{"repo_name": "pyre-check", "repo_creator": "facebook", "programming_language": "V", "code": "Require Import String Bool ZArith List.\nRequire Pyre.Value.\nRequire Pyre.Lvalue.\nRequire Pyre.Typ.\nRequire Pyre.Expression.\nRequire Pyre.Statement.\nRequire Import Pyre.Map.\n\nImport Pyre.Value.ListHelpers.\nImport Pyre.Typ.ListHelpers.\nImport Pyre.Expression.ListHelpers.\n\n(* begin hide *)\nDefinition evaluate_boolean_operator lexpr op rexpr :=\n    match op with \n    | Expression.And => andb lexpr rexpr\n    | Expression.Or => orb lexpr rexpr\nend.\n\n(* Helper to evaluate value membership *)\nFixpoint value_in (x lst:Value.t) : bool :=\n    match lst with \n    | Value.Sequence lst => List.existsb (fun y => Value.eqb x y) lst\n    | _ => false \n    end.\n\nDefinition evaluate_int_comparison_operator lexpr op rexpr: bool :=\n    match lexpr, rexpr with \n    | Value.Integer lexpr, Value.Integer rexpr =>\n            match op with \n            | Expression.GreaterThan => Z.gtb lexpr rexpr\n            | Expression.GreaterThanOrEquals => Z.geb lexpr rexpr\n            | Expression.LessThan => Z.ltb lexpr rexpr\n            | Expression.LessThanOrEquals => Z.leb lexpr rexpr\n            | _ => false \n            end \n    | _ , _ => false \nend.\n\nDefinition evaluate_comparison_operator lexpr op rexpr :=\n    match op with \n    | Expression.Equals => Value.eqb lexpr rexpr\n    | Expression.NotEquals => negb (Value.eqb lexpr rexpr)\n    | Expression.GreaterThan \n    | Expression.GreaterThanOrEquals\n    | Expression.LessThan\n    | Expression.LessThanOrEquals =>\n      evaluate_int_comparison_operator lexpr op rexpr\n    | Expression.In => value_in lexpr rexpr\n    | Expression.NotIn => negb (value_in lexpr rexpr)\n    | _ => (* TODO(T53097965): implement Is/IsNot *) false\n    end\n.\n\nDefinition evaluate_unary_operator op expr : option Value.t :=\n    match op, expr with \n    | Expression.Not, Value.Boolean b => Some (Value.Boolean (negb b))\n    | Expression.Invert, Value.Integer z => Some (Value.Integer (-z -1)%Z) \n    | Expression.Negative, Value.Integer z => Some (Value.Integer (- z)%Z)\n    | Expression.Positive, Value.Integer z => Some (Value.Integer z)\n    | _, _ => None\n    end.\n\nLemma evaluate_unary_int_operator : forall op z,\n  evaluate_unary_operator op (Value.Integer z) =\n    match op with \n    | Expression.Negative => Some (Value.Integer (-z)%Z)\n    | Expression.Positive => Some (Value.Integer z)\n    | Expression.Invert => Some (Value.Integer (-z -1)%Z)\n    | _ => None \n    end.\nProof.\nnow destruct op; intros z; simpl.\nQed.\n(* end hide *)\n\n(** Map from identifiers to values. Used during <<Expression.t>> evaluation *)\nDefinition EState := SMap.t Value.t.\nDefinition Empty : EState := SMap.empty _.\n\n(** * Evaluation of expressions\n  Evaluates the expression <<expr>> using the state <<now>>. Returns some\n  <<Value.t>> if everything went ok, or <<None>> otherwise.\n*)\nFixpoint eval (now: EState) (expr : Expression.t) : option Value.t :=\n    match expr with\n    | Expression.BooleanOperator lexpr op rexpr => \n            match (eval now lexpr, eval now rexpr) with\n            | (Some (Value.Boolean b0), Some (Value.Boolean b1)) =>\n                    Some (Value.Boolean (evaluate_boolean_operator b0 op b1))\n            | (_, _) => None\n            end\n    | Expression.ComparisonOperator lexpr op rexpr =>\n            match (eval now lexpr, eval now rexpr) with\n            | (Some vl, Some vr) =>\n               Some (Value.Boolean (evaluate_comparison_operator vl op vr))\n            | (_, _) => None\n            end\n    | Expression.False_ => Some (Value.Boolean false)\n    | Expression.Integer z => Some (Value.Integer z)\n    | Expression.List el =>\n            match eval_list now el with\n            | Some vl => Some (Value.Sequence vl)\n            | None => None\n            end\n    | Expression.Id id => SMap.find id now\n    | Expression.None => Some Value.None\n    | Expression.String s => Some (Value.String s)\n    | Expression.Ternary target test alternative =>\n            match eval now test with\n            | Some (Value.Boolean true) => eval now target\n            | Some (Value.Boolean false) => eval now alternative\n            | Some _ => None\n            | None => None\n            end\n    | Expression.True_ => Some (Value.Boolean true)\n    | Expression.Tuple el =>\n            match eval_list now el with\n            | Some vl => Some (Value.Sequence vl)\n            | None => None\n            end\n    | Expression.UnaryOperator op e =>\n            match eval now e with\n            | Some v => evaluate_unary_operator op v\n            | None => None\n            end\n    end\nwith eval_list (now: EState) (elist : Expression.tlist) :\n  option Value.tlist :=\n  match elist with\n  | Expression.Nil => Some (Value.Nil)\n  | Expression.Cons hd tl =>\n          match (eval now hd, eval_list now tl) with\n          | (Some hd, Some tl) => Some (Value.Cons hd tl)\n          | (_, _) => None\n          end\n  end\n.\n\nLemma eval_list_length: forall (state: EState)\n  (l: Expression.tlist) (vl: Value.tlist),\n  eval_list state l = Some vl -> List.length l = List.length vl.\nProof.\nintro now; induction l as [ | e es hi]; intros vs' h; simpl in *.\n- now injection h; clear h; intro h; subst.\n- case_eq (eval now e); [ intros v | ]; intros hv; rewrite hv in h.\n  + case_eq (eval_list now es); [ intros vs | ]; intros hvs; rewrite hvs in h.\n    * injection h; clear h; intro h; subst; simpl.\n      now rewrite (hi _ hvs).\n    * discriminate h.\n  + discriminate h.\nQed.\n\n(** Global state for the statement operational semantic. It is made of\nthe state for expression evaluation, along with information about know\nfunctions. *)\nDefinition State := @Map.State Value.t.\nDefinition EState_of_State (state : State) : EState := RawState state.\nCoercion EState_of_State : State >-> EState.\n\n(* Creates an empty state, keeping the function information around. It is\nused to create the initial state for a sub-function call. *)\nDefinition reset_local (now: State) : State := \n  mkState _ Empty (FuncState now).\n\nFixpoint prepare_call_state (now: EState)\n    (arguments: list Value.t)\n    (parameters: list (string * Typ.t)) : option EState :=\n    match (arguments, parameters) with\n    | (nil, nil) => Some now \n    | (v :: arguments, ((name, _) :: parameters)) =>\n        prepare_call_state (SMap.add name v now) arguments parameters\n    | (_, _) => None\nend.\n\nLemma prepare_call_state_length: forall now arguments parameters after,\n  prepare_call_state now arguments parameters = Some after ->\n  List.length arguments = List.length parameters.\nProof.\nintros now arguments; revert now.\ninduction arguments as [ | arg arguments hi];\n    intros now [ | [? name] parameters]\n    after h; simpl in *; try discriminate; [ reflexivity | ].\nnow rewrite (hi _ _ _ h).\nQed.\n\nLemma prepare_call_state_same_length: forall now arguments parameters,\n  List.length arguments = List.length parameters ->\n  exists after, prepare_call_state now arguments parameters = Some after.\nProof.\nintros now arguments; revert now.\ninduction arguments as [ | arg arguments hi]; intros now [ | [name ?] params]\n    hlen; simpl in *; try discriminate.\n- now exists now.\n- injection hlen; intros; subst; clear hlen.\n  eapply hi in H as [after h].\n  now exists after; exact h.\nQed.\n\n(** * Continuations\n\nType of continuation, to deal with the execution flow.\n- <<KStop>> means that there is nothing left to execute.\n- <<KSeq statement k>> is the sequence operator. When the current statement is\n  evaluated, continue the evaluation with <<statement>> and then with <<k>>.\n- <<KWhile test body orelse k>> means that we are currently evaluating\n  a while loop. The payload will drive what happens when we reach the end\n  of the loop or a control operator. Once the loop is done, continue with\n    <<k>>.\n- <<KCall state target k>> means that we are executing a\n  sub-routine/function. Before the call, the current state was <<state>>.\n  Once the call returns, the output value (if any) will be stored in\n  the <<target>> identifier (if any).\n  execution then resumes using the <<k>> continuation.\n*)\nInductive Cont :=\n  | KStop: Cont\n  | KSeq: Statement.t -> Cont -> Cont\n  | KWhile: forall (test: Expression.t) (body orelse: Statement.t) (k: Cont),\n          Cont\n  | KCall: forall (call_state: State)\n                  (target: option (Lvalue.t * Typ.t))\n                  (k: Cont),\n                  Cont\n.\n\n(** *  Single Step Semantic\n\n    <<sss s st k s' st' k'>> means that in the <<State>> <<s>>, the\n    statement <<st>> with contiuation <<k>> will\n    evaluation in the statement <<st'>> with continuation <<k'>>. As a\n    result the new evaluation <<State>> is <<s'>>.\n*)\nInductive sss: State -> Statement.t -> Cont ->\n               State -> Statement.t -> Cont -> Prop  :=\n    | sssAssign: forall (state: State) id annotation value k v,\n        eval state value = Some v ->\n        sss state (Statement.Assign (Lvalue.Id id) annotation value) k\n            (set state id v) Statement.Pass k\n    (* executing a function call yield a fresh new state (and the current\n       one is stored in the <<KCall>> continuation *)\n    | sssCallFun: forall (state: State) id annotation callee arguments func k\n        (vargs: Value.tlist) call_state,\n        get_info state callee = Some func ->\n        eval_list state (from_list (List.map snd arguments)) = Some vargs ->\n        prepare_call_state Empty vargs (parameters func) = Some call_state ->\n        sss\n          state\n          (Statement.Call (Some (id, annotation)) (Expression.Id callee) arguments)\n          k\n          (mkState _ call_state (FuncState state))\n          (body func)\n          (KCall state (Some (id, return_annotation func)) k)\n    (* executing a procedure call yield a fresh new state (and the current\n       one is stored in the <<KCall>> continuation *)\n    | sssCallProc: forall (state: State) callee arguments func k\n        (vargs: Value.tlist) call_state,\n        get_info state callee = Some func ->\n        eval_list state (from_list (List.map snd arguments)) = Some vargs ->\n        prepare_call_state Empty vargs (parameters func) = Some call_state ->\n        sss\n          state\n          (Statement.Call None (Expression.Id callee) arguments)\n          k\n          (mkState _ call_state (FuncState state))\n          (body func)\n          (KCall state None k)\n    | sssReturnFun: forall (state call_state: State) ret id annotation k vret,\n        eval state ret = Some vret ->\n        sss state (Statement.Return ret) (KCall call_state (Some (Lvalue.Id id, annotation)) k)\n          (set call_state id vret) Statement.Pass k\n    | sssReturnProc: forall (state call_state: State)ret k,\n        sss state (Statement.Return ret) (KCall call_state None k)\n            call_state Statement.Pass k\n    | sssReturnWhile: forall state test body orelse k ret,\n        sss state (Statement.Return ret) (KWhile test body orelse k)\n            state (Statement.Return ret) k\n    | sssReturnSeq: forall state st k ret,\n        sss state (Statement.Return ret) (KSeq st k)\n            state (Statement.Return ret) k\n    (* if some `Return` is spotted at toplevel (outside any function),\n       we transition to the standard \"exit\" state: Pass/KStop *)\n    | sssReturnStop: forall state ret,\n        sss state (Statement.Return ret) KStop\n            state Statement.Pass KStop\n    | sssPassProc: forall (state call_state: State) k,\n        sss state Statement.Pass (KCall call_state None k)\n            call_state Statement.Pass k\n    | sssExpression : forall (state: State) expr v k, \n            eval state expr = Some v ->\n            sss state (Statement.Expression expr) k state Statement.Pass k\n    | sssSeq: forall state st0 st1 k,\n            sss state (Statement.Seq st0 st1) k state st0 (KSeq st1 k)\n    | sssPassSeq: forall state st k,\n            sss state Statement.Pass (KSeq st k) state st k\n    | sssWhileTrue: forall (state: State) test body orelse k,\n            eval state test = Some (Value.Boolean true) ->\n            sss state (Statement.While test body orelse) k\n                state body (KWhile test body orelse k)\n    | sssWhileFalse: forall (state: State) test body orelse k,\n            eval state test = Some (Value.Boolean false) ->\n            sss state (Statement.While test body orelse) k\n                state orelse k\n    | sssPassWhileTrue: forall (state: State) test body orelse k,\n            eval state test = Some (Value.Boolean true) ->\n            sss state Statement.Pass (KWhile test body orelse k)\n                state body (KWhile test body orelse k)\n    | sssPassWhileFalse: forall (state: State) test body orelse k,\n            eval state test = Some (Value.Boolean false) ->\n            sss state Statement.Pass (KWhile test body orelse k)\n                state orelse k\n    | sssIfTrue: forall test body orelse (state: State) k,\n            eval state test = Some (Value.Boolean true) ->\n            sss state (Statement.If test body orelse) k\n                state body k\n    | sssIfFalse: forall test body orelse (state: State) k,\n            eval state test = Some (Value.Boolean false) ->\n            sss state (Statement.If test body orelse) k\n                state orelse k\n.\n\n(** Multi step version of sss *)\nInductive sssn: State -> Statement.t -> Cont ->\n               State -> Statement.t -> Cont -> Prop  :=\n | sss_refl: forall state st k, sssn state st k state st k\n | sss_trans: forall state st k state' st' k' state'' st'' k'',\n         sss state st k state' st' k' ->\n         sssn state' st' k' state'' st'' k'' ->\n         sssn state st k state'' st'' k''\n.\n\nHint Constructors sss sssn : core.\n\nLemma sssn_step: forall state st k state' st' k',\n  sss state st k state' st' k' ->\n  sssn state st k state' st' k'.\nProof.\nintros ? ? ? ? ? ?  h.\neapply sss_trans; [now apply h | now apply sss_refl ].\nQed.\n\nLemma sssn_trans: forall state st k state' st' k' state'' st'' k'',\n         sssn state st k state' st' k' ->\n         sssn state' st' k' state'' st'' k'' ->\n         sssn state st k state'' st'' k''.\nProof.\nintros  s st k s' st' k' s'' st'' k'' h; revert s'' st'' k''.\ninduction h as [ s st k | s st k s' st' k' s'' st'' k'' h hs hi];\n        intros z zt l;[  now idtac | ]; intro h''.\neapply sss_trans; [ now apply h | ].\nnow apply hi.\nQed.\n\n(* begin hide *)\nModule Test.\n(* Toy examples to convince myself that everything is correct *)\nDefinition XID : Lvalue.t  := Lvalue.Id \"x\"%string.\nDefinition YID : Lvalue.t  := Lvalue.Id \"y\"%string.\nDefinition X : Expression.t := Expression.Id \"x\"%string.\nDefinition Ret x := Statement.Return x.\n(* Identity function, named \"int_id\", from int to int *)\n\nDefinition int_id_parameters := (((\"x\"%string), Typ.Integer) :: nil).\n\nDefinition int_id : func := mkFun \"int_id\"%string \n  int_id_parameters\n  Typ.Integer\n  (Ret X).\n\nDefinition Int z : Expression.t := Expression.Integer z.\n\n(* Empty value state, with a single function defined: int_id *)\nDefinition test_state : State :=\n  mkState _ Empty (SMap.add \"int_id\"%string int_id (SMap.empty _)).\n(* Value state has a single binding: y |-> 42. Function information\n   is the same as test_state *)\nDefinition final_state : State := set test_state \"y\"%string (Value.Integer 42).\n\n(* Function call `y := int_id(42)` *)\nDefinition Prog :=\n    Statement.Call (Some (YID, Typ.Integer))\n      (Expression.Id \"int_id\"%string)\n      ((None, Int 42) :: nil).\n\n(* Proof that the program `Prog` executes correctly and updates the \n   initial environment `test_state` into `final_state`. *)\nLemma sss_int_id_42:\n  sssn test_state Prog KStop final_state Statement.Pass KStop.\nProof.\nunfold Prog.\neapply sss_trans.\n  apply sssCallFun with (vargs := (Value.Cons (Value.Integer 42) Value.Nil)). \n  unfold get_info, test_state; simpl.\n  apply SMap.find_1.\n  apply SMap.add_1; reflexivity.\n\n  simpl; now reflexivity.\n\n  simpl; now reflexivity.\n\nsimpl.\neapply sss_trans.\n  constructor.\n  simpl.\n  apply SMap.find_1.\n  apply SMap.add_1; reflexivity.\nnow apply sss_refl.\nQed.\n\n(* Function \"expect_int\" : int -> void *)\nDefinition expect_int : func := mkFun \"expect_int\"%string \n  int_id_parameters (* we use the same list of parameters *)\n  Typ.None\n  Statement.Pass.\n\n(* New test state: Empty value state and a single function definition:\n expect_int *)\nDefinition test_state2 : State :=\n  mkState _ Empty (SMap.add \"expect_int\"%string expect_int (SMap.empty _)).\n\n(* Function call `expect_int(1664)` *)\nDefinition Prog2 :=\n    Statement.Call None\n      (Expression.Id \"expect_int\"%string)\n      ((None, Int 1664) :: nil).\n\n(* Proof that the program `Prog2` executes correctly and do not modify its\n   initial environment `test_state2`. *)\nLemma sss_expect_int:\n  sssn test_state2 Prog2 KStop test_state2 Statement.Pass KStop.\nProof.\nunfold Prog2.\neapply sss_trans.\n  apply sssCallProc with (vargs := Value.Cons (Value.Integer 1664) Value.Nil).\n  apply SMap.find_1.\n  apply SMap.add_1; reflexivity.\n\n  simpl; now reflexivity.\n\n  simpl; now reflexivity.\nsimpl.\neapply sss_trans.\n  now constructor.\nnow apply sss_refl.\nQed.\n\nLemma WhileFalse: forall s body orelse k,\n    sssn s (Statement.While Expression.False_ body orelse) k s orelse k.\nProof.\nintros s body orelse k.\neapply sss_trans.\nnow apply sssWhileFalse.\nnow apply sss_refl.\nQed.\n\nEnd Test.\n(* end hide *)\n\n(** Single Step Semantic is a deterministic relation *)\nLemma sss_determinist: forall s0 st0 k0 s1 st1 k1 s2 st2 k2,\n    sss s0 st0 k0 s1 st1 k1 ->\n    sss s0 st0 k0 s2 st2 k2 ->\n    (s1 = s2 /\\ st1 = st2 /\\ k1 = k2).\nProof.\nintros s0 st0 k0 s1 st1 k1 s2 st2 k2 h; revert s2 st2 k2.\ndestruct h as [\n      s id annotation value k v hvalue\n    | s id annotation callee arguments func k vargs cstate hf heval hstate\n    | s callee arguments func k vargs cstate hf heval hstate\n    | s s' ret id annotation k vret heval\n    | s s' ret k\n    | s test body orelse k ret\n    | s st k ret\n    | s ret\n    | s s' k\n    | s expr v k heval\n    | s st0 st1 k \n    | s st k\n    | s test body orelse k\n    | s test body orelse k\n    | s test body orelse k\n    | s test body orelse k\n    | test body orelse s k heval\n    | test body orelse s k\n]; intros s2 st2  k2 h; try now inversion h.\n- inversion h; subst; clear h.\n  rewrite hvalue in H7; injection H7; intros; subst.\n  now split.\n- inversion h; subst; clear h. \n  rewrite hf in H8; injection H8; clear H8; intros; subst.\n  rewrite heval in H9; injection H9; clear H9; intros; subst.\n  now rewrite hstate in H10; injection H10; clear H10; intros; subst.\n- inversion h; subst; clear h. \n  rewrite hf in H1; injection H1; clear H1; intros; subst.\n  rewrite heval in H3; injection H3; clear H3; intros; subst.\n  now rewrite hstate in H8; injection H8; clear H8; intros; subst.\n- inversion h; subst; clear h. \n  now rewrite heval in H8; injection H8; intros; subst.\n- inversion h; subst; clear h; [now idtac | ].\n  now rewrite H in H8; discriminate H8.\n- inversion h; subst; clear h; [ | now idtac ].\n  now rewrite H in H8; discriminate H8.\n- inversion h; subst; clear h; [ now idtac | ].\n  now rewrite H in H8; injection H8; intros; subst.\n- inversion h; subst; clear h; [ | now  idtac].\n  now rewrite H in H8; injection H8; intros; subst.\n- inversion h; subst; clear h; [ now idtac | ].\n  now rewrite heval in H7; injection H7; intros; subst.\n- inversion h; subst; clear h; [ | now idtac ].\n  now rewrite H in H8; injection H8; intros; subst.\nQed.\n", "num_lines": 512}
{"repo_name": "pyre-check", "repo_creator": "facebook", "programming_language": "V", "code": "Require Import ZArith List String.\n\n(** * Operators *)\n(** Boolean operators *)\nInductive boolean_operator :=\n  | And\n  | Or\n.\n\n(** Comparison operators\n    Currently <<Is>> and <<IsNot>> are not supported\n*)\nInductive comparison_operator :=\n  | Equals\n  | GreaterThan\n  | GreaterThanOrEquals\n  | In\n  | Is\n  | IsNot\n  | LessThan\n  | LessThanOrEquals\n  | NotEquals\n  | NotIn\n.\n\n(** Unary operators *)\nInductive unary_operator :=\n  | Invert\n  | Negative\n  | Not\n  | Positive.\n\n(** * Expressions\n    More will be added later. See\n    https://github.com/facebook/pyre-check/blob/main/ast/expression.mli#L216\n*)\nInductive t: Set :=\n  | BooleanOperator: forall (left: t) (op: boolean_operator) (right: t), t\n  | ComparisonOperator: forall (left: t) (op: comparison_operator) (right: t), t\n  | False_: t\n  | Integer: Z -> t\n  | List: tlist -> t\n  | Id: string -> t\n  | None: t\n  | String: string -> t\n  | Ternary: forall (target: t) (test: t) (alternative: t), t\n  | True_: t\n  | Tuple: tlist -> t\n  | UnaryOperator: unary_operator -> t -> t\nwith tlist: Set :=\n  | Nil: tlist\n  | Cons: t -> tlist -> tlist\n.\n\n(* begin hide *)\nHint Constructors t tlist : core.\n\nScheme expr_ind' := Induction for t Sort Prop\n    with expr_list_ind' := Induction for tlist Sort Prop.\n\nCombined Scheme expression_ind from expr_ind', expr_list_ind'.\n\nModule ListHelpers.\nFixpoint to_list (l: tlist) : list t :=\n    match l with\n    | Nil => nil\n    | Cons hd tl => hd :: to_list tl\n    end.\n\nFixpoint from_list (l: list t) : tlist :=\n    match l with\n    | nil => Nil\n    | hd :: tl => Cons hd (from_list tl)\n    end.\n\nLemma to_list_cancel: forall (l: tlist), from_list (to_list l) = l.\nProof.\ninduction l as [ | hd tl hi]; simpl in *; [ now idtac | ].\nnow rewrite hi.\nQed.\n\nLemma from_list_cancel: forall (l: list t), to_list (from_list l) = l.\nProof.\ninduction l as [ | hd tl hi]; simpl in *; [ now idtac | ].\nnow rewrite hi.\nQed.\n\nCoercion to_list: tlist >-> list.\nEnd ListHelpers.\n(* end hide *)\n", "num_lines": 91}
{"repo_name": "pyre-check", "repo_creator": "facebook", "programming_language": "V", "code": "Require Import String.\n\n(** Lvalues\n    Currently we only support simple variables.\n*)\nInductive t : Set :=\n  | Id : string -> t\n.\n", "num_lines": 9}
{"repo_name": "pyre-check", "repo_creator": "facebook", "programming_language": "V", "code": "From Coq Require Import Structures.OrderedTypeEx.\nFrom Coq Require Import FMapList.\nFrom Coq Require Import String.\nFrom Pyre Require Typ Statement.\n\nModule SMap := FMapList.Make(String_as_OT).\n\n(** * Information about function definitions\n\nWe store in here all relevant information about known functions:\n- their <<name>>.\n- their signature, as a list of <<parameters>> and a <<return annotation>>.\n- the actual <<body>> statement of the function.\n*)\nRecord func : Set := mkFun {\n    (* TODO(T53097965): support dotted access for methods *)\n    name: string;\n    (* TODO(T53097965): support more parameter kinds *)\n    parameters: list (string * Typ.t);\n    (* decorators: Expression.t list; *)\n    return_annotation: Typ.t; (* no option, set to TNone if need be *)\n    (* async: bool; *)\n    (* parent: Reference.t option; (1* The class owning the method. *1) *)\n    body: Statement.t;\n}.\n\n(** Global state for the statement operational semantic. It is made of\nthe state for expression evaluation, along with information about know\nfunctions. *)\nRecord State {A: Set} := mkState {\n  RawState :> SMap.t A;\n  FuncState : SMap.t func \n}.\n\nDefinition set {A: Set} (state: @State A) (id: string) (v: A) :=\n  mkState _ (SMap.add id v state) (FuncState state).\n\nDefinition remove {A: Set} (state : @State A) (id: string) : @State A :=\n  mkState _ (SMap.remove id state) (FuncState state).\n\n\nDefinition get_info {A: Set} (state: @State A) (fun_name: string) : option func :=\n  SMap.find fun_name (FuncState state).\n\nFrom Coq Require Import FMapFacts.\n\nModule SMapFacts := WFacts (SMap).\n\nLemma find_add_smap: forall {A: Set} (state : SMap.t A) (x y: string) (v : A),\n  SMap.find y (SMap.add x v state) =\n  if (y =? x)%string then Some v else SMap.find y state.\nProof.\nintros A state x y v.\ncase_eq (String.eqb y x); intro hyx.\n- apply SMapFacts.add_eq_o.\n  apply String.eqb_eq in hyx; rewrite hyx; reflexivity.\n- apply SMapFacts.add_neq_o.\n  apply String.eqb_neq in hyx.\n  firstorder.\nQed.\n\nLemma find_add: forall {A: Set} (state : @State A) (x y: string) (v : A),\n  SMap.find y (set state x v) =\n  if (y =? x)%string then Some v else SMap.find y state.\nProof.\nintros A state x y v.\nunfold set; simpl.\nrewrite find_add_smap.\nreflexivity.\nQed.\n\nLemma find_remove_smap: forall {A : Set} (state: @SMap.t A) (x z: string),\n  SMap.find z (SMap.remove x state) =\n  if (z =? x)%string then None else SMap.find z state.\nProof.\nintros A state x z.\ncase_eq (String.eqb z x); intro hzx.\n- apply SMapFacts.remove_eq_o.\n  apply String.eqb_eq in hzx; rewrite hzx; reflexivity.\n- apply SMapFacts.remove_neq_o.\n  apply String.eqb_neq in hzx.\n  firstorder.\nQed.\n", "num_lines": 84}
{"repo_name": "pyre-check", "repo_creator": "facebook", "programming_language": "V", "code": "Require Import List ZArith String.\nRequire Pyre.Lvalue.\nRequire Pyre.Value.\nRequire Pyre.Expression.\nRequire Import Pyre.Eval.\nRequire Pyre.Statement.\nRequire Pyre.Typ.\nRequire Import Pyre.Map.\n\nImport Pyre.Value.ListHelpers.\nImport Pyre.Typ.ListHelpers.\nImport Pyre.Expression.ListHelpers.\n\n(** * Typing judgements *)\n\n(** Typing context (Map from identifiers to types).\n    The bool parameter is only used in the typing of\n    Statement.t \n*)\nDefinition TContext := SMap.t (bool * Typ.t).\nDefinition Empty : TContext := SMap.empty _.\nSection TypingExpression.\n\nImport Pyre.Expression.\n\n(** Typing judgement for expressions *)\nInductive ok : TContext -> Expression.t -> Typ.t -> Prop :=\n  | typFalse: forall context, ok context False_ Typ.Boolean\n  | typTrue: forall context, ok context True_ Typ.Boolean\n  | typInteger: forall context z, ok context (Integer z) Typ.Integer\n  | typString: forall context str, ok context (String str) Typ.String\n  | typNone: forall  context,  ok context None Typ.None\n  | tyBop: forall context b0 b1 op,\n          ok context b0 Typ.Boolean ->\n          ok context b1 Typ.Boolean ->\n          ok context (BooleanOperator b0 op b1) Typ.Boolean\n  | tyCmp: forall context e0 e1 op,\n          ok context e0 Typ.Integer ->\n          ok context e1 Typ.Integer ->\n          ok context (ComparisonOperator e0 op e1) Typ.Boolean\n  | TyList: forall context (l: Expression.tlist) ty,\n          ok_list context l ty -> \n          ok context (List l) (Typ.List ty)\n  | TyTuple: forall context (l: Expression.tlist) lty,\n          ok_tuple context l lty ->\n          ok context (Tuple l) (Typ.Tuple lty)\n  | TyNot: forall context expr,\n          ok context expr Typ.Boolean ->\n          ok context (UnaryOperator Not expr) Typ.Boolean\n  | TyUnary: forall context expr op,\n         op <> Not -> \n         ok context expr Typ.Integer ->\n         ok context (UnaryOperator op expr) Typ.Integer\n  | TyTernary : forall context target test alternative typ,\n          ok context target typ ->\n          ok context alternative typ ->\n          ok context test Typ.Boolean ->\n          ok context (Ternary target test alternative) typ\n  | TyId: forall context id b T,\n          SMap.find id context = Some (b, T) ->\n          ok context (Id id) T\nwith ok_list: TContext -> Expression.tlist -> Typ.t -> Prop :=\n  | tyListNil : forall context typ, ok_list context Nil typ\n  | tyListCons : forall context hd tl typ,\n          ok context hd typ ->\n          ok_list context tl typ ->\n          ok_list context (Cons hd tl) typ\nwith ok_tuple : TContext -> Expression.tlist -> Typ.tlist -> Prop :=\n  | tyTupleSingl : forall context expr typ,\n          ok context expr typ ->\n          ok_tuple context (Cons expr Nil) (Typ.Cons typ Typ.Nil)\n  | tyTupleCons : forall context expr le typ lt,\n          ok context expr typ ->\n          ok_tuple context le lt ->\n          ok_tuple context (Cons expr le) (Typ.Cons typ lt)\n.\n\n(* begin hide *)\nScheme ok_ind' := Induction for ok Sort Prop\n  with ok_list_ind' := Induction for ok_list Sort Prop\n  with ok_tuple_ind' := Induction for ok_tuple Sort Prop.\n\nCombined Scheme ok_induc from ok_ind', ok_list_ind', ok_tuple_ind'.\n\nLemma ok_tuple_len: forall context le lt,\n    ok_tuple context le lt -> List.length le = List.length lt.\nProof.\nintro context.\ninduction 1; simpl in *; now intuition.\nQed.\n\nLemma ok_tuple_len_pos : forall context le lt,\n    ok_tuple context le lt -> List.length le > 0.\nProof.\nintro context.\ninduction 1; simpl in *; now intuition.\nQed.\n\nLemma ok_list_spec: forall context l typ,\n    ok_list context l typ -> Forall (fun expr => ok context expr typ) l.\nProof.\ninduction 1 as [ context typ | context hd tl typ h0 h1 hi ];\n    [ now apply Forall_nil | ].\nnow apply Forall_cons.\nQed.\n\nLemma ok_list_forall: forall context (l: Expression.tlist) typ,\n    Forall (fun expr => ok context expr typ) l -> ok_list context l typ.\nProof.\nintro context.\ninduction l as [ | hd tl hi]; intros typ h; inversion h; subst; clear h.\n- now constructor.\n- apply hi in H2.\n  now constructor.\nQed.\n\nLemma ok_tuple_spec: forall context l lt, ok_tuple context l lt ->\n    List.length l > 0 /\\\n    List.length l = List.length lt /\\\n    Forall (fun et => ok context (fst et) (snd et)) (List.combine l lt).\nProof.\ninduction 1 as [context expr typ h | context expr typ es et h hs hi ].\n- intuition.\n  now apply Forall_cons.\n- now simpl; intuition.\nQed.\n\nLemma ok_tuple_forall: forall context (l: Expression.tlist) (lt: Typ.tlist),\n    List.length l > 0 ->\n    List.length l = List.length lt ->\n    Forall (fun et => ok context (fst et) (snd et)) (List.combine l lt) ->\n    ok_tuple context l lt.\nProof.\ninduction l as [ | hd tl hi];\n       intros lt hp hl h; inversion h; subst; clear h; simpl in *.\n- now idtac.\n- destruct lt as [ | typ typs]; [now idtac | ]. \n  simpl in H0.\n  discriminate H0.\n- destruct x as [v' t']; simpl in *.\n  destruct lt as [ | typ typs]; [now idtac | ]. \n  injection hl; clear hl; intro hl.\n  simpl in H; injection H; clear H; intros heq0 heq1; subst.\n  (* special case for list of size 1 *)\n  case_eq tl.\n  + intros ? h; subst.\n    simpl in hl.\n    destruct typs as [ | ]; [ | now idtac].\n    now constructor.\n  + intros ? ? htl ?; subst.\n    constructor; [ now idtac | ].\n    now apply hi; simpl; intuition.\nQed.\n\nLemma ok_tuple_forall2: forall context (l: Expression.tlist) (lt: Typ.tlist),\n    List.length lt > 0 ->\n    List.length l = List.length lt ->\n    Forall (fun et => ok context (fst et) (snd et)) (List.combine l lt) ->\n    ok_tuple context l lt. \nProof.\nintros context l lt h heq hf.\nnow apply ok_tuple_forall; intuition.\nQed.\n(* end hide *)\n\nEnd TypingExpression.\n\nHint Constructors ok ok_list ok_tuple : core.\n\nSection TypingValue.\n\nImport Value.\n\n(** Typing judgement for values *)\nInductive okv : Value.t -> Typ.t -> Prop :=\n  | TyVBoolean: forall b, okv (Boolean b) Typ.Boolean\n  | TyVInteger: forall i, okv (Integer i) Typ.Integer\n  | TyVString: forall str, okv (String str) Typ.String\n  | TyVList: forall (l: Value.tlist) T,\n          okv_list l T ->\n          okv (Sequence l) (Typ.List T)\n  | TyVTuple: forall (l: Value.tlist) (lt: Typ.tlist),\n          okv_tuple l lt ->\n          okv (Sequence l) (Typ.Tuple lt)\n  | TyNone: okv Value.None Typ.None\nwith okv_list: Value.tlist -> Typ.t -> Prop :=\n  | TyVNil: forall typ, okv_list Nil typ\n  | TyVCons: forall hd tl typ,\n          okv hd typ ->\n          okv_list tl typ ->\n          okv_list (Cons hd tl) typ\nwith okv_tuple: Value.tlist -> Typ.tlist -> Prop :=\n  | TyVSingle: forall expr typ,\n          okv expr typ ->\n          okv_tuple (Cons expr Nil) (Typ.Cons typ Typ.Nil)\n  | TyVTuples: forall expr typ es typs,\n          okv expr typ ->\n          okv_tuple es typs ->\n          okv_tuple (Cons expr es) (Typ.Cons typ typs)\n.\n\n(* begin hide *)\nLemma okv_list_spec: forall lv typ, okv_list lv typ ->\n    Forall (fun v => okv v typ) lv.\nProof.\ninduction 1 as [ | hd tl typ h0 h1 hi ]; [ now apply Forall_nil | ].\nnow apply Forall_cons.\nQed.\n\nLemma okv_list_forall: forall (lv: Value.tlist) typ,\n    Forall (fun v => okv v typ) lv -> okv_list lv typ.\nProof.\ninduction lv as [ | hd tl hi]; intros typ h; inversion h; subst; clear h.\n- now constructor.\n- apply hi in H2.\n  now constructor.\nQed.\n\nLemma okv_tuple_spec: forall lv lt, okv_tuple lv lt ->\n    List.length lv > 0 /\\\n    List.length lv = List.length lt /\\\n    Forall (fun vt => okv (fst vt) (snd vt)) (List.combine lv lt).\nProof.\ninduction 1 as [ expr typ h | expr typ es et h hs hi ].\n- intuition.\n  now apply Forall_cons.\n- now simpl; intuition.\nQed.\n\nLemma okv_tuple_forall: forall (lv: Value.tlist) (lt: Typ.tlist),\n    List.length lv > 0 ->\n    List.length lv = List.length lt ->\n    Forall (fun vt => okv (fst vt) (snd vt)) (List.combine lv lt) ->\n    okv_tuple lv lt.\nProof.\ninduction lv as [ | hd tl hi];\n       intros lt hp hl h; inversion h; subst; clear h; simpl in *.\n- now idtac.\n- destruct lt as [ | typ typs]; [now idtac | ]. \n  simpl in H0.\n  discriminate H0.\n- destruct x as [v' t']; simpl in *.\n  destruct lt as [ | typ typs]; [now idtac | ]. \n  injection hl; clear hl; intro hl.\n  simpl in H; injection H; clear H; intros heq0 heq1; subst.\n  (* special case for list of size 1 *)\n  case_eq tl.\n  + intros ? h; subst.\n    simpl in hl.\n    destruct typs as [ | ]; [ | now idtac].\n    now constructor.\n  + intros ? ? htl ?; subst.\n    constructor; [ now idtac | ].\n    now apply hi; simpl; intuition.\nQed.\n\nLemma okv_tuple_forall2: forall (lv: Value.tlist) (lt: Typ.tlist),\n    List.length lt > 0 ->\n    List.length lv = List.length lt ->\n    Forall (fun vt => okv (fst vt) (snd vt)) (List.combine lv lt) ->\n    okv_tuple lv lt.\nProof.\nintros lv lt h heq hf.\nnow apply okv_tuple_forall; intuition.\nQed.\n(* end hide *)\n\nEnd TypingValue.\n\nHint Constructors okv okv_list okv_tuple : core.\n\n(** Well-formed <<EState>> w.r.t. some <<TContext>>:\n    for any typed variable in the context, there must be a value of the\n    right type associated to in the the state. *)\nDefinition well_formed_estate (state : EState) (context: TContext) : Prop :=\n    (forall k b T, SMap.find k context = Some (b, T) ->\n     exists v, SMap.find k state = Some v /\\ okv v T)\n.\n\n(* begin hide *)\nLemma well_formed_estate_get: forall state context,\n  well_formed_estate state context ->\n  forall id b T, SMap.find id context = Some (b, T) ->\n  exists v, SMap.find id state = Some v /\\ okv v T.\nProof.\nintros s context hwf k T.\nnow apply hwf.\nQed.\n\nLemma ty_bool_int : forall context expr typ, ok context expr typ ->\n    forall state, well_formed_estate state context ->\n    (typ = Typ.Boolean -> exists b, eval state expr = Some (Value.Boolean b)) /\\\n    (typ = Typ.Integer -> exists z, eval state expr = Some (Value.Integer z)).\nProof.\ninduction 1 as [\n    | context\n    | context z\n    | context str\n    | context\n    | context left right op hl hil hr hir\n    | context left right op hl hil hr hir\n    | context l typ hl\n    | context l typs hl\n    | context expr he hie\n    | context expr op hop he hie\n    | context target test alterntaive typ htarget hitarget\n            halt hialt htest hitest\n    | context id b T h\n]; intros state hwf; subst; split; intro heq; subst;\n   try discriminate; simpl in *.\n+ now exists false.\n+ now exists true.\n+ now exists z.\n+ destruct (hil state hwf) as [h0 _].\n  destruct (hir state hwf) as [h1 _].\n  destruct (h0 refl_equal) as [x0 hx0].\n  destruct (h1 refl_equal) as [x1 hx1].\n  rewrite hx0, hx1.\n  now exists (evaluate_boolean_operator x0 op x1).\n+ destruct (hil state hwf) as [_ h0].\n  destruct (hir state hwf) as [_ h1].\n  destruct (h0 refl_equal) as [x0 hx0].\n  destruct (h1 refl_equal) as [x1 hx1].\n  rewrite hx0, hx1.\n  now exists (evaluate_comparison_operator (Value.Integer x0) op (Value.Integer x1)).\n+ destruct (hie state hwf) as [h0 _]. \n  destruct (h0 refl_equal) as [ x0 hx0 ].\n  rewrite hx0.\n  now exists (negb x0).\n+ destruct (hie state hwf) as [_ h0].\n  destruct (h0 refl_equal) as [ x0 hx0 ].\n  rewrite hx0; simpl.\n  rewrite evaluate_unary_int_operator; destruct op; try (now elim hop).\n  * now exists (-x0 -1)%Z.\n  * now exists ( - x0 )%Z.\n  * now exists x0.\n+ destruct (hitarget state hwf) as [h0 _].\n  destruct (hialt state hwf) as [h1 _].\n  destruct (hitest state hwf) as [h2 _].\n  destruct (h0 refl_equal) as [x0 hx0].\n  destruct (h1 refl_equal) as [x1 hx1].\n  destruct (h2 refl_equal) as [x2 hx2].\n  rewrite hx2; destruct x2. \n  * rewrite hx0.\n    now exists x0.\n  * rewrite hx1.\n    now exists x1.\n+ destruct (hitarget state hwf) as [_ h0].\n  destruct (hialt state hwf) as [_ h1].\n  destruct (hitest state hwf) as [h2 _].\n  destruct (h0 refl_equal) as [x0 hx0].\n  destruct (h1 refl_equal) as [x1 hx1].\n  destruct (h2 refl_equal) as [x2 hx2].\n  rewrite hx2; destruct x2. \n  * rewrite hx0.\n    now exists x0.\n  * rewrite hx1.\n    now exists x1.\n+ apply well_formed_estate_get with (state := state) in h; [ | now idtac ].\n  destruct h as [ v [-> hv]].\n  inversion hv; subst; clear hv.\n  now exists b0.\n+ apply well_formed_estate_get with (state := state) in h; [ | now idtac ].\n  destruct h as [ v [-> hv]].\n  inversion hv; subst; clear hv.\n  now exists i.\nQed.\n(* end hide *)\n\n(** Every expression typed as <<Typ.Boolean>> must  be an actual <<bool>> *)\nLemma ty_bool : forall context expr, ok context expr Typ.Boolean ->\n    forall state, well_formed_estate state context ->\n    exists b, eval state expr = Some (Value.Boolean b).\nProof.\nintros context expr h s hwf; eapply ty_bool_int in h as [ h0 _].\n- now apply h0.\n- now apply hwf.\nQed.\n\n(** Every expression typed as <<Typ.Integer>> must  be an actual <<Z>> *)\nLemma ty_int : forall context expr, ok context expr Typ.Integer ->\n    forall state, well_formed_estate state context ->\n    exists z, eval state expr = Some (Value.Integer z).\nProof.\nintros context expr h s hwf; eapply ty_bool_int in h as [ _ h0].\n- now apply h0.\n- now apply hwf.\nQed.\n\n(* begin hide *)\nLemma ty_string_ : forall context expr typ, ok context expr typ -> \n    typ = Typ.String ->\n    forall state, well_formed_estate state context ->\n    exists str, eval state expr = Some (Value.String str).\nProof.\ninduction 1 as [\n    | context\n    | context z\n    | context str\n    | context\n    | context left right op hl hil hr hir\n    | context left right op hl hil hr hir\n    | context l typ hl\n    | context l typs hl\n    | context expr he hie\n    | context expr op hop he hie\n    | context target test alterntaive typ htarget hitarget\n            halt hialt htest hitest\n    | context id b T h\n] ; intros heq state hwf; subst; try discriminate; simpl in *.\n- now exists str.\n- apply ty_bool with (state := state) in htest as [ b hb ];[ | now idtac ].\n  rewrite hb.\n  destruct (hitarget refl_equal state hwf) as [s1 hs1].\n  destruct (hialt refl_equal state hwf) as [s2 hs2].\n  rewrite hs1, hs2.\n  destruct b.\n  + now exists s1.\n  + now exists s2.\n- apply well_formed_estate_get with (state := state) in h; [ | now idtac].\n  destruct h as [v [-> hv]].\n  inversion hv; subst; clear hv.\n  now exists str.\nQed.\n(* end hide *)\n\n(** Every expression typed as <<Typ.String>> must  be an actual <<string>> *)\nLemma ty_string : forall context expr, ok context expr Typ.String ->\n    forall state, well_formed_estate state context ->\n    exists str, eval state expr = Some (Value.String str).\nProof.\nintros context expr h state hwf.\nnow apply ty_string_ with (context := context) (state := state) in h.\nQed.\n\n(* begin hide *)\nLemma ty_none_: forall context expr typ, ok context expr typ ->\n    typ = Typ.None -> forall state, well_formed_estate state context ->\n    eval state expr = Some Value.None.\nProof.\ninduction 1 as [\n    | context\n    | context z\n    | context str\n    | context\n    | context left right op hl hil hr hir\n    | context left right op hl hil hr hir\n    | context l typ hl\n    | context l typs hl\n    | context expr he hie\n    | context expr op hop he hie\n    | context target test alterntaive typ htarget hitarget\n            halt hialt htest hitest\n    | context id b T h\n] ; intros heq state hwf; subst; try discriminate; simpl in *.\n- reflexivity.\n- apply ty_bool with (state := state) in htest as [ b hb ];[ | now idtac ].\n  rewrite hb.\n  rewrite (hitarget refl_equal state hwf).\n  rewrite (hialt refl_equal state hwf).\n  now destruct b.\n- apply well_formed_estate_get with (state := state) in h; [ | now idtac].\n  destruct h as [v [-> hv]].\n  inversion hv; subst; clear hv.\n  reflexivity.\nQed.\n(* end hide *)\n\n(** Every expression typed as <<Typ.None>>  must be <<None>> *)\nLemma ty_none: forall context expr, ok context expr Typ.None ->\n    forall state, well_formed_estate state context ->\n    eval state expr = Some Value.None.\nProof.\nintros  context expr h state hwf.\nnow apply ty_none_ with (context := context) (state := state) in h.\nQed.\n\nDefinition is_sequence (typ : Typ.t) : option Typ.t :=\n    match typ with\n    | Typ.List T => Some T\n    | _ => None\n    end.\n\nDefinition is_tuple (typ : Typ.t) : list Typ.t :=\n    match typ with\n    | Typ.Tuple l => l\n    | _ => nil\nend.\n\nSection TypingStatement.\n\nImport Pyre.Statement.\n\n(* TODO(T53097965):\n   use the strings in a correct way. For the moment they are totally\n   discarded and I consider that the order of arguments matches the\n   the order of parameters: we only consider positional arguments.\n *)\n\n(** Takes a list of arguments and a list of function parameter definitions \n    and (pairwise) checks that expressions are typed with the corresponding type, \n    in context <<context>>. *)\nFixpoint check_arguments context (arguments: list (option string * Expression.t))\n    (parameters: list (string * Typ.t)) : Prop :=\n    match (arguments, parameters) with\n    | ((_, arg) :: arguments, (_, ty) :: parameters) =>\n            ok context arg ty /\\ check_arguments context arguments parameters\n    | (nil, nil) => True\n    | _ => False\n    end.\n\nLemma check_arguments_length: forall context arguments parameters,\n  check_arguments context arguments parameters ->\n  List.length arguments = List.length parameters.\nProof.\nintro context; induction arguments as [| [ ? arg] arguments hi];\n    intros [| [name ?] parameters] h; simpl in *; try now elim h.\ndestruct h as [hok hc].\nnow rewrite (hi _ hc).\nQed.\n\n(** Helper to prepare the typing context of sub-routine/function calls *)\nFixpoint prepare_call_context (now: TContext)\n    (parameters: list (string * Typ.t)) : TContext :=\n    match parameters with\n    | nil => now\n    | (name, ty) :: parameters =>\n        prepare_call_context (SMap.add name (true, ty) now) parameters\nend.\n\n(** General context for type checking statements: it is made of an expression\n    typing context and some information about declared function *)\nDefinition Context := @Map.State (bool * Typ.t).\nDefinition TContext_of_Context (context : Context) : TContext := RawState context.\nCoercion TContext_of_Context : Context >-> TContext.\n\nDefinition mkContext context info : Context :=\n  mkState _ context info.\n\n(** Typing judgement for statements\n\n    <<typ C0 T st C1 >> means that in the typing context <<C0>>, evaluating the\n    statement <<st>> will generate the context <<C1>>.\n    <<T>> is the current expected return type (or None in case of procedure /\n    global statement).\n*)\nInductive typ : Context -> Typ.t -> Statement.t -> Context -> Prop :=\n  | typAssignIdNone: forall (context: Context) return_type id value T,\n      SMap.find id context = None ->\n      ok context value T ->\n      typ context return_type\n      (Assign (Lvalue.Id id) None value) (set context id (false, T))\n  | typAssignIdNoneWeak: forall (context: Context) return_type id value T Tid,\n      SMap.find id context = Some (false, Tid) ->\n      ok context value T ->\n      typ context return_type\n      (Assign (Lvalue.Id id) None value) (set context id (false, T))\n  | typAssignIdNoneStrong: forall (context: Context) return_type id value T,\n      SMap.find id context = Some (true, T) ->\n      ok context value T ->\n      typ context return_type\n      (Assign (Lvalue.Id id) None value) (set context id (true, T))\n  | typAssignIdAnnot: forall (context: Context) return_type id value T,\n      ok context value T ->\n      typ context return_type\n      (Assign (Lvalue.Id id) (Some T) value) (set context id (true, T))\n  | typExpression: forall (context: Context) return_type expr T,\n      ok context expr T ->\n      typ context return_type (Expression expr) context\n  | typIf: forall (context context': Context) return_type test body orelse,\n      ok context test Typ.Boolean ->\n      typ context return_type body context' ->\n      typ context return_type orelse context' ->\n      typ context return_type (If test body orelse) context'\n  | tyPass: forall (context: Context) return_type,\n      typ context return_type Pass context\n  | tySeq: forall (context context' context'': Context) return_type st next,\n      typ context return_type st context' ->\n      typ context' return_type next context'' ->\n      typ context return_type (Seq st next) context''\n  | typWhile: forall (context context': Context) return_type test body orelse,\n      ok context test Typ.Boolean ->\n      typ context return_type body context ->\n      typ context return_type orelse context' ->\n      typ context return_type (While test body orelse) context'\n  | typCallFun: forall (context: Context) return_type target annotation\n      function_name arguments function_def,\n      get_info context function_name = Some function_def ->\n      return_annotation function_def = annotation ->\n      check_arguments context arguments (parameters function_def) ->\n      typ\n        context\n        return_type\n        (Call (Some (Lvalue.Id target, annotation)) (Expression.Id function_name) arguments)\n        (set context target (true, return_annotation function_def))\n  | typCallProc: forall (context: Context) return_type function_name arguments\n      function_def,\n      get_info context function_name = Some function_def ->\n      return_annotation function_def = Typ.None ->\n      check_arguments context arguments (parameters function_def) ->\n      typ context return_type (Call None (Expression.Id function_name) arguments) context\n  | typReturn: forall (context context': Context) ret T,\n          ok context ret T ->\n          typ context T (Return ret) context'\n.\n\n(** Well-formed conditions for function definition: <<function_info>> is a\n    set of defined functions. In this context, a function <<f>> is\n    well-formed if its body is correctly typed w.r.t.  its arguments types\n    and return annotation. *)\nDefinition well_formed_function function_info (f: func) : Prop :=\n  (exists return_context,\n    typ (mkContext (prepare_call_context Empty (parameters f)) function_info)\n        (return_annotation f)\n        (body f) return_context)\n.\n\n(** General well-formed statement for State/Context:\n    - The underlying evaluation state / typing context must be well-formed.\n    - They must store the same information about function definitions.\n    - Every function definition recorded so far must be well-formed.\n*)\nDefinition well_formed (state: Eval.State) (context: Context) : Prop :=\n    (* underlying states are coherent *)\n    well_formed_estate state context /\\\n    (* same function definitions in both context *)\n    (FuncState state = FuncState context) /\\\n    (* functions are correctly typed *)\n    (forall function_name function_def,\n      get_info context function_name = Some function_def ->\n      well_formed_function (FuncState context) function_def)\n.\n\n(* begin hide *)\nLemma well_formed_get: forall state context, well_formed state context ->\n    forall id b T, SMap.find id context = Some (b, T) ->\n    exists v, SMap.find id state = Some v /\\ okv v T.\nProof.\nintros [s ?] [context ?] [hwf ?] k T h; simpl in *.\nnow apply hwf.\nQed.\n\nLemma well_formed_info_eq: forall state context, well_formed state context ->\n  FuncState state = FuncState context.\nProof.\nintros s context h; now apply h.\nQed.\n\nLemma well_formed_function_get: forall state context,\n  well_formed state context ->\n  forall function_name function_def,\n  get_info context function_name = Some function_def ->\n  well_formed_function (FuncState context) function_def.\nProof.\nintros s context h f func hg; now apply h in hg.\nQed.\n\nLemma well_formed_get_info: forall state context,\n  well_formed state context ->\n  forall function_name,\n  get_info context function_name = get_info state function_name.\nProof.\nintros s context [? [h ?]] f; unfold get_info.\nnow rewrite h.\nQed.\n\nLemma well_formed_function_get_alt: forall state context,\n  well_formed state context ->\n  forall function_name function_def,\n  get_info state function_name = Some function_def ->\n  well_formed_function (FuncState state) function_def.\nProof.\nintros s context h f  func hg.\nrewrite (well_formed_info_eq _ _ h).\napply well_formed_function_get with s f; intuition.\nnow rewrite well_formed_get_info with (state := s).\nQed.\n(* end hide *)\n\n(** Typing judgement for continuations\n\n    <<ktyp C0 T k>> encodes the fact that continuation <<k>> will correctly\n    execute under the context <<C0>>. The type <<T>> is the current return\n    type, or Typ.None if a procedure or a global statement is involved.\n*)\nInductive ktyp : Context -> Typ.t -> Cont -> Prop :=\n    | ktypKStop : forall context return_type,\n        ktyp context return_type KStop\n    | ktypSeq: forall context context' return_type st k,\n        typ context return_type st context' ->\n        ktyp context' return_type k -> \n        ktyp context return_type (KSeq st k)\n    | ktypKWhile: forall (context context': Context) return_type test\n        body orelse k,\n        ok context test Typ.Boolean ->\n        typ context return_type body context ->\n        typ context return_type orelse context' ->\n        ktyp context' return_type k ->\n        ktyp context return_type (KWhile test body orelse k)\n    | ktypKCallProc: forall context call_context return_type saved_state k,\n        well_formed saved_state call_context ->\n        ktyp call_context return_type k ->\n        ktyp context Typ.None (KCall saved_state None k)\n    | ktypKCallFun: forall context call_context return_type saved_state target\n        annotation k,\n        well_formed saved_state (remove call_context target) ->\n        SMap.find target call_context = Some (true, annotation) ->\n        ktyp call_context return_type k ->\n        ktyp context annotation (KCall saved_state (Some (Lvalue.Id target, annotation)) k)\n.\n\nEnd TypingStatement.\n\nHint Constructors typ ktyp : core.\n\n(** * Type soundness\n\n    Proof that a correctly typed expression always evaluate to a value,\n    and this value has the same type as the input expression.\n*)\n\nLemma eval_ok_ :\n    (forall context expr typ, ok context expr typ ->\n        forall state, well_formed_estate state context ->\n        exists v, eval state expr = Some v /\\  okv v typ) /\\\n    (forall context le typ, ok_list context le typ ->\n        forall state, well_formed_estate state context ->\n        exists lv, eval_list state le = Some lv /\\\n        okv_list lv typ) /\\\n    (forall context le lt, ok_tuple context le lt ->\n        forall state, well_formed_estate state context ->\n        exists lv, eval_list state le = Some lv /\\ okv_tuple lv lt).\nProof.\napply ok_induc.\n(* ok *)\n- intros context state hwf; subst; exists (Value.Boolean false); now split.\n- intros context state hwf; subst; exists (Value.Boolean true); now split.\n- intros context z state hwf; subst; exists (Value.Integer z); now split.\n- intros context str state hwf; subst; exists (Value.String str); now split.\n- intros context state hwf; subst; exists Value.None; now split.\n- intros context b0 b1 op h0 ? h1 ? state hwf; simpl; subst.\n  apply ty_bool with (state := state) in h0; [ | now idtac].\n  destruct h0 as [vb0 ->].\n  apply ty_bool with (state := state) in h1; [ | now idtac ].\n  destruct h1 as [vb1 ->].\n  now eexists; split; [ reflexivity | idtac].\n- intros context e0 e1 op h0 ? h1 ? state hwf; simpl; subst.\n  apply ty_int with (state := state) in h0; [ | now idtac ].\n  destruct h0 as [v0 ->].\n  apply ty_int with (state := state) in h1; [ | now idtac ].\n  destruct h1 as [v1 ->].\n  now eexists; split; [ reflexivity | idtac].\n- intros context l ty h hi state hwf; simpl.\n  destruct (hi _ hwf) as  [vl [-> h0]].\n  now eexists; split; [reflexivity  | constructor ].\n- intros context l ty h hi state hwf; simpl.\n  destruct (hi _ hwf) as  [vl [-> h0]].\n  now eexists; split; [reflexivity  | constructor ].\n- intros context expr h hi state hwf; simpl.\n  apply ty_bool with (state := state) in h as [v ->]; [ | now idtac ].\n  now eexists; split; [reflexivity | ].\n- intros context expr op hop h hi state hwf; simpl.\n  apply ty_int with (state := state) in h as [v ->]; [ | now idtac ].\n  rewrite evaluate_unary_int_operator.\n  destruct op; try (now elim hop); now eexists; split; [reflexivity | ].\n- intros context target test alt typ htarget hitarget halt hialt htest hitest\n    state hwf; simpl.\n  apply ty_bool with (state := state) in htest as [b ->]; [ | now idtac ].\n  destruct (hitarget _ hwf) as [vt [-> hvt]].\n  destruct (hialt _ hwf) as [va [-> hva]].\n  now destruct b; eexists; split; [ reflexivity | | reflexivity | ].\n- intros context id b typ hg state hwf; simpl.\n  now apply well_formed_estate_get with (context := context) (b := b);\n    [ now apply hwf | ].\n(* ok_list *)\n- intros context typ state hwf; simpl.\n  now exists Value.Nil; intuition.\n- intros context hd tl typ h0 hi0 h1 hi1 state hwf; simpl.\n  destruct (hi0 _ hwf) as [vhd [-> hv]].\n  destruct (hi1 _ hwf) as [vtl [-> ht]].\n  now exists (Value.Cons vhd vtl); intuition.\n(* ok_tuple *)\n- intros context expr typ h hi state hwf; simpl.\n  destruct (hi _ hwf) as [v [-> ?]].\n  now  exists (Value.Cons v Value.Nil); intuition.\n- intros context expr el typ tl h0 hi0 h1 hi1 state hwf; simpl.\n  destruct (hi0 _ hwf) as [vhd [-> ?]].\n  destruct (hi1 _ hwf) as [vtl [-> ?]].\n  now exists (Value.Cons vhd vtl); intuition.\nQed.\n\nLemma eval_ok: forall context expr typ, ok context expr typ ->\n    forall state, well_formed_estate state context ->\n    exists v, eval state expr = Some v /\\ okv v typ.\nProof.\nintros.\nnow eapply eval_ok_; eauto.\nQed.\n\nLemma eval_list_ok: forall context le typ, ok_list context le typ ->\n    forall state, well_formed_estate state context ->\n    exists lv, eval_list state le = Some lv /\\ okv_list lv typ.\nProof.\nintros.\nnow eapply eval_ok_; eauto.\nQed.\n\nLemma eval_tuple_ok: forall context le lt, ok_tuple context le lt ->\n    forall state, well_formed_estate state context ->\n    exists lv, eval_list state le = Some lv /\\ okv_tuple lv lt.\nProof.\nintros.\nnow eapply eval_ok_; eauto.\nQed.\n\nLemma ok_sequence : forall context expr T, ok context expr T ->\n    forall T', is_sequence T = Some T' ->\n    forall state, well_formed_estate state context ->\n    exists lv, eval state expr = Some (Value.Sequence lv).\nProof.\ninduction 1 as [\n    | context\n    | context z\n    | context str\n    | context\n    | context left right op hl hr\n    | context left right op hl hr\n    | context l typ hl\n    | context l typs hl\n    | context expr he\n    | context expr op hop he\n    | context target test alterntaive typ htarget hit halt hia htest hitest\n    | context id b T h\n]; intros T' hT state hwf; simpl; subst;\n  try (unfold is_sequence in hT; simpl in hT; discriminate).\n- apply eval_list_ok with (state := state) in hl as [lv [-> ?]]; [ | now idtac ].\n  now exists lv.\n- destruct (hit T' hT state hwf) as [l1 ->].\n  destruct (hia T' hT state hwf) as [l2 ->].\n  apply ty_bool with (state := state) in htest as [b ->]; [ | now idtac ].\n  now destruct b; eexists; reflexivity.\n- apply well_formed_estate_get with (state := state) in h as [v [-> h1]];\n    [ | now idtac ].\n  inversion h1; subst; clear h1; try discriminate; now eexists; reflexivity.\nQed.\n\nLemma ty_list: forall context expr T, ok context expr (Typ.List T) ->\n    forall state, well_formed_estate state context ->\n    exists lv, eval state expr = Some (Value.Sequence lv) /\\\n               okv (Value.Sequence lv) (Typ.List T).\nProof.\nintros context expr T hok state hwf.\napply eval_ok with (state := state) in hok; [ | now idtac].\ndestruct hok as [v [-> hv]].\ninversion hv; subst; clear hv.\nexists l; split; [ now idtac | ].\nnow constructor.\nQed.\n\n(* begin hide *)\nLemma well_formed_estate_add: forall state context,\n  well_formed_estate state context ->\n  forall id b v T, okv v T ->\n  well_formed_estate (SMap.add id v state) (SMap.add id (b, T) context).\nProof.\nintros state context hwf id b v T hok.\nintros k b' S.\nrewrite !find_add_smap.\ndestruct String.eqb.\n- intro h; injection h; clear h; intros; subst.\n  exists v; split; [ | assumption ].\n  reflexivity.\n- now apply hwf.\nQed.\n\nLemma well_formed_set: forall state context,\n  well_formed state context ->\n  forall id b v T, okv v T ->\n  well_formed (set state id v) (set context id (b, T)).\nProof.\nintros state context hwf id b v T hok; split; [| split].\n- now destruct hwf; apply well_formed_estate_add.\n- now apply hwf.\n- intros f func; simpl.\n  now apply hwf.\nQed.\n\n(* Helper lemma to build valid context and state for prepare_call_*:\n   In a well_formed global context/state, if some arguments are correctly\n   typed, then calling prepare_call_* on a well formed context/state pair leads\n   to a new well formed context/state pair.\n\n   We'll then use this function with the trival \"empty\" pair to build \n   the context/state we need for function calls *)\nLemma well_formed_estate_prepare_:\n  (* current context/state is well formed *)\n  forall current_context current_state,\n  well_formed_estate current_state current_context ->\n  (* arguments are typed by parameters *)\n  forall arguments parameters,\n  check_arguments current_context arguments parameters ->\n  forall value_arguments,\n  eval_list current_state (from_list (map snd arguments)) = Some value_arguments ->\n  (* updating a well formed pair leads to a new well formed pair *)\n  forall state context new_state,\n  well_formed_estate state context ->\n  prepare_call_state state value_arguments parameters = Some new_state ->\n  well_formed_estate new_state (prepare_call_context context parameters).\nProof.\nintros current_context current_state hwf_current.\ninduction arguments as [ | [? expr] arguments hi];\n    intros parameters hcheck value_arguments heval state context new_state hwf hprep;\n    simpl in *.\n- destruct parameters as []; [ | now elim hcheck ]; simpl.\n  injection heval; intro; subst; clear heval; simpl in hprep.\n  now injection hprep; intro; subst; clear hprep.\n- destruct parameters as [ | [ ? ty] parameters ]; [now elim hcheck | ]; simpl.\n  case_eq (eval current_state expr);\n    [intros v hv | intro hn; rewrite hn in heval; discriminate heval ].\n  rewrite hv in heval.\n  case_eq (eval_list current_state (from_list (map snd arguments)));\n    [intros vargs hvs | intro hn; rewrite hn in heval; discriminate heval ].\n  rewrite  hvs in heval; injection heval; clear heval; intro hvargs;\n    subst; simpl.\n  destruct hcheck as [hok hcheck].\n  simpl in hprep.\n  apply (hi _ hcheck _ hvs (SMap.add s v state) _); [ | assumption ].\n  apply well_formed_estate_add; [ now idtac | ].\n  apply eval_ok with (state := current_state) in hok; [ | now idtac ].\n  destruct hok as [w [h1 h2]].\n  now rewrite hv in h1; injection h1; clear h1; intro h1; subst.\nQed.\n\nLemma well_formed_estate_prepare:\n  forall context state arguments parameters value_arguments,\n  well_formed_estate state context ->\n  check_arguments context arguments parameters ->\n  eval_list state (from_list (map snd arguments)) = Some value_arguments ->\n  forall new_state,\n  prepare_call_state Eval.Empty value_arguments parameters =  Some new_state ->\n  well_formed_estate new_state (prepare_call_context Empty parameters).\nProof.\nintros context state arguments parameters value_arguments hwf hcheck heval \n  new_state hprep.\neapply well_formed_estate_prepare_.\n- now apply hwf.\n- now apply hcheck.\n- now apply heval.\n- intros k b T h; discriminate h.\n- now apply hprep.\nQed.\n\nLemma well_formed_estate_add_remove: forall state context,\n  well_formed_estate state context ->\n  forall id b T,\n  well_formed_estate state (SMap.remove id (SMap.add id (b, T) context)).\nProof.\nintros s ctx hwf id b T id' b' T'; simpl.\nrewrite find_remove_smap.\ncase_eq (id' =? id)%string; intros heq; [ intro; discriminate | ].\nrewrite find_add_smap, heq; intro hg.\nnow apply hwf in hg.\nQed.\n(* end hide *)\n\n(** * Type Preservation\n\n    Under a well-formed context/state, if a statement and a continuation\n    are correctly typed, then any operational step leads to new correctly\n    typed statement and resolution, and the resulting states are still\n    well-formed.\n*)\nLemma sss_preservation: forall context context' state state' stmt stmt'\n  k k' return_type,\n  typ context return_type stmt context' ->\n  ktyp context' return_type k ->\n  well_formed state context ->\n  sss state stmt k state' stmt' k' ->\n  exists ocontext ocontext' return_type',\n  typ ocontext return_type' stmt' ocontext' /\\\n  ktyp ocontext' return_type' k' /\\\n  well_formed state' ocontext.\nProof.\nintros context context' state state' stmt stmt' k k' return_type h;\n  revert state state' stmt' k k';\ndestruct h as [\n    context return_type id expr T hget okvalue\n  | context return_type id expr T Tid hget okvalue\n  | context return_type id expr T hget okvalue\n  | context return_type id expr T okvalue\n  | context return_type expr T h\n  | context context' return_type test body orelse oktest hbody horlese\n  | context return_type\n  | context context' context'' return_type stmt next hst hnext\n  | context context' return_type test body orlelse hok hbody horelse\n  | context return_type target annotation f arguments func hg hret hcheck\n  | context return_type f arguments func hg hret hcheck\n  | context context' ret T hok\n]; intros s s' stmt' k k' hk hwf hs.\n(* Assign *)\n- destruct (eval_ok _ _ _ okvalue s (proj1 hwf)) as [v [hv0 hv1]].\n  inversion hs; subst; clear hs.\n  exists (set context id (false, T)); exists (set context id (false, T));\n    exists return_type; intuition.\n  rewrite hv0 in H7; injection H7; clear H7; intros ?; subst.\n  now apply well_formed_set.\n- destruct (eval_ok _ _ _ okvalue s (proj1 hwf)) as [v [hv0 hv1]].\n  inversion hs; subst; clear hs.\n  exists (set context id (false, T)); exists (set context id (false, T));\n    exists return_type; intuition.\n  rewrite hv0 in H7; injection H7; clear H7; intros ?; subst.\n  now apply well_formed_set.\n- destruct (eval_ok _ _ _ okvalue s (proj1 hwf)) as [v [hv0 hv1]].\n  inversion hs; subst; clear hs.\n  exists (set context id (true, T)); exists (set context id (true, T));\n    exists return_type; intuition.\n  rewrite hv0 in H7; injection H7; clear H7; intros ?; subst.\n  now apply well_formed_set.\n- destruct (eval_ok _ _ _ okvalue s (proj1 hwf)) as [v [hv0 hv1]].\n  inversion hs; subst; clear hs.\n  exists (set context id (true, T)); exists (set context id (true, T));\n    exists return_type; intuition.\n  rewrite hv0 in H7; injection H7; clear H7; intros ?; subst.\n  now apply well_formed_set.\n(* Expression *)\n- inversion hs; subst; clear hs.\n  exists context; exists context; exists return_type; now split.\n(* If *)\n- inversion hs; subst; clear hs.\n  + exists context; exists context'; exists return_type; now split.\n  + exists context; exists context'; exists return_type; now split.\n(* Pass *)\n- inversion hs; subst; clear hs.\n  + inversion hk; subst; clear hk. \n    exists call_context; exists call_context; exists return_type0; now split.\n  + inversion hk; subst; clear hk. \n    exists context; exists context'; exists return_type; now split.\n  + inversion hk; subst; clear hk.\n    exists context; exists context; exists return_type; intuition.\n    now apply ktypKWhile with (context' := context') (return_type := return_type).\n  + inversion hk; subst; clear hk.\n    exists context; exists context'; exists return_type; now split.\n(* Seq *)\n- inversion hs; subst; clear hs.\n  exists context; exists context'; exists return_type; intuition.\n  now apply ktypSeq with (context' := context'') (return_type := return_type).\n(* While *)\n- inversion hs; subst; clear hs.\n  + exists context; exists context; exists return_type; intuition.\n    now apply ktypKWhile with (context' := context') (return_type := return_type).\n  + exists context; exists context'; exists return_type; now split.\n(* Call *)\n- inversion hs; subst; clear hs.\n  unfold get_info in H8; unfold get_info in hg.\n  rewrite (well_formed_info_eq _ _ hwf), hg in H8; injection H8; intros;\n    subst; clear H8.\n  apply well_formed_function_get with (state := s) in hg as [fctx hf]; [| now idtac].\n  exists (mkContext (prepare_call_context Empty (parameters func0))\n  (FuncState context)).\n  exists fctx; exists (return_annotation func0); split; [ assumption | split ].\n  + apply ktypKCallFun with \n      (call_context := set context target (true, return_annotation func0))\n      (return_type := return_type); intuition.\n      * split; [ now apply well_formed_estate_add_remove; apply hwf | ].\n        split; [ now apply hwf | ].\n        intros f' func'; simpl.\n        now apply hwf.\n      * now rewrite find_add, String.eqb_refl.\n  + split; [ | split ].\n    * eapply well_formed_estate_prepare;\n      [now apply hwf | now apply hcheck | now apply H9| assumption].\n    * now apply hwf.\n    * intros f' func'; simpl.\n      now apply hwf.\n- inversion hs; subst; clear hs.\n  unfold get_info in H1; unfold get_info in hg.\n  rewrite (well_formed_info_eq  _ _ hwf), hg in H1; injection H1; intros; subst; clear H1.\n  apply well_formed_function_get with (state := s) in hg as [ fctx hf ]; [ | now idtac ].\n  exists (mkContext (prepare_call_context Empty (parameters func0)) (FuncState context)).\n  rewrite hret in hf.\n  exists fctx; exists Typ.None; split; [ assumption | split ].\n  + now apply ktypKCallProc with (call_context := context) (return_type := return_type).\n  + split; [ | split ].\n    * eapply well_formed_estate_prepare;\n      [now apply hwf | now apply hcheck | now apply H3|  assumption ].\n    * now apply hwf.\n    * intros f' func'; simpl.\n      now apply hwf.\n(* Return *)\n- inversion hs; subst; clear hs.\n  + inversion hk; subst; clear hk.\n    exists call_context; exists call_context; exists return_type;\n      split; [now constructor | ].\n    split; [assumption | ].\n    destruct H5 as [hewf h].\n    split; [ | now apply h].\n    intros x bx Tx hx.\n    unfold get in H7.\n    generalize (hewf x bx Tx).\n    simpl.\n    rewrite find_remove_smap, find_add_smap.\n    case_eq (x =? id)%string; intro heq.\n    * intros _.\n      apply String.eqb_eq in heq; subst.\n      unfold TContext_of_Context in hx.\n      rewrite hx in H7; injection H7; clear H7; intro; subst.\n      apply eval_ok with (state := RawState s) in hok; [ | now apply hwf ].\n      destruct hok as [w [hw ?]].\n      unfold EState_of_State in H1.\n      rewrite hw in H1; injection H1; clear H1; intro; subst.\n      now exists vret.\n    * intro hg; apply hg in hx as [v [hv hv2]].\n      now exists v.\n  + inversion hk; subst; clear hk.\n    exists call_context; exists call_context; exists return_type;\n      split; [now constructor | now split ].\n  + inversion hk; subst; clear hk.\n    exists context; exists context'0; exists T;\n      split; [ now constructor | now split ].\n  + inversion hk; subst; clear hk.\n    exists context; exists context'0; exists T;\n      split; [ now constructor | now split ].\n  + inversion hk; subst; clear hk.\n    exists context; exists context; exists Typ.None;\n      split; [ now constructor | now split ].\nQed.\n\n(** If some <<arguments>> are correctly typed by some <<parameters>> then\n    evaluating the <<parameters>> leads to a list of values. *)\nLemma check_arguments_eval: forall (arguments : list (option string * Expression.t))\n  state context parameters,\n  well_formed_estate state context ->\n  check_arguments context arguments parameters ->\n  exists value_arguments,\n  eval_list state (from_list (map snd arguments)) = Some value_arguments.\nProof.\ninduction arguments as [ | [? arg] arguments hi];\n    intros state context parameters hwf hcheck; simpl in *.\n- destruct parameters; [| now elim hcheck].\n  now exists Value.Nil.\n- destruct parameters as [ | [? ty] parameters]; [ now elim hcheck |  ]; simpl in *.\n  destruct hcheck as [ha has].\n  apply eval_ok with (state := state) in ha as [ v [-> hv]]; [ | now idtac].\n  destruct (hi _ _ _ hwf has) as [vs ->].\n  now exists (Value.Cons v vs).\nQed.\n\n(** A <<done>> pair of statement and continuation is a situation where\n    there is no further possible reduction, and is considered a normal\n    final situation.\n    For the moment, we consider:\n    - statement == Pass and continuation == KStop: the \"genuine\" final state.\n    - statement == Pass and continuation == KCall: this one can only happen\n        when a return statement is missing. We can't rule it out using\n        typing only. We should make sure that all programs we check\n        have the relevant 'return' invocation in all functions.\n*)\nDefinition done st k :=\n  match st with \n  | Statement.Pass =>\n    match k with\n    | KStop \n    | KCall _ _ _ => True\n    | _ => False\n  end\n  | _ => False\nend.\n\n(** In this system, a correctly typed triple <<s, st, k>> is either a\n    final (<<done>>) configuration, or can be reduced at least one step \n    using the operational semantic.\n\n    With preservation and determinism, we have the main correctness tools\n    for our system. *)\nLemma progress: forall context context' return_type stmt k,\n    typ context return_type stmt context' ->\n    ktyp context' return_type k ->\n    forall state, well_formed state context ->\n    (done stmt k) \\/ (exists state' stmt' k', sss state stmt k state' stmt' k').\nProof.\ndestruct 1 as [\n    context return_type id expr T hget okvalue\n  | context return_type id expr T Tid hget okvalue\n  | context return_type id expr T hget okvalue\n  | context return_type id expr T okvalue\n  | context return_type expr T h\n  | context context' return_type test body orelse oktest hbody horlese\n  | context return_type\n  | context context' context'' return_type st next hst hnext\n  | context context' return_type test body orlelse hok hbody horelse\n  | context return_type target annotation function_name arguments function_def\n      hg hret hcheck\n  | context return_type function_name arguments function_def hg hret hcheck \n  | context context' ret T hok\n]; intros hk state hwf.\n- apply eval_ok with (state := RawState state) in okvalue; [ | now apply hwf ].\n  destruct okvalue as [v hv].\n  now right; repeat eexists; econstructor; apply hv.\n- apply eval_ok with (state := RawState state) in okvalue; [ | now apply hwf ].\n  destruct okvalue as [v hv].\n  now right; repeat eexists; econstructor; apply hv.\n- apply eval_ok with (state := RawState state) in okvalue; [ | now apply hwf ].\n  destruct okvalue as [v hv].\n  now right; repeat eexists; econstructor; apply hv.\n- apply eval_ok with (state := RawState state) in okvalue; [ | now apply hwf ].\n  destruct okvalue as [v hv].\n  now right; repeat eexists; econstructor; apply hv.\n- apply eval_ok with (state := RawState state) in h; [ | now apply hwf ].\n  destruct h as [v hv].\n  now right; repeat eexists; econstructor; apply hv.\n- right.\n  apply ty_bool with (state := RawState state) in oktest; [ | now apply hwf].\n  destruct oktest as [[] hb];\n    repeat eexists; econstructor; exact hb.\n- inversion hk; subst; clear hk.\n  + now left; split; firstorder.\n  + now right; repeat eexists; econstructor.\n  + right.\n    apply ty_bool with (state := RawState state) in H; [ | now apply hwf ].\n    destruct H as [[] hb];\n      repeat eexists; econstructor; exact hb.\n  + now right; repeat eexists; econstructor.\n  + now left; split; firstorder.\n- now right; repeat eexists; econstructor.\n- right.\n  apply ty_bool with (state := RawState state) in hok; [ | now apply hwf ].\n  destruct hok as [[] hb]; now repeat eexists; econstructor.\n- right.\n  assert (hlen: List.length arguments = List.length (parameters function_def))\n    by now apply check_arguments_length in hcheck. \n  apply check_arguments_eval with (state := RawState state) in hcheck; [ | now apply hwf].\n  destruct hcheck as [vs hvs].\n  assert (hlen2: List.length arguments = List.length vs) by\n    now apply eval_list_length in hvs;\n        rewrite <- hvs, Expression.ListHelpers.from_list_cancel, map_length.\n  destruct (prepare_call_state_same_length Eval.Empty vs (parameters function_def))\n    as [ after hafter ]; [now rewrite hlen2 in hlen | ].\n  repeat eexists.\n  econstructor; [| now apply hvs| now apply hafter].\n  apply well_formed_get_info with (function_name := function_name) in hwf;\n    rewrite <- hwf.\n  now apply hg.\n- right.\n  assert (hlen: List.length arguments = List.length (parameters function_def))\n    by now apply check_arguments_length in hcheck. \n  apply check_arguments_eval with (state := RawState state) in hcheck; [ | now apply hwf].\n  destruct hcheck as [vs hvs].\n  assert (hlen2: List.length arguments = List.length vs) by\n    now apply eval_list_length in hvs;\n        rewrite <- hvs, Expression.ListHelpers.from_list_cancel, map_length.\n  destruct (prepare_call_state_same_length Eval.Empty vs (parameters function_def))\n    as [ after hafter ]; [ now rewrite hlen2 in hlen | ].\n  repeat eexists.\n  econstructor; [| now apply hvs| now apply hafter].\n  apply well_formed_get_info with (function_name := function_name) in hwf;\n    rewrite <- hwf.\n  now apply hg.\n- inversion hk; subst; clear hk.\n  + right; repeat eexists.\n    now constructor.\n  + right; repeat eexists.\n    now econstructor.\n  + right; repeat eexists.\n    now econstructor.\n  + right; repeat eexists.\n    now econstructor.\n  + apply eval_ok with (state := RawState state) in hok as [v [hv1 hv2]];\n     [ | now apply hwf ].\n    right; exists (set saved_state target v); exists Statement.Pass; exists k0.\n    now constructor.\nQed.\n\n(* begin hide *)\nModule Test.\n\n(* Creating a test context with no type information on variable, and\nthe same function information that Eval.Test.test_state *)\nDefinition test_context: Context :=\n  mkState _ (SMap.empty _) (FuncState Eval.Test.test_state).\n\n(* Final typing context, with y:int as only type information *)\nDefinition final_context : Context :=\n  set test_context \"y\"%string (true, Typ.Integer).\n\n(* We show here that in the context `test_context`, and under any return type,\n   type checking the program Eval.Test.Prog only introduces y:int in the\n     context *)\nLemma Typing_Prog: forall return_type,\n  typ test_context return_type Eval.Test.Prog final_context.\nProof.\nintro return_type.\nunfold Test.Prog, final_context, Test.YID.\napply typCallFun with (function_def := Test.int_id).\n- apply SMap.find_1; apply SMap.add_1.\n  reflexivity.\n- reflexivity.\n- simpl; split; [| exact I].\n  now constructor.\nQed.\n\nDefinition test_context2 : Context :=\n  mkState _ (SMap.empty _) (FuncState Eval.Test.test_state2).\n\nLemma Typing_Prog2: forall return_type,\n  typ test_context2 return_type Eval.Test.Prog2 test_context2.\nProof.\nintro return_type.\napply typCallProc with (function_def := Test.expect_int).\n- apply SMap.find_1; apply SMap.add_1.\n  reflexivity.\n- reflexivity.\n- simpl; split; [| exact I].\n  now constructor.\nQed.\n\n(* Some well-formed proofs *)\nLemma well_formed_int_id : well_formed_function (FuncState test_context) Test.int_id.\nProof.\nunfold well_formed_function.\nexists (mkContext (prepare_call_context Empty (parameters Test.int_id))\n       (FuncState test_context)).\nconstructor.\neconstructor.\nsimpl.\napply SMap.find_1; apply SMap.add_1.\nreflexivity.\nQed.\n\nLemma well_formed_test: well_formed Test.test_state test_context.\nProof.\nsplit; [| split; [ reflexivity | intros fname fdef ]].\n- intros id T.\n  unfold test_context; simpl.\n  intros b h; discriminate h.\n- unfold get_info; simpl.\n  rewrite find_add_smap.\n  case_eq (fname =? \"int_id\")%string; intro heq.\n  + intro h; injection h; clear h; intro h; subst.\n    exact well_formed_int_id.\n  + intro h; discriminate h.\nQed.\n\n(* Successive valid assignement mixing weak and strong update *)\nDefinition Prog_Assign_good :=\n  Statement.to_seq\n    (Statement.Assign Eval.Test.XID None (Eval.Test.Int 42) ::\n    Statement.Assign Eval.Test.XID None Expression.True_ ::\n    Statement.Assign Eval.Test.XID (Some Typ.Integer) (Eval.Test.Int 42) ::\n    Statement.Assign Eval.Test.XID None (Eval.Test.Int 42) ::\n    Statement.Assign Eval.Test.XID (Some Typ.Boolean) Expression.False_ ::\n    nil).\n\nDefinition EmptyContext : Context :=\n  mkState _ (SMap.empty _) (SMap.empty _).\n\nLemma Prog_Assign_good_typed: forall return_type,\n  typ EmptyContext return_type Prog_Assign_good\n    (* resulting context. It's content is not really relevant *)\n    (set (set (set (set\n      (set EmptyContext  \"x\" (false, Typ.Integer))\n        \"x\" (false, Typ.Boolean))\n        \"x\" (true, Typ.Integer))\n        \"x\" (true, Typ.Integer))\n        \"x\" (true, Typ.Boolean)).\nProof.\nunfold EmptyContext.\nintros return_type.\neconstructor; [ | econstructor; [ | econstructor; [ | econstructor ]]].\n- apply typAssignIdNone; [ reflexivity | ].\n  now constructor.\n- unfold set; simpl.\n  apply typAssignIdNoneWeak with (Tid := Typ.Integer); [ | now constructor ].\n  apply SMap.find_1; apply SMap.add_1.\n  reflexivity.\n- apply typAssignIdAnnot.\n  now constructor.\n- apply typAssignIdNoneStrong; [ | now constructor ].\n  apply SMap.find_1; apply SMap.add_1.\n  reflexivity.\n- apply typAssignIdAnnot.\n  now constructor.\nQed.\n\n(* Invalid assignement *)\nDefinition Prog_Assign_wrong1 :=\n  Statement.Assign Eval.Test.XID (Some Typ.Integer) Expression.True_.\n\n(* Invalid assignement after user annotation *)\nDefinition Prog_Assign_wrong2 :=\n  Statement.to_seq\n    (Statement.Assign Eval.Test.XID (Some Typ.Integer) (Eval.Test.Int 42) ::\n     Statement.Assign Eval.Test.XID None Expression.True_ ::\n     nil).\n\nLemma Prog_Assign_wrong1_untypable: forall context return_type return_context,\n  typ context return_type Prog_Assign_wrong1 return_context -> False.\nProof.\nintros context return_type return_context h.\ninversion h; subst; clear h.\nnow inversion H5.\nQed.\n\nLemma Prog_Assign_wrong2_untypable: forall context return_type return_context,\n  typ context return_type Prog_Assign_wrong2 return_context -> False.\nProof.\nintros context return_type return_context h.\ninversion h; subst; clear h.\ninversion H3; subst; clear H3.\ninversion H5; subst; clear H5.\n- now rewrite find_add, String.eqb_refl in H3.\n- rewrite find_add, String.eqb_refl in H3.\n  now injection H3.\n- rewrite find_add, String.eqb_refl in H3.\n  injection H3; clear H3; intro hT.\n  rewrite <- hT in H6.\n  now inversion H6.\nQed.\n\nEnd Test.\n(* end hide *)\n", "num_lines": 1421}
{"repo_name": "pyre-check", "repo_creator": "facebook", "programming_language": "V", "code": "Require Import List String.\nRequire Pyre.Expression.\nRequire Pyre.Lvalue.\nRequire Pyre.Typ.\n\n(** * Statements\n\n  More will be added later on. See\n  https://github.com/facebook/pyre-check/blob/main/ast/statement.mli#L331\n*)\nInductive t : Set :=\n  | Assign: forall (target: Lvalue.t)\n                   (annotation: option Typ.t)\n                   (value: Expression.t),\n                   t\n  | Call: forall (target: option (Lvalue.t * Typ.t))\n                 (callee: Expression.t)\n                 (arguments: list ((option string) * Expression.t)),\n                 t\n  | Expression: Expression.t -> t\n  | Delete: Expression.t -> t\n  | For: forall (target: Lvalue.t) (iterator: Expression.t) (body orelse: t), t\n  | Global: list string -> t\n  | If: forall (test: Expression.t) (body orelse: t), t\n  | Nonlocal: list string -> t\n  | Pass: t\n  | While: forall (test: Expression.t) (body orelse: t), t\n  | Seq : forall (st next : t), t\n  | Return: forall (ret: Expression.t), t\n.\n\nFixpoint to_seq (statements: list t) : t :=\n  match statements with\n  | nil => Pass\n  | hd :: nil => hd\n  | hd :: tl => Seq hd (to_seq tl)\n  end.\n", "num_lines": 38}
{"repo_name": "pyre-check", "repo_creator": "facebook", "programming_language": "V", "code": "Require Import List ZArith String.\n\n(** Types *)\nInductive t: Set :=\n | Integer: t\n | Boolean: t\n | String: t\n | List: t -> t\n | Tuple: tlist -> t\n | None: t\nwith tlist: Set :=\n | Nil: tlist\n | Cons: t -> tlist -> tlist\n.\n\nHint Constructors t tlist : core.\n\nScheme typ_ind' := Induction for t Sort Prop\n  with typ_list_ind' := Induction for tlist Sort Prop.\n\nCombined Scheme typ_ind from typ_ind', typ_list_ind'.\n\nRequire Import List.\n\nModule ListHelpers.\n\nFixpoint to_list (l: tlist) : list t :=\n    match l with\n    | Nil => nil\n    | Cons hd tl => hd :: to_list tl\n    end.\n\nFixpoint from_list (l: list t) : tlist :=\n    match l with\n    | nil => Nil\n    | hd :: tl => Cons hd (from_list tl)\n    end.\n\nLemma to_list_cancel: forall l, from_list (to_list l) = l.\nProof.\ninduction l as [ | hd tl hi]; simpl in *; [ now idtac | ].\nnow rewrite hi.\nQed.\n\nLemma from_list_cancel: forall l, to_list (from_list l) = l.\nProof.\ninduction l as [ | hd tl hi]; simpl in *; [ now idtac | ].\nnow rewrite hi.\nQed.\n\nCoercion to_list: tlist >-> list.\nEnd ListHelpers.\n", "num_lines": 53}
{"repo_name": "pyre-check", "repo_creator": "facebook", "programming_language": "V", "code": "Require Import String Bool ZArith List.\n\n(** * Values *)\nInductive t : Set :=\n  | Boolean: bool -> t\n  | Integer: Z -> t \n  | String: string -> t \n  | Sequence: tlist -> t \n  | None: t\nwith tlist  : Set :=\n  | Nil: tlist\n  | Cons: t -> tlist -> tlist\n.\n\nHint Constructors t tlist : core.\n\nScheme value_ind' := Induction for t Sort Prop\n  with value_list_ind' := Induction for tlist Sort Prop.\n\nCombined Scheme value_ind from value_ind', value_list_ind'.\n\n(** Boolean equality for values and list of values *)\nFixpoint eqb (l r: t) { struct l } : bool :=\n    match l, r with \n    | Boolean b0, Boolean b1 => Bool.eqb b0 b1\n    | Integer z0, Integer z1 => Z.eqb z0 z1\n    | String s0, String s1 => String.eqb s0 s1\n    | Sequence l1, Sequence l2 => eqb_list l1 l2\n    | None, None => true\n    | _ ,_ => false\n    end\nwith eqb_list (l1 l2: tlist) : bool :=\n    match l1, l2 with\n    | Nil, Nil => true\n    | (Cons hd1 tl1), (Cons  hd2 tl2) =>\n            andb (eqb hd1 hd2) (eqb_list tl1 tl2)\n    | _, _ => false\n    end.\n\nLemma eqb_true_ : (forall v0 v1, eqb v0 v1 = true -> v0 = v1)\n  /\\ (forall l0 l1, eqb_list l0 l1 = true -> l0 = l1).\nProof.\napply value_ind.\n- intros b [] h; simpl in *; try discriminate.\n  now apply Bool.eqb_prop in h; subst.\n- intros z []  h; simpl in *; try discriminate.\n  now apply Z.eqb_eq in h; subst.\n- intros str [] h; simpl in *; try discriminate.\n  now apply String.eqb_eq in h; subst.\n- intros l0 hi [ | | | l1 | ] h; simpl in *; try discriminate.\n   now apply hi in h; subst.\n- now intros [ ]; try discriminate.\n- now intros [ ]; try discriminate.\n- intros v hiv l0 hi [ | hd tl ] h; simpl in *; try discriminate.\n  apply andb_prop in h as [h0 h1].\n  apply hiv in h0 as ->.\n  now apply hi in h1 as ->.\nQed.\n\nLemma eqb_eq: forall v0 v1, eqb v0 v1 = true -> v0 = v1.\nProof.\n    now apply eqb_true_.\nQed.\n\nLemma eqb_list_eq:  forall l0 l1, eqb_list l0 l1 = true -> l0 = l1.\nProof.\n    now apply eqb_true_.\nQed.\n\nLemma eqb_refl_: (forall v, eqb v v = true) /\\ (forall lv, eqb_list lv lv = true).\nProof.\napply value_ind; try (now intros).\n- now intros [].\n- intro z; simpl.\n  now rewrite Z.eqb_refl.\n- intro s; simpl.\n  now rewrite String.eqb_refl.\n- intros v hv lv hlv; simpl.\n  now rewrite hv, hlv.\nQed.\n\nLemma eqb_refl: forall v, eqb v v = true.\nProof.\nnow apply eqb_refl_.\nQed.\n\nRequire Import List.\n\nModule ListHelpers.\n\nFixpoint to_list (l: tlist) : list t :=\n    match l with\n    | Nil => nil\n    | Cons hd tl => hd :: to_list tl\n    end.\n\nFixpoint from_list (l: list t) : tlist :=\n    match l with\n    | nil => Nil\n    | hd :: tl => Cons hd (from_list tl)\n    end.\n\nLemma to_list_cancel: forall l, from_list (to_list l) = l.\nProof.\ninduction l as [ | hd tl hi]; simpl in *; [ now idtac | ].\nnow rewrite hi.\nQed.\n\nLemma from_list_cancel: forall l, to_list (from_list l) = l.\nProof.\ninduction l as [ | hd tl hi]; simpl in *; [ now idtac | ].\nnow rewrite hi.\nQed.\n\nCoercion to_list: tlist >-> list.\nEnd ListHelpers.\n", "num_lines": 117}
{"repo_name": "pyre-check", "repo_creator": "facebook", "programming_language": "V", "code": "Require Import List Sorted.\nImport ListNotations.\n\n(** Facts about HdRel and Forall *)\nSection HdRelFacts.\nVariable A: Type.\nVariable R: A -> A -> Prop.\nHypothesis Rtrans : forall x y z, R x y -> R y z -> R x z.\n\nLemma HdRel_Forall: forall l x,\n  Sorted R l ->\n  HdRel R x l -> Forall (R x) l.\nProof.\ninduction l as [ | hd tl hi]; intros x hs h; simpl in *; [ now constructor | ].\napply HdRel_inv in h.\nconstructor; [ assumption | ].\napply Sorted_inv in hs as [ h0 h1].\napply hi; [assumption |].\ndestruct tl; [ now constructor | constructor].\napply HdRel_inv in h1.\nnow apply (Rtrans x hd a).\nQed.\nEnd HdRelFacts.\n", "num_lines": 24}
{"repo_name": "pyre-check", "repo_creator": "facebook", "programming_language": "V", "code": "Require Import String.\nRequire Import OrderedType OrderedTypeEx.\n\n(* Wrapper around String_as_OT *)\nModule String_facts := OrderedTypeFacts(String_as_OT).\n\nDefinition lt (s1 s2: string) : Prop := String_as_OT.lt s1 s2.\n\nDefinition ltb (s1 s2: string) : bool :=\n  match String_facts.lt_dec s1 s2 with \n  | left _ => true \n  | right _ => false\nend.\n\nLemma ltb_lt: forall s1 s2, lt s1 s2 <-> ltb s1 s2 = true.\nProof.\nunfold lt, ltb.\nintros s1 s2; split; intro h.\n- destruct String_facts.lt_dec as [ hdec | hdec ]; [ reflexivity | ].\n  now elim hdec.\n- destruct String_facts.lt_dec as [ hdec | hdec ]; [ | discriminate ].\n  assumption.\nQed.\n\nLemma ltb_nlt: forall s1 s2, (~ lt s1 s2) <-> ltb s1 s2 = false.\nProof.\nintros s1 s2; split; intro h.\n- destruct (ltb_lt s1 s2) as [h1 h2].\n  destruct (ltb s1 s2); [ | reflexivity ].\n  now elim (h (h2 refl_equal)).\n- destruct (ltb_lt s1 s2) as [h1 h2].\n  intro hlt.\n  apply h1 in hlt.\n  rewrite h in hlt.\n  discriminate.\nQed.\n\nDefinition lt_trans := String_as_OT.lt_trans.\n\nLemma lt_ge: forall x y:string, ltb x y = false -> ltb y x = true \\/ x = y.\nProof.\nintros x y hltb.\ndestruct (String_facts.lt_total x y) as [h | [h | h]].\n- apply ltb_lt in h.\n  now rewrite h in hltb; discriminate.\n- now subst; right.\n- apply ltb_lt in h.\n  now left.\nQed.\n\nDefinition lt_not_eq := String_as_OT.lt_not_eq.\n", "num_lines": 52}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nbGT7tfmyts6/yZChogAFs2kP2mbFmmuiFroOv0r8QQv1hFG6JERBCXNBXfGou+8mLPigR5LV4eDx\nWE5VTd+gHQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nCWoEkLQgvsHNvKsNgOsMIlwqULIpu7GrNWea7T7cH++wHThbYiHobD6dcKucCQM5dNGL646pzspi\ngvc21hWZnPx+X5N28b2dNoegtcTB2kLdLw7Lks54cB9DeoTavLfTRXQYufpEksbrNJTUFVb2cNyN\n6BMeJUXHbb0vXcc5VT4=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nFNNqjXbqqfIGkUevtN9QbqDJwQreUsmu9xji2a/w3CJH665OoQqvJUOiq4+1ZDezrG2FheefDlOu\nudQOQzfUbqq4ZB7QVsrZ5+hnOl4+bTdi/FvverAngGvvJSU8+8gbzJ8jtcieV+kp8HrIMv5M1gu6\nVP5SY5P9OIiRMPqToUbAWBrFRpgduuTuMhaHwW7FZmVUVb1j1U3rE2T6UyEel2fueSISKzjAYa8d\nbMNfbkA2ORUFxDxV3b+bBcjCg+jYWECoAY59uutuI1TCRGdhy4DLAvrLFqaLXnKzQ/zhmv78sBnu\n10yEbUQnFKzl5lQwpKtElSrzEVryLPjEKxtU0Q==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nBtsuQ3rIBJ3UI+4s+peHFvk2pezsWjwgWqpQQAOktytWfnh45F6oITlHSewxA1WtBlnC7B06RlL1\nsh5uBcV81aLk24XWmuA7DcJrmhXRSOvl0k4gIwFckG2lpuYtWsH8y7owyOiD/FZUz/LSfTa3Mywh\nD7uNSNvKmmqFP0yIDB9zQtZJYDKPgeAlZS9NUZdzjF/a61kdekWKbPaCmwFQ0mA01X8N8Euy78Cm\ntwhuK1u9d5vu3NtNKQQjzffGoOig7AOKPE+KjZrhCajjfXLjFewajxJNXuRqE4Qr4GGCy18JUK+r\n9AD7YQrF9CXYq3xjR5zoOedNXXQz29GC/jViKA==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nGzBT1kWKJ35ymgjppXjhmBsPZAh+qqs629kt2BvXZjQHKHWH3WuilMysbQpFcvgaH9NxbR7qFPN6\nyb5XgBkpZDUCCrc6p6YR51wXM/nxNvw23FSNPFKjoFEw2V83YYFxlbr75lWeNCQl27cPfBPuxaSV\nIjlxIsm4eW9SkxEnTQqMX5ySy4IaL9yElffDeFxfvmZFrx9lJp5FMRFsWvs0CJEBnPV6KLu1CvY0\njoTQyovEbzWILZvpO6OoWWowRhHO/ukpDVkTQwizIuNbetdcKud8UyyAngECUSjve9k+rXX41zHR\nrDfFrjZc+RPg2YpdeYHykcsisoZ5sdzyCy4T5w==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\niim3M0ZIoSIeblUIY0hk1kn3BvlRMe2uVKS16OYK9H9BGNvnKistWqz2WEU4s7eijjhhkWdw6Rx0\n1TXQht76iCER16gWcazz66/Akg5MH+lOp9NPf3J2iEV7LK7f+3F9jgvrsadzyPoTuLecIoWFoNJk\nFXdJK8072alT4ln/U8w=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\npJ/yajVXTo6y0FFyEOL0HIGDXa+xEims4jF/m3KWWifm3tyRZ/Qmr6px8fbYo6wt98IysxEsBMsY\nOafake1VkQe9IEYdvl9w2pbHgnMGCgpFHt5GVkkx9kTM7g8X5yw1cj7dCjsuNtLtsSeZ7wW2gvp4\nba+UNyDRcpm3wErDehZlm6QU2gigOYOXUMH6KQLyei8VsyCUEOLrtDfoDMEgbTsPan0OVwWZ4Yma\nBViyJ567bWm+BUmLR7HMTK0+QktDEmFhL5lWaTS848MSM8+2esUyNGdKKutfcQWcpHUx0GkIOnS0\nlZ1qTioC56L1NI2aXWshT+ZrJgi5x4ZYDqF6IA==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64336)\n`pragma protect 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ikj4QY9qy76XYw6IDsQdBnIGtPSFwxd9wChRjkni7PaX9nBoTv4Hkv4/X71ms92d\ntJ/07jLvlYIC/ZQu83ENzkpZcQxr+WVAlk9voN1Lh8MJ41Cksb/e82lQv3tE0i33RVWsfpzzkmhl\n6+iCuWQ09/k8dS0FyYp1eOOSakJpDvCoKsuGEA54TK2SkuCKjd+GAxav426xXnGAV1GxKJw4LUC+\nBoIDk42kjGmgDrTucR4D8ebhRKZlfSndBkUN1MxM4jhRdlUOlo1unmkpDpwboVbaBL63n0cP4G6M\nMWgaQmfg3Yi3VurtkG15kqklP5W2hoXk4N43ho9pwxbkiD0fB7BonN/w9HJv4Zu26k8JguWWER+r\nF24R1GsE91Dl6f8PkWleIhz82kPHFEq5RrhTesz5mPkAh4LBNNYQcbTVLlK5Bz0FGVt33lgt9zoT\n1OXASFCArKzZWd2y0Q5uZ6j1/oVxBrIIV84Ebwg//J/PeKNV+7dWoxdxrSyxxRk9/vGvVL/UxkDL\nXNFXWyLhbVlxG08uYDNL1cw4o1C3ePlskKxvHjLKaClc/79HN04C/k9fm51CrfmvosEcGzKhDPBj\nHMwFxAT3Pw83gG0A4Em+qHW7Wk8Bzor/p/e6kDCX2WbCTGXt8ZMf/Cq6Dryzr2sDHKfteVQJ2fpF\nHC/D0b26BUXdwRPX01IK0w8qiZ5/xcJUdwszggylh3pIeyt8qnPlZ1xYYH05884oekPtILD0GlZx\ndRw6hgHq6NYCifq33HepQkocmMaiBik7yzszAuKAWn2x5Raf/FC2GSRLb3itncwKnJGL7yYaSZeJ\n8OUhkMmGPtZ8ImThhDZ/RWkOBq+OUYnTNhKc3FmrCT9LsMzW0ZyQ9o+VsZv9bTJ+USliatHl6PD/\nLRypXj3clKV1a/C8C+rxwRip4mEQfKcf0UiZgBr6eYubS93izNsyymJ1mp/BMX6jt+kcmR3LAEE0\ncpyyOM0mIgNkjmJmLmv3R6jg/bPvI2p1N7/cIyybB4G0BZtRYMXRngfz1Q6EMQeQVsUna9iAjvQy\nAG2r/xcgJFufo3kkRGq2V3bTmOg/azUFNjzL/9jw4R6mkP391rUCjjKNDXYCpxvDS4Ye2p86OKcN\nXM4s+2bmJRe5JMBVj+0ZHS7ii0Mabn0ehWpoyMokVNz6dMpxel4glyyMLn1uEeaGHRDWuRfCqrOB\nfTnvUVJz1HNeGj9q7pSndbVygb7ZUsG8h3ZCkcyQhLOw47qwv3lDHtO77/HoYY9Tr62YzSiUh3z0\n9j8wCnOkMiqstzZ3iSyRXlGTQ8cV0IIcZ4obZHfQfj7I+N4MXnxEm4Pf8DHrXxlE0RxiG3MLn8Qp\nv1AES70B0p6TKWBC7H1cOxVI/K1ykT6KjY377HDe//18VNIC6IlFJzNuCN1q/+iLfRWlGy+uFMco\nAuFhgOP9A77fsu7sTi6ay+PaHjwC+jIiDGXdUXLPAJHxpDQzZfnDDo14bCy2ZRz1RWNEkUkLH6tY\nuGcD3kggbTyfoEOTkCtHzmGI7kFz1z7J9DYLueA4OMGamCdMbQxvlcUkwx/Yam/jPH2MB8HtyspC\new/FctHMgwthFB+FzPoSwmv+vsUZD7p8hri9LeoCnXPfXS7B0PhDyaHknDkaPDhEol1WramhVo0u\nGKZ8x1eDO9ipKqbYemWHLiAhYr8UXDVwN94diYZ9VcYwIrwr1P2VsWG/9O+R3rFngUUFk8Z4Bvip\n3PBfNVwE/QWhb/BgkmHeTvSayZckM9vCuruECucSChqNjhhIvSGY8CStQKNM+eK89IlUPsvIBY6l\nRZyKERWn9mxbX4ormBumHi4IznKEziX9fRRAEGW0uSLFhi/c435Qai4kSdBAoqvRTsu+7pIC8yv6\nmZ3UTSFrP9ATOE0GChYyllkCW590wKjCJcVXcdotPCuG+4IkqGFXeEYFfkQRLFX5drsg6AMEKhFl\n8EQOwjKQBjK4HT2f4vT4b5aHjEJ05K9SP1v5aTcX90VaEP5hR0OJDY8zsD40NbAozDPvBHZFX0ED\nIRhn+i/XVUxf4KkXcZ7BGUHiQvjXmiD7rd4O0nP0t99gvs5eB1QqiK16/QSY+J8Hu63WZWcdZZAv\n1Bl0sb7QjEa1onPN6MvMm284XZNYPuENoTvl84tdVpwWTTy6KaFjMfpGvs3Zw5rbRYjDqMU6FeLb\n7tSZ/ahWSGlsvFIWoqELhastLHLkIeMZyt8jlYUTAGEOEEraoePUOpjacUg8HrSpHie81DOaay7P\nAAzT/Is2R6begRrTAGNPq50SNgzPNmJomzUDHxlbuHeJYqnJzbTNmu2mm/QNIY5g4T3/ZUKkVv9Q\nrDjVCP+lEG/cEUycZ1Z78nVFuQWmcsM+c+assi7pL+uhWZzCPQizzj2hiM7VoacDeeG1IZ5IwMq0\nXp2/giop0Ak1pp75BsLEDXdzpcD8l6Gf+GZorCsODJ9BfSE12ihwudD2D7osjC/C/bUYdsrC/chx\nlQYFtNBnmCnTwsSK1xoevId8Y2WMMdNPuOhUUHqEtFNHL4EK/KM3VZU+CxrDDhp/Z7aMvgsweO4e\nFmHhSnvDyIGqCB6yPNMXL+UsWckLz2OL1rLGupkCvcfX4pwo9bia0CTK1ZkU5mrPXtvJ8iLvH5ZD\nELwT4RUG2uPfT9F2VS7xhdsTOj5USFtL68jcB4lQ3LdUwqMunj+M/wFkRUsc5Wo1Rna/htuyd3aP\nmvR4afocTUND8sbqWF86oE0b7M84KSsFKWn254Yv45b/7AGVXhW/zTIDhey6hbDDHa3zUhsRJ+sd\n3a7q9Kv9D7ax7QymetYPp67OmrE0CctHogPx89wzVtGxxpSFh+PSbv3u7EfYVFE5UV70g5dbWi52\n3Fe0kbBYQmCR+aJTy4hgxK666akTNVD8jx6UNgpOeJ9oLxbdi9gaCeP4YvldmkPNuv6n5m2SSHCN\nysHNq38Ri4NO/g8LNN3ZqRaQeeW04n7wNj43g2u7Q+AhVjNDn+3cUoMWV0XEdGhAlsvLAziOS8Aj\nAqOcs8PgfNLRn+/63nhr3S1tpn0oiSKA/UymFDp4XkFAl/NSQdSlZdl9yZfocKZ14yfbXP4naSXw\nYXdD9IJooJYT4vc3XhlNgoWURjW+vzbrQ+9Q0aDVLGwmTPWJcogLZSm4kAy7IhXy2y/e6LLI81FT\nbGmZxodxElq3jHE3z0CJEqoS+gsdBtdqC9QTMQaetDKYZvI5/vmZh3QKAamIvXVJ8TAgO+OxHgFd\nFxrvt+kVuLs1msjlkgS8mm8zfI4owlc5u5lmeVXtyCNHPLKHYAzzMNPW5Ai1OR6HoLM6UG/N2T34\nIXbk1QrwXKk878mT9EznzAhb/4bv6hoFEDgRIvCyyYweHxvzpmEfLiP6QaYNWWpO7iR/eaJHWw/w\n790hhWcg44VxliUVIWvozPbEuqHwxbBcXeC5Ksuxlmk8QdBhjHjrT3c76PX/AgEVe+DRzjzKRv5h\nMl6B13x1nZfviHANI6UOudXTe3BSkKBQatOSiKX4yGd35hKnuRYnDSNt1mYXH7lATfmjJFJ1TT73\nWSe0PhhtU7SE6IFs9oBDUTj2gUo4sKYA4alF58i9FJIqvxNGJAiLHJ8E/+pWe+aWwISfrECu9G7z\nfL+1k6nrcGpAegDvvNaMk9nvrHO5U8w3cCleTCuOdPKfWUgRuMapzh4NZ3PMrh8SXD1InQrZuBr/\n9wwsVObR2mdCCdXa+rhcQ78GUFqAhDlb/gDGwNJXRHEtPEgwsgr/EIIqHKun5yMnH9RkzScVLm+J\nhQtsd+JNrs4PPnSzdYGRKsNeWR1uZedxdvvmQuK6V9mJ1/9Rmqx/+sHIBiu+E3k4orWWGYdd/T8M\nGKqyT1rmVf0d2BrSPHzAKYdcRuxuewmDHbGVC3lq/yp65QOvQQO7N1EnY1gqIuYuYDxWjYKeiuwP\nQFDZvr5e0iMckylJHxO2Zkx+I12SyzSel48QzIAVnQmCTJ+X5gndrUh6LnLPRXJ6+tqzD9dfe3fA\nlb+egkye9h3JlbY+3Pjc+50z73r88qa/PpdTLyGj43GkhQTcr/5gW5n0AHoRaXiFYkNscs0Nos39\naAH1XRkvy408nbWfa2Gi7jxH7uI3+F3JkxicVp4XMzt+l+R+Dx0jSIyNA8oHaGXR7iODXmIVoCZV\nsxZNGSarntyxgE8l3LcO9FCL/iMvzfprNsX4JFDepRadUjspZB3K37Rtlr8GmaLhjZU3JZATm0vv\nmoZDKTaGGimpaBiPWWIIg5udEW5MYhrK4QvK8iJiuFcjIg4IBX3XEXi6+aZluEko16/4dzOkmd+e\nlZ5Dld272oEIa31In6knS3GnJn+b1p4s5Hl54tgnvGpXSISYPWD9Lq75SgxS/jHTRboTU19NRWhU\nGZYbeD0sh+mVjL2njjkPKpQ+0YFlelzdofUpHWOTVgDIGUgPQvZBn42WfsNJ/RV5TtsMZLjKLxaK\nKCX8wuFnxtCLoOUXBkbbosQYxnMAy1U44OrJu+0HOBqsrwNh5zFGJ/zk9/5utr8aQg/2aGimsg6J\nv7HyvEFEat6XUm+SLNRb4egTjBiPMHtEUqQzXg5WFNHpof6b17s5owPbAJDewviuC6u0+/FBomnn\ncjdCfOBsKr5oKtdJ9G/cfWevYkjMPzom6RgYqWKsOT4oXSsridVr9YSMbqMjs6TQyI53UUFHfVrF\nl0ryDtX4aJ6oq3I0s1jkTBQK2SVIvmMqBBreOHIPCFKB9G1cVT3e874jfndchxKWHYKOtVIJFav+\nL8Uo1/AnORfpmZ3MT04TOIfAJNO2opY0B5YuzT3m9m+wiD5/zMo6PmrcJJ3WVBY227wPW7hMWNNn\noOjAzzCrYiiO0/jDCB8OvnLChzLzTJmbwJe4z3LzHUGQQrZK+y5Tu/hI2S0CbbCb5l/4CxcADGOZ\nuOemAiz3WmIs6bykPvKCJ3YUD3M4F2iFz0Jc9H30enm5yuyqcKJoLQU5EWDirhIaywUHXRLN0ibW\nopXtRRfHpNK3lMJsLOJLnG0zXZGCJqyTj3qaVPfuys0B3+EBk12yq5qHRl4wt4HdS7zjxXqETTCS\nDWmTnT4ql9Ls9BhQoHCyeboOSARvoJCyg5bUFY4+3V+0E88wVyH2mpmkwGMTO1U7hbxtNJeZNcQw\n4x29DNm1Stga6kl3x8cvgu6djzr1ZOQOVMvIglT/BJQsYwV5NRK8kEiN/JrcDmE4po5lmaqOrEEd\nHnLyIi24A9t/bIbw350lCnc78BGA1Sk896A7Q8M8RbN/bHcWZcBBVJXli29+Go0U1cZ6vjpF4ote\nR7juv/pOYnF6fJkTyMQwM+5vzXEOMm7HcWdYRkQ7D3BbHuSVrhMBF89SrP7kn+SQ7CMEvfEG9gkj\noehWcUlTOkAPgQk+upUfEQ1V0IXIo+XGVCHXw1HlEAli9rLRlvLn2t99tZVdA9gnXSWDnaG0xm8R\nLth+31whyvvqwX0YwczoV5ZcVxTocWZwY2x4rKKiN1sDJ5PCIH5NrEMgJS2of6yaSC59QyvehjBw\nrRNKaNn2j7ZVpchE7btRVq+TWFqRMEnDj6B0wiKHy9A95fPH/jFUEg44Wgx2iIrKPooK1JfFJjbe\nTFsVM//5ug78qIzr214qkcwpUd+Zda7rHkJwxj4C8LcySIdWlAhhrFv5gtSCqrEIxbb4dyTvJ3v2\n29J4OwnSmjFaRx+7TxM4bH5xZBPQ9Aa5XDTCjtMA25CHWN46dF58ljRBnuxj/sTwdaqBLwjLFC/s\nAkRKeGbyuEkgZDGkgQ2uyOxRytYfZgUOGXyYAlgT4iE1lexh5KlOeiAzDxJoIQpPoMWANujOCHAv\n0CCpwPRIDa+2RYtlmvxXnQ/d9rmV/+bvuLlyg/PZfyF4lTfQ+gT5J6linBQ87uSw91z63GevX3vQ\nqIXoRUlm7FQIt6H+l7ILegL0BuaK/5858vbFl7BmT0xi4xczqNU5s5sPC7Jc1JhCohsjVnHvfwY2\n8qzZE/wJGg/5VjtcQrrIsoKjKqxGlUmOmA+gdWpIsqYx8y3lBO3oGE6LdohlPe50Ww3ftoagW1cK\nDi3dli+FTZBsGvAg9jehYrd6aHzVfHf2Y9oH7wo5VVoihibkHkzqoQtIf5kh+5qyhZ+GPgQhBdpC\niJA246TRn9v15Fx0Zn4OzczQG20209azn2UqWQULiPUy0AxceMoKJoI5ebd/IcNXjzH7HNmZBafC\nqmkvrkIAJJ1FNjBf+O0QphrrXFi8bHblHGOPHvgNOuyzywWWqrV4b4ppE4J2k+8EHYdTLVKZZ4Al\nYZ6gJSjesf8kxIgFcpqWikpTVY2Lip3rXeArsRv4MfC5Cjm1TjSdZAhN82oUsfszt8WRD+zl2+Yf\n6uRI8rD7tjXtB5A6MGRMrj9OUEXOgZhE4jqyNnCg6ichcoBhMt6I2frqhye4WGXAEMLI6vSDYRj9\nSnUdSngCYww1VjOT6c5zDafPzD96R10ddX1dvw2srvEC+Ie2efp5Qbmo1aa5lIQ57nk9WBJJvgaG\nXIhje8wa2mkKm5xLGWe4Y/yHPEpOwlPKyb3PhHzx+zIGduSAlzJSD+OZsJct2O03JrLOTWClXpm6\nN7E/Nv8Eynggtxy9yi27yj8r3I9F2I6vcGjNVurnmPRazqa6xDRN5XmvoZIxhaoyc22aS/cA2JTZ\n+yitWSfoXkzAXu6UL610+zmV2mfaoN5ISO0E1Wx5BXyYs9W4io4v/Vs5fF853UcjI07FeyIHaH/8\n633CANkUvI/Ls+GIu3A6u55H4++25ow4UvCUUjPyjgbvM08a25F/61H6L+v+hRkxKtflljcz2yFa\nWzu18dTrzpB6moutKoGhVnBhkISm1U8JTlUhMSkcwDMRjb+QWWk12wexPsUG6Klj1tbVZRO/kCWY\nBowdwm2TW2y2buml37GpNk8DTcKnOZBrPm9KGKJ8AlE+UZvGwdmwZM4ppd/KPXrDRTSAvtgLzqiG\nVO0RfMkmDngv6DSQR63QVXfQ7X1tI1VJcSzIp2FnlO5umBtoXaQr1f6iQLjZs8mHKNN1fbisbV3L\nkiGCuSBWjdyaz7i3nnyYk48bT0DCaLmk04mdPsi84JnyqcWa5HEqD8v1EtfmKP7KCxyqvL6jrGdr\nY2QrX1loreGJp1YQyZJ88Lde9IZlrVYG7X36FxaYuiTpVwyV0lodctAqii6guogpO85KUTYtLiD8\nz6r1LkdsS5eJtVm1N0V8qPJE3B7E5O9Eg3rSsAZegNJwfXmz0h/KOL7ee+E9kESRKPAwzZ1eXpjo\n4C2PK+Lp+RhF9n5kn9ahWn98OsYboOQ/+Vlg4ObgQeIu6hzKJ9jgtuWxYVY5shh7Jrt0uV7Ozv2e\nvnAZTy1CG+AMaHYhJVCrk60hH2jHdkHlRGewtI/rVzCQphSTu76+MqrhzPFiuWNwGvg6Wkz76LLd\nhfcCd+meSIE5pccdbl+mARINHJz0MJdp+AN9v2UrsfZHTUOOa197dKapTQboB938J0Vm4c9r5xEC\n0WRR7MoCZSLvTdcX9g91U68eqZ7aZgO5/oJqod9jh9AZDcjOZ/IZEEUBdlJN2ygo7ddcNiCIpE1/\niePuIMRKEXOabn+Jezy3oVmDxGLZMWCmCtA7SlmqKl+bDtba+c1jfk3rwir0Gc24AQTl/8/AiX3U\nhJTblGzrePrFEtjyEPyRKLCey9jkUXrRCnIJSxb3niKARYGPop2ovE37z/rUVgTWkWj8jruVtmUk\nXDa5ugQIukRCNmF4DRWY2R6KcBoaHm5VD7WsYZHIJKP4fX6X0xUFhGYGx2gj4VlXKa6ceqCBpmlR\nY2Yh5U96Y7N8lnKjQo/1tCXe7lQclT/F0y6KMMUbMdHp4fPwWIyBj8PyvP2F488jZKoaYDcCBAZ2\nFzAB5SJ9UtxvTWJ2r7LOFU29HmpRsScH+gg5k8G/675wfProbnZ3vGj83QtH1cvEl+BkwvWj05Kz\nu4d/mYBk6otvnaXixVDPAz/V9t+eNvXRwVNJ3mcfQ+DzZ8EIJ/yws4jWIkiSofX9OxpLH3L1BbA7\n7UR79P+vuAW2XLA4/voxPvt0BPlz+7oPINnLbEnB3HVWY4zM+EgWeBPAvZEkq36WAZhUBBNguE7a\n8RtT7QkNQq5ZyDg8G6KuJnpx0w+cCkCHtGWTV8maNSJha8Bnt78kTWeN+iarpU9NOyzxGbh3tniz\nfdzfLr9gC2z7ZDK1D3NObjjHSgBGOoPQ8zbZNjIRvY+3m6FqvjcGFJw4v3EallVzfNEk0eJgbrt5\n0rMp2kwHVSf/vfKqjcIHeIC8D8JG6DdmSQr9owY9/HqnlzR5liMglbcTS6FXDgmcLu+iYYFY28gi\nqFNSo1na61Urj23WxbaWilZLtC1U0TU7gS7GCuctgPqLDKFO1gglsegQThvzcuC5bwEwRlU3q91F\nd2p+3+bdCCne65OxvO0ehShiW6Lg+NgoKVG7qfTwiYnE81HF0ok/tcaZNbE709lTsFWC5fIF/MER\nVg2+dV7U6+rJIRf2tW/Pwavee5fm7VAUPC12UC6dZaK3h+YowDeF08FW2raiLFxqZjDBI7TWFZ0H\nlgE0OCIY3aNCGDGD5lhpZXuu5IHqEIrSKrM1p0vl+PZUNwzxcr54yP9/GvEGNovVn3YSTQaYB3yU\nMdTUt4B5/l/48spJ9IQRZJOHNqo4sGuVsLADOy/rNUTcWrlHcKgT0DiALq9k8rvybuyPaMmTKkvo\n6QP1WR0m668K4o1bSzt0rGulNFO1jk1Dp6cffsvGPPQdaLN/J3MNpUcjPMOpHBLyGTB5OqG/4mjU\nGR0byR0Cymms9sl3FH/LrcCbOEyY8FxsvPhszWsKD+co+nol2ncq/5AGd1Yj+E7pPniAvEi/hEuc\n4OVUmFlFYInGD4BlOQ4z7I+0hlGZFj1oOTrUsy1FU6g8j+6m1E2quppZMIkT8lgtWyT/mG+E3j+Y\nyTjtYgsbRn/oerrBrKpvvS3drB6tNlZMZrOZYn8xWzgC3RLspbE8JWwrsZom9BJG1f5mNF2P1cDY\n1foGVSlP8cZisVdTvgY03D/ummRYd74ziD9XcdWpWqYWeCk9MtNUuQRQnisPwsDyf6Iagbu8mRNh\nn4FglPLDfVH04Qx32QoA6E6bWyHKtStBKy4F067MkUQGvBIpLfKFxyXeG3zDRkQuj4joUnzGTPD6\nTFaSLk++kWojfrkMMF/LqnQZ4evnUMmoTH1Knr677TbVuDUTS2VQbRSGuo33/AnFJJ5IVlnIb7JR\nvdHAIG8g4zp0ZE/WmWTCIuOdEGmsDXsBGbtZJQbVHPez+8LOcItfUC96XH06NYNEZI/mH1wGdBNz\nUbnCsAnd/JUaDNe5hgGNc0aDcDfpgNVmPPTG5itNB1SjFzSZbsw+dqkjOYxUxdgxyqlcA2xAz5Rl\nnWuA56Icpx5LJgrYk7NaUiCvbiRjQ4JVAI3UQfibmloLegVPOu0WaahNR5z7gt93JISTsBZDOdJk\nkUX50GH3o+E5y2s5uQtEHNVzT0/VdOuuolIpCU5aoFcrFR5cuklmtaXcpJn6CFDQa1YzjoUaCnKe\nnpeJymF5dt8FbhIpA8PSuo0aBUq09MODdh/ZRaotvwLbYMDzWQIfKj0ndZV1nXBFjD4SQ+HoJ54U\nunuE4OZbTfvcC7ViY/RqV+Xkd/APQDwMfey+cXxqr7guko1eOqgR94FuW//L9CD1ZKsEvXpmRJdX\nBqYyUW6GK3akL3uIfIQCFtwyGi/BfEVu3rAbR3yirvflkC2o79Wa4BP+zh3tyGglK0Bvli6iar+A\nX1DA/dkwf4OqHuuG59dpNE4p/om4LMJXdl6SqXLhI4N5WxYtX2Px7ooR1NSZJl53yzBYZMOuzaF/\noaof3V2t8hYmlrfqUyBusIMDXGV41H5pi8vusj2z+i84D5mMz2c8T98Oa1CJKdCY5FXja1/TSWDt\nD2rNXOtcZgKzLQudXyS3jPb2TCMq3jOBycBDFH65nKAyGIFyeTKPn6cIAJDkBuSl+0bjUg8pILwC\nNmlAfw7DE+Eiq8aseLP9HhlVRm23B66+ryPSlSuUGIVmrtKKhWS5OKNDEqTMGEh4aw2sGNVVYvKS\nKbaGhWe60voQWV2IT9vuouA0hlv604k3/EwY0gODPnA/L93YelofcHaEhQEVx7iesFAVqq3KF2ue\nfKECodO8wfwW+RnycXayyuWlb2UnYwFI2AUUGCWpKShmVUarMlQKrWrIhTbO+g0vXa7E7zS+9fgJ\nWObDboS6oXv3rL6aUh8CdHvmYvR8QdSvfQvK+UvouZhsqTiycdhIO9oHLN5xkd4WWxloyOWerSvq\ng8/d8gOPzhBtKlPnJzkossrJkFwt5Y5+O5X12/+c6/n4WD4ZOddoCXy8i9kTQ3C5lp207Hh8bOmM\nea5HEgG4SoKB7kJtEIB1+5Ylct58MZUcUaHt8DP+uWNMSnY77vn+3RQm095pjevy0+URNb+7rW+4\nf1D/G4xH/mtDeKGQGekaf2e+KUEiKVb4PmHoTINrx6Pv9Vg01K5cEUcjJeCDoKZLy4NJ5cDzQSp0\ncPt7sgk2Up2jSOfivtrO0Yt9UzS2JK9RnBrxR+jG0sE8Zbi0U2UceMTAzYtt/pXz5RGbTXlxns9a\niforlRb+rHpcZmBqUbX9HMaGj3A8EC5aSERwk62OvM48On0A0lfW7ckac9U7bI2UeHUVkgbsLi2Q\n4mCjKZsKM/64VwaiUxvf9D7mLGgyX+4UWKpzdIXaxzIjlaWixYOcJEkwDwe+8BIlMru9C2uZ9+MR\noI4sbmHJOyvASFf3FlN2zZCEFPPuHoiN6H3y/IZd82q3xCaLNiMiNxMCRUgIHFwWdHt5r0lcTTdU\nh/TssUxGaa2KzM8lEo7CUkgMeoU8bWjB0DkaSXtusExrM1uNSd1l+eZsOMX7qzzJPEZeCatCFhK/\nBkWBpVm9vF4v3gNfhsVPSfkH1x/AbGjze0ZSaPJiPc4r7NcPoFZE1nIOIBABM3sJxT3mv3COVn+M\n1O/O7vXVwaMnugQOegqaROMi5zZn6fGJzhh8/8IIifmBei7ylRRqhJaE1IqGvLY8iw2CFgUbCsEJ\nQTppgPJNm59zRAa/4LWLZvs0u+wssdq6yRTOLomawCTb2+YSrSm4cBaef2FUqaY8z361WXyqdFpi\nCbmgzpCBcYWBcX1fLlSDN0FTptFOxlVLEmS1xO2GF472l8hQLEqEV7vfJvno+Z//8TjoVJ0mPAT+\nOodKgQ7+RnJBzAHC2bdAd6Wr5Cs1KYmxfeO1w8diEQk+7UEYEUfqDWOnhHM12DPdhcstSug+kJFe\nriF2f+ULJp0BKy2kJ/JJPAGRt53i1m2+71io+LzZha+RdggjfDKJr8EonB3mJTv6Ey/YxtD7/aPz\nsM+MIrZOFx4as9lBSVDYwTBZMvxLWLSdJsX/hZ8uFDZQxVyFQxfvrth/I158LUm56IUJcIyHeitQ\nJFFKCU2sw7McobUMR3H0dnKt749a5TFcp6Pt9OOnS0Kj2ZJ0zW0QRSFoUjeqWSlfVCVDBR7r2BpL\nG1tjy7Cqfqv1o53HItNjtOM4y2wZ53IpX5e+QjWiKzzYm5bi9Zw0sqCkhWYea/Ikvaaj5i7a+N2Q\nGUDekF0yxvDgpNKLYReqsEnViPjfOthZsiQ/ZF4f5FZkimf28UGqFSCYBhoyAoZCObcuokDZHSc7\nqbD8R5YbQFNmIhBTfo+LwHmZS9/r6GTAHKzt3NdOZJ+BlaPdFo9LoXpZFl7BISoGQNZp+cqJmxMX\nlElx0u0GPPHTNt6ilQWCwLZM9xFAQ5dH9aplVb1fFAdsjXUEJusNpQVa0ohBX/MlRqEA/ok7gkYU\nRg1Sl+gij7mTVCyaeKWlDR08H+GjsgnqBew6ptWyV+BLqxz1pIwS1TPPT9g2LEF/AXbgalw06Mhr\ngWyomNUgaddL15diQS7eKVlYwVtuO9Dio3USx5ootyq/tTQhrjkS124tYNG/4ozFsQy8kXW/28uQ\nVj60rTnm/QkMkD33zu8zBwXYOZ6+BhuSbsTph+WRnBagf9hxLJXfKYBbTirzgFHDPcrp6unySw1h\nXerYV26lMrK/9VrkVxxsC8LW/JGxQG0PHDl1cLs6YGseHZQa/ShX8XE7AtAYkJ56xfWkYduswh8s\n/xwWm/i19+VTuedahTPvXTRWxxvy7nbn2xV6LaUFixHNVy9k8lKLRdXzpNX1zCe2kB53fgz6XHnL\nxhN2WaHHuNFzUWCv8NghHah9YgCVwcCYh8YcQrqbuhpjVm/NprIxoZuqSuN1xRy/zfwU28FCMI0Z\nb3PwLG7AvfldFgTZPwBIWcODxzP894mHaNG9itsQjhW0ksSSxvYweLBofWtKhxFthCxXRjQYQlAo\n14uDlf24ruW2lki/ARokBEZ3c9WOn7xG+8a0XIAMh2Ze32MFWm50mba6Yk0jKXF7aZbfuH0MHbk7\n9U84WW80Rl7zWp7WK3mvHdR8kaFAyO/KFGsmPo3QwmBX3cmq0huPQVvvq9BjQq8b6DVoR0HRMFh6\nTS6HT6Gw205Po+wLRbrwzwbq6pUVKfHCySnZhHc2j3EXi1QjMy/UoGuW7bFHDALulwEzC7c4N1nP\n58hDhowIruHJ2UgjnpJYzV99YlPGs3RNfL2D5+uUFvkflxDXHnH14Ay7+zHIxr4HvncQGHOr5Fu9\nhSc76XDHb8pIGd8IdDD2aKLshPMrNF7ZVpt0IS/ThWkjpqI4HAwa99Oor5TJGkGnrK5nXCKl/V4U\neaSxXvHyD26Ry4NGBk2JasO8VqLSOVfuemwekAA795kOriGjdcU0hRZS0UK+YZIbt5M29s5xxQvn\nZgNF6Abotf57E+YP1F1eVCsopFPKfvATEpYTvUxBFxW4h/29TjMvkq9uvfS6ys+XhHfCrVIsAwv6\nr1aIxORiIZbULnlflxEryS///gUFpreGJpoPgLIzo848gKdf1bu+I5g+bikGAFcVIi27P74t0Q3D\n2+8X3z/i+DPkeMw0IwTCCxYpl/lnyV84ZlOjbvO+yak1dW85HmcOxI+Yx4X/aTWBxL1E1JUhsXny\na+5tcHCihqtH9TJ73Dz1Ctb0OQgLEcfPmziIrLrdgcEZv5fWYBjEp1PlCpqXnSKJik/ADIM2x1ZS\nwTuWTrBZXoTUnBmLXJvXwMOS3iK93JnKWLmogkAwQfj4NpYV9rRnNTEG8OtcRO6x+ScjxM3q2WcL\nNxMiwGOvrqy1PNsk5tqJrr+C/vX12LjRSBmKiu6xD3m84Sfo1ACMuimkJwSHDqd1FhpqLMWkEHd0\nTlg38sEgiPxPzQX8nNNDU+AP4ONfUTzkEdOKcKZiBzccH3Dh/3hMwpWY37LbN9EhqqQ6iS69/Nff\nI8jj0x7Ekmf6ZhNztfDvMTrHdMA+xBQdc4cL3BT8LiOLzDV8rROTTFwn8nHNro4jnAUqYf4sOABW\nwXiNohg3LLOwTe7gQpSThqCx5mSjmdOvwSEZXlSaciS6BJC8lgM5zJSzOURYOSMRl0CzfSVfiPjL\nl2lYdpYudLJqm32t+mntGbSc1wCqRy6djjjhFUadcHGBtn7ZMpcsGXeZ6PRYLYuWEiFrcxdeCBSJ\nMa6nR+aAfqAll8jQGr/c+1QtM1fgbtgUdnqpw2qWuRmW6LDkmuIxUHDJ+RS60L5zrYrgI27cYpEK\nUMcf/Dju2oqap/yP9KN2nvWiK6+OwAuvG22RDw7VIX/YU/KvVgED17M9VrSaGN8tqaHzNTGM2IDV\n7LGeSz1D15I00bC7lsM2GgX1s0o62Iwj6j/6deZ1ZiCwBtmmGzh0KCdzK/qSxCMHjC8qBAR9tQhk\n4mPouLUTQqh/4hTq4ku1SbVCqI3ZkjKytxnuhq5akCqQrq7Xx4JIaoeSH4sVIsXN3sfWGc7Zdh7T\ni+pQhzqsbkDGV/HO8zi1aJ0mPesChbkgZCI74tqxqtLgFFdUJepfQtEynJ7h7I8ZkfjccYsS3Ohl\nNdLTLxug/y1cWwWXQSU0L5+Z5ElHcoJH1LfwaUMungbZ1U5u/8Nry2jURK8LFHaLT/yRSn4Pg9fw\nuejDkeRSbGy1MMesbWXCO/uT8gOA9JYa99/xwuim3E5zGDUMaJWKg8WBZVyKEpY+KGjBFJOUrtMj\n3rcJNY9d4slEqcn2wDzuKUIcttvsC70XG0awDYSDQz2CYfHkWS5/uSF4ALpgjLcBzwC048jZUueV\nviWS5VudzFvxXLkz+NbWjjiE2B1O4wAGgrcimGJyiRUvU1wynIl9r0Qqr8iOCQSA/p+8qQ+0ZvY0\n8OWok9uq4V9RixaeLSckAEEGfom+KfvqiTv6AE9kw5848t2IU1HTaOCavLmA4A72Vd8XeLeqVW3U\nORuyyYkVjVxZLFIiWhx6jaF1/WT5jDluydog4xcvKVb1cwhxfvI67EmnSWsmK+xxBxA1Sdi7WWnc\ndkJLSWmQspe6eQDylbt/PkPSCYJz6mJ1PlmhwCT+ocHTX24eu0oRM0yobEJ+3BSUeR+k/u097WQl\nwq4+Q2wmmZFNmiX5L9MdI1REqstsyRBeZ8mabMRSV3ztx9WkA0kiru0Z+odw8re63Z1qNv39K66I\nTndTC3lMVLOU7jlDSzpqlgvEx8YKdGwtWR10ffvObGb67Bs39n3fup2O5Qi1hrrMjj0BIo4In58J\n8LGbRJzf7MFALj6nevF6KLhs0HBXaaZal5m62IjWRf2V4Mgj/ZGFih8cnTIM6QHcU/FgUQFPePxJ\nUFklzOMkiUFOiXbKDmaG7rsR9wcJTuZI4OH2Bra0GYY0KpgYcjeZ8INrWeiRUHCuEdkTH4UDhyp5\nkd8qBv1XPDMPgRjQcQXR6su+W3Da+OSeSSDEz7Jqx0ORWQwANUskxJVyC8b+ewdldz/8gCmU3jLn\n2vZKZvfj6KayKRHK7FxWrJokhNjnuKUgWI84ehgXQFuuDHRJfsvH02d5LM9+D71xfG+2+9DfEDEM\nzsiw5dAyaZX1pVpkXQoCukJgESE+6q1hKi1Kcz4k6hy82Eu/uov1cLMo7NeNKQrZHJ6lX//AvLfO\nTUpHyaByz2otzZmpVIAOL5/ycXUC0C07jfBxvL0sQKTQ/J6GtD+DUSWCHZNSFNqTz0Sf0KmVIyEQ\nt4myxo0muliPnbEu6LWT/DYOv7SzJafk1TWWvnEHUrkRmcqohZZisBgk0gIpe9nRRsFcWAwQ0rZJ\nr6DiRpm0z5qDe5QA9XauzWq8kyavTYLromTgMFc3Y0S0m9YSuzqOWbuo1Jb6MGD0y4CrD4Wos/V1\nnsoQwwLEOtso9goiwNi2drd9k2vm2wmYUewf6sazlvghzXheJRjDrXQIclJ+sQx8ho5y2EA8Ic6t\n0rw9KrHa/tlPwPMY8w39fnveTmcgywMtLX7eEIoqb4HpKpm8TqXczal7spNuWhPPe4J8DTU9T3Hv\nZFy6kHLsLwI97vN58c1TNYlnFDCCOmFUkoE97iNuWXejagNdoAKEE8wtPSGH8c8YhdCepyPwtsN0\n6j/dy7KxJmuxggcEYvS/1HBYgQ9IQTgGeHe+RJtjU0abY0fAFTcMKKVkS6VdimguNoiWsWPhDf0T\nSQwbwNsrU+9Wtk+St0Ib+B9D5sjQuAl60CS0arfZtMR1ZGkp2AlwqMlXL4vaFfD6+0cv26jC0RcC\neuQ631uzlivVyMyfaJW2a9/Pad+6aMWDv0fgd0t6wS3X7Vw+GHBo2jfevvFiiEvaY+OWL3LXWfDe\nWqMN0yntP5YqHFz1reseiRFn8klauOW63/7kJQB+WG7swSJKND/JGbeQfPCFMEOrNpHoGrVMfmIr\nViTWD9s/E+x2vSdqInLC12+lG30LYxhcaKGGtog0wRMOFziKHHGkxpgd6cIFalUPDVmH8D4Z0qYw\n0EmoZQBqSKVUt0ZAC6rvQUOtKdJHZHubC4++dutZAVZmAW5vZrIf5aPYUYMG7yyuExnDIBf6o+fO\nUKV4G48uKd6r+L0b/4kVosCyhh8DQ5xPibzLg1awGZHznPhqhCthPUNnuweG0I5j25iasRN4R/se\nvidCKbQjy5M1KyhWL2CFqpN+LIkJ4Bce4uGoB8fJ7Rex/UjHYfduoWEsh7Lz+GgUto4MVUyVg7mk\nsEZFgT0oLlmie4VzzARU+ngPfgaDftJgrNaW92UOpVa1AxvwLiIJCFPT5oNV9UpDfoEBZnmAcFc/\ns72pZNIMZ/6PBd7MnAAE3JJbkIUvr622GwGoBDkHTSTzCuTXdcAmpuGNS6qzrsglL8GIEnq1azaB\nfLcxBq20pyiPaf5WzT4O3YJFPde+jrl5bIi3nQ/xIkrPgyaixO+9g5ws+vTuYlTdwV+aw6Z2Eg4L\nwTCBB92MFE9JDAfYEFsazggJ4c+CFEGftfYuh6XosmP5Fk2EHNRIzIy1GE0uFYNCr0HrKxcDU8Gw\nvwNinbs1W26C6/mfEoCWGhtBEgXvy0fxpOqlczkT3MzWVB1H/3MDHhQhbdjaKdZKrhbyPefTM4mn\nRUwg4H9UKqMMxY8MpelKrUSjY5Rhn0E3IibFJGNmP1Km6DfK6Bz9izzj3SlBM2tuyc/pK8pJPybn\nVY7xZ3bAQA9TCSrYluNQ7Ku7eTeKTnQFanDf+MV6WzCmwj/zQon1Rytur+gV5eyhsYV7rt7bFu7h\nYnzt9cTUCyQWzC0jEWUqDg4dVnDKcpRaT4mZghot5rDxL+LgRbGj6bzvgkMabT8xpkNdlGjJN5n6\np9xZNBlZS/KMEkqIjAI1tdGO29hkLd7oqYF274ELPP5l1CvPBr1u0PgGilPa4LGW2TNx1mBux49h\ndqlUUJe1nIq28DPuRhe/YqGf4IUv+bihFqfjdOoPzEDxijtuPjf71rL2EOjqhbOBOoJS3H6yjqoz\nnAgVC1go6wodCenXIqAIQg78k/lP48fYaqhu4Yaec1dXXV8UyR4Zw2pdUFtBABUjWJbl/a6GZUg6\nFQ6HA06wwYXpfwivS5o95dfQvMcshAMquaE+Uk7t+zpPrFxLnTITOGafA4+vt7+zSiC+Nf0FCxTb\nMD3JDvplk0ljylaXpR0/mYid+K6EEN+gcyb/eY8i6/xTRvPt6GmdZNHeibD65PVZ1rWqBgXTyM3Q\nq3IIpyPJkJzY+dHBPQHcnUE0Yn1Ep7IXmnIy86737wq6h8ed84H8QzVuQtKAjWD0h6Pdq1/8VWKH\nQf6Srovz5Y/B/hEnFO80ED1zrw5kP5jGWIK3lzHgPvOuov0d34iKEWXeDA1xSD1h5lLNSBvtMG/n\nYgutmfLDuIKlg5CgxoWNuDOxK7CQNUvrtTlyRBS4cdzErCBugBmCyvATG+sl0iNPlgaSxHyTegVY\nCF1lMIotYzUCPWG9W2AIfo9xEq4BInp5seaDZlWAueRWsSVfIMuzGl1plry/Zzis6CVGs0QpntlQ\nmXpu0lGftlcasJEbC/EZNjUkOcZvVxNtpZdpyFKxmmejHkcvJmbKiZt61rr/Y0W3No1XLwbUfIhw\nXObmHdAFsLR98O7EhfpIs+e2Ii5vn8lYDmRa1gYK9IFj6Ikcd70mI9RSPhgpQgQn3CW0vX1DAdVv\nHYU9u6ThKMw6jlvFyHneAkBJ/NueXZenXLAhy/NmfEin02PEBq8MvZGes3LvIR6fSlYm2JGR7hcR\nscNtTbmuyI20CfzH3330djQ/hXf+61PlvpLlebaC6yhnnSQHSITI0pUzl9Ao2chkGfLIv4lkarzf\nVvGKA6bR4cLQ7lfMSb3jiAK/QFow/pQOHeoBGpiIJKnyfBfm5svJ35ns4KrF2u9yX68kHNn3GzD3\nHgV/iy4tNWUmkFYbPbbXyobnNbXNQtZOX3Rp8AOG9/Oo2SEnX0DhJ71qKmWpcbp/1BYCRfkXHiqC\neBMAYFNqIsb0UFGb4p3NWy607mqLirPXn3hFmV2MsgJ+JIeBuFIfOEt+uzSoD8KC8tMwqJybtYlH\ncmA7TusUFo2YYZJEMC4hhSPr9Vf3cxQ9FdrWuhoeFLtW3XVvlHvTawERVdqJGI33qy29xmhJ4nz+\n7/wP/l+gt5FG93Ni/8IEm6tB4obo5u0os7Xg7gmEy/6HCVFtfhNkqZyn4LTI6fi3wnIp7HIJWPkw\ndHPnAy7Za9wVoP70xhJbmtieW3CdDLEwW6k9qRmo91m35ph+NUrp6it8IEB3jqZbiqJOrGid/bGt\nDRe3ZwHQlGMqCSrGYYoQkn2elADRgSBi+SEBmIS969msvSUdcffrzFh1zgziOwKYJ7A+zgPAV5wQ\nmRIYCaCueGXcq3+Y3dqX6Xz+q2Urhdjug0VcDF4LTRCKJ/z4BoxHnhPJ0Kg3E/XNFOrxbodTy+V/\nf60jkELut0u9bDLnWv7CI3wgQxfZmbDzWDBBq+CqS6nFL3lJI202FIRh8gHqVyCn6QXFS84Aps6o\nsVsDBM31a9sYV/0IJ2eoJXSJWJpMa7JuEJj1QpCWgKPuFUqL00RmWetqTT4XnPXnNJc2l60XGhY+\nAsHEmLA/EUP7dssvL1l19DmPl1664WI9yN8JwrKMKIQIyQpp1lqKvA/uD8KUtUSf230Tt66HgLB1\n4j+idT++O+33nL1aQTVSDABPdZnV8MsvJ5W0oJhM5T5tvoPxWS/TY8Ok/AcSZOzeVYeGdZxwfQ2Z\nG1fYvu+0B592E4wGHMgZbomABjWALpDg+oDRscuswztBlv34wRiBfRhVq0+xjopYKqaMfRrv7Add\ncCpEx8xtg5/R5o61oOJlc15EqnvaFBqF6W1GW9eHl6mEvxDHkpVbvS0Z/XxySSsBQ8B4OtJjUiJ/\nLgEnTM87J2olOEnHHN/z2It2S/AEBFqRaqCJTXLb/vXe6gKekLNSu4qO/5RJpTms5R0vX/nwTvkl\nEoKqq2fRO4WVPGePAka7NO6i6uTxfoUXzyuckHg1WMvjj2uoW0aucppzCJ18nGBtTTqK9/hidxWo\nZypCiHytpCfX3S+v3W8xlss9vPeb8XoUbPytxfgNsJhLql8YMcldO5pFm0jVazvHJe9caPj65/6a\nmQNi5o5KGRI1YrgN37NHqaYSj3ig9w5K5r1vTpTim68ZUVHS2B70gveIPxtcfJj6MDjza9KDgar4\nL2j+0oCV7N5QCh+3eXAbatOp9GsqEK8NyPLDCMsTtR2UVyQpbKmXt/mmPW4E10r+zzMfJ6dDL2lA\nedhHtsi8mbms9bRX/Cb/S9SduVk3vefqeBSsK/lCxd1Gm+QXnMErrXxnR5MXNN9L8b0mosSL+4s+\nEiiRkZ28NL39wlIq1dpcgq2SObgCPTEHfwEkBROFvzkMC37TQSu9S55uWIs1FuyuXNLdBELb2ESV\ndDD+vw0deBrYhbroR94kQgadZshZY9xcmMpkOPQD4KJj1Pn9KyDfiFj1taahXAewxkfUfjsZLNGY\nj4Ufii6NpDrTkb9+WFudZyVk8IJKiDgggd08rG9vKD9IY3z+RAejotDLYRUnJHNKM5vFuzrQceYI\nE6Tu0LILRbrMcJ9tmkKRGd7VR6llDLUWRXGQFI71zJIuhxIVnSw6K2TdqCyvxxXuhHR6BrdlFIW4\n9RvXFMvEbB2Efao/7VnpBqBp5x2b5m+6iv59/EKuhg4u4Y8peLcZ+Zy2t7kQ4FbI3hmXmVxnqDkx\n/mkTxs0WH7D6PwoVvsKwBYnHonDmK161cFu2IMNNS0kzTM1oX+QFDdm8eCu60xr8VrnPYbIBO+4w\nMkhpp4qJ3tFvNXTiz+bKC9Jhmt6A10MXwDwgHUfcEl/+8zM2LF1wQIFtW71HHyjlTrl8ezgvRdIL\nd/tBKgK6FOeBmfE3j3rqlvTrC7kevvf0QS9YvHUUEBVwG/Y/waNnJizM2KZTUGRpTQrNJ8b+y99j\nepvmiFaaadQMB1pMNQYgYoxSxuEnU15ZhjWo2BAAGL9Zr/ffyHkHoBcxpYlz/iI4IXPrYCGEhdQp\n0AUwN1/o0xWBJJQ4rT1vsZOGbAMTJIKFZr0UmRKDKiYZ/n20BZna0F6r+KyX6lQ5I8WjKWsQb0Ur\nywvSrYTaMyFHYbzNuWm5oEAQ9Xz7DewoFdbX4fReQhA197aZ9TPNlFW/3EONWP9RksdrMk8qILgP\n8fx7K3mt3OICfTfeW2O9P3/ge2LbbShr1cNO7VAR6H09wWhTRwTSxYTIXy/bStPGX5GrfEswk/CF\nU1VpgaTDux7IoLgJ854i6sHqVnUtv9g/yHrtHg1maXOyWelyjK0Obe1cP+98aWZkOSQehCaJ3Pdf\nyDYQXgOINx+M/oSZrRSgRxlWuoagwzJfNmX37nHCfzajxk2lagYcEq8gAOWe6qrQyj1YyYtToghK\n4us7h4un8UaPqBlfdicmryRXwhbFdEKcqhJiCFfpce7jAwWJPjIASAEwvs+2c4dClq1d3impKYP5\nRXndnYPvkhD5HHyrHqc40lGTvcw2HG81JeEuWRVQ29NcOrYxAdZDM3MqajlNFm4KPFJ+Hxkf52F/\n3dKkvR8cy2lpV25ExE13xr1Fe91exh2KVl2IexsicXXmFFg9Vp72h8Xo01Q8Pket6ShJS9tPEh2W\neRtSyo8ZESXtb/eYmlS3r9eud5juW5xJy6oIhnMMpFVJ8l6uxv5FaAiJ1ou0EgV0ZE2aO4sjYXH/\nlaZjJA147M8OsNHMxQN7BRS7WTiZsb/FU/f6R0AEmkkVR/90sKRYYhbs9/Ms8t9vXl9JpWoAVsGx\nm9OAOq3DbfkYT3OO7YuerL1WuO8Hxfa8GjT6+tX+uOYNjyXqE89/Xzuk7nZfPdUu6cuCeOv+fr/I\ncAw+XUXFY9i/EIRBDRjeI1BGw3CRnlBTE7UUmLRDofAmzGNig+mvmR4GTX0Oy5dUisE0269mncb4\nRsxmB9BW7O8baRCKKBDNVWCKwr+gmHtXhVN/Z1t0axbdVnFEWNr39f6T/0oqPp+FourFiT6onjdZ\n20RdryNEaSOdlViXMPAbNvHyEyRNI07lZrTKLi97KNn4Ow8ASDwEYngohaQoWBjBeyzKvTUYKu45\na0yUeuB8zIuY3Yrp8y6+QOoVjbMCKrJleJnf5FnOaLLW/l92IIofSSy1h7xZmhNK/MXcDvk24kRR\nVzmT2+lbkK2YQC/Q964uZCgsHP0l3YSIAdOyHmsDy233o0GjrgL+Tfh2dHh+94MH439aJw4utIjR\nAudhAMZsqLck2OudCxFR9GkgCsLyR9MbzZrDK01gDt94e2qTBEIPYC6QIebeYJCz+bpTA8Qp03ej\nDkBFKXUUn5wrXP8exjyoIpkZ81yKHXpx+nnRQ8t8REAa5ypIf/UOHBalatg6ZlJW/PQs3YKcYXBH\njpMLoQn7CQZpg6FcLCTIh+twsBvnEf82dwzciuzXY5IOPHDNd818QrYS3FGd8m/lytyweVcBWWfq\nKoyDlZvYKNGbIWvieucWEaIL/GpaV0nej6it6vpkx1C9mcdcpxygg8EwU+Q9TqebsjMqdMckx3YK\nPNUJr8iTsrX9migJ75RE6+w9+v/3EtfZC4hW9khYG4ehiG+M5NeYVqzRaSnGNxTsZOb+cuV80hpM\n5kbrEgdq80c5e8zHdush5wXifTorS0vHdVzUercyr8LwVJDJClHoXRguNTqbGzfRO0h3/SGvKfXv\neJAFBsonKZpRfnFNj6KXfSEdlPLoKKr2x0HKnjYHa1O2nFSaZezwMmf4wazBPQ2DvJ9Oiv4B+cSO\nFrAB8wovlgGSC2XpFWY6/J0v8c/0tysxdLZwUzGbu8dXxS/imWXGTMMPQdZnRxoPaipn2kWbYnTF\nnebNrre4I86/E/MFT8Y21DhVJNzRNsoxMZcsN+xeVxgYBgk2vEV6p2llC7JNVbDqz0KsU/V0rsyI\ngQm/Dv5OknCFOuVM+YOoAwiQreo3nHHdWbkeKYS42sw9rv49O4vtL+QtJG7863L8dumpAYndpX/l\nz1Gp8vM4OrhYt6Qn7Rephu5lrDK7nVzVXDshoC1XzCI5b+aWHtB3iy4ktbPhgW1yln18ubd3/WsM\nnWrccDeq78IHQn/pf1Q4C74LUgG1jkid0dyecwvMHbI2ps7Hu6/9Ythx+yi3qypwYayAF9fPpugj\nAGgFBNzwnSFWMu39vT/o0r+mz/sOype0lCGpF/4pkMi3rVRSG4O0wKL012MrdqPUvL8lCYvmJ+E1\nYJYQR1F3oyY8qWklcIMSIXeGynLJrVEkY8EVdyDlEAbLgd+4Ytzbm0tUG2XHH+r9NCOZkk/N67Jq\np9I+cnMfr/AYnJAzABJPqwC9dekyl7KK4usEpnjk4Jst0Fp+pfNlYFododZooqmxfvkKJOurqkwG\n9o37CP20uKhZzJnqTGNL0BC5/ZrvTabulqD19dFpDdg6BGd4vREAAd7Gqp6jxBTvNRQZI20d2BuN\nFBJ+8CziDWG2CsBdoGlI7NdjcgZdBsO7bvCNqHFa0FqWkby7BKVuAVekUAfX6RitgHKugIXhgtL6\nsKnV8v0tfhlaX1xc2uSxePTfYsMtMBEJrEypxsk7y+Exof6AoIyHBZiBvov/hxU7bSHu/nrYNAtZ\nJOYqBNYGMfxaAcOYVe2Vg/UbCHFlV2HIZiAy/gD74Qg8icJ8RjS1AGd7t3Dk0zDERWlinv09DBlM\nOe/RudF8dTfb1DI4g33vSu/OMHm8yscI3GVxGRciorqLX9YRn0ji9noSlSo9389QCFCp9RXOEtub\nh5gnB6vSUDvEZ+umw/C2GQsl7N03vY9FJEOftg3+o1uQb4q3Pcqa+C3kv7Zvxa0HYtc5N34lWXIf\nNnfbCOdcO45XUaPen+411pPcsCybMS7vYf2boFvZ5C/oFH2fxWLeYOEFJuoD9ORHIeOGiqq2yodN\nvkjolfq3C8HR3ywAan1BP+qtapDuBzcoZheHEq//WJnF/kqoQNkhdeaqUGZTcPEd+ZjArKCdPj8F\npfYhhpY4GrlPpFnwlw0oyYNN2yH9Ii4Ym1coemVDC2afnECWviSn4y8fQLYRbVdrdsgyIHaACUNk\nwyoVtTjt/lMYUFOOpEZgnmcn6PwT0vtrvcW/0wDZJFx8FT7Ju3V7FVxSoVhzWr2NgXApggby0G7v\ngaBBC5iIzSJRRAkwOibIhjQGupZxxESlvPAZfpeWXxnyA7YmEHx4EJy7vwEUvvvnwMK4pZ8RTQ5t\n/qgGTww6jntZ9YLCNz/REKPFSVaNFPCQvQzf2PNJdPe9a7OX+C3idY7WlhggbaCeWfsFQFq1n2pI\n1Up2Ju1qCayXN2bD25j0qONpeVV2wMTfA3/0PQvZ7NjulQy45kwFLhjrHKi1SZ3Lo6IsHy1W1lzz\n+T6kjyQDgHKEPxmgbKEePSYFw9m57IRBSB1lVL/lXhgcp3fV8iFAZbUz9vPdCXYkSA0Mnop9p9+W\ngXFiq9fxsGvjlhzNzacvJJ4lNuEZy/8Zl9ywYYRILB/hbw3jB6T+Sl7DBN0JfR623qilI/Erkl4b\nBmEHK10J5v07/+2OoHjVtND30VN83BbYkj0GCA3AG0xNTll7Mqce7tDOC97j4C2DJqkJ7bLpOw/x\nNzvjLevB+tOm5fHydrs1fHRGOLNpTd+tNaXzZJLicRPAQ3PwRCU/KhfUhD/lnwMquRemNah3+9J/\nWbDvDX7y5pZAwtFvTl1Fx9D64CTBMDRLvToJsHMW7TNnmchuf6e0UU3kSMZ7Qh6GBQTbWX3QM6H1\n891oVivzTN/iAvn7S3PCQMqWca/8EwEySxPLhLv/V+g2qU0vWgmRAwgSZGW8qhB+hKiyROe4iovT\nZ7f/ATkdIc/NU7F6uAOSfbTF5HtIKkHTtrRBh/GPODrZync/1Unq6XicDyUoFNdJO0otZpWg0UJr\nIm0baDbtDrMr2nxM3f5NWpkThFB7ogT7J6jP5Uk/W5gA92yUYXraImArkXpJIkzrMVUBcZYjVXAK\nby5IG+0dAnShjrYUMbCDCeWRqd23AQ+Gmib9SjRAvoyzqNSavj1SBCaFi+GWhUlDEzJRjcx8ucq/\n1O95KAytmC/bzLw19wV7dcHvXpYXenZdTj7NIqNvkMdEFQQ3W98i9NwAcYtUOEda+02qLkc78Imt\nEFLSJZ7EKE23BqprZuOH5UTGjH+bdjHnBephoFRnLuwZvF0sPVHLCQz6E11Kl8x67Lg7TMz/JMGy\n0QWWJno+6E233Lt27bt4uZOF4ridnseWnNw42Mojo2ZkS+F63DJcZlmjFOGUVnis87CHis7eVVVd\njVZWDDQ6Zn/wZ/rKAB7Nj8qRVs4g05fCKKzodda4WHnCVF3g3nZA47sdOjb1VGpJCwXqP2YcpkFT\nTAXPnPquxGaaGENiXmKqa5xdskfuw1Y4af7vm1MqI6lcPOF5TxhJ1Qtt53NI+69mG9IdHkpVNj1y\n/G16ztIE1JNeEtmB+BYO0mO2X0dblG9J2YB752FGSgWYV8EnXjP4Sxw5odQw6Wt5LGoLlfylOGcu\ngbhuMJQ7pgb21+gJh/ngTUpwzKK4Hcn0fA1ilriMz/e+CfZFP2IgWlQ15Yt6ECjl/QAX3aAyciLi\n2pcfzoq/Ic7mWuUiwcFzJPte9OngUghbbaNHB8SJIMiopXVGkfr1KtDxrZ0bsWfVaqkM++xgcUOo\nbMQ4UTmjeig/FooIwVWLCwUblGVHyWYAdVeIh3843mflrTKFyQwuXMISN+lQO4i+WEPWHPkml7La\nrjWlBEditPmyzJHe0W207fjznpN/km+Ne2v/R4elmY9pdqL4KL0ubbaOaZpAvlxlAisoaIZVPDq9\nF4oUjfoRR3053AluL3WEd8t1hWG+I5767HWYMG+De6VQRXGb0aE+8M4o/vBinyggTiXrkFS0wkPm\nPSObUf85seJ5x9gm9winqS0b1+5gIKEfpDNZNwf7r9+HUqvigZ8oPVsbEWjjT5fm2TgDLUbBVrT/\n8eMGSj2YLSsfViqir+717cLXHWH06yukH4WjaOXbulc7zkI4iHRX5DuvX2hDlEUCXju37W/7eyVc\nJaxXcJsw02ylBFhVwvLwRDiJUFT4s6tL3oofXqp3SAfLfm36qZJ5jjLjKeUwjot1eGA+NroRHqH0\nmgtjvwYrR5rVyVbWrYwo34eren6W2O7//yte0mey6VJb5UQPVQjQLDyFHJ8zSG/AiRjgwri3tDKG\nrA/0fUOdQGiz+RwQmrOjtDLah0oLdcnKNGdOuYgfRwuMR5kqO88aRVVDccmhnSjkmckLlEa3UbW/\nCCaLOdPOZVG43P03loHDBkump67PWIwSJufgTY2dzbjHQYWFJH4Q+HXVMJAaKwMREVUD4RfgA8lA\ncyJvj/zKyZAJEdF8EP0rk8ZsS+FplatlugSCfQVGudYccNSYpvVKtoiX82LcJs9S/HqsqzCrhkA+\ngDJEbI+8wshtd6KxUXstlXRaPBq/JYp4JESRJqGNH3q0MPWYudy5IU1Ex+Lx/WqW4Cyt6RXnulxh\n7qYgvc/1Li6u6wA2y1x1R9g6qBJDOmN95n40iDkqYuToeiI3oC54fxAOfE94As08xEGHE8kAaOta\no8l+uX4BdtrDoafhBf2VH9N+GTluvEe71ZT3DlKFjbKEsaA/9rj28XJic42JsPn5qkuf7gWNqSA3\nFkaQ68kOF/xwL8BFwUA4I1qpi84bn5o2gVQdLJJzvEHtIQTGmhCc685iDeCUbdbkw1FT3EXdEz7K\nAXzeVmsQTC3MSoefYgbwhcKSCniWMFXMwZCvqu1o0KOypwDjoi5M7wtwWyF1ssuZ/ERb8vFk1TKq\nAckwlJgpVQ3g2JcrjBwdIuAb6y0vpTto8iav0v/pMkDxrkPHa+5edxeg/bR57Dg9M9i6T4QJB6x4\nkkfyZ1w2jFGdyASCxZg+4obC4Xahrh5rvE7rpL/jAt6/JytixqGe85/NdmqycrPD3SpHj4HG73M/\n62NrImyUrHvAP/qdOGD93JyXizrcbws9HXLDfuK8gmZx0E+Q17Eq3ktdG6Im54bdQOOQJT4sbOhj\nwp0PIO/22O0nZVQBFd4Xi2gytLXMo/Jexr/IaEB+IOp3WfOvck/ycksR8uztlg5RC4mpYN3WvnWk\nebkIUPD5cYMCH55xQdzKPFCwCayAb18492wALyccze3xXGlUZkys4O/HRH1NCzgQIfHuZ2894SrB\nXxp20sVF6LGPOCfyBBGEGgpXlUGNgf0lYkUvh1XfD0U/PLpxY6Ms+fNecyGrWQ9Zboy4U7deDa/c\nlDarHQTyrSK7K96Z8gTxVpqWF2ltlrb64uQ9JW0doObxUxumbu3P+d4gfnwFzwxOKVzdeMyxe6ho\nV9G5KUKsBFPZpOaKb5eugVmH2PkBA+lWZFeHWTgOtJYCBZZFv6u9RSZ/ohBhg4bYVotZCYdVwtqa\n/z6XJaRdUKc7E7h7UU0qs4oLqh7OeCHJ9CIFiz6fOTG2ydP3O/+LkIHXj8M07BNjV1vW8hn0jA44\nf2gzojPMkX9n+D0g3kJXmDfyBJzwNG5z9hK2a6xXRgJSRNSGNPNF8Q6IrUJsBaTi5m3lrKedv+4a\n+kNlozrJBXuzvH3eArtARRpnLD4jSt5HAGRSE872rEU1XwbIxMO42s3NXr4zBQu92AdAFd6bfp8H\nb+zjoiUSdpFuOIqfAwt3fxSo6+1wwapPzNlUqHhMfKTiKqOukaeKPDs4E2PP8jHXvWzRb2W6uJ8Q\n59Dysnjtz2acTJCJW5hkHDIlnjwva90WF8hnAXeWRF1JN46CA/Rg0lzvNiHK/A7QSJo1H+8uRIpt\nkR1XM8bh3jWFkHTzVyHdNqPl8PnAjGBM2Z1QeXZJ9UgtO2amnqcO2uhydu4FcnssdGAo19p0K1h9\nDAAuNoaj6+8g5By7RqQpjLssbVgkTyW2vgACzh9kZEaRaGbIVXc5EbiZ5jUniul3T1QSfYmNpXEi\npsmWjHWBONA4r1AG2GokuJkSYdWmkXcnTQrzbNJgVbhz5k2/PbdNRU9yiDX8+YBKuaeJO8r25UBX\nfErFZr5+j2uKwIwBpHVY6ca2PRs93wNUctx+wfT9BmhWV0KOrESlVv5+etnqOZyBBj8AOy3jNLaJ\nMW6hFuSWpjVJiaK2u3Mec+zcJMOqdTpeebSCfSoa0Jv9KeSoeHd8FEP+uA4+6ufZs85JJSTJ6YeE\ndD5VHAFVYTgP7+/ydJa7bnw+leDGzHgOlIsqlASMGbXtRLxobUDu3rtJKrKLvzuusyGTvByu6ANW\nFoi27fW3leSO/k8mEYEYxDviJtlzV2Ew4DCZwlCStk7F60g+hqb8j7JlX/A4sZ7jNvzGf33+oDoI\n51RkUjiaAWH927l0Zax1VnBHHNGY3/aEcP9cn0JNLWqXOPEZaDG2AEViXc4SXglF/zjYRvSsh4jm\nlZDf+6JLapKNFj/U6WOaz/1Q+jnLOy/4jwlbGUui/0pxOwjO53EiIb8+cuRNv6lgncg4kT0vZhYU\nqI3kiVjWCqaTVYo5J0mDy9VOufJyjis/Owf30YbzK8tXhskSMnVGCEYaXysqIegIAPK2MYigbHv4\nYgV5UQNE+eud1015tIvPOBOxwMZFGoZE+m6FcD/lb0pip+7XGQHKbLnWpuM0J0Wgyt2oHHIWuwcE\nZmOznDdt9PUrecb4M0RmzKCR49k+FFBt6PVGZKkTDAMkfCcLL7TnyDp2ufoPjXYl8eFikpZ76AyF\n0O8LbQMUnC0UuD/IV4loxCdPwND+BUaV+xpgcTJLITJX52+GBY3Jx9Hr10udTcpWA4zkVkU56kah\nUtNfcGDqHyPW9c/wdOsB2uNwjN+kH1WUsm53Gl6HdZ240slkKAY9WBm70a2L1U39AWs23CzTZB3W\ncq8nSDk+xg3/2LqE44rdfmqjx4dlr74zmxQFFwnzD3CgIZWuHOT2oguHOTgfrH5gs2jT8m2F3Ksn\na7VXwcQCjVrzGbUr88rB6mXeoiM7Ax1aH9Cg5ObBctrpOejx9vBF5ZDxray1IgUot9VC1om7YIY/\nVdYiLhpe5Id8gygXCI2InUDOPutyjOvW8Fy9xpQOZxxhtV+CO6VFfW5C17Xsl+wBOcjKMGHvDGga\nDDIUGcFGlg/SRkMWBD/INUhFIG+AHsUj8zdIbmx+mIJGl11P9RlN7v06g4LUa+/N8sxmbEpZ4TCV\ndgfWQ+O4OMNl0uOoqVFcbkk5KySct9h8AAiRe1pApC4TpbbFdrV4F01uMNDu9JgLSfjJBAS0Wqsr\nWVP/tTJnBDUHBQREgEwXmUZaPmhI7TTJG3yrXoVrmGoeIH8lJRFxDIAT0j69KTSQzC0DnH/ZluKG\nlQu4BEMiQZpzAf6Ctg01cbuFOx9ZJlV9SQVOt2LtsaxaejPLRRq35SRUoZmqeZvHk6kZnx2JVutr\nb8tHbXcf4jY/xYvfYEFX4HOSvaOWoKQZp62bHLvvIaZSQc8zzZD0dz8sUqUONgaVEppfuM/WMImq\ngwMnGFhZ0DpjWeDdPEdOvxllLjNCBrJoMXk0NoZQ6FGekTHCdpuNxIKZDK8PDSuh3pH4Udn7UHg+\nkCip0T+gk4au+y1JHVcNdnx4ZrQgCc/aEC2T/UxqPRVw30xYhPl9qUGdlYHqX86Nb5nBWaGQOpy2\nFkj66xmYSqUYZThyAMQWkV7q/K1NcRHF9iD3PB4KbAvRJMbfPXRsVwK1sSP7R5nQdxg+YTaUgLKH\nDnbPx89r3MBelsRGrWQJeEa5pk3C9bDfMcDWdA3j6rTLjl8ZtTsrkn+mjWhO/C3F3s6rMY0Q6Rn+\nGUA05HEwcQ+1b3I/p4fhvDdm23QzQyRXUY5EtnP1HeP5gBk/e1C/pGOr2xgZ1Gt5FcbFfx5pvFJ/\nnG1+MqwEwLebNnBzfAgF/bwPd6KiVEFV7PU93PgbX0q8GDHMCYW2pi10p4JVorjoZIwsHTSbH7/h\n0RWSB10CY8WdocmknRsCcU10+X4Epi6ym499noha9lvBByhG+opGOQ9HqG6t/Nw31Y7U4uNj2rN9\nf7556Lp1BLOQWsAVDjQDMgRAKMpP0lfriq2XYSglbcrNybGw0AEXMX6CsFcW8H9NPxXpBk3Grt85\n+m19BUp6TYd/OSiSHyDJee3n0PlTXidCCSqKWx4eIo/SdI0d8MZrW+5914zUD/oLyNPK+gmxbd8d\nmQU2UsCClOF3pUxgccR7Dr0Ux5C6UlZBHhoIRS2aDhZRobZFqzrUhmSxSHr5vamn4txkY9JdG0PH\nntWgNn6Eih5VFDXV5NS/w2Ogc0JDHow08+Dpgy73juN2rBZhn9PVf2oVCw8uV0Wz3NN3GwV21Iuh\nzbdb5gaBvL1+lOE63dPPnCnql8P6/E/RjCAAv0pCb09svITM5W623E7wVXV35pVGDycKtO0rANJC\nQViv0aGls9jehkvD+pNfUKog5rxHFMRxGgeUB3fAI7Ml1jLS6hzuKKqBl9H5kI02FSk0Eqx3sxWO\n35z479p6mI1+CeKNkM6R5jdFKLVcux2jWoWB2T5Ze63CdwAGjTs3QrXiYTcYkJONdHNe/fgs0VGg\n4zzkv7AXoIsHn8K5HqyqoW1X/r/x3Ql1Bc6mXkOmRkfa8iEXsTgSOST82UU4r4lfHCjjCLSi6Sul\nw8E/Aj8Si/TOh2y4xv8OmJmuKbQ0YxIcbZU5UTZyvwtJ8GapX2+DoPhmVfJNjPYFFH5PQvehmwmT\ndgx4rhZxHqkrYO0lOKg1gMR/24M0cGkpIyzMExAGK26SRm2HjKlpXOdwCbft4y3wtruYsLHuNDpv\nrhHUu1Akv93ikJ7v/ghFHVTdo9XGJZVxl+pFQmrNu8vD8mG8C3OQ2TlAVpeqAgCCRYX+Ly35K0a3\nhNoGqO3Ul/DkyXYbdwbctWpTC8zn9EBzNxxwtkLhS7psDn+TWfDlpP7Z2XYi4NVSBxVGgapS8yzY\neSP6L7TD5HKcQnLW3CBtWk4riZzf3thpYF7RXIs2t8iL53IdB2YkikGsMu/BnvPFFJHPF1XzpTf1\n1GAEUNn4rbgp+h9xj0odIY1m7DYoKAwduAZ53fF5TtaY1gklZfRtZdP0qJISM16uWVx0VPaicdJt\n8l9pE5rmK6VJV5bfkzz+2LeNjen2iJLIdYR/EH8nmjzGQin/GKIGlG0XfNknxNRKkiyE6KML0hNL\nRIyzOK34XYuE4ymmnZzgzmS4uNCtg/oB4rw4ZQ9Y06fY6x/M+Aix7Z58rE+icVHft8BMDmNIOKC8\nfkTIA9WfdK8QoPSfZ9P5RQrGQ5YW0d1wRWKqNIYvor5aE0MFS5N5p8rbzdGtjMIOspT1wd8gmJgx\nv6NLOSdPV6P228cpNZ9cnGr+8M7EerdjD8xUTBZO2e897RQUC04/6LIJGqfBFKWsgDGv3kUXOQ+t\n5WOI0tbmSVFDavJJmzz61GPMnT3MKugw6r2yqhX2Sv2A2P6cEsDq3MmgrbdWs4cvzQsPMclNmgA9\n26joYmlJsUz0ID14LLYezi35HMN/8znhYLYkk+iO1Mxt+En78EKuPjQA+XRu64aKTT5CeK+icB4G\nRDq5D4mWKRODlLhEcR4vJWer47kF7ZxiOPFc4h5TvQJwX8bV9+ttvSgdTDv6+7BoqmYGNDM0KrbV\norA4ymoZH2IqZevYvXn6gs1t83upmYS9E5W553qp+pVav6PxGbW4E2DNmFtfbK22PZjn+NOfdOnC\nZRnmbp0KjISOxN1DplSkpppMGGLEvHhS+99+xay1wpK4NXbskGhIBKAGDPQ1M4/JnLB2CLHZfV16\nmYQjktluxwp/AyDDJRPX83Z0DnyMATsm/SpFNKnhxuVcsUbnW0OPH15IYca/VfEJ9ZyQUJv5hS5u\nbua0je7G1Hk2mbj2g6L8ZxialXajFTc5kaTCPPOfUCYGlJd5UCXUSvSmZS7UCzs5qMiMNUzQiWfy\nN4N8YDSPh6mPXPDPwPeSihf59jWss9LgWf0b+r88XS5VsNtxbMWFnfrP2SFOStSXfMK2MSP3KA4p\n9vOyrwrXCe37G+PfSql2gEI5vis13IlRhYKXzyk4Nf9zHg/l5vWsR50JJ1ddhKx0YeL8cbiAv1AT\nlzqGBgZAOkMinsVyO8qDWgByqaptxT2sPOBxUaXx1ZoH6h5A3bjlHG0iM16TAZ1BK09X2pDRiQXP\nEeUGB/kTxxLiyBK3BciO5EwCvaTfsVBowIZyizCoXrKOrNeGzAg/E3tOfvwHDk37f535YZvsMI8F\nwsqHEHicB82TcoXVK0yya49sKe0nkMmLcxa92nKzKrkeVuE02y1f27G8gYA2JKmh34DFLfoAf42c\nFiidrnPcZcHRaiTwb7P0kRZqbZFb0V8OB9iDZV9qQq47ZGq+OY541WpW48zGqvLEAjH5req9LE8J\nt5VJU9g7kzgFlQVS7vH0yKnN6X+gZ/qqVtxLYJl6KtWDQw56F3VSxSnP6BXG5FtOsWc54oVxmYJg\n3dez6qaAnUYYagtXbljgpL06Z5uRChLxCUJc6O2wbS1wxckRA6wlVAPpxalEACteY2ao5goDytN4\nb79hN2WqDvnzQFBvMuZzYZcm/ZMNPXzhEnTWHsD1mqxhemlFhPGocUPxViD0lvgbYusbzoT7Ze9i\nmkasjH7XeUfF4Ov3bAvYlZx2nWoqBXhBHEiR+g0UyegKKyevU19Iw1Iu+2D/7Rmb51mkq6TRezIW\nlmmvYvKf3I/BCjmHxYqsb1fyjUK6p9PgNq/QjqQO25SxCLdV3eKzUCT7txEVJs7W9dJ616IFYBXQ\nWDNaViIKApw73K+44BusnPAYR1vhQEHO3MUjzrGVC+LyRDlR2UxkRbZgVxu7CMBVMJwUy9SMxYNW\nIodQH21No8Hx7ClUbssGWqFfF295RYSe2vKz+QXyC0jV6SrsytjJ/acQyYpkx6KSSendqYJdo1d2\n1QWP6k/nCG3Ot+ON23JWRGrFn7ucT31h8faPpSCebSMDmXJDnTEQDjpvaj6QD7Yu/51JkmHCN4F1\nrE/n7gHwgH31Z1giQVUKZwKRPxPTksPdzyCgJGXSA4aI8uXuOhBfN+xZr3tTwvSLCYLRWtQSn+x3\nCl1pvQ6nTXTBgxz79p7m8c40xp7aSa3b0hhfn+Gl8xdW4pcgL0loYtU1le2clNuGgmPG179i2/uu\nClQMjD4GD6BcbDzDFN/XpL1dZYglqIbXIawigcKxcFBYDTmsRXJEFTRn6SXwjrYFNLgfC/yUdNkU\nEYEtBi/0eKX3Wa8Lh9XHiXDmlQd7wsWBEiSYEEkjTTNzhon7XJN6AAY43NjalbBLcqmX5l1i/8b5\n1w+e5bzSmX0WHcyWCoThx7WABeHWdLytMuWx/fvk0uGexf1ytVbX9XaF3vziR0SYJ0QUSF7jYoUC\npqmOwDSKrcR995m9qI2IAuYp2yTCG7PvKdn4FkjrjlHuD9ycXdYWHUVR/WgZToqeinwTdeRGLCp0\nWuxVRjzkfFKvyPROUMnvRny09a25/wTETVo+crnXSjILyUWQib7habPmyEoQLS19e32CrXE3rbLW\nmoj3lJNj9vOsZDJkdcnDb7iZ0+KA8CeLMfm6G6sGBq0GFq7IcP+cwM3wzB3YrmjNQBsYzrQJMsDs\nCaaE+TlVAR3KmrEXssfPInpTbu70ZuWlwYbPGSa5utwno+AOs891LYQKTAKwcpio20sbSEnXknOA\nihNc/KO6b2ODy8dHQYe2tWc3+jmqozOQsNHtNTRd+vAt+2Nh7Q6+C1vTppWc02x703ZDLaYZiWd+\nku3ASFwZm+YG3ac0DnYfXoAVojQ00ZeY/QHoBaEJFYnVEuoergfIF/vA+2AYa9g66cZZ0uF7ITfp\nNDFK/Rq90btOenrD4sP7dYLLMFOonJlC7hAkJF9bviXGYR4w95entPxMv+oPFhKr/83KezLPclOO\na9drF25tp+Y2LRZwB4owHe3DFce+DT8VZbySR+mqQqShnb7WtuAyRLahPs6DDEEQmS8EK8jyPSXb\n8YOSBnxG7XuKnw8Lv56v+NONoGQwsgDuF5jfXRuKCu/9PeSRVSWqIx6tIjsBWQON7/sMrqDUXhTU\nP/z5b3GKlIrmN9wVF32x3RLsZ0xs+PeCpcnW4neNVzSi8e54CQQEII6q8yun0SBH+mDXxdw8+jCp\nI/hiG7Z+NuoPlKjvPFqWF8yqddQQ7LmB/oQFkrAYwS7cONCc+g+9R888UG/VJjYRWROlwD/VsMkX\noBwb54pBv2OMxZVFhN9946P32mF3Gm33ssSRTTlY/TPGveeiqD1FtepBHnRIQ+XAN2eP5cd/+Rn1\n/awP0x8ME09OdUhn0XGgIksd+AziSrA1GkKiikudfGzQvqj2a1uwfOseQosoXcGOIAY4V+krSmPk\nOvZXdc4/dvSxXfv7EOe/i5sAw2LCbVgprkmeemR7K/H9kwesUv1xAyy04Ng981gTa2Pw6XgyzlR+\nWHKApQc/FJa91wXVrNLOKiLV2ttSwXtyROjDdVQx0XuxHzTJudCumppXwifst0D7pJa1KWx9iUvU\n//CF+VLQsubHA0051h4+dPLg9073kxolsyJbdjOm+kZXvKWtLN92wQ3qa4qmHE/kXtW02XKXPm+t\nDOXJIMUAp/C1tRbhCfg6hhFK4lrKvnH3jVpmKGMOi3rELj6989e9xj9HzNC0+TJ/IjS5Liw2g17l\nFOnV5xIwpUwN5tJ/cf5nzO3bmA67ENfoKBK9XHULdImTpY60ZQWh0v6dyt+zRMcMRMbBqkcxXjOh\nd2drqdtPIcshuCuIYmcAI+ODGXCFtC+tjb+q2EE7wlCZiaaDYdgVibg5yenqh5ZR7BlG8+dnaZtd\nVVqTIdwYYFgSl21aEa0TIEX7TEA5xN4H7Bma9vYgAHiOS/YacTwQklxMDXN0FXGSK44neOurRYmJ\nlexE8qaugJ4Qo/MbKfF85yXvxrKo5cmFcI73AiJm+04vQkS//MNZgqJaCj18foDt5A131OSCS+yP\ns+vMgqKRoTQXCguDOCbv7oOD5AL6YcJRTZqLSTZ2Ep7t3hxYs5wtOf5II9zef7NtL2AU8566AwcN\nBv1X5NmA+QBq6A8+AaNuk3Sk+eWNYR4r6FJbLmj7dEPVZAJFLN5Ldrsx+FDDTwgnGpIE4vgeZBrl\ndDDZ/OZ1tIflMukpwYpuLm95chxPPMgHhcr2TY0T44peWcWCX9mf/oHfU0EIaQ1trQTpWZ9UgOgv\nJ+BqUh2kD/ZY8xY3ZxtRl5cUS+d/BQ/dGNcHVXfWGpblRGcHuDXQUSgQIQ5fs96PCpEWeQrBEqce\n835ejJOjwckfqKguukrarnK9MQTALwzxwrF7qSEJOdL2Kd6E1Sj25F2frPDw775D4TTf+QnkzkB8\nuwLul0inUosRQWaapvR1jQJOzvysUAvfCRA9dgbKem2n2Ji7r9ZbpYkt5b9BoIDb6VrY9FuhpnFG\n+N7rkUrR/VFKVZmWTzc5BewyXbTa+SblY7FtvUZ7iH9BvCq8nY+IxjG3WGx/Vndxy1dMnFBeIhHs\nfpRufL4fC+GfMvJBxJxoEyfbGW5BtFbo+uqfUq64kNUw4oVli8A5tLaYd9y3/LdfbZn1zL1kixuX\nJsBhRYwWgGKxpbo88x+3FaGovmRLQ0uiAvf+lzDVuI17RFLwvbgS4MeNpGqr0iK43vohOKiALC7a\nmiUGzxMP9+r5XbhAx9Nah3riZW2wpLIp2GPuOBy2GtwBbNKd0w1BN8jfH6p50YdFZfksroMqArR8\nd2b/qG8VwPyVt1gfdDrNtiGzZo/oexOiCXWDx42LQ6OtrcjQUGL7Eyh6DV7+/QEX5gFJ2McUflPl\nHbyv6Rf4x8c5wO1QsEFWaLGTxOr6fTvfFZ+A4OZhmC2IzniHjL6OJMykDxbrGxcfumgzokHmy6Bj\ndqfZBV+yYdJaqSjRjg8TQS5xL+31qweX9jy5XPRrZjj/nPO7WCfrALdAkZCRLbM/lB3CYp7snq/u\n2FQPUJKzck84Q6brIc0yyHU7cZirWPuCCJm902jQfF1Z4eeNBniVJqMxGxD02fyvBco+zDRR7wg5\nMwKvzf9KCPLCMRDMCwvw1TZ1SLv0aWNJ9yJp2MIxp6PpsUIjg84Ne1nZTjRC667gWR8RdM1HSMvp\nR/7CjeSVYqHKN6klkOZrtYFEWmP8tS49pJMupw6rrUtfubwgMJvsVlsb7zVRcFr93LNl1H0e/645\nyXQRxWG2+4wTzpf1vlhQHumG9ELNNRScKfUtMXWH8NLo0b9JOz4DX0BYTMiPXTTSr+rVInFhH9vt\nyrLIir/KW633WHZm9HwHfVrNspsymo0wtIEabYHgDykp9IqD+mncW5WQosOpZ9c4vkofCTg+awnc\n9g9fe6dakktrevhHyNh1sB5eGeg5gfeQHNFELghRHiRSSuuaP70GqMPN6n+FgH2kSfiBn7WOfo1Z\nOg8ypRlaIWlDvEQozS+0hlB5Dt5B4dgvD3VHzllJayJgpCBBigpy4EUqYp/wW8UAINtpVtpmvxTh\nrj3DAKLlaTDm4rtplrM/QG2R2gSl3DkGIKa+oslquw9wiJUDsStTuWkX/Csqg1hF7yHpGi0gjWgp\nes0ZFOARHpaTv1eNyijqt/5kL3mS/Uyu+Xf7nqYg2sW93lU4MRunY4E3x7gVjVlnDqrH38RsgVbf\n/bAB53riBSBEVwvrIhNCLJf2YSx0dQnknNj9TrGqG7wg3siYtKyw7dITk+j1adr1yT4WF3JPMXfc\nCGCzd99DwEMf8GebDHPdamt+dEcMNraG0LlM0/vyu1DcPydE79HjWORYiwyjETFYxHgP0ieLY9/7\nbI9J0zAIV4h/SBn2tQvbZPMzROTS8cHMtYmGYIAW/DOx4F6lPzxBsQxGcsi5bomkSw3WG54ymtra\nZtfJokEersbLJNwoqItcy93giFl9IAtCELZl3/U1XZHZg9mEYTGHi+vBdcGOqdpQIlvRX9p1F2Ip\nTS+2As10HdT+ixcdc0Zilu3zsL1nC7aL+qOP83pBQo8WlmXPB7g/p+8+Whhe+6M313uinCh+X2R4\ntLcLDG5oPorL6DrBeWkOCRhppgNms0upxAws0c4vpFv1G5Yi3kS8D9QjDa9PxB7Zy5XIImLr5qPc\n+8UsRuj/sjnk1nk8FLFkVBuK8anycdHLyZlXSBldoluzkSexK2ccVW+p7pHqcaL2LdwCThrtKHPA\nTToUHml18jm/0AFR4DlPjn0Ay83jr2CjaCJg88QoYmejDgsmSwS+qrzdyenn92N8YNQwXHnOxvDI\nEX8NEjgGwejNCX+F6UDu4ooXRWCHV/db1LUmOJi3tZ6pHl5T7C3UGZrLvvGq4rqTC8dnXu7QElEl\ndXB0Jfvj1WkEZwRcfDqnNndXXvdb0+eXayHK5eaj4SRInIPnJRdtP+2MMCMg3IZRDGKyyi3qm+9q\nnUkNNue5OIeLn4DECovWjKy41O8/ssjasnXEaC8b175d2zW1YJudXn9amXWCbX9Ud/bmb6nBE4Mg\npCO8ysuApFyU/RpvYgZgCQjbJfU71XAZCVgt05sizCXay1VKVROFnEp4uljDGbKOjbHbH3gaC7I0\nRWZMB6dkGm/ZxIpiU/6RKB01qIJZr0erZoOeIK42YBb9tyTfgSvQD52iJKevHGEhXK2s8Z8x9dqV\ngbuqj/yvDnIYAOXW6DSyphyGUq3aKIziCwwukrCtLswyddA6M/CtafF8B4FN1BuIfx/+G0b6ngwm\nlBCcR9txsFqfBFL7baf7JUUA5EOboWh/ow+ujMJ8iFpfInczwga6nLqBexAosYjMKIre1kpSkuk7\nmegLJWwe2EgVBEDQ+FmrZqOwYXmJns+jqYMgk1QuPZ8jdmeZuiWEaoAqPj/BjdTnewI/MRkRQsdY\neMANESKrmSRpTRosqItt/o5xjdCDEWk8hsvMP6Bj6VQ/1SArS5QfXG+Q/Y8E1dB16ZwIFCvFp58f\nsaGN0k88w2vMwShz0YC4qI+VDEaGMPvj1ETiDId9F+Tk1HacHTQy+l8YVIKzpadWyDJUEaOHUqvc\nV/kktcLl6/A+rZacuEmYxtPG0SaB0+bzx7ulrKNeyDQpLQTxgW8cxwbZvxcx783MMKW/oQTKfMgy\naoO2bwD69EWFTjHW80RXlrGm0cI2zi5rXy1U+NuljLwFfXu458eZWWzbfGKiHRvM2eprcivaE45u\nhe9tUrWmJPNjmytP9CxzArvdMbGunwZGzfOtNt0YrijI9OLSvrDbl6x88Sqqw4GQJVKTm4/q7xh6\n8ibl/9i80mHDxOj91I3UiCwqkZg5G5zVN/4axYNihActqP41F5lLkw+hWR5kQsFBAFQHJT2SOVLa\nLUPhs1boCE42XK6Gfj/Tx2j9Yd44Qx+XdDEVSyZWuxsFSH1i8yN1NUw4ChRYkNerHAZBEqCnNdYK\nw32X9be7UtGPqWm+3kydmuOe71OrhlKu2HeBilBviVP0AYa/zkoUuFj3s8Hgt6bSKoet6LloUUgJ\nqI8wIbgurQBUaNaxNnZ6GxVO9KTx4uKjRMmSU2XP0Twz4ImN3C6y+UBZG4qhw9TRUwf76N31aXXX\nez8PQ3sgpQkm/gt0naEV3+9SFysH1BRKSrz+TOIbPy2QJV7qnWWK5k2FNjHhbbtb+AleTOtfBoLe\nEc51YElVxUKld/cOOHHazFVO/nT4EqFRiIn799Zn9pqxR1xVuX13gQXEHlVlh3GnV30FjahAXr2x\nMOWxch6dz3IBXnmtnX2n7mx1OQ4jT31f/LAhehnnyv7TpK59ZVYFQh9c8I98SXNxo7wb5b3nIqNF\nMjBSWnwLaerX6UcJ5wPGVssWMw3zOtuQjt5MxS/pTaI1S1jL6dio5/xyaY6deEFJ9UwS/nOXgjhU\n6NIeYRg1kI4nSBmdu5f8sxS7Qp/N86BSrRb18TCrGZco50Sw9wTR/ACbl/Ch93aVY2XnhtEYIFWe\nY3nQhAncBNIhNdS6reDaGsxj1G5BA0HDk9YheJUOGCxMmUG2sRwD7LpOjbl+q9LupIxRmUdvqvYD\nJKntjzxXKsvtro8LogYiYb9jU7/5yiFQpM4uCDTXQBl+n36tHKaSLrOH/W0xGbxcPK/0m/f2h/bI\nCbQ4FdopFGjDlNksSv1Y4F/TlRRs5+ychHtOC6UcY+BgwNJp2Gat9d0aT1oXlCfNnY04bSqAGmNj\n8DZTRVeCVeUzmHHqyl1m/pWKL96Gqk5EI9JtPjXn1wuNhHJ9ekiv1uy4uQ1o33Vi+ASxHhqBazSH\nFQOgKrrK465oVwU9iZk8Zpt0a8UYjBp+CDjOP5tFwWpi0nRehaSdfluPmr1s3qcre4Z1dlyuV0jf\nXfgz5hiEtEcttscDae5WKJL6W/0vYIFH2/vsm8OoD4RQPSJNN34jUFlwqzZEPLtc/ZeiJIqzUumu\nt64Yslx5F4I99PgpeRYFCw8dD3CtgpNJKeBoTpReAT7O0ob0NK+MEpspLAce7CGA4RRjowNNGMZj\nbwf+qjEbROMQm/19sdfd4eoWtFMcBEmUDcIwy3zadlH98AjuPeKJtAWtfbfzFWDM9Mcdeew5V37J\ndf1g2fkmvBh5dgTvCXMr2x0NWwFcd5imxh94VvATHfw7O39QEdBXFfPj3ffEeqTAgbel0UvfSnjU\njZftrWynlJu4kqQSU10JfnORHe4h72DiU/HtIjRMysSqF593SJ5BRQkc3ByixiPExTfE9XghBavi\nhedetJextNsM2o0MfQZ7M2NMv/CWFgI6DP1xZ2Fio8L5dpeAqYORS+WFgznPUvW4j8x9179cliRC\nH8FawTKxlGrZ/zMnEQqOo2fMkXd8byn8oV2qv/l1HDNFJXxAzGydp4ep9xXaGpaRCjqYJGv35KRC\ntxLJsY10Td+DHMNcdv6zJUtkWJdetQUQjsIqxJgUh2NTibilW7zwlph+ltuOQiZj7dhGo2NwpRxj\npRSOiTAthj8O3Oox5lTjkWsZQOJYZhsuLWdQf9lHcs0ZUsj5S9+2RM6U0rewlBsYMkgeEIO9WrvZ\nnFWjGBlhlIAI6hW6Ek754Y1NwfwcihhMlbFjezjsdA7r0d57sHy10dnyKk2dKzP4lsXx4oFswI31\nMlJeO4e+OQuXMjC2s9QtD99djW+BQN8vS2hss2jXp0RUFN2ALmqlKUlQY7F8Qk7GA8W8xEdMSRfC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CgNeDKXAqsyHlBqiikZBELrTLQziUuO2Ozlm5IjiDh2U1AcE58FeYpCUcAKk7tuudNf4kA\n+4IZMoylovZMIy1uk6gDeTs8t7ZT+qbKAYqvQHGc680oqpHHqBGMlkn6SvYbCvdeT57YiL8qgbua\nHHRqgt76f9I6m2gEbzKXyq73F1XA7iNkIQH6wvVGab9k5vFK6t3VknynPia/XwHedkmztqfsJPcL\ndpmsfLCWWjJB71zBzndOPEH4gQlmdtbPTUCG907wykBW6mbI2D6F8RXBFxLFiTe3lLlK9f6JqaKS\n6P5Urf4pShGjQxePyekutNDkOXiqBWkNmqlwZ0Mf+998Ey554Ts5BpfAZKA3iTDnLqa1WjM8MdFu\nz5cnBm2QmsWFiDw07bde4lWuor/GigLLSGoi61c1W9VUUTxsmRW3Nm9hedl/LMIi+IVd3Ie5yuhm\njFTZ6GPtxceQZ0a4n/9zmY1LfzOKboZDW8/yeLpK37K4KdBjNJqUeWPNEgbkAwu3B6nDVdpVe58R\nyE2+HOOoxDbkIulCG/2Z/niLLNiqicjDej6x19gTcxFfvW+AKN3OywTja1dzXhKcg8TxzQWMPch1\n7hIDvB5NzUnEvJPUkHECOzjp3pErBKiXve85ZxpQKaT3uOCuv48BGPUNsb4Lfbil/ZB2YfZA375g\nBWHRJSLDuy+pUEyTq8jZoZFHXN7uX9th5cbBFjtERzEP1e47KFVu+y2grd0uT/p3aA/Dnc1rAVN3\n0OUl/SCM2fRrCgXsZVeNO9TXtrL2agt1/h3Lf+NdAkcZvn9s+8p2KQQWKc+XZxkefaWM9yc/9fsX\nPY1bSFbAWYgAawdP8Rju5Hw/OWV8Sbv9vq7xEY9BvZleZMYuNtFgj/xGBc+xuvt2uXAyHW8FfkIM\n8cL8AdK9g14QyRhkyT0yYQinZHzS1u8UeYNIafkE9LsetGUZn6zTUy/AAQpdOJF5R9QumyGkPJIG\nDLlbHC3SGKKie2/q6GjryZedQrBwkwtDiAxTW0Qz0ZfWnHQKZUXchgOf2KSxyoc9cL5NvBSM6pDT\nBAvpvpDR9IQrbp1Me+korQHewv8IU/iJGQDmW9irBUgAsfKFL10de5y0FcL4nlC33hPYvgoiE8RU\n7OI7bRcSswtiJb7UhlyHXhX/Qq1xYGb13RquMH7/TEr+w0tdRTXngTK1PlKg/fw+yvbbbz84vm14\n69gZb0aJzCbyTfgznfo6NSyt+Yc89ItF7q9pqhZCgcdoPXmBq3Yy9NMPtoxsUH6kOSfBF8AAXDx9\nadNlsmO5H/J6vjfLVMwnD8RGzKg6O36A/qO8CTAXdFBWJK1mHmV7AHkQWbWjtI+29Y8Cjcm5TMCZ\nVcGqgrTLwebwYR99+75or4EP+AEvUyYflRqH7zmkV397XZfJrtGjYDfVNOaw6Fwwl0BUaCVklg+U\n5ujWXPqT+WCdWww8BHlzRx7C/fcE8QYr6jkhv8ZWaZVWeR7m0BETZyFFtYpPQbknoTrZ5yogazvW\nHlomBpRuB+kPMi3hXD9VvYxmmzlMPKDSqnD8oEc+v2HUEWT0UgCJFxQMm9iGggPf3YHN9D0jFjsl\nmgTwaen8m0tCFvDheznqa5R4IJ6bRUvo2XU9OK9xcgDzQcHU2WgdEott1qQL2QD9Xhj4zN09paCL\nT/tIIUjT3V9B5xBRw1DMZULj460qadkGntA2s4bdSew3xEhDt1THe7ANelYoDzMrlueUPA5ybCN9\nj9ihdm9lEllXxLg3gyWzGmSmuv3HEWoNkOVomnTHzZ3J3QNTFDOMQOkjTsUcMNbO06kf3AfMG0np\nYy1LjpLqweinJgeFCZihIUKgUh+mM5q83dzxHzSQOkbp4qgEnX8XTdz8z9rDrqNF5Lis+cg/r2ky\n1v5mr4jN6tquOWltmsh6mJqtbEflof2B82KIIYqy+oo3T5rJ8j7yS3pspqLojUPsoDdI63Y38pnl\n/hAd0oP2aCtDsnE/pfTIXiWPGhPniqLkuv7cBGBWXYznkXvzGpkOqxyxhWAgwn279Vl4NoWBY9nG\nP+D7yenxJFKzsvPZCtA18L/DbNpESKFNX/zlfxsNo1TD+3r7PZTSdNqrXwlbhXO/m/+5mT+w5GDX\nG0lC5guj/TIRf87wZd8GuzTYgQ1MRFizqy6t3AMudVJ2vnbE2fTM/qu7afzJMvpQ6f4Q2V05ln8/\n7q3U9uBhrpQvPrvVqap3SfhElGbEOS4idqH+lE2LwPXQ3rvBZaWDG/ZqR0WAPWNNl6uprwIj8V9F\n/nbYOcr9WtpeB5Z0NEKE1Wdxf71w7Ne79WOVGcm8UQCtaI9HHu+ky22iO7zNt7mGTopdMTplddm0\nXuIyP7Cf2kKXQqso4w68N66MJgEeKS8ICKONtQ2HfqETdm23OPCItND6bDztQXOM215iJj/463Sd\nYBeMiN1aY1cnhgrab2oVuroETi3DwUIewB0lELB61LHLjpKT1uFQeSRnVjZ44sLqvXljLc7VhQ9O\nkM67M+SRbxF7gdwjNVUCJtaTxVM6Vad93zRoRBBi48nRC4GogHXTVFX+P6PK4lESKZ3QFQVE5E2X\nZJPoqgI8udlaVeBK1CyOphB54UqTOMDo6yXhK3f1Oo0Xb7Z6EvQYSu1ZmiGlj/VxnNju6GIffPbU\noj36vPOyJjH8eHw5Lsq+wMg9hiBym/bv+XrGLRz5gPQOhulovqdHuA3VfuOkQpBXA7ZwWqE0XEHA\nHlX4GYw2s6WZRP35U8njSsTSSEzeHuQwdhGLNBLKiGCMrt1OGn5KvLQhhz3uFmvCvtO0YQgr4gRv\n/vmpo6suAL/ASzgOaEPhiVzMmPkrWYzIBE3QRLskFPR7umUQrpLgsHbonxi24nKArAZlLqvR8zG5\nMJW+VCRb5DvU/3epE0IoFGxaMXInK3yTSqfouU25pcD7UPznWiUd+Z3ZbKcsRUDqqTFSWVEIdDtj\ne1soBVA1ECD1iz6+bTpNY5Oh1fX651YQ9lvHKncJ2+dN9V+hRK0ngC8rt429CK7a2Idalpmi3JWg\nDc+d/z1QrUiknXJdMXdblP5a2mivNqIY+P9N58n+bZLVRKzRPI5fH+TaiZ5jTqJPrlNeN6D2tTa1\ngbHLS1Bq9dYuOLXi9TsbmXBgJBQwwPEWK5yG6KdPu9G2WhBizqyKJONkO+nGznTqzepavVi1EtT2\nDSy2ZlkxvRjUjhs6nkJ8oFotJICNfcBze5Rsg/eui9K9LduHWu4KMEEnfS6sgxuooXB2mSH26zwV\nij9uuzBYnF5pUMZP5ZIHwUnjANwa5J9TVpzTTsyHD+lSA1anl0ixbWrZqBWojDnzT+iwlGIxFd5a\nCr7uEUoz7+tyA+l+rF2lKvvxzfe+zdYMMBvqsNDGdYqNAW9FkmJhCLqy/xwgk+n2wVFwkP5bs5+I\n3CWz708qj0Xl3IUamaiej1IyWbCM3/65rfAs1jw/SeAXlA5GLuL0OQre+5ukvItsHTy5WCsZy25m\nIlzQgA+g35NVaLX8dpPHhdDcFPt1hGXhP7Yr6joKGvJFCTAqQSq1Ept7/OihaNf5XXI4dZlwggzW\n2O6+s9dtuhAiKtqIJ4ijww+apXGJirR6xUAhOeSg0/dL5FZGPXCUkxIV/mjEPUtP8xHtTf+8DOkY\nPWXBtnx2mGH1KZHfCfdcUVSPmQCAIA9DeWX3Q/v0IL1BHCVTaOsQ0i772YTDjXu0N/Va45Up12M2\npPcrdVHbahLP7O39ql/r6SNm08f+RwI7JPRtDX6X7V9G6+hu0iepMxsxBHk/8XaLUie4D6F8Tp66\n6wGBZoUWXHhVYxe1w2xSgRvnaXfLtyfhQlgn8KmHdgk8ibc3u4wSRbVtHfjrajovxVnePPubf0sR\nGGHlwLMSkklmrNGL+lSFGUi1thX7/vm25FpgBAf+b4KILInLLMnv3/NiX04A6G6zgU8xudOjKqA4\nQagbl+lgpX1lp/P67vogTffKrn8q3i1bhVvE/95/IJpHNxGD/YefOIJie6yvd4g4+QI0Msv2w6Cd\nidnVFRjhjKzWFPITgzw+/cK7BbMWwZa8ZVr/R0Ea4sWBVTZPvhPjDIMDuVTtZ/BIXrN3ZvcoZLIt\nuEf9nP+YPyFSF9h0+9M0/nnp9F71JHyX7jYpqOOfRpiL3Nxuokq2bunZore8JzX0eTcdJscbMtrD\nxCeKBmGQnzKQ6UiCUFkKvuf94g0f+IGcEZumf//3NSJuBvPpTbwMJSm+sY9G//ySSjk7pQqkuR8b\nMd1KFK517XUMgD7SMRegkJwaEV+w81z7aG1qIch/hQCgQbYqsyjvh5nQId8PgIl3hj4GB2InI72Y\nUAhpGWuaDLA6TX7OKs162hqSHhiyjirChFnxXjvJ+txbFF2Fcvd8Lle4qgP9HzwonfxA4tbzBytC\nLJ8EbIpgGoQE0uuPrT7LQg5Ul5yacTYpsvgQiEs6/+lSlLDAjEpcyOT1BIsadKqhJF6LUpao/Yqd\n8nYhQPOfQ9M4yxojCmXWRMhypMMDagM5T9sv6qzL6qgJ4635y7SHWV5n1z+x2GMB2W7SBYChf9Cg\naynz2TV6w7UesU0HBZfyRI8NLkyMS7ihpqyH1jAn2v1bX9SC3mKHK1xiPPb7MyxWS2sPaIZTX3dn\nLSFpuj14rJiJBIzNUKOQfgxBQxFfjiC+nqamVkFll9Me0K3Pzx4nWb15saHV2Agy2l4DayCQQSf/\ngFu+g2qlmJp4rljeZnvFcfEJsOYyCCSq72bieaiG+5CDM8FK4XKb+yzUHKzInHArOoYBwfcoqN49\nPkjVl2JDlQyLuLK8pcfOC8FrGunZkBIccptg7+MMvM6q5pSPMdCQzLJdSw9VJocDG6zh3Z5jUJwH\nJq6pFgVUxL4mHQb/BSlbgvs7NHbdBWKz8rrRA4eVc1kv0JgHRrOMv+3zEIoIiDWuTT3t+yN96Iyu\npS+PKCweGUCAk35o3tdplD/UZzdXhXqDMyDWXStqKnsQIolGFL1H7y7QpISzFxs688S5FmO1T2+D\nM5ktv/9S3iEiq/1qs2t/zEaENLUrc7DR/jifXMCRgj63g3PpLxVEDTtL/3O4f3ScoHrkebcb9I7i\nNaMRY216C8UOoH2/Ce4vGbBnHlqnvcEceN9HJrjnPVfBNQgn3cqClEzhriztssglsio529EdYhvp\nAI3zSbuJdREq0mii65Ch+MFopk7xMl0FkZtWXazGh5EG8XUCqTTwL68iZQBJNXNwpWsMwOjvvVMZ\ncvUCwskXIgeBTeVeZn9bFKUZ2F3GnOTZ5jC7ctowLND5yXfbzx9O0liZCTrjtu53iTdFHajEz/b4\nl8p2KTpbmC2CvZInR7lx9ZYk2MP7OjxSovdxxXIwpgMYWg1YKAiEIew1eILGHH9xYot4oEMFno35\nqX/JcF2ps8iJNJ5XQ1YzV7SduBeTCx/Yb2d4VHhNd6lfGJ/VPyBamni0Pp9q2Dj928OQezu1XIGJ\nvaLVosBVp1vLOs0cqntR2L8Ok3H6FZqtFm8mugOIB7ULCucN5ryxyJlP6Mrpe7ya1q8lqOGtAwth\nG/Dy3taw/Yy5HG6TB2aoRw2kQ4Btsq5j++25XkrGXxx5TvMK5qSWyxOU2HSAXZZI0Cn+jichK5fs\nZG/1nqyorqf8a3ei98nqpjNgoHVp13lYVrpLCWjOaECv0Opzj1i6EBPMbhdUBAh9TkIuZZlMVuR3\nRh3hDvelRcMCee0tJn0NB1Wo0yrT1Hnz8diHo+bDuao4G00VU82hBM5EkCU6X58wSPK5Y39d0nUO\nHn4Exdiza1nnBgC5bhX9sWMeuT1jWxW1lo98Wgg9WCuJU11VR+TlEeM+FKOVQRTr1Pz+sZNQxv7G\n5d93rqlCR8T4JnKkrFpEu0vUDzqHKU9hKuIJpFddQkwSB2xvH1Ts23XKgRXCs0PBmPhGZ9fSHQke\n6HQRh6E/R+JlmU00vuzxXNYgXqd9Ima7gLVPBiuGcv2c6w8sz9lOe0reW1OoxgvI4MANQ1k5Qp3c\n8cIsxgheBdrhp5iBVRipALi64MIShWbP5ZPoC0/pKzYVhS1qbqeAYfngLEsaGyl1GbQiAKOpwRlF\nIj8fVr9LS0n286kxnV9KaZo35NiXSH+DeeJHugfPaKqRPArvCi51KSMF8TRpImRrY5g12Q77sDQy\nuaSsxVmQ+gC+MrGhQk+Ferh4zGEzjSHtNC5ofHgArM1c+JvCB4xiTF9PDKwaSAZ1gS7diLNW1Bae\njLSh/zH9yp2jy6upD1uDSCyY4UH6LJchwsOuMFwcaLN+CgxYvly0DIo8bjbzFwfBkFpGByBmPOSw\nX+53dM1x29EpbpVG9DnxzhIEiTGtwhrwJbrLXT43mpBbRKdfi36hOpAPxzwxGmM2XQpL58RRNhcj\n8J3y+kVQZQrtEp/v5MaE00o051ZKzTsCgatNlb1+h7mQ/c7C4QiCOxC33qTJun7RX8BJo39ZrxTW\nYDNppnA5iD22u5ou7Y2jTNRktD7kCCFgu+pWxFz2NCOwx0LWL/xwthI4uWgbfvNB2k/63fFlHEaj\nE/lOWNFbj23yjG4E8gRNJy714aUef4Tuh7kJF8XPER30VGXe3k6uKrLNYFb/CjramGTQtoZqG1Wi\nNtwN4PiXY4YZV/V7DJw5tBEQC+OFyKd8PvCYSCZXox/xteCAfB1CGiTkBdDPfuo95ppWrd5sYro4\n+m/uYlT5oiDyS4hcdq8NZrPRJ7t3f6AEZyKJHp8ZmpqJr35SNV0Axo3GFIGOQMDxaw2HBiCFz8ay\n0cqG5lTZlQoSb2/5YRFNwgAL3XRgaPuzhiWC0+iZX4FfOSVo7pMENSc0SRR1oq9QxE68hWiSkdRE\noq2dpOWG019B4JrlXKNvrLkrMUJ5sH4zilU1RN16NshlO4pE/W+iLCp9yU3tOhdOroeDMEBV5sSX\n88rzfqWGbCdzlLwovLmF6OC4mjmrF4HPSsi+jJqVq2LoTCm4TxIAWNwNYUfKI+KzAGYV2zVKIdc3\ntv0Wqz2HF/Z+mmlP21Pxb9zNw2JAzU912iUJrv85MmEUSXlRqOnV5EpBN8dt2ng82MQtAztJzPj5\nm0wOljbovym9o2s68UWKkcVsW+u/o4fpmLEDu0/z7IJj39E2uS4Bl12w26sC0xzNue9Ykx4+XW3u\niMkZqb9QY/xdNNi+tFcPMQW/CatBNuqFXQfaUvwS0FxSHLkgwa/6tPKdt9Lby8Qc9UIlXM2UpJl/\nNhhYzC0x6EdFGNul7x37AnjCNny4Ub/Ww0R4cX8qod0lRCuYjc9/OQU4C8qBVlWUvWiqPj/h8D8f\nQhCRt8sv1r0iAYpJk3cZpgmuKHxm8jFvDjo5WIz/+22ypyGDYseC1OctClKvmM7/cVdn5VkUnqgn\nJt4FETNQvt7chlPPD1Blrf1lky8HAFkUz5s1KeXaTm0rNu7JE6XR8V3h7Czf5z1eFm5FpaVLnA6i\nl6gkI1Oy031mO6fuF+2UNE0kbZWVL/z2MovoMxd61gsIaH2gjmOgomeRnukJmCRVi68MY3kbsyx7\nAjDUjeD7TumBK+WhBzseB7EYdYrrjC0xNAbW0KTZsa8VJzao26yLPqoVlniszEUaEfmZIu4GUBZX\nvH18+FvNpADgh1KH5fdSuHDiDUnv9oODiC5mrl2wVb904J4khorffh4MJpK0Hyqb15eO2Ca0JtV4\nZjVozV4xm0JoXjRu8uL/nTLuVXTAPNoM3SVKkg1n280oUNhYvCX3i0WN5ylfMuGbNpcN9LJBddp4\n11SqFP1NXhuLwJ5bA0jOtdxqBXbHcdhaeMWFitR3fXFHOvuu8aymkbkfDY0gdRGGti7aSaKU0hMX\nHgwRHUVqc1iR4XykXmb7Q5WfcLF4ooqZtxsSikSNFHzAti/2yk0oMmHKWKyVyVjJdIxz2SwSrPSL\najb0N3knTHQ3MuD1lBFy1po5ELmLCBhy7+rf4itkuo+NQAIac6/zcKBIYoXi1zD23vt5qsgqoE+I\n0Dp90ubxmdHHTmnbPTc4+NNMjNe802tiwRX8CZpAyNkqWZ8oNywJ1SpJTAhL7vDB8KGw10MW2FXs\nnGOuoVn4I66Wj2AWJ7runJR9WAguApiSNyEhtPJ9f/zccN9yj/QteX4ipYXXTXBPY8cAUCzK+kOu\nYX4J5okSHWg7aWiQu8JL7aFCRdxLsadgw2aFgeoz9vX5B0AzCBF7usdHNbf0jEDami6RCH93J/m8\n2OgYYgL8Ej+KCoG6lvUB7OtCjCvIoCrDHKr9U6qbY5BHtKNyZWKLJBRjYgJAXT9v2Nb8RrAlBDkB\nfHRdOhwhcF7TCnh85ucoPzf9Migqgrtr8G8uA/mMezhbEr8QjgZa1i0Plo3+XCsWN7z4bcLKWxvK\nbESWGbRCbDxXRh2vLlXTlrKJrqt7Nf8FtiBJRUl6EPPL4Rba0BmI69JvljAh38P317fIDE4GOtIa\n9mBH4b3fi7i3IjZADl/THipU4HGXDKUo7LVhZ4WWooXNxMBYiHj2F9OO8d51cHckkNvwl4dDHfF0\ngX5x6HZ2Z0euPtHAxIAIvGN3a28eNgs1FbBm4Cj574vBPQ1sPztO3qkYdPps8yHnpZHu8LAKpnjX\n/Uhn45oxLvgkox1/n41E0uciB3IWvFt/eOXl1sE4Op++7BmN26/XUIdbybUof0JAEltx3flou5sP\nXd+BlU/qHvEJ+g7hhcBKwWZ3W/4Ugib2r3wlCRoKzqhT6iG+AvHfkBV08TRK6j9lSio1idWQ88JS\nTHQ+2lESdjCcCVAInngcchEjo53n+PCUerJ9L2ZC1REI8gmQnPT0XkhNUxwEg75EddN7xBVUaSIU\nDErm9gXrJvZQPsIuIkhgQk8i8CZKRfQibb7WYSuhc4dGRTCbAVa5NtFD9MSglM0bKlt17zEKpJEC\nVZllz9DiRMdzE6DzA3RxRnxsyZUYg+Rbqgy67o8VeLTv7GZ0hb168GMPVgLm2aoA+awycuS2nmIu\nBwxSU8jdhryhCanImlvv7n7OM9qDKeFnUHub7j5/vLqo0gUPKbw19DAqLrR/dBm4RiruWwkJL+Vr\nYaDpf63ayaEeAzSnD0cpQHU3ZCLJeBhnfxX0uYGMQNvJLhjZOUAZIKU+q2xLMNBK0s1Oj2SGLJIP\nB9ay9bhEDKNDG+q9tz0jk/lHWt+27PBZ2Orbru1IB6PGvcF7o4IINZ47Y61IJdvNx85lEXBrcA7B\nbbOn6CJjQB+T7JsIxok8+2GENpgNIZb6Bcgqp+lkWXRcSdm4Crhur5On6XLP3Smat8qdnIApPLs9\nbQbuEEgK4iGY0R2XON7EFDqcwpvd9HJfF0doNmYRnby4O5jr4dNWSJcrtpiL1SVKnyGhInFEfQHQ\n+DXG4xim+qZiObzxjxlE91J3P7ns/Z4agRzKnj4Bs8sCFphJUAtf1b8M6ki8+wqxmoorOBQ0TSW2\nfic1JdtlBxtJjj96bMWtzNWxqmdMErlwhYYmgLITsu2NM4iCAfcGKBZf5/2QJAc6KpuJ0YXmAr9P\nQDh8+p7+bfBMOizKNKsdDJpQoKd+BK2c70R8IalyjokLs1SjxebWlA3xdmVEjTqbNeiC6czWFnc8\nMh7lwb3BOc6Ndlx0fLvO1LygzG94HCJEuodp4BDA/XekIbw6e2jXryvJZNncxNOdSAp7NhXD0MTq\nL+eYms7r3dzLqPnTIoOapuMLt9z6pTGSFu4prxt3KfZEY/tg5m2xYjs5S3UTESqK8EGQ4Uh7mj2C\nmeTpL+NnPHN9D6Tcwlf2wKcwzEIoPFOH+KRGp7qU47u00mHtM1w0CJBaprBpNYslLWtgr73bM+TI\netuwVX9xMdE1iIPLtqDKqToNmwqLbTqYbDF7AhnuGCclTOQO7rKzXkiuu2cgkNXs9MDcgBERnrlp\noSmH+1XF5zy5EgDY/aj6bc5p8COX9j8fILa9GWyrAzi1rYG+qiFjYiaUKLyhPeYAdWWmMyh4i84B\nbKvDE01pJCRGteMwcLryJl1FlmrVWZXeKcC8QAzchBBp/Jf37YDds+XbqrZ1m5Ume42Oz+OwaVx9\nQEp0d3b8U+2JSWf7DEIHq8A4CPn0Yz0MR+6IFckEv3n37qebhFORndRzGMZYLwBPz5F+lDjhD1nN\nOBG8YI5McpkZKsODGLCYC3wWWtO9//k/syJXo3iJiTHAkaY3Pk5xdKwb9VUpZc9922a2AA284kJS\nc/w6K1tp0gLU0Mpr0z6sOE2lMiA9auYS/Ut9xt9km5TLfRwtApCrVpLkRpuATTyDkPyjw0zHlluA\nDR8qhNAd0dv12ExG7HMW9hu1wx2tg7gT6DB7czWMjfl0oWfOni5ihNtwEk6CQZd28NjZhRLPtWUH\n+FSLzUGO6SUc7y0gXgUKHWWu6ZLCJjuzVlela+dOL72QeEaZr9W2zZsVyJuHyVD52aVnwTT3AOFK\nn35NMxcXw8wKd2P5UJy7K9ud/l3TB787S29ZjoA3P2PfHD3O3ogtqpAvHFKHvQH6FCjFAhfTNKsk\nHErVZ+LMGHXIHVT6Z+l/KcDRafI2MULITYDczj4T/XSoW77h0fPEHYqOvITz9/+t1jS4SF/xhMpy\nCJ+vM1OJD717OQYw3I8AuWVAKbEFDmdfhO2gYi1hMuJLe7msDDDJmugXMUoF9mrZsfZexfV9i3oi\n23Wes31mp6gUDeJmUnRxu8vnEXLXkiWl/9u8IHC7E2XwWrRrQjWJ0kfamR8dvKkDDNULew+4K2sT\n56U8REcr3Q7WZl30N9S69uRhCs6IfmjziRSl+vlcdn4FfriLuiXy7muqlQV0Clg60PupqJcebXH6\nBUv3N+vgcEBJNag9MeJroiptA5SBkyIwauhthJkNyG9cjMvY+Y0bNjtsLtZs343tIffMIGKFux57\ntQPtlA+1zsQMMx1GkhXVLeWNpNUusFkTpgwJDoQLEOEi8Zp614efkCcYVhmJGzjWSCqabm/Gw1Nj\nJ4Ik0tMKnueBJdhaSEWWsyIg7gzCo6ojbJ/1WK3XZUo8cSbAmj3NpQ8f3K6RGgsE+d42pR/T303c\n/Z3Uhu2BKb+FQ6s9dIHtFotmPfqktj7KhthqO8zqlyNKxItDaisn3SMELHmsayGM/owrpF7nv40K\ne3ed0W7e4bQB4884HK+HliaLERfHqfd6sojXuwMehsBRnJoO8m8q7ahZ6s1LsWkB+Zksnu71S2zV\nHiUZFid7GiuHHiBUQ7Qd/vPMsMJp5bVtz9D4AP3I3dU61RrSKIdqL+KD0OMmiKLD1s9vfq/Lggi8\nyDYOXnEaPvoLPpgMT75wyaLD6A0hux7nQa5XkbPzjFu1KSD8ZwP3SxVWbxj4j/8Tzh4FywINBztF\nn2rzHSaTZJ//RC8teqLSj6JWF8TEBft6NrAKWOnkEeiJ1bjapFbu+Xyc0moJisEfKi0XSUhqo0ZJ\nvo+Nkd9+TnyKNuD7VUbg4gMLsUjs7mfxUIZOcoNkcwrH0C/4n6c2WEoFq4cd7OfYh/pSCxWV4n3x\nxbmPFKTRbHeiuvL8dbAskiR1ebL4RRpvWaeM+4p55Hnr3ivCoL+t3xpR0JDvaq6dyUHXNbah57hJ\nhOWl8WUzGzQ3liqx1NFx5loduc/et/E44cmgxsaUGPrg9EcyCZ3LnhBMH7HJyYsqKWSnevkH3XS0\ndlQkPwd9HJJ6GwvDI5twDfDft49yqpn1LCdAWzFgtEquhfGIISyZRrOYzqkfKkXNSoavO7FzqJ5u\nPXRF4tJdvSlIrbdeRCN/Ru3p5rSBg0ipHtF+YdGXE++Vo0KAvLwFCBynpEUwYwLmFI6ab/wmzDEt\nPfJGznXMlE77hq2SQW8HU0lyYvPYMGpxZxfiyPJaal63xXG4+I5HTlYhvbYcEtXEwlFDuFMuGhzR\ncryuABzlVKTwMFcuBnLV1j4SaflPSwDiIrvcgc59ZFXh1InS6sDvwvBNCyqeuySJLzlUVZ6wuFcI\nrvDc/zMvFRimVCFvYsAlNyuXRDoaH6xbrVJ3rp3Kn2O1IXDh1yB/RKT/G+2HcP5rvHJL3ELRbZuJ\nieInGchMdkenMJGUy1maicvl8bwhYOb6T7q++1RqjyDOc6kG+bGxCEwGjwsHMylLReYe7fA/tld7\nZlOvMXTPD8Wr+YnIJQbNBu3wT0m06a3nMCX0Tf8mPMOQeujDiCxxBKUNU1Z4gUkdM956Frg/AqGE\nK1yAtEJgrP+R7Z4492iBt89YoCfexnBVxaWIsHhy5oy0Gbec+N1pXPvIGK4yaaLUKLn39KYX9oT/\n2kRr5m+fbiSVE6RvSRlihIvzTM0ELxW661/yQWQ3SEB3IV98hF+50e6Qofx7DMLs4a3pNNPMBuGL\nD5lgohDSC8CNH4nLId9yG7gsqxXylVWLKrFltKhvWIIe3Uhb8JG/qQ3posjDegfujtrmpc2W7H7s\n/FvHykVCTUfdYwybgi6uam7nskMH0JWOGeQi/ReIQgbyqGEJ0skd5h+AUDHmwcIYx1j0JtWGV0A0\nmb646def0eNaz5NXkKFscfG/zjwX5yi8+knp6y1K5DqQ5gSM7PFvWO3gc6BzW3QOKRZhwHI1FAaM\n+HHPxvSNMHyntRLaEXef+qV3vRUoAgVTQpadvT8Er6GaRMyVtoPUBLaJ0l+r9Ab+DDx4oAJBQdAy\nhSmfEmWKxdh4jCVEvLIg9RKw/nMZ3g17ElSkyV8JmptZ64i3nwISnFKTqAdaEwoCIDxWLYgXRH7B\nmkzrk8wzEG3zU6gr3RRW3zcpdTqWXJhVVzF20I1vgVqvlb2OMs/D7r+JqyCs71YVHigTOhc5oAdq\nmB/cZ1HOdX0H/45grCiX/WF2SxeJFBUjBzLF+vzOpruChX4Z29SXujo5mumzxkGUkz7ODmqPVbvC\n/qs/p+SVyywnPtg+ST+2NfP6Qm/GvOpc8DTE0mxKNlsTsE2Zo/Q1esOj6yRa8GAagmaAlfvxdIr2\nqQ9GRxzMW6WmYX4OtS7LZcUTygKZ66tKmEmiDT4ysvYlpXwj8Z/+7P8/gKISQYgRttmULOT71oQX\nRIUxl8biceYAQqmhuFWA7+c814MC6h/TQDmQFXE+5lRQlFFNLJeTOxxA7v0x8aDRxs+dw+Ws4CJn\nnF7tPsB7rCl7FNdzKPRG5Inlc8b76YKnLHN8PmDIMofpVmGH3vxbUJPmvoa/Gp1iSAyeqyO6DPMn\nOBEifX39xJdcDRc2HCFkh/OhEXGomdtpu6jtlaldzyxjjq01Hl/LKo7Vo6FklHLsOoo91ViQYEDT\n3jMHPVxSWXXHW5tgH/Ur7RTFxAUGJYfsw5ZHWqXl7hi7MBszl5Q4Zgmw0BwZZbrjBYrMT9ih+TJG\nCIa45gtEJLuoelht5168UiFEo8HXwEak1mCn0NqAnOG07YO0yiFxOR3N5XjH66iljxcI0/oM11ja\nM3jpJT7sIjDAPnJ8HpEkp0YHyPFnokJuWDEvv7j+tcQ85BcAWasVgN2xwJ8c3kOevuPpg3LLjegb\nwedODw9VxVyFUytIpddFyi+Ek3Ef/Q4EszVXZ7wSrZdqVFjVI+PEMaOw3lVur0LxFWsyTaf+WtVp\noCkznzxdoBsTSh1m2znlZ8iufzwiVZ+2k2zaKw8CGe1kw1Iuhi7V5LCdWRDup+eGBrG/MzqR97hh\nFj1+K6JVm8AdT5y3K/iCHnHdmkrAJe7LAjTKAVM2Ckd7mP7mFisLqir41jGxjs12Roi28k6szUau\nbxE4s4wOUxEE+PdrvL4sCjamvasmS24xaw2+sy3UAJ2/HTHf7Yg2SnRGvXrOx/Y3cHbhGP+aDgEb\nKktD+hEx5ivKUWMjX0ekgNUtkg8rP6tFM1HT5rnQe4RKQs13OgvkBF3dWaXWzCRx+xYycevTNusq\nzV/PH1N3W2ZPjrNNtNqwzM5yWOftRUiKNzr2HNyW2KeceGx8l0O4hG2A5kUOSsT2g3GUHVLNl5NG\nNXshenvVTyNS1iwSJzE1mXaMxcWI8xX2ZFXCTTsSKPD3z+Vdgaema+3tVmX9SsUAG+55jgwM3MZn\nntgcXr8wwDDm9/62v4asp+IvfpDb87r7YPj3AwI5u1Q2vWBBPaGRYLUe1YL+KjVMZkTz7yC14/kg\nKUcmXoJMX6E0hYYJbvsr/GxHEmoe0yXgyplmD8z8VHHRqULysYtJX+BomMvdqMSiXMrC1ftqP6Xf\n5lJLt3R1NupQCDd2yg1r0GVoif5x1Cg4O6/MztO0ot4PH13EP+8JhVoVyIzvLTsaG3LpYiI/E04w\ntvtok0m6B1GB1IKYOdn5UhTnnOeDSF8yqSsJdT5+W2nf0Mw4/nPefv5Fi3tEWiKG6MzYu5gAKqyX\nYsM94IBtU4+PjmNVbFDMQqspJboqD93At71pujtI9Yyr4NGe2U7LWqH5DJFqSuDwmUOpkT9NtzIX\n6Ykdg9VGhqU0BpnhvO9mlizoE4kkFRju4BfRyAmukFgTSb32zFRJsA0LLfSyOVbAZk4QIQYIBNOK\n1itbIDXymGcwdFMDHIxFkuj4VBJ6Mquw0sDqF7vVqSSqeARjBK8VEv4fJhammre0ZyavBbU737X5\nUfQ7aLfv/6SCeMYcZYfIVI7uxuSh2yqrF3veYKZiiNavx8Ve7Y8xap/jMfza9JtAtLOt6vgnUjK2\nY0tIRKdGEigJRkc3RXVQgavCbuILff4hg3SLaZVnBhGWAWV2CBTT/gWgjyw/DI0QBukw2P0qTy4v\n0eO8+qeDpwkbzPkDEvV6wrlJwA+bxlDBBxmCgkD6jX3Wl3LXyRqU8D1AYPbJk8/Ai7kKu1dHAi5H\nvZZ1NNIHI4dRuS3IlHtfzaYGr/2+JmvsjNrtVA3Rtq1x9MsHAwTIOE6+2RYZJY/qKW/AhkByIA2q\nzSh1zpWYmq77b6nx/aONic35PMRSW2JCMY+T5HLVhjQqh7tW5eSGPem7IlKhn9sJgRafYJhjbHjC\nkENxS2TGESqOUIw/w5o3d6DnInjBwcCnoF5tM7l0/rhqkxV1NH4tnNEyw1Ga8uaXKvHynOVE6lKT\nsMPfCAlPSfWGZy+Fx8ztjrXqQBm2eIWzC1+5ctxF8z2ITBViDt6othitax+2/VuHm5nRlwdzHjzQ\nshIj1OgtYd2GkFvojf5/hG79QUoRnxDCmRksNc51B9l2OiMNEntpIzx+oPfke9ZOIK0ixFNJU8BO\nt2dd50MFHemU1q+yhgyeJLhcJk4NSlqx6qm4CDxjG+6WFkPQPPX+Xw1HshenS4V4k2yyFz0nzU6i\ntLO75/btg2GsAQMENk4e3YRZ8Nb/EBQo2cOba80ASIzOzxpVXq8pPqJX/hSMy/djXARzfibMu4Hn\n8m7Iu1/RBZf/X/W7tjv2NcyIWgMy8q0FsJN/i9YtagiuR1ZohjiKb0xkZwkfeVJmUXuCiyB+nubx\nwaT1LAYKlobs+U4ROsQNwY14dQKQ379GafZR1NtJfj5NMMXRZl6TOFaZBsxe9Kbh3Do3udKVzs2D\ni32A4mW8HUwROMXLUXpyMzn9X0rXvM7Ef9Ld0xY61wew9Rrxwei8YVlJgaXytu1d0ZPkJZR23Xvw\ny9Iw/ZIWOgvvmnzyitpH+oJ7hjltq4AF3QBBQI6Of5yvm2EwRCGqLxspPgxuO6U2+3yltWBjfnn1\npXTYyTSBLHdoWoP2orkWjwFfKgBMnimJMfhp6BsdcCa+1oQncshZZk5HtNvUHFcaTcBEG/1PE3yv\nFwH2oCdQ7DNsD8ITEoKwUUZXaZcDvEYju4c3FpKZMpUImMJBTjgTLhAJkoh2ZalfJHLf3IbNLmCt\nuDQhwJni81iJA3bKwWcauwNnhTTTkGz0BJnx8pgM/ttQKz1J+s4zap3Nji/DMKWT4bP4GCYt2zD6\nyIY8h9iyhL3bgmYfmFAJ5z6FgbJcWiN5//p95xzkoKaAmWq8bB/qHQKFcPEN3qsWcFmZg2v+lUql\n5c4sT5GQBsZOIaN6hLXcbuBPNUskEmv6opS2zLWsq8n0CAbB8kzlR853B73iImgYV2YeP69BCO8T\nHtlm57drDF7XvirIQTInsyLhQ49a5O3WPn2NYe9pK6sYyiclFE3efqqAs9oCOgmNf49Rk3erhrHm\nXoGcLrwaPpjYfKiDo2jw2BFgabsKfzj8dliDIyS0e+rrT60k/ZntazsdMOPTx8kzLROY0LUXtMu6\ntlXdWX5uxiDe3mk+UlYVmTu56F2SvQ47HAFj4BWEZ4q9MGTKtmt4BIOr3uongvsWnzQRp14uF/yQ\nsEIDOmaaIMg/W4x9FyttQNgQaFRJ8b9B08otcQLH2oZ9wqjZoF5mkuQx8AG4UbTOVvfe2yj3/kOC\nVK/OfyaiJLTL4Bk2StaF6VB6dz6ZE5fMRxXmPvqpGWjv7zDnNvXXpkllH+cuixrr0OmDO4I0Vm39\n23TIhJUPJt+8b+ODtseo3On3NV1tnoKcObkmRzFAQcwz8xSP2O/+Awqeou4aiU2FQL9joaZcqCMG\nafhZz37qUv3Bt446BoTiB4QGz/LOcEyXolSKV+IfDTZzJl7toGQZ7Aqg4wohPKoZuyQnfybaoCYL\noXLdIad2k18KpeEV/Qh5XI61PN6P2Zi31UWvQf73Df5yGbU6QJGOqjdDQqrEEWhF0Z3FMBQgmOLP\ntGi24v1xAMr8t3YtF6mSME9WboB+blOMgVZqx9tdaxxEMj6CAFR7QHiRldIPM9dz3FHcUjCaUN7m\nCg4aMaceWlW9RKackBQlqVfVIC3MMGKu9dJPSHa4Cs1e60hKD5QidTWc3OwxRXdPbzDOROIl9Ly3\nAnK8u8it5J2SKrFvh/AtF7RONh7hX6Yv0OMbQZEYdQRphuNG+/5joFAN0FViCo28VvzRn+U32gsz\nJFjvG7CBccUtF3/SzJTOCRmeal6KSYDWjrC8xT5nVfEN8ik8dDRdvEFlwENhEa4FI+JxEMuYzpbq\n48k4OvNbdsz9YcLSrhiMu+fpC3iC6wn0AcEsVFSewyI357cK0IH4De2iLHmwnC+kOrdMiYOkhEVc\noue7YWGmUDNCEvhGo1VDX9ov6rx/50pAF5ugzOd0600+P9OZQb61XCZNKaN2cRegZKbtthLaSwjM\n3dg8IRMt+J2u/TUzvT/0O/LcCGRtefIi37fdhEqwA8HXy5FQ3xL99QR7Pecn0mCyjEzQy/v0oa5o\n/L/fOZPvIyI+0r8gmjx84THuroakqvrOGC2y+O6RMkcrXBVv6H2yybbv8yWEWIni7nRisZ8JxteS\nxJx58CGqxX/JkjXmFoHwDXjjdv2yKlFzB5HMS7FNMmtBWwS+oSRVtglPJdMpU9u7F9BRqrtwpZK7\ngo781YZSBIV85g1zZFf4t96jZpfUkd0isrYhnPeozon4+fC7m+NFNs58DXo0NSSbORMjgVNyZIKB\nvD1MXkJULySUvu8QqvrHYlVS+TZCj5tSlt8IVcDuLnJu5sa6p6l9Ad/XlY8qzx5hHR+AxxguC+fV\nlZfw2KoXDd0ZfB2qbtbTtXTRrMbEL1xpX8rtksswuHMnGq5juDh7Cpd9nridkZPEiOauzKxsRRI7\nCVB8jfp+2vI0SjvSffxhG3T+/vmlp725nViP4B9tEdwoMtpgd81dIFSk2rpwdVVlayNE+IpqftzH\nEiB9gaK4fEd4+Fdv+177Xs9wg5T1xLxhk1rJKrnRQ/ob7E3PVHjRnZqbTn1lN4m1OE9tM1tEA2+2\nkcETTxPY8wLo3islGIiY1ixpRjeEQq105WXt3NAEOen9pxBSziJ7znplh3Bv5Jhfd4LE+DH+62Q8\nUri2paOD3ASb5LpWvWlIBO1X0c0/GE9yYkw3UT0R90UCvMSQeybhF6LpbIvS7Mj2N7UIDNktDlWg\neoIj8XOGvhC7rulio9/jhvdoMMXW/BGwffJ3bvW6F1j8ofBgnNLf/sD2+CBwmShcJnktV917PB/c\nGkwpiHYwifvb5QsxDC+USJ/6bS618fIluvgemawe96FOvHXuOeQBO+5AAQJFrv6MOETHaBLyxkZZ\nhdFiSwbWgyJC3tTQthStNYQ2Ijqcq8pTeVjc97GyA0FKJAmWDs738KR7ADaCIAkqHkAD0h1MUnR9\n+FbDRNd3OFbCyEZHJivq2ZprIyi9jlHy0wWhXcjpZQ8ol+UEjQTNjbOG3zpMQoUn113I+jr0Gc1S\nTM87ulMhgtzr3TJ7yKkiezPUaUsGLNkJulnKZEben0CeifLkqxfqUkHJ6keOY4liCtxP6/5Q4+wO\nHtduaKRT0bd1vD7Qqm81MA8B09mkDjn2wISomez3owX/JtP3v30LM4K7C7FcjQbHPR49D28EA3BC\nSofi9nkwue+1K/ld8/Bp4ztCQAyHBZlPEpXaZletvBOXNKVHythVgvrTcQbHjUFtOP+9sgM5eL9/\n9xE8khHPex2eMJlYRYEKPrB+RnCR4F3kLYhSx6no4JF1QZ244aj1NXW1NJE92tzOUv7oXvUSAjtI\n5NlBtojAsBX6hxmiiWktePYzERylLrS2omlaxpcwptQEhEMmJS5IfIZJwAgRbCUmX9p98mOqg8+w\n9ktHLbqhVXGf/VbQ55MtRysucuCbFGSbHRdwch7bzJxArfGyxSrFYvM0x/RcGuQ0IweJsY3RdyHg\nFaDJUVNOuZh7yQ10Tca8Y6CzPWA33cBrzqe+DtCn4xWfVmsJwH+RCrljc/+kmStNrPqdFIscSq8W\nz53TCfMW+/r5emiCGSivPAgEUkmqO9Yr1zvHlr4ACSLSHIij6m0KFFoY8KgTPji0vV0i9UwEVr4s\nndgKGEl6X3JoHup/pIDAlbDW9qpn9zCldTtqMDkpCIFNn5Jzz/C+aKzLPDkhkHANF6WBWgl+k9ng\nJfyDERt6EgaSw3jvDjEUGBLWY+Osf4EUumh1zolZ2WxfKIZJ+LGMlk45NeP2yNtb8eKIHUjfhDuB\nAAL78ilWKyuNeSNEneeEKkJkkrDlWGL91FhvkgJiOVKmhuk1imMe2W9Vq4nf6LmSA4Gd4x1eAQ93\n/HhGxwyqJXiSTYoajr1ECwWCZpGCDCtKnhZbEaeklNh7KnPZip/UiId4U+Ll5eG6X4anovlPAZRX\nuN+BRI3VL/HAyrXrkIeFc8Az6/0y9X31vvZlo/cVSWP3PJd5xmelp/FdD2tmUCBh3HE1kI8w4tk6\nKnk0Sl4a/xLXX41mvrJcZt7UGip9fNfOxSoshDLNQSHY0ZZWzwK2M5r2OOE7lqrYEFek3r/sw8Ig\n4bo2+VUUYk8DiEfP0Ug4bKeS+tJk0D/h8nP81R8rz5pIjiZIvTPW4qaL3xxzLNIkjNMWKnHCVA8S\nqz3F6rOVLcRxizrNh/gKRNTTobKB2QU5le5EpNTqZi3brLiIFrb6j1WgRqrKaW0w+E1Hv5dqUmAC\ndygR5dP+BcwYOAoEb0AIQ1Leig19elwk9eQqk6CHHnHoizGmpwM6wWTvuBscCYGynFSduqniI3cD\nX3Ychq+IdmsbN4Eia09nMLa9XT/fgQ2NhHqmr0hhfHAAGsCIm3EL3SIrO37rLXaM9Tj32a9sE8Sd\no131hv5Jqnl38gB2e7gywOI4s66Yj3/gijchJUOUus4vPZ014cQOnwc3d24pRu/LE+c0Gd2h7b8h\nYiLxYPzxUKLOhOcV0ng/k0dVwgwZX/qtCqLJjIPMWZoKBl9XSg7obLru+lEBnUz6UDcynE0yRAn3\nJ1oHW6CHnGACh2ZHMRkcnR+yyiJOaiTDBYoNhUjJTvuC9JF3wK3mMHo4s+QUKIeVuxN7/7EW2ExH\npSKwlBwWgU7D1glsfu2gNUr9AXa37/5Xj4crYCm4d00LBssDXNw8lTV+za2l/ga0t2pEglG7Iq0z\nV8osC9aVgapXhnBeagIeBGgY/8HedP/j5bUcRcrbCXoYqWLDJf4IwwoigyBL7TQhE1qG6V6O21dk\nbeYFLG7kIXwkr5uJTFy93OwTLh5V871nGPNaVaGP0DdMNkTmOlBt5beUabdqElBWxvILKqOr0ynf\ndBqxFbUpSHTxH7beZxZQfgNPu/M4V1A8KY7L/t+HT91HxIP5QKzr9xxkPH9LclB7bfJLIagBQPDS\nkggrpbBnJjtJUcWyEf++hLMI6rdTXlYXw2Rv098jxz8PBtS8/0WtAesiXUQ5llqkMq6BJh//cbCL\nsq0efXDLyFcJtW6TpSy5YyY7aNVkjKzLNavaN+mANVospWckzBwgT1QPt2olmFsuj7JFeK4Zj/B2\n6F4jxR30unHQ4lDf3ga/HCQSpuL4mJrfNyzlEK7F5fmH+/s8UlJGK+DM4CkXv7Q0f237spoSn0dt\n/TI2zupItZoXFpvO3flbGJYpheAA5zhlAnTD95j6twP6V+5BOzZA4RYKW471/7y+851slUNQaqXQ\nCIp9B7OxFjblSZpJV/weOapzR9GGu2WUL34MtsBCFeaQzFx2MLNzu9aSthoU/PyiFjk6Lj/wLaN5\n+zyh95016WymScCXr3F2EFVrj7LC/FwmkAEIDVDNwfPJ9mpoiZ1919PXirdGiVkPuOHPEcMapDO3\nsnb1NVvSkj2CnbbZThL0GPImnc/t3exEY5SXPx6ybzj6T94UQ27BvPByC7kBOD49wmuyviRXcl2F\nIdqUOSbxaaiH5egftzelDJOX1vzyR0YubGDtY5qv0Umxu0Omqb2Xt9TMZdYumooKtV83gZxHVpXK\n99GAZz7+qyLJ9F/AWEycCeWMqgBIE9erlLg/tn0sN6avwR2/nrSFNLc/EC+/bGOUqJNj8z7IBPGB\nfQ8zYY6PrRwjmqPZWK1+Jv0AUJSyUZhJmQcLbZ3Z+Vf4gcrML1Zn+OIEWcvmRV0uMBfgANh4GoHQ\nooR+sgjc3g+XA513j45GTEqX0J38oIjuuejri0o0s1qV3aX1ZDPVFs+iQT5SOlBgaFzniZFnVR+W\nCJMWoFnfp3lRaIAae8dptvQ+z1lb6WbF8E00LnfutS8fEYN5BAvFUShschcve0aNbO2Fd9ZwKNou\neIUdlpNR1xw2YRi6sS0bsxHkj3w9dAhof4Ive4XDr+wdEZR1dcMdReAFmPe4r9M8fAC8TcD+ziCs\ndAyyiXjiTseYpE/SqL45QNnUX8wU1SY7Wkmbj7qB2lFEudgCsl5DvKwNnwf7NPmKtQp4fUAIqbUY\nWawf6h6LleeFJFFbANP6KS4s18rl9e7q45eRXFkkz0xtSYnNtMIqRatPqfLqaYYHtQVlgdJCV+XT\nyxBrVvKWjtS9dGambh+xqG8anwDRaBsvtYTPFjz4EK96d1dxSwc0cs0RZjzQWzJQX2MZkmVDrH9b\n1IzsV9C4oh7jpnOIXc0TE6wi4z5ZmWJDp0R92M51XM+2/JLAjTcmyXbZC1ZjT0uYJasHG64Y0rh3\nsJwZADr6qIUiYINbRVOTY6U3f/Ef+mLQdp3FT/uIg8zZJ1i5GPCy+N2QtXSl6CYryLARFRB36LaG\nUyv0AzNpTVkQ87Y6bjQKXk9PD6vN5epC6J1JmAnmvqK+MlsOBAhm+9pDIdTq6WOAyNFNsuYuo8Xl\nBx3fvu1Zxq2tumbbRaA/i8EDFX/m6ykEO4mFNU3Pl8AV8tn3F3Lf7D44Kmyyml4G5sW/9BgPRbh7\nThxIO5EGz5VFq06zFacwQLo4pLhRBzWLoz+UTHQ44EPlr+3tHCGLVCTWNIge/jchsyFhcIyREanS\ncZ+zNPVhYNTHufWAbKLcDfc0yvqikPWjy3YzXgrbodebfAP/eirsaBJZu8NCQijcbn7MqRiLl6L2\nRteTEVsUyGhODDCfc8VHTiB+ghs3tvTA7+Lc+AIh3t3hNDVH/PH8akeoG7vA3ygHGO0tq0aWP7bp\nduwFCxjfG5L5NaGxRRvUuxDAMgYGInp+NK1+q4jQalIyOLj0kbP//qXFTUaZ9n7Bg7Dp0ujKcqcg\nWv9m/ambWSMtb4uOOcUJT+ifnHmxRO/bOGJGWJ2XPiFn1EtK/ZpyFaBZE9p1wmm8hONEAyILZwU0\nInke7A1LhPXZtTe9ocL6HpV3CZ1XPdIQ5s+iZvjkez1lXN8t1Z2v5BX6rJ7LgqcOR9e7MIgeqr/z\nexY5taAnpUhmG2oIWpNjxhZkKyZkhjpoJu3Fk8j7rVo8jphKtq44KyhtWEk8kL9N2jjzoT7uolgH\n+JObgjkLvRGUcdvWzfL5ag53dRhXyYZsMcON0z9wJmh52pt4CN579yQnbOpGxqSGRmxZmyhFdqeV\nl/p3Gik+8kOPQ+gyvucYfwVhItuwMC06eQ8nuLiG1OJXO76XLRQvEutgU89ZUaZERvWyx0GamYV0\n8nHuCgqCu6IcTwqlQLhrmqM9wsjF/D0T6x4EENrezJNhCMo/69srqn9pE3e5QhPeu3yH3aeqQ/Y/\npYaMArkanCFNUV7TlOHYcqWP61nPzKuVcbmxrpXHTHLQ+KObmfOe5D03iRRGxRl3Aoabr4MUXLSV\nmAWsk9JbnNnBa3oBDusnLinaCrewLFqWjnSmsB3QZGVyxEZGV5ppLDHayV5+Ojy3YVHSdq/o5rfX\nELHj6S4K1KuTvOKug2G9AO6DdldTXD889WyZyJA9I2rl8oOLobw34Z6lr3RqTqZVxeN3/qkMTmVN\ncH8yYWfz4Eejs05L2KjwOOMy7+WWVSDz2SY2Yt+hvoZhaSYkwWipjl7C9s2jMkePlTYRFsCuG4bH\nT46WPqptd9DjIKj0G6IV8Nb3EOVRMCou2kHyEsnHxaK4LjC1yHDP7GRoy8wGHf+03rV02t3T7ZQu\n8KXrObaY6+U7BMIMpvjEmouWQBSg/TeMV8gYzzjMBCr1CjU9VixPiJ23jAUZ6PC84twcOwrPjtBJ\n9Ps9St5u2HpCF0R+dQEiukM0q+ig6+ZfxnqtctaveuLes9pQh6VoD6n7YWGkwVhJWn7Zcl4Xrvof\nb2EestQavqVV94EqwxZw+J2l0wwyjStduogZ5nR465etBuSmPyqpBEzFnv9m/EnvbV2KYdmUy+Hk\nZn37bG2q5a9Lf2SCz2kDknkESUlUo42vrqlIJ8ZljplfrHZvylAgNE5Dp2l3vqamjiMsGkmp5QX+\nc0nbzSWouRIuzsoB5gO1vkmZgajbNKZNkOTjXn/02QayhahheTOXQQ34eA50nuUFBIKcVSk9VdjT\nxBKiCfJnXl9rbX5mY5DOCXxQzH2XNyq7O1f8EUA4tXtYRpGUQc3tHWdqhQpvQblU1PsKFkGT9qCi\nJhg0kt/bLsRiOrKIF+nFMGNFLXYB9pf2+d97R31NRe+r/4AYED4d8y6GIOCqaplPjN2GFmdJmXNx\npDg/PfS5R2trl040plZ65yP75D7vqwV8RYw4R74OX/KMt5rkub4heCpsFWaFwLmPfDax9NiA7uMR\no5AZrTNt67CmOlYKYKFsxPfJx39EDQdqIoPHwZsaNCREcbF8UnO/uuf/stoAIMMKzOYU7Tq7wk1g\naoYuHsh1zOsPq9M1dsoLQQvrIVT6mcslB6L/Ya5HfoO9xLwShFQJlDn2BFP2bk2ZiDwWPksJ5AWQ\nxPyXvs5gEI7K5D4VUc/r8JRWeTKahIZC2A5uQ2l8VPpWfYQm4fXmMOatljtRnW/jUxjHT9oBNKkD\nqVxOF7InA9LrqEPIf6W9F26Jn9Je3Kj61enEkQT7N8C0eR5BO98mUBZsaTHA9eO+mZ0zY6yBHH9w\nIZIhemVTpxVzfFmz+eyY+2xzs1QnCrg45RzeEvUu0GuLNpkx3xg2F8iVk3kuhkgVZaYDYxRQML2q\nB5GxzJuw/4Po04A+WUBVanjXT9cSSB/HkPXdN4eynZIYzpLITcBi9mrSDMoFtv+a9I3cl+O8DdCa\nqYUWNoqWg0JsUYcTLCtR/Cwpe+rhdBoyr1qV7Pb+2kMYHZ4CPYgQqlXzIpsustkAlJjiy+wK/vBl\nfzqHsdM+VGJuL/5Pvx9Z+hmpNZ+/09z+Gl4n3Souu+Zna3gXbBPm9hTEjkEAHqWRmKIC/tcpnWu/\n9m6eym927TklGXpNh2gKnbXQMxUcNaVdt/EyYOGaE/X0Pp6E21GZDj08HgjvlSRZekC2FFww9ZSL\nFhZmCjWUr77qriZfhmaMYo38mtWIC307XLh+385Y/ByGaQkEbR//qCjLSMJSAOi23zGlfD9alyS7\nyzSbI+R1nKYqR0pUJVAv7NnRxVW6IusZ1SyRxgGDUOz2nxVk6QmOQBg4pn4OK1/hkWkCdalkr5VO\nle3IXYWZBupCe/B81dhLl66IemjID2jk4M0Fob/2a3FPpbeoiBIU/la0Ykmi6d0I9RMhyKhDo1NW\nH0kHSRxDD65uGyhx2iasDN+oCCmTMcVoJoAB8ihQBapgDRQKkiJgykvor0GVGVlJHThFcc5sOknu\nEcHXIM5pDSiYilxbV1hOiZFRi0zfKN2C81oXkcJh69IWA7MEPvKhP9XzewiVgwyw9bE2DTr+vqKJ\nGpKPhaSYb2PCf/xMOkKw/2IxZy0DvldZQIz/H42mRGnxqK6GJOcbc59J/CcZ9wicZ0vlX3dvdCSm\nG/tCgWlIuQo2mBqDLEoEyrSrg29yjYYQ9PEgRsJIeh2C2wK15n5uJ63tt5OWr5DLFThm3fkQbXgA\nXzkGaTJGsD5Gs2Tx+fBfn6UyTOK1IVwPAN2zlwML3qEovVHmxCxxqtRzmdIHf7GFU+QS3eF5ypJb\n0Wkqgu0lYdjYtGF1HqJZ/w8g4N2UtppxgUKvgsuArP0ddOyJnm6Orag0C+mU1jVJOTLJsZK9rrwa\nVqnj/xAt03OsMP7FfJJHDWN1iM0JjKx5TLVesJsyMHgC3fgIwfs1WJzkf+Jfi9zmVIQRRq4r8iWC\ndIy7DQ0oHJAiYGNlibIGm0pzBxeWw4gNavG4UxYrnq+stF1WW1gQ/LowmenwG0Cjy8d+i8DiU2tx\nqE5kkIRLYskE4J6IlQRKWkbBdjunTe0d0Y/x9vFKR5vbTOuUbFIiw4mrAwCCuC2x2SudYBNzDkAb\n9mqrAKsiJW2MMW3oV8nAwZmWBbAr8VjbeR8fRgoB65KNf98+GVk5xezWu6x/lnr0CSqNhgP8Aa5w\nQB+C8B3rl00CAv4LtcFA1OSpH9mVbGJT9jlNU34s6OS66nmJrHTsunWjWwfVT/YtIc070EwUHhu3\nkerJEV9OAsm2mblaCWXdeH3oJzAWOt/S+oMvNdV2qbdpyyJLWi9I1SxLtlFBqPLUdAhPAkz1jsLo\n2NRCg8YRSi+yN+uNbNtBQocjb7uBxCeT29n3ml3LzabvmlOf6To0cuq0SNOzxR9EqwHpiruBbcoa\nMBc77aBf1a+9UX28gIncucc0fWsN1jEkEXvx5chO+sTft3RXfVehJrpbpg1g8/SV/s0KS9NxY3GR\n+TNV9hAIdzH2xpxdAZA8rSqKcNG8BWa97giCGGom7uEEC7G7iZs06soDK+AxQRAJ+WmZZyXjdefk\nS0xqti/2PLgu3RiskjNwJldrE1I0uHPnCXTr+d7iBEMi6hjRTrVY0V1THygB5Wz3ABeLA5eOOzeQ\n8Vi5uyjlKB93QlFWHH3lYO+j7VPFOcfCLG9spKytNXO+3ZMuZYAEh/nurWu4ElE3s+omZ4Ov2r46\nEPwYJkVSjk2kGvj25OW3am+nVgLQqyod3R4eeO+slIxDIlI+vEyjLr2vXsUl59o/8nNJajFRrNeC\nQBKbaVlwgeYycDwQiAAlX7U0TlyCmV8LvO+qMuJA8nURMapsXSzQ7NOWsqrGyOWi5RpvFeLBpYJp\nlpXLdwJeAfpbP5TsqK/x2BBwqCw5+v8ts6eJrk7ZnXlkdQFfppkElqUPdjJRdrtJljlexJUV7l/S\n9EDrkcun2vl4KeoH970x/9UwnhhlWeos67t+L7KIn/jTSKVLCFzmgUCeWZOXApSSksada+4I4AAt\n7z60FhuEx6Wcbv5oZ1T1KOEQG7No24iw6ZsU+bkit31BeKNlNlf9iykLR1hA+9n4s/SHpuFH5j3O\nZSNjGYijauXyMyTR4ixS+lSVSyrpQkorw8J0EKC6Gj9/QrLDt12EFhqRc/lDsV3fcl6xs9O9V8dY\nA7lvM7Wafixk9rc43bfekx0ML7M7XG4s9WK3csfpY1oiMozMgqXOJxKD0kuzPssANEUXQ/D85/G/\nnAGdrXqPPiwy3wr6+JocvyteJL9WBanC4cihtz5nna5s1tFdbiuqfysaBZfzBV/6YcTDZKwKvTgm\nqZhIglOMJ9yJqyfJq63r14kkxSjwQMWG3RRiWcLLVOKSZtthZfeH77m4D41miS7Tc/HemOyqdMG9\n7Mw6ogHGykZ/Y7w7Q0wt8JRsdQCYRQQ4KdGqy4hgYTg64Y3Mio7eARXUZoVzr/CL0MIkbX3qQrSJ\n848dCKoRD/hC67cnMPZtbz1gXdq2Qe07Uf9HoKEBU6yOw/Gzj4NiAuP0mSKpjqY0J+M1wrQvgEvh\noYxui0aJNJD3C79rW+WPGfmfHlhkbxLLK4xp2Qbd3PTJR7sOAXqMjlWayatca8PLqsvo3/SUsDOd\nact9UheGGJcJzsHrFJGW4uJVKPja248SGfmB1ezEknT0Kn77YINW3YbBKksXNzXs/TRZwXPPmeSM\nillWe9EpxQsik/xmmOYNuaJZqBpJHWsO5zviU5Cqmtej8YXYjsiUzS0X6nwa2joG55fD2ePKRs2c\nD4kZc18LH99zxLxqlAqef7Z7VbPzF7rRytYhJo3++aDb/F1okJvnlhcWdE8oivy4CynFXCq34Dzk\nZddT5JfNqsqbsjI+Dvnk1g460kimaqtZiSlBWjGOWPbO5Q3FefJ2yYguWtBjOhXLkRhmtS3Jqkyq\ngaB6RKaxgzhqO7fR+aeq1r7dlFxYg/rwfgT/ou0hs/cLKDT2RzS9IeUgL82bZiI3uwApqaOWHjLf\nYSHAEZHmujq+y5+hiIUudFbVXYop0+n9iz8D9T08Y5aZ8XX3jSHKIoP+lzADFDe/st5DYrqf2V5W\ncYAuMkNmBP5vJjfK5rv7oKycQAyZpdD3KKir++RKXBz+ytv6KDZ3ruKbihq3P45XWbI9LE8M/NAV\nS64P1J5LKMAjAAkp+vYYdgjlsVqQL/Xbuly/xdraRbc1pRq/1hjWinOYOUkgFMajLAThGgfpYUkE\nJgYiVJsGajIzDh/jbbxj1TYpCLVE6S7b+OmyVEZ0T/xfxVDka94tS8QhS+UCxIXrIBfU5o/3SQ0h\n3vQn2lPeB6NmP8skmoExA7DVm82EtJ+we2cyJ8urhAD9sVqsW78f4S1IwcxShqM8Tuq8g5BgivVO\nX3JMd11qi6nKODzvG//MJffmArwG12IWCeAjpSSYpaf+6M1NIO+tY/2ZRIBgaTyaYDoaiQK5NVY4\nmYcA92h6QkfdvQXPFJAy4ys/CdO1Yrj99gjrzF+9+gtH5kj5guAt5HCh+4eciVqTfzSfmJaPLQlj\nUw+nQLaoq7hw9DWAfCut81PbxqUUcrVoZYdkhuFacEbq1fsKdSPr9w==\n`pragma protect end_protected\n", "num_lines": 1194}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nCgyLps+SA0ui7dPkXtm83wP9WSUpTVOaNUUaEiTx3o8bDibppEo7uXVLsKORYUGbahjOTDE6kwIY\nyzdcsZuJjQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nls1ZVg3oo/4jpb/tGSZ67UhcCiJPRZSibleEkmR8FGMVr6khAWRoF6kYXnp1zsyHU3zpkX5aZudH\nhQIPiuWIX1ItHdefmGknlXR0g8ejEjnCuf7wiNI29U6+5iw2QftYNsn+9bDRp5kdheVUcuxELJlA\nXulkNd/ln7GkFepSqYc=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nB9jNLech/g/tKNMUKP6f+gjxZsMheNAx8UaJ4vLJVXHNXpNxk91NHRM3Xm9hGCv9VXOliR2a8QYA\nPQ1bZLU5blYqH+18qF0ZF9Jo3IiF0g2nN4gOYAI7m5j6VqkzD58XFZMLPANE17Rohp8jENs7nh79\n49oN+0loRI7XCt+F/XHBh8FH2rSJmirxDK2iqylD74LWMeTBokuvbg3zEGTXe5qvYmMaRiXcTPZB\nDS3JpPd04FW7EUk+5RM0Kcu0Ly1TuyTKFn0mEksltOKTCKOerop73A+MOzn1eX1pf23lWhgzfN8Q\n8HjhN+i90Hmn+Ojdq+WsQMHc6+n0Or8KFbFReQ==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nCS3PEjLSMy66Y5kMQ0y4fL/X9nvJthfWlN6tOA1JzOyIwzumGq0fkllz2YtjUH+WZKf3DOAh6h50\nM/7oiAgx47vujLlrhLAvEpjj8WUfQd3LXqVk3NCO1ki3s4QNBrpCKhg86ykdPOiLuEXDkUt3v04y\nuxmO8exLVDFMG+CzMLadbS6QzvWCMXeAb/FFPfVqwPMMw1ByBbbNZPDHX94DLgrF41I4jklsrd2r\nI3FoDtv57i7fvGeyrplt+iDFl8lNUqFZyHP+5+yvGYA60xKn+8Y180eYGnmQ4wGtQ6Kkzn55UAKq\nBjhfYJqchzaFN68doG8FMNl5CP4MfMmIG1TAbA==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nnQe6+EVbiKYI6EF2Gkjs7kvdzSmGHXU4qtFfR2dYFwHCWHPPG8cZ35Gns8SCNITeaBfeRRFcv/q3\nUoOZpWturDci6dtPwvXGTKFk/2M0wDGp1JDGd5iTwJk4WyDb6tdfibGrM334X5OHFRDy3qX1Uovz\nSj9hOU/EFGjRS84ag4TVcz9z1f1Y+CgW8Ym4KNOI8D0oIv5DmjP/nJr5kVGL/WNmhRB0h+vtCoTs\nUcGqCPC2gQnw0GIBNKrE9ivvsGq/ACxJuuSLwAzquqUInK187ExgWQLiPHhTH6pfZDqnyZpMvGrr\n9OumyGggkggl7j/JE2vtz+6aHVWB1956RXcbLA==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nVPB71QTo5TspzkUp7HQwn2zfRQ8tDgsnLTLdZIsMOrJ+Y8fHz9hexHBR3Yhia6VnY8XCYjgPbAId\n7QK0Myn0r32s+olwHQ8M3jsY7WJNK96AiGDDRm0HHR2rAUT0mbjaG5Vdc3kGr5OmZ9abSnBv6qJl\nd6qqhUFQ2fTIk0vkv9s=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nIOa65t4pEqSGhDPlzgVIxaBhM6TFiSGG2C8XLJL6CyEFm0OzjlVbdnJuVLSSsqeN9g9q0ucPVcBs\n0MDNHCUMFAPmUvHCALV35V9sWsxZnNLruGv6jYCoLT4RcYb/Hskha3PIaIz4tnT++Oplm8SDc6KE\nj0p7EoQtGWfdUwtiBHuUQr6oMBdko07oc+MLXZy3P4PwN6CMYbgRTZvUcrJfxR1JLpjpTlr85sRE\nQCUEGnVHiSu2dgyZ1oOqfyUJGaHcNOM13rm1E+h8I++ksRVlalZKIcrckCfC48c5nJdrthR+8rsa\no+k61kcLH2NbhPC9dAejCTOCHyq4j6eKfXBGGw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25328)\n`pragma protect data_block\nkSwfaOQ2lUKsMClQk038C3qrnU/w3gNGhmdlLNfR9sWwqt9+mhQ5FChgk+V041Zn4jr0vEzfPK9c\nu3LNWSj7Kuy7mPDQPF4wc/gQY3v1ZqRVfjn2zXECRESZ7SISVb3/zgxGap9q5OV9OP32RkaV4kdr\nws8IbzNgdjoMmUEPWIST7YMeljelbQVuNUUiauyLev5wd5EZQgjtqiLEePwttFZFz+wDhSrZ+MSh\nmmVhsv4hlANMdsmgswzLepN8QpuS2x+4bV16nI3UsgySXVY0LRP+KYonO3zuI7oGlDGAKq7rVAA3\nosLmIrbqcv9oa8RF7mwv8MG56fHnNtMapNiNUP5a204RBeFO8tYuAT8VwFE66FWyg0x+SFytJzKX\nnDz/x5eXYt6o3ivPJ9zrCY3V2GzhHa8xLWUdmY+f0t06M/pjIKnPlBKPRL27dlEboBL1WLxjolrb\nZFxdGyaOrUIkqkQm8IlHVFmnZtXeSYrONP35eMP2kL4cGqUTusPeoqJ8DoPv/15TbKPwDOmaEXYn\nOEGzSGJPYZPw4+XZbtGAj0kRbQ261OYzNHDs3X7G23Gf83cq2BWgy5D0KMg8x7egPLMpaWTEJFAo\nwHEzBZROkgZBRyzx4uuOLJAzJ1Ww6ceB1GR8wqI1RSlj8gKQ1TwofF5FVToWZLT6C3Qy89q2zVS9\nA0mSl07IkvpxGwr60pFS+XBimis29n5s8FX1+Y2s6ykhocSOf8NQXfkCEGy+ol7sHN6ItVozii4Q\niSDgC+BYBApCgZz8ak4UXWCf4OdR75O09s2dPW1NNUB0LmDZ+JYg2+lHMwwfQbN8T9npoNochopd\nGUxTp/6OzrzXYuXdCTP14tOiLSckvwYVGLQRUNEHZFUjoAyI/K/pit5jx3240OUI/mdlbVjdEtUG\nZyZ6ijoMx/CJC0RWukb6rnM7lnnhpTUapuQNw9WieVmTSHV397OKlU7n+hVDrAOVM0fnBQoXDeAC\nPJlef//l7tgQN1x1eqzQkPGyXOWazM8DwiOoFa0tqkAslzrrb6K+PMxVs85IisOolgJv4q2sSZdV\n8RYCZM7MjfQlQzFbENfRZbZsAYj7zqKAdfnblfnQtX2D7QAAZtAVZbtICaIF1IOSNnsCi9uxK78Y\njHAC2RNWOwn/P7vBzImG9xwfIQ3kJklicNBdaHlR6kV22DiWPytbzi7H5Yh+1OnunmSMF5aO/a1P\nglEwFosYm2rOGqobOtvZdtOvQZbF2TLhNoCULxpUVohVdo53ERTsmRP3+szwtxMpYpRMOSIt1tO/\nmsxP5ho7MgE/Cc90lcabOMXU6TwV9GMz2Ec8YIMp8yPLEuaGXNyAKwcENA7mOQabA8/QNE8TzFxr\nzDj4HnLuxNA7bZFjKzEa951JtnbjQteNvnEOqy3O3vneTPebf0DNwD/PH2HzUyztYeqCd+4Ke4dl\n2XYcyyJlr51kmlzHyIsGKooMqHJz+hNY04caoQWD+Ev5YGjEMqMIxwhmZIm5te4ZzfunIO6qNTcU\n43BM4NF6J3RO7yg4ITHq50A/iI5hpAQKix4j86HXuGTgrvH7bsVcD2RZlv4gBrOkQU3BGQPAJeZl\nd25lZzULXvWYJCgbaXnlh+1h/NCjB/xX8TnucsxmmHdRBOGDImMff3FDsIEnGC0nEiFLP/fR0vhE\nog92bMwB4+f6Ja/JwPj/hHsU/Y7/vhRpgrJZFtljDVR5p6SPzfqZ+d6oqCyffmOU1mzMzEWLf/T+\nlKoSQNrcH05a6ts9/xvttvEnJoUmUf/H/09aoExwqbqLqI4rb+nzL1Mij1Mj5wjZqg+RzpWMw8fH\niJRUlCev79gLIKjs14oiBS/tPttcY/zs2qHsglefkqtfKIEk9s1OKKBE0NXUYo2xaULzpfqKFTo5\nEFsbG/eTmyP2NlgcNGiGzT4KFsKcX7sZCgsrutPwhhdzOBA/8N+CfVeVEsdrP9sS6ZIQs7McQ/7D\neNshaOGNMbXYLbebelDWqbszWYtgfVphDQs3tNtemJrIcmtApxUA/7VfLQRaw7D19ar4E8ozZz5P\n52VP5E6TvxR0qnt4C02mR733IZNNNYzEN62jdN7lHbe38BYdDWlVSjQ+j/iu8H9Uw1c9sRKzhMvt\nYSbje5593WOrVBZd8GSLK+W2/0BXU1rU8o321xmPD4KzgPFpNqOVlFZBVpuhz+66JTzg0dN+hk/t\nFZhN7JfVIRWniAPyHn2JDFXcGwD706qDbKu+155s7n+ZohU1JSwKxTvrORfYyvnLkkGm7fJQ7YRL\nt7BfgeyatEZYG14LIXAYjvgfjq2wtToa/TvQDGhvQ4Vm8nZzgWZcwGS7TJsxAg9p8hrMrp6rWD7q\nT9p4sQFyZjXkeGQMbXKNj+j76S+MV1+ZlwlpMQmax83Q8n0eG6krBX8W07reDMXwDi/pfHZnR9be\nwf1owb0a9mwrd2uTVsyua6HoiqBX3Pal1FZOUICvgzVeRPQjtX+5z2m2bTFa9Husd5qgJtC018Kw\nio6hzaTDp6k0pEhuNWKxCu5MYR5qZsH1QhQI1Tvc624IFJ/K3Ay7xDjun3verJ4OUefTvdYz0TxI\n3K/tmfQB5VfrezfWLkF0jHF8SXCf/aAil2oXjvKKfzIV+wTzXtKohwD8MEfjITbrP8BbeHj4Qjjg\nGdLwOy1xTGJgUSS9oGRx2/393scsFP4J00gbt2yy4ZaVBbdIV4oPk9/9nJniWlCNrHYcY0VkRd3s\n2h1bfTegZQUVLvAzHmVWExqww+QVrN72GuinDns3uQJzkjW2oXpXU1+I8K/xOe0aOZgVL57N1lkR\nL1i82WWSl7WHMwreThqjifFVASVCTX6sg/1eVK52Ab/QWUmFtTRLUWIOVBozlcWjVZGi0/sDgJfM\nXBSZLF6a9wWTbhObbri+/RP2EJDzxBS7ImjPO7YXCEuHFqwdPBxr5pz9gOmjeSWjbTU3TD498X/8\n7PjURq5/I+TJmVdTEm8qoPvBEILhT17sOnZOCqN1sxzYTUTwOP/fh+5SFWILs8IjXlmtv+wC5IiW\nzInQYX1V02BveC/m0fmFsn8knWeUXWW75GIw8voicnX5MIB28JxYzTqzCcaiKqRigyYOs4Osdese\n1rIQSr15MSZogNQA4Q9uqpVZIJiqX0tGTYJRAdmcBKUUxy5OaslK5g4juCb+CqT435m4GHC5QyDz\nxUGN/7A4jI4VXcnL0KDU0uPNygMNYGjlBIIeSVJzFfLW0SZVCpssVP7xEDYv9oPoBQRrOeKRQ5qP\nGKUUx62dOlmuZ06pL1CFyRCnptFpfjZpiy/u0X9DAKJVLS28kyK4E4aPAlySXPnAgykaXMpq6+L4\ngwQTlJj/RWrDVVZDLpgDv/dSjiDLi1gzYGXu6QoY6yv9kehm9i/zGfAH4Nm4iDp3ttttUcdsGJUY\nOX5pBJJFOq7Xm2WbEGNOUKF4n31GtBjRcid3c6qrQAnTffL/kjQYzMWjjxtyQ4Gq1S8SG8wnZxh0\nLa2V4nn9sNN22rx8nyxr0WZxxCT7FRXBfRsyViBXA/HhwUGT8UtOaucltcNOBKQ9aGEPrXr+bnhq\nCEhMfhyJPjgUKZpaam2DDDqz+BNXGTJ1q3nD4XKRahlStabRjg2WslgaR0sUa4f1P8T98v4+AyKA\nbzxBCXiDIjjI5UCH9o6n0WB3psXj43WGP7Bm9PfB/emi58Acg56+fqEW5+VjMvHJo29TmFL8byAB\novlmPIyfC/Fii0v3LlYWAxWVA4VBG/LpFcgo9qPW+Yhz7sSZNlYWYRx8BSBtFHPZ0UDQKoIXQ/Ne\nRDObMN/WxcEJcEwTRilhQhKx6hlQ7hinqOaDY5B1GFPMN3gTpB1dC5lfOwDwQ6XQbTif0MUVz+e8\nRa51wUr1nWRmVvnL+wl6eX+bie4IcMHbk1IifHUDQJLPPCwJqQ0W/PTILBcdBSnfkn8nQdImfOp7\n+/WRn+WQl5S/4KjVdl0zWtYEetGtJxHGs8S/wOZJ2nxSnzGuFeaomei8jl2gP4EFf/WIa4OzwqKj\nz+2uN4cJx2vlfkt2FtUjeUovD56+jlPthlDUP86m828E6z+HVX7ZoDEV33LWhlQsHyKkmoiMWzYy\nHdVJabgGfyUmXygSYdEqr4ED3FjHYpkAtC/7g4WhqFvZ0TALvPcdB40O9TF3LtysXZQrhEeY14J7\nKdzxRRPsCltAu07xoEYgxU18+1twpdaZZD+XfOXHND3Y6kE3bjIxMBv4dV3AHbmPRivs4kW6H4gT\nFVcUWuPssTRNyv66CLVgv3pLFaGbN1fN1GBG2XQeBv+9kUDCq+rBrqgBwhSj0fncbah7q13tfYsi\nqMGF8LzDq5M97C3HMEMuM4FfQBc0zP81oqicqoWuBh1mhWihKI4/ZlaRO33f3t8wPtZ5Nqn0G8GE\nUNlv8CLzYvaC7tSaKV9gJySIfJKQt6yEnk4CGj+RVRu1UA1/0Er+TlbXajVybaQRgpbkQWq58eU3\nyOaqQ1Nc6JIJRNFNfKNfxWmJlQJCMbbGoPS163X0V0rQ8l5UNfYvEM1AJnntSTTZpcfamyGcrk1F\nydtxqkwn/hjqbFePqd7AqmcKjnKUO8ZLM+mkQD9gvnYXy8VMY4JM3F7mjELqgskwNrDfqk7KYp84\n8H92vTOvdcxMbuELQOGt+G0tx01omR3v2+zCUYlWznKkQJTzg7hSduynfrqjRa4s+ukUMKw9nW6s\nMH5T9pqhfXqizyUg1dFErIGw+8Nn+ezQ2lycDwRRDq5Q7kyS6RHPjMeqERFvlIbn8kimWfeQB+gd\nDYrZ4Sea0vnHhZ8T7nYIWltwn6NkOjxMONqbv5nBAXBhf6rU8M8Upjt6ub1Pp7fpd5Z4O9XOIn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XEmW6zwtcpFPQIxv6hxYxwC/spdTrLGoB4ILEP+NODQpYsELTZi9WLQc6L/iOQgxB2qkazE7\nznpYIqd971MHDyIBimsMsV2MIlfJx+fbxPxgOLnlldWhu0vSMbvH0tKsCaqq51bg80SjHoTbLdRI\n0RXKBNHiY/hwNrAd/uDNI1VArQPSevUJihWecel8HQA/qErqDeuyR3fvz+etmwA+wEarTYrJTqBx\n+0gxN2lWRXXSb1WzVOI/HRxWhUkbQg5KGLcd6MW/+7yH/J74DfKqSSUFnkbQtw4D3iiyobxCMVEz\n//3tVZ94deYB0NSkbNhQwYVGtoYwo8MnoIs31fabSPiDq38l7xlx9fp75ALhijgOEf37nXuBTGRE\nroDKkPV2KRClavVRGPGPcF4rrGho2vJSIvjU67WpSxyZ/hef2sjInD5/VTfOHdjuUA39/udvN5md\n5PU8SA5cevPi3hZnv9LPMedfbs8OfRpINO1/cETQpi3uun7In3BwZIys6d9lrhe0okK1aRQK8Cnh\nqnMJ5Yk/vCW1DzxsS0YjsZ5++CKwZzuxv+pfhRoA360JbNFJ2+BnWfrTDAYfBh3X7DTAN41eWGJT\ndNIaOmQe9nucKLsM+5bqmytNG1XR3x8eQfnSG7y9u95+a0KSMLLs8vDW4TMjY7wKGfjMrcLBXALX\n5RdBS8d7iquImUPCqSe5fyfq8aViMuTA8JyRpN7reZ7hr04/nzBj5v/GYAf/fcwf9/zsj7pkvu7Q\ngA3tRRZn7bfQXUAh4a8r1qtWmNvSRZjlNWf/0mlhv3MlEmSS3VN0lREGa6jOvJOOx7rhOXLSBPTP\nrhkBwriy03trzUP0PVLbhK+GHV8SATZ0qhsPJPvKJ1ArUmrcalWO7R95YB7EZ30RaQUr8LDu8H0H\nxSfvBDwdMyeOuWz28PLk4bAYYi1GFnYL3c+9aBO2/cQRrQOIR7B6zDTzfn8ZAlxv+JYcFcA7cDdS\nneY1+v1AEHA410TBSGLSJ7W603q44z94d7QgfZKpq9JGZ8Ss+XuzuocrjtI/CwzxAYaXJAfyCkLM\nvSecX9VlMHY48b4tYVPrX1WJPcL5vc4bTwpv5yDhIsqRRo4lpshMtpmjP/LBQkThJMDwD4Evjxd+\n0Z5fgZIhj9Cesf9L2z7FA58DJ/shqe5H6BxQXh5EHfWSUwr7+FGISDY+aOXzkINZDYyhT4Qc3M1d\nOp5u/YuAiJwVw0oS31g6x+nPXEvDwGDKIO0jR6+C30Wqzb2uD73ACi3CpG0Pju7LE3x7sgwWFaqP\nR1UHgtF0dYf7H2mg2E3Jvz0vEn7MLjcTcCLLvU551616Q1+rUxIxuCVVppmXP/ktQRbLUsMyXdfy\nEN7oeJSTC5WEEe+ruuQFCDTKWJdT2y0pdFnqTf2ppYzWv/n3pGBJxEdDfXYHh9u/s0uBYf4UjqdW\nkys6LWD2yMmnuC7j3ENi77hkb9Qjl2aJb4q/BM+soWZt+ENkM8mFnzNODGlHgiLZlOivoIO4IjDT\nBguf2s76miE8Y5v7LW+4nz7zaAzAZZrtrzoR8mPrEoLsw426l0yobffsmLCoxB0Myjxs0J/P8V4/\nWHvRj8uQlYUXrrS2N5l1TWLrnIRYqvGam//oUfGoVR04Bsr5BsiUo90ulRGVW0U8zFC43lotvhXY\nI9uIv5zMi4kvR+nv0IiHkozj516FuEBJae321TuWKRqcMNkLJjM0K4k6x2V7fexudWDHVhskWRpt\n2uQAgpcdhkCDKRctrzCKI3GumkTB6yHazXLoWdpVJ4nlq3TwjQiQ+FOK8VG7Juv9qDoWxTEwXLLT\njtJla8yzDow8WL7U+/9B877wQveVsQ2a9OJ0avMJCtrCgZt4IXYX/lmVkkIYi35HVACSra0Yc1TE\nIpiIqWFNdQuwsaJe71w/LZ7wTfkjeVGaxK0A7sSf2+WmYCASD1CkPFFrFdSXvJvK8IUNvAZt+gk9\nPgN0ff1oOOnee5eda9NIQGfaH7++ZnwFYNZ3JUzh7aP8PLUTmDuIUcEhtjMXZC7eyLGN1xrxC6Xm\nxxqU4iBoCLOpL/h28ZMnNPN3/L62xF/eXFI1K2c1NiFp1NcI/Uv0MP+uhyQsTsx2KA8WjYRHyqe9\n46ma8xWeqTc8FpQH+/SNsISHnF73a0dCecKtu6hKNrOLslP96Tl+o63d3HvD2JUGHkG4rEB8PzKN\nIG/N9pDhl2GaeIZVHaWgMC9dzD8ms0fWghnIhCfvYHErSkD8icLH7Q8OyhqS8ZUrhB+Ye6hnH20d\nGhvF09nRJI7YR/b2nPE25M33KKEY5ejkELQZCtvUhn1WEFtH5alKE7dXQG/jjYYTVK0+CbxVbBeZ\n7Ew0/6sJYi7p7QlWt/RihMVY46UHvglpKJfzlAmyPi3vdxpoEQypPvXCL7gOkR1cJKu5xhIzJ5t7\n0hT4uN7EMvLo6IfiRaKGNeCjrHmQ6nRlL76bp3vJs3/szupk1BRBTId+pKkQOlPZjq0CiyEfkOR6\n7xAEu8rgPdRSiY142Yr03ZfgL1tjSTWPwbqe6yXZJHECCaKhS8dOwv0iG1HG1xqfCpDb8bGNG5SD\ncJtGHW1H/y5DkRSh1qCMPyfyH4/v1T/E4/sXAUigrTVxwaz4x5qzq8sdSeVPJ6zEkLLm95p+QG/Z\nujUA1GC4Kp+JWSbCmGIGmH5hywCzcC5aZ7AmfTYTacxrOMh7eHq39R+INTMuzAjRsR7wgxvCfi9j\nVCrjcKH2e9tWJqYS06w9fHygPwsQBnxDua6ufBzh1vXJw9p+1YSqcdHr2J1GbaCDH9g/QIvGU/6O\ndbzF9qmG7acOplOV+UUN7bPImCfV4amD9Atdpn/yCqr17sbq/XnL8PbEfLFWwGtxeTDJNewdRG7I\nPuwOhE7/lAPAbTUjhdmGRU5jtZxwizcz0L2uya35thXsjXDoa6rM6KEoM8AGcBK1tb+yd7PGqnVV\ntl1tPRqgqsMj/Xfk6jwPKq3lc+rwQykIHRcKtuqFITMDLadL5ep6HMsOO/2PjRxrIT10V+AWqKcB\nWLdowlVBAqHvybs7xj18q7zmKGvn1/Z7s9JF9HeX+DM1keWzTV9lyDS8cfCEWKfxCCEMi8KH54Qj\nEzrbqFKm7Fwlg8Oz26tPJ6cJolCH45fSrmQ5PmfPIbAWYgadv4hxIy+8YqesRGAJS+JIa5SOSXAb\nATecjyYRjiHOI3AS8/HJUC3fqZ8N9qAX11K9lBiIjeAbccZK8eaJvQpoXGMA5/BH0vPycGo6k8hl\nTza8n1FJfrMyIORyUNwP5Peq3yZFkXNUcnMjt7tXqHfSWCwg3IFwfmOAgLs5w+K8IQjqtJZqxtv8\ndakxmjezVpTcmWXGsnw99P9JqDGt+BqYzoTXmJxw2iUPHthmNl6jiRoh49BtCqHRnQgIj5pNFX5r\n8t2qFy3ToUPQLoIhrYuIfhzw0AQLDFDScB/23Sk/8pxu19MVCgBmkfh/2xMMKtRbDkLQwTjdwpxQ\nrqEJ8nqvLO+tBbczQsREhamGHxOUpgAZam0D/KuSIlERbp1BpeZziflu3F3wDf2icJEXWOzomO0S\nnodxZZmHYclWxNI/ZytanByEfYfTNEbOvhpHGASwciuVfAXSoXNV7cVmuRG7sBuTSczVQJP0cjeD\nbfzIkwIhsW2Njg80CgQT6mdi4zfsAb0fr80e1VwVbWwtlX4ofhP1JmDrCrDU+AxxV1iJsCSzS7AN\n5aOdu3W16RzErzEE/1um+Ev7z174+8ddYoUfOtuFxVvAElaTxFOt9vUDJ3a5Z4WNvJgPe8cNt8R9\nYfuVdgr0BeqEC38Mm2VemwCGWJiilw8ZNufPdaDuT5CKev6WQzm2VpdCUPYYY3j7gTd23FeyHfZ+\nzX0yCzO3DJT4trtRE6sOb133kXpQkQyw6c32bsOGEHQ2MwtPveJMyiLcdphCUSbZygAY0Wm4OjtT\npq6LXISTFqDQGMYxqDI215O6O1e2d3yv6JmcN6E1AfLIkJScfFfda+qd4yuqjCTuj/65YSaMNf+z\n+SnvOvjH45e7Ad5YSVZ7pLWHQBLz+jaDxlZDwwhfnUCKmKLsz8mKHMw6AveW9NnUvh/sOtiLOd02\nWQJaSR/GcX6plGQLt87uWd/Se+wkzsTJ8uapmtIznpPZ0fg5NY7OuiIjmj3X/cxbsUcJsP4QK8Yo\nXMYEoSVaU6M7gc3m4CsLJESDVWv9usg/ACikf54onEvQw9jGFnP8AV7yhFIZLvfTg4xiFbNjRrcQ\n16mwcW0Fe6L1BAPAPhrb6wDKTI1hd39jJ52C1XA2BpBmZ5yGkT92S8cH0LOJf/v8yb7ymcF1OPYw\n5jYG7X5OUOCrQmmOlINIVsu8XHMlnRa9IDv4H+0ylUJnE2So7kW3rjDFNDyJpJ2yJi6NlHcxpHCW\nm65qtutuY+kbFMpIWHpxjs1cQfiQPCBISnJFVxNGTwgCqr6sHj/5ICiIsCkCO0QIy1jEVJDN2qVk\nl/ZVfIdNHng6I7vy5BzCCb63/mIDlBbCjFiafEPKSnzQwP/0N56D2ImUBCbYSdsjfLV9hiVIBYpj\nYQnNFNDu81Y6Ty/Od2AKyy6UjTdmLb1rdqkGnZ5qqAfhwM2AKZ/XoXwiurBa7+Xgwy+R2jBggubw\nbeRjsDJa7gU4M0gGheeRgNDnoizYw02Vzlg4k1VnPjAsxNr5XcW1BJ4Jm8vjEEXBBGGvVP0psXB+\nL4iy7FHUCgYPy8hYFqN5g7hLvb/wT6pkyNoUMoj6h+9GrrTy+rnjI6kGmNlIsSYu15F7oQbA+V9k\nkLTaiiD0deoYHRklY7pt3lUK7rZHQKf/n6Vx10/80i9aBofpZOIi3uyImyCN7hHcCCpYnvew8SZT\ncfFxgKGYa7V8OeAxk7jpLBvMxfr2ARp+Ep4D1sSRH2oSzKbtM/f9ncdKLxEMHr9wxupSW+XoOraE\n1yy49P59KV53Y3YnD4miFcBODs7CRM+6bqoK9hO1K2W5kvfodbOzIB1IARSmOhRwYdljB19jurPE\nYU3GUTC+u9Te1SflGvr4XsqCbbGMLETHb1HZmXendPnGcnneY+LtnYkbqK7SkCN7x9OkYrdD4Vsq\ntbk3FZFRMB6EZ5WZ214LiLTHzEmLckyG670YR7BNLjK1rQInQAgxS7Ri/B0TGCrTYRAynDMCPXB+\nEBZOhtu0kTKOAVnDj1uOhBFDA7cmnm7e9k9QBKhHkPOHHz6q/8B+iEM+hX+B4q9fpPM6oKw+Y+1s\n8b1LtwySajwDTHtloQWcxc1uR/UsnkCWBPuL9DMNYGr3ZmKTEnGhp70LePkIcfJYuwsfo/E7aCW1\naxn2sWtKwZrw0+CDk0QTotfQ6nG6Wr7hhUAnSqfG2O6kYjQyPSn4k6m+aEiUWQ48MMUvY9ABq87V\nofVf0Efv1OdyGUNFigWmZe8JDvXnZiWw1K9gwZqBldibpaASp9bfFJgdiPr2CAGTDl+r8eoMd1jn\nBbQ2igsBTuhTaV10ZWJFSAIdZ4+V3HYLkLU8oSRXqIzqcI/IiAg5SWLWSaeHmkCkSbn70TQGXGOF\npfjhv2J5yzmkmWDiwFq2qT5eWOMB38FWcEeOtiJ9xvBgjz0qOyAP17fXFxTm23JpVYazHXlTlnnH\nxJSftOg+EKpf3k7fWj4DxyytvhYqXy/Cw2R1dyUtnLFEbMzZd3Kd3ejeXjJdr8nuiqNi+s7uqd6f\nln+VwVZ9a3biIRoGDPRIqfXo5untTcj3xHOwq02XjoFfYNwh12xIfB5ZpUmpKZj34IsNZiFggBr6\n6jqqGibpp2bK8BYBtgi5WPUHkZJIuu/COkKemycnSDpeAv9Dc3KRz3nwhCU41HMq1xWMVrrY5W/B\n6Q1U+SBjTYpQ04mjzFOvYTtEim9f+nV2S1wghga3XTYpWdtpng6n/69RizgI6R1dyj9sZOcdhPFC\nLSFGTswmGoFRGvNeDd01cU3XMMT4u2Z5ZOJ0f9yEb2V0quk1hIqMxHLPaG78pHgJeAtI4ztI+h8x\nW6bMzRi+2SADpd92+2fWMSzXApfsMfb/CJmztrl81bZ/RiWoHQO7FahUXnuklE54bClGGhaEsp/H\nJDvuGKJi/CWrkZltXV3V+Y9rHOa2gxVtp1SNceOD7LJQtxy0tEh8+Mc9z+X68qvpUrp/u4tsNXDV\nXsi751iqAXXO0dnHOJ6OM0o4xjFty4aOINWoxA+xCmcx4EJTLLggpKAdzIwtad13EDly/znQSFLF\nbnp6kOJKqe0W85XvkYnXQff6cnhRSWsY8q2CG0w18siVnfa3E4xAO6o6vcJsbyH18/PAKl3e7Bh6\nNTN5XB88JkKGd58BVcAOZpxLiupbboAJCvsueNHTlyWyvvwbLqsDVuAJBSHpPs1cFjLtkeiTGT+a\nSrqsgMO+UHPBsrwvBGWtDxj3TIKE2Bnvjmq3fKgev8QgzmUU6ZF4/FNAnmzGpTTvADIiUY9lHdUv\nE12u4qX+I69/sHvIACAnIwYXNbd7R33aQ91VJeAcxifdcZA5v9C3ahUaFH3A1RK+enmmfq3TzpVu\noJN+l23KiY1hkUYhiR2aCWIXRySCyiY55+b1G2/fRN6+GV6tJ2/hDe+vqM3JlVPptTG3ZIX5Xn6w\nXYIcd4doI14tVLSyAXT+x6QXdffSrHe/NgPJaYs5pg3BnLI3GSDNxlUE/pU+OvTXDTutF6naLbGk\n3H2+OtT92hDETD3Fix908xWiPIyeY70Cbx6Buqa8znPrRqc4DyitrDyvoQlrTxSwsLstbSVHw7mV\nHsYKgDvPmw1+ZSb9KyxoMxkr19CiTRb3JOrETdiA/VQqnMkjJGK0IEojw02kx+ft8nWEvJkEjXTT\nvyjahSTIEhA1jVfUxN86LHEucrkqhb13um/j1XrS3GRfic1TgpHHW1S+0OcCHpiKzX11xznmgBbt\npi/8dC8uMXKveFYefwObSfPZ+WEbNUFC1u1Mtd1FGzNLljP9SEYPCSYTWYIzMmwRwWT6betJJ+MV\nq/08MKx6b4l9hUTYOylZcrfrrBLhb+qmqYl3C4dEybhehzgcKYDwq4KVDUSo7uPJKSObyezVPZGp\nYxK9gGsaTY2Y1vrww2p4LBm31MsezorYaIvvDZrRulc378EkVjjMFY74VdMTXqb+rpjLfZYvEheR\nltiLMDnzHFMTLx7MnxbGVbuTWXJtisMsbH5vXoXWGEWinvXUjir4yICOZiMgUdQNG9dJKF61yV5d\nD8vuzUbVZWMNKO50MKFFeQDEIi/QK3y9S7CoVspKGFiX9huOjtKEFypMTRvN25ZU6IsPSKFyBU3G\nsf2LC3U6O3+Aia+yJnOJ9j68fJ4j/y4h4EZddq3di2jiahqK6+92jBeqa2iljZiYWvUWjn1GLa6B\nmAddWZnuVAaG7sBULE1a2OvCuqt0/rpv4E2T0oCtg83dwV2wF1xwvR4TTP0k3VJkMDa+bRc6F1If\ng2DHdDMHOJ+zr50PcE8q3ATEQ3aRsHk3kiBDSNjCLxAu8Aloh4dvJok4QPOA82ahFUluEQOphCXJ\nnoGJVkBSWcXhXojWVO2iZmFMpOVj7j7CK7BqYLDRlfM7pQg0hLVUf+8hH8DhQSjK0e4V7/wJZLTP\npmLh/NhqxxhNtRDUhEa3xSQBmYRvWk0RbL7Z4jTo5yamAInndOM6Pz15AIijBTmggr42FdGAT7j3\nT+Hsa3nAUQEAshewF6KGwmCpKUL6hJwVxwujj3qdOYfcfVJVXWy+j2BjVZF3yRPrb6ZcsBK79nqA\n6znStSrjcPRpIMR0WyiPVw7kxu8u41VKTh7+x9iKHXw+V3xz8LDyVhCea+Lu421k0ftGM39elZzw\niICuqn848ke6Z7HBYQQcmBZLAnCjpKlEfKXiBiXC9/jrnytaxYWEwM1XfMDvfrkot4s/9EvpHeoK\nheSD1gXbrFhPXM2+kcS29UIcUeqaXVoFbCth3Q4gQ62DHteN0gw3hY0UNsY9Q05PN9qWfQoEZuBr\na2Bzj2u0Gt9YJuiH9AjxbWdYdJCoTVqSHPFsfTG+SS+TX8PcfGlHY1VZSdrScBIh1mWOl+bRxvvw\nt1Tr6dyDMLPJXu/CwyCj7teA4QrSMaPNh85K9Dylja1im0yXfAR+C7wRmRZ7Dd7QeOV5hvEC0YGR\n8TZxe1HAae7Zs+dfgdvBmR0esfWzNoda1mq2QiWH6R05QM/1sLqzdodSeB28NPx9WP2IqimxNBQh\niv35VU4A3epX/FjfVmMt40C8+kH2eC+fry5mYwvLXIAXZisbdynQAnoM+GQPONBsjaTyOZptbijq\nx6/Z8Ujz3G9XSvdiA2SVWuD410cnGgQrcWQ3tDBKfsz469bMz7VlELQn6SUzoUmTVeXqlunLMgAT\nZjAFpyhxsekFxEesgRUprfqnBWj8WZiwYk+++EaFrrl2LOVoKTGlASaf7i7PCgiMuDiow55MtAdH\nUQ2BBuXL5Hb7cpA7Qv5m/wgDTkM/0KJe9wVdZ1x+8bqBXTFyDz51576DrvtZtAD/XbJnA1kE5pDO\nTIqF52tj1j095Awo65eN1D9llYHxAe5KqySoIQ/mUCts9O55Ttef/xCU3rgLPln/8KfKrqhanX9f\nQytLhGJplYSQ+JeTpwLQ4AMsrKC5htbluB5tV8y6yp0i2ERPTDEqqtq/V7XMiqYbdH+04sQBR2nE\n4k8UUrISsEJt1r/1p4kKu08UaqcNRB+543qvLgCj6oYuFvcyZ26VMqgmFqYnLBBt6rxv0NbItcuv\njnXcTIV4DNLBpHsCGtPT6iKVmV+AarzOVNre2mZDZSjxENol85XuFWZKPGwuQHGf/13N0FwUZj33\nbcAaynRH5O1xKzw6B7o/6QOLte8t808bN8lTg4RtVzap6jb2nZQ79xfViEMvZj4TZ7mREpQb+UH5\n5w0c1wRH6IQcWeMYS4tEKNOFbj1fgfFa5WqDh5RkiRSuT07K4kqQ0IDvbuKVkJLaGtrQikvV568j\nJtt1GYLsDnJvj414UYYVlISVETETB+9wP5/n9mMPoKD1REvPhzX0F436v7GKY4JczyQWlQtdlIMy\nHSjPO318tn07kwO3cAJ5fsIffJCCNagrTfspZf9bzICnrQL6maPSuNgYQgqFwfDF2RM7YKFE+zpQ\n1JcpFaojBF1JuaWNYohO3O3iXCJB/AErTdLoDmZkRGr7+6yhSCU/MqKmeu1eMpbHzscQ1l6VgAoj\nh+JdxnWiH1hTvWfwHuxNuwiNd6hyvHjUyakzZlmJsCLhEWk28R7wCG+6TQMA1Qsc63dQtHvPUxkC\nn2VqxSKjMhSxtS2iXEtF2i4gqnU7RrlZPaNwq7N8FfBAIovNAkquXXYkv5QqOch1Inbmi4qUAA1k\nQPEde2r+zd3qjLYuEGGSjcTd4RTxuMzh80+//d8arJdfJKpgc51kD89xm2S2hti42Db5ewQ/NgEx\nD5Oc6V+9Fp6zaOdR68MZ1vqFLmPmxrnOc77er0e4ciLRpueVvrks4AXCvLpDexU+qwqJpHcO4Nsq\nePNG3yBCFBf+OkklK9K2i96oQfq61gTjMYDrqdASmgo46lvYVsliKZxiATnOtrw40xLe/I4HyUek\nUzpOa7lwnkXdKgZe+gx5Q0jxiJiTE/F3r+2UpJTaO7MRcwplFvXFPSSbDHfKwF/BQjoMq8/pnM5R\nqZYfGin5xwtXkin877nraCfD6s189FrFvYKq96F5I+uEq7n74mQyY274WQJw9Pq12zUEbQsDg0DR\ndgsWPYQEt21HWe5pj1YjzKc3k9dC903kOq1+KD26+8pdMcpvICRq+WJddxHfZxl6ec1XAt2QKB/w\npyPg4yDmh/5/aEOuP45dLO4gUbGL3EinXZWQ+E1jIJoSnHh6vilbDhtX4e7DJ46+QIqny0h7R5eW\nsfDz0mHmHpRxuhReQWkB2yJeHEe5qYDVKFzzV+a/yM9kAxoFkRxFTn9o6n0mtJORZm4wxoGeQlwA\nIXr9swVxSPgM0S8/RwgkdEGMDAz+BfFrjvRRbbXsrQK3aPWDSTFswnscfXV7EW6+nDVhMJMbes+D\nf4yXRYnRL45CqKVRwr8am3VA8FgN+DQrwIvAbrZaiZMzBU3TBLFQnt3zNny734g6Ufl5gloVBA0q\nt29E/m/RIobK12HWVG/5m/8MNwNY070i2VYegXW8o9i74wAONxZgngxdmnerN+0Bmu5ugMhe0V92\nT/X9Yt9A99AjMEGdljk06tBlYIWLBBv7JdeUmUItCy/FWuPaUZzUGLKbzoBfwXuQG458SVeCmYqq\nKCBgyFSQONeMJe7dhcaNg88JTodC+KDndvWzuL/Gu3YGc0LuoOFqIE6SumcamDQzxQSTHzxsJW5D\n9+WgLz7d9U1V9dZkBWq8WC7scYXmYEJY2TVNJjHVgu/DaW5+XOEKNkvtj6pDnGIwi1nRHt/ywZEv\nMkcqF+WVwZAEUXVXzMuF3xvk/ytRRhgorncR5sS3ArptApRy/neZT/RDVsyV4JDMGSdzgvweGLjn\nD2KQlEpHOu1r0lCWsdTnBML5Ya5tXGQcD0s0DXsJWiJqHyeWFXE8YmOpRBKrnBiGLJaz3D7xF+dm\nYF950bejYl9BrCezc8s2dFTTXOiPC2aLtsqtvhGaPGRNomr9s6FF5YDKECFX9Gtzy65jD2Uxi/tQ\n528R4MC/Kh3P/bo6d+mGGThuyYu/w08SZJKPSMmO2HDiE+mtRVzR9pP+WZ/MpeKRWYf8JZZ1cvz+\nQ9r0fJKYmsiQgj9LJWZYCdjz3tupcrvAXARjilyqBOxVIq2OQzjnIINDF7IvpWnGaenn/Ml+wiLF\nuK+niFvzqRl0ZzeOc9MHYQii1+56TeTxWGY+DM1kHBxBOGVqJVkIwtxkFtjDVk+Zk6HyIPDCN2AR\nms7Ojlj8L9WJyotBzxLNdmBQ0dGc1tpCwdthepMi86OcbLBDaImZ6elWWAFQx/1seibqgSYGXwAM\nllhCxzv1smGoW5ScDPlgpzxfrIsVNvlBXRBMTkmJ+qOQ1/ZonCBNBvc6wysO2/bRH2q22N1pvx8Y\nMeL3M30cfu2qmswOY8Q7zJl7tBMfeaj22LgZsejWPOlhwAzfQWVy5IwBujhIplfaAel33LBOiS/p\nAkS5XH8sMf7x24AVDupRC/hXOAy/awmE5KNbsFq/OL14Ptlmnjpyf9NEh5ea/cw7fNWpTaK1Ozo7\nBa1/0RAk203DiiRfXWBNTVH2047nL0PGx5U0jzNtxRJtrx7qOVd0bnP8bRRX0fgGJvrI+whKaSa2\ndI9EJ2rAnBxkJrexb7OzccL5GW9f8fOd6HUYa0KUq7s9PTeV/hqqXND6gZlfbVp+6LRn9XX232ig\n3TigRnOeqs5gBWxf+yNhnbttVTrVkhyHkg/4XF/hGzljDgM3xhGsLlAQYBlu1IFgDQKB0QCcqLB8\nuT+ItAHiLDsKp22zq7XP3hZuPvXsiMVXhk3gzW80XBjO9YdryFgZKvJOslBV9LRpqDLqwVjbwVvJ\nFJvKaKH95Kobys5cQLXhCVkROVJNghm2IzD+gAvjjNNN4v1g7o0HPABDSfWhWSxdr3Q+M7NvmgKg\nmX4lG5pYL9gwmWn43rwtbxilOwvejyvzUpDsfT7sN6rywK4FiicOwdZu1znqp9rTkkleBJU8oWzw\npMUGzh3EvA3wmUx+yi2nJAivFxWtCIBBLF093Qk5TZ9JF5SsZMriphe019NHeJPN7VM0igq8m1nB\nMNsGXrJNqPg3d5+VMFqxPsN1xlVssCxiDRU7hLUnSCPJwOsPbrJ4jJ+iI5Eu3MZqffJdPCUKVxX+\ne8VIBYaCIU1n88ZRBy0/fvnfyBlP3rJegasVh+Gw19ccUnEcs9NjM/kJdHh6qCi41KIxuTjFD9IL\nuJakkfHei206Hx86Hfs68M1idoaz1YXPzE6MLxYEHPJL/jC8wgpUZbfDQMUY2fq151hTgA5UrVXn\nzNvQRvIwp+ejQ2rq7HsJh4xpyAWWp+UNkpIIGfCUtHjAZl5HT30QkWkdsNytGN0EparGxYu8oIDB\ng5rze1cL7TqjaaZth3GqMe8oc6Ee0mdxzqr6WT0jcmT9C0+Id2YSDXTVsKA4MPNekS8nIvoD+FzK\n3wunleyNqhPmHrATn4TtGMsq7mlqvPpyOvoW5T95hr0vyPIYpnDBvJ2EE3A+GoWaeAMfVInayQk6\nXNjWGST0FMagFBvciuZTo/A2VTJLDygqcDZPqqZ+0NfBGuJwo+CRzq5ICxtDwv0oLe5kj3d5G1qy\n2vqHd5m0/71p3ZseGeQM8DgW7Hqv36f7iGKfaXQmvwwIkOY8H2KYBOpRuwOPMwj1Ez+LZipYbyI9\nmKj9lNhNz3+5fIKZFgF29TCo6d6au9imnNXR2ZW7fZGiGKIOKv265X3hNpcDmYeyEeetT7nHsAlV\nElEAcD62bZJAp0i5Riea1lpN9hD7nin+GHCGsCd8W9cYSE22IJKvejLcO5WgiW5lvqCCDCvfwO9I\nasCxXebGi4uqUSQJBxRfSbhVSG8FeKR4XldRaugEqxc5/843LFRdlm1V832Igc+G8q/M9pmobo56\nB5/SwdIjFyaaBofHMML2Dlv/P5YHqmWOMGyNfBRWRtS9gcE2rNA5FtcXXli9iKiF1v6ngG3GKJVS\n1zkwJNaHKKV8OMARo/c3JSYi/l7iC8eWvXxNDMKc/3fjIVgTCeY7RM6H6cWYQQdJoPqR7EG4bDYR\nosVI79WGWVefVhS3TxGX8UYWAxQLbwhbOuie2aLQBy7YXgMNPgV8PIPPHFmVIzHhEZA1OuVkbi7G\nGFhRIUifmPq5g6EVr+xX9TuJHZWSJJUT1/JUWNRNVOu6XNpNEeP1S2ghf6oMAIr+ISdEeDNZOJO9\nwXy8Rcklo4dPaT+lHianOxRpRHEX5YMO55V6aeibuQKXJRwjgfWnbc0EKoPuor8XUbqug/6ZE7j1\nE7yXZYS7KtOsUnB17h6KzjGFznBVRt1q+84oVWJKQIROClMVT9XTjGP9kFT70snh1O9nsL/grGB0\nfUzU/WoBVRdp0oFtZ26Hk82ha/hl++Uivq8UDIol/hzYkA4wQBuvgSSCvkmMbHWQLfMHy9PjciE9\n/e9Vjgvc9KbFGHTb31tbg4MoGmcc0HGO3raQPrLTnXfdGV3VWfGKMfy/RGdSD57qi9E3wNrgGMSP\nBKiCjKLPLI3xHu2qsaJJ2F8uno+WVTOfp2lZxEBWxLGsES+FmU65TrT1fy5ZCeIeaHQabk/HcBXt\nF1uSFz42aPdTZA0SqK5+4faKUTata+cQjVPjsAADtfrToRZy2d+6EHlvXC9ksn4GH17OlPSdv8pP\nnpKDZ1eaJxzV6D8qqVXPOFttt360qx7cWRYCcFenhFVUpxBKZfuQEW7mYS9lVhghyDTWX5chKYKm\neC/efWFFT30OfTwIwInLus4LYOnj8WdaxW9uNOTfZoric7rUiAhwkJb3wNBW65F4QwRZdlyJ1Feq\nkEi+rEKgRdqli6dElxf6CVDapNmiUshH5HOp/PN/FbkZZxw1EZBecJ5TzDfX5rhFCPZqvWb3T7je\nx4Rg0yb8S4ora4wundEjGAzJvfgGZlpLsiHC/UJe+I4zbZAucVG46ZmOgKdt+Z0m3YhyMH1RA5tp\ngR3G4qTnB9TvDF28GTvh5m+KaTNQxve9wPIRpTpVveO39FeFWdrs/8z/yfDbqaBSyFBkaPFFKU0E\nnjRhobVb+g1SYKEkDZYWqeJ6jOLhSqsmpktl86KRKj5T+ZHI0KDotADU2BybQyijJDyR5TvNLU2z\noLnSh+nuPPP/uQ99UDd/ES+CYINuFbbN5iv3ootOk752D8/+eMepxL4TbjcVeiMJsglorDY26rQb\ntHspGg9kI+tmPLftbvJLY1Ah/jkqc9e9dJrx0Gd2X+zVGNFXtgRQEDiG0HBcACcNuC0sNo8ufju+\nDLi3gbESCBkLR5/Ku6ErOVAIaS5saiy4aDoQnu2wbBZfRvVdFLCJxpISgQCcyzt9/4Ni3fLtQqiT\ntG/HKy5+RvsyDoImtnejDJx1REIWGfd9yxIoLnsb7gSJxk3qqKd1HZJRBpcVjUQ/g9EWWECeSSl6\n4BN3NqO9qO2cEU8Gy59FzzD6Nqet0wfwTgbLbeI1ULxDlaghm2HBKvemR//cQPfelFaw8oT0H2pn\nE5IBJs/LYwG8S5XcAN/bT1DfjGTTPIqkcnCuKTJJPisEplPXbcpn9c5KWjApA4dBZiDuABxt4LRh\n9k0hb3AeHhWXvrYWj57EiwiOlS3XOg6iJv7BKgiZC/UJz4yuH/J+IERjAKj6dQ0pqveXN5Ghp5l1\n1hUwA/eKbHE1h9S+2oItwWl1gxNcmjYk3i3ogZVpSmkUoxeyVDyNTrZviXD9FcFBgUtAGOaEetbq\nZFyHbI1B/VBG33BnvSJ2WgGyypH5ggV7azeAYZ7djam33U8yU0wMIMtj7bTxQWnhhEITSH3TTa9E\nndkI06pkCNH0SA7tahb3c6IUOkrLqxZ+1oR8htcEE1AIEpHTBX4kNQHWjAJIxLC6KI//lbj4hk6n\nXCIYAKrm/P7sFmWEwDD8AQYqpChgDejn9MV+4YQYreP5x71z0l5s+//OS6fNIY1YQqlKAnJFgSiS\nkL8Mop5IvPv1Lca7HioxXCMT+QXJ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protect end_protected\n", "num_lines": 510}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_axi4 (\nclk,\n\ntrig_in,\ntrig_in_ack,\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26\n);\n\ninput clk;\n\ninput trig_in;\noutput trig_in_ack;\ninput [15 : 0] probe0;\ninput [63 : 0] probe1;\ninput [0 : 0] probe2;\ninput [0 : 0] probe3;\ninput [7 : 0] probe4;\ninput [2 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [31 : 0] probe8;\ninput [3 : 0] probe9;\ninput [0 : 0] probe10;\ninput [15 : 0] probe11;\ninput [0 : 0] probe12;\ninput [0 : 0] probe13;\ninput [1 : 0] probe14;\ninput [15 : 0] probe15;\ninput [63 : 0] probe16;\ninput [0 : 0] probe17;\ninput [0 : 0] probe18;\ninput [7 : 0] probe19;\ninput [2 : 0] probe20;\ninput [15 : 0] probe21;\ninput [0 : 0] probe22;\ninput [0 : 0] probe23;\ninput [31 : 0] probe24;\ninput [1 : 0] probe25;\ninput [0 : 0] probe26;\n\n\nendmodule\n", "num_lines": 117}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"ila_axi4,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_axi4,ila,{x_ipProduct=Vivado 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H=1,C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROB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*)\n\nmodule ila_axi4 (\nclk,\n\ntrig_in,\ntrig_in_ack,\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26\n);\n\ninput clk;\n\ninput trig_in;\noutput trig_in_ack;\ninput [15 : 0] probe0;\ninput [63 : 0] probe1;\ninput [0 : 0] probe2;\ninput [0 : 0] probe3;\ninput [7 : 0] probe4;\ninput [2 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [31 : 0] probe8;\ninput [3 : 0] probe9;\ninput [0 : 0] probe10;\ninput [15 : 0] probe11;\ninput [0 : 0] probe12;\ninput [0 : 0] probe13;\ninput [1 : 0] probe14;\ninput [15 : 0] probe15;\ninput [63 : 0] probe16;\ninput [0 : 0] probe17;\ninput [0 : 0] probe18;\ninput [7 : 0] probe19;\ninput [2 : 0] probe20;\ninput [15 : 0] probe21;\ninput [0 : 0] probe22;\ninput [0 : 0] probe23;\ninput [31 : 0] probe24;\ninput [1 : 0] probe25;\ninput [0 : 0] probe26;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_5_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(27),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2017),\n.C_MINOR_VERSION(4),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(1),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(4),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH 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E65_MU_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT(1),\n.C_PROBE275_MU_CNT(1),\n.C_PROBE276_MU_CNT(1),\n.C_PROBE277_MU_CNT(1),\n.C_PROBE278_MU_CNT(1),\n.C_PROBE279_MU_CNT(1),\n.C_PROBE280_MU_CNT(1),\n.C_PROBE281_MU_CNT(1),\n.C_PROBE282_MU_CNT(1),\n.C_PROBE283_MU_CNT(1),\n.C_PROBE284_MU_CNT(1),\n.C_PROBE285_MU_CNT(1),\n.C_PROBE286_MU_CNT(1),\n.C_PROBE287_MU_CNT(1),\n.C_PROBE288_MU_CNT(1),\n.C_PROBE289_MU_CNT(1),\n.C_PROBE290_MU_CNT(1),\n.C_PROBE291_MU_CNT(1),\n.C_PROBE292_MU_CNT(1),\n.C_PROBE293_MU_CNT(1),\n.C_PROBE294_MU_CNT(1),\n.C_PROBE295_MU_CNT(1),\n.C_PROBE296_MU_CNT(1),\n.C_PROBE297_MU_CNT(1),\n.C_PROBE298_MU_CNT(1),\n.C_PROBE299_MU_CNT(1),\n.C_PROBE300_MU_CNT(1),\n.C_PROBE301_MU_CNT(1),\n.C_PROBE302_MU_CNT(1),\n.C_PROBE303_MU_CNT(1),\n.C_PROBE304_MU_CNT(1),\n.C_PROBE305_MU_CNT(1),\n.C_PROBE306_MU_CNT(1),\n.C_PROBE307_MU_CNT(1),\n.C_PROBE308_MU_CNT(1),\n.C_PROBE309_MU_CNT(1),\n.C_PROBE310_MU_CNT(1),\n.C_PROBE311_MU_CNT(1),\n.C_PROBE312_MU_CNT(1),\n.C_PROBE313_MU_CNT(1),\n.C_PROBE314_MU_CNT(1),\n.C_PROBE315_MU_CNT(1),\n.C_PROBE316_MU_CNT(1),\n.C_PROBE317_MU_CNT(1),\n.C_PROBE318_MU_CNT(1),\n.C_PROBE319_MU_CNT(1),\n.C_PROBE320_MU_CNT(1),\n.C_PROBE321_MU_CNT(1),\n.C_PROBE322_MU_CNT(1),\n.C_PROBE323_MU_CNT(1),\n.C_PROBE324_MU_CNT(1),\n.C_PROBE325_MU_CNT(1),\n.C_PROBE326_MU_CNT(1),\n.C_PROBE327_MU_CNT(1),\n.C_PROBE328_MU_CNT(1),\n.C_PROBE329_MU_CNT(1),\n.C_PROBE330_MU_CNT(1),\n.C_PROBE331_MU_CNT(1),\n.C_PROBE332_MU_CNT(1),\n.C_PROBE333_MU_CNT(1),\n.C_PROBE334_MU_CNT(1),\n.C_PROBE335_MU_CNT(1),\n.C_PROBE336_MU_CNT(1),\n.C_PROBE337_MU_CNT(1),\n.C_PROBE338_MU_CNT(1),\n.C_PROBE339_MU_CNT(1),\n.C_PROBE340_MU_CNT(1),\n.C_PROBE341_MU_CNT(1),\n.C_PROBE342_MU_CNT(1),\n.C_PROBE343_MU_CNT(1),\n.C_PROBE344_MU_CNT(1),\n.C_PROBE345_MU_CNT(1),\n.C_PROBE346_MU_CNT(1),\n.C_PROBE347_MU_CNT(1),\n.C_PROBE348_MU_CNT(1),\n.C_PROBE349_MU_CNT(1),\n.C_PROBE350_MU_CNT(1),\n.C_PROBE351_MU_CNT(1),\n.C_PROBE352_MU_CNT(1),\n.C_PROBE353_MU_CNT(1),\n.C_PROBE354_MU_CNT(1),\n.C_PROBE355_MU_CNT(1),\n.C_PROBE356_MU_CNT(1),\n.C_PROBE357_MU_CNT(1),\n.C_PROBE358_MU_CNT(1),\n.C_PROBE359_MU_CNT(1),\n.C_PROBE360_MU_CNT(1),\n.C_PROBE361_MU_CNT(1),\n.C_PROBE362_MU_CNT(1),\n.C_PROBE363_MU_CNT(1),\n.C_PROBE364_MU_CNT(1),\n.C_PROBE365_MU_CNT(1),\n.C_PROBE366_MU_CNT(1),\n.C_PROBE367_MU_CNT(1),\n.C_PROBE368_MU_CNT(1),\n.C_PROBE369_MU_CNT(1),\n.C_PROBE370_MU_CNT(1),\n.C_PROBE371_MU_CNT(1),\n.C_PROBE372_MU_CNT(1),\n.C_PROBE373_MU_CNT(1),\n.C_PROBE374_MU_CNT(1),\n.C_PROBE375_MU_CNT(1),\n.C_PROBE376_MU_CNT(1),\n.C_PROBE377_MU_CNT(1),\n.C_PROBE378_MU_CNT(1),\n.C_PROBE379_MU_CNT(1),\n.C_PROBE380_MU_CNT(1),\n.C_PROBE381_MU_CNT(1),\n.C_PROBE382_MU_CNT(1),\n.C_PROBE383_MU_CNT(1),\n.C_PROBE384_MU_CNT(1),\n.C_PROBE385_MU_CNT(1),\n.C_PROBE386_MU_CNT(1),\n.C_PROBE387_MU_CNT(1),\n.C_PROBE388_MU_CNT(1),\n.C_PROBE389_MU_CNT(1),\n.C_PROBE390_MU_CNT(1),\n.C_PROBE391_MU_CNT(1),\n.C_PROBE392_MU_CNT(1),\n.C_PROBE393_MU_CNT(1),\n.C_PROBE394_MU_CNT(1),\n.C_PROBE395_MU_CNT(1),\n.C_PROBE396_MU_CNT(1),\n.C_PROBE397_MU_CNT(1),\n.C_PROBE398_MU_CNT(1),\n.C_PROBE399_MU_CNT(1),\n.C_PROBE400_MU_CNT(1),\n.C_PROBE401_MU_CNT(1),\n.C_PROBE402_MU_CNT(1),\n.C_PROBE403_MU_CNT(1),\n.C_PROBE404_MU_CNT(1),\n.C_PROBE405_MU_CNT(1),\n.C_PROBE406_MU_CNT(1),\n.C_PROBE407_MU_CNT(1),\n.C_PROBE408_MU_CNT(1),\n.C_PROBE409_MU_CNT(1),\n.C_PROBE410_MU_CNT(1),\n.C_PROBE411_MU_CNT(1),\n.C_PROBE412_MU_CNT(1),\n.C_PROBE413_MU_CNT(1),\n.C_PROBE414_MU_CNT(1),\n.C_PROBE415_MU_CNT(1),\n.C_PROBE416_MU_CNT(1),\n.C_PROBE417_MU_CNT(1),\n.C_PROBE418_MU_CNT(1),\n.C_PROBE419_MU_CNT(1),\n.C_PROBE420_MU_CNT(1),\n.C_PROBE421_MU_CNT(1),\n.C_PROBE422_MU_CNT(1),\n.C_PROBE423_MU_CNT(1),\n.C_PROBE424_MU_CNT(1),\n.C_PROBE425_MU_CNT(1),\n.C_PROBE426_MU_CNT(1),\n.C_PROBE427_MU_CNT(1),\n.C_PROBE428_MU_CNT(1),\n.C_PROBE429_MU_CNT(1),\n.C_PROBE430_MU_CNT(1),\n.C_PROBE431_MU_CNT(1),\n.C_PROBE432_MU_CNT(1),\n.C_PROBE433_MU_CNT(1),\n.C_PROBE434_MU_CNT(1),\n.C_PROBE435_MU_CNT(1),\n.C_PROBE436_MU_CNT(1),\n.C_PROBE437_MU_CNT(1),\n.C_PROBE438_MU_CNT(1),\n.C_PROBE439_MU_CNT(1),\n.C_PROBE440_MU_CNT(1),\n.C_PROBE441_MU_CNT(1),\n.C_PROBE442_MU_CNT(1),\n.C_PROBE443_MU_CNT(1),\n.C_PROBE444_MU_CNT(1),\n.C_PROBE445_MU_CNT(1),\n.C_PROBE446_MU_CNT(1),\n.C_PROBE447_MU_CNT(1),\n.C_PROBE448_MU_CNT(1),\n.C_PROBE449_MU_CNT(1),\n.C_PROBE450_MU_CNT(1),\n.C_PROBE451_MU_CNT(1),\n.C_PROBE452_MU_CNT(1),\n.C_PROBE453_MU_CNT(1),\n.C_PROBE454_MU_CNT(1),\n.C_PROBE455_MU_CNT(1),\n.C_PROBE456_MU_CNT(1),\n.C_PROBE457_MU_CNT(1),\n.C_PROBE458_MU_CNT(1),\n.C_PROBE459_MU_CNT(1),\n.C_PROBE460_MU_CNT(1),\n.C_PROBE461_MU_CNT(1),\n.C_PROBE462_MU_CNT(1),\n.C_PROBE463_MU_CNT(1),\n.C_PROBE464_MU_CNT(1),\n.C_PROBE465_MU_CNT(1),\n.C_PROBE466_MU_CNT(1),\n.C_PROBE467_MU_CNT(1),\n.C_PROBE468_MU_CNT(1),\n.C_PROBE469_MU_CNT(1),\n.C_PROBE470_MU_CNT(1),\n.C_PROBE471_MU_CNT(1),\n.C_PROBE472_MU_CNT(1),\n.C_PROBE473_MU_CNT(1),\n.C_PROBE474_MU_CNT(1),\n.C_PROBE475_MU_CNT(1),\n.C_PROBE476_MU_CNT(1),\n.C_PROBE477_MU_CNT(1),\n.C_PROBE478_MU_CNT(1),\n.C_PROBE479_MU_CNT(1),\n.C_PROBE480_MU_CNT(1),\n.C_PROBE481_MU_CNT(1),\n.C_PROBE482_MU_CNT(1),\n.C_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1),\n.C_PROBE691_MU_CNT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synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4296}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nbGT7tfmyts6/yZChogAFs2kP2mbFmmuiFroOv0r8QQv1hFG6JERBCXNBXfGou+8mLPigR5LV4eDx\nWE5VTd+gHQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nCWoEkLQgvsHNvKsNgOsMIlwqULIpu7GrNWea7T7cH++wHThbYiHobD6dcKucCQM5dNGL646pzspi\ngvc21hWZnPx+X5N28b2dNoegtcTB2kLdLw7Lks54cB9DeoTavLfTRXQYufpEksbrNJTUFVb2cNyN\n6BMeJUXHbb0vXcc5VT4=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nFNNqjXbqqfIGkUevtN9QbqDJwQreUsmu9xji2a/w3CJH665OoQqvJUOiq4+1ZDezrG2FheefDlOu\nudQOQzfUbqq4ZB7QVsrZ5+hnOl4+bTdi/FvverAngGvvJSU8+8gbzJ8jtcieV+kp8HrIMv5M1gu6\nVP5SY5P9OIiRMPqToUbAWBrFRpgduuTuMhaHwW7FZmVUVb1j1U3rE2T6UyEel2fueSISKzjAYa8d\nbMNfbkA2ORUFxDxV3b+bBcjCg+jYWECoAY59uutuI1TCRGdhy4DLAvrLFqaLXnKzQ/zhmv78sBnu\n10yEbUQnFKzl5lQwpKtElSrzEVryLPjEKxtU0Q==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nBtsuQ3rIBJ3UI+4s+peHFvk2pezsWjwgWqpQQAOktytWfnh45F6oITlHSewxA1WtBlnC7B06RlL1\nsh5uBcV81aLk24XWmuA7DcJrmhXRSOvl0k4gIwFckG2lpuYtWsH8y7owyOiD/FZUz/LSfTa3Mywh\nD7uNSNvKmmqFP0yIDB9zQtZJYDKPgeAlZS9NUZdzjF/a61kdekWKbPaCmwFQ0mA01X8N8Euy78Cm\ntwhuK1u9d5vu3NtNKQQjzffGoOig7AOKPE+KjZrhCajjfXLjFewajxJNXuRqE4Qr4GGCy18JUK+r\n9AD7YQrF9CXYq3xjR5zoOedNXXQz29GC/jViKA==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nGzBT1kWKJ35ymgjppXjhmBsPZAh+qqs629kt2BvXZjQHKHWH3WuilMysbQpFcvgaH9NxbR7qFPN6\nyb5XgBkpZDUCCrc6p6YR51wXM/nxNvw23FSNPFKjoFEw2V83YYFxlbr75lWeNCQl27cPfBPuxaSV\nIjlxIsm4eW9SkxEnTQqMX5ySy4IaL9yElffDeFxfvmZFrx9lJp5FMRFsWvs0CJEBnPV6KLu1CvY0\njoTQyovEbzWILZvpO6OoWWowRhHO/ukpDVkTQwizIuNbetdcKud8UyyAngECUSjve9k+rXX41zHR\nrDfFrjZc+RPg2YpdeYHykcsisoZ5sdzyCy4T5w==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\niim3M0ZIoSIeblUIY0hk1kn3BvlRMe2uVKS16OYK9H9BGNvnKistWqz2WEU4s7eijjhhkWdw6Rx0\n1TXQht76iCER16gWcazz66/Akg5MH+lOp9NPf3J2iEV7LK7f+3F9jgvrsadzyPoTuLecIoWFoNJk\nFXdJK8072alT4ln/U8w=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\npJ/yajVXTo6y0FFyEOL0HIGDXa+xEims4jF/m3KWWifm3tyRZ/Qmr6px8fbYo6wt98IysxEsBMsY\nOafake1VkQe9IEYdvl9w2pbHgnMGCgpFHt5GVkkx9kTM7g8X5yw1cj7dCjsuNtLtsSeZ7wW2gvp4\nba+UNyDRcpm3wErDehZlm6QU2gigOYOXUMH6KQLyei8VsyCUEOLrtDfoDMEgbTsPan0OVwWZ4Yma\nBViyJ567bWm+BUmLR7HMTK0+QktDEmFhL5lWaTS848MSM8+2esUyNGdKKutfcQWcpHUx0GkIOnS0\nlZ1qTioC56L1NI2aXWshT+ZrJgi5x4ZYDqF6IA==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64336)\n`pragma protect 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ikj4QY9qy76XYw6IDsQdBnIGtPSFwxd9wChRjkni7PaX9nBoTv4Hkv4/X71ms92d\ntJ/07jLvlYIC/ZQu83ENzkpZcQxr+WVAlk9voN1Lh8MJ41Cksb/e82lQv3tE0i33RVWsfpzzkmhl\n6+iCuWQ09/k8dS0FyYp1eOOSakJpDvCoKsuGEA54TK2SkuCKjd+GAxav426xXnGAV1GxKJw4LUC+\nBoIDk42kjGmgDrTucR4D8ebhRKZlfSndBkUN1MxM4jhRdlUOlo1unmkpDpwboVbaBL63n0cP4G6M\nMWgaQmfg3Yi3VurtkG15kqklP5W2hoXk4N43ho9pwxbkiD0fB7BonN/w9HJv4Zu26k8JguWWER+r\nF24R1GsE91Dl6f8PkWleIhz82kPHFEq5RrhTesz5mPkAh4LBNNYQcbTVLlK5Bz0FGVt33lgt9zoT\n1OXASFCArKzZWd2y0Q5uZ6j1/oVxBrIIV84Ebwg//J/PeKNV+7dWoxdxrSyxxRk9/vGvVL/UxkDL\nXNFXWyLhbVlxG08uYDNL1cw4o1C3ePlskKxvHjLKaClc/79HN04C/k9fm51CrfmvosEcGzKhDPBj\nHMwFxAT3Pw83gG0A4Em+qHW7Wk8Bzor/p/e6kDCX2WbCTGXt8ZMf/Cq6Dryzr2sDHKfteVQJ2fpF\nHC/D0b26BUXdwRPX01IK0w8qiZ5/xcJUdwszggylh3pIeyt8qnPlZ1xYYH05884oekPtILD0GlZx\ndRw6hgHq6NYCifq33HepQkocmMaiBik7yzszAuKAWn2x5Raf/FC2GSRLb3itncwKnJGL7yYaSZeJ\n8OUhkMmGPtZ8ImThhDZ/RWkOBq+OUYnTNhKc3FmrCT9LsMzW0ZyQ9o+VsZv9bTJ+USliatHl6PD/\nLRypXj3clKV1a/C8C+rxwRip4mEQfKcf0UiZgBr6eYubS93izNsyymJ1mp/BMX6jt+kcmR3LAEE0\ncpyyOM0mIgNkjmJmLmv3R6jg/bPvI2p1N7/cIyybB4G0BZtRYMXRngfz1Q6EMQeQVsUna9iAjvQy\nAG2r/xcgJFufo3kkRGq2V3bTmOg/azUFNjzL/9jw4R6mkP391rUCjjKNDXYCpxvDS4Ye2p86OKcN\nXM4s+2bmJRe5JMBVj+0ZHS7ii0Mabn0ehWpoyMokVNz6dMpxel4glyyMLn1uEeaGHRDWuRfCqrOB\nfTnvUVJz1HNeGj9q7pSndbVygb7ZUsG8h3ZCkcyQhLOw47qwv3lDHtO77/HoYY9Tr62YzSiUh3z0\n9j8wCnOkMiqstzZ3iSyRXlGTQ8cV0IIcZ4obZHfQfj7I+N4MXnxEm4Pf8DHrXxlE0RxiG3MLn8Qp\nv1AES70B0p6TKWBC7H1cOxVI/K1ykT6KjY377HDe//18VNIC6IlFJzNuCN1q/+iLfRWlGy+uFMco\nAuFhgOP9A77fsu7sTi6ay+PaHjwC+jIiDGXdUXLPAJHxpDQzZfnDDo14bCy2ZRz1RWNEkUkLH6tY\nuGcD3kggbTyfoEOTkCtHzmGI7kFz1z7J9DYLueA4OMGamCdMbQxvlcUkwx/Yam/jPH2MB8HtyspC\new/FctHMgwthFB+FzPoSwmv+vsUZD7p8hri9LeoCnXPfXS7B0PhDyaHknDkaPDhEol1WramhVo0u\nGKZ8x1eDO9ipKqbYemWHLiAhYr8UXDVwN94diYZ9VcYwIrwr1P2VsWG/9O+R3rFngUUFk8Z4Bvip\n3PBfNVwE/QWhb/BgkmHeTvSayZckM9vCuruECucSChqNjhhIvSGY8CStQKNM+eK89IlUPsvIBY6l\nRZyKERWn9mxbX4ormBumHi4IznKEziX9fRRAEGW0uSLFhi/c435Qai4kSdBAoqvRTsu+7pIC8yv6\nmZ3UTSFrP9ATOE0GChYyllkCW590wKjCJcVXcdotPCuG+4IkqGFXeEYFfkQRLFX5drsg6AMEKhFl\n8EQOwjKQBjK4HT2f4vT4b5aHjEJ05K9SP1v5aTcX90VaEP5hR0OJDY8zsD40NbAozDPvBHZFX0ED\nIRhn+i/XVUxf4KkXcZ7BGUHiQvjXmiD7rd4O0nP0t99gvs5eB1QqiK16/QSY+J8Hu63WZWcdZZAv\n1Bl0sb7QjEa1onPN6MvMm284XZNYPuENoTvl84tdVpwWTTy6KaFjMfpGvs3Zw5rbRYjDqMU6FeLb\n7tSZ/ahWSGlsvFIWoqELhastLHLkIeMZyt8jlYUTAGEOEEraoePUOpjacUg8HrSpHie81DOaay7P\nAAzT/Is2R6begRrTAGNPq50SNgzPNmJomzUDHxlbuHeJYqnJzbTNmu2mm/QNIY5g4T3/ZUKkVv9Q\nrDjVCP+lEG/cEUycZ1Z78nVFuQWmcsM+c+assi7pL+uhWZzCPQizzj2hiM7VoacDeeG1IZ5IwMq0\nXp2/giop0Ak1pp75BsLEDXdzpcD8l6Gf+GZorCsODJ9BfSE12ihwudD2D7osjC/C/bUYdsrC/chx\nlQYFtNBnmCnTwsSK1xoevId8Y2WMMdNPuOhUUHqEtFNHL4EK/KM3VZU+CxrDDhp/Z7aMvgsweO4e\nFmHhSnvDyIGqCB6yPNMXL+UsWckLz2OL1rLGupkCvcfX4pwo9bia0CTK1ZkU5mrPXtvJ8iLvH5ZD\nELwT4RUG2uPfT9F2VS7xhdsTOj5USFtL68jcB4lQ3LdUwqMunj+M/wFkRUsc5Wo1Rna/htuyd3aP\nmvR4afocTUND8sbqWF86oE0b7M84KSsFKWn254Yv45b/7AGVXhW/zTIDhey6hbDDHa3zUhsRJ+sd\n3a7q9Kv9D7ax7QymetYPp67OmrE0CctHogPx89wzVtGxxpSFh+PSbv3u7EfYVFE5UV70g5dbWi52\n3Fe0kbBYQmCR+aJTy4hgxK666akTNVD8jx6UNgpOeJ9oLxbdi9gaCeP4YvldmkPNuv6n5m2SSHCN\nysHNq38Ri4NO/g8LNN3ZqRaQeeW04n7wNj43g2u7Q+AhVjNDn+3cUoMWV0XEdGhAlsvLAziOS8Aj\nAqOcs8PgfNLRn+/63nhr3S1tpn0oiSKA/UymFDp4XkFAl/NSQdSlZdl9yZfocKZ14yfbXP4naSXw\nYXdD9IJooJYT4vc3XhlNgoWURjW+vzbrQ+9Q0aDVLGwmTPWJcogLZSm4kAy7IhXy2y/e6LLI81FT\nbGmZxodxElq3jHE3z0CJEqoS+gsdBtdqC9QTMQaetDKYZvI5/vmZh3QKAamIvXVJ8TAgO+OxHgFd\nFxrvt+kVuLs1msjlkgS8mm8zfI4owlc5u5lmeVXtyCNHPLKHYAzzMNPW5Ai1OR6HoLM6UG/N2T34\nIXbk1QrwXKk878mT9EznzAhb/4bv6hoFEDgRIvCyyYweHxvzpmEfLiP6QaYNWWpO7iR/eaJHWw/w\n790hhWcg44VxliUVIWvozPbEuqHwxbBcXeC5Ksuxlmk8QdBhjHjrT3c76PX/AgEVe+DRzjzKRv5h\nMl6B13x1nZfviHANI6UOudXTe3BSkKBQatOSiKX4yGd35hKnuRYnDSNt1mYXH7lATfmjJFJ1TT73\nWSe0PhhtU7SE6IFs9oBDUTj2gUo4sKYA4alF58i9FJIqvxNGJAiLHJ8E/+pWe+aWwISfrECu9G7z\nfL+1k6nrcGpAegDvvNaMk9nvrHO5U8w3cCleTCuOdPKfWUgRuMapzh4NZ3PMrh8SXD1InQrZuBr/\n9wwsVObR2mdCCdXa+rhcQ78GUFqAhDlb/gDGwNJXRHEtPEgwsgr/EIIqHKun5yMnH9RkzScVLm+J\nhQtsd+JNrs4PPnSzdYGRKsNeWR1uZedxdvvmQuK6V9mJ1/9Rmqx/+sHIBiu+E3k4orWWGYdd/T8M\nGKqyT1rmVf0d2BrSPHzAKYdcRuxuewmDHbGVC3lq/yp65QOvQQO7N1EnY1gqIuYuYDxWjYKeiuwP\nQFDZvr5e0iMckylJHxO2Zkx+I12SyzSel48QzIAVnQmCTJ+X5gndrUh6LnLPRXJ6+tqzD9dfe3fA\nlb+egkye9h3JlbY+3Pjc+50z73r88qa/PpdTLyGj43GkhQTcr/5gW5n0AHoRaXiFYkNscs0Nos39\naAH1XRkvy408nbWfa2Gi7jxH7uI3+F3JkxicVp4XMzt+l+R+Dx0jSIyNA8oHaGXR7iODXmIVoCZV\nsxZNGSarntyxgE8l3LcO9FCL/iMvzfprNsX4JFDepRadUjspZB3K37Rtlr8GmaLhjZU3JZATm0vv\nmoZDKTaGGimpaBiPWWIIg5udEW5MYhrK4QvK8iJiuFcjIg4IBX3XEXi6+aZluEko16/4dzOkmd+e\nlZ5Dld272oEIa31In6knS3GnJn+b1p4s5Hl54tgnvGpXSISYPWD9Lq75SgxS/jHTRboTU19NRWhU\nGZYbeD0sh+mVjL2njjkPKpQ+0YFlelzdofUpHWOTVgDIGUgPQvZBn42WfsNJ/RV5TtsMZLjKLxaK\nKCX8wuFnxtCLoOUXBkbbosQYxnMAy1U44OrJu+0HOBqsrwNh5zFGJ/zk9/5utr8aQg/2aGimsg6J\nv7HyvEFEat6XUm+SLNRb4egTjBiPMHtEUqQzXg5WFNHpof6b17s5owPbAJDewviuC6u0+/FBomnn\ncjdCfOBsKr5oKtdJ9G/cfWevYkjMPzom6RgYqWKsOT4oXSsridVr9YSMbqMjs6TQyI53UUFHfVrF\nl0ryDtX4aJ6oq3I0s1jkTBQK2SVIvmMqBBreOHIPCFKB9G1cVT3e874jfndchxKWHYKOtVIJFav+\nL8Uo1/AnORfpmZ3MT04TOIfAJNO2opY0B5YuzT3m9m+wiD5/zMo6PmrcJJ3WVBY227wPW7hMWNNn\noOjAzzCrYiiO0/jDCB8OvnLChzLzTJmbwJe4z3LzHUGQQrZK+y5Tu/hI2S0CbbCb5l/4CxcADGOZ\nuOemAiz3WmIs6bykPvKCJ3YUD3M4F2iFz0Jc9H30enm5yuyqcKJoLQU5EWDirhIaywUHXRLN0ibW\nopXtRRfHpNK3lMJsLOJLnG0zXZGCJqyTj3qaVPfuys0B3+EBk12yq5qHRl4wt4HdS7zjxXqETTCS\nDWmTnT4ql9Ls9BhQoHCyeboOSARvoJCyg5bUFY4+3V+0E88wVyH2mpmkwGMTO1U7hbxtNJeZNcQw\n4x29DNm1Stga6kl3x8cvgu6djzr1ZOQOVMvIglT/BJQsYwV5NRK8kEiN/JrcDmE4po5lmaqOrEEd\nHnLyIi24A9t/bIbw350lCnc78BGA1Sk896A7Q8M8RbN/bHcWZcBBVJXli29+Go0U1cZ6vjpF4ote\nR7juv/pOYnF6fJkTyMQwM+5vzXEOMm7HcWdYRkQ7D3BbHuSVrhMBF89SrP7kn+SQ7CMEvfEG9gkj\noehWcUlTOkAPgQk+upUfEQ1V0IXIo+XGVCHXw1HlEAli9rLRlvLn2t99tZVdA9gnXSWDnaG0xm8R\nLth+31whyvvqwX0YwczoV5ZcVxTocWZwY2x4rKKiN1sDJ5PCIH5NrEMgJS2of6yaSC59QyvehjBw\nrRNKaNn2j7ZVpchE7btRVq+TWFqRMEnDj6B0wiKHy9A95fPH/jFUEg44Wgx2iIrKPooK1JfFJjbe\nTFsVM//5ug78qIzr214qkcwpUd+Zda7rHkJwxj4C8LcySIdWlAhhrFv5gtSCqrEIxbb4dyTvJ3v2\n29J4OwnSmjFaRx+7TxM4bH5xZBPQ9Aa5XDTCjtMA25CHWN46dF58ljRBnuxj/sTwdaqBLwjLFC/s\nAkRKeGbyuEkgZDGkgQ2uyOxRytYfZgUOGXyYAlgT4iE1lexh5KlOeiAzDxJoIQpPoMWANujOCHAv\n0CCpwPRIDa+2RYtlmvxXnQ/d9rmV/+bvuLlyg/PZfyF4lTfQ+gT5J6linBQ87uSw91z63GevX3vQ\nqIXoRUlm7FQIt6H+l7ILegL0BuaK/5858vbFl7BmT0xi4xczqNU5s5sPC7Jc1JhCohsjVnHvfwY2\n8qzZE/wJGg/5VjtcQrrIsoKjKqxGlUmOmA+gdWpIsqYx8y3lBO3oGE6LdohlPe50Ww3ftoagW1cK\nDi3dli+FTZBsGvAg9jehYrd6aHzVfHf2Y9oH7wo5VVoihibkHkzqoQtIf5kh+5qyhZ+GPgQhBdpC\niJA246TRn9v15Fx0Zn4OzczQG20209azn2UqWQULiPUy0AxceMoKJoI5ebd/IcNXjzH7HNmZBafC\nqmkvrkIAJJ1FNjBf+O0QphrrXFi8bHblHGOPHvgNOuyzywWWqrV4b4ppE4J2k+8EHYdTLVKZZ4Al\nYZ6gJSjesf8kxIgFcpqWikpTVY2Lip3rXeArsRv4MfC5Cjm1TjSdZAhN82oUsfszt8WRD+zl2+Yf\n6uRI8rD7tjXtB5A6MGRMrj9OUEXOgZhE4jqyNnCg6ichcoBhMt6I2frqhye4WGXAEMLI6vSDYRj9\nSnUdSngCYww1VjOT6c5zDafPzD96R10ddX1dvw2srvEC+Ie2efp5Qbmo1aa5lIQ57nk9WBJJvgaG\nXIhje8wa2mkKm5xLGWe4Y/yHPEpOwlPKyb3PhHzx+zIGduSAlzJSD+OZsJct2O03JrLOTWClXpm6\nN7E/Nv8Eynggtxy9yi27yj8r3I9F2I6vcGjNVurnmPRazqa6xDRN5XmvoZIxhaoyc22aS/cA2JTZ\n+yitWSfoXkzAXu6UL610+zmV2mfaoN5ISO0E1Wx5BXyYs9W4io4v/Vs5fF853UcjI07FeyIHaH/8\n633CANkUvI/Ls+GIu3A6u55H4++25ow4UvCUUjPyjgbvM08a25F/61H6L+v+hRkxKtflljcz2yFa\nWzu18dTrzpB6moutKoGhVnBhkISm1U8JTlUhMSkcwDMRjb+QWWk12wexPsUG6Klj1tbVZRO/kCWY\nBowdwm2TW2y2buml37GpNk8DTcKnOZBrPm9KGKJ8AlE+UZvGwdmwZM4ppd/KPXrDRTSAvtgLzqiG\nVO0RfMkmDngv6DSQR63QVXfQ7X1tI1VJcSzIp2FnlO5umBtoXaQr1f6iQLjZs8mHKNN1fbisbV3L\nkiGCuSBWjdyaz7i3nnyYk48bT0DCaLmk04mdPsi84JnyqcWa5HEqD8v1EtfmKP7KCxyqvL6jrGdr\nY2QrX1loreGJp1YQyZJ88Lde9IZlrVYG7X36FxaYuiTpVwyV0lodctAqii6guogpO85KUTYtLiD8\nz6r1LkdsS5eJtVm1N0V8qPJE3B7E5O9Eg3rSsAZegNJwfXmz0h/KOL7ee+E9kESRKPAwzZ1eXpjo\n4C2PK+Lp+RhF9n5kn9ahWn98OsYboOQ/+Vlg4ObgQeIu6hzKJ9jgtuWxYVY5shh7Jrt0uV7Ozv2e\nvnAZTy1CG+AMaHYhJVCrk60hH2jHdkHlRGewtI/rVzCQphSTu76+MqrhzPFiuWNwGvg6Wkz76LLd\nhfcCd+meSIE5pccdbl+mARINHJz0MJdp+AN9v2UrsfZHTUOOa197dKapTQboB938J0Vm4c9r5xEC\n0WRR7MoCZSLvTdcX9g91U68eqZ7aZgO5/oJqod9jh9AZDcjOZ/IZEEUBdlJN2ygo7ddcNiCIpE1/\niePuIMRKEXOabn+Jezy3oVmDxGLZMWCmCtA7SlmqKl+bDtba+c1jfk3rwir0Gc24AQTl/8/AiX3U\nhJTblGzrePrFEtjyEPyRKLCey9jkUXrRCnIJSxb3niKARYGPop2ovE37z/rUVgTWkWj8jruVtmUk\nXDa5ugQIukRCNmF4DRWY2R6KcBoaHm5VD7WsYZHIJKP4fX6X0xUFhGYGx2gj4VlXKa6ceqCBpmlR\nY2Yh5U96Y7N8lnKjQo/1tCXe7lQclT/F0y6KMMUbMdHp4fPwWIyBj8PyvP2F488jZKoaYDcCBAZ2\nFzAB5SJ9UtxvTWJ2r7LOFU29HmpRsScH+gg5k8G/675wfProbnZ3vGj83QtH1cvEl+BkwvWj05Kz\nu4d/mYBk6otvnaXixVDPAz/V9t+eNvXRwVNJ3mcfQ+DzZ8EIJ/yws4jWIkiSofX9OxpLH3L1BbA7\n7UR79P+vuAW2XLA4/voxPvt0BPlz+7oPINnLbEnB3HVWY4zM+EgWeBPAvZEkq36WAZhUBBNguE7a\n8RtT7QkNQq5ZyDg8G6KuJnpx0w+cCkCHtGWTV8maNSJha8Bnt78kTWeN+iarpU9NOyzxGbh3tniz\nfdzfLr9gC2z7ZDK1D3NObjjHSgBGOoPQ8zbZNjIRvY+3m6FqvjcGFJw4v3EallVzfNEk0eJgbrt5\n0rMp2kwHVSf/vfKqjcIHeIC8D8JG6DdmSQr9owY9/HqnlzR5liMglbcTS6FXDgmcLu+iYYFY28gi\nqFNSo1na61Urj23WxbaWilZLtC1U0TU7gS7GCuctgPqLDKFO1gglsegQThvzcuC5bwEwRlU3q91F\nd2p+3+bdCCne65OxvO0ehShiW6Lg+NgoKVG7qfTwiYnE81HF0ok/tcaZNbE709lTsFWC5fIF/MER\nVg2+dV7U6+rJIRf2tW/Pwavee5fm7VAUPC12UC6dZaK3h+YowDeF08FW2raiLFxqZjDBI7TWFZ0H\nlgE0OCIY3aNCGDGD5lhpZXuu5IHqEIrSKrM1p0vl+PZUNwzxcr54yP9/GvEGNovVn3YSTQaYB3yU\nMdTUt4B5/l/48spJ9IQRZJOHNqo4sGuVsLADOy/rNUTcWrlHcKgT0DiALq9k8rvybuyPaMmTKkvo\n6QP1WR0m668K4o1bSzt0rGulNFO1jk1Dp6cffsvGPPQdaLN/J3MNpUcjPMOpHBLyGTB5OqG/4mjU\nGR0byR0Cymms9sl3FH/LrcCbOEyY8FxsvPhszWsKD+co+nol2ncq/5AGd1Yj+E7pPniAvEi/hEuc\n4OVUmFlFYInGD4BlOQ4z7I+0hlGZFj1oOTrUsy1FU6g8j+6m1E2quppZMIkT8lgtWyT/mG+E3j+Y\nyTjtYgsbRn/oerrBrKpvvS3drB6tNlZMZrOZYn8xWzgC3RLspbE8JWwrsZom9BJG1f5mNF2P1cDY\n1foGVSlP8cZisVdTvgY03D/ummRYd74ziD9XcdWpWqYWeCk9MtNUuQRQnisPwsDyf6Iagbu8mRNh\nn4FglPLDfVH04Qx32QoA6E6bWyHKtStBKy4F067MkUQGvBIpLfKFxyXeG3zDRkQuj4joUnzGTPD6\nTFaSLk++kWojfrkMMF/LqnQZ4evnUMmoTH1Knr677TbVuDUTS2VQbRSGuo33/AnFJJ5IVlnIb7JR\nvdHAIG8g4zp0ZE/WmWTCIuOdEGmsDXsBGbtZJQbVHPez+8LOcItfUC96XH06NYNEZI/mH1wGdBNz\nUbnCsAnd/JUaDNe5hgGNc0aDcDfpgNVmPPTG5itNB1SjFzSZbsw+dqkjOYxUxdgxyqlcA2xAz5Rl\nnWuA56Icpx5LJgrYk7NaUiCvbiRjQ4JVAI3UQfibmloLegVPOu0WaahNR5z7gt93JISTsBZDOdJk\nkUX50GH3o+E5y2s5uQtEHNVzT0/VdOuuolIpCU5aoFcrFR5cuklmtaXcpJn6CFDQa1YzjoUaCnKe\nnpeJymF5dt8FbhIpA8PSuo0aBUq09MODdh/ZRaotvwLbYMDzWQIfKj0ndZV1nXBFjD4SQ+HoJ54U\nunuE4OZbTfvcC7ViY/RqV+Xkd/APQDwMfey+cXxqr7guko1eOqgR94FuW//L9CD1ZKsEvXpmRJdX\nBqYyUW6GK3akL3uIfIQCFtwyGi/BfEVu3rAbR3yirvflkC2o79Wa4BP+zh3tyGglK0Bvli6iar+A\nX1DA/dkwf4OqHuuG59dpNE4p/om4LMJXdl6SqXLhI4N5WxYtX2Px7ooR1NSZJl53yzBYZMOuzaF/\noaof3V2t8hYmlrfqUyBusIMDXGV41H5pi8vusj2z+i84D5mMz2c8T98Oa1CJKdCY5FXja1/TSWDt\nD2rNXOtcZgKzLQudXyS3jPb2TCMq3jOBycBDFH65nKAyGIFyeTKPn6cIAJDkBuSl+0bjUg8pILwC\nNmlAfw7DE+Eiq8aseLP9HhlVRm23B66+ryPSlSuUGIVmrtKKhWS5OKNDEqTMGEh4aw2sGNVVYvKS\nKbaGhWe60voQWV2IT9vuouA0hlv604k3/EwY0gODPnA/L93YelofcHaEhQEVx7iesFAVqq3KF2ue\nfKECodO8wfwW+RnycXayyuWlb2UnYwFI2AUUGCWpKShmVUarMlQKrWrIhTbO+g0vXa7E7zS+9fgJ\nWObDboS6oXv3rL6aUh8CdHvmYvR8QdSvfQvK+UvouZhsqTiycdhIO9oHLN5xkd4WWxloyOWerSvq\ng8/d8gOPzhBtKlPnJzkossrJkFwt5Y5+O5X12/+c6/n4WD4ZOddoCXy8i9kTQ3C5lp207Hh8bOmM\nea5HEgG4SoKB7kJtEIB1+5Ylct58MZUcUaHt8DP+uWNMSnY77vn+3RQm095pjevy0+URNb+7rW+4\nf1D/G4xH/mtDeKGQGekaf2e+KUEiKVb4PmHoTINrx6Pv9Vg01K5cEUcjJeCDoKZLy4NJ5cDzQSp0\ncPt7sgk2Up2jSOfivtrO0Yt9UzS2JK9RnBrxR+jG0sE8Zbi0U2UceMTAzYtt/pXz5RGbTXlxns9a\niforlRb+rHpcZmBqUbX9HMaGj3A8EC5aSERwk62OvM48On0A0lfW7ckac9U7bI2UeHUVkgbsLi2Q\n4mCjKZsKM/64VwaiUxvf9D7mLGgyX+4UWKpzdIXaxzIjlaWixYOcJEkwDwe+8BIlMru9C2uZ9+MR\noI4sbmHJOyvASFf3FlN2zZCEFPPuHoiN6H3y/IZd82q3xCaLNiMiNxMCRUgIHFwWdHt5r0lcTTdU\nh/TssUxGaa2KzM8lEo7CUkgMeoU8bWjB0DkaSXtusExrM1uNSd1l+eZsOMX7qzzJPEZeCatCFhK/\nBkWBpVm9vF4v3gNfhsVPSfkH1x/AbGjze0ZSaPJiPc4r7NcPoFZE1nIOIBABM3sJxT3mv3COVn+M\n1O/O7vXVwaMnugQOegqaROMi5zZn6fGJzhh8/8IIifmBei7ylRRqhJaE1IqGvLY8iw2CFgUbCsEJ\nQTppgPJNm59zRAa/4LWLZvs0u+wssdq6yRTOLomawCTb2+YSrSm4cBaef2FUqaY8z361WXyqdFpi\nCbmgzpCBcYWBcX1fLlSDN0FTptFOxlVLEmS1xO2GF472l8hQLEqEV7vfJvno+Z//8TjoVJ0mPAT+\nOodKgQ7+RnJBzAHC2bdAd6Wr5Cs1KYmxfeO1w8diEQk+7UEYEUfqDWOnhHM12DPdhcstSug+kJFe\nriF2f+ULJp0BKy2kJ/JJPAGRt53i1m2+71io+LzZha+RdggjfDKJr8EonB3mJTv6Ey/YxtD7/aPz\nsM+MIrZOFx4as9lBSVDYwTBZMvxLWLSdJsX/hZ8uFDZQxVyFQxfvrth/I158LUm56IUJcIyHeitQ\nJFFKCU2sw7McobUMR3H0dnKt749a5TFcp6Pt9OOnS0Kj2ZJ0zW0QRSFoUjeqWSlfVCVDBR7r2BpL\nG1tjy7Cqfqv1o53HItNjtOM4y2wZ53IpX5e+QjWiKzzYm5bi9Zw0sqCkhWYea/Ikvaaj5i7a+N2Q\nGUDekF0yxvDgpNKLYReqsEnViPjfOthZsiQ/ZF4f5FZkimf28UGqFSCYBhoyAoZCObcuokDZHSc7\nqbD8R5YbQFNmIhBTfo+LwHmZS9/r6GTAHKzt3NdOZJ+BlaPdFo9LoXpZFl7BISoGQNZp+cqJmxMX\nlElx0u0GPPHTNt6ilQWCwLZM9xFAQ5dH9aplVb1fFAdsjXUEJusNpQVa0ohBX/MlRqEA/ok7gkYU\nRg1Sl+gij7mTVCyaeKWlDR08H+GjsgnqBew6ptWyV+BLqxz1pIwS1TPPT9g2LEF/AXbgalw06Mhr\ngWyomNUgaddL15diQS7eKVlYwVtuO9Dio3USx5ootyq/tTQhrjkS124tYNG/4ozFsQy8kXW/28uQ\nVj60rTnm/QkMkD33zu8zBwXYOZ6+BhuSbsTph+WRnBagf9hxLJXfKYBbTirzgFHDPcrp6unySw1h\nXerYV26lMrK/9VrkVxxsC8LW/JGxQG0PHDl1cLs6YGseHZQa/ShX8XE7AtAYkJ56xfWkYduswh8s\n/xwWm/i19+VTuedahTPvXTRWxxvy7nbn2xV6LaUFixHNVy9k8lKLRdXzpNX1zCe2kB53fgz6XHnL\nxhN2WaHHuNFzUWCv8NghHah9YgCVwcCYh8YcQrqbuhpjVm/NprIxoZuqSuN1xRy/zfwU28FCMI0Z\nb3PwLG7AvfldFgTZPwBIWcODxzP894mHaNG9itsQjhW0ksSSxvYweLBofWtKhxFthCxXRjQYQlAo\n14uDlf24ruW2lki/ARokBEZ3c9WOn7xG+8a0XIAMh2Ze32MFWm50mba6Yk0jKXF7aZbfuH0MHbk7\n9U84WW80Rl7zWp7WK3mvHdR8kaFAyO/KFGsmPo3QwmBX3cmq0huPQVvvq9BjQq8b6DVoR0HRMFh6\nTS6HT6Gw205Po+wLRbrwzwbq6pUVKfHCySnZhHc2j3EXi1QjMy/UoGuW7bFHDALulwEzC7c4N1nP\n58hDhowIruHJ2UgjnpJYzV99YlPGs3RNfL2D5+uUFvkflxDXHnH14Ay7+zHIxr4HvncQGHOr5Fu9\nhSc76XDHb8pIGd8IdDD2aKLshPMrNF7ZVpt0IS/ThWkjpqI4HAwa99Oor5TJGkGnrK5nXCKl/V4U\neaSxXvHyD26Ry4NGBk2JasO8VqLSOVfuemwekAA795kOriGjdcU0hRZS0UK+YZIbt5M29s5xxQvn\nZgNF6Abotf57E+YP1F1eVCsopFPKfvATEpYTvUxBFxW4h/29TjMvkq9uvfS6ys+XhHfCrVIsAwv6\nr1aIxORiIZbULnlflxEryS///gUFpreGJpoPgLIzo848gKdf1bu+I5g+bikGAFcVIi27P74t0Q3D\n2+8X3z/i+DPkeMw0IwTCCxYpl/lnyV84ZlOjbvO+yak1dW85HmcOxI+Yx4X/aTWBxL1E1JUhsXny\na+5tcHCihqtH9TJ73Dz1Ctb0OQgLEcfPmziIrLrdgcEZv5fWYBjEp1PlCpqXnSKJik/ADIM2x1ZS\nwTuWTrBZXoTUnBmLXJvXwMOS3iK93JnKWLmogkAwQfj4NpYV9rRnNTEG8OtcRO6x+ScjxM3q2WcL\nNxMiwGOvrqy1PNsk5tqJrr+C/vX12LjRSBmKiu6xD3m84Sfo1ACMuimkJwSHDqd1FhpqLMWkEHd0\nTlg38sEgiPxPzQX8nNNDU+AP4ONfUTzkEdOKcKZiBzccH3Dh/3hMwpWY37LbN9EhqqQ6iS69/Nff\nI8jj0x7Ekmf6ZhNztfDvMTrHdMA+xBQdc4cL3BT8LiOLzDV8rROTTFwn8nHNro4jnAUqYf4sOABW\nwXiNohg3LLOwTe7gQpSThqCx5mSjmdOvwSEZXlSaciS6BJC8lgM5zJSzOURYOSMRl0CzfSVfiPjL\nl2lYdpYudLJqm32t+mntGbSc1wCqRy6djjjhFUadcHGBtn7ZMpcsGXeZ6PRYLYuWEiFrcxdeCBSJ\nMa6nR+aAfqAll8jQGr/c+1QtM1fgbtgUdnqpw2qWuRmW6LDkmuIxUHDJ+RS60L5zrYrgI27cYpEK\nUMcf/Dju2oqap/yP9KN2nvWiK6+OwAuvG22RDw7VIX/YU/KvVgED17M9VrSaGN8tqaHzNTGM2IDV\n7LGeSz1D15I00bC7lsM2GgX1s0o62Iwj6j/6deZ1ZiCwBtmmGzh0KCdzK/qSxCMHjC8qBAR9tQhk\n4mPouLUTQqh/4hTq4ku1SbVCqI3ZkjKytxnuhq5akCqQrq7Xx4JIaoeSH4sVIsXN3sfWGc7Zdh7T\ni+pQhzqsbkDGV/HO8zi1aJ0mPesChbkgZCI74tqxqtLgFFdUJepfQtEynJ7h7I8ZkfjccYsS3Ohl\nNdLTLxug/y1cWwWXQSU0L5+Z5ElHcoJH1LfwaUMungbZ1U5u/8Nry2jURK8LFHaLT/yRSn4Pg9fw\nuejDkeRSbGy1MMesbWXCO/uT8gOA9JYa99/xwuim3E5zGDUMaJWKg8WBZVyKEpY+KGjBFJOUrtMj\n3rcJNY9d4slEqcn2wDzuKUIcttvsC70XG0awDYSDQz2CYfHkWS5/uSF4ALpgjLcBzwC048jZUueV\nviWS5VudzFvxXLkz+NbWjjiE2B1O4wAGgrcimGJyiRUvU1wynIl9r0Qqr8iOCQSA/p+8qQ+0ZvY0\n8OWok9uq4V9RixaeLSckAEEGfom+KfvqiTv6AE9kw5848t2IU1HTaOCavLmA4A72Vd8XeLeqVW3U\nORuyyYkVjVxZLFIiWhx6jaF1/WT5jDluydog4xcvKVb1cwhxfvI67EmnSWsmK+xxBxA1Sdi7WWnc\ndkJLSWmQspe6eQDylbt/PkPSCYJz6mJ1PlmhwCT+ocHTX24eu0oRM0yobEJ+3BSUeR+k/u097WQl\nwq4+Q2wmmZFNmiX5L9MdI1REqstsyRBeZ8mabMRSV3ztx9WkA0kiru0Z+odw8re63Z1qNv39K66I\nTndTC3lMVLOU7jlDSzpqlgvEx8YKdGwtWR10ffvObGb67Bs39n3fup2O5Qi1hrrMjj0BIo4In58J\n8LGbRJzf7MFALj6nevF6KLhs0HBXaaZal5m62IjWRf2V4Mgj/ZGFih8cnTIM6QHcU/FgUQFPePxJ\nUFklzOMkiUFOiXbKDmaG7rsR9wcJTuZI4OH2Bra0GYY0KpgYcjeZ8INrWeiRUHCuEdkTH4UDhyp5\nkd8qBv1XPDMPgRjQcQXR6su+W3Da+OSeSSDEz7Jqx0ORWQwANUskxJVyC8b+ewdldz/8gCmU3jLn\n2vZKZvfj6KayKRHK7FxWrJokhNjnuKUgWI84ehgXQFuuDHRJfsvH02d5LM9+D71xfG+2+9DfEDEM\nzsiw5dAyaZX1pVpkXQoCukJgESE+6q1hKi1Kcz4k6hy82Eu/uov1cLMo7NeNKQrZHJ6lX//AvLfO\nTUpHyaByz2otzZmpVIAOL5/ycXUC0C07jfBxvL0sQKTQ/J6GtD+DUSWCHZNSFNqTz0Sf0KmVIyEQ\nt4myxo0muliPnbEu6LWT/DYOv7SzJafk1TWWvnEHUrkRmcqohZZisBgk0gIpe9nRRsFcWAwQ0rZJ\nr6DiRpm0z5qDe5QA9XauzWq8kyavTYLromTgMFc3Y0S0m9YSuzqOWbuo1Jb6MGD0y4CrD4Wos/V1\nnsoQwwLEOtso9goiwNi2drd9k2vm2wmYUewf6sazlvghzXheJRjDrXQIclJ+sQx8ho5y2EA8Ic6t\n0rw9KrHa/tlPwPMY8w39fnveTmcgywMtLX7eEIoqb4HpKpm8TqXczal7spNuWhPPe4J8DTU9T3Hv\nZFy6kHLsLwI97vN58c1TNYlnFDCCOmFUkoE97iNuWXejagNdoAKEE8wtPSGH8c8YhdCepyPwtsN0\n6j/dy7KxJmuxggcEYvS/1HBYgQ9IQTgGeHe+RJtjU0abY0fAFTcMKKVkS6VdimguNoiWsWPhDf0T\nSQwbwNsrU+9Wtk+St0Ib+B9D5sjQuAl60CS0arfZtMR1ZGkp2AlwqMlXL4vaFfD6+0cv26jC0RcC\neuQ631uzlivVyMyfaJW2a9/Pad+6aMWDv0fgd0t6wS3X7Vw+GHBo2jfevvFiiEvaY+OWL3LXWfDe\nWqMN0yntP5YqHFz1reseiRFn8klauOW63/7kJQB+WG7swSJKND/JGbeQfPCFMEOrNpHoGrVMfmIr\nViTWD9s/E+x2vSdqInLC12+lG30LYxhcaKGGtog0wRMOFziKHHGkxpgd6cIFalUPDVmH8D4Z0qYw\n0EmoZQBqSKVUt0ZAC6rvQUOtKdJHZHubC4++dutZAVZmAW5vZrIf5aPYUYMG7yyuExnDIBf6o+fO\nUKV4G48uKd6r+L0b/4kVosCyhh8DQ5xPibzLg1awGZHznPhqhCthPUNnuweG0I5j25iasRN4R/se\nvidCKbQjy5M1KyhWL2CFqpN+LIkJ4Bce4uGoB8fJ7Rex/UjHYfduoWEsh7Lz+GgUto4MVUyVg7mk\nsEZFgT0oLlmie4VzzARU+ngPfgaDftJgrNaW92UOpVa1AxvwLiIJCFPT5oNV9UpDfoEBZnmAcFc/\ns72pZNIMZ/6PBd7MnAAE3JJbkIUvr622GwGoBDkHTSTzCuTXdcAmpuGNS6qzrsglL8GIEnq1azaB\nfLcxBq20pyiPaf5WzT4O3YJFPde+jrl5bIi3nQ/xIkrPgyaixO+9g5ws+vTuYlTdwV+aw6Z2Eg4L\nwTCBB92MFE9JDAfYEFsazggJ4c+CFEGftfYuh6XosmP5Fk2EHNRIzIy1GE0uFYNCr0HrKxcDU8Gw\nvwNinbs1W26C6/mfEoCWGhtBEgXvy0fxpOqlczkT3MzWVB1H/3MDHhQhbdjaKdZKrhbyPefTM4mn\nRUwg4H9UKqMMxY8MpelKrUSjY5Rhn0E3IibFJGNmP1Km6DfK6Bz9izzj3SlBM2tuyc/pK8pJPybn\nVY7xZ3bAQA9TCSrYluNQ7Ku7eTeKTnQFanDf+MV6WzCmwj/zQon1Rytur+gV5eyhsYV7rt7bFu7h\nYnzt9cTUCyQWzC0jEWUqDg4dVnDKcpRaT4mZghot5rDxL+LgRbGj6bzvgkMabT8xpkNdlGjJN5n6\np9xZNBlZS/KMEkqIjAI1tdGO29hkLd7oqYF274ELPP5l1CvPBr1u0PgGilPa4LGW2TNx1mBux49h\ndqlUUJe1nIq28DPuRhe/YqGf4IUv+bihFqfjdOoPzEDxijtuPjf71rL2EOjqhbOBOoJS3H6yjqoz\nnAgVC1go6wodCenXIqAIQg78k/lP48fYaqhu4Yaec1dXXV8UyR4Zw2pdUFtBABUjWJbl/a6GZUg6\nFQ6HA06wwYXpfwivS5o95dfQvMcshAMquaE+Uk7t+zpPrFxLnTITOGafA4+vt7+zSiC+Nf0FCxTb\nMD3JDvplk0ljylaXpR0/mYid+K6EEN+gcyb/eY8i6/xTRvPt6GmdZNHeibD65PVZ1rWqBgXTyM3Q\nq3IIpyPJkJzY+dHBPQHcnUE0Yn1Ep7IXmnIy86737wq6h8ed84H8QzVuQtKAjWD0h6Pdq1/8VWKH\nQf6Srovz5Y/B/hEnFO80ED1zrw5kP5jGWIK3lzHgPvOuov0d34iKEWXeDA1xSD1h5lLNSBvtMG/n\nYgutmfLDuIKlg5CgxoWNuDOxK7CQNUvrtTlyRBS4cdzErCBugBmCyvATG+sl0iNPlgaSxHyTegVY\nCF1lMIotYzUCPWG9W2AIfo9xEq4BInp5seaDZlWAueRWsSVfIMuzGl1plry/Zzis6CVGs0QpntlQ\nmXpu0lGftlcasJEbC/EZNjUkOcZvVxNtpZdpyFKxmmejHkcvJmbKiZt61rr/Y0W3No1XLwbUfIhw\nXObmHdAFsLR98O7EhfpIs+e2Ii5vn8lYDmRa1gYK9IFj6Ikcd70mI9RSPhgpQgQn3CW0vX1DAdVv\nHYU9u6ThKMw6jlvFyHneAkBJ/NueXZenXLAhy/NmfEin02PEBq8MvZGes3LvIR6fSlYm2JGR7hcR\nscNtTbmuyI20CfzH3330djQ/hXf+61PlvpLlebaC6yhnnSQHSITI0pUzl9Ao2chkGfLIv4lkarzf\nVvGKA6bR4cLQ7lfMSb3jiAK/QFow/pQOHeoBGpiIJKnyfBfm5svJ35ns4KrF2u9yX68kHNn3GzD3\nHgV/iy4tNWUmkFYbPbbXyobnNbXNQtZOX3Rp8AOG9/Oo2SEnX0DhJ71qKmWpcbp/1BYCRfkXHiqC\neBMAYFNqIsb0UFGb4p3NWy607mqLirPXn3hFmV2MsgJ+JIeBuFIfOEt+uzSoD8KC8tMwqJybtYlH\ncmA7TusUFo2YYZJEMC4hhSPr9Vf3cxQ9FdrWuhoeFLtW3XVvlHvTawERVdqJGI33qy29xmhJ4nz+\n7/wP/l+gt5FG93Ni/8IEm6tB4obo5u0os7Xg7gmEy/6HCVFtfhNkqZyn4LTI6fi3wnIp7HIJWPkw\ndHPnAy7Za9wVoP70xhJbmtieW3CdDLEwW6k9qRmo91m35ph+NUrp6it8IEB3jqZbiqJOrGid/bGt\nDRe3ZwHQlGMqCSrGYYoQkn2elADRgSBi+SEBmIS969msvSUdcffrzFh1zgziOwKYJ7A+zgPAV5wQ\nmRIYCaCueGXcq3+Y3dqX6Xz+q2Urhdjug0VcDF4LTRCKJ/z4BoxHnhPJ0Kg3E/XNFOrxbodTy+V/\nf60jkELut0u9bDLnWv7CI3wgQxfZmbDzWDBBq+CqS6nFL3lJI202FIRh8gHqVyCn6QXFS84Aps6o\nsVsDBM31a9sYV/0IJ2eoJXSJWJpMa7JuEJj1QpCWgKPuFUqL00RmWetqTT4XnPXnNJc2l60XGhY+\nAsHEmLA/EUP7dssvL1l19DmPl1664WI9yN8JwrKMKIQIyQpp1lqKvA/uD8KUtUSf230Tt66HgLB1\n4j+idT++O+33nL1aQTVSDABPdZnV8MsvJ5W0oJhM5T5tvoPxWS/TY8Ok/AcSZOzeVYeGdZxwfQ2Z\nG1fYvu+0B592E4wGHMgZbomABjWALpDg+oDRscuswztBlv34wRiBfRhVq0+xjopYKqaMfRrv7Add\ncCpEx8xtg5/R5o61oOJlc15EqnvaFBqF6W1GW9eHl6mEvxDHkpVbvS0Z/XxySSsBQ8B4OtJjUiJ/\nLgEnTM87J2olOEnHHN/z2It2S/AEBFqRaqCJTXLb/vXe6gKekLNSu4qO/5RJpTms5R0vX/nwTvkl\nEoKqq2fRO4WVPGePAka7NO6i6uTxfoUXzyuckHg1WMvjj2uoW0aucppzCJ18nGBtTTqK9/hidxWo\nZypCiHytpCfX3S+v3W8xlss9vPeb8XoUbPytxfgNsJhLql8YMcldO5pFm0jVazvHJe9caPj65/6a\nmQNi5o5KGRI1YrgN37NHqaYSj3ig9w5K5r1vTpTim68ZUVHS2B70gveIPxtcfJj6MDjza9KDgar4\nL2j+0oCV7N5QCh+3eXAbatOp9GsqEK8NyPLDCMsTtR2UVyQpbKmXt/mmPW4E10r+zzMfJ6dDL2lA\nedhHtsi8mbms9bRX/Cb/S9SduVk3vefqeBSsK/lCxd1Gm+QXnMErrXxnR5MXNN9L8b0mosSL+4s+\nEiiRkZ28NL39wlIq1dpcgq2SObgCPTEHfwEkBROFvzkMC37TQSu9S55uWIs1FuyuXNLdBELb2ESV\ndDD+vw0deBrYhbroR94kQgadZshZY9xcmMpkOPQD4KJj1Pn9KyDfiFj1taahXAewxkfUfjsZLNGY\nj4Ufii6NpDrTkb9+WFudZyVk8IJKiDgggd08rG9vKD9IY3z+RAejotDLYRUnJHNKM5vFuzrQceYI\nE6Tu0LILRbrMcJ9tmkKRGd7VR6llDLUWRXGQFI71zJIuhxIVnSw6K2TdqCyvxxXuhHR6BrdlFIW4\n9RvXFMvEbB2Efao/7VnpBqBp5x2b5m+6iv59/EKuhg4u4Y8peLcZ+Zy2t7kQ4FbI3hmXmVxnqDkx\n/mkTxs0WH7D6PwoVvsKwBYnHonDmK161cFu2IMNNS0kzTM1oX+QFDdm8eCu60xr8VrnPYbIBO+4w\nMkhpp4qJ3tFvNXTiz+bKC9Jhmt6A10MXwDwgHUfcEl/+8zM2LF1wQIFtW71HHyjlTrl8ezgvRdIL\nd/tBKgK6FOeBmfE3j3rqlvTrC7kevvf0QS9YvHUUEBVwG/Y/waNnJizM2KZTUGRpTQrNJ8b+y99j\nepvmiFaaadQMB1pMNQYgYoxSxuEnU15ZhjWo2BAAGL9Zr/ffyHkHoBcxpYlz/iI4IXPrYCGEhdQp\n0AUwN1/o0xWBJJQ4rT1vsZOGbAMTJIKFZr0UmRKDKiYZ/n20BZna0F6r+KyX6lQ5I8WjKWsQb0Ur\nywvSrYTaMyFHYbzNuWm5oEAQ9Xz7DewoFdbX4fReQhA197aZ9TPNlFW/3EONWP9RksdrMk8qILgP\n8fx7K3mt3OICfTfeW2O9P3/ge2LbbShr1cNO7VAR6H09wWhTRwTSxYTIXy/bStPGX5GrfEswk/CF\nU1VpgaTDux7IoLgJ854i6sHqVnUtv9g/yHrtHg1maXOyWelyjK0Obe1cP+98aWZkOSQehCaJ3Pdf\nyDYQXgOINx+M/oSZrRSgRxlWuoagwzJfNmX37nHCfzajxk2lagYcEq8gAOWe6qrQyj1YyYtToghK\n4us7h4un8UaPqBlfdicmryRXwhbFdEKcqhJiCFfpce7jAwWJPjIASAEwvs+2c4dClq1d3impKYP5\nRXndnYPvkhD5HHyrHqc40lGTvcw2HG81JeEuWRVQ29NcOrYxAdZDM3MqajlNFm4KPFJ+Hxkf52F/\n3dKkvR8cy2lpV25ExE13xr1Fe91exh2KVl2IexsicXXmFFg9Vp72h8Xo01Q8Pket6ShJS9tPEh2W\neRtSyo8ZESXtb/eYmlS3r9eud5juW5xJy6oIhnMMpFVJ8l6uxv5FaAiJ1ou0EgV0ZE2aO4sjYXH/\nlaZjJA147M8OsNHMxQN7BRS7WTiZsb/FU/f6R0AEmkkVR/90sKRYYhbs9/Ms8t9vXl9JpWoAVsGx\nm9OAOq3DbfkYT3OO7YuerL1WuO8Hxfa8GjT6+tX+uOYNjyXqE89/Xzuk7nZfPdUu6cuCeOv+fr/I\ncAw+XUXFY9i/EIRBDRjeI1BGw3CRnlBTE7UUmLRDofAmzGNig+mvmR4GTX0Oy5dUisE0269mncb4\nRsxmB9BW7O8baRCKKBDNVWCKwr+gmHtXhVN/Z1t0axbdVnFEWNr39f6T/0oqPp+FourFiT6onjdZ\n20RdryNEaSOdlViXMPAbNvHyEyRNI07lZrTKLi97KNn4Ow8ASDwEYngohaQoWBjBeyzKvTUYKu45\na0yUeuB8zIuY3Yrp8y6+QOoVjbMCKrJleJnf5FnOaLLW/l92IIofSSy1h7xZmhNK/MXcDvk24kRR\nVzmT2+lbkK2YQC/Q964uZCgsHP0l3YSIAdOyHmsDy233o0GjrgL+Tfh2dHh+94MH439aJw4utIjR\nAudhAMZsqLck2OudCxFR9GkgCsLyR9MbzZrDK01gDt94e2qTBEIPYC6QIebeYJCz+bpTA8Qp03ej\nDkBFKXUUn5wrXP8exjyoIpkZ81yKHXpx+nnRQ8t8REAa5ypIf/UOHBalatg6ZlJW/PQs3YKcYXBH\njpMLoQn7CQZpg6FcLCTIh+twsBvnEf82dwzciuzXY5IOPHDNd818QrYS3FGd8m/lytyweVcBWWfq\nKoyDlZvYKNGbIWvieucWEaIL/GpaV0nej6it6vpkx1C9mcdcpxygg8EwU+Q9TqebsjMqdMckx3YK\nPNUJr8iTsrX9migJ75RE6+w9+v/3EtfZC4hW9khYG4ehiG+M5NeYVqzRaSnGNxTsZOb+cuV80hpM\n5kbrEgdq80c5e8zHdush5wXifTorS0vHdVzUercyr8LwVJDJClHoXRguNTqbGzfRO0h3/SGvKfXv\neJAFBsonKZpRfnFNj6KXfSEdlPLoKKr2x0HKnjYHa1O2nFSaZezwMmf4wazBPQ2DvJ9Oiv4B+cSO\nFrAB8wovlgGSC2XpFWY6/J0v8c/0tysxdLZwUzGbu8dXxS/imWXGTMMPQdZnRxoPaipn2kWbYnTF\nnebNrre4I86/E/MFT8Y21DhVJNzRNsoxMZcsN+xeVxgYBgk2vEV6p2llC7JNVbDqz0KsU/V0rsyI\ngQm/Dv5OknCFOuVM+YOoAwiQreo3nHHdWbkeKYS42sw9rv49O4vtL+QtJG7863L8dumpAYndpX/l\nz1Gp8vM4OrhYt6Qn7Rephu5lrDK7nVzVXDshoC1XzCI5b+aWHtB3iy4ktbPhgW1yln18ubd3/WsM\nnWrccDeq78IHQn/pf1Q4C74LUgG1jkid0dyecwvMHbI2ps7Hu6/9Ythx+yi3qypwYayAF9fPpugj\nAGgFBNzwnSFWMu39vT/o0r+mz/sOype0lCGpF/4pkMi3rVRSG4O0wKL012MrdqPUvL8lCYvmJ+E1\nYJYQR1F3oyY8qWklcIMSIXeGynLJrVEkY8EVdyDlEAbLgd+4Ytzbm0tUG2XHH+r9NCOZkk/N67Jq\np9I+cnMfr/AYnJAzABJPqwC9dekyl7KK4usEpnjk4Jst0Fp+pfNlYFododZooqmxfvkKJOurqkwG\n9o37CP20uKhZzJnqTGNL0BC5/ZrvTabulqD19dFpDdg6BGd4vREAAd7Gqp6jxBTvNRQZI20d2BuN\nFBJ+8CziDWG2CsBdoGlI7NdjcgZdBsO7bvCNqHFa0FqWkby7BKVuAVekUAfX6RitgHKugIXhgtL6\nsKnV8v0tfhlaX1xc2uSxePTfYsMtMBEJrEypxsk7y+Exof6AoIyHBZiBvov/hxU7bSHu/nrYNAtZ\nJOYqBNYGMfxaAcOYVe2Vg/UbCHFlV2HIZiAy/gD74Qg8icJ8RjS1AGd7t3Dk0zDERWlinv09DBlM\nOe/RudF8dTfb1DI4g33vSu/OMHm8yscI3GVxGRciorqLX9YRn0ji9noSlSo9389QCFCp9RXOEtub\nh5gnB6vSUDvEZ+umw/C2GQsl7N03vY9FJEOftg3+o1uQb4q3Pcqa+C3kv7Zvxa0HYtc5N34lWXIf\nNnfbCOdcO45XUaPen+411pPcsCybMS7vYf2boFvZ5C/oFH2fxWLeYOEFJuoD9ORHIeOGiqq2yodN\nvkjolfq3C8HR3ywAan1BP+qtapDuBzcoZheHEq//WJnF/kqoQNkhdeaqUGZTcPEd+ZjArKCdPj8F\npfYhhpY4GrlPpFnwlw0oyYNN2yH9Ii4Ym1coemVDC2afnECWviSn4y8fQLYRbVdrdsgyIHaACUNk\nwyoVtTjt/lMYUFOOpEZgnmcn6PwT0vtrvcW/0wDZJFx8FT7Ju3V7FVxSoVhzWr2NgXApggby0G7v\ngaBBC5iIzSJRRAkwOibIhjQGupZxxESlvPAZfpeWXxnyA7YmEHx4EJy7vwEUvvvnwMK4pZ8RTQ5t\n/qgGTww6jntZ9YLCNz/REKPFSVaNFPCQvQzf2PNJdPe9a7OX+C3idY7WlhggbaCeWfsFQFq1n2pI\n1Up2Ju1qCayXN2bD25j0qONpeVV2wMTfA3/0PQvZ7NjulQy45kwFLhjrHKi1SZ3Lo6IsHy1W1lzz\n+T6kjyQDgHKEPxmgbKEePSYFw9m57IRBSB1lVL/lXhgcp3fV8iFAZbUz9vPdCXYkSA0Mnop9p9+W\ngXFiq9fxsGvjlhzNzacvJJ4lNuEZy/8Zl9ywYYRILB/hbw3jB6T+Sl7DBN0JfR623qilI/Erkl4b\nBmEHK10J5v07/+2OoHjVtND30VN83BbYkj0GCA3AG0xNTll7Mqce7tDOC97j4C2DJqkJ7bLpOw/x\nNzvjLevB+tOm5fHydrs1fHRGOLNpTd+tNaXzZJLicRPAQ3PwRCU/KhfUhD/lnwMquRemNah3+9J/\nWbDvDX7y5pZAwtFvTl1Fx9D64CTBMDRLvToJsHMW7TNnmchuf6e0UU3kSMZ7Qh6GBQTbWX3QM6H1\n891oVivzTN/iAvn7S3PCQMqWca/8EwEySxPLhLv/V+g2qU0vWgmRAwgSZGW8qhB+hKiyROe4iovT\nZ7f/ATkdIc/NU7F6uAOSfbTF5HtIKkHTtrRBh/GPODrZync/1Unq6XicDyUoFNdJO0otZpWg0UJr\nIm0baDbtDrMr2nxM3f5NWpkThFB7ogT7J6jP5Uk/W5gA92yUYXraImArkXpJIkzrMVUBcZYjVXAK\nby5IG+0dAnShjrYUMbCDCeWRqd23AQ+Gmib9SjRAvoyzqNSavj1SBCaFi+GWhUlDEzJRjcx8ucq/\n1O95KAytmC/bzLw19wV7dcHvXpYXenZdTj7NIqNvkMdEFQQ3W98i9NwAcYtUOEda+02qLkc78Imt\nEFLSJZ7EKE23BqprZuOH5UTGjH+bdjHnBephoFRnLuwZvF0sPVHLCQz6E11Kl8x67Lg7TMz/JMGy\n0QWWJno+6E233Lt27bt4uZOF4ridnseWnNw42Mojo2ZkS+F63DJcZlmjFOGUVnis87CHis7eVVVd\njVZWDDQ6Zn/wZ/rKAB7Nj8qRVs4g05fCKKzodda4WHnCVF3g3nZA47sdOjb1VGpJCwXqP2YcpkFT\nTAXPnPquxGaaGENiXmKqa5xdskfuw1Y4af7vm1MqI6lcPOF5TxhJ1Qtt53NI+69mG9IdHkpVNj1y\n/G16ztIE1JNeEtmB+BYO0mO2X0dblG9J2YB752FGSgWYV8EnXjP4Sxw5odQw6Wt5LGoLlfylOGcu\ngbhuMJQ7pgb21+gJh/ngTUpwzKK4Hcn0fA1ilriMz/e+CfZFP2IgWlQ15Yt6ECjl/QAX3aAyciLi\n2pcfzoq/Ic7mWuUiwcFzJPte9OngUghbbaNHB8SJIMiopXVGkfr1KtDxrZ0bsWfVaqkM++xgcUOo\nbMQ4UTmjeig/FooIwVWLCwUblGVHyWYAdVeIh3843mflrTKFyQwuXMISN+lQO4i+WEPWHPkml7La\nrjWlBEditPmyzJHe0W207fjznpN/km+Ne2v/R4elmY9pdqL4KL0ubbaOaZpAvlxlAisoaIZVPDq9\nF4oUjfoRR3053AluL3WEd8t1hWG+I5767HWYMG+De6VQRXGb0aE+8M4o/vBinyggTiXrkFS0wkPm\nPSObUf85seJ5x9gm9winqS0b1+5gIKEfpDNZNwf7r9+HUqvigZ8oPVsbEWjjT5fm2TgDLUbBVrT/\n8eMGSj2YLSsfViqir+717cLXHWH06yukH4WjaOXbulc7zkI4iHRX5DuvX2hDlEUCXju37W/7eyVc\nJaxXcJsw02ylBFhVwvLwRDiJUFT4s6tL3oofXqp3SAfLfm36qZJ5jjLjKeUwjot1eGA+NroRHqH0\nmgtjvwYrR5rVyVbWrYwo34eren6W2O7//yte0mey6VJb5UQPVQjQLDyFHJ8zSG/AiRjgwri3tDKG\nrA/0fUOdQGiz+RwQmrOjtDLah0oLdcnKNGdOuYgfRwuMR5kqO88aRVVDccmhnSjkmckLlEa3UbW/\nCCaLOdPOZVG43P03loHDBkump67PWIwSJufgTY2dzbjHQYWFJH4Q+HXVMJAaKwMREVUD4RfgA8lA\ncyJvj/zKyZAJEdF8EP0rk8ZsS+FplatlugSCfQVGudYccNSYpvVKtoiX82LcJs9S/HqsqzCrhkA+\ngDJEbI+8wshtd6KxUXstlXRaPBq/JYp4JESRJqGNH3q0MPWYudy5IU1Ex+Lx/WqW4Cyt6RXnulxh\n7qYgvc/1Li6u6wA2y1x1R9g6qBJDOmN95n40iDkqYuToeiI3oC54fxAOfE94As08xEGHE8kAaOta\no8l+uX4BdtrDoafhBf2VH9N+GTluvEe71ZT3DlKFjbKEsaA/9rj28XJic42JsPn5qkuf7gWNqSA3\nFkaQ68kOF/xwL8BFwUA4I1qpi84bn5o2gVQdLJJzvEHtIQTGmhCc685iDeCUbdbkw1FT3EXdEz7K\nAXzeVmsQTC3MSoefYgbwhcKSCniWMFXMwZCvqu1o0KOypwDjoi5M7wtwWyF1ssuZ/ERb8vFk1TKq\nAckwlJgpVQ3g2JcrjBwdIuAb6y0vpTto8iav0v/pMkDxrkPHa+5edxeg/bR57Dg9M9i6T4QJB6x4\nkkfyZ1w2jFGdyASCxZg+4obC4Xahrh5rvE7rpL/jAt6/JytixqGe85/NdmqycrPD3SpHj4HG73M/\n62NrImyUrHvAP/qdOGD93JyXizrcbws9HXLDfuK8gmZx0E+Q17Eq3ktdG6Im54bdQOOQJT4sbOhj\nwp0PIO/22O0nZVQBFd4Xi2gytLXMo/Jexr/IaEB+IOp3WfOvck/ycksR8uztlg5RC4mpYN3WvnWk\nebkIUPD5cYMCH55xQdzKPFCwCayAb18492wALyccze3xXGlUZkys4O/HRH1NCzgQIfHuZ2894SrB\nXxp20sVF6LGPOCfyBBGEGgpXlUGNgf0lYkUvh1XfD0U/PLpxY6Ms+fNecyGrWQ9Zboy4U7deDa/c\nlDarHQTyrSK7K96Z8gTxVpqWF2ltlrb64uQ9JW0doObxUxumbu3P+d4gfnwFzwxOKVzdeMyxe6ho\nV9G5KUKsBFPZpOaKb5eugVmH2PkBA+lWZFeHWTgOtJYCBZZFv6u9RSZ/ohBhg4bYVotZCYdVwtqa\n/z6XJaRdUKc7E7h7UU0qs4oLqh7OeCHJ9CIFiz6fOTG2ydP3O/+LkIHXj8M07BNjV1vW8hn0jA44\nf2gzojPMkX9n+D0g3kJXmDfyBJzwNG5z9hK2a6xXRgJSRNSGNPNF8Q6IrUJsBaTi5m3lrKedv+4a\n+kNlozrJBXuzvH3eArtARRpnLD4jSt5HAGRSE872rEU1XwbIxMO42s3NXr4zBQu92AdAFd6bfp8H\nb+zjoiUSdpFuOIqfAwt3fxSo6+1wwapPzNlUqHhMfKTiKqOukaeKPDs4E2PP8jHXvWzRb2W6uJ8Q\n59Dysnjtz2acTJCJW5hkHDIlnjwva90WF8hnAXeWRF1JN46CA/Rg0lzvNiHK/A7QSJo1H+8uRIpt\nkR1XM8bh3jWFkHTzVyHdNqPl8PnAjGBM2Z1QeXZJ9UgtO2amnqcO2uhydu4FcnssdGAo19p0K1h9\nDAAuNoaj6+8g5By7RqQpjLssbVgkTyW2vgACzh9kZEaRaGbIVXc5EbiZ5jUniul3T1QSfYmNpXEi\npsmWjHWBONA4r1AG2GokuJkSYdWmkXcnTQrzbNJgVbhz5k2/PbdNRU9yiDX8+YBKuaeJO8r25UBX\nfErFZr5+j2uKwIwBpHVY6ca2PRs93wNUctx+wfT9BmhWV0KOrESlVv5+etnqOZyBBj8AOy3jNLaJ\nMW6hFuSWpjVJiaK2u3Mec+zcJMOqdTpeebSCfSoa0Jv9KeSoeHd8FEP+uA4+6ufZs85JJSTJ6YeE\ndD5VHAFVYTgP7+/ydJa7bnw+leDGzHgOlIsqlASMGbXtRLxobUDu3rtJKrKLvzuusyGTvByu6ANW\nFoi27fW3leSO/k8mEYEYxDviJtlzV2Ew4DCZwlCStk7F60g+hqb8j7JlX/A4sZ7jNvzGf33+oDoI\n51RkUjiaAWH927l0Zax1VnBHHNGY3/aEcP9cn0JNLWqXOPEZaDG2AEViXc4SXglF/zjYRvSsh4jm\nlZDf+6JLapKNFj/U6WOaz/1Q+jnLOy/4jwlbGUui/0pxOwjO53EiIb8+cuRNv6lgncg4kT0vZhYU\nqI3kiVjWCqaTVYo5J0mDy9VOufJyjis/Owf30YbzK8tXhskSMnVGCEYaXysqIegIAPK2MYigbHv4\nYgV5UQNE+eud1015tIvPOBOxwMZFGoZE+m6FcD/lb0pip+7XGQHKbLnWpuM0J0Wgyt2oHHIWuwcE\nZmOznDdt9PUrecb4M0RmzKCR49k+FFBt6PVGZKkTDAMkfCcLL7TnyDp2ufoPjXYl8eFikpZ76AyF\n0O8LbQMUnC0UuD/IV4loxCdPwND+BUaV+xpgcTJLITJX52+GBY3Jx9Hr10udTcpWA4zkVkU56kah\nUtNfcGDqHyPW9c/wdOsB2uNwjN+kH1WUsm53Gl6HdZ240slkKAY9WBm70a2L1U39AWs23CzTZB3W\ncq8nSDk+xg3/2LqE44rdfmqjx4dlr74zmxQFFwnzD3CgIZWuHOT2oguHOTgfrH5gs2jT8m2F3Ksn\na7VXwcQCjVrzGbUr88rB6mXeoiM7Ax1aH9Cg5ObBctrpOejx9vBF5ZDxray1IgUot9VC1om7YIY/\nVdYiLhpe5Id8gygXCI2InUDOPutyjOvW8Fy9xpQOZxxhtV+CO6VFfW5C17Xsl+wBOcjKMGHvDGga\nDDIUGcFGlg/SRkMWBD/INUhFIG+AHsUj8zdIbmx+mIJGl11P9RlN7v06g4LUa+/N8sxmbEpZ4TCV\ndgfWQ+O4OMNl0uOoqVFcbkk5KySct9h8AAiRe1pApC4TpbbFdrV4F01uMNDu9JgLSfjJBAS0Wqsr\nWVP/tTJnBDUHBQREgEwXmUZaPmhI7TTJG3yrXoVrmGoeIH8lJRFxDIAT0j69KTSQzC0DnH/ZluKG\nlQu4BEMiQZpzAf6Ctg01cbuFOx9ZJlV9SQVOt2LtsaxaejPLRRq35SRUoZmqeZvHk6kZnx2JVutr\nb8tHbXcf4jY/xYvfYEFX4HOSvaOWoKQZp62bHLvvIaZSQc8zzZD0dz8sUqUONgaVEppfuM/WMImq\ngwMnGFhZ0DpjWeDdPEdOvxllLjNCBrJoMXk0NoZQ6FGekTHCdpuNxIKZDK8PDSuh3pH4Udn7UHg+\nkCip0T+gk4au+y1JHVcNdnx4ZrQgCc/aEC2T/UxqPRVw30xYhPl9qUGdlYHqX86Nb5nBWaGQOpy2\nFkj66xmYSqUYZThyAMQWkV7q/K1NcRHF9iD3PB4KbAvRJMbfPXRsVwK1sSP7R5nQdxg+YTaUgLKH\nDnbPx89r3MBelsRGrWQJeEa5pk3C9bDfMcDWdA3j6rTLjl8ZtTsrkn+mjWhO/C3F3s6rMY0Q6Rn+\nGUA05HEwcQ+1b3I/p4fhvDdm23QzQyRXUY5EtnP1HeP5gBk/e1C/pGOr2xgZ1Gt5FcbFfx5pvFJ/\nnG1+MqwEwLebNnBzfAgF/bwPd6KiVEFV7PU93PgbX0q8GDHMCYW2pi10p4JVorjoZIwsHTSbH7/h\n0RWSB10CY8WdocmknRsCcU10+X4Epi6ym499noha9lvBByhG+opGOQ9HqG6t/Nw31Y7U4uNj2rN9\nf7556Lp1BLOQWsAVDjQDMgRAKMpP0lfriq2XYSglbcrNybGw0AEXMX6CsFcW8H9NPxXpBk3Grt85\n+m19BUp6TYd/OSiSHyDJee3n0PlTXidCCSqKWx4eIo/SdI0d8MZrW+5914zUD/oLyNPK+gmxbd8d\nmQU2UsCClOF3pUxgccR7Dr0Ux5C6UlZBHhoIRS2aDhZRobZFqzrUhmSxSHr5vamn4txkY9JdG0PH\nntWgNn6Eih5VFDXV5NS/w2Ogc0JDHow08+Dpgy73juN2rBZhn9PVf2oVCw8uV0Wz3NN3GwV21Iuh\nzbdb5gaBvL1+lOE63dPPnCnql8P6/E/RjCAAv0pCb09svITM5W623E7wVXV35pVGDycKtO0rANJC\nQViv0aGls9jehkvD+pNfUKog5rxHFMRxGgeUB3fAI7Ml1jLS6hzuKKqBl9H5kI02FSk0Eqx3sxWO\n35z479p6mI1+CeKNkM6R5jdFKLVcux2jWoWB2T5Ze63CdwAGjTs3QrXiYTcYkJONdHNe/fgs0VGg\n4zzkv7AXoIsHn8K5HqyqoW1X/r/x3Ql1Bc6mXkOmRkfa8iEXsTgSOST82UU4r4lfHCjjCLSi6Sul\nw8E/Aj8Si/TOh2y4xv8OmJmuKbQ0YxIcbZU5UTZyvwtJ8GapX2+DoPhmVfJNjPYFFH5PQvehmwmT\ndgx4rhZxHqkrYO0lOKg1gMR/24M0cGkpIyzMExAGK26SRm2HjKlpXOdwCbft4y3wtruYsLHuNDpv\nrhHUu1Akv93ikJ7v/ghFHVTdo9XGJZVxl+pFQmrNu8vD8mG8C3OQ2TlAVpeqAgCCRYX+Ly35K0a3\nhNoGqO3Ul/DkyXYbdwbctWpTC8zn9EBzNxxwtkLhS7psDn+TWfDlpP7Z2XYi4NVSBxVGgapS8yzY\neSP6L7TD5HKcQnLW3CBtWk4riZzf3thpYF7RXIs2t8iL53IdB2YkikGsMu/BnvPFFJHPF1XzpTf1\n1GAEUNn4rbgp+h9xj0odIY1m7DYoKAwduAZ53fF5TtaY1gklZfRtZdP0qJISM16uWVx0VPaicdJt\n8l9pE5rmK6VJV5bfkzz+2LeNjen2iJLIdYR/EH8nmjzGQin/GKIGlG0XfNknxNRKkiyE6KML0hNL\nRIyzOK34XYuE4ymmnZzgzmS4uNCtg/oB4rw4ZQ9Y06fY6x/M+Aix7Z58rE+icVHft8BMDmNIOKC8\nfkTIA9WfdK8QoPSfZ9P5RQrGQ5YW0d1wRWKqNIYvor5aE0MFS5N5p8rbzdGtjMIOspT1wd8gmJgx\nv6NLOSdPV6P228cpNZ9cnGr+8M7EerdjD8xUTBZO2e897RQUC04/6LIJGqfBFKWsgDGv3kUXOQ+t\n5WOI0tbmSVFDavJJmzz61GPMnT3MKugw6r2yqhX2Sv2A2P6cEsDq3MmgrbdWs4cvzQsPMclNmgA9\n26joYmlJsUz0ID14LLYezi35HMN/8znhYLYkk+iO1Mxt+En78EKuPjQA+XRu64aKTT5CeK+icB4G\nRDq5D4mWKRODlLhEcR4vJWer47kF7ZxiOPFc4h5TvQJwX8bV9+ttvSgdTDv6+7BoqmYGNDM0KrbV\norA4ymoZH2IqZevYvXn6gs1t83upmYS9E5W553qp+pVav6PxGbW4E2DNmFtfbK22PZjn+NOfdOnC\nZRnmbp0KjISOxN1DplSkpppMGGLEvHhS+99+xay1wpK4NXbskGhIBKAGDPQ1M4/JnLB2CLHZfV16\nmYQjktluxwp/AyDDJRPX83Z0DnyMATsm/SpFNKnhxuVcsUbnW0OPH15IYca/VfEJ9ZyQUJv5hS5u\nbua0je7G1Hk2mbj2g6L8ZxialXajFTc5kaTCPPOfUCYGlJd5UCXUSvSmZS7UCzs5qMiMNUzQiWfy\nN4N8YDSPh6mPXPDPwPeSihf59jWss9LgWf0b+r88XS5VsNtxbMWFnfrP2SFOStSXfMK2MSP3KA4p\n9vOyrwrXCe37G+PfSql2gEI5vis13IlRhYKXzyk4Nf9zHg/l5vWsR50JJ1ddhKx0YeL8cbiAv1AT\nlzqGBgZAOkMinsVyO8qDWgByqaptxT2sPOBxUaXx1ZoH6h5A3bjlHG0iM16TAZ1BK09X2pDRiQXP\nEeUGB/kTxxLiyBK3BciO5EwCvaTfsVBowIZyizCoXrKOrNeGzAg/E3tOfvwHDk37f535YZvsMI8F\nwsqHEHicB82TcoXVK0yya49sKe0nkMmLcxa92nKzKrkeVuE02y1f27G8gYA2JKmh34DFLfoAf42c\nFiidrnPcZcHRaiTwb7P0kRZqbZFb0V8OB9iDZV9qQq47ZGq+OY541WpW48zGqvLEAjH5req9LE8J\nt5VJU9g7kzgFlQVS7vH0yKnN6X+gZ/qqVtxLYJl6KtWDQw56F3VSxSnP6BXG5FtOsWc54oVxmYJg\n3dez6qaAnUYYagtXbljgpL06Z5uRChLxCUJc6O2wbS1wxckRA6wlVAPpxalEACteY2ao5goDytN4\nb79hN2WqDvnzQFBvMuZzYZcm/ZMNPXzhEnTWHsD1mqxhemlFhPGocUPxViD0lvgbYusbzoT7Ze9i\nmkasjH7XeUfF4Ov3bAvYlZx2nWoqBXhBHEiR+g0UyegKKyevU19Iw1Iu+2D/7Rmb51mkq6TRezIW\nlmmvYvKf3I/BCjmHxYqsb1fyjUK6p9PgNq/QjqQO25SxCLdV3eKzUCT7txEVJs7W9dJ616IFYBXQ\nWDNaViIKApw73K+44BusnPAYR1vhQEHO3MUjzrGVC+LyRDlR2UxkRbZgVxu7CMBVMJwUy9SMxYNW\nIodQH21No8Hx7ClUbssGWqFfF295RYSe2vKz+QXyC0jV6SrsytjJ/acQyYpkx6KSSendqYJdo1d2\n1QWP6k/nCG3Ot+ON23JWRGrFn7ucT31h8faPpSCebSMDmXJDnTEQDjpvaj6QD7Yu/51JkmHCN4F1\nrE/n7gHwgH31Z1giQVUKZwKRPxPTksPdzyCgJGXSA4aI8uXuOhBfN+xZr3tTwvSLCYLRWtQSn+x3\nCl1pvQ6nTXTBgxz79p7m8c40xp7aSa3b0hhfn+Gl8xdW4pcgL0loYtU1le2clNuGgmPG179i2/uu\nClQMjD4GD6BcbDzDFN/XpL1dZYglqIbXIawigcKxcFBYDTmsRXJEFTRn6SXwjrYFNLgfC/yUdNkU\nEYEtBi/0eKX3Wa8Lh9XHiXDmlQd7wsWBEiSYEEkjTTNzhon7XJN6AAY43NjalbBLcqmX5l1i/8b5\n1w+e5bzSmX0WHcyWCoThx7WABeHWdLytMuWx/fvk0uGexf1ytVbX9XaF3vziR0SYJ0QUSF7jYoUC\npqmOwDSKrcR995m9qI2IAuYp2yTCG7PvKdn4FkjrjlHuD9ycXdYWHUVR/WgZToqeinwTdeRGLCp0\nWuxVRjzkfFKvyPROUMnvRny09a25/wTETVo+crnXSjILyUWQib7habPmyEoQLS19e32CrXE3rbLW\nmoj3lJNj9vOsZDJkdcnDb7iZ0+KA8CeLMfm6G6sGBq0GFq7IcP+cwM3wzB3YrmjNQBsYzrQJMsDs\nCaaE+TlVAR3KmrEXssfPInpTbu70ZuWlwYbPGSa5utwno+AOs891LYQKTAKwcpio20sbSEnXknOA\nihNc/KO6b2ODy8dHQYe2tWc3+jmqozOQsNHtNTRd+vAt+2Nh7Q6+C1vTppWc02x703ZDLaYZiWd+\nku3ASFwZm+YG3ac0DnYfXoAVojQ00ZeY/QHoBaEJFYnVEuoergfIF/vA+2AYa9g66cZZ0uF7ITfp\nNDFK/Rq90btOenrD4sP7dYLLMFOonJlC7hAkJF9bviXGYR4w95entPxMv+oPFhKr/83KezLPclOO\na9drF25tp+Y2LRZwB4owHe3DFce+DT8VZbySR+mqQqShnb7WtuAyRLahPs6DDEEQmS8EK8jyPSXb\n8YOSBnxG7XuKnw8Lv56v+NONoGQwsgDuF5jfXRuKCu/9PeSRVSWqIx6tIjsBWQON7/sMrqDUXhTU\nP/z5b3GKlIrmN9wVF32x3RLsZ0xs+PeCpcnW4neNVzSi8e54CQQEII6q8yun0SBH+mDXxdw8+jCp\nI/hiG7Z+NuoPlKjvPFqWF8yqddQQ7LmB/oQFkrAYwS7cONCc+g+9R888UG/VJjYRWROlwD/VsMkX\noBwb54pBv2OMxZVFhN9946P32mF3Gm33ssSRTTlY/TPGveeiqD1FtepBHnRIQ+XAN2eP5cd/+Rn1\n/awP0x8ME09OdUhn0XGgIksd+AziSrA1GkKiikudfGzQvqj2a1uwfOseQosoXcGOIAY4V+krSmPk\nOvZXdc4/dvSxXfv7EOe/i5sAw2LCbVgprkmeemR7K/H9kwesUv1xAyy04Ng981gTa2Pw6XgyzlR+\nWHKApQc/FJa91wXVrNLOKiLV2ttSwXtyROjDdVQx0XuxHzTJudCumppXwifst0D7pJa1KWx9iUvU\n//CF+VLQsubHA0051h4+dPLg9073kxolsyJbdjOm+kZXvKWtLN92wQ3qa4qmHE/kXtW02XKXPm+t\nDOXJIMUAp/C1tRbhCfg6hhFK4lrKvnH3jVpmKGMOi3rELj6989e9xj9HzNC0+TJ/IjS5Liw2g17l\nFOnV5xIwpUwN5tJ/cf5nzO3bmA67ENfoKBK9XHULdImTpY60ZQWh0v6dyt+zRMcMRMbBqkcxXjOh\nd2drqdtPIcshuCuIYmcAI+ODGXCFtC+tjb+q2EE7wlCZiaaDYdgVibg5yenqh5ZR7BlG8+dnaZtd\nVVqTIdwYYFgSl21aEa0TIEX7TEA5xN4H7Bma9vYgAHiOS/YacTwQklxMDXN0FXGSK44neOurRYmJ\nlexE8qaugJ4Qo/MbKfF85yXvxrKo5cmFcI73AiJm+04vQkS//MNZgqJaCj18foDt5A131OSCS+yP\ns+vMgqKRoTQXCguDOCbv7oOD5AL6YcJRTZqLSTZ2Ep7t3hxYs5wtOf5II9zef7NtL2AU8566AwcN\nBv1X5NmA+QBq6A8+AaNuk3Sk+eWNYR4r6FJbLmj7dEPVZAJFLN5Ldrsx+FDDTwgnGpIE4vgeZBrl\ndDDZ/OZ1tIflMukpwYpuLm95chxPPMgHhcr2TY0T44peWcWCX9mf/oHfU0EIaQ1trQTpWZ9UgOgv\nJ+BqUh2kD/ZY8xY3ZxtRl5cUS+d/BQ/dGNcHVXfWGpblRGcHuDXQUSgQIQ5fs96PCpEWeQrBEqce\n835ejJOjwckfqKguukrarnK9MQTALwzxwrF7qSEJOdL2Kd6E1Sj25F2frPDw775D4TTf+QnkzkB8\nuwLul0inUosRQWaapvR1jQJOzvysUAvfCRA9dgbKem2n2Ji7r9ZbpYkt5b9BoIDb6VrY9FuhpnFG\n+N7rkUrR/VFKVZmWTzc5BewyXbTa+SblY7FtvUZ7iH9BvCq8nY+IxjG3WGx/Vndxy1dMnFBeIhHs\nfpRufL4fC+GfMvJBxJxoEyfbGW5BtFbo+uqfUq64kNUw4oVli8A5tLaYd9y3/LdfbZn1zL1kixuX\nJsBhRYwWgGKxpbo88x+3FaGovmRLQ0uiAvf+lzDVuI17RFLwvbgS4MeNpGqr0iK43vohOKiALC7a\nmiUGzxMP9+r5XbhAx9Nah3riZW2wpLIp2GPuOBy2GtwBbNKd0w1BN8jfH6p50YdFZfksroMqArR8\nd2b/qG8VwPyVt1gfdDrNtiGzZo/oexOiCXWDx42LQ6OtrcjQUGL7Eyh6DV7+/QEX5gFJ2McUflPl\nHbyv6Rf4x8c5wO1QsEFWaLGTxOr6fTvfFZ+A4OZhmC2IzniHjL6OJMykDxbrGxcfumgzokHmy6Bj\ndqfZBV+yYdJaqSjRjg8TQS5xL+31qweX9jy5XPRrZjj/nPO7WCfrALdAkZCRLbM/lB3CYp7snq/u\n2FQPUJKzck84Q6brIc0yyHU7cZirWPuCCJm902jQfF1Z4eeNBniVJqMxGxD02fyvBco+zDRR7wg5\nMwKvzf9KCPLCMRDMCwvw1TZ1SLv0aWNJ9yJp2MIxp6PpsUIjg84Ne1nZTjRC667gWR8RdM1HSMvp\nR/7CjeSVYqHKN6klkOZrtYFEWmP8tS49pJMupw6rrUtfubwgMJvsVlsb7zVRcFr93LNl1H0e/645\nyXQRxWG2+4wTzpf1vlhQHumG9ELNNRScKfUtMXWH8NLo0b9JOz4DX0BYTMiPXTTSr+rVInFhH9vt\nyrLIir/KW633WHZm9HwHfVrNspsymo0wtIEabYHgDykp9IqD+mncW5WQosOpZ9c4vkofCTg+awnc\n9g9fe6dakktrevhHyNh1sB5eGeg5gfeQHNFELghRHiRSSuuaP70GqMPN6n+FgH2kSfiBn7WOfo1Z\nOg8ypRlaIWlDvEQozS+0hlB5Dt5B4dgvD3VHzllJayJgpCBBigpy4EUqYp/wW8UAINtpVtpmvxTh\nrj3DAKLlaTDm4rtplrM/QG2R2gSl3DkGIKa+oslquw9wiJUDsStTuWkX/Csqg1hF7yHpGi0gjWgp\nes0ZFOARHpaTv1eNyijqt/5kL3mS/Uyu+Xf7nqYg2sW93lU4MRunY4E3x7gVjVlnDqrH38RsgVbf\n/bAB53riBSBEVwvrIhNCLJf2YSx0dQnknNj9TrGqG7wg3siYtKyw7dITk+j1adr1yT4WF3JPMXfc\nCGCzd99DwEMf8GebDHPdamt+dEcMNraG0LlM0/vyu1DcPydE79HjWORYiwyjETFYxHgP0ieLY9/7\nbI9J0zAIV4h/SBn2tQvbZPMzROTS8cHMtYmGYIAW/DOx4F6lPzxBsQxGcsi5bomkSw3WG54ymtra\nZtfJokEersbLJNwoqItcy93giFl9IAtCELZl3/U1XZHZg9mEYTGHi+vBdcGOqdpQIlvRX9p1F2Ip\nTS+2As10HdT+ixcdc0Zilu3zsL1nC7aL+qOP83pBQo8WlmXPB7g/p+8+Whhe+6M313uinCh+X2R4\ntLcLDG5oPorL6DrBeWkOCRhppgNms0upxAws0c4vpFv1G5Yi3kS8D9QjDa9PxB7Zy5XIImLr5qPc\n+8UsRuj/sjnk1nk8FLFkVBuK8anycdHLyZlXSBldoluzkSexK2ccVW+p7pHqcaL2LdwCThrtKHPA\nTToUHml18jm/0AFR4DlPjn0Ay83jr2CjaCJg88QoYmejDgsmSwS+qrzdyenn92N8YNQwXHnOxvDI\nEX8NEjgGwejNCX+F6UDu4ooXRWCHV/db1LUmOJi3tZ6pHl5T7C3UGZrLvvGq4rqTC8dnXu7QElEl\ndXB0Jfvj1WkEZwRcfDqnNndXXvdb0+eXayHK5eaj4SRInIPnJRdtP+2MMCMg3IZRDGKyyi3qm+9q\nnUkNNue5OIeLn4DECovWjKy41O8/ssjasnXEaC8b175d2zW1YJudXn9amXWCbX9Ud/bmb6nBE4Mg\npCO8ysuApFyU/RpvYgZgCQjbJfU71XAZCVgt05sizCXay1VKVROFnEp4uljDGbKOjbHbH3gaC7I0\nRWZMB6dkGm/ZxIpiU/6RKB01qIJZr0erZoOeIK42YBb9tyTfgSvQD52iJKevHGEhXK2s8Z8x9dqV\ngbuqj/yvDnIYAOXW6DSyphyGUq3aKIziCwwukrCtLswyddA6M/CtafF8B4FN1BuIfx/+G0b6ngwm\nlBCcR9txsFqfBFL7baf7JUUA5EOboWh/ow+ujMJ8iFpfInczwga6nLqBexAosYjMKIre1kpSkuk7\nmegLJWwe2EgVBEDQ+FmrZqOwYXmJns+jqYMgk1QuPZ8jdmeZuiWEaoAqPj/BjdTnewI/MRkRQsdY\neMANESKrmSRpTRosqItt/o5xjdCDEWk8hsvMP6Bj6VQ/1SArS5QfXG+Q/Y8E1dB16ZwIFCvFp58f\nsaGN0k88w2vMwShz0YC4qI+VDEaGMPvj1ETiDId9F+Tk1HacHTQy+l8YVIKzpadWyDJUEaOHUqvc\nV/kktcLl6/A+rZacuEmYxtPG0SaB0+bzx7ulrKNeyDQpLQTxgW8cxwbZvxcx783MMKW/oQTKfMgy\naoO2bwD69EWFTjHW80RXlrGm0cI2zi5rXy1U+NuljLwFfXu458eZWWzbfGKiHRvM2eprcivaE45u\nhe9tUrWmJPNjmytP9CxzArvdMbGunwZGzfOtNt0YrijI9OLSvrDbl6x88Sqqw4GQJVKTm4/q7xh6\n8ibl/9i80mHDxOj91I3UiCwqkZg5G5zVN/4axYNihActqP41F5lLkw+hWR5kQsFBAFQHJT2SOVLa\nLUPhs1boCE42XK6Gfj/Tx2j9Yd44Qx+XdDEVSyZWuxsFSH1i8yN1NUw4ChRYkNerHAZBEqCnNdYK\nw32X9be7UtGPqWm+3kydmuOe71OrhlKu2HeBilBviVP0AYa/zkoUuFj3s8Hgt6bSKoet6LloUUgJ\nqI8wIbgurQBUaNaxNnZ6GxVO9KTx4uKjRMmSU2XP0Twz4ImN3C6y+UBZG4qhw9TRUwf76N31aXXX\nez8PQ3sgpQkm/gt0naEV3+9SFysH1BRKSrz+TOIbPy2QJV7qnWWK5k2FNjHhbbtb+AleTOtfBoLe\nEc51YElVxUKld/cOOHHazFVO/nT4EqFRiIn799Zn9pqxR1xVuX13gQXEHlVlh3GnV30FjahAXr2x\nMOWxch6dz3IBXnmtnX2n7mx1OQ4jT31f/LAhehnnyv7TpK59ZVYFQh9c8I98SXNxo7wb5b3nIqNF\nMjBSWnwLaerX6UcJ5wPGVssWMw3zOtuQjt5MxS/pTaI1S1jL6dio5/xyaY6deEFJ9UwS/nOXgjhU\n6NIeYRg1kI4nSBmdu5f8sxS7Qp/N86BSrRb18TCrGZco50Sw9wTR/ACbl/Ch93aVY2XnhtEYIFWe\nY3nQhAncBNIhNdS6reDaGsxj1G5BA0HDk9YheJUOGCxMmUG2sRwD7LpOjbl+q9LupIxRmUdvqvYD\nJKntjzxXKsvtro8LogYiYb9jU7/5yiFQpM4uCDTXQBl+n36tHKaSLrOH/W0xGbxcPK/0m/f2h/bI\nCbQ4FdopFGjDlNksSv1Y4F/TlRRs5+ychHtOC6UcY+BgwNJp2Gat9d0aT1oXlCfNnY04bSqAGmNj\n8DZTRVeCVeUzmHHqyl1m/pWKL96Gqk5EI9JtPjXn1wuNhHJ9ekiv1uy4uQ1o33Vi+ASxHhqBazSH\nFQOgKrrK465oVwU9iZk8Zpt0a8UYjBp+CDjOP5tFwWpi0nRehaSdfluPmr1s3qcre4Z1dlyuV0jf\nXfgz5hiEtEcttscDae5WKJL6W/0vYIFH2/vsm8OoD4RQPSJNN34jUFlwqzZEPLtc/ZeiJIqzUumu\nt64Yslx5F4I99PgpeRYFCw8dD3CtgpNJKeBoTpReAT7O0ob0NK+MEpspLAce7CGA4RRjowNNGMZj\nbwf+qjEbROMQm/19sdfd4eoWtFMcBEmUDcIwy3zadlH98AjuPeKJtAWtfbfzFWDM9Mcdeew5V37J\ndf1g2fkmvBh5dgTvCXMr2x0NWwFcd5imxh94VvATHfw7O39QEdBXFfPj3ffEeqTAgbel0UvfSnjU\njZftrWynlJu4kqQSU10JfnORHe4h72DiU/HtIjRMysSqF593SJ5BRQkc3ByixiPExTfE9XghBavi\nhedetJextNsM2o0MfQZ7M2NMv/CWFgI6DP1xZ2Fio8L5dpeAqYORS+WFgznPUvW4j8x9179cliRC\nH8FawTKxlGrZ/zMnEQqOo2fMkXd8byn8oV2qv/l1HDNFJXxAzGydp4ep9xXaGpaRCjqYJGv35KRC\ntxLJsY10Td+DHMNcdv6zJUtkWJdetQUQjsIqxJgUh2NTibilW7zwlph+ltuOQiZj7dhGo2NwpRxj\npRSOiTAthj8O3Oox5lTjkWsZQOJYZhsuLWdQf9lHcs0ZUsj5S9+2RM6U0rewlBsYMkgeEIO9WrvZ\nnFWjGBlhlIAI6hW6Ek754Y1NwfwcihhMlbFjezjsdA7r0d57sHy10dnyKk2dKzP4lsXx4oFswI31\nMlJeO4e+OQuXMjC2s9QtD99djW+BQN8vS2hss2jXp0RUFN2ALmqlKUlQY7F8Qk7GA8W8xEdMSRfC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CgNeDKXAqsyHlBqiikZBELrTLQziUuO2Ozlm5IjiDh2U1AcE58FeYpCUcAKk7tuudNf4kA\n+4IZMoylovZMIy1uk6gDeTs8t7ZT+qbKAYqvQHGc680oqpHHqBGMlkn6SvYbCvdeT57YiL8qgbua\nHHRqgt76f9I6m2gEbzKXyq73F1XA7iNkIQH6wvVGab9k5vFK6t3VknynPia/XwHedkmztqfsJPcL\ndpmsfLCWWjJB71zBzndOPEH4gQlmdtbPTUCG907wykBW6mbI2D6F8RXBFxLFiTe3lLlK9f6JqaKS\n6P5Urf4pShGjQxePyekutNDkOXiqBWkNmqlwZ0Mf+998Ey554Ts5BpfAZKA3iTDnLqa1WjM8MdFu\nz5cnBm2QmsWFiDw07bde4lWuor/GigLLSGoi61c1W9VUUTxsmRW3Nm9hedl/LMIi+IVd3Ie5yuhm\njFTZ6GPtxceQZ0a4n/9zmY1LfzOKboZDW8/yeLpK37K4KdBjNJqUeWPNEgbkAwu3B6nDVdpVe58R\nyE2+HOOoxDbkIulCG/2Z/niLLNiqicjDej6x19gTcxFfvW+AKN3OywTja1dzXhKcg8TxzQWMPch1\n7hIDvB5NzUnEvJPUkHECOzjp3pErBKiXve85ZxpQKaT3uOCuv48BGPUNsb4Lfbil/ZB2YfZA375g\nBWHRJSLDuy+pUEyTq8jZoZFHXN7uX9th5cbBFjtERzEP1e47KFVu+y2grd0uT/p3aA/Dnc1rAVN3\n0OUl/SCM2fRrCgXsZVeNO9TXtrL2agt1/h3Lf+NdAkcZvn9s+8p2KQQWKc+XZxkefaWM9yc/9fsX\nPY1bSFbAWYgAawdP8Rju5Hw/OWV8Sbv9vq7xEY9BvZleZMYuNtFgj/xGBc+xuvt2uXAyHW8FfkIM\n8cL8AdK9g14QyRhkyT0yYQinZHzS1u8UeYNIafkE9LsetGUZn6zTUy/AAQpdOJF5R9QumyGkPJIG\nDLlbHC3SGKKie2/q6GjryZedQrBwkwtDiAxTW0Qz0ZfWnHQKZUXchgOf2KSxyoc9cL5NvBSM6pDT\nBAvpvpDR9IQrbp1Me+korQHewv8IU/iJGQDmW9irBUgAsfKFL10de5y0FcL4nlC33hPYvgoiE8RU\n7OI7bRcSswtiJb7UhlyHXhX/Qq1xYGb13RquMH7/TEr+w0tdRTXngTK1PlKg/fw+yvbbbz84vm14\n69gZb0aJzCbyTfgznfo6NSyt+Yc89ItF7q9pqhZCgcdoPXmBq3Yy9NMPtoxsUH6kOSfBF8AAXDx9\nadNlsmO5H/J6vjfLVMwnD8RGzKg6O36A/qO8CTAXdFBWJK1mHmV7AHkQWbWjtI+29Y8Cjcm5TMCZ\nVcGqgrTLwebwYR99+75or4EP+AEvUyYflRqH7zmkV397XZfJrtGjYDfVNOaw6Fwwl0BUaCVklg+U\n5ujWXPqT+WCdWww8BHlzRx7C/fcE8QYr6jkhv8ZWaZVWeR7m0BETZyFFtYpPQbknoTrZ5yogazvW\nHlomBpRuB+kPMi3hXD9VvYxmmzlMPKDSqnD8oEc+v2HUEWT0UgCJFxQMm9iGggPf3YHN9D0jFjsl\nmgTwaen8m0tCFvDheznqa5R4IJ6bRUvo2XU9OK9xcgDzQcHU2WgdEott1qQL2QD9Xhj4zN09paCL\nT/tIIUjT3V9B5xBRw1DMZULj460qadkGntA2s4bdSew3xEhDt1THe7ANelYoDzMrlueUPA5ybCN9\nj9ihdm9lEllXxLg3gyWzGmSmuv3HEWoNkOVomnTHzZ3J3QNTFDOMQOkjTsUcMNbO06kf3AfMG0np\nYy1LjpLqweinJgeFCZihIUKgUh+mM5q83dzxHzSQOkbp4qgEnX8XTdz8z9rDrqNF5Lis+cg/r2ky\n1v5mr4jN6tquOWltmsh6mJqtbEflof2B82KIIYqy+oo3T5rJ8j7yS3pspqLojUPsoDdI63Y38pnl\n/hAd0oP2aCtDsnE/pfTIXiWPGhPniqLkuv7cBGBWXYznkXvzGpkOqxyxhWAgwn279Vl4NoWBY9nG\nP+D7yenxJFKzsvPZCtA18L/DbNpESKFNX/zlfxsNo1TD+3r7PZTSdNqrXwlbhXO/m/+5mT+w5GDX\nG0lC5guj/TIRf87wZd8GuzTYgQ1MRFizqy6t3AMudVJ2vnbE2fTM/qu7afzJMvpQ6f4Q2V05ln8/\n7q3U9uBhrpQvPrvVqap3SfhElGbEOS4idqH+lE2LwPXQ3rvBZaWDG/ZqR0WAPWNNl6uprwIj8V9F\n/nbYOcr9WtpeB5Z0NEKE1Wdxf71w7Ne79WOVGcm8UQCtaI9HHu+ky22iO7zNt7mGTopdMTplddm0\nXuIyP7Cf2kKXQqso4w68N66MJgEeKS8ICKONtQ2HfqETdm23OPCItND6bDztQXOM215iJj/463Sd\nYBeMiN1aY1cnhgrab2oVuroETi3DwUIewB0lELB61LHLjpKT1uFQeSRnVjZ44sLqvXljLc7VhQ9O\nkM67M+SRbxF7gdwjNVUCJtaTxVM6Vad93zRoRBBi48nRC4GogHXTVFX+P6PK4lESKZ3QFQVE5E2X\nZJPoqgI8udlaVeBK1CyOphB54UqTOMDo6yXhK3f1Oo0Xb7Z6EvQYSu1ZmiGlj/VxnNju6GIffPbU\noj36vPOyJjH8eHw5Lsq+wMg9hiBym/bv+XrGLRz5gPQOhulovqdHuA3VfuOkQpBXA7ZwWqE0XEHA\nHlX4GYw2s6WZRP35U8njSsTSSEzeHuQwdhGLNBLKiGCMrt1OGn5KvLQhhz3uFmvCvtO0YQgr4gRv\n/vmpo6suAL/ASzgOaEPhiVzMmPkrWYzIBE3QRLskFPR7umUQrpLgsHbonxi24nKArAZlLqvR8zG5\nMJW+VCRb5DvU/3epE0IoFGxaMXInK3yTSqfouU25pcD7UPznWiUd+Z3ZbKcsRUDqqTFSWVEIdDtj\ne1soBVA1ECD1iz6+bTpNY5Oh1fX651YQ9lvHKncJ2+dN9V+hRK0ngC8rt429CK7a2Idalpmi3JWg\nDc+d/z1QrUiknXJdMXdblP5a2mivNqIY+P9N58n+bZLVRKzRPI5fH+TaiZ5jTqJPrlNeN6D2tTa1\ngbHLS1Bq9dYuOLXi9TsbmXBgJBQwwPEWK5yG6KdPu9G2WhBizqyKJONkO+nGznTqzepavVi1EtT2\nDSy2ZlkxvRjUjhs6nkJ8oFotJICNfcBze5Rsg/eui9K9LduHWu4KMEEnfS6sgxuooXB2mSH26zwV\nij9uuzBYnF5pUMZP5ZIHwUnjANwa5J9TVpzTTsyHD+lSA1anl0ixbWrZqBWojDnzT+iwlGIxFd5a\nCr7uEUoz7+tyA+l+rF2lKvvxzfe+zdYMMBvqsNDGdYqNAW9FkmJhCLqy/xwgk+n2wVFwkP5bs5+I\n3CWz708qj0Xl3IUamaiej1IyWbCM3/65rfAs1jw/SeAXlA5GLuL0OQre+5ukvItsHTy5WCsZy25m\nIlzQgA+g35NVaLX8dpPHhdDcFPt1hGXhP7Yr6joKGvJFCTAqQSq1Ept7/OihaNf5XXI4dZlwggzW\n2O6+s9dtuhAiKtqIJ4ijww+apXGJirR6xUAhOeSg0/dL5FZGPXCUkxIV/mjEPUtP8xHtTf+8DOkY\nPWXBtnx2mGH1KZHfCfdcUVSPmQCAIA9DeWX3Q/v0IL1BHCVTaOsQ0i772YTDjXu0N/Va45Up12M2\npPcrdVHbahLP7O39ql/r6SNm08f+RwI7JPRtDX6X7V9G6+hu0iepMxsxBHk/8XaLUie4D6F8Tp66\n6wGBZoUWXHhVYxe1w2xSgRvnaXfLtyfhQlgn8KmHdgk8ibc3u4wSRbVtHfjrajovxVnePPubf0sR\nGGHlwLMSkklmrNGL+lSFGUi1thX7/vm25FpgBAf+b4KILInLLMnv3/NiX04A6G6zgU8xudOjKqA4\nQagbl+lgpX1lp/P67vogTffKrn8q3i1bhVvE/95/IJpHNxGD/YefOIJie6yvd4g4+QI0Msv2w6Cd\nidnVFRjhjKzWFPITgzw+/cK7BbMWwZa8ZVr/R0Ea4sWBVTZPvhPjDIMDuVTtZ/BIXrN3ZvcoZLIt\nuEf9nP+YPyFSF9h0+9M0/nnp9F71JHyX7jYpqOOfRpiL3Nxuokq2bunZore8JzX0eTcdJscbMtrD\nxCeKBmGQnzKQ6UiCUFkKvuf94g0f+IGcEZumf//3NSJuBvPpTbwMJSm+sY9G//ySSjk7pQqkuR8b\nMd1KFK517XUMgD7SMRegkJwaEV+w81z7aG1qIch/hQCgQbYqsyjvh5nQId8PgIl3hj4GB2InI72Y\nUAhpGWuaDLA6TX7OKs162hqSHhiyjirChFnxXjvJ+txbFF2Fcvd8Lle4qgP9HzwonfxA4tbzBytC\nLJ8EbIpgGoQE0uuPrT7LQg5Ul5yacTYpsvgQiEs6/+lSlLDAjEpcyOT1BIsadKqhJF6LUpao/Yqd\n8nYhQPOfQ9M4yxojCmXWRMhypMMDagM5T9sv6qzL6qgJ4635y7SHWV5n1z+x2GMB2W7SBYChf9Cg\naynz2TV6w7UesU0HBZfyRI8NLkyMS7ihpqyH1jAn2v1bX9SC3mKHK1xiPPb7MyxWS2sPaIZTX3dn\nLSFpuj14rJiJBIzNUKOQfgxBQxFfjiC+nqamVkFll9Me0K3Pzx4nWb15saHV2Agy2l4DayCQQSf/\ngFu+g2qlmJp4rljeZnvFcfEJsOYyCCSq72bieaiG+5CDM8FK4XKb+yzUHKzInHArOoYBwfcoqN49\nPkjVl2JDlQyLuLK8pcfOC8FrGunZkBIccptg7+MMvM6q5pSPMdCQzLJdSw9VJocDG6zh3Z5jUJwH\nJq6pFgVUxL4mHQb/BSlbgvs7NHbdBWKz8rrRA4eVc1kv0JgHRrOMv+3zEIoIiDWuTT3t+yN96Iyu\npS+PKCweGUCAk35o3tdplD/UZzdXhXqDMyDWXStqKnsQIolGFL1H7y7QpISzFxs688S5FmO1T2+D\nM5ktv/9S3iEiq/1qs2t/zEaENLUrc7DR/jifXMCRgj63g3PpLxVEDTtL/3O4f3ScoHrkebcb9I7i\nNaMRY216C8UOoH2/Ce4vGbBnHlqnvcEceN9HJrjnPVfBNQgn3cqClEzhriztssglsio529EdYhvp\nAI3zSbuJdREq0mii65Ch+MFopk7xMl0FkZtWXazGh5EG8XUCqTTwL68iZQBJNXNwpWsMwOjvvVMZ\ncvUCwskXIgeBTeVeZn9bFKUZ2F3GnOTZ5jC7ctowLND5yXfbzx9O0liZCTrjtu53iTdFHajEz/b4\nl8p2KTpbmC2CvZInR7lx9ZYk2MP7OjxSovdxxXIwpgMYWg1YKAiEIew1eILGHH9xYot4oEMFno35\nqX/JcF2ps8iJNJ5XQ1YzV7SduBeTCx/Yb2d4VHhNd6lfGJ/VPyBamni0Pp9q2Dj928OQezu1XIGJ\nvaLVosBVp1vLOs0cqntR2L8Ok3H6FZqtFm8mugOIB7ULCucN5ryxyJlP6Mrpe7ya1q8lqOGtAwth\nG/Dy3taw/Yy5HG6TB2aoRw2kQ4Btsq5j++25XkrGXxx5TvMK5qSWyxOU2HSAXZZI0Cn+jichK5fs\nZG/1nqyorqf8a3ei98nqpjNgoHVp13lYVrpLCWjOaECv0Opzj1i6EBPMbhdUBAh9TkIuZZlMVuR3\nRh3hDvelRcMCee0tJn0NB1Wo0yrT1Hnz8diHo+bDuao4G00VU82hBM5EkCU6X58wSPK5Y39d0nUO\nHn4Exdiza1nnBgC5bhX9sWMeuT1jWxW1lo98Wgg9WCuJU11VR+TlEeM+FKOVQRTr1Pz+sZNQxv7G\n5d93rqlCR8T4JnKkrFpEu0vUDzqHKU9hKuIJpFddQkwSB2xvH1Ts23XKgRXCs0PBmPhGZ9fSHQke\n6HQRh6E/R+JlmU00vuzxXNYgXqd9Ima7gLVPBiuGcv2c6w8sz9lOe0reW1OoxgvI4MANQ1k5Qp3c\n8cIsxgheBdrhp5iBVRipALi64MIShWbP5ZPoC0/pKzYVhS1qbqeAYfngLEsaGyl1GbQiAKOpwRlF\nIj8fVr9LS0n286kxnV9KaZo35NiXSH+DeeJHugfPaKqRPArvCi51KSMF8TRpImRrY5g12Q77sDQy\nuaSsxVmQ+gC+MrGhQk+Ferh4zGEzjSHtNC5ofHgArM1c+JvCB4xiTF9PDKwaSAZ1gS7diLNW1Bae\njLSh/zH9yp2jy6upD1uDSCyY4UH6LJchwsOuMFwcaLN+CgxYvly0DIo8bjbzFwfBkFpGByBmPOSw\nX+53dM1x29EpbpVG9DnxzhIEiTGtwhrwJbrLXT43mpBbRKdfi36hOpAPxzwxGmM2XQpL58RRNhcj\n8J3y+kVQZQrtEp/v5MaE00o051ZKzTsCgatNlb1+h7mQ/c7C4QiCOxC33qTJun7RX8BJo39ZrxTW\nYDNppnA5iD22u5ou7Y2jTNRktD7kCCFgu+pWxFz2NCOwx0LWL/xwthI4uWgbfvNB2k/63fFlHEaj\nE/lOWNFbj23yjG4E8gRNJy714aUef4Tuh7kJF8XPER30VGXe3k6uKrLNYFb/CjramGTQtoZqG1Wi\nNtwN4PiXY4YZV/V7DJw5tBEQC+OFyKd8PvCYSCZXox/xteCAfB1CGiTkBdDPfuo95ppWrd5sYro4\n+m/uYlT5oiDyS4hcdq8NZrPRJ7t3f6AEZyKJHp8ZmpqJr35SNV0Axo3GFIGOQMDxaw2HBiCFz8ay\n0cqG5lTZlQoSb2/5YRFNwgAL3XRgaPuzhiWC0+iZX4FfOSVo7pMENSc0SRR1oq9QxE68hWiSkdRE\noq2dpOWG019B4JrlXKNvrLkrMUJ5sH4zilU1RN16NshlO4pE/W+iLCp9yU3tOhdOroeDMEBV5sSX\n88rzfqWGbCdzlLwovLmF6OC4mjmrF4HPSsi+jJqVq2LoTCm4TxIAWNwNYUfKI+KzAGYV2zVKIdc3\ntv0Wqz2HF/Z+mmlP21Pxb9zNw2JAzU912iUJrv85MmEUSXlRqOnV5EpBN8dt2ng82MQtAztJzPj5\nm0wOljbovym9o2s68UWKkcVsW+u/o4fpmLEDu0/z7IJj39E2uS4Bl12w26sC0xzNue9Ykx4+XW3u\niMkZqb9QY/xdNNi+tFcPMQW/CatBNuqFXQfaUvwS0FxSHLkgwa/6tPKdt9Lby8Qc9UIlXM2UpJl/\nNhhYzC0x6EdFGNul7x37AnjCNny4Ub/Ww0R4cX8qod0lRCuYjc9/OQU4C8qBVlWUvWiqPj/h8D8f\nQhCRt8sv1r0iAYpJk3cZpgmuKHxm8jFvDjo5WIz/+22ypyGDYseC1OctClKvmM7/cVdn5VkUnqgn\nJt4FETNQvt7chlPPD1Blrf1lky8HAFkUz5s1KeXaTm0rNu7JE6XR8V3h7Czf5z1eFm5FpaVLnA6i\nl6gkI1Oy031mO6fuF+2UNE0kbZWVL/z2MovoMxd61gsIaH2gjmOgomeRnukJmCRVi68MY3kbsyx7\nAjDUjeD7TumBK+WhBzseB7EYdYrrjC0xNAbW0KTZsa8VJzao26yLPqoVlniszEUaEfmZIu4GUBZX\nvH18+FvNpADgh1KH5fdSuHDiDUnv9oODiC5mrl2wVb904J4khorffh4MJpK0Hyqb15eO2Ca0JtV4\nZjVozV4xm0JoXjRu8uL/nTLuVXTAPNoM3SVKkg1n280oUNhYvCX3i0WN5ylfMuGbNpcN9LJBddp4\n11SqFP1NXhuLwJ5bA0jOtdxqBXbHcdhaeMWFitR3fXFHOvuu8aymkbkfDY0gdRGGti7aSaKU0hMX\nHgwRHUVqc1iR4XykXmb7Q5WfcLF4ooqZtxsSikSNFHzAti/2yk0oMmHKWKyVyVjJdIxz2SwSrPSL\najb0N3knTHQ3MuD1lBFy1po5ELmLCBhy7+rf4itkuo+NQAIac6/zcKBIYoXi1zD23vt5qsgqoE+I\n0Dp90ubxmdHHTmnbPTc4+NNMjNe802tiwRX8CZpAyNkqWZ8oNywJ1SpJTAhL7vDB8KGw10MW2FXs\nnGOuoVn4I66Wj2AWJ7runJR9WAguApiSNyEhtPJ9f/zccN9yj/QteX4ipYXXTXBPY8cAUCzK+kOu\nYX4J5okSHWg7aWiQu8JL7aFCRdxLsadgw2aFgeoz9vX5B0AzCBF7usdHNbf0jEDami6RCH93J/m8\n2OgYYgL8Ej+KCoG6lvUB7OtCjCvIoCrDHKr9U6qbY5BHtKNyZWKLJBRjYgJAXT9v2Nb8RrAlBDkB\nfHRdOhwhcF7TCnh85ucoPzf9Migqgrtr8G8uA/mMezhbEr8QjgZa1i0Plo3+XCsWN7z4bcLKWxvK\nbESWGbRCbDxXRh2vLlXTlrKJrqt7Nf8FtiBJRUl6EPPL4Rba0BmI69JvljAh38P317fIDE4GOtIa\n9mBH4b3fi7i3IjZADl/THipU4HGXDKUo7LVhZ4WWooXNxMBYiHj2F9OO8d51cHckkNvwl4dDHfF0\ngX5x6HZ2Z0euPtHAxIAIvGN3a28eNgs1FbBm4Cj574vBPQ1sPztO3qkYdPps8yHnpZHu8LAKpnjX\n/Uhn45oxLvgkox1/n41E0uciB3IWvFt/eOXl1sE4Op++7BmN26/XUIdbybUof0JAEltx3flou5sP\nXd+BlU/qHvEJ+g7hhcBKwWZ3W/4Ugib2r3wlCRoKzqhT6iG+AvHfkBV08TRK6j9lSio1idWQ88JS\nTHQ+2lESdjCcCVAInngcchEjo53n+PCUerJ9L2ZC1REI8gmQnPT0XkhNUxwEg75EddN7xBVUaSIU\nDErm9gXrJvZQPsIuIkhgQk8i8CZKRfQibb7WYSuhc4dGRTCbAVa5NtFD9MSglM0bKlt17zEKpJEC\nVZllz9DiRMdzE6DzA3RxRnxsyZUYg+Rbqgy67o8VeLTv7GZ0hb168GMPVgLm2aoA+awycuS2nmIu\nBwxSU8jdhryhCanImlvv7n7OM9qDKeFnUHub7j5/vLqo0gUPKbw19DAqLrR/dBm4RiruWwkJL+Vr\nYaDpf63ayaEeAzSnD0cpQHU3ZCLJeBhnfxX0uYGMQNvJLhjZOUAZIKU+q2xLMNBK0s1Oj2SGLJIP\nB9ay9bhEDKNDG+q9tz0jk/lHWt+27PBZ2Orbru1IB6PGvcF7o4IINZ47Y61IJdvNx85lEXBrcA7B\nbbOn6CJjQB+T7JsIxok8+2GENpgNIZb6Bcgqp+lkWXRcSdm4Crhur5On6XLP3Smat8qdnIApPLs9\nbQbuEEgK4iGY0R2XON7EFDqcwpvd9HJfF0doNmYRnby4O5jr4dNWSJcrtpiL1SVKnyGhInFEfQHQ\n+DXG4xim+qZiObzxjxlE91J3P7ns/Z4agRzKnj4Bs8sCFphJUAtf1b8M6ki8+wqxmoorOBQ0TSW2\nfic1JdtlBxtJjj96bMWtzNWxqmdMErlwhYYmgLITsu2NM4iCAfcGKBZf5/2QJAc6KpuJ0YXmAr9P\nQDh8+p7+bfBMOizKNKsdDJpQoKd+BK2c70R8IalyjokLs1SjxebWlA3xdmVEjTqbNeiC6czWFnc8\nMh7lwb3BOc6Ndlx0fLvO1LygzG94HCJEuodp4BDA/XekIbw6e2jXryvJZNncxNOdSAp7NhXD0MTq\nL+eYms7r3dzLqPnTIoOapuMLt9z6pTGSFu4prxt3KfZEY/tg5m2xYjs5S3UTESqK8EGQ4Uh7mj2C\nmeTpL+NnPHN9D6Tcwlf2wKcwzEIoPFOH+KRGp7qU47u00mHtM1w0CJBaprBpNYslLWtgr73bM+TI\netuwVX9xMdE1iIPLtqDKqToNmwqLbTqYbDF7AhnuGCclTOQO7rKzXkiuu2cgkNXs9MDcgBERnrlp\noSmH+1XF5zy5EgDY/aj6bc5p8COX9j8fILa9GWyrAzi1rYG+qiFjYiaUKLyhPeYAdWWmMyh4i84B\nbKvDE01pJCRGteMwcLryJl1FlmrVWZXeKcC8QAzchBBp/Jf37YDds+XbqrZ1m5Ume42Oz+OwaVx9\nQEp0d3b8U+2JSWf7DEIHq8A4CPn0Yz0MR+6IFckEv3n37qebhFORndRzGMZYLwBPz5F+lDjhD1nN\nOBG8YI5McpkZKsODGLCYC3wWWtO9//k/syJXo3iJiTHAkaY3Pk5xdKwb9VUpZc9922a2AA284kJS\nc/w6K1tp0gLU0Mpr0z6sOE2lMiA9auYS/Ut9xt9km5TLfRwtApCrVpLkRpuATTyDkPyjw0zHlluA\nDR8qhNAd0dv12ExG7HMW9hu1wx2tg7gT6DB7czWMjfl0oWfOni5ihNtwEk6CQZd28NjZhRLPtWUH\n+FSLzUGO6SUc7y0gXgUKHWWu6ZLCJjuzVlela+dOL72QeEaZr9W2zZsVyJuHyVD52aVnwTT3AOFK\nn35NMxcXw8wKd2P5UJy7K9ud/l3TB787S29ZjoA3P2PfHD3O3ogtqpAvHFKHvQH6FCjFAhfTNKsk\nHErVZ+LMGHXIHVT6Z+l/KcDRafI2MULITYDczj4T/XSoW77h0fPEHYqOvITz9/+t1jS4SF/xhMpy\nCJ+vM1OJD717OQYw3I8AuWVAKbEFDmdfhO2gYi1hMuJLe7msDDDJmugXMUoF9mrZsfZexfV9i3oi\n23Wes31mp6gUDeJmUnRxu8vnEXLXkiWl/9u8IHC7E2XwWrRrQjWJ0kfamR8dvKkDDNULew+4K2sT\n56U8REcr3Q7WZl30N9S69uRhCs6IfmjziRSl+vlcdn4FfriLuiXy7muqlQV0Clg60PupqJcebXH6\nBUv3N+vgcEBJNag9MeJroiptA5SBkyIwauhthJkNyG9cjMvY+Y0bNjtsLtZs343tIffMIGKFux57\ntQPtlA+1zsQMMx1GkhXVLeWNpNUusFkTpgwJDoQLEOEi8Zp614efkCcYVhmJGzjWSCqabm/Gw1Nj\nJ4Ik0tMKnueBJdhaSEWWsyIg7gzCo6ojbJ/1WK3XZUo8cSbAmj3NpQ8f3K6RGgsE+d42pR/T303c\n/Z3Uhu2BKb+FQ6s9dIHtFotmPfqktj7KhthqO8zqlyNKxItDaisn3SMELHmsayGM/owrpF7nv40K\ne3ed0W7e4bQB4884HK+HliaLERfHqfd6sojXuwMehsBRnJoO8m8q7ahZ6s1LsWkB+Zksnu71S2zV\nHiUZFid7GiuHHiBUQ7Qd/vPMsMJp5bVtz9D4AP3I3dU61RrSKIdqL+KD0OMmiKLD1s9vfq/Lggi8\nyDYOXnEaPvoLPpgMT75wyaLD6A0hux7nQa5XkbPzjFu1KSD8ZwP3SxVWbxj4j/8Tzh4FywINBztF\nn2rzHSaTZJ//RC8teqLSj6JWF8TEBft6NrAKWOnkEeiJ1bjapFbu+Xyc0moJisEfKi0XSUhqo0ZJ\nvo+Nkd9+TnyKNuD7VUbg4gMLsUjs7mfxUIZOcoNkcwrH0C/4n6c2WEoFq4cd7OfYh/pSCxWV4n3x\nxbmPFKTRbHeiuvL8dbAskiR1ebL4RRpvWaeM+4p55Hnr3ivCoL+t3xpR0JDvaq6dyUHXNbah57hJ\nhOWl8WUzGzQ3liqx1NFx5loduc/et/E44cmgxsaUGPrg9EcyCZ3LnhBMH7HJyYsqKWSnevkH3XS0\ndlQkPwd9HJJ6GwvDI5twDfDft49yqpn1LCdAWzFgtEquhfGIISyZRrOYzqkfKkXNSoavO7FzqJ5u\nPXRF4tJdvSlIrbdeRCN/Ru3p5rSBg0ipHtF+YdGXE++Vo0KAvLwFCBynpEUwYwLmFI6ab/wmzDEt\nPfJGznXMlE77hq2SQW8HU0lyYvPYMGpxZxfiyPJaal63xXG4+I5HTlYhvbYcEtXEwlFDuFMuGhzR\ncryuABzlVKTwMFcuBnLV1j4SaflPSwDiIrvcgc59ZFXh1InS6sDvwvBNCyqeuySJLzlUVZ6wuFcI\nrvDc/zMvFRimVCFvYsAlNyuXRDoaH6xbrVJ3rp3Kn2O1IXDh1yB/RKT/G+2HcP5rvHJL3ELRbZuJ\nieInGchMdkenMJGUy1maicvl8bwhYOb6T7q++1RqjyDOc6kG+bGxCEwGjwsHMylLReYe7fA/tld7\nZlOvMXTPD8Wr+YnIJQbNBu3wT0m06a3nMCX0Tf8mPMOQeujDiCxxBKUNU1Z4gUkdM956Frg/AqGE\nK1yAtEJgrP+R7Z4492iBt89YoCfexnBVxaWIsHhy5oy0Gbec+N1pXPvIGK4yaaLUKLn39KYX9oT/\n2kRr5m+fbiSVE6RvSRlihIvzTM0ELxW661/yQWQ3SEB3IV98hF+50e6Qofx7DMLs4a3pNNPMBuGL\nD5lgohDSC8CNH4nLId9yG7gsqxXylVWLKrFltKhvWIIe3Uhb8JG/qQ3posjDegfujtrmpc2W7H7s\n/FvHykVCTUfdYwybgi6uam7nskMH0JWOGeQi/ReIQgbyqGEJ0skd5h+AUDHmwcIYx1j0JtWGV0A0\nmb646def0eNaz5NXkKFscfG/zjwX5yi8+knp6y1K5DqQ5gSM7PFvWO3gc6BzW3QOKRZhwHI1FAaM\n+HHPxvSNMHyntRLaEXef+qV3vRUoAgVTQpadvT8Er6GaRMyVtoPUBLaJ0l+r9Ab+DDx4oAJBQdAy\nhSmfEmWKxdh4jCVEvLIg9RKw/nMZ3g17ElSkyV8JmptZ64i3nwISnFKTqAdaEwoCIDxWLYgXRH7B\nmkzrk8wzEG3zU6gr3RRW3zcpdTqWXJhVVzF20I1vgVqvlb2OMs/D7r+JqyCs71YVHigTOhc5oAdq\nmB/cZ1HOdX0H/45grCiX/WF2SxeJFBUjBzLF+vzOpruChX4Z29SXujo5mumzxkGUkz7ODmqPVbvC\n/qs/p+SVyywnPtg+ST+2NfP6Qm/GvOpc8DTE0mxKNlsTsE2Zo/Q1esOj6yRa8GAagmaAlfvxdIr2\nqQ9GRxzMW6WmYX4OtS7LZcUTygKZ66tKmEmiDT4ysvYlpXwj8Z/+7P8/gKISQYgRttmULOT71oQX\nRIUxl8biceYAQqmhuFWA7+c814MC6h/TQDmQFXE+5lRQlFFNLJeTOxxA7v0x8aDRxs+dw+Ws4CJn\nnF7tPsB7rCl7FNdzKPRG5Inlc8b76YKnLHN8PmDIMofpVmGH3vxbUJPmvoa/Gp1iSAyeqyO6DPMn\nOBEifX39xJdcDRc2HCFkh/OhEXGomdtpu6jtlaldzyxjjq01Hl/LKo7Vo6FklHLsOoo91ViQYEDT\n3jMHPVxSWXXHW5tgH/Ur7RTFxAUGJYfsw5ZHWqXl7hi7MBszl5Q4Zgmw0BwZZbrjBYrMT9ih+TJG\nCIa45gtEJLuoelht5168UiFEo8HXwEak1mCn0NqAnOG07YO0yiFxOR3N5XjH66iljxcI0/oM11ja\nM3jpJT7sIjDAPnJ8HpEkp0YHyPFnokJuWDEvv7j+tcQ85BcAWasVgN2xwJ8c3kOevuPpg3LLjegb\nwedODw9VxVyFUytIpddFyi+Ek3Ef/Q4EszVXZ7wSrZdqVFjVI+PEMaOw3lVur0LxFWsyTaf+WtVp\noCkznzxdoBsTSh1m2znlZ8iufzwiVZ+2k2zaKw8CGe1kw1Iuhi7V5LCdWRDup+eGBrG/MzqR97hh\nFj1+K6JVm8AdT5y3K/iCHnHdmkrAJe7LAjTKAVM2Ckd7mP7mFisLqir41jGxjs12Roi28k6szUau\nbxE4s4wOUxEE+PdrvL4sCjamvasmS24xaw2+sy3UAJ2/HTHf7Yg2SnRGvXrOx/Y3cHbhGP+aDgEb\nKktD+hEx5ivKUWMjX0ekgNUtkg8rP6tFM1HT5rnQe4RKQs13OgvkBF3dWaXWzCRx+xYycevTNusq\nzV/PH1N3W2ZPjrNNtNqwzM5yWOftRUiKNzr2HNyW2KeceGx8l0O4hG2A5kUOSsT2g3GUHVLNl5NG\nNXshenvVTyNS1iwSJzE1mXaMxcWI8xX2ZFXCTTsSKPD3z+Vdgaema+3tVmX9SsUAG+55jgwM3MZn\nntgcXr8wwDDm9/62v4asp+IvfpDb87r7YPj3AwI5u1Q2vWBBPaGRYLUe1YL+KjVMZkTz7yC14/kg\nKUcmXoJMX6E0hYYJbvsr/GxHEmoe0yXgyplmD8z8VHHRqULysYtJX+BomMvdqMSiXMrC1ftqP6Xf\n5lJLt3R1NupQCDd2yg1r0GVoif5x1Cg4O6/MztO0ot4PH13EP+8JhVoVyIzvLTsaG3LpYiI/E04w\ntvtok0m6B1GB1IKYOdn5UhTnnOeDSF8yqSsJdT5+W2nf0Mw4/nPefv5Fi3tEWiKG6MzYu5gAKqyX\nYsM94IBtU4+PjmNVbFDMQqspJboqD93At71pujtI9Yyr4NGe2U7LWqH5DJFqSuDwmUOpkT9NtzIX\n6Ykdg9VGhqU0BpnhvO9mlizoE4kkFRju4BfRyAmukFgTSb32zFRJsA0LLfSyOVbAZk4QIQYIBNOK\n1itbIDXymGcwdFMDHIxFkuj4VBJ6Mquw0sDqF7vVqSSqeARjBK8VEv4fJhammre0ZyavBbU737X5\nUfQ7aLfv/6SCeMYcZYfIVI7uxuSh2yqrF3veYKZiiNavx8Ve7Y8xap/jMfza9JtAtLOt6vgnUjK2\nY0tIRKdGEigJRkc3RXVQgavCbuILff4hg3SLaZVnBhGWAWV2CBTT/gWgjyw/DI0QBukw2P0qTy4v\n0eO8+qeDpwkbzPkDEvV6wrlJwA+bxlDBBxmCgkD6jX3Wl3LXyRqU8D1AYPbJk8/Ai7kKu1dHAi5H\nvZZ1NNIHI4dRuS3IlHtfzaYGr/2+JmvsjNrtVA3Rtq1x9MsHAwTIOE6+2RYZJY/qKW/AhkByIA2q\nzSh1zpWYmq77b6nx/aONic35PMRSW2JCMY+T5HLVhjQqh7tW5eSGPem7IlKhn9sJgRafYJhjbHjC\nkENxS2TGESqOUIw/w5o3d6DnInjBwcCnoF5tM7l0/rhqkxV1NH4tnNEyw1Ga8uaXKvHynOVE6lKT\nsMPfCAlPSfWGZy+Fx8ztjrXqQBm2eIWzC1+5ctxF8z2ITBViDt6othitax+2/VuHm5nRlwdzHjzQ\nshIj1OgtYd2GkFvojf5/hG79QUoRnxDCmRksNc51B9l2OiMNEntpIzx+oPfke9ZOIK0ixFNJU8BO\nt2dd50MFHemU1q+yhgyeJLhcJk4NSlqx6qm4CDxjG+6WFkPQPPX+Xw1HshenS4V4k2yyFz0nzU6i\ntLO75/btg2GsAQMENk4e3YRZ8Nb/EBQo2cOba80ASIzOzxpVXq8pPqJX/hSMy/djXARzfibMu4Hn\n8m7Iu1/RBZf/X/W7tjv2NcyIWgMy8q0FsJN/i9YtagiuR1ZohjiKb0xkZwkfeVJmUXuCiyB+nubx\nwaT1LAYKlobs+U4ROsQNwY14dQKQ379GafZR1NtJfj5NMMXRZl6TOFaZBsxe9Kbh3Do3udKVzs2D\ni32A4mW8HUwROMXLUXpyMzn9X0rXvM7Ef9Ld0xY61wew9Rrxwei8YVlJgaXytu1d0ZPkJZR23Xvw\ny9Iw/ZIWOgvvmnzyitpH+oJ7hjltq4AF3QBBQI6Of5yvm2EwRCGqLxspPgxuO6U2+3yltWBjfnn1\npXTYyTSBLHdoWoP2orkWjwFfKgBMnimJMfhp6BsdcCa+1oQncshZZk5HtNvUHFcaTcBEG/1PE3yv\nFwH2oCdQ7DNsD8ITEoKwUUZXaZcDvEYju4c3FpKZMpUImMJBTjgTLhAJkoh2ZalfJHLf3IbNLmCt\nuDQhwJni81iJA3bKwWcauwNnhTTTkGz0BJnx8pgM/ttQKz1J+s4zap3Nji/DMKWT4bP4GCYt2zD6\nyIY8h9iyhL3bgmYfmFAJ5z6FgbJcWiN5//p95xzkoKaAmWq8bB/qHQKFcPEN3qsWcFmZg2v+lUql\n5c4sT5GQBsZOIaN6hLXcbuBPNUskEmv6opS2zLWsq8n0CAbB8kzlR853B73iImgYV2YeP69BCO8T\nHtlm57drDF7XvirIQTInsyLhQ49a5O3WPn2NYe9pK6sYyiclFE3efqqAs9oCOgmNf49Rk3erhrHm\nXoGcLrwaPpjYfKiDo2jw2BFgabsKfzj8dliDIyS0e+rrT60k/ZntazsdMOPTx8kzLROY0LUXtMu6\ntlXdWX5uxiDe3mk+UlYVmTu56F2SvQ47HAFj4BWEZ4q9MGTKtmt4BIOr3uongvsWnzQRp14uF/yQ\nsEIDOmaaIMg/W4x9FyttQNgQaFRJ8b9B08otcQLH2oZ9wqjZoF5mkuQx8AG4UbTOVvfe2yj3/kOC\nVK/OfyaiJLTL4Bk2StaF6VB6dz6ZE5fMRxXmPvqpGWjv7zDnNvXXpkllH+cuixrr0OmDO4I0Vm39\n23TIhJUPJt+8b+ODtseo3On3NV1tnoKcObkmRzFAQcwz8xSP2O/+Awqeou4aiU2FQL9joaZcqCMG\nafhZz37qUv3Bt446BoTiB4QGz/LOcEyXolSKV+IfDTZzJl7toGQZ7Aqg4wohPKoZuyQnfybaoCYL\noXLdIad2k18KpeEV/Qh5XI61PN6P2Zi31UWvQf73Df5yGbU6QJGOqjdDQqrEEWhF0Z3FMBQgmOLP\ntGi24v1xAMr8t3YtF6mSME9WboB+blOMgVZqx9tdaxxEMj6CAFR7QHiRldIPM9dz3FHcUjCaUN7m\nCg4aMaceWlW9RKackBQlqVfVIC3MMGKu9dJPSHa4Cs1e60hKD5QidTWc3OwxRXdPbzDOROIl9Ly3\nAnK8u8it5J2SKrFvh/AtF7RONh7hX6Yv0OMbQZEYdQRphuNG+/5joFAN0FViCo28VvzRn+U32gsz\nJFjvG7CBccUtF3/SzJTOCRmeal6KSYDWjrC8xT5nVfEN8ik8dDRdvEFlwENhEa4FI+JxEMuYzpbq\n48k4OvNbdsz9YcLSrhiMu+fpC3iC6wn0AcEsVFSewyI357cK0IH4De2iLHmwnC+kOrdMiYOkhEVc\noue7YWGmUDNCEvhGo1VDX9ov6rx/50pAF5ugzOd0600+P9OZQb61XCZNKaN2cRegZKbtthLaSwjM\n3dg8IRMt+J2u/TUzvT/0O/LcCGRtefIi37fdhEqwA8HXy5FQ3xL99QR7Pecn0mCyjEzQy/v0oa5o\n/L/fOZPvIyI+0r8gmjx84THuroakqvrOGC2y+O6RMkcrXBVv6H2yybbv8yWEWIni7nRisZ8JxteS\nxJx58CGqxX/JkjXmFoHwDXjjdv2yKlFzB5HMS7FNMmtBWwS+oSRVtglPJdMpU9u7F9BRqrtwpZK7\ngo781YZSBIV85g1zZFf4t96jZpfUkd0isrYhnPeozon4+fC7m+NFNs58DXo0NSSbORMjgVNyZIKB\nvD1MXkJULySUvu8QqvrHYlVS+TZCj5tSlt8IVcDuLnJu5sa6p6l9Ad/XlY8qzx5hHR+AxxguC+fV\nlZfw2KoXDd0ZfB2qbtbTtXTRrMbEL1xpX8rtksswuHMnGq5juDh7Cpd9nridkZPEiOauzKxsRRI7\nCVB8jfp+2vI0SjvSffxhG3T+/vmlp725nViP4B9tEdwoMtpgd81dIFSk2rpwdVVlayNE+IpqftzH\nEiB9gaK4fEd4+Fdv+177Xs9wg5T1xLxhk1rJKrnRQ/ob7E3PVHjRnZqbTn1lN4m1OE9tM1tEA2+2\nkcETTxPY8wLo3islGIiY1ixpRjeEQq105WXt3NAEOen9pxBSziJ7znplh3Bv5Jhfd4LE+DH+62Q8\nUri2paOD3ASb5LpWvWlIBO1X0c0/GE9yYkw3UT0R90UCvMSQeybhF6LpbIvS7Mj2N7UIDNktDlWg\neoIj8XOGvhC7rulio9/jhvdoMMXW/BGwffJ3bvW6F1j8ofBgnNLf/sD2+CBwmShcJnktV917PB/c\nGkwpiHYwifvb5QsxDC+USJ/6bS618fIluvgemawe96FOvHXuOeQBO+5AAQJFrv6MOETHaBLyxkZZ\nhdFiSwbWgyJC3tTQthStNYQ2Ijqcq8pTeVjc97GyA0FKJAmWDs738KR7ADaCIAkqHkAD0h1MUnR9\n+FbDRNd3OFbCyEZHJivq2ZprIyi9jlHy0wWhXcjpZQ8ol+UEjQTNjbOG3zpMQoUn113I+jr0Gc1S\nTM87ulMhgtzr3TJ7yKkiezPUaUsGLNkJulnKZEben0CeifLkqxfqUkHJ6keOY4liCtxP6/5Q4+wO\nHtduaKRT0bd1vD7Qqm81MA8B09mkDjn2wISomez3owX/JtP3v30LM4K7C7FcjQbHPR49D28EA3BC\nSofi9nkwue+1K/ld8/Bp4ztCQAyHBZlPEpXaZletvBOXNKVHythVgvrTcQbHjUFtOP+9sgM5eL9/\n9xE8khHPex2eMJlYRYEKPrB+RnCR4F3kLYhSx6no4JF1QZ244aj1NXW1NJE92tzOUv7oXvUSAjtI\n5NlBtojAsBX6hxmiiWktePYzERylLrS2omlaxpcwptQEhEMmJS5IfIZJwAgRbCUmX9p98mOqg8+w\n9ktHLbqhVXGf/VbQ55MtRysucuCbFGSbHRdwch7bzJxArfGyxSrFYvM0x/RcGuQ0IweJsY3RdyHg\nFaDJUVNOuZh7yQ10Tca8Y6CzPWA33cBrzqe+DtCn4xWfVmsJwH+RCrljc/+kmStNrPqdFIscSq8W\nz53TCfMW+/r5emiCGSivPAgEUkmqO9Yr1zvHlr4ACSLSHIij6m0KFFoY8KgTPji0vV0i9UwEVr4s\nndgKGEl6X3JoHup/pIDAlbDW9qpn9zCldTtqMDkpCIFNn5Jzz/C+aKzLPDkhkHANF6WBWgl+k9ng\nJfyDERt6EgaSw3jvDjEUGBLWY+Osf4EUumh1zolZ2WxfKIZJ+LGMlk45NeP2yNtb8eKIHUjfhDuB\nAAL78ilWKyuNeSNEneeEKkJkkrDlWGL91FhvkgJiOVKmhuk1imMe2W9Vq4nf6LmSA4Gd4x1eAQ93\n/HhGxwyqJXiSTYoajr1ECwWCZpGCDCtKnhZbEaeklNh7KnPZip/UiId4U+Ll5eG6X4anovlPAZRX\nuN+BRI3VL/HAyrXrkIeFc8Az6/0y9X31vvZlo/cVSWP3PJd5xmelp/FdD2tmUCBh3HE1kI8w4tk6\nKnk0Sl4a/xLXX41mvrJcZt7UGip9fNfOxSoshDLNQSHY0ZZWzwK2M5r2OOE7lqrYEFek3r/sw8Ig\n4bo2+VUUYk8DiEfP0Ug4bKeS+tJk0D/h8nP81R8rz5pIjiZIvTPW4qaL3xxzLNIkjNMWKnHCVA8S\nqz3F6rOVLcRxizrNh/gKRNTTobKB2QU5le5EpNTqZi3brLiIFrb6j1WgRqrKaW0w+E1Hv5dqUmAC\ndygR5dP+BcwYOAoEb0AIQ1Leig19elwk9eQqk6CHHnHoizGmpwM6wWTvuBscCYGynFSduqniI3cD\nX3Ychq+IdmsbN4Eia09nMLa9XT/fgQ2NhHqmr0hhfHAAGsCIm3EL3SIrO37rLXaM9Tj32a9sE8Sd\no131hv5Jqnl38gB2e7gywOI4s66Yj3/gijchJUOUus4vPZ014cQOnwc3d24pRu/LE+c0Gd2h7b8h\nYiLxYPzxUKLOhOcV0ng/k0dVwgwZX/qtCqLJjIPMWZoKBl9XSg7obLru+lEBnUz6UDcynE0yRAn3\nJ1oHW6CHnGACh2ZHMRkcnR+yyiJOaiTDBYoNhUjJTvuC9JF3wK3mMHo4s+QUKIeVuxN7/7EW2ExH\npSKwlBwWgU7D1glsfu2gNUr9AXa37/5Xj4crYCm4d00LBssDXNw8lTV+za2l/ga0t2pEglG7Iq0z\nV8osC9aVgapXhnBeagIeBGgY/8HedP/j5bUcRcrbCXoYqWLDJf4IwwoigyBL7TQhE1qG6V6O21dk\nbeYFLG7kIXwkr5uJTFy93OwTLh5V871nGPNaVaGP0DdMNkTmOlBt5beUabdqElBWxvILKqOr0ynf\ndBqxFbUpSHTxH7beZxZQfgNPu/M4V1A8KY7L/t+HT91HxIP5QKzr9xxkPH9LclB7bfJLIagBQPDS\nkggrpbBnJjtJUcWyEf++hLMI6rdTXlYXw2Rv098jxz8PBtS8/0WtAesiXUQ5llqkMq6BJh//cbCL\nsq0efXDLyFcJtW6TpSy5YyY7aNVkjKzLNavaN+mANVospWckzBwgT1QPt2olmFsuj7JFeK4Zj/B2\n6F4jxR30unHQ4lDf3ga/HCQSpuL4mJrfNyzlEK7F5fmH+/s8UlJGK+DM4CkXv7Q0f237spoSn0dt\n/TI2zupItZoXFpvO3flbGJYpheAA5zhlAnTD95j6twP6V+5BOzZA4RYKW471/7y+851slUNQaqXQ\nCIp9B7OxFjblSZpJV/weOapzR9GGu2WUL34MtsBCFeaQzFx2MLNzu9aSthoU/PyiFjk6Lj/wLaN5\n+zyh95016WymScCXr3F2EFVrj7LC/FwmkAEIDVDNwfPJ9mpoiZ1919PXirdGiVkPuOHPEcMapDO3\nsnb1NVvSkj2CnbbZThL0GPImnc/t3exEY5SXPx6ybzj6T94UQ27BvPByC7kBOD49wmuyviRXcl2F\nIdqUOSbxaaiH5egftzelDJOX1vzyR0YubGDtY5qv0Umxu0Omqb2Xt9TMZdYumooKtV83gZxHVpXK\n99GAZz7+qyLJ9F/AWEycCeWMqgBIE9erlLg/tn0sN6avwR2/nrSFNLc/EC+/bGOUqJNj8z7IBPGB\nfQ8zYY6PrRwjmqPZWK1+Jv0AUJSyUZhJmQcLbZ3Z+Vf4gcrML1Zn+OIEWcvmRV0uMBfgANh4GoHQ\nooR+sgjc3g+XA513j45GTEqX0J38oIjuuejri0o0s1qV3aX1ZDPVFs+iQT5SOlBgaFzniZFnVR+W\nCJMWoFnfp3lRaIAae8dptvQ+z1lb6WbF8E00LnfutS8fEYN5BAvFUShschcve0aNbO2Fd9ZwKNou\neIUdlpNR1xw2YRi6sS0bsxHkj3w9dAhof4Ive4XDr+wdEZR1dcMdReAFmPe4r9M8fAC8TcD+ziCs\ndAyyiXjiTseYpE/SqL45QNnUX8wU1SY7Wkmbj7qB2lFEudgCsl5DvKwNnwf7NPmKtQp4fUAIqbUY\nWawf6h6LleeFJFFbANP6KS4s18rl9e7q45eRXFkkz0xtSYnNtMIqRatPqfLqaYYHtQVlgdJCV+XT\nyxBrVvKWjtS9dGambh+xqG8anwDRaBsvtYTPFjz4EK96d1dxSwc0cs0RZjzQWzJQX2MZkmVDrH9b\n1IzsV9C4oh7jpnOIXc0TE6wi4z5ZmWJDp0R92M51XM+2/JLAjTcmyXbZC1ZjT0uYJasHG64Y0rh3\nsJwZADr6qIUiYINbRVOTY6U3f/Ef+mLQdp3FT/uIg8zZJ1i5GPCy+N2QtXSl6CYryLARFRB36LaG\nUyv0AzNpTVkQ87Y6bjQKXk9PD6vN5epC6J1JmAnmvqK+MlsOBAhm+9pDIdTq6WOAyNFNsuYuo8Xl\nBx3fvu1Zxq2tumbbRaA/i8EDFX/m6ykEO4mFNU3Pl8AV8tn3F3Lf7D44Kmyyml4G5sW/9BgPRbh7\nThxIO5EGz5VFq06zFacwQLo4pLhRBzWLoz+UTHQ44EPlr+3tHCGLVCTWNIge/jchsyFhcIyREanS\ncZ+zNPVhYNTHufWAbKLcDfc0yvqikPWjy3YzXgrbodebfAP/eirsaBJZu8NCQijcbn7MqRiLl6L2\nRteTEVsUyGhODDCfc8VHTiB+ghs3tvTA7+Lc+AIh3t3hNDVH/PH8akeoG7vA3ygHGO0tq0aWP7bp\nduwFCxjfG5L5NaGxRRvUuxDAMgYGInp+NK1+q4jQalIyOLj0kbP//qXFTUaZ9n7Bg7Dp0ujKcqcg\nWv9m/ambWSMtb4uOOcUJT+ifnHmxRO/bOGJGWJ2XPiFn1EtK/ZpyFaBZE9p1wmm8hONEAyILZwU0\nInke7A1LhPXZtTe9ocL6HpV3CZ1XPdIQ5s+iZvjkez1lXN8t1Z2v5BX6rJ7LgqcOR9e7MIgeqr/z\nexY5taAnpUhmG2oIWpNjxhZkKyZkhjpoJu3Fk8j7rVo8jphKtq44KyhtWEk8kL9N2jjzoT7uolgH\n+JObgjkLvRGUcdvWzfL5ag53dRhXyYZsMcON0z9wJmh52pt4CN579yQnbOpGxqSGRmxZmyhFdqeV\nl/p3Gik+8kOPQ+gyvucYfwVhItuwMC06eQ8nuLiG1OJXO76XLRQvEutgU89ZUaZERvWyx0GamYV0\n8nHuCgqCu6IcTwqlQLhrmqM9wsjF/D0T6x4EENrezJNhCMo/69srqn9pE3e5QhPeu3yH3aeqQ/Y/\npYaMArkanCFNUV7TlOHYcqWP61nPzKuVcbmxrpXHTHLQ+KObmfOe5D03iRRGxRl3Aoabr4MUXLSV\nmAWsk9JbnNnBa3oBDusnLinaCrewLFqWjnSmsB3QZGVyxEZGV5ppLDHayV5+Ojy3YVHSdq/o5rfX\nELHj6S4K1KuTvOKug2G9AO6DdldTXD889WyZyJA9I2rl8oOLobw34Z6lr3RqTqZVxeN3/qkMTmVN\ncH8yYWfz4Eejs05L2KjwOOMy7+WWVSDz2SY2Yt+hvoZhaSYkwWipjl7C9s2jMkePlTYRFsCuG4bH\nT46WPqptd9DjIKj0G6IV8Nb3EOVRMCou2kHyEsnHxaK4LjC1yHDP7GRoy8wGHf+03rV02t3T7ZQu\n8KXrObaY6+U7BMIMpvjEmouWQBSg/TeMV8gYzzjMBCr1CjU9VixPiJ23jAUZ6PC84twcOwrPjtBJ\n9Ps9St5u2HpCF0R+dQEiukM0q+ig6+ZfxnqtctaveuLes9pQh6VoD6n7YWGkwVhJWn7Zcl4Xrvof\nb2EestQavqVV94EqwxZw+J2l0wwyjStduogZ5nR465etBuSmPyqpBEzFnv9m/EnvbV2KYdmUy+Hk\nZn37bG2q5a9Lf2SCz2kDknkESUlUo42vrqlIJ8ZljplfrHZvylAgNE5Dp2l3vqamjiMsGkmp5QX+\nc0nbzSWouRIuzsoB5gO1vkmZgajbNKZNkOTjXn/02QayhahheTOXQQ34eA50nuUFBIKcVSk9VdjT\nxBKiCfJnXl9rbX5mY5DOCXxQzH2XNyq7O1f8EUA4tXtYRpGUQc3tHWdqhQpvQblU1PsKFkGT9qCi\nJhg0kt/bLsRiOrKIF+nFMGNFLXYB9pf2+d97R31NRe+r/4AYED4d8y6GIOCqaplPjN2GFmdJmXNx\npDg/PfS5R2trl040plZ65yP75D7vqwV8RYw4R74OX/KMt5rkub4heCpsFWaFwLmPfDax9NiA7uMR\no5AZrTNt67CmOlYKYKFsxPfJx39EDQdqIoPHwZsaNCREcbF8UnO/uuf/stoAIMMKzOYU7Tq7wk1g\naoYuHsh1zOsPq9M1dsoLQQvrIVT6mcslB6L/Ya5HfoO9xLwShFQJlDn2BFP2bk2ZiDwWPksJ5AWQ\nxPyXvs5gEI7K5D4VUc/r8JRWeTKahIZC2A5uQ2l8VPpWfYQm4fXmMOatljtRnW/jUxjHT9oBNKkD\nqVxOF7InA9LrqEPIf6W9F26Jn9Je3Kj61enEkQT7N8C0eR5BO98mUBZsaTHA9eO+mZ0zY6yBHH9w\nIZIhemVTpxVzfFmz+eyY+2xzs1QnCrg45RzeEvUu0GuLNpkx3xg2F8iVk3kuhkgVZaYDYxRQML2q\nB5GxzJuw/4Po04A+WUBVanjXT9cSSB/HkPXdN4eynZIYzpLITcBi9mrSDMoFtv+a9I3cl+O8DdCa\nqYUWNoqWg0JsUYcTLCtR/Cwpe+rhdBoyr1qV7Pb+2kMYHZ4CPYgQqlXzIpsustkAlJjiy+wK/vBl\nfzqHsdM+VGJuL/5Pvx9Z+hmpNZ+/09z+Gl4n3Souu+Zna3gXbBPm9hTEjkEAHqWRmKIC/tcpnWu/\n9m6eym927TklGXpNh2gKnbXQMxUcNaVdt/EyYOGaE/X0Pp6E21GZDj08HgjvlSRZekC2FFww9ZSL\nFhZmCjWUr77qriZfhmaMYo38mtWIC307XLh+385Y/ByGaQkEbR//qCjLSMJSAOi23zGlfD9alyS7\nyzSbI+R1nKYqR0pUJVAv7NnRxVW6IusZ1SyRxgGDUOz2nxVk6QmOQBg4pn4OK1/hkWkCdalkr5VO\nle3IXYWZBupCe/B81dhLl66IemjID2jk4M0Fob/2a3FPpbeoiBIU/la0Ykmi6d0I9RMhyKhDo1NW\nH0kHSRxDD65uGyhx2iasDN+oCCmTMcVoJoAB8ihQBapgDRQKkiJgykvor0GVGVlJHThFcc5sOknu\nEcHXIM5pDSiYilxbV1hOiZFRi0zfKN2C81oXkcJh69IWA7MEPvKhP9XzewiVgwyw9bE2DTr+vqKJ\nGpKPhaSYb2PCf/xMOkKw/2IxZy0DvldZQIz/H42mRGnxqK6GJOcbc59J/CcZ9wicZ0vlX3dvdCSm\nG/tCgWlIuQo2mBqDLEoEyrSrg29yjYYQ9PEgRsJIeh2C2wK15n5uJ63tt5OWr5DLFThm3fkQbXgA\nXzkGaTJGsD5Gs2Tx+fBfn6UyTOK1IVwPAN2zlwML3qEovVHmxCxxqtRzmdIHf7GFU+QS3eF5ypJb\n0Wkqgu0lYdjYtGF1HqJZ/w8g4N2UtppxgUKvgsuArP0ddOyJnm6Orag0C+mU1jVJOTLJsZK9rrwa\nVqnj/xAt03OsMP7FfJJHDWN1iM0JjKx5TLVesJsyMHgC3fgIwfs1WJzkf+Jfi9zmVIQRRq4r8iWC\ndIy7DQ0oHJAiYGNlibIGm0pzBxeWw4gNavG4UxYrnq+stF1WW1gQ/LowmenwG0Cjy8d+i8DiU2tx\nqE5kkIRLYskE4J6IlQRKWkbBdjunTe0d0Y/x9vFKR5vbTOuUbFIiw4mrAwCCuC2x2SudYBNzDkAb\n9mqrAKsiJW2MMW3oV8nAwZmWBbAr8VjbeR8fRgoB65KNf98+GVk5xezWu6x/lnr0CSqNhgP8Aa5w\nQB+C8B3rl00CAv4LtcFA1OSpH9mVbGJT9jlNU34s6OS66nmJrHTsunWjWwfVT/YtIc070EwUHhu3\nkerJEV9OAsm2mblaCWXdeH3oJzAWOt/S+oMvNdV2qbdpyyJLWi9I1SxLtlFBqPLUdAhPAkz1jsLo\n2NRCg8YRSi+yN+uNbNtBQocjb7uBxCeT29n3ml3LzabvmlOf6To0cuq0SNOzxR9EqwHpiruBbcoa\nMBc77aBf1a+9UX28gIncucc0fWsN1jEkEXvx5chO+sTft3RXfVehJrpbpg1g8/SV/s0KS9NxY3GR\n+TNV9hAIdzH2xpxdAZA8rSqKcNG8BWa97giCGGom7uEEC7G7iZs06soDK+AxQRAJ+WmZZyXjdefk\nS0xqti/2PLgu3RiskjNwJldrE1I0uHPnCXTr+d7iBEMi6hjRTrVY0V1THygB5Wz3ABeLA5eOOzeQ\n8Vi5uyjlKB93QlFWHH3lYO+j7VPFOcfCLG9spKytNXO+3ZMuZYAEh/nurWu4ElE3s+omZ4Ov2r46\nEPwYJkVSjk2kGvj25OW3am+nVgLQqyod3R4eeO+slIxDIlI+vEyjLr2vXsUl59o/8nNJajFRrNeC\nQBKbaVlwgeYycDwQiAAlX7U0TlyCmV8LvO+qMuJA8nURMapsXSzQ7NOWsqrGyOWi5RpvFeLBpYJp\nlpXLdwJeAfpbP5TsqK/x2BBwqCw5+v8ts6eJrk7ZnXlkdQFfppkElqUPdjJRdrtJljlexJUV7l/S\n9EDrkcun2vl4KeoH970x/9UwnhhlWeos67t+L7KIn/jTSKVLCFzmgUCeWZOXApSSksada+4I4AAt\n7z60FhuEx6Wcbv5oZ1T1KOEQG7No24iw6ZsU+bkit31BeKNlNlf9iykLR1hA+9n4s/SHpuFH5j3O\nZSNjGYijauXyMyTR4ixS+lSVSyrpQkorw8J0EKC6Gj9/QrLDt12EFhqRc/lDsV3fcl6xs9O9V8dY\nA7lvM7Wafixk9rc43bfekx0ML7M7XG4s9WK3csfpY1oiMozMgqXOJxKD0kuzPssANEUXQ/D85/G/\nnAGdrXqPPiwy3wr6+JocvyteJL9WBanC4cihtz5nna5s1tFdbiuqfysaBZfzBV/6YcTDZKwKvTgm\nqZhIglOMJ9yJqyfJq63r14kkxSjwQMWG3RRiWcLLVOKSZtthZfeH77m4D41miS7Tc/HemOyqdMG9\n7Mw6ogHGykZ/Y7w7Q0wt8JRsdQCYRQQ4KdGqy4hgYTg64Y3Mio7eARXUZoVzr/CL0MIkbX3qQrSJ\n848dCKoRD/hC67cnMPZtbz1gXdq2Qe07Uf9HoKEBU6yOw/Gzj4NiAuP0mSKpjqY0J+M1wrQvgEvh\noYxui0aJNJD3C79rW+WPGfmfHlhkbxLLK4xp2Qbd3PTJR7sOAXqMjlWayatca8PLqsvo3/SUsDOd\nact9UheGGJcJzsHrFJGW4uJVKPja248SGfmB1ezEknT0Kn77YINW3YbBKksXNzXs/TRZwXPPmeSM\nillWe9EpxQsik/xmmOYNuaJZqBpJHWsO5zviU5Cqmtej8YXYjsiUzS0X6nwa2joG55fD2ePKRs2c\nD4kZc18LH99zxLxqlAqef7Z7VbPzF7rRytYhJo3++aDb/F1okJvnlhcWdE8oivy4CynFXCq34Dzk\nZddT5JfNqsqbsjI+Dvnk1g460kimaqtZiSlBWjGOWPbO5Q3FefJ2yYguWtBjOhXLkRhmtS3Jqkyq\ngaB6RKaxgzhqO7fR+aeq1r7dlFxYg/rwfgT/ou0hs/cLKDT2RzS9IeUgL82bZiI3uwApqaOWHjLf\nYSHAEZHmujq+y5+hiIUudFbVXYop0+n9iz8D9T08Y5aZ8XX3jSHKIoP+lzADFDe/st5DYrqf2V5W\ncYAuMkNmBP5vJjfK5rv7oKycQAyZpdD3KKir++RKXBz+ytv6KDZ3ruKbihq3P45XWbI9LE8M/NAV\nS64P1J5LKMAjAAkp+vYYdgjlsVqQL/Xbuly/xdraRbc1pRq/1hjWinOYOUkgFMajLAThGgfpYUkE\nJgYiVJsGajIzDh/jbbxj1TYpCLVE6S7b+OmyVEZ0T/xfxVDka94tS8QhS+UCxIXrIBfU5o/3SQ0h\n3vQn2lPeB6NmP8skmoExA7DVm82EtJ+we2cyJ8urhAD9sVqsW78f4S1IwcxShqM8Tuq8g5BgivVO\nX3JMd11qi6nKODzvG//MJffmArwG12IWCeAjpSSYpaf+6M1NIO+tY/2ZRIBgaTyaYDoaiQK5NVY4\nmYcA92h6QkfdvQXPFJAy4ys/CdO1Yrj99gjrzF+9+gtH5kj5guAt5HCh+4eciVqTfzSfmJaPLQlj\nUw+nQLaoq7hw9DWAfCut81PbxqUUcrVoZYdkhuFacEbq1fsKdSPr9w==\n`pragma protect end_protected\n", "num_lines": 1194}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nCgyLps+SA0ui7dPkXtm83wP9WSUpTVOaNUUaEiTx3o8bDibppEo7uXVLsKORYUGbahjOTDE6kwIY\nyzdcsZuJjQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nls1ZVg3oo/4jpb/tGSZ67UhcCiJPRZSibleEkmR8FGMVr6khAWRoF6kYXnp1zsyHU3zpkX5aZudH\nhQIPiuWIX1ItHdefmGknlXR0g8ejEjnCuf7wiNI29U6+5iw2QftYNsn+9bDRp5kdheVUcuxELJlA\nXulkNd/ln7GkFepSqYc=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nB9jNLech/g/tKNMUKP6f+gjxZsMheNAx8UaJ4vLJVXHNXpNxk91NHRM3Xm9hGCv9VXOliR2a8QYA\nPQ1bZLU5blYqH+18qF0ZF9Jo3IiF0g2nN4gOYAI7m5j6VqkzD58XFZMLPANE17Rohp8jENs7nh79\n49oN+0loRI7XCt+F/XHBh8FH2rSJmirxDK2iqylD74LWMeTBokuvbg3zEGTXe5qvYmMaRiXcTPZB\nDS3JpPd04FW7EUk+5RM0Kcu0Ly1TuyTKFn0mEksltOKTCKOerop73A+MOzn1eX1pf23lWhgzfN8Q\n8HjhN+i90Hmn+Ojdq+WsQMHc6+n0Or8KFbFReQ==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nCS3PEjLSMy66Y5kMQ0y4fL/X9nvJthfWlN6tOA1JzOyIwzumGq0fkllz2YtjUH+WZKf3DOAh6h50\nM/7oiAgx47vujLlrhLAvEpjj8WUfQd3LXqVk3NCO1ki3s4QNBrpCKhg86ykdPOiLuEXDkUt3v04y\nuxmO8exLVDFMG+CzMLadbS6QzvWCMXeAb/FFPfVqwPMMw1ByBbbNZPDHX94DLgrF41I4jklsrd2r\nI3FoDtv57i7fvGeyrplt+iDFl8lNUqFZyHP+5+yvGYA60xKn+8Y180eYGnmQ4wGtQ6Kkzn55UAKq\nBjhfYJqchzaFN68doG8FMNl5CP4MfMmIG1TAbA==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nnQe6+EVbiKYI6EF2Gkjs7kvdzSmGHXU4qtFfR2dYFwHCWHPPG8cZ35Gns8SCNITeaBfeRRFcv/q3\nUoOZpWturDci6dtPwvXGTKFk/2M0wDGp1JDGd5iTwJk4WyDb6tdfibGrM334X5OHFRDy3qX1Uovz\nSj9hOU/EFGjRS84ag4TVcz9z1f1Y+CgW8Ym4KNOI8D0oIv5DmjP/nJr5kVGL/WNmhRB0h+vtCoTs\nUcGqCPC2gQnw0GIBNKrE9ivvsGq/ACxJuuSLwAzquqUInK187ExgWQLiPHhTH6pfZDqnyZpMvGrr\n9OumyGggkggl7j/JE2vtz+6aHVWB1956RXcbLA==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nVPB71QTo5TspzkUp7HQwn2zfRQ8tDgsnLTLdZIsMOrJ+Y8fHz9hexHBR3Yhia6VnY8XCYjgPbAId\n7QK0Myn0r32s+olwHQ8M3jsY7WJNK96AiGDDRm0HHR2rAUT0mbjaG5Vdc3kGr5OmZ9abSnBv6qJl\nd6qqhUFQ2fTIk0vkv9s=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nIOa65t4pEqSGhDPlzgVIxaBhM6TFiSGG2C8XLJL6CyEFm0OzjlVbdnJuVLSSsqeN9g9q0ucPVcBs\n0MDNHCUMFAPmUvHCALV35V9sWsxZnNLruGv6jYCoLT4RcYb/Hskha3PIaIz4tnT++Oplm8SDc6KE\nj0p7EoQtGWfdUwtiBHuUQr6oMBdko07oc+MLXZy3P4PwN6CMYbgRTZvUcrJfxR1JLpjpTlr85sRE\nQCUEGnVHiSu2dgyZ1oOqfyUJGaHcNOM13rm1E+h8I++ksRVlalZKIcrckCfC48c5nJdrthR+8rsa\no+k61kcLH2NbhPC9dAejCTOCHyq4j6eKfXBGGw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25328)\n`pragma protect data_block\nkSwfaOQ2lUKsMClQk038C3qrnU/w3gNGhmdlLNfR9sWwqt9+mhQ5FChgk+V041Zn4jr0vEzfPK9c\nu3LNWSj7Kuy7mPDQPF4wc/gQY3v1ZqRVfjn2zXECRESZ7SISVb3/zgxGap9q5OV9OP32RkaV4kdr\nws8IbzNgdjoMmUEPWIST7YMeljelbQVuNUUiauyLev5wd5EZQgjtqiLEePwttFZFz+wDhSrZ+MSh\nmmVhsv4hlANMdsmgswzLepN8QpuS2x+4bV16nI3UsgySXVY0LRP+KYonO3zuI7oGlDGAKq7rVAA3\nosLmIrbqcv9oa8RF7mwv8MG56fHnNtMapNiNUP5a204RBeFO8tYuAT8VwFE66FWyg0x+SFytJzKX\nnDz/x5eXYt6o3ivPJ9zrCY3V2GzhHa8xLWUdmY+f0t06M/pjIKnPlBKPRL27dlEboBL1WLxjolrb\nZFxdGyaOrUIkqkQm8IlHVFmnZtXeSYrONP35eMP2kL4cGqUTusPeoqJ8DoPv/15TbKPwDOmaEXYn\nOEGzSGJPYZPw4+XZbtGAj0kRbQ261OYzNHDs3X7G23Gf83cq2BWgy5D0KMg8x7egPLMpaWTEJFAo\nwHEzBZROkgZBRyzx4uuOLJAzJ1Ww6ceB1GR8wqI1RSlj8gKQ1TwofF5FVToWZLT6C3Qy89q2zVS9\nA0mSl07IkvpxGwr60pFS+XBimis29n5s8FX1+Y2s6ykhocSOf8NQXfkCEGy+ol7sHN6ItVozii4Q\niSDgC+BYBApCgZz8ak4UXWCf4OdR75O09s2dPW1NNUB0LmDZ+JYg2+lHMwwfQbN8T9npoNochopd\nGUxTp/6OzrzXYuXdCTP14tOiLSckvwYVGLQRUNEHZFUjoAyI/K/pit5jx3240OUI/mdlbVjdEtUG\nZyZ6ijoMx/CJC0RWukb6rnM7lnnhpTUapuQNw9WieVmTSHV397OKlU7n+hVDrAOVM0fnBQoXDeAC\nPJlef//l7tgQN1x1eqzQkPGyXOWazM8DwiOoFa0tqkAslzrrb6K+PMxVs85IisOolgJv4q2sSZdV\n8RYCZM7MjfQlQzFbENfRZbZsAYj7zqKAdfnblfnQtX2D7QAAZtAVZbtICaIF1IOSNnsCi9uxK78Y\njHAC2RNWOwn/P7vBzImG9xwfIQ3kJklicNBdaHlR6kV22DiWPytbzi7H5Yh+1OnunmSMF5aO/a1P\nglEwFosYm2rOGqobOtvZdtOvQZbF2TLhNoCULxpUVohVdo53ERTsmRP3+szwtxMpYpRMOSIt1tO/\nmsxP5ho7MgE/Cc90lcabOMXU6TwV9GMz2Ec8YIMp8yPLEuaGXNyAKwcENA7mOQabA8/QNE8TzFxr\nzDj4HnLuxNA7bZFjKzEa951JtnbjQteNvnEOqy3O3vneTPebf0DNwD/PH2HzUyztYeqCd+4Ke4dl\n2XYcyyJlr51kmlzHyIsGKooMqHJz+hNY04caoQWD+Ev5YGjEMqMIxwhmZIm5te4ZzfunIO6qNTcU\n43BM4NF6J3RO7yg4ITHq50A/iI5hpAQKix4j86HXuGTgrvH7bsVcD2RZlv4gBrOkQU3BGQPAJeZl\nd25lZzULXvWYJCgbaXnlh+1h/NCjB/xX8TnucsxmmHdRBOGDImMff3FDsIEnGC0nEiFLP/fR0vhE\nog92bMwB4+f6Ja/JwPj/hHsU/Y7/vhRpgrJZFtljDVR5p6SPzfqZ+d6oqCyffmOU1mzMzEWLf/T+\nlKoSQNrcH05a6ts9/xvttvEnJoUmUf/H/09aoExwqbqLqI4rb+nzL1Mij1Mj5wjZqg+RzpWMw8fH\niJRUlCev79gLIKjs14oiBS/tPttcY/zs2qHsglefkqtfKIEk9s1OKKBE0NXUYo2xaULzpfqKFTo5\nEFsbG/eTmyP2NlgcNGiGzT4KFsKcX7sZCgsrutPwhhdzOBA/8N+CfVeVEsdrP9sS6ZIQs7McQ/7D\neNshaOGNMbXYLbebelDWqbszWYtgfVphDQs3tNtemJrIcmtApxUA/7VfLQRaw7D19ar4E8ozZz5P\n52VP5E6TvxR0qnt4C02mR733IZNNNYzEN62jdN7lHbe38BYdDWlVSjQ+j/iu8H9Uw1c9sRKzhMvt\nYSbje5593WOrVBZd8GSLK+W2/0BXU1rU8o321xmPD4KzgPFpNqOVlFZBVpuhz+66JTzg0dN+hk/t\nFZhN7JfVIRWniAPyHn2JDFXcGwD706qDbKu+155s7n+ZohU1JSwKxTvrORfYyvnLkkGm7fJQ7YRL\nt7BfgeyatEZYG14LIXAYjvgfjq2wtToa/TvQDGhvQ4Vm8nZzgWZcwGS7TJsxAg9p8hrMrp6rWD7q\nT9p4sQFyZjXkeGQMbXKNj+j76S+MV1+ZlwlpMQmax83Q8n0eG6krBX8W07reDMXwDi/pfHZnR9be\nwf1owb0a9mwrd2uTVsyua6HoiqBX3Pal1FZOUICvgzVeRPQjtX+5z2m2bTFa9Husd5qgJtC018Kw\nio6hzaTDp6k0pEhuNWKxCu5MYR5qZsH1QhQI1Tvc624IFJ/K3Ay7xDjun3verJ4OUefTvdYz0TxI\n3K/tmfQB5VfrezfWLkF0jHF8SXCf/aAil2oXjvKKfzIV+wTzXtKohwD8MEfjITbrP8BbeHj4Qjjg\nGdLwOy1xTGJgUSS9oGRx2/393scsFP4J00gbt2yy4ZaVBbdIV4oPk9/9nJniWlCNrHYcY0VkRd3s\n2h1bfTegZQUVLvAzHmVWExqww+QVrN72GuinDns3uQJzkjW2oXpXU1+I8K/xOe0aOZgVL57N1lkR\nL1i82WWSl7WHMwreThqjifFVASVCTX6sg/1eVK52Ab/QWUmFtTRLUWIOVBozlcWjVZGi0/sDgJfM\nXBSZLF6a9wWTbhObbri+/RP2EJDzxBS7ImjPO7YXCEuHFqwdPBxr5pz9gOmjeSWjbTU3TD498X/8\n7PjURq5/I+TJmVdTEm8qoPvBEILhT17sOnZOCqN1sxzYTUTwOP/fh+5SFWILs8IjXlmtv+wC5IiW\nzInQYX1V02BveC/m0fmFsn8knWeUXWW75GIw8voicnX5MIB28JxYzTqzCcaiKqRigyYOs4Osdese\n1rIQSr15MSZogNQA4Q9uqpVZIJiqX0tGTYJRAdmcBKUUxy5OaslK5g4juCb+CqT435m4GHC5QyDz\nxUGN/7A4jI4VXcnL0KDU0uPNygMNYGjlBIIeSVJzFfLW0SZVCpssVP7xEDYv9oPoBQRrOeKRQ5qP\nGKUUx62dOlmuZ06pL1CFyRCnptFpfjZpiy/u0X9DAKJVLS28kyK4E4aPAlySXPnAgykaXMpq6+L4\ngwQTlJj/RWrDVVZDLpgDv/dSjiDLi1gzYGXu6QoY6yv9kehm9i/zGfAH4Nm4iDp3ttttUcdsGJUY\nOX5pBJJFOq7Xm2WbEGNOUKF4n31GtBjRcid3c6qrQAnTffL/kjQYzMWjjxtyQ4Gq1S8SG8wnZxh0\nLa2V4nn9sNN22rx8nyxr0WZxxCT7FRXBfRsyViBXA/HhwUGT8UtOaucltcNOBKQ9aGEPrXr+bnhq\nCEhMfhyJPjgUKZpaam2DDDqz+BNXGTJ1q3nD4XKRahlStabRjg2WslgaR0sUa4f1P8T98v4+AyKA\nbzxBCXiDIjjI5UCH9o6n0WB3psXj43WGP7Bm9PfB/emi58Acg56+fqEW5+VjMvHJo29TmFL8byAB\novlmPIyfC/Fii0v3LlYWAxWVA4VBG/LpFcgo9qPW+Yhz7sSZNlYWYRx8BSBtFHPZ0UDQKoIXQ/Ne\nRDObMN/WxcEJcEwTRilhQhKx6hlQ7hinqOaDY5B1GFPMN3gTpB1dC5lfOwDwQ6XQbTif0MUVz+e8\nRa51wUr1nWRmVvnL+wl6eX+bie4IcMHbk1IifHUDQJLPPCwJqQ0W/PTILBcdBSnfkn8nQdImfOp7\n+/WRn+WQl5S/4KjVdl0zWtYEetGtJxHGs8S/wOZJ2nxSnzGuFeaomei8jl2gP4EFf/WIa4OzwqKj\nz+2uN4cJx2vlfkt2FtUjeUovD56+jlPthlDUP86m828E6z+HVX7ZoDEV33LWhlQsHyKkmoiMWzYy\nHdVJabgGfyUmXygSYdEqr4ED3FjHYpkAtC/7g4WhqFvZ0TALvPcdB40O9TF3LtysXZQrhEeY14J7\nKdzxRRPsCltAu07xoEYgxU18+1twpdaZZD+XfOXHND3Y6kE3bjIxMBv4dV3AHbmPRivs4kW6H4gT\nFVcUWuPssTRNyv66CLVgv3pLFaGbN1fN1GBG2XQeBv+9kUDCq+rBrqgBwhSj0fncbah7q13tfYsi\nqMGF8LzDq5M97C3HMEMuM4FfQBc0zP81oqicqoWuBh1mhWihKI4/ZlaRO33f3t8wPtZ5Nqn0G8GE\nUNlv8CLzYvaC7tSaKV9gJySIfJKQt6yEnk4CGj+RVRu1UA1/0Er+TlbXajVybaQRgpbkQWq58eU3\nyOaqQ1Nc6JIJRNFNfKNfxWmJlQJCMbbGoPS163X0V0rQ8l5UNfYvEM1AJnntSTTZpcfamyGcrk1F\nydtxqkwn/hjqbFePqd7AqmcKjnKUO8ZLM+mkQD9gvnYXy8VMY4JM3F7mjELqgskwNrDfqk7KYp84\n8H92vTOvdcxMbuELQOGt+G0tx01omR3v2+zCUYlWznKkQJTzg7hSduynfrqjRa4s+ukUMKw9nW6s\nMH5T9pqhfXqizyUg1dFErIGw+8Nn+ezQ2lycDwRRDq5Q7kyS6RHPjMeqERFvlIbn8kimWfeQB+gd\nDYrZ4Sea0vnHhZ8T7nYIWltwn6NkOjxMONqbv5nBAXBhf6rU8M8Upjt6ub1Pp7fpd5Z4O9XOIn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XEmW6zwtcpFPQIxv6hxYxwC/spdTrLGoB4ILEP+NODQpYsELTZi9WLQc6L/iOQgxB2qkazE7\nznpYIqd971MHDyIBimsMsV2MIlfJx+fbxPxgOLnlldWhu0vSMbvH0tKsCaqq51bg80SjHoTbLdRI\n0RXKBNHiY/hwNrAd/uDNI1VArQPSevUJihWecel8HQA/qErqDeuyR3fvz+etmwA+wEarTYrJTqBx\n+0gxN2lWRXXSb1WzVOI/HRxWhUkbQg5KGLcd6MW/+7yH/J74DfKqSSUFnkbQtw4D3iiyobxCMVEz\n//3tVZ94deYB0NSkbNhQwYVGtoYwo8MnoIs31fabSPiDq38l7xlx9fp75ALhijgOEf37nXuBTGRE\nroDKkPV2KRClavVRGPGPcF4rrGho2vJSIvjU67WpSxyZ/hef2sjInD5/VTfOHdjuUA39/udvN5md\n5PU8SA5cevPi3hZnv9LPMedfbs8OfRpINO1/cETQpi3uun7In3BwZIys6d9lrhe0okK1aRQK8Cnh\nqnMJ5Yk/vCW1DzxsS0YjsZ5++CKwZzuxv+pfhRoA360JbNFJ2+BnWfrTDAYfBh3X7DTAN41eWGJT\ndNIaOmQe9nucKLsM+5bqmytNG1XR3x8eQfnSG7y9u95+a0KSMLLs8vDW4TMjY7wKGfjMrcLBXALX\n5RdBS8d7iquImUPCqSe5fyfq8aViMuTA8JyRpN7reZ7hr04/nzBj5v/GYAf/fcwf9/zsj7pkvu7Q\ngA3tRRZn7bfQXUAh4a8r1qtWmNvSRZjlNWf/0mlhv3MlEmSS3VN0lREGa6jOvJOOx7rhOXLSBPTP\nrhkBwriy03trzUP0PVLbhK+GHV8SATZ0qhsPJPvKJ1ArUmrcalWO7R95YB7EZ30RaQUr8LDu8H0H\nxSfvBDwdMyeOuWz28PLk4bAYYi1GFnYL3c+9aBO2/cQRrQOIR7B6zDTzfn8ZAlxv+JYcFcA7cDdS\nneY1+v1AEHA410TBSGLSJ7W603q44z94d7QgfZKpq9JGZ8Ss+XuzuocrjtI/CwzxAYaXJAfyCkLM\nvSecX9VlMHY48b4tYVPrX1WJPcL5vc4bTwpv5yDhIsqRRo4lpshMtpmjP/LBQkThJMDwD4Evjxd+\n0Z5fgZIhj9Cesf9L2z7FA58DJ/shqe5H6BxQXh5EHfWSUwr7+FGISDY+aOXzkINZDYyhT4Qc3M1d\nOp5u/YuAiJwVw0oS31g6x+nPXEvDwGDKIO0jR6+C30Wqzb2uD73ACi3CpG0Pju7LE3x7sgwWFaqP\nR1UHgtF0dYf7H2mg2E3Jvz0vEn7MLjcTcCLLvU551616Q1+rUxIxuCVVppmXP/ktQRbLUsMyXdfy\nEN7oeJSTC5WEEe+ruuQFCDTKWJdT2y0pdFnqTf2ppYzWv/n3pGBJxEdDfXYHh9u/s0uBYf4UjqdW\nkys6LWD2yMmnuC7j3ENi77hkb9Qjl2aJb4q/BM+soWZt+ENkM8mFnzNODGlHgiLZlOivoIO4IjDT\nBguf2s76miE8Y5v7LW+4nz7zaAzAZZrtrzoR8mPrEoLsw426l0yobffsmLCoxB0Myjxs0J/P8V4/\nWHvRj8uQlYUXrrS2N5l1TWLrnIRYqvGam//oUfGoVR04Bsr5BsiUo90ulRGVW0U8zFC43lotvhXY\nI9uIv5zMi4kvR+nv0IiHkozj516FuEBJae321TuWKRqcMNkLJjM0K4k6x2V7fexudWDHVhskWRpt\n2uQAgpcdhkCDKRctrzCKI3GumkTB6yHazXLoWdpVJ4nlq3TwjQiQ+FOK8VG7Juv9qDoWxTEwXLLT\njtJla8yzDow8WL7U+/9B877wQveVsQ2a9OJ0avMJCtrCgZt4IXYX/lmVkkIYi35HVACSra0Yc1TE\nIpiIqWFNdQuwsaJe71w/LZ7wTfkjeVGaxK0A7sSf2+WmYCASD1CkPFFrFdSXvJvK8IUNvAZt+gk9\nPgN0ff1oOOnee5eda9NIQGfaH7++ZnwFYNZ3JUzh7aP8PLUTmDuIUcEhtjMXZC7eyLGN1xrxC6Xm\nxxqU4iBoCLOpL/h28ZMnNPN3/L62xF/eXFI1K2c1NiFp1NcI/Uv0MP+uhyQsTsx2KA8WjYRHyqe9\n46ma8xWeqTc8FpQH+/SNsISHnF73a0dCecKtu6hKNrOLslP96Tl+o63d3HvD2JUGHkG4rEB8PzKN\nIG/N9pDhl2GaeIZVHaWgMC9dzD8ms0fWghnIhCfvYHErSkD8icLH7Q8OyhqS8ZUrhB+Ye6hnH20d\nGhvF09nRJI7YR/b2nPE25M33KKEY5ejkELQZCtvUhn1WEFtH5alKE7dXQG/jjYYTVK0+CbxVbBeZ\n7Ew0/6sJYi7p7QlWt/RihMVY46UHvglpKJfzlAmyPi3vdxpoEQypPvXCL7gOkR1cJKu5xhIzJ5t7\n0hT4uN7EMvLo6IfiRaKGNeCjrHmQ6nRlL76bp3vJs3/szupk1BRBTId+pKkQOlPZjq0CiyEfkOR6\n7xAEu8rgPdRSiY142Yr03ZfgL1tjSTWPwbqe6yXZJHECCaKhS8dOwv0iG1HG1xqfCpDb8bGNG5SD\ncJtGHW1H/y5DkRSh1qCMPyfyH4/v1T/E4/sXAUigrTVxwaz4x5qzq8sdSeVPJ6zEkLLm95p+QG/Z\nujUA1GC4Kp+JWSbCmGIGmH5hywCzcC5aZ7AmfTYTacxrOMh7eHq39R+INTMuzAjRsR7wgxvCfi9j\nVCrjcKH2e9tWJqYS06w9fHygPwsQBnxDua6ufBzh1vXJw9p+1YSqcdHr2J1GbaCDH9g/QIvGU/6O\ndbzF9qmG7acOplOV+UUN7bPImCfV4amD9Atdpn/yCqr17sbq/XnL8PbEfLFWwGtxeTDJNewdRG7I\nPuwOhE7/lAPAbTUjhdmGRU5jtZxwizcz0L2uya35thXsjXDoa6rM6KEoM8AGcBK1tb+yd7PGqnVV\ntl1tPRqgqsMj/Xfk6jwPKq3lc+rwQykIHRcKtuqFITMDLadL5ep6HMsOO/2PjRxrIT10V+AWqKcB\nWLdowlVBAqHvybs7xj18q7zmKGvn1/Z7s9JF9HeX+DM1keWzTV9lyDS8cfCEWKfxCCEMi8KH54Qj\nEzrbqFKm7Fwlg8Oz26tPJ6cJolCH45fSrmQ5PmfPIbAWYgadv4hxIy+8YqesRGAJS+JIa5SOSXAb\nATecjyYRjiHOI3AS8/HJUC3fqZ8N9qAX11K9lBiIjeAbccZK8eaJvQpoXGMA5/BH0vPycGo6k8hl\nTza8n1FJfrMyIORyUNwP5Peq3yZFkXNUcnMjt7tXqHfSWCwg3IFwfmOAgLs5w+K8IQjqtJZqxtv8\ndakxmjezVpTcmWXGsnw99P9JqDGt+BqYzoTXmJxw2iUPHthmNl6jiRoh49BtCqHRnQgIj5pNFX5r\n8t2qFy3ToUPQLoIhrYuIfhzw0AQLDFDScB/23Sk/8pxu19MVCgBmkfh/2xMMKtRbDkLQwTjdwpxQ\nrqEJ8nqvLO+tBbczQsREhamGHxOUpgAZam0D/KuSIlERbp1BpeZziflu3F3wDf2icJEXWOzomO0S\nnodxZZmHYclWxNI/ZytanByEfYfTNEbOvhpHGASwciuVfAXSoXNV7cVmuRG7sBuTSczVQJP0cjeD\nbfzIkwIhsW2Njg80CgQT6mdi4zfsAb0fr80e1VwVbWwtlX4ofhP1JmDrCrDU+AxxV1iJsCSzS7AN\n5aOdu3W16RzErzEE/1um+Ev7z174+8ddYoUfOtuFxVvAElaTxFOt9vUDJ3a5Z4WNvJgPe8cNt8R9\nYfuVdgr0BeqEC38Mm2VemwCGWJiilw8ZNufPdaDuT5CKev6WQzm2VpdCUPYYY3j7gTd23FeyHfZ+\nzX0yCzO3DJT4trtRE6sOb133kXpQkQyw6c32bsOGEHQ2MwtPveJMyiLcdphCUSbZygAY0Wm4OjtT\npq6LXISTFqDQGMYxqDI215O6O1e2d3yv6JmcN6E1AfLIkJScfFfda+qd4yuqjCTuj/65YSaMNf+z\n+SnvOvjH45e7Ad5YSVZ7pLWHQBLz+jaDxlZDwwhfnUCKmKLsz8mKHMw6AveW9NnUvh/sOtiLOd02\nWQJaSR/GcX6plGQLt87uWd/Se+wkzsTJ8uapmtIznpPZ0fg5NY7OuiIjmj3X/cxbsUcJsP4QK8Yo\nXMYEoSVaU6M7gc3m4CsLJESDVWv9usg/ACikf54onEvQw9jGFnP8AV7yhFIZLvfTg4xiFbNjRrcQ\n16mwcW0Fe6L1BAPAPhrb6wDKTI1hd39jJ52C1XA2BpBmZ5yGkT92S8cH0LOJf/v8yb7ymcF1OPYw\n5jYG7X5OUOCrQmmOlINIVsu8XHMlnRa9IDv4H+0ylUJnE2So7kW3rjDFNDyJpJ2yJi6NlHcxpHCW\nm65qtutuY+kbFMpIWHpxjs1cQfiQPCBISnJFVxNGTwgCqr6sHj/5ICiIsCkCO0QIy1jEVJDN2qVk\nl/ZVfIdNHng6I7vy5BzCCb63/mIDlBbCjFiafEPKSnzQwP/0N56D2ImUBCbYSdsjfLV9hiVIBYpj\nYQnNFNDu81Y6Ty/Od2AKyy6UjTdmLb1rdqkGnZ5qqAfhwM2AKZ/XoXwiurBa7+Xgwy+R2jBggubw\nbeRjsDJa7gU4M0gGheeRgNDnoizYw02Vzlg4k1VnPjAsxNr5XcW1BJ4Jm8vjEEXBBGGvVP0psXB+\nL4iy7FHUCgYPy8hYFqN5g7hLvb/wT6pkyNoUMoj6h+9GrrTy+rnjI6kGmNlIsSYu15F7oQbA+V9k\nkLTaiiD0deoYHRklY7pt3lUK7rZHQKf/n6Vx10/80i9aBofpZOIi3uyImyCN7hHcCCpYnvew8SZT\ncfFxgKGYa7V8OeAxk7jpLBvMxfr2ARp+Ep4D1sSRH2oSzKbtM/f9ncdKLxEMHr9wxupSW+XoOraE\n1yy49P59KV53Y3YnD4miFcBODs7CRM+6bqoK9hO1K2W5kvfodbOzIB1IARSmOhRwYdljB19jurPE\nYU3GUTC+u9Te1SflGvr4XsqCbbGMLETHb1HZmXendPnGcnneY+LtnYkbqK7SkCN7x9OkYrdD4Vsq\ntbk3FZFRMB6EZ5WZ214LiLTHzEmLckyG670YR7BNLjK1rQInQAgxS7Ri/B0TGCrTYRAynDMCPXB+\nEBZOhtu0kTKOAVnDj1uOhBFDA7cmnm7e9k9QBKhHkPOHHz6q/8B+iEM+hX+B4q9fpPM6oKw+Y+1s\n8b1LtwySajwDTHtloQWcxc1uR/UsnkCWBPuL9DMNYGr3ZmKTEnGhp70LePkIcfJYuwsfo/E7aCW1\naxn2sWtKwZrw0+CDk0QTotfQ6nG6Wr7hhUAnSqfG2O6kYjQyPSn4k6m+aEiUWQ48MMUvY9ABq87V\nofVf0Efv1OdyGUNFigWmZe8JDvXnZiWw1K9gwZqBldibpaASp9bfFJgdiPr2CAGTDl+r8eoMd1jn\nBbQ2igsBTuhTaV10ZWJFSAIdZ4+V3HYLkLU8oSRXqIzqcI/IiAg5SWLWSaeHmkCkSbn70TQGXGOF\npfjhv2J5yzmkmWDiwFq2qT5eWOMB38FWcEeOtiJ9xvBgjz0qOyAP17fXFxTm23JpVYazHXlTlnnH\nxJSftOg+EKpf3k7fWj4DxyytvhYqXy/Cw2R1dyUtnLFEbMzZd3Kd3ejeXjJdr8nuiqNi+s7uqd6f\nln+VwVZ9a3biIRoGDPRIqfXo5untTcj3xHOwq02XjoFfYNwh12xIfB5ZpUmpKZj34IsNZiFggBr6\n6jqqGibpp2bK8BYBtgi5WPUHkZJIuu/COkKemycnSDpeAv9Dc3KRz3nwhCU41HMq1xWMVrrY5W/B\n6Q1U+SBjTYpQ04mjzFOvYTtEim9f+nV2S1wghga3XTYpWdtpng6n/69RizgI6R1dyj9sZOcdhPFC\nLSFGTswmGoFRGvNeDd01cU3XMMT4u2Z5ZOJ0f9yEb2V0quk1hIqMxHLPaG78pHgJeAtI4ztI+h8x\nW6bMzRi+2SADpd92+2fWMSzXApfsMfb/CJmztrl81bZ/RiWoHQO7FahUXnuklE54bClGGhaEsp/H\nJDvuGKJi/CWrkZltXV3V+Y9rHOa2gxVtp1SNceOD7LJQtxy0tEh8+Mc9z+X68qvpUrp/u4tsNXDV\nXsi751iqAXXO0dnHOJ6OM0o4xjFty4aOINWoxA+xCmcx4EJTLLggpKAdzIwtad13EDly/znQSFLF\nbnp6kOJKqe0W85XvkYnXQff6cnhRSWsY8q2CG0w18siVnfa3E4xAO6o6vcJsbyH18/PAKl3e7Bh6\nNTN5XB88JkKGd58BVcAOZpxLiupbboAJCvsueNHTlyWyvvwbLqsDVuAJBSHpPs1cFjLtkeiTGT+a\nSrqsgMO+UHPBsrwvBGWtDxj3TIKE2Bnvjmq3fKgev8QgzmUU6ZF4/FNAnmzGpTTvADIiUY9lHdUv\nE12u4qX+I69/sHvIACAnIwYXNbd7R33aQ91VJeAcxifdcZA5v9C3ahUaFH3A1RK+enmmfq3TzpVu\noJN+l23KiY1hkUYhiR2aCWIXRySCyiY55+b1G2/fRN6+GV6tJ2/hDe+vqM3JlVPptTG3ZIX5Xn6w\nXYIcd4doI14tVLSyAXT+x6QXdffSrHe/NgPJaYs5pg3BnLI3GSDNxlUE/pU+OvTXDTutF6naLbGk\n3H2+OtT92hDETD3Fix908xWiPIyeY70Cbx6Buqa8znPrRqc4DyitrDyvoQlrTxSwsLstbSVHw7mV\nHsYKgDvPmw1+ZSb9KyxoMxkr19CiTRb3JOrETdiA/VQqnMkjJGK0IEojw02kx+ft8nWEvJkEjXTT\nvyjahSTIEhA1jVfUxN86LHEucrkqhb13um/j1XrS3GRfic1TgpHHW1S+0OcCHpiKzX11xznmgBbt\npi/8dC8uMXKveFYefwObSfPZ+WEbNUFC1u1Mtd1FGzNLljP9SEYPCSYTWYIzMmwRwWT6betJJ+MV\nq/08MKx6b4l9hUTYOylZcrfrrBLhb+qmqYl3C4dEybhehzgcKYDwq4KVDUSo7uPJKSObyezVPZGp\nYxK9gGsaTY2Y1vrww2p4LBm31MsezorYaIvvDZrRulc378EkVjjMFY74VdMTXqb+rpjLfZYvEheR\nltiLMDnzHFMTLx7MnxbGVbuTWXJtisMsbH5vXoXWGEWinvXUjir4yICOZiMgUdQNG9dJKF61yV5d\nD8vuzUbVZWMNKO50MKFFeQDEIi/QK3y9S7CoVspKGFiX9huOjtKEFypMTRvN25ZU6IsPSKFyBU3G\nsf2LC3U6O3+Aia+yJnOJ9j68fJ4j/y4h4EZddq3di2jiahqK6+92jBeqa2iljZiYWvUWjn1GLa6B\nmAddWZnuVAaG7sBULE1a2OvCuqt0/rpv4E2T0oCtg83dwV2wF1xwvR4TTP0k3VJkMDa+bRc6F1If\ng2DHdDMHOJ+zr50PcE8q3ATEQ3aRsHk3kiBDSNjCLxAu8Aloh4dvJok4QPOA82ahFUluEQOphCXJ\nnoGJVkBSWcXhXojWVO2iZmFMpOVj7j7CK7BqYLDRlfM7pQg0hLVUf+8hH8DhQSjK0e4V7/wJZLTP\npmLh/NhqxxhNtRDUhEa3xSQBmYRvWk0RbL7Z4jTo5yamAInndOM6Pz15AIijBTmggr42FdGAT7j3\nT+Hsa3nAUQEAshewF6KGwmCpKUL6hJwVxwujj3qdOYfcfVJVXWy+j2BjVZF3yRPrb6ZcsBK79nqA\n6znStSrjcPRpIMR0WyiPVw7kxu8u41VKTh7+x9iKHXw+V3xz8LDyVhCea+Lu421k0ftGM39elZzw\niICuqn848ke6Z7HBYQQcmBZLAnCjpKlEfKXiBiXC9/jrnytaxYWEwM1XfMDvfrkot4s/9EvpHeoK\nheSD1gXbrFhPXM2+kcS29UIcUeqaXVoFbCth3Q4gQ62DHteN0gw3hY0UNsY9Q05PN9qWfQoEZuBr\na2Bzj2u0Gt9YJuiH9AjxbWdYdJCoTVqSHPFsfTG+SS+TX8PcfGlHY1VZSdrScBIh1mWOl+bRxvvw\nt1Tr6dyDMLPJXu/CwyCj7teA4QrSMaPNh85K9Dylja1im0yXfAR+C7wRmRZ7Dd7QeOV5hvEC0YGR\n8TZxe1HAae7Zs+dfgdvBmR0esfWzNoda1mq2QiWH6R05QM/1sLqzdodSeB28NPx9WP2IqimxNBQh\niv35VU4A3epX/FjfVmMt40C8+kH2eC+fry5mYwvLXIAXZisbdynQAnoM+GQPONBsjaTyOZptbijq\nx6/Z8Ujz3G9XSvdiA2SVWuD410cnGgQrcWQ3tDBKfsz469bMz7VlELQn6SUzoUmTVeXqlunLMgAT\nZjAFpyhxsekFxEesgRUprfqnBWj8WZiwYk+++EaFrrl2LOVoKTGlASaf7i7PCgiMuDiow55MtAdH\nUQ2BBuXL5Hb7cpA7Qv5m/wgDTkM/0KJe9wVdZ1x+8bqBXTFyDz51576DrvtZtAD/XbJnA1kE5pDO\nTIqF52tj1j095Awo65eN1D9llYHxAe5KqySoIQ/mUCts9O55Ttef/xCU3rgLPln/8KfKrqhanX9f\nQytLhGJplYSQ+JeTpwLQ4AMsrKC5htbluB5tV8y6yp0i2ERPTDEqqtq/V7XMiqYbdH+04sQBR2nE\n4k8UUrISsEJt1r/1p4kKu08UaqcNRB+543qvLgCj6oYuFvcyZ26VMqgmFqYnLBBt6rxv0NbItcuv\njnXcTIV4DNLBpHsCGtPT6iKVmV+AarzOVNre2mZDZSjxENol85XuFWZKPGwuQHGf/13N0FwUZj33\nbcAaynRH5O1xKzw6B7o/6QOLte8t808bN8lTg4RtVzap6jb2nZQ79xfViEMvZj4TZ7mREpQb+UH5\n5w0c1wRH6IQcWeMYS4tEKNOFbj1fgfFa5WqDh5RkiRSuT07K4kqQ0IDvbuKVkJLaGtrQikvV568j\nJtt1GYLsDnJvj414UYYVlISVETETB+9wP5/n9mMPoKD1REvPhzX0F436v7GKY4JczyQWlQtdlIMy\nHSjPO318tn07kwO3cAJ5fsIffJCCNagrTfspZf9bzICnrQL6maPSuNgYQgqFwfDF2RM7YKFE+zpQ\n1JcpFaojBF1JuaWNYohO3O3iXCJB/AErTdLoDmZkRGr7+6yhSCU/MqKmeu1eMpbHzscQ1l6VgAoj\nh+JdxnWiH1hTvWfwHuxNuwiNd6hyvHjUyakzZlmJsCLhEWk28R7wCG+6TQMA1Qsc63dQtHvPUxkC\nn2VqxSKjMhSxtS2iXEtF2i4gqnU7RrlZPaNwq7N8FfBAIovNAkquXXYkv5QqOch1Inbmi4qUAA1k\nQPEde2r+zd3qjLYuEGGSjcTd4RTxuMzh80+//d8arJdfJKpgc51kD89xm2S2hti42Db5ewQ/NgEx\nD5Oc6V+9Fp6zaOdR68MZ1vqFLmPmxrnOc77er0e4ciLRpueVvrks4AXCvLpDexU+qwqJpHcO4Nsq\nePNG3yBCFBf+OkklK9K2i96oQfq61gTjMYDrqdASmgo46lvYVsliKZxiATnOtrw40xLe/I4HyUek\nUzpOa7lwnkXdKgZe+gx5Q0jxiJiTE/F3r+2UpJTaO7MRcwplFvXFPSSbDHfKwF/BQjoMq8/pnM5R\nqZYfGin5xwtXkin877nraCfD6s189FrFvYKq96F5I+uEq7n74mQyY274WQJw9Pq12zUEbQsDg0DR\ndgsWPYQEt21HWe5pj1YjzKc3k9dC903kOq1+KD26+8pdMcpvICRq+WJddxHfZxl6ec1XAt2QKB/w\npyPg4yDmh/5/aEOuP45dLO4gUbGL3EinXZWQ+E1jIJoSnHh6vilbDhtX4e7DJ46+QIqny0h7R5eW\nsfDz0mHmHpRxuhReQWkB2yJeHEe5qYDVKFzzV+a/yM9kAxoFkRxFTn9o6n0mtJORZm4wxoGeQlwA\nIXr9swVxSPgM0S8/RwgkdEGMDAz+BfFrjvRRbbXsrQK3aPWDSTFswnscfXV7EW6+nDVhMJMbes+D\nf4yXRYnRL45CqKVRwr8am3VA8FgN+DQrwIvAbrZaiZMzBU3TBLFQnt3zNny734g6Ufl5gloVBA0q\nt29E/m/RIobK12HWVG/5m/8MNwNY070i2VYegXW8o9i74wAONxZgngxdmnerN+0Bmu5ugMhe0V92\nT/X9Yt9A99AjMEGdljk06tBlYIWLBBv7JdeUmUItCy/FWuPaUZzUGLKbzoBfwXuQG458SVeCmYqq\nKCBgyFSQONeMJe7dhcaNg88JTodC+KDndvWzuL/Gu3YGc0LuoOFqIE6SumcamDQzxQSTHzxsJW5D\n9+WgLz7d9U1V9dZkBWq8WC7scYXmYEJY2TVNJjHVgu/DaW5+XOEKNkvtj6pDnGIwi1nRHt/ywZEv\nMkcqF+WVwZAEUXVXzMuF3xvk/ytRRhgorncR5sS3ArptApRy/neZT/RDVsyV4JDMGSdzgvweGLjn\nD2KQlEpHOu1r0lCWsdTnBML5Ya5tXGQcD0s0DXsJWiJqHyeWFXE8YmOpRBKrnBiGLJaz3D7xF+dm\nYF950bejYl9BrCezc8s2dFTTXOiPC2aLtsqtvhGaPGRNomr9s6FF5YDKECFX9Gtzy65jD2Uxi/tQ\n528R4MC/Kh3P/bo6d+mGGThuyYu/w08SZJKPSMmO2HDiE+mtRVzR9pP+WZ/MpeKRWYf8JZZ1cvz+\nQ9r0fJKYmsiQgj9LJWZYCdjz3tupcrvAXARjilyqBOxVIq2OQzjnIINDF7IvpWnGaenn/Ml+wiLF\nuK+niFvzqRl0ZzeOc9MHYQii1+56TeTxWGY+DM1kHBxBOGVqJVkIwtxkFtjDVk+Zk6HyIPDCN2AR\nms7Ojlj8L9WJyotBzxLNdmBQ0dGc1tpCwdthepMi86OcbLBDaImZ6elWWAFQx/1seibqgSYGXwAM\nllhCxzv1smGoW5ScDPlgpzxfrIsVNvlBXRBMTkmJ+qOQ1/ZonCBNBvc6wysO2/bRH2q22N1pvx8Y\nMeL3M30cfu2qmswOY8Q7zJl7tBMfeaj22LgZsejWPOlhwAzfQWVy5IwBujhIplfaAel33LBOiS/p\nAkS5XH8sMf7x24AVDupRC/hXOAy/awmE5KNbsFq/OL14Ptlmnjpyf9NEh5ea/cw7fNWpTaK1Ozo7\nBa1/0RAk203DiiRfXWBNTVH2047nL0PGx5U0jzNtxRJtrx7qOVd0bnP8bRRX0fgGJvrI+whKaSa2\ndI9EJ2rAnBxkJrexb7OzccL5GW9f8fOd6HUYa0KUq7s9PTeV/hqqXND6gZlfbVp+6LRn9XX232ig\n3TigRnOeqs5gBWxf+yNhnbttVTrVkhyHkg/4XF/hGzljDgM3xhGsLlAQYBlu1IFgDQKB0QCcqLB8\nuT+ItAHiLDsKp22zq7XP3hZuPvXsiMVXhk3gzW80XBjO9YdryFgZKvJOslBV9LRpqDLqwVjbwVvJ\nFJvKaKH95Kobys5cQLXhCVkROVJNghm2IzD+gAvjjNNN4v1g7o0HPABDSfWhWSxdr3Q+M7NvmgKg\nmX4lG5pYL9gwmWn43rwtbxilOwvejyvzUpDsfT7sN6rywK4FiicOwdZu1znqp9rTkkleBJU8oWzw\npMUGzh3EvA3wmUx+yi2nJAivFxWtCIBBLF093Qk5TZ9JF5SsZMriphe019NHeJPN7VM0igq8m1nB\nMNsGXrJNqPg3d5+VMFqxPsN1xlVssCxiDRU7hLUnSCPJwOsPbrJ4jJ+iI5Eu3MZqffJdPCUKVxX+\ne8VIBYaCIU1n88ZRBy0/fvnfyBlP3rJegasVh+Gw19ccUnEcs9NjM/kJdHh6qCi41KIxuTjFD9IL\nuJakkfHei206Hx86Hfs68M1idoaz1YXPzE6MLxYEHPJL/jC8wgpUZbfDQMUY2fq151hTgA5UrVXn\nzNvQRvIwp+ejQ2rq7HsJh4xpyAWWp+UNkpIIGfCUtHjAZl5HT30QkWkdsNytGN0EparGxYu8oIDB\ng5rze1cL7TqjaaZth3GqMe8oc6Ee0mdxzqr6WT0jcmT9C0+Id2YSDXTVsKA4MPNekS8nIvoD+FzK\n3wunleyNqhPmHrATn4TtGMsq7mlqvPpyOvoW5T95hr0vyPIYpnDBvJ2EE3A+GoWaeAMfVInayQk6\nXNjWGST0FMagFBvciuZTo/A2VTJLDygqcDZPqqZ+0NfBGuJwo+CRzq5ICxtDwv0oLe5kj3d5G1qy\n2vqHd5m0/71p3ZseGeQM8DgW7Hqv36f7iGKfaXQmvwwIkOY8H2KYBOpRuwOPMwj1Ez+LZipYbyI9\nmKj9lNhNz3+5fIKZFgF29TCo6d6au9imnNXR2ZW7fZGiGKIOKv265X3hNpcDmYeyEeetT7nHsAlV\nElEAcD62bZJAp0i5Riea1lpN9hD7nin+GHCGsCd8W9cYSE22IJKvejLcO5WgiW5lvqCCDCvfwO9I\nasCxXebGi4uqUSQJBxRfSbhVSG8FeKR4XldRaugEqxc5/843LFRdlm1V832Igc+G8q/M9pmobo56\nB5/SwdIjFyaaBofHMML2Dlv/P5YHqmWOMGyNfBRWRtS9gcE2rNA5FtcXXli9iKiF1v6ngG3GKJVS\n1zkwJNaHKKV8OMARo/c3JSYi/l7iC8eWvXxNDMKc/3fjIVgTCeY7RM6H6cWYQQdJoPqR7EG4bDYR\nosVI79WGWVefVhS3TxGX8UYWAxQLbwhbOuie2aLQBy7YXgMNPgV8PIPPHFmVIzHhEZA1OuVkbi7G\nGFhRIUifmPq5g6EVr+xX9TuJHZWSJJUT1/JUWNRNVOu6XNpNEeP1S2ghf6oMAIr+ISdEeDNZOJO9\nwXy8Rcklo4dPaT+lHianOxRpRHEX5YMO55V6aeibuQKXJRwjgfWnbc0EKoPuor8XUbqug/6ZE7j1\nE7yXZYS7KtOsUnB17h6KzjGFznBVRt1q+84oVWJKQIROClMVT9XTjGP9kFT70snh1O9nsL/grGB0\nfUzU/WoBVRdp0oFtZ26Hk82ha/hl++Uivq8UDIol/hzYkA4wQBuvgSSCvkmMbHWQLfMHy9PjciE9\n/e9Vjgvc9KbFGHTb31tbg4MoGmcc0HGO3raQPrLTnXfdGV3VWfGKMfy/RGdSD57qi9E3wNrgGMSP\nBKiCjKLPLI3xHu2qsaJJ2F8uno+WVTOfp2lZxEBWxLGsES+FmU65TrT1fy5ZCeIeaHQabk/HcBXt\nF1uSFz42aPdTZA0SqK5+4faKUTata+cQjVPjsAADtfrToRZy2d+6EHlvXC9ksn4GH17OlPSdv8pP\nnpKDZ1eaJxzV6D8qqVXPOFttt360qx7cWRYCcFenhFVUpxBKZfuQEW7mYS9lVhghyDTWX5chKYKm\neC/efWFFT30OfTwIwInLus4LYOnj8WdaxW9uNOTfZoric7rUiAhwkJb3wNBW65F4QwRZdlyJ1Feq\nkEi+rEKgRdqli6dElxf6CVDapNmiUshH5HOp/PN/FbkZZxw1EZBecJ5TzDfX5rhFCPZqvWb3T7je\nx4Rg0yb8S4ora4wundEjGAzJvfgGZlpLsiHC/UJe+I4zbZAucVG46ZmOgKdt+Z0m3YhyMH1RA5tp\ngR3G4qTnB9TvDF28GTvh5m+KaTNQxve9wPIRpTpVveO39FeFWdrs/8z/yfDbqaBSyFBkaPFFKU0E\nnjRhobVb+g1SYKEkDZYWqeJ6jOLhSqsmpktl86KRKj5T+ZHI0KDotADU2BybQyijJDyR5TvNLU2z\noLnSh+nuPPP/uQ99UDd/ES+CYINuFbbN5iv3ootOk752D8/+eMepxL4TbjcVeiMJsglorDY26rQb\ntHspGg9kI+tmPLftbvJLY1Ah/jkqc9e9dJrx0Gd2X+zVGNFXtgRQEDiG0HBcACcNuC0sNo8ufju+\nDLi3gbESCBkLR5/Ku6ErOVAIaS5saiy4aDoQnu2wbBZfRvVdFLCJxpISgQCcyzt9/4Ni3fLtQqiT\ntG/HKy5+RvsyDoImtnejDJx1REIWGfd9yxIoLnsb7gSJxk3qqKd1HZJRBpcVjUQ/g9EWWECeSSl6\n4BN3NqO9qO2cEU8Gy59FzzD6Nqet0wfwTgbLbeI1ULxDlaghm2HBKvemR//cQPfelFaw8oT0H2pn\nE5IBJs/LYwG8S5XcAN/bT1DfjGTTPIqkcnCuKTJJPisEplPXbcpn9c5KWjApA4dBZiDuABxt4LRh\n9k0hb3AeHhWXvrYWj57EiwiOlS3XOg6iJv7BKgiZC/UJz4yuH/J+IERjAKj6dQ0pqveXN5Ghp5l1\n1hUwA/eKbHE1h9S+2oItwWl1gxNcmjYk3i3ogZVpSmkUoxeyVDyNTrZviXD9FcFBgUtAGOaEetbq\nZFyHbI1B/VBG33BnvSJ2WgGyypH5ggV7azeAYZ7djam33U8yU0wMIMtj7bTxQWnhhEITSH3TTa9E\nndkI06pkCNH0SA7tahb3c6IUOkrLqxZ+1oR8htcEE1AIEpHTBX4kNQHWjAJIxLC6KI//lbj4hk6n\nXCIYAKrm/P7sFmWEwDD8AQYqpChgDejn9MV+4YQYreP5x71z0l5s+//OS6fNIY1YQqlKAnJFgSiS\nkL8Mop5IvPv1Lca7HioxXCMT+QXJ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protect end_protected\n", "num_lines": 510}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_axi4_512 (\nclk,\n\ntrig_in,\ntrig_in_ack,\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26\n);\n\ninput clk;\n\ninput trig_in;\noutput trig_in_ack;\ninput [15 : 0] probe0;\ninput [63 : 0] probe1;\ninput [0 : 0] probe2;\ninput [0 : 0] probe3;\ninput [7 : 0] probe4;\ninput [2 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [511 : 0] probe8;\ninput [63 : 0] probe9;\ninput [0 : 0] probe10;\ninput [15 : 0] probe11;\ninput [0 : 0] probe12;\ninput [0 : 0] probe13;\ninput [1 : 0] probe14;\ninput [15 : 0] probe15;\ninput [63 : 0] probe16;\ninput [0 : 0] probe17;\ninput [0 : 0] probe18;\ninput [7 : 0] probe19;\ninput [2 : 0] probe20;\ninput [15 : 0] probe21;\ninput [0 : 0] probe22;\ninput [0 : 0] probe23;\ninput [511 : 0] probe24;\ninput [1 : 0] probe25;\ninput [0 : 0] probe26;\n\n\nendmodule\n", "num_lines": 117}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"ila_axi4_512,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_axi4_512,ila,{x_ipProduct=Vivado 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IDTH=1,C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1,C_PROBE0_TYPE=0,C_PROBE1_TYPE=0,C_PROBE2_TYPE=0,C_PROBE3_TYPE=0,C_PROBE4_TYPE=0,C_PROBE5_TYPE=0,\\\nC_PROBE6_TYPE=0,C_PROBE7_TYPE=0,C_PROBE8_TYPE=0,C_PROBE9_TYPE=0,C_PROBE10_TYPE=0,C_PROBE11_TYPE=0,C_PROBE12_TYPE=0,C_PROBE13_TYPE=0,C_PROBE14_TYPE=0,C_PROBE15_TYPE=0,C_PROBE16_TYPE=0,C_PROBE17_TYPE=0,C_PROBE18_TYPE=0,C_PROBE19_TYPE=0,C_PROBE20_TYPE=0,C_PROBE21_TYPE=0,C_PROBE22_TYPE=0,C_PROBE23_TYPE=0,C_PROBE24_TYPE=0,C_PROBE25_TYPE=0,C_PROBE26_TYPE=0,C_PROBE27_TYPE=1,C_PROBE28_TYPE=1,C_PROBE29_TYPE=1,C_PROBE30_TYPE=1,C_PROBE31_TYPE=1,C_PROBE32_TYPE=1,C_PROBE33_TYPE=1,C_PROBE34_TYPE=1,C_PROBE35_TYPE=1,C_PROBE36_TYPE=1,C_PROBE37_TYPE=1,C_PROBE38_TYPE=1,C_PROBE39_TYPE=1,C_PROBE40_TYPE=1,C_PROBE41_TYPE=1,C_PROBE42_TYPE=1,C_PROBE43_TYPE=1,C_PROBE44_TYPE=1,C_PROBE45_TYPE=1,C_PROBE46_TYPE=1,C_PROBE47_TYPE=1,C_PROBE48_TYPE=1,C_PROBE49_TYPE=1,C_PROBE50_TYPE=1,C_PROBE51_TYPE=1,C_PROBE52_TYPE=1,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,\\\nC_PROBE106_TYPE=1,C_PROBE107_TYPE=1,C_PROBE108_TYPE=1,C_PROBE109_TYPE=1,C_PROBE110_TYPE=1,C_PROBE111_TYPE=1,C_PROBE112_TYPE=1,C_PROBE113_TYPE=1,C_PROBE114_TYPE=1,C_PROBE115_TYPE=1,C_PROBE116_TYPE=1,C_PROBE117_TYPE=1,C_PROBE118_TYPE=1,C_PROBE119_TYPE=1,C_PROBE120_TYPE=1,C_PROBE121_TYPE=1,C_PROBE122_TYPE=1,C_PROBE123_TYPE=1,C_PROBE124_TYPE=1,C_PROBE125_TYPE=1,C_PROBE126_TYPE=1,C_PROBE127_TYPE=1,C_PROBE128_TYPE=1,C_PROBE129_TYPE=1,C_PROBE130_TYPE=1,C_PROBE131_TYPE=1,C_PROBE132_TYPE=1,C_PROBE133_TYPE=1,C_PROBE134_TYPE=1,C_PROBE135_TYPE=1,C_PROBE136_TYPE=1,C_PROBE137_TYPE=1,C_PROBE138_TYPE=1,C_PROBE139_TYPE=1,C_PROBE140_TYPE=1,C_PROBE141_TYPE=1,C_PROBE142_TYPE=1,C_PROBE143_TYPE=1,C_PROBE144_TYPE=1,C_PROBE145_TYPE=1,C_PROBE146_TYPE=1,C_PROBE147_TYPE=1,C_PROBE148_TYPE=1,C_PROBE149_TYPE=1,C_PROBE150_TYPE=1,C_PROBE151_TYPE=1,C_PROBE152_TYPE=1,C_PROBE153_TYPE=1,C_PROBE154_TYPE=1,C_PROBE155_TYPE=1,C_PROBE156_TYPE=1,C_PROBE157_TYPE=1,C_PROBE158_TYPE=1,C_PROBE159_TYPE=1,C_PROBE160_TYPE=1,C_PROBE161_TYPE=1,C_PROBE162_TYPE=1,C_PROBE163_TYPE=1,C_PROBE164_TYPE=1,C_PROBE165_TYPE=1,C_PROBE166_TYPE=1,C_PROBE167_TYPE=1,C_PROBE168_TYPE=1,C_PROBE169_TYPE=1,C_PROBE170_TYPE=1,C_PROBE171_TYPE=1,C_PROBE172_TYPE=1,C_PROBE173_TYPE=1,C_PROBE174_TYPE=1,C_PROBE175_TYPE=1,C_PROBE176_TYPE=1,C_PROBE177_TYPE=1,C_PROBE178_TYPE=1,C_PROBE179_TYPE=1,C_PROBE180_TYPE=1,C_PROBE181_TYPE=1,C_PROBE182_TYPE=1,C_PROBE183_TYPE=1,C_PROBE184_TYPE=1,C_PROBE185_TYPE=1,C_PROBE186_TYPE=1,C_PROBE187_TYPE=1,C_PROBE188_TYPE=1,C_PROBE189_TYPE=1,C_PROBE190_TYPE=1,C_PROBE191_TYPE=1,C_PROBE192_TYPE=1,C_PROBE193_TYPE=1,C_PROBE194_TYPE=1,C_PROBE195_TYPE=1,C_PROBE196_TYPE=1,C_PROBE197_TYPE=1,C_PROBE198_TYPE=1,C_PROBE199_TYPE=1,C_PROBE200_TYPE=1,C_PROBE201_TYPE=1,C_PROBE202_TYPE=1,C_PROBE203_TYPE=1,C_PROBE204_TYPE=1,C_PROBE205_TYPE=1,\\\nC_PROBE206_TYPE=1,C_PROBE207_TYPE=1,C_PROBE208_TYPE=1,C_PROBE209_TYPE=1,C_PROBE210_TYPE=1,C_PROBE211_TYPE=1,C_PROBE212_TYPE=1,C_PROBE213_TYPE=1,C_PROBE214_TYPE=1,C_PROBE215_TYPE=1,C_PROBE216_TYPE=1,C_PROBE217_TYPE=1,C_PROBE218_TYPE=1,C_PROBE219_TYPE=1,C_PROBE220_TYPE=1,C_PROBE221_TYPE=1,C_PROBE222_TYPE=1,C_PROBE223_TYPE=1,C_PROBE224_TYPE=1,C_PROBE225_TYPE=1,C_PROBE226_TYPE=1,C_PROBE227_TYPE=1,C_PROBE228_TYPE=1,C_PROBE229_TYPE=1,C_PROBE230_TYPE=1,C_PROBE231_TYPE=1,C_PROBE232_TYPE=1,C_PROBE233_TYPE=1,C_PROBE234_TYPE=1,C_PROBE235_TYPE=1,C_PROBE236_TYPE=1,C_PROBE237_TYPE=1,C_PROBE238_TYPE=1,C_PROBE239_TYPE=1,C_PROBE240_TYPE=1,C_PROBE241_TYPE=1,C_PROBE242_TYPE=1,C_PROBE243_TYPE=1,C_PROBE244_TYPE=1,C_PROBE245_TYPE=1,C_PROBE246_TYPE=1,C_PROBE247_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*)\n\nmodule ila_axi4_512 (\nclk,\n\ntrig_in,\ntrig_in_ack,\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26\n);\n\ninput clk;\n\ninput trig_in;\noutput trig_in_ack;\ninput [15 : 0] probe0;\ninput [63 : 0] probe1;\ninput [0 : 0] probe2;\ninput [0 : 0] probe3;\ninput [7 : 0] probe4;\ninput [2 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [511 : 0] probe8;\ninput [63 : 0] probe9;\ninput [0 : 0] probe10;\ninput [15 : 0] probe11;\ninput [0 : 0] probe12;\ninput [0 : 0] probe13;\ninput [1 : 0] probe14;\ninput [15 : 0] probe15;\ninput [63 : 0] probe16;\ninput [0 : 0] probe17;\ninput [0 : 0] probe18;\ninput [7 : 0] probe19;\ninput [2 : 0] probe20;\ninput [15 : 0] probe21;\ninput [0 : 0] probe22;\ninput [0 : 0] probe23;\ninput [511 : 0] probe24;\ninput [1 : 0] probe25;\ninput [0 : 0] probe26;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_5_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(27),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2017),\n.C_MINOR_VERSION(4),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(1),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(4),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH 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ROBE65_MU_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT(1),\n.C_PROBE275_MU_CNT(1),\n.C_PROBE276_MU_CNT(1),\n.C_PROBE277_MU_CNT(1),\n.C_PROBE278_MU_CNT(1),\n.C_PROBE279_MU_CNT(1),\n.C_PROBE280_MU_CNT(1),\n.C_PROBE281_MU_CNT(1),\n.C_PROBE282_MU_CNT(1),\n.C_PROBE283_MU_CNT(1),\n.C_PROBE284_MU_CNT(1),\n.C_PROBE285_MU_CNT(1),\n.C_PROBE286_MU_CNT(1),\n.C_PROBE287_MU_CNT(1),\n.C_PROBE288_MU_CNT(1),\n.C_PROBE289_MU_CNT(1),\n.C_PROBE290_MU_CNT(1),\n.C_PROBE291_MU_CNT(1),\n.C_PROBE292_MU_CNT(1),\n.C_PROBE293_MU_CNT(1),\n.C_PROBE294_MU_CNT(1),\n.C_PROBE295_MU_CNT(1),\n.C_PROBE296_MU_CNT(1),\n.C_PROBE297_MU_CNT(1),\n.C_PROBE298_MU_CNT(1),\n.C_PROBE299_MU_CNT(1),\n.C_PROBE300_MU_CNT(1),\n.C_PROBE301_MU_CNT(1),\n.C_PROBE302_MU_CNT(1),\n.C_PROBE303_MU_CNT(1),\n.C_PROBE304_MU_CNT(1),\n.C_PROBE305_MU_CNT(1),\n.C_PROBE306_MU_CNT(1),\n.C_PROBE307_MU_CNT(1),\n.C_PROBE308_MU_CNT(1),\n.C_PROBE309_MU_CNT(1),\n.C_PROBE310_MU_CNT(1),\n.C_PROBE311_MU_CNT(1),\n.C_PROBE312_MU_CNT(1),\n.C_PROBE313_MU_CNT(1),\n.C_PROBE314_MU_CNT(1),\n.C_PROBE315_MU_CNT(1),\n.C_PROBE316_MU_CNT(1),\n.C_PROBE317_MU_CNT(1),\n.C_PROBE318_MU_CNT(1),\n.C_PROBE319_MU_CNT(1),\n.C_PROBE320_MU_CNT(1),\n.C_PROBE321_MU_CNT(1),\n.C_PROBE322_MU_CNT(1),\n.C_PROBE323_MU_CNT(1),\n.C_PROBE324_MU_CNT(1),\n.C_PROBE325_MU_CNT(1),\n.C_PROBE326_MU_CNT(1),\n.C_PROBE327_MU_CNT(1),\n.C_PROBE328_MU_CNT(1),\n.C_PROBE329_MU_CNT(1),\n.C_PROBE330_MU_CNT(1),\n.C_PROBE331_MU_CNT(1),\n.C_PROBE332_MU_CNT(1),\n.C_PROBE333_MU_CNT(1),\n.C_PROBE334_MU_CNT(1),\n.C_PROBE335_MU_CNT(1),\n.C_PROBE336_MU_CNT(1),\n.C_PROBE337_MU_CNT(1),\n.C_PROBE338_MU_CNT(1),\n.C_PROBE339_MU_CNT(1),\n.C_PROBE340_MU_CNT(1),\n.C_PROBE341_MU_CNT(1),\n.C_PROBE342_MU_CNT(1),\n.C_PROBE343_MU_CNT(1),\n.C_PROBE344_MU_CNT(1),\n.C_PROBE345_MU_CNT(1),\n.C_PROBE346_MU_CNT(1),\n.C_PROBE347_MU_CNT(1),\n.C_PROBE348_MU_CNT(1),\n.C_PROBE349_MU_CNT(1),\n.C_PROBE350_MU_CNT(1),\n.C_PROBE351_MU_CNT(1),\n.C_PROBE352_MU_CNT(1),\n.C_PROBE353_MU_CNT(1),\n.C_PROBE354_MU_CNT(1),\n.C_PROBE355_MU_CNT(1),\n.C_PROBE356_MU_CNT(1),\n.C_PROBE357_MU_CNT(1),\n.C_PROBE358_MU_CNT(1),\n.C_PROBE359_MU_CNT(1),\n.C_PROBE360_MU_CNT(1),\n.C_PROBE361_MU_CNT(1),\n.C_PROBE362_MU_CNT(1),\n.C_PROBE363_MU_CNT(1),\n.C_PROBE364_MU_CNT(1),\n.C_PROBE365_MU_CNT(1),\n.C_PROBE366_MU_CNT(1),\n.C_PROBE367_MU_CNT(1),\n.C_PROBE368_MU_CNT(1),\n.C_PROBE369_MU_CNT(1),\n.C_PROBE370_MU_CNT(1),\n.C_PROBE371_MU_CNT(1),\n.C_PROBE372_MU_CNT(1),\n.C_PROBE373_MU_CNT(1),\n.C_PROBE374_MU_CNT(1),\n.C_PROBE375_MU_CNT(1),\n.C_PROBE376_MU_CNT(1),\n.C_PROBE377_MU_CNT(1),\n.C_PROBE378_MU_CNT(1),\n.C_PROBE379_MU_CNT(1),\n.C_PROBE380_MU_CNT(1),\n.C_PROBE381_MU_CNT(1),\n.C_PROBE382_MU_CNT(1),\n.C_PROBE383_MU_CNT(1),\n.C_PROBE384_MU_CNT(1),\n.C_PROBE385_MU_CNT(1),\n.C_PROBE386_MU_CNT(1),\n.C_PROBE387_MU_CNT(1),\n.C_PROBE388_MU_CNT(1),\n.C_PROBE389_MU_CNT(1),\n.C_PROBE390_MU_CNT(1),\n.C_PROBE391_MU_CNT(1),\n.C_PROBE392_MU_CNT(1),\n.C_PROBE393_MU_CNT(1),\n.C_PROBE394_MU_CNT(1),\n.C_PROBE395_MU_CNT(1),\n.C_PROBE396_MU_CNT(1),\n.C_PROBE397_MU_CNT(1),\n.C_PROBE398_MU_CNT(1),\n.C_PROBE399_MU_CNT(1),\n.C_PROBE400_MU_CNT(1),\n.C_PROBE401_MU_CNT(1),\n.C_PROBE402_MU_CNT(1),\n.C_PROBE403_MU_CNT(1),\n.C_PROBE404_MU_CNT(1),\n.C_PROBE405_MU_CNT(1),\n.C_PROBE406_MU_CNT(1),\n.C_PROBE407_MU_CNT(1),\n.C_PROBE408_MU_CNT(1),\n.C_PROBE409_MU_CNT(1),\n.C_PROBE410_MU_CNT(1),\n.C_PROBE411_MU_CNT(1),\n.C_PROBE412_MU_CNT(1),\n.C_PROBE413_MU_CNT(1),\n.C_PROBE414_MU_CNT(1),\n.C_PROBE415_MU_CNT(1),\n.C_PROBE416_MU_CNT(1),\n.C_PROBE417_MU_CNT(1),\n.C_PROBE418_MU_CNT(1),\n.C_PROBE419_MU_CNT(1),\n.C_PROBE420_MU_CNT(1),\n.C_PROBE421_MU_CNT(1),\n.C_PROBE422_MU_CNT(1),\n.C_PROBE423_MU_CNT(1),\n.C_PROBE424_MU_CNT(1),\n.C_PROBE425_MU_CNT(1),\n.C_PROBE426_MU_CNT(1),\n.C_PROBE427_MU_CNT(1),\n.C_PROBE428_MU_CNT(1),\n.C_PROBE429_MU_CNT(1),\n.C_PROBE430_MU_CNT(1),\n.C_PROBE431_MU_CNT(1),\n.C_PROBE432_MU_CNT(1),\n.C_PROBE433_MU_CNT(1),\n.C_PROBE434_MU_CNT(1),\n.C_PROBE435_MU_CNT(1),\n.C_PROBE436_MU_CNT(1),\n.C_PROBE437_MU_CNT(1),\n.C_PROBE438_MU_CNT(1),\n.C_PROBE439_MU_CNT(1),\n.C_PROBE440_MU_CNT(1),\n.C_PROBE441_MU_CNT(1),\n.C_PROBE442_MU_CNT(1),\n.C_PROBE443_MU_CNT(1),\n.C_PROBE444_MU_CNT(1),\n.C_PROBE445_MU_CNT(1),\n.C_PROBE446_MU_CNT(1),\n.C_PROBE447_MU_CNT(1),\n.C_PROBE448_MU_CNT(1),\n.C_PROBE449_MU_CNT(1),\n.C_PROBE450_MU_CNT(1),\n.C_PROBE451_MU_CNT(1),\n.C_PROBE452_MU_CNT(1),\n.C_PROBE453_MU_CNT(1),\n.C_PROBE454_MU_CNT(1),\n.C_PROBE455_MU_CNT(1),\n.C_PROBE456_MU_CNT(1),\n.C_PROBE457_MU_CNT(1),\n.C_PROBE458_MU_CNT(1),\n.C_PROBE459_MU_CNT(1),\n.C_PROBE460_MU_CNT(1),\n.C_PROBE461_MU_CNT(1),\n.C_PROBE462_MU_CNT(1),\n.C_PROBE463_MU_CNT(1),\n.C_PROBE464_MU_CNT(1),\n.C_PROBE465_MU_CNT(1),\n.C_PROBE466_MU_CNT(1),\n.C_PROBE467_MU_CNT(1),\n.C_PROBE468_MU_CNT(1),\n.C_PROBE469_MU_CNT(1),\n.C_PROBE470_MU_CNT(1),\n.C_PROBE471_MU_CNT(1),\n.C_PROBE472_MU_CNT(1),\n.C_PROBE473_MU_CNT(1),\n.C_PROBE474_MU_CNT(1),\n.C_PROBE475_MU_CNT(1),\n.C_PROBE476_MU_CNT(1),\n.C_PROBE477_MU_CNT(1),\n.C_PROBE478_MU_CNT(1),\n.C_PROBE479_MU_CNT(1),\n.C_PROBE480_MU_CNT(1),\n.C_PROBE481_MU_CNT(1),\n.C_PROBE482_MU_CNT(1),\n.C_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1),\n.C_PROBE691_MU_CNT(1),\n.C_PROBE692_MU_CNT(1),\n.C_PROBE693_MU_CNT(1),\n.C_PROBE694_MU_CNT(1),\n.C_PROBE695_MU_CNT(1),\n.C_PROBE696_MU_CNT(1),\n.C_PROBE697_MU_CNT(1),\n.C_PROBE698_MU_CNT(1),\n.C_PROBE699_MU_CNT(1),\n.C_PROBE700_MU_CNT(1),\n.C_PROBE701_MU_CNT(1),\n.C_PROBE702_MU_CNT(1),\n.C_PROBE703_MU_CNT(1),\n.C_PROBE704_MU_CNT(1),\n.C_PROBE705_MU_CNT(1),\n.C_PROBE706_MU_CNT(1),\n.C_PROBE707_MU_CNT(1),\n.C_PROBE708_MU_CNT(1),\n.C_PROBE709_MU_CNT(1),\n.C_PROBE710_MU_CNT(1),\n.C_PROBE711_MU_CNT(1),\n.C_PROBE712_MU_CNT(1),\n.C_PROBE713_MU_CNT(1),\n.C_PROBE714_MU_CNT(1),\n.C_PROBE715_MU_CNT(1),\n.C_PROBE716_MU_CNT(1),\n.C_PROBE717_MU_CNT(1),\n.C_PROBE718_MU_CNT(1),\n.C_PROBE719_MU_CNT(1),\n.C_PROBE720_MU_CNT(1),\n.C_PROBE721_MU_CNT(1),\n.C_PROBE722_MU_CNT(1),\n.C_PROBE723_MU_CNT(1),\n.C_PROBE724_MU_CNT(1),\n.C_PROBE725_MU_CNT(1),\n.C_PROBE726_MU_CNT(1),\n.C_PROBE727_MU_CNT(1),\n.C_PROBE728_MU_CNT(1),\n.C_PROBE729_MU_CNT(1),\n.C_PROBE730_MU_CNT(1),\n.C_PROBE731_MU_CNT(1),\n.C_PROBE732_MU_CNT(1),\n.C_PROBE733_MU_CNT(1),\n.C_PROBE734_MU_CNT(1),\n.C_PROBE735_MU_CNT(1),\n.C_PROBE736_MU_CNT(1),\n.C_PROBE737_MU_CNT(1),\n.C_PROBE738_MU_CNT(1),\n.C_PROBE739_MU_CNT(1),\n.C_PROBE740_MU_CNT(1),\n.C_PROBE741_MU_CNT(1),\n.C_PROBE742_MU_CNT(1),\n.C_PROBE743_MU_CNT(1),\n.C_PROBE744_MU_CNT(1),\n.C_PROBE745_MU_CNT(1),\n.C_PROBE746_MU_CNT(1),\n.C_PROBE747_MU_CNT(1),\n.C_PROBE748_MU_CNT(1),\n.C_PROBE749_MU_CNT(1),\n.C_PROBE750_MU_CNT(1),\n.C_PROBE751_MU_CNT(1),\n.C_PROBE752_MU_CNT(1),\n.C_PROBE753_MU_CNT(1),\n.C_PROBE754_MU_CNT(1),\n.C_PROBE755_MU_CNT(1),\n.C_PROBE756_MU_CNT(1),\n.C_PROBE757_MU_CNT(1),\n.C_PROBE758_MU_CNT(1),\n.C_PROBE759_MU_CNT(1),\n.C_PROBE760_MU_CNT(1),\n.C_PROBE761_MU_CNT(1),\n.C_PROBE762_MU_CNT(1),\n.C_PROBE763_MU_CNT(1),\n.C_PROBE764_MU_CNT(1),\n.C_PROBE765_MU_CNT(1),\n.C_PROBE766_MU_CNT(1),\n.C_PROBE767_MU_CNT(1),\n.C_PROBE768_MU_CNT(1),\n.C_PROBE769_MU_CNT(1),\n.C_PROBE770_MU_CNT(1),\n.C_PROBE771_MU_CNT(1),\n.C_PROBE772_MU_CNT(1),\n.C_PROBE773_MU_CNT(1),\n.C_PROBE774_MU_CNT(1),\n.C_PROBE775_MU_CNT(1),\n.C_PROBE776_MU_CNT(1),\n.C_PROBE777_MU_CNT(1),\n.C_PROBE778_MU_CNT(1),\n.C_PROBE779_MU_CNT(1),\n.C_PROBE780_MU_CNT(1),\n.C_PROBE781_MU_CNT(1),\n.C_PROBE782_MU_CNT(1),\n.C_PROBE783_MU_CNT(1),\n.C_PROBE784_MU_CNT(1),\n.C_PROBE785_MU_CNT(1),\n.C_PROBE786_MU_CNT(1),\n.C_PROBE787_MU_CNT(1),\n.C_PROBE788_MU_CNT(1),\n.C_PROBE789_MU_CNT(1),\n.C_PROBE790_MU_CNT(1),\n.C_PROBE791_MU_CNT(1),\n.C_PROBE792_MU_CNT(1),\n.C_PROBE793_MU_CNT(1),\n.C_PROBE794_MU_CNT(1),\n.C_PROBE795_MU_CNT(1),\n.C_PROBE796_MU_CNT(1),\n.C_PROBE797_MU_CNT(1),\n.C_PROBE798_MU_CNT(1),\n.C_PROBE799_MU_CNT(1),\n.C_PROBE800_MU_CNT(1),\n.C_PROBE801_MU_CNT(1),\n.C_PROBE802_MU_CNT(1),\n.C_PROBE803_MU_CNT(1),\n.C_PROBE804_MU_CNT(1),\n.C_PROBE805_MU_CNT(1),\n.C_PROBE806_MU_CNT(1),\n.C_PROBE807_MU_CNT(1),\n.C_PROBE808_MU_CNT(1),\n.C_PROBE809_MU_CNT(1),\n.C_PROBE810_MU_CNT(1),\n.C_PROBE811_MU_CNT(1),\n.C_PROBE812_MU_CNT(1),\n.C_PROBE813_MU_CNT(1),\n.C_PROBE814_MU_CNT(1),\n.C_PROBE815_MU_CNT(1),\n.C_PROBE816_MU_CNT(1),\n.C_PROBE817_MU_CNT(1),\n.C_PROBE818_MU_CNT(1),\n.C_PROBE819_MU_CNT(1),\n.C_PROBE820_MU_CNT(1),\n.C_PROBE821_MU_CNT(1),\n.C_PROBE822_MU_CNT(1),\n.C_PROBE823_MU_CNT(1),\n.C_PROBE824_MU_CNT(1),\n.C_PROBE825_MU_CNT(1),\n.C_PROBE826_MU_CNT(1),\n.C_PROBE827_MU_CNT(1),\n.C_PROBE828_MU_CNT(1),\n.C_PROBE829_MU_CNT(1),\n.C_PROBE830_MU_CNT(1),\n.C_PROBE831_MU_CNT(1),\n.C_PROBE832_MU_CNT(1),\n.C_PROBE833_MU_CNT(1),\n.C_PROBE834_MU_CNT(1),\n.C_PROBE835_MU_CNT(1),\n.C_PROBE836_MU_CNT(1),\n.C_PROBE837_MU_CNT(1),\n.C_PROBE838_MU_CNT(1),\n.C_PROBE839_MU_CNT(1),\n.C_PROBE840_MU_CNT(1),\n.C_PROBE841_MU_CNT(1),\n.C_PROBE842_MU_CNT(1),\n.C_PROBE843_MU_CNT(1),\n.C_PROBE844_MU_CNT(1),\n.C_PROBE845_MU_CNT(1),\n.C_PROBE846_MU_CNT(1),\n.C_PROBE847_MU_CNT(1),\n.C_PROBE848_MU_CNT(1),\n.C_PROBE849_MU_CNT(1),\n.C_PROBE850_MU_CNT(1),\n.C_PROBE851_MU_CNT(1),\n.C_PROBE852_MU_CNT(1),\n.C_PROBE853_MU_CNT(1),\n.C_PROBE854_MU_CNT(1),\n.C_PROBE855_MU_CNT(1),\n.C_PROBE856_MU_CNT(1),\n.C_PROBE857_MU_CNT(1),\n.C_PROBE858_MU_CNT(1),\n.C_PROBE859_MU_CNT(1),\n.C_PROBE860_MU_CNT(1),\n.C_PROBE861_MU_CNT(1),\n.C_PROBE862_MU_CNT(1),\n.C_PROBE863_MU_CNT(1),\n.C_PROBE864_MU_CNT(1),\n.C_PROBE865_MU_CNT(1),\n.C_PROBE866_MU_CNT(1),\n.C_PROBE867_MU_CNT(1),\n.C_PROBE868_MU_CNT(1),\n.C_PROBE869_MU_CNT(1),\n.C_PROBE870_MU_CNT(1),\n.C_PROBE871_MU_CNT(1),\n.C_PROBE872_MU_CNT(1),\n.C_PROBE873_MU_CNT(1),\n.C_PROBE874_MU_CNT(1),\n.C_PROBE875_MU_CNT(1),\n.C_PROBE876_MU_CNT(1),\n.C_PROBE877_MU_CNT(1),\n.C_PROBE878_MU_CNT(1),\n.C_PROBE879_MU_CNT(1),\n.C_PROBE880_MU_CNT(1),\n.C_PROBE881_MU_CNT(1),\n.C_PROBE882_MU_CNT(1),\n.C_PROBE883_MU_CNT(1),\n.C_PROBE884_MU_CNT(1),\n.C_PROBE885_MU_CNT(1),\n.C_PROBE886_MU_CNT(1),\n.C_PROBE887_MU_CNT(1),\n.C_PROBE888_MU_CNT(1),\n.C_PROBE889_MU_CNT(1),\n.C_PROBE890_MU_CNT(1),\n.C_PROBE891_MU_CNT(1),\n.C_PROBE892_MU_CNT(1),\n.C_PROBE893_MU_CNT(1),\n.C_PROBE894_MU_CNT(1),\n.C_PROBE895_MU_CNT(1),\n.C_PROBE896_MU_CNT(1),\n.C_PROBE897_MU_CNT(1),\n.C_PROBE898_MU_CNT(1),\n.C_PROBE899_MU_CNT(1),\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synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4296}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nYugOLIF1XBreTDYRaNSWelgjmV3GIQ3y7FKiDB9UiIB++fAUC4TXcrfthfgN8befqwACkO3Q4k0c\nvJxv/aokgQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nP86BhFBNNa0qr9Q2+Wo0KACiIyDg4VPZdSis8bLUVn6FrcCD6TyMD6qWsX7GqSzkSyajfw5KoNS5\nrAZcRWAMv14anbm7VDJCIblrxr97wW1wDK0tJz6KsyHENdmS+W0PhSl0PyC6LE8TbUq4mev1WMPa\ne8qt1TLduNZhmfYNEEg=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\ngWBenVTIP5Q+rcNXfn1zPEjuUtszskvpUVNF25Xh81JnRdMPCp/0AGJPx+mPKwQ62keEUCK7jImu\n0uCqq7uEhg8CAhGkckxz0ziMi5p3crim/FOPfZSxzcfVA0myImyw/jA25kK2gqWItxmETSoXCqJJ\nxjTH/Kdlxzn5v3BlGFnjUMmgDpw+7ZlRLWclsVDPWcyttlqzmOpUVNRybjmRjQ047dZKoaEnV7aL\nJadzAQ1SqJzBdkDtBC4ls9rDZ0efLPq2CaHSH2lKmJWzqvjdbahTe/uDqwZlM/3ri9uvioLaock3\nBYN0ATxKAINgg8QSBFGOvETVtbNj0tmio/74Jg==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUA332GmFKmVHrrGry7Cyuflehk/VbtxlBHEATtE4ZDxpaTPEmq4fqpuW3/eIdDceGsGBiaQuMN9K\nWHRjmvo00KBUbhMYtfB1gjlmZEboE2pGVM53sCnoWcRuUcFptlHy3SPD43x91G4s/5AG3W+1+WfG\ndqqfUNJVltc7+nD/QSz52JWyt2BKcwXzXUegWHFyWPlXXyRha6uiHm5A3aFVX9XSCQMUBVg9KOgQ\nr17LLKqYda/v6o1fu2DbIpPXqeviObYOGtxIlZlCKEQ0WQ16wVhC7M7JMUM8K1ajQIP6aFm+lH0T\nT0TAEilCZfV2IBv8ZeVngUGkozMdcE2q607VAg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nJkclL4oQ89VKThgpnFORp4DkQ+l+oHyNRU+cUXBcYSussbqYTJL6YmJORdubTTO26u6Gzu7Zi8eR\nCof7Krp+GgFdv/lyHLisqmpxJDZ7fQJTFSmWQ1sN09PbMajgp5uypgG17Qqsv6Efx7DaBK5bWBFL\nzYY4TfY8F27SWO7q+F4ZXrJVV+ljd3jMxOp0CO33BlH7VTdJmnHbnGwVoy7NS7ktTu5O4mtjSy5B\nim8NDWKOPmwonslxiaCWWhRcIUWJMoS3RW+hbISleB+u2f6Hv6Cq0ewXO8bpInYwlzrVk138Qwn8\nPZory2IpEEHyD3/RAkNZjAO5MGkRMmlC6knbhg==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nP0095JhTyRSuAcV3jYJyGhT1pAQ63Ikz2jcw/xarWfO4myeR2ki2IxiL2BogiBQPifhiQ+8e/taC\nZCqKABC2nUd7sP5K5FMLxqEqvaSGhMtRO2Qx+bTN2vfUmVhFmm5F0IDL69aSPE0VUYhlP+Aw6isG\nmHBHYBCtHhMlBBTHiBI=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfVKST5L4zOIHEw8rTePPdwZAh4xL2unQREo9UhjWF63YVGB1vNoHQzJFNQi2s74hnMxp4aeUGW3A\nnhI/ztVR4LEwZ7XH7wwwmLntNjOp08e4L0SwqDu4k9wj2Mq4P87tHDh2OlNiLNBP9KNGLRKuh6L7\nrvsNzCz5uZW5s7nBY60UupCfWM5iYb05yX1fiPvYksz5uEon77IwhleTgsDLGSjDpO/3MsRecpOY\n6zxdY0uNkfRy/e+huHZvIRI9Tgx9p4p5MHkKiVX5pzmTHVFHILH/8jpxbyunuxTvGsgkRSrn/BzR\nCr6wvT7hHeY/W1F7h1vfxGVI4Ek5baJkO9T+vg==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64336)\n`pragma protect data_block\nkE3zh5FB1r3vI8ZJiCJ6FWF+XzfFQVQgnzQJ/PJpjvgCXoAs4Zjsl6nmvDpPHpRl1X32r55UNGOi\nrzvS7eJCMJeieiUb8KcN1+k9krnT6S4qk6dWAtm57amEO8+SlPVtgy1tkIGJYbb8LomTrg6JKf1q\nmpnSuP6AyfZHl1hcXlpc6bd4uJId9F/xcZnJaMEQTk2Xkh0YZwzFzeJiYXNXkaANr2sFv7jst1E1\nwJT0/zDSlQMmJHtvHYgqniLGO0LTUERIJn2n3LlE+Nb1n6im8tMfUK9/omKdJrvVZAmHwm6y1KfX\nSR5hA5hizsxzuEmVhhICN34dve/ajVFv00CqzpxQcnSBCirgk/Od85aRxbLRw7wKTDQVTqkGC5vk\n8B71OWlKiZ/nHzlwZ9hkKlT5HkYDPZN426UwuQXkSdSoit7sDolGhTt4BUWi4BL1gUE1DZ/7H+Pc\nOIDFwGjTInrdA+MN85INFgXppeRHIfUeeJV6PNisW2AElJtcXF97zM77KR0g2IiTqapwRFlRAMpQ\ndmybCFy78g+H+cfr3d76Eo7sgOSPiULbuDnW5OocD16sTNjQBvfOBZ1a8fcYC0eVM/MPfFqAJMX8\nhzpp+YLA1YWJ8/mAVQhlhjc4KKcIn0RiMbw1LSTX142bdXJMBujGVnYH2QwtVCJwtuERXFtiBcHK\nU7EKh6EAIU9yCp58uJMNIub6tmkKj3b3pO5oAxbD2T1vOSfaQzg0TsmrVL6y+n+rXPnEyvrgMtw7\nDlQ8o1tq4vjKbXAMiP3VHX9luvJQB5yRoanW10HoSFcPyGhuyvBscFIWTC+BEA3hNGyk5czChKPF\n+vMFqE5wtBfiuGKEi4YBS4B6ZwpMPspnZwYf2NHSNQqfLSp1Y8r9RY/RbhF3Hc9AAXs29XP2YY2R\nDt8z15QRDaBBCVYRckMMTmGpOJ26zR/MWF3F5a9Qf5IghfFoimkitsN8O4mGDH1avgkPNpfc/5oq\nrh8goxqhDyYi9r6oAZxul3ymzQaklgK8XVa9W2wYLPQ5HVUIzH+fx7yOryc/b0XpcAYDhsiA55uW\nxPOsFmqwrzhGoEM6/sPeESOzKxGqAuWArX1dYw3B1NIRwc/SiICNy0gVTvq67BOMMfU2jEfH1zss\n907/tTkECdjUTaTA+D9QGzdlwAnxMLZS/5Jp7CaJduYxlS3SjEgCALpp8pO3FrG3dvCbzob3X6l/\nHywXPt6zQeozZUD9te+GbwL4nVBJQoDFFiKpciE0aFKU2H6IF0YZ9bQKJKYkBkYI6Lg68EPLAPfi\nHgpWSGcq0sr03CFqAvZIennPxsmwghVPPQBDInhSRM7ogh6JVSa3wYiW90Im3BjhIeZuTVwWoejY\nZtDwCn1vqNjdVK1h0k+6sZkoAJx/tKymMzQ79DNfKptG48yUmhC/F7A6bL9CZ4J0xKpJAT+0rmtd\nwEym2mskpzCcOGgRltbipx2L0w5kmRXMdyjEta4eXyFEMAzsWznDHXMv2vq5XwM0savwMfuWTyY4\nXXPdS5QFO94+jhMoG9DQ1+S+LR69rqNM/jCH6/Zgk9+GUebipjHT3BHiNgq3pjhrhoBCNVW+k8Ra\nikrBqwm62uE0Kvj7UIagh8ZVrswAyXSLIof3/bVQAJhZmB3055LH2U/4a+fEsD4mlboFaa6zet2t\nAhSATWM5T2Rxo27bt59Gb3ZUMBPTojqEfgvWWMBvawl1GlesvaxdtH3t7LjvwoXN9tdEdhdIoXW7\ncnPRYqV9hD+jSj/wDAHBKCAqn/06LxSxEo1v06AkDTali2Ibu/LpGRg+v42BQSTALzWzxmp9OZ+G\nQBOmW0FWoBr3Np7cOgqb1y5OI+hODFfRwREojfbzTDLy7ZR3RTOCEdwJ83BGogbKuZHCe4F8fVy/\nEzUHRrXI9Glt4cEZiFsJDXxf8DrBbMCe47ZO/4Vb8CQwK0Zp1ur0bGW6eZJLvm2CZDenu+smqHyM\n8cNa+X5ZWUSZdAky0ggxJvYzGj1NLWRkA3m+yU+dKGGtlf/ZyyKW8UFiemUtcK14bXza4wz86bh6\nbsEzG2TRvNc6sbZMVnkxLHYnx/xPQrWFNhKNcb16XcXCaB6WFYv+E6+GM/mR8raMgI0K1rSj7Cni\nWyKsBmpgxTKkNy540JxNPM1vmm48rjCWehZwR/BFn/eNpQZlRe261hIosBDqnVgUvGphdsrJk2tP\nuvtY6UHx4FoZy42AjlxAG9fTbwMZP/GKLN2Wn+uc6iDBnGswOQTOQl0glpbfKEJnkxuscJBlzVXK\nbIAc516dj2fAc4P8qSHMIIMMmrRtKlyoKbGUpuCdDAGCwNiB8e2ZkD3Z18aQUYjYXrudHUOsg5jn\nIoIQN89ZyPNR6r6l7HM3EmnD2I7C4nxEzYwSOaIKPYClX6pE2lH4j3BfWEH6sEd/Ff/H2P8j3/jW\nIbBz30hNDupx7kOjNavnbibhcWayZ8dsA9bmGHm0bVu6SOuXd5uKev9QnYaVITu/jLI61Wkmpcsp\nYHhaVaSFaRUStXZIcYv3VNPkuxE2az0Z9VNN0Mi73rrXGMw4pp9YL65ByzJgP3fG97U38ltLHgKS\nn5Itl199gb7ZMl0lsAh83uPfA4iGuOv2sBn7g3pyREGWaEYieHfHKq+ju38etYApkb22FnsjfVD2\ni/YIM15a0/JUEGc64KHZASi8A4NiUntFmVDG7YkPNdOXQ5BqsqprUqtMd/b17Bm0nkxc8e426Me6\nUbOlAHlZce+4uAmZvy+E4ghu6RTfGS1y2gVO/RFbNEKDLQmvXGS0//UZVhj+TNSiInw25dxsDuCV\n6utZNSIb92gOGTuKghxb07yu8yXyZy9A4biLLqaVQU0vb/PW4EP049J7YYdO9sQwrJCoeFtVEaPf\nwo2nIVX6hOpH1aFEkrg9ERiPnt1UUXlgrQTkKdlkJvC5wQSP2ZNIRveY6jHSw1gVBWkr9k0daovZ\nz0G04BIfsbm+NtmkVJ7OoDEv4XuZ4Il00Ap9vBN8bSHNO/PsMj2JNKVH3v/Xx8eisuCdeN4Hu3Xs\nzsUtx0nJQggOIjEbi1WrdnD95V5yipfY1V/ZC5V7ii5zHDUDkP+p14NMbuE9sjfsL51Rfoty0wsl\n+MoLxpOr4NcXnX7QOWmy4aGdL8C3ZikuPP00WhtKRG4p6H6MkrAttXHz6L5wCnUV4O2kGfhkhYjf\n3yQJVii52aRvT7Lv6S/BAOJFByUGl4wpHoyfLS8dLrarEOyI1mnoeOsjefSUTMceLOKuPWkMk0I+\nLR/T838qusGpX/26srrf80SWxKr7ch0YEK9xGGHAO7cgvPQTlncT37QvLwfutO2xOZT+81H22NiZ\n13z31W0LurQciFfxyNz3bOQeKWnQHIqtFv3JGGJnux7/cOP614w/LW/aL7/YOzC8F0xM3YhaMeUW\n9UA+GBxyn9FtuQ0/g8hs0RhuccMBjsnxQzSBS603FlXaUQV2FfsfMLBL7TasPZ4rIHuUWTEu9mYL\nfWz2rZbpwwfRq35JbtQKwphJScZVbTaLWyH2Isjcm3GRFrOK9OpEZwYx/HTc9n/EtRmmZFwdUe4J\nlDnueKc/fDmoU4G3+Zw6rm3p3XTOo9DXUArS/uSnCylnmGrAaBLaKnFsQKd8kCmJX12Uj/xdyOF9\nOpIg19vrcrSE0ejJQ5dUcLrb3i0Rk8eLyGew8jmMMtFOBRmqVwscepGRMPG03RMp4W3rEJn8UXb1\neP5XFWhrxazaFOY5ljiIWHk9hYQOnH/Vt8DG01HUbQNcvQH1xHNwUIooc0fbM+PgxMn2hQ0pM6+c\n0wPfDIKABiNmKLhcHnljST+ofM0yPaynaEkePqVxWiKlmFSgAsBtBcerrFImky4wOHdJwOLvldx3\n4dVj6HduJgYtLUQGVl0tI3IbmvX6s0MKeONdhJKp69hWLHhEiYl/t1cPpLJB+SUFp/r1x1s+MzD+\ncKZW7hNtDThOdBJjoeAKmavGBoh4VHBtQqDP0lL+EwpSg25V6X9XW+dFUEpwaZ0CuVXWHBtwGuce\nMaku0HU9yyOJSHRk7R5AzoBM0QCbfNIwoEqrpTgUW78VzRjekms34MQvc6/VWtqoA6IIgPs8ybLJ\n1pXEw/utkcwR/tMBVJvyKzEp9b6Dc0sotuhEJRY553G31bb6xa7Y7PG38YByPiqfJPK4AuPhcaO4\nN8WILCcgXuWL93xjqu0/Ew6z+GNqQm3Jz4ntiHysc/AluO6K7vtwO4UcS8ccMt5z4bpA4T5arE4/\nb1eHDWK6JT2gX5/4lOlR7pJLy5qwKyffyaH/Nqz7AsCVsPZi3Qwvygy7NndJ5ubyVcHxyItssjGq\nDNBwkJOOVIQtsmfxXko9LsA2I6zOgj51rqOlqXg2Gk7DDJjUk66K8JUFHjHbyUHJoAgAJXbcvFfs\njDDBZ6zps82PHgzQSOWlueInlKXLUvswdqg8Szm9Rmfe07P0jivX7y1UdWGu42d2G9+SbnpVwkAY\nd1j6kvNq/oN/n3VLX3UuBoSfGik63mKL3qmADCS+UFhJpi4xHFbwZh7pqoTDSA81OoplAD6RtIk2\nxTHfTfakM+NDXKgW5LVuaFtBz+6XsG5LuuVK324YlMwuHsdtjt6EchzSz/yYaMPHCFdNxyRgcbqD\nSIm/1x9m9ypB7i8tHeuJrv5TiGMrS9fK/EjFDH9s0XHcvfmBsVMUNdJPggy2rEwjwRnqEXo66at/\nAfc7We4AA8PDP1d76rGrBczWskspbNfVGtzLYmsuK1aMAzAGE2VnjMJ/OJqy2qkF5qntyuXtWXp1\nXYYHmfMdE0HqigV/1OZ1p6fodgR3cMw7dqDD4xSvY3zej5zcUNWAw6yrxJEPGUhaUjPtNS7+r2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fRoNqOEwbphWrnFxpR1uQtlznt7NunmA/HAq9QD0jc3VCyUGLK1m9jzfR+MiOxGkvi40fGIh\no5q6cp6WZYQE5sG2u1HePNz260XW98o1SKmGAnVADmN9oRH+kJs27wjueapaewwDVg8pnq6kJUOh\njQd0RkYcTMItDGvp+sFqeIIdADsTHRvr1h+M+pYqq9sLbwUoz1Alak51hZNlSXhSEVXzQLkppmeO\ntB13Z6wglCy2BICINwlSr/7HP1cYop92mfeTXL3QGuFjsDOYJeT9Igcq+fS6YIfWCA08MY5r7yVk\nVPB84f/igRg5ddrxoxTIiw6w7GWDOhG+zTxF1zyp5jJA3yKcpqPzSQpf9MKcNt+PzeKm+wneK6Jo\nhpoN/97lq7oMjwcqj4fYDI3pT7J8WHKkZCIdUVNrv0PtjsuMpkuTQbOr8hbWLJNy8UKFlgHOcfrj\nOvGAARiIQRbgB0ehYmzYwrLOYCEEGz6BajWpYh+QjcQz68HI9uD0KJTeFrxECsQhCkd+nhXmR6Fd\nTuqTwMlfvUxKMpfl+zweX6F5NmHmeyPDY7Z3diHFdJVtYNhc+jcelDo1qmERGZj0HjhlAXvpn27V\nveZu3AVSpka5ElIwtvHc/TpRzjvbeQHF5yFv9E3VhZftw6+ajD4mjDYjGCqQeNasu/oomGN+bD06\nLx4hi4Wsc5ABDp9+84vB9wTN4vdXWfDxjG6e8iiMfWuezpQtLWJtxG2XnhaF3oXBpRIS2VVSE3h9\nz+2gpVoEZT3vzJjOS8nL57iPKloZn6rbf5gWqxxUAtYbGct7VUgqevGHgWDGl0dAqT8VpJaQ21q6\nFkr/uOy+vbpdI3AICEPSgGKQQMnk1kAfWxfgJ/kaxhZc4f5XlC0ZGSh+C2CWzhNE/JAksw0YQmsi\nne+rOYuBn6qvg4VY/SXyC6jNTUu4fEhiqCBJKvOpstSpQS2jYVyQK6GIEoOtvRL+AeqOwN4ylvak\nQVkg+2A6cwY7T1x3wkcNeZMXbEpORaOJMy9wXl09aJXky2uN9qgpXHXgPTZNWf+saMNRN+uBGVzs\nZjhjfEYYTVSnY0pqS+gpfbtlNOxXo7TL8OvbkRAThNpVfqwQtupoPNk2HHNbdmWP1tZGcqPsQf6c\nCPJwuj8fcPCQUh1HIZMnT9DYnr+Z1+9YVL/Rz7jLHyA2rFlsPXsEC9hUanPqMe7CAAEbjTq0PKon\n6vcDhC4OeDhfHkwfTiOS9fxMjBLTcaoTqPWTZt8ChH4gnVvPWfUBK7kvIhw+dKvaxIvX9bk/BH/Y\nB6uSJzU7imXZJLx07cEcU/6LrWAx6BrPF2/b6Su1t6eCb+t1Q3QZIS/1RXup1A8KEnaMO28WsZcw\nZQ5vCfX86ljiIl+HfGiLBpKoa7+SdP/+q0BolGpFDPCce56LZLDSOjBraFCS81FH07TgMpEW/Koe\n73WJ43JWWkZBQNZzN+JlfWtwo4qAocwsQJX0w6MOAIE+RO9Iwh1IPv1zbtcWHBpWy1yK1K+qVbiT\nkI8txebAMYWE1fJJdK/cP/tTZXiQLhiPzBsl9ezZjJsjAPcq3dbWErzH6ZEEnAKTv6PShy3Znw3q\nOT6++Nsz6N/njj6GqwN1E2zfnMNA9tFHXPkjpOfSbyTnzGEEZwPile3fiO38kzzHEjoAkb37KavT\no8WtZsohsnfTezPzzWxB9cFMtrTKv+u3cIIlr3mM8PZGdN2ZSq9ahQfTqRYp5KGtKnkkBIfsbqqM\n6M/SBVm5RMtrKRYp3/ey+lutDPtoUKLWJMnsv76her8S4uek1nzv4wTizdqJoCHy04vb5HAcgpVC\nfcWHgEVDqREje1ZKN9cggmiVpXRsjmWDBU/wAg8c14gohHPFlXNZgAA+ytO9js8szFDnt/0cCj7Z\nkDd0C21SAR1LHBI9KUf497LL8Tu6L6XEd7Tm3XEXeAS5OgHmGdAHyGPiqI9u8ClEt6BkfXamciI6\nlfeQj+z1nCxMPEJCjjzMwvV+3Ah7f/pMVMzaycr537MfD4P9+Ch+Y0vIsYpwt4zU/30BNXnQqfs7\n67i6Wfe/ptu3NRiQFhoPNGZytUbv/evSNDXxFaqwfruUEUqn0eUopvcwacq1XD9XaRIAXBGNpSoS\nKKesrN7Q6LZ+PG/cPTdT84w/+X0t954GdIewb65IP9dwf17eYtg2FQZyM5t0f3iNHe0pojKIaM1a\nmcTIJ8FIFYHoORq8DSEu6tyA3X53jjGyQRjVmLNIZdZSbRVoyoBsiZ36Zh4U4aW+U1leOK18co4C\nxLB2Om7MWuPJT3VKJMuG8psZ0iW9z0Zxrl1RyfZ9Lk3hYM0VRdpLKgxqEDiEeCVqfhlGlFXUj3wu\nacVLRH6dhSEBumjFuWq/lHbTsYfS2PGWkPdKedT/skbFeOsHLU4V1O84M8q9+qmppce19MSMwXeO\nQ2jn8v1qDqQoaq9r7Jvksqp/+A8wClhvUJmaqnTcDX+MLOJSbHG2ZNR/3PvUYpDVUrL6FwJJEASQ\nPfeLTPm7SGxsfS/ZVEf5pC70NwkE/6UEcyIx7xiVjxXhDxpA1pBvp9PRueOVwllHhE6dRkC/iGjc\nY8YKShjZxisO3URdOWXpt8F8PTMjnWoGzvbX4aIve+X5KKntuaYeQxKXCf8OJaSDgRc27KSBsG77\nFYG6/6BcH6AAXrtXc/OMZ5Hu9pwGsV20Zxo2xAGLOFRpmnHdImjGCwHmcTrhQpQH8Br0AYr8Dchr\nzb/JJoGRA3WukUlj+NanwbgVkpDoHAJD1a4ftoDvHJVleoDf867gupHQThJhVF6z8LcDtafpRVrE\nSHNxS9sSGI31+aTuQ/0YqhEiBI0k38xXFesQY1mW/zireb4cohUmw/0Nx4uTsUCRUE3WLfpwBeb4\nMp8qasvOM4Uf9kQqF+GnmseyoR8jF+xEaBjyzrsJ7WpU6EQqH7Cs2y+0nkw7vULcWZ7PtxCkTi+y\nl+KY1Ss3um8ryMQYGvKj7L2/zAzwrarkjBW4JAtWsM1SrwqZe6veUIqe3Z4G6jiNsQ4NTDb8oypf\nuYa8F3nzw3hTgsLTGVQU9pMPE08BjCvQKFqc57jBAj6RXHMnE3TWWc73XS/zYTiQ/OmvpnxjZ8lu\nvX+/r/dA5KdxINswaLmFPw3KzzuWJBz/nVwLRbAGp9IHQYa6bgjjJRm5ZmLKGmzzyuRrQXUPKOTn\ncopnuL/JvlWnSdn90TMc2Tzzm7TXaIcgX9EDepTRW4sN2XWdc4AmncQYlE3Pc3mjMKKgB95f5TEm\nSgoHGZwRKlzoBLvmO6GOz1aatdeR50BMPUt7pSJwIgfBdLnvzstov1W42zn7AgW7Su/pfCewVOQc\ntZ3KuOMYDHtAQmPMuM620hdwLoXkyIatvRSwpr0SFvGi6O8B6kQ+5QxGad7VgcpGZArl8TiH6QY8\nUrI26KJkzhP9OikTZ6om4ZAs0bloMAPotwByB7KXegEUUn/G7uE2JTlScgVp8fNt08IHyAO9ubEL\ndk6s6Dfr0H5HdXOKdMAGD3C2jl0fudKu4zYcx0s+KraQSQgLXI1G2qoLzPeW4fGtztn4k6iTlSBg\nRGAbX+gnK/iuGfb+++nrxTBI8qFUX6YIlcOAkg//OSKGJJjat28UHn7BITZnedR7Lf2K2lu2q4yM\nUFzK+WcQU2KYHp8iy1VQ7x84oZsD1hpSPIvo8xCeiXIPtrxEHjRh9OZp7jAHNkZxhB53ii81SHB/\njEzrBHa4MLE/6WMisOhbmjPDUtQLtgnO86q7gzdmJX0C1jvl0VzQx+0ISJcZc1limXckLBS3F+rI\nMi8MGBfMyw+BygdEr2f6yRlYvJdRZJhXOXmHT77UlUuCfmArP6UIswPKplZN7Q+XLflYU+I7OUPp\n3qMXyzrC5ko38DucoiwqvsXMSMVx3U4vLK9VKA3sPt/QP1E0S7tFJB6lDoYQbdTI/vUgNy3iAmmw\nLl5BmdtFBDWdwEMFan9pvoDEbzNfFkIUBGuzvnjKtAFBwA67RYWKtqglvto8q74Btd/PMxWugAs2\nRDrpHJWYNh1j5vrsdRj6sRpJRMQ9FpQRBFbz8fol8FWWJFG0S8M+zbG317tUs/p0GjHB+hTwItqR\nv15KlK1LZfgIy6o7gd1a/8MIRTXjAVUuVviJ68d44vkkJr3mh1OphI4SBhUhzOaf+44CoHK2dorL\n9MyTI6q2dacNJIgHdhaJF+ebOKOMQ0olKCeLvE1KmN4SbPr9dHBv/d7cupOKbz1XYMcK66m5e/El\nRWsYMbQf2uawzWEs8cZBm585waVMQtfAQNoE7/Rs2/2SY+vnUPguioY+EDwZsTxfJWkI8zHk2a9+\nrJrYuXiNAW4sd3i5EDq/+2Ak2GPpRmfpxb7u6NIBKlwXugW8ktrqwlNqYCtg5vVaseU+FGNiVsvF\nFIuNWu1U7GpZ8HtnZu6aFs7IBPIoYMl7vu3aDQpZG9I7sSkjhPjg7s+ijQIJ3BGlmyuljXClWhZL\nJIDVQLnzS1pM0pvibM+4youBOCPFCx3sFuvQJZk3DpKOy2HX8XmKOtbKgZHL2FBjFFosaGOqcL05\nIgcxAvuqHB/0PhosWC4fcQy9X0ohWgMLrtpWE8mEqH+l/idgHAn3azKZjNDZTlrOZEPh5Y71cZak\npKgDUjLW4WthFcIERr+HL9L9PI43LQ0EKDsQTa6UW3qJFAXgUMTYgZtO2S8RQB23wPZI6bncN69z\ncEU5z6OZdFP2CgLvdInA1tFbRhPanE7dmxgxqPwFREzFyPLMwVsw9YgzsxSxbhJODZvVY1Bp6C4e\nf8VmwXIAZt+OfsTInDC+dttMHHHCvtu8TBUbI+ZLgsD0HzsESIpV/BFvQsRAJyfHJ1Qu2kByntgu\nauKads6lHHGN1Tz23/hFq7PVfLwm2Rv+/yx5DUv8Uj7PLsaHqrCdZkVzr0ECfIwPFt7nW50xCqQK\nxMu8QoV4cuZFAJzIhqj5t05ByOQPFRcxOQEfZrShvvNR9GdpYtghDBF0fU7BDHiagP5xDQ+UrHtz\nka7nRo1FHnm5QoYRJoEBABCLmeYI2KoWtLqx/CHi30vFLoru7CkCPX2Ll5A5mIHnjWmu/VKJrgNa\ntThK/it4atG3Inp2n1vlkQJQNib7fEUdfuFjiiCQRuNtmJX+MqELiPQnVEY9VWHNKjBPREYUQKnP\nJkfsG+QfkgAOqxHLM6oCfy2FFrS9aHOTMK/+PdNJLxa769Vi1zeXV0kwzsjTsJp6LwEAdQ4xKPck\n5bRahBrDgSJfUTcQYR+fbWtE8OdbPM/FWuaIc9SEfNMEebsH/lUKGSB86OWHZNz4CMk5ebH3R5JV\n6DdoBjfP4Atab/RbwcQqnZG0UdOPbBy2c7wTzqK1i+/C1l3+nDVheGhizstvKZZdm6XehGdOgf90\nOPsGrNckYz2jn61FOH0PY9mFh1FLr+59tTVOFZ8+6G/JJcGGo8HJhb6b5sCjXHSsT78/4ldD51uE\nJDiwF+PKeYLd+bhW7XjkVvG7+LYAG5h34M4tD8XHnDUKzWkpzBJ97ZFr8lV/euLpwJ/XlVImBXwp\nwZCzDdGwiTrZC+ogqcsGqoZxLQ0lv7VhpBL8skkTAYlBc2XQufABCHG+gWEuy3TJvqodDuGo0iZz\nQzftJFbueGn7t2+s/eYkOYS6arOhlDNJX2nYR5xtrB1FbV8m+jaHEiJbQc7h1G4HB07HukZZp/9P\nLFvsRYJ6uqex6hCbbqMMHQGrId6QGSH6/q5SVMSgN2/gJFrr5scKkIFUDU79QyiUDCNwsC5hwA/Q\n52vnU3pPU6vXy2f5Q7ZwUWdsJFEI6O0jxqL+Ga7+MIwsqnVb4GlFZdjTH+jRLEyw039RgVDhgKFx\nliWSLpSVpJs1r/645DGyzIbsFE6cPjg38+CcoAWYla+Gp7OtVF5Aqtp7iC2fGffTn7TvJOPCsVjY\n5MHx5QGSiT/mOGO5OVGVbXQzgTu/3GVWMajEmAq7T3+Ddw+yw94k9rT6IDk1t3lnruZSEJTPTyok\nw+bsJPG7RO6DcD66Igd1WzLO5JiNwENjJVrvbbBMYTJCgVPc3hJvvFQvfkLiuZsa03mylgBXKHAX\ng1TT+hvmb6ZTIuNi6x63/487ZXtXCLFNhUfNlssg6Z7KCyDb+mOiA/8aaC12vb51w7SWXNrmZCWd\n7wJVMUngtcinyUXoTuPe67Tbwu7Y3zQ3ZBvKMzu/YFyR0SsSeD+/yJ1siLMoqudSse4aThJOdPbm\n/YEW/tF7aovwdtXP+40gIRqfPjqUfFDJzhIh5XTJx+5XI6b1ZNJdT1+zC9ZCv0wpUCNzcYDWP2v2\n+73X+DI2B9Hk+GQUz/uV+HUBxDiALLNqS2pBnu03BRN2K3Ae6udAdykdB3XrMGU3apddVfl2Qzxp\nIMqedE5qxJzRw+S8ghl7CQ/HLPmeR4VLqSCR+4vWCWIw/nWGOStxbAxslLYMvqSQqcOh9SyzCdy4\ns+S2RDRsuoiRadrTnFE9DK9AV7YVbx1TL/4UsryqKTyD6TZgb3LhhYOUcpIpv4eGF6c886m7YxCy\n2UDtdlk5mzEa450taWmN0KN6rx09qVH7bTyCrbrVUDBIPLqFlGt6zsHsfsvCJAI3c9lNyy/K4Csx\nnVy11QZ2mZmv5FNhUpC9/LR77nEsEfKmmY+ZvmK6ZHudJHG1/VfBI8FoBMT/fDIUDwW+BhOel/Mr\nViAUiihouIkWJnuBu1qd0eyhHAEwYLpl67lU9OZtC+Hw4nRKD7xL4yeaFxYMdBRfHT536DpZkC91\nDyLn1w51UXVeDMGmEk5w/suYHhiKKlsSF4c+HVkT4yWcG6HjE+nqeKji/CAw5c+5piMrQDdaQcJW\n3nb0iIj0gXRBN+Eotil3B7bIpwe2t+faDTQec05jrigHMr3ZgWGPMkTWRs4Qir553sMKABMSYkcR\nnG1bX1HCd5Umeid7Ko9w+QAO4nPsP5d0GRtDcIyTVJxEMoOOJPe6s5d3iX9a55AGR4JeQOBinV5c\nvQTaqc7NHTeR4spVOyNLX0Vt4r4xYeQPAv/7STKb3KraVueUbYH++IptBnYURSH+JYRUgLc3wOAY\nvaIiWiWgsMJN4S9Tj57MZ21MxkcOD4n+daasVl9bXICg5bV/qCKv8GLgLa75Lmkb/q5ZMWqIh9oE\nBXG7qwnhfQdr1GBfNX5e2CHlpmAsJSuPYxfplnTe9x7rmzk1saELs+J5Zod3BW8s9PqEOytiKyFp\nNgIyYxnpDHg3KfkpBCzAqsNwFrRhkG0cNj6GW0rXcjnK5XVsm5EJsIpUIuwUUCM9FS4M4tQvHqzr\n1S0Rwfa/ZmOL+3kwiLwUF5yWFKNs9N2uwmJT5wYI/8PK/4X7jfYBxLNFiM1d7/Ot/0CD2Ygqno20\nGjj8idQj+8zcvopFkqmlICXcCSsY1CN8ytSbrd2KnMUs733/3JrtKjQJchP9IvaMZn4C8GZRjQ6B\n2FQEh8t7rEVQECSOxQ4L5fKxi4VjvlFFV5om0bkmX9dxai9YM/IwxOrmiEVbScRlOGYie5dHSd5V\nk90VtMGSxisAx3kJM2aVn69wCxymu0VbpXmPT+80tJOSJSASfShtKF9vvaTCkQlfQzw6bL7yoPjh\nwEpRBVB8nS+srJxgzTpzxf6kWSrfKwaXXevwejax6otuoFF3YEUOCVQgG2aUWnXPnlQBNC9MPtAr\nmChzvfkMA49tIz4Ra/kpvwGya9myjGuIQ+DpHiMvJrcsopWNYHjXYldeCzHaIWvnSOHGMM7nBGD6\nboOM+PIpyOs0dw3ymADCy1T+tsTasU62qNcuquHRip5asAz3bozJHUulZhGOlVgRZUNdbA/meTnk\n/sjtLjzMLOoPyFtPJUmnUvTECUkmGukcIMhdEnWfA+OgOzrM61GTUK5bwGME8XNRsprWjCchp57f\nxii8cEiyhO9Nm1pmdrMnxiPCjIW2WSFsnp1BUNnQEWDbigo95ithoSdZejaydDJCNHQMVMB7BgbH\nJVUUva0f/ZGTwU3kz+FTzsT6PT+E2GNMZm6rzSz1Q3yNoH4OXUbJwQ/vRFtTpicFPDJoLzVZKQ8T\npYc5LFd897P0DLzZ8yT219GrhNpk8PgFDRC+bylWmXrFl+BbEfkaO9VEr+LIfaNoM8p0/YLHLo0l\nMrvk/FTzdn5XhFvxyS+Sky7a8fU9qLu5xKvwZGoA2MbCvP/9924WG5xmAmsvN7gJQ5JylMq+lFvT\n9vBEEkmXTi/zMkw0f9CycHzh0eBomR3kzWnpWRJ8aBj76yXKuWdrSZi8qbVdo8wh8eb5xoIV0ir3\nEqgdL7Zjn1IcBmqhcr3AfwkhQEaXeBA6hqImHgPIpyxviqMTA0xjkebO9YGuzZAUIa6uCCzR8XPj\nbYJjNkm+wZNwzr79+h2XV6wDs4JS8VDdZcAVCwvmjHY8WHHb0jZTF+cMbLcUDsGNXONUc06UzHa4\njGjOviVfcTwRaVwQs82CNgjt5OHwna+Fj+b2mGBEyENynvXGlAo4ECvuBzpI8LU+ABqJINwvANwS\n44b0GVEJNVekwlMSByybrdYq2Lca3a9BtZmGtoxI5vIDG8U8CGIe/HaNFpFIvuyGDgYAGr2eb2tc\nhbOnJu4LASxc2GdEl6I0f/Z0R7seDGa895BuyGGcT/HYktcCq70sTyk8r6H0klX8wc2w+1UT9sPp\n13PTlh3zLdvGFzKPfIx0Bovn0nIoViJ/W+tgIbtcCnPhaL4gh3QePzoLOGoIWzrZKrfXdQUkepGM\nnGqctZ3+0XpR/XS7seqRDlstOjCXkPam6oFji3lfLKqM8ABKgItNsWesmVaCeblTHDPu+zmR3Swj\n3XSa7hlf1r2EC1jqZ+oubGX9WZjOz1p0gsINsM9ZgUPOKlzt+VBwtUQGbtj29NqAdJ2m+hFTMnXL\nwnUTOLl4CkzQ/3PrqSxqEMLrVcMbDav1VqHyySeQ9SUXcPePCnXTp88Ns0q+RqrpL9STvlzfv43d\nQWoOfT+y5jzqBr99d34ltSn1jq5Mk5kfg331aVBVDGP8CPubrq/MjnUyQ2o2sw0VX2JfGMN2BjHw\nfFEQGRoV/qgnxP+Yg/hdQHYj+r8qrXledHrHiSIHvAPs4IQgUCb7GIaSaT8McI1pg/MxpBTzTrLO\nHedJ4drTUgQ0yZ/iYK1+QT4h4+42fAkQ1PTj0z825aLEk1E6e1O4mTyuokRi5lFL0i4Xo2nnJmcg\nY2HAeYmkS26cU2mggoFsRs/ZxkSkF1qMN7lvHplO+1XTHO0DVfLkBuhEnnqTZn8rhmPL7cnoZaUH\nZ+WcnLY2VJJpEsl14KAieVLy0ABlPd+RP5UZna1k+42P6i95rcEg3jt0xbOAbrd3GZ10GT4chHwX\nZCLWJjslyLcbPGL1XdWjgDMZ3dtfG0z3hucdHb6/ueD5YQwPMdQIir9TjhHok4WPalVXcz9OwrDv\nkkUDrWxC6S8tuOFRsk6jqShA+Nv1loaSF+IqNB9sfeSGW8EsyVZIuI1fnErGqbXf2i3DInx/KFau\nWTBKYaTk6krZM9fG1+OzTGuQ4ubpSMe6o30MtzdVl/db9M7hv27LYlU0miFi0OmEUVGOOZDK+gSW\nYVlr43tdFyGvXHSuVyUe8+IhswC9IOCUS+h418D19ZNCQT6af/VQDeVmfOTnnZpP6DOc5p+hPFvn\nn/ISPeLm5qeknJULbDWxnHSxTeKqsw6FsTlJo72ZuEd1zLdA0lJqNxSH7YKQEawd8S0tE50OyfKP\nJjTDQ09tW/9msny5f6YFRscHzIbThNRsbQX1saPn1Gu4rhrY5lijfWRBI18U06gYijFIC5rZDP01\nVBYwmOnQa+ODOGfcUiQmM5pZVc0/4xmoHedHdwn4afREXvUzDZpKM2ZwPhNdB/Bf1RFqcRr9sgEf\nIub20BMNkJYzK5VVtGRXanivzfdoCbqJo4V8P/5J/jpsiDuZrb6BRaaYsv6z0mpEcr4RDQLHVkHN\nuy/UCVRX4N5yYskMUYbh+yf9ItFGH9xiMcWEvuCIcyyyXxQdjN8M72SBJ7rSGqi/iT7lD6zS9rCt\nQ25SxFqFjyMFb3/PCyopcf+doCoAKth86socVbKc8wQxwpfsjnsmDg6VfStQW3j6HbTJRR6cBKWg\no4hq5QyH4OzFyrWlze3EVjvAIRNo80YsifUXn/YmjqXkqejTAMs5rvnQMXvCCx5iTbO8GIqe1ZIO\n6g9nf6cdH8rgKjU2irIjf8wuR6WdAKliC5HyFO8HHKQ+o6jDL3Gp3V28RPoZe/ggfrNdJXuljh2p\nxgmoX0sLC4F1b8ary0X9O5Uk4Rm6NbJpHEMhDyFLk1/DSblBMxjOyWf69ua/+JJBU1aCUg73Ef5C\nKAF+0i0bW7wQ+1F6T3OIrZADAm3G0/7kCMyEk/pFhEeiyRgxWwHJyu8Lq3uncIQ6F+BT7fiZp8Lb\nzeD7TYdel7zVmCJayJKdXAqYfe4tHf2ggNiRQtb6rW7zzuDWxC6j9MOehd+wYLkKuWxcheZiDDGY\nXoW8Dn3gDgb6qmAR+aoQ6SUd0NHC2KkR9FKyVg+bhUh+gryvAjrRb/wdpK17v8W0/2ConYAt5qvV\nSx9opD6CbxukzGkKByTs+VXu8lWI81F+WVfosuLsrM3FC7WwGAbBF9jP7DkjemdKvZgK9sQ7+E/w\nykL8i/agCWoq9h+u27h1mXU6LVJOUIupwTkiLc4gn+eMXDqL1Zs0XW4Ft6C5zRmojOAbLVdpcML9\ncO8kViI9Uir6g48iHpcD7UCRyJ9cYSxliNW/0Rb9paOHITEcA0vN+6M2stDiWjLaznLsiRPKqFdo\nrfGWs887UdLqjo8r5gfiIx3q6dJCU+McJNwPj2I3Jch/01qA1AnDeFImKz1P1Q3HCe1YUpwzVdVf\nPkhvqIK1pUei69jyfiI5P4YZY6+RsP2tTebP3EhStUcOU/D0JIBRQ3VQrJa7Jzg7XWISFhF95Ti7\n3z2sHCcTzbDUqq+3k6gp4LymdHgAeI7RRHTNZ1hM3gc+e2Uv7wdyHBjADM7L9XBxGBNcR4RN5X/O\nwHBTw2vsQLZ+ETCgA03rkxnuHqpDB0M1lN0U7rKFUSuPu3NDS4bkCedhAckj6irfUrxnUC0QgoTs\ntFKAHU4pGb6keU3Kg7myTPkUugg3IWlMW9CYcpswzcYlzxnplzkXmUsTb7yUni/FzJOxd2qE3yTt\nWQa9KaZrnpU1W5773WQ03FUrxVsCIZefTOPmIur8T7txGR8gnCqsv6QBEWRakWYYXlNDPF2o7A4r\ncVeo8ba3lyADQB+lGcry8YqZvA2wzuQ59Ct4i0KA9Mb2LF9KQ7bB1/9OTdfRZWE8PslluZPYlEzU\nGIiorzNfpWh8X4UZP3wT2l3N9GODYuwlA54ZzhLwHUMEGM/utYMeZ4VrLFEqJHjqnVqVqEm0obrN\nPZqP5mgXq3WGmC5pYfblJggRYFU1uHNmMHxPLzFUwLZgD7GeQfZGvj2C13G3y26TPQRTpuhDb35A\nvsAETZta7bv79C8GhKUuszAXdEQqSt1AoFC0iB1GHCSIayhEsCwyn0tZAjwF4K71go9RPoIkdhxL\nkDi3AoLRdpPebNp0ZkA9jEvHY5jXMLUERzVAQloyXoj2mtsRNxGVEfImCoMq2ZVf389ZlS6517uC\n4F4WcDbMyf0BmdD6i/dLuCSP+aCs2mm8HWSoppsZuy2SM+34/m/fZC3KiLWa61trhcRHNacVqLWM\nM1ySVSUKbL8qF/lX5NNiyWlQ/hIKgo5zbSVAjFIuGdhB47cwhr9qYQOyQP4KYaqkT8bOk0gV608H\n9Su7bdsKfB78LbLtQvLgcdNmpq12lLrtp9JGg/aWPRjjRaXmzfcImW6wBiDh0AY6WYpGq6NDGwpA\nhLfZGiij/5kgTLLcNTwUpioAt8QzoLhp2p84Ra3LcHOeoAkKE+yMQ4mK09MSzL3P8Ld3KD0QDPou\n1mkPSzbvEsAv4b6WlnAkHgE2C1liHlCCPEIbY9RLAAIFGGASnOKMf/JBTcFSO9khlVSyREctfL/+\n+2sm5V5I000OI6HLT4IQGxsyKIQvLst4SWJd8GdsMkxBNNQIYLCFd+M0FLfYVnhAzTiCmhTAdxgY\nRnLY7sYZmGyfqmehgJkb1ErB7sPfr8vyZ0Z0qTGm6pysX+dmnzDmfCExQjMKu2kaH/Jnkf/0K2QE\n0mcQe+kaAC78lUWAaER1hQxg/ftOI+igRhks1sWXY8MhssSIc7iGfYiaSX5yUYwzEYIHyeamk+D4\nBGZ+YPTRPzSmZn6JHsKxCpVHspJambLKzdn9L1iverJbe9RBJ67u0pDof6txNi6q6cx9UXuddpCI\nADEaNB0dJMRmsoCj/fzzaSGw17nmnS+BC3WaBGJJ0aCoAnc7XqxprYwTNjCwcfmnuTnz1ll4P6KP\nR+tCsMDxVPxLH/eOccJdv0WR697d04aU2f4TlS+gELkIjB7NOCRbsRGhdrgC41wGRaA+u+ADhUP7\nfgqEuPYH+Xlvsr5QZvd0mPJRtUhqeR2AuVxy+G+kreN/F08X6X8tMFL6Avnl939hF6Tg7+BCy/Kx\nsrsD7ivYDRBQnMEoH7qkapYrGwu2L/ehj7ukBgOh/3Ejp1E+c1s1tWHeKPFMNpF2yx01Jy+5AhDZ\nPSdTYZFa7GgCvLmaicDHdeUnz3cvuYB2rZDX7nVooQnhB8Rf+6UTzaLdWwGrNu6c81vDrNUZGidl\nQpQwK1Ec1ecQqUWRK/KRYcg6m1Ot+IeGKFnPa/63sxwZ9w5pVjXJPGPrKvbZa+Pia3+MyDaMUQhw\nBm7TiPETp8qNL5v2hc4ybZJ1/NoEc6gdnGO9J8VQT/rE0pdpllH9k8vOItKpkEd0jdM2GPJK7ZuN\ngT4VCNV6rhNPeauuN4NuXgK+v3g/K4wTktuiZM36cOktYWhuiMZu+ZjnMmX/A5QrpZY+t9Xt2bxy\nbHncUMvFL14jNC6856bBlk5GSJjHRntBzQZMCIPtVN/C7jb/kxC/Q7mQMrWGDUbmc86VpIqxeQJW\nzEbg6DHJt4qOKlU6bzOt8FHPe3nnL37FuSrsjXpMBPVMzU6CF7izUOh5UBzaFpu5fbh/g4VrqznQ\nSEQ5WlWoVXW4ZN/ojhEvPD67BMdowjFSWDwe9HlddgB5BC49PAYRBh+jjeP9WdnkJ6GMfTXpMvgJ\n26AvgS3NcETqckZHSEGXEL/OPVvIwi8nyhmM/7l2ITTs1PcfqQdiKkc+COW6I/hfYNUYQTh2Aifb\nDt5iI9OZplitDHVxotoP5baEwDpoUsYSWH4r+9DsqjnnDi7BzEOGahmcDVhlbI6rjq2uhPt+/p38\n+LkfOBeCYUg9lxYke403tx9nNLtpnFQ+qSkNG+pUBDWPYGdMnrduCCwJnxaR20CQJOegEZCtYDGD\n2Pz7oh3uP06B+ju74IrcowxofXDERrXjwd6aL2u1rgWhjNv/qvk3swUVmQ2VnYZVN2u1qvFFwOLo\n8xArvHTfDmfdrv+mnz6ewWhBNZHVrK6zR44f5wUhX3ohSyWzCmey+ygAmJrPygJtZw9dvtjXPfkP\nmq6gwA+UUZ2D/1HAOpktggmARU0cJShJJl/ZQbfEq82hZjpZo4tj2wQquzt3CtJJ1biCnMf7MQLu\nxD5o0THKOO7mjLvlVn1vM3tTUc4TgSqw79cpS2caat1pA6PVms/BbFd7QjoHad+W5Vxhj/3Wdva9\n+rbOmR2Hr8d3OazwSj7QDN+4RyMmE12o2q4Wn8ZIxoD3tJCCKuOhqSWPDKASZv/IkLTin6nfXule\nIs2eVAEvlNHa3yVruUydEwXXk81lM5Uw+tSdYhQuqPKwBTGysUzTYknJlqjnyiJoXPUd9YTrcDuh\nwFtFWGr8LHDBhe8GRsZMvaYVZ16IRpnWVDZXGMMXqJNZhBDZMowW7UiEdpYqEBpvKHYMG5ASHsOq\nH2eZFgW7h1wB2fWRp3zq+htPMYw1HPP+PNgsCtaRQubfV2+g8YN7JSdRuJVQRKB7HfbRlfal4MbO\nQob2YcOhWtM3Tkow+j+pMAfbns+amYldYEUnaKZZKXgICtzUe+8tc6c9xgVYa/sNKoIeW0nQBgNM\n4rCru5DDjI6BMNPTgpTdVNWaZG8SR5DzenlSrkXBFykWTQ4LjxfY9iSBnutE8jbzjzwPekKq0wC4\nGfTVpOKVUaTaZo5wkojWs42LwU+Fh2ieJ0FEh24ZgSmFkbiiKAU+zrc3dANLGSgsgvCfVs/nP9OU\nJ1hObUY9Wo98gIoZr3Gz0C18ojCwZEb/dDxvyJM56jypCZsl61dYEVTjoW4z8i9chA1Mzbxs9eCQ\nB/SAYWddeyQDiHx6tFAi0C5AhuE8RktZjQ2yt9UFiouVgJZ6wAl/my9J6gKj2Am8k7CzKhlfV9F/\nVXJXNDBDxuDiqSec9vv8heMTxQL2hvtaZRbS4Nm2UH6mj2L5VmngiqZpUahulzswui8rW1Y4Wnfs\nKRTh1jiCT3mA0NfnDcq01KTgR38nkQ32gdQ42NUQGHAie8oiq3p6WSea/2JzXYXpKZb+cH45ODro\ndyUi4j/yaktRND+QJjGGrC4CC8qT5iwirtXKo9X67CllayE6G25mEe9A+huiY0thk+QYib0Lmnk1\nc5S1eJxEg6Gq0HMfuOIW8ogQTs++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qvZJ+ZCMnS4whysx+BCN7ma6YkyIFNzyLTBKHcjS\nE4yr0tuw3kDPz5v78ORBOVhPwizhH/dYdZV6B4mpONFDbGpxkNkVK9fLeTarpzCabmO1Cn4BjkIp\niiT9kovJnycvCa/1N5GHTOyUxMQ7cIlR8GyuJ9G9vjXMwxgt/iu6Nhs8Xf3iefAXLo2vTG778wZG\niKCTTviNxG6RCk8eWCflhdYo1C27j+Rqirx/r19s5oysIyqAS+9JIvOVLIg8jHsKyFqJoA/bNCFW\n0Ygrq/HNoWa48zWRfKr+os8ajBpjXRLOUeJhAxUEyFZWwKTJX5nTylPs+PHtuQ1bmgj4YfnGYxvl\nKvPBm/3LmGttISWgPjv3bic5rgM/YbQJWlKrDbIbTkJM9dGIVqw26kNaoKEGhqo5MGof42C6lrXE\nqRv3QktEZnMKBxdGhro9rM+0/4QV+aqX1Mk8X2EShfFeGJrur3mnwzkou97INnrS+JcpT7To5jQU\n8Ig/dgCx60pkXDh9dcoI+//AXBmIMTNEgpsdZ6wXK8vuSIKnMPcr0ID+Ztxy3w8MRNBtswnCnLsp\nhBP2QoArHvrGmhDZjvRiFpzhslgdPyiMeHyaQCICXKOF55QZ6sa+C9DkTJugfp2EZQIga5LrSTc6\n3rppuK6lJ1j1+cYnKipG2R5TcJtZYEWShSakYrnc7XPyQej0Wmb8qjCXO+hZmkIwnMTyoiWGBcYM\n09bc7DVHXvI+nlwPUh2GB0OIBveYyuUVzALBfiNkLkfMZ4Rqt8xNNMrsmVGziDMhoQ6nUl57Io/e\nlClBb+8fioCu5h7vDGc2/iMQLvtjWVYutiTPp36vtvUG/FoMa5MrJ6s5MCEAqI85DRmzUcebGP4v\na/K9n6bF6KBPBtScqz8oZlfhCGDyFCldXyqteMR6RZyV1yKKAXiBunsqmukS0xXpk/0BUbHgCbDd\nWWxClazeNUXUabl4DDzfN82FipbyFe8ShlLA80QBEES3Qp/u2bRb2cx+nnqcV48ReQsr4Pi9H68u\nY4jtp/sti345Av+WI96CPNYanltsmSKatJe4mN4X04++5oxfI0B2IOB6ZrHLPPB4LAPKz8/FiqsA\nKrIeX7V6Rw3X6sqlox+6PvJcpK/xrO7wCPcz33aZT87UVbK+rFka1xcQL+8T0yUDvGoKsX+1SygW\nWOu5fA6jInKD1e6gct0HWVj85CMVGApFoaCYCY+wKsvxUnJpbYgdRUMDayFyYOcSvPcuWrlc30NT\nzHXrPRalxD56Ym6Q3gTiEtvwj8PegDnb7EtcZ0uwjK8OCt/U3HrmFEscrH8i1q6alcAPKtq9WK1B\n0nwlZSUaYz+DnXD+fdlzQl4B6DGP+z65+kJ23NNlQ3O4FBsE3CVPVS1jInQYFN1R/MZ/NDsNKcT2\n/9HOVf54MFx4y4KYpD12c6rt3mrL03cr0AqQpOjfGPOzxZAOsxsGx5pydhpitDOsT+YLpdDok65f\neaRNQOciBmskv3OvgyoedBPWUtssp4dZRWivjakHQ4nyzSB6LPBzdHKugKM7Hiagzp3TqwoBg03e\nocqaUwsmLbrrweIw/zClSv0Ybb4PA11ZEnYLUTtBEF5Nvzl7ygkiFthizCzrS7TZkkJYYB8ltUUs\nzcOKgYFoNkTomQdhNHo3sWyNjhqeCijCSV/5+PllquArtqQuzLrMaQkCdQ68163mfRWsbzKIUbuY\nLAM/FnMX8/HTvqZl8gSN1yOdYrn5yUM00CeA+ShEd2TiKPWygLaUZ2MTv1YbNQJTZJRT/XYKjJQ3\nPCmoXiiSpSvl1Xh8mrDaeqZI/CR5Xo+7ItoX/fwwHs9nhipM6AOPthpsCJGNSpl95Qd3V7BZ53FL\nDAc0aOuivhvZCafQo2FPwjV+wmeEEBvTX8fZ0KYdJ9juXbCU83XRxu37KZxX6UieHu5H9sDi3v7y\nlMOmlu+PZvNPh0YPNzUXb89xjhl/XkrP5GQB/Puv9O3TAheVV2l4vi/GbfC93y/h1eLsSzkIHVAq\nDQKexnt5GJrnKmPCE0z6exBRrNPLJRxivLXsgEfcNg40OJAxbtsiL57zWkswvcdymPifzKbue5b1\na+sAZQZNc0yCKa5H8zy5gqK2epyicY483zdRS/BDHGdi+H2zwcOinQEbWt1uv6iKjOin15tbfsvv\n7PidT58wPRvkJKx9xaeJApmPB0x/z/UQwCGQCSp2PriFN8Yqv3vrUlA2A97FbW8rAoNtU8l1PgPm\n67G92DFxvYzMsjrFLicOXoAq0jWkESzbR0DKPmaZKkIShNKFlJigWGDVNPpMox1bNvDMH5J7LPZ4\n1wWixDY/ZS16rUbmxHdvfir1t89trPgVxF4jXaQcsnokQwDLQjjj41WUeZR80CcrJ927rx+f7tHr\npWhF31kQEDHgBvQBT8/POvhWv4f/mAfNwYSWylKvRAH6+sPoo361/wxXsq2q8Tc5m36wCxhyKS9L\ng2Wgjd/tDIGqlKNVTMaROSrU8YX9sZDpIJp9sMvnO4p818XDslDKxx1yNDIG/WxWuS+1SajgzUpe\nihK4Q6cnKrw22SD76yZE7Q4vtl4EwPNAisrd1ooqjIpsbW62kz7zPQFK0I6otG0rwwZ5YidX8FCa\no5M3MgSB+gDNka6ulGapZFd0IpvK4uRo+QQMULNO7QIM29KsTg27G6vFaAOPAjJm9gt+1WYOE1XS\nnw9EOd13mvBVZ+t4t+TY7SwE8ThnyRJ1gZ2L7Sg//93GTdbdEDlFiPnIzARxJzBudVU+3QEXE/RH\nNCnfuh3DaThukZSnjIEG3hNae1YBonjqFdbQfd47oOPybmPm9X1U+mKxmuPF5OQ/GuNe8oxKnu5C\nWdufrxecSlWnGMusxb7gbzcFE7dDL/grNTD9vQ/JPVDYfXmsBbGUZm9unK3Vun0XjadGgvRH+rfy\nC65jgpDIrKeWZr+oQW6dRLHBuYKMAbwSJE3BoT55PXuOH/dL/QvfZN4kgnFmo1yI9wgh1SSvF0Xz\nHrdg1nZp0NStwjiZURc8+UtEyOO3lNFjC8djdRtJDYf44YQZjyDZQtd7jdIl+TXJD/GcWnzhynwN\nTGmG+RFMk81Hr42hNMuaghElfpVbtIJnJMYlvmxT72ptojCXy7hczYP5vFEW0g++4dz7DZyk0sNM\nUJimDy3CDpgimqEq+KtxF0vMeWWTt+pWI2pAwsd4GfxrDcn/8ApWymuXE2ev6QGhkHLWwvVP0jHX\nwQjnUKDfHwhhe5WrWbCdPHGiDLEZ0ad9baM8ZWRhoilq81aalMGswIzIEzluihzHoobJ/nwjm24+\n9Gr7OS80DeyNDBc0+dtxoCu7ro+OWvfxl7myvwwnvq+AfPzWUcPNnI0K6xgIVpngiSqcjaGVFudV\nQrunp8i+ykRRyNhN+sH7p1Z5bWV0RI++6WWCOO55zp3fINIipPizzRWzQaq4pS415l+BVYgFiF/y\neQPnEFN0XhL4MlRRZQ2C5cVkej4hQJoTFbXMCCGzCos+M/6WVnK0RgBYp1uK0hcpwPz5yEeRb5Zg\nYLbRBoqhm8M5Gc2PfSRW5LWeT1NVikspCC+zO0c+2XEcl74GBIM/Os7d2YPYnQIwphJ6tcGd6kJ/\n6zwtKae0LKo2p4X8J2/LXPKxhHToHjnZheRJN+Ws7bhWQb0awbS4RjoAgxQQ4Uq0atWMLjk0ui5J\nO6HXgVWzY+jzCoh6shHixW1+BvGwxUy/Iy+iUwU9AYeG5W9S4ZMOP0FKCDu/DhHOWn6AHJxhRDbJ\ngZsCnwtrzo1teetnUOZfEc2eqto9SeuZxuHeofUJRFiimCVDXSer9XnIc94XzK3r5aGLtlQdVqXE\nrXR58StHCXah+7I2Igw+8Yp918fUg5/ARHntXb2ToyiogzGS7wLlx0ZRPZ777PmBHNwDGr5D22uW\nEylrVhpmlgJfARtHEke46DXR+vcLzW1K1Z5GSyvnOQVOYaPE/VSF0chC1L8aXm8TykNWOsqqFHqa\nizB9aKBGwoBrzzLirm6b4zIbDOMD4bBsmTTVjn51LN57+7gUwWR0hF6KmUNuGDDJsPb12o5jdpC5\nhuzsXk/+le5CG90IcxAN1aL0w6s36e8xoDnShTDihHvu9Npu2hMrXXYIAc28kSLww2HdK5Yi3BgN\ne1zSyMky4ACs+RnGYvWHmP0lN59X/+mLcZRnObeYLRKpAzRrSNi72f7AU7LpdsxxQAQ6q6jKYEs+\nA5fhmyuUW3G+AaF52mpaRE1OJ+YKw/qLj4R7boI5jZ5P40Z1K1fVRCenPEFX6IEb2NcOlgNjLNCf\nfiMF5mYFGz0eamcRhM0RItlZkWNJe2Iakazklay7mW/V42pensipU39nBMx5fq8myPltRu6F3AH9\n+zWDsJpDTn4bTYZXpOwTmtNiSm9XnTZbviehgqe0OHUHFby+i0XtJmTqoqQHlJSEt7vJuZX643wx\nqEnZrxMcCR6p6psZwcxMv3qfVsMQtWp4UB4w5T1OGtxY5ACFqjDFli1CChYwcHDdP+LnMOWoJReb\nmrJPq1Yp98ZTUpmEAeIU9CCgfbLLa9oyCcHfVa6Lm2ZT33E/eeFer0L+PPV8hloIiWXjWvjIyKjx\nInZpJy47H011IlrofI5xNkU7Pun5+/cabxuuL6bFc7Di6dNJwwgrU/FBcutPz6mUQ9ATroMac7OG\nn8xMFAdWEXH05T4KcdPP1Yo4jKE77NYu1JOtTxbSKIciRZGFBKUXwkMfmkVSrio/6ZvPUSO1ATxm\nD8rndadTmvy5U4N4uwE0LDNlbzRBrQEpJQV8kX6Yi3njGLHUes0x6NIgE2ou0eMnsNiXggENmqbR\nXq/UGbY0yHLg5mnmEXQX2aJu2kj73Jqxnf1ie9QhkqxPTt9hDIcb5/xqpdnlQQCfdmXPz5BAHuMy\nyTpHpGLeAp7Q2VyDM+6T/k4QWVtnnQd4yR9oJFdO5c1caLTt5T+W1wBwgGhKtmqYsdb3dfnfuI7P\nnccUl9cC0cLt8jOVnbVVklyrsryIvWClOEhTSaOwmmsU7sQsFBPLDRswYednMSaz3Fr/ldTHIH/l\nRNf/5rPL/sepbycc1cnYhL4lMI8PuuF3TpikP5aV822eIq/itmBp5FeWOFTlsPpExv6FN1KtextJ\nlm8ikFNPEI/rvndxBE+5kqTA7Ut7SiK5OwIWlDxbFKX8GwaSkh6gxecLTN8/DjhU2R/uuTAZgWRY\nAHughyKHd4V4LKBLK/VNlu6xGLmu2RPpAlV5t32adrb9OdBS2BSqwHc34tYnzT8F5JnIiYqdjlX0\nCFtcql4nv5ea9dSEaTZm1TWJIl8yJanGq4vbxLknl/vgtBrCc9OF/ENyqUhEop4c45UYDpCLaAvO\nCDU+eJ9/5Q8DxVE9cht55IaKxVEhUAQjahx0UMIc9zzQWo36xPFw6efhpXmCPHzDgY3CirPIST9U\nZtJNO7hsvkRXUi6UF9k3SMoQHugIltuGT4oaN2ie8q4hWQAAFlHDbeNSIO/OzTZJFwRltUzW+eP2\nL6SjbIXFBbYeeGDutFw6WZHmhNTePMBDL/YWxwEDjtq1fD6ZOZYfWHxo5Sbrj5h3AKqAvjfooQdZ\nNXZ/UI5HRrK8LkB3d3OS7+8QedJy0l0hBuNdKW/9ZSV6v/aPaq73P5Hsxwub6HppOTdpuhc79mGQ\n/BL9pDmndVUjWyHcgyNkt+zcO9z6QD7PVAuNSZyCb2mI+Bff5GXfNbfpDPMpONpx7ky9z2+yr1dc\nXauIT4xqFGOXmBIPXbiJqIdb7ZHM9Gi3/k+4PBHgUknBatmkDJ5eecnrjZ26gwas6Oe5lVS5KLOg\nGqXTIVVFFpiYzK3ljzoiT0yeBqaJNI4pbjLfcboRyIF8VIWqoO2IfYdEhoC3o+i0Yl3keAXcLh+S\n/AXycHMCysu/X788u4qjRxfaxD0xjZGm9dunBZOgWm/yfFpUUIZE2ozu5nF8DUaEFp6vXVjSE7OC\n02fb7LzkwSuroCbayLt++NlPwDysNXHq0BbIC8BUW+7COg9Qq2NB2AUh03NHpEWm1uBZuBVXJxoI\naKTHQ3t6wWxYxXNg6z4TLgc170rTOlgGGp3YovVUcjXTRTHomEB78mYyHPLuCRrYEW2NQ4J0urgJ\nnzWCUwF0042xITA7DBxUAmoH41LK8eL/DYk2qg61L3MJAJUX3AAr98caLhagCUn01UX6enPIKQb5\nnWUVB56bgpQYcLifI2EwlpY7hK7HFeWXrHyhTZQnGd0p8gRSS8KuVRpyH7z0GeetQ/+myE/r3aOY\n9plLEK6QPf+vNoK30hqRzbsnu3cys/K1TggUEVmS4N2c7i7OcTTRe7S/VDkSc8ZgoQXnOpJVTsiN\n1v+5FUfsmi12db2BlUXAtUM9Iz+r/XxaciAzOgFgFHQfl+exQV34Ney9FwNtVJpwXFa0q4nIfts2\nekxTFNLzEAyhDYtgVffuOl4VnPF9BSHN6y508ESUrPdBJwXfHzV+jflurF1MCqX8G80p9xDud75a\nmnGZPak1w+6EfxPOhAgPm+NonRFVRM0ki3B3HZW5HKs0HGPiLl9Q3ZQP/fUlfHDCeKbvT0xWPKXU\nXXgxtu1ZNmEvyud/3jvhFDfmjh6AaCKi2XXMsh1BkT2a87E56X0VGZmscW8gdPzx2UvCqsOa67y6\nnIiWH+wTfx7jzcaZEY9tJhBxicXzVAkpbL7hh2Do2hGc83L4n+tKZ6IN2tq1FXxdUJmkVh2cLX2z\n/Jn1ixyJ9VdzWIdzkFKwLsA2QD7ns7QMs/dl8UMxO/RtjKahl4TZl8BTyQfFd3sQLIlQECEzfKX6\nJDKfd6WAXaTYDedLRVf4TCuwjx1rLab5XU4zhO8Q1Yku2qeKD+hth7Spsn+0i5ocMLoBSiCTpZ9h\nXn8ds3geBGqt2SPd4eyMefSzBIGx/Q00rnMIHHUVN3jQ2oxmAbAOTgsqd5GgrLdsLwRQrwpBZqsK\n3J6LAW5bFThJ8G66/rlxbFInnGCQ4yXlpbHslAgsDBcmk0nHvM9oG/RmlySbKcQ2zAlOxVrA2hGf\n+SWPpsoPahzsXFFJuAXtHzIM78ErCC2jCojJaoej3YR63BqdghIaE9nFiYcVBQmNBJCybtRZJT2N\nB2pPbfAVXCbVS9SFGQyAmmyOtB4sgXG4LYaMSgLYWttbh+Bq9gGUJaYRur19ZmwEqYUAWu4ACyAs\nHTjhc602LAuPwH9ZGwCO3EbfbFMT0AyaCqY0u6qW2OIOhNDjGVMooNmLyj2RZEuzlJcNNDOs9GYv\nKNrrEuZXcqkjZ5v0MjIkm8CXX9EpU/pslZMYmIYHuxUFOD4ZCC5htF4KHvR64VAfy8eJZnjElbQb\n+h9ZFi918azIWgSoWm5mPnDYXQUQhA37JFZMdLrBGVWd5J5zhrnOeweKYUsJOVz2UhrKIOZWpNV4\n1XboWeIC39bRJQh4+9g8KY8keLAK6avgMPrp9Y3+RV+gzucUzb8S14/b4UsFcVv0FLDeJr1qeYnn\n77ASlZSJ8MZZlEy5PH5iLp8xF4/Jcib7bXU0DgSOHqppPU01FWFAAFQ3pdS2vIaSH0ON07RDG9Qy\nDmlmF/n7ek/vZIjfOXU55wrDl0II6bocsUVBvIqMki5b5JqGzm28HY5AGgN+nNIEw+N1n4gzKNGR\ndOIN9g7gMcmFTls5wuBWvWHP8awlMGRvasNMXrgM1HkIis+Dm8TQAJ4eRFgDj9Iogn6wvT+qgShM\np1iCgj70yAabS6Ohq3JZtCernQSX13/S92WHEVe0YKTT0mH6HSdoodhQctB3XY4D0iiNZJpC8zqB\nHlnlP/RZft0zTU+v2hmkGePJb2ia/jfiGu20DZd6WM+8Q6cifUTUwureuHURzyZsx5zyUb9WAekK\nRW1xl21z+xTacEK2L8qi3EdLgEsZXUzhvr27O1QV+uIuL/V+/YLdwleK2RAqn5ROW42Y3Q56r/dV\ngawH4Wl0ANU6S2JwbGBais2O+2nLVwhLQriUcyYNXhuWc+7xPwsAyHw2R9M6vb3Kkdg4Wcfk21NJ\nMyVY6REt/UBtqkC/hYVNoE5n2qhGSpoRWVQQFCkbew8WzBWOZdyzmISJQDyy3b3BA237ujhb/uJR\nzRuzsGaaKnA/cog1unB1GU2VUljglPDy7n3Hesx5xosdn/gxURO79XFk5S/jzWaPBJuvpenaFFxr\nyESg/K2qR0dEvEDJihX+2a/GkpGghU+ZhezhnC/mapM0ykkmzBxUwUrSc/IMUWmpZCpVJrNLVYOF\nnJSPS3KIxdL1diiYh64ICDSHr9i7pqKueTjsEK67qlhAIYCk6xXck4I5C2kRjRThjv2EHQxOR5dX\nVe8XbzrBwIiyJvvCxm3g5+EPCt0b6EwYALvCH8WAZ91lCtTCFqomRB6/dUS23DP+Sx0y/QYdr15T\nRZTWH8LGyO1E1W08SYbUFZtMUnNPzcykFRMCYI1IUWLBJXMMPtiTWlyEltXCCL3kMn0AIwnYyFvJ\nn7SxCiA1qUsD7CWrhRpOU49dneEphwxJeNyz9bOUGxcuqUwJbnum1eH7rAtSANIQtNZaBQ2Ke6oJ\nlzJdhJE12MRV65B4Nsd2fZWUUTBQM2uXE1k3NQPO3xQ7bngSv1sJ5so2zKPo7iMSdH626ljtmqmQ\n4K6QlEtlWL0ryLMVOe8ywCbeCs0+KF6DlQTPjvaRIFgSf+/XUxGSNDAP67Ww6HJGJvhnJeA/bOtW\nkC1vPFANG0f0HbgdV/VGUIEMPfTvVWQI5mO8xP2mooXHRsBUytHDx6Xaqc/F56+ERQd3bsJ0U05A\nGY73sBTAXcfT80bail6td4LXnB6q0mGIcoRpavQcXpT/crKmwSJau6UOwwVeuKIBtvh72mAKOXFI\nD4jy7sk43ZbMnS+4o8p4lneUY8fHwRlAYDs1OFhi5nvGUjqRfrW4W7D6NjF/ao2Q+RWVwZYgPhmu\nc/QpJsPsoyTZyPYiSI6X5gQQRwgy6PujvtJR2cllkLm0y2X4BnRNbQthFy2DGmlXwV9jKpwHwCkQ\nNUudN5MZ7wkx/S9/gtj2iaAZzFSlyGE83QahJLMkTHh99PnViB1VScVdloR0E/9zj6HyijTBtz5c\nTvpFgdEm1VltojHW0yR3KPsfXBPNvV3qxZGcine3CYB38XNAoOpwQ+m9KiaMjpS+Z3g5jVSvEPRz\nI6Swyc2GHSslRqysHLDmqIFkPYMglv6rb3SP4MPqxcHdDQ42D2QUrIg5QGSsCFVKWYNzuMHNS7MG\n0q9S/CRSYZI6pd+BdxF7QMfYvTxG/z7SX1Y4He65yVsu0BUGxVAycgESC0yqDb/mPS5gu8ICCL/U\nKFYEMO8VavxBguJHpSOZqgfn9uQPdQKICYTyk3gkYwquOIgMeAzUERFY9rDolU/bFQBcrEE04bCl\nGbT1w4HHb2SwKQtCKUFOU/iz1/RQhSELBLKUUWiylPcK8ah60oQCSYEw5Fp/BmjNb6AtVYKSP5lu\n5OCzixPZqSYs/qpGhwGoFduI5ihI6wWRCEmtDWr4fn/VaQEIhnrCOaWyCB7dopkGrzthw/KTqugv\naPwLPvra19o4S7x9snvKUE38ohqiZ3jxQqQhD1jzOVB2BL5T2OlqTN20EzxkwlLulKoNVmKAloLu\nK81FvAwebD4TJBam7Dj09uvH7Vc4ovQsnweC5ZGwKQHDr5l+KYUTpuzAV56b1L4mWVv9KC1AuoWR\n1+u1AypMa7rfYuU8J/YBsH3L2l90hyykLH38XhVxAMQfE+rppwXmCK50Opvfu+3464I40J41o3/U\n2ukQgp2CV4cEALbpyBdHPBeTVEsGU7XgzZjhL8ywTq2g0uOMdr/GUHvajFz5WmKBD1Kn2/A48CSp\nNOF7aTFa1MO+YxEGpsbEGFzGwB/8DZSAS44NI2IJwsH+Pqdb5mDPEp99GepNImg4ax3xuQ5/fmM1\niCvyST6YzO9vDztRrx6DVty4yCz18qh/CBLLq2VO5mQjtLwx3EEoU5WRzivutrc7rYh7fYKPzW6u\ncMCbmpHfD4KjmtbzdCp0jbtSJ702e3alBxvL3fNxgtubgy1qwi8RdognRQaW3lJmodwMVdrO7qL2\nATWjJoDQ7N1vlYlF7a5JdHlqQdFmmyEZOcyxul/lb+66+qwRWiA+s/AxFe3OmsWkfQrkzcrm3bBM\nYCgq7RiGK/Nyg5CqZcFt6sIPEbjDril9Rk9eyfW6+rg2ti5qirauu6GTi89nmG90XFTqbWa2INSi\nu/+J87FDqz6mNQjHTpylfV+unw/2zp2uejZSOmCYg6slgJ5VzEmbLA/loWbbF169Jss2HKsqkJU1\nFDucH9pO1HhVVLLAgvzdWWSWVqHggZ7fdGPKKbND/q0DJS/MlSC4K9wc4d+a7LVqf7YfcArWJBSw\nb/CDJopZa8X7vfppRshZdLKB65dkiC71qdw45IYggV30dDfgL4Y6lqB0d83MFZ2fWmFGA1k+6opi\nCCFPqhmIsVyJwa8YQWio6rNR1n3Kf+cb5LMmmvDH08KeKeBi94wzMkfx8HbU3C4pNA3tFI8HU5lu\n2zYjSejh21ePxj8+f7hNOWHj53eIVwlGFJbeHtuOPKRCUR0ofAhhjWRTTqd91EmVEEKVQGqTsv+X\n0Ofoh1RZyKvBRJFf2qKEDx5HrHBNDup38TtEIQw5seyIR2VVWs7VfqMlt1PMiNCEK5djB6+o6Vq/\nPx0LnlJneHZ4aPg+7Jdx1UYG072d4qEzCB1Xqg37CLd3Y+xHDV+7QDYT75oX/2vO/RsHH8+4CwRy\nrw0knqI4mwfuKMWauSJU5fNvt6owB+BumMxKi6CJn8q/Ahp/Qkye13tRKneKn9RIxeKkXX4bdp3U\nPOdPMfTsdf5FfIIT9fsBZk1q+DN584O8YXhQ/vwoYlxkO03yFQy0t+v98xYVtoBWsnIGcVXZNaGl\nFp1BakMoraD+DIttVaUf0wB36pUfnDLTDvuHLmpgk2XG1LmVRvfdZ52WboncKChN3klluk0pt/AS\nKBTVmhloAwycTXnHnam5GBIjPwPDtu4qEf+m1DyGAo4egZXTy/t8J7tOICSHhwa0V4icen50x4mi\nF+80cHQS+r6jwF0I6P1+0waqv711ZoZ9e8OEeCKtD9cg3UxIbQHJ//qPhG5GqYQ79nNCUcxL0COr\nSihjFJOyM1HcroFKCiJuOCu56NDvE64S/ohFW/8B1RyBPYqcsGOHDusP3PPujuXmd9wra9whktlS\nDiBxU69cPygcHZGCAXvFCc6/4qczdg5RBWeH+cTSnEQ+LQqWVNL4KQSshKyGpjX1CQtCARE3/khz\no0pMSYSst5xKLVspDiAYAYwmHaMhq30l8dct7s5EfvE3vTEOpYsUgzkK5FnMpTMQm080koGudP7x\nS04xhfKQ6LW4wSxG0WxmHIr3hmuVc9tsRFZ9T1mIH5KgBBhi7XEvYeFSvhdw5utdWBc9yE1bV/IJ\n0vrEHBdEJQQ1jC3JHiDeNsWkxk/8VV3v1QMAB8N793KXxgQ/1jEoCwo4r+DgCws300qN53E2O69u\nJKMVjejhty9xQp2+lHRIZ36dvXnVTUpvw4PjnRr6nvdxbkar40A1xSTwZtOv035brN6W7IDeKByR\n9CV6S2CH6CocTKT9Zt8vPpltk8xGtfZvL6iP8+E7DEyTKpJNSbto6tPn78lb2k5J+EbZgbkvLq8M\nTagu9wcsOPFmD6zm8ytmIjLDQnJX7Ly06AkqKfoEgCv/RX3sJDmhLxuUrYN2P/XZyZEXHtLmfjYB\nsIWtLwccXsmc3oVsi2Pq7OJa6yyIdyX0Vag1r3cBSfGMXuhqSEbsGPpHGQAb1bemX6ZL+eaRR8Ir\n/eZQNuhoWG52LpqKtzgzdwYD4dXnawZEgrqPm6go4nMxHajMMT9x+EPRWMRCblVLMU1luSH9kaS8\nMkIoiifAeNimveh9mQ9+m9uCae7DWwiSrDtGe5S0aFDcbg5demK9BS6oJ2C3dBToRiv6isyitqJ1\nK4hru5Lh0iC4ja53Qd1Vl1IsNzYAQ9eEtiubhzCW0UnxLC9l1YlHe0Okqfplx0X85fEe2NfClZkN\nMVvns0Q6cI1RCZoehNR7MEbMUb9sf+YE/zd78entJAGGQcMvgDqc8GPH3Ph5iq6REzmUCizdjv0I\nQuRHIwhl2tSwe3c7oALp7AMb0UEUcEEa7yNBMnSZAwJHxxIcLHifNZnM03He4c7JsB4yGdsZlDmm\nzZoBCJNcbpyRnlvDk7moNefE4BJO/fNaReEAiICWIlZxQA9zDxlf0qEz2FZgadqLiPvXKd0SRjA4\n6iDTL+0XdstQT0EMQUdeOAiDZ+gMhw8gXB9TUZ2KzJmzbfZUOKnt4Dk3S7ZP5reZ67wa9T0Iow/r\nK6VXvm9MDYeTLJlHKJb26IFas/UWABGe7CEM3RCFR5ryVylbEh2frp60MtSfC0mHZIPj4PZVdoNI\nNiG8ls6YxLThfFsXWp20HODlp8vhiepNTHOGoXXKgqoP4qHxUDqUcc0RwU3Qppj3tAK4RurMczSz\nhhlq8xWyWv5vlyJxmJzk7hfCkbradsEVNkfl6K9Oahz0QpXDpQf2iFIk6sdPbjligmhJi1mM1nkw\nG1OXII9kBqnpENv9N9RSHAqqC2EZ0rpCoo86Ow5r0oOJiUmcc65rAomtlFdRFu978TKuwgSK9C0+\nlvBiOfqqfF1RXBAt3OP8BIZgKX0duUVG6lxYs7unXE7WrDkaG3V/VbM8WbHectyWnEAvRcw0S9mS\nDdiKwWKoS0qbSDhtaCGXzhWMnM28+4kegOOYPbRk/Ztu6Uz4g76nX9OiU9zuNUq1WLLjEKfHhK8a\nGSK7TjD0XfBFlJBN6zICribUSvhRDQzFzH7HC5lKMwntykOMgHH5PeJ5U6E5npyoaAjscpk+WPXA\nO7umsA3PQlzkImQmqtskI30+FAMhso1bisaFVT2D0o3MCcuLkhHfMWr+6sIBgfjsPS3K/nIc79Q9\nW78xWZMkiRzh/66GAojp5UtmS+9z0Yefinic4ll5BWvFt8Nji6T5qr3JNbmRxSLIrWy6SEQYWFbk\nuvDa9GkoamiLQGh8cxjQYiz4sGUOXLRClIx0n/r+aCLxc1osC4zXCCC/H656dE9KpcyrxrxNNjGg\n2Q/qsDxIDgLGrTldEhfzYQxCutaJFSxO5+lBXt/b35vFIgu9EBtQDrf4Yb/vRBnwosJ4EXFzhc3t\nCGxZRFmfJk2EolT7/9M5D6mI5D69lbzOGLfsas8scb1Fu5WzV/LVcuhOFhwOfbhxdKjynFeYJIlM\nMg2Y8V8wIoqQqw/LaPQs50OVfuhNZMfG9jmA+ExAZe/ucokZeZna/5j8jVI/rtQkEIg3A9fboOJs\nI3w+MI485SEWZ775L/kBv3b+b5mquXpb/LxY4Zzek05EvFEWOdHaJHOx53f320jbIAufGGFQ7S+r\nMLP5o3+SIoY8UWBBcJL/pLJPPMXYzHLYwo9sUUSrSNf91mMHDv+HU0Wh2eySI5i0INK9gBkxx1fe\nOnym/qYScFhvYPMDuq+TPTH0iEWD46s7Nv4wuIOAq5xV9O3uryeKpUQziY+T6z//hsGBBWNbBl8w\nILc8gwYVkfUv/2L46Ne4F0DRSMim/kOuxiN/MLiwivYwaMYLPCHBYTLCq5EqNIO7UnifZgY8GmPv\n+dI7bySys73tXKSYwPwdbvMeqWjgnm15QxWxPxnL31tSCh69yHnuR/2UDjSIAvziXETZPI1wgtzH\n4zNfH60m1Y4fzEgIkEhWL20v/86j2eS8LajMp6wG+zX/SH0ofwqc4WEYNTUUVt0txzLsY6vccknj\nAMiGAZ9WGwk3ltiCXvSiA37xd/64b7OTSOxdAKC4lCMw32HOZK16d/EHl772X/CW65LGXjBwz+g0\noKGa2hjFuaO6U8i2AJDZO+yb5Md2Cr5tLRbRSWmk81RoMVUqIUbpNRAsjbXUGZpNblzYOeQe0vt1\nf6PxfYHe7oPrkpdbVGRb6G25F5Js82fbjUpzX2HDdU7Il1twenLOBN4cdD6eLejdhO+pwQdYX1pB\nQYJ438wpPpXiwEpSgmIMlspfG1mNSTxfdEUAHgFRWzDvdbBaWM8XFSyfjpZSVh3K0/L5Oz1KaHMK\nmlL84qRPVU6Rp+NoD29VfZb4OyRsO4UNd4pduIp4FeB0TQVM95pQ6okMDeNIceKcw1O91PWKden7\nflkLY+RgDV691cdU4QbC2BRx5asY+ZiKu0bEWOhkJH2/KmRJITdtA+7xavT839GCEWYZCM3YHo6B\ncuw/VqDedEV4xND7mx0bYG9x9guBtGVTHiDTyb7phXjVe7Fyi/x5t8VufShAgo/rtyoswiJ8BhlJ\niPsuCwoul5MxCFqHLK5B+UZJqSIR9/1VIFuGceMk5Ubv0d1H8Z5bPpQwCvdfLL07qvjUEvpa5mUB\nuJJkNEG5juaNM0/IUY2FxPzrNx/PTRIjl9LuV5dlE6NhxpbJtZRWPj0lE8jjK1chUV+6+2I9lrTc\nrJ5rmF7L+wbi4C9Dnp2x2xYaS/tE0F+VimsBt7l7B9bAarIiivHNFgTe2qE/+Kb1M3H1ct1Hqjm5\nAL1YaKcUqsQLLnEvw5cPBqQ8QW32XBuof6yn+xxK1EOpb7J8gdZC9ud9Atb/F+rDUY3Zk042VOJ9\n+38BfXth0Ew8oVZmdThyt5KDvzgcpYhgHwKbx8cB7uW0LcTT3DG+SLkqMgun6MwLUownC1+r4G+k\nPOYQgyWZ2hwdrVfUEm2FQ8T7jIjofPdRiOV6vMIyo1LQtEHryCdfVlFdMVkX+zEa1uMOonNlIG6F\nqlwAOm8pi+/BvGuB+BRrikGczOJB0Wg/rgpg72XrFf3i1rneXsCsO+VpQRvcvl0H7+GloQpZ8e4/\nL6/LM7YId2uE/6LP5MJwBkwdYhnQeIBRDsaT4SqBqvFFGUwo9XHQ7BX9hvDKJNNr2WJx/TN4DGSc\nQSXf7zNQkznf33MkIXuht7XWfQq0F2JDmeO2vQWLYbSyGuKMoCeZqlWTINTX0kKL2gXogQo0CSFu\nl3yJUjzzXg8kxWRp881QDeoh0QXJzkJlSK9RcBJyAPoGq8MGVQnhqlZCaCtKwWjxXPJMod56Ofz9\n6d5QEnLnZTdUaNX5elPnAy//gVbggUKwOQ/skaVSauu/sHjK5FOnEBYk65Rd7tYGD0NeBXwgdzq7\nZjElbS8KS/Cefr+77JrYrMx0aZBZJ7PQi9t6EAB8LJx3ynPMFiOi1mFRiRTnoOunlquPz+IQPZCz\nMGnV/sBJnYWAFfT6SVllXQSioS/rUjluR4vovLgImmCkRQKUSj5xnZdY4AVssYcDjdo02+On7piN\n8qNFmcN5E7Yf/TncOjvzUDpXawtm4XcUunz6fz+TAFwd6SFGP3I6tLXK7Ell/AJ6615QZubiMzMy\n5isLZteUKQdn5qY5SU487hB+j5EiF/KIGAbITt3VhdHrimshB5ya4LsOjyuKLV8kB/V2FxEcrVP5\nlPsWo8vJ/pCG1SE+UmhSQrWcx4/NM1rtR7bCmMtSfeu3ZhArzYJK2EjxCmwxqxivMXGcsAByH55s\nRNnTvl30k066eZStn34hQlok8+Uj4MJAmSuHpOlft5Cw/TOrk1MOZFdyyX5HyQGbCwAhDElXG7Np\nNtIBPPZERmcalGEy/Owm1PoUFZGrD0ygMaJgnLTHY6MLYf5DaqbqAsq33MOscg/qw0ro97IvQveu\nbVHyQ8dKOw0H4XCakKKp59qL+Lo06pAmqctYoqEAI6NyA5PBetT83h7XnqI61qecb+efcMBgjAHx\njfy4b1SDC/HxaiPhae5rVoY4Mii9nQB7tuiNNT6Gmu1Vwwpg+FqVEjv+kwb5pFPKdcoYZP+5TaCc\npfDutBLUv54hLF1z9ZTSVfm8dhinFIriv3FGv9/qh+OBVnE05kFf0guuqhsiraGuH03jxhZjWfyS\nOaM8SAV0mGwdime6bWsWIdynqw2HAyQx5ZB4Y4WQMUkJTUZZqfnyJoiPtmujk+CkRIbdfqOinQVP\nO07DTJxDEzoF7uhPsOTK3EFXwpS8pYBJ6rBUpkDv2cdF+nkS/+/cAXKl/YHTpBgNyZhjRpWyxHsn\niFcLNNJfu2sWWDKVydWGDedDKCGcvqLPUsStmaG3e0WUzqYcTIcOw4FcGgqM5B7L1taswxouzywa\nIj0O+yHtm4lcDaUaPBH1jpC3Tx1teYcGoV9p1KGhmnqYHidnh8j5RR7mQphYOBTEDhrfxBok0oZp\nxEb5R0n0lHsnE5wR+R4TmYpqKaUpaZOnnhRH5vBWzpvNoXJZHsCXpiaDJFAEE6vHItaTa0n+jLX3\nsAKceIWi2N0ON80jpDAKDd8n2CWy5iOPEydoKV62sboxWYLHelvWFOVdHFqza9cLsXbUMPH/vDsB\n8zUXcORUvcn7XjjuxPfPOc0t/Q0dPFlQIuhEr08hTBnRjrrlpX7+x6ZTY+fPNHR9F91Pv0fPWCIy\nbROzbw3bSzeY6s15+qHzXfdfy24+QkpwFfNxBLscbYdYMJuaHRfUkYdyiSvy88tiTke0cWsJIgL8\nb6LF55Fl+0MmwuU9qJt6LFzPlqMjg3MTJMUSxs+oM8M2Y5lbhwQwyifFyhKYtLmLusjTARMM25Y6\nukzQRYRNI3Oxe5UbT7SrcwTUy1Lzewof6EN8wyjkP5FSWkYNXeMzogCzF/M5OPrEz3P23auJXL5f\nPSwxg5GwtiAddrpoxwVq7t/SXomVKF8qrK6QHhSEkffLcH8rFeij+Eex34jAGjtyYThMr2yAKAjQ\nvo4wSdK/C8Znry4ZN2XvcUYAMID1n0uTpMVXdijFIGLqamf0k6GmXzQ3UpVfSzrDS8bynQPdLLGI\nuxvSeQyS5cbAMWmj6MtbyYyhYMLNeIGeHc1Ble5JKk9XcBOCCFgzOOv31ocUMajLFqBtSfkqRVra\nFJiVtRF38mFRo9WKRHhb8sdoITC8hS2CTMQSsxPCAmNaVD2bJ/qFT0p1EZZq6BoZITEqjyAZmtZx\nXqR5qhQI4oxW96jPl+BN8zN6fFGwSg8Uc/RdDO4jXwwJaU3DhK6+dMf6pj/dlOYkkqJWJ5zvJtdI\nN/rpUYECSK50BXCzYV95c0h8TYbjLL07Bo0wAZsx9en9mAAJjFeW5J9b6bw8wSryqIlFuv/vii/8\n0NeNbQ3HukqaJ6WS8ig24kNpl9AaJTw1mevhFDSLwa3iuPULC+87SJhRoIKk7u5faUsPh5M+BdS3\nnwwNBqnyAL/eoOxdZGIbuQgqWGGzqOOHbG1kV1nNYc7Xp33yYYqiV7WseZtb4ifQcYtnIMXRuCPs\n0HNXHhr7bZxfYss+z0D8ocASvnpOL8w4nlKT2PiLsJ+jpVGuGS67p7kyScbgWATTr1CCJkP8hlGI\nMX4ceG7sdnxo3SvwA743LtMPEDxxTJV+J/+6w03IxGuA5NzYdhkU5Br4pGMfka9XTP8KCa/gkIs2\nw9HFq5FtvyOmvpOL4+vO90uK7rMdlqzeGa/PolqIB6YyPVJKLa4IIK9yih6/HfL4Dr+t/VMfsX6r\nwVNKcvxe0cS/qHRNS5g613kQ6UhUK6nbWfngwumJfxEVujPsHnfwLImvXV+Z0lpohVidsRwRstCl\nypmA///VlWrIIEfM9ztYImxJ+QCWHceJt6eh32pSrS1Y7CAJmjnpYkmyNQzNY63+27caRFAiePJe\ntSVGh1aHXEvlFIm5wia01tXhKIajPWowqppLHpWsZQkS1rJJUM4r0e11wGleAGGxpzLFv++3rRZV\n2E7P0LyqAMCVXwuJgbDCIUjKBeXleHsoXTjsTJ0RcfA16W2S7LwZUHCmJVq4hjScokm5x4LP6eKu\nnW7YbxZKQNnAIWffjZAbiPXmq2NpSzKlWV7VBEHvhB3WX+EGeM3dY6Fg0rL393oyDKouyjUWwtJK\nKkxwPWhTHPfGtMQHZyUM25PNCS9dRLKFvj+8Yuv+Cjbmf1HTxuUHNkIppVMhe3pp/EoYQdCKYkf4\nNmIqgPEpc1Xw53xrv3c2+5Qe2RPVMCBF8XCVGS08pfg+iaC35dIcxw6Arwcub7q1AJUHYWWH3e17\n++/sVHV8krkistFmP10E1UX/+MJ9cPXKZtgTdfX1nP1wgv2fZiV86BE76jaU7foSkNjoqQztHEvH\nvnjg5wHfIOBGVzLQvSsux2gimvtklrdrQeNtEAOAQpNS+C53UQWER5i7GMN1FpWJmOMX0AnM0fdP\nN+AUFHdOIyVfThnj/V74mNf8KRQZT8nQUqmy3LgdGQ7uPX4esG3SBEeLh2JSQd7DG8Rzy7bzFHcT\nR/lPn6HC2RR7J+MiEZbxOgXfw5CazrPTtOwGqDjFroba3fEyK6BRmL6ltjB2nnNbZ3QMS84Tngu0\nztlVsUNRQ0vVqF0YHm5Xzu/LFsbmB7GIOauNfKOdAPUZ9+FyQsOahJKfbgvle/vzDZKF7dJBesQR\n7G6ng9CIXGpMPYE0Je+/agXWFSxCKueeO+bxz3ykBrwSkZqafIocSh2im4U+LUrsdQ6Qg5KHNbvA\n+2ko1mWue4ZHKFv3GFIz6qy8sSdD4o1YWaRzp6QR6CuG/L0GNdQmSRM22JvOQ9ORJ8zEvxHKtsnC\nDDxX0UtcYsOlNPodlxY2wv52fihmfKKbhbhMpFY9wB8xvbiq2ZD4NKhflfFlzzNjsaAJtm07xKlJ\nvemry435VhaDY+TdxjrGnAKY8dtM50Zuw5GkpQQl8/L7DdmvUu0b4+ozCk3HZICokDOSzb1zTgvU\ngwko9mlZjy6Ro+IL6CNR27Huwainy4TT/R0u8/+5Fv179JNlvHyGxYXUa5rJRKrKic7H2nf4dykH\npcfDPpPIdH1kEIrpLaMjMoIsf9ypnvIpIO6RdGv6+Q6txwVGizW36oyiNd3BGZXe5F2CH4ImOqdT\nzMQ3d6iYRlIvqU9Kw5Ul/e++X+NLUudXHoAMRCPNbvPhB7hOYnKeR40UYNCDjm3KNgvMxzKh4Dd3\neQKaZuo7/YToyzwW/jjo35H8jGygVz0cA4hssv3j0DESJpsjI4uINFEqYK45Jn4fRPDMBxpU0V6Y\niAEQF54vjRcFgtShdk019k5MuVKNoQ+6ioiLfV0VtqEfVItvGAa9IlriFbDStqq4/rmdvZSArMUk\n+uF0EFdygH6DTJhAGoF6uE3zm+O7VytcdokHJmfnvl+LCSqwm2E9nVmqp/LTVl3GOKTP5PHZPyHE\nKCi06jAtv4vqhcRfdpwIt5LhZiXTuDrW/LJOqRdZXN5Lf4RO5T2gjYjgq+1ujG4JBq8ayr4Jhmky\nRSYp9fjRtfWn9lJAN8k+AdmkvXs8jy7wF2739kvWDAN/un1R/jxWygm4VjmCETmc3tgWZTBsyj3h\ndS7ip9ZGkO9ob6spwsAgTdxMfvK1vrx+UtwMbTZXoYLsDRtOHOpZtSlwqzdwlfTfP8wqu2owh4NY\nIMFNw2uV7x8Z19AnwHVSVg/+LRFyuUaDGsY0Tx2w+AWOhecrWJh18NUOCcw6WYG+/zLfHMsOy0Jw\nzbwdo+ynwtdG7mf4UVXSsr8vvwXKUGLzH/u7HLX6ri89GzLPTloHlsDEKlwnHWE+ElKuvbcbSNLz\n7MAhzh77MOCAOzn1JWSviNo9oDwCiru+wmYkeVGBLPncm+tbZi33xvyqZBmfdAiF26M8iEdZ0fC2\n9yNPdv8S/uO19rku7PiiqZvBEsudotq/zr7KC4V4r4Be4Fi1bhMPs17pJKEbnnZRV95jnZZBbWVl\nB8dCXMdwhms4DwWuimrqylqqF0BkHLvolrJ1PF4O/vId65g+6REAfD0mWExq5NMxA6QraCswyXBM\njO5ogsRfcuZw4y/Uft/kFMIM83hr6URIolvB7wRczzYNd/L/rUCnaBE2JIX+ZGd/Agmvy6lyaeSg\nQDDJ+ud46UMBCh7q2VG6ShlCYR4MyG+vuI9eUoHQ6OXuK+5XogDKPl1ThMXtIbZR37r3hWwh1axd\nlmfN8x31WfLCjsSFuBJExJkMZ5INe4PrSVpnMhT/MPhDbvh3TfPx9q/rDwDpqNlXg/4wsen236QP\nfqYOepmKZ/R5cPOjQsQp1EdDmykoEBb5vKZC+wJ2Ni7GDDTyuIUczE5uoWPFaOeHshGDmqpAyi0C\nYF3y8L311F3BT0yRTvNn18HPzKtJTn/lava4O4X0UK9gmPS9IUpRzvG535glq+TPTBeNNmMmjpoF\ncK043+6zBszbg1lgYMvoV403GptiT72C7uIAvpG0g3jR8ktV8ITtR8Ho36g3WEjUWFxurrhR5I/3\nMa4Igyi43BjEzm7f6cmxIh3L6OaadG2DZ38XUSedfRuMRuwWT60QG0FmYXdeGFv4215blbNsymcm\nk2mIDQbGDk/Qybmsoc7LPxjQV4G98NugY3JbxzfgqetsT99VhDmj0GBIG+LC1hlb++vcKjraa/C8\njN6NZRKehIkIZC4+vQS6gw27OP4PJrkOkXASle88FbbPhxozfa1WyIQrOq1xIqmLOHigv/faefeW\nAxTVyv8ScMVWcpI+jLJLLy4a1Ch7/HJ/igiVmCHlJm7ckJMbgtBVztLXQmXnjJTL6Pynsx6MKv0l\n8BVbVKIE16HLCsUqMPkgg0arbqf7yDPlygpesUhx0cUmFWse8vcOA+1H06P+4dycC80KWTsmPS6B\n5EGvU3RjL2y74HpjqP3MRfZBswhULeDpxvyXTaudo8034t8jEmw2Rp5ffDKcalxJbexN0612mGqK\nXqkLlz70YN9vIddrjYU26o3OdmYoBfN5cTWD72Re4pVTTuUqJ1HEE8xye8F24YDscQOv/4SaVieW\n8xM1S9bv0ifD1RYJymN5BCskUXl/bB/maR9C0MzQ47TZprWfZ8Zdhg9whQ54UgBUNuESTH+6DGs2\nACGSy1Dns4Y1955iy1Q8actfsbkIxYi2/oNqHZ02D2Xvwg3tHecFHzolEI6SlfAbGebSE8zOPlnO\nDk5WFDm7R7Ya9Wzde1ycw2/dEPIiNXKlzF14E2Q5XodVnrcpMwAWMhgnnuHIE49vs6jmYNq3GQis\nlhQUwP/dNeK3tPco+bLYIdxZJ7pWhl6d05lMr3MGDeem4/Cpl2QjnO3aBmxJ8J0XA9RR8gUjA23l\n3vpbX7HbQi51qCNjyhGK1Tmn2en0/fGcEOGhZyyCvJH4Qo6zB9uGykWijrxVWG4RmvxqKqqag0FJ\nDlk12cU1XziDHfGXtE4VhXARzXiF6esJwhhcSD4ZrgY1ji1RUxpWB+b4TuzJKPDpWO79abKalORo\nC/stTdrUrz/piO2okmJ8sOj74MQPCPxN9rpJdhy2k4LrMMhDh1kaspAmkqlclPY1falbZE7cfe/0\nin7NtWeOPQrKTl/qhE1qao7k6Ua4ZeGWC5GHaS2ipHen6ikeqettySwzRKBmkdDQSHamPY/wDQo/\nVo5THKpvcnZFmnuRDI9gsWrl2HV8Cnu3cziisYvsdFyyjFJlLwQI080Hm7YI3tK2ujDpuxu37bkd\nVnshVjH6Lm3O9gsdW5jBFwOx23KmV5lftiKdYyRkiF2iMjSw3tLSSlHQ2n29KzYnL1G/26FjOuI6\nmThzBJljDQuqaE3P8+F0mWoEBHmZCjrTaPb/too5PFL5RvZtiGun/PNgZX/pUEuzDeQeX08IRmek\nEKmkvHTs/bc7f9diRmuKuZ0H6KhygPZAuIP+2JJ8Zcy94C0B3pNqkm7GypUhQXN7SZe4ND/q67LO\nmfiUWXZhCIigT7LLJt8OkggXTxYdk0ArF5AA/dHoUgKcvhfFXSnNFzcF4C42BPgt5D5lWQUDipZ3\nQ8715I9sCHyxQVihVdsS/jzu8jW7ZiT9fmouvloW+afVRWXnzp4xWrqsHwJes5dBP+OMnR5K9XyV\nwpOQXuAExmx/sSUECT2cwytphepaK9GB4+yxMNZU8XIqfaawkSCeupH1jiH5ztVfu01WsSVZL0Vt\nZ9G2/wCR77e+YWHiga0WAuSbN0Sm/kAOZTbRQ3Iqu2L6xEwsAt5OufgkCG3QWEA6ZFCgt/11FtNo\nWCg8dspVc7wjJGcaQh62kkHOHeKyQP/GPfc6zfn8ojkU6lx6BtJUzVc9+5iSeiziOxJVcg+XiNfm\nry1bTBPVqs9V7GfXZMNMeTPpqgwy/SDSL7PSaaGXTc51e2rpsZPCv4PWW+k/3SAK4kBHSFsXoFai\nlWnFbldiXTkPzBByW64STapLmZt/db23NfGWmSAgnfeLy077nTB6S5VN3QJaubOw+sUFq8QDZWhq\nJlxIh/AxMOu9CnXuhl5COX2kO9MnYp2ibQXZjYB2Uz8GzbRh3KOr6O9O6W3eiJS0HmB8DwT3eBwt\niH4rzeVRFdnU9sZW7iCshmVvJV+XW7oEo5D+mVIWBfKFAxW2CN0E7mi2blglmwl/uUoXwiZWTQHN\nkhag0uDa1dx9iDbItFz0ff9B2+bFpQ8AkwoXj77KoRfnZlVXLC+351BetTTY9QZUbC9jM5kBy01H\nTMWQkj5fvhJ9zuXsRqN/ZPhdJDq6JQuiEcgl4fc7vL6BcDmgAMISZNEBSA8QIcAwmMU9Z0K6SvzL\nNAwuXYfobpCOxANwrbOXWCIRHi0LUYEAp0zpK3AeyOedeZ68F9Dx0fhcv7R5k4sHHwUeJ8QWMJl4\nuqJXzDcHIn54qJtSVy2yQ36u4QGuUmRMJ1QDFwxXSrRk4ewO5n6ndJrxupnl+yw9N8jpv0rFyy8x\nv6tNb1KSNcA65G38Uk+f9pXDFVAm9yVMVmNARfZzNrQybf4G+K193zlQGV+SrzXvvGpmOAfRhgox\nHa0Gj16eO+vvj9fYyRY0sOv+3uwbC1pn85cfGt8zdhHAShA/eICI6mnWYE+luL8oTUPFjbA6JuTg\nfWgf6iE/NXQSL2DBUMw5RF9/G3yfPOT8oYWbJZqL/s2pDbLW9hNGYXFQpXD1iH7/dJeQ1tdJipcu\nXGlb3slj/kcLiggxed89F/4aDEvVs0e6Ln27lb0ihd7NmvZrkbjT7vY8qISWtBVA7tNKlVV00HvZ\n0qvK87ftjk92FJK4fSekoReIxDjO50jci6dwOEqmYM16fIkvpBIllveCmSgWyYQxJoOrTBhPJJtf\nXfZ6PPmEUUvXU2cz8AnKfLRCcN/Cf29cKf549Q98BDW9jyemH6WdntrxM71+Hhjv4S5TtU0U0g0V\n0+t2NEX2ofWopXzTd7xXyQWW+2FlEeHbIg6Yi7LuQwhxTEUHKro+BW4SDMa8Zmib3qrPzVE1roWa\nMlCU552UI7bRNUR67/3lL2I9V5OF2EUctqNmUS1uRRUduiEN98Ni5WnO9pj7dC/aEx5fYbprxuUP\ntYj6TxMUAK4EpYp2EU81lidmWfGE+PSltOYjZqwp0eX2VQG8gtQ5XLQ5VDL5EmdTdG94MAZ3KWl4\n71qGiCGftP1gc02JOeebdCLPs9RB01Qamz/7qRrtLZqfjEm7vFGnZjrPbvouq6aLrTrkSoQ9Rku9\nBq7sCRWpZJHwIQW3joU6vIKWqovqZrmuMZEMt50iADknpPAcVttuorkxIhrY8EMGTVLaeiKc6+aC\nw90fEP2IluyabL4KCB9IP5YRud8Vem80dhNNefrYqAytpEjcQQMbkigJA71KxdxCMLHjPZhIqf9P\n1FOlQfDEyWStjz45PhUvBsWGfNfY4e7RP7t/msJ7F3wQoa9QKpj9K/iurRXNZN2eKT6Hj7SGkUn0\nACtUn9Zun7Ua1be3Kb+uXxXfvj7+T0Uz3jlSydytD55UnuDAYq+K2gAwynXtc6841qezeIxadr37\nLq8AbB4IT5X/oDEUDdtuxJhziiuLroU27SrBYnAx3ZoKLS6XfVF7wXS4LTlEOGi4AzkJlFgbtjDN\n0n2EsteXDHoJpKSx1AqY+vi7VY3JpoxH1RemFZ4Rbxr3Xmzsdx4BaO8hsfUOAXD/iq2b3VP/iWhB\n8XRPiTNtsAKVeSMyRv+E/9K5cMsB+gFtd1En27yHSX5qBO9M1g4ncHw+EIhgU0Tg1aEZlnpBXn1f\n8KAdY+kh8PwqGgcbkRdJC3bttZ/g9xR3roFPxpAZ+boxGrp2jE40Fcr3X4g44jgrA4IRgiUDIWTX\nqR8lxjalxvMOV3ATBs+7cP/BSaFzc7AbNgflKhebuvoh9OVDpfPv5+tJj/Ucv9iEIo7eCoyA4QTT\noY1enrvni6ko5gsAxgyanuHdkjnMV9qdVIMntJDRkt0cWEfdAEj8z4tYB/hGCMz103rrnFkX+aid\n3cFFPfSGptu7BMWqfuRmrduQ2xdKKgZPaj+yLnReK/vEbKIkBYZl8MlESCeAWwf1nzu1G6V7xSXU\nFruXmDy+vFG1QwwK2CMJKGUq1PintY4siRuRBhjdR8bY/v9Dppoqiq0GbWCnEnoeZ0lgvS53Avh+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GcA9Zn6JSJxTUCwYs8aQ3SIm8x3etRqToWjYKTAbZmvRezqKjuhJ1htlHyPt+p\ngxFYba0DOIa5737BxwzgTL+BM/X75cddRAx9O1zRk7WcZscO4nKsuVed5vzVpY5fUeeam4wpEreH\ndf5fZo+i2TN8VR099r6xe3IuXjepLpUDSqgz1s6fjumUU49h8B5VogWCzI/Sng4e2ySs3DuudcTN\neTbO7F7hocbaR4Ja+OHzwSKcERs2tKt3SKOZaqCzh1C4cN7icnZeSfmDXVkJyB9mTWl/6wSahflp\neg4bS3CxHvVHBxc1wTPp6ZwEbCNJZ1GeG3MurB9i3JbnUDzmOFhwg7eOaFurXoGiv45RB8vQKvjc\ngyyFG8V0I0UxUmA9cFlbilM6mXKs0c7bvXdGnxv2DQpmqWwHJafqZ9Ub7GIRP2nIw0yClX3C5UaC\nyf/tjtAnY/dw/5LntI5BBunmuEC6fBhZSntF7uXrDWv1s+C859IbUO234tYG7dJFDQHZH29sVYfg\nQYZDwlOgb8VuP8Lpo6c88I1UFVYFMgCF3P5SQ+v1m63bfe3bay4HUTISeVJUy8JV8sfADq2wubcG\nuWcfUD5AShQOLmrpWHHJ7kOetd/o40exAcRpY6ruMZpAbw/XTk3w+IZeYAjXvoV4HsxbneA/j/6v\nRCzoW5P3UuUoaB5PgGjjGV5hyDlRE22MnFsaD1Edp4Aaazf6x/abJR+gEuiOjIkZdFyslNkczRoD\nu7By43V/wCySOAnWyFDHOhN+Rk2yxZXouQu7q4FFldEH1iFrGHvxaAEezrQSskVgSBq5s+L59ioU\neO9CS8jae071lEKSz2D/g93/OL82GyJlZWj+PeSbqzhShQ+oX05Il2Hif0Nxbu2fUZVIMzIa9VDD\nf0JX96UWWVTDr3evRvYoh7RwhDS82OKImfwBmSzxFjawoemFpUn6yy4AdrgWom6pB82BOMrWyxCm\nr0baPyGumEcnivasXzu3Ghg7l4NtwjlcTuSrDJyiIIqWlD01qFIT/NSe8XGEUU3cnSBqQfMnb1rY\ni9O0ljhYVL8fURPadXIpnmspDZRBbO/9U5PDuTLIDUARR58h3mS92o8oG+2mYSEHMk9Yt23OoVZN\naP/TqOTjA3bB1PM7YulgzasFE+gl9SAFP7u9cTy07ik7Z6RqLfrweuEgZzZGPgnx+HDSN6clM4mE\nVHYMRJf5jlERFhrV8NNEHb+dJ1cy1o+50SKlrf2bfrsA1sMfqwFFA7WTEXfXopqTuOy2pS6YuTzn\nLtt8mp+m9VBSNQNLGSuPeVQKDL2c/GFdlc6tWG5msBw+rNDavwUIHfgdxQT3krhLdr0g/Xg3vX10\nmVcpqzA8cPWZU/PuRqdqDxxY+pCqDWMuX9X7UVKrPye75k4QcLary7mM+LoUhbsrfeeVgHdXbQQM\nzMhNtPA4SoBi7w0scbWfeGmkJixU8Sj4L6lA3ZvMrp/M8AR+++6EBCX9ttW8OQssFTRvoTnGA4Jn\n2kCJwehXlV5jwMSToYsyFFZIfrJxAUbo/+5sJXPMGPJIZRxRvhgucH3WnPrzojvDrhoDhR9WTn/D\nUIlyqa4FG7wIMST9OtD7LQ2xc2zji5zZN9DmxSdSMDQA/03HnR0gcY5xRBuJZ1lVW93DRflHAlIE\ndxPAtrUw4T1wgmfkkOnNCKxOsSAufvMYEchVBCXPVSTCIUgCl1WDz1FztJXRkZhd7VubxRZycQbb\n7F0xSiDk4EP7d4d1bLSz4fXRdkVa7inKtRAzuHfrKZes8NViU4Hb0i39UaHG/0rHCiWuEqEaemNZ\nta6O+8TeqDy5mRWmtS04oiQBIqj/a+YJjajeqKkJo5PwXbtHvSQh8grTm2jifLLDtyc7quNULvHe\ncOm9lfFtaaA9EHzxLtTm2U+5jwj6VdaXu/Ui+MVFI0xsQHgjT2wK5sk2yH071CVmBEItMF1tRgQd\nQIH/aNQjpXW0VHg7b+/8rumUFrN+pmkyUxhN2563muCP4KBJd0JQrKwU7s1O3br5fHuueVJAe9LR\nyXRESLNfzc+gr9SgamtzGojIrCBDOUdjjM6J49tE5jD0h77qR7N0SyxngO1MjZbfnYlh0TiZkDrO\nSn6LQCdtHe8jRfHGsS0T3MouZqBxtTrH1h/5Wg9xfQiQNzbjFdKkT5KfBmXj5IMkhLC+nYB2DwNu\nSJ3tFGNeOhrevRvFD3kUC7fsFE/ZwDgMmeDRMbfPY/Lb4XcSd2iIZBORBSlcLw+e83D2PnE6mkza\nnmnmKneUB+XbLJ5SGoG2x3n3eYD1iqpgIRRjPc9+6cuqbbkDWi4/eLtllVND026fbWEIF7PSYUK0\nwh1664zeBZIErMhQYj2uSBUZUWLIb2ys6q64oBSI5R7dLu3h3FuVojFnfAKueZRqbC9twker0itL\nIMphRzQ97vqXPOpQwskpiS+j4989IJOhDe4UTwtvUFVPhujGAfnowG3xIolbZ07V4VTbTzi61amj\n29GzddvermmeN/WW4di+c798HQaVMAPlLpjdy5BwGUk0SINd/oPNbjC3LeDtSSBdv9jld6nDeIjT\nNOVG8bBSqDP+0SDTjI0VlDlLKXh3KmZKpG+OA/z3ssNWrlyCFOgq6ZD/BUQCb3CLl7yKAVDswePh\nnK5UpUiGqm79YFthbWwOedumd7lJPMBxNYnJmAmZtSqcx38lGLipvw3ZMIEBliw4TlSRjPOodnCj\n5uztSEunBm5DjF2YJrzC/eZ7ea8lkj2HjtFZOrVG1eLYgh9Xi2PTJn3eCiZZBLMyEIGbpmrAHEEt\nDir1mN23gE9E3gGAm5AIQd0X/ZM5UBNPXpYcT4QMDGFeR8CC502+5jQ68swFIiwkynNbXW7v85kP\ngNi6PG3pHfS7G8j5+v0eyr4z87SXr+0wQ7+YrKvAjVHMKwTGds7JZSrwY/xbyS41jfuL4BK0XGi4\nGKhXRrAV6L4csIatF/43SQRMQAYQTLkSdDlWFrYmimVcttsF3Nb/V6BRPKOMZf/AIRfl2g25CdOh\n8t4wi8f2wZ/6vvyVQ3JjUs1GtUYeFEY2jWTfc1nfqrw6YJmSZExzhFIq5LVEZ9hcIQ/mWBgf4VfF\nldlM3cF86EoYz2hdMw/bPSu8pHqYAOWsZvsPVeLvR5bf+ugQYrAbCzBTFgM4SHoJsfINe6+0nnZW\nfkR1pXXII24Nn1y/HuBasCbvkzcHQwFyLWOi1PcOxspjoOrteHd+nv1PwUwED5QpalSFP5gx0j/F\nP6OQXBmrcu8HNETcC5BNbjUUgxVH8NmEx0vYKQka2u9RIWNOY86IY1UCKu4wT5U1nRyTpAy96rY1\nCUY2eeSu15cl3mFEsc9cR2SaZp7oGFiGkOeASbDfact9JWvN8TRyKi8cuY8jnRLtMh8w6wkHUW+F\noAxhkhQG48kdBvp3WBM4eJC/FhAoYDpTS3VrpOPFn7cHPRte76xha7ph35Pmy2bw6sY+BQ99Yk6h\n9vmke0+Iyb0+XXIHT2rKEiFSiu8dRJ6l+AqhZidZgZkJhwWP6y3ecQwmJVAhV+qEd0wPaFwMQoVI\nrzJC7r4gIi5KpEF26KGVAz/C0/Cj9x5E11XzeRsFpyYKNmgKzN2jhUC5+yg2/QIQ5A8h7Kg4dieQ\ntCofAS5iA+FaHtsY/jn5rX+UwExiVSxZRm7UjJbNW83QQwfFcfsW8O/bvA5lU1tk58Ii8KbxIvek\naLGlNnWFN8WThhNIHLSDeHRq2zxLQ8tG40cLPkNsyz+rMRzi/zjKmRbDejskopG5i/lb499GmbXr\n2C4NU1qBCMI4HfUZ5Mr9joo7/9FzpKG/HWLSct91DJ1rOP/RoZv4rbb9zKm+zlwL76OYPF9yA5Ma\nZe0asLuYZRnc/l/2AeEAdQVhjZCwsrClN22r88vb16gNFKtjTExjrzsDtDjZ38VXUOkOveq4mhYn\n4vnLjumrZBCz7y+6ZCszoIOjULEXOLchdJYytt2ysJfcaHDBPBxcJn+WKQ7xUvPyzh5WgRMUdsim\nDuVT+D7JaCvgAT2j1VfqyHMGXgfq5ph5OLNiOevTUYgC1V5HA70U8xcLfS4RYJI6WJCHWC9Wbngz\nzNLDlUD69JGv7uThe26LzvY/ivOrbkXghyYbkN4VT4GLqOsWMCYEtyAxmvgWAqIhNSPw0NSJjE5x\nxO2zQm1FoNF5mu+nCWJdUPtx70u0a8e5jdN9GFlj0EYq8DNB1X0nZZoBnNM/W7TUMATH/6CXWzd0\n498UFlvIFo2HQrBaKisdbEQ1Qb007Rp6TCnkkwgEHAcKg6AJiU/DZLXeYF60Biwb6N4KrGT3PWbt\nf0Kmi1vBxjXBTZbQXGjHwCQ5D6b5cYFeRxyCBrMFOUv8qbAKJEjRmrVW2MuIwIBgNbqnWIRstX03\nI5zhAC0x0EWpvNz4BOglCPcHaYYzo76rjSDZh4aQlyQmEiCxXT06Jv2NYSW0tU39elbVs4GHgI4T\nym3nR1zd9r7mOP4orAjs574aT/9ikdzavVr1NoMgeyyPCkPAIT7IxIce9jz6PdNk6zDEySO/wwdI\nCOV0YVAH8zQKQZLiL4bx5xvT3KZbcAHR1SsaJeuBZ8Lga1pt/5pLF36+kIJ9mqMHR18nWmcyeBNL\ncJEQH1ntn5eN1jpnbbQWsPwozLdy48vcXxr7N+qr9eUL8XPBcUpq43UZWMr+XUhhbgimqWxbY/NV\nfuSLs0MZQYkqzSennveOAr5UkIRGGlsWXubl8MxTBCT+GUtanJRS9duOH1yU+l8Lh8/orNoh7Nrv\nc1FaI7GMH9dMRFNACBQILarMsF7GoiZaxVxfCgQZMv2meRqmfLlgJ8HupWxkyoCgnlZLndHInG9y\n7Hs7zUmIhAGYuwtq9HnuBcKJzUP6hi82F7qk88GLhmoWaGDy+9WlFirxxJj9q5kYRwok79jIwzx/\no0ZQQUUtE1ZYANeGBMwhPqW86Ltz+DOq0vA/z8rOS2GDPEfNq/zALAuz9Wgmfp2XmtwiMCk9wXRA\nn0NajGKBfnpxQhGvH6Kt6j6GX4ZePX92brl37hhv+v3goAezP8T05xCAO3ENq58hojoRpLskhm2q\neGZIZA7RMgLk1EOC4eXqf4gyTW/XzzZphuSs3NBT4PvNCbJweAzuRW2koJNRXexyhIMu/uOSuyNB\ndtKF3ndxgqvrzqFVmxk0eyVDB1YxZW9xE2fGTDOgCvXURap9QR8KZM4J9nrn1Ogzt7jBEfj704HZ\nVL8HU2WnafB+1NDxgugtg31MWoZs7+giC5VUC5hoa7dc9vsbU9FNT5fR5ozf3v3797tYGsmcH2Fg\nBi2aS/mM6JqJ4rSaK6oFh+5Wnqc9pEtpsucK/lxY7dtCcWQ0t8pHncn7E1jhJyb8SqUXGzUXbo1B\nCyT8jRoNNy23C2KPdfcFdjUmnbnp7AUtpwN62qySlv3Xz0U5EXU97y8tdFxE0cnjt153zSfb3OMS\nrDlVGh/Qwsi9CyoBK5YapXAeceF8PZ9xlL1yT8la2l+ZO8oZsBW/PIV7k8XBWXeWzjtyWjjkXogp\nC2Lm+SenlvnxblFP5MjHdLkLIhRChOx8UFJcwPVGKWVLLVGpIdZ8VNsih0z4E+8g28p1tUC4wMRa\nhTAxtupzWMdOflDIVg9KeDAMPXp9zX7ZJHykJWRxR6q+3Y9PVIaJ53118LYjbT5kA6t3dHjfr4ga\n6sqPWD3DDpfagbv0tUyujVlnxaXTUCPu3tzOIEoPC9sIuCYESsSkquOFkoWAnE+2GEkSzPxgGDM7\nvLjNRbflPpBjjD7xsDSf/E7LDMCtiopSM521w2KOc+kCS9QcRDIGhLkYCFnxICp2SqEvoFAjSe9o\nTYG41/kG1FuDm+R+VFxytSo6hKqkhqIt8dtb0dDsY30Mlci13Rcd+MS05Bkihxs+hx/MHusmBKOm\nMcXWSABJJeJzN1ID+bRm565QsBExStKd1TmzjAsdljAUPv24FISbs5iz1ruSFpaRugTX0vIHGAWb\nvG87IsgEaDzpNSnFPVlWWb3Ae1kcMx2LlRb7534qDRmszfq8fgmYIwZQrsLjY2WjdhrsiHAMwmVh\nj289MTKDn9SH2Aq8pcgbc797NRoZvcxtJ0hD0yHoPpWJI+YmG128Pp/E0A/GLhZCfd9dPwhXprJK\n60DQduAqe0JXJZUhh4ziuj+sYnoQjandEFhZGa0cLdl3CZ+Tgs9w3FiHQ9o+KK67QgGrOT/N71tk\nr5TsA7eIZWGwk01L8o9+qmH2JnRrG+zQEEzjEK1FAz664FHDeqTSGHOpHHw4lR5PELHyFxVBRkqN\neIzgX9sV68iuU8n0DfDKic996LdsiexJexW9WLfH3DXMO8cwO5Abb6S1T5kFK4Sksh0sDSt3Escf\nArHXyYGyjOtQJXSZW38Ldjmje3CpMA/HYzl5aXruIhqnzy0L9tnGrNHIPThnvpk1CVEQA+1eMusG\nMZIyNx1nyaZ+GHA+pkdcdP90dDpHKZwqsPZVHf3kKHY0u1jqeTGchDgTlz8mFXE0HTq3HbzfKnMG\nY4zbW2OP4nzYZWPS0pgl2IcLCrPAA85AAWVMa6Ceg7mYLxdrMm0Ln/tOgzauSvkKI/ViZs1ahKOr\n2WeG7lAVi52tQpol+rSeDks6zGvoP+ePTUgYap9zCWUfTadF9/i3UdFf69hTsDZmD0YQrT/fC0mx\nhKHChOT2KdWe5TIrnbOpJ+I84InHqS1QLscyRhBYy5vOsM+XA5bxcpDSjulcZsRMdY++KfgzvGiJ\najuh9zs3L3sLdv9tCsf+elYA+GbduF7WdmxEGpEa7iKfjeJY4zU4oazPjTzVIdR6JqOFhIhziKmO\nsjU2IhcGEuVu0ogfcgl05hvDseGWlLz5oVJU6yXQSmyr7O6l1MRqaqPyKLBIMLYpXcqhMq0/R/ab\ninKhZtKEP7YnWJMq1CH91hQFThZ4vwmO9zVI9fxlfHMUoKxTIwsTHDXoyw0FdD2hfdXNZxhe/f72\n4Wkgp2qTz90wVlz1lYM+jJvggFVY+7WEQaCoHUu05e+ljIcie5sErvk0ueTOFywdM7iGowcO7d7e\nuhLyo+BAtsxpcGkBGtqomxgkZlyY7RePmNKMBesg6ouC4tmKlrOycTjVGljWsaY4mPLSKGFs13Ra\nGSwSEX53xGzieC4mFPwvJxIcirobSwW4pdubhvbdMEosfL6boa8QnLBz/2mETCSFBiJbu+Nb46H6\niGuD2cLAIuwbx8am8NAyM698phBwoPVElhRwpmZeeVpwbWfVWoMWq2v7t1oHEBH/VMcZ6PpzTcc7\ncp/vmAcidEHGZDVDjL+fl/tIQXVdSMRpJJlPqb1wALZTuVkD97DejftYg+7qTx0/nIjJtDAUI54d\nyMgtysL/yZlNf4EHhXvLz1XncBT5XlN1DiUVSNYQZGCUhU8UzCVbMCS49jY6IBUDzOVJnAOuPF6/\nHMf2nZcr5x5WnkZyCN/cm6ZZIkgwOgZd5I20Tk8LL0w1+tVygB6/J77LT1Th22rHnaGEDZEbKKIi\nEEMBRJ2zsprpglgMScv3wLsEiREmKu8lKuIYiP+IeHEJJgQy36vrSzm4Q3dLPSDLjqR8/ZOKCn3d\npgDbg5/XGvIVsThfR0tXjQuUKdw81GrqUM0MuYXkRjtzLsy6rMbTxOhCGtoIvWbkZ3ssP3xj2RMg\nzfUoGSj0PZNY6l9lCwpnuIJ7cWGYs90MGL8HLMAfCPGIPUtm6GGY7nfeHS4KIjKA4RVAXWqx+SiW\nZxSdxmiYIP/Hvl51ndadC7pc60ttuS06NeYHXDOO0S3vRQ1rMaA1jakkTxF47o+Jzcza7CiNSktj\nEXb3DfuBJlztT3vvicAdnTOu20Gk9HYImFU+V1l/7aGLrH4/rSSwmdoczLdNzpbPA2hNeLWpRTPd\nnt4lF7BZRk3h4ZwjdtQp4S0xFB3VdV9jJvtgJicwK1dzB0H3zAbJTvRTzN46JGxdDXOLV9Plgmhc\n3lK7uzj1V8wDQnncaKGeiLzwyK94e45MybepGzrp3DoeHM8I4HgjPTcRt7qL0nPWX1LvcGwaMdJy\nk3Z7nH2hrilPTCD0VbiNxfG6Du0uTixzYusHNlfx8ghsn0AHQec+Qe4dYvyN/8+uAb9ZIGOJPbAa\nwK9XZk7oblrvouXXXFBfbzsjWrOWnX+GL7ohONrsy8kJjey1WHiulVvVwSLudcs4F3gwYa1QN2JZ\n8bRw60FZz56Ne6LkeKXCfZOh0FOiTm0cRwrzrWUMTrM7CIT/YXJuJsqr/0mw2ZZ7NBFqXHLsxihZ\neFB61egffeahE+lhoLQpiZs1e33waVVLxDfY/evj3FocdMGNoQMQK/nWPz2KxxQXBtQHVZOjNrdh\nsx7U/Wnia3HajdqoupouLpo60fgJXgzGUlw8Nw8xfqgoJVF9jI7VDkdebQRUTW8U7XSVXMXF1wF9\ncPiYqw99dhUqF/Dqn38W7ivfQ+4pRrdLESpuSJ3k1DQGXMaSrmVUTgdaC40qBl3HLDKLCCHFiyw5\nHaHsZvKQ4IwKZ9p8uvWQiNYgzB/dywmnnWdg01VvpSWfMPsaIXN+TZOjB3x7At3FLyCvqU0KDBcP\nNSLmiavag9CucAQ5X0a4CbO4zq2rHFvb84VRgV7X/igswCO86CPlH+OTjiXC+98PSbQyv3Yt7yjN\nwu0vs76r90T1nhqxFoi+c82OdInCNUEyQIyMJJH1ub9t6qBHzXXy1lf2qd+S+lqoceDEDqwwc46v\neT7zK9dsLyQ8OVg6qprjyOXF+KPyYj8pvCgXrWzL46iuWuIGmQGhIjY5ctoN0taZPkzYnBpexaSK\nplkhhI675tI07CXRNHAYJ9V4WU04ItWkJcraQMbPh9pQd9jVjpeb156ehydxPUL5aUTpP4UWbDiQ\n6v3XwS04kaMW4C1S73RsASKsDIGwDxpUWkE/Fx/xjGazT2O9XC2tF/HfFu09QnBwAEv3xgxCsSgG\nhVYJmi+uSU7Pi0yk1UAx9CIBJZfvXCOBSSeqfbZQznoPl6VUDETyAtFWk++1ikObWg/mxDHhHMMs\nxxa/A/VfI6lDgdQWlRsDVfzhDYEuoBMA0A4FWpgfr9hkcsI6UjGOSyN8vGGPWfSf1kjG+4Hzkofl\n620EcndQrjZ/dZvi8FeOcveao7y3JpYdSlF2FJQpUfvrBcdHMu5PHvrjgysK9rHHuKLSrkLBU8/s\nARpzA/e6gYZoH0HpWEYwD48tt16u8tRvblN/h5H7g1tmLXRp6u77LuzB8AsUtEPspLTA7AjTXJ6g\n5T/wROxlhGKoJZC9/+si0e86GYGpR+iim1BlYnv02qIx6mX482NtCSam6G+6VbYpVdyX3t2Lm0qC\nOSdh+hlPvlsHAciO3AbGMXHS2MJMV7JVX9IQvBu7D++EeTrzHGEBigjDN2R/GdKaq7QBpwQrhv9Y\nQB1SI+U6pyEG7T5xpAw/BOsMczH5JwLlaSrljxEgzk6CkjR5t1JlKntP1W2tc/QOTiNJdAfLDJ36\nJcEywJ4KCMoDcSrl8NTApf71iPxqy38aNuehOuG8CAcC7twSHMW+1PdIlTOX/JGw5ydU0MlRxFFM\nw5PBJ2kA+0TPwLjn//9Wc/Z6jMvVS8yJ1hSLH4w7pJFT5ZhBUQXfcZMRp171i3T3Aw08GkfoUZzr\nyIQ6aItW860T2VbybbseJ+5ksBUs++IuROqDkR7JXmMXdZYpF6dcioHHU7F3r8/PSCZehCbLX8eL\nzeS2cyP103uUmRO+7BIJydB88XMvw8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5BPlgv0Ysd+eSR+SctxdgsIGfUYDU11OM0zbr/\nWzLoM1Oq+kbqKRimCRPQavzTq28qw2vNV76NgLf+Mi4voQMXDED873/xvIVY9TQsjopYhTTJgQ7T\nDYAvw4caDJO2T69XIDBCS5MwBLxZp7dspfoN/4oGjaDljcUVf52RQHBD0be6K7+UgXh3e722sNlr\nGIWdCtUs2ieNFcswyUkhb+J/TQcA3Q/BQjg525rpirxX/935A7IqWEBSrSJUyQ6bR/6RI178+VoP\nb+nZ31dSV5cLusb3bgBEdqMgFpIZQ04+C2h3rT66h+w8lgB1i8lDhFJYj6Z914taI7u7XrL9hdWk\nnS+oZs+XLf2TEHM6XhtWY0UfGTB4gk81QcHMPBR7FSj3PPjs6NfrpN8PnEta5+m7Bw8yWJ8hEufG\n6GNBPRuCN+ST78w728pgI2Aj77qgmO4bfF2EIh3e6jnqiqqKZvpottUU+wOnw0FfbAyzdkZHKegD\ntYerAldliSEsyacASt5YCPbQ2tBOlTdWlpRKGK5jhAdSN6XMihXy+VfCBF+iu55vsDQpKODwBf/l\nB8ttqqB8/6nZfoXzhq/Pgq6dwlP2EvSsHywtVGlAv/1vlQl1lWqIB0YX39bQW0bL61gJtp7dIyJN\nGXTGXiLo5VjnKbEblEGRVajzzcIM29VWYOsxCrtzGGusMJRb1cdgRqy49yWsGih068zm2wuMn/fg\noAhj5GcjxA7ozuv/6so6Csemv4QKW0vWEsu5LBWrPlIP4vocr3NsGTixATur/amAbbTeFCIGYoaS\nSjoM44N3wDyqsx/UFjyLFnf9A99T+by/+5RHIeoNkEG8Ghax53GNSvtO42NXxbhJJmixJNswdKVg\nrefi1rMLQQIDBFMeXpZctKcGDYHnTa6qWsI2Xxz8s44DR6MMt1MsroC9xPrPDUdujxc4s4h6R6Tx\nb4avq0fk/TlXz4ay7Wcgeldi8emJ5XtM/1MLpbTI5e+rGvBBJZn2f3R4FN1XVaK1leID3H8+MPhr\n72Xl7ZxK1k34nugWgEF7KkgInRkOy08AUeTUF8rIEIXHpXm6PzsCJIgJgNh9PrfxDGoh9XFHzHPo\n95su+nlqpTVGpiCjjD6GZ+YE1OZPhae8S3cdoeM4FgcVXsF1NP7PIy5DJ/R9pQ27TJvx5PdeDcrq\n5P4jynMDt/WXG5SmHtNJV+WD0q1vQMIkdeSX5wzCHcBDiWVqjER96rpl2Qwbdpo/W367GH8KPvUf\nAitgUV8GOu8TN4BBXonsdv684d89itGwwRGrKuVoUZtt+y/SwlhSTwA72MH4a9QWBe/jZpuc5eW0\np5DSHEiITaA/lyEk08vTfYQe0gsbQTg2dvpUbshMmvAWeWd6RoxDkEVNp20ryoGQJ9utSaixLGtR\nyKaaO8q4EwLtIjey5YKY0a/3Qn7OLrNo1W8xkOTYeRhC5E+kCtLKeve2NtgVQaSMiYr6SuYyk4HA\nTVxnfpuozhoMblkqkkj+JtQkbwJuxCBzRB8cLs2Xxd+Aul/LIjAAr183pTtklyhzIwnfiMNLW444\nc0/9McUB7gL+/gks92ElnH8khm4fpLUp/DwCEFKDend6hDZ7X3Cp5Wo4svtWu/v3fw1kgz6M9bUW\nJ9A61uWMsoS2wRbMsgifchp/N9DMHA9++hvfdpxBqXGOIw0VmqNAmPKrG0X4JEIU/6SKZRNNOG5E\nY2uVsHIfAYgw/4n8mv2fF7gvKyUSoHTbURYbZcKmmVv4q64b2x9J8+IZx6XZmLLBU+XJ5NxJsW6A\nTg6MU88JjupiEyYLylToCFKqyik7AWoTVJC/p2Xrt0MiHG5QRpKPsfMkhjb7gBS2PrvNBP00ee6P\nVSElr/CEpazyvPPZIuF6u6ze/u8Zhj1w0aneXH+14KnaFc1B1k2gl84kK+7MadGPCJxFy0HNW2zL\nsCOV74lcGAUuSqkLylCXZiiGtsicrnSiyTRstEasEvEkx+V+kbd8R/wO9Y0EQ5a6o3IFIwJzO0sB\n6KJeYHUhNr65982JC6t9Hoxt6agDzUeijvPjWMRhTu2CK0iKcmGyXsVdYQgI1YfBnQIOTXJZzY0O\neNTS8hH5fIPuWrBg6F9lwL5FPZd9APt5Wkv5fo+RC47fWbhQBmxpdUXF6HLjzGuq8GBLkcfkzGC9\n/ArWqnKORSiu8GUHX6crwulCXqSvYjc9Hypjw7TPuTVvnZKSiPHGRAaREIspT1dEiZHFaDF0Z1mg\ndn2tK03yOJ169Ud0SUyzXsOmi+JRIMM35oolbfoV+uW7YomtxUzbnIzt963yB2eN/GuMQQYpXXxK\ni7tsbvfSJNE3WE6xrJIq6MV30YgsQdPl/2DyCy1oAu2HIdIBAHwXptE5U3SFKDIr0aP24ePPJFXZ\nrY5YWECy6t+ORaljfEW/OAWSt6EKEx9LBJSAHyZRXz2oMrV9qUImx4xa8doClkt/i4zWMwbCsT3X\nDLxxvqAK32Nc+7kxkOtjbAYSVU3E2fMUSQV8s9CrmI/UELunLGXFd6HE6q1HgjODgnM/ZQ1vJcMc\neYpleSccQNtFsdHo796N82J74xCsK7uXVn7Q+0I3tJ2WDwPZvuZizHh39LkRwQQmdVDc/J4OSoky\nDsVgjI0p+2PatJf8L9EPyFtQmQ0JApa5FD/MKz1u9czJavCX8cEDPvGAGAczTWw2uWYgANc5p4UF\nl2p584ecb9ssVvKqGcKk/YaN1QQ/43AG8ut8UtlQxmxQXpjZqNrY06Vr1tuRj6mEjzJ2ijDFBdCS\naSlPbp1cld9hYjIdXm+u36IheCLV4JAjyQlfENRN5ctVJQ65A34472DzYIEMWaOevpdz8LpwMDrb\nomcM9KS+IZcT2FP+FpPQGXx2tGz9IySsDsNw9FmyJjyPSCVhpX91n06Bm/TcIbWasCWgo8LCvra7\nV8A8lh1qYPYC0T6+PFPJbTz/SA/59IjS0EpwAz2Nh08OLhek4atEM2Q1fVVNml9qj3ecByeuj4vM\n2LIxdpGoWAiusFpbmhQKOwqw3GAtXMQj4isIg0+uLjC8TCGBK06j3P+QQH4sSzR+yRzn2vthMXfp\nHGb6shHBzxIUcUgEvXPlfRUKvuVCRqjv8YE1eQQ52QGrqgudZiRiaPKFJW75ddXYlOlBr5ZVMSNY\nBWGoulXjstXKWx+SJs7Bzm8Zm8MKSf44HLYgw6h5r1v8JFtiw2tMxNvce68O5qF5+arcIB/4Tm5X\nCNPdJv2DyMnAr0TnFgqM/vhYPt5dPqDtSajak7mXYNjaBRdhDkenWytBOccR8UOfInk06KmRCdYn\n/DU3FiBgJ+AKdlDf41m248j/KcteFR07COdXIkvQohKy8egbvc4sTpjgIaaETRQ7/l8WtgtIi0BL\nd0EVC1t3zDqWlEZYBBZsuXzC4ma7BvqOOTSe0qKePROklF6IUVpmiQWQkH5aTETOJ9XJgJKKFbJa\ncmUpaDWhISKweR5Xv9EZmeowJxVP90+N4JBDhfZZbdtK5hhYYeAb5qYznhkPD6kgi7mZJR+kxCOx\n4nQCYaSxKwdMdyNciGoev/CclCZ3k/Cb4NSfadqiJAkCSfCUnbRFG/vUC/wICZJki+/C8JunjzQk\nJ90d+klizyWMuzr+5bYf+vIHjCGHOxHArWLAWPkRf5WH3vlGZgTnVL3f/fMk832dHFj6UnGUj0wx\nGxP5gWFpwUro6Men/V8AYtf1y7nW64E7F7fOJBOWJ/DlPBSYJS3RCBnA5LaskopBso435CmmPC1P\ny+Tjs0FpULQ69Bf47RHXv+V9AXgTK12IdFwqZCX6euUungXT3WuvAIGzkz97OWRGaGqetAh1ecn6\n4yaKh3rC82y+tgJYpWt6mLdj9raleyQBJ1uFwdWVUnsf/+dfEC2sOn1IWMliGEpBZWCKlOEk3QQb\ncZMwetiYbzXTOBKfN9RZTF7aj9LkbqS/H3c+qQAYbplKQeCg3XHop49pc2+fwYD49dkguyPfUHZl\nFgbzOZeQW/j8lIvrs75f1kG2RXfrSipSYqvqGp8SjPDvHL3wd/NZ2mG0LHaIG0mg/ciih9+qn7Hw\nEXPYWhJFOswmiLgdoUyiK4YBKlVLhb6m9I2hU2K9HfpcK3JyHMzJbn2I5SJWQAE9+b0DjyUKAj6j\nMfHC+a52JEKkvAne05p02nnaGk/1MXvd5CCXk9OXdUma2uvP4SW0e0lOUtY1DfpF3AKGUjyRI87U\nRlguRxedaDyIv/Er+OyN11YZwEfvDi4MqE1o816W0+OeL8tPBCzytBVnWuhkc9wnijE18uqCfSb8\n8odutiu9uDFz8d+JXSjV7LSOu5QjouGbsmIfe+WEt+7vPkB2ULnV/sA3W37eHvat9uf/6lrXbEMB\nscgvH9gj7gfnVY66tGVIvLl2ICHvsPIYwO08FGz7lcER3h8no0g8nelO2qKdHYFkKmy+NhSzGziS\n3dAISETXF4/ezAjVj9/S1GdQwyuIqwttvsZ762j+iVf0dbRWt1NVCi3xGOH2vR7Jk8FnjbY6Di7S\nVQa2Jf/A74o4lpaemRlYMfwpkIApjX8D3se1h4buv3OnK1gOZjauVk5A2Yng5eq96IAK0ndd47PS\nXmvIy6nR5I1RRn1nIfdDkTr3Lng/f9q8etL17YXrxtM3l+lRFl+GNfYKjTcjAi+B+2JxcAtZfDxm\nW2lmBY0AWPm90geNxjKI/KGTVLHszKI/e5HOEUeXYQKcif0hMNpubhQvtSPhsCZESv1UmtIzfbq1\n9k58zlNq6rXzF8DP87ksk/vrtgHLm/4VTfbgjXg/xX/A0rePI2O1TUUZchLtgrkaYjiYR3AFi5Zc\nACktDnPXn3jFYyiRZaduSkoob/bZ/aLaWKGOvsPUi8wRYw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protect end_protected\n", "num_lines": 1194}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nSS96R7wwFQ/awBJYajmb1uyxVW7Dxe+Arw4icTEGgmn49jUuwRsWmvS+gH97qfjXRux0tm4UqqDx\ntyk4/LtkUg==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nA+Z7s4sYG1dC1S/OLd5onaqChDDoqDKxIH0wDyu0FbLuPuh2W2mXAUgA6ygUDyPxGR1xLs3AnLf5\n3U/y+fEPvjbByjgXYRdoaB1qwaS5zdnv6ZIRFF0LC1q8dbQM70j2RSMZ6Bs31wvj0c4OYXETbX2h\nDtNML4rTAuRM+iAVpLk=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\np880H0PUjXmUBTEI3c/dRMxRl/IL+XvlWrRVCBPlh6HVE/9bghIS/wvhgyOQ1mp4fyEUGZHgNQPX\n25j3cqsyfDCSGvVGO/rQ3RvIhdjhXBbmfxZXGx5UxofTc+/fp7JQTUPxhKk+Zmp3B6J8UpkkRaQ+\nTlbH9Glza9Jhze+cKRbGwVPrfS4Rk6pzkwHnm+iB+WGLJnSJVBVgXGfhp+ygbrBv+U3zrTXgsOb3\nxSJhSd/AWJ+PCYXQ27sJJr74LZYIQx/gg5QzMyTEoCqxw75cGP3bD2xXz+cFe0EdDkJH8sFvd1LG\n7SPcDQ9xmFnq3WPw2Ghv6DnJe4/yMXGiVRDxCw==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nej7XPZ5hWPkq70QwibQmqqDg1SWNzBrsMbYSFestfs+BR9J7xzmVMkCeifHuWqh/wSvpJXMW8pOX\n6HsD+kakwLfs8E+v/+QJqlLtBdlE3y4Pqmiw2GNPbakNzU8DMNQXOTe2AmJmoqO1VEHW3S//PRDJ\nqs4qvgIM1HXRfRRIgECiAHz7eGE358gw007G2YwbitOL3cveSqDocjOGV3jV5HepWYKXINH11Reh\nBMkGynjTuYTMJY/92mdl1ZV87kDCsW8+FHqKhOA1FfPvj1RPIfsKuqgUkZvW2pAYk5eBuA+vJEkN\nxVCniFgVwsrAdlKrWnw46FoutQ+m90CDu8Kygg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nLMe3TxzR1Zx/ByHI5/w6/SqhTVkyqBbjVaIILoDGOy4Y/RehV35vNFgESx+MOdmetaV1j08wlqer\nDz3Rfr2Gfq6hgHMLEHPCaIF/5SymT5AVpwhkmFaQdge1sI373fv8K78kRC8JGM9DNSFOClhGJDQC\nXB+yastK7IXkt+VYwM7nXa0xSHywkBIAeivPY/BwBX8XfbLzv9zV6rh2SAW84YIp2jb4kcYm1Mqj\nYgWPATpqkdqbBqii+7aziLQkRP/MSmF7cT5UKQiHxn/Ns1lKMenELV8RgHq6jdkdBs1uaoi1JQKQ\nfqmUv9kYnWWDKWW+rc0V9APlL62HYOLDnbo4+Q==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nq6xSi+pTFm18WzGq+65YbFhiK1j9sHarfxu6mSyjDniOO2/jW7gfvXXrv+B56wzSE9P0346jIlVL\n/B4h/Z+ac0SVqu+wV8pg+OJDyBvWhtnNYZI/7k1BSUWzzR6flVJw+lEcue42YZ9yoX/3JUlz26Zq\nBi2/4jMu3LmppUWsrAo=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nOQtIJXostrr6X7QDA+MBULvA7CIKk70kDF2hMqsQ2sI/8QR9LMuap/TXdjn0XLAZTkxLKNLqD11T\nxAlasu0+U1hOXgMBxoOPU/EUG1bM7wR1UF83Qhigm2Qm0c5xtp78LF89EgU/YOJtHjCcMSpExbax\nGFg3QnSgmE/7yqaeLbA8DKDWxW05qT8jxOwcDuZ3zIdkL3n1NxrWQjM3U5py6K5PTmC+vcoEptq+\n7ZI2ka+SP+NX5R9IadM4lpUB6CqAxroG6xIUBcSx5r2BQ2CrzH4EcZiQVNCUwYx8tyBREplKIsC0\no21e6uMpC5pDqqckCzSWGZns3l40rTQV8PP6hQ==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25328)\n`pragma protect data_block\nomU0F4cB12yO2ZdV+t8D/whbbDWmycZw/StDHYdtlxBQqHD2Rt979k5WQq+7+dcCL3+IPJmrHRVW\nGmVBB+3psg2CMKD8dWV8+f1duqdQ1ruc9IDTn3kyrMv8WzUZr2BsXVR7LoT/8ARttZYBzN9SlXOB\nIu5fROLcXGXIC69mZclXZ3kqw6gKbDdcIPTYaARyazI1N1JT6MpiPeX0B2e9dgibZS4NLoFf1C+8\n4lKKRF3P6Ms14sMsxNaM1rVifA4iQ/Ak5XeKnn27tB72RmlJm4ojRMRkD7cqreK6a2V7DXB0zAWw\nD7/HzKVzqh1lZF/69Z53r8BDyCI3oRPiIo9/2kpnZMcnV87uI6FNq1UsblfLwnFVkv2E1TroogPQ\noUVZd48nZKP6G3hipN1IkHU5wYHpG7S1px7d8HSx5vZKl3pFpv28aN5BxEuhvJV9FBghlpwG57HM\nQYhtJs3QjvuUXcTQo6mt6uaJkEmGMltqmMlwvreBEPDAzXivRCwBt4lZjduB8i1eYRSuMv0nI/Qx\noswjFa0lFt6divro4C8AxVAJIiIIEzOrht0zHz9Ss0+qCELQPEGk5lc3IDAHgjbCPWmObsbEidaS\nx7t0E/Jz7yoYsInuJGfETjIEklMYJJhVHJH1GgtFiwCDIXtjIG7Sv93vg8+dTBX2fVHjOswe3xhc\nlJcoB8yU+RvIb4FuwVwKcNAPT/0Py8wp2Pis/gDA1dsSpGioBjVoz90+AOI7ltbVQYEYqMCTLtJ8\nFmzXBx2tt+iWxg+co9z8phmO8gLRzjKzWoLbGSZBBw7G+/VWR6G6lGo4ZvKAtDdFvu3H0Lk06rJW\nTeOr2wSeT/Kd+gQCC8o2Cf/8PyI3xP+tzcDP+L/jkEdaFrHo2Z7v+LzFwcprHqiZldZmlCwK78ks\nVjmAujF9tHZe3H3Y+tr78xko8hSvvPzSklNvrskK6bA6f7i7LNvPXEu3FV0hY4/9kDRar+ls9hff\nDSRygqt1uAtTYP/7REZfujc+wsurY+MbzHHxp6jq3EOwSgRyL2cHXx4Vmo62A7wgKyTWk5EdPIPd\nr6n847VMqI15sXBo8nYyLWEkzrNVtVQEvWpeA5oqeDEHaduoNXyXlyRSwDv0duY7A3m1BAFlglvR\n0N2sjqwWzKhYFj5Ns5HQQBtHh9Zw21QqT1laFBjSz7cAsrFrpDoB8SDQCefHnKEzSHYnfb3WRQQs\nxCjXR4TlJRnLnZMyHVfyYtH7USi2/l9V/Yrd/PO4+NmUgdIxGbToTlQIBx5gigJGs0XoaWvVskwf\nNXlK3UaoOJ85tDPYp9Ejz86GyMYerWLlf1u9Hn1BCIDeuOMqiHVvTkLMoY2uQf/g9NOChlcWM+hW\n5AZH9uc91mLwBKTrHi1k4EM6CVoDhS5i88eLGDj7WUosHcAYcjaiNhkZ97tZbVK3yKkVFEtdjoL7\nh4Bum8rQwYxHNx2gWytbEbl8qIT1k0uisTMGRDOmApn7rixESdulVbMR9qGrvrPLqY8EtDH7jJY1\nlS+kchhLcPKLemI+liKF7h5VSUNsc+PGwK4Poi/2EFa7XfIpHc8E6l0gZt+qwW+qsA4aH16FPrxe\nsPlGeRTRqQDdA2OwzUgpbcvKx2JTx5qswVjgMW5mHt2EnLjW6SHvLc/Vzy7fr/O3kiV3uy4dyWGO\noloO64jspiFBJnLbb6eaTNqyAvbpj+ZF/Bw+QrCdIb0EdsWj9GmUUmsmiWLI+Lz81KUCzEc4H+Hh\nGglDloivAeynD9N8HFp8OpgQFagNeWtfAonUqCDV3B+hsNXo+x3Nj49PDKdY5aesqlaahKr1fAHT\nfierHFNbvOT41MYGioKDQPLwon8ptmydyahnP5MmlDi3knIlULZ8de+mnbKISNCyvzua9eAc994K\n6B4Kj8/swf/hAOZxTJ+HqtpK/DgmCA9FiU3JYIsSB3rhufuLP+mFayZ1tK7d2t3i+FZt7TbMxR3w\nuZgEVxQBf6VU4vQ+r6EHuytjSggM/20/7CtQ6JVqeRD65+i4n1E7b/yeCapiKyLEHcF5+TolHg4N\n2IN8M3DjZGThrN/W4aFXsyj4YqaVr87z3w3GM8FGp7rDv5JqVehoF+ATrA0OcYRvBVPsgnnvlPOg\nWuMIIahHuKGHwW50zPwsNaUod1E2fk8gLhkqMqiE3SQU2y1T3hmK6MZXN9GSwJ5IIw5eyyO1FWGr\nbcgG3rsONmih7ecMwUp42jLQ5vSszqiQ+yHXepZzC0e2VcYZhWWEGgQ2qAP/mX+y+xDfZ5e//Dp9\n1vw1SwFlk48f3CJcsRXrWfDocPNxPWQEcFtYDHSPNwEAWpRDWrd1jQdLRZ7riiKEwygrvCTBTy66\nWshkAAe+V5my9AeXa0Ml2QTFJnaGjonlt4LTbDpP6lrDNO48TxYvwTeeqfPcLaHr0uKQt7YHP6Lz\niQFo8+yjuc0zEfQzoaETRrimF1qol1PWK3Qpfih9XrskpouGoT/zEL9vl3TEyQopv4PUZPj0Ynk5\ngLrEEhd5zkdYa0GWHcoa4Fot3qrp3UwIaXp3J0srL6FzrCXbDBf2Mo5NN+P8lk095AJm7GbHDjvE\ncDphpGwBKdvmbBEGbh6fHIOHTAhf+Vc8cPPX6BHmHbNOHZD0JlWZppGdjhHNpBNPnIBYS3tfqeR0\nfpgTvVPYXHmM322F7ZoQ/fwObdQAoj+tk3q0RroBJxQWakMIeQLVoja31p0u56OMldxuQgfF/7kr\npJIVirx6SAQcDVwcFSqf13qBuM+0Ol/D3mNr7ZjwWtpprSUZlH21ailV+zw2WyvthkiTp8YWVQBy\n1q09ZacNze6Y1ElACgh58iPN4woxeuIgISJzdoXdZHKr2rmaCQ72e80pFTsQDzTlRLDVRkpqAnDC\nxN+Mwpe+Fkm7f7w6HD9kr73bageDnyHcFZXpA468LRFJPWYg6wq9iFZ4TJAxrhk7MUFsxJtUscnr\nxLex9FDXv5JNgmR/UE/CD/ih5AN+x6gWb6/W3lszhJtU5l4b4IoAIBzFNDGa48+PO6Tl/fTG2S7N\nNWLwVUe5S3/022dgOuBphepqPGBaEk9aWfzhttADsYbd+EEH0DLjYEUNdOy0L0wxxD+dTHWxJZSV\n0ChMWF8mHSAFDH5fO+Hy1cRtVcPIRrjGMzyyvJjDaKoXzOfyN4HKL0d2Zjm/gFo8lez/ydTkt/CS\nxYar4AEGp/BN7QDDP5IH+BMU2l+zrhxqwQPo4bLd65LBxuQDXhUginwDEo82bBweomEKB5ujxPvH\nkuKtvrIWHrfWIsK10kpV2kY1erMU26KgDhIsF6eqON5qRijRBS4IWa4trUlIKxFe0tR1G+0lTAnA\n2b2zENNs3Owv+ZV3WgEeJpcYOOwbsG7qq3snQYse5j0ltcLyBO+dYgzePpcE55rg3YWCCn4hjKVN\n0vSNNutZw9QqsPBhK0qUZEvot0e3Awajv6HKZPq73c6PpUOaaFCTRl7V70cOsdlrUwteXMQJV3F3\n1Qszx9GyIwFkBAfl5tn7jsQzd2tUlf+3rxISOSF4by79j8FsMlkJW+++qk29OrwkSW/XexL+uk5x\nDWSc2fgm68pygKu/3KtuFKMEnPktko2ej3qtKmVvRPolck9fuCxtkXDMY/lRA/cMCbVJdOST8PNH\nltx8N3OjAHjF7qztXIGEbTgETs6qdtIS8Aaec2vMw8sZrpkkrCd83yeYgg89AlK1PMMWYpKw37mq\nTeNpJu+HCa81ry2c3bCvCvpF74Sll6oEliNJLH1QXvcQWLSiz6bAPjPvZNysBOkqwipQO7FIFujc\nH1i9gsKzAISZqDQ4COwcFkxKsZqQ+3+9LWF/SyoBGXGllUl7fn6Y1xtEzEcb3vTq2Sqz32OVeKu+\nLWl+IaE2DFDUpnM3NlaxYilLHTm/OtF29z+8txLIi56qb1wlsAsobeLHB8KpgUKsEzE/Edpzr+k4\nykpmm8XtbKx+rz1FpVqtx7C8k4J7ebUClTt9AaE+jJujIyeR6IIX9uzQBNiB2+o2Tb4XsG9P9SMb\nGbauD0yjImseltwlb22KCPcxWEUe2/7VOir1DkE9/wbtk6Q8eF02TJxwTZv/epiH8p09Zns7H33/\ngS6CyE0neXPK839SOHGZCftWF36xqrP1yS17/OA6PI3s/CTLfTs7YTx2codFR4imZz29y71VIoEB\nxtUhCuqGobdRNa2lmU42q3mPHQLOU1UisLPDeDI8qxbUi5FfabTKeFW8+xirZfgTs10x10q7KGnp\nbd0QGVaqot1rOHQ0HlG1SiSDeBp+s8HaYAdx9PmjO4bwDtiQdZ0aMJafmmYAYDSiRxKXnWvwtwJv\nkDDIMdqVSgH9shOr2WCOVuD4hebJ4kxzvxLQQYK3OsKY1CUdS6LMg1EBJ5fzEPsGHi2w0Eh2srkc\nkFRoCpIPylVJ01RZzkM7BHiJ7SsmbDucJMBZCFb8KFsmi6QZ4vhiXdTczreE7AXWtxd2/bUiG4vk\n+rP8o411sER8+1SpV3MujyYSJIwyGRA97P3vw8pDfsF+Ktr4FQ1M5S/UvCCDYU1c1fwEXhRTig9x\n8kRj/i/4u19Y7f8pW+4TRIfXSmqpxQLvlViUn89CBFT6NLiVqBHxzowlhoWrhi5zpYXxw5SRXBPZ\nsPxr44yLN8Onh2QMGqi/H00xNhG5pB31BEfTeuisYQiVZsCmsDMNFCZSUIZJ/+qQK5aL6ASPafTH\n35NsiMMmEtBVPcun5MPDeCi/5Yak2R3SSylLb62ucpJCFEiNSW9XXihs4lvRiD0m9Q35QHQaqlWN\na8FAdZpgxcb9I9bO7md4qPV/TFLA9Fbfw/ttXdf1LSjH9WiYpKiNsii9ttBH1On7jV9IE5ZlK9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G9UB4lpGFa3EvQQylVj7gEIapdNZX+/KvWDE1Uw+Mx1ch19lMWPerej3V2JsR60z8FZDuZBI\nrMa1yIuu3scJW/W9+zxr1+L71th+wD0N0930H0FW77WXKD73hpu0itMeJl1kTLX0C+4du/oXwiPP\nkKFMnSlhnmADk5Nzs4kXX56QHHCbRnr6eMuvZblXK0EZHGXSb4pQePS8267+j8iT4e78/dD60NSn\n3kcUWmiDaD6B8DhgaHuHl3jgJoT7tgyerSxV1v1ywnD+ooBqWrUAsYnJXP35pM9lvw9shjKGAAX7\njCObOS8VJZci9eTJcmygBtQacBP0AzSh8d0ZMgtsEerarYOHl0VaqrURAHTNs1zfXZ6atogVW572\naPtBaqUaUJB4BnKzRoP+YM/+HbN+k5jn6HFPg/wFHeOOsIPE4dpfWM76Fj9OndYwBoJrRfjLOqsu\n4QbnGR3BRAD5bq9p9CIqMna7zaj6r1Kh8y3bz0JLMChWeZWjoOnjrSOb3n0S0OcprlGZwIkSPhD9\n5e7JOYw8xSO/acOGMOr7XhVwxsvj5N71yDY9oIIxCmp2i5mKFvjdFKT7b3ivsMqpU6ooUNL1cB3B\nct1l8a3kFj0xj3Vjz0ipLbKBkR/JC+iOtZk5LGHDKd1jaSTRl9nSuO+bV9kLdDxwvYHAm3PP+PD+\nzXW0fPnQVICDYqkZG1xto1it9QOrHjy2vBNh/0ETekywdX5BIejkFzloAAm2ddh6NFnynQ81RPOp\nB6Ei5sZhxqlniMTJQNFN+PNXyW2lrwNTLew+TNDyj9rIZ6ETik2SHQpVEwsfSVmzfDCWqm0kta9i\nAjvtzWWnW+IsuGEsEL2hoy4He54jqi2mtn5jgFPt8o/zfixB4kuNpqBIoSoWJqkPuB6IQ/KJWlFC\nszg1J5hey/xx856i3HzxFJd9mVXALJY1cvYVCa3JSMQEP0sUcICrI0GoEYQ7pi3w1mAa8bB78jMD\nrfvLju0deZS0V3tBedhCRm9yt9XbJCp1F+62+qLtP8hSRUC/gOs9rvVULoMDmyAEgrf1nsbcBaRM\nQX/2dEMQzcBUd2mMjdpR0nCeJ5oxvFymHSOvlBYVhLq4CaROMreoChqIuejDpaErVFOfvu3lq30l\ngiYyAdBlGI+/GenmbO8fLK2EtGigHy8pIzuFQvaj350cfHLlcO2jHrl6UbUnMLdM/S+aBXd2Dg2E\nFKbI8PeZwIJrbP6987aJSwhWKLNgMNNjCkUqfYJ/NRB2eSOiC40TgfhufZuYh1fA7Q32tdQqW/Xy\nNv5slA2fH5SgHmwS9Uqxfc4jvp7SUOc7EToDWJKkVHzNtxfk+PpKRbG7gledErTqMBqWRm7rkwhC\n3jsX/qzzTT0uawrfLEtK5qRoYxdoZzMRcK6ix0rVWema9+AZIkOkf2eQ1XIts9qHSuNKuze2RXJt\n7XTiojoorg+kyigvlSv1D+o8cAQrd78YiWvhEj0QphJmFmC6jy6xpe/6eGwfy0a+fsjgc0ZCdt0o\nA4sV8eOhNsGrSsGhMLickahQrinsXh/8ILbGqvKtKAbNVNLyJk+6w9BTy8HoYPwRccXIahYFpgS0\n7pjDe1Gyor2dlKT72Rs9SvooqSu5tkPK3AFc6o8oQIzNtMx5dKNBHmDyeQntb/GTk8d4H6TAExAo\nsrSIFYwaxyXWQsgbStzgbi1/n6R3kvBFDAMD9ttwZ4hmPlj4sygAgzv6c6CfyuMZpH/keY20cVAJ\nOXijLo3hPgVD0p4n6FOUdu/JYgrTsHnOzGhUcEGws6R51FcuHxqXcBA57apz8QY31Jr8lbuhCmpj\nTNvGlI0SX6VE/NSoJli7V68oxvxAR58toqGrfJU+/YwnuIenC07xeN+mOIKyGO3P+4F7UuNDCPYH\nseoQxJua5/0RsZTGA9NHNAdpXJzze6l0n52PzQItK4epiSZiE7ZHGKz1YfRLvAFBrpIT1ArDhLFw\ndOB1iZgy9GNqwH8pNMvbfuz/+FeP1oM8/SIDdLSv0WDwM33gsrenitpREzjdByQjjFRtunJe2kyk\neQ4GhszWY0Dhm3qNNUlvlMc0xXvIiPl/w/QE8JJ6KgtMUdzTXgWd43HK+VjPyg1yJm9SC1+o6xlP\npEt6awJB3VCzxpu7jVf2OMsrQjiF4W728yfUJwPQUfr7VR2E97zmjsbiHbf1fo14acawqG5MHQW2\nZsMwfep7N5NAIX5rav2q5ZC3g9rfOUVkwnvp2F1HSNOWxKV+jJz7B6Xb5o+YhzoDd2Y3u9mZF/cD\n14Q3uTuV9Y/ufXtAhC372DYtV4oSeLNkdvW+eOTDr/k0eKWqnidKW9xIeLpCtmtUEhv+gSYNMZ4u\ndj1KJgp7/bMQMYReDRLQJIZTkcDnKvrEc8ObcYZ4GV1OwvpdWTtkiszhRjsUWD4YA3ir81byw1gt\nZKff6VWwZakXMdmcY0gcEhHqjdELSZFplYxqXNFX4LV5x+7eFjRz0S0IbvsVKlu5RD/Stma5/ZA9\nG5dOyFeuG5u5jQ1wu149LA4HvM0m0lg8BEG1MMOo9vjgOYEgfRz3sYRtSz2M+SnoWlt+o73somiM\nS8u+Sfiz3Nyg1GNSWlT3LLhfK8pxIEkDKkLPjRDkvjsBfkIr9jYYnK4PjvOHmKaPH0ZTSQzVm4M/\nvMz48765bXGQd4xL77svOl5rK8uyJoMmyQq76t/aXV1iCMNLgIiZDHa9eodbgsJTeLDB92bf3zgb\nkHDPhp/5Y96aH08BelfvO9ZsntgDvmOi0++IymB9PI2l3eMx8LjleptsWU81WDExuENmSPn5b9V7\nww0PkB4L+OrwEVDHPmgQvzOp/S5lY86506IzyZk+EFaoisJPL4Ix7TXgo7u2wHc8Kssp0X5YZFj+\ntUOk8kYsuNRrd81CR6V+ukNkM89t+W4aw/ajKDTT0LmUqRhMGQvh2hOqw9UksTCdMr6/WgIz5pbm\nKniZXfCh3cMZu2TysZd0Gmg/MbZ6ohsBnlsnrft6p/E88NNo66e9qomw1v7eVWGswqmbDwalyPv1\nxBVjkSxrxfkyLQB1YfibsLY/wqmdq7CHSlB0eY3D5meq6O7XDf7jcjnKVJ3lnx8bvmKf6aT8I1cj\nHtPVm31bdpptslWZUHTXnDl5VYP4NJJQN/JJQ+GcRra/Ik+SxQ4vqTeRuhOtQb3NjBm4FpDEKSSH\nj3/IaA/l3KdxVNAbLRenx7/pEnd94HpKkLGiH9J++D+WtogNWlV5Ran0qN9ZVxtMgYRQ2CfhS+M8\nOoVZJYYvVWBFHmhz0Mng5gkK7LODy7ij23SNkqmbfMzeniulSE1jAHHSIgqxdMSNQ4Q4AwN1m4YH\nQ/xsFz07AK9LzQIQDv7U9Wr+nglKxlsXV4hcMSdcPHy6cOcH1+LQihIVUm4XUhH+8jEFRcwVzbKI\nGfP3Qa4PE3o6CHTTLgjitYN9jl/G7Y4dTuIWbIu9jgPWY/Z9eP0EIIj0WKWsFBD24E/QTfUUgNxH\nGe1uU+XisJ+7XHwnFN1GVgqCja43OyD+CIWdiYhsTWjUgpJ5E0fxc+AHqzHFY2a9Xj1wfDPyxyoA\nW1S9e0KjBPXF8hTpLMATGsbXCltlAQxJlttlBFZKCCAsI7R5cW+xpMyW/mU7SgBUJ2lPHybFdvIS\n/kkKwhO/kHKUXCYtD5Fvgg33/UXIA8UcEHrhUraEik9Cv0YEmwcEdEM+b6CMPDjwUqHMLLWJvB/r\nYZOfvrPtNP97tOh+Gzilb3WkMDsLHUw1HwbErVEhj11lziLbaej7JqgEO9/M8AC27Al7FXaRqDYP\nCuxwoB43b8tGyEmDFLCCjC8Kk1ztEP/gVA+n8Q5l5sev/rTz30Zxgwc5ZZ1d227+TLCP21iPo4O/\n1ZwVEJ0/mri5mBLBOP3qpG1jjuxhpb6xsDRuvbXY/bu6nxERErD1bIVcywy+vBTa65irGR6PBNhZ\nRLtGiZQ9eVfYdXcOnzksALgbMY3RihTlYwNLoDhz/KfMFGTo/3Gah8gk4zf8cCFZO+jFWjQ7l6nV\nZaFpZHFkxLWZxdn+9jKXsFEObkKPKJ01RmnwsIrgcszIiDb5qUx41z0djy6IcBO0+CJ2IigVN/XL\nADeVMeG/d55n0yNPBJtXwU0HxKtT95amNObp/i3V/o7cGrc1TfIfD6ucXn6RtcPGYh6v6pTh0wsn\nmitC17c2iHIWWU/b1+kGcN6VSOkti/66NmUcNWTQHUiQ2I/pD8RWfbxqGNXn2QQhSwST+hAve3p9\n3CqIBPuTqPwBNNWr2jH6IeaRn3adw9H+MCX1QYAF7v/zF2gaYnQVDTduzTN25/V8vUg4lPbOQqG8\n2KCc8NqRPN+trTzRMrh0HIeK8q/+G6pncDXe3PngfyXmfFpCIJUF9RiAs4/J/Yu4ZUd7Nso57o+9\nIA6EVndlXVZlK6nkkZRzhAdYfso8SfpArimn/HYTgGUpfs35MOvKk7zmKqXAxPZkcurMVQ01YS8u\nONptVvI0ZpoDxl/FyLoSGTPo0BzKwwj4UnI6xVjdsT0V5swbEFntLW9IArikjcP7AbfVyOXSats6\nTNoO3qGEve+FXkt/onl8a41AgCWlL00twIoOs6AasHipMeQkOgS0ipUaGjDKcn5ceCWM6+jm2JdC\npbP+MOMtLYYdCyLcULAkhpPwRQIkGQeDcRnsPAjuZWfUHPBWkwkzIHYn2fDi84yh2FvppMqxrLWH\ntNcrGlgWvpHDCdojVWATJI60DjXrYDvJwXNW2kNUC6ZIBr917ItTlQ5surQtNdLCMVKXEWoQNU7q\n5vXU4Cj19Cb84ao5ZpC1dWAI/CNtZyV+9D8HsSf1oISFMRwY4cOAnTDekXrOj/Zj/1qLeXU0HPw/\nuyNcYPiG2qitycy1Df7+/FuFDukKiLkrUsbkdvhOeFQ/LOBWfbBPtNd3m+/57kevqzQpwSQ3q1JL\nAfhHcE29kLQb6ZkrFywzimdO1QUhQLrDxd2C7A+H+0ErTsLOBt8mTIf0bHXUMG8jo8SF3fH3dcW0\ni9VqjocNa8gvtiDGpX4ejz2/hkdEgc50Nsogn1Yop21X8oNvDFJ9Z+2S46IilYBArzBIMhPc7GK7\nTzaIknEGcVckL+lip1TqCZOkxBQdWju+T9/x2rLovnQJScWz/DRT3QKfMf117zA83RxVQrZxfQw4\n15AcEPVUkobhsGOyWd/uonrJ18Chkp6zj8VX8Ha5smr+QpVq3eLzlb9br/VOnrAnUSZ0bvPvjQl1\nI6+lK7EaYF1Lef2z/LfRBTYgqXAewf3nzpmM0wdzIBK4+WCChRBH25ieuAj6DhGU/4dNd5iYkNKw\n5UFjIH0w/7U/+ugyHgDp+nC6JDYtfubj0m0KJJ87RJMmQ1mTNarOu0urmlikkD7+HDMSgYyLEtuQ\nGaSH5vSHsJNe1baNRTA9VZqhlK0zAIBSMEOEhwUqnE1As8+bX9mBFw1Yisk7M/bpzK1mIF1ayLiJ\nGtRL+mvAF7ogzydkw6AZq49ZnkRye/Rc3FSP0qOsX0GAdCjMyaPoSZ919BBXkDatQplglrL5Ap7G\nC9SnQ+UEph9gWx619N+OqIaVd0Sy4GHMXVNXZoWzCGStmOBFx5wU/Whmf+CQQC00fC5T2zyRX0X3\n8TKMKhvJpwWVNtsQv13de3iiNlO1r33Rr6Rz90IILkiLnaaOlZn0gsuUdQQFv5nAq9ZklwQU7St0\nUuSwd+CMyM3cBpYc0HdW3qNwu+ekYlkNKdIFoJ3e0E7qqdNgrYC3Gf12pJiH4lzbRTPZeJzMtMiJ\nS/W+W2H7pW8uOJhZtvIHy/r6/12etJ58zmR/j3PTISTH+55NnYBSGQhXfLN/PrZxEkqeUV44ke+K\ntGWb4cvQD9qBtaL/2JvQzWdwPwTNnq/VOMDHujxwxkazRZQLoavtItyYdaNm1gt8xEzjW2jnxkHL\n7KbB5ZaBXIktxcKqBK64RnziU/bgmFdkLltLuHI55XJSKFd6m/eTU2FmwVMg2rvrgS5i4TwtpL/a\nrsSKWWQCHSIYhb9xTqrzYigYpHuKDjayBqK9+OuA2rTgDdKq9oaxyR/jXySiUxcDh6/az9/NMLQe\n+KGX2bvG3wWdxOs215xclv2w75gXDDOqmYINX+R6Roj/5aUgY1dVU4YCrTi6JGSdprum/c8R6r3K\nBuNzCsiwGCuC+B8q8n8awIiiACjqG/gTisr2FnyUMF19VU65vml2ClFxMEIgiDsG+7uVpVF7Ks5f\nybAZ75BxISPCu2Liw27/nEs4H4aIfBZFm9ffGbAJBal071TlBZhk4rtNqVmQHiEou4C/NvmxcFNm\nZdBkKqo+rmrY3o+/7PrhbZPAZmgUbjAtMHtVne+vge0EF0uj/h3Sq9/2W6bgen0xIv/fzQVSGlPd\n46ZekLfUr6UsLfTrPd3ZFy1yrg8VGInFaN11yTTkTPzcD5p6MzOwLm7UJp18wmNmjk/BlTQ1zvvg\n7e9NX6SRJyF7YdaKwCQYxTQKm5lvUiBxrCcChQJdg6/BG+zVTZT+8x5ShfbbzcXnrfZXMB1RKLuv\nQilDIlQD5VNRgP2K/nbYxsMDjoPRRuQduQ9AG2NyeDT3fGzcxnaUhF6cMSgXV18yfbNBKrl/ie0/\nH7CkmgeL55l3iV2HtsERAx5kEki5NSNovvtZ+jLzxOiuMFxGe2YRpHttIX0l9YscBYzcuESoumlj\nRp6KFFo224Mw8LZSYX0+QLN/W8SRrww56eKNDbbiVU8DBgXEWLXhS/1q/+SoMLbvnr00BDAfbScp\nMOlo9rgdLsOBwD90jQAAvWVk42DxTWfqs/2Q6sE5CHHDEeytdzchnA+2sHM1Ua5LyW8R735BypzF\nyS7tDnyBRxdi8fLOqvDT+LrkjyQsdeCPaZ5HyGpPW55Mmqg00U78uV99LQOwL3Lu+klhr205h/Vh\nyqRvrSBDsjXlBcERGNTb874qY4U2oIdRTqkR8JatCImB6tOG4z4OGkZnCaMespRfx0xh1h/b8c4U\n0m3cjfx+GyjuXBXKNzK0L5f26aA4HLeOMwHuQtRxmhUth92jdHCtkyV5fzbr19dt3PdWn+DnghNw\nmvRsWnJq1pTlpo9aeDt3NDSHra0iEsRfxb3UD9AeHjI0+AkahdLHzNLPRihKpE4llriErZtBC09Y\n1pZq82vu7ZAyYxw9UowxtlJZJ+RcLopN9S34fJ9APRQ66/uuYuD68W+7tTiTNyZHoKkS7FY1Uu6W\nHFyanD61UeLyH9apnXw9DwRQisUpKCy3q21CqCEiWvQ5+C/vy5qC2N8WwBSqj61aW1yQyiYWkBXO\n4xQU+j7sgnBN81KG0kSJXHWcFk/h7X4X1tLr5Ggr890jmGDv7DA+VzdZ7Q3fTJofXmuTIgU1iE0B\neJdgyl1EXsPbo7hUVFVd2EgQRtj3vkHwSCjFVF0gMLaNVf9LcazqIvW4HFFI2tt8+9MFEyenBEgB\nh2xqefXa5q97T4n7zl52mZa4apuhFg21ZyMgeHFgcvbyMJ+BkFVkeKcVVLVyBkZ33V1fcKy90Lv1\nEQIYUQyIACjaEpO+V8EzSUHzmbiWHkouuOe7aRlkH8lTQFjwNnFjhii5SN7T/HR2gqfQoRpSLNoX\n11xPlONY3eNXFfbyVaOKUMCenFuAqN4TTcGrdAeKnFQHvGSbS8wuxr0L6LwRRtmN25YOmq9n5BxF\npV9Chlz3Nhtm+6T4ei3j3vremc2G9BTq8PZ1YLQZqJRyh3Tb2IMQ23HCLb3yoQ4ZpPg1ZZNymmug\nVql8TPMelPFuU3IEXjpgy0SDbqUvZKcP5PKHTuVpdY5eRizzWbn7a6akaK67C//8IU6pBT6WkpLA\nVDG7HQ5KKlwvriaieUvWovcdt+7QusnnssrSWlMdK9jrZ82u9HUYHVKV8Xd5hDB1jYVu6Px36hQ2\n0v1g782llhV76QhcNlBHkDU2CsK3X555FSOcdMTD8BI+n5h0GROXkhSGlodgZTbWppO5QN3jaeWZ\n9a1HLU6dNMfTCEeOUe88KwDZPEFqSG4p0VtwrI863aJ04foZhZDyAjI1PDUNtgBZO2Oz+DJyhXaa\nKSEoR2Yj36JwX9JPzW8mkGxRb5Wx9N9I1/Szbje9t4KwPjOml4qWWpMqrBbpyrs2396STi4KCNLQ\n8dD2nwuApS26e6KvA3swEStkmcg4lPaHt73uL6N1VQxViQ2EEy4rbFy0S2AJzYqERyU+GtstUOcW\nh04cyB/2ofzso/h7nK59EXXXc8lmeFNNll2++rzh4sKZqQajxs/8Gcj65TLhk+uPqyAaFKmmSZeW\nd6jvCOCCgywB1EHAYOnOb9vwGGRCO3JGCLmC7QDTjTOm0FkqGoMUKYsee9Jqd+AtP+t17eVGuIVY\ntAr571S/EkWBcgDYPevACCxmnBp9OjNNBOskcVRUg5XMIim40rW6rv7bFDEDgpcXtBTw5dz7m505\nEJTbnrS+//j8NK4fgaIOl5bKD5x2qP1Z5CcPQc1rxLrkLFrTy8XlEptKXR0t1lQXd0Wkef55TxMT\nqs89vIeZfvIhprc2C9fK2RVjSYAhkj6Iu7TCimjFyr+HmsOsOQQZdQ50WNhAid1TjahlCJ9yCSM2\nSFk2oFhu/qBAvz5cPs0x6lrrRmRIoxvX3WA+IElb9TyFBPyP4BWdTcbfqnQ6XGDijou91uAVawoD\n27aFmoq2OCWPF/Fp+D8dcmb/XoPpK0SOEHaBU1ILRJkdRd6Ys4bq4isO3Sg8vkyA2iNcEZ2DtGkV\nH9IgbGEg1Mv8sPc/wjFMhb4BEqxNWQEKiYgDyA9+0VdYpJdy5X5gZnJxYxhzpEOLZpbbnjd3UeK0\nEKkNXwA41V21GqTZrrUlF76kn367l0KZTNgiNodIaDhxBkTPLMOtpDt75KoJ4Mrtz7HxeJXlUMLs\nj3HezUvOkrRldg1d/XonaIPRDgjcQFhIRTjOEald59tKjB5scFlrOqdI9zQycV4HLXdjifdfH/Dr\nfrQHwLor3niSXfIlsq9V9vLUCFDTNCRYzaE+LlNQbFITqmDUqy70neszXu3lowOaugZOrCx/xLiP\nss7Ja4qppT2Ctc13JZXtKVL6TKDel2VCx7xv0TxpPluSpiKZKUTQwzEb//Cf3o8HRx2YSwZM+kXo\ndb6T5DfBGcLWIujpgWhXW1i1aawHOLQMRqa/bpKAA5En4IfdYbHy0jt2k40ZG11elMVI6RKAtaZb\niRfZ9R5+Q/n0q/XlsbqpiOST0JUqHw3TQzIUl3a/GTAEM1B7E4/aXxOBXoEIBgR+lDXq59z+aZ6V\na/qDF6Cq85iXpIprWSu5PAw2ImEaHr3kZMg5pBYq2xjpYIX0L+FWB+/rlaegVs8JRRX8w7TjuPiI\nldwrcr8nj1s9l18z3ZjIvvfO6i9F8v61PVCGw+cJMCffOL1DUXz2/A4LdTO0Qq63fsJBzfrwNPyM\n4L9m0il1+TVxHhXVoSuSoXNhiIJbWut7GbW+rvTCQJjWk9HIPTN9xKxKFZsH/oRcWIyUI3ogahdW\nH9NEjMeVGwKaYqs85ai7US4jnVmxeYqc6sL6b4AI8zQW9lDAoyygkqC5NsuGZrbk5/GwdIpbCUza\nlV4lvoWrT2nzlCPdE7HqdofSVI/GPQ7EIhG0S9jqrL83rET779F7bWP9oFwAM3WXq2FD3zm2vtbh\nc2dLOEuB32W9sPfobiDEuqaCkrDTI60b+AgewQJcZ9mzktJhauyA5bDFxm/U0ffkqJaEswDtl8AD\nmAo2U8WeHnyMJEqkxx5ld5cLyF2UAMmCM6lGPtpgvknUUkNYs/lD2XhqxuM3cNCLZuvieJKxtFvM\nLbd0bNRMCX6bSVLjKfv+IW0WDBrtuJ17aCr50G1IvprZKzT/xRPVIu0p6p8hNH4953J/ghs9oo7c\nlKQ8loRvT6zSp3GyffPZJOVn9gu8lInMpJwWkFydpk0q/59aiHDXSoigjSM50xfZkM2xB7PXVYTd\nQEfibQ8bp33CVYbaynaCCaQqHVGy+9ML5q0Dsu1Mgs7ttCcpp3W5akyYcO5d8+GUxBMUe0sNq4tl\npVZNNwltEOiqD+QngAx6UkKw0PCg2lxyNyCQZ/E/symhb7OauoiCzQZVF02qMdopaQmGiY/ODvoh\nYtacenkASzgbBSOk0fOO8SsKAaWfuD6KRT0n8bSgZSPboejfoQpVOEmcxM1fFfIbZn60elHh0TWB\nclK+JftnN+AWkwQfTB/JKniwZ+lvqCsuieW1NmyUSR7ykBcRXXSA/0az0coEL/9bCmUeJje42E7X\n3q948+DGDEJc3wvWBANApYi3T8dvHoSv/xB3Sg3uVrCc6Q+vzOhQ1zgvY16rPkvBghqXZg4f/ibO\nGUrA30eB9dJYQkpT6sAhBVevG7t2YLCNsCNH/EpX88wA24JkJNBICyrhs/fbTQI5l86rmfxDybaZ\nV+C5cLUfrLvS74A9KOm8LzImz38+RE9naZuWIUwEKZtI/IqDkLJksZiw7jp+r1Rt7CnpJ9kUQ/ZY\nxwC6FwKaMOPLuelslAkGiig+MUGK8U8q/0wzWTJQgRZBSfu2Md+jmJQdLrdN4HfPGddtNg/rkqpZ\nGnTqmDTCNZHKaKyh8av5iZgAl4C5nsLhKmLgbbDFzsnrzKEv/IoHy9a2gtR2q2q9+ZmZ+TI9YeuG\nVfTbvZgjNKN+nNiL2kT1tpRoHf07mpdAkuAWMrXqddkcn9QyHYLlNOp0dRup0GM1yx0nHY/0hNZS\ngSJkzkBSDJu8fLjwG48jloXCrLjLGo/IUBDwOwUhyCk9ZJtLg5AefO1JndkWU33X+0y1xJGhoK6X\nt6FG7I4nyaqrsoFB6Ha0+UWSqsM/H+hyWWejJpBaI5nHPEZBbLwwaVm10hAFZdZ7oWB2Ve0Dbnyc\npOrPOVUmWOxTiIt5+hkylvrkGu1sQfRU1kBh7ynYIRKOvgljxP/AY0TI7Xs5ZxGJEJn2Y2H1PseT\nxvStZw5RwT5vYJxk/4tT+g9K3BU0LtE0UyGwpIDNlHpLPIT6CIYXNO/GC6vUfCrJh3qh8Pnyd0sX\nNEktZgvb5zGBYxGF46EU9bBwCX0s84fJ97aaxn/gTVv0Hcwq3cUb7U35uO5LHLjrlnUCh29jH0C4\nldzTqhf4Ch9XicZ/uJPVEONESBUmYskm2Y4EuudYmwvVcwEKCAOpmOVSfIHqvjU6EtHuvL2cdO8D\nx41OztnDd/549tkkn/p5SAcs25RZf0vBjrsl9Y1Iezqa3V8z0ZhE3rNUhNB5Oon2IkuC0Rvvltt0\np98veNeUyJDoO2k+hmaWflAEhX1e1RCZNLYx0xSquZxXD0VeaFUEObTKXdejMa7v597GFmoVPkPh\nYKH6ST9ati0TjVdJf+dNVqBRcaHkEzJcAMZLSdNRhPRTOB8J2OM71ealSLZ2lR31089Zlq2QZNaj\nK/viSQPz9ANHmXy4Y9WozP0JCYvMvkRgeF6hmpUEozNEh6efj09VSvAQ80lRJEP4pkFKJoahZ3Wh\nsGB5Z+pR90jHHKeMmQM6lKnUbSlr5YUmqeaSnY2FH60mUkKudlzklCc093iBPlN9fpdkbyQYXbZx\nfa5JtVZLHRLhAJVlIE/gR0js7KeS6d9pKkTFPRPbBwhFPPmZ1TZH//Z99ZlfRf0puhG2nMjqC8Aj\npYZlQ3yB3QR4fmEtLxIjdpY2/IsBNuR4WMI9P7scb/3S9L29X8bwzpVCBQy6WgdogzCZwX/KSInT\nqudwNMs34MHNXvRRBpzB4PVypZOD2LPg4A/JFwAe4PaD7f12CqAISeKEDLQJ8mgfGXEgYzOkRrI/\n3+YV8GNHuTH111rUwy5EO/xyhuMQCnKcUeTbg4hNXfYVdHTr/rsDNAhZg4RfYg2qBoBQblA+Hgoh\nkbvSH9IxR3JbuZGgoS9Dtsr3ichy2pHeO+wsbz1+EFBXE2+Nv1o27Ctl9YTjZy1FkA4F4DugCwI5\nJwmp4CSxlR5V9SDaFHV+Vu1TwBdQY3ttVnuAN6i7awhN1Ad1tIIaF8TH5pERQd5S0fYyxWgjLhn9\npHWVDFC2G+fhIL3BhQUohuHk4oCLQ6L5awnrPPLRqRn4zQDlebCN+fK9J0gdnvHyNyYQ/kaeXF9x\n4QhjVofyFnwwGIIh+pEx3UggaiMCTfm12/JPErbaC2cWkqNJaBKJ+kZUBwTutslEOVEue6ZPibBC\nlvVbw1M+zU3xyPx4SY/MzPQav6MEvRbaT7aTZcFf9la1TtyYvLgsQIB+uB1Jki8vLi6HOMcBThQv\nemw1tXDJlwv/TYh78mMNpllnTGG2prieiBG9cResrv5mEZRJS1RjRyTk9AGQ9GaqTIs0MAVikqco\neK2iSkNM0GWEjHtSluZrD/SzfyYXZsSzJKzD/RmeX2pJmqBaZ1KHgSOzUJC3O6GAQiLE2SDYrQfc\noA14lbLXgYldDUXJX5nrM6EhnNcaT5xBYelhPiqIG/qOsAt4HWOm3SdtK9P6COkCKAWUXhHTeukL\nmKEVwZsqRLRbu0SdhxgItkILQs0JHSpLRmuJfkmZgm53NthwkWNu2unlsZdzeNpVDXL9ilhT2iO1\nNH7HurARdw83ECxK3Who2IcWtdm9+cJ8LNR925XkNJKhHJhhQXGa4GesfJTlLwa0J3J1olAv7dJD\nIVeq5XnXOyW6gzhDzTpK2afgLW3Thq9EY8cM2oWk+vjabJ5i094lTotFRSv9B2lzbIuWBxF3JH0I\nudYhXIW6B9qFceaPBMQM793OUBQSBOi3WGu/Lm0k0FUyRzsTPr/9d1BRWD9b5YqxnWniN/mzDQmA\nYZpqnFuhZFS83FJ7EriLaOJXoisxsE2uVFxQZ7E3c0/WVyt9Pyk+Rq9vxE2c7PUmojV3Rewu3xgC\nHUxvS/q4yXuSWMwqLEbhRt8KyDGB2EcHrMGojI9A0ILuJiueXyd++NuiozOyn33QRNg79tDZH3mv\ni+8I7tqNxp3T0CfBA9QeH1tn6GHvkNBaiaZJ4ioqg2EiNpcbn5nNy33NT53S9uSlyB0Gzkqj9wf8\n0hR3wtkRcGA248PtuON0okzf7rE1mJDI5+hfpRgGyJjEbfJixeU7Lhk1PobdVkkGahSBtTqc2Ldk\noQMllEOGJTuXu46HY55ne9BLbK29u+3MMBz1KAZ58qKCo7sPv5eDsexOr/w3IGHx6Kdyme9VC4gI\nHpr/JGRH5gXt8I9AjgOObZ8YzWCs/KErnh5vKjYPgooq9PMFmD0MKcDUxefsPGCZbtJmcVefKM6h\nBlmVXH28KYc1/71keR1eZBOfhZN5H4IKnWJvnGSPEPWlNmkHDCmMBA/arDVDvUljsoTjFZDXP7T0\n+TjMu/o/7F+zMcZWiYKhgVKkKdWexgpiHXrV/jzlxFhT9fPcBL331pgw832rrR3zn2xBtdx3s/Ag\nK1Cob56W+pntouKPOSBv235PCfPB6A6/Ccw7rvfYZk8LHxle4Y1/PzsISmSD/LVo4cm/Exalc3bJ\n+jWv5iO6jmO2H94k1iA0Nv/3zHgy5iIpqr1Mv6JDpEAtk7Fh/Vh31tsj8vm7ypdcArVQLrZwKYjX\nULh2r6jJOaE8J4PZIgVVGLE9YOmo7BFmfeOhlhkettJhttRcLQdBg126cn1h07bgI2/R4A8FI5ux\nEaWY3u77/vSyaIdQhCF/P3CDABPg+NUyB2mOZkueZZLn5WcQXi/qsIaWa/tXDAGrSaNPF0BUpr0D\nNORQ2oB+sPYpR+iCKvBonHa0hnYsrGlwdwEsz3yguKJpXImkzHAzuYg4Liz6ePZcCW2ZhCSATfZC\nnsGKryGfcDacjk9bvdnNyM0GErMfMbCStu5PZ2r7tRBl+JAYLs0q4OUbr3pX0ne4yoJ31nWSCsl/\no6uk+txkgX3mufLWDGXeNyfaar2RWSKXXQNY1ypDhVTMGj8kPYvQq5HkaZ11Xme0QHgfuRwJqtqh\n8lzVdEQqR1iXV4T6JXENbyBJKTdtkWgcHSzL2s489b3ObCag7j8FPZT5bw+8FliIPY0yxkAr0cRR\ndaKSqx8MxxqntzyJSv66i46SMpCdBKRq0RxZxkv+pHlbESDlhJnZATCho6xuoLk3LI/X2BFR4VX0\numzxeRO/zPXvZWEFgvWb7vPucX5mlBx4j/13u9aZVNcv8qzODK5Tvgdgwc5TSSZq49U0v+9FJFNu\nvSxtSDPPL0b52168r8Kj8O5EgF745J7FdO8n+gu+ma79Qfo/v3LNezC1Q7phWk+RLwYWEB/fC44v\nDbkUkzn7niBiRc+gffcMBzcWNXXMg6ym6FHOMi+xkiVFXFvLIc39i1tT+PyocfD9Yf2DSG2WtUXb\nrExRkxKCe/O/375k4LLknHaBoJmB7m4FcgFZl6WZcgL7Ak78RhFXrmeGuxcuGW4b2njWh+RwOFuD\n1tPq/OWTREvGcq4/OCyOPhuOmLuJuFbKroZYZQKxLS9rTBBVudy8Lm6wygRT4cNoQgO0Ft6wE7Dk\nLVV5SkjkW1wCKNuC32+quUYlwToikg8OX9hqMxp8EAryEIAkhcYpC4+WBh682E/q+e3UzWLiutoy\nxserP8cf15U6aL4UT7nL/Nxmwhw6EzKtHC8JgJevouggntc2V+PvI6qi9bqstuyZu2ogmWkrB9O/\n0vwCkKjyNJMOY9w4Ltb+Jc3mm6sZ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{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_axis (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [0 : 0] probe1;\ninput [63 : 0] probe2;\ninput [31 : 0] probe3;\ninput [63 : 0] probe4;\ninput [0 : 0] probe5;\n\n\nendmodule\n", "num_lines": 73}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"ila_axis,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_axis,ila,{x_ipProduct=Vivado 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PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1,C_PROBE0_TYPE=0,C_PROBE1_TYPE=0,C_PROBE2_TYPE=0,C_PROBE3_TYPE=0,C_PROBE4_TYPE=0,C_PROBE5_TYPE=0,\\\nC_PROBE6_TYPE=1,C_PROBE7_TYPE=1,C_PROBE8_TYPE=1,C_PROBE9_TYPE=1,C_PROBE10_TYPE=1,C_PROBE11_TYPE=1,C_PROBE12_TYPE=1,C_PROBE13_TYPE=1,C_PROBE14_TYPE=1,C_PROBE15_TYPE=1,C_PROBE16_TYPE=1,C_PROBE17_TYPE=1,C_PROBE18_TYPE=1,C_PROBE19_TYPE=1,C_PROBE20_TYPE=1,C_PROBE21_TYPE=1,C_PROBE22_TYPE=1,C_PROBE23_TYPE=1,C_PROBE24_TYPE=1,C_PROBE25_TYPE=1,C_PROBE26_TYPE=1,C_PROBE27_TYPE=1,C_PROBE28_TYPE=1,C_PROBE29_TYPE=1,C_PROBE30_TYPE=1,C_PROBE31_TYPE=1,C_PROBE32_TYPE=1,C_PROBE33_TYPE=1,C_PROBE34_TYPE=1,C_PROBE35_TYPE=1,C_PROBE36_TYPE=1,C_PROBE37_TYPE=1,C_PROBE38_TYPE=1,C_PROBE39_TYPE=1,C_PROBE40_TYPE=1,C_PROBE41_TYPE=1,C_PROBE42_TYPE=1,C_PROBE43_TYPE=1,C_PROBE44_TYPE=1,C_PROBE45_TYPE=1,C_PROBE46_TYPE=1,C_PROBE47_TYPE=1,C_PROBE48_TYPE=1,C_PROBE49_TYPE=1,C_PROBE50_TYPE=1,C_PROBE51_TYPE=1,C_PROBE52_TYPE=1,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,\\\nC_PROBE106_TYPE=1,C_PROBE107_TYPE=1,C_PROBE108_TYPE=1,C_PROBE109_TYPE=1,C_PROBE110_TYPE=1,C_PROBE111_TYPE=1,C_PROBE112_TYPE=1,C_PROBE113_TYPE=1,C_PROBE114_TYPE=1,C_PROBE115_TYPE=1,C_PROBE116_TYPE=1,C_PROBE117_TYPE=1,C_PROBE118_TYPE=1,C_PROBE119_TYPE=1,C_PROBE120_TYPE=1,C_PROBE121_TYPE=1,C_PROBE122_TYPE=1,C_PROBE123_TYPE=1,C_PROBE124_TYPE=1,C_PROBE125_TYPE=1,C_PROBE126_TYPE=1,C_PROBE127_TYPE=1,C_PROBE128_TYPE=1,C_PROBE129_TYPE=1,C_PROBE130_TYPE=1,C_PROBE131_TYPE=1,C_PROBE132_TYPE=1,C_PROBE133_TYPE=1,C_PROBE134_TYPE=1,C_PROBE135_TYPE=1,C_PROBE136_TYPE=1,C_PROBE137_TYPE=1,C_PROBE138_TYPE=1,C_PROBE139_TYPE=1,C_PROBE140_TYPE=1,C_PROBE141_TYPE=1,C_PROBE142_TYPE=1,C_PROBE143_TYPE=1,C_PROBE144_TYPE=1,C_PROBE145_TYPE=1,C_PROBE146_TYPE=1,C_PROBE147_TYPE=1,C_PROBE148_TYPE=1,C_PROBE149_TYPE=1,C_PROBE150_TYPE=1,C_PROBE151_TYPE=1,C_PROBE152_TYPE=1,C_PROBE153_TYPE=1,C_PROBE154_TYPE=1,C_PROBE155_TYPE=1,C_PROBE156_TYPE=1,C_PROBE157_TYPE=1,C_PROBE158_TYPE=1,C_PROBE159_TYPE=1,C_PROBE160_TYPE=1,C_PROBE161_TYPE=1,C_PROBE162_TYPE=1,C_PROBE163_TYPE=1,C_PROBE164_TYPE=1,C_PROBE165_TYPE=1,C_PROBE166_TYPE=1,C_PROBE167_TYPE=1,C_PROBE168_TYPE=1,C_PROBE169_TYPE=1,C_PROBE170_TYPE=1,C_PROBE171_TYPE=1,C_PROBE172_TYPE=1,C_PROBE173_TYPE=1,C_PROBE174_TYPE=1,C_PROBE175_TYPE=1,C_PROBE176_TYPE=1,C_PROBE177_TYPE=1,C_PROBE178_TYPE=1,C_PROBE179_TYPE=1,C_PROBE180_TYPE=1,C_PROBE181_TYPE=1,C_PROBE182_TYPE=1,C_PROBE183_TYPE=1,C_PROBE184_TYPE=1,C_PROBE185_TYPE=1,C_PROBE186_TYPE=1,C_PROBE187_TYPE=1,C_PROBE188_TYPE=1,C_PROBE189_TYPE=1,C_PROBE190_TYPE=1,C_PROBE191_TYPE=1,C_PROBE192_TYPE=1,C_PROBE193_TYPE=1,C_PROBE194_TYPE=1,C_PROBE195_TYPE=1,C_PROBE196_TYPE=1,C_PROBE197_TYPE=1,C_PROBE198_TYPE=1,C_PROBE199_TYPE=1,C_PROBE200_TYPE=1,C_PROBE201_TYPE=1,C_PROBE202_TYPE=1,C_PROBE203_TYPE=1,C_PROBE204_TYPE=1,C_PROBE205_TYPE=1,\\\nC_PROBE206_TYPE=1,C_PROBE207_TYPE=1,C_PROBE208_TYPE=1,C_PROBE209_TYPE=1,C_PROBE210_TYPE=1,C_PROBE211_TYPE=1,C_PROBE212_TYPE=1,C_PROBE213_TYPE=1,C_PROBE214_TYPE=1,C_PROBE215_TYPE=1,C_PROBE216_TYPE=1,C_PROBE217_TYPE=1,C_PROBE218_TYPE=1,C_PROBE219_TYPE=1,C_PROBE220_TYPE=1,C_PROBE221_TYPE=1,C_PROBE222_TYPE=1,C_PROBE223_TYPE=1,C_PROBE224_TYPE=1,C_PROBE225_TYPE=1,C_PROBE226_TYPE=1,C_PROBE227_TYPE=1,C_PROBE228_TYPE=1,C_PROBE229_TYPE=1,C_PROBE230_TYPE=1,C_PROBE231_TYPE=1,C_PROBE232_TYPE=1,C_PROBE233_TYPE=1,C_PROBE234_TYPE=1,C_PROBE235_TYPE=1,C_PROBE236_TYPE=1,C_PROBE237_TYPE=1,C_PROBE238_TYPE=1,C_PROBE239_TYPE=1,C_PROBE240_TYPE=1,C_PROBE241_TYPE=1,C_PROBE242_TYPE=1,C_PROBE243_TYPE=1,C_PROBE244_TYPE=1,C_PROBE245_TYPE=1,C_PROBE246_TYPE=1,C_PROBE247_TYPE=1,C_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OBE525_TYPE=1,C_PROBE526_TYPE=1,C_PROBE527_TYPE=1,C_PROBE528_TYPE=1,C_PROBE529_TYPE=1,C_PROBE530_TYPE=1,C_PROBE531_TYPE=1,C_PROBE532_TYPE=1,C_PROBE533_TYPE=1,C_PROBE534_TYPE=1,C_PROBE535_TYPE=1,C_PROBE536_TYPE=1,C_PROBE537_TYPE=1,C_PROBE538_TYPE=1,C_PROBE539_TYPE=1,C_PROBE540_TYPE=1,C_PROBE541_TYPE=1,C_PROBE542_TYPE=1,C_PROBE543_TYPE=1,C_PROBE544_TYPE=1,C_PROBE545_TYPE=1,C_PROBE546_TYPE=1,C_PROBE547_TYPE=1,C_PROBE548_TYPE=1,C_PROBE549_TYPE=1,C_PROBE550_TYPE=1,C_PROBE551_TYPE=1,C_PROBE552_TYPE=1,C_PROBE553_TYPE=1,C_PROBE554_TYPE=1,C_PROBE555_TYPE=1,C_PROBE556_TYPE=1,C_PROBE557_TYPE=1,C_PROBE558_TYPE=1,C_PROBE559_TYPE=1,C_PROBE560_TYPE=1,C_PROBE561_TYPE=1,C_PROBE562_TYPE=1,C_PROBE563_TYPE=1,C_PROBE564_TYPE=1,C_PROBE565_TYPE=1,C_PROBE566_TYPE=1,C_PROBE567_TYPE=1,C_PROBE568_TYPE=1,C_PROBE569_TYPE=1,C_PROBE570_TYPE=1,C_PROBE571_TYPE=1,C_PROBE572_TYPE=1,C_PROBE573_TYPE=1,C_PROBE574_TYPE=1,C_PROBE575_TYPE=1,C_PROBE576_TYPE=1,C_PROBE577_TYPE=1,C_PROBE578_TYPE=1,C_PROBE579_TYPE=1,C_PROBE580_TYPE=1,C_PROBE581_TYPE=1,C_PROBE582_TYPE=1,C_PROBE583_TYPE=1,C_PROBE584_TYPE=1,C_PROBE585_TYPE=1,C_PROBE586_TYPE=1,C_PROBE587_TYPE=1,C_PROBE588_TYPE=1,C_PROBE589_TYPE=1,C_PROBE590_TYPE=1,C_PROBE591_TYPE=1,C_PROBE592_TYPE=1,C_PROBE593_TYPE=1,C_PROBE594_TYPE=1,C_PROBE595_TYPE=1,C_PROBE596_TYPE=1,C_PROBE597_TYPE=1,C_PROBE598_TYPE=1,C_PROBE599_TYPE=1,C_PROBE600_TYPE=1,C_PROBE601_TYPE=1,C_PROBE602_TYPE=1,C_PROBE603_TYPE=1,C_PROBE604_TYPE=1,C_PROBE605_TYPE=1,\\\nC_PROBE606_TYPE=1,C_PROBE607_TYPE=1,C_PROBE608_TYPE=1,C_PROBE609_TYPE=1,C_PROBE610_TYPE=1,C_PROBE611_TYPE=1,C_PROBE612_TYPE=1,C_PROBE613_TYPE=1,C_PROBE614_TYPE=1,C_PROBE615_TYPE=1,C_PROBE616_TYPE=1,C_PROBE617_TYPE=1,C_PROBE618_TYPE=1,C_PROBE619_TYPE=1,C_PROBE620_TYPE=1,C_PROBE621_TYPE=1,C_PROBE622_TYPE=1,C_PROBE623_TYPE=1,C_PROBE624_TYPE=1,C_PROBE625_TYPE=1,C_PROBE626_TYPE=1,C_PROBE627_TYPE=1,C_PROBE628_TYPE=1,C_PROBE629_TYPE=1,C_PROBE630_TYPE=1,C_PROBE631_TYPE=1,C_PROBE632_TYPE=1,C_PROBE633_TYPE=1,C_PROBE634_TYPE=1,C_PROBE635_TYPE=1,C_PROBE636_TYPE=1,C_PROBE637_TYPE=1,C_PROBE638_TYPE=1,C_PROBE639_TYPE=1,C_PROBE640_TYPE=1,C_PROBE641_TYPE=1,C_PROBE642_TYPE=1,C_PROBE643_TYPE=1,C_PROBE644_TYPE=1,C_PROBE645_TYPE=1,C_PROBE646_TYPE=1,C_PROBE647_TYPE=1,C_PROBE648_TYPE=1,C_PROBE649_TYPE=1,C_PROBE650_TYPE=1,C_PROBE651_TYPE=1,C_PROBE652_TYPE=1,C_PROBE653_TYPE=1,C_PROBE654_TYPE=1,C_PROBE655_TYPE=1,C_PROBE656_TYPE=1,C_PROBE657_TYPE=1,C_PROBE658_TYPE=1,C_PROBE659_TYPE=1,C_PROBE660_TYPE=1,C_PROBE661_TYPE=1,C_PROBE662_TYPE=1,C_PROBE663_TYPE=1,C_PROBE664_TYPE=1,C_PROBE665_TYPE=1,C_PROBE666_TYPE=1,C_PROBE667_TYPE=1,C_PROBE668_TYPE=1,C_PROBE669_TYPE=1,C_PROBE670_TYPE=1,C_PROBE671_TYPE=1,C_PROBE672_TYPE=1,C_PROBE673_TYPE=1,C_PROBE674_TYPE=1,C_PROBE675_TYPE=1,C_PROBE676_TYPE=1,C_PROBE677_TYPE=1,C_PROBE678_TYPE=1,C_PROBE679_TYPE=1,C_PROBE680_TYPE=1,C_PROBE681_TYPE=1,C_PROBE682_TYPE=1,C_PROBE683_TYPE=1,C_PROBE684_TYPE=1,C_PROBE685_TYPE=1,C_PROBE686_TYPE=1,C_PROBE687_TYPE=1,C_PROBE688_TYPE=1,C_PROBE689_TYPE=1,C_PROBE690_TYPE=1,C_PROBE691_TYPE=1,C_PROBE692_TYPE=1,C_PROBE693_TYPE=1,C_PROBE694_TYPE=1,C_PROBE695_TYPE=1,C_PROBE696_TYPE=1,C_PROBE697_TYPE=1,C_PROBE698_TYPE=1,C_PROBE699_TYPE=1,C_PROBE700_TYPE=1,C_PROBE701_TYPE=1,C_PROBE702_TYPE=1,C_PROBE703_TYPE=1,C_PROBE704_TYPE=1,C_PROBE705_TYPE=1,\\\nC_PROBE706_TYPE=1,C_PROBE707_TYPE=1,C_PROBE708_TYPE=1,C_PROBE709_TYPE=1,C_PROBE710_TYPE=1,C_PROBE711_TYPE=1,C_PROBE712_TYPE=1,C_PROBE713_TYPE=1,C_PROBE714_TYPE=1,C_PROBE715_TYPE=1,C_PROBE716_TYPE=1,C_PROBE717_TYPE=1,C_PROBE718_TYPE=1,C_PROBE719_TYPE=1,C_PROBE720_TYPE=1,C_PROBE721_TYPE=1,C_PROBE722_TYPE=1,C_PROBE723_TYPE=1,C_PROBE724_TYPE=1,C_PROBE725_TYPE=1,C_PROBE726_TYPE=1,C_PROBE727_TYPE=1,C_PROBE728_TYPE=1,C_PROBE729_TYPE=1,C_PROBE730_TYPE=1,C_PROBE731_TYPE=1,C_PROBE732_TYPE=1,C_PROBE733_TYPE=1,C_PROBE734_TYPE=1,C_PROBE735_TYPE=1,C_PROBE736_TYPE=1,C_PROBE737_TYPE=1,C_PROBE738_TYPE=1,C_PROBE739_TYPE=1,C_PROBE740_TYPE=1,C_PROBE741_TYPE=1,C_PROBE742_TYPE=1,C_PROBE743_TYPE=1,C_PROBE744_TYPE=1,C_PROBE745_TYPE=1,C_PROBE746_TYPE=1,C_PROBE747_TYPE=1,C_PROBE748_TYPE=1,C_PROBE749_TYPE=1,C_PROBE750_TYPE=1,C_PROBE751_TYPE=1,C_PROBE752_TYPE=1,C_PROBE753_TYPE=1,C_PROBE754_TYPE=1,C_PROBE755_TYPE=1,C_PROBE756_TYPE=1,C_PROBE757_TYPE=1,C_PROBE758_TYPE=1,C_PROBE759_TYPE=1,C_PROBE760_TYPE=1,C_PROBE761_TYPE=1,C_PROBE762_TYPE=1,C_PROBE763_TYPE=1,C_PROBE764_TYPE=1,C_PROBE765_TYPE=1,C_PROBE766_TYPE=1,C_PROBE767_TYPE=1,C_PROBE768_TYPE=1,C_PROBE769_TYPE=1,C_PROBE770_TYPE=1,C_PROBE771_TYPE=1,C_PROBE772_TYPE=1,C_PROBE773_TYPE=1,C_PROBE774_TYPE=1,C_PROBE775_TYPE=1,C_PROBE776_TYPE=1,C_PROBE777_TYPE=1,C_PROBE778_TYPE=1,C_PROBE779_TYPE=1,C_PROBE780_TYPE=1,C_PROBE781_TYPE=1,C_PROBE782_TYPE=1,C_PROBE783_TYPE=1,C_PROBE784_TYPE=1,C_PROBE785_TYPE=1,C_PROBE786_TYPE=1,C_PROBE787_TYPE=1,C_PROBE788_TYPE=1,C_PROBE789_TYPE=1,C_PROBE790_TYPE=1,C_PROBE791_TYPE=1,C_PROBE792_TYPE=1,C_PROBE793_TYPE=1,C_PROBE794_TYPE=1,C_PROBE795_TYPE=1,C_PROBE796_TYPE=1,C_PROBE797_TYPE=1,C_PROBE798_TYPE=1,C_PROBE799_TYPE=1,C_PROBE800_TYPE=1,C_PROBE801_TYPE=1,C_PROBE802_TYPE=1,C_PROBE803_TYPE=1,C_PROBE804_TYPE=1,C_PROBE805_TYPE=1,\\\nC_PROBE806_TYPE=1,C_PROBE807_TYPE=1,C_PROBE808_TYPE=1,C_PROBE809_TYPE=1,C_PROBE810_TYPE=1,C_PROBE811_TYPE=1,C_PROBE812_TYPE=1,C_PROBE813_TYPE=1,C_PROBE814_TYPE=1,C_PROBE815_TYPE=1,C_PROBE816_TYPE=1,C_PROBE817_TYPE=1,C_PROBE818_TYPE=1,C_PROBE819_TYPE=1,C_PROBE820_TYPE=1,C_PROBE821_TYPE=1,C_PROBE822_TYPE=1,C_PROBE823_TYPE=1,C_PROBE824_TYPE=1,C_PROBE825_TYPE=1,C_PROBE826_TYPE=1,C_PROBE827_TYPE=1,C_PROBE828_TYPE=1,C_PROBE829_TYPE=1,C_PROBE830_TYPE=1,C_PROBE831_TYPE=1,C_PROBE832_TYPE=1,C_PROBE833_TYPE=1,C_PROBE834_TYPE=1,C_PROBE835_TYPE=1,C_PROBE836_TYPE=1,C_PROBE837_TYPE=1,C_PROBE838_TYPE=1,C_PROBE839_TYPE=1,C_PROBE840_TYPE=1,C_PROBE841_TYPE=1,C_PROBE842_TYPE=1,C_PROBE843_TYPE=1,C_PROBE844_TYPE=1,C_PROBE845_TYPE=1,C_PROBE846_TYPE=1,C_PROBE847_TYPE=1,C_PROBE848_TYPE=1,C_PROBE849_TYPE=1,C_PROBE850_TYPE=1,C_PROBE851_TYPE=1,C_PROBE852_TYPE=1,C_PROBE853_TYPE=1,C_PROBE854_TYPE=1,C_PROBE855_TYPE=1,C_PROBE856_TYPE=1,C_PROBE857_TYPE=1,C_PROBE858_TYPE=1,C_PROBE859_TYPE=1,C_PROBE860_TYPE=1,C_PROBE861_TYPE=1,C_PROBE862_TYPE=1,C_PROBE863_TYPE=1,C_PROBE864_TYPE=1,C_PROBE865_TYPE=1,C_PROBE866_TYPE=1,C_PROBE867_TYPE=1,C_PROBE868_TYPE=1,C_PROBE869_TYPE=1,C_PROBE870_TYPE=1,C_PROBE871_TYPE=1,C_PROBE872_TYPE=1,C_PROBE873_TYPE=1,C_PROBE874_TYPE=1,C_PROBE875_TYPE=1,C_PROBE876_TYPE=1,C_PROBE877_TYPE=1,C_PROBE878_TYPE=1,C_PROBE879_TYPE=1,C_PROBE880_TYPE=1,C_PROBE881_TYPE=1,C_PROBE882_TYPE=1,C_PROBE883_TYPE=1,C_PROBE884_TYPE=1,C_PROBE885_TYPE=1,C_PROBE886_TYPE=1,C_PROBE887_TYPE=1,C_PROBE888_TYPE=1,C_PROBE889_TYPE=1,C_PROBE890_TYPE=1,C_PROBE891_TYPE=1,C_PROBE892_TYPE=1,C_PROBE893_TYPE=1,C_PROBE894_TYPE=1,C_PROBE895_TYPE=1,C_PROBE896_TYPE=1,C_PROBE897_TYPE=1,C_PROBE898_TYPE=1,C_PROBE899_TYPE=1,C_PROBE900_TYPE=1,C_PROBE901_TYPE=1,C_PROBE902_TYPE=1,C_PROBE903_TYPE=1,C_PROBE904_TYPE=1,C_PROBE905_TYPE=1,\\\nC_PROBE906_TYPE=1,C_PROBE907_TYPE=1,C_PROBE908_TYPE=1,C_PROBE909_TYPE=1,C_PROBE910_TYPE=1,C_PROBE911_TYPE=1,C_PROBE912_TYPE=1,C_PROBE913_TYPE=1,C_PROBE914_TYPE=1,C_PROBE915_TYPE=1,C_PROBE916_TYPE=1,C_PROBE917_TYPE=1,C_PROBE918_TYPE=1,C_PROBE919_TYPE=1,C_PROBE920_TYPE=1,C_PROBE921_TYPE=1,C_PROBE922_TYPE=1,C_PROBE923_TYPE=1,C_PROBE924_TYPE=1,C_PROBE925_TYPE=1,C_PROBE926_TYPE=1,C_PROBE927_TYPE=1,C_PROBE928_TYPE=1,C_PROBE929_TYPE=1,C_PROBE930_TYPE=1,C_PROBE931_TYPE=1,C_PROBE932_TYPE=1,C_PROBE933_TYPE=1,C_PROBE934_TYPE=1,C_PROBE935_TYPE=1,C_PROBE936_TYPE=1,C_PROBE937_TYPE=1,C_PROBE938_TYPE=1,C_PROBE939_TYPE=1,C_PROBE940_TYPE=1,C_PROBE941_TYPE=1,C_PROBE942_TYPE=1,C_PROBE943_TYPE=1,C_PROBE944_TYPE=1,C_PROBE945_TYPE=1,C_PROBE946_TYPE=1,C_PROBE947_TYPE=1,C_PROBE948_TYPE=1,C_PROBE949_TYPE=1,C_PROBE950_TYPE=1,C_PROBE951_TYPE=1,C_PROBE952_TYPE=1,C_PROBE953_TYPE=1,C_PROBE954_TYPE=1,C_PROBE955_TYPE=1,C_PROBE956_TYPE=1,C_PROBE957_TYPE=1,C_PROBE958_TYPE=1,C_PROBE959_TYPE=1,C_PROBE960_TYPE=1,C_PROBE961_TYPE=1,C_PROBE962_TYPE=1,C_PROBE963_TYPE=1,C_PROBE964_TYPE=1,C_PROBE965_TYPE=1,C_PROBE966_TYPE=1,C_PROBE967_TYPE=1,C_PROBE968_TYPE=1,C_PROBE969_TYPE=1,C_PROBE970_TYPE=1,C_PROBE971_TYPE=1,C_PROBE972_TYPE=1,C_PROBE973_TYPE=1,C_PROBE974_TYPE=1,C_PROBE975_TYPE=1,C_PROBE976_TYPE=1,C_PROBE977_TYPE=1,C_PROBE978_TYPE=1,C_PROBE979_TYPE=1,C_PROBE980_TYPE=1,C_PROBE981_TYPE=1,C_PROBE982_TYPE=1,C_PROBE983_TYPE=1,C_PROBE984_TYPE=1,C_PROBE985_TYPE=1,C_PROBE986_TYPE=1,C_PROBE987_TYPE=1,C_PROBE988_TYPE=1,C_PROBE989_TYPE=1,C_PROBE990_TYPE=1,C_PROBE991_TYPE=1,C_PROBE992_TYPE=1,C_PROBE993_TYPE=1,C_PROBE994_TYPE=1,C_PROBE995_TYPE=1,C_PROBE996_TYPE=1,C_PROBE997_TYPE=1,C_PROBE998_TYPE=1,C_PROBE999_TYPE=1,C_PROBE1000_TYPE=1,C_PROBE1001_TYPE=1,C_PROBE1002_TYPE=1,C_PROBE1003_TYPE=1,C_PROBE1004_TYPE=1,C_PROBE1005_TYPE=1,\\\nC_PROBE1006_TYPE=1,C_PROBE1007_TYPE=1,C_PROBE1008_TYPE=1,C_PROBE1009_TYPE=1,C_PROBE1010_TYPE=1,C_PROBE1011_TYPE=1,C_PROBE1012_TYPE=1,C_PROBE1013_TYPE=1,C_PROBE1014_TYPE=1,C_PROBE1015_TYPE=1,C_PROBE1016_TYPE=1,C_PROBE1017_TYPE=1,C_PROBE1018_TYPE=1,C_PROBE1019_TYPE=1,C_PROBE1020_TYPE=1,C_PROBE1021_TYPE=1,C_PROBE1022_TYPE=1,C_PROBE1023_TYPE=1}\" *)\n\nmodule ila_axis (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [0 : 0] probe1;\ninput [63 : 0] probe2;\ninput [31 : 0] probe3;\ninput [63 : 0] probe4;\ninput [0 : 0] probe5;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_5_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(6),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2017),\n.C_MINOR_VERSION(4),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(0),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(2),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH (32),\n.C_ILA_CLK_FREQ(2000000),\n.C_PROBE0_WIDTH(1),\n.C_PROBE1_WIDTH(1),\n.C_PROBE2_WIDTH(64),\n.C_PROBE3_WIDTH(32),\n.C_PROBE4_WIDTH(64),\n.C_PROBE5_WIDTH(1),\n.C_PROBE6_WIDTH(1),\n.C_PROBE7_WIDTH(1),\n.C_PROBE8_WIDTH(1),\n.C_PROBE9_WIDTH(1),\n.C_PROBE10_WIDTH(1),\n.C_PROBE11_WIDTH(1),\n.C_PROBE12_WIDTH(1),\n.C_PROBE13_WIDTH(1),\n.C_PROBE14_WIDTH(1),\n.C_PROBE15_WIDTH(1),\n.C_PROBE16_WIDTH(1),\n.C_PROBE17_WIDTH(1),\n.C_PROBE18_WIDTH(1),\n.C_PROBE19_WIDTH(1),\n.C_PROBE20_WIDTH(1),\n.C_PROBE21_WIDTH(1),\n.C_PROBE22_WIDTH(1),\n.C_PROBE23_WIDTH(1),\n.C_PROBE24_WIDTH(1),\n.C_PROBE25_WIDTH(1),\n.C_PROBE26_WIDTH(1),\n.C_PROBE27_WIDTH(1),\n.C_PROBE28_WIDTH(1),\n.C_PROBE29_WIDTH(1),\n.C_PROBE30_WIDTH(1),\n.C_PROBE31_WIDTH(1),\n.C_PROBE32_WIDTH(1),\n.C_PROBE33_WIDTH(1),\n.C_PROBE34_WIDTH(1),\n.C_PROBE35_WIDTH(1),\n.C_PROBE36_WIDTH(1),\n.C_PROBE37_WIDTH(1),\n.C_PROBE38_WIDTH(1),\n.C_PROBE39_WIDTH(1),\n.C_PROBE40_WIDTH(1),\n.C_PROBE41_WIDTH(1),\n.C_PROBE42_WIDTH(1),\n.C_PROBE43_WIDTH(1),\n.C_PROBE44_WIDTH(1),\n.C_PROBE45_WIDTH(1),\n.C_PROBE46_WIDTH(1),\n.C_PROBE47_WIDTH(1),\n.C_PROBE48_WIDTH(1),\n.C_PROBE49_WIDTH(1),\n.C_PROBE50_WIDTH(1),\n.C_PROBE51_WIDTH(1),\n.C_PROBE52_WIDTH(1),\n.C_PROBE53_WIDTH(1),\n.C_PROBE54_WIDTH(1),\n.C_PROBE55_WIDTH(1),\n.C_PROBE56_WIDTH(1),\n.C_PROBE57_WIDTH(1),\n.C_PROBE58_WIDTH(1),\n.C_PROBE59_WIDTH(1),\n.C_PROBE60_WIDTH(1),\n.C_PROBE61_WIDTH(1),\n.C_PROBE62_WIDTH(1),\n.C_PROBE63_WIDTH(1),\n.C_PROBE64_WIDTH(1),\n.C_PROBE65_WIDTH(1),\n.C_PROBE66_WIDTH(1),\n.C_PROBE67_WIDTH(1),\n.C_PROBE68_WIDTH(1),\n.C_PROBE69_WIDTH(1),\n.C_PROBE70_WIDTH(1),\n.C_PROBE71_WIDTH(1),\n.C_PROBE72_WIDTH(1),\n.C_PROBE73_WIDTH(1),\n.C_PROBE74_WIDTH(1),\n.C_PROBE75_WIDTH(1),\n.C_PROBE76_WIDTH(1),\n.C_PROBE77_WIDTH(1),\n.C_PROBE78_WIDTH(1),\n.C_PROBE79_WIDTH(1),\n.C_PROBE80_WIDTH(1),\n.C_PROBE81_WIDTH(1),\n.C_PROBE82_WIDTH(1),\n.C_PROBE83_WIDTH(1),\n.C_PROBE84_WIDTH(1),\n.C_PROBE85_WIDTH(1),\n.C_PROBE86_WIDTH(1),\n.C_PROBE87_WIDTH(1),\n.C_PROBE88_WIDTH(1),\n.C_PROBE89_WIDTH(1),\n.C_PROBE90_WIDTH(1),\n.C_PROBE91_WIDTH(1),\n.C_PROBE92_WIDTH(1),\n.C_PROBE93_WIDTH(1),\n.C_PROBE94_WIDTH(1),\n.C_PROBE95_WIDTH(1),\n.C_PROBE96_WIDTH(1),\n.C_PROBE97_WIDTH(1),\n.C_PROBE98_WIDTH(1),\n.C_PROBE99_WIDTH(1),\n.C_PROBE100_WIDTH(1),\n.C_PROBE101_WIDTH(1),\n.C_PROBE102_WIDTH(1),\n.C_PROBE103_WIDTH(1),\n.C_PROBE104_WIDTH(1),\n.C_PROBE105_WIDTH(1),\n.C_PROBE106_WIDTH(1),\n.C_PROBE107_WIDTH(1),\n.C_PROBE108_WIDTH(1),\n.C_PROBE109_WIDTH(1),\n.C_PROBE110_WIDTH(1),\n.C_PROBE111_WIDTH(1),\n.C_PROBE112_WIDTH(1),\n.C_PROBE113_WIDTH(1),\n.C_PROBE114_WIDTH(1),\n.C_PROBE115_WIDTH(1),\n.C_PROBE116_WIDTH(1),\n.C_PROBE117_WIDTH(1),\n.C_PROBE118_WIDTH(1),\n.C_PROBE119_WIDTH(1),\n.C_PROBE120_WIDTH(1),\n.C_PROBE121_WIDTH(1),\n.C_PROBE122_WIDTH(1),\n.C_PROBE123_WIDTH(1),\n.C_PROBE124_WIDTH(1),\n.C_PROBE125_WIDTH(1),\n.C_PROBE126_WIDTH(1),\n.C_PROBE127_WIDTH(1),\n.C_PROBE128_WIDTH(1),\n.C_PROBE129_WIDTH(1),\n.C_PROBE130_WIDTH(1),\n.C_PROBE131_WIDTH(1),\n.C_PROBE132_WIDTH(1),\n.C_PROBE133_WIDTH(1),\n.C_PROBE134_WIDTH(1),\n.C_PROBE135_WIDTH(1),\n.C_PROBE136_WIDTH(1),\n.C_PROBE137_WIDTH(1),\n.C_PROBE138_WIDTH(1),\n.C_PROBE139_WIDTH(1),\n.C_PROBE140_WIDTH(1),\n.C_PROBE141_WIDTH(1),\n.C_PROBE142_WIDTH(1),\n.C_PROBE143_WIDTH(1),\n.C_PROBE144_WIDTH(1),\n.C_PROBE145_WIDTH(1),\n.C_PROBE146_WIDTH(1),\n.C_PROBE147_WIDTH(1),\n.C_PROBE148_WIDTH(1),\n.C_PROBE149_WIDTH(1),\n.C_PROBE150_WIDTH(1),\n.C_PROBE151_WIDTH(1),\n.C_PROBE152_WIDTH(1),\n.C_PROBE153_WIDTH(1),\n.C_PROBE154_WIDTH(1),\n.C_PROBE155_WIDTH(1),\n.C_PROBE156_WIDTH(1),\n.C_PROBE157_WIDTH(1),\n.C_PROBE158_WIDTH(1),\n.C_PROBE159_WIDTH(1),\n.C_PROBE160_WIDTH(1),\n.C_PROBE161_WIDTH(1),\n.C_PROBE162_WIDTH(1),\n.C_PROBE163_WIDTH(1),\n.C_PROBE164_WIDTH(1),\n.C_PROBE165_WIDTH(1),\n.C_PROBE166_WIDTH(1),\n.C_PROBE167_WIDTH(1),\n.C_PROBE168_WIDTH(1),\n.C_PROBE169_WIDTH(1),\n.C_PROBE170_WIDTH(1),\n.C_PROBE171_WIDTH(1),\n.C_PROBE172_WIDTH(1),\n.C_PROBE173_WIDTH(1),\n.C_PROBE174_WIDTH(1),\n.C_PROBE175_WIDTH(1),\n.C_PROBE176_WIDTH(1),\n.C_PROBE177_WIDTH(1),\n.C_PROBE178_WIDTH(1),\n.C_PROBE179_WIDTH(1),\n.C_PROBE180_WIDTH(1),\n.C_PROBE181_WIDTH(1),\n.C_PROBE182_WIDTH(1),\n.C_PROBE183_WIDTH(1),\n.C_PROBE184_WIDTH(1),\n.C_PROBE185_WIDTH(1),\n.C_PROBE186_WIDTH(1),\n.C_PROBE187_WIDTH(1),\n.C_PROBE188_WIDTH(1),\n.C_PROBE189_WIDTH(1),\n.C_PROBE190_WIDTH(1),\n.C_PROBE191_WIDTH(1),\n.C_PROBE192_WIDTH(1),\n.C_PROBE193_WIDTH(1),\n.C_PROBE194_WIDTH(1),\n.C_PROBE195_WIDTH(1),\n.C_PROBE196_WIDTH(1),\n.C_PROBE197_WIDTH(1),\n.C_PROBE198_WIDTH(1),\n.C_PROBE199_WIDTH(1),\n.C_PROBE200_WIDTH(1),\n.C_PROBE201_WIDTH(1),\n.C_PROBE202_WIDTH(1),\n.C_PROBE203_WIDTH(1),\n.C_PROBE204_WIDTH(1),\n.C_PROBE205_WIDTH(1),\n.C_PROBE206_WIDTH(1),\n.C_PROBE207_WIDTH(1),\n.C_PROBE208_WIDTH(1),\n.C_PROBE209_WIDTH(1),\n.C_PROBE210_WIDTH(1),\n.C_PROBE211_WIDTH(1),\n.C_PROBE212_WIDTH(1),\n.C_PROBE213_WIDTH(1),\n.C_PROBE214_WIDTH(1),\n.C_PROBE215_WIDTH(1),\n.C_PROBE216_WIDTH(1),\n.C_PROBE217_WIDTH(1),\n.C_PROBE218_WIDTH(1),\n.C_PROBE219_WIDTH(1),\n.C_PROBE220_W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U_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT(1),\n.C_PROBE275_MU_CNT(1),\n.C_PROBE276_MU_CNT(1),\n.C_PROBE277_MU_CNT(1),\n.C_PROBE278_MU_CNT(1),\n.C_PROBE279_MU_CNT(1),\n.C_PROBE280_MU_CNT(1),\n.C_PROBE281_MU_CNT(1),\n.C_PROBE282_MU_CNT(1),\n.C_PROBE283_MU_CNT(1),\n.C_PROBE284_MU_CNT(1),\n.C_PROBE285_MU_CNT(1),\n.C_PROBE286_MU_CNT(1),\n.C_PROBE287_MU_CNT(1),\n.C_PROBE288_MU_CNT(1),\n.C_PROBE289_MU_CNT(1),\n.C_PROBE290_MU_CNT(1),\n.C_PROBE291_MU_CNT(1),\n.C_PROBE292_MU_CNT(1),\n.C_PROBE293_MU_CNT(1),\n.C_PROBE294_MU_CNT(1),\n.C_PROBE295_MU_CNT(1),\n.C_PROBE296_MU_CNT(1),\n.C_PROBE297_MU_CNT(1),\n.C_PROBE298_MU_CNT(1),\n.C_PROBE299_MU_CNT(1),\n.C_PROBE300_MU_CNT(1),\n.C_PROBE301_MU_CNT(1),\n.C_PROBE302_MU_CNT(1),\n.C_PROBE303_MU_CNT(1),\n.C_PROBE304_MU_CNT(1),\n.C_PROBE305_MU_CNT(1),\n.C_PROBE306_MU_CNT(1),\n.C_PROBE307_MU_CNT(1),\n.C_PROBE308_MU_CNT(1),\n.C_PROBE309_MU_CNT(1),\n.C_PROBE310_MU_CNT(1),\n.C_PROBE311_MU_CNT(1),\n.C_PROBE312_MU_CNT(1),\n.C_PROBE313_MU_CNT(1),\n.C_PROBE314_MU_CNT(1),\n.C_PROBE315_MU_CNT(1),\n.C_PROBE316_MU_CNT(1),\n.C_PROBE317_MU_CNT(1),\n.C_PROBE318_MU_CNT(1),\n.C_PROBE319_MU_CNT(1),\n.C_PROBE320_MU_CNT(1),\n.C_PROBE321_MU_CNT(1),\n.C_PROBE322_MU_CNT(1),\n.C_PROBE323_MU_CNT(1),\n.C_PROBE324_MU_CNT(1),\n.C_PROBE325_MU_CNT(1),\n.C_PROBE326_MU_CNT(1),\n.C_PROBE327_MU_CNT(1),\n.C_PROBE328_MU_CNT(1),\n.C_PROBE329_MU_CNT(1),\n.C_PROBE330_MU_CNT(1),\n.C_PROBE331_MU_CNT(1),\n.C_PROBE332_MU_CNT(1),\n.C_PROBE333_MU_CNT(1),\n.C_PROBE334_MU_CNT(1),\n.C_PROBE335_MU_CNT(1),\n.C_PROBE336_MU_CNT(1),\n.C_PROBE337_MU_CNT(1),\n.C_PROBE338_MU_CNT(1),\n.C_PROBE339_MU_CNT(1),\n.C_PROBE340_MU_CNT(1),\n.C_PROBE341_MU_CNT(1),\n.C_PROBE342_MU_CNT(1),\n.C_PROBE343_MU_CNT(1),\n.C_PROBE344_MU_CNT(1),\n.C_PROBE345_MU_CNT(1),\n.C_PROBE346_MU_CNT(1),\n.C_PROBE347_MU_CNT(1),\n.C_PROBE348_MU_CNT(1),\n.C_PROBE349_MU_CNT(1),\n.C_PROBE350_MU_CNT(1),\n.C_PROBE351_MU_CNT(1),\n.C_PROBE352_MU_CNT(1),\n.C_PROBE353_MU_CNT(1),\n.C_PROBE354_MU_CNT(1),\n.C_PROBE355_MU_CNT(1),\n.C_PROBE356_MU_CNT(1),\n.C_PROBE357_MU_CNT(1),\n.C_PROBE358_MU_CNT(1),\n.C_PROBE359_MU_CNT(1),\n.C_PROBE360_MU_CNT(1),\n.C_PROBE361_MU_CNT(1),\n.C_PROBE362_MU_CNT(1),\n.C_PROBE363_MU_CNT(1),\n.C_PROBE364_MU_CNT(1),\n.C_PROBE365_MU_CNT(1),\n.C_PROBE366_MU_CNT(1),\n.C_PROBE367_MU_CNT(1),\n.C_PROBE368_MU_CNT(1),\n.C_PROBE369_MU_CNT(1),\n.C_PROBE370_MU_CNT(1),\n.C_PROBE371_MU_CNT(1),\n.C_PROBE372_MU_CNT(1),\n.C_PROBE373_MU_CNT(1),\n.C_PROBE374_MU_CNT(1),\n.C_PROBE375_MU_CNT(1),\n.C_PROBE376_MU_CNT(1),\n.C_PROBE377_MU_CNT(1),\n.C_PROBE378_MU_CNT(1),\n.C_PROBE379_MU_CNT(1),\n.C_PROBE380_MU_CNT(1),\n.C_PROBE381_MU_CNT(1),\n.C_PROBE382_MU_CNT(1),\n.C_PROBE383_MU_CNT(1),\n.C_PROBE384_MU_CNT(1),\n.C_PROBE385_MU_CNT(1),\n.C_PROBE386_MU_CNT(1),\n.C_PROBE387_MU_CNT(1),\n.C_PROBE388_MU_CNT(1),\n.C_PROBE389_MU_CNT(1),\n.C_PROBE390_MU_CNT(1),\n.C_PROBE391_MU_CNT(1),\n.C_PROBE392_MU_CNT(1),\n.C_PROBE393_MU_CNT(1),\n.C_PROBE394_MU_CNT(1),\n.C_PROBE395_MU_CNT(1),\n.C_PROBE396_MU_CNT(1),\n.C_PROBE397_MU_CNT(1),\n.C_PROBE398_MU_CNT(1),\n.C_PROBE399_MU_CNT(1),\n.C_PROBE400_MU_CNT(1),\n.C_PROBE401_MU_CNT(1),\n.C_PROBE402_MU_CNT(1),\n.C_PROBE403_MU_CNT(1),\n.C_PROBE404_MU_CNT(1),\n.C_PROBE405_MU_CNT(1),\n.C_PROBE406_MU_CNT(1),\n.C_PROBE407_MU_CNT(1),\n.C_PROBE408_MU_CNT(1),\n.C_PROBE409_MU_CNT(1),\n.C_PROBE410_MU_CNT(1),\n.C_PROBE411_MU_CNT(1),\n.C_PROBE412_MU_CNT(1),\n.C_PROBE413_MU_CNT(1),\n.C_PROBE414_MU_CNT(1),\n.C_PROBE415_MU_CNT(1),\n.C_PROBE416_MU_CNT(1),\n.C_PROBE417_MU_CNT(1),\n.C_PROBE418_MU_CNT(1),\n.C_PROBE419_MU_CNT(1),\n.C_PROBE420_MU_CNT(1),\n.C_PROBE421_MU_CNT(1),\n.C_PROBE422_MU_CNT(1),\n.C_PROBE423_MU_CNT(1),\n.C_PROBE424_MU_CNT(1),\n.C_PROBE425_MU_CNT(1),\n.C_PROBE426_MU_CNT(1),\n.C_PROBE427_MU_CNT(1),\n.C_PROBE428_MU_CNT(1),\n.C_PROBE429_MU_CNT(1),\n.C_PROBE430_MU_CNT(1),\n.C_PROBE431_MU_CNT(1),\n.C_PROBE432_MU_CNT(1),\n.C_PROBE433_MU_CNT(1),\n.C_PROBE434_MU_CNT(1),\n.C_PROBE435_MU_CNT(1),\n.C_PROBE436_MU_CNT(1),\n.C_PROBE437_MU_CNT(1),\n.C_PROBE438_MU_CNT(1),\n.C_PROBE439_MU_CNT(1),\n.C_PROBE440_MU_CNT(1),\n.C_PROBE441_MU_CNT(1),\n.C_PROBE442_MU_CNT(1),\n.C_PROBE443_MU_CNT(1),\n.C_PROBE444_MU_CNT(1),\n.C_PROBE445_MU_CNT(1),\n.C_PROBE446_MU_CNT(1),\n.C_PROBE447_MU_CNT(1),\n.C_PROBE448_MU_CNT(1),\n.C_PROBE449_MU_CNT(1),\n.C_PROBE450_MU_CNT(1),\n.C_PROBE451_MU_CNT(1),\n.C_PROBE452_MU_CNT(1),\n.C_PROBE453_MU_CNT(1),\n.C_PROBE454_MU_CNT(1),\n.C_PROBE455_MU_CNT(1),\n.C_PROBE456_MU_CNT(1),\n.C_PROBE457_MU_CNT(1),\n.C_PROBE458_MU_CNT(1),\n.C_PROBE459_MU_CNT(1),\n.C_PROBE460_MU_CNT(1),\n.C_PROBE461_MU_CNT(1),\n.C_PROBE462_MU_CNT(1),\n.C_PROBE463_MU_CNT(1),\n.C_PROBE464_MU_CNT(1),\n.C_PROBE465_MU_CNT(1),\n.C_PROBE466_MU_CNT(1),\n.C_PROBE467_MU_CNT(1),\n.C_PROBE468_MU_CNT(1),\n.C_PROBE469_MU_CNT(1),\n.C_PROBE470_MU_CNT(1),\n.C_PROBE471_MU_CNT(1),\n.C_PROBE472_MU_CNT(1),\n.C_PROBE473_MU_CNT(1),\n.C_PROBE474_MU_CNT(1),\n.C_PROBE475_MU_CNT(1),\n.C_PROBE476_MU_CNT(1),\n.C_PROBE477_MU_CNT(1),\n.C_PROBE478_MU_CNT(1),\n.C_PROBE479_MU_CNT(1),\n.C_PROBE480_MU_CNT(1),\n.C_PROBE481_MU_CNT(1),\n.C_PROBE482_MU_CNT(1),\n.C_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1),\n.C_PROBE691_MU_CNT(1),\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synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4251}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nbGT7tfmyts6/yZChogAFs2kP2mbFmmuiFroOv0r8QQv1hFG6JERBCXNBXfGou+8mLPigR5LV4eDx\nWE5VTd+gHQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nCWoEkLQgvsHNvKsNgOsMIlwqULIpu7GrNWea7T7cH++wHThbYiHobD6dcKucCQM5dNGL646pzspi\ngvc21hWZnPx+X5N28b2dNoegtcTB2kLdLw7Lks54cB9DeoTavLfTRXQYufpEksbrNJTUFVb2cNyN\n6BMeJUXHbb0vXcc5VT4=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nFNNqjXbqqfIGkUevtN9QbqDJwQreUsmu9xji2a/w3CJH665OoQqvJUOiq4+1ZDezrG2FheefDlOu\nudQOQzfUbqq4ZB7QVsrZ5+hnOl4+bTdi/FvverAngGvvJSU8+8gbzJ8jtcieV+kp8HrIMv5M1gu6\nVP5SY5P9OIiRMPqToUbAWBrFRpgduuTuMhaHwW7FZmVUVb1j1U3rE2T6UyEel2fueSISKzjAYa8d\nbMNfbkA2ORUFxDxV3b+bBcjCg+jYWECoAY59uutuI1TCRGdhy4DLAvrLFqaLXnKzQ/zhmv78sBnu\n10yEbUQnFKzl5lQwpKtElSrzEVryLPjEKxtU0Q==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nBtsuQ3rIBJ3UI+4s+peHFvk2pezsWjwgWqpQQAOktytWfnh45F6oITlHSewxA1WtBlnC7B06RlL1\nsh5uBcV81aLk24XWmuA7DcJrmhXRSOvl0k4gIwFckG2lpuYtWsH8y7owyOiD/FZUz/LSfTa3Mywh\nD7uNSNvKmmqFP0yIDB9zQtZJYDKPgeAlZS9NUZdzjF/a61kdekWKbPaCmwFQ0mA01X8N8Euy78Cm\ntwhuK1u9d5vu3NtNKQQjzffGoOig7AOKPE+KjZrhCajjfXLjFewajxJNXuRqE4Qr4GGCy18JUK+r\n9AD7YQrF9CXYq3xjR5zoOedNXXQz29GC/jViKA==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nGzBT1kWKJ35ymgjppXjhmBsPZAh+qqs629kt2BvXZjQHKHWH3WuilMysbQpFcvgaH9NxbR7qFPN6\nyb5XgBkpZDUCCrc6p6YR51wXM/nxNvw23FSNPFKjoFEw2V83YYFxlbr75lWeNCQl27cPfBPuxaSV\nIjlxIsm4eW9SkxEnTQqMX5ySy4IaL9yElffDeFxfvmZFrx9lJp5FMRFsWvs0CJEBnPV6KLu1CvY0\njoTQyovEbzWILZvpO6OoWWowRhHO/ukpDVkTQwizIuNbetdcKud8UyyAngECUSjve9k+rXX41zHR\nrDfFrjZc+RPg2YpdeYHykcsisoZ5sdzyCy4T5w==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\niim3M0ZIoSIeblUIY0hk1kn3BvlRMe2uVKS16OYK9H9BGNvnKistWqz2WEU4s7eijjhhkWdw6Rx0\n1TXQht76iCER16gWcazz66/Akg5MH+lOp9NPf3J2iEV7LK7f+3F9jgvrsadzyPoTuLecIoWFoNJk\nFXdJK8072alT4ln/U8w=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\npJ/yajVXTo6y0FFyEOL0HIGDXa+xEims4jF/m3KWWifm3tyRZ/Qmr6px8fbYo6wt98IysxEsBMsY\nOafake1VkQe9IEYdvl9w2pbHgnMGCgpFHt5GVkkx9kTM7g8X5yw1cj7dCjsuNtLtsSeZ7wW2gvp4\nba+UNyDRcpm3wErDehZlm6QU2gigOYOXUMH6KQLyei8VsyCUEOLrtDfoDMEgbTsPan0OVwWZ4Yma\nBViyJ567bWm+BUmLR7HMTK0+QktDEmFhL5lWaTS848MSM8+2esUyNGdKKutfcQWcpHUx0GkIOnS0\nlZ1qTioC56L1NI2aXWshT+ZrJgi5x4ZYDqF6IA==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64336)\n`pragma protect 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ikj4QY9qy76XYw6IDsQdBnIGtPSFwxd9wChRjkni7PaX9nBoTv4Hkv4/X71ms92d\ntJ/07jLvlYIC/ZQu83ENzkpZcQxr+WVAlk9voN1Lh8MJ41Cksb/e82lQv3tE0i33RVWsfpzzkmhl\n6+iCuWQ09/k8dS0FyYp1eOOSakJpDvCoKsuGEA54TK2SkuCKjd+GAxav426xXnGAV1GxKJw4LUC+\nBoIDk42kjGmgDrTucR4D8ebhRKZlfSndBkUN1MxM4jhRdlUOlo1unmkpDpwboVbaBL63n0cP4G6M\nMWgaQmfg3Yi3VurtkG15kqklP5W2hoXk4N43ho9pwxbkiD0fB7BonN/w9HJv4Zu26k8JguWWER+r\nF24R1GsE91Dl6f8PkWleIhz82kPHFEq5RrhTesz5mPkAh4LBNNYQcbTVLlK5Bz0FGVt33lgt9zoT\n1OXASFCArKzZWd2y0Q5uZ6j1/oVxBrIIV84Ebwg//J/PeKNV+7dWoxdxrSyxxRk9/vGvVL/UxkDL\nXNFXWyLhbVlxG08uYDNL1cw4o1C3ePlskKxvHjLKaClc/79HN04C/k9fm51CrfmvosEcGzKhDPBj\nHMwFxAT3Pw83gG0A4Em+qHW7Wk8Bzor/p/e6kDCX2WbCTGXt8ZMf/Cq6Dryzr2sDHKfteVQJ2fpF\nHC/D0b26BUXdwRPX01IK0w8qiZ5/xcJUdwszggylh3pIeyt8qnPlZ1xYYH05884oekPtILD0GlZx\ndRw6hgHq6NYCifq33HepQkocmMaiBik7yzszAuKAWn2x5Raf/FC2GSRLb3itncwKnJGL7yYaSZeJ\n8OUhkMmGPtZ8ImThhDZ/RWkOBq+OUYnTNhKc3FmrCT9LsMzW0ZyQ9o+VsZv9bTJ+USliatHl6PD/\nLRypXj3clKV1a/C8C+rxwRip4mEQfKcf0UiZgBr6eYubS93izNsyymJ1mp/BMX6jt+kcmR3LAEE0\ncpyyOM0mIgNkjmJmLmv3R6jg/bPvI2p1N7/cIyybB4G0BZtRYMXRngfz1Q6EMQeQVsUna9iAjvQy\nAG2r/xcgJFufo3kkRGq2V3bTmOg/azUFNjzL/9jw4R6mkP391rUCjjKNDXYCpxvDS4Ye2p86OKcN\nXM4s+2bmJRe5JMBVj+0ZHS7ii0Mabn0ehWpoyMokVNz6dMpxel4glyyMLn1uEeaGHRDWuRfCqrOB\nfTnvUVJz1HNeGj9q7pSndbVygb7ZUsG8h3ZCkcyQhLOw47qwv3lDHtO77/HoYY9Tr62YzSiUh3z0\n9j8wCnOkMiqstzZ3iSyRXlGTQ8cV0IIcZ4obZHfQfj7I+N4MXnxEm4Pf8DHrXxlE0RxiG3MLn8Qp\nv1AES70B0p6TKWBC7H1cOxVI/K1ykT6KjY377HDe//18VNIC6IlFJzNuCN1q/+iLfRWlGy+uFMco\nAuFhgOP9A77fsu7sTi6ay+PaHjwC+jIiDGXdUXLPAJHxpDQzZfnDDo14bCy2ZRz1RWNEkUkLH6tY\nuGcD3kggbTyfoEOTkCtHzmGI7kFz1z7J9DYLueA4OMGamCdMbQxvlcUkwx/Yam/jPH2MB8HtyspC\new/FctHMgwthFB+FzPoSwmv+vsUZD7p8hri9LeoCnXPfXS7B0PhDyaHknDkaPDhEol1WramhVo0u\nGKZ8x1eDO9ipKqbYemWHLiAhYr8UXDVwN94diYZ9VcYwIrwr1P2VsWG/9O+R3rFngUUFk8Z4Bvip\n3PBfNVwE/QWhb/BgkmHeTvSayZckM9vCuruECucSChqNjhhIvSGY8CStQKNM+eK89IlUPsvIBY6l\nRZyKERWn9mxbX4ormBumHi4IznKEziX9fRRAEGW0uSLFhi/c435Qai4kSdBAoqvRTsu+7pIC8yv6\nmZ3UTSFrP9ATOE0GChYyllkCW590wKjCJcVXcdotPCuG+4IkqGFXeEYFfkQRLFX5drsg6AMEKhFl\n8EQOwjKQBjK4HT2f4vT4b5aHjEJ05K9SP1v5aTcX90VaEP5hR0OJDY8zsD40NbAozDPvBHZFX0ED\nIRhn+i/XVUxf4KkXcZ7BGUHiQvjXmiD7rd4O0nP0t99gvs5eB1QqiK16/QSY+J8Hu63WZWcdZZAv\n1Bl0sb7QjEa1onPN6MvMm284XZNYPuENoTvl84tdVpwWTTy6KaFjMfpGvs3Zw5rbRYjDqMU6FeLb\n7tSZ/ahWSGlsvFIWoqELhastLHLkIeMZyt8jlYUTAGEOEEraoePUOpjacUg8HrSpHie81DOaay7P\nAAzT/Is2R6begRrTAGNPq50SNgzPNmJomzUDHxlbuHeJYqnJzbTNmu2mm/QNIY5g4T3/ZUKkVv9Q\nrDjVCP+lEG/cEUycZ1Z78nVFuQWmcsM+c+assi7pL+uhWZzCPQizzj2hiM7VoacDeeG1IZ5IwMq0\nXp2/giop0Ak1pp75BsLEDXdzpcD8l6Gf+GZorCsODJ9BfSE12ihwudD2D7osjC/C/bUYdsrC/chx\nlQYFtNBnmCnTwsSK1xoevId8Y2WMMdNPuOhUUHqEtFNHL4EK/KM3VZU+CxrDDhp/Z7aMvgsweO4e\nFmHhSnvDyIGqCB6yPNMXL+UsWckLz2OL1rLGupkCvcfX4pwo9bia0CTK1ZkU5mrPXtvJ8iLvH5ZD\nELwT4RUG2uPfT9F2VS7xhdsTOj5USFtL68jcB4lQ3LdUwqMunj+M/wFkRUsc5Wo1Rna/htuyd3aP\nmvR4afocTUND8sbqWF86oE0b7M84KSsFKWn254Yv45b/7AGVXhW/zTIDhey6hbDDHa3zUhsRJ+sd\n3a7q9Kv9D7ax7QymetYPp67OmrE0CctHogPx89wzVtGxxpSFh+PSbv3u7EfYVFE5UV70g5dbWi52\n3Fe0kbBYQmCR+aJTy4hgxK666akTNVD8jx6UNgpOeJ9oLxbdi9gaCeP4YvldmkPNuv6n5m2SSHCN\nysHNq38Ri4NO/g8LNN3ZqRaQeeW04n7wNj43g2u7Q+AhVjNDn+3cUoMWV0XEdGhAlsvLAziOS8Aj\nAqOcs8PgfNLRn+/63nhr3S1tpn0oiSKA/UymFDp4XkFAl/NSQdSlZdl9yZfocKZ14yfbXP4naSXw\nYXdD9IJooJYT4vc3XhlNgoWURjW+vzbrQ+9Q0aDVLGwmTPWJcogLZSm4kAy7IhXy2y/e6LLI81FT\nbGmZxodxElq3jHE3z0CJEqoS+gsdBtdqC9QTMQaetDKYZvI5/vmZh3QKAamIvXVJ8TAgO+OxHgFd\nFxrvt+kVuLs1msjlkgS8mm8zfI4owlc5u5lmeVXtyCNHPLKHYAzzMNPW5Ai1OR6HoLM6UG/N2T34\nIXbk1QrwXKk878mT9EznzAhb/4bv6hoFEDgRIvCyyYweHxvzpmEfLiP6QaYNWWpO7iR/eaJHWw/w\n790hhWcg44VxliUVIWvozPbEuqHwxbBcXeC5Ksuxlmk8QdBhjHjrT3c76PX/AgEVe+DRzjzKRv5h\nMl6B13x1nZfviHANI6UOudXTe3BSkKBQatOSiKX4yGd35hKnuRYnDSNt1mYXH7lATfmjJFJ1TT73\nWSe0PhhtU7SE6IFs9oBDUTj2gUo4sKYA4alF58i9FJIqvxNGJAiLHJ8E/+pWe+aWwISfrECu9G7z\nfL+1k6nrcGpAegDvvNaMk9nvrHO5U8w3cCleTCuOdPKfWUgRuMapzh4NZ3PMrh8SXD1InQrZuBr/\n9wwsVObR2mdCCdXa+rhcQ78GUFqAhDlb/gDGwNJXRHEtPEgwsgr/EIIqHKun5yMnH9RkzScVLm+J\nhQtsd+JNrs4PPnSzdYGRKsNeWR1uZedxdvvmQuK6V9mJ1/9Rmqx/+sHIBiu+E3k4orWWGYdd/T8M\nGKqyT1rmVf0d2BrSPHzAKYdcRuxuewmDHbGVC3lq/yp65QOvQQO7N1EnY1gqIuYuYDxWjYKeiuwP\nQFDZvr5e0iMckylJHxO2Zkx+I12SyzSel48QzIAVnQmCTJ+X5gndrUh6LnLPRXJ6+tqzD9dfe3fA\nlb+egkye9h3JlbY+3Pjc+50z73r88qa/PpdTLyGj43GkhQTcr/5gW5n0AHoRaXiFYkNscs0Nos39\naAH1XRkvy408nbWfa2Gi7jxH7uI3+F3JkxicVp4XMzt+l+R+Dx0jSIyNA8oHaGXR7iODXmIVoCZV\nsxZNGSarntyxgE8l3LcO9FCL/iMvzfprNsX4JFDepRadUjspZB3K37Rtlr8GmaLhjZU3JZATm0vv\nmoZDKTaGGimpaBiPWWIIg5udEW5MYhrK4QvK8iJiuFcjIg4IBX3XEXi6+aZluEko16/4dzOkmd+e\nlZ5Dld272oEIa31In6knS3GnJn+b1p4s5Hl54tgnvGpXSISYPWD9Lq75SgxS/jHTRboTU19NRWhU\nGZYbeD0sh+mVjL2njjkPKpQ+0YFlelzdofUpHWOTVgDIGUgPQvZBn42WfsNJ/RV5TtsMZLjKLxaK\nKCX8wuFnxtCLoOUXBkbbosQYxnMAy1U44OrJu+0HOBqsrwNh5zFGJ/zk9/5utr8aQg/2aGimsg6J\nv7HyvEFEat6XUm+SLNRb4egTjBiPMHtEUqQzXg5WFNHpof6b17s5owPbAJDewviuC6u0+/FBomnn\ncjdCfOBsKr5oKtdJ9G/cfWevYkjMPzom6RgYqWKsOT4oXSsridVr9YSMbqMjs6TQyI53UUFHfVrF\nl0ryDtX4aJ6oq3I0s1jkTBQK2SVIvmMqBBreOHIPCFKB9G1cVT3e874jfndchxKWHYKOtVIJFav+\nL8Uo1/AnORfpmZ3MT04TOIfAJNO2opY0B5YuzT3m9m+wiD5/zMo6PmrcJJ3WVBY227wPW7hMWNNn\noOjAzzCrYiiO0/jDCB8OvnLChzLzTJmbwJe4z3LzHUGQQrZK+y5Tu/hI2S0CbbCb5l/4CxcADGOZ\nuOemAiz3WmIs6bykPvKCJ3YUD3M4F2iFz0Jc9H30enm5yuyqcKJoLQU5EWDirhIaywUHXRLN0ibW\nopXtRRfHpNK3lMJsLOJLnG0zXZGCJqyTj3qaVPfuys0B3+EBk12yq5qHRl4wt4HdS7zjxXqETTCS\nDWmTnT4ql9Ls9BhQoHCyeboOSARvoJCyg5bUFY4+3V+0E88wVyH2mpmkwGMTO1U7hbxtNJeZNcQw\n4x29DNm1Stga6kl3x8cvgu6djzr1ZOQOVMvIglT/BJQsYwV5NRK8kEiN/JrcDmE4po5lmaqOrEEd\nHnLyIi24A9t/bIbw350lCnc78BGA1Sk896A7Q8M8RbN/bHcWZcBBVJXli29+Go0U1cZ6vjpF4ote\nR7juv/pOYnF6fJkTyMQwM+5vzXEOMm7HcWdYRkQ7D3BbHuSVrhMBF89SrP7kn+SQ7CMEvfEG9gkj\noehWcUlTOkAPgQk+upUfEQ1V0IXIo+XGVCHXw1HlEAli9rLRlvLn2t99tZVdA9gnXSWDnaG0xm8R\nLth+31whyvvqwX0YwczoV5ZcVxTocWZwY2x4rKKiN1sDJ5PCIH5NrEMgJS2of6yaSC59QyvehjBw\nrRNKaNn2j7ZVpchE7btRVq+TWFqRMEnDj6B0wiKHy9A95fPH/jFUEg44Wgx2iIrKPooK1JfFJjbe\nTFsVM//5ug78qIzr214qkcwpUd+Zda7rHkJwxj4C8LcySIdWlAhhrFv5gtSCqrEIxbb4dyTvJ3v2\n29J4OwnSmjFaRx+7TxM4bH5xZBPQ9Aa5XDTCjtMA25CHWN46dF58ljRBnuxj/sTwdaqBLwjLFC/s\nAkRKeGbyuEkgZDGkgQ2uyOxRytYfZgUOGXyYAlgT4iE1lexh5KlOeiAzDxJoIQpPoMWANujOCHAv\n0CCpwPRIDa+2RYtlmvxXnQ/d9rmV/+bvuLlyg/PZfyF4lTfQ+gT5J6linBQ87uSw91z63GevX3vQ\nqIXoRUlm7FQIt6H+l7ILegL0BuaK/5858vbFl7BmT0xi4xczqNU5s5sPC7Jc1JhCohsjVnHvfwY2\n8qzZE/wJGg/5VjtcQrrIsoKjKqxGlUmOmA+gdWpIsqYx8y3lBO3oGE6LdohlPe50Ww3ftoagW1cK\nDi3dli+FTZBsGvAg9jehYrd6aHzVfHf2Y9oH7wo5VVoihibkHkzqoQtIf5kh+5qyhZ+GPgQhBdpC\niJA246TRn9v15Fx0Zn4OzczQG20209azn2UqWQULiPUy0AxceMoKJoI5ebd/IcNXjzH7HNmZBafC\nqmkvrkIAJJ1FNjBf+O0QphrrXFi8bHblHGOPHvgNOuyzywWWqrV4b4ppE4J2k+8EHYdTLVKZZ4Al\nYZ6gJSjesf8kxIgFcpqWikpTVY2Lip3rXeArsRv4MfC5Cjm1TjSdZAhN82oUsfszt8WRD+zl2+Yf\n6uRI8rD7tjXtB5A6MGRMrj9OUEXOgZhE4jqyNnCg6ichcoBhMt6I2frqhye4WGXAEMLI6vSDYRj9\nSnUdSngCYww1VjOT6c5zDafPzD96R10ddX1dvw2srvEC+Ie2efp5Qbmo1aa5lIQ57nk9WBJJvgaG\nXIhje8wa2mkKm5xLGWe4Y/yHPEpOwlPKyb3PhHzx+zIGduSAlzJSD+OZsJct2O03JrLOTWClXpm6\nN7E/Nv8Eynggtxy9yi27yj8r3I9F2I6vcGjNVurnmPRazqa6xDRN5XmvoZIxhaoyc22aS/cA2JTZ\n+yitWSfoXkzAXu6UL610+zmV2mfaoN5ISO0E1Wx5BXyYs9W4io4v/Vs5fF853UcjI07FeyIHaH/8\n633CANkUvI/Ls+GIu3A6u55H4++25ow4UvCUUjPyjgbvM08a25F/61H6L+v+hRkxKtflljcz2yFa\nWzu18dTrzpB6moutKoGhVnBhkISm1U8JTlUhMSkcwDMRjb+QWWk12wexPsUG6Klj1tbVZRO/kCWY\nBowdwm2TW2y2buml37GpNk8DTcKnOZBrPm9KGKJ8AlE+UZvGwdmwZM4ppd/KPXrDRTSAvtgLzqiG\nVO0RfMkmDngv6DSQR63QVXfQ7X1tI1VJcSzIp2FnlO5umBtoXaQr1f6iQLjZs8mHKNN1fbisbV3L\nkiGCuSBWjdyaz7i3nnyYk48bT0DCaLmk04mdPsi84JnyqcWa5HEqD8v1EtfmKP7KCxyqvL6jrGdr\nY2QrX1loreGJp1YQyZJ88Lde9IZlrVYG7X36FxaYuiTpVwyV0lodctAqii6guogpO85KUTYtLiD8\nz6r1LkdsS5eJtVm1N0V8qPJE3B7E5O9Eg3rSsAZegNJwfXmz0h/KOL7ee+E9kESRKPAwzZ1eXpjo\n4C2PK+Lp+RhF9n5kn9ahWn98OsYboOQ/+Vlg4ObgQeIu6hzKJ9jgtuWxYVY5shh7Jrt0uV7Ozv2e\nvnAZTy1CG+AMaHYhJVCrk60hH2jHdkHlRGewtI/rVzCQphSTu76+MqrhzPFiuWNwGvg6Wkz76LLd\nhfcCd+meSIE5pccdbl+mARINHJz0MJdp+AN9v2UrsfZHTUOOa197dKapTQboB938J0Vm4c9r5xEC\n0WRR7MoCZSLvTdcX9g91U68eqZ7aZgO5/oJqod9jh9AZDcjOZ/IZEEUBdlJN2ygo7ddcNiCIpE1/\niePuIMRKEXOabn+Jezy3oVmDxGLZMWCmCtA7SlmqKl+bDtba+c1jfk3rwir0Gc24AQTl/8/AiX3U\nhJTblGzrePrFEtjyEPyRKLCey9jkUXrRCnIJSxb3niKARYGPop2ovE37z/rUVgTWkWj8jruVtmUk\nXDa5ugQIukRCNmF4DRWY2R6KcBoaHm5VD7WsYZHIJKP4fX6X0xUFhGYGx2gj4VlXKa6ceqCBpmlR\nY2Yh5U96Y7N8lnKjQo/1tCXe7lQclT/F0y6KMMUbMdHp4fPwWIyBj8PyvP2F488jZKoaYDcCBAZ2\nFzAB5SJ9UtxvTWJ2r7LOFU29HmpRsScH+gg5k8G/675wfProbnZ3vGj83QtH1cvEl+BkwvWj05Kz\nu4d/mYBk6otvnaXixVDPAz/V9t+eNvXRwVNJ3mcfQ+DzZ8EIJ/yws4jWIkiSofX9OxpLH3L1BbA7\n7UR79P+vuAW2XLA4/voxPvt0BPlz+7oPINnLbEnB3HVWY4zM+EgWeBPAvZEkq36WAZhUBBNguE7a\n8RtT7QkNQq5ZyDg8G6KuJnpx0w+cCkCHtGWTV8maNSJha8Bnt78kTWeN+iarpU9NOyzxGbh3tniz\nfdzfLr9gC2z7ZDK1D3NObjjHSgBGOoPQ8zbZNjIRvY+3m6FqvjcGFJw4v3EallVzfNEk0eJgbrt5\n0rMp2kwHVSf/vfKqjcIHeIC8D8JG6DdmSQr9owY9/HqnlzR5liMglbcTS6FXDgmcLu+iYYFY28gi\nqFNSo1na61Urj23WxbaWilZLtC1U0TU7gS7GCuctgPqLDKFO1gglsegQThvzcuC5bwEwRlU3q91F\nd2p+3+bdCCne65OxvO0ehShiW6Lg+NgoKVG7qfTwiYnE81HF0ok/tcaZNbE709lTsFWC5fIF/MER\nVg2+dV7U6+rJIRf2tW/Pwavee5fm7VAUPC12UC6dZaK3h+YowDeF08FW2raiLFxqZjDBI7TWFZ0H\nlgE0OCIY3aNCGDGD5lhpZXuu5IHqEIrSKrM1p0vl+PZUNwzxcr54yP9/GvEGNovVn3YSTQaYB3yU\nMdTUt4B5/l/48spJ9IQRZJOHNqo4sGuVsLADOy/rNUTcWrlHcKgT0DiALq9k8rvybuyPaMmTKkvo\n6QP1WR0m668K4o1bSzt0rGulNFO1jk1Dp6cffsvGPPQdaLN/J3MNpUcjPMOpHBLyGTB5OqG/4mjU\nGR0byR0Cymms9sl3FH/LrcCbOEyY8FxsvPhszWsKD+co+nol2ncq/5AGd1Yj+E7pPniAvEi/hEuc\n4OVUmFlFYInGD4BlOQ4z7I+0hlGZFj1oOTrUsy1FU6g8j+6m1E2quppZMIkT8lgtWyT/mG+E3j+Y\nyTjtYgsbRn/oerrBrKpvvS3drB6tNlZMZrOZYn8xWzgC3RLspbE8JWwrsZom9BJG1f5mNF2P1cDY\n1foGVSlP8cZisVdTvgY03D/ummRYd74ziD9XcdWpWqYWeCk9MtNUuQRQnisPwsDyf6Iagbu8mRNh\nn4FglPLDfVH04Qx32QoA6E6bWyHKtStBKy4F067MkUQGvBIpLfKFxyXeG3zDRkQuj4joUnzGTPD6\nTFaSLk++kWojfrkMMF/LqnQZ4evnUMmoTH1Knr677TbVuDUTS2VQbRSGuo33/AnFJJ5IVlnIb7JR\nvdHAIG8g4zp0ZE/WmWTCIuOdEGmsDXsBGbtZJQbVHPez+8LOcItfUC96XH06NYNEZI/mH1wGdBNz\nUbnCsAnd/JUaDNe5hgGNc0aDcDfpgNVmPPTG5itNB1SjFzSZbsw+dqkjOYxUxdgxyqlcA2xAz5Rl\nnWuA56Icpx5LJgrYk7NaUiCvbiRjQ4JVAI3UQfibmloLegVPOu0WaahNR5z7gt93JISTsBZDOdJk\nkUX50GH3o+E5y2s5uQtEHNVzT0/VdOuuolIpCU5aoFcrFR5cuklmtaXcpJn6CFDQa1YzjoUaCnKe\nnpeJymF5dt8FbhIpA8PSuo0aBUq09MODdh/ZRaotvwLbYMDzWQIfKj0ndZV1nXBFjD4SQ+HoJ54U\nunuE4OZbTfvcC7ViY/RqV+Xkd/APQDwMfey+cXxqr7guko1eOqgR94FuW//L9CD1ZKsEvXpmRJdX\nBqYyUW6GK3akL3uIfIQCFtwyGi/BfEVu3rAbR3yirvflkC2o79Wa4BP+zh3tyGglK0Bvli6iar+A\nX1DA/dkwf4OqHuuG59dpNE4p/om4LMJXdl6SqXLhI4N5WxYtX2Px7ooR1NSZJl53yzBYZMOuzaF/\noaof3V2t8hYmlrfqUyBusIMDXGV41H5pi8vusj2z+i84D5mMz2c8T98Oa1CJKdCY5FXja1/TSWDt\nD2rNXOtcZgKzLQudXyS3jPb2TCMq3jOBycBDFH65nKAyGIFyeTKPn6cIAJDkBuSl+0bjUg8pILwC\nNmlAfw7DE+Eiq8aseLP9HhlVRm23B66+ryPSlSuUGIVmrtKKhWS5OKNDEqTMGEh4aw2sGNVVYvKS\nKbaGhWe60voQWV2IT9vuouA0hlv604k3/EwY0gODPnA/L93YelofcHaEhQEVx7iesFAVqq3KF2ue\nfKECodO8wfwW+RnycXayyuWlb2UnYwFI2AUUGCWpKShmVUarMlQKrWrIhTbO+g0vXa7E7zS+9fgJ\nWObDboS6oXv3rL6aUh8CdHvmYvR8QdSvfQvK+UvouZhsqTiycdhIO9oHLN5xkd4WWxloyOWerSvq\ng8/d8gOPzhBtKlPnJzkossrJkFwt5Y5+O5X12/+c6/n4WD4ZOddoCXy8i9kTQ3C5lp207Hh8bOmM\nea5HEgG4SoKB7kJtEIB1+5Ylct58MZUcUaHt8DP+uWNMSnY77vn+3RQm095pjevy0+URNb+7rW+4\nf1D/G4xH/mtDeKGQGekaf2e+KUEiKVb4PmHoTINrx6Pv9Vg01K5cEUcjJeCDoKZLy4NJ5cDzQSp0\ncPt7sgk2Up2jSOfivtrO0Yt9UzS2JK9RnBrxR+jG0sE8Zbi0U2UceMTAzYtt/pXz5RGbTXlxns9a\niforlRb+rHpcZmBqUbX9HMaGj3A8EC5aSERwk62OvM48On0A0lfW7ckac9U7bI2UeHUVkgbsLi2Q\n4mCjKZsKM/64VwaiUxvf9D7mLGgyX+4UWKpzdIXaxzIjlaWixYOcJEkwDwe+8BIlMru9C2uZ9+MR\noI4sbmHJOyvASFf3FlN2zZCEFPPuHoiN6H3y/IZd82q3xCaLNiMiNxMCRUgIHFwWdHt5r0lcTTdU\nh/TssUxGaa2KzM8lEo7CUkgMeoU8bWjB0DkaSXtusExrM1uNSd1l+eZsOMX7qzzJPEZeCatCFhK/\nBkWBpVm9vF4v3gNfhsVPSfkH1x/AbGjze0ZSaPJiPc4r7NcPoFZE1nIOIBABM3sJxT3mv3COVn+M\n1O/O7vXVwaMnugQOegqaROMi5zZn6fGJzhh8/8IIifmBei7ylRRqhJaE1IqGvLY8iw2CFgUbCsEJ\nQTppgPJNm59zRAa/4LWLZvs0u+wssdq6yRTOLomawCTb2+YSrSm4cBaef2FUqaY8z361WXyqdFpi\nCbmgzpCBcYWBcX1fLlSDN0FTptFOxlVLEmS1xO2GF472l8hQLEqEV7vfJvno+Z//8TjoVJ0mPAT+\nOodKgQ7+RnJBzAHC2bdAd6Wr5Cs1KYmxfeO1w8diEQk+7UEYEUfqDWOnhHM12DPdhcstSug+kJFe\nriF2f+ULJp0BKy2kJ/JJPAGRt53i1m2+71io+LzZha+RdggjfDKJr8EonB3mJTv6Ey/YxtD7/aPz\nsM+MIrZOFx4as9lBSVDYwTBZMvxLWLSdJsX/hZ8uFDZQxVyFQxfvrth/I158LUm56IUJcIyHeitQ\nJFFKCU2sw7McobUMR3H0dnKt749a5TFcp6Pt9OOnS0Kj2ZJ0zW0QRSFoUjeqWSlfVCVDBR7r2BpL\nG1tjy7Cqfqv1o53HItNjtOM4y2wZ53IpX5e+QjWiKzzYm5bi9Zw0sqCkhWYea/Ikvaaj5i7a+N2Q\nGUDekF0yxvDgpNKLYReqsEnViPjfOthZsiQ/ZF4f5FZkimf28UGqFSCYBhoyAoZCObcuokDZHSc7\nqbD8R5YbQFNmIhBTfo+LwHmZS9/r6GTAHKzt3NdOZJ+BlaPdFo9LoXpZFl7BISoGQNZp+cqJmxMX\nlElx0u0GPPHTNt6ilQWCwLZM9xFAQ5dH9aplVb1fFAdsjXUEJusNpQVa0ohBX/MlRqEA/ok7gkYU\nRg1Sl+gij7mTVCyaeKWlDR08H+GjsgnqBew6ptWyV+BLqxz1pIwS1TPPT9g2LEF/AXbgalw06Mhr\ngWyomNUgaddL15diQS7eKVlYwVtuO9Dio3USx5ootyq/tTQhrjkS124tYNG/4ozFsQy8kXW/28uQ\nVj60rTnm/QkMkD33zu8zBwXYOZ6+BhuSbsTph+WRnBagf9hxLJXfKYBbTirzgFHDPcrp6unySw1h\nXerYV26lMrK/9VrkVxxsC8LW/JGxQG0PHDl1cLs6YGseHZQa/ShX8XE7AtAYkJ56xfWkYduswh8s\n/xwWm/i19+VTuedahTPvXTRWxxvy7nbn2xV6LaUFixHNVy9k8lKLRdXzpNX1zCe2kB53fgz6XHnL\nxhN2WaHHuNFzUWCv8NghHah9YgCVwcCYh8YcQrqbuhpjVm/NprIxoZuqSuN1xRy/zfwU28FCMI0Z\nb3PwLG7AvfldFgTZPwBIWcODxzP894mHaNG9itsQjhW0ksSSxvYweLBofWtKhxFthCxXRjQYQlAo\n14uDlf24ruW2lki/ARokBEZ3c9WOn7xG+8a0XIAMh2Ze32MFWm50mba6Yk0jKXF7aZbfuH0MHbk7\n9U84WW80Rl7zWp7WK3mvHdR8kaFAyO/KFGsmPo3QwmBX3cmq0huPQVvvq9BjQq8b6DVoR0HRMFh6\nTS6HT6Gw205Po+wLRbrwzwbq6pUVKfHCySnZhHc2j3EXi1QjMy/UoGuW7bFHDALulwEzC7c4N1nP\n58hDhowIruHJ2UgjnpJYzV99YlPGs3RNfL2D5+uUFvkflxDXHnH14Ay7+zHIxr4HvncQGHOr5Fu9\nhSc76XDHb8pIGd8IdDD2aKLshPMrNF7ZVpt0IS/ThWkjpqI4HAwa99Oor5TJGkGnrK5nXCKl/V4U\neaSxXvHyD26Ry4NGBk2JasO8VqLSOVfuemwekAA795kOriGjdcU0hRZS0UK+YZIbt5M29s5xxQvn\nZgNF6Abotf57E+YP1F1eVCsopFPKfvATEpYTvUxBFxW4h/29TjMvkq9uvfS6ys+XhHfCrVIsAwv6\nr1aIxORiIZbULnlflxEryS///gUFpreGJpoPgLIzo848gKdf1bu+I5g+bikGAFcVIi27P74t0Q3D\n2+8X3z/i+DPkeMw0IwTCCxYpl/lnyV84ZlOjbvO+yak1dW85HmcOxI+Yx4X/aTWBxL1E1JUhsXny\na+5tcHCihqtH9TJ73Dz1Ctb0OQgLEcfPmziIrLrdgcEZv5fWYBjEp1PlCpqXnSKJik/ADIM2x1ZS\nwTuWTrBZXoTUnBmLXJvXwMOS3iK93JnKWLmogkAwQfj4NpYV9rRnNTEG8OtcRO6x+ScjxM3q2WcL\nNxMiwGOvrqy1PNsk5tqJrr+C/vX12LjRSBmKiu6xD3m84Sfo1ACMuimkJwSHDqd1FhpqLMWkEHd0\nTlg38sEgiPxPzQX8nNNDU+AP4ONfUTzkEdOKcKZiBzccH3Dh/3hMwpWY37LbN9EhqqQ6iS69/Nff\nI8jj0x7Ekmf6ZhNztfDvMTrHdMA+xBQdc4cL3BT8LiOLzDV8rROTTFwn8nHNro4jnAUqYf4sOABW\nwXiNohg3LLOwTe7gQpSThqCx5mSjmdOvwSEZXlSaciS6BJC8lgM5zJSzOURYOSMRl0CzfSVfiPjL\nl2lYdpYudLJqm32t+mntGbSc1wCqRy6djjjhFUadcHGBtn7ZMpcsGXeZ6PRYLYuWEiFrcxdeCBSJ\nMa6nR+aAfqAll8jQGr/c+1QtM1fgbtgUdnqpw2qWuRmW6LDkmuIxUHDJ+RS60L5zrYrgI27cYpEK\nUMcf/Dju2oqap/yP9KN2nvWiK6+OwAuvG22RDw7VIX/YU/KvVgED17M9VrSaGN8tqaHzNTGM2IDV\n7LGeSz1D15I00bC7lsM2GgX1s0o62Iwj6j/6deZ1ZiCwBtmmGzh0KCdzK/qSxCMHjC8qBAR9tQhk\n4mPouLUTQqh/4hTq4ku1SbVCqI3ZkjKytxnuhq5akCqQrq7Xx4JIaoeSH4sVIsXN3sfWGc7Zdh7T\ni+pQhzqsbkDGV/HO8zi1aJ0mPesChbkgZCI74tqxqtLgFFdUJepfQtEynJ7h7I8ZkfjccYsS3Ohl\nNdLTLxug/y1cWwWXQSU0L5+Z5ElHcoJH1LfwaUMungbZ1U5u/8Nry2jURK8LFHaLT/yRSn4Pg9fw\nuejDkeRSbGy1MMesbWXCO/uT8gOA9JYa99/xwuim3E5zGDUMaJWKg8WBZVyKEpY+KGjBFJOUrtMj\n3rcJNY9d4slEqcn2wDzuKUIcttvsC70XG0awDYSDQz2CYfHkWS5/uSF4ALpgjLcBzwC048jZUueV\nviWS5VudzFvxXLkz+NbWjjiE2B1O4wAGgrcimGJyiRUvU1wynIl9r0Qqr8iOCQSA/p+8qQ+0ZvY0\n8OWok9uq4V9RixaeLSckAEEGfom+KfvqiTv6AE9kw5848t2IU1HTaOCavLmA4A72Vd8XeLeqVW3U\nORuyyYkVjVxZLFIiWhx6jaF1/WT5jDluydog4xcvKVb1cwhxfvI67EmnSWsmK+xxBxA1Sdi7WWnc\ndkJLSWmQspe6eQDylbt/PkPSCYJz6mJ1PlmhwCT+ocHTX24eu0oRM0yobEJ+3BSUeR+k/u097WQl\nwq4+Q2wmmZFNmiX5L9MdI1REqstsyRBeZ8mabMRSV3ztx9WkA0kiru0Z+odw8re63Z1qNv39K66I\nTndTC3lMVLOU7jlDSzpqlgvEx8YKdGwtWR10ffvObGb67Bs39n3fup2O5Qi1hrrMjj0BIo4In58J\n8LGbRJzf7MFALj6nevF6KLhs0HBXaaZal5m62IjWRf2V4Mgj/ZGFih8cnTIM6QHcU/FgUQFPePxJ\nUFklzOMkiUFOiXbKDmaG7rsR9wcJTuZI4OH2Bra0GYY0KpgYcjeZ8INrWeiRUHCuEdkTH4UDhyp5\nkd8qBv1XPDMPgRjQcQXR6su+W3Da+OSeSSDEz7Jqx0ORWQwANUskxJVyC8b+ewdldz/8gCmU3jLn\n2vZKZvfj6KayKRHK7FxWrJokhNjnuKUgWI84ehgXQFuuDHRJfsvH02d5LM9+D71xfG+2+9DfEDEM\nzsiw5dAyaZX1pVpkXQoCukJgESE+6q1hKi1Kcz4k6hy82Eu/uov1cLMo7NeNKQrZHJ6lX//AvLfO\nTUpHyaByz2otzZmpVIAOL5/ycXUC0C07jfBxvL0sQKTQ/J6GtD+DUSWCHZNSFNqTz0Sf0KmVIyEQ\nt4myxo0muliPnbEu6LWT/DYOv7SzJafk1TWWvnEHUrkRmcqohZZisBgk0gIpe9nRRsFcWAwQ0rZJ\nr6DiRpm0z5qDe5QA9XauzWq8kyavTYLromTgMFc3Y0S0m9YSuzqOWbuo1Jb6MGD0y4CrD4Wos/V1\nnsoQwwLEOtso9goiwNi2drd9k2vm2wmYUewf6sazlvghzXheJRjDrXQIclJ+sQx8ho5y2EA8Ic6t\n0rw9KrHa/tlPwPMY8w39fnveTmcgywMtLX7eEIoqb4HpKpm8TqXczal7spNuWhPPe4J8DTU9T3Hv\nZFy6kHLsLwI97vN58c1TNYlnFDCCOmFUkoE97iNuWXejagNdoAKEE8wtPSGH8c8YhdCepyPwtsN0\n6j/dy7KxJmuxggcEYvS/1HBYgQ9IQTgGeHe+RJtjU0abY0fAFTcMKKVkS6VdimguNoiWsWPhDf0T\nSQwbwNsrU+9Wtk+St0Ib+B9D5sjQuAl60CS0arfZtMR1ZGkp2AlwqMlXL4vaFfD6+0cv26jC0RcC\neuQ631uzlivVyMyfaJW2a9/Pad+6aMWDv0fgd0t6wS3X7Vw+GHBo2jfevvFiiEvaY+OWL3LXWfDe\nWqMN0yntP5YqHFz1reseiRFn8klauOW63/7kJQB+WG7swSJKND/JGbeQfPCFMEOrNpHoGrVMfmIr\nViTWD9s/E+x2vSdqInLC12+lG30LYxhcaKGGtog0wRMOFziKHHGkxpgd6cIFalUPDVmH8D4Z0qYw\n0EmoZQBqSKVUt0ZAC6rvQUOtKdJHZHubC4++dutZAVZmAW5vZrIf5aPYUYMG7yyuExnDIBf6o+fO\nUKV4G48uKd6r+L0b/4kVosCyhh8DQ5xPibzLg1awGZHznPhqhCthPUNnuweG0I5j25iasRN4R/se\nvidCKbQjy5M1KyhWL2CFqpN+LIkJ4Bce4uGoB8fJ7Rex/UjHYfduoWEsh7Lz+GgUto4MVUyVg7mk\nsEZFgT0oLlmie4VzzARU+ngPfgaDftJgrNaW92UOpVa1AxvwLiIJCFPT5oNV9UpDfoEBZnmAcFc/\ns72pZNIMZ/6PBd7MnAAE3JJbkIUvr622GwGoBDkHTSTzCuTXdcAmpuGNS6qzrsglL8GIEnq1azaB\nfLcxBq20pyiPaf5WzT4O3YJFPde+jrl5bIi3nQ/xIkrPgyaixO+9g5ws+vTuYlTdwV+aw6Z2Eg4L\nwTCBB92MFE9JDAfYEFsazggJ4c+CFEGftfYuh6XosmP5Fk2EHNRIzIy1GE0uFYNCr0HrKxcDU8Gw\nvwNinbs1W26C6/mfEoCWGhtBEgXvy0fxpOqlczkT3MzWVB1H/3MDHhQhbdjaKdZKrhbyPefTM4mn\nRUwg4H9UKqMMxY8MpelKrUSjY5Rhn0E3IibFJGNmP1Km6DfK6Bz9izzj3SlBM2tuyc/pK8pJPybn\nVY7xZ3bAQA9TCSrYluNQ7Ku7eTeKTnQFanDf+MV6WzCmwj/zQon1Rytur+gV5eyhsYV7rt7bFu7h\nYnzt9cTUCyQWzC0jEWUqDg4dVnDKcpRaT4mZghot5rDxL+LgRbGj6bzvgkMabT8xpkNdlGjJN5n6\np9xZNBlZS/KMEkqIjAI1tdGO29hkLd7oqYF274ELPP5l1CvPBr1u0PgGilPa4LGW2TNx1mBux49h\ndqlUUJe1nIq28DPuRhe/YqGf4IUv+bihFqfjdOoPzEDxijtuPjf71rL2EOjqhbOBOoJS3H6yjqoz\nnAgVC1go6wodCenXIqAIQg78k/lP48fYaqhu4Yaec1dXXV8UyR4Zw2pdUFtBABUjWJbl/a6GZUg6\nFQ6HA06wwYXpfwivS5o95dfQvMcshAMquaE+Uk7t+zpPrFxLnTITOGafA4+vt7+zSiC+Nf0FCxTb\nMD3JDvplk0ljylaXpR0/mYid+K6EEN+gcyb/eY8i6/xTRvPt6GmdZNHeibD65PVZ1rWqBgXTyM3Q\nq3IIpyPJkJzY+dHBPQHcnUE0Yn1Ep7IXmnIy86737wq6h8ed84H8QzVuQtKAjWD0h6Pdq1/8VWKH\nQf6Srovz5Y/B/hEnFO80ED1zrw5kP5jGWIK3lzHgPvOuov0d34iKEWXeDA1xSD1h5lLNSBvtMG/n\nYgutmfLDuIKlg5CgxoWNuDOxK7CQNUvrtTlyRBS4cdzErCBugBmCyvATG+sl0iNPlgaSxHyTegVY\nCF1lMIotYzUCPWG9W2AIfo9xEq4BInp5seaDZlWAueRWsSVfIMuzGl1plry/Zzis6CVGs0QpntlQ\nmXpu0lGftlcasJEbC/EZNjUkOcZvVxNtpZdpyFKxmmejHkcvJmbKiZt61rr/Y0W3No1XLwbUfIhw\nXObmHdAFsLR98O7EhfpIs+e2Ii5vn8lYDmRa1gYK9IFj6Ikcd70mI9RSPhgpQgQn3CW0vX1DAdVv\nHYU9u6ThKMw6jlvFyHneAkBJ/NueXZenXLAhy/NmfEin02PEBq8MvZGes3LvIR6fSlYm2JGR7hcR\nscNtTbmuyI20CfzH3330djQ/hXf+61PlvpLlebaC6yhnnSQHSITI0pUzl9Ao2chkGfLIv4lkarzf\nVvGKA6bR4cLQ7lfMSb3jiAK/QFow/pQOHeoBGpiIJKnyfBfm5svJ35ns4KrF2u9yX68kHNn3GzD3\nHgV/iy4tNWUmkFYbPbbXyobnNbXNQtZOX3Rp8AOG9/Oo2SEnX0DhJ71qKmWpcbp/1BYCRfkXHiqC\neBMAYFNqIsb0UFGb4p3NWy607mqLirPXn3hFmV2MsgJ+JIeBuFIfOEt+uzSoD8KC8tMwqJybtYlH\ncmA7TusUFo2YYZJEMC4hhSPr9Vf3cxQ9FdrWuhoeFLtW3XVvlHvTawERVdqJGI33qy29xmhJ4nz+\n7/wP/l+gt5FG93Ni/8IEm6tB4obo5u0os7Xg7gmEy/6HCVFtfhNkqZyn4LTI6fi3wnIp7HIJWPkw\ndHPnAy7Za9wVoP70xhJbmtieW3CdDLEwW6k9qRmo91m35ph+NUrp6it8IEB3jqZbiqJOrGid/bGt\nDRe3ZwHQlGMqCSrGYYoQkn2elADRgSBi+SEBmIS969msvSUdcffrzFh1zgziOwKYJ7A+zgPAV5wQ\nmRIYCaCueGXcq3+Y3dqX6Xz+q2Urhdjug0VcDF4LTRCKJ/z4BoxHnhPJ0Kg3E/XNFOrxbodTy+V/\nf60jkELut0u9bDLnWv7CI3wgQxfZmbDzWDBBq+CqS6nFL3lJI202FIRh8gHqVyCn6QXFS84Aps6o\nsVsDBM31a9sYV/0IJ2eoJXSJWJpMa7JuEJj1QpCWgKPuFUqL00RmWetqTT4XnPXnNJc2l60XGhY+\nAsHEmLA/EUP7dssvL1l19DmPl1664WI9yN8JwrKMKIQIyQpp1lqKvA/uD8KUtUSf230Tt66HgLB1\n4j+idT++O+33nL1aQTVSDABPdZnV8MsvJ5W0oJhM5T5tvoPxWS/TY8Ok/AcSZOzeVYeGdZxwfQ2Z\nG1fYvu+0B592E4wGHMgZbomABjWALpDg+oDRscuswztBlv34wRiBfRhVq0+xjopYKqaMfRrv7Add\ncCpEx8xtg5/R5o61oOJlc15EqnvaFBqF6W1GW9eHl6mEvxDHkpVbvS0Z/XxySSsBQ8B4OtJjUiJ/\nLgEnTM87J2olOEnHHN/z2It2S/AEBFqRaqCJTXLb/vXe6gKekLNSu4qO/5RJpTms5R0vX/nwTvkl\nEoKqq2fRO4WVPGePAka7NO6i6uTxfoUXzyuckHg1WMvjj2uoW0aucppzCJ18nGBtTTqK9/hidxWo\nZypCiHytpCfX3S+v3W8xlss9vPeb8XoUbPytxfgNsJhLql8YMcldO5pFm0jVazvHJe9caPj65/6a\nmQNi5o5KGRI1YrgN37NHqaYSj3ig9w5K5r1vTpTim68ZUVHS2B70gveIPxtcfJj6MDjza9KDgar4\nL2j+0oCV7N5QCh+3eXAbatOp9GsqEK8NyPLDCMsTtR2UVyQpbKmXt/mmPW4E10r+zzMfJ6dDL2lA\nedhHtsi8mbms9bRX/Cb/S9SduVk3vefqeBSsK/lCxd1Gm+QXnMErrXxnR5MXNN9L8b0mosSL+4s+\nEiiRkZ28NL39wlIq1dpcgq2SObgCPTEHfwEkBROFvzkMC37TQSu9S55uWIs1FuyuXNLdBELb2ESV\ndDD+vw0deBrYhbroR94kQgadZshZY9xcmMpkOPQD4KJj1Pn9KyDfiFj1taahXAewxkfUfjsZLNGY\nj4Ufii6NpDrTkb9+WFudZyVk8IJKiDgggd08rG9vKD9IY3z+RAejotDLYRUnJHNKM5vFuzrQceYI\nE6Tu0LILRbrMcJ9tmkKRGd7VR6llDLUWRXGQFI71zJIuhxIVnSw6K2TdqCyvxxXuhHR6BrdlFIW4\n9RvXFMvEbB2Efao/7VnpBqBp5x2b5m+6iv59/EKuhg4u4Y8peLcZ+Zy2t7kQ4FbI3hmXmVxnqDkx\n/mkTxs0WH7D6PwoVvsKwBYnHonDmK161cFu2IMNNS0kzTM1oX+QFDdm8eCu60xr8VrnPYbIBO+4w\nMkhpp4qJ3tFvNXTiz+bKC9Jhmt6A10MXwDwgHUfcEl/+8zM2LF1wQIFtW71HHyjlTrl8ezgvRdIL\nd/tBKgK6FOeBmfE3j3rqlvTrC7kevvf0QS9YvHUUEBVwG/Y/waNnJizM2KZTUGRpTQrNJ8b+y99j\nepvmiFaaadQMB1pMNQYgYoxSxuEnU15ZhjWo2BAAGL9Zr/ffyHkHoBcxpYlz/iI4IXPrYCGEhdQp\n0AUwN1/o0xWBJJQ4rT1vsZOGbAMTJIKFZr0UmRKDKiYZ/n20BZna0F6r+KyX6lQ5I8WjKWsQb0Ur\nywvSrYTaMyFHYbzNuWm5oEAQ9Xz7DewoFdbX4fReQhA197aZ9TPNlFW/3EONWP9RksdrMk8qILgP\n8fx7K3mt3OICfTfeW2O9P3/ge2LbbShr1cNO7VAR6H09wWhTRwTSxYTIXy/bStPGX5GrfEswk/CF\nU1VpgaTDux7IoLgJ854i6sHqVnUtv9g/yHrtHg1maXOyWelyjK0Obe1cP+98aWZkOSQehCaJ3Pdf\nyDYQXgOINx+M/oSZrRSgRxlWuoagwzJfNmX37nHCfzajxk2lagYcEq8gAOWe6qrQyj1YyYtToghK\n4us7h4un8UaPqBlfdicmryRXwhbFdEKcqhJiCFfpce7jAwWJPjIASAEwvs+2c4dClq1d3impKYP5\nRXndnYPvkhD5HHyrHqc40lGTvcw2HG81JeEuWRVQ29NcOrYxAdZDM3MqajlNFm4KPFJ+Hxkf52F/\n3dKkvR8cy2lpV25ExE13xr1Fe91exh2KVl2IexsicXXmFFg9Vp72h8Xo01Q8Pket6ShJS9tPEh2W\neRtSyo8ZESXtb/eYmlS3r9eud5juW5xJy6oIhnMMpFVJ8l6uxv5FaAiJ1ou0EgV0ZE2aO4sjYXH/\nlaZjJA147M8OsNHMxQN7BRS7WTiZsb/FU/f6R0AEmkkVR/90sKRYYhbs9/Ms8t9vXl9JpWoAVsGx\nm9OAOq3DbfkYT3OO7YuerL1WuO8Hxfa8GjT6+tX+uOYNjyXqE89/Xzuk7nZfPdUu6cuCeOv+fr/I\ncAw+XUXFY9i/EIRBDRjeI1BGw3CRnlBTE7UUmLRDofAmzGNig+mvmR4GTX0Oy5dUisE0269mncb4\nRsxmB9BW7O8baRCKKBDNVWCKwr+gmHtXhVN/Z1t0axbdVnFEWNr39f6T/0oqPp+FourFiT6onjdZ\n20RdryNEaSOdlViXMPAbNvHyEyRNI07lZrTKLi97KNn4Ow8ASDwEYngohaQoWBjBeyzKvTUYKu45\na0yUeuB8zIuY3Yrp8y6+QOoVjbMCKrJleJnf5FnOaLLW/l92IIofSSy1h7xZmhNK/MXcDvk24kRR\nVzmT2+lbkK2YQC/Q964uZCgsHP0l3YSIAdOyHmsDy233o0GjrgL+Tfh2dHh+94MH439aJw4utIjR\nAudhAMZsqLck2OudCxFR9GkgCsLyR9MbzZrDK01gDt94e2qTBEIPYC6QIebeYJCz+bpTA8Qp03ej\nDkBFKXUUn5wrXP8exjyoIpkZ81yKHXpx+nnRQ8t8REAa5ypIf/UOHBalatg6ZlJW/PQs3YKcYXBH\njpMLoQn7CQZpg6FcLCTIh+twsBvnEf82dwzciuzXY5IOPHDNd818QrYS3FGd8m/lytyweVcBWWfq\nKoyDlZvYKNGbIWvieucWEaIL/GpaV0nej6it6vpkx1C9mcdcpxygg8EwU+Q9TqebsjMqdMckx3YK\nPNUJr8iTsrX9migJ75RE6+w9+v/3EtfZC4hW9khYG4ehiG+M5NeYVqzRaSnGNxTsZOb+cuV80hpM\n5kbrEgdq80c5e8zHdush5wXifTorS0vHdVzUercyr8LwVJDJClHoXRguNTqbGzfRO0h3/SGvKfXv\neJAFBsonKZpRfnFNj6KXfSEdlPLoKKr2x0HKnjYHa1O2nFSaZezwMmf4wazBPQ2DvJ9Oiv4B+cSO\nFrAB8wovlgGSC2XpFWY6/J0v8c/0tysxdLZwUzGbu8dXxS/imWXGTMMPQdZnRxoPaipn2kWbYnTF\nnebNrre4I86/E/MFT8Y21DhVJNzRNsoxMZcsN+xeVxgYBgk2vEV6p2llC7JNVbDqz0KsU/V0rsyI\ngQm/Dv5OknCFOuVM+YOoAwiQreo3nHHdWbkeKYS42sw9rv49O4vtL+QtJG7863L8dumpAYndpX/l\nz1Gp8vM4OrhYt6Qn7Rephu5lrDK7nVzVXDshoC1XzCI5b+aWHtB3iy4ktbPhgW1yln18ubd3/WsM\nnWrccDeq78IHQn/pf1Q4C74LUgG1jkid0dyecwvMHbI2ps7Hu6/9Ythx+yi3qypwYayAF9fPpugj\nAGgFBNzwnSFWMu39vT/o0r+mz/sOype0lCGpF/4pkMi3rVRSG4O0wKL012MrdqPUvL8lCYvmJ+E1\nYJYQR1F3oyY8qWklcIMSIXeGynLJrVEkY8EVdyDlEAbLgd+4Ytzbm0tUG2XHH+r9NCOZkk/N67Jq\np9I+cnMfr/AYnJAzABJPqwC9dekyl7KK4usEpnjk4Jst0Fp+pfNlYFododZooqmxfvkKJOurqkwG\n9o37CP20uKhZzJnqTGNL0BC5/ZrvTabulqD19dFpDdg6BGd4vREAAd7Gqp6jxBTvNRQZI20d2BuN\nFBJ+8CziDWG2CsBdoGlI7NdjcgZdBsO7bvCNqHFa0FqWkby7BKVuAVekUAfX6RitgHKugIXhgtL6\nsKnV8v0tfhlaX1xc2uSxePTfYsMtMBEJrEypxsk7y+Exof6AoIyHBZiBvov/hxU7bSHu/nrYNAtZ\nJOYqBNYGMfxaAcOYVe2Vg/UbCHFlV2HIZiAy/gD74Qg8icJ8RjS1AGd7t3Dk0zDERWlinv09DBlM\nOe/RudF8dTfb1DI4g33vSu/OMHm8yscI3GVxGRciorqLX9YRn0ji9noSlSo9389QCFCp9RXOEtub\nh5gnB6vSUDvEZ+umw/C2GQsl7N03vY9FJEOftg3+o1uQb4q3Pcqa+C3kv7Zvxa0HYtc5N34lWXIf\nNnfbCOdcO45XUaPen+411pPcsCybMS7vYf2boFvZ5C/oFH2fxWLeYOEFJuoD9ORHIeOGiqq2yodN\nvkjolfq3C8HR3ywAan1BP+qtapDuBzcoZheHEq//WJnF/kqoQNkhdeaqUGZTcPEd+ZjArKCdPj8F\npfYhhpY4GrlPpFnwlw0oyYNN2yH9Ii4Ym1coemVDC2afnECWviSn4y8fQLYRbVdrdsgyIHaACUNk\nwyoVtTjt/lMYUFOOpEZgnmcn6PwT0vtrvcW/0wDZJFx8FT7Ju3V7FVxSoVhzWr2NgXApggby0G7v\ngaBBC5iIzSJRRAkwOibIhjQGupZxxESlvPAZfpeWXxnyA7YmEHx4EJy7vwEUvvvnwMK4pZ8RTQ5t\n/qgGTww6jntZ9YLCNz/REKPFSVaNFPCQvQzf2PNJdPe9a7OX+C3idY7WlhggbaCeWfsFQFq1n2pI\n1Up2Ju1qCayXN2bD25j0qONpeVV2wMTfA3/0PQvZ7NjulQy45kwFLhjrHKi1SZ3Lo6IsHy1W1lzz\n+T6kjyQDgHKEPxmgbKEePSYFw9m57IRBSB1lVL/lXhgcp3fV8iFAZbUz9vPdCXYkSA0Mnop9p9+W\ngXFiq9fxsGvjlhzNzacvJJ4lNuEZy/8Zl9ywYYRILB/hbw3jB6T+Sl7DBN0JfR623qilI/Erkl4b\nBmEHK10J5v07/+2OoHjVtND30VN83BbYkj0GCA3AG0xNTll7Mqce7tDOC97j4C2DJqkJ7bLpOw/x\nNzvjLevB+tOm5fHydrs1fHRGOLNpTd+tNaXzZJLicRPAQ3PwRCU/KhfUhD/lnwMquRemNah3+9J/\nWbDvDX7y5pZAwtFvTl1Fx9D64CTBMDRLvToJsHMW7TNnmchuf6e0UU3kSMZ7Qh6GBQTbWX3QM6H1\n891oVivzTN/iAvn7S3PCQMqWca/8EwEySxPLhLv/V+g2qU0vWgmRAwgSZGW8qhB+hKiyROe4iovT\nZ7f/ATkdIc/NU7F6uAOSfbTF5HtIKkHTtrRBh/GPODrZync/1Unq6XicDyUoFNdJO0otZpWg0UJr\nIm0baDbtDrMr2nxM3f5NWpkThFB7ogT7J6jP5Uk/W5gA92yUYXraImArkXpJIkzrMVUBcZYjVXAK\nby5IG+0dAnShjrYUMbCDCeWRqd23AQ+Gmib9SjRAvoyzqNSavj1SBCaFi+GWhUlDEzJRjcx8ucq/\n1O95KAytmC/bzLw19wV7dcHvXpYXenZdTj7NIqNvkMdEFQQ3W98i9NwAcYtUOEda+02qLkc78Imt\nEFLSJZ7EKE23BqprZuOH5UTGjH+bdjHnBephoFRnLuwZvF0sPVHLCQz6E11Kl8x67Lg7TMz/JMGy\n0QWWJno+6E233Lt27bt4uZOF4ridnseWnNw42Mojo2ZkS+F63DJcZlmjFOGUVnis87CHis7eVVVd\njVZWDDQ6Zn/wZ/rKAB7Nj8qRVs4g05fCKKzodda4WHnCVF3g3nZA47sdOjb1VGpJCwXqP2YcpkFT\nTAXPnPquxGaaGENiXmKqa5xdskfuw1Y4af7vm1MqI6lcPOF5TxhJ1Qtt53NI+69mG9IdHkpVNj1y\n/G16ztIE1JNeEtmB+BYO0mO2X0dblG9J2YB752FGSgWYV8EnXjP4Sxw5odQw6Wt5LGoLlfylOGcu\ngbhuMJQ7pgb21+gJh/ngTUpwzKK4Hcn0fA1ilriMz/e+CfZFP2IgWlQ15Yt6ECjl/QAX3aAyciLi\n2pcfzoq/Ic7mWuUiwcFzJPte9OngUghbbaNHB8SJIMiopXVGkfr1KtDxrZ0bsWfVaqkM++xgcUOo\nbMQ4UTmjeig/FooIwVWLCwUblGVHyWYAdVeIh3843mflrTKFyQwuXMISN+lQO4i+WEPWHPkml7La\nrjWlBEditPmyzJHe0W207fjznpN/km+Ne2v/R4elmY9pdqL4KL0ubbaOaZpAvlxlAisoaIZVPDq9\nF4oUjfoRR3053AluL3WEd8t1hWG+I5767HWYMG+De6VQRXGb0aE+8M4o/vBinyggTiXrkFS0wkPm\nPSObUf85seJ5x9gm9winqS0b1+5gIKEfpDNZNwf7r9+HUqvigZ8oPVsbEWjjT5fm2TgDLUbBVrT/\n8eMGSj2YLSsfViqir+717cLXHWH06yukH4WjaOXbulc7zkI4iHRX5DuvX2hDlEUCXju37W/7eyVc\nJaxXcJsw02ylBFhVwvLwRDiJUFT4s6tL3oofXqp3SAfLfm36qZJ5jjLjKeUwjot1eGA+NroRHqH0\nmgtjvwYrR5rVyVbWrYwo34eren6W2O7//yte0mey6VJb5UQPVQjQLDyFHJ8zSG/AiRjgwri3tDKG\nrA/0fUOdQGiz+RwQmrOjtDLah0oLdcnKNGdOuYgfRwuMR5kqO88aRVVDccmhnSjkmckLlEa3UbW/\nCCaLOdPOZVG43P03loHDBkump67PWIwSJufgTY2dzbjHQYWFJH4Q+HXVMJAaKwMREVUD4RfgA8lA\ncyJvj/zKyZAJEdF8EP0rk8ZsS+FplatlugSCfQVGudYccNSYpvVKtoiX82LcJs9S/HqsqzCrhkA+\ngDJEbI+8wshtd6KxUXstlXRaPBq/JYp4JESRJqGNH3q0MPWYudy5IU1Ex+Lx/WqW4Cyt6RXnulxh\n7qYgvc/1Li6u6wA2y1x1R9g6qBJDOmN95n40iDkqYuToeiI3oC54fxAOfE94As08xEGHE8kAaOta\no8l+uX4BdtrDoafhBf2VH9N+GTluvEe71ZT3DlKFjbKEsaA/9rj28XJic42JsPn5qkuf7gWNqSA3\nFkaQ68kOF/xwL8BFwUA4I1qpi84bn5o2gVQdLJJzvEHtIQTGmhCc685iDeCUbdbkw1FT3EXdEz7K\nAXzeVmsQTC3MSoefYgbwhcKSCniWMFXMwZCvqu1o0KOypwDjoi5M7wtwWyF1ssuZ/ERb8vFk1TKq\nAckwlJgpVQ3g2JcrjBwdIuAb6y0vpTto8iav0v/pMkDxrkPHa+5edxeg/bR57Dg9M9i6T4QJB6x4\nkkfyZ1w2jFGdyASCxZg+4obC4Xahrh5rvE7rpL/jAt6/JytixqGe85/NdmqycrPD3SpHj4HG73M/\n62NrImyUrHvAP/qdOGD93JyXizrcbws9HXLDfuK8gmZx0E+Q17Eq3ktdG6Im54bdQOOQJT4sbOhj\nwp0PIO/22O0nZVQBFd4Xi2gytLXMo/Jexr/IaEB+IOp3WfOvck/ycksR8uztlg5RC4mpYN3WvnWk\nebkIUPD5cYMCH55xQdzKPFCwCayAb18492wALyccze3xXGlUZkys4O/HRH1NCzgQIfHuZ2894SrB\nXxp20sVF6LGPOCfyBBGEGgpXlUGNgf0lYkUvh1XfD0U/PLpxY6Ms+fNecyGrWQ9Zboy4U7deDa/c\nlDarHQTyrSK7K96Z8gTxVpqWF2ltlrb64uQ9JW0doObxUxumbu3P+d4gfnwFzwxOKVzdeMyxe6ho\nV9G5KUKsBFPZpOaKb5eugVmH2PkBA+lWZFeHWTgOtJYCBZZFv6u9RSZ/ohBhg4bYVotZCYdVwtqa\n/z6XJaRdUKc7E7h7UU0qs4oLqh7OeCHJ9CIFiz6fOTG2ydP3O/+LkIHXj8M07BNjV1vW8hn0jA44\nf2gzojPMkX9n+D0g3kJXmDfyBJzwNG5z9hK2a6xXRgJSRNSGNPNF8Q6IrUJsBaTi5m3lrKedv+4a\n+kNlozrJBXuzvH3eArtARRpnLD4jSt5HAGRSE872rEU1XwbIxMO42s3NXr4zBQu92AdAFd6bfp8H\nb+zjoiUSdpFuOIqfAwt3fxSo6+1wwapPzNlUqHhMfKTiKqOukaeKPDs4E2PP8jHXvWzRb2W6uJ8Q\n59Dysnjtz2acTJCJW5hkHDIlnjwva90WF8hnAXeWRF1JN46CA/Rg0lzvNiHK/A7QSJo1H+8uRIpt\nkR1XM8bh3jWFkHTzVyHdNqPl8PnAjGBM2Z1QeXZJ9UgtO2amnqcO2uhydu4FcnssdGAo19p0K1h9\nDAAuNoaj6+8g5By7RqQpjLssbVgkTyW2vgACzh9kZEaRaGbIVXc5EbiZ5jUniul3T1QSfYmNpXEi\npsmWjHWBONA4r1AG2GokuJkSYdWmkXcnTQrzbNJgVbhz5k2/PbdNRU9yiDX8+YBKuaeJO8r25UBX\nfErFZr5+j2uKwIwBpHVY6ca2PRs93wNUctx+wfT9BmhWV0KOrESlVv5+etnqOZyBBj8AOy3jNLaJ\nMW6hFuSWpjVJiaK2u3Mec+zcJMOqdTpeebSCfSoa0Jv9KeSoeHd8FEP+uA4+6ufZs85JJSTJ6YeE\ndD5VHAFVYTgP7+/ydJa7bnw+leDGzHgOlIsqlASMGbXtRLxobUDu3rtJKrKLvzuusyGTvByu6ANW\nFoi27fW3leSO/k8mEYEYxDviJtlzV2Ew4DCZwlCStk7F60g+hqb8j7JlX/A4sZ7jNvzGf33+oDoI\n51RkUjiaAWH927l0Zax1VnBHHNGY3/aEcP9cn0JNLWqXOPEZaDG2AEViXc4SXglF/zjYRvSsh4jm\nlZDf+6JLapKNFj/U6WOaz/1Q+jnLOy/4jwlbGUui/0pxOwjO53EiIb8+cuRNv6lgncg4kT0vZhYU\nqI3kiVjWCqaTVYo5J0mDy9VOufJyjis/Owf30YbzK8tXhskSMnVGCEYaXysqIegIAPK2MYigbHv4\nYgV5UQNE+eud1015tIvPOBOxwMZFGoZE+m6FcD/lb0pip+7XGQHKbLnWpuM0J0Wgyt2oHHIWuwcE\nZmOznDdt9PUrecb4M0RmzKCR49k+FFBt6PVGZKkTDAMkfCcLL7TnyDp2ufoPjXYl8eFikpZ76AyF\n0O8LbQMUnC0UuD/IV4loxCdPwND+BUaV+xpgcTJLITJX52+GBY3Jx9Hr10udTcpWA4zkVkU56kah\nUtNfcGDqHyPW9c/wdOsB2uNwjN+kH1WUsm53Gl6HdZ240slkKAY9WBm70a2L1U39AWs23CzTZB3W\ncq8nSDk+xg3/2LqE44rdfmqjx4dlr74zmxQFFwnzD3CgIZWuHOT2oguHOTgfrH5gs2jT8m2F3Ksn\na7VXwcQCjVrzGbUr88rB6mXeoiM7Ax1aH9Cg5ObBctrpOejx9vBF5ZDxray1IgUot9VC1om7YIY/\nVdYiLhpe5Id8gygXCI2InUDOPutyjOvW8Fy9xpQOZxxhtV+CO6VFfW5C17Xsl+wBOcjKMGHvDGga\nDDIUGcFGlg/SRkMWBD/INUhFIG+AHsUj8zdIbmx+mIJGl11P9RlN7v06g4LUa+/N8sxmbEpZ4TCV\ndgfWQ+O4OMNl0uOoqVFcbkk5KySct9h8AAiRe1pApC4TpbbFdrV4F01uMNDu9JgLSfjJBAS0Wqsr\nWVP/tTJnBDUHBQREgEwXmUZaPmhI7TTJG3yrXoVrmGoeIH8lJRFxDIAT0j69KTSQzC0DnH/ZluKG\nlQu4BEMiQZpzAf6Ctg01cbuFOx9ZJlV9SQVOt2LtsaxaejPLRRq35SRUoZmqeZvHk6kZnx2JVutr\nb8tHbXcf4jY/xYvfYEFX4HOSvaOWoKQZp62bHLvvIaZSQc8zzZD0dz8sUqUONgaVEppfuM/WMImq\ngwMnGFhZ0DpjWeDdPEdOvxllLjNCBrJoMXk0NoZQ6FGekTHCdpuNxIKZDK8PDSuh3pH4Udn7UHg+\nkCip0T+gk4au+y1JHVcNdnx4ZrQgCc/aEC2T/UxqPRVw30xYhPl9qUGdlYHqX86Nb5nBWaGQOpy2\nFkj66xmYSqUYZThyAMQWkV7q/K1NcRHF9iD3PB4KbAvRJMbfPXRsVwK1sSP7R5nQdxg+YTaUgLKH\nDnbPx89r3MBelsRGrWQJeEa5pk3C9bDfMcDWdA3j6rTLjl8ZtTsrkn+mjWhO/C3F3s6rMY0Q6Rn+\nGUA05HEwcQ+1b3I/p4fhvDdm23QzQyRXUY5EtnP1HeP5gBk/e1C/pGOr2xgZ1Gt5FcbFfx5pvFJ/\nnG1+MqwEwLebNnBzfAgF/bwPd6KiVEFV7PU93PgbX0q8GDHMCYW2pi10p4JVorjoZIwsHTSbH7/h\n0RWSB10CY8WdocmknRsCcU10+X4Epi6ym499noha9lvBByhG+opGOQ9HqG6t/Nw31Y7U4uNj2rN9\nf7556Lp1BLOQWsAVDjQDMgRAKMpP0lfriq2XYSglbcrNybGw0AEXMX6CsFcW8H9NPxXpBk3Grt85\n+m19BUp6TYd/OSiSHyDJee3n0PlTXidCCSqKWx4eIo/SdI0d8MZrW+5914zUD/oLyNPK+gmxbd8d\nmQU2UsCClOF3pUxgccR7Dr0Ux5C6UlZBHhoIRS2aDhZRobZFqzrUhmSxSHr5vamn4txkY9JdG0PH\nntWgNn6Eih5VFDXV5NS/w2Ogc0JDHow08+Dpgy73juN2rBZhn9PVf2oVCw8uV0Wz3NN3GwV21Iuh\nzbdb5gaBvL1+lOE63dPPnCnql8P6/E/RjCAAv0pCb09svITM5W623E7wVXV35pVGDycKtO0rANJC\nQViv0aGls9jehkvD+pNfUKog5rxHFMRxGgeUB3fAI7Ml1jLS6hzuKKqBl9H5kI02FSk0Eqx3sxWO\n35z479p6mI1+CeKNkM6R5jdFKLVcux2jWoWB2T5Ze63CdwAGjTs3QrXiYTcYkJONdHNe/fgs0VGg\n4zzkv7AXoIsHn8K5HqyqoW1X/r/x3Ql1Bc6mXkOmRkfa8iEXsTgSOST82UU4r4lfHCjjCLSi6Sul\nw8E/Aj8Si/TOh2y4xv8OmJmuKbQ0YxIcbZU5UTZyvwtJ8GapX2+DoPhmVfJNjPYFFH5PQvehmwmT\ndgx4rhZxHqkrYO0lOKg1gMR/24M0cGkpIyzMExAGK26SRm2HjKlpXOdwCbft4y3wtruYsLHuNDpv\nrhHUu1Akv93ikJ7v/ghFHVTdo9XGJZVxl+pFQmrNu8vD8mG8C3OQ2TlAVpeqAgCCRYX+Ly35K0a3\nhNoGqO3Ul/DkyXYbdwbctWpTC8zn9EBzNxxwtkLhS7psDn+TWfDlpP7Z2XYi4NVSBxVGgapS8yzY\neSP6L7TD5HKcQnLW3CBtWk4riZzf3thpYF7RXIs2t8iL53IdB2YkikGsMu/BnvPFFJHPF1XzpTf1\n1GAEUNn4rbgp+h9xj0odIY1m7DYoKAwduAZ53fF5TtaY1gklZfRtZdP0qJISM16uWVx0VPaicdJt\n8l9pE5rmK6VJV5bfkzz+2LeNjen2iJLIdYR/EH8nmjzGQin/GKIGlG0XfNknxNRKkiyE6KML0hNL\nRIyzOK34XYuE4ymmnZzgzmS4uNCtg/oB4rw4ZQ9Y06fY6x/M+Aix7Z58rE+icVHft8BMDmNIOKC8\nfkTIA9WfdK8QoPSfZ9P5RQrGQ5YW0d1wRWKqNIYvor5aE0MFS5N5p8rbzdGtjMIOspT1wd8gmJgx\nv6NLOSdPV6P228cpNZ9cnGr+8M7EerdjD8xUTBZO2e897RQUC04/6LIJGqfBFKWsgDGv3kUXOQ+t\n5WOI0tbmSVFDavJJmzz61GPMnT3MKugw6r2yqhX2Sv2A2P6cEsDq3MmgrbdWs4cvzQsPMclNmgA9\n26joYmlJsUz0ID14LLYezi35HMN/8znhYLYkk+iO1Mxt+En78EKuPjQA+XRu64aKTT5CeK+icB4G\nRDq5D4mWKRODlLhEcR4vJWer47kF7ZxiOPFc4h5TvQJwX8bV9+ttvSgdTDv6+7BoqmYGNDM0KrbV\norA4ymoZH2IqZevYvXn6gs1t83upmYS9E5W553qp+pVav6PxGbW4E2DNmFtfbK22PZjn+NOfdOnC\nZRnmbp0KjISOxN1DplSkpppMGGLEvHhS+99+xay1wpK4NXbskGhIBKAGDPQ1M4/JnLB2CLHZfV16\nmYQjktluxwp/AyDDJRPX83Z0DnyMATsm/SpFNKnhxuVcsUbnW0OPH15IYca/VfEJ9ZyQUJv5hS5u\nbua0je7G1Hk2mbj2g6L8ZxialXajFTc5kaTCPPOfUCYGlJd5UCXUSvSmZS7UCzs5qMiMNUzQiWfy\nN4N8YDSPh6mPXPDPwPeSihf59jWss9LgWf0b+r88XS5VsNtxbMWFnfrP2SFOStSXfMK2MSP3KA4p\n9vOyrwrXCe37G+PfSql2gEI5vis13IlRhYKXzyk4Nf9zHg/l5vWsR50JJ1ddhKx0YeL8cbiAv1AT\nlzqGBgZAOkMinsVyO8qDWgByqaptxT2sPOBxUaXx1ZoH6h5A3bjlHG0iM16TAZ1BK09X2pDRiQXP\nEeUGB/kTxxLiyBK3BciO5EwCvaTfsVBowIZyizCoXrKOrNeGzAg/E3tOfvwHDk37f535YZvsMI8F\nwsqHEHicB82TcoXVK0yya49sKe0nkMmLcxa92nKzKrkeVuE02y1f27G8gYA2JKmh34DFLfoAf42c\nFiidrnPcZcHRaiTwb7P0kRZqbZFb0V8OB9iDZV9qQq47ZGq+OY541WpW48zGqvLEAjH5req9LE8J\nt5VJU9g7kzgFlQVS7vH0yKnN6X+gZ/qqVtxLYJl6KtWDQw56F3VSxSnP6BXG5FtOsWc54oVxmYJg\n3dez6qaAnUYYagtXbljgpL06Z5uRChLxCUJc6O2wbS1wxckRA6wlVAPpxalEACteY2ao5goDytN4\nb79hN2WqDvnzQFBvMuZzYZcm/ZMNPXzhEnTWHsD1mqxhemlFhPGocUPxViD0lvgbYusbzoT7Ze9i\nmkasjH7XeUfF4Ov3bAvYlZx2nWoqBXhBHEiR+g0UyegKKyevU19Iw1Iu+2D/7Rmb51mkq6TRezIW\nlmmvYvKf3I/BCjmHxYqsb1fyjUK6p9PgNq/QjqQO25SxCLdV3eKzUCT7txEVJs7W9dJ616IFYBXQ\nWDNaViIKApw73K+44BusnPAYR1vhQEHO3MUjzrGVC+LyRDlR2UxkRbZgVxu7CMBVMJwUy9SMxYNW\nIodQH21No8Hx7ClUbssGWqFfF295RYSe2vKz+QXyC0jV6SrsytjJ/acQyYpkx6KSSendqYJdo1d2\n1QWP6k/nCG3Ot+ON23JWRGrFn7ucT31h8faPpSCebSMDmXJDnTEQDjpvaj6QD7Yu/51JkmHCN4F1\nrE/n7gHwgH31Z1giQVUKZwKRPxPTksPdzyCgJGXSA4aI8uXuOhBfN+xZr3tTwvSLCYLRWtQSn+x3\nCl1pvQ6nTXTBgxz79p7m8c40xp7aSa3b0hhfn+Gl8xdW4pcgL0loYtU1le2clNuGgmPG179i2/uu\nClQMjD4GD6BcbDzDFN/XpL1dZYglqIbXIawigcKxcFBYDTmsRXJEFTRn6SXwjrYFNLgfC/yUdNkU\nEYEtBi/0eKX3Wa8Lh9XHiXDmlQd7wsWBEiSYEEkjTTNzhon7XJN6AAY43NjalbBLcqmX5l1i/8b5\n1w+e5bzSmX0WHcyWCoThx7WABeHWdLytMuWx/fvk0uGexf1ytVbX9XaF3vziR0SYJ0QUSF7jYoUC\npqmOwDSKrcR995m9qI2IAuYp2yTCG7PvKdn4FkjrjlHuD9ycXdYWHUVR/WgZToqeinwTdeRGLCp0\nWuxVRjzkfFKvyPROUMnvRny09a25/wTETVo+crnXSjILyUWQib7habPmyEoQLS19e32CrXE3rbLW\nmoj3lJNj9vOsZDJkdcnDb7iZ0+KA8CeLMfm6G6sGBq0GFq7IcP+cwM3wzB3YrmjNQBsYzrQJMsDs\nCaaE+TlVAR3KmrEXssfPInpTbu70ZuWlwYbPGSa5utwno+AOs891LYQKTAKwcpio20sbSEnXknOA\nihNc/KO6b2ODy8dHQYe2tWc3+jmqozOQsNHtNTRd+vAt+2Nh7Q6+C1vTppWc02x703ZDLaYZiWd+\nku3ASFwZm+YG3ac0DnYfXoAVojQ00ZeY/QHoBaEJFYnVEuoergfIF/vA+2AYa9g66cZZ0uF7ITfp\nNDFK/Rq90btOenrD4sP7dYLLMFOonJlC7hAkJF9bviXGYR4w95entPxMv+oPFhKr/83KezLPclOO\na9drF25tp+Y2LRZwB4owHe3DFce+DT8VZbySR+mqQqShnb7WtuAyRLahPs6DDEEQmS8EK8jyPSXb\n8YOSBnxG7XuKnw8Lv56v+NONoGQwsgDuF5jfXRuKCu/9PeSRVSWqIx6tIjsBWQON7/sMrqDUXhTU\nP/z5b3GKlIrmN9wVF32x3RLsZ0xs+PeCpcnW4neNVzSi8e54CQQEII6q8yun0SBH+mDXxdw8+jCp\nI/hiG7Z+NuoPlKjvPFqWF8yqddQQ7LmB/oQFkrAYwS7cONCc+g+9R888UG/VJjYRWROlwD/VsMkX\noBwb54pBv2OMxZVFhN9946P32mF3Gm33ssSRTTlY/TPGveeiqD1FtepBHnRIQ+XAN2eP5cd/+Rn1\n/awP0x8ME09OdUhn0XGgIksd+AziSrA1GkKiikudfGzQvqj2a1uwfOseQosoXcGOIAY4V+krSmPk\nOvZXdc4/dvSxXfv7EOe/i5sAw2LCbVgprkmeemR7K/H9kwesUv1xAyy04Ng981gTa2Pw6XgyzlR+\nWHKApQc/FJa91wXVrNLOKiLV2ttSwXtyROjDdVQx0XuxHzTJudCumppXwifst0D7pJa1KWx9iUvU\n//CF+VLQsubHA0051h4+dPLg9073kxolsyJbdjOm+kZXvKWtLN92wQ3qa4qmHE/kXtW02XKXPm+t\nDOXJIMUAp/C1tRbhCfg6hhFK4lrKvnH3jVpmKGMOi3rELj6989e9xj9HzNC0+TJ/IjS5Liw2g17l\nFOnV5xIwpUwN5tJ/cf5nzO3bmA67ENfoKBK9XHULdImTpY60ZQWh0v6dyt+zRMcMRMbBqkcxXjOh\nd2drqdtPIcshuCuIYmcAI+ODGXCFtC+tjb+q2EE7wlCZiaaDYdgVibg5yenqh5ZR7BlG8+dnaZtd\nVVqTIdwYYFgSl21aEa0TIEX7TEA5xN4H7Bma9vYgAHiOS/YacTwQklxMDXN0FXGSK44neOurRYmJ\nlexE8qaugJ4Qo/MbKfF85yXvxrKo5cmFcI73AiJm+04vQkS//MNZgqJaCj18foDt5A131OSCS+yP\ns+vMgqKRoTQXCguDOCbv7oOD5AL6YcJRTZqLSTZ2Ep7t3hxYs5wtOf5II9zef7NtL2AU8566AwcN\nBv1X5NmA+QBq6A8+AaNuk3Sk+eWNYR4r6FJbLmj7dEPVZAJFLN5Ldrsx+FDDTwgnGpIE4vgeZBrl\ndDDZ/OZ1tIflMukpwYpuLm95chxPPMgHhcr2TY0T44peWcWCX9mf/oHfU0EIaQ1trQTpWZ9UgOgv\nJ+BqUh2kD/ZY8xY3ZxtRl5cUS+d/BQ/dGNcHVXfWGpblRGcHuDXQUSgQIQ5fs96PCpEWeQrBEqce\n835ejJOjwckfqKguukrarnK9MQTALwzxwrF7qSEJOdL2Kd6E1Sj25F2frPDw775D4TTf+QnkzkB8\nuwLul0inUosRQWaapvR1jQJOzvysUAvfCRA9dgbKem2n2Ji7r9ZbpYkt5b9BoIDb6VrY9FuhpnFG\n+N7rkUrR/VFKVZmWTzc5BewyXbTa+SblY7FtvUZ7iH9BvCq8nY+IxjG3WGx/Vndxy1dMnFBeIhHs\nfpRufL4fC+GfMvJBxJxoEyfbGW5BtFbo+uqfUq64kNUw4oVli8A5tLaYd9y3/LdfbZn1zL1kixuX\nJsBhRYwWgGKxpbo88x+3FaGovmRLQ0uiAvf+lzDVuI17RFLwvbgS4MeNpGqr0iK43vohOKiALC7a\nmiUGzxMP9+r5XbhAx9Nah3riZW2wpLIp2GPuOBy2GtwBbNKd0w1BN8jfH6p50YdFZfksroMqArR8\nd2b/qG8VwPyVt1gfdDrNtiGzZo/oexOiCXWDx42LQ6OtrcjQUGL7Eyh6DV7+/QEX5gFJ2McUflPl\nHbyv6Rf4x8c5wO1QsEFWaLGTxOr6fTvfFZ+A4OZhmC2IzniHjL6OJMykDxbrGxcfumgzokHmy6Bj\ndqfZBV+yYdJaqSjRjg8TQS5xL+31qweX9jy5XPRrZjj/nPO7WCfrALdAkZCRLbM/lB3CYp7snq/u\n2FQPUJKzck84Q6brIc0yyHU7cZirWPuCCJm902jQfF1Z4eeNBniVJqMxGxD02fyvBco+zDRR7wg5\nMwKvzf9KCPLCMRDMCwvw1TZ1SLv0aWNJ9yJp2MIxp6PpsUIjg84Ne1nZTjRC667gWR8RdM1HSMvp\nR/7CjeSVYqHKN6klkOZrtYFEWmP8tS49pJMupw6rrUtfubwgMJvsVlsb7zVRcFr93LNl1H0e/645\nyXQRxWG2+4wTzpf1vlhQHumG9ELNNRScKfUtMXWH8NLo0b9JOz4DX0BYTMiPXTTSr+rVInFhH9vt\nyrLIir/KW633WHZm9HwHfVrNspsymo0wtIEabYHgDykp9IqD+mncW5WQosOpZ9c4vkofCTg+awnc\n9g9fe6dakktrevhHyNh1sB5eGeg5gfeQHNFELghRHiRSSuuaP70GqMPN6n+FgH2kSfiBn7WOfo1Z\nOg8ypRlaIWlDvEQozS+0hlB5Dt5B4dgvD3VHzllJayJgpCBBigpy4EUqYp/wW8UAINtpVtpmvxTh\nrj3DAKLlaTDm4rtplrM/QG2R2gSl3DkGIKa+oslquw9wiJUDsStTuWkX/Csqg1hF7yHpGi0gjWgp\nes0ZFOARHpaTv1eNyijqt/5kL3mS/Uyu+Xf7nqYg2sW93lU4MRunY4E3x7gVjVlnDqrH38RsgVbf\n/bAB53riBSBEVwvrIhNCLJf2YSx0dQnknNj9TrGqG7wg3siYtKyw7dITk+j1adr1yT4WF3JPMXfc\nCGCzd99DwEMf8GebDHPdamt+dEcMNraG0LlM0/vyu1DcPydE79HjWORYiwyjETFYxHgP0ieLY9/7\nbI9J0zAIV4h/SBn2tQvbZPMzROTS8cHMtYmGYIAW/DOx4F6lPzxBsQxGcsi5bomkSw3WG54ymtra\nZtfJokEersbLJNwoqItcy93giFl9IAtCELZl3/U1XZHZg9mEYTGHi+vBdcGOqdpQIlvRX9p1F2Ip\nTS+2As10HdT+ixcdc0Zilu3zsL1nC7aL+qOP83pBQo8WlmXPB7g/p+8+Whhe+6M313uinCh+X2R4\ntLcLDG5oPorL6DrBeWkOCRhppgNms0upxAws0c4vpFv1G5Yi3kS8D9QjDa9PxB7Zy5XIImLr5qPc\n+8UsRuj/sjnk1nk8FLFkVBuK8anycdHLyZlXSBldoluzkSexK2ccVW+p7pHqcaL2LdwCThrtKHPA\nTToUHml18jm/0AFR4DlPjn0Ay83jr2CjaCJg88QoYmejDgsmSwS+qrzdyenn92N8YNQwXHnOxvDI\nEX8NEjgGwejNCX+F6UDu4ooXRWCHV/db1LUmOJi3tZ6pHl5T7C3UGZrLvvGq4rqTC8dnXu7QElEl\ndXB0Jfvj1WkEZwRcfDqnNndXXvdb0+eXayHK5eaj4SRInIPnJRdtP+2MMCMg3IZRDGKyyi3qm+9q\nnUkNNue5OIeLn4DECovWjKy41O8/ssjasnXEaC8b175d2zW1YJudXn9amXWCbX9Ud/bmb6nBE4Mg\npCO8ysuApFyU/RpvYgZgCQjbJfU71XAZCVgt05sizCXay1VKVROFnEp4uljDGbKOjbHbH3gaC7I0\nRWZMB6dkGm/ZxIpiU/6RKB01qIJZr0erZoOeIK42YBb9tyTfgSvQD52iJKevHGEhXK2s8Z8x9dqV\ngbuqj/yvDnIYAOXW6DSyphyGUq3aKIziCwwukrCtLswyddA6M/CtafF8B4FN1BuIfx/+G0b6ngwm\nlBCcR9txsFqfBFL7baf7JUUA5EOboWh/ow+ujMJ8iFpfInczwga6nLqBexAosYjMKIre1kpSkuk7\nmegLJWwe2EgVBEDQ+FmrZqOwYXmJns+jqYMgk1QuPZ8jdmeZuiWEaoAqPj/BjdTnewI/MRkRQsdY\neMANESKrmSRpTRosqItt/o5xjdCDEWk8hsvMP6Bj6VQ/1SArS5QfXG+Q/Y8E1dB16ZwIFCvFp58f\nsaGN0k88w2vMwShz0YC4qI+VDEaGMPvj1ETiDId9F+Tk1HacHTQy+l8YVIKzpadWyDJUEaOHUqvc\nV/kktcLl6/A+rZacuEmYxtPG0SaB0+bzx7ulrKNeyDQpLQTxgW8cxwbZvxcx783MMKW/oQTKfMgy\naoO2bwD69EWFTjHW80RXlrGm0cI2zi5rXy1U+NuljLwFfXu458eZWWzbfGKiHRvM2eprcivaE45u\nhe9tUrWmJPNjmytP9CxzArvdMbGunwZGzfOtNt0YrijI9OLSvrDbl6x88Sqqw4GQJVKTm4/q7xh6\n8ibl/9i80mHDxOj91I3UiCwqkZg5G5zVN/4axYNihActqP41F5lLkw+hWR5kQsFBAFQHJT2SOVLa\nLUPhs1boCE42XK6Gfj/Tx2j9Yd44Qx+XdDEVSyZWuxsFSH1i8yN1NUw4ChRYkNerHAZBEqCnNdYK\nw32X9be7UtGPqWm+3kydmuOe71OrhlKu2HeBilBviVP0AYa/zkoUuFj3s8Hgt6bSKoet6LloUUgJ\nqI8wIbgurQBUaNaxNnZ6GxVO9KTx4uKjRMmSU2XP0Twz4ImN3C6y+UBZG4qhw9TRUwf76N31aXXX\nez8PQ3sgpQkm/gt0naEV3+9SFysH1BRKSrz+TOIbPy2QJV7qnWWK5k2FNjHhbbtb+AleTOtfBoLe\nEc51YElVxUKld/cOOHHazFVO/nT4EqFRiIn799Zn9pqxR1xVuX13gQXEHlVlh3GnV30FjahAXr2x\nMOWxch6dz3IBXnmtnX2n7mx1OQ4jT31f/LAhehnnyv7TpK59ZVYFQh9c8I98SXNxo7wb5b3nIqNF\nMjBSWnwLaerX6UcJ5wPGVssWMw3zOtuQjt5MxS/pTaI1S1jL6dio5/xyaY6deEFJ9UwS/nOXgjhU\n6NIeYRg1kI4nSBmdu5f8sxS7Qp/N86BSrRb18TCrGZco50Sw9wTR/ACbl/Ch93aVY2XnhtEYIFWe\nY3nQhAncBNIhNdS6reDaGsxj1G5BA0HDk9YheJUOGCxMmUG2sRwD7LpOjbl+q9LupIxRmUdvqvYD\nJKntjzxXKsvtro8LogYiYb9jU7/5yiFQpM4uCDTXQBl+n36tHKaSLrOH/W0xGbxcPK/0m/f2h/bI\nCbQ4FdopFGjDlNksSv1Y4F/TlRRs5+ychHtOC6UcY+BgwNJp2Gat9d0aT1oXlCfNnY04bSqAGmNj\n8DZTRVeCVeUzmHHqyl1m/pWKL96Gqk5EI9JtPjXn1wuNhHJ9ekiv1uy4uQ1o33Vi+ASxHhqBazSH\nFQOgKrrK465oVwU9iZk8Zpt0a8UYjBp+CDjOP5tFwWpi0nRehaSdfluPmr1s3qcre4Z1dlyuV0jf\nXfgz5hiEtEcttscDae5WKJL6W/0vYIFH2/vsm8OoD4RQPSJNN34jUFlwqzZEPLtc/ZeiJIqzUumu\nt64Yslx5F4I99PgpeRYFCw8dD3CtgpNJKeBoTpReAT7O0ob0NK+MEpspLAce7CGA4RRjowNNGMZj\nbwf+qjEbROMQm/19sdfd4eoWtFMcBEmUDcIwy3zadlH98AjuPeKJtAWtfbfzFWDM9Mcdeew5V37J\ndf1g2fkmvBh5dgTvCXMr2x0NWwFcd5imxh94VvATHfw7O39QEdBXFfPj3ffEeqTAgbel0UvfSnjU\njZftrWynlJu4kqQSU10JfnORHe4h72DiU/HtIjRMysSqF593SJ5BRQkc3ByixiPExTfE9XghBavi\nhedetJextNsM2o0MfQZ7M2NMv/CWFgI6DP1xZ2Fio8L5dpeAqYORS+WFgznPUvW4j8x9179cliRC\nH8FawTKxlGrZ/zMnEQqOo2fMkXd8byn8oV2qv/l1HDNFJXxAzGydp4ep9xXaGpaRCjqYJGv35KRC\ntxLJsY10Td+DHMNcdv6zJUtkWJdetQUQjsIqxJgUh2NTibilW7zwlph+ltuOQiZj7dhGo2NwpRxj\npRSOiTAthj8O3Oox5lTjkWsZQOJYZhsuLWdQf9lHcs0ZUsj5S9+2RM6U0rewlBsYMkgeEIO9WrvZ\nnFWjGBlhlIAI6hW6Ek754Y1NwfwcihhMlbFjezjsdA7r0d57sHy10dnyKk2dKzP4lsXx4oFswI31\nMlJeO4e+OQuXMjC2s9QtD99djW+BQN8vS2hss2jXp0RUFN2ALmqlKUlQY7F8Qk7GA8W8xEdMSRfC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CgNeDKXAqsyHlBqiikZBELrTLQziUuO2Ozlm5IjiDh2U1AcE58FeYpCUcAKk7tuudNf4kA\n+4IZMoylovZMIy1uk6gDeTs8t7ZT+qbKAYqvQHGc680oqpHHqBGMlkn6SvYbCvdeT57YiL8qgbua\nHHRqgt76f9I6m2gEbzKXyq73F1XA7iNkIQH6wvVGab9k5vFK6t3VknynPia/XwHedkmztqfsJPcL\ndpmsfLCWWjJB71zBzndOPEH4gQlmdtbPTUCG907wykBW6mbI2D6F8RXBFxLFiTe3lLlK9f6JqaKS\n6P5Urf4pShGjQxePyekutNDkOXiqBWkNmqlwZ0Mf+998Ey554Ts5BpfAZKA3iTDnLqa1WjM8MdFu\nz5cnBm2QmsWFiDw07bde4lWuor/GigLLSGoi61c1W9VUUTxsmRW3Nm9hedl/LMIi+IVd3Ie5yuhm\njFTZ6GPtxceQZ0a4n/9zmY1LfzOKboZDW8/yeLpK37K4KdBjNJqUeWPNEgbkAwu3B6nDVdpVe58R\nyE2+HOOoxDbkIulCG/2Z/niLLNiqicjDej6x19gTcxFfvW+AKN3OywTja1dzXhKcg8TxzQWMPch1\n7hIDvB5NzUnEvJPUkHECOzjp3pErBKiXve85ZxpQKaT3uOCuv48BGPUNsb4Lfbil/ZB2YfZA375g\nBWHRJSLDuy+pUEyTq8jZoZFHXN7uX9th5cbBFjtERzEP1e47KFVu+y2grd0uT/p3aA/Dnc1rAVN3\n0OUl/SCM2fRrCgXsZVeNO9TXtrL2agt1/h3Lf+NdAkcZvn9s+8p2KQQWKc+XZxkefaWM9yc/9fsX\nPY1bSFbAWYgAawdP8Rju5Hw/OWV8Sbv9vq7xEY9BvZleZMYuNtFgj/xGBc+xuvt2uXAyHW8FfkIM\n8cL8AdK9g14QyRhkyT0yYQinZHzS1u8UeYNIafkE9LsetGUZn6zTUy/AAQpdOJF5R9QumyGkPJIG\nDLlbHC3SGKKie2/q6GjryZedQrBwkwtDiAxTW0Qz0ZfWnHQKZUXchgOf2KSxyoc9cL5NvBSM6pDT\nBAvpvpDR9IQrbp1Me+korQHewv8IU/iJGQDmW9irBUgAsfKFL10de5y0FcL4nlC33hPYvgoiE8RU\n7OI7bRcSswtiJb7UhlyHXhX/Qq1xYGb13RquMH7/TEr+w0tdRTXngTK1PlKg/fw+yvbbbz84vm14\n69gZb0aJzCbyTfgznfo6NSyt+Yc89ItF7q9pqhZCgcdoPXmBq3Yy9NMPtoxsUH6kOSfBF8AAXDx9\nadNlsmO5H/J6vjfLVMwnD8RGzKg6O36A/qO8CTAXdFBWJK1mHmV7AHkQWbWjtI+29Y8Cjcm5TMCZ\nVcGqgrTLwebwYR99+75or4EP+AEvUyYflRqH7zmkV397XZfJrtGjYDfVNOaw6Fwwl0BUaCVklg+U\n5ujWXPqT+WCdWww8BHlzRx7C/fcE8QYr6jkhv8ZWaZVWeR7m0BETZyFFtYpPQbknoTrZ5yogazvW\nHlomBpRuB+kPMi3hXD9VvYxmmzlMPKDSqnD8oEc+v2HUEWT0UgCJFxQMm9iGggPf3YHN9D0jFjsl\nmgTwaen8m0tCFvDheznqa5R4IJ6bRUvo2XU9OK9xcgDzQcHU2WgdEott1qQL2QD9Xhj4zN09paCL\nT/tIIUjT3V9B5xBRw1DMZULj460qadkGntA2s4bdSew3xEhDt1THe7ANelYoDzMrlueUPA5ybCN9\nj9ihdm9lEllXxLg3gyWzGmSmuv3HEWoNkOVomnTHzZ3J3QNTFDOMQOkjTsUcMNbO06kf3AfMG0np\nYy1LjpLqweinJgeFCZihIUKgUh+mM5q83dzxHzSQOkbp4qgEnX8XTdz8z9rDrqNF5Lis+cg/r2ky\n1v5mr4jN6tquOWltmsh6mJqtbEflof2B82KIIYqy+oo3T5rJ8j7yS3pspqLojUPsoDdI63Y38pnl\n/hAd0oP2aCtDsnE/pfTIXiWPGhPniqLkuv7cBGBWXYznkXvzGpkOqxyxhWAgwn279Vl4NoWBY9nG\nP+D7yenxJFKzsvPZCtA18L/DbNpESKFNX/zlfxsNo1TD+3r7PZTSdNqrXwlbhXO/m/+5mT+w5GDX\nG0lC5guj/TIRf87wZd8GuzTYgQ1MRFizqy6t3AMudVJ2vnbE2fTM/qu7afzJMvpQ6f4Q2V05ln8/\n7q3U9uBhrpQvPrvVqap3SfhElGbEOS4idqH+lE2LwPXQ3rvBZaWDG/ZqR0WAPWNNl6uprwIj8V9F\n/nbYOcr9WtpeB5Z0NEKE1Wdxf71w7Ne79WOVGcm8UQCtaI9HHu+ky22iO7zNt7mGTopdMTplddm0\nXuIyP7Cf2kKXQqso4w68N66MJgEeKS8ICKONtQ2HfqETdm23OPCItND6bDztQXOM215iJj/463Sd\nYBeMiN1aY1cnhgrab2oVuroETi3DwUIewB0lELB61LHLjpKT1uFQeSRnVjZ44sLqvXljLc7VhQ9O\nkM67M+SRbxF7gdwjNVUCJtaTxVM6Vad93zRoRBBi48nRC4GogHXTVFX+P6PK4lESKZ3QFQVE5E2X\nZJPoqgI8udlaVeBK1CyOphB54UqTOMDo6yXhK3f1Oo0Xb7Z6EvQYSu1ZmiGlj/VxnNju6GIffPbU\noj36vPOyJjH8eHw5Lsq+wMg9hiBym/bv+XrGLRz5gPQOhulovqdHuA3VfuOkQpBXA7ZwWqE0XEHA\nHlX4GYw2s6WZRP35U8njSsTSSEzeHuQwdhGLNBLKiGCMrt1OGn5KvLQhhz3uFmvCvtO0YQgr4gRv\n/vmpo6suAL/ASzgOaEPhiVzMmPkrWYzIBE3QRLskFPR7umUQrpLgsHbonxi24nKArAZlLqvR8zG5\nMJW+VCRb5DvU/3epE0IoFGxaMXInK3yTSqfouU25pcD7UPznWiUd+Z3ZbKcsRUDqqTFSWVEIdDtj\ne1soBVA1ECD1iz6+bTpNY5Oh1fX651YQ9lvHKncJ2+dN9V+hRK0ngC8rt429CK7a2Idalpmi3JWg\nDc+d/z1QrUiknXJdMXdblP5a2mivNqIY+P9N58n+bZLVRKzRPI5fH+TaiZ5jTqJPrlNeN6D2tTa1\ngbHLS1Bq9dYuOLXi9TsbmXBgJBQwwPEWK5yG6KdPu9G2WhBizqyKJONkO+nGznTqzepavVi1EtT2\nDSy2ZlkxvRjUjhs6nkJ8oFotJICNfcBze5Rsg/eui9K9LduHWu4KMEEnfS6sgxuooXB2mSH26zwV\nij9uuzBYnF5pUMZP5ZIHwUnjANwa5J9TVpzTTsyHD+lSA1anl0ixbWrZqBWojDnzT+iwlGIxFd5a\nCr7uEUoz7+tyA+l+rF2lKvvxzfe+zdYMMBvqsNDGdYqNAW9FkmJhCLqy/xwgk+n2wVFwkP5bs5+I\n3CWz708qj0Xl3IUamaiej1IyWbCM3/65rfAs1jw/SeAXlA5GLuL0OQre+5ukvItsHTy5WCsZy25m\nIlzQgA+g35NVaLX8dpPHhdDcFPt1hGXhP7Yr6joKGvJFCTAqQSq1Ept7/OihaNf5XXI4dZlwggzW\n2O6+s9dtuhAiKtqIJ4ijww+apXGJirR6xUAhOeSg0/dL5FZGPXCUkxIV/mjEPUtP8xHtTf+8DOkY\nPWXBtnx2mGH1KZHfCfdcUVSPmQCAIA9DeWX3Q/v0IL1BHCVTaOsQ0i772YTDjXu0N/Va45Up12M2\npPcrdVHbahLP7O39ql/r6SNm08f+RwI7JPRtDX6X7V9G6+hu0iepMxsxBHk/8XaLUie4D6F8Tp66\n6wGBZoUWXHhVYxe1w2xSgRvnaXfLtyfhQlgn8KmHdgk8ibc3u4wSRbVtHfjrajovxVnePPubf0sR\nGGHlwLMSkklmrNGL+lSFGUi1thX7/vm25FpgBAf+b4KILInLLMnv3/NiX04A6G6zgU8xudOjKqA4\nQagbl+lgpX1lp/P67vogTffKrn8q3i1bhVvE/95/IJpHNxGD/YefOIJie6yvd4g4+QI0Msv2w6Cd\nidnVFRjhjKzWFPITgzw+/cK7BbMWwZa8ZVr/R0Ea4sWBVTZPvhPjDIMDuVTtZ/BIXrN3ZvcoZLIt\nuEf9nP+YPyFSF9h0+9M0/nnp9F71JHyX7jYpqOOfRpiL3Nxuokq2bunZore8JzX0eTcdJscbMtrD\nxCeKBmGQnzKQ6UiCUFkKvuf94g0f+IGcEZumf//3NSJuBvPpTbwMJSm+sY9G//ySSjk7pQqkuR8b\nMd1KFK517XUMgD7SMRegkJwaEV+w81z7aG1qIch/hQCgQbYqsyjvh5nQId8PgIl3hj4GB2InI72Y\nUAhpGWuaDLA6TX7OKs162hqSHhiyjirChFnxXjvJ+txbFF2Fcvd8Lle4qgP9HzwonfxA4tbzBytC\nLJ8EbIpgGoQE0uuPrT7LQg5Ul5yacTYpsvgQiEs6/+lSlLDAjEpcyOT1BIsadKqhJF6LUpao/Yqd\n8nYhQPOfQ9M4yxojCmXWRMhypMMDagM5T9sv6qzL6qgJ4635y7SHWV5n1z+x2GMB2W7SBYChf9Cg\naynz2TV6w7UesU0HBZfyRI8NLkyMS7ihpqyH1jAn2v1bX9SC3mKHK1xiPPb7MyxWS2sPaIZTX3dn\nLSFpuj14rJiJBIzNUKOQfgxBQxFfjiC+nqamVkFll9Me0K3Pzx4nWb15saHV2Agy2l4DayCQQSf/\ngFu+g2qlmJp4rljeZnvFcfEJsOYyCCSq72bieaiG+5CDM8FK4XKb+yzUHKzInHArOoYBwfcoqN49\nPkjVl2JDlQyLuLK8pcfOC8FrGunZkBIccptg7+MMvM6q5pSPMdCQzLJdSw9VJocDG6zh3Z5jUJwH\nJq6pFgVUxL4mHQb/BSlbgvs7NHbdBWKz8rrRA4eVc1kv0JgHRrOMv+3zEIoIiDWuTT3t+yN96Iyu\npS+PKCweGUCAk35o3tdplD/UZzdXhXqDMyDWXStqKnsQIolGFL1H7y7QpISzFxs688S5FmO1T2+D\nM5ktv/9S3iEiq/1qs2t/zEaENLUrc7DR/jifXMCRgj63g3PpLxVEDTtL/3O4f3ScoHrkebcb9I7i\nNaMRY216C8UOoH2/Ce4vGbBnHlqnvcEceN9HJrjnPVfBNQgn3cqClEzhriztssglsio529EdYhvp\nAI3zSbuJdREq0mii65Ch+MFopk7xMl0FkZtWXazGh5EG8XUCqTTwL68iZQBJNXNwpWsMwOjvvVMZ\ncvUCwskXIgeBTeVeZn9bFKUZ2F3GnOTZ5jC7ctowLND5yXfbzx9O0liZCTrjtu53iTdFHajEz/b4\nl8p2KTpbmC2CvZInR7lx9ZYk2MP7OjxSovdxxXIwpgMYWg1YKAiEIew1eILGHH9xYot4oEMFno35\nqX/JcF2ps8iJNJ5XQ1YzV7SduBeTCx/Yb2d4VHhNd6lfGJ/VPyBamni0Pp9q2Dj928OQezu1XIGJ\nvaLVosBVp1vLOs0cqntR2L8Ok3H6FZqtFm8mugOIB7ULCucN5ryxyJlP6Mrpe7ya1q8lqOGtAwth\nG/Dy3taw/Yy5HG6TB2aoRw2kQ4Btsq5j++25XkrGXxx5TvMK5qSWyxOU2HSAXZZI0Cn+jichK5fs\nZG/1nqyorqf8a3ei98nqpjNgoHVp13lYVrpLCWjOaECv0Opzj1i6EBPMbhdUBAh9TkIuZZlMVuR3\nRh3hDvelRcMCee0tJn0NB1Wo0yrT1Hnz8diHo+bDuao4G00VU82hBM5EkCU6X58wSPK5Y39d0nUO\nHn4Exdiza1nnBgC5bhX9sWMeuT1jWxW1lo98Wgg9WCuJU11VR+TlEeM+FKOVQRTr1Pz+sZNQxv7G\n5d93rqlCR8T4JnKkrFpEu0vUDzqHKU9hKuIJpFddQkwSB2xvH1Ts23XKgRXCs0PBmPhGZ9fSHQke\n6HQRh6E/R+JlmU00vuzxXNYgXqd9Ima7gLVPBiuGcv2c6w8sz9lOe0reW1OoxgvI4MANQ1k5Qp3c\n8cIsxgheBdrhp5iBVRipALi64MIShWbP5ZPoC0/pKzYVhS1qbqeAYfngLEsaGyl1GbQiAKOpwRlF\nIj8fVr9LS0n286kxnV9KaZo35NiXSH+DeeJHugfPaKqRPArvCi51KSMF8TRpImRrY5g12Q77sDQy\nuaSsxVmQ+gC+MrGhQk+Ferh4zGEzjSHtNC5ofHgArM1c+JvCB4xiTF9PDKwaSAZ1gS7diLNW1Bae\njLSh/zH9yp2jy6upD1uDSCyY4UH6LJchwsOuMFwcaLN+CgxYvly0DIo8bjbzFwfBkFpGByBmPOSw\nX+53dM1x29EpbpVG9DnxzhIEiTGtwhrwJbrLXT43mpBbRKdfi36hOpAPxzwxGmM2XQpL58RRNhcj\n8J3y+kVQZQrtEp/v5MaE00o051ZKzTsCgatNlb1+h7mQ/c7C4QiCOxC33qTJun7RX8BJo39ZrxTW\nYDNppnA5iD22u5ou7Y2jTNRktD7kCCFgu+pWxFz2NCOwx0LWL/xwthI4uWgbfvNB2k/63fFlHEaj\nE/lOWNFbj23yjG4E8gRNJy714aUef4Tuh7kJF8XPER30VGXe3k6uKrLNYFb/CjramGTQtoZqG1Wi\nNtwN4PiXY4YZV/V7DJw5tBEQC+OFyKd8PvCYSCZXox/xteCAfB1CGiTkBdDPfuo95ppWrd5sYro4\n+m/uYlT5oiDyS4hcdq8NZrPRJ7t3f6AEZyKJHp8ZmpqJr35SNV0Axo3GFIGOQMDxaw2HBiCFz8ay\n0cqG5lTZlQoSb2/5YRFNwgAL3XRgaPuzhiWC0+iZX4FfOSVo7pMENSc0SRR1oq9QxE68hWiSkdRE\noq2dpOWG019B4JrlXKNvrLkrMUJ5sH4zilU1RN16NshlO4pE/W+iLCp9yU3tOhdOroeDMEBV5sSX\n88rzfqWGbCdzlLwovLmF6OC4mjmrF4HPSsi+jJqVq2LoTCm4TxIAWNwNYUfKI+KzAGYV2zVKIdc3\ntv0Wqz2HF/Z+mmlP21Pxb9zNw2JAzU912iUJrv85MmEUSXlRqOnV5EpBN8dt2ng82MQtAztJzPj5\nm0wOljbovym9o2s68UWKkcVsW+u/o4fpmLEDu0/z7IJj39E2uS4Bl12w26sC0xzNue9Ykx4+XW3u\niMkZqb9QY/xdNNi+tFcPMQW/CatBNuqFXQfaUvwS0FxSHLkgwa/6tPKdt9Lby8Qc9UIlXM2UpJl/\nNhhYzC0x6EdFGNul7x37AnjCNny4Ub/Ww0R4cX8qod0lRCuYjc9/OQU4C8qBVlWUvWiqPj/h8D8f\nQhCRt8sv1r0iAYpJk3cZpgmuKHxm8jFvDjo5WIz/+22ypyGDYseC1OctClKvmM7/cVdn5VkUnqgn\nJt4FETNQvt7chlPPD1Blrf1lky8HAFkUz5s1KeXaTm0rNu7JE6XR8V3h7Czf5z1eFm5FpaVLnA6i\nl6gkI1Oy031mO6fuF+2UNE0kbZWVL/z2MovoMxd61gsIaH2gjmOgomeRnukJmCRVi68MY3kbsyx7\nAjDUjeD7TumBK+WhBzseB7EYdYrrjC0xNAbW0KTZsa8VJzao26yLPqoVlniszEUaEfmZIu4GUBZX\nvH18+FvNpADgh1KH5fdSuHDiDUnv9oODiC5mrl2wVb904J4khorffh4MJpK0Hyqb15eO2Ca0JtV4\nZjVozV4xm0JoXjRu8uL/nTLuVXTAPNoM3SVKkg1n280oUNhYvCX3i0WN5ylfMuGbNpcN9LJBddp4\n11SqFP1NXhuLwJ5bA0jOtdxqBXbHcdhaeMWFitR3fXFHOvuu8aymkbkfDY0gdRGGti7aSaKU0hMX\nHgwRHUVqc1iR4XykXmb7Q5WfcLF4ooqZtxsSikSNFHzAti/2yk0oMmHKWKyVyVjJdIxz2SwSrPSL\najb0N3knTHQ3MuD1lBFy1po5ELmLCBhy7+rf4itkuo+NQAIac6/zcKBIYoXi1zD23vt5qsgqoE+I\n0Dp90ubxmdHHTmnbPTc4+NNMjNe802tiwRX8CZpAyNkqWZ8oNywJ1SpJTAhL7vDB8KGw10MW2FXs\nnGOuoVn4I66Wj2AWJ7runJR9WAguApiSNyEhtPJ9f/zccN9yj/QteX4ipYXXTXBPY8cAUCzK+kOu\nYX4J5okSHWg7aWiQu8JL7aFCRdxLsadgw2aFgeoz9vX5B0AzCBF7usdHNbf0jEDami6RCH93J/m8\n2OgYYgL8Ej+KCoG6lvUB7OtCjCvIoCrDHKr9U6qbY5BHtKNyZWKLJBRjYgJAXT9v2Nb8RrAlBDkB\nfHRdOhwhcF7TCnh85ucoPzf9Migqgrtr8G8uA/mMezhbEr8QjgZa1i0Plo3+XCsWN7z4bcLKWxvK\nbESWGbRCbDxXRh2vLlXTlrKJrqt7Nf8FtiBJRUl6EPPL4Rba0BmI69JvljAh38P317fIDE4GOtIa\n9mBH4b3fi7i3IjZADl/THipU4HGXDKUo7LVhZ4WWooXNxMBYiHj2F9OO8d51cHckkNvwl4dDHfF0\ngX5x6HZ2Z0euPtHAxIAIvGN3a28eNgs1FbBm4Cj574vBPQ1sPztO3qkYdPps8yHnpZHu8LAKpnjX\n/Uhn45oxLvgkox1/n41E0uciB3IWvFt/eOXl1sE4Op++7BmN26/XUIdbybUof0JAEltx3flou5sP\nXd+BlU/qHvEJ+g7hhcBKwWZ3W/4Ugib2r3wlCRoKzqhT6iG+AvHfkBV08TRK6j9lSio1idWQ88JS\nTHQ+2lESdjCcCVAInngcchEjo53n+PCUerJ9L2ZC1REI8gmQnPT0XkhNUxwEg75EddN7xBVUaSIU\nDErm9gXrJvZQPsIuIkhgQk8i8CZKRfQibb7WYSuhc4dGRTCbAVa5NtFD9MSglM0bKlt17zEKpJEC\nVZllz9DiRMdzE6DzA3RxRnxsyZUYg+Rbqgy67o8VeLTv7GZ0hb168GMPVgLm2aoA+awycuS2nmIu\nBwxSU8jdhryhCanImlvv7n7OM9qDKeFnUHub7j5/vLqo0gUPKbw19DAqLrR/dBm4RiruWwkJL+Vr\nYaDpf63ayaEeAzSnD0cpQHU3ZCLJeBhnfxX0uYGMQNvJLhjZOUAZIKU+q2xLMNBK0s1Oj2SGLJIP\nB9ay9bhEDKNDG+q9tz0jk/lHWt+27PBZ2Orbru1IB6PGvcF7o4IINZ47Y61IJdvNx85lEXBrcA7B\nbbOn6CJjQB+T7JsIxok8+2GENpgNIZb6Bcgqp+lkWXRcSdm4Crhur5On6XLP3Smat8qdnIApPLs9\nbQbuEEgK4iGY0R2XON7EFDqcwpvd9HJfF0doNmYRnby4O5jr4dNWSJcrtpiL1SVKnyGhInFEfQHQ\n+DXG4xim+qZiObzxjxlE91J3P7ns/Z4agRzKnj4Bs8sCFphJUAtf1b8M6ki8+wqxmoorOBQ0TSW2\nfic1JdtlBxtJjj96bMWtzNWxqmdMErlwhYYmgLITsu2NM4iCAfcGKBZf5/2QJAc6KpuJ0YXmAr9P\nQDh8+p7+bfBMOizKNKsdDJpQoKd+BK2c70R8IalyjokLs1SjxebWlA3xdmVEjTqbNeiC6czWFnc8\nMh7lwb3BOc6Ndlx0fLvO1LygzG94HCJEuodp4BDA/XekIbw6e2jXryvJZNncxNOdSAp7NhXD0MTq\nL+eYms7r3dzLqPnTIoOapuMLt9z6pTGSFu4prxt3KfZEY/tg5m2xYjs5S3UTESqK8EGQ4Uh7mj2C\nmeTpL+NnPHN9D6Tcwlf2wKcwzEIoPFOH+KRGp7qU47u00mHtM1w0CJBaprBpNYslLWtgr73bM+TI\netuwVX9xMdE1iIPLtqDKqToNmwqLbTqYbDF7AhnuGCclTOQO7rKzXkiuu2cgkNXs9MDcgBERnrlp\noSmH+1XF5zy5EgDY/aj6bc5p8COX9j8fILa9GWyrAzi1rYG+qiFjYiaUKLyhPeYAdWWmMyh4i84B\nbKvDE01pJCRGteMwcLryJl1FlmrVWZXeKcC8QAzchBBp/Jf37YDds+XbqrZ1m5Ume42Oz+OwaVx9\nQEp0d3b8U+2JSWf7DEIHq8A4CPn0Yz0MR+6IFckEv3n37qebhFORndRzGMZYLwBPz5F+lDjhD1nN\nOBG8YI5McpkZKsODGLCYC3wWWtO9//k/syJXo3iJiTHAkaY3Pk5xdKwb9VUpZc9922a2AA284kJS\nc/w6K1tp0gLU0Mpr0z6sOE2lMiA9auYS/Ut9xt9km5TLfRwtApCrVpLkRpuATTyDkPyjw0zHlluA\nDR8qhNAd0dv12ExG7HMW9hu1wx2tg7gT6DB7czWMjfl0oWfOni5ihNtwEk6CQZd28NjZhRLPtWUH\n+FSLzUGO6SUc7y0gXgUKHWWu6ZLCJjuzVlela+dOL72QeEaZr9W2zZsVyJuHyVD52aVnwTT3AOFK\nn35NMxcXw8wKd2P5UJy7K9ud/l3TB787S29ZjoA3P2PfHD3O3ogtqpAvHFKHvQH6FCjFAhfTNKsk\nHErVZ+LMGHXIHVT6Z+l/KcDRafI2MULITYDczj4T/XSoW77h0fPEHYqOvITz9/+t1jS4SF/xhMpy\nCJ+vM1OJD717OQYw3I8AuWVAKbEFDmdfhO2gYi1hMuJLe7msDDDJmugXMUoF9mrZsfZexfV9i3oi\n23Wes31mp6gUDeJmUnRxu8vnEXLXkiWl/9u8IHC7E2XwWrRrQjWJ0kfamR8dvKkDDNULew+4K2sT\n56U8REcr3Q7WZl30N9S69uRhCs6IfmjziRSl+vlcdn4FfriLuiXy7muqlQV0Clg60PupqJcebXH6\nBUv3N+vgcEBJNag9MeJroiptA5SBkyIwauhthJkNyG9cjMvY+Y0bNjtsLtZs343tIffMIGKFux57\ntQPtlA+1zsQMMx1GkhXVLeWNpNUusFkTpgwJDoQLEOEi8Zp614efkCcYVhmJGzjWSCqabm/Gw1Nj\nJ4Ik0tMKnueBJdhaSEWWsyIg7gzCo6ojbJ/1WK3XZUo8cSbAmj3NpQ8f3K6RGgsE+d42pR/T303c\n/Z3Uhu2BKb+FQ6s9dIHtFotmPfqktj7KhthqO8zqlyNKxItDaisn3SMELHmsayGM/owrpF7nv40K\ne3ed0W7e4bQB4884HK+HliaLERfHqfd6sojXuwMehsBRnJoO8m8q7ahZ6s1LsWkB+Zksnu71S2zV\nHiUZFid7GiuHHiBUQ7Qd/vPMsMJp5bVtz9D4AP3I3dU61RrSKIdqL+KD0OMmiKLD1s9vfq/Lggi8\nyDYOXnEaPvoLPpgMT75wyaLD6A0hux7nQa5XkbPzjFu1KSD8ZwP3SxVWbxj4j/8Tzh4FywINBztF\nn2rzHSaTZJ//RC8teqLSj6JWF8TEBft6NrAKWOnkEeiJ1bjapFbu+Xyc0moJisEfKi0XSUhqo0ZJ\nvo+Nkd9+TnyKNuD7VUbg4gMLsUjs7mfxUIZOcoNkcwrH0C/4n6c2WEoFq4cd7OfYh/pSCxWV4n3x\nxbmPFKTRbHeiuvL8dbAskiR1ebL4RRpvWaeM+4p55Hnr3ivCoL+t3xpR0JDvaq6dyUHXNbah57hJ\nhOWl8WUzGzQ3liqx1NFx5loduc/et/E44cmgxsaUGPrg9EcyCZ3LnhBMH7HJyYsqKWSnevkH3XS0\ndlQkPwd9HJJ6GwvDI5twDfDft49yqpn1LCdAWzFgtEquhfGIISyZRrOYzqkfKkXNSoavO7FzqJ5u\nPXRF4tJdvSlIrbdeRCN/Ru3p5rSBg0ipHtF+YdGXE++Vo0KAvLwFCBynpEUwYwLmFI6ab/wmzDEt\nPfJGznXMlE77hq2SQW8HU0lyYvPYMGpxZxfiyPJaal63xXG4+I5HTlYhvbYcEtXEwlFDuFMuGhzR\ncryuABzlVKTwMFcuBnLV1j4SaflPSwDiIrvcgc59ZFXh1InS6sDvwvBNCyqeuySJLzlUVZ6wuFcI\nrvDc/zMvFRimVCFvYsAlNyuXRDoaH6xbrVJ3rp3Kn2O1IXDh1yB/RKT/G+2HcP5rvHJL3ELRbZuJ\nieInGchMdkenMJGUy1maicvl8bwhYOb6T7q++1RqjyDOc6kG+bGxCEwGjwsHMylLReYe7fA/tld7\nZlOvMXTPD8Wr+YnIJQbNBu3wT0m06a3nMCX0Tf8mPMOQeujDiCxxBKUNU1Z4gUkdM956Frg/AqGE\nK1yAtEJgrP+R7Z4492iBt89YoCfexnBVxaWIsHhy5oy0Gbec+N1pXPvIGK4yaaLUKLn39KYX9oT/\n2kRr5m+fbiSVE6RvSRlihIvzTM0ELxW661/yQWQ3SEB3IV98hF+50e6Qofx7DMLs4a3pNNPMBuGL\nD5lgohDSC8CNH4nLId9yG7gsqxXylVWLKrFltKhvWIIe3Uhb8JG/qQ3posjDegfujtrmpc2W7H7s\n/FvHykVCTUfdYwybgi6uam7nskMH0JWOGeQi/ReIQgbyqGEJ0skd5h+AUDHmwcIYx1j0JtWGV0A0\nmb646def0eNaz5NXkKFscfG/zjwX5yi8+knp6y1K5DqQ5gSM7PFvWO3gc6BzW3QOKRZhwHI1FAaM\n+HHPxvSNMHyntRLaEXef+qV3vRUoAgVTQpadvT8Er6GaRMyVtoPUBLaJ0l+r9Ab+DDx4oAJBQdAy\nhSmfEmWKxdh4jCVEvLIg9RKw/nMZ3g17ElSkyV8JmptZ64i3nwISnFKTqAdaEwoCIDxWLYgXRH7B\nmkzrk8wzEG3zU6gr3RRW3zcpdTqWXJhVVzF20I1vgVqvlb2OMs/D7r+JqyCs71YVHigTOhc5oAdq\nmB/cZ1HOdX0H/45grCiX/WF2SxeJFBUjBzLF+vzOpruChX4Z29SXujo5mumzxkGUkz7ODmqPVbvC\n/qs/p+SVyywnPtg+ST+2NfP6Qm/GvOpc8DTE0mxKNlsTsE2Zo/Q1esOj6yRa8GAagmaAlfvxdIr2\nqQ9GRxzMW6WmYX4OtS7LZcUTygKZ66tKmEmiDT4ysvYlpXwj8Z/+7P8/gKISQYgRttmULOT71oQX\nRIUxl8biceYAQqmhuFWA7+c814MC6h/TQDmQFXE+5lRQlFFNLJeTOxxA7v0x8aDRxs+dw+Ws4CJn\nnF7tPsB7rCl7FNdzKPRG5Inlc8b76YKnLHN8PmDIMofpVmGH3vxbUJPmvoa/Gp1iSAyeqyO6DPMn\nOBEifX39xJdcDRc2HCFkh/OhEXGomdtpu6jtlaldzyxjjq01Hl/LKo7Vo6FklHLsOoo91ViQYEDT\n3jMHPVxSWXXHW5tgH/Ur7RTFxAUGJYfsw5ZHWqXl7hi7MBszl5Q4Zgmw0BwZZbrjBYrMT9ih+TJG\nCIa45gtEJLuoelht5168UiFEo8HXwEak1mCn0NqAnOG07YO0yiFxOR3N5XjH66iljxcI0/oM11ja\nM3jpJT7sIjDAPnJ8HpEkp0YHyPFnokJuWDEvv7j+tcQ85BcAWasVgN2xwJ8c3kOevuPpg3LLjegb\nwedODw9VxVyFUytIpddFyi+Ek3Ef/Q4EszVXZ7wSrZdqVFjVI+PEMaOw3lVur0LxFWsyTaf+WtVp\noCkznzxdoBsTSh1m2znlZ8iufzwiVZ+2k2zaKw8CGe1kw1Iuhi7V5LCdWRDup+eGBrG/MzqR97hh\nFj1+K6JVm8AdT5y3K/iCHnHdmkrAJe7LAjTKAVM2Ckd7mP7mFisLqir41jGxjs12Roi28k6szUau\nbxE4s4wOUxEE+PdrvL4sCjamvasmS24xaw2+sy3UAJ2/HTHf7Yg2SnRGvXrOx/Y3cHbhGP+aDgEb\nKktD+hEx5ivKUWMjX0ekgNUtkg8rP6tFM1HT5rnQe4RKQs13OgvkBF3dWaXWzCRx+xYycevTNusq\nzV/PH1N3W2ZPjrNNtNqwzM5yWOftRUiKNzr2HNyW2KeceGx8l0O4hG2A5kUOSsT2g3GUHVLNl5NG\nNXshenvVTyNS1iwSJzE1mXaMxcWI8xX2ZFXCTTsSKPD3z+Vdgaema+3tVmX9SsUAG+55jgwM3MZn\nntgcXr8wwDDm9/62v4asp+IvfpDb87r7YPj3AwI5u1Q2vWBBPaGRYLUe1YL+KjVMZkTz7yC14/kg\nKUcmXoJMX6E0hYYJbvsr/GxHEmoe0yXgyplmD8z8VHHRqULysYtJX+BomMvdqMSiXMrC1ftqP6Xf\n5lJLt3R1NupQCDd2yg1r0GVoif5x1Cg4O6/MztO0ot4PH13EP+8JhVoVyIzvLTsaG3LpYiI/E04w\ntvtok0m6B1GB1IKYOdn5UhTnnOeDSF8yqSsJdT5+W2nf0Mw4/nPefv5Fi3tEWiKG6MzYu5gAKqyX\nYsM94IBtU4+PjmNVbFDMQqspJboqD93At71pujtI9Yyr4NGe2U7LWqH5DJFqSuDwmUOpkT9NtzIX\n6Ykdg9VGhqU0BpnhvO9mlizoE4kkFRju4BfRyAmukFgTSb32zFRJsA0LLfSyOVbAZk4QIQYIBNOK\n1itbIDXymGcwdFMDHIxFkuj4VBJ6Mquw0sDqF7vVqSSqeARjBK8VEv4fJhammre0ZyavBbU737X5\nUfQ7aLfv/6SCeMYcZYfIVI7uxuSh2yqrF3veYKZiiNavx8Ve7Y8xap/jMfza9JtAtLOt6vgnUjK2\nY0tIRKdGEigJRkc3RXVQgavCbuILff4hg3SLaZVnBhGWAWV2CBTT/gWgjyw/DI0QBukw2P0qTy4v\n0eO8+qeDpwkbzPkDEvV6wrlJwA+bxlDBBxmCgkD6jX3Wl3LXyRqU8D1AYPbJk8/Ai7kKu1dHAi5H\nvZZ1NNIHI4dRuS3IlHtfzaYGr/2+JmvsjNrtVA3Rtq1x9MsHAwTIOE6+2RYZJY/qKW/AhkByIA2q\nzSh1zpWYmq77b6nx/aONic35PMRSW2JCMY+T5HLVhjQqh7tW5eSGPem7IlKhn9sJgRafYJhjbHjC\nkENxS2TGESqOUIw/w5o3d6DnInjBwcCnoF5tM7l0/rhqkxV1NH4tnNEyw1Ga8uaXKvHynOVE6lKT\nsMPfCAlPSfWGZy+Fx8ztjrXqQBm2eIWzC1+5ctxF8z2ITBViDt6othitax+2/VuHm5nRlwdzHjzQ\nshIj1OgtYd2GkFvojf5/hG79QUoRnxDCmRksNc51B9l2OiMNEntpIzx+oPfke9ZOIK0ixFNJU8BO\nt2dd50MFHemU1q+yhgyeJLhcJk4NSlqx6qm4CDxjG+6WFkPQPPX+Xw1HshenS4V4k2yyFz0nzU6i\ntLO75/btg2GsAQMENk4e3YRZ8Nb/EBQo2cOba80ASIzOzxpVXq8pPqJX/hSMy/djXARzfibMu4Hn\n8m7Iu1/RBZf/X/W7tjv2NcyIWgMy8q0FsJN/i9YtagiuR1ZohjiKb0xkZwkfeVJmUXuCiyB+nubx\nwaT1LAYKlobs+U4ROsQNwY14dQKQ379GafZR1NtJfj5NMMXRZl6TOFaZBsxe9Kbh3Do3udKVzs2D\ni32A4mW8HUwROMXLUXpyMzn9X0rXvM7Ef9Ld0xY61wew9Rrxwei8YVlJgaXytu1d0ZPkJZR23Xvw\ny9Iw/ZIWOgvvmnzyitpH+oJ7hjltq4AF3QBBQI6Of5yvm2EwRCGqLxspPgxuO6U2+3yltWBjfnn1\npXTYyTSBLHdoWoP2orkWjwFfKgBMnimJMfhp6BsdcCa+1oQncshZZk5HtNvUHFcaTcBEG/1PE3yv\nFwH2oCdQ7DNsD8ITEoKwUUZXaZcDvEYju4c3FpKZMpUImMJBTjgTLhAJkoh2ZalfJHLf3IbNLmCt\nuDQhwJni81iJA3bKwWcauwNnhTTTkGz0BJnx8pgM/ttQKz1J+s4zap3Nji/DMKWT4bP4GCYt2zD6\nyIY8h9iyhL3bgmYfmFAJ5z6FgbJcWiN5//p95xzkoKaAmWq8bB/qHQKFcPEN3qsWcFmZg2v+lUql\n5c4sT5GQBsZOIaN6hLXcbuBPNUskEmv6opS2zLWsq8n0CAbB8kzlR853B73iImgYV2YeP69BCO8T\nHtlm57drDF7XvirIQTInsyLhQ49a5O3WPn2NYe9pK6sYyiclFE3efqqAs9oCOgmNf49Rk3erhrHm\nXoGcLrwaPpjYfKiDo2jw2BFgabsKfzj8dliDIyS0e+rrT60k/ZntazsdMOPTx8kzLROY0LUXtMu6\ntlXdWX5uxiDe3mk+UlYVmTu56F2SvQ47HAFj4BWEZ4q9MGTKtmt4BIOr3uongvsWnzQRp14uF/yQ\nsEIDOmaaIMg/W4x9FyttQNgQaFRJ8b9B08otcQLH2oZ9wqjZoF5mkuQx8AG4UbTOVvfe2yj3/kOC\nVK/OfyaiJLTL4Bk2StaF6VB6dz6ZE5fMRxXmPvqpGWjv7zDnNvXXpkllH+cuixrr0OmDO4I0Vm39\n23TIhJUPJt+8b+ODtseo3On3NV1tnoKcObkmRzFAQcwz8xSP2O/+Awqeou4aiU2FQL9joaZcqCMG\nafhZz37qUv3Bt446BoTiB4QGz/LOcEyXolSKV+IfDTZzJl7toGQZ7Aqg4wohPKoZuyQnfybaoCYL\noXLdIad2k18KpeEV/Qh5XI61PN6P2Zi31UWvQf73Df5yGbU6QJGOqjdDQqrEEWhF0Z3FMBQgmOLP\ntGi24v1xAMr8t3YtF6mSME9WboB+blOMgVZqx9tdaxxEMj6CAFR7QHiRldIPM9dz3FHcUjCaUN7m\nCg4aMaceWlW9RKackBQlqVfVIC3MMGKu9dJPSHa4Cs1e60hKD5QidTWc3OwxRXdPbzDOROIl9Ly3\nAnK8u8it5J2SKrFvh/AtF7RONh7hX6Yv0OMbQZEYdQRphuNG+/5joFAN0FViCo28VvzRn+U32gsz\nJFjvG7CBccUtF3/SzJTOCRmeal6KSYDWjrC8xT5nVfEN8ik8dDRdvEFlwENhEa4FI+JxEMuYzpbq\n48k4OvNbdsz9YcLSrhiMu+fpC3iC6wn0AcEsVFSewyI357cK0IH4De2iLHmwnC+kOrdMiYOkhEVc\noue7YWGmUDNCEvhGo1VDX9ov6rx/50pAF5ugzOd0600+P9OZQb61XCZNKaN2cRegZKbtthLaSwjM\n3dg8IRMt+J2u/TUzvT/0O/LcCGRtefIi37fdhEqwA8HXy5FQ3xL99QR7Pecn0mCyjEzQy/v0oa5o\n/L/fOZPvIyI+0r8gmjx84THuroakqvrOGC2y+O6RMkcrXBVv6H2yybbv8yWEWIni7nRisZ8JxteS\nxJx58CGqxX/JkjXmFoHwDXjjdv2yKlFzB5HMS7FNMmtBWwS+oSRVtglPJdMpU9u7F9BRqrtwpZK7\ngo781YZSBIV85g1zZFf4t96jZpfUkd0isrYhnPeozon4+fC7m+NFNs58DXo0NSSbORMjgVNyZIKB\nvD1MXkJULySUvu8QqvrHYlVS+TZCj5tSlt8IVcDuLnJu5sa6p6l9Ad/XlY8qzx5hHR+AxxguC+fV\nlZfw2KoXDd0ZfB2qbtbTtXTRrMbEL1xpX8rtksswuHMnGq5juDh7Cpd9nridkZPEiOauzKxsRRI7\nCVB8jfp+2vI0SjvSffxhG3T+/vmlp725nViP4B9tEdwoMtpgd81dIFSk2rpwdVVlayNE+IpqftzH\nEiB9gaK4fEd4+Fdv+177Xs9wg5T1xLxhk1rJKrnRQ/ob7E3PVHjRnZqbTn1lN4m1OE9tM1tEA2+2\nkcETTxPY8wLo3islGIiY1ixpRjeEQq105WXt3NAEOen9pxBSziJ7znplh3Bv5Jhfd4LE+DH+62Q8\nUri2paOD3ASb5LpWvWlIBO1X0c0/GE9yYkw3UT0R90UCvMSQeybhF6LpbIvS7Mj2N7UIDNktDlWg\neoIj8XOGvhC7rulio9/jhvdoMMXW/BGwffJ3bvW6F1j8ofBgnNLf/sD2+CBwmShcJnktV917PB/c\nGkwpiHYwifvb5QsxDC+USJ/6bS618fIluvgemawe96FOvHXuOeQBO+5AAQJFrv6MOETHaBLyxkZZ\nhdFiSwbWgyJC3tTQthStNYQ2Ijqcq8pTeVjc97GyA0FKJAmWDs738KR7ADaCIAkqHkAD0h1MUnR9\n+FbDRNd3OFbCyEZHJivq2ZprIyi9jlHy0wWhXcjpZQ8ol+UEjQTNjbOG3zpMQoUn113I+jr0Gc1S\nTM87ulMhgtzr3TJ7yKkiezPUaUsGLNkJulnKZEben0CeifLkqxfqUkHJ6keOY4liCtxP6/5Q4+wO\nHtduaKRT0bd1vD7Qqm81MA8B09mkDjn2wISomez3owX/JtP3v30LM4K7C7FcjQbHPR49D28EA3BC\nSofi9nkwue+1K/ld8/Bp4ztCQAyHBZlPEpXaZletvBOXNKVHythVgvrTcQbHjUFtOP+9sgM5eL9/\n9xE8khHPex2eMJlYRYEKPrB+RnCR4F3kLYhSx6no4JF1QZ244aj1NXW1NJE92tzOUv7oXvUSAjtI\n5NlBtojAsBX6hxmiiWktePYzERylLrS2omlaxpcwptQEhEMmJS5IfIZJwAgRbCUmX9p98mOqg8+w\n9ktHLbqhVXGf/VbQ55MtRysucuCbFGSbHRdwch7bzJxArfGyxSrFYvM0x/RcGuQ0IweJsY3RdyHg\nFaDJUVNOuZh7yQ10Tca8Y6CzPWA33cBrzqe+DtCn4xWfVmsJwH+RCrljc/+kmStNrPqdFIscSq8W\nz53TCfMW+/r5emiCGSivPAgEUkmqO9Yr1zvHlr4ACSLSHIij6m0KFFoY8KgTPji0vV0i9UwEVr4s\nndgKGEl6X3JoHup/pIDAlbDW9qpn9zCldTtqMDkpCIFNn5Jzz/C+aKzLPDkhkHANF6WBWgl+k9ng\nJfyDERt6EgaSw3jvDjEUGBLWY+Osf4EUumh1zolZ2WxfKIZJ+LGMlk45NeP2yNtb8eKIHUjfhDuB\nAAL78ilWKyuNeSNEneeEKkJkkrDlWGL91FhvkgJiOVKmhuk1imMe2W9Vq4nf6LmSA4Gd4x1eAQ93\n/HhGxwyqJXiSTYoajr1ECwWCZpGCDCtKnhZbEaeklNh7KnPZip/UiId4U+Ll5eG6X4anovlPAZRX\nuN+BRI3VL/HAyrXrkIeFc8Az6/0y9X31vvZlo/cVSWP3PJd5xmelp/FdD2tmUCBh3HE1kI8w4tk6\nKnk0Sl4a/xLXX41mvrJcZt7UGip9fNfOxSoshDLNQSHY0ZZWzwK2M5r2OOE7lqrYEFek3r/sw8Ig\n4bo2+VUUYk8DiEfP0Ug4bKeS+tJk0D/h8nP81R8rz5pIjiZIvTPW4qaL3xxzLNIkjNMWKnHCVA8S\nqz3F6rOVLcRxizrNh/gKRNTTobKB2QU5le5EpNTqZi3brLiIFrb6j1WgRqrKaW0w+E1Hv5dqUmAC\ndygR5dP+BcwYOAoEb0AIQ1Leig19elwk9eQqk6CHHnHoizGmpwM6wWTvuBscCYGynFSduqniI3cD\nX3Ychq+IdmsbN4Eia09nMLa9XT/fgQ2NhHqmr0hhfHAAGsCIm3EL3SIrO37rLXaM9Tj32a9sE8Sd\no131hv5Jqnl38gB2e7gywOI4s66Yj3/gijchJUOUus4vPZ014cQOnwc3d24pRu/LE+c0Gd2h7b8h\nYiLxYPzxUKLOhOcV0ng/k0dVwgwZX/qtCqLJjIPMWZoKBl9XSg7obLru+lEBnUz6UDcynE0yRAn3\nJ1oHW6CHnGACh2ZHMRkcnR+yyiJOaiTDBYoNhUjJTvuC9JF3wK3mMHo4s+QUKIeVuxN7/7EW2ExH\npSKwlBwWgU7D1glsfu2gNUr9AXa37/5Xj4crYCm4d00LBssDXNw8lTV+za2l/ga0t2pEglG7Iq0z\nV8osC9aVgapXhnBeagIeBGgY/8HedP/j5bUcRcrbCXoYqWLDJf4IwwoigyBL7TQhE1qG6V6O21dk\nbeYFLG7kIXwkr5uJTFy93OwTLh5V871nGPNaVaGP0DdMNkTmOlBt5beUabdqElBWxvILKqOr0ynf\ndBqxFbUpSHTxH7beZxZQfgNPu/M4V1A8KY7L/t+HT91HxIP5QKzr9xxkPH9LclB7bfJLIagBQPDS\nkggrpbBnJjtJUcWyEf++hLMI6rdTXlYXw2Rv098jxz8PBtS8/0WtAesiXUQ5llqkMq6BJh//cbCL\nsq0efXDLyFcJtW6TpSy5YyY7aNVkjKzLNavaN+mANVospWckzBwgT1QPt2olmFsuj7JFeK4Zj/B2\n6F4jxR30unHQ4lDf3ga/HCQSpuL4mJrfNyzlEK7F5fmH+/s8UlJGK+DM4CkXv7Q0f237spoSn0dt\n/TI2zupItZoXFpvO3flbGJYpheAA5zhlAnTD95j6twP6V+5BOzZA4RYKW471/7y+851slUNQaqXQ\nCIp9B7OxFjblSZpJV/weOapzR9GGu2WUL34MtsBCFeaQzFx2MLNzu9aSthoU/PyiFjk6Lj/wLaN5\n+zyh95016WymScCXr3F2EFVrj7LC/FwmkAEIDVDNwfPJ9mpoiZ1919PXirdGiVkPuOHPEcMapDO3\nsnb1NVvSkj2CnbbZThL0GPImnc/t3exEY5SXPx6ybzj6T94UQ27BvPByC7kBOD49wmuyviRXcl2F\nIdqUOSbxaaiH5egftzelDJOX1vzyR0YubGDtY5qv0Umxu0Omqb2Xt9TMZdYumooKtV83gZxHVpXK\n99GAZz7+qyLJ9F/AWEycCeWMqgBIE9erlLg/tn0sN6avwR2/nrSFNLc/EC+/bGOUqJNj8z7IBPGB\nfQ8zYY6PrRwjmqPZWK1+Jv0AUJSyUZhJmQcLbZ3Z+Vf4gcrML1Zn+OIEWcvmRV0uMBfgANh4GoHQ\nooR+sgjc3g+XA513j45GTEqX0J38oIjuuejri0o0s1qV3aX1ZDPVFs+iQT5SOlBgaFzniZFnVR+W\nCJMWoFnfp3lRaIAae8dptvQ+z1lb6WbF8E00LnfutS8fEYN5BAvFUShschcve0aNbO2Fd9ZwKNou\neIUdlpNR1xw2YRi6sS0bsxHkj3w9dAhof4Ive4XDr+wdEZR1dcMdReAFmPe4r9M8fAC8TcD+ziCs\ndAyyiXjiTseYpE/SqL45QNnUX8wU1SY7Wkmbj7qB2lFEudgCsl5DvKwNnwf7NPmKtQp4fUAIqbUY\nWawf6h6LleeFJFFbANP6KS4s18rl9e7q45eRXFkkz0xtSYnNtMIqRatPqfLqaYYHtQVlgdJCV+XT\nyxBrVvKWjtS9dGambh+xqG8anwDRaBsvtYTPFjz4EK96d1dxSwc0cs0RZjzQWzJQX2MZkmVDrH9b\n1IzsV9C4oh7jpnOIXc0TE6wi4z5ZmWJDp0R92M51XM+2/JLAjTcmyXbZC1ZjT0uYJasHG64Y0rh3\nsJwZADr6qIUiYINbRVOTY6U3f/Ef+mLQdp3FT/uIg8zZJ1i5GPCy+N2QtXSl6CYryLARFRB36LaG\nUyv0AzNpTVkQ87Y6bjQKXk9PD6vN5epC6J1JmAnmvqK+MlsOBAhm+9pDIdTq6WOAyNFNsuYuo8Xl\nBx3fvu1Zxq2tumbbRaA/i8EDFX/m6ykEO4mFNU3Pl8AV8tn3F3Lf7D44Kmyyml4G5sW/9BgPRbh7\nThxIO5EGz5VFq06zFacwQLo4pLhRBzWLoz+UTHQ44EPlr+3tHCGLVCTWNIge/jchsyFhcIyREanS\ncZ+zNPVhYNTHufWAbKLcDfc0yvqikPWjy3YzXgrbodebfAP/eirsaBJZu8NCQijcbn7MqRiLl6L2\nRteTEVsUyGhODDCfc8VHTiB+ghs3tvTA7+Lc+AIh3t3hNDVH/PH8akeoG7vA3ygHGO0tq0aWP7bp\nduwFCxjfG5L5NaGxRRvUuxDAMgYGInp+NK1+q4jQalIyOLj0kbP//qXFTUaZ9n7Bg7Dp0ujKcqcg\nWv9m/ambWSMtb4uOOcUJT+ifnHmxRO/bOGJGWJ2XPiFn1EtK/ZpyFaBZE9p1wmm8hONEAyILZwU0\nInke7A1LhPXZtTe9ocL6HpV3CZ1XPdIQ5s+iZvjkez1lXN8t1Z2v5BX6rJ7LgqcOR9e7MIgeqr/z\nexY5taAnpUhmG2oIWpNjxhZkKyZkhjpoJu3Fk8j7rVo8jphKtq44KyhtWEk8kL9N2jjzoT7uolgH\n+JObgjkLvRGUcdvWzfL5ag53dRhXyYZsMcON0z9wJmh52pt4CN579yQnbOpGxqSGRmxZmyhFdqeV\nl/p3Gik+8kOPQ+gyvucYfwVhItuwMC06eQ8nuLiG1OJXO76XLRQvEutgU89ZUaZERvWyx0GamYV0\n8nHuCgqCu6IcTwqlQLhrmqM9wsjF/D0T6x4EENrezJNhCMo/69srqn9pE3e5QhPeu3yH3aeqQ/Y/\npYaMArkanCFNUV7TlOHYcqWP61nPzKuVcbmxrpXHTHLQ+KObmfOe5D03iRRGxRl3Aoabr4MUXLSV\nmAWsk9JbnNnBa3oBDusnLinaCrewLFqWjnSmsB3QZGVyxEZGV5ppLDHayV5+Ojy3YVHSdq/o5rfX\nELHj6S4K1KuTvOKug2G9AO6DdldTXD889WyZyJA9I2rl8oOLobw34Z6lr3RqTqZVxeN3/qkMTmVN\ncH8yYWfz4Eejs05L2KjwOOMy7+WWVSDz2SY2Yt+hvoZhaSYkwWipjl7C9s2jMkePlTYRFsCuG4bH\nT46WPqptd9DjIKj0G6IV8Nb3EOVRMCou2kHyEsnHxaK4LjC1yHDP7GRoy8wGHf+03rV02t3T7ZQu\n8KXrObaY6+U7BMIMpvjEmouWQBSg/TeMV8gYzzjMBCr1CjU9VixPiJ23jAUZ6PC84twcOwrPjtBJ\n9Ps9St5u2HpCF0R+dQEiukM0q+ig6+ZfxnqtctaveuLes9pQh6VoD6n7YWGkwVhJWn7Zcl4Xrvof\nb2EestQavqVV94EqwxZw+J2l0wwyjStduogZ5nR465etBuSmPyqpBEzFnv9m/EnvbV2KYdmUy+Hk\nZn37bG2q5a9Lf2SCz2kDknkESUlUo42vrqlIJ8ZljplfrHZvylAgNE5Dp2l3vqamjiMsGkmp5QX+\nc0nbzSWouRIuzsoB5gO1vkmZgajbNKZNkOTjXn/02QayhahheTOXQQ34eA50nuUFBIKcVSk9VdjT\nxBKiCfJnXl9rbX5mY5DOCXxQzH2XNyq7O1f8EUA4tXtYRpGUQc3tHWdqhQpvQblU1PsKFkGT9qCi\nJhg0kt/bLsRiOrKIF+nFMGNFLXYB9pf2+d97R31NRe+r/4AYED4d8y6GIOCqaplPjN2GFmdJmXNx\npDg/PfS5R2trl040plZ65yP75D7vqwV8RYw4R74OX/KMt5rkub4heCpsFWaFwLmPfDax9NiA7uMR\no5AZrTNt67CmOlYKYKFsxPfJx39EDQdqIoPHwZsaNCREcbF8UnO/uuf/stoAIMMKzOYU7Tq7wk1g\naoYuHsh1zOsPq9M1dsoLQQvrIVT6mcslB6L/Ya5HfoO9xLwShFQJlDn2BFP2bk2ZiDwWPksJ5AWQ\nxPyXvs5gEI7K5D4VUc/r8JRWeTKahIZC2A5uQ2l8VPpWfYQm4fXmMOatljtRnW/jUxjHT9oBNKkD\nqVxOF7InA9LrqEPIf6W9F26Jn9Je3Kj61enEkQT7N8C0eR5BO98mUBZsaTHA9eO+mZ0zY6yBHH9w\nIZIhemVTpxVzfFmz+eyY+2xzs1QnCrg45RzeEvUu0GuLNpkx3xg2F8iVk3kuhkgVZaYDYxRQML2q\nB5GxzJuw/4Po04A+WUBVanjXT9cSSB/HkPXdN4eynZIYzpLITcBi9mrSDMoFtv+a9I3cl+O8DdCa\nqYUWNoqWg0JsUYcTLCtR/Cwpe+rhdBoyr1qV7Pb+2kMYHZ4CPYgQqlXzIpsustkAlJjiy+wK/vBl\nfzqHsdM+VGJuL/5Pvx9Z+hmpNZ+/09z+Gl4n3Souu+Zna3gXbBPm9hTEjkEAHqWRmKIC/tcpnWu/\n9m6eym927TklGXpNh2gKnbXQMxUcNaVdt/EyYOGaE/X0Pp6E21GZDj08HgjvlSRZekC2FFww9ZSL\nFhZmCjWUr77qriZfhmaMYo38mtWIC307XLh+385Y/ByGaQkEbR//qCjLSMJSAOi23zGlfD9alyS7\nyzSbI+R1nKYqR0pUJVAv7NnRxVW6IusZ1SyRxgGDUOz2nxVk6QmOQBg4pn4OK1/hkWkCdalkr5VO\nle3IXYWZBupCe/B81dhLl66IemjID2jk4M0Fob/2a3FPpbeoiBIU/la0Ykmi6d0I9RMhyKhDo1NW\nH0kHSRxDD65uGyhx2iasDN+oCCmTMcVoJoAB8ihQBapgDRQKkiJgykvor0GVGVlJHThFcc5sOknu\nEcHXIM5pDSiYilxbV1hOiZFRi0zfKN2C81oXkcJh69IWA7MEPvKhP9XzewiVgwyw9bE2DTr+vqKJ\nGpKPhaSYb2PCf/xMOkKw/2IxZy0DvldZQIz/H42mRGnxqK6GJOcbc59J/CcZ9wicZ0vlX3dvdCSm\nG/tCgWlIuQo2mBqDLEoEyrSrg29yjYYQ9PEgRsJIeh2C2wK15n5uJ63tt5OWr5DLFThm3fkQbXgA\nXzkGaTJGsD5Gs2Tx+fBfn6UyTOK1IVwPAN2zlwML3qEovVHmxCxxqtRzmdIHf7GFU+QS3eF5ypJb\n0Wkqgu0lYdjYtGF1HqJZ/w8g4N2UtppxgUKvgsuArP0ddOyJnm6Orag0C+mU1jVJOTLJsZK9rrwa\nVqnj/xAt03OsMP7FfJJHDWN1iM0JjKx5TLVesJsyMHgC3fgIwfs1WJzkf+Jfi9zmVIQRRq4r8iWC\ndIy7DQ0oHJAiYGNlibIGm0pzBxeWw4gNavG4UxYrnq+stF1WW1gQ/LowmenwG0Cjy8d+i8DiU2tx\nqE5kkIRLYskE4J6IlQRKWkbBdjunTe0d0Y/x9vFKR5vbTOuUbFIiw4mrAwCCuC2x2SudYBNzDkAb\n9mqrAKsiJW2MMW3oV8nAwZmWBbAr8VjbeR8fRgoB65KNf98+GVk5xezWu6x/lnr0CSqNhgP8Aa5w\nQB+C8B3rl00CAv4LtcFA1OSpH9mVbGJT9jlNU34s6OS66nmJrHTsunWjWwfVT/YtIc070EwUHhu3\nkerJEV9OAsm2mblaCWXdeH3oJzAWOt/S+oMvNdV2qbdpyyJLWi9I1SxLtlFBqPLUdAhPAkz1jsLo\n2NRCg8YRSi+yN+uNbNtBQocjb7uBxCeT29n3ml3LzabvmlOf6To0cuq0SNOzxR9EqwHpiruBbcoa\nMBc77aBf1a+9UX28gIncucc0fWsN1jEkEXvx5chO+sTft3RXfVehJrpbpg1g8/SV/s0KS9NxY3GR\n+TNV9hAIdzH2xpxdAZA8rSqKcNG8BWa97giCGGom7uEEC7G7iZs06soDK+AxQRAJ+WmZZyXjdefk\nS0xqti/2PLgu3RiskjNwJldrE1I0uHPnCXTr+d7iBEMi6hjRTrVY0V1THygB5Wz3ABeLA5eOOzeQ\n8Vi5uyjlKB93QlFWHH3lYO+j7VPFOcfCLG9spKytNXO+3ZMuZYAEh/nurWu4ElE3s+omZ4Ov2r46\nEPwYJkVSjk2kGvj25OW3am+nVgLQqyod3R4eeO+slIxDIlI+vEyjLr2vXsUl59o/8nNJajFRrNeC\nQBKbaVlwgeYycDwQiAAlX7U0TlyCmV8LvO+qMuJA8nURMapsXSzQ7NOWsqrGyOWi5RpvFeLBpYJp\nlpXLdwJeAfpbP5TsqK/x2BBwqCw5+v8ts6eJrk7ZnXlkdQFfppkElqUPdjJRdrtJljlexJUV7l/S\n9EDrkcun2vl4KeoH970x/9UwnhhlWeos67t+L7KIn/jTSKVLCFzmgUCeWZOXApSSksada+4I4AAt\n7z60FhuEx6Wcbv5oZ1T1KOEQG7No24iw6ZsU+bkit31BeKNlNlf9iykLR1hA+9n4s/SHpuFH5j3O\nZSNjGYijauXyMyTR4ixS+lSVSyrpQkorw8J0EKC6Gj9/QrLDt12EFhqRc/lDsV3fcl6xs9O9V8dY\nA7lvM7Wafixk9rc43bfekx0ML7M7XG4s9WK3csfpY1oiMozMgqXOJxKD0kuzPssANEUXQ/D85/G/\nnAGdrXqPPiwy3wr6+JocvyteJL9WBanC4cihtz5nna5s1tFdbiuqfysaBZfzBV/6YcTDZKwKvTgm\nqZhIglOMJ9yJqyfJq63r14kkxSjwQMWG3RRiWcLLVOKSZtthZfeH77m4D41miS7Tc/HemOyqdMG9\n7Mw6ogHGykZ/Y7w7Q0wt8JRsdQCYRQQ4KdGqy4hgYTg64Y3Mio7eARXUZoVzr/CL0MIkbX3qQrSJ\n848dCKoRD/hC67cnMPZtbz1gXdq2Qe07Uf9HoKEBU6yOw/Gzj4NiAuP0mSKpjqY0J+M1wrQvgEvh\noYxui0aJNJD3C79rW+WPGfmfHlhkbxLLK4xp2Qbd3PTJR7sOAXqMjlWayatca8PLqsvo3/SUsDOd\nact9UheGGJcJzsHrFJGW4uJVKPja248SGfmB1ezEknT0Kn77YINW3YbBKksXNzXs/TRZwXPPmeSM\nillWe9EpxQsik/xmmOYNuaJZqBpJHWsO5zviU5Cqmtej8YXYjsiUzS0X6nwa2joG55fD2ePKRs2c\nD4kZc18LH99zxLxqlAqef7Z7VbPzF7rRytYhJo3++aDb/F1okJvnlhcWdE8oivy4CynFXCq34Dzk\nZddT5JfNqsqbsjI+Dvnk1g460kimaqtZiSlBWjGOWPbO5Q3FefJ2yYguWtBjOhXLkRhmtS3Jqkyq\ngaB6RKaxgzhqO7fR+aeq1r7dlFxYg/rwfgT/ou0hs/cLKDT2RzS9IeUgL82bZiI3uwApqaOWHjLf\nYSHAEZHmujq+y5+hiIUudFbVXYop0+n9iz8D9T08Y5aZ8XX3jSHKIoP+lzADFDe/st5DYrqf2V5W\ncYAuMkNmBP5vJjfK5rv7oKycQAyZpdD3KKir++RKXBz+ytv6KDZ3ruKbihq3P45XWbI9LE8M/NAV\nS64P1J5LKMAjAAkp+vYYdgjlsVqQL/Xbuly/xdraRbc1pRq/1hjWinOYOUkgFMajLAThGgfpYUkE\nJgYiVJsGajIzDh/jbbxj1TYpCLVE6S7b+OmyVEZ0T/xfxVDka94tS8QhS+UCxIXrIBfU5o/3SQ0h\n3vQn2lPeB6NmP8skmoExA7DVm82EtJ+we2cyJ8urhAD9sVqsW78f4S1IwcxShqM8Tuq8g5BgivVO\nX3JMd11qi6nKODzvG//MJffmArwG12IWCeAjpSSYpaf+6M1NIO+tY/2ZRIBgaTyaYDoaiQK5NVY4\nmYcA92h6QkfdvQXPFJAy4ys/CdO1Yrj99gjrzF+9+gtH5kj5guAt5HCh+4eciVqTfzSfmJaPLQlj\nUw+nQLaoq7hw9DWAfCut81PbxqUUcrVoZYdkhuFacEbq1fsKdSPr9w==\n`pragma protect end_protected\n", "num_lines": 1194}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nCgyLps+SA0ui7dPkXtm83wP9WSUpTVOaNUUaEiTx3o8bDibppEo7uXVLsKORYUGbahjOTDE6kwIY\nyzdcsZuJjQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nls1ZVg3oo/4jpb/tGSZ67UhcCiJPRZSibleEkmR8FGMVr6khAWRoF6kYXnp1zsyHU3zpkX5aZudH\nhQIPiuWIX1ItHdefmGknlXR0g8ejEjnCuf7wiNI29U6+5iw2QftYNsn+9bDRp5kdheVUcuxELJlA\nXulkNd/ln7GkFepSqYc=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nB9jNLech/g/tKNMUKP6f+gjxZsMheNAx8UaJ4vLJVXHNXpNxk91NHRM3Xm9hGCv9VXOliR2a8QYA\nPQ1bZLU5blYqH+18qF0ZF9Jo3IiF0g2nN4gOYAI7m5j6VqkzD58XFZMLPANE17Rohp8jENs7nh79\n49oN+0loRI7XCt+F/XHBh8FH2rSJmirxDK2iqylD74LWMeTBokuvbg3zEGTXe5qvYmMaRiXcTPZB\nDS3JpPd04FW7EUk+5RM0Kcu0Ly1TuyTKFn0mEksltOKTCKOerop73A+MOzn1eX1pf23lWhgzfN8Q\n8HjhN+i90Hmn+Ojdq+WsQMHc6+n0Or8KFbFReQ==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nCS3PEjLSMy66Y5kMQ0y4fL/X9nvJthfWlN6tOA1JzOyIwzumGq0fkllz2YtjUH+WZKf3DOAh6h50\nM/7oiAgx47vujLlrhLAvEpjj8WUfQd3LXqVk3NCO1ki3s4QNBrpCKhg86ykdPOiLuEXDkUt3v04y\nuxmO8exLVDFMG+CzMLadbS6QzvWCMXeAb/FFPfVqwPMMw1ByBbbNZPDHX94DLgrF41I4jklsrd2r\nI3FoDtv57i7fvGeyrplt+iDFl8lNUqFZyHP+5+yvGYA60xKn+8Y180eYGnmQ4wGtQ6Kkzn55UAKq\nBjhfYJqchzaFN68doG8FMNl5CP4MfMmIG1TAbA==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nnQe6+EVbiKYI6EF2Gkjs7kvdzSmGHXU4qtFfR2dYFwHCWHPPG8cZ35Gns8SCNITeaBfeRRFcv/q3\nUoOZpWturDci6dtPwvXGTKFk/2M0wDGp1JDGd5iTwJk4WyDb6tdfibGrM334X5OHFRDy3qX1Uovz\nSj9hOU/EFGjRS84ag4TVcz9z1f1Y+CgW8Ym4KNOI8D0oIv5DmjP/nJr5kVGL/WNmhRB0h+vtCoTs\nUcGqCPC2gQnw0GIBNKrE9ivvsGq/ACxJuuSLwAzquqUInK187ExgWQLiPHhTH6pfZDqnyZpMvGrr\n9OumyGggkggl7j/JE2vtz+6aHVWB1956RXcbLA==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nVPB71QTo5TspzkUp7HQwn2zfRQ8tDgsnLTLdZIsMOrJ+Y8fHz9hexHBR3Yhia6VnY8XCYjgPbAId\n7QK0Myn0r32s+olwHQ8M3jsY7WJNK96AiGDDRm0HHR2rAUT0mbjaG5Vdc3kGr5OmZ9abSnBv6qJl\nd6qqhUFQ2fTIk0vkv9s=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nIOa65t4pEqSGhDPlzgVIxaBhM6TFiSGG2C8XLJL6CyEFm0OzjlVbdnJuVLSSsqeN9g9q0ucPVcBs\n0MDNHCUMFAPmUvHCALV35V9sWsxZnNLruGv6jYCoLT4RcYb/Hskha3PIaIz4tnT++Oplm8SDc6KE\nj0p7EoQtGWfdUwtiBHuUQr6oMBdko07oc+MLXZy3P4PwN6CMYbgRTZvUcrJfxR1JLpjpTlr85sRE\nQCUEGnVHiSu2dgyZ1oOqfyUJGaHcNOM13rm1E+h8I++ksRVlalZKIcrckCfC48c5nJdrthR+8rsa\no+k61kcLH2NbhPC9dAejCTOCHyq4j6eKfXBGGw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25328)\n`pragma protect data_block\nkSwfaOQ2lUKsMClQk038C3qrnU/w3gNGhmdlLNfR9sWwqt9+mhQ5FChgk+V041Zn4jr0vEzfPK9c\nu3LNWSj7Kuy7mPDQPF4wc/gQY3v1ZqRVfjn2zXECRESZ7SISVb3/zgxGap9q5OV9OP32RkaV4kdr\nws8IbzNgdjoMmUEPWIST7YMeljelbQVuNUUiauyLev5wd5EZQgjtqiLEePwttFZFz+wDhSrZ+MSh\nmmVhsv4hlANMdsmgswzLepN8QpuS2x+4bV16nI3UsgySXVY0LRP+KYonO3zuI7oGlDGAKq7rVAA3\nosLmIrbqcv9oa8RF7mwv8MG56fHnNtMapNiNUP5a204RBeFO8tYuAT8VwFE66FWyg0x+SFytJzKX\nnDz/x5eXYt6o3ivPJ9zrCY3V2GzhHa8xLWUdmY+f0t06M/pjIKnPlBKPRL27dlEboBL1WLxjolrb\nZFxdGyaOrUIkqkQm8IlHVFmnZtXeSYrONP35eMP2kL4cGqUTusPeoqJ8DoPv/15TbKPwDOmaEXYn\nOEGzSGJPYZPw4+XZbtGAj0kRbQ261OYzNHDs3X7G23Gf83cq2BWgy5D0KMg8x7egPLMpaWTEJFAo\nwHEzBZROkgZBRyzx4uuOLJAzJ1Ww6ceB1GR8wqI1RSlj8gKQ1TwofF5FVToWZLT6C3Qy89q2zVS9\nA0mSl07IkvpxGwr60pFS+XBimis29n5s8FX1+Y2s6ykhocSOf8NQXfkCEGy+ol7sHN6ItVozii4Q\niSDgC+BYBApCgZz8ak4UXWCf4OdR75O09s2dPW1NNUB0LmDZ+JYg2+lHMwwfQbN8T9npoNochopd\nGUxTp/6OzrzXYuXdCTP14tOiLSckvwYVGLQRUNEHZFUjoAyI/K/pit5jx3240OUI/mdlbVjdEtUG\nZyZ6ijoMx/CJC0RWukb6rnM7lnnhpTUapuQNw9WieVmTSHV397OKlU7n+hVDrAOVM0fnBQoXDeAC\nPJlef//l7tgQN1x1eqzQkPGyXOWazM8DwiOoFa0tqkAslzrrb6K+PMxVs85IisOolgJv4q2sSZdV\n8RYCZM7MjfQlQzFbENfRZbZsAYj7zqKAdfnblfnQtX2D7QAAZtAVZbtICaIF1IOSNnsCi9uxK78Y\njHAC2RNWOwn/P7vBzImG9xwfIQ3kJklicNBdaHlR6kV22DiWPytbzi7H5Yh+1OnunmSMF5aO/a1P\nglEwFosYm2rOGqobOtvZdtOvQZbF2TLhNoCULxpUVohVdo53ERTsmRP3+szwtxMpYpRMOSIt1tO/\nmsxP5ho7MgE/Cc90lcabOMXU6TwV9GMz2Ec8YIMp8yPLEuaGXNyAKwcENA7mOQabA8/QNE8TzFxr\nzDj4HnLuxNA7bZFjKzEa951JtnbjQteNvnEOqy3O3vneTPebf0DNwD/PH2HzUyztYeqCd+4Ke4dl\n2XYcyyJlr51kmlzHyIsGKooMqHJz+hNY04caoQWD+Ev5YGjEMqMIxwhmZIm5te4ZzfunIO6qNTcU\n43BM4NF6J3RO7yg4ITHq50A/iI5hpAQKix4j86HXuGTgrvH7bsVcD2RZlv4gBrOkQU3BGQPAJeZl\nd25lZzULXvWYJCgbaXnlh+1h/NCjB/xX8TnucsxmmHdRBOGDImMff3FDsIEnGC0nEiFLP/fR0vhE\nog92bMwB4+f6Ja/JwPj/hHsU/Y7/vhRpgrJZFtljDVR5p6SPzfqZ+d6oqCyffmOU1mzMzEWLf/T+\nlKoSQNrcH05a6ts9/xvttvEnJoUmUf/H/09aoExwqbqLqI4rb+nzL1Mij1Mj5wjZqg+RzpWMw8fH\niJRUlCev79gLIKjs14oiBS/tPttcY/zs2qHsglefkqtfKIEk9s1OKKBE0NXUYo2xaULzpfqKFTo5\nEFsbG/eTmyP2NlgcNGiGzT4KFsKcX7sZCgsrutPwhhdzOBA/8N+CfVeVEsdrP9sS6ZIQs7McQ/7D\neNshaOGNMbXYLbebelDWqbszWYtgfVphDQs3tNtemJrIcmtApxUA/7VfLQRaw7D19ar4E8ozZz5P\n52VP5E6TvxR0qnt4C02mR733IZNNNYzEN62jdN7lHbe38BYdDWlVSjQ+j/iu8H9Uw1c9sRKzhMvt\nYSbje5593WOrVBZd8GSLK+W2/0BXU1rU8o321xmPD4KzgPFpNqOVlFZBVpuhz+66JTzg0dN+hk/t\nFZhN7JfVIRWniAPyHn2JDFXcGwD706qDbKu+155s7n+ZohU1JSwKxTvrORfYyvnLkkGm7fJQ7YRL\nt7BfgeyatEZYG14LIXAYjvgfjq2wtToa/TvQDGhvQ4Vm8nZzgWZcwGS7TJsxAg9p8hrMrp6rWD7q\nT9p4sQFyZjXkeGQMbXKNj+j76S+MV1+ZlwlpMQmax83Q8n0eG6krBX8W07reDMXwDi/pfHZnR9be\nwf1owb0a9mwrd2uTVsyua6HoiqBX3Pal1FZOUICvgzVeRPQjtX+5z2m2bTFa9Husd5qgJtC018Kw\nio6hzaTDp6k0pEhuNWKxCu5MYR5qZsH1QhQI1Tvc624IFJ/K3Ay7xDjun3verJ4OUefTvdYz0TxI\n3K/tmfQB5VfrezfWLkF0jHF8SXCf/aAil2oXjvKKfzIV+wTzXtKohwD8MEfjITbrP8BbeHj4Qjjg\nGdLwOy1xTGJgUSS9oGRx2/393scsFP4J00gbt2yy4ZaVBbdIV4oPk9/9nJniWlCNrHYcY0VkRd3s\n2h1bfTegZQUVLvAzHmVWExqww+QVrN72GuinDns3uQJzkjW2oXpXU1+I8K/xOe0aOZgVL57N1lkR\nL1i82WWSl7WHMwreThqjifFVASVCTX6sg/1eVK52Ab/QWUmFtTRLUWIOVBozlcWjVZGi0/sDgJfM\nXBSZLF6a9wWTbhObbri+/RP2EJDzxBS7ImjPO7YXCEuHFqwdPBxr5pz9gOmjeSWjbTU3TD498X/8\n7PjURq5/I+TJmVdTEm8qoPvBEILhT17sOnZOCqN1sxzYTUTwOP/fh+5SFWILs8IjXlmtv+wC5IiW\nzInQYX1V02BveC/m0fmFsn8knWeUXWW75GIw8voicnX5MIB28JxYzTqzCcaiKqRigyYOs4Osdese\n1rIQSr15MSZogNQA4Q9uqpVZIJiqX0tGTYJRAdmcBKUUxy5OaslK5g4juCb+CqT435m4GHC5QyDz\nxUGN/7A4jI4VXcnL0KDU0uPNygMNYGjlBIIeSVJzFfLW0SZVCpssVP7xEDYv9oPoBQRrOeKRQ5qP\nGKUUx62dOlmuZ06pL1CFyRCnptFpfjZpiy/u0X9DAKJVLS28kyK4E4aPAlySXPnAgykaXMpq6+L4\ngwQTlJj/RWrDVVZDLpgDv/dSjiDLi1gzYGXu6QoY6yv9kehm9i/zGfAH4Nm4iDp3ttttUcdsGJUY\nOX5pBJJFOq7Xm2WbEGNOUKF4n31GtBjRcid3c6qrQAnTffL/kjQYzMWjjxtyQ4Gq1S8SG8wnZxh0\nLa2V4nn9sNN22rx8nyxr0WZxxCT7FRXBfRsyViBXA/HhwUGT8UtOaucltcNOBKQ9aGEPrXr+bnhq\nCEhMfhyJPjgUKZpaam2DDDqz+BNXGTJ1q3nD4XKRahlStabRjg2WslgaR0sUa4f1P8T98v4+AyKA\nbzxBCXiDIjjI5UCH9o6n0WB3psXj43WGP7Bm9PfB/emi58Acg56+fqEW5+VjMvHJo29TmFL8byAB\novlmPIyfC/Fii0v3LlYWAxWVA4VBG/LpFcgo9qPW+Yhz7sSZNlYWYRx8BSBtFHPZ0UDQKoIXQ/Ne\nRDObMN/WxcEJcEwTRilhQhKx6hlQ7hinqOaDY5B1GFPMN3gTpB1dC5lfOwDwQ6XQbTif0MUVz+e8\nRa51wUr1nWRmVvnL+wl6eX+bie4IcMHbk1IifHUDQJLPPCwJqQ0W/PTILBcdBSnfkn8nQdImfOp7\n+/WRn+WQl5S/4KjVdl0zWtYEetGtJxHGs8S/wOZJ2nxSnzGuFeaomei8jl2gP4EFf/WIa4OzwqKj\nz+2uN4cJx2vlfkt2FtUjeUovD56+jlPthlDUP86m828E6z+HVX7ZoDEV33LWhlQsHyKkmoiMWzYy\nHdVJabgGfyUmXygSYdEqr4ED3FjHYpkAtC/7g4WhqFvZ0TALvPcdB40O9TF3LtysXZQrhEeY14J7\nKdzxRRPsCltAu07xoEYgxU18+1twpdaZZD+XfOXHND3Y6kE3bjIxMBv4dV3AHbmPRivs4kW6H4gT\nFVcUWuPssTRNyv66CLVgv3pLFaGbN1fN1GBG2XQeBv+9kUDCq+rBrqgBwhSj0fncbah7q13tfYsi\nqMGF8LzDq5M97C3HMEMuM4FfQBc0zP81oqicqoWuBh1mhWihKI4/ZlaRO33f3t8wPtZ5Nqn0G8GE\nUNlv8CLzYvaC7tSaKV9gJySIfJKQt6yEnk4CGj+RVRu1UA1/0Er+TlbXajVybaQRgpbkQWq58eU3\nyOaqQ1Nc6JIJRNFNfKNfxWmJlQJCMbbGoPS163X0V0rQ8l5UNfYvEM1AJnntSTTZpcfamyGcrk1F\nydtxqkwn/hjqbFePqd7AqmcKjnKUO8ZLM+mkQD9gvnYXy8VMY4JM3F7mjELqgskwNrDfqk7KYp84\n8H92vTOvdcxMbuELQOGt+G0tx01omR3v2+zCUYlWznKkQJTzg7hSduynfrqjRa4s+ukUMKw9nW6s\nMH5T9pqhfXqizyUg1dFErIGw+8Nn+ezQ2lycDwRRDq5Q7kyS6RHPjMeqERFvlIbn8kimWfeQB+gd\nDYrZ4Sea0vnHhZ8T7nYIWltwn6NkOjxMONqbv5nBAXBhf6rU8M8Upjt6ub1Pp7fpd5Z4O9XOIn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XEmW6zwtcpFPQIxv6hxYxwC/spdTrLGoB4ILEP+NODQpYsELTZi9WLQc6L/iOQgxB2qkazE7\nznpYIqd971MHDyIBimsMsV2MIlfJx+fbxPxgOLnlldWhu0vSMbvH0tKsCaqq51bg80SjHoTbLdRI\n0RXKBNHiY/hwNrAd/uDNI1VArQPSevUJihWecel8HQA/qErqDeuyR3fvz+etmwA+wEarTYrJTqBx\n+0gxN2lWRXXSb1WzVOI/HRxWhUkbQg5KGLcd6MW/+7yH/J74DfKqSSUFnkbQtw4D3iiyobxCMVEz\n//3tVZ94deYB0NSkbNhQwYVGtoYwo8MnoIs31fabSPiDq38l7xlx9fp75ALhijgOEf37nXuBTGRE\nroDKkPV2KRClavVRGPGPcF4rrGho2vJSIvjU67WpSxyZ/hef2sjInD5/VTfOHdjuUA39/udvN5md\n5PU8SA5cevPi3hZnv9LPMedfbs8OfRpINO1/cETQpi3uun7In3BwZIys6d9lrhe0okK1aRQK8Cnh\nqnMJ5Yk/vCW1DzxsS0YjsZ5++CKwZzuxv+pfhRoA360JbNFJ2+BnWfrTDAYfBh3X7DTAN41eWGJT\ndNIaOmQe9nucKLsM+5bqmytNG1XR3x8eQfnSG7y9u95+a0KSMLLs8vDW4TMjY7wKGfjMrcLBXALX\n5RdBS8d7iquImUPCqSe5fyfq8aViMuTA8JyRpN7reZ7hr04/nzBj5v/GYAf/fcwf9/zsj7pkvu7Q\ngA3tRRZn7bfQXUAh4a8r1qtWmNvSRZjlNWf/0mlhv3MlEmSS3VN0lREGa6jOvJOOx7rhOXLSBPTP\nrhkBwriy03trzUP0PVLbhK+GHV8SATZ0qhsPJPvKJ1ArUmrcalWO7R95YB7EZ30RaQUr8LDu8H0H\nxSfvBDwdMyeOuWz28PLk4bAYYi1GFnYL3c+9aBO2/cQRrQOIR7B6zDTzfn8ZAlxv+JYcFcA7cDdS\nneY1+v1AEHA410TBSGLSJ7W603q44z94d7QgfZKpq9JGZ8Ss+XuzuocrjtI/CwzxAYaXJAfyCkLM\nvSecX9VlMHY48b4tYVPrX1WJPcL5vc4bTwpv5yDhIsqRRo4lpshMtpmjP/LBQkThJMDwD4Evjxd+\n0Z5fgZIhj9Cesf9L2z7FA58DJ/shqe5H6BxQXh5EHfWSUwr7+FGISDY+aOXzkINZDYyhT4Qc3M1d\nOp5u/YuAiJwVw0oS31g6x+nPXEvDwGDKIO0jR6+C30Wqzb2uD73ACi3CpG0Pju7LE3x7sgwWFaqP\nR1UHgtF0dYf7H2mg2E3Jvz0vEn7MLjcTcCLLvU551616Q1+rUxIxuCVVppmXP/ktQRbLUsMyXdfy\nEN7oeJSTC5WEEe+ruuQFCDTKWJdT2y0pdFnqTf2ppYzWv/n3pGBJxEdDfXYHh9u/s0uBYf4UjqdW\nkys6LWD2yMmnuC7j3ENi77hkb9Qjl2aJb4q/BM+soWZt+ENkM8mFnzNODGlHgiLZlOivoIO4IjDT\nBguf2s76miE8Y5v7LW+4nz7zaAzAZZrtrzoR8mPrEoLsw426l0yobffsmLCoxB0Myjxs0J/P8V4/\nWHvRj8uQlYUXrrS2N5l1TWLrnIRYqvGam//oUfGoVR04Bsr5BsiUo90ulRGVW0U8zFC43lotvhXY\nI9uIv5zMi4kvR+nv0IiHkozj516FuEBJae321TuWKRqcMNkLJjM0K4k6x2V7fexudWDHVhskWRpt\n2uQAgpcdhkCDKRctrzCKI3GumkTB6yHazXLoWdpVJ4nlq3TwjQiQ+FOK8VG7Juv9qDoWxTEwXLLT\njtJla8yzDow8WL7U+/9B877wQveVsQ2a9OJ0avMJCtrCgZt4IXYX/lmVkkIYi35HVACSra0Yc1TE\nIpiIqWFNdQuwsaJe71w/LZ7wTfkjeVGaxK0A7sSf2+WmYCASD1CkPFFrFdSXvJvK8IUNvAZt+gk9\nPgN0ff1oOOnee5eda9NIQGfaH7++ZnwFYNZ3JUzh7aP8PLUTmDuIUcEhtjMXZC7eyLGN1xrxC6Xm\nxxqU4iBoCLOpL/h28ZMnNPN3/L62xF/eXFI1K2c1NiFp1NcI/Uv0MP+uhyQsTsx2KA8WjYRHyqe9\n46ma8xWeqTc8FpQH+/SNsISHnF73a0dCecKtu6hKNrOLslP96Tl+o63d3HvD2JUGHkG4rEB8PzKN\nIG/N9pDhl2GaeIZVHaWgMC9dzD8ms0fWghnIhCfvYHErSkD8icLH7Q8OyhqS8ZUrhB+Ye6hnH20d\nGhvF09nRJI7YR/b2nPE25M33KKEY5ejkELQZCtvUhn1WEFtH5alKE7dXQG/jjYYTVK0+CbxVbBeZ\n7Ew0/6sJYi7p7QlWt/RihMVY46UHvglpKJfzlAmyPi3vdxpoEQypPvXCL7gOkR1cJKu5xhIzJ5t7\n0hT4uN7EMvLo6IfiRaKGNeCjrHmQ6nRlL76bp3vJs3/szupk1BRBTId+pKkQOlPZjq0CiyEfkOR6\n7xAEu8rgPdRSiY142Yr03ZfgL1tjSTWPwbqe6yXZJHECCaKhS8dOwv0iG1HG1xqfCpDb8bGNG5SD\ncJtGHW1H/y5DkRSh1qCMPyfyH4/v1T/E4/sXAUigrTVxwaz4x5qzq8sdSeVPJ6zEkLLm95p+QG/Z\nujUA1GC4Kp+JWSbCmGIGmH5hywCzcC5aZ7AmfTYTacxrOMh7eHq39R+INTMuzAjRsR7wgxvCfi9j\nVCrjcKH2e9tWJqYS06w9fHygPwsQBnxDua6ufBzh1vXJw9p+1YSqcdHr2J1GbaCDH9g/QIvGU/6O\ndbzF9qmG7acOplOV+UUN7bPImCfV4amD9Atdpn/yCqr17sbq/XnL8PbEfLFWwGtxeTDJNewdRG7I\nPuwOhE7/lAPAbTUjhdmGRU5jtZxwizcz0L2uya35thXsjXDoa6rM6KEoM8AGcBK1tb+yd7PGqnVV\ntl1tPRqgqsMj/Xfk6jwPKq3lc+rwQykIHRcKtuqFITMDLadL5ep6HMsOO/2PjRxrIT10V+AWqKcB\nWLdowlVBAqHvybs7xj18q7zmKGvn1/Z7s9JF9HeX+DM1keWzTV9lyDS8cfCEWKfxCCEMi8KH54Qj\nEzrbqFKm7Fwlg8Oz26tPJ6cJolCH45fSrmQ5PmfPIbAWYgadv4hxIy+8YqesRGAJS+JIa5SOSXAb\nATecjyYRjiHOI3AS8/HJUC3fqZ8N9qAX11K9lBiIjeAbccZK8eaJvQpoXGMA5/BH0vPycGo6k8hl\nTza8n1FJfrMyIORyUNwP5Peq3yZFkXNUcnMjt7tXqHfSWCwg3IFwfmOAgLs5w+K8IQjqtJZqxtv8\ndakxmjezVpTcmWXGsnw99P9JqDGt+BqYzoTXmJxw2iUPHthmNl6jiRoh49BtCqHRnQgIj5pNFX5r\n8t2qFy3ToUPQLoIhrYuIfhzw0AQLDFDScB/23Sk/8pxu19MVCgBmkfh/2xMMKtRbDkLQwTjdwpxQ\nrqEJ8nqvLO+tBbczQsREhamGHxOUpgAZam0D/KuSIlERbp1BpeZziflu3F3wDf2icJEXWOzomO0S\nnodxZZmHYclWxNI/ZytanByEfYfTNEbOvhpHGASwciuVfAXSoXNV7cVmuRG7sBuTSczVQJP0cjeD\nbfzIkwIhsW2Njg80CgQT6mdi4zfsAb0fr80e1VwVbWwtlX4ofhP1JmDrCrDU+AxxV1iJsCSzS7AN\n5aOdu3W16RzErzEE/1um+Ev7z174+8ddYoUfOtuFxVvAElaTxFOt9vUDJ3a5Z4WNvJgPe8cNt8R9\nYfuVdgr0BeqEC38Mm2VemwCGWJiilw8ZNufPdaDuT5CKev6WQzm2VpdCUPYYY3j7gTd23FeyHfZ+\nzX0yCzO3DJT4trtRE6sOb133kXpQkQyw6c32bsOGEHQ2MwtPveJMyiLcdphCUSbZygAY0Wm4OjtT\npq6LXISTFqDQGMYxqDI215O6O1e2d3yv6JmcN6E1AfLIkJScfFfda+qd4yuqjCTuj/65YSaMNf+z\n+SnvOvjH45e7Ad5YSVZ7pLWHQBLz+jaDxlZDwwhfnUCKmKLsz8mKHMw6AveW9NnUvh/sOtiLOd02\nWQJaSR/GcX6plGQLt87uWd/Se+wkzsTJ8uapmtIznpPZ0fg5NY7OuiIjmj3X/cxbsUcJsP4QK8Yo\nXMYEoSVaU6M7gc3m4CsLJESDVWv9usg/ACikf54onEvQw9jGFnP8AV7yhFIZLvfTg4xiFbNjRrcQ\n16mwcW0Fe6L1BAPAPhrb6wDKTI1hd39jJ52C1XA2BpBmZ5yGkT92S8cH0LOJf/v8yb7ymcF1OPYw\n5jYG7X5OUOCrQmmOlINIVsu8XHMlnRa9IDv4H+0ylUJnE2So7kW3rjDFNDyJpJ2yJi6NlHcxpHCW\nm65qtutuY+kbFMpIWHpxjs1cQfiQPCBISnJFVxNGTwgCqr6sHj/5ICiIsCkCO0QIy1jEVJDN2qVk\nl/ZVfIdNHng6I7vy5BzCCb63/mIDlBbCjFiafEPKSnzQwP/0N56D2ImUBCbYSdsjfLV9hiVIBYpj\nYQnNFNDu81Y6Ty/Od2AKyy6UjTdmLb1rdqkGnZ5qqAfhwM2AKZ/XoXwiurBa7+Xgwy+R2jBggubw\nbeRjsDJa7gU4M0gGheeRgNDnoizYw02Vzlg4k1VnPjAsxNr5XcW1BJ4Jm8vjEEXBBGGvVP0psXB+\nL4iy7FHUCgYPy8hYFqN5g7hLvb/wT6pkyNoUMoj6h+9GrrTy+rnjI6kGmNlIsSYu15F7oQbA+V9k\nkLTaiiD0deoYHRklY7pt3lUK7rZHQKf/n6Vx10/80i9aBofpZOIi3uyImyCN7hHcCCpYnvew8SZT\ncfFxgKGYa7V8OeAxk7jpLBvMxfr2ARp+Ep4D1sSRH2oSzKbtM/f9ncdKLxEMHr9wxupSW+XoOraE\n1yy49P59KV53Y3YnD4miFcBODs7CRM+6bqoK9hO1K2W5kvfodbOzIB1IARSmOhRwYdljB19jurPE\nYU3GUTC+u9Te1SflGvr4XsqCbbGMLETHb1HZmXendPnGcnneY+LtnYkbqK7SkCN7x9OkYrdD4Vsq\ntbk3FZFRMB6EZ5WZ214LiLTHzEmLckyG670YR7BNLjK1rQInQAgxS7Ri/B0TGCrTYRAynDMCPXB+\nEBZOhtu0kTKOAVnDj1uOhBFDA7cmnm7e9k9QBKhHkPOHHz6q/8B+iEM+hX+B4q9fpPM6oKw+Y+1s\n8b1LtwySajwDTHtloQWcxc1uR/UsnkCWBPuL9DMNYGr3ZmKTEnGhp70LePkIcfJYuwsfo/E7aCW1\naxn2sWtKwZrw0+CDk0QTotfQ6nG6Wr7hhUAnSqfG2O6kYjQyPSn4k6m+aEiUWQ48MMUvY9ABq87V\nofVf0Efv1OdyGUNFigWmZe8JDvXnZiWw1K9gwZqBldibpaASp9bfFJgdiPr2CAGTDl+r8eoMd1jn\nBbQ2igsBTuhTaV10ZWJFSAIdZ4+V3HYLkLU8oSRXqIzqcI/IiAg5SWLWSaeHmkCkSbn70TQGXGOF\npfjhv2J5yzmkmWDiwFq2qT5eWOMB38FWcEeOtiJ9xvBgjz0qOyAP17fXFxTm23JpVYazHXlTlnnH\nxJSftOg+EKpf3k7fWj4DxyytvhYqXy/Cw2R1dyUtnLFEbMzZd3Kd3ejeXjJdr8nuiqNi+s7uqd6f\nln+VwVZ9a3biIRoGDPRIqfXo5untTcj3xHOwq02XjoFfYNwh12xIfB5ZpUmpKZj34IsNZiFggBr6\n6jqqGibpp2bK8BYBtgi5WPUHkZJIuu/COkKemycnSDpeAv9Dc3KRz3nwhCU41HMq1xWMVrrY5W/B\n6Q1U+SBjTYpQ04mjzFOvYTtEim9f+nV2S1wghga3XTYpWdtpng6n/69RizgI6R1dyj9sZOcdhPFC\nLSFGTswmGoFRGvNeDd01cU3XMMT4u2Z5ZOJ0f9yEb2V0quk1hIqMxHLPaG78pHgJeAtI4ztI+h8x\nW6bMzRi+2SADpd92+2fWMSzXApfsMfb/CJmztrl81bZ/RiWoHQO7FahUXnuklE54bClGGhaEsp/H\nJDvuGKJi/CWrkZltXV3V+Y9rHOa2gxVtp1SNceOD7LJQtxy0tEh8+Mc9z+X68qvpUrp/u4tsNXDV\nXsi751iqAXXO0dnHOJ6OM0o4xjFty4aOINWoxA+xCmcx4EJTLLggpKAdzIwtad13EDly/znQSFLF\nbnp6kOJKqe0W85XvkYnXQff6cnhRSWsY8q2CG0w18siVnfa3E4xAO6o6vcJsbyH18/PAKl3e7Bh6\nNTN5XB88JkKGd58BVcAOZpxLiupbboAJCvsueNHTlyWyvvwbLqsDVuAJBSHpPs1cFjLtkeiTGT+a\nSrqsgMO+UHPBsrwvBGWtDxj3TIKE2Bnvjmq3fKgev8QgzmUU6ZF4/FNAnmzGpTTvADIiUY9lHdUv\nE12u4qX+I69/sHvIACAnIwYXNbd7R33aQ91VJeAcxifdcZA5v9C3ahUaFH3A1RK+enmmfq3TzpVu\noJN+l23KiY1hkUYhiR2aCWIXRySCyiY55+b1G2/fRN6+GV6tJ2/hDe+vqM3JlVPptTG3ZIX5Xn6w\nXYIcd4doI14tVLSyAXT+x6QXdffSrHe/NgPJaYs5pg3BnLI3GSDNxlUE/pU+OvTXDTutF6naLbGk\n3H2+OtT92hDETD3Fix908xWiPIyeY70Cbx6Buqa8znPrRqc4DyitrDyvoQlrTxSwsLstbSVHw7mV\nHsYKgDvPmw1+ZSb9KyxoMxkr19CiTRb3JOrETdiA/VQqnMkjJGK0IEojw02kx+ft8nWEvJkEjXTT\nvyjahSTIEhA1jVfUxN86LHEucrkqhb13um/j1XrS3GRfic1TgpHHW1S+0OcCHpiKzX11xznmgBbt\npi/8dC8uMXKveFYefwObSfPZ+WEbNUFC1u1Mtd1FGzNLljP9SEYPCSYTWYIzMmwRwWT6betJJ+MV\nq/08MKx6b4l9hUTYOylZcrfrrBLhb+qmqYl3C4dEybhehzgcKYDwq4KVDUSo7uPJKSObyezVPZGp\nYxK9gGsaTY2Y1vrww2p4LBm31MsezorYaIvvDZrRulc378EkVjjMFY74VdMTXqb+rpjLfZYvEheR\nltiLMDnzHFMTLx7MnxbGVbuTWXJtisMsbH5vXoXWGEWinvXUjir4yICOZiMgUdQNG9dJKF61yV5d\nD8vuzUbVZWMNKO50MKFFeQDEIi/QK3y9S7CoVspKGFiX9huOjtKEFypMTRvN25ZU6IsPSKFyBU3G\nsf2LC3U6O3+Aia+yJnOJ9j68fJ4j/y4h4EZddq3di2jiahqK6+92jBeqa2iljZiYWvUWjn1GLa6B\nmAddWZnuVAaG7sBULE1a2OvCuqt0/rpv4E2T0oCtg83dwV2wF1xwvR4TTP0k3VJkMDa+bRc6F1If\ng2DHdDMHOJ+zr50PcE8q3ATEQ3aRsHk3kiBDSNjCLxAu8Aloh4dvJok4QPOA82ahFUluEQOphCXJ\nnoGJVkBSWcXhXojWVO2iZmFMpOVj7j7CK7BqYLDRlfM7pQg0hLVUf+8hH8DhQSjK0e4V7/wJZLTP\npmLh/NhqxxhNtRDUhEa3xSQBmYRvWk0RbL7Z4jTo5yamAInndOM6Pz15AIijBTmggr42FdGAT7j3\nT+Hsa3nAUQEAshewF6KGwmCpKUL6hJwVxwujj3qdOYfcfVJVXWy+j2BjVZF3yRPrb6ZcsBK79nqA\n6znStSrjcPRpIMR0WyiPVw7kxu8u41VKTh7+x9iKHXw+V3xz8LDyVhCea+Lu421k0ftGM39elZzw\niICuqn848ke6Z7HBYQQcmBZLAnCjpKlEfKXiBiXC9/jrnytaxYWEwM1XfMDvfrkot4s/9EvpHeoK\nheSD1gXbrFhPXM2+kcS29UIcUeqaXVoFbCth3Q4gQ62DHteN0gw3hY0UNsY9Q05PN9qWfQoEZuBr\na2Bzj2u0Gt9YJuiH9AjxbWdYdJCoTVqSHPFsfTG+SS+TX8PcfGlHY1VZSdrScBIh1mWOl+bRxvvw\nt1Tr6dyDMLPJXu/CwyCj7teA4QrSMaPNh85K9Dylja1im0yXfAR+C7wRmRZ7Dd7QeOV5hvEC0YGR\n8TZxe1HAae7Zs+dfgdvBmR0esfWzNoda1mq2QiWH6R05QM/1sLqzdodSeB28NPx9WP2IqimxNBQh\niv35VU4A3epX/FjfVmMt40C8+kH2eC+fry5mYwvLXIAXZisbdynQAnoM+GQPONBsjaTyOZptbijq\nx6/Z8Ujz3G9XSvdiA2SVWuD410cnGgQrcWQ3tDBKfsz469bMz7VlELQn6SUzoUmTVeXqlunLMgAT\nZjAFpyhxsekFxEesgRUprfqnBWj8WZiwYk+++EaFrrl2LOVoKTGlASaf7i7PCgiMuDiow55MtAdH\nUQ2BBuXL5Hb7cpA7Qv5m/wgDTkM/0KJe9wVdZ1x+8bqBXTFyDz51576DrvtZtAD/XbJnA1kE5pDO\nTIqF52tj1j095Awo65eN1D9llYHxAe5KqySoIQ/mUCts9O55Ttef/xCU3rgLPln/8KfKrqhanX9f\nQytLhGJplYSQ+JeTpwLQ4AMsrKC5htbluB5tV8y6yp0i2ERPTDEqqtq/V7XMiqYbdH+04sQBR2nE\n4k8UUrISsEJt1r/1p4kKu08UaqcNRB+543qvLgCj6oYuFvcyZ26VMqgmFqYnLBBt6rxv0NbItcuv\njnXcTIV4DNLBpHsCGtPT6iKVmV+AarzOVNre2mZDZSjxENol85XuFWZKPGwuQHGf/13N0FwUZj33\nbcAaynRH5O1xKzw6B7o/6QOLte8t808bN8lTg4RtVzap6jb2nZQ79xfViEMvZj4TZ7mREpQb+UH5\n5w0c1wRH6IQcWeMYS4tEKNOFbj1fgfFa5WqDh5RkiRSuT07K4kqQ0IDvbuKVkJLaGtrQikvV568j\nJtt1GYLsDnJvj414UYYVlISVETETB+9wP5/n9mMPoKD1REvPhzX0F436v7GKY4JczyQWlQtdlIMy\nHSjPO318tn07kwO3cAJ5fsIffJCCNagrTfspZf9bzICnrQL6maPSuNgYQgqFwfDF2RM7YKFE+zpQ\n1JcpFaojBF1JuaWNYohO3O3iXCJB/AErTdLoDmZkRGr7+6yhSCU/MqKmeu1eMpbHzscQ1l6VgAoj\nh+JdxnWiH1hTvWfwHuxNuwiNd6hyvHjUyakzZlmJsCLhEWk28R7wCG+6TQMA1Qsc63dQtHvPUxkC\nn2VqxSKjMhSxtS2iXEtF2i4gqnU7RrlZPaNwq7N8FfBAIovNAkquXXYkv5QqOch1Inbmi4qUAA1k\nQPEde2r+zd3qjLYuEGGSjcTd4RTxuMzh80+//d8arJdfJKpgc51kD89xm2S2hti42Db5ewQ/NgEx\nD5Oc6V+9Fp6zaOdR68MZ1vqFLmPmxrnOc77er0e4ciLRpueVvrks4AXCvLpDexU+qwqJpHcO4Nsq\nePNG3yBCFBf+OkklK9K2i96oQfq61gTjMYDrqdASmgo46lvYVsliKZxiATnOtrw40xLe/I4HyUek\nUzpOa7lwnkXdKgZe+gx5Q0jxiJiTE/F3r+2UpJTaO7MRcwplFvXFPSSbDHfKwF/BQjoMq8/pnM5R\nqZYfGin5xwtXkin877nraCfD6s189FrFvYKq96F5I+uEq7n74mQyY274WQJw9Pq12zUEbQsDg0DR\ndgsWPYQEt21HWe5pj1YjzKc3k9dC903kOq1+KD26+8pdMcpvICRq+WJddxHfZxl6ec1XAt2QKB/w\npyPg4yDmh/5/aEOuP45dLO4gUbGL3EinXZWQ+E1jIJoSnHh6vilbDhtX4e7DJ46+QIqny0h7R5eW\nsfDz0mHmHpRxuhReQWkB2yJeHEe5qYDVKFzzV+a/yM9kAxoFkRxFTn9o6n0mtJORZm4wxoGeQlwA\nIXr9swVxSPgM0S8/RwgkdEGMDAz+BfFrjvRRbbXsrQK3aPWDSTFswnscfXV7EW6+nDVhMJMbes+D\nf4yXRYnRL45CqKVRwr8am3VA8FgN+DQrwIvAbrZaiZMzBU3TBLFQnt3zNny734g6Ufl5gloVBA0q\nt29E/m/RIobK12HWVG/5m/8MNwNY070i2VYegXW8o9i74wAONxZgngxdmnerN+0Bmu5ugMhe0V92\nT/X9Yt9A99AjMEGdljk06tBlYIWLBBv7JdeUmUItCy/FWuPaUZzUGLKbzoBfwXuQG458SVeCmYqq\nKCBgyFSQONeMJe7dhcaNg88JTodC+KDndvWzuL/Gu3YGc0LuoOFqIE6SumcamDQzxQSTHzxsJW5D\n9+WgLz7d9U1V9dZkBWq8WC7scYXmYEJY2TVNJjHVgu/DaW5+XOEKNkvtj6pDnGIwi1nRHt/ywZEv\nMkcqF+WVwZAEUXVXzMuF3xvk/ytRRhgorncR5sS3ArptApRy/neZT/RDVsyV4JDMGSdzgvweGLjn\nD2KQlEpHOu1r0lCWsdTnBML5Ya5tXGQcD0s0DXsJWiJqHyeWFXE8YmOpRBKrnBiGLJaz3D7xF+dm\nYF950bejYl9BrCezc8s2dFTTXOiPC2aLtsqtvhGaPGRNomr9s6FF5YDKECFX9Gtzy65jD2Uxi/tQ\n528R4MC/Kh3P/bo6d+mGGThuyYu/w08SZJKPSMmO2HDiE+mtRVzR9pP+WZ/MpeKRWYf8JZZ1cvz+\nQ9r0fJKYmsiQgj9LJWZYCdjz3tupcrvAXARjilyqBOxVIq2OQzjnIINDF7IvpWnGaenn/Ml+wiLF\nuK+niFvzqRl0ZzeOc9MHYQii1+56TeTxWGY+DM1kHBxBOGVqJVkIwtxkFtjDVk+Zk6HyIPDCN2AR\nms7Ojlj8L9WJyotBzxLNdmBQ0dGc1tpCwdthepMi86OcbLBDaImZ6elWWAFQx/1seibqgSYGXwAM\nllhCxzv1smGoW5ScDPlgpzxfrIsVNvlBXRBMTkmJ+qOQ1/ZonCBNBvc6wysO2/bRH2q22N1pvx8Y\nMeL3M30cfu2qmswOY8Q7zJl7tBMfeaj22LgZsejWPOlhwAzfQWVy5IwBujhIplfaAel33LBOiS/p\nAkS5XH8sMf7x24AVDupRC/hXOAy/awmE5KNbsFq/OL14Ptlmnjpyf9NEh5ea/cw7fNWpTaK1Ozo7\nBa1/0RAk203DiiRfXWBNTVH2047nL0PGx5U0jzNtxRJtrx7qOVd0bnP8bRRX0fgGJvrI+whKaSa2\ndI9EJ2rAnBxkJrexb7OzccL5GW9f8fOd6HUYa0KUq7s9PTeV/hqqXND6gZlfbVp+6LRn9XX232ig\n3TigRnOeqs5gBWxf+yNhnbttVTrVkhyHkg/4XF/hGzljDgM3xhGsLlAQYBlu1IFgDQKB0QCcqLB8\nuT+ItAHiLDsKp22zq7XP3hZuPvXsiMVXhk3gzW80XBjO9YdryFgZKvJOslBV9LRpqDLqwVjbwVvJ\nFJvKaKH95Kobys5cQLXhCVkROVJNghm2IzD+gAvjjNNN4v1g7o0HPABDSfWhWSxdr3Q+M7NvmgKg\nmX4lG5pYL9gwmWn43rwtbxilOwvejyvzUpDsfT7sN6rywK4FiicOwdZu1znqp9rTkkleBJU8oWzw\npMUGzh3EvA3wmUx+yi2nJAivFxWtCIBBLF093Qk5TZ9JF5SsZMriphe019NHeJPN7VM0igq8m1nB\nMNsGXrJNqPg3d5+VMFqxPsN1xlVssCxiDRU7hLUnSCPJwOsPbrJ4jJ+iI5Eu3MZqffJdPCUKVxX+\ne8VIBYaCIU1n88ZRBy0/fvnfyBlP3rJegasVh+Gw19ccUnEcs9NjM/kJdHh6qCi41KIxuTjFD9IL\nuJakkfHei206Hx86Hfs68M1idoaz1YXPzE6MLxYEHPJL/jC8wgpUZbfDQMUY2fq151hTgA5UrVXn\nzNvQRvIwp+ejQ2rq7HsJh4xpyAWWp+UNkpIIGfCUtHjAZl5HT30QkWkdsNytGN0EparGxYu8oIDB\ng5rze1cL7TqjaaZth3GqMe8oc6Ee0mdxzqr6WT0jcmT9C0+Id2YSDXTVsKA4MPNekS8nIvoD+FzK\n3wunleyNqhPmHrATn4TtGMsq7mlqvPpyOvoW5T95hr0vyPIYpnDBvJ2EE3A+GoWaeAMfVInayQk6\nXNjWGST0FMagFBvciuZTo/A2VTJLDygqcDZPqqZ+0NfBGuJwo+CRzq5ICxtDwv0oLe5kj3d5G1qy\n2vqHd5m0/71p3ZseGeQM8DgW7Hqv36f7iGKfaXQmvwwIkOY8H2KYBOpRuwOPMwj1Ez+LZipYbyI9\nmKj9lNhNz3+5fIKZFgF29TCo6d6au9imnNXR2ZW7fZGiGKIOKv265X3hNpcDmYeyEeetT7nHsAlV\nElEAcD62bZJAp0i5Riea1lpN9hD7nin+GHCGsCd8W9cYSE22IJKvejLcO5WgiW5lvqCCDCvfwO9I\nasCxXebGi4uqUSQJBxRfSbhVSG8FeKR4XldRaugEqxc5/843LFRdlm1V832Igc+G8q/M9pmobo56\nB5/SwdIjFyaaBofHMML2Dlv/P5YHqmWOMGyNfBRWRtS9gcE2rNA5FtcXXli9iKiF1v6ngG3GKJVS\n1zkwJNaHKKV8OMARo/c3JSYi/l7iC8eWvXxNDMKc/3fjIVgTCeY7RM6H6cWYQQdJoPqR7EG4bDYR\nosVI79WGWVefVhS3TxGX8UYWAxQLbwhbOuie2aLQBy7YXgMNPgV8PIPPHFmVIzHhEZA1OuVkbi7G\nGFhRIUifmPq5g6EVr+xX9TuJHZWSJJUT1/JUWNRNVOu6XNpNEeP1S2ghf6oMAIr+ISdEeDNZOJO9\nwXy8Rcklo4dPaT+lHianOxRpRHEX5YMO55V6aeibuQKXJRwjgfWnbc0EKoPuor8XUbqug/6ZE7j1\nE7yXZYS7KtOsUnB17h6KzjGFznBVRt1q+84oVWJKQIROClMVT9XTjGP9kFT70snh1O9nsL/grGB0\nfUzU/WoBVRdp0oFtZ26Hk82ha/hl++Uivq8UDIol/hzYkA4wQBuvgSSCvkmMbHWQLfMHy9PjciE9\n/e9Vjgvc9KbFGHTb31tbg4MoGmcc0HGO3raQPrLTnXfdGV3VWfGKMfy/RGdSD57qi9E3wNrgGMSP\nBKiCjKLPLI3xHu2qsaJJ2F8uno+WVTOfp2lZxEBWxLGsES+FmU65TrT1fy5ZCeIeaHQabk/HcBXt\nF1uSFz42aPdTZA0SqK5+4faKUTata+cQjVPjsAADtfrToRZy2d+6EHlvXC9ksn4GH17OlPSdv8pP\nnpKDZ1eaJxzV6D8qqVXPOFttt360qx7cWRYCcFenhFVUpxBKZfuQEW7mYS9lVhghyDTWX5chKYKm\neC/efWFFT30OfTwIwInLus4LYOnj8WdaxW9uNOTfZoric7rUiAhwkJb3wNBW65F4QwRZdlyJ1Feq\nkEi+rEKgRdqli6dElxf6CVDapNmiUshH5HOp/PN/FbkZZxw1EZBecJ5TzDfX5rhFCPZqvWb3T7je\nx4Rg0yb8S4ora4wundEjGAzJvfgGZlpLsiHC/UJe+I4zbZAucVG46ZmOgKdt+Z0m3YhyMH1RA5tp\ngR3G4qTnB9TvDF28GTvh5m+KaTNQxve9wPIRpTpVveO39FeFWdrs/8z/yfDbqaBSyFBkaPFFKU0E\nnjRhobVb+g1SYKEkDZYWqeJ6jOLhSqsmpktl86KRKj5T+ZHI0KDotADU2BybQyijJDyR5TvNLU2z\noLnSh+nuPPP/uQ99UDd/ES+CYINuFbbN5iv3ootOk752D8/+eMepxL4TbjcVeiMJsglorDY26rQb\ntHspGg9kI+tmPLftbvJLY1Ah/jkqc9e9dJrx0Gd2X+zVGNFXtgRQEDiG0HBcACcNuC0sNo8ufju+\nDLi3gbESCBkLR5/Ku6ErOVAIaS5saiy4aDoQnu2wbBZfRvVdFLCJxpISgQCcyzt9/4Ni3fLtQqiT\ntG/HKy5+RvsyDoImtnejDJx1REIWGfd9yxIoLnsb7gSJxk3qqKd1HZJRBpcVjUQ/g9EWWECeSSl6\n4BN3NqO9qO2cEU8Gy59FzzD6Nqet0wfwTgbLbeI1ULxDlaghm2HBKvemR//cQPfelFaw8oT0H2pn\nE5IBJs/LYwG8S5XcAN/bT1DfjGTTPIqkcnCuKTJJPisEplPXbcpn9c5KWjApA4dBZiDuABxt4LRh\n9k0hb3AeHhWXvrYWj57EiwiOlS3XOg6iJv7BKgiZC/UJz4yuH/J+IERjAKj6dQ0pqveXN5Ghp5l1\n1hUwA/eKbHE1h9S+2oItwWl1gxNcmjYk3i3ogZVpSmkUoxeyVDyNTrZviXD9FcFBgUtAGOaEetbq\nZFyHbI1B/VBG33BnvSJ2WgGyypH5ggV7azeAYZ7djam33U8yU0wMIMtj7bTxQWnhhEITSH3TTa9E\nndkI06pkCNH0SA7tahb3c6IUOkrLqxZ+1oR8htcEE1AIEpHTBX4kNQHWjAJIxLC6KI//lbj4hk6n\nXCIYAKrm/P7sFmWEwDD8AQYqpChgDejn9MV+4YQYreP5x71z0l5s+//OS6fNIY1YQqlKAnJFgSiS\nkL8Mop5IvPv1Lca7HioxXCMT+QXJ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protect end_protected\n", "num_lines": 510}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_sde_c2h_buf (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [8 : 0] probe1;\ninput [15 : 0] probe2;\ninput [15 : 0] probe3;\ninput [15 : 0] probe4;\ninput [15 : 0] probe5;\ninput [15 : 0] probe6;\ninput [0 : 0] probe7;\ninput [6 : 0] probe8;\ninput [15 : 0] probe9;\ninput [15 : 0] probe10;\ninput [15 : 0] probe11;\ninput [15 : 0] probe12;\ninput [0 : 0] probe13;\ninput [0 : 0] probe14;\ninput [0 : 0] probe15;\ninput [15 : 0] probe16;\ninput [15 : 0] probe17;\n\n\nendmodule\n", "num_lines": 97}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"ila_sde_c2h_buf,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_sde_c2h_buf,ila,{x_ipProduct=Vivado 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WIDTH=1,C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=14,C_PROBE1_MU_CNT=14,C_PROBE2_MU_CNT=14,C_PROBE3_MU_CNT=14,C_PROBE4_MU_CNT=14,C_PROBE5_MU_CNT=14,C_PROBE6_MU_CNT=14,C_PROBE7_MU_CNT=14,C_PROBE8_MU_CNT=14,C_PROBE9_MU_CNT=14,C_PROBE10_MU_CNT=14,C_PROBE11_MU_CNT=14,C_PROBE12_MU_CNT=14,C_PROBE13_MU_CNT=14,C_PROBE14_MU_CNT=14,C_PROBE15_MU_CNT=14,C_PROBE16_MU_CNT=14,C_PROBE17_MU_CNT=14,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PR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*)\n\nmodule ila_sde_c2h_buf (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [8 : 0] probe1;\ninput [15 : 0] probe2;\ninput [15 : 0] probe3;\ninput [15 : 0] probe4;\ninput [15 : 0] probe5;\ninput [15 : 0] probe6;\ninput [0 : 0] probe7;\ninput [6 : 0] probe8;\ninput [15 : 0] probe9;\ninput [15 : 0] probe10;\ninput [15 : 0] probe11;\ninput [15 : 0] probe12;\ninput [0 : 0] probe13;\ninput [0 : 0] probe14;\ninput [0 : 0] probe15;\ninput [15 : 0] probe16;\ninput [15 : 0] probe17;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_5_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(18),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2017),\n.C_MINOR_VERSION(4),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(0),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(2),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH 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4_MU_CNT(1),\n.C_PROBE65_MU_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT(1),\n.C_PROBE275_MU_CNT(1),\n.C_PROBE276_MU_CNT(1),\n.C_PROBE277_MU_CNT(1),\n.C_PROBE278_MU_CNT(1),\n.C_PROBE279_MU_CNT(1),\n.C_PROBE280_MU_CNT(1),\n.C_PROBE281_MU_CNT(1),\n.C_PROBE282_MU_CNT(1),\n.C_PROBE283_MU_CNT(1),\n.C_PROBE284_MU_CNT(1),\n.C_PROBE285_MU_CNT(1),\n.C_PROBE286_MU_CNT(1),\n.C_PROBE287_MU_CNT(1),\n.C_PROBE288_MU_CNT(1),\n.C_PROBE289_MU_CNT(1),\n.C_PROBE290_MU_CNT(1),\n.C_PROBE291_MU_CNT(1),\n.C_PROBE292_MU_CNT(1),\n.C_PROBE293_MU_CNT(1),\n.C_PROBE294_MU_CNT(1),\n.C_PROBE295_MU_CNT(1),\n.C_PROBE296_MU_CNT(1),\n.C_PROBE297_MU_CNT(1),\n.C_PROBE298_MU_CNT(1),\n.C_PROBE299_MU_CNT(1),\n.C_PROBE300_MU_CNT(1),\n.C_PROBE301_MU_CNT(1),\n.C_PROBE302_MU_CNT(1),\n.C_PROBE303_MU_CNT(1),\n.C_PROBE304_MU_CNT(1),\n.C_PROBE305_MU_CNT(1),\n.C_PROBE306_MU_CNT(1),\n.C_PROBE307_MU_CNT(1),\n.C_PROBE308_MU_CNT(1),\n.C_PROBE309_MU_CNT(1),\n.C_PROBE310_MU_CNT(1),\n.C_PROBE311_MU_CNT(1),\n.C_PROBE312_MU_CNT(1),\n.C_PROBE313_MU_CNT(1),\n.C_PROBE314_MU_CNT(1),\n.C_PROBE315_MU_CNT(1),\n.C_PROBE316_MU_CNT(1),\n.C_PROBE317_MU_CNT(1),\n.C_PROBE318_MU_CNT(1),\n.C_PROBE319_MU_CNT(1),\n.C_PROBE320_MU_CNT(1),\n.C_PROBE321_MU_CNT(1),\n.C_PROBE322_MU_CNT(1),\n.C_PROBE323_MU_CNT(1),\n.C_PROBE324_MU_CNT(1),\n.C_PROBE325_MU_CNT(1),\n.C_PROBE326_MU_CNT(1),\n.C_PROBE327_MU_CNT(1),\n.C_PROBE328_MU_CNT(1),\n.C_PROBE329_MU_CNT(1),\n.C_PROBE330_MU_CNT(1),\n.C_PROBE331_MU_CNT(1),\n.C_PROBE332_MU_CNT(1),\n.C_PROBE333_MU_CNT(1),\n.C_PROBE334_MU_CNT(1),\n.C_PROBE335_MU_CNT(1),\n.C_PROBE336_MU_CNT(1),\n.C_PROBE337_MU_CNT(1),\n.C_PROBE338_MU_CNT(1),\n.C_PROBE339_MU_CNT(1),\n.C_PROBE340_MU_CNT(1),\n.C_PROBE341_MU_CNT(1),\n.C_PROBE342_MU_CNT(1),\n.C_PROBE343_MU_CNT(1),\n.C_PROBE344_MU_CNT(1),\n.C_PROBE345_MU_CNT(1),\n.C_PROBE346_MU_CNT(1),\n.C_PROBE347_MU_CNT(1),\n.C_PROBE348_MU_CNT(1),\n.C_PROBE349_MU_CNT(1),\n.C_PROBE350_MU_CNT(1),\n.C_PROBE351_MU_CNT(1),\n.C_PROBE352_MU_CNT(1),\n.C_PROBE353_MU_CNT(1),\n.C_PROBE354_MU_CNT(1),\n.C_PROBE355_MU_CNT(1),\n.C_PROBE356_MU_CNT(1),\n.C_PROBE357_MU_CNT(1),\n.C_PROBE358_MU_CNT(1),\n.C_PROBE359_MU_CNT(1),\n.C_PROBE360_MU_CNT(1),\n.C_PROBE361_MU_CNT(1),\n.C_PROBE362_MU_CNT(1),\n.C_PROBE363_MU_CNT(1),\n.C_PROBE364_MU_CNT(1),\n.C_PROBE365_MU_CNT(1),\n.C_PROBE366_MU_CNT(1),\n.C_PROBE367_MU_CNT(1),\n.C_PROBE368_MU_CNT(1),\n.C_PROBE369_MU_CNT(1),\n.C_PROBE370_MU_CNT(1),\n.C_PROBE371_MU_CNT(1),\n.C_PROBE372_MU_CNT(1),\n.C_PROBE373_MU_CNT(1),\n.C_PROBE374_MU_CNT(1),\n.C_PROBE375_MU_CNT(1),\n.C_PROBE376_MU_CNT(1),\n.C_PROBE377_MU_CNT(1),\n.C_PROBE378_MU_CNT(1),\n.C_PROBE379_MU_CNT(1),\n.C_PROBE380_MU_CNT(1),\n.C_PROBE381_MU_CNT(1),\n.C_PROBE382_MU_CNT(1),\n.C_PROBE383_MU_CNT(1),\n.C_PROBE384_MU_CNT(1),\n.C_PROBE385_MU_CNT(1),\n.C_PROBE386_MU_CNT(1),\n.C_PROBE387_MU_CNT(1),\n.C_PROBE388_MU_CNT(1),\n.C_PROBE389_MU_CNT(1),\n.C_PROBE390_MU_CNT(1),\n.C_PROBE391_MU_CNT(1),\n.C_PROBE392_MU_CNT(1),\n.C_PROBE393_MU_CNT(1),\n.C_PROBE394_MU_CNT(1),\n.C_PROBE395_MU_CNT(1),\n.C_PROBE396_MU_CNT(1),\n.C_PROBE397_MU_CNT(1),\n.C_PROBE398_MU_CNT(1),\n.C_PROBE399_MU_CNT(1),\n.C_PROBE400_MU_CNT(1),\n.C_PROBE401_MU_CNT(1),\n.C_PROBE402_MU_CNT(1),\n.C_PROBE403_MU_CNT(1),\n.C_PROBE404_MU_CNT(1),\n.C_PROBE405_MU_CNT(1),\n.C_PROBE406_MU_CNT(1),\n.C_PROBE407_MU_CNT(1),\n.C_PROBE408_MU_CNT(1),\n.C_PROBE409_MU_CNT(1),\n.C_PROBE410_MU_CNT(1),\n.C_PROBE411_MU_CNT(1),\n.C_PROBE412_MU_CNT(1),\n.C_PROBE413_MU_CNT(1),\n.C_PROBE414_MU_CNT(1),\n.C_PROBE415_MU_CNT(1),\n.C_PROBE416_MU_CNT(1),\n.C_PROBE417_MU_CNT(1),\n.C_PROBE418_MU_CNT(1),\n.C_PROBE419_MU_CNT(1),\n.C_PROBE420_MU_CNT(1),\n.C_PROBE421_MU_CNT(1),\n.C_PROBE422_MU_CNT(1),\n.C_PROBE423_MU_CNT(1),\n.C_PROBE424_MU_CNT(1),\n.C_PROBE425_MU_CNT(1),\n.C_PROBE426_MU_CNT(1),\n.C_PROBE427_MU_CNT(1),\n.C_PROBE428_MU_CNT(1),\n.C_PROBE429_MU_CNT(1),\n.C_PROBE430_MU_CNT(1),\n.C_PROBE431_MU_CNT(1),\n.C_PROBE432_MU_CNT(1),\n.C_PROBE433_MU_CNT(1),\n.C_PROBE434_MU_CNT(1),\n.C_PROBE435_MU_CNT(1),\n.C_PROBE436_MU_CNT(1),\n.C_PROBE437_MU_CNT(1),\n.C_PROBE438_MU_CNT(1),\n.C_PROBE439_MU_CNT(1),\n.C_PROBE440_MU_CNT(1),\n.C_PROBE441_MU_CNT(1),\n.C_PROBE442_MU_CNT(1),\n.C_PROBE443_MU_CNT(1),\n.C_PROBE444_MU_CNT(1),\n.C_PROBE445_MU_CNT(1),\n.C_PROBE446_MU_CNT(1),\n.C_PROBE447_MU_CNT(1),\n.C_PROBE448_MU_CNT(1),\n.C_PROBE449_MU_CNT(1),\n.C_PROBE450_MU_CNT(1),\n.C_PROBE451_MU_CNT(1),\n.C_PROBE452_MU_CNT(1),\n.C_PROBE453_MU_CNT(1),\n.C_PROBE454_MU_CNT(1),\n.C_PROBE455_MU_CNT(1),\n.C_PROBE456_MU_CNT(1),\n.C_PROBE457_MU_CNT(1),\n.C_PROBE458_MU_CNT(1),\n.C_PROBE459_MU_CNT(1),\n.C_PROBE460_MU_CNT(1),\n.C_PROBE461_MU_CNT(1),\n.C_PROBE462_MU_CNT(1),\n.C_PROBE463_MU_CNT(1),\n.C_PROBE464_MU_CNT(1),\n.C_PROBE465_MU_CNT(1),\n.C_PROBE466_MU_CNT(1),\n.C_PROBE467_MU_CNT(1),\n.C_PROBE468_MU_CNT(1),\n.C_PROBE469_MU_CNT(1),\n.C_PROBE470_MU_CNT(1),\n.C_PROBE471_MU_CNT(1),\n.C_PROBE472_MU_CNT(1),\n.C_PROBE473_MU_CNT(1),\n.C_PROBE474_MU_CNT(1),\n.C_PROBE475_MU_CNT(1),\n.C_PROBE476_MU_CNT(1),\n.C_PROBE477_MU_CNT(1),\n.C_PROBE478_MU_CNT(1),\n.C_PROBE479_MU_CNT(1),\n.C_PROBE480_MU_CNT(1),\n.C_PROBE481_MU_CNT(1),\n.C_PROBE482_MU_CNT(1),\n.C_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1)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synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4275}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nbGT7tfmyts6/yZChogAFs2kP2mbFmmuiFroOv0r8QQv1hFG6JERBCXNBXfGou+8mLPigR5LV4eDx\nWE5VTd+gHQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nCWoEkLQgvsHNvKsNgOsMIlwqULIpu7GrNWea7T7cH++wHThbYiHobD6dcKucCQM5dNGL646pzspi\ngvc21hWZnPx+X5N28b2dNoegtcTB2kLdLw7Lks54cB9DeoTavLfTRXQYufpEksbrNJTUFVb2cNyN\n6BMeJUXHbb0vXcc5VT4=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nFNNqjXbqqfIGkUevtN9QbqDJwQreUsmu9xji2a/w3CJH665OoQqvJUOiq4+1ZDezrG2FheefDlOu\nudQOQzfUbqq4ZB7QVsrZ5+hnOl4+bTdi/FvverAngGvvJSU8+8gbzJ8jtcieV+kp8HrIMv5M1gu6\nVP5SY5P9OIiRMPqToUbAWBrFRpgduuTuMhaHwW7FZmVUVb1j1U3rE2T6UyEel2fueSISKzjAYa8d\nbMNfbkA2ORUFxDxV3b+bBcjCg+jYWECoAY59uutuI1TCRGdhy4DLAvrLFqaLXnKzQ/zhmv78sBnu\n10yEbUQnFKzl5lQwpKtElSrzEVryLPjEKxtU0Q==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nBtsuQ3rIBJ3UI+4s+peHFvk2pezsWjwgWqpQQAOktytWfnh45F6oITlHSewxA1WtBlnC7B06RlL1\nsh5uBcV81aLk24XWmuA7DcJrmhXRSOvl0k4gIwFckG2lpuYtWsH8y7owyOiD/FZUz/LSfTa3Mywh\nD7uNSNvKmmqFP0yIDB9zQtZJYDKPgeAlZS9NUZdzjF/a61kdekWKbPaCmwFQ0mA01X8N8Euy78Cm\ntwhuK1u9d5vu3NtNKQQjzffGoOig7AOKPE+KjZrhCajjfXLjFewajxJNXuRqE4Qr4GGCy18JUK+r\n9AD7YQrF9CXYq3xjR5zoOedNXXQz29GC/jViKA==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nGzBT1kWKJ35ymgjppXjhmBsPZAh+qqs629kt2BvXZjQHKHWH3WuilMysbQpFcvgaH9NxbR7qFPN6\nyb5XgBkpZDUCCrc6p6YR51wXM/nxNvw23FSNPFKjoFEw2V83YYFxlbr75lWeNCQl27cPfBPuxaSV\nIjlxIsm4eW9SkxEnTQqMX5ySy4IaL9yElffDeFxfvmZFrx9lJp5FMRFsWvs0CJEBnPV6KLu1CvY0\njoTQyovEbzWILZvpO6OoWWowRhHO/ukpDVkTQwizIuNbetdcKud8UyyAngECUSjve9k+rXX41zHR\nrDfFrjZc+RPg2YpdeYHykcsisoZ5sdzyCy4T5w==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\niim3M0ZIoSIeblUIY0hk1kn3BvlRMe2uVKS16OYK9H9BGNvnKistWqz2WEU4s7eijjhhkWdw6Rx0\n1TXQht76iCER16gWcazz66/Akg5MH+lOp9NPf3J2iEV7LK7f+3F9jgvrsadzyPoTuLecIoWFoNJk\nFXdJK8072alT4ln/U8w=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\npJ/yajVXTo6y0FFyEOL0HIGDXa+xEims4jF/m3KWWifm3tyRZ/Qmr6px8fbYo6wt98IysxEsBMsY\nOafake1VkQe9IEYdvl9w2pbHgnMGCgpFHt5GVkkx9kTM7g8X5yw1cj7dCjsuNtLtsSeZ7wW2gvp4\nba+UNyDRcpm3wErDehZlm6QU2gigOYOXUMH6KQLyei8VsyCUEOLrtDfoDMEgbTsPan0OVwWZ4Yma\nBViyJ567bWm+BUmLR7HMTK0+QktDEmFhL5lWaTS848MSM8+2esUyNGdKKutfcQWcpHUx0GkIOnS0\nlZ1qTioC56L1NI2aXWshT+ZrJgi5x4ZYDqF6IA==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64336)\n`pragma protect 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ikj4QY9qy76XYw6IDsQdBnIGtPSFwxd9wChRjkni7PaX9nBoTv4Hkv4/X71ms92d\ntJ/07jLvlYIC/ZQu83ENzkpZcQxr+WVAlk9voN1Lh8MJ41Cksb/e82lQv3tE0i33RVWsfpzzkmhl\n6+iCuWQ09/k8dS0FyYp1eOOSakJpDvCoKsuGEA54TK2SkuCKjd+GAxav426xXnGAV1GxKJw4LUC+\nBoIDk42kjGmgDrTucR4D8ebhRKZlfSndBkUN1MxM4jhRdlUOlo1unmkpDpwboVbaBL63n0cP4G6M\nMWgaQmfg3Yi3VurtkG15kqklP5W2hoXk4N43ho9pwxbkiD0fB7BonN/w9HJv4Zu26k8JguWWER+r\nF24R1GsE91Dl6f8PkWleIhz82kPHFEq5RrhTesz5mPkAh4LBNNYQcbTVLlK5Bz0FGVt33lgt9zoT\n1OXASFCArKzZWd2y0Q5uZ6j1/oVxBrIIV84Ebwg//J/PeKNV+7dWoxdxrSyxxRk9/vGvVL/UxkDL\nXNFXWyLhbVlxG08uYDNL1cw4o1C3ePlskKxvHjLKaClc/79HN04C/k9fm51CrfmvosEcGzKhDPBj\nHMwFxAT3Pw83gG0A4Em+qHW7Wk8Bzor/p/e6kDCX2WbCTGXt8ZMf/Cq6Dryzr2sDHKfteVQJ2fpF\nHC/D0b26BUXdwRPX01IK0w8qiZ5/xcJUdwszggylh3pIeyt8qnPlZ1xYYH05884oekPtILD0GlZx\ndRw6hgHq6NYCifq33HepQkocmMaiBik7yzszAuKAWn2x5Raf/FC2GSRLb3itncwKnJGL7yYaSZeJ\n8OUhkMmGPtZ8ImThhDZ/RWkOBq+OUYnTNhKc3FmrCT9LsMzW0ZyQ9o+VsZv9bTJ+USliatHl6PD/\nLRypXj3clKV1a/C8C+rxwRip4mEQfKcf0UiZgBr6eYubS93izNsyymJ1mp/BMX6jt+kcmR3LAEE0\ncpyyOM0mIgNkjmJmLmv3R6jg/bPvI2p1N7/cIyybB4G0BZtRYMXRngfz1Q6EMQeQVsUna9iAjvQy\nAG2r/xcgJFufo3kkRGq2V3bTmOg/azUFNjzL/9jw4R6mkP391rUCjjKNDXYCpxvDS4Ye2p86OKcN\nXM4s+2bmJRe5JMBVj+0ZHS7ii0Mabn0ehWpoyMokVNz6dMpxel4glyyMLn1uEeaGHRDWuRfCqrOB\nfTnvUVJz1HNeGj9q7pSndbVygb7ZUsG8h3ZCkcyQhLOw47qwv3lDHtO77/HoYY9Tr62YzSiUh3z0\n9j8wCnOkMiqstzZ3iSyRXlGTQ8cV0IIcZ4obZHfQfj7I+N4MXnxEm4Pf8DHrXxlE0RxiG3MLn8Qp\nv1AES70B0p6TKWBC7H1cOxVI/K1ykT6KjY377HDe//18VNIC6IlFJzNuCN1q/+iLfRWlGy+uFMco\nAuFhgOP9A77fsu7sTi6ay+PaHjwC+jIiDGXdUXLPAJHxpDQzZfnDDo14bCy2ZRz1RWNEkUkLH6tY\nuGcD3kggbTyfoEOTkCtHzmGI7kFz1z7J9DYLueA4OMGamCdMbQxvlcUkwx/Yam/jPH2MB8HtyspC\new/FctHMgwthFB+FzPoSwmv+vsUZD7p8hri9LeoCnXPfXS7B0PhDyaHknDkaPDhEol1WramhVo0u\nGKZ8x1eDO9ipKqbYemWHLiAhYr8UXDVwN94diYZ9VcYwIrwr1P2VsWG/9O+R3rFngUUFk8Z4Bvip\n3PBfNVwE/QWhb/BgkmHeTvSayZckM9vCuruECucSChqNjhhIvSGY8CStQKNM+eK89IlUPsvIBY6l\nRZyKERWn9mxbX4ormBumHi4IznKEziX9fRRAEGW0uSLFhi/c435Qai4kSdBAoqvRTsu+7pIC8yv6\nmZ3UTSFrP9ATOE0GChYyllkCW590wKjCJcVXcdotPCuG+4IkqGFXeEYFfkQRLFX5drsg6AMEKhFl\n8EQOwjKQBjK4HT2f4vT4b5aHjEJ05K9SP1v5aTcX90VaEP5hR0OJDY8zsD40NbAozDPvBHZFX0ED\nIRhn+i/XVUxf4KkXcZ7BGUHiQvjXmiD7rd4O0nP0t99gvs5eB1QqiK16/QSY+J8Hu63WZWcdZZAv\n1Bl0sb7QjEa1onPN6MvMm284XZNYPuENoTvl84tdVpwWTTy6KaFjMfpGvs3Zw5rbRYjDqMU6FeLb\n7tSZ/ahWSGlsvFIWoqELhastLHLkIeMZyt8jlYUTAGEOEEraoePUOpjacUg8HrSpHie81DOaay7P\nAAzT/Is2R6begRrTAGNPq50SNgzPNmJomzUDHxlbuHeJYqnJzbTNmu2mm/QNIY5g4T3/ZUKkVv9Q\nrDjVCP+lEG/cEUycZ1Z78nVFuQWmcsM+c+assi7pL+uhWZzCPQizzj2hiM7VoacDeeG1IZ5IwMq0\nXp2/giop0Ak1pp75BsLEDXdzpcD8l6Gf+GZorCsODJ9BfSE12ihwudD2D7osjC/C/bUYdsrC/chx\nlQYFtNBnmCnTwsSK1xoevId8Y2WMMdNPuOhUUHqEtFNHL4EK/KM3VZU+CxrDDhp/Z7aMvgsweO4e\nFmHhSnvDyIGqCB6yPNMXL+UsWckLz2OL1rLGupkCvcfX4pwo9bia0CTK1ZkU5mrPXtvJ8iLvH5ZD\nELwT4RUG2uPfT9F2VS7xhdsTOj5USFtL68jcB4lQ3LdUwqMunj+M/wFkRUsc5Wo1Rna/htuyd3aP\nmvR4afocTUND8sbqWF86oE0b7M84KSsFKWn254Yv45b/7AGVXhW/zTIDhey6hbDDHa3zUhsRJ+sd\n3a7q9Kv9D7ax7QymetYPp67OmrE0CctHogPx89wzVtGxxpSFh+PSbv3u7EfYVFE5UV70g5dbWi52\n3Fe0kbBYQmCR+aJTy4hgxK666akTNVD8jx6UNgpOeJ9oLxbdi9gaCeP4YvldmkPNuv6n5m2SSHCN\nysHNq38Ri4NO/g8LNN3ZqRaQeeW04n7wNj43g2u7Q+AhVjNDn+3cUoMWV0XEdGhAlsvLAziOS8Aj\nAqOcs8PgfNLRn+/63nhr3S1tpn0oiSKA/UymFDp4XkFAl/NSQdSlZdl9yZfocKZ14yfbXP4naSXw\nYXdD9IJooJYT4vc3XhlNgoWURjW+vzbrQ+9Q0aDVLGwmTPWJcogLZSm4kAy7IhXy2y/e6LLI81FT\nbGmZxodxElq3jHE3z0CJEqoS+gsdBtdqC9QTMQaetDKYZvI5/vmZh3QKAamIvXVJ8TAgO+OxHgFd\nFxrvt+kVuLs1msjlkgS8mm8zfI4owlc5u5lmeVXtyCNHPLKHYAzzMNPW5Ai1OR6HoLM6UG/N2T34\nIXbk1QrwXKk878mT9EznzAhb/4bv6hoFEDgRIvCyyYweHxvzpmEfLiP6QaYNWWpO7iR/eaJHWw/w\n790hhWcg44VxliUVIWvozPbEuqHwxbBcXeC5Ksuxlmk8QdBhjHjrT3c76PX/AgEVe+DRzjzKRv5h\nMl6B13x1nZfviHANI6UOudXTe3BSkKBQatOSiKX4yGd35hKnuRYnDSNt1mYXH7lATfmjJFJ1TT73\nWSe0PhhtU7SE6IFs9oBDUTj2gUo4sKYA4alF58i9FJIqvxNGJAiLHJ8E/+pWe+aWwISfrECu9G7z\nfL+1k6nrcGpAegDvvNaMk9nvrHO5U8w3cCleTCuOdPKfWUgRuMapzh4NZ3PMrh8SXD1InQrZuBr/\n9wwsVObR2mdCCdXa+rhcQ78GUFqAhDlb/gDGwNJXRHEtPEgwsgr/EIIqHKun5yMnH9RkzScVLm+J\nhQtsd+JNrs4PPnSzdYGRKsNeWR1uZedxdvvmQuK6V9mJ1/9Rmqx/+sHIBiu+E3k4orWWGYdd/T8M\nGKqyT1rmVf0d2BrSPHzAKYdcRuxuewmDHbGVC3lq/yp65QOvQQO7N1EnY1gqIuYuYDxWjYKeiuwP\nQFDZvr5e0iMckylJHxO2Zkx+I12SyzSel48QzIAVnQmCTJ+X5gndrUh6LnLPRXJ6+tqzD9dfe3fA\nlb+egkye9h3JlbY+3Pjc+50z73r88qa/PpdTLyGj43GkhQTcr/5gW5n0AHoRaXiFYkNscs0Nos39\naAH1XRkvy408nbWfa2Gi7jxH7uI3+F3JkxicVp4XMzt+l+R+Dx0jSIyNA8oHaGXR7iODXmIVoCZV\nsxZNGSarntyxgE8l3LcO9FCL/iMvzfprNsX4JFDepRadUjspZB3K37Rtlr8GmaLhjZU3JZATm0vv\nmoZDKTaGGimpaBiPWWIIg5udEW5MYhrK4QvK8iJiuFcjIg4IBX3XEXi6+aZluEko16/4dzOkmd+e\nlZ5Dld272oEIa31In6knS3GnJn+b1p4s5Hl54tgnvGpXSISYPWD9Lq75SgxS/jHTRboTU19NRWhU\nGZYbeD0sh+mVjL2njjkPKpQ+0YFlelzdofUpHWOTVgDIGUgPQvZBn42WfsNJ/RV5TtsMZLjKLxaK\nKCX8wuFnxtCLoOUXBkbbosQYxnMAy1U44OrJu+0HOBqsrwNh5zFGJ/zk9/5utr8aQg/2aGimsg6J\nv7HyvEFEat6XUm+SLNRb4egTjBiPMHtEUqQzXg5WFNHpof6b17s5owPbAJDewviuC6u0+/FBomnn\ncjdCfOBsKr5oKtdJ9G/cfWevYkjMPzom6RgYqWKsOT4oXSsridVr9YSMbqMjs6TQyI53UUFHfVrF\nl0ryDtX4aJ6oq3I0s1jkTBQK2SVIvmMqBBreOHIPCFKB9G1cVT3e874jfndchxKWHYKOtVIJFav+\nL8Uo1/AnORfpmZ3MT04TOIfAJNO2opY0B5YuzT3m9m+wiD5/zMo6PmrcJJ3WVBY227wPW7hMWNNn\noOjAzzCrYiiO0/jDCB8OvnLChzLzTJmbwJe4z3LzHUGQQrZK+y5Tu/hI2S0CbbCb5l/4CxcADGOZ\nuOemAiz3WmIs6bykPvKCJ3YUD3M4F2iFz0Jc9H30enm5yuyqcKJoLQU5EWDirhIaywUHXRLN0ibW\nopXtRRfHpNK3lMJsLOJLnG0zXZGCJqyTj3qaVPfuys0B3+EBk12yq5qHRl4wt4HdS7zjxXqETTCS\nDWmTnT4ql9Ls9BhQoHCyeboOSARvoJCyg5bUFY4+3V+0E88wVyH2mpmkwGMTO1U7hbxtNJeZNcQw\n4x29DNm1Stga6kl3x8cvgu6djzr1ZOQOVMvIglT/BJQsYwV5NRK8kEiN/JrcDmE4po5lmaqOrEEd\nHnLyIi24A9t/bIbw350lCnc78BGA1Sk896A7Q8M8RbN/bHcWZcBBVJXli29+Go0U1cZ6vjpF4ote\nR7juv/pOYnF6fJkTyMQwM+5vzXEOMm7HcWdYRkQ7D3BbHuSVrhMBF89SrP7kn+SQ7CMEvfEG9gkj\noehWcUlTOkAPgQk+upUfEQ1V0IXIo+XGVCHXw1HlEAli9rLRlvLn2t99tZVdA9gnXSWDnaG0xm8R\nLth+31whyvvqwX0YwczoV5ZcVxTocWZwY2x4rKKiN1sDJ5PCIH5NrEMgJS2of6yaSC59QyvehjBw\nrRNKaNn2j7ZVpchE7btRVq+TWFqRMEnDj6B0wiKHy9A95fPH/jFUEg44Wgx2iIrKPooK1JfFJjbe\nTFsVM//5ug78qIzr214qkcwpUd+Zda7rHkJwxj4C8LcySIdWlAhhrFv5gtSCqrEIxbb4dyTvJ3v2\n29J4OwnSmjFaRx+7TxM4bH5xZBPQ9Aa5XDTCjtMA25CHWN46dF58ljRBnuxj/sTwdaqBLwjLFC/s\nAkRKeGbyuEkgZDGkgQ2uyOxRytYfZgUOGXyYAlgT4iE1lexh5KlOeiAzDxJoIQpPoMWANujOCHAv\n0CCpwPRIDa+2RYtlmvxXnQ/d9rmV/+bvuLlyg/PZfyF4lTfQ+gT5J6linBQ87uSw91z63GevX3vQ\nqIXoRUlm7FQIt6H+l7ILegL0BuaK/5858vbFl7BmT0xi4xczqNU5s5sPC7Jc1JhCohsjVnHvfwY2\n8qzZE/wJGg/5VjtcQrrIsoKjKqxGlUmOmA+gdWpIsqYx8y3lBO3oGE6LdohlPe50Ww3ftoagW1cK\nDi3dli+FTZBsGvAg9jehYrd6aHzVfHf2Y9oH7wo5VVoihibkHkzqoQtIf5kh+5qyhZ+GPgQhBdpC\niJA246TRn9v15Fx0Zn4OzczQG20209azn2UqWQULiPUy0AxceMoKJoI5ebd/IcNXjzH7HNmZBafC\nqmkvrkIAJJ1FNjBf+O0QphrrXFi8bHblHGOPHvgNOuyzywWWqrV4b4ppE4J2k+8EHYdTLVKZZ4Al\nYZ6gJSjesf8kxIgFcpqWikpTVY2Lip3rXeArsRv4MfC5Cjm1TjSdZAhN82oUsfszt8WRD+zl2+Yf\n6uRI8rD7tjXtB5A6MGRMrj9OUEXOgZhE4jqyNnCg6ichcoBhMt6I2frqhye4WGXAEMLI6vSDYRj9\nSnUdSngCYww1VjOT6c5zDafPzD96R10ddX1dvw2srvEC+Ie2efp5Qbmo1aa5lIQ57nk9WBJJvgaG\nXIhje8wa2mkKm5xLGWe4Y/yHPEpOwlPKyb3PhHzx+zIGduSAlzJSD+OZsJct2O03JrLOTWClXpm6\nN7E/Nv8Eynggtxy9yi27yj8r3I9F2I6vcGjNVurnmPRazqa6xDRN5XmvoZIxhaoyc22aS/cA2JTZ\n+yitWSfoXkzAXu6UL610+zmV2mfaoN5ISO0E1Wx5BXyYs9W4io4v/Vs5fF853UcjI07FeyIHaH/8\n633CANkUvI/Ls+GIu3A6u55H4++25ow4UvCUUjPyjgbvM08a25F/61H6L+v+hRkxKtflljcz2yFa\nWzu18dTrzpB6moutKoGhVnBhkISm1U8JTlUhMSkcwDMRjb+QWWk12wexPsUG6Klj1tbVZRO/kCWY\nBowdwm2TW2y2buml37GpNk8DTcKnOZBrPm9KGKJ8AlE+UZvGwdmwZM4ppd/KPXrDRTSAvtgLzqiG\nVO0RfMkmDngv6DSQR63QVXfQ7X1tI1VJcSzIp2FnlO5umBtoXaQr1f6iQLjZs8mHKNN1fbisbV3L\nkiGCuSBWjdyaz7i3nnyYk48bT0DCaLmk04mdPsi84JnyqcWa5HEqD8v1EtfmKP7KCxyqvL6jrGdr\nY2QrX1loreGJp1YQyZJ88Lde9IZlrVYG7X36FxaYuiTpVwyV0lodctAqii6guogpO85KUTYtLiD8\nz6r1LkdsS5eJtVm1N0V8qPJE3B7E5O9Eg3rSsAZegNJwfXmz0h/KOL7ee+E9kESRKPAwzZ1eXpjo\n4C2PK+Lp+RhF9n5kn9ahWn98OsYboOQ/+Vlg4ObgQeIu6hzKJ9jgtuWxYVY5shh7Jrt0uV7Ozv2e\nvnAZTy1CG+AMaHYhJVCrk60hH2jHdkHlRGewtI/rVzCQphSTu76+MqrhzPFiuWNwGvg6Wkz76LLd\nhfcCd+meSIE5pccdbl+mARINHJz0MJdp+AN9v2UrsfZHTUOOa197dKapTQboB938J0Vm4c9r5xEC\n0WRR7MoCZSLvTdcX9g91U68eqZ7aZgO5/oJqod9jh9AZDcjOZ/IZEEUBdlJN2ygo7ddcNiCIpE1/\niePuIMRKEXOabn+Jezy3oVmDxGLZMWCmCtA7SlmqKl+bDtba+c1jfk3rwir0Gc24AQTl/8/AiX3U\nhJTblGzrePrFEtjyEPyRKLCey9jkUXrRCnIJSxb3niKARYGPop2ovE37z/rUVgTWkWj8jruVtmUk\nXDa5ugQIukRCNmF4DRWY2R6KcBoaHm5VD7WsYZHIJKP4fX6X0xUFhGYGx2gj4VlXKa6ceqCBpmlR\nY2Yh5U96Y7N8lnKjQo/1tCXe7lQclT/F0y6KMMUbMdHp4fPwWIyBj8PyvP2F488jZKoaYDcCBAZ2\nFzAB5SJ9UtxvTWJ2r7LOFU29HmpRsScH+gg5k8G/675wfProbnZ3vGj83QtH1cvEl+BkwvWj05Kz\nu4d/mYBk6otvnaXixVDPAz/V9t+eNvXRwVNJ3mcfQ+DzZ8EIJ/yws4jWIkiSofX9OxpLH3L1BbA7\n7UR79P+vuAW2XLA4/voxPvt0BPlz+7oPINnLbEnB3HVWY4zM+EgWeBPAvZEkq36WAZhUBBNguE7a\n8RtT7QkNQq5ZyDg8G6KuJnpx0w+cCkCHtGWTV8maNSJha8Bnt78kTWeN+iarpU9NOyzxGbh3tniz\nfdzfLr9gC2z7ZDK1D3NObjjHSgBGOoPQ8zbZNjIRvY+3m6FqvjcGFJw4v3EallVzfNEk0eJgbrt5\n0rMp2kwHVSf/vfKqjcIHeIC8D8JG6DdmSQr9owY9/HqnlzR5liMglbcTS6FXDgmcLu+iYYFY28gi\nqFNSo1na61Urj23WxbaWilZLtC1U0TU7gS7GCuctgPqLDKFO1gglsegQThvzcuC5bwEwRlU3q91F\nd2p+3+bdCCne65OxvO0ehShiW6Lg+NgoKVG7qfTwiYnE81HF0ok/tcaZNbE709lTsFWC5fIF/MER\nVg2+dV7U6+rJIRf2tW/Pwavee5fm7VAUPC12UC6dZaK3h+YowDeF08FW2raiLFxqZjDBI7TWFZ0H\nlgE0OCIY3aNCGDGD5lhpZXuu5IHqEIrSKrM1p0vl+PZUNwzxcr54yP9/GvEGNovVn3YSTQaYB3yU\nMdTUt4B5/l/48spJ9IQRZJOHNqo4sGuVsLADOy/rNUTcWrlHcKgT0DiALq9k8rvybuyPaMmTKkvo\n6QP1WR0m668K4o1bSzt0rGulNFO1jk1Dp6cffsvGPPQdaLN/J3MNpUcjPMOpHBLyGTB5OqG/4mjU\nGR0byR0Cymms9sl3FH/LrcCbOEyY8FxsvPhszWsKD+co+nol2ncq/5AGd1Yj+E7pPniAvEi/hEuc\n4OVUmFlFYInGD4BlOQ4z7I+0hlGZFj1oOTrUsy1FU6g8j+6m1E2quppZMIkT8lgtWyT/mG+E3j+Y\nyTjtYgsbRn/oerrBrKpvvS3drB6tNlZMZrOZYn8xWzgC3RLspbE8JWwrsZom9BJG1f5mNF2P1cDY\n1foGVSlP8cZisVdTvgY03D/ummRYd74ziD9XcdWpWqYWeCk9MtNUuQRQnisPwsDyf6Iagbu8mRNh\nn4FglPLDfVH04Qx32QoA6E6bWyHKtStBKy4F067MkUQGvBIpLfKFxyXeG3zDRkQuj4joUnzGTPD6\nTFaSLk++kWojfrkMMF/LqnQZ4evnUMmoTH1Knr677TbVuDUTS2VQbRSGuo33/AnFJJ5IVlnIb7JR\nvdHAIG8g4zp0ZE/WmWTCIuOdEGmsDXsBGbtZJQbVHPez+8LOcItfUC96XH06NYNEZI/mH1wGdBNz\nUbnCsAnd/JUaDNe5hgGNc0aDcDfpgNVmPPTG5itNB1SjFzSZbsw+dqkjOYxUxdgxyqlcA2xAz5Rl\nnWuA56Icpx5LJgrYk7NaUiCvbiRjQ4JVAI3UQfibmloLegVPOu0WaahNR5z7gt93JISTsBZDOdJk\nkUX50GH3o+E5y2s5uQtEHNVzT0/VdOuuolIpCU5aoFcrFR5cuklmtaXcpJn6CFDQa1YzjoUaCnKe\nnpeJymF5dt8FbhIpA8PSuo0aBUq09MODdh/ZRaotvwLbYMDzWQIfKj0ndZV1nXBFjD4SQ+HoJ54U\nunuE4OZbTfvcC7ViY/RqV+Xkd/APQDwMfey+cXxqr7guko1eOqgR94FuW//L9CD1ZKsEvXpmRJdX\nBqYyUW6GK3akL3uIfIQCFtwyGi/BfEVu3rAbR3yirvflkC2o79Wa4BP+zh3tyGglK0Bvli6iar+A\nX1DA/dkwf4OqHuuG59dpNE4p/om4LMJXdl6SqXLhI4N5WxYtX2Px7ooR1NSZJl53yzBYZMOuzaF/\noaof3V2t8hYmlrfqUyBusIMDXGV41H5pi8vusj2z+i84D5mMz2c8T98Oa1CJKdCY5FXja1/TSWDt\nD2rNXOtcZgKzLQudXyS3jPb2TCMq3jOBycBDFH65nKAyGIFyeTKPn6cIAJDkBuSl+0bjUg8pILwC\nNmlAfw7DE+Eiq8aseLP9HhlVRm23B66+ryPSlSuUGIVmrtKKhWS5OKNDEqTMGEh4aw2sGNVVYvKS\nKbaGhWe60voQWV2IT9vuouA0hlv604k3/EwY0gODPnA/L93YelofcHaEhQEVx7iesFAVqq3KF2ue\nfKECodO8wfwW+RnycXayyuWlb2UnYwFI2AUUGCWpKShmVUarMlQKrWrIhTbO+g0vXa7E7zS+9fgJ\nWObDboS6oXv3rL6aUh8CdHvmYvR8QdSvfQvK+UvouZhsqTiycdhIO9oHLN5xkd4WWxloyOWerSvq\ng8/d8gOPzhBtKlPnJzkossrJkFwt5Y5+O5X12/+c6/n4WD4ZOddoCXy8i9kTQ3C5lp207Hh8bOmM\nea5HEgG4SoKB7kJtEIB1+5Ylct58MZUcUaHt8DP+uWNMSnY77vn+3RQm095pjevy0+URNb+7rW+4\nf1D/G4xH/mtDeKGQGekaf2e+KUEiKVb4PmHoTINrx6Pv9Vg01K5cEUcjJeCDoKZLy4NJ5cDzQSp0\ncPt7sgk2Up2jSOfivtrO0Yt9UzS2JK9RnBrxR+jG0sE8Zbi0U2UceMTAzYtt/pXz5RGbTXlxns9a\niforlRb+rHpcZmBqUbX9HMaGj3A8EC5aSERwk62OvM48On0A0lfW7ckac9U7bI2UeHUVkgbsLi2Q\n4mCjKZsKM/64VwaiUxvf9D7mLGgyX+4UWKpzdIXaxzIjlaWixYOcJEkwDwe+8BIlMru9C2uZ9+MR\noI4sbmHJOyvASFf3FlN2zZCEFPPuHoiN6H3y/IZd82q3xCaLNiMiNxMCRUgIHFwWdHt5r0lcTTdU\nh/TssUxGaa2KzM8lEo7CUkgMeoU8bWjB0DkaSXtusExrM1uNSd1l+eZsOMX7qzzJPEZeCatCFhK/\nBkWBpVm9vF4v3gNfhsVPSfkH1x/AbGjze0ZSaPJiPc4r7NcPoFZE1nIOIBABM3sJxT3mv3COVn+M\n1O/O7vXVwaMnugQOegqaROMi5zZn6fGJzhh8/8IIifmBei7ylRRqhJaE1IqGvLY8iw2CFgUbCsEJ\nQTppgPJNm59zRAa/4LWLZvs0u+wssdq6yRTOLomawCTb2+YSrSm4cBaef2FUqaY8z361WXyqdFpi\nCbmgzpCBcYWBcX1fLlSDN0FTptFOxlVLEmS1xO2GF472l8hQLEqEV7vfJvno+Z//8TjoVJ0mPAT+\nOodKgQ7+RnJBzAHC2bdAd6Wr5Cs1KYmxfeO1w8diEQk+7UEYEUfqDWOnhHM12DPdhcstSug+kJFe\nriF2f+ULJp0BKy2kJ/JJPAGRt53i1m2+71io+LzZha+RdggjfDKJr8EonB3mJTv6Ey/YxtD7/aPz\nsM+MIrZOFx4as9lBSVDYwTBZMvxLWLSdJsX/hZ8uFDZQxVyFQxfvrth/I158LUm56IUJcIyHeitQ\nJFFKCU2sw7McobUMR3H0dnKt749a5TFcp6Pt9OOnS0Kj2ZJ0zW0QRSFoUjeqWSlfVCVDBR7r2BpL\nG1tjy7Cqfqv1o53HItNjtOM4y2wZ53IpX5e+QjWiKzzYm5bi9Zw0sqCkhWYea/Ikvaaj5i7a+N2Q\nGUDekF0yxvDgpNKLYReqsEnViPjfOthZsiQ/ZF4f5FZkimf28UGqFSCYBhoyAoZCObcuokDZHSc7\nqbD8R5YbQFNmIhBTfo+LwHmZS9/r6GTAHKzt3NdOZJ+BlaPdFo9LoXpZFl7BISoGQNZp+cqJmxMX\nlElx0u0GPPHTNt6ilQWCwLZM9xFAQ5dH9aplVb1fFAdsjXUEJusNpQVa0ohBX/MlRqEA/ok7gkYU\nRg1Sl+gij7mTVCyaeKWlDR08H+GjsgnqBew6ptWyV+BLqxz1pIwS1TPPT9g2LEF/AXbgalw06Mhr\ngWyomNUgaddL15diQS7eKVlYwVtuO9Dio3USx5ootyq/tTQhrjkS124tYNG/4ozFsQy8kXW/28uQ\nVj60rTnm/QkMkD33zu8zBwXYOZ6+BhuSbsTph+WRnBagf9hxLJXfKYBbTirzgFHDPcrp6unySw1h\nXerYV26lMrK/9VrkVxxsC8LW/JGxQG0PHDl1cLs6YGseHZQa/ShX8XE7AtAYkJ56xfWkYduswh8s\n/xwWm/i19+VTuedahTPvXTRWxxvy7nbn2xV6LaUFixHNVy9k8lKLRdXzpNX1zCe2kB53fgz6XHnL\nxhN2WaHHuNFzUWCv8NghHah9YgCVwcCYh8YcQrqbuhpjVm/NprIxoZuqSuN1xRy/zfwU28FCMI0Z\nb3PwLG7AvfldFgTZPwBIWcODxzP894mHaNG9itsQjhW0ksSSxvYweLBofWtKhxFthCxXRjQYQlAo\n14uDlf24ruW2lki/ARokBEZ3c9WOn7xG+8a0XIAMh2Ze32MFWm50mba6Yk0jKXF7aZbfuH0MHbk7\n9U84WW80Rl7zWp7WK3mvHdR8kaFAyO/KFGsmPo3QwmBX3cmq0huPQVvvq9BjQq8b6DVoR0HRMFh6\nTS6HT6Gw205Po+wLRbrwzwbq6pUVKfHCySnZhHc2j3EXi1QjMy/UoGuW7bFHDALulwEzC7c4N1nP\n58hDhowIruHJ2UgjnpJYzV99YlPGs3RNfL2D5+uUFvkflxDXHnH14Ay7+zHIxr4HvncQGHOr5Fu9\nhSc76XDHb8pIGd8IdDD2aKLshPMrNF7ZVpt0IS/ThWkjpqI4HAwa99Oor5TJGkGnrK5nXCKl/V4U\neaSxXvHyD26Ry4NGBk2JasO8VqLSOVfuemwekAA795kOriGjdcU0hRZS0UK+YZIbt5M29s5xxQvn\nZgNF6Abotf57E+YP1F1eVCsopFPKfvATEpYTvUxBFxW4h/29TjMvkq9uvfS6ys+XhHfCrVIsAwv6\nr1aIxORiIZbULnlflxEryS///gUFpreGJpoPgLIzo848gKdf1bu+I5g+bikGAFcVIi27P74t0Q3D\n2+8X3z/i+DPkeMw0IwTCCxYpl/lnyV84ZlOjbvO+yak1dW85HmcOxI+Yx4X/aTWBxL1E1JUhsXny\na+5tcHCihqtH9TJ73Dz1Ctb0OQgLEcfPmziIrLrdgcEZv5fWYBjEp1PlCpqXnSKJik/ADIM2x1ZS\nwTuWTrBZXoTUnBmLXJvXwMOS3iK93JnKWLmogkAwQfj4NpYV9rRnNTEG8OtcRO6x+ScjxM3q2WcL\nNxMiwGOvrqy1PNsk5tqJrr+C/vX12LjRSBmKiu6xD3m84Sfo1ACMuimkJwSHDqd1FhpqLMWkEHd0\nTlg38sEgiPxPzQX8nNNDU+AP4ONfUTzkEdOKcKZiBzccH3Dh/3hMwpWY37LbN9EhqqQ6iS69/Nff\nI8jj0x7Ekmf6ZhNztfDvMTrHdMA+xBQdc4cL3BT8LiOLzDV8rROTTFwn8nHNro4jnAUqYf4sOABW\nwXiNohg3LLOwTe7gQpSThqCx5mSjmdOvwSEZXlSaciS6BJC8lgM5zJSzOURYOSMRl0CzfSVfiPjL\nl2lYdpYudLJqm32t+mntGbSc1wCqRy6djjjhFUadcHGBtn7ZMpcsGXeZ6PRYLYuWEiFrcxdeCBSJ\nMa6nR+aAfqAll8jQGr/c+1QtM1fgbtgUdnqpw2qWuRmW6LDkmuIxUHDJ+RS60L5zrYrgI27cYpEK\nUMcf/Dju2oqap/yP9KN2nvWiK6+OwAuvG22RDw7VIX/YU/KvVgED17M9VrSaGN8tqaHzNTGM2IDV\n7LGeSz1D15I00bC7lsM2GgX1s0o62Iwj6j/6deZ1ZiCwBtmmGzh0KCdzK/qSxCMHjC8qBAR9tQhk\n4mPouLUTQqh/4hTq4ku1SbVCqI3ZkjKytxnuhq5akCqQrq7Xx4JIaoeSH4sVIsXN3sfWGc7Zdh7T\ni+pQhzqsbkDGV/HO8zi1aJ0mPesChbkgZCI74tqxqtLgFFdUJepfQtEynJ7h7I8ZkfjccYsS3Ohl\nNdLTLxug/y1cWwWXQSU0L5+Z5ElHcoJH1LfwaUMungbZ1U5u/8Nry2jURK8LFHaLT/yRSn4Pg9fw\nuejDkeRSbGy1MMesbWXCO/uT8gOA9JYa99/xwuim3E5zGDUMaJWKg8WBZVyKEpY+KGjBFJOUrtMj\n3rcJNY9d4slEqcn2wDzuKUIcttvsC70XG0awDYSDQz2CYfHkWS5/uSF4ALpgjLcBzwC048jZUueV\nviWS5VudzFvxXLkz+NbWjjiE2B1O4wAGgrcimGJyiRUvU1wynIl9r0Qqr8iOCQSA/p+8qQ+0ZvY0\n8OWok9uq4V9RixaeLSckAEEGfom+KfvqiTv6AE9kw5848t2IU1HTaOCavLmA4A72Vd8XeLeqVW3U\nORuyyYkVjVxZLFIiWhx6jaF1/WT5jDluydog4xcvKVb1cwhxfvI67EmnSWsmK+xxBxA1Sdi7WWnc\ndkJLSWmQspe6eQDylbt/PkPSCYJz6mJ1PlmhwCT+ocHTX24eu0oRM0yobEJ+3BSUeR+k/u097WQl\nwq4+Q2wmmZFNmiX5L9MdI1REqstsyRBeZ8mabMRSV3ztx9WkA0kiru0Z+odw8re63Z1qNv39K66I\nTndTC3lMVLOU7jlDSzpqlgvEx8YKdGwtWR10ffvObGb67Bs39n3fup2O5Qi1hrrMjj0BIo4In58J\n8LGbRJzf7MFALj6nevF6KLhs0HBXaaZal5m62IjWRf2V4Mgj/ZGFih8cnTIM6QHcU/FgUQFPePxJ\nUFklzOMkiUFOiXbKDmaG7rsR9wcJTuZI4OH2Bra0GYY0KpgYcjeZ8INrWeiRUHCuEdkTH4UDhyp5\nkd8qBv1XPDMPgRjQcQXR6su+W3Da+OSeSSDEz7Jqx0ORWQwANUskxJVyC8b+ewdldz/8gCmU3jLn\n2vZKZvfj6KayKRHK7FxWrJokhNjnuKUgWI84ehgXQFuuDHRJfsvH02d5LM9+D71xfG+2+9DfEDEM\nzsiw5dAyaZX1pVpkXQoCukJgESE+6q1hKi1Kcz4k6hy82Eu/uov1cLMo7NeNKQrZHJ6lX//AvLfO\nTUpHyaByz2otzZmpVIAOL5/ycXUC0C07jfBxvL0sQKTQ/J6GtD+DUSWCHZNSFNqTz0Sf0KmVIyEQ\nt4myxo0muliPnbEu6LWT/DYOv7SzJafk1TWWvnEHUrkRmcqohZZisBgk0gIpe9nRRsFcWAwQ0rZJ\nr6DiRpm0z5qDe5QA9XauzWq8kyavTYLromTgMFc3Y0S0m9YSuzqOWbuo1Jb6MGD0y4CrD4Wos/V1\nnsoQwwLEOtso9goiwNi2drd9k2vm2wmYUewf6sazlvghzXheJRjDrXQIclJ+sQx8ho5y2EA8Ic6t\n0rw9KrHa/tlPwPMY8w39fnveTmcgywMtLX7eEIoqb4HpKpm8TqXczal7spNuWhPPe4J8DTU9T3Hv\nZFy6kHLsLwI97vN58c1TNYlnFDCCOmFUkoE97iNuWXejagNdoAKEE8wtPSGH8c8YhdCepyPwtsN0\n6j/dy7KxJmuxggcEYvS/1HBYgQ9IQTgGeHe+RJtjU0abY0fAFTcMKKVkS6VdimguNoiWsWPhDf0T\nSQwbwNsrU+9Wtk+St0Ib+B9D5sjQuAl60CS0arfZtMR1ZGkp2AlwqMlXL4vaFfD6+0cv26jC0RcC\neuQ631uzlivVyMyfaJW2a9/Pad+6aMWDv0fgd0t6wS3X7Vw+GHBo2jfevvFiiEvaY+OWL3LXWfDe\nWqMN0yntP5YqHFz1reseiRFn8klauOW63/7kJQB+WG7swSJKND/JGbeQfPCFMEOrNpHoGrVMfmIr\nViTWD9s/E+x2vSdqInLC12+lG30LYxhcaKGGtog0wRMOFziKHHGkxpgd6cIFalUPDVmH8D4Z0qYw\n0EmoZQBqSKVUt0ZAC6rvQUOtKdJHZHubC4++dutZAVZmAW5vZrIf5aPYUYMG7yyuExnDIBf6o+fO\nUKV4G48uKd6r+L0b/4kVosCyhh8DQ5xPibzLg1awGZHznPhqhCthPUNnuweG0I5j25iasRN4R/se\nvidCKbQjy5M1KyhWL2CFqpN+LIkJ4Bce4uGoB8fJ7Rex/UjHYfduoWEsh7Lz+GgUto4MVUyVg7mk\nsEZFgT0oLlmie4VzzARU+ngPfgaDftJgrNaW92UOpVa1AxvwLiIJCFPT5oNV9UpDfoEBZnmAcFc/\ns72pZNIMZ/6PBd7MnAAE3JJbkIUvr622GwGoBDkHTSTzCuTXdcAmpuGNS6qzrsglL8GIEnq1azaB\nfLcxBq20pyiPaf5WzT4O3YJFPde+jrl5bIi3nQ/xIkrPgyaixO+9g5ws+vTuYlTdwV+aw6Z2Eg4L\nwTCBB92MFE9JDAfYEFsazggJ4c+CFEGftfYuh6XosmP5Fk2EHNRIzIy1GE0uFYNCr0HrKxcDU8Gw\nvwNinbs1W26C6/mfEoCWGhtBEgXvy0fxpOqlczkT3MzWVB1H/3MDHhQhbdjaKdZKrhbyPefTM4mn\nRUwg4H9UKqMMxY8MpelKrUSjY5Rhn0E3IibFJGNmP1Km6DfK6Bz9izzj3SlBM2tuyc/pK8pJPybn\nVY7xZ3bAQA9TCSrYluNQ7Ku7eTeKTnQFanDf+MV6WzCmwj/zQon1Rytur+gV5eyhsYV7rt7bFu7h\nYnzt9cTUCyQWzC0jEWUqDg4dVnDKcpRaT4mZghot5rDxL+LgRbGj6bzvgkMabT8xpkNdlGjJN5n6\np9xZNBlZS/KMEkqIjAI1tdGO29hkLd7oqYF274ELPP5l1CvPBr1u0PgGilPa4LGW2TNx1mBux49h\ndqlUUJe1nIq28DPuRhe/YqGf4IUv+bihFqfjdOoPzEDxijtuPjf71rL2EOjqhbOBOoJS3H6yjqoz\nnAgVC1go6wodCenXIqAIQg78k/lP48fYaqhu4Yaec1dXXV8UyR4Zw2pdUFtBABUjWJbl/a6GZUg6\nFQ6HA06wwYXpfwivS5o95dfQvMcshAMquaE+Uk7t+zpPrFxLnTITOGafA4+vt7+zSiC+Nf0FCxTb\nMD3JDvplk0ljylaXpR0/mYid+K6EEN+gcyb/eY8i6/xTRvPt6GmdZNHeibD65PVZ1rWqBgXTyM3Q\nq3IIpyPJkJzY+dHBPQHcnUE0Yn1Ep7IXmnIy86737wq6h8ed84H8QzVuQtKAjWD0h6Pdq1/8VWKH\nQf6Srovz5Y/B/hEnFO80ED1zrw5kP5jGWIK3lzHgPvOuov0d34iKEWXeDA1xSD1h5lLNSBvtMG/n\nYgutmfLDuIKlg5CgxoWNuDOxK7CQNUvrtTlyRBS4cdzErCBugBmCyvATG+sl0iNPlgaSxHyTegVY\nCF1lMIotYzUCPWG9W2AIfo9xEq4BInp5seaDZlWAueRWsSVfIMuzGl1plry/Zzis6CVGs0QpntlQ\nmXpu0lGftlcasJEbC/EZNjUkOcZvVxNtpZdpyFKxmmejHkcvJmbKiZt61rr/Y0W3No1XLwbUfIhw\nXObmHdAFsLR98O7EhfpIs+e2Ii5vn8lYDmRa1gYK9IFj6Ikcd70mI9RSPhgpQgQn3CW0vX1DAdVv\nHYU9u6ThKMw6jlvFyHneAkBJ/NueXZenXLAhy/NmfEin02PEBq8MvZGes3LvIR6fSlYm2JGR7hcR\nscNtTbmuyI20CfzH3330djQ/hXf+61PlvpLlebaC6yhnnSQHSITI0pUzl9Ao2chkGfLIv4lkarzf\nVvGKA6bR4cLQ7lfMSb3jiAK/QFow/pQOHeoBGpiIJKnyfBfm5svJ35ns4KrF2u9yX68kHNn3GzD3\nHgV/iy4tNWUmkFYbPbbXyobnNbXNQtZOX3Rp8AOG9/Oo2SEnX0DhJ71qKmWpcbp/1BYCRfkXHiqC\neBMAYFNqIsb0UFGb4p3NWy607mqLirPXn3hFmV2MsgJ+JIeBuFIfOEt+uzSoD8KC8tMwqJybtYlH\ncmA7TusUFo2YYZJEMC4hhSPr9Vf3cxQ9FdrWuhoeFLtW3XVvlHvTawERVdqJGI33qy29xmhJ4nz+\n7/wP/l+gt5FG93Ni/8IEm6tB4obo5u0os7Xg7gmEy/6HCVFtfhNkqZyn4LTI6fi3wnIp7HIJWPkw\ndHPnAy7Za9wVoP70xhJbmtieW3CdDLEwW6k9qRmo91m35ph+NUrp6it8IEB3jqZbiqJOrGid/bGt\nDRe3ZwHQlGMqCSrGYYoQkn2elADRgSBi+SEBmIS969msvSUdcffrzFh1zgziOwKYJ7A+zgPAV5wQ\nmRIYCaCueGXcq3+Y3dqX6Xz+q2Urhdjug0VcDF4LTRCKJ/z4BoxHnhPJ0Kg3E/XNFOrxbodTy+V/\nf60jkELut0u9bDLnWv7CI3wgQxfZmbDzWDBBq+CqS6nFL3lJI202FIRh8gHqVyCn6QXFS84Aps6o\nsVsDBM31a9sYV/0IJ2eoJXSJWJpMa7JuEJj1QpCWgKPuFUqL00RmWetqTT4XnPXnNJc2l60XGhY+\nAsHEmLA/EUP7dssvL1l19DmPl1664WI9yN8JwrKMKIQIyQpp1lqKvA/uD8KUtUSf230Tt66HgLB1\n4j+idT++O+33nL1aQTVSDABPdZnV8MsvJ5W0oJhM5T5tvoPxWS/TY8Ok/AcSZOzeVYeGdZxwfQ2Z\nG1fYvu+0B592E4wGHMgZbomABjWALpDg+oDRscuswztBlv34wRiBfRhVq0+xjopYKqaMfRrv7Add\ncCpEx8xtg5/R5o61oOJlc15EqnvaFBqF6W1GW9eHl6mEvxDHkpVbvS0Z/XxySSsBQ8B4OtJjUiJ/\nLgEnTM87J2olOEnHHN/z2It2S/AEBFqRaqCJTXLb/vXe6gKekLNSu4qO/5RJpTms5R0vX/nwTvkl\nEoKqq2fRO4WVPGePAka7NO6i6uTxfoUXzyuckHg1WMvjj2uoW0aucppzCJ18nGBtTTqK9/hidxWo\nZypCiHytpCfX3S+v3W8xlss9vPeb8XoUbPytxfgNsJhLql8YMcldO5pFm0jVazvHJe9caPj65/6a\nmQNi5o5KGRI1YrgN37NHqaYSj3ig9w5K5r1vTpTim68ZUVHS2B70gveIPxtcfJj6MDjza9KDgar4\nL2j+0oCV7N5QCh+3eXAbatOp9GsqEK8NyPLDCMsTtR2UVyQpbKmXt/mmPW4E10r+zzMfJ6dDL2lA\nedhHtsi8mbms9bRX/Cb/S9SduVk3vefqeBSsK/lCxd1Gm+QXnMErrXxnR5MXNN9L8b0mosSL+4s+\nEiiRkZ28NL39wlIq1dpcgq2SObgCPTEHfwEkBROFvzkMC37TQSu9S55uWIs1FuyuXNLdBELb2ESV\ndDD+vw0deBrYhbroR94kQgadZshZY9xcmMpkOPQD4KJj1Pn9KyDfiFj1taahXAewxkfUfjsZLNGY\nj4Ufii6NpDrTkb9+WFudZyVk8IJKiDgggd08rG9vKD9IY3z+RAejotDLYRUnJHNKM5vFuzrQceYI\nE6Tu0LILRbrMcJ9tmkKRGd7VR6llDLUWRXGQFI71zJIuhxIVnSw6K2TdqCyvxxXuhHR6BrdlFIW4\n9RvXFMvEbB2Efao/7VnpBqBp5x2b5m+6iv59/EKuhg4u4Y8peLcZ+Zy2t7kQ4FbI3hmXmVxnqDkx\n/mkTxs0WH7D6PwoVvsKwBYnHonDmK161cFu2IMNNS0kzTM1oX+QFDdm8eCu60xr8VrnPYbIBO+4w\nMkhpp4qJ3tFvNXTiz+bKC9Jhmt6A10MXwDwgHUfcEl/+8zM2LF1wQIFtW71HHyjlTrl8ezgvRdIL\nd/tBKgK6FOeBmfE3j3rqlvTrC7kevvf0QS9YvHUUEBVwG/Y/waNnJizM2KZTUGRpTQrNJ8b+y99j\nepvmiFaaadQMB1pMNQYgYoxSxuEnU15ZhjWo2BAAGL9Zr/ffyHkHoBcxpYlz/iI4IXPrYCGEhdQp\n0AUwN1/o0xWBJJQ4rT1vsZOGbAMTJIKFZr0UmRKDKiYZ/n20BZna0F6r+KyX6lQ5I8WjKWsQb0Ur\nywvSrYTaMyFHYbzNuWm5oEAQ9Xz7DewoFdbX4fReQhA197aZ9TPNlFW/3EONWP9RksdrMk8qILgP\n8fx7K3mt3OICfTfeW2O9P3/ge2LbbShr1cNO7VAR6H09wWhTRwTSxYTIXy/bStPGX5GrfEswk/CF\nU1VpgaTDux7IoLgJ854i6sHqVnUtv9g/yHrtHg1maXOyWelyjK0Obe1cP+98aWZkOSQehCaJ3Pdf\nyDYQXgOINx+M/oSZrRSgRxlWuoagwzJfNmX37nHCfzajxk2lagYcEq8gAOWe6qrQyj1YyYtToghK\n4us7h4un8UaPqBlfdicmryRXwhbFdEKcqhJiCFfpce7jAwWJPjIASAEwvs+2c4dClq1d3impKYP5\nRXndnYPvkhD5HHyrHqc40lGTvcw2HG81JeEuWRVQ29NcOrYxAdZDM3MqajlNFm4KPFJ+Hxkf52F/\n3dKkvR8cy2lpV25ExE13xr1Fe91exh2KVl2IexsicXXmFFg9Vp72h8Xo01Q8Pket6ShJS9tPEh2W\neRtSyo8ZESXtb/eYmlS3r9eud5juW5xJy6oIhnMMpFVJ8l6uxv5FaAiJ1ou0EgV0ZE2aO4sjYXH/\nlaZjJA147M8OsNHMxQN7BRS7WTiZsb/FU/f6R0AEmkkVR/90sKRYYhbs9/Ms8t9vXl9JpWoAVsGx\nm9OAOq3DbfkYT3OO7YuerL1WuO8Hxfa8GjT6+tX+uOYNjyXqE89/Xzuk7nZfPdUu6cuCeOv+fr/I\ncAw+XUXFY9i/EIRBDRjeI1BGw3CRnlBTE7UUmLRDofAmzGNig+mvmR4GTX0Oy5dUisE0269mncb4\nRsxmB9BW7O8baRCKKBDNVWCKwr+gmHtXhVN/Z1t0axbdVnFEWNr39f6T/0oqPp+FourFiT6onjdZ\n20RdryNEaSOdlViXMPAbNvHyEyRNI07lZrTKLi97KNn4Ow8ASDwEYngohaQoWBjBeyzKvTUYKu45\na0yUeuB8zIuY3Yrp8y6+QOoVjbMCKrJleJnf5FnOaLLW/l92IIofSSy1h7xZmhNK/MXcDvk24kRR\nVzmT2+lbkK2YQC/Q964uZCgsHP0l3YSIAdOyHmsDy233o0GjrgL+Tfh2dHh+94MH439aJw4utIjR\nAudhAMZsqLck2OudCxFR9GkgCsLyR9MbzZrDK01gDt94e2qTBEIPYC6QIebeYJCz+bpTA8Qp03ej\nDkBFKXUUn5wrXP8exjyoIpkZ81yKHXpx+nnRQ8t8REAa5ypIf/UOHBalatg6ZlJW/PQs3YKcYXBH\njpMLoQn7CQZpg6FcLCTIh+twsBvnEf82dwzciuzXY5IOPHDNd818QrYS3FGd8m/lytyweVcBWWfq\nKoyDlZvYKNGbIWvieucWEaIL/GpaV0nej6it6vpkx1C9mcdcpxygg8EwU+Q9TqebsjMqdMckx3YK\nPNUJr8iTsrX9migJ75RE6+w9+v/3EtfZC4hW9khYG4ehiG+M5NeYVqzRaSnGNxTsZOb+cuV80hpM\n5kbrEgdq80c5e8zHdush5wXifTorS0vHdVzUercyr8LwVJDJClHoXRguNTqbGzfRO0h3/SGvKfXv\neJAFBsonKZpRfnFNj6KXfSEdlPLoKKr2x0HKnjYHa1O2nFSaZezwMmf4wazBPQ2DvJ9Oiv4B+cSO\nFrAB8wovlgGSC2XpFWY6/J0v8c/0tysxdLZwUzGbu8dXxS/imWXGTMMPQdZnRxoPaipn2kWbYnTF\nnebNrre4I86/E/MFT8Y21DhVJNzRNsoxMZcsN+xeVxgYBgk2vEV6p2llC7JNVbDqz0KsU/V0rsyI\ngQm/Dv5OknCFOuVM+YOoAwiQreo3nHHdWbkeKYS42sw9rv49O4vtL+QtJG7863L8dumpAYndpX/l\nz1Gp8vM4OrhYt6Qn7Rephu5lrDK7nVzVXDshoC1XzCI5b+aWHtB3iy4ktbPhgW1yln18ubd3/WsM\nnWrccDeq78IHQn/pf1Q4C74LUgG1jkid0dyecwvMHbI2ps7Hu6/9Ythx+yi3qypwYayAF9fPpugj\nAGgFBNzwnSFWMu39vT/o0r+mz/sOype0lCGpF/4pkMi3rVRSG4O0wKL012MrdqPUvL8lCYvmJ+E1\nYJYQR1F3oyY8qWklcIMSIXeGynLJrVEkY8EVdyDlEAbLgd+4Ytzbm0tUG2XHH+r9NCOZkk/N67Jq\np9I+cnMfr/AYnJAzABJPqwC9dekyl7KK4usEpnjk4Jst0Fp+pfNlYFododZooqmxfvkKJOurqkwG\n9o37CP20uKhZzJnqTGNL0BC5/ZrvTabulqD19dFpDdg6BGd4vREAAd7Gqp6jxBTvNRQZI20d2BuN\nFBJ+8CziDWG2CsBdoGlI7NdjcgZdBsO7bvCNqHFa0FqWkby7BKVuAVekUAfX6RitgHKugIXhgtL6\nsKnV8v0tfhlaX1xc2uSxePTfYsMtMBEJrEypxsk7y+Exof6AoIyHBZiBvov/hxU7bSHu/nrYNAtZ\nJOYqBNYGMfxaAcOYVe2Vg/UbCHFlV2HIZiAy/gD74Qg8icJ8RjS1AGd7t3Dk0zDERWlinv09DBlM\nOe/RudF8dTfb1DI4g33vSu/OMHm8yscI3GVxGRciorqLX9YRn0ji9noSlSo9389QCFCp9RXOEtub\nh5gnB6vSUDvEZ+umw/C2GQsl7N03vY9FJEOftg3+o1uQb4q3Pcqa+C3kv7Zvxa0HYtc5N34lWXIf\nNnfbCOdcO45XUaPen+411pPcsCybMS7vYf2boFvZ5C/oFH2fxWLeYOEFJuoD9ORHIeOGiqq2yodN\nvkjolfq3C8HR3ywAan1BP+qtapDuBzcoZheHEq//WJnF/kqoQNkhdeaqUGZTcPEd+ZjArKCdPj8F\npfYhhpY4GrlPpFnwlw0oyYNN2yH9Ii4Ym1coemVDC2afnECWviSn4y8fQLYRbVdrdsgyIHaACUNk\nwyoVtTjt/lMYUFOOpEZgnmcn6PwT0vtrvcW/0wDZJFx8FT7Ju3V7FVxSoVhzWr2NgXApggby0G7v\ngaBBC5iIzSJRRAkwOibIhjQGupZxxESlvPAZfpeWXxnyA7YmEHx4EJy7vwEUvvvnwMK4pZ8RTQ5t\n/qgGTww6jntZ9YLCNz/REKPFSVaNFPCQvQzf2PNJdPe9a7OX+C3idY7WlhggbaCeWfsFQFq1n2pI\n1Up2Ju1qCayXN2bD25j0qONpeVV2wMTfA3/0PQvZ7NjulQy45kwFLhjrHKi1SZ3Lo6IsHy1W1lzz\n+T6kjyQDgHKEPxmgbKEePSYFw9m57IRBSB1lVL/lXhgcp3fV8iFAZbUz9vPdCXYkSA0Mnop9p9+W\ngXFiq9fxsGvjlhzNzacvJJ4lNuEZy/8Zl9ywYYRILB/hbw3jB6T+Sl7DBN0JfR623qilI/Erkl4b\nBmEHK10J5v07/+2OoHjVtND30VN83BbYkj0GCA3AG0xNTll7Mqce7tDOC97j4C2DJqkJ7bLpOw/x\nNzvjLevB+tOm5fHydrs1fHRGOLNpTd+tNaXzZJLicRPAQ3PwRCU/KhfUhD/lnwMquRemNah3+9J/\nWbDvDX7y5pZAwtFvTl1Fx9D64CTBMDRLvToJsHMW7TNnmchuf6e0UU3kSMZ7Qh6GBQTbWX3QM6H1\n891oVivzTN/iAvn7S3PCQMqWca/8EwEySxPLhLv/V+g2qU0vWgmRAwgSZGW8qhB+hKiyROe4iovT\nZ7f/ATkdIc/NU7F6uAOSfbTF5HtIKkHTtrRBh/GPODrZync/1Unq6XicDyUoFNdJO0otZpWg0UJr\nIm0baDbtDrMr2nxM3f5NWpkThFB7ogT7J6jP5Uk/W5gA92yUYXraImArkXpJIkzrMVUBcZYjVXAK\nby5IG+0dAnShjrYUMbCDCeWRqd23AQ+Gmib9SjRAvoyzqNSavj1SBCaFi+GWhUlDEzJRjcx8ucq/\n1O95KAytmC/bzLw19wV7dcHvXpYXenZdTj7NIqNvkMdEFQQ3W98i9NwAcYtUOEda+02qLkc78Imt\nEFLSJZ7EKE23BqprZuOH5UTGjH+bdjHnBephoFRnLuwZvF0sPVHLCQz6E11Kl8x67Lg7TMz/JMGy\n0QWWJno+6E233Lt27bt4uZOF4ridnseWnNw42Mojo2ZkS+F63DJcZlmjFOGUVnis87CHis7eVVVd\njVZWDDQ6Zn/wZ/rKAB7Nj8qRVs4g05fCKKzodda4WHnCVF3g3nZA47sdOjb1VGpJCwXqP2YcpkFT\nTAXPnPquxGaaGENiXmKqa5xdskfuw1Y4af7vm1MqI6lcPOF5TxhJ1Qtt53NI+69mG9IdHkpVNj1y\n/G16ztIE1JNeEtmB+BYO0mO2X0dblG9J2YB752FGSgWYV8EnXjP4Sxw5odQw6Wt5LGoLlfylOGcu\ngbhuMJQ7pgb21+gJh/ngTUpwzKK4Hcn0fA1ilriMz/e+CfZFP2IgWlQ15Yt6ECjl/QAX3aAyciLi\n2pcfzoq/Ic7mWuUiwcFzJPte9OngUghbbaNHB8SJIMiopXVGkfr1KtDxrZ0bsWfVaqkM++xgcUOo\nbMQ4UTmjeig/FooIwVWLCwUblGVHyWYAdVeIh3843mflrTKFyQwuXMISN+lQO4i+WEPWHPkml7La\nrjWlBEditPmyzJHe0W207fjznpN/km+Ne2v/R4elmY9pdqL4KL0ubbaOaZpAvlxlAisoaIZVPDq9\nF4oUjfoRR3053AluL3WEd8t1hWG+I5767HWYMG+De6VQRXGb0aE+8M4o/vBinyggTiXrkFS0wkPm\nPSObUf85seJ5x9gm9winqS0b1+5gIKEfpDNZNwf7r9+HUqvigZ8oPVsbEWjjT5fm2TgDLUbBVrT/\n8eMGSj2YLSsfViqir+717cLXHWH06yukH4WjaOXbulc7zkI4iHRX5DuvX2hDlEUCXju37W/7eyVc\nJaxXcJsw02ylBFhVwvLwRDiJUFT4s6tL3oofXqp3SAfLfm36qZJ5jjLjKeUwjot1eGA+NroRHqH0\nmgtjvwYrR5rVyVbWrYwo34eren6W2O7//yte0mey6VJb5UQPVQjQLDyFHJ8zSG/AiRjgwri3tDKG\nrA/0fUOdQGiz+RwQmrOjtDLah0oLdcnKNGdOuYgfRwuMR5kqO88aRVVDccmhnSjkmckLlEa3UbW/\nCCaLOdPOZVG43P03loHDBkump67PWIwSJufgTY2dzbjHQYWFJH4Q+HXVMJAaKwMREVUD4RfgA8lA\ncyJvj/zKyZAJEdF8EP0rk8ZsS+FplatlugSCfQVGudYccNSYpvVKtoiX82LcJs9S/HqsqzCrhkA+\ngDJEbI+8wshtd6KxUXstlXRaPBq/JYp4JESRJqGNH3q0MPWYudy5IU1Ex+Lx/WqW4Cyt6RXnulxh\n7qYgvc/1Li6u6wA2y1x1R9g6qBJDOmN95n40iDkqYuToeiI3oC54fxAOfE94As08xEGHE8kAaOta\no8l+uX4BdtrDoafhBf2VH9N+GTluvEe71ZT3DlKFjbKEsaA/9rj28XJic42JsPn5qkuf7gWNqSA3\nFkaQ68kOF/xwL8BFwUA4I1qpi84bn5o2gVQdLJJzvEHtIQTGmhCc685iDeCUbdbkw1FT3EXdEz7K\nAXzeVmsQTC3MSoefYgbwhcKSCniWMFXMwZCvqu1o0KOypwDjoi5M7wtwWyF1ssuZ/ERb8vFk1TKq\nAckwlJgpVQ3g2JcrjBwdIuAb6y0vpTto8iav0v/pMkDxrkPHa+5edxeg/bR57Dg9M9i6T4QJB6x4\nkkfyZ1w2jFGdyASCxZg+4obC4Xahrh5rvE7rpL/jAt6/JytixqGe85/NdmqycrPD3SpHj4HG73M/\n62NrImyUrHvAP/qdOGD93JyXizrcbws9HXLDfuK8gmZx0E+Q17Eq3ktdG6Im54bdQOOQJT4sbOhj\nwp0PIO/22O0nZVQBFd4Xi2gytLXMo/Jexr/IaEB+IOp3WfOvck/ycksR8uztlg5RC4mpYN3WvnWk\nebkIUPD5cYMCH55xQdzKPFCwCayAb18492wALyccze3xXGlUZkys4O/HRH1NCzgQIfHuZ2894SrB\nXxp20sVF6LGPOCfyBBGEGgpXlUGNgf0lYkUvh1XfD0U/PLpxY6Ms+fNecyGrWQ9Zboy4U7deDa/c\nlDarHQTyrSK7K96Z8gTxVpqWF2ltlrb64uQ9JW0doObxUxumbu3P+d4gfnwFzwxOKVzdeMyxe6ho\nV9G5KUKsBFPZpOaKb5eugVmH2PkBA+lWZFeHWTgOtJYCBZZFv6u9RSZ/ohBhg4bYVotZCYdVwtqa\n/z6XJaRdUKc7E7h7UU0qs4oLqh7OeCHJ9CIFiz6fOTG2ydP3O/+LkIHXj8M07BNjV1vW8hn0jA44\nf2gzojPMkX9n+D0g3kJXmDfyBJzwNG5z9hK2a6xXRgJSRNSGNPNF8Q6IrUJsBaTi5m3lrKedv+4a\n+kNlozrJBXuzvH3eArtARRpnLD4jSt5HAGRSE872rEU1XwbIxMO42s3NXr4zBQu92AdAFd6bfp8H\nb+zjoiUSdpFuOIqfAwt3fxSo6+1wwapPzNlUqHhMfKTiKqOukaeKPDs4E2PP8jHXvWzRb2W6uJ8Q\n59Dysnjtz2acTJCJW5hkHDIlnjwva90WF8hnAXeWRF1JN46CA/Rg0lzvNiHK/A7QSJo1H+8uRIpt\nkR1XM8bh3jWFkHTzVyHdNqPl8PnAjGBM2Z1QeXZJ9UgtO2amnqcO2uhydu4FcnssdGAo19p0K1h9\nDAAuNoaj6+8g5By7RqQpjLssbVgkTyW2vgACzh9kZEaRaGbIVXc5EbiZ5jUniul3T1QSfYmNpXEi\npsmWjHWBONA4r1AG2GokuJkSYdWmkXcnTQrzbNJgVbhz5k2/PbdNRU9yiDX8+YBKuaeJO8r25UBX\nfErFZr5+j2uKwIwBpHVY6ca2PRs93wNUctx+wfT9BmhWV0KOrESlVv5+etnqOZyBBj8AOy3jNLaJ\nMW6hFuSWpjVJiaK2u3Mec+zcJMOqdTpeebSCfSoa0Jv9KeSoeHd8FEP+uA4+6ufZs85JJSTJ6YeE\ndD5VHAFVYTgP7+/ydJa7bnw+leDGzHgOlIsqlASMGbXtRLxobUDu3rtJKrKLvzuusyGTvByu6ANW\nFoi27fW3leSO/k8mEYEYxDviJtlzV2Ew4DCZwlCStk7F60g+hqb8j7JlX/A4sZ7jNvzGf33+oDoI\n51RkUjiaAWH927l0Zax1VnBHHNGY3/aEcP9cn0JNLWqXOPEZaDG2AEViXc4SXglF/zjYRvSsh4jm\nlZDf+6JLapKNFj/U6WOaz/1Q+jnLOy/4jwlbGUui/0pxOwjO53EiIb8+cuRNv6lgncg4kT0vZhYU\nqI3kiVjWCqaTVYo5J0mDy9VOufJyjis/Owf30YbzK8tXhskSMnVGCEYaXysqIegIAPK2MYigbHv4\nYgV5UQNE+eud1015tIvPOBOxwMZFGoZE+m6FcD/lb0pip+7XGQHKbLnWpuM0J0Wgyt2oHHIWuwcE\nZmOznDdt9PUrecb4M0RmzKCR49k+FFBt6PVGZKkTDAMkfCcLL7TnyDp2ufoPjXYl8eFikpZ76AyF\n0O8LbQMUnC0UuD/IV4loxCdPwND+BUaV+xpgcTJLITJX52+GBY3Jx9Hr10udTcpWA4zkVkU56kah\nUtNfcGDqHyPW9c/wdOsB2uNwjN+kH1WUsm53Gl6HdZ240slkKAY9WBm70a2L1U39AWs23CzTZB3W\ncq8nSDk+xg3/2LqE44rdfmqjx4dlr74zmxQFFwnzD3CgIZWuHOT2oguHOTgfrH5gs2jT8m2F3Ksn\na7VXwcQCjVrzGbUr88rB6mXeoiM7Ax1aH9Cg5ObBctrpOejx9vBF5ZDxray1IgUot9VC1om7YIY/\nVdYiLhpe5Id8gygXCI2InUDOPutyjOvW8Fy9xpQOZxxhtV+CO6VFfW5C17Xsl+wBOcjKMGHvDGga\nDDIUGcFGlg/SRkMWBD/INUhFIG+AHsUj8zdIbmx+mIJGl11P9RlN7v06g4LUa+/N8sxmbEpZ4TCV\ndgfWQ+O4OMNl0uOoqVFcbkk5KySct9h8AAiRe1pApC4TpbbFdrV4F01uMNDu9JgLSfjJBAS0Wqsr\nWVP/tTJnBDUHBQREgEwXmUZaPmhI7TTJG3yrXoVrmGoeIH8lJRFxDIAT0j69KTSQzC0DnH/ZluKG\nlQu4BEMiQZpzAf6Ctg01cbuFOx9ZJlV9SQVOt2LtsaxaejPLRRq35SRUoZmqeZvHk6kZnx2JVutr\nb8tHbXcf4jY/xYvfYEFX4HOSvaOWoKQZp62bHLvvIaZSQc8zzZD0dz8sUqUONgaVEppfuM/WMImq\ngwMnGFhZ0DpjWeDdPEdOvxllLjNCBrJoMXk0NoZQ6FGekTHCdpuNxIKZDK8PDSuh3pH4Udn7UHg+\nkCip0T+gk4au+y1JHVcNdnx4ZrQgCc/aEC2T/UxqPRVw30xYhPl9qUGdlYHqX86Nb5nBWaGQOpy2\nFkj66xmYSqUYZThyAMQWkV7q/K1NcRHF9iD3PB4KbAvRJMbfPXRsVwK1sSP7R5nQdxg+YTaUgLKH\nDnbPx89r3MBelsRGrWQJeEa5pk3C9bDfMcDWdA3j6rTLjl8ZtTsrkn+mjWhO/C3F3s6rMY0Q6Rn+\nGUA05HEwcQ+1b3I/p4fhvDdm23QzQyRXUY5EtnP1HeP5gBk/e1C/pGOr2xgZ1Gt5FcbFfx5pvFJ/\nnG1+MqwEwLebNnBzfAgF/bwPd6KiVEFV7PU93PgbX0q8GDHMCYW2pi10p4JVorjoZIwsHTSbH7/h\n0RWSB10CY8WdocmknRsCcU10+X4Epi6ym499noha9lvBByhG+opGOQ9HqG6t/Nw31Y7U4uNj2rN9\nf7556Lp1BLOQWsAVDjQDMgRAKMpP0lfriq2XYSglbcrNybGw0AEXMX6CsFcW8H9NPxXpBk3Grt85\n+m19BUp6TYd/OSiSHyDJee3n0PlTXidCCSqKWx4eIo/SdI0d8MZrW+5914zUD/oLyNPK+gmxbd8d\nmQU2UsCClOF3pUxgccR7Dr0Ux5C6UlZBHhoIRS2aDhZRobZFqzrUhmSxSHr5vamn4txkY9JdG0PH\nntWgNn6Eih5VFDXV5NS/w2Ogc0JDHow08+Dpgy73juN2rBZhn9PVf2oVCw8uV0Wz3NN3GwV21Iuh\nzbdb5gaBvL1+lOE63dPPnCnql8P6/E/RjCAAv0pCb09svITM5W623E7wVXV35pVGDycKtO0rANJC\nQViv0aGls9jehkvD+pNfUKog5rxHFMRxGgeUB3fAI7Ml1jLS6hzuKKqBl9H5kI02FSk0Eqx3sxWO\n35z479p6mI1+CeKNkM6R5jdFKLVcux2jWoWB2T5Ze63CdwAGjTs3QrXiYTcYkJONdHNe/fgs0VGg\n4zzkv7AXoIsHn8K5HqyqoW1X/r/x3Ql1Bc6mXkOmRkfa8iEXsTgSOST82UU4r4lfHCjjCLSi6Sul\nw8E/Aj8Si/TOh2y4xv8OmJmuKbQ0YxIcbZU5UTZyvwtJ8GapX2+DoPhmVfJNjPYFFH5PQvehmwmT\ndgx4rhZxHqkrYO0lOKg1gMR/24M0cGkpIyzMExAGK26SRm2HjKlpXOdwCbft4y3wtruYsLHuNDpv\nrhHUu1Akv93ikJ7v/ghFHVTdo9XGJZVxl+pFQmrNu8vD8mG8C3OQ2TlAVpeqAgCCRYX+Ly35K0a3\nhNoGqO3Ul/DkyXYbdwbctWpTC8zn9EBzNxxwtkLhS7psDn+TWfDlpP7Z2XYi4NVSBxVGgapS8yzY\neSP6L7TD5HKcQnLW3CBtWk4riZzf3thpYF7RXIs2t8iL53IdB2YkikGsMu/BnvPFFJHPF1XzpTf1\n1GAEUNn4rbgp+h9xj0odIY1m7DYoKAwduAZ53fF5TtaY1gklZfRtZdP0qJISM16uWVx0VPaicdJt\n8l9pE5rmK6VJV5bfkzz+2LeNjen2iJLIdYR/EH8nmjzGQin/GKIGlG0XfNknxNRKkiyE6KML0hNL\nRIyzOK34XYuE4ymmnZzgzmS4uNCtg/oB4rw4ZQ9Y06fY6x/M+Aix7Z58rE+icVHft8BMDmNIOKC8\nfkTIA9WfdK8QoPSfZ9P5RQrGQ5YW0d1wRWKqNIYvor5aE0MFS5N5p8rbzdGtjMIOspT1wd8gmJgx\nv6NLOSdPV6P228cpNZ9cnGr+8M7EerdjD8xUTBZO2e897RQUC04/6LIJGqfBFKWsgDGv3kUXOQ+t\n5WOI0tbmSVFDavJJmzz61GPMnT3MKugw6r2yqhX2Sv2A2P6cEsDq3MmgrbdWs4cvzQsPMclNmgA9\n26joYmlJsUz0ID14LLYezi35HMN/8znhYLYkk+iO1Mxt+En78EKuPjQA+XRu64aKTT5CeK+icB4G\nRDq5D4mWKRODlLhEcR4vJWer47kF7ZxiOPFc4h5TvQJwX8bV9+ttvSgdTDv6+7BoqmYGNDM0KrbV\norA4ymoZH2IqZevYvXn6gs1t83upmYS9E5W553qp+pVav6PxGbW4E2DNmFtfbK22PZjn+NOfdOnC\nZRnmbp0KjISOxN1DplSkpppMGGLEvHhS+99+xay1wpK4NXbskGhIBKAGDPQ1M4/JnLB2CLHZfV16\nmYQjktluxwp/AyDDJRPX83Z0DnyMATsm/SpFNKnhxuVcsUbnW0OPH15IYca/VfEJ9ZyQUJv5hS5u\nbua0je7G1Hk2mbj2g6L8ZxialXajFTc5kaTCPPOfUCYGlJd5UCXUSvSmZS7UCzs5qMiMNUzQiWfy\nN4N8YDSPh6mPXPDPwPeSihf59jWss9LgWf0b+r88XS5VsNtxbMWFnfrP2SFOStSXfMK2MSP3KA4p\n9vOyrwrXCe37G+PfSql2gEI5vis13IlRhYKXzyk4Nf9zHg/l5vWsR50JJ1ddhKx0YeL8cbiAv1AT\nlzqGBgZAOkMinsVyO8qDWgByqaptxT2sPOBxUaXx1ZoH6h5A3bjlHG0iM16TAZ1BK09X2pDRiQXP\nEeUGB/kTxxLiyBK3BciO5EwCvaTfsVBowIZyizCoXrKOrNeGzAg/E3tOfvwHDk37f535YZvsMI8F\nwsqHEHicB82TcoXVK0yya49sKe0nkMmLcxa92nKzKrkeVuE02y1f27G8gYA2JKmh34DFLfoAf42c\nFiidrnPcZcHRaiTwb7P0kRZqbZFb0V8OB9iDZV9qQq47ZGq+OY541WpW48zGqvLEAjH5req9LE8J\nt5VJU9g7kzgFlQVS7vH0yKnN6X+gZ/qqVtxLYJl6KtWDQw56F3VSxSnP6BXG5FtOsWc54oVxmYJg\n3dez6qaAnUYYagtXbljgpL06Z5uRChLxCUJc6O2wbS1wxckRA6wlVAPpxalEACteY2ao5goDytN4\nb79hN2WqDvnzQFBvMuZzYZcm/ZMNPXzhEnTWHsD1mqxhemlFhPGocUPxViD0lvgbYusbzoT7Ze9i\nmkasjH7XeUfF4Ov3bAvYlZx2nWoqBXhBHEiR+g0UyegKKyevU19Iw1Iu+2D/7Rmb51mkq6TRezIW\nlmmvYvKf3I/BCjmHxYqsb1fyjUK6p9PgNq/QjqQO25SxCLdV3eKzUCT7txEVJs7W9dJ616IFYBXQ\nWDNaViIKApw73K+44BusnPAYR1vhQEHO3MUjzrGVC+LyRDlR2UxkRbZgVxu7CMBVMJwUy9SMxYNW\nIodQH21No8Hx7ClUbssGWqFfF295RYSe2vKz+QXyC0jV6SrsytjJ/acQyYpkx6KSSendqYJdo1d2\n1QWP6k/nCG3Ot+ON23JWRGrFn7ucT31h8faPpSCebSMDmXJDnTEQDjpvaj6QD7Yu/51JkmHCN4F1\nrE/n7gHwgH31Z1giQVUKZwKRPxPTksPdzyCgJGXSA4aI8uXuOhBfN+xZr3tTwvSLCYLRWtQSn+x3\nCl1pvQ6nTXTBgxz79p7m8c40xp7aSa3b0hhfn+Gl8xdW4pcgL0loYtU1le2clNuGgmPG179i2/uu\nClQMjD4GD6BcbDzDFN/XpL1dZYglqIbXIawigcKxcFBYDTmsRXJEFTRn6SXwjrYFNLgfC/yUdNkU\nEYEtBi/0eKX3Wa8Lh9XHiXDmlQd7wsWBEiSYEEkjTTNzhon7XJN6AAY43NjalbBLcqmX5l1i/8b5\n1w+e5bzSmX0WHcyWCoThx7WABeHWdLytMuWx/fvk0uGexf1ytVbX9XaF3vziR0SYJ0QUSF7jYoUC\npqmOwDSKrcR995m9qI2IAuYp2yTCG7PvKdn4FkjrjlHuD9ycXdYWHUVR/WgZToqeinwTdeRGLCp0\nWuxVRjzkfFKvyPROUMnvRny09a25/wTETVo+crnXSjILyUWQib7habPmyEoQLS19e32CrXE3rbLW\nmoj3lJNj9vOsZDJkdcnDb7iZ0+KA8CeLMfm6G6sGBq0GFq7IcP+cwM3wzB3YrmjNQBsYzrQJMsDs\nCaaE+TlVAR3KmrEXssfPInpTbu70ZuWlwYbPGSa5utwno+AOs891LYQKTAKwcpio20sbSEnXknOA\nihNc/KO6b2ODy8dHQYe2tWc3+jmqozOQsNHtNTRd+vAt+2Nh7Q6+C1vTppWc02x703ZDLaYZiWd+\nku3ASFwZm+YG3ac0DnYfXoAVojQ00ZeY/QHoBaEJFYnVEuoergfIF/vA+2AYa9g66cZZ0uF7ITfp\nNDFK/Rq90btOenrD4sP7dYLLMFOonJlC7hAkJF9bviXGYR4w95entPxMv+oPFhKr/83KezLPclOO\na9drF25tp+Y2LRZwB4owHe3DFce+DT8VZbySR+mqQqShnb7WtuAyRLahPs6DDEEQmS8EK8jyPSXb\n8YOSBnxG7XuKnw8Lv56v+NONoGQwsgDuF5jfXRuKCu/9PeSRVSWqIx6tIjsBWQON7/sMrqDUXhTU\nP/z5b3GKlIrmN9wVF32x3RLsZ0xs+PeCpcnW4neNVzSi8e54CQQEII6q8yun0SBH+mDXxdw8+jCp\nI/hiG7Z+NuoPlKjvPFqWF8yqddQQ7LmB/oQFkrAYwS7cONCc+g+9R888UG/VJjYRWROlwD/VsMkX\noBwb54pBv2OMxZVFhN9946P32mF3Gm33ssSRTTlY/TPGveeiqD1FtepBHnRIQ+XAN2eP5cd/+Rn1\n/awP0x8ME09OdUhn0XGgIksd+AziSrA1GkKiikudfGzQvqj2a1uwfOseQosoXcGOIAY4V+krSmPk\nOvZXdc4/dvSxXfv7EOe/i5sAw2LCbVgprkmeemR7K/H9kwesUv1xAyy04Ng981gTa2Pw6XgyzlR+\nWHKApQc/FJa91wXVrNLOKiLV2ttSwXtyROjDdVQx0XuxHzTJudCumppXwifst0D7pJa1KWx9iUvU\n//CF+VLQsubHA0051h4+dPLg9073kxolsyJbdjOm+kZXvKWtLN92wQ3qa4qmHE/kXtW02XKXPm+t\nDOXJIMUAp/C1tRbhCfg6hhFK4lrKvnH3jVpmKGMOi3rELj6989e9xj9HzNC0+TJ/IjS5Liw2g17l\nFOnV5xIwpUwN5tJ/cf5nzO3bmA67ENfoKBK9XHULdImTpY60ZQWh0v6dyt+zRMcMRMbBqkcxXjOh\nd2drqdtPIcshuCuIYmcAI+ODGXCFtC+tjb+q2EE7wlCZiaaDYdgVibg5yenqh5ZR7BlG8+dnaZtd\nVVqTIdwYYFgSl21aEa0TIEX7TEA5xN4H7Bma9vYgAHiOS/YacTwQklxMDXN0FXGSK44neOurRYmJ\nlexE8qaugJ4Qo/MbKfF85yXvxrKo5cmFcI73AiJm+04vQkS//MNZgqJaCj18foDt5A131OSCS+yP\ns+vMgqKRoTQXCguDOCbv7oOD5AL6YcJRTZqLSTZ2Ep7t3hxYs5wtOf5II9zef7NtL2AU8566AwcN\nBv1X5NmA+QBq6A8+AaNuk3Sk+eWNYR4r6FJbLmj7dEPVZAJFLN5Ldrsx+FDDTwgnGpIE4vgeZBrl\ndDDZ/OZ1tIflMukpwYpuLm95chxPPMgHhcr2TY0T44peWcWCX9mf/oHfU0EIaQ1trQTpWZ9UgOgv\nJ+BqUh2kD/ZY8xY3ZxtRl5cUS+d/BQ/dGNcHVXfWGpblRGcHuDXQUSgQIQ5fs96PCpEWeQrBEqce\n835ejJOjwckfqKguukrarnK9MQTALwzxwrF7qSEJOdL2Kd6E1Sj25F2frPDw775D4TTf+QnkzkB8\nuwLul0inUosRQWaapvR1jQJOzvysUAvfCRA9dgbKem2n2Ji7r9ZbpYkt5b9BoIDb6VrY9FuhpnFG\n+N7rkUrR/VFKVZmWTzc5BewyXbTa+SblY7FtvUZ7iH9BvCq8nY+IxjG3WGx/Vndxy1dMnFBeIhHs\nfpRufL4fC+GfMvJBxJxoEyfbGW5BtFbo+uqfUq64kNUw4oVli8A5tLaYd9y3/LdfbZn1zL1kixuX\nJsBhRYwWgGKxpbo88x+3FaGovmRLQ0uiAvf+lzDVuI17RFLwvbgS4MeNpGqr0iK43vohOKiALC7a\nmiUGzxMP9+r5XbhAx9Nah3riZW2wpLIp2GPuOBy2GtwBbNKd0w1BN8jfH6p50YdFZfksroMqArR8\nd2b/qG8VwPyVt1gfdDrNtiGzZo/oexOiCXWDx42LQ6OtrcjQUGL7Eyh6DV7+/QEX5gFJ2McUflPl\nHbyv6Rf4x8c5wO1QsEFWaLGTxOr6fTvfFZ+A4OZhmC2IzniHjL6OJMykDxbrGxcfumgzokHmy6Bj\ndqfZBV+yYdJaqSjRjg8TQS5xL+31qweX9jy5XPRrZjj/nPO7WCfrALdAkZCRLbM/lB3CYp7snq/u\n2FQPUJKzck84Q6brIc0yyHU7cZirWPuCCJm902jQfF1Z4eeNBniVJqMxGxD02fyvBco+zDRR7wg5\nMwKvzf9KCPLCMRDMCwvw1TZ1SLv0aWNJ9yJp2MIxp6PpsUIjg84Ne1nZTjRC667gWR8RdM1HSMvp\nR/7CjeSVYqHKN6klkOZrtYFEWmP8tS49pJMupw6rrUtfubwgMJvsVlsb7zVRcFr93LNl1H0e/645\nyXQRxWG2+4wTzpf1vlhQHumG9ELNNRScKfUtMXWH8NLo0b9JOz4DX0BYTMiPXTTSr+rVInFhH9vt\nyrLIir/KW633WHZm9HwHfVrNspsymo0wtIEabYHgDykp9IqD+mncW5WQosOpZ9c4vkofCTg+awnc\n9g9fe6dakktrevhHyNh1sB5eGeg5gfeQHNFELghRHiRSSuuaP70GqMPN6n+FgH2kSfiBn7WOfo1Z\nOg8ypRlaIWlDvEQozS+0hlB5Dt5B4dgvD3VHzllJayJgpCBBigpy4EUqYp/wW8UAINtpVtpmvxTh\nrj3DAKLlaTDm4rtplrM/QG2R2gSl3DkGIKa+oslquw9wiJUDsStTuWkX/Csqg1hF7yHpGi0gjWgp\nes0ZFOARHpaTv1eNyijqt/5kL3mS/Uyu+Xf7nqYg2sW93lU4MRunY4E3x7gVjVlnDqrH38RsgVbf\n/bAB53riBSBEVwvrIhNCLJf2YSx0dQnknNj9TrGqG7wg3siYtKyw7dITk+j1adr1yT4WF3JPMXfc\nCGCzd99DwEMf8GebDHPdamt+dEcMNraG0LlM0/vyu1DcPydE79HjWORYiwyjETFYxHgP0ieLY9/7\nbI9J0zAIV4h/SBn2tQvbZPMzROTS8cHMtYmGYIAW/DOx4F6lPzxBsQxGcsi5bomkSw3WG54ymtra\nZtfJokEersbLJNwoqItcy93giFl9IAtCELZl3/U1XZHZg9mEYTGHi+vBdcGOqdpQIlvRX9p1F2Ip\nTS+2As10HdT+ixcdc0Zilu3zsL1nC7aL+qOP83pBQo8WlmXPB7g/p+8+Whhe+6M313uinCh+X2R4\ntLcLDG5oPorL6DrBeWkOCRhppgNms0upxAws0c4vpFv1G5Yi3kS8D9QjDa9PxB7Zy5XIImLr5qPc\n+8UsRuj/sjnk1nk8FLFkVBuK8anycdHLyZlXSBldoluzkSexK2ccVW+p7pHqcaL2LdwCThrtKHPA\nTToUHml18jm/0AFR4DlPjn0Ay83jr2CjaCJg88QoYmejDgsmSwS+qrzdyenn92N8YNQwXHnOxvDI\nEX8NEjgGwejNCX+F6UDu4ooXRWCHV/db1LUmOJi3tZ6pHl5T7C3UGZrLvvGq4rqTC8dnXu7QElEl\ndXB0Jfvj1WkEZwRcfDqnNndXXvdb0+eXayHK5eaj4SRInIPnJRdtP+2MMCMg3IZRDGKyyi3qm+9q\nnUkNNue5OIeLn4DECovWjKy41O8/ssjasnXEaC8b175d2zW1YJudXn9amXWCbX9Ud/bmb6nBE4Mg\npCO8ysuApFyU/RpvYgZgCQjbJfU71XAZCVgt05sizCXay1VKVROFnEp4uljDGbKOjbHbH3gaC7I0\nRWZMB6dkGm/ZxIpiU/6RKB01qIJZr0erZoOeIK42YBb9tyTfgSvQD52iJKevHGEhXK2s8Z8x9dqV\ngbuqj/yvDnIYAOXW6DSyphyGUq3aKIziCwwukrCtLswyddA6M/CtafF8B4FN1BuIfx/+G0b6ngwm\nlBCcR9txsFqfBFL7baf7JUUA5EOboWh/ow+ujMJ8iFpfInczwga6nLqBexAosYjMKIre1kpSkuk7\nmegLJWwe2EgVBEDQ+FmrZqOwYXmJns+jqYMgk1QuPZ8jdmeZuiWEaoAqPj/BjdTnewI/MRkRQsdY\neMANESKrmSRpTRosqItt/o5xjdCDEWk8hsvMP6Bj6VQ/1SArS5QfXG+Q/Y8E1dB16ZwIFCvFp58f\nsaGN0k88w2vMwShz0YC4qI+VDEaGMPvj1ETiDId9F+Tk1HacHTQy+l8YVIKzpadWyDJUEaOHUqvc\nV/kktcLl6/A+rZacuEmYxtPG0SaB0+bzx7ulrKNeyDQpLQTxgW8cxwbZvxcx783MMKW/oQTKfMgy\naoO2bwD69EWFTjHW80RXlrGm0cI2zi5rXy1U+NuljLwFfXu458eZWWzbfGKiHRvM2eprcivaE45u\nhe9tUrWmJPNjmytP9CxzArvdMbGunwZGzfOtNt0YrijI9OLSvrDbl6x88Sqqw4GQJVKTm4/q7xh6\n8ibl/9i80mHDxOj91I3UiCwqkZg5G5zVN/4axYNihActqP41F5lLkw+hWR5kQsFBAFQHJT2SOVLa\nLUPhs1boCE42XK6Gfj/Tx2j9Yd44Qx+XdDEVSyZWuxsFSH1i8yN1NUw4ChRYkNerHAZBEqCnNdYK\nw32X9be7UtGPqWm+3kydmuOe71OrhlKu2HeBilBviVP0AYa/zkoUuFj3s8Hgt6bSKoet6LloUUgJ\nqI8wIbgurQBUaNaxNnZ6GxVO9KTx4uKjRMmSU2XP0Twz4ImN3C6y+UBZG4qhw9TRUwf76N31aXXX\nez8PQ3sgpQkm/gt0naEV3+9SFysH1BRKSrz+TOIbPy2QJV7qnWWK5k2FNjHhbbtb+AleTOtfBoLe\nEc51YElVxUKld/cOOHHazFVO/nT4EqFRiIn799Zn9pqxR1xVuX13gQXEHlVlh3GnV30FjahAXr2x\nMOWxch6dz3IBXnmtnX2n7mx1OQ4jT31f/LAhehnnyv7TpK59ZVYFQh9c8I98SXNxo7wb5b3nIqNF\nMjBSWnwLaerX6UcJ5wPGVssWMw3zOtuQjt5MxS/pTaI1S1jL6dio5/xyaY6deEFJ9UwS/nOXgjhU\n6NIeYRg1kI4nSBmdu5f8sxS7Qp/N86BSrRb18TCrGZco50Sw9wTR/ACbl/Ch93aVY2XnhtEYIFWe\nY3nQhAncBNIhNdS6reDaGsxj1G5BA0HDk9YheJUOGCxMmUG2sRwD7LpOjbl+q9LupIxRmUdvqvYD\nJKntjzxXKsvtro8LogYiYb9jU7/5yiFQpM4uCDTXQBl+n36tHKaSLrOH/W0xGbxcPK/0m/f2h/bI\nCbQ4FdopFGjDlNksSv1Y4F/TlRRs5+ychHtOC6UcY+BgwNJp2Gat9d0aT1oXlCfNnY04bSqAGmNj\n8DZTRVeCVeUzmHHqyl1m/pWKL96Gqk5EI9JtPjXn1wuNhHJ9ekiv1uy4uQ1o33Vi+ASxHhqBazSH\nFQOgKrrK465oVwU9iZk8Zpt0a8UYjBp+CDjOP5tFwWpi0nRehaSdfluPmr1s3qcre4Z1dlyuV0jf\nXfgz5hiEtEcttscDae5WKJL6W/0vYIFH2/vsm8OoD4RQPSJNN34jUFlwqzZEPLtc/ZeiJIqzUumu\nt64Yslx5F4I99PgpeRYFCw8dD3CtgpNJKeBoTpReAT7O0ob0NK+MEpspLAce7CGA4RRjowNNGMZj\nbwf+qjEbROMQm/19sdfd4eoWtFMcBEmUDcIwy3zadlH98AjuPeKJtAWtfbfzFWDM9Mcdeew5V37J\ndf1g2fkmvBh5dgTvCXMr2x0NWwFcd5imxh94VvATHfw7O39QEdBXFfPj3ffEeqTAgbel0UvfSnjU\njZftrWynlJu4kqQSU10JfnORHe4h72DiU/HtIjRMysSqF593SJ5BRQkc3ByixiPExTfE9XghBavi\nhedetJextNsM2o0MfQZ7M2NMv/CWFgI6DP1xZ2Fio8L5dpeAqYORS+WFgznPUvW4j8x9179cliRC\nH8FawTKxlGrZ/zMnEQqOo2fMkXd8byn8oV2qv/l1HDNFJXxAzGydp4ep9xXaGpaRCjqYJGv35KRC\ntxLJsY10Td+DHMNcdv6zJUtkWJdetQUQjsIqxJgUh2NTibilW7zwlph+ltuOQiZj7dhGo2NwpRxj\npRSOiTAthj8O3Oox5lTjkWsZQOJYZhsuLWdQf9lHcs0ZUsj5S9+2RM6U0rewlBsYMkgeEIO9WrvZ\nnFWjGBlhlIAI6hW6Ek754Y1NwfwcihhMlbFjezjsdA7r0d57sHy10dnyKk2dKzP4lsXx4oFswI31\nMlJeO4e+OQuXMjC2s9QtD99djW+BQN8vS2hss2jXp0RUFN2ALmqlKUlQY7F8Qk7GA8W8xEdMSRfC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CgNeDKXAqsyHlBqiikZBELrTLQziUuO2Ozlm5IjiDh2U1AcE58FeYpCUcAKk7tuudNf4kA\n+4IZMoylovZMIy1uk6gDeTs8t7ZT+qbKAYqvQHGc680oqpHHqBGMlkn6SvYbCvdeT57YiL8qgbua\nHHRqgt76f9I6m2gEbzKXyq73F1XA7iNkIQH6wvVGab9k5vFK6t3VknynPia/XwHedkmztqfsJPcL\ndpmsfLCWWjJB71zBzndOPEH4gQlmdtbPTUCG907wykBW6mbI2D6F8RXBFxLFiTe3lLlK9f6JqaKS\n6P5Urf4pShGjQxePyekutNDkOXiqBWkNmqlwZ0Mf+998Ey554Ts5BpfAZKA3iTDnLqa1WjM8MdFu\nz5cnBm2QmsWFiDw07bde4lWuor/GigLLSGoi61c1W9VUUTxsmRW3Nm9hedl/LMIi+IVd3Ie5yuhm\njFTZ6GPtxceQZ0a4n/9zmY1LfzOKboZDW8/yeLpK37K4KdBjNJqUeWPNEgbkAwu3B6nDVdpVe58R\nyE2+HOOoxDbkIulCG/2Z/niLLNiqicjDej6x19gTcxFfvW+AKN3OywTja1dzXhKcg8TxzQWMPch1\n7hIDvB5NzUnEvJPUkHECOzjp3pErBKiXve85ZxpQKaT3uOCuv48BGPUNsb4Lfbil/ZB2YfZA375g\nBWHRJSLDuy+pUEyTq8jZoZFHXN7uX9th5cbBFjtERzEP1e47KFVu+y2grd0uT/p3aA/Dnc1rAVN3\n0OUl/SCM2fRrCgXsZVeNO9TXtrL2agt1/h3Lf+NdAkcZvn9s+8p2KQQWKc+XZxkefaWM9yc/9fsX\nPY1bSFbAWYgAawdP8Rju5Hw/OWV8Sbv9vq7xEY9BvZleZMYuNtFgj/xGBc+xuvt2uXAyHW8FfkIM\n8cL8AdK9g14QyRhkyT0yYQinZHzS1u8UeYNIafkE9LsetGUZn6zTUy/AAQpdOJF5R9QumyGkPJIG\nDLlbHC3SGKKie2/q6GjryZedQrBwkwtDiAxTW0Qz0ZfWnHQKZUXchgOf2KSxyoc9cL5NvBSM6pDT\nBAvpvpDR9IQrbp1Me+korQHewv8IU/iJGQDmW9irBUgAsfKFL10de5y0FcL4nlC33hPYvgoiE8RU\n7OI7bRcSswtiJb7UhlyHXhX/Qq1xYGb13RquMH7/TEr+w0tdRTXngTK1PlKg/fw+yvbbbz84vm14\n69gZb0aJzCbyTfgznfo6NSyt+Yc89ItF7q9pqhZCgcdoPXmBq3Yy9NMPtoxsUH6kOSfBF8AAXDx9\nadNlsmO5H/J6vjfLVMwnD8RGzKg6O36A/qO8CTAXdFBWJK1mHmV7AHkQWbWjtI+29Y8Cjcm5TMCZ\nVcGqgrTLwebwYR99+75or4EP+AEvUyYflRqH7zmkV397XZfJrtGjYDfVNOaw6Fwwl0BUaCVklg+U\n5ujWXPqT+WCdWww8BHlzRx7C/fcE8QYr6jkhv8ZWaZVWeR7m0BETZyFFtYpPQbknoTrZ5yogazvW\nHlomBpRuB+kPMi3hXD9VvYxmmzlMPKDSqnD8oEc+v2HUEWT0UgCJFxQMm9iGggPf3YHN9D0jFjsl\nmgTwaen8m0tCFvDheznqa5R4IJ6bRUvo2XU9OK9xcgDzQcHU2WgdEott1qQL2QD9Xhj4zN09paCL\nT/tIIUjT3V9B5xBRw1DMZULj460qadkGntA2s4bdSew3xEhDt1THe7ANelYoDzMrlueUPA5ybCN9\nj9ihdm9lEllXxLg3gyWzGmSmuv3HEWoNkOVomnTHzZ3J3QNTFDOMQOkjTsUcMNbO06kf3AfMG0np\nYy1LjpLqweinJgeFCZihIUKgUh+mM5q83dzxHzSQOkbp4qgEnX8XTdz8z9rDrqNF5Lis+cg/r2ky\n1v5mr4jN6tquOWltmsh6mJqtbEflof2B82KIIYqy+oo3T5rJ8j7yS3pspqLojUPsoDdI63Y38pnl\n/hAd0oP2aCtDsnE/pfTIXiWPGhPniqLkuv7cBGBWXYznkXvzGpkOqxyxhWAgwn279Vl4NoWBY9nG\nP+D7yenxJFKzsvPZCtA18L/DbNpESKFNX/zlfxsNo1TD+3r7PZTSdNqrXwlbhXO/m/+5mT+w5GDX\nG0lC5guj/TIRf87wZd8GuzTYgQ1MRFizqy6t3AMudVJ2vnbE2fTM/qu7afzJMvpQ6f4Q2V05ln8/\n7q3U9uBhrpQvPrvVqap3SfhElGbEOS4idqH+lE2LwPXQ3rvBZaWDG/ZqR0WAPWNNl6uprwIj8V9F\n/nbYOcr9WtpeB5Z0NEKE1Wdxf71w7Ne79WOVGcm8UQCtaI9HHu+ky22iO7zNt7mGTopdMTplddm0\nXuIyP7Cf2kKXQqso4w68N66MJgEeKS8ICKONtQ2HfqETdm23OPCItND6bDztQXOM215iJj/463Sd\nYBeMiN1aY1cnhgrab2oVuroETi3DwUIewB0lELB61LHLjpKT1uFQeSRnVjZ44sLqvXljLc7VhQ9O\nkM67M+SRbxF7gdwjNVUCJtaTxVM6Vad93zRoRBBi48nRC4GogHXTVFX+P6PK4lESKZ3QFQVE5E2X\nZJPoqgI8udlaVeBK1CyOphB54UqTOMDo6yXhK3f1Oo0Xb7Z6EvQYSu1ZmiGlj/VxnNju6GIffPbU\noj36vPOyJjH8eHw5Lsq+wMg9hiBym/bv+XrGLRz5gPQOhulovqdHuA3VfuOkQpBXA7ZwWqE0XEHA\nHlX4GYw2s6WZRP35U8njSsTSSEzeHuQwdhGLNBLKiGCMrt1OGn5KvLQhhz3uFmvCvtO0YQgr4gRv\n/vmpo6suAL/ASzgOaEPhiVzMmPkrWYzIBE3QRLskFPR7umUQrpLgsHbonxi24nKArAZlLqvR8zG5\nMJW+VCRb5DvU/3epE0IoFGxaMXInK3yTSqfouU25pcD7UPznWiUd+Z3ZbKcsRUDqqTFSWVEIdDtj\ne1soBVA1ECD1iz6+bTpNY5Oh1fX651YQ9lvHKncJ2+dN9V+hRK0ngC8rt429CK7a2Idalpmi3JWg\nDc+d/z1QrUiknXJdMXdblP5a2mivNqIY+P9N58n+bZLVRKzRPI5fH+TaiZ5jTqJPrlNeN6D2tTa1\ngbHLS1Bq9dYuOLXi9TsbmXBgJBQwwPEWK5yG6KdPu9G2WhBizqyKJONkO+nGznTqzepavVi1EtT2\nDSy2ZlkxvRjUjhs6nkJ8oFotJICNfcBze5Rsg/eui9K9LduHWu4KMEEnfS6sgxuooXB2mSH26zwV\nij9uuzBYnF5pUMZP5ZIHwUnjANwa5J9TVpzTTsyHD+lSA1anl0ixbWrZqBWojDnzT+iwlGIxFd5a\nCr7uEUoz7+tyA+l+rF2lKvvxzfe+zdYMMBvqsNDGdYqNAW9FkmJhCLqy/xwgk+n2wVFwkP5bs5+I\n3CWz708qj0Xl3IUamaiej1IyWbCM3/65rfAs1jw/SeAXlA5GLuL0OQre+5ukvItsHTy5WCsZy25m\nIlzQgA+g35NVaLX8dpPHhdDcFPt1hGXhP7Yr6joKGvJFCTAqQSq1Ept7/OihaNf5XXI4dZlwggzW\n2O6+s9dtuhAiKtqIJ4ijww+apXGJirR6xUAhOeSg0/dL5FZGPXCUkxIV/mjEPUtP8xHtTf+8DOkY\nPWXBtnx2mGH1KZHfCfdcUVSPmQCAIA9DeWX3Q/v0IL1BHCVTaOsQ0i772YTDjXu0N/Va45Up12M2\npPcrdVHbahLP7O39ql/r6SNm08f+RwI7JPRtDX6X7V9G6+hu0iepMxsxBHk/8XaLUie4D6F8Tp66\n6wGBZoUWXHhVYxe1w2xSgRvnaXfLtyfhQlgn8KmHdgk8ibc3u4wSRbVtHfjrajovxVnePPubf0sR\nGGHlwLMSkklmrNGL+lSFGUi1thX7/vm25FpgBAf+b4KILInLLMnv3/NiX04A6G6zgU8xudOjKqA4\nQagbl+lgpX1lp/P67vogTffKrn8q3i1bhVvE/95/IJpHNxGD/YefOIJie6yvd4g4+QI0Msv2w6Cd\nidnVFRjhjKzWFPITgzw+/cK7BbMWwZa8ZVr/R0Ea4sWBVTZPvhPjDIMDuVTtZ/BIXrN3ZvcoZLIt\nuEf9nP+YPyFSF9h0+9M0/nnp9F71JHyX7jYpqOOfRpiL3Nxuokq2bunZore8JzX0eTcdJscbMtrD\nxCeKBmGQnzKQ6UiCUFkKvuf94g0f+IGcEZumf//3NSJuBvPpTbwMJSm+sY9G//ySSjk7pQqkuR8b\nMd1KFK517XUMgD7SMRegkJwaEV+w81z7aG1qIch/hQCgQbYqsyjvh5nQId8PgIl3hj4GB2InI72Y\nUAhpGWuaDLA6TX7OKs162hqSHhiyjirChFnxXjvJ+txbFF2Fcvd8Lle4qgP9HzwonfxA4tbzBytC\nLJ8EbIpgGoQE0uuPrT7LQg5Ul5yacTYpsvgQiEs6/+lSlLDAjEpcyOT1BIsadKqhJF6LUpao/Yqd\n8nYhQPOfQ9M4yxojCmXWRMhypMMDagM5T9sv6qzL6qgJ4635y7SHWV5n1z+x2GMB2W7SBYChf9Cg\naynz2TV6w7UesU0HBZfyRI8NLkyMS7ihpqyH1jAn2v1bX9SC3mKHK1xiPPb7MyxWS2sPaIZTX3dn\nLSFpuj14rJiJBIzNUKOQfgxBQxFfjiC+nqamVkFll9Me0K3Pzx4nWb15saHV2Agy2l4DayCQQSf/\ngFu+g2qlmJp4rljeZnvFcfEJsOYyCCSq72bieaiG+5CDM8FK4XKb+yzUHKzInHArOoYBwfcoqN49\nPkjVl2JDlQyLuLK8pcfOC8FrGunZkBIccptg7+MMvM6q5pSPMdCQzLJdSw9VJocDG6zh3Z5jUJwH\nJq6pFgVUxL4mHQb/BSlbgvs7NHbdBWKz8rrRA4eVc1kv0JgHRrOMv+3zEIoIiDWuTT3t+yN96Iyu\npS+PKCweGUCAk35o3tdplD/UZzdXhXqDMyDWXStqKnsQIolGFL1H7y7QpISzFxs688S5FmO1T2+D\nM5ktv/9S3iEiq/1qs2t/zEaENLUrc7DR/jifXMCRgj63g3PpLxVEDTtL/3O4f3ScoHrkebcb9I7i\nNaMRY216C8UOoH2/Ce4vGbBnHlqnvcEceN9HJrjnPVfBNQgn3cqClEzhriztssglsio529EdYhvp\nAI3zSbuJdREq0mii65Ch+MFopk7xMl0FkZtWXazGh5EG8XUCqTTwL68iZQBJNXNwpWsMwOjvvVMZ\ncvUCwskXIgeBTeVeZn9bFKUZ2F3GnOTZ5jC7ctowLND5yXfbzx9O0liZCTrjtu53iTdFHajEz/b4\nl8p2KTpbmC2CvZInR7lx9ZYk2MP7OjxSovdxxXIwpgMYWg1YKAiEIew1eILGHH9xYot4oEMFno35\nqX/JcF2ps8iJNJ5XQ1YzV7SduBeTCx/Yb2d4VHhNd6lfGJ/VPyBamni0Pp9q2Dj928OQezu1XIGJ\nvaLVosBVp1vLOs0cqntR2L8Ok3H6FZqtFm8mugOIB7ULCucN5ryxyJlP6Mrpe7ya1q8lqOGtAwth\nG/Dy3taw/Yy5HG6TB2aoRw2kQ4Btsq5j++25XkrGXxx5TvMK5qSWyxOU2HSAXZZI0Cn+jichK5fs\nZG/1nqyorqf8a3ei98nqpjNgoHVp13lYVrpLCWjOaECv0Opzj1i6EBPMbhdUBAh9TkIuZZlMVuR3\nRh3hDvelRcMCee0tJn0NB1Wo0yrT1Hnz8diHo+bDuao4G00VU82hBM5EkCU6X58wSPK5Y39d0nUO\nHn4Exdiza1nnBgC5bhX9sWMeuT1jWxW1lo98Wgg9WCuJU11VR+TlEeM+FKOVQRTr1Pz+sZNQxv7G\n5d93rqlCR8T4JnKkrFpEu0vUDzqHKU9hKuIJpFddQkwSB2xvH1Ts23XKgRXCs0PBmPhGZ9fSHQke\n6HQRh6E/R+JlmU00vuzxXNYgXqd9Ima7gLVPBiuGcv2c6w8sz9lOe0reW1OoxgvI4MANQ1k5Qp3c\n8cIsxgheBdrhp5iBVRipALi64MIShWbP5ZPoC0/pKzYVhS1qbqeAYfngLEsaGyl1GbQiAKOpwRlF\nIj8fVr9LS0n286kxnV9KaZo35NiXSH+DeeJHugfPaKqRPArvCi51KSMF8TRpImRrY5g12Q77sDQy\nuaSsxVmQ+gC+MrGhQk+Ferh4zGEzjSHtNC5ofHgArM1c+JvCB4xiTF9PDKwaSAZ1gS7diLNW1Bae\njLSh/zH9yp2jy6upD1uDSCyY4UH6LJchwsOuMFwcaLN+CgxYvly0DIo8bjbzFwfBkFpGByBmPOSw\nX+53dM1x29EpbpVG9DnxzhIEiTGtwhrwJbrLXT43mpBbRKdfi36hOpAPxzwxGmM2XQpL58RRNhcj\n8J3y+kVQZQrtEp/v5MaE00o051ZKzTsCgatNlb1+h7mQ/c7C4QiCOxC33qTJun7RX8BJo39ZrxTW\nYDNppnA5iD22u5ou7Y2jTNRktD7kCCFgu+pWxFz2NCOwx0LWL/xwthI4uWgbfvNB2k/63fFlHEaj\nE/lOWNFbj23yjG4E8gRNJy714aUef4Tuh7kJF8XPER30VGXe3k6uKrLNYFb/CjramGTQtoZqG1Wi\nNtwN4PiXY4YZV/V7DJw5tBEQC+OFyKd8PvCYSCZXox/xteCAfB1CGiTkBdDPfuo95ppWrd5sYro4\n+m/uYlT5oiDyS4hcdq8NZrPRJ7t3f6AEZyKJHp8ZmpqJr35SNV0Axo3GFIGOQMDxaw2HBiCFz8ay\n0cqG5lTZlQoSb2/5YRFNwgAL3XRgaPuzhiWC0+iZX4FfOSVo7pMENSc0SRR1oq9QxE68hWiSkdRE\noq2dpOWG019B4JrlXKNvrLkrMUJ5sH4zilU1RN16NshlO4pE/W+iLCp9yU3tOhdOroeDMEBV5sSX\n88rzfqWGbCdzlLwovLmF6OC4mjmrF4HPSsi+jJqVq2LoTCm4TxIAWNwNYUfKI+KzAGYV2zVKIdc3\ntv0Wqz2HF/Z+mmlP21Pxb9zNw2JAzU912iUJrv85MmEUSXlRqOnV5EpBN8dt2ng82MQtAztJzPj5\nm0wOljbovym9o2s68UWKkcVsW+u/o4fpmLEDu0/z7IJj39E2uS4Bl12w26sC0xzNue9Ykx4+XW3u\niMkZqb9QY/xdNNi+tFcPMQW/CatBNuqFXQfaUvwS0FxSHLkgwa/6tPKdt9Lby8Qc9UIlXM2UpJl/\nNhhYzC0x6EdFGNul7x37AnjCNny4Ub/Ww0R4cX8qod0lRCuYjc9/OQU4C8qBVlWUvWiqPj/h8D8f\nQhCRt8sv1r0iAYpJk3cZpgmuKHxm8jFvDjo5WIz/+22ypyGDYseC1OctClKvmM7/cVdn5VkUnqgn\nJt4FETNQvt7chlPPD1Blrf1lky8HAFkUz5s1KeXaTm0rNu7JE6XR8V3h7Czf5z1eFm5FpaVLnA6i\nl6gkI1Oy031mO6fuF+2UNE0kbZWVL/z2MovoMxd61gsIaH2gjmOgomeRnukJmCRVi68MY3kbsyx7\nAjDUjeD7TumBK+WhBzseB7EYdYrrjC0xNAbW0KTZsa8VJzao26yLPqoVlniszEUaEfmZIu4GUBZX\nvH18+FvNpADgh1KH5fdSuHDiDUnv9oODiC5mrl2wVb904J4khorffh4MJpK0Hyqb15eO2Ca0JtV4\nZjVozV4xm0JoXjRu8uL/nTLuVXTAPNoM3SVKkg1n280oUNhYvCX3i0WN5ylfMuGbNpcN9LJBddp4\n11SqFP1NXhuLwJ5bA0jOtdxqBXbHcdhaeMWFitR3fXFHOvuu8aymkbkfDY0gdRGGti7aSaKU0hMX\nHgwRHUVqc1iR4XykXmb7Q5WfcLF4ooqZtxsSikSNFHzAti/2yk0oMmHKWKyVyVjJdIxz2SwSrPSL\najb0N3knTHQ3MuD1lBFy1po5ELmLCBhy7+rf4itkuo+NQAIac6/zcKBIYoXi1zD23vt5qsgqoE+I\n0Dp90ubxmdHHTmnbPTc4+NNMjNe802tiwRX8CZpAyNkqWZ8oNywJ1SpJTAhL7vDB8KGw10MW2FXs\nnGOuoVn4I66Wj2AWJ7runJR9WAguApiSNyEhtPJ9f/zccN9yj/QteX4ipYXXTXBPY8cAUCzK+kOu\nYX4J5okSHWg7aWiQu8JL7aFCRdxLsadgw2aFgeoz9vX5B0AzCBF7usdHNbf0jEDami6RCH93J/m8\n2OgYYgL8Ej+KCoG6lvUB7OtCjCvIoCrDHKr9U6qbY5BHtKNyZWKLJBRjYgJAXT9v2Nb8RrAlBDkB\nfHRdOhwhcF7TCnh85ucoPzf9Migqgrtr8G8uA/mMezhbEr8QjgZa1i0Plo3+XCsWN7z4bcLKWxvK\nbESWGbRCbDxXRh2vLlXTlrKJrqt7Nf8FtiBJRUl6EPPL4Rba0BmI69JvljAh38P317fIDE4GOtIa\n9mBH4b3fi7i3IjZADl/THipU4HGXDKUo7LVhZ4WWooXNxMBYiHj2F9OO8d51cHckkNvwl4dDHfF0\ngX5x6HZ2Z0euPtHAxIAIvGN3a28eNgs1FbBm4Cj574vBPQ1sPztO3qkYdPps8yHnpZHu8LAKpnjX\n/Uhn45oxLvgkox1/n41E0uciB3IWvFt/eOXl1sE4Op++7BmN26/XUIdbybUof0JAEltx3flou5sP\nXd+BlU/qHvEJ+g7hhcBKwWZ3W/4Ugib2r3wlCRoKzqhT6iG+AvHfkBV08TRK6j9lSio1idWQ88JS\nTHQ+2lESdjCcCVAInngcchEjo53n+PCUerJ9L2ZC1REI8gmQnPT0XkhNUxwEg75EddN7xBVUaSIU\nDErm9gXrJvZQPsIuIkhgQk8i8CZKRfQibb7WYSuhc4dGRTCbAVa5NtFD9MSglM0bKlt17zEKpJEC\nVZllz9DiRMdzE6DzA3RxRnxsyZUYg+Rbqgy67o8VeLTv7GZ0hb168GMPVgLm2aoA+awycuS2nmIu\nBwxSU8jdhryhCanImlvv7n7OM9qDKeFnUHub7j5/vLqo0gUPKbw19DAqLrR/dBm4RiruWwkJL+Vr\nYaDpf63ayaEeAzSnD0cpQHU3ZCLJeBhnfxX0uYGMQNvJLhjZOUAZIKU+q2xLMNBK0s1Oj2SGLJIP\nB9ay9bhEDKNDG+q9tz0jk/lHWt+27PBZ2Orbru1IB6PGvcF7o4IINZ47Y61IJdvNx85lEXBrcA7B\nbbOn6CJjQB+T7JsIxok8+2GENpgNIZb6Bcgqp+lkWXRcSdm4Crhur5On6XLP3Smat8qdnIApPLs9\nbQbuEEgK4iGY0R2XON7EFDqcwpvd9HJfF0doNmYRnby4O5jr4dNWSJcrtpiL1SVKnyGhInFEfQHQ\n+DXG4xim+qZiObzxjxlE91J3P7ns/Z4agRzKnj4Bs8sCFphJUAtf1b8M6ki8+wqxmoorOBQ0TSW2\nfic1JdtlBxtJjj96bMWtzNWxqmdMErlwhYYmgLITsu2NM4iCAfcGKBZf5/2QJAc6KpuJ0YXmAr9P\nQDh8+p7+bfBMOizKNKsdDJpQoKd+BK2c70R8IalyjokLs1SjxebWlA3xdmVEjTqbNeiC6czWFnc8\nMh7lwb3BOc6Ndlx0fLvO1LygzG94HCJEuodp4BDA/XekIbw6e2jXryvJZNncxNOdSAp7NhXD0MTq\nL+eYms7r3dzLqPnTIoOapuMLt9z6pTGSFu4prxt3KfZEY/tg5m2xYjs5S3UTESqK8EGQ4Uh7mj2C\nmeTpL+NnPHN9D6Tcwlf2wKcwzEIoPFOH+KRGp7qU47u00mHtM1w0CJBaprBpNYslLWtgr73bM+TI\netuwVX9xMdE1iIPLtqDKqToNmwqLbTqYbDF7AhnuGCclTOQO7rKzXkiuu2cgkNXs9MDcgBERnrlp\noSmH+1XF5zy5EgDY/aj6bc5p8COX9j8fILa9GWyrAzi1rYG+qiFjYiaUKLyhPeYAdWWmMyh4i84B\nbKvDE01pJCRGteMwcLryJl1FlmrVWZXeKcC8QAzchBBp/Jf37YDds+XbqrZ1m5Ume42Oz+OwaVx9\nQEp0d3b8U+2JSWf7DEIHq8A4CPn0Yz0MR+6IFckEv3n37qebhFORndRzGMZYLwBPz5F+lDjhD1nN\nOBG8YI5McpkZKsODGLCYC3wWWtO9//k/syJXo3iJiTHAkaY3Pk5xdKwb9VUpZc9922a2AA284kJS\nc/w6K1tp0gLU0Mpr0z6sOE2lMiA9auYS/Ut9xt9km5TLfRwtApCrVpLkRpuATTyDkPyjw0zHlluA\nDR8qhNAd0dv12ExG7HMW9hu1wx2tg7gT6DB7czWMjfl0oWfOni5ihNtwEk6CQZd28NjZhRLPtWUH\n+FSLzUGO6SUc7y0gXgUKHWWu6ZLCJjuzVlela+dOL72QeEaZr9W2zZsVyJuHyVD52aVnwTT3AOFK\nn35NMxcXw8wKd2P5UJy7K9ud/l3TB787S29ZjoA3P2PfHD3O3ogtqpAvHFKHvQH6FCjFAhfTNKsk\nHErVZ+LMGHXIHVT6Z+l/KcDRafI2MULITYDczj4T/XSoW77h0fPEHYqOvITz9/+t1jS4SF/xhMpy\nCJ+vM1OJD717OQYw3I8AuWVAKbEFDmdfhO2gYi1hMuJLe7msDDDJmugXMUoF9mrZsfZexfV9i3oi\n23Wes31mp6gUDeJmUnRxu8vnEXLXkiWl/9u8IHC7E2XwWrRrQjWJ0kfamR8dvKkDDNULew+4K2sT\n56U8REcr3Q7WZl30N9S69uRhCs6IfmjziRSl+vlcdn4FfriLuiXy7muqlQV0Clg60PupqJcebXH6\nBUv3N+vgcEBJNag9MeJroiptA5SBkyIwauhthJkNyG9cjMvY+Y0bNjtsLtZs343tIffMIGKFux57\ntQPtlA+1zsQMMx1GkhXVLeWNpNUusFkTpgwJDoQLEOEi8Zp614efkCcYVhmJGzjWSCqabm/Gw1Nj\nJ4Ik0tMKnueBJdhaSEWWsyIg7gzCo6ojbJ/1WK3XZUo8cSbAmj3NpQ8f3K6RGgsE+d42pR/T303c\n/Z3Uhu2BKb+FQ6s9dIHtFotmPfqktj7KhthqO8zqlyNKxItDaisn3SMELHmsayGM/owrpF7nv40K\ne3ed0W7e4bQB4884HK+HliaLERfHqfd6sojXuwMehsBRnJoO8m8q7ahZ6s1LsWkB+Zksnu71S2zV\nHiUZFid7GiuHHiBUQ7Qd/vPMsMJp5bVtz9D4AP3I3dU61RrSKIdqL+KD0OMmiKLD1s9vfq/Lggi8\nyDYOXnEaPvoLPpgMT75wyaLD6A0hux7nQa5XkbPzjFu1KSD8ZwP3SxVWbxj4j/8Tzh4FywINBztF\nn2rzHSaTZJ//RC8teqLSj6JWF8TEBft6NrAKWOnkEeiJ1bjapFbu+Xyc0moJisEfKi0XSUhqo0ZJ\nvo+Nkd9+TnyKNuD7VUbg4gMLsUjs7mfxUIZOcoNkcwrH0C/4n6c2WEoFq4cd7OfYh/pSCxWV4n3x\nxbmPFKTRbHeiuvL8dbAskiR1ebL4RRpvWaeM+4p55Hnr3ivCoL+t3xpR0JDvaq6dyUHXNbah57hJ\nhOWl8WUzGzQ3liqx1NFx5loduc/et/E44cmgxsaUGPrg9EcyCZ3LnhBMH7HJyYsqKWSnevkH3XS0\ndlQkPwd9HJJ6GwvDI5twDfDft49yqpn1LCdAWzFgtEquhfGIISyZRrOYzqkfKkXNSoavO7FzqJ5u\nPXRF4tJdvSlIrbdeRCN/Ru3p5rSBg0ipHtF+YdGXE++Vo0KAvLwFCBynpEUwYwLmFI6ab/wmzDEt\nPfJGznXMlE77hq2SQW8HU0lyYvPYMGpxZxfiyPJaal63xXG4+I5HTlYhvbYcEtXEwlFDuFMuGhzR\ncryuABzlVKTwMFcuBnLV1j4SaflPSwDiIrvcgc59ZFXh1InS6sDvwvBNCyqeuySJLzlUVZ6wuFcI\nrvDc/zMvFRimVCFvYsAlNyuXRDoaH6xbrVJ3rp3Kn2O1IXDh1yB/RKT/G+2HcP5rvHJL3ELRbZuJ\nieInGchMdkenMJGUy1maicvl8bwhYOb6T7q++1RqjyDOc6kG+bGxCEwGjwsHMylLReYe7fA/tld7\nZlOvMXTPD8Wr+YnIJQbNBu3wT0m06a3nMCX0Tf8mPMOQeujDiCxxBKUNU1Z4gUkdM956Frg/AqGE\nK1yAtEJgrP+R7Z4492iBt89YoCfexnBVxaWIsHhy5oy0Gbec+N1pXPvIGK4yaaLUKLn39KYX9oT/\n2kRr5m+fbiSVE6RvSRlihIvzTM0ELxW661/yQWQ3SEB3IV98hF+50e6Qofx7DMLs4a3pNNPMBuGL\nD5lgohDSC8CNH4nLId9yG7gsqxXylVWLKrFltKhvWIIe3Uhb8JG/qQ3posjDegfujtrmpc2W7H7s\n/FvHykVCTUfdYwybgi6uam7nskMH0JWOGeQi/ReIQgbyqGEJ0skd5h+AUDHmwcIYx1j0JtWGV0A0\nmb646def0eNaz5NXkKFscfG/zjwX5yi8+knp6y1K5DqQ5gSM7PFvWO3gc6BzW3QOKRZhwHI1FAaM\n+HHPxvSNMHyntRLaEXef+qV3vRUoAgVTQpadvT8Er6GaRMyVtoPUBLaJ0l+r9Ab+DDx4oAJBQdAy\nhSmfEmWKxdh4jCVEvLIg9RKw/nMZ3g17ElSkyV8JmptZ64i3nwISnFKTqAdaEwoCIDxWLYgXRH7B\nmkzrk8wzEG3zU6gr3RRW3zcpdTqWXJhVVzF20I1vgVqvlb2OMs/D7r+JqyCs71YVHigTOhc5oAdq\nmB/cZ1HOdX0H/45grCiX/WF2SxeJFBUjBzLF+vzOpruChX4Z29SXujo5mumzxkGUkz7ODmqPVbvC\n/qs/p+SVyywnPtg+ST+2NfP6Qm/GvOpc8DTE0mxKNlsTsE2Zo/Q1esOj6yRa8GAagmaAlfvxdIr2\nqQ9GRxzMW6WmYX4OtS7LZcUTygKZ66tKmEmiDT4ysvYlpXwj8Z/+7P8/gKISQYgRttmULOT71oQX\nRIUxl8biceYAQqmhuFWA7+c814MC6h/TQDmQFXE+5lRQlFFNLJeTOxxA7v0x8aDRxs+dw+Ws4CJn\nnF7tPsB7rCl7FNdzKPRG5Inlc8b76YKnLHN8PmDIMofpVmGH3vxbUJPmvoa/Gp1iSAyeqyO6DPMn\nOBEifX39xJdcDRc2HCFkh/OhEXGomdtpu6jtlaldzyxjjq01Hl/LKo7Vo6FklHLsOoo91ViQYEDT\n3jMHPVxSWXXHW5tgH/Ur7RTFxAUGJYfsw5ZHWqXl7hi7MBszl5Q4Zgmw0BwZZbrjBYrMT9ih+TJG\nCIa45gtEJLuoelht5168UiFEo8HXwEak1mCn0NqAnOG07YO0yiFxOR3N5XjH66iljxcI0/oM11ja\nM3jpJT7sIjDAPnJ8HpEkp0YHyPFnokJuWDEvv7j+tcQ85BcAWasVgN2xwJ8c3kOevuPpg3LLjegb\nwedODw9VxVyFUytIpddFyi+Ek3Ef/Q4EszVXZ7wSrZdqVFjVI+PEMaOw3lVur0LxFWsyTaf+WtVp\noCkznzxdoBsTSh1m2znlZ8iufzwiVZ+2k2zaKw8CGe1kw1Iuhi7V5LCdWRDup+eGBrG/MzqR97hh\nFj1+K6JVm8AdT5y3K/iCHnHdmkrAJe7LAjTKAVM2Ckd7mP7mFisLqir41jGxjs12Roi28k6szUau\nbxE4s4wOUxEE+PdrvL4sCjamvasmS24xaw2+sy3UAJ2/HTHf7Yg2SnRGvXrOx/Y3cHbhGP+aDgEb\nKktD+hEx5ivKUWMjX0ekgNUtkg8rP6tFM1HT5rnQe4RKQs13OgvkBF3dWaXWzCRx+xYycevTNusq\nzV/PH1N3W2ZPjrNNtNqwzM5yWOftRUiKNzr2HNyW2KeceGx8l0O4hG2A5kUOSsT2g3GUHVLNl5NG\nNXshenvVTyNS1iwSJzE1mXaMxcWI8xX2ZFXCTTsSKPD3z+Vdgaema+3tVmX9SsUAG+55jgwM3MZn\nntgcXr8wwDDm9/62v4asp+IvfpDb87r7YPj3AwI5u1Q2vWBBPaGRYLUe1YL+KjVMZkTz7yC14/kg\nKUcmXoJMX6E0hYYJbvsr/GxHEmoe0yXgyplmD8z8VHHRqULysYtJX+BomMvdqMSiXMrC1ftqP6Xf\n5lJLt3R1NupQCDd2yg1r0GVoif5x1Cg4O6/MztO0ot4PH13EP+8JhVoVyIzvLTsaG3LpYiI/E04w\ntvtok0m6B1GB1IKYOdn5UhTnnOeDSF8yqSsJdT5+W2nf0Mw4/nPefv5Fi3tEWiKG6MzYu5gAKqyX\nYsM94IBtU4+PjmNVbFDMQqspJboqD93At71pujtI9Yyr4NGe2U7LWqH5DJFqSuDwmUOpkT9NtzIX\n6Ykdg9VGhqU0BpnhvO9mlizoE4kkFRju4BfRyAmukFgTSb32zFRJsA0LLfSyOVbAZk4QIQYIBNOK\n1itbIDXymGcwdFMDHIxFkuj4VBJ6Mquw0sDqF7vVqSSqeARjBK8VEv4fJhammre0ZyavBbU737X5\nUfQ7aLfv/6SCeMYcZYfIVI7uxuSh2yqrF3veYKZiiNavx8Ve7Y8xap/jMfza9JtAtLOt6vgnUjK2\nY0tIRKdGEigJRkc3RXVQgavCbuILff4hg3SLaZVnBhGWAWV2CBTT/gWgjyw/DI0QBukw2P0qTy4v\n0eO8+qeDpwkbzPkDEvV6wrlJwA+bxlDBBxmCgkD6jX3Wl3LXyRqU8D1AYPbJk8/Ai7kKu1dHAi5H\nvZZ1NNIHI4dRuS3IlHtfzaYGr/2+JmvsjNrtVA3Rtq1x9MsHAwTIOE6+2RYZJY/qKW/AhkByIA2q\nzSh1zpWYmq77b6nx/aONic35PMRSW2JCMY+T5HLVhjQqh7tW5eSGPem7IlKhn9sJgRafYJhjbHjC\nkENxS2TGESqOUIw/w5o3d6DnInjBwcCnoF5tM7l0/rhqkxV1NH4tnNEyw1Ga8uaXKvHynOVE6lKT\nsMPfCAlPSfWGZy+Fx8ztjrXqQBm2eIWzC1+5ctxF8z2ITBViDt6othitax+2/VuHm5nRlwdzHjzQ\nshIj1OgtYd2GkFvojf5/hG79QUoRnxDCmRksNc51B9l2OiMNEntpIzx+oPfke9ZOIK0ixFNJU8BO\nt2dd50MFHemU1q+yhgyeJLhcJk4NSlqx6qm4CDxjG+6WFkPQPPX+Xw1HshenS4V4k2yyFz0nzU6i\ntLO75/btg2GsAQMENk4e3YRZ8Nb/EBQo2cOba80ASIzOzxpVXq8pPqJX/hSMy/djXARzfibMu4Hn\n8m7Iu1/RBZf/X/W7tjv2NcyIWgMy8q0FsJN/i9YtagiuR1ZohjiKb0xkZwkfeVJmUXuCiyB+nubx\nwaT1LAYKlobs+U4ROsQNwY14dQKQ379GafZR1NtJfj5NMMXRZl6TOFaZBsxe9Kbh3Do3udKVzs2D\ni32A4mW8HUwROMXLUXpyMzn9X0rXvM7Ef9Ld0xY61wew9Rrxwei8YVlJgaXytu1d0ZPkJZR23Xvw\ny9Iw/ZIWOgvvmnzyitpH+oJ7hjltq4AF3QBBQI6Of5yvm2EwRCGqLxspPgxuO6U2+3yltWBjfnn1\npXTYyTSBLHdoWoP2orkWjwFfKgBMnimJMfhp6BsdcCa+1oQncshZZk5HtNvUHFcaTcBEG/1PE3yv\nFwH2oCdQ7DNsD8ITEoKwUUZXaZcDvEYju4c3FpKZMpUImMJBTjgTLhAJkoh2ZalfJHLf3IbNLmCt\nuDQhwJni81iJA3bKwWcauwNnhTTTkGz0BJnx8pgM/ttQKz1J+s4zap3Nji/DMKWT4bP4GCYt2zD6\nyIY8h9iyhL3bgmYfmFAJ5z6FgbJcWiN5//p95xzkoKaAmWq8bB/qHQKFcPEN3qsWcFmZg2v+lUql\n5c4sT5GQBsZOIaN6hLXcbuBPNUskEmv6opS2zLWsq8n0CAbB8kzlR853B73iImgYV2YeP69BCO8T\nHtlm57drDF7XvirIQTInsyLhQ49a5O3WPn2NYe9pK6sYyiclFE3efqqAs9oCOgmNf49Rk3erhrHm\nXoGcLrwaPpjYfKiDo2jw2BFgabsKfzj8dliDIyS0e+rrT60k/ZntazsdMOPTx8kzLROY0LUXtMu6\ntlXdWX5uxiDe3mk+UlYVmTu56F2SvQ47HAFj4BWEZ4q9MGTKtmt4BIOr3uongvsWnzQRp14uF/yQ\nsEIDOmaaIMg/W4x9FyttQNgQaFRJ8b9B08otcQLH2oZ9wqjZoF5mkuQx8AG4UbTOVvfe2yj3/kOC\nVK/OfyaiJLTL4Bk2StaF6VB6dz6ZE5fMRxXmPvqpGWjv7zDnNvXXpkllH+cuixrr0OmDO4I0Vm39\n23TIhJUPJt+8b+ODtseo3On3NV1tnoKcObkmRzFAQcwz8xSP2O/+Awqeou4aiU2FQL9joaZcqCMG\nafhZz37qUv3Bt446BoTiB4QGz/LOcEyXolSKV+IfDTZzJl7toGQZ7Aqg4wohPKoZuyQnfybaoCYL\noXLdIad2k18KpeEV/Qh5XI61PN6P2Zi31UWvQf73Df5yGbU6QJGOqjdDQqrEEWhF0Z3FMBQgmOLP\ntGi24v1xAMr8t3YtF6mSME9WboB+blOMgVZqx9tdaxxEMj6CAFR7QHiRldIPM9dz3FHcUjCaUN7m\nCg4aMaceWlW9RKackBQlqVfVIC3MMGKu9dJPSHa4Cs1e60hKD5QidTWc3OwxRXdPbzDOROIl9Ly3\nAnK8u8it5J2SKrFvh/AtF7RONh7hX6Yv0OMbQZEYdQRphuNG+/5joFAN0FViCo28VvzRn+U32gsz\nJFjvG7CBccUtF3/SzJTOCRmeal6KSYDWjrC8xT5nVfEN8ik8dDRdvEFlwENhEa4FI+JxEMuYzpbq\n48k4OvNbdsz9YcLSrhiMu+fpC3iC6wn0AcEsVFSewyI357cK0IH4De2iLHmwnC+kOrdMiYOkhEVc\noue7YWGmUDNCEvhGo1VDX9ov6rx/50pAF5ugzOd0600+P9OZQb61XCZNKaN2cRegZKbtthLaSwjM\n3dg8IRMt+J2u/TUzvT/0O/LcCGRtefIi37fdhEqwA8HXy5FQ3xL99QR7Pecn0mCyjEzQy/v0oa5o\n/L/fOZPvIyI+0r8gmjx84THuroakqvrOGC2y+O6RMkcrXBVv6H2yybbv8yWEWIni7nRisZ8JxteS\nxJx58CGqxX/JkjXmFoHwDXjjdv2yKlFzB5HMS7FNMmtBWwS+oSRVtglPJdMpU9u7F9BRqrtwpZK7\ngo781YZSBIV85g1zZFf4t96jZpfUkd0isrYhnPeozon4+fC7m+NFNs58DXo0NSSbORMjgVNyZIKB\nvD1MXkJULySUvu8QqvrHYlVS+TZCj5tSlt8IVcDuLnJu5sa6p6l9Ad/XlY8qzx5hHR+AxxguC+fV\nlZfw2KoXDd0ZfB2qbtbTtXTRrMbEL1xpX8rtksswuHMnGq5juDh7Cpd9nridkZPEiOauzKxsRRI7\nCVB8jfp+2vI0SjvSffxhG3T+/vmlp725nViP4B9tEdwoMtpgd81dIFSk2rpwdVVlayNE+IpqftzH\nEiB9gaK4fEd4+Fdv+177Xs9wg5T1xLxhk1rJKrnRQ/ob7E3PVHjRnZqbTn1lN4m1OE9tM1tEA2+2\nkcETTxPY8wLo3islGIiY1ixpRjeEQq105WXt3NAEOen9pxBSziJ7znplh3Bv5Jhfd4LE+DH+62Q8\nUri2paOD3ASb5LpWvWlIBO1X0c0/GE9yYkw3UT0R90UCvMSQeybhF6LpbIvS7Mj2N7UIDNktDlWg\neoIj8XOGvhC7rulio9/jhvdoMMXW/BGwffJ3bvW6F1j8ofBgnNLf/sD2+CBwmShcJnktV917PB/c\nGkwpiHYwifvb5QsxDC+USJ/6bS618fIluvgemawe96FOvHXuOeQBO+5AAQJFrv6MOETHaBLyxkZZ\nhdFiSwbWgyJC3tTQthStNYQ2Ijqcq8pTeVjc97GyA0FKJAmWDs738KR7ADaCIAkqHkAD0h1MUnR9\n+FbDRNd3OFbCyEZHJivq2ZprIyi9jlHy0wWhXcjpZQ8ol+UEjQTNjbOG3zpMQoUn113I+jr0Gc1S\nTM87ulMhgtzr3TJ7yKkiezPUaUsGLNkJulnKZEben0CeifLkqxfqUkHJ6keOY4liCtxP6/5Q4+wO\nHtduaKRT0bd1vD7Qqm81MA8B09mkDjn2wISomez3owX/JtP3v30LM4K7C7FcjQbHPR49D28EA3BC\nSofi9nkwue+1K/ld8/Bp4ztCQAyHBZlPEpXaZletvBOXNKVHythVgvrTcQbHjUFtOP+9sgM5eL9/\n9xE8khHPex2eMJlYRYEKPrB+RnCR4F3kLYhSx6no4JF1QZ244aj1NXW1NJE92tzOUv7oXvUSAjtI\n5NlBtojAsBX6hxmiiWktePYzERylLrS2omlaxpcwptQEhEMmJS5IfIZJwAgRbCUmX9p98mOqg8+w\n9ktHLbqhVXGf/VbQ55MtRysucuCbFGSbHRdwch7bzJxArfGyxSrFYvM0x/RcGuQ0IweJsY3RdyHg\nFaDJUVNOuZh7yQ10Tca8Y6CzPWA33cBrzqe+DtCn4xWfVmsJwH+RCrljc/+kmStNrPqdFIscSq8W\nz53TCfMW+/r5emiCGSivPAgEUkmqO9Yr1zvHlr4ACSLSHIij6m0KFFoY8KgTPji0vV0i9UwEVr4s\nndgKGEl6X3JoHup/pIDAlbDW9qpn9zCldTtqMDkpCIFNn5Jzz/C+aKzLPDkhkHANF6WBWgl+k9ng\nJfyDERt6EgaSw3jvDjEUGBLWY+Osf4EUumh1zolZ2WxfKIZJ+LGMlk45NeP2yNtb8eKIHUjfhDuB\nAAL78ilWKyuNeSNEneeEKkJkkrDlWGL91FhvkgJiOVKmhuk1imMe2W9Vq4nf6LmSA4Gd4x1eAQ93\n/HhGxwyqJXiSTYoajr1ECwWCZpGCDCtKnhZbEaeklNh7KnPZip/UiId4U+Ll5eG6X4anovlPAZRX\nuN+BRI3VL/HAyrXrkIeFc8Az6/0y9X31vvZlo/cVSWP3PJd5xmelp/FdD2tmUCBh3HE1kI8w4tk6\nKnk0Sl4a/xLXX41mvrJcZt7UGip9fNfOxSoshDLNQSHY0ZZWzwK2M5r2OOE7lqrYEFek3r/sw8Ig\n4bo2+VUUYk8DiEfP0Ug4bKeS+tJk0D/h8nP81R8rz5pIjiZIvTPW4qaL3xxzLNIkjNMWKnHCVA8S\nqz3F6rOVLcRxizrNh/gKRNTTobKB2QU5le5EpNTqZi3brLiIFrb6j1WgRqrKaW0w+E1Hv5dqUmAC\ndygR5dP+BcwYOAoEb0AIQ1Leig19elwk9eQqk6CHHnHoizGmpwM6wWTvuBscCYGynFSduqniI3cD\nX3Ychq+IdmsbN4Eia09nMLa9XT/fgQ2NhHqmr0hhfHAAGsCIm3EL3SIrO37rLXaM9Tj32a9sE8Sd\no131hv5Jqnl38gB2e7gywOI4s66Yj3/gijchJUOUus4vPZ014cQOnwc3d24pRu/LE+c0Gd2h7b8h\nYiLxYPzxUKLOhOcV0ng/k0dVwgwZX/qtCqLJjIPMWZoKBl9XSg7obLru+lEBnUz6UDcynE0yRAn3\nJ1oHW6CHnGACh2ZHMRkcnR+yyiJOaiTDBYoNhUjJTvuC9JF3wK3mMHo4s+QUKIeVuxN7/7EW2ExH\npSKwlBwWgU7D1glsfu2gNUr9AXa37/5Xj4crYCm4d00LBssDXNw8lTV+za2l/ga0t2pEglG7Iq0z\nV8osC9aVgapXhnBeagIeBGgY/8HedP/j5bUcRcrbCXoYqWLDJf4IwwoigyBL7TQhE1qG6V6O21dk\nbeYFLG7kIXwkr5uJTFy93OwTLh5V871nGPNaVaGP0DdMNkTmOlBt5beUabdqElBWxvILKqOr0ynf\ndBqxFbUpSHTxH7beZxZQfgNPu/M4V1A8KY7L/t+HT91HxIP5QKzr9xxkPH9LclB7bfJLIagBQPDS\nkggrpbBnJjtJUcWyEf++hLMI6rdTXlYXw2Rv098jxz8PBtS8/0WtAesiXUQ5llqkMq6BJh//cbCL\nsq0efXDLyFcJtW6TpSy5YyY7aNVkjKzLNavaN+mANVospWckzBwgT1QPt2olmFsuj7JFeK4Zj/B2\n6F4jxR30unHQ4lDf3ga/HCQSpuL4mJrfNyzlEK7F5fmH+/s8UlJGK+DM4CkXv7Q0f237spoSn0dt\n/TI2zupItZoXFpvO3flbGJYpheAA5zhlAnTD95j6twP6V+5BOzZA4RYKW471/7y+851slUNQaqXQ\nCIp9B7OxFjblSZpJV/weOapzR9GGu2WUL34MtsBCFeaQzFx2MLNzu9aSthoU/PyiFjk6Lj/wLaN5\n+zyh95016WymScCXr3F2EFVrj7LC/FwmkAEIDVDNwfPJ9mpoiZ1919PXirdGiVkPuOHPEcMapDO3\nsnb1NVvSkj2CnbbZThL0GPImnc/t3exEY5SXPx6ybzj6T94UQ27BvPByC7kBOD49wmuyviRXcl2F\nIdqUOSbxaaiH5egftzelDJOX1vzyR0YubGDtY5qv0Umxu0Omqb2Xt9TMZdYumooKtV83gZxHVpXK\n99GAZz7+qyLJ9F/AWEycCeWMqgBIE9erlLg/tn0sN6avwR2/nrSFNLc/EC+/bGOUqJNj8z7IBPGB\nfQ8zYY6PrRwjmqPZWK1+Jv0AUJSyUZhJmQcLbZ3Z+Vf4gcrML1Zn+OIEWcvmRV0uMBfgANh4GoHQ\nooR+sgjc3g+XA513j45GTEqX0J38oIjuuejri0o0s1qV3aX1ZDPVFs+iQT5SOlBgaFzniZFnVR+W\nCJMWoFnfp3lRaIAae8dptvQ+z1lb6WbF8E00LnfutS8fEYN5BAvFUShschcve0aNbO2Fd9ZwKNou\neIUdlpNR1xw2YRi6sS0bsxHkj3w9dAhof4Ive4XDr+wdEZR1dcMdReAFmPe4r9M8fAC8TcD+ziCs\ndAyyiXjiTseYpE/SqL45QNnUX8wU1SY7Wkmbj7qB2lFEudgCsl5DvKwNnwf7NPmKtQp4fUAIqbUY\nWawf6h6LleeFJFFbANP6KS4s18rl9e7q45eRXFkkz0xtSYnNtMIqRatPqfLqaYYHtQVlgdJCV+XT\nyxBrVvKWjtS9dGambh+xqG8anwDRaBsvtYTPFjz4EK96d1dxSwc0cs0RZjzQWzJQX2MZkmVDrH9b\n1IzsV9C4oh7jpnOIXc0TE6wi4z5ZmWJDp0R92M51XM+2/JLAjTcmyXbZC1ZjT0uYJasHG64Y0rh3\nsJwZADr6qIUiYINbRVOTY6U3f/Ef+mLQdp3FT/uIg8zZJ1i5GPCy+N2QtXSl6CYryLARFRB36LaG\nUyv0AzNpTVkQ87Y6bjQKXk9PD6vN5epC6J1JmAnmvqK+MlsOBAhm+9pDIdTq6WOAyNFNsuYuo8Xl\nBx3fvu1Zxq2tumbbRaA/i8EDFX/m6ykEO4mFNU3Pl8AV8tn3F3Lf7D44Kmyyml4G5sW/9BgPRbh7\nThxIO5EGz5VFq06zFacwQLo4pLhRBzWLoz+UTHQ44EPlr+3tHCGLVCTWNIge/jchsyFhcIyREanS\ncZ+zNPVhYNTHufWAbKLcDfc0yvqikPWjy3YzXgrbodebfAP/eirsaBJZu8NCQijcbn7MqRiLl6L2\nRteTEVsUyGhODDCfc8VHTiB+ghs3tvTA7+Lc+AIh3t3hNDVH/PH8akeoG7vA3ygHGO0tq0aWP7bp\nduwFCxjfG5L5NaGxRRvUuxDAMgYGInp+NK1+q4jQalIyOLj0kbP//qXFTUaZ9n7Bg7Dp0ujKcqcg\nWv9m/ambWSMtb4uOOcUJT+ifnHmxRO/bOGJGWJ2XPiFn1EtK/ZpyFaBZE9p1wmm8hONEAyILZwU0\nInke7A1LhPXZtTe9ocL6HpV3CZ1XPdIQ5s+iZvjkez1lXN8t1Z2v5BX6rJ7LgqcOR9e7MIgeqr/z\nexY5taAnpUhmG2oIWpNjxhZkKyZkhjpoJu3Fk8j7rVo8jphKtq44KyhtWEk8kL9N2jjzoT7uolgH\n+JObgjkLvRGUcdvWzfL5ag53dRhXyYZsMcON0z9wJmh52pt4CN579yQnbOpGxqSGRmxZmyhFdqeV\nl/p3Gik+8kOPQ+gyvucYfwVhItuwMC06eQ8nuLiG1OJXO76XLRQvEutgU89ZUaZERvWyx0GamYV0\n8nHuCgqCu6IcTwqlQLhrmqM9wsjF/D0T6x4EENrezJNhCMo/69srqn9pE3e5QhPeu3yH3aeqQ/Y/\npYaMArkanCFNUV7TlOHYcqWP61nPzKuVcbmxrpXHTHLQ+KObmfOe5D03iRRGxRl3Aoabr4MUXLSV\nmAWsk9JbnNnBa3oBDusnLinaCrewLFqWjnSmsB3QZGVyxEZGV5ppLDHayV5+Ojy3YVHSdq/o5rfX\nELHj6S4K1KuTvOKug2G9AO6DdldTXD889WyZyJA9I2rl8oOLobw34Z6lr3RqTqZVxeN3/qkMTmVN\ncH8yYWfz4Eejs05L2KjwOOMy7+WWVSDz2SY2Yt+hvoZhaSYkwWipjl7C9s2jMkePlTYRFsCuG4bH\nT46WPqptd9DjIKj0G6IV8Nb3EOVRMCou2kHyEsnHxaK4LjC1yHDP7GRoy8wGHf+03rV02t3T7ZQu\n8KXrObaY6+U7BMIMpvjEmouWQBSg/TeMV8gYzzjMBCr1CjU9VixPiJ23jAUZ6PC84twcOwrPjtBJ\n9Ps9St5u2HpCF0R+dQEiukM0q+ig6+ZfxnqtctaveuLes9pQh6VoD6n7YWGkwVhJWn7Zcl4Xrvof\nb2EestQavqVV94EqwxZw+J2l0wwyjStduogZ5nR465etBuSmPyqpBEzFnv9m/EnvbV2KYdmUy+Hk\nZn37bG2q5a9Lf2SCz2kDknkESUlUo42vrqlIJ8ZljplfrHZvylAgNE5Dp2l3vqamjiMsGkmp5QX+\nc0nbzSWouRIuzsoB5gO1vkmZgajbNKZNkOTjXn/02QayhahheTOXQQ34eA50nuUFBIKcVSk9VdjT\nxBKiCfJnXl9rbX5mY5DOCXxQzH2XNyq7O1f8EUA4tXtYRpGUQc3tHWdqhQpvQblU1PsKFkGT9qCi\nJhg0kt/bLsRiOrKIF+nFMGNFLXYB9pf2+d97R31NRe+r/4AYED4d8y6GIOCqaplPjN2GFmdJmXNx\npDg/PfS5R2trl040plZ65yP75D7vqwV8RYw4R74OX/KMt5rkub4heCpsFWaFwLmPfDax9NiA7uMR\no5AZrTNt67CmOlYKYKFsxPfJx39EDQdqIoPHwZsaNCREcbF8UnO/uuf/stoAIMMKzOYU7Tq7wk1g\naoYuHsh1zOsPq9M1dsoLQQvrIVT6mcslB6L/Ya5HfoO9xLwShFQJlDn2BFP2bk2ZiDwWPksJ5AWQ\nxPyXvs5gEI7K5D4VUc/r8JRWeTKahIZC2A5uQ2l8VPpWfYQm4fXmMOatljtRnW/jUxjHT9oBNKkD\nqVxOF7InA9LrqEPIf6W9F26Jn9Je3Kj61enEkQT7N8C0eR5BO98mUBZsaTHA9eO+mZ0zY6yBHH9w\nIZIhemVTpxVzfFmz+eyY+2xzs1QnCrg45RzeEvUu0GuLNpkx3xg2F8iVk3kuhkgVZaYDYxRQML2q\nB5GxzJuw/4Po04A+WUBVanjXT9cSSB/HkPXdN4eynZIYzpLITcBi9mrSDMoFtv+a9I3cl+O8DdCa\nqYUWNoqWg0JsUYcTLCtR/Cwpe+rhdBoyr1qV7Pb+2kMYHZ4CPYgQqlXzIpsustkAlJjiy+wK/vBl\nfzqHsdM+VGJuL/5Pvx9Z+hmpNZ+/09z+Gl4n3Souu+Zna3gXbBPm9hTEjkEAHqWRmKIC/tcpnWu/\n9m6eym927TklGXpNh2gKnbXQMxUcNaVdt/EyYOGaE/X0Pp6E21GZDj08HgjvlSRZekC2FFww9ZSL\nFhZmCjWUr77qriZfhmaMYo38mtWIC307XLh+385Y/ByGaQkEbR//qCjLSMJSAOi23zGlfD9alyS7\nyzSbI+R1nKYqR0pUJVAv7NnRxVW6IusZ1SyRxgGDUOz2nxVk6QmOQBg4pn4OK1/hkWkCdalkr5VO\nle3IXYWZBupCe/B81dhLl66IemjID2jk4M0Fob/2a3FPpbeoiBIU/la0Ykmi6d0I9RMhyKhDo1NW\nH0kHSRxDD65uGyhx2iasDN+oCCmTMcVoJoAB8ihQBapgDRQKkiJgykvor0GVGVlJHThFcc5sOknu\nEcHXIM5pDSiYilxbV1hOiZFRi0zfKN2C81oXkcJh69IWA7MEPvKhP9XzewiVgwyw9bE2DTr+vqKJ\nGpKPhaSYb2PCf/xMOkKw/2IxZy0DvldZQIz/H42mRGnxqK6GJOcbc59J/CcZ9wicZ0vlX3dvdCSm\nG/tCgWlIuQo2mBqDLEoEyrSrg29yjYYQ9PEgRsJIeh2C2wK15n5uJ63tt5OWr5DLFThm3fkQbXgA\nXzkGaTJGsD5Gs2Tx+fBfn6UyTOK1IVwPAN2zlwML3qEovVHmxCxxqtRzmdIHf7GFU+QS3eF5ypJb\n0Wkqgu0lYdjYtGF1HqJZ/w8g4N2UtppxgUKvgsuArP0ddOyJnm6Orag0C+mU1jVJOTLJsZK9rrwa\nVqnj/xAt03OsMP7FfJJHDWN1iM0JjKx5TLVesJsyMHgC3fgIwfs1WJzkf+Jfi9zmVIQRRq4r8iWC\ndIy7DQ0oHJAiYGNlibIGm0pzBxeWw4gNavG4UxYrnq+stF1WW1gQ/LowmenwG0Cjy8d+i8DiU2tx\nqE5kkIRLYskE4J6IlQRKWkbBdjunTe0d0Y/x9vFKR5vbTOuUbFIiw4mrAwCCuC2x2SudYBNzDkAb\n9mqrAKsiJW2MMW3oV8nAwZmWBbAr8VjbeR8fRgoB65KNf98+GVk5xezWu6x/lnr0CSqNhgP8Aa5w\nQB+C8B3rl00CAv4LtcFA1OSpH9mVbGJT9jlNU34s6OS66nmJrHTsunWjWwfVT/YtIc070EwUHhu3\nkerJEV9OAsm2mblaCWXdeH3oJzAWOt/S+oMvNdV2qbdpyyJLWi9I1SxLtlFBqPLUdAhPAkz1jsLo\n2NRCg8YRSi+yN+uNbNtBQocjb7uBxCeT29n3ml3LzabvmlOf6To0cuq0SNOzxR9EqwHpiruBbcoa\nMBc77aBf1a+9UX28gIncucc0fWsN1jEkEXvx5chO+sTft3RXfVehJrpbpg1g8/SV/s0KS9NxY3GR\n+TNV9hAIdzH2xpxdAZA8rSqKcNG8BWa97giCGGom7uEEC7G7iZs06soDK+AxQRAJ+WmZZyXjdefk\nS0xqti/2PLgu3RiskjNwJldrE1I0uHPnCXTr+d7iBEMi6hjRTrVY0V1THygB5Wz3ABeLA5eOOzeQ\n8Vi5uyjlKB93QlFWHH3lYO+j7VPFOcfCLG9spKytNXO+3ZMuZYAEh/nurWu4ElE3s+omZ4Ov2r46\nEPwYJkVSjk2kGvj25OW3am+nVgLQqyod3R4eeO+slIxDIlI+vEyjLr2vXsUl59o/8nNJajFRrNeC\nQBKbaVlwgeYycDwQiAAlX7U0TlyCmV8LvO+qMuJA8nURMapsXSzQ7NOWsqrGyOWi5RpvFeLBpYJp\nlpXLdwJeAfpbP5TsqK/x2BBwqCw5+v8ts6eJrk7ZnXlkdQFfppkElqUPdjJRdrtJljlexJUV7l/S\n9EDrkcun2vl4KeoH970x/9UwnhhlWeos67t+L7KIn/jTSKVLCFzmgUCeWZOXApSSksada+4I4AAt\n7z60FhuEx6Wcbv5oZ1T1KOEQG7No24iw6ZsU+bkit31BeKNlNlf9iykLR1hA+9n4s/SHpuFH5j3O\nZSNjGYijauXyMyTR4ixS+lSVSyrpQkorw8J0EKC6Gj9/QrLDt12EFhqRc/lDsV3fcl6xs9O9V8dY\nA7lvM7Wafixk9rc43bfekx0ML7M7XG4s9WK3csfpY1oiMozMgqXOJxKD0kuzPssANEUXQ/D85/G/\nnAGdrXqPPiwy3wr6+JocvyteJL9WBanC4cihtz5nna5s1tFdbiuqfysaBZfzBV/6YcTDZKwKvTgm\nqZhIglOMJ9yJqyfJq63r14kkxSjwQMWG3RRiWcLLVOKSZtthZfeH77m4D41miS7Tc/HemOyqdMG9\n7Mw6ogHGykZ/Y7w7Q0wt8JRsdQCYRQQ4KdGqy4hgYTg64Y3Mio7eARXUZoVzr/CL0MIkbX3qQrSJ\n848dCKoRD/hC67cnMPZtbz1gXdq2Qe07Uf9HoKEBU6yOw/Gzj4NiAuP0mSKpjqY0J+M1wrQvgEvh\noYxui0aJNJD3C79rW+WPGfmfHlhkbxLLK4xp2Qbd3PTJR7sOAXqMjlWayatca8PLqsvo3/SUsDOd\nact9UheGGJcJzsHrFJGW4uJVKPja248SGfmB1ezEknT0Kn77YINW3YbBKksXNzXs/TRZwXPPmeSM\nillWe9EpxQsik/xmmOYNuaJZqBpJHWsO5zviU5Cqmtej8YXYjsiUzS0X6nwa2joG55fD2ePKRs2c\nD4kZc18LH99zxLxqlAqef7Z7VbPzF7rRytYhJo3++aDb/F1okJvnlhcWdE8oivy4CynFXCq34Dzk\nZddT5JfNqsqbsjI+Dvnk1g460kimaqtZiSlBWjGOWPbO5Q3FefJ2yYguWtBjOhXLkRhmtS3Jqkyq\ngaB6RKaxgzhqO7fR+aeq1r7dlFxYg/rwfgT/ou0hs/cLKDT2RzS9IeUgL82bZiI3uwApqaOWHjLf\nYSHAEZHmujq+y5+hiIUudFbVXYop0+n9iz8D9T08Y5aZ8XX3jSHKIoP+lzADFDe/st5DYrqf2V5W\ncYAuMkNmBP5vJjfK5rv7oKycQAyZpdD3KKir++RKXBz+ytv6KDZ3ruKbihq3P45XWbI9LE8M/NAV\nS64P1J5LKMAjAAkp+vYYdgjlsVqQL/Xbuly/xdraRbc1pRq/1hjWinOYOUkgFMajLAThGgfpYUkE\nJgYiVJsGajIzDh/jbbxj1TYpCLVE6S7b+OmyVEZ0T/xfxVDka94tS8QhS+UCxIXrIBfU5o/3SQ0h\n3vQn2lPeB6NmP8skmoExA7DVm82EtJ+we2cyJ8urhAD9sVqsW78f4S1IwcxShqM8Tuq8g5BgivVO\nX3JMd11qi6nKODzvG//MJffmArwG12IWCeAjpSSYpaf+6M1NIO+tY/2ZRIBgaTyaYDoaiQK5NVY4\nmYcA92h6QkfdvQXPFJAy4ys/CdO1Yrj99gjrzF+9+gtH5kj5guAt5HCh+4eciVqTfzSfmJaPLQlj\nUw+nQLaoq7hw9DWAfCut81PbxqUUcrVoZYdkhuFacEbq1fsKdSPr9w==\n`pragma protect end_protected\n", "num_lines": 1194}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nCgyLps+SA0ui7dPkXtm83wP9WSUpTVOaNUUaEiTx3o8bDibppEo7uXVLsKORYUGbahjOTDE6kwIY\nyzdcsZuJjQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nls1ZVg3oo/4jpb/tGSZ67UhcCiJPRZSibleEkmR8FGMVr6khAWRoF6kYXnp1zsyHU3zpkX5aZudH\nhQIPiuWIX1ItHdefmGknlXR0g8ejEjnCuf7wiNI29U6+5iw2QftYNsn+9bDRp5kdheVUcuxELJlA\nXulkNd/ln7GkFepSqYc=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nB9jNLech/g/tKNMUKP6f+gjxZsMheNAx8UaJ4vLJVXHNXpNxk91NHRM3Xm9hGCv9VXOliR2a8QYA\nPQ1bZLU5blYqH+18qF0ZF9Jo3IiF0g2nN4gOYAI7m5j6VqkzD58XFZMLPANE17Rohp8jENs7nh79\n49oN+0loRI7XCt+F/XHBh8FH2rSJmirxDK2iqylD74LWMeTBokuvbg3zEGTXe5qvYmMaRiXcTPZB\nDS3JpPd04FW7EUk+5RM0Kcu0Ly1TuyTKFn0mEksltOKTCKOerop73A+MOzn1eX1pf23lWhgzfN8Q\n8HjhN+i90Hmn+Ojdq+WsQMHc6+n0Or8KFbFReQ==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nCS3PEjLSMy66Y5kMQ0y4fL/X9nvJthfWlN6tOA1JzOyIwzumGq0fkllz2YtjUH+WZKf3DOAh6h50\nM/7oiAgx47vujLlrhLAvEpjj8WUfQd3LXqVk3NCO1ki3s4QNBrpCKhg86ykdPOiLuEXDkUt3v04y\nuxmO8exLVDFMG+CzMLadbS6QzvWCMXeAb/FFPfVqwPMMw1ByBbbNZPDHX94DLgrF41I4jklsrd2r\nI3FoDtv57i7fvGeyrplt+iDFl8lNUqFZyHP+5+yvGYA60xKn+8Y180eYGnmQ4wGtQ6Kkzn55UAKq\nBjhfYJqchzaFN68doG8FMNl5CP4MfMmIG1TAbA==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nnQe6+EVbiKYI6EF2Gkjs7kvdzSmGHXU4qtFfR2dYFwHCWHPPG8cZ35Gns8SCNITeaBfeRRFcv/q3\nUoOZpWturDci6dtPwvXGTKFk/2M0wDGp1JDGd5iTwJk4WyDb6tdfibGrM334X5OHFRDy3qX1Uovz\nSj9hOU/EFGjRS84ag4TVcz9z1f1Y+CgW8Ym4KNOI8D0oIv5DmjP/nJr5kVGL/WNmhRB0h+vtCoTs\nUcGqCPC2gQnw0GIBNKrE9ivvsGq/ACxJuuSLwAzquqUInK187ExgWQLiPHhTH6pfZDqnyZpMvGrr\n9OumyGggkggl7j/JE2vtz+6aHVWB1956RXcbLA==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nVPB71QTo5TspzkUp7HQwn2zfRQ8tDgsnLTLdZIsMOrJ+Y8fHz9hexHBR3Yhia6VnY8XCYjgPbAId\n7QK0Myn0r32s+olwHQ8M3jsY7WJNK96AiGDDRm0HHR2rAUT0mbjaG5Vdc3kGr5OmZ9abSnBv6qJl\nd6qqhUFQ2fTIk0vkv9s=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nIOa65t4pEqSGhDPlzgVIxaBhM6TFiSGG2C8XLJL6CyEFm0OzjlVbdnJuVLSSsqeN9g9q0ucPVcBs\n0MDNHCUMFAPmUvHCALV35V9sWsxZnNLruGv6jYCoLT4RcYb/Hskha3PIaIz4tnT++Oplm8SDc6KE\nj0p7EoQtGWfdUwtiBHuUQr6oMBdko07oc+MLXZy3P4PwN6CMYbgRTZvUcrJfxR1JLpjpTlr85sRE\nQCUEGnVHiSu2dgyZ1oOqfyUJGaHcNOM13rm1E+h8I++ksRVlalZKIcrckCfC48c5nJdrthR+8rsa\no+k61kcLH2NbhPC9dAejCTOCHyq4j6eKfXBGGw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25328)\n`pragma protect data_block\nkSwfaOQ2lUKsMClQk038C3qrnU/w3gNGhmdlLNfR9sWwqt9+mhQ5FChgk+V041Zn4jr0vEzfPK9c\nu3LNWSj7Kuy7mPDQPF4wc/gQY3v1ZqRVfjn2zXECRESZ7SISVb3/zgxGap9q5OV9OP32RkaV4kdr\nws8IbzNgdjoMmUEPWIST7YMeljelbQVuNUUiauyLev5wd5EZQgjtqiLEePwttFZFz+wDhSrZ+MSh\nmmVhsv4hlANMdsmgswzLepN8QpuS2x+4bV16nI3UsgySXVY0LRP+KYonO3zuI7oGlDGAKq7rVAA3\nosLmIrbqcv9oa8RF7mwv8MG56fHnNtMapNiNUP5a204RBeFO8tYuAT8VwFE66FWyg0x+SFytJzKX\nnDz/x5eXYt6o3ivPJ9zrCY3V2GzhHa8xLWUdmY+f0t06M/pjIKnPlBKPRL27dlEboBL1WLxjolrb\nZFxdGyaOrUIkqkQm8IlHVFmnZtXeSYrONP35eMP2kL4cGqUTusPeoqJ8DoPv/15TbKPwDOmaEXYn\nOEGzSGJPYZPw4+XZbtGAj0kRbQ261OYzNHDs3X7G23Gf83cq2BWgy5D0KMg8x7egPLMpaWTEJFAo\nwHEzBZROkgZBRyzx4uuOLJAzJ1Ww6ceB1GR8wqI1RSlj8gKQ1TwofF5FVToWZLT6C3Qy89q2zVS9\nA0mSl07IkvpxGwr60pFS+XBimis29n5s8FX1+Y2s6ykhocSOf8NQXfkCEGy+ol7sHN6ItVozii4Q\niSDgC+BYBApCgZz8ak4UXWCf4OdR75O09s2dPW1NNUB0LmDZ+JYg2+lHMwwfQbN8T9npoNochopd\nGUxTp/6OzrzXYuXdCTP14tOiLSckvwYVGLQRUNEHZFUjoAyI/K/pit5jx3240OUI/mdlbVjdEtUG\nZyZ6ijoMx/CJC0RWukb6rnM7lnnhpTUapuQNw9WieVmTSHV397OKlU7n+hVDrAOVM0fnBQoXDeAC\nPJlef//l7tgQN1x1eqzQkPGyXOWazM8DwiOoFa0tqkAslzrrb6K+PMxVs85IisOolgJv4q2sSZdV\n8RYCZM7MjfQlQzFbENfRZbZsAYj7zqKAdfnblfnQtX2D7QAAZtAVZbtICaIF1IOSNnsCi9uxK78Y\njHAC2RNWOwn/P7vBzImG9xwfIQ3kJklicNBdaHlR6kV22DiWPytbzi7H5Yh+1OnunmSMF5aO/a1P\nglEwFosYm2rOGqobOtvZdtOvQZbF2TLhNoCULxpUVohVdo53ERTsmRP3+szwtxMpYpRMOSIt1tO/\nmsxP5ho7MgE/Cc90lcabOMXU6TwV9GMz2Ec8YIMp8yPLEuaGXNyAKwcENA7mOQabA8/QNE8TzFxr\nzDj4HnLuxNA7bZFjKzEa951JtnbjQteNvnEOqy3O3vneTPebf0DNwD/PH2HzUyztYeqCd+4Ke4dl\n2XYcyyJlr51kmlzHyIsGKooMqHJz+hNY04caoQWD+Ev5YGjEMqMIxwhmZIm5te4ZzfunIO6qNTcU\n43BM4NF6J3RO7yg4ITHq50A/iI5hpAQKix4j86HXuGTgrvH7bsVcD2RZlv4gBrOkQU3BGQPAJeZl\nd25lZzULXvWYJCgbaXnlh+1h/NCjB/xX8TnucsxmmHdRBOGDImMff3FDsIEnGC0nEiFLP/fR0vhE\nog92bMwB4+f6Ja/JwPj/hHsU/Y7/vhRpgrJZFtljDVR5p6SPzfqZ+d6oqCyffmOU1mzMzEWLf/T+\nlKoSQNrcH05a6ts9/xvttvEnJoUmUf/H/09aoExwqbqLqI4rb+nzL1Mij1Mj5wjZqg+RzpWMw8fH\niJRUlCev79gLIKjs14oiBS/tPttcY/zs2qHsglefkqtfKIEk9s1OKKBE0NXUYo2xaULzpfqKFTo5\nEFsbG/eTmyP2NlgcNGiGzT4KFsKcX7sZCgsrutPwhhdzOBA/8N+CfVeVEsdrP9sS6ZIQs7McQ/7D\neNshaOGNMbXYLbebelDWqbszWYtgfVphDQs3tNtemJrIcmtApxUA/7VfLQRaw7D19ar4E8ozZz5P\n52VP5E6TvxR0qnt4C02mR733IZNNNYzEN62jdN7lHbe38BYdDWlVSjQ+j/iu8H9Uw1c9sRKzhMvt\nYSbje5593WOrVBZd8GSLK+W2/0BXU1rU8o321xmPD4KzgPFpNqOVlFZBVpuhz+66JTzg0dN+hk/t\nFZhN7JfVIRWniAPyHn2JDFXcGwD706qDbKu+155s7n+ZohU1JSwKxTvrORfYyvnLkkGm7fJQ7YRL\nt7BfgeyatEZYG14LIXAYjvgfjq2wtToa/TvQDGhvQ4Vm8nZzgWZcwGS7TJsxAg9p8hrMrp6rWD7q\nT9p4sQFyZjXkeGQMbXKNj+j76S+MV1+ZlwlpMQmax83Q8n0eG6krBX8W07reDMXwDi/pfHZnR9be\nwf1owb0a9mwrd2uTVsyua6HoiqBX3Pal1FZOUICvgzVeRPQjtX+5z2m2bTFa9Husd5qgJtC018Kw\nio6hzaTDp6k0pEhuNWKxCu5MYR5qZsH1QhQI1Tvc624IFJ/K3Ay7xDjun3verJ4OUefTvdYz0TxI\n3K/tmfQB5VfrezfWLkF0jHF8SXCf/aAil2oXjvKKfzIV+wTzXtKohwD8MEfjITbrP8BbeHj4Qjjg\nGdLwOy1xTGJgUSS9oGRx2/393scsFP4J00gbt2yy4ZaVBbdIV4oPk9/9nJniWlCNrHYcY0VkRd3s\n2h1bfTegZQUVLvAzHmVWExqww+QVrN72GuinDns3uQJzkjW2oXpXU1+I8K/xOe0aOZgVL57N1lkR\nL1i82WWSl7WHMwreThqjifFVASVCTX6sg/1eVK52Ab/QWUmFtTRLUWIOVBozlcWjVZGi0/sDgJfM\nXBSZLF6a9wWTbhObbri+/RP2EJDzxBS7ImjPO7YXCEuHFqwdPBxr5pz9gOmjeSWjbTU3TD498X/8\n7PjURq5/I+TJmVdTEm8qoPvBEILhT17sOnZOCqN1sxzYTUTwOP/fh+5SFWILs8IjXlmtv+wC5IiW\nzInQYX1V02BveC/m0fmFsn8knWeUXWW75GIw8voicnX5MIB28JxYzTqzCcaiKqRigyYOs4Osdese\n1rIQSr15MSZogNQA4Q9uqpVZIJiqX0tGTYJRAdmcBKUUxy5OaslK5g4juCb+CqT435m4GHC5QyDz\nxUGN/7A4jI4VXcnL0KDU0uPNygMNYGjlBIIeSVJzFfLW0SZVCpssVP7xEDYv9oPoBQRrOeKRQ5qP\nGKUUx62dOlmuZ06pL1CFyRCnptFpfjZpiy/u0X9DAKJVLS28kyK4E4aPAlySXPnAgykaXMpq6+L4\ngwQTlJj/RWrDVVZDLpgDv/dSjiDLi1gzYGXu6QoY6yv9kehm9i/zGfAH4Nm4iDp3ttttUcdsGJUY\nOX5pBJJFOq7Xm2WbEGNOUKF4n31GtBjRcid3c6qrQAnTffL/kjQYzMWjjxtyQ4Gq1S8SG8wnZxh0\nLa2V4nn9sNN22rx8nyxr0WZxxCT7FRXBfRsyViBXA/HhwUGT8UtOaucltcNOBKQ9aGEPrXr+bnhq\nCEhMfhyJPjgUKZpaam2DDDqz+BNXGTJ1q3nD4XKRahlStabRjg2WslgaR0sUa4f1P8T98v4+AyKA\nbzxBCXiDIjjI5UCH9o6n0WB3psXj43WGP7Bm9PfB/emi58Acg56+fqEW5+VjMvHJo29TmFL8byAB\novlmPIyfC/Fii0v3LlYWAxWVA4VBG/LpFcgo9qPW+Yhz7sSZNlYWYRx8BSBtFHPZ0UDQKoIXQ/Ne\nRDObMN/WxcEJcEwTRilhQhKx6hlQ7hinqOaDY5B1GFPMN3gTpB1dC5lfOwDwQ6XQbTif0MUVz+e8\nRa51wUr1nWRmVvnL+wl6eX+bie4IcMHbk1IifHUDQJLPPCwJqQ0W/PTILBcdBSnfkn8nQdImfOp7\n+/WRn+WQl5S/4KjVdl0zWtYEetGtJxHGs8S/wOZJ2nxSnzGuFeaomei8jl2gP4EFf/WIa4OzwqKj\nz+2uN4cJx2vlfkt2FtUjeUovD56+jlPthlDUP86m828E6z+HVX7ZoDEV33LWhlQsHyKkmoiMWzYy\nHdVJabgGfyUmXygSYdEqr4ED3FjHYpkAtC/7g4WhqFvZ0TALvPcdB40O9TF3LtysXZQrhEeY14J7\nKdzxRRPsCltAu07xoEYgxU18+1twpdaZZD+XfOXHND3Y6kE3bjIxMBv4dV3AHbmPRivs4kW6H4gT\nFVcUWuPssTRNyv66CLVgv3pLFaGbN1fN1GBG2XQeBv+9kUDCq+rBrqgBwhSj0fncbah7q13tfYsi\nqMGF8LzDq5M97C3HMEMuM4FfQBc0zP81oqicqoWuBh1mhWihKI4/ZlaRO33f3t8wPtZ5Nqn0G8GE\nUNlv8CLzYvaC7tSaKV9gJySIfJKQt6yEnk4CGj+RVRu1UA1/0Er+TlbXajVybaQRgpbkQWq58eU3\nyOaqQ1Nc6JIJRNFNfKNfxWmJlQJCMbbGoPS163X0V0rQ8l5UNfYvEM1AJnntSTTZpcfamyGcrk1F\nydtxqkwn/hjqbFePqd7AqmcKjnKUO8ZLM+mkQD9gvnYXy8VMY4JM3F7mjELqgskwNrDfqk7KYp84\n8H92vTOvdcxMbuELQOGt+G0tx01omR3v2+zCUYlWznKkQJTzg7hSduynfrqjRa4s+ukUMKw9nW6s\nMH5T9pqhfXqizyUg1dFErIGw+8Nn+ezQ2lycDwRRDq5Q7kyS6RHPjMeqERFvlIbn8kimWfeQB+gd\nDYrZ4Sea0vnHhZ8T7nYIWltwn6NkOjxMONqbv5nBAXBhf6rU8M8Upjt6ub1Pp7fpd5Z4O9XOIn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XEmW6zwtcpFPQIxv6hxYxwC/spdTrLGoB4ILEP+NODQpYsELTZi9WLQc6L/iOQgxB2qkazE7\nznpYIqd971MHDyIBimsMsV2MIlfJx+fbxPxgOLnlldWhu0vSMbvH0tKsCaqq51bg80SjHoTbLdRI\n0RXKBNHiY/hwNrAd/uDNI1VArQPSevUJihWecel8HQA/qErqDeuyR3fvz+etmwA+wEarTYrJTqBx\n+0gxN2lWRXXSb1WzVOI/HRxWhUkbQg5KGLcd6MW/+7yH/J74DfKqSSUFnkbQtw4D3iiyobxCMVEz\n//3tVZ94deYB0NSkbNhQwYVGtoYwo8MnoIs31fabSPiDq38l7xlx9fp75ALhijgOEf37nXuBTGRE\nroDKkPV2KRClavVRGPGPcF4rrGho2vJSIvjU67WpSxyZ/hef2sjInD5/VTfOHdjuUA39/udvN5md\n5PU8SA5cevPi3hZnv9LPMedfbs8OfRpINO1/cETQpi3uun7In3BwZIys6d9lrhe0okK1aRQK8Cnh\nqnMJ5Yk/vCW1DzxsS0YjsZ5++CKwZzuxv+pfhRoA360JbNFJ2+BnWfrTDAYfBh3X7DTAN41eWGJT\ndNIaOmQe9nucKLsM+5bqmytNG1XR3x8eQfnSG7y9u95+a0KSMLLs8vDW4TMjY7wKGfjMrcLBXALX\n5RdBS8d7iquImUPCqSe5fyfq8aViMuTA8JyRpN7reZ7hr04/nzBj5v/GYAf/fcwf9/zsj7pkvu7Q\ngA3tRRZn7bfQXUAh4a8r1qtWmNvSRZjlNWf/0mlhv3MlEmSS3VN0lREGa6jOvJOOx7rhOXLSBPTP\nrhkBwriy03trzUP0PVLbhK+GHV8SATZ0qhsPJPvKJ1ArUmrcalWO7R95YB7EZ30RaQUr8LDu8H0H\nxSfvBDwdMyeOuWz28PLk4bAYYi1GFnYL3c+9aBO2/cQRrQOIR7B6zDTzfn8ZAlxv+JYcFcA7cDdS\nneY1+v1AEHA410TBSGLSJ7W603q44z94d7QgfZKpq9JGZ8Ss+XuzuocrjtI/CwzxAYaXJAfyCkLM\nvSecX9VlMHY48b4tYVPrX1WJPcL5vc4bTwpv5yDhIsqRRo4lpshMtpmjP/LBQkThJMDwD4Evjxd+\n0Z5fgZIhj9Cesf9L2z7FA58DJ/shqe5H6BxQXh5EHfWSUwr7+FGISDY+aOXzkINZDYyhT4Qc3M1d\nOp5u/YuAiJwVw0oS31g6x+nPXEvDwGDKIO0jR6+C30Wqzb2uD73ACi3CpG0Pju7LE3x7sgwWFaqP\nR1UHgtF0dYf7H2mg2E3Jvz0vEn7MLjcTcCLLvU551616Q1+rUxIxuCVVppmXP/ktQRbLUsMyXdfy\nEN7oeJSTC5WEEe+ruuQFCDTKWJdT2y0pdFnqTf2ppYzWv/n3pGBJxEdDfXYHh9u/s0uBYf4UjqdW\nkys6LWD2yMmnuC7j3ENi77hkb9Qjl2aJb4q/BM+soWZt+ENkM8mFnzNODGlHgiLZlOivoIO4IjDT\nBguf2s76miE8Y5v7LW+4nz7zaAzAZZrtrzoR8mPrEoLsw426l0yobffsmLCoxB0Myjxs0J/P8V4/\nWHvRj8uQlYUXrrS2N5l1TWLrnIRYqvGam//oUfGoVR04Bsr5BsiUo90ulRGVW0U8zFC43lotvhXY\nI9uIv5zMi4kvR+nv0IiHkozj516FuEBJae321TuWKRqcMNkLJjM0K4k6x2V7fexudWDHVhskWRpt\n2uQAgpcdhkCDKRctrzCKI3GumkTB6yHazXLoWdpVJ4nlq3TwjQiQ+FOK8VG7Juv9qDoWxTEwXLLT\njtJla8yzDow8WL7U+/9B877wQveVsQ2a9OJ0avMJCtrCgZt4IXYX/lmVkkIYi35HVACSra0Yc1TE\nIpiIqWFNdQuwsaJe71w/LZ7wTfkjeVGaxK0A7sSf2+WmYCASD1CkPFFrFdSXvJvK8IUNvAZt+gk9\nPgN0ff1oOOnee5eda9NIQGfaH7++ZnwFYNZ3JUzh7aP8PLUTmDuIUcEhtjMXZC7eyLGN1xrxC6Xm\nxxqU4iBoCLOpL/h28ZMnNPN3/L62xF/eXFI1K2c1NiFp1NcI/Uv0MP+uhyQsTsx2KA8WjYRHyqe9\n46ma8xWeqTc8FpQH+/SNsISHnF73a0dCecKtu6hKNrOLslP96Tl+o63d3HvD2JUGHkG4rEB8PzKN\nIG/N9pDhl2GaeIZVHaWgMC9dzD8ms0fWghnIhCfvYHErSkD8icLH7Q8OyhqS8ZUrhB+Ye6hnH20d\nGhvF09nRJI7YR/b2nPE25M33KKEY5ejkELQZCtvUhn1WEFtH5alKE7dXQG/jjYYTVK0+CbxVbBeZ\n7Ew0/6sJYi7p7QlWt/RihMVY46UHvglpKJfzlAmyPi3vdxpoEQypPvXCL7gOkR1cJKu5xhIzJ5t7\n0hT4uN7EMvLo6IfiRaKGNeCjrHmQ6nRlL76bp3vJs3/szupk1BRBTId+pKkQOlPZjq0CiyEfkOR6\n7xAEu8rgPdRSiY142Yr03ZfgL1tjSTWPwbqe6yXZJHECCaKhS8dOwv0iG1HG1xqfCpDb8bGNG5SD\ncJtGHW1H/y5DkRSh1qCMPyfyH4/v1T/E4/sXAUigrTVxwaz4x5qzq8sdSeVPJ6zEkLLm95p+QG/Z\nujUA1GC4Kp+JWSbCmGIGmH5hywCzcC5aZ7AmfTYTacxrOMh7eHq39R+INTMuzAjRsR7wgxvCfi9j\nVCrjcKH2e9tWJqYS06w9fHygPwsQBnxDua6ufBzh1vXJw9p+1YSqcdHr2J1GbaCDH9g/QIvGU/6O\ndbzF9qmG7acOplOV+UUN7bPImCfV4amD9Atdpn/yCqr17sbq/XnL8PbEfLFWwGtxeTDJNewdRG7I\nPuwOhE7/lAPAbTUjhdmGRU5jtZxwizcz0L2uya35thXsjXDoa6rM6KEoM8AGcBK1tb+yd7PGqnVV\ntl1tPRqgqsMj/Xfk6jwPKq3lc+rwQykIHRcKtuqFITMDLadL5ep6HMsOO/2PjRxrIT10V+AWqKcB\nWLdowlVBAqHvybs7xj18q7zmKGvn1/Z7s9JF9HeX+DM1keWzTV9lyDS8cfCEWKfxCCEMi8KH54Qj\nEzrbqFKm7Fwlg8Oz26tPJ6cJolCH45fSrmQ5PmfPIbAWYgadv4hxIy+8YqesRGAJS+JIa5SOSXAb\nATecjyYRjiHOI3AS8/HJUC3fqZ8N9qAX11K9lBiIjeAbccZK8eaJvQpoXGMA5/BH0vPycGo6k8hl\nTza8n1FJfrMyIORyUNwP5Peq3yZFkXNUcnMjt7tXqHfSWCwg3IFwfmOAgLs5w+K8IQjqtJZqxtv8\ndakxmjezVpTcmWXGsnw99P9JqDGt+BqYzoTXmJxw2iUPHthmNl6jiRoh49BtCqHRnQgIj5pNFX5r\n8t2qFy3ToUPQLoIhrYuIfhzw0AQLDFDScB/23Sk/8pxu19MVCgBmkfh/2xMMKtRbDkLQwTjdwpxQ\nrqEJ8nqvLO+tBbczQsREhamGHxOUpgAZam0D/KuSIlERbp1BpeZziflu3F3wDf2icJEXWOzomO0S\nnodxZZmHYclWxNI/ZytanByEfYfTNEbOvhpHGASwciuVfAXSoXNV7cVmuRG7sBuTSczVQJP0cjeD\nbfzIkwIhsW2Njg80CgQT6mdi4zfsAb0fr80e1VwVbWwtlX4ofhP1JmDrCrDU+AxxV1iJsCSzS7AN\n5aOdu3W16RzErzEE/1um+Ev7z174+8ddYoUfOtuFxVvAElaTxFOt9vUDJ3a5Z4WNvJgPe8cNt8R9\nYfuVdgr0BeqEC38Mm2VemwCGWJiilw8ZNufPdaDuT5CKev6WQzm2VpdCUPYYY3j7gTd23FeyHfZ+\nzX0yCzO3DJT4trtRE6sOb133kXpQkQyw6c32bsOGEHQ2MwtPveJMyiLcdphCUSbZygAY0Wm4OjtT\npq6LXISTFqDQGMYxqDI215O6O1e2d3yv6JmcN6E1AfLIkJScfFfda+qd4yuqjCTuj/65YSaMNf+z\n+SnvOvjH45e7Ad5YSVZ7pLWHQBLz+jaDxlZDwwhfnUCKmKLsz8mKHMw6AveW9NnUvh/sOtiLOd02\nWQJaSR/GcX6plGQLt87uWd/Se+wkzsTJ8uapmtIznpPZ0fg5NY7OuiIjmj3X/cxbsUcJsP4QK8Yo\nXMYEoSVaU6M7gc3m4CsLJESDVWv9usg/ACikf54onEvQw9jGFnP8AV7yhFIZLvfTg4xiFbNjRrcQ\n16mwcW0Fe6L1BAPAPhrb6wDKTI1hd39jJ52C1XA2BpBmZ5yGkT92S8cH0LOJf/v8yb7ymcF1OPYw\n5jYG7X5OUOCrQmmOlINIVsu8XHMlnRa9IDv4H+0ylUJnE2So7kW3rjDFNDyJpJ2yJi6NlHcxpHCW\nm65qtutuY+kbFMpIWHpxjs1cQfiQPCBISnJFVxNGTwgCqr6sHj/5ICiIsCkCO0QIy1jEVJDN2qVk\nl/ZVfIdNHng6I7vy5BzCCb63/mIDlBbCjFiafEPKSnzQwP/0N56D2ImUBCbYSdsjfLV9hiVIBYpj\nYQnNFNDu81Y6Ty/Od2AKyy6UjTdmLb1rdqkGnZ5qqAfhwM2AKZ/XoXwiurBa7+Xgwy+R2jBggubw\nbeRjsDJa7gU4M0gGheeRgNDnoizYw02Vzlg4k1VnPjAsxNr5XcW1BJ4Jm8vjEEXBBGGvVP0psXB+\nL4iy7FHUCgYPy8hYFqN5g7hLvb/wT6pkyNoUMoj6h+9GrrTy+rnjI6kGmNlIsSYu15F7oQbA+V9k\nkLTaiiD0deoYHRklY7pt3lUK7rZHQKf/n6Vx10/80i9aBofpZOIi3uyImyCN7hHcCCpYnvew8SZT\ncfFxgKGYa7V8OeAxk7jpLBvMxfr2ARp+Ep4D1sSRH2oSzKbtM/f9ncdKLxEMHr9wxupSW+XoOraE\n1yy49P59KV53Y3YnD4miFcBODs7CRM+6bqoK9hO1K2W5kvfodbOzIB1IARSmOhRwYdljB19jurPE\nYU3GUTC+u9Te1SflGvr4XsqCbbGMLETHb1HZmXendPnGcnneY+LtnYkbqK7SkCN7x9OkYrdD4Vsq\ntbk3FZFRMB6EZ5WZ214LiLTHzEmLckyG670YR7BNLjK1rQInQAgxS7Ri/B0TGCrTYRAynDMCPXB+\nEBZOhtu0kTKOAVnDj1uOhBFDA7cmnm7e9k9QBKhHkPOHHz6q/8B+iEM+hX+B4q9fpPM6oKw+Y+1s\n8b1LtwySajwDTHtloQWcxc1uR/UsnkCWBPuL9DMNYGr3ZmKTEnGhp70LePkIcfJYuwsfo/E7aCW1\naxn2sWtKwZrw0+CDk0QTotfQ6nG6Wr7hhUAnSqfG2O6kYjQyPSn4k6m+aEiUWQ48MMUvY9ABq87V\nofVf0Efv1OdyGUNFigWmZe8JDvXnZiWw1K9gwZqBldibpaASp9bfFJgdiPr2CAGTDl+r8eoMd1jn\nBbQ2igsBTuhTaV10ZWJFSAIdZ4+V3HYLkLU8oSRXqIzqcI/IiAg5SWLWSaeHmkCkSbn70TQGXGOF\npfjhv2J5yzmkmWDiwFq2qT5eWOMB38FWcEeOtiJ9xvBgjz0qOyAP17fXFxTm23JpVYazHXlTlnnH\nxJSftOg+EKpf3k7fWj4DxyytvhYqXy/Cw2R1dyUtnLFEbMzZd3Kd3ejeXjJdr8nuiqNi+s7uqd6f\nln+VwVZ9a3biIRoGDPRIqfXo5untTcj3xHOwq02XjoFfYNwh12xIfB5ZpUmpKZj34IsNZiFggBr6\n6jqqGibpp2bK8BYBtgi5WPUHkZJIuu/COkKemycnSDpeAv9Dc3KRz3nwhCU41HMq1xWMVrrY5W/B\n6Q1U+SBjTYpQ04mjzFOvYTtEim9f+nV2S1wghga3XTYpWdtpng6n/69RizgI6R1dyj9sZOcdhPFC\nLSFGTswmGoFRGvNeDd01cU3XMMT4u2Z5ZOJ0f9yEb2V0quk1hIqMxHLPaG78pHgJeAtI4ztI+h8x\nW6bMzRi+2SADpd92+2fWMSzXApfsMfb/CJmztrl81bZ/RiWoHQO7FahUXnuklE54bClGGhaEsp/H\nJDvuGKJi/CWrkZltXV3V+Y9rHOa2gxVtp1SNceOD7LJQtxy0tEh8+Mc9z+X68qvpUrp/u4tsNXDV\nXsi751iqAXXO0dnHOJ6OM0o4xjFty4aOINWoxA+xCmcx4EJTLLggpKAdzIwtad13EDly/znQSFLF\nbnp6kOJKqe0W85XvkYnXQff6cnhRSWsY8q2CG0w18siVnfa3E4xAO6o6vcJsbyH18/PAKl3e7Bh6\nNTN5XB88JkKGd58BVcAOZpxLiupbboAJCvsueNHTlyWyvvwbLqsDVuAJBSHpPs1cFjLtkeiTGT+a\nSrqsgMO+UHPBsrwvBGWtDxj3TIKE2Bnvjmq3fKgev8QgzmUU6ZF4/FNAnmzGpTTvADIiUY9lHdUv\nE12u4qX+I69/sHvIACAnIwYXNbd7R33aQ91VJeAcxifdcZA5v9C3ahUaFH3A1RK+enmmfq3TzpVu\noJN+l23KiY1hkUYhiR2aCWIXRySCyiY55+b1G2/fRN6+GV6tJ2/hDe+vqM3JlVPptTG3ZIX5Xn6w\nXYIcd4doI14tVLSyAXT+x6QXdffSrHe/NgPJaYs5pg3BnLI3GSDNxlUE/pU+OvTXDTutF6naLbGk\n3H2+OtT92hDETD3Fix908xWiPIyeY70Cbx6Buqa8znPrRqc4DyitrDyvoQlrTxSwsLstbSVHw7mV\nHsYKgDvPmw1+ZSb9KyxoMxkr19CiTRb3JOrETdiA/VQqnMkjJGK0IEojw02kx+ft8nWEvJkEjXTT\nvyjahSTIEhA1jVfUxN86LHEucrkqhb13um/j1XrS3GRfic1TgpHHW1S+0OcCHpiKzX11xznmgBbt\npi/8dC8uMXKveFYefwObSfPZ+WEbNUFC1u1Mtd1FGzNLljP9SEYPCSYTWYIzMmwRwWT6betJJ+MV\nq/08MKx6b4l9hUTYOylZcrfrrBLhb+qmqYl3C4dEybhehzgcKYDwq4KVDUSo7uPJKSObyezVPZGp\nYxK9gGsaTY2Y1vrww2p4LBm31MsezorYaIvvDZrRulc378EkVjjMFY74VdMTXqb+rpjLfZYvEheR\nltiLMDnzHFMTLx7MnxbGVbuTWXJtisMsbH5vXoXWGEWinvXUjir4yICOZiMgUdQNG9dJKF61yV5d\nD8vuzUbVZWMNKO50MKFFeQDEIi/QK3y9S7CoVspKGFiX9huOjtKEFypMTRvN25ZU6IsPSKFyBU3G\nsf2LC3U6O3+Aia+yJnOJ9j68fJ4j/y4h4EZddq3di2jiahqK6+92jBeqa2iljZiYWvUWjn1GLa6B\nmAddWZnuVAaG7sBULE1a2OvCuqt0/rpv4E2T0oCtg83dwV2wF1xwvR4TTP0k3VJkMDa+bRc6F1If\ng2DHdDMHOJ+zr50PcE8q3ATEQ3aRsHk3kiBDSNjCLxAu8Aloh4dvJok4QPOA82ahFUluEQOphCXJ\nnoGJVkBSWcXhXojWVO2iZmFMpOVj7j7CK7BqYLDRlfM7pQg0hLVUf+8hH8DhQSjK0e4V7/wJZLTP\npmLh/NhqxxhNtRDUhEa3xSQBmYRvWk0RbL7Z4jTo5yamAInndOM6Pz15AIijBTmggr42FdGAT7j3\nT+Hsa3nAUQEAshewF6KGwmCpKUL6hJwVxwujj3qdOYfcfVJVXWy+j2BjVZF3yRPrb6ZcsBK79nqA\n6znStSrjcPRpIMR0WyiPVw7kxu8u41VKTh7+x9iKHXw+V3xz8LDyVhCea+Lu421k0ftGM39elZzw\niICuqn848ke6Z7HBYQQcmBZLAnCjpKlEfKXiBiXC9/jrnytaxYWEwM1XfMDvfrkot4s/9EvpHeoK\nheSD1gXbrFhPXM2+kcS29UIcUeqaXVoFbCth3Q4gQ62DHteN0gw3hY0UNsY9Q05PN9qWfQoEZuBr\na2Bzj2u0Gt9YJuiH9AjxbWdYdJCoTVqSHPFsfTG+SS+TX8PcfGlHY1VZSdrScBIh1mWOl+bRxvvw\nt1Tr6dyDMLPJXu/CwyCj7teA4QrSMaPNh85K9Dylja1im0yXfAR+C7wRmRZ7Dd7QeOV5hvEC0YGR\n8TZxe1HAae7Zs+dfgdvBmR0esfWzNoda1mq2QiWH6R05QM/1sLqzdodSeB28NPx9WP2IqimxNBQh\niv35VU4A3epX/FjfVmMt40C8+kH2eC+fry5mYwvLXIAXZisbdynQAnoM+GQPONBsjaTyOZptbijq\nx6/Z8Ujz3G9XSvdiA2SVWuD410cnGgQrcWQ3tDBKfsz469bMz7VlELQn6SUzoUmTVeXqlunLMgAT\nZjAFpyhxsekFxEesgRUprfqnBWj8WZiwYk+++EaFrrl2LOVoKTGlASaf7i7PCgiMuDiow55MtAdH\nUQ2BBuXL5Hb7cpA7Qv5m/wgDTkM/0KJe9wVdZ1x+8bqBXTFyDz51576DrvtZtAD/XbJnA1kE5pDO\nTIqF52tj1j095Awo65eN1D9llYHxAe5KqySoIQ/mUCts9O55Ttef/xCU3rgLPln/8KfKrqhanX9f\nQytLhGJplYSQ+JeTpwLQ4AMsrKC5htbluB5tV8y6yp0i2ERPTDEqqtq/V7XMiqYbdH+04sQBR2nE\n4k8UUrISsEJt1r/1p4kKu08UaqcNRB+543qvLgCj6oYuFvcyZ26VMqgmFqYnLBBt6rxv0NbItcuv\njnXcTIV4DNLBpHsCGtPT6iKVmV+AarzOVNre2mZDZSjxENol85XuFWZKPGwuQHGf/13N0FwUZj33\nbcAaynRH5O1xKzw6B7o/6QOLte8t808bN8lTg4RtVzap6jb2nZQ79xfViEMvZj4TZ7mREpQb+UH5\n5w0c1wRH6IQcWeMYS4tEKNOFbj1fgfFa5WqDh5RkiRSuT07K4kqQ0IDvbuKVkJLaGtrQikvV568j\nJtt1GYLsDnJvj414UYYVlISVETETB+9wP5/n9mMPoKD1REvPhzX0F436v7GKY4JczyQWlQtdlIMy\nHSjPO318tn07kwO3cAJ5fsIffJCCNagrTfspZf9bzICnrQL6maPSuNgYQgqFwfDF2RM7YKFE+zpQ\n1JcpFaojBF1JuaWNYohO3O3iXCJB/AErTdLoDmZkRGr7+6yhSCU/MqKmeu1eMpbHzscQ1l6VgAoj\nh+JdxnWiH1hTvWfwHuxNuwiNd6hyvHjUyakzZlmJsCLhEWk28R7wCG+6TQMA1Qsc63dQtHvPUxkC\nn2VqxSKjMhSxtS2iXEtF2i4gqnU7RrlZPaNwq7N8FfBAIovNAkquXXYkv5QqOch1Inbmi4qUAA1k\nQPEde2r+zd3qjLYuEGGSjcTd4RTxuMzh80+//d8arJdfJKpgc51kD89xm2S2hti42Db5ewQ/NgEx\nD5Oc6V+9Fp6zaOdR68MZ1vqFLmPmxrnOc77er0e4ciLRpueVvrks4AXCvLpDexU+qwqJpHcO4Nsq\nePNG3yBCFBf+OkklK9K2i96oQfq61gTjMYDrqdASmgo46lvYVsliKZxiATnOtrw40xLe/I4HyUek\nUzpOa7lwnkXdKgZe+gx5Q0jxiJiTE/F3r+2UpJTaO7MRcwplFvXFPSSbDHfKwF/BQjoMq8/pnM5R\nqZYfGin5xwtXkin877nraCfD6s189FrFvYKq96F5I+uEq7n74mQyY274WQJw9Pq12zUEbQsDg0DR\ndgsWPYQEt21HWe5pj1YjzKc3k9dC903kOq1+KD26+8pdMcpvICRq+WJddxHfZxl6ec1XAt2QKB/w\npyPg4yDmh/5/aEOuP45dLO4gUbGL3EinXZWQ+E1jIJoSnHh6vilbDhtX4e7DJ46+QIqny0h7R5eW\nsfDz0mHmHpRxuhReQWkB2yJeHEe5qYDVKFzzV+a/yM9kAxoFkRxFTn9o6n0mtJORZm4wxoGeQlwA\nIXr9swVxSPgM0S8/RwgkdEGMDAz+BfFrjvRRbbXsrQK3aPWDSTFswnscfXV7EW6+nDVhMJMbes+D\nf4yXRYnRL45CqKVRwr8am3VA8FgN+DQrwIvAbrZaiZMzBU3TBLFQnt3zNny734g6Ufl5gloVBA0q\nt29E/m/RIobK12HWVG/5m/8MNwNY070i2VYegXW8o9i74wAONxZgngxdmnerN+0Bmu5ugMhe0V92\nT/X9Yt9A99AjMEGdljk06tBlYIWLBBv7JdeUmUItCy/FWuPaUZzUGLKbzoBfwXuQG458SVeCmYqq\nKCBgyFSQONeMJe7dhcaNg88JTodC+KDndvWzuL/Gu3YGc0LuoOFqIE6SumcamDQzxQSTHzxsJW5D\n9+WgLz7d9U1V9dZkBWq8WC7scYXmYEJY2TVNJjHVgu/DaW5+XOEKNkvtj6pDnGIwi1nRHt/ywZEv\nMkcqF+WVwZAEUXVXzMuF3xvk/ytRRhgorncR5sS3ArptApRy/neZT/RDVsyV4JDMGSdzgvweGLjn\nD2KQlEpHOu1r0lCWsdTnBML5Ya5tXGQcD0s0DXsJWiJqHyeWFXE8YmOpRBKrnBiGLJaz3D7xF+dm\nYF950bejYl9BrCezc8s2dFTTXOiPC2aLtsqtvhGaPGRNomr9s6FF5YDKECFX9Gtzy65jD2Uxi/tQ\n528R4MC/Kh3P/bo6d+mGGThuyYu/w08SZJKPSMmO2HDiE+mtRVzR9pP+WZ/MpeKRWYf8JZZ1cvz+\nQ9r0fJKYmsiQgj9LJWZYCdjz3tupcrvAXARjilyqBOxVIq2OQzjnIINDF7IvpWnGaenn/Ml+wiLF\nuK+niFvzqRl0ZzeOc9MHYQii1+56TeTxWGY+DM1kHBxBOGVqJVkIwtxkFtjDVk+Zk6HyIPDCN2AR\nms7Ojlj8L9WJyotBzxLNdmBQ0dGc1tpCwdthepMi86OcbLBDaImZ6elWWAFQx/1seibqgSYGXwAM\nllhCxzv1smGoW5ScDPlgpzxfrIsVNvlBXRBMTkmJ+qOQ1/ZonCBNBvc6wysO2/bRH2q22N1pvx8Y\nMeL3M30cfu2qmswOY8Q7zJl7tBMfeaj22LgZsejWPOlhwAzfQWVy5IwBujhIplfaAel33LBOiS/p\nAkS5XH8sMf7x24AVDupRC/hXOAy/awmE5KNbsFq/OL14Ptlmnjpyf9NEh5ea/cw7fNWpTaK1Ozo7\nBa1/0RAk203DiiRfXWBNTVH2047nL0PGx5U0jzNtxRJtrx7qOVd0bnP8bRRX0fgGJvrI+whKaSa2\ndI9EJ2rAnBxkJrexb7OzccL5GW9f8fOd6HUYa0KUq7s9PTeV/hqqXND6gZlfbVp+6LRn9XX232ig\n3TigRnOeqs5gBWxf+yNhnbttVTrVkhyHkg/4XF/hGzljDgM3xhGsLlAQYBlu1IFgDQKB0QCcqLB8\nuT+ItAHiLDsKp22zq7XP3hZuPvXsiMVXhk3gzW80XBjO9YdryFgZKvJOslBV9LRpqDLqwVjbwVvJ\nFJvKaKH95Kobys5cQLXhCVkROVJNghm2IzD+gAvjjNNN4v1g7o0HPABDSfWhWSxdr3Q+M7NvmgKg\nmX4lG5pYL9gwmWn43rwtbxilOwvejyvzUpDsfT7sN6rywK4FiicOwdZu1znqp9rTkkleBJU8oWzw\npMUGzh3EvA3wmUx+yi2nJAivFxWtCIBBLF093Qk5TZ9JF5SsZMriphe019NHeJPN7VM0igq8m1nB\nMNsGXrJNqPg3d5+VMFqxPsN1xlVssCxiDRU7hLUnSCPJwOsPbrJ4jJ+iI5Eu3MZqffJdPCUKVxX+\ne8VIBYaCIU1n88ZRBy0/fvnfyBlP3rJegasVh+Gw19ccUnEcs9NjM/kJdHh6qCi41KIxuTjFD9IL\nuJakkfHei206Hx86Hfs68M1idoaz1YXPzE6MLxYEHPJL/jC8wgpUZbfDQMUY2fq151hTgA5UrVXn\nzNvQRvIwp+ejQ2rq7HsJh4xpyAWWp+UNkpIIGfCUtHjAZl5HT30QkWkdsNytGN0EparGxYu8oIDB\ng5rze1cL7TqjaaZth3GqMe8oc6Ee0mdxzqr6WT0jcmT9C0+Id2YSDXTVsKA4MPNekS8nIvoD+FzK\n3wunleyNqhPmHrATn4TtGMsq7mlqvPpyOvoW5T95hr0vyPIYpnDBvJ2EE3A+GoWaeAMfVInayQk6\nXNjWGST0FMagFBvciuZTo/A2VTJLDygqcDZPqqZ+0NfBGuJwo+CRzq5ICxtDwv0oLe5kj3d5G1qy\n2vqHd5m0/71p3ZseGeQM8DgW7Hqv36f7iGKfaXQmvwwIkOY8H2KYBOpRuwOPMwj1Ez+LZipYbyI9\nmKj9lNhNz3+5fIKZFgF29TCo6d6au9imnNXR2ZW7fZGiGKIOKv265X3hNpcDmYeyEeetT7nHsAlV\nElEAcD62bZJAp0i5Riea1lpN9hD7nin+GHCGsCd8W9cYSE22IJKvejLcO5WgiW5lvqCCDCvfwO9I\nasCxXebGi4uqUSQJBxRfSbhVSG8FeKR4XldRaugEqxc5/843LFRdlm1V832Igc+G8q/M9pmobo56\nB5/SwdIjFyaaBofHMML2Dlv/P5YHqmWOMGyNfBRWRtS9gcE2rNA5FtcXXli9iKiF1v6ngG3GKJVS\n1zkwJNaHKKV8OMARo/c3JSYi/l7iC8eWvXxNDMKc/3fjIVgTCeY7RM6H6cWYQQdJoPqR7EG4bDYR\nosVI79WGWVefVhS3TxGX8UYWAxQLbwhbOuie2aLQBy7YXgMNPgV8PIPPHFmVIzHhEZA1OuVkbi7G\nGFhRIUifmPq5g6EVr+xX9TuJHZWSJJUT1/JUWNRNVOu6XNpNEeP1S2ghf6oMAIr+ISdEeDNZOJO9\nwXy8Rcklo4dPaT+lHianOxRpRHEX5YMO55V6aeibuQKXJRwjgfWnbc0EKoPuor8XUbqug/6ZE7j1\nE7yXZYS7KtOsUnB17h6KzjGFznBVRt1q+84oVWJKQIROClMVT9XTjGP9kFT70snh1O9nsL/grGB0\nfUzU/WoBVRdp0oFtZ26Hk82ha/hl++Uivq8UDIol/hzYkA4wQBuvgSSCvkmMbHWQLfMHy9PjciE9\n/e9Vjgvc9KbFGHTb31tbg4MoGmcc0HGO3raQPrLTnXfdGV3VWfGKMfy/RGdSD57qi9E3wNrgGMSP\nBKiCjKLPLI3xHu2qsaJJ2F8uno+WVTOfp2lZxEBWxLGsES+FmU65TrT1fy5ZCeIeaHQabk/HcBXt\nF1uSFz42aPdTZA0SqK5+4faKUTata+cQjVPjsAADtfrToRZy2d+6EHlvXC9ksn4GH17OlPSdv8pP\nnpKDZ1eaJxzV6D8qqVXPOFttt360qx7cWRYCcFenhFVUpxBKZfuQEW7mYS9lVhghyDTWX5chKYKm\neC/efWFFT30OfTwIwInLus4LYOnj8WdaxW9uNOTfZoric7rUiAhwkJb3wNBW65F4QwRZdlyJ1Feq\nkEi+rEKgRdqli6dElxf6CVDapNmiUshH5HOp/PN/FbkZZxw1EZBecJ5TzDfX5rhFCPZqvWb3T7je\nx4Rg0yb8S4ora4wundEjGAzJvfgGZlpLsiHC/UJe+I4zbZAucVG46ZmOgKdt+Z0m3YhyMH1RA5tp\ngR3G4qTnB9TvDF28GTvh5m+KaTNQxve9wPIRpTpVveO39FeFWdrs/8z/yfDbqaBSyFBkaPFFKU0E\nnjRhobVb+g1SYKEkDZYWqeJ6jOLhSqsmpktl86KRKj5T+ZHI0KDotADU2BybQyijJDyR5TvNLU2z\noLnSh+nuPPP/uQ99UDd/ES+CYINuFbbN5iv3ootOk752D8/+eMepxL4TbjcVeiMJsglorDY26rQb\ntHspGg9kI+tmPLftbvJLY1Ah/jkqc9e9dJrx0Gd2X+zVGNFXtgRQEDiG0HBcACcNuC0sNo8ufju+\nDLi3gbESCBkLR5/Ku6ErOVAIaS5saiy4aDoQnu2wbBZfRvVdFLCJxpISgQCcyzt9/4Ni3fLtQqiT\ntG/HKy5+RvsyDoImtnejDJx1REIWGfd9yxIoLnsb7gSJxk3qqKd1HZJRBpcVjUQ/g9EWWECeSSl6\n4BN3NqO9qO2cEU8Gy59FzzD6Nqet0wfwTgbLbeI1ULxDlaghm2HBKvemR//cQPfelFaw8oT0H2pn\nE5IBJs/LYwG8S5XcAN/bT1DfjGTTPIqkcnCuKTJJPisEplPXbcpn9c5KWjApA4dBZiDuABxt4LRh\n9k0hb3AeHhWXvrYWj57EiwiOlS3XOg6iJv7BKgiZC/UJz4yuH/J+IERjAKj6dQ0pqveXN5Ghp5l1\n1hUwA/eKbHE1h9S+2oItwWl1gxNcmjYk3i3ogZVpSmkUoxeyVDyNTrZviXD9FcFBgUtAGOaEetbq\nZFyHbI1B/VBG33BnvSJ2WgGyypH5ggV7azeAYZ7djam33U8yU0wMIMtj7bTxQWnhhEITSH3TTa9E\nndkI06pkCNH0SA7tahb3c6IUOkrLqxZ+1oR8htcEE1AIEpHTBX4kNQHWjAJIxLC6KI//lbj4hk6n\nXCIYAKrm/P7sFmWEwDD8AQYqpChgDejn9MV+4YQYreP5x71z0l5s+//OS6fNIY1YQqlKAnJFgSiS\nkL8Mop5IvPv1Lca7HioxXCMT+QXJ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protect end_protected\n", "num_lines": 510}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_sde_c2h_dm (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26,\nprobe27,\nprobe28,\nprobe29,\nprobe30,\nprobe31,\nprobe32,\nprobe33,\nprobe34,\nprobe35,\nprobe36,\nprobe37,\nprobe38,\nprobe39,\nprobe40,\nprobe41,\nprobe42,\nprobe43,\nprobe44,\nprobe45,\nprobe46,\nprobe47,\nprobe48,\nprobe49,\nprobe50,\nprobe51,\nprobe52,\nprobe53,\nprobe54,\nprobe55,\nprobe56,\nprobe57,\nprobe58,\nprobe59,\nprobe60,\nprobe61,\nprobe62,\nprobe63\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [15 : 0] probe1;\ninput [15 : 0] probe2;\ninput [31 : 0] probe3;\ninput [0 : 0] probe4;\ninput [5 : 0] probe5;\ninput [2 : 0] probe6;\ninput [63 : 0] probe7;\ninput [31 : 0] probe8;\ninput [31 : 0] probe9;\ninput [31 : 0] probe10;\ninput [0 : 0] probe11;\ninput [12 : 0] probe12;\ninput [15 : 0] probe13;\ninput [63 : 0] probe14;\ninput [12 : 0] probe15;\ninput [7 : 0] probe16;\ninput [6 : 0] probe17;\ninput [6 : 0] probe18;\ninput [6 : 0] probe19;\ninput [6 : 0] probe20;\ninput [0 : 0] probe21;\ninput [0 : 0] probe22;\ninput [0 : 0] probe23;\ninput [0 : 0] probe24;\ninput [0 : 0] probe25;\ninput [0 : 0] probe26;\ninput [0 : 0] probe27;\ninput [0 : 0] probe28;\ninput [0 : 0] probe29;\ninput [0 : 0] probe30;\ninput [0 : 0] probe31;\ninput [0 : 0] probe32;\ninput [0 : 0] probe33;\ninput [0 : 0] probe34;\ninput [0 : 0] probe35;\ninput [15 : 0] probe36;\ninput [0 : 0] probe37;\ninput [0 : 0] probe38;\ninput [15 : 0] probe39;\ninput [0 : 0] probe40;\ninput [15 : 0] probe41;\ninput [0 : 0] probe42;\ninput [6 : 0] probe43;\ninput [0 : 0] probe44;\ninput [0 : 0] probe45;\ninput [0 : 0] probe46;\ninput [15 : 0] probe47;\ninput [0 : 0] probe48;\ninput [6 : 0] probe49;\ninput [0 : 0] probe50;\ninput [0 : 0] probe51;\ninput [0 : 0] probe52;\ninput [0 : 0] probe53;\ninput [6 : 0] probe54;\ninput [0 : 0] probe55;\ninput [0 : 0] probe56;\ninput [0 : 0] probe57;\ninput [15 : 0] probe58;\ninput [7 : 0] probe59;\ninput [0 : 0] probe60;\ninput [0 : 0] probe61;\ninput [0 : 0] probe62;\ninput [0 : 0] probe63;\n\n\nendmodule\n", "num_lines": 189}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"ila_sde_c2h_dm,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_sde_c2h_dm,ila,{x_ipProduct=Vivado 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013_WIDTH=1,C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=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*)\n\nmodule ila_sde_c2h_dm (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26,\nprobe27,\nprobe28,\nprobe29,\nprobe30,\nprobe31,\nprobe32,\nprobe33,\nprobe34,\nprobe35,\nprobe36,\nprobe37,\nprobe38,\nprobe39,\nprobe40,\nprobe41,\nprobe42,\nprobe43,\nprobe44,\nprobe45,\nprobe46,\nprobe47,\nprobe48,\nprobe49,\nprobe50,\nprobe51,\nprobe52,\nprobe53,\nprobe54,\nprobe55,\nprobe56,\nprobe57,\nprobe58,\nprobe59,\nprobe60,\nprobe61,\nprobe62,\nprobe63\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [15 : 0] probe1;\ninput [15 : 0] probe2;\ninput [31 : 0] probe3;\ninput [0 : 0] probe4;\ninput [5 : 0] probe5;\ninput [2 : 0] probe6;\ninput [63 : 0] probe7;\ninput [31 : 0] probe8;\ninput [31 : 0] probe9;\ninput [31 : 0] probe10;\ninput [0 : 0] probe11;\ninput [12 : 0] probe12;\ninput [15 : 0] probe13;\ninput [63 : 0] probe14;\ninput [12 : 0] probe15;\ninput [7 : 0] probe16;\ninput [6 : 0] probe17;\ninput [6 : 0] probe18;\ninput [6 : 0] probe19;\ninput [6 : 0] probe20;\ninput [0 : 0] probe21;\ninput [0 : 0] probe22;\ninput [0 : 0] probe23;\ninput [0 : 0] probe24;\ninput [0 : 0] probe25;\ninput [0 : 0] probe26;\ninput [0 : 0] probe27;\ninput [0 : 0] probe28;\ninput [0 : 0] probe29;\ninput [0 : 0] probe30;\ninput [0 : 0] probe31;\ninput [0 : 0] probe32;\ninput [0 : 0] probe33;\ninput [0 : 0] probe34;\ninput [0 : 0] probe35;\ninput [15 : 0] probe36;\ninput [0 : 0] probe37;\ninput [0 : 0] probe38;\ninput [15 : 0] probe39;\ninput [0 : 0] probe40;\ninput [15 : 0] probe41;\ninput [0 : 0] probe42;\ninput [6 : 0] probe43;\ninput [0 : 0] probe44;\ninput [0 : 0] probe45;\ninput [0 : 0] probe46;\ninput [15 : 0] probe47;\ninput [0 : 0] probe48;\ninput [6 : 0] probe49;\ninput [0 : 0] probe50;\ninput [0 : 0] probe51;\ninput [0 : 0] probe52;\ninput [0 : 0] probe53;\ninput [6 : 0] probe54;\ninput [0 : 0] probe55;\ninput [0 : 0] probe56;\ninput [0 : 0] probe57;\ninput [15 : 0] probe58;\ninput [7 : 0] probe59;\ninput [0 : 0] probe60;\ninput [0 : 0] probe61;\ninput [0 : 0] probe62;\ninput [0 : 0] probe63;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_5_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(64),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2017),\n.C_MINOR_VERSION(4),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(0),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(2),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH 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n.C_PROBE65_MU_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT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_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1),\n.C_PROBE691_MU_CNT(1),\n.C_PROBE692_MU_CNT(1),\n.C_PROBE693_MU_CNT(1),\n.C_PROBE694_MU_CNT(1),\n.C_PROBE695_MU_CNT(1),\n.C_PROBE696_MU_CNT(1),\n.C_PROBE697_MU_CNT(1),\n.C_PROBE698_MU_CNT(1),\n.C_PROBE699_MU_CNT(1),\n.C_PROBE700_MU_CNT(1),\n.C_PROBE701_MU_CNT(1),\n.C_PROBE702_MU_CNT(1),\n.C_PROBE703_MU_CNT(1),\n.C_PROBE704_MU_CNT(1),\n.C_PROBE705_MU_CNT(1),\n.C_PROBE706_MU_CNT(1),\n.C_PROBE707_MU_CNT(1),\n.C_PROBE708_MU_CNT(1),\n.C_PROBE709_MU_CNT(1),\n.C_PROBE710_MU_CNT(1),\n.C_PROBE711_MU_CNT(1),\n.C_PROBE712_MU_CNT(1),\n.C_PROBE713_MU_CNT(1),\n.C_PROBE714_MU_CNT(1),\n.C_PROBE715_MU_CNT(1),\n.C_PROBE716_MU_CNT(1),\n.C_PROBE717_MU_CNT(1),\n.C_PROBE718_MU_CNT(1),\n.C_PROBE719_MU_CNT(1),\n.C_PROBE720_MU_CNT(1),\n.C_PROBE721_MU_CNT(1),\n.C_PROBE722_MU_CNT(1),\n.C_PROBE723_MU_CNT(1),\n.C_PROBE724_MU_CNT(1),\n.C_PROBE725_MU_CNT(1),\n.C_PROBE726_MU_CNT(1),\n.C_PROBE727_MU_CNT(1),\n.C_PROBE728_MU_CNT(1),\n.C_PROBE729_MU_CNT(1),\n.C_PROBE730_MU_CNT(1),\n.C_PROBE731_MU_CNT(1),\n.C_PROBE732_MU_CNT(1),\n.C_PROBE733_MU_CNT(1),\n.C_PROBE734_MU_CNT(1),\n.C_PROBE735_MU_CNT(1),\n.C_PROBE736_MU_CNT(1),\n.C_PROBE737_MU_CNT(1),\n.C_PROBE738_MU_CNT(1),\n.C_PROBE739_MU_CNT(1),\n.C_PROBE740_MU_CNT(1),\n.C_PROBE741_MU_CNT(1),\n.C_PROBE742_MU_CNT(1),\n.C_PROBE743_MU_CNT(1),\n.C_PROBE744_MU_CNT(1),\n.C_PROBE745_MU_CNT(1),\n.C_PROBE746_MU_CNT(1),\n.C_PROBE747_MU_CNT(1),\n.C_PROBE748_MU_CNT(1),\n.C_PROBE749_MU_CNT(1),\n.C_PROBE750_MU_CNT(1),\n.C_PROBE751_MU_CNT(1),\n.C_PROBE752_MU_CNT(1),\n.C_PROBE753_MU_CNT(1),\n.C_PROBE754_MU_CNT(1),\n.C_PROBE755_MU_CNT(1),\n.C_PROBE756_MU_CNT(1),\n.C_PROBE757_MU_CNT(1),\n.C_PROBE758_MU_CNT(1),\n.C_PROBE759_MU_CNT(1),\n.C_PROBE760_MU_CNT(1),\n.C_PROBE761_MU_CNT(1),\n.C_PROBE762_MU_CNT(1),\n.C_PROBE763_MU_CNT(1),\n.C_PROBE764_MU_CNT(1),\n.C_PROBE765_MU_CNT(1),\n.C_PROBE766_MU_CNT(1),\n.C_PROBE767_MU_CNT(1),\n.C_PROBE768_MU_CNT(1),\n.C_PROBE769_MU_CNT(1),\n.C_PROBE770_MU_CNT(1),\n.C_PROBE771_MU_CNT(1),\n.C_PROBE772_MU_CNT(1),\n.C_PROBE773_MU_CNT(1),\n.C_PROBE774_MU_CNT(1),\n.C_PROBE775_MU_CNT(1),\n.C_PROBE776_MU_CNT(1),\n.C_PROBE777_MU_CNT(1),\n.C_PROBE778_MU_CNT(1),\n.C_PROBE779_MU_CNT(1),\n.C_PROBE780_MU_CNT(1),\n.C_PROBE781_MU_CNT(1),\n.C_PROBE782_MU_CNT(1),\n.C_PROBE783_MU_CNT(1),\n.C_PROBE784_MU_CNT(1),\n.C_PROBE785_MU_CNT(1),\n.C_PROBE786_MU_CNT(1),\n.C_PROBE787_MU_CNT(1),\n.C_PROBE788_MU_CNT(1),\n.C_PROBE789_MU_CNT(1),\n.C_PROBE790_MU_CNT(1),\n.C_PROBE791_MU_CNT(1),\n.C_PROBE792_MU_CNT(1),\n.C_PROBE793_MU_CNT(1),\n.C_PROBE794_MU_CNT(1),\n.C_PROBE795_MU_CNT(1),\n.C_PROBE796_MU_CNT(1),\n.C_PROBE797_MU_CNT(1),\n.C_PROBE798_MU_CNT(1),\n.C_PROBE799_MU_CNT(1),\n.C_PROBE800_MU_CNT(1),\n.C_PROBE801_MU_CNT(1),\n.C_PROBE802_MU_CNT(1),\n.C_PROBE803_MU_CNT(1),\n.C_PROBE804_MU_CNT(1),\n.C_PROBE805_MU_CNT(1),\n.C_PROBE806_MU_CNT(1),\n.C_PROBE807_MU_CNT(1),\n.C_PROBE808_MU_CNT(1),\n.C_PROBE809_MU_CNT(1),\n.C_PROBE810_MU_CNT(1),\n.C_PROBE811_MU_CNT(1),\n.C_PROBE812_MU_CNT(1),\n.C_PROBE813_MU_CNT(1),\n.C_PROBE814_MU_CNT(1),\n.C_PROBE815_MU_CNT(1),\n.C_PROBE816_MU_CNT(1),\n.C_PROBE817_MU_CNT(1),\n.C_PROBE818_MU_CNT(1),\n.C_PROBE819_MU_CNT(1),\n.C_PROBE820_MU_CNT(1),\n.C_PROBE821_MU_CNT(1),\n.C_PROBE822_MU_CNT(1),\n.C_PROBE823_MU_CNT(1),\n.C_PROBE824_MU_CNT(1),\n.C_PROBE825_MU_CNT(1),\n.C_PROBE826_MU_CNT(1),\n.C_PROBE827_MU_CNT(1),\n.C_PROBE828_MU_CNT(1),\n.C_PROBE829_MU_CNT(1),\n.C_PROBE830_MU_CNT(1),\n.C_PROBE831_MU_CNT(1),\n.C_PROBE832_MU_CNT(1),\n.C_PROBE833_MU_CNT(1),\n.C_PROBE834_MU_CNT(1),\n.C_PROBE835_MU_CNT(1),\n.C_PROBE836_MU_CNT(1),\n.C_PROBE837_MU_CNT(1),\n.C_PROBE838_MU_CNT(1),\n.C_PROBE839_MU_CNT(1),\n.C_PROBE840_MU_CNT(1),\n.C_PROBE841_MU_CNT(1),\n.C_PROBE842_MU_CNT(1),\n.C_PROBE843_MU_CNT(1),\n.C_PROBE844_MU_CNT(1),\n.C_PROBE845_MU_CNT(1),\n.C_PROBE846_MU_CNT(1),\n.C_PROBE847_MU_CNT(1),\n.C_PROBE848_MU_CNT(1),\n.C_PROBE849_MU_CNT(1),\n.C_PROBE850_MU_CNT(1),\n.C_PROBE851_MU_CNT(1),\n.C_PROBE852_MU_CNT(1),\n.C_PROBE853_MU_CNT(1),\n.C_PROBE854_MU_CNT(1),\n.C_PROBE855_MU_CNT(1),\n.C_PROBE856_MU_CNT(1),\n.C_PROBE857_MU_CNT(1),\n.C_PROBE858_MU_CNT(1),\n.C_PROBE859_MU_CNT(1),\n.C_PROBE860_MU_CNT(1),\n.C_PROBE861_MU_CNT(1),\n.C_PROBE862_MU_CNT(1),\n.C_PROBE863_MU_CNT(1),\n.C_PROBE864_MU_CNT(1),\n.C_PROBE865_MU_CNT(1),\n.C_PROBE866_MU_CNT(1),\n.C_PROBE867_MU_CNT(1),\n.C_PROBE868_MU_CNT(1),\n.C_PROBE869_MU_CNT(1),\n.C_PROBE870_MU_CNT(1),\n.C_PROBE871_MU_CNT(1),\n.C_PROBE872_MU_CNT(1),\n.C_PROBE873_MU_CNT(1),\n.C_PROBE874_MU_CNT(1),\n.C_PROBE875_MU_CNT(1),\n.C_PROBE876_MU_CNT(1),\n.C_PROBE877_MU_CNT(1),\n.C_PROBE878_MU_CNT(1),\n.C_PROBE879_MU_CNT(1),\n.C_PROBE880_MU_CNT(1),\n.C_PROBE881_MU_CNT(1),\n.C_PROBE882_MU_CNT(1),\n.C_PROBE883_MU_CNT(1),\n.C_PROBE884_MU_CNT(1),\n.C_PROBE885_MU_CNT(1),\n.C_PROBE886_MU_CNT(1),\n.C_PROBE887_MU_CNT(1),\n.C_PROBE888_MU_CNT(1),\n.C_PROBE889_MU_CNT(1),\n.C_PROBE890_MU_CNT(1),\n.C_PROBE891_MU_CNT(1),\n.C_PROBE892_MU_CNT(1),\n.C_PROBE893_MU_CNT(1),\n.C_PROBE894_MU_CNT(1),\n.C_PROBE895_MU_CNT(1),\n.C_PROBE896_MU_CNT(1),\n.C_PROBE897_MU_CNT(1),\n.C_PROBE898_MU_CNT(1),\n.C_PROBE899_MU_CNT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synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4367}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nbGT7tfmyts6/yZChogAFs2kP2mbFmmuiFroOv0r8QQv1hFG6JERBCXNBXfGou+8mLPigR5LV4eDx\nWE5VTd+gHQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nCWoEkLQgvsHNvKsNgOsMIlwqULIpu7GrNWea7T7cH++wHThbYiHobD6dcKucCQM5dNGL646pzspi\ngvc21hWZnPx+X5N28b2dNoegtcTB2kLdLw7Lks54cB9DeoTavLfTRXQYufpEksbrNJTUFVb2cNyN\n6BMeJUXHbb0vXcc5VT4=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nFNNqjXbqqfIGkUevtN9QbqDJwQreUsmu9xji2a/w3CJH665OoQqvJUOiq4+1ZDezrG2FheefDlOu\nudQOQzfUbqq4ZB7QVsrZ5+hnOl4+bTdi/FvverAngGvvJSU8+8gbzJ8jtcieV+kp8HrIMv5M1gu6\nVP5SY5P9OIiRMPqToUbAWBrFRpgduuTuMhaHwW7FZmVUVb1j1U3rE2T6UyEel2fueSISKzjAYa8d\nbMNfbkA2ORUFxDxV3b+bBcjCg+jYWECoAY59uutuI1TCRGdhy4DLAvrLFqaLXnKzQ/zhmv78sBnu\n10yEbUQnFKzl5lQwpKtElSrzEVryLPjEKxtU0Q==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nBtsuQ3rIBJ3UI+4s+peHFvk2pezsWjwgWqpQQAOktytWfnh45F6oITlHSewxA1WtBlnC7B06RlL1\nsh5uBcV81aLk24XWmuA7DcJrmhXRSOvl0k4gIwFckG2lpuYtWsH8y7owyOiD/FZUz/LSfTa3Mywh\nD7uNSNvKmmqFP0yIDB9zQtZJYDKPgeAlZS9NUZdzjF/a61kdekWKbPaCmwFQ0mA01X8N8Euy78Cm\ntwhuK1u9d5vu3NtNKQQjzffGoOig7AOKPE+KjZrhCajjfXLjFewajxJNXuRqE4Qr4GGCy18JUK+r\n9AD7YQrF9CXYq3xjR5zoOedNXXQz29GC/jViKA==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nGzBT1kWKJ35ymgjppXjhmBsPZAh+qqs629kt2BvXZjQHKHWH3WuilMysbQpFcvgaH9NxbR7qFPN6\nyb5XgBkpZDUCCrc6p6YR51wXM/nxNvw23FSNPFKjoFEw2V83YYFxlbr75lWeNCQl27cPfBPuxaSV\nIjlxIsm4eW9SkxEnTQqMX5ySy4IaL9yElffDeFxfvmZFrx9lJp5FMRFsWvs0CJEBnPV6KLu1CvY0\njoTQyovEbzWILZvpO6OoWWowRhHO/ukpDVkTQwizIuNbetdcKud8UyyAngECUSjve9k+rXX41zHR\nrDfFrjZc+RPg2YpdeYHykcsisoZ5sdzyCy4T5w==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\niim3M0ZIoSIeblUIY0hk1kn3BvlRMe2uVKS16OYK9H9BGNvnKistWqz2WEU4s7eijjhhkWdw6Rx0\n1TXQht76iCER16gWcazz66/Akg5MH+lOp9NPf3J2iEV7LK7f+3F9jgvrsadzyPoTuLecIoWFoNJk\nFXdJK8072alT4ln/U8w=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\npJ/yajVXTo6y0FFyEOL0HIGDXa+xEims4jF/m3KWWifm3tyRZ/Qmr6px8fbYo6wt98IysxEsBMsY\nOafake1VkQe9IEYdvl9w2pbHgnMGCgpFHt5GVkkx9kTM7g8X5yw1cj7dCjsuNtLtsSeZ7wW2gvp4\nba+UNyDRcpm3wErDehZlm6QU2gigOYOXUMH6KQLyei8VsyCUEOLrtDfoDMEgbTsPan0OVwWZ4Yma\nBViyJ567bWm+BUmLR7HMTK0+QktDEmFhL5lWaTS848MSM8+2esUyNGdKKutfcQWcpHUx0GkIOnS0\nlZ1qTioC56L1NI2aXWshT+ZrJgi5x4ZYDqF6IA==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64336)\n`pragma protect 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ikj4QY9qy76XYw6IDsQdBnIGtPSFwxd9wChRjkni7PaX9nBoTv4Hkv4/X71ms92d\ntJ/07jLvlYIC/ZQu83ENzkpZcQxr+WVAlk9voN1Lh8MJ41Cksb/e82lQv3tE0i33RVWsfpzzkmhl\n6+iCuWQ09/k8dS0FyYp1eOOSakJpDvCoKsuGEA54TK2SkuCKjd+GAxav426xXnGAV1GxKJw4LUC+\nBoIDk42kjGmgDrTucR4D8ebhRKZlfSndBkUN1MxM4jhRdlUOlo1unmkpDpwboVbaBL63n0cP4G6M\nMWgaQmfg3Yi3VurtkG15kqklP5W2hoXk4N43ho9pwxbkiD0fB7BonN/w9HJv4Zu26k8JguWWER+r\nF24R1GsE91Dl6f8PkWleIhz82kPHFEq5RrhTesz5mPkAh4LBNNYQcbTVLlK5Bz0FGVt33lgt9zoT\n1OXASFCArKzZWd2y0Q5uZ6j1/oVxBrIIV84Ebwg//J/PeKNV+7dWoxdxrSyxxRk9/vGvVL/UxkDL\nXNFXWyLhbVlxG08uYDNL1cw4o1C3ePlskKxvHjLKaClc/79HN04C/k9fm51CrfmvosEcGzKhDPBj\nHMwFxAT3Pw83gG0A4Em+qHW7Wk8Bzor/p/e6kDCX2WbCTGXt8ZMf/Cq6Dryzr2sDHKfteVQJ2fpF\nHC/D0b26BUXdwRPX01IK0w8qiZ5/xcJUdwszggylh3pIeyt8qnPlZ1xYYH05884oekPtILD0GlZx\ndRw6hgHq6NYCifq33HepQkocmMaiBik7yzszAuKAWn2x5Raf/FC2GSRLb3itncwKnJGL7yYaSZeJ\n8OUhkMmGPtZ8ImThhDZ/RWkOBq+OUYnTNhKc3FmrCT9LsMzW0ZyQ9o+VsZv9bTJ+USliatHl6PD/\nLRypXj3clKV1a/C8C+rxwRip4mEQfKcf0UiZgBr6eYubS93izNsyymJ1mp/BMX6jt+kcmR3LAEE0\ncpyyOM0mIgNkjmJmLmv3R6jg/bPvI2p1N7/cIyybB4G0BZtRYMXRngfz1Q6EMQeQVsUna9iAjvQy\nAG2r/xcgJFufo3kkRGq2V3bTmOg/azUFNjzL/9jw4R6mkP391rUCjjKNDXYCpxvDS4Ye2p86OKcN\nXM4s+2bmJRe5JMBVj+0ZHS7ii0Mabn0ehWpoyMokVNz6dMpxel4glyyMLn1uEeaGHRDWuRfCqrOB\nfTnvUVJz1HNeGj9q7pSndbVygb7ZUsG8h3ZCkcyQhLOw47qwv3lDHtO77/HoYY9Tr62YzSiUh3z0\n9j8wCnOkMiqstzZ3iSyRXlGTQ8cV0IIcZ4obZHfQfj7I+N4MXnxEm4Pf8DHrXxlE0RxiG3MLn8Qp\nv1AES70B0p6TKWBC7H1cOxVI/K1ykT6KjY377HDe//18VNIC6IlFJzNuCN1q/+iLfRWlGy+uFMco\nAuFhgOP9A77fsu7sTi6ay+PaHjwC+jIiDGXdUXLPAJHxpDQzZfnDDo14bCy2ZRz1RWNEkUkLH6tY\nuGcD3kggbTyfoEOTkCtHzmGI7kFz1z7J9DYLueA4OMGamCdMbQxvlcUkwx/Yam/jPH2MB8HtyspC\new/FctHMgwthFB+FzPoSwmv+vsUZD7p8hri9LeoCnXPfXS7B0PhDyaHknDkaPDhEol1WramhVo0u\nGKZ8x1eDO9ipKqbYemWHLiAhYr8UXDVwN94diYZ9VcYwIrwr1P2VsWG/9O+R3rFngUUFk8Z4Bvip\n3PBfNVwE/QWhb/BgkmHeTvSayZckM9vCuruECucSChqNjhhIvSGY8CStQKNM+eK89IlUPsvIBY6l\nRZyKERWn9mxbX4ormBumHi4IznKEziX9fRRAEGW0uSLFhi/c435Qai4kSdBAoqvRTsu+7pIC8yv6\nmZ3UTSFrP9ATOE0GChYyllkCW590wKjCJcVXcdotPCuG+4IkqGFXeEYFfkQRLFX5drsg6AMEKhFl\n8EQOwjKQBjK4HT2f4vT4b5aHjEJ05K9SP1v5aTcX90VaEP5hR0OJDY8zsD40NbAozDPvBHZFX0ED\nIRhn+i/XVUxf4KkXcZ7BGUHiQvjXmiD7rd4O0nP0t99gvs5eB1QqiK16/QSY+J8Hu63WZWcdZZAv\n1Bl0sb7QjEa1onPN6MvMm284XZNYPuENoTvl84tdVpwWTTy6KaFjMfpGvs3Zw5rbRYjDqMU6FeLb\n7tSZ/ahWSGlsvFIWoqELhastLHLkIeMZyt8jlYUTAGEOEEraoePUOpjacUg8HrSpHie81DOaay7P\nAAzT/Is2R6begRrTAGNPq50SNgzPNmJomzUDHxlbuHeJYqnJzbTNmu2mm/QNIY5g4T3/ZUKkVv9Q\nrDjVCP+lEG/cEUycZ1Z78nVFuQWmcsM+c+assi7pL+uhWZzCPQizzj2hiM7VoacDeeG1IZ5IwMq0\nXp2/giop0Ak1pp75BsLEDXdzpcD8l6Gf+GZorCsODJ9BfSE12ihwudD2D7osjC/C/bUYdsrC/chx\nlQYFtNBnmCnTwsSK1xoevId8Y2WMMdNPuOhUUHqEtFNHL4EK/KM3VZU+CxrDDhp/Z7aMvgsweO4e\nFmHhSnvDyIGqCB6yPNMXL+UsWckLz2OL1rLGupkCvcfX4pwo9bia0CTK1ZkU5mrPXtvJ8iLvH5ZD\nELwT4RUG2uPfT9F2VS7xhdsTOj5USFtL68jcB4lQ3LdUwqMunj+M/wFkRUsc5Wo1Rna/htuyd3aP\nmvR4afocTUND8sbqWF86oE0b7M84KSsFKWn254Yv45b/7AGVXhW/zTIDhey6hbDDHa3zUhsRJ+sd\n3a7q9Kv9D7ax7QymetYPp67OmrE0CctHogPx89wzVtGxxpSFh+PSbv3u7EfYVFE5UV70g5dbWi52\n3Fe0kbBYQmCR+aJTy4hgxK666akTNVD8jx6UNgpOeJ9oLxbdi9gaCeP4YvldmkPNuv6n5m2SSHCN\nysHNq38Ri4NO/g8LNN3ZqRaQeeW04n7wNj43g2u7Q+AhVjNDn+3cUoMWV0XEdGhAlsvLAziOS8Aj\nAqOcs8PgfNLRn+/63nhr3S1tpn0oiSKA/UymFDp4XkFAl/NSQdSlZdl9yZfocKZ14yfbXP4naSXw\nYXdD9IJooJYT4vc3XhlNgoWURjW+vzbrQ+9Q0aDVLGwmTPWJcogLZSm4kAy7IhXy2y/e6LLI81FT\nbGmZxodxElq3jHE3z0CJEqoS+gsdBtdqC9QTMQaetDKYZvI5/vmZh3QKAamIvXVJ8TAgO+OxHgFd\nFxrvt+kVuLs1msjlkgS8mm8zfI4owlc5u5lmeVXtyCNHPLKHYAzzMNPW5Ai1OR6HoLM6UG/N2T34\nIXbk1QrwXKk878mT9EznzAhb/4bv6hoFEDgRIvCyyYweHxvzpmEfLiP6QaYNWWpO7iR/eaJHWw/w\n790hhWcg44VxliUVIWvozPbEuqHwxbBcXeC5Ksuxlmk8QdBhjHjrT3c76PX/AgEVe+DRzjzKRv5h\nMl6B13x1nZfviHANI6UOudXTe3BSkKBQatOSiKX4yGd35hKnuRYnDSNt1mYXH7lATfmjJFJ1TT73\nWSe0PhhtU7SE6IFs9oBDUTj2gUo4sKYA4alF58i9FJIqvxNGJAiLHJ8E/+pWe+aWwISfrECu9G7z\nfL+1k6nrcGpAegDvvNaMk9nvrHO5U8w3cCleTCuOdPKfWUgRuMapzh4NZ3PMrh8SXD1InQrZuBr/\n9wwsVObR2mdCCdXa+rhcQ78GUFqAhDlb/gDGwNJXRHEtPEgwsgr/EIIqHKun5yMnH9RkzScVLm+J\nhQtsd+JNrs4PPnSzdYGRKsNeWR1uZedxdvvmQuK6V9mJ1/9Rmqx/+sHIBiu+E3k4orWWGYdd/T8M\nGKqyT1rmVf0d2BrSPHzAKYdcRuxuewmDHbGVC3lq/yp65QOvQQO7N1EnY1gqIuYuYDxWjYKeiuwP\nQFDZvr5e0iMckylJHxO2Zkx+I12SyzSel48QzIAVnQmCTJ+X5gndrUh6LnLPRXJ6+tqzD9dfe3fA\nlb+egkye9h3JlbY+3Pjc+50z73r88qa/PpdTLyGj43GkhQTcr/5gW5n0AHoRaXiFYkNscs0Nos39\naAH1XRkvy408nbWfa2Gi7jxH7uI3+F3JkxicVp4XMzt+l+R+Dx0jSIyNA8oHaGXR7iODXmIVoCZV\nsxZNGSarntyxgE8l3LcO9FCL/iMvzfprNsX4JFDepRadUjspZB3K37Rtlr8GmaLhjZU3JZATm0vv\nmoZDKTaGGimpaBiPWWIIg5udEW5MYhrK4QvK8iJiuFcjIg4IBX3XEXi6+aZluEko16/4dzOkmd+e\nlZ5Dld272oEIa31In6knS3GnJn+b1p4s5Hl54tgnvGpXSISYPWD9Lq75SgxS/jHTRboTU19NRWhU\nGZYbeD0sh+mVjL2njjkPKpQ+0YFlelzdofUpHWOTVgDIGUgPQvZBn42WfsNJ/RV5TtsMZLjKLxaK\nKCX8wuFnxtCLoOUXBkbbosQYxnMAy1U44OrJu+0HOBqsrwNh5zFGJ/zk9/5utr8aQg/2aGimsg6J\nv7HyvEFEat6XUm+SLNRb4egTjBiPMHtEUqQzXg5WFNHpof6b17s5owPbAJDewviuC6u0+/FBomnn\ncjdCfOBsKr5oKtdJ9G/cfWevYkjMPzom6RgYqWKsOT4oXSsridVr9YSMbqMjs6TQyI53UUFHfVrF\nl0ryDtX4aJ6oq3I0s1jkTBQK2SVIvmMqBBreOHIPCFKB9G1cVT3e874jfndchxKWHYKOtVIJFav+\nL8Uo1/AnORfpmZ3MT04TOIfAJNO2opY0B5YuzT3m9m+wiD5/zMo6PmrcJJ3WVBY227wPW7hMWNNn\noOjAzzCrYiiO0/jDCB8OvnLChzLzTJmbwJe4z3LzHUGQQrZK+y5Tu/hI2S0CbbCb5l/4CxcADGOZ\nuOemAiz3WmIs6bykPvKCJ3YUD3M4F2iFz0Jc9H30enm5yuyqcKJoLQU5EWDirhIaywUHXRLN0ibW\nopXtRRfHpNK3lMJsLOJLnG0zXZGCJqyTj3qaVPfuys0B3+EBk12yq5qHRl4wt4HdS7zjxXqETTCS\nDWmTnT4ql9Ls9BhQoHCyeboOSARvoJCyg5bUFY4+3V+0E88wVyH2mpmkwGMTO1U7hbxtNJeZNcQw\n4x29DNm1Stga6kl3x8cvgu6djzr1ZOQOVMvIglT/BJQsYwV5NRK8kEiN/JrcDmE4po5lmaqOrEEd\nHnLyIi24A9t/bIbw350lCnc78BGA1Sk896A7Q8M8RbN/bHcWZcBBVJXli29+Go0U1cZ6vjpF4ote\nR7juv/pOYnF6fJkTyMQwM+5vzXEOMm7HcWdYRkQ7D3BbHuSVrhMBF89SrP7kn+SQ7CMEvfEG9gkj\noehWcUlTOkAPgQk+upUfEQ1V0IXIo+XGVCHXw1HlEAli9rLRlvLn2t99tZVdA9gnXSWDnaG0xm8R\nLth+31whyvvqwX0YwczoV5ZcVxTocWZwY2x4rKKiN1sDJ5PCIH5NrEMgJS2of6yaSC59QyvehjBw\nrRNKaNn2j7ZVpchE7btRVq+TWFqRMEnDj6B0wiKHy9A95fPH/jFUEg44Wgx2iIrKPooK1JfFJjbe\nTFsVM//5ug78qIzr214qkcwpUd+Zda7rHkJwxj4C8LcySIdWlAhhrFv5gtSCqrEIxbb4dyTvJ3v2\n29J4OwnSmjFaRx+7TxM4bH5xZBPQ9Aa5XDTCjtMA25CHWN46dF58ljRBnuxj/sTwdaqBLwjLFC/s\nAkRKeGbyuEkgZDGkgQ2uyOxRytYfZgUOGXyYAlgT4iE1lexh5KlOeiAzDxJoIQpPoMWANujOCHAv\n0CCpwPRIDa+2RYtlmvxXnQ/d9rmV/+bvuLlyg/PZfyF4lTfQ+gT5J6linBQ87uSw91z63GevX3vQ\nqIXoRUlm7FQIt6H+l7ILegL0BuaK/5858vbFl7BmT0xi4xczqNU5s5sPC7Jc1JhCohsjVnHvfwY2\n8qzZE/wJGg/5VjtcQrrIsoKjKqxGlUmOmA+gdWpIsqYx8y3lBO3oGE6LdohlPe50Ww3ftoagW1cK\nDi3dli+FTZBsGvAg9jehYrd6aHzVfHf2Y9oH7wo5VVoihibkHkzqoQtIf5kh+5qyhZ+GPgQhBdpC\niJA246TRn9v15Fx0Zn4OzczQG20209azn2UqWQULiPUy0AxceMoKJoI5ebd/IcNXjzH7HNmZBafC\nqmkvrkIAJJ1FNjBf+O0QphrrXFi8bHblHGOPHvgNOuyzywWWqrV4b4ppE4J2k+8EHYdTLVKZZ4Al\nYZ6gJSjesf8kxIgFcpqWikpTVY2Lip3rXeArsRv4MfC5Cjm1TjSdZAhN82oUsfszt8WRD+zl2+Yf\n6uRI8rD7tjXtB5A6MGRMrj9OUEXOgZhE4jqyNnCg6ichcoBhMt6I2frqhye4WGXAEMLI6vSDYRj9\nSnUdSngCYww1VjOT6c5zDafPzD96R10ddX1dvw2srvEC+Ie2efp5Qbmo1aa5lIQ57nk9WBJJvgaG\nXIhje8wa2mkKm5xLGWe4Y/yHPEpOwlPKyb3PhHzx+zIGduSAlzJSD+OZsJct2O03JrLOTWClXpm6\nN7E/Nv8Eynggtxy9yi27yj8r3I9F2I6vcGjNVurnmPRazqa6xDRN5XmvoZIxhaoyc22aS/cA2JTZ\n+yitWSfoXkzAXu6UL610+zmV2mfaoN5ISO0E1Wx5BXyYs9W4io4v/Vs5fF853UcjI07FeyIHaH/8\n633CANkUvI/Ls+GIu3A6u55H4++25ow4UvCUUjPyjgbvM08a25F/61H6L+v+hRkxKtflljcz2yFa\nWzu18dTrzpB6moutKoGhVnBhkISm1U8JTlUhMSkcwDMRjb+QWWk12wexPsUG6Klj1tbVZRO/kCWY\nBowdwm2TW2y2buml37GpNk8DTcKnOZBrPm9KGKJ8AlE+UZvGwdmwZM4ppd/KPXrDRTSAvtgLzqiG\nVO0RfMkmDngv6DSQR63QVXfQ7X1tI1VJcSzIp2FnlO5umBtoXaQr1f6iQLjZs8mHKNN1fbisbV3L\nkiGCuSBWjdyaz7i3nnyYk48bT0DCaLmk04mdPsi84JnyqcWa5HEqD8v1EtfmKP7KCxyqvL6jrGdr\nY2QrX1loreGJp1YQyZJ88Lde9IZlrVYG7X36FxaYuiTpVwyV0lodctAqii6guogpO85KUTYtLiD8\nz6r1LkdsS5eJtVm1N0V8qPJE3B7E5O9Eg3rSsAZegNJwfXmz0h/KOL7ee+E9kESRKPAwzZ1eXpjo\n4C2PK+Lp+RhF9n5kn9ahWn98OsYboOQ/+Vlg4ObgQeIu6hzKJ9jgtuWxYVY5shh7Jrt0uV7Ozv2e\nvnAZTy1CG+AMaHYhJVCrk60hH2jHdkHlRGewtI/rVzCQphSTu76+MqrhzPFiuWNwGvg6Wkz76LLd\nhfcCd+meSIE5pccdbl+mARINHJz0MJdp+AN9v2UrsfZHTUOOa197dKapTQboB938J0Vm4c9r5xEC\n0WRR7MoCZSLvTdcX9g91U68eqZ7aZgO5/oJqod9jh9AZDcjOZ/IZEEUBdlJN2ygo7ddcNiCIpE1/\niePuIMRKEXOabn+Jezy3oVmDxGLZMWCmCtA7SlmqKl+bDtba+c1jfk3rwir0Gc24AQTl/8/AiX3U\nhJTblGzrePrFEtjyEPyRKLCey9jkUXrRCnIJSxb3niKARYGPop2ovE37z/rUVgTWkWj8jruVtmUk\nXDa5ugQIukRCNmF4DRWY2R6KcBoaHm5VD7WsYZHIJKP4fX6X0xUFhGYGx2gj4VlXKa6ceqCBpmlR\nY2Yh5U96Y7N8lnKjQo/1tCXe7lQclT/F0y6KMMUbMdHp4fPwWIyBj8PyvP2F488jZKoaYDcCBAZ2\nFzAB5SJ9UtxvTWJ2r7LOFU29HmpRsScH+gg5k8G/675wfProbnZ3vGj83QtH1cvEl+BkwvWj05Kz\nu4d/mYBk6otvnaXixVDPAz/V9t+eNvXRwVNJ3mcfQ+DzZ8EIJ/yws4jWIkiSofX9OxpLH3L1BbA7\n7UR79P+vuAW2XLA4/voxPvt0BPlz+7oPINnLbEnB3HVWY4zM+EgWeBPAvZEkq36WAZhUBBNguE7a\n8RtT7QkNQq5ZyDg8G6KuJnpx0w+cCkCHtGWTV8maNSJha8Bnt78kTWeN+iarpU9NOyzxGbh3tniz\nfdzfLr9gC2z7ZDK1D3NObjjHSgBGOoPQ8zbZNjIRvY+3m6FqvjcGFJw4v3EallVzfNEk0eJgbrt5\n0rMp2kwHVSf/vfKqjcIHeIC8D8JG6DdmSQr9owY9/HqnlzR5liMglbcTS6FXDgmcLu+iYYFY28gi\nqFNSo1na61Urj23WxbaWilZLtC1U0TU7gS7GCuctgPqLDKFO1gglsegQThvzcuC5bwEwRlU3q91F\nd2p+3+bdCCne65OxvO0ehShiW6Lg+NgoKVG7qfTwiYnE81HF0ok/tcaZNbE709lTsFWC5fIF/MER\nVg2+dV7U6+rJIRf2tW/Pwavee5fm7VAUPC12UC6dZaK3h+YowDeF08FW2raiLFxqZjDBI7TWFZ0H\nlgE0OCIY3aNCGDGD5lhpZXuu5IHqEIrSKrM1p0vl+PZUNwzxcr54yP9/GvEGNovVn3YSTQaYB3yU\nMdTUt4B5/l/48spJ9IQRZJOHNqo4sGuVsLADOy/rNUTcWrlHcKgT0DiALq9k8rvybuyPaMmTKkvo\n6QP1WR0m668K4o1bSzt0rGulNFO1jk1Dp6cffsvGPPQdaLN/J3MNpUcjPMOpHBLyGTB5OqG/4mjU\nGR0byR0Cymms9sl3FH/LrcCbOEyY8FxsvPhszWsKD+co+nol2ncq/5AGd1Yj+E7pPniAvEi/hEuc\n4OVUmFlFYInGD4BlOQ4z7I+0hlGZFj1oOTrUsy1FU6g8j+6m1E2quppZMIkT8lgtWyT/mG+E3j+Y\nyTjtYgsbRn/oerrBrKpvvS3drB6tNlZMZrOZYn8xWzgC3RLspbE8JWwrsZom9BJG1f5mNF2P1cDY\n1foGVSlP8cZisVdTvgY03D/ummRYd74ziD9XcdWpWqYWeCk9MtNUuQRQnisPwsDyf6Iagbu8mRNh\nn4FglPLDfVH04Qx32QoA6E6bWyHKtStBKy4F067MkUQGvBIpLfKFxyXeG3zDRkQuj4joUnzGTPD6\nTFaSLk++kWojfrkMMF/LqnQZ4evnUMmoTH1Knr677TbVuDUTS2VQbRSGuo33/AnFJJ5IVlnIb7JR\nvdHAIG8g4zp0ZE/WmWTCIuOdEGmsDXsBGbtZJQbVHPez+8LOcItfUC96XH06NYNEZI/mH1wGdBNz\nUbnCsAnd/JUaDNe5hgGNc0aDcDfpgNVmPPTG5itNB1SjFzSZbsw+dqkjOYxUxdgxyqlcA2xAz5Rl\nnWuA56Icpx5LJgrYk7NaUiCvbiRjQ4JVAI3UQfibmloLegVPOu0WaahNR5z7gt93JISTsBZDOdJk\nkUX50GH3o+E5y2s5uQtEHNVzT0/VdOuuolIpCU5aoFcrFR5cuklmtaXcpJn6CFDQa1YzjoUaCnKe\nnpeJymF5dt8FbhIpA8PSuo0aBUq09MODdh/ZRaotvwLbYMDzWQIfKj0ndZV1nXBFjD4SQ+HoJ54U\nunuE4OZbTfvcC7ViY/RqV+Xkd/APQDwMfey+cXxqr7guko1eOqgR94FuW//L9CD1ZKsEvXpmRJdX\nBqYyUW6GK3akL3uIfIQCFtwyGi/BfEVu3rAbR3yirvflkC2o79Wa4BP+zh3tyGglK0Bvli6iar+A\nX1DA/dkwf4OqHuuG59dpNE4p/om4LMJXdl6SqXLhI4N5WxYtX2Px7ooR1NSZJl53yzBYZMOuzaF/\noaof3V2t8hYmlrfqUyBusIMDXGV41H5pi8vusj2z+i84D5mMz2c8T98Oa1CJKdCY5FXja1/TSWDt\nD2rNXOtcZgKzLQudXyS3jPb2TCMq3jOBycBDFH65nKAyGIFyeTKPn6cIAJDkBuSl+0bjUg8pILwC\nNmlAfw7DE+Eiq8aseLP9HhlVRm23B66+ryPSlSuUGIVmrtKKhWS5OKNDEqTMGEh4aw2sGNVVYvKS\nKbaGhWe60voQWV2IT9vuouA0hlv604k3/EwY0gODPnA/L93YelofcHaEhQEVx7iesFAVqq3KF2ue\nfKECodO8wfwW+RnycXayyuWlb2UnYwFI2AUUGCWpKShmVUarMlQKrWrIhTbO+g0vXa7E7zS+9fgJ\nWObDboS6oXv3rL6aUh8CdHvmYvR8QdSvfQvK+UvouZhsqTiycdhIO9oHLN5xkd4WWxloyOWerSvq\ng8/d8gOPzhBtKlPnJzkossrJkFwt5Y5+O5X12/+c6/n4WD4ZOddoCXy8i9kTQ3C5lp207Hh8bOmM\nea5HEgG4SoKB7kJtEIB1+5Ylct58MZUcUaHt8DP+uWNMSnY77vn+3RQm095pjevy0+URNb+7rW+4\nf1D/G4xH/mtDeKGQGekaf2e+KUEiKVb4PmHoTINrx6Pv9Vg01K5cEUcjJeCDoKZLy4NJ5cDzQSp0\ncPt7sgk2Up2jSOfivtrO0Yt9UzS2JK9RnBrxR+jG0sE8Zbi0U2UceMTAzYtt/pXz5RGbTXlxns9a\niforlRb+rHpcZmBqUbX9HMaGj3A8EC5aSERwk62OvM48On0A0lfW7ckac9U7bI2UeHUVkgbsLi2Q\n4mCjKZsKM/64VwaiUxvf9D7mLGgyX+4UWKpzdIXaxzIjlaWixYOcJEkwDwe+8BIlMru9C2uZ9+MR\noI4sbmHJOyvASFf3FlN2zZCEFPPuHoiN6H3y/IZd82q3xCaLNiMiNxMCRUgIHFwWdHt5r0lcTTdU\nh/TssUxGaa2KzM8lEo7CUkgMeoU8bWjB0DkaSXtusExrM1uNSd1l+eZsOMX7qzzJPEZeCatCFhK/\nBkWBpVm9vF4v3gNfhsVPSfkH1x/AbGjze0ZSaPJiPc4r7NcPoFZE1nIOIBABM3sJxT3mv3COVn+M\n1O/O7vXVwaMnugQOegqaROMi5zZn6fGJzhh8/8IIifmBei7ylRRqhJaE1IqGvLY8iw2CFgUbCsEJ\nQTppgPJNm59zRAa/4LWLZvs0u+wssdq6yRTOLomawCTb2+YSrSm4cBaef2FUqaY8z361WXyqdFpi\nCbmgzpCBcYWBcX1fLlSDN0FTptFOxlVLEmS1xO2GF472l8hQLEqEV7vfJvno+Z//8TjoVJ0mPAT+\nOodKgQ7+RnJBzAHC2bdAd6Wr5Cs1KYmxfeO1w8diEQk+7UEYEUfqDWOnhHM12DPdhcstSug+kJFe\nriF2f+ULJp0BKy2kJ/JJPAGRt53i1m2+71io+LzZha+RdggjfDKJr8EonB3mJTv6Ey/YxtD7/aPz\nsM+MIrZOFx4as9lBSVDYwTBZMvxLWLSdJsX/hZ8uFDZQxVyFQxfvrth/I158LUm56IUJcIyHeitQ\nJFFKCU2sw7McobUMR3H0dnKt749a5TFcp6Pt9OOnS0Kj2ZJ0zW0QRSFoUjeqWSlfVCVDBR7r2BpL\nG1tjy7Cqfqv1o53HItNjtOM4y2wZ53IpX5e+QjWiKzzYm5bi9Zw0sqCkhWYea/Ikvaaj5i7a+N2Q\nGUDekF0yxvDgpNKLYReqsEnViPjfOthZsiQ/ZF4f5FZkimf28UGqFSCYBhoyAoZCObcuokDZHSc7\nqbD8R5YbQFNmIhBTfo+LwHmZS9/r6GTAHKzt3NdOZJ+BlaPdFo9LoXpZFl7BISoGQNZp+cqJmxMX\nlElx0u0GPPHTNt6ilQWCwLZM9xFAQ5dH9aplVb1fFAdsjXUEJusNpQVa0ohBX/MlRqEA/ok7gkYU\nRg1Sl+gij7mTVCyaeKWlDR08H+GjsgnqBew6ptWyV+BLqxz1pIwS1TPPT9g2LEF/AXbgalw06Mhr\ngWyomNUgaddL15diQS7eKVlYwVtuO9Dio3USx5ootyq/tTQhrjkS124tYNG/4ozFsQy8kXW/28uQ\nVj60rTnm/QkMkD33zu8zBwXYOZ6+BhuSbsTph+WRnBagf9hxLJXfKYBbTirzgFHDPcrp6unySw1h\nXerYV26lMrK/9VrkVxxsC8LW/JGxQG0PHDl1cLs6YGseHZQa/ShX8XE7AtAYkJ56xfWkYduswh8s\n/xwWm/i19+VTuedahTPvXTRWxxvy7nbn2xV6LaUFixHNVy9k8lKLRdXzpNX1zCe2kB53fgz6XHnL\nxhN2WaHHuNFzUWCv8NghHah9YgCVwcCYh8YcQrqbuhpjVm/NprIxoZuqSuN1xRy/zfwU28FCMI0Z\nb3PwLG7AvfldFgTZPwBIWcODxzP894mHaNG9itsQjhW0ksSSxvYweLBofWtKhxFthCxXRjQYQlAo\n14uDlf24ruW2lki/ARokBEZ3c9WOn7xG+8a0XIAMh2Ze32MFWm50mba6Yk0jKXF7aZbfuH0MHbk7\n9U84WW80Rl7zWp7WK3mvHdR8kaFAyO/KFGsmPo3QwmBX3cmq0huPQVvvq9BjQq8b6DVoR0HRMFh6\nTS6HT6Gw205Po+wLRbrwzwbq6pUVKfHCySnZhHc2j3EXi1QjMy/UoGuW7bFHDALulwEzC7c4N1nP\n58hDhowIruHJ2UgjnpJYzV99YlPGs3RNfL2D5+uUFvkflxDXHnH14Ay7+zHIxr4HvncQGHOr5Fu9\nhSc76XDHb8pIGd8IdDD2aKLshPMrNF7ZVpt0IS/ThWkjpqI4HAwa99Oor5TJGkGnrK5nXCKl/V4U\neaSxXvHyD26Ry4NGBk2JasO8VqLSOVfuemwekAA795kOriGjdcU0hRZS0UK+YZIbt5M29s5xxQvn\nZgNF6Abotf57E+YP1F1eVCsopFPKfvATEpYTvUxBFxW4h/29TjMvkq9uvfS6ys+XhHfCrVIsAwv6\nr1aIxORiIZbULnlflxEryS///gUFpreGJpoPgLIzo848gKdf1bu+I5g+bikGAFcVIi27P74t0Q3D\n2+8X3z/i+DPkeMw0IwTCCxYpl/lnyV84ZlOjbvO+yak1dW85HmcOxI+Yx4X/aTWBxL1E1JUhsXny\na+5tcHCihqtH9TJ73Dz1Ctb0OQgLEcfPmziIrLrdgcEZv5fWYBjEp1PlCpqXnSKJik/ADIM2x1ZS\nwTuWTrBZXoTUnBmLXJvXwMOS3iK93JnKWLmogkAwQfj4NpYV9rRnNTEG8OtcRO6x+ScjxM3q2WcL\nNxMiwGOvrqy1PNsk5tqJrr+C/vX12LjRSBmKiu6xD3m84Sfo1ACMuimkJwSHDqd1FhpqLMWkEHd0\nTlg38sEgiPxPzQX8nNNDU+AP4ONfUTzkEdOKcKZiBzccH3Dh/3hMwpWY37LbN9EhqqQ6iS69/Nff\nI8jj0x7Ekmf6ZhNztfDvMTrHdMA+xBQdc4cL3BT8LiOLzDV8rROTTFwn8nHNro4jnAUqYf4sOABW\nwXiNohg3LLOwTe7gQpSThqCx5mSjmdOvwSEZXlSaciS6BJC8lgM5zJSzOURYOSMRl0CzfSVfiPjL\nl2lYdpYudLJqm32t+mntGbSc1wCqRy6djjjhFUadcHGBtn7ZMpcsGXeZ6PRYLYuWEiFrcxdeCBSJ\nMa6nR+aAfqAll8jQGr/c+1QtM1fgbtgUdnqpw2qWuRmW6LDkmuIxUHDJ+RS60L5zrYrgI27cYpEK\nUMcf/Dju2oqap/yP9KN2nvWiK6+OwAuvG22RDw7VIX/YU/KvVgED17M9VrSaGN8tqaHzNTGM2IDV\n7LGeSz1D15I00bC7lsM2GgX1s0o62Iwj6j/6deZ1ZiCwBtmmGzh0KCdzK/qSxCMHjC8qBAR9tQhk\n4mPouLUTQqh/4hTq4ku1SbVCqI3ZkjKytxnuhq5akCqQrq7Xx4JIaoeSH4sVIsXN3sfWGc7Zdh7T\ni+pQhzqsbkDGV/HO8zi1aJ0mPesChbkgZCI74tqxqtLgFFdUJepfQtEynJ7h7I8ZkfjccYsS3Ohl\nNdLTLxug/y1cWwWXQSU0L5+Z5ElHcoJH1LfwaUMungbZ1U5u/8Nry2jURK8LFHaLT/yRSn4Pg9fw\nuejDkeRSbGy1MMesbWXCO/uT8gOA9JYa99/xwuim3E5zGDUMaJWKg8WBZVyKEpY+KGjBFJOUrtMj\n3rcJNY9d4slEqcn2wDzuKUIcttvsC70XG0awDYSDQz2CYfHkWS5/uSF4ALpgjLcBzwC048jZUueV\nviWS5VudzFvxXLkz+NbWjjiE2B1O4wAGgrcimGJyiRUvU1wynIl9r0Qqr8iOCQSA/p+8qQ+0ZvY0\n8OWok9uq4V9RixaeLSckAEEGfom+KfvqiTv6AE9kw5848t2IU1HTaOCavLmA4A72Vd8XeLeqVW3U\nORuyyYkVjVxZLFIiWhx6jaF1/WT5jDluydog4xcvKVb1cwhxfvI67EmnSWsmK+xxBxA1Sdi7WWnc\ndkJLSWmQspe6eQDylbt/PkPSCYJz6mJ1PlmhwCT+ocHTX24eu0oRM0yobEJ+3BSUeR+k/u097WQl\nwq4+Q2wmmZFNmiX5L9MdI1REqstsyRBeZ8mabMRSV3ztx9WkA0kiru0Z+odw8re63Z1qNv39K66I\nTndTC3lMVLOU7jlDSzpqlgvEx8YKdGwtWR10ffvObGb67Bs39n3fup2O5Qi1hrrMjj0BIo4In58J\n8LGbRJzf7MFALj6nevF6KLhs0HBXaaZal5m62IjWRf2V4Mgj/ZGFih8cnTIM6QHcU/FgUQFPePxJ\nUFklzOMkiUFOiXbKDmaG7rsR9wcJTuZI4OH2Bra0GYY0KpgYcjeZ8INrWeiRUHCuEdkTH4UDhyp5\nkd8qBv1XPDMPgRjQcQXR6su+W3Da+OSeSSDEz7Jqx0ORWQwANUskxJVyC8b+ewdldz/8gCmU3jLn\n2vZKZvfj6KayKRHK7FxWrJokhNjnuKUgWI84ehgXQFuuDHRJfsvH02d5LM9+D71xfG+2+9DfEDEM\nzsiw5dAyaZX1pVpkXQoCukJgESE+6q1hKi1Kcz4k6hy82Eu/uov1cLMo7NeNKQrZHJ6lX//AvLfO\nTUpHyaByz2otzZmpVIAOL5/ycXUC0C07jfBxvL0sQKTQ/J6GtD+DUSWCHZNSFNqTz0Sf0KmVIyEQ\nt4myxo0muliPnbEu6LWT/DYOv7SzJafk1TWWvnEHUrkRmcqohZZisBgk0gIpe9nRRsFcWAwQ0rZJ\nr6DiRpm0z5qDe5QA9XauzWq8kyavTYLromTgMFc3Y0S0m9YSuzqOWbuo1Jb6MGD0y4CrD4Wos/V1\nnsoQwwLEOtso9goiwNi2drd9k2vm2wmYUewf6sazlvghzXheJRjDrXQIclJ+sQx8ho5y2EA8Ic6t\n0rw9KrHa/tlPwPMY8w39fnveTmcgywMtLX7eEIoqb4HpKpm8TqXczal7spNuWhPPe4J8DTU9T3Hv\nZFy6kHLsLwI97vN58c1TNYlnFDCCOmFUkoE97iNuWXejagNdoAKEE8wtPSGH8c8YhdCepyPwtsN0\n6j/dy7KxJmuxggcEYvS/1HBYgQ9IQTgGeHe+RJtjU0abY0fAFTcMKKVkS6VdimguNoiWsWPhDf0T\nSQwbwNsrU+9Wtk+St0Ib+B9D5sjQuAl60CS0arfZtMR1ZGkp2AlwqMlXL4vaFfD6+0cv26jC0RcC\neuQ631uzlivVyMyfaJW2a9/Pad+6aMWDv0fgd0t6wS3X7Vw+GHBo2jfevvFiiEvaY+OWL3LXWfDe\nWqMN0yntP5YqHFz1reseiRFn8klauOW63/7kJQB+WG7swSJKND/JGbeQfPCFMEOrNpHoGrVMfmIr\nViTWD9s/E+x2vSdqInLC12+lG30LYxhcaKGGtog0wRMOFziKHHGkxpgd6cIFalUPDVmH8D4Z0qYw\n0EmoZQBqSKVUt0ZAC6rvQUOtKdJHZHubC4++dutZAVZmAW5vZrIf5aPYUYMG7yyuExnDIBf6o+fO\nUKV4G48uKd6r+L0b/4kVosCyhh8DQ5xPibzLg1awGZHznPhqhCthPUNnuweG0I5j25iasRN4R/se\nvidCKbQjy5M1KyhWL2CFqpN+LIkJ4Bce4uGoB8fJ7Rex/UjHYfduoWEsh7Lz+GgUto4MVUyVg7mk\nsEZFgT0oLlmie4VzzARU+ngPfgaDftJgrNaW92UOpVa1AxvwLiIJCFPT5oNV9UpDfoEBZnmAcFc/\ns72pZNIMZ/6PBd7MnAAE3JJbkIUvr622GwGoBDkHTSTzCuTXdcAmpuGNS6qzrsglL8GIEnq1azaB\nfLcxBq20pyiPaf5WzT4O3YJFPde+jrl5bIi3nQ/xIkrPgyaixO+9g5ws+vTuYlTdwV+aw6Z2Eg4L\nwTCBB92MFE9JDAfYEFsazggJ4c+CFEGftfYuh6XosmP5Fk2EHNRIzIy1GE0uFYNCr0HrKxcDU8Gw\nvwNinbs1W26C6/mfEoCWGhtBEgXvy0fxpOqlczkT3MzWVB1H/3MDHhQhbdjaKdZKrhbyPefTM4mn\nRUwg4H9UKqMMxY8MpelKrUSjY5Rhn0E3IibFJGNmP1Km6DfK6Bz9izzj3SlBM2tuyc/pK8pJPybn\nVY7xZ3bAQA9TCSrYluNQ7Ku7eTeKTnQFanDf+MV6WzCmwj/zQon1Rytur+gV5eyhsYV7rt7bFu7h\nYnzt9cTUCyQWzC0jEWUqDg4dVnDKcpRaT4mZghot5rDxL+LgRbGj6bzvgkMabT8xpkNdlGjJN5n6\np9xZNBlZS/KMEkqIjAI1tdGO29hkLd7oqYF274ELPP5l1CvPBr1u0PgGilPa4LGW2TNx1mBux49h\ndqlUUJe1nIq28DPuRhe/YqGf4IUv+bihFqfjdOoPzEDxijtuPjf71rL2EOjqhbOBOoJS3H6yjqoz\nnAgVC1go6wodCenXIqAIQg78k/lP48fYaqhu4Yaec1dXXV8UyR4Zw2pdUFtBABUjWJbl/a6GZUg6\nFQ6HA06wwYXpfwivS5o95dfQvMcshAMquaE+Uk7t+zpPrFxLnTITOGafA4+vt7+zSiC+Nf0FCxTb\nMD3JDvplk0ljylaXpR0/mYid+K6EEN+gcyb/eY8i6/xTRvPt6GmdZNHeibD65PVZ1rWqBgXTyM3Q\nq3IIpyPJkJzY+dHBPQHcnUE0Yn1Ep7IXmnIy86737wq6h8ed84H8QzVuQtKAjWD0h6Pdq1/8VWKH\nQf6Srovz5Y/B/hEnFO80ED1zrw5kP5jGWIK3lzHgPvOuov0d34iKEWXeDA1xSD1h5lLNSBvtMG/n\nYgutmfLDuIKlg5CgxoWNuDOxK7CQNUvrtTlyRBS4cdzErCBugBmCyvATG+sl0iNPlgaSxHyTegVY\nCF1lMIotYzUCPWG9W2AIfo9xEq4BInp5seaDZlWAueRWsSVfIMuzGl1plry/Zzis6CVGs0QpntlQ\nmXpu0lGftlcasJEbC/EZNjUkOcZvVxNtpZdpyFKxmmejHkcvJmbKiZt61rr/Y0W3No1XLwbUfIhw\nXObmHdAFsLR98O7EhfpIs+e2Ii5vn8lYDmRa1gYK9IFj6Ikcd70mI9RSPhgpQgQn3CW0vX1DAdVv\nHYU9u6ThKMw6jlvFyHneAkBJ/NueXZenXLAhy/NmfEin02PEBq8MvZGes3LvIR6fSlYm2JGR7hcR\nscNtTbmuyI20CfzH3330djQ/hXf+61PlvpLlebaC6yhnnSQHSITI0pUzl9Ao2chkGfLIv4lkarzf\nVvGKA6bR4cLQ7lfMSb3jiAK/QFow/pQOHeoBGpiIJKnyfBfm5svJ35ns4KrF2u9yX68kHNn3GzD3\nHgV/iy4tNWUmkFYbPbbXyobnNbXNQtZOX3Rp8AOG9/Oo2SEnX0DhJ71qKmWpcbp/1BYCRfkXHiqC\neBMAYFNqIsb0UFGb4p3NWy607mqLirPXn3hFmV2MsgJ+JIeBuFIfOEt+uzSoD8KC8tMwqJybtYlH\ncmA7TusUFo2YYZJEMC4hhSPr9Vf3cxQ9FdrWuhoeFLtW3XVvlHvTawERVdqJGI33qy29xmhJ4nz+\n7/wP/l+gt5FG93Ni/8IEm6tB4obo5u0os7Xg7gmEy/6HCVFtfhNkqZyn4LTI6fi3wnIp7HIJWPkw\ndHPnAy7Za9wVoP70xhJbmtieW3CdDLEwW6k9qRmo91m35ph+NUrp6it8IEB3jqZbiqJOrGid/bGt\nDRe3ZwHQlGMqCSrGYYoQkn2elADRgSBi+SEBmIS969msvSUdcffrzFh1zgziOwKYJ7A+zgPAV5wQ\nmRIYCaCueGXcq3+Y3dqX6Xz+q2Urhdjug0VcDF4LTRCKJ/z4BoxHnhPJ0Kg3E/XNFOrxbodTy+V/\nf60jkELut0u9bDLnWv7CI3wgQxfZmbDzWDBBq+CqS6nFL3lJI202FIRh8gHqVyCn6QXFS84Aps6o\nsVsDBM31a9sYV/0IJ2eoJXSJWJpMa7JuEJj1QpCWgKPuFUqL00RmWetqTT4XnPXnNJc2l60XGhY+\nAsHEmLA/EUP7dssvL1l19DmPl1664WI9yN8JwrKMKIQIyQpp1lqKvA/uD8KUtUSf230Tt66HgLB1\n4j+idT++O+33nL1aQTVSDABPdZnV8MsvJ5W0oJhM5T5tvoPxWS/TY8Ok/AcSZOzeVYeGdZxwfQ2Z\nG1fYvu+0B592E4wGHMgZbomABjWALpDg+oDRscuswztBlv34wRiBfRhVq0+xjopYKqaMfRrv7Add\ncCpEx8xtg5/R5o61oOJlc15EqnvaFBqF6W1GW9eHl6mEvxDHkpVbvS0Z/XxySSsBQ8B4OtJjUiJ/\nLgEnTM87J2olOEnHHN/z2It2S/AEBFqRaqCJTXLb/vXe6gKekLNSu4qO/5RJpTms5R0vX/nwTvkl\nEoKqq2fRO4WVPGePAka7NO6i6uTxfoUXzyuckHg1WMvjj2uoW0aucppzCJ18nGBtTTqK9/hidxWo\nZypCiHytpCfX3S+v3W8xlss9vPeb8XoUbPytxfgNsJhLql8YMcldO5pFm0jVazvHJe9caPj65/6a\nmQNi5o5KGRI1YrgN37NHqaYSj3ig9w5K5r1vTpTim68ZUVHS2B70gveIPxtcfJj6MDjza9KDgar4\nL2j+0oCV7N5QCh+3eXAbatOp9GsqEK8NyPLDCMsTtR2UVyQpbKmXt/mmPW4E10r+zzMfJ6dDL2lA\nedhHtsi8mbms9bRX/Cb/S9SduVk3vefqeBSsK/lCxd1Gm+QXnMErrXxnR5MXNN9L8b0mosSL+4s+\nEiiRkZ28NL39wlIq1dpcgq2SObgCPTEHfwEkBROFvzkMC37TQSu9S55uWIs1FuyuXNLdBELb2ESV\ndDD+vw0deBrYhbroR94kQgadZshZY9xcmMpkOPQD4KJj1Pn9KyDfiFj1taahXAewxkfUfjsZLNGY\nj4Ufii6NpDrTkb9+WFudZyVk8IJKiDgggd08rG9vKD9IY3z+RAejotDLYRUnJHNKM5vFuzrQceYI\nE6Tu0LILRbrMcJ9tmkKRGd7VR6llDLUWRXGQFI71zJIuhxIVnSw6K2TdqCyvxxXuhHR6BrdlFIW4\n9RvXFMvEbB2Efao/7VnpBqBp5x2b5m+6iv59/EKuhg4u4Y8peLcZ+Zy2t7kQ4FbI3hmXmVxnqDkx\n/mkTxs0WH7D6PwoVvsKwBYnHonDmK161cFu2IMNNS0kzTM1oX+QFDdm8eCu60xr8VrnPYbIBO+4w\nMkhpp4qJ3tFvNXTiz+bKC9Jhmt6A10MXwDwgHUfcEl/+8zM2LF1wQIFtW71HHyjlTrl8ezgvRdIL\nd/tBKgK6FOeBmfE3j3rqlvTrC7kevvf0QS9YvHUUEBVwG/Y/waNnJizM2KZTUGRpTQrNJ8b+y99j\nepvmiFaaadQMB1pMNQYgYoxSxuEnU15ZhjWo2BAAGL9Zr/ffyHkHoBcxpYlz/iI4IXPrYCGEhdQp\n0AUwN1/o0xWBJJQ4rT1vsZOGbAMTJIKFZr0UmRKDKiYZ/n20BZna0F6r+KyX6lQ5I8WjKWsQb0Ur\nywvSrYTaMyFHYbzNuWm5oEAQ9Xz7DewoFdbX4fReQhA197aZ9TPNlFW/3EONWP9RksdrMk8qILgP\n8fx7K3mt3OICfTfeW2O9P3/ge2LbbShr1cNO7VAR6H09wWhTRwTSxYTIXy/bStPGX5GrfEswk/CF\nU1VpgaTDux7IoLgJ854i6sHqVnUtv9g/yHrtHg1maXOyWelyjK0Obe1cP+98aWZkOSQehCaJ3Pdf\nyDYQXgOINx+M/oSZrRSgRxlWuoagwzJfNmX37nHCfzajxk2lagYcEq8gAOWe6qrQyj1YyYtToghK\n4us7h4un8UaPqBlfdicmryRXwhbFdEKcqhJiCFfpce7jAwWJPjIASAEwvs+2c4dClq1d3impKYP5\nRXndnYPvkhD5HHyrHqc40lGTvcw2HG81JeEuWRVQ29NcOrYxAdZDM3MqajlNFm4KPFJ+Hxkf52F/\n3dKkvR8cy2lpV25ExE13xr1Fe91exh2KVl2IexsicXXmFFg9Vp72h8Xo01Q8Pket6ShJS9tPEh2W\neRtSyo8ZESXtb/eYmlS3r9eud5juW5xJy6oIhnMMpFVJ8l6uxv5FaAiJ1ou0EgV0ZE2aO4sjYXH/\nlaZjJA147M8OsNHMxQN7BRS7WTiZsb/FU/f6R0AEmkkVR/90sKRYYhbs9/Ms8t9vXl9JpWoAVsGx\nm9OAOq3DbfkYT3OO7YuerL1WuO8Hxfa8GjT6+tX+uOYNjyXqE89/Xzuk7nZfPdUu6cuCeOv+fr/I\ncAw+XUXFY9i/EIRBDRjeI1BGw3CRnlBTE7UUmLRDofAmzGNig+mvmR4GTX0Oy5dUisE0269mncb4\nRsxmB9BW7O8baRCKKBDNVWCKwr+gmHtXhVN/Z1t0axbdVnFEWNr39f6T/0oqPp+FourFiT6onjdZ\n20RdryNEaSOdlViXMPAbNvHyEyRNI07lZrTKLi97KNn4Ow8ASDwEYngohaQoWBjBeyzKvTUYKu45\na0yUeuB8zIuY3Yrp8y6+QOoVjbMCKrJleJnf5FnOaLLW/l92IIofSSy1h7xZmhNK/MXcDvk24kRR\nVzmT2+lbkK2YQC/Q964uZCgsHP0l3YSIAdOyHmsDy233o0GjrgL+Tfh2dHh+94MH439aJw4utIjR\nAudhAMZsqLck2OudCxFR9GkgCsLyR9MbzZrDK01gDt94e2qTBEIPYC6QIebeYJCz+bpTA8Qp03ej\nDkBFKXUUn5wrXP8exjyoIpkZ81yKHXpx+nnRQ8t8REAa5ypIf/UOHBalatg6ZlJW/PQs3YKcYXBH\njpMLoQn7CQZpg6FcLCTIh+twsBvnEf82dwzciuzXY5IOPHDNd818QrYS3FGd8m/lytyweVcBWWfq\nKoyDlZvYKNGbIWvieucWEaIL/GpaV0nej6it6vpkx1C9mcdcpxygg8EwU+Q9TqebsjMqdMckx3YK\nPNUJr8iTsrX9migJ75RE6+w9+v/3EtfZC4hW9khYG4ehiG+M5NeYVqzRaSnGNxTsZOb+cuV80hpM\n5kbrEgdq80c5e8zHdush5wXifTorS0vHdVzUercyr8LwVJDJClHoXRguNTqbGzfRO0h3/SGvKfXv\neJAFBsonKZpRfnFNj6KXfSEdlPLoKKr2x0HKnjYHa1O2nFSaZezwMmf4wazBPQ2DvJ9Oiv4B+cSO\nFrAB8wovlgGSC2XpFWY6/J0v8c/0tysxdLZwUzGbu8dXxS/imWXGTMMPQdZnRxoPaipn2kWbYnTF\nnebNrre4I86/E/MFT8Y21DhVJNzRNsoxMZcsN+xeVxgYBgk2vEV6p2llC7JNVbDqz0KsU/V0rsyI\ngQm/Dv5OknCFOuVM+YOoAwiQreo3nHHdWbkeKYS42sw9rv49O4vtL+QtJG7863L8dumpAYndpX/l\nz1Gp8vM4OrhYt6Qn7Rephu5lrDK7nVzVXDshoC1XzCI5b+aWHtB3iy4ktbPhgW1yln18ubd3/WsM\nnWrccDeq78IHQn/pf1Q4C74LUgG1jkid0dyecwvMHbI2ps7Hu6/9Ythx+yi3qypwYayAF9fPpugj\nAGgFBNzwnSFWMu39vT/o0r+mz/sOype0lCGpF/4pkMi3rVRSG4O0wKL012MrdqPUvL8lCYvmJ+E1\nYJYQR1F3oyY8qWklcIMSIXeGynLJrVEkY8EVdyDlEAbLgd+4Ytzbm0tUG2XHH+r9NCOZkk/N67Jq\np9I+cnMfr/AYnJAzABJPqwC9dekyl7KK4usEpnjk4Jst0Fp+pfNlYFododZooqmxfvkKJOurqkwG\n9o37CP20uKhZzJnqTGNL0BC5/ZrvTabulqD19dFpDdg6BGd4vREAAd7Gqp6jxBTvNRQZI20d2BuN\nFBJ+8CziDWG2CsBdoGlI7NdjcgZdBsO7bvCNqHFa0FqWkby7BKVuAVekUAfX6RitgHKugIXhgtL6\nsKnV8v0tfhlaX1xc2uSxePTfYsMtMBEJrEypxsk7y+Exof6AoIyHBZiBvov/hxU7bSHu/nrYNAtZ\nJOYqBNYGMfxaAcOYVe2Vg/UbCHFlV2HIZiAy/gD74Qg8icJ8RjS1AGd7t3Dk0zDERWlinv09DBlM\nOe/RudF8dTfb1DI4g33vSu/OMHm8yscI3GVxGRciorqLX9YRn0ji9noSlSo9389QCFCp9RXOEtub\nh5gnB6vSUDvEZ+umw/C2GQsl7N03vY9FJEOftg3+o1uQb4q3Pcqa+C3kv7Zvxa0HYtc5N34lWXIf\nNnfbCOdcO45XUaPen+411pPcsCybMS7vYf2boFvZ5C/oFH2fxWLeYOEFJuoD9ORHIeOGiqq2yodN\nvkjolfq3C8HR3ywAan1BP+qtapDuBzcoZheHEq//WJnF/kqoQNkhdeaqUGZTcPEd+ZjArKCdPj8F\npfYhhpY4GrlPpFnwlw0oyYNN2yH9Ii4Ym1coemVDC2afnECWviSn4y8fQLYRbVdrdsgyIHaACUNk\nwyoVtTjt/lMYUFOOpEZgnmcn6PwT0vtrvcW/0wDZJFx8FT7Ju3V7FVxSoVhzWr2NgXApggby0G7v\ngaBBC5iIzSJRRAkwOibIhjQGupZxxESlvPAZfpeWXxnyA7YmEHx4EJy7vwEUvvvnwMK4pZ8RTQ5t\n/qgGTww6jntZ9YLCNz/REKPFSVaNFPCQvQzf2PNJdPe9a7OX+C3idY7WlhggbaCeWfsFQFq1n2pI\n1Up2Ju1qCayXN2bD25j0qONpeVV2wMTfA3/0PQvZ7NjulQy45kwFLhjrHKi1SZ3Lo6IsHy1W1lzz\n+T6kjyQDgHKEPxmgbKEePSYFw9m57IRBSB1lVL/lXhgcp3fV8iFAZbUz9vPdCXYkSA0Mnop9p9+W\ngXFiq9fxsGvjlhzNzacvJJ4lNuEZy/8Zl9ywYYRILB/hbw3jB6T+Sl7DBN0JfR623qilI/Erkl4b\nBmEHK10J5v07/+2OoHjVtND30VN83BbYkj0GCA3AG0xNTll7Mqce7tDOC97j4C2DJqkJ7bLpOw/x\nNzvjLevB+tOm5fHydrs1fHRGOLNpTd+tNaXzZJLicRPAQ3PwRCU/KhfUhD/lnwMquRemNah3+9J/\nWbDvDX7y5pZAwtFvTl1Fx9D64CTBMDRLvToJsHMW7TNnmchuf6e0UU3kSMZ7Qh6GBQTbWX3QM6H1\n891oVivzTN/iAvn7S3PCQMqWca/8EwEySxPLhLv/V+g2qU0vWgmRAwgSZGW8qhB+hKiyROe4iovT\nZ7f/ATkdIc/NU7F6uAOSfbTF5HtIKkHTtrRBh/GPODrZync/1Unq6XicDyUoFNdJO0otZpWg0UJr\nIm0baDbtDrMr2nxM3f5NWpkThFB7ogT7J6jP5Uk/W5gA92yUYXraImArkXpJIkzrMVUBcZYjVXAK\nby5IG+0dAnShjrYUMbCDCeWRqd23AQ+Gmib9SjRAvoyzqNSavj1SBCaFi+GWhUlDEzJRjcx8ucq/\n1O95KAytmC/bzLw19wV7dcHvXpYXenZdTj7NIqNvkMdEFQQ3W98i9NwAcYtUOEda+02qLkc78Imt\nEFLSJZ7EKE23BqprZuOH5UTGjH+bdjHnBephoFRnLuwZvF0sPVHLCQz6E11Kl8x67Lg7TMz/JMGy\n0QWWJno+6E233Lt27bt4uZOF4ridnseWnNw42Mojo2ZkS+F63DJcZlmjFOGUVnis87CHis7eVVVd\njVZWDDQ6Zn/wZ/rKAB7Nj8qRVs4g05fCKKzodda4WHnCVF3g3nZA47sdOjb1VGpJCwXqP2YcpkFT\nTAXPnPquxGaaGENiXmKqa5xdskfuw1Y4af7vm1MqI6lcPOF5TxhJ1Qtt53NI+69mG9IdHkpVNj1y\n/G16ztIE1JNeEtmB+BYO0mO2X0dblG9J2YB752FGSgWYV8EnXjP4Sxw5odQw6Wt5LGoLlfylOGcu\ngbhuMJQ7pgb21+gJh/ngTUpwzKK4Hcn0fA1ilriMz/e+CfZFP2IgWlQ15Yt6ECjl/QAX3aAyciLi\n2pcfzoq/Ic7mWuUiwcFzJPte9OngUghbbaNHB8SJIMiopXVGkfr1KtDxrZ0bsWfVaqkM++xgcUOo\nbMQ4UTmjeig/FooIwVWLCwUblGVHyWYAdVeIh3843mflrTKFyQwuXMISN+lQO4i+WEPWHPkml7La\nrjWlBEditPmyzJHe0W207fjznpN/km+Ne2v/R4elmY9pdqL4KL0ubbaOaZpAvlxlAisoaIZVPDq9\nF4oUjfoRR3053AluL3WEd8t1hWG+I5767HWYMG+De6VQRXGb0aE+8M4o/vBinyggTiXrkFS0wkPm\nPSObUf85seJ5x9gm9winqS0b1+5gIKEfpDNZNwf7r9+HUqvigZ8oPVsbEWjjT5fm2TgDLUbBVrT/\n8eMGSj2YLSsfViqir+717cLXHWH06yukH4WjaOXbulc7zkI4iHRX5DuvX2hDlEUCXju37W/7eyVc\nJaxXcJsw02ylBFhVwvLwRDiJUFT4s6tL3oofXqp3SAfLfm36qZJ5jjLjKeUwjot1eGA+NroRHqH0\nmgtjvwYrR5rVyVbWrYwo34eren6W2O7//yte0mey6VJb5UQPVQjQLDyFHJ8zSG/AiRjgwri3tDKG\nrA/0fUOdQGiz+RwQmrOjtDLah0oLdcnKNGdOuYgfRwuMR5kqO88aRVVDccmhnSjkmckLlEa3UbW/\nCCaLOdPOZVG43P03loHDBkump67PWIwSJufgTY2dzbjHQYWFJH4Q+HXVMJAaKwMREVUD4RfgA8lA\ncyJvj/zKyZAJEdF8EP0rk8ZsS+FplatlugSCfQVGudYccNSYpvVKtoiX82LcJs9S/HqsqzCrhkA+\ngDJEbI+8wshtd6KxUXstlXRaPBq/JYp4JESRJqGNH3q0MPWYudy5IU1Ex+Lx/WqW4Cyt6RXnulxh\n7qYgvc/1Li6u6wA2y1x1R9g6qBJDOmN95n40iDkqYuToeiI3oC54fxAOfE94As08xEGHE8kAaOta\no8l+uX4BdtrDoafhBf2VH9N+GTluvEe71ZT3DlKFjbKEsaA/9rj28XJic42JsPn5qkuf7gWNqSA3\nFkaQ68kOF/xwL8BFwUA4I1qpi84bn5o2gVQdLJJzvEHtIQTGmhCc685iDeCUbdbkw1FT3EXdEz7K\nAXzeVmsQTC3MSoefYgbwhcKSCniWMFXMwZCvqu1o0KOypwDjoi5M7wtwWyF1ssuZ/ERb8vFk1TKq\nAckwlJgpVQ3g2JcrjBwdIuAb6y0vpTto8iav0v/pMkDxrkPHa+5edxeg/bR57Dg9M9i6T4QJB6x4\nkkfyZ1w2jFGdyASCxZg+4obC4Xahrh5rvE7rpL/jAt6/JytixqGe85/NdmqycrPD3SpHj4HG73M/\n62NrImyUrHvAP/qdOGD93JyXizrcbws9HXLDfuK8gmZx0E+Q17Eq3ktdG6Im54bdQOOQJT4sbOhj\nwp0PIO/22O0nZVQBFd4Xi2gytLXMo/Jexr/IaEB+IOp3WfOvck/ycksR8uztlg5RC4mpYN3WvnWk\nebkIUPD5cYMCH55xQdzKPFCwCayAb18492wALyccze3xXGlUZkys4O/HRH1NCzgQIfHuZ2894SrB\nXxp20sVF6LGPOCfyBBGEGgpXlUGNgf0lYkUvh1XfD0U/PLpxY6Ms+fNecyGrWQ9Zboy4U7deDa/c\nlDarHQTyrSK7K96Z8gTxVpqWF2ltlrb64uQ9JW0doObxUxumbu3P+d4gfnwFzwxOKVzdeMyxe6ho\nV9G5KUKsBFPZpOaKb5eugVmH2PkBA+lWZFeHWTgOtJYCBZZFv6u9RSZ/ohBhg4bYVotZCYdVwtqa\n/z6XJaRdUKc7E7h7UU0qs4oLqh7OeCHJ9CIFiz6fOTG2ydP3O/+LkIHXj8M07BNjV1vW8hn0jA44\nf2gzojPMkX9n+D0g3kJXmDfyBJzwNG5z9hK2a6xXRgJSRNSGNPNF8Q6IrUJsBaTi5m3lrKedv+4a\n+kNlozrJBXuzvH3eArtARRpnLD4jSt5HAGRSE872rEU1XwbIxMO42s3NXr4zBQu92AdAFd6bfp8H\nb+zjoiUSdpFuOIqfAwt3fxSo6+1wwapPzNlUqHhMfKTiKqOukaeKPDs4E2PP8jHXvWzRb2W6uJ8Q\n59Dysnjtz2acTJCJW5hkHDIlnjwva90WF8hnAXeWRF1JN46CA/Rg0lzvNiHK/A7QSJo1H+8uRIpt\nkR1XM8bh3jWFkHTzVyHdNqPl8PnAjGBM2Z1QeXZJ9UgtO2amnqcO2uhydu4FcnssdGAo19p0K1h9\nDAAuNoaj6+8g5By7RqQpjLssbVgkTyW2vgACzh9kZEaRaGbIVXc5EbiZ5jUniul3T1QSfYmNpXEi\npsmWjHWBONA4r1AG2GokuJkSYdWmkXcnTQrzbNJgVbhz5k2/PbdNRU9yiDX8+YBKuaeJO8r25UBX\nfErFZr5+j2uKwIwBpHVY6ca2PRs93wNUctx+wfT9BmhWV0KOrESlVv5+etnqOZyBBj8AOy3jNLaJ\nMW6hFuSWpjVJiaK2u3Mec+zcJMOqdTpeebSCfSoa0Jv9KeSoeHd8FEP+uA4+6ufZs85JJSTJ6YeE\ndD5VHAFVYTgP7+/ydJa7bnw+leDGzHgOlIsqlASMGbXtRLxobUDu3rtJKrKLvzuusyGTvByu6ANW\nFoi27fW3leSO/k8mEYEYxDviJtlzV2Ew4DCZwlCStk7F60g+hqb8j7JlX/A4sZ7jNvzGf33+oDoI\n51RkUjiaAWH927l0Zax1VnBHHNGY3/aEcP9cn0JNLWqXOPEZaDG2AEViXc4SXglF/zjYRvSsh4jm\nlZDf+6JLapKNFj/U6WOaz/1Q+jnLOy/4jwlbGUui/0pxOwjO53EiIb8+cuRNv6lgncg4kT0vZhYU\nqI3kiVjWCqaTVYo5J0mDy9VOufJyjis/Owf30YbzK8tXhskSMnVGCEYaXysqIegIAPK2MYigbHv4\nYgV5UQNE+eud1015tIvPOBOxwMZFGoZE+m6FcD/lb0pip+7XGQHKbLnWpuM0J0Wgyt2oHHIWuwcE\nZmOznDdt9PUrecb4M0RmzKCR49k+FFBt6PVGZKkTDAMkfCcLL7TnyDp2ufoPjXYl8eFikpZ76AyF\n0O8LbQMUnC0UuD/IV4loxCdPwND+BUaV+xpgcTJLITJX52+GBY3Jx9Hr10udTcpWA4zkVkU56kah\nUtNfcGDqHyPW9c/wdOsB2uNwjN+kH1WUsm53Gl6HdZ240slkKAY9WBm70a2L1U39AWs23CzTZB3W\ncq8nSDk+xg3/2LqE44rdfmqjx4dlr74zmxQFFwnzD3CgIZWuHOT2oguHOTgfrH5gs2jT8m2F3Ksn\na7VXwcQCjVrzGbUr88rB6mXeoiM7Ax1aH9Cg5ObBctrpOejx9vBF5ZDxray1IgUot9VC1om7YIY/\nVdYiLhpe5Id8gygXCI2InUDOPutyjOvW8Fy9xpQOZxxhtV+CO6VFfW5C17Xsl+wBOcjKMGHvDGga\nDDIUGcFGlg/SRkMWBD/INUhFIG+AHsUj8zdIbmx+mIJGl11P9RlN7v06g4LUa+/N8sxmbEpZ4TCV\ndgfWQ+O4OMNl0uOoqVFcbkk5KySct9h8AAiRe1pApC4TpbbFdrV4F01uMNDu9JgLSfjJBAS0Wqsr\nWVP/tTJnBDUHBQREgEwXmUZaPmhI7TTJG3yrXoVrmGoeIH8lJRFxDIAT0j69KTSQzC0DnH/ZluKG\nlQu4BEMiQZpzAf6Ctg01cbuFOx9ZJlV9SQVOt2LtsaxaejPLRRq35SRUoZmqeZvHk6kZnx2JVutr\nb8tHbXcf4jY/xYvfYEFX4HOSvaOWoKQZp62bHLvvIaZSQc8zzZD0dz8sUqUONgaVEppfuM/WMImq\ngwMnGFhZ0DpjWeDdPEdOvxllLjNCBrJoMXk0NoZQ6FGekTHCdpuNxIKZDK8PDSuh3pH4Udn7UHg+\nkCip0T+gk4au+y1JHVcNdnx4ZrQgCc/aEC2T/UxqPRVw30xYhPl9qUGdlYHqX86Nb5nBWaGQOpy2\nFkj66xmYSqUYZThyAMQWkV7q/K1NcRHF9iD3PB4KbAvRJMbfPXRsVwK1sSP7R5nQdxg+YTaUgLKH\nDnbPx89r3MBelsRGrWQJeEa5pk3C9bDfMcDWdA3j6rTLjl8ZtTsrkn+mjWhO/C3F3s6rMY0Q6Rn+\nGUA05HEwcQ+1b3I/p4fhvDdm23QzQyRXUY5EtnP1HeP5gBk/e1C/pGOr2xgZ1Gt5FcbFfx5pvFJ/\nnG1+MqwEwLebNnBzfAgF/bwPd6KiVEFV7PU93PgbX0q8GDHMCYW2pi10p4JVorjoZIwsHTSbH7/h\n0RWSB10CY8WdocmknRsCcU10+X4Epi6ym499noha9lvBByhG+opGOQ9HqG6t/Nw31Y7U4uNj2rN9\nf7556Lp1BLOQWsAVDjQDMgRAKMpP0lfriq2XYSglbcrNybGw0AEXMX6CsFcW8H9NPxXpBk3Grt85\n+m19BUp6TYd/OSiSHyDJee3n0PlTXidCCSqKWx4eIo/SdI0d8MZrW+5914zUD/oLyNPK+gmxbd8d\nmQU2UsCClOF3pUxgccR7Dr0Ux5C6UlZBHhoIRS2aDhZRobZFqzrUhmSxSHr5vamn4txkY9JdG0PH\nntWgNn6Eih5VFDXV5NS/w2Ogc0JDHow08+Dpgy73juN2rBZhn9PVf2oVCw8uV0Wz3NN3GwV21Iuh\nzbdb5gaBvL1+lOE63dPPnCnql8P6/E/RjCAAv0pCb09svITM5W623E7wVXV35pVGDycKtO0rANJC\nQViv0aGls9jehkvD+pNfUKog5rxHFMRxGgeUB3fAI7Ml1jLS6hzuKKqBl9H5kI02FSk0Eqx3sxWO\n35z479p6mI1+CeKNkM6R5jdFKLVcux2jWoWB2T5Ze63CdwAGjTs3QrXiYTcYkJONdHNe/fgs0VGg\n4zzkv7AXoIsHn8K5HqyqoW1X/r/x3Ql1Bc6mXkOmRkfa8iEXsTgSOST82UU4r4lfHCjjCLSi6Sul\nw8E/Aj8Si/TOh2y4xv8OmJmuKbQ0YxIcbZU5UTZyvwtJ8GapX2+DoPhmVfJNjPYFFH5PQvehmwmT\ndgx4rhZxHqkrYO0lOKg1gMR/24M0cGkpIyzMExAGK26SRm2HjKlpXOdwCbft4y3wtruYsLHuNDpv\nrhHUu1Akv93ikJ7v/ghFHVTdo9XGJZVxl+pFQmrNu8vD8mG8C3OQ2TlAVpeqAgCCRYX+Ly35K0a3\nhNoGqO3Ul/DkyXYbdwbctWpTC8zn9EBzNxxwtkLhS7psDn+TWfDlpP7Z2XYi4NVSBxVGgapS8yzY\neSP6L7TD5HKcQnLW3CBtWk4riZzf3thpYF7RXIs2t8iL53IdB2YkikGsMu/BnvPFFJHPF1XzpTf1\n1GAEUNn4rbgp+h9xj0odIY1m7DYoKAwduAZ53fF5TtaY1gklZfRtZdP0qJISM16uWVx0VPaicdJt\n8l9pE5rmK6VJV5bfkzz+2LeNjen2iJLIdYR/EH8nmjzGQin/GKIGlG0XfNknxNRKkiyE6KML0hNL\nRIyzOK34XYuE4ymmnZzgzmS4uNCtg/oB4rw4ZQ9Y06fY6x/M+Aix7Z58rE+icVHft8BMDmNIOKC8\nfkTIA9WfdK8QoPSfZ9P5RQrGQ5YW0d1wRWKqNIYvor5aE0MFS5N5p8rbzdGtjMIOspT1wd8gmJgx\nv6NLOSdPV6P228cpNZ9cnGr+8M7EerdjD8xUTBZO2e897RQUC04/6LIJGqfBFKWsgDGv3kUXOQ+t\n5WOI0tbmSVFDavJJmzz61GPMnT3MKugw6r2yqhX2Sv2A2P6cEsDq3MmgrbdWs4cvzQsPMclNmgA9\n26joYmlJsUz0ID14LLYezi35HMN/8znhYLYkk+iO1Mxt+En78EKuPjQA+XRu64aKTT5CeK+icB4G\nRDq5D4mWKRODlLhEcR4vJWer47kF7ZxiOPFc4h5TvQJwX8bV9+ttvSgdTDv6+7BoqmYGNDM0KrbV\norA4ymoZH2IqZevYvXn6gs1t83upmYS9E5W553qp+pVav6PxGbW4E2DNmFtfbK22PZjn+NOfdOnC\nZRnmbp0KjISOxN1DplSkpppMGGLEvHhS+99+xay1wpK4NXbskGhIBKAGDPQ1M4/JnLB2CLHZfV16\nmYQjktluxwp/AyDDJRPX83Z0DnyMATsm/SpFNKnhxuVcsUbnW0OPH15IYca/VfEJ9ZyQUJv5hS5u\nbua0je7G1Hk2mbj2g6L8ZxialXajFTc5kaTCPPOfUCYGlJd5UCXUSvSmZS7UCzs5qMiMNUzQiWfy\nN4N8YDSPh6mPXPDPwPeSihf59jWss9LgWf0b+r88XS5VsNtxbMWFnfrP2SFOStSXfMK2MSP3KA4p\n9vOyrwrXCe37G+PfSql2gEI5vis13IlRhYKXzyk4Nf9zHg/l5vWsR50JJ1ddhKx0YeL8cbiAv1AT\nlzqGBgZAOkMinsVyO8qDWgByqaptxT2sPOBxUaXx1ZoH6h5A3bjlHG0iM16TAZ1BK09X2pDRiQXP\nEeUGB/kTxxLiyBK3BciO5EwCvaTfsVBowIZyizCoXrKOrNeGzAg/E3tOfvwHDk37f535YZvsMI8F\nwsqHEHicB82TcoXVK0yya49sKe0nkMmLcxa92nKzKrkeVuE02y1f27G8gYA2JKmh34DFLfoAf42c\nFiidrnPcZcHRaiTwb7P0kRZqbZFb0V8OB9iDZV9qQq47ZGq+OY541WpW48zGqvLEAjH5req9LE8J\nt5VJU9g7kzgFlQVS7vH0yKnN6X+gZ/qqVtxLYJl6KtWDQw56F3VSxSnP6BXG5FtOsWc54oVxmYJg\n3dez6qaAnUYYagtXbljgpL06Z5uRChLxCUJc6O2wbS1wxckRA6wlVAPpxalEACteY2ao5goDytN4\nb79hN2WqDvnzQFBvMuZzYZcm/ZMNPXzhEnTWHsD1mqxhemlFhPGocUPxViD0lvgbYusbzoT7Ze9i\nmkasjH7XeUfF4Ov3bAvYlZx2nWoqBXhBHEiR+g0UyegKKyevU19Iw1Iu+2D/7Rmb51mkq6TRezIW\nlmmvYvKf3I/BCjmHxYqsb1fyjUK6p9PgNq/QjqQO25SxCLdV3eKzUCT7txEVJs7W9dJ616IFYBXQ\nWDNaViIKApw73K+44BusnPAYR1vhQEHO3MUjzrGVC+LyRDlR2UxkRbZgVxu7CMBVMJwUy9SMxYNW\nIodQH21No8Hx7ClUbssGWqFfF295RYSe2vKz+QXyC0jV6SrsytjJ/acQyYpkx6KSSendqYJdo1d2\n1QWP6k/nCG3Ot+ON23JWRGrFn7ucT31h8faPpSCebSMDmXJDnTEQDjpvaj6QD7Yu/51JkmHCN4F1\nrE/n7gHwgH31Z1giQVUKZwKRPxPTksPdzyCgJGXSA4aI8uXuOhBfN+xZr3tTwvSLCYLRWtQSn+x3\nCl1pvQ6nTXTBgxz79p7m8c40xp7aSa3b0hhfn+Gl8xdW4pcgL0loYtU1le2clNuGgmPG179i2/uu\nClQMjD4GD6BcbDzDFN/XpL1dZYglqIbXIawigcKxcFBYDTmsRXJEFTRn6SXwjrYFNLgfC/yUdNkU\nEYEtBi/0eKX3Wa8Lh9XHiXDmlQd7wsWBEiSYEEkjTTNzhon7XJN6AAY43NjalbBLcqmX5l1i/8b5\n1w+e5bzSmX0WHcyWCoThx7WABeHWdLytMuWx/fvk0uGexf1ytVbX9XaF3vziR0SYJ0QUSF7jYoUC\npqmOwDSKrcR995m9qI2IAuYp2yTCG7PvKdn4FkjrjlHuD9ycXdYWHUVR/WgZToqeinwTdeRGLCp0\nWuxVRjzkfFKvyPROUMnvRny09a25/wTETVo+crnXSjILyUWQib7habPmyEoQLS19e32CrXE3rbLW\nmoj3lJNj9vOsZDJkdcnDb7iZ0+KA8CeLMfm6G6sGBq0GFq7IcP+cwM3wzB3YrmjNQBsYzrQJMsDs\nCaaE+TlVAR3KmrEXssfPInpTbu70ZuWlwYbPGSa5utwno+AOs891LYQKTAKwcpio20sbSEnXknOA\nihNc/KO6b2ODy8dHQYe2tWc3+jmqozOQsNHtNTRd+vAt+2Nh7Q6+C1vTppWc02x703ZDLaYZiWd+\nku3ASFwZm+YG3ac0DnYfXoAVojQ00ZeY/QHoBaEJFYnVEuoergfIF/vA+2AYa9g66cZZ0uF7ITfp\nNDFK/Rq90btOenrD4sP7dYLLMFOonJlC7hAkJF9bviXGYR4w95entPxMv+oPFhKr/83KezLPclOO\na9drF25tp+Y2LRZwB4owHe3DFce+DT8VZbySR+mqQqShnb7WtuAyRLahPs6DDEEQmS8EK8jyPSXb\n8YOSBnxG7XuKnw8Lv56v+NONoGQwsgDuF5jfXRuKCu/9PeSRVSWqIx6tIjsBWQON7/sMrqDUXhTU\nP/z5b3GKlIrmN9wVF32x3RLsZ0xs+PeCpcnW4neNVzSi8e54CQQEII6q8yun0SBH+mDXxdw8+jCp\nI/hiG7Z+NuoPlKjvPFqWF8yqddQQ7LmB/oQFkrAYwS7cONCc+g+9R888UG/VJjYRWROlwD/VsMkX\noBwb54pBv2OMxZVFhN9946P32mF3Gm33ssSRTTlY/TPGveeiqD1FtepBHnRIQ+XAN2eP5cd/+Rn1\n/awP0x8ME09OdUhn0XGgIksd+AziSrA1GkKiikudfGzQvqj2a1uwfOseQosoXcGOIAY4V+krSmPk\nOvZXdc4/dvSxXfv7EOe/i5sAw2LCbVgprkmeemR7K/H9kwesUv1xAyy04Ng981gTa2Pw6XgyzlR+\nWHKApQc/FJa91wXVrNLOKiLV2ttSwXtyROjDdVQx0XuxHzTJudCumppXwifst0D7pJa1KWx9iUvU\n//CF+VLQsubHA0051h4+dPLg9073kxolsyJbdjOm+kZXvKWtLN92wQ3qa4qmHE/kXtW02XKXPm+t\nDOXJIMUAp/C1tRbhCfg6hhFK4lrKvnH3jVpmKGMOi3rELj6989e9xj9HzNC0+TJ/IjS5Liw2g17l\nFOnV5xIwpUwN5tJ/cf5nzO3bmA67ENfoKBK9XHULdImTpY60ZQWh0v6dyt+zRMcMRMbBqkcxXjOh\nd2drqdtPIcshuCuIYmcAI+ODGXCFtC+tjb+q2EE7wlCZiaaDYdgVibg5yenqh5ZR7BlG8+dnaZtd\nVVqTIdwYYFgSl21aEa0TIEX7TEA5xN4H7Bma9vYgAHiOS/YacTwQklxMDXN0FXGSK44neOurRYmJ\nlexE8qaugJ4Qo/MbKfF85yXvxrKo5cmFcI73AiJm+04vQkS//MNZgqJaCj18foDt5A131OSCS+yP\ns+vMgqKRoTQXCguDOCbv7oOD5AL6YcJRTZqLSTZ2Ep7t3hxYs5wtOf5II9zef7NtL2AU8566AwcN\nBv1X5NmA+QBq6A8+AaNuk3Sk+eWNYR4r6FJbLmj7dEPVZAJFLN5Ldrsx+FDDTwgnGpIE4vgeZBrl\ndDDZ/OZ1tIflMukpwYpuLm95chxPPMgHhcr2TY0T44peWcWCX9mf/oHfU0EIaQ1trQTpWZ9UgOgv\nJ+BqUh2kD/ZY8xY3ZxtRl5cUS+d/BQ/dGNcHVXfWGpblRGcHuDXQUSgQIQ5fs96PCpEWeQrBEqce\n835ejJOjwckfqKguukrarnK9MQTALwzxwrF7qSEJOdL2Kd6E1Sj25F2frPDw775D4TTf+QnkzkB8\nuwLul0inUosRQWaapvR1jQJOzvysUAvfCRA9dgbKem2n2Ji7r9ZbpYkt5b9BoIDb6VrY9FuhpnFG\n+N7rkUrR/VFKVZmWTzc5BewyXbTa+SblY7FtvUZ7iH9BvCq8nY+IxjG3WGx/Vndxy1dMnFBeIhHs\nfpRufL4fC+GfMvJBxJxoEyfbGW5BtFbo+uqfUq64kNUw4oVli8A5tLaYd9y3/LdfbZn1zL1kixuX\nJsBhRYwWgGKxpbo88x+3FaGovmRLQ0uiAvf+lzDVuI17RFLwvbgS4MeNpGqr0iK43vohOKiALC7a\nmiUGzxMP9+r5XbhAx9Nah3riZW2wpLIp2GPuOBy2GtwBbNKd0w1BN8jfH6p50YdFZfksroMqArR8\nd2b/qG8VwPyVt1gfdDrNtiGzZo/oexOiCXWDx42LQ6OtrcjQUGL7Eyh6DV7+/QEX5gFJ2McUflPl\nHbyv6Rf4x8c5wO1QsEFWaLGTxOr6fTvfFZ+A4OZhmC2IzniHjL6OJMykDxbrGxcfumgzokHmy6Bj\ndqfZBV+yYdJaqSjRjg8TQS5xL+31qweX9jy5XPRrZjj/nPO7WCfrALdAkZCRLbM/lB3CYp7snq/u\n2FQPUJKzck84Q6brIc0yyHU7cZirWPuCCJm902jQfF1Z4eeNBniVJqMxGxD02fyvBco+zDRR7wg5\nMwKvzf9KCPLCMRDMCwvw1TZ1SLv0aWNJ9yJp2MIxp6PpsUIjg84Ne1nZTjRC667gWR8RdM1HSMvp\nR/7CjeSVYqHKN6klkOZrtYFEWmP8tS49pJMupw6rrUtfubwgMJvsVlsb7zVRcFr93LNl1H0e/645\nyXQRxWG2+4wTzpf1vlhQHumG9ELNNRScKfUtMXWH8NLo0b9JOz4DX0BYTMiPXTTSr+rVInFhH9vt\nyrLIir/KW633WHZm9HwHfVrNspsymo0wtIEabYHgDykp9IqD+mncW5WQosOpZ9c4vkofCTg+awnc\n9g9fe6dakktrevhHyNh1sB5eGeg5gfeQHNFELghRHiRSSuuaP70GqMPN6n+FgH2kSfiBn7WOfo1Z\nOg8ypRlaIWlDvEQozS+0hlB5Dt5B4dgvD3VHzllJayJgpCBBigpy4EUqYp/wW8UAINtpVtpmvxTh\nrj3DAKLlaTDm4rtplrM/QG2R2gSl3DkGIKa+oslquw9wiJUDsStTuWkX/Csqg1hF7yHpGi0gjWgp\nes0ZFOARHpaTv1eNyijqt/5kL3mS/Uyu+Xf7nqYg2sW93lU4MRunY4E3x7gVjVlnDqrH38RsgVbf\n/bAB53riBSBEVwvrIhNCLJf2YSx0dQnknNj9TrGqG7wg3siYtKyw7dITk+j1adr1yT4WF3JPMXfc\nCGCzd99DwEMf8GebDHPdamt+dEcMNraG0LlM0/vyu1DcPydE79HjWORYiwyjETFYxHgP0ieLY9/7\nbI9J0zAIV4h/SBn2tQvbZPMzROTS8cHMtYmGYIAW/DOx4F6lPzxBsQxGcsi5bomkSw3WG54ymtra\nZtfJokEersbLJNwoqItcy93giFl9IAtCELZl3/U1XZHZg9mEYTGHi+vBdcGOqdpQIlvRX9p1F2Ip\nTS+2As10HdT+ixcdc0Zilu3zsL1nC7aL+qOP83pBQo8WlmXPB7g/p+8+Whhe+6M313uinCh+X2R4\ntLcLDG5oPorL6DrBeWkOCRhppgNms0upxAws0c4vpFv1G5Yi3kS8D9QjDa9PxB7Zy5XIImLr5qPc\n+8UsRuj/sjnk1nk8FLFkVBuK8anycdHLyZlXSBldoluzkSexK2ccVW+p7pHqcaL2LdwCThrtKHPA\nTToUHml18jm/0AFR4DlPjn0Ay83jr2CjaCJg88QoYmejDgsmSwS+qrzdyenn92N8YNQwXHnOxvDI\nEX8NEjgGwejNCX+F6UDu4ooXRWCHV/db1LUmOJi3tZ6pHl5T7C3UGZrLvvGq4rqTC8dnXu7QElEl\ndXB0Jfvj1WkEZwRcfDqnNndXXvdb0+eXayHK5eaj4SRInIPnJRdtP+2MMCMg3IZRDGKyyi3qm+9q\nnUkNNue5OIeLn4DECovWjKy41O8/ssjasnXEaC8b175d2zW1YJudXn9amXWCbX9Ud/bmb6nBE4Mg\npCO8ysuApFyU/RpvYgZgCQjbJfU71XAZCVgt05sizCXay1VKVROFnEp4uljDGbKOjbHbH3gaC7I0\nRWZMB6dkGm/ZxIpiU/6RKB01qIJZr0erZoOeIK42YBb9tyTfgSvQD52iJKevHGEhXK2s8Z8x9dqV\ngbuqj/yvDnIYAOXW6DSyphyGUq3aKIziCwwukrCtLswyddA6M/CtafF8B4FN1BuIfx/+G0b6ngwm\nlBCcR9txsFqfBFL7baf7JUUA5EOboWh/ow+ujMJ8iFpfInczwga6nLqBexAosYjMKIre1kpSkuk7\nmegLJWwe2EgVBEDQ+FmrZqOwYXmJns+jqYMgk1QuPZ8jdmeZuiWEaoAqPj/BjdTnewI/MRkRQsdY\neMANESKrmSRpTRosqItt/o5xjdCDEWk8hsvMP6Bj6VQ/1SArS5QfXG+Q/Y8E1dB16ZwIFCvFp58f\nsaGN0k88w2vMwShz0YC4qI+VDEaGMPvj1ETiDId9F+Tk1HacHTQy+l8YVIKzpadWyDJUEaOHUqvc\nV/kktcLl6/A+rZacuEmYxtPG0SaB0+bzx7ulrKNeyDQpLQTxgW8cxwbZvxcx783MMKW/oQTKfMgy\naoO2bwD69EWFTjHW80RXlrGm0cI2zi5rXy1U+NuljLwFfXu458eZWWzbfGKiHRvM2eprcivaE45u\nhe9tUrWmJPNjmytP9CxzArvdMbGunwZGzfOtNt0YrijI9OLSvrDbl6x88Sqqw4GQJVKTm4/q7xh6\n8ibl/9i80mHDxOj91I3UiCwqkZg5G5zVN/4axYNihActqP41F5lLkw+hWR5kQsFBAFQHJT2SOVLa\nLUPhs1boCE42XK6Gfj/Tx2j9Yd44Qx+XdDEVSyZWuxsFSH1i8yN1NUw4ChRYkNerHAZBEqCnNdYK\nw32X9be7UtGPqWm+3kydmuOe71OrhlKu2HeBilBviVP0AYa/zkoUuFj3s8Hgt6bSKoet6LloUUgJ\nqI8wIbgurQBUaNaxNnZ6GxVO9KTx4uKjRMmSU2XP0Twz4ImN3C6y+UBZG4qhw9TRUwf76N31aXXX\nez8PQ3sgpQkm/gt0naEV3+9SFysH1BRKSrz+TOIbPy2QJV7qnWWK5k2FNjHhbbtb+AleTOtfBoLe\nEc51YElVxUKld/cOOHHazFVO/nT4EqFRiIn799Zn9pqxR1xVuX13gQXEHlVlh3GnV30FjahAXr2x\nMOWxch6dz3IBXnmtnX2n7mx1OQ4jT31f/LAhehnnyv7TpK59ZVYFQh9c8I98SXNxo7wb5b3nIqNF\nMjBSWnwLaerX6UcJ5wPGVssWMw3zOtuQjt5MxS/pTaI1S1jL6dio5/xyaY6deEFJ9UwS/nOXgjhU\n6NIeYRg1kI4nSBmdu5f8sxS7Qp/N86BSrRb18TCrGZco50Sw9wTR/ACbl/Ch93aVY2XnhtEYIFWe\nY3nQhAncBNIhNdS6reDaGsxj1G5BA0HDk9YheJUOGCxMmUG2sRwD7LpOjbl+q9LupIxRmUdvqvYD\nJKntjzxXKsvtro8LogYiYb9jU7/5yiFQpM4uCDTXQBl+n36tHKaSLrOH/W0xGbxcPK/0m/f2h/bI\nCbQ4FdopFGjDlNksSv1Y4F/TlRRs5+ychHtOC6UcY+BgwNJp2Gat9d0aT1oXlCfNnY04bSqAGmNj\n8DZTRVeCVeUzmHHqyl1m/pWKL96Gqk5EI9JtPjXn1wuNhHJ9ekiv1uy4uQ1o33Vi+ASxHhqBazSH\nFQOgKrrK465oVwU9iZk8Zpt0a8UYjBp+CDjOP5tFwWpi0nRehaSdfluPmr1s3qcre4Z1dlyuV0jf\nXfgz5hiEtEcttscDae5WKJL6W/0vYIFH2/vsm8OoD4RQPSJNN34jUFlwqzZEPLtc/ZeiJIqzUumu\nt64Yslx5F4I99PgpeRYFCw8dD3CtgpNJKeBoTpReAT7O0ob0NK+MEpspLAce7CGA4RRjowNNGMZj\nbwf+qjEbROMQm/19sdfd4eoWtFMcBEmUDcIwy3zadlH98AjuPeKJtAWtfbfzFWDM9Mcdeew5V37J\ndf1g2fkmvBh5dgTvCXMr2x0NWwFcd5imxh94VvATHfw7O39QEdBXFfPj3ffEeqTAgbel0UvfSnjU\njZftrWynlJu4kqQSU10JfnORHe4h72DiU/HtIjRMysSqF593SJ5BRQkc3ByixiPExTfE9XghBavi\nhedetJextNsM2o0MfQZ7M2NMv/CWFgI6DP1xZ2Fio8L5dpeAqYORS+WFgznPUvW4j8x9179cliRC\nH8FawTKxlGrZ/zMnEQqOo2fMkXd8byn8oV2qv/l1HDNFJXxAzGydp4ep9xXaGpaRCjqYJGv35KRC\ntxLJsY10Td+DHMNcdv6zJUtkWJdetQUQjsIqxJgUh2NTibilW7zwlph+ltuOQiZj7dhGo2NwpRxj\npRSOiTAthj8O3Oox5lTjkWsZQOJYZhsuLWdQf9lHcs0ZUsj5S9+2RM6U0rewlBsYMkgeEIO9WrvZ\nnFWjGBlhlIAI6hW6Ek754Y1NwfwcihhMlbFjezjsdA7r0d57sHy10dnyKk2dKzP4lsXx4oFswI31\nMlJeO4e+OQuXMjC2s9QtD99djW+BQN8vS2hss2jXp0RUFN2ALmqlKUlQY7F8Qk7GA8W8xEdMSRfC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CgNeDKXAqsyHlBqiikZBELrTLQziUuO2Ozlm5IjiDh2U1AcE58FeYpCUcAKk7tuudNf4kA\n+4IZMoylovZMIy1uk6gDeTs8t7ZT+qbKAYqvQHGc680oqpHHqBGMlkn6SvYbCvdeT57YiL8qgbua\nHHRqgt76f9I6m2gEbzKXyq73F1XA7iNkIQH6wvVGab9k5vFK6t3VknynPia/XwHedkmztqfsJPcL\ndpmsfLCWWjJB71zBzndOPEH4gQlmdtbPTUCG907wykBW6mbI2D6F8RXBFxLFiTe3lLlK9f6JqaKS\n6P5Urf4pShGjQxePyekutNDkOXiqBWkNmqlwZ0Mf+998Ey554Ts5BpfAZKA3iTDnLqa1WjM8MdFu\nz5cnBm2QmsWFiDw07bde4lWuor/GigLLSGoi61c1W9VUUTxsmRW3Nm9hedl/LMIi+IVd3Ie5yuhm\njFTZ6GPtxceQZ0a4n/9zmY1LfzOKboZDW8/yeLpK37K4KdBjNJqUeWPNEgbkAwu3B6nDVdpVe58R\nyE2+HOOoxDbkIulCG/2Z/niLLNiqicjDej6x19gTcxFfvW+AKN3OywTja1dzXhKcg8TxzQWMPch1\n7hIDvB5NzUnEvJPUkHECOzjp3pErBKiXve85ZxpQKaT3uOCuv48BGPUNsb4Lfbil/ZB2YfZA375g\nBWHRJSLDuy+pUEyTq8jZoZFHXN7uX9th5cbBFjtERzEP1e47KFVu+y2grd0uT/p3aA/Dnc1rAVN3\n0OUl/SCM2fRrCgXsZVeNO9TXtrL2agt1/h3Lf+NdAkcZvn9s+8p2KQQWKc+XZxkefaWM9yc/9fsX\nPY1bSFbAWYgAawdP8Rju5Hw/OWV8Sbv9vq7xEY9BvZleZMYuNtFgj/xGBc+xuvt2uXAyHW8FfkIM\n8cL8AdK9g14QyRhkyT0yYQinZHzS1u8UeYNIafkE9LsetGUZn6zTUy/AAQpdOJF5R9QumyGkPJIG\nDLlbHC3SGKKie2/q6GjryZedQrBwkwtDiAxTW0Qz0ZfWnHQKZUXchgOf2KSxyoc9cL5NvBSM6pDT\nBAvpvpDR9IQrbp1Me+korQHewv8IU/iJGQDmW9irBUgAsfKFL10de5y0FcL4nlC33hPYvgoiE8RU\n7OI7bRcSswtiJb7UhlyHXhX/Qq1xYGb13RquMH7/TEr+w0tdRTXngTK1PlKg/fw+yvbbbz84vm14\n69gZb0aJzCbyTfgznfo6NSyt+Yc89ItF7q9pqhZCgcdoPXmBq3Yy9NMPtoxsUH6kOSfBF8AAXDx9\nadNlsmO5H/J6vjfLVMwnD8RGzKg6O36A/qO8CTAXdFBWJK1mHmV7AHkQWbWjtI+29Y8Cjcm5TMCZ\nVcGqgrTLwebwYR99+75or4EP+AEvUyYflRqH7zmkV397XZfJrtGjYDfVNOaw6Fwwl0BUaCVklg+U\n5ujWXPqT+WCdWww8BHlzRx7C/fcE8QYr6jkhv8ZWaZVWeR7m0BETZyFFtYpPQbknoTrZ5yogazvW\nHlomBpRuB+kPMi3hXD9VvYxmmzlMPKDSqnD8oEc+v2HUEWT0UgCJFxQMm9iGggPf3YHN9D0jFjsl\nmgTwaen8m0tCFvDheznqa5R4IJ6bRUvo2XU9OK9xcgDzQcHU2WgdEott1qQL2QD9Xhj4zN09paCL\nT/tIIUjT3V9B5xBRw1DMZULj460qadkGntA2s4bdSew3xEhDt1THe7ANelYoDzMrlueUPA5ybCN9\nj9ihdm9lEllXxLg3gyWzGmSmuv3HEWoNkOVomnTHzZ3J3QNTFDOMQOkjTsUcMNbO06kf3AfMG0np\nYy1LjpLqweinJgeFCZihIUKgUh+mM5q83dzxHzSQOkbp4qgEnX8XTdz8z9rDrqNF5Lis+cg/r2ky\n1v5mr4jN6tquOWltmsh6mJqtbEflof2B82KIIYqy+oo3T5rJ8j7yS3pspqLojUPsoDdI63Y38pnl\n/hAd0oP2aCtDsnE/pfTIXiWPGhPniqLkuv7cBGBWXYznkXvzGpkOqxyxhWAgwn279Vl4NoWBY9nG\nP+D7yenxJFKzsvPZCtA18L/DbNpESKFNX/zlfxsNo1TD+3r7PZTSdNqrXwlbhXO/m/+5mT+w5GDX\nG0lC5guj/TIRf87wZd8GuzTYgQ1MRFizqy6t3AMudVJ2vnbE2fTM/qu7afzJMvpQ6f4Q2V05ln8/\n7q3U9uBhrpQvPrvVqap3SfhElGbEOS4idqH+lE2LwPXQ3rvBZaWDG/ZqR0WAPWNNl6uprwIj8V9F\n/nbYOcr9WtpeB5Z0NEKE1Wdxf71w7Ne79WOVGcm8UQCtaI9HHu+ky22iO7zNt7mGTopdMTplddm0\nXuIyP7Cf2kKXQqso4w68N66MJgEeKS8ICKONtQ2HfqETdm23OPCItND6bDztQXOM215iJj/463Sd\nYBeMiN1aY1cnhgrab2oVuroETi3DwUIewB0lELB61LHLjpKT1uFQeSRnVjZ44sLqvXljLc7VhQ9O\nkM67M+SRbxF7gdwjNVUCJtaTxVM6Vad93zRoRBBi48nRC4GogHXTVFX+P6PK4lESKZ3QFQVE5E2X\nZJPoqgI8udlaVeBK1CyOphB54UqTOMDo6yXhK3f1Oo0Xb7Z6EvQYSu1ZmiGlj/VxnNju6GIffPbU\noj36vPOyJjH8eHw5Lsq+wMg9hiBym/bv+XrGLRz5gPQOhulovqdHuA3VfuOkQpBXA7ZwWqE0XEHA\nHlX4GYw2s6WZRP35U8njSsTSSEzeHuQwdhGLNBLKiGCMrt1OGn5KvLQhhz3uFmvCvtO0YQgr4gRv\n/vmpo6suAL/ASzgOaEPhiVzMmPkrWYzIBE3QRLskFPR7umUQrpLgsHbonxi24nKArAZlLqvR8zG5\nMJW+VCRb5DvU/3epE0IoFGxaMXInK3yTSqfouU25pcD7UPznWiUd+Z3ZbKcsRUDqqTFSWVEIdDtj\ne1soBVA1ECD1iz6+bTpNY5Oh1fX651YQ9lvHKncJ2+dN9V+hRK0ngC8rt429CK7a2Idalpmi3JWg\nDc+d/z1QrUiknXJdMXdblP5a2mivNqIY+P9N58n+bZLVRKzRPI5fH+TaiZ5jTqJPrlNeN6D2tTa1\ngbHLS1Bq9dYuOLXi9TsbmXBgJBQwwPEWK5yG6KdPu9G2WhBizqyKJONkO+nGznTqzepavVi1EtT2\nDSy2ZlkxvRjUjhs6nkJ8oFotJICNfcBze5Rsg/eui9K9LduHWu4KMEEnfS6sgxuooXB2mSH26zwV\nij9uuzBYnF5pUMZP5ZIHwUnjANwa5J9TVpzTTsyHD+lSA1anl0ixbWrZqBWojDnzT+iwlGIxFd5a\nCr7uEUoz7+tyA+l+rF2lKvvxzfe+zdYMMBvqsNDGdYqNAW9FkmJhCLqy/xwgk+n2wVFwkP5bs5+I\n3CWz708qj0Xl3IUamaiej1IyWbCM3/65rfAs1jw/SeAXlA5GLuL0OQre+5ukvItsHTy5WCsZy25m\nIlzQgA+g35NVaLX8dpPHhdDcFPt1hGXhP7Yr6joKGvJFCTAqQSq1Ept7/OihaNf5XXI4dZlwggzW\n2O6+s9dtuhAiKtqIJ4ijww+apXGJirR6xUAhOeSg0/dL5FZGPXCUkxIV/mjEPUtP8xHtTf+8DOkY\nPWXBtnx2mGH1KZHfCfdcUVSPmQCAIA9DeWX3Q/v0IL1BHCVTaOsQ0i772YTDjXu0N/Va45Up12M2\npPcrdVHbahLP7O39ql/r6SNm08f+RwI7JPRtDX6X7V9G6+hu0iepMxsxBHk/8XaLUie4D6F8Tp66\n6wGBZoUWXHhVYxe1w2xSgRvnaXfLtyfhQlgn8KmHdgk8ibc3u4wSRbVtHfjrajovxVnePPubf0sR\nGGHlwLMSkklmrNGL+lSFGUi1thX7/vm25FpgBAf+b4KILInLLMnv3/NiX04A6G6zgU8xudOjKqA4\nQagbl+lgpX1lp/P67vogTffKrn8q3i1bhVvE/95/IJpHNxGD/YefOIJie6yvd4g4+QI0Msv2w6Cd\nidnVFRjhjKzWFPITgzw+/cK7BbMWwZa8ZVr/R0Ea4sWBVTZPvhPjDIMDuVTtZ/BIXrN3ZvcoZLIt\nuEf9nP+YPyFSF9h0+9M0/nnp9F71JHyX7jYpqOOfRpiL3Nxuokq2bunZore8JzX0eTcdJscbMtrD\nxCeKBmGQnzKQ6UiCUFkKvuf94g0f+IGcEZumf//3NSJuBvPpTbwMJSm+sY9G//ySSjk7pQqkuR8b\nMd1KFK517XUMgD7SMRegkJwaEV+w81z7aG1qIch/hQCgQbYqsyjvh5nQId8PgIl3hj4GB2InI72Y\nUAhpGWuaDLA6TX7OKs162hqSHhiyjirChFnxXjvJ+txbFF2Fcvd8Lle4qgP9HzwonfxA4tbzBytC\nLJ8EbIpgGoQE0uuPrT7LQg5Ul5yacTYpsvgQiEs6/+lSlLDAjEpcyOT1BIsadKqhJF6LUpao/Yqd\n8nYhQPOfQ9M4yxojCmXWRMhypMMDagM5T9sv6qzL6qgJ4635y7SHWV5n1z+x2GMB2W7SBYChf9Cg\naynz2TV6w7UesU0HBZfyRI8NLkyMS7ihpqyH1jAn2v1bX9SC3mKHK1xiPPb7MyxWS2sPaIZTX3dn\nLSFpuj14rJiJBIzNUKOQfgxBQxFfjiC+nqamVkFll9Me0K3Pzx4nWb15saHV2Agy2l4DayCQQSf/\ngFu+g2qlmJp4rljeZnvFcfEJsOYyCCSq72bieaiG+5CDM8FK4XKb+yzUHKzInHArOoYBwfcoqN49\nPkjVl2JDlQyLuLK8pcfOC8FrGunZkBIccptg7+MMvM6q5pSPMdCQzLJdSw9VJocDG6zh3Z5jUJwH\nJq6pFgVUxL4mHQb/BSlbgvs7NHbdBWKz8rrRA4eVc1kv0JgHRrOMv+3zEIoIiDWuTT3t+yN96Iyu\npS+PKCweGUCAk35o3tdplD/UZzdXhXqDMyDWXStqKnsQIolGFL1H7y7QpISzFxs688S5FmO1T2+D\nM5ktv/9S3iEiq/1qs2t/zEaENLUrc7DR/jifXMCRgj63g3PpLxVEDTtL/3O4f3ScoHrkebcb9I7i\nNaMRY216C8UOoH2/Ce4vGbBnHlqnvcEceN9HJrjnPVfBNQgn3cqClEzhriztssglsio529EdYhvp\nAI3zSbuJdREq0mii65Ch+MFopk7xMl0FkZtWXazGh5EG8XUCqTTwL68iZQBJNXNwpWsMwOjvvVMZ\ncvUCwskXIgeBTeVeZn9bFKUZ2F3GnOTZ5jC7ctowLND5yXfbzx9O0liZCTrjtu53iTdFHajEz/b4\nl8p2KTpbmC2CvZInR7lx9ZYk2MP7OjxSovdxxXIwpgMYWg1YKAiEIew1eILGHH9xYot4oEMFno35\nqX/JcF2ps8iJNJ5XQ1YzV7SduBeTCx/Yb2d4VHhNd6lfGJ/VPyBamni0Pp9q2Dj928OQezu1XIGJ\nvaLVosBVp1vLOs0cqntR2L8Ok3H6FZqtFm8mugOIB7ULCucN5ryxyJlP6Mrpe7ya1q8lqOGtAwth\nG/Dy3taw/Yy5HG6TB2aoRw2kQ4Btsq5j++25XkrGXxx5TvMK5qSWyxOU2HSAXZZI0Cn+jichK5fs\nZG/1nqyorqf8a3ei98nqpjNgoHVp13lYVrpLCWjOaECv0Opzj1i6EBPMbhdUBAh9TkIuZZlMVuR3\nRh3hDvelRcMCee0tJn0NB1Wo0yrT1Hnz8diHo+bDuao4G00VU82hBM5EkCU6X58wSPK5Y39d0nUO\nHn4Exdiza1nnBgC5bhX9sWMeuT1jWxW1lo98Wgg9WCuJU11VR+TlEeM+FKOVQRTr1Pz+sZNQxv7G\n5d93rqlCR8T4JnKkrFpEu0vUDzqHKU9hKuIJpFddQkwSB2xvH1Ts23XKgRXCs0PBmPhGZ9fSHQke\n6HQRh6E/R+JlmU00vuzxXNYgXqd9Ima7gLVPBiuGcv2c6w8sz9lOe0reW1OoxgvI4MANQ1k5Qp3c\n8cIsxgheBdrhp5iBVRipALi64MIShWbP5ZPoC0/pKzYVhS1qbqeAYfngLEsaGyl1GbQiAKOpwRlF\nIj8fVr9LS0n286kxnV9KaZo35NiXSH+DeeJHugfPaKqRPArvCi51KSMF8TRpImRrY5g12Q77sDQy\nuaSsxVmQ+gC+MrGhQk+Ferh4zGEzjSHtNC5ofHgArM1c+JvCB4xiTF9PDKwaSAZ1gS7diLNW1Bae\njLSh/zH9yp2jy6upD1uDSCyY4UH6LJchwsOuMFwcaLN+CgxYvly0DIo8bjbzFwfBkFpGByBmPOSw\nX+53dM1x29EpbpVG9DnxzhIEiTGtwhrwJbrLXT43mpBbRKdfi36hOpAPxzwxGmM2XQpL58RRNhcj\n8J3y+kVQZQrtEp/v5MaE00o051ZKzTsCgatNlb1+h7mQ/c7C4QiCOxC33qTJun7RX8BJo39ZrxTW\nYDNppnA5iD22u5ou7Y2jTNRktD7kCCFgu+pWxFz2NCOwx0LWL/xwthI4uWgbfvNB2k/63fFlHEaj\nE/lOWNFbj23yjG4E8gRNJy714aUef4Tuh7kJF8XPER30VGXe3k6uKrLNYFb/CjramGTQtoZqG1Wi\nNtwN4PiXY4YZV/V7DJw5tBEQC+OFyKd8PvCYSCZXox/xteCAfB1CGiTkBdDPfuo95ppWrd5sYro4\n+m/uYlT5oiDyS4hcdq8NZrPRJ7t3f6AEZyKJHp8ZmpqJr35SNV0Axo3GFIGOQMDxaw2HBiCFz8ay\n0cqG5lTZlQoSb2/5YRFNwgAL3XRgaPuzhiWC0+iZX4FfOSVo7pMENSc0SRR1oq9QxE68hWiSkdRE\noq2dpOWG019B4JrlXKNvrLkrMUJ5sH4zilU1RN16NshlO4pE/W+iLCp9yU3tOhdOroeDMEBV5sSX\n88rzfqWGbCdzlLwovLmF6OC4mjmrF4HPSsi+jJqVq2LoTCm4TxIAWNwNYUfKI+KzAGYV2zVKIdc3\ntv0Wqz2HF/Z+mmlP21Pxb9zNw2JAzU912iUJrv85MmEUSXlRqOnV5EpBN8dt2ng82MQtAztJzPj5\nm0wOljbovym9o2s68UWKkcVsW+u/o4fpmLEDu0/z7IJj39E2uS4Bl12w26sC0xzNue9Ykx4+XW3u\niMkZqb9QY/xdNNi+tFcPMQW/CatBNuqFXQfaUvwS0FxSHLkgwa/6tPKdt9Lby8Qc9UIlXM2UpJl/\nNhhYzC0x6EdFGNul7x37AnjCNny4Ub/Ww0R4cX8qod0lRCuYjc9/OQU4C8qBVlWUvWiqPj/h8D8f\nQhCRt8sv1r0iAYpJk3cZpgmuKHxm8jFvDjo5WIz/+22ypyGDYseC1OctClKvmM7/cVdn5VkUnqgn\nJt4FETNQvt7chlPPD1Blrf1lky8HAFkUz5s1KeXaTm0rNu7JE6XR8V3h7Czf5z1eFm5FpaVLnA6i\nl6gkI1Oy031mO6fuF+2UNE0kbZWVL/z2MovoMxd61gsIaH2gjmOgomeRnukJmCRVi68MY3kbsyx7\nAjDUjeD7TumBK+WhBzseB7EYdYrrjC0xNAbW0KTZsa8VJzao26yLPqoVlniszEUaEfmZIu4GUBZX\nvH18+FvNpADgh1KH5fdSuHDiDUnv9oODiC5mrl2wVb904J4khorffh4MJpK0Hyqb15eO2Ca0JtV4\nZjVozV4xm0JoXjRu8uL/nTLuVXTAPNoM3SVKkg1n280oUNhYvCX3i0WN5ylfMuGbNpcN9LJBddp4\n11SqFP1NXhuLwJ5bA0jOtdxqBXbHcdhaeMWFitR3fXFHOvuu8aymkbkfDY0gdRGGti7aSaKU0hMX\nHgwRHUVqc1iR4XykXmb7Q5WfcLF4ooqZtxsSikSNFHzAti/2yk0oMmHKWKyVyVjJdIxz2SwSrPSL\najb0N3knTHQ3MuD1lBFy1po5ELmLCBhy7+rf4itkuo+NQAIac6/zcKBIYoXi1zD23vt5qsgqoE+I\n0Dp90ubxmdHHTmnbPTc4+NNMjNe802tiwRX8CZpAyNkqWZ8oNywJ1SpJTAhL7vDB8KGw10MW2FXs\nnGOuoVn4I66Wj2AWJ7runJR9WAguApiSNyEhtPJ9f/zccN9yj/QteX4ipYXXTXBPY8cAUCzK+kOu\nYX4J5okSHWg7aWiQu8JL7aFCRdxLsadgw2aFgeoz9vX5B0AzCBF7usdHNbf0jEDami6RCH93J/m8\n2OgYYgL8Ej+KCoG6lvUB7OtCjCvIoCrDHKr9U6qbY5BHtKNyZWKLJBRjYgJAXT9v2Nb8RrAlBDkB\nfHRdOhwhcF7TCnh85ucoPzf9Migqgrtr8G8uA/mMezhbEr8QjgZa1i0Plo3+XCsWN7z4bcLKWxvK\nbESWGbRCbDxXRh2vLlXTlrKJrqt7Nf8FtiBJRUl6EPPL4Rba0BmI69JvljAh38P317fIDE4GOtIa\n9mBH4b3fi7i3IjZADl/THipU4HGXDKUo7LVhZ4WWooXNxMBYiHj2F9OO8d51cHckkNvwl4dDHfF0\ngX5x6HZ2Z0euPtHAxIAIvGN3a28eNgs1FbBm4Cj574vBPQ1sPztO3qkYdPps8yHnpZHu8LAKpnjX\n/Uhn45oxLvgkox1/n41E0uciB3IWvFt/eOXl1sE4Op++7BmN26/XUIdbybUof0JAEltx3flou5sP\nXd+BlU/qHvEJ+g7hhcBKwWZ3W/4Ugib2r3wlCRoKzqhT6iG+AvHfkBV08TRK6j9lSio1idWQ88JS\nTHQ+2lESdjCcCVAInngcchEjo53n+PCUerJ9L2ZC1REI8gmQnPT0XkhNUxwEg75EddN7xBVUaSIU\nDErm9gXrJvZQPsIuIkhgQk8i8CZKRfQibb7WYSuhc4dGRTCbAVa5NtFD9MSglM0bKlt17zEKpJEC\nVZllz9DiRMdzE6DzA3RxRnxsyZUYg+Rbqgy67o8VeLTv7GZ0hb168GMPVgLm2aoA+awycuS2nmIu\nBwxSU8jdhryhCanImlvv7n7OM9qDKeFnUHub7j5/vLqo0gUPKbw19DAqLrR/dBm4RiruWwkJL+Vr\nYaDpf63ayaEeAzSnD0cpQHU3ZCLJeBhnfxX0uYGMQNvJLhjZOUAZIKU+q2xLMNBK0s1Oj2SGLJIP\nB9ay9bhEDKNDG+q9tz0jk/lHWt+27PBZ2Orbru1IB6PGvcF7o4IINZ47Y61IJdvNx85lEXBrcA7B\nbbOn6CJjQB+T7JsIxok8+2GENpgNIZb6Bcgqp+lkWXRcSdm4Crhur5On6XLP3Smat8qdnIApPLs9\nbQbuEEgK4iGY0R2XON7EFDqcwpvd9HJfF0doNmYRnby4O5jr4dNWSJcrtpiL1SVKnyGhInFEfQHQ\n+DXG4xim+qZiObzxjxlE91J3P7ns/Z4agRzKnj4Bs8sCFphJUAtf1b8M6ki8+wqxmoorOBQ0TSW2\nfic1JdtlBxtJjj96bMWtzNWxqmdMErlwhYYmgLITsu2NM4iCAfcGKBZf5/2QJAc6KpuJ0YXmAr9P\nQDh8+p7+bfBMOizKNKsdDJpQoKd+BK2c70R8IalyjokLs1SjxebWlA3xdmVEjTqbNeiC6czWFnc8\nMh7lwb3BOc6Ndlx0fLvO1LygzG94HCJEuodp4BDA/XekIbw6e2jXryvJZNncxNOdSAp7NhXD0MTq\nL+eYms7r3dzLqPnTIoOapuMLt9z6pTGSFu4prxt3KfZEY/tg5m2xYjs5S3UTESqK8EGQ4Uh7mj2C\nmeTpL+NnPHN9D6Tcwlf2wKcwzEIoPFOH+KRGp7qU47u00mHtM1w0CJBaprBpNYslLWtgr73bM+TI\netuwVX9xMdE1iIPLtqDKqToNmwqLbTqYbDF7AhnuGCclTOQO7rKzXkiuu2cgkNXs9MDcgBERnrlp\noSmH+1XF5zy5EgDY/aj6bc5p8COX9j8fILa9GWyrAzi1rYG+qiFjYiaUKLyhPeYAdWWmMyh4i84B\nbKvDE01pJCRGteMwcLryJl1FlmrVWZXeKcC8QAzchBBp/Jf37YDds+XbqrZ1m5Ume42Oz+OwaVx9\nQEp0d3b8U+2JSWf7DEIHq8A4CPn0Yz0MR+6IFckEv3n37qebhFORndRzGMZYLwBPz5F+lDjhD1nN\nOBG8YI5McpkZKsODGLCYC3wWWtO9//k/syJXo3iJiTHAkaY3Pk5xdKwb9VUpZc9922a2AA284kJS\nc/w6K1tp0gLU0Mpr0z6sOE2lMiA9auYS/Ut9xt9km5TLfRwtApCrVpLkRpuATTyDkPyjw0zHlluA\nDR8qhNAd0dv12ExG7HMW9hu1wx2tg7gT6DB7czWMjfl0oWfOni5ihNtwEk6CQZd28NjZhRLPtWUH\n+FSLzUGO6SUc7y0gXgUKHWWu6ZLCJjuzVlela+dOL72QeEaZr9W2zZsVyJuHyVD52aVnwTT3AOFK\nn35NMxcXw8wKd2P5UJy7K9ud/l3TB787S29ZjoA3P2PfHD3O3ogtqpAvHFKHvQH6FCjFAhfTNKsk\nHErVZ+LMGHXIHVT6Z+l/KcDRafI2MULITYDczj4T/XSoW77h0fPEHYqOvITz9/+t1jS4SF/xhMpy\nCJ+vM1OJD717OQYw3I8AuWVAKbEFDmdfhO2gYi1hMuJLe7msDDDJmugXMUoF9mrZsfZexfV9i3oi\n23Wes31mp6gUDeJmUnRxu8vnEXLXkiWl/9u8IHC7E2XwWrRrQjWJ0kfamR8dvKkDDNULew+4K2sT\n56U8REcr3Q7WZl30N9S69uRhCs6IfmjziRSl+vlcdn4FfriLuiXy7muqlQV0Clg60PupqJcebXH6\nBUv3N+vgcEBJNag9MeJroiptA5SBkyIwauhthJkNyG9cjMvY+Y0bNjtsLtZs343tIffMIGKFux57\ntQPtlA+1zsQMMx1GkhXVLeWNpNUusFkTpgwJDoQLEOEi8Zp614efkCcYVhmJGzjWSCqabm/Gw1Nj\nJ4Ik0tMKnueBJdhaSEWWsyIg7gzCo6ojbJ/1WK3XZUo8cSbAmj3NpQ8f3K6RGgsE+d42pR/T303c\n/Z3Uhu2BKb+FQ6s9dIHtFotmPfqktj7KhthqO8zqlyNKxItDaisn3SMELHmsayGM/owrpF7nv40K\ne3ed0W7e4bQB4884HK+HliaLERfHqfd6sojXuwMehsBRnJoO8m8q7ahZ6s1LsWkB+Zksnu71S2zV\nHiUZFid7GiuHHiBUQ7Qd/vPMsMJp5bVtz9D4AP3I3dU61RrSKIdqL+KD0OMmiKLD1s9vfq/Lggi8\nyDYOXnEaPvoLPpgMT75wyaLD6A0hux7nQa5XkbPzjFu1KSD8ZwP3SxVWbxj4j/8Tzh4FywINBztF\nn2rzHSaTZJ//RC8teqLSj6JWF8TEBft6NrAKWOnkEeiJ1bjapFbu+Xyc0moJisEfKi0XSUhqo0ZJ\nvo+Nkd9+TnyKNuD7VUbg4gMLsUjs7mfxUIZOcoNkcwrH0C/4n6c2WEoFq4cd7OfYh/pSCxWV4n3x\nxbmPFKTRbHeiuvL8dbAskiR1ebL4RRpvWaeM+4p55Hnr3ivCoL+t3xpR0JDvaq6dyUHXNbah57hJ\nhOWl8WUzGzQ3liqx1NFx5loduc/et/E44cmgxsaUGPrg9EcyCZ3LnhBMH7HJyYsqKWSnevkH3XS0\ndlQkPwd9HJJ6GwvDI5twDfDft49yqpn1LCdAWzFgtEquhfGIISyZRrOYzqkfKkXNSoavO7FzqJ5u\nPXRF4tJdvSlIrbdeRCN/Ru3p5rSBg0ipHtF+YdGXE++Vo0KAvLwFCBynpEUwYwLmFI6ab/wmzDEt\nPfJGznXMlE77hq2SQW8HU0lyYvPYMGpxZxfiyPJaal63xXG4+I5HTlYhvbYcEtXEwlFDuFMuGhzR\ncryuABzlVKTwMFcuBnLV1j4SaflPSwDiIrvcgc59ZFXh1InS6sDvwvBNCyqeuySJLzlUVZ6wuFcI\nrvDc/zMvFRimVCFvYsAlNyuXRDoaH6xbrVJ3rp3Kn2O1IXDh1yB/RKT/G+2HcP5rvHJL3ELRbZuJ\nieInGchMdkenMJGUy1maicvl8bwhYOb6T7q++1RqjyDOc6kG+bGxCEwGjwsHMylLReYe7fA/tld7\nZlOvMXTPD8Wr+YnIJQbNBu3wT0m06a3nMCX0Tf8mPMOQeujDiCxxBKUNU1Z4gUkdM956Frg/AqGE\nK1yAtEJgrP+R7Z4492iBt89YoCfexnBVxaWIsHhy5oy0Gbec+N1pXPvIGK4yaaLUKLn39KYX9oT/\n2kRr5m+fbiSVE6RvSRlihIvzTM0ELxW661/yQWQ3SEB3IV98hF+50e6Qofx7DMLs4a3pNNPMBuGL\nD5lgohDSC8CNH4nLId9yG7gsqxXylVWLKrFltKhvWIIe3Uhb8JG/qQ3posjDegfujtrmpc2W7H7s\n/FvHykVCTUfdYwybgi6uam7nskMH0JWOGeQi/ReIQgbyqGEJ0skd5h+AUDHmwcIYx1j0JtWGV0A0\nmb646def0eNaz5NXkKFscfG/zjwX5yi8+knp6y1K5DqQ5gSM7PFvWO3gc6BzW3QOKRZhwHI1FAaM\n+HHPxvSNMHyntRLaEXef+qV3vRUoAgVTQpadvT8Er6GaRMyVtoPUBLaJ0l+r9Ab+DDx4oAJBQdAy\nhSmfEmWKxdh4jCVEvLIg9RKw/nMZ3g17ElSkyV8JmptZ64i3nwISnFKTqAdaEwoCIDxWLYgXRH7B\nmkzrk8wzEG3zU6gr3RRW3zcpdTqWXJhVVzF20I1vgVqvlb2OMs/D7r+JqyCs71YVHigTOhc5oAdq\nmB/cZ1HOdX0H/45grCiX/WF2SxeJFBUjBzLF+vzOpruChX4Z29SXujo5mumzxkGUkz7ODmqPVbvC\n/qs/p+SVyywnPtg+ST+2NfP6Qm/GvOpc8DTE0mxKNlsTsE2Zo/Q1esOj6yRa8GAagmaAlfvxdIr2\nqQ9GRxzMW6WmYX4OtS7LZcUTygKZ66tKmEmiDT4ysvYlpXwj8Z/+7P8/gKISQYgRttmULOT71oQX\nRIUxl8biceYAQqmhuFWA7+c814MC6h/TQDmQFXE+5lRQlFFNLJeTOxxA7v0x8aDRxs+dw+Ws4CJn\nnF7tPsB7rCl7FNdzKPRG5Inlc8b76YKnLHN8PmDIMofpVmGH3vxbUJPmvoa/Gp1iSAyeqyO6DPMn\nOBEifX39xJdcDRc2HCFkh/OhEXGomdtpu6jtlaldzyxjjq01Hl/LKo7Vo6FklHLsOoo91ViQYEDT\n3jMHPVxSWXXHW5tgH/Ur7RTFxAUGJYfsw5ZHWqXl7hi7MBszl5Q4Zgmw0BwZZbrjBYrMT9ih+TJG\nCIa45gtEJLuoelht5168UiFEo8HXwEak1mCn0NqAnOG07YO0yiFxOR3N5XjH66iljxcI0/oM11ja\nM3jpJT7sIjDAPnJ8HpEkp0YHyPFnokJuWDEvv7j+tcQ85BcAWasVgN2xwJ8c3kOevuPpg3LLjegb\nwedODw9VxVyFUytIpddFyi+Ek3Ef/Q4EszVXZ7wSrZdqVFjVI+PEMaOw3lVur0LxFWsyTaf+WtVp\noCkznzxdoBsTSh1m2znlZ8iufzwiVZ+2k2zaKw8CGe1kw1Iuhi7V5LCdWRDup+eGBrG/MzqR97hh\nFj1+K6JVm8AdT5y3K/iCHnHdmkrAJe7LAjTKAVM2Ckd7mP7mFisLqir41jGxjs12Roi28k6szUau\nbxE4s4wOUxEE+PdrvL4sCjamvasmS24xaw2+sy3UAJ2/HTHf7Yg2SnRGvXrOx/Y3cHbhGP+aDgEb\nKktD+hEx5ivKUWMjX0ekgNUtkg8rP6tFM1HT5rnQe4RKQs13OgvkBF3dWaXWzCRx+xYycevTNusq\nzV/PH1N3W2ZPjrNNtNqwzM5yWOftRUiKNzr2HNyW2KeceGx8l0O4hG2A5kUOSsT2g3GUHVLNl5NG\nNXshenvVTyNS1iwSJzE1mXaMxcWI8xX2ZFXCTTsSKPD3z+Vdgaema+3tVmX9SsUAG+55jgwM3MZn\nntgcXr8wwDDm9/62v4asp+IvfpDb87r7YPj3AwI5u1Q2vWBBPaGRYLUe1YL+KjVMZkTz7yC14/kg\nKUcmXoJMX6E0hYYJbvsr/GxHEmoe0yXgyplmD8z8VHHRqULysYtJX+BomMvdqMSiXMrC1ftqP6Xf\n5lJLt3R1NupQCDd2yg1r0GVoif5x1Cg4O6/MztO0ot4PH13EP+8JhVoVyIzvLTsaG3LpYiI/E04w\ntvtok0m6B1GB1IKYOdn5UhTnnOeDSF8yqSsJdT5+W2nf0Mw4/nPefv5Fi3tEWiKG6MzYu5gAKqyX\nYsM94IBtU4+PjmNVbFDMQqspJboqD93At71pujtI9Yyr4NGe2U7LWqH5DJFqSuDwmUOpkT9NtzIX\n6Ykdg9VGhqU0BpnhvO9mlizoE4kkFRju4BfRyAmukFgTSb32zFRJsA0LLfSyOVbAZk4QIQYIBNOK\n1itbIDXymGcwdFMDHIxFkuj4VBJ6Mquw0sDqF7vVqSSqeARjBK8VEv4fJhammre0ZyavBbU737X5\nUfQ7aLfv/6SCeMYcZYfIVI7uxuSh2yqrF3veYKZiiNavx8Ve7Y8xap/jMfza9JtAtLOt6vgnUjK2\nY0tIRKdGEigJRkc3RXVQgavCbuILff4hg3SLaZVnBhGWAWV2CBTT/gWgjyw/DI0QBukw2P0qTy4v\n0eO8+qeDpwkbzPkDEvV6wrlJwA+bxlDBBxmCgkD6jX3Wl3LXyRqU8D1AYPbJk8/Ai7kKu1dHAi5H\nvZZ1NNIHI4dRuS3IlHtfzaYGr/2+JmvsjNrtVA3Rtq1x9MsHAwTIOE6+2RYZJY/qKW/AhkByIA2q\nzSh1zpWYmq77b6nx/aONic35PMRSW2JCMY+T5HLVhjQqh7tW5eSGPem7IlKhn9sJgRafYJhjbHjC\nkENxS2TGESqOUIw/w5o3d6DnInjBwcCnoF5tM7l0/rhqkxV1NH4tnNEyw1Ga8uaXKvHynOVE6lKT\nsMPfCAlPSfWGZy+Fx8ztjrXqQBm2eIWzC1+5ctxF8z2ITBViDt6othitax+2/VuHm5nRlwdzHjzQ\nshIj1OgtYd2GkFvojf5/hG79QUoRnxDCmRksNc51B9l2OiMNEntpIzx+oPfke9ZOIK0ixFNJU8BO\nt2dd50MFHemU1q+yhgyeJLhcJk4NSlqx6qm4CDxjG+6WFkPQPPX+Xw1HshenS4V4k2yyFz0nzU6i\ntLO75/btg2GsAQMENk4e3YRZ8Nb/EBQo2cOba80ASIzOzxpVXq8pPqJX/hSMy/djXARzfibMu4Hn\n8m7Iu1/RBZf/X/W7tjv2NcyIWgMy8q0FsJN/i9YtagiuR1ZohjiKb0xkZwkfeVJmUXuCiyB+nubx\nwaT1LAYKlobs+U4ROsQNwY14dQKQ379GafZR1NtJfj5NMMXRZl6TOFaZBsxe9Kbh3Do3udKVzs2D\ni32A4mW8HUwROMXLUXpyMzn9X0rXvM7Ef9Ld0xY61wew9Rrxwei8YVlJgaXytu1d0ZPkJZR23Xvw\ny9Iw/ZIWOgvvmnzyitpH+oJ7hjltq4AF3QBBQI6Of5yvm2EwRCGqLxspPgxuO6U2+3yltWBjfnn1\npXTYyTSBLHdoWoP2orkWjwFfKgBMnimJMfhp6BsdcCa+1oQncshZZk5HtNvUHFcaTcBEG/1PE3yv\nFwH2oCdQ7DNsD8ITEoKwUUZXaZcDvEYju4c3FpKZMpUImMJBTjgTLhAJkoh2ZalfJHLf3IbNLmCt\nuDQhwJni81iJA3bKwWcauwNnhTTTkGz0BJnx8pgM/ttQKz1J+s4zap3Nji/DMKWT4bP4GCYt2zD6\nyIY8h9iyhL3bgmYfmFAJ5z6FgbJcWiN5//p95xzkoKaAmWq8bB/qHQKFcPEN3qsWcFmZg2v+lUql\n5c4sT5GQBsZOIaN6hLXcbuBPNUskEmv6opS2zLWsq8n0CAbB8kzlR853B73iImgYV2YeP69BCO8T\nHtlm57drDF7XvirIQTInsyLhQ49a5O3WPn2NYe9pK6sYyiclFE3efqqAs9oCOgmNf49Rk3erhrHm\nXoGcLrwaPpjYfKiDo2jw2BFgabsKfzj8dliDIyS0e+rrT60k/ZntazsdMOPTx8kzLROY0LUXtMu6\ntlXdWX5uxiDe3mk+UlYVmTu56F2SvQ47HAFj4BWEZ4q9MGTKtmt4BIOr3uongvsWnzQRp14uF/yQ\nsEIDOmaaIMg/W4x9FyttQNgQaFRJ8b9B08otcQLH2oZ9wqjZoF5mkuQx8AG4UbTOVvfe2yj3/kOC\nVK/OfyaiJLTL4Bk2StaF6VB6dz6ZE5fMRxXmPvqpGWjv7zDnNvXXpkllH+cuixrr0OmDO4I0Vm39\n23TIhJUPJt+8b+ODtseo3On3NV1tnoKcObkmRzFAQcwz8xSP2O/+Awqeou4aiU2FQL9joaZcqCMG\nafhZz37qUv3Bt446BoTiB4QGz/LOcEyXolSKV+IfDTZzJl7toGQZ7Aqg4wohPKoZuyQnfybaoCYL\noXLdIad2k18KpeEV/Qh5XI61PN6P2Zi31UWvQf73Df5yGbU6QJGOqjdDQqrEEWhF0Z3FMBQgmOLP\ntGi24v1xAMr8t3YtF6mSME9WboB+blOMgVZqx9tdaxxEMj6CAFR7QHiRldIPM9dz3FHcUjCaUN7m\nCg4aMaceWlW9RKackBQlqVfVIC3MMGKu9dJPSHa4Cs1e60hKD5QidTWc3OwxRXdPbzDOROIl9Ly3\nAnK8u8it5J2SKrFvh/AtF7RONh7hX6Yv0OMbQZEYdQRphuNG+/5joFAN0FViCo28VvzRn+U32gsz\nJFjvG7CBccUtF3/SzJTOCRmeal6KSYDWjrC8xT5nVfEN8ik8dDRdvEFlwENhEa4FI+JxEMuYzpbq\n48k4OvNbdsz9YcLSrhiMu+fpC3iC6wn0AcEsVFSewyI357cK0IH4De2iLHmwnC+kOrdMiYOkhEVc\noue7YWGmUDNCEvhGo1VDX9ov6rx/50pAF5ugzOd0600+P9OZQb61XCZNKaN2cRegZKbtthLaSwjM\n3dg8IRMt+J2u/TUzvT/0O/LcCGRtefIi37fdhEqwA8HXy5FQ3xL99QR7Pecn0mCyjEzQy/v0oa5o\n/L/fOZPvIyI+0r8gmjx84THuroakqvrOGC2y+O6RMkcrXBVv6H2yybbv8yWEWIni7nRisZ8JxteS\nxJx58CGqxX/JkjXmFoHwDXjjdv2yKlFzB5HMS7FNMmtBWwS+oSRVtglPJdMpU9u7F9BRqrtwpZK7\ngo781YZSBIV85g1zZFf4t96jZpfUkd0isrYhnPeozon4+fC7m+NFNs58DXo0NSSbORMjgVNyZIKB\nvD1MXkJULySUvu8QqvrHYlVS+TZCj5tSlt8IVcDuLnJu5sa6p6l9Ad/XlY8qzx5hHR+AxxguC+fV\nlZfw2KoXDd0ZfB2qbtbTtXTRrMbEL1xpX8rtksswuHMnGq5juDh7Cpd9nridkZPEiOauzKxsRRI7\nCVB8jfp+2vI0SjvSffxhG3T+/vmlp725nViP4B9tEdwoMtpgd81dIFSk2rpwdVVlayNE+IpqftzH\nEiB9gaK4fEd4+Fdv+177Xs9wg5T1xLxhk1rJKrnRQ/ob7E3PVHjRnZqbTn1lN4m1OE9tM1tEA2+2\nkcETTxPY8wLo3islGIiY1ixpRjeEQq105WXt3NAEOen9pxBSziJ7znplh3Bv5Jhfd4LE+DH+62Q8\nUri2paOD3ASb5LpWvWlIBO1X0c0/GE9yYkw3UT0R90UCvMSQeybhF6LpbIvS7Mj2N7UIDNktDlWg\neoIj8XOGvhC7rulio9/jhvdoMMXW/BGwffJ3bvW6F1j8ofBgnNLf/sD2+CBwmShcJnktV917PB/c\nGkwpiHYwifvb5QsxDC+USJ/6bS618fIluvgemawe96FOvHXuOeQBO+5AAQJFrv6MOETHaBLyxkZZ\nhdFiSwbWgyJC3tTQthStNYQ2Ijqcq8pTeVjc97GyA0FKJAmWDs738KR7ADaCIAkqHkAD0h1MUnR9\n+FbDRNd3OFbCyEZHJivq2ZprIyi9jlHy0wWhXcjpZQ8ol+UEjQTNjbOG3zpMQoUn113I+jr0Gc1S\nTM87ulMhgtzr3TJ7yKkiezPUaUsGLNkJulnKZEben0CeifLkqxfqUkHJ6keOY4liCtxP6/5Q4+wO\nHtduaKRT0bd1vD7Qqm81MA8B09mkDjn2wISomez3owX/JtP3v30LM4K7C7FcjQbHPR49D28EA3BC\nSofi9nkwue+1K/ld8/Bp4ztCQAyHBZlPEpXaZletvBOXNKVHythVgvrTcQbHjUFtOP+9sgM5eL9/\n9xE8khHPex2eMJlYRYEKPrB+RnCR4F3kLYhSx6no4JF1QZ244aj1NXW1NJE92tzOUv7oXvUSAjtI\n5NlBtojAsBX6hxmiiWktePYzERylLrS2omlaxpcwptQEhEMmJS5IfIZJwAgRbCUmX9p98mOqg8+w\n9ktHLbqhVXGf/VbQ55MtRysucuCbFGSbHRdwch7bzJxArfGyxSrFYvM0x/RcGuQ0IweJsY3RdyHg\nFaDJUVNOuZh7yQ10Tca8Y6CzPWA33cBrzqe+DtCn4xWfVmsJwH+RCrljc/+kmStNrPqdFIscSq8W\nz53TCfMW+/r5emiCGSivPAgEUkmqO9Yr1zvHlr4ACSLSHIij6m0KFFoY8KgTPji0vV0i9UwEVr4s\nndgKGEl6X3JoHup/pIDAlbDW9qpn9zCldTtqMDkpCIFNn5Jzz/C+aKzLPDkhkHANF6WBWgl+k9ng\nJfyDERt6EgaSw3jvDjEUGBLWY+Osf4EUumh1zolZ2WxfKIZJ+LGMlk45NeP2yNtb8eKIHUjfhDuB\nAAL78ilWKyuNeSNEneeEKkJkkrDlWGL91FhvkgJiOVKmhuk1imMe2W9Vq4nf6LmSA4Gd4x1eAQ93\n/HhGxwyqJXiSTYoajr1ECwWCZpGCDCtKnhZbEaeklNh7KnPZip/UiId4U+Ll5eG6X4anovlPAZRX\nuN+BRI3VL/HAyrXrkIeFc8Az6/0y9X31vvZlo/cVSWP3PJd5xmelp/FdD2tmUCBh3HE1kI8w4tk6\nKnk0Sl4a/xLXX41mvrJcZt7UGip9fNfOxSoshDLNQSHY0ZZWzwK2M5r2OOE7lqrYEFek3r/sw8Ig\n4bo2+VUUYk8DiEfP0Ug4bKeS+tJk0D/h8nP81R8rz5pIjiZIvTPW4qaL3xxzLNIkjNMWKnHCVA8S\nqz3F6rOVLcRxizrNh/gKRNTTobKB2QU5le5EpNTqZi3brLiIFrb6j1WgRqrKaW0w+E1Hv5dqUmAC\ndygR5dP+BcwYOAoEb0AIQ1Leig19elwk9eQqk6CHHnHoizGmpwM6wWTvuBscCYGynFSduqniI3cD\nX3Ychq+IdmsbN4Eia09nMLa9XT/fgQ2NhHqmr0hhfHAAGsCIm3EL3SIrO37rLXaM9Tj32a9sE8Sd\no131hv5Jqnl38gB2e7gywOI4s66Yj3/gijchJUOUus4vPZ014cQOnwc3d24pRu/LE+c0Gd2h7b8h\nYiLxYPzxUKLOhOcV0ng/k0dVwgwZX/qtCqLJjIPMWZoKBl9XSg7obLru+lEBnUz6UDcynE0yRAn3\nJ1oHW6CHnGACh2ZHMRkcnR+yyiJOaiTDBYoNhUjJTvuC9JF3wK3mMHo4s+QUKIeVuxN7/7EW2ExH\npSKwlBwWgU7D1glsfu2gNUr9AXa37/5Xj4crYCm4d00LBssDXNw8lTV+za2l/ga0t2pEglG7Iq0z\nV8osC9aVgapXhnBeagIeBGgY/8HedP/j5bUcRcrbCXoYqWLDJf4IwwoigyBL7TQhE1qG6V6O21dk\nbeYFLG7kIXwkr5uJTFy93OwTLh5V871nGPNaVaGP0DdMNkTmOlBt5beUabdqElBWxvILKqOr0ynf\ndBqxFbUpSHTxH7beZxZQfgNPu/M4V1A8KY7L/t+HT91HxIP5QKzr9xxkPH9LclB7bfJLIagBQPDS\nkggrpbBnJjtJUcWyEf++hLMI6rdTXlYXw2Rv098jxz8PBtS8/0WtAesiXUQ5llqkMq6BJh//cbCL\nsq0efXDLyFcJtW6TpSy5YyY7aNVkjKzLNavaN+mANVospWckzBwgT1QPt2olmFsuj7JFeK4Zj/B2\n6F4jxR30unHQ4lDf3ga/HCQSpuL4mJrfNyzlEK7F5fmH+/s8UlJGK+DM4CkXv7Q0f237spoSn0dt\n/TI2zupItZoXFpvO3flbGJYpheAA5zhlAnTD95j6twP6V+5BOzZA4RYKW471/7y+851slUNQaqXQ\nCIp9B7OxFjblSZpJV/weOapzR9GGu2WUL34MtsBCFeaQzFx2MLNzu9aSthoU/PyiFjk6Lj/wLaN5\n+zyh95016WymScCXr3F2EFVrj7LC/FwmkAEIDVDNwfPJ9mpoiZ1919PXirdGiVkPuOHPEcMapDO3\nsnb1NVvSkj2CnbbZThL0GPImnc/t3exEY5SXPx6ybzj6T94UQ27BvPByC7kBOD49wmuyviRXcl2F\nIdqUOSbxaaiH5egftzelDJOX1vzyR0YubGDtY5qv0Umxu0Omqb2Xt9TMZdYumooKtV83gZxHVpXK\n99GAZz7+qyLJ9F/AWEycCeWMqgBIE9erlLg/tn0sN6avwR2/nrSFNLc/EC+/bGOUqJNj8z7IBPGB\nfQ8zYY6PrRwjmqPZWK1+Jv0AUJSyUZhJmQcLbZ3Z+Vf4gcrML1Zn+OIEWcvmRV0uMBfgANh4GoHQ\nooR+sgjc3g+XA513j45GTEqX0J38oIjuuejri0o0s1qV3aX1ZDPVFs+iQT5SOlBgaFzniZFnVR+W\nCJMWoFnfp3lRaIAae8dptvQ+z1lb6WbF8E00LnfutS8fEYN5BAvFUShschcve0aNbO2Fd9ZwKNou\neIUdlpNR1xw2YRi6sS0bsxHkj3w9dAhof4Ive4XDr+wdEZR1dcMdReAFmPe4r9M8fAC8TcD+ziCs\ndAyyiXjiTseYpE/SqL45QNnUX8wU1SY7Wkmbj7qB2lFEudgCsl5DvKwNnwf7NPmKtQp4fUAIqbUY\nWawf6h6LleeFJFFbANP6KS4s18rl9e7q45eRXFkkz0xtSYnNtMIqRatPqfLqaYYHtQVlgdJCV+XT\nyxBrVvKWjtS9dGambh+xqG8anwDRaBsvtYTPFjz4EK96d1dxSwc0cs0RZjzQWzJQX2MZkmVDrH9b\n1IzsV9C4oh7jpnOIXc0TE6wi4z5ZmWJDp0R92M51XM+2/JLAjTcmyXbZC1ZjT0uYJasHG64Y0rh3\nsJwZADr6qIUiYINbRVOTY6U3f/Ef+mLQdp3FT/uIg8zZJ1i5GPCy+N2QtXSl6CYryLARFRB36LaG\nUyv0AzNpTVkQ87Y6bjQKXk9PD6vN5epC6J1JmAnmvqK+MlsOBAhm+9pDIdTq6WOAyNFNsuYuo8Xl\nBx3fvu1Zxq2tumbbRaA/i8EDFX/m6ykEO4mFNU3Pl8AV8tn3F3Lf7D44Kmyyml4G5sW/9BgPRbh7\nThxIO5EGz5VFq06zFacwQLo4pLhRBzWLoz+UTHQ44EPlr+3tHCGLVCTWNIge/jchsyFhcIyREanS\ncZ+zNPVhYNTHufWAbKLcDfc0yvqikPWjy3YzXgrbodebfAP/eirsaBJZu8NCQijcbn7MqRiLl6L2\nRteTEVsUyGhODDCfc8VHTiB+ghs3tvTA7+Lc+AIh3t3hNDVH/PH8akeoG7vA3ygHGO0tq0aWP7bp\nduwFCxjfG5L5NaGxRRvUuxDAMgYGInp+NK1+q4jQalIyOLj0kbP//qXFTUaZ9n7Bg7Dp0ujKcqcg\nWv9m/ambWSMtb4uOOcUJT+ifnHmxRO/bOGJGWJ2XPiFn1EtK/ZpyFaBZE9p1wmm8hONEAyILZwU0\nInke7A1LhPXZtTe9ocL6HpV3CZ1XPdIQ5s+iZvjkez1lXN8t1Z2v5BX6rJ7LgqcOR9e7MIgeqr/z\nexY5taAnpUhmG2oIWpNjxhZkKyZkhjpoJu3Fk8j7rVo8jphKtq44KyhtWEk8kL9N2jjzoT7uolgH\n+JObgjkLvRGUcdvWzfL5ag53dRhXyYZsMcON0z9wJmh52pt4CN579yQnbOpGxqSGRmxZmyhFdqeV\nl/p3Gik+8kOPQ+gyvucYfwVhItuwMC06eQ8nuLiG1OJXO76XLRQvEutgU89ZUaZERvWyx0GamYV0\n8nHuCgqCu6IcTwqlQLhrmqM9wsjF/D0T6x4EENrezJNhCMo/69srqn9pE3e5QhPeu3yH3aeqQ/Y/\npYaMArkanCFNUV7TlOHYcqWP61nPzKuVcbmxrpXHTHLQ+KObmfOe5D03iRRGxRl3Aoabr4MUXLSV\nmAWsk9JbnNnBa3oBDusnLinaCrewLFqWjnSmsB3QZGVyxEZGV5ppLDHayV5+Ojy3YVHSdq/o5rfX\nELHj6S4K1KuTvOKug2G9AO6DdldTXD889WyZyJA9I2rl8oOLobw34Z6lr3RqTqZVxeN3/qkMTmVN\ncH8yYWfz4Eejs05L2KjwOOMy7+WWVSDz2SY2Yt+hvoZhaSYkwWipjl7C9s2jMkePlTYRFsCuG4bH\nT46WPqptd9DjIKj0G6IV8Nb3EOVRMCou2kHyEsnHxaK4LjC1yHDP7GRoy8wGHf+03rV02t3T7ZQu\n8KXrObaY6+U7BMIMpvjEmouWQBSg/TeMV8gYzzjMBCr1CjU9VixPiJ23jAUZ6PC84twcOwrPjtBJ\n9Ps9St5u2HpCF0R+dQEiukM0q+ig6+ZfxnqtctaveuLes9pQh6VoD6n7YWGkwVhJWn7Zcl4Xrvof\nb2EestQavqVV94EqwxZw+J2l0wwyjStduogZ5nR465etBuSmPyqpBEzFnv9m/EnvbV2KYdmUy+Hk\nZn37bG2q5a9Lf2SCz2kDknkESUlUo42vrqlIJ8ZljplfrHZvylAgNE5Dp2l3vqamjiMsGkmp5QX+\nc0nbzSWouRIuzsoB5gO1vkmZgajbNKZNkOTjXn/02QayhahheTOXQQ34eA50nuUFBIKcVSk9VdjT\nxBKiCfJnXl9rbX5mY5DOCXxQzH2XNyq7O1f8EUA4tXtYRpGUQc3tHWdqhQpvQblU1PsKFkGT9qCi\nJhg0kt/bLsRiOrKIF+nFMGNFLXYB9pf2+d97R31NRe+r/4AYED4d8y6GIOCqaplPjN2GFmdJmXNx\npDg/PfS5R2trl040plZ65yP75D7vqwV8RYw4R74OX/KMt5rkub4heCpsFWaFwLmPfDax9NiA7uMR\no5AZrTNt67CmOlYKYKFsxPfJx39EDQdqIoPHwZsaNCREcbF8UnO/uuf/stoAIMMKzOYU7Tq7wk1g\naoYuHsh1zOsPq9M1dsoLQQvrIVT6mcslB6L/Ya5HfoO9xLwShFQJlDn2BFP2bk2ZiDwWPksJ5AWQ\nxPyXvs5gEI7K5D4VUc/r8JRWeTKahIZC2A5uQ2l8VPpWfYQm4fXmMOatljtRnW/jUxjHT9oBNKkD\nqVxOF7InA9LrqEPIf6W9F26Jn9Je3Kj61enEkQT7N8C0eR5BO98mUBZsaTHA9eO+mZ0zY6yBHH9w\nIZIhemVTpxVzfFmz+eyY+2xzs1QnCrg45RzeEvUu0GuLNpkx3xg2F8iVk3kuhkgVZaYDYxRQML2q\nB5GxzJuw/4Po04A+WUBVanjXT9cSSB/HkPXdN4eynZIYzpLITcBi9mrSDMoFtv+a9I3cl+O8DdCa\nqYUWNoqWg0JsUYcTLCtR/Cwpe+rhdBoyr1qV7Pb+2kMYHZ4CPYgQqlXzIpsustkAlJjiy+wK/vBl\nfzqHsdM+VGJuL/5Pvx9Z+hmpNZ+/09z+Gl4n3Souu+Zna3gXbBPm9hTEjkEAHqWRmKIC/tcpnWu/\n9m6eym927TklGXpNh2gKnbXQMxUcNaVdt/EyYOGaE/X0Pp6E21GZDj08HgjvlSRZekC2FFww9ZSL\nFhZmCjWUr77qriZfhmaMYo38mtWIC307XLh+385Y/ByGaQkEbR//qCjLSMJSAOi23zGlfD9alyS7\nyzSbI+R1nKYqR0pUJVAv7NnRxVW6IusZ1SyRxgGDUOz2nxVk6QmOQBg4pn4OK1/hkWkCdalkr5VO\nle3IXYWZBupCe/B81dhLl66IemjID2jk4M0Fob/2a3FPpbeoiBIU/la0Ykmi6d0I9RMhyKhDo1NW\nH0kHSRxDD65uGyhx2iasDN+oCCmTMcVoJoAB8ihQBapgDRQKkiJgykvor0GVGVlJHThFcc5sOknu\nEcHXIM5pDSiYilxbV1hOiZFRi0zfKN2C81oXkcJh69IWA7MEPvKhP9XzewiVgwyw9bE2DTr+vqKJ\nGpKPhaSYb2PCf/xMOkKw/2IxZy0DvldZQIz/H42mRGnxqK6GJOcbc59J/CcZ9wicZ0vlX3dvdCSm\nG/tCgWlIuQo2mBqDLEoEyrSrg29yjYYQ9PEgRsJIeh2C2wK15n5uJ63tt5OWr5DLFThm3fkQbXgA\nXzkGaTJGsD5Gs2Tx+fBfn6UyTOK1IVwPAN2zlwML3qEovVHmxCxxqtRzmdIHf7GFU+QS3eF5ypJb\n0Wkqgu0lYdjYtGF1HqJZ/w8g4N2UtppxgUKvgsuArP0ddOyJnm6Orag0C+mU1jVJOTLJsZK9rrwa\nVqnj/xAt03OsMP7FfJJHDWN1iM0JjKx5TLVesJsyMHgC3fgIwfs1WJzkf+Jfi9zmVIQRRq4r8iWC\ndIy7DQ0oHJAiYGNlibIGm0pzBxeWw4gNavG4UxYrnq+stF1WW1gQ/LowmenwG0Cjy8d+i8DiU2tx\nqE5kkIRLYskE4J6IlQRKWkbBdjunTe0d0Y/x9vFKR5vbTOuUbFIiw4mrAwCCuC2x2SudYBNzDkAb\n9mqrAKsiJW2MMW3oV8nAwZmWBbAr8VjbeR8fRgoB65KNf98+GVk5xezWu6x/lnr0CSqNhgP8Aa5w\nQB+C8B3rl00CAv4LtcFA1OSpH9mVbGJT9jlNU34s6OS66nmJrHTsunWjWwfVT/YtIc070EwUHhu3\nkerJEV9OAsm2mblaCWXdeH3oJzAWOt/S+oMvNdV2qbdpyyJLWi9I1SxLtlFBqPLUdAhPAkz1jsLo\n2NRCg8YRSi+yN+uNbNtBQocjb7uBxCeT29n3ml3LzabvmlOf6To0cuq0SNOzxR9EqwHpiruBbcoa\nMBc77aBf1a+9UX28gIncucc0fWsN1jEkEXvx5chO+sTft3RXfVehJrpbpg1g8/SV/s0KS9NxY3GR\n+TNV9hAIdzH2xpxdAZA8rSqKcNG8BWa97giCGGom7uEEC7G7iZs06soDK+AxQRAJ+WmZZyXjdefk\nS0xqti/2PLgu3RiskjNwJldrE1I0uHPnCXTr+d7iBEMi6hjRTrVY0V1THygB5Wz3ABeLA5eOOzeQ\n8Vi5uyjlKB93QlFWHH3lYO+j7VPFOcfCLG9spKytNXO+3ZMuZYAEh/nurWu4ElE3s+omZ4Ov2r46\nEPwYJkVSjk2kGvj25OW3am+nVgLQqyod3R4eeO+slIxDIlI+vEyjLr2vXsUl59o/8nNJajFRrNeC\nQBKbaVlwgeYycDwQiAAlX7U0TlyCmV8LvO+qMuJA8nURMapsXSzQ7NOWsqrGyOWi5RpvFeLBpYJp\nlpXLdwJeAfpbP5TsqK/x2BBwqCw5+v8ts6eJrk7ZnXlkdQFfppkElqUPdjJRdrtJljlexJUV7l/S\n9EDrkcun2vl4KeoH970x/9UwnhhlWeos67t+L7KIn/jTSKVLCFzmgUCeWZOXApSSksada+4I4AAt\n7z60FhuEx6Wcbv5oZ1T1KOEQG7No24iw6ZsU+bkit31BeKNlNlf9iykLR1hA+9n4s/SHpuFH5j3O\nZSNjGYijauXyMyTR4ixS+lSVSyrpQkorw8J0EKC6Gj9/QrLDt12EFhqRc/lDsV3fcl6xs9O9V8dY\nA7lvM7Wafixk9rc43bfekx0ML7M7XG4s9WK3csfpY1oiMozMgqXOJxKD0kuzPssANEUXQ/D85/G/\nnAGdrXqPPiwy3wr6+JocvyteJL9WBanC4cihtz5nna5s1tFdbiuqfysaBZfzBV/6YcTDZKwKvTgm\nqZhIglOMJ9yJqyfJq63r14kkxSjwQMWG3RRiWcLLVOKSZtthZfeH77m4D41miS7Tc/HemOyqdMG9\n7Mw6ogHGykZ/Y7w7Q0wt8JRsdQCYRQQ4KdGqy4hgYTg64Y3Mio7eARXUZoVzr/CL0MIkbX3qQrSJ\n848dCKoRD/hC67cnMPZtbz1gXdq2Qe07Uf9HoKEBU6yOw/Gzj4NiAuP0mSKpjqY0J+M1wrQvgEvh\noYxui0aJNJD3C79rW+WPGfmfHlhkbxLLK4xp2Qbd3PTJR7sOAXqMjlWayatca8PLqsvo3/SUsDOd\nact9UheGGJcJzsHrFJGW4uJVKPja248SGfmB1ezEknT0Kn77YINW3YbBKksXNzXs/TRZwXPPmeSM\nillWe9EpxQsik/xmmOYNuaJZqBpJHWsO5zviU5Cqmtej8YXYjsiUzS0X6nwa2joG55fD2ePKRs2c\nD4kZc18LH99zxLxqlAqef7Z7VbPzF7rRytYhJo3++aDb/F1okJvnlhcWdE8oivy4CynFXCq34Dzk\nZddT5JfNqsqbsjI+Dvnk1g460kimaqtZiSlBWjGOWPbO5Q3FefJ2yYguWtBjOhXLkRhmtS3Jqkyq\ngaB6RKaxgzhqO7fR+aeq1r7dlFxYg/rwfgT/ou0hs/cLKDT2RzS9IeUgL82bZiI3uwApqaOWHjLf\nYSHAEZHmujq+y5+hiIUudFbVXYop0+n9iz8D9T08Y5aZ8XX3jSHKIoP+lzADFDe/st5DYrqf2V5W\ncYAuMkNmBP5vJjfK5rv7oKycQAyZpdD3KKir++RKXBz+ytv6KDZ3ruKbihq3P45XWbI9LE8M/NAV\nS64P1J5LKMAjAAkp+vYYdgjlsVqQL/Xbuly/xdraRbc1pRq/1hjWinOYOUkgFMajLAThGgfpYUkE\nJgYiVJsGajIzDh/jbbxj1TYpCLVE6S7b+OmyVEZ0T/xfxVDka94tS8QhS+UCxIXrIBfU5o/3SQ0h\n3vQn2lPeB6NmP8skmoExA7DVm82EtJ+we2cyJ8urhAD9sVqsW78f4S1IwcxShqM8Tuq8g5BgivVO\nX3JMd11qi6nKODzvG//MJffmArwG12IWCeAjpSSYpaf+6M1NIO+tY/2ZRIBgaTyaYDoaiQK5NVY4\nmYcA92h6QkfdvQXPFJAy4ys/CdO1Yrj99gjrzF+9+gtH5kj5guAt5HCh+4eciVqTfzSfmJaPLQlj\nUw+nQLaoq7hw9DWAfCut81PbxqUUcrVoZYdkhuFacEbq1fsKdSPr9w==\n`pragma protect end_protected\n", "num_lines": 1194}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nCgyLps+SA0ui7dPkXtm83wP9WSUpTVOaNUUaEiTx3o8bDibppEo7uXVLsKORYUGbahjOTDE6kwIY\nyzdcsZuJjQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nls1ZVg3oo/4jpb/tGSZ67UhcCiJPRZSibleEkmR8FGMVr6khAWRoF6kYXnp1zsyHU3zpkX5aZudH\nhQIPiuWIX1ItHdefmGknlXR0g8ejEjnCuf7wiNI29U6+5iw2QftYNsn+9bDRp5kdheVUcuxELJlA\nXulkNd/ln7GkFepSqYc=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nB9jNLech/g/tKNMUKP6f+gjxZsMheNAx8UaJ4vLJVXHNXpNxk91NHRM3Xm9hGCv9VXOliR2a8QYA\nPQ1bZLU5blYqH+18qF0ZF9Jo3IiF0g2nN4gOYAI7m5j6VqkzD58XFZMLPANE17Rohp8jENs7nh79\n49oN+0loRI7XCt+F/XHBh8FH2rSJmirxDK2iqylD74LWMeTBokuvbg3zEGTXe5qvYmMaRiXcTPZB\nDS3JpPd04FW7EUk+5RM0Kcu0Ly1TuyTKFn0mEksltOKTCKOerop73A+MOzn1eX1pf23lWhgzfN8Q\n8HjhN+i90Hmn+Ojdq+WsQMHc6+n0Or8KFbFReQ==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nCS3PEjLSMy66Y5kMQ0y4fL/X9nvJthfWlN6tOA1JzOyIwzumGq0fkllz2YtjUH+WZKf3DOAh6h50\nM/7oiAgx47vujLlrhLAvEpjj8WUfQd3LXqVk3NCO1ki3s4QNBrpCKhg86ykdPOiLuEXDkUt3v04y\nuxmO8exLVDFMG+CzMLadbS6QzvWCMXeAb/FFPfVqwPMMw1ByBbbNZPDHX94DLgrF41I4jklsrd2r\nI3FoDtv57i7fvGeyrplt+iDFl8lNUqFZyHP+5+yvGYA60xKn+8Y180eYGnmQ4wGtQ6Kkzn55UAKq\nBjhfYJqchzaFN68doG8FMNl5CP4MfMmIG1TAbA==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nnQe6+EVbiKYI6EF2Gkjs7kvdzSmGHXU4qtFfR2dYFwHCWHPPG8cZ35Gns8SCNITeaBfeRRFcv/q3\nUoOZpWturDci6dtPwvXGTKFk/2M0wDGp1JDGd5iTwJk4WyDb6tdfibGrM334X5OHFRDy3qX1Uovz\nSj9hOU/EFGjRS84ag4TVcz9z1f1Y+CgW8Ym4KNOI8D0oIv5DmjP/nJr5kVGL/WNmhRB0h+vtCoTs\nUcGqCPC2gQnw0GIBNKrE9ivvsGq/ACxJuuSLwAzquqUInK187ExgWQLiPHhTH6pfZDqnyZpMvGrr\n9OumyGggkggl7j/JE2vtz+6aHVWB1956RXcbLA==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nVPB71QTo5TspzkUp7HQwn2zfRQ8tDgsnLTLdZIsMOrJ+Y8fHz9hexHBR3Yhia6VnY8XCYjgPbAId\n7QK0Myn0r32s+olwHQ8M3jsY7WJNK96AiGDDRm0HHR2rAUT0mbjaG5Vdc3kGr5OmZ9abSnBv6qJl\nd6qqhUFQ2fTIk0vkv9s=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nIOa65t4pEqSGhDPlzgVIxaBhM6TFiSGG2C8XLJL6CyEFm0OzjlVbdnJuVLSSsqeN9g9q0ucPVcBs\n0MDNHCUMFAPmUvHCALV35V9sWsxZnNLruGv6jYCoLT4RcYb/Hskha3PIaIz4tnT++Oplm8SDc6KE\nj0p7EoQtGWfdUwtiBHuUQr6oMBdko07oc+MLXZy3P4PwN6CMYbgRTZvUcrJfxR1JLpjpTlr85sRE\nQCUEGnVHiSu2dgyZ1oOqfyUJGaHcNOM13rm1E+h8I++ksRVlalZKIcrckCfC48c5nJdrthR+8rsa\no+k61kcLH2NbhPC9dAejCTOCHyq4j6eKfXBGGw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25328)\n`pragma protect data_block\nkSwfaOQ2lUKsMClQk038C3qrnU/w3gNGhmdlLNfR9sWwqt9+mhQ5FChgk+V041Zn4jr0vEzfPK9c\nu3LNWSj7Kuy7mPDQPF4wc/gQY3v1ZqRVfjn2zXECRESZ7SISVb3/zgxGap9q5OV9OP32RkaV4kdr\nws8IbzNgdjoMmUEPWIST7YMeljelbQVuNUUiauyLev5wd5EZQgjtqiLEePwttFZFz+wDhSrZ+MSh\nmmVhsv4hlANMdsmgswzLepN8QpuS2x+4bV16nI3UsgySXVY0LRP+KYonO3zuI7oGlDGAKq7rVAA3\nosLmIrbqcv9oa8RF7mwv8MG56fHnNtMapNiNUP5a204RBeFO8tYuAT8VwFE66FWyg0x+SFytJzKX\nnDz/x5eXYt6o3ivPJ9zrCY3V2GzhHa8xLWUdmY+f0t06M/pjIKnPlBKPRL27dlEboBL1WLxjolrb\nZFxdGyaOrUIkqkQm8IlHVFmnZtXeSYrONP35eMP2kL4cGqUTusPeoqJ8DoPv/15TbKPwDOmaEXYn\nOEGzSGJPYZPw4+XZbtGAj0kRbQ261OYzNHDs3X7G23Gf83cq2BWgy5D0KMg8x7egPLMpaWTEJFAo\nwHEzBZROkgZBRyzx4uuOLJAzJ1Ww6ceB1GR8wqI1RSlj8gKQ1TwofF5FVToWZLT6C3Qy89q2zVS9\nA0mSl07IkvpxGwr60pFS+XBimis29n5s8FX1+Y2s6ykhocSOf8NQXfkCEGy+ol7sHN6ItVozii4Q\niSDgC+BYBApCgZz8ak4UXWCf4OdR75O09s2dPW1NNUB0LmDZ+JYg2+lHMwwfQbN8T9npoNochopd\nGUxTp/6OzrzXYuXdCTP14tOiLSckvwYVGLQRUNEHZFUjoAyI/K/pit5jx3240OUI/mdlbVjdEtUG\nZyZ6ijoMx/CJC0RWukb6rnM7lnnhpTUapuQNw9WieVmTSHV397OKlU7n+hVDrAOVM0fnBQoXDeAC\nPJlef//l7tgQN1x1eqzQkPGyXOWazM8DwiOoFa0tqkAslzrrb6K+PMxVs85IisOolgJv4q2sSZdV\n8RYCZM7MjfQlQzFbENfRZbZsAYj7zqKAdfnblfnQtX2D7QAAZtAVZbtICaIF1IOSNnsCi9uxK78Y\njHAC2RNWOwn/P7vBzImG9xwfIQ3kJklicNBdaHlR6kV22DiWPytbzi7H5Yh+1OnunmSMF5aO/a1P\nglEwFosYm2rOGqobOtvZdtOvQZbF2TLhNoCULxpUVohVdo53ERTsmRP3+szwtxMpYpRMOSIt1tO/\nmsxP5ho7MgE/Cc90lcabOMXU6TwV9GMz2Ec8YIMp8yPLEuaGXNyAKwcENA7mOQabA8/QNE8TzFxr\nzDj4HnLuxNA7bZFjKzEa951JtnbjQteNvnEOqy3O3vneTPebf0DNwD/PH2HzUyztYeqCd+4Ke4dl\n2XYcyyJlr51kmlzHyIsGKooMqHJz+hNY04caoQWD+Ev5YGjEMqMIxwhmZIm5te4ZzfunIO6qNTcU\n43BM4NF6J3RO7yg4ITHq50A/iI5hpAQKix4j86HXuGTgrvH7bsVcD2RZlv4gBrOkQU3BGQPAJeZl\nd25lZzULXvWYJCgbaXnlh+1h/NCjB/xX8TnucsxmmHdRBOGDImMff3FDsIEnGC0nEiFLP/fR0vhE\nog92bMwB4+f6Ja/JwPj/hHsU/Y7/vhRpgrJZFtljDVR5p6SPzfqZ+d6oqCyffmOU1mzMzEWLf/T+\nlKoSQNrcH05a6ts9/xvttvEnJoUmUf/H/09aoExwqbqLqI4rb+nzL1Mij1Mj5wjZqg+RzpWMw8fH\niJRUlCev79gLIKjs14oiBS/tPttcY/zs2qHsglefkqtfKIEk9s1OKKBE0NXUYo2xaULzpfqKFTo5\nEFsbG/eTmyP2NlgcNGiGzT4KFsKcX7sZCgsrutPwhhdzOBA/8N+CfVeVEsdrP9sS6ZIQs7McQ/7D\neNshaOGNMbXYLbebelDWqbszWYtgfVphDQs3tNtemJrIcmtApxUA/7VfLQRaw7D19ar4E8ozZz5P\n52VP5E6TvxR0qnt4C02mR733IZNNNYzEN62jdN7lHbe38BYdDWlVSjQ+j/iu8H9Uw1c9sRKzhMvt\nYSbje5593WOrVBZd8GSLK+W2/0BXU1rU8o321xmPD4KzgPFpNqOVlFZBVpuhz+66JTzg0dN+hk/t\nFZhN7JfVIRWniAPyHn2JDFXcGwD706qDbKu+155s7n+ZohU1JSwKxTvrORfYyvnLkkGm7fJQ7YRL\nt7BfgeyatEZYG14LIXAYjvgfjq2wtToa/TvQDGhvQ4Vm8nZzgWZcwGS7TJsxAg9p8hrMrp6rWD7q\nT9p4sQFyZjXkeGQMbXKNj+j76S+MV1+ZlwlpMQmax83Q8n0eG6krBX8W07reDMXwDi/pfHZnR9be\nwf1owb0a9mwrd2uTVsyua6HoiqBX3Pal1FZOUICvgzVeRPQjtX+5z2m2bTFa9Husd5qgJtC018Kw\nio6hzaTDp6k0pEhuNWKxCu5MYR5qZsH1QhQI1Tvc624IFJ/K3Ay7xDjun3verJ4OUefTvdYz0TxI\n3K/tmfQB5VfrezfWLkF0jHF8SXCf/aAil2oXjvKKfzIV+wTzXtKohwD8MEfjITbrP8BbeHj4Qjjg\nGdLwOy1xTGJgUSS9oGRx2/393scsFP4J00gbt2yy4ZaVBbdIV4oPk9/9nJniWlCNrHYcY0VkRd3s\n2h1bfTegZQUVLvAzHmVWExqww+QVrN72GuinDns3uQJzkjW2oXpXU1+I8K/xOe0aOZgVL57N1lkR\nL1i82WWSl7WHMwreThqjifFVASVCTX6sg/1eVK52Ab/QWUmFtTRLUWIOVBozlcWjVZGi0/sDgJfM\nXBSZLF6a9wWTbhObbri+/RP2EJDzxBS7ImjPO7YXCEuHFqwdPBxr5pz9gOmjeSWjbTU3TD498X/8\n7PjURq5/I+TJmVdTEm8qoPvBEILhT17sOnZOCqN1sxzYTUTwOP/fh+5SFWILs8IjXlmtv+wC5IiW\nzInQYX1V02BveC/m0fmFsn8knWeUXWW75GIw8voicnX5MIB28JxYzTqzCcaiKqRigyYOs4Osdese\n1rIQSr15MSZogNQA4Q9uqpVZIJiqX0tGTYJRAdmcBKUUxy5OaslK5g4juCb+CqT435m4GHC5QyDz\nxUGN/7A4jI4VXcnL0KDU0uPNygMNYGjlBIIeSVJzFfLW0SZVCpssVP7xEDYv9oPoBQRrOeKRQ5qP\nGKUUx62dOlmuZ06pL1CFyRCnptFpfjZpiy/u0X9DAKJVLS28kyK4E4aPAlySXPnAgykaXMpq6+L4\ngwQTlJj/RWrDVVZDLpgDv/dSjiDLi1gzYGXu6QoY6yv9kehm9i/zGfAH4Nm4iDp3ttttUcdsGJUY\nOX5pBJJFOq7Xm2WbEGNOUKF4n31GtBjRcid3c6qrQAnTffL/kjQYzMWjjxtyQ4Gq1S8SG8wnZxh0\nLa2V4nn9sNN22rx8nyxr0WZxxCT7FRXBfRsyViBXA/HhwUGT8UtOaucltcNOBKQ9aGEPrXr+bnhq\nCEhMfhyJPjgUKZpaam2DDDqz+BNXGTJ1q3nD4XKRahlStabRjg2WslgaR0sUa4f1P8T98v4+AyKA\nbzxBCXiDIjjI5UCH9o6n0WB3psXj43WGP7Bm9PfB/emi58Acg56+fqEW5+VjMvHJo29TmFL8byAB\novlmPIyfC/Fii0v3LlYWAxWVA4VBG/LpFcgo9qPW+Yhz7sSZNlYWYRx8BSBtFHPZ0UDQKoIXQ/Ne\nRDObMN/WxcEJcEwTRilhQhKx6hlQ7hinqOaDY5B1GFPMN3gTpB1dC5lfOwDwQ6XQbTif0MUVz+e8\nRa51wUr1nWRmVvnL+wl6eX+bie4IcMHbk1IifHUDQJLPPCwJqQ0W/PTILBcdBSnfkn8nQdImfOp7\n+/WRn+WQl5S/4KjVdl0zWtYEetGtJxHGs8S/wOZJ2nxSnzGuFeaomei8jl2gP4EFf/WIa4OzwqKj\nz+2uN4cJx2vlfkt2FtUjeUovD56+jlPthlDUP86m828E6z+HVX7ZoDEV33LWhlQsHyKkmoiMWzYy\nHdVJabgGfyUmXygSYdEqr4ED3FjHYpkAtC/7g4WhqFvZ0TALvPcdB40O9TF3LtysXZQrhEeY14J7\nKdzxRRPsCltAu07xoEYgxU18+1twpdaZZD+XfOXHND3Y6kE3bjIxMBv4dV3AHbmPRivs4kW6H4gT\nFVcUWuPssTRNyv66CLVgv3pLFaGbN1fN1GBG2XQeBv+9kUDCq+rBrqgBwhSj0fncbah7q13tfYsi\nqMGF8LzDq5M97C3HMEMuM4FfQBc0zP81oqicqoWuBh1mhWihKI4/ZlaRO33f3t8wPtZ5Nqn0G8GE\nUNlv8CLzYvaC7tSaKV9gJySIfJKQt6yEnk4CGj+RVRu1UA1/0Er+TlbXajVybaQRgpbkQWq58eU3\nyOaqQ1Nc6JIJRNFNfKNfxWmJlQJCMbbGoPS163X0V0rQ8l5UNfYvEM1AJnntSTTZpcfamyGcrk1F\nydtxqkwn/hjqbFePqd7AqmcKjnKUO8ZLM+mkQD9gvnYXy8VMY4JM3F7mjELqgskwNrDfqk7KYp84\n8H92vTOvdcxMbuELQOGt+G0tx01omR3v2+zCUYlWznKkQJTzg7hSduynfrqjRa4s+ukUMKw9nW6s\nMH5T9pqhfXqizyUg1dFErIGw+8Nn+ezQ2lycDwRRDq5Q7kyS6RHPjMeqERFvlIbn8kimWfeQB+gd\nDYrZ4Sea0vnHhZ8T7nYIWltwn6NkOjxMONqbv5nBAXBhf6rU8M8Upjt6ub1Pp7fpd5Z4O9XOIn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XEmW6zwtcpFPQIxv6hxYxwC/spdTrLGoB4ILEP+NODQpYsELTZi9WLQc6L/iOQgxB2qkazE7\nznpYIqd971MHDyIBimsMsV2MIlfJx+fbxPxgOLnlldWhu0vSMbvH0tKsCaqq51bg80SjHoTbLdRI\n0RXKBNHiY/hwNrAd/uDNI1VArQPSevUJihWecel8HQA/qErqDeuyR3fvz+etmwA+wEarTYrJTqBx\n+0gxN2lWRXXSb1WzVOI/HRxWhUkbQg5KGLcd6MW/+7yH/J74DfKqSSUFnkbQtw4D3iiyobxCMVEz\n//3tVZ94deYB0NSkbNhQwYVGtoYwo8MnoIs31fabSPiDq38l7xlx9fp75ALhijgOEf37nXuBTGRE\nroDKkPV2KRClavVRGPGPcF4rrGho2vJSIvjU67WpSxyZ/hef2sjInD5/VTfOHdjuUA39/udvN5md\n5PU8SA5cevPi3hZnv9LPMedfbs8OfRpINO1/cETQpi3uun7In3BwZIys6d9lrhe0okK1aRQK8Cnh\nqnMJ5Yk/vCW1DzxsS0YjsZ5++CKwZzuxv+pfhRoA360JbNFJ2+BnWfrTDAYfBh3X7DTAN41eWGJT\ndNIaOmQe9nucKLsM+5bqmytNG1XR3x8eQfnSG7y9u95+a0KSMLLs8vDW4TMjY7wKGfjMrcLBXALX\n5RdBS8d7iquImUPCqSe5fyfq8aViMuTA8JyRpN7reZ7hr04/nzBj5v/GYAf/fcwf9/zsj7pkvu7Q\ngA3tRRZn7bfQXUAh4a8r1qtWmNvSRZjlNWf/0mlhv3MlEmSS3VN0lREGa6jOvJOOx7rhOXLSBPTP\nrhkBwriy03trzUP0PVLbhK+GHV8SATZ0qhsPJPvKJ1ArUmrcalWO7R95YB7EZ30RaQUr8LDu8H0H\nxSfvBDwdMyeOuWz28PLk4bAYYi1GFnYL3c+9aBO2/cQRrQOIR7B6zDTzfn8ZAlxv+JYcFcA7cDdS\nneY1+v1AEHA410TBSGLSJ7W603q44z94d7QgfZKpq9JGZ8Ss+XuzuocrjtI/CwzxAYaXJAfyCkLM\nvSecX9VlMHY48b4tYVPrX1WJPcL5vc4bTwpv5yDhIsqRRo4lpshMtpmjP/LBQkThJMDwD4Evjxd+\n0Z5fgZIhj9Cesf9L2z7FA58DJ/shqe5H6BxQXh5EHfWSUwr7+FGISDY+aOXzkINZDYyhT4Qc3M1d\nOp5u/YuAiJwVw0oS31g6x+nPXEvDwGDKIO0jR6+C30Wqzb2uD73ACi3CpG0Pju7LE3x7sgwWFaqP\nR1UHgtF0dYf7H2mg2E3Jvz0vEn7MLjcTcCLLvU551616Q1+rUxIxuCVVppmXP/ktQRbLUsMyXdfy\nEN7oeJSTC5WEEe+ruuQFCDTKWJdT2y0pdFnqTf2ppYzWv/n3pGBJxEdDfXYHh9u/s0uBYf4UjqdW\nkys6LWD2yMmnuC7j3ENi77hkb9Qjl2aJb4q/BM+soWZt+ENkM8mFnzNODGlHgiLZlOivoIO4IjDT\nBguf2s76miE8Y5v7LW+4nz7zaAzAZZrtrzoR8mPrEoLsw426l0yobffsmLCoxB0Myjxs0J/P8V4/\nWHvRj8uQlYUXrrS2N5l1TWLrnIRYqvGam//oUfGoVR04Bsr5BsiUo90ulRGVW0U8zFC43lotvhXY\nI9uIv5zMi4kvR+nv0IiHkozj516FuEBJae321TuWKRqcMNkLJjM0K4k6x2V7fexudWDHVhskWRpt\n2uQAgpcdhkCDKRctrzCKI3GumkTB6yHazXLoWdpVJ4nlq3TwjQiQ+FOK8VG7Juv9qDoWxTEwXLLT\njtJla8yzDow8WL7U+/9B877wQveVsQ2a9OJ0avMJCtrCgZt4IXYX/lmVkkIYi35HVACSra0Yc1TE\nIpiIqWFNdQuwsaJe71w/LZ7wTfkjeVGaxK0A7sSf2+WmYCASD1CkPFFrFdSXvJvK8IUNvAZt+gk9\nPgN0ff1oOOnee5eda9NIQGfaH7++ZnwFYNZ3JUzh7aP8PLUTmDuIUcEhtjMXZC7eyLGN1xrxC6Xm\nxxqU4iBoCLOpL/h28ZMnNPN3/L62xF/eXFI1K2c1NiFp1NcI/Uv0MP+uhyQsTsx2KA8WjYRHyqe9\n46ma8xWeqTc8FpQH+/SNsISHnF73a0dCecKtu6hKNrOLslP96Tl+o63d3HvD2JUGHkG4rEB8PzKN\nIG/N9pDhl2GaeIZVHaWgMC9dzD8ms0fWghnIhCfvYHErSkD8icLH7Q8OyhqS8ZUrhB+Ye6hnH20d\nGhvF09nRJI7YR/b2nPE25M33KKEY5ejkELQZCtvUhn1WEFtH5alKE7dXQG/jjYYTVK0+CbxVbBeZ\n7Ew0/6sJYi7p7QlWt/RihMVY46UHvglpKJfzlAmyPi3vdxpoEQypPvXCL7gOkR1cJKu5xhIzJ5t7\n0hT4uN7EMvLo6IfiRaKGNeCjrHmQ6nRlL76bp3vJs3/szupk1BRBTId+pKkQOlPZjq0CiyEfkOR6\n7xAEu8rgPdRSiY142Yr03ZfgL1tjSTWPwbqe6yXZJHECCaKhS8dOwv0iG1HG1xqfCpDb8bGNG5SD\ncJtGHW1H/y5DkRSh1qCMPyfyH4/v1T/E4/sXAUigrTVxwaz4x5qzq8sdSeVPJ6zEkLLm95p+QG/Z\nujUA1GC4Kp+JWSbCmGIGmH5hywCzcC5aZ7AmfTYTacxrOMh7eHq39R+INTMuzAjRsR7wgxvCfi9j\nVCrjcKH2e9tWJqYS06w9fHygPwsQBnxDua6ufBzh1vXJw9p+1YSqcdHr2J1GbaCDH9g/QIvGU/6O\ndbzF9qmG7acOplOV+UUN7bPImCfV4amD9Atdpn/yCqr17sbq/XnL8PbEfLFWwGtxeTDJNewdRG7I\nPuwOhE7/lAPAbTUjhdmGRU5jtZxwizcz0L2uya35thXsjXDoa6rM6KEoM8AGcBK1tb+yd7PGqnVV\ntl1tPRqgqsMj/Xfk6jwPKq3lc+rwQykIHRcKtuqFITMDLadL5ep6HMsOO/2PjRxrIT10V+AWqKcB\nWLdowlVBAqHvybs7xj18q7zmKGvn1/Z7s9JF9HeX+DM1keWzTV9lyDS8cfCEWKfxCCEMi8KH54Qj\nEzrbqFKm7Fwlg8Oz26tPJ6cJolCH45fSrmQ5PmfPIbAWYgadv4hxIy+8YqesRGAJS+JIa5SOSXAb\nATecjyYRjiHOI3AS8/HJUC3fqZ8N9qAX11K9lBiIjeAbccZK8eaJvQpoXGMA5/BH0vPycGo6k8hl\nTza8n1FJfrMyIORyUNwP5Peq3yZFkXNUcnMjt7tXqHfSWCwg3IFwfmOAgLs5w+K8IQjqtJZqxtv8\ndakxmjezVpTcmWXGsnw99P9JqDGt+BqYzoTXmJxw2iUPHthmNl6jiRoh49BtCqHRnQgIj5pNFX5r\n8t2qFy3ToUPQLoIhrYuIfhzw0AQLDFDScB/23Sk/8pxu19MVCgBmkfh/2xMMKtRbDkLQwTjdwpxQ\nrqEJ8nqvLO+tBbczQsREhamGHxOUpgAZam0D/KuSIlERbp1BpeZziflu3F3wDf2icJEXWOzomO0S\nnodxZZmHYclWxNI/ZytanByEfYfTNEbOvhpHGASwciuVfAXSoXNV7cVmuRG7sBuTSczVQJP0cjeD\nbfzIkwIhsW2Njg80CgQT6mdi4zfsAb0fr80e1VwVbWwtlX4ofhP1JmDrCrDU+AxxV1iJsCSzS7AN\n5aOdu3W16RzErzEE/1um+Ev7z174+8ddYoUfOtuFxVvAElaTxFOt9vUDJ3a5Z4WNvJgPe8cNt8R9\nYfuVdgr0BeqEC38Mm2VemwCGWJiilw8ZNufPdaDuT5CKev6WQzm2VpdCUPYYY3j7gTd23FeyHfZ+\nzX0yCzO3DJT4trtRE6sOb133kXpQkQyw6c32bsOGEHQ2MwtPveJMyiLcdphCUSbZygAY0Wm4OjtT\npq6LXISTFqDQGMYxqDI215O6O1e2d3yv6JmcN6E1AfLIkJScfFfda+qd4yuqjCTuj/65YSaMNf+z\n+SnvOvjH45e7Ad5YSVZ7pLWHQBLz+jaDxlZDwwhfnUCKmKLsz8mKHMw6AveW9NnUvh/sOtiLOd02\nWQJaSR/GcX6plGQLt87uWd/Se+wkzsTJ8uapmtIznpPZ0fg5NY7OuiIjmj3X/cxbsUcJsP4QK8Yo\nXMYEoSVaU6M7gc3m4CsLJESDVWv9usg/ACikf54onEvQw9jGFnP8AV7yhFIZLvfTg4xiFbNjRrcQ\n16mwcW0Fe6L1BAPAPhrb6wDKTI1hd39jJ52C1XA2BpBmZ5yGkT92S8cH0LOJf/v8yb7ymcF1OPYw\n5jYG7X5OUOCrQmmOlINIVsu8XHMlnRa9IDv4H+0ylUJnE2So7kW3rjDFNDyJpJ2yJi6NlHcxpHCW\nm65qtutuY+kbFMpIWHpxjs1cQfiQPCBISnJFVxNGTwgCqr6sHj/5ICiIsCkCO0QIy1jEVJDN2qVk\nl/ZVfIdNHng6I7vy5BzCCb63/mIDlBbCjFiafEPKSnzQwP/0N56D2ImUBCbYSdsjfLV9hiVIBYpj\nYQnNFNDu81Y6Ty/Od2AKyy6UjTdmLb1rdqkGnZ5qqAfhwM2AKZ/XoXwiurBa7+Xgwy+R2jBggubw\nbeRjsDJa7gU4M0gGheeRgNDnoizYw02Vzlg4k1VnPjAsxNr5XcW1BJ4Jm8vjEEXBBGGvVP0psXB+\nL4iy7FHUCgYPy8hYFqN5g7hLvb/wT6pkyNoUMoj6h+9GrrTy+rnjI6kGmNlIsSYu15F7oQbA+V9k\nkLTaiiD0deoYHRklY7pt3lUK7rZHQKf/n6Vx10/80i9aBofpZOIi3uyImyCN7hHcCCpYnvew8SZT\ncfFxgKGYa7V8OeAxk7jpLBvMxfr2ARp+Ep4D1sSRH2oSzKbtM/f9ncdKLxEMHr9wxupSW+XoOraE\n1yy49P59KV53Y3YnD4miFcBODs7CRM+6bqoK9hO1K2W5kvfodbOzIB1IARSmOhRwYdljB19jurPE\nYU3GUTC+u9Te1SflGvr4XsqCbbGMLETHb1HZmXendPnGcnneY+LtnYkbqK7SkCN7x9OkYrdD4Vsq\ntbk3FZFRMB6EZ5WZ214LiLTHzEmLckyG670YR7BNLjK1rQInQAgxS7Ri/B0TGCrTYRAynDMCPXB+\nEBZOhtu0kTKOAVnDj1uOhBFDA7cmnm7e9k9QBKhHkPOHHz6q/8B+iEM+hX+B4q9fpPM6oKw+Y+1s\n8b1LtwySajwDTHtloQWcxc1uR/UsnkCWBPuL9DMNYGr3ZmKTEnGhp70LePkIcfJYuwsfo/E7aCW1\naxn2sWtKwZrw0+CDk0QTotfQ6nG6Wr7hhUAnSqfG2O6kYjQyPSn4k6m+aEiUWQ48MMUvY9ABq87V\nofVf0Efv1OdyGUNFigWmZe8JDvXnZiWw1K9gwZqBldibpaASp9bfFJgdiPr2CAGTDl+r8eoMd1jn\nBbQ2igsBTuhTaV10ZWJFSAIdZ4+V3HYLkLU8oSRXqIzqcI/IiAg5SWLWSaeHmkCkSbn70TQGXGOF\npfjhv2J5yzmkmWDiwFq2qT5eWOMB38FWcEeOtiJ9xvBgjz0qOyAP17fXFxTm23JpVYazHXlTlnnH\nxJSftOg+EKpf3k7fWj4DxyytvhYqXy/Cw2R1dyUtnLFEbMzZd3Kd3ejeXjJdr8nuiqNi+s7uqd6f\nln+VwVZ9a3biIRoGDPRIqfXo5untTcj3xHOwq02XjoFfYNwh12xIfB5ZpUmpKZj34IsNZiFggBr6\n6jqqGibpp2bK8BYBtgi5WPUHkZJIuu/COkKemycnSDpeAv9Dc3KRz3nwhCU41HMq1xWMVrrY5W/B\n6Q1U+SBjTYpQ04mjzFOvYTtEim9f+nV2S1wghga3XTYpWdtpng6n/69RizgI6R1dyj9sZOcdhPFC\nLSFGTswmGoFRGvNeDd01cU3XMMT4u2Z5ZOJ0f9yEb2V0quk1hIqMxHLPaG78pHgJeAtI4ztI+h8x\nW6bMzRi+2SADpd92+2fWMSzXApfsMfb/CJmztrl81bZ/RiWoHQO7FahUXnuklE54bClGGhaEsp/H\nJDvuGKJi/CWrkZltXV3V+Y9rHOa2gxVtp1SNceOD7LJQtxy0tEh8+Mc9z+X68qvpUrp/u4tsNXDV\nXsi751iqAXXO0dnHOJ6OM0o4xjFty4aOINWoxA+xCmcx4EJTLLggpKAdzIwtad13EDly/znQSFLF\nbnp6kOJKqe0W85XvkYnXQff6cnhRSWsY8q2CG0w18siVnfa3E4xAO6o6vcJsbyH18/PAKl3e7Bh6\nNTN5XB88JkKGd58BVcAOZpxLiupbboAJCvsueNHTlyWyvvwbLqsDVuAJBSHpPs1cFjLtkeiTGT+a\nSrqsgMO+UHPBsrwvBGWtDxj3TIKE2Bnvjmq3fKgev8QgzmUU6ZF4/FNAnmzGpTTvADIiUY9lHdUv\nE12u4qX+I69/sHvIACAnIwYXNbd7R33aQ91VJeAcxifdcZA5v9C3ahUaFH3A1RK+enmmfq3TzpVu\noJN+l23KiY1hkUYhiR2aCWIXRySCyiY55+b1G2/fRN6+GV6tJ2/hDe+vqM3JlVPptTG3ZIX5Xn6w\nXYIcd4doI14tVLSyAXT+x6QXdffSrHe/NgPJaYs5pg3BnLI3GSDNxlUE/pU+OvTXDTutF6naLbGk\n3H2+OtT92hDETD3Fix908xWiPIyeY70Cbx6Buqa8znPrRqc4DyitrDyvoQlrTxSwsLstbSVHw7mV\nHsYKgDvPmw1+ZSb9KyxoMxkr19CiTRb3JOrETdiA/VQqnMkjJGK0IEojw02kx+ft8nWEvJkEjXTT\nvyjahSTIEhA1jVfUxN86LHEucrkqhb13um/j1XrS3GRfic1TgpHHW1S+0OcCHpiKzX11xznmgBbt\npi/8dC8uMXKveFYefwObSfPZ+WEbNUFC1u1Mtd1FGzNLljP9SEYPCSYTWYIzMmwRwWT6betJJ+MV\nq/08MKx6b4l9hUTYOylZcrfrrBLhb+qmqYl3C4dEybhehzgcKYDwq4KVDUSo7uPJKSObyezVPZGp\nYxK9gGsaTY2Y1vrww2p4LBm31MsezorYaIvvDZrRulc378EkVjjMFY74VdMTXqb+rpjLfZYvEheR\nltiLMDnzHFMTLx7MnxbGVbuTWXJtisMsbH5vXoXWGEWinvXUjir4yICOZiMgUdQNG9dJKF61yV5d\nD8vuzUbVZWMNKO50MKFFeQDEIi/QK3y9S7CoVspKGFiX9huOjtKEFypMTRvN25ZU6IsPSKFyBU3G\nsf2LC3U6O3+Aia+yJnOJ9j68fJ4j/y4h4EZddq3di2jiahqK6+92jBeqa2iljZiYWvUWjn1GLa6B\nmAddWZnuVAaG7sBULE1a2OvCuqt0/rpv4E2T0oCtg83dwV2wF1xwvR4TTP0k3VJkMDa+bRc6F1If\ng2DHdDMHOJ+zr50PcE8q3ATEQ3aRsHk3kiBDSNjCLxAu8Aloh4dvJok4QPOA82ahFUluEQOphCXJ\nnoGJVkBSWcXhXojWVO2iZmFMpOVj7j7CK7BqYLDRlfM7pQg0hLVUf+8hH8DhQSjK0e4V7/wJZLTP\npmLh/NhqxxhNtRDUhEa3xSQBmYRvWk0RbL7Z4jTo5yamAInndOM6Pz15AIijBTmggr42FdGAT7j3\nT+Hsa3nAUQEAshewF6KGwmCpKUL6hJwVxwujj3qdOYfcfVJVXWy+j2BjVZF3yRPrb6ZcsBK79nqA\n6znStSrjcPRpIMR0WyiPVw7kxu8u41VKTh7+x9iKHXw+V3xz8LDyVhCea+Lu421k0ftGM39elZzw\niICuqn848ke6Z7HBYQQcmBZLAnCjpKlEfKXiBiXC9/jrnytaxYWEwM1XfMDvfrkot4s/9EvpHeoK\nheSD1gXbrFhPXM2+kcS29UIcUeqaXVoFbCth3Q4gQ62DHteN0gw3hY0UNsY9Q05PN9qWfQoEZuBr\na2Bzj2u0Gt9YJuiH9AjxbWdYdJCoTVqSHPFsfTG+SS+TX8PcfGlHY1VZSdrScBIh1mWOl+bRxvvw\nt1Tr6dyDMLPJXu/CwyCj7teA4QrSMaPNh85K9Dylja1im0yXfAR+C7wRmRZ7Dd7QeOV5hvEC0YGR\n8TZxe1HAae7Zs+dfgdvBmR0esfWzNoda1mq2QiWH6R05QM/1sLqzdodSeB28NPx9WP2IqimxNBQh\niv35VU4A3epX/FjfVmMt40C8+kH2eC+fry5mYwvLXIAXZisbdynQAnoM+GQPONBsjaTyOZptbijq\nx6/Z8Ujz3G9XSvdiA2SVWuD410cnGgQrcWQ3tDBKfsz469bMz7VlELQn6SUzoUmTVeXqlunLMgAT\nZjAFpyhxsekFxEesgRUprfqnBWj8WZiwYk+++EaFrrl2LOVoKTGlASaf7i7PCgiMuDiow55MtAdH\nUQ2BBuXL5Hb7cpA7Qv5m/wgDTkM/0KJe9wVdZ1x+8bqBXTFyDz51576DrvtZtAD/XbJnA1kE5pDO\nTIqF52tj1j095Awo65eN1D9llYHxAe5KqySoIQ/mUCts9O55Ttef/xCU3rgLPln/8KfKrqhanX9f\nQytLhGJplYSQ+JeTpwLQ4AMsrKC5htbluB5tV8y6yp0i2ERPTDEqqtq/V7XMiqYbdH+04sQBR2nE\n4k8UUrISsEJt1r/1p4kKu08UaqcNRB+543qvLgCj6oYuFvcyZ26VMqgmFqYnLBBt6rxv0NbItcuv\njnXcTIV4DNLBpHsCGtPT6iKVmV+AarzOVNre2mZDZSjxENol85XuFWZKPGwuQHGf/13N0FwUZj33\nbcAaynRH5O1xKzw6B7o/6QOLte8t808bN8lTg4RtVzap6jb2nZQ79xfViEMvZj4TZ7mREpQb+UH5\n5w0c1wRH6IQcWeMYS4tEKNOFbj1fgfFa5WqDh5RkiRSuT07K4kqQ0IDvbuKVkJLaGtrQikvV568j\nJtt1GYLsDnJvj414UYYVlISVETETB+9wP5/n9mMPoKD1REvPhzX0F436v7GKY4JczyQWlQtdlIMy\nHSjPO318tn07kwO3cAJ5fsIffJCCNagrTfspZf9bzICnrQL6maPSuNgYQgqFwfDF2RM7YKFE+zpQ\n1JcpFaojBF1JuaWNYohO3O3iXCJB/AErTdLoDmZkRGr7+6yhSCU/MqKmeu1eMpbHzscQ1l6VgAoj\nh+JdxnWiH1hTvWfwHuxNuwiNd6hyvHjUyakzZlmJsCLhEWk28R7wCG+6TQMA1Qsc63dQtHvPUxkC\nn2VqxSKjMhSxtS2iXEtF2i4gqnU7RrlZPaNwq7N8FfBAIovNAkquXXYkv5QqOch1Inbmi4qUAA1k\nQPEde2r+zd3qjLYuEGGSjcTd4RTxuMzh80+//d8arJdfJKpgc51kD89xm2S2hti42Db5ewQ/NgEx\nD5Oc6V+9Fp6zaOdR68MZ1vqFLmPmxrnOc77er0e4ciLRpueVvrks4AXCvLpDexU+qwqJpHcO4Nsq\nePNG3yBCFBf+OkklK9K2i96oQfq61gTjMYDrqdASmgo46lvYVsliKZxiATnOtrw40xLe/I4HyUek\nUzpOa7lwnkXdKgZe+gx5Q0jxiJiTE/F3r+2UpJTaO7MRcwplFvXFPSSbDHfKwF/BQjoMq8/pnM5R\nqZYfGin5xwtXkin877nraCfD6s189FrFvYKq96F5I+uEq7n74mQyY274WQJw9Pq12zUEbQsDg0DR\ndgsWPYQEt21HWe5pj1YjzKc3k9dC903kOq1+KD26+8pdMcpvICRq+WJddxHfZxl6ec1XAt2QKB/w\npyPg4yDmh/5/aEOuP45dLO4gUbGL3EinXZWQ+E1jIJoSnHh6vilbDhtX4e7DJ46+QIqny0h7R5eW\nsfDz0mHmHpRxuhReQWkB2yJeHEe5qYDVKFzzV+a/yM9kAxoFkRxFTn9o6n0mtJORZm4wxoGeQlwA\nIXr9swVxSPgM0S8/RwgkdEGMDAz+BfFrjvRRbbXsrQK3aPWDSTFswnscfXV7EW6+nDVhMJMbes+D\nf4yXRYnRL45CqKVRwr8am3VA8FgN+DQrwIvAbrZaiZMzBU3TBLFQnt3zNny734g6Ufl5gloVBA0q\nt29E/m/RIobK12HWVG/5m/8MNwNY070i2VYegXW8o9i74wAONxZgngxdmnerN+0Bmu5ugMhe0V92\nT/X9Yt9A99AjMEGdljk06tBlYIWLBBv7JdeUmUItCy/FWuPaUZzUGLKbzoBfwXuQG458SVeCmYqq\nKCBgyFSQONeMJe7dhcaNg88JTodC+KDndvWzuL/Gu3YGc0LuoOFqIE6SumcamDQzxQSTHzxsJW5D\n9+WgLz7d9U1V9dZkBWq8WC7scYXmYEJY2TVNJjHVgu/DaW5+XOEKNkvtj6pDnGIwi1nRHt/ywZEv\nMkcqF+WVwZAEUXVXzMuF3xvk/ytRRhgorncR5sS3ArptApRy/neZT/RDVsyV4JDMGSdzgvweGLjn\nD2KQlEpHOu1r0lCWsdTnBML5Ya5tXGQcD0s0DXsJWiJqHyeWFXE8YmOpRBKrnBiGLJaz3D7xF+dm\nYF950bejYl9BrCezc8s2dFTTXOiPC2aLtsqtvhGaPGRNomr9s6FF5YDKECFX9Gtzy65jD2Uxi/tQ\n528R4MC/Kh3P/bo6d+mGGThuyYu/w08SZJKPSMmO2HDiE+mtRVzR9pP+WZ/MpeKRWYf8JZZ1cvz+\nQ9r0fJKYmsiQgj9LJWZYCdjz3tupcrvAXARjilyqBOxVIq2OQzjnIINDF7IvpWnGaenn/Ml+wiLF\nuK+niFvzqRl0ZzeOc9MHYQii1+56TeTxWGY+DM1kHBxBOGVqJVkIwtxkFtjDVk+Zk6HyIPDCN2AR\nms7Ojlj8L9WJyotBzxLNdmBQ0dGc1tpCwdthepMi86OcbLBDaImZ6elWWAFQx/1seibqgSYGXwAM\nllhCxzv1smGoW5ScDPlgpzxfrIsVNvlBXRBMTkmJ+qOQ1/ZonCBNBvc6wysO2/bRH2q22N1pvx8Y\nMeL3M30cfu2qmswOY8Q7zJl7tBMfeaj22LgZsejWPOlhwAzfQWVy5IwBujhIplfaAel33LBOiS/p\nAkS5XH8sMf7x24AVDupRC/hXOAy/awmE5KNbsFq/OL14Ptlmnjpyf9NEh5ea/cw7fNWpTaK1Ozo7\nBa1/0RAk203DiiRfXWBNTVH2047nL0PGx5U0jzNtxRJtrx7qOVd0bnP8bRRX0fgGJvrI+whKaSa2\ndI9EJ2rAnBxkJrexb7OzccL5GW9f8fOd6HUYa0KUq7s9PTeV/hqqXND6gZlfbVp+6LRn9XX232ig\n3TigRnOeqs5gBWxf+yNhnbttVTrVkhyHkg/4XF/hGzljDgM3xhGsLlAQYBlu1IFgDQKB0QCcqLB8\nuT+ItAHiLDsKp22zq7XP3hZuPvXsiMVXhk3gzW80XBjO9YdryFgZKvJOslBV9LRpqDLqwVjbwVvJ\nFJvKaKH95Kobys5cQLXhCVkROVJNghm2IzD+gAvjjNNN4v1g7o0HPABDSfWhWSxdr3Q+M7NvmgKg\nmX4lG5pYL9gwmWn43rwtbxilOwvejyvzUpDsfT7sN6rywK4FiicOwdZu1znqp9rTkkleBJU8oWzw\npMUGzh3EvA3wmUx+yi2nJAivFxWtCIBBLF093Qk5TZ9JF5SsZMriphe019NHeJPN7VM0igq8m1nB\nMNsGXrJNqPg3d5+VMFqxPsN1xlVssCxiDRU7hLUnSCPJwOsPbrJ4jJ+iI5Eu3MZqffJdPCUKVxX+\ne8VIBYaCIU1n88ZRBy0/fvnfyBlP3rJegasVh+Gw19ccUnEcs9NjM/kJdHh6qCi41KIxuTjFD9IL\nuJakkfHei206Hx86Hfs68M1idoaz1YXPzE6MLxYEHPJL/jC8wgpUZbfDQMUY2fq151hTgA5UrVXn\nzNvQRvIwp+ejQ2rq7HsJh4xpyAWWp+UNkpIIGfCUtHjAZl5HT30QkWkdsNytGN0EparGxYu8oIDB\ng5rze1cL7TqjaaZth3GqMe8oc6Ee0mdxzqr6WT0jcmT9C0+Id2YSDXTVsKA4MPNekS8nIvoD+FzK\n3wunleyNqhPmHrATn4TtGMsq7mlqvPpyOvoW5T95hr0vyPIYpnDBvJ2EE3A+GoWaeAMfVInayQk6\nXNjWGST0FMagFBvciuZTo/A2VTJLDygqcDZPqqZ+0NfBGuJwo+CRzq5ICxtDwv0oLe5kj3d5G1qy\n2vqHd5m0/71p3ZseGeQM8DgW7Hqv36f7iGKfaXQmvwwIkOY8H2KYBOpRuwOPMwj1Ez+LZipYbyI9\nmKj9lNhNz3+5fIKZFgF29TCo6d6au9imnNXR2ZW7fZGiGKIOKv265X3hNpcDmYeyEeetT7nHsAlV\nElEAcD62bZJAp0i5Riea1lpN9hD7nin+GHCGsCd8W9cYSE22IJKvejLcO5WgiW5lvqCCDCvfwO9I\nasCxXebGi4uqUSQJBxRfSbhVSG8FeKR4XldRaugEqxc5/843LFRdlm1V832Igc+G8q/M9pmobo56\nB5/SwdIjFyaaBofHMML2Dlv/P5YHqmWOMGyNfBRWRtS9gcE2rNA5FtcXXli9iKiF1v6ngG3GKJVS\n1zkwJNaHKKV8OMARo/c3JSYi/l7iC8eWvXxNDMKc/3fjIVgTCeY7RM6H6cWYQQdJoPqR7EG4bDYR\nosVI79WGWVefVhS3TxGX8UYWAxQLbwhbOuie2aLQBy7YXgMNPgV8PIPPHFmVIzHhEZA1OuVkbi7G\nGFhRIUifmPq5g6EVr+xX9TuJHZWSJJUT1/JUWNRNVOu6XNpNEeP1S2ghf6oMAIr+ISdEeDNZOJO9\nwXy8Rcklo4dPaT+lHianOxRpRHEX5YMO55V6aeibuQKXJRwjgfWnbc0EKoPuor8XUbqug/6ZE7j1\nE7yXZYS7KtOsUnB17h6KzjGFznBVRt1q+84oVWJKQIROClMVT9XTjGP9kFT70snh1O9nsL/grGB0\nfUzU/WoBVRdp0oFtZ26Hk82ha/hl++Uivq8UDIol/hzYkA4wQBuvgSSCvkmMbHWQLfMHy9PjciE9\n/e9Vjgvc9KbFGHTb31tbg4MoGmcc0HGO3raQPrLTnXfdGV3VWfGKMfy/RGdSD57qi9E3wNrgGMSP\nBKiCjKLPLI3xHu2qsaJJ2F8uno+WVTOfp2lZxEBWxLGsES+FmU65TrT1fy5ZCeIeaHQabk/HcBXt\nF1uSFz42aPdTZA0SqK5+4faKUTata+cQjVPjsAADtfrToRZy2d+6EHlvXC9ksn4GH17OlPSdv8pP\nnpKDZ1eaJxzV6D8qqVXPOFttt360qx7cWRYCcFenhFVUpxBKZfuQEW7mYS9lVhghyDTWX5chKYKm\neC/efWFFT30OfTwIwInLus4LYOnj8WdaxW9uNOTfZoric7rUiAhwkJb3wNBW65F4QwRZdlyJ1Feq\nkEi+rEKgRdqli6dElxf6CVDapNmiUshH5HOp/PN/FbkZZxw1EZBecJ5TzDfX5rhFCPZqvWb3T7je\nx4Rg0yb8S4ora4wundEjGAzJvfgGZlpLsiHC/UJe+I4zbZAucVG46ZmOgKdt+Z0m3YhyMH1RA5tp\ngR3G4qTnB9TvDF28GTvh5m+KaTNQxve9wPIRpTpVveO39FeFWdrs/8z/yfDbqaBSyFBkaPFFKU0E\nnjRhobVb+g1SYKEkDZYWqeJ6jOLhSqsmpktl86KRKj5T+ZHI0KDotADU2BybQyijJDyR5TvNLU2z\noLnSh+nuPPP/uQ99UDd/ES+CYINuFbbN5iv3ootOk752D8/+eMepxL4TbjcVeiMJsglorDY26rQb\ntHspGg9kI+tmPLftbvJLY1Ah/jkqc9e9dJrx0Gd2X+zVGNFXtgRQEDiG0HBcACcNuC0sNo8ufju+\nDLi3gbESCBkLR5/Ku6ErOVAIaS5saiy4aDoQnu2wbBZfRvVdFLCJxpISgQCcyzt9/4Ni3fLtQqiT\ntG/HKy5+RvsyDoImtnejDJx1REIWGfd9yxIoLnsb7gSJxk3qqKd1HZJRBpcVjUQ/g9EWWECeSSl6\n4BN3NqO9qO2cEU8Gy59FzzD6Nqet0wfwTgbLbeI1ULxDlaghm2HBKvemR//cQPfelFaw8oT0H2pn\nE5IBJs/LYwG8S5XcAN/bT1DfjGTTPIqkcnCuKTJJPisEplPXbcpn9c5KWjApA4dBZiDuABxt4LRh\n9k0hb3AeHhWXvrYWj57EiwiOlS3XOg6iJv7BKgiZC/UJz4yuH/J+IERjAKj6dQ0pqveXN5Ghp5l1\n1hUwA/eKbHE1h9S+2oItwWl1gxNcmjYk3i3ogZVpSmkUoxeyVDyNTrZviXD9FcFBgUtAGOaEetbq\nZFyHbI1B/VBG33BnvSJ2WgGyypH5ggV7azeAYZ7djam33U8yU0wMIMtj7bTxQWnhhEITSH3TTa9E\nndkI06pkCNH0SA7tahb3c6IUOkrLqxZ+1oR8htcEE1AIEpHTBX4kNQHWjAJIxLC6KI//lbj4hk6n\nXCIYAKrm/P7sFmWEwDD8AQYqpChgDejn9MV+4YQYreP5x71z0l5s+//OS6fNIY1YQqlKAnJFgSiS\nkL8Mop5IvPv1Lca7HioxXCMT+QXJ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protect end_protected\n", "num_lines": 510}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_sde_h2c_buf (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26,\nprobe27,\nprobe28\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [0 : 0] probe1;\ninput [0 : 0] probe2;\ninput [9 : 0] probe3;\ninput [0 : 0] probe4;\ninput [31 : 0] probe5;\ninput [5 : 0] probe6;\ninput [0 : 0] probe7;\ninput [0 : 0] probe8;\ninput [0 : 0] probe9;\ninput [0 : 0] probe10;\ninput [9 : 0] probe11;\ninput [0 : 0] probe12;\ninput [9 : 0] probe13;\ninput [0 : 0] probe14;\ninput [0 : 0] probe15;\ninput [0 : 0] probe16;\ninput [0 : 0] probe17;\ninput [0 : 0] probe18;\ninput [5 : 0] probe19;\ninput [5 : 0] probe20;\ninput [0 : 0] probe21;\ninput [0 : 0] probe22;\ninput [0 : 0] probe23;\ninput [0 : 0] probe24;\ninput [9 : 0] probe25;\ninput [9 : 0] probe26;\ninput [9 : 0] probe27;\ninput [9 : 0] probe28;\n\n\nendmodule\n", "num_lines": 119}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"ila_sde_h2c_buf,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_sde_h2c_buf,ila,{x_ipProduct=Vivado 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H=1,C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROB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*)\n\nmodule ila_sde_h2c_buf (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26,\nprobe27,\nprobe28\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [0 : 0] probe1;\ninput [0 : 0] probe2;\ninput [9 : 0] probe3;\ninput [0 : 0] probe4;\ninput [31 : 0] probe5;\ninput [5 : 0] probe6;\ninput [0 : 0] probe7;\ninput [0 : 0] probe8;\ninput [0 : 0] probe9;\ninput [0 : 0] probe10;\ninput [9 : 0] probe11;\ninput [0 : 0] probe12;\ninput [9 : 0] probe13;\ninput [0 : 0] probe14;\ninput [0 : 0] probe15;\ninput [0 : 0] probe16;\ninput [0 : 0] probe17;\ninput [0 : 0] probe18;\ninput [5 : 0] probe19;\ninput [5 : 0] probe20;\ninput [0 : 0] probe21;\ninput [0 : 0] probe22;\ninput [0 : 0] probe23;\ninput [0 : 0] probe24;\ninput [9 : 0] probe25;\ninput [9 : 0] probe26;\ninput [9 : 0] probe27;\ninput [9 : 0] probe28;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_5_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(29),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2017),\n.C_MINOR_VERSION(4),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(0),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(2),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH 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E65_MU_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT(1),\n.C_PROBE275_MU_CNT(1),\n.C_PROBE276_MU_CNT(1),\n.C_PROBE277_MU_CNT(1),\n.C_PROBE278_MU_CNT(1),\n.C_PROBE279_MU_CNT(1),\n.C_PROBE280_MU_CNT(1),\n.C_PROBE281_MU_CNT(1),\n.C_PROBE282_MU_CNT(1),\n.C_PROBE283_MU_CNT(1),\n.C_PROBE284_MU_CNT(1),\n.C_PROBE285_MU_CNT(1),\n.C_PROBE286_MU_CNT(1),\n.C_PROBE287_MU_CNT(1),\n.C_PROBE288_MU_CNT(1),\n.C_PROBE289_MU_CNT(1),\n.C_PROBE290_MU_CNT(1),\n.C_PROBE291_MU_CNT(1),\n.C_PROBE292_MU_CNT(1),\n.C_PROBE293_MU_CNT(1),\n.C_PROBE294_MU_CNT(1),\n.C_PROBE295_MU_CNT(1),\n.C_PROBE296_MU_CNT(1),\n.C_PROBE297_MU_CNT(1),\n.C_PROBE298_MU_CNT(1),\n.C_PROBE299_MU_CNT(1),\n.C_PROBE300_MU_CNT(1),\n.C_PROBE301_MU_CNT(1),\n.C_PROBE302_MU_CNT(1),\n.C_PROBE303_MU_CNT(1),\n.C_PROBE304_MU_CNT(1),\n.C_PROBE305_MU_CNT(1),\n.C_PROBE306_MU_CNT(1),\n.C_PROBE307_MU_CNT(1),\n.C_PROBE308_MU_CNT(1),\n.C_PROBE309_MU_CNT(1),\n.C_PROBE310_MU_CNT(1),\n.C_PROBE311_MU_CNT(1),\n.C_PROBE312_MU_CNT(1),\n.C_PROBE313_MU_CNT(1),\n.C_PROBE314_MU_CNT(1),\n.C_PROBE315_MU_CNT(1),\n.C_PROBE316_MU_CNT(1),\n.C_PROBE317_MU_CNT(1),\n.C_PROBE318_MU_CNT(1),\n.C_PROBE319_MU_CNT(1),\n.C_PROBE320_MU_CNT(1),\n.C_PROBE321_MU_CNT(1),\n.C_PROBE322_MU_CNT(1),\n.C_PROBE323_MU_CNT(1),\n.C_PROBE324_MU_CNT(1),\n.C_PROBE325_MU_CNT(1),\n.C_PROBE326_MU_CNT(1),\n.C_PROBE327_MU_CNT(1),\n.C_PROBE328_MU_CNT(1),\n.C_PROBE329_MU_CNT(1),\n.C_PROBE330_MU_CNT(1),\n.C_PROBE331_MU_CNT(1),\n.C_PROBE332_MU_CNT(1),\n.C_PROBE333_MU_CNT(1),\n.C_PROBE334_MU_CNT(1),\n.C_PROBE335_MU_CNT(1),\n.C_PROBE336_MU_CNT(1),\n.C_PROBE337_MU_CNT(1),\n.C_PROBE338_MU_CNT(1),\n.C_PROBE339_MU_CNT(1),\n.C_PROBE340_MU_CNT(1),\n.C_PROBE341_MU_CNT(1),\n.C_PROBE342_MU_CNT(1),\n.C_PROBE343_MU_CNT(1),\n.C_PROBE344_MU_CNT(1),\n.C_PROBE345_MU_CNT(1),\n.C_PROBE346_MU_CNT(1),\n.C_PROBE347_MU_CNT(1),\n.C_PROBE348_MU_CNT(1),\n.C_PROBE349_MU_CNT(1),\n.C_PROBE350_MU_CNT(1),\n.C_PROBE351_MU_CNT(1),\n.C_PROBE352_MU_CNT(1),\n.C_PROBE353_MU_CNT(1),\n.C_PROBE354_MU_CNT(1),\n.C_PROBE355_MU_CNT(1),\n.C_PROBE356_MU_CNT(1),\n.C_PROBE357_MU_CNT(1),\n.C_PROBE358_MU_CNT(1),\n.C_PROBE359_MU_CNT(1),\n.C_PROBE360_MU_CNT(1),\n.C_PROBE361_MU_CNT(1),\n.C_PROBE362_MU_CNT(1),\n.C_PROBE363_MU_CNT(1),\n.C_PROBE364_MU_CNT(1),\n.C_PROBE365_MU_CNT(1),\n.C_PROBE366_MU_CNT(1),\n.C_PROBE367_MU_CNT(1),\n.C_PROBE368_MU_CNT(1),\n.C_PROBE369_MU_CNT(1),\n.C_PROBE370_MU_CNT(1),\n.C_PROBE371_MU_CNT(1),\n.C_PROBE372_MU_CNT(1),\n.C_PROBE373_MU_CNT(1),\n.C_PROBE374_MU_CNT(1),\n.C_PROBE375_MU_CNT(1),\n.C_PROBE376_MU_CNT(1),\n.C_PROBE377_MU_CNT(1),\n.C_PROBE378_MU_CNT(1),\n.C_PROBE379_MU_CNT(1),\n.C_PROBE380_MU_CNT(1),\n.C_PROBE381_MU_CNT(1),\n.C_PROBE382_MU_CNT(1),\n.C_PROBE383_MU_CNT(1),\n.C_PROBE384_MU_CNT(1),\n.C_PROBE385_MU_CNT(1),\n.C_PROBE386_MU_CNT(1),\n.C_PROBE387_MU_CNT(1),\n.C_PROBE388_MU_CNT(1),\n.C_PROBE389_MU_CNT(1),\n.C_PROBE390_MU_CNT(1),\n.C_PROBE391_MU_CNT(1),\n.C_PROBE392_MU_CNT(1),\n.C_PROBE393_MU_CNT(1),\n.C_PROBE394_MU_CNT(1),\n.C_PROBE395_MU_CNT(1),\n.C_PROBE396_MU_CNT(1),\n.C_PROBE397_MU_CNT(1),\n.C_PROBE398_MU_CNT(1),\n.C_PROBE399_MU_CNT(1),\n.C_PROBE400_MU_CNT(1),\n.C_PROBE401_MU_CNT(1),\n.C_PROBE402_MU_CNT(1),\n.C_PROBE403_MU_CNT(1),\n.C_PROBE404_MU_CNT(1),\n.C_PROBE405_MU_CNT(1),\n.C_PROBE406_MU_CNT(1),\n.C_PROBE407_MU_CNT(1),\n.C_PROBE408_MU_CNT(1),\n.C_PROBE409_MU_CNT(1),\n.C_PROBE410_MU_CNT(1),\n.C_PROBE411_MU_CNT(1),\n.C_PROBE412_MU_CNT(1),\n.C_PROBE413_MU_CNT(1),\n.C_PROBE414_MU_CNT(1),\n.C_PROBE415_MU_CNT(1),\n.C_PROBE416_MU_CNT(1),\n.C_PROBE417_MU_CNT(1),\n.C_PROBE418_MU_CNT(1),\n.C_PROBE419_MU_CNT(1),\n.C_PROBE420_MU_CNT(1),\n.C_PROBE421_MU_CNT(1),\n.C_PROBE422_MU_CNT(1),\n.C_PROBE423_MU_CNT(1),\n.C_PROBE424_MU_CNT(1),\n.C_PROBE425_MU_CNT(1),\n.C_PROBE426_MU_CNT(1),\n.C_PROBE427_MU_CNT(1),\n.C_PROBE428_MU_CNT(1),\n.C_PROBE429_MU_CNT(1),\n.C_PROBE430_MU_CNT(1),\n.C_PROBE431_MU_CNT(1),\n.C_PROBE432_MU_CNT(1),\n.C_PROBE433_MU_CNT(1),\n.C_PROBE434_MU_CNT(1),\n.C_PROBE435_MU_CNT(1),\n.C_PROBE436_MU_CNT(1),\n.C_PROBE437_MU_CNT(1),\n.C_PROBE438_MU_CNT(1),\n.C_PROBE439_MU_CNT(1),\n.C_PROBE440_MU_CNT(1),\n.C_PROBE441_MU_CNT(1),\n.C_PROBE442_MU_CNT(1),\n.C_PROBE443_MU_CNT(1),\n.C_PROBE444_MU_CNT(1),\n.C_PROBE445_MU_CNT(1),\n.C_PROBE446_MU_CNT(1),\n.C_PROBE447_MU_CNT(1),\n.C_PROBE448_MU_CNT(1),\n.C_PROBE449_MU_CNT(1),\n.C_PROBE450_MU_CNT(1),\n.C_PROBE451_MU_CNT(1),\n.C_PROBE452_MU_CNT(1),\n.C_PROBE453_MU_CNT(1),\n.C_PROBE454_MU_CNT(1),\n.C_PROBE455_MU_CNT(1),\n.C_PROBE456_MU_CNT(1),\n.C_PROBE457_MU_CNT(1),\n.C_PROBE458_MU_CNT(1),\n.C_PROBE459_MU_CNT(1),\n.C_PROBE460_MU_CNT(1),\n.C_PROBE461_MU_CNT(1),\n.C_PROBE462_MU_CNT(1),\n.C_PROBE463_MU_CNT(1),\n.C_PROBE464_MU_CNT(1),\n.C_PROBE465_MU_CNT(1),\n.C_PROBE466_MU_CNT(1),\n.C_PROBE467_MU_CNT(1),\n.C_PROBE468_MU_CNT(1),\n.C_PROBE469_MU_CNT(1),\n.C_PROBE470_MU_CNT(1),\n.C_PROBE471_MU_CNT(1),\n.C_PROBE472_MU_CNT(1),\n.C_PROBE473_MU_CNT(1),\n.C_PROBE474_MU_CNT(1),\n.C_PROBE475_MU_CNT(1),\n.C_PROBE476_MU_CNT(1),\n.C_PROBE477_MU_CNT(1),\n.C_PROBE478_MU_CNT(1),\n.C_PROBE479_MU_CNT(1),\n.C_PROBE480_MU_CNT(1),\n.C_PROBE481_MU_CNT(1),\n.C_PROBE482_MU_CNT(1),\n.C_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1),\n.C_PROBE691_MU_CNT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synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4297}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nbGT7tfmyts6/yZChogAFs2kP2mbFmmuiFroOv0r8QQv1hFG6JERBCXNBXfGou+8mLPigR5LV4eDx\nWE5VTd+gHQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nCWoEkLQgvsHNvKsNgOsMIlwqULIpu7GrNWea7T7cH++wHThbYiHobD6dcKucCQM5dNGL646pzspi\ngvc21hWZnPx+X5N28b2dNoegtcTB2kLdLw7Lks54cB9DeoTavLfTRXQYufpEksbrNJTUFVb2cNyN\n6BMeJUXHbb0vXcc5VT4=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nFNNqjXbqqfIGkUevtN9QbqDJwQreUsmu9xji2a/w3CJH665OoQqvJUOiq4+1ZDezrG2FheefDlOu\nudQOQzfUbqq4ZB7QVsrZ5+hnOl4+bTdi/FvverAngGvvJSU8+8gbzJ8jtcieV+kp8HrIMv5M1gu6\nVP5SY5P9OIiRMPqToUbAWBrFRpgduuTuMhaHwW7FZmVUVb1j1U3rE2T6UyEel2fueSISKzjAYa8d\nbMNfbkA2ORUFxDxV3b+bBcjCg+jYWECoAY59uutuI1TCRGdhy4DLAvrLFqaLXnKzQ/zhmv78sBnu\n10yEbUQnFKzl5lQwpKtElSrzEVryLPjEKxtU0Q==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nBtsuQ3rIBJ3UI+4s+peHFvk2pezsWjwgWqpQQAOktytWfnh45F6oITlHSewxA1WtBlnC7B06RlL1\nsh5uBcV81aLk24XWmuA7DcJrmhXRSOvl0k4gIwFckG2lpuYtWsH8y7owyOiD/FZUz/LSfTa3Mywh\nD7uNSNvKmmqFP0yIDB9zQtZJYDKPgeAlZS9NUZdzjF/a61kdekWKbPaCmwFQ0mA01X8N8Euy78Cm\ntwhuK1u9d5vu3NtNKQQjzffGoOig7AOKPE+KjZrhCajjfXLjFewajxJNXuRqE4Qr4GGCy18JUK+r\n9AD7YQrF9CXYq3xjR5zoOedNXXQz29GC/jViKA==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nGzBT1kWKJ35ymgjppXjhmBsPZAh+qqs629kt2BvXZjQHKHWH3WuilMysbQpFcvgaH9NxbR7qFPN6\nyb5XgBkpZDUCCrc6p6YR51wXM/nxNvw23FSNPFKjoFEw2V83YYFxlbr75lWeNCQl27cPfBPuxaSV\nIjlxIsm4eW9SkxEnTQqMX5ySy4IaL9yElffDeFxfvmZFrx9lJp5FMRFsWvs0CJEBnPV6KLu1CvY0\njoTQyovEbzWILZvpO6OoWWowRhHO/ukpDVkTQwizIuNbetdcKud8UyyAngECUSjve9k+rXX41zHR\nrDfFrjZc+RPg2YpdeYHykcsisoZ5sdzyCy4T5w==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\niim3M0ZIoSIeblUIY0hk1kn3BvlRMe2uVKS16OYK9H9BGNvnKistWqz2WEU4s7eijjhhkWdw6Rx0\n1TXQht76iCER16gWcazz66/Akg5MH+lOp9NPf3J2iEV7LK7f+3F9jgvrsadzyPoTuLecIoWFoNJk\nFXdJK8072alT4ln/U8w=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\npJ/yajVXTo6y0FFyEOL0HIGDXa+xEims4jF/m3KWWifm3tyRZ/Qmr6px8fbYo6wt98IysxEsBMsY\nOafake1VkQe9IEYdvl9w2pbHgnMGCgpFHt5GVkkx9kTM7g8X5yw1cj7dCjsuNtLtsSeZ7wW2gvp4\nba+UNyDRcpm3wErDehZlm6QU2gigOYOXUMH6KQLyei8VsyCUEOLrtDfoDMEgbTsPan0OVwWZ4Yma\nBViyJ567bWm+BUmLR7HMTK0+QktDEmFhL5lWaTS848MSM8+2esUyNGdKKutfcQWcpHUx0GkIOnS0\nlZ1qTioC56L1NI2aXWshT+ZrJgi5x4ZYDqF6IA==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64336)\n`pragma protect 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ikj4QY9qy76XYw6IDsQdBnIGtPSFwxd9wChRjkni7PaX9nBoTv4Hkv4/X71ms92d\ntJ/07jLvlYIC/ZQu83ENzkpZcQxr+WVAlk9voN1Lh8MJ41Cksb/e82lQv3tE0i33RVWsfpzzkmhl\n6+iCuWQ09/k8dS0FyYp1eOOSakJpDvCoKsuGEA54TK2SkuCKjd+GAxav426xXnGAV1GxKJw4LUC+\nBoIDk42kjGmgDrTucR4D8ebhRKZlfSndBkUN1MxM4jhRdlUOlo1unmkpDpwboVbaBL63n0cP4G6M\nMWgaQmfg3Yi3VurtkG15kqklP5W2hoXk4N43ho9pwxbkiD0fB7BonN/w9HJv4Zu26k8JguWWER+r\nF24R1GsE91Dl6f8PkWleIhz82kPHFEq5RrhTesz5mPkAh4LBNNYQcbTVLlK5Bz0FGVt33lgt9zoT\n1OXASFCArKzZWd2y0Q5uZ6j1/oVxBrIIV84Ebwg//J/PeKNV+7dWoxdxrSyxxRk9/vGvVL/UxkDL\nXNFXWyLhbVlxG08uYDNL1cw4o1C3ePlskKxvHjLKaClc/79HN04C/k9fm51CrfmvosEcGzKhDPBj\nHMwFxAT3Pw83gG0A4Em+qHW7Wk8Bzor/p/e6kDCX2WbCTGXt8ZMf/Cq6Dryzr2sDHKfteVQJ2fpF\nHC/D0b26BUXdwRPX01IK0w8qiZ5/xcJUdwszggylh3pIeyt8qnPlZ1xYYH05884oekPtILD0GlZx\ndRw6hgHq6NYCifq33HepQkocmMaiBik7yzszAuKAWn2x5Raf/FC2GSRLb3itncwKnJGL7yYaSZeJ\n8OUhkMmGPtZ8ImThhDZ/RWkOBq+OUYnTNhKc3FmrCT9LsMzW0ZyQ9o+VsZv9bTJ+USliatHl6PD/\nLRypXj3clKV1a/C8C+rxwRip4mEQfKcf0UiZgBr6eYubS93izNsyymJ1mp/BMX6jt+kcmR3LAEE0\ncpyyOM0mIgNkjmJmLmv3R6jg/bPvI2p1N7/cIyybB4G0BZtRYMXRngfz1Q6EMQeQVsUna9iAjvQy\nAG2r/xcgJFufo3kkRGq2V3bTmOg/azUFNjzL/9jw4R6mkP391rUCjjKNDXYCpxvDS4Ye2p86OKcN\nXM4s+2bmJRe5JMBVj+0ZHS7ii0Mabn0ehWpoyMokVNz6dMpxel4glyyMLn1uEeaGHRDWuRfCqrOB\nfTnvUVJz1HNeGj9q7pSndbVygb7ZUsG8h3ZCkcyQhLOw47qwv3lDHtO77/HoYY9Tr62YzSiUh3z0\n9j8wCnOkMiqstzZ3iSyRXlGTQ8cV0IIcZ4obZHfQfj7I+N4MXnxEm4Pf8DHrXxlE0RxiG3MLn8Qp\nv1AES70B0p6TKWBC7H1cOxVI/K1ykT6KjY377HDe//18VNIC6IlFJzNuCN1q/+iLfRWlGy+uFMco\nAuFhgOP9A77fsu7sTi6ay+PaHjwC+jIiDGXdUXLPAJHxpDQzZfnDDo14bCy2ZRz1RWNEkUkLH6tY\nuGcD3kggbTyfoEOTkCtHzmGI7kFz1z7J9DYLueA4OMGamCdMbQxvlcUkwx/Yam/jPH2MB8HtyspC\new/FctHMgwthFB+FzPoSwmv+vsUZD7p8hri9LeoCnXPfXS7B0PhDyaHknDkaPDhEol1WramhVo0u\nGKZ8x1eDO9ipKqbYemWHLiAhYr8UXDVwN94diYZ9VcYwIrwr1P2VsWG/9O+R3rFngUUFk8Z4Bvip\n3PBfNVwE/QWhb/BgkmHeTvSayZckM9vCuruECucSChqNjhhIvSGY8CStQKNM+eK89IlUPsvIBY6l\nRZyKERWn9mxbX4ormBumHi4IznKEziX9fRRAEGW0uSLFhi/c435Qai4kSdBAoqvRTsu+7pIC8yv6\nmZ3UTSFrP9ATOE0GChYyllkCW590wKjCJcVXcdotPCuG+4IkqGFXeEYFfkQRLFX5drsg6AMEKhFl\n8EQOwjKQBjK4HT2f4vT4b5aHjEJ05K9SP1v5aTcX90VaEP5hR0OJDY8zsD40NbAozDPvBHZFX0ED\nIRhn+i/XVUxf4KkXcZ7BGUHiQvjXmiD7rd4O0nP0t99gvs5eB1QqiK16/QSY+J8Hu63WZWcdZZAv\n1Bl0sb7QjEa1onPN6MvMm284XZNYPuENoTvl84tdVpwWTTy6KaFjMfpGvs3Zw5rbRYjDqMU6FeLb\n7tSZ/ahWSGlsvFIWoqELhastLHLkIeMZyt8jlYUTAGEOEEraoePUOpjacUg8HrSpHie81DOaay7P\nAAzT/Is2R6begRrTAGNPq50SNgzPNmJomzUDHxlbuHeJYqnJzbTNmu2mm/QNIY5g4T3/ZUKkVv9Q\nrDjVCP+lEG/cEUycZ1Z78nVFuQWmcsM+c+assi7pL+uhWZzCPQizzj2hiM7VoacDeeG1IZ5IwMq0\nXp2/giop0Ak1pp75BsLEDXdzpcD8l6Gf+GZorCsODJ9BfSE12ihwudD2D7osjC/C/bUYdsrC/chx\nlQYFtNBnmCnTwsSK1xoevId8Y2WMMdNPuOhUUHqEtFNHL4EK/KM3VZU+CxrDDhp/Z7aMvgsweO4e\nFmHhSnvDyIGqCB6yPNMXL+UsWckLz2OL1rLGupkCvcfX4pwo9bia0CTK1ZkU5mrPXtvJ8iLvH5ZD\nELwT4RUG2uPfT9F2VS7xhdsTOj5USFtL68jcB4lQ3LdUwqMunj+M/wFkRUsc5Wo1Rna/htuyd3aP\nmvR4afocTUND8sbqWF86oE0b7M84KSsFKWn254Yv45b/7AGVXhW/zTIDhey6hbDDHa3zUhsRJ+sd\n3a7q9Kv9D7ax7QymetYPp67OmrE0CctHogPx89wzVtGxxpSFh+PSbv3u7EfYVFE5UV70g5dbWi52\n3Fe0kbBYQmCR+aJTy4hgxK666akTNVD8jx6UNgpOeJ9oLxbdi9gaCeP4YvldmkPNuv6n5m2SSHCN\nysHNq38Ri4NO/g8LNN3ZqRaQeeW04n7wNj43g2u7Q+AhVjNDn+3cUoMWV0XEdGhAlsvLAziOS8Aj\nAqOcs8PgfNLRn+/63nhr3S1tpn0oiSKA/UymFDp4XkFAl/NSQdSlZdl9yZfocKZ14yfbXP4naSXw\nYXdD9IJooJYT4vc3XhlNgoWURjW+vzbrQ+9Q0aDVLGwmTPWJcogLZSm4kAy7IhXy2y/e6LLI81FT\nbGmZxodxElq3jHE3z0CJEqoS+gsdBtdqC9QTMQaetDKYZvI5/vmZh3QKAamIvXVJ8TAgO+OxHgFd\nFxrvt+kVuLs1msjlkgS8mm8zfI4owlc5u5lmeVXtyCNHPLKHYAzzMNPW5Ai1OR6HoLM6UG/N2T34\nIXbk1QrwXKk878mT9EznzAhb/4bv6hoFEDgRIvCyyYweHxvzpmEfLiP6QaYNWWpO7iR/eaJHWw/w\n790hhWcg44VxliUVIWvozPbEuqHwxbBcXeC5Ksuxlmk8QdBhjHjrT3c76PX/AgEVe+DRzjzKRv5h\nMl6B13x1nZfviHANI6UOudXTe3BSkKBQatOSiKX4yGd35hKnuRYnDSNt1mYXH7lATfmjJFJ1TT73\nWSe0PhhtU7SE6IFs9oBDUTj2gUo4sKYA4alF58i9FJIqvxNGJAiLHJ8E/+pWe+aWwISfrECu9G7z\nfL+1k6nrcGpAegDvvNaMk9nvrHO5U8w3cCleTCuOdPKfWUgRuMapzh4NZ3PMrh8SXD1InQrZuBr/\n9wwsVObR2mdCCdXa+rhcQ78GUFqAhDlb/gDGwNJXRHEtPEgwsgr/EIIqHKun5yMnH9RkzScVLm+J\nhQtsd+JNrs4PPnSzdYGRKsNeWR1uZedxdvvmQuK6V9mJ1/9Rmqx/+sHIBiu+E3k4orWWGYdd/T8M\nGKqyT1rmVf0d2BrSPHzAKYdcRuxuewmDHbGVC3lq/yp65QOvQQO7N1EnY1gqIuYuYDxWjYKeiuwP\nQFDZvr5e0iMckylJHxO2Zkx+I12SyzSel48QzIAVnQmCTJ+X5gndrUh6LnLPRXJ6+tqzD9dfe3fA\nlb+egkye9h3JlbY+3Pjc+50z73r88qa/PpdTLyGj43GkhQTcr/5gW5n0AHoRaXiFYkNscs0Nos39\naAH1XRkvy408nbWfa2Gi7jxH7uI3+F3JkxicVp4XMzt+l+R+Dx0jSIyNA8oHaGXR7iODXmIVoCZV\nsxZNGSarntyxgE8l3LcO9FCL/iMvzfprNsX4JFDepRadUjspZB3K37Rtlr8GmaLhjZU3JZATm0vv\nmoZDKTaGGimpaBiPWWIIg5udEW5MYhrK4QvK8iJiuFcjIg4IBX3XEXi6+aZluEko16/4dzOkmd+e\nlZ5Dld272oEIa31In6knS3GnJn+b1p4s5Hl54tgnvGpXSISYPWD9Lq75SgxS/jHTRboTU19NRWhU\nGZYbeD0sh+mVjL2njjkPKpQ+0YFlelzdofUpHWOTVgDIGUgPQvZBn42WfsNJ/RV5TtsMZLjKLxaK\nKCX8wuFnxtCLoOUXBkbbosQYxnMAy1U44OrJu+0HOBqsrwNh5zFGJ/zk9/5utr8aQg/2aGimsg6J\nv7HyvEFEat6XUm+SLNRb4egTjBiPMHtEUqQzXg5WFNHpof6b17s5owPbAJDewviuC6u0+/FBomnn\ncjdCfOBsKr5oKtdJ9G/cfWevYkjMPzom6RgYqWKsOT4oXSsridVr9YSMbqMjs6TQyI53UUFHfVrF\nl0ryDtX4aJ6oq3I0s1jkTBQK2SVIvmMqBBreOHIPCFKB9G1cVT3e874jfndchxKWHYKOtVIJFav+\nL8Uo1/AnORfpmZ3MT04TOIfAJNO2opY0B5YuzT3m9m+wiD5/zMo6PmrcJJ3WVBY227wPW7hMWNNn\noOjAzzCrYiiO0/jDCB8OvnLChzLzTJmbwJe4z3LzHUGQQrZK+y5Tu/hI2S0CbbCb5l/4CxcADGOZ\nuOemAiz3WmIs6bykPvKCJ3YUD3M4F2iFz0Jc9H30enm5yuyqcKJoLQU5EWDirhIaywUHXRLN0ibW\nopXtRRfHpNK3lMJsLOJLnG0zXZGCJqyTj3qaVPfuys0B3+EBk12yq5qHRl4wt4HdS7zjxXqETTCS\nDWmTnT4ql9Ls9BhQoHCyeboOSARvoJCyg5bUFY4+3V+0E88wVyH2mpmkwGMTO1U7hbxtNJeZNcQw\n4x29DNm1Stga6kl3x8cvgu6djzr1ZOQOVMvIglT/BJQsYwV5NRK8kEiN/JrcDmE4po5lmaqOrEEd\nHnLyIi24A9t/bIbw350lCnc78BGA1Sk896A7Q8M8RbN/bHcWZcBBVJXli29+Go0U1cZ6vjpF4ote\nR7juv/pOYnF6fJkTyMQwM+5vzXEOMm7HcWdYRkQ7D3BbHuSVrhMBF89SrP7kn+SQ7CMEvfEG9gkj\noehWcUlTOkAPgQk+upUfEQ1V0IXIo+XGVCHXw1HlEAli9rLRlvLn2t99tZVdA9gnXSWDnaG0xm8R\nLth+31whyvvqwX0YwczoV5ZcVxTocWZwY2x4rKKiN1sDJ5PCIH5NrEMgJS2of6yaSC59QyvehjBw\nrRNKaNn2j7ZVpchE7btRVq+TWFqRMEnDj6B0wiKHy9A95fPH/jFUEg44Wgx2iIrKPooK1JfFJjbe\nTFsVM//5ug78qIzr214qkcwpUd+Zda7rHkJwxj4C8LcySIdWlAhhrFv5gtSCqrEIxbb4dyTvJ3v2\n29J4OwnSmjFaRx+7TxM4bH5xZBPQ9Aa5XDTCjtMA25CHWN46dF58ljRBnuxj/sTwdaqBLwjLFC/s\nAkRKeGbyuEkgZDGkgQ2uyOxRytYfZgUOGXyYAlgT4iE1lexh5KlOeiAzDxJoIQpPoMWANujOCHAv\n0CCpwPRIDa+2RYtlmvxXnQ/d9rmV/+bvuLlyg/PZfyF4lTfQ+gT5J6linBQ87uSw91z63GevX3vQ\nqIXoRUlm7FQIt6H+l7ILegL0BuaK/5858vbFl7BmT0xi4xczqNU5s5sPC7Jc1JhCohsjVnHvfwY2\n8qzZE/wJGg/5VjtcQrrIsoKjKqxGlUmOmA+gdWpIsqYx8y3lBO3oGE6LdohlPe50Ww3ftoagW1cK\nDi3dli+FTZBsGvAg9jehYrd6aHzVfHf2Y9oH7wo5VVoihibkHkzqoQtIf5kh+5qyhZ+GPgQhBdpC\niJA246TRn9v15Fx0Zn4OzczQG20209azn2UqWQULiPUy0AxceMoKJoI5ebd/IcNXjzH7HNmZBafC\nqmkvrkIAJJ1FNjBf+O0QphrrXFi8bHblHGOPHvgNOuyzywWWqrV4b4ppE4J2k+8EHYdTLVKZZ4Al\nYZ6gJSjesf8kxIgFcpqWikpTVY2Lip3rXeArsRv4MfC5Cjm1TjSdZAhN82oUsfszt8WRD+zl2+Yf\n6uRI8rD7tjXtB5A6MGRMrj9OUEXOgZhE4jqyNnCg6ichcoBhMt6I2frqhye4WGXAEMLI6vSDYRj9\nSnUdSngCYww1VjOT6c5zDafPzD96R10ddX1dvw2srvEC+Ie2efp5Qbmo1aa5lIQ57nk9WBJJvgaG\nXIhje8wa2mkKm5xLGWe4Y/yHPEpOwlPKyb3PhHzx+zIGduSAlzJSD+OZsJct2O03JrLOTWClXpm6\nN7E/Nv8Eynggtxy9yi27yj8r3I9F2I6vcGjNVurnmPRazqa6xDRN5XmvoZIxhaoyc22aS/cA2JTZ\n+yitWSfoXkzAXu6UL610+zmV2mfaoN5ISO0E1Wx5BXyYs9W4io4v/Vs5fF853UcjI07FeyIHaH/8\n633CANkUvI/Ls+GIu3A6u55H4++25ow4UvCUUjPyjgbvM08a25F/61H6L+v+hRkxKtflljcz2yFa\nWzu18dTrzpB6moutKoGhVnBhkISm1U8JTlUhMSkcwDMRjb+QWWk12wexPsUG6Klj1tbVZRO/kCWY\nBowdwm2TW2y2buml37GpNk8DTcKnOZBrPm9KGKJ8AlE+UZvGwdmwZM4ppd/KPXrDRTSAvtgLzqiG\nVO0RfMkmDngv6DSQR63QVXfQ7X1tI1VJcSzIp2FnlO5umBtoXaQr1f6iQLjZs8mHKNN1fbisbV3L\nkiGCuSBWjdyaz7i3nnyYk48bT0DCaLmk04mdPsi84JnyqcWa5HEqD8v1EtfmKP7KCxyqvL6jrGdr\nY2QrX1loreGJp1YQyZJ88Lde9IZlrVYG7X36FxaYuiTpVwyV0lodctAqii6guogpO85KUTYtLiD8\nz6r1LkdsS5eJtVm1N0V8qPJE3B7E5O9Eg3rSsAZegNJwfXmz0h/KOL7ee+E9kESRKPAwzZ1eXpjo\n4C2PK+Lp+RhF9n5kn9ahWn98OsYboOQ/+Vlg4ObgQeIu6hzKJ9jgtuWxYVY5shh7Jrt0uV7Ozv2e\nvnAZTy1CG+AMaHYhJVCrk60hH2jHdkHlRGewtI/rVzCQphSTu76+MqrhzPFiuWNwGvg6Wkz76LLd\nhfcCd+meSIE5pccdbl+mARINHJz0MJdp+AN9v2UrsfZHTUOOa197dKapTQboB938J0Vm4c9r5xEC\n0WRR7MoCZSLvTdcX9g91U68eqZ7aZgO5/oJqod9jh9AZDcjOZ/IZEEUBdlJN2ygo7ddcNiCIpE1/\niePuIMRKEXOabn+Jezy3oVmDxGLZMWCmCtA7SlmqKl+bDtba+c1jfk3rwir0Gc24AQTl/8/AiX3U\nhJTblGzrePrFEtjyEPyRKLCey9jkUXrRCnIJSxb3niKARYGPop2ovE37z/rUVgTWkWj8jruVtmUk\nXDa5ugQIukRCNmF4DRWY2R6KcBoaHm5VD7WsYZHIJKP4fX6X0xUFhGYGx2gj4VlXKa6ceqCBpmlR\nY2Yh5U96Y7N8lnKjQo/1tCXe7lQclT/F0y6KMMUbMdHp4fPwWIyBj8PyvP2F488jZKoaYDcCBAZ2\nFzAB5SJ9UtxvTWJ2r7LOFU29HmpRsScH+gg5k8G/675wfProbnZ3vGj83QtH1cvEl+BkwvWj05Kz\nu4d/mYBk6otvnaXixVDPAz/V9t+eNvXRwVNJ3mcfQ+DzZ8EIJ/yws4jWIkiSofX9OxpLH3L1BbA7\n7UR79P+vuAW2XLA4/voxPvt0BPlz+7oPINnLbEnB3HVWY4zM+EgWeBPAvZEkq36WAZhUBBNguE7a\n8RtT7QkNQq5ZyDg8G6KuJnpx0w+cCkCHtGWTV8maNSJha8Bnt78kTWeN+iarpU9NOyzxGbh3tniz\nfdzfLr9gC2z7ZDK1D3NObjjHSgBGOoPQ8zbZNjIRvY+3m6FqvjcGFJw4v3EallVzfNEk0eJgbrt5\n0rMp2kwHVSf/vfKqjcIHeIC8D8JG6DdmSQr9owY9/HqnlzR5liMglbcTS6FXDgmcLu+iYYFY28gi\nqFNSo1na61Urj23WxbaWilZLtC1U0TU7gS7GCuctgPqLDKFO1gglsegQThvzcuC5bwEwRlU3q91F\nd2p+3+bdCCne65OxvO0ehShiW6Lg+NgoKVG7qfTwiYnE81HF0ok/tcaZNbE709lTsFWC5fIF/MER\nVg2+dV7U6+rJIRf2tW/Pwavee5fm7VAUPC12UC6dZaK3h+YowDeF08FW2raiLFxqZjDBI7TWFZ0H\nlgE0OCIY3aNCGDGD5lhpZXuu5IHqEIrSKrM1p0vl+PZUNwzxcr54yP9/GvEGNovVn3YSTQaYB3yU\nMdTUt4B5/l/48spJ9IQRZJOHNqo4sGuVsLADOy/rNUTcWrlHcKgT0DiALq9k8rvybuyPaMmTKkvo\n6QP1WR0m668K4o1bSzt0rGulNFO1jk1Dp6cffsvGPPQdaLN/J3MNpUcjPMOpHBLyGTB5OqG/4mjU\nGR0byR0Cymms9sl3FH/LrcCbOEyY8FxsvPhszWsKD+co+nol2ncq/5AGd1Yj+E7pPniAvEi/hEuc\n4OVUmFlFYInGD4BlOQ4z7I+0hlGZFj1oOTrUsy1FU6g8j+6m1E2quppZMIkT8lgtWyT/mG+E3j+Y\nyTjtYgsbRn/oerrBrKpvvS3drB6tNlZMZrOZYn8xWzgC3RLspbE8JWwrsZom9BJG1f5mNF2P1cDY\n1foGVSlP8cZisVdTvgY03D/ummRYd74ziD9XcdWpWqYWeCk9MtNUuQRQnisPwsDyf6Iagbu8mRNh\nn4FglPLDfVH04Qx32QoA6E6bWyHKtStBKy4F067MkUQGvBIpLfKFxyXeG3zDRkQuj4joUnzGTPD6\nTFaSLk++kWojfrkMMF/LqnQZ4evnUMmoTH1Knr677TbVuDUTS2VQbRSGuo33/AnFJJ5IVlnIb7JR\nvdHAIG8g4zp0ZE/WmWTCIuOdEGmsDXsBGbtZJQbVHPez+8LOcItfUC96XH06NYNEZI/mH1wGdBNz\nUbnCsAnd/JUaDNe5hgGNc0aDcDfpgNVmPPTG5itNB1SjFzSZbsw+dqkjOYxUxdgxyqlcA2xAz5Rl\nnWuA56Icpx5LJgrYk7NaUiCvbiRjQ4JVAI3UQfibmloLegVPOu0WaahNR5z7gt93JISTsBZDOdJk\nkUX50GH3o+E5y2s5uQtEHNVzT0/VdOuuolIpCU5aoFcrFR5cuklmtaXcpJn6CFDQa1YzjoUaCnKe\nnpeJymF5dt8FbhIpA8PSuo0aBUq09MODdh/ZRaotvwLbYMDzWQIfKj0ndZV1nXBFjD4SQ+HoJ54U\nunuE4OZbTfvcC7ViY/RqV+Xkd/APQDwMfey+cXxqr7guko1eOqgR94FuW//L9CD1ZKsEvXpmRJdX\nBqYyUW6GK3akL3uIfIQCFtwyGi/BfEVu3rAbR3yirvflkC2o79Wa4BP+zh3tyGglK0Bvli6iar+A\nX1DA/dkwf4OqHuuG59dpNE4p/om4LMJXdl6SqXLhI4N5WxYtX2Px7ooR1NSZJl53yzBYZMOuzaF/\noaof3V2t8hYmlrfqUyBusIMDXGV41H5pi8vusj2z+i84D5mMz2c8T98Oa1CJKdCY5FXja1/TSWDt\nD2rNXOtcZgKzLQudXyS3jPb2TCMq3jOBycBDFH65nKAyGIFyeTKPn6cIAJDkBuSl+0bjUg8pILwC\nNmlAfw7DE+Eiq8aseLP9HhlVRm23B66+ryPSlSuUGIVmrtKKhWS5OKNDEqTMGEh4aw2sGNVVYvKS\nKbaGhWe60voQWV2IT9vuouA0hlv604k3/EwY0gODPnA/L93YelofcHaEhQEVx7iesFAVqq3KF2ue\nfKECodO8wfwW+RnycXayyuWlb2UnYwFI2AUUGCWpKShmVUarMlQKrWrIhTbO+g0vXa7E7zS+9fgJ\nWObDboS6oXv3rL6aUh8CdHvmYvR8QdSvfQvK+UvouZhsqTiycdhIO9oHLN5xkd4WWxloyOWerSvq\ng8/d8gOPzhBtKlPnJzkossrJkFwt5Y5+O5X12/+c6/n4WD4ZOddoCXy8i9kTQ3C5lp207Hh8bOmM\nea5HEgG4SoKB7kJtEIB1+5Ylct58MZUcUaHt8DP+uWNMSnY77vn+3RQm095pjevy0+URNb+7rW+4\nf1D/G4xH/mtDeKGQGekaf2e+KUEiKVb4PmHoTINrx6Pv9Vg01K5cEUcjJeCDoKZLy4NJ5cDzQSp0\ncPt7sgk2Up2jSOfivtrO0Yt9UzS2JK9RnBrxR+jG0sE8Zbi0U2UceMTAzYtt/pXz5RGbTXlxns9a\niforlRb+rHpcZmBqUbX9HMaGj3A8EC5aSERwk62OvM48On0A0lfW7ckac9U7bI2UeHUVkgbsLi2Q\n4mCjKZsKM/64VwaiUxvf9D7mLGgyX+4UWKpzdIXaxzIjlaWixYOcJEkwDwe+8BIlMru9C2uZ9+MR\noI4sbmHJOyvASFf3FlN2zZCEFPPuHoiN6H3y/IZd82q3xCaLNiMiNxMCRUgIHFwWdHt5r0lcTTdU\nh/TssUxGaa2KzM8lEo7CUkgMeoU8bWjB0DkaSXtusExrM1uNSd1l+eZsOMX7qzzJPEZeCatCFhK/\nBkWBpVm9vF4v3gNfhsVPSfkH1x/AbGjze0ZSaPJiPc4r7NcPoFZE1nIOIBABM3sJxT3mv3COVn+M\n1O/O7vXVwaMnugQOegqaROMi5zZn6fGJzhh8/8IIifmBei7ylRRqhJaE1IqGvLY8iw2CFgUbCsEJ\nQTppgPJNm59zRAa/4LWLZvs0u+wssdq6yRTOLomawCTb2+YSrSm4cBaef2FUqaY8z361WXyqdFpi\nCbmgzpCBcYWBcX1fLlSDN0FTptFOxlVLEmS1xO2GF472l8hQLEqEV7vfJvno+Z//8TjoVJ0mPAT+\nOodKgQ7+RnJBzAHC2bdAd6Wr5Cs1KYmxfeO1w8diEQk+7UEYEUfqDWOnhHM12DPdhcstSug+kJFe\nriF2f+ULJp0BKy2kJ/JJPAGRt53i1m2+71io+LzZha+RdggjfDKJr8EonB3mJTv6Ey/YxtD7/aPz\nsM+MIrZOFx4as9lBSVDYwTBZMvxLWLSdJsX/hZ8uFDZQxVyFQxfvrth/I158LUm56IUJcIyHeitQ\nJFFKCU2sw7McobUMR3H0dnKt749a5TFcp6Pt9OOnS0Kj2ZJ0zW0QRSFoUjeqWSlfVCVDBR7r2BpL\nG1tjy7Cqfqv1o53HItNjtOM4y2wZ53IpX5e+QjWiKzzYm5bi9Zw0sqCkhWYea/Ikvaaj5i7a+N2Q\nGUDekF0yxvDgpNKLYReqsEnViPjfOthZsiQ/ZF4f5FZkimf28UGqFSCYBhoyAoZCObcuokDZHSc7\nqbD8R5YbQFNmIhBTfo+LwHmZS9/r6GTAHKzt3NdOZJ+BlaPdFo9LoXpZFl7BISoGQNZp+cqJmxMX\nlElx0u0GPPHTNt6ilQWCwLZM9xFAQ5dH9aplVb1fFAdsjXUEJusNpQVa0ohBX/MlRqEA/ok7gkYU\nRg1Sl+gij7mTVCyaeKWlDR08H+GjsgnqBew6ptWyV+BLqxz1pIwS1TPPT9g2LEF/AXbgalw06Mhr\ngWyomNUgaddL15diQS7eKVlYwVtuO9Dio3USx5ootyq/tTQhrjkS124tYNG/4ozFsQy8kXW/28uQ\nVj60rTnm/QkMkD33zu8zBwXYOZ6+BhuSbsTph+WRnBagf9hxLJXfKYBbTirzgFHDPcrp6unySw1h\nXerYV26lMrK/9VrkVxxsC8LW/JGxQG0PHDl1cLs6YGseHZQa/ShX8XE7AtAYkJ56xfWkYduswh8s\n/xwWm/i19+VTuedahTPvXTRWxxvy7nbn2xV6LaUFixHNVy9k8lKLRdXzpNX1zCe2kB53fgz6XHnL\nxhN2WaHHuNFzUWCv8NghHah9YgCVwcCYh8YcQrqbuhpjVm/NprIxoZuqSuN1xRy/zfwU28FCMI0Z\nb3PwLG7AvfldFgTZPwBIWcODxzP894mHaNG9itsQjhW0ksSSxvYweLBofWtKhxFthCxXRjQYQlAo\n14uDlf24ruW2lki/ARokBEZ3c9WOn7xG+8a0XIAMh2Ze32MFWm50mba6Yk0jKXF7aZbfuH0MHbk7\n9U84WW80Rl7zWp7WK3mvHdR8kaFAyO/KFGsmPo3QwmBX3cmq0huPQVvvq9BjQq8b6DVoR0HRMFh6\nTS6HT6Gw205Po+wLRbrwzwbq6pUVKfHCySnZhHc2j3EXi1QjMy/UoGuW7bFHDALulwEzC7c4N1nP\n58hDhowIruHJ2UgjnpJYzV99YlPGs3RNfL2D5+uUFvkflxDXHnH14Ay7+zHIxr4HvncQGHOr5Fu9\nhSc76XDHb8pIGd8IdDD2aKLshPMrNF7ZVpt0IS/ThWkjpqI4HAwa99Oor5TJGkGnrK5nXCKl/V4U\neaSxXvHyD26Ry4NGBk2JasO8VqLSOVfuemwekAA795kOriGjdcU0hRZS0UK+YZIbt5M29s5xxQvn\nZgNF6Abotf57E+YP1F1eVCsopFPKfvATEpYTvUxBFxW4h/29TjMvkq9uvfS6ys+XhHfCrVIsAwv6\nr1aIxORiIZbULnlflxEryS///gUFpreGJpoPgLIzo848gKdf1bu+I5g+bikGAFcVIi27P74t0Q3D\n2+8X3z/i+DPkeMw0IwTCCxYpl/lnyV84ZlOjbvO+yak1dW85HmcOxI+Yx4X/aTWBxL1E1JUhsXny\na+5tcHCihqtH9TJ73Dz1Ctb0OQgLEcfPmziIrLrdgcEZv5fWYBjEp1PlCpqXnSKJik/ADIM2x1ZS\nwTuWTrBZXoTUnBmLXJvXwMOS3iK93JnKWLmogkAwQfj4NpYV9rRnNTEG8OtcRO6x+ScjxM3q2WcL\nNxMiwGOvrqy1PNsk5tqJrr+C/vX12LjRSBmKiu6xD3m84Sfo1ACMuimkJwSHDqd1FhpqLMWkEHd0\nTlg38sEgiPxPzQX8nNNDU+AP4ONfUTzkEdOKcKZiBzccH3Dh/3hMwpWY37LbN9EhqqQ6iS69/Nff\nI8jj0x7Ekmf6ZhNztfDvMTrHdMA+xBQdc4cL3BT8LiOLzDV8rROTTFwn8nHNro4jnAUqYf4sOABW\nwXiNohg3LLOwTe7gQpSThqCx5mSjmdOvwSEZXlSaciS6BJC8lgM5zJSzOURYOSMRl0CzfSVfiPjL\nl2lYdpYudLJqm32t+mntGbSc1wCqRy6djjjhFUadcHGBtn7ZMpcsGXeZ6PRYLYuWEiFrcxdeCBSJ\nMa6nR+aAfqAll8jQGr/c+1QtM1fgbtgUdnqpw2qWuRmW6LDkmuIxUHDJ+RS60L5zrYrgI27cYpEK\nUMcf/Dju2oqap/yP9KN2nvWiK6+OwAuvG22RDw7VIX/YU/KvVgED17M9VrSaGN8tqaHzNTGM2IDV\n7LGeSz1D15I00bC7lsM2GgX1s0o62Iwj6j/6deZ1ZiCwBtmmGzh0KCdzK/qSxCMHjC8qBAR9tQhk\n4mPouLUTQqh/4hTq4ku1SbVCqI3ZkjKytxnuhq5akCqQrq7Xx4JIaoeSH4sVIsXN3sfWGc7Zdh7T\ni+pQhzqsbkDGV/HO8zi1aJ0mPesChbkgZCI74tqxqtLgFFdUJepfQtEynJ7h7I8ZkfjccYsS3Ohl\nNdLTLxug/y1cWwWXQSU0L5+Z5ElHcoJH1LfwaUMungbZ1U5u/8Nry2jURK8LFHaLT/yRSn4Pg9fw\nuejDkeRSbGy1MMesbWXCO/uT8gOA9JYa99/xwuim3E5zGDUMaJWKg8WBZVyKEpY+KGjBFJOUrtMj\n3rcJNY9d4slEqcn2wDzuKUIcttvsC70XG0awDYSDQz2CYfHkWS5/uSF4ALpgjLcBzwC048jZUueV\nviWS5VudzFvxXLkz+NbWjjiE2B1O4wAGgrcimGJyiRUvU1wynIl9r0Qqr8iOCQSA/p+8qQ+0ZvY0\n8OWok9uq4V9RixaeLSckAEEGfom+KfvqiTv6AE9kw5848t2IU1HTaOCavLmA4A72Vd8XeLeqVW3U\nORuyyYkVjVxZLFIiWhx6jaF1/WT5jDluydog4xcvKVb1cwhxfvI67EmnSWsmK+xxBxA1Sdi7WWnc\ndkJLSWmQspe6eQDylbt/PkPSCYJz6mJ1PlmhwCT+ocHTX24eu0oRM0yobEJ+3BSUeR+k/u097WQl\nwq4+Q2wmmZFNmiX5L9MdI1REqstsyRBeZ8mabMRSV3ztx9WkA0kiru0Z+odw8re63Z1qNv39K66I\nTndTC3lMVLOU7jlDSzpqlgvEx8YKdGwtWR10ffvObGb67Bs39n3fup2O5Qi1hrrMjj0BIo4In58J\n8LGbRJzf7MFALj6nevF6KLhs0HBXaaZal5m62IjWRf2V4Mgj/ZGFih8cnTIM6QHcU/FgUQFPePxJ\nUFklzOMkiUFOiXbKDmaG7rsR9wcJTuZI4OH2Bra0GYY0KpgYcjeZ8INrWeiRUHCuEdkTH4UDhyp5\nkd8qBv1XPDMPgRjQcQXR6su+W3Da+OSeSSDEz7Jqx0ORWQwANUskxJVyC8b+ewdldz/8gCmU3jLn\n2vZKZvfj6KayKRHK7FxWrJokhNjnuKUgWI84ehgXQFuuDHRJfsvH02d5LM9+D71xfG+2+9DfEDEM\nzsiw5dAyaZX1pVpkXQoCukJgESE+6q1hKi1Kcz4k6hy82Eu/uov1cLMo7NeNKQrZHJ6lX//AvLfO\nTUpHyaByz2otzZmpVIAOL5/ycXUC0C07jfBxvL0sQKTQ/J6GtD+DUSWCHZNSFNqTz0Sf0KmVIyEQ\nt4myxo0muliPnbEu6LWT/DYOv7SzJafk1TWWvnEHUrkRmcqohZZisBgk0gIpe9nRRsFcWAwQ0rZJ\nr6DiRpm0z5qDe5QA9XauzWq8kyavTYLromTgMFc3Y0S0m9YSuzqOWbuo1Jb6MGD0y4CrD4Wos/V1\nnsoQwwLEOtso9goiwNi2drd9k2vm2wmYUewf6sazlvghzXheJRjDrXQIclJ+sQx8ho5y2EA8Ic6t\n0rw9KrHa/tlPwPMY8w39fnveTmcgywMtLX7eEIoqb4HpKpm8TqXczal7spNuWhPPe4J8DTU9T3Hv\nZFy6kHLsLwI97vN58c1TNYlnFDCCOmFUkoE97iNuWXejagNdoAKEE8wtPSGH8c8YhdCepyPwtsN0\n6j/dy7KxJmuxggcEYvS/1HBYgQ9IQTgGeHe+RJtjU0abY0fAFTcMKKVkS6VdimguNoiWsWPhDf0T\nSQwbwNsrU+9Wtk+St0Ib+B9D5sjQuAl60CS0arfZtMR1ZGkp2AlwqMlXL4vaFfD6+0cv26jC0RcC\neuQ631uzlivVyMyfaJW2a9/Pad+6aMWDv0fgd0t6wS3X7Vw+GHBo2jfevvFiiEvaY+OWL3LXWfDe\nWqMN0yntP5YqHFz1reseiRFn8klauOW63/7kJQB+WG7swSJKND/JGbeQfPCFMEOrNpHoGrVMfmIr\nViTWD9s/E+x2vSdqInLC12+lG30LYxhcaKGGtog0wRMOFziKHHGkxpgd6cIFalUPDVmH8D4Z0qYw\n0EmoZQBqSKVUt0ZAC6rvQUOtKdJHZHubC4++dutZAVZmAW5vZrIf5aPYUYMG7yyuExnDIBf6o+fO\nUKV4G48uKd6r+L0b/4kVosCyhh8DQ5xPibzLg1awGZHznPhqhCthPUNnuweG0I5j25iasRN4R/se\nvidCKbQjy5M1KyhWL2CFqpN+LIkJ4Bce4uGoB8fJ7Rex/UjHYfduoWEsh7Lz+GgUto4MVUyVg7mk\nsEZFgT0oLlmie4VzzARU+ngPfgaDftJgrNaW92UOpVa1AxvwLiIJCFPT5oNV9UpDfoEBZnmAcFc/\ns72pZNIMZ/6PBd7MnAAE3JJbkIUvr622GwGoBDkHTSTzCuTXdcAmpuGNS6qzrsglL8GIEnq1azaB\nfLcxBq20pyiPaf5WzT4O3YJFPde+jrl5bIi3nQ/xIkrPgyaixO+9g5ws+vTuYlTdwV+aw6Z2Eg4L\nwTCBB92MFE9JDAfYEFsazggJ4c+CFEGftfYuh6XosmP5Fk2EHNRIzIy1GE0uFYNCr0HrKxcDU8Gw\nvwNinbs1W26C6/mfEoCWGhtBEgXvy0fxpOqlczkT3MzWVB1H/3MDHhQhbdjaKdZKrhbyPefTM4mn\nRUwg4H9UKqMMxY8MpelKrUSjY5Rhn0E3IibFJGNmP1Km6DfK6Bz9izzj3SlBM2tuyc/pK8pJPybn\nVY7xZ3bAQA9TCSrYluNQ7Ku7eTeKTnQFanDf+MV6WzCmwj/zQon1Rytur+gV5eyhsYV7rt7bFu7h\nYnzt9cTUCyQWzC0jEWUqDg4dVnDKcpRaT4mZghot5rDxL+LgRbGj6bzvgkMabT8xpkNdlGjJN5n6\np9xZNBlZS/KMEkqIjAI1tdGO29hkLd7oqYF274ELPP5l1CvPBr1u0PgGilPa4LGW2TNx1mBux49h\ndqlUUJe1nIq28DPuRhe/YqGf4IUv+bihFqfjdOoPzEDxijtuPjf71rL2EOjqhbOBOoJS3H6yjqoz\nnAgVC1go6wodCenXIqAIQg78k/lP48fYaqhu4Yaec1dXXV8UyR4Zw2pdUFtBABUjWJbl/a6GZUg6\nFQ6HA06wwYXpfwivS5o95dfQvMcshAMquaE+Uk7t+zpPrFxLnTITOGafA4+vt7+zSiC+Nf0FCxTb\nMD3JDvplk0ljylaXpR0/mYid+K6EEN+gcyb/eY8i6/xTRvPt6GmdZNHeibD65PVZ1rWqBgXTyM3Q\nq3IIpyPJkJzY+dHBPQHcnUE0Yn1Ep7IXmnIy86737wq6h8ed84H8QzVuQtKAjWD0h6Pdq1/8VWKH\nQf6Srovz5Y/B/hEnFO80ED1zrw5kP5jGWIK3lzHgPvOuov0d34iKEWXeDA1xSD1h5lLNSBvtMG/n\nYgutmfLDuIKlg5CgxoWNuDOxK7CQNUvrtTlyRBS4cdzErCBugBmCyvATG+sl0iNPlgaSxHyTegVY\nCF1lMIotYzUCPWG9W2AIfo9xEq4BInp5seaDZlWAueRWsSVfIMuzGl1plry/Zzis6CVGs0QpntlQ\nmXpu0lGftlcasJEbC/EZNjUkOcZvVxNtpZdpyFKxmmejHkcvJmbKiZt61rr/Y0W3No1XLwbUfIhw\nXObmHdAFsLR98O7EhfpIs+e2Ii5vn8lYDmRa1gYK9IFj6Ikcd70mI9RSPhgpQgQn3CW0vX1DAdVv\nHYU9u6ThKMw6jlvFyHneAkBJ/NueXZenXLAhy/NmfEin02PEBq8MvZGes3LvIR6fSlYm2JGR7hcR\nscNtTbmuyI20CfzH3330djQ/hXf+61PlvpLlebaC6yhnnSQHSITI0pUzl9Ao2chkGfLIv4lkarzf\nVvGKA6bR4cLQ7lfMSb3jiAK/QFow/pQOHeoBGpiIJKnyfBfm5svJ35ns4KrF2u9yX68kHNn3GzD3\nHgV/iy4tNWUmkFYbPbbXyobnNbXNQtZOX3Rp8AOG9/Oo2SEnX0DhJ71qKmWpcbp/1BYCRfkXHiqC\neBMAYFNqIsb0UFGb4p3NWy607mqLirPXn3hFmV2MsgJ+JIeBuFIfOEt+uzSoD8KC8tMwqJybtYlH\ncmA7TusUFo2YYZJEMC4hhSPr9Vf3cxQ9FdrWuhoeFLtW3XVvlHvTawERVdqJGI33qy29xmhJ4nz+\n7/wP/l+gt5FG93Ni/8IEm6tB4obo5u0os7Xg7gmEy/6HCVFtfhNkqZyn4LTI6fi3wnIp7HIJWPkw\ndHPnAy7Za9wVoP70xhJbmtieW3CdDLEwW6k9qRmo91m35ph+NUrp6it8IEB3jqZbiqJOrGid/bGt\nDRe3ZwHQlGMqCSrGYYoQkn2elADRgSBi+SEBmIS969msvSUdcffrzFh1zgziOwKYJ7A+zgPAV5wQ\nmRIYCaCueGXcq3+Y3dqX6Xz+q2Urhdjug0VcDF4LTRCKJ/z4BoxHnhPJ0Kg3E/XNFOrxbodTy+V/\nf60jkELut0u9bDLnWv7CI3wgQxfZmbDzWDBBq+CqS6nFL3lJI202FIRh8gHqVyCn6QXFS84Aps6o\nsVsDBM31a9sYV/0IJ2eoJXSJWJpMa7JuEJj1QpCWgKPuFUqL00RmWetqTT4XnPXnNJc2l60XGhY+\nAsHEmLA/EUP7dssvL1l19DmPl1664WI9yN8JwrKMKIQIyQpp1lqKvA/uD8KUtUSf230Tt66HgLB1\n4j+idT++O+33nL1aQTVSDABPdZnV8MsvJ5W0oJhM5T5tvoPxWS/TY8Ok/AcSZOzeVYeGdZxwfQ2Z\nG1fYvu+0B592E4wGHMgZbomABjWALpDg+oDRscuswztBlv34wRiBfRhVq0+xjopYKqaMfRrv7Add\ncCpEx8xtg5/R5o61oOJlc15EqnvaFBqF6W1GW9eHl6mEvxDHkpVbvS0Z/XxySSsBQ8B4OtJjUiJ/\nLgEnTM87J2olOEnHHN/z2It2S/AEBFqRaqCJTXLb/vXe6gKekLNSu4qO/5RJpTms5R0vX/nwTvkl\nEoKqq2fRO4WVPGePAka7NO6i6uTxfoUXzyuckHg1WMvjj2uoW0aucppzCJ18nGBtTTqK9/hidxWo\nZypCiHytpCfX3S+v3W8xlss9vPeb8XoUbPytxfgNsJhLql8YMcldO5pFm0jVazvHJe9caPj65/6a\nmQNi5o5KGRI1YrgN37NHqaYSj3ig9w5K5r1vTpTim68ZUVHS2B70gveIPxtcfJj6MDjza9KDgar4\nL2j+0oCV7N5QCh+3eXAbatOp9GsqEK8NyPLDCMsTtR2UVyQpbKmXt/mmPW4E10r+zzMfJ6dDL2lA\nedhHtsi8mbms9bRX/Cb/S9SduVk3vefqeBSsK/lCxd1Gm+QXnMErrXxnR5MXNN9L8b0mosSL+4s+\nEiiRkZ28NL39wlIq1dpcgq2SObgCPTEHfwEkBROFvzkMC37TQSu9S55uWIs1FuyuXNLdBELb2ESV\ndDD+vw0deBrYhbroR94kQgadZshZY9xcmMpkOPQD4KJj1Pn9KyDfiFj1taahXAewxkfUfjsZLNGY\nj4Ufii6NpDrTkb9+WFudZyVk8IJKiDgggd08rG9vKD9IY3z+RAejotDLYRUnJHNKM5vFuzrQceYI\nE6Tu0LILRbrMcJ9tmkKRGd7VR6llDLUWRXGQFI71zJIuhxIVnSw6K2TdqCyvxxXuhHR6BrdlFIW4\n9RvXFMvEbB2Efao/7VnpBqBp5x2b5m+6iv59/EKuhg4u4Y8peLcZ+Zy2t7kQ4FbI3hmXmVxnqDkx\n/mkTxs0WH7D6PwoVvsKwBYnHonDmK161cFu2IMNNS0kzTM1oX+QFDdm8eCu60xr8VrnPYbIBO+4w\nMkhpp4qJ3tFvNXTiz+bKC9Jhmt6A10MXwDwgHUfcEl/+8zM2LF1wQIFtW71HHyjlTrl8ezgvRdIL\nd/tBKgK6FOeBmfE3j3rqlvTrC7kevvf0QS9YvHUUEBVwG/Y/waNnJizM2KZTUGRpTQrNJ8b+y99j\nepvmiFaaadQMB1pMNQYgYoxSxuEnU15ZhjWo2BAAGL9Zr/ffyHkHoBcxpYlz/iI4IXPrYCGEhdQp\n0AUwN1/o0xWBJJQ4rT1vsZOGbAMTJIKFZr0UmRKDKiYZ/n20BZna0F6r+KyX6lQ5I8WjKWsQb0Ur\nywvSrYTaMyFHYbzNuWm5oEAQ9Xz7DewoFdbX4fReQhA197aZ9TPNlFW/3EONWP9RksdrMk8qILgP\n8fx7K3mt3OICfTfeW2O9P3/ge2LbbShr1cNO7VAR6H09wWhTRwTSxYTIXy/bStPGX5GrfEswk/CF\nU1VpgaTDux7IoLgJ854i6sHqVnUtv9g/yHrtHg1maXOyWelyjK0Obe1cP+98aWZkOSQehCaJ3Pdf\nyDYQXgOINx+M/oSZrRSgRxlWuoagwzJfNmX37nHCfzajxk2lagYcEq8gAOWe6qrQyj1YyYtToghK\n4us7h4un8UaPqBlfdicmryRXwhbFdEKcqhJiCFfpce7jAwWJPjIASAEwvs+2c4dClq1d3impKYP5\nRXndnYPvkhD5HHyrHqc40lGTvcw2HG81JeEuWRVQ29NcOrYxAdZDM3MqajlNFm4KPFJ+Hxkf52F/\n3dKkvR8cy2lpV25ExE13xr1Fe91exh2KVl2IexsicXXmFFg9Vp72h8Xo01Q8Pket6ShJS9tPEh2W\neRtSyo8ZESXtb/eYmlS3r9eud5juW5xJy6oIhnMMpFVJ8l6uxv5FaAiJ1ou0EgV0ZE2aO4sjYXH/\nlaZjJA147M8OsNHMxQN7BRS7WTiZsb/FU/f6R0AEmkkVR/90sKRYYhbs9/Ms8t9vXl9JpWoAVsGx\nm9OAOq3DbfkYT3OO7YuerL1WuO8Hxfa8GjT6+tX+uOYNjyXqE89/Xzuk7nZfPdUu6cuCeOv+fr/I\ncAw+XUXFY9i/EIRBDRjeI1BGw3CRnlBTE7UUmLRDofAmzGNig+mvmR4GTX0Oy5dUisE0269mncb4\nRsxmB9BW7O8baRCKKBDNVWCKwr+gmHtXhVN/Z1t0axbdVnFEWNr39f6T/0oqPp+FourFiT6onjdZ\n20RdryNEaSOdlViXMPAbNvHyEyRNI07lZrTKLi97KNn4Ow8ASDwEYngohaQoWBjBeyzKvTUYKu45\na0yUeuB8zIuY3Yrp8y6+QOoVjbMCKrJleJnf5FnOaLLW/l92IIofSSy1h7xZmhNK/MXcDvk24kRR\nVzmT2+lbkK2YQC/Q964uZCgsHP0l3YSIAdOyHmsDy233o0GjrgL+Tfh2dHh+94MH439aJw4utIjR\nAudhAMZsqLck2OudCxFR9GkgCsLyR9MbzZrDK01gDt94e2qTBEIPYC6QIebeYJCz+bpTA8Qp03ej\nDkBFKXUUn5wrXP8exjyoIpkZ81yKHXpx+nnRQ8t8REAa5ypIf/UOHBalatg6ZlJW/PQs3YKcYXBH\njpMLoQn7CQZpg6FcLCTIh+twsBvnEf82dwzciuzXY5IOPHDNd818QrYS3FGd8m/lytyweVcBWWfq\nKoyDlZvYKNGbIWvieucWEaIL/GpaV0nej6it6vpkx1C9mcdcpxygg8EwU+Q9TqebsjMqdMckx3YK\nPNUJr8iTsrX9migJ75RE6+w9+v/3EtfZC4hW9khYG4ehiG+M5NeYVqzRaSnGNxTsZOb+cuV80hpM\n5kbrEgdq80c5e8zHdush5wXifTorS0vHdVzUercyr8LwVJDJClHoXRguNTqbGzfRO0h3/SGvKfXv\neJAFBsonKZpRfnFNj6KXfSEdlPLoKKr2x0HKnjYHa1O2nFSaZezwMmf4wazBPQ2DvJ9Oiv4B+cSO\nFrAB8wovlgGSC2XpFWY6/J0v8c/0tysxdLZwUzGbu8dXxS/imWXGTMMPQdZnRxoPaipn2kWbYnTF\nnebNrre4I86/E/MFT8Y21DhVJNzRNsoxMZcsN+xeVxgYBgk2vEV6p2llC7JNVbDqz0KsU/V0rsyI\ngQm/Dv5OknCFOuVM+YOoAwiQreo3nHHdWbkeKYS42sw9rv49O4vtL+QtJG7863L8dumpAYndpX/l\nz1Gp8vM4OrhYt6Qn7Rephu5lrDK7nVzVXDshoC1XzCI5b+aWHtB3iy4ktbPhgW1yln18ubd3/WsM\nnWrccDeq78IHQn/pf1Q4C74LUgG1jkid0dyecwvMHbI2ps7Hu6/9Ythx+yi3qypwYayAF9fPpugj\nAGgFBNzwnSFWMu39vT/o0r+mz/sOype0lCGpF/4pkMi3rVRSG4O0wKL012MrdqPUvL8lCYvmJ+E1\nYJYQR1F3oyY8qWklcIMSIXeGynLJrVEkY8EVdyDlEAbLgd+4Ytzbm0tUG2XHH+r9NCOZkk/N67Jq\np9I+cnMfr/AYnJAzABJPqwC9dekyl7KK4usEpnjk4Jst0Fp+pfNlYFododZooqmxfvkKJOurqkwG\n9o37CP20uKhZzJnqTGNL0BC5/ZrvTabulqD19dFpDdg6BGd4vREAAd7Gqp6jxBTvNRQZI20d2BuN\nFBJ+8CziDWG2CsBdoGlI7NdjcgZdBsO7bvCNqHFa0FqWkby7BKVuAVekUAfX6RitgHKugIXhgtL6\nsKnV8v0tfhlaX1xc2uSxePTfYsMtMBEJrEypxsk7y+Exof6AoIyHBZiBvov/hxU7bSHu/nrYNAtZ\nJOYqBNYGMfxaAcOYVe2Vg/UbCHFlV2HIZiAy/gD74Qg8icJ8RjS1AGd7t3Dk0zDERWlinv09DBlM\nOe/RudF8dTfb1DI4g33vSu/OMHm8yscI3GVxGRciorqLX9YRn0ji9noSlSo9389QCFCp9RXOEtub\nh5gnB6vSUDvEZ+umw/C2GQsl7N03vY9FJEOftg3+o1uQb4q3Pcqa+C3kv7Zvxa0HYtc5N34lWXIf\nNnfbCOdcO45XUaPen+411pPcsCybMS7vYf2boFvZ5C/oFH2fxWLeYOEFJuoD9ORHIeOGiqq2yodN\nvkjolfq3C8HR3ywAan1BP+qtapDuBzcoZheHEq//WJnF/kqoQNkhdeaqUGZTcPEd+ZjArKCdPj8F\npfYhhpY4GrlPpFnwlw0oyYNN2yH9Ii4Ym1coemVDC2afnECWviSn4y8fQLYRbVdrdsgyIHaACUNk\nwyoVtTjt/lMYUFOOpEZgnmcn6PwT0vtrvcW/0wDZJFx8FT7Ju3V7FVxSoVhzWr2NgXApggby0G7v\ngaBBC5iIzSJRRAkwOibIhjQGupZxxESlvPAZfpeWXxnyA7YmEHx4EJy7vwEUvvvnwMK4pZ8RTQ5t\n/qgGTww6jntZ9YLCNz/REKPFSVaNFPCQvQzf2PNJdPe9a7OX+C3idY7WlhggbaCeWfsFQFq1n2pI\n1Up2Ju1qCayXN2bD25j0qONpeVV2wMTfA3/0PQvZ7NjulQy45kwFLhjrHKi1SZ3Lo6IsHy1W1lzz\n+T6kjyQDgHKEPxmgbKEePSYFw9m57IRBSB1lVL/lXhgcp3fV8iFAZbUz9vPdCXYkSA0Mnop9p9+W\ngXFiq9fxsGvjlhzNzacvJJ4lNuEZy/8Zl9ywYYRILB/hbw3jB6T+Sl7DBN0JfR623qilI/Erkl4b\nBmEHK10J5v07/+2OoHjVtND30VN83BbYkj0GCA3AG0xNTll7Mqce7tDOC97j4C2DJqkJ7bLpOw/x\nNzvjLevB+tOm5fHydrs1fHRGOLNpTd+tNaXzZJLicRPAQ3PwRCU/KhfUhD/lnwMquRemNah3+9J/\nWbDvDX7y5pZAwtFvTl1Fx9D64CTBMDRLvToJsHMW7TNnmchuf6e0UU3kSMZ7Qh6GBQTbWX3QM6H1\n891oVivzTN/iAvn7S3PCQMqWca/8EwEySxPLhLv/V+g2qU0vWgmRAwgSZGW8qhB+hKiyROe4iovT\nZ7f/ATkdIc/NU7F6uAOSfbTF5HtIKkHTtrRBh/GPODrZync/1Unq6XicDyUoFNdJO0otZpWg0UJr\nIm0baDbtDrMr2nxM3f5NWpkThFB7ogT7J6jP5Uk/W5gA92yUYXraImArkXpJIkzrMVUBcZYjVXAK\nby5IG+0dAnShjrYUMbCDCeWRqd23AQ+Gmib9SjRAvoyzqNSavj1SBCaFi+GWhUlDEzJRjcx8ucq/\n1O95KAytmC/bzLw19wV7dcHvXpYXenZdTj7NIqNvkMdEFQQ3W98i9NwAcYtUOEda+02qLkc78Imt\nEFLSJZ7EKE23BqprZuOH5UTGjH+bdjHnBephoFRnLuwZvF0sPVHLCQz6E11Kl8x67Lg7TMz/JMGy\n0QWWJno+6E233Lt27bt4uZOF4ridnseWnNw42Mojo2ZkS+F63DJcZlmjFOGUVnis87CHis7eVVVd\njVZWDDQ6Zn/wZ/rKAB7Nj8qRVs4g05fCKKzodda4WHnCVF3g3nZA47sdOjb1VGpJCwXqP2YcpkFT\nTAXPnPquxGaaGENiXmKqa5xdskfuw1Y4af7vm1MqI6lcPOF5TxhJ1Qtt53NI+69mG9IdHkpVNj1y\n/G16ztIE1JNeEtmB+BYO0mO2X0dblG9J2YB752FGSgWYV8EnXjP4Sxw5odQw6Wt5LGoLlfylOGcu\ngbhuMJQ7pgb21+gJh/ngTUpwzKK4Hcn0fA1ilriMz/e+CfZFP2IgWlQ15Yt6ECjl/QAX3aAyciLi\n2pcfzoq/Ic7mWuUiwcFzJPte9OngUghbbaNHB8SJIMiopXVGkfr1KtDxrZ0bsWfVaqkM++xgcUOo\nbMQ4UTmjeig/FooIwVWLCwUblGVHyWYAdVeIh3843mflrTKFyQwuXMISN+lQO4i+WEPWHPkml7La\nrjWlBEditPmyzJHe0W207fjznpN/km+Ne2v/R4elmY9pdqL4KL0ubbaOaZpAvlxlAisoaIZVPDq9\nF4oUjfoRR3053AluL3WEd8t1hWG+I5767HWYMG+De6VQRXGb0aE+8M4o/vBinyggTiXrkFS0wkPm\nPSObUf85seJ5x9gm9winqS0b1+5gIKEfpDNZNwf7r9+HUqvigZ8oPVsbEWjjT5fm2TgDLUbBVrT/\n8eMGSj2YLSsfViqir+717cLXHWH06yukH4WjaOXbulc7zkI4iHRX5DuvX2hDlEUCXju37W/7eyVc\nJaxXcJsw02ylBFhVwvLwRDiJUFT4s6tL3oofXqp3SAfLfm36qZJ5jjLjKeUwjot1eGA+NroRHqH0\nmgtjvwYrR5rVyVbWrYwo34eren6W2O7//yte0mey6VJb5UQPVQjQLDyFHJ8zSG/AiRjgwri3tDKG\nrA/0fUOdQGiz+RwQmrOjtDLah0oLdcnKNGdOuYgfRwuMR5kqO88aRVVDccmhnSjkmckLlEa3UbW/\nCCaLOdPOZVG43P03loHDBkump67PWIwSJufgTY2dzbjHQYWFJH4Q+HXVMJAaKwMREVUD4RfgA8lA\ncyJvj/zKyZAJEdF8EP0rk8ZsS+FplatlugSCfQVGudYccNSYpvVKtoiX82LcJs9S/HqsqzCrhkA+\ngDJEbI+8wshtd6KxUXstlXRaPBq/JYp4JESRJqGNH3q0MPWYudy5IU1Ex+Lx/WqW4Cyt6RXnulxh\n7qYgvc/1Li6u6wA2y1x1R9g6qBJDOmN95n40iDkqYuToeiI3oC54fxAOfE94As08xEGHE8kAaOta\no8l+uX4BdtrDoafhBf2VH9N+GTluvEe71ZT3DlKFjbKEsaA/9rj28XJic42JsPn5qkuf7gWNqSA3\nFkaQ68kOF/xwL8BFwUA4I1qpi84bn5o2gVQdLJJzvEHtIQTGmhCc685iDeCUbdbkw1FT3EXdEz7K\nAXzeVmsQTC3MSoefYgbwhcKSCniWMFXMwZCvqu1o0KOypwDjoi5M7wtwWyF1ssuZ/ERb8vFk1TKq\nAckwlJgpVQ3g2JcrjBwdIuAb6y0vpTto8iav0v/pMkDxrkPHa+5edxeg/bR57Dg9M9i6T4QJB6x4\nkkfyZ1w2jFGdyASCxZg+4obC4Xahrh5rvE7rpL/jAt6/JytixqGe85/NdmqycrPD3SpHj4HG73M/\n62NrImyUrHvAP/qdOGD93JyXizrcbws9HXLDfuK8gmZx0E+Q17Eq3ktdG6Im54bdQOOQJT4sbOhj\nwp0PIO/22O0nZVQBFd4Xi2gytLXMo/Jexr/IaEB+IOp3WfOvck/ycksR8uztlg5RC4mpYN3WvnWk\nebkIUPD5cYMCH55xQdzKPFCwCayAb18492wALyccze3xXGlUZkys4O/HRH1NCzgQIfHuZ2894SrB\nXxp20sVF6LGPOCfyBBGEGgpXlUGNgf0lYkUvh1XfD0U/PLpxY6Ms+fNecyGrWQ9Zboy4U7deDa/c\nlDarHQTyrSK7K96Z8gTxVpqWF2ltlrb64uQ9JW0doObxUxumbu3P+d4gfnwFzwxOKVzdeMyxe6ho\nV9G5KUKsBFPZpOaKb5eugVmH2PkBA+lWZFeHWTgOtJYCBZZFv6u9RSZ/ohBhg4bYVotZCYdVwtqa\n/z6XJaRdUKc7E7h7UU0qs4oLqh7OeCHJ9CIFiz6fOTG2ydP3O/+LkIHXj8M07BNjV1vW8hn0jA44\nf2gzojPMkX9n+D0g3kJXmDfyBJzwNG5z9hK2a6xXRgJSRNSGNPNF8Q6IrUJsBaTi5m3lrKedv+4a\n+kNlozrJBXuzvH3eArtARRpnLD4jSt5HAGRSE872rEU1XwbIxMO42s3NXr4zBQu92AdAFd6bfp8H\nb+zjoiUSdpFuOIqfAwt3fxSo6+1wwapPzNlUqHhMfKTiKqOukaeKPDs4E2PP8jHXvWzRb2W6uJ8Q\n59Dysnjtz2acTJCJW5hkHDIlnjwva90WF8hnAXeWRF1JN46CA/Rg0lzvNiHK/A7QSJo1H+8uRIpt\nkR1XM8bh3jWFkHTzVyHdNqPl8PnAjGBM2Z1QeXZJ9UgtO2amnqcO2uhydu4FcnssdGAo19p0K1h9\nDAAuNoaj6+8g5By7RqQpjLssbVgkTyW2vgACzh9kZEaRaGbIVXc5EbiZ5jUniul3T1QSfYmNpXEi\npsmWjHWBONA4r1AG2GokuJkSYdWmkXcnTQrzbNJgVbhz5k2/PbdNRU9yiDX8+YBKuaeJO8r25UBX\nfErFZr5+j2uKwIwBpHVY6ca2PRs93wNUctx+wfT9BmhWV0KOrESlVv5+etnqOZyBBj8AOy3jNLaJ\nMW6hFuSWpjVJiaK2u3Mec+zcJMOqdTpeebSCfSoa0Jv9KeSoeHd8FEP+uA4+6ufZs85JJSTJ6YeE\ndD5VHAFVYTgP7+/ydJa7bnw+leDGzHgOlIsqlASMGbXtRLxobUDu3rtJKrKLvzuusyGTvByu6ANW\nFoi27fW3leSO/k8mEYEYxDviJtlzV2Ew4DCZwlCStk7F60g+hqb8j7JlX/A4sZ7jNvzGf33+oDoI\n51RkUjiaAWH927l0Zax1VnBHHNGY3/aEcP9cn0JNLWqXOPEZaDG2AEViXc4SXglF/zjYRvSsh4jm\nlZDf+6JLapKNFj/U6WOaz/1Q+jnLOy/4jwlbGUui/0pxOwjO53EiIb8+cuRNv6lgncg4kT0vZhYU\nqI3kiVjWCqaTVYo5J0mDy9VOufJyjis/Owf30YbzK8tXhskSMnVGCEYaXysqIegIAPK2MYigbHv4\nYgV5UQNE+eud1015tIvPOBOxwMZFGoZE+m6FcD/lb0pip+7XGQHKbLnWpuM0J0Wgyt2oHHIWuwcE\nZmOznDdt9PUrecb4M0RmzKCR49k+FFBt6PVGZKkTDAMkfCcLL7TnyDp2ufoPjXYl8eFikpZ76AyF\n0O8LbQMUnC0UuD/IV4loxCdPwND+BUaV+xpgcTJLITJX52+GBY3Jx9Hr10udTcpWA4zkVkU56kah\nUtNfcGDqHyPW9c/wdOsB2uNwjN+kH1WUsm53Gl6HdZ240slkKAY9WBm70a2L1U39AWs23CzTZB3W\ncq8nSDk+xg3/2LqE44rdfmqjx4dlr74zmxQFFwnzD3CgIZWuHOT2oguHOTgfrH5gs2jT8m2F3Ksn\na7VXwcQCjVrzGbUr88rB6mXeoiM7Ax1aH9Cg5ObBctrpOejx9vBF5ZDxray1IgUot9VC1om7YIY/\nVdYiLhpe5Id8gygXCI2InUDOPutyjOvW8Fy9xpQOZxxhtV+CO6VFfW5C17Xsl+wBOcjKMGHvDGga\nDDIUGcFGlg/SRkMWBD/INUhFIG+AHsUj8zdIbmx+mIJGl11P9RlN7v06g4LUa+/N8sxmbEpZ4TCV\ndgfWQ+O4OMNl0uOoqVFcbkk5KySct9h8AAiRe1pApC4TpbbFdrV4F01uMNDu9JgLSfjJBAS0Wqsr\nWVP/tTJnBDUHBQREgEwXmUZaPmhI7TTJG3yrXoVrmGoeIH8lJRFxDIAT0j69KTSQzC0DnH/ZluKG\nlQu4BEMiQZpzAf6Ctg01cbuFOx9ZJlV9SQVOt2LtsaxaejPLRRq35SRUoZmqeZvHk6kZnx2JVutr\nb8tHbXcf4jY/xYvfYEFX4HOSvaOWoKQZp62bHLvvIaZSQc8zzZD0dz8sUqUONgaVEppfuM/WMImq\ngwMnGFhZ0DpjWeDdPEdOvxllLjNCBrJoMXk0NoZQ6FGekTHCdpuNxIKZDK8PDSuh3pH4Udn7UHg+\nkCip0T+gk4au+y1JHVcNdnx4ZrQgCc/aEC2T/UxqPRVw30xYhPl9qUGdlYHqX86Nb5nBWaGQOpy2\nFkj66xmYSqUYZThyAMQWkV7q/K1NcRHF9iD3PB4KbAvRJMbfPXRsVwK1sSP7R5nQdxg+YTaUgLKH\nDnbPx89r3MBelsRGrWQJeEa5pk3C9bDfMcDWdA3j6rTLjl8ZtTsrkn+mjWhO/C3F3s6rMY0Q6Rn+\nGUA05HEwcQ+1b3I/p4fhvDdm23QzQyRXUY5EtnP1HeP5gBk/e1C/pGOr2xgZ1Gt5FcbFfx5pvFJ/\nnG1+MqwEwLebNnBzfAgF/bwPd6KiVEFV7PU93PgbX0q8GDHMCYW2pi10p4JVorjoZIwsHTSbH7/h\n0RWSB10CY8WdocmknRsCcU10+X4Epi6ym499noha9lvBByhG+opGOQ9HqG6t/Nw31Y7U4uNj2rN9\nf7556Lp1BLOQWsAVDjQDMgRAKMpP0lfriq2XYSglbcrNybGw0AEXMX6CsFcW8H9NPxXpBk3Grt85\n+m19BUp6TYd/OSiSHyDJee3n0PlTXidCCSqKWx4eIo/SdI0d8MZrW+5914zUD/oLyNPK+gmxbd8d\nmQU2UsCClOF3pUxgccR7Dr0Ux5C6UlZBHhoIRS2aDhZRobZFqzrUhmSxSHr5vamn4txkY9JdG0PH\nntWgNn6Eih5VFDXV5NS/w2Ogc0JDHow08+Dpgy73juN2rBZhn9PVf2oVCw8uV0Wz3NN3GwV21Iuh\nzbdb5gaBvL1+lOE63dPPnCnql8P6/E/RjCAAv0pCb09svITM5W623E7wVXV35pVGDycKtO0rANJC\nQViv0aGls9jehkvD+pNfUKog5rxHFMRxGgeUB3fAI7Ml1jLS6hzuKKqBl9H5kI02FSk0Eqx3sxWO\n35z479p6mI1+CeKNkM6R5jdFKLVcux2jWoWB2T5Ze63CdwAGjTs3QrXiYTcYkJONdHNe/fgs0VGg\n4zzkv7AXoIsHn8K5HqyqoW1X/r/x3Ql1Bc6mXkOmRkfa8iEXsTgSOST82UU4r4lfHCjjCLSi6Sul\nw8E/Aj8Si/TOh2y4xv8OmJmuKbQ0YxIcbZU5UTZyvwtJ8GapX2+DoPhmVfJNjPYFFH5PQvehmwmT\ndgx4rhZxHqkrYO0lOKg1gMR/24M0cGkpIyzMExAGK26SRm2HjKlpXOdwCbft4y3wtruYsLHuNDpv\nrhHUu1Akv93ikJ7v/ghFHVTdo9XGJZVxl+pFQmrNu8vD8mG8C3OQ2TlAVpeqAgCCRYX+Ly35K0a3\nhNoGqO3Ul/DkyXYbdwbctWpTC8zn9EBzNxxwtkLhS7psDn+TWfDlpP7Z2XYi4NVSBxVGgapS8yzY\neSP6L7TD5HKcQnLW3CBtWk4riZzf3thpYF7RXIs2t8iL53IdB2YkikGsMu/BnvPFFJHPF1XzpTf1\n1GAEUNn4rbgp+h9xj0odIY1m7DYoKAwduAZ53fF5TtaY1gklZfRtZdP0qJISM16uWVx0VPaicdJt\n8l9pE5rmK6VJV5bfkzz+2LeNjen2iJLIdYR/EH8nmjzGQin/GKIGlG0XfNknxNRKkiyE6KML0hNL\nRIyzOK34XYuE4ymmnZzgzmS4uNCtg/oB4rw4ZQ9Y06fY6x/M+Aix7Z58rE+icVHft8BMDmNIOKC8\nfkTIA9WfdK8QoPSfZ9P5RQrGQ5YW0d1wRWKqNIYvor5aE0MFS5N5p8rbzdGtjMIOspT1wd8gmJgx\nv6NLOSdPV6P228cpNZ9cnGr+8M7EerdjD8xUTBZO2e897RQUC04/6LIJGqfBFKWsgDGv3kUXOQ+t\n5WOI0tbmSVFDavJJmzz61GPMnT3MKugw6r2yqhX2Sv2A2P6cEsDq3MmgrbdWs4cvzQsPMclNmgA9\n26joYmlJsUz0ID14LLYezi35HMN/8znhYLYkk+iO1Mxt+En78EKuPjQA+XRu64aKTT5CeK+icB4G\nRDq5D4mWKRODlLhEcR4vJWer47kF7ZxiOPFc4h5TvQJwX8bV9+ttvSgdTDv6+7BoqmYGNDM0KrbV\norA4ymoZH2IqZevYvXn6gs1t83upmYS9E5W553qp+pVav6PxGbW4E2DNmFtfbK22PZjn+NOfdOnC\nZRnmbp0KjISOxN1DplSkpppMGGLEvHhS+99+xay1wpK4NXbskGhIBKAGDPQ1M4/JnLB2CLHZfV16\nmYQjktluxwp/AyDDJRPX83Z0DnyMATsm/SpFNKnhxuVcsUbnW0OPH15IYca/VfEJ9ZyQUJv5hS5u\nbua0je7G1Hk2mbj2g6L8ZxialXajFTc5kaTCPPOfUCYGlJd5UCXUSvSmZS7UCzs5qMiMNUzQiWfy\nN4N8YDSPh6mPXPDPwPeSihf59jWss9LgWf0b+r88XS5VsNtxbMWFnfrP2SFOStSXfMK2MSP3KA4p\n9vOyrwrXCe37G+PfSql2gEI5vis13IlRhYKXzyk4Nf9zHg/l5vWsR50JJ1ddhKx0YeL8cbiAv1AT\nlzqGBgZAOkMinsVyO8qDWgByqaptxT2sPOBxUaXx1ZoH6h5A3bjlHG0iM16TAZ1BK09X2pDRiQXP\nEeUGB/kTxxLiyBK3BciO5EwCvaTfsVBowIZyizCoXrKOrNeGzAg/E3tOfvwHDk37f535YZvsMI8F\nwsqHEHicB82TcoXVK0yya49sKe0nkMmLcxa92nKzKrkeVuE02y1f27G8gYA2JKmh34DFLfoAf42c\nFiidrnPcZcHRaiTwb7P0kRZqbZFb0V8OB9iDZV9qQq47ZGq+OY541WpW48zGqvLEAjH5req9LE8J\nt5VJU9g7kzgFlQVS7vH0yKnN6X+gZ/qqVtxLYJl6KtWDQw56F3VSxSnP6BXG5FtOsWc54oVxmYJg\n3dez6qaAnUYYagtXbljgpL06Z5uRChLxCUJc6O2wbS1wxckRA6wlVAPpxalEACteY2ao5goDytN4\nb79hN2WqDvnzQFBvMuZzYZcm/ZMNPXzhEnTWHsD1mqxhemlFhPGocUPxViD0lvgbYusbzoT7Ze9i\nmkasjH7XeUfF4Ov3bAvYlZx2nWoqBXhBHEiR+g0UyegKKyevU19Iw1Iu+2D/7Rmb51mkq6TRezIW\nlmmvYvKf3I/BCjmHxYqsb1fyjUK6p9PgNq/QjqQO25SxCLdV3eKzUCT7txEVJs7W9dJ616IFYBXQ\nWDNaViIKApw73K+44BusnPAYR1vhQEHO3MUjzrGVC+LyRDlR2UxkRbZgVxu7CMBVMJwUy9SMxYNW\nIodQH21No8Hx7ClUbssGWqFfF295RYSe2vKz+QXyC0jV6SrsytjJ/acQyYpkx6KSSendqYJdo1d2\n1QWP6k/nCG3Ot+ON23JWRGrFn7ucT31h8faPpSCebSMDmXJDnTEQDjpvaj6QD7Yu/51JkmHCN4F1\nrE/n7gHwgH31Z1giQVUKZwKRPxPTksPdzyCgJGXSA4aI8uXuOhBfN+xZr3tTwvSLCYLRWtQSn+x3\nCl1pvQ6nTXTBgxz79p7m8c40xp7aSa3b0hhfn+Gl8xdW4pcgL0loYtU1le2clNuGgmPG179i2/uu\nClQMjD4GD6BcbDzDFN/XpL1dZYglqIbXIawigcKxcFBYDTmsRXJEFTRn6SXwjrYFNLgfC/yUdNkU\nEYEtBi/0eKX3Wa8Lh9XHiXDmlQd7wsWBEiSYEEkjTTNzhon7XJN6AAY43NjalbBLcqmX5l1i/8b5\n1w+e5bzSmX0WHcyWCoThx7WABeHWdLytMuWx/fvk0uGexf1ytVbX9XaF3vziR0SYJ0QUSF7jYoUC\npqmOwDSKrcR995m9qI2IAuYp2yTCG7PvKdn4FkjrjlHuD9ycXdYWHUVR/WgZToqeinwTdeRGLCp0\nWuxVRjzkfFKvyPROUMnvRny09a25/wTETVo+crnXSjILyUWQib7habPmyEoQLS19e32CrXE3rbLW\nmoj3lJNj9vOsZDJkdcnDb7iZ0+KA8CeLMfm6G6sGBq0GFq7IcP+cwM3wzB3YrmjNQBsYzrQJMsDs\nCaaE+TlVAR3KmrEXssfPInpTbu70ZuWlwYbPGSa5utwno+AOs891LYQKTAKwcpio20sbSEnXknOA\nihNc/KO6b2ODy8dHQYe2tWc3+jmqozOQsNHtNTRd+vAt+2Nh7Q6+C1vTppWc02x703ZDLaYZiWd+\nku3ASFwZm+YG3ac0DnYfXoAVojQ00ZeY/QHoBaEJFYnVEuoergfIF/vA+2AYa9g66cZZ0uF7ITfp\nNDFK/Rq90btOenrD4sP7dYLLMFOonJlC7hAkJF9bviXGYR4w95entPxMv+oPFhKr/83KezLPclOO\na9drF25tp+Y2LRZwB4owHe3DFce+DT8VZbySR+mqQqShnb7WtuAyRLahPs6DDEEQmS8EK8jyPSXb\n8YOSBnxG7XuKnw8Lv56v+NONoGQwsgDuF5jfXRuKCu/9PeSRVSWqIx6tIjsBWQON7/sMrqDUXhTU\nP/z5b3GKlIrmN9wVF32x3RLsZ0xs+PeCpcnW4neNVzSi8e54CQQEII6q8yun0SBH+mDXxdw8+jCp\nI/hiG7Z+NuoPlKjvPFqWF8yqddQQ7LmB/oQFkrAYwS7cONCc+g+9R888UG/VJjYRWROlwD/VsMkX\noBwb54pBv2OMxZVFhN9946P32mF3Gm33ssSRTTlY/TPGveeiqD1FtepBHnRIQ+XAN2eP5cd/+Rn1\n/awP0x8ME09OdUhn0XGgIksd+AziSrA1GkKiikudfGzQvqj2a1uwfOseQosoXcGOIAY4V+krSmPk\nOvZXdc4/dvSxXfv7EOe/i5sAw2LCbVgprkmeemR7K/H9kwesUv1xAyy04Ng981gTa2Pw6XgyzlR+\nWHKApQc/FJa91wXVrNLOKiLV2ttSwXtyROjDdVQx0XuxHzTJudCumppXwifst0D7pJa1KWx9iUvU\n//CF+VLQsubHA0051h4+dPLg9073kxolsyJbdjOm+kZXvKWtLN92wQ3qa4qmHE/kXtW02XKXPm+t\nDOXJIMUAp/C1tRbhCfg6hhFK4lrKvnH3jVpmKGMOi3rELj6989e9xj9HzNC0+TJ/IjS5Liw2g17l\nFOnV5xIwpUwN5tJ/cf5nzO3bmA67ENfoKBK9XHULdImTpY60ZQWh0v6dyt+zRMcMRMbBqkcxXjOh\nd2drqdtPIcshuCuIYmcAI+ODGXCFtC+tjb+q2EE7wlCZiaaDYdgVibg5yenqh5ZR7BlG8+dnaZtd\nVVqTIdwYYFgSl21aEa0TIEX7TEA5xN4H7Bma9vYgAHiOS/YacTwQklxMDXN0FXGSK44neOurRYmJ\nlexE8qaugJ4Qo/MbKfF85yXvxrKo5cmFcI73AiJm+04vQkS//MNZgqJaCj18foDt5A131OSCS+yP\ns+vMgqKRoTQXCguDOCbv7oOD5AL6YcJRTZqLSTZ2Ep7t3hxYs5wtOf5II9zef7NtL2AU8566AwcN\nBv1X5NmA+QBq6A8+AaNuk3Sk+eWNYR4r6FJbLmj7dEPVZAJFLN5Ldrsx+FDDTwgnGpIE4vgeZBrl\ndDDZ/OZ1tIflMukpwYpuLm95chxPPMgHhcr2TY0T44peWcWCX9mf/oHfU0EIaQ1trQTpWZ9UgOgv\nJ+BqUh2kD/ZY8xY3ZxtRl5cUS+d/BQ/dGNcHVXfWGpblRGcHuDXQUSgQIQ5fs96PCpEWeQrBEqce\n835ejJOjwckfqKguukrarnK9MQTALwzxwrF7qSEJOdL2Kd6E1Sj25F2frPDw775D4TTf+QnkzkB8\nuwLul0inUosRQWaapvR1jQJOzvysUAvfCRA9dgbKem2n2Ji7r9ZbpYkt5b9BoIDb6VrY9FuhpnFG\n+N7rkUrR/VFKVZmWTzc5BewyXbTa+SblY7FtvUZ7iH9BvCq8nY+IxjG3WGx/Vndxy1dMnFBeIhHs\nfpRufL4fC+GfMvJBxJxoEyfbGW5BtFbo+uqfUq64kNUw4oVli8A5tLaYd9y3/LdfbZn1zL1kixuX\nJsBhRYwWgGKxpbo88x+3FaGovmRLQ0uiAvf+lzDVuI17RFLwvbgS4MeNpGqr0iK43vohOKiALC7a\nmiUGzxMP9+r5XbhAx9Nah3riZW2wpLIp2GPuOBy2GtwBbNKd0w1BN8jfH6p50YdFZfksroMqArR8\nd2b/qG8VwPyVt1gfdDrNtiGzZo/oexOiCXWDx42LQ6OtrcjQUGL7Eyh6DV7+/QEX5gFJ2McUflPl\nHbyv6Rf4x8c5wO1QsEFWaLGTxOr6fTvfFZ+A4OZhmC2IzniHjL6OJMykDxbrGxcfumgzokHmy6Bj\ndqfZBV+yYdJaqSjRjg8TQS5xL+31qweX9jy5XPRrZjj/nPO7WCfrALdAkZCRLbM/lB3CYp7snq/u\n2FQPUJKzck84Q6brIc0yyHU7cZirWPuCCJm902jQfF1Z4eeNBniVJqMxGxD02fyvBco+zDRR7wg5\nMwKvzf9KCPLCMRDMCwvw1TZ1SLv0aWNJ9yJp2MIxp6PpsUIjg84Ne1nZTjRC667gWR8RdM1HSMvp\nR/7CjeSVYqHKN6klkOZrtYFEWmP8tS49pJMupw6rrUtfubwgMJvsVlsb7zVRcFr93LNl1H0e/645\nyXQRxWG2+4wTzpf1vlhQHumG9ELNNRScKfUtMXWH8NLo0b9JOz4DX0BYTMiPXTTSr+rVInFhH9vt\nyrLIir/KW633WHZm9HwHfVrNspsymo0wtIEabYHgDykp9IqD+mncW5WQosOpZ9c4vkofCTg+awnc\n9g9fe6dakktrevhHyNh1sB5eGeg5gfeQHNFELghRHiRSSuuaP70GqMPN6n+FgH2kSfiBn7WOfo1Z\nOg8ypRlaIWlDvEQozS+0hlB5Dt5B4dgvD3VHzllJayJgpCBBigpy4EUqYp/wW8UAINtpVtpmvxTh\nrj3DAKLlaTDm4rtplrM/QG2R2gSl3DkGIKa+oslquw9wiJUDsStTuWkX/Csqg1hF7yHpGi0gjWgp\nes0ZFOARHpaTv1eNyijqt/5kL3mS/Uyu+Xf7nqYg2sW93lU4MRunY4E3x7gVjVlnDqrH38RsgVbf\n/bAB53riBSBEVwvrIhNCLJf2YSx0dQnknNj9TrGqG7wg3siYtKyw7dITk+j1adr1yT4WF3JPMXfc\nCGCzd99DwEMf8GebDHPdamt+dEcMNraG0LlM0/vyu1DcPydE79HjWORYiwyjETFYxHgP0ieLY9/7\nbI9J0zAIV4h/SBn2tQvbZPMzROTS8cHMtYmGYIAW/DOx4F6lPzxBsQxGcsi5bomkSw3WG54ymtra\nZtfJokEersbLJNwoqItcy93giFl9IAtCELZl3/U1XZHZg9mEYTGHi+vBdcGOqdpQIlvRX9p1F2Ip\nTS+2As10HdT+ixcdc0Zilu3zsL1nC7aL+qOP83pBQo8WlmXPB7g/p+8+Whhe+6M313uinCh+X2R4\ntLcLDG5oPorL6DrBeWkOCRhppgNms0upxAws0c4vpFv1G5Yi3kS8D9QjDa9PxB7Zy5XIImLr5qPc\n+8UsRuj/sjnk1nk8FLFkVBuK8anycdHLyZlXSBldoluzkSexK2ccVW+p7pHqcaL2LdwCThrtKHPA\nTToUHml18jm/0AFR4DlPjn0Ay83jr2CjaCJg88QoYmejDgsmSwS+qrzdyenn92N8YNQwXHnOxvDI\nEX8NEjgGwejNCX+F6UDu4ooXRWCHV/db1LUmOJi3tZ6pHl5T7C3UGZrLvvGq4rqTC8dnXu7QElEl\ndXB0Jfvj1WkEZwRcfDqnNndXXvdb0+eXayHK5eaj4SRInIPnJRdtP+2MMCMg3IZRDGKyyi3qm+9q\nnUkNNue5OIeLn4DECovWjKy41O8/ssjasnXEaC8b175d2zW1YJudXn9amXWCbX9Ud/bmb6nBE4Mg\npCO8ysuApFyU/RpvYgZgCQjbJfU71XAZCVgt05sizCXay1VKVROFnEp4uljDGbKOjbHbH3gaC7I0\nRWZMB6dkGm/ZxIpiU/6RKB01qIJZr0erZoOeIK42YBb9tyTfgSvQD52iJKevHGEhXK2s8Z8x9dqV\ngbuqj/yvDnIYAOXW6DSyphyGUq3aKIziCwwukrCtLswyddA6M/CtafF8B4FN1BuIfx/+G0b6ngwm\nlBCcR9txsFqfBFL7baf7JUUA5EOboWh/ow+ujMJ8iFpfInczwga6nLqBexAosYjMKIre1kpSkuk7\nmegLJWwe2EgVBEDQ+FmrZqOwYXmJns+jqYMgk1QuPZ8jdmeZuiWEaoAqPj/BjdTnewI/MRkRQsdY\neMANESKrmSRpTRosqItt/o5xjdCDEWk8hsvMP6Bj6VQ/1SArS5QfXG+Q/Y8E1dB16ZwIFCvFp58f\nsaGN0k88w2vMwShz0YC4qI+VDEaGMPvj1ETiDId9F+Tk1HacHTQy+l8YVIKzpadWyDJUEaOHUqvc\nV/kktcLl6/A+rZacuEmYxtPG0SaB0+bzx7ulrKNeyDQpLQTxgW8cxwbZvxcx783MMKW/oQTKfMgy\naoO2bwD69EWFTjHW80RXlrGm0cI2zi5rXy1U+NuljLwFfXu458eZWWzbfGKiHRvM2eprcivaE45u\nhe9tUrWmJPNjmytP9CxzArvdMbGunwZGzfOtNt0YrijI9OLSvrDbl6x88Sqqw4GQJVKTm4/q7xh6\n8ibl/9i80mHDxOj91I3UiCwqkZg5G5zVN/4axYNihActqP41F5lLkw+hWR5kQsFBAFQHJT2SOVLa\nLUPhs1boCE42XK6Gfj/Tx2j9Yd44Qx+XdDEVSyZWuxsFSH1i8yN1NUw4ChRYkNerHAZBEqCnNdYK\nw32X9be7UtGPqWm+3kydmuOe71OrhlKu2HeBilBviVP0AYa/zkoUuFj3s8Hgt6bSKoet6LloUUgJ\nqI8wIbgurQBUaNaxNnZ6GxVO9KTx4uKjRMmSU2XP0Twz4ImN3C6y+UBZG4qhw9TRUwf76N31aXXX\nez8PQ3sgpQkm/gt0naEV3+9SFysH1BRKSrz+TOIbPy2QJV7qnWWK5k2FNjHhbbtb+AleTOtfBoLe\nEc51YElVxUKld/cOOHHazFVO/nT4EqFRiIn799Zn9pqxR1xVuX13gQXEHlVlh3GnV30FjahAXr2x\nMOWxch6dz3IBXnmtnX2n7mx1OQ4jT31f/LAhehnnyv7TpK59ZVYFQh9c8I98SXNxo7wb5b3nIqNF\nMjBSWnwLaerX6UcJ5wPGVssWMw3zOtuQjt5MxS/pTaI1S1jL6dio5/xyaY6deEFJ9UwS/nOXgjhU\n6NIeYRg1kI4nSBmdu5f8sxS7Qp/N86BSrRb18TCrGZco50Sw9wTR/ACbl/Ch93aVY2XnhtEYIFWe\nY3nQhAncBNIhNdS6reDaGsxj1G5BA0HDk9YheJUOGCxMmUG2sRwD7LpOjbl+q9LupIxRmUdvqvYD\nJKntjzxXKsvtro8LogYiYb9jU7/5yiFQpM4uCDTXQBl+n36tHKaSLrOH/W0xGbxcPK/0m/f2h/bI\nCbQ4FdopFGjDlNksSv1Y4F/TlRRs5+ychHtOC6UcY+BgwNJp2Gat9d0aT1oXlCfNnY04bSqAGmNj\n8DZTRVeCVeUzmHHqyl1m/pWKL96Gqk5EI9JtPjXn1wuNhHJ9ekiv1uy4uQ1o33Vi+ASxHhqBazSH\nFQOgKrrK465oVwU9iZk8Zpt0a8UYjBp+CDjOP5tFwWpi0nRehaSdfluPmr1s3qcre4Z1dlyuV0jf\nXfgz5hiEtEcttscDae5WKJL6W/0vYIFH2/vsm8OoD4RQPSJNN34jUFlwqzZEPLtc/ZeiJIqzUumu\nt64Yslx5F4I99PgpeRYFCw8dD3CtgpNJKeBoTpReAT7O0ob0NK+MEpspLAce7CGA4RRjowNNGMZj\nbwf+qjEbROMQm/19sdfd4eoWtFMcBEmUDcIwy3zadlH98AjuPeKJtAWtfbfzFWDM9Mcdeew5V37J\ndf1g2fkmvBh5dgTvCXMr2x0NWwFcd5imxh94VvATHfw7O39QEdBXFfPj3ffEeqTAgbel0UvfSnjU\njZftrWynlJu4kqQSU10JfnORHe4h72DiU/HtIjRMysSqF593SJ5BRQkc3ByixiPExTfE9XghBavi\nhedetJextNsM2o0MfQZ7M2NMv/CWFgI6DP1xZ2Fio8L5dpeAqYORS+WFgznPUvW4j8x9179cliRC\nH8FawTKxlGrZ/zMnEQqOo2fMkXd8byn8oV2qv/l1HDNFJXxAzGydp4ep9xXaGpaRCjqYJGv35KRC\ntxLJsY10Td+DHMNcdv6zJUtkWJdetQUQjsIqxJgUh2NTibilW7zwlph+ltuOQiZj7dhGo2NwpRxj\npRSOiTAthj8O3Oox5lTjkWsZQOJYZhsuLWdQf9lHcs0ZUsj5S9+2RM6U0rewlBsYMkgeEIO9WrvZ\nnFWjGBlhlIAI6hW6Ek754Y1NwfwcihhMlbFjezjsdA7r0d57sHy10dnyKk2dKzP4lsXx4oFswI31\nMlJeO4e+OQuXMjC2s9QtD99djW+BQN8vS2hss2jXp0RUFN2ALmqlKUlQY7F8Qk7GA8W8xEdMSRfC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CgNeDKXAqsyHlBqiikZBELrTLQziUuO2Ozlm5IjiDh2U1AcE58FeYpCUcAKk7tuudNf4kA\n+4IZMoylovZMIy1uk6gDeTs8t7ZT+qbKAYqvQHGc680oqpHHqBGMlkn6SvYbCvdeT57YiL8qgbua\nHHRqgt76f9I6m2gEbzKXyq73F1XA7iNkIQH6wvVGab9k5vFK6t3VknynPia/XwHedkmztqfsJPcL\ndpmsfLCWWjJB71zBzndOPEH4gQlmdtbPTUCG907wykBW6mbI2D6F8RXBFxLFiTe3lLlK9f6JqaKS\n6P5Urf4pShGjQxePyekutNDkOXiqBWkNmqlwZ0Mf+998Ey554Ts5BpfAZKA3iTDnLqa1WjM8MdFu\nz5cnBm2QmsWFiDw07bde4lWuor/GigLLSGoi61c1W9VUUTxsmRW3Nm9hedl/LMIi+IVd3Ie5yuhm\njFTZ6GPtxceQZ0a4n/9zmY1LfzOKboZDW8/yeLpK37K4KdBjNJqUeWPNEgbkAwu3B6nDVdpVe58R\nyE2+HOOoxDbkIulCG/2Z/niLLNiqicjDej6x19gTcxFfvW+AKN3OywTja1dzXhKcg8TxzQWMPch1\n7hIDvB5NzUnEvJPUkHECOzjp3pErBKiXve85ZxpQKaT3uOCuv48BGPUNsb4Lfbil/ZB2YfZA375g\nBWHRJSLDuy+pUEyTq8jZoZFHXN7uX9th5cbBFjtERzEP1e47KFVu+y2grd0uT/p3aA/Dnc1rAVN3\n0OUl/SCM2fRrCgXsZVeNO9TXtrL2agt1/h3Lf+NdAkcZvn9s+8p2KQQWKc+XZxkefaWM9yc/9fsX\nPY1bSFbAWYgAawdP8Rju5Hw/OWV8Sbv9vq7xEY9BvZleZMYuNtFgj/xGBc+xuvt2uXAyHW8FfkIM\n8cL8AdK9g14QyRhkyT0yYQinZHzS1u8UeYNIafkE9LsetGUZn6zTUy/AAQpdOJF5R9QumyGkPJIG\nDLlbHC3SGKKie2/q6GjryZedQrBwkwtDiAxTW0Qz0ZfWnHQKZUXchgOf2KSxyoc9cL5NvBSM6pDT\nBAvpvpDR9IQrbp1Me+korQHewv8IU/iJGQDmW9irBUgAsfKFL10de5y0FcL4nlC33hPYvgoiE8RU\n7OI7bRcSswtiJb7UhlyHXhX/Qq1xYGb13RquMH7/TEr+w0tdRTXngTK1PlKg/fw+yvbbbz84vm14\n69gZb0aJzCbyTfgznfo6NSyt+Yc89ItF7q9pqhZCgcdoPXmBq3Yy9NMPtoxsUH6kOSfBF8AAXDx9\nadNlsmO5H/J6vjfLVMwnD8RGzKg6O36A/qO8CTAXdFBWJK1mHmV7AHkQWbWjtI+29Y8Cjcm5TMCZ\nVcGqgrTLwebwYR99+75or4EP+AEvUyYflRqH7zmkV397XZfJrtGjYDfVNOaw6Fwwl0BUaCVklg+U\n5ujWXPqT+WCdWww8BHlzRx7C/fcE8QYr6jkhv8ZWaZVWeR7m0BETZyFFtYpPQbknoTrZ5yogazvW\nHlomBpRuB+kPMi3hXD9VvYxmmzlMPKDSqnD8oEc+v2HUEWT0UgCJFxQMm9iGggPf3YHN9D0jFjsl\nmgTwaen8m0tCFvDheznqa5R4IJ6bRUvo2XU9OK9xcgDzQcHU2WgdEott1qQL2QD9Xhj4zN09paCL\nT/tIIUjT3V9B5xBRw1DMZULj460qadkGntA2s4bdSew3xEhDt1THe7ANelYoDzMrlueUPA5ybCN9\nj9ihdm9lEllXxLg3gyWzGmSmuv3HEWoNkOVomnTHzZ3J3QNTFDOMQOkjTsUcMNbO06kf3AfMG0np\nYy1LjpLqweinJgeFCZihIUKgUh+mM5q83dzxHzSQOkbp4qgEnX8XTdz8z9rDrqNF5Lis+cg/r2ky\n1v5mr4jN6tquOWltmsh6mJqtbEflof2B82KIIYqy+oo3T5rJ8j7yS3pspqLojUPsoDdI63Y38pnl\n/hAd0oP2aCtDsnE/pfTIXiWPGhPniqLkuv7cBGBWXYznkXvzGpkOqxyxhWAgwn279Vl4NoWBY9nG\nP+D7yenxJFKzsvPZCtA18L/DbNpESKFNX/zlfxsNo1TD+3r7PZTSdNqrXwlbhXO/m/+5mT+w5GDX\nG0lC5guj/TIRf87wZd8GuzTYgQ1MRFizqy6t3AMudVJ2vnbE2fTM/qu7afzJMvpQ6f4Q2V05ln8/\n7q3U9uBhrpQvPrvVqap3SfhElGbEOS4idqH+lE2LwPXQ3rvBZaWDG/ZqR0WAPWNNl6uprwIj8V9F\n/nbYOcr9WtpeB5Z0NEKE1Wdxf71w7Ne79WOVGcm8UQCtaI9HHu+ky22iO7zNt7mGTopdMTplddm0\nXuIyP7Cf2kKXQqso4w68N66MJgEeKS8ICKONtQ2HfqETdm23OPCItND6bDztQXOM215iJj/463Sd\nYBeMiN1aY1cnhgrab2oVuroETi3DwUIewB0lELB61LHLjpKT1uFQeSRnVjZ44sLqvXljLc7VhQ9O\nkM67M+SRbxF7gdwjNVUCJtaTxVM6Vad93zRoRBBi48nRC4GogHXTVFX+P6PK4lESKZ3QFQVE5E2X\nZJPoqgI8udlaVeBK1CyOphB54UqTOMDo6yXhK3f1Oo0Xb7Z6EvQYSu1ZmiGlj/VxnNju6GIffPbU\noj36vPOyJjH8eHw5Lsq+wMg9hiBym/bv+XrGLRz5gPQOhulovqdHuA3VfuOkQpBXA7ZwWqE0XEHA\nHlX4GYw2s6WZRP35U8njSsTSSEzeHuQwdhGLNBLKiGCMrt1OGn5KvLQhhz3uFmvCvtO0YQgr4gRv\n/vmpo6suAL/ASzgOaEPhiVzMmPkrWYzIBE3QRLskFPR7umUQrpLgsHbonxi24nKArAZlLqvR8zG5\nMJW+VCRb5DvU/3epE0IoFGxaMXInK3yTSqfouU25pcD7UPznWiUd+Z3ZbKcsRUDqqTFSWVEIdDtj\ne1soBVA1ECD1iz6+bTpNY5Oh1fX651YQ9lvHKncJ2+dN9V+hRK0ngC8rt429CK7a2Idalpmi3JWg\nDc+d/z1QrUiknXJdMXdblP5a2mivNqIY+P9N58n+bZLVRKzRPI5fH+TaiZ5jTqJPrlNeN6D2tTa1\ngbHLS1Bq9dYuOLXi9TsbmXBgJBQwwPEWK5yG6KdPu9G2WhBizqyKJONkO+nGznTqzepavVi1EtT2\nDSy2ZlkxvRjUjhs6nkJ8oFotJICNfcBze5Rsg/eui9K9LduHWu4KMEEnfS6sgxuooXB2mSH26zwV\nij9uuzBYnF5pUMZP5ZIHwUnjANwa5J9TVpzTTsyHD+lSA1anl0ixbWrZqBWojDnzT+iwlGIxFd5a\nCr7uEUoz7+tyA+l+rF2lKvvxzfe+zdYMMBvqsNDGdYqNAW9FkmJhCLqy/xwgk+n2wVFwkP5bs5+I\n3CWz708qj0Xl3IUamaiej1IyWbCM3/65rfAs1jw/SeAXlA5GLuL0OQre+5ukvItsHTy5WCsZy25m\nIlzQgA+g35NVaLX8dpPHhdDcFPt1hGXhP7Yr6joKGvJFCTAqQSq1Ept7/OihaNf5XXI4dZlwggzW\n2O6+s9dtuhAiKtqIJ4ijww+apXGJirR6xUAhOeSg0/dL5FZGPXCUkxIV/mjEPUtP8xHtTf+8DOkY\nPWXBtnx2mGH1KZHfCfdcUVSPmQCAIA9DeWX3Q/v0IL1BHCVTaOsQ0i772YTDjXu0N/Va45Up12M2\npPcrdVHbahLP7O39ql/r6SNm08f+RwI7JPRtDX6X7V9G6+hu0iepMxsxBHk/8XaLUie4D6F8Tp66\n6wGBZoUWXHhVYxe1w2xSgRvnaXfLtyfhQlgn8KmHdgk8ibc3u4wSRbVtHfjrajovxVnePPubf0sR\nGGHlwLMSkklmrNGL+lSFGUi1thX7/vm25FpgBAf+b4KILInLLMnv3/NiX04A6G6zgU8xudOjKqA4\nQagbl+lgpX1lp/P67vogTffKrn8q3i1bhVvE/95/IJpHNxGD/YefOIJie6yvd4g4+QI0Msv2w6Cd\nidnVFRjhjKzWFPITgzw+/cK7BbMWwZa8ZVr/R0Ea4sWBVTZPvhPjDIMDuVTtZ/BIXrN3ZvcoZLIt\nuEf9nP+YPyFSF9h0+9M0/nnp9F71JHyX7jYpqOOfRpiL3Nxuokq2bunZore8JzX0eTcdJscbMtrD\nxCeKBmGQnzKQ6UiCUFkKvuf94g0f+IGcEZumf//3NSJuBvPpTbwMJSm+sY9G//ySSjk7pQqkuR8b\nMd1KFK517XUMgD7SMRegkJwaEV+w81z7aG1qIch/hQCgQbYqsyjvh5nQId8PgIl3hj4GB2InI72Y\nUAhpGWuaDLA6TX7OKs162hqSHhiyjirChFnxXjvJ+txbFF2Fcvd8Lle4qgP9HzwonfxA4tbzBytC\nLJ8EbIpgGoQE0uuPrT7LQg5Ul5yacTYpsvgQiEs6/+lSlLDAjEpcyOT1BIsadKqhJF6LUpao/Yqd\n8nYhQPOfQ9M4yxojCmXWRMhypMMDagM5T9sv6qzL6qgJ4635y7SHWV5n1z+x2GMB2W7SBYChf9Cg\naynz2TV6w7UesU0HBZfyRI8NLkyMS7ihpqyH1jAn2v1bX9SC3mKHK1xiPPb7MyxWS2sPaIZTX3dn\nLSFpuj14rJiJBIzNUKOQfgxBQxFfjiC+nqamVkFll9Me0K3Pzx4nWb15saHV2Agy2l4DayCQQSf/\ngFu+g2qlmJp4rljeZnvFcfEJsOYyCCSq72bieaiG+5CDM8FK4XKb+yzUHKzInHArOoYBwfcoqN49\nPkjVl2JDlQyLuLK8pcfOC8FrGunZkBIccptg7+MMvM6q5pSPMdCQzLJdSw9VJocDG6zh3Z5jUJwH\nJq6pFgVUxL4mHQb/BSlbgvs7NHbdBWKz8rrRA4eVc1kv0JgHRrOMv+3zEIoIiDWuTT3t+yN96Iyu\npS+PKCweGUCAk35o3tdplD/UZzdXhXqDMyDWXStqKnsQIolGFL1H7y7QpISzFxs688S5FmO1T2+D\nM5ktv/9S3iEiq/1qs2t/zEaENLUrc7DR/jifXMCRgj63g3PpLxVEDTtL/3O4f3ScoHrkebcb9I7i\nNaMRY216C8UOoH2/Ce4vGbBnHlqnvcEceN9HJrjnPVfBNQgn3cqClEzhriztssglsio529EdYhvp\nAI3zSbuJdREq0mii65Ch+MFopk7xMl0FkZtWXazGh5EG8XUCqTTwL68iZQBJNXNwpWsMwOjvvVMZ\ncvUCwskXIgeBTeVeZn9bFKUZ2F3GnOTZ5jC7ctowLND5yXfbzx9O0liZCTrjtu53iTdFHajEz/b4\nl8p2KTpbmC2CvZInR7lx9ZYk2MP7OjxSovdxxXIwpgMYWg1YKAiEIew1eILGHH9xYot4oEMFno35\nqX/JcF2ps8iJNJ5XQ1YzV7SduBeTCx/Yb2d4VHhNd6lfGJ/VPyBamni0Pp9q2Dj928OQezu1XIGJ\nvaLVosBVp1vLOs0cqntR2L8Ok3H6FZqtFm8mugOIB7ULCucN5ryxyJlP6Mrpe7ya1q8lqOGtAwth\nG/Dy3taw/Yy5HG6TB2aoRw2kQ4Btsq5j++25XkrGXxx5TvMK5qSWyxOU2HSAXZZI0Cn+jichK5fs\nZG/1nqyorqf8a3ei98nqpjNgoHVp13lYVrpLCWjOaECv0Opzj1i6EBPMbhdUBAh9TkIuZZlMVuR3\nRh3hDvelRcMCee0tJn0NB1Wo0yrT1Hnz8diHo+bDuao4G00VU82hBM5EkCU6X58wSPK5Y39d0nUO\nHn4Exdiza1nnBgC5bhX9sWMeuT1jWxW1lo98Wgg9WCuJU11VR+TlEeM+FKOVQRTr1Pz+sZNQxv7G\n5d93rqlCR8T4JnKkrFpEu0vUDzqHKU9hKuIJpFddQkwSB2xvH1Ts23XKgRXCs0PBmPhGZ9fSHQke\n6HQRh6E/R+JlmU00vuzxXNYgXqd9Ima7gLVPBiuGcv2c6w8sz9lOe0reW1OoxgvI4MANQ1k5Qp3c\n8cIsxgheBdrhp5iBVRipALi64MIShWbP5ZPoC0/pKzYVhS1qbqeAYfngLEsaGyl1GbQiAKOpwRlF\nIj8fVr9LS0n286kxnV9KaZo35NiXSH+DeeJHugfPaKqRPArvCi51KSMF8TRpImRrY5g12Q77sDQy\nuaSsxVmQ+gC+MrGhQk+Ferh4zGEzjSHtNC5ofHgArM1c+JvCB4xiTF9PDKwaSAZ1gS7diLNW1Bae\njLSh/zH9yp2jy6upD1uDSCyY4UH6LJchwsOuMFwcaLN+CgxYvly0DIo8bjbzFwfBkFpGByBmPOSw\nX+53dM1x29EpbpVG9DnxzhIEiTGtwhrwJbrLXT43mpBbRKdfi36hOpAPxzwxGmM2XQpL58RRNhcj\n8J3y+kVQZQrtEp/v5MaE00o051ZKzTsCgatNlb1+h7mQ/c7C4QiCOxC33qTJun7RX8BJo39ZrxTW\nYDNppnA5iD22u5ou7Y2jTNRktD7kCCFgu+pWxFz2NCOwx0LWL/xwthI4uWgbfvNB2k/63fFlHEaj\nE/lOWNFbj23yjG4E8gRNJy714aUef4Tuh7kJF8XPER30VGXe3k6uKrLNYFb/CjramGTQtoZqG1Wi\nNtwN4PiXY4YZV/V7DJw5tBEQC+OFyKd8PvCYSCZXox/xteCAfB1CGiTkBdDPfuo95ppWrd5sYro4\n+m/uYlT5oiDyS4hcdq8NZrPRJ7t3f6AEZyKJHp8ZmpqJr35SNV0Axo3GFIGOQMDxaw2HBiCFz8ay\n0cqG5lTZlQoSb2/5YRFNwgAL3XRgaPuzhiWC0+iZX4FfOSVo7pMENSc0SRR1oq9QxE68hWiSkdRE\noq2dpOWG019B4JrlXKNvrLkrMUJ5sH4zilU1RN16NshlO4pE/W+iLCp9yU3tOhdOroeDMEBV5sSX\n88rzfqWGbCdzlLwovLmF6OC4mjmrF4HPSsi+jJqVq2LoTCm4TxIAWNwNYUfKI+KzAGYV2zVKIdc3\ntv0Wqz2HF/Z+mmlP21Pxb9zNw2JAzU912iUJrv85MmEUSXlRqOnV5EpBN8dt2ng82MQtAztJzPj5\nm0wOljbovym9o2s68UWKkcVsW+u/o4fpmLEDu0/z7IJj39E2uS4Bl12w26sC0xzNue9Ykx4+XW3u\niMkZqb9QY/xdNNi+tFcPMQW/CatBNuqFXQfaUvwS0FxSHLkgwa/6tPKdt9Lby8Qc9UIlXM2UpJl/\nNhhYzC0x6EdFGNul7x37AnjCNny4Ub/Ww0R4cX8qod0lRCuYjc9/OQU4C8qBVlWUvWiqPj/h8D8f\nQhCRt8sv1r0iAYpJk3cZpgmuKHxm8jFvDjo5WIz/+22ypyGDYseC1OctClKvmM7/cVdn5VkUnqgn\nJt4FETNQvt7chlPPD1Blrf1lky8HAFkUz5s1KeXaTm0rNu7JE6XR8V3h7Czf5z1eFm5FpaVLnA6i\nl6gkI1Oy031mO6fuF+2UNE0kbZWVL/z2MovoMxd61gsIaH2gjmOgomeRnukJmCRVi68MY3kbsyx7\nAjDUjeD7TumBK+WhBzseB7EYdYrrjC0xNAbW0KTZsa8VJzao26yLPqoVlniszEUaEfmZIu4GUBZX\nvH18+FvNpADgh1KH5fdSuHDiDUnv9oODiC5mrl2wVb904J4khorffh4MJpK0Hyqb15eO2Ca0JtV4\nZjVozV4xm0JoXjRu8uL/nTLuVXTAPNoM3SVKkg1n280oUNhYvCX3i0WN5ylfMuGbNpcN9LJBddp4\n11SqFP1NXhuLwJ5bA0jOtdxqBXbHcdhaeMWFitR3fXFHOvuu8aymkbkfDY0gdRGGti7aSaKU0hMX\nHgwRHUVqc1iR4XykXmb7Q5WfcLF4ooqZtxsSikSNFHzAti/2yk0oMmHKWKyVyVjJdIxz2SwSrPSL\najb0N3knTHQ3MuD1lBFy1po5ELmLCBhy7+rf4itkuo+NQAIac6/zcKBIYoXi1zD23vt5qsgqoE+I\n0Dp90ubxmdHHTmnbPTc4+NNMjNe802tiwRX8CZpAyNkqWZ8oNywJ1SpJTAhL7vDB8KGw10MW2FXs\nnGOuoVn4I66Wj2AWJ7runJR9WAguApiSNyEhtPJ9f/zccN9yj/QteX4ipYXXTXBPY8cAUCzK+kOu\nYX4J5okSHWg7aWiQu8JL7aFCRdxLsadgw2aFgeoz9vX5B0AzCBF7usdHNbf0jEDami6RCH93J/m8\n2OgYYgL8Ej+KCoG6lvUB7OtCjCvIoCrDHKr9U6qbY5BHtKNyZWKLJBRjYgJAXT9v2Nb8RrAlBDkB\nfHRdOhwhcF7TCnh85ucoPzf9Migqgrtr8G8uA/mMezhbEr8QjgZa1i0Plo3+XCsWN7z4bcLKWxvK\nbESWGbRCbDxXRh2vLlXTlrKJrqt7Nf8FtiBJRUl6EPPL4Rba0BmI69JvljAh38P317fIDE4GOtIa\n9mBH4b3fi7i3IjZADl/THipU4HGXDKUo7LVhZ4WWooXNxMBYiHj2F9OO8d51cHckkNvwl4dDHfF0\ngX5x6HZ2Z0euPtHAxIAIvGN3a28eNgs1FbBm4Cj574vBPQ1sPztO3qkYdPps8yHnpZHu8LAKpnjX\n/Uhn45oxLvgkox1/n41E0uciB3IWvFt/eOXl1sE4Op++7BmN26/XUIdbybUof0JAEltx3flou5sP\nXd+BlU/qHvEJ+g7hhcBKwWZ3W/4Ugib2r3wlCRoKzqhT6iG+AvHfkBV08TRK6j9lSio1idWQ88JS\nTHQ+2lESdjCcCVAInngcchEjo53n+PCUerJ9L2ZC1REI8gmQnPT0XkhNUxwEg75EddN7xBVUaSIU\nDErm9gXrJvZQPsIuIkhgQk8i8CZKRfQibb7WYSuhc4dGRTCbAVa5NtFD9MSglM0bKlt17zEKpJEC\nVZllz9DiRMdzE6DzA3RxRnxsyZUYg+Rbqgy67o8VeLTv7GZ0hb168GMPVgLm2aoA+awycuS2nmIu\nBwxSU8jdhryhCanImlvv7n7OM9qDKeFnUHub7j5/vLqo0gUPKbw19DAqLrR/dBm4RiruWwkJL+Vr\nYaDpf63ayaEeAzSnD0cpQHU3ZCLJeBhnfxX0uYGMQNvJLhjZOUAZIKU+q2xLMNBK0s1Oj2SGLJIP\nB9ay9bhEDKNDG+q9tz0jk/lHWt+27PBZ2Orbru1IB6PGvcF7o4IINZ47Y61IJdvNx85lEXBrcA7B\nbbOn6CJjQB+T7JsIxok8+2GENpgNIZb6Bcgqp+lkWXRcSdm4Crhur5On6XLP3Smat8qdnIApPLs9\nbQbuEEgK4iGY0R2XON7EFDqcwpvd9HJfF0doNmYRnby4O5jr4dNWSJcrtpiL1SVKnyGhInFEfQHQ\n+DXG4xim+qZiObzxjxlE91J3P7ns/Z4agRzKnj4Bs8sCFphJUAtf1b8M6ki8+wqxmoorOBQ0TSW2\nfic1JdtlBxtJjj96bMWtzNWxqmdMErlwhYYmgLITsu2NM4iCAfcGKBZf5/2QJAc6KpuJ0YXmAr9P\nQDh8+p7+bfBMOizKNKsdDJpQoKd+BK2c70R8IalyjokLs1SjxebWlA3xdmVEjTqbNeiC6czWFnc8\nMh7lwb3BOc6Ndlx0fLvO1LygzG94HCJEuodp4BDA/XekIbw6e2jXryvJZNncxNOdSAp7NhXD0MTq\nL+eYms7r3dzLqPnTIoOapuMLt9z6pTGSFu4prxt3KfZEY/tg5m2xYjs5S3UTESqK8EGQ4Uh7mj2C\nmeTpL+NnPHN9D6Tcwlf2wKcwzEIoPFOH+KRGp7qU47u00mHtM1w0CJBaprBpNYslLWtgr73bM+TI\netuwVX9xMdE1iIPLtqDKqToNmwqLbTqYbDF7AhnuGCclTOQO7rKzXkiuu2cgkNXs9MDcgBERnrlp\noSmH+1XF5zy5EgDY/aj6bc5p8COX9j8fILa9GWyrAzi1rYG+qiFjYiaUKLyhPeYAdWWmMyh4i84B\nbKvDE01pJCRGteMwcLryJl1FlmrVWZXeKcC8QAzchBBp/Jf37YDds+XbqrZ1m5Ume42Oz+OwaVx9\nQEp0d3b8U+2JSWf7DEIHq8A4CPn0Yz0MR+6IFckEv3n37qebhFORndRzGMZYLwBPz5F+lDjhD1nN\nOBG8YI5McpkZKsODGLCYC3wWWtO9//k/syJXo3iJiTHAkaY3Pk5xdKwb9VUpZc9922a2AA284kJS\nc/w6K1tp0gLU0Mpr0z6sOE2lMiA9auYS/Ut9xt9km5TLfRwtApCrVpLkRpuATTyDkPyjw0zHlluA\nDR8qhNAd0dv12ExG7HMW9hu1wx2tg7gT6DB7czWMjfl0oWfOni5ihNtwEk6CQZd28NjZhRLPtWUH\n+FSLzUGO6SUc7y0gXgUKHWWu6ZLCJjuzVlela+dOL72QeEaZr9W2zZsVyJuHyVD52aVnwTT3AOFK\nn35NMxcXw8wKd2P5UJy7K9ud/l3TB787S29ZjoA3P2PfHD3O3ogtqpAvHFKHvQH6FCjFAhfTNKsk\nHErVZ+LMGHXIHVT6Z+l/KcDRafI2MULITYDczj4T/XSoW77h0fPEHYqOvITz9/+t1jS4SF/xhMpy\nCJ+vM1OJD717OQYw3I8AuWVAKbEFDmdfhO2gYi1hMuJLe7msDDDJmugXMUoF9mrZsfZexfV9i3oi\n23Wes31mp6gUDeJmUnRxu8vnEXLXkiWl/9u8IHC7E2XwWrRrQjWJ0kfamR8dvKkDDNULew+4K2sT\n56U8REcr3Q7WZl30N9S69uRhCs6IfmjziRSl+vlcdn4FfriLuiXy7muqlQV0Clg60PupqJcebXH6\nBUv3N+vgcEBJNag9MeJroiptA5SBkyIwauhthJkNyG9cjMvY+Y0bNjtsLtZs343tIffMIGKFux57\ntQPtlA+1zsQMMx1GkhXVLeWNpNUusFkTpgwJDoQLEOEi8Zp614efkCcYVhmJGzjWSCqabm/Gw1Nj\nJ4Ik0tMKnueBJdhaSEWWsyIg7gzCo6ojbJ/1WK3XZUo8cSbAmj3NpQ8f3K6RGgsE+d42pR/T303c\n/Z3Uhu2BKb+FQ6s9dIHtFotmPfqktj7KhthqO8zqlyNKxItDaisn3SMELHmsayGM/owrpF7nv40K\ne3ed0W7e4bQB4884HK+HliaLERfHqfd6sojXuwMehsBRnJoO8m8q7ahZ6s1LsWkB+Zksnu71S2zV\nHiUZFid7GiuHHiBUQ7Qd/vPMsMJp5bVtz9D4AP3I3dU61RrSKIdqL+KD0OMmiKLD1s9vfq/Lggi8\nyDYOXnEaPvoLPpgMT75wyaLD6A0hux7nQa5XkbPzjFu1KSD8ZwP3SxVWbxj4j/8Tzh4FywINBztF\nn2rzHSaTZJ//RC8teqLSj6JWF8TEBft6NrAKWOnkEeiJ1bjapFbu+Xyc0moJisEfKi0XSUhqo0ZJ\nvo+Nkd9+TnyKNuD7VUbg4gMLsUjs7mfxUIZOcoNkcwrH0C/4n6c2WEoFq4cd7OfYh/pSCxWV4n3x\nxbmPFKTRbHeiuvL8dbAskiR1ebL4RRpvWaeM+4p55Hnr3ivCoL+t3xpR0JDvaq6dyUHXNbah57hJ\nhOWl8WUzGzQ3liqx1NFx5loduc/et/E44cmgxsaUGPrg9EcyCZ3LnhBMH7HJyYsqKWSnevkH3XS0\ndlQkPwd9HJJ6GwvDI5twDfDft49yqpn1LCdAWzFgtEquhfGIISyZRrOYzqkfKkXNSoavO7FzqJ5u\nPXRF4tJdvSlIrbdeRCN/Ru3p5rSBg0ipHtF+YdGXE++Vo0KAvLwFCBynpEUwYwLmFI6ab/wmzDEt\nPfJGznXMlE77hq2SQW8HU0lyYvPYMGpxZxfiyPJaal63xXG4+I5HTlYhvbYcEtXEwlFDuFMuGhzR\ncryuABzlVKTwMFcuBnLV1j4SaflPSwDiIrvcgc59ZFXh1InS6sDvwvBNCyqeuySJLzlUVZ6wuFcI\nrvDc/zMvFRimVCFvYsAlNyuXRDoaH6xbrVJ3rp3Kn2O1IXDh1yB/RKT/G+2HcP5rvHJL3ELRbZuJ\nieInGchMdkenMJGUy1maicvl8bwhYOb6T7q++1RqjyDOc6kG+bGxCEwGjwsHMylLReYe7fA/tld7\nZlOvMXTPD8Wr+YnIJQbNBu3wT0m06a3nMCX0Tf8mPMOQeujDiCxxBKUNU1Z4gUkdM956Frg/AqGE\nK1yAtEJgrP+R7Z4492iBt89YoCfexnBVxaWIsHhy5oy0Gbec+N1pXPvIGK4yaaLUKLn39KYX9oT/\n2kRr5m+fbiSVE6RvSRlihIvzTM0ELxW661/yQWQ3SEB3IV98hF+50e6Qofx7DMLs4a3pNNPMBuGL\nD5lgohDSC8CNH4nLId9yG7gsqxXylVWLKrFltKhvWIIe3Uhb8JG/qQ3posjDegfujtrmpc2W7H7s\n/FvHykVCTUfdYwybgi6uam7nskMH0JWOGeQi/ReIQgbyqGEJ0skd5h+AUDHmwcIYx1j0JtWGV0A0\nmb646def0eNaz5NXkKFscfG/zjwX5yi8+knp6y1K5DqQ5gSM7PFvWO3gc6BzW3QOKRZhwHI1FAaM\n+HHPxvSNMHyntRLaEXef+qV3vRUoAgVTQpadvT8Er6GaRMyVtoPUBLaJ0l+r9Ab+DDx4oAJBQdAy\nhSmfEmWKxdh4jCVEvLIg9RKw/nMZ3g17ElSkyV8JmptZ64i3nwISnFKTqAdaEwoCIDxWLYgXRH7B\nmkzrk8wzEG3zU6gr3RRW3zcpdTqWXJhVVzF20I1vgVqvlb2OMs/D7r+JqyCs71YVHigTOhc5oAdq\nmB/cZ1HOdX0H/45grCiX/WF2SxeJFBUjBzLF+vzOpruChX4Z29SXujo5mumzxkGUkz7ODmqPVbvC\n/qs/p+SVyywnPtg+ST+2NfP6Qm/GvOpc8DTE0mxKNlsTsE2Zo/Q1esOj6yRa8GAagmaAlfvxdIr2\nqQ9GRxzMW6WmYX4OtS7LZcUTygKZ66tKmEmiDT4ysvYlpXwj8Z/+7P8/gKISQYgRttmULOT71oQX\nRIUxl8biceYAQqmhuFWA7+c814MC6h/TQDmQFXE+5lRQlFFNLJeTOxxA7v0x8aDRxs+dw+Ws4CJn\nnF7tPsB7rCl7FNdzKPRG5Inlc8b76YKnLHN8PmDIMofpVmGH3vxbUJPmvoa/Gp1iSAyeqyO6DPMn\nOBEifX39xJdcDRc2HCFkh/OhEXGomdtpu6jtlaldzyxjjq01Hl/LKo7Vo6FklHLsOoo91ViQYEDT\n3jMHPVxSWXXHW5tgH/Ur7RTFxAUGJYfsw5ZHWqXl7hi7MBszl5Q4Zgmw0BwZZbrjBYrMT9ih+TJG\nCIa45gtEJLuoelht5168UiFEo8HXwEak1mCn0NqAnOG07YO0yiFxOR3N5XjH66iljxcI0/oM11ja\nM3jpJT7sIjDAPnJ8HpEkp0YHyPFnokJuWDEvv7j+tcQ85BcAWasVgN2xwJ8c3kOevuPpg3LLjegb\nwedODw9VxVyFUytIpddFyi+Ek3Ef/Q4EszVXZ7wSrZdqVFjVI+PEMaOw3lVur0LxFWsyTaf+WtVp\noCkznzxdoBsTSh1m2znlZ8iufzwiVZ+2k2zaKw8CGe1kw1Iuhi7V5LCdWRDup+eGBrG/MzqR97hh\nFj1+K6JVm8AdT5y3K/iCHnHdmkrAJe7LAjTKAVM2Ckd7mP7mFisLqir41jGxjs12Roi28k6szUau\nbxE4s4wOUxEE+PdrvL4sCjamvasmS24xaw2+sy3UAJ2/HTHf7Yg2SnRGvXrOx/Y3cHbhGP+aDgEb\nKktD+hEx5ivKUWMjX0ekgNUtkg8rP6tFM1HT5rnQe4RKQs13OgvkBF3dWaXWzCRx+xYycevTNusq\nzV/PH1N3W2ZPjrNNtNqwzM5yWOftRUiKNzr2HNyW2KeceGx8l0O4hG2A5kUOSsT2g3GUHVLNl5NG\nNXshenvVTyNS1iwSJzE1mXaMxcWI8xX2ZFXCTTsSKPD3z+Vdgaema+3tVmX9SsUAG+55jgwM3MZn\nntgcXr8wwDDm9/62v4asp+IvfpDb87r7YPj3AwI5u1Q2vWBBPaGRYLUe1YL+KjVMZkTz7yC14/kg\nKUcmXoJMX6E0hYYJbvsr/GxHEmoe0yXgyplmD8z8VHHRqULysYtJX+BomMvdqMSiXMrC1ftqP6Xf\n5lJLt3R1NupQCDd2yg1r0GVoif5x1Cg4O6/MztO0ot4PH13EP+8JhVoVyIzvLTsaG3LpYiI/E04w\ntvtok0m6B1GB1IKYOdn5UhTnnOeDSF8yqSsJdT5+W2nf0Mw4/nPefv5Fi3tEWiKG6MzYu5gAKqyX\nYsM94IBtU4+PjmNVbFDMQqspJboqD93At71pujtI9Yyr4NGe2U7LWqH5DJFqSuDwmUOpkT9NtzIX\n6Ykdg9VGhqU0BpnhvO9mlizoE4kkFRju4BfRyAmukFgTSb32zFRJsA0LLfSyOVbAZk4QIQYIBNOK\n1itbIDXymGcwdFMDHIxFkuj4VBJ6Mquw0sDqF7vVqSSqeARjBK8VEv4fJhammre0ZyavBbU737X5\nUfQ7aLfv/6SCeMYcZYfIVI7uxuSh2yqrF3veYKZiiNavx8Ve7Y8xap/jMfza9JtAtLOt6vgnUjK2\nY0tIRKdGEigJRkc3RXVQgavCbuILff4hg3SLaZVnBhGWAWV2CBTT/gWgjyw/DI0QBukw2P0qTy4v\n0eO8+qeDpwkbzPkDEvV6wrlJwA+bxlDBBxmCgkD6jX3Wl3LXyRqU8D1AYPbJk8/Ai7kKu1dHAi5H\nvZZ1NNIHI4dRuS3IlHtfzaYGr/2+JmvsjNrtVA3Rtq1x9MsHAwTIOE6+2RYZJY/qKW/AhkByIA2q\nzSh1zpWYmq77b6nx/aONic35PMRSW2JCMY+T5HLVhjQqh7tW5eSGPem7IlKhn9sJgRafYJhjbHjC\nkENxS2TGESqOUIw/w5o3d6DnInjBwcCnoF5tM7l0/rhqkxV1NH4tnNEyw1Ga8uaXKvHynOVE6lKT\nsMPfCAlPSfWGZy+Fx8ztjrXqQBm2eIWzC1+5ctxF8z2ITBViDt6othitax+2/VuHm5nRlwdzHjzQ\nshIj1OgtYd2GkFvojf5/hG79QUoRnxDCmRksNc51B9l2OiMNEntpIzx+oPfke9ZOIK0ixFNJU8BO\nt2dd50MFHemU1q+yhgyeJLhcJk4NSlqx6qm4CDxjG+6WFkPQPPX+Xw1HshenS4V4k2yyFz0nzU6i\ntLO75/btg2GsAQMENk4e3YRZ8Nb/EBQo2cOba80ASIzOzxpVXq8pPqJX/hSMy/djXARzfibMu4Hn\n8m7Iu1/RBZf/X/W7tjv2NcyIWgMy8q0FsJN/i9YtagiuR1ZohjiKb0xkZwkfeVJmUXuCiyB+nubx\nwaT1LAYKlobs+U4ROsQNwY14dQKQ379GafZR1NtJfj5NMMXRZl6TOFaZBsxe9Kbh3Do3udKVzs2D\ni32A4mW8HUwROMXLUXpyMzn9X0rXvM7Ef9Ld0xY61wew9Rrxwei8YVlJgaXytu1d0ZPkJZR23Xvw\ny9Iw/ZIWOgvvmnzyitpH+oJ7hjltq4AF3QBBQI6Of5yvm2EwRCGqLxspPgxuO6U2+3yltWBjfnn1\npXTYyTSBLHdoWoP2orkWjwFfKgBMnimJMfhp6BsdcCa+1oQncshZZk5HtNvUHFcaTcBEG/1PE3yv\nFwH2oCdQ7DNsD8ITEoKwUUZXaZcDvEYju4c3FpKZMpUImMJBTjgTLhAJkoh2ZalfJHLf3IbNLmCt\nuDQhwJni81iJA3bKwWcauwNnhTTTkGz0BJnx8pgM/ttQKz1J+s4zap3Nji/DMKWT4bP4GCYt2zD6\nyIY8h9iyhL3bgmYfmFAJ5z6FgbJcWiN5//p95xzkoKaAmWq8bB/qHQKFcPEN3qsWcFmZg2v+lUql\n5c4sT5GQBsZOIaN6hLXcbuBPNUskEmv6opS2zLWsq8n0CAbB8kzlR853B73iImgYV2YeP69BCO8T\nHtlm57drDF7XvirIQTInsyLhQ49a5O3WPn2NYe9pK6sYyiclFE3efqqAs9oCOgmNf49Rk3erhrHm\nXoGcLrwaPpjYfKiDo2jw2BFgabsKfzj8dliDIyS0e+rrT60k/ZntazsdMOPTx8kzLROY0LUXtMu6\ntlXdWX5uxiDe3mk+UlYVmTu56F2SvQ47HAFj4BWEZ4q9MGTKtmt4BIOr3uongvsWnzQRp14uF/yQ\nsEIDOmaaIMg/W4x9FyttQNgQaFRJ8b9B08otcQLH2oZ9wqjZoF5mkuQx8AG4UbTOVvfe2yj3/kOC\nVK/OfyaiJLTL4Bk2StaF6VB6dz6ZE5fMRxXmPvqpGWjv7zDnNvXXpkllH+cuixrr0OmDO4I0Vm39\n23TIhJUPJt+8b+ODtseo3On3NV1tnoKcObkmRzFAQcwz8xSP2O/+Awqeou4aiU2FQL9joaZcqCMG\nafhZz37qUv3Bt446BoTiB4QGz/LOcEyXolSKV+IfDTZzJl7toGQZ7Aqg4wohPKoZuyQnfybaoCYL\noXLdIad2k18KpeEV/Qh5XI61PN6P2Zi31UWvQf73Df5yGbU6QJGOqjdDQqrEEWhF0Z3FMBQgmOLP\ntGi24v1xAMr8t3YtF6mSME9WboB+blOMgVZqx9tdaxxEMj6CAFR7QHiRldIPM9dz3FHcUjCaUN7m\nCg4aMaceWlW9RKackBQlqVfVIC3MMGKu9dJPSHa4Cs1e60hKD5QidTWc3OwxRXdPbzDOROIl9Ly3\nAnK8u8it5J2SKrFvh/AtF7RONh7hX6Yv0OMbQZEYdQRphuNG+/5joFAN0FViCo28VvzRn+U32gsz\nJFjvG7CBccUtF3/SzJTOCRmeal6KSYDWjrC8xT5nVfEN8ik8dDRdvEFlwENhEa4FI+JxEMuYzpbq\n48k4OvNbdsz9YcLSrhiMu+fpC3iC6wn0AcEsVFSewyI357cK0IH4De2iLHmwnC+kOrdMiYOkhEVc\noue7YWGmUDNCEvhGo1VDX9ov6rx/50pAF5ugzOd0600+P9OZQb61XCZNKaN2cRegZKbtthLaSwjM\n3dg8IRMt+J2u/TUzvT/0O/LcCGRtefIi37fdhEqwA8HXy5FQ3xL99QR7Pecn0mCyjEzQy/v0oa5o\n/L/fOZPvIyI+0r8gmjx84THuroakqvrOGC2y+O6RMkcrXBVv6H2yybbv8yWEWIni7nRisZ8JxteS\nxJx58CGqxX/JkjXmFoHwDXjjdv2yKlFzB5HMS7FNMmtBWwS+oSRVtglPJdMpU9u7F9BRqrtwpZK7\ngo781YZSBIV85g1zZFf4t96jZpfUkd0isrYhnPeozon4+fC7m+NFNs58DXo0NSSbORMjgVNyZIKB\nvD1MXkJULySUvu8QqvrHYlVS+TZCj5tSlt8IVcDuLnJu5sa6p6l9Ad/XlY8qzx5hHR+AxxguC+fV\nlZfw2KoXDd0ZfB2qbtbTtXTRrMbEL1xpX8rtksswuHMnGq5juDh7Cpd9nridkZPEiOauzKxsRRI7\nCVB8jfp+2vI0SjvSffxhG3T+/vmlp725nViP4B9tEdwoMtpgd81dIFSk2rpwdVVlayNE+IpqftzH\nEiB9gaK4fEd4+Fdv+177Xs9wg5T1xLxhk1rJKrnRQ/ob7E3PVHjRnZqbTn1lN4m1OE9tM1tEA2+2\nkcETTxPY8wLo3islGIiY1ixpRjeEQq105WXt3NAEOen9pxBSziJ7znplh3Bv5Jhfd4LE+DH+62Q8\nUri2paOD3ASb5LpWvWlIBO1X0c0/GE9yYkw3UT0R90UCvMSQeybhF6LpbIvS7Mj2N7UIDNktDlWg\neoIj8XOGvhC7rulio9/jhvdoMMXW/BGwffJ3bvW6F1j8ofBgnNLf/sD2+CBwmShcJnktV917PB/c\nGkwpiHYwifvb5QsxDC+USJ/6bS618fIluvgemawe96FOvHXuOeQBO+5AAQJFrv6MOETHaBLyxkZZ\nhdFiSwbWgyJC3tTQthStNYQ2Ijqcq8pTeVjc97GyA0FKJAmWDs738KR7ADaCIAkqHkAD0h1MUnR9\n+FbDRNd3OFbCyEZHJivq2ZprIyi9jlHy0wWhXcjpZQ8ol+UEjQTNjbOG3zpMQoUn113I+jr0Gc1S\nTM87ulMhgtzr3TJ7yKkiezPUaUsGLNkJulnKZEben0CeifLkqxfqUkHJ6keOY4liCtxP6/5Q4+wO\nHtduaKRT0bd1vD7Qqm81MA8B09mkDjn2wISomez3owX/JtP3v30LM4K7C7FcjQbHPR49D28EA3BC\nSofi9nkwue+1K/ld8/Bp4ztCQAyHBZlPEpXaZletvBOXNKVHythVgvrTcQbHjUFtOP+9sgM5eL9/\n9xE8khHPex2eMJlYRYEKPrB+RnCR4F3kLYhSx6no4JF1QZ244aj1NXW1NJE92tzOUv7oXvUSAjtI\n5NlBtojAsBX6hxmiiWktePYzERylLrS2omlaxpcwptQEhEMmJS5IfIZJwAgRbCUmX9p98mOqg8+w\n9ktHLbqhVXGf/VbQ55MtRysucuCbFGSbHRdwch7bzJxArfGyxSrFYvM0x/RcGuQ0IweJsY3RdyHg\nFaDJUVNOuZh7yQ10Tca8Y6CzPWA33cBrzqe+DtCn4xWfVmsJwH+RCrljc/+kmStNrPqdFIscSq8W\nz53TCfMW+/r5emiCGSivPAgEUkmqO9Yr1zvHlr4ACSLSHIij6m0KFFoY8KgTPji0vV0i9UwEVr4s\nndgKGEl6X3JoHup/pIDAlbDW9qpn9zCldTtqMDkpCIFNn5Jzz/C+aKzLPDkhkHANF6WBWgl+k9ng\nJfyDERt6EgaSw3jvDjEUGBLWY+Osf4EUumh1zolZ2WxfKIZJ+LGMlk45NeP2yNtb8eKIHUjfhDuB\nAAL78ilWKyuNeSNEneeEKkJkkrDlWGL91FhvkgJiOVKmhuk1imMe2W9Vq4nf6LmSA4Gd4x1eAQ93\n/HhGxwyqJXiSTYoajr1ECwWCZpGCDCtKnhZbEaeklNh7KnPZip/UiId4U+Ll5eG6X4anovlPAZRX\nuN+BRI3VL/HAyrXrkIeFc8Az6/0y9X31vvZlo/cVSWP3PJd5xmelp/FdD2tmUCBh3HE1kI8w4tk6\nKnk0Sl4a/xLXX41mvrJcZt7UGip9fNfOxSoshDLNQSHY0ZZWzwK2M5r2OOE7lqrYEFek3r/sw8Ig\n4bo2+VUUYk8DiEfP0Ug4bKeS+tJk0D/h8nP81R8rz5pIjiZIvTPW4qaL3xxzLNIkjNMWKnHCVA8S\nqz3F6rOVLcRxizrNh/gKRNTTobKB2QU5le5EpNTqZi3brLiIFrb6j1WgRqrKaW0w+E1Hv5dqUmAC\ndygR5dP+BcwYOAoEb0AIQ1Leig19elwk9eQqk6CHHnHoizGmpwM6wWTvuBscCYGynFSduqniI3cD\nX3Ychq+IdmsbN4Eia09nMLa9XT/fgQ2NhHqmr0hhfHAAGsCIm3EL3SIrO37rLXaM9Tj32a9sE8Sd\no131hv5Jqnl38gB2e7gywOI4s66Yj3/gijchJUOUus4vPZ014cQOnwc3d24pRu/LE+c0Gd2h7b8h\nYiLxYPzxUKLOhOcV0ng/k0dVwgwZX/qtCqLJjIPMWZoKBl9XSg7obLru+lEBnUz6UDcynE0yRAn3\nJ1oHW6CHnGACh2ZHMRkcnR+yyiJOaiTDBYoNhUjJTvuC9JF3wK3mMHo4s+QUKIeVuxN7/7EW2ExH\npSKwlBwWgU7D1glsfu2gNUr9AXa37/5Xj4crYCm4d00LBssDXNw8lTV+za2l/ga0t2pEglG7Iq0z\nV8osC9aVgapXhnBeagIeBGgY/8HedP/j5bUcRcrbCXoYqWLDJf4IwwoigyBL7TQhE1qG6V6O21dk\nbeYFLG7kIXwkr5uJTFy93OwTLh5V871nGPNaVaGP0DdMNkTmOlBt5beUabdqElBWxvILKqOr0ynf\ndBqxFbUpSHTxH7beZxZQfgNPu/M4V1A8KY7L/t+HT91HxIP5QKzr9xxkPH9LclB7bfJLIagBQPDS\nkggrpbBnJjtJUcWyEf++hLMI6rdTXlYXw2Rv098jxz8PBtS8/0WtAesiXUQ5llqkMq6BJh//cbCL\nsq0efXDLyFcJtW6TpSy5YyY7aNVkjKzLNavaN+mANVospWckzBwgT1QPt2olmFsuj7JFeK4Zj/B2\n6F4jxR30unHQ4lDf3ga/HCQSpuL4mJrfNyzlEK7F5fmH+/s8UlJGK+DM4CkXv7Q0f237spoSn0dt\n/TI2zupItZoXFpvO3flbGJYpheAA5zhlAnTD95j6twP6V+5BOzZA4RYKW471/7y+851slUNQaqXQ\nCIp9B7OxFjblSZpJV/weOapzR9GGu2WUL34MtsBCFeaQzFx2MLNzu9aSthoU/PyiFjk6Lj/wLaN5\n+zyh95016WymScCXr3F2EFVrj7LC/FwmkAEIDVDNwfPJ9mpoiZ1919PXirdGiVkPuOHPEcMapDO3\nsnb1NVvSkj2CnbbZThL0GPImnc/t3exEY5SXPx6ybzj6T94UQ27BvPByC7kBOD49wmuyviRXcl2F\nIdqUOSbxaaiH5egftzelDJOX1vzyR0YubGDtY5qv0Umxu0Omqb2Xt9TMZdYumooKtV83gZxHVpXK\n99GAZz7+qyLJ9F/AWEycCeWMqgBIE9erlLg/tn0sN6avwR2/nrSFNLc/EC+/bGOUqJNj8z7IBPGB\nfQ8zYY6PrRwjmqPZWK1+Jv0AUJSyUZhJmQcLbZ3Z+Vf4gcrML1Zn+OIEWcvmRV0uMBfgANh4GoHQ\nooR+sgjc3g+XA513j45GTEqX0J38oIjuuejri0o0s1qV3aX1ZDPVFs+iQT5SOlBgaFzniZFnVR+W\nCJMWoFnfp3lRaIAae8dptvQ+z1lb6WbF8E00LnfutS8fEYN5BAvFUShschcve0aNbO2Fd9ZwKNou\neIUdlpNR1xw2YRi6sS0bsxHkj3w9dAhof4Ive4XDr+wdEZR1dcMdReAFmPe4r9M8fAC8TcD+ziCs\ndAyyiXjiTseYpE/SqL45QNnUX8wU1SY7Wkmbj7qB2lFEudgCsl5DvKwNnwf7NPmKtQp4fUAIqbUY\nWawf6h6LleeFJFFbANP6KS4s18rl9e7q45eRXFkkz0xtSYnNtMIqRatPqfLqaYYHtQVlgdJCV+XT\nyxBrVvKWjtS9dGambh+xqG8anwDRaBsvtYTPFjz4EK96d1dxSwc0cs0RZjzQWzJQX2MZkmVDrH9b\n1IzsV9C4oh7jpnOIXc0TE6wi4z5ZmWJDp0R92M51XM+2/JLAjTcmyXbZC1ZjT0uYJasHG64Y0rh3\nsJwZADr6qIUiYINbRVOTY6U3f/Ef+mLQdp3FT/uIg8zZJ1i5GPCy+N2QtXSl6CYryLARFRB36LaG\nUyv0AzNpTVkQ87Y6bjQKXk9PD6vN5epC6J1JmAnmvqK+MlsOBAhm+9pDIdTq6WOAyNFNsuYuo8Xl\nBx3fvu1Zxq2tumbbRaA/i8EDFX/m6ykEO4mFNU3Pl8AV8tn3F3Lf7D44Kmyyml4G5sW/9BgPRbh7\nThxIO5EGz5VFq06zFacwQLo4pLhRBzWLoz+UTHQ44EPlr+3tHCGLVCTWNIge/jchsyFhcIyREanS\ncZ+zNPVhYNTHufWAbKLcDfc0yvqikPWjy3YzXgrbodebfAP/eirsaBJZu8NCQijcbn7MqRiLl6L2\nRteTEVsUyGhODDCfc8VHTiB+ghs3tvTA7+Lc+AIh3t3hNDVH/PH8akeoG7vA3ygHGO0tq0aWP7bp\nduwFCxjfG5L5NaGxRRvUuxDAMgYGInp+NK1+q4jQalIyOLj0kbP//qXFTUaZ9n7Bg7Dp0ujKcqcg\nWv9m/ambWSMtb4uOOcUJT+ifnHmxRO/bOGJGWJ2XPiFn1EtK/ZpyFaBZE9p1wmm8hONEAyILZwU0\nInke7A1LhPXZtTe9ocL6HpV3CZ1XPdIQ5s+iZvjkez1lXN8t1Z2v5BX6rJ7LgqcOR9e7MIgeqr/z\nexY5taAnpUhmG2oIWpNjxhZkKyZkhjpoJu3Fk8j7rVo8jphKtq44KyhtWEk8kL9N2jjzoT7uolgH\n+JObgjkLvRGUcdvWzfL5ag53dRhXyYZsMcON0z9wJmh52pt4CN579yQnbOpGxqSGRmxZmyhFdqeV\nl/p3Gik+8kOPQ+gyvucYfwVhItuwMC06eQ8nuLiG1OJXO76XLRQvEutgU89ZUaZERvWyx0GamYV0\n8nHuCgqCu6IcTwqlQLhrmqM9wsjF/D0T6x4EENrezJNhCMo/69srqn9pE3e5QhPeu3yH3aeqQ/Y/\npYaMArkanCFNUV7TlOHYcqWP61nPzKuVcbmxrpXHTHLQ+KObmfOe5D03iRRGxRl3Aoabr4MUXLSV\nmAWsk9JbnNnBa3oBDusnLinaCrewLFqWjnSmsB3QZGVyxEZGV5ppLDHayV5+Ojy3YVHSdq/o5rfX\nELHj6S4K1KuTvOKug2G9AO6DdldTXD889WyZyJA9I2rl8oOLobw34Z6lr3RqTqZVxeN3/qkMTmVN\ncH8yYWfz4Eejs05L2KjwOOMy7+WWVSDz2SY2Yt+hvoZhaSYkwWipjl7C9s2jMkePlTYRFsCuG4bH\nT46WPqptd9DjIKj0G6IV8Nb3EOVRMCou2kHyEsnHxaK4LjC1yHDP7GRoy8wGHf+03rV02t3T7ZQu\n8KXrObaY6+U7BMIMpvjEmouWQBSg/TeMV8gYzzjMBCr1CjU9VixPiJ23jAUZ6PC84twcOwrPjtBJ\n9Ps9St5u2HpCF0R+dQEiukM0q+ig6+ZfxnqtctaveuLes9pQh6VoD6n7YWGkwVhJWn7Zcl4Xrvof\nb2EestQavqVV94EqwxZw+J2l0wwyjStduogZ5nR465etBuSmPyqpBEzFnv9m/EnvbV2KYdmUy+Hk\nZn37bG2q5a9Lf2SCz2kDknkESUlUo42vrqlIJ8ZljplfrHZvylAgNE5Dp2l3vqamjiMsGkmp5QX+\nc0nbzSWouRIuzsoB5gO1vkmZgajbNKZNkOTjXn/02QayhahheTOXQQ34eA50nuUFBIKcVSk9VdjT\nxBKiCfJnXl9rbX5mY5DOCXxQzH2XNyq7O1f8EUA4tXtYRpGUQc3tHWdqhQpvQblU1PsKFkGT9qCi\nJhg0kt/bLsRiOrKIF+nFMGNFLXYB9pf2+d97R31NRe+r/4AYED4d8y6GIOCqaplPjN2GFmdJmXNx\npDg/PfS5R2trl040plZ65yP75D7vqwV8RYw4R74OX/KMt5rkub4heCpsFWaFwLmPfDax9NiA7uMR\no5AZrTNt67CmOlYKYKFsxPfJx39EDQdqIoPHwZsaNCREcbF8UnO/uuf/stoAIMMKzOYU7Tq7wk1g\naoYuHsh1zOsPq9M1dsoLQQvrIVT6mcslB6L/Ya5HfoO9xLwShFQJlDn2BFP2bk2ZiDwWPksJ5AWQ\nxPyXvs5gEI7K5D4VUc/r8JRWeTKahIZC2A5uQ2l8VPpWfYQm4fXmMOatljtRnW/jUxjHT9oBNKkD\nqVxOF7InA9LrqEPIf6W9F26Jn9Je3Kj61enEkQT7N8C0eR5BO98mUBZsaTHA9eO+mZ0zY6yBHH9w\nIZIhemVTpxVzfFmz+eyY+2xzs1QnCrg45RzeEvUu0GuLNpkx3xg2F8iVk3kuhkgVZaYDYxRQML2q\nB5GxzJuw/4Po04A+WUBVanjXT9cSSB/HkPXdN4eynZIYzpLITcBi9mrSDMoFtv+a9I3cl+O8DdCa\nqYUWNoqWg0JsUYcTLCtR/Cwpe+rhdBoyr1qV7Pb+2kMYHZ4CPYgQqlXzIpsustkAlJjiy+wK/vBl\nfzqHsdM+VGJuL/5Pvx9Z+hmpNZ+/09z+Gl4n3Souu+Zna3gXbBPm9hTEjkEAHqWRmKIC/tcpnWu/\n9m6eym927TklGXpNh2gKnbXQMxUcNaVdt/EyYOGaE/X0Pp6E21GZDj08HgjvlSRZekC2FFww9ZSL\nFhZmCjWUr77qriZfhmaMYo38mtWIC307XLh+385Y/ByGaQkEbR//qCjLSMJSAOi23zGlfD9alyS7\nyzSbI+R1nKYqR0pUJVAv7NnRxVW6IusZ1SyRxgGDUOz2nxVk6QmOQBg4pn4OK1/hkWkCdalkr5VO\nle3IXYWZBupCe/B81dhLl66IemjID2jk4M0Fob/2a3FPpbeoiBIU/la0Ykmi6d0I9RMhyKhDo1NW\nH0kHSRxDD65uGyhx2iasDN+oCCmTMcVoJoAB8ihQBapgDRQKkiJgykvor0GVGVlJHThFcc5sOknu\nEcHXIM5pDSiYilxbV1hOiZFRi0zfKN2C81oXkcJh69IWA7MEPvKhP9XzewiVgwyw9bE2DTr+vqKJ\nGpKPhaSYb2PCf/xMOkKw/2IxZy0DvldZQIz/H42mRGnxqK6GJOcbc59J/CcZ9wicZ0vlX3dvdCSm\nG/tCgWlIuQo2mBqDLEoEyrSrg29yjYYQ9PEgRsJIeh2C2wK15n5uJ63tt5OWr5DLFThm3fkQbXgA\nXzkGaTJGsD5Gs2Tx+fBfn6UyTOK1IVwPAN2zlwML3qEovVHmxCxxqtRzmdIHf7GFU+QS3eF5ypJb\n0Wkqgu0lYdjYtGF1HqJZ/w8g4N2UtppxgUKvgsuArP0ddOyJnm6Orag0C+mU1jVJOTLJsZK9rrwa\nVqnj/xAt03OsMP7FfJJHDWN1iM0JjKx5TLVesJsyMHgC3fgIwfs1WJzkf+Jfi9zmVIQRRq4r8iWC\ndIy7DQ0oHJAiYGNlibIGm0pzBxeWw4gNavG4UxYrnq+stF1WW1gQ/LowmenwG0Cjy8d+i8DiU2tx\nqE5kkIRLYskE4J6IlQRKWkbBdjunTe0d0Y/x9vFKR5vbTOuUbFIiw4mrAwCCuC2x2SudYBNzDkAb\n9mqrAKsiJW2MMW3oV8nAwZmWBbAr8VjbeR8fRgoB65KNf98+GVk5xezWu6x/lnr0CSqNhgP8Aa5w\nQB+C8B3rl00CAv4LtcFA1OSpH9mVbGJT9jlNU34s6OS66nmJrHTsunWjWwfVT/YtIc070EwUHhu3\nkerJEV9OAsm2mblaCWXdeH3oJzAWOt/S+oMvNdV2qbdpyyJLWi9I1SxLtlFBqPLUdAhPAkz1jsLo\n2NRCg8YRSi+yN+uNbNtBQocjb7uBxCeT29n3ml3LzabvmlOf6To0cuq0SNOzxR9EqwHpiruBbcoa\nMBc77aBf1a+9UX28gIncucc0fWsN1jEkEXvx5chO+sTft3RXfVehJrpbpg1g8/SV/s0KS9NxY3GR\n+TNV9hAIdzH2xpxdAZA8rSqKcNG8BWa97giCGGom7uEEC7G7iZs06soDK+AxQRAJ+WmZZyXjdefk\nS0xqti/2PLgu3RiskjNwJldrE1I0uHPnCXTr+d7iBEMi6hjRTrVY0V1THygB5Wz3ABeLA5eOOzeQ\n8Vi5uyjlKB93QlFWHH3lYO+j7VPFOcfCLG9spKytNXO+3ZMuZYAEh/nurWu4ElE3s+omZ4Ov2r46\nEPwYJkVSjk2kGvj25OW3am+nVgLQqyod3R4eeO+slIxDIlI+vEyjLr2vXsUl59o/8nNJajFRrNeC\nQBKbaVlwgeYycDwQiAAlX7U0TlyCmV8LvO+qMuJA8nURMapsXSzQ7NOWsqrGyOWi5RpvFeLBpYJp\nlpXLdwJeAfpbP5TsqK/x2BBwqCw5+v8ts6eJrk7ZnXlkdQFfppkElqUPdjJRdrtJljlexJUV7l/S\n9EDrkcun2vl4KeoH970x/9UwnhhlWeos67t+L7KIn/jTSKVLCFzmgUCeWZOXApSSksada+4I4AAt\n7z60FhuEx6Wcbv5oZ1T1KOEQG7No24iw6ZsU+bkit31BeKNlNlf9iykLR1hA+9n4s/SHpuFH5j3O\nZSNjGYijauXyMyTR4ixS+lSVSyrpQkorw8J0EKC6Gj9/QrLDt12EFhqRc/lDsV3fcl6xs9O9V8dY\nA7lvM7Wafixk9rc43bfekx0ML7M7XG4s9WK3csfpY1oiMozMgqXOJxKD0kuzPssANEUXQ/D85/G/\nnAGdrXqPPiwy3wr6+JocvyteJL9WBanC4cihtz5nna5s1tFdbiuqfysaBZfzBV/6YcTDZKwKvTgm\nqZhIglOMJ9yJqyfJq63r14kkxSjwQMWG3RRiWcLLVOKSZtthZfeH77m4D41miS7Tc/HemOyqdMG9\n7Mw6ogHGykZ/Y7w7Q0wt8JRsdQCYRQQ4KdGqy4hgYTg64Y3Mio7eARXUZoVzr/CL0MIkbX3qQrSJ\n848dCKoRD/hC67cnMPZtbz1gXdq2Qe07Uf9HoKEBU6yOw/Gzj4NiAuP0mSKpjqY0J+M1wrQvgEvh\noYxui0aJNJD3C79rW+WPGfmfHlhkbxLLK4xp2Qbd3PTJR7sOAXqMjlWayatca8PLqsvo3/SUsDOd\nact9UheGGJcJzsHrFJGW4uJVKPja248SGfmB1ezEknT0Kn77YINW3YbBKksXNzXs/TRZwXPPmeSM\nillWe9EpxQsik/xmmOYNuaJZqBpJHWsO5zviU5Cqmtej8YXYjsiUzS0X6nwa2joG55fD2ePKRs2c\nD4kZc18LH99zxLxqlAqef7Z7VbPzF7rRytYhJo3++aDb/F1okJvnlhcWdE8oivy4CynFXCq34Dzk\nZddT5JfNqsqbsjI+Dvnk1g460kimaqtZiSlBWjGOWPbO5Q3FefJ2yYguWtBjOhXLkRhmtS3Jqkyq\ngaB6RKaxgzhqO7fR+aeq1r7dlFxYg/rwfgT/ou0hs/cLKDT2RzS9IeUgL82bZiI3uwApqaOWHjLf\nYSHAEZHmujq+y5+hiIUudFbVXYop0+n9iz8D9T08Y5aZ8XX3jSHKIoP+lzADFDe/st5DYrqf2V5W\ncYAuMkNmBP5vJjfK5rv7oKycQAyZpdD3KKir++RKXBz+ytv6KDZ3ruKbihq3P45XWbI9LE8M/NAV\nS64P1J5LKMAjAAkp+vYYdgjlsVqQL/Xbuly/xdraRbc1pRq/1hjWinOYOUkgFMajLAThGgfpYUkE\nJgYiVJsGajIzDh/jbbxj1TYpCLVE6S7b+OmyVEZ0T/xfxVDka94tS8QhS+UCxIXrIBfU5o/3SQ0h\n3vQn2lPeB6NmP8skmoExA7DVm82EtJ+we2cyJ8urhAD9sVqsW78f4S1IwcxShqM8Tuq8g5BgivVO\nX3JMd11qi6nKODzvG//MJffmArwG12IWCeAjpSSYpaf+6M1NIO+tY/2ZRIBgaTyaYDoaiQK5NVY4\nmYcA92h6QkfdvQXPFJAy4ys/CdO1Yrj99gjrzF+9+gtH5kj5guAt5HCh+4eciVqTfzSfmJaPLQlj\nUw+nQLaoq7hw9DWAfCut81PbxqUUcrVoZYdkhuFacEbq1fsKdSPr9w==\n`pragma protect end_protected\n", "num_lines": 1194}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nCgyLps+SA0ui7dPkXtm83wP9WSUpTVOaNUUaEiTx3o8bDibppEo7uXVLsKORYUGbahjOTDE6kwIY\nyzdcsZuJjQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nls1ZVg3oo/4jpb/tGSZ67UhcCiJPRZSibleEkmR8FGMVr6khAWRoF6kYXnp1zsyHU3zpkX5aZudH\nhQIPiuWIX1ItHdefmGknlXR0g8ejEjnCuf7wiNI29U6+5iw2QftYNsn+9bDRp5kdheVUcuxELJlA\nXulkNd/ln7GkFepSqYc=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nB9jNLech/g/tKNMUKP6f+gjxZsMheNAx8UaJ4vLJVXHNXpNxk91NHRM3Xm9hGCv9VXOliR2a8QYA\nPQ1bZLU5blYqH+18qF0ZF9Jo3IiF0g2nN4gOYAI7m5j6VqkzD58XFZMLPANE17Rohp8jENs7nh79\n49oN+0loRI7XCt+F/XHBh8FH2rSJmirxDK2iqylD74LWMeTBokuvbg3zEGTXe5qvYmMaRiXcTPZB\nDS3JpPd04FW7EUk+5RM0Kcu0Ly1TuyTKFn0mEksltOKTCKOerop73A+MOzn1eX1pf23lWhgzfN8Q\n8HjhN+i90Hmn+Ojdq+WsQMHc6+n0Or8KFbFReQ==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nCS3PEjLSMy66Y5kMQ0y4fL/X9nvJthfWlN6tOA1JzOyIwzumGq0fkllz2YtjUH+WZKf3DOAh6h50\nM/7oiAgx47vujLlrhLAvEpjj8WUfQd3LXqVk3NCO1ki3s4QNBrpCKhg86ykdPOiLuEXDkUt3v04y\nuxmO8exLVDFMG+CzMLadbS6QzvWCMXeAb/FFPfVqwPMMw1ByBbbNZPDHX94DLgrF41I4jklsrd2r\nI3FoDtv57i7fvGeyrplt+iDFl8lNUqFZyHP+5+yvGYA60xKn+8Y180eYGnmQ4wGtQ6Kkzn55UAKq\nBjhfYJqchzaFN68doG8FMNl5CP4MfMmIG1TAbA==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nnQe6+EVbiKYI6EF2Gkjs7kvdzSmGHXU4qtFfR2dYFwHCWHPPG8cZ35Gns8SCNITeaBfeRRFcv/q3\nUoOZpWturDci6dtPwvXGTKFk/2M0wDGp1JDGd5iTwJk4WyDb6tdfibGrM334X5OHFRDy3qX1Uovz\nSj9hOU/EFGjRS84ag4TVcz9z1f1Y+CgW8Ym4KNOI8D0oIv5DmjP/nJr5kVGL/WNmhRB0h+vtCoTs\nUcGqCPC2gQnw0GIBNKrE9ivvsGq/ACxJuuSLwAzquqUInK187ExgWQLiPHhTH6pfZDqnyZpMvGrr\n9OumyGggkggl7j/JE2vtz+6aHVWB1956RXcbLA==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nVPB71QTo5TspzkUp7HQwn2zfRQ8tDgsnLTLdZIsMOrJ+Y8fHz9hexHBR3Yhia6VnY8XCYjgPbAId\n7QK0Myn0r32s+olwHQ8M3jsY7WJNK96AiGDDRm0HHR2rAUT0mbjaG5Vdc3kGr5OmZ9abSnBv6qJl\nd6qqhUFQ2fTIk0vkv9s=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nIOa65t4pEqSGhDPlzgVIxaBhM6TFiSGG2C8XLJL6CyEFm0OzjlVbdnJuVLSSsqeN9g9q0ucPVcBs\n0MDNHCUMFAPmUvHCALV35V9sWsxZnNLruGv6jYCoLT4RcYb/Hskha3PIaIz4tnT++Oplm8SDc6KE\nj0p7EoQtGWfdUwtiBHuUQr6oMBdko07oc+MLXZy3P4PwN6CMYbgRTZvUcrJfxR1JLpjpTlr85sRE\nQCUEGnVHiSu2dgyZ1oOqfyUJGaHcNOM13rm1E+h8I++ksRVlalZKIcrckCfC48c5nJdrthR+8rsa\no+k61kcLH2NbhPC9dAejCTOCHyq4j6eKfXBGGw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25328)\n`pragma protect data_block\nkSwfaOQ2lUKsMClQk038C3qrnU/w3gNGhmdlLNfR9sWwqt9+mhQ5FChgk+V041Zn4jr0vEzfPK9c\nu3LNWSj7Kuy7mPDQPF4wc/gQY3v1ZqRVfjn2zXECRESZ7SISVb3/zgxGap9q5OV9OP32RkaV4kdr\nws8IbzNgdjoMmUEPWIST7YMeljelbQVuNUUiauyLev5wd5EZQgjtqiLEePwttFZFz+wDhSrZ+MSh\nmmVhsv4hlANMdsmgswzLepN8QpuS2x+4bV16nI3UsgySXVY0LRP+KYonO3zuI7oGlDGAKq7rVAA3\nosLmIrbqcv9oa8RF7mwv8MG56fHnNtMapNiNUP5a204RBeFO8tYuAT8VwFE66FWyg0x+SFytJzKX\nnDz/x5eXYt6o3ivPJ9zrCY3V2GzhHa8xLWUdmY+f0t06M/pjIKnPlBKPRL27dlEboBL1WLxjolrb\nZFxdGyaOrUIkqkQm8IlHVFmnZtXeSYrONP35eMP2kL4cGqUTusPeoqJ8DoPv/15TbKPwDOmaEXYn\nOEGzSGJPYZPw4+XZbtGAj0kRbQ261OYzNHDs3X7G23Gf83cq2BWgy5D0KMg8x7egPLMpaWTEJFAo\nwHEzBZROkgZBRyzx4uuOLJAzJ1Ww6ceB1GR8wqI1RSlj8gKQ1TwofF5FVToWZLT6C3Qy89q2zVS9\nA0mSl07IkvpxGwr60pFS+XBimis29n5s8FX1+Y2s6ykhocSOf8NQXfkCEGy+ol7sHN6ItVozii4Q\niSDgC+BYBApCgZz8ak4UXWCf4OdR75O09s2dPW1NNUB0LmDZ+JYg2+lHMwwfQbN8T9npoNochopd\nGUxTp/6OzrzXYuXdCTP14tOiLSckvwYVGLQRUNEHZFUjoAyI/K/pit5jx3240OUI/mdlbVjdEtUG\nZyZ6ijoMx/CJC0RWukb6rnM7lnnhpTUapuQNw9WieVmTSHV397OKlU7n+hVDrAOVM0fnBQoXDeAC\nPJlef//l7tgQN1x1eqzQkPGyXOWazM8DwiOoFa0tqkAslzrrb6K+PMxVs85IisOolgJv4q2sSZdV\n8RYCZM7MjfQlQzFbENfRZbZsAYj7zqKAdfnblfnQtX2D7QAAZtAVZbtICaIF1IOSNnsCi9uxK78Y\njHAC2RNWOwn/P7vBzImG9xwfIQ3kJklicNBdaHlR6kV22DiWPytbzi7H5Yh+1OnunmSMF5aO/a1P\nglEwFosYm2rOGqobOtvZdtOvQZbF2TLhNoCULxpUVohVdo53ERTsmRP3+szwtxMpYpRMOSIt1tO/\nmsxP5ho7MgE/Cc90lcabOMXU6TwV9GMz2Ec8YIMp8yPLEuaGXNyAKwcENA7mOQabA8/QNE8TzFxr\nzDj4HnLuxNA7bZFjKzEa951JtnbjQteNvnEOqy3O3vneTPebf0DNwD/PH2HzUyztYeqCd+4Ke4dl\n2XYcyyJlr51kmlzHyIsGKooMqHJz+hNY04caoQWD+Ev5YGjEMqMIxwhmZIm5te4ZzfunIO6qNTcU\n43BM4NF6J3RO7yg4ITHq50A/iI5hpAQKix4j86HXuGTgrvH7bsVcD2RZlv4gBrOkQU3BGQPAJeZl\nd25lZzULXvWYJCgbaXnlh+1h/NCjB/xX8TnucsxmmHdRBOGDImMff3FDsIEnGC0nEiFLP/fR0vhE\nog92bMwB4+f6Ja/JwPj/hHsU/Y7/vhRpgrJZFtljDVR5p6SPzfqZ+d6oqCyffmOU1mzMzEWLf/T+\nlKoSQNrcH05a6ts9/xvttvEnJoUmUf/H/09aoExwqbqLqI4rb+nzL1Mij1Mj5wjZqg+RzpWMw8fH\niJRUlCev79gLIKjs14oiBS/tPttcY/zs2qHsglefkqtfKIEk9s1OKKBE0NXUYo2xaULzpfqKFTo5\nEFsbG/eTmyP2NlgcNGiGzT4KFsKcX7sZCgsrutPwhhdzOBA/8N+CfVeVEsdrP9sS6ZIQs7McQ/7D\neNshaOGNMbXYLbebelDWqbszWYtgfVphDQs3tNtemJrIcmtApxUA/7VfLQRaw7D19ar4E8ozZz5P\n52VP5E6TvxR0qnt4C02mR733IZNNNYzEN62jdN7lHbe38BYdDWlVSjQ+j/iu8H9Uw1c9sRKzhMvt\nYSbje5593WOrVBZd8GSLK+W2/0BXU1rU8o321xmPD4KzgPFpNqOVlFZBVpuhz+66JTzg0dN+hk/t\nFZhN7JfVIRWniAPyHn2JDFXcGwD706qDbKu+155s7n+ZohU1JSwKxTvrORfYyvnLkkGm7fJQ7YRL\nt7BfgeyatEZYG14LIXAYjvgfjq2wtToa/TvQDGhvQ4Vm8nZzgWZcwGS7TJsxAg9p8hrMrp6rWD7q\nT9p4sQFyZjXkeGQMbXKNj+j76S+MV1+ZlwlpMQmax83Q8n0eG6krBX8W07reDMXwDi/pfHZnR9be\nwf1owb0a9mwrd2uTVsyua6HoiqBX3Pal1FZOUICvgzVeRPQjtX+5z2m2bTFa9Husd5qgJtC018Kw\nio6hzaTDp6k0pEhuNWKxCu5MYR5qZsH1QhQI1Tvc624IFJ/K3Ay7xDjun3verJ4OUefTvdYz0TxI\n3K/tmfQB5VfrezfWLkF0jHF8SXCf/aAil2oXjvKKfzIV+wTzXtKohwD8MEfjITbrP8BbeHj4Qjjg\nGdLwOy1xTGJgUSS9oGRx2/393scsFP4J00gbt2yy4ZaVBbdIV4oPk9/9nJniWlCNrHYcY0VkRd3s\n2h1bfTegZQUVLvAzHmVWExqww+QVrN72GuinDns3uQJzkjW2oXpXU1+I8K/xOe0aOZgVL57N1lkR\nL1i82WWSl7WHMwreThqjifFVASVCTX6sg/1eVK52Ab/QWUmFtTRLUWIOVBozlcWjVZGi0/sDgJfM\nXBSZLF6a9wWTbhObbri+/RP2EJDzxBS7ImjPO7YXCEuHFqwdPBxr5pz9gOmjeSWjbTU3TD498X/8\n7PjURq5/I+TJmVdTEm8qoPvBEILhT17sOnZOCqN1sxzYTUTwOP/fh+5SFWILs8IjXlmtv+wC5IiW\nzInQYX1V02BveC/m0fmFsn8knWeUXWW75GIw8voicnX5MIB28JxYzTqzCcaiKqRigyYOs4Osdese\n1rIQSr15MSZogNQA4Q9uqpVZIJiqX0tGTYJRAdmcBKUUxy5OaslK5g4juCb+CqT435m4GHC5QyDz\nxUGN/7A4jI4VXcnL0KDU0uPNygMNYGjlBIIeSVJzFfLW0SZVCpssVP7xEDYv9oPoBQRrOeKRQ5qP\nGKUUx62dOlmuZ06pL1CFyRCnptFpfjZpiy/u0X9DAKJVLS28kyK4E4aPAlySXPnAgykaXMpq6+L4\ngwQTlJj/RWrDVVZDLpgDv/dSjiDLi1gzYGXu6QoY6yv9kehm9i/zGfAH4Nm4iDp3ttttUcdsGJUY\nOX5pBJJFOq7Xm2WbEGNOUKF4n31GtBjRcid3c6qrQAnTffL/kjQYzMWjjxtyQ4Gq1S8SG8wnZxh0\nLa2V4nn9sNN22rx8nyxr0WZxxCT7FRXBfRsyViBXA/HhwUGT8UtOaucltcNOBKQ9aGEPrXr+bnhq\nCEhMfhyJPjgUKZpaam2DDDqz+BNXGTJ1q3nD4XKRahlStabRjg2WslgaR0sUa4f1P8T98v4+AyKA\nbzxBCXiDIjjI5UCH9o6n0WB3psXj43WGP7Bm9PfB/emi58Acg56+fqEW5+VjMvHJo29TmFL8byAB\novlmPIyfC/Fii0v3LlYWAxWVA4VBG/LpFcgo9qPW+Yhz7sSZNlYWYRx8BSBtFHPZ0UDQKoIXQ/Ne\nRDObMN/WxcEJcEwTRilhQhKx6hlQ7hinqOaDY5B1GFPMN3gTpB1dC5lfOwDwQ6XQbTif0MUVz+e8\nRa51wUr1nWRmVvnL+wl6eX+bie4IcMHbk1IifHUDQJLPPCwJqQ0W/PTILBcdBSnfkn8nQdImfOp7\n+/WRn+WQl5S/4KjVdl0zWtYEetGtJxHGs8S/wOZJ2nxSnzGuFeaomei8jl2gP4EFf/WIa4OzwqKj\nz+2uN4cJx2vlfkt2FtUjeUovD56+jlPthlDUP86m828E6z+HVX7ZoDEV33LWhlQsHyKkmoiMWzYy\nHdVJabgGfyUmXygSYdEqr4ED3FjHYpkAtC/7g4WhqFvZ0TALvPcdB40O9TF3LtysXZQrhEeY14J7\nKdzxRRPsCltAu07xoEYgxU18+1twpdaZZD+XfOXHND3Y6kE3bjIxMBv4dV3AHbmPRivs4kW6H4gT\nFVcUWuPssTRNyv66CLVgv3pLFaGbN1fN1GBG2XQeBv+9kUDCq+rBrqgBwhSj0fncbah7q13tfYsi\nqMGF8LzDq5M97C3HMEMuM4FfQBc0zP81oqicqoWuBh1mhWihKI4/ZlaRO33f3t8wPtZ5Nqn0G8GE\nUNlv8CLzYvaC7tSaKV9gJySIfJKQt6yEnk4CGj+RVRu1UA1/0Er+TlbXajVybaQRgpbkQWq58eU3\nyOaqQ1Nc6JIJRNFNfKNfxWmJlQJCMbbGoPS163X0V0rQ8l5UNfYvEM1AJnntSTTZpcfamyGcrk1F\nydtxqkwn/hjqbFePqd7AqmcKjnKUO8ZLM+mkQD9gvnYXy8VMY4JM3F7mjELqgskwNrDfqk7KYp84\n8H92vTOvdcxMbuELQOGt+G0tx01omR3v2+zCUYlWznKkQJTzg7hSduynfrqjRa4s+ukUMKw9nW6s\nMH5T9pqhfXqizyUg1dFErIGw+8Nn+ezQ2lycDwRRDq5Q7kyS6RHPjMeqERFvlIbn8kimWfeQB+gd\nDYrZ4Sea0vnHhZ8T7nYIWltwn6NkOjxMONqbv5nBAXBhf6rU8M8Upjt6ub1Pp7fpd5Z4O9XOIn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XEmW6zwtcpFPQIxv6hxYxwC/spdTrLGoB4ILEP+NODQpYsELTZi9WLQc6L/iOQgxB2qkazE7\nznpYIqd971MHDyIBimsMsV2MIlfJx+fbxPxgOLnlldWhu0vSMbvH0tKsCaqq51bg80SjHoTbLdRI\n0RXKBNHiY/hwNrAd/uDNI1VArQPSevUJihWecel8HQA/qErqDeuyR3fvz+etmwA+wEarTYrJTqBx\n+0gxN2lWRXXSb1WzVOI/HRxWhUkbQg5KGLcd6MW/+7yH/J74DfKqSSUFnkbQtw4D3iiyobxCMVEz\n//3tVZ94deYB0NSkbNhQwYVGtoYwo8MnoIs31fabSPiDq38l7xlx9fp75ALhijgOEf37nXuBTGRE\nroDKkPV2KRClavVRGPGPcF4rrGho2vJSIvjU67WpSxyZ/hef2sjInD5/VTfOHdjuUA39/udvN5md\n5PU8SA5cevPi3hZnv9LPMedfbs8OfRpINO1/cETQpi3uun7In3BwZIys6d9lrhe0okK1aRQK8Cnh\nqnMJ5Yk/vCW1DzxsS0YjsZ5++CKwZzuxv+pfhRoA360JbNFJ2+BnWfrTDAYfBh3X7DTAN41eWGJT\ndNIaOmQe9nucKLsM+5bqmytNG1XR3x8eQfnSG7y9u95+a0KSMLLs8vDW4TMjY7wKGfjMrcLBXALX\n5RdBS8d7iquImUPCqSe5fyfq8aViMuTA8JyRpN7reZ7hr04/nzBj5v/GYAf/fcwf9/zsj7pkvu7Q\ngA3tRRZn7bfQXUAh4a8r1qtWmNvSRZjlNWf/0mlhv3MlEmSS3VN0lREGa6jOvJOOx7rhOXLSBPTP\nrhkBwriy03trzUP0PVLbhK+GHV8SATZ0qhsPJPvKJ1ArUmrcalWO7R95YB7EZ30RaQUr8LDu8H0H\nxSfvBDwdMyeOuWz28PLk4bAYYi1GFnYL3c+9aBO2/cQRrQOIR7B6zDTzfn8ZAlxv+JYcFcA7cDdS\nneY1+v1AEHA410TBSGLSJ7W603q44z94d7QgfZKpq9JGZ8Ss+XuzuocrjtI/CwzxAYaXJAfyCkLM\nvSecX9VlMHY48b4tYVPrX1WJPcL5vc4bTwpv5yDhIsqRRo4lpshMtpmjP/LBQkThJMDwD4Evjxd+\n0Z5fgZIhj9Cesf9L2z7FA58DJ/shqe5H6BxQXh5EHfWSUwr7+FGISDY+aOXzkINZDYyhT4Qc3M1d\nOp5u/YuAiJwVw0oS31g6x+nPXEvDwGDKIO0jR6+C30Wqzb2uD73ACi3CpG0Pju7LE3x7sgwWFaqP\nR1UHgtF0dYf7H2mg2E3Jvz0vEn7MLjcTcCLLvU551616Q1+rUxIxuCVVppmXP/ktQRbLUsMyXdfy\nEN7oeJSTC5WEEe+ruuQFCDTKWJdT2y0pdFnqTf2ppYzWv/n3pGBJxEdDfXYHh9u/s0uBYf4UjqdW\nkys6LWD2yMmnuC7j3ENi77hkb9Qjl2aJb4q/BM+soWZt+ENkM8mFnzNODGlHgiLZlOivoIO4IjDT\nBguf2s76miE8Y5v7LW+4nz7zaAzAZZrtrzoR8mPrEoLsw426l0yobffsmLCoxB0Myjxs0J/P8V4/\nWHvRj8uQlYUXrrS2N5l1TWLrnIRYqvGam//oUfGoVR04Bsr5BsiUo90ulRGVW0U8zFC43lotvhXY\nI9uIv5zMi4kvR+nv0IiHkozj516FuEBJae321TuWKRqcMNkLJjM0K4k6x2V7fexudWDHVhskWRpt\n2uQAgpcdhkCDKRctrzCKI3GumkTB6yHazXLoWdpVJ4nlq3TwjQiQ+FOK8VG7Juv9qDoWxTEwXLLT\njtJla8yzDow8WL7U+/9B877wQveVsQ2a9OJ0avMJCtrCgZt4IXYX/lmVkkIYi35HVACSra0Yc1TE\nIpiIqWFNdQuwsaJe71w/LZ7wTfkjeVGaxK0A7sSf2+WmYCASD1CkPFFrFdSXvJvK8IUNvAZt+gk9\nPgN0ff1oOOnee5eda9NIQGfaH7++ZnwFYNZ3JUzh7aP8PLUTmDuIUcEhtjMXZC7eyLGN1xrxC6Xm\nxxqU4iBoCLOpL/h28ZMnNPN3/L62xF/eXFI1K2c1NiFp1NcI/Uv0MP+uhyQsTsx2KA8WjYRHyqe9\n46ma8xWeqTc8FpQH+/SNsISHnF73a0dCecKtu6hKNrOLslP96Tl+o63d3HvD2JUGHkG4rEB8PzKN\nIG/N9pDhl2GaeIZVHaWgMC9dzD8ms0fWghnIhCfvYHErSkD8icLH7Q8OyhqS8ZUrhB+Ye6hnH20d\nGhvF09nRJI7YR/b2nPE25M33KKEY5ejkELQZCtvUhn1WEFtH5alKE7dXQG/jjYYTVK0+CbxVbBeZ\n7Ew0/6sJYi7p7QlWt/RihMVY46UHvglpKJfzlAmyPi3vdxpoEQypPvXCL7gOkR1cJKu5xhIzJ5t7\n0hT4uN7EMvLo6IfiRaKGNeCjrHmQ6nRlL76bp3vJs3/szupk1BRBTId+pKkQOlPZjq0CiyEfkOR6\n7xAEu8rgPdRSiY142Yr03ZfgL1tjSTWPwbqe6yXZJHECCaKhS8dOwv0iG1HG1xqfCpDb8bGNG5SD\ncJtGHW1H/y5DkRSh1qCMPyfyH4/v1T/E4/sXAUigrTVxwaz4x5qzq8sdSeVPJ6zEkLLm95p+QG/Z\nujUA1GC4Kp+JWSbCmGIGmH5hywCzcC5aZ7AmfTYTacxrOMh7eHq39R+INTMuzAjRsR7wgxvCfi9j\nVCrjcKH2e9tWJqYS06w9fHygPwsQBnxDua6ufBzh1vXJw9p+1YSqcdHr2J1GbaCDH9g/QIvGU/6O\ndbzF9qmG7acOplOV+UUN7bPImCfV4amD9Atdpn/yCqr17sbq/XnL8PbEfLFWwGtxeTDJNewdRG7I\nPuwOhE7/lAPAbTUjhdmGRU5jtZxwizcz0L2uya35thXsjXDoa6rM6KEoM8AGcBK1tb+yd7PGqnVV\ntl1tPRqgqsMj/Xfk6jwPKq3lc+rwQykIHRcKtuqFITMDLadL5ep6HMsOO/2PjRxrIT10V+AWqKcB\nWLdowlVBAqHvybs7xj18q7zmKGvn1/Z7s9JF9HeX+DM1keWzTV9lyDS8cfCEWKfxCCEMi8KH54Qj\nEzrbqFKm7Fwlg8Oz26tPJ6cJolCH45fSrmQ5PmfPIbAWYgadv4hxIy+8YqesRGAJS+JIa5SOSXAb\nATecjyYRjiHOI3AS8/HJUC3fqZ8N9qAX11K9lBiIjeAbccZK8eaJvQpoXGMA5/BH0vPycGo6k8hl\nTza8n1FJfrMyIORyUNwP5Peq3yZFkXNUcnMjt7tXqHfSWCwg3IFwfmOAgLs5w+K8IQjqtJZqxtv8\ndakxmjezVpTcmWXGsnw99P9JqDGt+BqYzoTXmJxw2iUPHthmNl6jiRoh49BtCqHRnQgIj5pNFX5r\n8t2qFy3ToUPQLoIhrYuIfhzw0AQLDFDScB/23Sk/8pxu19MVCgBmkfh/2xMMKtRbDkLQwTjdwpxQ\nrqEJ8nqvLO+tBbczQsREhamGHxOUpgAZam0D/KuSIlERbp1BpeZziflu3F3wDf2icJEXWOzomO0S\nnodxZZmHYclWxNI/ZytanByEfYfTNEbOvhpHGASwciuVfAXSoXNV7cVmuRG7sBuTSczVQJP0cjeD\nbfzIkwIhsW2Njg80CgQT6mdi4zfsAb0fr80e1VwVbWwtlX4ofhP1JmDrCrDU+AxxV1iJsCSzS7AN\n5aOdu3W16RzErzEE/1um+Ev7z174+8ddYoUfOtuFxVvAElaTxFOt9vUDJ3a5Z4WNvJgPe8cNt8R9\nYfuVdgr0BeqEC38Mm2VemwCGWJiilw8ZNufPdaDuT5CKev6WQzm2VpdCUPYYY3j7gTd23FeyHfZ+\nzX0yCzO3DJT4trtRE6sOb133kXpQkQyw6c32bsOGEHQ2MwtPveJMyiLcdphCUSbZygAY0Wm4OjtT\npq6LXISTFqDQGMYxqDI215O6O1e2d3yv6JmcN6E1AfLIkJScfFfda+qd4yuqjCTuj/65YSaMNf+z\n+SnvOvjH45e7Ad5YSVZ7pLWHQBLz+jaDxlZDwwhfnUCKmKLsz8mKHMw6AveW9NnUvh/sOtiLOd02\nWQJaSR/GcX6plGQLt87uWd/Se+wkzsTJ8uapmtIznpPZ0fg5NY7OuiIjmj3X/cxbsUcJsP4QK8Yo\nXMYEoSVaU6M7gc3m4CsLJESDVWv9usg/ACikf54onEvQw9jGFnP8AV7yhFIZLvfTg4xiFbNjRrcQ\n16mwcW0Fe6L1BAPAPhrb6wDKTI1hd39jJ52C1XA2BpBmZ5yGkT92S8cH0LOJf/v8yb7ymcF1OPYw\n5jYG7X5OUOCrQmmOlINIVsu8XHMlnRa9IDv4H+0ylUJnE2So7kW3rjDFNDyJpJ2yJi6NlHcxpHCW\nm65qtutuY+kbFMpIWHpxjs1cQfiQPCBISnJFVxNGTwgCqr6sHj/5ICiIsCkCO0QIy1jEVJDN2qVk\nl/ZVfIdNHng6I7vy5BzCCb63/mIDlBbCjFiafEPKSnzQwP/0N56D2ImUBCbYSdsjfLV9hiVIBYpj\nYQnNFNDu81Y6Ty/Od2AKyy6UjTdmLb1rdqkGnZ5qqAfhwM2AKZ/XoXwiurBa7+Xgwy+R2jBggubw\nbeRjsDJa7gU4M0gGheeRgNDnoizYw02Vzlg4k1VnPjAsxNr5XcW1BJ4Jm8vjEEXBBGGvVP0psXB+\nL4iy7FHUCgYPy8hYFqN5g7hLvb/wT6pkyNoUMoj6h+9GrrTy+rnjI6kGmNlIsSYu15F7oQbA+V9k\nkLTaiiD0deoYHRklY7pt3lUK7rZHQKf/n6Vx10/80i9aBofpZOIi3uyImyCN7hHcCCpYnvew8SZT\ncfFxgKGYa7V8OeAxk7jpLBvMxfr2ARp+Ep4D1sSRH2oSzKbtM/f9ncdKLxEMHr9wxupSW+XoOraE\n1yy49P59KV53Y3YnD4miFcBODs7CRM+6bqoK9hO1K2W5kvfodbOzIB1IARSmOhRwYdljB19jurPE\nYU3GUTC+u9Te1SflGvr4XsqCbbGMLETHb1HZmXendPnGcnneY+LtnYkbqK7SkCN7x9OkYrdD4Vsq\ntbk3FZFRMB6EZ5WZ214LiLTHzEmLckyG670YR7BNLjK1rQInQAgxS7Ri/B0TGCrTYRAynDMCPXB+\nEBZOhtu0kTKOAVnDj1uOhBFDA7cmnm7e9k9QBKhHkPOHHz6q/8B+iEM+hX+B4q9fpPM6oKw+Y+1s\n8b1LtwySajwDTHtloQWcxc1uR/UsnkCWBPuL9DMNYGr3ZmKTEnGhp70LePkIcfJYuwsfo/E7aCW1\naxn2sWtKwZrw0+CDk0QTotfQ6nG6Wr7hhUAnSqfG2O6kYjQyPSn4k6m+aEiUWQ48MMUvY9ABq87V\nofVf0Efv1OdyGUNFigWmZe8JDvXnZiWw1K9gwZqBldibpaASp9bfFJgdiPr2CAGTDl+r8eoMd1jn\nBbQ2igsBTuhTaV10ZWJFSAIdZ4+V3HYLkLU8oSRXqIzqcI/IiAg5SWLWSaeHmkCkSbn70TQGXGOF\npfjhv2J5yzmkmWDiwFq2qT5eWOMB38FWcEeOtiJ9xvBgjz0qOyAP17fXFxTm23JpVYazHXlTlnnH\nxJSftOg+EKpf3k7fWj4DxyytvhYqXy/Cw2R1dyUtnLFEbMzZd3Kd3ejeXjJdr8nuiqNi+s7uqd6f\nln+VwVZ9a3biIRoGDPRIqfXo5untTcj3xHOwq02XjoFfYNwh12xIfB5ZpUmpKZj34IsNZiFggBr6\n6jqqGibpp2bK8BYBtgi5WPUHkZJIuu/COkKemycnSDpeAv9Dc3KRz3nwhCU41HMq1xWMVrrY5W/B\n6Q1U+SBjTYpQ04mjzFOvYTtEim9f+nV2S1wghga3XTYpWdtpng6n/69RizgI6R1dyj9sZOcdhPFC\nLSFGTswmGoFRGvNeDd01cU3XMMT4u2Z5ZOJ0f9yEb2V0quk1hIqMxHLPaG78pHgJeAtI4ztI+h8x\nW6bMzRi+2SADpd92+2fWMSzXApfsMfb/CJmztrl81bZ/RiWoHQO7FahUXnuklE54bClGGhaEsp/H\nJDvuGKJi/CWrkZltXV3V+Y9rHOa2gxVtp1SNceOD7LJQtxy0tEh8+Mc9z+X68qvpUrp/u4tsNXDV\nXsi751iqAXXO0dnHOJ6OM0o4xjFty4aOINWoxA+xCmcx4EJTLLggpKAdzIwtad13EDly/znQSFLF\nbnp6kOJKqe0W85XvkYnXQff6cnhRSWsY8q2CG0w18siVnfa3E4xAO6o6vcJsbyH18/PAKl3e7Bh6\nNTN5XB88JkKGd58BVcAOZpxLiupbboAJCvsueNHTlyWyvvwbLqsDVuAJBSHpPs1cFjLtkeiTGT+a\nSrqsgMO+UHPBsrwvBGWtDxj3TIKE2Bnvjmq3fKgev8QgzmUU6ZF4/FNAnmzGpTTvADIiUY9lHdUv\nE12u4qX+I69/sHvIACAnIwYXNbd7R33aQ91VJeAcxifdcZA5v9C3ahUaFH3A1RK+enmmfq3TzpVu\noJN+l23KiY1hkUYhiR2aCWIXRySCyiY55+b1G2/fRN6+GV6tJ2/hDe+vqM3JlVPptTG3ZIX5Xn6w\nXYIcd4doI14tVLSyAXT+x6QXdffSrHe/NgPJaYs5pg3BnLI3GSDNxlUE/pU+OvTXDTutF6naLbGk\n3H2+OtT92hDETD3Fix908xWiPIyeY70Cbx6Buqa8znPrRqc4DyitrDyvoQlrTxSwsLstbSVHw7mV\nHsYKgDvPmw1+ZSb9KyxoMxkr19CiTRb3JOrETdiA/VQqnMkjJGK0IEojw02kx+ft8nWEvJkEjXTT\nvyjahSTIEhA1jVfUxN86LHEucrkqhb13um/j1XrS3GRfic1TgpHHW1S+0OcCHpiKzX11xznmgBbt\npi/8dC8uMXKveFYefwObSfPZ+WEbNUFC1u1Mtd1FGzNLljP9SEYPCSYTWYIzMmwRwWT6betJJ+MV\nq/08MKx6b4l9hUTYOylZcrfrrBLhb+qmqYl3C4dEybhehzgcKYDwq4KVDUSo7uPJKSObyezVPZGp\nYxK9gGsaTY2Y1vrww2p4LBm31MsezorYaIvvDZrRulc378EkVjjMFY74VdMTXqb+rpjLfZYvEheR\nltiLMDnzHFMTLx7MnxbGVbuTWXJtisMsbH5vXoXWGEWinvXUjir4yICOZiMgUdQNG9dJKF61yV5d\nD8vuzUbVZWMNKO50MKFFeQDEIi/QK3y9S7CoVspKGFiX9huOjtKEFypMTRvN25ZU6IsPSKFyBU3G\nsf2LC3U6O3+Aia+yJnOJ9j68fJ4j/y4h4EZddq3di2jiahqK6+92jBeqa2iljZiYWvUWjn1GLa6B\nmAddWZnuVAaG7sBULE1a2OvCuqt0/rpv4E2T0oCtg83dwV2wF1xwvR4TTP0k3VJkMDa+bRc6F1If\ng2DHdDMHOJ+zr50PcE8q3ATEQ3aRsHk3kiBDSNjCLxAu8Aloh4dvJok4QPOA82ahFUluEQOphCXJ\nnoGJVkBSWcXhXojWVO2iZmFMpOVj7j7CK7BqYLDRlfM7pQg0hLVUf+8hH8DhQSjK0e4V7/wJZLTP\npmLh/NhqxxhNtRDUhEa3xSQBmYRvWk0RbL7Z4jTo5yamAInndOM6Pz15AIijBTmggr42FdGAT7j3\nT+Hsa3nAUQEAshewF6KGwmCpKUL6hJwVxwujj3qdOYfcfVJVXWy+j2BjVZF3yRPrb6ZcsBK79nqA\n6znStSrjcPRpIMR0WyiPVw7kxu8u41VKTh7+x9iKHXw+V3xz8LDyVhCea+Lu421k0ftGM39elZzw\niICuqn848ke6Z7HBYQQcmBZLAnCjpKlEfKXiBiXC9/jrnytaxYWEwM1XfMDvfrkot4s/9EvpHeoK\nheSD1gXbrFhPXM2+kcS29UIcUeqaXVoFbCth3Q4gQ62DHteN0gw3hY0UNsY9Q05PN9qWfQoEZuBr\na2Bzj2u0Gt9YJuiH9AjxbWdYdJCoTVqSHPFsfTG+SS+TX8PcfGlHY1VZSdrScBIh1mWOl+bRxvvw\nt1Tr6dyDMLPJXu/CwyCj7teA4QrSMaPNh85K9Dylja1im0yXfAR+C7wRmRZ7Dd7QeOV5hvEC0YGR\n8TZxe1HAae7Zs+dfgdvBmR0esfWzNoda1mq2QiWH6R05QM/1sLqzdodSeB28NPx9WP2IqimxNBQh\niv35VU4A3epX/FjfVmMt40C8+kH2eC+fry5mYwvLXIAXZisbdynQAnoM+GQPONBsjaTyOZptbijq\nx6/Z8Ujz3G9XSvdiA2SVWuD410cnGgQrcWQ3tDBKfsz469bMz7VlELQn6SUzoUmTVeXqlunLMgAT\nZjAFpyhxsekFxEesgRUprfqnBWj8WZiwYk+++EaFrrl2LOVoKTGlASaf7i7PCgiMuDiow55MtAdH\nUQ2BBuXL5Hb7cpA7Qv5m/wgDTkM/0KJe9wVdZ1x+8bqBXTFyDz51576DrvtZtAD/XbJnA1kE5pDO\nTIqF52tj1j095Awo65eN1D9llYHxAe5KqySoIQ/mUCts9O55Ttef/xCU3rgLPln/8KfKrqhanX9f\nQytLhGJplYSQ+JeTpwLQ4AMsrKC5htbluB5tV8y6yp0i2ERPTDEqqtq/V7XMiqYbdH+04sQBR2nE\n4k8UUrISsEJt1r/1p4kKu08UaqcNRB+543qvLgCj6oYuFvcyZ26VMqgmFqYnLBBt6rxv0NbItcuv\njnXcTIV4DNLBpHsCGtPT6iKVmV+AarzOVNre2mZDZSjxENol85XuFWZKPGwuQHGf/13N0FwUZj33\nbcAaynRH5O1xKzw6B7o/6QOLte8t808bN8lTg4RtVzap6jb2nZQ79xfViEMvZj4TZ7mREpQb+UH5\n5w0c1wRH6IQcWeMYS4tEKNOFbj1fgfFa5WqDh5RkiRSuT07K4kqQ0IDvbuKVkJLaGtrQikvV568j\nJtt1GYLsDnJvj414UYYVlISVETETB+9wP5/n9mMPoKD1REvPhzX0F436v7GKY4JczyQWlQtdlIMy\nHSjPO318tn07kwO3cAJ5fsIffJCCNagrTfspZf9bzICnrQL6maPSuNgYQgqFwfDF2RM7YKFE+zpQ\n1JcpFaojBF1JuaWNYohO3O3iXCJB/AErTdLoDmZkRGr7+6yhSCU/MqKmeu1eMpbHzscQ1l6VgAoj\nh+JdxnWiH1hTvWfwHuxNuwiNd6hyvHjUyakzZlmJsCLhEWk28R7wCG+6TQMA1Qsc63dQtHvPUxkC\nn2VqxSKjMhSxtS2iXEtF2i4gqnU7RrlZPaNwq7N8FfBAIovNAkquXXYkv5QqOch1Inbmi4qUAA1k\nQPEde2r+zd3qjLYuEGGSjcTd4RTxuMzh80+//d8arJdfJKpgc51kD89xm2S2hti42Db5ewQ/NgEx\nD5Oc6V+9Fp6zaOdR68MZ1vqFLmPmxrnOc77er0e4ciLRpueVvrks4AXCvLpDexU+qwqJpHcO4Nsq\nePNG3yBCFBf+OkklK9K2i96oQfq61gTjMYDrqdASmgo46lvYVsliKZxiATnOtrw40xLe/I4HyUek\nUzpOa7lwnkXdKgZe+gx5Q0jxiJiTE/F3r+2UpJTaO7MRcwplFvXFPSSbDHfKwF/BQjoMq8/pnM5R\nqZYfGin5xwtXkin877nraCfD6s189FrFvYKq96F5I+uEq7n74mQyY274WQJw9Pq12zUEbQsDg0DR\ndgsWPYQEt21HWe5pj1YjzKc3k9dC903kOq1+KD26+8pdMcpvICRq+WJddxHfZxl6ec1XAt2QKB/w\npyPg4yDmh/5/aEOuP45dLO4gUbGL3EinXZWQ+E1jIJoSnHh6vilbDhtX4e7DJ46+QIqny0h7R5eW\nsfDz0mHmHpRxuhReQWkB2yJeHEe5qYDVKFzzV+a/yM9kAxoFkRxFTn9o6n0mtJORZm4wxoGeQlwA\nIXr9swVxSPgM0S8/RwgkdEGMDAz+BfFrjvRRbbXsrQK3aPWDSTFswnscfXV7EW6+nDVhMJMbes+D\nf4yXRYnRL45CqKVRwr8am3VA8FgN+DQrwIvAbrZaiZMzBU3TBLFQnt3zNny734g6Ufl5gloVBA0q\nt29E/m/RIobK12HWVG/5m/8MNwNY070i2VYegXW8o9i74wAONxZgngxdmnerN+0Bmu5ugMhe0V92\nT/X9Yt9A99AjMEGdljk06tBlYIWLBBv7JdeUmUItCy/FWuPaUZzUGLKbzoBfwXuQG458SVeCmYqq\nKCBgyFSQONeMJe7dhcaNg88JTodC+KDndvWzuL/Gu3YGc0LuoOFqIE6SumcamDQzxQSTHzxsJW5D\n9+WgLz7d9U1V9dZkBWq8WC7scYXmYEJY2TVNJjHVgu/DaW5+XOEKNkvtj6pDnGIwi1nRHt/ywZEv\nMkcqF+WVwZAEUXVXzMuF3xvk/ytRRhgorncR5sS3ArptApRy/neZT/RDVsyV4JDMGSdzgvweGLjn\nD2KQlEpHOu1r0lCWsdTnBML5Ya5tXGQcD0s0DXsJWiJqHyeWFXE8YmOpRBKrnBiGLJaz3D7xF+dm\nYF950bejYl9BrCezc8s2dFTTXOiPC2aLtsqtvhGaPGRNomr9s6FF5YDKECFX9Gtzy65jD2Uxi/tQ\n528R4MC/Kh3P/bo6d+mGGThuyYu/w08SZJKPSMmO2HDiE+mtRVzR9pP+WZ/MpeKRWYf8JZZ1cvz+\nQ9r0fJKYmsiQgj9LJWZYCdjz3tupcrvAXARjilyqBOxVIq2OQzjnIINDF7IvpWnGaenn/Ml+wiLF\nuK+niFvzqRl0ZzeOc9MHYQii1+56TeTxWGY+DM1kHBxBOGVqJVkIwtxkFtjDVk+Zk6HyIPDCN2AR\nms7Ojlj8L9WJyotBzxLNdmBQ0dGc1tpCwdthepMi86OcbLBDaImZ6elWWAFQx/1seibqgSYGXwAM\nllhCxzv1smGoW5ScDPlgpzxfrIsVNvlBXRBMTkmJ+qOQ1/ZonCBNBvc6wysO2/bRH2q22N1pvx8Y\nMeL3M30cfu2qmswOY8Q7zJl7tBMfeaj22LgZsejWPOlhwAzfQWVy5IwBujhIplfaAel33LBOiS/p\nAkS5XH8sMf7x24AVDupRC/hXOAy/awmE5KNbsFq/OL14Ptlmnjpyf9NEh5ea/cw7fNWpTaK1Ozo7\nBa1/0RAk203DiiRfXWBNTVH2047nL0PGx5U0jzNtxRJtrx7qOVd0bnP8bRRX0fgGJvrI+whKaSa2\ndI9EJ2rAnBxkJrexb7OzccL5GW9f8fOd6HUYa0KUq7s9PTeV/hqqXND6gZlfbVp+6LRn9XX232ig\n3TigRnOeqs5gBWxf+yNhnbttVTrVkhyHkg/4XF/hGzljDgM3xhGsLlAQYBlu1IFgDQKB0QCcqLB8\nuT+ItAHiLDsKp22zq7XP3hZuPvXsiMVXhk3gzW80XBjO9YdryFgZKvJOslBV9LRpqDLqwVjbwVvJ\nFJvKaKH95Kobys5cQLXhCVkROVJNghm2IzD+gAvjjNNN4v1g7o0HPABDSfWhWSxdr3Q+M7NvmgKg\nmX4lG5pYL9gwmWn43rwtbxilOwvejyvzUpDsfT7sN6rywK4FiicOwdZu1znqp9rTkkleBJU8oWzw\npMUGzh3EvA3wmUx+yi2nJAivFxWtCIBBLF093Qk5TZ9JF5SsZMriphe019NHeJPN7VM0igq8m1nB\nMNsGXrJNqPg3d5+VMFqxPsN1xlVssCxiDRU7hLUnSCPJwOsPbrJ4jJ+iI5Eu3MZqffJdPCUKVxX+\ne8VIBYaCIU1n88ZRBy0/fvnfyBlP3rJegasVh+Gw19ccUnEcs9NjM/kJdHh6qCi41KIxuTjFD9IL\nuJakkfHei206Hx86Hfs68M1idoaz1YXPzE6MLxYEHPJL/jC8wgpUZbfDQMUY2fq151hTgA5UrVXn\nzNvQRvIwp+ejQ2rq7HsJh4xpyAWWp+UNkpIIGfCUtHjAZl5HT30QkWkdsNytGN0EparGxYu8oIDB\ng5rze1cL7TqjaaZth3GqMe8oc6Ee0mdxzqr6WT0jcmT9C0+Id2YSDXTVsKA4MPNekS8nIvoD+FzK\n3wunleyNqhPmHrATn4TtGMsq7mlqvPpyOvoW5T95hr0vyPIYpnDBvJ2EE3A+GoWaeAMfVInayQk6\nXNjWGST0FMagFBvciuZTo/A2VTJLDygqcDZPqqZ+0NfBGuJwo+CRzq5ICxtDwv0oLe5kj3d5G1qy\n2vqHd5m0/71p3ZseGeQM8DgW7Hqv36f7iGKfaXQmvwwIkOY8H2KYBOpRuwOPMwj1Ez+LZipYbyI9\nmKj9lNhNz3+5fIKZFgF29TCo6d6au9imnNXR2ZW7fZGiGKIOKv265X3hNpcDmYeyEeetT7nHsAlV\nElEAcD62bZJAp0i5Riea1lpN9hD7nin+GHCGsCd8W9cYSE22IJKvejLcO5WgiW5lvqCCDCvfwO9I\nasCxXebGi4uqUSQJBxRfSbhVSG8FeKR4XldRaugEqxc5/843LFRdlm1V832Igc+G8q/M9pmobo56\nB5/SwdIjFyaaBofHMML2Dlv/P5YHqmWOMGyNfBRWRtS9gcE2rNA5FtcXXli9iKiF1v6ngG3GKJVS\n1zkwJNaHKKV8OMARo/c3JSYi/l7iC8eWvXxNDMKc/3fjIVgTCeY7RM6H6cWYQQdJoPqR7EG4bDYR\nosVI79WGWVefVhS3TxGX8UYWAxQLbwhbOuie2aLQBy7YXgMNPgV8PIPPHFmVIzHhEZA1OuVkbi7G\nGFhRIUifmPq5g6EVr+xX9TuJHZWSJJUT1/JUWNRNVOu6XNpNEeP1S2ghf6oMAIr+ISdEeDNZOJO9\nwXy8Rcklo4dPaT+lHianOxRpRHEX5YMO55V6aeibuQKXJRwjgfWnbc0EKoPuor8XUbqug/6ZE7j1\nE7yXZYS7KtOsUnB17h6KzjGFznBVRt1q+84oVWJKQIROClMVT9XTjGP9kFT70snh1O9nsL/grGB0\nfUzU/WoBVRdp0oFtZ26Hk82ha/hl++Uivq8UDIol/hzYkA4wQBuvgSSCvkmMbHWQLfMHy9PjciE9\n/e9Vjgvc9KbFGHTb31tbg4MoGmcc0HGO3raQPrLTnXfdGV3VWfGKMfy/RGdSD57qi9E3wNrgGMSP\nBKiCjKLPLI3xHu2qsaJJ2F8uno+WVTOfp2lZxEBWxLGsES+FmU65TrT1fy5ZCeIeaHQabk/HcBXt\nF1uSFz42aPdTZA0SqK5+4faKUTata+cQjVPjsAADtfrToRZy2d+6EHlvXC9ksn4GH17OlPSdv8pP\nnpKDZ1eaJxzV6D8qqVXPOFttt360qx7cWRYCcFenhFVUpxBKZfuQEW7mYS9lVhghyDTWX5chKYKm\neC/efWFFT30OfTwIwInLus4LYOnj8WdaxW9uNOTfZoric7rUiAhwkJb3wNBW65F4QwRZdlyJ1Feq\nkEi+rEKgRdqli6dElxf6CVDapNmiUshH5HOp/PN/FbkZZxw1EZBecJ5TzDfX5rhFCPZqvWb3T7je\nx4Rg0yb8S4ora4wundEjGAzJvfgGZlpLsiHC/UJe+I4zbZAucVG46ZmOgKdt+Z0m3YhyMH1RA5tp\ngR3G4qTnB9TvDF28GTvh5m+KaTNQxve9wPIRpTpVveO39FeFWdrs/8z/yfDbqaBSyFBkaPFFKU0E\nnjRhobVb+g1SYKEkDZYWqeJ6jOLhSqsmpktl86KRKj5T+ZHI0KDotADU2BybQyijJDyR5TvNLU2z\noLnSh+nuPPP/uQ99UDd/ES+CYINuFbbN5iv3ootOk752D8/+eMepxL4TbjcVeiMJsglorDY26rQb\ntHspGg9kI+tmPLftbvJLY1Ah/jkqc9e9dJrx0Gd2X+zVGNFXtgRQEDiG0HBcACcNuC0sNo8ufju+\nDLi3gbESCBkLR5/Ku6ErOVAIaS5saiy4aDoQnu2wbBZfRvVdFLCJxpISgQCcyzt9/4Ni3fLtQqiT\ntG/HKy5+RvsyDoImtnejDJx1REIWGfd9yxIoLnsb7gSJxk3qqKd1HZJRBpcVjUQ/g9EWWECeSSl6\n4BN3NqO9qO2cEU8Gy59FzzD6Nqet0wfwTgbLbeI1ULxDlaghm2HBKvemR//cQPfelFaw8oT0H2pn\nE5IBJs/LYwG8S5XcAN/bT1DfjGTTPIqkcnCuKTJJPisEplPXbcpn9c5KWjApA4dBZiDuABxt4LRh\n9k0hb3AeHhWXvrYWj57EiwiOlS3XOg6iJv7BKgiZC/UJz4yuH/J+IERjAKj6dQ0pqveXN5Ghp5l1\n1hUwA/eKbHE1h9S+2oItwWl1gxNcmjYk3i3ogZVpSmkUoxeyVDyNTrZviXD9FcFBgUtAGOaEetbq\nZFyHbI1B/VBG33BnvSJ2WgGyypH5ggV7azeAYZ7djam33U8yU0wMIMtj7bTxQWnhhEITSH3TTa9E\nndkI06pkCNH0SA7tahb3c6IUOkrLqxZ+1oR8htcEE1AIEpHTBX4kNQHWjAJIxLC6KI//lbj4hk6n\nXCIYAKrm/P7sFmWEwDD8AQYqpChgDejn9MV+4YQYreP5x71z0l5s+//OS6fNIY1YQqlKAnJFgSiS\nkL8Mop5IvPv1Lca7HioxXCMT+QXJ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protect end_protected\n", "num_lines": 510}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_sde_h2c_dm (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26,\nprobe27,\nprobe28,\nprobe29,\nprobe30,\nprobe31,\nprobe32,\nprobe33,\nprobe34,\nprobe35,\nprobe36,\nprobe37,\nprobe38,\nprobe39,\nprobe40,\nprobe41,\nprobe42,\nprobe43,\nprobe44,\nprobe45,\nprobe46,\nprobe47,\nprobe48,\nprobe49,\nprobe50\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [0 : 0] probe1;\ninput [0 : 0] probe2;\ninput [0 : 0] probe3;\ninput [0 : 0] probe4;\ninput [63 : 0] probe5;\ninput [7 : 0] probe6;\ninput [0 : 0] probe7;\ninput [0 : 0] probe8;\ninput [0 : 0] probe9;\ninput [0 : 0] probe10;\ninput [9 : 0] probe11;\ninput [0 : 0] probe12;\ninput [31 : 0] probe13;\ninput [9 : 0] probe14;\ninput [0 : 0] probe15;\ninput [0 : 0] probe16;\ninput [0 : 0] probe17;\ninput [2 : 0] probe18;\ninput [0 : 0] probe19;\ninput [0 : 0] probe20;\ninput [31 : 0] probe21;\ninput [0 : 0] probe22;\ninput [0 : 0] probe23;\ninput [31 : 0] probe24;\ninput [31 : 0] probe25;\ninput [15 : 0] probe26;\ninput [31 : 0] probe27;\ninput [15 : 0] probe28;\ninput [0 : 0] probe29;\ninput [0 : 0] probe30;\ninput [0 : 0] probe31;\ninput [0 : 0] probe32;\ninput [0 : 0] probe33;\ninput [0 : 0] probe34;\ninput [0 : 0] probe35;\ninput [6 : 0] probe36;\ninput [0 : 0] probe37;\ninput [0 : 0] probe38;\ninput [0 : 0] probe39;\ninput [0 : 0] probe40;\ninput [0 : 0] probe41;\ninput [0 : 0] probe42;\ninput [0 : 0] probe43;\ninput [0 : 0] probe44;\ninput [0 : 0] probe45;\ninput [0 : 0] probe46;\ninput [0 : 0] probe47;\ninput [0 : 0] probe48;\ninput [6 : 0] probe49;\ninput [0 : 0] probe50;\n\n\nendmodule\n", "num_lines": 163}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"ila_sde_h2c_dm,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_sde_h2c_dm,ila,{x_ipProduct=Vivado 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DTH=1,C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PR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*)\n\nmodule ila_sde_h2c_dm (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26,\nprobe27,\nprobe28,\nprobe29,\nprobe30,\nprobe31,\nprobe32,\nprobe33,\nprobe34,\nprobe35,\nprobe36,\nprobe37,\nprobe38,\nprobe39,\nprobe40,\nprobe41,\nprobe42,\nprobe43,\nprobe44,\nprobe45,\nprobe46,\nprobe47,\nprobe48,\nprobe49,\nprobe50\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [0 : 0] probe1;\ninput [0 : 0] probe2;\ninput [0 : 0] probe3;\ninput [0 : 0] probe4;\ninput [63 : 0] probe5;\ninput [7 : 0] probe6;\ninput [0 : 0] probe7;\ninput [0 : 0] probe8;\ninput [0 : 0] probe9;\ninput [0 : 0] probe10;\ninput [9 : 0] probe11;\ninput [0 : 0] probe12;\ninput [31 : 0] probe13;\ninput [9 : 0] probe14;\ninput [0 : 0] probe15;\ninput [0 : 0] probe16;\ninput [0 : 0] probe17;\ninput [2 : 0] probe18;\ninput [0 : 0] probe19;\ninput [0 : 0] probe20;\ninput [31 : 0] probe21;\ninput [0 : 0] probe22;\ninput [0 : 0] probe23;\ninput [31 : 0] probe24;\ninput [31 : 0] probe25;\ninput [15 : 0] probe26;\ninput [31 : 0] probe27;\ninput [15 : 0] probe28;\ninput [0 : 0] probe29;\ninput [0 : 0] probe30;\ninput [0 : 0] probe31;\ninput [0 : 0] probe32;\ninput [0 : 0] probe33;\ninput [0 : 0] probe34;\ninput [0 : 0] probe35;\ninput [6 : 0] probe36;\ninput [0 : 0] probe37;\ninput [0 : 0] probe38;\ninput [0 : 0] probe39;\ninput [0 : 0] probe40;\ninput [0 : 0] probe41;\ninput [0 : 0] probe42;\ninput [0 : 0] probe43;\ninput [0 : 0] probe44;\ninput [0 : 0] probe45;\ninput [0 : 0] probe46;\ninput [0 : 0] probe47;\ninput [0 : 0] probe48;\ninput [6 : 0] probe49;\ninput [0 : 0] probe50;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_5_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(51),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2017),\n.C_MINOR_VERSION(4),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(0),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(2),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH 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OBE65_MU_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT(1),\n.C_PROBE275_MU_CNT(1),\n.C_PROBE276_MU_CNT(1),\n.C_PROBE277_MU_CNT(1),\n.C_PROBE278_MU_CNT(1),\n.C_PROBE279_MU_CNT(1),\n.C_PROBE280_MU_CNT(1),\n.C_PROBE281_MU_CNT(1),\n.C_PROBE282_MU_CNT(1),\n.C_PROBE283_MU_CNT(1),\n.C_PROBE284_MU_CNT(1),\n.C_PROBE285_MU_CNT(1),\n.C_PROBE286_MU_CNT(1),\n.C_PROBE287_MU_CNT(1),\n.C_PROBE288_MU_CNT(1),\n.C_PROBE289_MU_CNT(1),\n.C_PROBE290_MU_CNT(1),\n.C_PROBE291_MU_CNT(1),\n.C_PROBE292_MU_CNT(1),\n.C_PROBE293_MU_CNT(1),\n.C_PROBE294_MU_CNT(1),\n.C_PROBE295_MU_CNT(1),\n.C_PROBE296_MU_CNT(1),\n.C_PROBE297_MU_CNT(1),\n.C_PROBE298_MU_CNT(1),\n.C_PROBE299_MU_CNT(1),\n.C_PROBE300_MU_CNT(1),\n.C_PROBE301_MU_CNT(1),\n.C_PROBE302_MU_CNT(1),\n.C_PROBE303_MU_CNT(1),\n.C_PROBE304_MU_CNT(1),\n.C_PROBE305_MU_CNT(1),\n.C_PROBE306_MU_CNT(1),\n.C_PROBE307_MU_CNT(1),\n.C_PROBE308_MU_CNT(1),\n.C_PROBE309_MU_CNT(1),\n.C_PROBE310_MU_CNT(1),\n.C_PROBE311_MU_CNT(1),\n.C_PROBE312_MU_CNT(1),\n.C_PROBE313_MU_CNT(1),\n.C_PROBE314_MU_CNT(1),\n.C_PROBE315_MU_CNT(1),\n.C_PROBE316_MU_CNT(1),\n.C_PROBE317_MU_CNT(1),\n.C_PROBE318_MU_CNT(1),\n.C_PROBE319_MU_CNT(1),\n.C_PROBE320_MU_CNT(1),\n.C_PROBE321_MU_CNT(1),\n.C_PROBE322_MU_CNT(1),\n.C_PROBE323_MU_CNT(1),\n.C_PROBE324_MU_CNT(1),\n.C_PROBE325_MU_CNT(1),\n.C_PROBE326_MU_CNT(1),\n.C_PROBE327_MU_CNT(1),\n.C_PROBE328_MU_CNT(1),\n.C_PROBE329_MU_CNT(1),\n.C_PROBE330_MU_CNT(1),\n.C_PROBE331_MU_CNT(1),\n.C_PROBE332_MU_CNT(1),\n.C_PROBE333_MU_CNT(1),\n.C_PROBE334_MU_CNT(1),\n.C_PROBE335_MU_CNT(1),\n.C_PROBE336_MU_CNT(1),\n.C_PROBE337_MU_CNT(1),\n.C_PROBE338_MU_CNT(1),\n.C_PROBE339_MU_CNT(1),\n.C_PROBE340_MU_CNT(1),\n.C_PROBE341_MU_CNT(1),\n.C_PROBE342_MU_CNT(1),\n.C_PROBE343_MU_CNT(1),\n.C_PROBE344_MU_CNT(1),\n.C_PROBE345_MU_CNT(1),\n.C_PROBE346_MU_CNT(1),\n.C_PROBE347_MU_CNT(1),\n.C_PROBE348_MU_CNT(1),\n.C_PROBE349_MU_CNT(1),\n.C_PROBE350_MU_CNT(1),\n.C_PROBE351_MU_CNT(1),\n.C_PROBE352_MU_CNT(1),\n.C_PROBE353_MU_CNT(1),\n.C_PROBE354_MU_CNT(1),\n.C_PROBE355_MU_CNT(1),\n.C_PROBE356_MU_CNT(1),\n.C_PROBE357_MU_CNT(1),\n.C_PROBE358_MU_CNT(1),\n.C_PROBE359_MU_CNT(1),\n.C_PROBE360_MU_CNT(1),\n.C_PROBE361_MU_CNT(1),\n.C_PROBE362_MU_CNT(1),\n.C_PROBE363_MU_CNT(1),\n.C_PROBE364_MU_CNT(1),\n.C_PROBE365_MU_CNT(1),\n.C_PROBE366_MU_CNT(1),\n.C_PROBE367_MU_CNT(1),\n.C_PROBE368_MU_CNT(1),\n.C_PROBE369_MU_CNT(1),\n.C_PROBE370_MU_CNT(1),\n.C_PROBE371_MU_CNT(1),\n.C_PROBE372_MU_CNT(1),\n.C_PROBE373_MU_CNT(1),\n.C_PROBE374_MU_CNT(1),\n.C_PROBE375_MU_CNT(1),\n.C_PROBE376_MU_CNT(1),\n.C_PROBE377_MU_CNT(1),\n.C_PROBE378_MU_CNT(1),\n.C_PROBE379_MU_CNT(1),\n.C_PROBE380_MU_CNT(1),\n.C_PROBE381_MU_CNT(1),\n.C_PROBE382_MU_CNT(1),\n.C_PROBE383_MU_CNT(1),\n.C_PROBE384_MU_CNT(1),\n.C_PROBE385_MU_CNT(1),\n.C_PROBE386_MU_CNT(1),\n.C_PROBE387_MU_CNT(1),\n.C_PROBE388_MU_CNT(1),\n.C_PROBE389_MU_CNT(1),\n.C_PROBE390_MU_CNT(1),\n.C_PROBE391_MU_CNT(1),\n.C_PROBE392_MU_CNT(1),\n.C_PROBE393_MU_CNT(1),\n.C_PROBE394_MU_CNT(1),\n.C_PROBE395_MU_CNT(1),\n.C_PROBE396_MU_CNT(1),\n.C_PROBE397_MU_CNT(1),\n.C_PROBE398_MU_CNT(1),\n.C_PROBE399_MU_CNT(1),\n.C_PROBE400_MU_CNT(1),\n.C_PROBE401_MU_CNT(1),\n.C_PROBE402_MU_CNT(1),\n.C_PROBE403_MU_CNT(1),\n.C_PROBE404_MU_CNT(1),\n.C_PROBE405_MU_CNT(1),\n.C_PROBE406_MU_CNT(1),\n.C_PROBE407_MU_CNT(1),\n.C_PROBE408_MU_CNT(1),\n.C_PROBE409_MU_CNT(1),\n.C_PROBE410_MU_CNT(1),\n.C_PROBE411_MU_CNT(1),\n.C_PROBE412_MU_CNT(1),\n.C_PROBE413_MU_CNT(1),\n.C_PROBE414_MU_CNT(1),\n.C_PROBE415_MU_CNT(1),\n.C_PROBE416_MU_CNT(1),\n.C_PROBE417_MU_CNT(1),\n.C_PROBE418_MU_CNT(1),\n.C_PROBE419_MU_CNT(1),\n.C_PROBE420_MU_CNT(1),\n.C_PROBE421_MU_CNT(1),\n.C_PROBE422_MU_CNT(1),\n.C_PROBE423_MU_CNT(1),\n.C_PROBE424_MU_CNT(1),\n.C_PROBE425_MU_CNT(1),\n.C_PROBE426_MU_CNT(1),\n.C_PROBE427_MU_CNT(1),\n.C_PROBE428_MU_CNT(1),\n.C_PROBE429_MU_CNT(1),\n.C_PROBE430_MU_CNT(1),\n.C_PROBE431_MU_CNT(1),\n.C_PROBE432_MU_CNT(1),\n.C_PROBE433_MU_CNT(1),\n.C_PROBE434_MU_CNT(1),\n.C_PROBE435_MU_CNT(1),\n.C_PROBE436_MU_CNT(1),\n.C_PROBE437_MU_CNT(1),\n.C_PROBE438_MU_CNT(1),\n.C_PROBE439_MU_CNT(1),\n.C_PROBE440_MU_CNT(1),\n.C_PROBE441_MU_CNT(1),\n.C_PROBE442_MU_CNT(1),\n.C_PROBE443_MU_CNT(1),\n.C_PROBE444_MU_CNT(1),\n.C_PROBE445_MU_CNT(1),\n.C_PROBE446_MU_CNT(1),\n.C_PROBE447_MU_CNT(1),\n.C_PROBE448_MU_CNT(1),\n.C_PROBE449_MU_CNT(1),\n.C_PROBE450_MU_CNT(1),\n.C_PROBE451_MU_CNT(1),\n.C_PROBE452_MU_CNT(1),\n.C_PROBE453_MU_CNT(1),\n.C_PROBE454_MU_CNT(1),\n.C_PROBE455_MU_CNT(1),\n.C_PROBE456_MU_CNT(1),\n.C_PROBE457_MU_CNT(1),\n.C_PROBE458_MU_CNT(1),\n.C_PROBE459_MU_CNT(1),\n.C_PROBE460_MU_CNT(1),\n.C_PROBE461_MU_CNT(1),\n.C_PROBE462_MU_CNT(1),\n.C_PROBE463_MU_CNT(1),\n.C_PROBE464_MU_CNT(1),\n.C_PROBE465_MU_CNT(1),\n.C_PROBE466_MU_CNT(1),\n.C_PROBE467_MU_CNT(1),\n.C_PROBE468_MU_CNT(1),\n.C_PROBE469_MU_CNT(1),\n.C_PROBE470_MU_CNT(1),\n.C_PROBE471_MU_CNT(1),\n.C_PROBE472_MU_CNT(1),\n.C_PROBE473_MU_CNT(1),\n.C_PROBE474_MU_CNT(1),\n.C_PROBE475_MU_CNT(1),\n.C_PROBE476_MU_CNT(1),\n.C_PROBE477_MU_CNT(1),\n.C_PROBE478_MU_CNT(1),\n.C_PROBE479_MU_CNT(1),\n.C_PROBE480_MU_CNT(1),\n.C_PROBE481_MU_CNT(1),\n.C_PROBE482_MU_CNT(1),\n.C_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1),\n.C_PROBE691_MU_C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synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4341}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nYugOLIF1XBreTDYRaNSWelgjmV3GIQ3y7FKiDB9UiIB++fAUC4TXcrfthfgN8befqwACkO3Q4k0c\nvJxv/aokgQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nP86BhFBNNa0qr9Q2+Wo0KACiIyDg4VPZdSis8bLUVn6FrcCD6TyMD6qWsX7GqSzkSyajfw5KoNS5\nrAZcRWAMv14anbm7VDJCIblrxr97wW1wDK0tJz6KsyHENdmS+W0PhSl0PyC6LE8TbUq4mev1WMPa\ne8qt1TLduNZhmfYNEEg=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\ngWBenVTIP5Q+rcNXfn1zPEjuUtszskvpUVNF25Xh81JnRdMPCp/0AGJPx+mPKwQ62keEUCK7jImu\n0uCqq7uEhg8CAhGkckxz0ziMi5p3crim/FOPfZSxzcfVA0myImyw/jA25kK2gqWItxmETSoXCqJJ\nxjTH/Kdlxzn5v3BlGFnjUMmgDpw+7ZlRLWclsVDPWcyttlqzmOpUVNRybjmRjQ047dZKoaEnV7aL\nJadzAQ1SqJzBdkDtBC4ls9rDZ0efLPq2CaHSH2lKmJWzqvjdbahTe/uDqwZlM/3ri9uvioLaock3\nBYN0ATxKAINgg8QSBFGOvETVtbNj0tmio/74Jg==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUA332GmFKmVHrrGry7Cyuflehk/VbtxlBHEATtE4ZDxpaTPEmq4fqpuW3/eIdDceGsGBiaQuMN9K\nWHRjmvo00KBUbhMYtfB1gjlmZEboE2pGVM53sCnoWcRuUcFptlHy3SPD43x91G4s/5AG3W+1+WfG\ndqqfUNJVltc7+nD/QSz52JWyt2BKcwXzXUegWHFyWPlXXyRha6uiHm5A3aFVX9XSCQMUBVg9KOgQ\nr17LLKqYda/v6o1fu2DbIpPXqeviObYOGtxIlZlCKEQ0WQ16wVhC7M7JMUM8K1ajQIP6aFm+lH0T\nT0TAEilCZfV2IBv8ZeVngUGkozMdcE2q607VAg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nJkclL4oQ89VKThgpnFORp4DkQ+l+oHyNRU+cUXBcYSussbqYTJL6YmJORdubTTO26u6Gzu7Zi8eR\nCof7Krp+GgFdv/lyHLisqmpxJDZ7fQJTFSmWQ1sN09PbMajgp5uypgG17Qqsv6Efx7DaBK5bWBFL\nzYY4TfY8F27SWO7q+F4ZXrJVV+ljd3jMxOp0CO33BlH7VTdJmnHbnGwVoy7NS7ktTu5O4mtjSy5B\nim8NDWKOPmwonslxiaCWWhRcIUWJMoS3RW+hbISleB+u2f6Hv6Cq0ewXO8bpInYwlzrVk138Qwn8\nPZory2IpEEHyD3/RAkNZjAO5MGkRMmlC6knbhg==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nP0095JhTyRSuAcV3jYJyGhT1pAQ63Ikz2jcw/xarWfO4myeR2ki2IxiL2BogiBQPifhiQ+8e/taC\nZCqKABC2nUd7sP5K5FMLxqEqvaSGhMtRO2Qx+bTN2vfUmVhFmm5F0IDL69aSPE0VUYhlP+Aw6isG\nmHBHYBCtHhMlBBTHiBI=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfVKST5L4zOIHEw8rTePPdwZAh4xL2unQREo9UhjWF63YVGB1vNoHQzJFNQi2s74hnMxp4aeUGW3A\nnhI/ztVR4LEwZ7XH7wwwmLntNjOp08e4L0SwqDu4k9wj2Mq4P87tHDh2OlNiLNBP9KNGLRKuh6L7\nrvsNzCz5uZW5s7nBY60UupCfWM5iYb05yX1fiPvYksz5uEon77IwhleTgsDLGSjDpO/3MsRecpOY\n6zxdY0uNkfRy/e+huHZvIRI9Tgx9p4p5MHkKiVX5pzmTHVFHILH/8jpxbyunuxTvGsgkRSrn/BzR\nCr6wvT7hHeY/W1F7h1vfxGVI4Ek5baJkO9T+vg==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64336)\n`pragma protect data_block\nkE3zh5FB1r3vI8ZJiCJ6FWF+XzfFQVQgnzQJ/PJpjvgCXoAs4Zjsl6nmvDpPHpRl1X32r55UNGOi\nrzvS7eJCMJeieiUb8KcN1+k9krnT6S4qk6dWAtm57amEO8+SlPVtgy1tkIGJYbb8LomTrg6JKf1q\nmpnSuP6AyfZHl1hcXlpc6bd4uJId9F/xcZnJaMEQTk2Xkh0YZwzFzeJiYXNXkaANr2sFv7jst1E1\nwJT0/zDSlQMmJHtvHYgqniLGO0LTUERIJn2n3LlE+Nb1n6im8tMfUK9/omKdJrvVZAmHwm6y1KfX\nSR5hA5hizsxzuEmVhhICN34dve/ajVFv00CqzpxQcnSBCirgk/Od85aRxbLRw7wKTDQVTqkGC5vk\n8B71OWlKiZ/nHzlwZ9hkKlT5HkYDPZN426UwuQXkSdSoit7sDolGhTt4BUWi4BL1gUE1DZ/7H+Pc\nOIDFwGjTInrdA+MN85INFgXppeRHIfUeeJV6PNisW2AElJtcXF97zM77KR0g2IiTqapwRFlRAMpQ\ndmybCFy78g+H+cfr3d76Eo7sgOSPiULbuDnW5OocD16sTNjQBvfOBZ1a8fcYC0eVM/MPfFqAJMX8\nhzpp+YLA1YWJ8/mAVQhlhjc4KKcIn0RiMbw1LSTX142bdXJMBujGVnYH2QwtVCJwtuERXFtiBcHK\nU7EKh6EAIU9yCp58uJMNIub6tmkKj3b3pO5oAxbD2T1vOSfaQzg0TsmrVL6y+n+rXPnEyvrgMtw7\nDlQ8o1tq4vjKbXAMiP3VHX9luvJQB5yRoanW10HoSFcPyGhuyvBscFIWTC+BEA3hNGyk5czChKPF\n+vMFqE5wtBfiuGKEi4YBS4B6ZwpMPspnZwYf2NHSNQqfLSp1Y8r9RY/RbhF3Hc9AAXs29XP2YY2R\nDt8z15QRDaBBCVYRckMMTmGpOJ26zR/MWF3F5a9Qf5IghfFoimkitsN8O4mGDH1avgkPNpfc/5oq\nrh8goxqhDyYi9r6oAZxul3ymzQaklgK8XVa9W2wYLPQ5HVUIzH+fx7yOryc/b0XpcAYDhsiA55uW\nxPOsFmqwrzhGoEM6/sPeESOzKxGqAuWArX1dYw3B1NIRwc/SiICNy0gVTvq67BOMMfU2jEfH1zss\n907/tTkECdjUTaTA+D9QGzdlwAnxMLZS/5Jp7CaJduYxlS3SjEgCALpp8pO3FrG3dvCbzob3X6l/\nHywXPt6zQeozZUD9te+GbwL4nVBJQoDFFiKpciE0aFKU2H6IF0YZ9bQKJKYkBkYI6Lg68EPLAPfi\nHgpWSGcq0sr03CFqAvZIennPxsmwghVPPQBDInhSRM7ogh6JVSa3wYiW90Im3BjhIeZuTVwWoejY\nZtDwCn1vqNjdVK1h0k+6sZkoAJx/tKymMzQ79DNfKptG48yUmhC/F7A6bL9CZ4J0xKpJAT+0rmtd\nwEym2mskpzCcOGgRltbipx2L0w5kmRXMdyjEta4eXyFEMAzsWznDHXMv2vq5XwM0savwMfuWTyY4\nXXPdS5QFO94+jhMoG9DQ1+S+LR69rqNM/jCH6/Zgk9+GUebipjHT3BHiNgq3pjhrhoBCNVW+k8Ra\nikrBqwm62uE0Kvj7UIagh8ZVrswAyXSLIof3/bVQAJhZmB3055LH2U/4a+fEsD4mlboFaa6zet2t\nAhSATWM5T2Rxo27bt59Gb3ZUMBPTojqEfgvWWMBvawl1GlesvaxdtH3t7LjvwoXN9tdEdhdIoXW7\ncnPRYqV9hD+jSj/wDAHBKCAqn/06LxSxEo1v06AkDTali2Ibu/LpGRg+v42BQSTALzWzxmp9OZ+G\nQBOmW0FWoBr3Np7cOgqb1y5OI+hODFfRwREojfbzTDLy7ZR3RTOCEdwJ83BGogbKuZHCe4F8fVy/\nEzUHRrXI9Glt4cEZiFsJDXxf8DrBbMCe47ZO/4Vb8CQwK0Zp1ur0bGW6eZJLvm2CZDenu+smqHyM\n8cNa+X5ZWUSZdAky0ggxJvYzGj1NLWRkA3m+yU+dKGGtlf/ZyyKW8UFiemUtcK14bXza4wz86bh6\nbsEzG2TRvNc6sbZMVnkxLHYnx/xPQrWFNhKNcb16XcXCaB6WFYv+E6+GM/mR8raMgI0K1rSj7Cni\nWyKsBmpgxTKkNy540JxNPM1vmm48rjCWehZwR/BFn/eNpQZlRe261hIosBDqnVgUvGphdsrJk2tP\nuvtY6UHx4FoZy42AjlxAG9fTbwMZP/GKLN2Wn+uc6iDBnGswOQTOQl0glpbfKEJnkxuscJBlzVXK\nbIAc516dj2fAc4P8qSHMIIMMmrRtKlyoKbGUpuCdDAGCwNiB8e2ZkD3Z18aQUYjYXrudHUOsg5jn\nIoIQN89ZyPNR6r6l7HM3EmnD2I7C4nxEzYwSOaIKPYClX6pE2lH4j3BfWEH6sEd/Ff/H2P8j3/jW\nIbBz30hNDupx7kOjNavnbibhcWayZ8dsA9bmGHm0bVu6SOuXd5uKev9QnYaVITu/jLI61Wkmpcsp\nYHhaVaSFaRUStXZIcYv3VNPkuxE2az0Z9VNN0Mi73rrXGMw4pp9YL65ByzJgP3fG97U38ltLHgKS\nn5Itl199gb7ZMl0lsAh83uPfA4iGuOv2sBn7g3pyREGWaEYieHfHKq+ju38etYApkb22FnsjfVD2\ni/YIM15a0/JUEGc64KHZASi8A4NiUntFmVDG7YkPNdOXQ5BqsqprUqtMd/b17Bm0nkxc8e426Me6\nUbOlAHlZce+4uAmZvy+E4ghu6RTfGS1y2gVO/RFbNEKDLQmvXGS0//UZVhj+TNSiInw25dxsDuCV\n6utZNSIb92gOGTuKghxb07yu8yXyZy9A4biLLqaVQU0vb/PW4EP049J7YYdO9sQwrJCoeFtVEaPf\nwo2nIVX6hOpH1aFEkrg9ERiPnt1UUXlgrQTkKdlkJvC5wQSP2ZNIRveY6jHSw1gVBWkr9k0daovZ\nz0G04BIfsbm+NtmkVJ7OoDEv4XuZ4Il00Ap9vBN8bSHNO/PsMj2JNKVH3v/Xx8eisuCdeN4Hu3Xs\nzsUtx0nJQggOIjEbi1WrdnD95V5yipfY1V/ZC5V7ii5zHDUDkP+p14NMbuE9sjfsL51Rfoty0wsl\n+MoLxpOr4NcXnX7QOWmy4aGdL8C3ZikuPP00WhtKRG4p6H6MkrAttXHz6L5wCnUV4O2kGfhkhYjf\n3yQJVii52aRvT7Lv6S/BAOJFByUGl4wpHoyfLS8dLrarEOyI1mnoeOsjefSUTMceLOKuPWkMk0I+\nLR/T838qusGpX/26srrf80SWxKr7ch0YEK9xGGHAO7cgvPQTlncT37QvLwfutO2xOZT+81H22NiZ\n13z31W0LurQciFfxyNz3bOQeKWnQHIqtFv3JGGJnux7/cOP614w/LW/aL7/YOzC8F0xM3YhaMeUW\n9UA+GBxyn9FtuQ0/g8hs0RhuccMBjsnxQzSBS603FlXaUQV2FfsfMLBL7TasPZ4rIHuUWTEu9mYL\nfWz2rZbpwwfRq35JbtQKwphJScZVbTaLWyH2Isjcm3GRFrOK9OpEZwYx/HTc9n/EtRmmZFwdUe4J\nlDnueKc/fDmoU4G3+Zw6rm3p3XTOo9DXUArS/uSnCylnmGrAaBLaKnFsQKd8kCmJX12Uj/xdyOF9\nOpIg19vrcrSE0ejJQ5dUcLrb3i0Rk8eLyGew8jmMMtFOBRmqVwscepGRMPG03RMp4W3rEJn8UXb1\neP5XFWhrxazaFOY5ljiIWHk9hYQOnH/Vt8DG01HUbQNcvQH1xHNwUIooc0fbM+PgxMn2hQ0pM6+c\n0wPfDIKABiNmKLhcHnljST+ofM0yPaynaEkePqVxWiKlmFSgAsBtBcerrFImky4wOHdJwOLvldx3\n4dVj6HduJgYtLUQGVl0tI3IbmvX6s0MKeONdhJKp69hWLHhEiYl/t1cPpLJB+SUFp/r1x1s+MzD+\ncKZW7hNtDThOdBJjoeAKmavGBoh4VHBtQqDP0lL+EwpSg25V6X9XW+dFUEpwaZ0CuVXWHBtwGuce\nMaku0HU9yyOJSHRk7R5AzoBM0QCbfNIwoEqrpTgUW78VzRjekms34MQvc6/VWtqoA6IIgPs8ybLJ\n1pXEw/utkcwR/tMBVJvyKzEp9b6Dc0sotuhEJRY553G31bb6xa7Y7PG38YByPiqfJPK4AuPhcaO4\nN8WILCcgXuWL93xjqu0/Ew6z+GNqQm3Jz4ntiHysc/AluO6K7vtwO4UcS8ccMt5z4bpA4T5arE4/\nb1eHDWK6JT2gX5/4lOlR7pJLy5qwKyffyaH/Nqz7AsCVsPZi3Qwvygy7NndJ5ubyVcHxyItssjGq\nDNBwkJOOVIQtsmfxXko9LsA2I6zOgj51rqOlqXg2Gk7DDJjUk66K8JUFHjHbyUHJoAgAJXbcvFfs\njDDBZ6zps82PHgzQSOWlueInlKXLUvswdqg8Szm9Rmfe07P0jivX7y1UdWGu42d2G9+SbnpVwkAY\nd1j6kvNq/oN/n3VLX3UuBoSfGik63mKL3qmADCS+UFhJpi4xHFbwZh7pqoTDSA81OoplAD6RtIk2\nxTHfTfakM+NDXKgW5LVuaFtBz+6XsG5LuuVK324YlMwuHsdtjt6EchzSz/yYaMPHCFdNxyRgcbqD\nSIm/1x9m9ypB7i8tHeuJrv5TiGMrS9fK/EjFDH9s0XHcvfmBsVMUNdJPggy2rEwjwRnqEXo66at/\nAfc7We4AA8PDP1d76rGrBczWskspbNfVGtzLYmsuK1aMAzAGE2VnjMJ/OJqy2qkF5qntyuXtWXp1\nXYYHmfMdE0HqigV/1OZ1p6fodgR3cMw7dqDD4xSvY3zej5zcUNWAw6yrxJEPGUhaUjPtNS7+r2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fRoNqOEwbphWrnFxpR1uQtlznt7NunmA/HAq9QD0jc3VCyUGLK1m9jzfR+MiOxGkvi40fGIh\no5q6cp6WZYQE5sG2u1HePNz260XW98o1SKmGAnVADmN9oRH+kJs27wjueapaewwDVg8pnq6kJUOh\njQd0RkYcTMItDGvp+sFqeIIdADsTHRvr1h+M+pYqq9sLbwUoz1Alak51hZNlSXhSEVXzQLkppmeO\ntB13Z6wglCy2BICINwlSr/7HP1cYop92mfeTXL3QGuFjsDOYJeT9Igcq+fS6YIfWCA08MY5r7yVk\nVPB84f/igRg5ddrxoxTIiw6w7GWDOhG+zTxF1zyp5jJA3yKcpqPzSQpf9MKcNt+PzeKm+wneK6Jo\nhpoN/97lq7oMjwcqj4fYDI3pT7J8WHKkZCIdUVNrv0PtjsuMpkuTQbOr8hbWLJNy8UKFlgHOcfrj\nOvGAARiIQRbgB0ehYmzYwrLOYCEEGz6BajWpYh+QjcQz68HI9uD0KJTeFrxECsQhCkd+nhXmR6Fd\nTuqTwMlfvUxKMpfl+zweX6F5NmHmeyPDY7Z3diHFdJVtYNhc+jcelDo1qmERGZj0HjhlAXvpn27V\nveZu3AVSpka5ElIwtvHc/TpRzjvbeQHF5yFv9E3VhZftw6+ajD4mjDYjGCqQeNasu/oomGN+bD06\nLx4hi4Wsc5ABDp9+84vB9wTN4vdXWfDxjG6e8iiMfWuezpQtLWJtxG2XnhaF3oXBpRIS2VVSE3h9\nz+2gpVoEZT3vzJjOS8nL57iPKloZn6rbf5gWqxxUAtYbGct7VUgqevGHgWDGl0dAqT8VpJaQ21q6\nFkr/uOy+vbpdI3AICEPSgGKQQMnk1kAfWxfgJ/kaxhZc4f5XlC0ZGSh+C2CWzhNE/JAksw0YQmsi\nne+rOYuBn6qvg4VY/SXyC6jNTUu4fEhiqCBJKvOpstSpQS2jYVyQK6GIEoOtvRL+AeqOwN4ylvak\nQVkg+2A6cwY7T1x3wkcNeZMXbEpORaOJMy9wXl09aJXky2uN9qgpXHXgPTZNWf+saMNRN+uBGVzs\nZjhjfEYYTVSnY0pqS+gpfbtlNOxXo7TL8OvbkRAThNpVfqwQtupoPNk2HHNbdmWP1tZGcqPsQf6c\nCPJwuj8fcPCQUh1HIZMnT9DYnr+Z1+9YVL/Rz7jLHyA2rFlsPXsEC9hUanPqMe7CAAEbjTq0PKon\n6vcDhC4OeDhfHkwfTiOS9fxMjBLTcaoTqPWTZt8ChH4gnVvPWfUBK7kvIhw+dKvaxIvX9bk/BH/Y\nB6uSJzU7imXZJLx07cEcU/6LrWAx6BrPF2/b6Su1t6eCb+t1Q3QZIS/1RXup1A8KEnaMO28WsZcw\nZQ5vCfX86ljiIl+HfGiLBpKoa7+SdP/+q0BolGpFDPCce56LZLDSOjBraFCS81FH07TgMpEW/Koe\n73WJ43JWWkZBQNZzN+JlfWtwo4qAocwsQJX0w6MOAIE+RO9Iwh1IPv1zbtcWHBpWy1yK1K+qVbiT\nkI8txebAMYWE1fJJdK/cP/tTZXiQLhiPzBsl9ezZjJsjAPcq3dbWErzH6ZEEnAKTv6PShy3Znw3q\nOT6++Nsz6N/njj6GqwN1E2zfnMNA9tFHXPkjpOfSbyTnzGEEZwPile3fiO38kzzHEjoAkb37KavT\no8WtZsohsnfTezPzzWxB9cFMtrTKv+u3cIIlr3mM8PZGdN2ZSq9ahQfTqRYp5KGtKnkkBIfsbqqM\n6M/SBVm5RMtrKRYp3/ey+lutDPtoUKLWJMnsv76her8S4uek1nzv4wTizdqJoCHy04vb5HAcgpVC\nfcWHgEVDqREje1ZKN9cggmiVpXRsjmWDBU/wAg8c14gohHPFlXNZgAA+ytO9js8szFDnt/0cCj7Z\nkDd0C21SAR1LHBI9KUf497LL8Tu6L6XEd7Tm3XEXeAS5OgHmGdAHyGPiqI9u8ClEt6BkfXamciI6\nlfeQj+z1nCxMPEJCjjzMwvV+3Ah7f/pMVMzaycr537MfD4P9+Ch+Y0vIsYpwt4zU/30BNXnQqfs7\n67i6Wfe/ptu3NRiQFhoPNGZytUbv/evSNDXxFaqwfruUEUqn0eUopvcwacq1XD9XaRIAXBGNpSoS\nKKesrN7Q6LZ+PG/cPTdT84w/+X0t954GdIewb65IP9dwf17eYtg2FQZyM5t0f3iNHe0pojKIaM1a\nmcTIJ8FIFYHoORq8DSEu6tyA3X53jjGyQRjVmLNIZdZSbRVoyoBsiZ36Zh4U4aW+U1leOK18co4C\nxLB2Om7MWuPJT3VKJMuG8psZ0iW9z0Zxrl1RyfZ9Lk3hYM0VRdpLKgxqEDiEeCVqfhlGlFXUj3wu\nacVLRH6dhSEBumjFuWq/lHbTsYfS2PGWkPdKedT/skbFeOsHLU4V1O84M8q9+qmppce19MSMwXeO\nQ2jn8v1qDqQoaq9r7Jvksqp/+A8wClhvUJmaqnTcDX+MLOJSbHG2ZNR/3PvUYpDVUrL6FwJJEASQ\nPfeLTPm7SGxsfS/ZVEf5pC70NwkE/6UEcyIx7xiVjxXhDxpA1pBvp9PRueOVwllHhE6dRkC/iGjc\nY8YKShjZxisO3URdOWXpt8F8PTMjnWoGzvbX4aIve+X5KKntuaYeQxKXCf8OJaSDgRc27KSBsG77\nFYG6/6BcH6AAXrtXc/OMZ5Hu9pwGsV20Zxo2xAGLOFRpmnHdImjGCwHmcTrhQpQH8Br0AYr8Dchr\nzb/JJoGRA3WukUlj+NanwbgVkpDoHAJD1a4ftoDvHJVleoDf867gupHQThJhVF6z8LcDtafpRVrE\nSHNxS9sSGI31+aTuQ/0YqhEiBI0k38xXFesQY1mW/zireb4cohUmw/0Nx4uTsUCRUE3WLfpwBeb4\nMp8qasvOM4Uf9kQqF+GnmseyoR8jF+xEaBjyzrsJ7WpU6EQqH7Cs2y+0nkw7vULcWZ7PtxCkTi+y\nl+KY1Ss3um8ryMQYGvKj7L2/zAzwrarkjBW4JAtWsM1SrwqZe6veUIqe3Z4G6jiNsQ4NTDb8oypf\nuYa8F3nzw3hTgsLTGVQU9pMPE08BjCvQKFqc57jBAj6RXHMnE3TWWc73XS/zYTiQ/OmvpnxjZ8lu\nvX+/r/dA5KdxINswaLmFPw3KzzuWJBz/nVwLRbAGp9IHQYa6bgjjJRm5ZmLKGmzzyuRrQXUPKOTn\ncopnuL/JvlWnSdn90TMc2Tzzm7TXaIcgX9EDepTRW4sN2XWdc4AmncQYlE3Pc3mjMKKgB95f5TEm\nSgoHGZwRKlzoBLvmO6GOz1aatdeR50BMPUt7pSJwIgfBdLnvzstov1W42zn7AgW7Su/pfCewVOQc\ntZ3KuOMYDHtAQmPMuM620hdwLoXkyIatvRSwpr0SFvGi6O8B6kQ+5QxGad7VgcpGZArl8TiH6QY8\nUrI26KJkzhP9OikTZ6om4ZAs0bloMAPotwByB7KXegEUUn/G7uE2JTlScgVp8fNt08IHyAO9ubEL\ndk6s6Dfr0H5HdXOKdMAGD3C2jl0fudKu4zYcx0s+KraQSQgLXI1G2qoLzPeW4fGtztn4k6iTlSBg\nRGAbX+gnK/iuGfb+++nrxTBI8qFUX6YIlcOAkg//OSKGJJjat28UHn7BITZnedR7Lf2K2lu2q4yM\nUFzK+WcQU2KYHp8iy1VQ7x84oZsD1hpSPIvo8xCeiXIPtrxEHjRh9OZp7jAHNkZxhB53ii81SHB/\njEzrBHa4MLE/6WMisOhbmjPDUtQLtgnO86q7gzdmJX0C1jvl0VzQx+0ISJcZc1limXckLBS3F+rI\nMi8MGBfMyw+BygdEr2f6yRlYvJdRZJhXOXmHT77UlUuCfmArP6UIswPKplZN7Q+XLflYU+I7OUPp\n3qMXyzrC5ko38DucoiwqvsXMSMVx3U4vLK9VKA3sPt/QP1E0S7tFJB6lDoYQbdTI/vUgNy3iAmmw\nLl5BmdtFBDWdwEMFan9pvoDEbzNfFkIUBGuzvnjKtAFBwA67RYWKtqglvto8q74Btd/PMxWugAs2\nRDrpHJWYNh1j5vrsdRj6sRpJRMQ9FpQRBFbz8fol8FWWJFG0S8M+zbG317tUs/p0GjHB+hTwItqR\nv15KlK1LZfgIy6o7gd1a/8MIRTXjAVUuVviJ68d44vkkJr3mh1OphI4SBhUhzOaf+44CoHK2dorL\n9MyTI6q2dacNJIgHdhaJF+ebOKOMQ0olKCeLvE1KmN4SbPr9dHBv/d7cupOKbz1XYMcK66m5e/El\nRWsYMbQf2uawzWEs8cZBm585waVMQtfAQNoE7/Rs2/2SY+vnUPguioY+EDwZsTxfJWkI8zHk2a9+\nrJrYuXiNAW4sd3i5EDq/+2Ak2GPpRmfpxb7u6NIBKlwXugW8ktrqwlNqYCtg5vVaseU+FGNiVsvF\nFIuNWu1U7GpZ8HtnZu6aFs7IBPIoYMl7vu3aDQpZG9I7sSkjhPjg7s+ijQIJ3BGlmyuljXClWhZL\nJIDVQLnzS1pM0pvibM+4youBOCPFCx3sFuvQJZk3DpKOy2HX8XmKOtbKgZHL2FBjFFosaGOqcL05\nIgcxAvuqHB/0PhosWC4fcQy9X0ohWgMLrtpWE8mEqH+l/idgHAn3azKZjNDZTlrOZEPh5Y71cZak\npKgDUjLW4WthFcIERr+HL9L9PI43LQ0EKDsQTa6UW3qJFAXgUMTYgZtO2S8RQB23wPZI6bncN69z\ncEU5z6OZdFP2CgLvdInA1tFbRhPanE7dmxgxqPwFREzFyPLMwVsw9YgzsxSxbhJODZvVY1Bp6C4e\nf8VmwXIAZt+OfsTInDC+dttMHHHCvtu8TBUbI+ZLgsD0HzsESIpV/BFvQsRAJyfHJ1Qu2kByntgu\nauKads6lHHGN1Tz23/hFq7PVfLwm2Rv+/yx5DUv8Uj7PLsaHqrCdZkVzr0ECfIwPFt7nW50xCqQK\nxMu8QoV4cuZFAJzIhqj5t05ByOQPFRcxOQEfZrShvvNR9GdpYtghDBF0fU7BDHiagP5xDQ+UrHtz\nka7nRo1FHnm5QoYRJoEBABCLmeYI2KoWtLqx/CHi30vFLoru7CkCPX2Ll5A5mIHnjWmu/VKJrgNa\ntThK/it4atG3Inp2n1vlkQJQNib7fEUdfuFjiiCQRuNtmJX+MqELiPQnVEY9VWHNKjBPREYUQKnP\nJkfsG+QfkgAOqxHLM6oCfy2FFrS9aHOTMK/+PdNJLxa769Vi1zeXV0kwzsjTsJp6LwEAdQ4xKPck\n5bRahBrDgSJfUTcQYR+fbWtE8OdbPM/FWuaIc9SEfNMEebsH/lUKGSB86OWHZNz4CMk5ebH3R5JV\n6DdoBjfP4Atab/RbwcQqnZG0UdOPbBy2c7wTzqK1i+/C1l3+nDVheGhizstvKZZdm6XehGdOgf90\nOPsGrNckYz2jn61FOH0PY9mFh1FLr+59tTVOFZ8+6G/JJcGGo8HJhb6b5sCjXHSsT78/4ldD51uE\nJDiwF+PKeYLd+bhW7XjkVvG7+LYAG5h34M4tD8XHnDUKzWkpzBJ97ZFr8lV/euLpwJ/XlVImBXwp\nwZCzDdGwiTrZC+ogqcsGqoZxLQ0lv7VhpBL8skkTAYlBc2XQufABCHG+gWEuy3TJvqodDuGo0iZz\nQzftJFbueGn7t2+s/eYkOYS6arOhlDNJX2nYR5xtrB1FbV8m+jaHEiJbQc7h1G4HB07HukZZp/9P\nLFvsRYJ6uqex6hCbbqMMHQGrId6QGSH6/q5SVMSgN2/gJFrr5scKkIFUDU79QyiUDCNwsC5hwA/Q\n52vnU3pPU6vXy2f5Q7ZwUWdsJFEI6O0jxqL+Ga7+MIwsqnVb4GlFZdjTH+jRLEyw039RgVDhgKFx\nliWSLpSVpJs1r/645DGyzIbsFE6cPjg38+CcoAWYla+Gp7OtVF5Aqtp7iC2fGffTn7TvJOPCsVjY\n5MHx5QGSiT/mOGO5OVGVbXQzgTu/3GVWMajEmAq7T3+Ddw+yw94k9rT6IDk1t3lnruZSEJTPTyok\nw+bsJPG7RO6DcD66Igd1WzLO5JiNwENjJVrvbbBMYTJCgVPc3hJvvFQvfkLiuZsa03mylgBXKHAX\ng1TT+hvmb6ZTIuNi6x63/487ZXtXCLFNhUfNlssg6Z7KCyDb+mOiA/8aaC12vb51w7SWXNrmZCWd\n7wJVMUngtcinyUXoTuPe67Tbwu7Y3zQ3ZBvKMzu/YFyR0SsSeD+/yJ1siLMoqudSse4aThJOdPbm\n/YEW/tF7aovwdtXP+40gIRqfPjqUfFDJzhIh5XTJx+5XI6b1ZNJdT1+zC9ZCv0wpUCNzcYDWP2v2\n+73X+DI2B9Hk+GQUz/uV+HUBxDiALLNqS2pBnu03BRN2K3Ae6udAdykdB3XrMGU3apddVfl2Qzxp\nIMqedE5qxJzRw+S8ghl7CQ/HLPmeR4VLqSCR+4vWCWIw/nWGOStxbAxslLYMvqSQqcOh9SyzCdy4\ns+S2RDRsuoiRadrTnFE9DK9AV7YVbx1TL/4UsryqKTyD6TZgb3LhhYOUcpIpv4eGF6c886m7YxCy\n2UDtdlk5mzEa450taWmN0KN6rx09qVH7bTyCrbrVUDBIPLqFlGt6zsHsfsvCJAI3c9lNyy/K4Csx\nnVy11QZ2mZmv5FNhUpC9/LR77nEsEfKmmY+ZvmK6ZHudJHG1/VfBI8FoBMT/fDIUDwW+BhOel/Mr\nViAUiihouIkWJnuBu1qd0eyhHAEwYLpl67lU9OZtC+Hw4nRKD7xL4yeaFxYMdBRfHT536DpZkC91\nDyLn1w51UXVeDMGmEk5w/suYHhiKKlsSF4c+HVkT4yWcG6HjE+nqeKji/CAw5c+5piMrQDdaQcJW\n3nb0iIj0gXRBN+Eotil3B7bIpwe2t+faDTQec05jrigHMr3ZgWGPMkTWRs4Qir553sMKABMSYkcR\nnG1bX1HCd5Umeid7Ko9w+QAO4nPsP5d0GRtDcIyTVJxEMoOOJPe6s5d3iX9a55AGR4JeQOBinV5c\nvQTaqc7NHTeR4spVOyNLX0Vt4r4xYeQPAv/7STKb3KraVueUbYH++IptBnYURSH+JYRUgLc3wOAY\nvaIiWiWgsMJN4S9Tj57MZ21MxkcOD4n+daasVl9bXICg5bV/qCKv8GLgLa75Lmkb/q5ZMWqIh9oE\nBXG7qwnhfQdr1GBfNX5e2CHlpmAsJSuPYxfplnTe9x7rmzk1saELs+J5Zod3BW8s9PqEOytiKyFp\nNgIyYxnpDHg3KfkpBCzAqsNwFrRhkG0cNj6GW0rXcjnK5XVsm5EJsIpUIuwUUCM9FS4M4tQvHqzr\n1S0Rwfa/ZmOL+3kwiLwUF5yWFKNs9N2uwmJT5wYI/8PK/4X7jfYBxLNFiM1d7/Ot/0CD2Ygqno20\nGjj8idQj+8zcvopFkqmlICXcCSsY1CN8ytSbrd2KnMUs733/3JrtKjQJchP9IvaMZn4C8GZRjQ6B\n2FQEh8t7rEVQECSOxQ4L5fKxi4VjvlFFV5om0bkmX9dxai9YM/IwxOrmiEVbScRlOGYie5dHSd5V\nk90VtMGSxisAx3kJM2aVn69wCxymu0VbpXmPT+80tJOSJSASfShtKF9vvaTCkQlfQzw6bL7yoPjh\nwEpRBVB8nS+srJxgzTpzxf6kWSrfKwaXXevwejax6otuoFF3YEUOCVQgG2aUWnXPnlQBNC9MPtAr\nmChzvfkMA49tIz4Ra/kpvwGya9myjGuIQ+DpHiMvJrcsopWNYHjXYldeCzHaIWvnSOHGMM7nBGD6\nboOM+PIpyOs0dw3ymADCy1T+tsTasU62qNcuquHRip5asAz3bozJHUulZhGOlVgRZUNdbA/meTnk\n/sjtLjzMLOoPyFtPJUmnUvTECUkmGukcIMhdEnWfA+OgOzrM61GTUK5bwGME8XNRsprWjCchp57f\nxii8cEiyhO9Nm1pmdrMnxiPCjIW2WSFsnp1BUNnQEWDbigo95ithoSdZejaydDJCNHQMVMB7BgbH\nJVUUva0f/ZGTwU3kz+FTzsT6PT+E2GNMZm6rzSz1Q3yNoH4OXUbJwQ/vRFtTpicFPDJoLzVZKQ8T\npYc5LFd897P0DLzZ8yT219GrhNpk8PgFDRC+bylWmXrFl+BbEfkaO9VEr+LIfaNoM8p0/YLHLo0l\nMrvk/FTzdn5XhFvxyS+Sky7a8fU9qLu5xKvwZGoA2MbCvP/9924WG5xmAmsvN7gJQ5JylMq+lFvT\n9vBEEkmXTi/zMkw0f9CycHzh0eBomR3kzWnpWRJ8aBj76yXKuWdrSZi8qbVdo8wh8eb5xoIV0ir3\nEqgdL7Zjn1IcBmqhcr3AfwkhQEaXeBA6hqImHgPIpyxviqMTA0xjkebO9YGuzZAUIa6uCCzR8XPj\nbYJjNkm+wZNwzr79+h2XV6wDs4JS8VDdZcAVCwvmjHY8WHHb0jZTF+cMbLcUDsGNXONUc06UzHa4\njGjOviVfcTwRaVwQs82CNgjt5OHwna+Fj+b2mGBEyENynvXGlAo4ECvuBzpI8LU+ABqJINwvANwS\n44b0GVEJNVekwlMSByybrdYq2Lca3a9BtZmGtoxI5vIDG8U8CGIe/HaNFpFIvuyGDgYAGr2eb2tc\nhbOnJu4LASxc2GdEl6I0f/Z0R7seDGa895BuyGGcT/HYktcCq70sTyk8r6H0klX8wc2w+1UT9sPp\n13PTlh3zLdvGFzKPfIx0Bovn0nIoViJ/W+tgIbtcCnPhaL4gh3QePzoLOGoIWzrZKrfXdQUkepGM\nnGqctZ3+0XpR/XS7seqRDlstOjCXkPam6oFji3lfLKqM8ABKgItNsWesmVaCeblTHDPu+zmR3Swj\n3XSa7hlf1r2EC1jqZ+oubGX9WZjOz1p0gsINsM9ZgUPOKlzt+VBwtUQGbtj29NqAdJ2m+hFTMnXL\nwnUTOLl4CkzQ/3PrqSxqEMLrVcMbDav1VqHyySeQ9SUXcPePCnXTp88Ns0q+RqrpL9STvlzfv43d\nQWoOfT+y5jzqBr99d34ltSn1jq5Mk5kfg331aVBVDGP8CPubrq/MjnUyQ2o2sw0VX2JfGMN2BjHw\nfFEQGRoV/qgnxP+Yg/hdQHYj+r8qrXledHrHiSIHvAPs4IQgUCb7GIaSaT8McI1pg/MxpBTzTrLO\nHedJ4drTUgQ0yZ/iYK1+QT4h4+42fAkQ1PTj0z825aLEk1E6e1O4mTyuokRi5lFL0i4Xo2nnJmcg\nY2HAeYmkS26cU2mggoFsRs/ZxkSkF1qMN7lvHplO+1XTHO0DVfLkBuhEnnqTZn8rhmPL7cnoZaUH\nZ+WcnLY2VJJpEsl14KAieVLy0ABlPd+RP5UZna1k+42P6i95rcEg3jt0xbOAbrd3GZ10GT4chHwX\nZCLWJjslyLcbPGL1XdWjgDMZ3dtfG0z3hucdHb6/ueD5YQwPMdQIir9TjhHok4WPalVXcz9OwrDv\nkkUDrWxC6S8tuOFRsk6jqShA+Nv1loaSF+IqNB9sfeSGW8EsyVZIuI1fnErGqbXf2i3DInx/KFau\nWTBKYaTk6krZM9fG1+OzTGuQ4ubpSMe6o30MtzdVl/db9M7hv27LYlU0miFi0OmEUVGOOZDK+gSW\nYVlr43tdFyGvXHSuVyUe8+IhswC9IOCUS+h418D19ZNCQT6af/VQDeVmfOTnnZpP6DOc5p+hPFvn\nn/ISPeLm5qeknJULbDWxnHSxTeKqsw6FsTlJo72ZuEd1zLdA0lJqNxSH7YKQEawd8S0tE50OyfKP\nJjTDQ09tW/9msny5f6YFRscHzIbThNRsbQX1saPn1Gu4rhrY5lijfWRBI18U06gYijFIC5rZDP01\nVBYwmOnQa+ODOGfcUiQmM5pZVc0/4xmoHedHdwn4afREXvUzDZpKM2ZwPhNdB/Bf1RFqcRr9sgEf\nIub20BMNkJYzK5VVtGRXanivzfdoCbqJo4V8P/5J/jpsiDuZrb6BRaaYsv6z0mpEcr4RDQLHVkHN\nuy/UCVRX4N5yYskMUYbh+yf9ItFGH9xiMcWEvuCIcyyyXxQdjN8M72SBJ7rSGqi/iT7lD6zS9rCt\nQ25SxFqFjyMFb3/PCyopcf+doCoAKth86socVbKc8wQxwpfsjnsmDg6VfStQW3j6HbTJRR6cBKWg\no4hq5QyH4OzFyrWlze3EVjvAIRNo80YsifUXn/YmjqXkqejTAMs5rvnQMXvCCx5iTbO8GIqe1ZIO\n6g9nf6cdH8rgKjU2irIjf8wuR6WdAKliC5HyFO8HHKQ+o6jDL3Gp3V28RPoZe/ggfrNdJXuljh2p\nxgmoX0sLC4F1b8ary0X9O5Uk4Rm6NbJpHEMhDyFLk1/DSblBMxjOyWf69ua/+JJBU1aCUg73Ef5C\nKAF+0i0bW7wQ+1F6T3OIrZADAm3G0/7kCMyEk/pFhEeiyRgxWwHJyu8Lq3uncIQ6F+BT7fiZp8Lb\nzeD7TYdel7zVmCJayJKdXAqYfe4tHf2ggNiRQtb6rW7zzuDWxC6j9MOehd+wYLkKuWxcheZiDDGY\nXoW8Dn3gDgb6qmAR+aoQ6SUd0NHC2KkR9FKyVg+bhUh+gryvAjrRb/wdpK17v8W0/2ConYAt5qvV\nSx9opD6CbxukzGkKByTs+VXu8lWI81F+WVfosuLsrM3FC7WwGAbBF9jP7DkjemdKvZgK9sQ7+E/w\nykL8i/agCWoq9h+u27h1mXU6LVJOUIupwTkiLc4gn+eMXDqL1Zs0XW4Ft6C5zRmojOAbLVdpcML9\ncO8kViI9Uir6g48iHpcD7UCRyJ9cYSxliNW/0Rb9paOHITEcA0vN+6M2stDiWjLaznLsiRPKqFdo\nrfGWs887UdLqjo8r5gfiIx3q6dJCU+McJNwPj2I3Jch/01qA1AnDeFImKz1P1Q3HCe1YUpwzVdVf\nPkhvqIK1pUei69jyfiI5P4YZY6+RsP2tTebP3EhStUcOU/D0JIBRQ3VQrJa7Jzg7XWISFhF95Ti7\n3z2sHCcTzbDUqq+3k6gp4LymdHgAeI7RRHTNZ1hM3gc+e2Uv7wdyHBjADM7L9XBxGBNcR4RN5X/O\nwHBTw2vsQLZ+ETCgA03rkxnuHqpDB0M1lN0U7rKFUSuPu3NDS4bkCedhAckj6irfUrxnUC0QgoTs\ntFKAHU4pGb6keU3Kg7myTPkUugg3IWlMW9CYcpswzcYlzxnplzkXmUsTb7yUni/FzJOxd2qE3yTt\nWQa9KaZrnpU1W5773WQ03FUrxVsCIZefTOPmIur8T7txGR8gnCqsv6QBEWRakWYYXlNDPF2o7A4r\ncVeo8ba3lyADQB+lGcry8YqZvA2wzuQ59Ct4i0KA9Mb2LF9KQ7bB1/9OTdfRZWE8PslluZPYlEzU\nGIiorzNfpWh8X4UZP3wT2l3N9GODYuwlA54ZzhLwHUMEGM/utYMeZ4VrLFEqJHjqnVqVqEm0obrN\nPZqP5mgXq3WGmC5pYfblJggRYFU1uHNmMHxPLzFUwLZgD7GeQfZGvj2C13G3y26TPQRTpuhDb35A\nvsAETZta7bv79C8GhKUuszAXdEQqSt1AoFC0iB1GHCSIayhEsCwyn0tZAjwF4K71go9RPoIkdhxL\nkDi3AoLRdpPebNp0ZkA9jEvHY5jXMLUERzVAQloyXoj2mtsRNxGVEfImCoMq2ZVf389ZlS6517uC\n4F4WcDbMyf0BmdD6i/dLuCSP+aCs2mm8HWSoppsZuy2SM+34/m/fZC3KiLWa61trhcRHNacVqLWM\nM1ySVSUKbL8qF/lX5NNiyWlQ/hIKgo5zbSVAjFIuGdhB47cwhr9qYQOyQP4KYaqkT8bOk0gV608H\n9Su7bdsKfB78LbLtQvLgcdNmpq12lLrtp9JGg/aWPRjjRaXmzfcImW6wBiDh0AY6WYpGq6NDGwpA\nhLfZGiij/5kgTLLcNTwUpioAt8QzoLhp2p84Ra3LcHOeoAkKE+yMQ4mK09MSzL3P8Ld3KD0QDPou\n1mkPSzbvEsAv4b6WlnAkHgE2C1liHlCCPEIbY9RLAAIFGGASnOKMf/JBTcFSO9khlVSyREctfL/+\n+2sm5V5I000OI6HLT4IQGxsyKIQvLst4SWJd8GdsMkxBNNQIYLCFd+M0FLfYVnhAzTiCmhTAdxgY\nRnLY7sYZmGyfqmehgJkb1ErB7sPfr8vyZ0Z0qTGm6pysX+dmnzDmfCExQjMKu2kaH/Jnkf/0K2QE\n0mcQe+kaAC78lUWAaER1hQxg/ftOI+igRhks1sWXY8MhssSIc7iGfYiaSX5yUYwzEYIHyeamk+D4\nBGZ+YPTRPzSmZn6JHsKxCpVHspJambLKzdn9L1iverJbe9RBJ67u0pDof6txNi6q6cx9UXuddpCI\nADEaNB0dJMRmsoCj/fzzaSGw17nmnS+BC3WaBGJJ0aCoAnc7XqxprYwTNjCwcfmnuTnz1ll4P6KP\nR+tCsMDxVPxLH/eOccJdv0WR697d04aU2f4TlS+gELkIjB7NOCRbsRGhdrgC41wGRaA+u+ADhUP7\nfgqEuPYH+Xlvsr5QZvd0mPJRtUhqeR2AuVxy+G+kreN/F08X6X8tMFL6Avnl939hF6Tg7+BCy/Kx\nsrsD7ivYDRBQnMEoH7qkapYrGwu2L/ehj7ukBgOh/3Ejp1E+c1s1tWHeKPFMNpF2yx01Jy+5AhDZ\nPSdTYZFa7GgCvLmaicDHdeUnz3cvuYB2rZDX7nVooQnhB8Rf+6UTzaLdWwGrNu6c81vDrNUZGidl\nQpQwK1Ec1ecQqUWRK/KRYcg6m1Ot+IeGKFnPa/63sxwZ9w5pVjXJPGPrKvbZa+Pia3+MyDaMUQhw\nBm7TiPETp8qNL5v2hc4ybZJ1/NoEc6gdnGO9J8VQT/rE0pdpllH9k8vOItKpkEd0jdM2GPJK7ZuN\ngT4VCNV6rhNPeauuN4NuXgK+v3g/K4wTktuiZM36cOktYWhuiMZu+ZjnMmX/A5QrpZY+t9Xt2bxy\nbHncUMvFL14jNC6856bBlk5GSJjHRntBzQZMCIPtVN/C7jb/kxC/Q7mQMrWGDUbmc86VpIqxeQJW\nzEbg6DHJt4qOKlU6bzOt8FHPe3nnL37FuSrsjXpMBPVMzU6CF7izUOh5UBzaFpu5fbh/g4VrqznQ\nSEQ5WlWoVXW4ZN/ojhEvPD67BMdowjFSWDwe9HlddgB5BC49PAYRBh+jjeP9WdnkJ6GMfTXpMvgJ\n26AvgS3NcETqckZHSEGXEL/OPVvIwi8nyhmM/7l2ITTs1PcfqQdiKkc+COW6I/hfYNUYQTh2Aifb\nDt5iI9OZplitDHVxotoP5baEwDpoUsYSWH4r+9DsqjnnDi7BzEOGahmcDVhlbI6rjq2uhPt+/p38\n+LkfOBeCYUg9lxYke403tx9nNLtpnFQ+qSkNG+pUBDWPYGdMnrduCCwJnxaR20CQJOegEZCtYDGD\n2Pz7oh3uP06B+ju74IrcowxofXDERrXjwd6aL2u1rgWhjNv/qvk3swUVmQ2VnYZVN2u1qvFFwOLo\n8xArvHTfDmfdrv+mnz6ewWhBNZHVrK6zR44f5wUhX3ohSyWzCmey+ygAmJrPygJtZw9dvtjXPfkP\nmq6gwA+UUZ2D/1HAOpktggmARU0cJShJJl/ZQbfEq82hZjpZo4tj2wQquzt3CtJJ1biCnMf7MQLu\nxD5o0THKOO7mjLvlVn1vM3tTUc4TgSqw79cpS2caat1pA6PVms/BbFd7QjoHad+W5Vxhj/3Wdva9\n+rbOmR2Hr8d3OazwSj7QDN+4RyMmE12o2q4Wn8ZIxoD3tJCCKuOhqSWPDKASZv/IkLTin6nfXule\nIs2eVAEvlNHa3yVruUydEwXXk81lM5Uw+tSdYhQuqPKwBTGysUzTYknJlqjnyiJoXPUd9YTrcDuh\nwFtFWGr8LHDBhe8GRsZMvaYVZ16IRpnWVDZXGMMXqJNZhBDZMowW7UiEdpYqEBpvKHYMG5ASHsOq\nH2eZFgW7h1wB2fWRp3zq+htPMYw1HPP+PNgsCtaRQubfV2+g8YN7JSdRuJVQRKB7HfbRlfal4MbO\nQob2YcOhWtM3Tkow+j+pMAfbns+amYldYEUnaKZZKXgICtzUe+8tc6c9xgVYa/sNKoIeW0nQBgNM\n4rCru5DDjI6BMNPTgpTdVNWaZG8SR5DzenlSrkXBFykWTQ4LjxfY9iSBnutE8jbzjzwPekKq0wC4\nGfTVpOKVUaTaZo5wkojWs42LwU+Fh2ieJ0FEh24ZgSmFkbiiKAU+zrc3dANLGSgsgvCfVs/nP9OU\nJ1hObUY9Wo98gIoZr3Gz0C18ojCwZEb/dDxvyJM56jypCZsl61dYEVTjoW4z8i9chA1Mzbxs9eCQ\nB/SAYWddeyQDiHx6tFAi0C5AhuE8RktZjQ2yt9UFiouVgJZ6wAl/my9J6gKj2Am8k7CzKhlfV9F/\nVXJXNDBDxuDiqSec9vv8heMTxQL2hvtaZRbS4Nm2UH6mj2L5VmngiqZpUahulzswui8rW1Y4Wnfs\nKRTh1jiCT3mA0NfnDcq01KTgR38nkQ32gdQ42NUQGHAie8oiq3p6WSea/2JzXYXpKZb+cH45ODro\ndyUi4j/yaktRND+QJjGGrC4CC8qT5iwirtXKo9X67CllayE6G25mEe9A+huiY0thk+QYib0Lmnk1\nc5S1eJxEg6Gq0HMfuOIW8ogQTs++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qvZJ+ZCMnS4whysx+BCN7ma6YkyIFNzyLTBKHcjS\nE4yr0tuw3kDPz5v78ORBOVhPwizhH/dYdZV6B4mpONFDbGpxkNkVK9fLeTarpzCabmO1Cn4BjkIp\niiT9kovJnycvCa/1N5GHTOyUxMQ7cIlR8GyuJ9G9vjXMwxgt/iu6Nhs8Xf3iefAXLo2vTG778wZG\niKCTTviNxG6RCk8eWCflhdYo1C27j+Rqirx/r19s5oysIyqAS+9JIvOVLIg8jHsKyFqJoA/bNCFW\n0Ygrq/HNoWa48zWRfKr+os8ajBpjXRLOUeJhAxUEyFZWwKTJX5nTylPs+PHtuQ1bmgj4YfnGYxvl\nKvPBm/3LmGttISWgPjv3bic5rgM/YbQJWlKrDbIbTkJM9dGIVqw26kNaoKEGhqo5MGof42C6lrXE\nqRv3QktEZnMKBxdGhro9rM+0/4QV+aqX1Mk8X2EShfFeGJrur3mnwzkou97INnrS+JcpT7To5jQU\n8Ig/dgCx60pkXDh9dcoI+//AXBmIMTNEgpsdZ6wXK8vuSIKnMPcr0ID+Ztxy3w8MRNBtswnCnLsp\nhBP2QoArHvrGmhDZjvRiFpzhslgdPyiMeHyaQCICXKOF55QZ6sa+C9DkTJugfp2EZQIga5LrSTc6\n3rppuK6lJ1j1+cYnKipG2R5TcJtZYEWShSakYrnc7XPyQej0Wmb8qjCXO+hZmkIwnMTyoiWGBcYM\n09bc7DVHXvI+nlwPUh2GB0OIBveYyuUVzALBfiNkLkfMZ4Rqt8xNNMrsmVGziDMhoQ6nUl57Io/e\nlClBb+8fioCu5h7vDGc2/iMQLvtjWVYutiTPp36vtvUG/FoMa5MrJ6s5MCEAqI85DRmzUcebGP4v\na/K9n6bF6KBPBtScqz8oZlfhCGDyFCldXyqteMR6RZyV1yKKAXiBunsqmukS0xXpk/0BUbHgCbDd\nWWxClazeNUXUabl4DDzfN82FipbyFe8ShlLA80QBEES3Qp/u2bRb2cx+nnqcV48ReQsr4Pi9H68u\nY4jtp/sti345Av+WI96CPNYanltsmSKatJe4mN4X04++5oxfI0B2IOB6ZrHLPPB4LAPKz8/FiqsA\nKrIeX7V6Rw3X6sqlox+6PvJcpK/xrO7wCPcz33aZT87UVbK+rFka1xcQL+8T0yUDvGoKsX+1SygW\nWOu5fA6jInKD1e6gct0HWVj85CMVGApFoaCYCY+wKsvxUnJpbYgdRUMDayFyYOcSvPcuWrlc30NT\nzHXrPRalxD56Ym6Q3gTiEtvwj8PegDnb7EtcZ0uwjK8OCt/U3HrmFEscrH8i1q6alcAPKtq9WK1B\n0nwlZSUaYz+DnXD+fdlzQl4B6DGP+z65+kJ23NNlQ3O4FBsE3CVPVS1jInQYFN1R/MZ/NDsNKcT2\n/9HOVf54MFx4y4KYpD12c6rt3mrL03cr0AqQpOjfGPOzxZAOsxsGx5pydhpitDOsT+YLpdDok65f\neaRNQOciBmskv3OvgyoedBPWUtssp4dZRWivjakHQ4nyzSB6LPBzdHKugKM7Hiagzp3TqwoBg03e\nocqaUwsmLbrrweIw/zClSv0Ybb4PA11ZEnYLUTtBEF5Nvzl7ygkiFthizCzrS7TZkkJYYB8ltUUs\nzcOKgYFoNkTomQdhNHo3sWyNjhqeCijCSV/5+PllquArtqQuzLrMaQkCdQ68163mfRWsbzKIUbuY\nLAM/FnMX8/HTvqZl8gSN1yOdYrn5yUM00CeA+ShEd2TiKPWygLaUZ2MTv1YbNQJTZJRT/XYKjJQ3\nPCmoXiiSpSvl1Xh8mrDaeqZI/CR5Xo+7ItoX/fwwHs9nhipM6AOPthpsCJGNSpl95Qd3V7BZ53FL\nDAc0aOuivhvZCafQo2FPwjV+wmeEEBvTX8fZ0KYdJ9juXbCU83XRxu37KZxX6UieHu5H9sDi3v7y\nlMOmlu+PZvNPh0YPNzUXb89xjhl/XkrP5GQB/Puv9O3TAheVV2l4vi/GbfC93y/h1eLsSzkIHVAq\nDQKexnt5GJrnKmPCE0z6exBRrNPLJRxivLXsgEfcNg40OJAxbtsiL57zWkswvcdymPifzKbue5b1\na+sAZQZNc0yCKa5H8zy5gqK2epyicY483zdRS/BDHGdi+H2zwcOinQEbWt1uv6iKjOin15tbfsvv\n7PidT58wPRvkJKx9xaeJApmPB0x/z/UQwCGQCSp2PriFN8Yqv3vrUlA2A97FbW8rAoNtU8l1PgPm\n67G92DFxvYzMsjrFLicOXoAq0jWkESzbR0DKPmaZKkIShNKFlJigWGDVNPpMox1bNvDMH5J7LPZ4\n1wWixDY/ZS16rUbmxHdvfir1t89trPgVxF4jXaQcsnokQwDLQjjj41WUeZR80CcrJ927rx+f7tHr\npWhF31kQEDHgBvQBT8/POvhWv4f/mAfNwYSWylKvRAH6+sPoo361/wxXsq2q8Tc5m36wCxhyKS9L\ng2Wgjd/tDIGqlKNVTMaROSrU8YX9sZDpIJp9sMvnO4p818XDslDKxx1yNDIG/WxWuS+1SajgzUpe\nihK4Q6cnKrw22SD76yZE7Q4vtl4EwPNAisrd1ooqjIpsbW62kz7zPQFK0I6otG0rwwZ5YidX8FCa\no5M3MgSB+gDNka6ulGapZFd0IpvK4uRo+QQMULNO7QIM29KsTg27G6vFaAOPAjJm9gt+1WYOE1XS\nnw9EOd13mvBVZ+t4t+TY7SwE8ThnyRJ1gZ2L7Sg//93GTdbdEDlFiPnIzARxJzBudVU+3QEXE/RH\nNCnfuh3DaThukZSnjIEG3hNae1YBonjqFdbQfd47oOPybmPm9X1U+mKxmuPF5OQ/GuNe8oxKnu5C\nWdufrxecSlWnGMusxb7gbzcFE7dDL/grNTD9vQ/JPVDYfXmsBbGUZm9unK3Vun0XjadGgvRH+rfy\nC65jgpDIrKeWZr+oQW6dRLHBuYKMAbwSJE3BoT55PXuOH/dL/QvfZN4kgnFmo1yI9wgh1SSvF0Xz\nHrdg1nZp0NStwjiZURc8+UtEyOO3lNFjC8djdRtJDYf44YQZjyDZQtd7jdIl+TXJD/GcWnzhynwN\nTGmG+RFMk81Hr42hNMuaghElfpVbtIJnJMYlvmxT72ptojCXy7hczYP5vFEW0g++4dz7DZyk0sNM\nUJimDy3CDpgimqEq+KtxF0vMeWWTt+pWI2pAwsd4GfxrDcn/8ApWymuXE2ev6QGhkHLWwvVP0jHX\nwQjnUKDfHwhhe5WrWbCdPHGiDLEZ0ad9baM8ZWRhoilq81aalMGswIzIEzluihzHoobJ/nwjm24+\n9Gr7OS80DeyNDBc0+dtxoCu7ro+OWvfxl7myvwwnvq+AfPzWUcPNnI0K6xgIVpngiSqcjaGVFudV\nQrunp8i+ykRRyNhN+sH7p1Z5bWV0RI++6WWCOO55zp3fINIipPizzRWzQaq4pS415l+BVYgFiF/y\neQPnEFN0XhL4MlRRZQ2C5cVkej4hQJoTFbXMCCGzCos+M/6WVnK0RgBYp1uK0hcpwPz5yEeRb5Zg\nYLbRBoqhm8M5Gc2PfSRW5LWeT1NVikspCC+zO0c+2XEcl74GBIM/Os7d2YPYnQIwphJ6tcGd6kJ/\n6zwtKae0LKo2p4X8J2/LXPKxhHToHjnZheRJN+Ws7bhWQb0awbS4RjoAgxQQ4Uq0atWMLjk0ui5J\nO6HXgVWzY+jzCoh6shHixW1+BvGwxUy/Iy+iUwU9AYeG5W9S4ZMOP0FKCDu/DhHOWn6AHJxhRDbJ\ngZsCnwtrzo1teetnUOZfEc2eqto9SeuZxuHeofUJRFiimCVDXSer9XnIc94XzK3r5aGLtlQdVqXE\nrXR58StHCXah+7I2Igw+8Yp918fUg5/ARHntXb2ToyiogzGS7wLlx0ZRPZ777PmBHNwDGr5D22uW\nEylrVhpmlgJfARtHEke46DXR+vcLzW1K1Z5GSyvnOQVOYaPE/VSF0chC1L8aXm8TykNWOsqqFHqa\nizB9aKBGwoBrzzLirm6b4zIbDOMD4bBsmTTVjn51LN57+7gUwWR0hF6KmUNuGDDJsPb12o5jdpC5\nhuzsXk/+le5CG90IcxAN1aL0w6s36e8xoDnShTDihHvu9Npu2hMrXXYIAc28kSLww2HdK5Yi3BgN\ne1zSyMky4ACs+RnGYvWHmP0lN59X/+mLcZRnObeYLRKpAzRrSNi72f7AU7LpdsxxQAQ6q6jKYEs+\nA5fhmyuUW3G+AaF52mpaRE1OJ+YKw/qLj4R7boI5jZ5P40Z1K1fVRCenPEFX6IEb2NcOlgNjLNCf\nfiMF5mYFGz0eamcRhM0RItlZkWNJe2Iakazklay7mW/V42pensipU39nBMx5fq8myPltRu6F3AH9\n+zWDsJpDTn4bTYZXpOwTmtNiSm9XnTZbviehgqe0OHUHFby+i0XtJmTqoqQHlJSEt7vJuZX643wx\nqEnZrxMcCR6p6psZwcxMv3qfVsMQtWp4UB4w5T1OGtxY5ACFqjDFli1CChYwcHDdP+LnMOWoJReb\nmrJPq1Yp98ZTUpmEAeIU9CCgfbLLa9oyCcHfVa6Lm2ZT33E/eeFer0L+PPV8hloIiWXjWvjIyKjx\nInZpJy47H011IlrofI5xNkU7Pun5+/cabxuuL6bFc7Di6dNJwwgrU/FBcutPz6mUQ9ATroMac7OG\nn8xMFAdWEXH05T4KcdPP1Yo4jKE77NYu1JOtTxbSKIciRZGFBKUXwkMfmkVSrio/6ZvPUSO1ATxm\nD8rndadTmvy5U4N4uwE0LDNlbzRBrQEpJQV8kX6Yi3njGLHUes0x6NIgE2ou0eMnsNiXggENmqbR\nXq/UGbY0yHLg5mnmEXQX2aJu2kj73Jqxnf1ie9QhkqxPTt9hDIcb5/xqpdnlQQCfdmXPz5BAHuMy\nyTpHpGLeAp7Q2VyDM+6T/k4QWVtnnQd4yR9oJFdO5c1caLTt5T+W1wBwgGhKtmqYsdb3dfnfuI7P\nnccUl9cC0cLt8jOVnbVVklyrsryIvWClOEhTSaOwmmsU7sQsFBPLDRswYednMSaz3Fr/ldTHIH/l\nRNf/5rPL/sepbycc1cnYhL4lMI8PuuF3TpikP5aV822eIq/itmBp5FeWOFTlsPpExv6FN1KtextJ\nlm8ikFNPEI/rvndxBE+5kqTA7Ut7SiK5OwIWlDxbFKX8GwaSkh6gxecLTN8/DjhU2R/uuTAZgWRY\nAHughyKHd4V4LKBLK/VNlu6xGLmu2RPpAlV5t32adrb9OdBS2BSqwHc34tYnzT8F5JnIiYqdjlX0\nCFtcql4nv5ea9dSEaTZm1TWJIl8yJanGq4vbxLknl/vgtBrCc9OF/ENyqUhEop4c45UYDpCLaAvO\nCDU+eJ9/5Q8DxVE9cht55IaKxVEhUAQjahx0UMIc9zzQWo36xPFw6efhpXmCPHzDgY3CirPIST9U\nZtJNO7hsvkRXUi6UF9k3SMoQHugIltuGT4oaN2ie8q4hWQAAFlHDbeNSIO/OzTZJFwRltUzW+eP2\nL6SjbIXFBbYeeGDutFw6WZHmhNTePMBDL/YWxwEDjtq1fD6ZOZYfWHxo5Sbrj5h3AKqAvjfooQdZ\nNXZ/UI5HRrK8LkB3d3OS7+8QedJy0l0hBuNdKW/9ZSV6v/aPaq73P5Hsxwub6HppOTdpuhc79mGQ\n/BL9pDmndVUjWyHcgyNkt+zcO9z6QD7PVAuNSZyCb2mI+Bff5GXfNbfpDPMpONpx7ky9z2+yr1dc\nXauIT4xqFGOXmBIPXbiJqIdb7ZHM9Gi3/k+4PBHgUknBatmkDJ5eecnrjZ26gwas6Oe5lVS5KLOg\nGqXTIVVFFpiYzK3ljzoiT0yeBqaJNI4pbjLfcboRyIF8VIWqoO2IfYdEhoC3o+i0Yl3keAXcLh+S\n/AXycHMCysu/X788u4qjRxfaxD0xjZGm9dunBZOgWm/yfFpUUIZE2ozu5nF8DUaEFp6vXVjSE7OC\n02fb7LzkwSuroCbayLt++NlPwDysNXHq0BbIC8BUW+7COg9Qq2NB2AUh03NHpEWm1uBZuBVXJxoI\naKTHQ3t6wWxYxXNg6z4TLgc170rTOlgGGp3YovVUcjXTRTHomEB78mYyHPLuCRrYEW2NQ4J0urgJ\nnzWCUwF0042xITA7DBxUAmoH41LK8eL/DYk2qg61L3MJAJUX3AAr98caLhagCUn01UX6enPIKQb5\nnWUVB56bgpQYcLifI2EwlpY7hK7HFeWXrHyhTZQnGd0p8gRSS8KuVRpyH7z0GeetQ/+myE/r3aOY\n9plLEK6QPf+vNoK30hqRzbsnu3cys/K1TggUEVmS4N2c7i7OcTTRe7S/VDkSc8ZgoQXnOpJVTsiN\n1v+5FUfsmi12db2BlUXAtUM9Iz+r/XxaciAzOgFgFHQfl+exQV34Ney9FwNtVJpwXFa0q4nIfts2\nekxTFNLzEAyhDYtgVffuOl4VnPF9BSHN6y508ESUrPdBJwXfHzV+jflurF1MCqX8G80p9xDud75a\nmnGZPak1w+6EfxPOhAgPm+NonRFVRM0ki3B3HZW5HKs0HGPiLl9Q3ZQP/fUlfHDCeKbvT0xWPKXU\nXXgxtu1ZNmEvyud/3jvhFDfmjh6AaCKi2XXMsh1BkT2a87E56X0VGZmscW8gdPzx2UvCqsOa67y6\nnIiWH+wTfx7jzcaZEY9tJhBxicXzVAkpbL7hh2Do2hGc83L4n+tKZ6IN2tq1FXxdUJmkVh2cLX2z\n/Jn1ixyJ9VdzWIdzkFKwLsA2QD7ns7QMs/dl8UMxO/RtjKahl4TZl8BTyQfFd3sQLIlQECEzfKX6\nJDKfd6WAXaTYDedLRVf4TCuwjx1rLab5XU4zhO8Q1Yku2qeKD+hth7Spsn+0i5ocMLoBSiCTpZ9h\nXn8ds3geBGqt2SPd4eyMefSzBIGx/Q00rnMIHHUVN3jQ2oxmAbAOTgsqd5GgrLdsLwRQrwpBZqsK\n3J6LAW5bFThJ8G66/rlxbFInnGCQ4yXlpbHslAgsDBcmk0nHvM9oG/RmlySbKcQ2zAlOxVrA2hGf\n+SWPpsoPahzsXFFJuAXtHzIM78ErCC2jCojJaoej3YR63BqdghIaE9nFiYcVBQmNBJCybtRZJT2N\nB2pPbfAVXCbVS9SFGQyAmmyOtB4sgXG4LYaMSgLYWttbh+Bq9gGUJaYRur19ZmwEqYUAWu4ACyAs\nHTjhc602LAuPwH9ZGwCO3EbfbFMT0AyaCqY0u6qW2OIOhNDjGVMooNmLyj2RZEuzlJcNNDOs9GYv\nKNrrEuZXcqkjZ5v0MjIkm8CXX9EpU/pslZMYmIYHuxUFOD4ZCC5htF4KHvR64VAfy8eJZnjElbQb\n+h9ZFi918azIWgSoWm5mPnDYXQUQhA37JFZMdLrBGVWd5J5zhrnOeweKYUsJOVz2UhrKIOZWpNV4\n1XboWeIC39bRJQh4+9g8KY8keLAK6avgMPrp9Y3+RV+gzucUzb8S14/b4UsFcVv0FLDeJr1qeYnn\n77ASlZSJ8MZZlEy5PH5iLp8xF4/Jcib7bXU0DgSOHqppPU01FWFAAFQ3pdS2vIaSH0ON07RDG9Qy\nDmlmF/n7ek/vZIjfOXU55wrDl0II6bocsUVBvIqMki5b5JqGzm28HY5AGgN+nNIEw+N1n4gzKNGR\ndOIN9g7gMcmFTls5wuBWvWHP8awlMGRvasNMXrgM1HkIis+Dm8TQAJ4eRFgDj9Iogn6wvT+qgShM\np1iCgj70yAabS6Ohq3JZtCernQSX13/S92WHEVe0YKTT0mH6HSdoodhQctB3XY4D0iiNZJpC8zqB\nHlnlP/RZft0zTU+v2hmkGePJb2ia/jfiGu20DZd6WM+8Q6cifUTUwureuHURzyZsx5zyUb9WAekK\nRW1xl21z+xTacEK2L8qi3EdLgEsZXUzhvr27O1QV+uIuL/V+/YLdwleK2RAqn5ROW42Y3Q56r/dV\ngawH4Wl0ANU6S2JwbGBais2O+2nLVwhLQriUcyYNXhuWc+7xPwsAyHw2R9M6vb3Kkdg4Wcfk21NJ\nMyVY6REt/UBtqkC/hYVNoE5n2qhGSpoRWVQQFCkbew8WzBWOZdyzmISJQDyy3b3BA237ujhb/uJR\nzRuzsGaaKnA/cog1unB1GU2VUljglPDy7n3Hesx5xosdn/gxURO79XFk5S/jzWaPBJuvpenaFFxr\nyESg/K2qR0dEvEDJihX+2a/GkpGghU+ZhezhnC/mapM0ykkmzBxUwUrSc/IMUWmpZCpVJrNLVYOF\nnJSPS3KIxdL1diiYh64ICDSHr9i7pqKueTjsEK67qlhAIYCk6xXck4I5C2kRjRThjv2EHQxOR5dX\nVe8XbzrBwIiyJvvCxm3g5+EPCt0b6EwYALvCH8WAZ91lCtTCFqomRB6/dUS23DP+Sx0y/QYdr15T\nRZTWH8LGyO1E1W08SYbUFZtMUnNPzcykFRMCYI1IUWLBJXMMPtiTWlyEltXCCL3kMn0AIwnYyFvJ\nn7SxCiA1qUsD7CWrhRpOU49dneEphwxJeNyz9bOUGxcuqUwJbnum1eH7rAtSANIQtNZaBQ2Ke6oJ\nlzJdhJE12MRV65B4Nsd2fZWUUTBQM2uXE1k3NQPO3xQ7bngSv1sJ5so2zKPo7iMSdH626ljtmqmQ\n4K6QlEtlWL0ryLMVOe8ywCbeCs0+KF6DlQTPjvaRIFgSf+/XUxGSNDAP67Ww6HJGJvhnJeA/bOtW\nkC1vPFANG0f0HbgdV/VGUIEMPfTvVWQI5mO8xP2mooXHRsBUytHDx6Xaqc/F56+ERQd3bsJ0U05A\nGY73sBTAXcfT80bail6td4LXnB6q0mGIcoRpavQcXpT/crKmwSJau6UOwwVeuKIBtvh72mAKOXFI\nD4jy7sk43ZbMnS+4o8p4lneUY8fHwRlAYDs1OFhi5nvGUjqRfrW4W7D6NjF/ao2Q+RWVwZYgPhmu\nc/QpJsPsoyTZyPYiSI6X5gQQRwgy6PujvtJR2cllkLm0y2X4BnRNbQthFy2DGmlXwV9jKpwHwCkQ\nNUudN5MZ7wkx/S9/gtj2iaAZzFSlyGE83QahJLMkTHh99PnViB1VScVdloR0E/9zj6HyijTBtz5c\nTvpFgdEm1VltojHW0yR3KPsfXBPNvV3qxZGcine3CYB38XNAoOpwQ+m9KiaMjpS+Z3g5jVSvEPRz\nI6Swyc2GHSslRqysHLDmqIFkPYMglv6rb3SP4MPqxcHdDQ42D2QUrIg5QGSsCFVKWYNzuMHNS7MG\n0q9S/CRSYZI6pd+BdxF7QMfYvTxG/z7SX1Y4He65yVsu0BUGxVAycgESC0yqDb/mPS5gu8ICCL/U\nKFYEMO8VavxBguJHpSOZqgfn9uQPdQKICYTyk3gkYwquOIgMeAzUERFY9rDolU/bFQBcrEE04bCl\nGbT1w4HHb2SwKQtCKUFOU/iz1/RQhSELBLKUUWiylPcK8ah60oQCSYEw5Fp/BmjNb6AtVYKSP5lu\n5OCzixPZqSYs/qpGhwGoFduI5ihI6wWRCEmtDWr4fn/VaQEIhnrCOaWyCB7dopkGrzthw/KTqugv\naPwLPvra19o4S7x9snvKUE38ohqiZ3jxQqQhD1jzOVB2BL5T2OlqTN20EzxkwlLulKoNVmKAloLu\nK81FvAwebD4TJBam7Dj09uvH7Vc4ovQsnweC5ZGwKQHDr5l+KYUTpuzAV56b1L4mWVv9KC1AuoWR\n1+u1AypMa7rfYuU8J/YBsH3L2l90hyykLH38XhVxAMQfE+rppwXmCK50Opvfu+3464I40J41o3/U\n2ukQgp2CV4cEALbpyBdHPBeTVEsGU7XgzZjhL8ywTq2g0uOMdr/GUHvajFz5WmKBD1Kn2/A48CSp\nNOF7aTFa1MO+YxEGpsbEGFzGwB/8DZSAS44NI2IJwsH+Pqdb5mDPEp99GepNImg4ax3xuQ5/fmM1\niCvyST6YzO9vDztRrx6DVty4yCz18qh/CBLLq2VO5mQjtLwx3EEoU5WRzivutrc7rYh7fYKPzW6u\ncMCbmpHfD4KjmtbzdCp0jbtSJ702e3alBxvL3fNxgtubgy1qwi8RdognRQaW3lJmodwMVdrO7qL2\nATWjJoDQ7N1vlYlF7a5JdHlqQdFmmyEZOcyxul/lb+66+qwRWiA+s/AxFe3OmsWkfQrkzcrm3bBM\nYCgq7RiGK/Nyg5CqZcFt6sIPEbjDril9Rk9eyfW6+rg2ti5qirauu6GTi89nmG90XFTqbWa2INSi\nu/+J87FDqz6mNQjHTpylfV+unw/2zp2uejZSOmCYg6slgJ5VzEmbLA/loWbbF169Jss2HKsqkJU1\nFDucH9pO1HhVVLLAgvzdWWSWVqHggZ7fdGPKKbND/q0DJS/MlSC4K9wc4d+a7LVqf7YfcArWJBSw\nb/CDJopZa8X7vfppRshZdLKB65dkiC71qdw45IYggV30dDfgL4Y6lqB0d83MFZ2fWmFGA1k+6opi\nCCFPqhmIsVyJwa8YQWio6rNR1n3Kf+cb5LMmmvDH08KeKeBi94wzMkfx8HbU3C4pNA3tFI8HU5lu\n2zYjSejh21ePxj8+f7hNOWHj53eIVwlGFJbeHtuOPKRCUR0ofAhhjWRTTqd91EmVEEKVQGqTsv+X\n0Ofoh1RZyKvBRJFf2qKEDx5HrHBNDup38TtEIQw5seyIR2VVWs7VfqMlt1PMiNCEK5djB6+o6Vq/\nPx0LnlJneHZ4aPg+7Jdx1UYG072d4qEzCB1Xqg37CLd3Y+xHDV+7QDYT75oX/2vO/RsHH8+4CwRy\nrw0knqI4mwfuKMWauSJU5fNvt6owB+BumMxKi6CJn8q/Ahp/Qkye13tRKneKn9RIxeKkXX4bdp3U\nPOdPMfTsdf5FfIIT9fsBZk1q+DN584O8YXhQ/vwoYlxkO03yFQy0t+v98xYVtoBWsnIGcVXZNaGl\nFp1BakMoraD+DIttVaUf0wB36pUfnDLTDvuHLmpgk2XG1LmVRvfdZ52WboncKChN3klluk0pt/AS\nKBTVmhloAwycTXnHnam5GBIjPwPDtu4qEf+m1DyGAo4egZXTy/t8J7tOICSHhwa0V4icen50x4mi\nF+80cHQS+r6jwF0I6P1+0waqv711ZoZ9e8OEeCKtD9cg3UxIbQHJ//qPhG5GqYQ79nNCUcxL0COr\nSihjFJOyM1HcroFKCiJuOCu56NDvE64S/ohFW/8B1RyBPYqcsGOHDusP3PPujuXmd9wra9whktlS\nDiBxU69cPygcHZGCAXvFCc6/4qczdg5RBWeH+cTSnEQ+LQqWVNL4KQSshKyGpjX1CQtCARE3/khz\no0pMSYSst5xKLVspDiAYAYwmHaMhq30l8dct7s5EfvE3vTEOpYsUgzkK5FnMpTMQm080koGudP7x\nS04xhfKQ6LW4wSxG0WxmHIr3hmuVc9tsRFZ9T1mIH5KgBBhi7XEvYeFSvhdw5utdWBc9yE1bV/IJ\n0vrEHBdEJQQ1jC3JHiDeNsWkxk/8VV3v1QMAB8N793KXxgQ/1jEoCwo4r+DgCws300qN53E2O69u\nJKMVjejhty9xQp2+lHRIZ36dvXnVTUpvw4PjnRr6nvdxbkar40A1xSTwZtOv035brN6W7IDeKByR\n9CV6S2CH6CocTKT9Zt8vPpltk8xGtfZvL6iP8+E7DEyTKpJNSbto6tPn78lb2k5J+EbZgbkvLq8M\nTagu9wcsOPFmD6zm8ytmIjLDQnJX7Ly06AkqKfoEgCv/RX3sJDmhLxuUrYN2P/XZyZEXHtLmfjYB\nsIWtLwccXsmc3oVsi2Pq7OJa6yyIdyX0Vag1r3cBSfGMXuhqSEbsGPpHGQAb1bemX6ZL+eaRR8Ir\n/eZQNuhoWG52LpqKtzgzdwYD4dXnawZEgrqPm6go4nMxHajMMT9x+EPRWMRCblVLMU1luSH9kaS8\nMkIoiifAeNimveh9mQ9+m9uCae7DWwiSrDtGe5S0aFDcbg5demK9BS6oJ2C3dBToRiv6isyitqJ1\nK4hru5Lh0iC4ja53Qd1Vl1IsNzYAQ9eEtiubhzCW0UnxLC9l1YlHe0Okqfplx0X85fEe2NfClZkN\nMVvns0Q6cI1RCZoehNR7MEbMUb9sf+YE/zd78entJAGGQcMvgDqc8GPH3Ph5iq6REzmUCizdjv0I\nQuRHIwhl2tSwe3c7oALp7AMb0UEUcEEa7yNBMnSZAwJHxxIcLHifNZnM03He4c7JsB4yGdsZlDmm\nzZoBCJNcbpyRnlvDk7moNefE4BJO/fNaReEAiICWIlZxQA9zDxlf0qEz2FZgadqLiPvXKd0SRjA4\n6iDTL+0XdstQT0EMQUdeOAiDZ+gMhw8gXB9TUZ2KzJmzbfZUOKnt4Dk3S7ZP5reZ67wa9T0Iow/r\nK6VXvm9MDYeTLJlHKJb26IFas/UWABGe7CEM3RCFR5ryVylbEh2frp60MtSfC0mHZIPj4PZVdoNI\nNiG8ls6YxLThfFsXWp20HODlp8vhiepNTHOGoXXKgqoP4qHxUDqUcc0RwU3Qppj3tAK4RurMczSz\nhhlq8xWyWv5vlyJxmJzk7hfCkbradsEVNkfl6K9Oahz0QpXDpQf2iFIk6sdPbjligmhJi1mM1nkw\nG1OXII9kBqnpENv9N9RSHAqqC2EZ0rpCoo86Ow5r0oOJiUmcc65rAomtlFdRFu978TKuwgSK9C0+\nlvBiOfqqfF1RXBAt3OP8BIZgKX0duUVG6lxYs7unXE7WrDkaG3V/VbM8WbHectyWnEAvRcw0S9mS\nDdiKwWKoS0qbSDhtaCGXzhWMnM28+4kegOOYPbRk/Ztu6Uz4g76nX9OiU9zuNUq1WLLjEKfHhK8a\nGSK7TjD0XfBFlJBN6zICribUSvhRDQzFzH7HC5lKMwntykOMgHH5PeJ5U6E5npyoaAjscpk+WPXA\nO7umsA3PQlzkImQmqtskI30+FAMhso1bisaFVT2D0o3MCcuLkhHfMWr+6sIBgfjsPS3K/nIc79Q9\nW78xWZMkiRzh/66GAojp5UtmS+9z0Yefinic4ll5BWvFt8Nji6T5qr3JNbmRxSLIrWy6SEQYWFbk\nuvDa9GkoamiLQGh8cxjQYiz4sGUOXLRClIx0n/r+aCLxc1osC4zXCCC/H656dE9KpcyrxrxNNjGg\n2Q/qsDxIDgLGrTldEhfzYQxCutaJFSxO5+lBXt/b35vFIgu9EBtQDrf4Yb/vRBnwosJ4EXFzhc3t\nCGxZRFmfJk2EolT7/9M5D6mI5D69lbzOGLfsas8scb1Fu5WzV/LVcuhOFhwOfbhxdKjynFeYJIlM\nMg2Y8V8wIoqQqw/LaPQs50OVfuhNZMfG9jmA+ExAZe/ucokZeZna/5j8jVI/rtQkEIg3A9fboOJs\nI3w+MI485SEWZ775L/kBv3b+b5mquXpb/LxY4Zzek05EvFEWOdHaJHOx53f320jbIAufGGFQ7S+r\nMLP5o3+SIoY8UWBBcJL/pLJPPMXYzHLYwo9sUUSrSNf91mMHDv+HU0Wh2eySI5i0INK9gBkxx1fe\nOnym/qYScFhvYPMDuq+TPTH0iEWD46s7Nv4wuIOAq5xV9O3uryeKpUQziY+T6z//hsGBBWNbBl8w\nILc8gwYVkfUv/2L46Ne4F0DRSMim/kOuxiN/MLiwivYwaMYLPCHBYTLCq5EqNIO7UnifZgY8GmPv\n+dI7bySys73tXKSYwPwdbvMeqWjgnm15QxWxPxnL31tSCh69yHnuR/2UDjSIAvziXETZPI1wgtzH\n4zNfH60m1Y4fzEgIkEhWL20v/86j2eS8LajMp6wG+zX/SH0ofwqc4WEYNTUUVt0txzLsY6vccknj\nAMiGAZ9WGwk3ltiCXvSiA37xd/64b7OTSOxdAKC4lCMw32HOZK16d/EHl772X/CW65LGXjBwz+g0\noKGa2hjFuaO6U8i2AJDZO+yb5Md2Cr5tLRbRSWmk81RoMVUqIUbpNRAsjbXUGZpNblzYOeQe0vt1\nf6PxfYHe7oPrkpdbVGRb6G25F5Js82fbjUpzX2HDdU7Il1twenLOBN4cdD6eLejdhO+pwQdYX1pB\nQYJ438wpPpXiwEpSgmIMlspfG1mNSTxfdEUAHgFRWzDvdbBaWM8XFSyfjpZSVh3K0/L5Oz1KaHMK\nmlL84qRPVU6Rp+NoD29VfZb4OyRsO4UNd4pduIp4FeB0TQVM95pQ6okMDeNIceKcw1O91PWKden7\nflkLY+RgDV691cdU4QbC2BRx5asY+ZiKu0bEWOhkJH2/KmRJITdtA+7xavT839GCEWYZCM3YHo6B\ncuw/VqDedEV4xND7mx0bYG9x9guBtGVTHiDTyb7phXjVe7Fyi/x5t8VufShAgo/rtyoswiJ8BhlJ\niPsuCwoul5MxCFqHLK5B+UZJqSIR9/1VIFuGceMk5Ubv0d1H8Z5bPpQwCvdfLL07qvjUEvpa5mUB\nuJJkNEG5juaNM0/IUY2FxPzrNx/PTRIjl9LuV5dlE6NhxpbJtZRWPj0lE8jjK1chUV+6+2I9lrTc\nrJ5rmF7L+wbi4C9Dnp2x2xYaS/tE0F+VimsBt7l7B9bAarIiivHNFgTe2qE/+Kb1M3H1ct1Hqjm5\nAL1YaKcUqsQLLnEvw5cPBqQ8QW32XBuof6yn+xxK1EOpb7J8gdZC9ud9Atb/F+rDUY3Zk042VOJ9\n+38BfXth0Ew8oVZmdThyt5KDvzgcpYhgHwKbx8cB7uW0LcTT3DG+SLkqMgun6MwLUownC1+r4G+k\nPOYQgyWZ2hwdrVfUEm2FQ8T7jIjofPdRiOV6vMIyo1LQtEHryCdfVlFdMVkX+zEa1uMOonNlIG6F\nqlwAOm8pi+/BvGuB+BRrikGczOJB0Wg/rgpg72XrFf3i1rneXsCsO+VpQRvcvl0H7+GloQpZ8e4/\nL6/LM7YId2uE/6LP5MJwBkwdYhnQeIBRDsaT4SqBqvFFGUwo9XHQ7BX9hvDKJNNr2WJx/TN4DGSc\nQSXf7zNQkznf33MkIXuht7XWfQq0F2JDmeO2vQWLYbSyGuKMoCeZqlWTINTX0kKL2gXogQo0CSFu\nl3yJUjzzXg8kxWRp881QDeoh0QXJzkJlSK9RcBJyAPoGq8MGVQnhqlZCaCtKwWjxXPJMod56Ofz9\n6d5QEnLnZTdUaNX5elPnAy//gVbggUKwOQ/skaVSauu/sHjK5FOnEBYk65Rd7tYGD0NeBXwgdzq7\nZjElbS8KS/Cefr+77JrYrMx0aZBZJ7PQi9t6EAB8LJx3ynPMFiOi1mFRiRTnoOunlquPz+IQPZCz\nMGnV/sBJnYWAFfT6SVllXQSioS/rUjluR4vovLgImmCkRQKUSj5xnZdY4AVssYcDjdo02+On7piN\n8qNFmcN5E7Yf/TncOjvzUDpXawtm4XcUunz6fz+TAFwd6SFGP3I6tLXK7Ell/AJ6615QZubiMzMy\n5isLZteUKQdn5qY5SU487hB+j5EiF/KIGAbITt3VhdHrimshB5ya4LsOjyuKLV8kB/V2FxEcrVP5\nlPsWo8vJ/pCG1SE+UmhSQrWcx4/NM1rtR7bCmMtSfeu3ZhArzYJK2EjxCmwxqxivMXGcsAByH55s\nRNnTvl30k066eZStn34hQlok8+Uj4MJAmSuHpOlft5Cw/TOrk1MOZFdyyX5HyQGbCwAhDElXG7Np\nNtIBPPZERmcalGEy/Owm1PoUFZGrD0ygMaJgnLTHY6MLYf5DaqbqAsq33MOscg/qw0ro97IvQveu\nbVHyQ8dKOw0H4XCakKKp59qL+Lo06pAmqctYoqEAI6NyA5PBetT83h7XnqI61qecb+efcMBgjAHx\njfy4b1SDC/HxaiPhae5rVoY4Mii9nQB7tuiNNT6Gmu1Vwwpg+FqVEjv+kwb5pFPKdcoYZP+5TaCc\npfDutBLUv54hLF1z9ZTSVfm8dhinFIriv3FGv9/qh+OBVnE05kFf0guuqhsiraGuH03jxhZjWfyS\nOaM8SAV0mGwdime6bWsWIdynqw2HAyQx5ZB4Y4WQMUkJTUZZqfnyJoiPtmujk+CkRIbdfqOinQVP\nO07DTJxDEzoF7uhPsOTK3EFXwpS8pYBJ6rBUpkDv2cdF+nkS/+/cAXKl/YHTpBgNyZhjRpWyxHsn\niFcLNNJfu2sWWDKVydWGDedDKCGcvqLPUsStmaG3e0WUzqYcTIcOw4FcGgqM5B7L1taswxouzywa\nIj0O+yHtm4lcDaUaPBH1jpC3Tx1teYcGoV9p1KGhmnqYHidnh8j5RR7mQphYOBTEDhrfxBok0oZp\nxEb5R0n0lHsnE5wR+R4TmYpqKaUpaZOnnhRH5vBWzpvNoXJZHsCXpiaDJFAEE6vHItaTa0n+jLX3\nsAKceIWi2N0ON80jpDAKDd8n2CWy5iOPEydoKV62sboxWYLHelvWFOVdHFqza9cLsXbUMPH/vDsB\n8zUXcORUvcn7XjjuxPfPOc0t/Q0dPFlQIuhEr08hTBnRjrrlpX7+x6ZTY+fPNHR9F91Pv0fPWCIy\nbROzbw3bSzeY6s15+qHzXfdfy24+QkpwFfNxBLscbYdYMJuaHRfUkYdyiSvy88tiTke0cWsJIgL8\nb6LF55Fl+0MmwuU9qJt6LFzPlqMjg3MTJMUSxs+oM8M2Y5lbhwQwyifFyhKYtLmLusjTARMM25Y6\nukzQRYRNI3Oxe5UbT7SrcwTUy1Lzewof6EN8wyjkP5FSWkYNXeMzogCzF/M5OPrEz3P23auJXL5f\nPSwxg5GwtiAddrpoxwVq7t/SXomVKF8qrK6QHhSEkffLcH8rFeij+Eex34jAGjtyYThMr2yAKAjQ\nvo4wSdK/C8Znry4ZN2XvcUYAMID1n0uTpMVXdijFIGLqamf0k6GmXzQ3UpVfSzrDS8bynQPdLLGI\nuxvSeQyS5cbAMWmj6MtbyYyhYMLNeIGeHc1Ble5JKk9XcBOCCFgzOOv31ocUMajLFqBtSfkqRVra\nFJiVtRF38mFRo9WKRHhb8sdoITC8hS2CTMQSsxPCAmNaVD2bJ/qFT0p1EZZq6BoZITEqjyAZmtZx\nXqR5qhQI4oxW96jPl+BN8zN6fFGwSg8Uc/RdDO4jXwwJaU3DhK6+dMf6pj/dlOYkkqJWJ5zvJtdI\nN/rpUYECSK50BXCzYV95c0h8TYbjLL07Bo0wAZsx9en9mAAJjFeW5J9b6bw8wSryqIlFuv/vii/8\n0NeNbQ3HukqaJ6WS8ig24kNpl9AaJTw1mevhFDSLwa3iuPULC+87SJhRoIKk7u5faUsPh5M+BdS3\nnwwNBqnyAL/eoOxdZGIbuQgqWGGzqOOHbG1kV1nNYc7Xp33yYYqiV7WseZtb4ifQcYtnIMXRuCPs\n0HNXHhr7bZxfYss+z0D8ocASvnpOL8w4nlKT2PiLsJ+jpVGuGS67p7kyScbgWATTr1CCJkP8hlGI\nMX4ceG7sdnxo3SvwA743LtMPEDxxTJV+J/+6w03IxGuA5NzYdhkU5Br4pGMfka9XTP8KCa/gkIs2\nw9HFq5FtvyOmvpOL4+vO90uK7rMdlqzeGa/PolqIB6YyPVJKLa4IIK9yih6/HfL4Dr+t/VMfsX6r\nwVNKcvxe0cS/qHRNS5g613kQ6UhUK6nbWfngwumJfxEVujPsHnfwLImvXV+Z0lpohVidsRwRstCl\nypmA///VlWrIIEfM9ztYImxJ+QCWHceJt6eh32pSrS1Y7CAJmjnpYkmyNQzNY63+27caRFAiePJe\ntSVGh1aHXEvlFIm5wia01tXhKIajPWowqppLHpWsZQkS1rJJUM4r0e11wGleAGGxpzLFv++3rRZV\n2E7P0LyqAMCVXwuJgbDCIUjKBeXleHsoXTjsTJ0RcfA16W2S7LwZUHCmJVq4hjScokm5x4LP6eKu\nnW7YbxZKQNnAIWffjZAbiPXmq2NpSzKlWV7VBEHvhB3WX+EGeM3dY6Fg0rL393oyDKouyjUWwtJK\nKkxwPWhTHPfGtMQHZyUM25PNCS9dRLKFvj+8Yuv+Cjbmf1HTxuUHNkIppVMhe3pp/EoYQdCKYkf4\nNmIqgPEpc1Xw53xrv3c2+5Qe2RPVMCBF8XCVGS08pfg+iaC35dIcxw6Arwcub7q1AJUHYWWH3e17\n++/sVHV8krkistFmP10E1UX/+MJ9cPXKZtgTdfX1nP1wgv2fZiV86BE76jaU7foSkNjoqQztHEvH\nvnjg5wHfIOBGVzLQvSsux2gimvtklrdrQeNtEAOAQpNS+C53UQWER5i7GMN1FpWJmOMX0AnM0fdP\nN+AUFHdOIyVfThnj/V74mNf8KRQZT8nQUqmy3LgdGQ7uPX4esG3SBEeLh2JSQd7DG8Rzy7bzFHcT\nR/lPn6HC2RR7J+MiEZbxOgXfw5CazrPTtOwGqDjFroba3fEyK6BRmL6ltjB2nnNbZ3QMS84Tngu0\nztlVsUNRQ0vVqF0YHm5Xzu/LFsbmB7GIOauNfKOdAPUZ9+FyQsOahJKfbgvle/vzDZKF7dJBesQR\n7G6ng9CIXGpMPYE0Je+/agXWFSxCKueeO+bxz3ykBrwSkZqafIocSh2im4U+LUrsdQ6Qg5KHNbvA\n+2ko1mWue4ZHKFv3GFIz6qy8sSdD4o1YWaRzp6QR6CuG/L0GNdQmSRM22JvOQ9ORJ8zEvxHKtsnC\nDDxX0UtcYsOlNPodlxY2wv52fihmfKKbhbhMpFY9wB8xvbiq2ZD4NKhflfFlzzNjsaAJtm07xKlJ\nvemry435VhaDY+TdxjrGnAKY8dtM50Zuw5GkpQQl8/L7DdmvUu0b4+ozCk3HZICokDOSzb1zTgvU\ngwko9mlZjy6Ro+IL6CNR27Huwainy4TT/R0u8/+5Fv179JNlvHyGxYXUa5rJRKrKic7H2nf4dykH\npcfDPpPIdH1kEIrpLaMjMoIsf9ypnvIpIO6RdGv6+Q6txwVGizW36oyiNd3BGZXe5F2CH4ImOqdT\nzMQ3d6iYRlIvqU9Kw5Ul/e++X+NLUudXHoAMRCPNbvPhB7hOYnKeR40UYNCDjm3KNgvMxzKh4Dd3\neQKaZuo7/YToyzwW/jjo35H8jGygVz0cA4hssv3j0DESJpsjI4uINFEqYK45Jn4fRPDMBxpU0V6Y\niAEQF54vjRcFgtShdk019k5MuVKNoQ+6ioiLfV0VtqEfVItvGAa9IlriFbDStqq4/rmdvZSArMUk\n+uF0EFdygH6DTJhAGoF6uE3zm+O7VytcdokHJmfnvl+LCSqwm2E9nVmqp/LTVl3GOKTP5PHZPyHE\nKCi06jAtv4vqhcRfdpwIt5LhZiXTuDrW/LJOqRdZXN5Lf4RO5T2gjYjgq+1ujG4JBq8ayr4Jhmky\nRSYp9fjRtfWn9lJAN8k+AdmkvXs8jy7wF2739kvWDAN/un1R/jxWygm4VjmCETmc3tgWZTBsyj3h\ndS7ip9ZGkO9ob6spwsAgTdxMfvK1vrx+UtwMbTZXoYLsDRtOHOpZtSlwqzdwlfTfP8wqu2owh4NY\nIMFNw2uV7x8Z19AnwHVSVg/+LRFyuUaDGsY0Tx2w+AWOhecrWJh18NUOCcw6WYG+/zLfHMsOy0Jw\nzbwdo+ynwtdG7mf4UVXSsr8vvwXKUGLzH/u7HLX6ri89GzLPTloHlsDEKlwnHWE+ElKuvbcbSNLz\n7MAhzh77MOCAOzn1JWSviNo9oDwCiru+wmYkeVGBLPncm+tbZi33xvyqZBmfdAiF26M8iEdZ0fC2\n9yNPdv8S/uO19rku7PiiqZvBEsudotq/zr7KC4V4r4Be4Fi1bhMPs17pJKEbnnZRV95jnZZBbWVl\nB8dCXMdwhms4DwWuimrqylqqF0BkHLvolrJ1PF4O/vId65g+6REAfD0mWExq5NMxA6QraCswyXBM\njO5ogsRfcuZw4y/Uft/kFMIM83hr6URIolvB7wRczzYNd/L/rUCnaBE2JIX+ZGd/Agmvy6lyaeSg\nQDDJ+ud46UMBCh7q2VG6ShlCYR4MyG+vuI9eUoHQ6OXuK+5XogDKPl1ThMXtIbZR37r3hWwh1axd\nlmfN8x31WfLCjsSFuBJExJkMZ5INe4PrSVpnMhT/MPhDbvh3TfPx9q/rDwDpqNlXg/4wsen236QP\nfqYOepmKZ/R5cPOjQsQp1EdDmykoEBb5vKZC+wJ2Ni7GDDTyuIUczE5uoWPFaOeHshGDmqpAyi0C\nYF3y8L311F3BT0yRTvNn18HPzKtJTn/lava4O4X0UK9gmPS9IUpRzvG535glq+TPTBeNNmMmjpoF\ncK043+6zBszbg1lgYMvoV403GptiT72C7uIAvpG0g3jR8ktV8ITtR8Ho36g3WEjUWFxurrhR5I/3\nMa4Igyi43BjEzm7f6cmxIh3L6OaadG2DZ38XUSedfRuMRuwWT60QG0FmYXdeGFv4215blbNsymcm\nk2mIDQbGDk/Qybmsoc7LPxjQV4G98NugY3JbxzfgqetsT99VhDmj0GBIG+LC1hlb++vcKjraa/C8\njN6NZRKehIkIZC4+vQS6gw27OP4PJrkOkXASle88FbbPhxozfa1WyIQrOq1xIqmLOHigv/faefeW\nAxTVyv8ScMVWcpI+jLJLLy4a1Ch7/HJ/igiVmCHlJm7ckJMbgtBVztLXQmXnjJTL6Pynsx6MKv0l\n8BVbVKIE16HLCsUqMPkgg0arbqf7yDPlygpesUhx0cUmFWse8vcOA+1H06P+4dycC80KWTsmPS6B\n5EGvU3RjL2y74HpjqP3MRfZBswhULeDpxvyXTaudo8034t8jEmw2Rp5ffDKcalxJbexN0612mGqK\nXqkLlz70YN9vIddrjYU26o3OdmYoBfN5cTWD72Re4pVTTuUqJ1HEE8xye8F24YDscQOv/4SaVieW\n8xM1S9bv0ifD1RYJymN5BCskUXl/bB/maR9C0MzQ47TZprWfZ8Zdhg9whQ54UgBUNuESTH+6DGs2\nACGSy1Dns4Y1955iy1Q8actfsbkIxYi2/oNqHZ02D2Xvwg3tHecFHzolEI6SlfAbGebSE8zOPlnO\nDk5WFDm7R7Ya9Wzde1ycw2/dEPIiNXKlzF14E2Q5XodVnrcpMwAWMhgnnuHIE49vs6jmYNq3GQis\nlhQUwP/dNeK3tPco+bLYIdxZJ7pWhl6d05lMr3MGDeem4/Cpl2QjnO3aBmxJ8J0XA9RR8gUjA23l\n3vpbX7HbQi51qCNjyhGK1Tmn2en0/fGcEOGhZyyCvJH4Qo6zB9uGykWijrxVWG4RmvxqKqqag0FJ\nDlk12cU1XziDHfGXtE4VhXARzXiF6esJwhhcSD4ZrgY1ji1RUxpWB+b4TuzJKPDpWO79abKalORo\nC/stTdrUrz/piO2okmJ8sOj74MQPCPxN9rpJdhy2k4LrMMhDh1kaspAmkqlclPY1falbZE7cfe/0\nin7NtWeOPQrKTl/qhE1qao7k6Ua4ZeGWC5GHaS2ipHen6ikeqettySwzRKBmkdDQSHamPY/wDQo/\nVo5THKpvcnZFmnuRDI9gsWrl2HV8Cnu3cziisYvsdFyyjFJlLwQI080Hm7YI3tK2ujDpuxu37bkd\nVnshVjH6Lm3O9gsdW5jBFwOx23KmV5lftiKdYyRkiF2iMjSw3tLSSlHQ2n29KzYnL1G/26FjOuI6\nmThzBJljDQuqaE3P8+F0mWoEBHmZCjrTaPb/too5PFL5RvZtiGun/PNgZX/pUEuzDeQeX08IRmek\nEKmkvHTs/bc7f9diRmuKuZ0H6KhygPZAuIP+2JJ8Zcy94C0B3pNqkm7GypUhQXN7SZe4ND/q67LO\nmfiUWXZhCIigT7LLJt8OkggXTxYdk0ArF5AA/dHoUgKcvhfFXSnNFzcF4C42BPgt5D5lWQUDipZ3\nQ8715I9sCHyxQVihVdsS/jzu8jW7ZiT9fmouvloW+afVRWXnzp4xWrqsHwJes5dBP+OMnR5K9XyV\nwpOQXuAExmx/sSUECT2cwytphepaK9GB4+yxMNZU8XIqfaawkSCeupH1jiH5ztVfu01WsSVZL0Vt\nZ9G2/wCR77e+YWHiga0WAuSbN0Sm/kAOZTbRQ3Iqu2L6xEwsAt5OufgkCG3QWEA6ZFCgt/11FtNo\nWCg8dspVc7wjJGcaQh62kkHOHeKyQP/GPfc6zfn8ojkU6lx6BtJUzVc9+5iSeiziOxJVcg+XiNfm\nry1bTBPVqs9V7GfXZMNMeTPpqgwy/SDSL7PSaaGXTc51e2rpsZPCv4PWW+k/3SAK4kBHSFsXoFai\nlWnFbldiXTkPzBByW64STapLmZt/db23NfGWmSAgnfeLy077nTB6S5VN3QJaubOw+sUFq8QDZWhq\nJlxIh/AxMOu9CnXuhl5COX2kO9MnYp2ibQXZjYB2Uz8GzbRh3KOr6O9O6W3eiJS0HmB8DwT3eBwt\niH4rzeVRFdnU9sZW7iCshmVvJV+XW7oEo5D+mVIWBfKFAxW2CN0E7mi2blglmwl/uUoXwiZWTQHN\nkhag0uDa1dx9iDbItFz0ff9B2+bFpQ8AkwoXj77KoRfnZlVXLC+351BetTTY9QZUbC9jM5kBy01H\nTMWQkj5fvhJ9zuXsRqN/ZPhdJDq6JQuiEcgl4fc7vL6BcDmgAMISZNEBSA8QIcAwmMU9Z0K6SvzL\nNAwuXYfobpCOxANwrbOXWCIRHi0LUYEAp0zpK3AeyOedeZ68F9Dx0fhcv7R5k4sHHwUeJ8QWMJl4\nuqJXzDcHIn54qJtSVy2yQ36u4QGuUmRMJ1QDFwxXSrRk4ewO5n6ndJrxupnl+yw9N8jpv0rFyy8x\nv6tNb1KSNcA65G38Uk+f9pXDFVAm9yVMVmNARfZzNrQybf4G+K193zlQGV+SrzXvvGpmOAfRhgox\nHa0Gj16eO+vvj9fYyRY0sOv+3uwbC1pn85cfGt8zdhHAShA/eICI6mnWYE+luL8oTUPFjbA6JuTg\nfWgf6iE/NXQSL2DBUMw5RF9/G3yfPOT8oYWbJZqL/s2pDbLW9hNGYXFQpXD1iH7/dJeQ1tdJipcu\nXGlb3slj/kcLiggxed89F/4aDEvVs0e6Ln27lb0ihd7NmvZrkbjT7vY8qISWtBVA7tNKlVV00HvZ\n0qvK87ftjk92FJK4fSekoReIxDjO50jci6dwOEqmYM16fIkvpBIllveCmSgWyYQxJoOrTBhPJJtf\nXfZ6PPmEUUvXU2cz8AnKfLRCcN/Cf29cKf549Q98BDW9jyemH6WdntrxM71+Hhjv4S5TtU0U0g0V\n0+t2NEX2ofWopXzTd7xXyQWW+2FlEeHbIg6Yi7LuQwhxTEUHKro+BW4SDMa8Zmib3qrPzVE1roWa\nMlCU552UI7bRNUR67/3lL2I9V5OF2EUctqNmUS1uRRUduiEN98Ni5WnO9pj7dC/aEx5fYbprxuUP\ntYj6TxMUAK4EpYp2EU81lidmWfGE+PSltOYjZqwp0eX2VQG8gtQ5XLQ5VDL5EmdTdG94MAZ3KWl4\n71qGiCGftP1gc02JOeebdCLPs9RB01Qamz/7qRrtLZqfjEm7vFGnZjrPbvouq6aLrTrkSoQ9Rku9\nBq7sCRWpZJHwIQW3joU6vIKWqovqZrmuMZEMt50iADknpPAcVttuorkxIhrY8EMGTVLaeiKc6+aC\nw90fEP2IluyabL4KCB9IP5YRud8Vem80dhNNefrYqAytpEjcQQMbkigJA71KxdxCMLHjPZhIqf9P\n1FOlQfDEyWStjz45PhUvBsWGfNfY4e7RP7t/msJ7F3wQoa9QKpj9K/iurRXNZN2eKT6Hj7SGkUn0\nACtUn9Zun7Ua1be3Kb+uXxXfvj7+T0Uz3jlSydytD55UnuDAYq+K2gAwynXtc6841qezeIxadr37\nLq8AbB4IT5X/oDEUDdtuxJhziiuLroU27SrBYnAx3ZoKLS6XfVF7wXS4LTlEOGi4AzkJlFgbtjDN\n0n2EsteXDHoJpKSx1AqY+vi7VY3JpoxH1RemFZ4Rbxr3Xmzsdx4BaO8hsfUOAXD/iq2b3VP/iWhB\n8XRPiTNtsAKVeSMyRv+E/9K5cMsB+gFtd1En27yHSX5qBO9M1g4ncHw+EIhgU0Tg1aEZlnpBXn1f\n8KAdY+kh8PwqGgcbkRdJC3bttZ/g9xR3roFPxpAZ+boxGrp2jE40Fcr3X4g44jgrA4IRgiUDIWTX\nqR8lxjalxvMOV3ATBs+7cP/BSaFzc7AbNgflKhebuvoh9OVDpfPv5+tJj/Ucv9iEIo7eCoyA4QTT\noY1enrvni6ko5gsAxgyanuHdkjnMV9qdVIMntJDRkt0cWEfdAEj8z4tYB/hGCMz103rrnFkX+aid\n3cFFPfSGptu7BMWqfuRmrduQ2xdKKgZPaj+yLnReK/vEbKIkBYZl8MlESCeAWwf1nzu1G6V7xSXU\nFruXmDy+vFG1QwwK2CMJKGUq1PintY4siRuRBhjdR8bY/v9Dppoqiq0GbWCnEnoeZ0lgvS53Avh+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GcA9Zn6JSJxTUCwYs8aQ3SIm8x3etRqToWjYKTAbZmvRezqKjuhJ1htlHyPt+p\ngxFYba0DOIa5737BxwzgTL+BM/X75cddRAx9O1zRk7WcZscO4nKsuVed5vzVpY5fUeeam4wpEreH\ndf5fZo+i2TN8VR099r6xe3IuXjepLpUDSqgz1s6fjumUU49h8B5VogWCzI/Sng4e2ySs3DuudcTN\neTbO7F7hocbaR4Ja+OHzwSKcERs2tKt3SKOZaqCzh1C4cN7icnZeSfmDXVkJyB9mTWl/6wSahflp\neg4bS3CxHvVHBxc1wTPp6ZwEbCNJZ1GeG3MurB9i3JbnUDzmOFhwg7eOaFurXoGiv45RB8vQKvjc\ngyyFG8V0I0UxUmA9cFlbilM6mXKs0c7bvXdGnxv2DQpmqWwHJafqZ9Ub7GIRP2nIw0yClX3C5UaC\nyf/tjtAnY/dw/5LntI5BBunmuEC6fBhZSntF7uXrDWv1s+C859IbUO234tYG7dJFDQHZH29sVYfg\nQYZDwlOgb8VuP8Lpo6c88I1UFVYFMgCF3P5SQ+v1m63bfe3bay4HUTISeVJUy8JV8sfADq2wubcG\nuWcfUD5AShQOLmrpWHHJ7kOetd/o40exAcRpY6ruMZpAbw/XTk3w+IZeYAjXvoV4HsxbneA/j/6v\nRCzoW5P3UuUoaB5PgGjjGV5hyDlRE22MnFsaD1Edp4Aaazf6x/abJR+gEuiOjIkZdFyslNkczRoD\nu7By43V/wCySOAnWyFDHOhN+Rk2yxZXouQu7q4FFldEH1iFrGHvxaAEezrQSskVgSBq5s+L59ioU\neO9CS8jae071lEKSz2D/g93/OL82GyJlZWj+PeSbqzhShQ+oX05Il2Hif0Nxbu2fUZVIMzIa9VDD\nf0JX96UWWVTDr3evRvYoh7RwhDS82OKImfwBmSzxFjawoemFpUn6yy4AdrgWom6pB82BOMrWyxCm\nr0baPyGumEcnivasXzu3Ghg7l4NtwjlcTuSrDJyiIIqWlD01qFIT/NSe8XGEUU3cnSBqQfMnb1rY\ni9O0ljhYVL8fURPadXIpnmspDZRBbO/9U5PDuTLIDUARR58h3mS92o8oG+2mYSEHMk9Yt23OoVZN\naP/TqOTjA3bB1PM7YulgzasFE+gl9SAFP7u9cTy07ik7Z6RqLfrweuEgZzZGPgnx+HDSN6clM4mE\nVHYMRJf5jlERFhrV8NNEHb+dJ1cy1o+50SKlrf2bfrsA1sMfqwFFA7WTEXfXopqTuOy2pS6YuTzn\nLtt8mp+m9VBSNQNLGSuPeVQKDL2c/GFdlc6tWG5msBw+rNDavwUIHfgdxQT3krhLdr0g/Xg3vX10\nmVcpqzA8cPWZU/PuRqdqDxxY+pCqDWMuX9X7UVKrPye75k4QcLary7mM+LoUhbsrfeeVgHdXbQQM\nzMhNtPA4SoBi7w0scbWfeGmkJixU8Sj4L6lA3ZvMrp/M8AR+++6EBCX9ttW8OQssFTRvoTnGA4Jn\n2kCJwehXlV5jwMSToYsyFFZIfrJxAUbo/+5sJXPMGPJIZRxRvhgucH3WnPrzojvDrhoDhR9WTn/D\nUIlyqa4FG7wIMST9OtD7LQ2xc2zji5zZN9DmxSdSMDQA/03HnR0gcY5xRBuJZ1lVW93DRflHAlIE\ndxPAtrUw4T1wgmfkkOnNCKxOsSAufvMYEchVBCXPVSTCIUgCl1WDz1FztJXRkZhd7VubxRZycQbb\n7F0xSiDk4EP7d4d1bLSz4fXRdkVa7inKtRAzuHfrKZes8NViU4Hb0i39UaHG/0rHCiWuEqEaemNZ\nta6O+8TeqDy5mRWmtS04oiQBIqj/a+YJjajeqKkJo5PwXbtHvSQh8grTm2jifLLDtyc7quNULvHe\ncOm9lfFtaaA9EHzxLtTm2U+5jwj6VdaXu/Ui+MVFI0xsQHgjT2wK5sk2yH071CVmBEItMF1tRgQd\nQIH/aNQjpXW0VHg7b+/8rumUFrN+pmkyUxhN2563muCP4KBJd0JQrKwU7s1O3br5fHuueVJAe9LR\nyXRESLNfzc+gr9SgamtzGojIrCBDOUdjjM6J49tE5jD0h77qR7N0SyxngO1MjZbfnYlh0TiZkDrO\nSn6LQCdtHe8jRfHGsS0T3MouZqBxtTrH1h/5Wg9xfQiQNzbjFdKkT5KfBmXj5IMkhLC+nYB2DwNu\nSJ3tFGNeOhrevRvFD3kUC7fsFE/ZwDgMmeDRMbfPY/Lb4XcSd2iIZBORBSlcLw+e83D2PnE6mkza\nnmnmKneUB+XbLJ5SGoG2x3n3eYD1iqpgIRRjPc9+6cuqbbkDWi4/eLtllVND026fbWEIF7PSYUK0\nwh1664zeBZIErMhQYj2uSBUZUWLIb2ys6q64oBSI5R7dLu3h3FuVojFnfAKueZRqbC9twker0itL\nIMphRzQ97vqXPOpQwskpiS+j4989IJOhDe4UTwtvUFVPhujGAfnowG3xIolbZ07V4VTbTzi61amj\n29GzddvermmeN/WW4di+c798HQaVMAPlLpjdy5BwGUk0SINd/oPNbjC3LeDtSSBdv9jld6nDeIjT\nNOVG8bBSqDP+0SDTjI0VlDlLKXh3KmZKpG+OA/z3ssNWrlyCFOgq6ZD/BUQCb3CLl7yKAVDswePh\nnK5UpUiGqm79YFthbWwOedumd7lJPMBxNYnJmAmZtSqcx38lGLipvw3ZMIEBliw4TlSRjPOodnCj\n5uztSEunBm5DjF2YJrzC/eZ7ea8lkj2HjtFZOrVG1eLYgh9Xi2PTJn3eCiZZBLMyEIGbpmrAHEEt\nDir1mN23gE9E3gGAm5AIQd0X/ZM5UBNPXpYcT4QMDGFeR8CC502+5jQ68swFIiwkynNbXW7v85kP\ngNi6PG3pHfS7G8j5+v0eyr4z87SXr+0wQ7+YrKvAjVHMKwTGds7JZSrwY/xbyS41jfuL4BK0XGi4\nGKhXRrAV6L4csIatF/43SQRMQAYQTLkSdDlWFrYmimVcttsF3Nb/V6BRPKOMZf/AIRfl2g25CdOh\n8t4wi8f2wZ/6vvyVQ3JjUs1GtUYeFEY2jWTfc1nfqrw6YJmSZExzhFIq5LVEZ9hcIQ/mWBgf4VfF\nldlM3cF86EoYz2hdMw/bPSu8pHqYAOWsZvsPVeLvR5bf+ugQYrAbCzBTFgM4SHoJsfINe6+0nnZW\nfkR1pXXII24Nn1y/HuBasCbvkzcHQwFyLWOi1PcOxspjoOrteHd+nv1PwUwED5QpalSFP5gx0j/F\nP6OQXBmrcu8HNETcC5BNbjUUgxVH8NmEx0vYKQka2u9RIWNOY86IY1UCKu4wT5U1nRyTpAy96rY1\nCUY2eeSu15cl3mFEsc9cR2SaZp7oGFiGkOeASbDfact9JWvN8TRyKi8cuY8jnRLtMh8w6wkHUW+F\noAxhkhQG48kdBvp3WBM4eJC/FhAoYDpTS3VrpOPFn7cHPRte76xha7ph35Pmy2bw6sY+BQ99Yk6h\n9vmke0+Iyb0+XXIHT2rKEiFSiu8dRJ6l+AqhZidZgZkJhwWP6y3ecQwmJVAhV+qEd0wPaFwMQoVI\nrzJC7r4gIi5KpEF26KGVAz/C0/Cj9x5E11XzeRsFpyYKNmgKzN2jhUC5+yg2/QIQ5A8h7Kg4dieQ\ntCofAS5iA+FaHtsY/jn5rX+UwExiVSxZRm7UjJbNW83QQwfFcfsW8O/bvA5lU1tk58Ii8KbxIvek\naLGlNnWFN8WThhNIHLSDeHRq2zxLQ8tG40cLPkNsyz+rMRzi/zjKmRbDejskopG5i/lb499GmbXr\n2C4NU1qBCMI4HfUZ5Mr9joo7/9FzpKG/HWLSct91DJ1rOP/RoZv4rbb9zKm+zlwL76OYPF9yA5Ma\nZe0asLuYZRnc/l/2AeEAdQVhjZCwsrClN22r88vb16gNFKtjTExjrzsDtDjZ38VXUOkOveq4mhYn\n4vnLjumrZBCz7y+6ZCszoIOjULEXOLchdJYytt2ysJfcaHDBPBxcJn+WKQ7xUvPyzh5WgRMUdsim\nDuVT+D7JaCvgAT2j1VfqyHMGXgfq5ph5OLNiOevTUYgC1V5HA70U8xcLfS4RYJI6WJCHWC9Wbngz\nzNLDlUD69JGv7uThe26LzvY/ivOrbkXghyYbkN4VT4GLqOsWMCYEtyAxmvgWAqIhNSPw0NSJjE5x\nxO2zQm1FoNF5mu+nCWJdUPtx70u0a8e5jdN9GFlj0EYq8DNB1X0nZZoBnNM/W7TUMATH/6CXWzd0\n498UFlvIFo2HQrBaKisdbEQ1Qb007Rp6TCnkkwgEHAcKg6AJiU/DZLXeYF60Biwb6N4KrGT3PWbt\nf0Kmi1vBxjXBTZbQXGjHwCQ5D6b5cYFeRxyCBrMFOUv8qbAKJEjRmrVW2MuIwIBgNbqnWIRstX03\nI5zhAC0x0EWpvNz4BOglCPcHaYYzo76rjSDZh4aQlyQmEiCxXT06Jv2NYSW0tU39elbVs4GHgI4T\nym3nR1zd9r7mOP4orAjs574aT/9ikdzavVr1NoMgeyyPCkPAIT7IxIce9jz6PdNk6zDEySO/wwdI\nCOV0YVAH8zQKQZLiL4bx5xvT3KZbcAHR1SsaJeuBZ8Lga1pt/5pLF36+kIJ9mqMHR18nWmcyeBNL\ncJEQH1ntn5eN1jpnbbQWsPwozLdy48vcXxr7N+qr9eUL8XPBcUpq43UZWMr+XUhhbgimqWxbY/NV\nfuSLs0MZQYkqzSennveOAr5UkIRGGlsWXubl8MxTBCT+GUtanJRS9duOH1yU+l8Lh8/orNoh7Nrv\nc1FaI7GMH9dMRFNACBQILarMsF7GoiZaxVxfCgQZMv2meRqmfLlgJ8HupWxkyoCgnlZLndHInG9y\n7Hs7zUmIhAGYuwtq9HnuBcKJzUP6hi82F7qk88GLhmoWaGDy+9WlFirxxJj9q5kYRwok79jIwzx/\no0ZQQUUtE1ZYANeGBMwhPqW86Ltz+DOq0vA/z8rOS2GDPEfNq/zALAuz9Wgmfp2XmtwiMCk9wXRA\nn0NajGKBfnpxQhGvH6Kt6j6GX4ZePX92brl37hhv+v3goAezP8T05xCAO3ENq58hojoRpLskhm2q\neGZIZA7RMgLk1EOC4eXqf4gyTW/XzzZphuSs3NBT4PvNCbJweAzuRW2koJNRXexyhIMu/uOSuyNB\ndtKF3ndxgqvrzqFVmxk0eyVDB1YxZW9xE2fGTDOgCvXURap9QR8KZM4J9nrn1Ogzt7jBEfj704HZ\nVL8HU2WnafB+1NDxgugtg31MWoZs7+giC5VUC5hoa7dc9vsbU9FNT5fR5ozf3v3797tYGsmcH2Fg\nBi2aS/mM6JqJ4rSaK6oFh+5Wnqc9pEtpsucK/lxY7dtCcWQ0t8pHncn7E1jhJyb8SqUXGzUXbo1B\nCyT8jRoNNy23C2KPdfcFdjUmnbnp7AUtpwN62qySlv3Xz0U5EXU97y8tdFxE0cnjt153zSfb3OMS\nrDlVGh/Qwsi9CyoBK5YapXAeceF8PZ9xlL1yT8la2l+ZO8oZsBW/PIV7k8XBWXeWzjtyWjjkXogp\nC2Lm+SenlvnxblFP5MjHdLkLIhRChOx8UFJcwPVGKWVLLVGpIdZ8VNsih0z4E+8g28p1tUC4wMRa\nhTAxtupzWMdOflDIVg9KeDAMPXp9zX7ZJHykJWRxR6q+3Y9PVIaJ53118LYjbT5kA6t3dHjfr4ga\n6sqPWD3DDpfagbv0tUyujVlnxaXTUCPu3tzOIEoPC9sIuCYESsSkquOFkoWAnE+2GEkSzPxgGDM7\nvLjNRbflPpBjjD7xsDSf/E7LDMCtiopSM521w2KOc+kCS9QcRDIGhLkYCFnxICp2SqEvoFAjSe9o\nTYG41/kG1FuDm+R+VFxytSo6hKqkhqIt8dtb0dDsY30Mlci13Rcd+MS05Bkihxs+hx/MHusmBKOm\nMcXWSABJJeJzN1ID+bRm565QsBExStKd1TmzjAsdljAUPv24FISbs5iz1ruSFpaRugTX0vIHGAWb\nvG87IsgEaDzpNSnFPVlWWb3Ae1kcMx2LlRb7534qDRmszfq8fgmYIwZQrsLjY2WjdhrsiHAMwmVh\nj289MTKDn9SH2Aq8pcgbc797NRoZvcxtJ0hD0yHoPpWJI+YmG128Pp/E0A/GLhZCfd9dPwhXprJK\n60DQduAqe0JXJZUhh4ziuj+sYnoQjandEFhZGa0cLdl3CZ+Tgs9w3FiHQ9o+KK67QgGrOT/N71tk\nr5TsA7eIZWGwk01L8o9+qmH2JnRrG+zQEEzjEK1FAz664FHDeqTSGHOpHHw4lR5PELHyFxVBRkqN\neIzgX9sV68iuU8n0DfDKic996LdsiexJexW9WLfH3DXMO8cwO5Abb6S1T5kFK4Sksh0sDSt3Escf\nArHXyYGyjOtQJXSZW38Ldjmje3CpMA/HYzl5aXruIhqnzy0L9tnGrNHIPThnvpk1CVEQA+1eMusG\nMZIyNx1nyaZ+GHA+pkdcdP90dDpHKZwqsPZVHf3kKHY0u1jqeTGchDgTlz8mFXE0HTq3HbzfKnMG\nY4zbW2OP4nzYZWPS0pgl2IcLCrPAA85AAWVMa6Ceg7mYLxdrMm0Ln/tOgzauSvkKI/ViZs1ahKOr\n2WeG7lAVi52tQpol+rSeDks6zGvoP+ePTUgYap9zCWUfTadF9/i3UdFf69hTsDZmD0YQrT/fC0mx\nhKHChOT2KdWe5TIrnbOpJ+I84InHqS1QLscyRhBYy5vOsM+XA5bxcpDSjulcZsRMdY++KfgzvGiJ\najuh9zs3L3sLdv9tCsf+elYA+GbduF7WdmxEGpEa7iKfjeJY4zU4oazPjTzVIdR6JqOFhIhziKmO\nsjU2IhcGEuVu0ogfcgl05hvDseGWlLz5oVJU6yXQSmyr7O6l1MRqaqPyKLBIMLYpXcqhMq0/R/ab\ninKhZtKEP7YnWJMq1CH91hQFThZ4vwmO9zVI9fxlfHMUoKxTIwsTHDXoyw0FdD2hfdXNZxhe/f72\n4Wkgp2qTz90wVlz1lYM+jJvggFVY+7WEQaCoHUu05e+ljIcie5sErvk0ueTOFywdM7iGowcO7d7e\nuhLyo+BAtsxpcGkBGtqomxgkZlyY7RePmNKMBesg6ouC4tmKlrOycTjVGljWsaY4mPLSKGFs13Ra\nGSwSEX53xGzieC4mFPwvJxIcirobSwW4pdubhvbdMEosfL6boa8QnLBz/2mETCSFBiJbu+Nb46H6\niGuD2cLAIuwbx8am8NAyM698phBwoPVElhRwpmZeeVpwbWfVWoMWq2v7t1oHEBH/VMcZ6PpzTcc7\ncp/vmAcidEHGZDVDjL+fl/tIQXVdSMRpJJlPqb1wALZTuVkD97DejftYg+7qTx0/nIjJtDAUI54d\nyMgtysL/yZlNf4EHhXvLz1XncBT5XlN1DiUVSNYQZGCUhU8UzCVbMCS49jY6IBUDzOVJnAOuPF6/\nHMf2nZcr5x5WnkZyCN/cm6ZZIkgwOgZd5I20Tk8LL0w1+tVygB6/J77LT1Th22rHnaGEDZEbKKIi\nEEMBRJ2zsprpglgMScv3wLsEiREmKu8lKuIYiP+IeHEJJgQy36vrSzm4Q3dLPSDLjqR8/ZOKCn3d\npgDbg5/XGvIVsThfR0tXjQuUKdw81GrqUM0MuYXkRjtzLsy6rMbTxOhCGtoIvWbkZ3ssP3xj2RMg\nzfUoGSj0PZNY6l9lCwpnuIJ7cWGYs90MGL8HLMAfCPGIPUtm6GGY7nfeHS4KIjKA4RVAXWqx+SiW\nZxSdxmiYIP/Hvl51ndadC7pc60ttuS06NeYHXDOO0S3vRQ1rMaA1jakkTxF47o+Jzcza7CiNSktj\nEXb3DfuBJlztT3vvicAdnTOu20Gk9HYImFU+V1l/7aGLrH4/rSSwmdoczLdNzpbPA2hNeLWpRTPd\nnt4lF7BZRk3h4ZwjdtQp4S0xFB3VdV9jJvtgJicwK1dzB0H3zAbJTvRTzN46JGxdDXOLV9Plgmhc\n3lK7uzj1V8wDQnncaKGeiLzwyK94e45MybepGzrp3DoeHM8I4HgjPTcRt7qL0nPWX1LvcGwaMdJy\nk3Z7nH2hrilPTCD0VbiNxfG6Du0uTixzYusHNlfx8ghsn0AHQec+Qe4dYvyN/8+uAb9ZIGOJPbAa\nwK9XZk7oblrvouXXXFBfbzsjWrOWnX+GL7ohONrsy8kJjey1WHiulVvVwSLudcs4F3gwYa1QN2JZ\n8bRw60FZz56Ne6LkeKXCfZOh0FOiTm0cRwrzrWUMTrM7CIT/YXJuJsqr/0mw2ZZ7NBFqXHLsxihZ\neFB61egffeahE+lhoLQpiZs1e33waVVLxDfY/evj3FocdMGNoQMQK/nWPz2KxxQXBtQHVZOjNrdh\nsx7U/Wnia3HajdqoupouLpo60fgJXgzGUlw8Nw8xfqgoJVF9jI7VDkdebQRUTW8U7XSVXMXF1wF9\ncPiYqw99dhUqF/Dqn38W7ivfQ+4pRrdLESpuSJ3k1DQGXMaSrmVUTgdaC40qBl3HLDKLCCHFiyw5\nHaHsZvKQ4IwKZ9p8uvWQiNYgzB/dywmnnWdg01VvpSWfMPsaIXN+TZOjB3x7At3FLyCvqU0KDBcP\nNSLmiavag9CucAQ5X0a4CbO4zq2rHFvb84VRgV7X/igswCO86CPlH+OTjiXC+98PSbQyv3Yt7yjN\nwu0vs76r90T1nhqxFoi+c82OdInCNUEyQIyMJJH1ub9t6qBHzXXy1lf2qd+S+lqoceDEDqwwc46v\neT7zK9dsLyQ8OVg6qprjyOXF+KPyYj8pvCgXrWzL46iuWuIGmQGhIjY5ctoN0taZPkzYnBpexaSK\nplkhhI675tI07CXRNHAYJ9V4WU04ItWkJcraQMbPh9pQd9jVjpeb156ehydxPUL5aUTpP4UWbDiQ\n6v3XwS04kaMW4C1S73RsASKsDIGwDxpUWkE/Fx/xjGazT2O9XC2tF/HfFu09QnBwAEv3xgxCsSgG\nhVYJmi+uSU7Pi0yk1UAx9CIBJZfvXCOBSSeqfbZQznoPl6VUDETyAtFWk++1ikObWg/mxDHhHMMs\nxxa/A/VfI6lDgdQWlRsDVfzhDYEuoBMA0A4FWpgfr9hkcsI6UjGOSyN8vGGPWfSf1kjG+4Hzkofl\n620EcndQrjZ/dZvi8FeOcveao7y3JpYdSlF2FJQpUfvrBcdHMu5PHvrjgysK9rHHuKLSrkLBU8/s\nARpzA/e6gYZoH0HpWEYwD48tt16u8tRvblN/h5H7g1tmLXRp6u77LuzB8AsUtEPspLTA7AjTXJ6g\n5T/wROxlhGKoJZC9/+si0e86GYGpR+iim1BlYnv02qIx6mX482NtCSam6G+6VbYpVdyX3t2Lm0qC\nOSdh+hlPvlsHAciO3AbGMXHS2MJMV7JVX9IQvBu7D++EeTrzHGEBigjDN2R/GdKaq7QBpwQrhv9Y\nQB1SI+U6pyEG7T5xpAw/BOsMczH5JwLlaSrljxEgzk6CkjR5t1JlKntP1W2tc/QOTiNJdAfLDJ36\nJcEywJ4KCMoDcSrl8NTApf71iPxqy38aNuehOuG8CAcC7twSHMW+1PdIlTOX/JGw5ydU0MlRxFFM\nw5PBJ2kA+0TPwLjn//9Wc/Z6jMvVS8yJ1hSLH4w7pJFT5ZhBUQXfcZMRp171i3T3Aw08GkfoUZzr\nyIQ6aItW860T2VbybbseJ+5ksBUs++IuROqDkR7JXmMXdZYpF6dcioHHU7F3r8/PSCZehCbLX8eL\nzeS2cyP103uUmRO+7BIJydB88XMvw8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5BPlgv0Ysd+eSR+SctxdgsIGfUYDU11OM0zbr/\nWzLoM1Oq+kbqKRimCRPQavzTq28qw2vNV76NgLf+Mi4voQMXDED873/xvIVY9TQsjopYhTTJgQ7T\nDYAvw4caDJO2T69XIDBCS5MwBLxZp7dspfoN/4oGjaDljcUVf52RQHBD0be6K7+UgXh3e722sNlr\nGIWdCtUs2ieNFcswyUkhb+J/TQcA3Q/BQjg525rpirxX/935A7IqWEBSrSJUyQ6bR/6RI178+VoP\nb+nZ31dSV5cLusb3bgBEdqMgFpIZQ04+C2h3rT66h+w8lgB1i8lDhFJYj6Z914taI7u7XrL9hdWk\nnS+oZs+XLf2TEHM6XhtWY0UfGTB4gk81QcHMPBR7FSj3PPjs6NfrpN8PnEta5+m7Bw8yWJ8hEufG\n6GNBPRuCN+ST78w728pgI2Aj77qgmO4bfF2EIh3e6jnqiqqKZvpottUU+wOnw0FfbAyzdkZHKegD\ntYerAldliSEsyacASt5YCPbQ2tBOlTdWlpRKGK5jhAdSN6XMihXy+VfCBF+iu55vsDQpKODwBf/l\nB8ttqqB8/6nZfoXzhq/Pgq6dwlP2EvSsHywtVGlAv/1vlQl1lWqIB0YX39bQW0bL61gJtp7dIyJN\nGXTGXiLo5VjnKbEblEGRVajzzcIM29VWYOsxCrtzGGusMJRb1cdgRqy49yWsGih068zm2wuMn/fg\noAhj5GcjxA7ozuv/6so6Csemv4QKW0vWEsu5LBWrPlIP4vocr3NsGTixATur/amAbbTeFCIGYoaS\nSjoM44N3wDyqsx/UFjyLFnf9A99T+by/+5RHIeoNkEG8Ghax53GNSvtO42NXxbhJJmixJNswdKVg\nrefi1rMLQQIDBFMeXpZctKcGDYHnTa6qWsI2Xxz8s44DR6MMt1MsroC9xPrPDUdujxc4s4h6R6Tx\nb4avq0fk/TlXz4ay7Wcgeldi8emJ5XtM/1MLpbTI5e+rGvBBJZn2f3R4FN1XVaK1leID3H8+MPhr\n72Xl7ZxK1k34nugWgEF7KkgInRkOy08AUeTUF8rIEIXHpXm6PzsCJIgJgNh9PrfxDGoh9XFHzHPo\n95su+nlqpTVGpiCjjD6GZ+YE1OZPhae8S3cdoeM4FgcVXsF1NP7PIy5DJ/R9pQ27TJvx5PdeDcrq\n5P4jynMDt/WXG5SmHtNJV+WD0q1vQMIkdeSX5wzCHcBDiWVqjER96rpl2Qwbdpo/W367GH8KPvUf\nAitgUV8GOu8TN4BBXonsdv684d89itGwwRGrKuVoUZtt+y/SwlhSTwA72MH4a9QWBe/jZpuc5eW0\np5DSHEiITaA/lyEk08vTfYQe0gsbQTg2dvpUbshMmvAWeWd6RoxDkEVNp20ryoGQJ9utSaixLGtR\nyKaaO8q4EwLtIjey5YKY0a/3Qn7OLrNo1W8xkOTYeRhC5E+kCtLKeve2NtgVQaSMiYr6SuYyk4HA\nTVxnfpuozhoMblkqkkj+JtQkbwJuxCBzRB8cLs2Xxd+Aul/LIjAAr183pTtklyhzIwnfiMNLW444\nc0/9McUB7gL+/gks92ElnH8khm4fpLUp/DwCEFKDend6hDZ7X3Cp5Wo4svtWu/v3fw1kgz6M9bUW\nJ9A61uWMsoS2wRbMsgifchp/N9DMHA9++hvfdpxBqXGOIw0VmqNAmPKrG0X4JEIU/6SKZRNNOG5E\nY2uVsHIfAYgw/4n8mv2fF7gvKyUSoHTbURYbZcKmmVv4q64b2x9J8+IZx6XZmLLBU+XJ5NxJsW6A\nTg6MU88JjupiEyYLylToCFKqyik7AWoTVJC/p2Xrt0MiHG5QRpKPsfMkhjb7gBS2PrvNBP00ee6P\nVSElr/CEpazyvPPZIuF6u6ze/u8Zhj1w0aneXH+14KnaFc1B1k2gl84kK+7MadGPCJxFy0HNW2zL\nsCOV74lcGAUuSqkLylCXZiiGtsicrnSiyTRstEasEvEkx+V+kbd8R/wO9Y0EQ5a6o3IFIwJzO0sB\n6KJeYHUhNr65982JC6t9Hoxt6agDzUeijvPjWMRhTu2CK0iKcmGyXsVdYQgI1YfBnQIOTXJZzY0O\neNTS8hH5fIPuWrBg6F9lwL5FPZd9APt5Wkv5fo+RC47fWbhQBmxpdUXF6HLjzGuq8GBLkcfkzGC9\n/ArWqnKORSiu8GUHX6crwulCXqSvYjc9Hypjw7TPuTVvnZKSiPHGRAaREIspT1dEiZHFaDF0Z1mg\ndn2tK03yOJ169Ud0SUyzXsOmi+JRIMM35oolbfoV+uW7YomtxUzbnIzt963yB2eN/GuMQQYpXXxK\ni7tsbvfSJNE3WE6xrJIq6MV30YgsQdPl/2DyCy1oAu2HIdIBAHwXptE5U3SFKDIr0aP24ePPJFXZ\nrY5YWECy6t+ORaljfEW/OAWSt6EKEx9LBJSAHyZRXz2oMrV9qUImx4xa8doClkt/i4zWMwbCsT3X\nDLxxvqAK32Nc+7kxkOtjbAYSVU3E2fMUSQV8s9CrmI/UELunLGXFd6HE6q1HgjODgnM/ZQ1vJcMc\neYpleSccQNtFsdHo796N82J74xCsK7uXVn7Q+0I3tJ2WDwPZvuZizHh39LkRwQQmdVDc/J4OSoky\nDsVgjI0p+2PatJf8L9EPyFtQmQ0JApa5FD/MKz1u9czJavCX8cEDPvGAGAczTWw2uWYgANc5p4UF\nl2p584ecb9ssVvKqGcKk/YaN1QQ/43AG8ut8UtlQxmxQXpjZqNrY06Vr1tuRj6mEjzJ2ijDFBdCS\naSlPbp1cld9hYjIdXm+u36IheCLV4JAjyQlfENRN5ctVJQ65A34472DzYIEMWaOevpdz8LpwMDrb\nomcM9KS+IZcT2FP+FpPQGXx2tGz9IySsDsNw9FmyJjyPSCVhpX91n06Bm/TcIbWasCWgo8LCvra7\nV8A8lh1qYPYC0T6+PFPJbTz/SA/59IjS0EpwAz2Nh08OLhek4atEM2Q1fVVNml9qj3ecByeuj4vM\n2LIxdpGoWAiusFpbmhQKOwqw3GAtXMQj4isIg0+uLjC8TCGBK06j3P+QQH4sSzR+yRzn2vthMXfp\nHGb6shHBzxIUcUgEvXPlfRUKvuVCRqjv8YE1eQQ52QGrqgudZiRiaPKFJW75ddXYlOlBr5ZVMSNY\nBWGoulXjstXKWx+SJs7Bzm8Zm8MKSf44HLYgw6h5r1v8JFtiw2tMxNvce68O5qF5+arcIB/4Tm5X\nCNPdJv2DyMnAr0TnFgqM/vhYPt5dPqDtSajak7mXYNjaBRdhDkenWytBOccR8UOfInk06KmRCdYn\n/DU3FiBgJ+AKdlDf41m248j/KcteFR07COdXIkvQohKy8egbvc4sTpjgIaaETRQ7/l8WtgtIi0BL\nd0EVC1t3zDqWlEZYBBZsuXzC4ma7BvqOOTSe0qKePROklF6IUVpmiQWQkH5aTETOJ9XJgJKKFbJa\ncmUpaDWhISKweR5Xv9EZmeowJxVP90+N4JBDhfZZbdtK5hhYYeAb5qYznhkPD6kgi7mZJR+kxCOx\n4nQCYaSxKwdMdyNciGoev/CclCZ3k/Cb4NSfadqiJAkCSfCUnbRFG/vUC/wICZJki+/C8JunjzQk\nJ90d+klizyWMuzr+5bYf+vIHjCGHOxHArWLAWPkRf5WH3vlGZgTnVL3f/fMk832dHFj6UnGUj0wx\nGxP5gWFpwUro6Men/V8AYtf1y7nW64E7F7fOJBOWJ/DlPBSYJS3RCBnA5LaskopBso435CmmPC1P\ny+Tjs0FpULQ69Bf47RHXv+V9AXgTK12IdFwqZCX6euUungXT3WuvAIGzkz97OWRGaGqetAh1ecn6\n4yaKh3rC82y+tgJYpWt6mLdj9raleyQBJ1uFwdWVUnsf/+dfEC2sOn1IWMliGEpBZWCKlOEk3QQb\ncZMwetiYbzXTOBKfN9RZTF7aj9LkbqS/H3c+qQAYbplKQeCg3XHop49pc2+fwYD49dkguyPfUHZl\nFgbzOZeQW/j8lIvrs75f1kG2RXfrSipSYqvqGp8SjPDvHL3wd/NZ2mG0LHaIG0mg/ciih9+qn7Hw\nEXPYWhJFOswmiLgdoUyiK4YBKlVLhb6m9I2hU2K9HfpcK3JyHMzJbn2I5SJWQAE9+b0DjyUKAj6j\nMfHC+a52JEKkvAne05p02nnaGk/1MXvd5CCXk9OXdUma2uvP4SW0e0lOUtY1DfpF3AKGUjyRI87U\nRlguRxedaDyIv/Er+OyN11YZwEfvDi4MqE1o816W0+OeL8tPBCzytBVnWuhkc9wnijE18uqCfSb8\n8odutiu9uDFz8d+JXSjV7LSOu5QjouGbsmIfe+WEt+7vPkB2ULnV/sA3W37eHvat9uf/6lrXbEMB\nscgvH9gj7gfnVY66tGVIvLl2ICHvsPIYwO08FGz7lcER3h8no0g8nelO2qKdHYFkKmy+NhSzGziS\n3dAISETXF4/ezAjVj9/S1GdQwyuIqwttvsZ762j+iVf0dbRWt1NVCi3xGOH2vR7Jk8FnjbY6Di7S\nVQa2Jf/A74o4lpaemRlYMfwpkIApjX8D3se1h4buv3OnK1gOZjauVk5A2Yng5eq96IAK0ndd47PS\nXmvIy6nR5I1RRn1nIfdDkTr3Lng/f9q8etL17YXrxtM3l+lRFl+GNfYKjTcjAi+B+2JxcAtZfDxm\nW2lmBY0AWPm90geNxjKI/KGTVLHszKI/e5HOEUeXYQKcif0hMNpubhQvtSPhsCZESv1UmtIzfbq1\n9k58zlNq6rXzF8DP87ksk/vrtgHLm/4VTfbgjXg/xX/A0rePI2O1TUUZchLtgrkaYjiYR3AFi5Zc\nACktDnPXn3jFYyiRZaduSkoob/bZ/aLaWKGOvsPUi8wRYw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protect end_protected\n", "num_lines": 1194}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nSS96R7wwFQ/awBJYajmb1uyxVW7Dxe+Arw4icTEGgmn49jUuwRsWmvS+gH97qfjXRux0tm4UqqDx\ntyk4/LtkUg==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nA+Z7s4sYG1dC1S/OLd5onaqChDDoqDKxIH0wDyu0FbLuPuh2W2mXAUgA6ygUDyPxGR1xLs3AnLf5\n3U/y+fEPvjbByjgXYRdoaB1qwaS5zdnv6ZIRFF0LC1q8dbQM70j2RSMZ6Bs31wvj0c4OYXETbX2h\nDtNML4rTAuRM+iAVpLk=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\np880H0PUjXmUBTEI3c/dRMxRl/IL+XvlWrRVCBPlh6HVE/9bghIS/wvhgyOQ1mp4fyEUGZHgNQPX\n25j3cqsyfDCSGvVGO/rQ3RvIhdjhXBbmfxZXGx5UxofTc+/fp7JQTUPxhKk+Zmp3B6J8UpkkRaQ+\nTlbH9Glza9Jhze+cKRbGwVPrfS4Rk6pzkwHnm+iB+WGLJnSJVBVgXGfhp+ygbrBv+U3zrTXgsOb3\nxSJhSd/AWJ+PCYXQ27sJJr74LZYIQx/gg5QzMyTEoCqxw75cGP3bD2xXz+cFe0EdDkJH8sFvd1LG\n7SPcDQ9xmFnq3WPw2Ghv6DnJe4/yMXGiVRDxCw==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nej7XPZ5hWPkq70QwibQmqqDg1SWNzBrsMbYSFestfs+BR9J7xzmVMkCeifHuWqh/wSvpJXMW8pOX\n6HsD+kakwLfs8E+v/+QJqlLtBdlE3y4Pqmiw2GNPbakNzU8DMNQXOTe2AmJmoqO1VEHW3S//PRDJ\nqs4qvgIM1HXRfRRIgECiAHz7eGE358gw007G2YwbitOL3cveSqDocjOGV3jV5HepWYKXINH11Reh\nBMkGynjTuYTMJY/92mdl1ZV87kDCsW8+FHqKhOA1FfPvj1RPIfsKuqgUkZvW2pAYk5eBuA+vJEkN\nxVCniFgVwsrAdlKrWnw46FoutQ+m90CDu8Kygg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nLMe3TxzR1Zx/ByHI5/w6/SqhTVkyqBbjVaIILoDGOy4Y/RehV35vNFgESx+MOdmetaV1j08wlqer\nDz3Rfr2Gfq6hgHMLEHPCaIF/5SymT5AVpwhkmFaQdge1sI373fv8K78kRC8JGM9DNSFOClhGJDQC\nXB+yastK7IXkt+VYwM7nXa0xSHywkBIAeivPY/BwBX8XfbLzv9zV6rh2SAW84YIp2jb4kcYm1Mqj\nYgWPATpqkdqbBqii+7aziLQkRP/MSmF7cT5UKQiHxn/Ns1lKMenELV8RgHq6jdkdBs1uaoi1JQKQ\nfqmUv9kYnWWDKWW+rc0V9APlL62HYOLDnbo4+Q==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nq6xSi+pTFm18WzGq+65YbFhiK1j9sHarfxu6mSyjDniOO2/jW7gfvXXrv+B56wzSE9P0346jIlVL\n/B4h/Z+ac0SVqu+wV8pg+OJDyBvWhtnNYZI/7k1BSUWzzR6flVJw+lEcue42YZ9yoX/3JUlz26Zq\nBi2/4jMu3LmppUWsrAo=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nOQtIJXostrr6X7QDA+MBULvA7CIKk70kDF2hMqsQ2sI/8QR9LMuap/TXdjn0XLAZTkxLKNLqD11T\nxAlasu0+U1hOXgMBxoOPU/EUG1bM7wR1UF83Qhigm2Qm0c5xtp78LF89EgU/YOJtHjCcMSpExbax\nGFg3QnSgmE/7yqaeLbA8DKDWxW05qT8jxOwcDuZ3zIdkL3n1NxrWQjM3U5py6K5PTmC+vcoEptq+\n7ZI2ka+SP+NX5R9IadM4lpUB6CqAxroG6xIUBcSx5r2BQ2CrzH4EcZiQVNCUwYx8tyBREplKIsC0\no21e6uMpC5pDqqckCzSWGZns3l40rTQV8PP6hQ==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25328)\n`pragma protect data_block\nomU0F4cB12yO2ZdV+t8D/whbbDWmycZw/StDHYdtlxBQqHD2Rt979k5WQq+7+dcCL3+IPJmrHRVW\nGmVBB+3psg2CMKD8dWV8+f1duqdQ1ruc9IDTn3kyrMv8WzUZr2BsXVR7LoT/8ARttZYBzN9SlXOB\nIu5fROLcXGXIC69mZclXZ3kqw6gKbDdcIPTYaARyazI1N1JT6MpiPeX0B2e9dgibZS4NLoFf1C+8\n4lKKRF3P6Ms14sMsxNaM1rVifA4iQ/Ak5XeKnn27tB72RmlJm4ojRMRkD7cqreK6a2V7DXB0zAWw\nD7/HzKVzqh1lZF/69Z53r8BDyCI3oRPiIo9/2kpnZMcnV87uI6FNq1UsblfLwnFVkv2E1TroogPQ\noUVZd48nZKP6G3hipN1IkHU5wYHpG7S1px7d8HSx5vZKl3pFpv28aN5BxEuhvJV9FBghlpwG57HM\nQYhtJs3QjvuUXcTQo6mt6uaJkEmGMltqmMlwvreBEPDAzXivRCwBt4lZjduB8i1eYRSuMv0nI/Qx\noswjFa0lFt6divro4C8AxVAJIiIIEzOrht0zHz9Ss0+qCELQPEGk5lc3IDAHgjbCPWmObsbEidaS\nx7t0E/Jz7yoYsInuJGfETjIEklMYJJhVHJH1GgtFiwCDIXtjIG7Sv93vg8+dTBX2fVHjOswe3xhc\nlJcoB8yU+RvIb4FuwVwKcNAPT/0Py8wp2Pis/gDA1dsSpGioBjVoz90+AOI7ltbVQYEYqMCTLtJ8\nFmzXBx2tt+iWxg+co9z8phmO8gLRzjKzWoLbGSZBBw7G+/VWR6G6lGo4ZvKAtDdFvu3H0Lk06rJW\nTeOr2wSeT/Kd+gQCC8o2Cf/8PyI3xP+tzcDP+L/jkEdaFrHo2Z7v+LzFwcprHqiZldZmlCwK78ks\nVjmAujF9tHZe3H3Y+tr78xko8hSvvPzSklNvrskK6bA6f7i7LNvPXEu3FV0hY4/9kDRar+ls9hff\nDSRygqt1uAtTYP/7REZfujc+wsurY+MbzHHxp6jq3EOwSgRyL2cHXx4Vmo62A7wgKyTWk5EdPIPd\nr6n847VMqI15sXBo8nYyLWEkzrNVtVQEvWpeA5oqeDEHaduoNXyXlyRSwDv0duY7A3m1BAFlglvR\n0N2sjqwWzKhYFj5Ns5HQQBtHh9Zw21QqT1laFBjSz7cAsrFrpDoB8SDQCefHnKEzSHYnfb3WRQQs\nxCjXR4TlJRnLnZMyHVfyYtH7USi2/l9V/Yrd/PO4+NmUgdIxGbToTlQIBx5gigJGs0XoaWvVskwf\nNXlK3UaoOJ85tDPYp9Ejz86GyMYerWLlf1u9Hn1BCIDeuOMqiHVvTkLMoY2uQf/g9NOChlcWM+hW\n5AZH9uc91mLwBKTrHi1k4EM6CVoDhS5i88eLGDj7WUosHcAYcjaiNhkZ97tZbVK3yKkVFEtdjoL7\nh4Bum8rQwYxHNx2gWytbEbl8qIT1k0uisTMGRDOmApn7rixESdulVbMR9qGrvrPLqY8EtDH7jJY1\nlS+kchhLcPKLemI+liKF7h5VSUNsc+PGwK4Poi/2EFa7XfIpHc8E6l0gZt+qwW+qsA4aH16FPrxe\nsPlGeRTRqQDdA2OwzUgpbcvKx2JTx5qswVjgMW5mHt2EnLjW6SHvLc/Vzy7fr/O3kiV3uy4dyWGO\noloO64jspiFBJnLbb6eaTNqyAvbpj+ZF/Bw+QrCdIb0EdsWj9GmUUmsmiWLI+Lz81KUCzEc4H+Hh\nGglDloivAeynD9N8HFp8OpgQFagNeWtfAonUqCDV3B+hsNXo+x3Nj49PDKdY5aesqlaahKr1fAHT\nfierHFNbvOT41MYGioKDQPLwon8ptmydyahnP5MmlDi3knIlULZ8de+mnbKISNCyvzua9eAc994K\n6B4Kj8/swf/hAOZxTJ+HqtpK/DgmCA9FiU3JYIsSB3rhufuLP+mFayZ1tK7d2t3i+FZt7TbMxR3w\nuZgEVxQBf6VU4vQ+r6EHuytjSggM/20/7CtQ6JVqeRD65+i4n1E7b/yeCapiKyLEHcF5+TolHg4N\n2IN8M3DjZGThrN/W4aFXsyj4YqaVr87z3w3GM8FGp7rDv5JqVehoF+ATrA0OcYRvBVPsgnnvlPOg\nWuMIIahHuKGHwW50zPwsNaUod1E2fk8gLhkqMqiE3SQU2y1T3hmK6MZXN9GSwJ5IIw5eyyO1FWGr\nbcgG3rsONmih7ecMwUp42jLQ5vSszqiQ+yHXepZzC0e2VcYZhWWEGgQ2qAP/mX+y+xDfZ5e//Dp9\n1vw1SwFlk48f3CJcsRXrWfDocPNxPWQEcFtYDHSPNwEAWpRDWrd1jQdLRZ7riiKEwygrvCTBTy66\nWshkAAe+V5my9AeXa0Ml2QTFJnaGjonlt4LTbDpP6lrDNO48TxYvwTeeqfPcLaHr0uKQt7YHP6Lz\niQFo8+yjuc0zEfQzoaETRrimF1qol1PWK3Qpfih9XrskpouGoT/zEL9vl3TEyQopv4PUZPj0Ynk5\ngLrEEhd5zkdYa0GWHcoa4Fot3qrp3UwIaXp3J0srL6FzrCXbDBf2Mo5NN+P8lk095AJm7GbHDjvE\ncDphpGwBKdvmbBEGbh6fHIOHTAhf+Vc8cPPX6BHmHbNOHZD0JlWZppGdjhHNpBNPnIBYS3tfqeR0\nfpgTvVPYXHmM322F7ZoQ/fwObdQAoj+tk3q0RroBJxQWakMIeQLVoja31p0u56OMldxuQgfF/7kr\npJIVirx6SAQcDVwcFSqf13qBuM+0Ol/D3mNr7ZjwWtpprSUZlH21ailV+zw2WyvthkiTp8YWVQBy\n1q09ZacNze6Y1ElACgh58iPN4woxeuIgISJzdoXdZHKr2rmaCQ72e80pFTsQDzTlRLDVRkpqAnDC\nxN+Mwpe+Fkm7f7w6HD9kr73bageDnyHcFZXpA468LRFJPWYg6wq9iFZ4TJAxrhk7MUFsxJtUscnr\nxLex9FDXv5JNgmR/UE/CD/ih5AN+x6gWb6/W3lszhJtU5l4b4IoAIBzFNDGa48+PO6Tl/fTG2S7N\nNWLwVUe5S3/022dgOuBphepqPGBaEk9aWfzhttADsYbd+EEH0DLjYEUNdOy0L0wxxD+dTHWxJZSV\n0ChMWF8mHSAFDH5fO+Hy1cRtVcPIRrjGMzyyvJjDaKoXzOfyN4HKL0d2Zjm/gFo8lez/ydTkt/CS\nxYar4AEGp/BN7QDDP5IH+BMU2l+zrhxqwQPo4bLd65LBxuQDXhUginwDEo82bBweomEKB5ujxPvH\nkuKtvrIWHrfWIsK10kpV2kY1erMU26KgDhIsF6eqON5qRijRBS4IWa4trUlIKxFe0tR1G+0lTAnA\n2b2zENNs3Owv+ZV3WgEeJpcYOOwbsG7qq3snQYse5j0ltcLyBO+dYgzePpcE55rg3YWCCn4hjKVN\n0vSNNutZw9QqsPBhK0qUZEvot0e3Awajv6HKZPq73c6PpUOaaFCTRl7V70cOsdlrUwteXMQJV3F3\n1Qszx9GyIwFkBAfl5tn7jsQzd2tUlf+3rxISOSF4by79j8FsMlkJW+++qk29OrwkSW/XexL+uk5x\nDWSc2fgm68pygKu/3KtuFKMEnPktko2ej3qtKmVvRPolck9fuCxtkXDMY/lRA/cMCbVJdOST8PNH\nltx8N3OjAHjF7qztXIGEbTgETs6qdtIS8Aaec2vMw8sZrpkkrCd83yeYgg89AlK1PMMWYpKw37mq\nTeNpJu+HCa81ry2c3bCvCvpF74Sll6oEliNJLH1QXvcQWLSiz6bAPjPvZNysBOkqwipQO7FIFujc\nH1i9gsKzAISZqDQ4COwcFkxKsZqQ+3+9LWF/SyoBGXGllUl7fn6Y1xtEzEcb3vTq2Sqz32OVeKu+\nLWl+IaE2DFDUpnM3NlaxYilLHTm/OtF29z+8txLIi56qb1wlsAsobeLHB8KpgUKsEzE/Edpzr+k4\nykpmm8XtbKx+rz1FpVqtx7C8k4J7ebUClTt9AaE+jJujIyeR6IIX9uzQBNiB2+o2Tb4XsG9P9SMb\nGbauD0yjImseltwlb22KCPcxWEUe2/7VOir1DkE9/wbtk6Q8eF02TJxwTZv/epiH8p09Zns7H33/\ngS6CyE0neXPK839SOHGZCftWF36xqrP1yS17/OA6PI3s/CTLfTs7YTx2codFR4imZz29y71VIoEB\nxtUhCuqGobdRNa2lmU42q3mPHQLOU1UisLPDeDI8qxbUi5FfabTKeFW8+xirZfgTs10x10q7KGnp\nbd0QGVaqot1rOHQ0HlG1SiSDeBp+s8HaYAdx9PmjO4bwDtiQdZ0aMJafmmYAYDSiRxKXnWvwtwJv\nkDDIMdqVSgH9shOr2WCOVuD4hebJ4kxzvxLQQYK3OsKY1CUdS6LMg1EBJ5fzEPsGHi2w0Eh2srkc\nkFRoCpIPylVJ01RZzkM7BHiJ7SsmbDucJMBZCFb8KFsmi6QZ4vhiXdTczreE7AXWtxd2/bUiG4vk\n+rP8o411sER8+1SpV3MujyYSJIwyGRA97P3vw8pDfsF+Ktr4FQ1M5S/UvCCDYU1c1fwEXhRTig9x\n8kRj/i/4u19Y7f8pW+4TRIfXSmqpxQLvlViUn89CBFT6NLiVqBHxzowlhoWrhi5zpYXxw5SRXBPZ\nsPxr44yLN8Onh2QMGqi/H00xNhG5pB31BEfTeuisYQiVZsCmsDMNFCZSUIZJ/+qQK5aL6ASPafTH\n35NsiMMmEtBVPcun5MPDeCi/5Yak2R3SSylLb62ucpJCFEiNSW9XXihs4lvRiD0m9Q35QHQaqlWN\na8FAdZpgxcb9I9bO7md4qPV/TFLA9Fbfw/ttXdf1LSjH9WiYpKiNsii9ttBH1On7jV9IE5ZlK9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G9UB4lpGFa3EvQQylVj7gEIapdNZX+/KvWDE1Uw+Mx1ch19lMWPerej3V2JsR60z8FZDuZBI\nrMa1yIuu3scJW/W9+zxr1+L71th+wD0N0930H0FW77WXKD73hpu0itMeJl1kTLX0C+4du/oXwiPP\nkKFMnSlhnmADk5Nzs4kXX56QHHCbRnr6eMuvZblXK0EZHGXSb4pQePS8267+j8iT4e78/dD60NSn\n3kcUWmiDaD6B8DhgaHuHl3jgJoT7tgyerSxV1v1ywnD+ooBqWrUAsYnJXP35pM9lvw9shjKGAAX7\njCObOS8VJZci9eTJcmygBtQacBP0AzSh8d0ZMgtsEerarYOHl0VaqrURAHTNs1zfXZ6atogVW572\naPtBaqUaUJB4BnKzRoP+YM/+HbN+k5jn6HFPg/wFHeOOsIPE4dpfWM76Fj9OndYwBoJrRfjLOqsu\n4QbnGR3BRAD5bq9p9CIqMna7zaj6r1Kh8y3bz0JLMChWeZWjoOnjrSOb3n0S0OcprlGZwIkSPhD9\n5e7JOYw8xSO/acOGMOr7XhVwxsvj5N71yDY9oIIxCmp2i5mKFvjdFKT7b3ivsMqpU6ooUNL1cB3B\nct1l8a3kFj0xj3Vjz0ipLbKBkR/JC+iOtZk5LGHDKd1jaSTRl9nSuO+bV9kLdDxwvYHAm3PP+PD+\nzXW0fPnQVICDYqkZG1xto1it9QOrHjy2vBNh/0ETekywdX5BIejkFzloAAm2ddh6NFnynQ81RPOp\nB6Ei5sZhxqlniMTJQNFN+PNXyW2lrwNTLew+TNDyj9rIZ6ETik2SHQpVEwsfSVmzfDCWqm0kta9i\nAjvtzWWnW+IsuGEsEL2hoy4He54jqi2mtn5jgFPt8o/zfixB4kuNpqBIoSoWJqkPuB6IQ/KJWlFC\nszg1J5hey/xx856i3HzxFJd9mVXALJY1cvYVCa3JSMQEP0sUcICrI0GoEYQ7pi3w1mAa8bB78jMD\nrfvLju0deZS0V3tBedhCRm9yt9XbJCp1F+62+qLtP8hSRUC/gOs9rvVULoMDmyAEgrf1nsbcBaRM\nQX/2dEMQzcBUd2mMjdpR0nCeJ5oxvFymHSOvlBYVhLq4CaROMreoChqIuejDpaErVFOfvu3lq30l\ngiYyAdBlGI+/GenmbO8fLK2EtGigHy8pIzuFQvaj350cfHLlcO2jHrl6UbUnMLdM/S+aBXd2Dg2E\nFKbI8PeZwIJrbP6987aJSwhWKLNgMNNjCkUqfYJ/NRB2eSOiC40TgfhufZuYh1fA7Q32tdQqW/Xy\nNv5slA2fH5SgHmwS9Uqxfc4jvp7SUOc7EToDWJKkVHzNtxfk+PpKRbG7gledErTqMBqWRm7rkwhC\n3jsX/qzzTT0uawrfLEtK5qRoYxdoZzMRcK6ix0rVWema9+AZIkOkf2eQ1XIts9qHSuNKuze2RXJt\n7XTiojoorg+kyigvlSv1D+o8cAQrd78YiWvhEj0QphJmFmC6jy6xpe/6eGwfy0a+fsjgc0ZCdt0o\nA4sV8eOhNsGrSsGhMLickahQrinsXh/8ILbGqvKtKAbNVNLyJk+6w9BTy8HoYPwRccXIahYFpgS0\n7pjDe1Gyor2dlKT72Rs9SvooqSu5tkPK3AFc6o8oQIzNtMx5dKNBHmDyeQntb/GTk8d4H6TAExAo\nsrSIFYwaxyXWQsgbStzgbi1/n6R3kvBFDAMD9ttwZ4hmPlj4sygAgzv6c6CfyuMZpH/keY20cVAJ\nOXijLo3hPgVD0p4n6FOUdu/JYgrTsHnOzGhUcEGws6R51FcuHxqXcBA57apz8QY31Jr8lbuhCmpj\nTNvGlI0SX6VE/NSoJli7V68oxvxAR58toqGrfJU+/YwnuIenC07xeN+mOIKyGO3P+4F7UuNDCPYH\nseoQxJua5/0RsZTGA9NHNAdpXJzze6l0n52PzQItK4epiSZiE7ZHGKz1YfRLvAFBrpIT1ArDhLFw\ndOB1iZgy9GNqwH8pNMvbfuz/+FeP1oM8/SIDdLSv0WDwM33gsrenitpREzjdByQjjFRtunJe2kyk\neQ4GhszWY0Dhm3qNNUlvlMc0xXvIiPl/w/QE8JJ6KgtMUdzTXgWd43HK+VjPyg1yJm9SC1+o6xlP\npEt6awJB3VCzxpu7jVf2OMsrQjiF4W728yfUJwPQUfr7VR2E97zmjsbiHbf1fo14acawqG5MHQW2\nZsMwfep7N5NAIX5rav2q5ZC3g9rfOUVkwnvp2F1HSNOWxKV+jJz7B6Xb5o+YhzoDd2Y3u9mZF/cD\n14Q3uTuV9Y/ufXtAhC372DYtV4oSeLNkdvW+eOTDr/k0eKWqnidKW9xIeLpCtmtUEhv+gSYNMZ4u\ndj1KJgp7/bMQMYReDRLQJIZTkcDnKvrEc8ObcYZ4GV1OwvpdWTtkiszhRjsUWD4YA3ir81byw1gt\nZKff6VWwZakXMdmcY0gcEhHqjdELSZFplYxqXNFX4LV5x+7eFjRz0S0IbvsVKlu5RD/Stma5/ZA9\nG5dOyFeuG5u5jQ1wu149LA4HvM0m0lg8BEG1MMOo9vjgOYEgfRz3sYRtSz2M+SnoWlt+o73somiM\nS8u+Sfiz3Nyg1GNSWlT3LLhfK8pxIEkDKkLPjRDkvjsBfkIr9jYYnK4PjvOHmKaPH0ZTSQzVm4M/\nvMz48765bXGQd4xL77svOl5rK8uyJoMmyQq76t/aXV1iCMNLgIiZDHa9eodbgsJTeLDB92bf3zgb\nkHDPhp/5Y96aH08BelfvO9ZsntgDvmOi0++IymB9PI2l3eMx8LjleptsWU81WDExuENmSPn5b9V7\nww0PkB4L+OrwEVDHPmgQvzOp/S5lY86506IzyZk+EFaoisJPL4Ix7TXgo7u2wHc8Kssp0X5YZFj+\ntUOk8kYsuNRrd81CR6V+ukNkM89t+W4aw/ajKDTT0LmUqRhMGQvh2hOqw9UksTCdMr6/WgIz5pbm\nKniZXfCh3cMZu2TysZd0Gmg/MbZ6ohsBnlsnrft6p/E88NNo66e9qomw1v7eVWGswqmbDwalyPv1\nxBVjkSxrxfkyLQB1YfibsLY/wqmdq7CHSlB0eY3D5meq6O7XDf7jcjnKVJ3lnx8bvmKf6aT8I1cj\nHtPVm31bdpptslWZUHTXnDl5VYP4NJJQN/JJQ+GcRra/Ik+SxQ4vqTeRuhOtQb3NjBm4FpDEKSSH\nj3/IaA/l3KdxVNAbLRenx7/pEnd94HpKkLGiH9J++D+WtogNWlV5Ran0qN9ZVxtMgYRQ2CfhS+M8\nOoVZJYYvVWBFHmhz0Mng5gkK7LODy7ij23SNkqmbfMzeniulSE1jAHHSIgqxdMSNQ4Q4AwN1m4YH\nQ/xsFz07AK9LzQIQDv7U9Wr+nglKxlsXV4hcMSdcPHy6cOcH1+LQihIVUm4XUhH+8jEFRcwVzbKI\nGfP3Qa4PE3o6CHTTLgjitYN9jl/G7Y4dTuIWbIu9jgPWY/Z9eP0EIIj0WKWsFBD24E/QTfUUgNxH\nGe1uU+XisJ+7XHwnFN1GVgqCja43OyD+CIWdiYhsTWjUgpJ5E0fxc+AHqzHFY2a9Xj1wfDPyxyoA\nW1S9e0KjBPXF8hTpLMATGsbXCltlAQxJlttlBFZKCCAsI7R5cW+xpMyW/mU7SgBUJ2lPHybFdvIS\n/kkKwhO/kHKUXCYtD5Fvgg33/UXIA8UcEHrhUraEik9Cv0YEmwcEdEM+b6CMPDjwUqHMLLWJvB/r\nYZOfvrPtNP97tOh+Gzilb3WkMDsLHUw1HwbErVEhj11lziLbaej7JqgEO9/M8AC27Al7FXaRqDYP\nCuxwoB43b8tGyEmDFLCCjC8Kk1ztEP/gVA+n8Q5l5sev/rTz30Zxgwc5ZZ1d227+TLCP21iPo4O/\n1ZwVEJ0/mri5mBLBOP3qpG1jjuxhpb6xsDRuvbXY/bu6nxERErD1bIVcywy+vBTa65irGR6PBNhZ\nRLtGiZQ9eVfYdXcOnzksALgbMY3RihTlYwNLoDhz/KfMFGTo/3Gah8gk4zf8cCFZO+jFWjQ7l6nV\nZaFpZHFkxLWZxdn+9jKXsFEObkKPKJ01RmnwsIrgcszIiDb5qUx41z0djy6IcBO0+CJ2IigVN/XL\nADeVMeG/d55n0yNPBJtXwU0HxKtT95amNObp/i3V/o7cGrc1TfIfD6ucXn6RtcPGYh6v6pTh0wsn\nmitC17c2iHIWWU/b1+kGcN6VSOkti/66NmUcNWTQHUiQ2I/pD8RWfbxqGNXn2QQhSwST+hAve3p9\n3CqIBPuTqPwBNNWr2jH6IeaRn3adw9H+MCX1QYAF7v/zF2gaYnQVDTduzTN25/V8vUg4lPbOQqG8\n2KCc8NqRPN+trTzRMrh0HIeK8q/+G6pncDXe3PngfyXmfFpCIJUF9RiAs4/J/Yu4ZUd7Nso57o+9\nIA6EVndlXVZlK6nkkZRzhAdYfso8SfpArimn/HYTgGUpfs35MOvKk7zmKqXAxPZkcurMVQ01YS8u\nONptVvI0ZpoDxl/FyLoSGTPo0BzKwwj4UnI6xVjdsT0V5swbEFntLW9IArikjcP7AbfVyOXSats6\nTNoO3qGEve+FXkt/onl8a41AgCWlL00twIoOs6AasHipMeQkOgS0ipUaGjDKcn5ceCWM6+jm2JdC\npbP+MOMtLYYdCyLcULAkhpPwRQIkGQeDcRnsPAjuZWfUHPBWkwkzIHYn2fDi84yh2FvppMqxrLWH\ntNcrGlgWvpHDCdojVWATJI60DjXrYDvJwXNW2kNUC6ZIBr917ItTlQ5surQtNdLCMVKXEWoQNU7q\n5vXU4Cj19Cb84ao5ZpC1dWAI/CNtZyV+9D8HsSf1oISFMRwY4cOAnTDekXrOj/Zj/1qLeXU0HPw/\nuyNcYPiG2qitycy1Df7+/FuFDukKiLkrUsbkdvhOeFQ/LOBWfbBPtNd3m+/57kevqzQpwSQ3q1JL\nAfhHcE29kLQb6ZkrFywzimdO1QUhQLrDxd2C7A+H+0ErTsLOBt8mTIf0bHXUMG8jo8SF3fH3dcW0\ni9VqjocNa8gvtiDGpX4ejz2/hkdEgc50Nsogn1Yop21X8oNvDFJ9Z+2S46IilYBArzBIMhPc7GK7\nTzaIknEGcVckL+lip1TqCZOkxBQdWju+T9/x2rLovnQJScWz/DRT3QKfMf117zA83RxVQrZxfQw4\n15AcEPVUkobhsGOyWd/uonrJ18Chkp6zj8VX8Ha5smr+QpVq3eLzlb9br/VOnrAnUSZ0bvPvjQl1\nI6+lK7EaYF1Lef2z/LfRBTYgqXAewf3nzpmM0wdzIBK4+WCChRBH25ieuAj6DhGU/4dNd5iYkNKw\n5UFjIH0w/7U/+ugyHgDp+nC6JDYtfubj0m0KJJ87RJMmQ1mTNarOu0urmlikkD7+HDMSgYyLEtuQ\nGaSH5vSHsJNe1baNRTA9VZqhlK0zAIBSMEOEhwUqnE1As8+bX9mBFw1Yisk7M/bpzK1mIF1ayLiJ\nGtRL+mvAF7ogzydkw6AZq49ZnkRye/Rc3FSP0qOsX0GAdCjMyaPoSZ919BBXkDatQplglrL5Ap7G\nC9SnQ+UEph9gWx619N+OqIaVd0Sy4GHMXVNXZoWzCGStmOBFx5wU/Whmf+CQQC00fC5T2zyRX0X3\n8TKMKhvJpwWVNtsQv13de3iiNlO1r33Rr6Rz90IILkiLnaaOlZn0gsuUdQQFv5nAq9ZklwQU7St0\nUuSwd+CMyM3cBpYc0HdW3qNwu+ekYlkNKdIFoJ3e0E7qqdNgrYC3Gf12pJiH4lzbRTPZeJzMtMiJ\nS/W+W2H7pW8uOJhZtvIHy/r6/12etJ58zmR/j3PTISTH+55NnYBSGQhXfLN/PrZxEkqeUV44ke+K\ntGWb4cvQD9qBtaL/2JvQzWdwPwTNnq/VOMDHujxwxkazRZQLoavtItyYdaNm1gt8xEzjW2jnxkHL\n7KbB5ZaBXIktxcKqBK64RnziU/bgmFdkLltLuHI55XJSKFd6m/eTU2FmwVMg2rvrgS5i4TwtpL/a\nrsSKWWQCHSIYhb9xTqrzYigYpHuKDjayBqK9+OuA2rTgDdKq9oaxyR/jXySiUxcDh6/az9/NMLQe\n+KGX2bvG3wWdxOs215xclv2w75gXDDOqmYINX+R6Roj/5aUgY1dVU4YCrTi6JGSdprum/c8R6r3K\nBuNzCsiwGCuC+B8q8n8awIiiACjqG/gTisr2FnyUMF19VU65vml2ClFxMEIgiDsG+7uVpVF7Ks5f\nybAZ75BxISPCu2Liw27/nEs4H4aIfBZFm9ffGbAJBal071TlBZhk4rtNqVmQHiEou4C/NvmxcFNm\nZdBkKqo+rmrY3o+/7PrhbZPAZmgUbjAtMHtVne+vge0EF0uj/h3Sq9/2W6bgen0xIv/fzQVSGlPd\n46ZekLfUr6UsLfTrPd3ZFy1yrg8VGInFaN11yTTkTPzcD5p6MzOwLm7UJp18wmNmjk/BlTQ1zvvg\n7e9NX6SRJyF7YdaKwCQYxTQKm5lvUiBxrCcChQJdg6/BG+zVTZT+8x5ShfbbzcXnrfZXMB1RKLuv\nQilDIlQD5VNRgP2K/nbYxsMDjoPRRuQduQ9AG2NyeDT3fGzcxnaUhF6cMSgXV18yfbNBKrl/ie0/\nH7CkmgeL55l3iV2HtsERAx5kEki5NSNovvtZ+jLzxOiuMFxGe2YRpHttIX0l9YscBYzcuESoumlj\nRp6KFFo224Mw8LZSYX0+QLN/W8SRrww56eKNDbbiVU8DBgXEWLXhS/1q/+SoMLbvnr00BDAfbScp\nMOlo9rgdLsOBwD90jQAAvWVk42DxTWfqs/2Q6sE5CHHDEeytdzchnA+2sHM1Ua5LyW8R735BypzF\nyS7tDnyBRxdi8fLOqvDT+LrkjyQsdeCPaZ5HyGpPW55Mmqg00U78uV99LQOwL3Lu+klhr205h/Vh\nyqRvrSBDsjXlBcERGNTb874qY4U2oIdRTqkR8JatCImB6tOG4z4OGkZnCaMespRfx0xh1h/b8c4U\n0m3cjfx+GyjuXBXKNzK0L5f26aA4HLeOMwHuQtRxmhUth92jdHCtkyV5fzbr19dt3PdWn+DnghNw\nmvRsWnJq1pTlpo9aeDt3NDSHra0iEsRfxb3UD9AeHjI0+AkahdLHzNLPRihKpE4llriErZtBC09Y\n1pZq82vu7ZAyYxw9UowxtlJZJ+RcLopN9S34fJ9APRQ66/uuYuD68W+7tTiTNyZHoKkS7FY1Uu6W\nHFyanD61UeLyH9apnXw9DwRQisUpKCy3q21CqCEiWvQ5+C/vy5qC2N8WwBSqj61aW1yQyiYWkBXO\n4xQU+j7sgnBN81KG0kSJXHWcFk/h7X4X1tLr5Ggr890jmGDv7DA+VzdZ7Q3fTJofXmuTIgU1iE0B\neJdgyl1EXsPbo7hUVFVd2EgQRtj3vkHwSCjFVF0gMLaNVf9LcazqIvW4HFFI2tt8+9MFEyenBEgB\nh2xqefXa5q97T4n7zl52mZa4apuhFg21ZyMgeHFgcvbyMJ+BkFVkeKcVVLVyBkZ33V1fcKy90Lv1\nEQIYUQyIACjaEpO+V8EzSUHzmbiWHkouuOe7aRlkH8lTQFjwNnFjhii5SN7T/HR2gqfQoRpSLNoX\n11xPlONY3eNXFfbyVaOKUMCenFuAqN4TTcGrdAeKnFQHvGSbS8wuxr0L6LwRRtmN25YOmq9n5BxF\npV9Chlz3Nhtm+6T4ei3j3vremc2G9BTq8PZ1YLQZqJRyh3Tb2IMQ23HCLb3yoQ4ZpPg1ZZNymmug\nVql8TPMelPFuU3IEXjpgy0SDbqUvZKcP5PKHTuVpdY5eRizzWbn7a6akaK67C//8IU6pBT6WkpLA\nVDG7HQ5KKlwvriaieUvWovcdt+7QusnnssrSWlMdK9jrZ82u9HUYHVKV8Xd5hDB1jYVu6Px36hQ2\n0v1g782llhV76QhcNlBHkDU2CsK3X555FSOcdMTD8BI+n5h0GROXkhSGlodgZTbWppO5QN3jaeWZ\n9a1HLU6dNMfTCEeOUe88KwDZPEFqSG4p0VtwrI863aJ04foZhZDyAjI1PDUNtgBZO2Oz+DJyhXaa\nKSEoR2Yj36JwX9JPzW8mkGxRb5Wx9N9I1/Szbje9t4KwPjOml4qWWpMqrBbpyrs2396STi4KCNLQ\n8dD2nwuApS26e6KvA3swEStkmcg4lPaHt73uL6N1VQxViQ2EEy4rbFy0S2AJzYqERyU+GtstUOcW\nh04cyB/2ofzso/h7nK59EXXXc8lmeFNNll2++rzh4sKZqQajxs/8Gcj65TLhk+uPqyAaFKmmSZeW\nd6jvCOCCgywB1EHAYOnOb9vwGGRCO3JGCLmC7QDTjTOm0FkqGoMUKYsee9Jqd+AtP+t17eVGuIVY\ntAr571S/EkWBcgDYPevACCxmnBp9OjNNBOskcVRUg5XMIim40rW6rv7bFDEDgpcXtBTw5dz7m505\nEJTbnrS+//j8NK4fgaIOl5bKD5x2qP1Z5CcPQc1rxLrkLFrTy8XlEptKXR0t1lQXd0Wkef55TxMT\nqs89vIeZfvIhprc2C9fK2RVjSYAhkj6Iu7TCimjFyr+HmsOsOQQZdQ50WNhAid1TjahlCJ9yCSM2\nSFk2oFhu/qBAvz5cPs0x6lrrRmRIoxvX3WA+IElb9TyFBPyP4BWdTcbfqnQ6XGDijou91uAVawoD\n27aFmoq2OCWPF/Fp+D8dcmb/XoPpK0SOEHaBU1ILRJkdRd6Ys4bq4isO3Sg8vkyA2iNcEZ2DtGkV\nH9IgbGEg1Mv8sPc/wjFMhb4BEqxNWQEKiYgDyA9+0VdYpJdy5X5gZnJxYxhzpEOLZpbbnjd3UeK0\nEKkNXwA41V21GqTZrrUlF76kn367l0KZTNgiNodIaDhxBkTPLMOtpDt75KoJ4Mrtz7HxeJXlUMLs\nj3HezUvOkrRldg1d/XonaIPRDgjcQFhIRTjOEald59tKjB5scFlrOqdI9zQycV4HLXdjifdfH/Dr\nfrQHwLor3niSXfIlsq9V9vLUCFDTNCRYzaE+LlNQbFITqmDUqy70neszXu3lowOaugZOrCx/xLiP\nss7Ja4qppT2Ctc13JZXtKVL6TKDel2VCx7xv0TxpPluSpiKZKUTQwzEb//Cf3o8HRx2YSwZM+kXo\ndb6T5DfBGcLWIujpgWhXW1i1aawHOLQMRqa/bpKAA5En4IfdYbHy0jt2k40ZG11elMVI6RKAtaZb\niRfZ9R5+Q/n0q/XlsbqpiOST0JUqHw3TQzIUl3a/GTAEM1B7E4/aXxOBXoEIBgR+lDXq59z+aZ6V\na/qDF6Cq85iXpIprWSu5PAw2ImEaHr3kZMg5pBYq2xjpYIX0L+FWB+/rlaegVs8JRRX8w7TjuPiI\nldwrcr8nj1s9l18z3ZjIvvfO6i9F8v61PVCGw+cJMCffOL1DUXz2/A4LdTO0Qq63fsJBzfrwNPyM\n4L9m0il1+TVxHhXVoSuSoXNhiIJbWut7GbW+rvTCQJjWk9HIPTN9xKxKFZsH/oRcWIyUI3ogahdW\nH9NEjMeVGwKaYqs85ai7US4jnVmxeYqc6sL6b4AI8zQW9lDAoyygkqC5NsuGZrbk5/GwdIpbCUza\nlV4lvoWrT2nzlCPdE7HqdofSVI/GPQ7EIhG0S9jqrL83rET779F7bWP9oFwAM3WXq2FD3zm2vtbh\nc2dLOEuB32W9sPfobiDEuqaCkrDTI60b+AgewQJcZ9mzktJhauyA5bDFxm/U0ffkqJaEswDtl8AD\nmAo2U8WeHnyMJEqkxx5ld5cLyF2UAMmCM6lGPtpgvknUUkNYs/lD2XhqxuM3cNCLZuvieJKxtFvM\nLbd0bNRMCX6bSVLjKfv+IW0WDBrtuJ17aCr50G1IvprZKzT/xRPVIu0p6p8hNH4953J/ghs9oo7c\nlKQ8loRvT6zSp3GyffPZJOVn9gu8lInMpJwWkFydpk0q/59aiHDXSoigjSM50xfZkM2xB7PXVYTd\nQEfibQ8bp33CVYbaynaCCaQqHVGy+9ML5q0Dsu1Mgs7ttCcpp3W5akyYcO5d8+GUxBMUe0sNq4tl\npVZNNwltEOiqD+QngAx6UkKw0PCg2lxyNyCQZ/E/symhb7OauoiCzQZVF02qMdopaQmGiY/ODvoh\nYtacenkASzgbBSOk0fOO8SsKAaWfuD6KRT0n8bSgZSPboejfoQpVOEmcxM1fFfIbZn60elHh0TWB\nclK+JftnN+AWkwQfTB/JKniwZ+lvqCsuieW1NmyUSR7ykBcRXXSA/0az0coEL/9bCmUeJje42E7X\n3q948+DGDEJc3wvWBANApYi3T8dvHoSv/xB3Sg3uVrCc6Q+vzOhQ1zgvY16rPkvBghqXZg4f/ibO\nGUrA30eB9dJYQkpT6sAhBVevG7t2YLCNsCNH/EpX88wA24JkJNBICyrhs/fbTQI5l86rmfxDybaZ\nV+C5cLUfrLvS74A9KOm8LzImz38+RE9naZuWIUwEKZtI/IqDkLJksZiw7jp+r1Rt7CnpJ9kUQ/ZY\nxwC6FwKaMOPLuelslAkGiig+MUGK8U8q/0wzWTJQgRZBSfu2Md+jmJQdLrdN4HfPGddtNg/rkqpZ\nGnTqmDTCNZHKaKyh8av5iZgAl4C5nsLhKmLgbbDFzsnrzKEv/IoHy9a2gtR2q2q9+ZmZ+TI9YeuG\nVfTbvZgjNKN+nNiL2kT1tpRoHf07mpdAkuAWMrXqddkcn9QyHYLlNOp0dRup0GM1yx0nHY/0hNZS\ngSJkzkBSDJu8fLjwG48jloXCrLjLGo/IUBDwOwUhyCk9ZJtLg5AefO1JndkWU33X+0y1xJGhoK6X\nt6FG7I4nyaqrsoFB6Ha0+UWSqsM/H+hyWWejJpBaI5nHPEZBbLwwaVm10hAFZdZ7oWB2Ve0Dbnyc\npOrPOVUmWOxTiIt5+hkylvrkGu1sQfRU1kBh7ynYIRKOvgljxP/AY0TI7Xs5ZxGJEJn2Y2H1PseT\nxvStZw5RwT5vYJxk/4tT+g9K3BU0LtE0UyGwpIDNlHpLPIT6CIYXNO/GC6vUfCrJh3qh8Pnyd0sX\nNEktZgvb5zGBYxGF46EU9bBwCX0s84fJ97aaxn/gTVv0Hcwq3cUb7U35uO5LHLjrlnUCh29jH0C4\nldzTqhf4Ch9XicZ/uJPVEONESBUmYskm2Y4EuudYmwvVcwEKCAOpmOVSfIHqvjU6EtHuvL2cdO8D\nx41OztnDd/549tkkn/p5SAcs25RZf0vBjrsl9Y1Iezqa3V8z0ZhE3rNUhNB5Oon2IkuC0Rvvltt0\np98veNeUyJDoO2k+hmaWflAEhX1e1RCZNLYx0xSquZxXD0VeaFUEObTKXdejMa7v597GFmoVPkPh\nYKH6ST9ati0TjVdJf+dNVqBRcaHkEzJcAMZLSdNRhPRTOB8J2OM71ealSLZ2lR31089Zlq2QZNaj\nK/viSQPz9ANHmXy4Y9WozP0JCYvMvkRgeF6hmpUEozNEh6efj09VSvAQ80lRJEP4pkFKJoahZ3Wh\nsGB5Z+pR90jHHKeMmQM6lKnUbSlr5YUmqeaSnY2FH60mUkKudlzklCc093iBPlN9fpdkbyQYXbZx\nfa5JtVZLHRLhAJVlIE/gR0js7KeS6d9pKkTFPRPbBwhFPPmZ1TZH//Z99ZlfRf0puhG2nMjqC8Aj\npYZlQ3yB3QR4fmEtLxIjdpY2/IsBNuR4WMI9P7scb/3S9L29X8bwzpVCBQy6WgdogzCZwX/KSInT\nqudwNMs34MHNXvRRBpzB4PVypZOD2LPg4A/JFwAe4PaD7f12CqAISeKEDLQJ8mgfGXEgYzOkRrI/\n3+YV8GNHuTH111rUwy5EO/xyhuMQCnKcUeTbg4hNXfYVdHTr/rsDNAhZg4RfYg2qBoBQblA+Hgoh\nkbvSH9IxR3JbuZGgoS9Dtsr3ichy2pHeO+wsbz1+EFBXE2+Nv1o27Ctl9YTjZy1FkA4F4DugCwI5\nJwmp4CSxlR5V9SDaFHV+Vu1TwBdQY3ttVnuAN6i7awhN1Ad1tIIaF8TH5pERQd5S0fYyxWgjLhn9\npHWVDFC2G+fhIL3BhQUohuHk4oCLQ6L5awnrPPLRqRn4zQDlebCN+fK9J0gdnvHyNyYQ/kaeXF9x\n4QhjVofyFnwwGIIh+pEx3UggaiMCTfm12/JPErbaC2cWkqNJaBKJ+kZUBwTutslEOVEue6ZPibBC\nlvVbw1M+zU3xyPx4SY/MzPQav6MEvRbaT7aTZcFf9la1TtyYvLgsQIB+uB1Jki8vLi6HOMcBThQv\nemw1tXDJlwv/TYh78mMNpllnTGG2prieiBG9cResrv5mEZRJS1RjRyTk9AGQ9GaqTIs0MAVikqco\neK2iSkNM0GWEjHtSluZrD/SzfyYXZsSzJKzD/RmeX2pJmqBaZ1KHgSOzUJC3O6GAQiLE2SDYrQfc\noA14lbLXgYldDUXJX5nrM6EhnNcaT5xBYelhPiqIG/qOsAt4HWOm3SdtK9P6COkCKAWUXhHTeukL\nmKEVwZsqRLRbu0SdhxgItkILQs0JHSpLRmuJfkmZgm53NthwkWNu2unlsZdzeNpVDXL9ilhT2iO1\nNH7HurARdw83ECxK3Who2IcWtdm9+cJ8LNR925XkNJKhHJhhQXGa4GesfJTlLwa0J3J1olAv7dJD\nIVeq5XnXOyW6gzhDzTpK2afgLW3Thq9EY8cM2oWk+vjabJ5i094lTotFRSv9B2lzbIuWBxF3JH0I\nudYhXIW6B9qFceaPBMQM793OUBQSBOi3WGu/Lm0k0FUyRzsTPr/9d1BRWD9b5YqxnWniN/mzDQmA\nYZpqnFuhZFS83FJ7EriLaOJXoisxsE2uVFxQZ7E3c0/WVyt9Pyk+Rq9vxE2c7PUmojV3Rewu3xgC\nHUxvS/q4yXuSWMwqLEbhRt8KyDGB2EcHrMGojI9A0ILuJiueXyd++NuiozOyn33QRNg79tDZH3mv\ni+8I7tqNxp3T0CfBA9QeH1tn6GHvkNBaiaZJ4ioqg2EiNpcbn5nNy33NT53S9uSlyB0Gzkqj9wf8\n0hR3wtkRcGA248PtuON0okzf7rE1mJDI5+hfpRgGyJjEbfJixeU7Lhk1PobdVkkGahSBtTqc2Ldk\noQMllEOGJTuXu46HY55ne9BLbK29u+3MMBz1KAZ58qKCo7sPv5eDsexOr/w3IGHx6Kdyme9VC4gI\nHpr/JGRH5gXt8I9AjgOObZ8YzWCs/KErnh5vKjYPgooq9PMFmD0MKcDUxefsPGCZbtJmcVefKM6h\nBlmVXH28KYc1/71keR1eZBOfhZN5H4IKnWJvnGSPEPWlNmkHDCmMBA/arDVDvUljsoTjFZDXP7T0\n+TjMu/o/7F+zMcZWiYKhgVKkKdWexgpiHXrV/jzlxFhT9fPcBL331pgw832rrR3zn2xBtdx3s/Ag\nK1Cob56W+pntouKPOSBv235PCfPB6A6/Ccw7rvfYZk8LHxle4Y1/PzsISmSD/LVo4cm/Exalc3bJ\n+jWv5iO6jmO2H94k1iA0Nv/3zHgy5iIpqr1Mv6JDpEAtk7Fh/Vh31tsj8vm7ypdcArVQLrZwKYjX\nULh2r6jJOaE8J4PZIgVVGLE9YOmo7BFmfeOhlhkettJhttRcLQdBg126cn1h07bgI2/R4A8FI5ux\nEaWY3u77/vSyaIdQhCF/P3CDABPg+NUyB2mOZkueZZLn5WcQXi/qsIaWa/tXDAGrSaNPF0BUpr0D\nNORQ2oB+sPYpR+iCKvBonHa0hnYsrGlwdwEsz3yguKJpXImkzHAzuYg4Liz6ePZcCW2ZhCSATfZC\nnsGKryGfcDacjk9bvdnNyM0GErMfMbCStu5PZ2r7tRBl+JAYLs0q4OUbr3pX0ne4yoJ31nWSCsl/\no6uk+txkgX3mufLWDGXeNyfaar2RWSKXXQNY1ypDhVTMGj8kPYvQq5HkaZ11Xme0QHgfuRwJqtqh\n8lzVdEQqR1iXV4T6JXENbyBJKTdtkWgcHSzL2s489b3ObCag7j8FPZT5bw+8FliIPY0yxkAr0cRR\ndaKSqx8MxxqntzyJSv66i46SMpCdBKRq0RxZxkv+pHlbESDlhJnZATCho6xuoLk3LI/X2BFR4VX0\numzxeRO/zPXvZWEFgvWb7vPucX5mlBx4j/13u9aZVNcv8qzODK5Tvgdgwc5TSSZq49U0v+9FJFNu\nvSxtSDPPL0b52168r8Kj8O5EgF745J7FdO8n+gu+ma79Qfo/v3LNezC1Q7phWk+RLwYWEB/fC44v\nDbkUkzn7niBiRc+gffcMBzcWNXXMg6ym6FHOMi+xkiVFXFvLIc39i1tT+PyocfD9Yf2DSG2WtUXb\nrExRkxKCe/O/375k4LLknHaBoJmB7m4FcgFZl6WZcgL7Ak78RhFXrmeGuxcuGW4b2njWh+RwOFuD\n1tPq/OWTREvGcq4/OCyOPhuOmLuJuFbKroZYZQKxLS9rTBBVudy8Lm6wygRT4cNoQgO0Ft6wE7Dk\nLVV5SkjkW1wCKNuC32+quUYlwToikg8OX9hqMxp8EAryEIAkhcYpC4+WBh682E/q+e3UzWLiutoy\nxserP8cf15U6aL4UT7nL/Nxmwhw6EzKtHC8JgJevouggntc2V+PvI6qi9bqstuyZu2ogmWkrB9O/\n0vwCkKjyNJMOY9w4Ltb+Jc3mm6sZ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protect end_protected\n", "num_lines": 510}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_sde_ps (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26,\nprobe27,\nprobe28,\nprobe29,\nprobe30,\nprobe31,\nprobe32,\nprobe33,\nprobe34,\nprobe35,\nprobe36,\nprobe37,\nprobe38,\nprobe39,\nprobe40,\nprobe41,\nprobe42,\nprobe43,\nprobe44,\nprobe45,\nprobe46\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [31 : 0] probe1;\ninput [0 : 0] probe2;\ninput [0 : 0] probe3;\ninput [31 : 0] probe4;\ninput [0 : 0] probe5;\ninput [0 : 0] probe6;\ninput [31 : 0] probe7;\ninput [0 : 0] probe8;\ninput [0 : 0] probe9;\ninput [0 : 0] probe10;\ninput [15 : 0] probe11;\ninput [31 : 0] probe12;\ninput [0 : 0] probe13;\ninput [31 : 0] probe14;\ninput [0 : 0] probe15;\ninput [0 : 0] probe16;\ninput [15 : 0] probe17;\ninput [31 : 0] probe18;\ninput [0 : 0] probe19;\ninput [31 : 0] probe20;\ninput [0 : 0] probe21;\ninput [0 : 0] probe22;\ninput [15 : 0] probe23;\ninput [31 : 0] probe24;\ninput [0 : 0] probe25;\ninput [31 : 0] probe26;\ninput [0 : 0] probe27;\ninput [0 : 0] probe28;\ninput [15 : 0] probe29;\ninput [31 : 0] probe30;\ninput [0 : 0] probe31;\ninput [31 : 0] probe32;\ninput [0 : 0] probe33;\ninput [4 : 0] probe34;\ninput [0 : 0] probe35;\ninput [0 : 0] probe36;\ninput [0 : 0] probe37;\ninput [0 : 0] probe38;\ninput [0 : 0] probe39;\ninput [0 : 0] probe40;\ninput [0 : 0] probe41;\ninput [0 : 0] probe42;\ninput [0 : 0] probe43;\ninput [0 : 0] probe44;\ninput [0 : 0] probe45;\ninput [0 : 0] probe46;\n\n\nendmodule\n", "num_lines": 155}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"ila_sde_ps,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_sde_ps,ila,{x_ipProduct=Vivado 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13_WIDTH=1,C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1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*)\n\nmodule ila_sde_ps (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26,\nprobe27,\nprobe28,\nprobe29,\nprobe30,\nprobe31,\nprobe32,\nprobe33,\nprobe34,\nprobe35,\nprobe36,\nprobe37,\nprobe38,\nprobe39,\nprobe40,\nprobe41,\nprobe42,\nprobe43,\nprobe44,\nprobe45,\nprobe46\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [31 : 0] probe1;\ninput [0 : 0] probe2;\ninput [0 : 0] probe3;\ninput [31 : 0] probe4;\ninput [0 : 0] probe5;\ninput [0 : 0] probe6;\ninput [31 : 0] probe7;\ninput [0 : 0] probe8;\ninput [0 : 0] probe9;\ninput [0 : 0] probe10;\ninput [15 : 0] probe11;\ninput [31 : 0] probe12;\ninput [0 : 0] probe13;\ninput [31 : 0] probe14;\ninput [0 : 0] probe15;\ninput [0 : 0] probe16;\ninput [15 : 0] probe17;\ninput [31 : 0] probe18;\ninput [0 : 0] probe19;\ninput [31 : 0] probe20;\ninput [0 : 0] probe21;\ninput [0 : 0] probe22;\ninput [15 : 0] probe23;\ninput [31 : 0] probe24;\ninput [0 : 0] probe25;\ninput [31 : 0] probe26;\ninput [0 : 0] probe27;\ninput [0 : 0] probe28;\ninput [15 : 0] probe29;\ninput [31 : 0] probe30;\ninput [0 : 0] probe31;\ninput [31 : 0] probe32;\ninput [0 : 0] probe33;\ninput [4 : 0] probe34;\ninput [0 : 0] probe35;\ninput [0 : 0] probe36;\ninput [0 : 0] probe37;\ninput [0 : 0] probe38;\ninput [0 : 0] probe39;\ninput [0 : 0] probe40;\ninput [0 : 0] probe41;\ninput [0 : 0] probe42;\ninput [0 : 0] probe43;\ninput [0 : 0] probe44;\ninput [0 : 0] probe45;\ninput [0 : 0] probe46;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_5_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(47),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2017),\n.C_MINOR_VERSION(4),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(0),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(2),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH 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.C_PROBE65_MU_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT(1),\n.C_PROBE275_MU_CNT(1),\n.C_PROBE276_MU_CNT(1),\n.C_PROBE277_MU_CNT(1),\n.C_PROBE278_MU_CNT(1),\n.C_PROBE279_MU_CNT(1),\n.C_PROBE280_MU_CNT(1),\n.C_PROBE281_MU_CNT(1),\n.C_PROBE282_MU_CNT(1),\n.C_PROBE283_MU_CNT(1),\n.C_PROBE284_MU_CNT(1),\n.C_PROBE285_MU_CNT(1),\n.C_PROBE286_MU_CNT(1),\n.C_PROBE287_MU_CNT(1),\n.C_PROBE288_MU_CNT(1),\n.C_PROBE289_MU_CNT(1),\n.C_PROBE290_MU_CNT(1),\n.C_PROBE291_MU_CNT(1),\n.C_PROBE292_MU_CNT(1),\n.C_PROBE293_MU_CNT(1),\n.C_PROBE294_MU_CNT(1),\n.C_PROBE295_MU_CNT(1),\n.C_PROBE296_MU_CNT(1),\n.C_PROBE297_MU_CNT(1),\n.C_PROBE298_MU_CNT(1),\n.C_PROBE299_MU_CNT(1),\n.C_PROBE300_MU_CNT(1),\n.C_PROBE301_MU_CNT(1),\n.C_PROBE302_MU_CNT(1),\n.C_PROBE303_MU_CNT(1),\n.C_PROBE304_MU_CNT(1),\n.C_PROBE305_MU_CNT(1),\n.C_PROBE306_MU_CNT(1),\n.C_PROBE307_MU_CNT(1),\n.C_PROBE308_MU_CNT(1),\n.C_PROBE309_MU_CNT(1),\n.C_PROBE310_MU_CNT(1),\n.C_PROBE311_MU_CNT(1),\n.C_PROBE312_MU_CNT(1),\n.C_PROBE313_MU_CNT(1),\n.C_PROBE314_MU_CNT(1),\n.C_PROBE315_MU_CNT(1),\n.C_PROBE316_MU_CNT(1),\n.C_PROBE317_MU_CNT(1),\n.C_PROBE318_MU_CNT(1),\n.C_PROBE319_MU_CNT(1),\n.C_PROBE320_MU_CNT(1),\n.C_PROBE321_MU_CNT(1),\n.C_PROBE322_MU_CNT(1),\n.C_PROBE323_MU_CNT(1),\n.C_PROBE324_MU_CNT(1),\n.C_PROBE325_MU_CNT(1),\n.C_PROBE326_MU_CNT(1),\n.C_PROBE327_MU_CNT(1),\n.C_PROBE328_MU_CNT(1),\n.C_PROBE329_MU_CNT(1),\n.C_PROBE330_MU_CNT(1),\n.C_PROBE331_MU_CNT(1),\n.C_PROBE332_MU_CNT(1),\n.C_PROBE333_MU_CNT(1),\n.C_PROBE334_MU_CNT(1),\n.C_PROBE335_MU_CNT(1),\n.C_PROBE336_MU_CNT(1),\n.C_PROBE337_MU_CNT(1),\n.C_PROBE338_MU_CNT(1),\n.C_PROBE339_MU_CNT(1),\n.C_PROBE340_MU_CNT(1),\n.C_PROBE341_MU_CNT(1),\n.C_PROBE342_MU_CNT(1),\n.C_PROBE343_MU_CNT(1),\n.C_PROBE344_MU_CNT(1),\n.C_PROBE345_MU_CNT(1),\n.C_PROBE346_MU_CNT(1),\n.C_PROBE347_MU_CNT(1),\n.C_PROBE348_MU_CNT(1),\n.C_PROBE349_MU_CNT(1),\n.C_PROBE350_MU_CNT(1),\n.C_PROBE351_MU_CNT(1),\n.C_PROBE352_MU_CNT(1),\n.C_PROBE353_MU_CNT(1),\n.C_PROBE354_MU_CNT(1),\n.C_PROBE355_MU_CNT(1),\n.C_PROBE356_MU_CNT(1),\n.C_PROBE357_MU_CNT(1),\n.C_PROBE358_MU_CNT(1),\n.C_PROBE359_MU_CNT(1),\n.C_PROBE360_MU_CNT(1),\n.C_PROBE361_MU_CNT(1),\n.C_PROBE362_MU_CNT(1),\n.C_PROBE363_MU_CNT(1),\n.C_PROBE364_MU_CNT(1),\n.C_PROBE365_MU_CNT(1),\n.C_PROBE366_MU_CNT(1),\n.C_PROBE367_MU_CNT(1),\n.C_PROBE368_MU_CNT(1),\n.C_PROBE369_MU_CNT(1),\n.C_PROBE370_MU_CNT(1),\n.C_PROBE371_MU_CNT(1),\n.C_PROBE372_MU_CNT(1),\n.C_PROBE373_MU_CNT(1),\n.C_PROBE374_MU_CNT(1),\n.C_PROBE375_MU_CNT(1),\n.C_PROBE376_MU_CNT(1),\n.C_PROBE377_MU_CNT(1),\n.C_PROBE378_MU_CNT(1),\n.C_PROBE379_MU_CNT(1),\n.C_PROBE380_MU_CNT(1),\n.C_PROBE381_MU_CNT(1),\n.C_PROBE382_MU_CNT(1),\n.C_PROBE383_MU_CNT(1),\n.C_PROBE384_MU_CNT(1),\n.C_PROBE385_MU_CNT(1),\n.C_PROBE386_MU_CNT(1),\n.C_PROBE387_MU_CNT(1),\n.C_PROBE388_MU_CNT(1),\n.C_PROBE389_MU_CNT(1),\n.C_PROBE390_MU_CNT(1),\n.C_PROBE391_MU_CNT(1),\n.C_PROBE392_MU_CNT(1),\n.C_PROBE393_MU_CNT(1),\n.C_PROBE394_MU_CNT(1),\n.C_PROBE395_MU_CNT(1),\n.C_PROBE396_MU_CNT(1),\n.C_PROBE397_MU_CNT(1),\n.C_PROBE398_MU_CNT(1),\n.C_PROBE399_MU_CNT(1),\n.C_PROBE400_MU_CNT(1),\n.C_PROBE401_MU_CNT(1),\n.C_PROBE402_MU_CNT(1),\n.C_PROBE403_MU_CNT(1),\n.C_PROBE404_MU_CNT(1),\n.C_PROBE405_MU_CNT(1),\n.C_PROBE406_MU_CNT(1),\n.C_PROBE407_MU_CNT(1),\n.C_PROBE408_MU_CNT(1),\n.C_PROBE409_MU_CNT(1),\n.C_PROBE410_MU_CNT(1),\n.C_PROBE411_MU_CNT(1),\n.C_PROBE412_MU_CNT(1),\n.C_PROBE413_MU_CNT(1),\n.C_PROBE414_MU_CNT(1),\n.C_PROBE415_MU_CNT(1),\n.C_PROBE416_MU_CNT(1),\n.C_PROBE417_MU_CNT(1),\n.C_PROBE418_MU_CNT(1),\n.C_PROBE419_MU_CNT(1),\n.C_PROBE420_MU_CNT(1),\n.C_PROBE421_MU_CNT(1),\n.C_PROBE422_MU_CNT(1),\n.C_PROBE423_MU_CNT(1),\n.C_PROBE424_MU_CNT(1),\n.C_PROBE425_MU_CNT(1),\n.C_PROBE426_MU_CNT(1),\n.C_PROBE427_MU_CNT(1),\n.C_PROBE428_MU_CNT(1),\n.C_PROBE429_MU_CNT(1),\n.C_PROBE430_MU_CNT(1),\n.C_PROBE431_MU_CNT(1),\n.C_PROBE432_MU_CNT(1),\n.C_PROBE433_MU_CNT(1),\n.C_PROBE434_MU_CNT(1),\n.C_PROBE435_MU_CNT(1),\n.C_PROBE436_MU_CNT(1),\n.C_PROBE437_MU_CNT(1),\n.C_PROBE438_MU_CNT(1),\n.C_PROBE439_MU_CNT(1),\n.C_PROBE440_MU_CNT(1),\n.C_PROBE441_MU_CNT(1),\n.C_PROBE442_MU_CNT(1),\n.C_PROBE443_MU_CNT(1),\n.C_PROBE444_MU_CNT(1),\n.C_PROBE445_MU_CNT(1),\n.C_PROBE446_MU_CNT(1),\n.C_PROBE447_MU_CNT(1),\n.C_PROBE448_MU_CNT(1),\n.C_PROBE449_MU_CNT(1),\n.C_PROBE450_MU_CNT(1),\n.C_PROBE451_MU_CNT(1),\n.C_PROBE452_MU_CNT(1),\n.C_PROBE453_MU_CNT(1),\n.C_PROBE454_MU_CNT(1),\n.C_PROBE455_MU_CNT(1),\n.C_PROBE456_MU_CNT(1),\n.C_PROBE457_MU_CNT(1),\n.C_PROBE458_MU_CNT(1),\n.C_PROBE459_MU_CNT(1),\n.C_PROBE460_MU_CNT(1),\n.C_PROBE461_MU_CNT(1),\n.C_PROBE462_MU_CNT(1),\n.C_PROBE463_MU_CNT(1),\n.C_PROBE464_MU_CNT(1),\n.C_PROBE465_MU_CNT(1),\n.C_PROBE466_MU_CNT(1),\n.C_PROBE467_MU_CNT(1),\n.C_PROBE468_MU_CNT(1),\n.C_PROBE469_MU_CNT(1),\n.C_PROBE470_MU_CNT(1),\n.C_PROBE471_MU_CNT(1),\n.C_PROBE472_MU_CNT(1),\n.C_PROBE473_MU_CNT(1),\n.C_PROBE474_MU_CNT(1),\n.C_PROBE475_MU_CNT(1),\n.C_PROBE476_MU_CNT(1),\n.C_PROBE477_MU_CNT(1),\n.C_PROBE478_MU_CNT(1),\n.C_PROBE479_MU_CNT(1),\n.C_PROBE480_MU_CNT(1),\n.C_PROBE481_MU_CNT(1),\n.C_PROBE482_MU_CNT(1),\n.C_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1),\n.C_PROBE691_MU_CNT(1),\n.C_PROBE692_MU_CNT(1),\n.C_PROBE693_MU_CNT(1),\n.C_PROBE694_MU_CNT(1),\n.C_PROBE695_MU_CNT(1),\n.C_PROBE696_MU_CNT(1),\n.C_PROBE697_MU_CNT(1),\n.C_PROBE698_MU_CNT(1),\n.C_PROBE699_MU_CNT(1),\n.C_PROBE700_MU_CNT(1),\n.C_PROBE701_MU_CNT(1),\n.C_PROBE702_MU_CNT(1),\n.C_PROBE703_MU_CNT(1),\n.C_PROBE704_MU_CNT(1),\n.C_PROBE705_MU_CNT(1),\n.C_PROBE706_MU_CNT(1),\n.C_PROBE707_MU_CNT(1),\n.C_PROBE708_MU_CNT(1),\n.C_PROBE709_MU_CNT(1),\n.C_PROBE710_MU_CNT(1),\n.C_PROBE711_MU_CNT(1),\n.C_PROBE712_MU_CNT(1),\n.C_PROBE713_MU_CNT(1),\n.C_PROBE714_MU_CNT(1),\n.C_PROBE715_MU_CNT(1),\n.C_PROBE716_MU_CNT(1),\n.C_PROBE717_MU_CNT(1),\n.C_PROBE718_MU_CNT(1),\n.C_PROBE719_MU_CNT(1),\n.C_PROBE720_MU_CNT(1),\n.C_PROBE721_MU_CNT(1),\n.C_PROBE722_MU_CNT(1),\n.C_PROBE723_MU_CNT(1),\n.C_PROBE724_MU_CNT(1),\n.C_PROBE725_MU_CNT(1),\n.C_PROBE726_MU_CNT(1),\n.C_PROBE727_MU_CNT(1),\n.C_PROBE728_MU_CNT(1),\n.C_PROBE729_MU_CNT(1),\n.C_PROBE730_MU_CNT(1),\n.C_PROBE731_MU_CNT(1),\n.C_PROBE732_MU_CNT(1),\n.C_PROBE733_MU_CNT(1),\n.C_PROBE734_MU_CNT(1),\n.C_PROBE735_MU_CNT(1),\n.C_PROBE736_MU_CNT(1),\n.C_PROBE737_MU_CNT(1),\n.C_PROBE738_MU_CNT(1),\n.C_PROBE739_MU_CNT(1),\n.C_PROBE740_MU_CNT(1),\n.C_PROBE741_MU_CNT(1),\n.C_PROBE742_MU_CNT(1),\n.C_PROBE743_MU_CNT(1),\n.C_PROBE744_MU_CNT(1),\n.C_PROBE745_MU_CNT(1),\n.C_PROBE746_MU_CNT(1),\n.C_PROBE747_MU_CNT(1),\n.C_PROBE748_MU_CNT(1),\n.C_PROBE749_MU_CNT(1),\n.C_PROBE750_MU_CNT(1),\n.C_PROBE751_MU_CNT(1),\n.C_PROBE752_MU_CNT(1),\n.C_PROBE753_MU_CNT(1),\n.C_PROBE754_MU_CNT(1),\n.C_PROBE755_MU_CNT(1),\n.C_PROBE756_MU_CNT(1),\n.C_PROBE757_MU_CNT(1),\n.C_PROBE758_MU_CNT(1),\n.C_PROBE759_MU_CNT(1),\n.C_PROBE760_MU_CNT(1),\n.C_PROBE761_MU_CNT(1),\n.C_PROBE762_MU_CNT(1),\n.C_PROBE763_MU_CNT(1),\n.C_PROBE764_MU_CNT(1),\n.C_PROBE765_MU_CNT(1),\n.C_PROBE766_MU_CNT(1),\n.C_PROBE767_MU_CNT(1),\n.C_PROBE768_MU_CNT(1),\n.C_PROBE769_MU_CNT(1),\n.C_PROBE770_MU_CNT(1),\n.C_PROBE771_MU_CNT(1),\n.C_PROBE772_MU_CNT(1),\n.C_PROBE773_MU_CNT(1),\n.C_PROBE774_MU_CNT(1),\n.C_PROBE775_MU_CNT(1),\n.C_PROBE776_MU_CNT(1),\n.C_PROBE777_MU_CNT(1),\n.C_PROBE778_MU_CNT(1),\n.C_PROBE779_MU_CNT(1),\n.C_PROBE780_MU_CNT(1),\n.C_PROBE781_MU_CNT(1),\n.C_PROBE782_MU_CNT(1),\n.C_PROBE783_MU_CNT(1),\n.C_PROBE784_MU_CNT(1),\n.C_PROBE785_MU_CNT(1),\n.C_PROBE786_MU_CNT(1),\n.C_PROBE787_MU_CNT(1),\n.C_PROBE788_MU_CNT(1),\n.C_PROBE789_MU_CNT(1),\n.C_PROBE790_MU_CNT(1),\n.C_PROBE791_MU_CNT(1),\n.C_PROBE792_MU_CNT(1),\n.C_PROBE793_MU_CNT(1),\n.C_PROBE794_MU_CNT(1),\n.C_PROBE795_MU_CNT(1),\n.C_PROBE796_MU_CNT(1),\n.C_PROBE797_MU_CNT(1),\n.C_PROBE798_MU_CNT(1),\n.C_PROBE799_MU_CNT(1),\n.C_PROBE800_MU_CNT(1),\n.C_PROBE801_MU_CNT(1),\n.C_PROBE802_MU_CNT(1),\n.C_PROBE803_MU_CNT(1),\n.C_PROBE804_MU_CNT(1),\n.C_PROBE805_MU_CNT(1),\n.C_PROBE806_MU_CNT(1),\n.C_PROBE807_MU_CNT(1),\n.C_PROBE808_MU_CNT(1),\n.C_PROBE809_MU_CNT(1),\n.C_PROBE810_MU_CNT(1),\n.C_PROBE811_MU_CNT(1),\n.C_PROBE812_MU_CNT(1),\n.C_PROBE813_MU_CNT(1),\n.C_PROBE814_MU_CNT(1),\n.C_PROBE815_MU_CNT(1),\n.C_PROBE816_MU_CNT(1),\n.C_PROBE817_MU_CNT(1),\n.C_PROBE818_MU_CNT(1),\n.C_PROBE819_MU_CNT(1),\n.C_PROBE820_MU_CNT(1),\n.C_PROBE821_MU_CNT(1),\n.C_PROBE822_MU_CNT(1),\n.C_PROBE823_MU_CNT(1),\n.C_PROBE824_MU_CNT(1),\n.C_PROBE825_MU_CNT(1),\n.C_PROBE826_MU_CNT(1),\n.C_PROBE827_MU_CNT(1),\n.C_PROBE828_MU_CNT(1),\n.C_PROBE829_MU_CNT(1),\n.C_PROBE830_MU_CNT(1),\n.C_PROBE831_MU_CNT(1),\n.C_PROBE832_MU_CNT(1),\n.C_PROBE833_MU_CNT(1),\n.C_PROBE834_MU_CNT(1),\n.C_PROBE835_MU_CNT(1),\n.C_PROBE836_MU_CNT(1),\n.C_PROBE837_MU_CNT(1),\n.C_PROBE838_MU_CNT(1),\n.C_PROBE839_MU_CNT(1),\n.C_PROBE840_MU_CNT(1),\n.C_PROBE841_MU_CNT(1),\n.C_PROBE842_MU_CNT(1),\n.C_PROBE843_MU_CNT(1),\n.C_PROBE844_MU_CNT(1),\n.C_PROBE845_MU_CNT(1),\n.C_PROBE846_MU_CNT(1),\n.C_PROBE847_MU_CNT(1),\n.C_PROBE848_MU_CNT(1),\n.C_PROBE849_MU_CNT(1),\n.C_PROBE850_MU_CNT(1),\n.C_PROBE851_MU_CNT(1),\n.C_PROBE852_MU_CNT(1),\n.C_PROBE853_MU_CNT(1),\n.C_PROBE854_MU_CNT(1),\n.C_PROBE855_MU_CNT(1),\n.C_PROBE856_MU_CNT(1),\n.C_PROBE857_MU_CNT(1),\n.C_PROBE858_MU_CNT(1),\n.C_PROBE859_MU_CNT(1),\n.C_PROBE860_MU_CNT(1),\n.C_PROBE861_MU_CNT(1),\n.C_PROBE862_MU_CNT(1),\n.C_PROBE863_MU_CNT(1),\n.C_PROBE864_MU_CNT(1),\n.C_PROBE865_MU_CNT(1),\n.C_PROBE866_MU_CNT(1),\n.C_PROBE867_MU_CNT(1),\n.C_PROBE868_MU_CNT(1),\n.C_PROBE869_MU_CNT(1),\n.C_PROBE870_MU_CNT(1),\n.C_PROBE871_MU_CNT(1),\n.C_PROBE872_MU_CNT(1),\n.C_PROBE873_MU_CNT(1),\n.C_PROBE874_MU_CNT(1),\n.C_PROBE875_MU_CNT(1),\n.C_PROBE876_MU_CNT(1),\n.C_PROBE877_MU_CNT(1),\n.C_PROBE878_MU_CNT(1),\n.C_PROBE879_MU_CNT(1),\n.C_PROBE880_MU_CNT(1),\n.C_PROBE881_MU_CNT(1),\n.C_PROBE882_MU_CNT(1),\n.C_PROBE883_MU_CNT(1),\n.C_PROBE884_MU_CNT(1),\n.C_PROBE885_MU_CNT(1),\n.C_PROBE886_MU_CNT(1),\n.C_PROBE887_MU_CNT(1),\n.C_PROBE888_MU_CNT(1),\n.C_PROBE889_MU_CNT(1),\n.C_PROBE890_MU_CNT(1),\n.C_PROBE891_MU_CNT(1),\n.C_PROBE892_MU_CNT(1),\n.C_PROBE893_MU_CNT(1),\n.C_PROBE894_MU_CNT(1),\n.C_PROBE895_MU_CNT(1),\n.C_PROBE896_MU_CNT(1),\n.C_PROBE897_MU_CNT(1),\n.C_PROBE898_MU_CNT(1),\n.C_PROBE899_MU_CNT(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synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4333}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nbGT7tfmyts6/yZChogAFs2kP2mbFmmuiFroOv0r8QQv1hFG6JERBCXNBXfGou+8mLPigR5LV4eDx\nWE5VTd+gHQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nCWoEkLQgvsHNvKsNgOsMIlwqULIpu7GrNWea7T7cH++wHThbYiHobD6dcKucCQM5dNGL646pzspi\ngvc21hWZnPx+X5N28b2dNoegtcTB2kLdLw7Lks54cB9DeoTavLfTRXQYufpEksbrNJTUFVb2cNyN\n6BMeJUXHbb0vXcc5VT4=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nFNNqjXbqqfIGkUevtN9QbqDJwQreUsmu9xji2a/w3CJH665OoQqvJUOiq4+1ZDezrG2FheefDlOu\nudQOQzfUbqq4ZB7QVsrZ5+hnOl4+bTdi/FvverAngGvvJSU8+8gbzJ8jtcieV+kp8HrIMv5M1gu6\nVP5SY5P9OIiRMPqToUbAWBrFRpgduuTuMhaHwW7FZmVUVb1j1U3rE2T6UyEel2fueSISKzjAYa8d\nbMNfbkA2ORUFxDxV3b+bBcjCg+jYWECoAY59uutuI1TCRGdhy4DLAvrLFqaLXnKzQ/zhmv78sBnu\n10yEbUQnFKzl5lQwpKtElSrzEVryLPjEKxtU0Q==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nBtsuQ3rIBJ3UI+4s+peHFvk2pezsWjwgWqpQQAOktytWfnh45F6oITlHSewxA1WtBlnC7B06RlL1\nsh5uBcV81aLk24XWmuA7DcJrmhXRSOvl0k4gIwFckG2lpuYtWsH8y7owyOiD/FZUz/LSfTa3Mywh\nD7uNSNvKmmqFP0yIDB9zQtZJYDKPgeAlZS9NUZdzjF/a61kdekWKbPaCmwFQ0mA01X8N8Euy78Cm\ntwhuK1u9d5vu3NtNKQQjzffGoOig7AOKPE+KjZrhCajjfXLjFewajxJNXuRqE4Qr4GGCy18JUK+r\n9AD7YQrF9CXYq3xjR5zoOedNXXQz29GC/jViKA==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nGzBT1kWKJ35ymgjppXjhmBsPZAh+qqs629kt2BvXZjQHKHWH3WuilMysbQpFcvgaH9NxbR7qFPN6\nyb5XgBkpZDUCCrc6p6YR51wXM/nxNvw23FSNPFKjoFEw2V83YYFxlbr75lWeNCQl27cPfBPuxaSV\nIjlxIsm4eW9SkxEnTQqMX5ySy4IaL9yElffDeFxfvmZFrx9lJp5FMRFsWvs0CJEBnPV6KLu1CvY0\njoTQyovEbzWILZvpO6OoWWowRhHO/ukpDVkTQwizIuNbetdcKud8UyyAngECUSjve9k+rXX41zHR\nrDfFrjZc+RPg2YpdeYHykcsisoZ5sdzyCy4T5w==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\niim3M0ZIoSIeblUIY0hk1kn3BvlRMe2uVKS16OYK9H9BGNvnKistWqz2WEU4s7eijjhhkWdw6Rx0\n1TXQht76iCER16gWcazz66/Akg5MH+lOp9NPf3J2iEV7LK7f+3F9jgvrsadzyPoTuLecIoWFoNJk\nFXdJK8072alT4ln/U8w=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\npJ/yajVXTo6y0FFyEOL0HIGDXa+xEims4jF/m3KWWifm3tyRZ/Qmr6px8fbYo6wt98IysxEsBMsY\nOafake1VkQe9IEYdvl9w2pbHgnMGCgpFHt5GVkkx9kTM7g8X5yw1cj7dCjsuNtLtsSeZ7wW2gvp4\nba+UNyDRcpm3wErDehZlm6QU2gigOYOXUMH6KQLyei8VsyCUEOLrtDfoDMEgbTsPan0OVwWZ4Yma\nBViyJ567bWm+BUmLR7HMTK0+QktDEmFhL5lWaTS848MSM8+2esUyNGdKKutfcQWcpHUx0GkIOnS0\nlZ1qTioC56L1NI2aXWshT+ZrJgi5x4ZYDqF6IA==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64336)\n`pragma protect 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ikj4QY9qy76XYw6IDsQdBnIGtPSFwxd9wChRjkni7PaX9nBoTv4Hkv4/X71ms92d\ntJ/07jLvlYIC/ZQu83ENzkpZcQxr+WVAlk9voN1Lh8MJ41Cksb/e82lQv3tE0i33RVWsfpzzkmhl\n6+iCuWQ09/k8dS0FyYp1eOOSakJpDvCoKsuGEA54TK2SkuCKjd+GAxav426xXnGAV1GxKJw4LUC+\nBoIDk42kjGmgDrTucR4D8ebhRKZlfSndBkUN1MxM4jhRdlUOlo1unmkpDpwboVbaBL63n0cP4G6M\nMWgaQmfg3Yi3VurtkG15kqklP5W2hoXk4N43ho9pwxbkiD0fB7BonN/w9HJv4Zu26k8JguWWER+r\nF24R1GsE91Dl6f8PkWleIhz82kPHFEq5RrhTesz5mPkAh4LBNNYQcbTVLlK5Bz0FGVt33lgt9zoT\n1OXASFCArKzZWd2y0Q5uZ6j1/oVxBrIIV84Ebwg//J/PeKNV+7dWoxdxrSyxxRk9/vGvVL/UxkDL\nXNFXWyLhbVlxG08uYDNL1cw4o1C3ePlskKxvHjLKaClc/79HN04C/k9fm51CrfmvosEcGzKhDPBj\nHMwFxAT3Pw83gG0A4Em+qHW7Wk8Bzor/p/e6kDCX2WbCTGXt8ZMf/Cq6Dryzr2sDHKfteVQJ2fpF\nHC/D0b26BUXdwRPX01IK0w8qiZ5/xcJUdwszggylh3pIeyt8qnPlZ1xYYH05884oekPtILD0GlZx\ndRw6hgHq6NYCifq33HepQkocmMaiBik7yzszAuKAWn2x5Raf/FC2GSRLb3itncwKnJGL7yYaSZeJ\n8OUhkMmGPtZ8ImThhDZ/RWkOBq+OUYnTNhKc3FmrCT9LsMzW0ZyQ9o+VsZv9bTJ+USliatHl6PD/\nLRypXj3clKV1a/C8C+rxwRip4mEQfKcf0UiZgBr6eYubS93izNsyymJ1mp/BMX6jt+kcmR3LAEE0\ncpyyOM0mIgNkjmJmLmv3R6jg/bPvI2p1N7/cIyybB4G0BZtRYMXRngfz1Q6EMQeQVsUna9iAjvQy\nAG2r/xcgJFufo3kkRGq2V3bTmOg/azUFNjzL/9jw4R6mkP391rUCjjKNDXYCpxvDS4Ye2p86OKcN\nXM4s+2bmJRe5JMBVj+0ZHS7ii0Mabn0ehWpoyMokVNz6dMpxel4glyyMLn1uEeaGHRDWuRfCqrOB\nfTnvUVJz1HNeGj9q7pSndbVygb7ZUsG8h3ZCkcyQhLOw47qwv3lDHtO77/HoYY9Tr62YzSiUh3z0\n9j8wCnOkMiqstzZ3iSyRXlGTQ8cV0IIcZ4obZHfQfj7I+N4MXnxEm4Pf8DHrXxlE0RxiG3MLn8Qp\nv1AES70B0p6TKWBC7H1cOxVI/K1ykT6KjY377HDe//18VNIC6IlFJzNuCN1q/+iLfRWlGy+uFMco\nAuFhgOP9A77fsu7sTi6ay+PaHjwC+jIiDGXdUXLPAJHxpDQzZfnDDo14bCy2ZRz1RWNEkUkLH6tY\nuGcD3kggbTyfoEOTkCtHzmGI7kFz1z7J9DYLueA4OMGamCdMbQxvlcUkwx/Yam/jPH2MB8HtyspC\new/FctHMgwthFB+FzPoSwmv+vsUZD7p8hri9LeoCnXPfXS7B0PhDyaHknDkaPDhEol1WramhVo0u\nGKZ8x1eDO9ipKqbYemWHLiAhYr8UXDVwN94diYZ9VcYwIrwr1P2VsWG/9O+R3rFngUUFk8Z4Bvip\n3PBfNVwE/QWhb/BgkmHeTvSayZckM9vCuruECucSChqNjhhIvSGY8CStQKNM+eK89IlUPsvIBY6l\nRZyKERWn9mxbX4ormBumHi4IznKEziX9fRRAEGW0uSLFhi/c435Qai4kSdBAoqvRTsu+7pIC8yv6\nmZ3UTSFrP9ATOE0GChYyllkCW590wKjCJcVXcdotPCuG+4IkqGFXeEYFfkQRLFX5drsg6AMEKhFl\n8EQOwjKQBjK4HT2f4vT4b5aHjEJ05K9SP1v5aTcX90VaEP5hR0OJDY8zsD40NbAozDPvBHZFX0ED\nIRhn+i/XVUxf4KkXcZ7BGUHiQvjXmiD7rd4O0nP0t99gvs5eB1QqiK16/QSY+J8Hu63WZWcdZZAv\n1Bl0sb7QjEa1onPN6MvMm284XZNYPuENoTvl84tdVpwWTTy6KaFjMfpGvs3Zw5rbRYjDqMU6FeLb\n7tSZ/ahWSGlsvFIWoqELhastLHLkIeMZyt8jlYUTAGEOEEraoePUOpjacUg8HrSpHie81DOaay7P\nAAzT/Is2R6begRrTAGNPq50SNgzPNmJomzUDHxlbuHeJYqnJzbTNmu2mm/QNIY5g4T3/ZUKkVv9Q\nrDjVCP+lEG/cEUycZ1Z78nVFuQWmcsM+c+assi7pL+uhWZzCPQizzj2hiM7VoacDeeG1IZ5IwMq0\nXp2/giop0Ak1pp75BsLEDXdzpcD8l6Gf+GZorCsODJ9BfSE12ihwudD2D7osjC/C/bUYdsrC/chx\nlQYFtNBnmCnTwsSK1xoevId8Y2WMMdNPuOhUUHqEtFNHL4EK/KM3VZU+CxrDDhp/Z7aMvgsweO4e\nFmHhSnvDyIGqCB6yPNMXL+UsWckLz2OL1rLGupkCvcfX4pwo9bia0CTK1ZkU5mrPXtvJ8iLvH5ZD\nELwT4RUG2uPfT9F2VS7xhdsTOj5USFtL68jcB4lQ3LdUwqMunj+M/wFkRUsc5Wo1Rna/htuyd3aP\nmvR4afocTUND8sbqWF86oE0b7M84KSsFKWn254Yv45b/7AGVXhW/zTIDhey6hbDDHa3zUhsRJ+sd\n3a7q9Kv9D7ax7QymetYPp67OmrE0CctHogPx89wzVtGxxpSFh+PSbv3u7EfYVFE5UV70g5dbWi52\n3Fe0kbBYQmCR+aJTy4hgxK666akTNVD8jx6UNgpOeJ9oLxbdi9gaCeP4YvldmkPNuv6n5m2SSHCN\nysHNq38Ri4NO/g8LNN3ZqRaQeeW04n7wNj43g2u7Q+AhVjNDn+3cUoMWV0XEdGhAlsvLAziOS8Aj\nAqOcs8PgfNLRn+/63nhr3S1tpn0oiSKA/UymFDp4XkFAl/NSQdSlZdl9yZfocKZ14yfbXP4naSXw\nYXdD9IJooJYT4vc3XhlNgoWURjW+vzbrQ+9Q0aDVLGwmTPWJcogLZSm4kAy7IhXy2y/e6LLI81FT\nbGmZxodxElq3jHE3z0CJEqoS+gsdBtdqC9QTMQaetDKYZvI5/vmZh3QKAamIvXVJ8TAgO+OxHgFd\nFxrvt+kVuLs1msjlkgS8mm8zfI4owlc5u5lmeVXtyCNHPLKHYAzzMNPW5Ai1OR6HoLM6UG/N2T34\nIXbk1QrwXKk878mT9EznzAhb/4bv6hoFEDgRIvCyyYweHxvzpmEfLiP6QaYNWWpO7iR/eaJHWw/w\n790hhWcg44VxliUVIWvozPbEuqHwxbBcXeC5Ksuxlmk8QdBhjHjrT3c76PX/AgEVe+DRzjzKRv5h\nMl6B13x1nZfviHANI6UOudXTe3BSkKBQatOSiKX4yGd35hKnuRYnDSNt1mYXH7lATfmjJFJ1TT73\nWSe0PhhtU7SE6IFs9oBDUTj2gUo4sKYA4alF58i9FJIqvxNGJAiLHJ8E/+pWe+aWwISfrECu9G7z\nfL+1k6nrcGpAegDvvNaMk9nvrHO5U8w3cCleTCuOdPKfWUgRuMapzh4NZ3PMrh8SXD1InQrZuBr/\n9wwsVObR2mdCCdXa+rhcQ78GUFqAhDlb/gDGwNJXRHEtPEgwsgr/EIIqHKun5yMnH9RkzScVLm+J\nhQtsd+JNrs4PPnSzdYGRKsNeWR1uZedxdvvmQuK6V9mJ1/9Rmqx/+sHIBiu+E3k4orWWGYdd/T8M\nGKqyT1rmVf0d2BrSPHzAKYdcRuxuewmDHbGVC3lq/yp65QOvQQO7N1EnY1gqIuYuYDxWjYKeiuwP\nQFDZvr5e0iMckylJHxO2Zkx+I12SyzSel48QzIAVnQmCTJ+X5gndrUh6LnLPRXJ6+tqzD9dfe3fA\nlb+egkye9h3JlbY+3Pjc+50z73r88qa/PpdTLyGj43GkhQTcr/5gW5n0AHoRaXiFYkNscs0Nos39\naAH1XRkvy408nbWfa2Gi7jxH7uI3+F3JkxicVp4XMzt+l+R+Dx0jSIyNA8oHaGXR7iODXmIVoCZV\nsxZNGSarntyxgE8l3LcO9FCL/iMvzfprNsX4JFDepRadUjspZB3K37Rtlr8GmaLhjZU3JZATm0vv\nmoZDKTaGGimpaBiPWWIIg5udEW5MYhrK4QvK8iJiuFcjIg4IBX3XEXi6+aZluEko16/4dzOkmd+e\nlZ5Dld272oEIa31In6knS3GnJn+b1p4s5Hl54tgnvGpXSISYPWD9Lq75SgxS/jHTRboTU19NRWhU\nGZYbeD0sh+mVjL2njjkPKpQ+0YFlelzdofUpHWOTVgDIGUgPQvZBn42WfsNJ/RV5TtsMZLjKLxaK\nKCX8wuFnxtCLoOUXBkbbosQYxnMAy1U44OrJu+0HOBqsrwNh5zFGJ/zk9/5utr8aQg/2aGimsg6J\nv7HyvEFEat6XUm+SLNRb4egTjBiPMHtEUqQzXg5WFNHpof6b17s5owPbAJDewviuC6u0+/FBomnn\ncjdCfOBsKr5oKtdJ9G/cfWevYkjMPzom6RgYqWKsOT4oXSsridVr9YSMbqMjs6TQyI53UUFHfVrF\nl0ryDtX4aJ6oq3I0s1jkTBQK2SVIvmMqBBreOHIPCFKB9G1cVT3e874jfndchxKWHYKOtVIJFav+\nL8Uo1/AnORfpmZ3MT04TOIfAJNO2opY0B5YuzT3m9m+wiD5/zMo6PmrcJJ3WVBY227wPW7hMWNNn\noOjAzzCrYiiO0/jDCB8OvnLChzLzTJmbwJe4z3LzHUGQQrZK+y5Tu/hI2S0CbbCb5l/4CxcADGOZ\nuOemAiz3WmIs6bykPvKCJ3YUD3M4F2iFz0Jc9H30enm5yuyqcKJoLQU5EWDirhIaywUHXRLN0ibW\nopXtRRfHpNK3lMJsLOJLnG0zXZGCJqyTj3qaVPfuys0B3+EBk12yq5qHRl4wt4HdS7zjxXqETTCS\nDWmTnT4ql9Ls9BhQoHCyeboOSARvoJCyg5bUFY4+3V+0E88wVyH2mpmkwGMTO1U7hbxtNJeZNcQw\n4x29DNm1Stga6kl3x8cvgu6djzr1ZOQOVMvIglT/BJQsYwV5NRK8kEiN/JrcDmE4po5lmaqOrEEd\nHnLyIi24A9t/bIbw350lCnc78BGA1Sk896A7Q8M8RbN/bHcWZcBBVJXli29+Go0U1cZ6vjpF4ote\nR7juv/pOYnF6fJkTyMQwM+5vzXEOMm7HcWdYRkQ7D3BbHuSVrhMBF89SrP7kn+SQ7CMEvfEG9gkj\noehWcUlTOkAPgQk+upUfEQ1V0IXIo+XGVCHXw1HlEAli9rLRlvLn2t99tZVdA9gnXSWDnaG0xm8R\nLth+31whyvvqwX0YwczoV5ZcVxTocWZwY2x4rKKiN1sDJ5PCIH5NrEMgJS2of6yaSC59QyvehjBw\nrRNKaNn2j7ZVpchE7btRVq+TWFqRMEnDj6B0wiKHy9A95fPH/jFUEg44Wgx2iIrKPooK1JfFJjbe\nTFsVM//5ug78qIzr214qkcwpUd+Zda7rHkJwxj4C8LcySIdWlAhhrFv5gtSCqrEIxbb4dyTvJ3v2\n29J4OwnSmjFaRx+7TxM4bH5xZBPQ9Aa5XDTCjtMA25CHWN46dF58ljRBnuxj/sTwdaqBLwjLFC/s\nAkRKeGbyuEkgZDGkgQ2uyOxRytYfZgUOGXyYAlgT4iE1lexh5KlOeiAzDxJoIQpPoMWANujOCHAv\n0CCpwPRIDa+2RYtlmvxXnQ/d9rmV/+bvuLlyg/PZfyF4lTfQ+gT5J6linBQ87uSw91z63GevX3vQ\nqIXoRUlm7FQIt6H+l7ILegL0BuaK/5858vbFl7BmT0xi4xczqNU5s5sPC7Jc1JhCohsjVnHvfwY2\n8qzZE/wJGg/5VjtcQrrIsoKjKqxGlUmOmA+gdWpIsqYx8y3lBO3oGE6LdohlPe50Ww3ftoagW1cK\nDi3dli+FTZBsGvAg9jehYrd6aHzVfHf2Y9oH7wo5VVoihibkHkzqoQtIf5kh+5qyhZ+GPgQhBdpC\niJA246TRn9v15Fx0Zn4OzczQG20209azn2UqWQULiPUy0AxceMoKJoI5ebd/IcNXjzH7HNmZBafC\nqmkvrkIAJJ1FNjBf+O0QphrrXFi8bHblHGOPHvgNOuyzywWWqrV4b4ppE4J2k+8EHYdTLVKZZ4Al\nYZ6gJSjesf8kxIgFcpqWikpTVY2Lip3rXeArsRv4MfC5Cjm1TjSdZAhN82oUsfszt8WRD+zl2+Yf\n6uRI8rD7tjXtB5A6MGRMrj9OUEXOgZhE4jqyNnCg6ichcoBhMt6I2frqhye4WGXAEMLI6vSDYRj9\nSnUdSngCYww1VjOT6c5zDafPzD96R10ddX1dvw2srvEC+Ie2efp5Qbmo1aa5lIQ57nk9WBJJvgaG\nXIhje8wa2mkKm5xLGWe4Y/yHPEpOwlPKyb3PhHzx+zIGduSAlzJSD+OZsJct2O03JrLOTWClXpm6\nN7E/Nv8Eynggtxy9yi27yj8r3I9F2I6vcGjNVurnmPRazqa6xDRN5XmvoZIxhaoyc22aS/cA2JTZ\n+yitWSfoXkzAXu6UL610+zmV2mfaoN5ISO0E1Wx5BXyYs9W4io4v/Vs5fF853UcjI07FeyIHaH/8\n633CANkUvI/Ls+GIu3A6u55H4++25ow4UvCUUjPyjgbvM08a25F/61H6L+v+hRkxKtflljcz2yFa\nWzu18dTrzpB6moutKoGhVnBhkISm1U8JTlUhMSkcwDMRjb+QWWk12wexPsUG6Klj1tbVZRO/kCWY\nBowdwm2TW2y2buml37GpNk8DTcKnOZBrPm9KGKJ8AlE+UZvGwdmwZM4ppd/KPXrDRTSAvtgLzqiG\nVO0RfMkmDngv6DSQR63QVXfQ7X1tI1VJcSzIp2FnlO5umBtoXaQr1f6iQLjZs8mHKNN1fbisbV3L\nkiGCuSBWjdyaz7i3nnyYk48bT0DCaLmk04mdPsi84JnyqcWa5HEqD8v1EtfmKP7KCxyqvL6jrGdr\nY2QrX1loreGJp1YQyZJ88Lde9IZlrVYG7X36FxaYuiTpVwyV0lodctAqii6guogpO85KUTYtLiD8\nz6r1LkdsS5eJtVm1N0V8qPJE3B7E5O9Eg3rSsAZegNJwfXmz0h/KOL7ee+E9kESRKPAwzZ1eXpjo\n4C2PK+Lp+RhF9n5kn9ahWn98OsYboOQ/+Vlg4ObgQeIu6hzKJ9jgtuWxYVY5shh7Jrt0uV7Ozv2e\nvnAZTy1CG+AMaHYhJVCrk60hH2jHdkHlRGewtI/rVzCQphSTu76+MqrhzPFiuWNwGvg6Wkz76LLd\nhfcCd+meSIE5pccdbl+mARINHJz0MJdp+AN9v2UrsfZHTUOOa197dKapTQboB938J0Vm4c9r5xEC\n0WRR7MoCZSLvTdcX9g91U68eqZ7aZgO5/oJqod9jh9AZDcjOZ/IZEEUBdlJN2ygo7ddcNiCIpE1/\niePuIMRKEXOabn+Jezy3oVmDxGLZMWCmCtA7SlmqKl+bDtba+c1jfk3rwir0Gc24AQTl/8/AiX3U\nhJTblGzrePrFEtjyEPyRKLCey9jkUXrRCnIJSxb3niKARYGPop2ovE37z/rUVgTWkWj8jruVtmUk\nXDa5ugQIukRCNmF4DRWY2R6KcBoaHm5VD7WsYZHIJKP4fX6X0xUFhGYGx2gj4VlXKa6ceqCBpmlR\nY2Yh5U96Y7N8lnKjQo/1tCXe7lQclT/F0y6KMMUbMdHp4fPwWIyBj8PyvP2F488jZKoaYDcCBAZ2\nFzAB5SJ9UtxvTWJ2r7LOFU29HmpRsScH+gg5k8G/675wfProbnZ3vGj83QtH1cvEl+BkwvWj05Kz\nu4d/mYBk6otvnaXixVDPAz/V9t+eNvXRwVNJ3mcfQ+DzZ8EIJ/yws4jWIkiSofX9OxpLH3L1BbA7\n7UR79P+vuAW2XLA4/voxPvt0BPlz+7oPINnLbEnB3HVWY4zM+EgWeBPAvZEkq36WAZhUBBNguE7a\n8RtT7QkNQq5ZyDg8G6KuJnpx0w+cCkCHtGWTV8maNSJha8Bnt78kTWeN+iarpU9NOyzxGbh3tniz\nfdzfLr9gC2z7ZDK1D3NObjjHSgBGOoPQ8zbZNjIRvY+3m6FqvjcGFJw4v3EallVzfNEk0eJgbrt5\n0rMp2kwHVSf/vfKqjcIHeIC8D8JG6DdmSQr9owY9/HqnlzR5liMglbcTS6FXDgmcLu+iYYFY28gi\nqFNSo1na61Urj23WxbaWilZLtC1U0TU7gS7GCuctgPqLDKFO1gglsegQThvzcuC5bwEwRlU3q91F\nd2p+3+bdCCne65OxvO0ehShiW6Lg+NgoKVG7qfTwiYnE81HF0ok/tcaZNbE709lTsFWC5fIF/MER\nVg2+dV7U6+rJIRf2tW/Pwavee5fm7VAUPC12UC6dZaK3h+YowDeF08FW2raiLFxqZjDBI7TWFZ0H\nlgE0OCIY3aNCGDGD5lhpZXuu5IHqEIrSKrM1p0vl+PZUNwzxcr54yP9/GvEGNovVn3YSTQaYB3yU\nMdTUt4B5/l/48spJ9IQRZJOHNqo4sGuVsLADOy/rNUTcWrlHcKgT0DiALq9k8rvybuyPaMmTKkvo\n6QP1WR0m668K4o1bSzt0rGulNFO1jk1Dp6cffsvGPPQdaLN/J3MNpUcjPMOpHBLyGTB5OqG/4mjU\nGR0byR0Cymms9sl3FH/LrcCbOEyY8FxsvPhszWsKD+co+nol2ncq/5AGd1Yj+E7pPniAvEi/hEuc\n4OVUmFlFYInGD4BlOQ4z7I+0hlGZFj1oOTrUsy1FU6g8j+6m1E2quppZMIkT8lgtWyT/mG+E3j+Y\nyTjtYgsbRn/oerrBrKpvvS3drB6tNlZMZrOZYn8xWzgC3RLspbE8JWwrsZom9BJG1f5mNF2P1cDY\n1foGVSlP8cZisVdTvgY03D/ummRYd74ziD9XcdWpWqYWeCk9MtNUuQRQnisPwsDyf6Iagbu8mRNh\nn4FglPLDfVH04Qx32QoA6E6bWyHKtStBKy4F067MkUQGvBIpLfKFxyXeG3zDRkQuj4joUnzGTPD6\nTFaSLk++kWojfrkMMF/LqnQZ4evnUMmoTH1Knr677TbVuDUTS2VQbRSGuo33/AnFJJ5IVlnIb7JR\nvdHAIG8g4zp0ZE/WmWTCIuOdEGmsDXsBGbtZJQbVHPez+8LOcItfUC96XH06NYNEZI/mH1wGdBNz\nUbnCsAnd/JUaDNe5hgGNc0aDcDfpgNVmPPTG5itNB1SjFzSZbsw+dqkjOYxUxdgxyqlcA2xAz5Rl\nnWuA56Icpx5LJgrYk7NaUiCvbiRjQ4JVAI3UQfibmloLegVPOu0WaahNR5z7gt93JISTsBZDOdJk\nkUX50GH3o+E5y2s5uQtEHNVzT0/VdOuuolIpCU5aoFcrFR5cuklmtaXcpJn6CFDQa1YzjoUaCnKe\nnpeJymF5dt8FbhIpA8PSuo0aBUq09MODdh/ZRaotvwLbYMDzWQIfKj0ndZV1nXBFjD4SQ+HoJ54U\nunuE4OZbTfvcC7ViY/RqV+Xkd/APQDwMfey+cXxqr7guko1eOqgR94FuW//L9CD1ZKsEvXpmRJdX\nBqYyUW6GK3akL3uIfIQCFtwyGi/BfEVu3rAbR3yirvflkC2o79Wa4BP+zh3tyGglK0Bvli6iar+A\nX1DA/dkwf4OqHuuG59dpNE4p/om4LMJXdl6SqXLhI4N5WxYtX2Px7ooR1NSZJl53yzBYZMOuzaF/\noaof3V2t8hYmlrfqUyBusIMDXGV41H5pi8vusj2z+i84D5mMz2c8T98Oa1CJKdCY5FXja1/TSWDt\nD2rNXOtcZgKzLQudXyS3jPb2TCMq3jOBycBDFH65nKAyGIFyeTKPn6cIAJDkBuSl+0bjUg8pILwC\nNmlAfw7DE+Eiq8aseLP9HhlVRm23B66+ryPSlSuUGIVmrtKKhWS5OKNDEqTMGEh4aw2sGNVVYvKS\nKbaGhWe60voQWV2IT9vuouA0hlv604k3/EwY0gODPnA/L93YelofcHaEhQEVx7iesFAVqq3KF2ue\nfKECodO8wfwW+RnycXayyuWlb2UnYwFI2AUUGCWpKShmVUarMlQKrWrIhTbO+g0vXa7E7zS+9fgJ\nWObDboS6oXv3rL6aUh8CdHvmYvR8QdSvfQvK+UvouZhsqTiycdhIO9oHLN5xkd4WWxloyOWerSvq\ng8/d8gOPzhBtKlPnJzkossrJkFwt5Y5+O5X12/+c6/n4WD4ZOddoCXy8i9kTQ3C5lp207Hh8bOmM\nea5HEgG4SoKB7kJtEIB1+5Ylct58MZUcUaHt8DP+uWNMSnY77vn+3RQm095pjevy0+URNb+7rW+4\nf1D/G4xH/mtDeKGQGekaf2e+KUEiKVb4PmHoTINrx6Pv9Vg01K5cEUcjJeCDoKZLy4NJ5cDzQSp0\ncPt7sgk2Up2jSOfivtrO0Yt9UzS2JK9RnBrxR+jG0sE8Zbi0U2UceMTAzYtt/pXz5RGbTXlxns9a\niforlRb+rHpcZmBqUbX9HMaGj3A8EC5aSERwk62OvM48On0A0lfW7ckac9U7bI2UeHUVkgbsLi2Q\n4mCjKZsKM/64VwaiUxvf9D7mLGgyX+4UWKpzdIXaxzIjlaWixYOcJEkwDwe+8BIlMru9C2uZ9+MR\noI4sbmHJOyvASFf3FlN2zZCEFPPuHoiN6H3y/IZd82q3xCaLNiMiNxMCRUgIHFwWdHt5r0lcTTdU\nh/TssUxGaa2KzM8lEo7CUkgMeoU8bWjB0DkaSXtusExrM1uNSd1l+eZsOMX7qzzJPEZeCatCFhK/\nBkWBpVm9vF4v3gNfhsVPSfkH1x/AbGjze0ZSaPJiPc4r7NcPoFZE1nIOIBABM3sJxT3mv3COVn+M\n1O/O7vXVwaMnugQOegqaROMi5zZn6fGJzhh8/8IIifmBei7ylRRqhJaE1IqGvLY8iw2CFgUbCsEJ\nQTppgPJNm59zRAa/4LWLZvs0u+wssdq6yRTOLomawCTb2+YSrSm4cBaef2FUqaY8z361WXyqdFpi\nCbmgzpCBcYWBcX1fLlSDN0FTptFOxlVLEmS1xO2GF472l8hQLEqEV7vfJvno+Z//8TjoVJ0mPAT+\nOodKgQ7+RnJBzAHC2bdAd6Wr5Cs1KYmxfeO1w8diEQk+7UEYEUfqDWOnhHM12DPdhcstSug+kJFe\nriF2f+ULJp0BKy2kJ/JJPAGRt53i1m2+71io+LzZha+RdggjfDKJr8EonB3mJTv6Ey/YxtD7/aPz\nsM+MIrZOFx4as9lBSVDYwTBZMvxLWLSdJsX/hZ8uFDZQxVyFQxfvrth/I158LUm56IUJcIyHeitQ\nJFFKCU2sw7McobUMR3H0dnKt749a5TFcp6Pt9OOnS0Kj2ZJ0zW0QRSFoUjeqWSlfVCVDBR7r2BpL\nG1tjy7Cqfqv1o53HItNjtOM4y2wZ53IpX5e+QjWiKzzYm5bi9Zw0sqCkhWYea/Ikvaaj5i7a+N2Q\nGUDekF0yxvDgpNKLYReqsEnViPjfOthZsiQ/ZF4f5FZkimf28UGqFSCYBhoyAoZCObcuokDZHSc7\nqbD8R5YbQFNmIhBTfo+LwHmZS9/r6GTAHKzt3NdOZJ+BlaPdFo9LoXpZFl7BISoGQNZp+cqJmxMX\nlElx0u0GPPHTNt6ilQWCwLZM9xFAQ5dH9aplVb1fFAdsjXUEJusNpQVa0ohBX/MlRqEA/ok7gkYU\nRg1Sl+gij7mTVCyaeKWlDR08H+GjsgnqBew6ptWyV+BLqxz1pIwS1TPPT9g2LEF/AXbgalw06Mhr\ngWyomNUgaddL15diQS7eKVlYwVtuO9Dio3USx5ootyq/tTQhrjkS124tYNG/4ozFsQy8kXW/28uQ\nVj60rTnm/QkMkD33zu8zBwXYOZ6+BhuSbsTph+WRnBagf9hxLJXfKYBbTirzgFHDPcrp6unySw1h\nXerYV26lMrK/9VrkVxxsC8LW/JGxQG0PHDl1cLs6YGseHZQa/ShX8XE7AtAYkJ56xfWkYduswh8s\n/xwWm/i19+VTuedahTPvXTRWxxvy7nbn2xV6LaUFixHNVy9k8lKLRdXzpNX1zCe2kB53fgz6XHnL\nxhN2WaHHuNFzUWCv8NghHah9YgCVwcCYh8YcQrqbuhpjVm/NprIxoZuqSuN1xRy/zfwU28FCMI0Z\nb3PwLG7AvfldFgTZPwBIWcODxzP894mHaNG9itsQjhW0ksSSxvYweLBofWtKhxFthCxXRjQYQlAo\n14uDlf24ruW2lki/ARokBEZ3c9WOn7xG+8a0XIAMh2Ze32MFWm50mba6Yk0jKXF7aZbfuH0MHbk7\n9U84WW80Rl7zWp7WK3mvHdR8kaFAyO/KFGsmPo3QwmBX3cmq0huPQVvvq9BjQq8b6DVoR0HRMFh6\nTS6HT6Gw205Po+wLRbrwzwbq6pUVKfHCySnZhHc2j3EXi1QjMy/UoGuW7bFHDALulwEzC7c4N1nP\n58hDhowIruHJ2UgjnpJYzV99YlPGs3RNfL2D5+uUFvkflxDXHnH14Ay7+zHIxr4HvncQGHOr5Fu9\nhSc76XDHb8pIGd8IdDD2aKLshPMrNF7ZVpt0IS/ThWkjpqI4HAwa99Oor5TJGkGnrK5nXCKl/V4U\neaSxXvHyD26Ry4NGBk2JasO8VqLSOVfuemwekAA795kOriGjdcU0hRZS0UK+YZIbt5M29s5xxQvn\nZgNF6Abotf57E+YP1F1eVCsopFPKfvATEpYTvUxBFxW4h/29TjMvkq9uvfS6ys+XhHfCrVIsAwv6\nr1aIxORiIZbULnlflxEryS///gUFpreGJpoPgLIzo848gKdf1bu+I5g+bikGAFcVIi27P74t0Q3D\n2+8X3z/i+DPkeMw0IwTCCxYpl/lnyV84ZlOjbvO+yak1dW85HmcOxI+Yx4X/aTWBxL1E1JUhsXny\na+5tcHCihqtH9TJ73Dz1Ctb0OQgLEcfPmziIrLrdgcEZv5fWYBjEp1PlCpqXnSKJik/ADIM2x1ZS\nwTuWTrBZXoTUnBmLXJvXwMOS3iK93JnKWLmogkAwQfj4NpYV9rRnNTEG8OtcRO6x+ScjxM3q2WcL\nNxMiwGOvrqy1PNsk5tqJrr+C/vX12LjRSBmKiu6xD3m84Sfo1ACMuimkJwSHDqd1FhpqLMWkEHd0\nTlg38sEgiPxPzQX8nNNDU+AP4ONfUTzkEdOKcKZiBzccH3Dh/3hMwpWY37LbN9EhqqQ6iS69/Nff\nI8jj0x7Ekmf6ZhNztfDvMTrHdMA+xBQdc4cL3BT8LiOLzDV8rROTTFwn8nHNro4jnAUqYf4sOABW\nwXiNohg3LLOwTe7gQpSThqCx5mSjmdOvwSEZXlSaciS6BJC8lgM5zJSzOURYOSMRl0CzfSVfiPjL\nl2lYdpYudLJqm32t+mntGbSc1wCqRy6djjjhFUadcHGBtn7ZMpcsGXeZ6PRYLYuWEiFrcxdeCBSJ\nMa6nR+aAfqAll8jQGr/c+1QtM1fgbtgUdnqpw2qWuRmW6LDkmuIxUHDJ+RS60L5zrYrgI27cYpEK\nUMcf/Dju2oqap/yP9KN2nvWiK6+OwAuvG22RDw7VIX/YU/KvVgED17M9VrSaGN8tqaHzNTGM2IDV\n7LGeSz1D15I00bC7lsM2GgX1s0o62Iwj6j/6deZ1ZiCwBtmmGzh0KCdzK/qSxCMHjC8qBAR9tQhk\n4mPouLUTQqh/4hTq4ku1SbVCqI3ZkjKytxnuhq5akCqQrq7Xx4JIaoeSH4sVIsXN3sfWGc7Zdh7T\ni+pQhzqsbkDGV/HO8zi1aJ0mPesChbkgZCI74tqxqtLgFFdUJepfQtEynJ7h7I8ZkfjccYsS3Ohl\nNdLTLxug/y1cWwWXQSU0L5+Z5ElHcoJH1LfwaUMungbZ1U5u/8Nry2jURK8LFHaLT/yRSn4Pg9fw\nuejDkeRSbGy1MMesbWXCO/uT8gOA9JYa99/xwuim3E5zGDUMaJWKg8WBZVyKEpY+KGjBFJOUrtMj\n3rcJNY9d4slEqcn2wDzuKUIcttvsC70XG0awDYSDQz2CYfHkWS5/uSF4ALpgjLcBzwC048jZUueV\nviWS5VudzFvxXLkz+NbWjjiE2B1O4wAGgrcimGJyiRUvU1wynIl9r0Qqr8iOCQSA/p+8qQ+0ZvY0\n8OWok9uq4V9RixaeLSckAEEGfom+KfvqiTv6AE9kw5848t2IU1HTaOCavLmA4A72Vd8XeLeqVW3U\nORuyyYkVjVxZLFIiWhx6jaF1/WT5jDluydog4xcvKVb1cwhxfvI67EmnSWsmK+xxBxA1Sdi7WWnc\ndkJLSWmQspe6eQDylbt/PkPSCYJz6mJ1PlmhwCT+ocHTX24eu0oRM0yobEJ+3BSUeR+k/u097WQl\nwq4+Q2wmmZFNmiX5L9MdI1REqstsyRBeZ8mabMRSV3ztx9WkA0kiru0Z+odw8re63Z1qNv39K66I\nTndTC3lMVLOU7jlDSzpqlgvEx8YKdGwtWR10ffvObGb67Bs39n3fup2O5Qi1hrrMjj0BIo4In58J\n8LGbRJzf7MFALj6nevF6KLhs0HBXaaZal5m62IjWRf2V4Mgj/ZGFih8cnTIM6QHcU/FgUQFPePxJ\nUFklzOMkiUFOiXbKDmaG7rsR9wcJTuZI4OH2Bra0GYY0KpgYcjeZ8INrWeiRUHCuEdkTH4UDhyp5\nkd8qBv1XPDMPgRjQcQXR6su+W3Da+OSeSSDEz7Jqx0ORWQwANUskxJVyC8b+ewdldz/8gCmU3jLn\n2vZKZvfj6KayKRHK7FxWrJokhNjnuKUgWI84ehgXQFuuDHRJfsvH02d5LM9+D71xfG+2+9DfEDEM\nzsiw5dAyaZX1pVpkXQoCukJgESE+6q1hKi1Kcz4k6hy82Eu/uov1cLMo7NeNKQrZHJ6lX//AvLfO\nTUpHyaByz2otzZmpVIAOL5/ycXUC0C07jfBxvL0sQKTQ/J6GtD+DUSWCHZNSFNqTz0Sf0KmVIyEQ\nt4myxo0muliPnbEu6LWT/DYOv7SzJafk1TWWvnEHUrkRmcqohZZisBgk0gIpe9nRRsFcWAwQ0rZJ\nr6DiRpm0z5qDe5QA9XauzWq8kyavTYLromTgMFc3Y0S0m9YSuzqOWbuo1Jb6MGD0y4CrD4Wos/V1\nnsoQwwLEOtso9goiwNi2drd9k2vm2wmYUewf6sazlvghzXheJRjDrXQIclJ+sQx8ho5y2EA8Ic6t\n0rw9KrHa/tlPwPMY8w39fnveTmcgywMtLX7eEIoqb4HpKpm8TqXczal7spNuWhPPe4J8DTU9T3Hv\nZFy6kHLsLwI97vN58c1TNYlnFDCCOmFUkoE97iNuWXejagNdoAKEE8wtPSGH8c8YhdCepyPwtsN0\n6j/dy7KxJmuxggcEYvS/1HBYgQ9IQTgGeHe+RJtjU0abY0fAFTcMKKVkS6VdimguNoiWsWPhDf0T\nSQwbwNsrU+9Wtk+St0Ib+B9D5sjQuAl60CS0arfZtMR1ZGkp2AlwqMlXL4vaFfD6+0cv26jC0RcC\neuQ631uzlivVyMyfaJW2a9/Pad+6aMWDv0fgd0t6wS3X7Vw+GHBo2jfevvFiiEvaY+OWL3LXWfDe\nWqMN0yntP5YqHFz1reseiRFn8klauOW63/7kJQB+WG7swSJKND/JGbeQfPCFMEOrNpHoGrVMfmIr\nViTWD9s/E+x2vSdqInLC12+lG30LYxhcaKGGtog0wRMOFziKHHGkxpgd6cIFalUPDVmH8D4Z0qYw\n0EmoZQBqSKVUt0ZAC6rvQUOtKdJHZHubC4++dutZAVZmAW5vZrIf5aPYUYMG7yyuExnDIBf6o+fO\nUKV4G48uKd6r+L0b/4kVosCyhh8DQ5xPibzLg1awGZHznPhqhCthPUNnuweG0I5j25iasRN4R/se\nvidCKbQjy5M1KyhWL2CFqpN+LIkJ4Bce4uGoB8fJ7Rex/UjHYfduoWEsh7Lz+GgUto4MVUyVg7mk\nsEZFgT0oLlmie4VzzARU+ngPfgaDftJgrNaW92UOpVa1AxvwLiIJCFPT5oNV9UpDfoEBZnmAcFc/\ns72pZNIMZ/6PBd7MnAAE3JJbkIUvr622GwGoBDkHTSTzCuTXdcAmpuGNS6qzrsglL8GIEnq1azaB\nfLcxBq20pyiPaf5WzT4O3YJFPde+jrl5bIi3nQ/xIkrPgyaixO+9g5ws+vTuYlTdwV+aw6Z2Eg4L\nwTCBB92MFE9JDAfYEFsazggJ4c+CFEGftfYuh6XosmP5Fk2EHNRIzIy1GE0uFYNCr0HrKxcDU8Gw\nvwNinbs1W26C6/mfEoCWGhtBEgXvy0fxpOqlczkT3MzWVB1H/3MDHhQhbdjaKdZKrhbyPefTM4mn\nRUwg4H9UKqMMxY8MpelKrUSjY5Rhn0E3IibFJGNmP1Km6DfK6Bz9izzj3SlBM2tuyc/pK8pJPybn\nVY7xZ3bAQA9TCSrYluNQ7Ku7eTeKTnQFanDf+MV6WzCmwj/zQon1Rytur+gV5eyhsYV7rt7bFu7h\nYnzt9cTUCyQWzC0jEWUqDg4dVnDKcpRaT4mZghot5rDxL+LgRbGj6bzvgkMabT8xpkNdlGjJN5n6\np9xZNBlZS/KMEkqIjAI1tdGO29hkLd7oqYF274ELPP5l1CvPBr1u0PgGilPa4LGW2TNx1mBux49h\ndqlUUJe1nIq28DPuRhe/YqGf4IUv+bihFqfjdOoPzEDxijtuPjf71rL2EOjqhbOBOoJS3H6yjqoz\nnAgVC1go6wodCenXIqAIQg78k/lP48fYaqhu4Yaec1dXXV8UyR4Zw2pdUFtBABUjWJbl/a6GZUg6\nFQ6HA06wwYXpfwivS5o95dfQvMcshAMquaE+Uk7t+zpPrFxLnTITOGafA4+vt7+zSiC+Nf0FCxTb\nMD3JDvplk0ljylaXpR0/mYid+K6EEN+gcyb/eY8i6/xTRvPt6GmdZNHeibD65PVZ1rWqBgXTyM3Q\nq3IIpyPJkJzY+dHBPQHcnUE0Yn1Ep7IXmnIy86737wq6h8ed84H8QzVuQtKAjWD0h6Pdq1/8VWKH\nQf6Srovz5Y/B/hEnFO80ED1zrw5kP5jGWIK3lzHgPvOuov0d34iKEWXeDA1xSD1h5lLNSBvtMG/n\nYgutmfLDuIKlg5CgxoWNuDOxK7CQNUvrtTlyRBS4cdzErCBugBmCyvATG+sl0iNPlgaSxHyTegVY\nCF1lMIotYzUCPWG9W2AIfo9xEq4BInp5seaDZlWAueRWsSVfIMuzGl1plry/Zzis6CVGs0QpntlQ\nmXpu0lGftlcasJEbC/EZNjUkOcZvVxNtpZdpyFKxmmejHkcvJmbKiZt61rr/Y0W3No1XLwbUfIhw\nXObmHdAFsLR98O7EhfpIs+e2Ii5vn8lYDmRa1gYK9IFj6Ikcd70mI9RSPhgpQgQn3CW0vX1DAdVv\nHYU9u6ThKMw6jlvFyHneAkBJ/NueXZenXLAhy/NmfEin02PEBq8MvZGes3LvIR6fSlYm2JGR7hcR\nscNtTbmuyI20CfzH3330djQ/hXf+61PlvpLlebaC6yhnnSQHSITI0pUzl9Ao2chkGfLIv4lkarzf\nVvGKA6bR4cLQ7lfMSb3jiAK/QFow/pQOHeoBGpiIJKnyfBfm5svJ35ns4KrF2u9yX68kHNn3GzD3\nHgV/iy4tNWUmkFYbPbbXyobnNbXNQtZOX3Rp8AOG9/Oo2SEnX0DhJ71qKmWpcbp/1BYCRfkXHiqC\neBMAYFNqIsb0UFGb4p3NWy607mqLirPXn3hFmV2MsgJ+JIeBuFIfOEt+uzSoD8KC8tMwqJybtYlH\ncmA7TusUFo2YYZJEMC4hhSPr9Vf3cxQ9FdrWuhoeFLtW3XVvlHvTawERVdqJGI33qy29xmhJ4nz+\n7/wP/l+gt5FG93Ni/8IEm6tB4obo5u0os7Xg7gmEy/6HCVFtfhNkqZyn4LTI6fi3wnIp7HIJWPkw\ndHPnAy7Za9wVoP70xhJbmtieW3CdDLEwW6k9qRmo91m35ph+NUrp6it8IEB3jqZbiqJOrGid/bGt\nDRe3ZwHQlGMqCSrGYYoQkn2elADRgSBi+SEBmIS969msvSUdcffrzFh1zgziOwKYJ7A+zgPAV5wQ\nmRIYCaCueGXcq3+Y3dqX6Xz+q2Urhdjug0VcDF4LTRCKJ/z4BoxHnhPJ0Kg3E/XNFOrxbodTy+V/\nf60jkELut0u9bDLnWv7CI3wgQxfZmbDzWDBBq+CqS6nFL3lJI202FIRh8gHqVyCn6QXFS84Aps6o\nsVsDBM31a9sYV/0IJ2eoJXSJWJpMa7JuEJj1QpCWgKPuFUqL00RmWetqTT4XnPXnNJc2l60XGhY+\nAsHEmLA/EUP7dssvL1l19DmPl1664WI9yN8JwrKMKIQIyQpp1lqKvA/uD8KUtUSf230Tt66HgLB1\n4j+idT++O+33nL1aQTVSDABPdZnV8MsvJ5W0oJhM5T5tvoPxWS/TY8Ok/AcSZOzeVYeGdZxwfQ2Z\nG1fYvu+0B592E4wGHMgZbomABjWALpDg+oDRscuswztBlv34wRiBfRhVq0+xjopYKqaMfRrv7Add\ncCpEx8xtg5/R5o61oOJlc15EqnvaFBqF6W1GW9eHl6mEvxDHkpVbvS0Z/XxySSsBQ8B4OtJjUiJ/\nLgEnTM87J2olOEnHHN/z2It2S/AEBFqRaqCJTXLb/vXe6gKekLNSu4qO/5RJpTms5R0vX/nwTvkl\nEoKqq2fRO4WVPGePAka7NO6i6uTxfoUXzyuckHg1WMvjj2uoW0aucppzCJ18nGBtTTqK9/hidxWo\nZypCiHytpCfX3S+v3W8xlss9vPeb8XoUbPytxfgNsJhLql8YMcldO5pFm0jVazvHJe9caPj65/6a\nmQNi5o5KGRI1YrgN37NHqaYSj3ig9w5K5r1vTpTim68ZUVHS2B70gveIPxtcfJj6MDjza9KDgar4\nL2j+0oCV7N5QCh+3eXAbatOp9GsqEK8NyPLDCMsTtR2UVyQpbKmXt/mmPW4E10r+zzMfJ6dDL2lA\nedhHtsi8mbms9bRX/Cb/S9SduVk3vefqeBSsK/lCxd1Gm+QXnMErrXxnR5MXNN9L8b0mosSL+4s+\nEiiRkZ28NL39wlIq1dpcgq2SObgCPTEHfwEkBROFvzkMC37TQSu9S55uWIs1FuyuXNLdBELb2ESV\ndDD+vw0deBrYhbroR94kQgadZshZY9xcmMpkOPQD4KJj1Pn9KyDfiFj1taahXAewxkfUfjsZLNGY\nj4Ufii6NpDrTkb9+WFudZyVk8IJKiDgggd08rG9vKD9IY3z+RAejotDLYRUnJHNKM5vFuzrQceYI\nE6Tu0LILRbrMcJ9tmkKRGd7VR6llDLUWRXGQFI71zJIuhxIVnSw6K2TdqCyvxxXuhHR6BrdlFIW4\n9RvXFMvEbB2Efao/7VnpBqBp5x2b5m+6iv59/EKuhg4u4Y8peLcZ+Zy2t7kQ4FbI3hmXmVxnqDkx\n/mkTxs0WH7D6PwoVvsKwBYnHonDmK161cFu2IMNNS0kzTM1oX+QFDdm8eCu60xr8VrnPYbIBO+4w\nMkhpp4qJ3tFvNXTiz+bKC9Jhmt6A10MXwDwgHUfcEl/+8zM2LF1wQIFtW71HHyjlTrl8ezgvRdIL\nd/tBKgK6FOeBmfE3j3rqlvTrC7kevvf0QS9YvHUUEBVwG/Y/waNnJizM2KZTUGRpTQrNJ8b+y99j\nepvmiFaaadQMB1pMNQYgYoxSxuEnU15ZhjWo2BAAGL9Zr/ffyHkHoBcxpYlz/iI4IXPrYCGEhdQp\n0AUwN1/o0xWBJJQ4rT1vsZOGbAMTJIKFZr0UmRKDKiYZ/n20BZna0F6r+KyX6lQ5I8WjKWsQb0Ur\nywvSrYTaMyFHYbzNuWm5oEAQ9Xz7DewoFdbX4fReQhA197aZ9TPNlFW/3EONWP9RksdrMk8qILgP\n8fx7K3mt3OICfTfeW2O9P3/ge2LbbShr1cNO7VAR6H09wWhTRwTSxYTIXy/bStPGX5GrfEswk/CF\nU1VpgaTDux7IoLgJ854i6sHqVnUtv9g/yHrtHg1maXOyWelyjK0Obe1cP+98aWZkOSQehCaJ3Pdf\nyDYQXgOINx+M/oSZrRSgRxlWuoagwzJfNmX37nHCfzajxk2lagYcEq8gAOWe6qrQyj1YyYtToghK\n4us7h4un8UaPqBlfdicmryRXwhbFdEKcqhJiCFfpce7jAwWJPjIASAEwvs+2c4dClq1d3impKYP5\nRXndnYPvkhD5HHyrHqc40lGTvcw2HG81JeEuWRVQ29NcOrYxAdZDM3MqajlNFm4KPFJ+Hxkf52F/\n3dKkvR8cy2lpV25ExE13xr1Fe91exh2KVl2IexsicXXmFFg9Vp72h8Xo01Q8Pket6ShJS9tPEh2W\neRtSyo8ZESXtb/eYmlS3r9eud5juW5xJy6oIhnMMpFVJ8l6uxv5FaAiJ1ou0EgV0ZE2aO4sjYXH/\nlaZjJA147M8OsNHMxQN7BRS7WTiZsb/FU/f6R0AEmkkVR/90sKRYYhbs9/Ms8t9vXl9JpWoAVsGx\nm9OAOq3DbfkYT3OO7YuerL1WuO8Hxfa8GjT6+tX+uOYNjyXqE89/Xzuk7nZfPdUu6cuCeOv+fr/I\ncAw+XUXFY9i/EIRBDRjeI1BGw3CRnlBTE7UUmLRDofAmzGNig+mvmR4GTX0Oy5dUisE0269mncb4\nRsxmB9BW7O8baRCKKBDNVWCKwr+gmHtXhVN/Z1t0axbdVnFEWNr39f6T/0oqPp+FourFiT6onjdZ\n20RdryNEaSOdlViXMPAbNvHyEyRNI07lZrTKLi97KNn4Ow8ASDwEYngohaQoWBjBeyzKvTUYKu45\na0yUeuB8zIuY3Yrp8y6+QOoVjbMCKrJleJnf5FnOaLLW/l92IIofSSy1h7xZmhNK/MXcDvk24kRR\nVzmT2+lbkK2YQC/Q964uZCgsHP0l3YSIAdOyHmsDy233o0GjrgL+Tfh2dHh+94MH439aJw4utIjR\nAudhAMZsqLck2OudCxFR9GkgCsLyR9MbzZrDK01gDt94e2qTBEIPYC6QIebeYJCz+bpTA8Qp03ej\nDkBFKXUUn5wrXP8exjyoIpkZ81yKHXpx+nnRQ8t8REAa5ypIf/UOHBalatg6ZlJW/PQs3YKcYXBH\njpMLoQn7CQZpg6FcLCTIh+twsBvnEf82dwzciuzXY5IOPHDNd818QrYS3FGd8m/lytyweVcBWWfq\nKoyDlZvYKNGbIWvieucWEaIL/GpaV0nej6it6vpkx1C9mcdcpxygg8EwU+Q9TqebsjMqdMckx3YK\nPNUJr8iTsrX9migJ75RE6+w9+v/3EtfZC4hW9khYG4ehiG+M5NeYVqzRaSnGNxTsZOb+cuV80hpM\n5kbrEgdq80c5e8zHdush5wXifTorS0vHdVzUercyr8LwVJDJClHoXRguNTqbGzfRO0h3/SGvKfXv\neJAFBsonKZpRfnFNj6KXfSEdlPLoKKr2x0HKnjYHa1O2nFSaZezwMmf4wazBPQ2DvJ9Oiv4B+cSO\nFrAB8wovlgGSC2XpFWY6/J0v8c/0tysxdLZwUzGbu8dXxS/imWXGTMMPQdZnRxoPaipn2kWbYnTF\nnebNrre4I86/E/MFT8Y21DhVJNzRNsoxMZcsN+xeVxgYBgk2vEV6p2llC7JNVbDqz0KsU/V0rsyI\ngQm/Dv5OknCFOuVM+YOoAwiQreo3nHHdWbkeKYS42sw9rv49O4vtL+QtJG7863L8dumpAYndpX/l\nz1Gp8vM4OrhYt6Qn7Rephu5lrDK7nVzVXDshoC1XzCI5b+aWHtB3iy4ktbPhgW1yln18ubd3/WsM\nnWrccDeq78IHQn/pf1Q4C74LUgG1jkid0dyecwvMHbI2ps7Hu6/9Ythx+yi3qypwYayAF9fPpugj\nAGgFBNzwnSFWMu39vT/o0r+mz/sOype0lCGpF/4pkMi3rVRSG4O0wKL012MrdqPUvL8lCYvmJ+E1\nYJYQR1F3oyY8qWklcIMSIXeGynLJrVEkY8EVdyDlEAbLgd+4Ytzbm0tUG2XHH+r9NCOZkk/N67Jq\np9I+cnMfr/AYnJAzABJPqwC9dekyl7KK4usEpnjk4Jst0Fp+pfNlYFododZooqmxfvkKJOurqkwG\n9o37CP20uKhZzJnqTGNL0BC5/ZrvTabulqD19dFpDdg6BGd4vREAAd7Gqp6jxBTvNRQZI20d2BuN\nFBJ+8CziDWG2CsBdoGlI7NdjcgZdBsO7bvCNqHFa0FqWkby7BKVuAVekUAfX6RitgHKugIXhgtL6\nsKnV8v0tfhlaX1xc2uSxePTfYsMtMBEJrEypxsk7y+Exof6AoIyHBZiBvov/hxU7bSHu/nrYNAtZ\nJOYqBNYGMfxaAcOYVe2Vg/UbCHFlV2HIZiAy/gD74Qg8icJ8RjS1AGd7t3Dk0zDERWlinv09DBlM\nOe/RudF8dTfb1DI4g33vSu/OMHm8yscI3GVxGRciorqLX9YRn0ji9noSlSo9389QCFCp9RXOEtub\nh5gnB6vSUDvEZ+umw/C2GQsl7N03vY9FJEOftg3+o1uQb4q3Pcqa+C3kv7Zvxa0HYtc5N34lWXIf\nNnfbCOdcO45XUaPen+411pPcsCybMS7vYf2boFvZ5C/oFH2fxWLeYOEFJuoD9ORHIeOGiqq2yodN\nvkjolfq3C8HR3ywAan1BP+qtapDuBzcoZheHEq//WJnF/kqoQNkhdeaqUGZTcPEd+ZjArKCdPj8F\npfYhhpY4GrlPpFnwlw0oyYNN2yH9Ii4Ym1coemVDC2afnECWviSn4y8fQLYRbVdrdsgyIHaACUNk\nwyoVtTjt/lMYUFOOpEZgnmcn6PwT0vtrvcW/0wDZJFx8FT7Ju3V7FVxSoVhzWr2NgXApggby0G7v\ngaBBC5iIzSJRRAkwOibIhjQGupZxxESlvPAZfpeWXxnyA7YmEHx4EJy7vwEUvvvnwMK4pZ8RTQ5t\n/qgGTww6jntZ9YLCNz/REKPFSVaNFPCQvQzf2PNJdPe9a7OX+C3idY7WlhggbaCeWfsFQFq1n2pI\n1Up2Ju1qCayXN2bD25j0qONpeVV2wMTfA3/0PQvZ7NjulQy45kwFLhjrHKi1SZ3Lo6IsHy1W1lzz\n+T6kjyQDgHKEPxmgbKEePSYFw9m57IRBSB1lVL/lXhgcp3fV8iFAZbUz9vPdCXYkSA0Mnop9p9+W\ngXFiq9fxsGvjlhzNzacvJJ4lNuEZy/8Zl9ywYYRILB/hbw3jB6T+Sl7DBN0JfR623qilI/Erkl4b\nBmEHK10J5v07/+2OoHjVtND30VN83BbYkj0GCA3AG0xNTll7Mqce7tDOC97j4C2DJqkJ7bLpOw/x\nNzvjLevB+tOm5fHydrs1fHRGOLNpTd+tNaXzZJLicRPAQ3PwRCU/KhfUhD/lnwMquRemNah3+9J/\nWbDvDX7y5pZAwtFvTl1Fx9D64CTBMDRLvToJsHMW7TNnmchuf6e0UU3kSMZ7Qh6GBQTbWX3QM6H1\n891oVivzTN/iAvn7S3PCQMqWca/8EwEySxPLhLv/V+g2qU0vWgmRAwgSZGW8qhB+hKiyROe4iovT\nZ7f/ATkdIc/NU7F6uAOSfbTF5HtIKkHTtrRBh/GPODrZync/1Unq6XicDyUoFNdJO0otZpWg0UJr\nIm0baDbtDrMr2nxM3f5NWpkThFB7ogT7J6jP5Uk/W5gA92yUYXraImArkXpJIkzrMVUBcZYjVXAK\nby5IG+0dAnShjrYUMbCDCeWRqd23AQ+Gmib9SjRAvoyzqNSavj1SBCaFi+GWhUlDEzJRjcx8ucq/\n1O95KAytmC/bzLw19wV7dcHvXpYXenZdTj7NIqNvkMdEFQQ3W98i9NwAcYtUOEda+02qLkc78Imt\nEFLSJZ7EKE23BqprZuOH5UTGjH+bdjHnBephoFRnLuwZvF0sPVHLCQz6E11Kl8x67Lg7TMz/JMGy\n0QWWJno+6E233Lt27bt4uZOF4ridnseWnNw42Mojo2ZkS+F63DJcZlmjFOGUVnis87CHis7eVVVd\njVZWDDQ6Zn/wZ/rKAB7Nj8qRVs4g05fCKKzodda4WHnCVF3g3nZA47sdOjb1VGpJCwXqP2YcpkFT\nTAXPnPquxGaaGENiXmKqa5xdskfuw1Y4af7vm1MqI6lcPOF5TxhJ1Qtt53NI+69mG9IdHkpVNj1y\n/G16ztIE1JNeEtmB+BYO0mO2X0dblG9J2YB752FGSgWYV8EnXjP4Sxw5odQw6Wt5LGoLlfylOGcu\ngbhuMJQ7pgb21+gJh/ngTUpwzKK4Hcn0fA1ilriMz/e+CfZFP2IgWlQ15Yt6ECjl/QAX3aAyciLi\n2pcfzoq/Ic7mWuUiwcFzJPte9OngUghbbaNHB8SJIMiopXVGkfr1KtDxrZ0bsWfVaqkM++xgcUOo\nbMQ4UTmjeig/FooIwVWLCwUblGVHyWYAdVeIh3843mflrTKFyQwuXMISN+lQO4i+WEPWHPkml7La\nrjWlBEditPmyzJHe0W207fjznpN/km+Ne2v/R4elmY9pdqL4KL0ubbaOaZpAvlxlAisoaIZVPDq9\nF4oUjfoRR3053AluL3WEd8t1hWG+I5767HWYMG+De6VQRXGb0aE+8M4o/vBinyggTiXrkFS0wkPm\nPSObUf85seJ5x9gm9winqS0b1+5gIKEfpDNZNwf7r9+HUqvigZ8oPVsbEWjjT5fm2TgDLUbBVrT/\n8eMGSj2YLSsfViqir+717cLXHWH06yukH4WjaOXbulc7zkI4iHRX5DuvX2hDlEUCXju37W/7eyVc\nJaxXcJsw02ylBFhVwvLwRDiJUFT4s6tL3oofXqp3SAfLfm36qZJ5jjLjKeUwjot1eGA+NroRHqH0\nmgtjvwYrR5rVyVbWrYwo34eren6W2O7//yte0mey6VJb5UQPVQjQLDyFHJ8zSG/AiRjgwri3tDKG\nrA/0fUOdQGiz+RwQmrOjtDLah0oLdcnKNGdOuYgfRwuMR5kqO88aRVVDccmhnSjkmckLlEa3UbW/\nCCaLOdPOZVG43P03loHDBkump67PWIwSJufgTY2dzbjHQYWFJH4Q+HXVMJAaKwMREVUD4RfgA8lA\ncyJvj/zKyZAJEdF8EP0rk8ZsS+FplatlugSCfQVGudYccNSYpvVKtoiX82LcJs9S/HqsqzCrhkA+\ngDJEbI+8wshtd6KxUXstlXRaPBq/JYp4JESRJqGNH3q0MPWYudy5IU1Ex+Lx/WqW4Cyt6RXnulxh\n7qYgvc/1Li6u6wA2y1x1R9g6qBJDOmN95n40iDkqYuToeiI3oC54fxAOfE94As08xEGHE8kAaOta\no8l+uX4BdtrDoafhBf2VH9N+GTluvEe71ZT3DlKFjbKEsaA/9rj28XJic42JsPn5qkuf7gWNqSA3\nFkaQ68kOF/xwL8BFwUA4I1qpi84bn5o2gVQdLJJzvEHtIQTGmhCc685iDeCUbdbkw1FT3EXdEz7K\nAXzeVmsQTC3MSoefYgbwhcKSCniWMFXMwZCvqu1o0KOypwDjoi5M7wtwWyF1ssuZ/ERb8vFk1TKq\nAckwlJgpVQ3g2JcrjBwdIuAb6y0vpTto8iav0v/pMkDxrkPHa+5edxeg/bR57Dg9M9i6T4QJB6x4\nkkfyZ1w2jFGdyASCxZg+4obC4Xahrh5rvE7rpL/jAt6/JytixqGe85/NdmqycrPD3SpHj4HG73M/\n62NrImyUrHvAP/qdOGD93JyXizrcbws9HXLDfuK8gmZx0E+Q17Eq3ktdG6Im54bdQOOQJT4sbOhj\nwp0PIO/22O0nZVQBFd4Xi2gytLXMo/Jexr/IaEB+IOp3WfOvck/ycksR8uztlg5RC4mpYN3WvnWk\nebkIUPD5cYMCH55xQdzKPFCwCayAb18492wALyccze3xXGlUZkys4O/HRH1NCzgQIfHuZ2894SrB\nXxp20sVF6LGPOCfyBBGEGgpXlUGNgf0lYkUvh1XfD0U/PLpxY6Ms+fNecyGrWQ9Zboy4U7deDa/c\nlDarHQTyrSK7K96Z8gTxVpqWF2ltlrb64uQ9JW0doObxUxumbu3P+d4gfnwFzwxOKVzdeMyxe6ho\nV9G5KUKsBFPZpOaKb5eugVmH2PkBA+lWZFeHWTgOtJYCBZZFv6u9RSZ/ohBhg4bYVotZCYdVwtqa\n/z6XJaRdUKc7E7h7UU0qs4oLqh7OeCHJ9CIFiz6fOTG2ydP3O/+LkIHXj8M07BNjV1vW8hn0jA44\nf2gzojPMkX9n+D0g3kJXmDfyBJzwNG5z9hK2a6xXRgJSRNSGNPNF8Q6IrUJsBaTi5m3lrKedv+4a\n+kNlozrJBXuzvH3eArtARRpnLD4jSt5HAGRSE872rEU1XwbIxMO42s3NXr4zBQu92AdAFd6bfp8H\nb+zjoiUSdpFuOIqfAwt3fxSo6+1wwapPzNlUqHhMfKTiKqOukaeKPDs4E2PP8jHXvWzRb2W6uJ8Q\n59Dysnjtz2acTJCJW5hkHDIlnjwva90WF8hnAXeWRF1JN46CA/Rg0lzvNiHK/A7QSJo1H+8uRIpt\nkR1XM8bh3jWFkHTzVyHdNqPl8PnAjGBM2Z1QeXZJ9UgtO2amnqcO2uhydu4FcnssdGAo19p0K1h9\nDAAuNoaj6+8g5By7RqQpjLssbVgkTyW2vgACzh9kZEaRaGbIVXc5EbiZ5jUniul3T1QSfYmNpXEi\npsmWjHWBONA4r1AG2GokuJkSYdWmkXcnTQrzbNJgVbhz5k2/PbdNRU9yiDX8+YBKuaeJO8r25UBX\nfErFZr5+j2uKwIwBpHVY6ca2PRs93wNUctx+wfT9BmhWV0KOrESlVv5+etnqOZyBBj8AOy3jNLaJ\nMW6hFuSWpjVJiaK2u3Mec+zcJMOqdTpeebSCfSoa0Jv9KeSoeHd8FEP+uA4+6ufZs85JJSTJ6YeE\ndD5VHAFVYTgP7+/ydJa7bnw+leDGzHgOlIsqlASMGbXtRLxobUDu3rtJKrKLvzuusyGTvByu6ANW\nFoi27fW3leSO/k8mEYEYxDviJtlzV2Ew4DCZwlCStk7F60g+hqb8j7JlX/A4sZ7jNvzGf33+oDoI\n51RkUjiaAWH927l0Zax1VnBHHNGY3/aEcP9cn0JNLWqXOPEZaDG2AEViXc4SXglF/zjYRvSsh4jm\nlZDf+6JLapKNFj/U6WOaz/1Q+jnLOy/4jwlbGUui/0pxOwjO53EiIb8+cuRNv6lgncg4kT0vZhYU\nqI3kiVjWCqaTVYo5J0mDy9VOufJyjis/Owf30YbzK8tXhskSMnVGCEYaXysqIegIAPK2MYigbHv4\nYgV5UQNE+eud1015tIvPOBOxwMZFGoZE+m6FcD/lb0pip+7XGQHKbLnWpuM0J0Wgyt2oHHIWuwcE\nZmOznDdt9PUrecb4M0RmzKCR49k+FFBt6PVGZKkTDAMkfCcLL7TnyDp2ufoPjXYl8eFikpZ76AyF\n0O8LbQMUnC0UuD/IV4loxCdPwND+BUaV+xpgcTJLITJX52+GBY3Jx9Hr10udTcpWA4zkVkU56kah\nUtNfcGDqHyPW9c/wdOsB2uNwjN+kH1WUsm53Gl6HdZ240slkKAY9WBm70a2L1U39AWs23CzTZB3W\ncq8nSDk+xg3/2LqE44rdfmqjx4dlr74zmxQFFwnzD3CgIZWuHOT2oguHOTgfrH5gs2jT8m2F3Ksn\na7VXwcQCjVrzGbUr88rB6mXeoiM7Ax1aH9Cg5ObBctrpOejx9vBF5ZDxray1IgUot9VC1om7YIY/\nVdYiLhpe5Id8gygXCI2InUDOPutyjOvW8Fy9xpQOZxxhtV+CO6VFfW5C17Xsl+wBOcjKMGHvDGga\nDDIUGcFGlg/SRkMWBD/INUhFIG+AHsUj8zdIbmx+mIJGl11P9RlN7v06g4LUa+/N8sxmbEpZ4TCV\ndgfWQ+O4OMNl0uOoqVFcbkk5KySct9h8AAiRe1pApC4TpbbFdrV4F01uMNDu9JgLSfjJBAS0Wqsr\nWVP/tTJnBDUHBQREgEwXmUZaPmhI7TTJG3yrXoVrmGoeIH8lJRFxDIAT0j69KTSQzC0DnH/ZluKG\nlQu4BEMiQZpzAf6Ctg01cbuFOx9ZJlV9SQVOt2LtsaxaejPLRRq35SRUoZmqeZvHk6kZnx2JVutr\nb8tHbXcf4jY/xYvfYEFX4HOSvaOWoKQZp62bHLvvIaZSQc8zzZD0dz8sUqUONgaVEppfuM/WMImq\ngwMnGFhZ0DpjWeDdPEdOvxllLjNCBrJoMXk0NoZQ6FGekTHCdpuNxIKZDK8PDSuh3pH4Udn7UHg+\nkCip0T+gk4au+y1JHVcNdnx4ZrQgCc/aEC2T/UxqPRVw30xYhPl9qUGdlYHqX86Nb5nBWaGQOpy2\nFkj66xmYSqUYZThyAMQWkV7q/K1NcRHF9iD3PB4KbAvRJMbfPXRsVwK1sSP7R5nQdxg+YTaUgLKH\nDnbPx89r3MBelsRGrWQJeEa5pk3C9bDfMcDWdA3j6rTLjl8ZtTsrkn+mjWhO/C3F3s6rMY0Q6Rn+\nGUA05HEwcQ+1b3I/p4fhvDdm23QzQyRXUY5EtnP1HeP5gBk/e1C/pGOr2xgZ1Gt5FcbFfx5pvFJ/\nnG1+MqwEwLebNnBzfAgF/bwPd6KiVEFV7PU93PgbX0q8GDHMCYW2pi10p4JVorjoZIwsHTSbH7/h\n0RWSB10CY8WdocmknRsCcU10+X4Epi6ym499noha9lvBByhG+opGOQ9HqG6t/Nw31Y7U4uNj2rN9\nf7556Lp1BLOQWsAVDjQDMgRAKMpP0lfriq2XYSglbcrNybGw0AEXMX6CsFcW8H9NPxXpBk3Grt85\n+m19BUp6TYd/OSiSHyDJee3n0PlTXidCCSqKWx4eIo/SdI0d8MZrW+5914zUD/oLyNPK+gmxbd8d\nmQU2UsCClOF3pUxgccR7Dr0Ux5C6UlZBHhoIRS2aDhZRobZFqzrUhmSxSHr5vamn4txkY9JdG0PH\nntWgNn6Eih5VFDXV5NS/w2Ogc0JDHow08+Dpgy73juN2rBZhn9PVf2oVCw8uV0Wz3NN3GwV21Iuh\nzbdb5gaBvL1+lOE63dPPnCnql8P6/E/RjCAAv0pCb09svITM5W623E7wVXV35pVGDycKtO0rANJC\nQViv0aGls9jehkvD+pNfUKog5rxHFMRxGgeUB3fAI7Ml1jLS6hzuKKqBl9H5kI02FSk0Eqx3sxWO\n35z479p6mI1+CeKNkM6R5jdFKLVcux2jWoWB2T5Ze63CdwAGjTs3QrXiYTcYkJONdHNe/fgs0VGg\n4zzkv7AXoIsHn8K5HqyqoW1X/r/x3Ql1Bc6mXkOmRkfa8iEXsTgSOST82UU4r4lfHCjjCLSi6Sul\nw8E/Aj8Si/TOh2y4xv8OmJmuKbQ0YxIcbZU5UTZyvwtJ8GapX2+DoPhmVfJNjPYFFH5PQvehmwmT\ndgx4rhZxHqkrYO0lOKg1gMR/24M0cGkpIyzMExAGK26SRm2HjKlpXOdwCbft4y3wtruYsLHuNDpv\nrhHUu1Akv93ikJ7v/ghFHVTdo9XGJZVxl+pFQmrNu8vD8mG8C3OQ2TlAVpeqAgCCRYX+Ly35K0a3\nhNoGqO3Ul/DkyXYbdwbctWpTC8zn9EBzNxxwtkLhS7psDn+TWfDlpP7Z2XYi4NVSBxVGgapS8yzY\neSP6L7TD5HKcQnLW3CBtWk4riZzf3thpYF7RXIs2t8iL53IdB2YkikGsMu/BnvPFFJHPF1XzpTf1\n1GAEUNn4rbgp+h9xj0odIY1m7DYoKAwduAZ53fF5TtaY1gklZfRtZdP0qJISM16uWVx0VPaicdJt\n8l9pE5rmK6VJV5bfkzz+2LeNjen2iJLIdYR/EH8nmjzGQin/GKIGlG0XfNknxNRKkiyE6KML0hNL\nRIyzOK34XYuE4ymmnZzgzmS4uNCtg/oB4rw4ZQ9Y06fY6x/M+Aix7Z58rE+icVHft8BMDmNIOKC8\nfkTIA9WfdK8QoPSfZ9P5RQrGQ5YW0d1wRWKqNIYvor5aE0MFS5N5p8rbzdGtjMIOspT1wd8gmJgx\nv6NLOSdPV6P228cpNZ9cnGr+8M7EerdjD8xUTBZO2e897RQUC04/6LIJGqfBFKWsgDGv3kUXOQ+t\n5WOI0tbmSVFDavJJmzz61GPMnT3MKugw6r2yqhX2Sv2A2P6cEsDq3MmgrbdWs4cvzQsPMclNmgA9\n26joYmlJsUz0ID14LLYezi35HMN/8znhYLYkk+iO1Mxt+En78EKuPjQA+XRu64aKTT5CeK+icB4G\nRDq5D4mWKRODlLhEcR4vJWer47kF7ZxiOPFc4h5TvQJwX8bV9+ttvSgdTDv6+7BoqmYGNDM0KrbV\norA4ymoZH2IqZevYvXn6gs1t83upmYS9E5W553qp+pVav6PxGbW4E2DNmFtfbK22PZjn+NOfdOnC\nZRnmbp0KjISOxN1DplSkpppMGGLEvHhS+99+xay1wpK4NXbskGhIBKAGDPQ1M4/JnLB2CLHZfV16\nmYQjktluxwp/AyDDJRPX83Z0DnyMATsm/SpFNKnhxuVcsUbnW0OPH15IYca/VfEJ9ZyQUJv5hS5u\nbua0je7G1Hk2mbj2g6L8ZxialXajFTc5kaTCPPOfUCYGlJd5UCXUSvSmZS7UCzs5qMiMNUzQiWfy\nN4N8YDSPh6mPXPDPwPeSihf59jWss9LgWf0b+r88XS5VsNtxbMWFnfrP2SFOStSXfMK2MSP3KA4p\n9vOyrwrXCe37G+PfSql2gEI5vis13IlRhYKXzyk4Nf9zHg/l5vWsR50JJ1ddhKx0YeL8cbiAv1AT\nlzqGBgZAOkMinsVyO8qDWgByqaptxT2sPOBxUaXx1ZoH6h5A3bjlHG0iM16TAZ1BK09X2pDRiQXP\nEeUGB/kTxxLiyBK3BciO5EwCvaTfsVBowIZyizCoXrKOrNeGzAg/E3tOfvwHDk37f535YZvsMI8F\nwsqHEHicB82TcoXVK0yya49sKe0nkMmLcxa92nKzKrkeVuE02y1f27G8gYA2JKmh34DFLfoAf42c\nFiidrnPcZcHRaiTwb7P0kRZqbZFb0V8OB9iDZV9qQq47ZGq+OY541WpW48zGqvLEAjH5req9LE8J\nt5VJU9g7kzgFlQVS7vH0yKnN6X+gZ/qqVtxLYJl6KtWDQw56F3VSxSnP6BXG5FtOsWc54oVxmYJg\n3dez6qaAnUYYagtXbljgpL06Z5uRChLxCUJc6O2wbS1wxckRA6wlVAPpxalEACteY2ao5goDytN4\nb79hN2WqDvnzQFBvMuZzYZcm/ZMNPXzhEnTWHsD1mqxhemlFhPGocUPxViD0lvgbYusbzoT7Ze9i\nmkasjH7XeUfF4Ov3bAvYlZx2nWoqBXhBHEiR+g0UyegKKyevU19Iw1Iu+2D/7Rmb51mkq6TRezIW\nlmmvYvKf3I/BCjmHxYqsb1fyjUK6p9PgNq/QjqQO25SxCLdV3eKzUCT7txEVJs7W9dJ616IFYBXQ\nWDNaViIKApw73K+44BusnPAYR1vhQEHO3MUjzrGVC+LyRDlR2UxkRbZgVxu7CMBVMJwUy9SMxYNW\nIodQH21No8Hx7ClUbssGWqFfF295RYSe2vKz+QXyC0jV6SrsytjJ/acQyYpkx6KSSendqYJdo1d2\n1QWP6k/nCG3Ot+ON23JWRGrFn7ucT31h8faPpSCebSMDmXJDnTEQDjpvaj6QD7Yu/51JkmHCN4F1\nrE/n7gHwgH31Z1giQVUKZwKRPxPTksPdzyCgJGXSA4aI8uXuOhBfN+xZr3tTwvSLCYLRWtQSn+x3\nCl1pvQ6nTXTBgxz79p7m8c40xp7aSa3b0hhfn+Gl8xdW4pcgL0loYtU1le2clNuGgmPG179i2/uu\nClQMjD4GD6BcbDzDFN/XpL1dZYglqIbXIawigcKxcFBYDTmsRXJEFTRn6SXwjrYFNLgfC/yUdNkU\nEYEtBi/0eKX3Wa8Lh9XHiXDmlQd7wsWBEiSYEEkjTTNzhon7XJN6AAY43NjalbBLcqmX5l1i/8b5\n1w+e5bzSmX0WHcyWCoThx7WABeHWdLytMuWx/fvk0uGexf1ytVbX9XaF3vziR0SYJ0QUSF7jYoUC\npqmOwDSKrcR995m9qI2IAuYp2yTCG7PvKdn4FkjrjlHuD9ycXdYWHUVR/WgZToqeinwTdeRGLCp0\nWuxVRjzkfFKvyPROUMnvRny09a25/wTETVo+crnXSjILyUWQib7habPmyEoQLS19e32CrXE3rbLW\nmoj3lJNj9vOsZDJkdcnDb7iZ0+KA8CeLMfm6G6sGBq0GFq7IcP+cwM3wzB3YrmjNQBsYzrQJMsDs\nCaaE+TlVAR3KmrEXssfPInpTbu70ZuWlwYbPGSa5utwno+AOs891LYQKTAKwcpio20sbSEnXknOA\nihNc/KO6b2ODy8dHQYe2tWc3+jmqozOQsNHtNTRd+vAt+2Nh7Q6+C1vTppWc02x703ZDLaYZiWd+\nku3ASFwZm+YG3ac0DnYfXoAVojQ00ZeY/QHoBaEJFYnVEuoergfIF/vA+2AYa9g66cZZ0uF7ITfp\nNDFK/Rq90btOenrD4sP7dYLLMFOonJlC7hAkJF9bviXGYR4w95entPxMv+oPFhKr/83KezLPclOO\na9drF25tp+Y2LRZwB4owHe3DFce+DT8VZbySR+mqQqShnb7WtuAyRLahPs6DDEEQmS8EK8jyPSXb\n8YOSBnxG7XuKnw8Lv56v+NONoGQwsgDuF5jfXRuKCu/9PeSRVSWqIx6tIjsBWQON7/sMrqDUXhTU\nP/z5b3GKlIrmN9wVF32x3RLsZ0xs+PeCpcnW4neNVzSi8e54CQQEII6q8yun0SBH+mDXxdw8+jCp\nI/hiG7Z+NuoPlKjvPFqWF8yqddQQ7LmB/oQFkrAYwS7cONCc+g+9R888UG/VJjYRWROlwD/VsMkX\noBwb54pBv2OMxZVFhN9946P32mF3Gm33ssSRTTlY/TPGveeiqD1FtepBHnRIQ+XAN2eP5cd/+Rn1\n/awP0x8ME09OdUhn0XGgIksd+AziSrA1GkKiikudfGzQvqj2a1uwfOseQosoXcGOIAY4V+krSmPk\nOvZXdc4/dvSxXfv7EOe/i5sAw2LCbVgprkmeemR7K/H9kwesUv1xAyy04Ng981gTa2Pw6XgyzlR+\nWHKApQc/FJa91wXVrNLOKiLV2ttSwXtyROjDdVQx0XuxHzTJudCumppXwifst0D7pJa1KWx9iUvU\n//CF+VLQsubHA0051h4+dPLg9073kxolsyJbdjOm+kZXvKWtLN92wQ3qa4qmHE/kXtW02XKXPm+t\nDOXJIMUAp/C1tRbhCfg6hhFK4lrKvnH3jVpmKGMOi3rELj6989e9xj9HzNC0+TJ/IjS5Liw2g17l\nFOnV5xIwpUwN5tJ/cf5nzO3bmA67ENfoKBK9XHULdImTpY60ZQWh0v6dyt+zRMcMRMbBqkcxXjOh\nd2drqdtPIcshuCuIYmcAI+ODGXCFtC+tjb+q2EE7wlCZiaaDYdgVibg5yenqh5ZR7BlG8+dnaZtd\nVVqTIdwYYFgSl21aEa0TIEX7TEA5xN4H7Bma9vYgAHiOS/YacTwQklxMDXN0FXGSK44neOurRYmJ\nlexE8qaugJ4Qo/MbKfF85yXvxrKo5cmFcI73AiJm+04vQkS//MNZgqJaCj18foDt5A131OSCS+yP\ns+vMgqKRoTQXCguDOCbv7oOD5AL6YcJRTZqLSTZ2Ep7t3hxYs5wtOf5II9zef7NtL2AU8566AwcN\nBv1X5NmA+QBq6A8+AaNuk3Sk+eWNYR4r6FJbLmj7dEPVZAJFLN5Ldrsx+FDDTwgnGpIE4vgeZBrl\ndDDZ/OZ1tIflMukpwYpuLm95chxPPMgHhcr2TY0T44peWcWCX9mf/oHfU0EIaQ1trQTpWZ9UgOgv\nJ+BqUh2kD/ZY8xY3ZxtRl5cUS+d/BQ/dGNcHVXfWGpblRGcHuDXQUSgQIQ5fs96PCpEWeQrBEqce\n835ejJOjwckfqKguukrarnK9MQTALwzxwrF7qSEJOdL2Kd6E1Sj25F2frPDw775D4TTf+QnkzkB8\nuwLul0inUosRQWaapvR1jQJOzvysUAvfCRA9dgbKem2n2Ji7r9ZbpYkt5b9BoIDb6VrY9FuhpnFG\n+N7rkUrR/VFKVZmWTzc5BewyXbTa+SblY7FtvUZ7iH9BvCq8nY+IxjG3WGx/Vndxy1dMnFBeIhHs\nfpRufL4fC+GfMvJBxJxoEyfbGW5BtFbo+uqfUq64kNUw4oVli8A5tLaYd9y3/LdfbZn1zL1kixuX\nJsBhRYwWgGKxpbo88x+3FaGovmRLQ0uiAvf+lzDVuI17RFLwvbgS4MeNpGqr0iK43vohOKiALC7a\nmiUGzxMP9+r5XbhAx9Nah3riZW2wpLIp2GPuOBy2GtwBbNKd0w1BN8jfH6p50YdFZfksroMqArR8\nd2b/qG8VwPyVt1gfdDrNtiGzZo/oexOiCXWDx42LQ6OtrcjQUGL7Eyh6DV7+/QEX5gFJ2McUflPl\nHbyv6Rf4x8c5wO1QsEFWaLGTxOr6fTvfFZ+A4OZhmC2IzniHjL6OJMykDxbrGxcfumgzokHmy6Bj\ndqfZBV+yYdJaqSjRjg8TQS5xL+31qweX9jy5XPRrZjj/nPO7WCfrALdAkZCRLbM/lB3CYp7snq/u\n2FQPUJKzck84Q6brIc0yyHU7cZirWPuCCJm902jQfF1Z4eeNBniVJqMxGxD02fyvBco+zDRR7wg5\nMwKvzf9KCPLCMRDMCwvw1TZ1SLv0aWNJ9yJp2MIxp6PpsUIjg84Ne1nZTjRC667gWR8RdM1HSMvp\nR/7CjeSVYqHKN6klkOZrtYFEWmP8tS49pJMupw6rrUtfubwgMJvsVlsb7zVRcFr93LNl1H0e/645\nyXQRxWG2+4wTzpf1vlhQHumG9ELNNRScKfUtMXWH8NLo0b9JOz4DX0BYTMiPXTTSr+rVInFhH9vt\nyrLIir/KW633WHZm9HwHfVrNspsymo0wtIEabYHgDykp9IqD+mncW5WQosOpZ9c4vkofCTg+awnc\n9g9fe6dakktrevhHyNh1sB5eGeg5gfeQHNFELghRHiRSSuuaP70GqMPN6n+FgH2kSfiBn7WOfo1Z\nOg8ypRlaIWlDvEQozS+0hlB5Dt5B4dgvD3VHzllJayJgpCBBigpy4EUqYp/wW8UAINtpVtpmvxTh\nrj3DAKLlaTDm4rtplrM/QG2R2gSl3DkGIKa+oslquw9wiJUDsStTuWkX/Csqg1hF7yHpGi0gjWgp\nes0ZFOARHpaTv1eNyijqt/5kL3mS/Uyu+Xf7nqYg2sW93lU4MRunY4E3x7gVjVlnDqrH38RsgVbf\n/bAB53riBSBEVwvrIhNCLJf2YSx0dQnknNj9TrGqG7wg3siYtKyw7dITk+j1adr1yT4WF3JPMXfc\nCGCzd99DwEMf8GebDHPdamt+dEcMNraG0LlM0/vyu1DcPydE79HjWORYiwyjETFYxHgP0ieLY9/7\nbI9J0zAIV4h/SBn2tQvbZPMzROTS8cHMtYmGYIAW/DOx4F6lPzxBsQxGcsi5bomkSw3WG54ymtra\nZtfJokEersbLJNwoqItcy93giFl9IAtCELZl3/U1XZHZg9mEYTGHi+vBdcGOqdpQIlvRX9p1F2Ip\nTS+2As10HdT+ixcdc0Zilu3zsL1nC7aL+qOP83pBQo8WlmXPB7g/p+8+Whhe+6M313uinCh+X2R4\ntLcLDG5oPorL6DrBeWkOCRhppgNms0upxAws0c4vpFv1G5Yi3kS8D9QjDa9PxB7Zy5XIImLr5qPc\n+8UsRuj/sjnk1nk8FLFkVBuK8anycdHLyZlXSBldoluzkSexK2ccVW+p7pHqcaL2LdwCThrtKHPA\nTToUHml18jm/0AFR4DlPjn0Ay83jr2CjaCJg88QoYmejDgsmSwS+qrzdyenn92N8YNQwXHnOxvDI\nEX8NEjgGwejNCX+F6UDu4ooXRWCHV/db1LUmOJi3tZ6pHl5T7C3UGZrLvvGq4rqTC8dnXu7QElEl\ndXB0Jfvj1WkEZwRcfDqnNndXXvdb0+eXayHK5eaj4SRInIPnJRdtP+2MMCMg3IZRDGKyyi3qm+9q\nnUkNNue5OIeLn4DECovWjKy41O8/ssjasnXEaC8b175d2zW1YJudXn9amXWCbX9Ud/bmb6nBE4Mg\npCO8ysuApFyU/RpvYgZgCQjbJfU71XAZCVgt05sizCXay1VKVROFnEp4uljDGbKOjbHbH3gaC7I0\nRWZMB6dkGm/ZxIpiU/6RKB01qIJZr0erZoOeIK42YBb9tyTfgSvQD52iJKevHGEhXK2s8Z8x9dqV\ngbuqj/yvDnIYAOXW6DSyphyGUq3aKIziCwwukrCtLswyddA6M/CtafF8B4FN1BuIfx/+G0b6ngwm\nlBCcR9txsFqfBFL7baf7JUUA5EOboWh/ow+ujMJ8iFpfInczwga6nLqBexAosYjMKIre1kpSkuk7\nmegLJWwe2EgVBEDQ+FmrZqOwYXmJns+jqYMgk1QuPZ8jdmeZuiWEaoAqPj/BjdTnewI/MRkRQsdY\neMANESKrmSRpTRosqItt/o5xjdCDEWk8hsvMP6Bj6VQ/1SArS5QfXG+Q/Y8E1dB16ZwIFCvFp58f\nsaGN0k88w2vMwShz0YC4qI+VDEaGMPvj1ETiDId9F+Tk1HacHTQy+l8YVIKzpadWyDJUEaOHUqvc\nV/kktcLl6/A+rZacuEmYxtPG0SaB0+bzx7ulrKNeyDQpLQTxgW8cxwbZvxcx783MMKW/oQTKfMgy\naoO2bwD69EWFTjHW80RXlrGm0cI2zi5rXy1U+NuljLwFfXu458eZWWzbfGKiHRvM2eprcivaE45u\nhe9tUrWmJPNjmytP9CxzArvdMbGunwZGzfOtNt0YrijI9OLSvrDbl6x88Sqqw4GQJVKTm4/q7xh6\n8ibl/9i80mHDxOj91I3UiCwqkZg5G5zVN/4axYNihActqP41F5lLkw+hWR5kQsFBAFQHJT2SOVLa\nLUPhs1boCE42XK6Gfj/Tx2j9Yd44Qx+XdDEVSyZWuxsFSH1i8yN1NUw4ChRYkNerHAZBEqCnNdYK\nw32X9be7UtGPqWm+3kydmuOe71OrhlKu2HeBilBviVP0AYa/zkoUuFj3s8Hgt6bSKoet6LloUUgJ\nqI8wIbgurQBUaNaxNnZ6GxVO9KTx4uKjRMmSU2XP0Twz4ImN3C6y+UBZG4qhw9TRUwf76N31aXXX\nez8PQ3sgpQkm/gt0naEV3+9SFysH1BRKSrz+TOIbPy2QJV7qnWWK5k2FNjHhbbtb+AleTOtfBoLe\nEc51YElVxUKld/cOOHHazFVO/nT4EqFRiIn799Zn9pqxR1xVuX13gQXEHlVlh3GnV30FjahAXr2x\nMOWxch6dz3IBXnmtnX2n7mx1OQ4jT31f/LAhehnnyv7TpK59ZVYFQh9c8I98SXNxo7wb5b3nIqNF\nMjBSWnwLaerX6UcJ5wPGVssWMw3zOtuQjt5MxS/pTaI1S1jL6dio5/xyaY6deEFJ9UwS/nOXgjhU\n6NIeYRg1kI4nSBmdu5f8sxS7Qp/N86BSrRb18TCrGZco50Sw9wTR/ACbl/Ch93aVY2XnhtEYIFWe\nY3nQhAncBNIhNdS6reDaGsxj1G5BA0HDk9YheJUOGCxMmUG2sRwD7LpOjbl+q9LupIxRmUdvqvYD\nJKntjzxXKsvtro8LogYiYb9jU7/5yiFQpM4uCDTXQBl+n36tHKaSLrOH/W0xGbxcPK/0m/f2h/bI\nCbQ4FdopFGjDlNksSv1Y4F/TlRRs5+ychHtOC6UcY+BgwNJp2Gat9d0aT1oXlCfNnY04bSqAGmNj\n8DZTRVeCVeUzmHHqyl1m/pWKL96Gqk5EI9JtPjXn1wuNhHJ9ekiv1uy4uQ1o33Vi+ASxHhqBazSH\nFQOgKrrK465oVwU9iZk8Zpt0a8UYjBp+CDjOP5tFwWpi0nRehaSdfluPmr1s3qcre4Z1dlyuV0jf\nXfgz5hiEtEcttscDae5WKJL6W/0vYIFH2/vsm8OoD4RQPSJNN34jUFlwqzZEPLtc/ZeiJIqzUumu\nt64Yslx5F4I99PgpeRYFCw8dD3CtgpNJKeBoTpReAT7O0ob0NK+MEpspLAce7CGA4RRjowNNGMZj\nbwf+qjEbROMQm/19sdfd4eoWtFMcBEmUDcIwy3zadlH98AjuPeKJtAWtfbfzFWDM9Mcdeew5V37J\ndf1g2fkmvBh5dgTvCXMr2x0NWwFcd5imxh94VvATHfw7O39QEdBXFfPj3ffEeqTAgbel0UvfSnjU\njZftrWynlJu4kqQSU10JfnORHe4h72DiU/HtIjRMysSqF593SJ5BRQkc3ByixiPExTfE9XghBavi\nhedetJextNsM2o0MfQZ7M2NMv/CWFgI6DP1xZ2Fio8L5dpeAqYORS+WFgznPUvW4j8x9179cliRC\nH8FawTKxlGrZ/zMnEQqOo2fMkXd8byn8oV2qv/l1HDNFJXxAzGydp4ep9xXaGpaRCjqYJGv35KRC\ntxLJsY10Td+DHMNcdv6zJUtkWJdetQUQjsIqxJgUh2NTibilW7zwlph+ltuOQiZj7dhGo2NwpRxj\npRSOiTAthj8O3Oox5lTjkWsZQOJYZhsuLWdQf9lHcs0ZUsj5S9+2RM6U0rewlBsYMkgeEIO9WrvZ\nnFWjGBlhlIAI6hW6Ek754Y1NwfwcihhMlbFjezjsdA7r0d57sHy10dnyKk2dKzP4lsXx4oFswI31\nMlJeO4e+OQuXMjC2s9QtD99djW+BQN8vS2hss2jXp0RUFN2ALmqlKUlQY7F8Qk7GA8W8xEdMSRfC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CgNeDKXAqsyHlBqiikZBELrTLQziUuO2Ozlm5IjiDh2U1AcE58FeYpCUcAKk7tuudNf4kA\n+4IZMoylovZMIy1uk6gDeTs8t7ZT+qbKAYqvQHGc680oqpHHqBGMlkn6SvYbCvdeT57YiL8qgbua\nHHRqgt76f9I6m2gEbzKXyq73F1XA7iNkIQH6wvVGab9k5vFK6t3VknynPia/XwHedkmztqfsJPcL\ndpmsfLCWWjJB71zBzndOPEH4gQlmdtbPTUCG907wykBW6mbI2D6F8RXBFxLFiTe3lLlK9f6JqaKS\n6P5Urf4pShGjQxePyekutNDkOXiqBWkNmqlwZ0Mf+998Ey554Ts5BpfAZKA3iTDnLqa1WjM8MdFu\nz5cnBm2QmsWFiDw07bde4lWuor/GigLLSGoi61c1W9VUUTxsmRW3Nm9hedl/LMIi+IVd3Ie5yuhm\njFTZ6GPtxceQZ0a4n/9zmY1LfzOKboZDW8/yeLpK37K4KdBjNJqUeWPNEgbkAwu3B6nDVdpVe58R\nyE2+HOOoxDbkIulCG/2Z/niLLNiqicjDej6x19gTcxFfvW+AKN3OywTja1dzXhKcg8TxzQWMPch1\n7hIDvB5NzUnEvJPUkHECOzjp3pErBKiXve85ZxpQKaT3uOCuv48BGPUNsb4Lfbil/ZB2YfZA375g\nBWHRJSLDuy+pUEyTq8jZoZFHXN7uX9th5cbBFjtERzEP1e47KFVu+y2grd0uT/p3aA/Dnc1rAVN3\n0OUl/SCM2fRrCgXsZVeNO9TXtrL2agt1/h3Lf+NdAkcZvn9s+8p2KQQWKc+XZxkefaWM9yc/9fsX\nPY1bSFbAWYgAawdP8Rju5Hw/OWV8Sbv9vq7xEY9BvZleZMYuNtFgj/xGBc+xuvt2uXAyHW8FfkIM\n8cL8AdK9g14QyRhkyT0yYQinZHzS1u8UeYNIafkE9LsetGUZn6zTUy/AAQpdOJF5R9QumyGkPJIG\nDLlbHC3SGKKie2/q6GjryZedQrBwkwtDiAxTW0Qz0ZfWnHQKZUXchgOf2KSxyoc9cL5NvBSM6pDT\nBAvpvpDR9IQrbp1Me+korQHewv8IU/iJGQDmW9irBUgAsfKFL10de5y0FcL4nlC33hPYvgoiE8RU\n7OI7bRcSswtiJb7UhlyHXhX/Qq1xYGb13RquMH7/TEr+w0tdRTXngTK1PlKg/fw+yvbbbz84vm14\n69gZb0aJzCbyTfgznfo6NSyt+Yc89ItF7q9pqhZCgcdoPXmBq3Yy9NMPtoxsUH6kOSfBF8AAXDx9\nadNlsmO5H/J6vjfLVMwnD8RGzKg6O36A/qO8CTAXdFBWJK1mHmV7AHkQWbWjtI+29Y8Cjcm5TMCZ\nVcGqgrTLwebwYR99+75or4EP+AEvUyYflRqH7zmkV397XZfJrtGjYDfVNOaw6Fwwl0BUaCVklg+U\n5ujWXPqT+WCdWww8BHlzRx7C/fcE8QYr6jkhv8ZWaZVWeR7m0BETZyFFtYpPQbknoTrZ5yogazvW\nHlomBpRuB+kPMi3hXD9VvYxmmzlMPKDSqnD8oEc+v2HUEWT0UgCJFxQMm9iGggPf3YHN9D0jFjsl\nmgTwaen8m0tCFvDheznqa5R4IJ6bRUvo2XU9OK9xcgDzQcHU2WgdEott1qQL2QD9Xhj4zN09paCL\nT/tIIUjT3V9B5xBRw1DMZULj460qadkGntA2s4bdSew3xEhDt1THe7ANelYoDzMrlueUPA5ybCN9\nj9ihdm9lEllXxLg3gyWzGmSmuv3HEWoNkOVomnTHzZ3J3QNTFDOMQOkjTsUcMNbO06kf3AfMG0np\nYy1LjpLqweinJgeFCZihIUKgUh+mM5q83dzxHzSQOkbp4qgEnX8XTdz8z9rDrqNF5Lis+cg/r2ky\n1v5mr4jN6tquOWltmsh6mJqtbEflof2B82KIIYqy+oo3T5rJ8j7yS3pspqLojUPsoDdI63Y38pnl\n/hAd0oP2aCtDsnE/pfTIXiWPGhPniqLkuv7cBGBWXYznkXvzGpkOqxyxhWAgwn279Vl4NoWBY9nG\nP+D7yenxJFKzsvPZCtA18L/DbNpESKFNX/zlfxsNo1TD+3r7PZTSdNqrXwlbhXO/m/+5mT+w5GDX\nG0lC5guj/TIRf87wZd8GuzTYgQ1MRFizqy6t3AMudVJ2vnbE2fTM/qu7afzJMvpQ6f4Q2V05ln8/\n7q3U9uBhrpQvPrvVqap3SfhElGbEOS4idqH+lE2LwPXQ3rvBZaWDG/ZqR0WAPWNNl6uprwIj8V9F\n/nbYOcr9WtpeB5Z0NEKE1Wdxf71w7Ne79WOVGcm8UQCtaI9HHu+ky22iO7zNt7mGTopdMTplddm0\nXuIyP7Cf2kKXQqso4w68N66MJgEeKS8ICKONtQ2HfqETdm23OPCItND6bDztQXOM215iJj/463Sd\nYBeMiN1aY1cnhgrab2oVuroETi3DwUIewB0lELB61LHLjpKT1uFQeSRnVjZ44sLqvXljLc7VhQ9O\nkM67M+SRbxF7gdwjNVUCJtaTxVM6Vad93zRoRBBi48nRC4GogHXTVFX+P6PK4lESKZ3QFQVE5E2X\nZJPoqgI8udlaVeBK1CyOphB54UqTOMDo6yXhK3f1Oo0Xb7Z6EvQYSu1ZmiGlj/VxnNju6GIffPbU\noj36vPOyJjH8eHw5Lsq+wMg9hiBym/bv+XrGLRz5gPQOhulovqdHuA3VfuOkQpBXA7ZwWqE0XEHA\nHlX4GYw2s6WZRP35U8njSsTSSEzeHuQwdhGLNBLKiGCMrt1OGn5KvLQhhz3uFmvCvtO0YQgr4gRv\n/vmpo6suAL/ASzgOaEPhiVzMmPkrWYzIBE3QRLskFPR7umUQrpLgsHbonxi24nKArAZlLqvR8zG5\nMJW+VCRb5DvU/3epE0IoFGxaMXInK3yTSqfouU25pcD7UPznWiUd+Z3ZbKcsRUDqqTFSWVEIdDtj\ne1soBVA1ECD1iz6+bTpNY5Oh1fX651YQ9lvHKncJ2+dN9V+hRK0ngC8rt429CK7a2Idalpmi3JWg\nDc+d/z1QrUiknXJdMXdblP5a2mivNqIY+P9N58n+bZLVRKzRPI5fH+TaiZ5jTqJPrlNeN6D2tTa1\ngbHLS1Bq9dYuOLXi9TsbmXBgJBQwwPEWK5yG6KdPu9G2WhBizqyKJONkO+nGznTqzepavVi1EtT2\nDSy2ZlkxvRjUjhs6nkJ8oFotJICNfcBze5Rsg/eui9K9LduHWu4KMEEnfS6sgxuooXB2mSH26zwV\nij9uuzBYnF5pUMZP5ZIHwUnjANwa5J9TVpzTTsyHD+lSA1anl0ixbWrZqBWojDnzT+iwlGIxFd5a\nCr7uEUoz7+tyA+l+rF2lKvvxzfe+zdYMMBvqsNDGdYqNAW9FkmJhCLqy/xwgk+n2wVFwkP5bs5+I\n3CWz708qj0Xl3IUamaiej1IyWbCM3/65rfAs1jw/SeAXlA5GLuL0OQre+5ukvItsHTy5WCsZy25m\nIlzQgA+g35NVaLX8dpPHhdDcFPt1hGXhP7Yr6joKGvJFCTAqQSq1Ept7/OihaNf5XXI4dZlwggzW\n2O6+s9dtuhAiKtqIJ4ijww+apXGJirR6xUAhOeSg0/dL5FZGPXCUkxIV/mjEPUtP8xHtTf+8DOkY\nPWXBtnx2mGH1KZHfCfdcUVSPmQCAIA9DeWX3Q/v0IL1BHCVTaOsQ0i772YTDjXu0N/Va45Up12M2\npPcrdVHbahLP7O39ql/r6SNm08f+RwI7JPRtDX6X7V9G6+hu0iepMxsxBHk/8XaLUie4D6F8Tp66\n6wGBZoUWXHhVYxe1w2xSgRvnaXfLtyfhQlgn8KmHdgk8ibc3u4wSRbVtHfjrajovxVnePPubf0sR\nGGHlwLMSkklmrNGL+lSFGUi1thX7/vm25FpgBAf+b4KILInLLMnv3/NiX04A6G6zgU8xudOjKqA4\nQagbl+lgpX1lp/P67vogTffKrn8q3i1bhVvE/95/IJpHNxGD/YefOIJie6yvd4g4+QI0Msv2w6Cd\nidnVFRjhjKzWFPITgzw+/cK7BbMWwZa8ZVr/R0Ea4sWBVTZPvhPjDIMDuVTtZ/BIXrN3ZvcoZLIt\nuEf9nP+YPyFSF9h0+9M0/nnp9F71JHyX7jYpqOOfRpiL3Nxuokq2bunZore8JzX0eTcdJscbMtrD\nxCeKBmGQnzKQ6UiCUFkKvuf94g0f+IGcEZumf//3NSJuBvPpTbwMJSm+sY9G//ySSjk7pQqkuR8b\nMd1KFK517XUMgD7SMRegkJwaEV+w81z7aG1qIch/hQCgQbYqsyjvh5nQId8PgIl3hj4GB2InI72Y\nUAhpGWuaDLA6TX7OKs162hqSHhiyjirChFnxXjvJ+txbFF2Fcvd8Lle4qgP9HzwonfxA4tbzBytC\nLJ8EbIpgGoQE0uuPrT7LQg5Ul5yacTYpsvgQiEs6/+lSlLDAjEpcyOT1BIsadKqhJF6LUpao/Yqd\n8nYhQPOfQ9M4yxojCmXWRMhypMMDagM5T9sv6qzL6qgJ4635y7SHWV5n1z+x2GMB2W7SBYChf9Cg\naynz2TV6w7UesU0HBZfyRI8NLkyMS7ihpqyH1jAn2v1bX9SC3mKHK1xiPPb7MyxWS2sPaIZTX3dn\nLSFpuj14rJiJBIzNUKOQfgxBQxFfjiC+nqamVkFll9Me0K3Pzx4nWb15saHV2Agy2l4DayCQQSf/\ngFu+g2qlmJp4rljeZnvFcfEJsOYyCCSq72bieaiG+5CDM8FK4XKb+yzUHKzInHArOoYBwfcoqN49\nPkjVl2JDlQyLuLK8pcfOC8FrGunZkBIccptg7+MMvM6q5pSPMdCQzLJdSw9VJocDG6zh3Z5jUJwH\nJq6pFgVUxL4mHQb/BSlbgvs7NHbdBWKz8rrRA4eVc1kv0JgHRrOMv+3zEIoIiDWuTT3t+yN96Iyu\npS+PKCweGUCAk35o3tdplD/UZzdXhXqDMyDWXStqKnsQIolGFL1H7y7QpISzFxs688S5FmO1T2+D\nM5ktv/9S3iEiq/1qs2t/zEaENLUrc7DR/jifXMCRgj63g3PpLxVEDTtL/3O4f3ScoHrkebcb9I7i\nNaMRY216C8UOoH2/Ce4vGbBnHlqnvcEceN9HJrjnPVfBNQgn3cqClEzhriztssglsio529EdYhvp\nAI3zSbuJdREq0mii65Ch+MFopk7xMl0FkZtWXazGh5EG8XUCqTTwL68iZQBJNXNwpWsMwOjvvVMZ\ncvUCwskXIgeBTeVeZn9bFKUZ2F3GnOTZ5jC7ctowLND5yXfbzx9O0liZCTrjtu53iTdFHajEz/b4\nl8p2KTpbmC2CvZInR7lx9ZYk2MP7OjxSovdxxXIwpgMYWg1YKAiEIew1eILGHH9xYot4oEMFno35\nqX/JcF2ps8iJNJ5XQ1YzV7SduBeTCx/Yb2d4VHhNd6lfGJ/VPyBamni0Pp9q2Dj928OQezu1XIGJ\nvaLVosBVp1vLOs0cqntR2L8Ok3H6FZqtFm8mugOIB7ULCucN5ryxyJlP6Mrpe7ya1q8lqOGtAwth\nG/Dy3taw/Yy5HG6TB2aoRw2kQ4Btsq5j++25XkrGXxx5TvMK5qSWyxOU2HSAXZZI0Cn+jichK5fs\nZG/1nqyorqf8a3ei98nqpjNgoHVp13lYVrpLCWjOaECv0Opzj1i6EBPMbhdUBAh9TkIuZZlMVuR3\nRh3hDvelRcMCee0tJn0NB1Wo0yrT1Hnz8diHo+bDuao4G00VU82hBM5EkCU6X58wSPK5Y39d0nUO\nHn4Exdiza1nnBgC5bhX9sWMeuT1jWxW1lo98Wgg9WCuJU11VR+TlEeM+FKOVQRTr1Pz+sZNQxv7G\n5d93rqlCR8T4JnKkrFpEu0vUDzqHKU9hKuIJpFddQkwSB2xvH1Ts23XKgRXCs0PBmPhGZ9fSHQke\n6HQRh6E/R+JlmU00vuzxXNYgXqd9Ima7gLVPBiuGcv2c6w8sz9lOe0reW1OoxgvI4MANQ1k5Qp3c\n8cIsxgheBdrhp5iBVRipALi64MIShWbP5ZPoC0/pKzYVhS1qbqeAYfngLEsaGyl1GbQiAKOpwRlF\nIj8fVr9LS0n286kxnV9KaZo35NiXSH+DeeJHugfPaKqRPArvCi51KSMF8TRpImRrY5g12Q77sDQy\nuaSsxVmQ+gC+MrGhQk+Ferh4zGEzjSHtNC5ofHgArM1c+JvCB4xiTF9PDKwaSAZ1gS7diLNW1Bae\njLSh/zH9yp2jy6upD1uDSCyY4UH6LJchwsOuMFwcaLN+CgxYvly0DIo8bjbzFwfBkFpGByBmPOSw\nX+53dM1x29EpbpVG9DnxzhIEiTGtwhrwJbrLXT43mpBbRKdfi36hOpAPxzwxGmM2XQpL58RRNhcj\n8J3y+kVQZQrtEp/v5MaE00o051ZKzTsCgatNlb1+h7mQ/c7C4QiCOxC33qTJun7RX8BJo39ZrxTW\nYDNppnA5iD22u5ou7Y2jTNRktD7kCCFgu+pWxFz2NCOwx0LWL/xwthI4uWgbfvNB2k/63fFlHEaj\nE/lOWNFbj23yjG4E8gRNJy714aUef4Tuh7kJF8XPER30VGXe3k6uKrLNYFb/CjramGTQtoZqG1Wi\nNtwN4PiXY4YZV/V7DJw5tBEQC+OFyKd8PvCYSCZXox/xteCAfB1CGiTkBdDPfuo95ppWrd5sYro4\n+m/uYlT5oiDyS4hcdq8NZrPRJ7t3f6AEZyKJHp8ZmpqJr35SNV0Axo3GFIGOQMDxaw2HBiCFz8ay\n0cqG5lTZlQoSb2/5YRFNwgAL3XRgaPuzhiWC0+iZX4FfOSVo7pMENSc0SRR1oq9QxE68hWiSkdRE\noq2dpOWG019B4JrlXKNvrLkrMUJ5sH4zilU1RN16NshlO4pE/W+iLCp9yU3tOhdOroeDMEBV5sSX\n88rzfqWGbCdzlLwovLmF6OC4mjmrF4HPSsi+jJqVq2LoTCm4TxIAWNwNYUfKI+KzAGYV2zVKIdc3\ntv0Wqz2HF/Z+mmlP21Pxb9zNw2JAzU912iUJrv85MmEUSXlRqOnV5EpBN8dt2ng82MQtAztJzPj5\nm0wOljbovym9o2s68UWKkcVsW+u/o4fpmLEDu0/z7IJj39E2uS4Bl12w26sC0xzNue9Ykx4+XW3u\niMkZqb9QY/xdNNi+tFcPMQW/CatBNuqFXQfaUvwS0FxSHLkgwa/6tPKdt9Lby8Qc9UIlXM2UpJl/\nNhhYzC0x6EdFGNul7x37AnjCNny4Ub/Ww0R4cX8qod0lRCuYjc9/OQU4C8qBVlWUvWiqPj/h8D8f\nQhCRt8sv1r0iAYpJk3cZpgmuKHxm8jFvDjo5WIz/+22ypyGDYseC1OctClKvmM7/cVdn5VkUnqgn\nJt4FETNQvt7chlPPD1Blrf1lky8HAFkUz5s1KeXaTm0rNu7JE6XR8V3h7Czf5z1eFm5FpaVLnA6i\nl6gkI1Oy031mO6fuF+2UNE0kbZWVL/z2MovoMxd61gsIaH2gjmOgomeRnukJmCRVi68MY3kbsyx7\nAjDUjeD7TumBK+WhBzseB7EYdYrrjC0xNAbW0KTZsa8VJzao26yLPqoVlniszEUaEfmZIu4GUBZX\nvH18+FvNpADgh1KH5fdSuHDiDUnv9oODiC5mrl2wVb904J4khorffh4MJpK0Hyqb15eO2Ca0JtV4\nZjVozV4xm0JoXjRu8uL/nTLuVXTAPNoM3SVKkg1n280oUNhYvCX3i0WN5ylfMuGbNpcN9LJBddp4\n11SqFP1NXhuLwJ5bA0jOtdxqBXbHcdhaeMWFitR3fXFHOvuu8aymkbkfDY0gdRGGti7aSaKU0hMX\nHgwRHUVqc1iR4XykXmb7Q5WfcLF4ooqZtxsSikSNFHzAti/2yk0oMmHKWKyVyVjJdIxz2SwSrPSL\najb0N3knTHQ3MuD1lBFy1po5ELmLCBhy7+rf4itkuo+NQAIac6/zcKBIYoXi1zD23vt5qsgqoE+I\n0Dp90ubxmdHHTmnbPTc4+NNMjNe802tiwRX8CZpAyNkqWZ8oNywJ1SpJTAhL7vDB8KGw10MW2FXs\nnGOuoVn4I66Wj2AWJ7runJR9WAguApiSNyEhtPJ9f/zccN9yj/QteX4ipYXXTXBPY8cAUCzK+kOu\nYX4J5okSHWg7aWiQu8JL7aFCRdxLsadgw2aFgeoz9vX5B0AzCBF7usdHNbf0jEDami6RCH93J/m8\n2OgYYgL8Ej+KCoG6lvUB7OtCjCvIoCrDHKr9U6qbY5BHtKNyZWKLJBRjYgJAXT9v2Nb8RrAlBDkB\nfHRdOhwhcF7TCnh85ucoPzf9Migqgrtr8G8uA/mMezhbEr8QjgZa1i0Plo3+XCsWN7z4bcLKWxvK\nbESWGbRCbDxXRh2vLlXTlrKJrqt7Nf8FtiBJRUl6EPPL4Rba0BmI69JvljAh38P317fIDE4GOtIa\n9mBH4b3fi7i3IjZADl/THipU4HGXDKUo7LVhZ4WWooXNxMBYiHj2F9OO8d51cHckkNvwl4dDHfF0\ngX5x6HZ2Z0euPtHAxIAIvGN3a28eNgs1FbBm4Cj574vBPQ1sPztO3qkYdPps8yHnpZHu8LAKpnjX\n/Uhn45oxLvgkox1/n41E0uciB3IWvFt/eOXl1sE4Op++7BmN26/XUIdbybUof0JAEltx3flou5sP\nXd+BlU/qHvEJ+g7hhcBKwWZ3W/4Ugib2r3wlCRoKzqhT6iG+AvHfkBV08TRK6j9lSio1idWQ88JS\nTHQ+2lESdjCcCVAInngcchEjo53n+PCUerJ9L2ZC1REI8gmQnPT0XkhNUxwEg75EddN7xBVUaSIU\nDErm9gXrJvZQPsIuIkhgQk8i8CZKRfQibb7WYSuhc4dGRTCbAVa5NtFD9MSglM0bKlt17zEKpJEC\nVZllz9DiRMdzE6DzA3RxRnxsyZUYg+Rbqgy67o8VeLTv7GZ0hb168GMPVgLm2aoA+awycuS2nmIu\nBwxSU8jdhryhCanImlvv7n7OM9qDKeFnUHub7j5/vLqo0gUPKbw19DAqLrR/dBm4RiruWwkJL+Vr\nYaDpf63ayaEeAzSnD0cpQHU3ZCLJeBhnfxX0uYGMQNvJLhjZOUAZIKU+q2xLMNBK0s1Oj2SGLJIP\nB9ay9bhEDKNDG+q9tz0jk/lHWt+27PBZ2Orbru1IB6PGvcF7o4IINZ47Y61IJdvNx85lEXBrcA7B\nbbOn6CJjQB+T7JsIxok8+2GENpgNIZb6Bcgqp+lkWXRcSdm4Crhur5On6XLP3Smat8qdnIApPLs9\nbQbuEEgK4iGY0R2XON7EFDqcwpvd9HJfF0doNmYRnby4O5jr4dNWSJcrtpiL1SVKnyGhInFEfQHQ\n+DXG4xim+qZiObzxjxlE91J3P7ns/Z4agRzKnj4Bs8sCFphJUAtf1b8M6ki8+wqxmoorOBQ0TSW2\nfic1JdtlBxtJjj96bMWtzNWxqmdMErlwhYYmgLITsu2NM4iCAfcGKBZf5/2QJAc6KpuJ0YXmAr9P\nQDh8+p7+bfBMOizKNKsdDJpQoKd+BK2c70R8IalyjokLs1SjxebWlA3xdmVEjTqbNeiC6czWFnc8\nMh7lwb3BOc6Ndlx0fLvO1LygzG94HCJEuodp4BDA/XekIbw6e2jXryvJZNncxNOdSAp7NhXD0MTq\nL+eYms7r3dzLqPnTIoOapuMLt9z6pTGSFu4prxt3KfZEY/tg5m2xYjs5S3UTESqK8EGQ4Uh7mj2C\nmeTpL+NnPHN9D6Tcwlf2wKcwzEIoPFOH+KRGp7qU47u00mHtM1w0CJBaprBpNYslLWtgr73bM+TI\netuwVX9xMdE1iIPLtqDKqToNmwqLbTqYbDF7AhnuGCclTOQO7rKzXkiuu2cgkNXs9MDcgBERnrlp\noSmH+1XF5zy5EgDY/aj6bc5p8COX9j8fILa9GWyrAzi1rYG+qiFjYiaUKLyhPeYAdWWmMyh4i84B\nbKvDE01pJCRGteMwcLryJl1FlmrVWZXeKcC8QAzchBBp/Jf37YDds+XbqrZ1m5Ume42Oz+OwaVx9\nQEp0d3b8U+2JSWf7DEIHq8A4CPn0Yz0MR+6IFckEv3n37qebhFORndRzGMZYLwBPz5F+lDjhD1nN\nOBG8YI5McpkZKsODGLCYC3wWWtO9//k/syJXo3iJiTHAkaY3Pk5xdKwb9VUpZc9922a2AA284kJS\nc/w6K1tp0gLU0Mpr0z6sOE2lMiA9auYS/Ut9xt9km5TLfRwtApCrVpLkRpuATTyDkPyjw0zHlluA\nDR8qhNAd0dv12ExG7HMW9hu1wx2tg7gT6DB7czWMjfl0oWfOni5ihNtwEk6CQZd28NjZhRLPtWUH\n+FSLzUGO6SUc7y0gXgUKHWWu6ZLCJjuzVlela+dOL72QeEaZr9W2zZsVyJuHyVD52aVnwTT3AOFK\nn35NMxcXw8wKd2P5UJy7K9ud/l3TB787S29ZjoA3P2PfHD3O3ogtqpAvHFKHvQH6FCjFAhfTNKsk\nHErVZ+LMGHXIHVT6Z+l/KcDRafI2MULITYDczj4T/XSoW77h0fPEHYqOvITz9/+t1jS4SF/xhMpy\nCJ+vM1OJD717OQYw3I8AuWVAKbEFDmdfhO2gYi1hMuJLe7msDDDJmugXMUoF9mrZsfZexfV9i3oi\n23Wes31mp6gUDeJmUnRxu8vnEXLXkiWl/9u8IHC7E2XwWrRrQjWJ0kfamR8dvKkDDNULew+4K2sT\n56U8REcr3Q7WZl30N9S69uRhCs6IfmjziRSl+vlcdn4FfriLuiXy7muqlQV0Clg60PupqJcebXH6\nBUv3N+vgcEBJNag9MeJroiptA5SBkyIwauhthJkNyG9cjMvY+Y0bNjtsLtZs343tIffMIGKFux57\ntQPtlA+1zsQMMx1GkhXVLeWNpNUusFkTpgwJDoQLEOEi8Zp614efkCcYVhmJGzjWSCqabm/Gw1Nj\nJ4Ik0tMKnueBJdhaSEWWsyIg7gzCo6ojbJ/1WK3XZUo8cSbAmj3NpQ8f3K6RGgsE+d42pR/T303c\n/Z3Uhu2BKb+FQ6s9dIHtFotmPfqktj7KhthqO8zqlyNKxItDaisn3SMELHmsayGM/owrpF7nv40K\ne3ed0W7e4bQB4884HK+HliaLERfHqfd6sojXuwMehsBRnJoO8m8q7ahZ6s1LsWkB+Zksnu71S2zV\nHiUZFid7GiuHHiBUQ7Qd/vPMsMJp5bVtz9D4AP3I3dU61RrSKIdqL+KD0OMmiKLD1s9vfq/Lggi8\nyDYOXnEaPvoLPpgMT75wyaLD6A0hux7nQa5XkbPzjFu1KSD8ZwP3SxVWbxj4j/8Tzh4FywINBztF\nn2rzHSaTZJ//RC8teqLSj6JWF8TEBft6NrAKWOnkEeiJ1bjapFbu+Xyc0moJisEfKi0XSUhqo0ZJ\nvo+Nkd9+TnyKNuD7VUbg4gMLsUjs7mfxUIZOcoNkcwrH0C/4n6c2WEoFq4cd7OfYh/pSCxWV4n3x\nxbmPFKTRbHeiuvL8dbAskiR1ebL4RRpvWaeM+4p55Hnr3ivCoL+t3xpR0JDvaq6dyUHXNbah57hJ\nhOWl8WUzGzQ3liqx1NFx5loduc/et/E44cmgxsaUGPrg9EcyCZ3LnhBMH7HJyYsqKWSnevkH3XS0\ndlQkPwd9HJJ6GwvDI5twDfDft49yqpn1LCdAWzFgtEquhfGIISyZRrOYzqkfKkXNSoavO7FzqJ5u\nPXRF4tJdvSlIrbdeRCN/Ru3p5rSBg0ipHtF+YdGXE++Vo0KAvLwFCBynpEUwYwLmFI6ab/wmzDEt\nPfJGznXMlE77hq2SQW8HU0lyYvPYMGpxZxfiyPJaal63xXG4+I5HTlYhvbYcEtXEwlFDuFMuGhzR\ncryuABzlVKTwMFcuBnLV1j4SaflPSwDiIrvcgc59ZFXh1InS6sDvwvBNCyqeuySJLzlUVZ6wuFcI\nrvDc/zMvFRimVCFvYsAlNyuXRDoaH6xbrVJ3rp3Kn2O1IXDh1yB/RKT/G+2HcP5rvHJL3ELRbZuJ\nieInGchMdkenMJGUy1maicvl8bwhYOb6T7q++1RqjyDOc6kG+bGxCEwGjwsHMylLReYe7fA/tld7\nZlOvMXTPD8Wr+YnIJQbNBu3wT0m06a3nMCX0Tf8mPMOQeujDiCxxBKUNU1Z4gUkdM956Frg/AqGE\nK1yAtEJgrP+R7Z4492iBt89YoCfexnBVxaWIsHhy5oy0Gbec+N1pXPvIGK4yaaLUKLn39KYX9oT/\n2kRr5m+fbiSVE6RvSRlihIvzTM0ELxW661/yQWQ3SEB3IV98hF+50e6Qofx7DMLs4a3pNNPMBuGL\nD5lgohDSC8CNH4nLId9yG7gsqxXylVWLKrFltKhvWIIe3Uhb8JG/qQ3posjDegfujtrmpc2W7H7s\n/FvHykVCTUfdYwybgi6uam7nskMH0JWOGeQi/ReIQgbyqGEJ0skd5h+AUDHmwcIYx1j0JtWGV0A0\nmb646def0eNaz5NXkKFscfG/zjwX5yi8+knp6y1K5DqQ5gSM7PFvWO3gc6BzW3QOKRZhwHI1FAaM\n+HHPxvSNMHyntRLaEXef+qV3vRUoAgVTQpadvT8Er6GaRMyVtoPUBLaJ0l+r9Ab+DDx4oAJBQdAy\nhSmfEmWKxdh4jCVEvLIg9RKw/nMZ3g17ElSkyV8JmptZ64i3nwISnFKTqAdaEwoCIDxWLYgXRH7B\nmkzrk8wzEG3zU6gr3RRW3zcpdTqWXJhVVzF20I1vgVqvlb2OMs/D7r+JqyCs71YVHigTOhc5oAdq\nmB/cZ1HOdX0H/45grCiX/WF2SxeJFBUjBzLF+vzOpruChX4Z29SXujo5mumzxkGUkz7ODmqPVbvC\n/qs/p+SVyywnPtg+ST+2NfP6Qm/GvOpc8DTE0mxKNlsTsE2Zo/Q1esOj6yRa8GAagmaAlfvxdIr2\nqQ9GRxzMW6WmYX4OtS7LZcUTygKZ66tKmEmiDT4ysvYlpXwj8Z/+7P8/gKISQYgRttmULOT71oQX\nRIUxl8biceYAQqmhuFWA7+c814MC6h/TQDmQFXE+5lRQlFFNLJeTOxxA7v0x8aDRxs+dw+Ws4CJn\nnF7tPsB7rCl7FNdzKPRG5Inlc8b76YKnLHN8PmDIMofpVmGH3vxbUJPmvoa/Gp1iSAyeqyO6DPMn\nOBEifX39xJdcDRc2HCFkh/OhEXGomdtpu6jtlaldzyxjjq01Hl/LKo7Vo6FklHLsOoo91ViQYEDT\n3jMHPVxSWXXHW5tgH/Ur7RTFxAUGJYfsw5ZHWqXl7hi7MBszl5Q4Zgmw0BwZZbrjBYrMT9ih+TJG\nCIa45gtEJLuoelht5168UiFEo8HXwEak1mCn0NqAnOG07YO0yiFxOR3N5XjH66iljxcI0/oM11ja\nM3jpJT7sIjDAPnJ8HpEkp0YHyPFnokJuWDEvv7j+tcQ85BcAWasVgN2xwJ8c3kOevuPpg3LLjegb\nwedODw9VxVyFUytIpddFyi+Ek3Ef/Q4EszVXZ7wSrZdqVFjVI+PEMaOw3lVur0LxFWsyTaf+WtVp\noCkznzxdoBsTSh1m2znlZ8iufzwiVZ+2k2zaKw8CGe1kw1Iuhi7V5LCdWRDup+eGBrG/MzqR97hh\nFj1+K6JVm8AdT5y3K/iCHnHdmkrAJe7LAjTKAVM2Ckd7mP7mFisLqir41jGxjs12Roi28k6szUau\nbxE4s4wOUxEE+PdrvL4sCjamvasmS24xaw2+sy3UAJ2/HTHf7Yg2SnRGvXrOx/Y3cHbhGP+aDgEb\nKktD+hEx5ivKUWMjX0ekgNUtkg8rP6tFM1HT5rnQe4RKQs13OgvkBF3dWaXWzCRx+xYycevTNusq\nzV/PH1N3W2ZPjrNNtNqwzM5yWOftRUiKNzr2HNyW2KeceGx8l0O4hG2A5kUOSsT2g3GUHVLNl5NG\nNXshenvVTyNS1iwSJzE1mXaMxcWI8xX2ZFXCTTsSKPD3z+Vdgaema+3tVmX9SsUAG+55jgwM3MZn\nntgcXr8wwDDm9/62v4asp+IvfpDb87r7YPj3AwI5u1Q2vWBBPaGRYLUe1YL+KjVMZkTz7yC14/kg\nKUcmXoJMX6E0hYYJbvsr/GxHEmoe0yXgyplmD8z8VHHRqULysYtJX+BomMvdqMSiXMrC1ftqP6Xf\n5lJLt3R1NupQCDd2yg1r0GVoif5x1Cg4O6/MztO0ot4PH13EP+8JhVoVyIzvLTsaG3LpYiI/E04w\ntvtok0m6B1GB1IKYOdn5UhTnnOeDSF8yqSsJdT5+W2nf0Mw4/nPefv5Fi3tEWiKG6MzYu5gAKqyX\nYsM94IBtU4+PjmNVbFDMQqspJboqD93At71pujtI9Yyr4NGe2U7LWqH5DJFqSuDwmUOpkT9NtzIX\n6Ykdg9VGhqU0BpnhvO9mlizoE4kkFRju4BfRyAmukFgTSb32zFRJsA0LLfSyOVbAZk4QIQYIBNOK\n1itbIDXymGcwdFMDHIxFkuj4VBJ6Mquw0sDqF7vVqSSqeARjBK8VEv4fJhammre0ZyavBbU737X5\nUfQ7aLfv/6SCeMYcZYfIVI7uxuSh2yqrF3veYKZiiNavx8Ve7Y8xap/jMfza9JtAtLOt6vgnUjK2\nY0tIRKdGEigJRkc3RXVQgavCbuILff4hg3SLaZVnBhGWAWV2CBTT/gWgjyw/DI0QBukw2P0qTy4v\n0eO8+qeDpwkbzPkDEvV6wrlJwA+bxlDBBxmCgkD6jX3Wl3LXyRqU8D1AYPbJk8/Ai7kKu1dHAi5H\nvZZ1NNIHI4dRuS3IlHtfzaYGr/2+JmvsjNrtVA3Rtq1x9MsHAwTIOE6+2RYZJY/qKW/AhkByIA2q\nzSh1zpWYmq77b6nx/aONic35PMRSW2JCMY+T5HLVhjQqh7tW5eSGPem7IlKhn9sJgRafYJhjbHjC\nkENxS2TGESqOUIw/w5o3d6DnInjBwcCnoF5tM7l0/rhqkxV1NH4tnNEyw1Ga8uaXKvHynOVE6lKT\nsMPfCAlPSfWGZy+Fx8ztjrXqQBm2eIWzC1+5ctxF8z2ITBViDt6othitax+2/VuHm5nRlwdzHjzQ\nshIj1OgtYd2GkFvojf5/hG79QUoRnxDCmRksNc51B9l2OiMNEntpIzx+oPfke9ZOIK0ixFNJU8BO\nt2dd50MFHemU1q+yhgyeJLhcJk4NSlqx6qm4CDxjG+6WFkPQPPX+Xw1HshenS4V4k2yyFz0nzU6i\ntLO75/btg2GsAQMENk4e3YRZ8Nb/EBQo2cOba80ASIzOzxpVXq8pPqJX/hSMy/djXARzfibMu4Hn\n8m7Iu1/RBZf/X/W7tjv2NcyIWgMy8q0FsJN/i9YtagiuR1ZohjiKb0xkZwkfeVJmUXuCiyB+nubx\nwaT1LAYKlobs+U4ROsQNwY14dQKQ379GafZR1NtJfj5NMMXRZl6TOFaZBsxe9Kbh3Do3udKVzs2D\ni32A4mW8HUwROMXLUXpyMzn9X0rXvM7Ef9Ld0xY61wew9Rrxwei8YVlJgaXytu1d0ZPkJZR23Xvw\ny9Iw/ZIWOgvvmnzyitpH+oJ7hjltq4AF3QBBQI6Of5yvm2EwRCGqLxspPgxuO6U2+3yltWBjfnn1\npXTYyTSBLHdoWoP2orkWjwFfKgBMnimJMfhp6BsdcCa+1oQncshZZk5HtNvUHFcaTcBEG/1PE3yv\nFwH2oCdQ7DNsD8ITEoKwUUZXaZcDvEYju4c3FpKZMpUImMJBTjgTLhAJkoh2ZalfJHLf3IbNLmCt\nuDQhwJni81iJA3bKwWcauwNnhTTTkGz0BJnx8pgM/ttQKz1J+s4zap3Nji/DMKWT4bP4GCYt2zD6\nyIY8h9iyhL3bgmYfmFAJ5z6FgbJcWiN5//p95xzkoKaAmWq8bB/qHQKFcPEN3qsWcFmZg2v+lUql\n5c4sT5GQBsZOIaN6hLXcbuBPNUskEmv6opS2zLWsq8n0CAbB8kzlR853B73iImgYV2YeP69BCO8T\nHtlm57drDF7XvirIQTInsyLhQ49a5O3WPn2NYe9pK6sYyiclFE3efqqAs9oCOgmNf49Rk3erhrHm\nXoGcLrwaPpjYfKiDo2jw2BFgabsKfzj8dliDIyS0e+rrT60k/ZntazsdMOPTx8kzLROY0LUXtMu6\ntlXdWX5uxiDe3mk+UlYVmTu56F2SvQ47HAFj4BWEZ4q9MGTKtmt4BIOr3uongvsWnzQRp14uF/yQ\nsEIDOmaaIMg/W4x9FyttQNgQaFRJ8b9B08otcQLH2oZ9wqjZoF5mkuQx8AG4UbTOVvfe2yj3/kOC\nVK/OfyaiJLTL4Bk2StaF6VB6dz6ZE5fMRxXmPvqpGWjv7zDnNvXXpkllH+cuixrr0OmDO4I0Vm39\n23TIhJUPJt+8b+ODtseo3On3NV1tnoKcObkmRzFAQcwz8xSP2O/+Awqeou4aiU2FQL9joaZcqCMG\nafhZz37qUv3Bt446BoTiB4QGz/LOcEyXolSKV+IfDTZzJl7toGQZ7Aqg4wohPKoZuyQnfybaoCYL\noXLdIad2k18KpeEV/Qh5XI61PN6P2Zi31UWvQf73Df5yGbU6QJGOqjdDQqrEEWhF0Z3FMBQgmOLP\ntGi24v1xAMr8t3YtF6mSME9WboB+blOMgVZqx9tdaxxEMj6CAFR7QHiRldIPM9dz3FHcUjCaUN7m\nCg4aMaceWlW9RKackBQlqVfVIC3MMGKu9dJPSHa4Cs1e60hKD5QidTWc3OwxRXdPbzDOROIl9Ly3\nAnK8u8it5J2SKrFvh/AtF7RONh7hX6Yv0OMbQZEYdQRphuNG+/5joFAN0FViCo28VvzRn+U32gsz\nJFjvG7CBccUtF3/SzJTOCRmeal6KSYDWjrC8xT5nVfEN8ik8dDRdvEFlwENhEa4FI+JxEMuYzpbq\n48k4OvNbdsz9YcLSrhiMu+fpC3iC6wn0AcEsVFSewyI357cK0IH4De2iLHmwnC+kOrdMiYOkhEVc\noue7YWGmUDNCEvhGo1VDX9ov6rx/50pAF5ugzOd0600+P9OZQb61XCZNKaN2cRegZKbtthLaSwjM\n3dg8IRMt+J2u/TUzvT/0O/LcCGRtefIi37fdhEqwA8HXy5FQ3xL99QR7Pecn0mCyjEzQy/v0oa5o\n/L/fOZPvIyI+0r8gmjx84THuroakqvrOGC2y+O6RMkcrXBVv6H2yybbv8yWEWIni7nRisZ8JxteS\nxJx58CGqxX/JkjXmFoHwDXjjdv2yKlFzB5HMS7FNMmtBWwS+oSRVtglPJdMpU9u7F9BRqrtwpZK7\ngo781YZSBIV85g1zZFf4t96jZpfUkd0isrYhnPeozon4+fC7m+NFNs58DXo0NSSbORMjgVNyZIKB\nvD1MXkJULySUvu8QqvrHYlVS+TZCj5tSlt8IVcDuLnJu5sa6p6l9Ad/XlY8qzx5hHR+AxxguC+fV\nlZfw2KoXDd0ZfB2qbtbTtXTRrMbEL1xpX8rtksswuHMnGq5juDh7Cpd9nridkZPEiOauzKxsRRI7\nCVB8jfp+2vI0SjvSffxhG3T+/vmlp725nViP4B9tEdwoMtpgd81dIFSk2rpwdVVlayNE+IpqftzH\nEiB9gaK4fEd4+Fdv+177Xs9wg5T1xLxhk1rJKrnRQ/ob7E3PVHjRnZqbTn1lN4m1OE9tM1tEA2+2\nkcETTxPY8wLo3islGIiY1ixpRjeEQq105WXt3NAEOen9pxBSziJ7znplh3Bv5Jhfd4LE+DH+62Q8\nUri2paOD3ASb5LpWvWlIBO1X0c0/GE9yYkw3UT0R90UCvMSQeybhF6LpbIvS7Mj2N7UIDNktDlWg\neoIj8XOGvhC7rulio9/jhvdoMMXW/BGwffJ3bvW6F1j8ofBgnNLf/sD2+CBwmShcJnktV917PB/c\nGkwpiHYwifvb5QsxDC+USJ/6bS618fIluvgemawe96FOvHXuOeQBO+5AAQJFrv6MOETHaBLyxkZZ\nhdFiSwbWgyJC3tTQthStNYQ2Ijqcq8pTeVjc97GyA0FKJAmWDs738KR7ADaCIAkqHkAD0h1MUnR9\n+FbDRNd3OFbCyEZHJivq2ZprIyi9jlHy0wWhXcjpZQ8ol+UEjQTNjbOG3zpMQoUn113I+jr0Gc1S\nTM87ulMhgtzr3TJ7yKkiezPUaUsGLNkJulnKZEben0CeifLkqxfqUkHJ6keOY4liCtxP6/5Q4+wO\nHtduaKRT0bd1vD7Qqm81MA8B09mkDjn2wISomez3owX/JtP3v30LM4K7C7FcjQbHPR49D28EA3BC\nSofi9nkwue+1K/ld8/Bp4ztCQAyHBZlPEpXaZletvBOXNKVHythVgvrTcQbHjUFtOP+9sgM5eL9/\n9xE8khHPex2eMJlYRYEKPrB+RnCR4F3kLYhSx6no4JF1QZ244aj1NXW1NJE92tzOUv7oXvUSAjtI\n5NlBtojAsBX6hxmiiWktePYzERylLrS2omlaxpcwptQEhEMmJS5IfIZJwAgRbCUmX9p98mOqg8+w\n9ktHLbqhVXGf/VbQ55MtRysucuCbFGSbHRdwch7bzJxArfGyxSrFYvM0x/RcGuQ0IweJsY3RdyHg\nFaDJUVNOuZh7yQ10Tca8Y6CzPWA33cBrzqe+DtCn4xWfVmsJwH+RCrljc/+kmStNrPqdFIscSq8W\nz53TCfMW+/r5emiCGSivPAgEUkmqO9Yr1zvHlr4ACSLSHIij6m0KFFoY8KgTPji0vV0i9UwEVr4s\nndgKGEl6X3JoHup/pIDAlbDW9qpn9zCldTtqMDkpCIFNn5Jzz/C+aKzLPDkhkHANF6WBWgl+k9ng\nJfyDERt6EgaSw3jvDjEUGBLWY+Osf4EUumh1zolZ2WxfKIZJ+LGMlk45NeP2yNtb8eKIHUjfhDuB\nAAL78ilWKyuNeSNEneeEKkJkkrDlWGL91FhvkgJiOVKmhuk1imMe2W9Vq4nf6LmSA4Gd4x1eAQ93\n/HhGxwyqJXiSTYoajr1ECwWCZpGCDCtKnhZbEaeklNh7KnPZip/UiId4U+Ll5eG6X4anovlPAZRX\nuN+BRI3VL/HAyrXrkIeFc8Az6/0y9X31vvZlo/cVSWP3PJd5xmelp/FdD2tmUCBh3HE1kI8w4tk6\nKnk0Sl4a/xLXX41mvrJcZt7UGip9fNfOxSoshDLNQSHY0ZZWzwK2M5r2OOE7lqrYEFek3r/sw8Ig\n4bo2+VUUYk8DiEfP0Ug4bKeS+tJk0D/h8nP81R8rz5pIjiZIvTPW4qaL3xxzLNIkjNMWKnHCVA8S\nqz3F6rOVLcRxizrNh/gKRNTTobKB2QU5le5EpNTqZi3brLiIFrb6j1WgRqrKaW0w+E1Hv5dqUmAC\ndygR5dP+BcwYOAoEb0AIQ1Leig19elwk9eQqk6CHHnHoizGmpwM6wWTvuBscCYGynFSduqniI3cD\nX3Ychq+IdmsbN4Eia09nMLa9XT/fgQ2NhHqmr0hhfHAAGsCIm3EL3SIrO37rLXaM9Tj32a9sE8Sd\no131hv5Jqnl38gB2e7gywOI4s66Yj3/gijchJUOUus4vPZ014cQOnwc3d24pRu/LE+c0Gd2h7b8h\nYiLxYPzxUKLOhOcV0ng/k0dVwgwZX/qtCqLJjIPMWZoKBl9XSg7obLru+lEBnUz6UDcynE0yRAn3\nJ1oHW6CHnGACh2ZHMRkcnR+yyiJOaiTDBYoNhUjJTvuC9JF3wK3mMHo4s+QUKIeVuxN7/7EW2ExH\npSKwlBwWgU7D1glsfu2gNUr9AXa37/5Xj4crYCm4d00LBssDXNw8lTV+za2l/ga0t2pEglG7Iq0z\nV8osC9aVgapXhnBeagIeBGgY/8HedP/j5bUcRcrbCXoYqWLDJf4IwwoigyBL7TQhE1qG6V6O21dk\nbeYFLG7kIXwkr5uJTFy93OwTLh5V871nGPNaVaGP0DdMNkTmOlBt5beUabdqElBWxvILKqOr0ynf\ndBqxFbUpSHTxH7beZxZQfgNPu/M4V1A8KY7L/t+HT91HxIP5QKzr9xxkPH9LclB7bfJLIagBQPDS\nkggrpbBnJjtJUcWyEf++hLMI6rdTXlYXw2Rv098jxz8PBtS8/0WtAesiXUQ5llqkMq6BJh//cbCL\nsq0efXDLyFcJtW6TpSy5YyY7aNVkjKzLNavaN+mANVospWckzBwgT1QPt2olmFsuj7JFeK4Zj/B2\n6F4jxR30unHQ4lDf3ga/HCQSpuL4mJrfNyzlEK7F5fmH+/s8UlJGK+DM4CkXv7Q0f237spoSn0dt\n/TI2zupItZoXFpvO3flbGJYpheAA5zhlAnTD95j6twP6V+5BOzZA4RYKW471/7y+851slUNQaqXQ\nCIp9B7OxFjblSZpJV/weOapzR9GGu2WUL34MtsBCFeaQzFx2MLNzu9aSthoU/PyiFjk6Lj/wLaN5\n+zyh95016WymScCXr3F2EFVrj7LC/FwmkAEIDVDNwfPJ9mpoiZ1919PXirdGiVkPuOHPEcMapDO3\nsnb1NVvSkj2CnbbZThL0GPImnc/t3exEY5SXPx6ybzj6T94UQ27BvPByC7kBOD49wmuyviRXcl2F\nIdqUOSbxaaiH5egftzelDJOX1vzyR0YubGDtY5qv0Umxu0Omqb2Xt9TMZdYumooKtV83gZxHVpXK\n99GAZz7+qyLJ9F/AWEycCeWMqgBIE9erlLg/tn0sN6avwR2/nrSFNLc/EC+/bGOUqJNj8z7IBPGB\nfQ8zYY6PrRwjmqPZWK1+Jv0AUJSyUZhJmQcLbZ3Z+Vf4gcrML1Zn+OIEWcvmRV0uMBfgANh4GoHQ\nooR+sgjc3g+XA513j45GTEqX0J38oIjuuejri0o0s1qV3aX1ZDPVFs+iQT5SOlBgaFzniZFnVR+W\nCJMWoFnfp3lRaIAae8dptvQ+z1lb6WbF8E00LnfutS8fEYN5BAvFUShschcve0aNbO2Fd9ZwKNou\neIUdlpNR1xw2YRi6sS0bsxHkj3w9dAhof4Ive4XDr+wdEZR1dcMdReAFmPe4r9M8fAC8TcD+ziCs\ndAyyiXjiTseYpE/SqL45QNnUX8wU1SY7Wkmbj7qB2lFEudgCsl5DvKwNnwf7NPmKtQp4fUAIqbUY\nWawf6h6LleeFJFFbANP6KS4s18rl9e7q45eRXFkkz0xtSYnNtMIqRatPqfLqaYYHtQVlgdJCV+XT\nyxBrVvKWjtS9dGambh+xqG8anwDRaBsvtYTPFjz4EK96d1dxSwc0cs0RZjzQWzJQX2MZkmVDrH9b\n1IzsV9C4oh7jpnOIXc0TE6wi4z5ZmWJDp0R92M51XM+2/JLAjTcmyXbZC1ZjT0uYJasHG64Y0rh3\nsJwZADr6qIUiYINbRVOTY6U3f/Ef+mLQdp3FT/uIg8zZJ1i5GPCy+N2QtXSl6CYryLARFRB36LaG\nUyv0AzNpTVkQ87Y6bjQKXk9PD6vN5epC6J1JmAnmvqK+MlsOBAhm+9pDIdTq6WOAyNFNsuYuo8Xl\nBx3fvu1Zxq2tumbbRaA/i8EDFX/m6ykEO4mFNU3Pl8AV8tn3F3Lf7D44Kmyyml4G5sW/9BgPRbh7\nThxIO5EGz5VFq06zFacwQLo4pLhRBzWLoz+UTHQ44EPlr+3tHCGLVCTWNIge/jchsyFhcIyREanS\ncZ+zNPVhYNTHufWAbKLcDfc0yvqikPWjy3YzXgrbodebfAP/eirsaBJZu8NCQijcbn7MqRiLl6L2\nRteTEVsUyGhODDCfc8VHTiB+ghs3tvTA7+Lc+AIh3t3hNDVH/PH8akeoG7vA3ygHGO0tq0aWP7bp\nduwFCxjfG5L5NaGxRRvUuxDAMgYGInp+NK1+q4jQalIyOLj0kbP//qXFTUaZ9n7Bg7Dp0ujKcqcg\nWv9m/ambWSMtb4uOOcUJT+ifnHmxRO/bOGJGWJ2XPiFn1EtK/ZpyFaBZE9p1wmm8hONEAyILZwU0\nInke7A1LhPXZtTe9ocL6HpV3CZ1XPdIQ5s+iZvjkez1lXN8t1Z2v5BX6rJ7LgqcOR9e7MIgeqr/z\nexY5taAnpUhmG2oIWpNjxhZkKyZkhjpoJu3Fk8j7rVo8jphKtq44KyhtWEk8kL9N2jjzoT7uolgH\n+JObgjkLvRGUcdvWzfL5ag53dRhXyYZsMcON0z9wJmh52pt4CN579yQnbOpGxqSGRmxZmyhFdqeV\nl/p3Gik+8kOPQ+gyvucYfwVhItuwMC06eQ8nuLiG1OJXO76XLRQvEutgU89ZUaZERvWyx0GamYV0\n8nHuCgqCu6IcTwqlQLhrmqM9wsjF/D0T6x4EENrezJNhCMo/69srqn9pE3e5QhPeu3yH3aeqQ/Y/\npYaMArkanCFNUV7TlOHYcqWP61nPzKuVcbmxrpXHTHLQ+KObmfOe5D03iRRGxRl3Aoabr4MUXLSV\nmAWsk9JbnNnBa3oBDusnLinaCrewLFqWjnSmsB3QZGVyxEZGV5ppLDHayV5+Ojy3YVHSdq/o5rfX\nELHj6S4K1KuTvOKug2G9AO6DdldTXD889WyZyJA9I2rl8oOLobw34Z6lr3RqTqZVxeN3/qkMTmVN\ncH8yYWfz4Eejs05L2KjwOOMy7+WWVSDz2SY2Yt+hvoZhaSYkwWipjl7C9s2jMkePlTYRFsCuG4bH\nT46WPqptd9DjIKj0G6IV8Nb3EOVRMCou2kHyEsnHxaK4LjC1yHDP7GRoy8wGHf+03rV02t3T7ZQu\n8KXrObaY6+U7BMIMpvjEmouWQBSg/TeMV8gYzzjMBCr1CjU9VixPiJ23jAUZ6PC84twcOwrPjtBJ\n9Ps9St5u2HpCF0R+dQEiukM0q+ig6+ZfxnqtctaveuLes9pQh6VoD6n7YWGkwVhJWn7Zcl4Xrvof\nb2EestQavqVV94EqwxZw+J2l0wwyjStduogZ5nR465etBuSmPyqpBEzFnv9m/EnvbV2KYdmUy+Hk\nZn37bG2q5a9Lf2SCz2kDknkESUlUo42vrqlIJ8ZljplfrHZvylAgNE5Dp2l3vqamjiMsGkmp5QX+\nc0nbzSWouRIuzsoB5gO1vkmZgajbNKZNkOTjXn/02QayhahheTOXQQ34eA50nuUFBIKcVSk9VdjT\nxBKiCfJnXl9rbX5mY5DOCXxQzH2XNyq7O1f8EUA4tXtYRpGUQc3tHWdqhQpvQblU1PsKFkGT9qCi\nJhg0kt/bLsRiOrKIF+nFMGNFLXYB9pf2+d97R31NRe+r/4AYED4d8y6GIOCqaplPjN2GFmdJmXNx\npDg/PfS5R2trl040plZ65yP75D7vqwV8RYw4R74OX/KMt5rkub4heCpsFWaFwLmPfDax9NiA7uMR\no5AZrTNt67CmOlYKYKFsxPfJx39EDQdqIoPHwZsaNCREcbF8UnO/uuf/stoAIMMKzOYU7Tq7wk1g\naoYuHsh1zOsPq9M1dsoLQQvrIVT6mcslB6L/Ya5HfoO9xLwShFQJlDn2BFP2bk2ZiDwWPksJ5AWQ\nxPyXvs5gEI7K5D4VUc/r8JRWeTKahIZC2A5uQ2l8VPpWfYQm4fXmMOatljtRnW/jUxjHT9oBNKkD\nqVxOF7InA9LrqEPIf6W9F26Jn9Je3Kj61enEkQT7N8C0eR5BO98mUBZsaTHA9eO+mZ0zY6yBHH9w\nIZIhemVTpxVzfFmz+eyY+2xzs1QnCrg45RzeEvUu0GuLNpkx3xg2F8iVk3kuhkgVZaYDYxRQML2q\nB5GxzJuw/4Po04A+WUBVanjXT9cSSB/HkPXdN4eynZIYzpLITcBi9mrSDMoFtv+a9I3cl+O8DdCa\nqYUWNoqWg0JsUYcTLCtR/Cwpe+rhdBoyr1qV7Pb+2kMYHZ4CPYgQqlXzIpsustkAlJjiy+wK/vBl\nfzqHsdM+VGJuL/5Pvx9Z+hmpNZ+/09z+Gl4n3Souu+Zna3gXbBPm9hTEjkEAHqWRmKIC/tcpnWu/\n9m6eym927TklGXpNh2gKnbXQMxUcNaVdt/EyYOGaE/X0Pp6E21GZDj08HgjvlSRZekC2FFww9ZSL\nFhZmCjWUr77qriZfhmaMYo38mtWIC307XLh+385Y/ByGaQkEbR//qCjLSMJSAOi23zGlfD9alyS7\nyzSbI+R1nKYqR0pUJVAv7NnRxVW6IusZ1SyRxgGDUOz2nxVk6QmOQBg4pn4OK1/hkWkCdalkr5VO\nle3IXYWZBupCe/B81dhLl66IemjID2jk4M0Fob/2a3FPpbeoiBIU/la0Ykmi6d0I9RMhyKhDo1NW\nH0kHSRxDD65uGyhx2iasDN+oCCmTMcVoJoAB8ihQBapgDRQKkiJgykvor0GVGVlJHThFcc5sOknu\nEcHXIM5pDSiYilxbV1hOiZFRi0zfKN2C81oXkcJh69IWA7MEPvKhP9XzewiVgwyw9bE2DTr+vqKJ\nGpKPhaSYb2PCf/xMOkKw/2IxZy0DvldZQIz/H42mRGnxqK6GJOcbc59J/CcZ9wicZ0vlX3dvdCSm\nG/tCgWlIuQo2mBqDLEoEyrSrg29yjYYQ9PEgRsJIeh2C2wK15n5uJ63tt5OWr5DLFThm3fkQbXgA\nXzkGaTJGsD5Gs2Tx+fBfn6UyTOK1IVwPAN2zlwML3qEovVHmxCxxqtRzmdIHf7GFU+QS3eF5ypJb\n0Wkqgu0lYdjYtGF1HqJZ/w8g4N2UtppxgUKvgsuArP0ddOyJnm6Orag0C+mU1jVJOTLJsZK9rrwa\nVqnj/xAt03OsMP7FfJJHDWN1iM0JjKx5TLVesJsyMHgC3fgIwfs1WJzkf+Jfi9zmVIQRRq4r8iWC\ndIy7DQ0oHJAiYGNlibIGm0pzBxeWw4gNavG4UxYrnq+stF1WW1gQ/LowmenwG0Cjy8d+i8DiU2tx\nqE5kkIRLYskE4J6IlQRKWkbBdjunTe0d0Y/x9vFKR5vbTOuUbFIiw4mrAwCCuC2x2SudYBNzDkAb\n9mqrAKsiJW2MMW3oV8nAwZmWBbAr8VjbeR8fRgoB65KNf98+GVk5xezWu6x/lnr0CSqNhgP8Aa5w\nQB+C8B3rl00CAv4LtcFA1OSpH9mVbGJT9jlNU34s6OS66nmJrHTsunWjWwfVT/YtIc070EwUHhu3\nkerJEV9OAsm2mblaCWXdeH3oJzAWOt/S+oMvNdV2qbdpyyJLWi9I1SxLtlFBqPLUdAhPAkz1jsLo\n2NRCg8YRSi+yN+uNbNtBQocjb7uBxCeT29n3ml3LzabvmlOf6To0cuq0SNOzxR9EqwHpiruBbcoa\nMBc77aBf1a+9UX28gIncucc0fWsN1jEkEXvx5chO+sTft3RXfVehJrpbpg1g8/SV/s0KS9NxY3GR\n+TNV9hAIdzH2xpxdAZA8rSqKcNG8BWa97giCGGom7uEEC7G7iZs06soDK+AxQRAJ+WmZZyXjdefk\nS0xqti/2PLgu3RiskjNwJldrE1I0uHPnCXTr+d7iBEMi6hjRTrVY0V1THygB5Wz3ABeLA5eOOzeQ\n8Vi5uyjlKB93QlFWHH3lYO+j7VPFOcfCLG9spKytNXO+3ZMuZYAEh/nurWu4ElE3s+omZ4Ov2r46\nEPwYJkVSjk2kGvj25OW3am+nVgLQqyod3R4eeO+slIxDIlI+vEyjLr2vXsUl59o/8nNJajFRrNeC\nQBKbaVlwgeYycDwQiAAlX7U0TlyCmV8LvO+qMuJA8nURMapsXSzQ7NOWsqrGyOWi5RpvFeLBpYJp\nlpXLdwJeAfpbP5TsqK/x2BBwqCw5+v8ts6eJrk7ZnXlkdQFfppkElqUPdjJRdrtJljlexJUV7l/S\n9EDrkcun2vl4KeoH970x/9UwnhhlWeos67t+L7KIn/jTSKVLCFzmgUCeWZOXApSSksada+4I4AAt\n7z60FhuEx6Wcbv5oZ1T1KOEQG7No24iw6ZsU+bkit31BeKNlNlf9iykLR1hA+9n4s/SHpuFH5j3O\nZSNjGYijauXyMyTR4ixS+lSVSyrpQkorw8J0EKC6Gj9/QrLDt12EFhqRc/lDsV3fcl6xs9O9V8dY\nA7lvM7Wafixk9rc43bfekx0ML7M7XG4s9WK3csfpY1oiMozMgqXOJxKD0kuzPssANEUXQ/D85/G/\nnAGdrXqPPiwy3wr6+JocvyteJL9WBanC4cihtz5nna5s1tFdbiuqfysaBZfzBV/6YcTDZKwKvTgm\nqZhIglOMJ9yJqyfJq63r14kkxSjwQMWG3RRiWcLLVOKSZtthZfeH77m4D41miS7Tc/HemOyqdMG9\n7Mw6ogHGykZ/Y7w7Q0wt8JRsdQCYRQQ4KdGqy4hgYTg64Y3Mio7eARXUZoVzr/CL0MIkbX3qQrSJ\n848dCKoRD/hC67cnMPZtbz1gXdq2Qe07Uf9HoKEBU6yOw/Gzj4NiAuP0mSKpjqY0J+M1wrQvgEvh\noYxui0aJNJD3C79rW+WPGfmfHlhkbxLLK4xp2Qbd3PTJR7sOAXqMjlWayatca8PLqsvo3/SUsDOd\nact9UheGGJcJzsHrFJGW4uJVKPja248SGfmB1ezEknT0Kn77YINW3YbBKksXNzXs/TRZwXPPmeSM\nillWe9EpxQsik/xmmOYNuaJZqBpJHWsO5zviU5Cqmtej8YXYjsiUzS0X6nwa2joG55fD2ePKRs2c\nD4kZc18LH99zxLxqlAqef7Z7VbPzF7rRytYhJo3++aDb/F1okJvnlhcWdE8oivy4CynFXCq34Dzk\nZddT5JfNqsqbsjI+Dvnk1g460kimaqtZiSlBWjGOWPbO5Q3FefJ2yYguWtBjOhXLkRhmtS3Jqkyq\ngaB6RKaxgzhqO7fR+aeq1r7dlFxYg/rwfgT/ou0hs/cLKDT2RzS9IeUgL82bZiI3uwApqaOWHjLf\nYSHAEZHmujq+y5+hiIUudFbVXYop0+n9iz8D9T08Y5aZ8XX3jSHKIoP+lzADFDe/st5DYrqf2V5W\ncYAuMkNmBP5vJjfK5rv7oKycQAyZpdD3KKir++RKXBz+ytv6KDZ3ruKbihq3P45XWbI9LE8M/NAV\nS64P1J5LKMAjAAkp+vYYdgjlsVqQL/Xbuly/xdraRbc1pRq/1hjWinOYOUkgFMajLAThGgfpYUkE\nJgYiVJsGajIzDh/jbbxj1TYpCLVE6S7b+OmyVEZ0T/xfxVDka94tS8QhS+UCxIXrIBfU5o/3SQ0h\n3vQn2lPeB6NmP8skmoExA7DVm82EtJ+we2cyJ8urhAD9sVqsW78f4S1IwcxShqM8Tuq8g5BgivVO\nX3JMd11qi6nKODzvG//MJffmArwG12IWCeAjpSSYpaf+6M1NIO+tY/2ZRIBgaTyaYDoaiQK5NVY4\nmYcA92h6QkfdvQXPFJAy4ys/CdO1Yrj99gjrzF+9+gtH5kj5guAt5HCh+4eciVqTfzSfmJaPLQlj\nUw+nQLaoq7hw9DWAfCut81PbxqUUcrVoZYdkhuFacEbq1fsKdSPr9w==\n`pragma protect end_protected\n", "num_lines": 1194}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nCgyLps+SA0ui7dPkXtm83wP9WSUpTVOaNUUaEiTx3o8bDibppEo7uXVLsKORYUGbahjOTDE6kwIY\nyzdcsZuJjQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nls1ZVg3oo/4jpb/tGSZ67UhcCiJPRZSibleEkmR8FGMVr6khAWRoF6kYXnp1zsyHU3zpkX5aZudH\nhQIPiuWIX1ItHdefmGknlXR0g8ejEjnCuf7wiNI29U6+5iw2QftYNsn+9bDRp5kdheVUcuxELJlA\nXulkNd/ln7GkFepSqYc=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nB9jNLech/g/tKNMUKP6f+gjxZsMheNAx8UaJ4vLJVXHNXpNxk91NHRM3Xm9hGCv9VXOliR2a8QYA\nPQ1bZLU5blYqH+18qF0ZF9Jo3IiF0g2nN4gOYAI7m5j6VqkzD58XFZMLPANE17Rohp8jENs7nh79\n49oN+0loRI7XCt+F/XHBh8FH2rSJmirxDK2iqylD74LWMeTBokuvbg3zEGTXe5qvYmMaRiXcTPZB\nDS3JpPd04FW7EUk+5RM0Kcu0Ly1TuyTKFn0mEksltOKTCKOerop73A+MOzn1eX1pf23lWhgzfN8Q\n8HjhN+i90Hmn+Ojdq+WsQMHc6+n0Or8KFbFReQ==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nCS3PEjLSMy66Y5kMQ0y4fL/X9nvJthfWlN6tOA1JzOyIwzumGq0fkllz2YtjUH+WZKf3DOAh6h50\nM/7oiAgx47vujLlrhLAvEpjj8WUfQd3LXqVk3NCO1ki3s4QNBrpCKhg86ykdPOiLuEXDkUt3v04y\nuxmO8exLVDFMG+CzMLadbS6QzvWCMXeAb/FFPfVqwPMMw1ByBbbNZPDHX94DLgrF41I4jklsrd2r\nI3FoDtv57i7fvGeyrplt+iDFl8lNUqFZyHP+5+yvGYA60xKn+8Y180eYGnmQ4wGtQ6Kkzn55UAKq\nBjhfYJqchzaFN68doG8FMNl5CP4MfMmIG1TAbA==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nnQe6+EVbiKYI6EF2Gkjs7kvdzSmGHXU4qtFfR2dYFwHCWHPPG8cZ35Gns8SCNITeaBfeRRFcv/q3\nUoOZpWturDci6dtPwvXGTKFk/2M0wDGp1JDGd5iTwJk4WyDb6tdfibGrM334X5OHFRDy3qX1Uovz\nSj9hOU/EFGjRS84ag4TVcz9z1f1Y+CgW8Ym4KNOI8D0oIv5DmjP/nJr5kVGL/WNmhRB0h+vtCoTs\nUcGqCPC2gQnw0GIBNKrE9ivvsGq/ACxJuuSLwAzquqUInK187ExgWQLiPHhTH6pfZDqnyZpMvGrr\n9OumyGggkggl7j/JE2vtz+6aHVWB1956RXcbLA==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nVPB71QTo5TspzkUp7HQwn2zfRQ8tDgsnLTLdZIsMOrJ+Y8fHz9hexHBR3Yhia6VnY8XCYjgPbAId\n7QK0Myn0r32s+olwHQ8M3jsY7WJNK96AiGDDRm0HHR2rAUT0mbjaG5Vdc3kGr5OmZ9abSnBv6qJl\nd6qqhUFQ2fTIk0vkv9s=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nIOa65t4pEqSGhDPlzgVIxaBhM6TFiSGG2C8XLJL6CyEFm0OzjlVbdnJuVLSSsqeN9g9q0ucPVcBs\n0MDNHCUMFAPmUvHCALV35V9sWsxZnNLruGv6jYCoLT4RcYb/Hskha3PIaIz4tnT++Oplm8SDc6KE\nj0p7EoQtGWfdUwtiBHuUQr6oMBdko07oc+MLXZy3P4PwN6CMYbgRTZvUcrJfxR1JLpjpTlr85sRE\nQCUEGnVHiSu2dgyZ1oOqfyUJGaHcNOM13rm1E+h8I++ksRVlalZKIcrckCfC48c5nJdrthR+8rsa\no+k61kcLH2NbhPC9dAejCTOCHyq4j6eKfXBGGw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25328)\n`pragma protect data_block\nkSwfaOQ2lUKsMClQk038C3qrnU/w3gNGhmdlLNfR9sWwqt9+mhQ5FChgk+V041Zn4jr0vEzfPK9c\nu3LNWSj7Kuy7mPDQPF4wc/gQY3v1ZqRVfjn2zXECRESZ7SISVb3/zgxGap9q5OV9OP32RkaV4kdr\nws8IbzNgdjoMmUEPWIST7YMeljelbQVuNUUiauyLev5wd5EZQgjtqiLEePwttFZFz+wDhSrZ+MSh\nmmVhsv4hlANMdsmgswzLepN8QpuS2x+4bV16nI3UsgySXVY0LRP+KYonO3zuI7oGlDGAKq7rVAA3\nosLmIrbqcv9oa8RF7mwv8MG56fHnNtMapNiNUP5a204RBeFO8tYuAT8VwFE66FWyg0x+SFytJzKX\nnDz/x5eXYt6o3ivPJ9zrCY3V2GzhHa8xLWUdmY+f0t06M/pjIKnPlBKPRL27dlEboBL1WLxjolrb\nZFxdGyaOrUIkqkQm8IlHVFmnZtXeSYrONP35eMP2kL4cGqUTusPeoqJ8DoPv/15TbKPwDOmaEXYn\nOEGzSGJPYZPw4+XZbtGAj0kRbQ261OYzNHDs3X7G23Gf83cq2BWgy5D0KMg8x7egPLMpaWTEJFAo\nwHEzBZROkgZBRyzx4uuOLJAzJ1Ww6ceB1GR8wqI1RSlj8gKQ1TwofF5FVToWZLT6C3Qy89q2zVS9\nA0mSl07IkvpxGwr60pFS+XBimis29n5s8FX1+Y2s6ykhocSOf8NQXfkCEGy+ol7sHN6ItVozii4Q\niSDgC+BYBApCgZz8ak4UXWCf4OdR75O09s2dPW1NNUB0LmDZ+JYg2+lHMwwfQbN8T9npoNochopd\nGUxTp/6OzrzXYuXdCTP14tOiLSckvwYVGLQRUNEHZFUjoAyI/K/pit5jx3240OUI/mdlbVjdEtUG\nZyZ6ijoMx/CJC0RWukb6rnM7lnnhpTUapuQNw9WieVmTSHV397OKlU7n+hVDrAOVM0fnBQoXDeAC\nPJlef//l7tgQN1x1eqzQkPGyXOWazM8DwiOoFa0tqkAslzrrb6K+PMxVs85IisOolgJv4q2sSZdV\n8RYCZM7MjfQlQzFbENfRZbZsAYj7zqKAdfnblfnQtX2D7QAAZtAVZbtICaIF1IOSNnsCi9uxK78Y\njHAC2RNWOwn/P7vBzImG9xwfIQ3kJklicNBdaHlR6kV22DiWPytbzi7H5Yh+1OnunmSMF5aO/a1P\nglEwFosYm2rOGqobOtvZdtOvQZbF2TLhNoCULxpUVohVdo53ERTsmRP3+szwtxMpYpRMOSIt1tO/\nmsxP5ho7MgE/Cc90lcabOMXU6TwV9GMz2Ec8YIMp8yPLEuaGXNyAKwcENA7mOQabA8/QNE8TzFxr\nzDj4HnLuxNA7bZFjKzEa951JtnbjQteNvnEOqy3O3vneTPebf0DNwD/PH2HzUyztYeqCd+4Ke4dl\n2XYcyyJlr51kmlzHyIsGKooMqHJz+hNY04caoQWD+Ev5YGjEMqMIxwhmZIm5te4ZzfunIO6qNTcU\n43BM4NF6J3RO7yg4ITHq50A/iI5hpAQKix4j86HXuGTgrvH7bsVcD2RZlv4gBrOkQU3BGQPAJeZl\nd25lZzULXvWYJCgbaXnlh+1h/NCjB/xX8TnucsxmmHdRBOGDImMff3FDsIEnGC0nEiFLP/fR0vhE\nog92bMwB4+f6Ja/JwPj/hHsU/Y7/vhRpgrJZFtljDVR5p6SPzfqZ+d6oqCyffmOU1mzMzEWLf/T+\nlKoSQNrcH05a6ts9/xvttvEnJoUmUf/H/09aoExwqbqLqI4rb+nzL1Mij1Mj5wjZqg+RzpWMw8fH\niJRUlCev79gLIKjs14oiBS/tPttcY/zs2qHsglefkqtfKIEk9s1OKKBE0NXUYo2xaULzpfqKFTo5\nEFsbG/eTmyP2NlgcNGiGzT4KFsKcX7sZCgsrutPwhhdzOBA/8N+CfVeVEsdrP9sS6ZIQs7McQ/7D\neNshaOGNMbXYLbebelDWqbszWYtgfVphDQs3tNtemJrIcmtApxUA/7VfLQRaw7D19ar4E8ozZz5P\n52VP5E6TvxR0qnt4C02mR733IZNNNYzEN62jdN7lHbe38BYdDWlVSjQ+j/iu8H9Uw1c9sRKzhMvt\nYSbje5593WOrVBZd8GSLK+W2/0BXU1rU8o321xmPD4KzgPFpNqOVlFZBVpuhz+66JTzg0dN+hk/t\nFZhN7JfVIRWniAPyHn2JDFXcGwD706qDbKu+155s7n+ZohU1JSwKxTvrORfYyvnLkkGm7fJQ7YRL\nt7BfgeyatEZYG14LIXAYjvgfjq2wtToa/TvQDGhvQ4Vm8nZzgWZcwGS7TJsxAg9p8hrMrp6rWD7q\nT9p4sQFyZjXkeGQMbXKNj+j76S+MV1+ZlwlpMQmax83Q8n0eG6krBX8W07reDMXwDi/pfHZnR9be\nwf1owb0a9mwrd2uTVsyua6HoiqBX3Pal1FZOUICvgzVeRPQjtX+5z2m2bTFa9Husd5qgJtC018Kw\nio6hzaTDp6k0pEhuNWKxCu5MYR5qZsH1QhQI1Tvc624IFJ/K3Ay7xDjun3verJ4OUefTvdYz0TxI\n3K/tmfQB5VfrezfWLkF0jHF8SXCf/aAil2oXjvKKfzIV+wTzXtKohwD8MEfjITbrP8BbeHj4Qjjg\nGdLwOy1xTGJgUSS9oGRx2/393scsFP4J00gbt2yy4ZaVBbdIV4oPk9/9nJniWlCNrHYcY0VkRd3s\n2h1bfTegZQUVLvAzHmVWExqww+QVrN72GuinDns3uQJzkjW2oXpXU1+I8K/xOe0aOZgVL57N1lkR\nL1i82WWSl7WHMwreThqjifFVASVCTX6sg/1eVK52Ab/QWUmFtTRLUWIOVBozlcWjVZGi0/sDgJfM\nXBSZLF6a9wWTbhObbri+/RP2EJDzxBS7ImjPO7YXCEuHFqwdPBxr5pz9gOmjeSWjbTU3TD498X/8\n7PjURq5/I+TJmVdTEm8qoPvBEILhT17sOnZOCqN1sxzYTUTwOP/fh+5SFWILs8IjXlmtv+wC5IiW\nzInQYX1V02BveC/m0fmFsn8knWeUXWW75GIw8voicnX5MIB28JxYzTqzCcaiKqRigyYOs4Osdese\n1rIQSr15MSZogNQA4Q9uqpVZIJiqX0tGTYJRAdmcBKUUxy5OaslK5g4juCb+CqT435m4GHC5QyDz\nxUGN/7A4jI4VXcnL0KDU0uPNygMNYGjlBIIeSVJzFfLW0SZVCpssVP7xEDYv9oPoBQRrOeKRQ5qP\nGKUUx62dOlmuZ06pL1CFyRCnptFpfjZpiy/u0X9DAKJVLS28kyK4E4aPAlySXPnAgykaXMpq6+L4\ngwQTlJj/RWrDVVZDLpgDv/dSjiDLi1gzYGXu6QoY6yv9kehm9i/zGfAH4Nm4iDp3ttttUcdsGJUY\nOX5pBJJFOq7Xm2WbEGNOUKF4n31GtBjRcid3c6qrQAnTffL/kjQYzMWjjxtyQ4Gq1S8SG8wnZxh0\nLa2V4nn9sNN22rx8nyxr0WZxxCT7FRXBfRsyViBXA/HhwUGT8UtOaucltcNOBKQ9aGEPrXr+bnhq\nCEhMfhyJPjgUKZpaam2DDDqz+BNXGTJ1q3nD4XKRahlStabRjg2WslgaR0sUa4f1P8T98v4+AyKA\nbzxBCXiDIjjI5UCH9o6n0WB3psXj43WGP7Bm9PfB/emi58Acg56+fqEW5+VjMvHJo29TmFL8byAB\novlmPIyfC/Fii0v3LlYWAxWVA4VBG/LpFcgo9qPW+Yhz7sSZNlYWYRx8BSBtFHPZ0UDQKoIXQ/Ne\nRDObMN/WxcEJcEwTRilhQhKx6hlQ7hinqOaDY5B1GFPMN3gTpB1dC5lfOwDwQ6XQbTif0MUVz+e8\nRa51wUr1nWRmVvnL+wl6eX+bie4IcMHbk1IifHUDQJLPPCwJqQ0W/PTILBcdBSnfkn8nQdImfOp7\n+/WRn+WQl5S/4KjVdl0zWtYEetGtJxHGs8S/wOZJ2nxSnzGuFeaomei8jl2gP4EFf/WIa4OzwqKj\nz+2uN4cJx2vlfkt2FtUjeUovD56+jlPthlDUP86m828E6z+HVX7ZoDEV33LWhlQsHyKkmoiMWzYy\nHdVJabgGfyUmXygSYdEqr4ED3FjHYpkAtC/7g4WhqFvZ0TALvPcdB40O9TF3LtysXZQrhEeY14J7\nKdzxRRPsCltAu07xoEYgxU18+1twpdaZZD+XfOXHND3Y6kE3bjIxMBv4dV3AHbmPRivs4kW6H4gT\nFVcUWuPssTRNyv66CLVgv3pLFaGbN1fN1GBG2XQeBv+9kUDCq+rBrqgBwhSj0fncbah7q13tfYsi\nqMGF8LzDq5M97C3HMEMuM4FfQBc0zP81oqicqoWuBh1mhWihKI4/ZlaRO33f3t8wPtZ5Nqn0G8GE\nUNlv8CLzYvaC7tSaKV9gJySIfJKQt6yEnk4CGj+RVRu1UA1/0Er+TlbXajVybaQRgpbkQWq58eU3\nyOaqQ1Nc6JIJRNFNfKNfxWmJlQJCMbbGoPS163X0V0rQ8l5UNfYvEM1AJnntSTTZpcfamyGcrk1F\nydtxqkwn/hjqbFePqd7AqmcKjnKUO8ZLM+mkQD9gvnYXy8VMY4JM3F7mjELqgskwNrDfqk7KYp84\n8H92vTOvdcxMbuELQOGt+G0tx01omR3v2+zCUYlWznKkQJTzg7hSduynfrqjRa4s+ukUMKw9nW6s\nMH5T9pqhfXqizyUg1dFErIGw+8Nn+ezQ2lycDwRRDq5Q7kyS6RHPjMeqERFvlIbn8kimWfeQB+gd\nDYrZ4Sea0vnHhZ8T7nYIWltwn6NkOjxMONqbv5nBAXBhf6rU8M8Upjt6ub1Pp7fpd5Z4O9XOIn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XEmW6zwtcpFPQIxv6hxYxwC/spdTrLGoB4ILEP+NODQpYsELTZi9WLQc6L/iOQgxB2qkazE7\nznpYIqd971MHDyIBimsMsV2MIlfJx+fbxPxgOLnlldWhu0vSMbvH0tKsCaqq51bg80SjHoTbLdRI\n0RXKBNHiY/hwNrAd/uDNI1VArQPSevUJihWecel8HQA/qErqDeuyR3fvz+etmwA+wEarTYrJTqBx\n+0gxN2lWRXXSb1WzVOI/HRxWhUkbQg5KGLcd6MW/+7yH/J74DfKqSSUFnkbQtw4D3iiyobxCMVEz\n//3tVZ94deYB0NSkbNhQwYVGtoYwo8MnoIs31fabSPiDq38l7xlx9fp75ALhijgOEf37nXuBTGRE\nroDKkPV2KRClavVRGPGPcF4rrGho2vJSIvjU67WpSxyZ/hef2sjInD5/VTfOHdjuUA39/udvN5md\n5PU8SA5cevPi3hZnv9LPMedfbs8OfRpINO1/cETQpi3uun7In3BwZIys6d9lrhe0okK1aRQK8Cnh\nqnMJ5Yk/vCW1DzxsS0YjsZ5++CKwZzuxv+pfhRoA360JbNFJ2+BnWfrTDAYfBh3X7DTAN41eWGJT\ndNIaOmQe9nucKLsM+5bqmytNG1XR3x8eQfnSG7y9u95+a0KSMLLs8vDW4TMjY7wKGfjMrcLBXALX\n5RdBS8d7iquImUPCqSe5fyfq8aViMuTA8JyRpN7reZ7hr04/nzBj5v/GYAf/fcwf9/zsj7pkvu7Q\ngA3tRRZn7bfQXUAh4a8r1qtWmNvSRZjlNWf/0mlhv3MlEmSS3VN0lREGa6jOvJOOx7rhOXLSBPTP\nrhkBwriy03trzUP0PVLbhK+GHV8SATZ0qhsPJPvKJ1ArUmrcalWO7R95YB7EZ30RaQUr8LDu8H0H\nxSfvBDwdMyeOuWz28PLk4bAYYi1GFnYL3c+9aBO2/cQRrQOIR7B6zDTzfn8ZAlxv+JYcFcA7cDdS\nneY1+v1AEHA410TBSGLSJ7W603q44z94d7QgfZKpq9JGZ8Ss+XuzuocrjtI/CwzxAYaXJAfyCkLM\nvSecX9VlMHY48b4tYVPrX1WJPcL5vc4bTwpv5yDhIsqRRo4lpshMtpmjP/LBQkThJMDwD4Evjxd+\n0Z5fgZIhj9Cesf9L2z7FA58DJ/shqe5H6BxQXh5EHfWSUwr7+FGISDY+aOXzkINZDYyhT4Qc3M1d\nOp5u/YuAiJwVw0oS31g6x+nPXEvDwGDKIO0jR6+C30Wqzb2uD73ACi3CpG0Pju7LE3x7sgwWFaqP\nR1UHgtF0dYf7H2mg2E3Jvz0vEn7MLjcTcCLLvU551616Q1+rUxIxuCVVppmXP/ktQRbLUsMyXdfy\nEN7oeJSTC5WEEe+ruuQFCDTKWJdT2y0pdFnqTf2ppYzWv/n3pGBJxEdDfXYHh9u/s0uBYf4UjqdW\nkys6LWD2yMmnuC7j3ENi77hkb9Qjl2aJb4q/BM+soWZt+ENkM8mFnzNODGlHgiLZlOivoIO4IjDT\nBguf2s76miE8Y5v7LW+4nz7zaAzAZZrtrzoR8mPrEoLsw426l0yobffsmLCoxB0Myjxs0J/P8V4/\nWHvRj8uQlYUXrrS2N5l1TWLrnIRYqvGam//oUfGoVR04Bsr5BsiUo90ulRGVW0U8zFC43lotvhXY\nI9uIv5zMi4kvR+nv0IiHkozj516FuEBJae321TuWKRqcMNkLJjM0K4k6x2V7fexudWDHVhskWRpt\n2uQAgpcdhkCDKRctrzCKI3GumkTB6yHazXLoWdpVJ4nlq3TwjQiQ+FOK8VG7Juv9qDoWxTEwXLLT\njtJla8yzDow8WL7U+/9B877wQveVsQ2a9OJ0avMJCtrCgZt4IXYX/lmVkkIYi35HVACSra0Yc1TE\nIpiIqWFNdQuwsaJe71w/LZ7wTfkjeVGaxK0A7sSf2+WmYCASD1CkPFFrFdSXvJvK8IUNvAZt+gk9\nPgN0ff1oOOnee5eda9NIQGfaH7++ZnwFYNZ3JUzh7aP8PLUTmDuIUcEhtjMXZC7eyLGN1xrxC6Xm\nxxqU4iBoCLOpL/h28ZMnNPN3/L62xF/eXFI1K2c1NiFp1NcI/Uv0MP+uhyQsTsx2KA8WjYRHyqe9\n46ma8xWeqTc8FpQH+/SNsISHnF73a0dCecKtu6hKNrOLslP96Tl+o63d3HvD2JUGHkG4rEB8PzKN\nIG/N9pDhl2GaeIZVHaWgMC9dzD8ms0fWghnIhCfvYHErSkD8icLH7Q8OyhqS8ZUrhB+Ye6hnH20d\nGhvF09nRJI7YR/b2nPE25M33KKEY5ejkELQZCtvUhn1WEFtH5alKE7dXQG/jjYYTVK0+CbxVbBeZ\n7Ew0/6sJYi7p7QlWt/RihMVY46UHvglpKJfzlAmyPi3vdxpoEQypPvXCL7gOkR1cJKu5xhIzJ5t7\n0hT4uN7EMvLo6IfiRaKGNeCjrHmQ6nRlL76bp3vJs3/szupk1BRBTId+pKkQOlPZjq0CiyEfkOR6\n7xAEu8rgPdRSiY142Yr03ZfgL1tjSTWPwbqe6yXZJHECCaKhS8dOwv0iG1HG1xqfCpDb8bGNG5SD\ncJtGHW1H/y5DkRSh1qCMPyfyH4/v1T/E4/sXAUigrTVxwaz4x5qzq8sdSeVPJ6zEkLLm95p+QG/Z\nujUA1GC4Kp+JWSbCmGIGmH5hywCzcC5aZ7AmfTYTacxrOMh7eHq39R+INTMuzAjRsR7wgxvCfi9j\nVCrjcKH2e9tWJqYS06w9fHygPwsQBnxDua6ufBzh1vXJw9p+1YSqcdHr2J1GbaCDH9g/QIvGU/6O\ndbzF9qmG7acOplOV+UUN7bPImCfV4amD9Atdpn/yCqr17sbq/XnL8PbEfLFWwGtxeTDJNewdRG7I\nPuwOhE7/lAPAbTUjhdmGRU5jtZxwizcz0L2uya35thXsjXDoa6rM6KEoM8AGcBK1tb+yd7PGqnVV\ntl1tPRqgqsMj/Xfk6jwPKq3lc+rwQykIHRcKtuqFITMDLadL5ep6HMsOO/2PjRxrIT10V+AWqKcB\nWLdowlVBAqHvybs7xj18q7zmKGvn1/Z7s9JF9HeX+DM1keWzTV9lyDS8cfCEWKfxCCEMi8KH54Qj\nEzrbqFKm7Fwlg8Oz26tPJ6cJolCH45fSrmQ5PmfPIbAWYgadv4hxIy+8YqesRGAJS+JIa5SOSXAb\nATecjyYRjiHOI3AS8/HJUC3fqZ8N9qAX11K9lBiIjeAbccZK8eaJvQpoXGMA5/BH0vPycGo6k8hl\nTza8n1FJfrMyIORyUNwP5Peq3yZFkXNUcnMjt7tXqHfSWCwg3IFwfmOAgLs5w+K8IQjqtJZqxtv8\ndakxmjezVpTcmWXGsnw99P9JqDGt+BqYzoTXmJxw2iUPHthmNl6jiRoh49BtCqHRnQgIj5pNFX5r\n8t2qFy3ToUPQLoIhrYuIfhzw0AQLDFDScB/23Sk/8pxu19MVCgBmkfh/2xMMKtRbDkLQwTjdwpxQ\nrqEJ8nqvLO+tBbczQsREhamGHxOUpgAZam0D/KuSIlERbp1BpeZziflu3F3wDf2icJEXWOzomO0S\nnodxZZmHYclWxNI/ZytanByEfYfTNEbOvhpHGASwciuVfAXSoXNV7cVmuRG7sBuTSczVQJP0cjeD\nbfzIkwIhsW2Njg80CgQT6mdi4zfsAb0fr80e1VwVbWwtlX4ofhP1JmDrCrDU+AxxV1iJsCSzS7AN\n5aOdu3W16RzErzEE/1um+Ev7z174+8ddYoUfOtuFxVvAElaTxFOt9vUDJ3a5Z4WNvJgPe8cNt8R9\nYfuVdgr0BeqEC38Mm2VemwCGWJiilw8ZNufPdaDuT5CKev6WQzm2VpdCUPYYY3j7gTd23FeyHfZ+\nzX0yCzO3DJT4trtRE6sOb133kXpQkQyw6c32bsOGEHQ2MwtPveJMyiLcdphCUSbZygAY0Wm4OjtT\npq6LXISTFqDQGMYxqDI215O6O1e2d3yv6JmcN6E1AfLIkJScfFfda+qd4yuqjCTuj/65YSaMNf+z\n+SnvOvjH45e7Ad5YSVZ7pLWHQBLz+jaDxlZDwwhfnUCKmKLsz8mKHMw6AveW9NnUvh/sOtiLOd02\nWQJaSR/GcX6plGQLt87uWd/Se+wkzsTJ8uapmtIznpPZ0fg5NY7OuiIjmj3X/cxbsUcJsP4QK8Yo\nXMYEoSVaU6M7gc3m4CsLJESDVWv9usg/ACikf54onEvQw9jGFnP8AV7yhFIZLvfTg4xiFbNjRrcQ\n16mwcW0Fe6L1BAPAPhrb6wDKTI1hd39jJ52C1XA2BpBmZ5yGkT92S8cH0LOJf/v8yb7ymcF1OPYw\n5jYG7X5OUOCrQmmOlINIVsu8XHMlnRa9IDv4H+0ylUJnE2So7kW3rjDFNDyJpJ2yJi6NlHcxpHCW\nm65qtutuY+kbFMpIWHpxjs1cQfiQPCBISnJFVxNGTwgCqr6sHj/5ICiIsCkCO0QIy1jEVJDN2qVk\nl/ZVfIdNHng6I7vy5BzCCb63/mIDlBbCjFiafEPKSnzQwP/0N56D2ImUBCbYSdsjfLV9hiVIBYpj\nYQnNFNDu81Y6Ty/Od2AKyy6UjTdmLb1rdqkGnZ5qqAfhwM2AKZ/XoXwiurBa7+Xgwy+R2jBggubw\nbeRjsDJa7gU4M0gGheeRgNDnoizYw02Vzlg4k1VnPjAsxNr5XcW1BJ4Jm8vjEEXBBGGvVP0psXB+\nL4iy7FHUCgYPy8hYFqN5g7hLvb/wT6pkyNoUMoj6h+9GrrTy+rnjI6kGmNlIsSYu15F7oQbA+V9k\nkLTaiiD0deoYHRklY7pt3lUK7rZHQKf/n6Vx10/80i9aBofpZOIi3uyImyCN7hHcCCpYnvew8SZT\ncfFxgKGYa7V8OeAxk7jpLBvMxfr2ARp+Ep4D1sSRH2oSzKbtM/f9ncdKLxEMHr9wxupSW+XoOraE\n1yy49P59KV53Y3YnD4miFcBODs7CRM+6bqoK9hO1K2W5kvfodbOzIB1IARSmOhRwYdljB19jurPE\nYU3GUTC+u9Te1SflGvr4XsqCbbGMLETHb1HZmXendPnGcnneY+LtnYkbqK7SkCN7x9OkYrdD4Vsq\ntbk3FZFRMB6EZ5WZ214LiLTHzEmLckyG670YR7BNLjK1rQInQAgxS7Ri/B0TGCrTYRAynDMCPXB+\nEBZOhtu0kTKOAVnDj1uOhBFDA7cmnm7e9k9QBKhHkPOHHz6q/8B+iEM+hX+B4q9fpPM6oKw+Y+1s\n8b1LtwySajwDTHtloQWcxc1uR/UsnkCWBPuL9DMNYGr3ZmKTEnGhp70LePkIcfJYuwsfo/E7aCW1\naxn2sWtKwZrw0+CDk0QTotfQ6nG6Wr7hhUAnSqfG2O6kYjQyPSn4k6m+aEiUWQ48MMUvY9ABq87V\nofVf0Efv1OdyGUNFigWmZe8JDvXnZiWw1K9gwZqBldibpaASp9bfFJgdiPr2CAGTDl+r8eoMd1jn\nBbQ2igsBTuhTaV10ZWJFSAIdZ4+V3HYLkLU8oSRXqIzqcI/IiAg5SWLWSaeHmkCkSbn70TQGXGOF\npfjhv2J5yzmkmWDiwFq2qT5eWOMB38FWcEeOtiJ9xvBgjz0qOyAP17fXFxTm23JpVYazHXlTlnnH\nxJSftOg+EKpf3k7fWj4DxyytvhYqXy/Cw2R1dyUtnLFEbMzZd3Kd3ejeXjJdr8nuiqNi+s7uqd6f\nln+VwVZ9a3biIRoGDPRIqfXo5untTcj3xHOwq02XjoFfYNwh12xIfB5ZpUmpKZj34IsNZiFggBr6\n6jqqGibpp2bK8BYBtgi5WPUHkZJIuu/COkKemycnSDpeAv9Dc3KRz3nwhCU41HMq1xWMVrrY5W/B\n6Q1U+SBjTYpQ04mjzFOvYTtEim9f+nV2S1wghga3XTYpWdtpng6n/69RizgI6R1dyj9sZOcdhPFC\nLSFGTswmGoFRGvNeDd01cU3XMMT4u2Z5ZOJ0f9yEb2V0quk1hIqMxHLPaG78pHgJeAtI4ztI+h8x\nW6bMzRi+2SADpd92+2fWMSzXApfsMfb/CJmztrl81bZ/RiWoHQO7FahUXnuklE54bClGGhaEsp/H\nJDvuGKJi/CWrkZltXV3V+Y9rHOa2gxVtp1SNceOD7LJQtxy0tEh8+Mc9z+X68qvpUrp/u4tsNXDV\nXsi751iqAXXO0dnHOJ6OM0o4xjFty4aOINWoxA+xCmcx4EJTLLggpKAdzIwtad13EDly/znQSFLF\nbnp6kOJKqe0W85XvkYnXQff6cnhRSWsY8q2CG0w18siVnfa3E4xAO6o6vcJsbyH18/PAKl3e7Bh6\nNTN5XB88JkKGd58BVcAOZpxLiupbboAJCvsueNHTlyWyvvwbLqsDVuAJBSHpPs1cFjLtkeiTGT+a\nSrqsgMO+UHPBsrwvBGWtDxj3TIKE2Bnvjmq3fKgev8QgzmUU6ZF4/FNAnmzGpTTvADIiUY9lHdUv\nE12u4qX+I69/sHvIACAnIwYXNbd7R33aQ91VJeAcxifdcZA5v9C3ahUaFH3A1RK+enmmfq3TzpVu\noJN+l23KiY1hkUYhiR2aCWIXRySCyiY55+b1G2/fRN6+GV6tJ2/hDe+vqM3JlVPptTG3ZIX5Xn6w\nXYIcd4doI14tVLSyAXT+x6QXdffSrHe/NgPJaYs5pg3BnLI3GSDNxlUE/pU+OvTXDTutF6naLbGk\n3H2+OtT92hDETD3Fix908xWiPIyeY70Cbx6Buqa8znPrRqc4DyitrDyvoQlrTxSwsLstbSVHw7mV\nHsYKgDvPmw1+ZSb9KyxoMxkr19CiTRb3JOrETdiA/VQqnMkjJGK0IEojw02kx+ft8nWEvJkEjXTT\nvyjahSTIEhA1jVfUxN86LHEucrkqhb13um/j1XrS3GRfic1TgpHHW1S+0OcCHpiKzX11xznmgBbt\npi/8dC8uMXKveFYefwObSfPZ+WEbNUFC1u1Mtd1FGzNLljP9SEYPCSYTWYIzMmwRwWT6betJJ+MV\nq/08MKx6b4l9hUTYOylZcrfrrBLhb+qmqYl3C4dEybhehzgcKYDwq4KVDUSo7uPJKSObyezVPZGp\nYxK9gGsaTY2Y1vrww2p4LBm31MsezorYaIvvDZrRulc378EkVjjMFY74VdMTXqb+rpjLfZYvEheR\nltiLMDnzHFMTLx7MnxbGVbuTWXJtisMsbH5vXoXWGEWinvXUjir4yICOZiMgUdQNG9dJKF61yV5d\nD8vuzUbVZWMNKO50MKFFeQDEIi/QK3y9S7CoVspKGFiX9huOjtKEFypMTRvN25ZU6IsPSKFyBU3G\nsf2LC3U6O3+Aia+yJnOJ9j68fJ4j/y4h4EZddq3di2jiahqK6+92jBeqa2iljZiYWvUWjn1GLa6B\nmAddWZnuVAaG7sBULE1a2OvCuqt0/rpv4E2T0oCtg83dwV2wF1xwvR4TTP0k3VJkMDa+bRc6F1If\ng2DHdDMHOJ+zr50PcE8q3ATEQ3aRsHk3kiBDSNjCLxAu8Aloh4dvJok4QPOA82ahFUluEQOphCXJ\nnoGJVkBSWcXhXojWVO2iZmFMpOVj7j7CK7BqYLDRlfM7pQg0hLVUf+8hH8DhQSjK0e4V7/wJZLTP\npmLh/NhqxxhNtRDUhEa3xSQBmYRvWk0RbL7Z4jTo5yamAInndOM6Pz15AIijBTmggr42FdGAT7j3\nT+Hsa3nAUQEAshewF6KGwmCpKUL6hJwVxwujj3qdOYfcfVJVXWy+j2BjVZF3yRPrb6ZcsBK79nqA\n6znStSrjcPRpIMR0WyiPVw7kxu8u41VKTh7+x9iKHXw+V3xz8LDyVhCea+Lu421k0ftGM39elZzw\niICuqn848ke6Z7HBYQQcmBZLAnCjpKlEfKXiBiXC9/jrnytaxYWEwM1XfMDvfrkot4s/9EvpHeoK\nheSD1gXbrFhPXM2+kcS29UIcUeqaXVoFbCth3Q4gQ62DHteN0gw3hY0UNsY9Q05PN9qWfQoEZuBr\na2Bzj2u0Gt9YJuiH9AjxbWdYdJCoTVqSHPFsfTG+SS+TX8PcfGlHY1VZSdrScBIh1mWOl+bRxvvw\nt1Tr6dyDMLPJXu/CwyCj7teA4QrSMaPNh85K9Dylja1im0yXfAR+C7wRmRZ7Dd7QeOV5hvEC0YGR\n8TZxe1HAae7Zs+dfgdvBmR0esfWzNoda1mq2QiWH6R05QM/1sLqzdodSeB28NPx9WP2IqimxNBQh\niv35VU4A3epX/FjfVmMt40C8+kH2eC+fry5mYwvLXIAXZisbdynQAnoM+GQPONBsjaTyOZptbijq\nx6/Z8Ujz3G9XSvdiA2SVWuD410cnGgQrcWQ3tDBKfsz469bMz7VlELQn6SUzoUmTVeXqlunLMgAT\nZjAFpyhxsekFxEesgRUprfqnBWj8WZiwYk+++EaFrrl2LOVoKTGlASaf7i7PCgiMuDiow55MtAdH\nUQ2BBuXL5Hb7cpA7Qv5m/wgDTkM/0KJe9wVdZ1x+8bqBXTFyDz51576DrvtZtAD/XbJnA1kE5pDO\nTIqF52tj1j095Awo65eN1D9llYHxAe5KqySoIQ/mUCts9O55Ttef/xCU3rgLPln/8KfKrqhanX9f\nQytLhGJplYSQ+JeTpwLQ4AMsrKC5htbluB5tV8y6yp0i2ERPTDEqqtq/V7XMiqYbdH+04sQBR2nE\n4k8UUrISsEJt1r/1p4kKu08UaqcNRB+543qvLgCj6oYuFvcyZ26VMqgmFqYnLBBt6rxv0NbItcuv\njnXcTIV4DNLBpHsCGtPT6iKVmV+AarzOVNre2mZDZSjxENol85XuFWZKPGwuQHGf/13N0FwUZj33\nbcAaynRH5O1xKzw6B7o/6QOLte8t808bN8lTg4RtVzap6jb2nZQ79xfViEMvZj4TZ7mREpQb+UH5\n5w0c1wRH6IQcWeMYS4tEKNOFbj1fgfFa5WqDh5RkiRSuT07K4kqQ0IDvbuKVkJLaGtrQikvV568j\nJtt1GYLsDnJvj414UYYVlISVETETB+9wP5/n9mMPoKD1REvPhzX0F436v7GKY4JczyQWlQtdlIMy\nHSjPO318tn07kwO3cAJ5fsIffJCCNagrTfspZf9bzICnrQL6maPSuNgYQgqFwfDF2RM7YKFE+zpQ\n1JcpFaojBF1JuaWNYohO3O3iXCJB/AErTdLoDmZkRGr7+6yhSCU/MqKmeu1eMpbHzscQ1l6VgAoj\nh+JdxnWiH1hTvWfwHuxNuwiNd6hyvHjUyakzZlmJsCLhEWk28R7wCG+6TQMA1Qsc63dQtHvPUxkC\nn2VqxSKjMhSxtS2iXEtF2i4gqnU7RrlZPaNwq7N8FfBAIovNAkquXXYkv5QqOch1Inbmi4qUAA1k\nQPEde2r+zd3qjLYuEGGSjcTd4RTxuMzh80+//d8arJdfJKpgc51kD89xm2S2hti42Db5ewQ/NgEx\nD5Oc6V+9Fp6zaOdR68MZ1vqFLmPmxrnOc77er0e4ciLRpueVvrks4AXCvLpDexU+qwqJpHcO4Nsq\nePNG3yBCFBf+OkklK9K2i96oQfq61gTjMYDrqdASmgo46lvYVsliKZxiATnOtrw40xLe/I4HyUek\nUzpOa7lwnkXdKgZe+gx5Q0jxiJiTE/F3r+2UpJTaO7MRcwplFvXFPSSbDHfKwF/BQjoMq8/pnM5R\nqZYfGin5xwtXkin877nraCfD6s189FrFvYKq96F5I+uEq7n74mQyY274WQJw9Pq12zUEbQsDg0DR\ndgsWPYQEt21HWe5pj1YjzKc3k9dC903kOq1+KD26+8pdMcpvICRq+WJddxHfZxl6ec1XAt2QKB/w\npyPg4yDmh/5/aEOuP45dLO4gUbGL3EinXZWQ+E1jIJoSnHh6vilbDhtX4e7DJ46+QIqny0h7R5eW\nsfDz0mHmHpRxuhReQWkB2yJeHEe5qYDVKFzzV+a/yM9kAxoFkRxFTn9o6n0mtJORZm4wxoGeQlwA\nIXr9swVxSPgM0S8/RwgkdEGMDAz+BfFrjvRRbbXsrQK3aPWDSTFswnscfXV7EW6+nDVhMJMbes+D\nf4yXRYnRL45CqKVRwr8am3VA8FgN+DQrwIvAbrZaiZMzBU3TBLFQnt3zNny734g6Ufl5gloVBA0q\nt29E/m/RIobK12HWVG/5m/8MNwNY070i2VYegXW8o9i74wAONxZgngxdmnerN+0Bmu5ugMhe0V92\nT/X9Yt9A99AjMEGdljk06tBlYIWLBBv7JdeUmUItCy/FWuPaUZzUGLKbzoBfwXuQG458SVeCmYqq\nKCBgyFSQONeMJe7dhcaNg88JTodC+KDndvWzuL/Gu3YGc0LuoOFqIE6SumcamDQzxQSTHzxsJW5D\n9+WgLz7d9U1V9dZkBWq8WC7scYXmYEJY2TVNJjHVgu/DaW5+XOEKNkvtj6pDnGIwi1nRHt/ywZEv\nMkcqF+WVwZAEUXVXzMuF3xvk/ytRRhgorncR5sS3ArptApRy/neZT/RDVsyV4JDMGSdzgvweGLjn\nD2KQlEpHOu1r0lCWsdTnBML5Ya5tXGQcD0s0DXsJWiJqHyeWFXE8YmOpRBKrnBiGLJaz3D7xF+dm\nYF950bejYl9BrCezc8s2dFTTXOiPC2aLtsqtvhGaPGRNomr9s6FF5YDKECFX9Gtzy65jD2Uxi/tQ\n528R4MC/Kh3P/bo6d+mGGThuyYu/w08SZJKPSMmO2HDiE+mtRVzR9pP+WZ/MpeKRWYf8JZZ1cvz+\nQ9r0fJKYmsiQgj9LJWZYCdjz3tupcrvAXARjilyqBOxVIq2OQzjnIINDF7IvpWnGaenn/Ml+wiLF\nuK+niFvzqRl0ZzeOc9MHYQii1+56TeTxWGY+DM1kHBxBOGVqJVkIwtxkFtjDVk+Zk6HyIPDCN2AR\nms7Ojlj8L9WJyotBzxLNdmBQ0dGc1tpCwdthepMi86OcbLBDaImZ6elWWAFQx/1seibqgSYGXwAM\nllhCxzv1smGoW5ScDPlgpzxfrIsVNvlBXRBMTkmJ+qOQ1/ZonCBNBvc6wysO2/bRH2q22N1pvx8Y\nMeL3M30cfu2qmswOY8Q7zJl7tBMfeaj22LgZsejWPOlhwAzfQWVy5IwBujhIplfaAel33LBOiS/p\nAkS5XH8sMf7x24AVDupRC/hXOAy/awmE5KNbsFq/OL14Ptlmnjpyf9NEh5ea/cw7fNWpTaK1Ozo7\nBa1/0RAk203DiiRfXWBNTVH2047nL0PGx5U0jzNtxRJtrx7qOVd0bnP8bRRX0fgGJvrI+whKaSa2\ndI9EJ2rAnBxkJrexb7OzccL5GW9f8fOd6HUYa0KUq7s9PTeV/hqqXND6gZlfbVp+6LRn9XX232ig\n3TigRnOeqs5gBWxf+yNhnbttVTrVkhyHkg/4XF/hGzljDgM3xhGsLlAQYBlu1IFgDQKB0QCcqLB8\nuT+ItAHiLDsKp22zq7XP3hZuPvXsiMVXhk3gzW80XBjO9YdryFgZKvJOslBV9LRpqDLqwVjbwVvJ\nFJvKaKH95Kobys5cQLXhCVkROVJNghm2IzD+gAvjjNNN4v1g7o0HPABDSfWhWSxdr3Q+M7NvmgKg\nmX4lG5pYL9gwmWn43rwtbxilOwvejyvzUpDsfT7sN6rywK4FiicOwdZu1znqp9rTkkleBJU8oWzw\npMUGzh3EvA3wmUx+yi2nJAivFxWtCIBBLF093Qk5TZ9JF5SsZMriphe019NHeJPN7VM0igq8m1nB\nMNsGXrJNqPg3d5+VMFqxPsN1xlVssCxiDRU7hLUnSCPJwOsPbrJ4jJ+iI5Eu3MZqffJdPCUKVxX+\ne8VIBYaCIU1n88ZRBy0/fvnfyBlP3rJegasVh+Gw19ccUnEcs9NjM/kJdHh6qCi41KIxuTjFD9IL\nuJakkfHei206Hx86Hfs68M1idoaz1YXPzE6MLxYEHPJL/jC8wgpUZbfDQMUY2fq151hTgA5UrVXn\nzNvQRvIwp+ejQ2rq7HsJh4xpyAWWp+UNkpIIGfCUtHjAZl5HT30QkWkdsNytGN0EparGxYu8oIDB\ng5rze1cL7TqjaaZth3GqMe8oc6Ee0mdxzqr6WT0jcmT9C0+Id2YSDXTVsKA4MPNekS8nIvoD+FzK\n3wunleyNqhPmHrATn4TtGMsq7mlqvPpyOvoW5T95hr0vyPIYpnDBvJ2EE3A+GoWaeAMfVInayQk6\nXNjWGST0FMagFBvciuZTo/A2VTJLDygqcDZPqqZ+0NfBGuJwo+CRzq5ICxtDwv0oLe5kj3d5G1qy\n2vqHd5m0/71p3ZseGeQM8DgW7Hqv36f7iGKfaXQmvwwIkOY8H2KYBOpRuwOPMwj1Ez+LZipYbyI9\nmKj9lNhNz3+5fIKZFgF29TCo6d6au9imnNXR2ZW7fZGiGKIOKv265X3hNpcDmYeyEeetT7nHsAlV\nElEAcD62bZJAp0i5Riea1lpN9hD7nin+GHCGsCd8W9cYSE22IJKvejLcO5WgiW5lvqCCDCvfwO9I\nasCxXebGi4uqUSQJBxRfSbhVSG8FeKR4XldRaugEqxc5/843LFRdlm1V832Igc+G8q/M9pmobo56\nB5/SwdIjFyaaBofHMML2Dlv/P5YHqmWOMGyNfBRWRtS9gcE2rNA5FtcXXli9iKiF1v6ngG3GKJVS\n1zkwJNaHKKV8OMARo/c3JSYi/l7iC8eWvXxNDMKc/3fjIVgTCeY7RM6H6cWYQQdJoPqR7EG4bDYR\nosVI79WGWVefVhS3TxGX8UYWAxQLbwhbOuie2aLQBy7YXgMNPgV8PIPPHFmVIzHhEZA1OuVkbi7G\nGFhRIUifmPq5g6EVr+xX9TuJHZWSJJUT1/JUWNRNVOu6XNpNEeP1S2ghf6oMAIr+ISdEeDNZOJO9\nwXy8Rcklo4dPaT+lHianOxRpRHEX5YMO55V6aeibuQKXJRwjgfWnbc0EKoPuor8XUbqug/6ZE7j1\nE7yXZYS7KtOsUnB17h6KzjGFznBVRt1q+84oVWJKQIROClMVT9XTjGP9kFT70snh1O9nsL/grGB0\nfUzU/WoBVRdp0oFtZ26Hk82ha/hl++Uivq8UDIol/hzYkA4wQBuvgSSCvkmMbHWQLfMHy9PjciE9\n/e9Vjgvc9KbFGHTb31tbg4MoGmcc0HGO3raQPrLTnXfdGV3VWfGKMfy/RGdSD57qi9E3wNrgGMSP\nBKiCjKLPLI3xHu2qsaJJ2F8uno+WVTOfp2lZxEBWxLGsES+FmU65TrT1fy5ZCeIeaHQabk/HcBXt\nF1uSFz42aPdTZA0SqK5+4faKUTata+cQjVPjsAADtfrToRZy2d+6EHlvXC9ksn4GH17OlPSdv8pP\nnpKDZ1eaJxzV6D8qqVXPOFttt360qx7cWRYCcFenhFVUpxBKZfuQEW7mYS9lVhghyDTWX5chKYKm\neC/efWFFT30OfTwIwInLus4LYOnj8WdaxW9uNOTfZoric7rUiAhwkJb3wNBW65F4QwRZdlyJ1Feq\nkEi+rEKgRdqli6dElxf6CVDapNmiUshH5HOp/PN/FbkZZxw1EZBecJ5TzDfX5rhFCPZqvWb3T7je\nx4Rg0yb8S4ora4wundEjGAzJvfgGZlpLsiHC/UJe+I4zbZAucVG46ZmOgKdt+Z0m3YhyMH1RA5tp\ngR3G4qTnB9TvDF28GTvh5m+KaTNQxve9wPIRpTpVveO39FeFWdrs/8z/yfDbqaBSyFBkaPFFKU0E\nnjRhobVb+g1SYKEkDZYWqeJ6jOLhSqsmpktl86KRKj5T+ZHI0KDotADU2BybQyijJDyR5TvNLU2z\noLnSh+nuPPP/uQ99UDd/ES+CYINuFbbN5iv3ootOk752D8/+eMepxL4TbjcVeiMJsglorDY26rQb\ntHspGg9kI+tmPLftbvJLY1Ah/jkqc9e9dJrx0Gd2X+zVGNFXtgRQEDiG0HBcACcNuC0sNo8ufju+\nDLi3gbESCBkLR5/Ku6ErOVAIaS5saiy4aDoQnu2wbBZfRvVdFLCJxpISgQCcyzt9/4Ni3fLtQqiT\ntG/HKy5+RvsyDoImtnejDJx1REIWGfd9yxIoLnsb7gSJxk3qqKd1HZJRBpcVjUQ/g9EWWECeSSl6\n4BN3NqO9qO2cEU8Gy59FzzD6Nqet0wfwTgbLbeI1ULxDlaghm2HBKvemR//cQPfelFaw8oT0H2pn\nE5IBJs/LYwG8S5XcAN/bT1DfjGTTPIqkcnCuKTJJPisEplPXbcpn9c5KWjApA4dBZiDuABxt4LRh\n9k0hb3AeHhWXvrYWj57EiwiOlS3XOg6iJv7BKgiZC/UJz4yuH/J+IERjAKj6dQ0pqveXN5Ghp5l1\n1hUwA/eKbHE1h9S+2oItwWl1gxNcmjYk3i3ogZVpSmkUoxeyVDyNTrZviXD9FcFBgUtAGOaEetbq\nZFyHbI1B/VBG33BnvSJ2WgGyypH5ggV7azeAYZ7djam33U8yU0wMIMtj7bTxQWnhhEITSH3TTa9E\nndkI06pkCNH0SA7tahb3c6IUOkrLqxZ+1oR8htcEE1AIEpHTBX4kNQHWjAJIxLC6KI//lbj4hk6n\nXCIYAKrm/P7sFmWEwDD8AQYqpChgDejn9MV+4YQYreP5x71z0l5s+//OS6fNIY1YQqlKAnJFgSiS\nkL8Mop5IvPv1Lca7HioxXCMT+QXJ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protect end_protected\n", "num_lines": 510}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_sde_wb (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26,\nprobe27,\nprobe28,\nprobe29,\nprobe30,\nprobe31,\nprobe32,\nprobe33,\nprobe34,\nprobe35,\nprobe36,\nprobe37,\nprobe38,\nprobe39,\nprobe40,\nprobe41,\nprobe42,\nprobe43,\nprobe44,\nprobe45,\nprobe46,\nprobe47,\nprobe48\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [31 : 0] probe1;\ninput [0 : 0] probe2;\ninput [31 : 0] probe3;\ninput [0 : 0] probe4;\ninput [31 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [0 : 0] probe8;\ninput [63 : 0] probe9;\ninput [0 : 0] probe10;\ninput [0 : 0] probe11;\ninput [31 : 0] probe12;\ninput [0 : 0] probe13;\ninput [0 : 0] probe14;\ninput [0 : 0] probe15;\ninput [0 : 0] probe16;\ninput [0 : 0] probe17;\ninput [0 : 0] probe18;\ninput [0 : 0] probe19;\ninput [0 : 0] probe20;\ninput [0 : 0] probe21;\ninput [0 : 0] probe22;\ninput [0 : 0] probe23;\ninput [0 : 0] probe24;\ninput [0 : 0] probe25;\ninput [0 : 0] probe26;\ninput [31 : 0] probe27;\ninput [31 : 0] probe28;\ninput [31 : 0] probe29;\ninput [15 : 0] probe30;\ninput [0 : 0] probe31;\ninput [15 : 0] probe32;\ninput [0 : 0] probe33;\ninput [63 : 0] probe34;\ninput [3 : 0] probe35;\ninput [6 : 0] probe36;\ninput [6 : 0] probe37;\ninput [6 : 0] probe38;\ninput [6 : 0] probe39;\ninput [6 : 0] probe40;\ninput [3 : 0] probe41;\ninput [3 : 0] probe42;\ninput [3 : 0] probe43;\ninput [3 : 0] probe44;\ninput [0 : 0] probe45;\ninput [0 : 0] probe46;\ninput [0 : 0] probe47;\ninput [0 : 0] probe48;\n\n\nendmodule\n", "num_lines": 159}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"ila_sde_wb,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_sde_wb,ila,{x_ipProduct=Vivado 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IDTH=1,C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1,C_PROBE0_TYPE=0,C_PROBE1_TYPE=0,C_PROBE2_TYPE=0,C_PROBE3_TYPE=0,C_PROBE4_TYPE=0,C_PROBE5_TYPE=0,\\\nC_PROBE6_TYPE=0,C_PROBE7_TYPE=0,C_PROBE8_TYPE=0,C_PROBE9_TYPE=0,C_PROBE10_TYPE=0,C_PROBE11_TYPE=0,C_PROBE12_TYPE=0,C_PROBE13_TYPE=0,C_PROBE14_TYPE=0,C_PROBE15_TYPE=0,C_PROBE16_TYPE=0,C_PROBE17_TYPE=0,C_PROBE18_TYPE=0,C_PROBE19_TYPE=0,C_PROBE20_TYPE=0,C_PROBE21_TYPE=0,C_PROBE22_TYPE=0,C_PROBE23_TYPE=0,C_PROBE24_TYPE=0,C_PROBE25_TYPE=0,C_PROBE26_TYPE=0,C_PROBE27_TYPE=0,C_PROBE28_TYPE=0,C_PROBE29_TYPE=0,C_PROBE30_TYPE=0,C_PROBE31_TYPE=0,C_PROBE32_TYPE=0,C_PROBE33_TYPE=0,C_PROBE34_TYPE=0,C_PROBE35_TYPE=0,C_PROBE36_TYPE=0,C_PROBE37_TYPE=0,C_PROBE38_TYPE=0,C_PROBE39_TYPE=0,C_PROBE40_TYPE=0,C_PROBE41_TYPE=0,C_PROBE42_TYPE=0,C_PROBE43_TYPE=0,C_PROBE44_TYPE=0,C_PROBE45_TYPE=0,C_PROBE46_TYPE=0,C_PROBE47_TYPE=0,C_PROBE48_TYPE=0,C_PROBE49_TYPE=1,C_PROBE50_TYPE=1,C_PROBE51_TYPE=1,C_PROBE52_TYPE=1,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,\\\nC_PROBE106_TYPE=1,C_PROBE107_TYPE=1,C_PROBE108_TYPE=1,C_PROBE109_TYPE=1,C_PROBE110_TYPE=1,C_PROBE111_TYPE=1,C_PROBE112_TYPE=1,C_PROBE113_TYPE=1,C_PROBE114_TYPE=1,C_PROBE115_TYPE=1,C_PROBE116_TYPE=1,C_PROBE117_TYPE=1,C_PROBE118_TYPE=1,C_PROBE119_TYPE=1,C_PROBE120_TYPE=1,C_PROBE121_TYPE=1,C_PROBE122_TYPE=1,C_PROBE123_TYPE=1,C_PROBE124_TYPE=1,C_PROBE125_TYPE=1,C_PROBE126_TYPE=1,C_PROBE127_TYPE=1,C_PROBE128_TYPE=1,C_PROBE129_TYPE=1,C_PROBE130_TYPE=1,C_PROBE131_TYPE=1,C_PROBE132_TYPE=1,C_PROBE133_TYPE=1,C_PROBE134_TYPE=1,C_PROBE135_TYPE=1,C_PROBE136_TYPE=1,C_PROBE137_TYPE=1,C_PROBE138_TYPE=1,C_PROBE139_TYPE=1,C_PROBE140_TYPE=1,C_PROBE141_TYPE=1,C_PROBE142_TYPE=1,C_PROBE143_TYPE=1,C_PROBE144_TYPE=1,C_PROBE145_TYPE=1,C_PROBE146_TYPE=1,C_PROBE147_TYPE=1,C_PROBE148_TYPE=1,C_PROBE149_TYPE=1,C_PROBE150_TYPE=1,C_PROBE151_TYPE=1,C_PROBE152_TYPE=1,C_PROBE153_TYPE=1,C_PROBE154_TYPE=1,C_PROBE155_TYPE=1,C_PROBE156_TYPE=1,C_PROBE157_TYPE=1,C_PROBE158_TYPE=1,C_PROBE159_TYPE=1,C_PROBE160_TYPE=1,C_PROBE161_TYPE=1,C_PROBE162_TYPE=1,C_PROBE163_TYPE=1,C_PROBE164_TYPE=1,C_PROBE165_TYPE=1,C_PROBE166_TYPE=1,C_PROBE167_TYPE=1,C_PROBE168_TYPE=1,C_PROBE169_TYPE=1,C_PROBE170_TYPE=1,C_PROBE171_TYPE=1,C_PROBE172_TYPE=1,C_PROBE173_TYPE=1,C_PROBE174_TYPE=1,C_PROBE175_TYPE=1,C_PROBE176_TYPE=1,C_PROBE177_TYPE=1,C_PROBE178_TYPE=1,C_PROBE179_TYPE=1,C_PROBE180_TYPE=1,C_PROBE181_TYPE=1,C_PROBE182_TYPE=1,C_PROBE183_TYPE=1,C_PROBE184_TYPE=1,C_PROBE185_TYPE=1,C_PROBE186_TYPE=1,C_PROBE187_TYPE=1,C_PROBE188_TYPE=1,C_PROBE189_TYPE=1,C_PROBE190_TYPE=1,C_PROBE191_TYPE=1,C_PROBE192_TYPE=1,C_PROBE193_TYPE=1,C_PROBE194_TYPE=1,C_PROBE195_TYPE=1,C_PROBE196_TYPE=1,C_PROBE197_TYPE=1,C_PROBE198_TYPE=1,C_PROBE199_TYPE=1,C_PROBE200_TYPE=1,C_PROBE201_TYPE=1,C_PROBE202_TYPE=1,C_PROBE203_TYPE=1,C_PROBE204_TYPE=1,C_PROBE205_TYPE=1,\\\nC_PROBE206_TYPE=1,C_PROBE207_TYPE=1,C_PROBE208_TYPE=1,C_PROBE209_TYPE=1,C_PROBE210_TYPE=1,C_PROBE211_TYPE=1,C_PROBE212_TYPE=1,C_PROBE213_TYPE=1,C_PROBE214_TYPE=1,C_PROBE215_TYPE=1,C_PROBE216_TYPE=1,C_PROBE217_TYPE=1,C_PROBE218_TYPE=1,C_PROBE219_TYPE=1,C_PROBE220_TYPE=1,C_PROBE221_TYPE=1,C_PROBE222_TYPE=1,C_PROBE223_TYPE=1,C_PROBE224_TYPE=1,C_PROBE225_TYPE=1,C_PROBE226_TYPE=1,C_PROBE227_TYPE=1,C_PROBE228_TYPE=1,C_PROBE229_TYPE=1,C_PROBE230_TYPE=1,C_PROBE231_TYPE=1,C_PROBE232_TYPE=1,C_PROBE233_TYPE=1,C_PROBE234_TYPE=1,C_PROBE235_TYPE=1,C_PROBE236_TYPE=1,C_PROBE237_TYPE=1,C_PROBE238_TYPE=1,C_PROBE239_TYPE=1,C_PROBE240_TYPE=1,C_PROBE241_TYPE=1,C_PROBE242_TYPE=1,C_PROBE243_TYPE=1,C_PROBE244_TYPE=1,C_PROBE245_TYPE=1,C_PROBE246_TYPE=1,C_PROBE247_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*)\n\nmodule ila_sde_wb (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26,\nprobe27,\nprobe28,\nprobe29,\nprobe30,\nprobe31,\nprobe32,\nprobe33,\nprobe34,\nprobe35,\nprobe36,\nprobe37,\nprobe38,\nprobe39,\nprobe40,\nprobe41,\nprobe42,\nprobe43,\nprobe44,\nprobe45,\nprobe46,\nprobe47,\nprobe48\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [31 : 0] probe1;\ninput [0 : 0] probe2;\ninput [31 : 0] probe3;\ninput [0 : 0] probe4;\ninput [31 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [0 : 0] probe8;\ninput [63 : 0] probe9;\ninput [0 : 0] probe10;\ninput [0 : 0] probe11;\ninput [31 : 0] probe12;\ninput [0 : 0] probe13;\ninput [0 : 0] probe14;\ninput [0 : 0] probe15;\ninput [0 : 0] probe16;\ninput [0 : 0] probe17;\ninput [0 : 0] probe18;\ninput [0 : 0] probe19;\ninput [0 : 0] probe20;\ninput [0 : 0] probe21;\ninput [0 : 0] probe22;\ninput [0 : 0] probe23;\ninput [0 : 0] probe24;\ninput [0 : 0] probe25;\ninput [0 : 0] probe26;\ninput [31 : 0] probe27;\ninput [31 : 0] probe28;\ninput [31 : 0] probe29;\ninput [15 : 0] probe30;\ninput [0 : 0] probe31;\ninput [15 : 0] probe32;\ninput [0 : 0] probe33;\ninput [63 : 0] probe34;\ninput [3 : 0] probe35;\ninput [6 : 0] probe36;\ninput [6 : 0] probe37;\ninput [6 : 0] probe38;\ninput [6 : 0] probe39;\ninput [6 : 0] probe40;\ninput [3 : 0] probe41;\ninput [3 : 0] probe42;\ninput [3 : 0] probe43;\ninput [3 : 0] probe44;\ninput [0 : 0] probe45;\ninput [0 : 0] probe46;\ninput [0 : 0] probe47;\ninput [0 : 0] probe48;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_5_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(49),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2017),\n.C_MINOR_VERSION(4),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(0),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(2),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH 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ROBE65_MU_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT(1),\n.C_PROBE275_MU_CNT(1),\n.C_PROBE276_MU_CNT(1),\n.C_PROBE277_MU_CNT(1),\n.C_PROBE278_MU_CNT(1),\n.C_PROBE279_MU_CNT(1),\n.C_PROBE280_MU_CNT(1),\n.C_PROBE281_MU_CNT(1),\n.C_PROBE282_MU_CNT(1),\n.C_PROBE283_MU_CNT(1),\n.C_PROBE284_MU_CNT(1),\n.C_PROBE285_MU_CNT(1),\n.C_PROBE286_MU_CNT(1),\n.C_PROBE287_MU_CNT(1),\n.C_PROBE288_MU_CNT(1),\n.C_PROBE289_MU_CNT(1),\n.C_PROBE290_MU_CNT(1),\n.C_PROBE291_MU_CNT(1),\n.C_PROBE292_MU_CNT(1),\n.C_PROBE293_MU_CNT(1),\n.C_PROBE294_MU_CNT(1),\n.C_PROBE295_MU_CNT(1),\n.C_PROBE296_MU_CNT(1),\n.C_PROBE297_MU_CNT(1),\n.C_PROBE298_MU_CNT(1),\n.C_PROBE299_MU_CNT(1),\n.C_PROBE300_MU_CNT(1),\n.C_PROBE301_MU_CNT(1),\n.C_PROBE302_MU_CNT(1),\n.C_PROBE303_MU_CNT(1),\n.C_PROBE304_MU_CNT(1),\n.C_PROBE305_MU_CNT(1),\n.C_PROBE306_MU_CNT(1),\n.C_PROBE307_MU_CNT(1),\n.C_PROBE308_MU_CNT(1),\n.C_PROBE309_MU_CNT(1),\n.C_PROBE310_MU_CNT(1),\n.C_PROBE311_MU_CNT(1),\n.C_PROBE312_MU_CNT(1),\n.C_PROBE313_MU_CNT(1),\n.C_PROBE314_MU_CNT(1),\n.C_PROBE315_MU_CNT(1),\n.C_PROBE316_MU_CNT(1),\n.C_PROBE317_MU_CNT(1),\n.C_PROBE318_MU_CNT(1),\n.C_PROBE319_MU_CNT(1),\n.C_PROBE320_MU_CNT(1),\n.C_PROBE321_MU_CNT(1),\n.C_PROBE322_MU_CNT(1),\n.C_PROBE323_MU_CNT(1),\n.C_PROBE324_MU_CNT(1),\n.C_PROBE325_MU_CNT(1),\n.C_PROBE326_MU_CNT(1),\n.C_PROBE327_MU_CNT(1),\n.C_PROBE328_MU_CNT(1),\n.C_PROBE329_MU_CNT(1),\n.C_PROBE330_MU_CNT(1),\n.C_PROBE331_MU_CNT(1),\n.C_PROBE332_MU_CNT(1),\n.C_PROBE333_MU_CNT(1),\n.C_PROBE334_MU_CNT(1),\n.C_PROBE335_MU_CNT(1),\n.C_PROBE336_MU_CNT(1),\n.C_PROBE337_MU_CNT(1),\n.C_PROBE338_MU_CNT(1),\n.C_PROBE339_MU_CNT(1),\n.C_PROBE340_MU_CNT(1),\n.C_PROBE341_MU_CNT(1),\n.C_PROBE342_MU_CNT(1),\n.C_PROBE343_MU_CNT(1),\n.C_PROBE344_MU_CNT(1),\n.C_PROBE345_MU_CNT(1),\n.C_PROBE346_MU_CNT(1),\n.C_PROBE347_MU_CNT(1),\n.C_PROBE348_MU_CNT(1),\n.C_PROBE349_MU_CNT(1),\n.C_PROBE350_MU_CNT(1),\n.C_PROBE351_MU_CNT(1),\n.C_PROBE352_MU_CNT(1),\n.C_PROBE353_MU_CNT(1),\n.C_PROBE354_MU_CNT(1),\n.C_PROBE355_MU_CNT(1),\n.C_PROBE356_MU_CNT(1),\n.C_PROBE357_MU_CNT(1),\n.C_PROBE358_MU_CNT(1),\n.C_PROBE359_MU_CNT(1),\n.C_PROBE360_MU_CNT(1),\n.C_PROBE361_MU_CNT(1),\n.C_PROBE362_MU_CNT(1),\n.C_PROBE363_MU_CNT(1),\n.C_PROBE364_MU_CNT(1),\n.C_PROBE365_MU_CNT(1),\n.C_PROBE366_MU_CNT(1),\n.C_PROBE367_MU_CNT(1),\n.C_PROBE368_MU_CNT(1),\n.C_PROBE369_MU_CNT(1),\n.C_PROBE370_MU_CNT(1),\n.C_PROBE371_MU_CNT(1),\n.C_PROBE372_MU_CNT(1),\n.C_PROBE373_MU_CNT(1),\n.C_PROBE374_MU_CNT(1),\n.C_PROBE375_MU_CNT(1),\n.C_PROBE376_MU_CNT(1),\n.C_PROBE377_MU_CNT(1),\n.C_PROBE378_MU_CNT(1),\n.C_PROBE379_MU_CNT(1),\n.C_PROBE380_MU_CNT(1),\n.C_PROBE381_MU_CNT(1),\n.C_PROBE382_MU_CNT(1),\n.C_PROBE383_MU_CNT(1),\n.C_PROBE384_MU_CNT(1),\n.C_PROBE385_MU_CNT(1),\n.C_PROBE386_MU_CNT(1),\n.C_PROBE387_MU_CNT(1),\n.C_PROBE388_MU_CNT(1),\n.C_PROBE389_MU_CNT(1),\n.C_PROBE390_MU_CNT(1),\n.C_PROBE391_MU_CNT(1),\n.C_PROBE392_MU_CNT(1),\n.C_PROBE393_MU_CNT(1),\n.C_PROBE394_MU_CNT(1),\n.C_PROBE395_MU_CNT(1),\n.C_PROBE396_MU_CNT(1),\n.C_PROBE397_MU_CNT(1),\n.C_PROBE398_MU_CNT(1),\n.C_PROBE399_MU_CNT(1),\n.C_PROBE400_MU_CNT(1),\n.C_PROBE401_MU_CNT(1),\n.C_PROBE402_MU_CNT(1),\n.C_PROBE403_MU_CNT(1),\n.C_PROBE404_MU_CNT(1),\n.C_PROBE405_MU_CNT(1),\n.C_PROBE406_MU_CNT(1),\n.C_PROBE407_MU_CNT(1),\n.C_PROBE408_MU_CNT(1),\n.C_PROBE409_MU_CNT(1),\n.C_PROBE410_MU_CNT(1),\n.C_PROBE411_MU_CNT(1),\n.C_PROBE412_MU_CNT(1),\n.C_PROBE413_MU_CNT(1),\n.C_PROBE414_MU_CNT(1),\n.C_PROBE415_MU_CNT(1),\n.C_PROBE416_MU_CNT(1),\n.C_PROBE417_MU_CNT(1),\n.C_PROBE418_MU_CNT(1),\n.C_PROBE419_MU_CNT(1),\n.C_PROBE420_MU_CNT(1),\n.C_PROBE421_MU_CNT(1),\n.C_PROBE422_MU_CNT(1),\n.C_PROBE423_MU_CNT(1),\n.C_PROBE424_MU_CNT(1),\n.C_PROBE425_MU_CNT(1),\n.C_PROBE426_MU_CNT(1),\n.C_PROBE427_MU_CNT(1),\n.C_PROBE428_MU_CNT(1),\n.C_PROBE429_MU_CNT(1),\n.C_PROBE430_MU_CNT(1),\n.C_PROBE431_MU_CNT(1),\n.C_PROBE432_MU_CNT(1),\n.C_PROBE433_MU_CNT(1),\n.C_PROBE434_MU_CNT(1),\n.C_PROBE435_MU_CNT(1),\n.C_PROBE436_MU_CNT(1),\n.C_PROBE437_MU_CNT(1),\n.C_PROBE438_MU_CNT(1),\n.C_PROBE439_MU_CNT(1),\n.C_PROBE440_MU_CNT(1),\n.C_PROBE441_MU_CNT(1),\n.C_PROBE442_MU_CNT(1),\n.C_PROBE443_MU_CNT(1),\n.C_PROBE444_MU_CNT(1),\n.C_PROBE445_MU_CNT(1),\n.C_PROBE446_MU_CNT(1),\n.C_PROBE447_MU_CNT(1),\n.C_PROBE448_MU_CNT(1),\n.C_PROBE449_MU_CNT(1),\n.C_PROBE450_MU_CNT(1),\n.C_PROBE451_MU_CNT(1),\n.C_PROBE452_MU_CNT(1),\n.C_PROBE453_MU_CNT(1),\n.C_PROBE454_MU_CNT(1),\n.C_PROBE455_MU_CNT(1),\n.C_PROBE456_MU_CNT(1),\n.C_PROBE457_MU_CNT(1),\n.C_PROBE458_MU_CNT(1),\n.C_PROBE459_MU_CNT(1),\n.C_PROBE460_MU_CNT(1),\n.C_PROBE461_MU_CNT(1),\n.C_PROBE462_MU_CNT(1),\n.C_PROBE463_MU_CNT(1),\n.C_PROBE464_MU_CNT(1),\n.C_PROBE465_MU_CNT(1),\n.C_PROBE466_MU_CNT(1),\n.C_PROBE467_MU_CNT(1),\n.C_PROBE468_MU_CNT(1),\n.C_PROBE469_MU_CNT(1),\n.C_PROBE470_MU_CNT(1),\n.C_PROBE471_MU_CNT(1),\n.C_PROBE472_MU_CNT(1),\n.C_PROBE473_MU_CNT(1),\n.C_PROBE474_MU_CNT(1),\n.C_PROBE475_MU_CNT(1),\n.C_PROBE476_MU_CNT(1),\n.C_PROBE477_MU_CNT(1),\n.C_PROBE478_MU_CNT(1),\n.C_PROBE479_MU_CNT(1),\n.C_PROBE480_MU_CNT(1),\n.C_PROBE481_MU_CNT(1),\n.C_PROBE482_MU_CNT(1),\n.C_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1),\n.C_PROBE691_MU_CNT(1),\n.C_PROBE692_MU_CNT(1),\n.C_PROBE693_MU_CNT(1),\n.C_PROBE694_MU_CNT(1),\n.C_PROBE695_MU_CNT(1),\n.C_PROBE696_MU_CNT(1),\n.C_PROBE697_MU_CNT(1),\n.C_PROBE698_MU_CNT(1),\n.C_PROBE699_MU_CNT(1),\n.C_PROBE700_MU_CNT(1),\n.C_PROBE701_MU_CNT(1),\n.C_PROBE702_MU_CNT(1),\n.C_PROBE703_MU_CNT(1),\n.C_PROBE704_MU_CNT(1),\n.C_PROBE705_MU_CNT(1),\n.C_PROBE706_MU_CNT(1),\n.C_PROBE707_MU_CNT(1),\n.C_PROBE708_MU_CNT(1),\n.C_PROBE709_MU_CNT(1),\n.C_PROBE710_MU_CNT(1),\n.C_PROBE711_MU_CNT(1),\n.C_PROBE712_MU_CNT(1),\n.C_PROBE713_MU_CNT(1),\n.C_PROBE714_MU_CNT(1),\n.C_PROBE715_MU_CNT(1),\n.C_PROBE716_MU_CNT(1),\n.C_PROBE717_MU_CNT(1),\n.C_PROBE718_MU_CNT(1),\n.C_PROBE719_MU_CNT(1),\n.C_PROBE720_MU_CNT(1),\n.C_PROBE721_MU_CNT(1),\n.C_PROBE722_MU_CNT(1),\n.C_PROBE723_MU_CNT(1),\n.C_PROBE724_MU_CNT(1),\n.C_PROBE725_MU_CNT(1),\n.C_PROBE726_MU_CNT(1),\n.C_PROBE727_MU_CNT(1),\n.C_PROBE728_MU_CNT(1),\n.C_PROBE729_MU_CNT(1),\n.C_PROBE730_MU_CNT(1),\n.C_PROBE731_MU_CNT(1),\n.C_PROBE732_MU_CNT(1),\n.C_PROBE733_MU_CNT(1),\n.C_PROBE734_MU_CNT(1),\n.C_PROBE735_MU_CNT(1),\n.C_PROBE736_MU_CNT(1),\n.C_PROBE737_MU_CNT(1),\n.C_PROBE738_MU_CNT(1),\n.C_PROBE739_MU_CNT(1),\n.C_PROBE740_MU_CNT(1),\n.C_PROBE741_MU_CNT(1),\n.C_PROBE742_MU_CNT(1),\n.C_PROBE743_MU_CNT(1),\n.C_PROBE744_MU_CNT(1),\n.C_PROBE745_MU_CNT(1),\n.C_PROBE746_MU_CNT(1),\n.C_PROBE747_MU_CNT(1),\n.C_PROBE748_MU_CNT(1),\n.C_PROBE749_MU_CNT(1),\n.C_PROBE750_MU_CNT(1),\n.C_PROBE751_MU_CNT(1),\n.C_PROBE752_MU_CNT(1),\n.C_PROBE753_MU_CNT(1),\n.C_PROBE754_MU_CNT(1),\n.C_PROBE755_MU_CNT(1),\n.C_PROBE756_MU_CNT(1),\n.C_PROBE757_MU_CNT(1),\n.C_PROBE758_MU_CNT(1),\n.C_PROBE759_MU_CNT(1),\n.C_PROBE760_MU_CNT(1),\n.C_PROBE761_MU_CNT(1),\n.C_PROBE762_MU_CNT(1),\n.C_PROBE763_MU_CNT(1),\n.C_PROBE764_MU_CNT(1),\n.C_PROBE765_MU_CNT(1),\n.C_PROBE766_MU_CNT(1),\n.C_PROBE767_MU_CNT(1),\n.C_PROBE768_MU_CNT(1),\n.C_PROBE769_MU_CNT(1),\n.C_PROBE770_MU_CNT(1),\n.C_PROBE771_MU_CNT(1),\n.C_PROBE772_MU_CNT(1),\n.C_PROBE773_MU_CNT(1),\n.C_PROBE774_MU_CNT(1),\n.C_PROBE775_MU_CNT(1),\n.C_PROBE776_MU_CNT(1),\n.C_PROBE777_MU_CNT(1),\n.C_PROBE778_MU_CNT(1),\n.C_PROBE779_MU_CNT(1),\n.C_PROBE780_MU_CNT(1),\n.C_PROBE781_MU_CNT(1),\n.C_PROBE782_MU_CNT(1),\n.C_PROBE783_MU_CNT(1),\n.C_PROBE784_MU_CNT(1),\n.C_PROBE785_MU_CNT(1),\n.C_PROBE786_MU_CNT(1),\n.C_PROBE787_MU_CNT(1),\n.C_PROBE788_MU_CNT(1),\n.C_PROBE789_MU_CNT(1),\n.C_PROBE790_MU_CNT(1),\n.C_PROBE791_MU_CNT(1),\n.C_PROBE792_MU_CNT(1),\n.C_PROBE793_MU_CNT(1),\n.C_PROBE794_MU_CNT(1),\n.C_PROBE795_MU_CNT(1),\n.C_PROBE796_MU_CNT(1),\n.C_PROBE797_MU_CNT(1),\n.C_PROBE798_MU_CNT(1),\n.C_PROBE799_MU_CNT(1),\n.C_PROBE800_MU_CNT(1),\n.C_PROBE801_MU_CNT(1),\n.C_PROBE802_MU_CNT(1),\n.C_PROBE803_MU_CNT(1),\n.C_PROBE804_MU_CNT(1),\n.C_PROBE805_MU_CNT(1),\n.C_PROBE806_MU_CNT(1),\n.C_PROBE807_MU_CNT(1),\n.C_PROBE808_MU_CNT(1),\n.C_PROBE809_MU_CNT(1),\n.C_PROBE810_MU_CNT(1),\n.C_PROBE811_MU_CNT(1),\n.C_PROBE812_MU_CNT(1),\n.C_PROBE813_MU_CNT(1),\n.C_PROBE814_MU_CNT(1),\n.C_PROBE815_MU_CNT(1),\n.C_PROBE816_MU_CNT(1),\n.C_PROBE817_MU_CNT(1),\n.C_PROBE818_MU_CNT(1),\n.C_PROBE819_MU_CNT(1),\n.C_PROBE820_MU_CNT(1),\n.C_PROBE821_MU_CNT(1),\n.C_PROBE822_MU_CNT(1),\n.C_PROBE823_MU_CNT(1),\n.C_PROBE824_MU_CNT(1),\n.C_PROBE825_MU_CNT(1),\n.C_PROBE826_MU_CNT(1),\n.C_PROBE827_MU_CNT(1),\n.C_PROBE828_MU_CNT(1),\n.C_PROBE829_MU_CNT(1),\n.C_PROBE830_MU_CNT(1),\n.C_PROBE831_MU_CNT(1),\n.C_PROBE832_MU_CNT(1),\n.C_PROBE833_MU_CNT(1),\n.C_PROBE834_MU_CNT(1),\n.C_PROBE835_MU_CNT(1),\n.C_PROBE836_MU_CNT(1),\n.C_PROBE837_MU_CNT(1),\n.C_PROBE838_MU_CNT(1),\n.C_PROBE839_MU_CNT(1),\n.C_PROBE840_MU_CNT(1),\n.C_PROBE841_MU_CNT(1),\n.C_PROBE842_MU_CNT(1),\n.C_PROBE843_MU_CNT(1),\n.C_PROBE844_MU_CNT(1),\n.C_PROBE845_MU_CNT(1),\n.C_PROBE846_MU_CNT(1),\n.C_PROBE847_MU_CNT(1),\n.C_PROBE848_MU_CNT(1),\n.C_PROBE849_MU_CNT(1),\n.C_PROBE850_MU_CNT(1),\n.C_PROBE851_MU_CNT(1),\n.C_PROBE852_MU_CNT(1),\n.C_PROBE853_MU_CNT(1),\n.C_PROBE854_MU_CNT(1),\n.C_PROBE855_MU_CNT(1),\n.C_PROBE856_MU_CNT(1),\n.C_PROBE857_MU_CNT(1),\n.C_PROBE858_MU_CNT(1),\n.C_PROBE859_MU_CNT(1),\n.C_PROBE860_MU_CNT(1),\n.C_PROBE861_MU_CNT(1),\n.C_PROBE862_MU_CNT(1),\n.C_PROBE863_MU_CNT(1),\n.C_PROBE864_MU_CNT(1),\n.C_PROBE865_MU_CNT(1),\n.C_PROBE866_MU_CNT(1),\n.C_PROBE867_MU_CNT(1),\n.C_PROBE868_MU_CNT(1),\n.C_PROBE869_MU_CNT(1),\n.C_PROBE870_MU_CNT(1),\n.C_PROBE871_MU_CNT(1),\n.C_PROBE872_MU_CNT(1),\n.C_PROBE873_MU_CNT(1),\n.C_PROBE874_MU_CNT(1),\n.C_PROBE875_MU_CNT(1),\n.C_PROBE876_MU_CNT(1),\n.C_PROBE877_MU_CNT(1),\n.C_PROBE878_MU_CNT(1),\n.C_PROBE879_MU_CNT(1),\n.C_PROBE880_MU_CNT(1),\n.C_PROBE881_MU_CNT(1),\n.C_PROBE882_MU_CNT(1),\n.C_PROBE883_MU_CNT(1),\n.C_PROBE884_MU_CNT(1),\n.C_PROBE885_MU_CNT(1),\n.C_PROBE886_MU_CNT(1),\n.C_PROBE887_MU_CNT(1),\n.C_PROBE888_MU_CNT(1),\n.C_PROBE889_MU_CNT(1),\n.C_PROBE890_MU_CNT(1),\n.C_PROBE891_MU_CNT(1),\n.C_PROBE892_MU_CNT(1),\n.C_PROBE893_MU_CNT(1),\n.C_PROBE894_MU_CNT(1),\n.C_PROBE895_MU_CNT(1),\n.C_PROBE896_MU_CNT(1),\n.C_PROBE897_MU_CNT(1),\n.C_PROBE898_MU_CNT(1),\n.C_PROBE899_MU_CNT(1),\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n.probe985(0),\n.probe986(0),\n.probe987(0),\n.probe988(0),\n.probe989(0),\n.probe990(0),\n.probe991(0),\n.probe992(0),\n.probe993(0),\n.probe994(0),\n.probe995(0),\n.probe996(0),\n.probe997(0),\n.probe998(0),\n.probe999(0),\n.probe1000(0),\n.probe1001(0),\n.probe1002(0),\n.probe1003(0),\n.probe1004(0),\n.probe1005(0),\n.probe1006(0),\n.probe1007(0),\n.probe1008(0),\n.probe1009(0),\n.probe1010(0),\n.probe1011(0),\n.probe1012(0),\n.probe1013(0),\n.probe1014(0),\n.probe1015(0),\n.probe1016(0),\n.probe1017(0),\n.probe1018(0),\n.probe1019(0),\n.probe1020(0),\n.probe1021(0),\n.probe1022(0),\n.probe1023(0)\n)/* synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4337}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//----------------------------------------------------------------------------------\n//Copyright (c) 2014\n//\n//Permission is hereby granted, free of charge, to any person obtaining a copy\n//of this software and associated documentation files (the \"Software\"), to deal\n//in the Software without restriction, including without limitation the rights\n//to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n//copies of the Software, and to permit persons to whom the Software is\n//furnished to do so, subject to the following conditions:\n//\n//The above copyright notice and this permission notice shall be included in\n//all copies or substantial portions of the Software.\n//\n//THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n//IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n//FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n//AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n//LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n//OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n//THE SOFTWARE.\n//----------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//   Description : \n//   \n// This is a flow-through FIFO that converts a RAM-based FIFO (1 clock\n// latency on the RAM) to what looks like a flop based FIFO.  There is\n// no delay between pop and getting the next data.  This sometimes simplifies\n// the FIFO pop logic.\n//\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\nmodule ft_fifo (\n   clk,\n   rst_n,\n\n   sync_rst_n,\n\n   ram_fifo_empty,\n   ram_fifo_data,\n   ft_pop,\n\n   ram_pop,\n\n   ft_valid,\n   ft_data\n   );\n\nparameter FIFO_WIDTH = 32;\n\ninput clk;                          //Global clock\ninput rst_n;                        //Global reset\n\ninput sync_rst_n;                   //Synchronous reset\n\ninput ram_fifo_empty;               //RAM FIFO is empty\ninput[FIFO_WIDTH-1:0] ram_fifo_data;   //RAM FIFO data\ninput ft_pop;                       //POP FT FIFO\n\noutput ram_pop;                     //Pop the RAM FIFO\n\noutput ft_valid;                    //FT FIFO is valid\noutput[FIFO_WIDTH-1:0] ft_data;     //FT FIFO data\n\n////////////////////////////////////////////////////////\n//Flow through FIFO to present data to arbiter\nreg ram_pop_q;                         //Data is valid one clock after pop\nreg[FIFO_WIDTH:0] ft0, ft1;            //Flow through FIFO flops\nwire[FIFO_WIDTH:0] nxt_ft0, nxt_ft1;\n\nwire ft0_valid = ft0[FIFO_WIDTH];\nwire ft1_valid = ft1[FIFO_WIDTH];\n\nassign ram_pop = !ram_fifo_empty && (!ft1_valid||ft_pop) && (!ft0_valid||!ram_pop_q||ft_pop);\n\nalways @(negedge rst_n or posedge clk)\n   if (!rst_n)\n      ram_pop_q <= 0;   \n   else\n      ram_pop_q <= ram_pop; \n\nassign nxt_ft0 = (ram_pop_q && !ft0_valid)? {1'b1, ram_fifo_data}: ft0;\nassign nxt_ft1 = (ram_pop_q && ft0_valid )? {1'b1, ram_fifo_data}: ft1;\n\nalways @(negedge rst_n or posedge clk)\n   if (!rst_n)\n   begin\n      ft0 <= 0;\n      ft1 <= 0;   \n   end\n   else if (!sync_rst_n)\n   begin\n      ft0 <= 0;\n      ft1 <= 0;\n   end\n   else if (ft_pop)\n   begin\n      ft0 <= nxt_ft1;\n      ft1 <= 0;\n   end\n   else\n   begin \n      ft0 <= nxt_ft0;\n      ft1 <= nxt_ft1;\n   end\n\nassign {ft_valid, ft_data} = ft0;\n\nendmodule\n\n", "num_lines": 112}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//----------------------------------------------------------------------------------\n//Copyright (c) 2014\n//\n//Permission is hereby granted, free of charge, to any person obtaining a copy\n//of this software and associated documentation files (the \"Software\"), to deal\n//in the Software without restriction, including without limitation the rights\n//to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n//copies of the Software, and to permit persons to whom the Software is\n//furnished to do so, subject to the following conditions:\n//\n//The above copyright notice and this permission notice shall be included in\n//all copies or substantial portions of the Software.\n//\n//THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n//IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n//FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n//AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n//LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n//OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n//THE SOFTWARE.\n//----------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//   Description : \n//   \n// This is a flow-through FIFO that converts a RAM-based FIFO (2 clock\n// latency on the RAM) to what looks like a flop based FIFO.  There is\n// no delay between pop and getting the next data.  This sometimes simplifies\n// the FIFO pop logic.\n//\n// Note the _p stands for pipelined RAM, which means there is a 2 clock\n// latency on the RAM (registered out data)\n//\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\nmodule ft_fifo_p (\n   clk,\n   rst_n,\n\n   sync_rst_n,\n\n   ram_fifo_empty,\n   ram_fifo_data,\n   ft_pop,\n\n   ram_pop,\n\n   ft_valid,\n   ft_data\n   );\n\nparameter FIFO_WIDTH = 32;\n\ninput clk;                             //Global clock\ninput rst_n;                           //Global reset\n\ninput sync_rst_n;                      //Synchronous reset\n\ninput ram_fifo_empty;                  //RAM FIFO is empty\ninput[FIFO_WIDTH-1:0] ram_fifo_data;   //RAM FIFO data\ninput ft_pop;                          //POP FT FIFO\n\noutput ram_pop;                        //Pop the RAM FIFO\n\noutput ft_valid;                       //FT FIFO is valid\noutput[FIFO_WIDTH-1:0] ft_data;        //FT FIFO data\n\n////////////////////////////////////////////////////////\n//Flow through FIFO to present data to arbiter\nreg ram_pop_q, ram_pop_qq;             //Data is valid two clocks after pop\nreg[FIFO_WIDTH:0] ft0, ft1, ft2;       //Flow through FIFO flops\nwire[FIFO_WIDTH:0] nxt_ft0, nxt_ft1, nxt_ft2;\n\nwire ft0_valid = ft0[FIFO_WIDTH];\nwire ft1_valid = ft1[FIFO_WIDTH];\nwire ft2_valid = ft2[FIFO_WIDTH];\nreg[1:0] num_valid;\n\n//Qualify ft_pop with ft_valid;\nwire qual_ft_pop = ft_pop & ft0_valid;\n\nassign ram_pop = !ram_fifo_empty && sync_rst_n && ((num_valid<3) || qual_ft_pop);\n\n//Keep track of how many valid, will use this to determine if can POP or not\nalways @(negedge rst_n or posedge clk)\n   if (!rst_n)\n      num_valid <= 0;\n   else if (!sync_rst_n)\n      num_valid <= 0;\n   else\n   begin\n      case ({ram_pop, qual_ft_pop})\n         2'b00, 2'b11:  num_valid <= num_valid;\n         2'b01:      num_valid <= num_valid - 1;\n         2'b10:      num_valid <= num_valid + 1;\n      endcase\n   end\n\nalways @(negedge rst_n or posedge clk)\n   if (!rst_n)\n   begin\n      ram_pop_q <= 0;   \n      ram_pop_qq <= 0;\n   end\n   else\n   begin\n      ram_pop_q <= ram_pop; \n      ram_pop_qq <= ram_pop_q;\n   end\n\nassign nxt_ft0 = (ram_pop_qq && !ft0_valid)? {1'b1, ram_fifo_data}: ft0;\nassign nxt_ft1 = (ram_pop_qq && ft0_valid && !ft1_valid )? {1'b1, ram_fifo_data}: ft1;\nassign nxt_ft2 = (ram_pop_qq && ft1_valid && !ft2_valid )? {1'b1, ram_fifo_data}: ft2;\n\nalways @(negedge rst_n or posedge clk)\n   if (!rst_n)\n   begin\n      ft0 <= 0;\n      ft1 <= 0;   \n      ft2 <= 0;   \n   end\n   else if (!sync_rst_n)\n   begin\n      ft0 <= 0;\n      ft1 <= 0;\n      ft2 <= 0;\n   end\n   else if (qual_ft_pop)\n   begin\n      ft0 <= nxt_ft1;\n      ft1 <= nxt_ft2;\n      ft2 <= 0;\n   end\n   else\n   begin \n      ft0 <= nxt_ft0;\n      ft1 <= nxt_ft1;\n      ft2 <= nxt_ft2;\n   end\n\nassign {ft_valid, ft_data} = ft0;\n\n\n/////////////////////////\n//Simulation checks\n/////////////////////////\n//synopsys translate_off\n\n`ifdef DESIGN_ERROR\n`include \"design_error.inc\"\nreg[1:0] num_valid_q;\n \nalways @(posedge clk)\nbegin\n   if (!ft0_valid && ft_pop) begin\n      design_error(\"FIFO underflow (pop when not valid)\");\n   end\n\n   if ((num_valid==0) && (num_valid_q==3) && sync_rst_n)  begin\n      design_error(\"NumValid overflow\");\n   end\n\n   if ((num_valid==3) && (num_valid_q==0)) begin\n      design_error(\"NumValid underflow\");\n   end\n\n   num_valid_q <= num_valid;\nend\n`endif\n//synopsys translate_on\n\nendmodule\n\n", "num_lines": 175}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sync_clock_converter\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_14_axic_sync_clock_converter # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_FAMILY     = \"virtex6\",\n  parameter integer C_PAYLOAD_WIDTH = 32,\n  parameter integer C_S_ACLK_RATIO = 1,\n  parameter integer C_M_ACLK_RATIO = 1 ,\n  parameter integer C_MODE = 0  // 0 = light-weight (1-deep); 1 = fully-pipelined (2-deep)\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input wire                    SAMPLE_CYCLE_EARLY,\n  input wire                    SAMPLE_CYCLE,\n  // Slave side\n  input  wire                        S_ACLK,\n  input  wire                        S_ARESETN,\n  input  wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD,\n  input  wire                        S_VALID,\n  output wire                        S_READY,\n\n  // Master side\n  input  wire                        M_ACLK,\n  input  wire                        M_ARESETN,\n  output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD,\n  output wire                        M_VALID,\n  input  wire                        M_READY\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam [1:0] ZERO = 2'b10;\nlocalparam [1:0] ONE  = 2'b11;\nlocalparam [1:0] TWO  = 2'b01;\nlocalparam [1:0] INIT = 2'b00;\nlocalparam integer P_LIGHT_WT = 0;\nlocalparam integer P_FULLY_REG = 1;\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\ngenerate\n  if (C_S_ACLK_RATIO == C_M_ACLK_RATIO) begin : gen_passthru\n    assign M_PAYLOAD = S_PAYLOAD;\n    assign M_VALID   = S_VALID;\n    assign S_READY   = M_READY;      \n  end else begin : gen_sync_clock_converter\n    wire s_sample_cycle;\n    wire s_sample_cycle_early;\n    wire m_sample_cycle;\n    wire m_sample_cycle_early;\n\n    wire slow_aclk;\n    wire slow_areset;\n    wire s_areset_r;\n    wire m_areset_r;\n   \n    reg  s_tready_r = 1'b0; \n    wire s_tready_ns; \n    reg  m_tvalid_r = 1'b0; \n    wire m_tvalid_ns; \n    reg  [C_PAYLOAD_WIDTH-1:0] m_tpayload_r;\n    reg  [C_PAYLOAD_WIDTH-1:0] m_tstorage_r;\n    wire [C_PAYLOAD_WIDTH-1:0] m_tpayload_ns; \n    wire [C_PAYLOAD_WIDTH-1:0] m_tstorage_ns; \n    reg  m_tready_hold = 1'b0;\n    wire m_tready_sample;\n    wire load_tpayload;\n    wire load_tstorage;\n    wire load_tpayload_from_tstorage;\n    reg [1:0] state = INIT;\n    reg [1:0] next_state;\n    \n    reg s_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge S_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        s_aresetn_r <= 1'b0;\n      end else begin\n        s_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign s_areset_r = ~s_aresetn_r;\n\n    reg m_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge M_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        m_aresetn_r <= 1'b0;\n      end else begin\n        m_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign m_areset_r = ~m_aresetn_r;\n\n    if (C_S_ACLK_RATIO > C_M_ACLK_RATIO) begin : gen_slowclk_mi\n      assign slow_aclk = M_ACLK;\n    end else begin : gen_slowclk_si\n      assign slow_aclk = S_ACLK;\n    end\n  \n    assign slow_areset = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? m_areset_r : s_areset_r;\n    assign s_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE_EARLY : 1'b1;\n    assign s_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE : 1'b1;\n    assign m_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE_EARLY;\n    assign m_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE;\n\n    // Output flop for S_READY, value is encoded into state machine.\n    assign s_tready_ns = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? state[1] & (state != INIT) : next_state[1];\n\n    always @(posedge S_ACLK) begin \n      if (s_areset_r) begin\n        s_tready_r <= 1'b0;\n      end\n      else begin\n        s_tready_r <= s_sample_cycle_early ? s_tready_ns : 1'b0;\n      end\n    end\n\n    assign S_READY = s_tready_r;\n\n    // Output flop for M_VALID\n    assign m_tvalid_ns = next_state[0];\n\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tvalid_r <= 1'b0;\n      end\n      else begin\n        m_tvalid_r <= m_sample_cycle ? m_tvalid_ns : m_tvalid_r & ~M_READY;\n      end\n    end\n\n    assign M_VALID = m_tvalid_r;\n\n    // Hold register for M_READY when M_ACLK is fast.\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tready_hold <= 1'b0;\n      end\n      else begin\n        m_tready_hold <= m_sample_cycle ? 1'b0 : m_tready_sample;\n      end\n    end\n\n    assign m_tready_sample = (M_READY ) | m_tready_hold;\n    // Output/storage flops for PAYLOAD\n    assign m_tpayload_ns = ~load_tpayload ? m_tpayload_r :\n                           load_tpayload_from_tstorage ? m_tstorage_r : \n                           S_PAYLOAD;\n\n    assign m_tstorage_ns = C_MODE ? (load_tstorage ? S_PAYLOAD : m_tstorage_r) : 0;\n\n    always @(posedge slow_aclk) begin \n      m_tpayload_r <= m_tpayload_ns;\n      m_tstorage_r <= C_MODE ? m_tstorage_ns : 0;\n    end\n\n    assign M_PAYLOAD = m_tpayload_r;\n\n    // load logic\n    assign load_tstorage = C_MODE && (state != TWO);\n    assign load_tpayload = m_tready_sample || (state == ZERO);\n    assign load_tpayload_from_tstorage = C_MODE && (state == TWO) && m_tready_sample;\n    \n    // State machine\n    always @(posedge slow_aclk) begin \n      state <= next_state;\n    end\n\n    always @* begin \n      if (slow_areset) begin \n        next_state = INIT;\n      end else begin\n        case (state)\n          INIT: begin\n            next_state = ZERO;\n          end\n          // No transaction stored locally\n          ZERO: begin\n            if (S_VALID) begin\n              next_state = C_MODE ? ONE : TWO; // Push from empty\n            end\n            else begin\n              next_state = ZERO;\n            end\n          end\n\n          // One transaction stored locally\n          ONE: begin\n            if (C_MODE == 0) begin\n              next_state = TWO;  // State ONE is inaccessible when C_MODE=0\n            end \n            else if (m_tready_sample & ~S_VALID) begin \n              next_state = ZERO; // Read out one so move to ZERO\n            end\n            else if (~m_tready_sample & S_VALID) begin\n              next_state = TWO;  // Got another one so move to TWO\n            end\n            else begin\n              next_state = ONE;\n            end\n          end\n\n          // Storage registers full\n          TWO: begin \n            if (m_tready_sample) begin\n              next_state = C_MODE ? ONE : ZERO; // Pop from full\n            end\n            else begin\n              next_state = TWO;\n            end\n          end\n        endcase // case (state)\n      end\n    end\n  end // gen_sync_clock_converter\n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sample_cycle_ratio\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_14_axic_sample_cycle_ratio # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_RATIO = 2 // Must be > 0\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    SLOW_ACLK,\n  input  wire                    FAST_ACLK,\n\n  output wire                    SAMPLE_CYCLE_EARLY,\n  output wire                    SAMPLE_CYCLE\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam P_DELAY = C_RATIO > 2 ? C_RATIO-1 : C_RATIO-1; \n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_aclk_div2 = 1'b0;\nreg                posedge_finder_first = 1'b0;\nreg                posedge_finder_second = 1'b0;\nwire               first_edge;\nwire               second_edge;\nwire               any_edge;\nreg  [P_DELAY-1:0] sample_cycle_d = {P_DELAY{1'b0}};\n(* shreg_extract = \"no\" *) reg                sample_cycle_r = 1'b0;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\ngenerate\n  if (C_RATIO == 1) begin : gen_always_sample\n    assign SAMPLE_CYCLE_EARLY = 1'b1;\n    assign SAMPLE_CYCLE = 1'b1;\n  end\n  else begin : gen_sample_cycle\n    genvar i;\n    always @(posedge SLOW_ACLK) begin \n      slow_aclk_div2 <= ~slow_aclk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_aclk_div2 onto faster clock\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_first <= slow_aclk_div2;\n    end\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_second <= ~slow_aclk_div2;\n    end\n\n    assign first_edge = slow_aclk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;\n    assign any_edge = first_edge | second_edge;\n   \n    // delay the posedge alignment by C_RATIO - 1 to set the sample cycle as\n    // the clock one cycle before the posedge.\n    for (i = P_DELAY-1; i > 0; i = i - 1) begin : gen_delay\n      always @(posedge FAST_ACLK) begin\n        if (i == P_DELAY-1) begin\n          sample_cycle_d[i-1] <= any_edge;\n        end else begin\n          sample_cycle_d[i-1] <= sample_cycle_d[i];\n        end\n      end\n    end\n\n    always @(posedge FAST_ACLK) begin \n      sample_cycle_r <= (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    end\n    assign SAMPLE_CYCLE_EARLY = (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    assign SAMPLE_CYCLE = sample_cycle_r;\n  end\nendgenerate\n\nendmodule // axisc_sample_cycle_ratio\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2010 - 2016 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and\n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Clock converter module\n//   Asynchronous clock converter when asynchronous M:N conversion\n//   Bypass when synchronous and ratio between S and M clock is 1:1\n//   Synchronous clock converter (S:M or M:S must be integer ratio)\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_clock_conv\n//     fifo_generator\n//     axic_sync_clock_converter\n//       axic_sample_cycle_ratio\n//\n// PROTECTED NAMES:\n//   Instance names \"asyncfifo_*\" are pattern-matched in core-level UCF.\n//   Signal names \"*_resync\" are pattern-matched in core-level UCF.\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_14_lite_async #(\n  parameter integer C_DEST_SYNC_FF = 2,\n  parameter integer C_SRC_SYNC_FF  = 2,\n  parameter integer C_WIDTH        = 1\n) (\n  input wire                s_aclk,\n  input wire                m_aclk,\n  input wire                s_aresetn,\n  input wire                m_aresetn,\n  input wire                s_valid,\n  output wire                s_ready,\n  input wire [C_WIDTH-1:0]  s_payld,\n  output wire                m_valid,\n  input wire                m_ready,\n  output wire [C_WIDTH-1:0] m_payld\n);\n\nreg                s_ready_i = 1'b0;\nreg                m_valid_i = 1'b0;\nreg   src_send = 1'b0;\nreg   dest_ack = 1'b0;\nwire  src_rcv;\nwire  dest_req;\n\nassign s_ready = s_ready_i;\nassign m_valid = m_valid_i;\n\nlocalparam SRC_IDLE           = 2'b00;\nlocalparam SRC_DRV_SEND       = 2'b01;\nlocalparam SRC_WAIT_RCV_DONE  = 2'b10;\nreg [1:0] src_state = SRC_IDLE;\n\nalways @(posedge s_aclk) begin\n  if (s_aresetn == 1'b0) begin\n    s_ready_i <= 1'b0;\n    src_send <= 1'b0;\n    src_state <= SRC_IDLE;\n  end else begin\n    case (src_state)\n      SRC_IDLE: begin\n        if (s_valid) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end\n      end\n      SRC_DRV_SEND: begin\n        if (src_rcv) begin\n          s_ready_i <= 1'b1;\n          src_send <= 1'b0;\n          src_state <= SRC_WAIT_RCV_DONE;\n        end\n      end\n      SRC_WAIT_RCV_DONE: begin\n        s_ready_i <= 1'b0;\n        if (s_valid & !src_rcv) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end else if (!src_rcv) begin\n          src_state <= SRC_IDLE;\n        end\n      end\n      default: begin\n        s_ready_i <= 1'b0;\n        src_send <= 1'b0;\n        src_state <= SRC_IDLE;\n      end\n    endcase\n  end\nend\n\nlocalparam DEST_IDLE           = 2'b00;\nlocalparam DEST_DRV_VALID      = 2'b01;\nlocalparam DEST_DRV_ACK        = 2'b10;\nreg [1:0] dest_state = DEST_IDLE;\n\nalways @(posedge m_aclk) begin\n  if (m_aresetn == 1'b0) begin\n    m_valid_i <= 1'b0;\n    dest_ack <= 1'b0;\n    dest_state <= DEST_IDLE;\n  end else begin\n    case (dest_state)\n      DEST_IDLE: begin\n        if (dest_req) begin\n          dest_state <= DEST_DRV_VALID;\n          m_valid_i <= 1'b1;\n        end else begin\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b0;\n        end\n      end\n      DEST_DRV_VALID: begin\n        if (m_ready & m_valid_i) begin\n          dest_state <= DEST_DRV_ACK;\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b1;\n        end\n      end\n      DEST_DRV_ACK: begin\n        if (!dest_req) begin\n          dest_state <= DEST_IDLE;\n          dest_ack <= 1'b0;\n        end\n      end\n      default: begin\n        m_valid_i <= 1'b0;\n        dest_ack <= 1'b0;\n        dest_state <= DEST_IDLE;\n      end\n    endcase\n  end\nend\n\nxpm_cdc_handshake #(\n  .DEST_SYNC_FF   (C_DEST_SYNC_FF),\n  .SRC_SYNC_FF    (C_SRC_SYNC_FF),\n  .WIDTH          (C_WIDTH)\n) handshake (\n  .src_clk  (s_aclk),\n  .src_in   (s_payld),\n  .src_send (src_send),\n  .src_rcv  (src_rcv),\n  .dest_clk (m_aclk),\n  .dest_out (m_payld),\n  .dest_req (dest_req),\n  .dest_ack (dest_ack)\n);\n\nendmodule\n\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_14_axi_clock_converter #\n  (parameter         C_FAMILY = \"virtex7\",\n   parameter integer C_AXI_ID_WIDTH = 5,                    // Width of all ID signals on SI and MI side.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ADDR_WIDTH = 32,                 // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and\n                                                            // m_axi_araddr.\n                                                            // Range: 32.\n   parameter integer C_AXI_DATA_WIDTH = 32,       // Width of WDATA and RDATA (either side).\n                                                            // Format: Bit32;\n                                                            // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.\n   parameter integer C_S_AXI_ACLK_RATIO = 1,     // Clock frequency ratio of SI w.r.t. MI.\n   parameter integer C_M_AXI_ACLK_RATIO = 1,     // (Slowest of all clock inputs should have ratio=1.)\n                                                            // S:M or M:S must be integer ratio.\n                                                            // Format: Bit32; Range: >='h00000001.\n   parameter integer C_AXI_IS_ACLK_ASYNC = 1,            // Indicates whether S and M clocks are asynchronous.\n                                                            // FUTURE FEATURE\n                                                            // Format: Bit1. Range = 1'b0.\n   parameter integer C_AXI_PROTOCOL = 0,         // Protocol of this SI/MI slot.\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS  = 1,      // 1 = Propagate all USER signals, 0 = Do not propagate.\n   parameter integer C_AXI_AWUSER_WIDTH = 1,                // Width of AWUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ARUSER_WIDTH = 1,                // Width of ARUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_WUSER_WIDTH = 1,                 // Width of WUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_RUSER_WIDTH = 1,                 // Width of RUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_BUSER_WIDTH = 1,                 // Width of BUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,              // Implement AXI write channels\n   parameter integer C_AXI_SUPPORTS_READ = 1,               // Implement AXI read channels\n   parameter integer C_SYNCHRONIZER_STAGE = 3\n  )\n\n  (\n   // Slave Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n   input  wire [4-1:0]                    s_axi_awcache,\n   input  wire [3-1:0]                    s_axi_awprot,\n   input  wire [4-1:0]                    s_axi_awregion,\n   input  wire [4-1:0]                    s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0]   s_axi_awuser,\n   input  wire                            s_axi_awvalid,\n   output wire                            s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n   input  wire                            s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]    s_axi_wuser,\n   input  wire                            s_axi_wvalid,\n   output wire                            s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_bid,\n   output wire [2-1:0]                    s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0]    s_axi_buser,\n   output wire                            s_axi_bvalid,\n   input  wire                            s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n   input  wire [3-1:0]                    s_axi_arsize,\n   input  wire [2-1:0]                    s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n   input  wire [4-1:0]                    s_axi_arcache,\n   input  wire [3-1:0]                    s_axi_arprot,\n   input  wire [4-1:0]                    s_axi_arregion,\n   input  wire [4-1:0]                    s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0]   s_axi_aruser,\n   input  wire                            s_axi_arvalid,\n   output wire                            s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n   output wire [2-1:0]                    s_axi_rresp,\n   output wire                            s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0]    s_axi_ruser,\n   output wire                            s_axi_rvalid,\n   input  wire                            s_axi_rready,\n\n   // Master Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aresetn,\n\n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n   output wire [3-1:0]                    m_axi_awsize,\n   output wire [2-1:0]                    m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n   output wire [4-1:0]                    m_axi_awcache,\n   output wire [3-1:0]                    m_axi_awprot,\n   output wire [4-1:0]                    m_axi_awregion,\n   output wire [4-1:0]                    m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0]   m_axi_awuser,\n   output wire                            m_axi_awvalid,\n   input  wire                            m_axi_awready,\n\n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0]   m_axi_wstrb,\n   output wire                            m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]    m_axi_wuser,\n   output wire                            m_axi_wvalid,\n   input  wire                            m_axi_wready,\n\n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_bid,\n   input  wire [2-1:0]                    m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0]    m_axi_buser,\n   input  wire                            m_axi_bvalid,\n   output wire                            m_axi_bready,\n\n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n   output wire [3-1:0]                    m_axi_arsize,\n   output wire [2-1:0]                    m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n   output wire [4-1:0]                    m_axi_arcache,\n   output wire [3-1:0]                    m_axi_arprot,\n   output wire [4-1:0]                    m_axi_arregion,\n   output wire [4-1:0]                    m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0]   m_axi_aruser,\n   output wire                            m_axi_arvalid,\n   input  wire                            m_axi_arready,\n\n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     m_axi_rdata,\n   input  wire [2-1:0]                    m_axi_rresp,\n   input  wire                            m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0]    m_axi_ruser,\n   input  wire                            m_axi_rvalid,\n   output wire                            m_axi_rready);\n\n  localparam integer P_AXI4 = 0;\n  localparam integer P_AXI3 = 1;\n  localparam integer P_AXILITE = 2;\n  localparam integer P_LIGHT_WT = 0;\n  localparam integer P_FULLY_REG = 1;\n  localparam integer P_LUTRAM_ASYNC = 12;\n\n  // Sample cycle ratio\n  localparam  P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);\n  localparam integer P_ROUNDING_OFFSET = P_SI_LT_MI ? (C_S_AXI_ACLK_RATIO/2) : (C_M_AXI_ACLK_RATIO/2);\n  localparam integer P_ACLK_RATIO = P_SI_LT_MI ?\n    ((C_M_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_S_AXI_ACLK_RATIO) :\n    ((C_S_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_M_AXI_ACLK_RATIO);\n\n  // Write Address Port bit positions\n  localparam integer C_AWUSER_RIGHT   = 0;\n  localparam integer C_AWUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_AWUSER_WIDTH : 0;\n  localparam integer C_AWQOS_RIGHT    = C_AWUSER_RIGHT + C_AWUSER_WIDTH;\n  localparam integer C_AWQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWREGION_RIGHT = C_AWQOS_RIGHT + C_AWQOS_WIDTH;\n  localparam integer C_AWREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_AWPROT_RIGHT   = C_AWREGION_RIGHT + C_AWREGION_WIDTH;\n  localparam integer C_AWPROT_WIDTH     = 3;\n  localparam integer C_AWCACHE_RIGHT  = C_AWPROT_RIGHT + C_AWPROT_WIDTH;\n  localparam integer C_AWCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWLOCK_RIGHT   = C_AWCACHE_RIGHT + C_AWCACHE_WIDTH;\n  localparam integer C_AWLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_AWBURST_RIGHT  = C_AWLOCK_RIGHT + C_AWLOCK_WIDTH;\n  localparam integer C_AWBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_AWSIZE_RIGHT   = C_AWBURST_RIGHT + C_AWBURST_WIDTH;\n  localparam integer C_AWSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_AWLEN_RIGHT    = C_AWSIZE_RIGHT + C_AWSIZE_WIDTH;\n  localparam integer C_AWLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_AWADDR_RIGHT   = C_AWLEN_RIGHT + C_AWLEN_WIDTH;\n  localparam integer C_AWADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_AWID_RIGHT     = C_AWADDR_RIGHT + C_AWADDR_WIDTH;\n  localparam integer C_AWID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AW_WIDTH        = C_AWID_RIGHT + C_AWID_WIDTH;\n  localparam integer C_FIFO_AW_WIDTH   = C_AWUSER_WIDTH+C_AWQOS_WIDTH+C_AWQOS_WIDTH+3+C_AWCACHE_WIDTH+C_AWLOCK_WIDTH+C_AWBURST_WIDTH+C_AWSIZE_WIDTH+C_AWLEN_WIDTH+C_AXI_ADDR_WIDTH+C_AWID_WIDTH;\n\n  // Write Data Port bit positions\n  localparam integer C_WUSER_RIGHT   = 0;\n  localparam integer C_WUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_WUSER_WIDTH : 0;\n  localparam integer C_WLAST_RIGHT   = C_WUSER_RIGHT + C_WUSER_WIDTH;\n  localparam integer C_WLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_WSTRB_RIGHT   = C_WLAST_RIGHT + C_WLAST_WIDTH;\n  localparam integer C_WSTRB_WIDTH     = C_AXI_DATA_WIDTH/8;\n  localparam integer C_WDATA_RIGHT   = C_WSTRB_RIGHT + C_WSTRB_WIDTH;\n  localparam integer C_WDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_WID_RIGHT     = C_WDATA_RIGHT + C_WDATA_WIDTH;\n  localparam integer C_WID_WIDTH       = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_W_WIDTH        = C_WID_RIGHT + C_WID_WIDTH;\n  localparam integer C_FIFO_W_WIDTH   = C_WUSER_WIDTH + C_WLAST_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_DATA_WIDTH + C_WID_WIDTH;\n\n  // Write Response Port bit positions\n  localparam integer C_BUSER_RIGHT   = 0;\n  localparam integer C_BUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_BUSER_WIDTH : 0;\n  localparam integer C_BRESP_RIGHT   = C_BUSER_RIGHT + C_BUSER_WIDTH;\n  localparam integer C_BRESP_WIDTH     = 2;\n  localparam integer C_BID_RIGHT     = C_BRESP_RIGHT + C_BRESP_WIDTH;\n  localparam integer C_BID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_B_WIDTH        = C_BID_RIGHT + C_BID_WIDTH;\n  localparam integer C_FIFO_B_WIDTH    = C_BUSER_WIDTH + 2 + C_BID_WIDTH;\n\n  // Read Address Port bit positions\n  localparam integer C_ARUSER_RIGHT   = 0;\n  localparam integer C_ARUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_ARUSER_WIDTH : 0;\n  localparam integer C_ARQOS_RIGHT    = C_ARUSER_RIGHT + C_ARUSER_WIDTH;\n  localparam integer C_ARQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARREGION_RIGHT = C_ARQOS_RIGHT + C_ARQOS_WIDTH;\n  localparam integer C_ARREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_ARPROT_RIGHT   = C_ARREGION_RIGHT + C_ARREGION_WIDTH;\n  localparam integer C_ARPROT_WIDTH     = 3;\n  localparam integer C_ARCACHE_RIGHT  = C_ARPROT_RIGHT + C_ARPROT_WIDTH;\n  localparam integer C_ARCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARLOCK_RIGHT   = C_ARCACHE_RIGHT + C_ARCACHE_WIDTH;\n  localparam integer C_ARLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_ARBURST_RIGHT  = C_ARLOCK_RIGHT + C_ARLOCK_WIDTH;\n  localparam integer C_ARBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_ARSIZE_RIGHT   = C_ARBURST_RIGHT + C_ARBURST_WIDTH;\n  localparam integer C_ARSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_ARLEN_RIGHT    = C_ARSIZE_RIGHT + C_ARSIZE_WIDTH;\n  localparam integer C_ARLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_ARADDR_RIGHT   = C_ARLEN_RIGHT + C_ARLEN_WIDTH;\n  localparam integer C_ARADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_ARID_RIGHT     = C_ARADDR_RIGHT + C_ARADDR_WIDTH;\n  localparam integer C_ARID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AR_WIDTH        = C_ARID_RIGHT + C_ARID_WIDTH;\n  localparam integer C_FIFO_AR_WIDTH   = C_ARUSER_WIDTH+C_ARQOS_WIDTH+C_ARQOS_WIDTH+3+C_ARCACHE_WIDTH+C_ARLOCK_WIDTH+C_ARBURST_WIDTH+C_ARSIZE_WIDTH+C_ARLEN_WIDTH+C_AXI_ADDR_WIDTH+C_ARID_WIDTH;\n\n  // Read Data Ports bit positions\n  localparam integer C_RUSER_RIGHT   = 0;\n  localparam integer C_RUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_RUSER_WIDTH : 0;\n  localparam integer C_RLAST_RIGHT   = C_RUSER_RIGHT + C_RUSER_WIDTH;\n  localparam integer C_RLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_RRESP_RIGHT   = C_RLAST_RIGHT + C_RLAST_WIDTH;\n  localparam integer C_RRESP_WIDTH     = 2;\n  localparam integer C_RDATA_RIGHT   = C_RRESP_RIGHT + C_RRESP_WIDTH;\n  localparam integer C_RDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_RID_RIGHT     = C_RDATA_RIGHT + C_RDATA_WIDTH;\n  localparam integer C_RID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_R_WIDTH        = C_RID_RIGHT + C_RID_WIDTH;\n  localparam integer C_FIFO_R_WIDTH   = C_RUSER_WIDTH + C_RLAST_WIDTH + 2 + C_AXI_DATA_WIDTH + C_RID_WIDTH;\n\n  generate\n    if ((C_AXI_IS_ACLK_ASYNC == 0) && (P_ACLK_RATIO == 1)) begin : gen_bypass\n      \n      // Write address port\n      assign m_axi_awid     = s_axi_awid;\n      assign m_axi_awaddr   = s_axi_awaddr;\n      assign m_axi_awlen    = s_axi_awlen;\n      assign m_axi_awsize   = s_axi_awsize;\n      assign m_axi_awburst  = s_axi_awburst;\n      assign m_axi_awlock   = s_axi_awlock;\n      assign m_axi_awcache  = s_axi_awcache;\n      assign m_axi_awprot   = s_axi_awprot;\n      assign m_axi_awregion = s_axi_awregion;\n      assign m_axi_awqos    = s_axi_awqos;\n      assign m_axi_awuser   = s_axi_awuser;\n      assign m_axi_awvalid  = s_axi_awvalid;\n      assign s_axi_awready  = m_axi_awready;\n\n      // Write Data Port\n      assign m_axi_wid      = s_axi_wid;\n      assign m_axi_wdata    = s_axi_wdata;\n      assign m_axi_wstrb    = s_axi_wstrb;\n      assign m_axi_wlast    = s_axi_wlast;\n      assign m_axi_wuser    = s_axi_wuser;\n      assign m_axi_wvalid   = s_axi_wvalid;\n      assign s_axi_wready   = m_axi_wready;\n\n      // Write Response Port\n      assign s_axi_bid      = m_axi_bid;\n      assign s_axi_bresp    = m_axi_bresp;\n      assign s_axi_buser    = m_axi_buser;\n      assign s_axi_bvalid   = m_axi_bvalid;\n      assign m_axi_bready   = s_axi_bready;\n\n      // Read Address Port\n      assign m_axi_arid     = s_axi_arid;\n      assign m_axi_araddr   = s_axi_araddr;\n      assign m_axi_arlen    = s_axi_arlen;\n      assign m_axi_arsize   = s_axi_arsize;\n      assign m_axi_arburst  = s_axi_arburst;\n      assign m_axi_arlock   = s_axi_arlock;\n      assign m_axi_arcache  = s_axi_arcache;\n      assign m_axi_arprot   = s_axi_arprot;\n      assign m_axi_arregion = s_axi_arregion;\n      assign m_axi_arqos    = s_axi_arqos;\n      assign m_axi_aruser   = s_axi_aruser;\n      assign m_axi_arvalid  = s_axi_arvalid;\n      assign s_axi_arready  = m_axi_arready;\n\n      // Read Data Port\n      assign s_axi_rid      = m_axi_rid;\n      assign s_axi_rdata    = m_axi_rdata;\n      assign s_axi_rresp    = m_axi_rresp;\n      assign s_axi_rlast    = m_axi_rlast;\n      assign s_axi_ruser    = m_axi_ruser;\n      assign s_axi_rvalid   = m_axi_rvalid;\n      assign m_axi_rready   = s_axi_rready;\n      \n    end else begin : gen_clock_conv\n      \n      wire fast_aclk;\n      wire slow_aclk;\n      wire sample_cycle;\n      wire sample_cycle_early;\n    \n      // Write Address Port FIFO data read and write\n      wire [C_AW_WIDTH-1:0] s_aw_mesg ;\n      wire [C_AW_WIDTH-1:0] m_aw_mesg ;\n    \n      // Write Data Port FIFO data read and write\n      wire [C_W_WIDTH-1:0] s_w_mesg;\n      wire [C_W_WIDTH-1:0] m_w_mesg;\n    \n      // Write Response Port FIFO data read and write\n      wire [C_B_WIDTH-1:0] s_b_mesg;\n      wire [C_B_WIDTH-1:0] m_b_mesg;\n    \n      // Read Address Port FIFO data read and write\n      wire [C_AR_WIDTH-1:0] s_ar_mesg;\n      wire [C_AR_WIDTH-1:0] m_ar_mesg;\n    \n      // Read Data Ports FIFO data read and write\n      wire [C_R_WIDTH-1:0] s_r_mesg;\n      wire [C_R_WIDTH-1:0] m_r_mesg;\n    \n      wire async_conv_reset_n;\n      assign async_conv_reset_n = ~(~s_axi_aresetn | ~m_axi_aresetn);\n      \n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_awlen           ;\n      wire [3-1:0]                       si_cc_awsize          ;\n      wire [2-1:0]                       si_cc_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_awlock          ;\n      wire [4-1:0]                       si_cc_awcache         ;\n      wire [3-1:0]                       si_cc_awprot          ;\n      wire [4-1:0]                       si_cc_awregion        ;\n      wire [4-1:0]                       si_cc_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]      si_cc_awuser          ;\n      wire                               si_cc_awvalid         ;\n      wire                               si_cc_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_wid            ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]      si_cc_wstrb           ;\n      wire                               si_cc_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]       si_cc_wuser           ;\n      wire                               si_cc_wvalid          ;\n      wire                               si_cc_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_bid             ;\n      wire [2-1:0]                       si_cc_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]       si_cc_buser           ;\n      wire                               si_cc_bvalid          ;\n      wire                               si_cc_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_arlen           ;\n      wire [3-1:0]                       si_cc_arsize          ;\n      wire [2-1:0]                       si_cc_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_arlock          ;\n      wire [4-1:0]                       si_cc_arcache         ;\n      wire [3-1:0]                       si_cc_arprot          ;\n      wire [4-1:0]                       si_cc_arregion        ;\n      wire [4-1:0]                       si_cc_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]      si_cc_aruser          ;\n      wire                               si_cc_arvalid         ;\n      wire                               si_cc_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_rdata           ;\n      wire [2-1:0]                       si_cc_rresp           ;\n      wire                               si_cc_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]       si_cc_ruser           ;\n      wire                               si_cc_rvalid          ;\n      wire                               si_cc_rready          ;\n      \n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_awlen           ;\n      wire [3-1:0]                      cc_mi_awsize          ;\n      wire [2-1:0]                      cc_mi_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_awlock          ;\n      wire [4-1:0]                      cc_mi_awcache         ;\n      wire [3-1:0]                      cc_mi_awprot          ;\n      wire [4-1:0]                      cc_mi_awregion        ;\n      wire [4-1:0]                      cc_mi_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]     cc_mi_awuser          ;\n      wire                              cc_mi_awvalid         ;\n      wire                              cc_mi_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_wid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]     cc_mi_wstrb           ;\n      wire                              cc_mi_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]      cc_mi_wuser           ;\n      wire                              cc_mi_wvalid          ;\n      wire                              cc_mi_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_bid             ;\n      wire [2-1:0]                      cc_mi_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]      cc_mi_buser           ;\n      wire                              cc_mi_bvalid          ;\n      wire                              cc_mi_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_arlen           ;\n      wire [3-1:0]                      cc_mi_arsize          ;\n      wire [2-1:0]                      cc_mi_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_arlock          ;\n      wire [4-1:0]                      cc_mi_arcache         ;\n      wire [3-1:0]                      cc_mi_arprot          ;\n      wire [4-1:0]                      cc_mi_arregion        ;\n      wire [4-1:0]                      cc_mi_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]     cc_mi_aruser          ;\n      wire                              cc_mi_arvalid         ;\n      wire                              cc_mi_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_rdata           ;\n      wire [2-1:0]                      cc_mi_rresp           ;\n      wire                              cc_mi_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]      cc_mi_ruser           ;\n      wire                              cc_mi_rvalid          ;\n      wire                              cc_mi_rready          ;\n      \n    // Tie-offs\n      assign si_cc_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awid : 0 ;\n      assign si_cc_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awaddr : 0 ;\n      assign si_cc_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_awlen : {4'b0000, s_axi_awlen[3:0]}) : 0 ;\n      assign si_cc_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize : 0 ;\n      assign si_cc_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst : 0 ;\n      assign si_cc_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_awlock : {1'b0, s_axi_awlock[0]}) : 0 ;\n      assign si_cc_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache : 0 ;\n      assign si_cc_awprot    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awprot : 0 ;\n      assign si_cc_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos : 0 ;\n      assign si_cc_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion : 0 ;\n      assign si_cc_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser : 0 ;\n      assign si_cc_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awvalid : 0 ;\n      assign si_cc_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? s_axi_wid : 0 ;\n      assign si_cc_wdata     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wdata : 0 ;\n      assign si_cc_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wstrb : 0 ;\n      assign si_cc_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast : 1'b0 ;\n      assign si_cc_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser : 0 ;\n      assign si_cc_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wvalid : 0 ;\n      assign si_cc_bready    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_bready : 0 ;\n      assign si_cc_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arid : 0 ;\n      assign si_cc_araddr    = (C_AXI_SUPPORTS_READ ) ? s_axi_araddr : 0 ;\n      assign si_cc_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_arlen : {4'b0000, s_axi_arlen[3:0]}) : 0 ;\n      assign si_cc_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize : 0 ;\n      assign si_cc_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst : 0 ;\n      assign si_cc_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_arlock : {1'b0, s_axi_arlock[0]}) : 0 ;\n      assign si_cc_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache : 0 ;\n      assign si_cc_arprot    = (C_AXI_SUPPORTS_READ ) ? s_axi_arprot : 0 ;\n      assign si_cc_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos : 0 ;\n      assign si_cc_arregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion : 0 ;\n      assign si_cc_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser : 0 ;\n      assign si_cc_arvalid   = (C_AXI_SUPPORTS_READ ) ? s_axi_arvalid : 0 ;\n      assign si_cc_rready    = (C_AXI_SUPPORTS_READ ) ? s_axi_rready : 0 ;                                       \n                                                                                               \n      assign s_axi_awready   = (C_AXI_SUPPORTS_WRITE ) ? si_cc_awready : 0 ;\n      assign s_axi_wready    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_wready : 0 ;\n      assign s_axi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_bid : 0 ;\n      assign s_axi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bresp : 0 ;\n      assign s_axi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_buser : 0 ;\n      assign s_axi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bvalid : 0 ;\n      assign s_axi_arready   = (C_AXI_SUPPORTS_READ ) ? si_cc_arready : 0 ;\n      assign s_axi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rid : 0 ;\n      assign s_axi_rdata     = (C_AXI_SUPPORTS_READ ) ? si_cc_rdata : 0 ;\n      assign s_axi_rresp     = (C_AXI_SUPPORTS_READ ) ? si_cc_rresp : 0 ;\n      assign s_axi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rlast : 0 ;\n      assign s_axi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_ruser : 0 ;\n      assign s_axi_rvalid    = (C_AXI_SUPPORTS_READ ) ? si_cc_rvalid : 0 ;\n\n      assign m_axi_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awid : 0 ;\n      assign m_axi_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awaddr : 0 ;\n      assign m_axi_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_awlen : cc_mi_awlen[3:0]) : 0 ;\n      assign m_axi_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awsize : 0 ;\n      assign m_axi_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awburst : 0 ;\n      assign m_axi_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_awlock : cc_mi_awlock[0]) : 0 ;\n      assign m_axi_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awcache : 0 ;\n      assign m_axi_awprot    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awprot : 0 ;\n      assign m_axi_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_awregion : 0 ;\n      assign m_axi_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awqos : 0 ;\n      assign m_axi_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_awuser : 0 ;\n      assign m_axi_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awvalid : 0 ;\n      assign m_axi_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? cc_mi_wid : 0 ;\n      assign m_axi_wdata     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wdata : 0 ;\n      assign m_axi_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wstrb : 0 ;\n      assign m_axi_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_wlast : 0 ;\n      assign m_axi_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_wuser : 0 ;\n      assign m_axi_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wvalid : 0 ;\n      assign m_axi_bready    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_bready : 0 ;\n      assign m_axi_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arid : 0 ;\n      assign m_axi_araddr    = (C_AXI_SUPPORTS_READ ) ? cc_mi_araddr : 0 ;\n      assign m_axi_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_arlen : cc_mi_arlen[3:0]) : 0 ;\n      assign m_axi_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arsize : 0 ;\n      assign m_axi_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arburst : 0 ;\n      assign m_axi_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_arlock : cc_mi_arlock[0]) : 0 ;\n      assign m_axi_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arcache : 0 ;\n      assign m_axi_arprot    = (C_AXI_SUPPORTS_READ ) ? cc_mi_arprot : 0 ;\n      assign m_axi_arregion  = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_arregion : 0 ;\n      assign m_axi_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arqos : 0 ;\n      assign m_axi_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_aruser : 0 ;\n      assign m_axi_arvalid   = (C_AXI_SUPPORTS_READ ) ? cc_mi_arvalid : 0 ;\n      assign m_axi_rready    = (C_AXI_SUPPORTS_READ ) ? cc_mi_rready : 0 ;\n                                                                                                                                                                                                                                                                                        \n      assign cc_mi_awready   = (C_AXI_SUPPORTS_WRITE ) ? m_axi_awready : 0 ;\n      assign cc_mi_wready    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_wready : 0 ;\n      assign cc_mi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid : 0 ;\n      assign cc_mi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bresp : 0 ;\n      assign cc_mi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser : 0 ;\n      assign cc_mi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bvalid : 0 ;\n      assign cc_mi_arready   = (C_AXI_SUPPORTS_READ ) ? m_axi_arready : 0 ;\n      assign cc_mi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid : 0 ;\n      assign cc_mi_rdata     = (C_AXI_SUPPORTS_READ ) ? m_axi_rdata : 0 ;\n      assign cc_mi_rresp     = (C_AXI_SUPPORTS_READ ) ? m_axi_rresp : 0 ;\n      assign cc_mi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast : 1'b0 ;\n      assign cc_mi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser : 0 ;\n      assign cc_mi_rvalid    = (C_AXI_SUPPORTS_READ ) ? m_axi_rvalid : 0 ;\n      \n      if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL!=P_AXILITE)) begin : gen_async_conv\n        \n        fifo_generator_v13_2_1 #(\n          .C_EN_SAFETY_CKT(0),\n          .C_SELECT_XPM(0),\n          .C_INTERFACE_TYPE(2),\n          .C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ? 3 : 2),\n          .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n          .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n          .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n          .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n          .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n          .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),\n          .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n          .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n          .C_HAS_AXI_ID((C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0),\n          .C_AXI_LEN_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 8 : 4),\n          .C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 1 : 2),\n          .C_HAS_AXI_ARUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_AWUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_BUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_RUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_WUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_DIN_WIDTH_RACH(C_FIFO_AR_WIDTH),\n          .C_DIN_WIDTH_RDCH(C_FIFO_R_WIDTH),\n          .C_DIN_WIDTH_WACH(C_FIFO_AW_WIDTH),\n          .C_DIN_WIDTH_WDCH(C_FIFO_W_WIDTH),\n          .C_DIN_WIDTH_WRCH(C_FIFO_B_WIDTH),\n          .C_HAS_AXI_RD_CHANNEL(C_AXI_SUPPORTS_READ),\n          .C_HAS_AXI_WR_CHANNEL(C_AXI_SUPPORTS_WRITE),\n          .C_RACH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_RDCH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_WACH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WDCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WRCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),\n          .C_COMMON_CLOCK(0),\n          .C_COUNT_TYPE(0),\n          .C_DATA_COUNT_WIDTH(10),\n          .C_DEFAULT_VALUE(\"BlankString\"),\n          .C_DIN_WIDTH(18),\n          .C_DOUT_RST_VAL(\"0\"),\n          .C_DOUT_WIDTH(18),\n          .C_ENABLE_RLOCS(0),\n          .C_FAMILY(C_FAMILY),\n          .C_FULL_FLAGS_RST_VAL(1),\n          .C_HAS_ALMOST_EMPTY(0),\n          .C_HAS_ALMOST_FULL(0),\n          .C_HAS_BACKUP(0),\n          .C_HAS_DATA_COUNT(0),\n          .C_HAS_INT_CLK(0),\n          .C_HAS_MEMINIT_FILE(0),\n          .C_HAS_OVERFLOW(0),\n          .C_HAS_RD_DATA_COUNT(0),\n          .C_HAS_RD_RST(0),\n          .C_HAS_RST(1),\n          .C_HAS_SRST(0),\n          .C_HAS_UNDERFLOW(0),\n          .C_HAS_VALID(0),\n          .C_HAS_WR_ACK(0),\n          .C_HAS_WR_DATA_COUNT(0),\n          .C_HAS_WR_RST(0),\n          .C_IMPLEMENTATION_TYPE(0),\n          .C_INIT_WR_PNTR_VAL(0),\n          .C_MEMORY_TYPE(1),\n          .C_MIF_FILE_NAME(\"BlankString\"),\n          .C_OPTIMIZATION_MODE(0),\n          .C_OVERFLOW_LOW(0),\n          .C_PRELOAD_LATENCY(1),\n          .C_PRELOAD_REGS(0),\n          .C_PRIM_FIFO_TYPE(\"4kx4\"),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),\n          .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),\n          .C_PROG_EMPTY_TYPE(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL(1022),\n          .C_PROG_FULL_THRESH_NEGATE_VAL(1021),\n          .C_PROG_FULL_TYPE(0),\n          .C_RD_DATA_COUNT_WIDTH(10),\n          .C_RD_DEPTH(1024),\n          .C_RD_FREQ(1),\n          .C_RD_PNTR_WIDTH(10),\n          .C_UNDERFLOW_LOW(0),\n          .C_USE_DOUT_RST(1),\n          .C_USE_ECC(0),\n          .C_USE_EMBEDDED_REG(0),\n          .C_USE_FIFO16_FLAGS(0),\n          .C_USE_FWFT_DATA_COUNT(0),\n          .C_VALID_LOW(0),\n          .C_WR_ACK_LOW(0),\n          .C_WR_DATA_COUNT_WIDTH(10),\n          .C_WR_DEPTH(1024),\n          .C_WR_FREQ(1),\n          .C_WR_PNTR_WIDTH(10),\n          .C_WR_RESPONSE_LATENCY(1),\n          .C_MSGON_VAL(1),\n          .C_ENABLE_RST_SYNC(1),\n          .C_ERROR_INJECTION_TYPE(0),\n          .C_HAS_SLAVE_CE(0),\n          .C_HAS_MASTER_CE(0),\n          .C_ADD_NGC_CONSTRAINT(0),\n          .C_USE_COMMON_OVERFLOW(0),\n          .C_USE_COMMON_UNDERFLOW(0),\n          .C_USE_DEFAULT_SETTINGS(0),\n          .C_HAS_AXIS_TDATA(1),\n          .C_HAS_AXIS_TID(0),\n          .C_HAS_AXIS_TDEST(0),\n          .C_HAS_AXIS_TUSER(1),\n          .C_HAS_AXIS_TREADY(1),\n          .C_HAS_AXIS_TLAST(0),\n          .C_HAS_AXIS_TSTRB(0),\n          .C_HAS_AXIS_TKEEP(0),\n          .C_AXIS_TDATA_WIDTH(8),\n          .C_AXIS_TID_WIDTH(1),\n          .C_AXIS_TDEST_WIDTH(1),\n          .C_AXIS_TUSER_WIDTH(4),\n          .C_AXIS_TSTRB_WIDTH(1),\n          .C_AXIS_TKEEP_WIDTH(1),\n          .C_AXIS_TYPE(0),\n          .C_IMPLEMENTATION_TYPE_WACH(12),\n          .C_IMPLEMENTATION_TYPE_WDCH(12),\n          .C_IMPLEMENTATION_TYPE_WRCH(12),\n          .C_IMPLEMENTATION_TYPE_RACH(12),\n          .C_IMPLEMENTATION_TYPE_RDCH(12),\n          .C_IMPLEMENTATION_TYPE_AXIS(11),\n          .C_APPLICATION_TYPE_WACH(0),\n          .C_APPLICATION_TYPE_WDCH(0),\n          .C_APPLICATION_TYPE_WRCH(0),\n          .C_APPLICATION_TYPE_RACH(0),\n          .C_APPLICATION_TYPE_RDCH(0),\n          .C_APPLICATION_TYPE_AXIS(0),\n          .C_USE_ECC_WACH(0),\n          .C_USE_ECC_WDCH(0),\n          .C_USE_ECC_WRCH(0),\n          .C_USE_ECC_RACH(0),\n          .C_USE_ECC_RDCH(0),\n          .C_USE_ECC_AXIS(0),\n          .C_ERROR_INJECTION_TYPE_WACH(0),\n          .C_ERROR_INJECTION_TYPE_WDCH(0),\n          .C_ERROR_INJECTION_TYPE_WRCH(0),\n          .C_ERROR_INJECTION_TYPE_RACH(0),\n          .C_ERROR_INJECTION_TYPE_RDCH(0),\n          .C_ERROR_INJECTION_TYPE_AXIS(0),\n          .C_DIN_WIDTH_AXIS(1),\n          .C_WR_DEPTH_WACH(16),\n          .C_WR_DEPTH_WDCH(16),\n          .C_WR_DEPTH_WRCH(16),\n          .C_WR_DEPTH_RACH(16),\n          .C_WR_DEPTH_RDCH(16),\n          .C_WR_DEPTH_AXIS(1024),\n          .C_WR_PNTR_WIDTH_WACH(4),\n          .C_WR_PNTR_WIDTH_WDCH(4),\n          .C_WR_PNTR_WIDTH_WRCH(4),\n          .C_WR_PNTR_WIDTH_RACH(4),\n          .C_WR_PNTR_WIDTH_RDCH(4),\n          .C_WR_PNTR_WIDTH_AXIS(10),\n          .C_HAS_DATA_COUNTS_WACH(0),\n          .C_HAS_DATA_COUNTS_WDCH(0),\n          .C_HAS_DATA_COUNTS_WRCH(0),\n          .C_HAS_DATA_COUNTS_RACH(0),\n          .C_HAS_DATA_COUNTS_RDCH(0),\n          .C_HAS_DATA_COUNTS_AXIS(0),\n          .C_HAS_PROG_FLAGS_WACH(0),\n          .C_HAS_PROG_FLAGS_WDCH(0),\n          .C_HAS_PROG_FLAGS_WRCH(0),\n          .C_HAS_PROG_FLAGS_RACH(0),\n          .C_HAS_PROG_FLAGS_RDCH(0),\n          .C_HAS_PROG_FLAGS_AXIS(0),\n          .C_PROG_FULL_TYPE_WACH(0),\n          .C_PROG_FULL_TYPE_WDCH(0),\n          .C_PROG_FULL_TYPE_WRCH(0),\n          .C_PROG_FULL_TYPE_RACH(0),\n          .C_PROG_FULL_TYPE_RDCH(0),\n          .C_PROG_FULL_TYPE_AXIS(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),\n          .C_PROG_EMPTY_TYPE_WACH(0),\n          .C_PROG_EMPTY_TYPE_WDCH(0),\n          .C_PROG_EMPTY_TYPE_WRCH(0),\n          .C_PROG_EMPTY_TYPE_RACH(0),\n          .C_PROG_EMPTY_TYPE_RDCH(0),\n          .C_PROG_EMPTY_TYPE_AXIS(0),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1021),\n          .C_REG_SLICE_MODE_WACH(0),\n          .C_REG_SLICE_MODE_WDCH(0),\n          .C_REG_SLICE_MODE_WRCH(0),\n          .C_REG_SLICE_MODE_RACH(0),\n          .C_REG_SLICE_MODE_RDCH(0),\n          .C_REG_SLICE_MODE_AXIS(0)\n          )\n          asyncfifo_axi (\n            .s_aclk(s_axi_aclk),\n            .m_aclk(m_axi_aclk),\n            .s_aresetn(async_conv_reset_n),\n            .s_axi_awid           (si_cc_awid),\n            .s_axi_awaddr         (si_cc_awaddr),\n            .s_axi_awlen          (si_cc_awlen),\n            .s_axi_awsize         (si_cc_awsize),\n            .s_axi_awburst        (si_cc_awburst),\n            .s_axi_awlock         (si_cc_awlock),\n            .s_axi_awcache        (si_cc_awcache),\n            .s_axi_awprot         (si_cc_awprot),\n            .s_axi_awqos          (si_cc_awqos),\n            .s_axi_awregion       (si_cc_awregion),\n            .s_axi_awuser         (si_cc_awuser),\n            .s_axi_awvalid        (si_cc_awvalid),\n            .s_axi_awready        (si_cc_awready),\n            .s_axi_wid            (si_cc_wid),\n            .s_axi_wdata          (si_cc_wdata),\n            .s_axi_wstrb          (si_cc_wstrb),\n            .s_axi_wlast          (si_cc_wlast),\n            .s_axi_wuser          (si_cc_wuser),\n            .s_axi_wvalid         (si_cc_wvalid),\n            .s_axi_wready         (si_cc_wready),\n            .s_axi_bid            (si_cc_bid),\n            .s_axi_bresp          (si_cc_bresp),\n            .s_axi_buser          (si_cc_buser),\n            .s_axi_bvalid         (si_cc_bvalid),\n            .s_axi_bready         (si_cc_bready),\n            .m_axi_awid           (cc_mi_awid),\n            .m_axi_awaddr         (cc_mi_awaddr),\n            .m_axi_awlen          (cc_mi_awlen),\n            .m_axi_awsize         (cc_mi_awsize),\n            .m_axi_awburst        (cc_mi_awburst),\n            .m_axi_awlock         (cc_mi_awlock),\n            .m_axi_awcache        (cc_mi_awcache),\n            .m_axi_awprot         (cc_mi_awprot),\n            .m_axi_awqos          (cc_mi_awqos),\n            .m_axi_awregion       (cc_mi_awregion),\n            .m_axi_awuser         (cc_mi_awuser),\n            .m_axi_awvalid        (cc_mi_awvalid),\n            .m_axi_awready        (cc_mi_awready),\n            .m_axi_wid            (cc_mi_wid),\n            .m_axi_wdata          (cc_mi_wdata),\n            .m_axi_wstrb          (cc_mi_wstrb),\n            .m_axi_wlast          (cc_mi_wlast),\n            .m_axi_wuser          (cc_mi_wuser),\n            .m_axi_wvalid         (cc_mi_wvalid),\n            .m_axi_wready         (cc_mi_wready),\n            .m_axi_bid            (cc_mi_bid),\n            .m_axi_bresp          (cc_mi_bresp),\n            .m_axi_buser          (cc_mi_buser),\n            .m_axi_bvalid         (cc_mi_bvalid),\n            .m_axi_bready         (cc_mi_bready),\n            .s_axi_arid           (si_cc_arid),\n            .s_axi_araddr         (si_cc_araddr),\n            .s_axi_arlen          (si_cc_arlen),\n            .s_axi_arsize         (si_cc_arsize),\n            .s_axi_arburst        (si_cc_arburst),\n            .s_axi_arlock         (si_cc_arlock),\n            .s_axi_arcache        (si_cc_arcache),\n            .s_axi_arprot         (si_cc_arprot),\n            .s_axi_arqos          (si_cc_arqos),\n            .s_axi_arregion       (si_cc_arregion),\n            .s_axi_aruser         (si_cc_aruser),\n            .s_axi_arvalid        (si_cc_arvalid),\n            .s_axi_arready        (si_cc_arready),\n            .s_axi_rid            (si_cc_rid),\n            .s_axi_rdata          (si_cc_rdata),\n            .s_axi_rresp          (si_cc_rresp),\n            .s_axi_rlast          (si_cc_rlast),\n            .s_axi_ruser          (si_cc_ruser),\n            .s_axi_rvalid         (si_cc_rvalid),\n            .s_axi_rready         (si_cc_rready),\n            .m_axi_arid           (cc_mi_arid),\n            .m_axi_araddr         (cc_mi_araddr),\n            .m_axi_arlen          (cc_mi_arlen),\n            .m_axi_arsize         (cc_mi_arsize),\n            .m_axi_arburst        (cc_mi_arburst),\n            .m_axi_arlock         (cc_mi_arlock),\n            .m_axi_arcache        (cc_mi_arcache),\n            .m_axi_arprot         (cc_mi_arprot),\n            .m_axi_arqos          (cc_mi_arqos),\n            .m_axi_arregion       (cc_mi_arregion),\n            .m_axi_aruser         (cc_mi_aruser),\n            .m_axi_arvalid        (cc_mi_arvalid),\n            .m_axi_arready        (cc_mi_arready),\n            .m_axi_rid            (cc_mi_rid),\n            .m_axi_rdata          (cc_mi_rdata),\n            .m_axi_rresp          (cc_mi_rresp),\n            .m_axi_rlast          (cc_mi_rlast),\n            .m_axi_ruser          (cc_mi_ruser),\n            .m_axi_rvalid         (cc_mi_rvalid),\n            .m_axi_rready         (cc_mi_rready),\n            .m_aclk_en(1'b1),\n            .s_aclk_en(1'b1),\n            .almost_empty(),\n            .almost_full(),\n            .axis_data_count(),\n            .axis_dbiterr(),\n            .axis_injectdbiterr(1'b0),\n            .axis_injectsbiterr(1'b0),\n            .axis_overflow(),\n            .axis_prog_empty(),\n            .axis_prog_empty_thresh(10'b0),\n            .axis_prog_full(),\n            .axis_prog_full_thresh(10'b0),\n            .axis_rd_data_count(),\n            .axis_sbiterr(),\n            .axis_underflow(),\n            .axis_wr_data_count(),\n            .axi_ar_data_count(),\n            .axi_ar_dbiterr(),\n            .axi_ar_injectdbiterr(1'b0),\n            .axi_ar_injectsbiterr(1'b0),\n            .axi_ar_overflow(),\n            .axi_ar_prog_empty(),\n            .axi_ar_prog_empty_thresh(4'b0),\n            .axi_ar_prog_full(),\n            .axi_ar_prog_full_thresh(4'b0),\n            .axi_ar_rd_data_count(),\n            .axi_ar_sbiterr(),\n            .axi_ar_underflow(),\n            .axi_ar_wr_data_count(),\n            .axi_aw_data_count(),\n            .axi_aw_dbiterr(),\n            .axi_aw_injectdbiterr(1'b0),\n            .axi_aw_injectsbiterr(1'b0),\n            .axi_aw_overflow(),\n            .axi_aw_prog_empty(),\n            .axi_aw_prog_empty_thresh(4'b0),\n            .axi_aw_prog_full(),\n            .axi_aw_prog_full_thresh(4'b0),\n            .axi_aw_rd_data_count(),\n            .axi_aw_sbiterr(),\n            .axi_aw_underflow(),\n            .axi_aw_wr_data_count(),\n            .axi_b_data_count(),\n            .axi_b_dbiterr(),\n            .axi_b_injectdbiterr(1'b0),\n            .axi_b_injectsbiterr(1'b0),\n            .axi_b_overflow(),\n            .axi_b_prog_empty(),\n            .axi_b_prog_empty_thresh(4'b0),\n            .axi_b_prog_full(),\n            .axi_b_prog_full_thresh(4'b0),\n            .axi_b_rd_data_count(),\n            .axi_b_sbiterr(),\n            .axi_b_underflow(),\n            .axi_b_wr_data_count(),\n            .axi_r_data_count(),\n            .axi_r_dbiterr(),\n            .axi_r_injectdbiterr(1'b0),\n            .axi_r_injectsbiterr(1'b0),\n            .axi_r_overflow(),\n            .axi_r_prog_empty(),\n            .axi_r_prog_empty_thresh(4'b0),\n            .axi_r_prog_full(),\n            .axi_r_prog_full_thresh(4'b0),\n            .axi_r_rd_data_count(),\n            .axi_r_sbiterr(),\n            .axi_r_underflow(),\n            .axi_r_wr_data_count(),\n            .axi_w_data_count(),\n            .axi_w_dbiterr(),\n            .axi_w_injectdbiterr(1'b0),\n            .axi_w_injectsbiterr(1'b0),\n            .axi_w_overflow(),\n            .axi_w_prog_empty(),\n            .axi_w_prog_empty_thresh(4'b0),\n            .axi_w_prog_full(),\n            .axi_w_prog_full_thresh(4'b0),\n            .axi_w_rd_data_count(),\n            .axi_w_sbiterr(),\n            .axi_w_underflow(),\n            .axi_w_wr_data_count(),\n            .backup(1'b0),\n            .backup_marker(1'b0),\n            .clk(1'b0),\n            .data_count(),\n            .dbiterr(),\n            .din(18'b0),\n            .dout(),\n            .empty(),\n            .full(),\n            .injectdbiterr(1'b0),\n            .injectsbiterr(1'b0),\n            .int_clk(1'b0),\n            .m_axis_tdata(),\n            .m_axis_tdest(),\n            .m_axis_tid(),\n            .m_axis_tkeep(),\n            .m_axis_tlast(),\n            .m_axis_tready(1'b0),\n            .m_axis_tstrb(),\n            .m_axis_tuser(),\n            .m_axis_tvalid(),\n            .overflow(),\n            .prog_empty(),\n            .prog_empty_thresh(10'b0),\n            .prog_empty_thresh_assert(10'b0),\n            .prog_empty_thresh_negate(10'b0),\n            .prog_full(),\n            .prog_full_thresh(10'b0),\n            .prog_full_thresh_assert(10'b0),\n            .prog_full_thresh_negate(10'b0),\n            .rd_clk(1'b0),\n            .rd_data_count(),\n            .rd_en(1'b0),\n            .rd_rst(1'b0),\n            .rst(1'b0),\n            .sbiterr(),\n            .srst(1'b0),\n            .s_axis_tdata(8'b0),\n            .s_axis_tdest(1'b0),\n            .s_axis_tid(1'b0),\n            .s_axis_tkeep(1'b0),\n            .s_axis_tlast(1'b0),\n            .s_axis_tready(),\n            .s_axis_tstrb(1'b0),\n            .s_axis_tuser(4'b0),\n            .s_axis_tvalid(1'b0),\n            .underflow(),\n            .valid(),\n            .wr_ack(),\n            .wr_clk(1'b0),\n            .wr_data_count(),\n            .wr_en(1'b0),\n            .wr_rst(1'b0),\n            .wr_rst_busy(),\n            .rd_rst_busy(),\n            .sleep(1'b0)\n        );\n      end else if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_async_lite_conv\n        localparam C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n        `include \"axi_infrastructure_v1_1_0.vh\"\n\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n        axi_infrastructure_v1_1_0_axi2vector #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        axi2vec ( \n          .s_axi_awid      ( si_cc_awid      ) ,\n          .s_axi_awaddr    ( si_cc_awaddr    ) ,\n          .s_axi_awlen     ( s_axi_awlen     ) ,\n          .s_axi_awsize    ( si_cc_awsize    ) ,\n          .s_axi_awburst   ( si_cc_awburst   ) ,\n          .s_axi_awlock    ( s_axi_awlock    ) ,\n          .s_axi_awcache   ( si_cc_awcache   ) ,\n          .s_axi_awprot    ( si_cc_awprot    ) ,\n          .s_axi_awqos     ( si_cc_awqos     ) ,\n          .s_axi_awuser    ( si_cc_awuser    ) ,\n          .s_axi_awregion  ( si_cc_awregion  ) ,\n          .s_axi_wid       ( si_cc_wid       ) ,\n          .s_axi_wdata     ( si_cc_wdata     ) ,\n          .s_axi_wstrb     ( si_cc_wstrb     ) ,\n          .s_axi_wlast     ( si_cc_wlast     ) ,\n          .s_axi_wuser     ( si_cc_wuser     ) ,\n          .s_axi_bid       ( si_cc_bid       ) ,\n          .s_axi_bresp     ( si_cc_bresp     ) ,\n          .s_axi_buser     ( si_cc_buser     ) ,\n          .s_axi_arid      ( si_cc_arid      ) ,\n          .s_axi_araddr    ( si_cc_araddr    ) ,\n          .s_axi_arlen     ( s_axi_arlen     ) ,\n          .s_axi_arsize    ( si_cc_arsize    ) ,\n          .s_axi_arburst   ( si_cc_arburst   ) ,\n          .s_axi_arlock    ( s_axi_arlock    ) ,\n          .s_axi_arcache   ( si_cc_arcache   ) ,\n          .s_axi_arprot    ( si_cc_arprot    ) ,\n          .s_axi_arqos     ( si_cc_arqos     ) ,\n          .s_axi_aruser    ( si_cc_aruser    ) ,\n          .s_axi_arregion  ( si_cc_arregion  ) ,\n          .s_axi_rid       ( si_cc_rid       ) ,\n          .s_axi_rdata     ( si_cc_rdata     ) ,\n          .s_axi_rresp     ( si_cc_rresp     ) ,\n          .s_axi_rlast     ( si_cc_rlast     ) ,\n          .s_axi_ruser     ( si_cc_ruser     ) ,\n          .s_awpayload     ( s_awpayload ) ,\n          .s_wpayload      ( s_wpayload  ) ,\n          .s_bpayload      ( s_bpayload  ) ,\n          .s_arpayload     ( s_arpayload ) ,\n          .s_rpayload      ( s_rpayload  ) \n        );\n\n        axi_clock_converter_v2_1_14_lite_async #(\n          .C_DEST_SYNC_FF (2),\n          .C_SRC_SYNC_FF  (2),\n          .C_WIDTH        (G_AXI_AWPAYLOAD_WIDTH)\n        ) aw_handshake (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_awvalid),\n          .s_ready  (si_cc_awready),\n          .s_payld  (s_awpayload),\n          .m_valid  (cc_mi_awvalid),\n          .m_ready  (cc_mi_awready),\n          .m_payld  (m_awpayload)\n        );\n\n        axi_clock_converter_v2_1_14_lite_async #(\n          .C_DEST_SYNC_FF (2),\n          .C_SRC_SYNC_FF  (2),\n          .C_WIDTH        (G_AXI_ARPAYLOAD_WIDTH)\n        ) ar_handshake (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_arvalid),\n          .s_ready  (si_cc_arready),\n          .s_payld  (s_arpayload),\n          .m_valid  (cc_mi_arvalid),\n          .m_ready  (cc_mi_arready),\n          .m_payld  (m_arpayload)\n        );\n\n        axi_clock_converter_v2_1_14_lite_async #(\n          .C_DEST_SYNC_FF (2),\n          .C_SRC_SYNC_FF  (2),\n          .C_WIDTH        (G_AXI_WPAYLOAD_WIDTH)\n        ) w_handshake (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_wvalid),\n          .s_ready  (si_cc_wready),\n          .s_payld  (s_wpayload),\n          .m_valid  (cc_mi_wvalid),\n          .m_ready  (cc_mi_wready),\n          .m_payld  (m_wpayload)\n        );\n\n        axi_clock_converter_v2_1_14_lite_async #(\n          .C_DEST_SYNC_FF (2),\n          .C_SRC_SYNC_FF  (2),\n          .C_WIDTH        (G_AXI_BPAYLOAD_WIDTH)\n        ) b_handshake (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_bvalid),\n          .s_ready  (cc_mi_bready),\n          .s_payld  (m_bpayload),\n          .m_valid  (si_cc_bvalid),\n          .m_ready  (si_cc_bready),\n          .m_payld  (s_bpayload)\n        );\n\n        axi_clock_converter_v2_1_14_lite_async #(\n          .C_DEST_SYNC_FF (2),\n          .C_SRC_SYNC_FF  (2),\n          .C_WIDTH        (G_AXI_RPAYLOAD_WIDTH)\n        ) r_handshake (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_rvalid),\n          .s_ready  (cc_mi_rready),\n          .s_payld  (m_rpayload),\n          .m_valid  (si_cc_rvalid),\n          .m_ready  (si_cc_rready),\n          .m_payld  (s_rpayload)\n        );\n\n        axi_infrastructure_v1_1_0_vector2axi #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        vec2axi ( \n          .m_awpayload    ( m_awpayload    ) ,\n          .m_wpayload     ( m_wpayload     ) ,\n          .m_bpayload     ( m_bpayload     ) ,\n          .m_arpayload    ( m_arpayload    ) ,\n          .m_rpayload     ( m_rpayload     ) ,\n          .m_axi_awid     ( cc_mi_awid     ) ,\n          .m_axi_awaddr   ( cc_mi_awaddr   ) ,\n          .m_axi_awlen    ( cc_mi_awlen    ) ,\n          .m_axi_awsize   ( cc_mi_awsize   ) ,\n          .m_axi_awburst  ( cc_mi_awburst  ) ,\n          .m_axi_awlock   ( cc_mi_awlock   ) ,\n          .m_axi_awcache  ( cc_mi_awcache  ) ,\n          .m_axi_awprot   ( cc_mi_awprot   ) ,\n          .m_axi_awqos    ( cc_mi_awqos    ) ,\n          .m_axi_awuser   ( cc_mi_awuser   ) ,\n          .m_axi_awregion ( cc_mi_awregion ) ,\n          .m_axi_wid      ( cc_mi_wid      ) ,\n          .m_axi_wdata    ( cc_mi_wdata    ) ,\n          .m_axi_wstrb    ( cc_mi_wstrb    ) ,\n          .m_axi_wlast    ( cc_mi_wlast    ) ,\n          .m_axi_wuser    ( cc_mi_wuser    ) ,\n          .m_axi_bid      ( cc_mi_bid      ) ,\n          .m_axi_bresp    ( cc_mi_bresp    ) ,\n          .m_axi_buser    ( cc_mi_buser    ) ,\n          .m_axi_arid     ( cc_mi_arid     ) ,\n          .m_axi_araddr   ( cc_mi_araddr   ) ,\n          .m_axi_arlen    ( cc_mi_arlen    ) ,\n          .m_axi_arsize   ( cc_mi_arsize   ) ,\n          .m_axi_arburst  ( cc_mi_arburst  ) ,\n          .m_axi_arlock   ( cc_mi_arlock   ) ,\n          .m_axi_arcache  ( cc_mi_arcache  ) ,\n          .m_axi_arprot   ( cc_mi_arprot   ) ,\n          .m_axi_arqos    ( cc_mi_arqos    ) ,\n          .m_axi_aruser   ( cc_mi_aruser   ) ,\n          .m_axi_arregion ( cc_mi_arregion ) ,\n          .m_axi_rid      ( cc_mi_rid      ) ,\n          .m_axi_rdata    ( cc_mi_rdata    ) ,\n          .m_axi_rresp    ( cc_mi_rresp    ) ,\n          .m_axi_rlast    ( cc_mi_rlast    ) ,\n          .m_axi_ruser    ( cc_mi_ruser    ) \n        );\n\n      end else begin : gen_sync_conv\n        \n        assign {fast_aclk, slow_aclk} = P_SI_LT_MI ? {m_axi_aclk, s_axi_aclk} : {s_axi_aclk, m_axi_aclk};\n    \n        // Sample cycle used to determine when to assert a signal on a fast clock\n        // to be flopped onto a slow clock.\n        axi_clock_converter_v2_1_14_axic_sample_cycle_ratio #(\n          .C_RATIO ( P_ACLK_RATIO )\n        )\n        axic_sample_cycle_inst (\n          .SLOW_ACLK          ( slow_aclk               ) ,\n          .FAST_ACLK          ( fast_aclk               ) ,\n          .SAMPLE_CYCLE_EARLY ( sample_cycle_early ) ,\n          .SAMPLE_CYCLE       ( sample_cycle       )\n        );\n    \n      ////////////////////////////////////////////////////////////////////////////////\n      // AXI write channels\n      ////////////////////////////////////////////////////////////////////////////////\n        if (C_AXI_SUPPORTS_WRITE) begin : gen_conv_write_ch\n    \n          // Write Address Port\n          assign s_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH]     = si_cc_awaddr   ;\n          assign s_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH]     = si_cc_awprot   ;\n          assign cc_mi_awaddr   = m_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH];\n          assign cc_mi_awprot   = m_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_aw_axi4\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen    ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock[0] ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH] = si_cc_awregion ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awregion = m_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_aw_axi3\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen[3:0] ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock   ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_aw_user\n            assign s_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH]  = si_cc_awuser;\n            assign cc_mi_awuser = m_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_14_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AW_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          aw_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_aw_mesg ) ,\n            .S_VALID   ( si_cc_awvalid   ) ,\n            .S_READY   ( si_cc_awready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_aw_mesg ) ,\n            .M_VALID   ( cc_mi_awvalid   ) ,\n            .M_READY   ( cc_mi_awready   )\n          );\n    \n          // Write Data Port\n          assign s_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH] = si_cc_wdata; \n          assign s_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH] = si_cc_wstrb; \n          assign cc_mi_wdata    = m_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH];\n          assign cc_mi_wstrb    = m_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_w_axi4\n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_w_axi3\n            assign s_w_mesg[C_WID_RIGHT+:C_WID_WIDTH]     = si_cc_wid; \n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wid      = m_w_mesg[C_WID_RIGHT+:C_WID_WIDTH];\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_w_user\n            assign s_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH]  = si_cc_wuser;\n            assign cc_mi_wuser = m_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_14_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH  ( C_W_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE           ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          w_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_w_mesg ) ,\n            .S_VALID   ( si_cc_wvalid   ) ,\n            .S_READY   ( si_cc_wready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_w_mesg ) ,\n            .M_VALID   ( cc_mi_wvalid   ) ,\n            .M_READY   ( cc_mi_wready   )\n          );\n    \n          // Write Response Port\n          assign m_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH] = cc_mi_bresp;\n          assign si_cc_bresp    = s_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_b_axi\n            assign m_b_mesg[C_BID_RIGHT+:C_BID_WIDTH]     = cc_mi_bid;\n            assign si_cc_bid      = s_b_mesg[C_BID_RIGHT+:C_BID_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_b_user\n            assign m_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH] = cc_mi_buser;\n            assign si_cc_buser  = s_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_14_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_B_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          b_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_b_mesg ) ,\n            .S_VALID   ( cc_mi_bvalid   ) ,\n            .S_READY   ( cc_mi_bready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_b_mesg ) ,\n            .M_VALID   ( si_cc_bvalid   ) ,\n            .M_READY   ( si_cc_bready   )\n          );\n    \n        end else begin : gen_tieoff_write_ch\n    \n          // Write address port\n          assign cc_mi_awid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_awaddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_awlen    = {8{1'b0}};\n          assign cc_mi_awsize   = {3{1'b0}};\n          assign cc_mi_awburst  = {2{1'b0}};\n          assign cc_mi_awlock   = {2{1'b0}};\n          assign cc_mi_awcache  = {4{1'b0}};\n          assign cc_mi_awprot   = {3{1'b0}};\n          assign cc_mi_awregion = {4{1'b0}};\n          assign cc_mi_awqos    = {4{1'b0}};\n          assign cc_mi_awuser   = {C_AXI_AWUSER_WIDTH{1'b0}};\n          assign cc_mi_awvalid  = 1'b0;\n          assign si_cc_awready  = 1'b0;\n    \n          // Write data port\n          assign cc_mi_wid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_wdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign cc_mi_wstrb    = {C_AXI_DATA_WIDTH/8{1'b0}};\n          assign cc_mi_wlast    = 1'b0;\n          assign cc_mi_wuser    = {C_AXI_WUSER_WIDTH{1'b0}};\n          assign cc_mi_wvalid   = 1'b0;\n          assign si_cc_wready   = 1'b0;\n    \n          // Write response port\n          assign si_cc_bid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_bresp    = {2{1'b0}};\n          assign si_cc_buser    = {C_AXI_BUSER_WIDTH{1'b0}};\n          assign si_cc_bvalid   = 1'b0;\n          assign cc_mi_bready   = 1'b0;\n        end\n    \n        ////////////////////////////////////////////////////////////////////////////////\n        // AXI read channels\n        ////////////////////////////////////////////////////////////////////////////////\n    \n        if (C_AXI_SUPPORTS_READ) begin : gen_conv_read_ch\n    \n          // Read Address Port\n          assign s_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH]     = si_cc_araddr   ;\n          assign s_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH]     = si_cc_arprot   ;\n          assign cc_mi_araddr   = m_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH];\n          assign cc_mi_arprot   = m_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_ar_axi4\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen    ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock[0] ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH] = si_cc_arregion ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arregion = m_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_ar_axi3\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen[3:0] ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock   ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_ar_user\n            assign s_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH]  = si_cc_aruser;\n            assign cc_mi_aruser = m_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_14_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AR_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          ar_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_ar_mesg ) ,\n            .S_VALID   ( si_cc_arvalid   ) ,\n            .S_READY   ( si_cc_arready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN  ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_ar_mesg ) ,\n            .M_VALID   ( cc_mi_arvalid   ) ,\n            .M_READY   ( cc_mi_arready   )\n          );\n    \n          // Read Data Port\n          assign m_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH] = cc_mi_rdata; \n          assign m_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH] = cc_mi_rresp; \n          assign si_cc_rdata    = s_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH];\n          assign si_cc_rresp    = s_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_r_axi\n            assign m_r_mesg[C_RID_RIGHT+:C_RID_WIDTH]     = cc_mi_rid;   \n            assign m_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH] = cc_mi_rlast;\n            assign si_cc_rid      = s_r_mesg[C_RID_RIGHT+:C_RID_WIDTH];\n            assign si_cc_rlast    = s_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_r_user\n            assign m_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH] = cc_mi_ruser;\n            assign si_cc_ruser  = s_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_14_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_R_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          r_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_r_mesg ) ,\n            .S_VALID   ( cc_mi_rvalid   ) ,\n            .S_READY   ( cc_mi_rready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_r_mesg ) ,\n            .M_VALID   ( si_cc_rvalid   ) ,\n            .M_READY   ( si_cc_rready   )\n          );\n    \n        end else begin : gen_tieoff_read_ch\n    \n          // Read Address Port\n          assign cc_mi_arid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_araddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_arlen    = {8{1'b0}};\n          assign cc_mi_arsize   = {3{1'b0}};\n          assign cc_mi_arburst  = {2{1'b0}};\n          assign cc_mi_arlock   = {2{1'b0}};\n          assign cc_mi_arcache  = {4{1'b0}};\n          assign cc_mi_arprot   = {3{1'b0}};\n          assign cc_mi_arregion = {4{1'b0}};\n          assign cc_mi_arqos    = {4{1'b0}};\n          assign cc_mi_aruser   = {C_AXI_ARUSER_WIDTH{1'b0}};\n          assign cc_mi_arvalid  = 1'b0;\n          assign si_cc_arready  = 1'b0;\n    \n          // Read data port\n          assign si_cc_rid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_rdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign si_cc_rresp    = {2{1'b0}};\n          assign si_cc_rlast    = 1'b0;\n          assign si_cc_ruser    = {C_AXI_RUSER_WIDTH{1'b0}};\n          assign si_cc_rvalid   = 1'b0;\n          assign cc_mi_rready   = 1'b0;\n        end\n      end\n    end\n\n  endgenerate\n\nendmodule\n\n\n\n", "num_lines": 2174}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1\n// IP Revision: 14\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_clock_converter_0 (\n  s_axi_aclk,\n  s_axi_aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awuser,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_aruser,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_aclk,\n  m_axi_aresetn,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awuser,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_aruser,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_CLK, FREQ_HZ 10000000, PHASE 0.000\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 SI_CLK CLK\" *)\ninput wire s_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 SI_RST RST\" *)\ninput wire s_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWUSER\" *)\ninput wire [18 : 0] s_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARUSER\" *)\ninput wire [18 : 0] s_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 19, ARUSER_WIDTH 19, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_CLK, FREQ_HZ 10000000, PHASE 0.000\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 MI_CLK CLK\" *)\ninput wire m_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 MI_RST RST\" *)\ninput wire m_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWUSER\" *)\noutput wire [18 : 0] m_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARUSER\" *)\noutput wire [18 : 0] m_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 19, ARUSER_WIDTH 19, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_clock_converter_v2_1_14_axi_clock_converter #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_S_AXI_ACLK_RATIO(1),\n    .C_M_AXI_ACLK_RATIO(2),\n    .C_AXI_IS_ACLK_ASYNC(1),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_SUPPORTS_USER_SIGNALS(1),\n    .C_AXI_AWUSER_WIDTH(19),\n    .C_AXI_ARUSER_WIDTH(19),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_AXI_SUPPORTS_WRITE(1),\n    .C_AXI_SUPPORTS_READ(1),\n    .C_SYNCHRONIZER_STAGE(2)\n  ) inst (\n    .s_axi_aclk(s_axi_aclk),\n    .s_axi_aresetn(s_axi_aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(s_axi_awuser),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(s_axi_aruser),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_aclk(m_axi_aclk),\n    .m_axi_aresetn(m_axi_aresetn),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(m_axi_awuser),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(m_axi_aruser),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 439}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "/*\n *******************************************************************************\n *\n * FIFO Generator - Verilog Behavioral Model\n *\n *******************************************************************************\n *\n * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.\n *\n * This file contains confidential and proprietary information\n * of Xilinx, Inc. and is protected under U.S. and\n * international copyright and other intellectual property\n * laws.\n *\n * DISCLAIMER\n * This disclaimer is not a license and does not grant any\n * rights to the materials distributed herewith. Except as\n * otherwise provided in a valid license issued to you by\n * Xilinx, and to the maximum extent permitted by applicable\n * law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n * (2) Xilinx shall not be liable (whether in contract or tort,\n * including negligence, or under any other theory of\n * liability) for any loss or damage of any kind or nature\n * related to, arising under or in connection with these\n * materials, including for any direct, or any indirect,\n * special, incidental, or consequential loss or damage\n * (including loss of data, profits, goodwill, or any type of\n * loss or damage suffered as a result of any action brought\n * by a third party) even if such damage or loss was\n * reasonably foreseeable or Xilinx had been advised of the\n * possibility of the same.\n *\n * CRITICAL APPLICATIONS\n * Xilinx products are not designed or intended to be fail-\n * safe, or for use in any application requiring fail-safe\n * performance, such as life-support or safety devices or\n * systems, Class III medical devices, nuclear facilities,\n * applications related to the deployment of airbags, or any\n * other applications that could lead to death, personal\n * injury, or severe property or environmental damage\n * (individually and collectively, \"Critical\n * Applications\"). Customer assumes the sole risk and\n * liability of any use of Xilinx products in Critical\n * Applications, subject only to applicable laws and\n * regulations governing limitations on product liability.\n *\n * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n * PART OF THIS FILE AT ALL TIMES.\n *\n *******************************************************************************\n *******************************************************************************\n *\n * Filename: fifo_generator_vlog_beh.v\n *\n * Author     : Xilinx\n *\n *******************************************************************************\n * Structure:\n * \n * fifo_generator_vlog_beh.v\n *    |\n *    +-fifo_generator_v13_2_1_bhv_ver_as\n *    |\n *    +-fifo_generator_v13_2_1_bhv_ver_ss\n *    |\n *    +-fifo_generator_v13_2_1_bhv_ver_preload0\n * \n *******************************************************************************\n * Description:\n *\n * The Verilog behavioral model for the FIFO Generator.\n *\n *   The behavioral model has three parts:\n *      - The behavioral model for independent clocks FIFOs (_as)\n *      - The behavioral model for common clock FIFOs (_ss)\n *      - The \"preload logic\" block which implements First-word Fall-through\n * \n *******************************************************************************\n * Description:\n *  The verilog behavioral model for the FIFO generator core.\n *\n *******************************************************************************\n */\n\n`timescale 1ps/1ps\n`ifndef TCQ\n `define TCQ 100\n`endif\n\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_vlog_beh\n  #(\n    //-----------------------------------------------------------------------\n    // Generic Declarations\n    //-----------------------------------------------------------------------\n    parameter C_COMMON_CLOCK                 = 0,\n    parameter C_COUNT_TYPE                   = 0,\n    parameter C_DATA_COUNT_WIDTH             = 2,\n    parameter C_DEFAULT_VALUE                = \"\",\n    parameter C_DIN_WIDTH                    = 8,\n    parameter C_DOUT_RST_VAL                 = \"\",\n    parameter C_DOUT_WIDTH                   = 8,\n    parameter C_ENABLE_RLOCS                 = 0,\n    parameter C_FAMILY                       = \"\",\n    parameter C_FULL_FLAGS_RST_VAL           = 1,\n    parameter C_HAS_ALMOST_EMPTY             = 0,\n    parameter C_HAS_ALMOST_FULL              = 0,\n    parameter C_HAS_BACKUP                   = 0,\n    parameter C_HAS_DATA_COUNT               = 0,\n    parameter C_HAS_INT_CLK                  = 0,\n    parameter C_HAS_MEMINIT_FILE             = 0,\n    parameter C_HAS_OVERFLOW                 = 0,\n    parameter C_HAS_RD_DATA_COUNT            = 0,\n    parameter C_HAS_RD_RST                   = 0,\n    parameter C_HAS_RST                      = 1,\n    parameter C_HAS_SRST                     = 0,\n    parameter C_HAS_UNDERFLOW                = 0,\n    parameter C_HAS_VALID                    = 0,\n    parameter C_HAS_WR_ACK                   = 0,\n    parameter C_HAS_WR_DATA_COUNT            = 0,\n    parameter C_HAS_WR_RST                   = 0,\n    parameter C_IMPLEMENTATION_TYPE          = 0,\n    parameter C_INIT_WR_PNTR_VAL             = 0,\n    parameter C_MEMORY_TYPE                  = 1,\n    parameter C_MIF_FILE_NAME                = \"\",\n    parameter C_OPTIMIZATION_MODE            = 0,\n    parameter C_OVERFLOW_LOW                 = 0,\n    parameter C_EN_SAFETY_CKT                = 0,\n    parameter C_PRELOAD_LATENCY              = 1,\n    parameter C_PRELOAD_REGS                 = 0,\n    parameter C_PRIM_FIFO_TYPE               = \"4kx4\",\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter C_PROG_EMPTY_TYPE              = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter C_PROG_FULL_TYPE               = 0,\n    parameter C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter C_RD_DEPTH                     = 256,\n    parameter C_RD_FREQ                      = 1,\n    parameter C_RD_PNTR_WIDTH                = 8,\n    parameter C_UNDERFLOW_LOW                = 0,\n    parameter C_USE_DOUT_RST                 = 0,\n    parameter C_USE_ECC                      = 0,\n    parameter C_USE_EMBEDDED_REG             = 0,\n    parameter C_USE_PIPELINE_REG             = 0,\n    parameter C_POWER_SAVING_MODE            = 0,\n    parameter C_USE_FIFO16_FLAGS             = 0,\n    parameter C_USE_FWFT_DATA_COUNT          = 0,\n    parameter C_VALID_LOW                    = 0,\n    parameter C_WR_ACK_LOW                   = 0,\n    parameter C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter C_WR_DEPTH                     = 256,\n    parameter C_WR_FREQ                      = 1,\n    parameter C_WR_PNTR_WIDTH                = 8,\n    parameter C_WR_RESPONSE_LATENCY          = 1,\n    parameter C_MSGON_VAL                    = 1,\n    parameter C_ENABLE_RST_SYNC              = 1,\n    parameter C_ERROR_INJECTION_TYPE         = 0,\n    parameter C_SYNCHRONIZER_STAGE           = 2,\n\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE               = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3\n    parameter C_AXI_TYPE                     = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3\n    parameter C_HAS_AXI_WR_CHANNEL           = 0,\n    parameter C_HAS_AXI_RD_CHANNEL           = 0,\n    parameter C_HAS_SLAVE_CE                 = 0,\n    parameter C_HAS_MASTER_CE                = 0,\n    parameter C_ADD_NGC_CONSTRAINT           = 0,\n    parameter C_USE_COMMON_UNDERFLOW         = 0,\n    parameter C_USE_COMMON_OVERFLOW          = 0,\n    parameter C_USE_DEFAULT_SETTINGS         = 0,\n\n    // AXI Full/Lite\n    parameter C_AXI_ID_WIDTH                 = 0,\n    parameter C_AXI_ADDR_WIDTH               = 0,\n    parameter C_AXI_DATA_WIDTH               = 0,\n    parameter C_AXI_LEN_WIDTH                = 8,\n    parameter C_AXI_LOCK_WIDTH               = 2,\n    parameter C_HAS_AXI_ID                   = 0,\n    parameter C_HAS_AXI_AWUSER               = 0,\n    parameter C_HAS_AXI_WUSER                = 0,\n    parameter C_HAS_AXI_BUSER                = 0,\n    parameter C_HAS_AXI_ARUSER               = 0,\n    parameter C_HAS_AXI_RUSER                = 0,\n    parameter C_AXI_ARUSER_WIDTH             = 0,\n    parameter C_AXI_AWUSER_WIDTH             = 0,\n    parameter C_AXI_WUSER_WIDTH              = 0,\n    parameter C_AXI_BUSER_WIDTH              = 0,\n    parameter C_AXI_RUSER_WIDTH              = 0,\n\n    // AXI Streaming\n    parameter C_HAS_AXIS_TDATA               = 0,\n    parameter C_HAS_AXIS_TID                 = 0,\n    parameter C_HAS_AXIS_TDEST               = 0,\n    parameter C_HAS_AXIS_TUSER               = 0,\n    parameter C_HAS_AXIS_TREADY              = 0,\n    parameter C_HAS_AXIS_TLAST               = 0,\n    parameter C_HAS_AXIS_TSTRB               = 0,\n    parameter C_HAS_AXIS_TKEEP               = 0,\n    parameter C_AXIS_TDATA_WIDTH             = 1,\n    parameter C_AXIS_TID_WIDTH               = 1,\n    parameter C_AXIS_TDEST_WIDTH             = 1,\n    parameter C_AXIS_TUSER_WIDTH             = 1,\n    parameter C_AXIS_TSTRB_WIDTH             = 1,\n    parameter C_AXIS_TKEEP_WIDTH             = 1,\n\n    // AXI Channel Type\n    // WACH --> Write Address Channel\n    // WDCH --> Write Data Channel\n    // WRCH --> Write Response Channel\n    // RACH --> Read Address Channel\n    // RDCH --> Read Data Channel\n    // AXIS --> AXI Streaming\n    parameter C_WACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic\n    parameter C_WDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_WRCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_AXIS_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n\n    // AXI Implementation Type\n    // 1 = Common Clock Block RAM FIFO\n    // 2 = Common Clock Distributed RAM FIFO\n    // 11 = Independent Clock Block RAM FIFO\n    // 12 = Independent Clock Distributed RAM FIFO\n    parameter C_IMPLEMENTATION_TYPE_WACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WRCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_AXIS     = 0,\n\n    // AXI FIFO Type\n    // 0 = Data FIFO\n    // 1 = Packet FIFO\n    // 2 = Low Latency Sync FIFO\n    // 3 = Low Latency Async FIFO\n    parameter C_APPLICATION_TYPE_WACH        = 0,\n    parameter C_APPLICATION_TYPE_WDCH        = 0,\n    parameter C_APPLICATION_TYPE_WRCH        = 0,\n    parameter C_APPLICATION_TYPE_RACH        = 0,\n    parameter C_APPLICATION_TYPE_RDCH        = 0,\n    parameter C_APPLICATION_TYPE_AXIS        = 0,\n\n    // AXI Built-in FIFO Primitive Type\n    // 512x36, 1kx18, 2kx9, 4kx4, etc\n    parameter C_PRIM_FIFO_TYPE_WACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WRCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_AXIS          = \"512x36\",\n\n    // Enable ECC\n    // 0 = ECC disabled\n    // 1 = ECC enabled\n    parameter C_USE_ECC_WACH                 = 0,\n    parameter C_USE_ECC_WDCH                 = 0,\n    parameter C_USE_ECC_WRCH                 = 0,\n    parameter C_USE_ECC_RACH                 = 0,\n    parameter C_USE_ECC_RDCH                 = 0,\n    parameter C_USE_ECC_AXIS                 = 0,\n\n    // ECC Error Injection Type\n    // 0 = No Error Injection\n    // 1 = Single Bit Error Injection\n    // 2 = Double Bit Error Injection\n    // 3 = Single Bit and Double Bit Error Injection\n    parameter C_ERROR_INJECTION_TYPE_WACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WRCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_AXIS    = 0,\n\n    // Input Data Width\n    // Accumulation of all AXI input signal's width\n    parameter C_DIN_WIDTH_WACH               = 1,\n    parameter C_DIN_WIDTH_WDCH               = 1,\n    parameter C_DIN_WIDTH_WRCH               = 1,\n    parameter C_DIN_WIDTH_RACH               = 1,\n    parameter C_DIN_WIDTH_RDCH               = 1,\n    parameter C_DIN_WIDTH_AXIS               = 1,\n\n    parameter C_WR_DEPTH_WACH                = 16,\n    parameter C_WR_DEPTH_WDCH                = 16,\n    parameter C_WR_DEPTH_WRCH                = 16,\n    parameter C_WR_DEPTH_RACH                = 16,\n    parameter C_WR_DEPTH_RDCH                = 16,\n    parameter C_WR_DEPTH_AXIS                = 16,\n\n    parameter C_WR_PNTR_WIDTH_WACH           = 4,\n    parameter C_WR_PNTR_WIDTH_WDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_WRCH           = 4,\n    parameter C_WR_PNTR_WIDTH_RACH           = 4,\n    parameter C_WR_PNTR_WIDTH_RDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_AXIS           = 4,\n\n    parameter C_HAS_DATA_COUNTS_WACH         = 0,\n    parameter C_HAS_DATA_COUNTS_WDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_WRCH         = 0,\n    parameter C_HAS_DATA_COUNTS_RACH         = 0,\n    parameter C_HAS_DATA_COUNTS_RDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_AXIS         = 0,\n\n    parameter C_HAS_PROG_FLAGS_WACH          = 0,\n    parameter C_HAS_PROG_FLAGS_WDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_WRCH          = 0,\n    parameter C_HAS_PROG_FLAGS_RACH          = 0,\n    parameter C_HAS_PROG_FLAGS_RDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_AXIS          = 0,\n\n    parameter C_PROG_FULL_TYPE_WACH          = 0,\n    parameter C_PROG_FULL_TYPE_WDCH          = 0,\n    parameter C_PROG_FULL_TYPE_WRCH          = 0,\n    parameter C_PROG_FULL_TYPE_RACH          = 0,\n    parameter C_PROG_FULL_TYPE_RDCH          = 0,\n    parameter C_PROG_FULL_TYPE_AXIS          = 0,\n\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS      = 0,\n\n    parameter C_PROG_EMPTY_TYPE_WACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WRCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_AXIS         = 0,\n\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS     = 0,\n\n    parameter C_REG_SLICE_MODE_WACH          = 0,\n    parameter C_REG_SLICE_MODE_WDCH          = 0,\n    parameter C_REG_SLICE_MODE_WRCH          = 0,\n    parameter C_REG_SLICE_MODE_RACH          = 0,\n    parameter C_REG_SLICE_MODE_RDCH          = 0,\n    parameter C_REG_SLICE_MODE_AXIS          = 0\n\n    )\n\n   (\n    //------------------------------------------------------------------------------\n    // Input and Output Declarations\n    //------------------------------------------------------------------------------\n\n    // Conventional FIFO Interface Signals\n    input                               backup,\n    input                               backup_marker,\n    input                               clk,\n    input                               rst,\n    input                               srst,\n    input                               wr_clk,\n    input                               wr_rst,\n    input                               rd_clk,\n    input                               rd_rst,\n    input [C_DIN_WIDTH-1:0]             din,\n    input                               wr_en,\n    input                               rd_en,\n    // Optional inputs\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_assert,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_negate,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_assert,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_negate,\n    input                               int_clk,\n    input                               injectdbiterr,\n    input                               injectsbiterr,\n    input                               sleep,\n\n    output [C_DOUT_WIDTH-1:0]           dout,\n    output                              full,\n    output                              almost_full,\n    output                              wr_ack,\n    output                              overflow,\n    output                              empty,\n    output                              almost_empty,\n    output                              valid,\n    output                              underflow,\n    output [C_DATA_COUNT_WIDTH-1:0]     data_count,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]  rd_data_count,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count,\n    output                              prog_full,\n    output                              prog_empty,\n    output                              sbiterr,\n    output                              dbiterr,\n    output                              wr_rst_busy,\n    output                              rd_rst_busy,\n\n\n    // AXI Global Signal\n    input                               m_aclk,\n    input                               s_aclk,\n    input                               s_aresetn,\n    input                               s_aclk_en,\n    input                               m_aclk_en,\n    \n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_awid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_awaddr,\n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_awlen,\n    input [3-1:0]                       s_axi_awsize,\n    input [2-1:0]                       s_axi_awburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_awlock,\n    input [4-1:0]                       s_axi_awcache,\n    input [3-1:0]                       s_axi_awprot,\n    input [4-1:0]                       s_axi_awqos,\n    input [4-1:0]                       s_axi_awregion,\n    input [C_AXI_AWUSER_WIDTH-1:0]      s_axi_awuser,\n    input                               s_axi_awvalid,\n    output                              s_axi_awready,\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_wid,\n    input [C_AXI_DATA_WIDTH-1:0]        s_axi_wdata,\n    input [C_AXI_DATA_WIDTH/8-1:0]      s_axi_wstrb,\n    input                               s_axi_wlast,\n    input [C_AXI_WUSER_WIDTH-1:0]       s_axi_wuser,\n    input                               s_axi_wvalid,\n    output                              s_axi_wready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_bid,\n    output [2-1:0]                      s_axi_bresp,\n    output [C_AXI_BUSER_WIDTH-1:0]      s_axi_buser,\n    output                              s_axi_bvalid,\n    input                               s_axi_bready,\n    \n    // AXI Full/Lite Master Write Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_awid,\n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_awlen,\n    output [3-1:0]                      m_axi_awsize,\n    output [2-1:0]                      m_axi_awburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_awlock,\n    output [4-1:0]                      m_axi_awcache,\n    output [3-1:0]                      m_axi_awprot,\n    output [4-1:0]                      m_axi_awqos,\n    output [4-1:0]                      m_axi_awregion,\n    output [C_AXI_AWUSER_WIDTH-1:0]     m_axi_awuser,\n    output                              m_axi_awvalid,\n    input                               m_axi_awready,\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_wid,\n    output [C_AXI_DATA_WIDTH-1:0]       m_axi_wdata,\n    output [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb,\n    output                              m_axi_wlast,\n    output [C_AXI_WUSER_WIDTH-1:0]      m_axi_wuser,\n    output                              m_axi_wvalid,\n    input                               m_axi_wready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_bid,\n    input [2-1:0]                       m_axi_bresp,\n    input [C_AXI_BUSER_WIDTH-1:0]       m_axi_buser,\n    input                               m_axi_bvalid,\n    output                              m_axi_bready,\n    \n    \n    // AXI Full/Lite Slave Read Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_arid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_araddr, \n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_arlen,\n    input [3-1:0]                       s_axi_arsize,\n    input [2-1:0]                       s_axi_arburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_arlock,\n    input [4-1:0]                       s_axi_arcache,\n    input [3-1:0]                       s_axi_arprot,\n    input [4-1:0]                       s_axi_arqos,\n    input [4-1:0]                       s_axi_arregion,\n    input [C_AXI_ARUSER_WIDTH-1:0]      s_axi_aruser,\n    input                               s_axi_arvalid,\n    output                              s_axi_arready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_rid,       \n    output [C_AXI_DATA_WIDTH-1:0]       s_axi_rdata, \n    output [2-1:0]                      s_axi_rresp,\n    output                              s_axi_rlast,\n    output [C_AXI_RUSER_WIDTH-1:0]      s_axi_ruser,\n    output                              s_axi_rvalid,\n    input                               s_axi_rready,\n    \n    \n    \n    // AXI Full/Lite Master Read Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_arid,        \n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,  \n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_arlen,\n    output [3-1:0]                      m_axi_arsize,\n    output [2-1:0]                      m_axi_arburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_arlock,\n    output [4-1:0]                      m_axi_arcache,\n    output [3-1:0]                      m_axi_arprot,\n    output [4-1:0]                      m_axi_arqos,\n    output [4-1:0]                      m_axi_arregion,\n    output [C_AXI_ARUSER_WIDTH-1:0]     m_axi_aruser,\n    output                              m_axi_arvalid,\n    input                               m_axi_arready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_rid,        \n    input [C_AXI_DATA_WIDTH-1:0]        m_axi_rdata,  \n    input [2-1:0]                       m_axi_rresp,\n    input                               m_axi_rlast,\n    input [C_AXI_RUSER_WIDTH-1:0]       m_axi_ruser,\n    input                               m_axi_rvalid,\n    output                              m_axi_rready,\n    \n    \n    // AXI Streaming Slave Signals (Write side)\n    input                               s_axis_tvalid,\n    output                              s_axis_tready,\n    input [C_AXIS_TDATA_WIDTH-1:0]      s_axis_tdata,\n    input [C_AXIS_TSTRB_WIDTH-1:0]      s_axis_tstrb,\n    input [C_AXIS_TKEEP_WIDTH-1:0]      s_axis_tkeep,\n    input                               s_axis_tlast,\n    input [C_AXIS_TID_WIDTH-1:0]        s_axis_tid,\n    input [C_AXIS_TDEST_WIDTH-1:0]      s_axis_tdest,\n    input [C_AXIS_TUSER_WIDTH-1:0]      s_axis_tuser,\n    \n    // AXI Streaming Master Signals (Read side)\n    output                              m_axis_tvalid,\n    input                               m_axis_tready,\n    output [C_AXIS_TDATA_WIDTH-1:0]     m_axis_tdata,\n    output [C_AXIS_TSTRB_WIDTH-1:0]     m_axis_tstrb,\n    output [C_AXIS_TKEEP_WIDTH-1:0]     m_axis_tkeep,\n    output                              m_axis_tlast,\n    output [C_AXIS_TID_WIDTH-1:0]       m_axis_tid,\n    output [C_AXIS_TDEST_WIDTH-1:0]     m_axis_tdest,\n    output [C_AXIS_TUSER_WIDTH-1:0]     m_axis_tuser,\n    \n           \n    \n    \n    // AXI Full/Lite Write Address Channel signals\n    input                               axi_aw_injectsbiterr,\n    input                               axi_aw_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_rd_data_count,\n    output                              axi_aw_sbiterr,\n    output                              axi_aw_dbiterr,\n    output                              axi_aw_overflow,\n    output                              axi_aw_underflow,\n    output                              axi_aw_prog_full,\n    output                              axi_aw_prog_empty,\n    \n    \n    // AXI Full/Lite Write Data Channel signals\n    input                               axi_w_injectsbiterr,\n    input                               axi_w_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_rd_data_count,\n    output                              axi_w_sbiterr,\n    output                              axi_w_dbiterr,\n    output                              axi_w_overflow,\n    output                              axi_w_underflow,\n    output                              axi_w_prog_full,\n    output                              axi_w_prog_empty,\n    \n    \n    // AXI Full/Lite Write Response Channel signals\n    input                               axi_b_injectsbiterr,\n    input                               axi_b_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_rd_data_count,\n    output                              axi_b_sbiterr,\n    output                              axi_b_dbiterr,\n    output                              axi_b_overflow,\n    output                              axi_b_underflow,\n    output                              axi_b_prog_full,\n    output                              axi_b_prog_empty,\n    \n    \n    \n    // AXI Full/Lite Read Address Channel signals\n    input                               axi_ar_injectsbiterr,\n    input                               axi_ar_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_rd_data_count,\n    output                              axi_ar_sbiterr,\n    output                              axi_ar_dbiterr,\n    output                              axi_ar_overflow,\n    output                              axi_ar_underflow,\n    output                              axi_ar_prog_full,\n    output                              axi_ar_prog_empty,\n\n    \n    // AXI Full/Lite Read Data Channel Signals\n    input                               axi_r_injectsbiterr,\n    input                               axi_r_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_rd_data_count,\n    output                              axi_r_sbiterr,\n    output                              axi_r_dbiterr,\n    output                              axi_r_overflow,\n    output                              axi_r_underflow,\n    output                              axi_r_prog_full,\n    output                              axi_r_prog_empty,\n\n    \n    // AXI Streaming FIFO Related Signals\n    input                               axis_injectsbiterr,\n    input                               axis_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_wr_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_rd_data_count,\n    output                              axis_sbiterr,\n    output                              axis_dbiterr,\n    output                              axis_overflow,\n    output                              axis_underflow,\n    output                              axis_prog_full,\n    output                              axis_prog_empty\n\n    );\n\n    wire                              BACKUP;\n    wire                              BACKUP_MARKER;\n    wire                              CLK;\n    wire                              RST;\n    wire                              SRST;\n    wire                              WR_CLK;\n    wire                              WR_RST;\n    wire                              RD_CLK;\n    wire                              RD_RST;\n    wire [C_DIN_WIDTH-1:0]            DIN;\n    wire                              WR_EN;\n    wire                              RD_EN;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_ASSERT;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_NEGATE;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_ASSERT;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_NEGATE;\n    wire                              INT_CLK;\n    wire                              INJECTDBITERR;\n    wire                              INJECTSBITERR;\n    wire                              SLEEP;\n    wire [C_DOUT_WIDTH-1:0]           DOUT;\n    wire                              FULL;\n    wire                              ALMOST_FULL;\n    wire                              WR_ACK;\n    wire                              OVERFLOW;\n    wire                              EMPTY;\n    wire                              ALMOST_EMPTY;\n    wire                              VALID;\n    wire                              UNDERFLOW;\n    wire [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT;\n    wire [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT;\n    wire                              PROG_FULL;\n    wire                              PROG_EMPTY;\n    wire                              SBITERR;\n    wire                              DBITERR;\n    wire                              WR_RST_BUSY;\n    wire                              RD_RST_BUSY;\n    wire                              M_ACLK;\n    wire                              S_ACLK;\n    wire                              S_ARESETN;\n    wire                              S_ACLK_EN;\n    wire                              M_ACLK_EN;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_AWLEN;\n    wire [3-1:0]                      S_AXI_AWSIZE;\n    wire [2-1:0]                      S_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_AWLOCK;\n    wire [4-1:0]                      S_AXI_AWCACHE;\n    wire [3-1:0]                      S_AXI_AWPROT;\n    wire [4-1:0]                      S_AXI_AWQOS;\n    wire [4-1:0]                      S_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     S_AXI_AWUSER;\n    wire                              S_AXI_AWVALID;\n    wire                              S_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     S_AXI_WSTRB;\n    wire                              S_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      S_AXI_WUSER;\n    wire                              S_AXI_WVALID;\n    wire                              S_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_BID;\n    wire [2-1:0]                      S_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      S_AXI_BUSER;\n    wire                              S_AXI_BVALID;\n    wire                              S_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_AWLEN;\n    wire [3-1:0]                      M_AXI_AWSIZE;\n    wire [2-1:0]                      M_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_AWLOCK;\n    wire [4-1:0]                      M_AXI_AWCACHE;\n    wire [3-1:0]                      M_AXI_AWPROT;\n    wire [4-1:0]                      M_AXI_AWQOS;\n    wire [4-1:0]                      M_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     M_AXI_AWUSER;\n    wire                              M_AXI_AWVALID;\n    wire                              M_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     M_AXI_WSTRB;\n    wire                              M_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      M_AXI_WUSER;\n    wire                              M_AXI_WVALID;\n    wire                              M_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_BID;\n    wire [2-1:0]                      M_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      M_AXI_BUSER;\n    wire                              M_AXI_BVALID;\n    wire                              M_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_ARID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_ARADDR; \n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_ARLEN;\n    wire [3-1:0]                      S_AXI_ARSIZE;\n    wire [2-1:0]                      S_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_ARLOCK;\n    wire [4-1:0]                      S_AXI_ARCACHE;\n    wire [3-1:0]                      S_AXI_ARPROT;\n    wire [4-1:0]                      S_AXI_ARQOS;\n    wire [4-1:0]                      S_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     S_AXI_ARUSER;\n    wire                              S_AXI_ARVALID;\n    wire                              S_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_RID;       \n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_RDATA; \n    wire [2-1:0]                      S_AXI_RRESP;\n    wire                              S_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      S_AXI_RUSER;\n    wire                              S_AXI_RVALID;\n    wire                              S_AXI_RREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_ARID;        \n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_ARADDR;  \n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_ARLEN;\n    wire [3-1:0]                      M_AXI_ARSIZE;\n    wire [2-1:0]                      M_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_ARLOCK;\n    wire [4-1:0]                      M_AXI_ARCACHE;\n    wire [3-1:0]                      M_AXI_ARPROT;\n    wire [4-1:0]                      M_AXI_ARQOS;\n    wire [4-1:0]                      M_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     M_AXI_ARUSER;\n    wire                              M_AXI_ARVALID;\n    wire                              M_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_RID;        \n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_RDATA;  \n    wire [2-1:0]                      M_AXI_RRESP;\n    wire                              M_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      M_AXI_RUSER;\n    wire                              M_AXI_RVALID;\n    wire                              M_AXI_RREADY;\n    wire                              S_AXIS_TVALID;\n    wire                              S_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     S_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     S_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     S_AXIS_TKEEP;\n    wire                              S_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       S_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     S_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     S_AXIS_TUSER;\n    wire                              M_AXIS_TVALID;\n    wire                              M_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     M_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     M_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     M_AXIS_TKEEP;\n    wire                              M_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       M_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     M_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     M_AXIS_TUSER;\n    wire                              AXI_AW_INJECTSBITERR;\n    wire                              AXI_AW_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_RD_DATA_COUNT;\n    wire                              AXI_AW_SBITERR;\n    wire                              AXI_AW_DBITERR;\n    wire                              AXI_AW_OVERFLOW;\n    wire                              AXI_AW_UNDERFLOW;\n    wire                              AXI_AW_PROG_FULL;\n    wire                              AXI_AW_PROG_EMPTY;\n    wire                              AXI_W_INJECTSBITERR;\n    wire                              AXI_W_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_RD_DATA_COUNT;\n    wire                              AXI_W_SBITERR;\n    wire                              AXI_W_DBITERR;\n    wire                              AXI_W_OVERFLOW;\n    wire                              AXI_W_UNDERFLOW;\n    wire                              AXI_W_PROG_FULL;\n    wire                              AXI_W_PROG_EMPTY;\n    wire                              AXI_B_INJECTSBITERR;\n    wire                              AXI_B_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_RD_DATA_COUNT;\n    wire                              AXI_B_SBITERR;\n    wire                              AXI_B_DBITERR;\n    wire                              AXI_B_OVERFLOW;\n    wire                              AXI_B_UNDERFLOW;\n    wire                              AXI_B_PROG_FULL;\n    wire                              AXI_B_PROG_EMPTY;\n    wire                              AXI_AR_INJECTSBITERR;\n    wire                              AXI_AR_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_RD_DATA_COUNT;\n    wire                              AXI_AR_SBITERR;\n    wire                              AXI_AR_DBITERR;\n    wire                              AXI_AR_OVERFLOW;\n    wire                              AXI_AR_UNDERFLOW;\n    wire                              AXI_AR_PROG_FULL;\n    wire                              AXI_AR_PROG_EMPTY;\n    wire                              AXI_R_INJECTSBITERR;\n    wire                              AXI_R_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_RD_DATA_COUNT;\n    wire                              AXI_R_SBITERR;\n    wire                              AXI_R_DBITERR;\n    wire                              AXI_R_OVERFLOW;\n    wire                              AXI_R_UNDERFLOW;\n    wire                              AXI_R_PROG_FULL;\n    wire                              AXI_R_PROG_EMPTY;\n    wire                              AXIS_INJECTSBITERR;\n    wire                              AXIS_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_RD_DATA_COUNT;\n    wire                              AXIS_SBITERR;\n    wire                              AXIS_DBITERR;\n    wire                              AXIS_OVERFLOW;\n    wire                              AXIS_UNDERFLOW;\n    wire                              AXIS_PROG_FULL;\n    wire                              AXIS_PROG_EMPTY;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count_in;\n    wire                              wr_rst_int;\n    wire                              rd_rst_int;\n    wire                              wr_rst_busy_o;\n    wire                              wr_rst_busy_ntve;\n    wire                              wr_rst_busy_axis;\n    wire                              wr_rst_busy_wach;\n    wire                              wr_rst_busy_wdch;\n    wire                              wr_rst_busy_wrch;\n    wire                              wr_rst_busy_rach;\n    wire                              wr_rst_busy_rdch;\n\n\n\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n\n\n\n    // Conventional FIFO Interface Signals\n    assign BACKUP                 = backup;\n    assign BACKUP_MARKER          = backup_marker;\n    assign CLK                    = clk;\n    assign RST                    = rst;\n    assign SRST                   = srst;\n    assign WR_CLK                 = wr_clk;\n    assign WR_RST                 = wr_rst;\n    assign RD_CLK                 = rd_clk;\n    assign RD_RST                 = rd_rst;\n    assign WR_EN                  = wr_en;\n    assign RD_EN                  = rd_en;\n    assign INT_CLK                = int_clk;\n    assign INJECTDBITERR          = injectdbiterr;\n    assign INJECTSBITERR          = injectsbiterr;\n    assign SLEEP                  = sleep;\n    assign full                   = FULL;\n    assign almost_full            = ALMOST_FULL;\n    assign wr_ack                 = WR_ACK;\n    assign overflow               = OVERFLOW;\n    assign empty                  = EMPTY;\n    assign almost_empty           = ALMOST_EMPTY;\n    assign valid                  = VALID;\n    assign underflow              = UNDERFLOW;\n    assign prog_full              = PROG_FULL;\n    assign prog_empty             = PROG_EMPTY;\n    assign sbiterr                = SBITERR;\n    assign dbiterr                = DBITERR;\n//    assign wr_rst_busy            = WR_RST_BUSY | wr_rst_busy_o;\n    assign wr_rst_busy            = wr_rst_busy_o;\n    assign rd_rst_busy            = RD_RST_BUSY;\n    assign M_ACLK                 = m_aclk;\n    assign S_ACLK                 = s_aclk;\n    assign S_ARESETN              = s_aresetn;\n    assign S_ACLK_EN              = s_aclk_en;\n    assign M_ACLK_EN              = m_aclk_en;\n    assign S_AXI_AWVALID          = s_axi_awvalid;\n    assign s_axi_awready          = S_AXI_AWREADY;\n    assign S_AXI_WLAST            = s_axi_wlast;\n    assign S_AXI_WVALID           = s_axi_wvalid;\n    assign s_axi_wready           = S_AXI_WREADY;\n    assign s_axi_bvalid           = S_AXI_BVALID;\n    assign S_AXI_BREADY           = s_axi_bready;\n    assign m_axi_awvalid          = M_AXI_AWVALID;\n    assign M_AXI_AWREADY          = m_axi_awready;\n    assign m_axi_wlast            = M_AXI_WLAST;\n    assign m_axi_wvalid           = M_AXI_WVALID;\n    assign M_AXI_WREADY           = m_axi_wready;\n    assign M_AXI_BVALID           = m_axi_bvalid;\n    assign m_axi_bready           = M_AXI_BREADY;\n    assign S_AXI_ARVALID          = s_axi_arvalid;\n    assign s_axi_arready          = S_AXI_ARREADY;\n    assign s_axi_rlast            = S_AXI_RLAST;\n    assign s_axi_rvalid           = S_AXI_RVALID;\n    assign S_AXI_RREADY           = s_axi_rready;\n    assign m_axi_arvalid          = M_AXI_ARVALID;\n    assign M_AXI_ARREADY          = m_axi_arready;\n    assign M_AXI_RLAST            = m_axi_rlast;\n    assign M_AXI_RVALID           = m_axi_rvalid;\n    assign m_axi_rready           = M_AXI_RREADY;\n    assign S_AXIS_TVALID          = s_axis_tvalid;\n    assign s_axis_tready          = S_AXIS_TREADY;\n    assign S_AXIS_TLAST           = s_axis_tlast;\n    assign m_axis_tvalid          = M_AXIS_TVALID;\n    assign M_AXIS_TREADY          = m_axis_tready;\n    assign m_axis_tlast           = M_AXIS_TLAST;\n    assign AXI_AW_INJECTSBITERR   = axi_aw_injectsbiterr;\n    assign AXI_AW_INJECTDBITERR   = axi_aw_injectdbiterr;\n    assign axi_aw_sbiterr         = AXI_AW_SBITERR;\n    assign axi_aw_dbiterr         = AXI_AW_DBITERR;\n    assign axi_aw_overflow        = AXI_AW_OVERFLOW;\n    assign axi_aw_underflow       = AXI_AW_UNDERFLOW;\n    assign axi_aw_prog_full       = AXI_AW_PROG_FULL;\n    assign axi_aw_prog_empty      = AXI_AW_PROG_EMPTY;\n    assign AXI_W_INJECTSBITERR    = axi_w_injectsbiterr;\n    assign AXI_W_INJECTDBITERR    = axi_w_injectdbiterr;\n    assign axi_w_sbiterr          = AXI_W_SBITERR;\n    assign axi_w_dbiterr          = AXI_W_DBITERR;\n    assign axi_w_overflow         = AXI_W_OVERFLOW;\n    assign axi_w_underflow        = AXI_W_UNDERFLOW;\n    assign axi_w_prog_full        = AXI_W_PROG_FULL;\n    assign axi_w_prog_empty       = AXI_W_PROG_EMPTY;\n    assign AXI_B_INJECTSBITERR    = axi_b_injectsbiterr;\n    assign AXI_B_INJECTDBITERR    = axi_b_injectdbiterr;\n    assign axi_b_sbiterr          = AXI_B_SBITERR;\n    assign axi_b_dbiterr          = AXI_B_DBITERR;\n    assign axi_b_overflow         = AXI_B_OVERFLOW;\n    assign axi_b_underflow        = AXI_B_UNDERFLOW;\n    assign axi_b_prog_full        = AXI_B_PROG_FULL;\n    assign axi_b_prog_empty       = AXI_B_PROG_EMPTY;\n    assign AXI_AR_INJECTSBITERR   = axi_ar_injectsbiterr;\n    assign AXI_AR_INJECTDBITERR   = axi_ar_injectdbiterr;\n    assign axi_ar_sbiterr         = AXI_AR_SBITERR;\n    assign axi_ar_dbiterr         = AXI_AR_DBITERR;\n    assign axi_ar_overflow        = AXI_AR_OVERFLOW;\n    assign axi_ar_underflow       = AXI_AR_UNDERFLOW;\n    assign axi_ar_prog_full       = AXI_AR_PROG_FULL;\n    assign axi_ar_prog_empty      = AXI_AR_PROG_EMPTY;\n    assign AXI_R_INJECTSBITERR    = axi_r_injectsbiterr;\n    assign AXI_R_INJECTDBITERR    = axi_r_injectdbiterr;\n    assign axi_r_sbiterr          = AXI_R_SBITERR;\n    assign axi_r_dbiterr          = AXI_R_DBITERR;\n    assign axi_r_overflow         = AXI_R_OVERFLOW;\n    assign axi_r_underflow        = AXI_R_UNDERFLOW;\n    assign axi_r_prog_full        = AXI_R_PROG_FULL;\n    assign axi_r_prog_empty       = AXI_R_PROG_EMPTY;\n    assign AXIS_INJECTSBITERR     = axis_injectsbiterr;\n    assign AXIS_INJECTDBITERR     = axis_injectdbiterr;\n    assign axis_sbiterr           = AXIS_SBITERR;\n    assign axis_dbiterr           = AXIS_DBITERR;\n    assign axis_overflow          = AXIS_OVERFLOW;\n    assign axis_underflow         = AXIS_UNDERFLOW;\n    assign axis_prog_full         = AXIS_PROG_FULL;\n    assign axis_prog_empty        = AXIS_PROG_EMPTY;\n\n\n    assign DIN                       = din;\n    assign PROG_EMPTY_THRESH         = prog_empty_thresh;\n    assign PROG_EMPTY_THRESH_ASSERT  = prog_empty_thresh_assert;\n    assign PROG_EMPTY_THRESH_NEGATE  = prog_empty_thresh_negate;\n    assign PROG_FULL_THRESH          = prog_full_thresh;\n    assign PROG_FULL_THRESH_ASSERT   = prog_full_thresh_assert;\n    assign PROG_FULL_THRESH_NEGATE   = prog_full_thresh_negate;\n    assign dout                      = DOUT;\n    assign data_count                = DATA_COUNT;\n    assign rd_data_count             = RD_DATA_COUNT;\n    assign wr_data_count             = WR_DATA_COUNT;\n    assign S_AXI_AWID                = s_axi_awid;\n    assign S_AXI_AWADDR              = s_axi_awaddr;\n    assign S_AXI_AWLEN               = s_axi_awlen;\n    assign S_AXI_AWSIZE              = s_axi_awsize;\n    assign S_AXI_AWBURST             = s_axi_awburst;\n    assign S_AXI_AWLOCK              = s_axi_awlock;\n    assign S_AXI_AWCACHE             = s_axi_awcache;\n    assign S_AXI_AWPROT              = s_axi_awprot;\n    assign S_AXI_AWQOS               = s_axi_awqos;\n    assign S_AXI_AWREGION            = s_axi_awregion;\n    assign S_AXI_AWUSER              = s_axi_awuser;\n    assign S_AXI_WID                 = s_axi_wid;\n    assign S_AXI_WDATA               = s_axi_wdata;\n    assign S_AXI_WSTRB               = s_axi_wstrb;\n    assign S_AXI_WUSER               = s_axi_wuser;\n    assign s_axi_bid                 = S_AXI_BID;\n    assign s_axi_bresp               = S_AXI_BRESP;\n    assign s_axi_buser               = S_AXI_BUSER;\n    assign m_axi_awid                = M_AXI_AWID;\n    assign m_axi_awaddr              = M_AXI_AWADDR;\n    assign m_axi_awlen               = M_AXI_AWLEN;\n    assign m_axi_awsize              = M_AXI_AWSIZE;\n    assign m_axi_awburst             = M_AXI_AWBURST;\n    assign m_axi_awlock              = M_AXI_AWLOCK;\n    assign m_axi_awcache             = M_AXI_AWCACHE;\n    assign m_axi_awprot              = M_AXI_AWPROT;\n    assign m_axi_awqos               = M_AXI_AWQOS;\n    assign m_axi_awregion            = M_AXI_AWREGION;\n    assign m_axi_awuser              = M_AXI_AWUSER;\n    assign m_axi_wid                 = M_AXI_WID;\n    assign m_axi_wdata               = M_AXI_WDATA;\n    assign m_axi_wstrb               = M_AXI_WSTRB;\n    assign m_axi_wuser               = M_AXI_WUSER;\n    assign M_AXI_BID                 = m_axi_bid;\n    assign M_AXI_BRESP               = m_axi_bresp;\n    assign M_AXI_BUSER               = m_axi_buser;\n    assign S_AXI_ARID                = s_axi_arid;\n    assign S_AXI_ARADDR              = s_axi_araddr; \n    assign S_AXI_ARLEN               = s_axi_arlen;\n    assign S_AXI_ARSIZE              = s_axi_arsize;\n    assign S_AXI_ARBURST             = s_axi_arburst;\n    assign S_AXI_ARLOCK              = s_axi_arlock;\n    assign S_AXI_ARCACHE             = s_axi_arcache;\n    assign S_AXI_ARPROT              = s_axi_arprot;\n    assign S_AXI_ARQOS               = s_axi_arqos;\n    assign S_AXI_ARREGION            = s_axi_arregion;\n    assign S_AXI_ARUSER              = s_axi_aruser;\n    assign s_axi_rid                 = S_AXI_RID;\n    assign s_axi_rdata               = S_AXI_RDATA;\n    assign s_axi_rresp               = S_AXI_RRESP;\n    assign s_axi_ruser               = S_AXI_RUSER;\n    assign m_axi_arid                = M_AXI_ARID;        \n    assign m_axi_araddr              = M_AXI_ARADDR;  \n    assign m_axi_arlen               = M_AXI_ARLEN;\n    assign m_axi_arsize              = M_AXI_ARSIZE;\n    assign m_axi_arburst             = M_AXI_ARBURST;\n    assign m_axi_arlock              = M_AXI_ARLOCK;\n    assign m_axi_arcache             = M_AXI_ARCACHE;\n    assign m_axi_arprot              = M_AXI_ARPROT;\n    assign m_axi_arqos               = M_AXI_ARQOS;\n    assign m_axi_arregion            = M_AXI_ARREGION;\n    assign m_axi_aruser              = M_AXI_ARUSER;\n    assign M_AXI_RID                 = m_axi_rid;        \n    assign M_AXI_RDATA               = m_axi_rdata;  \n    assign M_AXI_RRESP               = m_axi_rresp;\n    assign M_AXI_RUSER               = m_axi_ruser;\n    assign S_AXIS_TDATA              = s_axis_tdata;\n    assign S_AXIS_TSTRB              = s_axis_tstrb;\n    assign S_AXIS_TKEEP              = s_axis_tkeep;\n    assign S_AXIS_TID                = s_axis_tid;\n    assign S_AXIS_TDEST              = s_axis_tdest;\n    assign S_AXIS_TUSER              = s_axis_tuser;\n    assign m_axis_tdata              = M_AXIS_TDATA;\n    assign m_axis_tstrb              = M_AXIS_TSTRB;\n    assign m_axis_tkeep              = M_AXIS_TKEEP;\n    assign m_axis_tid                = M_AXIS_TID;\n    assign m_axis_tdest              = M_AXIS_TDEST;\n    assign m_axis_tuser              = M_AXIS_TUSER;\n    assign AXI_AW_PROG_FULL_THRESH   = axi_aw_prog_full_thresh;\n    assign AXI_AW_PROG_EMPTY_THRESH  = axi_aw_prog_empty_thresh;\n    assign axi_aw_data_count         = AXI_AW_DATA_COUNT;\n    assign axi_aw_wr_data_count      = AXI_AW_WR_DATA_COUNT;\n    assign axi_aw_rd_data_count      = AXI_AW_RD_DATA_COUNT;\n    assign AXI_W_PROG_FULL_THRESH    = axi_w_prog_full_thresh;\n    assign AXI_W_PROG_EMPTY_THRESH   = axi_w_prog_empty_thresh;\n    assign axi_w_data_count          = AXI_W_DATA_COUNT;\n    assign axi_w_wr_data_count       = AXI_W_WR_DATA_COUNT;\n    assign axi_w_rd_data_count       = AXI_W_RD_DATA_COUNT;\n    assign AXI_B_PROG_FULL_THRESH    = axi_b_prog_full_thresh;\n    assign AXI_B_PROG_EMPTY_THRESH   = axi_b_prog_empty_thresh;\n    assign axi_b_data_count          = AXI_B_DATA_COUNT;\n    assign axi_b_wr_data_count       = AXI_B_WR_DATA_COUNT;\n    assign axi_b_rd_data_count       = AXI_B_RD_DATA_COUNT;\n    assign AXI_AR_PROG_FULL_THRESH   = axi_ar_prog_full_thresh;\n    assign AXI_AR_PROG_EMPTY_THRESH  = axi_ar_prog_empty_thresh;\n    assign axi_ar_data_count         = AXI_AR_DATA_COUNT;\n    assign axi_ar_wr_data_count      = AXI_AR_WR_DATA_COUNT;\n    assign axi_ar_rd_data_count      = AXI_AR_RD_DATA_COUNT;\n    assign AXI_R_PROG_FULL_THRESH    = axi_r_prog_full_thresh;\n    assign AXI_R_PROG_EMPTY_THRESH   = axi_r_prog_empty_thresh;\n    assign axi_r_data_count          = AXI_R_DATA_COUNT;\n    assign axi_r_wr_data_count       = AXI_R_WR_DATA_COUNT;\n    assign axi_r_rd_data_count       = AXI_R_RD_DATA_COUNT;\n    assign AXIS_PROG_FULL_THRESH     = axis_prog_full_thresh;\n    assign AXIS_PROG_EMPTY_THRESH    = axis_prog_empty_thresh;\n    assign axis_data_count           = AXIS_DATA_COUNT;\n    assign axis_wr_data_count        = AXIS_WR_DATA_COUNT;\n    assign axis_rd_data_count        = AXIS_RD_DATA_COUNT;\n\n\n  generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_COMMON_CLOCK \t\t(C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DATA_COUNT_WIDTH\t\t(C_DATA_COUNT_WIDTH),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH),\n        .C_DOUT_RST_VAL\t\t\t(C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),\n        .C_DOUT_WIDTH\t\t\t(C_DOUT_WIDTH),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n        .C_HAS_ALMOST_EMPTY\t\t(C_HAS_ALMOST_EMPTY),\n        .C_HAS_ALMOST_FULL\t\t(C_HAS_ALMOST_FULL),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_DATA_COUNT\t\t(C_HAS_DATA_COUNT),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_HAS_RD_DATA_COUNT\t\t(C_HAS_RD_DATA_COUNT),\n        .C_HAS_RD_RST\t\t\t(C_HAS_RD_RST),\n        .C_HAS_RST\t\t\t(C_HAS_RST),\n        .C_HAS_SRST\t\t\t(C_HAS_SRST),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_HAS_VALID\t\t\t(C_HAS_VALID),\n        .C_HAS_WR_ACK\t\t\t(C_HAS_WR_ACK),\n        .C_HAS_WR_DATA_COUNT\t\t(C_HAS_WR_DATA_COUNT),\n        .C_HAS_WR_RST\t\t\t(C_HAS_WR_RST),\n        .C_IMPLEMENTATION_TYPE\t\t(C_IMPLEMENTATION_TYPE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_MEMORY_TYPE\t\t\t(C_MEMORY_TYPE),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n        .C_PRELOAD_LATENCY\t\t(C_PRELOAD_LATENCY),\n        .C_PRELOAD_REGS\t\t\t(C_PRELOAD_REGS),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL),\n        .C_PROG_EMPTY_THRESH_NEGATE_VAL\t(C_PROG_EMPTY_THRESH_NEGATE_VAL),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL),\n        .C_PROG_FULL_THRESH_NEGATE_VAL\t(C_PROG_FULL_THRESH_NEGATE_VAL),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_RD_DATA_COUNT_WIDTH),\n        .C_RD_DEPTH\t\t\t(C_RD_DEPTH),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_RD_PNTR_WIDTH\t\t(C_RD_PNTR_WIDTH),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n        .C_USE_ECC                      (C_USE_ECC),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_EN_SAFETY_CKT\t\t(C_EN_SAFETY_CKT),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_USE_FWFT_DATA_COUNT\t\t(C_USE_FWFT_DATA_COUNT),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_DATA_COUNT_WIDTH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (C_ENABLE_RST_SYNC),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE),\n        .C_AXI_TYPE                     (C_AXI_TYPE),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE)\n      )\n    fifo_generator_v13_2_1_conv_dut\n      (\n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .CLK                      (CLK),\n        .RST                      (RST),\n        .SRST                     (SRST),\n        .WR_CLK                   (WR_CLK),\n        .WR_RST                   (WR_RST),\n        .RD_CLK                   (RD_CLK),\n        .RD_RST                   (RD_RST),\n        .DIN                      (DIN),\n        .WR_EN                    (WR_EN),\n        .RD_EN                    (RD_EN),\n        .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),\n        .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),\n        .PROG_FULL_THRESH         (PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),\n        .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),\n        .INT_CLK                  (INT_CLK),\n        .INJECTDBITERR            (INJECTDBITERR), \n        .INJECTSBITERR            (INJECTSBITERR),\n  \n        .DOUT                     (DOUT),\n        .FULL                     (FULL),\n        .ALMOST_FULL              (ALMOST_FULL),\n        .WR_ACK                   (WR_ACK),\n        .OVERFLOW                 (OVERFLOW),\n        .EMPTY                    (EMPTY),\n        .ALMOST_EMPTY             (ALMOST_EMPTY),\n        .VALID                    (VALID),\n        .UNDERFLOW                (UNDERFLOW),\n        .DATA_COUNT               (DATA_COUNT),\n        .RD_DATA_COUNT            (RD_DATA_COUNT),\n        .WR_DATA_COUNT            (wr_data_count_in),\n        .PROG_FULL                (PROG_FULL),\n        .PROG_EMPTY               (PROG_EMPTY),\n        .SBITERR                  (SBITERR),\n        .DBITERR                  (DBITERR),\n        .wr_rst_busy_o            (wr_rst_busy_o),\n        .wr_rst_busy              (wr_rst_busy_i),\n        .rd_rst_busy              (rd_rst_busy),\n        .wr_rst_i_out             (wr_rst_int),\n        .rd_rst_i_out             (rd_rst_int)\n       );\n  end endgenerate\n\n\n\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n  localparam C_AXI_SIZE_WIDTH   = 3;\n  localparam C_AXI_BURST_WIDTH  = 2;\n  localparam C_AXI_CACHE_WIDTH  = 4;\n  localparam C_AXI_PROT_WIDTH   = 3;\n  localparam C_AXI_QOS_WIDTH    = 4;\n  localparam C_AXI_REGION_WIDTH = 4;\n  localparam C_AXI_BRESP_WIDTH  = 2;\n  localparam C_AXI_RRESP_WIDTH  = 2;\n\n  localparam IS_AXI_STREAMING  = C_INTERFACE_TYPE == 1 ? 1 : 0;\n  localparam TDATA_OFFSET      = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;\n  localparam TSTRB_OFFSET      = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;\n  localparam TKEEP_OFFSET      = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;\n  localparam TID_OFFSET        = C_HAS_AXIS_TID   == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;\n  localparam TDEST_OFFSET      = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;\n  localparam TUSER_OFFSET      = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;\n  localparam LOG_DEPTH_AXIS    = find_log2(C_WR_DEPTH_AXIS); \n  localparam LOG_WR_DEPTH      = find_log2(C_WR_DEPTH); \n\n\n  function [LOG_DEPTH_AXIS-1:0] bin2gray;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      begin\n         bin2gray = x ^ (x>>1);\n      end\n   endfunction\n\n  function [LOG_DEPTH_AXIS-1:0] gray2bin;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      integer                i;\n      begin\n         gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];\n         for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin\n            gray2bin[i] =  gray2bin[i+1] ^ x[i];\n         end\n      end\n   endfunction\n\nwire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;\nwire  [LOG_WR_DEPTH-1 : 0]  w_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;\nreg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;\nwire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;\nwire [LOG_WR_DEPTH : 0] r_inv_pad;\nwire [LOG_WR_DEPTH-1 : 0] d_cnt;\nreg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;\nreg adj_w_cnt_rd_pad_0 = 0;\nreg r_inv_pad_0 = 0;\n\n\n   genvar l;\n\n   generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage\n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (LOG_WR_DEPTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_int), \n         .CLK      (RD_CLK), \n         .DIN      (w_q[l-1]), \n         .DOUT     (w_q[l])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter\n    assign wr_eop_ad = WR_EN & !(FULL);\n    assign rd_eop_ad = RD_EN & !(EMPTY);\n\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt    <= 1'b0;\n      else if (wr_eop_ad)\n        w_cnt    <= w_cnt + 1;\n    end\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt_gc    <= 1'b0;\n      else \n        w_cnt_gc    <= bin2gray(w_cnt);\n    end\n\n\n    assign  w_q[0]  = w_cnt_gc;\n    assign  w_cnt_gc_asreg_last       = w_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        w_cnt_rd    <= 1'b0;\n      else \n        w_cnt_rd    <= gray2bin(w_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        r_cnt    <= 1'b0;\n      else if (rd_eop_ad)\n        r_cnt    <= r_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;\n   assign r_inv_pad[LOG_WR_DEPTH : 1]        = ~r_cnt;\n   assign adj_w_cnt_rd_pad[0]                = adj_w_cnt_rd_pad_0;\n   assign r_inv_pad[0]                       = r_inv_pad_0;\n\n\n  always @ ( rd_eop_ad )\n    begin\n      if (!rd_eop_ad) begin\n        adj_w_cnt_rd_pad_0    <= 1'b1;\n        r_inv_pad_0           <= 1'b1;\n      end else begin \n        adj_w_cnt_rd_pad_0    <= 1'b0;\n        r_inv_pad_0           <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        d_cnt_pad    <= 1'b0;\n      else \n        d_cnt_pad    <= adj_w_cnt_rd_pad + r_inv_pad ;\n    end\n\n   assign  d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;\n   assign  WR_DATA_COUNT = d_cnt;\n\n  end endgenerate // fifo_ic_adapter\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter\n   assign  WR_DATA_COUNT = wr_data_count_in;\n\n  end endgenerate // fifo_icn_adapter\n\n\n\n  wire                          inverted_reset = ~S_ARESETN;\n  wire                          axi_rs_rst;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_din          ;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_dout         ;\n  wire                          axis_full         ;\n  wire                          axis_almost_full  ;\n  wire                          axis_empty        ;\n  wire                          axis_s_axis_tready;\n  wire                          axis_m_axis_tvalid;\n  wire                          axis_wr_en        ;\n  wire                          axis_rd_en        ;\n  wire                          axis_we           ;\n  wire                          axis_re           ;\n  wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;\n  reg                           axis_pkt_read = 1'b0;\n  wire                          axis_rd_rst;\n  wire                          axis_wr_rst;\n\n  generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||\n               C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst\n      reg                           rst_d1 = 0        ;\n      reg                           rst_d2 = 0        ;\n      reg [3:0]                    axi_rst = 4'h0     ;\n      always @ (posedge inverted_reset or posedge S_ACLK) begin\n        if (inverted_reset) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          axi_rst        <= 4'hf;\n        end else begin\n          rst_d1         <= #`TCQ 1'b0;\n          rst_d2         <= #`TCQ rst_d1;\n          axi_rst        <= #`TCQ {axi_rst[2:0],1'b0};\n        end\n      end\n\n      assign axi_rs_rst = axi_rst[3];//rst_d2;\n  end endgenerate // gaxi_rs_rst\n\n  generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming\n\n    // Write protection when almost full or prog_full is high\n    assign axis_we    = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : \n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign axis_re    = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :\n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? axis_we & S_ACLK_EN : axis_we;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE               (C_INTERFACE_TYPE),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 2  || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_AXIS),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_AXIS),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),\n        .C_USE_ECC                      (C_USE_ECC_AXIS),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_AXIS),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_axis_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (axis_wr_en),\n        .RD_EN                    (axis_rd_en),\n        .PROG_FULL_THRESH         (AXIS_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXIS_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .INJECTDBITERR            (AXIS_INJECTDBITERR), \n        .INJECTSBITERR            (AXIS_INJECTSBITERR),\n  \n        .DIN                      (axis_din),\n        .DOUT                     (axis_dout),\n        .FULL                     (axis_full),\n        .EMPTY                    (axis_empty),\n        .ALMOST_FULL              (axis_almost_full),\n        .PROG_FULL                (AXIS_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXIS_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (AXIS_OVERFLOW),\n        .VALID                    (),\n        .UNDERFLOW                (AXIS_UNDERFLOW),\n        .DATA_COUNT               (axis_dc),\n        .RD_DATA_COUNT            (AXIS_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXIS_WR_DATA_COUNT),\n        .SBITERR                  (AXIS_SBITERR),\n        .DBITERR                  (AXIS_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_axis),\n        .rd_rst_busy              (rd_rst_busy_axis),\n        .wr_rst_i_out             (axis_wr_rst),\n        .rd_rst_i_out             (axis_rd_rst),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign axis_s_axis_tready    = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;\n    assign axis_m_axis_tvalid    = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;\n    assign S_AXIS_TREADY         = axis_s_axis_tready;\n    assign M_AXIS_TVALID         = axis_m_axis_tvalid;\n\n  end endgenerate // axi_streaming\n\n  wire axis_wr_eop;\n  reg  axis_wr_eop_d1 = 1'b0;\n  wire axis_rd_eop;\n  integer  axis_pkt_cnt;\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)\n        axis_pkt_read    <= 1'b0;\n      else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_wr_eop_d1    <= 1'b0;\n      else\n        axis_wr_eop_d1   <= axis_wr_eop;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_cnt    <= 0;\n      else if (axis_wr_eop_d1 && ~axis_rd_eop)\n        axis_pkt_cnt    <= axis_pkt_cnt + 1;\n      else if (axis_rd_eop && ~axis_wr_eop_d1)\n        axis_pkt_cnt    <= axis_pkt_cnt - 1;\n    end\n  end endgenerate // gaxis_pkt_fifo_cc\n\n\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;\nwire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;\nwire axis_rd_has_rst;\nwire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;\nwire  [LOG_DEPTH_AXIS-1 : 0]  wpkt_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;\nwire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;\nwire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;\nwire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;\nwire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;\nreg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;\nreg adj_axis_wpkt_cnt_rd_pad_0 = 0;\nreg rpkt_inv_pad_0 = 0;\nwire axis_af_rd ;\n\ngenerate if (C_HAS_RST == 1) begin : rst_blk_has\n  assign axis_rd_has_rst = axis_rd_rst;\nend endgenerate //rst_blk_has\n\ngenerate if (C_HAS_RST == 0) begin :rst_blk_no\n  assign axis_rd_has_rst = 1'b0;\nend endgenerate //rst_blk_no\n\n   genvar i;\n\n   generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage\n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (LOG_DEPTH_AXIS)\n        )\n     rd_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (wpkt_q[i-1]), \n         .DOUT     (wpkt_q[i])\n        );\n \n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (1)\n        )\n     wr_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (axis_af_q[i-1]), \n         .DOUT     (axis_af_q[i])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (diff_pkt_cnt == 1))\n        axis_pkt_read    <= 1'b0;\n      else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt    <= 1'b0;\n      else if (axis_wr_eop)\n        axis_wpkt_cnt    <= axis_wpkt_cnt + 1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt_gc    <= 1'b0;\n      else \n        axis_wpkt_cnt_gc    <= bin2gray(axis_wpkt_cnt);\n    end\n\n\n    assign  wpkt_q[0]  = axis_wpkt_cnt_gc;\n    assign  axis_wpkt_cnt_gc_asreg_last       = wpkt_q[C_SYNCHRONIZER_STAGE];\n    assign  axis_af_q[0]                      = axis_almost_full;\n    //assign  axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];\n    assign  axis_af_rd                        = axis_af_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_wpkt_cnt_rd    <= 1'b0;\n      else \n        axis_wpkt_cnt_rd    <= gray2bin(axis_wpkt_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_rpkt_cnt    <= 1'b0;\n      else if (axis_rd_eop)\n        axis_rpkt_cnt    <= axis_rpkt_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;\n   assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1]             = ~axis_rpkt_cnt;\n   assign adj_axis_wpkt_cnt_rd_pad[0]                                = adj_axis_wpkt_cnt_rd_pad_0;\n   assign rpkt_inv_pad[0]                                            = rpkt_inv_pad_0;\n\n\n  always @ ( axis_rd_eop )\n    begin\n      if (!axis_rd_eop) begin\n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b1;\n        rpkt_inv_pad_0                <= 1'b1;\n      end else begin \n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b0;\n        rpkt_inv_pad_0                <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        diff_pkt_cnt_pad    <= 1'b0;\n      else \n        diff_pkt_cnt_pad    <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;\n    end\n\n   assign  diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;\n\n\n\n\n\n   end endgenerate // gaxis_pkt_fifo_ic\n\n\n\n\n  // Generate the accurate data count for axi stream packet fifo configuration\n  reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_dc_pkt_fifo <= 0;\n      else if (axis_wr_en && (~axis_rd_en))\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;\n      else if (~axis_wr_en && axis_rd_en)\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;\n    end\n    assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;\n  end endgenerate // gdc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt\n    assign AXIS_DATA_COUNT = 0;\n  end endgenerate // gndc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc\n    assign AXIS_DATA_COUNT = axis_dc;\n  end endgenerate // gdc\n\n  // Register Slice for Write Address Channel\n  generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_AXIS),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_AXIS)\n            )\n    axis_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (axis_din),\n          .S_VALID                   (axis_wr_en),\n          .S_READY                   (S_AXIS_TREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (axis_dout),\n          .M_VALID                   (M_AXIS_TVALID),\n          .M_READY                   (axis_rd_en)\n          );\n  end endgenerate // gaxis_reg_slice\n\n\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata\n    assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;\n    assign M_AXIS_TDATA   = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb\n    assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;\n    assign M_AXIS_TSTRB   = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep\n    assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;\n    assign M_AXIS_TKEEP   = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid\n    assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;\n    assign M_AXIS_TID     = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest\n    assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;\n    assign M_AXIS_TDEST   = axis_dout[TID_OFFSET-1:TDEST_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser\n    assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;\n    assign M_AXIS_TUSER   = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast\n    assign axis_din[0] = S_AXIS_TLAST;\n    assign M_AXIS_TLAST   = axis_dout[0];\n  end endgenerate\n\n  //###########################################################################\n  //  AXI FULL Write Channel (axi_write_channel)\n  //###########################################################################\n\n  localparam IS_AXI_FULL       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;\n  localparam IS_AXI_LITE       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;\n\n  localparam IS_AXI_FULL_WACH  = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WDCH  = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WRCH  = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RACH  = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RDCH  = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_AXI_LITE_WACH  = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WDCH  = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WRCH  = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RACH  = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RDCH  = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_WR_ADDR_CH     = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;\n  localparam IS_WR_DATA_CH     = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;\n  localparam IS_WR_RESP_CH     = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;\n  localparam IS_RD_ADDR_CH     = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;\n  localparam IS_RD_DATA_CH     = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;\n\n  localparam AWID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;\n  localparam AWADDR_OFFSET     = AWID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam AWLEN_OFFSET      = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;\n  localparam AWSIZE_OFFSET     = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;\n  localparam AWBURST_OFFSET    = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;\n  localparam AWLOCK_OFFSET     = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;\n  localparam AWCACHE_OFFSET    = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;\n  localparam AWPROT_OFFSET     = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam AWQOS_OFFSET      = AWPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam AWREGION_OFFSET   = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;\n  localparam AWUSER_OFFSET     = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;\n\n  localparam WID_OFFSET        = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;\n  localparam WDATA_OFFSET      = WID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam WSTRB_OFFSET      = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;\n  localparam WUSER_OFFSET      = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;\n\n  localparam BID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;\n  localparam BRESP_OFFSET      = BID_OFFSET - C_AXI_BRESP_WIDTH;\n  localparam BUSER_OFFSET      = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;\n\n\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_din          ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout         ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout_pkt     ;\n  wire                          wach_full         ;\n  wire                          wach_almost_full  ;\n  wire                          wach_prog_full    ;\n  wire                          wach_empty        ;\n  wire                          wach_almost_empty ;\n  wire                          wach_prog_empty   ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_din          ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_dout         ;\n  wire                          wdch_full         ;\n  wire                          wdch_almost_full  ;\n  wire                          wdch_prog_full    ;\n  wire                          wdch_empty        ;\n  wire                          wdch_almost_empty ;\n  wire                          wdch_prog_empty   ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_din          ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_dout         ;\n  wire                          wrch_full         ;\n  wire                          wrch_almost_full  ;\n  wire                          wrch_prog_full    ;\n  wire                          wrch_empty        ;\n  wire                          wrch_almost_empty ;\n  wire                          wrch_prog_empty   ;\n  wire                          axi_aw_underflow_i;\n  wire                          axi_w_underflow_i ;\n  wire                          axi_b_underflow_i ;\n  wire                          axi_aw_overflow_i ;\n  wire                          axi_w_overflow_i  ;\n  wire                          axi_b_overflow_i  ;\n  wire                          axi_wr_underflow_i;\n  wire                          axi_wr_overflow_i ;\n  wire                          wach_s_axi_awready;\n  wire                          wach_m_axi_awvalid;\n  wire                          wach_wr_en        ;\n  wire                          wach_rd_en        ;\n  wire                          wdch_s_axi_wready ;\n  wire                          wdch_m_axi_wvalid ;\n  wire                          wdch_wr_en        ;\n  wire                          wdch_rd_en        ;\n  wire                          wrch_s_axi_bvalid ;\n  wire                          wrch_m_axi_bready ;\n  wire                          wrch_wr_en        ;\n  wire                          wrch_rd_en        ;\n  wire                          txn_count_up      ;\n  wire                          txn_count_down    ;\n  wire                          awvalid_en        ;\n  wire                          awvalid_pkt       ;\n  wire                          awready_pkt       ;\n  integer                       wr_pkt_count      ;\n  wire                          wach_we           ;\n  wire                          wach_re           ;\n  wire                          wdch_we           ;\n  wire                          wdch_re           ;\n  wire                          wrch_we           ;\n  wire                          wrch_re           ;\n\n  generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel\n    // Write protection when almost full or prog_full is high\n    assign wach_we    = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wach_re    = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        wach_m_axi_awvalid & awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY && wach_m_axi_awvalid :\n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY : 1'b0;\n    assign wach_wr_en = (C_HAS_SLAVE_CE == 1)  ? wach_we & S_ACLK_EN : wach_we;\n    assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 2  || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),\n        .C_USE_ECC                      (C_USE_ECC_WACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_wach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wach_wr_en),\n        .RD_EN                    (wach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AW_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AW_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AW_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AW_INJECTSBITERR),\n  \n        .DIN                      (wach_din),\n        .DOUT                     (wach_dout_pkt),\n        .FULL                     (wach_full),\n        .EMPTY                    (wach_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_AW_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_AW_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_aw_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_aw_underflow_i),\n        .DATA_COUNT               (AXI_AW_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AW_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AW_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AW_SBITERR),\n        .DBITERR                  (AXI_AW_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wach),\n        .rd_rst_busy              (rd_rst_busy_wach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wach_s_axi_awready    = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;\n    assign wach_m_axi_awvalid   = ~wach_empty;\n    assign S_AXI_AWREADY        = wach_s_axi_awready;\n\n    assign AXI_AW_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;\n    assign AXI_AW_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_aw_overflow_i  : 0;\n\n  end endgenerate // axi_write_address_channel\n\n  // Register Slice for Write Address Channel\n  generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WACH)\n            )\n    wach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_din),\n          .S_VALID                   (S_AXI_AWVALID),\n          .S_READY                   (S_AXI_AWREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n  end endgenerate // gwach_reg_slice\n  \n  generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (1)\n            )\n    wach_pkt_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_dout_pkt),\n          .S_VALID                   (awvalid_pkt),\n          .S_READY                   (awready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n\n    assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;\n\n    assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; \n    assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset == 1) begin\n\twr_pkt_count <= 0;\n      end else begin\n\tif(txn_count_up == 1 && txn_count_down == 0) begin\n\t  wr_pkt_count <= wr_pkt_count + 1;\n\tend else if(txn_count_up == 0 && txn_count_down == 1) begin\n\t  wr_pkt_count <= wr_pkt_count - 1;\n\tend\n      end\n    end //Always end\n    assign awvalid_en = (wr_pkt_count > 0)?1:0;\n  end endgenerate\n  \n  generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr\n    assign awvalid_en    = 1;    \n    assign wach_dout     = wach_dout_pkt;\n    assign M_AXI_AWVALID = wach_m_axi_awvalid;\n  end\n  endgenerate\n\n\n\n  generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel\n    // Write protection when almost full or prog_full is high\n    assign wdch_we    = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wdch_re    = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;\n    assign wdch_wr_en = (C_HAS_SLAVE_CE == 1)  ? wdch_we & S_ACLK_EN : wdch_we;\n    assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;\n\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 2  || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),\n        .C_USE_ECC                      (C_USE_ECC_WDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_wdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wdch_wr_en),\n        .RD_EN                    (wdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_W_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_W_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_W_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_W_INJECTSBITERR),\n  \n        .DIN                      (wdch_din),\n        .DOUT                     (wdch_dout),\n        .FULL                     (wdch_full),\n        .EMPTY                    (wdch_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_W_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_W_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_w_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_w_underflow_i),\n        .DATA_COUNT               (AXI_W_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_W_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_W_WR_DATA_COUNT),\n        .SBITERR                  (AXI_W_SBITERR),\n        .DBITERR                  (AXI_W_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wdch),\n        .rd_rst_busy              (rd_rst_busy_wdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wdch_s_axi_wready     = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;\n    assign wdch_m_axi_wvalid = ~wdch_empty;\n    assign S_AXI_WREADY      = wdch_s_axi_wready;\n    assign M_AXI_WVALID      = wdch_m_axi_wvalid;\n\n    assign AXI_W_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i  : 0;\n    assign AXI_W_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_w_overflow_i   : 0;\n\n  end endgenerate // axi_write_data_channel\n\n  // Register Slice for Write Data Channel\n  generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WDCH)\n            )\n    wdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wdch_din),\n          .S_VALID                   (S_AXI_WVALID),\n          .S_READY                   (S_AXI_WREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wdch_dout),\n          .M_VALID                   (M_AXI_WVALID),\n          .M_READY                   (M_AXI_WREADY)\n          );\n  end endgenerate // gwdch_reg_slice\n\n  generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel\n    // Write protection when almost full or prog_full is high\n    assign wrch_we    = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wrch_re    = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;\n    assign wrch_wr_en = (C_HAS_MASTER_CE == 1)  ? wrch_we & M_ACLK_EN : wrch_we;\n    assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 2  || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WRCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WRCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),\n        .C_USE_ECC                      (C_USE_ECC_WRCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WRCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WRCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_wrch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wrch_wr_en),\n        .RD_EN                    (wrch_rd_en),\n        .PROG_FULL_THRESH         (AXI_B_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_B_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .INJECTDBITERR            (AXI_B_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_B_INJECTSBITERR),\n  \n        .DIN                      (wrch_din),\n        .DOUT                     (wrch_dout),\n        .FULL                     (wrch_full),\n        .EMPTY                    (wrch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_B_PROG_FULL),\n        .PROG_EMPTY               (AXI_B_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_b_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_b_underflow_i),\n        .DATA_COUNT               (AXI_B_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_B_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_B_WR_DATA_COUNT),\n        .SBITERR                  (AXI_B_SBITERR),\n        .DBITERR                  (AXI_B_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wrch),\n        .rd_rst_busy              (rd_rst_busy_wrch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wrch_s_axi_bvalid = ~wrch_empty;\n    assign wrch_m_axi_bready     = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;\n    assign S_AXI_BVALID      = wrch_s_axi_bvalid;\n    assign M_AXI_BREADY      = wrch_m_axi_bready;\n\n    assign AXI_B_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i  : 0;\n    assign AXI_B_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_b_overflow_i   : 0;\n  end endgenerate // axi_write_resp_channel\n\n  // Register Slice for Write Response Channel\n  generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WRCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WRCH)\n            )\n    wrch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wrch_din),\n          .S_VALID                   (M_AXI_BVALID),\n          .S_READY                   (M_AXI_BREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wrch_dout),\n          .M_VALID                   (S_AXI_BVALID),\n          .M_READY                   (S_AXI_BREADY)\n          );\n  end endgenerate // gwrch_reg_slice\n\n\n    assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW  == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;\n    assign axi_wr_overflow_i  = C_USE_COMMON_OVERFLOW   == 1 ? (axi_aw_overflow_i  || axi_w_overflow_i  || axi_b_overflow_i)  : 0;\n\n  generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output\n    assign M_AXI_AWADDR    = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];    \n    assign M_AXI_AWLEN     = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];    \n    assign M_AXI_AWSIZE    = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];    \n    assign M_AXI_AWBURST   = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];    \n    assign M_AXI_AWLOCK    = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];    \n    assign M_AXI_AWCACHE   = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];    \n    assign M_AXI_AWQOS     = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];    \n    assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET]    = S_AXI_AWADDR;\n    assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET]   = S_AXI_AWLEN;\n    assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET]   = S_AXI_AWSIZE;\n    assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;\n    assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;\n    assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;\n    assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;\n    assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET]   = S_AXI_AWQOS;\n  end endgenerate // axi_wach_output\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion\n    assign M_AXI_AWREGION  = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];    \n  end endgenerate // axi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion\n    assign M_AXI_AWREGION  = 0;    \n  end endgenerate // naxi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser\n    assign M_AXI_AWUSER  = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];    \n  end endgenerate // axi_awuser\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser\n    assign M_AXI_AWUSER  = 0;    \n  end endgenerate // naxi_awuser\n\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid\n    assign M_AXI_AWID      = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];\n  end endgenerate //axi_awid\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid\n    assign M_AXI_AWID      = 0;\n  end endgenerate //naxi_awid\n\n  generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output\n    assign M_AXI_WDATA     = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n    assign M_AXI_WLAST     = wdch_dout[0];\n    assign wdch_din[WID_OFFSET-1:WDATA_OFFSET]   = S_AXI_WDATA;\n    assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;\n    assign wdch_din[0]   = S_AXI_WLAST;\n  end endgenerate // axi_wdch_output\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin\n    assign M_AXI_WID       = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];\n  end endgenerate\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin\n    assign M_AXI_WID       = 0;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin\n    assign M_AXI_WUSER     = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];    \n  end endgenerate\n  generate if (C_HAS_AXI_WUSER == 0) begin\n    assign M_AXI_WUSER       = 0;\n  end endgenerate\n\n  generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output\n    assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; \n    assign wrch_din[BID_OFFSET-1:BRESP_OFFSET]   = M_AXI_BRESP;\n  end endgenerate // axi_wrch_output\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser\n    assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];\n  end endgenerate // axi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser\n    assign S_AXI_BUSER = 0;\n  end endgenerate // naxi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid\n    assign S_AXI_BID   =  wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];\n  end endgenerate // axi_bid\n  \n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid\n    assign S_AXI_BID   =  0 ;\n  end endgenerate // naxi_bid  \n\n\n  generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1\n    assign wach_din        = {S_AXI_AWADDR, S_AXI_AWPROT};\n    assign M_AXI_AWADDR    = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];    \n  end endgenerate // axi_wach_output1\n\n  generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1\n    assign wdch_din        = {S_AXI_WDATA, S_AXI_WSTRB};\n    assign M_AXI_WDATA     = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n  end endgenerate // axi_wdch_output1\n\n  generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1\n    assign wrch_din        = M_AXI_BRESP;\n    assign S_AXI_BRESP     = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; \n  end endgenerate // axi_wrch_output1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1\n    assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET]     = S_AXI_AWUSER;\n  end endgenerate // gwach_din1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2\n    assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET]     = S_AXI_AWID;\n  end endgenerate // gwach_din2\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3\n    assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET]     = S_AXI_AWREGION;\n  end endgenerate // gwach_din3\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1\n    assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;\n  end endgenerate // gwdch_din1\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2\n    assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;\n  end endgenerate // gwdch_din2\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1\n    assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET]    = M_AXI_BUSER;\n  end endgenerate // gwrch_din1\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2\n    assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET]    = M_AXI_BID;\n  end endgenerate // gwrch_din2\n\n  //end of  axi_write_channel\n\n  //###########################################################################\n  //  AXI FULL Read Channel (axi_read_channel)\n  //###########################################################################\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_din            ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout           ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout_pkt       ;\n  wire                               rach_full           ;\n  wire                               rach_almost_full    ;\n  wire                               rach_prog_full      ;\n  wire                               rach_empty          ;\n  wire                               rach_almost_empty   ;\n  wire                               rach_prog_empty     ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_din            ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_dout           ;\n  wire                               rdch_full           ;\n  wire                               rdch_almost_full    ;\n  wire                               rdch_prog_full      ;\n  wire                               rdch_empty          ;\n  wire                               rdch_almost_empty   ;\n  wire                               rdch_prog_empty     ;\n  wire                               axi_ar_underflow_i  ;\n  wire                               axi_r_underflow_i   ;\n  wire                               axi_ar_overflow_i   ;\n  wire                               axi_r_overflow_i    ;\n  wire                               axi_rd_underflow_i  ;\n  wire                               axi_rd_overflow_i   ;\n  wire                               rach_s_axi_arready  ;\n  wire                               rach_m_axi_arvalid  ;\n  wire                               rach_wr_en          ;\n  wire                               rach_rd_en          ;\n  wire                               rdch_m_axi_rready   ;\n  wire                               rdch_s_axi_rvalid   ;\n  wire                               rdch_wr_en          ;\n  wire                               rdch_rd_en          ;\n  wire                               arvalid_pkt         ;\n  wire                               arready_pkt         ;\n  wire                               arvalid_en          ;\n  wire                               rdch_rd_ok          ;\n  wire                               accept_next_pkt     ;\n  integer                            rdch_free_space     ;\n  integer                            rdch_commited_space ;\n  wire                               rach_we             ;\n  wire                               rach_re             ;\n  wire                               rdch_we             ;\n  wire                               rdch_re             ;\n\n  localparam ARID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;\n  localparam ARADDR_OFFSET     = ARID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam ARLEN_OFFSET      = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;\n  localparam ARSIZE_OFFSET     = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;\n  localparam ARBURST_OFFSET    = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;\n  localparam ARLOCK_OFFSET     = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;\n  localparam ARCACHE_OFFSET    = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;\n  localparam ARPROT_OFFSET     = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam ARQOS_OFFSET      = ARPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam ARREGION_OFFSET   = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;\n  localparam ARUSER_OFFSET     = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;\n\n  localparam RID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;\n  localparam RDATA_OFFSET      = RID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam RRESP_OFFSET      = RDATA_OFFSET - C_AXI_RRESP_WIDTH;\n  localparam RUSER_OFFSET      = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;\n\n\n  generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rach_we    = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;\n\n    // Read protection when almost empty or prog_empty is high\n//    assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;\n    assign rach_re    = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        rach_m_axi_arvalid & arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY && rach_m_axi_arvalid :\n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY : 1'b0;\n    assign rach_wr_en = (C_HAS_SLAVE_CE == 1)  ? rach_we & S_ACLK_EN : rach_we;\n    assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;\n\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 2  || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),\n        .C_USE_ECC                      (C_USE_ECC_RACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_rach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rach_wr_en),\n        .RD_EN                    (rach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AR_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AR_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AR_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AR_INJECTSBITERR),\n  \n        .DIN                      (rach_din),\n        .DOUT                     (rach_dout_pkt),\n        .FULL                     (rach_full),\n        .EMPTY                    (rach_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_AR_PROG_FULL),\n        .PROG_EMPTY               (AXI_AR_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_ar_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_ar_underflow_i),\n        .DATA_COUNT               (AXI_AR_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AR_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AR_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AR_SBITERR),\n        .DBITERR                  (AXI_AR_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rach),\n        .rd_rst_busy              (rd_rst_busy_rach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rach_s_axi_arready    = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;\n    assign rach_m_axi_arvalid = ~rach_empty;\n    assign S_AXI_ARREADY      = rach_s_axi_arready;\n\n    assign AXI_AR_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;\n    assign AXI_AR_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_ar_overflow_i  : 0;\n\n  end endgenerate // axi_read_addr_channel\n\n  // Register Slice for Read Address Channel\n  generate if (C_RACH_TYPE == 1) begin : grach_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RACH)\n            )\n    rach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_din),\n          .S_VALID                   (S_AXI_ARVALID),\n          .S_READY                   (S_AXI_ARREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice\n\n  // Register Slice for Read Address Channel for MM Packet FIFO\n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (1)\n            )\n    reg_slice_mm_pkt_fifo_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_dout_pkt),\n          .S_VALID                   (arvalid_pkt),\n          .S_READY                   (arready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice_mm_pkt_fifo\n\n  \n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid\n    assign M_AXI_ARVALID      = rach_m_axi_arvalid;\n    assign rach_dout          = rach_dout_pkt;\n  end endgenerate // grach_m_axi_arvalid\n  \n  \n  generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd\n    assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;\n    assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;\n    assign accept_next_pkt  = rach_m_axi_arvalid && arready_pkt && arvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset) begin\n\trdch_commited_space <= 0;\n      end else begin\n\tif(rdch_rd_ok && !accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space-1;\n\tend else if(!rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);\n\tend else if(rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);\n\tend\n      end\n    end //Always end\n\n    always@(*) begin\n      rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));\n    end\n\n    assign arvalid_en = (rdch_free_space >= 0)?1:0;\n  end\n  endgenerate\n  \n  generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd\n    assign arvalid_en = 1;    \n  end\n  endgenerate\n\n  generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rdch_we    = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready  & M_AXI_RVALID : M_AXI_RVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign rdch_re    = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid  & S_AXI_RREADY : S_AXI_RREADY;\n    assign rdch_wr_en = (C_HAS_MASTER_CE == 1)  ? rdch_we & M_ACLK_EN : rdch_we;\n    assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 2  || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),\n        .C_USE_ECC                      (C_USE_ECC_RDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_RDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_rdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rdch_wr_en),\n        .RD_EN                    (rdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_R_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_R_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_R_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_R_INJECTSBITERR),\n  \n        .DIN                      (rdch_din),\n        .DOUT                     (rdch_dout),\n        .FULL                     (rdch_full),\n        .EMPTY                    (rdch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_R_PROG_FULL),\n        .PROG_EMPTY               (AXI_R_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_r_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_r_underflow_i),\n        .DATA_COUNT               (AXI_R_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_R_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_R_WR_DATA_COUNT),\n        .SBITERR                  (AXI_R_SBITERR),\n        .DBITERR                  (AXI_R_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rdch),\n        .rd_rst_busy              (rd_rst_busy_rdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rdch_s_axi_rvalid = ~rdch_empty;\n    assign rdch_m_axi_rready     = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;\n    assign S_AXI_RVALID      = rdch_s_axi_rvalid;\n    assign M_AXI_RREADY      = rdch_m_axi_rready;\n\n    assign AXI_R_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i  : 0;\n    assign AXI_R_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_r_overflow_i   : 0;\n\n  end endgenerate //axi_read_data_channel\n\n  // Register Slice for read Data Channel\n  generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RDCH)\n            )\n    rdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rdch_din),\n          .S_VALID                   (M_AXI_RVALID),\n          .S_READY                   (M_AXI_RREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rdch_dout),\n          .M_VALID                   (S_AXI_RVALID),\n          .M_READY                   (S_AXI_RREADY)\n          );\n  end endgenerate // grdch_reg_slice\n\n\n    assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;\n    assign axi_rd_overflow_i  = C_USE_COMMON_OVERFLOW  == 1 ? (axi_ar_overflow_i  || axi_r_overflow_i) : 0;\n\n\n  generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output\n    assign M_AXI_ARADDR    = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];    \n    assign M_AXI_ARLEN     = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];    \n    assign M_AXI_ARSIZE    = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];    \n    assign M_AXI_ARBURST   = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];    \n    assign M_AXI_ARLOCK    = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];    \n    assign M_AXI_ARCACHE   = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];    \n    assign M_AXI_ARPROT    = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];    \n    assign M_AXI_ARQOS     = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];    \n    assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET]    = S_AXI_ARADDR;\n    assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET]   = S_AXI_ARLEN;\n    assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET]   = S_AXI_ARSIZE;\n    assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;\n    assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;\n    assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;\n    assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;\n    assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET]   = S_AXI_ARQOS;\n  end endgenerate // axi_full_rach_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion\n    assign M_AXI_ARREGION  = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];    \n  end endgenerate // axi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion\n    assign M_AXI_ARREGION  = 0;    \n  end endgenerate // naxi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser\n    assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];    \n  end endgenerate // axi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser\n    assign M_AXI_ARUSER = 0;    \n  end endgenerate // naxi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid\n    assign M_AXI_ARID      = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];\n  end endgenerate // axi_arid\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid\n    assign M_AXI_ARID      = 0;\n  end endgenerate // naxi_arid\n\n  generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output\n    assign S_AXI_RDATA     = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];\n    assign S_AXI_RRESP     = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n    assign S_AXI_RLAST     = rdch_dout[0];\n    assign rdch_din[RID_OFFSET-1:RDATA_OFFSET]   = M_AXI_RDATA;\n    assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;\n    assign rdch_din[0] = M_AXI_RLAST;\n  end endgenerate // axi_full_rdch_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output\n    assign S_AXI_RUSER     = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];\n  end endgenerate // axi_full_ruser_output\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output\n    assign S_AXI_RUSER     =  0;\n  end endgenerate // axi_full_nruser_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid\n    assign S_AXI_RID       = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];\n  end endgenerate // axi_rid\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid\n    assign S_AXI_RID       = 0;\n  end endgenerate // naxi_rid\n\n  generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1\n    assign rach_din      = {S_AXI_ARADDR, S_AXI_ARPROT};\n    assign M_AXI_ARADDR  = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];\n    assign M_AXI_ARPROT  = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];\n  end endgenerate // axi_lite_rach_output\n\n  generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1\n    assign rdch_din      = {M_AXI_RDATA, M_AXI_RRESP};\n    assign S_AXI_RDATA   = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];\n    assign S_AXI_RRESP   = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n  end endgenerate // axi_lite_rdch_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1\n    assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET]     = S_AXI_ARUSER;\n  end endgenerate // grach_din1\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2\n    assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET]     = S_AXI_ARID;\n  end endgenerate // grach_din2\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin\n    assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1\n    assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET]     = M_AXI_RUSER;\n  end endgenerate // grdch_din1\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2\n    assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;\n  end endgenerate // grdch_din2\n\n  //end of axi_read_channel\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf\n    assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :\n                       (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :\n                       (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;\n  end endgenerate // gaxi_comm_uf\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of\n    assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :\n                      (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :\n                      (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;\n  end endgenerate // gaxi_comm_of\n  \n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  // Pass Through Logic or Wiring Logic\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  \n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Write Address Channel\n  generate if (C_WACH_TYPE == 2) begin : gwach_pass_through\n    assign M_AXI_AWID      = S_AXI_AWID;\n    assign M_AXI_AWADDR    = S_AXI_AWADDR;\n    assign M_AXI_AWLEN     = S_AXI_AWLEN;\n    assign M_AXI_AWSIZE    = S_AXI_AWSIZE;\n    assign M_AXI_AWBURST   = S_AXI_AWBURST;\n    assign M_AXI_AWLOCK    = S_AXI_AWLOCK;\n    assign M_AXI_AWCACHE   = S_AXI_AWCACHE;\n    assign M_AXI_AWPROT    = S_AXI_AWPROT;\n    assign M_AXI_AWQOS     = S_AXI_AWQOS;\n    assign M_AXI_AWREGION  = S_AXI_AWREGION;\n    assign M_AXI_AWUSER    = S_AXI_AWUSER;\n    assign S_AXI_AWREADY   = M_AXI_AWREADY;\n    assign M_AXI_AWVALID   = S_AXI_AWVALID;\n  end endgenerate // gwach_pass_through;\n\n  // Wiring logic for Write Data Channel\n  generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through\n    assign M_AXI_WID       = S_AXI_WID;\n    assign M_AXI_WDATA     = S_AXI_WDATA;\n    assign M_AXI_WSTRB     = S_AXI_WSTRB;\n    assign M_AXI_WLAST     = S_AXI_WLAST;\n    assign M_AXI_WUSER     = S_AXI_WUSER;\n    assign S_AXI_WREADY    = M_AXI_WREADY;\n    assign M_AXI_WVALID    = S_AXI_WVALID;\n  end endgenerate // gwdch_pass_through;\n\n  // Wiring logic for Write Response Channel\n  generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through\n    assign S_AXI_BID       = M_AXI_BID;\n    assign S_AXI_BRESP     = M_AXI_BRESP;\n    assign S_AXI_BUSER     = M_AXI_BUSER;\n    assign M_AXI_BREADY    = S_AXI_BREADY;\n    assign S_AXI_BVALID    = M_AXI_BVALID;\n  end endgenerate // gwrch_pass_through;\n\n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Read Address Channel\n  generate if (C_RACH_TYPE == 2) begin : grach_pass_through\n    assign M_AXI_ARID      = S_AXI_ARID;\n    assign M_AXI_ARADDR    = S_AXI_ARADDR;\n    assign M_AXI_ARLEN     = S_AXI_ARLEN;\n    assign M_AXI_ARSIZE    = S_AXI_ARSIZE;\n    assign M_AXI_ARBURST   = S_AXI_ARBURST;\n    assign M_AXI_ARLOCK    = S_AXI_ARLOCK;\n    assign M_AXI_ARCACHE   = S_AXI_ARCACHE;\n    assign M_AXI_ARPROT    = S_AXI_ARPROT;\n    assign M_AXI_ARQOS     = S_AXI_ARQOS;\n    assign M_AXI_ARREGION  = S_AXI_ARREGION;\n    assign M_AXI_ARUSER    = S_AXI_ARUSER;\n    assign S_AXI_ARREADY   = M_AXI_ARREADY;\n    assign M_AXI_ARVALID   = S_AXI_ARVALID;\n  end endgenerate // grach_pass_through;\n\n  // Wiring logic for Read Data Channel \n  generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through\n    assign S_AXI_RID      = M_AXI_RID;\n    assign S_AXI_RLAST    = M_AXI_RLAST;\n    assign S_AXI_RUSER    = M_AXI_RUSER;\n    assign S_AXI_RDATA    = M_AXI_RDATA;\n    assign S_AXI_RRESP    = M_AXI_RRESP;\n    assign S_AXI_RVALID   = M_AXI_RVALID;\n    assign M_AXI_RREADY   = S_AXI_RREADY;\n  end endgenerate // grdch_pass_through;\n\n  // Wiring logic for AXI Streaming\n  generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through\n    assign M_AXIS_TDATA   = S_AXIS_TDATA;\n    assign M_AXIS_TSTRB   = S_AXIS_TSTRB;\n    assign M_AXIS_TKEEP   = S_AXIS_TKEEP;\n    assign M_AXIS_TID     = S_AXIS_TID;\n    assign M_AXIS_TDEST   = S_AXIS_TDEST;\n    assign M_AXIS_TUSER   = S_AXIS_TUSER;\n    assign M_AXIS_TLAST   = S_AXIS_TLAST;\n    assign S_AXIS_TREADY  = M_AXIS_TREADY;\n    assign M_AXIS_TVALID  = S_AXIS_TVALID;\n  end endgenerate // gaxis_pass_through;\n\n\nendmodule //fifo_generator_v13_2_1\n\n\n\n/*******************************************************************************\n * Declaration of top-level module for Conventional FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_1_CONV_VER\n  #(\n    parameter  C_COMMON_CLOCK                 = 0,\n    parameter  C_INTERFACE_TYPE               = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_COUNT_TYPE                   = 0,\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DEFAULT_VALUE                = \"\",\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_ENABLE_RLOCS                 = 0,\n    parameter  C_FAMILY                       = \"virtex7\", //Not allowed in Verilog model\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_BACKUP                   = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_INT_CLK                  = 0,\n    parameter  C_HAS_MEMINIT_FILE             = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RD_RST                   = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_RST                   = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_INIT_WR_PNTR_VAL             = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_MIF_FILE_NAME                = \"\",\n    parameter  C_OPTIMIZATION_MODE            = 0,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PRIM_FIFO_TYPE               = \"\",\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_FREQ                      = 1,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_ECC                      = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_USE_FIFO16_FLAGS             = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_FREQ                      = 1,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_WR_RESPONSE_LATENCY          = 1,\n    parameter  C_MSGON_VAL                    = 1,\n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2,\n    parameter  C_AXI_TYPE                     = 0\n   )\n\n  (\n   input                               BACKUP,\n   input                               BACKUP_MARKER,\n   input                               CLK,\n   input                               RST,\n   input                               SRST,\n   input                               WR_CLK,\n   input                               WR_RST,\n   input                               RD_CLK,\n   input                               RD_RST,\n   input [C_DIN_WIDTH-1:0]             DIN,\n   input                               WR_EN,\n   input                               RD_EN,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_ASSERT,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_NEGATE,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_ASSERT,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_NEGATE,\n   input                               INT_CLK,\n   input                               INJECTDBITERR,\n   input                               INJECTSBITERR,\n  \n   output [C_DOUT_WIDTH-1:0]           DOUT,\n   output                              FULL,\n   output                              ALMOST_FULL,\n   output                              WR_ACK,\n   output                              OVERFLOW,\n   output                              EMPTY,\n   output                              ALMOST_EMPTY,\n   output                              VALID,\n   output                              UNDERFLOW,\n   output [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT,\n   output [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT,\n   output [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT,\n   output                              PROG_FULL,\n   output                              PROG_EMPTY,\n   output                              SBITERR,\n   output                              DBITERR,\n   output                              wr_rst_busy_o,\n   output                              wr_rst_busy,\n   output                              rd_rst_busy,\n   output                              wr_rst_i_out,\n   output                              rd_rst_i_out\n  );\n\n/*\n ******************************************************************************\n * Definition of Parameters\n ******************************************************************************\n *     C_COMMON_CLOCK                : Common Clock (1), Independent Clocks (0)\n *     C_COUNT_TYPE                  :    *not used\n *     C_DATA_COUNT_WIDTH            : Width of DATA_COUNT bus\n *     C_DEFAULT_VALUE               :    *not used\n *     C_DIN_WIDTH                   : Width of DIN bus\n *     C_DOUT_RST_VAL                : Reset value of DOUT\n *     C_DOUT_WIDTH                  : Width of DOUT bus\n *     C_ENABLE_RLOCS                :    *not used\n *     C_FAMILY                      : not used in bhv model\n *     C_FULL_FLAGS_RST_VAL          : Full flags rst val (0 or 1)\n *     C_HAS_ALMOST_EMPTY            : 1=Core has ALMOST_EMPTY flag\n *     C_HAS_ALMOST_FULL             : 1=Core has ALMOST_FULL flag\n *     C_HAS_BACKUP                  :    *not used\n *     C_HAS_DATA_COUNT              : 1=Core has DATA_COUNT bus\n *     C_HAS_INT_CLK                 : not used in bhv model\n *     C_HAS_MEMINIT_FILE            :    *not used\n *     C_HAS_OVERFLOW                : 1=Core has OVERFLOW flag\n *     C_HAS_RD_DATA_COUNT           : 1=Core has RD_DATA_COUNT bus\n *     C_HAS_RD_RST                  :    *not used\n *     C_HAS_RST                     : 1=Core has Async Rst\n *     C_HAS_SRST                    : 1=Core has Sync Rst\n *     C_HAS_UNDERFLOW               : 1=Core has UNDERFLOW flag\n *     C_HAS_VALID                   : 1=Core has VALID flag\n *     C_HAS_WR_ACK                  : 1=Core has WR_ACK flag\n *     C_HAS_WR_DATA_COUNT           : 1=Core has WR_DATA_COUNT bus\n *     C_HAS_WR_RST                  :    *not used\n *     C_IMPLEMENTATION_TYPE         : 0=Common-Clock Bram/Dram\n *                                     1=Common-Clock ShiftRam\n *                                     2=Indep. Clocks Bram/Dram\n *                                     3=Virtex-4 Built-in\n *                                     4=Virtex-5 Built-in\n *     C_INIT_WR_PNTR_VAL            :   *not used\n *     C_MEMORY_TYPE                 : 1=Block RAM\n *                                     2=Distributed RAM\n *                                     3=Shift RAM\n *                                     4=Built-in FIFO\n *     C_MIF_FILE_NAME               :   *not used\n *     C_OPTIMIZATION_MODE           :   *not used\n *     C_OVERFLOW_LOW                : 1=OVERFLOW active low\n *     C_PRELOAD_LATENCY             : Latency of read: 0, 1, 2\n *     C_PRELOAD_REGS                : 1=Use output registers\n *     C_PRIM_FIFO_TYPE              : not used in bhv model\n *     C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold\n *     C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold\n *     C_PROG_EMPTY_TYPE             : 0=No programmable empty\n *                                     1=Single prog empty thresh constant\n *                                     2=Multiple prog empty thresh constants\n *                                     3=Single prog empty thresh input\n *                                     4=Multiple prog empty thresh inputs\n *     C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold\n *     C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold\n *     C_PROG_FULL_TYPE              : 0=No prog full\n *                                     1=Single prog full thresh constant\n *                                     2=Multiple prog full thresh constants\n *                                     3=Single prog full thresh input\n *                                     4=Multiple prog full thresh inputs\n *     C_RD_DATA_COUNT_WIDTH         : Width of RD_DATA_COUNT bus\n *     C_RD_DEPTH                    : Depth of read interface (2^N)\n *     C_RD_FREQ                     : not used in bhv model\n *     C_RD_PNTR_WIDTH               : always log2(C_RD_DEPTH)\n *     C_UNDERFLOW_LOW               : 1=UNDERFLOW active low\n *     C_USE_DOUT_RST                : 1=Resets DOUT on RST\n *     C_USE_ECC                     : Used for error injection purpose\n *     C_USE_EMBEDDED_REG            : 1=Use BRAM embedded output register\n *     C_USE_FIFO16_FLAGS            : not used in bhv model\n *     C_USE_FWFT_DATA_COUNT         : 1=Use extra logic for FWFT data count\n *     C_VALID_LOW                   : 1=VALID active low\n *     C_WR_ACK_LOW                  : 1=WR_ACK active low\n *     C_WR_DATA_COUNT_WIDTH         : Width of WR_DATA_COUNT bus\n *     C_WR_DEPTH                    : Depth of write interface (2^N)\n *     C_WR_FREQ                     : not used in bhv model\n *     C_WR_PNTR_WIDTH               : always log2(C_WR_DEPTH)\n *     C_WR_RESPONSE_LATENCY         :    *not used\n *     C_MSGON_VAL                   :    *not used by bhv model\n *     C_ENABLE_RST_SYNC             : 0 = Use WR_RST & RD_RST\n *                                     1 = Use RST\n *     C_ERROR_INJECTION_TYPE        : 0 = No error injection\n *                                     1 = Single bit error injection only\n *                                     2 = Double bit error injection only\n *                                     3 = Single and double bit error injection\n ******************************************************************************\n * Definition of Ports\n ******************************************************************************\n *   BACKUP       : Not used\n *   BACKUP_MARKER: Not used\n *   CLK          : Clock\n *   DIN          : Input data bus\n *   PROG_EMPTY_THRESH       : Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag\n *   PROG_FULL_THRESH        : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag\n *   RD_CLK       : Read Domain Clock\n *   RD_EN        : Read enable\n *   RD_RST       : Read Reset\n *   RST          : Asynchronous Reset\n *   SRST         : Synchronous Reset\n *   WR_CLK       : Write Domain Clock\n *   WR_EN        : Write enable\n *   WR_RST       : Write Reset\n *   INT_CLK      : Internal Clock\n *   INJECTSBITERR: Inject Signle bit error\n *   INJECTDBITERR: Inject Double bit error\n *   ALMOST_EMPTY : One word remaining in FIFO\n *   ALMOST_FULL  : One empty space remaining in FIFO\n *   DATA_COUNT   : Number of data words in fifo( synchronous to CLK)\n *   DOUT         : Output data bus\n *   EMPTY        : Empty flag\n *   FULL         : Full flag\n *   OVERFLOW     : Last write rejected\n *   PROG_EMPTY   : Programmable Empty Flag\n *   PROG_FULL    : Programmable Full Flag\n *   RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)\n *   UNDERFLOW    : Last read rejected\n *   VALID        : Last read acknowledged, DOUT bus VALID\n *   WR_ACK       : Last write acknowledged\n *   WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)\n *   SBITERR      : Single Bit ECC Error Detected\n *   DBITERR      : Double Bit ECC Error Detected\n ******************************************************************************\n */\n\n  //----------------------------------------------------------------------------\n  //- Internal Signals for delayed input signals\n  //- All the input signals except Clock are delayed by 100 ps and then given to\n  //- the models.\n  //----------------------------------------------------------------------------\n \n  reg                         rst_delayed                       ;\n  reg                         empty_fb                       ;\n  reg                         srst_delayed                      ;\n  reg                         wr_rst_delayed                    ;\n  reg                         rd_rst_delayed                    ;\n  reg                         wr_en_delayed                     ;\n  reg                         rd_en_delayed                     ;\n  reg  [C_DIN_WIDTH-1:0]      din_delayed                       ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_delayed         ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_assert_delayed  ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_negate_delayed  ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_delayed          ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_assert_delayed   ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_negate_delayed   ;\n  reg                         injectdbiterr_delayed             ;\n  reg                         injectsbiterr_delayed             ;\n   wire                        empty_p0_out;\n\n  always @* rst_delayed                       <= #`TCQ RST                      ;\n  always @* empty_fb                       <= #`TCQ empty_p0_out                      ;\n  always @* srst_delayed                      <= #`TCQ SRST                     ; \n  always @* wr_rst_delayed                    <= #`TCQ WR_RST                   ; \n  always @* rd_rst_delayed                    <= #`TCQ RD_RST                   ; \n  always @* din_delayed                       <= #`TCQ DIN                      ; \n  always @* wr_en_delayed                     <= #`TCQ WR_EN                    ; \n  always @* rd_en_delayed                     <= #`TCQ RD_EN                    ; \n  always @* prog_empty_thresh_delayed         <= #`TCQ PROG_EMPTY_THRESH        ; \n  always @* prog_empty_thresh_assert_delayed  <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; \n  always @* prog_empty_thresh_negate_delayed  <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; \n  always @* prog_full_thresh_delayed          <= #`TCQ PROG_FULL_THRESH         ; \n  always @* prog_full_thresh_assert_delayed   <= #`TCQ PROG_FULL_THRESH_ASSERT  ; \n  always @* prog_full_thresh_negate_delayed   <= #`TCQ PROG_FULL_THRESH_NEGATE  ; \n  always @* injectdbiterr_delayed             <= #`TCQ INJECTDBITERR            ; \n  always @* injectsbiterr_delayed             <= #`TCQ INJECTSBITERR            ; \n\n  /*****************************************************************************\n   * Derived parameters\n   ****************************************************************************/\n  //There are 2 Verilog behavioral models\n  // 0 = Common-Clock FIFO/ShiftRam FIFO\n  // 1 = Independent Clocks FIFO\n  // 2 = Low Latency Synchronous FIFO\n  // 3 = Low Latency Asynchronous FIFO\n  localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :\n                              (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n\n  //Internal reset signals\n  reg                                rd_rst_asreg    = 1'b0;\n  reg                                rd_rst_asreg_d1 = 1'b0;\n  reg                                rd_rst_asreg_d2 = 1'b0;\n  reg                                rd_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_reg      = 1'b0;\n  reg                                rd_rst_comb     = 1'b1;\n  reg                                rd_rst_comb_d1  = 1'b0;\n  reg                                wr_rst_d0       = 1'b0;\n  reg                                wr_rst_d1       = 1'b0;\n  reg                                wr_rst_d2       = 1'b0;\n  reg                                rd_rst_d0       = 1'b0;\n  reg                                rd_rst_d1       = 1'b0;\n  reg                                rd_rst_d2       = 1'b0;\n  reg                                rd_rst_d3       = 1'b0;\n  reg                                wrrst_done      = 1'b0;\n  reg                                rdrst_done      = 1'b0;\n  reg                                wr_rst_asreg    = 1'b0;\n  reg                                wr_rst_asreg_d1 = 1'b0;\n  reg                                wr_rst_asreg_d2 = 1'b0;\n  reg                                wr_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_wr_d0    = 1'b0;\n  reg                                rd_rst_wr_d1    = 1'b0;\n  reg                                rd_rst_wr_d2    = 1'b0;\n  reg                                wr_rst_reg      = 1'b0;\n  reg                                rst_active_i    = 1'b1;\n  reg                                rst_delayed_d1  = 1'b1;\n  reg                                rst_delayed_d2  = 1'b1;\n  reg                                wr_rst_comb     = 1'b1;\n  reg                                wr_rst_comb_d1  = 1'b0;\n  wire                               wr_rst_i;\n  wire                               rd_rst_i;\n  wire                               rst_i;\n\n  //Internal reset signals\n  reg                                rst_asreg     = 1'b0;\n  reg                                srst_asreg    = 1'b0;\n  reg                                rst_asreg_d1  = 1'b0;\n  reg                                rst_asreg_d2  = 1'b0;\n  reg                                srst_asreg_d1 = 1'b0;\n  reg                                srst_asreg_d2 = 1'b0;\n  reg                                rst_reg       = 1'b0;\n  reg                                srst_reg      = 1'b0;\n  reg                                rst_comb      = 1'b1;\n  reg                                rst_comb_d1   = 1'b0;\n  wire                               srst_comb;\n  reg                                rst_full_gen_i = 0;\n  reg                                rst_full_ff_i = 0;\n  reg  [2:0]                         sckt_ff0_bsy_o_i = {3{1'b0}};\n                                     \n  wire                               RD_CLK_P0_IN;\n  wire                               RST_P0_IN;\n  wire                               RD_EN_FIFO_IN;\n  wire                               RD_EN_P0_IN;\n\n  wire                               ALMOST_EMPTY_FIFO_OUT;\n  wire                               ALMOST_FULL_FIFO_OUT;\n  wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT_FIFO_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DOUT_FIFO_OUT;\n  wire                               EMPTY_FIFO_OUT;\n  wire                               fifo_empty_fb;\n  wire                               FULL_FIFO_OUT;\n  wire                               OVERFLOW_FIFO_OUT;\n  wire                               PROG_EMPTY_FIFO_OUT;\n  wire                               PROG_FULL_FIFO_OUT;\n  wire                               VALID_FIFO_OUT;\n  wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT_FIFO_OUT;\n  wire                               UNDERFLOW_FIFO_OUT;\n  wire                               WR_ACK_FIFO_OUT;\n  wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT_FIFO_OUT;\n\n\n  //***************************************************************************\n  // Internal Signals\n  //   The core uses either the internal_ wires or the preload0_ wires depending\n  //     on whether the core uses Preload0 or not.\n  //   When using preload0, the internal signals connect the internal core to\n  //     the preload logic, and the external core's interfaces are tied to the\n  //     preload0 signals from the preload logic.\n  //***************************************************************************\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_OUT;\n  wire                               VALID_P0_OUT;\n  wire                               EMPTY_P0_OUT;\n  wire                               ALMOSTEMPTY_P0_OUT;\n  reg                                EMPTY_P0_OUT_Q;\n  reg                                ALMOSTEMPTY_P0_OUT_Q;\n  wire                               UNDERFLOW_P0_OUT;\n  wire                               RDEN_P0_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_IN;\n  wire                               EMPTY_P0_IN;\n  reg  [31:0]                        DATA_COUNT_FWFT;\n  reg                                SS_FWFT_WR  ;\n  reg                                SS_FWFT_RD ;\n\n  wire                               sbiterr_fifo_out;\n  wire                               dbiterr_fifo_out;\n  wire                               inject_sbit_err;\n  wire                               inject_dbit_err;\n  wire                               sckt_wr_rst_i;\n  wire                               sckt_rd_rst_i;\n  reg                                sckt_wr_rst_i_q = 1'b0;\n \n  wire                               w_fab_read_data_valid_i;\n  wire                               w_read_data_valid_i;\n  wire                               w_ram_valid_i;\n  // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.\n  assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectsbiterr_delayed : 0;\n  assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectdbiterr_delayed : 0;\n                           \n  assign wr_rst_i_out = wr_rst_i;\n  assign rd_rst_i_out = rd_rst_i;\n  assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];\n  generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o\n    wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;\n    always @ (posedge clk_i)\n      sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; \n  end endgenerate \n// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL\n// parameter (1=Independent Clocks, 0=Common Clock)\n\n  localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;\ngenerate\ncase (C_VERILOG_IMPL)\n0 : begin : block1_ss\n  //Common Clock Behavioral Model\n  fifo_generator_v13_2_1_bhv_ver_ss\n  #(\n    .C_FAMILY                            (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                  (C_DATA_COUNT_WIDTH),            \n    .C_DIN_WIDTH                         (C_DIN_WIDTH),                   \n    .C_DOUT_RST_VAL                      (C_DOUT_RST_VAL),                \n    .C_DOUT_WIDTH                        (C_DOUT_WIDTH),                  \n    .C_FULL_FLAGS_RST_VAL                (FULL_FLAGS_RST_VAL),            \n    .C_HAS_ALMOST_EMPTY                  (C_HAS_ALMOST_EMPTY),            \n    .C_HAS_ALMOST_FULL                   ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),             \n    .C_HAS_DATA_COUNT                    (C_HAS_DATA_COUNT),              \n    .C_HAS_OVERFLOW                      (C_HAS_OVERFLOW),                \n    .C_HAS_RD_DATA_COUNT                 (C_HAS_RD_DATA_COUNT),           \n    .C_HAS_RST                           (C_EN_SAFETY_CKT?0:C_HAS_RST),                     \n    .C_HAS_SRST                          (C_EN_SAFETY_CKT?1:C_HAS_SRST),                    \n    .C_HAS_UNDERFLOW                     (C_HAS_UNDERFLOW),               \n    .C_HAS_VALID                         (C_HAS_VALID),                   \n    .C_HAS_WR_ACK                        (C_HAS_WR_ACK),                  \n    .C_HAS_WR_DATA_COUNT                 (C_HAS_WR_DATA_COUNT),           \n    .C_IMPLEMENTATION_TYPE               (C_IMPLEMENTATION_TYPE),         \n    .C_MEMORY_TYPE                       (C_MEMORY_TYPE),                 \n    .C_OVERFLOW_LOW                      (C_OVERFLOW_LOW),                \n    .C_PRELOAD_LATENCY                   (C_PRELOAD_LATENCY),             \n    .C_PRELOAD_REGS                      (C_PRELOAD_REGS),                \n    .C_PROG_EMPTY_THRESH_ASSERT_VAL      (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL      (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                   (C_PROG_EMPTY_TYPE),             \n    .C_PROG_FULL_THRESH_ASSERT_VAL       (C_PROG_FULL_THRESH_ASSERT_VAL), \n    .C_PROG_FULL_THRESH_NEGATE_VAL       (C_PROG_FULL_THRESH_NEGATE_VAL), \n    .C_PROG_FULL_TYPE                    (C_PROG_FULL_TYPE),              \n    .C_RD_DATA_COUNT_WIDTH               (C_RD_DATA_COUNT_WIDTH),         \n    .C_RD_DEPTH                          (C_RD_DEPTH),                    \n    .C_RD_PNTR_WIDTH                     (C_RD_PNTR_WIDTH),               \n    .C_UNDERFLOW_LOW                     (C_UNDERFLOW_LOW),               \n    .C_USE_DOUT_RST                      (C_USE_DOUT_RST),                \n    .C_USE_EMBEDDED_REG                  (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                     (C_EN_SAFETY_CKT),            \n    .C_USE_FWFT_DATA_COUNT               (C_USE_FWFT_DATA_COUNT),         \n    .C_VALID_LOW                         (C_VALID_LOW),                   \n    .C_WR_ACK_LOW                        (C_WR_ACK_LOW),                  \n    .C_WR_DATA_COUNT_WIDTH               (C_WR_DATA_COUNT_WIDTH),         \n    .C_WR_DEPTH                          (C_WR_DEPTH),                    \n    .C_WR_PNTR_WIDTH                     (C_WR_PNTR_WIDTH),               \n    .C_USE_ECC                           (C_USE_ECC),                     \n    .C_ENABLE_RST_SYNC                   (C_ENABLE_RST_SYNC),             \n    .C_ERROR_INJECTION_TYPE              (C_ERROR_INJECTION_TYPE),\n    .C_FIFO_TYPE                         (C_FIFO_TYPE)                     \n  )\n  gen_ss\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .CLK                      (CLK),\n    .RST                      (C_EN_SAFETY_CKT?1'b0:rst_i),\n    .SRST                     (C_EN_SAFETY_CKT?sckt_wr_rst_i:srst_delayed),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .USER_EMPTY_FB            (empty_fb),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .DATA_COUNT               (DATA_COUNT_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .WR_RST_BUSY              (wr_rst_busy),\n    .RD_RST_BUSY              (rd_rst_busy),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n1 : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_1_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT), \n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .fab_read_data_valid_i    (w_fab_read_data_valid_i),\n    .read_data_valid_i        (w_read_data_valid_i),\n    .ram_valid_i              (w_ram_valid_i),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\n2 : begin : ll_afifo_inst\n  fifo_generator_v13_2_1_beh_ver_ll_afifo\n  #(\n    .C_DIN_WIDTH                    (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                 (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                   (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_RD_DATA_COUNT            (C_HAS_RD_DATA_COUNT),\n    .C_HAS_WR_DATA_COUNT            (C_HAS_WR_DATA_COUNT),\n    .C_RD_DEPTH                     (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                (C_RD_PNTR_WIDTH),\n    .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n    .C_WR_DATA_COUNT_WIDTH          (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                     (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                (C_WR_PNTR_WIDTH),\n    .C_FIFO_TYPE                    (C_FIFO_TYPE)\n   )\n  gen_ll_afifo\n  (\n    .DIN                        (din_delayed),\n    .RD_CLK                     (RD_CLK),\n    .RD_EN                      (rd_en_delayed),\n    .WR_RST                     (wr_rst_i),\n    .RD_RST                     (rd_rst_i),\n    .WR_CLK                     (WR_CLK),\n    .WR_EN                      (wr_en_delayed),\n    .DOUT                       (DOUT),\n    .EMPTY                      (EMPTY),\n    .FULL                       (FULL)\n  );\nend\ndefault : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_1_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT),\n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\nendcase\nendgenerate\n\n\n   //**************************************************************************\n   // Connect Internal Signals\n   //   (Signals labeled internal_*)\n   //  In the normal case, these signals tie directly to the FIFO's inputs and\n   //    outputs.\n   //  In the case of Preload Latency 0 or 1, there are intermediate\n   //    signals between the internal FIFO and the preload logic.\n   //**************************************************************************\n   \n   \n   //***********************************************\n   // If First-Word Fall-Through, instantiate\n   // the preload0 (FWFT) module\n   //***********************************************\n   wire                        rd_en_to_fwft_fifo;\n   wire                        sbiterr_fwft;\n   wire                        dbiterr_fwft;\n   wire [C_DOUT_WIDTH-1:0]     dout_fwft;\n   wire                        empty_fwft;\n   wire                        rd_en_fifo_in;\n   wire                        stage2_reg_en_i;\n   wire [1:0]                  valid_stages_i;\n   wire                        rst_fwft;\n   //wire                        empty_p0_out;\n   reg  [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n   localparam IS_PKT_FIFO      = (C_FIFO_TYPE == 1) ? 1 : 0;\n   localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;\n   assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2_fwft\n\n\n         fifo_generator_v13_2_1_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_EMBEDDED_REG  (C_USE_EMBEDDED_REG),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (C_FIFO_TYPE)\n             )\n             fgpl0\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (RST_P0_IN),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (RD_EN_P0_IN),\n                .FIFOEMPTY        (EMPTY_P0_IN),\n                .FIFODATA         (DATA_P0_IN),\n                .FIFOSBITERR      (sbiterr_fifo_out),\n                .FIFODBITERR      (dbiterr_fifo_out),\n                // Output\n                .USERDATA         (dout_fwft),\n                .USERVALID        (VALID_P0_OUT),\n                .USEREMPTY        (empty_fwft),\n                .USERALMOSTEMPTY  (ALMOSTEMPTY_P0_OUT),\n                .USERUNDERFLOW    (UNDERFLOW_P0_OUT),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_fifo_in),\n                .USERSBITERR      (sbiterr_fwft),\n                .USERDBITERR      (dbiterr_fwft),\n                .STAGE2_REG_EN    (stage2_reg_en_i),\n                .fab_read_data_valid_i_o    (w_fab_read_data_valid_i),\n                .read_data_valid_i_o        (w_read_data_valid_i),\n                .ram_valid_i_o              (w_ram_valid_i),\n                .VALID_STAGES                (valid_stages_i)\n                );\n\n         \n         //***********************************************\n         // Connect inputs to preload (FWFT) module\n         //***********************************************\n         //Connect the RD_CLK of the Preload (FWFT) module to CLK if we \n         // have a common-clock FIFO, or RD_CLK if we have an \n         // independent clock FIFO\n         assign RD_CLK_P0_IN       = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);\n         assign RST_P0_IN          = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;\n         assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n         assign EMPTY_P0_IN        = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;\n         assign DATA_P0_IN         = DOUT_FIFO_OUT;\n         \n         //***********************************************\n         // Connect outputs from preload (FWFT) module\n         //***********************************************\n         assign VALID              = VALID_P0_OUT ;\n         assign ALMOST_EMPTY       = ALMOSTEMPTY_P0_OUT;\n         assign UNDERFLOW          = UNDERFLOW_P0_OUT ;\n         \n         assign RD_EN_FIFO_IN      = rd_en_fifo_in;\n         \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:\n           (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : \n           DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];  \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               EMPTY_P0_OUT_Q       <= 1;\n               ALMOSTEMPTY_P0_OUT_Q <= 1;\n            end else begin\n               EMPTY_P0_OUT_Q       <= #`TCQ empty_p0_out;\n//               EMPTY_P0_OUT_Q       <= #`TCQ EMPTY_FIFO_OUT;\n               ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;\n            end\n         end //always\n         \n         \n         //***********************************************\n         // logic for common-clock data count when FWFT is selected\n         //***********************************************\n         initial begin\n            SS_FWFT_RD = 1'b0;\n            DATA_COUNT_FWFT = 0 ;\n            SS_FWFT_WR   = 1'b0 ;\n         end //initial\n         \n         \n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter. SS_FWFT_WR and SS_FWFT_RD\n         // are the up/down enables for the counter.\n         //***********************************************\n         always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin\n            if (C_VALID_LOW == 1) begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;\n            end else begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;\n            end\n            SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT))  ;\n         end \n\n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter for FWFT. This always block \n         // calculates the counter.\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               DATA_COUNT_FWFT      <= 0;\n            end else begin\n               //if (srst_delayed && (C_HAS_SRST == 1) ) begin\n               if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin\n                  DATA_COUNT_FWFT      <= #`TCQ 0;\n               end else begin\n                  case ( {SS_FWFT_WR, SS_FWFT_RD})\n                    2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                    2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;\n                    2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;\n                    2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                  endcase  \n               end //if SRST\n            end //IF RST\n         end //always\n\n      end endgenerate // : block2\n\n    // AXI Streaming Packet FIFO\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_plus1 = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_reg   = 0;\n    reg                         partial_packet     = 0;\n    reg                         stage1_eop_d1      = 0;\n    reg                         rd_en_fifo_in_d1   = 0;\n    reg                         eop_at_stage2      = 0;\n    reg                         ram_pkt_empty      = 0;\n    reg                         ram_pkt_empty_d1   = 0;\n\n    wire [C_DOUT_WIDTH-1:0]     dout_p0_out;\n    wire                        packet_empty_wr;\n    wire                        wr_rst_fwft_pkt_fifo;\n    wire                        dummy_wr_eop;\n    wire                        ram_wr_en_pkt_fifo;\n    wire                        wr_eop;\n    wire                        ram_rd_en_compare;\n    wire                        stage1_eop;\n    wire                        pkt_ready_to_read;\n    wire                        rd_en_2_stage2;\n\n    // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)\n    // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP\n    // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of\n    // write packet count\n    generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop\n       always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n          if (wr_rst_fwft_pkt_fifo)\n             partial_packet   <= 1'b0;\n          else begin\n             if (srst_delayed | wr_rst_busy | rd_rst_busy)\n                partial_packet <= #`TCQ 1'b0;\n             else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))\n                partial_packet <= #`TCQ 1'b1;\n             else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)\n                partial_packet <= #`TCQ 1'b0;\n          end\n        end\n    end endgenerate // gdummy_wr_eop\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin : gpkt_fifo_fwft\n      assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;\n      assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);\n      assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];\n  \n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft) begin\n          stage1_eop_d1    <= 1'b0;\n          rd_en_fifo_in_d1 <= 1'b0;\n        end else begin\n          if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            stage1_eop_d1    <= #`TCQ 1'b0;\n            rd_en_fifo_in_d1 <= #`TCQ 1'b0;\n          end else begin\n            stage1_eop_d1    <= #`TCQ stage1_eop;\n            rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;\n          end\n        end\n      end\n      assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;\n      assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);\n      assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);\n      assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;\n\n\n         fifo_generator_v13_2_1_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (2) // Enable low latency fwft logic\n             )\n         pkt_fifo_fwft\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (rst_fwft),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (rd_en_delayed),\n                .FIFOEMPTY        (pkt_ready_to_read),\n                .FIFODATA         (dout_fwft),\n                .FIFOSBITERR      (sbiterr_fwft),\n                .FIFODBITERR      (dbiterr_fwft),\n                // Output\n                .USERDATA         (dout_p0_out),\n                .USERVALID        (),\n                .USEREMPTY        (empty_p0_out),\n                .USERALMOSTEMPTY  (),\n                .USERUNDERFLOW    (),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_2_stage2),\n                .USERSBITERR      (SBITERR),\n                .USERDBITERR      (DBITERR),\n                .STAGE2_REG_EN    (),\n                .VALID_STAGES     ()\n                );\n\n      assign pkt_ready_to_read  = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));\n      assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft)\n          eop_at_stage2 <= 1'b0;\n        else if (stage2_reg_en_i)\n          eop_at_stage2 <= #`TCQ stage1_eop;\n      end\n\n      //---------------------------------------------------------------------------\n      // Write and Read Packet Count\n      //---------------------------------------------------------------------------\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count  <= 0;\n         else if (srst_delayed  | wr_rst_busy | rd_rst_busy)\n            wr_pkt_count  <= #`TCQ 0;\n         else if (wr_eop)\n            wr_pkt_count  <= #`TCQ wr_pkt_count + 1;\n      end\n    \n    end endgenerate //: gpkt_fifo_fwft\n\n    assign DOUT               = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;\n    assign EMPTY              = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            rd_pkt_count       <= 0;\n            rd_pkt_count_plus1 <= 1;\n         end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            rd_pkt_count       <= #`TCQ 0;\n            rd_pkt_count_plus1 <= #`TCQ 1;\n         end else if (stage2_reg_en_i && stage1_eop) begin\n            rd_pkt_count       <= #`TCQ rd_pkt_count + 1;\n            rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;\n         end\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (SRST | wr_rst_busy | rd_rst_busy) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n    end endgenerate //grss_pkt_cnt\n    \n    localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;\n    reg  [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_b2g = 0;\n    wire [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_rd;\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt\n      // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count_b2g  <= 0;\n         else\n            wr_pkt_count_b2g  <= #`TCQ wr_pkt_count;\n      end\n\n      // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            wr_pkt_count_q       <= 0;\n         else\n            wr_pkt_count_q       <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};\n      end\n\n      always @* begin\n        if (stage1_eop)\n           rd_pkt_count    <= rd_pkt_count_reg + 1;\n        else\n           rd_pkt_count    <= rd_pkt_count_reg;\n      end\n\n      assign wr_pkt_count_rd    = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            rd_pkt_count_reg       <= 0;\n         else if (rd_en_fifo_in)\n            rd_pkt_count_reg       <= #`TCQ rd_pkt_count;\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (rd_pkt_count != wr_pkt_count_rd) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n\n      // Synchronize the empty in write domain\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            pkt_empty_sync  <= 'b1;\n         else\n            pkt_empty_sync  <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};\n      end\n\n    end endgenerate //gras_pkt_cnt\n\n   generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO\n\n     //***********************************************\n     // If NOT First-Word Fall-Through, wire the outputs\n     // of the internal _ss or _as FIFO directly to the\n     // output, and do not instantiate the preload0\n     // module.\n     //***********************************************\n\n     assign RD_CLK_P0_IN       = 0;\n     assign RST_P0_IN          = 0;\n     assign RD_EN_P0_IN        = 0;\n\n     assign RD_EN_FIFO_IN      = rd_en_delayed;\n\n     assign DOUT               = DOUT_FIFO_OUT;\n     assign DATA_P0_IN         = 0;\n     assign VALID              = VALID_FIFO_OUT;\n     assign EMPTY              = EMPTY_FIFO_OUT;\n     assign ALMOST_EMPTY       = ALMOST_EMPTY_FIFO_OUT;\n     assign EMPTY_P0_IN        = 0;\n     assign UNDERFLOW          = UNDERFLOW_FIFO_OUT;\n     assign DATA_COUNT         = DATA_COUNT_FIFO_OUT;\n     assign SBITERR            = sbiterr_fifo_out;\n     assign DBITERR            = dbiterr_fifo_out;\n\n   end endgenerate // STD_FIFO\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO\n     assign empty_p0_out       = empty_fwft;\n     assign SBITERR            = sbiterr_fwft;\n     assign DBITERR            = dbiterr_fwft;\n     assign DOUT               = dout_fwft;\n     assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n\n   end endgenerate // NO_PKT_FIFO\n\n   //***********************************************\n   // Connect user flags to internal signals\n   //***********************************************\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3\n      if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);\n      end //block_ic\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3\n   endgenerate\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30\n       if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30\n   endgenerate\n\n\n    \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both\n       if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30_both\n   endgenerate\n\n generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both\n      if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));\n      end //block_ic_both\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3_both\n   endgenerate\n\n\n   //If we are not using extra logic for the FWFT data count,\n   //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the\n   //internal FIFO instance  \n   generate\n      if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n   //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal\n   //FIFO instance\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1) begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n      else begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n\n   //Connect other flags to the internal FIFO instance\n   assign       FULL        = FULL_FIFO_OUT;\n   assign       ALMOST_FULL = ALMOST_FULL_FIFO_OUT;\n   assign       WR_ACK      = WR_ACK_FIFO_OUT;\n   assign       OVERFLOW    = OVERFLOW_FIFO_OUT;\n   assign       PROG_FULL   = PROG_FULL_FIFO_OUT;\n   assign       PROG_EMPTY  = PROG_EMPTY_FIFO_OUT;\n\n\n  /**************************************************************************\n  * find_log2\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n   // if an asynchronous FIFO has been selected, display a message that the FIFO\n   //   will not be cycle-accurate in simulation\n   initial begin\n      if (C_IMPLEMENTATION_TYPE == 2) begin\n         $display(\"WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.\");\n      end else if (C_MEMORY_TYPE == 4) begin\n         $display(\"FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.\");\n         $finish;\n      end\n\n      if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin\n         $display(\"FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.\");\n         $finish;\n      end\n\n      if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin\n         $display(\"FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.\");\n         $finish;\n      end\n\n      if (C_USE_ECC == 1) begin\n         if (C_DIN_WIDTH != C_DOUT_WIDTH) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.\");\n            $finish;\n         end\n         if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.\");\n            $finish;\n         end\n      end\n\n   end //initial\n\n  /**************************************************************************\n  * Internal reset logic\n  **************************************************************************/\n  assign wr_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg|sckt_wr_rst_i : 0;\n  assign rd_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg|sckt_rd_rst_i : 0;\n  assign rst_i            = C_HAS_RST ? rst_reg|sckt_wr_rst_i : 0;\n\n  wire rst_2_sync;\n  wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;\n\n  localparam RST_SYNC_STAGES = C_EN_SAFETY_CKT == 0 ? C_COMMON_CLOCK ? C_SYNCHRONIZER_STAGE : C_SYNCHRONIZER_STAGE+2 : 5;\n  localparam RST_BUSY_LEN    = 4;\n  reg  wr_rst_busy_i = 0;\n  reg  rd_rst_busy_i = 0;\n  generate\n      if (C_ENABLE_RST_SYNC == 0 || (C_HAS_RST == 0 && C_HAS_SRST == 0)) begin : gnrst_sync\n        always @* begin\n          wr_rst_reg <= wr_rst_delayed;\n          rd_rst_reg <= rd_rst_delayed;\n          rst_reg    <= 1'b0;\n          srst_reg    <= 1'b0;\n        end\n        assign rst_2_sync = wr_rst_delayed;\n        assign wr_rst_busy = 1'b0;\n        assign wr_rst_busy_o = 1'b0;\n        assign rd_rst_busy = 1'b0;\n        assign sckt_wr_rst_i = 1'b0;\n      end // gnrst_sync\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 0) begin : g7s_ic_rst_nsckt\n        reg [1:0]                 arst_sync_wr  = 2'b11;\n        reg [1:0]                 arst_sync_rd  = 2'b11;\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge WR_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge RD_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_rd    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_rd    <= #`TCQ {arst_sync_rd[0], rst_delayed};\n        end\n        always @(posedge WR_CLK) begin\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n\tend\n        always @(posedge WR_CLK or posedge arst_sync_wr[1]) begin\n\t  if (arst_sync_wr[1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n            rd_rst_wr_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            rd_rst_wr_ext  <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t    if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t      sckt_wr_rst_ic <= #`TCQ 1'b0;\n            else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t      wr_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n        always @(posedge RD_CLK) begin\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], sckt_wr_rst_ic};\n\tend\n        always @(posedge RD_CLK or posedge arst_sync_rd[1]) begin\n\t  if (arst_sync_rd[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n            wr_rst_rd_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            wr_rst_rd_ext  <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t    if (wr_rst_rd_ext[1]) begin\n\t      sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t      rd_rst_busy_i  <= #`TCQ 1'b0;\n\t    end\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic|arst_sync_wr[1];\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic|arst_sync_rd[1];\n      end // g7s_ic_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 1) begin : g7s_ic_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] arst_sync_rd  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        always @(posedge WR_CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n          rd_rst_wr_ext    <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_wr[RST_SYNC_STAGES-1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n          end else if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t    sckt_wr_rst_ic <= #`TCQ 1'b0;\n          else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t    wr_rst_busy_i  <= #`TCQ 1'b0;\n\tend\n        always @(posedge RD_CLK) begin\n\t  arst_sync_rd     <= #`TCQ {arst_sync_rd[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n          wr_rst_rd_ext    <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_rd[RST_SYNC_STAGES-1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n\t  end else if (wr_rst_rd_ext[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t    rd_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic;\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic;\n      end // g7s_ic_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 0) begin : g7s_cc_rst_nsckt\n        reg [1:0]              arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge CLK) begin\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0] | arst_sync_wr[1]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc | arst_sync_wr[1];\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 1) begin : g7s_cc_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n\n        always @(posedge CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc;\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst\n        assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;\n        assign rd_rst_busy = rst_reg;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = rst_reg;\n        always @* rst_full_ff_i  <= 1'b0;\n        always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;\n\n        always @(posedge CLK) begin\n          rst_delayed_d1 <= #`TCQ srst_delayed;\n          rst_delayed_d2 <= #`TCQ rst_delayed_d1;\n          if (rst_reg || rst_delayed_d2) begin\n            rst_active_i <= #`TCQ 1'b1;\n          end else begin\n            rst_active_i <= #`TCQ rst_reg;\n          end    \n        end   \n        always @(posedge CLK) begin\n          if (~rst_reg && srst_delayed) begin\n             rst_reg <= #`TCQ 1'b1;\n           end else if (rst_reg) begin\n             rst_reg <= #`TCQ 1'b0;\n           end else begin\n             rst_reg <= #`TCQ rst_reg;\n           end    \n        end   \n      end // g8s_cc_rst\n      else if (IS_8SERIES != 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_srst\n        assign wr_rst_busy = srst_delayed;\n        assign rd_rst_busy = srst_delayed;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = srst_delayed;\n        always @* rst_full_ff_i  <= 1'b0;\n      end // g7s_cc_srst\n  endgenerate \n\n  reg rst_d1 = 1'b0;\n  reg rst_d2 = 1'b0;\n  reg rst_d3 = 1'b0;\n  reg rst_d4 = 1'b0;\n  generate\n    if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1\n    // RST_FULL_GEN replaces the reset falling edge detection used to de-assert\n    // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.\n\n    // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &\n    // PROG_FULL\n\n      always @ (posedge rst_2_sync or posedge clk_2_sync) begin\n        if (rst_2_sync && C_EN_SAFETY_CKT == 0) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          rst_d3         <= 1'b1;\n          rst_d4         <= 1'b0;\n        end else begin\n          if (srst_delayed) begin\n            rst_d1         <= #`TCQ 1'b1;\n            rst_d2         <= #`TCQ 1'b1;\n            rst_d3         <= #`TCQ 1'b1;\n            rst_d4         <= #`TCQ 1'b0;\n          end else begin\n            rst_d1         <= #`TCQ wr_rst_busy;//1'b0;\n            rst_d2         <= #`TCQ rst_d1;\n            rst_d3         <= #`TCQ rst_d2 | sckt_wr_rst_i;\n            rst_d4         <= #`TCQ rst_d3;\n          end\n        end\n      end\n\n      always @* rst_full_ff_i  <= C_HAS_SRST ? 1'b0 : rst_d2 | sckt_wr_rst_i;\n      always @* rst_full_gen_i <= C_HAS_SRST ? rst_d4 : rst_d3;\n\n    end else if (C_EN_SAFETY_CKT == 1 && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full_sckt\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end\n  endgenerate // grstd1\n\nendmodule //fifo_generator_v13_2_1_CONV_VER\n\n\nmodule fifo_generator_v13_2_1_sync_stage\n  #(\n    parameter  C_WIDTH          = 10\n   )\n   (\n    input                     RST,\n    input                     CLK,\n    input       [C_WIDTH-1:0] DIN,\n    output reg  [C_WIDTH-1:0] DOUT = 0\n   );\n   always @ (posedge RST or posedge CLK) begin\n     if (RST)\n       DOUT <= 0;\n     else\n       DOUT <= #`TCQ DIN;\n   end\nendmodule // fifo_generator_v13_2_1_sync_stage\n\n/*******************************************************************************\n * Declaration of Independent-Clocks FIFO Module\n ******************************************************************************/\nmodule fifo_generator_v13_2_1_bhv_ver_as\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2 \n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input                                         SAFETY_CKT_WR_RST,\n   input                                         SAFETY_CKT_RD_RST,\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_ASSERT,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_NEGATE,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_ASSERT,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_NEGATE,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         RD_EN_USER,\n   input                                         RST,\n   input                                         RST_FULL_GEN,\n   input                                         RST_FULL_FF,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   input                                         INJECTDBITERR,\n   input                                         INJECTSBITERR,\n   input                                         USER_EMPTY_FB,\n   input                                         fab_read_data_valid_i,\n   input                                         read_data_valid_i,\n   input                                         ram_valid_i,\n   output reg                                    ALMOST_EMPTY = 1'b1,\n   output reg                                    ALMOST_FULL = C_FULL_FLAGS_RST_VAL,\n   output      [C_DOUT_WIDTH-1:0]                DOUT,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    EMPTY_FB = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL,\n   output                                        OVERFLOW,\n   output                                        PROG_EMPTY,\n   output                                        PROG_FULL,\n   output                                        VALID,\n   output      [C_RD_DATA_COUNT_WIDTH-1:0]       RD_DATA_COUNT,\n   output                                        UNDERFLOW,\n   output                                        WR_ACK,\n   output      [C_WR_DATA_COUNT_WIDTH-1:0]       WR_DATA_COUNT,\n   output                                        SBITERR,\n   output                                        DBITERR\n  );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   \n  \n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   \n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;\n   // Array that holds the error injection type (single/double bit error) on \n   // a specific write operation, which is returned on read to corrupt the\n   // output data.\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   //The amount of data stored in the FIFO at any time is given\n   // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK\n   // domain.\n   //num_wr_bits is calculated by considering the total words in the FIFO,\n   // and the state of the read pointer (which may not have yet crossed clock\n   // domains.)\n   //num_rd_bits is calculated by considering the total words in the FIFO,\n   // and the state of the write pointer (which may not have yet crossed clock\n   // domains.)\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   wire                        wr_rst_i = WR_RST;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n   wire                        rd_rst_i = RD_RST;\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n\n\n\n   // Delayed ram_rd_en is needed only for STD Embedded register option\n   generate\n     if (C_PRELOAD_LATENCY == 2) begin : grd_d\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n       end\n     end\n   endgenerate\n   \n    generate\n     if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n           fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n       end\n     end\n   endgenerate\n\n  \n\n   // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;\n     end else begin : rdl // Read depth lesser than or equal to write depth\n       assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n     end\n   endgenerate\n\n   // Generate Empty and Almost Empty\n  // ram_rd_en used to determine EMPTY should depend on the EMPTY.\n   assign ram_rd_en        = RD_EN & !EMPTY;\n   assign empty_int        = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));\n   assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));\n\n   // Register Empty and Almost Empty\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else begin\n         rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};\n\n         if (empty_int)\n           EMPTY           <= #`TCQ 1'b1;\n         else\n           EMPTY           <= #`TCQ 1'b0;\n\n         if (!EMPTY) begin\n           if (almost_empty_int)\n             ALMOST_EMPTY  <= #`TCQ 1'b1;\n           else\n             ALMOST_EMPTY  <= #`TCQ 1'b0;\n         end\n       end // rd_rst_i\n     end // always\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY_FB     <= 1'b1;\n       end else begin\n         if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else if (empty_int)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else\n           EMPTY_FB   <= #`TCQ 1'b0;\n       end // rd_rst_i\n     end // always\n\n   // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;\n     end else begin : wdl // Write depth lesser than or equal to read depth\n       assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n     end\n   endgenerate\n\n  // Generate FULL and ALMOST_FULL\n  // ram_wr_en used to determine FULL should depend on the FULL.\n  assign ram_wr_en       = WR_EN & !FULL;\n  assign full_int        = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));\n  assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));\n\n   // Register FULL and ALMOST_FULL Empty\n   always @ (posedge WR_CLK or posedge RST_FULL_FF)\n     begin\n       if (RST_FULL_FF & C_HAS_RST) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else begin\n         if (full_int) begin\n           FULL           <= #`TCQ 1'b1;\n         end else begin\n           FULL           <= #`TCQ 1'b0;\n         end\n\n         if (RST_FULL_GEN) begin\n           ALMOST_FULL    <= #`TCQ 1'b0;\n         end else if (!FULL) begin\n           if (almost_full_int)\n             ALMOST_FULL  <= #`TCQ 1'b1;\n           else\n             ALMOST_FULL  <= #`TCQ 1'b0;\n         end\n       end // wr_rst_i\n     end // always\n   always @ (posedge WR_CLK or posedge wr_rst_i)\n     begin\n       if (wr_rst_i) begin\n         wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};\n       end else begin\n         wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};\n       end // wr_rst_i\n     end // always\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i) begin\n           stage1_valid     <= 0;\n           stage2_valid     <= 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n   //Pointers passed into opposite clock domain\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_EMPTY.\n   wire [31:0] num_read_words_pe = \n     num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_FULL.\n   wire [31:0] num_write_words_pf =\n     num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n    \n    \n   /***************************************************************************\n    * Internal registers and wires\n    **************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire [C_DOUT_WIDTH-1:0] ideal_dout_out;      \n   wire valid_i;\n   wire valid_out1;\n   wire valid_out2;\n   wire valid_out;  \n   wire underflow_i;\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]               err_type                 = 0;\n   reg [1:0]               err_type_d1              = 0;\n   reg [1:0]               err_type_both              = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout               = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_d1            = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_both            = 0;\n   reg                     ideal_wr_ack             = 0;\n   reg                     ideal_valid              = 0;\n   reg                     ideal_overflow           = C_OVERFLOW_LOW;\n   reg                     ideal_underflow          = C_UNDERFLOW_LOW;\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   reg         valid_d1     = 0;\n   reg         valid_d2     = 0; \n   \n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n   \n\n  /****************************************************************************\n   * Function Declarations\n   ***************************************************************************/\n\n  /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n      if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n    end\n  endtask\n\n  /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n  /***********************************************************************\n  * hexstr_conv\n  *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n  ***********************************************************************/\n  function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_d2           = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n    end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the \n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n    wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;   \n   wire RD_CLK;\n   wire RD_EN;\n   wire RST;\n   wire WR_CLK;\n   wire WR_EN;\n    */\n\n   //***************************************************************************\n   // Dout may change behavior based on latency\n   //***************************************************************************\n   assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?\n                         ideal_dout_d1: ideal_dout;   \n   assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; \n\n   //***************************************************************************\n   // Assign SBITERR and DBITERR based on latency \n   //***************************************************************************\n   assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                    (C_PRELOAD_LATENCY == 2 &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?\n                    err_type_d1[0]: err_type[0]; \n   assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                    (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                    err_type_d1[1]: err_type[1]; \n  \n   //***************************************************************************\n   // Safety-ckt logic with embedded reg/fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n       //  if (C_HAS_VALID == 1) begin\n       //       assign valid_out = valid_d1;\n       //  end\n             \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)\n          begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else \n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n          end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                  @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n           end\n           else begin\n                   if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                   end\n             end \n           end  \n      end \n      endgenerate   \n\n//***************************************************************************\n   // Safety-ckt logic with embedded reg + fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else begin\n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n               fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n          end\n        end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   ideal_dout_both <= #`TCQ dout_reset_val;\n              end\n           end else begin\n             if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n              \n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n             end\n           end \n         end      \n      end \n      endgenerate    \n \n   //***************************************************************************\n   // Overflow may be active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_OVERFLOW==1) begin : blockOF1\n   assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n      end\n   endgenerate\n\n   assign PROG_EMPTY = ideal_prog_empty;\n   assign PROG_FULL  = ideal_prog_full;\n\n   //***************************************************************************\n   // Valid may change behavior based on latency or active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_VALID==1) begin : blockVL1\n   assign valid_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;\n   assign valid_out1 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?\n                       valid_d1: valid_i;  \n   assign valid_out2 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?\n                       valid_d2: valid_i; \n   assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;\n   assign VALID     = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Underflow may change behavior based on latency or active-low   \n   //***************************************************************************\n   generate\n      if (C_HAS_UNDERFLOW==1) begin : blockUF1\n   assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;\n   assign UNDERFLOW   = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n    end\n   endgenerate\n\n   //***************************************************************************\n   // Write acknowledge may be active low\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_ACK==1) begin : blockWK1\n   assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext\n\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_wr_pntr = 0;\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_rd_pntr = 0;\n      wire [C_PNTR_WIDTH-1:0]  diff_wr_rd_tmp;\n      wire [C_PNTR_WIDTH:0]    diff_wr_rd;\n      reg  [C_PNTR_WIDTH:0]    wr_data_count_i  = 0;\n        always @* begin\n          if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = 0;\n            adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n          end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin\n            adjusted_rd_pntr = rd_pntr_wr;\n            adjusted_wr_pntr = 0;\n            adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n          end else begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = rd_pntr_wr;\n          end\n        end // always @*\n\n        assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;\n        assign diff_wr_rd     = {1'b0,diff_wr_rd_tmp};\n\n        always @ (posedge wr_rst_i or posedge WR_CLK)\n        begin\n            if (wr_rst_i)\n              wr_data_count_i <= 0;\n            else\n              wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;\n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n\n        always @* begin\n          if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];\n          else\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n        end // always @*\n      end // wdc_fwft_ext\n   endgenerate\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   reg  [C_RD_PNTR_WIDTH:0]    rdc_fwft_ext_as  = 0;\n\n   generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n\n\n   always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= 0;\n            end else begin\n              if (!stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 0;\n              else if (!stage1_valid && stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 1;\n              else\n                rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;\n            end \n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n      end // rdc_fwft_ext\n end\n   endgenerate\n\n\n  generate if (C_USE_EMBEDDED_REG == 3) begin\n     if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n        wire [C_RD_PNTR_WIDTH:0]  diff_rd_wr_1;\n   //     assign diff_rd_wr_1 = diff_rd_wr +2'h2;\n\n       always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= #`TCQ 0;\n            end else begin\n          //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))\n          //    rdc_fwft_ext_as <= 1'b0;\n          //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) \n          //    rdc_fwft_ext_as <= 1'b1;\n          //else\n            rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;\n        end\n\n\n\nend\nend\nend\nendgenerate\n          \n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1) begin : grdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?\n          rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :\n          rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?\n          wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :\n          wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n\n  /**************************************************************************\n  * Assorted registers for delayed versions of signals\n  **************************************************************************/\n  //Capture delayed version of valid\n  generate\n      if (C_HAS_VALID==1) begin : blockVL2\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n      valid_d1 <= 1'b0;\n      valid_d2 <= 1'b0;\n    end else begin\n      valid_d1 <= #`TCQ valid_i;\n      valid_d2 <= #`TCQ valid_d1;\n    end \n//    if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin\n  //      valid_d2 <= #`TCQ valid_d1;\n      //  end \n  end \n      end\n endgenerate  \n   \n  //Capture delayed version of dout\n  /**************************************************************************\n    *embedded/fabric reg with no safety ckt\n    **************************************************************************/\n  generate \n       if (C_USE_EMBEDDED_REG < 3) begin\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n       if (C_USE_DOUT_RST == 1'b1) begin\n         @(posedge RD_CLK)\n           ideal_dout_d1   <= #`TCQ dout_reset_val;\n           ideal_dout   <= #`TCQ dout_reset_val;\n       end\n      // Reset err_type only if ECC is not selected\n      if (C_USE_ECC == 0)\n        err_type_d1     <= #`TCQ 0;\n     end else if (ram_rd_en_d1) begin\n      ideal_dout_d1   <= #`TCQ ideal_dout;\n      err_type_d1     <= #`TCQ err_type;\n           end    \n  end  \n   \nend  \nendgenerate \n/**************************************************************************\n    *embedded + fabric reg with no safety ckt\n    **************************************************************************/\n\ngenerate \n  if (C_USE_EMBEDDED_REG == 3) begin\n    always @(posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i == 1'b1) begin\n        if (C_USE_DOUT_RST == 1'b1) begin\n           @(posedge RD_CLK)\n             ideal_dout    <= #`TCQ dout_reset_val;\n             ideal_dout_d1   <= #`TCQ dout_reset_val;\n             ideal_dout_both   <= #`TCQ dout_reset_val;\n        end\n        // Reset err_type only if ECC is not selected\n        if (C_USE_ECC == 0) begin\n          err_type_d1     <= #`TCQ 0;\n          err_type_both   <= #`TCQ 0;\n        end\n      end else begin\n         if (ram_rd_en_d1) begin\n           ideal_dout_both   <= #`TCQ ideal_dout;\n           err_type_both     <= #`TCQ err_type;\n         end    \n         if (fab_rd_en_d1) begin\n           ideal_dout_d1   <= #`TCQ ideal_dout_both;\n           err_type_d1     <= #`TCQ err_type_both;\n         end\n      end\n    end  \n  end  \nendgenerate \n\n  \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate\n     if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n       always @(posedge WR_CLK) begin\n         ideal_overflow    <= #`TCQ WR_EN & FULL;\n       end\n     end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n       always @(posedge WR_CLK) begin\n         //ideal_overflow    <= #`TCQ WR_EN & (FULL | wr_rst_i);\n         ideal_overflow    <= #`TCQ WR_EN & (FULL );\n       end\n     end\n   endgenerate\n\n   generate\n     if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ EMPTY & RD_EN;\n       end\n     end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ (EMPTY) & RD_EN;\n         //ideal_underflow    <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;\n       end\n     end\n   endgenerate\n\n   /**************************************************************************\n   * Write/Read Pointer Synchronization\n   **************************************************************************/\n   localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;\n   wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   genvar gss;\n\n   generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst\n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (C_WR_PNTR_WIDTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_i), \n         .CLK      (RD_CLK), \n         .DIN      (wr_pntr_sync_stgs[gss-1]), \n         .DOUT     (wr_pntr_sync_stgs[gss])\n        );\n \n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (C_RD_PNTR_WIDTH)\n        )\n     wr_stg_inst\n        (\n         .RST      (wr_rst_i), \n         .CLK      (WR_CLK), \n         .DIN      (rd_pntr_sync_stgs[gss-1]), \n         .DOUT     (rd_pntr_sync_stgs[gss])\n        );\n   end endgenerate // Sync_stage_inst\n\n   assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;\n   assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;\n   always@* begin\n     wr_pntr_rd           <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n     rd_pntr_wr           <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n   end\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp\n     if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)\n       wr_pntr           <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)\n       wr_pntr           <= #`TCQ 0;\n   end\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (wr_rst_i == 1'b1) begin\n       num_wr_bits       <= 0;\n       next_num_wr_bits   = 0;\n       wr_ptr            <= C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= C_RD_DEPTH - 1;\n       ideal_wr_ack      <= 0;\n       ideal_wr_count    <= 0;\n       tmp_wr_listsize    = 0;\n       rd_ptr_wrclk_next <= 0;\n       wr_pntr_rd1       <= 0;\n\n     end else begin //wr_rst_i==0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       //If this is a write, handle the write by adding the value\n       // to the linked list, and updating all outputs appropriately\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD \n             >= C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full, but reporting full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //With DEPTH-1 words in the FIFO, it is almost_full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n\n           //If the FIFO is completely empty, but it is\n           // reporting FULL for some reason (like reset)\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=\n                C_FIFO_WR_DEPTH-2) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //FIFO is really not close to full, so change flag status.\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n           end //(tmp_wr_listsize == 0)\n\n         end else begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=\n              C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack       <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count     <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;\n\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //This write is CAUSING the FIFO to go full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is 2 from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == \n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits =  next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Still 2 from full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is not close to being full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <\n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //wr_rst_i==0\n   end // gen_fifo_w\n\n\n  /***************************************************************************\n   * Programmable FULL flags\n   ***************************************************************************/\n\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;\n\n   generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;\n   end else begin // STD\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;\n   end endgenerate\n\n   always @(posedge WR_CLK or posedge wr_rst_i) begin\n\n     if (wr_rst_i == 1'b1) begin\n       diff_pntr         <= 0;\n     end else begin\n       if (ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);\n       else if (!ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);\n    end\n  end\n\n\n   always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf\n\n     if (RST_FULL_FF & C_HAS_RST) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else begin\n\n       if (RST_FULL_GEN)\n         ideal_prog_full   <= #`TCQ 0;\n       //Single Programmable Full Constant Threshold\n       else if (C_PROG_FULL_TYPE == 1) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else\n             ideal_prog_full <= #`TCQ 0;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Constant Thresholds\n       end else if (C_PROG_FULL_TYPE == 2) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else if (diff_pntr < pf_thr_negate_val)\n             ideal_prog_full <= #`TCQ 0;\n           else\n             ideal_prog_full <= #`TCQ ideal_prog_full;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Single Programmable Full Threshold Input\n       end else if (C_PROG_FULL_TYPE == 3) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH)\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Threshold Inputs\n       end else if (C_PROG_FULL_TYPE == 4) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH_ASSERT)\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < PROG_FULL_THRESH_NEGATE)\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       end // C_PROG_FULL_TYPE\n\n     end //wr_rst_i==0\n   end //\n\n   \n   /**************************************************************************\n   * Read Domain Logic\n   **************************************************************************/\n\n\n   /*********************************************************\n    * Programmable EMPTY flags\n    *********************************************************/\n   //Determine the Assert and Negate thresholds for Programmable Empty\n\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd      = 0;\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe\n\n     if (rd_rst_i & C_HAS_RST) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else begin\n       if (ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;\n       else if (!ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr);\n       else\n         diff_pntr_rd       <=  #`TCQ diff_pntr_rd;\n  \n       if (C_PROG_EMPTY_TYPE == 1) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 2) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 3) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 4) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end  //C_PROG_EMPTY_TYPE\n     end\n   end // gen_pe\n\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;\n   end endgenerate // single_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;\n   end endgenerate // multiple_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;\n   end endgenerate // single_multiple_pe_thr_const\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp\n     if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n       rd_pntr            <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)\n       rd_pntr            <= #`TCQ 0;\n   end\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rd_rst_i & C_HAS_RST) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n     end else begin //rd_rst_i==0\n\n       rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 1\n       /*****************************************************************/\n       if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Reminder that FIFO is still empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end // if (tmp_rd_listsize <= 0)\n\n             //If the FIFO is one from empty, but it is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 1)\n\n             //If the FIFO is two from empty, and is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Fifo has two words, so is neither empty or almost empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 2)\n\n             //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid <= #`TCQ 1'b0;\n                 //Note that the FIFO is No Longer Empty or Almost Empty\n\n                 ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n               end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n             end // else: if(ideal_empty == 1'b1)\n\n           else //if (ideal_empty == 1'b0)\n             begin\n\n               //If the FIFO is completely full, and we are successfully reading from it\n               if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)\n\n               //If the FIFO is not close to being empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n               //If the FIFO is two from empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Fifo is not yet empty. It is going almost_empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n\n               //If the FIFO is one from empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Note that FIFO is GOING empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 1)\n\n\n               //If the FIFO is completely empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n                 begin\n                   //Do not change the contents of the FIFO\n\n                   //Do not acknowledge the read from empty FIFO\n                   ideal_valid        <= #`TCQ 1'b0;\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize <= 0)\n\n             end // if (ideal_empty == 1'b0)\n\n           end //(RD_EN == 1'b1)\n\n         else //if (RD_EN == 1'b0)\n           begin\n             //If user did not attempt a read, do not give an ack or err\n             ideal_valid          <= #`TCQ 1'b0;\n\n             ideal_rd_count       <= #`TCQ num_read_words_sized_i;\n\n           end // else: !if(RD_EN == 1'b1)\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 0\n       /*****************************************************************/\n       end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty, but it is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty, and is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Fifo has two words, so is neither empty or almost empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                         (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that the FIFO is No Longer Empty or Almost Empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n           end else begin\n\n             //If the FIFO is completely full, and we are successfully reading from it\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is not close to being empty\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                          (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Fifo is not yet empty. It is going almost_empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Note that FIFO is GOING empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is completely empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if (tmp_rd_listsize <= 0)\n\n           end // if (ideal_empty == 1'b0)\n\n         end else begin//(RD_EN == 1'b0)\n\n         \n           //If user did not attempt a read, do not give an ack or err\n           ideal_valid           <= #`TCQ 1'b0;\n           ideal_rd_count        <= #`TCQ num_read_words_sized_i;\n\n         end // else: !if(RD_EN == 1'b1)\n       end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //rd_rst_i==0\n   end //always gen_fifo_r_as\n\nendmodule // fifo_generator_v13_2_1_bhv_ver_as\n\n\n/*******************************************************************************\n * Declaration of Low Latency Asynchronous FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_1_beh_ver_ll_afifo\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_FIFO_TYPE                    = 0\n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   output reg  [C_DOUT_WIDTH-1:0]                DOUT = 0,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL\n  );\n\n  //-----------------------------------------------------------------------------\n  // Low Latency Asynchronous FIFO\n  //-----------------------------------------------------------------------------\n\n  // Memory which will be used to simulate a FIFO\n  reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n  integer i;\n  initial begin\n    for (i = 0; i < C_WR_DEPTH; i = i + 1)\n      memory[i] = 0;\n  end\n\n  reg  [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;\n  wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;\n  reg  [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;\n  reg                        ll_afifo_full    = 1'b0;\n  reg                        ll_afifo_empty   = 1'b1;\n  wire                       write_allow;\n  wire                       read_allow;\n\n  assign write_allow = WR_EN & ~ll_afifo_full;\n  assign read_allow  = RD_EN & ~ll_afifo_empty;\n\n  //-----------------------------------------------------------------------------\n  // Write Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      wr_pntr_ll_afifo   <= 0;\n    else if (write_allow)\n      wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Read Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      rd_pntr_ll_afifo_q   <= 0;\n    else\n      rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;\n  end\n  assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;\n  \n  //-----------------------------------------------------------------------------\n  // Fill the Memory\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK) begin\n    if (write_allow)\n      memory[wr_pntr_ll_afifo] <= #`TCQ DIN;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate DOUT\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK) begin\n      DOUT <= #`TCQ memory[rd_pntr_ll_afifo];\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate EMPTY\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      ll_afifo_empty   <= 1'b1;\n    else\n      ll_afifo_empty   <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | \n                           (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate FULL\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      ll_afifo_full   <= 1'b1;\n    else\n      ll_afifo_full   <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | \n                           (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));\n  end\n\n  always @* begin\n    FULL  <= ll_afifo_full;\n    EMPTY <= ll_afifo_empty;\n  end\n\nendmodule // fifo_generator_v13_2_1_beh_ver_ll_afifo\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_v13_2_1_bhv_ver_ss\n   \n  /**************************************************************************\n   * Declare user parameters and their defaults\n   *************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0 \n   )\n   \n  /**************************************************************************\n   * Declare Input and Output Ports\n   *************************************************************************/\n   (\n    //Inputs\n    input                                 SAFETY_CKT_WR_RST,\n    input                                 CLK,\n    input       [C_DIN_WIDTH-1:0]         DIN,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_ASSERT,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_NEGATE,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_ASSERT,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_NEGATE,\n    input                                 RD_EN,\n    input                                 RD_EN_USER,\n    input                                 USER_EMPTY_FB,\n    input                                 RST,\n    input                                 RST_FULL_GEN,\n    input                                 RST_FULL_FF,\n    input                                 SRST,\n    input                                 WR_EN,\n    input                                 INJECTDBITERR,\n    input                                 INJECTSBITERR,\n    input                                 WR_RST_BUSY,\n    input                                 RD_RST_BUSY,\n                                    \n    //Outputs                       \n    output                                ALMOST_EMPTY,\n    output                                ALMOST_FULL,\n    output reg   [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,\n    output       [C_DOUT_WIDTH-1:0]       DOUT,\n    output                                EMPTY,\n    output reg                            EMPTY_FB = 1'b1,\n    output                                FULL,\n    output                                OVERFLOW,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]    RD_DATA_COUNT,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]    WR_DATA_COUNT,\n    output                                PROG_EMPTY,\n    output                                PROG_FULL,\n    output                                VALID,\n    output                                UNDERFLOW,\n    output                                WR_ACK,\n    output                                SBITERR,\n    output                                DBITERR\n   );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;\n   wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n   localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; \n\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n   localparam  EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //localparam  EXTRA_WORDS_PE_PARAM  = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not \n   //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.\n   // Therefore, during SRST, all the FULL flags reset to 0.\n   localparam                      C_HAS_FAST_FIFO = 0;\n   localparam                      C_FIFO_WR_DEPTH = C_WR_DEPTH;\n   localparam                      C_FIFO_RD_DEPTH = C_RD_DEPTH;\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;\n   localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;\n   localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;\n   localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n  localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; \n  localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; \n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   \n   /**************************************************************************\n    * Internal Registers and wires\n    *************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire                           underflow_i;\n   wire                           valid_i;\n   wire                           valid_out;\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_reg = 1'b0;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n   wire                         srst_rrst_busy;\n\n\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]                      err_type           = 0;\n   reg [1:0]                      err_type_d1        = 0;\n   reg [1:0]                      err_type_both      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout         = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_d1      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_both      = 0;\n   wire [C_DOUT_WIDTH-1:0]        ideal_dout_out;\n   wire                           fwft_enabled;\n   reg                            ideal_wr_ack       = 0;\n   reg                            ideal_valid        = 0;\n   reg                            ideal_overflow     = C_OVERFLOW_LOW;\n   reg                            ideal_underflow    = C_UNDERFLOW_LOW;\n\n   reg                            full_i             = C_FULL_FLAGS_RST_VAL;\n   reg                            full_i_temp        = 0;\n   reg                            empty_i            = 1;\n   reg                            almost_full_i      = 0;\n   reg                            almost_empty_i     = 1;\n   reg                            prog_full_i        = 0;\n   reg                            prog_empty_i       = 1;\n   reg [C_WR_PNTR_WIDTH-1:0]      wr_pntr            = 0;\n   reg [C_RD_PNTR_WIDTH-1:0]      rd_pntr            = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg [C_RD_PNTR_WIDTH-1:0]      diff_count         = 0;\n\n   reg                            write_allow_q      = 0;\n   reg                            read_allow_q       = 0;\n   reg                            valid_d1           = 0;\n   reg                            valid_both           = 0;\n   reg                            valid_d2           = 0;\n   wire                           rst_i;\n   wire                           srst_i;\n\n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]         dout_reset_val = 0;\n\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n\n\n\n   /****************************************************************************\n    * Function Declarations\n    ***************************************************************************/\n\n   /****************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***************************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin\n        case (def_data[7:0])\n          8'b00000000 : begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default : begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1) begin\n          if ((index*4)+j < C_DOUT_WIDTH) begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   //reg         valid_d1     = 0;\n   \n   \n   //user specified value for reseting the size of the fifo\n   //reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n\n\n /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n     if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n\n     end\n  endtask\n\n\n   \n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_dout_both    = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_both         = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n\n   end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the\n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n   wire CLK;\n   wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;\n   wire RD_EN;\n   wire RST;\n   wire WR_EN;\n    */\n\n  // Assign ALMOST_EPMTY\n  generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae\n    assign ALMOST_EMPTY = almost_empty_i;\n  end else begin : gnae\n    assign ALMOST_EMPTY = 0;\n  end endgenerate // gae\n\n  // Assign ALMOST_FULL\n  generate if (C_HAS_ALMOST_FULL==1) begin : gaf\n    assign ALMOST_FULL  = almost_full_i;\n  end else begin : gnaf\n    assign ALMOST_FULL  = 0;\n  end endgenerate // gaf\n\n   // Dout may change behavior based on latency\n  localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?\n                         ideal_dout_d1: ideal_dout; \n  assign DOUT = ideal_dout_out;\n\n  // Assign SBITERR and DBITERR based on latency \n  assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[0]: err_type[0]; \n  assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[1]: err_type[1]; \n\n  assign EMPTY         = empty_i;\n  assign FULL          = full_i;\n  //saftey_ckt with one register\n\n  generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)\n          begin\n          if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n              valid_d1 <= #`TCQ 1'b0;\n          end\n          else begin\n               ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n               valid_d1 <= #`TCQ valid_i;\n          end\n          end\n          \n           always@(posedge rst_delayed_sft2 or posedge CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n              end\n           else if (srst_rrst_busy == 1'b1) begin\n                   if (C_USE_DOUT_RST == 1'b1) begin\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   end\n           end else if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                end\n           end   \n      end //if \n      endgenerate   \n\n//safety ckt with both registers\n\ngenerate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK) begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            valid_d1 <= #`TCQ 1'b0;\n          end else begin\n            ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n            fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n            valid_both <= #`TCQ valid_i;\n            valid_d1 <= #`TCQ valid_both;\n          end\n        end\n\n        always@(posedge rst_delayed_sft2 or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                  ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else if (srst_rrst_busy == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else begin \n            if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n            end\n          end\n        end\n      end //if \n      endgenerate    \n \n \n  //Overflow may be active-low\n  generate if (C_HAS_OVERFLOW==1) begin : gof\n    assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n  end else begin : gnof\n    assign OVERFLOW = 0;\n  end endgenerate // gof\n\n  assign PROG_EMPTY    = prog_empty_i;\n  assign PROG_FULL     = prog_full_i;\n\n   //Valid may change behavior based on latency or active-low\n  generate if (C_HAS_VALID==1) begin : gvalid\n    assign valid_i       = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;\n    assign valid_out     = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?\n                            valid_d1 : valid_i; \n    assign VALID         = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n  end else begin : gnvalid\n    assign VALID         = 0;\n  end endgenerate // gvalid\n\n  //Trim data count differently depending on set widths\n  generate if (C_HAS_DATA_COUNT == 1) begin : gdc\n    always @* begin\n      diff_count <= wr_pntr - rd_pntr;\n      if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin\n        DATA_COUNT[C_RD_PNTR_WIDTH-1:0]  <= diff_count;\n        DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; \n      end else begin\n        DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];\n      end\n    end\n//  end else begin : gndc\n//    always @* DATA_COUNT <= 0;\n  end endgenerate // gdc\n\n  //Underflow may change behavior based on latency or active-low\n  generate if (C_HAS_UNDERFLOW==1) begin : guf\n    assign underflow_i   = ideal_underflow;\n    assign UNDERFLOW     = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n  end else begin : gnuf\n    assign UNDERFLOW     = 0;\n  end endgenerate // guf\n \n\n  //Write acknowledge may be active low \n  generate if (C_HAS_WR_ACK==1) begin : gwr_ack\n    assign WR_ACK        = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n  end else begin : gnwr_ack\n    assign WR_ACK        = 0;\n  end endgenerate // gwr_ack\n\n\n  /*****************************************************************************\n   * Internal reset logic \n   ****************************************************************************/\n  assign srst_i        = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;\n  assign rst_i            = C_HAS_RST ? RST : 0;\n  assign srst_wrst_busy   = srst_i;\n  assign srst_rrst_busy   = srst_i;\n\n   /**************************************************************************\n    * Assorted registers for delayed versions of signals\n    **************************************************************************/\n   //Capture delayed version of valid\n   generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20\n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1 <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n           end else begin\n              valid_d1 <= #`TCQ valid_i;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n     end \n   endgenerate // blockVL20\n\n  generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin \n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1   <= 1'b0;\n           valid_both <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n              valid_both <= #`TCQ 1'b0;\n              \n           end else begin\n              valid_both <= #`TCQ valid_i;\n               valid_d1 <= #`TCQ valid_both;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n  end\n endgenerate // blockVL20\n\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge CLK or posedge rst_i) begin\n         if (rst_i) begin\n           stage1_valid     <= #`TCQ 0;\n           stage2_valid     <= #`TCQ 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n\n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc\n       assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc\n       assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n   \n   //reg ram_rd_en_d1 = 1'b0;\n   //Capture delayed version of dout\n   generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         ram_rd_en_d1 <= #`TCQ 1'b0;\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n        end\n      end else begin\n         ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n         if (srst_rrst_busy) begin\n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            // Reset err_type only if ECC is not selected\n            if (C_USE_ECC == 0) begin\n               err_type_d1   <= #`TCQ 0;\n               err_type_both <= #`TCQ 0;\n            end\n            // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n            if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n            end \n         if (C_USE_DOUT_RST == 1) begin\n           // @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         end else begin\n            if (ram_rd_en_d1 ) begin\n            ideal_dout_d1 <= #`TCQ ideal_dout;\n            err_type_d1   <= #`TCQ err_type;\n            end\n         end\n      end    \n   end   // always\nend\nendgenerate \n\n//no safety ckt with both registers\n generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n          ram_rd_en_d1 <= #`TCQ 1'b0;\n          fab_rd_en_d1 <= #`TCQ 1'b0;\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val; \n            \n      end\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val;\n       end\n      end else begin\n         if (srst_rrst_busy) begin \n           ram_rd_en_d1 <= #`TCQ 1'b0;\n           fab_rd_en_d1 <= #`TCQ 1'b0;\n           // Reset err_type only if ECC is not selected\n           if (C_USE_ECC == 0) begin\n              err_type_d1   <= #`TCQ 0;\n              err_type_both <= #`TCQ 0;\n           end\n           // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n           if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n              ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end \n           if (C_USE_DOUT_RST == 1) begin\n             ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end\n         end else begin\n           ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n           fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);\n           if (ram_rd_en_d1 ) begin\n             ideal_dout_both <= #`TCQ ideal_dout;\n             err_type_both   <= #`TCQ err_type;\n           end\n           if (fab_rd_en_d1 ) begin\n             ideal_dout_d1 <= #`TCQ ideal_dout_both;\n             err_type_d1   <= #`TCQ err_type_both;\n           end\n         end\n      end    \n   end   // always\nend\nendgenerate \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n     always @(posedge CLK) begin\n       ideal_overflow    <= #`TCQ WR_EN & full_i;\n     end\n   end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n     always @(posedge CLK) begin\n       //ideal_overflow    <= #`TCQ WR_EN & (rst_i | full_i);\n       ideal_overflow    <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);\n     end\n   end endgenerate // blockOF20\n \n   generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n     always @(posedge CLK) begin\n       ideal_underflow   <= #`TCQ empty_i & RD_EN;\n     end\n   end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n     always @(posedge CLK) begin\n       //ideal_underflow   <= #`TCQ (rst_i | empty_i) & RD_EN;\n       ideal_underflow   <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;\n     end\n   end endgenerate // blockUF20\n\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n\n  /*************************************************************************\n   * Write and Read Logic  \n   ************************************************************************/\n   wire              write_allow;\n   wire              read_allow;\n   wire              read_allow_dc;\n   wire              write_only;\n   wire              read_only;\n   //wire              write_only_q;\n   reg              write_only_q;\n   //wire              read_only_q;\n   reg              read_only_q;\n   reg              full_reg;\n   reg              rst_full_ff_reg1;\n   reg              rst_full_ff_reg2;\n   wire              ram_full_comb;\n   wire              carry;\n   \n   assign write_allow  = WR_EN & ~full_i;\n   assign read_allow   = RD_EN & ~empty_i;\n   assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;\n   //assign write_only   = write_allow & ~read_allow;\n   //assign write_only_q = write_allow_q;\n   //assign read_only    = read_allow    & ~write_allow;\n   //assign read_only_q  = read_allow_q ;\n   wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;\n   wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;\n   wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;\n\n   assign diff_pntr_pe_max = DIFF_MAX_RD;\n   assign diff_pntr_max = DIFF_MAX_WR;\n\n\n\n   generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym\n    assign write_only   = write_allow & ~read_allow;\n    assign read_only    = read_allow    & ~write_allow;\n    end endgenerate\n    generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd\n     assign read_only   = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;\n     assign write_only    = write_allow    & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n    generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr\n     assign read_only   = read_allow & ~(write_allow  & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n     assign write_only    = write_allow &  &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;\n    end endgenerate\n\n\n   //-----------------------------------------------------------------------------\n   // Write and Read pointer generation\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       wr_pntr         <= 0;\n       rd_pntr         <= 0;\n     end else begin\n       if (srst_i) begin\n         wr_pntr       <= #`TCQ 0;\n         rd_pntr       <= #`TCQ 0;\n       end else begin\n         if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;\n         if (read_allow)  rd_pntr <= #`TCQ rd_pntr + 1;\n       end\n     end\n   end\n\n   generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout\n   always @(posedge CLK) begin\n     if (write_allow) begin\n       if (ENABLE_ERR_INJECTION == 1)\n         memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};\n       else\n         memory[wr_pntr] <= #`TCQ DIN;\n     end\n   end\n\n   reg  [C_DATA_WIDTH-1:0] dout_tmp_q;\n   reg [C_DATA_WIDTH-1:0] dout_tmp = 0;\n   reg  [C_DATA_WIDTH-1:0] dout_tmp1 = 0;\n   always @(posedge CLK) begin\n     dout_tmp_q <= #`TCQ ideal_dout;\n   end\n\n\n\n     always @* begin\n       if (read_allow)\n         ideal_dout <= memory[rd_pntr];\n       else\n         ideal_dout <= dout_tmp_q;\n     end\n   end endgenerate // gll_dm_dout\n\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   assign ram_rd_en        = RD_EN & !EMPTY;\n\n   //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   generate if (C_FIFO_TYPE != 2) begin : gnll_din\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i == 1'b1) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n\n     end else begin //rst_i==0\n     if (srst_wrst_busy) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n     end else begin//srst_i=0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n         end else begin\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error  \n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           //end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //srst_i==0\n     end //wr_rst_i==0\n   end // gen_fifo_w\n    end endgenerate\n\n   generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout\n     always @(posedge CLK) begin\n       if (rst_i || srst_rrst_busy) begin\n         if (C_USE_DOUT_RST == 1) begin\n           ideal_dout <= #`TCQ dout_reset_val;\n           ideal_dout_both <= #`TCQ dout_reset_val;\n         end\n       end\n     end\n    end endgenerate\n\n\n\n\n   generate if (C_FIFO_TYPE != 2) begin : gnll_dout\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_r\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n\n     end else begin //rd_rst_i==0\n     if (srst_rrst_busy) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets synchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= #`TCQ 0;\n         err_type_both    <= #`TCQ 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n      end //srst_i\n      else begin\n\n       //rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n         if (RD_EN == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end \n           else \n             begin\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n         end\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //s_rst_i==0\n     end //rd_rst_i==0\n   end //always\n  end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate diff_pntr for PROG_FULL generation\n   // Generate diff_pntr_pe for PROG_EMPTY generation\n   //-----------------------------------------------------------------------------\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         write_only_q   <= 1'b0;\n         read_only_q    <= 1'b0;\n         diff_pntr_reg1       <= 0;\n         diff_pntr_pe_reg1    <= 0;\n         diff_pntr_reg2       <= 0;\n         diff_pntr_pe_reg2    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_rrst_busy) begin\n           read_only_q  <= #`TCQ 1'b0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n           diff_pntr_pe_reg2  <= #`TCQ 0;\n          end\n          if (srst_wrst_busy) begin\n           write_only_q <= #`TCQ 1'b0;\n           diff_pntr_reg1     <= #`TCQ 0;\n           diff_pntr_reg2     <= #`TCQ 0;\n          end\n         end else begin\n           write_only_q <= #`TCQ write_only;\n           read_only_q  <= #`TCQ read_only;\n           diff_pntr_reg2  <= #`TCQ diff_pntr_reg1;\n           diff_pntr_pe_reg2  <= #`TCQ diff_pntr_pe_reg1;\n\n           // Add 1 to the difference pointer value when only write happens.\n           if (write_only)  \n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;\n           else\n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;\n\n           // Add 1 to the difference pointer value when write or both write & read or no write & read happen.\n           if (read_only)  \n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;\n           else\n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;\n         end\n       end\n     end\n   assign diff_pntr_pe = diff_pntr_pe_reg1;\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow\n\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym\n    assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};\n    assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         diff_pntr_pe_asym    <= 0;\n         diff_pntr_reg1       <= 0;\n         full_reg             <= 0;\n         rst_full_ff_reg1     <= 1;\n         rst_full_ff_reg2     <= 1;\n         diff_pntr_pe_reg1    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_wrst_busy)\n           diff_pntr_reg1     <= #`TCQ 0;\n          if (srst_rrst_busy)\n           full_reg             <=  #`TCQ 0;\n           rst_full_ff_reg1     <=  #`TCQ 1;\n           rst_full_ff_reg2     <=  #`TCQ 1;\n           diff_pntr_pe_asym    <=  #`TCQ 0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n         end else begin\n             diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;\n             full_reg          <= #`TCQ full_i;\n             rst_full_ff_reg1  <=  #`TCQ RST_FULL_FF;\n             rst_full_ff_reg2  <=  #`TCQ rst_full_ff_reg1;\n           if (~full_i) begin  \n             diff_pntr_reg1 <=  #`TCQ wr_pntr - adj_rd_pntr_wr;\n          end\n         end\n       end\n     end\n   assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));\n   assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow_asym\n\n\n   //-----------------------------------------------------------------------------\n   // Generate FULL flag\n   //-----------------------------------------------------------------------------\n   wire                 comp0;\n   wire                 comp1;\n   wire                 going_full;\n   wire                 leaving_full;\n \n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin :  gpad \t\n    assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;\n    assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin :  gtrim \n    assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n  end endgenerate\n\n   assign comp1         = (adj_rd_pntr_wr == (wr_pntr + 1'b1));\n   assign comp0         = (adj_rd_pntr_wr == wr_pntr);\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp\n     assign going_full    = (comp1 & write_allow & ~read_allow);\n     assign leaving_full  = (comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym\n      assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp \n      assign going_full = (comp1 & write_allow & ~read_allow);\n      assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n\n   assign ram_full_comb = going_full | (~leaving_full & full_i);\n\n   generate if (C_HAS_RST == 1) begin : grst_full\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF & C_HAS_RST)\n         full_i   <= C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_SRST == 1) begin : gsrst_full\n     always @(posedge CLK) begin\n       if (srst_wrst_busy)\n         full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_full\n     always @(posedge CLK) begin\n         full_i   <= #`TCQ ram_full_comb;\n     end\n   end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate EMPTY flag\n   //-----------------------------------------------------------------------------\n   wire                 ecomp0;\n   wire                 ecomp1;\n   wire                 going_empty;\n   wire                 leaving_empty;\n   wire                 ram_empty_comb;\n\n  \n generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin :  pad \t\n    assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n    assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin :  trim \n    assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n  end endgenerate\n\n   assign ecomp1         = (adj_wr_pntr_rd == (rd_pntr + 1'b1));\n   assign ecomp0         = (adj_wr_pntr_rd == rd_pntr);\n\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp\n     assign going_empty    = (ecomp1 & ~write_allow & read_allow);\n     assign leaving_empty  = (ecomp0 & write_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp\n      assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp \n      assign going_empty = (ecomp1 & ~write_allow & read_allow);\n      assign leaving_empty =(ecomp0 & write_allow);\n    end endgenerate\n\n\n\n    assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);\n\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       empty_i  <= 1'b1;\n     else if (srst_rrst_busy)\n       empty_i  <= #`TCQ 1'b1;\n     else\n       empty_i  <= #`TCQ ram_empty_comb;\n    end\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       EMPTY_FB     <= 1'b1;\n     end else begin\n       if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))\n         EMPTY_FB   <= #`TCQ 1'b1;\n       else\n         EMPTY_FB   <= #`TCQ ram_empty_comb;\n     end\n   end // always\n\n   //-----------------------------------------------------------------------------\n   // Generate Read and write data counts for asymmetic common clock\n   //-----------------------------------------------------------------------------\n\n    reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; \n    wire [C_GRTR_PNTR_WIDTH :0] ratio; \n    wire decr_by_one;\n    wire incr_by_ratio;\n    wire incr_by_one;\n    wire decr_by_ratio;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n\n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr \n      assign ratio         = C_DEPTH_RATIO_RD;\n      assign decr_by_one   = (IS_FWFT == 1)? read_allow_dc : read_allow;\n      assign incr_by_ratio = write_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (decr_by_one) begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc - 1;\n           else\n\t    count_dc <= #`TCQ count_dc - 1  + ratio ;\n\t end\n\t else begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc + ratio ;\n\tend\n       end\n       end\n\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n\n    end endgenerate\n\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd \n      assign ratio         = C_DEPTH_RATIO_WR;\n      assign incr_by_one   = write_allow;\n      assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (incr_by_one) begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc + 1;\n           else\n\t    count_dc <= #`TCQ count_dc + 1  - ratio ;\n\t end\n\t else begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc - ratio ;\n\tend\n       end\n       end\n\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n\n    end endgenerate\n\n\n\n\n\n\n   //-----------------------------------------------------------------------------\n   // Generate WR_ACK flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_wr_ack  <= 1'b0;\n     else if (srst_wrst_busy)\n       ideal_wr_ack  <= #`TCQ 1'b0;\n     else if (WR_EN & ~full_i)\n       ideal_wr_ack  <= #`TCQ 1'b1;\n     else\n       ideal_wr_ack  <= #`TCQ 1'b0;\n    end\n\n   //-----------------------------------------------------------------------------\n   // Generate VALID flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_valid  <= 1'b0;\n     else if (srst_rrst_busy)\n       ideal_valid  <= #`TCQ 1'b0;\n     else if (RD_EN & ~empty_i)\n       ideal_valid  <= #`TCQ 1'b1;\n     else\n       ideal_valid  <= #`TCQ 1'b0;\n    end\n\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_FULL flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss\n\n     wire                 fcomp2;\n     wire                 going_afull;\n     wire                 leaving_afull;\n     wire                 ram_afull_comb;\n\n\n   assign fcomp2         = (adj_rd_pntr_wr == (wr_pntr + 2'h2));\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp\n     assign going_afull    = (fcomp2 & write_allow & ~read_allow);\n     assign leaving_afull  = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym\n      assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp \n      assign going_afull = (fcomp2 & write_allow & ~read_allow);\n      assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n     assign ram_afull_comb  = going_afull | (~leaving_afull & almost_full_i);\n\n\n    generate if (C_HAS_RST == 1) begin : grst_afull\n      always @(posedge CLK or posedge RST_FULL_FF) begin\n        if (RST_FULL_FF & C_HAS_RST)\n          almost_full_i   <= C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_SRST == 1) begin : gsrst_afull\n      always @(posedge CLK) begin\n        if (srst_wrst_busy)\n          almost_full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_afull\n      always @(posedge CLK) begin\n          almost_full_i   <= #`TCQ ram_afull_comb;\n      end\n    end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_EMPTY flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss\n\n     wire                 ecomp2;\n     wire                 going_aempty;\n     wire                 leaving_aempty;\n     wire                 ram_aempty_comb;\n      \n     assign ecomp2          = (adj_wr_pntr_rd == (rd_pntr + 2'h2));\n   \n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp\n     assign going_aempty    = (ecomp2 & ~write_allow & read_allow);\n     assign leaving_aempty  = (ecomp1 & write_allow & ~read_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp\n      assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp \n      assign going_aempty = (ecomp2 & ~write_allow & read_allow);\n      assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);\n    end endgenerate\n\n\n     assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);\n\n     always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         almost_empty_i  <= 1'b1;\n       else if (srst_rrst_busy)\n         almost_empty_i  <= #`TCQ 1'b1;\n       else\n         almost_empty_i  <= #`TCQ ram_aempty_comb;\n      end\n  // end endgenerate // gae_ss\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL\n   //-----------------------------------------------------------------------------\n\n   localparam  C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT \n                                  C_PROG_FULL_THRESH_ASSERT_VAL; // STD\n   localparam  C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT\n                                  C_PROG_FULL_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;   \n   generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin \n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n          prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr>= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  ((diff_pntr) < C_PF_ASSERT_VAL )\n        prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate // single_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr >= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n       else if  (diff_pntr < C_PF_NEGATE_VAL)\n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate //multiple_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT\n                                               PROG_FULL_THRESH; // STD\n   generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input\n\n     always @(posedge CLK or posedge RST_FULL_FF) begin//0\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin //1\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin//2 \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin//3\n           if (diff_pntr > pf3_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if (diff_pntr == pf3_assert_val) begin//4\n             if (read_only_q)\n               prog_full_i <= #`TCQ 1'b0;\n             else\n               prog_full_i <= #`TCQ 1'b1;\n           end else//4\n             prog_full_i <= #`TCQ 1'b0;\n         end else//3\n           prog_full_i <= #`TCQ prog_full_i;\n       end //2\n       else begin//5\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin//6 \n        if (diff_pntr >= pf3_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  (diff_pntr < pf3_assert_val) begin//7\n         prog_full_i <= #`TCQ 1'b0;\n       end//7\n       end//6\n      else\n           prog_full_i <= #`TCQ prog_full_i;\n       end//5\n     end//1\n     end//0\n   end endgenerate //single_pf_input\n  \n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_ASSERT; // STD\n   wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_NEGATE; // STD\n\n   generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin\n           if (diff_pntr >= pf_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if ((diff_pntr == pf_negate_val && read_only_q) ||\n                  diff_pntr < pf_negate_val)\n             prog_full_i <= #`TCQ 1'b0;\n           else\n             prog_full_i <= #`TCQ prog_full_i;\n         end else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin \n        if (diff_pntr >= pf_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n       else if (diff_pntr < pf_negate_val) \n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n\n     end\n   end\n   end endgenerate //multiple_pf_inputs\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY\n   //-----------------------------------------------------------------------------\n   localparam  C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD\n   localparam  C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i) \n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy) \n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL)\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > C_PE_ASSERT_VAL)\n         prog_empty_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n     end\n     end\n   end endgenerate // single_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > C_PE_NEGATE_VAL) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n\n     end\n\n     end\n   end endgenerate //multiple_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH -2) : // FWFT\n                                                PROG_EMPTY_THRESH; // STD\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe < pe3_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (diff_pntr_pe == pe3_assert_val) begin\n             if (write_only_q)\n               prog_empty_i <= #`TCQ 1'b0;\n             else\n               prog_empty_i <= #`TCQ 1'b1;\n           end else\n             prog_empty_i <= #`TCQ 1'b0;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe3_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > pe3_assert_val)\n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n\n     end\n   end endgenerate // single_pe_input\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_ASSERT; // STD\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_NEGATE; // STD\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n      else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe <= pe4_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || \n                     (diff_pntr_pe > pe4_negate_val)) begin\n             prog_empty_i <= #`TCQ 1'b0;\n           end else\n             prog_empty_i <= #`TCQ prog_empty_i;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe4_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > pe4_negate_val) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n     end\n   end endgenerate // multiple_pe_inputs\n\nendmodule // fifo_generator_v13_2_1_bhv_ver_ss\n\n\n\n/**************************************************************************\n * First-Word Fall-Through module (preload 0)\n **************************************************************************/\nmodule fifo_generator_v13_2_1_bhv_ver_preload0\n  #(\n    parameter  C_DOUT_RST_VAL            = \"\",\n    parameter  C_DOUT_WIDTH              = 8,\n    parameter  C_HAS_RST                 = 0,\n    parameter  C_ENABLE_RST_SYNC         = 0,\n    parameter  C_HAS_SRST                = 0,\n    parameter  C_USE_EMBEDDED_REG        = 0,\n    parameter  C_EN_SAFETY_CKT           = 0, \n    parameter  C_USE_DOUT_RST            = 0,\n    parameter  C_USE_ECC                 = 0,\n    parameter  C_USERVALID_LOW           = 0,\n    parameter  C_USERUNDERFLOW_LOW       = 0,\n    parameter  C_MEMORY_TYPE             = 0,\n    parameter  C_FIFO_TYPE               = 0\n  )\n  (\n    //Inputs\n    input                          SAFETY_CKT_RD_RST,\n    input                          RD_CLK,\n    input                          RD_RST,\n    input                          SRST,\n    input                          WR_RST_BUSY,\n    input                          RD_RST_BUSY,\n    input                          RD_EN,\n    input                          FIFOEMPTY,\n    input       [C_DOUT_WIDTH-1:0] FIFODATA,\n    input                          FIFOSBITERR,\n    input                          FIFODBITERR,\n   \n    //Outputs\n    output reg  [C_DOUT_WIDTH-1:0] USERDATA,\n    output                         USERVALID,\n    output                         USERUNDERFLOW,\n    output                         USEREMPTY,\n    output                         USERALMOSTEMPTY,\n    output                         RAMVALID,\n    output                         FIFORDEN,\n    output reg                     USERSBITERR,\n    output reg                     USERDBITERR,\n    output reg                     STAGE2_REG_EN,\n    output                         fab_read_data_valid_i_o,\n    output                         read_data_valid_i_o,\n    output                         ram_valid_i_o,\n    output      [1:0]              VALID_STAGES \n  );\n //Internal signals\n wire                      preloadstage1;\n wire                      preloadstage2;\n reg                       ram_valid_i;\n reg                       fab_valid;\n reg                       read_data_valid_i;\n reg                       fab_read_data_valid_i;\n reg                       fab_read_data_valid_i_1;\n reg                       ram_valid_i_d;\n reg                       read_data_valid_i_d;\n reg                       fab_read_data_valid_i_d;\n wire                      ram_regout_en;\n reg                       ram_regout_en_d1;\n reg                       ram_regout_en_d2;\n wire                      fab_regout_en;\n wire                      ram_rd_en;\n reg                       empty_i        = 1'b1;\n reg                       empty_sckt     = 1'b1;\n reg                       sckt_rrst_q    = 1'b0;\n reg                       sckt_rrst_done = 1'b0;\n reg                       empty_q        = 1'b1;\n reg                       rd_en_q        = 1'b0;\n reg                       almost_empty_i = 1'b1;\n reg                       almost_empty_q = 1'b1;\n wire                      rd_rst_i;\n wire                      srst_i;\n reg  [C_DOUT_WIDTH-1:0]   userdata_both;\n wire                      uservalid_both;\n wire                      uservalid_one;\n reg                       user_sbiterr_both = 1'b0;\n reg                       user_dbiterr_both = 1'b0;\n  \nassign ram_valid_i_o = ram_valid_i;\nassign read_data_valid_i_o = read_data_valid_i;\nassign fab_read_data_valid_i_o = fab_read_data_valid_i; \n\n\n\n/*************************************************************************\n* FUNCTIONS\n*************************************************************************/\n\n   /*************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***********************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n   \n   //*************************************************************************\n   //  Set power-on states for regs\n   //*************************************************************************\n   initial begin\n      ram_valid_i       = 1'b0;\n      fab_valid         = 1'b0;\n      read_data_valid_i = 1'b0;\n      fab_read_data_valid_i = 1'b0;\n      fab_read_data_valid_i_1 = 1'b0;\n      USERDATA          = hexstr_conv(C_DOUT_RST_VAL);\n      userdata_both          = hexstr_conv(C_DOUT_RST_VAL);\n      USERSBITERR       = 1'b0;\n      USERDBITERR       = 1'b0;\n      user_sbiterr_both = 1'b0;\n      user_dbiterr_both = 1'b0;\n   end //initial\n\n   //***************************************************************************\n   //  connect up optional reset\n   //***************************************************************************\n   assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;\n   assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;\n\n   reg  sckt_rd_rst_fwft = 1'b0;\n   reg  fwft_rst_done_i  = 1'b0;\n   wire fwft_rst_done;\n   assign fwft_rst_done = 1'b1;//C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;\n   always @ (posedge RD_CLK) begin\n     sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;\n   end\n\n   always @ (posedge rd_rst_i or posedge RD_CLK) begin\n     if (rd_rst_i)\n       fwft_rst_done_i  <= 1'b0;\n     else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)\n       fwft_rst_done_i  <= #`TCQ 1'b1;\n   end\n\n   localparam INVALID             = 0;\n   localparam STAGE1_VALID        = 2;\n   localparam STAGE2_VALID        = 1;\n   localparam BOTH_STAGES_VALID   = 3;\n\n   reg  [1:0] curr_fwft_state = INVALID;\n   reg  [1:0] next_fwft_state = INVALID;\n\n\ngenerate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin\n         always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n \n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n     \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n    \n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = preloadstage2;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;\n   end\nendgenerate // gnll_fifo\n\n   reg curr_state         = 0;\n   reg next_state         = 0;\n   reg leaving_empty_fwft = 0;\n   reg going_empty_fwft   = 0;\n   reg empty_i_q          = 0;\n   reg ram_rd_en_fwft     = 0;\n   generate if (C_FIFO_TYPE == 2) begin : gll_fifo\n     always @* begin // FSM fo FWFT\n       case (curr_state)\n         1'b0: begin\n           if (~FIFOEMPTY)\n             next_state <= 1'b1;\n           else\n             next_state <= 1'b0;\n           end\n         1'b1: begin\n           if (FIFOEMPTY && RD_EN)\n             next_state <= 1'b0;\n           else\n             next_state <= 1'b1;\n           end\n         default: next_state <= 1'b0;\n       endcase\n     end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_i       <= 1'b1;\n           empty_i_q     <= 1'b1;\n           ram_valid_i   <= 1'b0;\n        end else if (srst_i) begin\n           empty_i       <= #`TCQ 1'b1;\n           empty_i_q     <= #`TCQ 1'b1;\n           ram_valid_i   <= #`TCQ 1'b0;\n        end else begin\n           empty_i       <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);\n           empty_i_q     <= #`TCQ FIFOEMPTY;\n           ram_valid_i   <= #`TCQ next_state;\n        end\n     end //always\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n           curr_state    <= 1'b0;\n        end else if (srst_i) begin\n           curr_state    <= #`TCQ 1'b0;\n        end else begin\n           curr_state    <= #`TCQ next_state;\n        end\n     end //always\n\n     wire                  fe_of_empty; \n     assign fe_of_empty   = empty_i_q & ~FIFOEMPTY;\n\n     always @* begin // Finding leaving empty\n       case (curr_state)\n         1'b0:    leaving_empty_fwft <= fe_of_empty;\n         1'b1:    leaving_empty_fwft <= 1'b1;\n         default: leaving_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Finding going empty\n       case (curr_state)\n         1'b1:    going_empty_fwft <= FIFOEMPTY & RD_EN;\n         default: going_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Generating FWFT rd_en\n       case (curr_state)\n         1'b0:    ram_rd_en_fwft <= ~FIFOEMPTY;\n         1'b1:    ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;\n         default: ram_rd_en_fwft <= 1'b0;\n       endcase\n     end\n\n     assign ram_regout_en = ram_rd_en_fwft;\n     //assign ram_regout_en_d1 = ram_rd_en_fwft;\n     //assign ram_regout_en_d2 = ram_rd_en_fwft;\n     assign ram_rd_en     = ram_rd_en_fwft;\n   end endgenerate // gll_fifo\n\n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false.\n   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n   generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           ram_valid_i     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              ram_valid_i     <= #`TCQ 1'b0;\n           end else begin\n              if (ram_rd_en == 1'b1) begin\n                 ram_valid_i   <= #`TCQ 1'b1;\n              end else begin\n                 if (ram_regout_en == 1'b1)\n                   ram_valid_i <= #`TCQ 1'b0;\n                 else\n                   ram_valid_i <= #`TCQ ram_valid_i;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_ram_valid\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n  \n generate if(C_USE_EMBEDDED_REG < 3) begin\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else\n        read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);\n   end //always\nend \nendgenerate\n\n   \n   \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n generate if ( C_USE_EMBEDDED_REG < 3) begin\n  always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin         // asynchronous reset (active high)\n             almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ FIFOEMPTY;\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n   \n   \n     \n  // BRAM resets synchronously\n generate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin\n   always @ ( posedge rd_rst_i)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n           @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n             USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end  else if (fwft_rst_done) begin\n            if (ram_regout_en) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end\n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n//safety ckt with one register\ngenerate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n            @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n        end\n     end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n          //@(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end \n       end\n        else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n            //  @(posedge RD_CLK)\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end else if (fwft_rst_done) begin\n            if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end          \n          end\n        end\n       end //always\n  end //if\nendgenerate\n\n\ngenerate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin\n         \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d1 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d1 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d1 <= #`TCQ ram_regout_en;\n                 end\n            end //always\n   //  assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));\n       assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d2 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d2 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;\n                 end\n            end //always\n\n    \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n     always @ (posedge RD_CLK) begin\n        ram_valid_i_d <= #`TCQ ram_valid_i;\n        read_data_valid_i_d <= #`TCQ read_data_valid_i;\n        fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;\n\n     end\n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n    \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;\n   end\n   endgenerate // gnll_fifo\n\n   \n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n     generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid\n\n     \n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           fab_valid     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              fab_valid    <= #`TCQ 1'b0;\n           end else begin\n              if (ram_regout_en == 1'b1) begin\n                 fab_valid  <= #`TCQ 1'b1;\n              end else begin\n                 if (fab_regout_en == 1'b1)\n                   fab_valid <= #`TCQ 1'b0;\n                 else\n                   fab_valid <= #`TCQ fab_valid;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_fab_valid\n\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n    generate if(C_USE_EMBEDDED_REG == 3) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else begin\n        if (ram_regout_en == 1'b1) begin\n          read_data_valid_i <= #`TCQ 1'b1;\n        end else begin\n         if (fab_regout_en == 1'b1)\n          read_data_valid_i <= #`TCQ 1'b0;\n        else\n          read_data_valid_i <= #`TCQ read_data_valid_i;\n        end \n      end \n   end //always\nend\nendgenerate\n\n//generate if(C_USE_EMBEDDED_REG == 3) begin\n//   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n//      if (rd_rst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//      else if (srst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//\n//      if (ram_regout_en == 1'b1) begin\n//        fab_read_data_valid_i <= #`TCQ 1'b0;\n//      end else begin\n//       if (fab_regout_en == 1'b1)\n//        fab_read_data_valid_i <= #`TCQ 1'b1;\n//      else\n//        fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;\n//      end \n//   end //always\n//end\n//endgenerate\n\n     generate if(C_USE_EMBEDDED_REG == 3 ) begin \n    always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid\n      if (rd_rst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else \n        fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);\n   end //always\nend\nendgenerate\n \nalways @ (posedge RD_CLK ) begin : proc_del1\n             begin\n                 fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;\n              end\n            end //always\n \n \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty_both\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n   reg FIFOEMPTY_1;\n   generate if (C_USE_EMBEDDED_REG == 3 ) begin\n    always @(posedge RD_CLK) begin\n            FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;\n           end\n    end\nendgenerate\n    generate if (C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n   begin\n      if (rd_rst_i) begin         // asynchronous reset (active high)\n           almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ (~ram_valid_i);\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_sckt <= #`TCQ 1'b1;\n           sckt_rrst_q <= #`TCQ 1'b0;\n           sckt_rrst_done <= #`TCQ 1'b0;\n        end else begin\n           sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;\n           if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin\n              sckt_rrst_done <= #`TCQ 1'b1;\n           end else if (sckt_rrst_done) begin\n              // rising clock edge\n              empty_sckt <= #`TCQ 1'b0;\n           end\n        end\n     end //always\n   \n   \n//   assign USEREMPTY       = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;\n   assign USEREMPTY       = empty_i;\n   assign USERALMOSTEMPTY = almost_empty_i;\n   assign FIFORDEN        = ram_rd_en;\n   assign RAMVALID        = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;\n   assign uservalid_both       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3)  ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);\n   assign uservalid_one       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3)  ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);\n   assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;\n   assign USERUNDERFLOW   = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;\n//no safety ckt with both reg\ngenerate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n            USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              userdata_both   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end else begin\n            if (fwft_rst_done) begin\n              if (ram_regout_en) begin\n                 userdata_both     <= #`TCQ FIFODATA; \n                 user_dbiterr_both <= #`TCQ FIFODBITERR;\n                 user_sbiterr_both <= #`TCQ FIFOSBITERR; \n              end\n              if (fab_regout_en) begin\n                 USERDATA     <= #`TCQ userdata_both;\n                 USERDBITERR  <= #`TCQ user_dbiterr_both;\n                 USERSBITERR  <= #`TCQ user_sbiterr_both; \n              end             \n            end             \n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n\n//safety_ckt with both registers\n generate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always @ (posedge RD_CLK) begin\n          if (rd_rst_i || srst_i) begin\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n              @(posedge RD_CLK)\n              USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n               userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end\n        end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n     if (rd_rst_i) begin //asynchronous reset (active high)\n       if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n         USERSBITERR       <= #`TCQ 0;\n         USERDBITERR       <= #`TCQ 0;\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end\n       // DRAM resets asynchronously\n       if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n         USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end \n     end else begin // rising clock edge\n       if (srst_i) begin\n         if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n           USERSBITERR       <= #`TCQ 0;\n           USERDBITERR       <= #`TCQ 0;\n           user_sbiterr_both <= #`TCQ 0;\n           user_dbiterr_both <= #`TCQ 0;\n         end\n         if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n           USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end\n       end else if (fwft_rst_done) begin\n         if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            userdata_both     <= #`TCQ FIFODATA;\n            user_dbiterr_both <= #`TCQ FIFODBITERR;\n            user_sbiterr_both <= #`TCQ FIFOSBITERR; \n         end\n         if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            USERDATA          <= #`TCQ userdata_both;\n            USERDBITERR       <= #`TCQ user_dbiterr_both;\n            USERSBITERR       <= #`TCQ user_sbiterr_both;\n         end\n       end\n     end\n   end //always\n  end //if\nendgenerate\n\nendmodule //fifo_generator_v13_2_1_bhv_ver_preload0\n\n\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Register one AXI channel on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   reg_slice\n//\n//--------------------------------------------------------------------------\n\nmodule fifo_generator_v13_2_1_axic_reg_slice #\n  (\n   parameter C_FAMILY     = \"virtex7\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   )\n  (\n   // System Signals\n   input  wire                      ACLK,\n   input  wire                      ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0]   S_PAYLOAD_DATA,\n   input  wire                      S_VALID,\n   output wire                      S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0]   M_PAYLOAD_DATA,\n   output wire                      M_VALID,\n   input  wire                      M_READY\n   );\n\n  localparam RST_SYNC_STAGES = 5;\n  localparam RST_BUSY_LEN    = 6;\n  reg [1:0] arst_sync_wr  = 2'b11;\n  reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n  wire sync_reset;\n  wire extnd_reset;\n\n\n  always @(posedge ARESET or posedge ACLK) begin\n    if (ARESET)\n      arst_sync_wr <= 2'b11;\n    else\n      arst_sync_wr <= #`TCQ {arst_sync_wr[0], 1'b0};\n  end\n\n  always @(posedge ACLK) begin\n    sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[1]};\n  end\n\n  assign sync_reset     = |sckt_wr_rst_cc[RST_BUSY_LEN-5:0] | arst_sync_wr[1]; \n  assign extnd_reset    = |sckt_wr_rst_cc | arst_sync_wr[1];\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000)\n    begin\n      reg [1:0] state;\n      localparam [1:0] \n        ZERO = 2'b10,\n        ONE  = 2'b11,\n        TWO  = 2'b01;\n      \n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg [C_DATA_WIDTH-1:0] storage_data2 = 0;\n      reg                    load_s1;\n      wire                   load_s2;\n      wire                   load_s1_from_s2;\n      reg                    s_ready_i; //local signal of output\n      wire                   m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with either slave side data or from storage2\n      always @(posedge ACLK) \n      begin\n        if (load_s1)\n          if (load_s1_from_s2)\n            storage_data1 <= storage_data2;\n          else\n            storage_data1 <= S_PAYLOAD_DATA;        \n      end\n\n      // Load storage2 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data1;\n\n      // Always load s2 on a valid transaction even if it's unnecessary\n      assign load_s2 = S_VALID & s_ready_i;\n\n      // Loading s1\n      always @ *\n      begin\n        if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction\n             // Load when ONE if we both have read and write at the same time\n             ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||\n             // Load when TWO and we have a transaction on Master side\n             ((state == TWO) && (M_READY == 1)))\n          load_s1 = 1'b1;\n        else\n          load_s1 = 1'b0;\n      end // always @ *\n\n      assign load_s1_from_s2 = (state == TWO);\n                       \n      // State Machine for handling output signals\n      always @(posedge ACLK) begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          state <= ZERO;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          case (state)\n            // No transaction stored locally\n            ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE\n\n            // One transaction stored locally\n            ONE: begin\n              if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO\n              if (~M_READY & S_VALID) begin\n                state <= TWO;  // Got another one so move to TWO\n                s_ready_i <= 1'b0;\n              end\n            end\n\n            // TWO transaction stored locally\n            TWO: if (M_READY) begin\n              state <= ONE; // Read out one so move to ONE\n              s_ready_i <= 1'b1;\n            end\n          endcase // case (state)\n        end\n      end // always @ (posedge ACLK)\n      \n      assign m_valid_i = state[0];\n\n    end // if (C_REG_CONFIG == 1)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000001)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg                    s_ready_i; //local signal of output\n      reg                    m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b0;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else if (m_valid_i & M_READY) begin\n          s_ready_i <= 1'b1;\n          m_valid_i <= 1'b0;\n        end else if (S_VALID & s_ready_i) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b1;\n        end\n        if (~m_valid_i) begin\n          storage_data1 <= S_PAYLOAD_DATA;        \n        end\n      end\n      assign M_PAYLOAD_DATA = storage_data1;\n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // reg_slice\n", "num_lines": 10519}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1\n// IP Revision: 14\n\n(* X_CORE_INFO = \"axi_clock_converter_v2_1_14_axi_clock_converter,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"axi_clock_converter_0,axi_clock_converter_v2_1_14_axi_clock_converter,{}\" *)\n(* CORE_GENERATION_INFO = \"axi_clock_converter_0,axi_clock_converter_v2_1_14_axi_clock_converter,{x_ipProduct=Vivado 2017.4.op,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_clock_converter,x_ipVersion=2.1,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_ID_WIDTH=16,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=1,C_AXI_PROTOCOL=0,C_AXI_SUPPORTS_USER_SIGNALS=1,C_AXI_AWUSER_WIDTH=19,C_AXI_ARUSER_WIDTH=19,C_AXI_WUSER_WIDTH=1,\\\nC_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_SYNCHRONIZER_STAGE=2}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_clock_converter_0 (\n  s_axi_aclk,\n  s_axi_aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awuser,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_aruser,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_aclk,\n  m_axi_aresetn,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awuser,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_aruser,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_CLK, FREQ_HZ 10000000, PHASE 0.000\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 SI_CLK CLK\" *)\ninput wire s_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 SI_RST RST\" *)\ninput wire s_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWUSER\" *)\ninput wire [18 : 0] s_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARUSER\" *)\ninput wire [18 : 0] s_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 19, ARUSER_WIDTH 19, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_CLK, FREQ_HZ 10000000, PHASE 0.000\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 MI_CLK CLK\" *)\ninput wire m_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 MI_RST RST\" *)\ninput wire m_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWUSER\" *)\noutput wire [18 : 0] m_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARUSER\" *)\noutput wire [18 : 0] m_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 19, ARUSER_WIDTH 19, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_clock_converter_v2_1_14_axi_clock_converter #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_S_AXI_ACLK_RATIO(1),\n    .C_M_AXI_ACLK_RATIO(2),\n    .C_AXI_IS_ACLK_ASYNC(1),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_SUPPORTS_USER_SIGNALS(1),\n    .C_AXI_AWUSER_WIDTH(19),\n    .C_AXI_ARUSER_WIDTH(19),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_AXI_SUPPORTS_WRITE(1),\n    .C_AXI_SUPPORTS_READ(1),\n    .C_SYNCHRONIZER_STAGE(2)\n  ) inst (\n    .s_axi_aclk(s_axi_aclk),\n    .s_axi_aresetn(s_axi_aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(s_axi_awuser),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(s_axi_aruser),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_aclk(m_axi_aclk),\n    .m_axi_aresetn(m_axi_aresetn),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(m_axi_awuser),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(m_axi_aruser),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 441}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_15_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      (* max_fanout = 66 *) reg s_valid_d;\n      (* max_fanout = 66 *) reg s_ready_d = 1'b0;\n      (* max_fanout = 66 *) reg s_ready_reg = 1'b0;\n      (* max_fanout = 66 *) reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_15_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS==2) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS==2) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_15_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      // System Signals\n      .ACLK(ACLK),\n      .ARESET(ARESET),\n\n      // Slave side\n      .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n      .S_VALID(S_VALID),\n      .S_READY(S_READY),\n\n      // Master side\n      .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n      .M_VALID(M_VALID),\n      .M_READY(M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK           ( ACLK ) ,\n        .ARESET         ( ARESET ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK           ( ACLK ) ,\n        .ARESET         ( ARESET ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (1) begin : common\n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    (* dont_touch=\"true\" *)  reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_handshake_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg [((C_PIPELINES>0)?(C_PIPELINES-1):0):0] ready_d = 0;\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0; \n        laguna_m_ready_d <= 1'b0; \n        ready_d <= 0;\n      end else begin\n        laguna_m_ready_d <= laguna_m_ready; \n        if (C_PIPELINES==0) begin\n          laguna_s_ready_i <= laguna_m_ready_d;\n        end else if (C_PIPELINES==1) begin\n          ready_d <= laguna_m_ready_d; \n          laguna_s_ready_i <= ready_d;\n        end else begin\n          ready_d <= {ready_d, laguna_m_ready_d}; \n          laguna_s_ready_i <= ready_d[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n        end\n      end\n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_d : payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, laguna_m_ready_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{laguna_m_ready_d}};\n            payload_valid_enable <= laguna_m_ready_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==0) begin\n                laguna_s_payload_d[i] <= laguna_s_payload[i];\n              end else if (p==C_PIPELINES+1) begin\n                laguna_m_payload_i[i] <= payload_i[C_PIPELINES*C_DATA_WIDTH + i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          if (areset_d) begin\n            laguna_s_handshake_d <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_s_handshake_d <= laguna_s_handshake;\n          end\n        end else if (p==C_PIPELINES+1) begin\n          if (areset_d) begin\n            laguna_m_handshake_i <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_m_handshake_i <= handshake_i[C_PIPELINES];\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (C_REG_CONFIG == 13) begin : tdm\n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* dont_touch=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_15_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_LATENCY = (C_PIPELINES>0) ? C_PIPELINES : 1;\n     \n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    (* dont_touch=\"true\" *)  reg laguna_m_handshake_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] ready_d = 0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_LATENCY-1];\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_ready_d <= 1'b0; \n        ready_d <= 0;\n      end else begin\n        laguna_m_ready_d <= laguna_m_ready; \n        if (C_PIPELINES>0) begin\n          ready_d <= {ready_d, laguna_m_ready_d}; \n        end\n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, laguna_m_ready_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{laguna_m_ready_d}};\n            payload_valid_enable <= laguna_m_ready_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (C_PIPELINES==0) begin\n          if (laguna_m_ready_d) begin\n            laguna_m_payload_i <= S_PAYLOAD_DATA;\n          end\n        end else begin\n          for (r=0; r<P_REPLICATION; r=r+1) begin\n            if (payload_data_enable[r]) begin\n              for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n                if (p==C_PIPELINES) begin\n                  laguna_m_payload_i[i] <= payload_i[((C_PIPELINES>0)?(C_PIPELINES-1):0)*C_DATA_WIDTH + i];\n                end else if (p==0) begin\n                  payload_data[i] <= S_PAYLOAD_DATA[i];\n                end else begin\n                  payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n                end\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (C_PIPELINES==0) begin\n          if (areset_d) begin\n            laguna_m_handshake_i <= 1'b0;\n          end else if (laguna_m_ready_d) begin\n            laguna_m_handshake_i <= S_VALID;\n          end\n        end else begin\n          if (p==C_PIPELINES) begin\n            if (areset_d) begin\n              laguna_m_handshake_i <= 1'b0;\n            end else if (payload_valid_enable) begin\n              laguna_m_handshake_i <= handshake_i[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n            end\n          end else if (p==0) begin\n            if (areset_d) begin\n              payload_valid <= 1'b0;\n            end else if (payload_valid_enable) begin\n              payload_valid <= S_VALID;\n            end\n          end else begin\n            if (areset_d) begin\n              payload_valid <= 1'b0;\n            end else if (payload_valid_enable) begin\n              payload_valid <= handshake_i[((p>0)?(p-1):0)];\n            end\n          end\n        end\n      end\n    end\n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_15_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (C_REG_CONFIG == 13) begin : tdm\n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n     \n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* dont_touch=\"true\" *)  reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg [((C_PIPELINES>0)?(C_PIPELINES-1):0):0] ready_d = 0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] push_enable_d = 0;\n    (* dont_touch=\"true\" *)  reg root_enable_d = 1'b0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    wire push_enable;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push_enable = push_enable_d[P_PIPE_LATENCY-1];\n    assign push = handshake_i[C_PIPELINES] & push_enable;      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0; \n        ready_d <= 0;\n        push_enable_d <= 0;\n        root_enable_d <= 1'b0; \n      end else begin\n        push_enable_d <= {push_enable_d, root_enable_d};\n        root_enable_d <= M_READY | ~m_valid_i;\n        if (C_PIPELINES==0) begin\n          laguna_s_ready_i <= root_enable_d;\n        end else if (C_PIPELINES==1) begin\n          ready_d <= root_enable_d; \n          laguna_s_ready_i <= ready_d;\n        end else begin\n          ready_d <= {ready_d, root_enable_d}; \n          laguna_s_ready_i <= ready_d[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n        end\n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_d : payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, root_enable_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{root_enable_d}};\n            payload_valid_enable <= root_enable_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==0) begin\n                laguna_s_payload_d[i] <= laguna_s_payload[i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          if (areset_d) begin\n            laguna_s_handshake_d <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_s_handshake_d <= laguna_s_handshake;\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n    if ((C_PIPELINES==0) && (C_SOURCE_LATENCY<=1)) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        ); \n  \n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_15_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_LATENCY = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (1) begin : common\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] ready_d = 0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] push_enable_d = 0;\n    (* dont_touch=\"true\" *)  reg root_enable_d = 1'b0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire s_ready_i;\n    wire push;\n    wire pop;\n    wire push_enable;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push_enable = (C_PIPELINES == 0) ? root_enable_d : push_enable_d[P_PIPE_LATENCY-1];\n    assign push = handshake_i[C_PIPELINES] & push_enable;      \n    assign M_VALID = m_valid_i;\n    assign s_ready_i = (C_PIPELINES == 0) ? root_enable_d : ready_d[P_PIPE_LATENCY-1];\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        ready_d <= 0;\n        push_enable_d <= 0;\n        root_enable_d <= 1'b0;\n      end else begin\n        root_enable_d <= M_READY | ~m_valid_i;\n        if (C_PIPELINES > 0) begin\n          ready_d <= {ready_d, root_enable_d}; \n          push_enable_d <= {push_enable_d, root_enable_d};\n        end\n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, root_enable_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{root_enable_d}};\n            payload_valid_enable <= root_enable_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==1) begin\n                payload_data[i] <= S_PAYLOAD_DATA[i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= S_VALID;\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n    if (C_PIPELINES<=1) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    (* fsm_encoding = \"none\" *) reg [1:0] state = K_EMPTY;  // State vector register\n    reg [1:0] next;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    \n    assign m_valid = state[0];  // Drive m_valid from state vector\n    assign m_mesg  = mesg_reg;\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid) begin\n            next = K_HAS1;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin\n      if (areset) begin\n        state <= K_EMPTY;\n      end else begin\n        state <= next;\n      end\n    end\n            \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      axi_register_slice_v2_1_15_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n\n  axi_infrastructure_v1_1_0_axi2vector #( \n    .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n    .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n    .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n    .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n    .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n    .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n    .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n    .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n    .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n    .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n    .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n    .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n    .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n    .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n    .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n    .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n  )\n  axi2vector_0 ( \n    .s_axi_awid      ( s_axi_awid      ) ,\n    .s_axi_awaddr    ( s_axi_awaddr    ) ,\n    .s_axi_awlen     ( s_axi_awlen     ) ,\n    .s_axi_awsize    ( s_axi_awsize    ) ,\n    .s_axi_awburst   ( s_axi_awburst   ) ,\n    .s_axi_awlock    ( s_axi_awlock    ) ,\n    .s_axi_awcache   ( s_axi_awcache   ) ,\n    .s_axi_awprot    ( s_axi_awprot    ) ,\n    .s_axi_awqos     ( s_axi_awqos     ) ,\n    .s_axi_awuser    ( s_axi_awuser    ) ,\n    .s_axi_awregion  ( s_axi_awregion  ) ,\n    .s_axi_wid       ( s_axi_wid       ) ,\n    .s_axi_wdata     ( s_axi_wdata     ) ,\n    .s_axi_wstrb     ( s_axi_wstrb     ) ,\n    .s_axi_wlast     ( s_axi_wlast     ) ,\n    .s_axi_wuser     ( s_axi_wuser     ) ,\n    .s_axi_bid       ( s_axi_bid       ) ,\n    .s_axi_bresp     ( s_axi_bresp     ) ,\n    .s_axi_buser     ( s_axi_buser     ) ,\n    .s_axi_arid      ( s_axi_arid      ) ,\n    .s_axi_araddr    ( s_axi_araddr    ) ,\n    .s_axi_arlen     ( s_axi_arlen     ) ,\n    .s_axi_arsize    ( s_axi_arsize    ) ,\n    .s_axi_arburst   ( s_axi_arburst   ) ,\n    .s_axi_arlock    ( s_axi_arlock    ) ,\n    .s_axi_arcache   ( s_axi_arcache   ) ,\n    .s_axi_arprot    ( s_axi_arprot    ) ,\n    .s_axi_arqos     ( s_axi_arqos     ) ,\n    .s_axi_aruser    ( s_axi_aruser    ) ,\n    .s_axi_arregion  ( s_axi_arregion  ) ,\n    .s_axi_rid       ( s_axi_rid       ) ,\n    .s_axi_rdata     ( s_axi_rdata     ) ,\n    .s_axi_rresp     ( s_axi_rresp     ) ,\n    .s_axi_rlast     ( s_axi_rlast     ) ,\n    .s_axi_ruser     ( s_axi_ruser     ) ,\n    .s_awpayload ( s_awpayload ) ,\n    .s_wpayload  ( s_wpayload  ) ,\n    .s_bpayload  ( s_bpayload  ) ,\n    .s_arpayload ( s_arpayload ) ,\n    .s_rpayload  ( s_rpayload  ) \n  );\n    \n  if (C_REG_CONFIG_AW <= 9) begin : aw\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_REG_CONFIG_AW == 15) begin : aw15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if (C_REG_CONFIG_W <= 9) begin : w\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_REG_CONFIG_W == 15) begin : w15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if (C_REG_CONFIG_B <= 9) begin : b\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if (C_REG_CONFIG_B == 15) begin : b15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if (C_REG_CONFIG_AR <= 9) begin : ar\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_REG_CONFIG_AR == 15) begin : ar15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if (C_REG_CONFIG_R <= 9) begin : r\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_REG_CONFIG_R == 15) begin : r15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\n  axi_infrastructure_v1_1_0_vector2axi #( \n    .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n    .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n    .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n    .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n    .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n    .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n    .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n    .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n    .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n    .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n    .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n    .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n    .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n    .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n    .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n    .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n  )\n  vector2axi_0 ( \n    .m_awpayload    ( m_awpayload    ) ,\n    .m_wpayload     ( m_wpayload     ) ,\n    .m_bpayload     ( m_bpayload     ) ,\n    .m_arpayload    ( m_arpayload    ) ,\n    .m_rpayload     ( m_rpayload     ) ,\n    .m_axi_awid     ( m_axi_awid     ) ,\n    .m_axi_awaddr   ( m_axi_awaddr   ) ,\n    .m_axi_awlen    ( m_axi_awlen    ) ,\n    .m_axi_awsize   ( m_axi_awsize   ) ,\n    .m_axi_awburst  ( m_axi_awburst  ) ,\n    .m_axi_awlock   ( m_axi_awlock   ) ,\n    .m_axi_awcache  ( m_axi_awcache  ) ,\n    .m_axi_awprot   ( m_axi_awprot   ) ,\n    .m_axi_awqos    ( m_axi_awqos    ) ,\n    .m_axi_awuser   ( m_axi_awuser   ) ,\n    .m_axi_awregion ( m_axi_awregion ) ,\n    .m_axi_wid      ( m_axi_wid      ) ,\n    .m_axi_wdata    ( m_axi_wdata    ) ,\n    .m_axi_wstrb    ( m_axi_wstrb    ) ,\n    .m_axi_wlast    ( m_axi_wlast    ) ,\n    .m_axi_wuser    ( m_axi_wuser    ) ,\n    .m_axi_bid      ( m_axi_bid      ) ,\n    .m_axi_bresp    ( m_axi_bresp    ) ,\n    .m_axi_buser    ( m_axi_buser    ) ,\n    .m_axi_arid     ( m_axi_arid     ) ,\n    .m_axi_araddr   ( m_axi_araddr   ) ,\n    .m_axi_arlen    ( m_axi_arlen    ) ,\n    .m_axi_arsize   ( m_axi_arsize   ) ,\n    .m_axi_arburst  ( m_axi_arburst  ) ,\n    .m_axi_arlock   ( m_axi_arlock   ) ,\n    .m_axi_arcache  ( m_axi_arcache  ) ,\n    .m_axi_arprot   ( m_axi_arprot   ) ,\n    .m_axi_arqos    ( m_axi_arqos    ) ,\n    .m_axi_aruser   ( m_axi_aruser   ) ,\n    .m_axi_arregion ( m_axi_arregion ) ,\n    .m_axi_rid      ( m_axi_rid      ) ,\n    .m_axi_rdata    ( m_axi_rdata    ) ,\n    .m_axi_rresp    ( m_axi_rresp    ) ,\n    .m_axi_rlast    ( m_axi_rlast    ) ,\n    .m_axi_ruser    ( m_axi_ruser    ) \n  );\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 3108}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 10000000, PHASE 0.000\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(1),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(1),\n    .C_REG_CONFIG_AR(1),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 433}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_15_axi_register_slice,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"axi_register_slice,axi_register_slice_v2_1_15_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"axi_register_slice,axi_register_slice_v2_1_15_axi_register_slice,{x_ipProduct=Vivado 2017.4.op,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=16,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=1,C_REG_CONFIG_W\\\n=1,C_REG_CONFIG_B=1,C_REG_CONFIG_AR=1,C_REG_CONFIG_R=1,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 10000000, PHASE 0.000\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(1),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(1),\n    .C_REG_CONFIG_AR(1),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 435}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_15_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      (* max_fanout = 66 *) reg s_valid_d;\n      (* max_fanout = 66 *) reg s_ready_d = 1'b0;\n      (* max_fanout = 66 *) reg s_ready_reg = 1'b0;\n      (* max_fanout = 66 *) reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_15_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS==2) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS==2) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_15_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      // System Signals\n      .ACLK(ACLK),\n      .ARESET(ARESET),\n\n      // Slave side\n      .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n      .S_VALID(S_VALID),\n      .S_READY(S_READY),\n\n      // Master side\n      .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n      .M_VALID(M_VALID),\n      .M_READY(M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK           ( ACLK ) ,\n        .ARESET         ( ARESET ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK           ( ACLK ) ,\n        .ARESET         ( ARESET ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (1) begin : common\n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    (* dont_touch=\"true\" *)  reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_handshake_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg [((C_PIPELINES>0)?(C_PIPELINES-1):0):0] ready_d = 0;\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0; \n        laguna_m_ready_d <= 1'b0; \n        ready_d <= 0;\n      end else begin\n        laguna_m_ready_d <= laguna_m_ready; \n        if (C_PIPELINES==0) begin\n          laguna_s_ready_i <= laguna_m_ready_d;\n        end else if (C_PIPELINES==1) begin\n          ready_d <= laguna_m_ready_d; \n          laguna_s_ready_i <= ready_d;\n        end else begin\n          ready_d <= {ready_d, laguna_m_ready_d}; \n          laguna_s_ready_i <= ready_d[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n        end\n      end\n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_d : payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, laguna_m_ready_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{laguna_m_ready_d}};\n            payload_valid_enable <= laguna_m_ready_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==0) begin\n                laguna_s_payload_d[i] <= laguna_s_payload[i];\n              end else if (p==C_PIPELINES+1) begin\n                laguna_m_payload_i[i] <= payload_i[C_PIPELINES*C_DATA_WIDTH + i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          if (areset_d) begin\n            laguna_s_handshake_d <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_s_handshake_d <= laguna_s_handshake;\n          end\n        end else if (p==C_PIPELINES+1) begin\n          if (areset_d) begin\n            laguna_m_handshake_i <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_m_handshake_i <= handshake_i[C_PIPELINES];\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (C_REG_CONFIG == 13) begin : tdm\n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* dont_touch=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_15_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_LATENCY = (C_PIPELINES>0) ? C_PIPELINES : 1;\n     \n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    (* dont_touch=\"true\" *)  reg laguna_m_handshake_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] ready_d = 0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_LATENCY-1];\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_ready_d <= 1'b0; \n        ready_d <= 0;\n      end else begin\n        laguna_m_ready_d <= laguna_m_ready; \n        if (C_PIPELINES>0) begin\n          ready_d <= {ready_d, laguna_m_ready_d}; \n        end\n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, laguna_m_ready_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{laguna_m_ready_d}};\n            payload_valid_enable <= laguna_m_ready_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (C_PIPELINES==0) begin\n          if (laguna_m_ready_d) begin\n            laguna_m_payload_i <= S_PAYLOAD_DATA;\n          end\n        end else begin\n          for (r=0; r<P_REPLICATION; r=r+1) begin\n            if (payload_data_enable[r]) begin\n              for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n                if (p==C_PIPELINES) begin\n                  laguna_m_payload_i[i] <= payload_i[((C_PIPELINES>0)?(C_PIPELINES-1):0)*C_DATA_WIDTH + i];\n                end else if (p==0) begin\n                  payload_data[i] <= S_PAYLOAD_DATA[i];\n                end else begin\n                  payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n                end\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (C_PIPELINES==0) begin\n          if (areset_d) begin\n            laguna_m_handshake_i <= 1'b0;\n          end else if (laguna_m_ready_d) begin\n            laguna_m_handshake_i <= S_VALID;\n          end\n        end else begin\n          if (p==C_PIPELINES) begin\n            if (areset_d) begin\n              laguna_m_handshake_i <= 1'b0;\n            end else if (payload_valid_enable) begin\n              laguna_m_handshake_i <= handshake_i[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n            end\n          end else if (p==0) begin\n            if (areset_d) begin\n              payload_valid <= 1'b0;\n            end else if (payload_valid_enable) begin\n              payload_valid <= S_VALID;\n            end\n          end else begin\n            if (areset_d) begin\n              payload_valid <= 1'b0;\n            end else if (payload_valid_enable) begin\n              payload_valid <= handshake_i[((p>0)?(p-1):0)];\n            end\n          end\n        end\n      end\n    end\n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_15_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (C_REG_CONFIG == 13) begin : tdm\n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n     \n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* dont_touch=\"true\" *)  reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg [((C_PIPELINES>0)?(C_PIPELINES-1):0):0] ready_d = 0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] push_enable_d = 0;\n    (* dont_touch=\"true\" *)  reg root_enable_d = 1'b0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    wire push_enable;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push_enable = push_enable_d[P_PIPE_LATENCY-1];\n    assign push = handshake_i[C_PIPELINES] & push_enable;      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0; \n        ready_d <= 0;\n        push_enable_d <= 0;\n        root_enable_d <= 1'b0; \n      end else begin\n        push_enable_d <= {push_enable_d, root_enable_d};\n        root_enable_d <= M_READY | ~m_valid_i;\n        if (C_PIPELINES==0) begin\n          laguna_s_ready_i <= root_enable_d;\n        end else if (C_PIPELINES==1) begin\n          ready_d <= root_enable_d; \n          laguna_s_ready_i <= ready_d;\n        end else begin\n          ready_d <= {ready_d, root_enable_d}; \n          laguna_s_ready_i <= ready_d[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n        end\n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_d : payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, root_enable_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{root_enable_d}};\n            payload_valid_enable <= root_enable_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==0) begin\n                laguna_s_payload_d[i] <= laguna_s_payload[i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          if (areset_d) begin\n            laguna_s_handshake_d <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_s_handshake_d <= laguna_s_handshake;\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n    if ((C_PIPELINES==0) && (C_SOURCE_LATENCY<=1)) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        ); \n  \n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_15_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_LATENCY = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (1) begin : common\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] ready_d = 0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] push_enable_d = 0;\n    (* dont_touch=\"true\" *)  reg root_enable_d = 1'b0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire s_ready_i;\n    wire push;\n    wire pop;\n    wire push_enable;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push_enable = (C_PIPELINES == 0) ? root_enable_d : push_enable_d[P_PIPE_LATENCY-1];\n    assign push = handshake_i[C_PIPELINES] & push_enable;      \n    assign M_VALID = m_valid_i;\n    assign s_ready_i = (C_PIPELINES == 0) ? root_enable_d : ready_d[P_PIPE_LATENCY-1];\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        ready_d <= 0;\n        push_enable_d <= 0;\n        root_enable_d <= 1'b0;\n      end else begin\n        root_enable_d <= M_READY | ~m_valid_i;\n        if (C_PIPELINES > 0) begin\n          ready_d <= {ready_d, root_enable_d}; \n          push_enable_d <= {push_enable_d, root_enable_d};\n        end\n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, root_enable_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{root_enable_d}};\n            payload_valid_enable <= root_enable_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==1) begin\n                payload_data[i] <= S_PAYLOAD_DATA[i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= S_VALID;\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n    if (C_PIPELINES<=1) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    (* fsm_encoding = \"none\" *) reg [1:0] state = K_EMPTY;  // State vector register\n    reg [1:0] next;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    \n    assign m_valid = state[0];  // Drive m_valid from state vector\n    assign m_mesg  = mesg_reg;\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid) begin\n            next = K_HAS1;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin\n      if (areset) begin\n        state <= K_EMPTY;\n      end else begin\n        state <= next;\n      end\n    end\n            \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      axi_register_slice_v2_1_15_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n\n  axi_infrastructure_v1_1_0_axi2vector #( \n    .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n    .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n    .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n    .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n    .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n    .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n    .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n    .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n    .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n    .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n    .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n    .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n    .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n    .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n    .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n    .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n  )\n  axi2vector_0 ( \n    .s_axi_awid      ( s_axi_awid      ) ,\n    .s_axi_awaddr    ( s_axi_awaddr    ) ,\n    .s_axi_awlen     ( s_axi_awlen     ) ,\n    .s_axi_awsize    ( s_axi_awsize    ) ,\n    .s_axi_awburst   ( s_axi_awburst   ) ,\n    .s_axi_awlock    ( s_axi_awlock    ) ,\n    .s_axi_awcache   ( s_axi_awcache   ) ,\n    .s_axi_awprot    ( s_axi_awprot    ) ,\n    .s_axi_awqos     ( s_axi_awqos     ) ,\n    .s_axi_awuser    ( s_axi_awuser    ) ,\n    .s_axi_awregion  ( s_axi_awregion  ) ,\n    .s_axi_wid       ( s_axi_wid       ) ,\n    .s_axi_wdata     ( s_axi_wdata     ) ,\n    .s_axi_wstrb     ( s_axi_wstrb     ) ,\n    .s_axi_wlast     ( s_axi_wlast     ) ,\n    .s_axi_wuser     ( s_axi_wuser     ) ,\n    .s_axi_bid       ( s_axi_bid       ) ,\n    .s_axi_bresp     ( s_axi_bresp     ) ,\n    .s_axi_buser     ( s_axi_buser     ) ,\n    .s_axi_arid      ( s_axi_arid      ) ,\n    .s_axi_araddr    ( s_axi_araddr    ) ,\n    .s_axi_arlen     ( s_axi_arlen     ) ,\n    .s_axi_arsize    ( s_axi_arsize    ) ,\n    .s_axi_arburst   ( s_axi_arburst   ) ,\n    .s_axi_arlock    ( s_axi_arlock    ) ,\n    .s_axi_arcache   ( s_axi_arcache   ) ,\n    .s_axi_arprot    ( s_axi_arprot    ) ,\n    .s_axi_arqos     ( s_axi_arqos     ) ,\n    .s_axi_aruser    ( s_axi_aruser    ) ,\n    .s_axi_arregion  ( s_axi_arregion  ) ,\n    .s_axi_rid       ( s_axi_rid       ) ,\n    .s_axi_rdata     ( s_axi_rdata     ) ,\n    .s_axi_rresp     ( s_axi_rresp     ) ,\n    .s_axi_rlast     ( s_axi_rlast     ) ,\n    .s_axi_ruser     ( s_axi_ruser     ) ,\n    .s_awpayload ( s_awpayload ) ,\n    .s_wpayload  ( s_wpayload  ) ,\n    .s_bpayload  ( s_bpayload  ) ,\n    .s_arpayload ( s_arpayload ) ,\n    .s_rpayload  ( s_rpayload  ) \n  );\n    \n  if (C_REG_CONFIG_AW <= 9) begin : aw\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_REG_CONFIG_AW == 15) begin : aw15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if (C_REG_CONFIG_W <= 9) begin : w\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_REG_CONFIG_W == 15) begin : w15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if (C_REG_CONFIG_B <= 9) begin : b\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if (C_REG_CONFIG_B == 15) begin : b15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if (C_REG_CONFIG_AR <= 9) begin : ar\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_REG_CONFIG_AR == 15) begin : ar15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if (C_REG_CONFIG_R <= 9) begin : r\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_REG_CONFIG_R == 15) begin : r15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\n  axi_infrastructure_v1_1_0_vector2axi #( \n    .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n    .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n    .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n    .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n    .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n    .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n    .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n    .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n    .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n    .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n    .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n    .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n    .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n    .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n    .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n    .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n  )\n  vector2axi_0 ( \n    .m_awpayload    ( m_awpayload    ) ,\n    .m_wpayload     ( m_wpayload     ) ,\n    .m_bpayload     ( m_bpayload     ) ,\n    .m_arpayload    ( m_arpayload    ) ,\n    .m_rpayload     ( m_rpayload     ) ,\n    .m_axi_awid     ( m_axi_awid     ) ,\n    .m_axi_awaddr   ( m_axi_awaddr   ) ,\n    .m_axi_awlen    ( m_axi_awlen    ) ,\n    .m_axi_awsize   ( m_axi_awsize   ) ,\n    .m_axi_awburst  ( m_axi_awburst  ) ,\n    .m_axi_awlock   ( m_axi_awlock   ) ,\n    .m_axi_awcache  ( m_axi_awcache  ) ,\n    .m_axi_awprot   ( m_axi_awprot   ) ,\n    .m_axi_awqos    ( m_axi_awqos    ) ,\n    .m_axi_awuser   ( m_axi_awuser   ) ,\n    .m_axi_awregion ( m_axi_awregion ) ,\n    .m_axi_wid      ( m_axi_wid      ) ,\n    .m_axi_wdata    ( m_axi_wdata    ) ,\n    .m_axi_wstrb    ( m_axi_wstrb    ) ,\n    .m_axi_wlast    ( m_axi_wlast    ) ,\n    .m_axi_wuser    ( m_axi_wuser    ) ,\n    .m_axi_bid      ( m_axi_bid      ) ,\n    .m_axi_bresp    ( m_axi_bresp    ) ,\n    .m_axi_buser    ( m_axi_buser    ) ,\n    .m_axi_arid     ( m_axi_arid     ) ,\n    .m_axi_araddr   ( m_axi_araddr   ) ,\n    .m_axi_arlen    ( m_axi_arlen    ) ,\n    .m_axi_arsize   ( m_axi_arsize   ) ,\n    .m_axi_arburst  ( m_axi_arburst  ) ,\n    .m_axi_arlock   ( m_axi_arlock   ) ,\n    .m_axi_arcache  ( m_axi_arcache  ) ,\n    .m_axi_arprot   ( m_axi_arprot   ) ,\n    .m_axi_arqos    ( m_axi_arqos    ) ,\n    .m_axi_aruser   ( m_axi_aruser   ) ,\n    .m_axi_arregion ( m_axi_arregion ) ,\n    .m_axi_rid      ( m_axi_rid      ) ,\n    .m_axi_rdata    ( m_axi_rdata    ) ,\n    .m_axi_rresp    ( m_axi_rresp    ) ,\n    .m_axi_rlast    ( m_axi_rlast    ) ,\n    .m_axi_ruser    ( m_axi_ruser    ) \n  );\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 3108}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_register_slice_light (\n  aclk,\n  aresetn,\n  s_axi_awaddr,\n  s_axi_awprot,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_araddr,\n  s_axi_arprot,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awaddr,\n  m_axi_awprot,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_araddr,\n  m_axi_arprot,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 10000000, PHASE 0.000\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [31 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [31 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [3 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [31 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [31 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [31 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [31 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [3 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [31 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [31 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(2),\n    .C_AXI_ID_WIDTH(1),\n    .C_AXI_ADDR_WIDTH(32),\n    .C_AXI_DATA_WIDTH(32),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(7),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(7),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(1'H0),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(8'H00),\n    .s_axi_awsize(3'H0),\n    .s_axi_awburst(2'H1),\n    .s_axi_awlock(1'H0),\n    .s_axi_awcache(4'H0),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(4'H0),\n    .s_axi_awqos(4'H0),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(1'H0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(1'H1),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(1'H0),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(8'H00),\n    .s_axi_arsize(3'H0),\n    .s_axi_arburst(2'H1),\n    .s_axi_arlock(1'H0),\n    .s_axi_arcache(4'H0),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(4'H0),\n    .s_axi_arqos(4'H0),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(),\n    .m_axi_awsize(),\n    .m_axi_awburst(),\n    .m_axi_awlock(),\n    .m_axi_awcache(),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(),\n    .m_axi_awqos(),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(1'H0),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(),\n    .m_axi_arsize(),\n    .m_axi_arburst(),\n    .m_axi_arlock(),\n    .m_axi_arcache(),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(),\n    .m_axi_arqos(),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(1'H0),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(1'H1),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 313}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_15_axi_register_slice,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"axi_register_slice_light,axi_register_slice_v2_1_15_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"axi_register_slice_light,axi_register_slice_v2_1_15_axi_register_slice,{x_ipProduct=Vivado 2017.4.op,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=2,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_REG_CONF\\\nIG_W=7,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=7,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_register_slice_light (\n  aclk,\n  aresetn,\n  s_axi_awaddr,\n  s_axi_awprot,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_araddr,\n  s_axi_arprot,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awaddr,\n  m_axi_awprot,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_araddr,\n  m_axi_arprot,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 10000000, PHASE 0.000\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [31 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [31 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [3 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [31 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [31 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [31 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [31 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [3 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [31 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [31 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(2),\n    .C_AXI_ID_WIDTH(1),\n    .C_AXI_ADDR_WIDTH(32),\n    .C_AXI_DATA_WIDTH(32),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(7),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(7),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(1'H0),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(8'H00),\n    .s_axi_awsize(3'H0),\n    .s_axi_awburst(2'H1),\n    .s_axi_awlock(1'H0),\n    .s_axi_awcache(4'H0),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(4'H0),\n    .s_axi_awqos(4'H0),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(1'H0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(1'H1),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(1'H0),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(8'H00),\n    .s_axi_arsize(3'H0),\n    .s_axi_arburst(2'H1),\n    .s_axi_arlock(1'H0),\n    .s_axi_arcache(4'H0),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(4'H0),\n    .s_axi_arqos(4'H0),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(),\n    .m_axi_awsize(),\n    .m_axi_awburst(),\n    .m_axi_awlock(),\n    .m_axi_awcache(),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(),\n    .m_axi_awqos(),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(1'H0),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(),\n    .m_axi_arsize(),\n    .m_axi_arburst(),\n    .m_axi_arlock(),\n    .m_axi_arcache(),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(),\n    .m_axi_arqos(),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(1'H0),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(1'H1),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 315}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2017.4.op (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017\n// Date        : Tue May 22 11:59:41 2018\n// Host        : ip-10-206-20-46 running 64-bit CentOS release 6.5 (Final)\n// Command     : write_verilog -force -mode synth_stub\n//               /proj/soc_work/cccabra/F1/Chimera/design/rtl/v4_venom_cl_github/v4_venom_cl_github.srcs/sources_1/bd/cl_axi_interconnect/cl_axi_interconnect_stub.v\n// Design      : cl_axi_interconnect\n// Purpose     : Stub declaration of top-level module interface\n// Device      : xcvu9p-flgb2104-2-i\n// --------------------------------------------------------------------------------\n\n// This empty module with port declaration file causes synthesis tools to infer a black box for IP.\n// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.\n// Please paste the declaration into a Verilog source file or add the file as an additional source.\nmodule cl_axi_interconnect(ACLK, ARESETN, M00_AXI_araddr, M00_AXI_arburst, \n  M00_AXI_arcache, M00_AXI_arid, M00_AXI_arlen, M00_AXI_arlock, M00_AXI_arprot, \n  M00_AXI_arqos, M00_AXI_arready, M00_AXI_arregion, M00_AXI_arsize, M00_AXI_arvalid, \n  M00_AXI_awaddr, M00_AXI_awburst, M00_AXI_awcache, M00_AXI_awid, M00_AXI_awlen, \n  M00_AXI_awlock, M00_AXI_awprot, M00_AXI_awqos, M00_AXI_awready, M00_AXI_awregion, \n  M00_AXI_awsize, M00_AXI_awvalid, M00_AXI_bid, M00_AXI_bready, M00_AXI_bresp, \n  M00_AXI_bvalid, M00_AXI_rdata, M00_AXI_rid, M00_AXI_rlast, M00_AXI_rready, M00_AXI_rresp, \n  M00_AXI_rvalid, M00_AXI_wdata, M00_AXI_wlast, M00_AXI_wready, M00_AXI_wstrb, \n  M00_AXI_wvalid, M01_AXI_araddr, M01_AXI_arburst, M01_AXI_arcache, M01_AXI_arid, \n  M01_AXI_arlen, M01_AXI_arlock, M01_AXI_arprot, M01_AXI_arqos, M01_AXI_arready, \n  M01_AXI_arregion, M01_AXI_arsize, M01_AXI_arvalid, M01_AXI_awaddr, M01_AXI_awburst, \n  M01_AXI_awcache, M01_AXI_awid, M01_AXI_awlen, M01_AXI_awlock, M01_AXI_awprot, \n  M01_AXI_awqos, M01_AXI_awready, M01_AXI_awregion, M01_AXI_awsize, M01_AXI_awvalid, \n  M01_AXI_bid, M01_AXI_bready, M01_AXI_bresp, M01_AXI_bvalid, M01_AXI_rdata, M01_AXI_rid, \n  M01_AXI_rlast, M01_AXI_rready, M01_AXI_rresp, M01_AXI_rvalid, M01_AXI_wdata, M01_AXI_wlast, \n  M01_AXI_wready, M01_AXI_wstrb, M01_AXI_wvalid, M02_AXI_araddr, M02_AXI_arburst, \n  M02_AXI_arcache, M02_AXI_arid, M02_AXI_arlen, M02_AXI_arlock, M02_AXI_arprot, \n  M02_AXI_arqos, M02_AXI_arready, M02_AXI_arregion, M02_AXI_arsize, M02_AXI_arvalid, \n  M02_AXI_awaddr, M02_AXI_awburst, M02_AXI_awcache, M02_AXI_awid, M02_AXI_awlen, \n  M02_AXI_awlock, M02_AXI_awprot, M02_AXI_awqos, M02_AXI_awready, M02_AXI_awregion, \n  M02_AXI_awsize, M02_AXI_awvalid, M02_AXI_bid, M02_AXI_bready, M02_AXI_bresp, \n  M02_AXI_bvalid, M02_AXI_rdata, M02_AXI_rid, M02_AXI_rlast, M02_AXI_rready, M02_AXI_rresp, \n  M02_AXI_rvalid, M02_AXI_wdata, M02_AXI_wlast, M02_AXI_wready, M02_AXI_wstrb, \n  M02_AXI_wvalid, M03_AXI_araddr, M03_AXI_arburst, M03_AXI_arcache, M03_AXI_arid, \n  M03_AXI_arlen, M03_AXI_arlock, M03_AXI_arprot, M03_AXI_arqos, M03_AXI_arready, \n  M03_AXI_arregion, M03_AXI_arsize, M03_AXI_arvalid, M03_AXI_awaddr, M03_AXI_awburst, \n  M03_AXI_awcache, M03_AXI_awid, M03_AXI_awlen, M03_AXI_awlock, M03_AXI_awprot, \n  M03_AXI_awqos, M03_AXI_awready, M03_AXI_awregion, M03_AXI_awsize, M03_AXI_awvalid, \n  M03_AXI_bid, M03_AXI_bready, M03_AXI_bresp, M03_AXI_bvalid, M03_AXI_rdata, M03_AXI_rid, \n  M03_AXI_rlast, M03_AXI_rready, M03_AXI_rresp, M03_AXI_rvalid, M03_AXI_wdata, M03_AXI_wlast, \n  M03_AXI_wready, M03_AXI_wstrb, M03_AXI_wvalid, S00_AXI_araddr, S00_AXI_arburst, \n  S00_AXI_arcache, S00_AXI_arid, S00_AXI_arlen, S00_AXI_arlock, S00_AXI_arprot, \n  S00_AXI_arqos, S00_AXI_arready, S00_AXI_arregion, S00_AXI_arsize, S00_AXI_arvalid, \n  S00_AXI_awaddr, S00_AXI_awburst, S00_AXI_awcache, S00_AXI_awid, S00_AXI_awlen, \n  S00_AXI_awlock, S00_AXI_awprot, S00_AXI_awqos, S00_AXI_awready, S00_AXI_awregion, \n  S00_AXI_awsize, S00_AXI_awvalid, S00_AXI_bid, S00_AXI_bready, S00_AXI_bresp, \n  S00_AXI_bvalid, S00_AXI_rdata, S00_AXI_rid, S00_AXI_rlast, S00_AXI_rready, S00_AXI_rresp, \n  S00_AXI_rvalid, S00_AXI_wdata, S00_AXI_wlast, S00_AXI_wready, S00_AXI_wstrb, \n  S00_AXI_wvalid, S01_AXI_araddr, S01_AXI_arburst, S01_AXI_arcache, S01_AXI_arid, \n  S01_AXI_arlen, S01_AXI_arlock, S01_AXI_arprot, S01_AXI_arqos, S01_AXI_arready, \n  S01_AXI_arregion, S01_AXI_arsize, S01_AXI_arvalid, S01_AXI_awaddr, S01_AXI_awburst, \n  S01_AXI_awcache, S01_AXI_awid, S01_AXI_awlen, S01_AXI_awlock, S01_AXI_awprot, \n  S01_AXI_awqos, S01_AXI_awready, S01_AXI_awregion, S01_AXI_awsize, S01_AXI_awvalid, \n  S01_AXI_bid, S01_AXI_bready, S01_AXI_bresp, S01_AXI_bvalid, S01_AXI_rdata, S01_AXI_rid, \n  S01_AXI_rlast, S01_AXI_rready, S01_AXI_rresp, S01_AXI_rvalid, S01_AXI_wdata, S01_AXI_wlast, \n  S01_AXI_wready, S01_AXI_wstrb, S01_AXI_wvalid)\n/* synthesis syn_black_box black_box_pad_pin=\"ACLK,ARESETN,M00_AXI_araddr[63:0],M00_AXI_arburst[1:0],M00_AXI_arcache[3:0],M00_AXI_arid[6:0],M00_AXI_arlen[7:0],M00_AXI_arlock[0:0],M00_AXI_arprot[2:0],M00_AXI_arqos[3:0],M00_AXI_arready,M00_AXI_arregion[3:0],M00_AXI_arsize[2:0],M00_AXI_arvalid,M00_AXI_awaddr[63:0],M00_AXI_awburst[1:0],M00_AXI_awcache[3:0],M00_AXI_awid[6:0],M00_AXI_awlen[7:0],M00_AXI_awlock[0:0],M00_AXI_awprot[2:0],M00_AXI_awqos[3:0],M00_AXI_awready,M00_AXI_awregion[3:0],M00_AXI_awsize[2:0],M00_AXI_awvalid,M00_AXI_bid[6:0],M00_AXI_bready,M00_AXI_bresp[1:0],M00_AXI_bvalid,M00_AXI_rdata[511:0],M00_AXI_rid[6:0],M00_AXI_rlast,M00_AXI_rready,M00_AXI_rresp[1:0],M00_AXI_rvalid,M00_AXI_wdata[511:0],M00_AXI_wlast,M00_AXI_wready,M00_AXI_wstrb[63:0],M00_AXI_wvalid,M01_AXI_araddr[63:0],M01_AXI_arburst[1:0],M01_AXI_arcache[3:0],M01_AXI_arid[6:0],M01_AXI_arlen[7:0],M01_AXI_arlock[0:0],M01_AXI_arprot[2:0],M01_AXI_arqos[3:0],M01_AXI_arready,M01_AXI_arregion[3:0],M01_AXI_arsize[2:0],M01_AXI_arvalid,M01_AXI_awaddr[63:0],M01_AXI_awburst[1:0],M01_AXI_awcache[3:0],M01_AXI_awid[6:0],M01_AXI_awlen[7:0],M01_AXI_awlock[0:0],M01_AXI_awprot[2:0],M01_AXI_awqos[3:0],M01_AXI_awready,M01_AXI_awregion[3:0],M01_AXI_awsize[2:0],M01_AXI_awvalid,M01_AXI_bid[6:0],M01_AXI_bready,M01_AXI_bresp[1:0],M01_AXI_bvalid,M01_AXI_rdata[511:0],M01_AXI_rid[6:0],M01_AXI_rlast,M01_AXI_rready,M01_AXI_rresp[1:0],M01_AXI_rvalid,M01_AXI_wdata[511:0],M01_AXI_wlast,M01_AXI_wready,M01_AXI_wstrb[63:0],M01_AXI_wvalid,M02_AXI_araddr[63:0],M02_AXI_arburst[1:0],M02_AXI_arcache[3:0],M02_AXI_arid[6:0],M02_AXI_arlen[7:0],M02_AXI_arlock[0:0],M02_AXI_arprot[2:0],M02_AXI_arqos[3:0],M02_AXI_arready,M02_AXI_arregion[3:0],M02_AXI_arsize[2:0],M02_AXI_arvalid,M02_AXI_awaddr[63:0],M02_AXI_awburst[1:0],M02_AXI_awcache[3:0],M02_AXI_awid[6:0],M02_AXI_awlen[7:0],M02_AXI_awlock[0:0],M02_AXI_awprot[2:0],M02_AXI_awqos[3:0],M02_AXI_awready,M02_AXI_awregion[3:0],M02_AXI_awsize[2:0],M02_AXI_awvalid,M02_AXI_bid[6:0],M02_AXI_bready,M02_AXI_bresp[1:0],M02_AXI_bvalid,M02_AXI_rdata[511:0],M02_AXI_rid[6:0],M02_AXI_rlast,M02_AXI_rready,M02_AXI_rresp[1:0],M02_AXI_rvalid,M02_AXI_wdata[511:0],M02_AXI_wlast,M02_AXI_wready,M02_AXI_wstrb[63:0],M02_AXI_wvalid,M03_AXI_araddr[63:0],M03_AXI_arburst[1:0],M03_AXI_arcache[3:0],M03_AXI_arid[6:0],M03_AXI_arlen[7:0],M03_AXI_arlock[0:0],M03_AXI_arprot[2:0],M03_AXI_arqos[3:0],M03_AXI_arready,M03_AXI_arregion[3:0],M03_AXI_arsize[2:0],M03_AXI_arvalid,M03_AXI_awaddr[63:0],M03_AXI_awburst[1:0],M03_AXI_awcache[3:0],M03_AXI_awid[6:0],M03_AXI_awlen[7:0],M03_AXI_awlock[0:0],M03_AXI_awprot[2:0],M03_AXI_awqos[3:0],M03_AXI_awready,M03_AXI_awregion[3:0],M03_AXI_awsize[2:0],M03_AXI_awvalid,M03_AXI_bid[6:0],M03_AXI_bready,M03_AXI_bresp[1:0],M03_AXI_bvalid,M03_AXI_rdata[511:0],M03_AXI_rid[6:0],M03_AXI_rlast,M03_AXI_rready,M03_AXI_rresp[1:0],M03_AXI_rvalid,M03_AXI_wdata[511:0],M03_AXI_wlast,M03_AXI_wready,M03_AXI_wstrb[63:0],M03_AXI_wvalid,S00_AXI_araddr[63:0],S00_AXI_arburst[1:0],S00_AXI_arcache[3:0],S00_AXI_arid[5:0],S00_AXI_arlen[7:0],S00_AXI_arlock[0:0],S00_AXI_arprot[2:0],S00_AXI_arqos[3:0],S00_AXI_arready,S00_AXI_arregion[3:0],S00_AXI_arsize[2:0],S00_AXI_arvalid,S00_AXI_awaddr[63:0],S00_AXI_awburst[1:0],S00_AXI_awcache[3:0],S00_AXI_awid[5:0],S00_AXI_awlen[7:0],S00_AXI_awlock[0:0],S00_AXI_awprot[2:0],S00_AXI_awqos[3:0],S00_AXI_awready,S00_AXI_awregion[3:0],S00_AXI_awsize[2:0],S00_AXI_awvalid,S00_AXI_bid[5:0],S00_AXI_bready,S00_AXI_bresp[1:0],S00_AXI_bvalid,S00_AXI_rdata[511:0],S00_AXI_rid[5:0],S00_AXI_rlast,S00_AXI_rready,S00_AXI_rresp[1:0],S00_AXI_rvalid,S00_AXI_wdata[511:0],S00_AXI_wlast,S00_AXI_wready,S00_AXI_wstrb[63:0],S00_AXI_wvalid,S01_AXI_araddr[63:0],S01_AXI_arburst[1:0],S01_AXI_arcache[3:0],S01_AXI_arid[5:0],S01_AXI_arlen[7:0],S01_AXI_arlock[0:0],S01_AXI_arprot[2:0],S01_AXI_arqos[3:0],S01_AXI_arready,S01_AXI_arregion[3:0],S01_AXI_arsize[2:0],S01_AXI_arvalid,S01_AXI_awaddr[63:0],S01_AXI_awburst[1:0],S01_AXI_awcache[3:0],S01_AXI_awid[5:0],S01_AXI_awlen[7:0],S01_AXI_awlock[0:0],S01_AXI_awprot[2:0],S01_AXI_awqos[3:0],S01_AXI_awready,S01_AXI_awregion[3:0],S01_AXI_awsize[2:0],S01_AXI_awvalid,S01_AXI_bid[5:0],S01_AXI_bready,S01_AXI_bresp[1:0],S01_AXI_bvalid,S01_AXI_rdata[511:0],S01_AXI_rid[5:0],S01_AXI_rlast,S01_AXI_rready,S01_AXI_rresp[1:0],S01_AXI_rvalid,S01_AXI_wdata[511:0],S01_AXI_wlast,S01_AXI_wready,S01_AXI_wstrb[63:0],S01_AXI_wvalid\" */;\n  input ACLK;\n  input ARESETN;\n  output [63:0]M00_AXI_araddr;\n  output [1:0]M00_AXI_arburst;\n  output [3:0]M00_AXI_arcache;\n  output [6:0]M00_AXI_arid;\n  output [7:0]M00_AXI_arlen;\n  output [0:0]M00_AXI_arlock;\n  output [2:0]M00_AXI_arprot;\n  output [3:0]M00_AXI_arqos;\n  input M00_AXI_arready;\n  output [3:0]M00_AXI_arregion;\n  output [2:0]M00_AXI_arsize;\n  output M00_AXI_arvalid;\n  output [63:0]M00_AXI_awaddr;\n  output [1:0]M00_AXI_awburst;\n  output [3:0]M00_AXI_awcache;\n  output [6:0]M00_AXI_awid;\n  output [7:0]M00_AXI_awlen;\n  output [0:0]M00_AXI_awlock;\n  output [2:0]M00_AXI_awprot;\n  output [3:0]M00_AXI_awqos;\n  input M00_AXI_awready;\n  output [3:0]M00_AXI_awregion;\n  output [2:0]M00_AXI_awsize;\n  output M00_AXI_awvalid;\n  input [6:0]M00_AXI_bid;\n  output M00_AXI_bready;\n  input [1:0]M00_AXI_bresp;\n  input M00_AXI_bvalid;\n  input [511:0]M00_AXI_rdata;\n  input [6:0]M00_AXI_rid;\n  input M00_AXI_rlast;\n  output M00_AXI_rready;\n  input [1:0]M00_AXI_rresp;\n  input M00_AXI_rvalid;\n  output [511:0]M00_AXI_wdata;\n  output M00_AXI_wlast;\n  input M00_AXI_wready;\n  output [63:0]M00_AXI_wstrb;\n  output M00_AXI_wvalid;\n  output [63:0]M01_AXI_araddr;\n  output [1:0]M01_AXI_arburst;\n  output [3:0]M01_AXI_arcache;\n  output [6:0]M01_AXI_arid;\n  output [7:0]M01_AXI_arlen;\n  output [0:0]M01_AXI_arlock;\n  output [2:0]M01_AXI_arprot;\n  output [3:0]M01_AXI_arqos;\n  input M01_AXI_arready;\n  output [3:0]M01_AXI_arregion;\n  output [2:0]M01_AXI_arsize;\n  output M01_AXI_arvalid;\n  output [63:0]M01_AXI_awaddr;\n  output [1:0]M01_AXI_awburst;\n  output [3:0]M01_AXI_awcache;\n  output [6:0]M01_AXI_awid;\n  output [7:0]M01_AXI_awlen;\n  output [0:0]M01_AXI_awlock;\n  output [2:0]M01_AXI_awprot;\n  output [3:0]M01_AXI_awqos;\n  input M01_AXI_awready;\n  output [3:0]M01_AXI_awregion;\n  output [2:0]M01_AXI_awsize;\n  output M01_AXI_awvalid;\n  input [6:0]M01_AXI_bid;\n  output M01_AXI_bready;\n  input [1:0]M01_AXI_bresp;\n  input M01_AXI_bvalid;\n  input [511:0]M01_AXI_rdata;\n  input [6:0]M01_AXI_rid;\n  input M01_AXI_rlast;\n  output M01_AXI_rready;\n  input [1:0]M01_AXI_rresp;\n  input M01_AXI_rvalid;\n  output [511:0]M01_AXI_wdata;\n  output M01_AXI_wlast;\n  input M01_AXI_wready;\n  output [63:0]M01_AXI_wstrb;\n  output M01_AXI_wvalid;\n  output [63:0]M02_AXI_araddr;\n  output [1:0]M02_AXI_arburst;\n  output [3:0]M02_AXI_arcache;\n  output [6:0]M02_AXI_arid;\n  output [7:0]M02_AXI_arlen;\n  output [0:0]M02_AXI_arlock;\n  output [2:0]M02_AXI_arprot;\n  output [3:0]M02_AXI_arqos;\n  input M02_AXI_arready;\n  output [3:0]M02_AXI_arregion;\n  output [2:0]M02_AXI_arsize;\n  output M02_AXI_arvalid;\n  output [63:0]M02_AXI_awaddr;\n  output [1:0]M02_AXI_awburst;\n  output [3:0]M02_AXI_awcache;\n  output [6:0]M02_AXI_awid;\n  output [7:0]M02_AXI_awlen;\n  output [0:0]M02_AXI_awlock;\n  output [2:0]M02_AXI_awprot;\n  output [3:0]M02_AXI_awqos;\n  input M02_AXI_awready;\n  output [3:0]M02_AXI_awregion;\n  output [2:0]M02_AXI_awsize;\n  output M02_AXI_awvalid;\n  input [6:0]M02_AXI_bid;\n  output M02_AXI_bready;\n  input [1:0]M02_AXI_bresp;\n  input M02_AXI_bvalid;\n  input [511:0]M02_AXI_rdata;\n  input [6:0]M02_AXI_rid;\n  input M02_AXI_rlast;\n  output M02_AXI_rready;\n  input [1:0]M02_AXI_rresp;\n  input M02_AXI_rvalid;\n  output [511:0]M02_AXI_wdata;\n  output M02_AXI_wlast;\n  input M02_AXI_wready;\n  output [63:0]M02_AXI_wstrb;\n  output M02_AXI_wvalid;\n  output [63:0]M03_AXI_araddr;\n  output [1:0]M03_AXI_arburst;\n  output [3:0]M03_AXI_arcache;\n  output [6:0]M03_AXI_arid;\n  output [7:0]M03_AXI_arlen;\n  output [0:0]M03_AXI_arlock;\n  output [2:0]M03_AXI_arprot;\n  output [3:0]M03_AXI_arqos;\n  input M03_AXI_arready;\n  output [3:0]M03_AXI_arregion;\n  output [2:0]M03_AXI_arsize;\n  output M03_AXI_arvalid;\n  output [63:0]M03_AXI_awaddr;\n  output [1:0]M03_AXI_awburst;\n  output [3:0]M03_AXI_awcache;\n  output [6:0]M03_AXI_awid;\n  output [7:0]M03_AXI_awlen;\n  output [0:0]M03_AXI_awlock;\n  output [2:0]M03_AXI_awprot;\n  output [3:0]M03_AXI_awqos;\n  input M03_AXI_awready;\n  output [3:0]M03_AXI_awregion;\n  output [2:0]M03_AXI_awsize;\n  output M03_AXI_awvalid;\n  input [6:0]M03_AXI_bid;\n  output M03_AXI_bready;\n  input [1:0]M03_AXI_bresp;\n  input M03_AXI_bvalid;\n  input [511:0]M03_AXI_rdata;\n  input [6:0]M03_AXI_rid;\n  input M03_AXI_rlast;\n  output M03_AXI_rready;\n  input [1:0]M03_AXI_rresp;\n  input M03_AXI_rvalid;\n  output [511:0]M03_AXI_wdata;\n  output M03_AXI_wlast;\n  input M03_AXI_wready;\n  output [63:0]M03_AXI_wstrb;\n  output M03_AXI_wvalid;\n  input [63:0]S00_AXI_araddr;\n  input [1:0]S00_AXI_arburst;\n  input [3:0]S00_AXI_arcache;\n  input [5:0]S00_AXI_arid;\n  input [7:0]S00_AXI_arlen;\n  input [0:0]S00_AXI_arlock;\n  input [2:0]S00_AXI_arprot;\n  input [3:0]S00_AXI_arqos;\n  output S00_AXI_arready;\n  input [3:0]S00_AXI_arregion;\n  input [2:0]S00_AXI_arsize;\n  input S00_AXI_arvalid;\n  input [63:0]S00_AXI_awaddr;\n  input [1:0]S00_AXI_awburst;\n  input [3:0]S00_AXI_awcache;\n  input [5:0]S00_AXI_awid;\n  input [7:0]S00_AXI_awlen;\n  input [0:0]S00_AXI_awlock;\n  input [2:0]S00_AXI_awprot;\n  input [3:0]S00_AXI_awqos;\n  output S00_AXI_awready;\n  input [3:0]S00_AXI_awregion;\n  input [2:0]S00_AXI_awsize;\n  input S00_AXI_awvalid;\n  output [5:0]S00_AXI_bid;\n  input S00_AXI_bready;\n  output [1:0]S00_AXI_bresp;\n  output S00_AXI_bvalid;\n  output [511:0]S00_AXI_rdata;\n  output [5:0]S00_AXI_rid;\n  output S00_AXI_rlast;\n  input S00_AXI_rready;\n  output [1:0]S00_AXI_rresp;\n  output S00_AXI_rvalid;\n  input [511:0]S00_AXI_wdata;\n  input S00_AXI_wlast;\n  output S00_AXI_wready;\n  input [63:0]S00_AXI_wstrb;\n  input S00_AXI_wvalid;\n  input [63:0]S01_AXI_araddr;\n  input [1:0]S01_AXI_arburst;\n  input [3:0]S01_AXI_arcache;\n  input [5:0]S01_AXI_arid;\n  input [7:0]S01_AXI_arlen;\n  input [0:0]S01_AXI_arlock;\n  input [2:0]S01_AXI_arprot;\n  input [3:0]S01_AXI_arqos;\n  output S01_AXI_arready;\n  input [3:0]S01_AXI_arregion;\n  input [2:0]S01_AXI_arsize;\n  input S01_AXI_arvalid;\n  input [63:0]S01_AXI_awaddr;\n  input [1:0]S01_AXI_awburst;\n  input [3:0]S01_AXI_awcache;\n  input [5:0]S01_AXI_awid;\n  input [7:0]S01_AXI_awlen;\n  input [0:0]S01_AXI_awlock;\n  input [2:0]S01_AXI_awprot;\n  input [3:0]S01_AXI_awqos;\n  output S01_AXI_awready;\n  input [3:0]S01_AXI_awregion;\n  input [2:0]S01_AXI_awsize;\n  input S01_AXI_awvalid;\n  output [5:0]S01_AXI_bid;\n  input S01_AXI_bready;\n  output [1:0]S01_AXI_bresp;\n  output S01_AXI_bvalid;\n  output [511:0]S01_AXI_rdata;\n  output [5:0]S01_AXI_rid;\n  output S01_AXI_rlast;\n  input S01_AXI_rready;\n  output [1:0]S01_AXI_rresp;\n  output S01_AXI_rvalid;\n  input [511:0]S01_AXI_wdata;\n  input S01_AXI_wlast;\n  output S01_AXI_wready;\n  input [63:0]S01_AXI_wstrb;\n  input S01_AXI_wvalid;\nendmodule\n", "num_lines": 300}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Tool Version: Vivado v.2017.4.op (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017\n//Date        : Tue May 22 11:47:37 2018\n//Host        : ip-10-206-20-46 running 64-bit CentOS release 6.5 (Final)\n//Command     : generate_target cl_axi_interconnect_wrapper.bd\n//Design      : cl_axi_interconnect_wrapper\n//Purpose     : IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule cl_axi_interconnect_wrapper\n   (ACLK,\n    ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  input ACLK;\n  input ARESETN;\n  output [63:0]M00_AXI_araddr;\n  output [1:0]M00_AXI_arburst;\n  output [3:0]M00_AXI_arcache;\n  output [6:0]M00_AXI_arid;\n  output [7:0]M00_AXI_arlen;\n  output [0:0]M00_AXI_arlock;\n  output [2:0]M00_AXI_arprot;\n  output [3:0]M00_AXI_arqos;\n  input M00_AXI_arready;\n  output [3:0]M00_AXI_arregion;\n  output [2:0]M00_AXI_arsize;\n  output M00_AXI_arvalid;\n  output [63:0]M00_AXI_awaddr;\n  output [1:0]M00_AXI_awburst;\n  output [3:0]M00_AXI_awcache;\n  output [6:0]M00_AXI_awid;\n  output [7:0]M00_AXI_awlen;\n  output [0:0]M00_AXI_awlock;\n  output [2:0]M00_AXI_awprot;\n  output [3:0]M00_AXI_awqos;\n  input M00_AXI_awready;\n  output [3:0]M00_AXI_awregion;\n  output [2:0]M00_AXI_awsize;\n  output M00_AXI_awvalid;\n  input [6:0]M00_AXI_bid;\n  output M00_AXI_bready;\n  input [1:0]M00_AXI_bresp;\n  input M00_AXI_bvalid;\n  input [511:0]M00_AXI_rdata;\n  input [6:0]M00_AXI_rid;\n  input M00_AXI_rlast;\n  output M00_AXI_rready;\n  input [1:0]M00_AXI_rresp;\n  input M00_AXI_rvalid;\n  output [511:0]M00_AXI_wdata;\n  output M00_AXI_wlast;\n  input M00_AXI_wready;\n  output [63:0]M00_AXI_wstrb;\n  output M00_AXI_wvalid;\n  output [63:0]M01_AXI_araddr;\n  output [1:0]M01_AXI_arburst;\n  output [3:0]M01_AXI_arcache;\n  output [6:0]M01_AXI_arid;\n  output [7:0]M01_AXI_arlen;\n  output [0:0]M01_AXI_arlock;\n  output [2:0]M01_AXI_arprot;\n  output [3:0]M01_AXI_arqos;\n  input M01_AXI_arready;\n  output [3:0]M01_AXI_arregion;\n  output [2:0]M01_AXI_arsize;\n  output M01_AXI_arvalid;\n  output [63:0]M01_AXI_awaddr;\n  output [1:0]M01_AXI_awburst;\n  output [3:0]M01_AXI_awcache;\n  output [6:0]M01_AXI_awid;\n  output [7:0]M01_AXI_awlen;\n  output [0:0]M01_AXI_awlock;\n  output [2:0]M01_AXI_awprot;\n  output [3:0]M01_AXI_awqos;\n  input M01_AXI_awready;\n  output [3:0]M01_AXI_awregion;\n  output [2:0]M01_AXI_awsize;\n  output M01_AXI_awvalid;\n  input [6:0]M01_AXI_bid;\n  output M01_AXI_bready;\n  input [1:0]M01_AXI_bresp;\n  input M01_AXI_bvalid;\n  input [511:0]M01_AXI_rdata;\n  input [6:0]M01_AXI_rid;\n  input M01_AXI_rlast;\n  output M01_AXI_rready;\n  input [1:0]M01_AXI_rresp;\n  input M01_AXI_rvalid;\n  output [511:0]M01_AXI_wdata;\n  output M01_AXI_wlast;\n  input M01_AXI_wready;\n  output [63:0]M01_AXI_wstrb;\n  output M01_AXI_wvalid;\n  output [63:0]M02_AXI_araddr;\n  output [1:0]M02_AXI_arburst;\n  output [3:0]M02_AXI_arcache;\n  output [6:0]M02_AXI_arid;\n  output [7:0]M02_AXI_arlen;\n  output [0:0]M02_AXI_arlock;\n  output [2:0]M02_AXI_arprot;\n  output [3:0]M02_AXI_arqos;\n  input M02_AXI_arready;\n  output [3:0]M02_AXI_arregion;\n  output [2:0]M02_AXI_arsize;\n  output M02_AXI_arvalid;\n  output [63:0]M02_AXI_awaddr;\n  output [1:0]M02_AXI_awburst;\n  output [3:0]M02_AXI_awcache;\n  output [6:0]M02_AXI_awid;\n  output [7:0]M02_AXI_awlen;\n  output [0:0]M02_AXI_awlock;\n  output [2:0]M02_AXI_awprot;\n  output [3:0]M02_AXI_awqos;\n  input M02_AXI_awready;\n  output [3:0]M02_AXI_awregion;\n  output [2:0]M02_AXI_awsize;\n  output M02_AXI_awvalid;\n  input [6:0]M02_AXI_bid;\n  output M02_AXI_bready;\n  input [1:0]M02_AXI_bresp;\n  input M02_AXI_bvalid;\n  input [511:0]M02_AXI_rdata;\n  input [6:0]M02_AXI_rid;\n  input M02_AXI_rlast;\n  output M02_AXI_rready;\n  input [1:0]M02_AXI_rresp;\n  input M02_AXI_rvalid;\n  output [511:0]M02_AXI_wdata;\n  output M02_AXI_wlast;\n  input M02_AXI_wready;\n  output [63:0]M02_AXI_wstrb;\n  output M02_AXI_wvalid;\n  output [63:0]M03_AXI_araddr;\n  output [1:0]M03_AXI_arburst;\n  output [3:0]M03_AXI_arcache;\n  output [6:0]M03_AXI_arid;\n  output [7:0]M03_AXI_arlen;\n  output [0:0]M03_AXI_arlock;\n  output [2:0]M03_AXI_arprot;\n  output [3:0]M03_AXI_arqos;\n  input M03_AXI_arready;\n  output [3:0]M03_AXI_arregion;\n  output [2:0]M03_AXI_arsize;\n  output M03_AXI_arvalid;\n  output [63:0]M03_AXI_awaddr;\n  output [1:0]M03_AXI_awburst;\n  output [3:0]M03_AXI_awcache;\n  output [6:0]M03_AXI_awid;\n  output [7:0]M03_AXI_awlen;\n  output [0:0]M03_AXI_awlock;\n  output [2:0]M03_AXI_awprot;\n  output [3:0]M03_AXI_awqos;\n  input M03_AXI_awready;\n  output [3:0]M03_AXI_awregion;\n  output [2:0]M03_AXI_awsize;\n  output M03_AXI_awvalid;\n  input [6:0]M03_AXI_bid;\n  output M03_AXI_bready;\n  input [1:0]M03_AXI_bresp;\n  input M03_AXI_bvalid;\n  input [511:0]M03_AXI_rdata;\n  input [6:0]M03_AXI_rid;\n  input M03_AXI_rlast;\n  output M03_AXI_rready;\n  input [1:0]M03_AXI_rresp;\n  input M03_AXI_rvalid;\n  output [511:0]M03_AXI_wdata;\n  output M03_AXI_wlast;\n  input M03_AXI_wready;\n  output [63:0]M03_AXI_wstrb;\n  output M03_AXI_wvalid;\n  input [63:0]S00_AXI_araddr;\n  input [1:0]S00_AXI_arburst;\n  input [3:0]S00_AXI_arcache;\n  input [5:0]S00_AXI_arid;\n  input [7:0]S00_AXI_arlen;\n  input [0:0]S00_AXI_arlock;\n  input [2:0]S00_AXI_arprot;\n  input [3:0]S00_AXI_arqos;\n  output S00_AXI_arready;\n  input [3:0]S00_AXI_arregion;\n  input [2:0]S00_AXI_arsize;\n  input S00_AXI_arvalid;\n  input [63:0]S00_AXI_awaddr;\n  input [1:0]S00_AXI_awburst;\n  input [3:0]S00_AXI_awcache;\n  input [5:0]S00_AXI_awid;\n  input [7:0]S00_AXI_awlen;\n  input [0:0]S00_AXI_awlock;\n  input [2:0]S00_AXI_awprot;\n  input [3:0]S00_AXI_awqos;\n  output S00_AXI_awready;\n  input [3:0]S00_AXI_awregion;\n  input [2:0]S00_AXI_awsize;\n  input S00_AXI_awvalid;\n  output [5:0]S00_AXI_bid;\n  input S00_AXI_bready;\n  output [1:0]S00_AXI_bresp;\n  output S00_AXI_bvalid;\n  output [511:0]S00_AXI_rdata;\n  output [5:0]S00_AXI_rid;\n  output S00_AXI_rlast;\n  input S00_AXI_rready;\n  output [1:0]S00_AXI_rresp;\n  output S00_AXI_rvalid;\n  input [511:0]S00_AXI_wdata;\n  input S00_AXI_wlast;\n  output S00_AXI_wready;\n  input [63:0]S00_AXI_wstrb;\n  input S00_AXI_wvalid;\n  input [63:0]S01_AXI_araddr;\n  input [1:0]S01_AXI_arburst;\n  input [3:0]S01_AXI_arcache;\n  input [5:0]S01_AXI_arid;\n  input [7:0]S01_AXI_arlen;\n  input [0:0]S01_AXI_arlock;\n  input [2:0]S01_AXI_arprot;\n  input [3:0]S01_AXI_arqos;\n  output S01_AXI_arready;\n  input [3:0]S01_AXI_arregion;\n  input [2:0]S01_AXI_arsize;\n  input S01_AXI_arvalid;\n  input [63:0]S01_AXI_awaddr;\n  input [1:0]S01_AXI_awburst;\n  input [3:0]S01_AXI_awcache;\n  input [5:0]S01_AXI_awid;\n  input [7:0]S01_AXI_awlen;\n  input [0:0]S01_AXI_awlock;\n  input [2:0]S01_AXI_awprot;\n  input [3:0]S01_AXI_awqos;\n  output S01_AXI_awready;\n  input [3:0]S01_AXI_awregion;\n  input [2:0]S01_AXI_awsize;\n  input S01_AXI_awvalid;\n  output [5:0]S01_AXI_bid;\n  input S01_AXI_bready;\n  output [1:0]S01_AXI_bresp;\n  output S01_AXI_bvalid;\n  output [511:0]S01_AXI_rdata;\n  output [5:0]S01_AXI_rid;\n  output S01_AXI_rlast;\n  input S01_AXI_rready;\n  output [1:0]S01_AXI_rresp;\n  output S01_AXI_rvalid;\n  input [511:0]S01_AXI_wdata;\n  input S01_AXI_wlast;\n  output S01_AXI_wready;\n  input [63:0]S01_AXI_wstrb;\n  input S01_AXI_wvalid;\n\n  wire ACLK;\n  wire ARESETN;\n  wire [63:0]M00_AXI_araddr;\n  wire [1:0]M00_AXI_arburst;\n  wire [3:0]M00_AXI_arcache;\n  wire [6:0]M00_AXI_arid;\n  wire [7:0]M00_AXI_arlen;\n  wire [0:0]M00_AXI_arlock;\n  wire [2:0]M00_AXI_arprot;\n  wire [3:0]M00_AXI_arqos;\n  wire M00_AXI_arready;\n  wire [3:0]M00_AXI_arregion;\n  wire [2:0]M00_AXI_arsize;\n  wire M00_AXI_arvalid;\n  wire [63:0]M00_AXI_awaddr;\n  wire [1:0]M00_AXI_awburst;\n  wire [3:0]M00_AXI_awcache;\n  wire [6:0]M00_AXI_awid;\n  wire [7:0]M00_AXI_awlen;\n  wire [0:0]M00_AXI_awlock;\n  wire [2:0]M00_AXI_awprot;\n  wire [3:0]M00_AXI_awqos;\n  wire M00_AXI_awready;\n  wire [3:0]M00_AXI_awregion;\n  wire [2:0]M00_AXI_awsize;\n  wire M00_AXI_awvalid;\n  wire [6:0]M00_AXI_bid;\n  wire M00_AXI_bready;\n  wire [1:0]M00_AXI_bresp;\n  wire M00_AXI_bvalid;\n  wire [511:0]M00_AXI_rdata;\n  wire [6:0]M00_AXI_rid;\n  wire M00_AXI_rlast;\n  wire M00_AXI_rready;\n  wire [1:0]M00_AXI_rresp;\n  wire M00_AXI_rvalid;\n  wire [511:0]M00_AXI_wdata;\n  wire M00_AXI_wlast;\n  wire M00_AXI_wready;\n  wire [63:0]M00_AXI_wstrb;\n  wire M00_AXI_wvalid;\n  wire [63:0]M01_AXI_araddr;\n  wire [1:0]M01_AXI_arburst;\n  wire [3:0]M01_AXI_arcache;\n  wire [6:0]M01_AXI_arid;\n  wire [7:0]M01_AXI_arlen;\n  wire [0:0]M01_AXI_arlock;\n  wire [2:0]M01_AXI_arprot;\n  wire [3:0]M01_AXI_arqos;\n  wire M01_AXI_arready;\n  wire [3:0]M01_AXI_arregion;\n  wire [2:0]M01_AXI_arsize;\n  wire M01_AXI_arvalid;\n  wire [63:0]M01_AXI_awaddr;\n  wire [1:0]M01_AXI_awburst;\n  wire [3:0]M01_AXI_awcache;\n  wire [6:0]M01_AXI_awid;\n  wire [7:0]M01_AXI_awlen;\n  wire [0:0]M01_AXI_awlock;\n  wire [2:0]M01_AXI_awprot;\n  wire [3:0]M01_AXI_awqos;\n  wire M01_AXI_awready;\n  wire [3:0]M01_AXI_awregion;\n  wire [2:0]M01_AXI_awsize;\n  wire M01_AXI_awvalid;\n  wire [6:0]M01_AXI_bid;\n  wire M01_AXI_bready;\n  wire [1:0]M01_AXI_bresp;\n  wire M01_AXI_bvalid;\n  wire [511:0]M01_AXI_rdata;\n  wire [6:0]M01_AXI_rid;\n  wire M01_AXI_rlast;\n  wire M01_AXI_rready;\n  wire [1:0]M01_AXI_rresp;\n  wire M01_AXI_rvalid;\n  wire [511:0]M01_AXI_wdata;\n  wire M01_AXI_wlast;\n  wire M01_AXI_wready;\n  wire [63:0]M01_AXI_wstrb;\n  wire M01_AXI_wvalid;\n  wire [63:0]M02_AXI_araddr;\n  wire [1:0]M02_AXI_arburst;\n  wire [3:0]M02_AXI_arcache;\n  wire [6:0]M02_AXI_arid;\n  wire [7:0]M02_AXI_arlen;\n  wire [0:0]M02_AXI_arlock;\n  wire [2:0]M02_AXI_arprot;\n  wire [3:0]M02_AXI_arqos;\n  wire M02_AXI_arready;\n  wire [3:0]M02_AXI_arregion;\n  wire [2:0]M02_AXI_arsize;\n  wire M02_AXI_arvalid;\n  wire [63:0]M02_AXI_awaddr;\n  wire [1:0]M02_AXI_awburst;\n  wire [3:0]M02_AXI_awcache;\n  wire [6:0]M02_AXI_awid;\n  wire [7:0]M02_AXI_awlen;\n  wire [0:0]M02_AXI_awlock;\n  wire [2:0]M02_AXI_awprot;\n  wire [3:0]M02_AXI_awqos;\n  wire M02_AXI_awready;\n  wire [3:0]M02_AXI_awregion;\n  wire [2:0]M02_AXI_awsize;\n  wire M02_AXI_awvalid;\n  wire [6:0]M02_AXI_bid;\n  wire M02_AXI_bready;\n  wire [1:0]M02_AXI_bresp;\n  wire M02_AXI_bvalid;\n  wire [511:0]M02_AXI_rdata;\n  wire [6:0]M02_AXI_rid;\n  wire M02_AXI_rlast;\n  wire M02_AXI_rready;\n  wire [1:0]M02_AXI_rresp;\n  wire M02_AXI_rvalid;\n  wire [511:0]M02_AXI_wdata;\n  wire M02_AXI_wlast;\n  wire M02_AXI_wready;\n  wire [63:0]M02_AXI_wstrb;\n  wire M02_AXI_wvalid;\n  wire [63:0]M03_AXI_araddr;\n  wire [1:0]M03_AXI_arburst;\n  wire [3:0]M03_AXI_arcache;\n  wire [6:0]M03_AXI_arid;\n  wire [7:0]M03_AXI_arlen;\n  wire [0:0]M03_AXI_arlock;\n  wire [2:0]M03_AXI_arprot;\n  wire [3:0]M03_AXI_arqos;\n  wire M03_AXI_arready;\n  wire [3:0]M03_AXI_arregion;\n  wire [2:0]M03_AXI_arsize;\n  wire M03_AXI_arvalid;\n  wire [63:0]M03_AXI_awaddr;\n  wire [1:0]M03_AXI_awburst;\n  wire [3:0]M03_AXI_awcache;\n  wire [6:0]M03_AXI_awid;\n  wire [7:0]M03_AXI_awlen;\n  wire [0:0]M03_AXI_awlock;\n  wire [2:0]M03_AXI_awprot;\n  wire [3:0]M03_AXI_awqos;\n  wire M03_AXI_awready;\n  wire [3:0]M03_AXI_awregion;\n  wire [2:0]M03_AXI_awsize;\n  wire M03_AXI_awvalid;\n  wire [6:0]M03_AXI_bid;\n  wire M03_AXI_bready;\n  wire [1:0]M03_AXI_bresp;\n  wire M03_AXI_bvalid;\n  wire [511:0]M03_AXI_rdata;\n  wire [6:0]M03_AXI_rid;\n  wire M03_AXI_rlast;\n  wire M03_AXI_rready;\n  wire [1:0]M03_AXI_rresp;\n  wire M03_AXI_rvalid;\n  wire [511:0]M03_AXI_wdata;\n  wire M03_AXI_wlast;\n  wire M03_AXI_wready;\n  wire [63:0]M03_AXI_wstrb;\n  wire M03_AXI_wvalid;\n  wire [63:0]S00_AXI_araddr;\n  wire [1:0]S00_AXI_arburst;\n  wire [3:0]S00_AXI_arcache;\n  wire [5:0]S00_AXI_arid;\n  wire [7:0]S00_AXI_arlen;\n  wire [0:0]S00_AXI_arlock;\n  wire [2:0]S00_AXI_arprot;\n  wire [3:0]S00_AXI_arqos;\n  wire S00_AXI_arready;\n  wire [3:0]S00_AXI_arregion;\n  wire [2:0]S00_AXI_arsize;\n  wire S00_AXI_arvalid;\n  wire [63:0]S00_AXI_awaddr;\n  wire [1:0]S00_AXI_awburst;\n  wire [3:0]S00_AXI_awcache;\n  wire [5:0]S00_AXI_awid;\n  wire [7:0]S00_AXI_awlen;\n  wire [0:0]S00_AXI_awlock;\n  wire [2:0]S00_AXI_awprot;\n  wire [3:0]S00_AXI_awqos;\n  wire S00_AXI_awready;\n  wire [3:0]S00_AXI_awregion;\n  wire [2:0]S00_AXI_awsize;\n  wire S00_AXI_awvalid;\n  wire [5:0]S00_AXI_bid;\n  wire S00_AXI_bready;\n  wire [1:0]S00_AXI_bresp;\n  wire S00_AXI_bvalid;\n  wire [511:0]S00_AXI_rdata;\n  wire [5:0]S00_AXI_rid;\n  wire S00_AXI_rlast;\n  wire S00_AXI_rready;\n  wire [1:0]S00_AXI_rresp;\n  wire S00_AXI_rvalid;\n  wire [511:0]S00_AXI_wdata;\n  wire S00_AXI_wlast;\n  wire S00_AXI_wready;\n  wire [63:0]S00_AXI_wstrb;\n  wire S00_AXI_wvalid;\n  wire [63:0]S01_AXI_araddr;\n  wire [1:0]S01_AXI_arburst;\n  wire [3:0]S01_AXI_arcache;\n  wire [5:0]S01_AXI_arid;\n  wire [7:0]S01_AXI_arlen;\n  wire [0:0]S01_AXI_arlock;\n  wire [2:0]S01_AXI_arprot;\n  wire [3:0]S01_AXI_arqos;\n  wire S01_AXI_arready;\n  wire [3:0]S01_AXI_arregion;\n  wire [2:0]S01_AXI_arsize;\n  wire S01_AXI_arvalid;\n  wire [63:0]S01_AXI_awaddr;\n  wire [1:0]S01_AXI_awburst;\n  wire [3:0]S01_AXI_awcache;\n  wire [5:0]S01_AXI_awid;\n  wire [7:0]S01_AXI_awlen;\n  wire [0:0]S01_AXI_awlock;\n  wire [2:0]S01_AXI_awprot;\n  wire [3:0]S01_AXI_awqos;\n  wire S01_AXI_awready;\n  wire [3:0]S01_AXI_awregion;\n  wire [2:0]S01_AXI_awsize;\n  wire S01_AXI_awvalid;\n  wire [5:0]S01_AXI_bid;\n  wire S01_AXI_bready;\n  wire [1:0]S01_AXI_bresp;\n  wire S01_AXI_bvalid;\n  wire [511:0]S01_AXI_rdata;\n  wire [5:0]S01_AXI_rid;\n  wire S01_AXI_rlast;\n  wire S01_AXI_rready;\n  wire [1:0]S01_AXI_rresp;\n  wire S01_AXI_rvalid;\n  wire [511:0]S01_AXI_wdata;\n  wire S01_AXI_wlast;\n  wire S01_AXI_wready;\n  wire [63:0]S01_AXI_wstrb;\n  wire S01_AXI_wvalid;\n\n  cl_axi_interconnect cl_axi_interconnect_i\n       (.ACLK(ACLK),\n        .ARESETN(ARESETN),\n        .M00_AXI_araddr(M00_AXI_araddr),\n        .M00_AXI_arburst(M00_AXI_arburst),\n        .M00_AXI_arcache(M00_AXI_arcache),\n        .M00_AXI_arid(M00_AXI_arid),\n        .M00_AXI_arlen(M00_AXI_arlen),\n        .M00_AXI_arlock(M00_AXI_arlock),\n        .M00_AXI_arprot(M00_AXI_arprot),\n        .M00_AXI_arqos(M00_AXI_arqos),\n        .M00_AXI_arready(M00_AXI_arready),\n        .M00_AXI_arregion(M00_AXI_arregion),\n        .M00_AXI_arsize(M00_AXI_arsize),\n        .M00_AXI_arvalid(M00_AXI_arvalid),\n        .M00_AXI_awaddr(M00_AXI_awaddr),\n        .M00_AXI_awburst(M00_AXI_awburst),\n        .M00_AXI_awcache(M00_AXI_awcache),\n        .M00_AXI_awid(M00_AXI_awid),\n        .M00_AXI_awlen(M00_AXI_awlen),\n        .M00_AXI_awlock(M00_AXI_awlock),\n        .M00_AXI_awprot(M00_AXI_awprot),\n        .M00_AXI_awqos(M00_AXI_awqos),\n        .M00_AXI_awready(M00_AXI_awready),\n        .M00_AXI_awregion(M00_AXI_awregion),\n        .M00_AXI_awsize(M00_AXI_awsize),\n        .M00_AXI_awvalid(M00_AXI_awvalid),\n        .M00_AXI_bid(M00_AXI_bid),\n        .M00_AXI_bready(M00_AXI_bready),\n        .M00_AXI_bresp(M00_AXI_bresp),\n        .M00_AXI_bvalid(M00_AXI_bvalid),\n        .M00_AXI_rdata(M00_AXI_rdata),\n        .M00_AXI_rid(M00_AXI_rid),\n        .M00_AXI_rlast(M00_AXI_rlast),\n        .M00_AXI_rready(M00_AXI_rready),\n        .M00_AXI_rresp(M00_AXI_rresp),\n        .M00_AXI_rvalid(M00_AXI_rvalid),\n        .M00_AXI_wdata(M00_AXI_wdata),\n        .M00_AXI_wlast(M00_AXI_wlast),\n        .M00_AXI_wready(M00_AXI_wready),\n        .M00_AXI_wstrb(M00_AXI_wstrb),\n        .M00_AXI_wvalid(M00_AXI_wvalid),\n        .M01_AXI_araddr(M01_AXI_araddr),\n        .M01_AXI_arburst(M01_AXI_arburst),\n        .M01_AXI_arcache(M01_AXI_arcache),\n        .M01_AXI_arid(M01_AXI_arid),\n        .M01_AXI_arlen(M01_AXI_arlen),\n        .M01_AXI_arlock(M01_AXI_arlock),\n        .M01_AXI_arprot(M01_AXI_arprot),\n        .M01_AXI_arqos(M01_AXI_arqos),\n        .M01_AXI_arready(M01_AXI_arready),\n        .M01_AXI_arregion(M01_AXI_arregion),\n        .M01_AXI_arsize(M01_AXI_arsize),\n        .M01_AXI_arvalid(M01_AXI_arvalid),\n        .M01_AXI_awaddr(M01_AXI_awaddr),\n        .M01_AXI_awburst(M01_AXI_awburst),\n        .M01_AXI_awcache(M01_AXI_awcache),\n        .M01_AXI_awid(M01_AXI_awid),\n        .M01_AXI_awlen(M01_AXI_awlen),\n        .M01_AXI_awlock(M01_AXI_awlock),\n        .M01_AXI_awprot(M01_AXI_awprot),\n        .M01_AXI_awqos(M01_AXI_awqos),\n        .M01_AXI_awready(M01_AXI_awready),\n        .M01_AXI_awregion(M01_AXI_awregion),\n        .M01_AXI_awsize(M01_AXI_awsize),\n        .M01_AXI_awvalid(M01_AXI_awvalid),\n        .M01_AXI_bid(M01_AXI_bid),\n        .M01_AXI_bready(M01_AXI_bready),\n        .M01_AXI_bresp(M01_AXI_bresp),\n        .M01_AXI_bvalid(M01_AXI_bvalid),\n        .M01_AXI_rdata(M01_AXI_rdata),\n        .M01_AXI_rid(M01_AXI_rid),\n        .M01_AXI_rlast(M01_AXI_rlast),\n        .M01_AXI_rready(M01_AXI_rready),\n        .M01_AXI_rresp(M01_AXI_rresp),\n        .M01_AXI_rvalid(M01_AXI_rvalid),\n        .M01_AXI_wdata(M01_AXI_wdata),\n        .M01_AXI_wlast(M01_AXI_wlast),\n        .M01_AXI_wready(M01_AXI_wready),\n        .M01_AXI_wstrb(M01_AXI_wstrb),\n        .M01_AXI_wvalid(M01_AXI_wvalid),\n        .M02_AXI_araddr(M02_AXI_araddr),\n        .M02_AXI_arburst(M02_AXI_arburst),\n        .M02_AXI_arcache(M02_AXI_arcache),\n        .M02_AXI_arid(M02_AXI_arid),\n        .M02_AXI_arlen(M02_AXI_arlen),\n        .M02_AXI_arlock(M02_AXI_arlock),\n        .M02_AXI_arprot(M02_AXI_arprot),\n        .M02_AXI_arqos(M02_AXI_arqos),\n        .M02_AXI_arready(M02_AXI_arready),\n        .M02_AXI_arregion(M02_AXI_arregion),\n        .M02_AXI_arsize(M02_AXI_arsize),\n        .M02_AXI_arvalid(M02_AXI_arvalid),\n        .M02_AXI_awaddr(M02_AXI_awaddr),\n        .M02_AXI_awburst(M02_AXI_awburst),\n        .M02_AXI_awcache(M02_AXI_awcache),\n        .M02_AXI_awid(M02_AXI_awid),\n        .M02_AXI_awlen(M02_AXI_awlen),\n        .M02_AXI_awlock(M02_AXI_awlock),\n        .M02_AXI_awprot(M02_AXI_awprot),\n        .M02_AXI_awqos(M02_AXI_awqos),\n        .M02_AXI_awready(M02_AXI_awready),\n        .M02_AXI_awregion(M02_AXI_awregion),\n        .M02_AXI_awsize(M02_AXI_awsize),\n        .M02_AXI_awvalid(M02_AXI_awvalid),\n        .M02_AXI_bid(M02_AXI_bid),\n        .M02_AXI_bready(M02_AXI_bready),\n        .M02_AXI_bresp(M02_AXI_bresp),\n        .M02_AXI_bvalid(M02_AXI_bvalid),\n        .M02_AXI_rdata(M02_AXI_rdata),\n        .M02_AXI_rid(M02_AXI_rid),\n        .M02_AXI_rlast(M02_AXI_rlast),\n        .M02_AXI_rready(M02_AXI_rready),\n        .M02_AXI_rresp(M02_AXI_rresp),\n        .M02_AXI_rvalid(M02_AXI_rvalid),\n        .M02_AXI_wdata(M02_AXI_wdata),\n        .M02_AXI_wlast(M02_AXI_wlast),\n        .M02_AXI_wready(M02_AXI_wready),\n        .M02_AXI_wstrb(M02_AXI_wstrb),\n        .M02_AXI_wvalid(M02_AXI_wvalid),\n        .M03_AXI_araddr(M03_AXI_araddr),\n        .M03_AXI_arburst(M03_AXI_arburst),\n        .M03_AXI_arcache(M03_AXI_arcache),\n        .M03_AXI_arid(M03_AXI_arid),\n        .M03_AXI_arlen(M03_AXI_arlen),\n        .M03_AXI_arlock(M03_AXI_arlock),\n        .M03_AXI_arprot(M03_AXI_arprot),\n        .M03_AXI_arqos(M03_AXI_arqos),\n        .M03_AXI_arready(M03_AXI_arready),\n        .M03_AXI_arregion(M03_AXI_arregion),\n        .M03_AXI_arsize(M03_AXI_arsize),\n        .M03_AXI_arvalid(M03_AXI_arvalid),\n        .M03_AXI_awaddr(M03_AXI_awaddr),\n        .M03_AXI_awburst(M03_AXI_awburst),\n        .M03_AXI_awcache(M03_AXI_awcache),\n        .M03_AXI_awid(M03_AXI_awid),\n        .M03_AXI_awlen(M03_AXI_awlen),\n        .M03_AXI_awlock(M03_AXI_awlock),\n        .M03_AXI_awprot(M03_AXI_awprot),\n        .M03_AXI_awqos(M03_AXI_awqos),\n        .M03_AXI_awready(M03_AXI_awready),\n        .M03_AXI_awregion(M03_AXI_awregion),\n        .M03_AXI_awsize(M03_AXI_awsize),\n        .M03_AXI_awvalid(M03_AXI_awvalid),\n        .M03_AXI_bid(M03_AXI_bid),\n        .M03_AXI_bready(M03_AXI_bready),\n        .M03_AXI_bresp(M03_AXI_bresp),\n        .M03_AXI_bvalid(M03_AXI_bvalid),\n        .M03_AXI_rdata(M03_AXI_rdata),\n        .M03_AXI_rid(M03_AXI_rid),\n        .M03_AXI_rlast(M03_AXI_rlast),\n        .M03_AXI_rready(M03_AXI_rready),\n        .M03_AXI_rresp(M03_AXI_rresp),\n        .M03_AXI_rvalid(M03_AXI_rvalid),\n        .M03_AXI_wdata(M03_AXI_wdata),\n        .M03_AXI_wlast(M03_AXI_wlast),\n        .M03_AXI_wready(M03_AXI_wready),\n        .M03_AXI_wstrb(M03_AXI_wstrb),\n        .M03_AXI_wvalid(M03_AXI_wvalid),\n        .S00_AXI_araddr(S00_AXI_araddr),\n        .S00_AXI_arburst(S00_AXI_arburst),\n        .S00_AXI_arcache(S00_AXI_arcache),\n        .S00_AXI_arid(S00_AXI_arid),\n        .S00_AXI_arlen(S00_AXI_arlen),\n        .S00_AXI_arlock(S00_AXI_arlock),\n        .S00_AXI_arprot(S00_AXI_arprot),\n        .S00_AXI_arqos(S00_AXI_arqos),\n        .S00_AXI_arready(S00_AXI_arready),\n        .S00_AXI_arregion(S00_AXI_arregion),\n        .S00_AXI_arsize(S00_AXI_arsize),\n        .S00_AXI_arvalid(S00_AXI_arvalid),\n        .S00_AXI_awaddr(S00_AXI_awaddr),\n        .S00_AXI_awburst(S00_AXI_awburst),\n        .S00_AXI_awcache(S00_AXI_awcache),\n        .S00_AXI_awid(S00_AXI_awid),\n        .S00_AXI_awlen(S00_AXI_awlen),\n        .S00_AXI_awlock(S00_AXI_awlock),\n        .S00_AXI_awprot(S00_AXI_awprot),\n        .S00_AXI_awqos(S00_AXI_awqos),\n        .S00_AXI_awready(S00_AXI_awready),\n        .S00_AXI_awregion(S00_AXI_awregion),\n        .S00_AXI_awsize(S00_AXI_awsize),\n        .S00_AXI_awvalid(S00_AXI_awvalid),\n        .S00_AXI_bid(S00_AXI_bid),\n        .S00_AXI_bready(S00_AXI_bready),\n        .S00_AXI_bresp(S00_AXI_bresp),\n        .S00_AXI_bvalid(S00_AXI_bvalid),\n        .S00_AXI_rdata(S00_AXI_rdata),\n        .S00_AXI_rid(S00_AXI_rid),\n        .S00_AXI_rlast(S00_AXI_rlast),\n        .S00_AXI_rready(S00_AXI_rready),\n        .S00_AXI_rresp(S00_AXI_rresp),\n        .S00_AXI_rvalid(S00_AXI_rvalid),\n        .S00_AXI_wdata(S00_AXI_wdata),\n        .S00_AXI_wlast(S00_AXI_wlast),\n        .S00_AXI_wready(S00_AXI_wready),\n        .S00_AXI_wstrb(S00_AXI_wstrb),\n        .S00_AXI_wvalid(S00_AXI_wvalid),\n        .S01_AXI_araddr(S01_AXI_araddr),\n        .S01_AXI_arburst(S01_AXI_arburst),\n        .S01_AXI_arcache(S01_AXI_arcache),\n        .S01_AXI_arid(S01_AXI_arid),\n        .S01_AXI_arlen(S01_AXI_arlen),\n        .S01_AXI_arlock(S01_AXI_arlock),\n        .S01_AXI_arprot(S01_AXI_arprot),\n        .S01_AXI_arqos(S01_AXI_arqos),\n        .S01_AXI_arready(S01_AXI_arready),\n        .S01_AXI_arregion(S01_AXI_arregion),\n        .S01_AXI_arsize(S01_AXI_arsize),\n        .S01_AXI_arvalid(S01_AXI_arvalid),\n        .S01_AXI_awaddr(S01_AXI_awaddr),\n        .S01_AXI_awburst(S01_AXI_awburst),\n        .S01_AXI_awcache(S01_AXI_awcache),\n        .S01_AXI_awid(S01_AXI_awid),\n        .S01_AXI_awlen(S01_AXI_awlen),\n        .S01_AXI_awlock(S01_AXI_awlock),\n        .S01_AXI_awprot(S01_AXI_awprot),\n        .S01_AXI_awqos(S01_AXI_awqos),\n        .S01_AXI_awready(S01_AXI_awready),\n        .S01_AXI_awregion(S01_AXI_awregion),\n        .S01_AXI_awsize(S01_AXI_awsize),\n        .S01_AXI_awvalid(S01_AXI_awvalid),\n        .S01_AXI_bid(S01_AXI_bid),\n        .S01_AXI_bready(S01_AXI_bready),\n        .S01_AXI_bresp(S01_AXI_bresp),\n        .S01_AXI_bvalid(S01_AXI_bvalid),\n        .S01_AXI_rdata(S01_AXI_rdata),\n        .S01_AXI_rid(S01_AXI_rid),\n        .S01_AXI_rlast(S01_AXI_rlast),\n        .S01_AXI_rready(S01_AXI_rready),\n        .S01_AXI_rresp(S01_AXI_rresp),\n        .S01_AXI_rvalid(S01_AXI_rvalid),\n        .S01_AXI_wdata(S01_AXI_wdata),\n        .S01_AXI_wlast(S01_AXI_wlast),\n        .S01_AXI_wready(S01_AXI_wready),\n        .S01_AXI_wstrb(S01_AXI_wstrb),\n        .S01_AXI_wvalid(S01_AXI_wvalid));\nendmodule\n", "num_lines": 961}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 250000000, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'H00),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 433}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_15_axi_register_slice,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_m00_regslice_0,axi_register_slice_v2_1_15_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_m00_regslice_0,axi_register_slice_v2_1_15_axi_register_slice,{x_ipProduct=Vivado 2017.4.op,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=7,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7\\\n,C_REG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 250000000, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'H00),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 435}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m01_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 250000000, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'H00),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 433}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_15_axi_register_slice,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_m01_regslice_0,axi_register_slice_v2_1_15_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_m01_regslice_0,axi_register_slice_v2_1_15_axi_register_slice,{x_ipProduct=Vivado 2017.4.op,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=7,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7\\\n,C_REG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m01_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 250000000, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'H00),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 435}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m02_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 250000000, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'H00),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 433}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_15_axi_register_slice,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_m02_regslice_0,axi_register_slice_v2_1_15_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_m02_regslice_0,axi_register_slice_v2_1_15_axi_register_slice,{x_ipProduct=Vivado 2017.4.op,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=7,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7\\\n,C_REG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m02_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 250000000, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'H00),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 435}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m03_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 250000000, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'H00),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 433}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_15_axi_register_slice,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_m03_regslice_0,axi_register_slice_v2_1_15_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_m03_regslice_0,axi_register_slice_v2_1_15_axi_register_slice,{x_ipProduct=Vivado 2017.4.op,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=7,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7\\\n,C_REG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m03_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 250000000, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'H00),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 435}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_s00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 250000000, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'H00),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 433}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_15_axi_register_slice,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_s00_regslice_0,axi_register_slice_v2_1_15_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_s00_regslice_0,axi_register_slice_v2_1_15_axi_register_slice,{x_ipProduct=Vivado 2017.4.op,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=6,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7\\\n,C_REG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_s00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 250000000, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'H00),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 435}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_s01_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 250000000, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'H00),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 433}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_15_axi_register_slice,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_s01_regslice_0,axi_register_slice_v2_1_15_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_s01_regslice_0,axi_register_slice_v2_1_15_axi_register_slice,{x_ipProduct=Vivado 2017.4.op,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=6,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7\\\n,C_REG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_s01_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 250000000, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'H00),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 435}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_crossbar:2.1\n// IP Revision: 16\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_xbar_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLKIF, FREQ_HZ 250000000, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLKIF CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RSTIF RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [6:0] [13:7]\" *)\ninput wire [13 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]\" *)\ninput wire [15 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]\" *)\ninput wire [3 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [511:0] [1023:512]\" *)\ninput wire [1023 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [6:0] [13:7]\" *)\noutput wire [13 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]\" *)\noutput wire [3 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [6:0] [13:7]\" *)\ninput wire [13 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]\" *)\ninput wire [15 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]\" *)\ninput wire [3 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [6:0] [13:7]\" *)\noutput wire [13 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [511:0] [1023:512]\" *)\noutput wire [1023 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]\" *)\noutput wire [3 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME S01_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI AWID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI AWID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI AWID [6:0] [27:21]\" *)\noutput wire [27 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI AWLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI AWLEN [7:0] [31:24]\" *)\noutput wire [31 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI AWBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI AWBURST [1:0] [7:6]\" *)\noutput wire [7 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWREGION [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWQOS [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [511:0] [1023:512], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [511:0] [1535:1024], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [511:0] [2047:1536]\" *)\noutput wire [2047 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WLAST [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI BID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI BID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI BID [6:0] [27:21]\" *)\ninput wire [27 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]\" *)\ninput wire [7 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI ARID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI ARID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI ARID [6:0] [27:21]\" *)\noutput wire [27 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI ARLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI ARLEN [7:0] [31:24]\" *)\noutput wire [31 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI ARBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI ARBURST [1:0] [7:6]\" *)\noutput wire [7 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARREGION [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARQOS [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI RID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI RID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI RID [6:0] [27:21]\" *)\ninput wire [27 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [511:0] [1023:512], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [511:0] [1535:1024], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [511:0] [2047:1536]\" *)\ninput wire [2047 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]\" *)\ninput wire [7 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RLAST [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_rready;\n\n  axi_crossbar_v2_1_16_axi_crossbar #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_NUM_SLAVE_SLOTS(2),\n    .C_NUM_MASTER_SLOTS(4),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_PROTOCOL(0),\n    .C_NUM_ADDR_RANGES(1),\n    .C_M_AXI_BASE_ADDR(256'H0000000c00000000000000080000000000000004000000000000000000000000),\n    .C_M_AXI_ADDR_WIDTH(128'H00000022000000220000002200000022),\n    .C_S_AXI_BASE_ID(64'H0000004000000000),\n    .C_S_AXI_THREAD_ID_WIDTH(64'H0000000600000006),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_M_AXI_WRITE_CONNECTIVITY(128'H00000003000000030000000300000003),\n    .C_M_AXI_READ_CONNECTIVITY(128'H00000003000000030000000300000003),\n    .C_R_REGISTER(0),\n    .C_S_AXI_SINGLE_THREAD(64'H0000000000000000),\n    .C_S_AXI_WRITE_ACCEPTANCE(64'H0000002000000020),\n    .C_S_AXI_READ_ACCEPTANCE(64'H0000002000000020),\n    .C_M_AXI_WRITE_ISSUING(128'H00000010000000100000001000000010),\n    .C_M_AXI_READ_ISSUING(128'H00000010000000100000001000000010),\n    .C_S_AXI_ARB_PRIORITY(64'H0000000000000000),\n    .C_M_AXI_SECURE(128'H00000000000000000000000000000000),\n    .C_CONNECTIVITY_MODE(1)\n  ) inst (\n    .aclk(aclk),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(2'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(14'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(2'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(2'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(4'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(4'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 421}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_crossbar:2.1\n// IP Revision: 16\n\n(* X_CORE_INFO = \"axi_crossbar_v2_1_16_axi_crossbar,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_xbar_0,axi_crossbar_v2_1_16_axi_crossbar,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_xbar_0,axi_crossbar_v2_1_16_axi_crossbar,{x_ipProduct=Vivado 2017.4.op,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=16,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_NUM_SLAVE_SLOTS=2,C_NUM_MASTER_SLOTS=4,C_AXI_ID_WIDTH=7,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_PROTOCOL=0,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x0000000c00000000000000080000000000000004000000000000000000000000,C_M_AXI_ADDR_WIDTH=0x00000022\\\n000000220000002200000022,C_S_AXI_BASE_ID=0x0000004000000000,C_S_AXI_THREAD_ID_WIDTH=0x0000000600000006,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000003000000030000000300000003,C_M_AXI_READ_CONNECTIVITY=0x00000003000000030000000300000003,C_R_REGISTER=0,C_S_AXI_SINGLE_THREAD=0x0000000000000000,C_S_AXI_WRITE_ACCEPTANCE=0x0000002000000020,C_S_AXI_READ_ACCEPTANCE=0x0000002000000020\\\n,C_M_AXI_WRITE_ISSUING=0x00000010000000100000001000000010,C_M_AXI_READ_ISSUING=0x00000010000000100000001000000010,C_S_AXI_ARB_PRIORITY=0x0000000000000000,C_M_AXI_SECURE=0x00000000000000000000000000000000,C_CONNECTIVITY_MODE=1}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_xbar_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLKIF, FREQ_HZ 250000000, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLKIF CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RSTIF RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [6:0] [13:7]\" *)\ninput wire [13 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]\" *)\ninput wire [15 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]\" *)\ninput wire [3 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [511:0] [1023:512]\" *)\ninput wire [1023 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [6:0] [13:7]\" *)\noutput wire [13 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]\" *)\noutput wire [3 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [6:0] [13:7]\" *)\ninput wire [13 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]\" *)\ninput wire [15 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]\" *)\ninput wire [3 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [6:0] [13:7]\" *)\noutput wire [13 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [511:0] [1023:512]\" *)\noutput wire [1023 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]\" *)\noutput wire [3 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME S01_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI AWID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI AWID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI AWID [6:0] [27:21]\" *)\noutput wire [27 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI AWLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI AWLEN [7:0] [31:24]\" *)\noutput wire [31 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI AWBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI AWBURST [1:0] [7:6]\" *)\noutput wire [7 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWREGION [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWQOS [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [511:0] [1023:512], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [511:0] [1535:1024], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [511:0] [2047:1536]\" *)\noutput wire [2047 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WLAST [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI BID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI BID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI BID [6:0] [27:21]\" *)\ninput wire [27 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]\" *)\ninput wire [7 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI ARID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI ARID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI ARID [6:0] [27:21]\" *)\noutput wire [27 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI ARLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI ARLEN [7:0] [31:24]\" *)\noutput wire [31 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI ARBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI ARBURST [1:0] [7:6]\" *)\noutput wire [7 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARREGION [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARQOS [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI RID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI RID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI RID [6:0] [27:21]\" *)\ninput wire [27 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [511:0] [1023:512], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [511:0] [1535:1024], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [511:0] [2047:1536]\" *)\ninput wire [2047 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]\" *)\ninput wire [7 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RLAST [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_rready;\n\n  axi_crossbar_v2_1_16_axi_crossbar #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_NUM_SLAVE_SLOTS(2),\n    .C_NUM_MASTER_SLOTS(4),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_PROTOCOL(0),\n    .C_NUM_ADDR_RANGES(1),\n    .C_M_AXI_BASE_ADDR(256'H0000000c00000000000000080000000000000004000000000000000000000000),\n    .C_M_AXI_ADDR_WIDTH(128'H00000022000000220000002200000022),\n    .C_S_AXI_BASE_ID(64'H0000004000000000),\n    .C_S_AXI_THREAD_ID_WIDTH(64'H0000000600000006),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_M_AXI_WRITE_CONNECTIVITY(128'H00000003000000030000000300000003),\n    .C_M_AXI_READ_CONNECTIVITY(128'H00000003000000030000000300000003),\n    .C_R_REGISTER(0),\n    .C_S_AXI_SINGLE_THREAD(64'H0000000000000000),\n    .C_S_AXI_WRITE_ACCEPTANCE(64'H0000002000000020),\n    .C_S_AXI_READ_ACCEPTANCE(64'H0000002000000020),\n    .C_M_AXI_WRITE_ISSUING(128'H00000010000000100000001000000010),\n    .C_M_AXI_READ_ISSUING(128'H00000010000000100000001000000010),\n    .C_S_AXI_ARB_PRIORITY(64'H0000000000000000),\n    .C_M_AXI_SECURE(128'H00000000000000000000000000000000),\n    .C_CONNECTIVITY_MODE(1)\n  ) inst (\n    .aclk(aclk),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(2'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(14'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(2'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(2'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(4'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(4'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 424}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_15_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      (* max_fanout = 66 *) reg s_valid_d;\n      (* max_fanout = 66 *) reg s_ready_d = 1'b0;\n      (* max_fanout = 66 *) reg s_ready_reg = 1'b0;\n      (* max_fanout = 66 *) reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_15_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS==2) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS==2) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_15_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      // System Signals\n      .ACLK(ACLK),\n      .ARESET(ARESET),\n\n      // Slave side\n      .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n      .S_VALID(S_VALID),\n      .S_READY(S_READY),\n\n      // Master side\n      .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n      .M_VALID(M_VALID),\n      .M_READY(M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK           ( ACLK ) ,\n        .ARESET         ( ARESET ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK           ( ACLK ) ,\n        .ARESET         ( ARESET ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (1) begin : common\n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    (* dont_touch=\"true\" *)  reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_handshake_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg [((C_PIPELINES>0)?(C_PIPELINES-1):0):0] ready_d = 0;\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0; \n        laguna_m_ready_d <= 1'b0; \n        ready_d <= 0;\n      end else begin\n        laguna_m_ready_d <= laguna_m_ready; \n        if (C_PIPELINES==0) begin\n          laguna_s_ready_i <= laguna_m_ready_d;\n        end else if (C_PIPELINES==1) begin\n          ready_d <= laguna_m_ready_d; \n          laguna_s_ready_i <= ready_d;\n        end else begin\n          ready_d <= {ready_d, laguna_m_ready_d}; \n          laguna_s_ready_i <= ready_d[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n        end\n      end\n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_d : payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, laguna_m_ready_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{laguna_m_ready_d}};\n            payload_valid_enable <= laguna_m_ready_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==0) begin\n                laguna_s_payload_d[i] <= laguna_s_payload[i];\n              end else if (p==C_PIPELINES+1) begin\n                laguna_m_payload_i[i] <= payload_i[C_PIPELINES*C_DATA_WIDTH + i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          if (areset_d) begin\n            laguna_s_handshake_d <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_s_handshake_d <= laguna_s_handshake;\n          end\n        end else if (p==C_PIPELINES+1) begin\n          if (areset_d) begin\n            laguna_m_handshake_i <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_m_handshake_i <= handshake_i[C_PIPELINES];\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (C_REG_CONFIG == 13) begin : tdm\n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* dont_touch=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_15_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_LATENCY = (C_PIPELINES>0) ? C_PIPELINES : 1;\n     \n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    (* dont_touch=\"true\" *)  reg laguna_m_handshake_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] ready_d = 0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_LATENCY-1];\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_ready_d <= 1'b0; \n        ready_d <= 0;\n      end else begin\n        laguna_m_ready_d <= laguna_m_ready; \n        if (C_PIPELINES>0) begin\n          ready_d <= {ready_d, laguna_m_ready_d}; \n        end\n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, laguna_m_ready_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{laguna_m_ready_d}};\n            payload_valid_enable <= laguna_m_ready_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (C_PIPELINES==0) begin\n          if (laguna_m_ready_d) begin\n            laguna_m_payload_i <= S_PAYLOAD_DATA;\n          end\n        end else begin\n          for (r=0; r<P_REPLICATION; r=r+1) begin\n            if (payload_data_enable[r]) begin\n              for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n                if (p==C_PIPELINES) begin\n                  laguna_m_payload_i[i] <= payload_i[((C_PIPELINES>0)?(C_PIPELINES-1):0)*C_DATA_WIDTH + i];\n                end else if (p==0) begin\n                  payload_data[i] <= S_PAYLOAD_DATA[i];\n                end else begin\n                  payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n                end\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (C_PIPELINES==0) begin\n          if (areset_d) begin\n            laguna_m_handshake_i <= 1'b0;\n          end else if (laguna_m_ready_d) begin\n            laguna_m_handshake_i <= S_VALID;\n          end\n        end else begin\n          if (p==C_PIPELINES) begin\n            if (areset_d) begin\n              laguna_m_handshake_i <= 1'b0;\n            end else if (payload_valid_enable) begin\n              laguna_m_handshake_i <= handshake_i[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n            end\n          end else if (p==0) begin\n            if (areset_d) begin\n              payload_valid <= 1'b0;\n            end else if (payload_valid_enable) begin\n              payload_valid <= S_VALID;\n            end\n          end else begin\n            if (areset_d) begin\n              payload_valid <= 1'b0;\n            end else if (payload_valid_enable) begin\n              payload_valid <= handshake_i[((p>0)?(p-1):0)];\n            end\n          end\n        end\n      end\n    end\n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_15_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (C_REG_CONFIG == 13) begin : tdm\n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n     \n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* dont_touch=\"true\" *)  reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg [((C_PIPELINES>0)?(C_PIPELINES-1):0):0] ready_d = 0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] push_enable_d = 0;\n    (* dont_touch=\"true\" *)  reg root_enable_d = 1'b0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    wire push_enable;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push_enable = push_enable_d[P_PIPE_LATENCY-1];\n    assign push = handshake_i[C_PIPELINES] & push_enable;      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0; \n        ready_d <= 0;\n        push_enable_d <= 0;\n        root_enable_d <= 1'b0; \n      end else begin\n        push_enable_d <= {push_enable_d, root_enable_d};\n        root_enable_d <= M_READY | ~m_valid_i;\n        if (C_PIPELINES==0) begin\n          laguna_s_ready_i <= root_enable_d;\n        end else if (C_PIPELINES==1) begin\n          ready_d <= root_enable_d; \n          laguna_s_ready_i <= ready_d;\n        end else begin\n          ready_d <= {ready_d, root_enable_d}; \n          laguna_s_ready_i <= ready_d[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n        end\n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_d : payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, root_enable_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{root_enable_d}};\n            payload_valid_enable <= root_enable_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==0) begin\n                laguna_s_payload_d[i] <= laguna_s_payload[i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          if (areset_d) begin\n            laguna_s_handshake_d <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_s_handshake_d <= laguna_s_handshake;\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n    if ((C_PIPELINES==0) && (C_SOURCE_LATENCY<=1)) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        ); \n  \n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_15_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_LATENCY = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (1) begin : common\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] ready_d = 0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] push_enable_d = 0;\n    (* dont_touch=\"true\" *)  reg root_enable_d = 1'b0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire s_ready_i;\n    wire push;\n    wire pop;\n    wire push_enable;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push_enable = (C_PIPELINES == 0) ? root_enable_d : push_enable_d[P_PIPE_LATENCY-1];\n    assign push = handshake_i[C_PIPELINES] & push_enable;      \n    assign M_VALID = m_valid_i;\n    assign s_ready_i = (C_PIPELINES == 0) ? root_enable_d : ready_d[P_PIPE_LATENCY-1];\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        ready_d <= 0;\n        push_enable_d <= 0;\n        root_enable_d <= 1'b0;\n      end else begin\n        root_enable_d <= M_READY | ~m_valid_i;\n        if (C_PIPELINES > 0) begin\n          ready_d <= {ready_d, root_enable_d}; \n          push_enable_d <= {push_enable_d, root_enable_d};\n        end\n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, root_enable_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{root_enable_d}};\n            payload_valid_enable <= root_enable_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==1) begin\n                payload_data[i] <= S_PAYLOAD_DATA[i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= S_VALID;\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n    if (C_PIPELINES<=1) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    (* fsm_encoding = \"none\" *) reg [1:0] state = K_EMPTY;  // State vector register\n    reg [1:0] next;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    \n    assign m_valid = state[0];  // Drive m_valid from state vector\n    assign m_mesg  = mesg_reg;\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid) begin\n            next = K_HAS1;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin\n      if (areset) begin\n        state <= K_EMPTY;\n      end else begin\n        state <= next;\n      end\n    end\n            \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      axi_register_slice_v2_1_15_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n\n  axi_infrastructure_v1_1_0_axi2vector #( \n    .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n    .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n    .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n    .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n    .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n    .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n    .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n    .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n    .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n    .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n    .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n    .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n    .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n    .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n    .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n    .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n  )\n  axi2vector_0 ( \n    .s_axi_awid      ( s_axi_awid      ) ,\n    .s_axi_awaddr    ( s_axi_awaddr    ) ,\n    .s_axi_awlen     ( s_axi_awlen     ) ,\n    .s_axi_awsize    ( s_axi_awsize    ) ,\n    .s_axi_awburst   ( s_axi_awburst   ) ,\n    .s_axi_awlock    ( s_axi_awlock    ) ,\n    .s_axi_awcache   ( s_axi_awcache   ) ,\n    .s_axi_awprot    ( s_axi_awprot    ) ,\n    .s_axi_awqos     ( s_axi_awqos     ) ,\n    .s_axi_awuser    ( s_axi_awuser    ) ,\n    .s_axi_awregion  ( s_axi_awregion  ) ,\n    .s_axi_wid       ( s_axi_wid       ) ,\n    .s_axi_wdata     ( s_axi_wdata     ) ,\n    .s_axi_wstrb     ( s_axi_wstrb     ) ,\n    .s_axi_wlast     ( s_axi_wlast     ) ,\n    .s_axi_wuser     ( s_axi_wuser     ) ,\n    .s_axi_bid       ( s_axi_bid       ) ,\n    .s_axi_bresp     ( s_axi_bresp     ) ,\n    .s_axi_buser     ( s_axi_buser     ) ,\n    .s_axi_arid      ( s_axi_arid      ) ,\n    .s_axi_araddr    ( s_axi_araddr    ) ,\n    .s_axi_arlen     ( s_axi_arlen     ) ,\n    .s_axi_arsize    ( s_axi_arsize    ) ,\n    .s_axi_arburst   ( s_axi_arburst   ) ,\n    .s_axi_arlock    ( s_axi_arlock    ) ,\n    .s_axi_arcache   ( s_axi_arcache   ) ,\n    .s_axi_arprot    ( s_axi_arprot    ) ,\n    .s_axi_arqos     ( s_axi_arqos     ) ,\n    .s_axi_aruser    ( s_axi_aruser    ) ,\n    .s_axi_arregion  ( s_axi_arregion  ) ,\n    .s_axi_rid       ( s_axi_rid       ) ,\n    .s_axi_rdata     ( s_axi_rdata     ) ,\n    .s_axi_rresp     ( s_axi_rresp     ) ,\n    .s_axi_rlast     ( s_axi_rlast     ) ,\n    .s_axi_ruser     ( s_axi_ruser     ) ,\n    .s_awpayload ( s_awpayload ) ,\n    .s_wpayload  ( s_wpayload  ) ,\n    .s_bpayload  ( s_bpayload  ) ,\n    .s_arpayload ( s_arpayload ) ,\n    .s_rpayload  ( s_rpayload  ) \n  );\n    \n  if (C_REG_CONFIG_AW <= 9) begin : aw\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_REG_CONFIG_AW == 15) begin : aw15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if (C_REG_CONFIG_W <= 9) begin : w\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_REG_CONFIG_W == 15) begin : w15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if (C_REG_CONFIG_B <= 9) begin : b\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if (C_REG_CONFIG_B == 15) begin : b15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if (C_REG_CONFIG_AR <= 9) begin : ar\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_REG_CONFIG_AR == 15) begin : ar15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if (C_REG_CONFIG_R <= 9) begin : r\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_REG_CONFIG_R == 15) begin : r15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\n  axi_infrastructure_v1_1_0_vector2axi #( \n    .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n    .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n    .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n    .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n    .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n    .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n    .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n    .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n    .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n    .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n    .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n    .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n    .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n    .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n    .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n    .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n  )\n  vector2axi_0 ( \n    .m_awpayload    ( m_awpayload    ) ,\n    .m_wpayload     ( m_wpayload     ) ,\n    .m_bpayload     ( m_bpayload     ) ,\n    .m_arpayload    ( m_arpayload    ) ,\n    .m_rpayload     ( m_rpayload     ) ,\n    .m_axi_awid     ( m_axi_awid     ) ,\n    .m_axi_awaddr   ( m_axi_awaddr   ) ,\n    .m_axi_awlen    ( m_axi_awlen    ) ,\n    .m_axi_awsize   ( m_axi_awsize   ) ,\n    .m_axi_awburst  ( m_axi_awburst  ) ,\n    .m_axi_awlock   ( m_axi_awlock   ) ,\n    .m_axi_awcache  ( m_axi_awcache  ) ,\n    .m_axi_awprot   ( m_axi_awprot   ) ,\n    .m_axi_awqos    ( m_axi_awqos    ) ,\n    .m_axi_awuser   ( m_axi_awuser   ) ,\n    .m_axi_awregion ( m_axi_awregion ) ,\n    .m_axi_wid      ( m_axi_wid      ) ,\n    .m_axi_wdata    ( m_axi_wdata    ) ,\n    .m_axi_wstrb    ( m_axi_wstrb    ) ,\n    .m_axi_wlast    ( m_axi_wlast    ) ,\n    .m_axi_wuser    ( m_axi_wuser    ) ,\n    .m_axi_bid      ( m_axi_bid      ) ,\n    .m_axi_bresp    ( m_axi_bresp    ) ,\n    .m_axi_buser    ( m_axi_buser    ) ,\n    .m_axi_arid     ( m_axi_arid     ) ,\n    .m_axi_araddr   ( m_axi_araddr   ) ,\n    .m_axi_arlen    ( m_axi_arlen    ) ,\n    .m_axi_arsize   ( m_axi_arsize   ) ,\n    .m_axi_arburst  ( m_axi_arburst  ) ,\n    .m_axi_arlock   ( m_axi_arlock   ) ,\n    .m_axi_arcache  ( m_axi_arcache  ) ,\n    .m_axi_arprot   ( m_axi_arprot   ) ,\n    .m_axi_arqos    ( m_axi_arqos    ) ,\n    .m_axi_aruser   ( m_axi_aruser   ) ,\n    .m_axi_arregion ( m_axi_arregion ) ,\n    .m_axi_rid      ( m_axi_rid      ) ,\n    .m_axi_rdata    ( m_axi_rdata    ) ,\n    .m_axi_rresp    ( m_axi_rresp    ) ,\n    .m_axi_rlast    ( m_axi_rlast    ) ,\n    .m_axi_ruser    ( m_axi_ruser    ) \n  );\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 3108}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "/*\n *******************************************************************************\n *\n * FIFO Generator - Verilog Behavioral Model\n *\n *******************************************************************************\n *\n * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.\n *\n * This file contains confidential and proprietary information\n * of Xilinx, Inc. and is protected under U.S. and\n * international copyright and other intellectual property\n * laws.\n *\n * DISCLAIMER\n * This disclaimer is not a license and does not grant any\n * rights to the materials distributed herewith. Except as\n * otherwise provided in a valid license issued to you by\n * Xilinx, and to the maximum extent permitted by applicable\n * law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n * (2) Xilinx shall not be liable (whether in contract or tort,\n * including negligence, or under any other theory of\n * liability) for any loss or damage of any kind or nature\n * related to, arising under or in connection with these\n * materials, including for any direct, or any indirect,\n * special, incidental, or consequential loss or damage\n * (including loss of data, profits, goodwill, or any type of\n * loss or damage suffered as a result of any action brought\n * by a third party) even if such damage or loss was\n * reasonably foreseeable or Xilinx had been advised of the\n * possibility of the same.\n *\n * CRITICAL APPLICATIONS\n * Xilinx products are not designed or intended to be fail-\n * safe, or for use in any application requiring fail-safe\n * performance, such as life-support or safety devices or\n * systems, Class III medical devices, nuclear facilities,\n * applications related to the deployment of airbags, or any\n * other applications that could lead to death, personal\n * injury, or severe property or environmental damage\n * (individually and collectively, \"Critical\n * Applications\"). Customer assumes the sole risk and\n * liability of any use of Xilinx products in Critical\n * Applications, subject only to applicable laws and\n * regulations governing limitations on product liability.\n *\n * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n * PART OF THIS FILE AT ALL TIMES.\n *\n *******************************************************************************\n *******************************************************************************\n *\n * Filename: fifo_generator_vlog_beh.v\n *\n * Author     : Xilinx\n *\n *******************************************************************************\n * Structure:\n * \n * fifo_generator_vlog_beh.v\n *    |\n *    +-fifo_generator_v13_2_1_bhv_ver_as\n *    |\n *    +-fifo_generator_v13_2_1_bhv_ver_ss\n *    |\n *    +-fifo_generator_v13_2_1_bhv_ver_preload0\n * \n *******************************************************************************\n * Description:\n *\n * The Verilog behavioral model for the FIFO Generator.\n *\n *   The behavioral model has three parts:\n *      - The behavioral model for independent clocks FIFOs (_as)\n *      - The behavioral model for common clock FIFOs (_ss)\n *      - The \"preload logic\" block which implements First-word Fall-through\n * \n *******************************************************************************\n * Description:\n *  The verilog behavioral model for the FIFO generator core.\n *\n *******************************************************************************\n */\n\n`timescale 1ps/1ps\n`ifndef TCQ\n `define TCQ 100\n`endif\n\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_vlog_beh\n  #(\n    //-----------------------------------------------------------------------\n    // Generic Declarations\n    //-----------------------------------------------------------------------\n    parameter C_COMMON_CLOCK                 = 0,\n    parameter C_COUNT_TYPE                   = 0,\n    parameter C_DATA_COUNT_WIDTH             = 2,\n    parameter C_DEFAULT_VALUE                = \"\",\n    parameter C_DIN_WIDTH                    = 8,\n    parameter C_DOUT_RST_VAL                 = \"\",\n    parameter C_DOUT_WIDTH                   = 8,\n    parameter C_ENABLE_RLOCS                 = 0,\n    parameter C_FAMILY                       = \"\",\n    parameter C_FULL_FLAGS_RST_VAL           = 1,\n    parameter C_HAS_ALMOST_EMPTY             = 0,\n    parameter C_HAS_ALMOST_FULL              = 0,\n    parameter C_HAS_BACKUP                   = 0,\n    parameter C_HAS_DATA_COUNT               = 0,\n    parameter C_HAS_INT_CLK                  = 0,\n    parameter C_HAS_MEMINIT_FILE             = 0,\n    parameter C_HAS_OVERFLOW                 = 0,\n    parameter C_HAS_RD_DATA_COUNT            = 0,\n    parameter C_HAS_RD_RST                   = 0,\n    parameter C_HAS_RST                      = 1,\n    parameter C_HAS_SRST                     = 0,\n    parameter C_HAS_UNDERFLOW                = 0,\n    parameter C_HAS_VALID                    = 0,\n    parameter C_HAS_WR_ACK                   = 0,\n    parameter C_HAS_WR_DATA_COUNT            = 0,\n    parameter C_HAS_WR_RST                   = 0,\n    parameter C_IMPLEMENTATION_TYPE          = 0,\n    parameter C_INIT_WR_PNTR_VAL             = 0,\n    parameter C_MEMORY_TYPE                  = 1,\n    parameter C_MIF_FILE_NAME                = \"\",\n    parameter C_OPTIMIZATION_MODE            = 0,\n    parameter C_OVERFLOW_LOW                 = 0,\n    parameter C_EN_SAFETY_CKT                = 0,\n    parameter C_PRELOAD_LATENCY              = 1,\n    parameter C_PRELOAD_REGS                 = 0,\n    parameter C_PRIM_FIFO_TYPE               = \"4kx4\",\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter C_PROG_EMPTY_TYPE              = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter C_PROG_FULL_TYPE               = 0,\n    parameter C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter C_RD_DEPTH                     = 256,\n    parameter C_RD_FREQ                      = 1,\n    parameter C_RD_PNTR_WIDTH                = 8,\n    parameter C_UNDERFLOW_LOW                = 0,\n    parameter C_USE_DOUT_RST                 = 0,\n    parameter C_USE_ECC                      = 0,\n    parameter C_USE_EMBEDDED_REG             = 0,\n    parameter C_USE_PIPELINE_REG             = 0,\n    parameter C_POWER_SAVING_MODE            = 0,\n    parameter C_USE_FIFO16_FLAGS             = 0,\n    parameter C_USE_FWFT_DATA_COUNT          = 0,\n    parameter C_VALID_LOW                    = 0,\n    parameter C_WR_ACK_LOW                   = 0,\n    parameter C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter C_WR_DEPTH                     = 256,\n    parameter C_WR_FREQ                      = 1,\n    parameter C_WR_PNTR_WIDTH                = 8,\n    parameter C_WR_RESPONSE_LATENCY          = 1,\n    parameter C_MSGON_VAL                    = 1,\n    parameter C_ENABLE_RST_SYNC              = 1,\n    parameter C_ERROR_INJECTION_TYPE         = 0,\n    parameter C_SYNCHRONIZER_STAGE           = 2,\n\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE               = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3\n    parameter C_AXI_TYPE                     = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3\n    parameter C_HAS_AXI_WR_CHANNEL           = 0,\n    parameter C_HAS_AXI_RD_CHANNEL           = 0,\n    parameter C_HAS_SLAVE_CE                 = 0,\n    parameter C_HAS_MASTER_CE                = 0,\n    parameter C_ADD_NGC_CONSTRAINT           = 0,\n    parameter C_USE_COMMON_UNDERFLOW         = 0,\n    parameter C_USE_COMMON_OVERFLOW          = 0,\n    parameter C_USE_DEFAULT_SETTINGS         = 0,\n\n    // AXI Full/Lite\n    parameter C_AXI_ID_WIDTH                 = 0,\n    parameter C_AXI_ADDR_WIDTH               = 0,\n    parameter C_AXI_DATA_WIDTH               = 0,\n    parameter C_AXI_LEN_WIDTH                = 8,\n    parameter C_AXI_LOCK_WIDTH               = 2,\n    parameter C_HAS_AXI_ID                   = 0,\n    parameter C_HAS_AXI_AWUSER               = 0,\n    parameter C_HAS_AXI_WUSER                = 0,\n    parameter C_HAS_AXI_BUSER                = 0,\n    parameter C_HAS_AXI_ARUSER               = 0,\n    parameter C_HAS_AXI_RUSER                = 0,\n    parameter C_AXI_ARUSER_WIDTH             = 0,\n    parameter C_AXI_AWUSER_WIDTH             = 0,\n    parameter C_AXI_WUSER_WIDTH              = 0,\n    parameter C_AXI_BUSER_WIDTH              = 0,\n    parameter C_AXI_RUSER_WIDTH              = 0,\n\n    // AXI Streaming\n    parameter C_HAS_AXIS_TDATA               = 0,\n    parameter C_HAS_AXIS_TID                 = 0,\n    parameter C_HAS_AXIS_TDEST               = 0,\n    parameter C_HAS_AXIS_TUSER               = 0,\n    parameter C_HAS_AXIS_TREADY              = 0,\n    parameter C_HAS_AXIS_TLAST               = 0,\n    parameter C_HAS_AXIS_TSTRB               = 0,\n    parameter C_HAS_AXIS_TKEEP               = 0,\n    parameter C_AXIS_TDATA_WIDTH             = 1,\n    parameter C_AXIS_TID_WIDTH               = 1,\n    parameter C_AXIS_TDEST_WIDTH             = 1,\n    parameter C_AXIS_TUSER_WIDTH             = 1,\n    parameter C_AXIS_TSTRB_WIDTH             = 1,\n    parameter C_AXIS_TKEEP_WIDTH             = 1,\n\n    // AXI Channel Type\n    // WACH --> Write Address Channel\n    // WDCH --> Write Data Channel\n    // WRCH --> Write Response Channel\n    // RACH --> Read Address Channel\n    // RDCH --> Read Data Channel\n    // AXIS --> AXI Streaming\n    parameter C_WACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic\n    parameter C_WDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_WRCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_AXIS_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n\n    // AXI Implementation Type\n    // 1 = Common Clock Block RAM FIFO\n    // 2 = Common Clock Distributed RAM FIFO\n    // 11 = Independent Clock Block RAM FIFO\n    // 12 = Independent Clock Distributed RAM FIFO\n    parameter C_IMPLEMENTATION_TYPE_WACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WRCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_AXIS     = 0,\n\n    // AXI FIFO Type\n    // 0 = Data FIFO\n    // 1 = Packet FIFO\n    // 2 = Low Latency Sync FIFO\n    // 3 = Low Latency Async FIFO\n    parameter C_APPLICATION_TYPE_WACH        = 0,\n    parameter C_APPLICATION_TYPE_WDCH        = 0,\n    parameter C_APPLICATION_TYPE_WRCH        = 0,\n    parameter C_APPLICATION_TYPE_RACH        = 0,\n    parameter C_APPLICATION_TYPE_RDCH        = 0,\n    parameter C_APPLICATION_TYPE_AXIS        = 0,\n\n    // AXI Built-in FIFO Primitive Type\n    // 512x36, 1kx18, 2kx9, 4kx4, etc\n    parameter C_PRIM_FIFO_TYPE_WACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WRCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_AXIS          = \"512x36\",\n\n    // Enable ECC\n    // 0 = ECC disabled\n    // 1 = ECC enabled\n    parameter C_USE_ECC_WACH                 = 0,\n    parameter C_USE_ECC_WDCH                 = 0,\n    parameter C_USE_ECC_WRCH                 = 0,\n    parameter C_USE_ECC_RACH                 = 0,\n    parameter C_USE_ECC_RDCH                 = 0,\n    parameter C_USE_ECC_AXIS                 = 0,\n\n    // ECC Error Injection Type\n    // 0 = No Error Injection\n    // 1 = Single Bit Error Injection\n    // 2 = Double Bit Error Injection\n    // 3 = Single Bit and Double Bit Error Injection\n    parameter C_ERROR_INJECTION_TYPE_WACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WRCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_AXIS    = 0,\n\n    // Input Data Width\n    // Accumulation of all AXI input signal's width\n    parameter C_DIN_WIDTH_WACH               = 1,\n    parameter C_DIN_WIDTH_WDCH               = 1,\n    parameter C_DIN_WIDTH_WRCH               = 1,\n    parameter C_DIN_WIDTH_RACH               = 1,\n    parameter C_DIN_WIDTH_RDCH               = 1,\n    parameter C_DIN_WIDTH_AXIS               = 1,\n\n    parameter C_WR_DEPTH_WACH                = 16,\n    parameter C_WR_DEPTH_WDCH                = 16,\n    parameter C_WR_DEPTH_WRCH                = 16,\n    parameter C_WR_DEPTH_RACH                = 16,\n    parameter C_WR_DEPTH_RDCH                = 16,\n    parameter C_WR_DEPTH_AXIS                = 16,\n\n    parameter C_WR_PNTR_WIDTH_WACH           = 4,\n    parameter C_WR_PNTR_WIDTH_WDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_WRCH           = 4,\n    parameter C_WR_PNTR_WIDTH_RACH           = 4,\n    parameter C_WR_PNTR_WIDTH_RDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_AXIS           = 4,\n\n    parameter C_HAS_DATA_COUNTS_WACH         = 0,\n    parameter C_HAS_DATA_COUNTS_WDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_WRCH         = 0,\n    parameter C_HAS_DATA_COUNTS_RACH         = 0,\n    parameter C_HAS_DATA_COUNTS_RDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_AXIS         = 0,\n\n    parameter C_HAS_PROG_FLAGS_WACH          = 0,\n    parameter C_HAS_PROG_FLAGS_WDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_WRCH          = 0,\n    parameter C_HAS_PROG_FLAGS_RACH          = 0,\n    parameter C_HAS_PROG_FLAGS_RDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_AXIS          = 0,\n\n    parameter C_PROG_FULL_TYPE_WACH          = 0,\n    parameter C_PROG_FULL_TYPE_WDCH          = 0,\n    parameter C_PROG_FULL_TYPE_WRCH          = 0,\n    parameter C_PROG_FULL_TYPE_RACH          = 0,\n    parameter C_PROG_FULL_TYPE_RDCH          = 0,\n    parameter C_PROG_FULL_TYPE_AXIS          = 0,\n\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS      = 0,\n\n    parameter C_PROG_EMPTY_TYPE_WACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WRCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_AXIS         = 0,\n\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS     = 0,\n\n    parameter C_REG_SLICE_MODE_WACH          = 0,\n    parameter C_REG_SLICE_MODE_WDCH          = 0,\n    parameter C_REG_SLICE_MODE_WRCH          = 0,\n    parameter C_REG_SLICE_MODE_RACH          = 0,\n    parameter C_REG_SLICE_MODE_RDCH          = 0,\n    parameter C_REG_SLICE_MODE_AXIS          = 0\n\n    )\n\n   (\n    //------------------------------------------------------------------------------\n    // Input and Output Declarations\n    //------------------------------------------------------------------------------\n\n    // Conventional FIFO Interface Signals\n    input                               backup,\n    input                               backup_marker,\n    input                               clk,\n    input                               rst,\n    input                               srst,\n    input                               wr_clk,\n    input                               wr_rst,\n    input                               rd_clk,\n    input                               rd_rst,\n    input [C_DIN_WIDTH-1:0]             din,\n    input                               wr_en,\n    input                               rd_en,\n    // Optional inputs\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_assert,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_negate,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_assert,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_negate,\n    input                               int_clk,\n    input                               injectdbiterr,\n    input                               injectsbiterr,\n    input                               sleep,\n\n    output [C_DOUT_WIDTH-1:0]           dout,\n    output                              full,\n    output                              almost_full,\n    output                              wr_ack,\n    output                              overflow,\n    output                              empty,\n    output                              almost_empty,\n    output                              valid,\n    output                              underflow,\n    output [C_DATA_COUNT_WIDTH-1:0]     data_count,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]  rd_data_count,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count,\n    output                              prog_full,\n    output                              prog_empty,\n    output                              sbiterr,\n    output                              dbiterr,\n    output                              wr_rst_busy,\n    output                              rd_rst_busy,\n\n\n    // AXI Global Signal\n    input                               m_aclk,\n    input                               s_aclk,\n    input                               s_aresetn,\n    input                               s_aclk_en,\n    input                               m_aclk_en,\n    \n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_awid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_awaddr,\n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_awlen,\n    input [3-1:0]                       s_axi_awsize,\n    input [2-1:0]                       s_axi_awburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_awlock,\n    input [4-1:0]                       s_axi_awcache,\n    input [3-1:0]                       s_axi_awprot,\n    input [4-1:0]                       s_axi_awqos,\n    input [4-1:0]                       s_axi_awregion,\n    input [C_AXI_AWUSER_WIDTH-1:0]      s_axi_awuser,\n    input                               s_axi_awvalid,\n    output                              s_axi_awready,\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_wid,\n    input [C_AXI_DATA_WIDTH-1:0]        s_axi_wdata,\n    input [C_AXI_DATA_WIDTH/8-1:0]      s_axi_wstrb,\n    input                               s_axi_wlast,\n    input [C_AXI_WUSER_WIDTH-1:0]       s_axi_wuser,\n    input                               s_axi_wvalid,\n    output                              s_axi_wready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_bid,\n    output [2-1:0]                      s_axi_bresp,\n    output [C_AXI_BUSER_WIDTH-1:0]      s_axi_buser,\n    output                              s_axi_bvalid,\n    input                               s_axi_bready,\n    \n    // AXI Full/Lite Master Write Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_awid,\n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_awlen,\n    output [3-1:0]                      m_axi_awsize,\n    output [2-1:0]                      m_axi_awburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_awlock,\n    output [4-1:0]                      m_axi_awcache,\n    output [3-1:0]                      m_axi_awprot,\n    output [4-1:0]                      m_axi_awqos,\n    output [4-1:0]                      m_axi_awregion,\n    output [C_AXI_AWUSER_WIDTH-1:0]     m_axi_awuser,\n    output                              m_axi_awvalid,\n    input                               m_axi_awready,\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_wid,\n    output [C_AXI_DATA_WIDTH-1:0]       m_axi_wdata,\n    output [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb,\n    output                              m_axi_wlast,\n    output [C_AXI_WUSER_WIDTH-1:0]      m_axi_wuser,\n    output                              m_axi_wvalid,\n    input                               m_axi_wready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_bid,\n    input [2-1:0]                       m_axi_bresp,\n    input [C_AXI_BUSER_WIDTH-1:0]       m_axi_buser,\n    input                               m_axi_bvalid,\n    output                              m_axi_bready,\n    \n    \n    // AXI Full/Lite Slave Read Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_arid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_araddr, \n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_arlen,\n    input [3-1:0]                       s_axi_arsize,\n    input [2-1:0]                       s_axi_arburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_arlock,\n    input [4-1:0]                       s_axi_arcache,\n    input [3-1:0]                       s_axi_arprot,\n    input [4-1:0]                       s_axi_arqos,\n    input [4-1:0]                       s_axi_arregion,\n    input [C_AXI_ARUSER_WIDTH-1:0]      s_axi_aruser,\n    input                               s_axi_arvalid,\n    output                              s_axi_arready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_rid,       \n    output [C_AXI_DATA_WIDTH-1:0]       s_axi_rdata, \n    output [2-1:0]                      s_axi_rresp,\n    output                              s_axi_rlast,\n    output [C_AXI_RUSER_WIDTH-1:0]      s_axi_ruser,\n    output                              s_axi_rvalid,\n    input                               s_axi_rready,\n    \n    \n    \n    // AXI Full/Lite Master Read Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_arid,        \n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,  \n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_arlen,\n    output [3-1:0]                      m_axi_arsize,\n    output [2-1:0]                      m_axi_arburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_arlock,\n    output [4-1:0]                      m_axi_arcache,\n    output [3-1:0]                      m_axi_arprot,\n    output [4-1:0]                      m_axi_arqos,\n    output [4-1:0]                      m_axi_arregion,\n    output [C_AXI_ARUSER_WIDTH-1:0]     m_axi_aruser,\n    output                              m_axi_arvalid,\n    input                               m_axi_arready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_rid,        \n    input [C_AXI_DATA_WIDTH-1:0]        m_axi_rdata,  \n    input [2-1:0]                       m_axi_rresp,\n    input                               m_axi_rlast,\n    input [C_AXI_RUSER_WIDTH-1:0]       m_axi_ruser,\n    input                               m_axi_rvalid,\n    output                              m_axi_rready,\n    \n    \n    // AXI Streaming Slave Signals (Write side)\n    input                               s_axis_tvalid,\n    output                              s_axis_tready,\n    input [C_AXIS_TDATA_WIDTH-1:0]      s_axis_tdata,\n    input [C_AXIS_TSTRB_WIDTH-1:0]      s_axis_tstrb,\n    input [C_AXIS_TKEEP_WIDTH-1:0]      s_axis_tkeep,\n    input                               s_axis_tlast,\n    input [C_AXIS_TID_WIDTH-1:0]        s_axis_tid,\n    input [C_AXIS_TDEST_WIDTH-1:0]      s_axis_tdest,\n    input [C_AXIS_TUSER_WIDTH-1:0]      s_axis_tuser,\n    \n    // AXI Streaming Master Signals (Read side)\n    output                              m_axis_tvalid,\n    input                               m_axis_tready,\n    output [C_AXIS_TDATA_WIDTH-1:0]     m_axis_tdata,\n    output [C_AXIS_TSTRB_WIDTH-1:0]     m_axis_tstrb,\n    output [C_AXIS_TKEEP_WIDTH-1:0]     m_axis_tkeep,\n    output                              m_axis_tlast,\n    output [C_AXIS_TID_WIDTH-1:0]       m_axis_tid,\n    output [C_AXIS_TDEST_WIDTH-1:0]     m_axis_tdest,\n    output [C_AXIS_TUSER_WIDTH-1:0]     m_axis_tuser,\n    \n           \n    \n    \n    // AXI Full/Lite Write Address Channel signals\n    input                               axi_aw_injectsbiterr,\n    input                               axi_aw_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_rd_data_count,\n    output                              axi_aw_sbiterr,\n    output                              axi_aw_dbiterr,\n    output                              axi_aw_overflow,\n    output                              axi_aw_underflow,\n    output                              axi_aw_prog_full,\n    output                              axi_aw_prog_empty,\n    \n    \n    // AXI Full/Lite Write Data Channel signals\n    input                               axi_w_injectsbiterr,\n    input                               axi_w_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_rd_data_count,\n    output                              axi_w_sbiterr,\n    output                              axi_w_dbiterr,\n    output                              axi_w_overflow,\n    output                              axi_w_underflow,\n    output                              axi_w_prog_full,\n    output                              axi_w_prog_empty,\n    \n    \n    // AXI Full/Lite Write Response Channel signals\n    input                               axi_b_injectsbiterr,\n    input                               axi_b_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_rd_data_count,\n    output                              axi_b_sbiterr,\n    output                              axi_b_dbiterr,\n    output                              axi_b_overflow,\n    output                              axi_b_underflow,\n    output                              axi_b_prog_full,\n    output                              axi_b_prog_empty,\n    \n    \n    \n    // AXI Full/Lite Read Address Channel signals\n    input                               axi_ar_injectsbiterr,\n    input                               axi_ar_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_rd_data_count,\n    output                              axi_ar_sbiterr,\n    output                              axi_ar_dbiterr,\n    output                              axi_ar_overflow,\n    output                              axi_ar_underflow,\n    output                              axi_ar_prog_full,\n    output                              axi_ar_prog_empty,\n\n    \n    // AXI Full/Lite Read Data Channel Signals\n    input                               axi_r_injectsbiterr,\n    input                               axi_r_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_rd_data_count,\n    output                              axi_r_sbiterr,\n    output                              axi_r_dbiterr,\n    output                              axi_r_overflow,\n    output                              axi_r_underflow,\n    output                              axi_r_prog_full,\n    output                              axi_r_prog_empty,\n\n    \n    // AXI Streaming FIFO Related Signals\n    input                               axis_injectsbiterr,\n    input                               axis_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_wr_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_rd_data_count,\n    output                              axis_sbiterr,\n    output                              axis_dbiterr,\n    output                              axis_overflow,\n    output                              axis_underflow,\n    output                              axis_prog_full,\n    output                              axis_prog_empty\n\n    );\n\n    wire                              BACKUP;\n    wire                              BACKUP_MARKER;\n    wire                              CLK;\n    wire                              RST;\n    wire                              SRST;\n    wire                              WR_CLK;\n    wire                              WR_RST;\n    wire                              RD_CLK;\n    wire                              RD_RST;\n    wire [C_DIN_WIDTH-1:0]            DIN;\n    wire                              WR_EN;\n    wire                              RD_EN;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_ASSERT;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_NEGATE;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_ASSERT;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_NEGATE;\n    wire                              INT_CLK;\n    wire                              INJECTDBITERR;\n    wire                              INJECTSBITERR;\n    wire                              SLEEP;\n    wire [C_DOUT_WIDTH-1:0]           DOUT;\n    wire                              FULL;\n    wire                              ALMOST_FULL;\n    wire                              WR_ACK;\n    wire                              OVERFLOW;\n    wire                              EMPTY;\n    wire                              ALMOST_EMPTY;\n    wire                              VALID;\n    wire                              UNDERFLOW;\n    wire [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT;\n    wire [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT;\n    wire                              PROG_FULL;\n    wire                              PROG_EMPTY;\n    wire                              SBITERR;\n    wire                              DBITERR;\n    wire                              WR_RST_BUSY;\n    wire                              RD_RST_BUSY;\n    wire                              M_ACLK;\n    wire                              S_ACLK;\n    wire                              S_ARESETN;\n    wire                              S_ACLK_EN;\n    wire                              M_ACLK_EN;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_AWLEN;\n    wire [3-1:0]                      S_AXI_AWSIZE;\n    wire [2-1:0]                      S_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_AWLOCK;\n    wire [4-1:0]                      S_AXI_AWCACHE;\n    wire [3-1:0]                      S_AXI_AWPROT;\n    wire [4-1:0]                      S_AXI_AWQOS;\n    wire [4-1:0]                      S_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     S_AXI_AWUSER;\n    wire                              S_AXI_AWVALID;\n    wire                              S_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     S_AXI_WSTRB;\n    wire                              S_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      S_AXI_WUSER;\n    wire                              S_AXI_WVALID;\n    wire                              S_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_BID;\n    wire [2-1:0]                      S_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      S_AXI_BUSER;\n    wire                              S_AXI_BVALID;\n    wire                              S_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_AWLEN;\n    wire [3-1:0]                      M_AXI_AWSIZE;\n    wire [2-1:0]                      M_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_AWLOCK;\n    wire [4-1:0]                      M_AXI_AWCACHE;\n    wire [3-1:0]                      M_AXI_AWPROT;\n    wire [4-1:0]                      M_AXI_AWQOS;\n    wire [4-1:0]                      M_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     M_AXI_AWUSER;\n    wire                              M_AXI_AWVALID;\n    wire                              M_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     M_AXI_WSTRB;\n    wire                              M_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      M_AXI_WUSER;\n    wire                              M_AXI_WVALID;\n    wire                              M_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_BID;\n    wire [2-1:0]                      M_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      M_AXI_BUSER;\n    wire                              M_AXI_BVALID;\n    wire                              M_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_ARID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_ARADDR; \n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_ARLEN;\n    wire [3-1:0]                      S_AXI_ARSIZE;\n    wire [2-1:0]                      S_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_ARLOCK;\n    wire [4-1:0]                      S_AXI_ARCACHE;\n    wire [3-1:0]                      S_AXI_ARPROT;\n    wire [4-1:0]                      S_AXI_ARQOS;\n    wire [4-1:0]                      S_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     S_AXI_ARUSER;\n    wire                              S_AXI_ARVALID;\n    wire                              S_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_RID;       \n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_RDATA; \n    wire [2-1:0]                      S_AXI_RRESP;\n    wire                              S_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      S_AXI_RUSER;\n    wire                              S_AXI_RVALID;\n    wire                              S_AXI_RREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_ARID;        \n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_ARADDR;  \n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_ARLEN;\n    wire [3-1:0]                      M_AXI_ARSIZE;\n    wire [2-1:0]                      M_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_ARLOCK;\n    wire [4-1:0]                      M_AXI_ARCACHE;\n    wire [3-1:0]                      M_AXI_ARPROT;\n    wire [4-1:0]                      M_AXI_ARQOS;\n    wire [4-1:0]                      M_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     M_AXI_ARUSER;\n    wire                              M_AXI_ARVALID;\n    wire                              M_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_RID;        \n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_RDATA;  \n    wire [2-1:0]                      M_AXI_RRESP;\n    wire                              M_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      M_AXI_RUSER;\n    wire                              M_AXI_RVALID;\n    wire                              M_AXI_RREADY;\n    wire                              S_AXIS_TVALID;\n    wire                              S_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     S_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     S_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     S_AXIS_TKEEP;\n    wire                              S_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       S_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     S_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     S_AXIS_TUSER;\n    wire                              M_AXIS_TVALID;\n    wire                              M_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     M_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     M_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     M_AXIS_TKEEP;\n    wire                              M_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       M_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     M_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     M_AXIS_TUSER;\n    wire                              AXI_AW_INJECTSBITERR;\n    wire                              AXI_AW_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_RD_DATA_COUNT;\n    wire                              AXI_AW_SBITERR;\n    wire                              AXI_AW_DBITERR;\n    wire                              AXI_AW_OVERFLOW;\n    wire                              AXI_AW_UNDERFLOW;\n    wire                              AXI_AW_PROG_FULL;\n    wire                              AXI_AW_PROG_EMPTY;\n    wire                              AXI_W_INJECTSBITERR;\n    wire                              AXI_W_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_RD_DATA_COUNT;\n    wire                              AXI_W_SBITERR;\n    wire                              AXI_W_DBITERR;\n    wire                              AXI_W_OVERFLOW;\n    wire                              AXI_W_UNDERFLOW;\n    wire                              AXI_W_PROG_FULL;\n    wire                              AXI_W_PROG_EMPTY;\n    wire                              AXI_B_INJECTSBITERR;\n    wire                              AXI_B_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_RD_DATA_COUNT;\n    wire                              AXI_B_SBITERR;\n    wire                              AXI_B_DBITERR;\n    wire                              AXI_B_OVERFLOW;\n    wire                              AXI_B_UNDERFLOW;\n    wire                              AXI_B_PROG_FULL;\n    wire                              AXI_B_PROG_EMPTY;\n    wire                              AXI_AR_INJECTSBITERR;\n    wire                              AXI_AR_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_RD_DATA_COUNT;\n    wire                              AXI_AR_SBITERR;\n    wire                              AXI_AR_DBITERR;\n    wire                              AXI_AR_OVERFLOW;\n    wire                              AXI_AR_UNDERFLOW;\n    wire                              AXI_AR_PROG_FULL;\n    wire                              AXI_AR_PROG_EMPTY;\n    wire                              AXI_R_INJECTSBITERR;\n    wire                              AXI_R_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_RD_DATA_COUNT;\n    wire                              AXI_R_SBITERR;\n    wire                              AXI_R_DBITERR;\n    wire                              AXI_R_OVERFLOW;\n    wire                              AXI_R_UNDERFLOW;\n    wire                              AXI_R_PROG_FULL;\n    wire                              AXI_R_PROG_EMPTY;\n    wire                              AXIS_INJECTSBITERR;\n    wire                              AXIS_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_RD_DATA_COUNT;\n    wire                              AXIS_SBITERR;\n    wire                              AXIS_DBITERR;\n    wire                              AXIS_OVERFLOW;\n    wire                              AXIS_UNDERFLOW;\n    wire                              AXIS_PROG_FULL;\n    wire                              AXIS_PROG_EMPTY;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count_in;\n    wire                              wr_rst_int;\n    wire                              rd_rst_int;\n    wire                              wr_rst_busy_o;\n    wire                              wr_rst_busy_ntve;\n    wire                              wr_rst_busy_axis;\n    wire                              wr_rst_busy_wach;\n    wire                              wr_rst_busy_wdch;\n    wire                              wr_rst_busy_wrch;\n    wire                              wr_rst_busy_rach;\n    wire                              wr_rst_busy_rdch;\n\n\n\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n\n\n\n    // Conventional FIFO Interface Signals\n    assign BACKUP                 = backup;\n    assign BACKUP_MARKER          = backup_marker;\n    assign CLK                    = clk;\n    assign RST                    = rst;\n    assign SRST                   = srst;\n    assign WR_CLK                 = wr_clk;\n    assign WR_RST                 = wr_rst;\n    assign RD_CLK                 = rd_clk;\n    assign RD_RST                 = rd_rst;\n    assign WR_EN                  = wr_en;\n    assign RD_EN                  = rd_en;\n    assign INT_CLK                = int_clk;\n    assign INJECTDBITERR          = injectdbiterr;\n    assign INJECTSBITERR          = injectsbiterr;\n    assign SLEEP                  = sleep;\n    assign full                   = FULL;\n    assign almost_full            = ALMOST_FULL;\n    assign wr_ack                 = WR_ACK;\n    assign overflow               = OVERFLOW;\n    assign empty                  = EMPTY;\n    assign almost_empty           = ALMOST_EMPTY;\n    assign valid                  = VALID;\n    assign underflow              = UNDERFLOW;\n    assign prog_full              = PROG_FULL;\n    assign prog_empty             = PROG_EMPTY;\n    assign sbiterr                = SBITERR;\n    assign dbiterr                = DBITERR;\n//    assign wr_rst_busy            = WR_RST_BUSY | wr_rst_busy_o;\n    assign wr_rst_busy            = wr_rst_busy_o;\n    assign rd_rst_busy            = RD_RST_BUSY;\n    assign M_ACLK                 = m_aclk;\n    assign S_ACLK                 = s_aclk;\n    assign S_ARESETN              = s_aresetn;\n    assign S_ACLK_EN              = s_aclk_en;\n    assign M_ACLK_EN              = m_aclk_en;\n    assign S_AXI_AWVALID          = s_axi_awvalid;\n    assign s_axi_awready          = S_AXI_AWREADY;\n    assign S_AXI_WLAST            = s_axi_wlast;\n    assign S_AXI_WVALID           = s_axi_wvalid;\n    assign s_axi_wready           = S_AXI_WREADY;\n    assign s_axi_bvalid           = S_AXI_BVALID;\n    assign S_AXI_BREADY           = s_axi_bready;\n    assign m_axi_awvalid          = M_AXI_AWVALID;\n    assign M_AXI_AWREADY          = m_axi_awready;\n    assign m_axi_wlast            = M_AXI_WLAST;\n    assign m_axi_wvalid           = M_AXI_WVALID;\n    assign M_AXI_WREADY           = m_axi_wready;\n    assign M_AXI_BVALID           = m_axi_bvalid;\n    assign m_axi_bready           = M_AXI_BREADY;\n    assign S_AXI_ARVALID          = s_axi_arvalid;\n    assign s_axi_arready          = S_AXI_ARREADY;\n    assign s_axi_rlast            = S_AXI_RLAST;\n    assign s_axi_rvalid           = S_AXI_RVALID;\n    assign S_AXI_RREADY           = s_axi_rready;\n    assign m_axi_arvalid          = M_AXI_ARVALID;\n    assign M_AXI_ARREADY          = m_axi_arready;\n    assign M_AXI_RLAST            = m_axi_rlast;\n    assign M_AXI_RVALID           = m_axi_rvalid;\n    assign m_axi_rready           = M_AXI_RREADY;\n    assign S_AXIS_TVALID          = s_axis_tvalid;\n    assign s_axis_tready          = S_AXIS_TREADY;\n    assign S_AXIS_TLAST           = s_axis_tlast;\n    assign m_axis_tvalid          = M_AXIS_TVALID;\n    assign M_AXIS_TREADY          = m_axis_tready;\n    assign m_axis_tlast           = M_AXIS_TLAST;\n    assign AXI_AW_INJECTSBITERR   = axi_aw_injectsbiterr;\n    assign AXI_AW_INJECTDBITERR   = axi_aw_injectdbiterr;\n    assign axi_aw_sbiterr         = AXI_AW_SBITERR;\n    assign axi_aw_dbiterr         = AXI_AW_DBITERR;\n    assign axi_aw_overflow        = AXI_AW_OVERFLOW;\n    assign axi_aw_underflow       = AXI_AW_UNDERFLOW;\n    assign axi_aw_prog_full       = AXI_AW_PROG_FULL;\n    assign axi_aw_prog_empty      = AXI_AW_PROG_EMPTY;\n    assign AXI_W_INJECTSBITERR    = axi_w_injectsbiterr;\n    assign AXI_W_INJECTDBITERR    = axi_w_injectdbiterr;\n    assign axi_w_sbiterr          = AXI_W_SBITERR;\n    assign axi_w_dbiterr          = AXI_W_DBITERR;\n    assign axi_w_overflow         = AXI_W_OVERFLOW;\n    assign axi_w_underflow        = AXI_W_UNDERFLOW;\n    assign axi_w_prog_full        = AXI_W_PROG_FULL;\n    assign axi_w_prog_empty       = AXI_W_PROG_EMPTY;\n    assign AXI_B_INJECTSBITERR    = axi_b_injectsbiterr;\n    assign AXI_B_INJECTDBITERR    = axi_b_injectdbiterr;\n    assign axi_b_sbiterr          = AXI_B_SBITERR;\n    assign axi_b_dbiterr          = AXI_B_DBITERR;\n    assign axi_b_overflow         = AXI_B_OVERFLOW;\n    assign axi_b_underflow        = AXI_B_UNDERFLOW;\n    assign axi_b_prog_full        = AXI_B_PROG_FULL;\n    assign axi_b_prog_empty       = AXI_B_PROG_EMPTY;\n    assign AXI_AR_INJECTSBITERR   = axi_ar_injectsbiterr;\n    assign AXI_AR_INJECTDBITERR   = axi_ar_injectdbiterr;\n    assign axi_ar_sbiterr         = AXI_AR_SBITERR;\n    assign axi_ar_dbiterr         = AXI_AR_DBITERR;\n    assign axi_ar_overflow        = AXI_AR_OVERFLOW;\n    assign axi_ar_underflow       = AXI_AR_UNDERFLOW;\n    assign axi_ar_prog_full       = AXI_AR_PROG_FULL;\n    assign axi_ar_prog_empty      = AXI_AR_PROG_EMPTY;\n    assign AXI_R_INJECTSBITERR    = axi_r_injectsbiterr;\n    assign AXI_R_INJECTDBITERR    = axi_r_injectdbiterr;\n    assign axi_r_sbiterr          = AXI_R_SBITERR;\n    assign axi_r_dbiterr          = AXI_R_DBITERR;\n    assign axi_r_overflow         = AXI_R_OVERFLOW;\n    assign axi_r_underflow        = AXI_R_UNDERFLOW;\n    assign axi_r_prog_full        = AXI_R_PROG_FULL;\n    assign axi_r_prog_empty       = AXI_R_PROG_EMPTY;\n    assign AXIS_INJECTSBITERR     = axis_injectsbiterr;\n    assign AXIS_INJECTDBITERR     = axis_injectdbiterr;\n    assign axis_sbiterr           = AXIS_SBITERR;\n    assign axis_dbiterr           = AXIS_DBITERR;\n    assign axis_overflow          = AXIS_OVERFLOW;\n    assign axis_underflow         = AXIS_UNDERFLOW;\n    assign axis_prog_full         = AXIS_PROG_FULL;\n    assign axis_prog_empty        = AXIS_PROG_EMPTY;\n\n\n    assign DIN                       = din;\n    assign PROG_EMPTY_THRESH         = prog_empty_thresh;\n    assign PROG_EMPTY_THRESH_ASSERT  = prog_empty_thresh_assert;\n    assign PROG_EMPTY_THRESH_NEGATE  = prog_empty_thresh_negate;\n    assign PROG_FULL_THRESH          = prog_full_thresh;\n    assign PROG_FULL_THRESH_ASSERT   = prog_full_thresh_assert;\n    assign PROG_FULL_THRESH_NEGATE   = prog_full_thresh_negate;\n    assign dout                      = DOUT;\n    assign data_count                = DATA_COUNT;\n    assign rd_data_count             = RD_DATA_COUNT;\n    assign wr_data_count             = WR_DATA_COUNT;\n    assign S_AXI_AWID                = s_axi_awid;\n    assign S_AXI_AWADDR              = s_axi_awaddr;\n    assign S_AXI_AWLEN               = s_axi_awlen;\n    assign S_AXI_AWSIZE              = s_axi_awsize;\n    assign S_AXI_AWBURST             = s_axi_awburst;\n    assign S_AXI_AWLOCK              = s_axi_awlock;\n    assign S_AXI_AWCACHE             = s_axi_awcache;\n    assign S_AXI_AWPROT              = s_axi_awprot;\n    assign S_AXI_AWQOS               = s_axi_awqos;\n    assign S_AXI_AWREGION            = s_axi_awregion;\n    assign S_AXI_AWUSER              = s_axi_awuser;\n    assign S_AXI_WID                 = s_axi_wid;\n    assign S_AXI_WDATA               = s_axi_wdata;\n    assign S_AXI_WSTRB               = s_axi_wstrb;\n    assign S_AXI_WUSER               = s_axi_wuser;\n    assign s_axi_bid                 = S_AXI_BID;\n    assign s_axi_bresp               = S_AXI_BRESP;\n    assign s_axi_buser               = S_AXI_BUSER;\n    assign m_axi_awid                = M_AXI_AWID;\n    assign m_axi_awaddr              = M_AXI_AWADDR;\n    assign m_axi_awlen               = M_AXI_AWLEN;\n    assign m_axi_awsize              = M_AXI_AWSIZE;\n    assign m_axi_awburst             = M_AXI_AWBURST;\n    assign m_axi_awlock              = M_AXI_AWLOCK;\n    assign m_axi_awcache             = M_AXI_AWCACHE;\n    assign m_axi_awprot              = M_AXI_AWPROT;\n    assign m_axi_awqos               = M_AXI_AWQOS;\n    assign m_axi_awregion            = M_AXI_AWREGION;\n    assign m_axi_awuser              = M_AXI_AWUSER;\n    assign m_axi_wid                 = M_AXI_WID;\n    assign m_axi_wdata               = M_AXI_WDATA;\n    assign m_axi_wstrb               = M_AXI_WSTRB;\n    assign m_axi_wuser               = M_AXI_WUSER;\n    assign M_AXI_BID                 = m_axi_bid;\n    assign M_AXI_BRESP               = m_axi_bresp;\n    assign M_AXI_BUSER               = m_axi_buser;\n    assign S_AXI_ARID                = s_axi_arid;\n    assign S_AXI_ARADDR              = s_axi_araddr; \n    assign S_AXI_ARLEN               = s_axi_arlen;\n    assign S_AXI_ARSIZE              = s_axi_arsize;\n    assign S_AXI_ARBURST             = s_axi_arburst;\n    assign S_AXI_ARLOCK              = s_axi_arlock;\n    assign S_AXI_ARCACHE             = s_axi_arcache;\n    assign S_AXI_ARPROT              = s_axi_arprot;\n    assign S_AXI_ARQOS               = s_axi_arqos;\n    assign S_AXI_ARREGION            = s_axi_arregion;\n    assign S_AXI_ARUSER              = s_axi_aruser;\n    assign s_axi_rid                 = S_AXI_RID;\n    assign s_axi_rdata               = S_AXI_RDATA;\n    assign s_axi_rresp               = S_AXI_RRESP;\n    assign s_axi_ruser               = S_AXI_RUSER;\n    assign m_axi_arid                = M_AXI_ARID;        \n    assign m_axi_araddr              = M_AXI_ARADDR;  \n    assign m_axi_arlen               = M_AXI_ARLEN;\n    assign m_axi_arsize              = M_AXI_ARSIZE;\n    assign m_axi_arburst             = M_AXI_ARBURST;\n    assign m_axi_arlock              = M_AXI_ARLOCK;\n    assign m_axi_arcache             = M_AXI_ARCACHE;\n    assign m_axi_arprot              = M_AXI_ARPROT;\n    assign m_axi_arqos               = M_AXI_ARQOS;\n    assign m_axi_arregion            = M_AXI_ARREGION;\n    assign m_axi_aruser              = M_AXI_ARUSER;\n    assign M_AXI_RID                 = m_axi_rid;        \n    assign M_AXI_RDATA               = m_axi_rdata;  \n    assign M_AXI_RRESP               = m_axi_rresp;\n    assign M_AXI_RUSER               = m_axi_ruser;\n    assign S_AXIS_TDATA              = s_axis_tdata;\n    assign S_AXIS_TSTRB              = s_axis_tstrb;\n    assign S_AXIS_TKEEP              = s_axis_tkeep;\n    assign S_AXIS_TID                = s_axis_tid;\n    assign S_AXIS_TDEST              = s_axis_tdest;\n    assign S_AXIS_TUSER              = s_axis_tuser;\n    assign m_axis_tdata              = M_AXIS_TDATA;\n    assign m_axis_tstrb              = M_AXIS_TSTRB;\n    assign m_axis_tkeep              = M_AXIS_TKEEP;\n    assign m_axis_tid                = M_AXIS_TID;\n    assign m_axis_tdest              = M_AXIS_TDEST;\n    assign m_axis_tuser              = M_AXIS_TUSER;\n    assign AXI_AW_PROG_FULL_THRESH   = axi_aw_prog_full_thresh;\n    assign AXI_AW_PROG_EMPTY_THRESH  = axi_aw_prog_empty_thresh;\n    assign axi_aw_data_count         = AXI_AW_DATA_COUNT;\n    assign axi_aw_wr_data_count      = AXI_AW_WR_DATA_COUNT;\n    assign axi_aw_rd_data_count      = AXI_AW_RD_DATA_COUNT;\n    assign AXI_W_PROG_FULL_THRESH    = axi_w_prog_full_thresh;\n    assign AXI_W_PROG_EMPTY_THRESH   = axi_w_prog_empty_thresh;\n    assign axi_w_data_count          = AXI_W_DATA_COUNT;\n    assign axi_w_wr_data_count       = AXI_W_WR_DATA_COUNT;\n    assign axi_w_rd_data_count       = AXI_W_RD_DATA_COUNT;\n    assign AXI_B_PROG_FULL_THRESH    = axi_b_prog_full_thresh;\n    assign AXI_B_PROG_EMPTY_THRESH   = axi_b_prog_empty_thresh;\n    assign axi_b_data_count          = AXI_B_DATA_COUNT;\n    assign axi_b_wr_data_count       = AXI_B_WR_DATA_COUNT;\n    assign axi_b_rd_data_count       = AXI_B_RD_DATA_COUNT;\n    assign AXI_AR_PROG_FULL_THRESH   = axi_ar_prog_full_thresh;\n    assign AXI_AR_PROG_EMPTY_THRESH  = axi_ar_prog_empty_thresh;\n    assign axi_ar_data_count         = AXI_AR_DATA_COUNT;\n    assign axi_ar_wr_data_count      = AXI_AR_WR_DATA_COUNT;\n    assign axi_ar_rd_data_count      = AXI_AR_RD_DATA_COUNT;\n    assign AXI_R_PROG_FULL_THRESH    = axi_r_prog_full_thresh;\n    assign AXI_R_PROG_EMPTY_THRESH   = axi_r_prog_empty_thresh;\n    assign axi_r_data_count          = AXI_R_DATA_COUNT;\n    assign axi_r_wr_data_count       = AXI_R_WR_DATA_COUNT;\n    assign axi_r_rd_data_count       = AXI_R_RD_DATA_COUNT;\n    assign AXIS_PROG_FULL_THRESH     = axis_prog_full_thresh;\n    assign AXIS_PROG_EMPTY_THRESH    = axis_prog_empty_thresh;\n    assign axis_data_count           = AXIS_DATA_COUNT;\n    assign axis_wr_data_count        = AXIS_WR_DATA_COUNT;\n    assign axis_rd_data_count        = AXIS_RD_DATA_COUNT;\n\n\n  generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_COMMON_CLOCK \t\t(C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DATA_COUNT_WIDTH\t\t(C_DATA_COUNT_WIDTH),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH),\n        .C_DOUT_RST_VAL\t\t\t(C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),\n        .C_DOUT_WIDTH\t\t\t(C_DOUT_WIDTH),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n        .C_HAS_ALMOST_EMPTY\t\t(C_HAS_ALMOST_EMPTY),\n        .C_HAS_ALMOST_FULL\t\t(C_HAS_ALMOST_FULL),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_DATA_COUNT\t\t(C_HAS_DATA_COUNT),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_HAS_RD_DATA_COUNT\t\t(C_HAS_RD_DATA_COUNT),\n        .C_HAS_RD_RST\t\t\t(C_HAS_RD_RST),\n        .C_HAS_RST\t\t\t(C_HAS_RST),\n        .C_HAS_SRST\t\t\t(C_HAS_SRST),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_HAS_VALID\t\t\t(C_HAS_VALID),\n        .C_HAS_WR_ACK\t\t\t(C_HAS_WR_ACK),\n        .C_HAS_WR_DATA_COUNT\t\t(C_HAS_WR_DATA_COUNT),\n        .C_HAS_WR_RST\t\t\t(C_HAS_WR_RST),\n        .C_IMPLEMENTATION_TYPE\t\t(C_IMPLEMENTATION_TYPE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_MEMORY_TYPE\t\t\t(C_MEMORY_TYPE),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n        .C_PRELOAD_LATENCY\t\t(C_PRELOAD_LATENCY),\n        .C_PRELOAD_REGS\t\t\t(C_PRELOAD_REGS),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL),\n        .C_PROG_EMPTY_THRESH_NEGATE_VAL\t(C_PROG_EMPTY_THRESH_NEGATE_VAL),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL),\n        .C_PROG_FULL_THRESH_NEGATE_VAL\t(C_PROG_FULL_THRESH_NEGATE_VAL),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_RD_DATA_COUNT_WIDTH),\n        .C_RD_DEPTH\t\t\t(C_RD_DEPTH),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_RD_PNTR_WIDTH\t\t(C_RD_PNTR_WIDTH),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n        .C_USE_ECC                      (C_USE_ECC),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_EN_SAFETY_CKT\t\t(C_EN_SAFETY_CKT),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_USE_FWFT_DATA_COUNT\t\t(C_USE_FWFT_DATA_COUNT),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_DATA_COUNT_WIDTH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (C_ENABLE_RST_SYNC),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE),\n        .C_AXI_TYPE                     (C_AXI_TYPE),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE)\n      )\n    fifo_generator_v13_2_1_conv_dut\n      (\n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .CLK                      (CLK),\n        .RST                      (RST),\n        .SRST                     (SRST),\n        .WR_CLK                   (WR_CLK),\n        .WR_RST                   (WR_RST),\n        .RD_CLK                   (RD_CLK),\n        .RD_RST                   (RD_RST),\n        .DIN                      (DIN),\n        .WR_EN                    (WR_EN),\n        .RD_EN                    (RD_EN),\n        .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),\n        .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),\n        .PROG_FULL_THRESH         (PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),\n        .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),\n        .INT_CLK                  (INT_CLK),\n        .INJECTDBITERR            (INJECTDBITERR), \n        .INJECTSBITERR            (INJECTSBITERR),\n  \n        .DOUT                     (DOUT),\n        .FULL                     (FULL),\n        .ALMOST_FULL              (ALMOST_FULL),\n        .WR_ACK                   (WR_ACK),\n        .OVERFLOW                 (OVERFLOW),\n        .EMPTY                    (EMPTY),\n        .ALMOST_EMPTY             (ALMOST_EMPTY),\n        .VALID                    (VALID),\n        .UNDERFLOW                (UNDERFLOW),\n        .DATA_COUNT               (DATA_COUNT),\n        .RD_DATA_COUNT            (RD_DATA_COUNT),\n        .WR_DATA_COUNT            (wr_data_count_in),\n        .PROG_FULL                (PROG_FULL),\n        .PROG_EMPTY               (PROG_EMPTY),\n        .SBITERR                  (SBITERR),\n        .DBITERR                  (DBITERR),\n        .wr_rst_busy_o            (wr_rst_busy_o),\n        .wr_rst_busy              (wr_rst_busy_i),\n        .rd_rst_busy              (rd_rst_busy),\n        .wr_rst_i_out             (wr_rst_int),\n        .rd_rst_i_out             (rd_rst_int)\n       );\n  end endgenerate\n\n\n\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n  localparam C_AXI_SIZE_WIDTH   = 3;\n  localparam C_AXI_BURST_WIDTH  = 2;\n  localparam C_AXI_CACHE_WIDTH  = 4;\n  localparam C_AXI_PROT_WIDTH   = 3;\n  localparam C_AXI_QOS_WIDTH    = 4;\n  localparam C_AXI_REGION_WIDTH = 4;\n  localparam C_AXI_BRESP_WIDTH  = 2;\n  localparam C_AXI_RRESP_WIDTH  = 2;\n\n  localparam IS_AXI_STREAMING  = C_INTERFACE_TYPE == 1 ? 1 : 0;\n  localparam TDATA_OFFSET      = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;\n  localparam TSTRB_OFFSET      = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;\n  localparam TKEEP_OFFSET      = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;\n  localparam TID_OFFSET        = C_HAS_AXIS_TID   == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;\n  localparam TDEST_OFFSET      = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;\n  localparam TUSER_OFFSET      = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;\n  localparam LOG_DEPTH_AXIS    = find_log2(C_WR_DEPTH_AXIS); \n  localparam LOG_WR_DEPTH      = find_log2(C_WR_DEPTH); \n\n\n  function [LOG_DEPTH_AXIS-1:0] bin2gray;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      begin\n         bin2gray = x ^ (x>>1);\n      end\n   endfunction\n\n  function [LOG_DEPTH_AXIS-1:0] gray2bin;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      integer                i;\n      begin\n         gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];\n         for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin\n            gray2bin[i] =  gray2bin[i+1] ^ x[i];\n         end\n      end\n   endfunction\n\nwire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;\nwire  [LOG_WR_DEPTH-1 : 0]  w_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;\nreg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;\nwire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;\nwire [LOG_WR_DEPTH : 0] r_inv_pad;\nwire [LOG_WR_DEPTH-1 : 0] d_cnt;\nreg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;\nreg adj_w_cnt_rd_pad_0 = 0;\nreg r_inv_pad_0 = 0;\n\n\n   genvar l;\n\n   generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage\n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (LOG_WR_DEPTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_int), \n         .CLK      (RD_CLK), \n         .DIN      (w_q[l-1]), \n         .DOUT     (w_q[l])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter\n    assign wr_eop_ad = WR_EN & !(FULL);\n    assign rd_eop_ad = RD_EN & !(EMPTY);\n\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt    <= 1'b0;\n      else if (wr_eop_ad)\n        w_cnt    <= w_cnt + 1;\n    end\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt_gc    <= 1'b0;\n      else \n        w_cnt_gc    <= bin2gray(w_cnt);\n    end\n\n\n    assign  w_q[0]  = w_cnt_gc;\n    assign  w_cnt_gc_asreg_last       = w_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        w_cnt_rd    <= 1'b0;\n      else \n        w_cnt_rd    <= gray2bin(w_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        r_cnt    <= 1'b0;\n      else if (rd_eop_ad)\n        r_cnt    <= r_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;\n   assign r_inv_pad[LOG_WR_DEPTH : 1]        = ~r_cnt;\n   assign adj_w_cnt_rd_pad[0]                = adj_w_cnt_rd_pad_0;\n   assign r_inv_pad[0]                       = r_inv_pad_0;\n\n\n  always @ ( rd_eop_ad )\n    begin\n      if (!rd_eop_ad) begin\n        adj_w_cnt_rd_pad_0    <= 1'b1;\n        r_inv_pad_0           <= 1'b1;\n      end else begin \n        adj_w_cnt_rd_pad_0    <= 1'b0;\n        r_inv_pad_0           <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        d_cnt_pad    <= 1'b0;\n      else \n        d_cnt_pad    <= adj_w_cnt_rd_pad + r_inv_pad ;\n    end\n\n   assign  d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;\n   assign  WR_DATA_COUNT = d_cnt;\n\n  end endgenerate // fifo_ic_adapter\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter\n   assign  WR_DATA_COUNT = wr_data_count_in;\n\n  end endgenerate // fifo_icn_adapter\n\n\n\n  wire                          inverted_reset = ~S_ARESETN;\n  wire                          axi_rs_rst;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_din          ;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_dout         ;\n  wire                          axis_full         ;\n  wire                          axis_almost_full  ;\n  wire                          axis_empty        ;\n  wire                          axis_s_axis_tready;\n  wire                          axis_m_axis_tvalid;\n  wire                          axis_wr_en        ;\n  wire                          axis_rd_en        ;\n  wire                          axis_we           ;\n  wire                          axis_re           ;\n  wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;\n  reg                           axis_pkt_read = 1'b0;\n  wire                          axis_rd_rst;\n  wire                          axis_wr_rst;\n\n  generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||\n               C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst\n      reg                           rst_d1 = 0        ;\n      reg                           rst_d2 = 0        ;\n      reg [3:0]                    axi_rst = 4'h0     ;\n      always @ (posedge inverted_reset or posedge S_ACLK) begin\n        if (inverted_reset) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          axi_rst        <= 4'hf;\n        end else begin\n          rst_d1         <= #`TCQ 1'b0;\n          rst_d2         <= #`TCQ rst_d1;\n          axi_rst        <= #`TCQ {axi_rst[2:0],1'b0};\n        end\n      end\n\n      assign axi_rs_rst = axi_rst[3];//rst_d2;\n  end endgenerate // gaxi_rs_rst\n\n  generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming\n\n    // Write protection when almost full or prog_full is high\n    assign axis_we    = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : \n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign axis_re    = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :\n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? axis_we & S_ACLK_EN : axis_we;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE               (C_INTERFACE_TYPE),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 2  || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_AXIS),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_AXIS),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),\n        .C_USE_ECC                      (C_USE_ECC_AXIS),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_AXIS),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_axis_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (axis_wr_en),\n        .RD_EN                    (axis_rd_en),\n        .PROG_FULL_THRESH         (AXIS_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXIS_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .INJECTDBITERR            (AXIS_INJECTDBITERR), \n        .INJECTSBITERR            (AXIS_INJECTSBITERR),\n  \n        .DIN                      (axis_din),\n        .DOUT                     (axis_dout),\n        .FULL                     (axis_full),\n        .EMPTY                    (axis_empty),\n        .ALMOST_FULL              (axis_almost_full),\n        .PROG_FULL                (AXIS_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXIS_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (AXIS_OVERFLOW),\n        .VALID                    (),\n        .UNDERFLOW                (AXIS_UNDERFLOW),\n        .DATA_COUNT               (axis_dc),\n        .RD_DATA_COUNT            (AXIS_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXIS_WR_DATA_COUNT),\n        .SBITERR                  (AXIS_SBITERR),\n        .DBITERR                  (AXIS_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_axis),\n        .rd_rst_busy              (rd_rst_busy_axis),\n        .wr_rst_i_out             (axis_wr_rst),\n        .rd_rst_i_out             (axis_rd_rst),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign axis_s_axis_tready    = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;\n    assign axis_m_axis_tvalid    = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;\n    assign S_AXIS_TREADY         = axis_s_axis_tready;\n    assign M_AXIS_TVALID         = axis_m_axis_tvalid;\n\n  end endgenerate // axi_streaming\n\n  wire axis_wr_eop;\n  reg  axis_wr_eop_d1 = 1'b0;\n  wire axis_rd_eop;\n  integer  axis_pkt_cnt;\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)\n        axis_pkt_read    <= 1'b0;\n      else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_wr_eop_d1    <= 1'b0;\n      else\n        axis_wr_eop_d1   <= axis_wr_eop;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_cnt    <= 0;\n      else if (axis_wr_eop_d1 && ~axis_rd_eop)\n        axis_pkt_cnt    <= axis_pkt_cnt + 1;\n      else if (axis_rd_eop && ~axis_wr_eop_d1)\n        axis_pkt_cnt    <= axis_pkt_cnt - 1;\n    end\n  end endgenerate // gaxis_pkt_fifo_cc\n\n\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;\nwire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;\nwire axis_rd_has_rst;\nwire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;\nwire  [LOG_DEPTH_AXIS-1 : 0]  wpkt_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;\nwire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;\nwire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;\nwire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;\nwire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;\nreg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;\nreg adj_axis_wpkt_cnt_rd_pad_0 = 0;\nreg rpkt_inv_pad_0 = 0;\nwire axis_af_rd ;\n\ngenerate if (C_HAS_RST == 1) begin : rst_blk_has\n  assign axis_rd_has_rst = axis_rd_rst;\nend endgenerate //rst_blk_has\n\ngenerate if (C_HAS_RST == 0) begin :rst_blk_no\n  assign axis_rd_has_rst = 1'b0;\nend endgenerate //rst_blk_no\n\n   genvar i;\n\n   generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage\n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (LOG_DEPTH_AXIS)\n        )\n     rd_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (wpkt_q[i-1]), \n         .DOUT     (wpkt_q[i])\n        );\n \n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (1)\n        )\n     wr_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (axis_af_q[i-1]), \n         .DOUT     (axis_af_q[i])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (diff_pkt_cnt == 1))\n        axis_pkt_read    <= 1'b0;\n      else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt    <= 1'b0;\n      else if (axis_wr_eop)\n        axis_wpkt_cnt    <= axis_wpkt_cnt + 1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt_gc    <= 1'b0;\n      else \n        axis_wpkt_cnt_gc    <= bin2gray(axis_wpkt_cnt);\n    end\n\n\n    assign  wpkt_q[0]  = axis_wpkt_cnt_gc;\n    assign  axis_wpkt_cnt_gc_asreg_last       = wpkt_q[C_SYNCHRONIZER_STAGE];\n    assign  axis_af_q[0]                      = axis_almost_full;\n    //assign  axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];\n    assign  axis_af_rd                        = axis_af_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_wpkt_cnt_rd    <= 1'b0;\n      else \n        axis_wpkt_cnt_rd    <= gray2bin(axis_wpkt_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_rpkt_cnt    <= 1'b0;\n      else if (axis_rd_eop)\n        axis_rpkt_cnt    <= axis_rpkt_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;\n   assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1]             = ~axis_rpkt_cnt;\n   assign adj_axis_wpkt_cnt_rd_pad[0]                                = adj_axis_wpkt_cnt_rd_pad_0;\n   assign rpkt_inv_pad[0]                                            = rpkt_inv_pad_0;\n\n\n  always @ ( axis_rd_eop )\n    begin\n      if (!axis_rd_eop) begin\n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b1;\n        rpkt_inv_pad_0                <= 1'b1;\n      end else begin \n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b0;\n        rpkt_inv_pad_0                <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        diff_pkt_cnt_pad    <= 1'b0;\n      else \n        diff_pkt_cnt_pad    <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;\n    end\n\n   assign  diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;\n\n\n\n\n\n   end endgenerate // gaxis_pkt_fifo_ic\n\n\n\n\n  // Generate the accurate data count for axi stream packet fifo configuration\n  reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_dc_pkt_fifo <= 0;\n      else if (axis_wr_en && (~axis_rd_en))\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;\n      else if (~axis_wr_en && axis_rd_en)\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;\n    end\n    assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;\n  end endgenerate // gdc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt\n    assign AXIS_DATA_COUNT = 0;\n  end endgenerate // gndc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc\n    assign AXIS_DATA_COUNT = axis_dc;\n  end endgenerate // gdc\n\n  // Register Slice for Write Address Channel\n  generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_AXIS),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_AXIS)\n            )\n    axis_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (axis_din),\n          .S_VALID                   (axis_wr_en),\n          .S_READY                   (S_AXIS_TREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (axis_dout),\n          .M_VALID                   (M_AXIS_TVALID),\n          .M_READY                   (axis_rd_en)\n          );\n  end endgenerate // gaxis_reg_slice\n\n\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata\n    assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;\n    assign M_AXIS_TDATA   = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb\n    assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;\n    assign M_AXIS_TSTRB   = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep\n    assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;\n    assign M_AXIS_TKEEP   = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid\n    assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;\n    assign M_AXIS_TID     = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest\n    assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;\n    assign M_AXIS_TDEST   = axis_dout[TID_OFFSET-1:TDEST_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser\n    assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;\n    assign M_AXIS_TUSER   = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast\n    assign axis_din[0] = S_AXIS_TLAST;\n    assign M_AXIS_TLAST   = axis_dout[0];\n  end endgenerate\n\n  //###########################################################################\n  //  AXI FULL Write Channel (axi_write_channel)\n  //###########################################################################\n\n  localparam IS_AXI_FULL       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;\n  localparam IS_AXI_LITE       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;\n\n  localparam IS_AXI_FULL_WACH  = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WDCH  = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WRCH  = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RACH  = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RDCH  = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_AXI_LITE_WACH  = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WDCH  = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WRCH  = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RACH  = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RDCH  = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_WR_ADDR_CH     = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;\n  localparam IS_WR_DATA_CH     = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;\n  localparam IS_WR_RESP_CH     = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;\n  localparam IS_RD_ADDR_CH     = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;\n  localparam IS_RD_DATA_CH     = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;\n\n  localparam AWID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;\n  localparam AWADDR_OFFSET     = AWID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam AWLEN_OFFSET      = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;\n  localparam AWSIZE_OFFSET     = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;\n  localparam AWBURST_OFFSET    = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;\n  localparam AWLOCK_OFFSET     = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;\n  localparam AWCACHE_OFFSET    = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;\n  localparam AWPROT_OFFSET     = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam AWQOS_OFFSET      = AWPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam AWREGION_OFFSET   = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;\n  localparam AWUSER_OFFSET     = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;\n\n  localparam WID_OFFSET        = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;\n  localparam WDATA_OFFSET      = WID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam WSTRB_OFFSET      = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;\n  localparam WUSER_OFFSET      = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;\n\n  localparam BID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;\n  localparam BRESP_OFFSET      = BID_OFFSET - C_AXI_BRESP_WIDTH;\n  localparam BUSER_OFFSET      = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;\n\n\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_din          ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout         ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout_pkt     ;\n  wire                          wach_full         ;\n  wire                          wach_almost_full  ;\n  wire                          wach_prog_full    ;\n  wire                          wach_empty        ;\n  wire                          wach_almost_empty ;\n  wire                          wach_prog_empty   ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_din          ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_dout         ;\n  wire                          wdch_full         ;\n  wire                          wdch_almost_full  ;\n  wire                          wdch_prog_full    ;\n  wire                          wdch_empty        ;\n  wire                          wdch_almost_empty ;\n  wire                          wdch_prog_empty   ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_din          ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_dout         ;\n  wire                          wrch_full         ;\n  wire                          wrch_almost_full  ;\n  wire                          wrch_prog_full    ;\n  wire                          wrch_empty        ;\n  wire                          wrch_almost_empty ;\n  wire                          wrch_prog_empty   ;\n  wire                          axi_aw_underflow_i;\n  wire                          axi_w_underflow_i ;\n  wire                          axi_b_underflow_i ;\n  wire                          axi_aw_overflow_i ;\n  wire                          axi_w_overflow_i  ;\n  wire                          axi_b_overflow_i  ;\n  wire                          axi_wr_underflow_i;\n  wire                          axi_wr_overflow_i ;\n  wire                          wach_s_axi_awready;\n  wire                          wach_m_axi_awvalid;\n  wire                          wach_wr_en        ;\n  wire                          wach_rd_en        ;\n  wire                          wdch_s_axi_wready ;\n  wire                          wdch_m_axi_wvalid ;\n  wire                          wdch_wr_en        ;\n  wire                          wdch_rd_en        ;\n  wire                          wrch_s_axi_bvalid ;\n  wire                          wrch_m_axi_bready ;\n  wire                          wrch_wr_en        ;\n  wire                          wrch_rd_en        ;\n  wire                          txn_count_up      ;\n  wire                          txn_count_down    ;\n  wire                          awvalid_en        ;\n  wire                          awvalid_pkt       ;\n  wire                          awready_pkt       ;\n  integer                       wr_pkt_count      ;\n  wire                          wach_we           ;\n  wire                          wach_re           ;\n  wire                          wdch_we           ;\n  wire                          wdch_re           ;\n  wire                          wrch_we           ;\n  wire                          wrch_re           ;\n\n  generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel\n    // Write protection when almost full or prog_full is high\n    assign wach_we    = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wach_re    = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        wach_m_axi_awvalid & awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY && wach_m_axi_awvalid :\n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY : 1'b0;\n    assign wach_wr_en = (C_HAS_SLAVE_CE == 1)  ? wach_we & S_ACLK_EN : wach_we;\n    assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 2  || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),\n        .C_USE_ECC                      (C_USE_ECC_WACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_wach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wach_wr_en),\n        .RD_EN                    (wach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AW_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AW_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AW_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AW_INJECTSBITERR),\n  \n        .DIN                      (wach_din),\n        .DOUT                     (wach_dout_pkt),\n        .FULL                     (wach_full),\n        .EMPTY                    (wach_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_AW_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_AW_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_aw_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_aw_underflow_i),\n        .DATA_COUNT               (AXI_AW_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AW_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AW_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AW_SBITERR),\n        .DBITERR                  (AXI_AW_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wach),\n        .rd_rst_busy              (rd_rst_busy_wach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wach_s_axi_awready    = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;\n    assign wach_m_axi_awvalid   = ~wach_empty;\n    assign S_AXI_AWREADY        = wach_s_axi_awready;\n\n    assign AXI_AW_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;\n    assign AXI_AW_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_aw_overflow_i  : 0;\n\n  end endgenerate // axi_write_address_channel\n\n  // Register Slice for Write Address Channel\n  generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WACH)\n            )\n    wach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_din),\n          .S_VALID                   (S_AXI_AWVALID),\n          .S_READY                   (S_AXI_AWREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n  end endgenerate // gwach_reg_slice\n  \n  generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (1)\n            )\n    wach_pkt_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_dout_pkt),\n          .S_VALID                   (awvalid_pkt),\n          .S_READY                   (awready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n\n    assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;\n\n    assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; \n    assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset == 1) begin\n\twr_pkt_count <= 0;\n      end else begin\n\tif(txn_count_up == 1 && txn_count_down == 0) begin\n\t  wr_pkt_count <= wr_pkt_count + 1;\n\tend else if(txn_count_up == 0 && txn_count_down == 1) begin\n\t  wr_pkt_count <= wr_pkt_count - 1;\n\tend\n      end\n    end //Always end\n    assign awvalid_en = (wr_pkt_count > 0)?1:0;\n  end endgenerate\n  \n  generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr\n    assign awvalid_en    = 1;    \n    assign wach_dout     = wach_dout_pkt;\n    assign M_AXI_AWVALID = wach_m_axi_awvalid;\n  end\n  endgenerate\n\n\n\n  generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel\n    // Write protection when almost full or prog_full is high\n    assign wdch_we    = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wdch_re    = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;\n    assign wdch_wr_en = (C_HAS_SLAVE_CE == 1)  ? wdch_we & S_ACLK_EN : wdch_we;\n    assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;\n\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 2  || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),\n        .C_USE_ECC                      (C_USE_ECC_WDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_wdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wdch_wr_en),\n        .RD_EN                    (wdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_W_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_W_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_W_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_W_INJECTSBITERR),\n  \n        .DIN                      (wdch_din),\n        .DOUT                     (wdch_dout),\n        .FULL                     (wdch_full),\n        .EMPTY                    (wdch_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_W_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_W_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_w_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_w_underflow_i),\n        .DATA_COUNT               (AXI_W_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_W_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_W_WR_DATA_COUNT),\n        .SBITERR                  (AXI_W_SBITERR),\n        .DBITERR                  (AXI_W_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wdch),\n        .rd_rst_busy              (rd_rst_busy_wdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wdch_s_axi_wready     = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;\n    assign wdch_m_axi_wvalid = ~wdch_empty;\n    assign S_AXI_WREADY      = wdch_s_axi_wready;\n    assign M_AXI_WVALID      = wdch_m_axi_wvalid;\n\n    assign AXI_W_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i  : 0;\n    assign AXI_W_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_w_overflow_i   : 0;\n\n  end endgenerate // axi_write_data_channel\n\n  // Register Slice for Write Data Channel\n  generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WDCH)\n            )\n    wdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wdch_din),\n          .S_VALID                   (S_AXI_WVALID),\n          .S_READY                   (S_AXI_WREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wdch_dout),\n          .M_VALID                   (M_AXI_WVALID),\n          .M_READY                   (M_AXI_WREADY)\n          );\n  end endgenerate // gwdch_reg_slice\n\n  generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel\n    // Write protection when almost full or prog_full is high\n    assign wrch_we    = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wrch_re    = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;\n    assign wrch_wr_en = (C_HAS_MASTER_CE == 1)  ? wrch_we & M_ACLK_EN : wrch_we;\n    assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 2  || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WRCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WRCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),\n        .C_USE_ECC                      (C_USE_ECC_WRCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WRCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WRCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_wrch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wrch_wr_en),\n        .RD_EN                    (wrch_rd_en),\n        .PROG_FULL_THRESH         (AXI_B_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_B_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .INJECTDBITERR            (AXI_B_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_B_INJECTSBITERR),\n  \n        .DIN                      (wrch_din),\n        .DOUT                     (wrch_dout),\n        .FULL                     (wrch_full),\n        .EMPTY                    (wrch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_B_PROG_FULL),\n        .PROG_EMPTY               (AXI_B_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_b_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_b_underflow_i),\n        .DATA_COUNT               (AXI_B_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_B_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_B_WR_DATA_COUNT),\n        .SBITERR                  (AXI_B_SBITERR),\n        .DBITERR                  (AXI_B_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wrch),\n        .rd_rst_busy              (rd_rst_busy_wrch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wrch_s_axi_bvalid = ~wrch_empty;\n    assign wrch_m_axi_bready     = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;\n    assign S_AXI_BVALID      = wrch_s_axi_bvalid;\n    assign M_AXI_BREADY      = wrch_m_axi_bready;\n\n    assign AXI_B_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i  : 0;\n    assign AXI_B_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_b_overflow_i   : 0;\n  end endgenerate // axi_write_resp_channel\n\n  // Register Slice for Write Response Channel\n  generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WRCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WRCH)\n            )\n    wrch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wrch_din),\n          .S_VALID                   (M_AXI_BVALID),\n          .S_READY                   (M_AXI_BREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wrch_dout),\n          .M_VALID                   (S_AXI_BVALID),\n          .M_READY                   (S_AXI_BREADY)\n          );\n  end endgenerate // gwrch_reg_slice\n\n\n    assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW  == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;\n    assign axi_wr_overflow_i  = C_USE_COMMON_OVERFLOW   == 1 ? (axi_aw_overflow_i  || axi_w_overflow_i  || axi_b_overflow_i)  : 0;\n\n  generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output\n    assign M_AXI_AWADDR    = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];    \n    assign M_AXI_AWLEN     = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];    \n    assign M_AXI_AWSIZE    = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];    \n    assign M_AXI_AWBURST   = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];    \n    assign M_AXI_AWLOCK    = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];    \n    assign M_AXI_AWCACHE   = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];    \n    assign M_AXI_AWQOS     = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];    \n    assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET]    = S_AXI_AWADDR;\n    assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET]   = S_AXI_AWLEN;\n    assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET]   = S_AXI_AWSIZE;\n    assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;\n    assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;\n    assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;\n    assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;\n    assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET]   = S_AXI_AWQOS;\n  end endgenerate // axi_wach_output\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion\n    assign M_AXI_AWREGION  = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];    \n  end endgenerate // axi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion\n    assign M_AXI_AWREGION  = 0;    \n  end endgenerate // naxi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser\n    assign M_AXI_AWUSER  = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];    \n  end endgenerate // axi_awuser\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser\n    assign M_AXI_AWUSER  = 0;    \n  end endgenerate // naxi_awuser\n\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid\n    assign M_AXI_AWID      = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];\n  end endgenerate //axi_awid\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid\n    assign M_AXI_AWID      = 0;\n  end endgenerate //naxi_awid\n\n  generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output\n    assign M_AXI_WDATA     = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n    assign M_AXI_WLAST     = wdch_dout[0];\n    assign wdch_din[WID_OFFSET-1:WDATA_OFFSET]   = S_AXI_WDATA;\n    assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;\n    assign wdch_din[0]   = S_AXI_WLAST;\n  end endgenerate // axi_wdch_output\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin\n    assign M_AXI_WID       = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];\n  end endgenerate\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin\n    assign M_AXI_WID       = 0;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin\n    assign M_AXI_WUSER     = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];    \n  end endgenerate\n  generate if (C_HAS_AXI_WUSER == 0) begin\n    assign M_AXI_WUSER       = 0;\n  end endgenerate\n\n  generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output\n    assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; \n    assign wrch_din[BID_OFFSET-1:BRESP_OFFSET]   = M_AXI_BRESP;\n  end endgenerate // axi_wrch_output\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser\n    assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];\n  end endgenerate // axi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser\n    assign S_AXI_BUSER = 0;\n  end endgenerate // naxi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid\n    assign S_AXI_BID   =  wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];\n  end endgenerate // axi_bid\n  \n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid\n    assign S_AXI_BID   =  0 ;\n  end endgenerate // naxi_bid  \n\n\n  generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1\n    assign wach_din        = {S_AXI_AWADDR, S_AXI_AWPROT};\n    assign M_AXI_AWADDR    = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];    \n  end endgenerate // axi_wach_output1\n\n  generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1\n    assign wdch_din        = {S_AXI_WDATA, S_AXI_WSTRB};\n    assign M_AXI_WDATA     = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n  end endgenerate // axi_wdch_output1\n\n  generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1\n    assign wrch_din        = M_AXI_BRESP;\n    assign S_AXI_BRESP     = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; \n  end endgenerate // axi_wrch_output1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1\n    assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET]     = S_AXI_AWUSER;\n  end endgenerate // gwach_din1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2\n    assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET]     = S_AXI_AWID;\n  end endgenerate // gwach_din2\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3\n    assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET]     = S_AXI_AWREGION;\n  end endgenerate // gwach_din3\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1\n    assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;\n  end endgenerate // gwdch_din1\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2\n    assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;\n  end endgenerate // gwdch_din2\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1\n    assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET]    = M_AXI_BUSER;\n  end endgenerate // gwrch_din1\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2\n    assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET]    = M_AXI_BID;\n  end endgenerate // gwrch_din2\n\n  //end of  axi_write_channel\n\n  //###########################################################################\n  //  AXI FULL Read Channel (axi_read_channel)\n  //###########################################################################\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_din            ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout           ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout_pkt       ;\n  wire                               rach_full           ;\n  wire                               rach_almost_full    ;\n  wire                               rach_prog_full      ;\n  wire                               rach_empty          ;\n  wire                               rach_almost_empty   ;\n  wire                               rach_prog_empty     ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_din            ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_dout           ;\n  wire                               rdch_full           ;\n  wire                               rdch_almost_full    ;\n  wire                               rdch_prog_full      ;\n  wire                               rdch_empty          ;\n  wire                               rdch_almost_empty   ;\n  wire                               rdch_prog_empty     ;\n  wire                               axi_ar_underflow_i  ;\n  wire                               axi_r_underflow_i   ;\n  wire                               axi_ar_overflow_i   ;\n  wire                               axi_r_overflow_i    ;\n  wire                               axi_rd_underflow_i  ;\n  wire                               axi_rd_overflow_i   ;\n  wire                               rach_s_axi_arready  ;\n  wire                               rach_m_axi_arvalid  ;\n  wire                               rach_wr_en          ;\n  wire                               rach_rd_en          ;\n  wire                               rdch_m_axi_rready   ;\n  wire                               rdch_s_axi_rvalid   ;\n  wire                               rdch_wr_en          ;\n  wire                               rdch_rd_en          ;\n  wire                               arvalid_pkt         ;\n  wire                               arready_pkt         ;\n  wire                               arvalid_en          ;\n  wire                               rdch_rd_ok          ;\n  wire                               accept_next_pkt     ;\n  integer                            rdch_free_space     ;\n  integer                            rdch_commited_space ;\n  wire                               rach_we             ;\n  wire                               rach_re             ;\n  wire                               rdch_we             ;\n  wire                               rdch_re             ;\n\n  localparam ARID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;\n  localparam ARADDR_OFFSET     = ARID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam ARLEN_OFFSET      = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;\n  localparam ARSIZE_OFFSET     = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;\n  localparam ARBURST_OFFSET    = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;\n  localparam ARLOCK_OFFSET     = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;\n  localparam ARCACHE_OFFSET    = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;\n  localparam ARPROT_OFFSET     = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam ARQOS_OFFSET      = ARPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam ARREGION_OFFSET   = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;\n  localparam ARUSER_OFFSET     = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;\n\n  localparam RID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;\n  localparam RDATA_OFFSET      = RID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam RRESP_OFFSET      = RDATA_OFFSET - C_AXI_RRESP_WIDTH;\n  localparam RUSER_OFFSET      = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;\n\n\n  generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rach_we    = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;\n\n    // Read protection when almost empty or prog_empty is high\n//    assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;\n    assign rach_re    = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        rach_m_axi_arvalid & arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY && rach_m_axi_arvalid :\n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY : 1'b0;\n    assign rach_wr_en = (C_HAS_SLAVE_CE == 1)  ? rach_we & S_ACLK_EN : rach_we;\n    assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;\n\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 2  || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),\n        .C_USE_ECC                      (C_USE_ECC_RACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_rach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rach_wr_en),\n        .RD_EN                    (rach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AR_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AR_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AR_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AR_INJECTSBITERR),\n  \n        .DIN                      (rach_din),\n        .DOUT                     (rach_dout_pkt),\n        .FULL                     (rach_full),\n        .EMPTY                    (rach_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_AR_PROG_FULL),\n        .PROG_EMPTY               (AXI_AR_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_ar_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_ar_underflow_i),\n        .DATA_COUNT               (AXI_AR_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AR_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AR_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AR_SBITERR),\n        .DBITERR                  (AXI_AR_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rach),\n        .rd_rst_busy              (rd_rst_busy_rach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rach_s_axi_arready    = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;\n    assign rach_m_axi_arvalid = ~rach_empty;\n    assign S_AXI_ARREADY      = rach_s_axi_arready;\n\n    assign AXI_AR_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;\n    assign AXI_AR_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_ar_overflow_i  : 0;\n\n  end endgenerate // axi_read_addr_channel\n\n  // Register Slice for Read Address Channel\n  generate if (C_RACH_TYPE == 1) begin : grach_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RACH)\n            )\n    rach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_din),\n          .S_VALID                   (S_AXI_ARVALID),\n          .S_READY                   (S_AXI_ARREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice\n\n  // Register Slice for Read Address Channel for MM Packet FIFO\n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (1)\n            )\n    reg_slice_mm_pkt_fifo_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_dout_pkt),\n          .S_VALID                   (arvalid_pkt),\n          .S_READY                   (arready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice_mm_pkt_fifo\n\n  \n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid\n    assign M_AXI_ARVALID      = rach_m_axi_arvalid;\n    assign rach_dout          = rach_dout_pkt;\n  end endgenerate // grach_m_axi_arvalid\n  \n  \n  generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd\n    assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;\n    assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;\n    assign accept_next_pkt  = rach_m_axi_arvalid && arready_pkt && arvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset) begin\n\trdch_commited_space <= 0;\n      end else begin\n\tif(rdch_rd_ok && !accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space-1;\n\tend else if(!rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);\n\tend else if(rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);\n\tend\n      end\n    end //Always end\n\n    always@(*) begin\n      rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));\n    end\n\n    assign arvalid_en = (rdch_free_space >= 0)?1:0;\n  end\n  endgenerate\n  \n  generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd\n    assign arvalid_en = 1;    \n  end\n  endgenerate\n\n  generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rdch_we    = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready  & M_AXI_RVALID : M_AXI_RVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign rdch_re    = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid  & S_AXI_RREADY : S_AXI_RREADY;\n    assign rdch_wr_en = (C_HAS_MASTER_CE == 1)  ? rdch_we & M_ACLK_EN : rdch_we;\n    assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 2  || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),\n        .C_USE_ECC                      (C_USE_ECC_RDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_RDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_rdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rdch_wr_en),\n        .RD_EN                    (rdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_R_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_R_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_R_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_R_INJECTSBITERR),\n  \n        .DIN                      (rdch_din),\n        .DOUT                     (rdch_dout),\n        .FULL                     (rdch_full),\n        .EMPTY                    (rdch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_R_PROG_FULL),\n        .PROG_EMPTY               (AXI_R_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_r_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_r_underflow_i),\n        .DATA_COUNT               (AXI_R_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_R_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_R_WR_DATA_COUNT),\n        .SBITERR                  (AXI_R_SBITERR),\n        .DBITERR                  (AXI_R_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rdch),\n        .rd_rst_busy              (rd_rst_busy_rdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rdch_s_axi_rvalid = ~rdch_empty;\n    assign rdch_m_axi_rready     = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;\n    assign S_AXI_RVALID      = rdch_s_axi_rvalid;\n    assign M_AXI_RREADY      = rdch_m_axi_rready;\n\n    assign AXI_R_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i  : 0;\n    assign AXI_R_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_r_overflow_i   : 0;\n\n  end endgenerate //axi_read_data_channel\n\n  // Register Slice for read Data Channel\n  generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RDCH)\n            )\n    rdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rdch_din),\n          .S_VALID                   (M_AXI_RVALID),\n          .S_READY                   (M_AXI_RREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rdch_dout),\n          .M_VALID                   (S_AXI_RVALID),\n          .M_READY                   (S_AXI_RREADY)\n          );\n  end endgenerate // grdch_reg_slice\n\n\n    assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;\n    assign axi_rd_overflow_i  = C_USE_COMMON_OVERFLOW  == 1 ? (axi_ar_overflow_i  || axi_r_overflow_i) : 0;\n\n\n  generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output\n    assign M_AXI_ARADDR    = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];    \n    assign M_AXI_ARLEN     = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];    \n    assign M_AXI_ARSIZE    = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];    \n    assign M_AXI_ARBURST   = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];    \n    assign M_AXI_ARLOCK    = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];    \n    assign M_AXI_ARCACHE   = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];    \n    assign M_AXI_ARPROT    = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];    \n    assign M_AXI_ARQOS     = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];    \n    assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET]    = S_AXI_ARADDR;\n    assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET]   = S_AXI_ARLEN;\n    assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET]   = S_AXI_ARSIZE;\n    assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;\n    assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;\n    assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;\n    assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;\n    assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET]   = S_AXI_ARQOS;\n  end endgenerate // axi_full_rach_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion\n    assign M_AXI_ARREGION  = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];    \n  end endgenerate // axi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion\n    assign M_AXI_ARREGION  = 0;    \n  end endgenerate // naxi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser\n    assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];    \n  end endgenerate // axi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser\n    assign M_AXI_ARUSER = 0;    \n  end endgenerate // naxi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid\n    assign M_AXI_ARID      = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];\n  end endgenerate // axi_arid\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid\n    assign M_AXI_ARID      = 0;\n  end endgenerate // naxi_arid\n\n  generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output\n    assign S_AXI_RDATA     = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];\n    assign S_AXI_RRESP     = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n    assign S_AXI_RLAST     = rdch_dout[0];\n    assign rdch_din[RID_OFFSET-1:RDATA_OFFSET]   = M_AXI_RDATA;\n    assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;\n    assign rdch_din[0] = M_AXI_RLAST;\n  end endgenerate // axi_full_rdch_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output\n    assign S_AXI_RUSER     = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];\n  end endgenerate // axi_full_ruser_output\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output\n    assign S_AXI_RUSER     =  0;\n  end endgenerate // axi_full_nruser_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid\n    assign S_AXI_RID       = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];\n  end endgenerate // axi_rid\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid\n    assign S_AXI_RID       = 0;\n  end endgenerate // naxi_rid\n\n  generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1\n    assign rach_din      = {S_AXI_ARADDR, S_AXI_ARPROT};\n    assign M_AXI_ARADDR  = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];\n    assign M_AXI_ARPROT  = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];\n  end endgenerate // axi_lite_rach_output\n\n  generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1\n    assign rdch_din      = {M_AXI_RDATA, M_AXI_RRESP};\n    assign S_AXI_RDATA   = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];\n    assign S_AXI_RRESP   = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n  end endgenerate // axi_lite_rdch_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1\n    assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET]     = S_AXI_ARUSER;\n  end endgenerate // grach_din1\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2\n    assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET]     = S_AXI_ARID;\n  end endgenerate // grach_din2\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin\n    assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1\n    assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET]     = M_AXI_RUSER;\n  end endgenerate // grdch_din1\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2\n    assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;\n  end endgenerate // grdch_din2\n\n  //end of axi_read_channel\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf\n    assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :\n                       (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :\n                       (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;\n  end endgenerate // gaxi_comm_uf\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of\n    assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :\n                      (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :\n                      (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;\n  end endgenerate // gaxi_comm_of\n  \n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  // Pass Through Logic or Wiring Logic\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  \n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Write Address Channel\n  generate if (C_WACH_TYPE == 2) begin : gwach_pass_through\n    assign M_AXI_AWID      = S_AXI_AWID;\n    assign M_AXI_AWADDR    = S_AXI_AWADDR;\n    assign M_AXI_AWLEN     = S_AXI_AWLEN;\n    assign M_AXI_AWSIZE    = S_AXI_AWSIZE;\n    assign M_AXI_AWBURST   = S_AXI_AWBURST;\n    assign M_AXI_AWLOCK    = S_AXI_AWLOCK;\n    assign M_AXI_AWCACHE   = S_AXI_AWCACHE;\n    assign M_AXI_AWPROT    = S_AXI_AWPROT;\n    assign M_AXI_AWQOS     = S_AXI_AWQOS;\n    assign M_AXI_AWREGION  = S_AXI_AWREGION;\n    assign M_AXI_AWUSER    = S_AXI_AWUSER;\n    assign S_AXI_AWREADY   = M_AXI_AWREADY;\n    assign M_AXI_AWVALID   = S_AXI_AWVALID;\n  end endgenerate // gwach_pass_through;\n\n  // Wiring logic for Write Data Channel\n  generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through\n    assign M_AXI_WID       = S_AXI_WID;\n    assign M_AXI_WDATA     = S_AXI_WDATA;\n    assign M_AXI_WSTRB     = S_AXI_WSTRB;\n    assign M_AXI_WLAST     = S_AXI_WLAST;\n    assign M_AXI_WUSER     = S_AXI_WUSER;\n    assign S_AXI_WREADY    = M_AXI_WREADY;\n    assign M_AXI_WVALID    = S_AXI_WVALID;\n  end endgenerate // gwdch_pass_through;\n\n  // Wiring logic for Write Response Channel\n  generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through\n    assign S_AXI_BID       = M_AXI_BID;\n    assign S_AXI_BRESP     = M_AXI_BRESP;\n    assign S_AXI_BUSER     = M_AXI_BUSER;\n    assign M_AXI_BREADY    = S_AXI_BREADY;\n    assign S_AXI_BVALID    = M_AXI_BVALID;\n  end endgenerate // gwrch_pass_through;\n\n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Read Address Channel\n  generate if (C_RACH_TYPE == 2) begin : grach_pass_through\n    assign M_AXI_ARID      = S_AXI_ARID;\n    assign M_AXI_ARADDR    = S_AXI_ARADDR;\n    assign M_AXI_ARLEN     = S_AXI_ARLEN;\n    assign M_AXI_ARSIZE    = S_AXI_ARSIZE;\n    assign M_AXI_ARBURST   = S_AXI_ARBURST;\n    assign M_AXI_ARLOCK    = S_AXI_ARLOCK;\n    assign M_AXI_ARCACHE   = S_AXI_ARCACHE;\n    assign M_AXI_ARPROT    = S_AXI_ARPROT;\n    assign M_AXI_ARQOS     = S_AXI_ARQOS;\n    assign M_AXI_ARREGION  = S_AXI_ARREGION;\n    assign M_AXI_ARUSER    = S_AXI_ARUSER;\n    assign S_AXI_ARREADY   = M_AXI_ARREADY;\n    assign M_AXI_ARVALID   = S_AXI_ARVALID;\n  end endgenerate // grach_pass_through;\n\n  // Wiring logic for Read Data Channel \n  generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through\n    assign S_AXI_RID      = M_AXI_RID;\n    assign S_AXI_RLAST    = M_AXI_RLAST;\n    assign S_AXI_RUSER    = M_AXI_RUSER;\n    assign S_AXI_RDATA    = M_AXI_RDATA;\n    assign S_AXI_RRESP    = M_AXI_RRESP;\n    assign S_AXI_RVALID   = M_AXI_RVALID;\n    assign M_AXI_RREADY   = S_AXI_RREADY;\n  end endgenerate // grdch_pass_through;\n\n  // Wiring logic for AXI Streaming\n  generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through\n    assign M_AXIS_TDATA   = S_AXIS_TDATA;\n    assign M_AXIS_TSTRB   = S_AXIS_TSTRB;\n    assign M_AXIS_TKEEP   = S_AXIS_TKEEP;\n    assign M_AXIS_TID     = S_AXIS_TID;\n    assign M_AXIS_TDEST   = S_AXIS_TDEST;\n    assign M_AXIS_TUSER   = S_AXIS_TUSER;\n    assign M_AXIS_TLAST   = S_AXIS_TLAST;\n    assign S_AXIS_TREADY  = M_AXIS_TREADY;\n    assign M_AXIS_TVALID  = S_AXIS_TVALID;\n  end endgenerate // gaxis_pass_through;\n\n\nendmodule //fifo_generator_v13_2_1\n\n\n\n/*******************************************************************************\n * Declaration of top-level module for Conventional FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_1_CONV_VER\n  #(\n    parameter  C_COMMON_CLOCK                 = 0,\n    parameter  C_INTERFACE_TYPE               = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_COUNT_TYPE                   = 0,\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DEFAULT_VALUE                = \"\",\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_ENABLE_RLOCS                 = 0,\n    parameter  C_FAMILY                       = \"virtex7\", //Not allowed in Verilog model\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_BACKUP                   = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_INT_CLK                  = 0,\n    parameter  C_HAS_MEMINIT_FILE             = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RD_RST                   = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_RST                   = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_INIT_WR_PNTR_VAL             = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_MIF_FILE_NAME                = \"\",\n    parameter  C_OPTIMIZATION_MODE            = 0,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PRIM_FIFO_TYPE               = \"\",\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_FREQ                      = 1,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_ECC                      = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_USE_FIFO16_FLAGS             = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_FREQ                      = 1,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_WR_RESPONSE_LATENCY          = 1,\n    parameter  C_MSGON_VAL                    = 1,\n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2,\n    parameter  C_AXI_TYPE                     = 0\n   )\n\n  (\n   input                               BACKUP,\n   input                               BACKUP_MARKER,\n   input                               CLK,\n   input                               RST,\n   input                               SRST,\n   input                               WR_CLK,\n   input                               WR_RST,\n   input                               RD_CLK,\n   input                               RD_RST,\n   input [C_DIN_WIDTH-1:0]             DIN,\n   input                               WR_EN,\n   input                               RD_EN,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_ASSERT,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_NEGATE,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_ASSERT,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_NEGATE,\n   input                               INT_CLK,\n   input                               INJECTDBITERR,\n   input                               INJECTSBITERR,\n  \n   output [C_DOUT_WIDTH-1:0]           DOUT,\n   output                              FULL,\n   output                              ALMOST_FULL,\n   output                              WR_ACK,\n   output                              OVERFLOW,\n   output                              EMPTY,\n   output                              ALMOST_EMPTY,\n   output                              VALID,\n   output                              UNDERFLOW,\n   output [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT,\n   output [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT,\n   output [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT,\n   output                              PROG_FULL,\n   output                              PROG_EMPTY,\n   output                              SBITERR,\n   output                              DBITERR,\n   output                              wr_rst_busy_o,\n   output                              wr_rst_busy,\n   output                              rd_rst_busy,\n   output                              wr_rst_i_out,\n   output                              rd_rst_i_out\n  );\n\n/*\n ******************************************************************************\n * Definition of Parameters\n ******************************************************************************\n *     C_COMMON_CLOCK                : Common Clock (1), Independent Clocks (0)\n *     C_COUNT_TYPE                  :    *not used\n *     C_DATA_COUNT_WIDTH            : Width of DATA_COUNT bus\n *     C_DEFAULT_VALUE               :    *not used\n *     C_DIN_WIDTH                   : Width of DIN bus\n *     C_DOUT_RST_VAL                : Reset value of DOUT\n *     C_DOUT_WIDTH                  : Width of DOUT bus\n *     C_ENABLE_RLOCS                :    *not used\n *     C_FAMILY                      : not used in bhv model\n *     C_FULL_FLAGS_RST_VAL          : Full flags rst val (0 or 1)\n *     C_HAS_ALMOST_EMPTY            : 1=Core has ALMOST_EMPTY flag\n *     C_HAS_ALMOST_FULL             : 1=Core has ALMOST_FULL flag\n *     C_HAS_BACKUP                  :    *not used\n *     C_HAS_DATA_COUNT              : 1=Core has DATA_COUNT bus\n *     C_HAS_INT_CLK                 : not used in bhv model\n *     C_HAS_MEMINIT_FILE            :    *not used\n *     C_HAS_OVERFLOW                : 1=Core has OVERFLOW flag\n *     C_HAS_RD_DATA_COUNT           : 1=Core has RD_DATA_COUNT bus\n *     C_HAS_RD_RST                  :    *not used\n *     C_HAS_RST                     : 1=Core has Async Rst\n *     C_HAS_SRST                    : 1=Core has Sync Rst\n *     C_HAS_UNDERFLOW               : 1=Core has UNDERFLOW flag\n *     C_HAS_VALID                   : 1=Core has VALID flag\n *     C_HAS_WR_ACK                  : 1=Core has WR_ACK flag\n *     C_HAS_WR_DATA_COUNT           : 1=Core has WR_DATA_COUNT bus\n *     C_HAS_WR_RST                  :    *not used\n *     C_IMPLEMENTATION_TYPE         : 0=Common-Clock Bram/Dram\n *                                     1=Common-Clock ShiftRam\n *                                     2=Indep. Clocks Bram/Dram\n *                                     3=Virtex-4 Built-in\n *                                     4=Virtex-5 Built-in\n *     C_INIT_WR_PNTR_VAL            :   *not used\n *     C_MEMORY_TYPE                 : 1=Block RAM\n *                                     2=Distributed RAM\n *                                     3=Shift RAM\n *                                     4=Built-in FIFO\n *     C_MIF_FILE_NAME               :   *not used\n *     C_OPTIMIZATION_MODE           :   *not used\n *     C_OVERFLOW_LOW                : 1=OVERFLOW active low\n *     C_PRELOAD_LATENCY             : Latency of read: 0, 1, 2\n *     C_PRELOAD_REGS                : 1=Use output registers\n *     C_PRIM_FIFO_TYPE              : not used in bhv model\n *     C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold\n *     C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold\n *     C_PROG_EMPTY_TYPE             : 0=No programmable empty\n *                                     1=Single prog empty thresh constant\n *                                     2=Multiple prog empty thresh constants\n *                                     3=Single prog empty thresh input\n *                                     4=Multiple prog empty thresh inputs\n *     C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold\n *     C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold\n *     C_PROG_FULL_TYPE              : 0=No prog full\n *                                     1=Single prog full thresh constant\n *                                     2=Multiple prog full thresh constants\n *                                     3=Single prog full thresh input\n *                                     4=Multiple prog full thresh inputs\n *     C_RD_DATA_COUNT_WIDTH         : Width of RD_DATA_COUNT bus\n *     C_RD_DEPTH                    : Depth of read interface (2^N)\n *     C_RD_FREQ                     : not used in bhv model\n *     C_RD_PNTR_WIDTH               : always log2(C_RD_DEPTH)\n *     C_UNDERFLOW_LOW               : 1=UNDERFLOW active low\n *     C_USE_DOUT_RST                : 1=Resets DOUT on RST\n *     C_USE_ECC                     : Used for error injection purpose\n *     C_USE_EMBEDDED_REG            : 1=Use BRAM embedded output register\n *     C_USE_FIFO16_FLAGS            : not used in bhv model\n *     C_USE_FWFT_DATA_COUNT         : 1=Use extra logic for FWFT data count\n *     C_VALID_LOW                   : 1=VALID active low\n *     C_WR_ACK_LOW                  : 1=WR_ACK active low\n *     C_WR_DATA_COUNT_WIDTH         : Width of WR_DATA_COUNT bus\n *     C_WR_DEPTH                    : Depth of write interface (2^N)\n *     C_WR_FREQ                     : not used in bhv model\n *     C_WR_PNTR_WIDTH               : always log2(C_WR_DEPTH)\n *     C_WR_RESPONSE_LATENCY         :    *not used\n *     C_MSGON_VAL                   :    *not used by bhv model\n *     C_ENABLE_RST_SYNC             : 0 = Use WR_RST & RD_RST\n *                                     1 = Use RST\n *     C_ERROR_INJECTION_TYPE        : 0 = No error injection\n *                                     1 = Single bit error injection only\n *                                     2 = Double bit error injection only\n *                                     3 = Single and double bit error injection\n ******************************************************************************\n * Definition of Ports\n ******************************************************************************\n *   BACKUP       : Not used\n *   BACKUP_MARKER: Not used\n *   CLK          : Clock\n *   DIN          : Input data bus\n *   PROG_EMPTY_THRESH       : Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag\n *   PROG_FULL_THRESH        : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag\n *   RD_CLK       : Read Domain Clock\n *   RD_EN        : Read enable\n *   RD_RST       : Read Reset\n *   RST          : Asynchronous Reset\n *   SRST         : Synchronous Reset\n *   WR_CLK       : Write Domain Clock\n *   WR_EN        : Write enable\n *   WR_RST       : Write Reset\n *   INT_CLK      : Internal Clock\n *   INJECTSBITERR: Inject Signle bit error\n *   INJECTDBITERR: Inject Double bit error\n *   ALMOST_EMPTY : One word remaining in FIFO\n *   ALMOST_FULL  : One empty space remaining in FIFO\n *   DATA_COUNT   : Number of data words in fifo( synchronous to CLK)\n *   DOUT         : Output data bus\n *   EMPTY        : Empty flag\n *   FULL         : Full flag\n *   OVERFLOW     : Last write rejected\n *   PROG_EMPTY   : Programmable Empty Flag\n *   PROG_FULL    : Programmable Full Flag\n *   RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)\n *   UNDERFLOW    : Last read rejected\n *   VALID        : Last read acknowledged, DOUT bus VALID\n *   WR_ACK       : Last write acknowledged\n *   WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)\n *   SBITERR      : Single Bit ECC Error Detected\n *   DBITERR      : Double Bit ECC Error Detected\n ******************************************************************************\n */\n\n  //----------------------------------------------------------------------------\n  //- Internal Signals for delayed input signals\n  //- All the input signals except Clock are delayed by 100 ps and then given to\n  //- the models.\n  //----------------------------------------------------------------------------\n \n  reg                         rst_delayed                       ;\n  reg                         empty_fb                       ;\n  reg                         srst_delayed                      ;\n  reg                         wr_rst_delayed                    ;\n  reg                         rd_rst_delayed                    ;\n  reg                         wr_en_delayed                     ;\n  reg                         rd_en_delayed                     ;\n  reg  [C_DIN_WIDTH-1:0]      din_delayed                       ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_delayed         ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_assert_delayed  ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_negate_delayed  ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_delayed          ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_assert_delayed   ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_negate_delayed   ;\n  reg                         injectdbiterr_delayed             ;\n  reg                         injectsbiterr_delayed             ;\n   wire                        empty_p0_out;\n\n  always @* rst_delayed                       <= #`TCQ RST                      ;\n  always @* empty_fb                       <= #`TCQ empty_p0_out                      ;\n  always @* srst_delayed                      <= #`TCQ SRST                     ; \n  always @* wr_rst_delayed                    <= #`TCQ WR_RST                   ; \n  always @* rd_rst_delayed                    <= #`TCQ RD_RST                   ; \n  always @* din_delayed                       <= #`TCQ DIN                      ; \n  always @* wr_en_delayed                     <= #`TCQ WR_EN                    ; \n  always @* rd_en_delayed                     <= #`TCQ RD_EN                    ; \n  always @* prog_empty_thresh_delayed         <= #`TCQ PROG_EMPTY_THRESH        ; \n  always @* prog_empty_thresh_assert_delayed  <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; \n  always @* prog_empty_thresh_negate_delayed  <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; \n  always @* prog_full_thresh_delayed          <= #`TCQ PROG_FULL_THRESH         ; \n  always @* prog_full_thresh_assert_delayed   <= #`TCQ PROG_FULL_THRESH_ASSERT  ; \n  always @* prog_full_thresh_negate_delayed   <= #`TCQ PROG_FULL_THRESH_NEGATE  ; \n  always @* injectdbiterr_delayed             <= #`TCQ INJECTDBITERR            ; \n  always @* injectsbiterr_delayed             <= #`TCQ INJECTSBITERR            ; \n\n  /*****************************************************************************\n   * Derived parameters\n   ****************************************************************************/\n  //There are 2 Verilog behavioral models\n  // 0 = Common-Clock FIFO/ShiftRam FIFO\n  // 1 = Independent Clocks FIFO\n  // 2 = Low Latency Synchronous FIFO\n  // 3 = Low Latency Asynchronous FIFO\n  localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :\n                              (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n\n  //Internal reset signals\n  reg                                rd_rst_asreg    = 1'b0;\n  reg                                rd_rst_asreg_d1 = 1'b0;\n  reg                                rd_rst_asreg_d2 = 1'b0;\n  reg                                rd_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_reg      = 1'b0;\n  reg                                rd_rst_comb     = 1'b1;\n  reg                                rd_rst_comb_d1  = 1'b0;\n  reg                                wr_rst_d0       = 1'b0;\n  reg                                wr_rst_d1       = 1'b0;\n  reg                                wr_rst_d2       = 1'b0;\n  reg                                rd_rst_d0       = 1'b0;\n  reg                                rd_rst_d1       = 1'b0;\n  reg                                rd_rst_d2       = 1'b0;\n  reg                                rd_rst_d3       = 1'b0;\n  reg                                wrrst_done      = 1'b0;\n  reg                                rdrst_done      = 1'b0;\n  reg                                wr_rst_asreg    = 1'b0;\n  reg                                wr_rst_asreg_d1 = 1'b0;\n  reg                                wr_rst_asreg_d2 = 1'b0;\n  reg                                wr_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_wr_d0    = 1'b0;\n  reg                                rd_rst_wr_d1    = 1'b0;\n  reg                                rd_rst_wr_d2    = 1'b0;\n  reg                                wr_rst_reg      = 1'b0;\n  reg                                rst_active_i    = 1'b1;\n  reg                                rst_delayed_d1  = 1'b1;\n  reg                                rst_delayed_d2  = 1'b1;\n  reg                                wr_rst_comb     = 1'b1;\n  reg                                wr_rst_comb_d1  = 1'b0;\n  wire                               wr_rst_i;\n  wire                               rd_rst_i;\n  wire                               rst_i;\n\n  //Internal reset signals\n  reg                                rst_asreg     = 1'b0;\n  reg                                srst_asreg    = 1'b0;\n  reg                                rst_asreg_d1  = 1'b0;\n  reg                                rst_asreg_d2  = 1'b0;\n  reg                                srst_asreg_d1 = 1'b0;\n  reg                                srst_asreg_d2 = 1'b0;\n  reg                                rst_reg       = 1'b0;\n  reg                                srst_reg      = 1'b0;\n  reg                                rst_comb      = 1'b1;\n  reg                                rst_comb_d1   = 1'b0;\n  wire                               srst_comb;\n  reg                                rst_full_gen_i = 0;\n  reg                                rst_full_ff_i = 0;\n  reg  [2:0]                         sckt_ff0_bsy_o_i = {3{1'b0}};\n                                     \n  wire                               RD_CLK_P0_IN;\n  wire                               RST_P0_IN;\n  wire                               RD_EN_FIFO_IN;\n  wire                               RD_EN_P0_IN;\n\n  wire                               ALMOST_EMPTY_FIFO_OUT;\n  wire                               ALMOST_FULL_FIFO_OUT;\n  wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT_FIFO_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DOUT_FIFO_OUT;\n  wire                               EMPTY_FIFO_OUT;\n  wire                               fifo_empty_fb;\n  wire                               FULL_FIFO_OUT;\n  wire                               OVERFLOW_FIFO_OUT;\n  wire                               PROG_EMPTY_FIFO_OUT;\n  wire                               PROG_FULL_FIFO_OUT;\n  wire                               VALID_FIFO_OUT;\n  wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT_FIFO_OUT;\n  wire                               UNDERFLOW_FIFO_OUT;\n  wire                               WR_ACK_FIFO_OUT;\n  wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT_FIFO_OUT;\n\n\n  //***************************************************************************\n  // Internal Signals\n  //   The core uses either the internal_ wires or the preload0_ wires depending\n  //     on whether the core uses Preload0 or not.\n  //   When using preload0, the internal signals connect the internal core to\n  //     the preload logic, and the external core's interfaces are tied to the\n  //     preload0 signals from the preload logic.\n  //***************************************************************************\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_OUT;\n  wire                               VALID_P0_OUT;\n  wire                               EMPTY_P0_OUT;\n  wire                               ALMOSTEMPTY_P0_OUT;\n  reg                                EMPTY_P0_OUT_Q;\n  reg                                ALMOSTEMPTY_P0_OUT_Q;\n  wire                               UNDERFLOW_P0_OUT;\n  wire                               RDEN_P0_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_IN;\n  wire                               EMPTY_P0_IN;\n  reg  [31:0]                        DATA_COUNT_FWFT;\n  reg                                SS_FWFT_WR  ;\n  reg                                SS_FWFT_RD ;\n\n  wire                               sbiterr_fifo_out;\n  wire                               dbiterr_fifo_out;\n  wire                               inject_sbit_err;\n  wire                               inject_dbit_err;\n  wire                               sckt_wr_rst_i;\n  wire                               sckt_rd_rst_i;\n  reg                                sckt_wr_rst_i_q = 1'b0;\n \n  wire                               w_fab_read_data_valid_i;\n  wire                               w_read_data_valid_i;\n  wire                               w_ram_valid_i;\n  // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.\n  assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectsbiterr_delayed : 0;\n  assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectdbiterr_delayed : 0;\n                           \n  assign wr_rst_i_out = wr_rst_i;\n  assign rd_rst_i_out = rd_rst_i;\n  assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];\n  generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o\n    wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;\n    always @ (posedge clk_i)\n      sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; \n  end endgenerate \n// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL\n// parameter (1=Independent Clocks, 0=Common Clock)\n\n  localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;\ngenerate\ncase (C_VERILOG_IMPL)\n0 : begin : block1_ss\n  //Common Clock Behavioral Model\n  fifo_generator_v13_2_1_bhv_ver_ss\n  #(\n    .C_FAMILY                            (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                  (C_DATA_COUNT_WIDTH),            \n    .C_DIN_WIDTH                         (C_DIN_WIDTH),                   \n    .C_DOUT_RST_VAL                      (C_DOUT_RST_VAL),                \n    .C_DOUT_WIDTH                        (C_DOUT_WIDTH),                  \n    .C_FULL_FLAGS_RST_VAL                (FULL_FLAGS_RST_VAL),            \n    .C_HAS_ALMOST_EMPTY                  (C_HAS_ALMOST_EMPTY),            \n    .C_HAS_ALMOST_FULL                   ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),             \n    .C_HAS_DATA_COUNT                    (C_HAS_DATA_COUNT),              \n    .C_HAS_OVERFLOW                      (C_HAS_OVERFLOW),                \n    .C_HAS_RD_DATA_COUNT                 (C_HAS_RD_DATA_COUNT),           \n    .C_HAS_RST                           (C_EN_SAFETY_CKT?0:C_HAS_RST),                     \n    .C_HAS_SRST                          (C_EN_SAFETY_CKT?1:C_HAS_SRST),                    \n    .C_HAS_UNDERFLOW                     (C_HAS_UNDERFLOW),               \n    .C_HAS_VALID                         (C_HAS_VALID),                   \n    .C_HAS_WR_ACK                        (C_HAS_WR_ACK),                  \n    .C_HAS_WR_DATA_COUNT                 (C_HAS_WR_DATA_COUNT),           \n    .C_IMPLEMENTATION_TYPE               (C_IMPLEMENTATION_TYPE),         \n    .C_MEMORY_TYPE                       (C_MEMORY_TYPE),                 \n    .C_OVERFLOW_LOW                      (C_OVERFLOW_LOW),                \n    .C_PRELOAD_LATENCY                   (C_PRELOAD_LATENCY),             \n    .C_PRELOAD_REGS                      (C_PRELOAD_REGS),                \n    .C_PROG_EMPTY_THRESH_ASSERT_VAL      (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL      (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                   (C_PROG_EMPTY_TYPE),             \n    .C_PROG_FULL_THRESH_ASSERT_VAL       (C_PROG_FULL_THRESH_ASSERT_VAL), \n    .C_PROG_FULL_THRESH_NEGATE_VAL       (C_PROG_FULL_THRESH_NEGATE_VAL), \n    .C_PROG_FULL_TYPE                    (C_PROG_FULL_TYPE),              \n    .C_RD_DATA_COUNT_WIDTH               (C_RD_DATA_COUNT_WIDTH),         \n    .C_RD_DEPTH                          (C_RD_DEPTH),                    \n    .C_RD_PNTR_WIDTH                     (C_RD_PNTR_WIDTH),               \n    .C_UNDERFLOW_LOW                     (C_UNDERFLOW_LOW),               \n    .C_USE_DOUT_RST                      (C_USE_DOUT_RST),                \n    .C_USE_EMBEDDED_REG                  (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                     (C_EN_SAFETY_CKT),            \n    .C_USE_FWFT_DATA_COUNT               (C_USE_FWFT_DATA_COUNT),         \n    .C_VALID_LOW                         (C_VALID_LOW),                   \n    .C_WR_ACK_LOW                        (C_WR_ACK_LOW),                  \n    .C_WR_DATA_COUNT_WIDTH               (C_WR_DATA_COUNT_WIDTH),         \n    .C_WR_DEPTH                          (C_WR_DEPTH),                    \n    .C_WR_PNTR_WIDTH                     (C_WR_PNTR_WIDTH),               \n    .C_USE_ECC                           (C_USE_ECC),                     \n    .C_ENABLE_RST_SYNC                   (C_ENABLE_RST_SYNC),             \n    .C_ERROR_INJECTION_TYPE              (C_ERROR_INJECTION_TYPE),\n    .C_FIFO_TYPE                         (C_FIFO_TYPE)                     \n  )\n  gen_ss\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .CLK                      (CLK),\n    .RST                      (C_EN_SAFETY_CKT?1'b0:rst_i),\n    .SRST                     (C_EN_SAFETY_CKT?sckt_wr_rst_i:srst_delayed),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .USER_EMPTY_FB            (empty_fb),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .DATA_COUNT               (DATA_COUNT_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .WR_RST_BUSY              (wr_rst_busy),\n    .RD_RST_BUSY              (rd_rst_busy),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n1 : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_1_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT), \n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .fab_read_data_valid_i    (w_fab_read_data_valid_i),\n    .read_data_valid_i        (w_read_data_valid_i),\n    .ram_valid_i              (w_ram_valid_i),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\n2 : begin : ll_afifo_inst\n  fifo_generator_v13_2_1_beh_ver_ll_afifo\n  #(\n    .C_DIN_WIDTH                    (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                 (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                   (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_RD_DATA_COUNT            (C_HAS_RD_DATA_COUNT),\n    .C_HAS_WR_DATA_COUNT            (C_HAS_WR_DATA_COUNT),\n    .C_RD_DEPTH                     (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                (C_RD_PNTR_WIDTH),\n    .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n    .C_WR_DATA_COUNT_WIDTH          (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                     (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                (C_WR_PNTR_WIDTH),\n    .C_FIFO_TYPE                    (C_FIFO_TYPE)\n   )\n  gen_ll_afifo\n  (\n    .DIN                        (din_delayed),\n    .RD_CLK                     (RD_CLK),\n    .RD_EN                      (rd_en_delayed),\n    .WR_RST                     (wr_rst_i),\n    .RD_RST                     (rd_rst_i),\n    .WR_CLK                     (WR_CLK),\n    .WR_EN                      (wr_en_delayed),\n    .DOUT                       (DOUT),\n    .EMPTY                      (EMPTY),\n    .FULL                       (FULL)\n  );\nend\ndefault : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_1_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT),\n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\nendcase\nendgenerate\n\n\n   //**************************************************************************\n   // Connect Internal Signals\n   //   (Signals labeled internal_*)\n   //  In the normal case, these signals tie directly to the FIFO's inputs and\n   //    outputs.\n   //  In the case of Preload Latency 0 or 1, there are intermediate\n   //    signals between the internal FIFO and the preload logic.\n   //**************************************************************************\n   \n   \n   //***********************************************\n   // If First-Word Fall-Through, instantiate\n   // the preload0 (FWFT) module\n   //***********************************************\n   wire                        rd_en_to_fwft_fifo;\n   wire                        sbiterr_fwft;\n   wire                        dbiterr_fwft;\n   wire [C_DOUT_WIDTH-1:0]     dout_fwft;\n   wire                        empty_fwft;\n   wire                        rd_en_fifo_in;\n   wire                        stage2_reg_en_i;\n   wire [1:0]                  valid_stages_i;\n   wire                        rst_fwft;\n   //wire                        empty_p0_out;\n   reg  [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n   localparam IS_PKT_FIFO      = (C_FIFO_TYPE == 1) ? 1 : 0;\n   localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;\n   assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2_fwft\n\n\n         fifo_generator_v13_2_1_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_EMBEDDED_REG  (C_USE_EMBEDDED_REG),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (C_FIFO_TYPE)\n             )\n             fgpl0\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (RST_P0_IN),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (RD_EN_P0_IN),\n                .FIFOEMPTY        (EMPTY_P0_IN),\n                .FIFODATA         (DATA_P0_IN),\n                .FIFOSBITERR      (sbiterr_fifo_out),\n                .FIFODBITERR      (dbiterr_fifo_out),\n                // Output\n                .USERDATA         (dout_fwft),\n                .USERVALID        (VALID_P0_OUT),\n                .USEREMPTY        (empty_fwft),\n                .USERALMOSTEMPTY  (ALMOSTEMPTY_P0_OUT),\n                .USERUNDERFLOW    (UNDERFLOW_P0_OUT),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_fifo_in),\n                .USERSBITERR      (sbiterr_fwft),\n                .USERDBITERR      (dbiterr_fwft),\n                .STAGE2_REG_EN    (stage2_reg_en_i),\n                .fab_read_data_valid_i_o    (w_fab_read_data_valid_i),\n                .read_data_valid_i_o        (w_read_data_valid_i),\n                .ram_valid_i_o              (w_ram_valid_i),\n                .VALID_STAGES                (valid_stages_i)\n                );\n\n         \n         //***********************************************\n         // Connect inputs to preload (FWFT) module\n         //***********************************************\n         //Connect the RD_CLK of the Preload (FWFT) module to CLK if we \n         // have a common-clock FIFO, or RD_CLK if we have an \n         // independent clock FIFO\n         assign RD_CLK_P0_IN       = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);\n         assign RST_P0_IN          = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;\n         assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n         assign EMPTY_P0_IN        = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;\n         assign DATA_P0_IN         = DOUT_FIFO_OUT;\n         \n         //***********************************************\n         // Connect outputs from preload (FWFT) module\n         //***********************************************\n         assign VALID              = VALID_P0_OUT ;\n         assign ALMOST_EMPTY       = ALMOSTEMPTY_P0_OUT;\n         assign UNDERFLOW          = UNDERFLOW_P0_OUT ;\n         \n         assign RD_EN_FIFO_IN      = rd_en_fifo_in;\n         \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:\n           (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : \n           DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];  \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               EMPTY_P0_OUT_Q       <= 1;\n               ALMOSTEMPTY_P0_OUT_Q <= 1;\n            end else begin\n               EMPTY_P0_OUT_Q       <= #`TCQ empty_p0_out;\n//               EMPTY_P0_OUT_Q       <= #`TCQ EMPTY_FIFO_OUT;\n               ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;\n            end\n         end //always\n         \n         \n         //***********************************************\n         // logic for common-clock data count when FWFT is selected\n         //***********************************************\n         initial begin\n            SS_FWFT_RD = 1'b0;\n            DATA_COUNT_FWFT = 0 ;\n            SS_FWFT_WR   = 1'b0 ;\n         end //initial\n         \n         \n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter. SS_FWFT_WR and SS_FWFT_RD\n         // are the up/down enables for the counter.\n         //***********************************************\n         always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin\n            if (C_VALID_LOW == 1) begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;\n            end else begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;\n            end\n            SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT))  ;\n         end \n\n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter for FWFT. This always block \n         // calculates the counter.\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               DATA_COUNT_FWFT      <= 0;\n            end else begin\n               //if (srst_delayed && (C_HAS_SRST == 1) ) begin\n               if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin\n                  DATA_COUNT_FWFT      <= #`TCQ 0;\n               end else begin\n                  case ( {SS_FWFT_WR, SS_FWFT_RD})\n                    2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                    2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;\n                    2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;\n                    2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                  endcase  \n               end //if SRST\n            end //IF RST\n         end //always\n\n      end endgenerate // : block2\n\n    // AXI Streaming Packet FIFO\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_plus1 = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_reg   = 0;\n    reg                         partial_packet     = 0;\n    reg                         stage1_eop_d1      = 0;\n    reg                         rd_en_fifo_in_d1   = 0;\n    reg                         eop_at_stage2      = 0;\n    reg                         ram_pkt_empty      = 0;\n    reg                         ram_pkt_empty_d1   = 0;\n\n    wire [C_DOUT_WIDTH-1:0]     dout_p0_out;\n    wire                        packet_empty_wr;\n    wire                        wr_rst_fwft_pkt_fifo;\n    wire                        dummy_wr_eop;\n    wire                        ram_wr_en_pkt_fifo;\n    wire                        wr_eop;\n    wire                        ram_rd_en_compare;\n    wire                        stage1_eop;\n    wire                        pkt_ready_to_read;\n    wire                        rd_en_2_stage2;\n\n    // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)\n    // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP\n    // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of\n    // write packet count\n    generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop\n       always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n          if (wr_rst_fwft_pkt_fifo)\n             partial_packet   <= 1'b0;\n          else begin\n             if (srst_delayed | wr_rst_busy | rd_rst_busy)\n                partial_packet <= #`TCQ 1'b0;\n             else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))\n                partial_packet <= #`TCQ 1'b1;\n             else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)\n                partial_packet <= #`TCQ 1'b0;\n          end\n        end\n    end endgenerate // gdummy_wr_eop\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin : gpkt_fifo_fwft\n      assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;\n      assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);\n      assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];\n  \n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft) begin\n          stage1_eop_d1    <= 1'b0;\n          rd_en_fifo_in_d1 <= 1'b0;\n        end else begin\n          if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            stage1_eop_d1    <= #`TCQ 1'b0;\n            rd_en_fifo_in_d1 <= #`TCQ 1'b0;\n          end else begin\n            stage1_eop_d1    <= #`TCQ stage1_eop;\n            rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;\n          end\n        end\n      end\n      assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;\n      assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);\n      assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);\n      assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;\n\n\n         fifo_generator_v13_2_1_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (2) // Enable low latency fwft logic\n             )\n         pkt_fifo_fwft\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (rst_fwft),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (rd_en_delayed),\n                .FIFOEMPTY        (pkt_ready_to_read),\n                .FIFODATA         (dout_fwft),\n                .FIFOSBITERR      (sbiterr_fwft),\n                .FIFODBITERR      (dbiterr_fwft),\n                // Output\n                .USERDATA         (dout_p0_out),\n                .USERVALID        (),\n                .USEREMPTY        (empty_p0_out),\n                .USERALMOSTEMPTY  (),\n                .USERUNDERFLOW    (),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_2_stage2),\n                .USERSBITERR      (SBITERR),\n                .USERDBITERR      (DBITERR),\n                .STAGE2_REG_EN    (),\n                .VALID_STAGES     ()\n                );\n\n      assign pkt_ready_to_read  = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));\n      assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft)\n          eop_at_stage2 <= 1'b0;\n        else if (stage2_reg_en_i)\n          eop_at_stage2 <= #`TCQ stage1_eop;\n      end\n\n      //---------------------------------------------------------------------------\n      // Write and Read Packet Count\n      //---------------------------------------------------------------------------\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count  <= 0;\n         else if (srst_delayed  | wr_rst_busy | rd_rst_busy)\n            wr_pkt_count  <= #`TCQ 0;\n         else if (wr_eop)\n            wr_pkt_count  <= #`TCQ wr_pkt_count + 1;\n      end\n    \n    end endgenerate //: gpkt_fifo_fwft\n\n    assign DOUT               = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;\n    assign EMPTY              = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            rd_pkt_count       <= 0;\n            rd_pkt_count_plus1 <= 1;\n         end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            rd_pkt_count       <= #`TCQ 0;\n            rd_pkt_count_plus1 <= #`TCQ 1;\n         end else if (stage2_reg_en_i && stage1_eop) begin\n            rd_pkt_count       <= #`TCQ rd_pkt_count + 1;\n            rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;\n         end\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (SRST | wr_rst_busy | rd_rst_busy) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n    end endgenerate //grss_pkt_cnt\n    \n    localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;\n    reg  [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_b2g = 0;\n    wire [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_rd;\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt\n      // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count_b2g  <= 0;\n         else\n            wr_pkt_count_b2g  <= #`TCQ wr_pkt_count;\n      end\n\n      // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            wr_pkt_count_q       <= 0;\n         else\n            wr_pkt_count_q       <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};\n      end\n\n      always @* begin\n        if (stage1_eop)\n           rd_pkt_count    <= rd_pkt_count_reg + 1;\n        else\n           rd_pkt_count    <= rd_pkt_count_reg;\n      end\n\n      assign wr_pkt_count_rd    = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            rd_pkt_count_reg       <= 0;\n         else if (rd_en_fifo_in)\n            rd_pkt_count_reg       <= #`TCQ rd_pkt_count;\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (rd_pkt_count != wr_pkt_count_rd) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n\n      // Synchronize the empty in write domain\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            pkt_empty_sync  <= 'b1;\n         else\n            pkt_empty_sync  <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};\n      end\n\n    end endgenerate //gras_pkt_cnt\n\n   generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO\n\n     //***********************************************\n     // If NOT First-Word Fall-Through, wire the outputs\n     // of the internal _ss or _as FIFO directly to the\n     // output, and do not instantiate the preload0\n     // module.\n     //***********************************************\n\n     assign RD_CLK_P0_IN       = 0;\n     assign RST_P0_IN          = 0;\n     assign RD_EN_P0_IN        = 0;\n\n     assign RD_EN_FIFO_IN      = rd_en_delayed;\n\n     assign DOUT               = DOUT_FIFO_OUT;\n     assign DATA_P0_IN         = 0;\n     assign VALID              = VALID_FIFO_OUT;\n     assign EMPTY              = EMPTY_FIFO_OUT;\n     assign ALMOST_EMPTY       = ALMOST_EMPTY_FIFO_OUT;\n     assign EMPTY_P0_IN        = 0;\n     assign UNDERFLOW          = UNDERFLOW_FIFO_OUT;\n     assign DATA_COUNT         = DATA_COUNT_FIFO_OUT;\n     assign SBITERR            = sbiterr_fifo_out;\n     assign DBITERR            = dbiterr_fifo_out;\n\n   end endgenerate // STD_FIFO\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO\n     assign empty_p0_out       = empty_fwft;\n     assign SBITERR            = sbiterr_fwft;\n     assign DBITERR            = dbiterr_fwft;\n     assign DOUT               = dout_fwft;\n     assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n\n   end endgenerate // NO_PKT_FIFO\n\n   //***********************************************\n   // Connect user flags to internal signals\n   //***********************************************\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3\n      if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);\n      end //block_ic\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3\n   endgenerate\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30\n       if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30\n   endgenerate\n\n\n    \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both\n       if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30_both\n   endgenerate\n\n generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both\n      if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));\n      end //block_ic_both\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3_both\n   endgenerate\n\n\n   //If we are not using extra logic for the FWFT data count,\n   //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the\n   //internal FIFO instance  \n   generate\n      if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n   //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal\n   //FIFO instance\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1) begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n      else begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n\n   //Connect other flags to the internal FIFO instance\n   assign       FULL        = FULL_FIFO_OUT;\n   assign       ALMOST_FULL = ALMOST_FULL_FIFO_OUT;\n   assign       WR_ACK      = WR_ACK_FIFO_OUT;\n   assign       OVERFLOW    = OVERFLOW_FIFO_OUT;\n   assign       PROG_FULL   = PROG_FULL_FIFO_OUT;\n   assign       PROG_EMPTY  = PROG_EMPTY_FIFO_OUT;\n\n\n  /**************************************************************************\n  * find_log2\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n   // if an asynchronous FIFO has been selected, display a message that the FIFO\n   //   will not be cycle-accurate in simulation\n   initial begin\n      if (C_IMPLEMENTATION_TYPE == 2) begin\n         $display(\"WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.\");\n      end else if (C_MEMORY_TYPE == 4) begin\n         $display(\"FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.\");\n         $finish;\n      end\n\n      if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin\n         $display(\"FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.\");\n         $finish;\n      end\n\n      if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin\n         $display(\"FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.\");\n         $finish;\n      end\n\n      if (C_USE_ECC == 1) begin\n         if (C_DIN_WIDTH != C_DOUT_WIDTH) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.\");\n            $finish;\n         end\n         if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.\");\n            $finish;\n         end\n      end\n\n   end //initial\n\n  /**************************************************************************\n  * Internal reset logic\n  **************************************************************************/\n  assign wr_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg|sckt_wr_rst_i : 0;\n  assign rd_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg|sckt_rd_rst_i : 0;\n  assign rst_i            = C_HAS_RST ? rst_reg|sckt_wr_rst_i : 0;\n\n  wire rst_2_sync;\n  wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;\n\n  localparam RST_SYNC_STAGES = C_EN_SAFETY_CKT == 0 ? C_COMMON_CLOCK ? C_SYNCHRONIZER_STAGE : C_SYNCHRONIZER_STAGE+2 : 5;\n  localparam RST_BUSY_LEN    = 4;\n  reg  wr_rst_busy_i = 0;\n  reg  rd_rst_busy_i = 0;\n  generate\n      if (C_ENABLE_RST_SYNC == 0 || (C_HAS_RST == 0 && C_HAS_SRST == 0)) begin : gnrst_sync\n        always @* begin\n          wr_rst_reg <= wr_rst_delayed;\n          rd_rst_reg <= rd_rst_delayed;\n          rst_reg    <= 1'b0;\n          srst_reg    <= 1'b0;\n        end\n        assign rst_2_sync = wr_rst_delayed;\n        assign wr_rst_busy = 1'b0;\n        assign wr_rst_busy_o = 1'b0;\n        assign rd_rst_busy = 1'b0;\n        assign sckt_wr_rst_i = 1'b0;\n      end // gnrst_sync\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 0) begin : g7s_ic_rst_nsckt\n        reg [1:0]                 arst_sync_wr  = 2'b11;\n        reg [1:0]                 arst_sync_rd  = 2'b11;\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge WR_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge RD_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_rd    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_rd    <= #`TCQ {arst_sync_rd[0], rst_delayed};\n        end\n        always @(posedge WR_CLK) begin\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n\tend\n        always @(posedge WR_CLK or posedge arst_sync_wr[1]) begin\n\t  if (arst_sync_wr[1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n            rd_rst_wr_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            rd_rst_wr_ext  <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t    if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t      sckt_wr_rst_ic <= #`TCQ 1'b0;\n            else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t      wr_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n        always @(posedge RD_CLK) begin\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], sckt_wr_rst_ic};\n\tend\n        always @(posedge RD_CLK or posedge arst_sync_rd[1]) begin\n\t  if (arst_sync_rd[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n            wr_rst_rd_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            wr_rst_rd_ext  <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t    if (wr_rst_rd_ext[1]) begin\n\t      sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t      rd_rst_busy_i  <= #`TCQ 1'b0;\n\t    end\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic|arst_sync_wr[1];\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic|arst_sync_rd[1];\n      end // g7s_ic_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 1) begin : g7s_ic_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] arst_sync_rd  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        always @(posedge WR_CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n          rd_rst_wr_ext    <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_wr[RST_SYNC_STAGES-1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n          end else if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t    sckt_wr_rst_ic <= #`TCQ 1'b0;\n          else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t    wr_rst_busy_i  <= #`TCQ 1'b0;\n\tend\n        always @(posedge RD_CLK) begin\n\t  arst_sync_rd     <= #`TCQ {arst_sync_rd[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n          wr_rst_rd_ext    <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_rd[RST_SYNC_STAGES-1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n\t  end else if (wr_rst_rd_ext[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t    rd_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic;\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic;\n      end // g7s_ic_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 0) begin : g7s_cc_rst_nsckt\n        reg [1:0]              arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge CLK) begin\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0] | arst_sync_wr[1]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc | arst_sync_wr[1];\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 1) begin : g7s_cc_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n\n        always @(posedge CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc;\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst\n        assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;\n        assign rd_rst_busy = rst_reg;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = rst_reg;\n        always @* rst_full_ff_i  <= 1'b0;\n        always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;\n\n        always @(posedge CLK) begin\n          rst_delayed_d1 <= #`TCQ srst_delayed;\n          rst_delayed_d2 <= #`TCQ rst_delayed_d1;\n          if (rst_reg || rst_delayed_d2) begin\n            rst_active_i <= #`TCQ 1'b1;\n          end else begin\n            rst_active_i <= #`TCQ rst_reg;\n          end    \n        end   \n        always @(posedge CLK) begin\n          if (~rst_reg && srst_delayed) begin\n             rst_reg <= #`TCQ 1'b1;\n           end else if (rst_reg) begin\n             rst_reg <= #`TCQ 1'b0;\n           end else begin\n             rst_reg <= #`TCQ rst_reg;\n           end    \n        end   \n      end // g8s_cc_rst\n      else if (IS_8SERIES != 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_srst\n        assign wr_rst_busy = srst_delayed;\n        assign rd_rst_busy = srst_delayed;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = srst_delayed;\n        always @* rst_full_ff_i  <= 1'b0;\n      end // g7s_cc_srst\n  endgenerate \n\n  reg rst_d1 = 1'b0;\n  reg rst_d2 = 1'b0;\n  reg rst_d3 = 1'b0;\n  reg rst_d4 = 1'b0;\n  generate\n    if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1\n    // RST_FULL_GEN replaces the reset falling edge detection used to de-assert\n    // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.\n\n    // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &\n    // PROG_FULL\n\n      always @ (posedge rst_2_sync or posedge clk_2_sync) begin\n        if (rst_2_sync && C_EN_SAFETY_CKT == 0) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          rst_d3         <= 1'b1;\n          rst_d4         <= 1'b0;\n        end else begin\n          if (srst_delayed) begin\n            rst_d1         <= #`TCQ 1'b1;\n            rst_d2         <= #`TCQ 1'b1;\n            rst_d3         <= #`TCQ 1'b1;\n            rst_d4         <= #`TCQ 1'b0;\n          end else begin\n            rst_d1         <= #`TCQ wr_rst_busy;//1'b0;\n            rst_d2         <= #`TCQ rst_d1;\n            rst_d3         <= #`TCQ rst_d2 | sckt_wr_rst_i;\n            rst_d4         <= #`TCQ rst_d3;\n          end\n        end\n      end\n\n      always @* rst_full_ff_i  <= C_HAS_SRST ? 1'b0 : rst_d2 | sckt_wr_rst_i;\n      always @* rst_full_gen_i <= C_HAS_SRST ? rst_d4 : rst_d3;\n\n    end else if (C_EN_SAFETY_CKT == 1 && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full_sckt\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end\n  endgenerate // grstd1\n\nendmodule //fifo_generator_v13_2_1_CONV_VER\n\n\nmodule fifo_generator_v13_2_1_sync_stage\n  #(\n    parameter  C_WIDTH          = 10\n   )\n   (\n    input                     RST,\n    input                     CLK,\n    input       [C_WIDTH-1:0] DIN,\n    output reg  [C_WIDTH-1:0] DOUT = 0\n   );\n   always @ (posedge RST or posedge CLK) begin\n     if (RST)\n       DOUT <= 0;\n     else\n       DOUT <= #`TCQ DIN;\n   end\nendmodule // fifo_generator_v13_2_1_sync_stage\n\n/*******************************************************************************\n * Declaration of Independent-Clocks FIFO Module\n ******************************************************************************/\nmodule fifo_generator_v13_2_1_bhv_ver_as\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2 \n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input                                         SAFETY_CKT_WR_RST,\n   input                                         SAFETY_CKT_RD_RST,\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_ASSERT,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_NEGATE,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_ASSERT,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_NEGATE,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         RD_EN_USER,\n   input                                         RST,\n   input                                         RST_FULL_GEN,\n   input                                         RST_FULL_FF,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   input                                         INJECTDBITERR,\n   input                                         INJECTSBITERR,\n   input                                         USER_EMPTY_FB,\n   input                                         fab_read_data_valid_i,\n   input                                         read_data_valid_i,\n   input                                         ram_valid_i,\n   output reg                                    ALMOST_EMPTY = 1'b1,\n   output reg                                    ALMOST_FULL = C_FULL_FLAGS_RST_VAL,\n   output      [C_DOUT_WIDTH-1:0]                DOUT,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    EMPTY_FB = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL,\n   output                                        OVERFLOW,\n   output                                        PROG_EMPTY,\n   output                                        PROG_FULL,\n   output                                        VALID,\n   output      [C_RD_DATA_COUNT_WIDTH-1:0]       RD_DATA_COUNT,\n   output                                        UNDERFLOW,\n   output                                        WR_ACK,\n   output      [C_WR_DATA_COUNT_WIDTH-1:0]       WR_DATA_COUNT,\n   output                                        SBITERR,\n   output                                        DBITERR\n  );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   \n  \n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   \n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;\n   // Array that holds the error injection type (single/double bit error) on \n   // a specific write operation, which is returned on read to corrupt the\n   // output data.\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   //The amount of data stored in the FIFO at any time is given\n   // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK\n   // domain.\n   //num_wr_bits is calculated by considering the total words in the FIFO,\n   // and the state of the read pointer (which may not have yet crossed clock\n   // domains.)\n   //num_rd_bits is calculated by considering the total words in the FIFO,\n   // and the state of the write pointer (which may not have yet crossed clock\n   // domains.)\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   wire                        wr_rst_i = WR_RST;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n   wire                        rd_rst_i = RD_RST;\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n\n\n\n   // Delayed ram_rd_en is needed only for STD Embedded register option\n   generate\n     if (C_PRELOAD_LATENCY == 2) begin : grd_d\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n       end\n     end\n   endgenerate\n   \n    generate\n     if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n           fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n       end\n     end\n   endgenerate\n\n  \n\n   // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;\n     end else begin : rdl // Read depth lesser than or equal to write depth\n       assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n     end\n   endgenerate\n\n   // Generate Empty and Almost Empty\n  // ram_rd_en used to determine EMPTY should depend on the EMPTY.\n   assign ram_rd_en        = RD_EN & !EMPTY;\n   assign empty_int        = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));\n   assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));\n\n   // Register Empty and Almost Empty\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else begin\n         rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};\n\n         if (empty_int)\n           EMPTY           <= #`TCQ 1'b1;\n         else\n           EMPTY           <= #`TCQ 1'b0;\n\n         if (!EMPTY) begin\n           if (almost_empty_int)\n             ALMOST_EMPTY  <= #`TCQ 1'b1;\n           else\n             ALMOST_EMPTY  <= #`TCQ 1'b0;\n         end\n       end // rd_rst_i\n     end // always\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY_FB     <= 1'b1;\n       end else begin\n         if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else if (empty_int)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else\n           EMPTY_FB   <= #`TCQ 1'b0;\n       end // rd_rst_i\n     end // always\n\n   // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;\n     end else begin : wdl // Write depth lesser than or equal to read depth\n       assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n     end\n   endgenerate\n\n  // Generate FULL and ALMOST_FULL\n  // ram_wr_en used to determine FULL should depend on the FULL.\n  assign ram_wr_en       = WR_EN & !FULL;\n  assign full_int        = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));\n  assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));\n\n   // Register FULL and ALMOST_FULL Empty\n   always @ (posedge WR_CLK or posedge RST_FULL_FF)\n     begin\n       if (RST_FULL_FF & C_HAS_RST) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else begin\n         if (full_int) begin\n           FULL           <= #`TCQ 1'b1;\n         end else begin\n           FULL           <= #`TCQ 1'b0;\n         end\n\n         if (RST_FULL_GEN) begin\n           ALMOST_FULL    <= #`TCQ 1'b0;\n         end else if (!FULL) begin\n           if (almost_full_int)\n             ALMOST_FULL  <= #`TCQ 1'b1;\n           else\n             ALMOST_FULL  <= #`TCQ 1'b0;\n         end\n       end // wr_rst_i\n     end // always\n   always @ (posedge WR_CLK or posedge wr_rst_i)\n     begin\n       if (wr_rst_i) begin\n         wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};\n       end else begin\n         wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};\n       end // wr_rst_i\n     end // always\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i) begin\n           stage1_valid     <= 0;\n           stage2_valid     <= 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n   //Pointers passed into opposite clock domain\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_EMPTY.\n   wire [31:0] num_read_words_pe = \n     num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_FULL.\n   wire [31:0] num_write_words_pf =\n     num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n    \n    \n   /***************************************************************************\n    * Internal registers and wires\n    **************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire [C_DOUT_WIDTH-1:0] ideal_dout_out;      \n   wire valid_i;\n   wire valid_out1;\n   wire valid_out2;\n   wire valid_out;  \n   wire underflow_i;\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]               err_type                 = 0;\n   reg [1:0]               err_type_d1              = 0;\n   reg [1:0]               err_type_both              = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout               = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_d1            = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_both            = 0;\n   reg                     ideal_wr_ack             = 0;\n   reg                     ideal_valid              = 0;\n   reg                     ideal_overflow           = C_OVERFLOW_LOW;\n   reg                     ideal_underflow          = C_UNDERFLOW_LOW;\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   reg         valid_d1     = 0;\n   reg         valid_d2     = 0; \n   \n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n   \n\n  /****************************************************************************\n   * Function Declarations\n   ***************************************************************************/\n\n  /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n      if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n    end\n  endtask\n\n  /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n  /***********************************************************************\n  * hexstr_conv\n  *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n  ***********************************************************************/\n  function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_d2           = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n    end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the \n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n    wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;   \n   wire RD_CLK;\n   wire RD_EN;\n   wire RST;\n   wire WR_CLK;\n   wire WR_EN;\n    */\n\n   //***************************************************************************\n   // Dout may change behavior based on latency\n   //***************************************************************************\n   assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?\n                         ideal_dout_d1: ideal_dout;   \n   assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; \n\n   //***************************************************************************\n   // Assign SBITERR and DBITERR based on latency \n   //***************************************************************************\n   assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                    (C_PRELOAD_LATENCY == 2 &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?\n                    err_type_d1[0]: err_type[0]; \n   assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                    (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                    err_type_d1[1]: err_type[1]; \n  \n   //***************************************************************************\n   // Safety-ckt logic with embedded reg/fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n       //  if (C_HAS_VALID == 1) begin\n       //       assign valid_out = valid_d1;\n       //  end\n             \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)\n          begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else \n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n          end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                  @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n           end\n           else begin\n                   if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                   end\n             end \n           end  \n      end \n      endgenerate   \n\n//***************************************************************************\n   // Safety-ckt logic with embedded reg + fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else begin\n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n               fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n          end\n        end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   ideal_dout_both <= #`TCQ dout_reset_val;\n              end\n           end else begin\n             if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n              \n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n             end\n           end \n         end      \n      end \n      endgenerate    \n \n   //***************************************************************************\n   // Overflow may be active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_OVERFLOW==1) begin : blockOF1\n   assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n      end\n   endgenerate\n\n   assign PROG_EMPTY = ideal_prog_empty;\n   assign PROG_FULL  = ideal_prog_full;\n\n   //***************************************************************************\n   // Valid may change behavior based on latency or active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_VALID==1) begin : blockVL1\n   assign valid_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;\n   assign valid_out1 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?\n                       valid_d1: valid_i;  \n   assign valid_out2 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?\n                       valid_d2: valid_i; \n   assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;\n   assign VALID     = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Underflow may change behavior based on latency or active-low   \n   //***************************************************************************\n   generate\n      if (C_HAS_UNDERFLOW==1) begin : blockUF1\n   assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;\n   assign UNDERFLOW   = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n    end\n   endgenerate\n\n   //***************************************************************************\n   // Write acknowledge may be active low\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_ACK==1) begin : blockWK1\n   assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext\n\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_wr_pntr = 0;\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_rd_pntr = 0;\n      wire [C_PNTR_WIDTH-1:0]  diff_wr_rd_tmp;\n      wire [C_PNTR_WIDTH:0]    diff_wr_rd;\n      reg  [C_PNTR_WIDTH:0]    wr_data_count_i  = 0;\n        always @* begin\n          if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = 0;\n            adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n          end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin\n            adjusted_rd_pntr = rd_pntr_wr;\n            adjusted_wr_pntr = 0;\n            adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n          end else begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = rd_pntr_wr;\n          end\n        end // always @*\n\n        assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;\n        assign diff_wr_rd     = {1'b0,diff_wr_rd_tmp};\n\n        always @ (posedge wr_rst_i or posedge WR_CLK)\n        begin\n            if (wr_rst_i)\n              wr_data_count_i <= 0;\n            else\n              wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;\n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n\n        always @* begin\n          if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];\n          else\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n        end // always @*\n      end // wdc_fwft_ext\n   endgenerate\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   reg  [C_RD_PNTR_WIDTH:0]    rdc_fwft_ext_as  = 0;\n\n   generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n\n\n   always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= 0;\n            end else begin\n              if (!stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 0;\n              else if (!stage1_valid && stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 1;\n              else\n                rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;\n            end \n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n      end // rdc_fwft_ext\n end\n   endgenerate\n\n\n  generate if (C_USE_EMBEDDED_REG == 3) begin\n     if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n        wire [C_RD_PNTR_WIDTH:0]  diff_rd_wr_1;\n   //     assign diff_rd_wr_1 = diff_rd_wr +2'h2;\n\n       always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= #`TCQ 0;\n            end else begin\n          //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))\n          //    rdc_fwft_ext_as <= 1'b0;\n          //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) \n          //    rdc_fwft_ext_as <= 1'b1;\n          //else\n            rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;\n        end\n\n\n\nend\nend\nend\nendgenerate\n          \n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1) begin : grdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?\n          rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :\n          rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?\n          wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :\n          wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n\n  /**************************************************************************\n  * Assorted registers for delayed versions of signals\n  **************************************************************************/\n  //Capture delayed version of valid\n  generate\n      if (C_HAS_VALID==1) begin : blockVL2\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n      valid_d1 <= 1'b0;\n      valid_d2 <= 1'b0;\n    end else begin\n      valid_d1 <= #`TCQ valid_i;\n      valid_d2 <= #`TCQ valid_d1;\n    end \n//    if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin\n  //      valid_d2 <= #`TCQ valid_d1;\n      //  end \n  end \n      end\n endgenerate  \n   \n  //Capture delayed version of dout\n  /**************************************************************************\n    *embedded/fabric reg with no safety ckt\n    **************************************************************************/\n  generate \n       if (C_USE_EMBEDDED_REG < 3) begin\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n       if (C_USE_DOUT_RST == 1'b1) begin\n         @(posedge RD_CLK)\n           ideal_dout_d1   <= #`TCQ dout_reset_val;\n           ideal_dout   <= #`TCQ dout_reset_val;\n       end\n      // Reset err_type only if ECC is not selected\n      if (C_USE_ECC == 0)\n        err_type_d1     <= #`TCQ 0;\n     end else if (ram_rd_en_d1) begin\n      ideal_dout_d1   <= #`TCQ ideal_dout;\n      err_type_d1     <= #`TCQ err_type;\n           end    \n  end  \n   \nend  \nendgenerate \n/**************************************************************************\n    *embedded + fabric reg with no safety ckt\n    **************************************************************************/\n\ngenerate \n  if (C_USE_EMBEDDED_REG == 3) begin\n    always @(posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i == 1'b1) begin\n        if (C_USE_DOUT_RST == 1'b1) begin\n           @(posedge RD_CLK)\n             ideal_dout    <= #`TCQ dout_reset_val;\n             ideal_dout_d1   <= #`TCQ dout_reset_val;\n             ideal_dout_both   <= #`TCQ dout_reset_val;\n        end\n        // Reset err_type only if ECC is not selected\n        if (C_USE_ECC == 0) begin\n          err_type_d1     <= #`TCQ 0;\n          err_type_both   <= #`TCQ 0;\n        end\n      end else begin\n         if (ram_rd_en_d1) begin\n           ideal_dout_both   <= #`TCQ ideal_dout;\n           err_type_both     <= #`TCQ err_type;\n         end    \n         if (fab_rd_en_d1) begin\n           ideal_dout_d1   <= #`TCQ ideal_dout_both;\n           err_type_d1     <= #`TCQ err_type_both;\n         end\n      end\n    end  \n  end  \nendgenerate \n\n  \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate\n     if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n       always @(posedge WR_CLK) begin\n         ideal_overflow    <= #`TCQ WR_EN & FULL;\n       end\n     end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n       always @(posedge WR_CLK) begin\n         //ideal_overflow    <= #`TCQ WR_EN & (FULL | wr_rst_i);\n         ideal_overflow    <= #`TCQ WR_EN & (FULL );\n       end\n     end\n   endgenerate\n\n   generate\n     if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ EMPTY & RD_EN;\n       end\n     end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ (EMPTY) & RD_EN;\n         //ideal_underflow    <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;\n       end\n     end\n   endgenerate\n\n   /**************************************************************************\n   * Write/Read Pointer Synchronization\n   **************************************************************************/\n   localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;\n   wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   genvar gss;\n\n   generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst\n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (C_WR_PNTR_WIDTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_i), \n         .CLK      (RD_CLK), \n         .DIN      (wr_pntr_sync_stgs[gss-1]), \n         .DOUT     (wr_pntr_sync_stgs[gss])\n        );\n \n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (C_RD_PNTR_WIDTH)\n        )\n     wr_stg_inst\n        (\n         .RST      (wr_rst_i), \n         .CLK      (WR_CLK), \n         .DIN      (rd_pntr_sync_stgs[gss-1]), \n         .DOUT     (rd_pntr_sync_stgs[gss])\n        );\n   end endgenerate // Sync_stage_inst\n\n   assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;\n   assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;\n   always@* begin\n     wr_pntr_rd           <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n     rd_pntr_wr           <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n   end\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp\n     if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)\n       wr_pntr           <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)\n       wr_pntr           <= #`TCQ 0;\n   end\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (wr_rst_i == 1'b1) begin\n       num_wr_bits       <= 0;\n       next_num_wr_bits   = 0;\n       wr_ptr            <= C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= C_RD_DEPTH - 1;\n       ideal_wr_ack      <= 0;\n       ideal_wr_count    <= 0;\n       tmp_wr_listsize    = 0;\n       rd_ptr_wrclk_next <= 0;\n       wr_pntr_rd1       <= 0;\n\n     end else begin //wr_rst_i==0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       //If this is a write, handle the write by adding the value\n       // to the linked list, and updating all outputs appropriately\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD \n             >= C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full, but reporting full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //With DEPTH-1 words in the FIFO, it is almost_full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n\n           //If the FIFO is completely empty, but it is\n           // reporting FULL for some reason (like reset)\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=\n                C_FIFO_WR_DEPTH-2) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //FIFO is really not close to full, so change flag status.\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n           end //(tmp_wr_listsize == 0)\n\n         end else begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=\n              C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack       <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count     <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;\n\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //This write is CAUSING the FIFO to go full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is 2 from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == \n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits =  next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Still 2 from full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is not close to being full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <\n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //wr_rst_i==0\n   end // gen_fifo_w\n\n\n  /***************************************************************************\n   * Programmable FULL flags\n   ***************************************************************************/\n\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;\n\n   generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;\n   end else begin // STD\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;\n   end endgenerate\n\n   always @(posedge WR_CLK or posedge wr_rst_i) begin\n\n     if (wr_rst_i == 1'b1) begin\n       diff_pntr         <= 0;\n     end else begin\n       if (ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);\n       else if (!ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);\n    end\n  end\n\n\n   always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf\n\n     if (RST_FULL_FF & C_HAS_RST) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else begin\n\n       if (RST_FULL_GEN)\n         ideal_prog_full   <= #`TCQ 0;\n       //Single Programmable Full Constant Threshold\n       else if (C_PROG_FULL_TYPE == 1) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else\n             ideal_prog_full <= #`TCQ 0;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Constant Thresholds\n       end else if (C_PROG_FULL_TYPE == 2) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else if (diff_pntr < pf_thr_negate_val)\n             ideal_prog_full <= #`TCQ 0;\n           else\n             ideal_prog_full <= #`TCQ ideal_prog_full;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Single Programmable Full Threshold Input\n       end else if (C_PROG_FULL_TYPE == 3) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH)\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Threshold Inputs\n       end else if (C_PROG_FULL_TYPE == 4) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH_ASSERT)\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < PROG_FULL_THRESH_NEGATE)\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       end // C_PROG_FULL_TYPE\n\n     end //wr_rst_i==0\n   end //\n\n   \n   /**************************************************************************\n   * Read Domain Logic\n   **************************************************************************/\n\n\n   /*********************************************************\n    * Programmable EMPTY flags\n    *********************************************************/\n   //Determine the Assert and Negate thresholds for Programmable Empty\n\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd      = 0;\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe\n\n     if (rd_rst_i & C_HAS_RST) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else begin\n       if (ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;\n       else if (!ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr);\n       else\n         diff_pntr_rd       <=  #`TCQ diff_pntr_rd;\n  \n       if (C_PROG_EMPTY_TYPE == 1) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 2) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 3) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 4) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end  //C_PROG_EMPTY_TYPE\n     end\n   end // gen_pe\n\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;\n   end endgenerate // single_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;\n   end endgenerate // multiple_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;\n   end endgenerate // single_multiple_pe_thr_const\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp\n     if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n       rd_pntr            <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)\n       rd_pntr            <= #`TCQ 0;\n   end\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rd_rst_i & C_HAS_RST) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n     end else begin //rd_rst_i==0\n\n       rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 1\n       /*****************************************************************/\n       if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Reminder that FIFO is still empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end // if (tmp_rd_listsize <= 0)\n\n             //If the FIFO is one from empty, but it is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 1)\n\n             //If the FIFO is two from empty, and is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Fifo has two words, so is neither empty or almost empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 2)\n\n             //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid <= #`TCQ 1'b0;\n                 //Note that the FIFO is No Longer Empty or Almost Empty\n\n                 ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n               end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n             end // else: if(ideal_empty == 1'b1)\n\n           else //if (ideal_empty == 1'b0)\n             begin\n\n               //If the FIFO is completely full, and we are successfully reading from it\n               if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)\n\n               //If the FIFO is not close to being empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n               //If the FIFO is two from empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Fifo is not yet empty. It is going almost_empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n\n               //If the FIFO is one from empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Note that FIFO is GOING empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 1)\n\n\n               //If the FIFO is completely empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n                 begin\n                   //Do not change the contents of the FIFO\n\n                   //Do not acknowledge the read from empty FIFO\n                   ideal_valid        <= #`TCQ 1'b0;\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize <= 0)\n\n             end // if (ideal_empty == 1'b0)\n\n           end //(RD_EN == 1'b1)\n\n         else //if (RD_EN == 1'b0)\n           begin\n             //If user did not attempt a read, do not give an ack or err\n             ideal_valid          <= #`TCQ 1'b0;\n\n             ideal_rd_count       <= #`TCQ num_read_words_sized_i;\n\n           end // else: !if(RD_EN == 1'b1)\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 0\n       /*****************************************************************/\n       end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty, but it is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty, and is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Fifo has two words, so is neither empty or almost empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                         (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that the FIFO is No Longer Empty or Almost Empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n           end else begin\n\n             //If the FIFO is completely full, and we are successfully reading from it\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is not close to being empty\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                          (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Fifo is not yet empty. It is going almost_empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Note that FIFO is GOING empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is completely empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if (tmp_rd_listsize <= 0)\n\n           end // if (ideal_empty == 1'b0)\n\n         end else begin//(RD_EN == 1'b0)\n\n         \n           //If user did not attempt a read, do not give an ack or err\n           ideal_valid           <= #`TCQ 1'b0;\n           ideal_rd_count        <= #`TCQ num_read_words_sized_i;\n\n         end // else: !if(RD_EN == 1'b1)\n       end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //rd_rst_i==0\n   end //always gen_fifo_r_as\n\nendmodule // fifo_generator_v13_2_1_bhv_ver_as\n\n\n/*******************************************************************************\n * Declaration of Low Latency Asynchronous FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_1_beh_ver_ll_afifo\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_FIFO_TYPE                    = 0\n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   output reg  [C_DOUT_WIDTH-1:0]                DOUT = 0,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL\n  );\n\n  //-----------------------------------------------------------------------------\n  // Low Latency Asynchronous FIFO\n  //-----------------------------------------------------------------------------\n\n  // Memory which will be used to simulate a FIFO\n  reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n  integer i;\n  initial begin\n    for (i = 0; i < C_WR_DEPTH; i = i + 1)\n      memory[i] = 0;\n  end\n\n  reg  [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;\n  wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;\n  reg  [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;\n  reg                        ll_afifo_full    = 1'b0;\n  reg                        ll_afifo_empty   = 1'b1;\n  wire                       write_allow;\n  wire                       read_allow;\n\n  assign write_allow = WR_EN & ~ll_afifo_full;\n  assign read_allow  = RD_EN & ~ll_afifo_empty;\n\n  //-----------------------------------------------------------------------------\n  // Write Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      wr_pntr_ll_afifo   <= 0;\n    else if (write_allow)\n      wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Read Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      rd_pntr_ll_afifo_q   <= 0;\n    else\n      rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;\n  end\n  assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;\n  \n  //-----------------------------------------------------------------------------\n  // Fill the Memory\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK) begin\n    if (write_allow)\n      memory[wr_pntr_ll_afifo] <= #`TCQ DIN;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate DOUT\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK) begin\n      DOUT <= #`TCQ memory[rd_pntr_ll_afifo];\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate EMPTY\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      ll_afifo_empty   <= 1'b1;\n    else\n      ll_afifo_empty   <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | \n                           (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate FULL\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      ll_afifo_full   <= 1'b1;\n    else\n      ll_afifo_full   <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | \n                           (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));\n  end\n\n  always @* begin\n    FULL  <= ll_afifo_full;\n    EMPTY <= ll_afifo_empty;\n  end\n\nendmodule // fifo_generator_v13_2_1_beh_ver_ll_afifo\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_v13_2_1_bhv_ver_ss\n   \n  /**************************************************************************\n   * Declare user parameters and their defaults\n   *************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0 \n   )\n   \n  /**************************************************************************\n   * Declare Input and Output Ports\n   *************************************************************************/\n   (\n    //Inputs\n    input                                 SAFETY_CKT_WR_RST,\n    input                                 CLK,\n    input       [C_DIN_WIDTH-1:0]         DIN,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_ASSERT,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_NEGATE,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_ASSERT,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_NEGATE,\n    input                                 RD_EN,\n    input                                 RD_EN_USER,\n    input                                 USER_EMPTY_FB,\n    input                                 RST,\n    input                                 RST_FULL_GEN,\n    input                                 RST_FULL_FF,\n    input                                 SRST,\n    input                                 WR_EN,\n    input                                 INJECTDBITERR,\n    input                                 INJECTSBITERR,\n    input                                 WR_RST_BUSY,\n    input                                 RD_RST_BUSY,\n                                    \n    //Outputs                       \n    output                                ALMOST_EMPTY,\n    output                                ALMOST_FULL,\n    output reg   [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,\n    output       [C_DOUT_WIDTH-1:0]       DOUT,\n    output                                EMPTY,\n    output reg                            EMPTY_FB = 1'b1,\n    output                                FULL,\n    output                                OVERFLOW,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]    RD_DATA_COUNT,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]    WR_DATA_COUNT,\n    output                                PROG_EMPTY,\n    output                                PROG_FULL,\n    output                                VALID,\n    output                                UNDERFLOW,\n    output                                WR_ACK,\n    output                                SBITERR,\n    output                                DBITERR\n   );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;\n   wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n   localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; \n\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n   localparam  EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //localparam  EXTRA_WORDS_PE_PARAM  = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not \n   //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.\n   // Therefore, during SRST, all the FULL flags reset to 0.\n   localparam                      C_HAS_FAST_FIFO = 0;\n   localparam                      C_FIFO_WR_DEPTH = C_WR_DEPTH;\n   localparam                      C_FIFO_RD_DEPTH = C_RD_DEPTH;\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;\n   localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;\n   localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;\n   localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n  localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; \n  localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; \n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   \n   /**************************************************************************\n    * Internal Registers and wires\n    *************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire                           underflow_i;\n   wire                           valid_i;\n   wire                           valid_out;\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_reg = 1'b0;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n   wire                         srst_rrst_busy;\n\n\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]                      err_type           = 0;\n   reg [1:0]                      err_type_d1        = 0;\n   reg [1:0]                      err_type_both      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout         = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_d1      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_both      = 0;\n   wire [C_DOUT_WIDTH-1:0]        ideal_dout_out;\n   wire                           fwft_enabled;\n   reg                            ideal_wr_ack       = 0;\n   reg                            ideal_valid        = 0;\n   reg                            ideal_overflow     = C_OVERFLOW_LOW;\n   reg                            ideal_underflow    = C_UNDERFLOW_LOW;\n\n   reg                            full_i             = C_FULL_FLAGS_RST_VAL;\n   reg                            full_i_temp        = 0;\n   reg                            empty_i            = 1;\n   reg                            almost_full_i      = 0;\n   reg                            almost_empty_i     = 1;\n   reg                            prog_full_i        = 0;\n   reg                            prog_empty_i       = 1;\n   reg [C_WR_PNTR_WIDTH-1:0]      wr_pntr            = 0;\n   reg [C_RD_PNTR_WIDTH-1:0]      rd_pntr            = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg [C_RD_PNTR_WIDTH-1:0]      diff_count         = 0;\n\n   reg                            write_allow_q      = 0;\n   reg                            read_allow_q       = 0;\n   reg                            valid_d1           = 0;\n   reg                            valid_both           = 0;\n   reg                            valid_d2           = 0;\n   wire                           rst_i;\n   wire                           srst_i;\n\n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]         dout_reset_val = 0;\n\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n\n\n\n   /****************************************************************************\n    * Function Declarations\n    ***************************************************************************/\n\n   /****************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***************************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin\n        case (def_data[7:0])\n          8'b00000000 : begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default : begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1) begin\n          if ((index*4)+j < C_DOUT_WIDTH) begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   //reg         valid_d1     = 0;\n   \n   \n   //user specified value for reseting the size of the fifo\n   //reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n\n\n /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n     if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n\n     end\n  endtask\n\n\n   \n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_dout_both    = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_both         = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n\n   end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the\n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n   wire CLK;\n   wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;\n   wire RD_EN;\n   wire RST;\n   wire WR_EN;\n    */\n\n  // Assign ALMOST_EPMTY\n  generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae\n    assign ALMOST_EMPTY = almost_empty_i;\n  end else begin : gnae\n    assign ALMOST_EMPTY = 0;\n  end endgenerate // gae\n\n  // Assign ALMOST_FULL\n  generate if (C_HAS_ALMOST_FULL==1) begin : gaf\n    assign ALMOST_FULL  = almost_full_i;\n  end else begin : gnaf\n    assign ALMOST_FULL  = 0;\n  end endgenerate // gaf\n\n   // Dout may change behavior based on latency\n  localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?\n                         ideal_dout_d1: ideal_dout; \n  assign DOUT = ideal_dout_out;\n\n  // Assign SBITERR and DBITERR based on latency \n  assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[0]: err_type[0]; \n  assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[1]: err_type[1]; \n\n  assign EMPTY         = empty_i;\n  assign FULL          = full_i;\n  //saftey_ckt with one register\n\n  generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)\n          begin\n          if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n              valid_d1 <= #`TCQ 1'b0;\n          end\n          else begin\n               ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n               valid_d1 <= #`TCQ valid_i;\n          end\n          end\n          \n           always@(posedge rst_delayed_sft2 or posedge CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n              end\n           else if (srst_rrst_busy == 1'b1) begin\n                   if (C_USE_DOUT_RST == 1'b1) begin\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   end\n           end else if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                end\n           end   \n      end //if \n      endgenerate   \n\n//safety ckt with both registers\n\ngenerate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK) begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            valid_d1 <= #`TCQ 1'b0;\n          end else begin\n            ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n            fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n            valid_both <= #`TCQ valid_i;\n            valid_d1 <= #`TCQ valid_both;\n          end\n        end\n\n        always@(posedge rst_delayed_sft2 or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                  ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else if (srst_rrst_busy == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else begin \n            if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n            end\n          end\n        end\n      end //if \n      endgenerate    \n \n \n  //Overflow may be active-low\n  generate if (C_HAS_OVERFLOW==1) begin : gof\n    assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n  end else begin : gnof\n    assign OVERFLOW = 0;\n  end endgenerate // gof\n\n  assign PROG_EMPTY    = prog_empty_i;\n  assign PROG_FULL     = prog_full_i;\n\n   //Valid may change behavior based on latency or active-low\n  generate if (C_HAS_VALID==1) begin : gvalid\n    assign valid_i       = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;\n    assign valid_out     = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?\n                            valid_d1 : valid_i; \n    assign VALID         = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n  end else begin : gnvalid\n    assign VALID         = 0;\n  end endgenerate // gvalid\n\n  //Trim data count differently depending on set widths\n  generate if (C_HAS_DATA_COUNT == 1) begin : gdc\n    always @* begin\n      diff_count <= wr_pntr - rd_pntr;\n      if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin\n        DATA_COUNT[C_RD_PNTR_WIDTH-1:0]  <= diff_count;\n        DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; \n      end else begin\n        DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];\n      end\n    end\n//  end else begin : gndc\n//    always @* DATA_COUNT <= 0;\n  end endgenerate // gdc\n\n  //Underflow may change behavior based on latency or active-low\n  generate if (C_HAS_UNDERFLOW==1) begin : guf\n    assign underflow_i   = ideal_underflow;\n    assign UNDERFLOW     = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n  end else begin : gnuf\n    assign UNDERFLOW     = 0;\n  end endgenerate // guf\n \n\n  //Write acknowledge may be active low \n  generate if (C_HAS_WR_ACK==1) begin : gwr_ack\n    assign WR_ACK        = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n  end else begin : gnwr_ack\n    assign WR_ACK        = 0;\n  end endgenerate // gwr_ack\n\n\n  /*****************************************************************************\n   * Internal reset logic \n   ****************************************************************************/\n  assign srst_i        = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;\n  assign rst_i            = C_HAS_RST ? RST : 0;\n  assign srst_wrst_busy   = srst_i;\n  assign srst_rrst_busy   = srst_i;\n\n   /**************************************************************************\n    * Assorted registers for delayed versions of signals\n    **************************************************************************/\n   //Capture delayed version of valid\n   generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20\n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1 <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n           end else begin\n              valid_d1 <= #`TCQ valid_i;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n     end \n   endgenerate // blockVL20\n\n  generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin \n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1   <= 1'b0;\n           valid_both <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n              valid_both <= #`TCQ 1'b0;\n              \n           end else begin\n              valid_both <= #`TCQ valid_i;\n               valid_d1 <= #`TCQ valid_both;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n  end\n endgenerate // blockVL20\n\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge CLK or posedge rst_i) begin\n         if (rst_i) begin\n           stage1_valid     <= #`TCQ 0;\n           stage2_valid     <= #`TCQ 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n\n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc\n       assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc\n       assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n   \n   //reg ram_rd_en_d1 = 1'b0;\n   //Capture delayed version of dout\n   generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         ram_rd_en_d1 <= #`TCQ 1'b0;\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n        end\n      end else begin\n         ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n         if (srst_rrst_busy) begin\n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            // Reset err_type only if ECC is not selected\n            if (C_USE_ECC == 0) begin\n               err_type_d1   <= #`TCQ 0;\n               err_type_both <= #`TCQ 0;\n            end\n            // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n            if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n            end \n         if (C_USE_DOUT_RST == 1) begin\n           // @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         end else begin\n            if (ram_rd_en_d1 ) begin\n            ideal_dout_d1 <= #`TCQ ideal_dout;\n            err_type_d1   <= #`TCQ err_type;\n            end\n         end\n      end    \n   end   // always\nend\nendgenerate \n\n//no safety ckt with both registers\n generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n          ram_rd_en_d1 <= #`TCQ 1'b0;\n          fab_rd_en_d1 <= #`TCQ 1'b0;\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val; \n            \n      end\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val;\n       end\n      end else begin\n         if (srst_rrst_busy) begin \n           ram_rd_en_d1 <= #`TCQ 1'b0;\n           fab_rd_en_d1 <= #`TCQ 1'b0;\n           // Reset err_type only if ECC is not selected\n           if (C_USE_ECC == 0) begin\n              err_type_d1   <= #`TCQ 0;\n              err_type_both <= #`TCQ 0;\n           end\n           // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n           if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n              ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end \n           if (C_USE_DOUT_RST == 1) begin\n             ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end\n         end else begin\n           ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n           fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);\n           if (ram_rd_en_d1 ) begin\n             ideal_dout_both <= #`TCQ ideal_dout;\n             err_type_both   <= #`TCQ err_type;\n           end\n           if (fab_rd_en_d1 ) begin\n             ideal_dout_d1 <= #`TCQ ideal_dout_both;\n             err_type_d1   <= #`TCQ err_type_both;\n           end\n         end\n      end    \n   end   // always\nend\nendgenerate \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n     always @(posedge CLK) begin\n       ideal_overflow    <= #`TCQ WR_EN & full_i;\n     end\n   end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n     always @(posedge CLK) begin\n       //ideal_overflow    <= #`TCQ WR_EN & (rst_i | full_i);\n       ideal_overflow    <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);\n     end\n   end endgenerate // blockOF20\n \n   generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n     always @(posedge CLK) begin\n       ideal_underflow   <= #`TCQ empty_i & RD_EN;\n     end\n   end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n     always @(posedge CLK) begin\n       //ideal_underflow   <= #`TCQ (rst_i | empty_i) & RD_EN;\n       ideal_underflow   <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;\n     end\n   end endgenerate // blockUF20\n\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n\n  /*************************************************************************\n   * Write and Read Logic  \n   ************************************************************************/\n   wire              write_allow;\n   wire              read_allow;\n   wire              read_allow_dc;\n   wire              write_only;\n   wire              read_only;\n   //wire              write_only_q;\n   reg              write_only_q;\n   //wire              read_only_q;\n   reg              read_only_q;\n   reg              full_reg;\n   reg              rst_full_ff_reg1;\n   reg              rst_full_ff_reg2;\n   wire              ram_full_comb;\n   wire              carry;\n   \n   assign write_allow  = WR_EN & ~full_i;\n   assign read_allow   = RD_EN & ~empty_i;\n   assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;\n   //assign write_only   = write_allow & ~read_allow;\n   //assign write_only_q = write_allow_q;\n   //assign read_only    = read_allow    & ~write_allow;\n   //assign read_only_q  = read_allow_q ;\n   wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;\n   wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;\n   wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;\n\n   assign diff_pntr_pe_max = DIFF_MAX_RD;\n   assign diff_pntr_max = DIFF_MAX_WR;\n\n\n\n   generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym\n    assign write_only   = write_allow & ~read_allow;\n    assign read_only    = read_allow    & ~write_allow;\n    end endgenerate\n    generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd\n     assign read_only   = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;\n     assign write_only    = write_allow    & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n    generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr\n     assign read_only   = read_allow & ~(write_allow  & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n     assign write_only    = write_allow &  &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;\n    end endgenerate\n\n\n   //-----------------------------------------------------------------------------\n   // Write and Read pointer generation\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       wr_pntr         <= 0;\n       rd_pntr         <= 0;\n     end else begin\n       if (srst_i) begin\n         wr_pntr       <= #`TCQ 0;\n         rd_pntr       <= #`TCQ 0;\n       end else begin\n         if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;\n         if (read_allow)  rd_pntr <= #`TCQ rd_pntr + 1;\n       end\n     end\n   end\n\n   generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout\n   always @(posedge CLK) begin\n     if (write_allow) begin\n       if (ENABLE_ERR_INJECTION == 1)\n         memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};\n       else\n         memory[wr_pntr] <= #`TCQ DIN;\n     end\n   end\n\n   reg  [C_DATA_WIDTH-1:0] dout_tmp_q;\n   reg [C_DATA_WIDTH-1:0] dout_tmp = 0;\n   reg  [C_DATA_WIDTH-1:0] dout_tmp1 = 0;\n   always @(posedge CLK) begin\n     dout_tmp_q <= #`TCQ ideal_dout;\n   end\n\n\n\n     always @* begin\n       if (read_allow)\n         ideal_dout <= memory[rd_pntr];\n       else\n         ideal_dout <= dout_tmp_q;\n     end\n   end endgenerate // gll_dm_dout\n\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   assign ram_rd_en        = RD_EN & !EMPTY;\n\n   //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   generate if (C_FIFO_TYPE != 2) begin : gnll_din\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i == 1'b1) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n\n     end else begin //rst_i==0\n     if (srst_wrst_busy) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n     end else begin//srst_i=0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n         end else begin\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error  \n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           //end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //srst_i==0\n     end //wr_rst_i==0\n   end // gen_fifo_w\n    end endgenerate\n\n   generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout\n     always @(posedge CLK) begin\n       if (rst_i || srst_rrst_busy) begin\n         if (C_USE_DOUT_RST == 1) begin\n           ideal_dout <= #`TCQ dout_reset_val;\n           ideal_dout_both <= #`TCQ dout_reset_val;\n         end\n       end\n     end\n    end endgenerate\n\n\n\n\n   generate if (C_FIFO_TYPE != 2) begin : gnll_dout\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_r\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n\n     end else begin //rd_rst_i==0\n     if (srst_rrst_busy) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets synchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= #`TCQ 0;\n         err_type_both    <= #`TCQ 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n      end //srst_i\n      else begin\n\n       //rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n         if (RD_EN == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end \n           else \n             begin\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n         end\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //s_rst_i==0\n     end //rd_rst_i==0\n   end //always\n  end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate diff_pntr for PROG_FULL generation\n   // Generate diff_pntr_pe for PROG_EMPTY generation\n   //-----------------------------------------------------------------------------\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         write_only_q   <= 1'b0;\n         read_only_q    <= 1'b0;\n         diff_pntr_reg1       <= 0;\n         diff_pntr_pe_reg1    <= 0;\n         diff_pntr_reg2       <= 0;\n         diff_pntr_pe_reg2    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_rrst_busy) begin\n           read_only_q  <= #`TCQ 1'b0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n           diff_pntr_pe_reg2  <= #`TCQ 0;\n          end\n          if (srst_wrst_busy) begin\n           write_only_q <= #`TCQ 1'b0;\n           diff_pntr_reg1     <= #`TCQ 0;\n           diff_pntr_reg2     <= #`TCQ 0;\n          end\n         end else begin\n           write_only_q <= #`TCQ write_only;\n           read_only_q  <= #`TCQ read_only;\n           diff_pntr_reg2  <= #`TCQ diff_pntr_reg1;\n           diff_pntr_pe_reg2  <= #`TCQ diff_pntr_pe_reg1;\n\n           // Add 1 to the difference pointer value when only write happens.\n           if (write_only)  \n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;\n           else\n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;\n\n           // Add 1 to the difference pointer value when write or both write & read or no write & read happen.\n           if (read_only)  \n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;\n           else\n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;\n         end\n       end\n     end\n   assign diff_pntr_pe = diff_pntr_pe_reg1;\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow\n\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym\n    assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};\n    assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         diff_pntr_pe_asym    <= 0;\n         diff_pntr_reg1       <= 0;\n         full_reg             <= 0;\n         rst_full_ff_reg1     <= 1;\n         rst_full_ff_reg2     <= 1;\n         diff_pntr_pe_reg1    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_wrst_busy)\n           diff_pntr_reg1     <= #`TCQ 0;\n          if (srst_rrst_busy)\n           full_reg             <=  #`TCQ 0;\n           rst_full_ff_reg1     <=  #`TCQ 1;\n           rst_full_ff_reg2     <=  #`TCQ 1;\n           diff_pntr_pe_asym    <=  #`TCQ 0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n         end else begin\n             diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;\n             full_reg          <= #`TCQ full_i;\n             rst_full_ff_reg1  <=  #`TCQ RST_FULL_FF;\n             rst_full_ff_reg2  <=  #`TCQ rst_full_ff_reg1;\n           if (~full_i) begin  \n             diff_pntr_reg1 <=  #`TCQ wr_pntr - adj_rd_pntr_wr;\n          end\n         end\n       end\n     end\n   assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));\n   assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow_asym\n\n\n   //-----------------------------------------------------------------------------\n   // Generate FULL flag\n   //-----------------------------------------------------------------------------\n   wire                 comp0;\n   wire                 comp1;\n   wire                 going_full;\n   wire                 leaving_full;\n \n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin :  gpad \t\n    assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;\n    assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin :  gtrim \n    assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n  end endgenerate\n\n   assign comp1         = (adj_rd_pntr_wr == (wr_pntr + 1'b1));\n   assign comp0         = (adj_rd_pntr_wr == wr_pntr);\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp\n     assign going_full    = (comp1 & write_allow & ~read_allow);\n     assign leaving_full  = (comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym\n      assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp \n      assign going_full = (comp1 & write_allow & ~read_allow);\n      assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n\n   assign ram_full_comb = going_full | (~leaving_full & full_i);\n\n   generate if (C_HAS_RST == 1) begin : grst_full\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF & C_HAS_RST)\n         full_i   <= C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_SRST == 1) begin : gsrst_full\n     always @(posedge CLK) begin\n       if (srst_wrst_busy)\n         full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_full\n     always @(posedge CLK) begin\n         full_i   <= #`TCQ ram_full_comb;\n     end\n   end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate EMPTY flag\n   //-----------------------------------------------------------------------------\n   wire                 ecomp0;\n   wire                 ecomp1;\n   wire                 going_empty;\n   wire                 leaving_empty;\n   wire                 ram_empty_comb;\n\n  \n generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin :  pad \t\n    assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n    assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin :  trim \n    assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n  end endgenerate\n\n   assign ecomp1         = (adj_wr_pntr_rd == (rd_pntr + 1'b1));\n   assign ecomp0         = (adj_wr_pntr_rd == rd_pntr);\n\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp\n     assign going_empty    = (ecomp1 & ~write_allow & read_allow);\n     assign leaving_empty  = (ecomp0 & write_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp\n      assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp \n      assign going_empty = (ecomp1 & ~write_allow & read_allow);\n      assign leaving_empty =(ecomp0 & write_allow);\n    end endgenerate\n\n\n\n    assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);\n\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       empty_i  <= 1'b1;\n     else if (srst_rrst_busy)\n       empty_i  <= #`TCQ 1'b1;\n     else\n       empty_i  <= #`TCQ ram_empty_comb;\n    end\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       EMPTY_FB     <= 1'b1;\n     end else begin\n       if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))\n         EMPTY_FB   <= #`TCQ 1'b1;\n       else\n         EMPTY_FB   <= #`TCQ ram_empty_comb;\n     end\n   end // always\n\n   //-----------------------------------------------------------------------------\n   // Generate Read and write data counts for asymmetic common clock\n   //-----------------------------------------------------------------------------\n\n    reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; \n    wire [C_GRTR_PNTR_WIDTH :0] ratio; \n    wire decr_by_one;\n    wire incr_by_ratio;\n    wire incr_by_one;\n    wire decr_by_ratio;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n\n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr \n      assign ratio         = C_DEPTH_RATIO_RD;\n      assign decr_by_one   = (IS_FWFT == 1)? read_allow_dc : read_allow;\n      assign incr_by_ratio = write_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (decr_by_one) begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc - 1;\n           else\n\t    count_dc <= #`TCQ count_dc - 1  + ratio ;\n\t end\n\t else begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc + ratio ;\n\tend\n       end\n       end\n\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n\n    end endgenerate\n\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd \n      assign ratio         = C_DEPTH_RATIO_WR;\n      assign incr_by_one   = write_allow;\n      assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (incr_by_one) begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc + 1;\n           else\n\t    count_dc <= #`TCQ count_dc + 1  - ratio ;\n\t end\n\t else begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc - ratio ;\n\tend\n       end\n       end\n\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n\n    end endgenerate\n\n\n\n\n\n\n   //-----------------------------------------------------------------------------\n   // Generate WR_ACK flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_wr_ack  <= 1'b0;\n     else if (srst_wrst_busy)\n       ideal_wr_ack  <= #`TCQ 1'b0;\n     else if (WR_EN & ~full_i)\n       ideal_wr_ack  <= #`TCQ 1'b1;\n     else\n       ideal_wr_ack  <= #`TCQ 1'b0;\n    end\n\n   //-----------------------------------------------------------------------------\n   // Generate VALID flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_valid  <= 1'b0;\n     else if (srst_rrst_busy)\n       ideal_valid  <= #`TCQ 1'b0;\n     else if (RD_EN & ~empty_i)\n       ideal_valid  <= #`TCQ 1'b1;\n     else\n       ideal_valid  <= #`TCQ 1'b0;\n    end\n\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_FULL flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss\n\n     wire                 fcomp2;\n     wire                 going_afull;\n     wire                 leaving_afull;\n     wire                 ram_afull_comb;\n\n\n   assign fcomp2         = (adj_rd_pntr_wr == (wr_pntr + 2'h2));\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp\n     assign going_afull    = (fcomp2 & write_allow & ~read_allow);\n     assign leaving_afull  = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym\n      assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp \n      assign going_afull = (fcomp2 & write_allow & ~read_allow);\n      assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n     assign ram_afull_comb  = going_afull | (~leaving_afull & almost_full_i);\n\n\n    generate if (C_HAS_RST == 1) begin : grst_afull\n      always @(posedge CLK or posedge RST_FULL_FF) begin\n        if (RST_FULL_FF & C_HAS_RST)\n          almost_full_i   <= C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_SRST == 1) begin : gsrst_afull\n      always @(posedge CLK) begin\n        if (srst_wrst_busy)\n          almost_full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_afull\n      always @(posedge CLK) begin\n          almost_full_i   <= #`TCQ ram_afull_comb;\n      end\n    end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_EMPTY flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss\n\n     wire                 ecomp2;\n     wire                 going_aempty;\n     wire                 leaving_aempty;\n     wire                 ram_aempty_comb;\n      \n     assign ecomp2          = (adj_wr_pntr_rd == (rd_pntr + 2'h2));\n   \n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp\n     assign going_aempty    = (ecomp2 & ~write_allow & read_allow);\n     assign leaving_aempty  = (ecomp1 & write_allow & ~read_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp\n      assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp \n      assign going_aempty = (ecomp2 & ~write_allow & read_allow);\n      assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);\n    end endgenerate\n\n\n     assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);\n\n     always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         almost_empty_i  <= 1'b1;\n       else if (srst_rrst_busy)\n         almost_empty_i  <= #`TCQ 1'b1;\n       else\n         almost_empty_i  <= #`TCQ ram_aempty_comb;\n      end\n  // end endgenerate // gae_ss\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL\n   //-----------------------------------------------------------------------------\n\n   localparam  C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT \n                                  C_PROG_FULL_THRESH_ASSERT_VAL; // STD\n   localparam  C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT\n                                  C_PROG_FULL_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;   \n   generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin \n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n          prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr>= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  ((diff_pntr) < C_PF_ASSERT_VAL )\n        prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate // single_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr >= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n       else if  (diff_pntr < C_PF_NEGATE_VAL)\n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate //multiple_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT\n                                               PROG_FULL_THRESH; // STD\n   generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input\n\n     always @(posedge CLK or posedge RST_FULL_FF) begin//0\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin //1\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin//2 \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin//3\n           if (diff_pntr > pf3_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if (diff_pntr == pf3_assert_val) begin//4\n             if (read_only_q)\n               prog_full_i <= #`TCQ 1'b0;\n             else\n               prog_full_i <= #`TCQ 1'b1;\n           end else//4\n             prog_full_i <= #`TCQ 1'b0;\n         end else//3\n           prog_full_i <= #`TCQ prog_full_i;\n       end //2\n       else begin//5\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin//6 \n        if (diff_pntr >= pf3_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  (diff_pntr < pf3_assert_val) begin//7\n         prog_full_i <= #`TCQ 1'b0;\n       end//7\n       end//6\n      else\n           prog_full_i <= #`TCQ prog_full_i;\n       end//5\n     end//1\n     end//0\n   end endgenerate //single_pf_input\n  \n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_ASSERT; // STD\n   wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_NEGATE; // STD\n\n   generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin\n           if (diff_pntr >= pf_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if ((diff_pntr == pf_negate_val && read_only_q) ||\n                  diff_pntr < pf_negate_val)\n             prog_full_i <= #`TCQ 1'b0;\n           else\n             prog_full_i <= #`TCQ prog_full_i;\n         end else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin \n        if (diff_pntr >= pf_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n       else if (diff_pntr < pf_negate_val) \n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n\n     end\n   end\n   end endgenerate //multiple_pf_inputs\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY\n   //-----------------------------------------------------------------------------\n   localparam  C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD\n   localparam  C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i) \n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy) \n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL)\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > C_PE_ASSERT_VAL)\n         prog_empty_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n     end\n     end\n   end endgenerate // single_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > C_PE_NEGATE_VAL) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n\n     end\n\n     end\n   end endgenerate //multiple_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH -2) : // FWFT\n                                                PROG_EMPTY_THRESH; // STD\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe < pe3_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (diff_pntr_pe == pe3_assert_val) begin\n             if (write_only_q)\n               prog_empty_i <= #`TCQ 1'b0;\n             else\n               prog_empty_i <= #`TCQ 1'b1;\n           end else\n             prog_empty_i <= #`TCQ 1'b0;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe3_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > pe3_assert_val)\n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n\n     end\n   end endgenerate // single_pe_input\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_ASSERT; // STD\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_NEGATE; // STD\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n      else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe <= pe4_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || \n                     (diff_pntr_pe > pe4_negate_val)) begin\n             prog_empty_i <= #`TCQ 1'b0;\n           end else\n             prog_empty_i <= #`TCQ prog_empty_i;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe4_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > pe4_negate_val) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n     end\n   end endgenerate // multiple_pe_inputs\n\nendmodule // fifo_generator_v13_2_1_bhv_ver_ss\n\n\n\n/**************************************************************************\n * First-Word Fall-Through module (preload 0)\n **************************************************************************/\nmodule fifo_generator_v13_2_1_bhv_ver_preload0\n  #(\n    parameter  C_DOUT_RST_VAL            = \"\",\n    parameter  C_DOUT_WIDTH              = 8,\n    parameter  C_HAS_RST                 = 0,\n    parameter  C_ENABLE_RST_SYNC         = 0,\n    parameter  C_HAS_SRST                = 0,\n    parameter  C_USE_EMBEDDED_REG        = 0,\n    parameter  C_EN_SAFETY_CKT           = 0, \n    parameter  C_USE_DOUT_RST            = 0,\n    parameter  C_USE_ECC                 = 0,\n    parameter  C_USERVALID_LOW           = 0,\n    parameter  C_USERUNDERFLOW_LOW       = 0,\n    parameter  C_MEMORY_TYPE             = 0,\n    parameter  C_FIFO_TYPE               = 0\n  )\n  (\n    //Inputs\n    input                          SAFETY_CKT_RD_RST,\n    input                          RD_CLK,\n    input                          RD_RST,\n    input                          SRST,\n    input                          WR_RST_BUSY,\n    input                          RD_RST_BUSY,\n    input                          RD_EN,\n    input                          FIFOEMPTY,\n    input       [C_DOUT_WIDTH-1:0] FIFODATA,\n    input                          FIFOSBITERR,\n    input                          FIFODBITERR,\n   \n    //Outputs\n    output reg  [C_DOUT_WIDTH-1:0] USERDATA,\n    output                         USERVALID,\n    output                         USERUNDERFLOW,\n    output                         USEREMPTY,\n    output                         USERALMOSTEMPTY,\n    output                         RAMVALID,\n    output                         FIFORDEN,\n    output reg                     USERSBITERR,\n    output reg                     USERDBITERR,\n    output reg                     STAGE2_REG_EN,\n    output                         fab_read_data_valid_i_o,\n    output                         read_data_valid_i_o,\n    output                         ram_valid_i_o,\n    output      [1:0]              VALID_STAGES \n  );\n //Internal signals\n wire                      preloadstage1;\n wire                      preloadstage2;\n reg                       ram_valid_i;\n reg                       fab_valid;\n reg                       read_data_valid_i;\n reg                       fab_read_data_valid_i;\n reg                       fab_read_data_valid_i_1;\n reg                       ram_valid_i_d;\n reg                       read_data_valid_i_d;\n reg                       fab_read_data_valid_i_d;\n wire                      ram_regout_en;\n reg                       ram_regout_en_d1;\n reg                       ram_regout_en_d2;\n wire                      fab_regout_en;\n wire                      ram_rd_en;\n reg                       empty_i        = 1'b1;\n reg                       empty_sckt     = 1'b1;\n reg                       sckt_rrst_q    = 1'b0;\n reg                       sckt_rrst_done = 1'b0;\n reg                       empty_q        = 1'b1;\n reg                       rd_en_q        = 1'b0;\n reg                       almost_empty_i = 1'b1;\n reg                       almost_empty_q = 1'b1;\n wire                      rd_rst_i;\n wire                      srst_i;\n reg  [C_DOUT_WIDTH-1:0]   userdata_both;\n wire                      uservalid_both;\n wire                      uservalid_one;\n reg                       user_sbiterr_both = 1'b0;\n reg                       user_dbiterr_both = 1'b0;\n  \nassign ram_valid_i_o = ram_valid_i;\nassign read_data_valid_i_o = read_data_valid_i;\nassign fab_read_data_valid_i_o = fab_read_data_valid_i; \n\n\n\n/*************************************************************************\n* FUNCTIONS\n*************************************************************************/\n\n   /*************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***********************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n   \n   //*************************************************************************\n   //  Set power-on states for regs\n   //*************************************************************************\n   initial begin\n      ram_valid_i       = 1'b0;\n      fab_valid         = 1'b0;\n      read_data_valid_i = 1'b0;\n      fab_read_data_valid_i = 1'b0;\n      fab_read_data_valid_i_1 = 1'b0;\n      USERDATA          = hexstr_conv(C_DOUT_RST_VAL);\n      userdata_both          = hexstr_conv(C_DOUT_RST_VAL);\n      USERSBITERR       = 1'b0;\n      USERDBITERR       = 1'b0;\n      user_sbiterr_both = 1'b0;\n      user_dbiterr_both = 1'b0;\n   end //initial\n\n   //***************************************************************************\n   //  connect up optional reset\n   //***************************************************************************\n   assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;\n   assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;\n\n   reg  sckt_rd_rst_fwft = 1'b0;\n   reg  fwft_rst_done_i  = 1'b0;\n   wire fwft_rst_done;\n   assign fwft_rst_done = 1'b1;//C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;\n   always @ (posedge RD_CLK) begin\n     sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;\n   end\n\n   always @ (posedge rd_rst_i or posedge RD_CLK) begin\n     if (rd_rst_i)\n       fwft_rst_done_i  <= 1'b0;\n     else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)\n       fwft_rst_done_i  <= #`TCQ 1'b1;\n   end\n\n   localparam INVALID             = 0;\n   localparam STAGE1_VALID        = 2;\n   localparam STAGE2_VALID        = 1;\n   localparam BOTH_STAGES_VALID   = 3;\n\n   reg  [1:0] curr_fwft_state = INVALID;\n   reg  [1:0] next_fwft_state = INVALID;\n\n\ngenerate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin\n         always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n \n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n     \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n    \n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = preloadstage2;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;\n   end\nendgenerate // gnll_fifo\n\n   reg curr_state         = 0;\n   reg next_state         = 0;\n   reg leaving_empty_fwft = 0;\n   reg going_empty_fwft   = 0;\n   reg empty_i_q          = 0;\n   reg ram_rd_en_fwft     = 0;\n   generate if (C_FIFO_TYPE == 2) begin : gll_fifo\n     always @* begin // FSM fo FWFT\n       case (curr_state)\n         1'b0: begin\n           if (~FIFOEMPTY)\n             next_state <= 1'b1;\n           else\n             next_state <= 1'b0;\n           end\n         1'b1: begin\n           if (FIFOEMPTY && RD_EN)\n             next_state <= 1'b0;\n           else\n             next_state <= 1'b1;\n           end\n         default: next_state <= 1'b0;\n       endcase\n     end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_i       <= 1'b1;\n           empty_i_q     <= 1'b1;\n           ram_valid_i   <= 1'b0;\n        end else if (srst_i) begin\n           empty_i       <= #`TCQ 1'b1;\n           empty_i_q     <= #`TCQ 1'b1;\n           ram_valid_i   <= #`TCQ 1'b0;\n        end else begin\n           empty_i       <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);\n           empty_i_q     <= #`TCQ FIFOEMPTY;\n           ram_valid_i   <= #`TCQ next_state;\n        end\n     end //always\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n           curr_state    <= 1'b0;\n        end else if (srst_i) begin\n           curr_state    <= #`TCQ 1'b0;\n        end else begin\n           curr_state    <= #`TCQ next_state;\n        end\n     end //always\n\n     wire                  fe_of_empty; \n     assign fe_of_empty   = empty_i_q & ~FIFOEMPTY;\n\n     always @* begin // Finding leaving empty\n       case (curr_state)\n         1'b0:    leaving_empty_fwft <= fe_of_empty;\n         1'b1:    leaving_empty_fwft <= 1'b1;\n         default: leaving_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Finding going empty\n       case (curr_state)\n         1'b1:    going_empty_fwft <= FIFOEMPTY & RD_EN;\n         default: going_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Generating FWFT rd_en\n       case (curr_state)\n         1'b0:    ram_rd_en_fwft <= ~FIFOEMPTY;\n         1'b1:    ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;\n         default: ram_rd_en_fwft <= 1'b0;\n       endcase\n     end\n\n     assign ram_regout_en = ram_rd_en_fwft;\n     //assign ram_regout_en_d1 = ram_rd_en_fwft;\n     //assign ram_regout_en_d2 = ram_rd_en_fwft;\n     assign ram_rd_en     = ram_rd_en_fwft;\n   end endgenerate // gll_fifo\n\n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false.\n   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n   generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           ram_valid_i     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              ram_valid_i     <= #`TCQ 1'b0;\n           end else begin\n              if (ram_rd_en == 1'b1) begin\n                 ram_valid_i   <= #`TCQ 1'b1;\n              end else begin\n                 if (ram_regout_en == 1'b1)\n                   ram_valid_i <= #`TCQ 1'b0;\n                 else\n                   ram_valid_i <= #`TCQ ram_valid_i;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_ram_valid\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n  \n generate if(C_USE_EMBEDDED_REG < 3) begin\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else\n        read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);\n   end //always\nend \nendgenerate\n\n   \n   \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n generate if ( C_USE_EMBEDDED_REG < 3) begin\n  always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin         // asynchronous reset (active high)\n             almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ FIFOEMPTY;\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n   \n   \n     \n  // BRAM resets synchronously\n generate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin\n   always @ ( posedge rd_rst_i)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n           @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n             USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end  else if (fwft_rst_done) begin\n            if (ram_regout_en) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end\n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n//safety ckt with one register\ngenerate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n            @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n        end\n     end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n          //@(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end \n       end\n        else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n            //  @(posedge RD_CLK)\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end else if (fwft_rst_done) begin\n            if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end          \n          end\n        end\n       end //always\n  end //if\nendgenerate\n\n\ngenerate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin\n         \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d1 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d1 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d1 <= #`TCQ ram_regout_en;\n                 end\n            end //always\n   //  assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));\n       assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d2 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d2 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;\n                 end\n            end //always\n\n    \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n     always @ (posedge RD_CLK) begin\n        ram_valid_i_d <= #`TCQ ram_valid_i;\n        read_data_valid_i_d <= #`TCQ read_data_valid_i;\n        fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;\n\n     end\n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n    \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;\n   end\n   endgenerate // gnll_fifo\n\n   \n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n     generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid\n\n     \n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           fab_valid     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              fab_valid    <= #`TCQ 1'b0;\n           end else begin\n              if (ram_regout_en == 1'b1) begin\n                 fab_valid  <= #`TCQ 1'b1;\n              end else begin\n                 if (fab_regout_en == 1'b1)\n                   fab_valid <= #`TCQ 1'b0;\n                 else\n                   fab_valid <= #`TCQ fab_valid;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_fab_valid\n\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n    generate if(C_USE_EMBEDDED_REG == 3) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else begin\n        if (ram_regout_en == 1'b1) begin\n          read_data_valid_i <= #`TCQ 1'b1;\n        end else begin\n         if (fab_regout_en == 1'b1)\n          read_data_valid_i <= #`TCQ 1'b0;\n        else\n          read_data_valid_i <= #`TCQ read_data_valid_i;\n        end \n      end \n   end //always\nend\nendgenerate\n\n//generate if(C_USE_EMBEDDED_REG == 3) begin\n//   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n//      if (rd_rst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//      else if (srst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//\n//      if (ram_regout_en == 1'b1) begin\n//        fab_read_data_valid_i <= #`TCQ 1'b0;\n//      end else begin\n//       if (fab_regout_en == 1'b1)\n//        fab_read_data_valid_i <= #`TCQ 1'b1;\n//      else\n//        fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;\n//      end \n//   end //always\n//end\n//endgenerate\n\n     generate if(C_USE_EMBEDDED_REG == 3 ) begin \n    always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid\n      if (rd_rst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else \n        fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);\n   end //always\nend\nendgenerate\n \nalways @ (posedge RD_CLK ) begin : proc_del1\n             begin\n                 fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;\n              end\n            end //always\n \n \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty_both\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n   reg FIFOEMPTY_1;\n   generate if (C_USE_EMBEDDED_REG == 3 ) begin\n    always @(posedge RD_CLK) begin\n            FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;\n           end\n    end\nendgenerate\n    generate if (C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n   begin\n      if (rd_rst_i) begin         // asynchronous reset (active high)\n           almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ (~ram_valid_i);\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_sckt <= #`TCQ 1'b1;\n           sckt_rrst_q <= #`TCQ 1'b0;\n           sckt_rrst_done <= #`TCQ 1'b0;\n        end else begin\n           sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;\n           if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin\n              sckt_rrst_done <= #`TCQ 1'b1;\n           end else if (sckt_rrst_done) begin\n              // rising clock edge\n              empty_sckt <= #`TCQ 1'b0;\n           end\n        end\n     end //always\n   \n   \n//   assign USEREMPTY       = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;\n   assign USEREMPTY       = empty_i;\n   assign USERALMOSTEMPTY = almost_empty_i;\n   assign FIFORDEN        = ram_rd_en;\n   assign RAMVALID        = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;\n   assign uservalid_both       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3)  ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);\n   assign uservalid_one       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3)  ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);\n   assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;\n   assign USERUNDERFLOW   = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;\n//no safety ckt with both reg\ngenerate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n            USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              userdata_both   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end else begin\n            if (fwft_rst_done) begin\n              if (ram_regout_en) begin\n                 userdata_both     <= #`TCQ FIFODATA; \n                 user_dbiterr_both <= #`TCQ FIFODBITERR;\n                 user_sbiterr_both <= #`TCQ FIFOSBITERR; \n              end\n              if (fab_regout_en) begin\n                 USERDATA     <= #`TCQ userdata_both;\n                 USERDBITERR  <= #`TCQ user_dbiterr_both;\n                 USERSBITERR  <= #`TCQ user_sbiterr_both; \n              end             \n            end             \n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n\n//safety_ckt with both registers\n generate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always @ (posedge RD_CLK) begin\n          if (rd_rst_i || srst_i) begin\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n              @(posedge RD_CLK)\n              USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n               userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end\n        end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n     if (rd_rst_i) begin //asynchronous reset (active high)\n       if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n         USERSBITERR       <= #`TCQ 0;\n         USERDBITERR       <= #`TCQ 0;\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end\n       // DRAM resets asynchronously\n       if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n         USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end \n     end else begin // rising clock edge\n       if (srst_i) begin\n         if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n           USERSBITERR       <= #`TCQ 0;\n           USERDBITERR       <= #`TCQ 0;\n           user_sbiterr_both <= #`TCQ 0;\n           user_dbiterr_both <= #`TCQ 0;\n         end\n         if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n           USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end\n       end else if (fwft_rst_done) begin\n         if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            userdata_both     <= #`TCQ FIFODATA;\n            user_dbiterr_both <= #`TCQ FIFODBITERR;\n            user_sbiterr_both <= #`TCQ FIFOSBITERR; \n         end\n         if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            USERDATA          <= #`TCQ userdata_both;\n            USERDBITERR       <= #`TCQ user_dbiterr_both;\n            USERSBITERR       <= #`TCQ user_sbiterr_both;\n         end\n       end\n     end\n   end //always\n  end //if\nendgenerate\n\nendmodule //fifo_generator_v13_2_1_bhv_ver_preload0\n\n\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Register one AXI channel on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   reg_slice\n//\n//--------------------------------------------------------------------------\n\nmodule fifo_generator_v13_2_1_axic_reg_slice #\n  (\n   parameter C_FAMILY     = \"virtex7\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   )\n  (\n   // System Signals\n   input  wire                      ACLK,\n   input  wire                      ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0]   S_PAYLOAD_DATA,\n   input  wire                      S_VALID,\n   output wire                      S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0]   M_PAYLOAD_DATA,\n   output wire                      M_VALID,\n   input  wire                      M_READY\n   );\n\n  localparam RST_SYNC_STAGES = 5;\n  localparam RST_BUSY_LEN    = 6;\n  reg [1:0] arst_sync_wr  = 2'b11;\n  reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n  wire sync_reset;\n  wire extnd_reset;\n\n\n  always @(posedge ARESET or posedge ACLK) begin\n    if (ARESET)\n      arst_sync_wr <= 2'b11;\n    else\n      arst_sync_wr <= #`TCQ {arst_sync_wr[0], 1'b0};\n  end\n\n  always @(posedge ACLK) begin\n    sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[1]};\n  end\n\n  assign sync_reset     = |sckt_wr_rst_cc[RST_BUSY_LEN-5:0] | arst_sync_wr[1]; \n  assign extnd_reset    = |sckt_wr_rst_cc | arst_sync_wr[1];\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000)\n    begin\n      reg [1:0] state;\n      localparam [1:0] \n        ZERO = 2'b10,\n        ONE  = 2'b11,\n        TWO  = 2'b01;\n      \n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg [C_DATA_WIDTH-1:0] storage_data2 = 0;\n      reg                    load_s1;\n      wire                   load_s2;\n      wire                   load_s1_from_s2;\n      reg                    s_ready_i; //local signal of output\n      wire                   m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with either slave side data or from storage2\n      always @(posedge ACLK) \n      begin\n        if (load_s1)\n          if (load_s1_from_s2)\n            storage_data1 <= storage_data2;\n          else\n            storage_data1 <= S_PAYLOAD_DATA;        \n      end\n\n      // Load storage2 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data1;\n\n      // Always load s2 on a valid transaction even if it's unnecessary\n      assign load_s2 = S_VALID & s_ready_i;\n\n      // Loading s1\n      always @ *\n      begin\n        if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction\n             // Load when ONE if we both have read and write at the same time\n             ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||\n             // Load when TWO and we have a transaction on Master side\n             ((state == TWO) && (M_READY == 1)))\n          load_s1 = 1'b1;\n        else\n          load_s1 = 1'b0;\n      end // always @ *\n\n      assign load_s1_from_s2 = (state == TWO);\n                       \n      // State Machine for handling output signals\n      always @(posedge ACLK) begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          state <= ZERO;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          case (state)\n            // No transaction stored locally\n            ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE\n\n            // One transaction stored locally\n            ONE: begin\n              if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO\n              if (~M_READY & S_VALID) begin\n                state <= TWO;  // Got another one so move to TWO\n                s_ready_i <= 1'b0;\n              end\n            end\n\n            // TWO transaction stored locally\n            TWO: if (M_READY) begin\n              state <= ONE; // Read out one so move to ONE\n              s_ready_i <= 1'b1;\n            end\n          endcase // case (state)\n        end\n      end // always @ (posedge ACLK)\n      \n      assign m_valid_i = state[0];\n\n    end // if (C_REG_CONFIG == 1)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000001)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg                    s_ready_i; //local signal of output\n      reg                    m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b0;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else if (m_valid_i & M_READY) begin\n          s_ready_i <= 1'b1;\n          m_valid_i <= 1'b0;\n        end else if (S_VALID & s_ready_i) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b1;\n        end\n        if (~m_valid_i) begin\n          storage_data1 <= S_PAYLOAD_DATA;        \n        end\n      end\n      assign M_PAYLOAD_DATA = storage_data1;\n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // reg_slice\n", "num_lines": 10519}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Generic single-channel AXI FIFO\n// Synchronous FIFO is implemented using either LUTs (SRL) or BRAM.\n// Transfers received on the AXI slave port are pushed onto the FIFO.\n// FIFO output, when available, is presented on the AXI master port and\n//   popped when the master port responds (M_READY).\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n// Structure:\n//   axic_fifo\n//     fifo_gen\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_14_axic_fifo #\n  (\n   parameter         C_FAMILY          = \"virtex6\",\n   parameter integer C_FIFO_DEPTH_LOG  = 5,      // FIFO depth = 2**C_FIFO_DEPTH_LOG\n                                                 // Range = [5:9] when TYPE=\"lut\",\n                                                 // Range = [5:12] when TYPE=\"bram\",\n   parameter integer C_FIFO_WIDTH      = 64,     // Width of payload [1:512]\n   parameter         C_FIFO_TYPE       = \"lut\"   // \"lut\" = LUT (SRL) based,\n                                                 // \"bram\" = BRAM based\n   )\n  (\n   // Global inputs\n   input  wire                        ACLK,    // Clock\n   input  wire                        ARESET,  // Reset\n   // Slave  Port\n   input  wire [C_FIFO_WIDTH-1:0]     S_MESG,  // Payload (may be any set of channel signals)\n   input  wire                        S_VALID, // FIFO push\n   output wire                        S_READY, // FIFO not full\n   // Master  Port\n   output wire [C_FIFO_WIDTH-1:0]     M_MESG,  // Payload\n   output wire                        M_VALID, // FIFO not empty\n   input  wire                        M_READY  // FIFO pop\n   );\n\n   axi_data_fifo_v2_1_14_fifo_gen #(\n     .C_FAMILY(C_FAMILY),\n     .C_COMMON_CLOCK(1),\n     .C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),\n     .C_FIFO_WIDTH(C_FIFO_WIDTH),\n     .C_FIFO_TYPE(C_FIFO_TYPE))\n   inst (\n     .clk(ACLK),\n     .rst(ARESET),\n     .wr_clk(1'b0),\n     .wr_en(S_VALID),\n     .wr_ready(S_READY),\n     .wr_data(S_MESG),\n     .rd_clk(1'b0),\n     .rd_en(M_READY),\n     .rd_valid(M_VALID),\n     .rd_data(M_MESG));\n\nendmodule\n\n\n// -- (c) Copyright 1995 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------\n\n// The synthesis directives \"translate_off/translate_on\" specified below are\n// supported by Xilinx, Mentor Graphics and Synplicity synthesis\n// tools. Ensure they are correct for your synthesis tool(s).\n\n// You must compile the fifo_generator wrapper file when simulating\n// the core. When compiling the wrapper file, be sure to\n// reference the XilinxCoreLib Verilog simulation library. For detailed\n// instructions, please refer to the \"CORE Generator Help\".\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_14_fifo_gen #(\nparameter C_FAMILY          = \"virtex7\",\nparameter integer C_COMMON_CLOCK    = 1,\nparameter integer C_SYNCHRONIZER_STAGE = 3,\nparameter integer C_FIFO_DEPTH_LOG  = 5,\nparameter integer C_FIFO_WIDTH      = 64,\nparameter C_FIFO_TYPE       = \"lut\"\n)(\n  clk,\n  rst,\n  wr_clk,\n  wr_en,\n  wr_ready,\n  wr_data,\n  rd_clk,\n  rd_en,\n  rd_valid,\n  rd_data);\n\ninput clk;\ninput wr_clk;\ninput rd_clk;\ninput rst;\ninput [C_FIFO_WIDTH-1 : 0] wr_data;\ninput wr_en;\ninput rd_en;\noutput [C_FIFO_WIDTH-1 : 0] rd_data;\noutput wr_ready;\noutput rd_valid;\n\nwire  full;\nwire  empty;\nwire  rd_valid = ~empty;\nwire  wr_ready = ~full;\n\nlocalparam C_MEMORY_TYPE =  (C_FIFO_TYPE == \"bram\")? 1 : 2;\n\nlocalparam C_IMPLEMENTATION_TYPE = (C_COMMON_CLOCK == 1)? 0 : 2;\n\n  fifo_generator_v13_2_1 #(\n    .C_COMMON_CLOCK(C_COMMON_CLOCK),\n    .C_DIN_WIDTH(C_FIFO_WIDTH),\n    .C_DOUT_WIDTH(C_FIFO_WIDTH),\n    .C_FAMILY(C_FAMILY),\n    .C_IMPLEMENTATION_TYPE(C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE(C_MEMORY_TYPE),\n    .C_RD_DEPTH(1<<C_FIFO_DEPTH_LOG),\n    .C_RD_PNTR_WIDTH(C_FIFO_DEPTH_LOG),\n    .C_WR_DEPTH(1<<C_FIFO_DEPTH_LOG),\n    .C_WR_PNTR_WIDTH(C_FIFO_DEPTH_LOG),\n    .C_ADD_NGC_CONSTRAINT(0),\n    .C_APPLICATION_TYPE_AXIS(0),\n    .C_APPLICATION_TYPE_RACH(0),\n    .C_APPLICATION_TYPE_RDCH(0),\n    .C_APPLICATION_TYPE_WACH(0),\n    .C_APPLICATION_TYPE_WDCH(0),\n    .C_APPLICATION_TYPE_WRCH(0),\n    .C_AXIS_TDATA_WIDTH(64),\n    .C_AXIS_TDEST_WIDTH(4),\n    .C_AXIS_TID_WIDTH(8),\n    .C_AXIS_TKEEP_WIDTH(4),\n    .C_AXIS_TSTRB_WIDTH(4),\n    .C_AXIS_TUSER_WIDTH(4),\n    .C_AXIS_TYPE(0),\n    .C_AXI_ADDR_WIDTH(32),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_AXI_DATA_WIDTH(64),\n    .C_AXI_ID_WIDTH(4),\n    .C_AXI_LEN_WIDTH(8),\n    .C_AXI_LOCK_WIDTH(2),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_TYPE(0),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_COUNT_TYPE(0),\n    .C_DATA_COUNT_WIDTH(6),\n    .C_DEFAULT_VALUE(\"BlankString\"),\n    .C_DIN_WIDTH_AXIS(1),\n    .C_DIN_WIDTH_RACH(32),\n    .C_DIN_WIDTH_RDCH(64),\n    .C_DIN_WIDTH_WACH(32),\n    .C_DIN_WIDTH_WDCH(64),\n    .C_DIN_WIDTH_WRCH(2),\n    .C_DOUT_RST_VAL(\"0\"),\n    .C_ENABLE_RLOCS(0),\n    .C_ENABLE_RST_SYNC(1),\n    .C_ERROR_INJECTION_TYPE(0),\n    .C_ERROR_INJECTION_TYPE_AXIS(0),\n    .C_ERROR_INJECTION_TYPE_RACH(0),\n    .C_ERROR_INJECTION_TYPE_RDCH(0),\n    .C_ERROR_INJECTION_TYPE_WACH(0),\n    .C_ERROR_INJECTION_TYPE_WDCH(0),\n    .C_ERROR_INJECTION_TYPE_WRCH(0),\n    .C_FULL_FLAGS_RST_VAL(0),\n    .C_HAS_ALMOST_EMPTY(0),\n    .C_HAS_ALMOST_FULL(0),\n    .C_HAS_AXIS_TDATA(0),\n    .C_HAS_AXIS_TDEST(0),\n    .C_HAS_AXIS_TID(0),\n    .C_HAS_AXIS_TKEEP(0),\n    .C_HAS_AXIS_TLAST(0),\n    .C_HAS_AXIS_TREADY(1),\n    .C_HAS_AXIS_TSTRB(0),\n    .C_HAS_AXIS_TUSER(0),\n    .C_HAS_AXI_ARUSER(0),\n    .C_HAS_AXI_AWUSER(0),\n    .C_HAS_AXI_BUSER(0),\n    .C_HAS_AXI_RD_CHANNEL(0),\n    .C_HAS_AXI_RUSER(0),\n    .C_HAS_AXI_WR_CHANNEL(0),\n    .C_HAS_AXI_WUSER(0),\n    .C_HAS_BACKUP(0),\n    .C_HAS_DATA_COUNT(0),\n    .C_HAS_DATA_COUNTS_AXIS(0),\n    .C_HAS_DATA_COUNTS_RACH(0),\n    .C_HAS_DATA_COUNTS_RDCH(0),\n    .C_HAS_DATA_COUNTS_WACH(0),\n    .C_HAS_DATA_COUNTS_WDCH(0),\n    .C_HAS_DATA_COUNTS_WRCH(0),\n    .C_HAS_INT_CLK(0),\n    .C_HAS_MASTER_CE(0),\n    .C_HAS_MEMINIT_FILE(0),\n    .C_HAS_OVERFLOW(0),\n    .C_HAS_PROG_FLAGS_AXIS(0),\n    .C_HAS_PROG_FLAGS_RACH(0),\n    .C_HAS_PROG_FLAGS_RDCH(0),\n    .C_HAS_PROG_FLAGS_WACH(0),\n    .C_HAS_PROG_FLAGS_WDCH(0),\n    .C_HAS_PROG_FLAGS_WRCH(0),\n    .C_HAS_RD_DATA_COUNT(0),\n    .C_HAS_RD_RST(0),\n    .C_HAS_RST(1),\n    .C_HAS_SLAVE_CE(0),\n    .C_HAS_SRST(0),\n    .C_HAS_UNDERFLOW(0),\n    .C_HAS_VALID(0),\n    .C_HAS_WR_ACK(0),\n    .C_HAS_WR_DATA_COUNT(0),\n    .C_HAS_WR_RST(0),\n    .C_IMPLEMENTATION_TYPE_AXIS(1),\n    .C_IMPLEMENTATION_TYPE_RACH(1),\n    .C_IMPLEMENTATION_TYPE_RDCH(1),\n    .C_IMPLEMENTATION_TYPE_WACH(1),\n    .C_IMPLEMENTATION_TYPE_WDCH(1),\n    .C_IMPLEMENTATION_TYPE_WRCH(1),\n    .C_INIT_WR_PNTR_VAL(0),\n    .C_INTERFACE_TYPE(0),\n    .C_MIF_FILE_NAME(\"BlankString\"),\n    .C_MSGON_VAL(1),\n    .C_OPTIMIZATION_MODE(0),\n    .C_OVERFLOW_LOW(0),\n    .C_PRELOAD_LATENCY(0),\n    .C_PRELOAD_REGS(1),\n    .C_PRIM_FIFO_TYPE(\"512x36\"),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),\n    .C_PROG_EMPTY_TYPE(0),\n    .C_PROG_EMPTY_TYPE_AXIS(0),\n    .C_PROG_EMPTY_TYPE_RACH(0),\n    .C_PROG_EMPTY_TYPE_RDCH(0),\n    .C_PROG_EMPTY_TYPE_WACH(0),\n    .C_PROG_EMPTY_TYPE_WDCH(0),\n    .C_PROG_EMPTY_TYPE_WRCH(0),\n    .C_PROG_FULL_THRESH_ASSERT_VAL(31),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),\n    .C_PROG_FULL_THRESH_NEGATE_VAL(30),\n    .C_PROG_FULL_TYPE(0),\n    .C_PROG_FULL_TYPE_AXIS(0),\n    .C_PROG_FULL_TYPE_RACH(0),\n    .C_PROG_FULL_TYPE_RDCH(0),\n    .C_PROG_FULL_TYPE_WACH(0),\n    .C_PROG_FULL_TYPE_WDCH(0),\n    .C_PROG_FULL_TYPE_WRCH(0),\n    .C_RACH_TYPE(0),\n    .C_RDCH_TYPE(0),\n    .C_RD_DATA_COUNT_WIDTH(6),\n    .C_RD_FREQ(1),\n    .C_REG_SLICE_MODE_AXIS(0),\n    .C_REG_SLICE_MODE_RACH(0),\n    .C_REG_SLICE_MODE_RDCH(0),\n    .C_REG_SLICE_MODE_WACH(0),\n    .C_REG_SLICE_MODE_WDCH(0),\n    .C_REG_SLICE_MODE_WRCH(0),\n    .C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),\n    .C_UNDERFLOW_LOW(0),\n    .C_USE_COMMON_OVERFLOW(0),\n    .C_USE_COMMON_UNDERFLOW(0),\n    .C_USE_DEFAULT_SETTINGS(0),\n    .C_USE_DOUT_RST(0),\n    .C_USE_ECC(0),\n    .C_USE_ECC_AXIS(0),\n    .C_USE_ECC_RACH(0),\n    .C_USE_ECC_RDCH(0),\n    .C_USE_ECC_WACH(0),\n    .C_USE_ECC_WDCH(0),\n    .C_USE_ECC_WRCH(0),\n    .C_USE_EMBEDDED_REG(0),\n    .C_USE_FIFO16_FLAGS(0),\n    .C_USE_FWFT_DATA_COUNT(1),\n    .C_VALID_LOW(0),\n    .C_WACH_TYPE(0),\n    .C_WDCH_TYPE(0),\n    .C_WRCH_TYPE(0),\n    .C_WR_ACK_LOW(0),\n    .C_WR_DATA_COUNT_WIDTH(6),\n    .C_WR_DEPTH_AXIS(1024),\n    .C_WR_DEPTH_RACH(16),\n    .C_WR_DEPTH_RDCH(1024),\n    .C_WR_DEPTH_WACH(16),\n    .C_WR_DEPTH_WDCH(1024),\n    .C_WR_DEPTH_WRCH(16),\n    .C_WR_FREQ(1),\n    .C_WR_PNTR_WIDTH_AXIS(10),\n    .C_WR_PNTR_WIDTH_RACH(4),\n    .C_WR_PNTR_WIDTH_RDCH(10),\n    .C_WR_PNTR_WIDTH_WACH(4),\n    .C_WR_PNTR_WIDTH_WDCH(10),\n    .C_WR_PNTR_WIDTH_WRCH(4),\n    .C_WR_RESPONSE_LATENCY(1)\n    )\n  fifo_gen_inst (\n    .clk(clk),\n    .din(wr_data),\n    .dout(rd_data),\n    .empty(empty),\n    .full(full),\n    .rd_clk(rd_clk),\n    .rd_en(rd_en),\n    .rst(rst),\n    .wr_clk(wr_clk),\n    .wr_en(wr_en),\n    .almost_empty(),\n    .almost_full(),\n    .axi_ar_data_count(),\n    .axi_ar_dbiterr(),\n    .axi_ar_injectdbiterr(1'b0),\n    .axi_ar_injectsbiterr(1'b0),\n    .axi_ar_overflow(),\n    .axi_ar_prog_empty(),\n    .axi_ar_prog_empty_thresh(4'b0),\n    .axi_ar_prog_full(),\n    .axi_ar_prog_full_thresh(4'b0),\n    .axi_ar_rd_data_count(),\n    .axi_ar_sbiterr(),\n    .axi_ar_underflow(),\n    .axi_ar_wr_data_count(),\n    .axi_aw_data_count(),\n    .axi_aw_dbiterr(),\n    .axi_aw_injectdbiterr(1'b0),\n    .axi_aw_injectsbiterr(1'b0),\n    .axi_aw_overflow(),\n    .axi_aw_prog_empty(),\n    .axi_aw_prog_empty_thresh(4'b0),\n    .axi_aw_prog_full(),\n    .axi_aw_prog_full_thresh(4'b0),\n    .axi_aw_rd_data_count(),\n    .axi_aw_sbiterr(),\n    .axi_aw_underflow(),\n    .axi_aw_wr_data_count(),\n    .axi_b_data_count(),\n    .axi_b_dbiterr(),\n    .axi_b_injectdbiterr(1'b0),\n    .axi_b_injectsbiterr(1'b0),\n    .axi_b_overflow(),\n    .axi_b_prog_empty(),\n    .axi_b_prog_empty_thresh(4'b0),\n    .axi_b_prog_full(),\n    .axi_b_prog_full_thresh(4'b0),\n    .axi_b_rd_data_count(),\n    .axi_b_sbiterr(),\n    .axi_b_underflow(),\n    .axi_b_wr_data_count(),\n    .axi_r_data_count(),\n    .axi_r_dbiterr(),\n    .axi_r_injectdbiterr(1'b0),\n    .axi_r_injectsbiterr(1'b0),\n    .axi_r_overflow(),\n    .axi_r_prog_empty(),\n    .axi_r_prog_empty_thresh(10'b0),\n    .axi_r_prog_full(),\n    .axi_r_prog_full_thresh(10'b0),\n    .axi_r_rd_data_count(),\n    .axi_r_sbiterr(),\n    .axi_r_underflow(),\n    .axi_r_wr_data_count(),\n    .axi_w_data_count(),\n    .axi_w_dbiterr(),\n    .axi_w_injectdbiterr(1'b0),\n    .axi_w_injectsbiterr(1'b0),\n    .axi_w_overflow(),\n    .axi_w_prog_empty(),\n    .axi_w_prog_empty_thresh(10'b0),\n    .axi_w_prog_full(),\n    .axi_w_prog_full_thresh(10'b0),\n    .axi_w_rd_data_count(),\n    .axi_w_sbiterr(),\n    .axi_w_underflow(),\n    .axi_w_wr_data_count(),\n    .axis_data_count(),\n    .axis_dbiterr(),\n    .axis_injectdbiterr(1'b0),\n    .axis_injectsbiterr(1'b0),\n    .axis_overflow(),\n    .axis_prog_empty(),\n    .axis_prog_empty_thresh(10'b0),\n    .axis_prog_full(),\n    .axis_prog_full_thresh(10'b0),\n    .axis_rd_data_count(),\n    .axis_sbiterr(),\n    .axis_underflow(),\n    .axis_wr_data_count(),\n    .backup(1'b0),\n    .backup_marker(1'b0),\n    .data_count(),\n    .dbiterr(),\n    .injectdbiterr(1'b0),\n    .injectsbiterr(1'b0),\n    .int_clk(1'b0),\n    .m_aclk(1'b0),\n    .m_aclk_en(1'b0),\n    .m_axi_araddr(),\n    .m_axi_arburst(),\n    .m_axi_arcache(),\n    .m_axi_arid(),\n    .m_axi_arlen(),\n    .m_axi_arlock(),\n    .m_axi_arprot(),\n    .m_axi_arqos(),\n    .m_axi_arready(1'b0),\n    .m_axi_arregion(),\n    .m_axi_arsize(),\n    .m_axi_aruser(),\n    .m_axi_arvalid(),\n    .m_axi_awaddr(),\n    .m_axi_awburst(),\n    .m_axi_awcache(),\n    .m_axi_awid(),\n    .m_axi_awlen(),\n    .m_axi_awlock(),\n    .m_axi_awprot(),\n    .m_axi_awqos(),\n    .m_axi_awready(1'b0),\n    .m_axi_awregion(),\n    .m_axi_awsize(),\n    .m_axi_awuser(),\n    .m_axi_awvalid(),\n    .m_axi_bid(4'b0),\n    .m_axi_bready(),\n    .m_axi_bresp(2'b0),\n    .m_axi_buser(1'b0),\n    .m_axi_bvalid(1'b0),\n    .m_axi_rdata(64'b0),\n    .m_axi_rid(4'b0),\n    .m_axi_rlast(1'b0),\n    .m_axi_rready(),\n    .m_axi_rresp(2'b0),\n    .m_axi_ruser(1'b0),\n    .m_axi_rvalid(1'b0),\n    .m_axi_wdata(),\n    .m_axi_wid(),\n    .m_axi_wlast(),\n    .m_axi_wready(1'b0),\n    .m_axi_wstrb(),\n    .m_axi_wuser(),\n    .m_axi_wvalid(),\n    .m_axis_tdata(),\n    .m_axis_tdest(),\n    .m_axis_tid(),\n    .m_axis_tkeep(),\n    .m_axis_tlast(),\n    .m_axis_tready(1'b0),\n    .m_axis_tstrb(),\n    .m_axis_tuser(),\n    .m_axis_tvalid(),\n    .overflow(),\n    .prog_empty(),\n    .prog_empty_thresh(5'b0),\n    .prog_empty_thresh_assert(5'b0),\n    .prog_empty_thresh_negate(5'b0),\n    .prog_full(),\n    .prog_full_thresh(5'b0),\n    .prog_full_thresh_assert(5'b0),\n    .prog_full_thresh_negate(5'b0),\n    .rd_data_count(),\n    .rd_rst(1'b0),\n    .s_aclk(1'b0),\n    .s_aclk_en(1'b0),\n    .s_aresetn(1'b0),\n    .s_axi_araddr(32'b0),\n    .s_axi_arburst(2'b0),\n    .s_axi_arcache(4'b0),\n    .s_axi_arid(4'b0),\n    .s_axi_arlen(8'b0),\n    .s_axi_arlock(2'b0),\n    .s_axi_arprot(3'b0),\n    .s_axi_arqos(4'b0),\n    .s_axi_arready(),\n    .s_axi_arregion(4'b0),\n    .s_axi_arsize(3'b0),\n    .s_axi_aruser(1'b0),\n    .s_axi_arvalid(1'b0),\n    .s_axi_awaddr(32'b0),\n    .s_axi_awburst(2'b0),\n    .s_axi_awcache(4'b0),\n    .s_axi_awid(4'b0),\n    .s_axi_awlen(8'b0),\n    .s_axi_awlock(2'b0),\n    .s_axi_awprot(3'b0),\n    .s_axi_awqos(4'b0),\n    .s_axi_awready(),\n    .s_axi_awregion(4'b0),\n    .s_axi_awsize(3'b0),\n    .s_axi_awuser(1'b0),\n    .s_axi_awvalid(1'b0),\n    .s_axi_bid(),\n    .s_axi_bready(1'b0),\n    .s_axi_bresp(),\n    .s_axi_buser(),\n    .s_axi_bvalid(),\n    .s_axi_rdata(),\n    .s_axi_rid(),\n    .s_axi_rlast(),\n    .s_axi_rready(1'b0),\n    .s_axi_rresp(),\n    .s_axi_ruser(),\n    .s_axi_rvalid(),\n    .s_axi_wdata(64'b0),\n    .s_axi_wid(4'b0),\n    .s_axi_wlast(1'b0),\n    .s_axi_wready(),\n    .s_axi_wstrb(8'b0),\n    .s_axi_wuser(1'b0),\n    .s_axi_wvalid(1'b0),\n    .s_axis_tdata(64'b0),\n    .s_axis_tdest(4'b0),\n    .s_axis_tid(8'b0),\n    .s_axis_tkeep(4'b0),\n    .s_axis_tlast(1'b0),\n    .s_axis_tready(),\n    .s_axis_tstrb(4'b0),\n    .s_axis_tuser(4'b0),\n    .s_axis_tvalid(1'b0),\n    .sbiterr(),\n    .srst(1'b0),\n    .underflow(),\n    .valid(),\n    .wr_ack(),\n    .wr_data_count(),\n    .wr_rst(1'b0),\n    .wr_rst_busy(),\n    .rd_rst_busy(),\n    .sleep(1'b0)\n  );\n\nendmodule\n\n\n\n// -- (c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n// Structure:\n//   axic_srl_fifo\n//     ndeep_srl\n//       nto1_mux\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_14_axic_srl_fifo #\n  (\n   parameter         C_FAMILY   = \"none\", // FPGA Family\n   parameter integer C_FIFO_WIDTH  = 1, // Width of S_MESG/M_MESG.\n   parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits\n                                             // the control logic can be used\n                                             // on before the control logic\n                                             // needs to be replicated.\n   parameter integer C_FIFO_DEPTH_LOG =  2,  // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.  \n                                             // The minimum size fifo generated is 4-deep.\n   parameter         C_USE_FULL =  1         // Prevent overwrite by throttling S_READY.                                              \n   )\n  (\n   input  wire                        ACLK,    // Clock\n   input  wire                        ARESET,  // Reset\n   input  wire [C_FIFO_WIDTH-1:0]     S_MESG,  // Input data\n   input  wire                        S_VALID, // Input data valid\n   output wire                        S_READY, // Input data ready\n   output wire [C_FIFO_WIDTH-1:0]     M_MESG,  // Output data\n   output wire                        M_VALID, // Output data valid\n   input  wire                        M_READY  // Output data ready\n   );\n  \n  localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;\n  localparam P_EMPTY       = {P_FIFO_DEPTH_LOG{1'b1}};\n  localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};\n  localparam P_ALMOSTFULL_TEMP  = {P_EMPTY, 1'b0};\n  localparam P_ALMOSTFULL  = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];\n  localparam P_NUM_REPS    = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?\n                             (C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :\n                             ((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;\n\n  (* syn_keep = \"1\" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0]  fifoaddr;\n  (* syn_keep = \"1\" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;\n\n  genvar i;\n  genvar j;\n\n  reg  M_VALID_i;\n  reg  S_READY_i;\n  wire push;     // FIFO push\n  wire pop;      // FIFO pop\n  reg  areset_d1; // Reset delay register\n  wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data\n\n  assign M_VALID = M_VALID_i;\n  assign S_READY = C_USE_FULL ? S_READY_i : 1'b1;\n  assign M_MESG = m_axi_mesg_i;\n  assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1'b1);\n  assign pop  = M_VALID_i & M_READY;\n  \n  always @(posedge ACLK) begin\n    areset_d1 <= ARESET;\n  end\n      \n  generate\n    //---------------------------------------------------------------------------\n    // Create count of number of elements in FIFOs\n    //---------------------------------------------------------------------------\n    for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep\n      assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] = \n         push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :\n                fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;\n      always @(posedge ACLK) begin\n        if (ARESET)\n          fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= \n                {P_FIFO_DEPTH_LOG{1'b1}};\n        else if (push ^ pop)\n          fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= \n                fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];\n      end\n    end\n\n    //---------------------------------------------------------------------------\n    // When FIFO is empty, reset master valid bit.  When not empty set valid bit.\n    // When FIFO is full,  reset slave  ready bit.  When not full  set ready bit.\n    //---------------------------------------------------------------------------\n    \n    always @(posedge ACLK) begin\n      if (ARESET) begin\n        M_VALID_i <= 1'b0;\n      end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == \n                               P_ALMOSTEMPTY) && pop && ~push) begin\n        M_VALID_i <= 1'b0;\n      end else if (push) begin\n        M_VALID_i <= 1'b1;\n      end\n    end\n      \n    always @(posedge ACLK) begin\n      if (ARESET) begin\n        S_READY_i <= 1'b0;\n      end else if (areset_d1) begin\n        S_READY_i <= 1'b1;\n      end else if (C_USE_FULL && \n        ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == \n         P_ALMOSTFULL) && push && ~pop)) begin\n        S_READY_i <= 1'b0;\n      end else if (C_USE_FULL && pop) begin\n        S_READY_i <= 1'b1;\n      end\n    end\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls\n      for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep\n        axi_data_fifo_v2_1_14_ndeep_srl #\n          (\n           .C_FAMILY  (C_FAMILY),\n           .C_A_WIDTH (P_FIFO_DEPTH_LOG)\n          )\n          srl_nx1\n          (\n           .CLK (ACLK),\n           .A   (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:\n                          P_FIFO_DEPTH_LOG*(i)]),\n           .CE  (push),\n           .D   (S_MESG[i*C_MAX_CTRL_FANOUT+j]),\n           .Q   (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j])\n          );\n      end\n    end      \n  endgenerate\n  \nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.\n//   Interface outputs are synchronized using ordinary flops for improved timing.\n//--------------------------------------------------------------------------\n// Structure:\n//   axic_reg_srl_fifo\n//     ndeep_srl\n//       nto1_mux\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_14_axic_reg_srl_fifo #\n  (\n   parameter         C_FAMILY   = \"none\", // FPGA Family\n   parameter integer C_FIFO_WIDTH  = 1, // Width of S_MESG/M_MESG.\n   parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits\n                                             // the control logic can be used\n                                             // on before the control logic\n                                             // needs to be replicated.\n   parameter integer C_FIFO_DEPTH_LOG =  2,  // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.  \n                                             // The minimum size fifo generated is 4-deep.\n   parameter         C_USE_FULL =  1         // Prevent overwrite by throttling S_READY.                                              \n   )\n  (\n   input  wire                        ACLK,    // Clock\n   input  wire                        ARESET,  // Reset\n   input  wire [C_FIFO_WIDTH-1:0]     S_MESG,  // Input data\n   input  wire                        S_VALID, // Input data valid\n   output wire                        S_READY, // Input data ready\n   output wire [C_FIFO_WIDTH-1:0]     M_MESG,  // Output data\n   output wire                        M_VALID, // Output data valid\n   input  wire                        M_READY  // Output data ready\n   );\n  \n  localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;\n  localparam P_EMPTY       = {P_FIFO_DEPTH_LOG{1'b1}};\n  localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};\n  localparam P_ALMOSTFULL_TEMP  = {P_EMPTY, 1'b0};\n  localparam P_ALMOSTFULL  = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];\n  localparam P_NUM_REPS    = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?\n                             (C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :\n                             ((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;\n\n  (* syn_keep = \"1\" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0]  fifoaddr;\n  (* syn_keep = \"1\" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;\n\n  genvar i;\n  genvar j;\n\n  \n  reg  m_valid_i = 1'b0;\n  reg  s_ready_i;\n  wire push;     // FIFO push\n  wire pop;      // FIFO pop\n  reg  areset_d1; // Reset delay register\n  reg  [C_FIFO_WIDTH-1:0] storage_data1;\n  wire [C_FIFO_WIDTH-1:0] storage_data2; // Intermediate SRL data\n  reg                    load_s1;\n  wire                   load_s1_from_s2;\n\n  reg [1:0] state;\n  localparam [1:0] \n    ZERO = 2'b10,\n    ONE  = 2'b11,\n    TWO  = 2'b01;\n      \n  assign M_VALID = m_valid_i;\n  assign S_READY = C_USE_FULL ? s_ready_i : 1'b1;\n  assign push = (S_VALID & (C_USE_FULL ? s_ready_i : 1'b1) & (state == TWO)) | (~M_READY & S_VALID & (state == ONE));\n  assign pop  = M_READY & (state == TWO);\n  assign M_MESG = storage_data1;\n  \n  always @(posedge ACLK) begin\n    areset_d1 <= ARESET;\n  end\n      \n  // Load storage1 with either slave side data or from storage2\n  always @(posedge ACLK) \n  begin\n    if (load_s1)\n      if (load_s1_from_s2)\n        storage_data1 <= storage_data2;\n      else\n        storage_data1 <= S_MESG;        \n  end\n\n  // Loading s1\n  always @ *\n  begin\n    if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction\n         // Load when ONE if we both have read and write at the same time\n         ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||\n         // Load when TWO and we have a transaction on Master side\n         ((state == TWO) && (M_READY == 1)))\n      load_s1 = 1'b1;\n    else\n      load_s1 = 1'b0;\n  end // always @ *\n\n  assign load_s1_from_s2 = (state == TWO);\n                   \n  // State Machine for handling output signals\n  always @(posedge ACLK) \n  begin\n    if (areset_d1) begin\n      state <= ZERO;\n      m_valid_i <= 1'b0;\n    end else begin\n      case (state)\n        // No transaction stored locally\n        ZERO: begin\n          if (S_VALID) begin\n            state <= ONE; // Got one so move to ONE\n            m_valid_i <= 1'b1;\n          end\n        end\n\n        // One transaction stored locally\n        ONE: begin\n          if (M_READY & ~S_VALID) begin\n            state <= ZERO; // Read out one so move to ZERO\n            m_valid_i <= 1'b0;\n          end else if (~M_READY & S_VALID) begin\n            state <= TWO;  // Got another one so move to TWO\n            m_valid_i <= 1'b1;\n          end\n        end\n\n        // TWO transaction stored locally\n        TWO: begin\n          if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == \n                 P_ALMOSTEMPTY) && pop && ~push) begin\n            state <= ONE; // Read out one so move to ONE\n            m_valid_i <= 1'b1;\n          end\n        end\n      endcase // case (state)\n    end\n  end // always @ (posedge ACLK)\n      \n  generate\n    //---------------------------------------------------------------------------\n    // Create count of number of elements in FIFOs\n    //---------------------------------------------------------------------------\n    for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep\n      assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] = \n         push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :\n                fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;\n      always @(posedge ACLK) begin\n        if (ARESET)\n          fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= \n                {P_FIFO_DEPTH_LOG{1'b1}};\n        else if (push ^ pop)\n          fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= \n                fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (ARESET) begin\n        s_ready_i <= 1'b0;\n      end else if (areset_d1) begin\n        s_ready_i <= 1'b1;\n      end else if (C_USE_FULL && \n        ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == \n         P_ALMOSTFULL) && push && ~pop)) begin\n        s_ready_i <= 1'b0;\n      end else if (C_USE_FULL && pop) begin\n        s_ready_i <= 1'b1;\n      end\n    end\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls\n      for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep\n        axi_data_fifo_v2_1_14_ndeep_srl #\n          (\n           .C_FAMILY  (C_FAMILY),\n           .C_A_WIDTH (P_FIFO_DEPTH_LOG)\n          )\n          srl_nx1\n          (\n           .CLK (ACLK),\n           .A   (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:\n                          P_FIFO_DEPTH_LOG*(i)]),\n           .CE  (push),\n           .D   (S_MESG[i*C_MAX_CTRL_FANOUT+j]),\n           .Q   (storage_data2[i*C_MAX_CTRL_FANOUT+j])\n          );\n      end\n    end      \n  endgenerate\n  \nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: This is a generic n-deep SRL instantiation\n// Verilog-standard:  Verilog 2001\n// $Revision: \n// $Date: \n//\n//-----------------------------------------------------------------------------\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_14_ndeep_srl #\n  (\n   parameter         C_FAMILY  = \"rtl\", // FPGA Family\n   parameter         C_A_WIDTH = 1          // Address Width (>= 1)\n   )\n  (\n   input  wire                 CLK, // Clock\n   input  wire [C_A_WIDTH-1:0] A,   // Address\n   input  wire                 CE,  // Clock Enable\n   input  wire                 D,   // Input Data\n   output wire                 Q    // Output Data\n   );\n\n  localparam integer P_SRLASIZE = 5;\n  localparam integer P_SRLDEPTH = 32;\n  localparam integer P_NUMSRLS  = (C_A_WIDTH>P_SRLASIZE) ? (2**(C_A_WIDTH-P_SRLASIZE)) : 1;\n  localparam integer P_SHIFT_DEPTH  = 2**C_A_WIDTH;\n  \n  wire [P_NUMSRLS:0]   d_i;\n  wire [P_NUMSRLS-1:0] q_i;\n  wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i;\n  \n  genvar i;\n  \n  // Instantiate SRLs in carry chain format\n  assign d_i[0] = D;\n  assign a_i = A;\n  \n  generate\n\t\t\t\t\t\n    if (C_FAMILY == \"rtl\") begin : gen_rtl_shifter\n      if (C_A_WIDTH <= P_SRLASIZE) begin : gen_inferred_srl\n        reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n        always @(posedge CLK)\n          if (CE)\n            shift_reg <= {shift_reg[P_SRLDEPTH-2:0], D};\n        assign Q = shift_reg[a_i];\n      end else begin : gen_logic_shifter  // Very wasteful\n        reg [P_SHIFT_DEPTH-1:0] shift_reg = {P_SHIFT_DEPTH{1'b0}};\n        always @(posedge CLK)\n          if (CE)\n            shift_reg <= {shift_reg[P_SHIFT_DEPTH-2:0], D};\n        assign Q = shift_reg[a_i];\n      end\n    end else begin : gen_primitive_shifter\n      for (i=0;i<P_NUMSRLS;i=i+1) begin : gen_srls\n        SRLC32E\n          srl_inst\n            (\n             .CLK (CLK),\n             .A   (a_i[P_SRLASIZE-1:0]),\n             .CE  (CE),\n             .D   (d_i[i]),\n             .Q   (q_i[i]),\n             .Q31 (d_i[i+1])\n             );\n      end\n      \n      if (C_A_WIDTH>P_SRLASIZE) begin : gen_srl_mux\n        generic_baseblocks_v2_1_0_nto1_mux #\n        (\n          .C_RATIO         (2**(C_A_WIDTH-P_SRLASIZE)),\n          .C_SEL_WIDTH     (C_A_WIDTH-P_SRLASIZE),\n          .C_DATAOUT_WIDTH (1),\n          .C_ONEHOT        (0)\n        )\n        srl_q_mux_inst\n        (\n          .SEL_ONEHOT ({2**(C_A_WIDTH-P_SRLASIZE){1'b0}}),\n          .SEL        (a_i[C_A_WIDTH-1:P_SRLASIZE]),\n          .IN         (q_i),\n          .OUT        (Q)\n        );\n      end else begin : gen_no_srl_mux\n        assign Q = q_i[0];\n      end\n    end\n  endgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// AXI data fifo module:    \n//   5-channel memory-mapped AXI4 interfaces.\n//   SRL or BRAM based FIFO on AXI W and/or R channels.\n//   FIFO to accommodate various data flow rates through the AXI interconnect\n//\n// Verilog-standard:  Verilog 2001\n//-----------------------------------------------------------------------------\n//\n// Structure:\n//   axi_data_fifo\n//     fifo_generator\n//\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_14_axi_data_fifo #\n  (\n   parameter         C_FAMILY                    = \"virtex7\",\n   parameter integer C_AXI_PROTOCOL              = 0,\n   parameter integer C_AXI_ID_WIDTH              = 4,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   parameter integer C_AXI_WRITE_FIFO_DEPTH      = 0,      // Range: (0, 32, 512)\n   parameter         C_AXI_WRITE_FIFO_TYPE       = \"lut\",  // \"lut\" = LUT (SRL) based,\n                                                           // \"bram\" = BRAM based\n   parameter integer C_AXI_WRITE_FIFO_DELAY      = 0,      // 0 = No, 1 = Yes\n                       // Indicates whether AWVALID and WVALID assertion is delayed until:\n                       //   a. the corresponding WLAST is stored in the FIFO, or\n                       //   b. no WLAST is stored and the FIFO is full.\n                       // 0 means AW channel is pass-through and \n                       //   WVALID is asserted whenever FIFO is not empty.\n   parameter integer C_AXI_READ_FIFO_DEPTH       = 0,      // Range: (0, 32, 512)\n   parameter         C_AXI_READ_FIFO_TYPE        = \"lut\",  // \"lut\" = LUT (SRL) based,\n                                                           // \"bram\" = BRAM based\n   parameter integer C_AXI_READ_FIFO_DELAY       = 0)      // 0 = No, 1 = Yes\n                       // Indicates whether ARVALID assertion is delayed until the \n                       //   the remaining vacancy of the FIFO is at least the burst length\n                       //   as indicated by ARLEN.\n                       // 0 means AR channel is pass-through.\n   // System Signals\n  (input wire aclk,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     s_axi_bid,\n   output wire [2-1:0]                  s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0]  s_axi_buser,\n   output wire                          s_axi_bvalid,\n   input  wire                          s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   s_axi_rdata,\n   output wire [2-1:0]                  s_axi_rresp,\n   output wire                          s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0]  s_axi_ruser,\n   output wire                          s_axi_rvalid,\n   input  wire                          s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     m_axi_bid,\n   input  wire [2-1:0]                  m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0]  m_axi_buser,\n   input  wire                          m_axi_bvalid,\n   output wire                          m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   m_axi_rdata,\n   input  wire [2-1:0]                  m_axi_rresp,\n   input  wire                          m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0]  m_axi_ruser,\n   input  wire                          m_axi_rvalid,\n   output wire                          m_axi_rready);\n  \n  localparam integer P_WIDTH_RACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_ARUSER_WIDTH;\n  localparam integer P_WIDTH_WACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_AWUSER_WIDTH;\n  localparam integer P_WIDTH_RDCH = 1 + 2 + C_AXI_DATA_WIDTH + C_AXI_ID_WIDTH + C_AXI_RUSER_WIDTH;\n  localparam integer P_WIDTH_WDCH = 1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+((C_AXI_PROTOCOL==1)?C_AXI_ID_WIDTH:0)+C_AXI_WUSER_WIDTH;\n  localparam integer P_WIDTH_WRCH = 2 + C_AXI_ID_WIDTH + C_AXI_BUSER_WIDTH;\n  \n  localparam         P_PRIM_FIFO_TYPE = \"512x72\" ;\n  localparam integer P_AXI4 = 0;\n  localparam integer P_AXI3 = 1;\n  localparam integer P_AXILITE = 2;\n  localparam integer P_WRITE_FIFO_DEPTH_LOG = (C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1;\n  localparam integer P_READ_FIFO_DEPTH_LOG = (C_AXI_READ_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1;\n  \n  // Ceiling of log2(x)\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  generate\n    if (((C_AXI_WRITE_FIFO_DEPTH == 0) && (C_AXI_READ_FIFO_DEPTH == 0)) || (C_AXI_PROTOCOL == P_AXILITE)) begin : gen_bypass\n      assign m_axi_awid     = s_axi_awid;\n      assign m_axi_awaddr   = s_axi_awaddr;\n      assign m_axi_awlen    = s_axi_awlen;\n      assign m_axi_awsize   = s_axi_awsize;\n      assign m_axi_awburst  = s_axi_awburst;\n      assign m_axi_awlock   = s_axi_awlock;\n      assign m_axi_awcache  = s_axi_awcache;\n      assign m_axi_awprot   = s_axi_awprot;\n      assign m_axi_awregion = s_axi_awregion;\n      assign m_axi_awqos    = s_axi_awqos;\n      assign m_axi_awuser   = s_axi_awuser;\n      assign m_axi_awvalid  = s_axi_awvalid;\n      assign s_axi_awready  = m_axi_awready;\n      \n      assign m_axi_wid      = s_axi_wid;\n      assign m_axi_wdata    = s_axi_wdata;\n      assign m_axi_wstrb    = s_axi_wstrb;\n      assign m_axi_wlast    = s_axi_wlast;\n      assign m_axi_wuser    = s_axi_wuser;\n      assign m_axi_wvalid   = s_axi_wvalid;\n      assign s_axi_wready   = m_axi_wready;\n    \n      assign s_axi_bid      = m_axi_bid;\n      assign s_axi_bresp    = m_axi_bresp;\n      assign s_axi_buser    = m_axi_buser;\n      assign s_axi_bvalid   = m_axi_bvalid;\n      assign m_axi_bready   = s_axi_bready;\n    \n      assign m_axi_arid     = s_axi_arid;\n      assign m_axi_araddr   = s_axi_araddr;\n      assign m_axi_arlen    = s_axi_arlen;\n      assign m_axi_arsize   = s_axi_arsize;\n      assign m_axi_arburst  = s_axi_arburst;\n      assign m_axi_arlock   = s_axi_arlock;\n      assign m_axi_arcache  = s_axi_arcache;\n      assign m_axi_arprot   = s_axi_arprot;\n      assign m_axi_arregion = s_axi_arregion;\n      assign m_axi_arqos    = s_axi_arqos;\n      assign m_axi_aruser   = s_axi_aruser;\n      assign m_axi_arvalid  = s_axi_arvalid;\n      assign s_axi_arready  = m_axi_arready;\n  \n      assign s_axi_rid      = m_axi_rid;\n      assign s_axi_rdata    = m_axi_rdata;\n      assign s_axi_rresp    = m_axi_rresp;\n      assign s_axi_rlast    = m_axi_rlast;\n      assign s_axi_ruser    = m_axi_ruser;\n      assign s_axi_rvalid   = m_axi_rvalid;\n      assign m_axi_rready   = s_axi_rready;\n      \n    end else begin : gen_fifo\n      \n      wire [4-1:0]                  s_axi_awregion_i;\n      wire [4-1:0]                  s_axi_arregion_i;\n      wire [4-1:0]                  m_axi_awregion_i;\n      wire [4-1:0]                  m_axi_arregion_i;\n      wire [C_AXI_ID_WIDTH-1:0]     s_axi_wid_i;\n      wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid_i;\n      \n      assign s_axi_awregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : s_axi_awregion;\n      assign s_axi_arregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : s_axi_arregion;\n      assign m_axi_awregion = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : m_axi_awregion_i;\n      assign m_axi_arregion = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : m_axi_arregion_i;\n      assign s_axi_wid_i = (C_AXI_PROTOCOL == P_AXI3) ? s_axi_wid : {C_AXI_ID_WIDTH{1'b0}};\n      assign m_axi_wid = (C_AXI_PROTOCOL == P_AXI3) ? m_axi_wid_i : {C_AXI_ID_WIDTH{1'b0}};\n\n\n      fifo_generator_v13_2_1 #(\n          .C_EN_SAFETY_CKT(0),\n          .C_SELECT_XPM(0),\n          .C_INTERFACE_TYPE(2),\n          .C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : 3),\n          .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n          .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n          .C_HAS_AXI_ID(1),\n          .C_AXI_LEN_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 8 : 4),\n          .C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 1 : 2),\n          .C_HAS_AXI_ARUSER(1),\n          .C_HAS_AXI_AWUSER(1),\n          .C_HAS_AXI_BUSER(1),\n          .C_HAS_AXI_RUSER(1),\n          .C_HAS_AXI_WUSER(1),\n          .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n          .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n          .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n          .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),\n          .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n          .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n          .C_DIN_WIDTH_RACH(P_WIDTH_RACH),\n          .C_DIN_WIDTH_RDCH(P_WIDTH_RDCH),\n          .C_DIN_WIDTH_WACH(P_WIDTH_WACH),\n          .C_DIN_WIDTH_WDCH(P_WIDTH_WDCH),\n          .C_DIN_WIDTH_WRCH(P_WIDTH_WDCH),\n          .C_RACH_TYPE(((C_AXI_READ_FIFO_DEPTH != 0) && C_AXI_READ_FIFO_DELAY) ? 0 : 2),\n          .C_WACH_TYPE(((C_AXI_WRITE_FIFO_DEPTH != 0) && C_AXI_WRITE_FIFO_DELAY) ? 0 : 2),\n          .C_WDCH_TYPE((C_AXI_WRITE_FIFO_DEPTH != 0) ? 0 : 2),\n          .C_RDCH_TYPE((C_AXI_READ_FIFO_DEPTH != 0) ? 0 : 2),\n          .C_WRCH_TYPE(2),\n          .C_COMMON_CLOCK(1),\n          .C_ADD_NGC_CONSTRAINT(0),\n          .C_APPLICATION_TYPE_AXIS(0),\n          .C_APPLICATION_TYPE_RACH(C_AXI_READ_FIFO_DELAY ? 1 : 0),\n          .C_APPLICATION_TYPE_RDCH(0),\n          .C_APPLICATION_TYPE_WACH(C_AXI_WRITE_FIFO_DELAY ? 1 : 0),\n          .C_APPLICATION_TYPE_WDCH(0),\n          .C_APPLICATION_TYPE_WRCH(0),\n          .C_AXIS_TDATA_WIDTH(64),\n          .C_AXIS_TDEST_WIDTH(4),\n          .C_AXIS_TID_WIDTH(8),\n          .C_AXIS_TKEEP_WIDTH(4),\n          .C_AXIS_TSTRB_WIDTH(4),\n          .C_AXIS_TUSER_WIDTH(4),\n          .C_AXIS_TYPE(0),\n          .C_COUNT_TYPE(0),\n          .C_DATA_COUNT_WIDTH(10),\n          .C_DEFAULT_VALUE(\"BlankString\"),\n          .C_DIN_WIDTH(18),\n          .C_DIN_WIDTH_AXIS(1),\n          .C_DOUT_RST_VAL(\"0\"),\n          .C_DOUT_WIDTH(18),\n          .C_ENABLE_RLOCS(0),\n          .C_ENABLE_RST_SYNC(1),\n          .C_ERROR_INJECTION_TYPE(0),\n          .C_ERROR_INJECTION_TYPE_AXIS(0),\n          .C_ERROR_INJECTION_TYPE_RACH(0),\n          .C_ERROR_INJECTION_TYPE_RDCH(0),\n          .C_ERROR_INJECTION_TYPE_WACH(0),\n          .C_ERROR_INJECTION_TYPE_WDCH(0),\n          .C_ERROR_INJECTION_TYPE_WRCH(0),\n          .C_FAMILY(C_FAMILY),\n          .C_FULL_FLAGS_RST_VAL(1),\n          .C_HAS_ALMOST_EMPTY(0),\n          .C_HAS_ALMOST_FULL(0),\n          .C_HAS_AXI_RD_CHANNEL(1),\n          .C_HAS_AXI_WR_CHANNEL(1),\n          .C_HAS_AXIS_TDATA(0),\n          .C_HAS_AXIS_TDEST(0),\n          .C_HAS_AXIS_TID(0),\n          .C_HAS_AXIS_TKEEP(0),\n          .C_HAS_AXIS_TLAST(0),\n          .C_HAS_AXIS_TREADY(1),\n          .C_HAS_AXIS_TSTRB(0),\n          .C_HAS_AXIS_TUSER(0),\n          .C_HAS_BACKUP(0),\n          .C_HAS_DATA_COUNT(0),\n          .C_HAS_DATA_COUNTS_AXIS(0),\n          .C_HAS_DATA_COUNTS_RACH(0),\n          .C_HAS_DATA_COUNTS_RDCH(0),\n          .C_HAS_DATA_COUNTS_WACH(0),\n          .C_HAS_DATA_COUNTS_WDCH(0),\n          .C_HAS_DATA_COUNTS_WRCH(0),\n          .C_HAS_INT_CLK(0),\n          .C_HAS_MASTER_CE(0),\n          .C_HAS_MEMINIT_FILE(0),\n          .C_HAS_OVERFLOW(0),\n          .C_HAS_PROG_FLAGS_AXIS(0),\n          .C_HAS_PROG_FLAGS_RACH(0),\n          .C_HAS_PROG_FLAGS_RDCH(0),\n          .C_HAS_PROG_FLAGS_WACH(0),\n          .C_HAS_PROG_FLAGS_WDCH(0),\n          .C_HAS_PROG_FLAGS_WRCH(0),\n          .C_HAS_RD_DATA_COUNT(0),\n          .C_HAS_RD_RST(0),\n          .C_HAS_RST(1),\n          .C_HAS_SLAVE_CE(0),\n          .C_HAS_SRST(0),\n          .C_HAS_UNDERFLOW(0),\n          .C_HAS_VALID(0),\n          .C_HAS_WR_ACK(0),\n          .C_HAS_WR_DATA_COUNT(0),\n          .C_HAS_WR_RST(0),\n          .C_IMPLEMENTATION_TYPE(0),\n          .C_IMPLEMENTATION_TYPE_AXIS(1),\n          .C_IMPLEMENTATION_TYPE_RACH(2),\n          .C_IMPLEMENTATION_TYPE_RDCH((C_AXI_READ_FIFO_TYPE == \"bram\") ? 1 : 2),\n          .C_IMPLEMENTATION_TYPE_WACH(2),\n          .C_IMPLEMENTATION_TYPE_WDCH((C_AXI_WRITE_FIFO_TYPE == \"bram\") ? 1 : 2),\n          .C_IMPLEMENTATION_TYPE_WRCH(2),\n          .C_INIT_WR_PNTR_VAL(0),\n          .C_MEMORY_TYPE(1),\n          .C_MIF_FILE_NAME(\"BlankString\"),\n          .C_MSGON_VAL(1),\n          .C_OPTIMIZATION_MODE(0),\n          .C_OVERFLOW_LOW(0),\n          .C_PRELOAD_LATENCY(1),\n          .C_PRELOAD_REGS(0),\n          .C_PRIM_FIFO_TYPE(P_PRIM_FIFO_TYPE),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(30),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(510),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(30),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(510),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(14),\n          .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),\n          .C_PROG_EMPTY_TYPE(0),\n          .C_PROG_EMPTY_TYPE_AXIS(5),\n          .C_PROG_EMPTY_TYPE_RACH(5),\n          .C_PROG_EMPTY_TYPE_RDCH(5),\n          .C_PROG_EMPTY_TYPE_WACH(5),\n          .C_PROG_EMPTY_TYPE_WDCH(5),\n          .C_PROG_EMPTY_TYPE_WRCH(5),\n          .C_PROG_FULL_THRESH_ASSERT_VAL(1022),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(31),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(511),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(31),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(511),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),\n          .C_PROG_FULL_THRESH_NEGATE_VAL(1021),\n          .C_PROG_FULL_TYPE(0),\n          .C_PROG_FULL_TYPE_AXIS(5),\n          .C_PROG_FULL_TYPE_RACH(5),\n          .C_PROG_FULL_TYPE_RDCH(5),\n          .C_PROG_FULL_TYPE_WACH(5),\n          .C_PROG_FULL_TYPE_WDCH(5),\n          .C_PROG_FULL_TYPE_WRCH(5),\n          .C_RD_DATA_COUNT_WIDTH(10),\n          .C_RD_DEPTH(1024),\n          .C_RD_FREQ(1),\n          .C_RD_PNTR_WIDTH(10),\n          .C_REG_SLICE_MODE_AXIS(0),\n          .C_REG_SLICE_MODE_RACH(0),\n          .C_REG_SLICE_MODE_RDCH(0),\n          .C_REG_SLICE_MODE_WACH(0),\n          .C_REG_SLICE_MODE_WDCH(0),\n          .C_REG_SLICE_MODE_WRCH(0),\n          .C_UNDERFLOW_LOW(0),\n          .C_USE_COMMON_OVERFLOW(0),\n          .C_USE_COMMON_UNDERFLOW(0),\n          .C_USE_DEFAULT_SETTINGS(0),\n          .C_USE_DOUT_RST(1),\n          .C_USE_ECC(0),\n          .C_USE_ECC_AXIS(0),\n          .C_USE_ECC_RACH(0),\n          .C_USE_ECC_RDCH(0),\n          .C_USE_ECC_WACH(0),\n          .C_USE_ECC_WDCH(0),\n          .C_USE_ECC_WRCH(0),\n          .C_USE_EMBEDDED_REG(0),\n          .C_USE_FIFO16_FLAGS(0),\n          .C_USE_FWFT_DATA_COUNT(0),\n          .C_VALID_LOW(0),\n          .C_WR_ACK_LOW(0),\n          .C_WR_DATA_COUNT_WIDTH(10),\n          .C_WR_DEPTH(1024),\n          .C_WR_DEPTH_AXIS(1024),\n          .C_WR_DEPTH_RACH(32),\n          .C_WR_DEPTH_RDCH(C_AXI_READ_FIFO_DEPTH),\n          .C_WR_DEPTH_WACH(32),\n          .C_WR_DEPTH_WDCH(C_AXI_WRITE_FIFO_DEPTH),\n          .C_WR_DEPTH_WRCH(16),\n          .C_WR_FREQ(1),\n          .C_WR_PNTR_WIDTH(10),\n          .C_WR_PNTR_WIDTH_AXIS(10),\n          .C_WR_PNTR_WIDTH_RACH(5),\n          .C_WR_PNTR_WIDTH_RDCH((C_AXI_READ_FIFO_DEPTH> 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1),\n          .C_WR_PNTR_WIDTH_WACH(5),\n          .C_WR_PNTR_WIDTH_WDCH((C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1),\n          .C_WR_PNTR_WIDTH_WRCH(4),\n          .C_WR_RESPONSE_LATENCY(1)\n        )\n        fifo_gen_inst (\n          .s_aclk(aclk),\n          .s_aresetn(aresetn),\n          .s_axi_awid(s_axi_awid),\n          .s_axi_awaddr(s_axi_awaddr),\n          .s_axi_awlen(s_axi_awlen),\n          .s_axi_awsize(s_axi_awsize),\n          .s_axi_awburst(s_axi_awburst),\n          .s_axi_awlock(s_axi_awlock),\n          .s_axi_awcache(s_axi_awcache),\n          .s_axi_awprot(s_axi_awprot),\n          .s_axi_awqos(s_axi_awqos),\n          .s_axi_awregion(s_axi_awregion_i),\n          .s_axi_awuser(s_axi_awuser),\n          .s_axi_awvalid(s_axi_awvalid),\n          .s_axi_awready(s_axi_awready),\n          .s_axi_wid(s_axi_wid_i),\n          .s_axi_wdata(s_axi_wdata),\n          .s_axi_wstrb(s_axi_wstrb),\n          .s_axi_wlast(s_axi_wlast),\n          .s_axi_wvalid(s_axi_wvalid),\n          .s_axi_wready(s_axi_wready),\n          .s_axi_bid(s_axi_bid),\n          .s_axi_bresp(s_axi_bresp),\n          .s_axi_bvalid(s_axi_bvalid),\n          .s_axi_bready(s_axi_bready),\n          .m_axi_awid(m_axi_awid),\n          .m_axi_awaddr(m_axi_awaddr),\n          .m_axi_awlen(m_axi_awlen),\n          .m_axi_awsize(m_axi_awsize),\n          .m_axi_awburst(m_axi_awburst),\n          .m_axi_awlock(m_axi_awlock),\n          .m_axi_awcache(m_axi_awcache),\n          .m_axi_awprot(m_axi_awprot),\n          .m_axi_awqos(m_axi_awqos),\n          .m_axi_awregion(m_axi_awregion_i),\n          .m_axi_awuser(m_axi_awuser),\n          .m_axi_awvalid(m_axi_awvalid),\n          .m_axi_awready(m_axi_awready),\n          .m_axi_wid(m_axi_wid_i),\n          .m_axi_wdata(m_axi_wdata),\n          .m_axi_wstrb(m_axi_wstrb),\n          .m_axi_wlast(m_axi_wlast),\n          .m_axi_wvalid(m_axi_wvalid),\n          .m_axi_wready(m_axi_wready),\n          .m_axi_bid(m_axi_bid),\n          .m_axi_bresp(m_axi_bresp),\n          .m_axi_bvalid(m_axi_bvalid),\n          .m_axi_bready(m_axi_bready),\n          .s_axi_arid(s_axi_arid),\n          .s_axi_araddr(s_axi_araddr),\n          .s_axi_arlen(s_axi_arlen),\n          .s_axi_arsize(s_axi_arsize),\n          .s_axi_arburst(s_axi_arburst),\n          .s_axi_arlock(s_axi_arlock),\n          .s_axi_arcache(s_axi_arcache),\n          .s_axi_arprot(s_axi_arprot),\n          .s_axi_arqos(s_axi_arqos),\n          .s_axi_arregion(s_axi_arregion_i),\n          .s_axi_arvalid(s_axi_arvalid),\n          .s_axi_arready(s_axi_arready),\n          .s_axi_rid(s_axi_rid),\n          .s_axi_rdata(s_axi_rdata),\n          .s_axi_rresp(s_axi_rresp),\n          .s_axi_rlast(s_axi_rlast),\n          .s_axi_rvalid(s_axi_rvalid),\n          .s_axi_rready(s_axi_rready),\n          .m_axi_arid(m_axi_arid),\n          .m_axi_araddr(m_axi_araddr),\n          .m_axi_arlen(m_axi_arlen),\n          .m_axi_arsize(m_axi_arsize),\n          .m_axi_arburst(m_axi_arburst),\n          .m_axi_arlock(m_axi_arlock),\n          .m_axi_arcache(m_axi_arcache),\n          .m_axi_arprot(m_axi_arprot),\n          .m_axi_arqos(m_axi_arqos),\n          .m_axi_arregion(m_axi_arregion_i),\n          .m_axi_arvalid(m_axi_arvalid),\n          .m_axi_arready(m_axi_arready),\n          .m_axi_rid(m_axi_rid),\n          .m_axi_rdata(m_axi_rdata),\n          .m_axi_rresp(m_axi_rresp),\n          .m_axi_rlast(m_axi_rlast),\n          .m_axi_rvalid(m_axi_rvalid),\n          .m_axi_rready(m_axi_rready),\n          .m_aclk(aclk),\n          .m_aclk_en(1'b1),\n          .s_aclk_en(1'b1),\n          .s_axi_wuser(s_axi_wuser),\n          .s_axi_buser(s_axi_buser),\n          .m_axi_wuser(m_axi_wuser),\n          .m_axi_buser(m_axi_buser),\n          .s_axi_aruser(s_axi_aruser),\n          .s_axi_ruser(s_axi_ruser),\n          .m_axi_aruser(m_axi_aruser),\n          .m_axi_ruser(m_axi_ruser),\n          .almost_empty(),\n          .almost_full(),\n          .axis_data_count(),\n          .axis_dbiterr(),\n          .axis_injectdbiterr(1'b0),\n          .axis_injectsbiterr(1'b0),\n          .axis_overflow(),\n          .axis_prog_empty(),\n          .axis_prog_empty_thresh(10'b0),\n          .axis_prog_full(),\n          .axis_prog_full_thresh(10'b0),\n          .axis_rd_data_count(),\n          .axis_sbiterr(),\n          .axis_underflow(),\n          .axis_wr_data_count(),\n          .axi_ar_data_count(),\n          .axi_ar_dbiterr(),\n          .axi_ar_injectdbiterr(1'b0),\n          .axi_ar_injectsbiterr(1'b0),\n          .axi_ar_overflow(),\n          .axi_ar_prog_empty(),\n          .axi_ar_prog_empty_thresh(5'b0),\n          .axi_ar_prog_full(),\n          .axi_ar_prog_full_thresh(5'b0),\n          .axi_ar_rd_data_count(),\n          .axi_ar_sbiterr(),\n          .axi_ar_underflow(),\n          .axi_ar_wr_data_count(),\n          .axi_aw_data_count(),\n          .axi_aw_dbiterr(),\n          .axi_aw_injectdbiterr(1'b0),\n          .axi_aw_injectsbiterr(1'b0),\n          .axi_aw_overflow(),\n          .axi_aw_prog_empty(),\n          .axi_aw_prog_empty_thresh(5'b0),\n          .axi_aw_prog_full(),\n          .axi_aw_prog_full_thresh(5'b0),\n          .axi_aw_rd_data_count(),\n          .axi_aw_sbiterr(),\n          .axi_aw_underflow(),\n          .axi_aw_wr_data_count(),\n          .axi_b_data_count(),\n          .axi_b_dbiterr(),\n          .axi_b_injectdbiterr(1'b0),\n          .axi_b_injectsbiterr(1'b0),\n          .axi_b_overflow(),\n          .axi_b_prog_empty(),\n          .axi_b_prog_empty_thresh(4'b0),\n          .axi_b_prog_full(),\n          .axi_b_prog_full_thresh(4'b0),\n          .axi_b_rd_data_count(),\n          .axi_b_sbiterr(),\n          .axi_b_underflow(),\n          .axi_b_wr_data_count(),\n          .axi_r_data_count(),\n          .axi_r_dbiterr(),\n          .axi_r_injectdbiterr(1'b0),\n          .axi_r_injectsbiterr(1'b0),\n          .axi_r_overflow(),\n          .axi_r_prog_empty(),\n          .axi_r_prog_empty_thresh({P_READ_FIFO_DEPTH_LOG{1'b0}}),\n          .axi_r_prog_full(),\n          .axi_r_prog_full_thresh({P_READ_FIFO_DEPTH_LOG{1'b0}}),\n          .axi_r_rd_data_count(),\n          .axi_r_sbiterr(),\n          .axi_r_underflow(),\n          .axi_r_wr_data_count(),\n          .axi_w_data_count(),\n          .axi_w_dbiterr(),\n          .axi_w_injectdbiterr(1'b0),\n          .axi_w_injectsbiterr(1'b0),\n          .axi_w_overflow(),\n          .axi_w_prog_empty(),\n          .axi_w_prog_empty_thresh({P_WRITE_FIFO_DEPTH_LOG{1'b0}}),\n          .axi_w_prog_full(),\n          .axi_w_prog_full_thresh({P_WRITE_FIFO_DEPTH_LOG{1'b0}}),\n          .axi_w_rd_data_count(),\n          .axi_w_sbiterr(),\n          .axi_w_underflow(),\n          .axi_w_wr_data_count(),\n          .backup(1'b0),\n          .backup_marker(1'b0),\n          .clk(1'b0),\n          .data_count(),\n          .dbiterr(),\n          .din(18'b0),\n          .dout(),\n          .empty(),\n          .full(),\n          .injectdbiterr(1'b0),\n          .injectsbiterr(1'b0),\n          .int_clk(1'b0),\n          .m_axis_tdata(),\n          .m_axis_tdest(),\n          .m_axis_tid(),\n          .m_axis_tkeep(),\n          .m_axis_tlast(),\n          .m_axis_tready(1'b0),\n          .m_axis_tstrb(),\n          .m_axis_tuser(),\n          .m_axis_tvalid(),\n          .overflow(),\n          .prog_empty(),\n          .prog_empty_thresh(10'b0),\n          .prog_empty_thresh_assert(10'b0),\n          .prog_empty_thresh_negate(10'b0),\n          .prog_full(),\n          .prog_full_thresh(10'b0),\n          .prog_full_thresh_assert(10'b0),\n          .prog_full_thresh_negate(10'b0),\n          .rd_clk(1'b0),\n          .rd_data_count(),\n          .rd_en(1'b0),\n          .rd_rst(1'b0),\n          .rst(1'b0),\n          .sbiterr(),\n          .srst(1'b0),\n          .s_axis_tdata(64'b0),\n          .s_axis_tdest(4'b0),\n          .s_axis_tid(8'b0),\n          .s_axis_tkeep(4'b0),\n          .s_axis_tlast(1'b0),\n          .s_axis_tready(),\n          .s_axis_tstrb(4'b0),\n          .s_axis_tuser(4'b0),\n          .s_axis_tvalid(1'b0),\n          .underflow(),\n          .valid(),\n          .wr_ack(),\n          .wr_clk(1'b0),\n          .wr_data_count(),\n          .wr_en(1'b0),\n          .wr_rst(1'b0),\n          .wr_rst_busy(),\n          .rd_rst_busy(),\n          .sleep(1'b0)\n        );\n    end\n  endgenerate\nendmodule\n\n\n\n", "num_lines": 1957}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized AND with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_carry_and #\n  (\n   parameter         C_FAMILY                         = \"virtex6\"\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   )\n  (\n   input  wire        CIN,\n   input  wire        S,\n   output wire        COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n\n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n      assign COUT = CIN & S;\n      \n    end else begin : USE_FPGA\n      MUXCY and_inst \n      (\n       .O (COUT), \n       .CI (CIN), \n       .DI (1'b0), \n       .S (S)\n      ); \n      \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized AND with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_carry_latch_and #\n  (\n   parameter          C_FAMILY                         = \"virtex6\"\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   )\n  (\n   input  wire        CIN,\n   input  wire        I,\n   output wire        O\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n\n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n      assign O = CIN & ~I;\n      \n    end else begin : USE_FPGA\n      wire I_n;\n      \n      assign I_n = ~I;\n    \n      AND2B1L and2b1l_inst \n        (\n         .O(O),\n         .DI(CIN),\n         .SRI(I_n)\n        );\n      \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized OR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_carry_latch_or #\n  (\n   parameter          C_FAMILY                         = \"virtex6\"\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   )\n  (\n   input  wire        CIN,\n   input  wire        I,\n   output wire        O\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n      assign O = CIN | I;\n      \n    end else begin : USE_FPGA\n      OR2L or2l_inst1\n        (\n         .O(O),\n         .DI(CIN),\n         .SRI(I)\n        );\n      \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized OR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_carry_or #\n  (\n   parameter         C_FAMILY                         = \"virtex6\"\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   )\n  (\n   input  wire        CIN,\n   input  wire        S,\n   output wire        COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n      assign COUT = CIN | S;\n      \n    end else begin : USE_FPGA\n      wire S_n;\n      \n      assign S_n = ~S;\n    \n      MUXCY and_inst \n      (\n       .O (COUT), \n       .CI (CIN), \n       .DI (1'b1), \n       .S (S_n)\n      ); \n      \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_carry #\n  (\n   parameter         C_FAMILY                         = \"virtex6\"\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   )\n  (\n   input  wire        CIN,\n   input  wire        S,\n   input  wire        DI,\n   output wire        COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n      assign COUT = (CIN & S) | (DI & ~S);\n      \n    end else begin : USE_FPGA\n    \n      MUXCY and_inst \n      (\n       .O (COUT), \n       .CI (CIN), \n       .DI (DI), \n       .S (S)\n      ); \n      \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized 16/32 word deep FIFO.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_command_fifo #\n  (\n   parameter         C_FAMILY                        = \"virtex6\",\n   parameter integer C_ENABLE_S_VALID_CARRY          = 0,\n   parameter integer C_ENABLE_REGISTERED_OUTPUT      = 0,\n   parameter integer C_FIFO_DEPTH_LOG                = 5,      // FIFO depth = 2**C_FIFO_DEPTH_LOG\n                                                               // Range = [4:5].\n   parameter integer C_FIFO_WIDTH                    = 64      // Width of payload [1:512]\n   )\n  (\n   // Global inputs\n   input  wire                        ACLK,    // Clock\n   input  wire                        ARESET,  // Reset\n   // Information\n   output wire                        EMPTY,   // FIFO empty (all stages)\n   // Slave  Port\n   input  wire [C_FIFO_WIDTH-1:0]     S_MESG,  // Payload (may be any set of channel signals)\n   input  wire                        S_VALID, // FIFO push\n   output wire                        S_READY, // FIFO not full\n   // Master  Port\n   output wire [C_FIFO_WIDTH-1:0]     M_MESG,  // Payload\n   output wire                        M_VALID, // FIFO not empty\n   input  wire                        M_READY  // FIFO pop\n   );\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for data vector.\n  genvar addr_cnt;\n  genvar bit_cnt;\n  integer index;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIFO_DEPTH_LOG-1:0] addr;\n  wire                        buffer_Full;\n  wire                        buffer_Empty;\n  \n  wire                        next_Data_Exists;\n  reg                         data_Exists_I = 1'b0;\n  \n  wire                        valid_Write;\n  wire                        new_write;\n  \n  wire [C_FIFO_DEPTH_LOG-1:0] hsum_A;\n  wire [C_FIFO_DEPTH_LOG-1:0] sum_A;\n  wire [C_FIFO_DEPTH_LOG-1:0] addr_cy;\n\n  wire                        buffer_full_early;\n  \n  wire [C_FIFO_WIDTH-1:0]     M_MESG_I;   // Payload\n  wire                        M_VALID_I;  // FIFO not empty\n  wire                        M_READY_I;  // FIFO pop\n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Create Flags \n  /////////////////////////////////////////////////////////////////////////////\n  \n  assign buffer_full_early  = ( (addr == {{C_FIFO_DEPTH_LOG-1{1'b1}}, 1'b0}) & valid_Write & ~M_READY_I ) |\n                              ( buffer_Full & ~M_READY_I );\n\n  assign S_READY            = ~buffer_Full;\n\n  assign buffer_Empty       = (addr == {C_FIFO_DEPTH_LOG{1'b0}});\n\n  assign next_Data_Exists   = (data_Exists_I & ~buffer_Empty) |\n                              (buffer_Empty & S_VALID) |\n                              (data_Exists_I & ~(M_READY_I & data_Exists_I));\n\n  always @ (posedge ACLK) begin\n    if (ARESET) begin\n      data_Exists_I <= 1'b0;\n    end else begin\n      data_Exists_I <= next_Data_Exists;\n    end\n  end\n\n  assign M_VALID_I = data_Exists_I;\n  \n  // Select RTL or FPGA optimized instatiations for critical parts.\n  generate\n    if ( C_FAMILY == \"rtl\" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE\n      reg                         buffer_Full_q = 1'b0;\n      \n      assign valid_Write = S_VALID & ~buffer_Full;\n      \n      assign new_write = (S_VALID | ~buffer_Empty);\n     \n      assign addr_cy[0] = valid_Write;\n      \n      always @ (posedge ACLK) begin\n        if (ARESET) begin\n          buffer_Full_q <= 1'b0;\n        end else if ( data_Exists_I ) begin\n          buffer_Full_q <= buffer_full_early;\n        end\n      end\n      assign buffer_Full = buffer_Full_q;\n      \n    end else begin : USE_FPGA_VALID_WRITE\n      wire s_valid_dummy1;\n      wire s_valid_dummy2;\n      wire sel_s_valid;\n      wire sel_new_write;\n      wire valid_Write_dummy1;\n      wire valid_Write_dummy2;\n      \n      assign sel_s_valid = ~buffer_Full;\n      \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) s_valid_dummy_inst1\n        (\n         .CIN(S_VALID),\n         .S(1'b1),\n         .COUT(s_valid_dummy1)\n         );\n      \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) s_valid_dummy_inst2\n        (\n         .CIN(s_valid_dummy1),\n         .S(1'b1),\n         .COUT(s_valid_dummy2)\n         );\n      \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) valid_write_inst\n        (\n         .CIN(s_valid_dummy2),\n         .S(sel_s_valid),\n         .COUT(valid_Write)\n         );\n      \n      assign sel_new_write = ~buffer_Empty;\n       \n      generic_baseblocks_v2_1_0_carry_latch_or #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) new_write_inst\n        (\n         .CIN(valid_Write),\n         .I(sel_new_write),\n         .O(new_write)\n         );\n         \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) valid_write_dummy_inst1\n        (\n         .CIN(valid_Write),\n         .S(1'b1),\n         .COUT(valid_Write_dummy1)\n         );\n      \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) valid_write_dummy_inst2\n        (\n         .CIN(valid_Write_dummy1),\n         .S(1'b1),\n         .COUT(valid_Write_dummy2)\n         );\n      \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) valid_write_dummy_inst3\n        (\n         .CIN(valid_Write_dummy2),\n         .S(1'b1),\n         .COUT(addr_cy[0])\n         );\n      \n      FDRE #(\n       .INIT(1'b0)              // Initial value of register (1'b0 or 1'b1)\n       ) FDRE_I1 (\n       .Q(buffer_Full),         // Data output\n       .C(ACLK),                // Clock input\n       .CE(data_Exists_I),      // Clock enable input\n       .R(ARESET),              // Synchronous reset input\n       .D(buffer_full_early)    // Data input\n       );\n       \n    end\n  endgenerate\n      \n    \n  /////////////////////////////////////////////////////////////////////////////\n  // Create address pointer\n  /////////////////////////////////////////////////////////////////////////////\n\n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_ADDR\n    \n      reg  [C_FIFO_DEPTH_LOG-1:0] addr_q = {C_FIFO_DEPTH_LOG{1'b0}};\n      \n      always @ (posedge ACLK) begin\n        if (ARESET) begin\n          addr_q <= {C_FIFO_DEPTH_LOG{1'b0}};\n        end else if ( data_Exists_I ) begin\n          if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin\n            addr_q <= addr_q + 1'b1;\n          end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin\n            addr_q <= addr_q - 1'b1;\n          end\n          else begin\n            addr_q <= addr_q;\n          end\n        end\n        else begin\n          addr_q <= addr_q;\n        end\n      end\n      \n      assign addr = addr_q;\n      \n    end else begin : USE_FPGA_ADDR\n      for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN\n        assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write;\n        \n        // Don't need the last muxcy, addr_cy(last) is not used anywhere\n        if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY\n          MUXCY MUXCY_inst (\n           .DI(addr[addr_cnt]),\n           .CI(addr_cy[addr_cnt]),\n           .S(hsum_A[addr_cnt]),\n           .O(addr_cy[addr_cnt+1])\n           );\n           \n        end\n        else begin : NO_MUXCY\n        end\n        \n        XORCY XORCY_inst (\n         .LI(hsum_A[addr_cnt]),\n         .CI(addr_cy[addr_cnt]),\n         .O(sum_A[addr_cnt])\n         );\n        \n        FDRE #(\n         .INIT(1'b0)             // Initial value of register (1'b0 or 1'b1)\n         ) FDRE_inst (\n         .Q(addr[addr_cnt]),     // Data output\n         .C(ACLK),               // Clock input\n         .CE(data_Exists_I),     // Clock enable input\n         .R(ARESET),             // Synchronous reset input\n         .D(sum_A[addr_cnt])     // Data input\n         );\n        \n      end // end for bit_cnt\n    end // C_FAMILY\n  endgenerate\n      \n      \n  /////////////////////////////////////////////////////////////////////////////\n  // Data storage\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_FIFO\n      reg  [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0];\n      \n      always @ (posedge ACLK) begin\n        if ( valid_Write ) begin\n          for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin\n            data_srl[index+1] <= data_srl[index];\n          end\n          data_srl[0]   <= S_MESG;\n        end\n      end\n      \n      assign M_MESG_I = data_srl[addr];\n      \n    end else begin : USE_FPGA_FIFO\n      for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN\n        \n        if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32\n            SRLC32E # (\n             .INIT(32'h00000000)    // Initial Value of Shift Register\n            ) SRLC32E_inst (\n             .Q(M_MESG_I[bit_cnt]), // SRL data output\n             .Q31(),                // SRL cascade output pin\n             .A(addr),              // 5-bit shift depth select input\n             .CE(valid_Write),      // Clock enable input\n             .CLK(ACLK),            // Clock input\n             .D(S_MESG[bit_cnt])    // SRL data input\n            );\n        end else begin : USE_16\n            SRLC16E # (\n             .INIT(32'h00000000)    // Initial Value of Shift Register\n            ) SRLC16E_inst (\n             .Q(M_MESG_I[bit_cnt]), // SRL data output\n             .Q15(),                // SRL cascade output pin\n             .A0(addr[0]),          // 4-bit shift depth select input 0\n             .A1(addr[1]),          // 4-bit shift depth select input 1\n             .A2(addr[2]),          // 4-bit shift depth select input 2\n             .A3(addr[3]),          // 4-bit shift depth select input 3\n             .CE(valid_Write),      // Clock enable input\n             .CLK(ACLK),            // Clock input\n             .D(S_MESG[bit_cnt])    // SRL data input\n            );\n        end // C_FIFO_DEPTH_LOG\n      \n      end // end for bit_cnt\n    end // C_FAMILY\n  endgenerate\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Pipeline stage\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT\n      \n      wire [C_FIFO_WIDTH-1:0]     M_MESG_FF;    // Payload\n      wire                        M_VALID_FF;   // FIFO not empty\n      \n      // Select RTL or FPGA optimized instatiations for critical parts.\n      if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_OUTPUT_PIPELINE\n      \n        reg  [C_FIFO_WIDTH-1:0]     M_MESG_Q;   // Payload\n        reg                         M_VALID_Q = 1'b0;  // FIFO not empty\n        \n        always @ (posedge ACLK) begin\n          if (ARESET) begin\n            M_MESG_Q    <= {C_FIFO_WIDTH{1'b0}};\n            M_VALID_Q   <= 1'b0;\n          end else begin\n            if ( M_READY_I ) begin\n              M_MESG_Q    <= M_MESG_I;\n              M_VALID_Q   <= M_VALID_I;\n            end\n          end\n        end\n      \n        assign M_MESG_FF     = M_MESG_Q;\n        assign M_VALID_FF    = M_VALID_Q;\n        \n      end else begin : USE_FPGA_OUTPUT_PIPELINE\n      \n        reg  [C_FIFO_WIDTH-1:0]     M_MESG_CMB;   // Payload\n        reg                         M_VALID_CMB;  // FIFO not empty\n        \n        always @ *\n        begin\n          if ( M_READY_I ) begin\n            M_MESG_CMB  <= M_MESG_I;\n            M_VALID_CMB <= M_VALID_I;\n          end else begin\n            M_MESG_CMB  <= M_MESG_FF;\n            M_VALID_CMB <= M_VALID_FF;\n          end\n        end\n        \n        for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN\n              \n          FDRE #(\n           .INIT(1'b0)                    // Initial value of register (1'b0 or 1'b1)\n           ) FDRE_inst (\n           .Q(M_MESG_FF[bit_cnt]),        // Data output\n           .C(ACLK),                      // Clock input\n           .CE(1'b1),                     // Clock enable input\n           .R(ARESET),                    // Synchronous reset input\n           .D(M_MESG_CMB[bit_cnt])        // Data input\n           );\n        end // end for bit_cnt\n            \n        FDRE #(\n         .INIT(1'b0)                    // Initial value of register (1'b0 or 1'b1)\n         ) FDRE_inst (\n         .Q(M_VALID_FF),                // Data output\n         .C(ACLK),                      // Clock input\n         .CE(1'b1),                     // Clock enable input\n         .R(ARESET),                    // Synchronous reset input\n         .D(M_VALID_CMB)                // Data input\n         );\n      \n      end\n      \n      assign EMPTY      = ~M_VALID_I & ~M_VALID_FF;\n      assign M_MESG     = M_MESG_FF;\n      assign M_VALID    = M_VALID_FF;\n      assign M_READY_I  = ( M_READY & M_VALID_FF ) | ~M_VALID_FF;\n      \n    end else begin : NO_FF_OUT\n      \n      assign EMPTY      = ~M_VALID_I;\n      assign M_MESG     = M_MESG_I;\n      assign M_VALID    = M_VALID_I;\n      assign M_READY_I  = M_READY;\n      \n    end\n  endgenerate\n\nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_mask_static #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter         C_VALUE                          = 4'b0,\n                       // Static value to compare against.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] M,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar lut_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 3;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] m_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign m_local        = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = C_VALUE;\n      assign m_local        = M;\n    end\n    \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == \n                              ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[lut_cnt+1]),\n       .CIN   (carry_local[lut_cnt]),\n       .S     (sel[lut_cnt])\n      ); \n      \n    end // end for lut_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_mask #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   input  wire [C_DATA_WIDTH-1:0] M,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar lut_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 2;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] m_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign m_local        = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n      assign m_local        = M;\n    end\n  \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == \n                              ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[lut_cnt+1]),\n       .CIN   (carry_local[lut_cnt]),\n       .S     (sel[lut_cnt])\n      ); \n      \n    end // end for lut_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_sel_mask_static #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter         C_VALUE                          = 4'b0,\n                       // Static value to compare against.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire                    S,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   input  wire [C_DATA_WIDTH-1:0] M,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar lut_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 1;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] m_local;\n  wire [C_FIX_DATA_WIDTH-1:0] v_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign m_local        = {M,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign v_local        = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n      assign m_local        = M;\n      assign v_local        = C_VALUE;\n    end\n    \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==\n                                ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |\n                            ( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==\n                                ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[lut_cnt+1]),\n       .CIN   (carry_local[lut_cnt]),\n       .S     (sel[lut_cnt])\n      ); \n      \n    end // end for lut_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_sel_mask #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire                    S,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   input  wire [C_DATA_WIDTH-1:0] M,\n   input  wire [C_DATA_WIDTH-1:0] V,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar lut_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 1;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] m_local;\n  wire [C_FIX_DATA_WIDTH-1:0] v_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign m_local        = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign v_local        = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n      assign m_local        = M;\n      assign v_local        = V;\n    end\n    \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==\n                                ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |\n                            ( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==\n                                ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[lut_cnt+1]),\n       .CIN   (carry_local[lut_cnt]),\n       .S     (sel[lut_cnt])\n      ); \n      \n    end // end for lut_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_sel_static #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter         C_VALUE                          = 4'b0,\n                       // Static value to compare against.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire                    S,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar bit_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 2;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] v_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign v_local        = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n      assign v_local        = C_VALUE;\n    end\n    \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                                v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |\n                            ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                                v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[bit_cnt+1]),\n       .CIN   (carry_local[bit_cnt]),\n       .S     (sel[bit_cnt])\n      ); \n      \n    end // end for bit_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_sel #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire                    S,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   input  wire [C_DATA_WIDTH-1:0] V,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar bit_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 1;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] v_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign v_local        = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n      assign v_local        = V;\n    end\n  \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                                v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |\n                            ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                                v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[bit_cnt+1]),\n       .CIN   (carry_local[bit_cnt]),\n       .S     (sel[bit_cnt])\n      ); \n      \n    end // end for bit_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_static #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter         C_VALUE                          = 4'b0,\n                       // Static value to compare against.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar bit_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 6;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = C_VALUE;\n    end\n    \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                              b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[bit_cnt+1]),\n       .CIN   (carry_local[bit_cnt]),\n       .S     (sel[bit_cnt])\n      ); \n      \n    end // end for bit_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar bit_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 3;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n    end\n  \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                              b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[bit_cnt+1]),\n       .CIN   (carry_local[bit_cnt]),\n       .S     (sel[bit_cnt])\n      ); \n      \n    end // end for bit_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized Mux using MUXF7/8.\n//  Any generic_baseblocks_v2_1_0_mux ratio.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   mux_enc\n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_mux_enc #\n  (\n   parameter         C_FAMILY                       = \"rtl\",\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_RATIO                        = 4,\n                       // Mux select ratio. Can be any binary value (>= 1)\n   parameter integer C_SEL_WIDTH                    = 2,\n                       // Log2-ceiling of C_RATIO (>= 1)\n   parameter integer C_DATA_WIDTH                   = 1\n                       // Data width for generic_baseblocks_v2_1_0_comparator (>= 1)\n   )\n  (\n   input  wire [C_SEL_WIDTH-1:0]                    S,\n   input  wire [C_RATIO*C_DATA_WIDTH-1:0]           A,\n   output wire [C_DATA_WIDTH-1:0]                   O,\n   input  wire                                      OE\n   );\n  \n  wire [C_DATA_WIDTH-1:0] o_i;\n  genvar bit_cnt;\n  \n  function [C_DATA_WIDTH-1:0] f_mux\n    (\n     input [C_SEL_WIDTH-1:0] s,\n     input [C_RATIO*C_DATA_WIDTH-1:0] a\n     );\n    integer i;\n    reg [C_RATIO*C_DATA_WIDTH-1:0] carry;\n    begin\n      carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];\n      for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc\n        carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] = \n          carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |\n          ({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);\n      end\n      f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)];\n    end\n  endfunction\n  \n  function [C_DATA_WIDTH-1:0] f_mux4\n    (\n     input [1:0] s,\n     input [4*C_DATA_WIDTH-1:0] a\n     );\n    integer i;\n    reg [4*C_DATA_WIDTH-1:0] carry;\n    begin\n      carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];\n      for (i=1;i<4;i=i+1) begin : gen_carrychain_enc\n        carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] = \n          carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |\n          ({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);\n      end\n      f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3];\n    end\n  endfunction\n  \n  assign O = o_i & {C_DATA_WIDTH{OE}};  // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic)\n  \n  generate\n    if ( C_RATIO < 2 ) begin : gen_bypass\n      assign o_i = A;\n    end else if ( C_FAMILY == \"rtl\" || C_RATIO < 5 ) begin : gen_rtl\n      assign o_i = f_mux(S, A);\n      \n    end else begin : gen_fpga\n      wire [C_DATA_WIDTH-1:0] l;\n      wire [C_DATA_WIDTH-1:0] h;\n      wire [C_DATA_WIDTH-1:0] ll;\n      wire [C_DATA_WIDTH-1:0] lh;\n      wire [C_DATA_WIDTH-1:0] hl;\n      wire [C_DATA_WIDTH-1:0] hh;\n      \n      case (C_RATIO)\n        1, 5, 9, 13: \n          assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        2, 6, 10, 14:\n          assign hh = S[0] ? \n            A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :\n            A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ;\n        3, 7, 11, 15:\n          assign hh = S[1] ? \n            A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :\n            (S[0] ? \n              A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] :\n              A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] );\n        4, 8, 12, 16:\n          assign hh = S[1] ? \n            (S[0] ? \n              A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :\n              A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) :\n            (S[0] ? \n              A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] :\n              A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] );\n        17:\n          assign hh = S[1] ? \n            (S[0] ? \n              A[15*C_DATA_WIDTH +: C_DATA_WIDTH] :\n              A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) :\n            (S[0] ? \n              A[13*C_DATA_WIDTH +: C_DATA_WIDTH] :\n              A[12*C_DATA_WIDTH +: C_DATA_WIDTH] );\n        default:\n          assign hh = 0; \n      endcase\n\n      case (C_RATIO)\n        5, 6, 7, 8: begin\n          assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);\n          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8\n            MUXF7 mux_s2_inst \n            (\n             .I0  (l[bit_cnt]),\n             .I1  (hh[bit_cnt]),\n             .S   (S[2]),\n             .O   (o_i[bit_cnt])\n            ); \n          end\n        end\n          \n        9, 10, 11, 12: begin\n          assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);\n          assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);\n          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12\n            MUXF7 muxf_s2_low_inst \n            (\n             .I0  (ll[bit_cnt]),\n             .I1  (lh[bit_cnt]),\n             .S   (S[2]),\n             .O   (l[bit_cnt])\n            ); \n            MUXF8 muxf_s3_inst \n            (\n             .I0  (l[bit_cnt]),\n             .I1  (hh[bit_cnt]),\n             .S   (S[3]),\n             .O   (o_i[bit_cnt])\n            ); \n          end\n        end\n          \n        13,14,15,16: begin\n          assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);\n          assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);\n          assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);\n          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16\n            MUXF7 muxf_s2_low_inst \n            (\n             .I0  (ll[bit_cnt]),\n             .I1  (lh[bit_cnt]),\n             .S   (S[2]),\n             .O   (l[bit_cnt])\n            ); \n            MUXF7 muxf_s2_hi_inst \n            (\n             .I0  (hl[bit_cnt]),\n             .I1  (hh[bit_cnt]),\n             .S   (S[2]),\n             .O   (h[bit_cnt])\n            );\n          \n            MUXF8 muxf_s3_inst \n            (\n             .I0  (l[bit_cnt]),\n             .I1  (h[bit_cnt]),\n             .S   (S[3]),\n             .O   (o_i[bit_cnt])\n            ); \n          end\n        end\n          \n        17: begin\n          assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);  // 5-input mux\n          assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);\n          assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);\n          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17\n            MUXF7 muxf_s2_low_inst \n            (\n             .I0  (ll[bit_cnt]),\n             .I1  (lh[bit_cnt]),\n             .S   (S[2]),\n             .O   (l[bit_cnt])\n            ); \n            MUXF7 muxf_s2_hi_inst \n            (\n             .I0  (hl[bit_cnt]),\n             .I1  (hh[bit_cnt]),\n             .S   (S[2]),\n             .O   (h[bit_cnt])\n            ); \n            MUXF8 muxf_s3_inst \n            (\n             .I0  (l[bit_cnt]),\n             .I1  (h[bit_cnt]),\n             .S   (S[3]),\n             .O   (o_i[bit_cnt])\n            ); \n          end\n        end\n          \n        default:  // If RATIO > 17, use RTL\n          assign o_i = f_mux(S, A);\n      endcase\n    end  // gen_fpga\n  endgenerate\nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized Mux from 2:1 upto 16:1.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_mux #\n  (\n   parameter         C_FAMILY                         = \"rtl\",\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_SEL_WIDTH                      = 4,\n                       // Data width for comparator.\n   parameter integer C_DATA_WIDTH                     = 2\n                       // Data width for comparator.\n   )\n  (\n   input  wire [C_SEL_WIDTH-1:0]                    S,\n   input  wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0]  A,\n   output wire [C_DATA_WIDTH-1:0]                   O\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar bit_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" || C_SEL_WIDTH < 3 ) begin : USE_RTL\n      assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH];\n      \n    end else begin : USE_FPGA\n      \n      wire [C_DATA_WIDTH-1:0] C;\n      wire [C_DATA_WIDTH-1:0] D;\n      \n      // Lower half recursively.\n      generic_baseblocks_v2_1_0_mux # \n      (\n       .C_FAMILY      (C_FAMILY),\n       .C_SEL_WIDTH   (C_SEL_WIDTH-1),\n       .C_DATA_WIDTH  (C_DATA_WIDTH)\n      ) mux_c_inst \n      (\n       .S   (S[C_SEL_WIDTH-2:0]),\n       .A   (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]),\n       .O   (C)\n      ); \n      \n      // Upper half recursively.\n      generic_baseblocks_v2_1_0_mux # \n      (\n       .C_FAMILY      (C_FAMILY),\n       .C_SEL_WIDTH   (C_SEL_WIDTH-1),\n       .C_DATA_WIDTH  (C_DATA_WIDTH)\n      ) mux_d_inst \n      (\n       .S   (S[C_SEL_WIDTH-2:0]),\n       .A   (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]),\n       .O   (D)\n      ); \n      \n      // Generate instantiated generic_baseblocks_v2_1_0_mux components as required.\n      for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM\n        if ( C_SEL_WIDTH == 4 ) begin : USE_F8\n        \n          MUXF8 muxf8_inst \n          (\n           .I0  (C[bit_cnt]),\n           .I1  (D[bit_cnt]),\n           .S   (S[C_SEL_WIDTH-1]),\n           .O   (O[bit_cnt])\n          ); \n          \n        end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7\n      \n          MUXF7 muxf7_inst \n          (\n           .I0  (C[bit_cnt]),\n           .I1  (D[bit_cnt]),\n           .S   (S[C_SEL_WIDTH-1]),\n           .O   (O[bit_cnt])\n          ); \n          \n        end // C_SEL_WIDTH\n      end // end for bit_cnt\n    \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: nto1_mux.v\n//\n// Description: N:1 MUX based on either binary-encoded or one-hot select input\n//   One-hot mode does not protect against multiple active SEL_ONEHOT inputs.\n//   Note: All port signals changed to all-upper-case (w.r.t. prior version).\n//\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_nto1_mux #\n  (\n   parameter integer C_RATIO         =  1,  // Range: >=1\n   parameter integer C_SEL_WIDTH     =  1,  // Range: >=1; recommended: ceil_log2(C_RATIO)\n   parameter integer C_DATAOUT_WIDTH =  1,  // Range: >=1\n   parameter integer C_ONEHOT        =  0   // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)\n   )\n  (\n   input  wire [C_RATIO-1:0]                 SEL_ONEHOT,  // One-hot generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=1)\n   input  wire [C_SEL_WIDTH-1:0]             SEL,         // Binary-encoded generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=0)\n   input  wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN,          // Data input array (num_selections x data_width)\n   output wire [C_DATAOUT_WIDTH-1:0]         OUT          // Data output vector\n   );\n\n  wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;\n  genvar i;\n  \n  generate\n    if (C_ONEHOT == 0) begin : gen_encoded\n      assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1'b1:1'b0}} & IN[C_DATAOUT_WIDTH-1:0];\n      for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc\n        assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] = \n               carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |\n               {C_DATAOUT_WIDTH{(SEL==i)?1'b1:1'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];\n      end\n    end else begin : gen_onehot\n      assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];\n      for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot\n        assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] = \n               carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |\n               {C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];\n      end\n    end\n  endgenerate\n  assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:\n                     C_DATAOUT_WIDTH*(C_RATIO-1)];\nendmodule\n\n`default_nettype wire\n\n\n", "num_lines": 2931}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: addr_arbiter_sasd.v\n//\n// Description: \n//   Hybrid priority + round-robin arbiter.\n//   Read & write requests combined (read preferred) at each slot\n//   Muxes AR and AW channel payload inputs based on arbitration results.\n//-----------------------------------------------------------------------------\n//\n// Structure:\n//    addr_arbiter_sasd\n//      mux_enc\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_16_addr_arbiter_sasd #\n  (\n   parameter         C_FAMILY                         = \"none\", \n   parameter integer C_NUM_S                = 1, \n   parameter integer C_NUM_S_LOG                = 1, \n   parameter integer C_AMESG_WIDTH                 = 1, \n   parameter         C_GRANT_ENC        = 0,\n   parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY             = {C_NUM_S{32'h00000000}}\n                       // Arbitration priority among each SI slot. \n                       // Higher values indicate higher priority.\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 'h0-'hF.\n   )\n  (\n   // Global Signals\n   input  wire                                      ACLK,\n   input  wire                                      ARESET,\n   // Slave Ports\n   input  wire [C_NUM_S*C_AMESG_WIDTH-1:0]  S_AWMESG,\n   input  wire [C_NUM_S*C_AMESG_WIDTH-1:0]  S_ARMESG,\n   input  wire [C_NUM_S-1:0]                S_AWVALID,\n   output wire [C_NUM_S-1:0]                S_AWREADY,\n   input  wire [C_NUM_S-1:0]                S_ARVALID,\n   output wire [C_NUM_S-1:0]                S_ARREADY,\n   // Master Ports\n   output wire [C_AMESG_WIDTH-1:0]          M_AMESG,\n   output wire [C_NUM_S_LOG-1:0]            M_GRANT_ENC,\n   output wire [C_NUM_S-1:0]                M_GRANT_HOT,\n   output wire                              M_GRANT_RNW,\n   output wire                              M_GRANT_ANY,\n   output wire                              M_AWVALID,\n   input  wire                              M_AWREADY,\n   output wire                              M_ARVALID,\n   input  wire                              M_ARREADY\n   );\n   \n  // Generates a mask for all input slots that are priority based\n  function [C_NUM_S-1:0] f_prio_mask\n    (\n      input integer null_arg\n    );\n    reg   [C_NUM_S-1:0]            mask;\n    integer                        i;    \n    begin\n      mask = 0;    \n      for (i=0; i < C_NUM_S; i=i+1) begin\n        mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0);\n      end \n      f_prio_mask = mask;\n    end   \n  endfunction\n  \n  // Convert 16-bit one-hot to 4-bit binary\n  function [3:0] f_hot2enc\n    (\n      input [15:0]  one_hot\n    );\n    begin\n      f_hot2enc[0] = |(one_hot & 16'b1010101010101010);\n      f_hot2enc[1] = |(one_hot & 16'b1100110011001100);\n      f_hot2enc[2] = |(one_hot & 16'b1111000011110000);\n      f_hot2enc[3] = |(one_hot & 16'b1111111100000000);\n    end\n  endfunction\n\n  localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0);\n\n  reg                     m_valid_i = 1'b0;\n  reg [C_NUM_S-1:0]       s_ready_i = 0;\n  reg [C_NUM_S-1:0]       s_awvalid_reg = 0;\n  reg [C_NUM_S-1:0]       s_arvalid_reg = 0;\n  wire [15:0]             s_avalid;\n  wire                    m_aready;\n  wire [C_NUM_S-1:0]      rnw;\n  reg                     grant_rnw;\n  reg [C_NUM_S_LOG-1:0]   m_grant_enc_i;\n  reg [C_NUM_S-1:0]       m_grant_hot_i; \n  reg [C_NUM_S-1:0]       last_rr_hot;\n  reg                     any_grant;\n  reg                     any_prio;\n  reg [C_NUM_S-1:0]       which_prio_hot;\n  reg [C_NUM_S_LOG-1:0]   which_prio_enc;          \n  reg [4:0]               current_highest;\n  reg [15:0]              next_prio_hot;\n  reg [C_NUM_S_LOG-1:0]   next_prio_enc;    \n  reg                     found_prio;\n  wire [C_NUM_S-1:0]      valid_rr;\n  reg [15:0]              next_rr_hot;\n  reg [C_NUM_S_LOG-1:0]   next_rr_enc;    \n  reg [C_NUM_S*C_NUM_S-1:0] carry_rr;\n  reg [C_NUM_S*C_NUM_S-1:0] mask_rr;\n  reg                     found_rr;\n  wire [C_NUM_S-1:0]      next_hot;\n  wire [C_NUM_S_LOG-1:0]  next_enc;    \n  integer                 i;\n  wire  [C_AMESG_WIDTH-1:0] amesg_mux;\n  reg   [C_AMESG_WIDTH-1:0] m_amesg_i;\n  wire [C_NUM_S*C_AMESG_WIDTH-1:0] s_amesg;\n  genvar                  gen_si;\n\n  always @(posedge ACLK) begin\n    if (ARESET) begin\n      s_awvalid_reg <= 0;\n      s_arvalid_reg <= 0;\n    end else if (|s_ready_i) begin\n      s_awvalid_reg <= 0;\n      s_arvalid_reg <= 0;\n    end else begin\n      s_arvalid_reg <= S_ARVALID & ~s_awvalid_reg;\n      s_awvalid_reg <= S_AWVALID & ~s_arvalid_reg & (~S_ARVALID | s_awvalid_reg);\n    end\n  end\n  \n  assign s_avalid = S_AWVALID | S_ARVALID;\n  assign M_AWVALID = m_valid_i & ~grant_rnw;\n  assign M_ARVALID = m_valid_i & grant_rnw;\n  assign S_AWREADY = s_ready_i & {C_NUM_S{~grant_rnw}};\n  assign S_ARREADY = s_ready_i & {C_NUM_S{grant_rnw}};\n  assign M_GRANT_ENC = C_GRANT_ENC ? m_grant_enc_i : 0;\n  assign M_GRANT_HOT = m_grant_hot_i;\n  assign M_GRANT_RNW = grant_rnw;\n  assign rnw = S_ARVALID & ~s_awvalid_reg;\n  assign M_AMESG = m_amesg_i;\n  assign m_aready = grant_rnw ? M_ARREADY : M_AWREADY;\n  \n  generate\n    for (gen_si=0; gen_si<C_NUM_S; gen_si=gen_si+1) begin : gen_mesg_mux\n      assign s_amesg[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] = rnw[gen_si] ? S_ARMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] : S_AWMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH];\n    end  // gen_mesg_mux\n         \n    if (C_NUM_S>1) begin : gen_arbiter\n    \n      /////////////////////////////////////////////////////////////////////////////\n      // Grant a new request when there is none still pending.\n      // If no qualified requests found, de-assert M_VALID.\n      /////////////////////////////////////////////////////////////////////////////\n      \n      assign M_GRANT_ANY = any_grant;\n      assign next_hot = found_prio ? next_prio_hot : next_rr_hot;\n      assign next_enc = found_prio ? next_prio_enc : next_rr_enc;\n      \n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          m_valid_i <= 0;\n          s_ready_i <= 0;\n          m_grant_hot_i <= 0;\n          m_grant_enc_i <= 0;\n          any_grant <= 1'b0;\n          last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};\n          grant_rnw <= 1'b0;\n        end else begin\n          s_ready_i <= 0;\n          if (m_valid_i) begin\n            // Stall 1 cycle after each master-side completion.\n            if (m_aready) begin  // Master-side completion\n              m_valid_i <= 1'b0;\n              m_grant_hot_i <= 0;\n              any_grant <= 1'b0;\n            end\n          end else if (any_grant) begin\n            m_valid_i <= 1'b1;\n            s_ready_i <= m_grant_hot_i;  // Assert S_AW/READY for 1 cycle to complete SI address transfer\n          end else begin\n            if (found_prio | found_rr) begin\n              m_grant_hot_i <= next_hot;\n              m_grant_enc_i <= next_enc;\n              any_grant <= 1'b1;\n              grant_rnw <= |(rnw & next_hot);\n              if (~found_prio) begin\n                last_rr_hot <= next_rr_hot;\n              end\n            end\n          end\n        end\n      end\n    \n      /////////////////////////////////////////////////////////////////////////////\n      // Fixed Priority arbiter\n      // Selects next request to grant from among inputs with PRIO > 0, if any.\n      /////////////////////////////////////////////////////////////////////////////\n      \n      always @ * begin : ALG_PRIO\n        integer ip;\n        any_prio = 1'b0;\n        which_prio_hot = 0;        \n        which_prio_enc = 0;    \n        current_highest = 0;    \n        for (ip=0; ip < C_NUM_S; ip=ip+1) begin\n          if (P_PRIO_MASK[ip] & ({1'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest)) begin\n            if (s_avalid[ip]) begin\n              current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4];\n              any_prio = 1'b1;\n              which_prio_hot = 1'b1 << ip;\n              which_prio_enc = ip;\n            end\n          end   \n        end\n        found_prio = any_prio;\n        next_prio_hot = which_prio_hot;\n        next_prio_enc = which_prio_enc;\n      end\n     \n      /////////////////////////////////////////////////////////////////////////////\n      // Round-robin arbiter\n      // Selects next request to grant from among inputs with PRIO = 0, if any.\n      /////////////////////////////////////////////////////////////////////////////\n      \n      assign valid_rr = ~P_PRIO_MASK & s_avalid;\n      \n      always @ * begin : ALG_RR\n        integer ir, jr, nr;\n        next_rr_hot = 0;\n        for (ir=0;ir<C_NUM_S;ir=ir+1) begin\n          nr = (ir>0) ? (ir-1) : (C_NUM_S-1);\n          carry_rr[ir*C_NUM_S] = last_rr_hot[nr];\n          mask_rr[ir*C_NUM_S] = ~valid_rr[nr];\n          for (jr=1;jr<C_NUM_S;jr=jr+1) begin\n            nr = (ir-jr > 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1);\n            carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]);\n            if (jr < C_NUM_S-1) begin\n              mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr];\n            end\n          end   \n          next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1];\n        end\n        next_rr_enc = f_hot2enc(next_rr_hot);\n        found_rr = |(next_rr_hot);\n      end\n  \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_S),\n         .C_SEL_WIDTH   (C_NUM_S_LOG),\n         .C_DATA_WIDTH  (C_AMESG_WIDTH)\n        ) si_amesg_mux_inst \n        (\n         .S   (next_enc),\n         .A   (s_amesg),\n         .O   (amesg_mux),\n         .OE  (1'b1)\n        ); \n        \n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          m_amesg_i <= 0;\n        end else if (~any_grant) begin\n          m_amesg_i <= amesg_mux;\n        end\n      end\n    \n    end else begin : gen_no_arbiter\n      \n      assign M_GRANT_ANY = m_grant_hot_i;\n\n      always @ (posedge ACLK) begin\n        if (ARESET) begin\n          m_valid_i <= 1'b0;\n          s_ready_i <= 1'b0;\n          m_grant_enc_i <= 0;\n          m_grant_hot_i <= 1'b0;\n          grant_rnw <= 1'b0;\n        end else begin\n          s_ready_i <= 1'b0;\n          if (m_valid_i) begin\n            if (m_aready) begin\n              m_valid_i <= 1'b0;\n              m_grant_hot_i <= 1'b0;\n            end\n          end else if (m_grant_hot_i) begin\n            m_valid_i <= 1'b1;\n            s_ready_i[0] <= 1'b1;  // Assert S_AW/READY for 1 cycle to complete SI address transfer\n          end else if (s_avalid[0]) begin\n            m_grant_hot_i <= 1'b1;\n            grant_rnw <= rnw[0];\n          end\n        end\n      end\n      \n      always @ (posedge ACLK) begin\n        if (ARESET) begin\n          m_amesg_i <= 0;\n        end else if (~m_grant_hot_i) begin\n          m_amesg_i <= s_amesg;\n        end\n      end\n    \n    end  // gen_arbiter\n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: addr_arbiter.v\n//\n// Description: \n//   Instantiates generic priority encoder.\n//   Each request is qualified if its target has not reached its issuing limit.\n//   Muxes mesg and target inputs based on arbitration results.\n//-----------------------------------------------------------------------------\n//\n// Structure:\n//    addr_arbiter\n//      mux_enc\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_16_addr_arbiter #\n  (\n   parameter         C_FAMILY                         = \"none\", \n   parameter integer C_NUM_S                = 1, \n   parameter integer C_NUM_S_LOG                = 1, \n   parameter integer C_NUM_M               = 1, \n   parameter integer C_MESG_WIDTH                 = 1, \n   parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY             = {C_NUM_S{32'h00000000}}\n                       // Arbitration priority among each SI slot. \n                       // Higher values indicate higher priority.\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 'h0-'hF.\n   )\n  (\n   // Global Signals\n   input  wire                                      ACLK,\n   input  wire                                      ARESET,\n   // Slave Ports\n   input  wire [C_NUM_S*C_MESG_WIDTH-1:0]  S_MESG,\n   input  wire [C_NUM_S*C_NUM_M-1:0]                S_TARGET_HOT,\n   input  wire [C_NUM_S-1:0]                S_VALID,\n   input  wire [C_NUM_S-1:0]                S_VALID_QUAL,\n   output wire [C_NUM_S-1:0]                S_READY,\n   // Master Ports\n   output wire [C_MESG_WIDTH-1:0]                    M_MESG,\n   output wire [C_NUM_M-1:0]                           M_TARGET_HOT,\n   output wire [C_NUM_S_LOG-1:0]                      M_GRANT_ENC,\n   output wire                                        M_VALID,\n   input  wire                                        M_READY,\n   // Sideband input\n   input  wire [C_NUM_M-1:0]                ISSUING_LIMIT\n   );\n   \n  // Generates a mask for all input slots that are priority based\n  function [C_NUM_S-1:0] f_prio_mask\n    (\n      input integer null_arg\n    );\n    reg   [C_NUM_S-1:0]            mask;\n    integer                        i;    \n    begin\n      mask = 0;    \n      for (i=0; i < C_NUM_S; i=i+1) begin\n        mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0);\n      end \n      f_prio_mask = mask;\n    end   \n  endfunction\n  \n  // Convert 16-bit one-hot to 4-bit binary\n  function [3:0] f_hot2enc\n    (\n      input [15:0]  one_hot\n    );\n    begin\n      f_hot2enc[0] = |(one_hot & 16'b1010101010101010);\n      f_hot2enc[1] = |(one_hot & 16'b1100110011001100);\n      f_hot2enc[2] = |(one_hot & 16'b1111000011110000);\n      f_hot2enc[3] = |(one_hot & 16'b1111111100000000);\n    end\n  endfunction\n\n  localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0);\n\n  reg                     m_valid_i = 1'b0;\n  reg [C_NUM_S-1:0]       s_ready_i = 0;\n  reg [C_NUM_S-1:0]       qual_reg;\n  reg [C_NUM_S-1:0]       grant_hot; \n  reg [C_NUM_S-1:0]       last_rr_hot;\n  reg                     any_grant;\n  reg                     any_prio;\n  reg                     found_prio;\n  reg [C_NUM_S-1:0]       which_prio_hot;\n  reg [C_NUM_S-1:0]       next_prio_hot;\n  reg [C_NUM_S_LOG-1:0]   which_prio_enc;          \n  reg [C_NUM_S_LOG-1:0]   next_prio_enc;    \n  reg [4:0]               current_highest;\n  wire [C_NUM_S-1:0]      valid_rr;\n  reg [15:0]              next_rr_hot;\n  reg [C_NUM_S_LOG-1:0]   next_rr_enc;    \n  reg [C_NUM_S*C_NUM_S-1:0] carry_rr;\n  reg [C_NUM_S*C_NUM_S-1:0] mask_rr;\n  reg                     found_rr;\n  wire [C_NUM_S-1:0]      next_hot;\n  wire [C_NUM_S_LOG-1:0]  next_enc;    \n  reg                     prio_stall;\n  integer                 i;\n  wire [C_NUM_S-1:0]      valid_qual_i;\n  reg  [C_NUM_S_LOG-1:0]  m_grant_enc_i;\n  reg  [C_NUM_M-1:0]      m_target_hot_i;\n  wire [C_NUM_M-1:0]      m_target_hot_mux;\n  reg  [C_MESG_WIDTH-1:0] m_mesg_i;\n  wire [C_MESG_WIDTH-1:0] m_mesg_mux;\n  genvar                  gen_si;\n\n  assign M_VALID = m_valid_i;\n  assign S_READY = s_ready_i;\n  assign M_GRANT_ENC = m_grant_enc_i;\n  assign M_MESG = m_mesg_i;\n  assign M_TARGET_HOT = m_target_hot_i;\n  \n  generate\n    if (C_NUM_S>1) begin : gen_arbiter\n      \n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          qual_reg <= 0;\n        end else begin \n          qual_reg <= valid_qual_i | ~S_VALID; // Don't disqualify when bus not VALID (valid_qual_i would be garbage)\n        end\n      end\n    \n      for (gen_si=0; gen_si<C_NUM_S; gen_si=gen_si+1) begin : gen_req_qual\n        assign valid_qual_i[gen_si] = S_VALID_QUAL[gen_si] & (|(S_TARGET_HOT[gen_si*C_NUM_M+:C_NUM_M] & ~ISSUING_LIMIT));\n      end\n    \n      /////////////////////////////////////////////////////////////////////////////\n      // Grant a new request when there is none still pending.\n      // If no qualified requests found, de-assert M_VALID.\n      /////////////////////////////////////////////////////////////////////////////\n      \n      assign next_hot = found_prio ? next_prio_hot : next_rr_hot;\n      assign next_enc = found_prio ? next_prio_enc : next_rr_enc;\n      \n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          m_valid_i <= 0;\n          s_ready_i <= 0;\n          grant_hot <= 0;\n          any_grant <= 1'b0;\n          m_grant_enc_i <= 0;\n          last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};\n          m_target_hot_i <= 0;\n        end else begin\n          s_ready_i <= 0;\n          if (m_valid_i) begin\n            // Stall 1 cycle after each master-side completion.\n            if (M_READY) begin  // Master-side completion\n              m_valid_i <= 1'b0;\n              grant_hot <= 0;\n              any_grant <= 1'b0;\n            end\n          end else if (any_grant) begin\n            m_valid_i <= 1'b1;\n            s_ready_i <= grant_hot;  // Assert S_AW/READY for 1 cycle to complete SI address transfer (regardless of M_AREADY)\n          end else begin\n            if ((found_prio | found_rr) & ~prio_stall) begin\n              // Waste 1 cycle and re-arbitrate if target of highest prio hit issuing limit in previous cycle (valid_qual_i).\n              if (|(next_hot & valid_qual_i)) begin  \n                grant_hot <= next_hot;\n                m_grant_enc_i <= next_enc;\n                any_grant <= 1'b1;\n                if (~found_prio) begin\n                  last_rr_hot <= next_rr_hot;\n                end\n                m_target_hot_i <= m_target_hot_mux;\n              end\n            end\n          end\n        end\n      end\n    \n      /////////////////////////////////////////////////////////////////////////////\n      // Fixed Priority arbiter\n      // Selects next request to grant from among inputs with PRIO > 0, if any.\n      /////////////////////////////////////////////////////////////////////////////\n          \n      always @ * begin : ALG_PRIO\n        integer ip;\n        any_prio = 1'b0;\n        prio_stall = 1'b0;\n        which_prio_hot = 0;        \n        which_prio_enc = 0;    \n        current_highest = 0;    \n        for (ip=0; ip < C_NUM_S; ip=ip+1) begin\n          // Disqualify slot if target hit issuing limit (pass to lower prio slot).\n          if (P_PRIO_MASK[ip] & S_VALID[ip] & qual_reg[ip]) begin\n            if ({1'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest) begin\n              current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4];\n              // Stall 1 cycle when highest prio is recovering from SI-side handshake.\n              // (Do not allow lower-prio slot to win arbitration.)\n              if (s_ready_i[ip]) begin\n                any_prio = 1'b0;\n                prio_stall = 1'b1;\n                which_prio_hot = 0;\n                which_prio_enc = 0;\n              end else begin\n                any_prio = 1'b1;\n                which_prio_hot = 1'b1 << ip;\n                which_prio_enc = ip;\n              end\n            end\n          end   \n        end\n        found_prio = any_prio;\n        next_prio_hot = which_prio_hot;\n        next_prio_enc = which_prio_enc;\n      end\n     \n      /////////////////////////////////////////////////////////////////////////////\n      // Round-robin arbiter\n      // Selects next request to grant from among inputs with PRIO = 0, if any.\n      /////////////////////////////////////////////////////////////////////////////\n      \n      // Disqualify slot if target hit issuing limit 2 or more cycles earlier (pass to next RR slot).\n      // Disqualify for 1 cycle a slot that is recovering from SI-side handshake (s_ready_i),\n      //   and allow arbitration to pass to any other RR requester.\n      assign valid_rr = ~P_PRIO_MASK & S_VALID & ~s_ready_i & qual_reg;\n      \n      always @ * begin : ALG_RR\n        integer ir, jr, nr;\n        next_rr_hot = 0;\n        for (ir=0;ir<C_NUM_S;ir=ir+1) begin\n          nr = (ir>0) ? (ir-1) : (C_NUM_S-1);\n          carry_rr[ir*C_NUM_S] = last_rr_hot[nr];\n          mask_rr[ir*C_NUM_S] = ~valid_rr[nr];\n          for (jr=1;jr<C_NUM_S;jr=jr+1) begin\n            nr = (ir-jr > 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1);\n            carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]);\n            if (jr < C_NUM_S-1) begin\n              mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr];\n            end\n          end   \n          next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1];\n        end\n        next_rr_enc = f_hot2enc(next_rr_hot);\n        found_rr = |(next_rr_hot);\n      end\n  \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_S),\n         .C_SEL_WIDTH   (C_NUM_S_LOG),\n         .C_DATA_WIDTH  (C_MESG_WIDTH)\n        ) mux_mesg \n        (\n         .S   (m_grant_enc_i),\n         .A   (S_MESG),\n         .O   (m_mesg_mux),\n         .OE  (1'b1)\n        ); \n        \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_S),\n         .C_SEL_WIDTH   (C_NUM_S_LOG),\n         .C_DATA_WIDTH  (C_NUM_M)\n        ) si_amesg_mux_inst \n        (\n         .S   (next_enc),\n         .A   (S_TARGET_HOT),\n         .O   (m_target_hot_mux),\n         .OE  (1'b1)\n        ); \n        \n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          m_mesg_i <= 0;\n        end else if (~m_valid_i) begin\n          m_mesg_i <= m_mesg_mux;\n        end\n      end\n    \n    end else begin : gen_no_arbiter\n      \n      assign valid_qual_i = S_VALID_QUAL & |(S_TARGET_HOT & ~ISSUING_LIMIT);\n      \n      always @ (posedge ACLK) begin\n        if (ARESET) begin\n          m_valid_i <= 1'b0;\n          s_ready_i <= 1'b0;\n          m_grant_enc_i <= 0;\n        end else begin\n          s_ready_i <= 1'b0;\n          if (m_valid_i) begin\n            if (M_READY) begin\n              m_valid_i <= 1'b0;\n            end\n          end else if (S_VALID[0] & valid_qual_i[0] & ~s_ready_i) begin\n            m_valid_i <= 1'b1;\n            s_ready_i <= 1'b1;\n            m_target_hot_i <= S_TARGET_HOT;\n          end\n        end\n      end\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          m_mesg_i <= 0;\n        end else if (~m_valid_i) begin\n          m_mesg_i <= S_MESG;\n        end\n      end\n      \n      \n    end  // gen_arbiter\n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: Addr Decoder\n// Each received address is compared to base and high address pairs for each \n//   of a set of decode targets. \n// The matching target's index (if any) is output combinatorially.\n// If the decode is successful (matches any target), the MATCH output is asserted.\n// For each target, a set of alternative address ranges may be specified.\n// The base and high address pairs are formatted as a pair of 2-dimensional arrays,\n//   alternative address ranges iterate within each target.\n// The alternative range which matches the address is also output as REGION.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   addr_decoder\n//      comparator_static\n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_16_addr_decoder #\n  (\n   parameter         C_FAMILY          = \"none\",\n   parameter integer C_NUM_TARGETS     = 2,  // Number of decode targets = [1:16]\n   parameter integer C_NUM_TARGETS_LOG = 1,  // Log2(C_NUM_TARGETS)\n   parameter integer C_NUM_RANGES      = 1, // Number of alternative ranges that\n                                             //    can match each target [1:16]\n   parameter integer C_ADDR_WIDTH      = 32, // Width of decoder operand and of\n                                             //   each base and high address [2:64]\n   parameter integer C_TARGET_ENC      = 0,  // Enable encoded target output\n   parameter integer C_TARGET_HOT      = 1,  // Enable 1-hot target output\n   parameter integer C_REGION_ENC      = 0,   // Enable REGION output\n   parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}}, \n   parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}}, \n   parameter [C_NUM_TARGETS:0]    C_TARGET_QUAL                 = {C_NUM_TARGETS{1'b1}},\n                       // Indicates whether each target has connectivity.\n                       // Format: C_NUM_TARGETS{Bit1}.\n   parameter integer   C_RESOLUTION                 = 0,\n                       // Number of low-order ADDR bits that can be ignored when decoding.\n   parameter integer   C_COMPARATOR_THRESHOLD       = 6\n                       // Number of decoded ADDR bits above which will implement comparator_static.\n   )\n  (\n   input  wire [C_ADDR_WIDTH-1:0]      ADDR,        // Decoder input operand\n   output wire [C_NUM_TARGETS-1:0]     TARGET_HOT,  // Target matching address (1-hot)\n   output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC,  // Target matching address (encoded)\n   output wire                         MATCH,       // Decode successful\n   output wire [3:0]                   REGION      // Range within target matching address (encoded)\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  genvar target_cnt;\n  genvar region_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Function to detect addrs is in the addressable range.\n  // Only compare 4KB page address (ignore low-order 12 bits)\n  function  decode_address;\n    input [C_ADDR_WIDTH-1:0] base, high, addr;\n    reg   [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask;\n    reg   [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page;\n    reg   [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page;\n    reg   [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page;\n  begin\n    addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];\n    base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];\n    high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];\n    if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin\n      decode_address = 1'b0;\n    end else begin\n      mask  = base_page ^ high_page;\n      if ( (base_page & ~mask) == (addr_page & ~mask) ) begin\n        decode_address = 1'b1;\n      end else begin\n        decode_address = 1'b0;\n      end\n    end\n  end\n  endfunction\n  \n  // Generates a binary coded from onehotone encoded\n  function [3:0] f_hot2enc\n    (\n      input [15:0]  one_hot\n    );\n    begin\n      f_hot2enc[0] = |(one_hot & 16'b1010101010101010);\n      f_hot2enc[1] = |(one_hot & 16'b1100110011001100);\n      f_hot2enc[2] = |(one_hot & 16'b1111000011110000);\n      f_hot2enc[3] = |(one_hot & 16'b1111111100000000);\n    end\n  endfunction\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  wire [C_NUM_TARGETS-1:0]              TARGET_HOT_I;     // Target matching address (1-hot).\n  wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT;      // For address hit (1-hot).\n  wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG;  // For address hit (1-hot).\n  wire [C_NUM_RANGES-1:0]               REGION_HOT;       // Reginon matching address (1-hot).\n  wire [3:0]                            TARGET_ENC_I;     // Internal version of encoded hit. \n  /////////////////////////////////////////////////////////////////////////////\n  // Generate detection per region per target.\n  generate\n    for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target\n      for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region\n        // Detect if this is an address hit (including used region decoding).\n        if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static\n          if (C_TARGET_QUAL[target_cnt] &&\n              ((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) ||\n               (C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range\n            generic_baseblocks_v2_1_0_comparator_static #\n            (\n            .C_FAMILY(\"rtl\"),\n            .C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]),\n            .C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION)\n            ) addr_decode_comparator\n            (\n            .CIN(1'b1),\n            .A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] &\n              ~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^\n                C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])),\n            .COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt])\n            );\n          end else begin : gen_null_range\n            assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0;\n          end\n        end else begin : gen_no_comparator_static\n          assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ? \n                                    decode_address(\n                                      C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],\n                                      C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],\n                                      ADDR)\n                                    : 1'b0;\n        end  // gen_comparator_static\n        assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt];\n      end  // gen_region\n      \n      // All regions are non-overlapping\n      // => Or all the region detections for this target to determine if it is a hit.\n      assign TARGET_HOT_I[target_cnt]  = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES];\n    end  // gen_target\n    \n    for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region_or\n      assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS];\n    end  // gen_region_or\n  endgenerate\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // All regions are non-overlapping\n  // => Or all the target hit detections if it is a match.\n  assign MATCH = | TARGET_HOT_I;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Assign conditional onehot target output signal.\n  generate\n    if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT\n      assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1;\n    end else begin : NO_TARGET_ONEHOT\n      assign TARGET_HOT = {C_NUM_TARGETS{1'b0}};\n    end\n  endgenerate\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Assign conditional encoded target output signal.\n  generate\n    if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED\n      assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I);\n      assign TARGET_ENC   = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0];\n    end else begin : NO_TARGET_ENCODED\n      assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}};\n    end\n  endgenerate\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Assign conditional encoded region output signal.\n  generate\n    if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED\n      assign REGION = f_hot2enc(REGION_HOT);\n    end else begin : NO_REGION_ENCODED\n      assign REGION = 4'b0;\n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Round-Robin Arbiter for R and B channel responses\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    arbiter_resp\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_16_arbiter_resp #\n  (\n   parameter         C_FAMILY       = \"none\",\n   parameter integer C_NUM_S        = 4,      // Number of requesting Slave ports = [2:16]\n   parameter integer C_NUM_S_LOG    = 2,      // Log2(C_NUM_S)\n   parameter integer C_GRANT_ENC    = 0,      // Enable encoded grant output\n   parameter integer C_GRANT_HOT    = 1       // Enable 1-hot grant output\n   )\n  (\n   // Global Inputs\n   input  wire                     ACLK,\n   input  wire                     ARESET,\n   // Slave  Ports\n   input  wire [C_NUM_S-1:0]       S_VALID,      // Request from each slave\n   output wire [C_NUM_S-1:0]       S_READY,      // Grant response to each slave\n   // Master Ports\n   output wire [C_NUM_S_LOG-1:0]   M_GRANT_ENC,  // Granted slave index (encoded)\n   output wire [C_NUM_S-1:0]       M_GRANT_HOT,  // Granted slave index (1-hot)\n   output wire                     M_VALID,      // Grant event\n   input  wire                     M_READY\n   );\n\n  // Generates a binary coded from onehotone encoded\n  function [4:0] f_hot2enc\n    (\n      input [16:0]  one_hot\n    );\n    begin\n      f_hot2enc[0] = |(one_hot & 17'b01010101010101010);\n      f_hot2enc[1] = |(one_hot & 17'b01100110011001100);\n      f_hot2enc[2] = |(one_hot & 17'b01111000011110000);\n      f_hot2enc[3] = |(one_hot & 17'b01111111100000000);\n      f_hot2enc[4] = |(one_hot & 17'b10000000000000000);\n    end\n  endfunction\n\n  (* use_clock_enable = \"yes\" *)\n  reg [C_NUM_S-1:0]      chosen = 0;\n  \n  wire [C_NUM_S-1:0]     grant_hot; \n  wire                   master_selected; \n  wire                   active_master;\n  wire                   need_arbitration;\n  wire                   m_valid_i;\n  wire [C_NUM_S-1:0]     s_ready_i;\n  wire                   access_done;\n  reg [C_NUM_S-1:0]      last_rr_hot;\n  wire [C_NUM_S-1:0]     valid_rr;\n  reg [C_NUM_S-1:0]      next_rr_hot;\n  reg [C_NUM_S*C_NUM_S-1:0] carry_rr;\n  reg [C_NUM_S*C_NUM_S-1:0] mask_rr;\n  integer                 i;\n  integer                 j;\n  integer                 n;\n  \n  /////////////////////////////////////////////////////////////////////////////\n  //   \n  // Implementation of the arbiter outputs independant of arbitration\n  //\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Mask the current requests with the chosen master\n  assign grant_hot        = chosen & S_VALID;\n\n  // See if we have a selected master\n  assign master_selected  = |grant_hot[0+:C_NUM_S];\n\n  // See if we have current requests\n  assign active_master    = |S_VALID;\n\n  // Access is completed\n  assign access_done = m_valid_i & M_READY;\n  \n  // Need to handle if we drive S_ready combinatorial and without an IDLE state\n\n  // Drive S_READY on the master who has been chosen when we get a M_READY\n  assign s_ready_i = {C_NUM_S{M_READY}} & grant_hot[0+:C_NUM_S];\n\n  // Drive M_VALID if we have a selected master\n  assign m_valid_i = master_selected;\n                \n  // If we have request and not a selected master, we need to arbitrate a new chosen \n  assign need_arbitration = (active_master & ~master_selected) | access_done;\n\n  // need internal signals of the output signals\n  assign M_VALID = m_valid_i;\n  assign S_READY = s_ready_i;\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Assign conditional onehot target output signal.\n  assign M_GRANT_HOT = (C_GRANT_HOT == 1) ? grant_hot[0+:C_NUM_S] : {C_NUM_S{1'b0}};\n  /////////////////////////////////////////////////////////////////////////////\n  // Assign conditional encoded target output signal.\n  assign M_GRANT_ENC = (C_GRANT_ENC == 1) ? f_hot2enc(grant_hot) : {C_NUM_S_LOG{1'b0}};\n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Select a new chosen when we need to arbitrate\n  // If we don't have a new chosen, keep the old one since it's a good chance\n  // that it will do another request\n  always @(posedge ACLK)\n    begin\n      if (ARESET) begin\n        chosen <= {C_NUM_S{1'b0}};\n        last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};\n      end else if (need_arbitration) begin\n        chosen <= next_rr_hot;   \n        if (|next_rr_hot) last_rr_hot <= next_rr_hot;\n      end\n    end\n\n  assign valid_rr =  S_VALID;\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Round-robin arbiter\n  // Selects next request to grant from among inputs with PRIO = 0, if any.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  always @ * begin\n    next_rr_hot = 0;\n    for (i=0;i<C_NUM_S;i=i+1) begin\n      n = (i>0) ? (i-1) : (C_NUM_S-1);\n      carry_rr[i*C_NUM_S] = last_rr_hot[n];\n      mask_rr[i*C_NUM_S] = ~valid_rr[n];\n      for (j=1;j<C_NUM_S;j=j+1) begin\n        n = (i-j > 0) ? (i-j-1) : (C_NUM_S+i-j-1);\n        carry_rr[i*C_NUM_S+j] = carry_rr[i*C_NUM_S+j-1] | (last_rr_hot[n] & mask_rr[i*C_NUM_S+j-1]);\n        if (j < C_NUM_S-1) begin\n          mask_rr[i*C_NUM_S+j] = mask_rr[i*C_NUM_S+j-1] & ~valid_rr[n];\n        end\n      end   \n      next_rr_hot[i] = valid_rr[i] & carry_rr[(i+1)*C_NUM_S-1];\n    end\n  end\n  \nendmodule\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: crossbar_sasd.v\n//\n// Description: \n//   This module is a M-master to N-slave AXI axi_crossbar_v2_1_16_crossbar switch.\n//   Single transaction issuing, single arbiter (both W&R), single data pathways.\n//   The interface of this module consists of a vectored slave and master interface\n//     in which all slots are sized and synchronized to the native width and clock \n//     of the interconnect, and are all AXI4 protocol.\n//   All width, clock and protocol conversions are done outside this block, as are\n//     any pipeline registers or data FIFOs.\n//   This module contains all arbitration, decoders and channel multiplexing logic.\n//     It also contains the diagnostic registers and control interface.\n//\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    crossbar_sasd\n//      addr_arbiter_sasd\n//        mux_enc\n//      addr_decoder\n//        comparator_static\n//      splitter\n//      mux_enc\n//      axic_register_slice\n//      decerr_slave\n//      \n//-----------------------------------------------------------------------------\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_16_crossbar_sasd #\n  (\n   parameter         C_FAMILY                       = \"none\", \n   parameter integer C_NUM_SLAVE_SLOTS              =   1, \n   parameter integer C_NUM_MASTER_SLOTS             =   1, \n   parameter integer C_NUM_ADDR_RANGES              = 1,\n   parameter integer C_AXI_ID_WIDTH                   = 1, \n   parameter integer C_AXI_ADDR_WIDTH                 = 32, \n   parameter integer C_AXI_DATA_WIDTH = 32, \n   parameter integer C_AXI_PROTOCOL                 = 0, \n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}}, \n   parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},\n   parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS      = 0,\n   parameter integer C_AXI_AWUSER_WIDTH               = 1,\n   parameter integer C_AXI_ARUSER_WIDTH               = 1,\n   parameter integer C_AXI_WUSER_WIDTH                = 1,\n   parameter integer C_AXI_RUSER_WIDTH                = 1,\n   parameter integer C_AXI_BUSER_WIDTH                = 1,\n   parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE           = {C_NUM_SLAVE_SLOTS{1'b1}}, \n   parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ            = {C_NUM_SLAVE_SLOTS{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE           = {C_NUM_MASTER_SLOTS{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ            = {C_NUM_MASTER_SLOTS{1'b1}}, \n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY             = {C_NUM_SLAVE_SLOTS{32'h00000000}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE                   = {C_NUM_MASTER_SLOTS{32'h00000000}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE            = {C_NUM_MASTER_SLOTS{32'h00000000}},\n   parameter integer C_R_REGISTER               = 0,\n   parameter integer C_RANGE_CHECK                    = 0,\n   parameter integer C_ADDR_DECODE                    = 0,\n   parameter integer C_DEBUG              = 1\n   )\n  (\n   // Global Signals\n   input  wire                                                    ACLK,\n   input  wire                                                    ARESETN,\n   // Slave Interface Write Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_AWID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           S_AXI_AWADDR,\n   input  wire [C_NUM_SLAVE_SLOTS*8-1:0]                          S_AXI_AWLEN,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_AWSIZE,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_AWBURST,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_AWLOCK,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWCACHE,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_AWPROT,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWREGION,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWQOS,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0]         S_AXI_AWUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_AWVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_AWREADY,\n   // Slave Interface Write Data Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_WID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]     S_AXI_WDATA,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0]   S_AXI_WSTRB,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WLAST,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0]          S_AXI_WUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WREADY,\n   // Slave Interface Write Response Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_BID,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_BRESP,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_BVALID,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_BREADY,\n   // Slave Interface Read Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_ARID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           S_AXI_ARADDR,\n   input  wire [C_NUM_SLAVE_SLOTS*8-1:0]                          S_AXI_ARLEN,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_ARSIZE,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_ARBURST,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_ARLOCK,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARCACHE,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_ARPROT,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARREGION,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARQOS,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0]         S_AXI_ARUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_ARVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_ARREADY,\n   // Slave Interface Read Data Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_RID,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]     S_AXI_RDATA,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_RRESP,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RLAST,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0]          S_AXI_RUSER,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RVALID,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RREADY,\n   // Master Interface Write Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_AWID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          M_AXI_AWADDR,\n   output wire [C_NUM_MASTER_SLOTS*8-1:0]                         M_AXI_AWLEN,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_AWSIZE,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_AWBURST,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_AWLOCK,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWCACHE,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_AWPROT,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWREGION,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWQOS,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0]        M_AXI_AWUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_AWVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_AWREADY,\n   // Master Interface Write Data Ports\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_WID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]    M_AXI_WDATA,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0]  M_AXI_WSTRB,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WLAST,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0]         M_AXI_WUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WREADY,\n   // Master Interface Write Response Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_BID,  // Unused\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_BRESP,\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0]         M_AXI_BUSER,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_BVALID,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_BREADY,\n   // Master Interface Read Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_ARID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          M_AXI_ARADDR,\n   output wire [C_NUM_MASTER_SLOTS*8-1:0]                         M_AXI_ARLEN,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_ARSIZE,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_ARBURST,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_ARLOCK,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARCACHE,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_ARPROT,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARREGION,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARQOS,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0]        M_AXI_ARUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_ARVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_ARREADY,\n   // Master Interface Read Data Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_RID,  // Unused\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]    M_AXI_RDATA,\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_RRESP,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RLAST,\n   input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0]         M_AXI_RUSER,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RVALID,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RREADY\n   );\n   \n  localparam integer  P_AXI4 = 0;\n  localparam integer  P_AXI3 = 1;\n  localparam integer  P_AXILITE = 2;\n  localparam integer P_NUM_MASTER_SLOTS_DE = C_RANGE_CHECK ? C_NUM_MASTER_SLOTS+1 : C_NUM_MASTER_SLOTS;\n  localparam integer P_NUM_MASTER_SLOTS_LOG = (C_NUM_MASTER_SLOTS>1) ? f_ceil_log2(C_NUM_MASTER_SLOTS) : 1;\n  localparam integer P_NUM_MASTER_SLOTS_DE_LOG = (P_NUM_MASTER_SLOTS_DE>1) ? f_ceil_log2(P_NUM_MASTER_SLOTS_DE) : 1;\n  localparam integer P_NUM_SLAVE_SLOTS_LOG = (C_NUM_SLAVE_SLOTS>1) ? f_ceil_log2(C_NUM_SLAVE_SLOTS) : 1;\n  localparam integer P_AXI_AUSER_WIDTH = (C_AXI_AWUSER_WIDTH > C_AXI_ARUSER_WIDTH) ? C_AXI_AWUSER_WIDTH : C_AXI_ARUSER_WIDTH;\n  localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1;\n  localparam integer P_AMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+2+4+4 + P_AXI_AUSER_WIDTH + 4;\n  localparam integer P_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH;\n  localparam integer P_RMESG_WIDTH = 1+2 + C_AXI_DATA_WIDTH + C_AXI_RUSER_WIDTH;\n  localparam integer P_WMESG_WIDTH = 1 + C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH;\n  localparam [31:0]   P_AXILITE_ERRMODE = 32'h00000001;\n  localparam integer P_NONSECURE_BIT = 1; \n  localparam [C_NUM_MASTER_SLOTS-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE);  // Mask of secure MI-slots\n  localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXILITE_MASK = f_m_axilite(0);  // Mask of axilite rule-check MI-slots\n  localparam [1:0]   P_FIXED = 2'b00;\n  localparam integer P_BYPASS = 0;\n  localparam integer P_LIGHTWT = 7;\n  localparam integer P_FULLY_REG = 1;\n  localparam integer P_R_REG_CONFIG = C_R_REGISTER == 8 ?  // \"Automatic\" reg-slice\n        (C_RANGE_CHECK ? ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHTWT : P_FULLY_REG) : P_BYPASS) :  // Bypass if no R-channel mux\n        C_R_REGISTER;\n  localparam P_DECERR = 2'b11;\n\n  //---------------------------------------------------------------------------\n  // Functions\n  //---------------------------------------------------------------------------\n  // Ceiling of log2(x)\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  // Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value\n  //   only for end-point SI-slots\n  function [C_AXI_ID_WIDTH-1:0] f_extend_ID\n    (\n     input [C_AXI_ID_WIDTH-1:0] s_id,\n     input integer slot\n     );\n    begin\n      f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH]));\n    end\n  endfunction\n\n  // Convert Bit32 vector of range [0,1] to Bit1 vector on MI\n  function [C_NUM_MASTER_SLOTS-1:0] f_bit32to1_mi\n    (input [C_NUM_MASTER_SLOTS*32-1:0] vec32);\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        f_bit32to1_mi[mi] = vec32[mi*32];\n      end\n    end\n  endfunction\n\n  // AxiLite error-checking mask (on MI)      \n  function [C_NUM_MASTER_SLOTS-1:0] f_m_axilite\n    (\n      input integer null_arg\n    );\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        f_m_axilite[mi] = (C_M_AXI_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);\n      end\n    end\n  endfunction\n\n  genvar gen_si_slot;\n  genvar gen_mi_slot;\n  wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0]                      si_awmesg          ;\n  wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0]                      si_armesg          ;\n  wire [P_AMESG_WIDTH-1:0]                                        aa_amesg         ;\n  wire [C_AXI_ID_WIDTH-1:0]                                       mi_aid            ;\n  wire [C_AXI_ADDR_WIDTH-1:0]                                     mi_aaddr          ;\n  wire [8-1:0]                                                    mi_alen           ;\n  wire [3-1:0]                                                    mi_asize          ;\n  wire [2-1:0]                                                    mi_alock          ;\n  wire [3-1:0]                                                    mi_aprot          ;\n  wire [2-1:0]                                                    mi_aburst        ;\n  wire [4-1:0]                                                    mi_acache        ;\n  wire [4-1:0]                                                    mi_aregion        ;\n  wire [4-1:0]                                                    mi_aqos        ;\n  wire [P_AXI_AUSER_WIDTH-1:0]                                    mi_auser        ;\n  wire [4-1:0]                                                    target_region        ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  aa_grant_hot     ;\n  wire [P_NUM_SLAVE_SLOTS_LOG-1:0]                                  aa_grant_enc     ;\n  wire                                                            aa_grant_rnw ;\n  wire                                                            aa_grant_any ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                                   target_mi_hot    ;\n  wire [P_NUM_MASTER_SLOTS_LOG-1:0]                                   target_mi_enc    ;\n  reg  [P_NUM_MASTER_SLOTS_DE-1:0]                               m_atarget_hot = 0    ;\n  reg  [P_NUM_MASTER_SLOTS_DE_LOG-1:0]                               m_atarget_enc = 0    ;\n  wire [P_NUM_MASTER_SLOTS_DE_LOG-1:0]                               m_atarget_enc_comb    ;\n  wire                                                            match;\n  wire                                                            any_error         ;\n  wire [7:0]                                                      m_aerror_i         ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_awvalid            ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_awready            ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_arvalid            ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_arready            ;\n  wire                                                            aa_awvalid         ;\n  wire                                                            aa_awready         ;\n  wire                                                            aa_arvalid         ;\n  wire                                                            aa_arready         ;\n  wire                                                            mi_awvalid_en;\n  wire                                                            mi_awready_mux;\n  wire                                                            mi_arvalid_en;\n  wire                                                            mi_arready_mux;\n  wire                                                            w_transfer_en;\n  wire                                                            w_complete_mux;\n  wire                                                            b_transfer_en;\n  wire                                                            b_complete_mux;\n  wire                                                            r_transfer_en;\n  wire                                                            r_complete_mux;\n  wire                                                            target_secure;\n  wire                                                            target_write;\n  wire                                                            target_read;\n  wire                                                            target_axilite;\n  \n  wire [P_BMESG_WIDTH-1:0]                                        si_bmesg           ;\n  wire [P_NUM_MASTER_SLOTS_DE*P_BMESG_WIDTH-1:0]                 mi_bmesg           ;\n  wire [P_NUM_MASTER_SLOTS_DE*2-1:0]                             mi_bresp           ;\n  wire [P_NUM_MASTER_SLOTS_DE*C_AXI_BUSER_WIDTH-1:0]             mi_buser           ;\n  wire [2-1:0]                                                    si_bresp           ;\n  wire [C_AXI_BUSER_WIDTH-1:0]                                    si_buser           ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_bvalid          ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_bready          ;\n  wire                                                            aa_bvalid          ;\n  wire                                                            aa_bready         ;\n  wire                                                            si_bready         ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                                    si_bvalid;\n  \n  wire [P_RMESG_WIDTH-1:0]                                        aa_rmesg           ;\n  wire [P_RMESG_WIDTH-1:0]                                        sr_rmesg           ;\n  wire [P_NUM_MASTER_SLOTS_DE*P_RMESG_WIDTH-1:0]                 mi_rmesg           ;\n  wire [P_NUM_MASTER_SLOTS_DE*2-1:0]                             mi_rresp           ;\n  wire [P_NUM_MASTER_SLOTS_DE*C_AXI_RUSER_WIDTH-1:0]             mi_ruser           ;\n  wire [P_NUM_MASTER_SLOTS_DE*C_AXI_DATA_WIDTH-1:0]          mi_rdata              ;\n  wire [P_NUM_MASTER_SLOTS_DE*1-1:0]                             mi_rlast              ;\n  wire [2-1:0]                                                    si_rresp           ;\n  wire [C_AXI_RUSER_WIDTH-1:0]                                    si_ruser           ;\n  wire [C_AXI_DATA_WIDTH-1:0]                                 si_rdata              ;\n  wire                                                            si_rlast              ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_rvalid          ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_rready          ;\n  wire                                                            aa_rvalid          ;\n  wire                                                            aa_rready         ;\n  wire                                                            sr_rvalid          ;\n  wire                                                            si_rready         ;\n  wire                                                            sr_rready         ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                                    si_rvalid;\n  \n  wire [C_NUM_SLAVE_SLOTS*P_WMESG_WIDTH-1:0]                      si_wmesg           ;\n  wire [P_WMESG_WIDTH-1:0]                                        mi_wmesg           ;\n  wire [C_AXI_ID_WIDTH-1:0]                                    mi_wid              ;\n  wire [C_AXI_DATA_WIDTH-1:0]                            mi_wdata              ;\n  wire [C_AXI_DATA_WIDTH/8-1:0]                          mi_wstrb              ;\n  wire [C_AXI_WUSER_WIDTH-1:0]                                    mi_wuser              ;\n  wire [1-1:0]                                                    mi_wlast              ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_wvalid          ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_wready          ;\n  wire                                                            aa_wvalid          ;\n  wire                                                            aa_wready         ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                                    si_wready;\n  \n  reg  [7:0]                                                      debug_r_beat_cnt_i;\n  reg  [7:0]                                                      debug_w_beat_cnt_i;\n  reg  [7:0]                                                      debug_aw_trans_seq_i;\n  reg  [7:0]                                                      debug_ar_trans_seq_i;\n\n  reg aresetn_d = 1'b0; // Reset delay register\n  always @(posedge ACLK) begin\n    if (~ARESETN) begin\n      aresetn_d <= 1'b0;\n    end else begin\n      aresetn_d <= ARESETN;\n    end\n  end\n  wire reset;\n  assign reset = ~aresetn_d;\n\n  generate\n    axi_crossbar_v2_1_16_addr_arbiter_sasd #\n      (\n       .C_FAMILY                (C_FAMILY),\n       .C_NUM_S                 (C_NUM_SLAVE_SLOTS),\n       .C_NUM_S_LOG             (P_NUM_SLAVE_SLOTS_LOG),\n       .C_AMESG_WIDTH            (P_AMESG_WIDTH),\n       .C_GRANT_ENC             (1),\n       .C_ARB_PRIORITY          (C_S_AXI_ARB_PRIORITY)\n       )\n      addr_arbiter_inst\n        (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         // Vector of SI-side AW command request inputs\n         .S_AWMESG                (si_awmesg),\n         .S_ARMESG                (si_armesg),\n         .S_AWVALID               (S_AXI_AWVALID),\n         .S_AWREADY               (S_AXI_AWREADY),\n         .S_ARVALID               (S_AXI_ARVALID),\n         .S_ARREADY               (S_AXI_ARREADY),\n         .M_GRANT_ENC           (aa_grant_enc),\n         .M_GRANT_HOT           (aa_grant_hot),  // SI-slot 1-hot mask of granted command\n         .M_GRANT_ANY             (aa_grant_any),\n         .M_GRANT_RNW             (aa_grant_rnw),\n         .M_AMESG                (aa_amesg),  // Either S_AWMESG or S_ARMESG, as indicated by M_AWVALID and M_ARVALID.\n         .M_AWVALID               (aa_awvalid),\n         .M_AWREADY               (aa_awready),\n         .M_ARVALID               (aa_arvalid),\n         .M_ARREADY               (aa_arready)\n         );\n\n    if (C_ADDR_DECODE) begin : gen_addr_decoder\n      axi_crossbar_v2_1_16_addr_decoder #\n        (\n          .C_FAMILY          (C_FAMILY),\n          .C_NUM_TARGETS     (C_NUM_MASTER_SLOTS),\n          .C_NUM_TARGETS_LOG (P_NUM_MASTER_SLOTS_LOG),\n          .C_NUM_RANGES      (C_NUM_ADDR_RANGES),\n          .C_ADDR_WIDTH      (C_AXI_ADDR_WIDTH),\n          .C_TARGET_ENC      (1),\n          .C_TARGET_HOT      (1),\n          .C_REGION_ENC      (1),\n          .C_BASE_ADDR      (C_M_AXI_BASE_ADDR),\n          .C_HIGH_ADDR      (C_M_AXI_HIGH_ADDR),\n          .C_TARGET_QUAL     ({C_NUM_MASTER_SLOTS{1'b1}}),\n          .C_RESOLUTION      (2)\n        ) \n        addr_decoder_inst \n        (\n          .ADDR             (mi_aaddr),        \n          .TARGET_HOT       (target_mi_hot),  \n          .TARGET_ENC       (target_mi_enc),  \n          .MATCH            (match),       \n          .REGION           (target_region)      \n        );\n    end else begin : gen_no_addr_decoder\n      assign target_mi_hot = 1;\n      assign match = 1'b1;\n      assign target_region = 4'b0000;\n    end  // gen_addr_decoder\n    \n    // AW-channel arbiter command transfer completes upon completion of both M-side AW-channel transfer and B channel completion.\n    axi_crossbar_v2_1_16_splitter #  \n      (\n        .C_NUM_M                (3)\n      )\n      splitter_aw\n      (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         .S_VALID              (aa_awvalid),\n         .S_READY              (aa_awready),\n         .M_VALID              ({mi_awvalid_en, w_transfer_en, b_transfer_en}),\n         .M_READY              ({mi_awready_mux, w_complete_mux, b_complete_mux})\n      );\n    \n    // AR-channel arbiter command transfer completes upon completion of both M-side AR-channel transfer and R channel completion.\n    axi_crossbar_v2_1_16_splitter #  \n      (\n        .C_NUM_M                (2)\n      )\n      splitter_ar\n      (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         .S_VALID              (aa_arvalid),\n         .S_READY              (aa_arready),\n         .M_VALID              ({mi_arvalid_en, r_transfer_en}),\n         .M_READY              ({mi_arready_mux, r_complete_mux})\n      );\n    \n    assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);\n    assign target_write = |(target_mi_hot & C_M_AXI_SUPPORTS_WRITE);\n    assign target_read = |(target_mi_hot & C_M_AXI_SUPPORTS_READ);\n    assign target_axilite = |(target_mi_hot & P_M_AXILITE_MASK);\n    \n    assign any_error = C_RANGE_CHECK && (m_aerror_i != 0);             // DECERR if error-detection enabled and any error condition.\n    assign m_aerror_i[0] = ~match;                                     // Invalid target address\n    assign m_aerror_i[1] = target_secure && mi_aprot[P_NONSECURE_BIT]; // TrustZone violation\n    assign m_aerror_i[2] = target_axilite && ((mi_alen != 0) || \n      (mi_asize[1:0] == 2'b11) || (mi_asize[2] == 1'b1));              // AxiLite access violation\n    assign m_aerror_i[3] = (~aa_grant_rnw && ~target_write) ||\n      (aa_grant_rnw && ~target_read);                                  // R/W direction unsupported by target\n    assign m_aerror_i[7:4] = 4'b0000;                                     // Reserved\n    assign m_atarget_enc_comb = any_error ? (P_NUM_MASTER_SLOTS_DE-1) : target_mi_enc;  // Select MI slot or decerr_slave\n      \n    always @(posedge ACLK) begin\n      if (reset) begin\n        m_atarget_hot <= 0;\n        m_atarget_enc <= 0;\n      end else begin\n        m_atarget_hot <= {P_NUM_MASTER_SLOTS_DE{aa_grant_any}} & (any_error ? {1'b1, {C_NUM_MASTER_SLOTS{1'b0}}} : {1'b0, target_mi_hot});  // Select MI slot or decerr_slave\n        m_atarget_enc <= m_atarget_enc_comb;\n      end\n    end\n    \n    // Receive AWREADY from targeted MI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (1)\n      ) mi_awready_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_awready),\n       .O   (mi_awready_mux),\n       .OE  (mi_awvalid_en)\n      ); \n      \n    // Receive ARREADY from targeted MI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (1)\n      ) mi_arready_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_arready),\n       .O   (mi_arready_mux),\n       .OE  (mi_arvalid_en)\n      ); \n      \n    assign mi_awvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_awvalid_en}};  // Assert AWVALID on targeted MI.\n    assign mi_arvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_arvalid_en}};  // Assert ARVALID on targeted MI.\n    assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS];  // Propagate to MI slots.\n    assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS];  // Propagate to MI slots.\n    assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY;  // Copy from MI slots.\n    assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY;  // Copy from MI slots.\n    \n    // Receive WREADY from targeted MI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (1)\n      ) mi_wready_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_wready),\n       .O   (aa_wready),\n       .OE  (w_transfer_en)\n      ); \n      \n    assign mi_wvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_wvalid}};  // Assert WVALID on targeted MI.\n    assign si_wready = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_wready}};  // Assert WREADY on granted SI.\n    assign S_AXI_WREADY = si_wready;\n    assign w_complete_mux = aa_wready & aa_wvalid & mi_wlast;  // W burst complete on on designated SI/MI.\n    \n    // Receive RREADY from granted SI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (C_NUM_SLAVE_SLOTS),\n       .C_SEL_WIDTH   (P_NUM_SLAVE_SLOTS_LOG),\n       .C_DATA_WIDTH  (1)\n      ) si_rready_mux_inst \n      (\n       .S   (aa_grant_enc),\n       .A   (S_AXI_RREADY),\n       .O   (si_rready),\n       .OE  (r_transfer_en)\n      ); \n      \n    assign sr_rready = si_rready & r_transfer_en;\n    assign mi_rready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_rready}};  // Assert RREADY on targeted MI.\n    assign si_rvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{sr_rvalid}};  // Assert RVALID on granted SI.\n    assign S_AXI_RVALID = si_rvalid;\n    assign r_complete_mux = sr_rready & sr_rvalid & si_rlast;  // R burst complete on on designated SI/MI.\n    \n    // Receive BREADY from granted SI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (C_NUM_SLAVE_SLOTS),\n       .C_SEL_WIDTH   (P_NUM_SLAVE_SLOTS_LOG),\n       .C_DATA_WIDTH  (1)\n      ) si_bready_mux_inst \n      (\n       .S   (aa_grant_enc),\n       .A   (S_AXI_BREADY),\n       .O   (si_bready),\n       .OE  (b_transfer_en)\n      ); \n      \n    assign aa_bready = si_bready & b_transfer_en;\n    assign mi_bready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_bready}};  // Assert BREADY on targeted MI.\n    assign si_bvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_bvalid}};  // Assert BVALID on granted SI.\n    assign S_AXI_BVALID = si_bvalid;\n    assign b_complete_mux = aa_bready & aa_bvalid;  // B transfer complete on on designated SI/MI.\n    \n    for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_si_amesg\n      assign si_armesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = {  // Concatenate from MSB to LSB\n        4'b0000,\n//        S_AXI_ARREGION[gen_si_slot*4+:4],\n        S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH +: C_AXI_ARUSER_WIDTH],\n        S_AXI_ARQOS[gen_si_slot*4+:4],\n        S_AXI_ARCACHE[gen_si_slot*4+:4],\n        S_AXI_ARBURST[gen_si_slot*2+:2],\n        S_AXI_ARPROT[gen_si_slot*3+:3],\n        S_AXI_ARLOCK[gen_si_slot*2+:2],\n        S_AXI_ARSIZE[gen_si_slot*3+:3],\n        S_AXI_ARLEN[gen_si_slot*8+:8],\n        S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH],\n        f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH +: C_AXI_ID_WIDTH], gen_si_slot)\n        };\n      assign si_awmesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = {  // Concatenate from MSB to LSB\n        4'b0000,\n//        S_AXI_AWREGION[gen_si_slot*4+:4],\n        S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH +: C_AXI_AWUSER_WIDTH],\n        S_AXI_AWQOS[gen_si_slot*4+:4],\n        S_AXI_AWCACHE[gen_si_slot*4+:4],\n        S_AXI_AWBURST[gen_si_slot*2+:2],\n        S_AXI_AWPROT[gen_si_slot*3+:3],\n        S_AXI_AWLOCK[gen_si_slot*2+:2],\n        S_AXI_AWSIZE[gen_si_slot*3+:3],\n        S_AXI_AWLEN[gen_si_slot*8+:8],\n        S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH],\n        f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)\n        };\n    end  // gen_si_amesg\n    \n    assign mi_aid        = aa_amesg[0 +: C_AXI_ID_WIDTH];\n    assign mi_aaddr      = aa_amesg[C_AXI_ID_WIDTH +: C_AXI_ADDR_WIDTH];\n    assign mi_alen       = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +: 8];\n    assign mi_asize      = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +: 3];\n    assign mi_alock      = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +: 2];\n    assign mi_aprot      = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +: 3];\n    assign mi_aburst     = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +: 2];\n    assign mi_acache     = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2 +: 4];\n    assign mi_aqos       = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4 +: 4];\n    assign mi_auser      = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4 +: P_AXI_AUSER_WIDTH];\n    assign mi_aregion    = (C_ADDR_DECODE != 0) ? target_region : aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4+P_AXI_AUSER_WIDTH +: 4];\n      \n    // Broadcast AW transfer payload to all MI-slots\n    assign M_AXI_AWID        = {C_NUM_MASTER_SLOTS{mi_aid}};\n    assign M_AXI_AWADDR      = {C_NUM_MASTER_SLOTS{mi_aaddr}};\n    assign M_AXI_AWLEN       = {C_NUM_MASTER_SLOTS{mi_alen }};\n    assign M_AXI_AWSIZE      = {C_NUM_MASTER_SLOTS{mi_asize}};\n    assign M_AXI_AWLOCK      = {C_NUM_MASTER_SLOTS{mi_alock}};\n    assign M_AXI_AWPROT      = {C_NUM_MASTER_SLOTS{mi_aprot}};\n    assign M_AXI_AWREGION    = {C_NUM_MASTER_SLOTS{mi_aregion}};\n    assign M_AXI_AWBURST     = {C_NUM_MASTER_SLOTS{mi_aburst}};\n    assign M_AXI_AWCACHE     = {C_NUM_MASTER_SLOTS{mi_acache}};\n    assign M_AXI_AWQOS       = {C_NUM_MASTER_SLOTS{mi_aqos  }};\n    assign M_AXI_AWUSER      = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_AWUSER_WIDTH] }};\n    \n    // Broadcast AR transfer payload to all MI-slots\n    assign M_AXI_ARID        = {C_NUM_MASTER_SLOTS{mi_aid}};\n    assign M_AXI_ARADDR      = {C_NUM_MASTER_SLOTS{mi_aaddr}};                        \n    assign M_AXI_ARLEN       = {C_NUM_MASTER_SLOTS{mi_alen }};                        \n    assign M_AXI_ARSIZE      = {C_NUM_MASTER_SLOTS{mi_asize}};                        \n    assign M_AXI_ARLOCK      = {C_NUM_MASTER_SLOTS{mi_alock}};                        \n    assign M_AXI_ARPROT      = {C_NUM_MASTER_SLOTS{mi_aprot}};                        \n    assign M_AXI_ARREGION    = {C_NUM_MASTER_SLOTS{mi_aregion}};                          \n    assign M_AXI_ARBURST     = {C_NUM_MASTER_SLOTS{mi_aburst}};                       \n    assign M_AXI_ARCACHE     = {C_NUM_MASTER_SLOTS{mi_acache}};                       \n    assign M_AXI_ARQOS       = {C_NUM_MASTER_SLOTS{mi_aqos  }};                       \n    assign M_AXI_ARUSER      = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_ARUSER_WIDTH] }};\n    \n    // W-channel MI handshakes\n    assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS];\n    assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY;\n    // Broadcast W transfer payload to all MI-slots\n    assign M_AXI_WLAST = {C_NUM_MASTER_SLOTS{mi_wlast}};\n    assign M_AXI_WUSER = {C_NUM_MASTER_SLOTS{mi_wuser}};\n    assign M_AXI_WDATA = {C_NUM_MASTER_SLOTS{mi_wdata}};\n    assign M_AXI_WSTRB = {C_NUM_MASTER_SLOTS{mi_wstrb}};\n    assign M_AXI_WID =   {C_NUM_MASTER_SLOTS{mi_wid}};\n    \n    // Broadcast R transfer payload to all SI-slots\n    assign S_AXI_RLAST = {C_NUM_SLAVE_SLOTS{si_rlast}};\n    assign S_AXI_RRESP = {C_NUM_SLAVE_SLOTS{si_rresp}};\n    assign S_AXI_RUSER = {C_NUM_SLAVE_SLOTS{si_ruser}};\n    assign S_AXI_RDATA = {C_NUM_SLAVE_SLOTS{si_rdata}};\n    assign S_AXI_RID =   {C_NUM_SLAVE_SLOTS{mi_aid}};\n    \n    // Broadcast B transfer payload to all SI-slots\n    assign S_AXI_BRESP = {C_NUM_SLAVE_SLOTS{si_bresp}};\n    assign S_AXI_BUSER = {C_NUM_SLAVE_SLOTS{si_buser}};\n    assign S_AXI_BID =   {C_NUM_SLAVE_SLOTS{mi_aid}};\n    \n    if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux\n      // SI WVALID mux.\n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_SLAVE_SLOTS),\n         .C_SEL_WIDTH   (P_NUM_SLAVE_SLOTS_LOG),\n         .C_DATA_WIDTH  (1)\n        ) si_w_valid_mux_inst \n        (\n         .S   (aa_grant_enc),\n         .A   (S_AXI_WVALID),\n         .O   (aa_wvalid),\n         .OE  (w_transfer_en)\n        ); \n      \n      // SI W-channel payload mux\n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_SLAVE_SLOTS),\n         .C_SEL_WIDTH   (P_NUM_SLAVE_SLOTS_LOG),\n         .C_DATA_WIDTH  (P_WMESG_WIDTH)\n        ) si_w_payload_mux_inst \n        (\n         .S   (aa_grant_enc),\n         .A   (si_wmesg),\n         .O   (mi_wmesg),\n         .OE  (1'b1)\n        ); \n        \n      for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_wmesg\n        assign si_wmesg[gen_si_slot*P_WMESG_WIDTH+:P_WMESG_WIDTH] = {  // Concatenate from MSB to LSB\n          ((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1'b0),\n          S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH],\n          S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8],\n          S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],\n          S_AXI_WLAST[gen_si_slot*1+:1]\n        };\n      end  // gen_wmesg\n      \n      assign mi_wlast = mi_wmesg[0];\n      assign mi_wdata = mi_wmesg[1 +: C_AXI_DATA_WIDTH];\n      assign mi_wstrb = mi_wmesg[1+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8];\n      assign mi_wuser = mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH];\n      assign mi_wid =   mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH];\n    end else begin : gen_no_wmux\n      assign aa_wvalid = w_transfer_en & S_AXI_WVALID;\n      assign mi_wlast  = S_AXI_WLAST;\n      assign mi_wdata  = S_AXI_WDATA;\n      assign mi_wstrb  = S_AXI_WSTRB;\n      assign mi_wuser  = S_AXI_WUSER;\n      assign mi_wid =    S_AXI_WID;\n    end  // gen_wmux\n    \n    // Receive RVALID from targeted MI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (1)\n      ) mi_rvalid_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_rvalid),\n       .O   (aa_rvalid),\n       .OE  (r_transfer_en)\n      ); \n      \n    // MI R-channel payload mux\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (P_RMESG_WIDTH)\n      ) mi_rmesg_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_rmesg),\n       .O   (aa_rmesg),\n       .OE  (1'b1)\n      ); \n      \n    axi_register_slice_v2_1_15_axic_register_slice #\n      (\n       .C_FAMILY (C_FAMILY),\n       .C_DATA_WIDTH (P_RMESG_WIDTH),\n       .C_REG_CONFIG (P_R_REG_CONFIG)\n       )\n      reg_slice_r\n      (\n       // System Signals\n       .ACLK(ACLK),\n       .ARESET(reset),\n\n       // Slave side\n       .S_PAYLOAD_DATA(aa_rmesg),\n       .S_VALID(aa_rvalid),\n       .S_READY(aa_rready),\n\n       // Master side\n       .M_PAYLOAD_DATA(sr_rmesg),\n       .M_VALID(sr_rvalid),\n       .M_READY(sr_rready)\n       );\n\n    assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID; \n    assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST; \n    assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP;\n    assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER;\n    assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA;\n    assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS];\n    \n    for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_rmesg\n      assign mi_rmesg[gen_mi_slot*P_RMESG_WIDTH+:P_RMESG_WIDTH] = {  // Concatenate from MSB to LSB\n        mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH],\n        mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],\n        mi_rresp[gen_mi_slot*2+:2],\n        mi_rlast[gen_mi_slot*1+:1]\n      };\n    end  // gen_rmesg\n    \n    assign si_rlast = sr_rmesg[0];\n    assign si_rresp = sr_rmesg[1 +: 2];\n    assign si_rdata = sr_rmesg[1+2 +: C_AXI_DATA_WIDTH];\n    assign si_ruser = sr_rmesg[1+2+C_AXI_DATA_WIDTH +: C_AXI_RUSER_WIDTH];\n      \n    // Receive BVALID from targeted MI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (1)\n      ) mi_bvalid_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_bvalid),\n       .O   (aa_bvalid),\n       .OE  (b_transfer_en)\n      ); \n      \n    // MI B-channel payload mux\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (P_BMESG_WIDTH)\n      ) mi_bmesg_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_bmesg),\n       .O   (si_bmesg),\n       .OE  (1'b1)\n      ); \n      \n    assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID; \n    assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP;\n    assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER;\n    assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS];\n    \n    for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_bmesg\n      assign mi_bmesg[gen_mi_slot*P_BMESG_WIDTH+:P_BMESG_WIDTH] = {  // Concatenate from MSB to LSB\n        mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH],\n        mi_bresp[gen_mi_slot*2+:2]\n      };\n    end  // gen_bmesg\n    \n    assign si_bresp = si_bmesg[0 +: 2];\n    assign si_buser = si_bmesg[2 +: C_AXI_BUSER_WIDTH];\n    \n    if (C_DEBUG) begin : gen_debug_trans_seq\n      // DEBUG WRITE TRANSACTION SEQUENCE COUNTER\n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_aw_trans_seq_i <= 1;\n        end else begin\n          if (aa_awvalid && aa_awready) begin\n            debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1;\n          end\n        end\n      end\n  \n      // DEBUG READ TRANSACTION SEQUENCE COUNTER\n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_ar_trans_seq_i <= 1;\n        end else begin\n          if (aa_arvalid && aa_arready) begin\n            debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1;\n          end\n        end\n      end\n      \n      // DEBUG WRITE BEAT COUNTER \n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_w_beat_cnt_i <= 0;\n        end else if (aa_wready & aa_wvalid) begin\n          if (mi_wlast) begin\n            debug_w_beat_cnt_i <= 0;\n          end else begin\n            debug_w_beat_cnt_i <= debug_w_beat_cnt_i + 1;\n          end\n        end\n      end  // Clocked process\n    \n      // DEBUG READ BEAT COUNTER \n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_r_beat_cnt_i <= 0;\n        end else if (sr_rready & sr_rvalid) begin\n          if (si_rlast) begin\n            debug_r_beat_cnt_i <= 0;\n          end else begin\n            debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;\n          end\n        end\n      end  // Clocked process\n    \n    end  // gen_debug_trans_seq\n\n    if (C_RANGE_CHECK) begin : gen_decerr\n      // Highest MI-slot (index C_NUM_MASTER_SLOTS) is the error handler\n      axi_crossbar_v2_1_16_decerr_slave #\n        (\n         .C_AXI_ID_WIDTH                 (1),\n         .C_AXI_DATA_WIDTH               (C_AXI_DATA_WIDTH),\n         .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),\n         .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),\n         .C_AXI_PROTOCOL                 (C_AXI_PROTOCOL),\n         .C_RESP                         (P_DECERR) \n        )\n        decerr_slave_inst\n          (\n           .S_AXI_ACLK (ACLK),\n           .S_AXI_ARESET (reset),\n           .S_AXI_AWID (1'b0),\n           .S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_WLAST (mi_wlast),\n           .S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_BID (),\n           .S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]),\n           .S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]),\n           .S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_ARID (1'b0),\n           .S_AXI_ARLEN (mi_alen),\n           .S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RID (),\n           .S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),\n           .S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]),\n           .S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]),\n           .S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS])\n         );\n    end  // gen_decerr\n\n  endgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: crossbar.v\n//\n// Description: \n//   This module is a M-master to N-slave AXI axi_crossbar_v2_1_16_crossbar switch.\n//   The interface of this module consists of a vectored slave and master interface\n//     in which all slots are sized and synchronized to the native width and clock \n//     of the interconnect.\n//   The SAMD axi_crossbar_v2_1_16_crossbar supports only AXI4 and AXI3 protocols.\n//   All width, clock and protocol conversions are done outside this block, as are\n//     any pipeline registers or data FIFOs.\n//   This module contains all arbitration, decoders and channel multiplexing logic.\n//     It also contains the diagnostic registers and control interface.\n//\n//-----------------------------------------------------------------------------\n//\n// Structure:\n//    crossbar\n//      si_transactor\n//        addr_decoder\n//          comparator_static\n//        mux_enc\n//        axic_srl_fifo\n//        arbiter_resp\n//      splitter\n//      wdata_router\n//        axic_reg_srl_fifo\n//      wdata_mux\n//        axic_reg_srl_fifo\n//        mux_enc\n//      addr_decoder\n//        comparator_static\n//      axic_srl_fifo\n//      axi_register_slice\n//      addr_arbiter\n//        mux_enc\n//      decerr_slave\n//      \n//-----------------------------------------------------------------------------\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_16_crossbar #\n  (\n   parameter         C_FAMILY                       = \"none\", \n   parameter integer C_NUM_SLAVE_SLOTS              =   1, \n   parameter integer C_NUM_MASTER_SLOTS             =   1, \n   parameter integer C_NUM_ADDR_RANGES              = 1,\n   parameter integer C_AXI_ID_WIDTH                   = 1, \n   parameter integer C_AXI_ADDR_WIDTH                 = 32, \n   parameter integer C_AXI_DATA_WIDTH = 32, \n   parameter integer C_AXI_PROTOCOL           = 0, \n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}}, \n   parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},\n   parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}}, \n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 1,\n   parameter integer C_AXI_ARUSER_WIDTH = 1,\n   parameter integer C_AXI_WUSER_WIDTH = 1,\n   parameter integer C_AXI_RUSER_WIDTH = 1,\n   parameter integer C_AXI_BUSER_WIDTH = 1,\n   parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE           = {C_NUM_SLAVE_SLOTS{1'b1}}, \n   parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ            = {C_NUM_SLAVE_SLOTS{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE           = {C_NUM_MASTER_SLOTS{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ            = {C_NUM_MASTER_SLOTS{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1'b1}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1'b1}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD                 = {C_NUM_SLAVE_SLOTS{32'h00000000}}, \n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE         = {C_NUM_SLAVE_SLOTS{32'h00000001}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE          = {C_NUM_SLAVE_SLOTS{32'h00000001}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING            = {C_NUM_MASTER_SLOTS{32'h00000001}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING            = {C_NUM_MASTER_SLOTS{32'h00000001}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY             = {C_NUM_SLAVE_SLOTS{32'h00000000}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE                   = {C_NUM_MASTER_SLOTS{32'h00000000}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE            = {C_NUM_MASTER_SLOTS{32'h00000000}},\n   parameter integer C_RANGE_CHECK                    = 0,\n   parameter integer C_ADDR_DECODE                    = 0,\n   parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_W_ISSUE_WIDTH  = {C_NUM_MASTER_SLOTS+1{32'h00000000}},\n   parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_R_ISSUE_WIDTH  = {C_NUM_MASTER_SLOTS+1{32'h00000000}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_W_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_R_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}},\n   parameter integer C_DEBUG              = 1\n   )\n  (\n   // Global Signals\n   input  wire                                                    ACLK,\n   input  wire                                                    ARESETN,\n   // Slave Interface Write Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_AWID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           S_AXI_AWADDR,\n   input  wire [C_NUM_SLAVE_SLOTS*8-1:0]                          S_AXI_AWLEN,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_AWSIZE,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_AWBURST,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_AWLOCK,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWCACHE,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_AWPROT,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWREGION,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWQOS,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0]         S_AXI_AWUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_AWVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_AWREADY,\n   // Slave Interface Write Data Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_WID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]     S_AXI_WDATA,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0]   S_AXI_WSTRB,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WLAST,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0]          S_AXI_WUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WREADY,\n   // Slave Interface Write Response Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_BID,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_BRESP,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_BVALID,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_BREADY,\n   // Slave Interface Read Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_ARID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           S_AXI_ARADDR,\n   input  wire [C_NUM_SLAVE_SLOTS*8-1:0]                          S_AXI_ARLEN,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_ARSIZE,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_ARBURST,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_ARLOCK,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARCACHE,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_ARPROT,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARREGION,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARQOS,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0]         S_AXI_ARUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_ARVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_ARREADY,\n   // Slave Interface Read Data Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_RID,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]     S_AXI_RDATA,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_RRESP,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RLAST,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0]          S_AXI_RUSER,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RVALID,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RREADY,\n   // Master Interface Write Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_AWID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          M_AXI_AWADDR,\n   output wire [C_NUM_MASTER_SLOTS*8-1:0]                         M_AXI_AWLEN,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_AWSIZE,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_AWBURST,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_AWLOCK,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWCACHE,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_AWPROT,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWREGION,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWQOS,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0]        M_AXI_AWUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_AWVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_AWREADY,\n   // Master Interface Write Data Ports\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_WID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]    M_AXI_WDATA,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0]  M_AXI_WSTRB,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WLAST,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0]         M_AXI_WUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WREADY,\n   // Master Interface Write Response Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_BID,\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_BRESP,\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0]         M_AXI_BUSER,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_BVALID,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_BREADY,\n   // Master Interface Read Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_ARID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          M_AXI_ARADDR,\n   output wire [C_NUM_MASTER_SLOTS*8-1:0]                         M_AXI_ARLEN,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_ARSIZE,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_ARBURST,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_ARLOCK,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARCACHE,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_ARPROT,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARREGION,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARQOS,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0]        M_AXI_ARUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_ARVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_ARREADY,\n   // Master Interface Read Data Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_RID,\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]    M_AXI_RDATA,\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_RRESP,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RLAST,\n   input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0]         M_AXI_RUSER,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RVALID,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RREADY\n   );\n   \n  localparam integer  P_AXI4 = 0;\n  localparam integer  P_AXI3 = 1;\n  localparam integer  P_AXILITE = 2;\n  localparam integer P_WRITE = 0;\n  localparam integer P_READ = 1;\n  localparam integer P_NUM_MASTER_SLOTS_LOG = f_ceil_log2(C_NUM_MASTER_SLOTS);\n  localparam integer P_NUM_SLAVE_SLOTS_LOG = f_ceil_log2((C_NUM_SLAVE_SLOTS>1) ? C_NUM_SLAVE_SLOTS : 2);\n  localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1;\n  localparam integer P_ST_AWMESG_WIDTH = 2+4+4 + C_AXI_AWUSER_WIDTH;\n  localparam integer P_AA_AWMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_AWMESG_WIDTH;\n  localparam integer P_ST_ARMESG_WIDTH = 2+4+4 + C_AXI_ARUSER_WIDTH;\n  localparam integer P_AA_ARMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_ARMESG_WIDTH;\n  localparam integer P_ST_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH;\n  localparam integer P_ST_RMESG_WIDTH = 2 + C_AXI_RUSER_WIDTH + C_AXI_DATA_WIDTH;\n  localparam integer P_WR_WMESG_WIDTH = C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH;\n  localparam [31:0] P_BYPASS  = 32'h00000000;\n  localparam [31:0] P_FWD_REV = 32'h00000001;\n  localparam [31:0] P_SIMPLE  = 32'h00000007;\n  localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_READ = {1'b1, C_M_AXI_SUPPORTS_READ[0+:C_NUM_MASTER_SLOTS]};\n  localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_WRITE = {1'b1, C_M_AXI_SUPPORTS_WRITE[0+:C_NUM_MASTER_SLOTS]};\n  localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_WRITE_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]};\n  localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_READ_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]};\n  localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_WRITE_CONNECTIVITY = f_si_write_connectivity(0);\n  localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_READ_CONNECTIVITY = f_si_read_connectivity(0);\n  localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_ISSUING = {32'h00000001, C_M_AXI_READ_ISSUING[0+:C_NUM_MASTER_SLOTS*32]};\n  localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_ISSUING = {32'h00000001, C_M_AXI_WRITE_ISSUING[0+:C_NUM_MASTER_SLOTS*32]};\n  localparam P_DECERR = 2'b11;\n\n  //---------------------------------------------------------------------------\n  // Functions\n  //---------------------------------------------------------------------------\n  // Ceiling of log2(x)\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  // Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value\n  //   only for end-point SI-slots\n  function [C_AXI_ID_WIDTH-1:0] f_extend_ID\n    (\n     input [C_AXI_ID_WIDTH-1:0] s_id,\n     input integer slot\n     );\n    begin\n      f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH]));\n    end\n  endfunction\n\n  // Write connectivity array transposed\n  function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_write_connectivity\n    (\n      input integer null_arg\n     );\n    integer si_slot;\n    integer mi_slot;\n    reg  [C_NUM_SLAVE_SLOTS*32-1:0]  result;\n    begin\n      result = {C_NUM_SLAVE_SLOTS*32{1'b1}};\n      for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin\n        for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin\n          result[si_slot*32+mi_slot] = C_M_AXI_WRITE_CONNECTIVITY[mi_slot*32+si_slot];\n        end\n      end\n    f_si_write_connectivity = result;\n    end\n  endfunction\n\n  // Read connectivity array transposed\n  function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_read_connectivity\n    (\n      input integer null_arg\n     );\n    integer si_slot;\n    integer mi_slot;\n    reg  [C_NUM_SLAVE_SLOTS*32-1:0]  result;\n    begin\n      result = {C_NUM_SLAVE_SLOTS*32{1'b1}};\n      for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin\n        for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin\n          result[si_slot*32+mi_slot] = C_M_AXI_READ_CONNECTIVITY[mi_slot*32+si_slot];\n        end\n      end\n    f_si_read_connectivity = result;\n    end\n  endfunction\n\n  genvar gen_si_slot;\n  genvar gen_mi_slot;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0]                  si_st_awmesg          ;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0]                  st_tmp_awmesg         ;\n  wire [C_NUM_SLAVE_SLOTS*P_AA_AWMESG_WIDTH-1:0]                  tmp_aa_awmesg         ;\n  wire [P_AA_AWMESG_WIDTH-1:0]                                    aa_mi_awmesg          ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]                     st_aa_awid            ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]                   st_aa_awaddr          ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                                  st_aa_awlen           ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                                  st_aa_awsize          ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                                  st_aa_awlock          ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                                  st_aa_awprot          ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                                  st_aa_awregion        ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                                  st_aa_awerror         ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_aa_awtarget_hot    ;\n  wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0]         st_aa_awtarget_enc    ;\n  wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0]                              aa_wm_awgrant_enc     ;\n  wire [(C_NUM_MASTER_SLOTS+1)-1:0]                               aa_mi_awtarget_hot    ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_aa_awvalid_qual    ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_ss_awvalid         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_ss_awready         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  ss_wr_awvalid         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  ss_wr_awready         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  ss_aa_awvalid         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  ss_aa_awready         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             sa_wm_awvalid         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             sa_wm_awready         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_awvalid            ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_awready            ;\n  wire                                                            aa_sa_awvalid         ;\n  wire                                                            aa_sa_awready         ;\n  wire                                                            aa_mi_arready         ;\n  wire                                                            mi_awvalid_en         ;\n  wire                                                            sa_wm_awvalid_en      ;\n  wire                                                            sa_wm_awready_mux     ;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0]                  si_st_armesg          ;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0]                  st_tmp_armesg         ;\n  wire [C_NUM_SLAVE_SLOTS*P_AA_ARMESG_WIDTH-1:0]                  tmp_aa_armesg         ;\n  wire [P_AA_ARMESG_WIDTH-1:0]                                    aa_mi_armesg          ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]                     st_aa_arid            ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]                   st_aa_araddr          ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                                  st_aa_arlen           ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                                  st_aa_arsize          ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                                  st_aa_arlock          ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                                  st_aa_arprot          ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                                  st_aa_arregion        ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                                  st_aa_arerror         ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_aa_artarget_hot    ;\n  wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0]         st_aa_artarget_enc    ;\n  wire [(C_NUM_MASTER_SLOTS+1)-1:0]                               aa_mi_artarget_hot    ;\n  wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0]                              aa_mi_argrant_enc     ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_aa_arvalid_qual    ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_aa_arvalid         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_aa_arready         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_arvalid            ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_arready            ;\n  wire                                                            aa_mi_arvalid         ;\n  wire                                                            mi_awready_mux        ;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_BMESG_WIDTH-1:0]                   st_si_bmesg           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*P_ST_BMESG_WIDTH-1:0]              st_mr_bmesg           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                st_mr_bid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*2-1:0]                             st_mr_bresp           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0]             st_mr_buser           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_bvalid          ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_bready          ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_tmp_bready         ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_tmp_bid_target     ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0]             tmp_mr_bid_target     ;\n  wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0]         debug_bid_target_i    ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             bid_match             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                mi_bid                ;\n  wire [(C_NUM_MASTER_SLOTS+1)*2-1:0]                             mi_bresp              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0]             mi_buser              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_bvalid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_bready             ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             bready_carry          ;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_RMESG_WIDTH-1:0]                   st_si_rmesg           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*P_ST_RMESG_WIDTH-1:0]              st_mr_rmesg           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                st_mr_rid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0]     st_mr_rdata           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0]             st_mr_ruser           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_rlast           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*2-1:0]                             st_mr_rresp           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_rvalid          ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_rready          ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_tmp_rready         ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_tmp_rid_target     ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0]             tmp_mr_rid_target     ;\n  wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0]         debug_rid_target_i    ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             rid_match             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                mi_rid                ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0]          mi_rdata              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0]             mi_ruser              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_rlast              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*2-1:0]                             mi_rresp              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_rvalid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_rready             ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             rready_carry          ;\n  wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0]                   si_wr_wmesg           ;\n  wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0]                   wr_wm_wmesg           ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  wr_wm_wlast           ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             wr_tmp_wvalid         ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             wr_tmp_wready         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0]             tmp_wm_wvalid         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0]             tmp_wm_wready         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*P_WR_WMESG_WIDTH-1:0]              wm_mr_wmesg              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0]          wm_mr_wdata              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0]        wm_mr_wstrb              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                wm_mr_wid              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0]             wm_mr_wuser              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             wm_mr_wlast              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             wm_mr_wvalid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             wm_mr_wready             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0]          mi_wdata              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0]        mi_wstrb              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0]             mi_wuser              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                mi_wid              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_wlast              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_wvalid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_wready             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             w_cmd_push            ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             w_cmd_pop             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             r_cmd_push            ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             r_cmd_pop             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_awmaxissuing      ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_armaxissuing      ;\n  reg  [(C_NUM_MASTER_SLOTS+1)*8-1:0]                             w_issuing_cnt        ;\n  reg  [(C_NUM_MASTER_SLOTS+1)*8-1:0]                             r_issuing_cnt        ;\n  reg  [8-1:0]                                                    debug_aw_trans_seq_i    ;\n  reg  [8-1:0]                                                    debug_ar_trans_seq_i    ;\n  wire [(C_NUM_MASTER_SLOTS+1)*8-1:0]                             debug_w_trans_seq_i     ;\n  reg  [(C_NUM_MASTER_SLOTS+1)*8-1:0]                             debug_w_beat_cnt_i      ;\n\n  reg aresetn_d = 1'b0; // Reset delay register\n  always @(posedge ACLK) begin\n    if (~ARESETN) begin\n      aresetn_d <= 1'b0;\n    end else begin\n      aresetn_d <= ARESETN;\n    end\n  end\n  wire reset;\n  assign reset = ~aresetn_d;\n\n  generate\n    for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_slave_slots\n      if (C_S_AXI_SUPPORTS_READ[gen_si_slot]) begin : gen_si_read\n        axi_crossbar_v2_1_16_si_transactor #  // \"ST\": SI Transactor (read channel)\n          (\n           .C_FAMILY                (C_FAMILY),\n           .C_SI                    (gen_si_slot),\n           .C_DIR                   (P_READ),\n           .C_NUM_ADDR_RANGES       (C_NUM_ADDR_RANGES),\n           .C_NUM_M                 (C_NUM_MASTER_SLOTS),\n           .C_NUM_M_LOG             (P_NUM_MASTER_SLOTS_LOG),\n           .C_ACCEPTANCE            (C_S_AXI_READ_ACCEPTANCE[gen_si_slot*32+:32]),\n           .C_ACCEPTANCE_LOG        (C_R_ACCEPT_WIDTH[gen_si_slot*32+:32]),\n           .C_ID_WIDTH              (C_AXI_ID_WIDTH),\n           .C_THREAD_ID_WIDTH       (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]),\n           .C_ADDR_WIDTH            (C_AXI_ADDR_WIDTH),\n           .C_AMESG_WIDTH           (P_ST_ARMESG_WIDTH),\n           .C_RMESG_WIDTH           (P_ST_RMESG_WIDTH),\n           .C_BASE_ID               (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),\n           .C_HIGH_ID               (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),\n           .C_SINGLE_THREAD         (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]),\n           .C_BASE_ADDR             (C_M_AXI_BASE_ADDR),\n           .C_HIGH_ADDR             (C_M_AXI_HIGH_ADDR),\n           .C_TARGET_QUAL           (P_S_AXI_READ_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]),\n           .C_M_AXI_SECURE          (C_M_AXI_SECURE),\n           .C_RANGE_CHECK           (C_RANGE_CHECK),\n           .C_ADDR_DECODE           (C_ADDR_DECODE),\n           .C_ERR_MODE              (C_M_AXI_ERR_MODE),\n           .C_DEBUG                 (C_DEBUG)\n           )\n          si_transactor_ar\n            (\n             .ACLK                  (ACLK),\n             .ARESET                (reset),\n             .S_AID                 (f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)),\n             .S_AADDR               (S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),\n             .S_ALEN                (S_AXI_ARLEN[gen_si_slot*8+:8]),\n             .S_ASIZE               (S_AXI_ARSIZE[gen_si_slot*3+:3]),\n             .S_ABURST              (S_AXI_ARBURST[gen_si_slot*2+:2]),\n             .S_ALOCK               (S_AXI_ARLOCK[gen_si_slot*2+:2]),\n             .S_APROT               (S_AXI_ARPROT[gen_si_slot*3+:3]),\n//             .S_AREGION             (S_AXI_ARREGION[gen_si_slot*4+:4]),\n             .S_AMESG               (si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]),\n             .S_AVALID              (S_AXI_ARVALID[gen_si_slot]),\n             .S_AREADY              (S_AXI_ARREADY[gen_si_slot]),\n             .M_AID                 (st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n             .M_AADDR               (st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),\n             .M_ALEN                (st_aa_arlen[gen_si_slot*8+:8]),\n             .M_ASIZE               (st_aa_arsize[gen_si_slot*3+:3]),\n             .M_ALOCK               (st_aa_arlock[gen_si_slot*2+:2]),\n             .M_APROT               (st_aa_arprot[gen_si_slot*3+:3]),\n             .M_AREGION             (st_aa_arregion[gen_si_slot*4+:4]),\n             .M_AMESG               (st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]),\n             .M_ATARGET_HOT         (st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .M_ATARGET_ENC         (st_aa_artarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),\n             .M_AERROR              (st_aa_arerror[gen_si_slot*8+:8]),\n             .M_AVALID_QUAL         (st_aa_arvalid_qual[gen_si_slot]),\n             .M_AVALID              (st_aa_arvalid[gen_si_slot]),\n             .M_AREADY              (st_aa_arready[gen_si_slot]),\n             .S_RID                 (S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n             .S_RMESG               (st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH]),\n             .S_RLAST               (S_AXI_RLAST[gen_si_slot]),\n             .S_RVALID              (S_AXI_RVALID[gen_si_slot]),\n             .S_RREADY              (S_AXI_RREADY[gen_si_slot]),\n             .M_RID                 (st_mr_rid),\n             .M_RLAST               (st_mr_rlast),\n             .M_RMESG               (st_mr_rmesg),\n             .M_RVALID              (st_mr_rvalid),\n             .M_RREADY              (st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .M_RTARGET             (st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .DEBUG_A_TRANS_SEQ     (C_DEBUG ? debug_ar_trans_seq_i : 8'h0)\n             );\n        \n        assign si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH] = {\n          S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH],\n          S_AXI_ARQOS[gen_si_slot*4+:4],\n          S_AXI_ARCACHE[gen_si_slot*4+:4],\n          S_AXI_ARBURST[gen_si_slot*2+:2]\n          };\n        assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = {\n          st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH],\n          st_aa_arregion[gen_si_slot*4+:4],\n          st_aa_arprot[gen_si_slot*3+:3],\n          st_aa_arlock[gen_si_slot*2+:2],\n          st_aa_arsize[gen_si_slot*3+:3],\n          st_aa_arlen[gen_si_slot*8+:8],\n          st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH],\n          st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]\n          };\n        assign S_AXI_RRESP[gen_si_slot*2+:2] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:2];\n        assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2 +: C_AXI_RUSER_WIDTH];\n        assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2+C_AXI_RUSER_WIDTH +: C_AXI_DATA_WIDTH];\n      end else begin : gen_no_si_read\n        assign S_AXI_ARREADY[gen_si_slot] = 1'b0;\n        assign st_aa_arvalid[gen_si_slot] = 1'b0;\n        assign st_aa_arvalid_qual[gen_si_slot] = 1'b1;\n        assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = 0;\n        assign S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;\n        assign S_AXI_RRESP[gen_si_slot*2+:2] = 0;\n        assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = 0;\n        assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0;\n        assign S_AXI_RVALID[gen_si_slot] = 1'b0;\n        assign S_AXI_RLAST[gen_si_slot] = 1'b0;\n        assign st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;\n        assign st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;\n      end  // gen_si_read\n        \n      if (C_S_AXI_SUPPORTS_WRITE[gen_si_slot]) begin : gen_si_write\n        axi_crossbar_v2_1_16_si_transactor #  // \"ST\": SI Transactor (write channel)\n          (\n           .C_FAMILY                (C_FAMILY),\n           .C_SI                    (gen_si_slot),\n           .C_DIR                   (P_WRITE),\n           .C_NUM_ADDR_RANGES       (C_NUM_ADDR_RANGES),\n           .C_NUM_M                 (C_NUM_MASTER_SLOTS),\n           .C_NUM_M_LOG             (P_NUM_MASTER_SLOTS_LOG),\n           .C_ACCEPTANCE            (C_S_AXI_WRITE_ACCEPTANCE[gen_si_slot*32+:32]),\n           .C_ACCEPTANCE_LOG        (C_W_ACCEPT_WIDTH[gen_si_slot*32+:32]),\n           .C_ID_WIDTH              (C_AXI_ID_WIDTH),\n           .C_THREAD_ID_WIDTH       (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]),\n           .C_ADDR_WIDTH            (C_AXI_ADDR_WIDTH),\n           .C_AMESG_WIDTH           (P_ST_AWMESG_WIDTH),\n           .C_RMESG_WIDTH           (P_ST_BMESG_WIDTH),\n           .C_BASE_ID               (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),\n           .C_HIGH_ID               (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),\n           .C_SINGLE_THREAD         (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]),\n           .C_BASE_ADDR             (C_M_AXI_BASE_ADDR),\n           .C_HIGH_ADDR             (C_M_AXI_HIGH_ADDR),\n           .C_TARGET_QUAL           (P_S_AXI_WRITE_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]),\n           .C_M_AXI_SECURE          (C_M_AXI_SECURE),\n           .C_RANGE_CHECK           (C_RANGE_CHECK),\n           .C_ADDR_DECODE           (C_ADDR_DECODE),\n           .C_ERR_MODE              (C_M_AXI_ERR_MODE),\n           .C_DEBUG                 (C_DEBUG)\n           )\n          si_transactor_aw\n            (\n             .ACLK                  (ACLK),\n             .ARESET                (reset),\n             .S_AID                 (f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)),\n             .S_AADDR               (S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),\n             .S_ALEN                (S_AXI_AWLEN[gen_si_slot*8+:8]),\n             .S_ASIZE               (S_AXI_AWSIZE[gen_si_slot*3+:3]),\n             .S_ABURST              (S_AXI_AWBURST[gen_si_slot*2+:2]),\n             .S_ALOCK               (S_AXI_AWLOCK[gen_si_slot*2+:2]),\n             .S_APROT               (S_AXI_AWPROT[gen_si_slot*3+:3]),\n//             .S_AREGION             (S_AXI_AWREGION[gen_si_slot*4+:4]),\n             .S_AMESG               (si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]),\n             .S_AVALID              (S_AXI_AWVALID[gen_si_slot]),\n             .S_AREADY              (S_AXI_AWREADY[gen_si_slot]),\n             .M_AID                 (st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n             .M_AADDR               (st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),\n             .M_ALEN                (st_aa_awlen[gen_si_slot*8+:8]),\n             .M_ASIZE               (st_aa_awsize[gen_si_slot*3+:3]),\n             .M_ALOCK               (st_aa_awlock[gen_si_slot*2+:2]),\n             .M_APROT               (st_aa_awprot[gen_si_slot*3+:3]),\n             .M_AREGION             (st_aa_awregion[gen_si_slot*4+:4]),\n             .M_AMESG               (st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]),\n             .M_ATARGET_HOT         (st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .M_ATARGET_ENC         (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),\n             .M_AERROR              (st_aa_awerror[gen_si_slot*8+:8]),\n             .M_AVALID_QUAL         (st_aa_awvalid_qual[gen_si_slot]),\n             .M_AVALID              (st_ss_awvalid[gen_si_slot]),\n             .M_AREADY              (st_ss_awready[gen_si_slot]),\n             .S_RID                 (S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n             .S_RMESG               (st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH]),\n             .S_RLAST               (),\n             .S_RVALID              (S_AXI_BVALID[gen_si_slot]),\n             .S_RREADY              (S_AXI_BREADY[gen_si_slot]),\n             .M_RID                 (st_mr_bid),\n             .M_RLAST               ({(C_NUM_MASTER_SLOTS+1){1'b1}}),\n             .M_RMESG               (st_mr_bmesg),\n             .M_RVALID              (st_mr_bvalid),\n             .M_RREADY              (st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .M_RTARGET             (st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .DEBUG_A_TRANS_SEQ     (C_DEBUG ? debug_aw_trans_seq_i : 8'h0)\n             );\n        \n        // Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.\n        assign si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH] = {\n          S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH],\n          S_AXI_AWQOS[gen_si_slot*4+:4],\n          S_AXI_AWCACHE[gen_si_slot*4+:4],\n          S_AXI_AWBURST[gen_si_slot*2+:2]\n          };\n        assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = {\n          st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH],\n          st_aa_awregion[gen_si_slot*4+:4],\n          st_aa_awprot[gen_si_slot*3+:3],\n          st_aa_awlock[gen_si_slot*2+:2],\n          st_aa_awsize[gen_si_slot*3+:3],\n          st_aa_awlen[gen_si_slot*8+:8],\n          st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH],\n          st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]\n          };\n        assign S_AXI_BRESP[gen_si_slot*2+:2] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:2];\n        assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+2 +: C_AXI_BUSER_WIDTH];\n                       \n        // AW SI-transactor transfer completes upon completion of both W-router address acceptance (command push) and AW arbitration\n        axi_crossbar_v2_1_16_splitter #  // \"SS\": Splitter from SI-Transactor (write channel)\n          (\n            .C_NUM_M                (2)\n          )\n          splitter_aw_si\n          (\n             .ACLK                  (ACLK),\n             .ARESET                (reset),\n             .S_VALID              (st_ss_awvalid[gen_si_slot]),\n             .S_READY              (st_ss_awready[gen_si_slot]),\n             .M_VALID              ({ss_wr_awvalid[gen_si_slot], ss_aa_awvalid[gen_si_slot]}),\n             .M_READY              ({ss_wr_awready[gen_si_slot], ss_aa_awready[gen_si_slot]})\n          );\n      \n        axi_crossbar_v2_1_16_wdata_router #  // \"WR\": Write data Router\n          (\n           .C_FAMILY                   (C_FAMILY),\n           .C_NUM_MASTER_SLOTS         (C_NUM_MASTER_SLOTS+1),\n           .C_SELECT_WIDTH             (P_NUM_MASTER_SLOTS_LOG+1),\n           .C_WMESG_WIDTH               (P_WR_WMESG_WIDTH),\n           .C_FIFO_DEPTH_LOG           (C_W_ACCEPT_WIDTH[gen_si_slot*32+:6])\n           )\n          wdata_router_w\n            (\n             .ACLK    (ACLK),\n             .ARESET  (reset),\n             // Write transfer input from the current SI-slot\n             .S_WMESG  (si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]),\n             .S_WLAST  (S_AXI_WLAST[gen_si_slot]),\n             .S_WVALID (S_AXI_WVALID[gen_si_slot]),\n             .S_WREADY (S_AXI_WREADY[gen_si_slot]),\n             // Vector of write transfer outputs to each MI-slot's W-mux\n             .M_WMESG  (wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH]),\n             .M_WLAST  (wr_wm_wlast[gen_si_slot]),\n             .M_WVALID (wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .M_WREADY (wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             // AW command push from local SI-slot\n             .S_ASELECT (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),  // Target MI-slot\n             .S_AVALID  (ss_wr_awvalid[gen_si_slot]),\n             .S_AREADY  (ss_wr_awready[gen_si_slot])\n             );\n             \n        assign si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH] = {\n          ((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1'b0),\n          S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH],\n          S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8],\n          S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]\n        };        \n      end else begin : gen_no_si_write\n        assign S_AXI_AWREADY[gen_si_slot] = 1'b0;\n        assign ss_aa_awvalid[gen_si_slot] = 1'b0;\n        assign st_aa_awvalid_qual[gen_si_slot] = 1'b1;\n        assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = 0;\n        assign S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;\n        assign S_AXI_BRESP[gen_si_slot*2+:2] = 0;\n        assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = 0;\n        assign S_AXI_BVALID[gen_si_slot] = 1'b0;\n        assign st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;\n        assign S_AXI_WREADY[gen_si_slot] = 1'b0;\n        assign wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH] = 0;\n        assign wr_wm_wlast[gen_si_slot] = 1'b0;\n        assign wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;\n        assign st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;\n      end  // gen_si_write\n    end  // gen_slave_slots\n    \n    for (gen_mi_slot=0; gen_mi_slot<C_NUM_MASTER_SLOTS+1; gen_mi_slot=gen_mi_slot+1) begin : gen_master_slots\n      if (P_M_AXI_SUPPORTS_READ[gen_mi_slot]) begin : gen_mi_read\n        if (C_NUM_SLAVE_SLOTS>1) begin : gen_rid_decoder\n          axi_crossbar_v2_1_16_addr_decoder #\n            (\n              .C_FAMILY          (C_FAMILY),\n              .C_NUM_TARGETS     (C_NUM_SLAVE_SLOTS),\n              .C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG),\n              .C_NUM_RANGES      (1),\n              .C_ADDR_WIDTH      (C_AXI_ID_WIDTH),\n              .C_TARGET_ENC      (C_DEBUG),\n              .C_TARGET_HOT      (1),\n              .C_REGION_ENC      (0),\n              .C_BASE_ADDR       (C_S_AXI_BASE_ID),\n              .C_HIGH_ADDR       (C_S_AXI_HIGH_ID),\n              .C_TARGET_QUAL     (P_M_AXI_READ_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]),\n              .C_RESOLUTION      (0)\n            ) \n            rid_decoder_inst \n            (\n              .ADDR             (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),        \n              .TARGET_HOT       (tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),  \n              .TARGET_ENC       (debug_rid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]),  \n              .MATCH            (rid_match[gen_mi_slot]),       \n              .REGION           ()      \n            );\n        end else begin : gen_no_rid_decoder\n          assign tmp_mr_rid_target[gen_mi_slot] = 1'b1;  // All response transfers route to solo SI-slot.\n          assign rid_match[gen_mi_slot] = 1'b1;\n        end\n        \n        assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = {\n          st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],\n          st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH], \n          st_mr_rresp[gen_mi_slot*2+:2]\n          }; \n      end else begin : gen_no_mi_read\n        assign tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;\n        assign rid_match[gen_mi_slot] = 1'b0;\n        assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = 0;\n      end  // gen_mi_read\n      \n      if (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot]) begin : gen_mi_write\n        if (C_NUM_SLAVE_SLOTS>1) begin : gen_bid_decoder\n          axi_crossbar_v2_1_16_addr_decoder #\n            (\n              .C_FAMILY          (C_FAMILY),\n              .C_NUM_TARGETS     (C_NUM_SLAVE_SLOTS),\n              .C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG),\n              .C_NUM_RANGES      (1),\n              .C_ADDR_WIDTH      (C_AXI_ID_WIDTH),\n              .C_TARGET_ENC      (C_DEBUG),\n              .C_TARGET_HOT      (1),\n              .C_REGION_ENC      (0),\n              .C_BASE_ADDR       (C_S_AXI_BASE_ID),\n              .C_HIGH_ADDR       (C_S_AXI_HIGH_ID),\n              .C_TARGET_QUAL     (P_M_AXI_WRITE_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]),\n              .C_RESOLUTION      (0)\n            ) \n            bid_decoder_inst \n            (\n              .ADDR             (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),        \n              .TARGET_HOT       (tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),  \n              .TARGET_ENC       (debug_bid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]),  \n              .MATCH            (bid_match[gen_mi_slot]),       \n              .REGION           ()      \n            );\n        end else begin : gen_no_bid_decoder\n          assign tmp_mr_bid_target[gen_mi_slot] = 1'b1;  // All response transfers route to solo SI-slot.\n          assign bid_match[gen_mi_slot] = 1'b1;\n        end\n      \n        axi_crossbar_v2_1_16_wdata_mux #  // \"WM\": Write data Mux, per MI-slot (incl error-handler)\n          (\n           .C_FAMILY                   (C_FAMILY),\n           .C_NUM_SLAVE_SLOTS         (C_NUM_SLAVE_SLOTS),\n           .C_SELECT_WIDTH     (P_NUM_SLAVE_SLOTS_LOG),\n           .C_WMESG_WIDTH               (P_WR_WMESG_WIDTH),\n           .C_FIFO_DEPTH_LOG           (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6])\n           )\n          wdata_mux_w\n            (\n             .ACLK    (ACLK),\n             .ARESET  (reset),\n             // Vector of write transfer inputs from each SI-slot's W-router\n             .S_WMESG  (wr_wm_wmesg),\n             .S_WLAST  (wr_wm_wlast),\n             .S_WVALID (tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),\n             .S_WREADY (tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),\n             // Write transfer output to the current MI-slot\n             .M_WMESG  (wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]),\n             .M_WLAST  (wm_mr_wlast[gen_mi_slot]),\n             .M_WVALID (wm_mr_wvalid[gen_mi_slot]),\n             .M_WREADY (wm_mr_wready[gen_mi_slot]),\n             // AW command push from AW arbiter output\n             .S_ASELECT (aa_wm_awgrant_enc),  // SI-slot selected by arbiter\n             .S_AVALID  (sa_wm_awvalid[gen_mi_slot]),\n             .S_AREADY  (sa_wm_awready[gen_mi_slot])\n             );\n             \n        if (C_DEBUG) begin : gen_debug_w\n          // DEBUG WRITE BEAT COUNTER\n          always @(posedge ACLK) begin\n            if (reset) begin\n              debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0;\n            end else begin\n              if (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot]) begin\n                if (mi_wlast[gen_mi_slot]) begin\n                  debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0;\n                end else begin\n                  debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= debug_w_beat_cnt_i[gen_mi_slot*8+:8] + 1;\n                end\n              end\n            end\n          end  // clocked process\n  \n          // DEBUG W-CHANNEL TRANSACTION SEQUENCE QUEUE\n          axi_data_fifo_v2_1_14_axic_srl_fifo #\n            (\n             .C_FAMILY          (C_FAMILY),\n             .C_FIFO_WIDTH      (8),\n             .C_FIFO_DEPTH_LOG  (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]),\n             .C_USE_FULL        (0)\n             )\n            debug_w_seq_fifo\n              (\n               .ACLK    (ACLK),\n               .ARESET  (reset),\n               .S_MESG  (debug_aw_trans_seq_i),\n               .S_VALID (sa_wm_awvalid[gen_mi_slot]),\n               .S_READY (),\n               .M_MESG  (debug_w_trans_seq_i[gen_mi_slot*8+:8]),\n               .M_VALID (),\n               .M_READY (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot] & mi_wlast[gen_mi_slot])\n              );\n        end  // gen_debug_w\n             \n        assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH +: C_AXI_DATA_WIDTH];\n        assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8];\n        assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH];\n        assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+(C_AXI_DATA_WIDTH/8)+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH];\n        assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = {\n          st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH],\n          st_mr_bresp[gen_mi_slot*2+:2]\n          }; \n      end else begin : gen_no_mi_write\n        assign tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;\n        assign bid_match[gen_mi_slot] = 1'b0;\n        assign wm_mr_wvalid[gen_mi_slot] = 0;\n        assign wm_mr_wlast[gen_mi_slot] = 0;\n        assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0;\n        assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = 0;\n        assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = 0;\n        assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;\n        assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = 0;\n        assign tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;\n        assign sa_wm_awready[gen_mi_slot] = 0;\n      end  // gen_mi_write\n      \n      for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_trans_si\n        // Transpose handshakes from W-router (SxM) to W-mux (MxS).\n        assign tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot] = wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot];\n        assign wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];\n        // Transpose response enables from ID decoders (MxS) to si_transactors (SxM).\n        assign st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];\n        assign st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];\n      end  // gen_trans_si\n      \n      assign bready_carry[gen_mi_slot] =  st_tmp_bready[gen_mi_slot];\n      assign rready_carry[gen_mi_slot] =  st_tmp_rready[gen_mi_slot];\n      for (gen_si_slot=1; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_resp_carry_si\n        assign bready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] =  // Generate M_BREADY if ...\n          bready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] |  // For any SI-slot (OR carry-chain across all SI-slots), ...\n          st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot];  // The write SI transactor indicates BREADY for that MI-slot.\n        assign rready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] =  // Generate M_RREADY if ...\n          rready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] |  // For any SI-slot (OR carry-chain across all SI-slots), ...\n          st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot];  // The write SI transactor indicates RREADY for that MI-slot.\n      end  // gen_resp_carry_si\n           \n      assign w_cmd_push[gen_mi_slot] = mi_awvalid[gen_mi_slot] && mi_awready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot];\n      assign r_cmd_push[gen_mi_slot] = mi_arvalid[gen_mi_slot] && mi_arready[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot];\n      assign w_cmd_pop[gen_mi_slot] = st_mr_bvalid[gen_mi_slot] && st_mr_bready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot];\n      assign r_cmd_pop[gen_mi_slot] = st_mr_rvalid[gen_mi_slot] && st_mr_rready[gen_mi_slot] && st_mr_rlast[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot];\n      // Disqualify arbitration of SI-slot if targeted MI-slot has reached its issuing limit.\n      assign mi_awmaxissuing[gen_mi_slot] = (w_issuing_cnt[gen_mi_slot*8 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] == \n          P_M_AXI_WRITE_ISSUING[gen_mi_slot*32 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~w_cmd_pop[gen_mi_slot];\n      assign mi_armaxissuing[gen_mi_slot] = (r_issuing_cnt[gen_mi_slot*8 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] == \n          P_M_AXI_READ_ISSUING[gen_mi_slot*32 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~r_cmd_pop[gen_mi_slot];\n      \n      always @(posedge ACLK) begin\n        if (reset) begin\n          w_issuing_cnt[gen_mi_slot*8+:8] <= 0;  // Some high-order bits remain constant 0\n          r_issuing_cnt[gen_mi_slot*8+:8] <= 0;  // Some high-order bits remain constant 0\n        end else begin\n          if (w_cmd_push[gen_mi_slot] && ~w_cmd_pop[gen_mi_slot]) begin\n            w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1;\n          end else if (w_cmd_pop[gen_mi_slot] && ~w_cmd_push[gen_mi_slot] && (|w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin\n            w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1;\n          end\n          if (r_cmd_push[gen_mi_slot] && ~r_cmd_pop[gen_mi_slot]) begin\n            r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1;\n          end else if (r_cmd_pop[gen_mi_slot] && ~r_cmd_push[gen_mi_slot] && (|r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin\n            r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1;\n          end\n        end\n      end  // Clocked process\n      \n      // Reg-slice must break combinatorial path from M_BID and M_RID inputs to M_BREADY and M_RREADY outputs.\n      //   (See m_rready_i and m_resp_en combinatorial assignments in si_transactor.)\n      //   Reg-slice incurs +1 latency, but no bubble-cycles.\n      axi_register_slice_v2_1_15_axi_register_slice #  // \"MR\": MI-side R/B-channel Reg-slice, per MI-slot (pass-through if only 1 SI-slot configured)\n        (\n          .C_FAMILY                         (C_FAMILY),\n          .C_AXI_PROTOCOL                   ((C_AXI_PROTOCOL == P_AXI3) ? P_AXI3 : P_AXI4),\n          .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),\n          .C_AXI_ADDR_WIDTH                 (1),\n          .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),\n          .C_AXI_SUPPORTS_USER_SIGNALS      (C_AXI_SUPPORTS_USER_SIGNALS),\n          .C_AXI_AWUSER_WIDTH               (1),\n          .C_AXI_ARUSER_WIDTH               (1),\n          .C_AXI_WUSER_WIDTH                (C_AXI_WUSER_WIDTH),\n          .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),\n          .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),\n          .C_REG_CONFIG_AW                  (P_BYPASS),\n          .C_REG_CONFIG_AR                  (P_BYPASS),\n          .C_REG_CONFIG_W                   (P_BYPASS),\n          .C_REG_CONFIG_R                   (P_M_AXI_SUPPORTS_READ[gen_mi_slot] ? P_FWD_REV : P_BYPASS),\n          .C_REG_CONFIG_B                   (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot] ? P_SIMPLE : P_BYPASS)\n        )\n        reg_slice_mi \n        (\n          .aresetn                          (ARESETN),\n          .aclk                             (ACLK),\n          .s_axi_awid                       ({C_AXI_ID_WIDTH{1'b0}}),\n          .s_axi_awaddr                     ({1{1'b0}}),\n          .s_axi_awlen                      ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1'b0}}),\n          .s_axi_awsize                     ({3{1'b0}}),\n          .s_axi_awburst                    ({2{1'b0}}),\n          .s_axi_awlock                     ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1'b0}}),\n          .s_axi_awcache                    ({4{1'b0}}),\n          .s_axi_awprot                     ({3{1'b0}}),\n          .s_axi_awregion                   ({4{1'b0}}),\n          .s_axi_awqos                      ({4{1'b0}}),\n          .s_axi_awuser                     ({1{1'b0}}),\n          .s_axi_awvalid                    ({1{1'b0}}),\n          .s_axi_awready                    (),\n          .s_axi_wid                        (wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n          .s_axi_wdata                      (wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),\n          .s_axi_wstrb                      (wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]),\n          .s_axi_wlast                      (wm_mr_wlast[gen_mi_slot]),\n          .s_axi_wuser                      (wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]),\n          .s_axi_wvalid                     (wm_mr_wvalid[gen_mi_slot]),\n          .s_axi_wready                     (wm_mr_wready[gen_mi_slot]),\n          .s_axi_bid                        (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]         ),\n          .s_axi_bresp                      (st_mr_bresp[gen_mi_slot*2+:2]                                 ),\n          .s_axi_buser                      (st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] ),\n          .s_axi_bvalid                     (st_mr_bvalid[gen_mi_slot*1+:1]                                ),\n          .s_axi_bready                     (st_mr_bready[gen_mi_slot*1+:1]                                ),\n          .s_axi_arid                       ({C_AXI_ID_WIDTH{1'b0}}),\n          .s_axi_araddr                     ({1{1'b0}}),\n          .s_axi_arlen                      ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1'b0}}),\n          .s_axi_arsize                     ({3{1'b0}}),\n          .s_axi_arburst                    ({2{1'b0}}),\n          .s_axi_arlock                     ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1'b0}}),\n          .s_axi_arcache                    ({4{1'b0}}),\n          .s_axi_arprot                     ({3{1'b0}}),\n          .s_axi_arregion                   ({4{1'b0}}),\n          .s_axi_arqos                      ({4{1'b0}}),\n          .s_axi_aruser                     ({1{1'b0}}),\n          .s_axi_arvalid                    ({1{1'b0}}),\n          .s_axi_arready                    (),\n          .s_axi_rid                        (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                          ),\n          .s_axi_rdata                      (st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]  ),\n          .s_axi_rresp                      (st_mr_rresp[gen_mi_slot*2+:2]                                                  ),\n          .s_axi_rlast                      (st_mr_rlast[gen_mi_slot*1+:1]                                                  ),\n          .s_axi_ruser                      (st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                  ),\n          .s_axi_rvalid                     (st_mr_rvalid[gen_mi_slot*1+:1]                                                 ),\n          .s_axi_rready                     (st_mr_rready[gen_mi_slot*1+:1]                                                 ),\n          .m_axi_awid                       (),\n          .m_axi_awaddr                     (),\n          .m_axi_awlen                      (),\n          .m_axi_awsize                     (),\n          .m_axi_awburst                    (),\n          .m_axi_awlock                     (),\n          .m_axi_awcache                    (),\n          .m_axi_awprot                     (),\n          .m_axi_awregion                   (),\n          .m_axi_awqos                      (),\n          .m_axi_awuser                     (),\n          .m_axi_awvalid                    (),\n          .m_axi_awready                    ({1{1'b0}}),\n          .m_axi_wid                        (mi_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n          .m_axi_wdata                      (mi_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),\n          .m_axi_wstrb                      (mi_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]),\n          .m_axi_wlast                      (mi_wlast[gen_mi_slot]),\n          .m_axi_wuser                      (mi_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]),\n          .m_axi_wvalid                     (mi_wvalid[gen_mi_slot]),\n          .m_axi_wready                     (mi_wready[gen_mi_slot]),\n          .m_axi_bid                        (mi_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                          ),\n          .m_axi_bresp                      (mi_bresp[gen_mi_slot*2+:2]                                                  ),\n          .m_axi_buser                      (mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                  ),\n          .m_axi_bvalid                     (mi_bvalid[gen_mi_slot*1+:1]                                                 ),\n          .m_axi_bready                     (mi_bready[gen_mi_slot*1+:1]                                                 ),\n          .m_axi_arid                       (),\n          .m_axi_araddr                     (),\n          .m_axi_arlen                      (),\n          .m_axi_arsize                     (),\n          .m_axi_arburst                    (),\n          .m_axi_arlock                     (),\n          .m_axi_arcache                    (),\n          .m_axi_arprot                     (),\n          .m_axi_arregion                   (),\n          .m_axi_arqos                      (),\n          .m_axi_aruser                     (),\n          .m_axi_arvalid                    (),\n          .m_axi_arready                    ({1{1'b0}}),\n          .m_axi_rid                        (mi_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                          ),\n          .m_axi_rdata                      (mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]  ),\n          .m_axi_rresp                      (mi_rresp[gen_mi_slot*2+:2]                                                  ),\n          .m_axi_rlast                      (mi_rlast[gen_mi_slot*1+:1]                                                  ),\n          .m_axi_ruser                      (mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                  ),\n          .m_axi_rvalid                     (mi_rvalid[gen_mi_slot*1+:1]                                                 ),\n          .m_axi_rready                     (mi_rready[gen_mi_slot*1+:1]                                                 )\n        );\n    end  // gen_master_slots (Next gen_mi_slot)\n  \n    // Highest row of *ready_carry contains accumulated OR across all SI-slots, for each MI-slot.\n    assign st_mr_bready = bready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1]; \n    assign st_mr_rready = rready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1]; \n    // Assign MI-side B, R and W channel ports (exclude error handler signals).\n    assign mi_bid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_BID;\n    assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID; \n    assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP;\n    assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER;\n    assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS];\n    assign mi_rid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_RID;\n    assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST; \n    assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID; \n    assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP;\n    assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER;\n    assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA;\n    assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS];\n    assign M_AXI_WLAST = mi_wlast[0+:C_NUM_MASTER_SLOTS];\n    assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS];\n    assign M_AXI_WUSER = mi_wuser[0+:C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH];\n    assign M_AXI_WID = (C_AXI_PROTOCOL == P_AXI3) ? mi_wid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] : 0;\n    assign M_AXI_WDATA = mi_wdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH];\n    assign M_AXI_WSTRB = mi_wstrb[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8];\n    assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY;\n\n    axi_crossbar_v2_1_16_addr_arbiter #  // \"AA\": Addr Arbiter (AW channel)\n      (\n       .C_FAMILY                (C_FAMILY),\n       .C_NUM_M                 (C_NUM_MASTER_SLOTS+1),\n       .C_NUM_S                 (C_NUM_SLAVE_SLOTS),\n       .C_NUM_S_LOG             (P_NUM_SLAVE_SLOTS_LOG),\n       .C_MESG_WIDTH            (P_AA_AWMESG_WIDTH),\n       .C_ARB_PRIORITY          (C_S_AXI_ARB_PRIORITY)\n       )\n      addr_arbiter_aw\n        (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         // Vector of SI-side AW command request inputs\n         .S_MESG                (tmp_aa_awmesg),\n         .S_TARGET_HOT          (st_aa_awtarget_hot),\n         .S_VALID               (ss_aa_awvalid),\n         .S_VALID_QUAL          (st_aa_awvalid_qual),\n         .S_READY               (ss_aa_awready),\n         // Granted AW command output\n         .M_MESG                (aa_mi_awmesg),\n         .M_TARGET_HOT          (aa_mi_awtarget_hot),  // MI-slot targeted by granted command\n         .M_GRANT_ENC           (aa_wm_awgrant_enc),  // SI-slot index of granted command\n         .M_VALID               (aa_sa_awvalid),\n         .M_READY               (aa_sa_awready),\n         .ISSUING_LIMIT        (mi_awmaxissuing)\n        );\n         \n    // Broadcast AW transfer payload to all MI-slots\n    assign M_AXI_AWID        = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[0+:C_AXI_ID_WIDTH]}};\n    assign M_AXI_AWADDR      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}};\n    assign M_AXI_AWLEN       = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}};\n    assign M_AXI_AWSIZE      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}};\n    assign M_AXI_AWLOCK      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}};\n    assign M_AXI_AWPROT      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}};\n    assign M_AXI_AWREGION    = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}};\n    assign M_AXI_AWBURST     = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}};\n    assign M_AXI_AWCACHE     = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}};\n    assign M_AXI_AWQOS       = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}};\n    assign M_AXI_AWUSER      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_AWUSER_WIDTH]}};\n         \n    axi_crossbar_v2_1_16_addr_arbiter #  // \"AA\": Addr Arbiter (AR channel)\n      (\n       .C_FAMILY                (C_FAMILY),\n       .C_NUM_M                 (C_NUM_MASTER_SLOTS+1),\n       .C_NUM_S                 (C_NUM_SLAVE_SLOTS),\n       .C_NUM_S_LOG             (P_NUM_SLAVE_SLOTS_LOG),\n       .C_MESG_WIDTH            (P_AA_ARMESG_WIDTH),\n       .C_ARB_PRIORITY          (C_S_AXI_ARB_PRIORITY)\n       )\n      addr_arbiter_ar\n        (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         // Vector of SI-side AR command request inputs\n         .S_MESG                (tmp_aa_armesg),\n         .S_TARGET_HOT          (st_aa_artarget_hot),\n         .S_VALID_QUAL          (st_aa_arvalid_qual),\n         .S_VALID               (st_aa_arvalid),\n         .S_READY               (st_aa_arready),\n         // Granted AR command output\n         .M_MESG                (aa_mi_armesg),\n         .M_TARGET_HOT          (aa_mi_artarget_hot),  // MI-slot targeted by granted command\n         .M_GRANT_ENC           (aa_mi_argrant_enc),\n         .M_VALID               (aa_mi_arvalid),  // SI-slot index of granted command\n         .M_READY               (aa_mi_arready),\n         .ISSUING_LIMIT        (mi_armaxissuing)\n        );\n    \n    if (C_DEBUG) begin : gen_debug_trans_seq\n      // DEBUG WRITE TRANSACTION SEQUENCE COUNTER\n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_aw_trans_seq_i <= 1;\n        end else begin\n          if (aa_sa_awvalid && aa_sa_awready) begin\n            debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1;\n          end\n        end\n      end\n  \n      // DEBUG READ TRANSACTION SEQUENCE COUNTER\n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_ar_trans_seq_i <= 1;\n        end else begin\n          if (aa_mi_arvalid && aa_mi_arready) begin\n            debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1;\n          end\n        end\n      end\n    end  // gen_debug_trans_seq\n\n    // Broadcast AR transfer payload to all MI-slots\n    assign M_AXI_ARID        = {C_NUM_MASTER_SLOTS{aa_mi_armesg[0+:C_AXI_ID_WIDTH]}};\n    assign M_AXI_ARADDR      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}};\n    assign M_AXI_ARLEN       = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}};\n    assign M_AXI_ARSIZE      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}};\n    assign M_AXI_ARLOCK      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}};\n    assign M_AXI_ARPROT      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}};\n    assign M_AXI_ARREGION    = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}};\n    assign M_AXI_ARBURST     = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}};\n    assign M_AXI_ARCACHE     = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}};\n    assign M_AXI_ARQOS       = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}};\n    assign M_AXI_ARUSER      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_ARUSER_WIDTH]}};\n         \n    // AW arbiter command transfer completes upon completion of both M-side AW-channel transfer and W-mux address acceptance (command push).\n    axi_crossbar_v2_1_16_splitter #  // \"SA\": Splitter for Write Addr Arbiter\n      (\n        .C_NUM_M                (2)\n      )\n      splitter_aw_mi\n      (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         .S_VALID              (aa_sa_awvalid),\n         .S_READY              (aa_sa_awready),\n         .M_VALID              ({mi_awvalid_en, sa_wm_awvalid_en}),\n         .M_READY              ({mi_awready_mux, sa_wm_awready_mux})\n      );\n      \n    assign mi_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{mi_awvalid_en}};\n    assign mi_awready_mux = |(aa_mi_awtarget_hot & mi_awready);\n    assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS];  // Slot C_NUM_MASTER_SLOTS+1 is the error handler\n    assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY;\n    assign sa_wm_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{sa_wm_awvalid_en}};\n    assign sa_wm_awready_mux = |(aa_mi_awtarget_hot & sa_wm_awready);\n    \n    assign mi_arvalid = aa_mi_artarget_hot & {C_NUM_MASTER_SLOTS+1{aa_mi_arvalid}};\n    assign aa_mi_arready = |(aa_mi_artarget_hot & mi_arready);\n    assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS];  // Slot C_NUM_MASTER_SLOTS+1 is the error handler\n    assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY;\n    \n    // MI-slot # C_NUM_MASTER_SLOTS is the error handler\n    if (C_RANGE_CHECK) begin : gen_decerr_slave\n      axi_crossbar_v2_1_16_decerr_slave #\n        (\n         .C_AXI_ID_WIDTH                 (C_AXI_ID_WIDTH),\n         .C_AXI_DATA_WIDTH               (C_AXI_DATA_WIDTH),\n         .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),\n         .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),\n         .C_AXI_PROTOCOL                 (C_AXI_PROTOCOL),\n         .C_RESP                         (P_DECERR) \n        )\n        decerr_slave_inst\n          (\n           .S_AXI_ACLK (ACLK),\n           .S_AXI_ARESET (reset),\n           .S_AXI_AWID (aa_mi_awmesg[0+:C_AXI_ID_WIDTH]),\n           .S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_WLAST (mi_wlast[C_NUM_MASTER_SLOTS]),\n           .S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_BID (mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n           .S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]),\n           .S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]),\n           .S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_ARID (aa_mi_armesg[0+:C_AXI_ID_WIDTH]),\n           .S_AXI_ARLEN (aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]),\n           .S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RID (mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n           .S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),\n           .S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]),\n           .S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]),\n           .S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS])\n         );\n    end else begin : gen_no_decerr_slave\n      assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;\n      assign mi_wready[C_NUM_MASTER_SLOTS] = 1'b0;\n      assign mi_arready[C_NUM_MASTER_SLOTS] = 1'b0;\n      assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;\n      assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;\n      assign mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                    = 0;\n      assign mi_bresp[C_NUM_MASTER_SLOTS*2+:2]                                            = 0;\n      assign mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]            = 0;\n      assign mi_bvalid[C_NUM_MASTER_SLOTS]                                                = 1'b0;\n      assign mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                    = 0;\n      assign mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0; \n      assign mi_rresp[C_NUM_MASTER_SLOTS*2+:2]                                            = 0; \n      assign mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]            = 0; \n      assign mi_rlast[C_NUM_MASTER_SLOTS]                                                  = 1'b0;\n      assign mi_rvalid[C_NUM_MASTER_SLOTS]                                                 = 1'b0;\n    end  // gen_decerr_slave\n  endgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: decerr_slave.v\n//\n// Description: \n//   Phantom slave interface used to complete W, R and B channel transfers when an\n//   erroneous transaction is trapped in the crossbar.\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    decerr_slave\n//    \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_16_decerr_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH           = 1,\n   parameter integer C_AXI_DATA_WIDTH         = 32,\n   parameter integer C_AXI_BUSER_WIDTH        = 1,\n   parameter integer C_AXI_RUSER_WIDTH        = 1,\n   parameter integer C_AXI_PROTOCOL           = 0,\n   parameter integer C_RESP                   = 2'b11   \n   )\n  (\n   input wire S_AXI_ACLK,\n   input wire S_AXI_ARESET,\n   input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,\n   input wire S_AXI_AWVALID,\n   output wire S_AXI_AWREADY,\n   input wire S_AXI_WLAST,\n   input wire S_AXI_WVALID,\n   output wire S_AXI_WREADY,\n   output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,\n   output wire [1:0] S_AXI_BRESP,\n   output wire [C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,\n   output wire S_AXI_BVALID,\n   input wire S_AXI_BREADY,\n   input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,\n   input wire [7:0] S_AXI_ARLEN,\n   input wire S_AXI_ARVALID,\n   output wire S_AXI_ARREADY,\n   output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,\n   output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,\n   output wire [1:0] S_AXI_RRESP,\n   output wire [C_AXI_RUSER_WIDTH-1:0]          S_AXI_RUSER,\n   output wire S_AXI_RLAST,\n   output wire S_AXI_RVALID,\n   input wire S_AXI_RREADY\n   );\n   \n  reg s_axi_awready_i = 1'b0;\n  reg s_axi_wready_i = 1'b0;\n  reg s_axi_bvalid_i = 1'b0;\n  reg s_axi_arready_i = 1'b0;\n  reg s_axi_rvalid_i = 1'b0;\n  \n  localparam P_WRITE_IDLE = 2'b00;\n  localparam P_WRITE_DATA = 2'b01;\n  localparam P_WRITE_RESP = 2'b10;\n  localparam P_READ_IDLE = 1'b0;\n  localparam P_READ_DATA = 1'b1;\n  localparam integer  P_AXI4 = 0;\n  localparam integer  P_AXI3 = 1;\n  localparam integer  P_AXILITE = 2;\n   \n  assign S_AXI_BRESP = C_RESP;\n  assign S_AXI_RRESP = C_RESP;\n  assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};\n  assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};\n  assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};\n  assign S_AXI_AWREADY = s_axi_awready_i;\n  assign S_AXI_WREADY = s_axi_wready_i;\n  assign S_AXI_BVALID = s_axi_bvalid_i;\n  assign S_AXI_ARREADY = s_axi_arready_i;\n  assign S_AXI_RVALID = s_axi_rvalid_i;\n  \n  generate\n  if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite\n    \n    assign S_AXI_RLAST = 1'b1;\n    assign S_AXI_BID = 0;\n    assign S_AXI_RID = 0;\n    \n    always @(posedge S_AXI_ACLK) begin\n      if (S_AXI_ARESET) begin\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        if (s_axi_bvalid_i) begin\n          if (S_AXI_BREADY) begin\n            s_axi_bvalid_i <= 1'b0;\n          end\n        end else if (S_AXI_AWVALID & S_AXI_WVALID) begin\n          if (s_axi_awready_i) begin\n            s_axi_awready_i <= 1'b0;\n            s_axi_wready_i <= 1'b0;\n            s_axi_bvalid_i <= 1'b1;\n          end else begin\n            s_axi_awready_i <= 1'b1;\n            s_axi_wready_i <= 1'b1;\n          end\n        end\n      end\n    end\n           \n    always @(posedge S_AXI_ACLK) begin\n      if (S_AXI_ARESET) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n      end else begin\n        if (s_axi_rvalid_i) begin\n          if (S_AXI_RREADY) begin\n            s_axi_rvalid_i <= 1'b0;\n          end\n        end else if (S_AXI_ARVALID & s_axi_arready_i) begin\n          s_axi_arready_i <= 1'b0;\n          s_axi_rvalid_i <= 1'b1;\n        end else begin\n          s_axi_arready_i <= 1'b1;\n        end\n      end\n    end\n        \n  end else begin : gen_axi\n  \n    reg s_axi_rlast_i;\n    reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;\n    reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;\n    reg [7:0] read_cnt;\n    reg [1:0] write_cs;\n    reg [0:0] read_cs;\n  \n    assign S_AXI_RLAST = s_axi_rlast_i;\n    assign S_AXI_BID = s_axi_bid_i;\n    assign S_AXI_RID = s_axi_rid_i;\n  \n    always @(posedge S_AXI_ACLK) begin\n      if (S_AXI_ARESET) begin\n        write_cs <= P_WRITE_IDLE;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n        s_axi_bid_i <= 0;\n      end else begin\n        case (write_cs) \n          P_WRITE_IDLE: \n            begin\n              if (S_AXI_AWVALID & s_axi_awready_i) begin\n                s_axi_awready_i <= 1'b0;\n                s_axi_bid_i <= S_AXI_AWID;\n                s_axi_wready_i <= 1'b1;\n                write_cs <= P_WRITE_DATA;\n              end else begin\n                s_axi_awready_i <= 1'b1;\n              end\n            end\n          P_WRITE_DATA:\n            begin\n              if (S_AXI_WVALID & S_AXI_WLAST) begin\n                s_axi_wready_i <= 1'b0;\n                s_axi_bvalid_i <= 1'b1;\n                write_cs <= P_WRITE_RESP;\n              end\n            end\n          P_WRITE_RESP:\n            begin\n              if (S_AXI_BREADY) begin\n                s_axi_bvalid_i <= 1'b0;\n                s_axi_awready_i <= 1'b1;\n                write_cs <= P_WRITE_IDLE;\n              end\n            end\n        endcase\n      end\n    end\n  \n    always @(posedge S_AXI_ACLK) begin\n      if (S_AXI_ARESET) begin\n        read_cs <= P_READ_IDLE;\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        s_axi_rlast_i <= 1'b0;\n        s_axi_rid_i <= 0;\n        read_cnt <= 0;\n      end else begin\n        case (read_cs) \n          P_READ_IDLE: \n            begin\n              if (S_AXI_ARVALID & s_axi_arready_i) begin\n                s_axi_arready_i <= 1'b0;\n                s_axi_rid_i <= S_AXI_ARID;\n                read_cnt <= S_AXI_ARLEN;\n                s_axi_rvalid_i <= 1'b1;\n                if (S_AXI_ARLEN == 0) begin\n                  s_axi_rlast_i <= 1'b1;\n                end else begin\n                  s_axi_rlast_i <= 1'b0;\n                end\n                read_cs <= P_READ_DATA;\n              end else begin\n                s_axi_arready_i <= 1'b1;\n              end\n            end\n          P_READ_DATA:\n            begin\n              if (S_AXI_RREADY) begin\n                if (read_cnt == 0) begin\n                  s_axi_rvalid_i <= 1'b0;\n                  s_axi_rlast_i <= 1'b0;\n                  s_axi_arready_i <= 1'b1;\n                  read_cs <= P_READ_IDLE;\n                end else begin\n                  if (read_cnt == 1) begin\n                    s_axi_rlast_i <= 1'b1;\n                  end\n                  read_cnt <= read_cnt - 1;\n                end\n              end\n            end\n        endcase\n      end\n    end\n  \n  end  \n  endgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: si_transactor.v\n//\n// Description: \n//   This module manages multi-threaded transactions for one SI-slot.\n//   The module interface consists of a 1-slave to 1-master address channel, plus a\n//     (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel.\n//   The module maintains transaction thread control registers that count the\n//     number of outstanding transations for each thread and the target MI-slot.\n//   On the address channel, the module decodes addresses to select among MI-slots \n//     accessible to the SI-slot where it is instantiated.\n//     It then qualifies whether each received transaction\n//     should be propagated as a request to the address channel arbiter.\n//     Transactions are blocked while there is any outstanding transaction to a \n//     different slave (MI-slot) for the requested ID thread (for deadlock avoidance).\n//   On the response channel, the module mulitplexes transfers from each of the \n//     MI-slots whenever a transfer targets the ID of an active thread,\n//     arbitrating between MI-slots if multiple threads respond concurrently.\n//\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    si_transactor\n//      addr_decoder\n//        comparator_static\n//      mux_enc\n//      axic_srl_fifo\n//      arbiter_resp\n//      \n//-----------------------------------------------------------------------------\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_16_si_transactor #\n  (\n   parameter         C_FAMILY                       = \"none\", \n   parameter integer C_SI             =   0, // SI-slot number of current instance.\n   parameter integer C_DIR             =   0, // Direction: 0 = Write; 1 = Read.\n   parameter integer C_NUM_ADDR_RANGES = 1,\n   parameter integer C_NUM_M             =   2, \n   parameter integer C_NUM_M_LOG             =   1, \n   parameter integer C_ACCEPTANCE             =   1,  // Acceptance limit of this SI-slot.\n   parameter integer C_ACCEPTANCE_LOG             =   0,  // Width of acceptance counter for this SI-slot.\n   parameter integer C_ID_WIDTH                   = 1, \n   parameter integer C_THREAD_ID_WIDTH                  = 0,\n   parameter integer C_ADDR_WIDTH                 = 32, \n   parameter integer C_AMESG_WIDTH = 1,  // Used for AW or AR channel payload, depending on instantiation.\n   parameter integer C_RMESG_WIDTH = 1,  // Used for B or R channel payload, depending on instantiation.\n   parameter [C_ID_WIDTH-1:0]  C_BASE_ID                  = {C_ID_WIDTH{1'b0}},\n   parameter [C_ID_WIDTH-1:0]  C_HIGH_ID                  = {C_ID_WIDTH{1'b0}},\n   parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b1}}, \n   parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b0}}, \n   parameter integer C_SINGLE_THREAD             =   0,\n   parameter [C_NUM_M-1:0]    C_TARGET_QUAL                 = {C_NUM_M{1'b1}},\n   parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE                   = {C_NUM_M{32'h00000000}},\n   parameter integer C_RANGE_CHECK                    = 0,\n   parameter integer C_ADDR_DECODE           =0,\n   parameter [C_NUM_M*32-1:0] C_ERR_MODE            = {C_NUM_M{32'h00000000}},\n   parameter integer C_DEBUG                = 1\n   )\n  (\n   // Global Signals\n   input  wire                                                    ACLK,\n   input  wire                                                    ARESET,\n   // Slave Address Channel Interface Ports\n   input  wire [C_ID_WIDTH-1:0]           S_AID,\n   input  wire [C_ADDR_WIDTH-1:0]          S_AADDR,\n   input  wire [8-1:0]                    S_ALEN,\n   input  wire [3-1:0]                    S_ASIZE,\n   input  wire [2-1:0]                    S_ABURST,\n   input  wire [2-1:0]                    S_ALOCK,\n   input  wire [3-1:0]                    S_APROT,\n//   input  wire [4-1:0]                    S_AREGION,\n   input  wire [C_AMESG_WIDTH-1:0]         S_AMESG,\n   input  wire                             S_AVALID,\n   output wire                             S_AREADY,\n   // Master Address Channel Interface Ports\n   output wire [C_ID_WIDTH-1:0]          M_AID,\n   output wire [C_ADDR_WIDTH-1:0]          M_AADDR,\n   output  wire [8-1:0]                    M_ALEN,\n   output  wire [3-1:0]                    M_ASIZE,\n   output  wire [2-1:0]                    M_ALOCK,\n   output  wire [3-1:0]                    M_APROT,\n   output wire [4-1:0]                         M_AREGION,\n   output wire [C_AMESG_WIDTH-1:0]                         M_AMESG,\n   output wire [(C_NUM_M+1)-1:0]                         M_ATARGET_HOT,\n   output wire [(C_NUM_M_LOG+1)-1:0]                         M_ATARGET_ENC,\n   output wire [7:0]                         M_AERROR,\n   output wire                            M_AVALID_QUAL,\n   output wire                            M_AVALID,\n   input  wire                            M_AREADY,\n   // Slave Response Channel Interface Ports\n   output  wire [C_ID_WIDTH-1:0]           S_RID,\n   output  wire [C_RMESG_WIDTH-1:0]         S_RMESG,\n   output  wire                             S_RLAST,\n   output  wire                             S_RVALID,\n   input wire                             S_RREADY,\n   // Master Response Channel Interface Ports\n   input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0]          M_RID,\n   input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0]             M_RMESG,\n   input wire [(C_NUM_M+1)-1:0]                           M_RLAST,\n   input wire [(C_NUM_M+1)-1:0]                           M_RVALID,\n   output  wire [(C_NUM_M+1)-1:0]                           M_RREADY,\n   input wire [(C_NUM_M+1)-1:0]           M_RTARGET,  // Does response ID from each MI-slot target this SI slot?\n   input wire [8-1:0]                        DEBUG_A_TRANS_SEQ\n   );\n\n  localparam integer P_WRITE = 0;\n  localparam integer P_READ = 1;\n  localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1;\n  localparam [31:0]   P_AXILITE_ERRMODE = 32'h00000001;\n  localparam integer P_NONSECURE_BIT = 1; \n  localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1;\n  localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0);  // Mask of AxiLite MI-slots\n  localparam [1:0]   P_FIXED = 2'b00;\n  localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1);\n  localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1; \n  localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH;\n  localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE;\n  localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE);  // Mask of secure MI-slots\n  \n  // Ceiling of log2(x)\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  // AxiLite protocol flag vector      \n  function [C_NUM_M-1:0] f_m_axilite\n    (\n      input integer null_arg\n    );\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_M; mi=mi+1) begin\n        f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);\n      end\n    end\n  endfunction\n\n  // Convert Bit32 vector of range [0,1] to Bit1 vector on MI\n  function [C_NUM_M-1:0] f_bit32to1_mi\n    (input [C_NUM_M*32-1:0] vec32);\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_M; mi=mi+1) begin\n        f_bit32to1_mi[mi] = vec32[mi*32];\n      end\n    end\n  endfunction\n  \n  wire [C_NUM_M-1:0] target_mi_hot;\n  wire [P_NUM_M_LOG_M1-1:0] target_mi_enc;\n  wire [(C_NUM_M+1)-1:0] m_atarget_hot_i;\n  wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i;\n  wire match;\n  wire [3:0] target_region;\n  wire [3:0] m_aregion_i;\n  wire m_avalid_i;\n  wire s_aready_i;\n  wire any_error;\n  wire s_rvalid_i;\n  wire [C_ID_WIDTH-1:0] s_rid_i;\n  wire s_rlast_i;\n  wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg;\n  wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg;\n  wire [(C_NUM_M+1)-1:0] m_rvalid_qual;\n  wire [(C_NUM_M+1)-1:0] m_rready_arb;\n  wire [(C_NUM_M+1)-1:0] m_rready_i;\n  wire target_secure;\n  wire target_axilite;\n  wire m_avalid_qual_i;\n  wire [7:0] m_aerror_i;\n  \n  genvar gen_mi;\n  genvar gen_thread;\n    \n  generate\n    if (C_ADDR_DECODE) begin : gen_addr_decoder\n      axi_crossbar_v2_1_16_addr_decoder #\n        (\n          .C_FAMILY          (C_FAMILY),\n          .C_NUM_TARGETS     (C_NUM_M),\n          .C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1),\n          .C_NUM_RANGES      (C_NUM_ADDR_RANGES),\n          .C_ADDR_WIDTH      (C_ADDR_WIDTH),\n          .C_TARGET_ENC      (1),\n          .C_TARGET_HOT      (1),\n          .C_REGION_ENC      (1),\n          .C_BASE_ADDR      (C_BASE_ADDR),\n          .C_HIGH_ADDR      (C_HIGH_ADDR),\n          .C_TARGET_QUAL     (C_TARGET_QUAL),\n          .C_RESOLUTION      (2)\n        ) \n        addr_decoder_inst \n        (\n          .ADDR             (S_AADDR),        \n          .TARGET_HOT       (target_mi_hot),  \n          .TARGET_ENC       (target_mi_enc),  \n          .MATCH            (match),       \n          .REGION           (target_region)      \n        );\n    end else begin : gen_no_addr_decoder\n      assign target_mi_hot = 1;\n      assign target_mi_enc = 0;\n      assign match = 1'b1;\n      assign target_region = 4'b0000;\n    end\n  endgenerate\n  \n  assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);\n  assign target_axilite = |(target_mi_hot & P_M_AXILITE);\n\n  assign any_error = C_RANGE_CHECK && (m_aerror_i != 0);            // DECERR if error-detection enabled and any error condition.\n  assign m_aerror_i[0] = ~match;                                    // Invalid target address\n  assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation\n  assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) || \n    (S_ASIZE[1:0] == 2'b11) || (S_ASIZE[2] == 1'b1));               // AxiLite access violation\n  assign m_aerror_i[7:3] = 5'b00000;                                    // Reserved\n  assign M_ATARGET_HOT = m_atarget_hot_i;\n  assign m_atarget_hot_i = (any_error ? {1'b1, {C_NUM_M{1'b0}}} : {1'b0, target_mi_hot});\n  assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc);\n    \n  assign M_AVALID = m_avalid_i;\n  assign m_avalid_i = S_AVALID;\n  assign M_AVALID_QUAL = m_avalid_qual_i; \n  assign S_AREADY = s_aready_i;\n  assign s_aready_i = M_AREADY;\n  assign M_AERROR = m_aerror_i;\n  assign M_ATARGET_ENC = m_atarget_enc_i;\n  assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4'b0000;\n//  assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION;\n  assign M_AREGION = m_aregion_i;\n  assign M_AID = S_AID;\n  assign M_AADDR = S_AADDR;\n  assign M_ALEN = S_ALEN;\n  assign M_ASIZE = S_ASIZE;\n  assign M_ALOCK = S_ALOCK;\n  assign M_APROT = S_APROT;\n  assign M_AMESG = S_AMESG;\n  \n  assign S_RVALID = s_rvalid_i;\n  assign M_RREADY = m_rready_i;\n  assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH];\n  assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH];\n  assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1];\n  assign S_RID = s_rid_i;\n  assign S_RLAST = s_rlast_i;\n  assign m_rvalid_qual = M_RVALID & M_RTARGET;\n  assign m_rready_i = m_rready_arb & M_RTARGET;\n\n  generate\n    for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi\n      // Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.\n      assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = {\n               M_RLAST[gen_mi],\n               M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH],\n               M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH]\n               };\n    end  // gen_rmesg_mi\n\n    if (C_ACCEPTANCE == 1) begin : gen_single_issue\n      wire  cmd_push;\n      wire  cmd_pop;\n      reg  [(C_NUM_M+1)-1:0] active_target_hot = 0;\n      reg  [P_NUM_M_DE_LOG-1:0] active_target_enc = 0;\n      reg  accept_cnt = 1'b0;\n      reg  [8-1:0] debug_r_beat_cnt_i;\n      wire [8-1:0] debug_r_trans_seq_i;\n\n      assign cmd_push = M_AREADY;\n      assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i;  // Pop command queue if end of read burst\n      assign m_avalid_qual_i = ~accept_cnt | cmd_pop;  // Ready for arbitration if no outstanding transaction or transaction being completed\n\n      always @(posedge ACLK) begin \n        if (ARESET) begin\n          accept_cnt <= 1'b0;\n          active_target_enc <= 0;\n          active_target_hot <= 0;\n        end else begin\n          if (cmd_push) begin\n            active_target_enc <= m_atarget_enc_i;\n            active_target_hot <= m_atarget_hot_i;\n            accept_cnt <= 1'b1;\n          end else if (cmd_pop) begin\n            accept_cnt <= 1'b0;\n          end\n        end \n      end  // Clocked process\n        \n      assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};\n      assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);\n                 \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (C_FAMILY),\n         .C_RATIO       (C_NUM_M+1),\n         .C_SEL_WIDTH   (P_NUM_M_DE_LOG),\n         .C_DATA_WIDTH  (P_RMUX_MESG_WIDTH)\n        ) mux_resp_single_issue\n        (\n         .S   (active_target_enc),\n         .A   (mi_rmux_mesg),\n         .O   (si_rmux_mesg),\n         .OE  (1'b1)\n        ); \n        \n      if (C_DEBUG) begin : gen_debug_r_single_issue\n        // DEBUG READ BEAT COUNTER (only meaningful for R-channel)\n        always @(posedge ACLK) begin\n          if (ARESET) begin\n            debug_r_beat_cnt_i <= 0;\n          end else if (C_DIR == P_READ) begin\n            if (s_rvalid_i && S_RREADY) begin\n              if (s_rlast_i) begin\n                debug_r_beat_cnt_i <= 0;\n              end else begin\n                debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;\n              end\n            end\n          end else begin\n            debug_r_beat_cnt_i <= 0;            \n          end\n        end  // Clocked process\n        \n        // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO\n        axi_data_fifo_v2_1_14_axic_srl_fifo #\n          (\n           .C_FAMILY          (C_FAMILY),\n           .C_FIFO_WIDTH      (8),\n           .C_FIFO_DEPTH_LOG  (C_ACCEPTANCE_LOG+1),\n           .C_USE_FULL        (0)\n           )\n          debug_r_seq_fifo_single_issue\n            (\n             .ACLK    (ACLK),\n             .ARESET  (ARESET),\n             .S_MESG  (DEBUG_A_TRANS_SEQ),\n             .S_VALID (cmd_push),\n             .S_READY (),\n             .M_MESG  (debug_r_trans_seq_i),\n             .M_VALID (),\n             .M_READY (cmd_pop)\n            );\n            \n      end  // gen_debug_r\n      \n    end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread\n      wire  s_avalid_en;\n      wire  cmd_push;\n      wire  cmd_pop;\n      reg  [C_ID_WIDTH-1:0] active_id;\n      reg  [(C_NUM_M+1)-1:0] active_target_hot = 0;\n      reg  [P_NUM_M_DE_LOG-1:0] active_target_enc = 0;\n      reg  [4-1:0] active_region;\n      reg  [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt = 0;\n      reg  [8-1:0] debug_r_beat_cnt_i;\n      wire [8-1:0] debug_r_trans_seq_i;\n      wire accept_limit ;\n\n      // Implement single-region-per-ID cyclic dependency avoidance method.\n      assign s_avalid_en =  // This transaction is qualified to request arbitration if ...\n        (accept_cnt == 0) ||  // Either there are no outstanding transactions, or ...\n        (((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) &&  // the current transaction ID matches the previous, and ...\n        (active_target_enc == m_atarget_enc_i) &&  // all outstanding transactions are to the same target MI ...\n        (active_region == m_aregion_i));  // and to the same REGION.\n      \n      assign cmd_push = M_AREADY;\n      assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i;  // Pop command queue if end of read burst\n      assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop;  // Allow next push if a transaction is currently being completed\n      assign m_avalid_qual_i = s_avalid_en & ~accept_limit; \n      \n      always @(posedge ACLK) begin \n        if (ARESET) begin\n          accept_cnt <= 0;\n          active_id <= 0;\n          active_target_enc <= 0;\n          active_target_hot <= 0;\n          active_region <= 0;\n        end else begin\n          if (cmd_push) begin\n            active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];\n            active_target_enc <= m_atarget_enc_i;\n            active_target_hot <= m_atarget_hot_i;\n            active_region <= m_aregion_i;\n            if (~cmd_pop) begin\n              accept_cnt <= accept_cnt + 1;\n            end\n          end else begin\n            if (cmd_pop & (accept_cnt != 0)) begin\n              accept_cnt <= accept_cnt - 1;\n            end\n          end\n        end \n      end  // Clocked process\n        \n      assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};\n      assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);\n                 \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (C_FAMILY),\n         .C_RATIO       (C_NUM_M+1),\n         .C_SEL_WIDTH   (P_NUM_M_DE_LOG),\n         .C_DATA_WIDTH  (P_RMUX_MESG_WIDTH)\n        ) mux_resp_single_thread\n        (\n         .S   (active_target_enc),\n         .A   (mi_rmux_mesg),\n         .O   (si_rmux_mesg),\n         .OE  (1'b1)\n        ); \n        \n      if (C_DEBUG) begin : gen_debug_r_single_thread\n        // DEBUG READ BEAT COUNTER (only meaningful for R-channel)\n        always @(posedge ACLK) begin\n          if (ARESET) begin\n            debug_r_beat_cnt_i <= 0;\n          end else if (C_DIR == P_READ) begin\n            if (s_rvalid_i && S_RREADY) begin\n              if (s_rlast_i) begin\n                debug_r_beat_cnt_i <= 0;\n              end else begin\n                debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;\n              end\n            end\n          end else begin\n            debug_r_beat_cnt_i <= 0;            \n          end\n        end  // Clocked process\n        \n        // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO\n        axi_data_fifo_v2_1_14_axic_srl_fifo #\n          (\n           .C_FAMILY          (C_FAMILY),\n           .C_FIFO_WIDTH      (8),\n           .C_FIFO_DEPTH_LOG  (C_ACCEPTANCE_LOG+1),\n           .C_USE_FULL        (0)\n           )\n          debug_r_seq_fifo_single_thread\n            (\n             .ACLK    (ACLK),\n             .ARESET  (ARESET),\n             .S_MESG  (DEBUG_A_TRANS_SEQ),\n             .S_VALID (cmd_push),\n             .S_READY (),\n             .M_MESG  (debug_r_trans_seq_i),\n             .M_VALID (),\n             .M_READY (cmd_pop)\n            );\n            \n      end  // gen_debug_r\n      \n    end else begin : gen_multi_thread\n      wire [(P_NUM_M_DE_LOG)-1:0] resp_select;\n      reg  [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt = 0;\n      wire [P_NUM_THREADS-1:0] s_avalid_en;\n      wire [P_NUM_THREADS-1:0] thread_valid;\n      wire [P_NUM_THREADS-1:0] aid_match;\n      wire [P_NUM_THREADS-1:0] rid_match;\n      wire [P_NUM_THREADS-1:0] cmd_push;\n      wire [P_NUM_THREADS-1:0] cmd_pop;\n      wire [P_NUM_THREADS:0]   accum_push;\n      reg  [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id;\n      reg  [P_NUM_THREADS*8-1:0] active_target;\n      reg  [P_NUM_THREADS*8-1:0] active_region;\n      reg  [P_NUM_THREADS*8-1:0] active_cnt = 0;\n      reg  [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i;\n      wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i;\n      wire any_aid_match;\n      wire any_rid_match;\n      wire accept_limit;\n      wire any_push;\n      wire any_pop;\n        \n      axi_crossbar_v2_1_16_arbiter_resp #  // Multi-thread response arbiter\n        (\n         .C_FAMILY                (C_FAMILY),\n         .C_NUM_S                 (C_NUM_M+1),\n         .C_NUM_S_LOG             (P_NUM_M_DE_LOG),\n         .C_GRANT_ENC            (1),\n         .C_GRANT_HOT            (0)\n         )\n        arbiter_resp_inst\n          (\n           .ACLK                  (ACLK),\n           .ARESET                (ARESET),\n           .S_VALID               (m_rvalid_qual),\n           .S_READY               (m_rready_arb),\n           .M_GRANT_HOT           (),\n           .M_GRANT_ENC           (resp_select),\n           .M_VALID               (s_rvalid_i),\n           .M_READY               (S_RREADY)\n           );\n                 \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (C_FAMILY),\n         .C_RATIO       (C_NUM_M+1),\n         .C_SEL_WIDTH   (P_NUM_M_DE_LOG),\n         .C_DATA_WIDTH  (P_RMUX_MESG_WIDTH)\n        ) mux_resp_multi_thread\n        (\n         .S   (resp_select),\n         .A   (mi_rmux_mesg),\n         .O   (si_rmux_mesg),\n         .OE  (1'b1)\n        ); \n        \n      assign any_push = M_AREADY;\n      assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i;\n      assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop;  // Allow next push if a transaction is currently being completed\n        assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit;  // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads.\n        assign any_aid_match = |aid_match;\n        assign any_rid_match = |rid_match;\n        assign accum_push[0] = 1'b0;\n        \n        always @(posedge ACLK) begin\n          if (ARESET) begin\n            accept_cnt <= 0; \n          end else begin\n            if (any_push & ~any_pop) begin\n              accept_cnt <= accept_cnt + 1;\n          end else if (any_pop & ~any_push & (accept_cnt != 0)) begin\n              accept_cnt <= accept_cnt - 1;\n            end\n          end \n        end  // Clocked process\n          \n        for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop\n          assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0);\n          assign aid_match[gen_thread] =  // The currect thread is active for the requested transaction if\n            thread_valid[gen_thread] &&  // this thread slot is not vacant, and\n          ((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]);  // the requested ID matches the active ID for this thread.\n          assign s_avalid_en[gen_thread] =  // The current request is qualified against this thread slot if\n            (~aid_match[gen_thread]) ||  // This thread slot is not active for the requested ID, or\n            ((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) &&  // this outstanding transaction was to the same target and\n            (m_aregion_i == active_region[gen_thread*8+:4]));  // to the same region.\n          \n          // cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot.\n          assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread];\n          assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread]));\n          \n          // cmd_pop points to the position of the active thread that matches the current RID.\n        assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]);\n          assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread];\n        \n          always @(posedge ACLK) begin\n            if (ARESET) begin\n              active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0;\n              active_target[gen_thread*8+:8] <= 0;\n              active_region[gen_thread*8+:8] <= 0;\n              active_cnt[gen_thread*8+:8] <= 0; \n            end else begin\n              if (cmd_push[gen_thread]) begin\n              active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];\n                active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i;\n                active_region[gen_thread*8+:4] <= m_aregion_i;\n                if (~cmd_pop[gen_thread]) begin\n                  active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1;\n                end\n              end else if (cmd_pop[gen_thread]) begin\n                  active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1;\n              end\n            end \n          end  // Clocked process\n            \n        if (C_DEBUG) begin : gen_debug_r_multi_thread\n            // DEBUG READ BEAT COUNTER (only meaningful for R-channel)\n            always @(posedge ACLK) begin\n              if (ARESET) begin\n                debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;\n              end else if (C_DIR == P_READ) begin\n                if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin\n                  if (s_rlast_i) begin\n                    debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;\n                  end else begin\n                    debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1;\n                  end\n                end\n              end else begin\n                debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;            \n              end\n            end  // Clocked process\n            \n            // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO\n            axi_data_fifo_v2_1_14_axic_srl_fifo #\n              (\n               .C_FAMILY          (C_FAMILY),\n               .C_FIFO_WIDTH      (8),\n               .C_FIFO_DEPTH_LOG  (C_ACCEPTANCE_LOG+1),\n               .C_USE_FULL        (0)\n               )\n            debug_r_seq_fifo_multi_thread\n                (\n                 .ACLK    (ACLK),\n                 .ARESET  (ARESET),\n                 .S_MESG  (DEBUG_A_TRANS_SEQ),\n                 .S_VALID (cmd_push[gen_thread]),\n                 .S_READY (),\n                 .M_MESG  (debug_r_trans_seq_i[gen_thread*8+:8]),\n                 .M_VALID (),\n                 .M_READY (cmd_pop[gen_thread])\n                );\n        end  // gen_debug_r_multi_thread\n      end  // Next gen_thread_loop\n            \n    end  // thread control\n        \n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: AXI Splitter\n// Each transfer received on the AXI handshake slave port is replicated onto \n//   each of the master ports, and is completed back to the slave (S_READY) \n//   once all master ports have completed.\n//   \n// M_VALID is asserted combinatorially from S_VALID assertion.\n// Each M_VALID is masked off beginning the cycle after each M_READY is\n//   received (if S_READY remains low) until the cycle after both S_VALID\n//   and S_READY are asserted.\n// S_READY is asserted combinatorially when the last (or all) of the M_READY\n//   inputs have been received.\n// If all M_READYs are asserted when S_VALID is asserted, back-to-back\n//   handshakes can occur without bubble cycles.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   splitter\n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_16_splitter #\n  (\n   parameter integer C_NUM_M = 2  // Number of master ports = [2:16]\n   )\n  (\n   // Global Signals\n   input  wire                             ACLK,\n   input  wire                             ARESET,\n   // Slave  Port\n   input  wire                             S_VALID,\n   output wire                             S_READY,\n   // Master Ports\n   output wire [C_NUM_M-1:0]               M_VALID,\n   input  wire [C_NUM_M-1:0]               M_READY\n   );\n\n   reg  [C_NUM_M-1:0] m_ready_d = 0;\n   wire               s_ready_i;\n   wire [C_NUM_M-1:0] m_valid_i;\n\n   always @(posedge ACLK) begin\n      if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1'b0}};\n      else                    m_ready_d <= m_ready_d | (m_valid_i & M_READY);\n   end\n\n   assign s_ready_i = &(m_ready_d | M_READY);\n   assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d;\n   assign M_VALID = m_valid_i;\n   assign S_READY = s_ready_i;\n\nendmodule\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: wdata_mux.v\n//\n// Description: \n//   Contains MI-side write command queue.\n//   SI-slot index selected by AW arbiter is pushed onto queue when S_AVALID transfer is received.\n//   Queue is popped when WLAST data beat is transferred.\n//   W-channel input from SI-slot selected by queue output is transferred to MI-side output .\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    wdata_mux\n//      axic_reg_srl_fifo\n//      mux_enc\n//      \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_16_wdata_mux #\n  (\n   parameter         C_FAMILY       = \"none\", // FPGA Family.\n   parameter integer C_WMESG_WIDTH            =  1, // Width of W-channel payload.\n   parameter integer C_NUM_SLAVE_SLOTS     =  1, // Number of S_* ports.\n   parameter integer C_SELECT_WIDTH      =  1, // Width of ASELECT.\n   parameter integer C_FIFO_DEPTH_LOG     =  0 // Queue depth = 2**C_FIFO_DEPTH_LOG.\n   )\n  (\n   // System Signals\n   input  wire                                        ACLK,\n   input  wire                                        ARESET,\n   // Slave Data Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_WMESG_WIDTH-1:0]     S_WMESG,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                S_WLAST,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                S_WVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                S_WREADY,\n   // Master Data Ports\n   output wire [C_WMESG_WIDTH-1:0]                       M_WMESG,\n   output wire                                        M_WLAST,\n   output wire                                        M_WVALID,\n   input  wire                                        M_WREADY,\n   // Write Command Ports\n   input  wire [C_SELECT_WIDTH-1:0]                 S_ASELECT,  // SI-slot index from AW arbiter\n   input  wire                                        S_AVALID,\n   output wire                                        S_AREADY\n   );\n\n  localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5;  // Max depth = 32\n  \n  // Decode select input to 1-hot\n  function [C_NUM_SLAVE_SLOTS-1:0] f_decoder (\n      input [C_SELECT_WIDTH-1:0] sel\n    );\n    integer i;\n    begin\n      for (i=0; i<C_NUM_SLAVE_SLOTS; i=i+1) begin\n        f_decoder[i] = (sel == i);\n      end\n    end\n  endfunction\n\n  wire                                          m_valid_i;\n  wire                                          m_last_i;\n  wire [C_NUM_SLAVE_SLOTS-1:0]             m_select_hot;\n  wire [C_SELECT_WIDTH-1:0]                 m_select_enc;\n  wire                                          m_avalid;\n  wire                                          m_aready;\n  \n  generate\n    if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux\n      // SI-side write command queue\n      axi_data_fifo_v2_1_14_axic_reg_srl_fifo #\n        (\n         .C_FAMILY          (C_FAMILY),\n         .C_FIFO_WIDTH      (C_SELECT_WIDTH),\n         .C_FIFO_DEPTH_LOG  (P_FIFO_DEPTH_LOG),\n         .C_USE_FULL        (0)\n         )\n        wmux_aw_fifo\n          (\n           .ACLK    (ACLK),\n           .ARESET  (ARESET),\n           .S_MESG  (S_ASELECT),\n           .S_VALID (S_AVALID),\n           .S_READY (S_AREADY),\n           .M_MESG  (m_select_enc),\n           .M_VALID (m_avalid),\n           .M_READY (m_aready)\n           );\n    \n      assign m_select_hot = f_decoder(m_select_enc);\n      \n      // Instantiate MUX\n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_SLAVE_SLOTS),\n         .C_SEL_WIDTH   (C_SELECT_WIDTH),\n         .C_DATA_WIDTH  (C_WMESG_WIDTH)\n        ) mux_w \n        (\n         .S   (m_select_enc),\n         .A   (S_WMESG),\n         .O   (M_WMESG),\n         .OE  (1'b1)\n        ); \n        \n      assign m_last_i  = |(S_WLAST & m_select_hot);\n      assign m_valid_i = |(S_WVALID & m_select_hot);\n      \n      assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY;\n      assign M_WLAST = m_last_i;\n      assign M_WVALID = m_valid_i & m_avalid;\n      assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}};\n    end else begin : gen_no_wmux\n      assign S_AREADY = 1'b1;\n      assign M_WVALID = S_WVALID;\n      assign S_WREADY = M_WREADY;\n      assign M_WLAST = S_WLAST;\n      assign M_WMESG = S_WMESG;\n    end\n  endgenerate\n  \nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: wdata_router.v\n//\n// Description: \n//   Contains SI-side write command queue.\n//   Target MI-slot index is pushed onto queue when S_AVALID transfer is received.\n//   Queue is popped when WLAST data beat is transferred.\n//   W-channel input is transferred to MI-slot output selected by queue output.\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    wdata_router\n//      axic_reg_srl_fifo\n//      \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_16_wdata_router #\n  (\n   parameter         C_FAMILY       = \"none\", // FPGA Family.\n   parameter integer C_WMESG_WIDTH          = 1, // Width of all data signals\n   parameter integer C_NUM_MASTER_SLOTS     = 1, // Number of M_* ports.\n   parameter integer C_SELECT_WIDTH     =  1, // Width of S_ASELECT.\n   parameter integer C_FIFO_DEPTH_LOG     =  0 // Queue depth = 2**C_FIFO_DEPTH_LOG.\n   )\n  (\n   // System Signals\n   input  wire                                        ACLK,\n   input  wire                                        ARESET,\n   // Slave Data Ports\n   input  wire [C_WMESG_WIDTH-1:0]                    S_WMESG,\n   input  wire                                        S_WLAST,\n   input  wire                                        S_WVALID,\n   output wire                                        S_WREADY,\n   // Master Data Ports\n   output wire [C_WMESG_WIDTH-1:0]                    M_WMESG,  // Broadcast to all MI-slots\n   output wire                                        M_WLAST,  // Broadcast to all MI-slots\n   output wire [C_NUM_MASTER_SLOTS-1:0]               M_WVALID,  // Per MI-slot\n   input  wire [C_NUM_MASTER_SLOTS-1:0]               M_WREADY,  // Per MI-slot\n   // Address Arbiter Ports\n   input  wire [C_SELECT_WIDTH-1:0]                   S_ASELECT,  // Target MI-slot index from SI-side AW command\n   input  wire                                        S_AVALID,\n   output wire                                        S_AREADY\n   );\n\n  localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5;  // Max depth = 32\n\n  // Decode select input to 1-hot\n  function [C_NUM_MASTER_SLOTS-1:0] f_decoder (\n      input [C_SELECT_WIDTH-1:0] sel\n    );\n    integer i;\n    begin\n      for (i=0; i<C_NUM_MASTER_SLOTS; i=i+1) begin\n        f_decoder[i] = (sel == i);\n      end\n    end\n  endfunction\n\n  //---------------------------------------------------------------------------\n  // Internal signal declarations\n  //---------------------------------------------------------------------------\n  wire [C_NUM_MASTER_SLOTS-1:0]             m_select_hot;\n  wire [C_SELECT_WIDTH-1:0]                 m_select_enc;\n  wire                                          m_avalid;\n  wire                                          m_aready;\n  \n  //---------------------------------------------------------------------------\n  // Router\n  //---------------------------------------------------------------------------\n\n  // SI-side write command queue\n  axi_data_fifo_v2_1_14_axic_reg_srl_fifo #\n    (\n     .C_FAMILY          (C_FAMILY),\n     .C_FIFO_WIDTH      (C_SELECT_WIDTH),\n     .C_FIFO_DEPTH_LOG  (P_FIFO_DEPTH_LOG),\n     .C_USE_FULL        (1)\n     )\n    wrouter_aw_fifo\n      (\n       .ACLK    (ACLK),\n       .ARESET  (ARESET),\n       .S_MESG  (S_ASELECT),\n       .S_VALID (S_AVALID),\n       .S_READY (S_AREADY),\n       .M_MESG  (m_select_enc),\n       .M_VALID (m_avalid),\n       .M_READY (m_aready)\n       );\n\n  assign m_select_hot = f_decoder(m_select_enc);\n  \n  // W-channel payload and LAST are broadcast to all MI-slot's W-mux\n  assign M_WMESG   = S_WMESG;\n  assign M_WLAST =   S_WLAST;\n  \n  // Assert m_aready when last beat acknowledged by slave\n  assign m_aready = m_avalid & S_WVALID & S_WLAST & (|(M_WREADY & m_select_hot));\n\n  // M_WVALID is generated per MI-slot (including error handler at slot C_NUM_MASTER_SLOTS).\n  // The slot selected by the head of the queue (m_select_enc) is enabled.\n  assign M_WVALID = {C_NUM_MASTER_SLOTS{S_WVALID & m_avalid}} & m_select_hot;\n\n  // S_WREADY is muxed from the MI slot selected by the head of the queue (m_select_enc).\n  assign S_WREADY = m_avalid & (|(M_WREADY & m_select_hot));\n  \nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2011-2014 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: axi_crossbar.v\n//-----------------------------------------------------------------------------\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_16_axi_crossbar # (\n   parameter         C_FAMILY                         = \"rtl\", \n                       // FPGA Base Family. Current version: virtex6 or spartan6.\n   parameter integer C_NUM_SLAVE_SLOTS                = 1, \n                       // Number of Slave Interface (SI) slots for connecting \n                       // to master IP. Range: 1-16.\n   parameter integer C_NUM_MASTER_SLOTS               = 2, \n                       // Number of Master Interface (MI) slots for connecting \n                       // to slave IP. Range: 1-16.                       \n   parameter integer C_AXI_ID_WIDTH                   = 1, \n                       // Width of ID signals propagated by the Interconnect.\n                       // Width of ID signals produced on all MI slots.\n                       // Range: 1-32.\n   parameter integer C_AXI_ADDR_WIDTH                 = 32, \n                       // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and \n                       // m_axi_araddr for all SI/MI slots.\n                       // Range: 1-64.\n   parameter integer C_AXI_DATA_WIDTH        = 32, \n                       // Data width of the internal interconnect write and read \n                       // data paths.\n                       // Range: 32, 64, 128, 256, 512, 1024.\n   parameter integer C_AXI_PROTOCOL                 = 0, \n                       // 0 = \"AXI4\",\n                       // 1 = \"AXI3\", \n                       // 2 = \"AXI4LITE\"\n                       //   Propagate WID only when C_AXI_PROTOCOL = 1.\n   parameter integer C_NUM_ADDR_RANGES = 1,\n                       // Number of BASE/HIGH_ADDR pairs per MI slot.\n                       // Range: 1-16.\n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = 128'h00000000001000000000000000000000,\n                       // Base address of each range of each MI slot. \n                       // For unused ranges, set C_M_AXI_BASE_ADDR[mm*aa*64 +: C_AXI_ADDR_WIDTH] = {C_AXI_ADDR_WIDTH{1'b1}}. \n                       //   (Bit positions above C_AXI_ADDR_WIDTH are ignored.)\n                       // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit64}}.\n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*32-1:0] C_M_AXI_ADDR_WIDTH = 64'H0000000c0000000c, \n                       // Number of low-order address bits that are used to select locations within each address range of each MI slot.\n                       // The High address of each range is derived as BASE_ADDR + 2**C_M_AXI_ADDR_WIDTH -1.\n                       // For used address ranges, C_M_AXI_ADDR_WIDTH must be > 0.\n                       // For unused ranges, set C_M_AXI_ADDR_WIDTH to 32'h00000000.\n                       // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit32}}.\n                       // Range: 0 - C_AXI_ADDR_WIDTH.\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_BASE_ID = 32'h00000000,\n                       // Base ID of each SI slot. \n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 0 to 2**C_AXI_ID_WIDTH-1.\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = 32'h00000000,\n                       // Number of low-order ID bits a connected master may vary to select a transaction thread.\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 0 - C_AXI_ID_WIDTH.\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS      = 0,\n                       // 1 = Propagate all USER signals, 0 = Dont propagate.\n   parameter integer C_AXI_AWUSER_WIDTH               = 1,\n                       // Width of AWUSER signals for all SI slots and MI slots. \n                       // Range: 1-1024.\n   parameter integer C_AXI_ARUSER_WIDTH               = 1,\n                       // Width of ARUSER signals for all SI slots and MI slots. \n                       // Range: 1-1024.\n   parameter integer C_AXI_WUSER_WIDTH                = 1,\n                       // Width of WUSER signals for all SI slots and MI slots. \n                       // Range: 1-1024.\n   parameter integer C_AXI_RUSER_WIDTH                = 1,\n                       // Width of RUSER signals for all SI slots and MI slots. \n                       // Range: 1-1024.\n   parameter integer C_AXI_BUSER_WIDTH                = 1,\n                       // Width of BUSER signals for all SI slots and MI slots. \n                       // Range: 1-1024.\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,\n                       // Multi-pathway write connectivity from each SI slot (N) to each \n                       // MI slot (M):\n                       // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)\n                       // Format: C_NUM_MASTER_SLOTS{Bit32}; \n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,\n                       // Multi-pathway read connectivity from each SI slot (N) to each \n                       // MI slot (M):\n                       // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)\n                       // Format: C_NUM_MASTER_SLOTS{Bit32}; \n   parameter integer C_R_REGISTER               = 0,\n                       // Insert register slice on R channel in the crossbar. (Valid only for SASD)\n                       // Range: Reg-slice type (0-8).\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD                 = 32'h00000000, \n                       // 0 = Implement separate command queues per ID thread.\n                       // 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD)\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32}; \n                       // Range: 0, 1\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE         = 32'H00000002,\n                       // Maximum number of active write transactions that each SI \n                       // slot can accept. (Valid only for SAMD)\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32}; \n                       // Range: 1-32.\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE          = 32'H00000002,\n                       // Maximum number of active read transactions that each SI \n                       // slot can accept. (Valid only for SAMD)\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 1-32.\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING            = 64'H0000000400000004,\n                       // Maximum number of data-active write transactions that \n                       // each MI slot can generate at any one time. (Valid only for SAMD)\n                       // Format: C_NUM_MASTER_SLOTS{Bit32};\n                       // Range: 1-32.\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING            = 64'H0000000400000004,\n                       // Maximum number of active read transactions that \n                       // each MI slot can generate at any one time. (Valid only for SAMD)\n                       // Format: C_NUM_MASTER_SLOTS{Bit32};\n                       // Range: 1-32.\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY             = 32'h00000000,\n                       // Arbitration priority among each SI slot. \n                       // Higher values indicate higher priority.\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 0-15.\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE                   = 32'h00000000,\n                       // Indicates whether each MI slot connects to a secure slave \n                       // (allows only TrustZone secure access).\n                       // Format: C_NUM_MASTER_SLOTS{Bit32}.\n                       // Range: 0, 1\n   parameter integer C_CONNECTIVITY_MODE = 1\n                       // 0 = Shared-Address Shared-Data (SASD).\n                       // 1 = Shared-Address Multi-Data (SAMD).\n                       // Default 1 (on) for simulation; default 0 (off) for implementation.\n)\n(\n   // Global Signals\n   input  wire                                                    aclk,\n   input  wire                                                    aresetn,\n   // Slave Interface Write Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_awid,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           s_axi_awaddr,\n   input  wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          s_axi_awsize,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          s_axi_awburst,\n   input  wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_awcache,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          s_axi_awprot,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_awregion,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_awqos,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0]         s_axi_awuser,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_awvalid,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_awready,\n   // Slave Interface Write Data Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_wid,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]           s_axi_wdata,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0]         s_axi_wstrb,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_wlast,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0]          s_axi_wuser,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_wvalid,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_wready,\n   // Slave Interface Write Response Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_bid,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          s_axi_bresp,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0]          s_axi_buser,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_bvalid,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_bready,\n   // Slave Interface Read Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_arid,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           s_axi_araddr,\n   input  wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          s_axi_arsize,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          s_axi_arburst,\n   input  wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_arcache,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          s_axi_arprot,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_arregion,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_arqos,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0]         s_axi_aruser,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_arvalid,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_arready,\n   // Slave Interface Read Data Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_rid,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]           s_axi_rdata,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          s_axi_rresp,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_rlast,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0]          s_axi_ruser,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_rvalid,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_rready,\n   // Master Interface Write Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_awid,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          m_axi_awaddr,\n   output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         m_axi_awsize,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         m_axi_awburst,\n   output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_awcache,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         m_axi_awprot,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_awregion,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_awqos,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0]        m_axi_awuser,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_awvalid,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_awready,\n   // Master Interface Write Data Ports\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_wid,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]          m_axi_wdata,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0]        m_axi_wstrb,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_wlast,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0]         m_axi_wuser,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_wvalid,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_wready,\n   // Master Interface Write Response Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_bid,\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         m_axi_bresp,\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0]         m_axi_buser,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_bvalid,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_bready,\n   // Master Interface Read Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_arid,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          m_axi_araddr,\n   output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         m_axi_arsize,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         m_axi_arburst,\n   output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_arcache,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         m_axi_arprot,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_arregion,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_arqos,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0]        m_axi_aruser,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_arvalid,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_arready,\n   // Master Interface Read Data Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_rid,\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]          m_axi_rdata,\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         m_axi_rresp,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_rlast,\n   input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0]          m_axi_ruser,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_rvalid,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_rready\n);\n\n  localparam [64:0] P_ONES = {65{1'b1}};\n  localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_BASE_ID = f_base_id(0);\n  localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_HIGH_ID = f_high_id(0);\n  localparam integer  P_AXI4 = 0;\n  localparam integer  P_AXI3 = 1;\n  localparam integer  P_AXILITE = 2;\n  localparam [2:0]   P_AXILITE_SIZE = 3'b010;\n  localparam [1:0]   P_INCR = 2'b01;\n  localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_WRITE = f_m_supports_write(0);\n  localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_READ = f_m_supports_read(0);\n  localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_WRITE = f_s_supports_write(0);\n  localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_READ = f_s_supports_read(0);\n  localparam integer C_DEBUG              = 1;\n  localparam integer P_RANGE_CHECK                    = 1;\n                       // 1 (non-zero) = Detect and issue DECERR on the following conditions:\n                       //   a. address range mismatch (no valid MI slot)\n                       //   b. Burst or >32-bit transfer to AxiLite slave\n                       //   c. TrustZone access violation\n                       //   d. R/W direction unsupported by target\n                       // 0 = Pass all transactions (no DECERR):\n                       //   a. Omit DECERR detection and response logic\n                       //   b. Omit address decoder and propagate s_axi_a*REGION to m_axi_a*REGION\n                       //      when C_NUM_MASTER_SLOTS=1 and C_NUM_ADDR_RANGES=1.\n                       //   c. Unpredictable target MI-slot if address mismatch and >1 MI-slot\n                       //   d. Transaction corruption if any burst or >32-bit transfer to AxiLite slave\n                       // Illegal combination: P_RANGE_CHECK = 0 && C_M_AXI_SECURE != 0.\n  localparam integer P_ADDR_DECODE = ((P_RANGE_CHECK == 1) || (C_NUM_MASTER_SLOTS > 1) || (C_NUM_ADDR_RANGES > 1)) ? 1 : 0;  // Always 1\n  localparam [C_NUM_MASTER_SLOTS*32-1:0] P_M_AXI_ERR_MODE            = {C_NUM_MASTER_SLOTS{32'h00000000}};\n                       // Transaction error detection (per MI-slot)\n                       // 0 = None; 1 = AXI4Lite burst violation\n                       // Format: C_NUM_MASTER_SLOTS{Bit32};\n  localparam integer P_LEN = (C_AXI_PROTOCOL == P_AXI3) ? 4 : 8;\n  localparam integer P_LOCK = (C_AXI_PROTOCOL == P_AXI3) ? 2 : 1;\n  localparam P_FAMILY = ((C_FAMILY == \"virtex7\") || (C_FAMILY == \"kintex7\") || (C_FAMILY == \"artix7\") || (C_FAMILY == \"zynq\")) ? C_FAMILY : \"rtl\";\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  // Widths of all write issuance counters implemented in axi_crossbar_v2_1_16_crossbar (before counter carry-out bit)\n  function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_write_issue_width_vec\n    (input null_arg);\n    integer mi;\n    reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;\n    begin\n      result = 0;\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_WRITE_ISSUING[mi*32+:32]);\n      end\n      result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;\n      f_write_issue_width_vec = result;\n    end\n  endfunction\n\n  // Widths of all read issuance counters implemented in axi_crossbar_v2_1_16_crossbar (before counter carry-out bit)\n  function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_read_issue_width_vec\n    (input null_arg);\n    integer mi;\n    reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;\n    begin\n      result = 0;\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_READ_ISSUING[mi*32+:32]);\n      end\n      result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;\n      f_read_issue_width_vec = result;\n    end\n  endfunction\n\n  // Widths of all write acceptance counters implemented in axi_crossbar_v2_1_16_crossbar (before counter carry-out bit)\n  function [C_NUM_SLAVE_SLOTS*32-1:0] f_write_accept_width_vec\n    (input null_arg);\n    integer si;\n    reg [C_NUM_SLAVE_SLOTS*32-1:0] result;\n    begin\n      result = 0;\n      for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin\n        result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_WRITE_ACCEPTANCE[si*32+:32]);\n      end\n      f_write_accept_width_vec = result;\n    end\n  endfunction\n\n  // Widths of all read acceptance counters implemented in axi_crossbar_v2_1_16_crossbar (before counter carry-out bit)\n  function [C_NUM_SLAVE_SLOTS*32-1:0] f_read_accept_width_vec\n    (input null_arg);\n    integer si;\n    reg [C_NUM_SLAVE_SLOTS*32-1:0] result;\n    begin\n      result = 0;\n      for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin\n        result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_READ_ACCEPTANCE[si*32+:32]);\n      end\n      f_read_accept_width_vec = result;\n    end\n  endfunction\n\n  // Convert C_S_AXI_BASE_ID vector from Bit32 to Bit64 format\n  function [C_NUM_SLAVE_SLOTS*64-1:0] f_base_id\n    (input null_arg);\n    integer si;\n    reg [C_NUM_SLAVE_SLOTS*64-1:0] result;\n    begin\n      result = 0;\n      for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin\n        result[si*64+:C_AXI_ID_WIDTH] = C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH];\n      end\n      f_base_id = result;\n    end\n  endfunction\n\n  // Construct P_S_HIGH_ID vector\n  function [C_NUM_SLAVE_SLOTS*64-1:0] f_high_id\n    (input null_arg);\n    integer si;\n    reg [C_NUM_SLAVE_SLOTS*64-1:0] result;\n    begin\n      result = 0;\n      for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin\n        result[si*64+:C_AXI_ID_WIDTH] = (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :\n          ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :\n          (C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));\n      end\n      f_high_id = result;\n    end\n  endfunction\n\n  // Construct P_M_HIGH_ADDR vector\n  function [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] f_high_addr\n    (input null_arg);\n    integer ar;\n    reg [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] result;\n    begin\n      result = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}};\n      for (ar=0; ar<C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES; ar=ar+1) begin\n        result[ar*64+:C_AXI_ADDR_WIDTH] = (C_M_AXI_ADDR_WIDTH[ar*32+:32] == 0) ? 64'h00000000_00000000 : \n          ({1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:31]} >= C_AXI_ADDR_WIDTH) ? {C_AXI_ADDR_WIDTH{1'b1}} :\n          (C_M_AXI_BASE_ADDR[ar*64+:C_AXI_ADDR_WIDTH] | ~(P_ONES << {1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:7]}));\n      end\n      f_high_addr = result;\n    end\n  endfunction\n\n  // Generate a mask of valid ID bits for a given SI slot.\n  function [C_AXI_ID_WIDTH-1:0] f_thread_id_mask\n    (input integer si);\n    begin\n      f_thread_id_mask = \n        (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? {C_AXI_ID_WIDTH{1'b0}} : \n        ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :\n        ({C_AXI_ID_WIDTH{1'b0}} | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));\n      end\n  endfunction\n\n  // Isolate thread bits of input S_ID and add to BASE_ID to form MI-side ID value\n  //   only for end-point SI-slots\n  function [C_AXI_ID_WIDTH-1:0] f_extend_ID (\n    input [C_AXI_ID_WIDTH-1:0] s_id,\n    input integer si\n    );\n    begin\n      f_extend_ID = \n        (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] : \n        ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? s_id :\n        (C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | (s_id &  ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]})));\n    end\n  endfunction\n\n  // Bit vector of SI slots with at least one write connection.\n  function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_write\n    (input null_arg);\n    integer mi;\n    reg [C_NUM_SLAVE_SLOTS-1:0] result;\n    begin\n      result = {C_NUM_SLAVE_SLOTS{1'b0}};\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        result = result | C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];\n      end\n      f_s_supports_write = result;\n    end\n  endfunction\n\n  // Bit vector of SI slots with at least one read connection.\n  function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_read\n    (input null_arg);\n    integer mi;\n    reg [C_NUM_SLAVE_SLOTS-1:0] result;\n    begin\n      result = {C_NUM_SLAVE_SLOTS{1'b0}};\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        result = result | C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];\n      end\n      f_s_supports_read = result;\n    end\n  endfunction\n\n  // Bit vector of MI slots with at least one write connection.\n  function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_write\n    (input null_arg);\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        f_m_supports_write[mi] = (|C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);\n      end\n    end\n  endfunction\n\n  // Bit vector of MI slots with at least one read connection.\n  function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_read\n    (input null_arg);\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        f_m_supports_read[mi] = (|C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);\n      end\n    end\n  endfunction\n\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_awid            ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]        si_cb_awaddr          ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                       si_cb_awlen           ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                       si_cb_awsize          ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_awburst         ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_awlock          ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_awcache         ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                       si_cb_awprot          ;\n//  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_awregion        ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_awqos           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0]      si_cb_awuser          ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_awvalid         ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_awready         ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_wid            ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]        si_cb_wdata           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0]      si_cb_wstrb           ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_wlast           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0]       si_cb_wuser           ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_wvalid          ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_wready          ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_bid             ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_bresp           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0]       si_cb_buser           ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_bvalid          ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_bready          ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_arid            ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]        si_cb_araddr          ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                       si_cb_arlen           ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                       si_cb_arsize          ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_arburst         ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_arlock          ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_arcache         ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                       si_cb_arprot          ;\n//  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_arregion        ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_arqos           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0]      si_cb_aruser          ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_arvalid         ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_arready         ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_rid             ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]        si_cb_rdata           ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_rresp           ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_rlast           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0]       si_cb_ruser           ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_rvalid          ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_rready          ;\n\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_awid            ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]       cb_mi_awaddr          ;\n  wire [C_NUM_MASTER_SLOTS*8-1:0]                      cb_mi_awlen           ;\n  wire [C_NUM_MASTER_SLOTS*3-1:0]                      cb_mi_awsize          ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_awburst         ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_awlock          ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_awcache         ;\n  wire [C_NUM_MASTER_SLOTS*3-1:0]                      cb_mi_awprot          ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_awregion        ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_awqos           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0]     cb_mi_awuser          ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_awvalid         ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_awready         ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_wid             ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]       cb_mi_wdata           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0]     cb_mi_wstrb           ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_wlast           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0]      cb_mi_wuser           ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_wvalid          ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_wready          ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_bid             ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_bresp           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0]      cb_mi_buser           ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_bvalid          ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_bready          ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_arid            ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]       cb_mi_araddr          ;\n  wire [C_NUM_MASTER_SLOTS*8-1:0]                      cb_mi_arlen           ;\n  wire [C_NUM_MASTER_SLOTS*3-1:0]                      cb_mi_arsize          ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_arburst         ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_arlock          ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_arcache         ;\n  wire [C_NUM_MASTER_SLOTS*3-1:0]                      cb_mi_arprot          ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_arregion        ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_arqos           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0]     cb_mi_aruser          ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_arvalid         ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_arready         ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_rid             ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]       cb_mi_rdata           ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_rresp           ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_rlast           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0]      cb_mi_ruser           ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_rvalid          ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_rready          ;\n  \n  genvar slot;\n\ngenerate\n    for (slot=0;slot<C_NUM_SLAVE_SLOTS;slot=slot+1) begin : gen_si_tieoff\n      assign si_cb_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? (s_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))              : 0 ;\n      assign si_cb_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       : 0 ;\n      assign si_cb_awlen[slot*8+:8]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awlen[slot*P_LEN+:P_LEN] : 0 ;\n      assign si_cb_awsize[slot*3+:3]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awsize[slot*3+:3]                                                     : P_AXILITE_SIZE ;\n      assign si_cb_awburst[slot*2+:2]                                                    = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awburst[slot*2+:2]                                                    : P_INCR ;\n      assign si_cb_awlock[slot*2+:2]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? {1'b0, s_axi_awlock[slot*P_LOCK+:1]}                                             : 0 ;\n      assign si_cb_awcache[slot*4+:4]                                                    = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awcache[slot*4+:4]                                                    : 0 ;\n      assign si_cb_awprot[slot*3+:3]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_awprot[slot*3+:3]                                                     : 0 ;\n      assign si_cb_awqos[slot*4+:4]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awqos[slot*4+:4]                                                      : 0 ;\n//      assign si_cb_awregion[slot*4+:4]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4)                                ) ? s_axi_awregion[slot*4+:4]                                                      : 0 ;\n      assign si_cb_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH]                   = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH]                   : 0 ;\n      assign si_cb_awvalid[slot*1+:1]                                                    = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_awvalid[slot*1+:1]                                                    : 0 ;\n      assign si_cb_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI3)                                   ) ? (s_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))   : 0 ;\n      assign si_cb_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]                        = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]     : 0 ;\n      assign si_cb_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]                    = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;\n      assign si_cb_wlast[slot*1+:1]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_wlast[slot*1+:1]                                                      : 1'b1 ;\n      assign si_cb_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]                      : 0 ;\n      assign si_cb_wvalid[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_wvalid[slot*1+:1]                                                     : 0 ;\n      assign si_cb_bready[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_bready[slot*1+:1]                                                     : 0 ;\n      assign si_cb_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? (s_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))              : 0 ;\n      assign si_cb_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? s_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       : 0 ;\n      assign si_cb_arlen[slot*8+:8]                                                      = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_arlen[slot*P_LEN+:P_LEN] : 0 ;\n      assign si_cb_arsize[slot*3+:3]                                                     = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_arsize[slot*3+:3]                                                     : P_AXILITE_SIZE ;\n      assign si_cb_arburst[slot*2+:2]                                                    = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_arburst[slot*2+:2]                                                    : P_INCR ;\n      assign si_cb_arlock[slot*2+:2]                                                     = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? {1'b0, s_axi_arlock[slot*P_LOCK+:1]}                                             : 0 ;\n      assign si_cb_arcache[slot*4+:4]                                                    = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                  ) ? s_axi_arcache[slot*4+:4]                                                    : 0 ;\n      assign si_cb_arprot[slot*3+:3]                                                     = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? s_axi_arprot[slot*3+:3]                                                     : 0 ;\n      assign si_cb_arqos[slot*4+:4]                                                      = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_arqos[slot*4+:4]                                                      : 0 ;\n//      assign si_cb_arregion[slot*4+:4]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4)                                ) ? s_axi_arregion[slot*4+:4]                                                      : 0 ;\n      assign si_cb_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH]                   = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH]                   : 0 ;\n      assign si_cb_arvalid[slot*1+:1]                                                    = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? s_axi_arvalid[slot*1+:1]                                                    : 0 ;\n      assign si_cb_rready[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? s_axi_rready[slot*1+:1]                                                     : 0 ;                                       \n\n      assign s_axi_awready[slot*1+:1]                                                    = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? si_cb_awready[slot*1+:1]                                                    : 0 ;\n      assign s_axi_wready[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? si_cb_wready[slot*1+:1]                                                     : 0 ;\n      assign s_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? (si_cb_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))               : 0 ;\n      assign s_axi_bresp[slot*2+:2]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? si_cb_bresp[slot*2+:2]                                                      : 0 ;\n      assign s_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                      : 0 ;\n      assign s_axi_bvalid[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? si_cb_bvalid[slot*1+:1]                                                     : 0 ;\n      assign s_axi_arready[slot*1+:1]                                                    = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? si_cb_arready[slot*1+:1]                                                    : 0 ;\n      assign s_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? (si_cb_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))               : 0 ;\n      assign s_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]                        = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? si_cb_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]     : 0 ;\n      assign s_axi_rresp[slot*2+:2]                                                      = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? si_cb_rresp[slot*2+:2]                                                      : 0 ;\n      assign s_axi_rlast[slot*1+:1]                                                      = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? si_cb_rlast[slot*1+:1]                                                      : 0 ;\n      assign s_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                      = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                      : 0 ;\n      assign s_axi_rvalid[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? si_cb_rvalid[slot*1+:1]                                                     : 0 ;\n    end  // gen_si_tieoff\n\n    for (slot=0;slot<C_NUM_MASTER_SLOTS;slot=slot+1) begin : gen_mi_tieoff\n      assign m_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             : 0 ;\n      assign m_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       : 0 ;\n      assign m_axi_awlen[slot*P_LEN+:P_LEN]                                              = (~P_M_AXI_SUPPORTS_WRITE[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4                             ) ? cb_mi_awlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_awlen[slot*8+:4] : 0 ;\n      assign m_axi_awsize[slot*3+:3]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awsize[slot*3+:3]                                                     : 0 ;\n      assign m_axi_awburst[slot*2+:2]                                                    = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awburst[slot*2+:2]                                                    : 0 ;\n      assign m_axi_awlock[slot*P_LOCK+:P_LOCK]                                           = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awlock[slot*2+:1]                                                     : 0 ;\n      assign m_axi_awcache[slot*4+:4]                                                    = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awcache[slot*4+:4]                                                    : 0 ;\n      assign m_axi_awprot[slot*3+:3]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_awprot[slot*3+:3]                                                     : 0 ;\n      assign m_axi_awregion[slot*4+:4]                                                   = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL==P_AXI4)                                 ) ? cb_mi_awregion[slot*4+:4]                                                   : 0 ;\n      assign m_axi_awqos[slot*4+:4]                                                      = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awqos[slot*4+:4]                                                      : 0 ;\n      assign m_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH]                   = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH]                   : 0 ;\n      assign m_axi_awvalid[slot*1+:1]                                                    = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_awvalid[slot*1+:1]                                                    : 0 ;\n      assign m_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              : 0 ;\n      assign m_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]                        = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]     : 0 ;\n      assign m_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]                    = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;\n      assign m_axi_wlast[slot*1+:1]                                                      = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_wlast[slot*1+:1]                                                      : 0 ;\n      assign m_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]                      = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]                      : 0 ;\n      assign m_axi_wvalid[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_wvalid[slot*1+:1]                                                     : 0 ;\n      assign m_axi_bready[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_bready[slot*1+:1]                                                     : 0 ;\n      assign m_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                            : 0 ;\n      assign m_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? cb_mi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       : 0 ;\n      assign m_axi_arlen[slot*P_LEN+:P_LEN]                                              = (~P_M_AXI_SUPPORTS_READ[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4                             ) ? cb_mi_arlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_arlen[slot*8+:4] : 0 ;\n      assign m_axi_arsize[slot*3+:3]                                                     = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arsize[slot*3+:3]                                                     : 0 ;\n      assign m_axi_arburst[slot*2+:2]                                                    = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arburst[slot*2+:2]                                                    : 0 ;\n      assign m_axi_arlock[slot*P_LOCK+:P_LOCK]                                           = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arlock[slot*2+:1]                                                     : 0 ;\n      assign m_axi_arcache[slot*4+:4]                                                    = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arcache[slot*4+:4]                                                    : 0 ;\n      assign m_axi_arprot[slot*3+:3]                                                     = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? cb_mi_arprot[slot*3+:3]                                                     : 0 ;\n      assign m_axi_arregion[slot*4+:4]                                                   = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL==P_AXI4)                                 ) ? cb_mi_arregion[slot*4+:4]                                                   : 0 ;\n      assign m_axi_arqos[slot*4+:4]                                                      = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arqos[slot*4+:4]                                                      : 0 ;\n      assign m_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH]                   = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH]                   : 0 ;\n      assign m_axi_arvalid[slot*1+:1]                                                    = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? cb_mi_arvalid[slot*1+:1]                                                    : 0 ;\n      assign m_axi_rready[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? cb_mi_rready[slot*1+:1]                                                     : 0 ;\n\n      assign cb_mi_awready[slot*1+:1]                                                    = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? m_axi_awready[slot*1+:1]                                                    : 0 ;\n      assign cb_mi_wready[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? m_axi_wready[slot*1+:1]                                                     : 0 ;\n      assign cb_mi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? m_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              : 0 ;\n      assign cb_mi_bresp[slot*2+:2]                                                      = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? m_axi_bresp[slot*2+:2]                                                      : 0 ;\n      assign cb_mi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                      = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                      : 0 ;\n      assign cb_mi_bvalid[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? m_axi_bvalid[slot*1+:1]                                                     : 0 ;\n      assign cb_mi_arready[slot*1+:1]                                                    = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? m_axi_arready[slot*1+:1]                                                    : 0 ;\n      assign cb_mi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? m_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              : 0 ;\n      assign cb_mi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]                        = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? m_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]     : 0 ;\n      assign cb_mi_rresp[slot*2+:2]                                                      = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? m_axi_rresp[slot*2+:2]                                                      : 0 ;\n      assign cb_mi_rlast[slot*1+:1]                                                      = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? m_axi_rlast[slot*1+:1]                                                      : 1'b1 ;\n      assign cb_mi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                      = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                      : 0 ;\n      assign cb_mi_rvalid[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? m_axi_rvalid[slot*1+:1]                                                     : 0 ;\n    end  // gen_mi_tieoff\n\n    if ((C_CONNECTIVITY_MODE==0) || (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_sasd\n      axi_crossbar_v2_1_16_crossbar_sasd #\n      (\n        .C_FAMILY                         (P_FAMILY),\n        .C_NUM_SLAVE_SLOTS                (C_NUM_SLAVE_SLOTS),\n        .C_NUM_MASTER_SLOTS               (C_NUM_MASTER_SLOTS),\n        .C_NUM_ADDR_RANGES                (C_NUM_ADDR_RANGES),\n        .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),\n        .C_AXI_ADDR_WIDTH                 (C_AXI_ADDR_WIDTH),\n        .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),\n        .C_AXI_PROTOCOL                   (C_AXI_PROTOCOL),\n        .C_M_AXI_BASE_ADDR                (C_M_AXI_BASE_ADDR),\n        .C_M_AXI_HIGH_ADDR                (f_high_addr(0)),\n        .C_S_AXI_BASE_ID                  (P_S_AXI_BASE_ID),\n        .C_S_AXI_HIGH_ID                  (P_S_AXI_HIGH_ID),\n        .C_AXI_SUPPORTS_USER_SIGNALS      (C_AXI_SUPPORTS_USER_SIGNALS),\n        .C_AXI_AWUSER_WIDTH               (C_AXI_AWUSER_WIDTH),\n        .C_AXI_ARUSER_WIDTH               (C_AXI_ARUSER_WIDTH),\n        .C_AXI_WUSER_WIDTH                (C_AXI_WUSER_WIDTH),\n        .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),\n        .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),\n        .C_S_AXI_SUPPORTS_WRITE           (P_S_AXI_SUPPORTS_WRITE),\n        .C_S_AXI_SUPPORTS_READ            (P_S_AXI_SUPPORTS_READ),\n        .C_M_AXI_SUPPORTS_WRITE           (P_M_AXI_SUPPORTS_WRITE),\n        .C_M_AXI_SUPPORTS_READ            (P_M_AXI_SUPPORTS_READ),\n        .C_S_AXI_ARB_PRIORITY             (C_S_AXI_ARB_PRIORITY),\n        .C_M_AXI_SECURE                   (C_M_AXI_SECURE),\n        .C_R_REGISTER                     (C_R_REGISTER),\n        .C_RANGE_CHECK                    (P_RANGE_CHECK),\n        .C_ADDR_DECODE                    (P_ADDR_DECODE),\n        .C_M_AXI_ERR_MODE                 (P_M_AXI_ERR_MODE),\n        .C_DEBUG                          (C_DEBUG)\n      )\n        crossbar_sasd_0\n      (\n          .ACLK                             (aclk),\n          .ARESETN                          (aresetn),\n          .S_AXI_AWID                       (si_cb_awid           ),\n          .S_AXI_AWADDR                     (si_cb_awaddr         ),\n          .S_AXI_AWLEN                      (si_cb_awlen          ),\n          .S_AXI_AWSIZE                     (si_cb_awsize         ),\n          .S_AXI_AWBURST                    (si_cb_awburst        ),\n          .S_AXI_AWLOCK                     (si_cb_awlock         ),\n          .S_AXI_AWCACHE                    (si_cb_awcache        ),\n          .S_AXI_AWPROT                     (si_cb_awprot         ),\n//          .S_AXI_AWREGION                   (si_cb_awregion       ),\n          .S_AXI_AWQOS                      (si_cb_awqos          ),\n          .S_AXI_AWUSER                     (si_cb_awuser         ),\n          .S_AXI_AWVALID                    (si_cb_awvalid        ),\n          .S_AXI_AWREADY                    (si_cb_awready        ),\n          .S_AXI_WID                        (si_cb_wid             ),\n          .S_AXI_WDATA                      (si_cb_wdata          ),\n          .S_AXI_WSTRB                      (si_cb_wstrb          ),\n          .S_AXI_WLAST                      (si_cb_wlast          ),\n          .S_AXI_WUSER                      (si_cb_wuser          ),\n          .S_AXI_WVALID                     (si_cb_wvalid         ),\n          .S_AXI_WREADY                     (si_cb_wready         ),\n          .S_AXI_BID                        (si_cb_bid            ),\n          .S_AXI_BRESP                      (si_cb_bresp          ),\n          .S_AXI_BUSER                      (si_cb_buser          ),\n          .S_AXI_BVALID                     (si_cb_bvalid         ),\n          .S_AXI_BREADY                     (si_cb_bready         ),\n          .S_AXI_ARID                       (si_cb_arid           ),\n          .S_AXI_ARADDR                     (si_cb_araddr         ),\n          .S_AXI_ARLEN                      (si_cb_arlen          ),\n          .S_AXI_ARSIZE                     (si_cb_arsize         ),\n          .S_AXI_ARBURST                    (si_cb_arburst        ),\n          .S_AXI_ARLOCK                     (si_cb_arlock         ),\n          .S_AXI_ARCACHE                    (si_cb_arcache        ),\n          .S_AXI_ARPROT                     (si_cb_arprot         ),\n//          .S_AXI_ARREGION                   (si_cb_arregion       ),\n          .S_AXI_ARQOS                      (si_cb_arqos          ),\n          .S_AXI_ARUSER                     (si_cb_aruser         ),\n          .S_AXI_ARVALID                    (si_cb_arvalid        ),\n          .S_AXI_ARREADY                    (si_cb_arready        ),\n          .S_AXI_RID                        (si_cb_rid            ),\n          .S_AXI_RDATA                      (si_cb_rdata          ),\n          .S_AXI_RRESP                      (si_cb_rresp          ),\n          .S_AXI_RLAST                      (si_cb_rlast          ),\n          .S_AXI_RUSER                      (si_cb_ruser          ),\n          .S_AXI_RVALID                     (si_cb_rvalid         ),\n          .S_AXI_RREADY                     (si_cb_rready         ),\n          .M_AXI_AWID                       (cb_mi_awid           ),\n          .M_AXI_AWADDR                     (cb_mi_awaddr         ),\n          .M_AXI_AWLEN                      (cb_mi_awlen          ),\n          .M_AXI_AWSIZE                     (cb_mi_awsize         ),\n          .M_AXI_AWBURST                    (cb_mi_awburst        ),\n          .M_AXI_AWLOCK                     (cb_mi_awlock         ),\n          .M_AXI_AWCACHE                    (cb_mi_awcache        ),\n          .M_AXI_AWPROT                     (cb_mi_awprot         ),\n          .M_AXI_AWREGION                   (cb_mi_awregion       ),\n          .M_AXI_AWQOS                      (cb_mi_awqos          ),\n          .M_AXI_AWUSER                     (cb_mi_awuser         ),\n          .M_AXI_AWVALID                    (cb_mi_awvalid        ),\n          .M_AXI_AWREADY                    (cb_mi_awready        ),\n          .M_AXI_WID                        (cb_mi_wid             ),\n          .M_AXI_WDATA                      (cb_mi_wdata          ),\n          .M_AXI_WSTRB                      (cb_mi_wstrb          ),\n          .M_AXI_WLAST                      (cb_mi_wlast          ),\n          .M_AXI_WUSER                      (cb_mi_wuser          ),\n          .M_AXI_WVALID                     (cb_mi_wvalid         ),\n          .M_AXI_WREADY                     (cb_mi_wready         ),\n          .M_AXI_BID                        (cb_mi_bid            ),\n          .M_AXI_BRESP                      (cb_mi_bresp          ),\n          .M_AXI_BUSER                      (cb_mi_buser          ),\n          .M_AXI_BVALID                     (cb_mi_bvalid         ),\n          .M_AXI_BREADY                     (cb_mi_bready         ),\n          .M_AXI_ARID                       (cb_mi_arid           ),\n          .M_AXI_ARADDR                     (cb_mi_araddr         ),\n          .M_AXI_ARLEN                      (cb_mi_arlen          ),\n          .M_AXI_ARSIZE                     (cb_mi_arsize         ),\n          .M_AXI_ARBURST                    (cb_mi_arburst        ),\n          .M_AXI_ARLOCK                     (cb_mi_arlock         ),\n          .M_AXI_ARCACHE                    (cb_mi_arcache        ),\n          .M_AXI_ARPROT                     (cb_mi_arprot         ),\n          .M_AXI_ARREGION                   (cb_mi_arregion       ),\n          .M_AXI_ARQOS                      (cb_mi_arqos          ),\n          .M_AXI_ARUSER                     (cb_mi_aruser         ),\n          .M_AXI_ARVALID                    (cb_mi_arvalid        ),\n          .M_AXI_ARREADY                    (cb_mi_arready        ),\n          .M_AXI_RID                        (cb_mi_rid            ),\n          .M_AXI_RDATA                      (cb_mi_rdata          ),\n          .M_AXI_RRESP                      (cb_mi_rresp          ),\n          .M_AXI_RLAST                      (cb_mi_rlast          ),\n          .M_AXI_RUSER                      (cb_mi_ruser          ),\n          .M_AXI_RVALID                     (cb_mi_rvalid         ),\n          .M_AXI_RREADY                     (cb_mi_rready         )\n      );\n    end else begin : gen_samd\n      axi_crossbar_v2_1_16_crossbar #\n      (\n        .C_FAMILY                         (P_FAMILY),\n        .C_NUM_SLAVE_SLOTS                (C_NUM_SLAVE_SLOTS),\n        .C_NUM_MASTER_SLOTS               (C_NUM_MASTER_SLOTS),\n        .C_NUM_ADDR_RANGES                (C_NUM_ADDR_RANGES),\n        .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),\n        .C_S_AXI_THREAD_ID_WIDTH          (C_S_AXI_THREAD_ID_WIDTH),\n        .C_AXI_ADDR_WIDTH                 (C_AXI_ADDR_WIDTH),\n        .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),\n        .C_AXI_PROTOCOL                   (C_AXI_PROTOCOL),\n        .C_M_AXI_BASE_ADDR                (C_M_AXI_BASE_ADDR),\n        .C_M_AXI_HIGH_ADDR                (f_high_addr(0)),\n        .C_S_AXI_BASE_ID                  (P_S_AXI_BASE_ID),\n        .C_S_AXI_HIGH_ID                  (P_S_AXI_HIGH_ID),\n        .C_AXI_SUPPORTS_USER_SIGNALS      (C_AXI_SUPPORTS_USER_SIGNALS),\n        .C_AXI_AWUSER_WIDTH               (C_AXI_AWUSER_WIDTH),\n        .C_AXI_ARUSER_WIDTH               (C_AXI_ARUSER_WIDTH),\n        .C_AXI_WUSER_WIDTH                (C_AXI_WUSER_WIDTH),\n        .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),\n        .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),\n        .C_S_AXI_SUPPORTS_WRITE           (P_S_AXI_SUPPORTS_WRITE),\n        .C_S_AXI_SUPPORTS_READ            (P_S_AXI_SUPPORTS_READ),\n        .C_M_AXI_SUPPORTS_WRITE           (P_M_AXI_SUPPORTS_WRITE),\n        .C_M_AXI_SUPPORTS_READ            (P_M_AXI_SUPPORTS_READ),\n        .C_M_AXI_WRITE_CONNECTIVITY       (C_M_AXI_WRITE_CONNECTIVITY),\n        .C_M_AXI_READ_CONNECTIVITY        (C_M_AXI_READ_CONNECTIVITY),\n        .C_S_AXI_SINGLE_THREAD            (C_S_AXI_SINGLE_THREAD),\n        .C_S_AXI_WRITE_ACCEPTANCE         (C_S_AXI_WRITE_ACCEPTANCE),\n        .C_S_AXI_READ_ACCEPTANCE          (C_S_AXI_READ_ACCEPTANCE),\n        .C_M_AXI_WRITE_ISSUING            (C_M_AXI_WRITE_ISSUING),\n        .C_M_AXI_READ_ISSUING             (C_M_AXI_READ_ISSUING),\n        .C_S_AXI_ARB_PRIORITY             (C_S_AXI_ARB_PRIORITY),\n        .C_M_AXI_SECURE                   (C_M_AXI_SECURE),\n        .C_RANGE_CHECK                    (P_RANGE_CHECK),\n        .C_ADDR_DECODE                    (P_ADDR_DECODE),\n        .C_W_ISSUE_WIDTH                  (f_write_issue_width_vec(0) ),\n        .C_R_ISSUE_WIDTH                  (f_read_issue_width_vec(0) ),\n        .C_W_ACCEPT_WIDTH                 (f_write_accept_width_vec(0)),\n        .C_R_ACCEPT_WIDTH                 (f_read_accept_width_vec(0)),\n        .C_M_AXI_ERR_MODE                 (P_M_AXI_ERR_MODE),\n        .C_DEBUG                          (C_DEBUG)\n      )\n        crossbar_samd \n      (\n          .ACLK                             (aclk),\n          .ARESETN                          (aresetn),\n          .S_AXI_AWID                       (si_cb_awid             ),\n          .S_AXI_AWADDR                     (si_cb_awaddr           ),\n          .S_AXI_AWLEN                      (si_cb_awlen            ),\n          .S_AXI_AWSIZE                     (si_cb_awsize           ),\n          .S_AXI_AWBURST                    (si_cb_awburst          ),\n          .S_AXI_AWLOCK                     (si_cb_awlock           ),\n          .S_AXI_AWCACHE                    (si_cb_awcache          ),\n          .S_AXI_AWPROT                     (si_cb_awprot           ),\n//          .S_AXI_AWREGION                   (si_cb_awregion       ),\n          .S_AXI_AWQOS                      (si_cb_awqos            ),\n          .S_AXI_AWUSER                     (si_cb_awuser           ),\n          .S_AXI_AWVALID                    (si_cb_awvalid          ),\n          .S_AXI_AWREADY                    (si_cb_awready          ),\n          .S_AXI_WID                        (si_cb_wid             ),\n          .S_AXI_WDATA                      (si_cb_wdata            ),\n          .S_AXI_WSTRB                      (si_cb_wstrb            ),\n          .S_AXI_WLAST                      (si_cb_wlast            ),\n          .S_AXI_WUSER                      (si_cb_wuser            ),\n          .S_AXI_WVALID                     (si_cb_wvalid           ),\n          .S_AXI_WREADY                     (si_cb_wready           ),\n          .S_AXI_BID                        (si_cb_bid              ),\n          .S_AXI_BRESP                      (si_cb_bresp            ),\n          .S_AXI_BUSER                      (si_cb_buser            ),\n          .S_AXI_BVALID                     (si_cb_bvalid           ),\n          .S_AXI_BREADY                     (si_cb_bready           ),\n          .S_AXI_ARID                       (si_cb_arid             ),\n          .S_AXI_ARADDR                     (si_cb_araddr           ),\n          .S_AXI_ARLEN                      (si_cb_arlen            ),\n          .S_AXI_ARSIZE                     (si_cb_arsize           ),\n          .S_AXI_ARBURST                    (si_cb_arburst          ),\n          .S_AXI_ARLOCK                     (si_cb_arlock           ),\n          .S_AXI_ARCACHE                    (si_cb_arcache          ),\n          .S_AXI_ARPROT                     (si_cb_arprot           ),\n//          .S_AXI_ARREGION                   (si_cb_arregion       ),\n          .S_AXI_ARQOS                      (si_cb_arqos            ),\n          .S_AXI_ARUSER                     (si_cb_aruser           ),\n          .S_AXI_ARVALID                    (si_cb_arvalid          ),\n          .S_AXI_ARREADY                    (si_cb_arready          ),\n          .S_AXI_RID                        (si_cb_rid              ),\n          .S_AXI_RDATA                      (si_cb_rdata            ),\n          .S_AXI_RRESP                      (si_cb_rresp            ),\n          .S_AXI_RLAST                      (si_cb_rlast            ),\n          .S_AXI_RUSER                      (si_cb_ruser            ),\n          .S_AXI_RVALID                     (si_cb_rvalid           ),\n          .S_AXI_RREADY                     (si_cb_rready           ),\n          .M_AXI_AWID                       (cb_mi_awid             ),\n          .M_AXI_AWADDR                     (cb_mi_awaddr           ),\n          .M_AXI_AWLEN                      (cb_mi_awlen            ),\n          .M_AXI_AWSIZE                     (cb_mi_awsize           ),\n          .M_AXI_AWBURST                    (cb_mi_awburst          ),\n          .M_AXI_AWLOCK                     (cb_mi_awlock           ),\n          .M_AXI_AWCACHE                    (cb_mi_awcache          ),\n          .M_AXI_AWPROT                     (cb_mi_awprot           ),\n          .M_AXI_AWREGION                   (cb_mi_awregion         ),\n          .M_AXI_AWQOS                      (cb_mi_awqos            ),\n          .M_AXI_AWUSER                     (cb_mi_awuser           ),\n          .M_AXI_AWVALID                    (cb_mi_awvalid          ),\n          .M_AXI_AWREADY                    (cb_mi_awready          ),\n          .M_AXI_WID                        (cb_mi_wid             ),\n          .M_AXI_WDATA                      (cb_mi_wdata            ),\n          .M_AXI_WSTRB                      (cb_mi_wstrb            ),\n          .M_AXI_WLAST                      (cb_mi_wlast            ),\n          .M_AXI_WUSER                      (cb_mi_wuser            ),\n          .M_AXI_WVALID                     (cb_mi_wvalid           ),\n          .M_AXI_WREADY                     (cb_mi_wready           ),\n          .M_AXI_BID                        (cb_mi_bid              ),\n          .M_AXI_BRESP                      (cb_mi_bresp            ),\n          .M_AXI_BUSER                      (cb_mi_buser            ),\n          .M_AXI_BVALID                     (cb_mi_bvalid           ),\n          .M_AXI_BREADY                     (cb_mi_bready           ),\n          .M_AXI_ARID                       (cb_mi_arid             ),\n          .M_AXI_ARADDR                     (cb_mi_araddr           ),\n          .M_AXI_ARLEN                      (cb_mi_arlen            ),\n          .M_AXI_ARSIZE                     (cb_mi_arsize           ),\n          .M_AXI_ARBURST                    (cb_mi_arburst          ),\n          .M_AXI_ARLOCK                     (cb_mi_arlock           ),\n          .M_AXI_ARCACHE                    (cb_mi_arcache          ),\n          .M_AXI_ARPROT                     (cb_mi_arprot           ),\n          .M_AXI_ARREGION                   (cb_mi_arregion         ),\n          .M_AXI_ARQOS                      (cb_mi_arqos            ),\n          .M_AXI_ARUSER                     (cb_mi_aruser           ),\n          .M_AXI_ARVALID                    (cb_mi_arvalid          ),\n          .M_AXI_ARREADY                    (cb_mi_arready          ),\n          .M_AXI_RID                        (cb_mi_rid              ),\n          .M_AXI_RDATA                      (cb_mi_rdata            ),\n          .M_AXI_RRESP                      (cb_mi_rresp            ),\n          .M_AXI_RLAST                      (cb_mi_rlast            ),\n          .M_AXI_RUSER                      (cb_mi_ruser            ),\n          .M_AXI_RVALID                     (cb_mi_rvalid           ),\n          .M_AXI_RREADY                     (cb_mi_rready           )\n      );\n    end  // gen_samd\n//  end  // gen_crossbar\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n", "num_lines": 5803}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Tool Version: Vivado v.2017.4.op (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017\n//Date        : Tue May 22 11:47:35 2018\n//Host        : ip-10-206-20-46 running 64-bit CentOS release 6.5 (Final)\n//Command     : generate_target cl_axi_interconnect.bd\n//Design      : cl_axi_interconnect\n//Purpose     : IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=cl_axi_interconnect,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=14,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_BD}\" *) (* HW_HANDOFF = \"cl_axi_interconnect.hwdef\" *) \nmodule cl_axi_interconnect\n   (ACLK,\n    ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.ACLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF S00_AXI:M00_AXI:M01_AXI:M02_AXI:M03_AXI:S01_AXI, ASSOCIATED_RESET ARESETN, CLK_DOMAIN cl_axi_interconnect_ACLK, FREQ_HZ 250000000, PHASE 0.000\" *) input ACLK;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.ARESETN RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.ARESETN, POLARITY ACTIVE_LOW\" *) input ARESETN;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M00_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M00_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARBURST\" *) output [1:0]M00_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE\" *) output [3:0]M00_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARID\" *) output [6:0]M00_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLEN\" *) output [7:0]M00_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK\" *) output [0:0]M00_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARPROT\" *) output [2:0]M00_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARQOS\" *) output [3:0]M00_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREADY\" *) input M00_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREGION\" *) output [3:0]M00_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE\" *) output [2:0]M00_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARVALID\" *) output M00_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWADDR\" *) output [63:0]M00_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWBURST\" *) output [1:0]M00_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE\" *) output [3:0]M00_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWID\" *) output [6:0]M00_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLEN\" *) output [7:0]M00_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK\" *) output [0:0]M00_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWPROT\" *) output [2:0]M00_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWQOS\" *) output [3:0]M00_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREADY\" *) input M00_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREGION\" *) output [3:0]M00_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE\" *) output [2:0]M00_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWVALID\" *) output M00_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BID\" *) input [6:0]M00_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BREADY\" *) output M00_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BRESP\" *) input [1:0]M00_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BVALID\" *) input M00_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RDATA\" *) input [511:0]M00_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RID\" *) input [6:0]M00_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RLAST\" *) input M00_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RREADY\" *) output M00_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RRESP\" *) input [1:0]M00_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RVALID\" *) input M00_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WDATA\" *) output [511:0]M00_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WLAST\" *) output M00_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WREADY\" *) input M00_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WSTRB\" *) output [63:0]M00_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WVALID\" *) output M00_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M01_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M01_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARBURST\" *) output [1:0]M01_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE\" *) output [3:0]M01_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARID\" *) output [6:0]M01_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARLEN\" *) output [7:0]M01_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK\" *) output [0:0]M01_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARPROT\" *) output [2:0]M01_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARQOS\" *) output [3:0]M01_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARREADY\" *) input M01_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARREGION\" *) output [3:0]M01_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE\" *) output [2:0]M01_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARVALID\" *) output M01_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWADDR\" *) output [63:0]M01_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWBURST\" *) output [1:0]M01_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE\" *) output [3:0]M01_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWID\" *) output [6:0]M01_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWLEN\" *) output [7:0]M01_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK\" *) output [0:0]M01_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWPROT\" *) output [2:0]M01_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWQOS\" *) output [3:0]M01_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWREADY\" *) input M01_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWREGION\" *) output [3:0]M01_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE\" *) output [2:0]M01_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWVALID\" *) output M01_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BID\" *) input [6:0]M01_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BREADY\" *) output M01_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BRESP\" *) input [1:0]M01_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BVALID\" *) input M01_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RDATA\" *) input [511:0]M01_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RID\" *) input [6:0]M01_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RLAST\" *) input M01_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RREADY\" *) output M01_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RRESP\" *) input [1:0]M01_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RVALID\" *) input M01_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WDATA\" *) output [511:0]M01_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WLAST\" *) output M01_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WREADY\" *) input M01_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WSTRB\" *) output [63:0]M01_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WVALID\" *) output M01_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M02_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M02_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARBURST\" *) output [1:0]M02_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE\" *) output [3:0]M02_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARID\" *) output [6:0]M02_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARLEN\" *) output [7:0]M02_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK\" *) output [0:0]M02_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARPROT\" *) output [2:0]M02_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARQOS\" *) output [3:0]M02_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARREADY\" *) input M02_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARREGION\" *) output [3:0]M02_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE\" *) output [2:0]M02_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARVALID\" *) output M02_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWADDR\" *) output [63:0]M02_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWBURST\" *) output [1:0]M02_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE\" *) output [3:0]M02_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWID\" *) output [6:0]M02_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWLEN\" *) output [7:0]M02_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK\" *) output [0:0]M02_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWPROT\" *) output [2:0]M02_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWQOS\" *) output [3:0]M02_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWREADY\" *) input M02_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWREGION\" *) output [3:0]M02_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE\" *) output [2:0]M02_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWVALID\" *) output M02_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BID\" *) input [6:0]M02_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BREADY\" *) output M02_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BRESP\" *) input [1:0]M02_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BVALID\" *) input M02_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RDATA\" *) input [511:0]M02_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RID\" *) input [6:0]M02_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RLAST\" *) input M02_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RREADY\" *) output M02_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RRESP\" *) input [1:0]M02_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RVALID\" *) input M02_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WDATA\" *) output [511:0]M02_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WLAST\" *) output M02_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WREADY\" *) input M02_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WSTRB\" *) output [63:0]M02_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WVALID\" *) output M02_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M03_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M03_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARBURST\" *) output [1:0]M03_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE\" *) output [3:0]M03_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARID\" *) output [6:0]M03_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARLEN\" *) output [7:0]M03_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK\" *) output [0:0]M03_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARPROT\" *) output [2:0]M03_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARQOS\" *) output [3:0]M03_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARREADY\" *) input M03_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARREGION\" *) output [3:0]M03_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE\" *) output [2:0]M03_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARVALID\" *) output M03_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWADDR\" *) output [63:0]M03_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWBURST\" *) output [1:0]M03_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE\" *) output [3:0]M03_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWID\" *) output [6:0]M03_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWLEN\" *) output [7:0]M03_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK\" *) output [0:0]M03_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWPROT\" *) output [2:0]M03_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWQOS\" *) output [3:0]M03_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWREADY\" *) input M03_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWREGION\" *) output [3:0]M03_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE\" *) output [2:0]M03_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWVALID\" *) output M03_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BID\" *) input [6:0]M03_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BREADY\" *) output M03_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BRESP\" *) input [1:0]M03_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BVALID\" *) input M03_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RDATA\" *) input [511:0]M03_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RID\" *) input [6:0]M03_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RLAST\" *) input M03_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RREADY\" *) output M03_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RRESP\" *) input [1:0]M03_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RVALID\" *) input M03_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WDATA\" *) output [511:0]M03_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WLAST\" *) output M03_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WREADY\" *) input M03_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WSTRB\" *) output [63:0]M03_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WVALID\" *) output M03_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S00_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 6, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 32, NUM_READ_THREADS 16, NUM_WRITE_OUTSTANDING 32, NUM_WRITE_THREADS 16, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) input [63:0]S00_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARBURST\" *) input [1:0]S00_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE\" *) input [3:0]S00_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARID\" *) input [5:0]S00_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLEN\" *) input [7:0]S00_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK\" *) input [0:0]S00_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARPROT\" *) input [2:0]S00_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARQOS\" *) input [3:0]S00_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREADY\" *) output S00_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREGION\" *) input [3:0]S00_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE\" *) input [2:0]S00_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARVALID\" *) input S00_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWADDR\" *) input [63:0]S00_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWBURST\" *) input [1:0]S00_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE\" *) input [3:0]S00_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWID\" *) input [5:0]S00_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLEN\" *) input [7:0]S00_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK\" *) input [0:0]S00_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWPROT\" *) input [2:0]S00_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWQOS\" *) input [3:0]S00_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREADY\" *) output S00_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREGION\" *) input [3:0]S00_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE\" *) input [2:0]S00_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWVALID\" *) input S00_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BID\" *) output [5:0]S00_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BREADY\" *) input S00_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BRESP\" *) output [1:0]S00_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BVALID\" *) output S00_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RDATA\" *) output [511:0]S00_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RID\" *) output [5:0]S00_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RLAST\" *) output S00_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RREADY\" *) input S00_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RRESP\" *) output [1:0]S00_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RVALID\" *) output S00_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WDATA\" *) input [511:0]S00_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WLAST\" *) input S00_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WREADY\" *) output S00_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WSTRB\" *) input [63:0]S00_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WVALID\" *) input S00_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S01_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 6, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 32, NUM_READ_THREADS 16, NUM_WRITE_OUTSTANDING 32, NUM_WRITE_THREADS 16, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) input [63:0]S01_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARBURST\" *) input [1:0]S01_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE\" *) input [3:0]S01_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARID\" *) input [5:0]S01_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARLEN\" *) input [7:0]S01_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK\" *) input [0:0]S01_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARPROT\" *) input [2:0]S01_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARQOS\" *) input [3:0]S01_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARREADY\" *) output S01_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARREGION\" *) input [3:0]S01_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE\" *) input [2:0]S01_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARVALID\" *) input S01_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWADDR\" *) input [63:0]S01_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWBURST\" *) input [1:0]S01_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE\" *) input [3:0]S01_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWID\" *) input [5:0]S01_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWLEN\" *) input [7:0]S01_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK\" *) input [0:0]S01_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWPROT\" *) input [2:0]S01_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWQOS\" *) input [3:0]S01_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWREADY\" *) output S01_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWREGION\" *) input [3:0]S01_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE\" *) input [2:0]S01_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWVALID\" *) input S01_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BID\" *) output [5:0]S01_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BREADY\" *) input S01_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BRESP\" *) output [1:0]S01_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BVALID\" *) output S01_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RDATA\" *) output [511:0]S01_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RID\" *) output [5:0]S01_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RLAST\" *) output S01_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RREADY\" *) input S01_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RRESP\" *) output [1:0]S01_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RVALID\" *) output S01_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WDATA\" *) input [511:0]S01_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WLAST\" *) input S01_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WREADY\" *) output S01_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WSTRB\" *) input [63:0]S01_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WVALID\" *) input S01_AXI_wvalid;\n\n  wire ACLK_1;\n  wire ARESETN_1;\n  wire [63:0]S00_AXI_1_ARADDR;\n  wire [1:0]S00_AXI_1_ARBURST;\n  wire [3:0]S00_AXI_1_ARCACHE;\n  wire [5:0]S00_AXI_1_ARID;\n  wire [7:0]S00_AXI_1_ARLEN;\n  wire [0:0]S00_AXI_1_ARLOCK;\n  wire [2:0]S00_AXI_1_ARPROT;\n  wire [3:0]S00_AXI_1_ARQOS;\n  wire S00_AXI_1_ARREADY;\n  wire [3:0]S00_AXI_1_ARREGION;\n  wire [2:0]S00_AXI_1_ARSIZE;\n  wire S00_AXI_1_ARVALID;\n  wire [63:0]S00_AXI_1_AWADDR;\n  wire [1:0]S00_AXI_1_AWBURST;\n  wire [3:0]S00_AXI_1_AWCACHE;\n  wire [5:0]S00_AXI_1_AWID;\n  wire [7:0]S00_AXI_1_AWLEN;\n  wire [0:0]S00_AXI_1_AWLOCK;\n  wire [2:0]S00_AXI_1_AWPROT;\n  wire [3:0]S00_AXI_1_AWQOS;\n  wire S00_AXI_1_AWREADY;\n  wire [3:0]S00_AXI_1_AWREGION;\n  wire [2:0]S00_AXI_1_AWSIZE;\n  wire S00_AXI_1_AWVALID;\n  wire [5:0]S00_AXI_1_BID;\n  wire S00_AXI_1_BREADY;\n  wire [1:0]S00_AXI_1_BRESP;\n  wire S00_AXI_1_BVALID;\n  wire [511:0]S00_AXI_1_RDATA;\n  wire [5:0]S00_AXI_1_RID;\n  wire S00_AXI_1_RLAST;\n  wire S00_AXI_1_RREADY;\n  wire [1:0]S00_AXI_1_RRESP;\n  wire S00_AXI_1_RVALID;\n  wire [511:0]S00_AXI_1_WDATA;\n  wire S00_AXI_1_WLAST;\n  wire S00_AXI_1_WREADY;\n  wire [63:0]S00_AXI_1_WSTRB;\n  wire S00_AXI_1_WVALID;\n  wire [63:0]S01_AXI_1_ARADDR;\n  wire [1:0]S01_AXI_1_ARBURST;\n  wire [3:0]S01_AXI_1_ARCACHE;\n  wire [5:0]S01_AXI_1_ARID;\n  wire [7:0]S01_AXI_1_ARLEN;\n  wire [0:0]S01_AXI_1_ARLOCK;\n  wire [2:0]S01_AXI_1_ARPROT;\n  wire [3:0]S01_AXI_1_ARQOS;\n  wire S01_AXI_1_ARREADY;\n  wire [3:0]S01_AXI_1_ARREGION;\n  wire [2:0]S01_AXI_1_ARSIZE;\n  wire S01_AXI_1_ARVALID;\n  wire [63:0]S01_AXI_1_AWADDR;\n  wire [1:0]S01_AXI_1_AWBURST;\n  wire [3:0]S01_AXI_1_AWCACHE;\n  wire [5:0]S01_AXI_1_AWID;\n  wire [7:0]S01_AXI_1_AWLEN;\n  wire [0:0]S01_AXI_1_AWLOCK;\n  wire [2:0]S01_AXI_1_AWPROT;\n  wire [3:0]S01_AXI_1_AWQOS;\n  wire S01_AXI_1_AWREADY;\n  wire [3:0]S01_AXI_1_AWREGION;\n  wire [2:0]S01_AXI_1_AWSIZE;\n  wire S01_AXI_1_AWVALID;\n  wire [5:0]S01_AXI_1_BID;\n  wire S01_AXI_1_BREADY;\n  wire [1:0]S01_AXI_1_BRESP;\n  wire S01_AXI_1_BVALID;\n  wire [511:0]S01_AXI_1_RDATA;\n  wire [5:0]S01_AXI_1_RID;\n  wire S01_AXI_1_RLAST;\n  wire S01_AXI_1_RREADY;\n  wire [1:0]S01_AXI_1_RRESP;\n  wire S01_AXI_1_RVALID;\n  wire [511:0]S01_AXI_1_WDATA;\n  wire S01_AXI_1_WLAST;\n  wire S01_AXI_1_WREADY;\n  wire [63:0]S01_AXI_1_WSTRB;\n  wire S01_AXI_1_WVALID;\n  wire [63:0]axi_interconnect_0_M00_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M00_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M00_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M00_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M00_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M00_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARQOS;\n  wire axi_interconnect_0_M00_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M00_AXI_ARSIZE;\n  wire axi_interconnect_0_M00_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M00_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M00_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M00_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M00_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M00_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M00_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWQOS;\n  wire axi_interconnect_0_M00_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M00_AXI_AWSIZE;\n  wire axi_interconnect_0_M00_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M00_AXI_BID;\n  wire axi_interconnect_0_M00_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M00_AXI_BRESP;\n  wire axi_interconnect_0_M00_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M00_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M00_AXI_RID;\n  wire axi_interconnect_0_M00_AXI_RLAST;\n  wire axi_interconnect_0_M00_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M00_AXI_RRESP;\n  wire axi_interconnect_0_M00_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M00_AXI_WDATA;\n  wire axi_interconnect_0_M00_AXI_WLAST;\n  wire axi_interconnect_0_M00_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M00_AXI_WSTRB;\n  wire axi_interconnect_0_M00_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M01_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M01_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M01_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M01_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M01_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M01_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARQOS;\n  wire axi_interconnect_0_M01_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M01_AXI_ARSIZE;\n  wire axi_interconnect_0_M01_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M01_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M01_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M01_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M01_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M01_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M01_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWQOS;\n  wire axi_interconnect_0_M01_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M01_AXI_AWSIZE;\n  wire axi_interconnect_0_M01_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M01_AXI_BID;\n  wire axi_interconnect_0_M01_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M01_AXI_BRESP;\n  wire axi_interconnect_0_M01_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M01_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M01_AXI_RID;\n  wire axi_interconnect_0_M01_AXI_RLAST;\n  wire axi_interconnect_0_M01_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M01_AXI_RRESP;\n  wire axi_interconnect_0_M01_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M01_AXI_WDATA;\n  wire axi_interconnect_0_M01_AXI_WLAST;\n  wire axi_interconnect_0_M01_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M01_AXI_WSTRB;\n  wire axi_interconnect_0_M01_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M02_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M02_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M02_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M02_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M02_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M02_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARQOS;\n  wire axi_interconnect_0_M02_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M02_AXI_ARSIZE;\n  wire axi_interconnect_0_M02_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M02_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M02_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M02_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M02_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M02_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M02_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWQOS;\n  wire axi_interconnect_0_M02_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M02_AXI_AWSIZE;\n  wire axi_interconnect_0_M02_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M02_AXI_BID;\n  wire axi_interconnect_0_M02_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M02_AXI_BRESP;\n  wire axi_interconnect_0_M02_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M02_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M02_AXI_RID;\n  wire axi_interconnect_0_M02_AXI_RLAST;\n  wire axi_interconnect_0_M02_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M02_AXI_RRESP;\n  wire axi_interconnect_0_M02_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M02_AXI_WDATA;\n  wire axi_interconnect_0_M02_AXI_WLAST;\n  wire axi_interconnect_0_M02_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M02_AXI_WSTRB;\n  wire axi_interconnect_0_M02_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M03_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M03_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M03_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M03_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M03_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M03_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARQOS;\n  wire axi_interconnect_0_M03_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M03_AXI_ARSIZE;\n  wire axi_interconnect_0_M03_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M03_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M03_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M03_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M03_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M03_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M03_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWQOS;\n  wire axi_interconnect_0_M03_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M03_AXI_AWSIZE;\n  wire axi_interconnect_0_M03_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M03_AXI_BID;\n  wire axi_interconnect_0_M03_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M03_AXI_BRESP;\n  wire axi_interconnect_0_M03_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M03_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M03_AXI_RID;\n  wire axi_interconnect_0_M03_AXI_RLAST;\n  wire axi_interconnect_0_M03_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M03_AXI_RRESP;\n  wire axi_interconnect_0_M03_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M03_AXI_WDATA;\n  wire axi_interconnect_0_M03_AXI_WLAST;\n  wire axi_interconnect_0_M03_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M03_AXI_WSTRB;\n  wire axi_interconnect_0_M03_AXI_WVALID;\n\n  assign ACLK_1 = ACLK;\n  assign ARESETN_1 = ARESETN;\n  assign M00_AXI_araddr[63:0] = axi_interconnect_0_M00_AXI_ARADDR;\n  assign M00_AXI_arburst[1:0] = axi_interconnect_0_M00_AXI_ARBURST;\n  assign M00_AXI_arcache[3:0] = axi_interconnect_0_M00_AXI_ARCACHE;\n  assign M00_AXI_arid[6:0] = axi_interconnect_0_M00_AXI_ARID;\n  assign M00_AXI_arlen[7:0] = axi_interconnect_0_M00_AXI_ARLEN;\n  assign M00_AXI_arlock[0] = axi_interconnect_0_M00_AXI_ARLOCK;\n  assign M00_AXI_arprot[2:0] = axi_interconnect_0_M00_AXI_ARPROT;\n  assign M00_AXI_arqos[3:0] = axi_interconnect_0_M00_AXI_ARQOS;\n  assign M00_AXI_arregion[3:0] = axi_interconnect_0_M00_AXI_ARREGION;\n  assign M00_AXI_arsize[2:0] = axi_interconnect_0_M00_AXI_ARSIZE;\n  assign M00_AXI_arvalid = axi_interconnect_0_M00_AXI_ARVALID;\n  assign M00_AXI_awaddr[63:0] = axi_interconnect_0_M00_AXI_AWADDR;\n  assign M00_AXI_awburst[1:0] = axi_interconnect_0_M00_AXI_AWBURST;\n  assign M00_AXI_awcache[3:0] = axi_interconnect_0_M00_AXI_AWCACHE;\n  assign M00_AXI_awid[6:0] = axi_interconnect_0_M00_AXI_AWID;\n  assign M00_AXI_awlen[7:0] = axi_interconnect_0_M00_AXI_AWLEN;\n  assign M00_AXI_awlock[0] = axi_interconnect_0_M00_AXI_AWLOCK;\n  assign M00_AXI_awprot[2:0] = axi_interconnect_0_M00_AXI_AWPROT;\n  assign M00_AXI_awqos[3:0] = axi_interconnect_0_M00_AXI_AWQOS;\n  assign M00_AXI_awregion[3:0] = axi_interconnect_0_M00_AXI_AWREGION;\n  assign M00_AXI_awsize[2:0] = axi_interconnect_0_M00_AXI_AWSIZE;\n  assign M00_AXI_awvalid = axi_interconnect_0_M00_AXI_AWVALID;\n  assign M00_AXI_bready = axi_interconnect_0_M00_AXI_BREADY;\n  assign M00_AXI_rready = axi_interconnect_0_M00_AXI_RREADY;\n  assign M00_AXI_wdata[511:0] = axi_interconnect_0_M00_AXI_WDATA;\n  assign M00_AXI_wlast = axi_interconnect_0_M00_AXI_WLAST;\n  assign M00_AXI_wstrb[63:0] = axi_interconnect_0_M00_AXI_WSTRB;\n  assign M00_AXI_wvalid = axi_interconnect_0_M00_AXI_WVALID;\n  assign M01_AXI_araddr[63:0] = axi_interconnect_0_M01_AXI_ARADDR;\n  assign M01_AXI_arburst[1:0] = axi_interconnect_0_M01_AXI_ARBURST;\n  assign M01_AXI_arcache[3:0] = axi_interconnect_0_M01_AXI_ARCACHE;\n  assign M01_AXI_arid[6:0] = axi_interconnect_0_M01_AXI_ARID;\n  assign M01_AXI_arlen[7:0] = axi_interconnect_0_M01_AXI_ARLEN;\n  assign M01_AXI_arlock[0] = axi_interconnect_0_M01_AXI_ARLOCK;\n  assign M01_AXI_arprot[2:0] = axi_interconnect_0_M01_AXI_ARPROT;\n  assign M01_AXI_arqos[3:0] = axi_interconnect_0_M01_AXI_ARQOS;\n  assign M01_AXI_arregion[3:0] = axi_interconnect_0_M01_AXI_ARREGION;\n  assign M01_AXI_arsize[2:0] = axi_interconnect_0_M01_AXI_ARSIZE;\n  assign M01_AXI_arvalid = axi_interconnect_0_M01_AXI_ARVALID;\n  assign M01_AXI_awaddr[63:0] = axi_interconnect_0_M01_AXI_AWADDR;\n  assign M01_AXI_awburst[1:0] = axi_interconnect_0_M01_AXI_AWBURST;\n  assign M01_AXI_awcache[3:0] = axi_interconnect_0_M01_AXI_AWCACHE;\n  assign M01_AXI_awid[6:0] = axi_interconnect_0_M01_AXI_AWID;\n  assign M01_AXI_awlen[7:0] = axi_interconnect_0_M01_AXI_AWLEN;\n  assign M01_AXI_awlock[0] = axi_interconnect_0_M01_AXI_AWLOCK;\n  assign M01_AXI_awprot[2:0] = axi_interconnect_0_M01_AXI_AWPROT;\n  assign M01_AXI_awqos[3:0] = axi_interconnect_0_M01_AXI_AWQOS;\n  assign M01_AXI_awregion[3:0] = axi_interconnect_0_M01_AXI_AWREGION;\n  assign M01_AXI_awsize[2:0] = axi_interconnect_0_M01_AXI_AWSIZE;\n  assign M01_AXI_awvalid = axi_interconnect_0_M01_AXI_AWVALID;\n  assign M01_AXI_bready = axi_interconnect_0_M01_AXI_BREADY;\n  assign M01_AXI_rready = axi_interconnect_0_M01_AXI_RREADY;\n  assign M01_AXI_wdata[511:0] = axi_interconnect_0_M01_AXI_WDATA;\n  assign M01_AXI_wlast = axi_interconnect_0_M01_AXI_WLAST;\n  assign M01_AXI_wstrb[63:0] = axi_interconnect_0_M01_AXI_WSTRB;\n  assign M01_AXI_wvalid = axi_interconnect_0_M01_AXI_WVALID;\n  assign M02_AXI_araddr[63:0] = axi_interconnect_0_M02_AXI_ARADDR;\n  assign M02_AXI_arburst[1:0] = axi_interconnect_0_M02_AXI_ARBURST;\n  assign M02_AXI_arcache[3:0] = axi_interconnect_0_M02_AXI_ARCACHE;\n  assign M02_AXI_arid[6:0] = axi_interconnect_0_M02_AXI_ARID;\n  assign M02_AXI_arlen[7:0] = axi_interconnect_0_M02_AXI_ARLEN;\n  assign M02_AXI_arlock[0] = axi_interconnect_0_M02_AXI_ARLOCK;\n  assign M02_AXI_arprot[2:0] = axi_interconnect_0_M02_AXI_ARPROT;\n  assign M02_AXI_arqos[3:0] = axi_interconnect_0_M02_AXI_ARQOS;\n  assign M02_AXI_arregion[3:0] = axi_interconnect_0_M02_AXI_ARREGION;\n  assign M02_AXI_arsize[2:0] = axi_interconnect_0_M02_AXI_ARSIZE;\n  assign M02_AXI_arvalid = axi_interconnect_0_M02_AXI_ARVALID;\n  assign M02_AXI_awaddr[63:0] = axi_interconnect_0_M02_AXI_AWADDR;\n  assign M02_AXI_awburst[1:0] = axi_interconnect_0_M02_AXI_AWBURST;\n  assign M02_AXI_awcache[3:0] = axi_interconnect_0_M02_AXI_AWCACHE;\n  assign M02_AXI_awid[6:0] = axi_interconnect_0_M02_AXI_AWID;\n  assign M02_AXI_awlen[7:0] = axi_interconnect_0_M02_AXI_AWLEN;\n  assign M02_AXI_awlock[0] = axi_interconnect_0_M02_AXI_AWLOCK;\n  assign M02_AXI_awprot[2:0] = axi_interconnect_0_M02_AXI_AWPROT;\n  assign M02_AXI_awqos[3:0] = axi_interconnect_0_M02_AXI_AWQOS;\n  assign M02_AXI_awregion[3:0] = axi_interconnect_0_M02_AXI_AWREGION;\n  assign M02_AXI_awsize[2:0] = axi_interconnect_0_M02_AXI_AWSIZE;\n  assign M02_AXI_awvalid = axi_interconnect_0_M02_AXI_AWVALID;\n  assign M02_AXI_bready = axi_interconnect_0_M02_AXI_BREADY;\n  assign M02_AXI_rready = axi_interconnect_0_M02_AXI_RREADY;\n  assign M02_AXI_wdata[511:0] = axi_interconnect_0_M02_AXI_WDATA;\n  assign M02_AXI_wlast = axi_interconnect_0_M02_AXI_WLAST;\n  assign M02_AXI_wstrb[63:0] = axi_interconnect_0_M02_AXI_WSTRB;\n  assign M02_AXI_wvalid = axi_interconnect_0_M02_AXI_WVALID;\n  assign M03_AXI_araddr[63:0] = axi_interconnect_0_M03_AXI_ARADDR;\n  assign M03_AXI_arburst[1:0] = axi_interconnect_0_M03_AXI_ARBURST;\n  assign M03_AXI_arcache[3:0] = axi_interconnect_0_M03_AXI_ARCACHE;\n  assign M03_AXI_arid[6:0] = axi_interconnect_0_M03_AXI_ARID;\n  assign M03_AXI_arlen[7:0] = axi_interconnect_0_M03_AXI_ARLEN;\n  assign M03_AXI_arlock[0] = axi_interconnect_0_M03_AXI_ARLOCK;\n  assign M03_AXI_arprot[2:0] = axi_interconnect_0_M03_AXI_ARPROT;\n  assign M03_AXI_arqos[3:0] = axi_interconnect_0_M03_AXI_ARQOS;\n  assign M03_AXI_arregion[3:0] = axi_interconnect_0_M03_AXI_ARREGION;\n  assign M03_AXI_arsize[2:0] = axi_interconnect_0_M03_AXI_ARSIZE;\n  assign M03_AXI_arvalid = axi_interconnect_0_M03_AXI_ARVALID;\n  assign M03_AXI_awaddr[63:0] = axi_interconnect_0_M03_AXI_AWADDR;\n  assign M03_AXI_awburst[1:0] = axi_interconnect_0_M03_AXI_AWBURST;\n  assign M03_AXI_awcache[3:0] = axi_interconnect_0_M03_AXI_AWCACHE;\n  assign M03_AXI_awid[6:0] = axi_interconnect_0_M03_AXI_AWID;\n  assign M03_AXI_awlen[7:0] = axi_interconnect_0_M03_AXI_AWLEN;\n  assign M03_AXI_awlock[0] = axi_interconnect_0_M03_AXI_AWLOCK;\n  assign M03_AXI_awprot[2:0] = axi_interconnect_0_M03_AXI_AWPROT;\n  assign M03_AXI_awqos[3:0] = axi_interconnect_0_M03_AXI_AWQOS;\n  assign M03_AXI_awregion[3:0] = axi_interconnect_0_M03_AXI_AWREGION;\n  assign M03_AXI_awsize[2:0] = axi_interconnect_0_M03_AXI_AWSIZE;\n  assign M03_AXI_awvalid = axi_interconnect_0_M03_AXI_AWVALID;\n  assign M03_AXI_bready = axi_interconnect_0_M03_AXI_BREADY;\n  assign M03_AXI_rready = axi_interconnect_0_M03_AXI_RREADY;\n  assign M03_AXI_wdata[511:0] = axi_interconnect_0_M03_AXI_WDATA;\n  assign M03_AXI_wlast = axi_interconnect_0_M03_AXI_WLAST;\n  assign M03_AXI_wstrb[63:0] = axi_interconnect_0_M03_AXI_WSTRB;\n  assign M03_AXI_wvalid = axi_interconnect_0_M03_AXI_WVALID;\n  assign S00_AXI_1_ARADDR = S00_AXI_araddr[63:0];\n  assign S00_AXI_1_ARBURST = S00_AXI_arburst[1:0];\n  assign S00_AXI_1_ARCACHE = S00_AXI_arcache[3:0];\n  assign S00_AXI_1_ARID = S00_AXI_arid[5:0];\n  assign S00_AXI_1_ARLEN = S00_AXI_arlen[7:0];\n  assign S00_AXI_1_ARLOCK = S00_AXI_arlock[0];\n  assign S00_AXI_1_ARPROT = S00_AXI_arprot[2:0];\n  assign S00_AXI_1_ARQOS = S00_AXI_arqos[3:0];\n  assign S00_AXI_1_ARREGION = S00_AXI_arregion[3:0];\n  assign S00_AXI_1_ARSIZE = S00_AXI_arsize[2:0];\n  assign S00_AXI_1_ARVALID = S00_AXI_arvalid;\n  assign S00_AXI_1_AWADDR = S00_AXI_awaddr[63:0];\n  assign S00_AXI_1_AWBURST = S00_AXI_awburst[1:0];\n  assign S00_AXI_1_AWCACHE = S00_AXI_awcache[3:0];\n  assign S00_AXI_1_AWID = S00_AXI_awid[5:0];\n  assign S00_AXI_1_AWLEN = S00_AXI_awlen[7:0];\n  assign S00_AXI_1_AWLOCK = S00_AXI_awlock[0];\n  assign S00_AXI_1_AWPROT = S00_AXI_awprot[2:0];\n  assign S00_AXI_1_AWQOS = S00_AXI_awqos[3:0];\n  assign S00_AXI_1_AWREGION = S00_AXI_awregion[3:0];\n  assign S00_AXI_1_AWSIZE = S00_AXI_awsize[2:0];\n  assign S00_AXI_1_AWVALID = S00_AXI_awvalid;\n  assign S00_AXI_1_BREADY = S00_AXI_bready;\n  assign S00_AXI_1_RREADY = S00_AXI_rready;\n  assign S00_AXI_1_WDATA = S00_AXI_wdata[511:0];\n  assign S00_AXI_1_WLAST = S00_AXI_wlast;\n  assign S00_AXI_1_WSTRB = S00_AXI_wstrb[63:0];\n  assign S00_AXI_1_WVALID = S00_AXI_wvalid;\n  assign S00_AXI_arready = S00_AXI_1_ARREADY;\n  assign S00_AXI_awready = S00_AXI_1_AWREADY;\n  assign S00_AXI_bid[5:0] = S00_AXI_1_BID;\n  assign S00_AXI_bresp[1:0] = S00_AXI_1_BRESP;\n  assign S00_AXI_bvalid = S00_AXI_1_BVALID;\n  assign S00_AXI_rdata[511:0] = S00_AXI_1_RDATA;\n  assign S00_AXI_rid[5:0] = S00_AXI_1_RID;\n  assign S00_AXI_rlast = S00_AXI_1_RLAST;\n  assign S00_AXI_rresp[1:0] = S00_AXI_1_RRESP;\n  assign S00_AXI_rvalid = S00_AXI_1_RVALID;\n  assign S00_AXI_wready = S00_AXI_1_WREADY;\n  assign S01_AXI_1_ARADDR = S01_AXI_araddr[63:0];\n  assign S01_AXI_1_ARBURST = S01_AXI_arburst[1:0];\n  assign S01_AXI_1_ARCACHE = S01_AXI_arcache[3:0];\n  assign S01_AXI_1_ARID = S01_AXI_arid[5:0];\n  assign S01_AXI_1_ARLEN = S01_AXI_arlen[7:0];\n  assign S01_AXI_1_ARLOCK = S01_AXI_arlock[0];\n  assign S01_AXI_1_ARPROT = S01_AXI_arprot[2:0];\n  assign S01_AXI_1_ARQOS = S01_AXI_arqos[3:0];\n  assign S01_AXI_1_ARREGION = S01_AXI_arregion[3:0];\n  assign S01_AXI_1_ARSIZE = S01_AXI_arsize[2:0];\n  assign S01_AXI_1_ARVALID = S01_AXI_arvalid;\n  assign S01_AXI_1_AWADDR = S01_AXI_awaddr[63:0];\n  assign S01_AXI_1_AWBURST = S01_AXI_awburst[1:0];\n  assign S01_AXI_1_AWCACHE = S01_AXI_awcache[3:0];\n  assign S01_AXI_1_AWID = S01_AXI_awid[5:0];\n  assign S01_AXI_1_AWLEN = S01_AXI_awlen[7:0];\n  assign S01_AXI_1_AWLOCK = S01_AXI_awlock[0];\n  assign S01_AXI_1_AWPROT = S01_AXI_awprot[2:0];\n  assign S01_AXI_1_AWQOS = S01_AXI_awqos[3:0];\n  assign S01_AXI_1_AWREGION = S01_AXI_awregion[3:0];\n  assign S01_AXI_1_AWSIZE = S01_AXI_awsize[2:0];\n  assign S01_AXI_1_AWVALID = S01_AXI_awvalid;\n  assign S01_AXI_1_BREADY = S01_AXI_bready;\n  assign S01_AXI_1_RREADY = S01_AXI_rready;\n  assign S01_AXI_1_WDATA = S01_AXI_wdata[511:0];\n  assign S01_AXI_1_WLAST = S01_AXI_wlast;\n  assign S01_AXI_1_WSTRB = S01_AXI_wstrb[63:0];\n  assign S01_AXI_1_WVALID = S01_AXI_wvalid;\n  assign S01_AXI_arready = S01_AXI_1_ARREADY;\n  assign S01_AXI_awready = S01_AXI_1_AWREADY;\n  assign S01_AXI_bid[5:0] = S01_AXI_1_BID;\n  assign S01_AXI_bresp[1:0] = S01_AXI_1_BRESP;\n  assign S01_AXI_bvalid = S01_AXI_1_BVALID;\n  assign S01_AXI_rdata[511:0] = S01_AXI_1_RDATA;\n  assign S01_AXI_rid[5:0] = S01_AXI_1_RID;\n  assign S01_AXI_rlast = S01_AXI_1_RLAST;\n  assign S01_AXI_rresp[1:0] = S01_AXI_1_RRESP;\n  assign S01_AXI_rvalid = S01_AXI_1_RVALID;\n  assign S01_AXI_wready = S01_AXI_1_WREADY;\n  assign axi_interconnect_0_M00_AXI_ARREADY = M00_AXI_arready;\n  assign axi_interconnect_0_M00_AXI_AWREADY = M00_AXI_awready;\n  assign axi_interconnect_0_M00_AXI_BID = M00_AXI_bid[6:0];\n  assign axi_interconnect_0_M00_AXI_BRESP = M00_AXI_bresp[1:0];\n  assign axi_interconnect_0_M00_AXI_BVALID = M00_AXI_bvalid;\n  assign axi_interconnect_0_M00_AXI_RDATA = M00_AXI_rdata[511:0];\n  assign axi_interconnect_0_M00_AXI_RID = M00_AXI_rid[6:0];\n  assign axi_interconnect_0_M00_AXI_RLAST = M00_AXI_rlast;\n  assign axi_interconnect_0_M00_AXI_RRESP = M00_AXI_rresp[1:0];\n  assign axi_interconnect_0_M00_AXI_RVALID = M00_AXI_rvalid;\n  assign axi_interconnect_0_M00_AXI_WREADY = M00_AXI_wready;\n  assign axi_interconnect_0_M01_AXI_ARREADY = M01_AXI_arready;\n  assign axi_interconnect_0_M01_AXI_AWREADY = M01_AXI_awready;\n  assign axi_interconnect_0_M01_AXI_BID = M01_AXI_bid[6:0];\n  assign axi_interconnect_0_M01_AXI_BRESP = M01_AXI_bresp[1:0];\n  assign axi_interconnect_0_M01_AXI_BVALID = M01_AXI_bvalid;\n  assign axi_interconnect_0_M01_AXI_RDATA = M01_AXI_rdata[511:0];\n  assign axi_interconnect_0_M01_AXI_RID = M01_AXI_rid[6:0];\n  assign axi_interconnect_0_M01_AXI_RLAST = M01_AXI_rlast;\n  assign axi_interconnect_0_M01_AXI_RRESP = M01_AXI_rresp[1:0];\n  assign axi_interconnect_0_M01_AXI_RVALID = M01_AXI_rvalid;\n  assign axi_interconnect_0_M01_AXI_WREADY = M01_AXI_wready;\n  assign axi_interconnect_0_M02_AXI_ARREADY = M02_AXI_arready;\n  assign axi_interconnect_0_M02_AXI_AWREADY = M02_AXI_awready;\n  assign axi_interconnect_0_M02_AXI_BID = M02_AXI_bid[6:0];\n  assign axi_interconnect_0_M02_AXI_BRESP = M02_AXI_bresp[1:0];\n  assign axi_interconnect_0_M02_AXI_BVALID = M02_AXI_bvalid;\n  assign axi_interconnect_0_M02_AXI_RDATA = M02_AXI_rdata[511:0];\n  assign axi_interconnect_0_M02_AXI_RID = M02_AXI_rid[6:0];\n  assign axi_interconnect_0_M02_AXI_RLAST = M02_AXI_rlast;\n  assign axi_interconnect_0_M02_AXI_RRESP = M02_AXI_rresp[1:0];\n  assign axi_interconnect_0_M02_AXI_RVALID = M02_AXI_rvalid;\n  assign axi_interconnect_0_M02_AXI_WREADY = M02_AXI_wready;\n  assign axi_interconnect_0_M03_AXI_ARREADY = M03_AXI_arready;\n  assign axi_interconnect_0_M03_AXI_AWREADY = M03_AXI_awready;\n  assign axi_interconnect_0_M03_AXI_BID = M03_AXI_bid[6:0];\n  assign axi_interconnect_0_M03_AXI_BRESP = M03_AXI_bresp[1:0];\n  assign axi_interconnect_0_M03_AXI_BVALID = M03_AXI_bvalid;\n  assign axi_interconnect_0_M03_AXI_RDATA = M03_AXI_rdata[511:0];\n  assign axi_interconnect_0_M03_AXI_RID = M03_AXI_rid[6:0];\n  assign axi_interconnect_0_M03_AXI_RLAST = M03_AXI_rlast;\n  assign axi_interconnect_0_M03_AXI_RRESP = M03_AXI_rresp[1:0];\n  assign axi_interconnect_0_M03_AXI_RVALID = M03_AXI_rvalid;\n  assign axi_interconnect_0_M03_AXI_WREADY = M03_AXI_wready;\n  cl_axi_interconnect_axi_interconnect_0_0 axi_interconnect_0\n       (.ACLK(ACLK_1),\n        .ARESETN(ARESETN_1),\n        .M00_ACLK(ACLK_1),\n        .M00_ARESETN(ARESETN_1),\n        .M00_AXI_araddr(axi_interconnect_0_M00_AXI_ARADDR),\n        .M00_AXI_arburst(axi_interconnect_0_M00_AXI_ARBURST),\n        .M00_AXI_arcache(axi_interconnect_0_M00_AXI_ARCACHE),\n        .M00_AXI_arid(axi_interconnect_0_M00_AXI_ARID),\n        .M00_AXI_arlen(axi_interconnect_0_M00_AXI_ARLEN),\n        .M00_AXI_arlock(axi_interconnect_0_M00_AXI_ARLOCK),\n        .M00_AXI_arprot(axi_interconnect_0_M00_AXI_ARPROT),\n        .M00_AXI_arqos(axi_interconnect_0_M00_AXI_ARQOS),\n        .M00_AXI_arready(axi_interconnect_0_M00_AXI_ARREADY),\n        .M00_AXI_arregion(axi_interconnect_0_M00_AXI_ARREGION),\n        .M00_AXI_arsize(axi_interconnect_0_M00_AXI_ARSIZE),\n        .M00_AXI_arvalid(axi_interconnect_0_M00_AXI_ARVALID),\n        .M00_AXI_awaddr(axi_interconnect_0_M00_AXI_AWADDR),\n        .M00_AXI_awburst(axi_interconnect_0_M00_AXI_AWBURST),\n        .M00_AXI_awcache(axi_interconnect_0_M00_AXI_AWCACHE),\n        .M00_AXI_awid(axi_interconnect_0_M00_AXI_AWID),\n        .M00_AXI_awlen(axi_interconnect_0_M00_AXI_AWLEN),\n        .M00_AXI_awlock(axi_interconnect_0_M00_AXI_AWLOCK),\n        .M00_AXI_awprot(axi_interconnect_0_M00_AXI_AWPROT),\n        .M00_AXI_awqos(axi_interconnect_0_M00_AXI_AWQOS),\n        .M00_AXI_awready(axi_interconnect_0_M00_AXI_AWREADY),\n        .M00_AXI_awregion(axi_interconnect_0_M00_AXI_AWREGION),\n        .M00_AXI_awsize(axi_interconnect_0_M00_AXI_AWSIZE),\n        .M00_AXI_awvalid(axi_interconnect_0_M00_AXI_AWVALID),\n        .M00_AXI_bid(axi_interconnect_0_M00_AXI_BID),\n        .M00_AXI_bready(axi_interconnect_0_M00_AXI_BREADY),\n        .M00_AXI_bresp(axi_interconnect_0_M00_AXI_BRESP),\n        .M00_AXI_bvalid(axi_interconnect_0_M00_AXI_BVALID),\n        .M00_AXI_rdata(axi_interconnect_0_M00_AXI_RDATA),\n        .M00_AXI_rid(axi_interconnect_0_M00_AXI_RID),\n        .M00_AXI_rlast(axi_interconnect_0_M00_AXI_RLAST),\n        .M00_AXI_rready(axi_interconnect_0_M00_AXI_RREADY),\n        .M00_AXI_rresp(axi_interconnect_0_M00_AXI_RRESP),\n        .M00_AXI_rvalid(axi_interconnect_0_M00_AXI_RVALID),\n        .M00_AXI_wdata(axi_interconnect_0_M00_AXI_WDATA),\n        .M00_AXI_wlast(axi_interconnect_0_M00_AXI_WLAST),\n        .M00_AXI_wready(axi_interconnect_0_M00_AXI_WREADY),\n        .M00_AXI_wstrb(axi_interconnect_0_M00_AXI_WSTRB),\n        .M00_AXI_wvalid(axi_interconnect_0_M00_AXI_WVALID),\n        .M01_ACLK(ACLK_1),\n        .M01_ARESETN(ARESETN_1),\n        .M01_AXI_araddr(axi_interconnect_0_M01_AXI_ARADDR),\n        .M01_AXI_arburst(axi_interconnect_0_M01_AXI_ARBURST),\n        .M01_AXI_arcache(axi_interconnect_0_M01_AXI_ARCACHE),\n        .M01_AXI_arid(axi_interconnect_0_M01_AXI_ARID),\n        .M01_AXI_arlen(axi_interconnect_0_M01_AXI_ARLEN),\n        .M01_AXI_arlock(axi_interconnect_0_M01_AXI_ARLOCK),\n        .M01_AXI_arprot(axi_interconnect_0_M01_AXI_ARPROT),\n        .M01_AXI_arqos(axi_interconnect_0_M01_AXI_ARQOS),\n        .M01_AXI_arready(axi_interconnect_0_M01_AXI_ARREADY),\n        .M01_AXI_arregion(axi_interconnect_0_M01_AXI_ARREGION),\n        .M01_AXI_arsize(axi_interconnect_0_M01_AXI_ARSIZE),\n        .M01_AXI_arvalid(axi_interconnect_0_M01_AXI_ARVALID),\n        .M01_AXI_awaddr(axi_interconnect_0_M01_AXI_AWADDR),\n        .M01_AXI_awburst(axi_interconnect_0_M01_AXI_AWBURST),\n        .M01_AXI_awcache(axi_interconnect_0_M01_AXI_AWCACHE),\n        .M01_AXI_awid(axi_interconnect_0_M01_AXI_AWID),\n        .M01_AXI_awlen(axi_interconnect_0_M01_AXI_AWLEN),\n        .M01_AXI_awlock(axi_interconnect_0_M01_AXI_AWLOCK),\n        .M01_AXI_awprot(axi_interconnect_0_M01_AXI_AWPROT),\n        .M01_AXI_awqos(axi_interconnect_0_M01_AXI_AWQOS),\n        .M01_AXI_awready(axi_interconnect_0_M01_AXI_AWREADY),\n        .M01_AXI_awregion(axi_interconnect_0_M01_AXI_AWREGION),\n        .M01_AXI_awsize(axi_interconnect_0_M01_AXI_AWSIZE),\n        .M01_AXI_awvalid(axi_interconnect_0_M01_AXI_AWVALID),\n        .M01_AXI_bid(axi_interconnect_0_M01_AXI_BID),\n        .M01_AXI_bready(axi_interconnect_0_M01_AXI_BREADY),\n        .M01_AXI_bresp(axi_interconnect_0_M01_AXI_BRESP),\n        .M01_AXI_bvalid(axi_interconnect_0_M01_AXI_BVALID),\n        .M01_AXI_rdata(axi_interconnect_0_M01_AXI_RDATA),\n        .M01_AXI_rid(axi_interconnect_0_M01_AXI_RID),\n        .M01_AXI_rlast(axi_interconnect_0_M01_AXI_RLAST),\n        .M01_AXI_rready(axi_interconnect_0_M01_AXI_RREADY),\n        .M01_AXI_rresp(axi_interconnect_0_M01_AXI_RRESP),\n        .M01_AXI_rvalid(axi_interconnect_0_M01_AXI_RVALID),\n        .M01_AXI_wdata(axi_interconnect_0_M01_AXI_WDATA),\n        .M01_AXI_wlast(axi_interconnect_0_M01_AXI_WLAST),\n        .M01_AXI_wready(axi_interconnect_0_M01_AXI_WREADY),\n        .M01_AXI_wstrb(axi_interconnect_0_M01_AXI_WSTRB),\n        .M01_AXI_wvalid(axi_interconnect_0_M01_AXI_WVALID),\n        .M02_ACLK(ACLK_1),\n        .M02_ARESETN(ARESETN_1),\n        .M02_AXI_araddr(axi_interconnect_0_M02_AXI_ARADDR),\n        .M02_AXI_arburst(axi_interconnect_0_M02_AXI_ARBURST),\n        .M02_AXI_arcache(axi_interconnect_0_M02_AXI_ARCACHE),\n        .M02_AXI_arid(axi_interconnect_0_M02_AXI_ARID),\n        .M02_AXI_arlen(axi_interconnect_0_M02_AXI_ARLEN),\n        .M02_AXI_arlock(axi_interconnect_0_M02_AXI_ARLOCK),\n        .M02_AXI_arprot(axi_interconnect_0_M02_AXI_ARPROT),\n        .M02_AXI_arqos(axi_interconnect_0_M02_AXI_ARQOS),\n        .M02_AXI_arready(axi_interconnect_0_M02_AXI_ARREADY),\n        .M02_AXI_arregion(axi_interconnect_0_M02_AXI_ARREGION),\n        .M02_AXI_arsize(axi_interconnect_0_M02_AXI_ARSIZE),\n        .M02_AXI_arvalid(axi_interconnect_0_M02_AXI_ARVALID),\n        .M02_AXI_awaddr(axi_interconnect_0_M02_AXI_AWADDR),\n        .M02_AXI_awburst(axi_interconnect_0_M02_AXI_AWBURST),\n        .M02_AXI_awcache(axi_interconnect_0_M02_AXI_AWCACHE),\n        .M02_AXI_awid(axi_interconnect_0_M02_AXI_AWID),\n        .M02_AXI_awlen(axi_interconnect_0_M02_AXI_AWLEN),\n        .M02_AXI_awlock(axi_interconnect_0_M02_AXI_AWLOCK),\n        .M02_AXI_awprot(axi_interconnect_0_M02_AXI_AWPROT),\n        .M02_AXI_awqos(axi_interconnect_0_M02_AXI_AWQOS),\n        .M02_AXI_awready(axi_interconnect_0_M02_AXI_AWREADY),\n        .M02_AXI_awregion(axi_interconnect_0_M02_AXI_AWREGION),\n        .M02_AXI_awsize(axi_interconnect_0_M02_AXI_AWSIZE),\n        .M02_AXI_awvalid(axi_interconnect_0_M02_AXI_AWVALID),\n        .M02_AXI_bid(axi_interconnect_0_M02_AXI_BID),\n        .M02_AXI_bready(axi_interconnect_0_M02_AXI_BREADY),\n        .M02_AXI_bresp(axi_interconnect_0_M02_AXI_BRESP),\n        .M02_AXI_bvalid(axi_interconnect_0_M02_AXI_BVALID),\n        .M02_AXI_rdata(axi_interconnect_0_M02_AXI_RDATA),\n        .M02_AXI_rid(axi_interconnect_0_M02_AXI_RID),\n        .M02_AXI_rlast(axi_interconnect_0_M02_AXI_RLAST),\n        .M02_AXI_rready(axi_interconnect_0_M02_AXI_RREADY),\n        .M02_AXI_rresp(axi_interconnect_0_M02_AXI_RRESP),\n        .M02_AXI_rvalid(axi_interconnect_0_M02_AXI_RVALID),\n        .M02_AXI_wdata(axi_interconnect_0_M02_AXI_WDATA),\n        .M02_AXI_wlast(axi_interconnect_0_M02_AXI_WLAST),\n        .M02_AXI_wready(axi_interconnect_0_M02_AXI_WREADY),\n        .M02_AXI_wstrb(axi_interconnect_0_M02_AXI_WSTRB),\n        .M02_AXI_wvalid(axi_interconnect_0_M02_AXI_WVALID),\n        .M03_ACLK(ACLK_1),\n        .M03_ARESETN(ARESETN_1),\n        .M03_AXI_araddr(axi_interconnect_0_M03_AXI_ARADDR),\n        .M03_AXI_arburst(axi_interconnect_0_M03_AXI_ARBURST),\n        .M03_AXI_arcache(axi_interconnect_0_M03_AXI_ARCACHE),\n        .M03_AXI_arid(axi_interconnect_0_M03_AXI_ARID),\n        .M03_AXI_arlen(axi_interconnect_0_M03_AXI_ARLEN),\n        .M03_AXI_arlock(axi_interconnect_0_M03_AXI_ARLOCK),\n        .M03_AXI_arprot(axi_interconnect_0_M03_AXI_ARPROT),\n        .M03_AXI_arqos(axi_interconnect_0_M03_AXI_ARQOS),\n        .M03_AXI_arready(axi_interconnect_0_M03_AXI_ARREADY),\n        .M03_AXI_arregion(axi_interconnect_0_M03_AXI_ARREGION),\n        .M03_AXI_arsize(axi_interconnect_0_M03_AXI_ARSIZE),\n        .M03_AXI_arvalid(axi_interconnect_0_M03_AXI_ARVALID),\n        .M03_AXI_awaddr(axi_interconnect_0_M03_AXI_AWADDR),\n        .M03_AXI_awburst(axi_interconnect_0_M03_AXI_AWBURST),\n        .M03_AXI_awcache(axi_interconnect_0_M03_AXI_AWCACHE),\n        .M03_AXI_awid(axi_interconnect_0_M03_AXI_AWID),\n        .M03_AXI_awlen(axi_interconnect_0_M03_AXI_AWLEN),\n        .M03_AXI_awlock(axi_interconnect_0_M03_AXI_AWLOCK),\n        .M03_AXI_awprot(axi_interconnect_0_M03_AXI_AWPROT),\n        .M03_AXI_awqos(axi_interconnect_0_M03_AXI_AWQOS),\n        .M03_AXI_awready(axi_interconnect_0_M03_AXI_AWREADY),\n        .M03_AXI_awregion(axi_interconnect_0_M03_AXI_AWREGION),\n        .M03_AXI_awsize(axi_interconnect_0_M03_AXI_AWSIZE),\n        .M03_AXI_awvalid(axi_interconnect_0_M03_AXI_AWVALID),\n        .M03_AXI_bid(axi_interconnect_0_M03_AXI_BID),\n        .M03_AXI_bready(axi_interconnect_0_M03_AXI_BREADY),\n        .M03_AXI_bresp(axi_interconnect_0_M03_AXI_BRESP),\n        .M03_AXI_bvalid(axi_interconnect_0_M03_AXI_BVALID),\n        .M03_AXI_rdata(axi_interconnect_0_M03_AXI_RDATA),\n        .M03_AXI_rid(axi_interconnect_0_M03_AXI_RID),\n        .M03_AXI_rlast(axi_interconnect_0_M03_AXI_RLAST),\n        .M03_AXI_rready(axi_interconnect_0_M03_AXI_RREADY),\n        .M03_AXI_rresp(axi_interconnect_0_M03_AXI_RRESP),\n        .M03_AXI_rvalid(axi_interconnect_0_M03_AXI_RVALID),\n        .M03_AXI_wdata(axi_interconnect_0_M03_AXI_WDATA),\n        .M03_AXI_wlast(axi_interconnect_0_M03_AXI_WLAST),\n        .M03_AXI_wready(axi_interconnect_0_M03_AXI_WREADY),\n        .M03_AXI_wstrb(axi_interconnect_0_M03_AXI_WSTRB),\n        .M03_AXI_wvalid(axi_interconnect_0_M03_AXI_WVALID),\n        .S00_ACLK(ACLK_1),\n        .S00_ARESETN(ARESETN_1),\n        .S00_AXI_araddr(S00_AXI_1_ARADDR),\n        .S00_AXI_arburst(S00_AXI_1_ARBURST),\n        .S00_AXI_arcache(S00_AXI_1_ARCACHE),\n        .S00_AXI_arid(S00_AXI_1_ARID),\n        .S00_AXI_arlen(S00_AXI_1_ARLEN),\n        .S00_AXI_arlock(S00_AXI_1_ARLOCK),\n        .S00_AXI_arprot(S00_AXI_1_ARPROT),\n        .S00_AXI_arqos(S00_AXI_1_ARQOS),\n        .S00_AXI_arready(S00_AXI_1_ARREADY),\n        .S00_AXI_arregion(S00_AXI_1_ARREGION),\n        .S00_AXI_arsize(S00_AXI_1_ARSIZE),\n        .S00_AXI_arvalid(S00_AXI_1_ARVALID),\n        .S00_AXI_awaddr(S00_AXI_1_AWADDR),\n        .S00_AXI_awburst(S00_AXI_1_AWBURST),\n        .S00_AXI_awcache(S00_AXI_1_AWCACHE),\n        .S00_AXI_awid(S00_AXI_1_AWID),\n        .S00_AXI_awlen(S00_AXI_1_AWLEN),\n        .S00_AXI_awlock(S00_AXI_1_AWLOCK),\n        .S00_AXI_awprot(S00_AXI_1_AWPROT),\n        .S00_AXI_awqos(S00_AXI_1_AWQOS),\n        .S00_AXI_awready(S00_AXI_1_AWREADY),\n        .S00_AXI_awregion(S00_AXI_1_AWREGION),\n        .S00_AXI_awsize(S00_AXI_1_AWSIZE),\n        .S00_AXI_awvalid(S00_AXI_1_AWVALID),\n        .S00_AXI_bid(S00_AXI_1_BID),\n        .S00_AXI_bready(S00_AXI_1_BREADY),\n        .S00_AXI_bresp(S00_AXI_1_BRESP),\n        .S00_AXI_bvalid(S00_AXI_1_BVALID),\n        .S00_AXI_rdata(S00_AXI_1_RDATA),\n        .S00_AXI_rid(S00_AXI_1_RID),\n        .S00_AXI_rlast(S00_AXI_1_RLAST),\n        .S00_AXI_rready(S00_AXI_1_RREADY),\n        .S00_AXI_rresp(S00_AXI_1_RRESP),\n        .S00_AXI_rvalid(S00_AXI_1_RVALID),\n        .S00_AXI_wdata(S00_AXI_1_WDATA),\n        .S00_AXI_wlast(S00_AXI_1_WLAST),\n        .S00_AXI_wready(S00_AXI_1_WREADY),\n        .S00_AXI_wstrb(S00_AXI_1_WSTRB),\n        .S00_AXI_wvalid(S00_AXI_1_WVALID),\n        .S01_ACLK(ACLK_1),\n        .S01_ARESETN(ARESETN_1),\n        .S01_AXI_araddr(S01_AXI_1_ARADDR),\n        .S01_AXI_arburst(S01_AXI_1_ARBURST),\n        .S01_AXI_arcache(S01_AXI_1_ARCACHE),\n        .S01_AXI_arid(S01_AXI_1_ARID),\n        .S01_AXI_arlen(S01_AXI_1_ARLEN),\n        .S01_AXI_arlock(S01_AXI_1_ARLOCK),\n        .S01_AXI_arprot(S01_AXI_1_ARPROT),\n        .S01_AXI_arqos(S01_AXI_1_ARQOS),\n        .S01_AXI_arready(S01_AXI_1_ARREADY),\n        .S01_AXI_arregion(S01_AXI_1_ARREGION),\n        .S01_AXI_arsize(S01_AXI_1_ARSIZE),\n        .S01_AXI_arvalid(S01_AXI_1_ARVALID),\n        .S01_AXI_awaddr(S01_AXI_1_AWADDR),\n        .S01_AXI_awburst(S01_AXI_1_AWBURST),\n        .S01_AXI_awcache(S01_AXI_1_AWCACHE),\n        .S01_AXI_awid(S01_AXI_1_AWID),\n        .S01_AXI_awlen(S01_AXI_1_AWLEN),\n        .S01_AXI_awlock(S01_AXI_1_AWLOCK),\n        .S01_AXI_awprot(S01_AXI_1_AWPROT),\n        .S01_AXI_awqos(S01_AXI_1_AWQOS),\n        .S01_AXI_awready(S01_AXI_1_AWREADY),\n        .S01_AXI_awregion(S01_AXI_1_AWREGION),\n        .S01_AXI_awsize(S01_AXI_1_AWSIZE),\n        .S01_AXI_awvalid(S01_AXI_1_AWVALID),\n        .S01_AXI_bid(S01_AXI_1_BID),\n        .S01_AXI_bready(S01_AXI_1_BREADY),\n        .S01_AXI_bresp(S01_AXI_1_BRESP),\n        .S01_AXI_bvalid(S01_AXI_1_BVALID),\n        .S01_AXI_rdata(S01_AXI_1_RDATA),\n        .S01_AXI_rid(S01_AXI_1_RID),\n        .S01_AXI_rlast(S01_AXI_1_RLAST),\n        .S01_AXI_rready(S01_AXI_1_RREADY),\n        .S01_AXI_rresp(S01_AXI_1_RRESP),\n        .S01_AXI_rvalid(S01_AXI_1_RVALID),\n        .S01_AXI_wdata(S01_AXI_1_WDATA),\n        .S01_AXI_wlast(S01_AXI_1_WLAST),\n        .S01_AXI_wready(S01_AXI_1_WREADY),\n        .S01_AXI_wstrb(S01_AXI_1_WSTRB),\n        .S01_AXI_wvalid(S01_AXI_1_WVALID));\nendmodule\n\nmodule cl_axi_interconnect_axi_interconnect_0_0\n   (ACLK,\n    ARESETN,\n    M00_ACLK,\n    M00_ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_ACLK,\n    M01_ARESETN,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_ACLK,\n    M02_ARESETN,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_ACLK,\n    M03_ARESETN,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_ACLK,\n    S00_ARESETN,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_ACLK,\n    S01_ARESETN,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  input ACLK;\n  input ARESETN;\n  input M00_ACLK;\n  input M00_ARESETN;\n  output [63:0]M00_AXI_araddr;\n  output [1:0]M00_AXI_arburst;\n  output [3:0]M00_AXI_arcache;\n  output [6:0]M00_AXI_arid;\n  output [7:0]M00_AXI_arlen;\n  output [0:0]M00_AXI_arlock;\n  output [2:0]M00_AXI_arprot;\n  output [3:0]M00_AXI_arqos;\n  input M00_AXI_arready;\n  output [3:0]M00_AXI_arregion;\n  output [2:0]M00_AXI_arsize;\n  output M00_AXI_arvalid;\n  output [63:0]M00_AXI_awaddr;\n  output [1:0]M00_AXI_awburst;\n  output [3:0]M00_AXI_awcache;\n  output [6:0]M00_AXI_awid;\n  output [7:0]M00_AXI_awlen;\n  output [0:0]M00_AXI_awlock;\n  output [2:0]M00_AXI_awprot;\n  output [3:0]M00_AXI_awqos;\n  input M00_AXI_awready;\n  output [3:0]M00_AXI_awregion;\n  output [2:0]M00_AXI_awsize;\n  output M00_AXI_awvalid;\n  input [6:0]M00_AXI_bid;\n  output M00_AXI_bready;\n  input [1:0]M00_AXI_bresp;\n  input M00_AXI_bvalid;\n  input [511:0]M00_AXI_rdata;\n  input [6:0]M00_AXI_rid;\n  input M00_AXI_rlast;\n  output M00_AXI_rready;\n  input [1:0]M00_AXI_rresp;\n  input M00_AXI_rvalid;\n  output [511:0]M00_AXI_wdata;\n  output M00_AXI_wlast;\n  input M00_AXI_wready;\n  output [63:0]M00_AXI_wstrb;\n  output M00_AXI_wvalid;\n  input M01_ACLK;\n  input M01_ARESETN;\n  output [63:0]M01_AXI_araddr;\n  output [1:0]M01_AXI_arburst;\n  output [3:0]M01_AXI_arcache;\n  output [6:0]M01_AXI_arid;\n  output [7:0]M01_AXI_arlen;\n  output [0:0]M01_AXI_arlock;\n  output [2:0]M01_AXI_arprot;\n  output [3:0]M01_AXI_arqos;\n  input M01_AXI_arready;\n  output [3:0]M01_AXI_arregion;\n  output [2:0]M01_AXI_arsize;\n  output M01_AXI_arvalid;\n  output [63:0]M01_AXI_awaddr;\n  output [1:0]M01_AXI_awburst;\n  output [3:0]M01_AXI_awcache;\n  output [6:0]M01_AXI_awid;\n  output [7:0]M01_AXI_awlen;\n  output [0:0]M01_AXI_awlock;\n  output [2:0]M01_AXI_awprot;\n  output [3:0]M01_AXI_awqos;\n  input M01_AXI_awready;\n  output [3:0]M01_AXI_awregion;\n  output [2:0]M01_AXI_awsize;\n  output M01_AXI_awvalid;\n  input [6:0]M01_AXI_bid;\n  output M01_AXI_bready;\n  input [1:0]M01_AXI_bresp;\n  input M01_AXI_bvalid;\n  input [511:0]M01_AXI_rdata;\n  input [6:0]M01_AXI_rid;\n  input M01_AXI_rlast;\n  output M01_AXI_rready;\n  input [1:0]M01_AXI_rresp;\n  input M01_AXI_rvalid;\n  output [511:0]M01_AXI_wdata;\n  output M01_AXI_wlast;\n  input M01_AXI_wready;\n  output [63:0]M01_AXI_wstrb;\n  output M01_AXI_wvalid;\n  input M02_ACLK;\n  input M02_ARESETN;\n  output [63:0]M02_AXI_araddr;\n  output [1:0]M02_AXI_arburst;\n  output [3:0]M02_AXI_arcache;\n  output [6:0]M02_AXI_arid;\n  output [7:0]M02_AXI_arlen;\n  output [0:0]M02_AXI_arlock;\n  output [2:0]M02_AXI_arprot;\n  output [3:0]M02_AXI_arqos;\n  input M02_AXI_arready;\n  output [3:0]M02_AXI_arregion;\n  output [2:0]M02_AXI_arsize;\n  output M02_AXI_arvalid;\n  output [63:0]M02_AXI_awaddr;\n  output [1:0]M02_AXI_awburst;\n  output [3:0]M02_AXI_awcache;\n  output [6:0]M02_AXI_awid;\n  output [7:0]M02_AXI_awlen;\n  output [0:0]M02_AXI_awlock;\n  output [2:0]M02_AXI_awprot;\n  output [3:0]M02_AXI_awqos;\n  input M02_AXI_awready;\n  output [3:0]M02_AXI_awregion;\n  output [2:0]M02_AXI_awsize;\n  output M02_AXI_awvalid;\n  input [6:0]M02_AXI_bid;\n  output M02_AXI_bready;\n  input [1:0]M02_AXI_bresp;\n  input M02_AXI_bvalid;\n  input [511:0]M02_AXI_rdata;\n  input [6:0]M02_AXI_rid;\n  input M02_AXI_rlast;\n  output M02_AXI_rready;\n  input [1:0]M02_AXI_rresp;\n  input M02_AXI_rvalid;\n  output [511:0]M02_AXI_wdata;\n  output M02_AXI_wlast;\n  input M02_AXI_wready;\n  output [63:0]M02_AXI_wstrb;\n  output M02_AXI_wvalid;\n  input M03_ACLK;\n  input M03_ARESETN;\n  output [63:0]M03_AXI_araddr;\n  output [1:0]M03_AXI_arburst;\n  output [3:0]M03_AXI_arcache;\n  output [6:0]M03_AXI_arid;\n  output [7:0]M03_AXI_arlen;\n  output [0:0]M03_AXI_arlock;\n  output [2:0]M03_AXI_arprot;\n  output [3:0]M03_AXI_arqos;\n  input M03_AXI_arready;\n  output [3:0]M03_AXI_arregion;\n  output [2:0]M03_AXI_arsize;\n  output M03_AXI_arvalid;\n  output [63:0]M03_AXI_awaddr;\n  output [1:0]M03_AXI_awburst;\n  output [3:0]M03_AXI_awcache;\n  output [6:0]M03_AXI_awid;\n  output [7:0]M03_AXI_awlen;\n  output [0:0]M03_AXI_awlock;\n  output [2:0]M03_AXI_awprot;\n  output [3:0]M03_AXI_awqos;\n  input M03_AXI_awready;\n  output [3:0]M03_AXI_awregion;\n  output [2:0]M03_AXI_awsize;\n  output M03_AXI_awvalid;\n  input [6:0]M03_AXI_bid;\n  output M03_AXI_bready;\n  input [1:0]M03_AXI_bresp;\n  input M03_AXI_bvalid;\n  input [511:0]M03_AXI_rdata;\n  input [6:0]M03_AXI_rid;\n  input M03_AXI_rlast;\n  output M03_AXI_rready;\n  input [1:0]M03_AXI_rresp;\n  input M03_AXI_rvalid;\n  output [511:0]M03_AXI_wdata;\n  output M03_AXI_wlast;\n  input M03_AXI_wready;\n  output [63:0]M03_AXI_wstrb;\n  output M03_AXI_wvalid;\n  input S00_ACLK;\n  input S00_ARESETN;\n  input [63:0]S00_AXI_araddr;\n  input [1:0]S00_AXI_arburst;\n  input [3:0]S00_AXI_arcache;\n  input [5:0]S00_AXI_arid;\n  input [7:0]S00_AXI_arlen;\n  input [0:0]S00_AXI_arlock;\n  input [2:0]S00_AXI_arprot;\n  input [3:0]S00_AXI_arqos;\n  output S00_AXI_arready;\n  input [3:0]S00_AXI_arregion;\n  input [2:0]S00_AXI_arsize;\n  input S00_AXI_arvalid;\n  input [63:0]S00_AXI_awaddr;\n  input [1:0]S00_AXI_awburst;\n  input [3:0]S00_AXI_awcache;\n  input [5:0]S00_AXI_awid;\n  input [7:0]S00_AXI_awlen;\n  input [0:0]S00_AXI_awlock;\n  input [2:0]S00_AXI_awprot;\n  input [3:0]S00_AXI_awqos;\n  output S00_AXI_awready;\n  input [3:0]S00_AXI_awregion;\n  input [2:0]S00_AXI_awsize;\n  input S00_AXI_awvalid;\n  output [5:0]S00_AXI_bid;\n  input S00_AXI_bready;\n  output [1:0]S00_AXI_bresp;\n  output S00_AXI_bvalid;\n  output [511:0]S00_AXI_rdata;\n  output [5:0]S00_AXI_rid;\n  output S00_AXI_rlast;\n  input S00_AXI_rready;\n  output [1:0]S00_AXI_rresp;\n  output S00_AXI_rvalid;\n  input [511:0]S00_AXI_wdata;\n  input S00_AXI_wlast;\n  output S00_AXI_wready;\n  input [63:0]S00_AXI_wstrb;\n  input S00_AXI_wvalid;\n  input S01_ACLK;\n  input S01_ARESETN;\n  input [63:0]S01_AXI_araddr;\n  input [1:0]S01_AXI_arburst;\n  input [3:0]S01_AXI_arcache;\n  input [5:0]S01_AXI_arid;\n  input [7:0]S01_AXI_arlen;\n  input [0:0]S01_AXI_arlock;\n  input [2:0]S01_AXI_arprot;\n  input [3:0]S01_AXI_arqos;\n  output S01_AXI_arready;\n  input [3:0]S01_AXI_arregion;\n  input [2:0]S01_AXI_arsize;\n  input S01_AXI_arvalid;\n  input [63:0]S01_AXI_awaddr;\n  input [1:0]S01_AXI_awburst;\n  input [3:0]S01_AXI_awcache;\n  input [5:0]S01_AXI_awid;\n  input [7:0]S01_AXI_awlen;\n  input [0:0]S01_AXI_awlock;\n  input [2:0]S01_AXI_awprot;\n  input [3:0]S01_AXI_awqos;\n  output S01_AXI_awready;\n  input [3:0]S01_AXI_awregion;\n  input [2:0]S01_AXI_awsize;\n  input S01_AXI_awvalid;\n  output [5:0]S01_AXI_bid;\n  input S01_AXI_bready;\n  output [1:0]S01_AXI_bresp;\n  output S01_AXI_bvalid;\n  output [511:0]S01_AXI_rdata;\n  output [5:0]S01_AXI_rid;\n  output S01_AXI_rlast;\n  input S01_AXI_rready;\n  output [1:0]S01_AXI_rresp;\n  output S01_AXI_rvalid;\n  input [511:0]S01_AXI_wdata;\n  input S01_AXI_wlast;\n  output S01_AXI_wready;\n  input [63:0]S01_AXI_wstrb;\n  input S01_AXI_wvalid;\n\n  wire axi_interconnect_0_ACLK_net;\n  wire axi_interconnect_0_ARESETN_net;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_ARADDR;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_ARBURST;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARCACHE;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_ARID;\n  wire [7:0]axi_interconnect_0_to_s00_couplers_ARLEN;\n  wire [0:0]axi_interconnect_0_to_s00_couplers_ARLOCK;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_ARPROT;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARQOS;\n  wire axi_interconnect_0_to_s00_couplers_ARREADY;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARREGION;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_ARSIZE;\n  wire axi_interconnect_0_to_s00_couplers_ARVALID;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_AWADDR;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_AWBURST;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWCACHE;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_AWID;\n  wire [7:0]axi_interconnect_0_to_s00_couplers_AWLEN;\n  wire [0:0]axi_interconnect_0_to_s00_couplers_AWLOCK;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_AWPROT;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWQOS;\n  wire axi_interconnect_0_to_s00_couplers_AWREADY;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWREGION;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_AWSIZE;\n  wire axi_interconnect_0_to_s00_couplers_AWVALID;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_BID;\n  wire axi_interconnect_0_to_s00_couplers_BREADY;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_BRESP;\n  wire axi_interconnect_0_to_s00_couplers_BVALID;\n  wire [511:0]axi_interconnect_0_to_s00_couplers_RDATA;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_RID;\n  wire axi_interconnect_0_to_s00_couplers_RLAST;\n  wire axi_interconnect_0_to_s00_couplers_RREADY;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_RRESP;\n  wire axi_interconnect_0_to_s00_couplers_RVALID;\n  wire [511:0]axi_interconnect_0_to_s00_couplers_WDATA;\n  wire axi_interconnect_0_to_s00_couplers_WLAST;\n  wire axi_interconnect_0_to_s00_couplers_WREADY;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_WSTRB;\n  wire axi_interconnect_0_to_s00_couplers_WVALID;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_ARADDR;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_ARBURST;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARCACHE;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_ARID;\n  wire [7:0]axi_interconnect_0_to_s01_couplers_ARLEN;\n  wire [0:0]axi_interconnect_0_to_s01_couplers_ARLOCK;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_ARPROT;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARQOS;\n  wire axi_interconnect_0_to_s01_couplers_ARREADY;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARREGION;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_ARSIZE;\n  wire axi_interconnect_0_to_s01_couplers_ARVALID;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_AWADDR;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_AWBURST;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWCACHE;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_AWID;\n  wire [7:0]axi_interconnect_0_to_s01_couplers_AWLEN;\n  wire [0:0]axi_interconnect_0_to_s01_couplers_AWLOCK;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_AWPROT;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWQOS;\n  wire axi_interconnect_0_to_s01_couplers_AWREADY;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWREGION;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_AWSIZE;\n  wire axi_interconnect_0_to_s01_couplers_AWVALID;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_BID;\n  wire axi_interconnect_0_to_s01_couplers_BREADY;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_BRESP;\n  wire axi_interconnect_0_to_s01_couplers_BVALID;\n  wire [511:0]axi_interconnect_0_to_s01_couplers_RDATA;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_RID;\n  wire axi_interconnect_0_to_s01_couplers_RLAST;\n  wire axi_interconnect_0_to_s01_couplers_RREADY;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_RRESP;\n  wire axi_interconnect_0_to_s01_couplers_RVALID;\n  wire [511:0]axi_interconnect_0_to_s01_couplers_WDATA;\n  wire axi_interconnect_0_to_s01_couplers_WLAST;\n  wire axi_interconnect_0_to_s01_couplers_WREADY;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_WSTRB;\n  wire axi_interconnect_0_to_s01_couplers_WVALID;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m00_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m00_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARQOS;\n  wire m00_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m00_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m00_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m00_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWQOS;\n  wire m00_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m00_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_BID;\n  wire m00_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_BRESP;\n  wire m00_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m00_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_RID;\n  wire m00_couplers_to_axi_interconnect_0_RLAST;\n  wire m00_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_RRESP;\n  wire m00_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m00_couplers_to_axi_interconnect_0_WDATA;\n  wire m00_couplers_to_axi_interconnect_0_WLAST;\n  wire m00_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_WSTRB;\n  wire m00_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m01_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m01_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARQOS;\n  wire m01_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m01_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m01_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m01_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWQOS;\n  wire m01_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m01_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_BID;\n  wire m01_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_BRESP;\n  wire m01_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m01_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_RID;\n  wire m01_couplers_to_axi_interconnect_0_RLAST;\n  wire m01_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_RRESP;\n  wire m01_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m01_couplers_to_axi_interconnect_0_WDATA;\n  wire m01_couplers_to_axi_interconnect_0_WLAST;\n  wire m01_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_WSTRB;\n  wire m01_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m02_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m02_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARQOS;\n  wire m02_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m02_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m02_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m02_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWQOS;\n  wire m02_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m02_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_BID;\n  wire m02_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_BRESP;\n  wire m02_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m02_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_RID;\n  wire m02_couplers_to_axi_interconnect_0_RLAST;\n  wire m02_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_RRESP;\n  wire m02_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m02_couplers_to_axi_interconnect_0_WDATA;\n  wire m02_couplers_to_axi_interconnect_0_WLAST;\n  wire m02_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_WSTRB;\n  wire m02_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m03_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m03_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARQOS;\n  wire m03_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m03_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m03_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m03_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWQOS;\n  wire m03_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m03_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_BID;\n  wire m03_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_BRESP;\n  wire m03_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m03_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_RID;\n  wire m03_couplers_to_axi_interconnect_0_RLAST;\n  wire m03_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_RRESP;\n  wire m03_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m03_couplers_to_axi_interconnect_0_WDATA;\n  wire m03_couplers_to_axi_interconnect_0_WLAST;\n  wire m03_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_WSTRB;\n  wire m03_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]s00_couplers_to_xbar_ARADDR;\n  wire [1:0]s00_couplers_to_xbar_ARBURST;\n  wire [3:0]s00_couplers_to_xbar_ARCACHE;\n  wire [5:0]s00_couplers_to_xbar_ARID;\n  wire [7:0]s00_couplers_to_xbar_ARLEN;\n  wire [0:0]s00_couplers_to_xbar_ARLOCK;\n  wire [2:0]s00_couplers_to_xbar_ARPROT;\n  wire [3:0]s00_couplers_to_xbar_ARQOS;\n  wire [0:0]s00_couplers_to_xbar_ARREADY;\n  wire [2:0]s00_couplers_to_xbar_ARSIZE;\n  wire s00_couplers_to_xbar_ARVALID;\n  wire [63:0]s00_couplers_to_xbar_AWADDR;\n  wire [1:0]s00_couplers_to_xbar_AWBURST;\n  wire [3:0]s00_couplers_to_xbar_AWCACHE;\n  wire [5:0]s00_couplers_to_xbar_AWID;\n  wire [7:0]s00_couplers_to_xbar_AWLEN;\n  wire [0:0]s00_couplers_to_xbar_AWLOCK;\n  wire [2:0]s00_couplers_to_xbar_AWPROT;\n  wire [3:0]s00_couplers_to_xbar_AWQOS;\n  wire [0:0]s00_couplers_to_xbar_AWREADY;\n  wire [2:0]s00_couplers_to_xbar_AWSIZE;\n  wire s00_couplers_to_xbar_AWVALID;\n  wire [6:0]s00_couplers_to_xbar_BID;\n  wire s00_couplers_to_xbar_BREADY;\n  wire [1:0]s00_couplers_to_xbar_BRESP;\n  wire [0:0]s00_couplers_to_xbar_BVALID;\n  wire [511:0]s00_couplers_to_xbar_RDATA;\n  wire [6:0]s00_couplers_to_xbar_RID;\n  wire [0:0]s00_couplers_to_xbar_RLAST;\n  wire s00_couplers_to_xbar_RREADY;\n  wire [1:0]s00_couplers_to_xbar_RRESP;\n  wire [0:0]s00_couplers_to_xbar_RVALID;\n  wire [511:0]s00_couplers_to_xbar_WDATA;\n  wire s00_couplers_to_xbar_WLAST;\n  wire [0:0]s00_couplers_to_xbar_WREADY;\n  wire [63:0]s00_couplers_to_xbar_WSTRB;\n  wire s00_couplers_to_xbar_WVALID;\n  wire [63:0]s01_couplers_to_xbar_ARADDR;\n  wire [1:0]s01_couplers_to_xbar_ARBURST;\n  wire [3:0]s01_couplers_to_xbar_ARCACHE;\n  wire [5:0]s01_couplers_to_xbar_ARID;\n  wire [7:0]s01_couplers_to_xbar_ARLEN;\n  wire [0:0]s01_couplers_to_xbar_ARLOCK;\n  wire [2:0]s01_couplers_to_xbar_ARPROT;\n  wire [3:0]s01_couplers_to_xbar_ARQOS;\n  wire [1:1]s01_couplers_to_xbar_ARREADY;\n  wire [2:0]s01_couplers_to_xbar_ARSIZE;\n  wire s01_couplers_to_xbar_ARVALID;\n  wire [63:0]s01_couplers_to_xbar_AWADDR;\n  wire [1:0]s01_couplers_to_xbar_AWBURST;\n  wire [3:0]s01_couplers_to_xbar_AWCACHE;\n  wire [5:0]s01_couplers_to_xbar_AWID;\n  wire [7:0]s01_couplers_to_xbar_AWLEN;\n  wire [0:0]s01_couplers_to_xbar_AWLOCK;\n  wire [2:0]s01_couplers_to_xbar_AWPROT;\n  wire [3:0]s01_couplers_to_xbar_AWQOS;\n  wire [1:1]s01_couplers_to_xbar_AWREADY;\n  wire [2:0]s01_couplers_to_xbar_AWSIZE;\n  wire s01_couplers_to_xbar_AWVALID;\n  wire [13:7]s01_couplers_to_xbar_BID;\n  wire s01_couplers_to_xbar_BREADY;\n  wire [3:2]s01_couplers_to_xbar_BRESP;\n  wire [1:1]s01_couplers_to_xbar_BVALID;\n  wire [1023:512]s01_couplers_to_xbar_RDATA;\n  wire [13:7]s01_couplers_to_xbar_RID;\n  wire [1:1]s01_couplers_to_xbar_RLAST;\n  wire s01_couplers_to_xbar_RREADY;\n  wire [3:2]s01_couplers_to_xbar_RRESP;\n  wire [1:1]s01_couplers_to_xbar_RVALID;\n  wire [511:0]s01_couplers_to_xbar_WDATA;\n  wire s01_couplers_to_xbar_WLAST;\n  wire [1:1]s01_couplers_to_xbar_WREADY;\n  wire [63:0]s01_couplers_to_xbar_WSTRB;\n  wire s01_couplers_to_xbar_WVALID;\n  wire [63:0]xbar_to_m00_couplers_ARADDR;\n  wire [1:0]xbar_to_m00_couplers_ARBURST;\n  wire [3:0]xbar_to_m00_couplers_ARCACHE;\n  wire [6:0]xbar_to_m00_couplers_ARID;\n  wire [7:0]xbar_to_m00_couplers_ARLEN;\n  wire [0:0]xbar_to_m00_couplers_ARLOCK;\n  wire [2:0]xbar_to_m00_couplers_ARPROT;\n  wire [3:0]xbar_to_m00_couplers_ARQOS;\n  wire xbar_to_m00_couplers_ARREADY;\n  wire [3:0]xbar_to_m00_couplers_ARREGION;\n  wire [2:0]xbar_to_m00_couplers_ARSIZE;\n  wire [0:0]xbar_to_m00_couplers_ARVALID;\n  wire [63:0]xbar_to_m00_couplers_AWADDR;\n  wire [1:0]xbar_to_m00_couplers_AWBURST;\n  wire [3:0]xbar_to_m00_couplers_AWCACHE;\n  wire [6:0]xbar_to_m00_couplers_AWID;\n  wire [7:0]xbar_to_m00_couplers_AWLEN;\n  wire [0:0]xbar_to_m00_couplers_AWLOCK;\n  wire [2:0]xbar_to_m00_couplers_AWPROT;\n  wire [3:0]xbar_to_m00_couplers_AWQOS;\n  wire xbar_to_m00_couplers_AWREADY;\n  wire [3:0]xbar_to_m00_couplers_AWREGION;\n  wire [2:0]xbar_to_m00_couplers_AWSIZE;\n  wire [0:0]xbar_to_m00_couplers_AWVALID;\n  wire [6:0]xbar_to_m00_couplers_BID;\n  wire [0:0]xbar_to_m00_couplers_BREADY;\n  wire [1:0]xbar_to_m00_couplers_BRESP;\n  wire xbar_to_m00_couplers_BVALID;\n  wire [511:0]xbar_to_m00_couplers_RDATA;\n  wire [6:0]xbar_to_m00_couplers_RID;\n  wire xbar_to_m00_couplers_RLAST;\n  wire [0:0]xbar_to_m00_couplers_RREADY;\n  wire [1:0]xbar_to_m00_couplers_RRESP;\n  wire xbar_to_m00_couplers_RVALID;\n  wire [511:0]xbar_to_m00_couplers_WDATA;\n  wire [0:0]xbar_to_m00_couplers_WLAST;\n  wire xbar_to_m00_couplers_WREADY;\n  wire [63:0]xbar_to_m00_couplers_WSTRB;\n  wire [0:0]xbar_to_m00_couplers_WVALID;\n  wire [127:64]xbar_to_m01_couplers_ARADDR;\n  wire [3:2]xbar_to_m01_couplers_ARBURST;\n  wire [7:4]xbar_to_m01_couplers_ARCACHE;\n  wire [13:7]xbar_to_m01_couplers_ARID;\n  wire [15:8]xbar_to_m01_couplers_ARLEN;\n  wire [1:1]xbar_to_m01_couplers_ARLOCK;\n  wire [5:3]xbar_to_m01_couplers_ARPROT;\n  wire [7:4]xbar_to_m01_couplers_ARQOS;\n  wire xbar_to_m01_couplers_ARREADY;\n  wire [7:4]xbar_to_m01_couplers_ARREGION;\n  wire [5:3]xbar_to_m01_couplers_ARSIZE;\n  wire [1:1]xbar_to_m01_couplers_ARVALID;\n  wire [127:64]xbar_to_m01_couplers_AWADDR;\n  wire [3:2]xbar_to_m01_couplers_AWBURST;\n  wire [7:4]xbar_to_m01_couplers_AWCACHE;\n  wire [13:7]xbar_to_m01_couplers_AWID;\n  wire [15:8]xbar_to_m01_couplers_AWLEN;\n  wire [1:1]xbar_to_m01_couplers_AWLOCK;\n  wire [5:3]xbar_to_m01_couplers_AWPROT;\n  wire [7:4]xbar_to_m01_couplers_AWQOS;\n  wire xbar_to_m01_couplers_AWREADY;\n  wire [7:4]xbar_to_m01_couplers_AWREGION;\n  wire [5:3]xbar_to_m01_couplers_AWSIZE;\n  wire [1:1]xbar_to_m01_couplers_AWVALID;\n  wire [6:0]xbar_to_m01_couplers_BID;\n  wire [1:1]xbar_to_m01_couplers_BREADY;\n  wire [1:0]xbar_to_m01_couplers_BRESP;\n  wire xbar_to_m01_couplers_BVALID;\n  wire [511:0]xbar_to_m01_couplers_RDATA;\n  wire [6:0]xbar_to_m01_couplers_RID;\n  wire xbar_to_m01_couplers_RLAST;\n  wire [1:1]xbar_to_m01_couplers_RREADY;\n  wire [1:0]xbar_to_m01_couplers_RRESP;\n  wire xbar_to_m01_couplers_RVALID;\n  wire [1023:512]xbar_to_m01_couplers_WDATA;\n  wire [1:1]xbar_to_m01_couplers_WLAST;\n  wire xbar_to_m01_couplers_WREADY;\n  wire [127:64]xbar_to_m01_couplers_WSTRB;\n  wire [1:1]xbar_to_m01_couplers_WVALID;\n  wire [191:128]xbar_to_m02_couplers_ARADDR;\n  wire [5:4]xbar_to_m02_couplers_ARBURST;\n  wire [11:8]xbar_to_m02_couplers_ARCACHE;\n  wire [20:14]xbar_to_m02_couplers_ARID;\n  wire [23:16]xbar_to_m02_couplers_ARLEN;\n  wire [2:2]xbar_to_m02_couplers_ARLOCK;\n  wire [8:6]xbar_to_m02_couplers_ARPROT;\n  wire [11:8]xbar_to_m02_couplers_ARQOS;\n  wire xbar_to_m02_couplers_ARREADY;\n  wire [11:8]xbar_to_m02_couplers_ARREGION;\n  wire [8:6]xbar_to_m02_couplers_ARSIZE;\n  wire [2:2]xbar_to_m02_couplers_ARVALID;\n  wire [191:128]xbar_to_m02_couplers_AWADDR;\n  wire [5:4]xbar_to_m02_couplers_AWBURST;\n  wire [11:8]xbar_to_m02_couplers_AWCACHE;\n  wire [20:14]xbar_to_m02_couplers_AWID;\n  wire [23:16]xbar_to_m02_couplers_AWLEN;\n  wire [2:2]xbar_to_m02_couplers_AWLOCK;\n  wire [8:6]xbar_to_m02_couplers_AWPROT;\n  wire [11:8]xbar_to_m02_couplers_AWQOS;\n  wire xbar_to_m02_couplers_AWREADY;\n  wire [11:8]xbar_to_m02_couplers_AWREGION;\n  wire [8:6]xbar_to_m02_couplers_AWSIZE;\n  wire [2:2]xbar_to_m02_couplers_AWVALID;\n  wire [6:0]xbar_to_m02_couplers_BID;\n  wire [2:2]xbar_to_m02_couplers_BREADY;\n  wire [1:0]xbar_to_m02_couplers_BRESP;\n  wire xbar_to_m02_couplers_BVALID;\n  wire [511:0]xbar_to_m02_couplers_RDATA;\n  wire [6:0]xbar_to_m02_couplers_RID;\n  wire xbar_to_m02_couplers_RLAST;\n  wire [2:2]xbar_to_m02_couplers_RREADY;\n  wire [1:0]xbar_to_m02_couplers_RRESP;\n  wire xbar_to_m02_couplers_RVALID;\n  wire [1535:1024]xbar_to_m02_couplers_WDATA;\n  wire [2:2]xbar_to_m02_couplers_WLAST;\n  wire xbar_to_m02_couplers_WREADY;\n  wire [191:128]xbar_to_m02_couplers_WSTRB;\n  wire [2:2]xbar_to_m02_couplers_WVALID;\n  wire [255:192]xbar_to_m03_couplers_ARADDR;\n  wire [7:6]xbar_to_m03_couplers_ARBURST;\n  wire [15:12]xbar_to_m03_couplers_ARCACHE;\n  wire [27:21]xbar_to_m03_couplers_ARID;\n  wire [31:24]xbar_to_m03_couplers_ARLEN;\n  wire [3:3]xbar_to_m03_couplers_ARLOCK;\n  wire [11:9]xbar_to_m03_couplers_ARPROT;\n  wire [15:12]xbar_to_m03_couplers_ARQOS;\n  wire xbar_to_m03_couplers_ARREADY;\n  wire [15:12]xbar_to_m03_couplers_ARREGION;\n  wire [11:9]xbar_to_m03_couplers_ARSIZE;\n  wire [3:3]xbar_to_m03_couplers_ARVALID;\n  wire [255:192]xbar_to_m03_couplers_AWADDR;\n  wire [7:6]xbar_to_m03_couplers_AWBURST;\n  wire [15:12]xbar_to_m03_couplers_AWCACHE;\n  wire [27:21]xbar_to_m03_couplers_AWID;\n  wire [31:24]xbar_to_m03_couplers_AWLEN;\n  wire [3:3]xbar_to_m03_couplers_AWLOCK;\n  wire [11:9]xbar_to_m03_couplers_AWPROT;\n  wire [15:12]xbar_to_m03_couplers_AWQOS;\n  wire xbar_to_m03_couplers_AWREADY;\n  wire [15:12]xbar_to_m03_couplers_AWREGION;\n  wire [11:9]xbar_to_m03_couplers_AWSIZE;\n  wire [3:3]xbar_to_m03_couplers_AWVALID;\n  wire [6:0]xbar_to_m03_couplers_BID;\n  wire [3:3]xbar_to_m03_couplers_BREADY;\n  wire [1:0]xbar_to_m03_couplers_BRESP;\n  wire xbar_to_m03_couplers_BVALID;\n  wire [511:0]xbar_to_m03_couplers_RDATA;\n  wire [6:0]xbar_to_m03_couplers_RID;\n  wire xbar_to_m03_couplers_RLAST;\n  wire [3:3]xbar_to_m03_couplers_RREADY;\n  wire [1:0]xbar_to_m03_couplers_RRESP;\n  wire xbar_to_m03_couplers_RVALID;\n  wire [2047:1536]xbar_to_m03_couplers_WDATA;\n  wire [3:3]xbar_to_m03_couplers_WLAST;\n  wire xbar_to_m03_couplers_WREADY;\n  wire [255:192]xbar_to_m03_couplers_WSTRB;\n  wire [3:3]xbar_to_m03_couplers_WVALID;\n\n  assign M00_AXI_araddr[63:0] = m00_couplers_to_axi_interconnect_0_ARADDR;\n  assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_interconnect_0_ARBURST;\n  assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M00_AXI_arid[6:0] = m00_couplers_to_axi_interconnect_0_ARID;\n  assign M00_AXI_arlen[7:0] = m00_couplers_to_axi_interconnect_0_ARLEN;\n  assign M00_AXI_arlock[0] = m00_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_interconnect_0_ARPROT;\n  assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_interconnect_0_ARQOS;\n  assign M00_AXI_arregion[3:0] = m00_couplers_to_axi_interconnect_0_ARREGION;\n  assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M00_AXI_arvalid = m00_couplers_to_axi_interconnect_0_ARVALID;\n  assign M00_AXI_awaddr[63:0] = m00_couplers_to_axi_interconnect_0_AWADDR;\n  assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_interconnect_0_AWBURST;\n  assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M00_AXI_awid[6:0] = m00_couplers_to_axi_interconnect_0_AWID;\n  assign M00_AXI_awlen[7:0] = m00_couplers_to_axi_interconnect_0_AWLEN;\n  assign M00_AXI_awlock[0] = m00_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_interconnect_0_AWPROT;\n  assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_interconnect_0_AWQOS;\n  assign M00_AXI_awregion[3:0] = m00_couplers_to_axi_interconnect_0_AWREGION;\n  assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M00_AXI_awvalid = m00_couplers_to_axi_interconnect_0_AWVALID;\n  assign M00_AXI_bready = m00_couplers_to_axi_interconnect_0_BREADY;\n  assign M00_AXI_rready = m00_couplers_to_axi_interconnect_0_RREADY;\n  assign M00_AXI_wdata[511:0] = m00_couplers_to_axi_interconnect_0_WDATA;\n  assign M00_AXI_wlast = m00_couplers_to_axi_interconnect_0_WLAST;\n  assign M00_AXI_wstrb[63:0] = m00_couplers_to_axi_interconnect_0_WSTRB;\n  assign M00_AXI_wvalid = m00_couplers_to_axi_interconnect_0_WVALID;\n  assign M01_AXI_araddr[63:0] = m01_couplers_to_axi_interconnect_0_ARADDR;\n  assign M01_AXI_arburst[1:0] = m01_couplers_to_axi_interconnect_0_ARBURST;\n  assign M01_AXI_arcache[3:0] = m01_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M01_AXI_arid[6:0] = m01_couplers_to_axi_interconnect_0_ARID;\n  assign M01_AXI_arlen[7:0] = m01_couplers_to_axi_interconnect_0_ARLEN;\n  assign M01_AXI_arlock[0] = m01_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M01_AXI_arprot[2:0] = m01_couplers_to_axi_interconnect_0_ARPROT;\n  assign M01_AXI_arqos[3:0] = m01_couplers_to_axi_interconnect_0_ARQOS;\n  assign M01_AXI_arregion[3:0] = m01_couplers_to_axi_interconnect_0_ARREGION;\n  assign M01_AXI_arsize[2:0] = m01_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M01_AXI_arvalid = m01_couplers_to_axi_interconnect_0_ARVALID;\n  assign M01_AXI_awaddr[63:0] = m01_couplers_to_axi_interconnect_0_AWADDR;\n  assign M01_AXI_awburst[1:0] = m01_couplers_to_axi_interconnect_0_AWBURST;\n  assign M01_AXI_awcache[3:0] = m01_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M01_AXI_awid[6:0] = m01_couplers_to_axi_interconnect_0_AWID;\n  assign M01_AXI_awlen[7:0] = m01_couplers_to_axi_interconnect_0_AWLEN;\n  assign M01_AXI_awlock[0] = m01_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M01_AXI_awprot[2:0] = m01_couplers_to_axi_interconnect_0_AWPROT;\n  assign M01_AXI_awqos[3:0] = m01_couplers_to_axi_interconnect_0_AWQOS;\n  assign M01_AXI_awregion[3:0] = m01_couplers_to_axi_interconnect_0_AWREGION;\n  assign M01_AXI_awsize[2:0] = m01_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M01_AXI_awvalid = m01_couplers_to_axi_interconnect_0_AWVALID;\n  assign M01_AXI_bready = m01_couplers_to_axi_interconnect_0_BREADY;\n  assign M01_AXI_rready = m01_couplers_to_axi_interconnect_0_RREADY;\n  assign M01_AXI_wdata[511:0] = m01_couplers_to_axi_interconnect_0_WDATA;\n  assign M01_AXI_wlast = m01_couplers_to_axi_interconnect_0_WLAST;\n  assign M01_AXI_wstrb[63:0] = m01_couplers_to_axi_interconnect_0_WSTRB;\n  assign M01_AXI_wvalid = m01_couplers_to_axi_interconnect_0_WVALID;\n  assign M02_AXI_araddr[63:0] = m02_couplers_to_axi_interconnect_0_ARADDR;\n  assign M02_AXI_arburst[1:0] = m02_couplers_to_axi_interconnect_0_ARBURST;\n  assign M02_AXI_arcache[3:0] = m02_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M02_AXI_arid[6:0] = m02_couplers_to_axi_interconnect_0_ARID;\n  assign M02_AXI_arlen[7:0] = m02_couplers_to_axi_interconnect_0_ARLEN;\n  assign M02_AXI_arlock[0] = m02_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M02_AXI_arprot[2:0] = m02_couplers_to_axi_interconnect_0_ARPROT;\n  assign M02_AXI_arqos[3:0] = m02_couplers_to_axi_interconnect_0_ARQOS;\n  assign M02_AXI_arregion[3:0] = m02_couplers_to_axi_interconnect_0_ARREGION;\n  assign M02_AXI_arsize[2:0] = m02_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M02_AXI_arvalid = m02_couplers_to_axi_interconnect_0_ARVALID;\n  assign M02_AXI_awaddr[63:0] = m02_couplers_to_axi_interconnect_0_AWADDR;\n  assign M02_AXI_awburst[1:0] = m02_couplers_to_axi_interconnect_0_AWBURST;\n  assign M02_AXI_awcache[3:0] = m02_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M02_AXI_awid[6:0] = m02_couplers_to_axi_interconnect_0_AWID;\n  assign M02_AXI_awlen[7:0] = m02_couplers_to_axi_interconnect_0_AWLEN;\n  assign M02_AXI_awlock[0] = m02_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M02_AXI_awprot[2:0] = m02_couplers_to_axi_interconnect_0_AWPROT;\n  assign M02_AXI_awqos[3:0] = m02_couplers_to_axi_interconnect_0_AWQOS;\n  assign M02_AXI_awregion[3:0] = m02_couplers_to_axi_interconnect_0_AWREGION;\n  assign M02_AXI_awsize[2:0] = m02_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M02_AXI_awvalid = m02_couplers_to_axi_interconnect_0_AWVALID;\n  assign M02_AXI_bready = m02_couplers_to_axi_interconnect_0_BREADY;\n  assign M02_AXI_rready = m02_couplers_to_axi_interconnect_0_RREADY;\n  assign M02_AXI_wdata[511:0] = m02_couplers_to_axi_interconnect_0_WDATA;\n  assign M02_AXI_wlast = m02_couplers_to_axi_interconnect_0_WLAST;\n  assign M02_AXI_wstrb[63:0] = m02_couplers_to_axi_interconnect_0_WSTRB;\n  assign M02_AXI_wvalid = m02_couplers_to_axi_interconnect_0_WVALID;\n  assign M03_AXI_araddr[63:0] = m03_couplers_to_axi_interconnect_0_ARADDR;\n  assign M03_AXI_arburst[1:0] = m03_couplers_to_axi_interconnect_0_ARBURST;\n  assign M03_AXI_arcache[3:0] = m03_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M03_AXI_arid[6:0] = m03_couplers_to_axi_interconnect_0_ARID;\n  assign M03_AXI_arlen[7:0] = m03_couplers_to_axi_interconnect_0_ARLEN;\n  assign M03_AXI_arlock[0] = m03_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M03_AXI_arprot[2:0] = m03_couplers_to_axi_interconnect_0_ARPROT;\n  assign M03_AXI_arqos[3:0] = m03_couplers_to_axi_interconnect_0_ARQOS;\n  assign M03_AXI_arregion[3:0] = m03_couplers_to_axi_interconnect_0_ARREGION;\n  assign M03_AXI_arsize[2:0] = m03_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M03_AXI_arvalid = m03_couplers_to_axi_interconnect_0_ARVALID;\n  assign M03_AXI_awaddr[63:0] = m03_couplers_to_axi_interconnect_0_AWADDR;\n  assign M03_AXI_awburst[1:0] = m03_couplers_to_axi_interconnect_0_AWBURST;\n  assign M03_AXI_awcache[3:0] = m03_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M03_AXI_awid[6:0] = m03_couplers_to_axi_interconnect_0_AWID;\n  assign M03_AXI_awlen[7:0] = m03_couplers_to_axi_interconnect_0_AWLEN;\n  assign M03_AXI_awlock[0] = m03_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M03_AXI_awprot[2:0] = m03_couplers_to_axi_interconnect_0_AWPROT;\n  assign M03_AXI_awqos[3:0] = m03_couplers_to_axi_interconnect_0_AWQOS;\n  assign M03_AXI_awregion[3:0] = m03_couplers_to_axi_interconnect_0_AWREGION;\n  assign M03_AXI_awsize[2:0] = m03_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M03_AXI_awvalid = m03_couplers_to_axi_interconnect_0_AWVALID;\n  assign M03_AXI_bready = m03_couplers_to_axi_interconnect_0_BREADY;\n  assign M03_AXI_rready = m03_couplers_to_axi_interconnect_0_RREADY;\n  assign M03_AXI_wdata[511:0] = m03_couplers_to_axi_interconnect_0_WDATA;\n  assign M03_AXI_wlast = m03_couplers_to_axi_interconnect_0_WLAST;\n  assign M03_AXI_wstrb[63:0] = m03_couplers_to_axi_interconnect_0_WSTRB;\n  assign M03_AXI_wvalid = m03_couplers_to_axi_interconnect_0_WVALID;\n  assign S00_AXI_arready = axi_interconnect_0_to_s00_couplers_ARREADY;\n  assign S00_AXI_awready = axi_interconnect_0_to_s00_couplers_AWREADY;\n  assign S00_AXI_bid[5:0] = axi_interconnect_0_to_s00_couplers_BID;\n  assign S00_AXI_bresp[1:0] = axi_interconnect_0_to_s00_couplers_BRESP;\n  assign S00_AXI_bvalid = axi_interconnect_0_to_s00_couplers_BVALID;\n  assign S00_AXI_rdata[511:0] = axi_interconnect_0_to_s00_couplers_RDATA;\n  assign S00_AXI_rid[5:0] = axi_interconnect_0_to_s00_couplers_RID;\n  assign S00_AXI_rlast = axi_interconnect_0_to_s00_couplers_RLAST;\n  assign S00_AXI_rresp[1:0] = axi_interconnect_0_to_s00_couplers_RRESP;\n  assign S00_AXI_rvalid = axi_interconnect_0_to_s00_couplers_RVALID;\n  assign S00_AXI_wready = axi_interconnect_0_to_s00_couplers_WREADY;\n  assign S01_AXI_arready = axi_interconnect_0_to_s01_couplers_ARREADY;\n  assign S01_AXI_awready = axi_interconnect_0_to_s01_couplers_AWREADY;\n  assign S01_AXI_bid[5:0] = axi_interconnect_0_to_s01_couplers_BID;\n  assign S01_AXI_bresp[1:0] = axi_interconnect_0_to_s01_couplers_BRESP;\n  assign S01_AXI_bvalid = axi_interconnect_0_to_s01_couplers_BVALID;\n  assign S01_AXI_rdata[511:0] = axi_interconnect_0_to_s01_couplers_RDATA;\n  assign S01_AXI_rid[5:0] = axi_interconnect_0_to_s01_couplers_RID;\n  assign S01_AXI_rlast = axi_interconnect_0_to_s01_couplers_RLAST;\n  assign S01_AXI_rresp[1:0] = axi_interconnect_0_to_s01_couplers_RRESP;\n  assign S01_AXI_rvalid = axi_interconnect_0_to_s01_couplers_RVALID;\n  assign S01_AXI_wready = axi_interconnect_0_to_s01_couplers_WREADY;\n  assign axi_interconnect_0_ACLK_net = ACLK;\n  assign axi_interconnect_0_ARESETN_net = ARESETN;\n  assign axi_interconnect_0_to_s00_couplers_ARADDR = S00_AXI_araddr[63:0];\n  assign axi_interconnect_0_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];\n  assign axi_interconnect_0_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARID = S00_AXI_arid[5:0];\n  assign axi_interconnect_0_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0];\n  assign axi_interconnect_0_to_s00_couplers_ARLOCK = S00_AXI_arlock[0];\n  assign axi_interconnect_0_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];\n  assign axi_interconnect_0_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARREGION = S00_AXI_arregion[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];\n  assign axi_interconnect_0_to_s00_couplers_ARVALID = S00_AXI_arvalid;\n  assign axi_interconnect_0_to_s00_couplers_AWADDR = S00_AXI_awaddr[63:0];\n  assign axi_interconnect_0_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];\n  assign axi_interconnect_0_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWID = S00_AXI_awid[5:0];\n  assign axi_interconnect_0_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0];\n  assign axi_interconnect_0_to_s00_couplers_AWLOCK = S00_AXI_awlock[0];\n  assign axi_interconnect_0_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];\n  assign axi_interconnect_0_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWREGION = S00_AXI_awregion[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];\n  assign axi_interconnect_0_to_s00_couplers_AWVALID = S00_AXI_awvalid;\n  assign axi_interconnect_0_to_s00_couplers_BREADY = S00_AXI_bready;\n  assign axi_interconnect_0_to_s00_couplers_RREADY = S00_AXI_rready;\n  assign axi_interconnect_0_to_s00_couplers_WDATA = S00_AXI_wdata[511:0];\n  assign axi_interconnect_0_to_s00_couplers_WLAST = S00_AXI_wlast;\n  assign axi_interconnect_0_to_s00_couplers_WSTRB = S00_AXI_wstrb[63:0];\n  assign axi_interconnect_0_to_s00_couplers_WVALID = S00_AXI_wvalid;\n  assign axi_interconnect_0_to_s01_couplers_ARADDR = S01_AXI_araddr[63:0];\n  assign axi_interconnect_0_to_s01_couplers_ARBURST = S01_AXI_arburst[1:0];\n  assign axi_interconnect_0_to_s01_couplers_ARCACHE = S01_AXI_arcache[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARID = S01_AXI_arid[5:0];\n  assign axi_interconnect_0_to_s01_couplers_ARLEN = S01_AXI_arlen[7:0];\n  assign axi_interconnect_0_to_s01_couplers_ARLOCK = S01_AXI_arlock[0];\n  assign axi_interconnect_0_to_s01_couplers_ARPROT = S01_AXI_arprot[2:0];\n  assign axi_interconnect_0_to_s01_couplers_ARQOS = S01_AXI_arqos[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARREGION = S01_AXI_arregion[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARSIZE = S01_AXI_arsize[2:0];\n  assign axi_interconnect_0_to_s01_couplers_ARVALID = S01_AXI_arvalid;\n  assign axi_interconnect_0_to_s01_couplers_AWADDR = S01_AXI_awaddr[63:0];\n  assign axi_interconnect_0_to_s01_couplers_AWBURST = S01_AXI_awburst[1:0];\n  assign axi_interconnect_0_to_s01_couplers_AWCACHE = S01_AXI_awcache[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWID = S01_AXI_awid[5:0];\n  assign axi_interconnect_0_to_s01_couplers_AWLEN = S01_AXI_awlen[7:0];\n  assign axi_interconnect_0_to_s01_couplers_AWLOCK = S01_AXI_awlock[0];\n  assign axi_interconnect_0_to_s01_couplers_AWPROT = S01_AXI_awprot[2:0];\n  assign axi_interconnect_0_to_s01_couplers_AWQOS = S01_AXI_awqos[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWREGION = S01_AXI_awregion[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWSIZE = S01_AXI_awsize[2:0];\n  assign axi_interconnect_0_to_s01_couplers_AWVALID = S01_AXI_awvalid;\n  assign axi_interconnect_0_to_s01_couplers_BREADY = S01_AXI_bready;\n  assign axi_interconnect_0_to_s01_couplers_RREADY = S01_AXI_rready;\n  assign axi_interconnect_0_to_s01_couplers_WDATA = S01_AXI_wdata[511:0];\n  assign axi_interconnect_0_to_s01_couplers_WLAST = S01_AXI_wlast;\n  assign axi_interconnect_0_to_s01_couplers_WSTRB = S01_AXI_wstrb[63:0];\n  assign axi_interconnect_0_to_s01_couplers_WVALID = S01_AXI_wvalid;\n  assign m00_couplers_to_axi_interconnect_0_ARREADY = M00_AXI_arready;\n  assign m00_couplers_to_axi_interconnect_0_AWREADY = M00_AXI_awready;\n  assign m00_couplers_to_axi_interconnect_0_BID = M00_AXI_bid[6:0];\n  assign m00_couplers_to_axi_interconnect_0_BRESP = M00_AXI_bresp[1:0];\n  assign m00_couplers_to_axi_interconnect_0_BVALID = M00_AXI_bvalid;\n  assign m00_couplers_to_axi_interconnect_0_RDATA = M00_AXI_rdata[511:0];\n  assign m00_couplers_to_axi_interconnect_0_RID = M00_AXI_rid[6:0];\n  assign m00_couplers_to_axi_interconnect_0_RLAST = M00_AXI_rlast;\n  assign m00_couplers_to_axi_interconnect_0_RRESP = M00_AXI_rresp[1:0];\n  assign m00_couplers_to_axi_interconnect_0_RVALID = M00_AXI_rvalid;\n  assign m00_couplers_to_axi_interconnect_0_WREADY = M00_AXI_wready;\n  assign m01_couplers_to_axi_interconnect_0_ARREADY = M01_AXI_arready;\n  assign m01_couplers_to_axi_interconnect_0_AWREADY = M01_AXI_awready;\n  assign m01_couplers_to_axi_interconnect_0_BID = M01_AXI_bid[6:0];\n  assign m01_couplers_to_axi_interconnect_0_BRESP = M01_AXI_bresp[1:0];\n  assign m01_couplers_to_axi_interconnect_0_BVALID = M01_AXI_bvalid;\n  assign m01_couplers_to_axi_interconnect_0_RDATA = M01_AXI_rdata[511:0];\n  assign m01_couplers_to_axi_interconnect_0_RID = M01_AXI_rid[6:0];\n  assign m01_couplers_to_axi_interconnect_0_RLAST = M01_AXI_rlast;\n  assign m01_couplers_to_axi_interconnect_0_RRESP = M01_AXI_rresp[1:0];\n  assign m01_couplers_to_axi_interconnect_0_RVALID = M01_AXI_rvalid;\n  assign m01_couplers_to_axi_interconnect_0_WREADY = M01_AXI_wready;\n  assign m02_couplers_to_axi_interconnect_0_ARREADY = M02_AXI_arready;\n  assign m02_couplers_to_axi_interconnect_0_AWREADY = M02_AXI_awready;\n  assign m02_couplers_to_axi_interconnect_0_BID = M02_AXI_bid[6:0];\n  assign m02_couplers_to_axi_interconnect_0_BRESP = M02_AXI_bresp[1:0];\n  assign m02_couplers_to_axi_interconnect_0_BVALID = M02_AXI_bvalid;\n  assign m02_couplers_to_axi_interconnect_0_RDATA = M02_AXI_rdata[511:0];\n  assign m02_couplers_to_axi_interconnect_0_RID = M02_AXI_rid[6:0];\n  assign m02_couplers_to_axi_interconnect_0_RLAST = M02_AXI_rlast;\n  assign m02_couplers_to_axi_interconnect_0_RRESP = M02_AXI_rresp[1:0];\n  assign m02_couplers_to_axi_interconnect_0_RVALID = M02_AXI_rvalid;\n  assign m02_couplers_to_axi_interconnect_0_WREADY = M02_AXI_wready;\n  assign m03_couplers_to_axi_interconnect_0_ARREADY = M03_AXI_arready;\n  assign m03_couplers_to_axi_interconnect_0_AWREADY = M03_AXI_awready;\n  assign m03_couplers_to_axi_interconnect_0_BID = M03_AXI_bid[6:0];\n  assign m03_couplers_to_axi_interconnect_0_BRESP = M03_AXI_bresp[1:0];\n  assign m03_couplers_to_axi_interconnect_0_BVALID = M03_AXI_bvalid;\n  assign m03_couplers_to_axi_interconnect_0_RDATA = M03_AXI_rdata[511:0];\n  assign m03_couplers_to_axi_interconnect_0_RID = M03_AXI_rid[6:0];\n  assign m03_couplers_to_axi_interconnect_0_RLAST = M03_AXI_rlast;\n  assign m03_couplers_to_axi_interconnect_0_RRESP = M03_AXI_rresp[1:0];\n  assign m03_couplers_to_axi_interconnect_0_RVALID = M03_AXI_rvalid;\n  assign m03_couplers_to_axi_interconnect_0_WREADY = M03_AXI_wready;\n  m00_couplers_imp_1QBJ6U2 m00_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m00_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m00_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m00_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m00_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m00_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m00_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m00_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m00_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m00_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m00_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m00_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m00_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m00_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m00_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m00_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m00_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m00_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m00_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m00_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m00_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m00_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m00_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m00_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m00_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m00_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m00_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m00_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m00_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m00_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m00_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m00_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m00_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m00_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m00_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m00_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m00_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m00_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m00_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m00_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m00_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m00_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m00_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m00_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m00_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m00_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m00_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m00_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m00_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m00_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m00_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m00_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m00_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m00_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m00_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m00_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m00_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m00_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m00_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m00_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m00_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m00_couplers_BID),\n        .S_AXI_bready(xbar_to_m00_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m00_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m00_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m00_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m00_couplers_RID),\n        .S_AXI_rlast(xbar_to_m00_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m00_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m00_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m00_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m00_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m00_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m00_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m00_couplers_WVALID));\n  m01_couplers_imp_10IMR9A m01_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m01_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m01_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m01_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m01_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m01_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m01_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m01_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m01_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m01_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m01_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m01_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m01_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m01_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m01_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m01_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m01_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m01_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m01_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m01_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m01_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m01_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m01_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m01_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m01_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m01_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m01_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m01_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m01_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m01_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m01_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m01_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m01_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m01_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m01_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m01_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m01_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m01_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m01_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m01_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m01_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m01_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m01_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m01_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m01_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m01_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m01_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m01_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m01_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m01_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m01_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m01_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m01_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m01_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m01_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m01_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m01_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m01_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m01_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m01_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m01_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m01_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m01_couplers_BID),\n        .S_AXI_bready(xbar_to_m01_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m01_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m01_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m01_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m01_couplers_RID),\n        .S_AXI_rlast(xbar_to_m01_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m01_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m01_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m01_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m01_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m01_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m01_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m01_couplers_WVALID));\n  m02_couplers_imp_APDUS2 m02_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m02_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m02_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m02_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m02_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m02_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m02_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m02_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m02_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m02_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m02_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m02_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m02_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m02_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m02_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m02_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m02_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m02_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m02_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m02_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m02_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m02_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m02_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m02_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m02_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m02_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m02_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m02_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m02_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m02_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m02_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m02_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m02_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m02_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m02_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m02_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m02_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m02_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m02_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m02_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m02_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m02_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m02_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m02_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m02_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m02_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m02_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m02_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m02_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m02_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m02_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m02_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m02_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m02_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m02_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m02_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m02_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m02_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m02_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m02_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m02_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m02_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m02_couplers_BID),\n        .S_AXI_bready(xbar_to_m02_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m02_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m02_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m02_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m02_couplers_RID),\n        .S_AXI_rlast(xbar_to_m02_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m02_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m02_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m02_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m02_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m02_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m02_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m02_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m02_couplers_WVALID));\n  m03_couplers_imp_JAYOMU m03_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m03_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m03_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m03_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m03_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m03_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m03_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m03_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m03_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m03_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m03_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m03_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m03_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m03_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m03_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m03_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m03_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m03_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m03_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m03_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m03_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m03_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m03_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m03_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m03_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m03_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m03_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m03_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m03_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m03_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m03_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m03_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m03_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m03_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m03_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m03_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m03_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m03_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m03_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m03_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m03_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m03_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m03_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m03_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m03_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m03_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m03_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m03_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m03_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m03_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m03_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m03_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m03_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m03_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m03_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m03_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m03_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m03_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m03_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m03_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m03_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m03_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m03_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m03_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m03_couplers_BID),\n        .S_AXI_bready(xbar_to_m03_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m03_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m03_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m03_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m03_couplers_RID),\n        .S_AXI_rlast(xbar_to_m03_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m03_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m03_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m03_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m03_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m03_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m03_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m03_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m03_couplers_WVALID));\n  s00_couplers_imp_QICM5G s00_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(s00_couplers_to_xbar_ARADDR),\n        .M_AXI_arburst(s00_couplers_to_xbar_ARBURST),\n        .M_AXI_arcache(s00_couplers_to_xbar_ARCACHE),\n        .M_AXI_arid(s00_couplers_to_xbar_ARID),\n        .M_AXI_arlen(s00_couplers_to_xbar_ARLEN),\n        .M_AXI_arlock(s00_couplers_to_xbar_ARLOCK),\n        .M_AXI_arprot(s00_couplers_to_xbar_ARPROT),\n        .M_AXI_arqos(s00_couplers_to_xbar_ARQOS),\n        .M_AXI_arready(s00_couplers_to_xbar_ARREADY),\n        .M_AXI_arsize(s00_couplers_to_xbar_ARSIZE),\n        .M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),\n        .M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),\n        .M_AXI_awburst(s00_couplers_to_xbar_AWBURST),\n        .M_AXI_awcache(s00_couplers_to_xbar_AWCACHE),\n        .M_AXI_awid(s00_couplers_to_xbar_AWID),\n        .M_AXI_awlen(s00_couplers_to_xbar_AWLEN),\n        .M_AXI_awlock(s00_couplers_to_xbar_AWLOCK),\n        .M_AXI_awprot(s00_couplers_to_xbar_AWPROT),\n        .M_AXI_awqos(s00_couplers_to_xbar_AWQOS),\n        .M_AXI_awready(s00_couplers_to_xbar_AWREADY),\n        .M_AXI_awsize(s00_couplers_to_xbar_AWSIZE),\n        .M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),\n        .M_AXI_bid(s00_couplers_to_xbar_BID),\n        .M_AXI_bready(s00_couplers_to_xbar_BREADY),\n        .M_AXI_bresp(s00_couplers_to_xbar_BRESP),\n        .M_AXI_bvalid(s00_couplers_to_xbar_BVALID),\n        .M_AXI_rdata(s00_couplers_to_xbar_RDATA),\n        .M_AXI_rid(s00_couplers_to_xbar_RID),\n        .M_AXI_rlast(s00_couplers_to_xbar_RLAST),\n        .M_AXI_rready(s00_couplers_to_xbar_RREADY),\n        .M_AXI_rresp(s00_couplers_to_xbar_RRESP),\n        .M_AXI_rvalid(s00_couplers_to_xbar_RVALID),\n        .M_AXI_wdata(s00_couplers_to_xbar_WDATA),\n        .M_AXI_wlast(s00_couplers_to_xbar_WLAST),\n        .M_AXI_wready(s00_couplers_to_xbar_WREADY),\n        .M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),\n        .M_AXI_wvalid(s00_couplers_to_xbar_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(axi_interconnect_0_to_s00_couplers_ARADDR),\n        .S_AXI_arburst(axi_interconnect_0_to_s00_couplers_ARBURST),\n        .S_AXI_arcache(axi_interconnect_0_to_s00_couplers_ARCACHE),\n        .S_AXI_arid(axi_interconnect_0_to_s00_couplers_ARID),\n        .S_AXI_arlen(axi_interconnect_0_to_s00_couplers_ARLEN),\n        .S_AXI_arlock(axi_interconnect_0_to_s00_couplers_ARLOCK),\n        .S_AXI_arprot(axi_interconnect_0_to_s00_couplers_ARPROT),\n        .S_AXI_arqos(axi_interconnect_0_to_s00_couplers_ARQOS),\n        .S_AXI_arready(axi_interconnect_0_to_s00_couplers_ARREADY),\n        .S_AXI_arregion(axi_interconnect_0_to_s00_couplers_ARREGION),\n        .S_AXI_arsize(axi_interconnect_0_to_s00_couplers_ARSIZE),\n        .S_AXI_arvalid(axi_interconnect_0_to_s00_couplers_ARVALID),\n        .S_AXI_awaddr(axi_interconnect_0_to_s00_couplers_AWADDR),\n        .S_AXI_awburst(axi_interconnect_0_to_s00_couplers_AWBURST),\n        .S_AXI_awcache(axi_interconnect_0_to_s00_couplers_AWCACHE),\n        .S_AXI_awid(axi_interconnect_0_to_s00_couplers_AWID),\n        .S_AXI_awlen(axi_interconnect_0_to_s00_couplers_AWLEN),\n        .S_AXI_awlock(axi_interconnect_0_to_s00_couplers_AWLOCK),\n        .S_AXI_awprot(axi_interconnect_0_to_s00_couplers_AWPROT),\n        .S_AXI_awqos(axi_interconnect_0_to_s00_couplers_AWQOS),\n        .S_AXI_awready(axi_interconnect_0_to_s00_couplers_AWREADY),\n        .S_AXI_awregion(axi_interconnect_0_to_s00_couplers_AWREGION),\n        .S_AXI_awsize(axi_interconnect_0_to_s00_couplers_AWSIZE),\n        .S_AXI_awvalid(axi_interconnect_0_to_s00_couplers_AWVALID),\n        .S_AXI_bid(axi_interconnect_0_to_s00_couplers_BID),\n        .S_AXI_bready(axi_interconnect_0_to_s00_couplers_BREADY),\n        .S_AXI_bresp(axi_interconnect_0_to_s00_couplers_BRESP),\n        .S_AXI_bvalid(axi_interconnect_0_to_s00_couplers_BVALID),\n        .S_AXI_rdata(axi_interconnect_0_to_s00_couplers_RDATA),\n        .S_AXI_rid(axi_interconnect_0_to_s00_couplers_RID),\n        .S_AXI_rlast(axi_interconnect_0_to_s00_couplers_RLAST),\n        .S_AXI_rready(axi_interconnect_0_to_s00_couplers_RREADY),\n        .S_AXI_rresp(axi_interconnect_0_to_s00_couplers_RRESP),\n        .S_AXI_rvalid(axi_interconnect_0_to_s00_couplers_RVALID),\n        .S_AXI_wdata(axi_interconnect_0_to_s00_couplers_WDATA),\n        .S_AXI_wlast(axi_interconnect_0_to_s00_couplers_WLAST),\n        .S_AXI_wready(axi_interconnect_0_to_s00_couplers_WREADY),\n        .S_AXI_wstrb(axi_interconnect_0_to_s00_couplers_WSTRB),\n        .S_AXI_wvalid(axi_interconnect_0_to_s00_couplers_WVALID));\n  s01_couplers_imp_GSTXQ8 s01_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(s01_couplers_to_xbar_ARADDR),\n        .M_AXI_arburst(s01_couplers_to_xbar_ARBURST),\n        .M_AXI_arcache(s01_couplers_to_xbar_ARCACHE),\n        .M_AXI_arid(s01_couplers_to_xbar_ARID),\n        .M_AXI_arlen(s01_couplers_to_xbar_ARLEN),\n        .M_AXI_arlock(s01_couplers_to_xbar_ARLOCK),\n        .M_AXI_arprot(s01_couplers_to_xbar_ARPROT),\n        .M_AXI_arqos(s01_couplers_to_xbar_ARQOS),\n        .M_AXI_arready(s01_couplers_to_xbar_ARREADY),\n        .M_AXI_arsize(s01_couplers_to_xbar_ARSIZE),\n        .M_AXI_arvalid(s01_couplers_to_xbar_ARVALID),\n        .M_AXI_awaddr(s01_couplers_to_xbar_AWADDR),\n        .M_AXI_awburst(s01_couplers_to_xbar_AWBURST),\n        .M_AXI_awcache(s01_couplers_to_xbar_AWCACHE),\n        .M_AXI_awid(s01_couplers_to_xbar_AWID),\n        .M_AXI_awlen(s01_couplers_to_xbar_AWLEN),\n        .M_AXI_awlock(s01_couplers_to_xbar_AWLOCK),\n        .M_AXI_awprot(s01_couplers_to_xbar_AWPROT),\n        .M_AXI_awqos(s01_couplers_to_xbar_AWQOS),\n        .M_AXI_awready(s01_couplers_to_xbar_AWREADY),\n        .M_AXI_awsize(s01_couplers_to_xbar_AWSIZE),\n        .M_AXI_awvalid(s01_couplers_to_xbar_AWVALID),\n        .M_AXI_bid(s01_couplers_to_xbar_BID),\n        .M_AXI_bready(s01_couplers_to_xbar_BREADY),\n        .M_AXI_bresp(s01_couplers_to_xbar_BRESP),\n        .M_AXI_bvalid(s01_couplers_to_xbar_BVALID),\n        .M_AXI_rdata(s01_couplers_to_xbar_RDATA),\n        .M_AXI_rid(s01_couplers_to_xbar_RID),\n        .M_AXI_rlast(s01_couplers_to_xbar_RLAST),\n        .M_AXI_rready(s01_couplers_to_xbar_RREADY),\n        .M_AXI_rresp(s01_couplers_to_xbar_RRESP),\n        .M_AXI_rvalid(s01_couplers_to_xbar_RVALID),\n        .M_AXI_wdata(s01_couplers_to_xbar_WDATA),\n        .M_AXI_wlast(s01_couplers_to_xbar_WLAST),\n        .M_AXI_wready(s01_couplers_to_xbar_WREADY),\n        .M_AXI_wstrb(s01_couplers_to_xbar_WSTRB),\n        .M_AXI_wvalid(s01_couplers_to_xbar_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(axi_interconnect_0_to_s01_couplers_ARADDR),\n        .S_AXI_arburst(axi_interconnect_0_to_s01_couplers_ARBURST),\n        .S_AXI_arcache(axi_interconnect_0_to_s01_couplers_ARCACHE),\n        .S_AXI_arid(axi_interconnect_0_to_s01_couplers_ARID),\n        .S_AXI_arlen(axi_interconnect_0_to_s01_couplers_ARLEN),\n        .S_AXI_arlock(axi_interconnect_0_to_s01_couplers_ARLOCK),\n        .S_AXI_arprot(axi_interconnect_0_to_s01_couplers_ARPROT),\n        .S_AXI_arqos(axi_interconnect_0_to_s01_couplers_ARQOS),\n        .S_AXI_arready(axi_interconnect_0_to_s01_couplers_ARREADY),\n        .S_AXI_arregion(axi_interconnect_0_to_s01_couplers_ARREGION),\n        .S_AXI_arsize(axi_interconnect_0_to_s01_couplers_ARSIZE),\n        .S_AXI_arvalid(axi_interconnect_0_to_s01_couplers_ARVALID),\n        .S_AXI_awaddr(axi_interconnect_0_to_s01_couplers_AWADDR),\n        .S_AXI_awburst(axi_interconnect_0_to_s01_couplers_AWBURST),\n        .S_AXI_awcache(axi_interconnect_0_to_s01_couplers_AWCACHE),\n        .S_AXI_awid(axi_interconnect_0_to_s01_couplers_AWID),\n        .S_AXI_awlen(axi_interconnect_0_to_s01_couplers_AWLEN),\n        .S_AXI_awlock(axi_interconnect_0_to_s01_couplers_AWLOCK),\n        .S_AXI_awprot(axi_interconnect_0_to_s01_couplers_AWPROT),\n        .S_AXI_awqos(axi_interconnect_0_to_s01_couplers_AWQOS),\n        .S_AXI_awready(axi_interconnect_0_to_s01_couplers_AWREADY),\n        .S_AXI_awregion(axi_interconnect_0_to_s01_couplers_AWREGION),\n        .S_AXI_awsize(axi_interconnect_0_to_s01_couplers_AWSIZE),\n        .S_AXI_awvalid(axi_interconnect_0_to_s01_couplers_AWVALID),\n        .S_AXI_bid(axi_interconnect_0_to_s01_couplers_BID),\n        .S_AXI_bready(axi_interconnect_0_to_s01_couplers_BREADY),\n        .S_AXI_bresp(axi_interconnect_0_to_s01_couplers_BRESP),\n        .S_AXI_bvalid(axi_interconnect_0_to_s01_couplers_BVALID),\n        .S_AXI_rdata(axi_interconnect_0_to_s01_couplers_RDATA),\n        .S_AXI_rid(axi_interconnect_0_to_s01_couplers_RID),\n        .S_AXI_rlast(axi_interconnect_0_to_s01_couplers_RLAST),\n        .S_AXI_rready(axi_interconnect_0_to_s01_couplers_RREADY),\n        .S_AXI_rresp(axi_interconnect_0_to_s01_couplers_RRESP),\n        .S_AXI_rvalid(axi_interconnect_0_to_s01_couplers_RVALID),\n        .S_AXI_wdata(axi_interconnect_0_to_s01_couplers_WDATA),\n        .S_AXI_wlast(axi_interconnect_0_to_s01_couplers_WLAST),\n        .S_AXI_wready(axi_interconnect_0_to_s01_couplers_WREADY),\n        .S_AXI_wstrb(axi_interconnect_0_to_s01_couplers_WSTRB),\n        .S_AXI_wvalid(axi_interconnect_0_to_s01_couplers_WVALID));\n  cl_axi_interconnect_xbar_0 xbar\n       (.aclk(axi_interconnect_0_ACLK_net),\n        .aresetn(axi_interconnect_0_ARESETN_net),\n        .m_axi_araddr({xbar_to_m03_couplers_ARADDR,xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),\n        .m_axi_arburst({xbar_to_m03_couplers_ARBURST,xbar_to_m02_couplers_ARBURST,xbar_to_m01_couplers_ARBURST,xbar_to_m00_couplers_ARBURST}),\n        .m_axi_arcache({xbar_to_m03_couplers_ARCACHE,xbar_to_m02_couplers_ARCACHE,xbar_to_m01_couplers_ARCACHE,xbar_to_m00_couplers_ARCACHE}),\n        .m_axi_arid({xbar_to_m03_couplers_ARID,xbar_to_m02_couplers_ARID,xbar_to_m01_couplers_ARID,xbar_to_m00_couplers_ARID}),\n        .m_axi_arlen({xbar_to_m03_couplers_ARLEN,xbar_to_m02_couplers_ARLEN,xbar_to_m01_couplers_ARLEN,xbar_to_m00_couplers_ARLEN}),\n        .m_axi_arlock({xbar_to_m03_couplers_ARLOCK,xbar_to_m02_couplers_ARLOCK,xbar_to_m01_couplers_ARLOCK,xbar_to_m00_couplers_ARLOCK}),\n        .m_axi_arprot({xbar_to_m03_couplers_ARPROT,xbar_to_m02_couplers_ARPROT,xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}),\n        .m_axi_arqos({xbar_to_m03_couplers_ARQOS,xbar_to_m02_couplers_ARQOS,xbar_to_m01_couplers_ARQOS,xbar_to_m00_couplers_ARQOS}),\n        .m_axi_arready({xbar_to_m03_couplers_ARREADY,xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),\n        .m_axi_arregion({xbar_to_m03_couplers_ARREGION,xbar_to_m02_couplers_ARREGION,xbar_to_m01_couplers_ARREGION,xbar_to_m00_couplers_ARREGION}),\n        .m_axi_arsize({xbar_to_m03_couplers_ARSIZE,xbar_to_m02_couplers_ARSIZE,xbar_to_m01_couplers_ARSIZE,xbar_to_m00_couplers_ARSIZE}),\n        .m_axi_arvalid({xbar_to_m03_couplers_ARVALID,xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),\n        .m_axi_awaddr({xbar_to_m03_couplers_AWADDR,xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),\n        .m_axi_awburst({xbar_to_m03_couplers_AWBURST,xbar_to_m02_couplers_AWBURST,xbar_to_m01_couplers_AWBURST,xbar_to_m00_couplers_AWBURST}),\n        .m_axi_awcache({xbar_to_m03_couplers_AWCACHE,xbar_to_m02_couplers_AWCACHE,xbar_to_m01_couplers_AWCACHE,xbar_to_m00_couplers_AWCACHE}),\n        .m_axi_awid({xbar_to_m03_couplers_AWID,xbar_to_m02_couplers_AWID,xbar_to_m01_couplers_AWID,xbar_to_m00_couplers_AWID}),\n        .m_axi_awlen({xbar_to_m03_couplers_AWLEN,xbar_to_m02_couplers_AWLEN,xbar_to_m01_couplers_AWLEN,xbar_to_m00_couplers_AWLEN}),\n        .m_axi_awlock({xbar_to_m03_couplers_AWLOCK,xbar_to_m02_couplers_AWLOCK,xbar_to_m01_couplers_AWLOCK,xbar_to_m00_couplers_AWLOCK}),\n        .m_axi_awprot({xbar_to_m03_couplers_AWPROT,xbar_to_m02_couplers_AWPROT,xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}),\n        .m_axi_awqos({xbar_to_m03_couplers_AWQOS,xbar_to_m02_couplers_AWQOS,xbar_to_m01_couplers_AWQOS,xbar_to_m00_couplers_AWQOS}),\n        .m_axi_awready({xbar_to_m03_couplers_AWREADY,xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),\n        .m_axi_awregion({xbar_to_m03_couplers_AWREGION,xbar_to_m02_couplers_AWREGION,xbar_to_m01_couplers_AWREGION,xbar_to_m00_couplers_AWREGION}),\n        .m_axi_awsize({xbar_to_m03_couplers_AWSIZE,xbar_to_m02_couplers_AWSIZE,xbar_to_m01_couplers_AWSIZE,xbar_to_m00_couplers_AWSIZE}),\n        .m_axi_awvalid({xbar_to_m03_couplers_AWVALID,xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),\n        .m_axi_bid({xbar_to_m03_couplers_BID,xbar_to_m02_couplers_BID,xbar_to_m01_couplers_BID,xbar_to_m00_couplers_BID}),\n        .m_axi_bready({xbar_to_m03_couplers_BREADY,xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),\n        .m_axi_bresp({xbar_to_m03_couplers_BRESP,xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),\n        .m_axi_bvalid({xbar_to_m03_couplers_BVALID,xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),\n        .m_axi_rdata({xbar_to_m03_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),\n        .m_axi_rid({xbar_to_m03_couplers_RID,xbar_to_m02_couplers_RID,xbar_to_m01_couplers_RID,xbar_to_m00_couplers_RID}),\n        .m_axi_rlast({xbar_to_m03_couplers_RLAST,xbar_to_m02_couplers_RLAST,xbar_to_m01_couplers_RLAST,xbar_to_m00_couplers_RLAST}),\n        .m_axi_rready({xbar_to_m03_couplers_RREADY,xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),\n        .m_axi_rresp({xbar_to_m03_couplers_RRESP,xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),\n        .m_axi_rvalid({xbar_to_m03_couplers_RVALID,xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),\n        .m_axi_wdata({xbar_to_m03_couplers_WDATA,xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),\n        .m_axi_wlast({xbar_to_m03_couplers_WLAST,xbar_to_m02_couplers_WLAST,xbar_to_m01_couplers_WLAST,xbar_to_m00_couplers_WLAST}),\n        .m_axi_wready({xbar_to_m03_couplers_WREADY,xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),\n        .m_axi_wstrb({xbar_to_m03_couplers_WSTRB,xbar_to_m02_couplers_WSTRB,xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),\n        .m_axi_wvalid({xbar_to_m03_couplers_WVALID,xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),\n        .s_axi_araddr({s01_couplers_to_xbar_ARADDR,s00_couplers_to_xbar_ARADDR}),\n        .s_axi_arburst({s01_couplers_to_xbar_ARBURST,s00_couplers_to_xbar_ARBURST}),\n        .s_axi_arcache({s01_couplers_to_xbar_ARCACHE,s00_couplers_to_xbar_ARCACHE}),\n        .s_axi_arid({1'b0,s01_couplers_to_xbar_ARID,1'b0,s00_couplers_to_xbar_ARID}),\n        .s_axi_arlen({s01_couplers_to_xbar_ARLEN,s00_couplers_to_xbar_ARLEN}),\n        .s_axi_arlock({s01_couplers_to_xbar_ARLOCK,s00_couplers_to_xbar_ARLOCK}),\n        .s_axi_arprot({s01_couplers_to_xbar_ARPROT,s00_couplers_to_xbar_ARPROT}),\n        .s_axi_arqos({s01_couplers_to_xbar_ARQOS,s00_couplers_to_xbar_ARQOS}),\n        .s_axi_arready({s01_couplers_to_xbar_ARREADY,s00_couplers_to_xbar_ARREADY}),\n        .s_axi_arsize({s01_couplers_to_xbar_ARSIZE,s00_couplers_to_xbar_ARSIZE}),\n        .s_axi_arvalid({s01_couplers_to_xbar_ARVALID,s00_couplers_to_xbar_ARVALID}),\n        .s_axi_awaddr({s01_couplers_to_xbar_AWADDR,s00_couplers_to_xbar_AWADDR}),\n        .s_axi_awburst({s01_couplers_to_xbar_AWBURST,s00_couplers_to_xbar_AWBURST}),\n        .s_axi_awcache({s01_couplers_to_xbar_AWCACHE,s00_couplers_to_xbar_AWCACHE}),\n        .s_axi_awid({1'b0,s01_couplers_to_xbar_AWID,1'b0,s00_couplers_to_xbar_AWID}),\n        .s_axi_awlen({s01_couplers_to_xbar_AWLEN,s00_couplers_to_xbar_AWLEN}),\n        .s_axi_awlock({s01_couplers_to_xbar_AWLOCK,s00_couplers_to_xbar_AWLOCK}),\n        .s_axi_awprot({s01_couplers_to_xbar_AWPROT,s00_couplers_to_xbar_AWPROT}),\n        .s_axi_awqos({s01_couplers_to_xbar_AWQOS,s00_couplers_to_xbar_AWQOS}),\n        .s_axi_awready({s01_couplers_to_xbar_AWREADY,s00_couplers_to_xbar_AWREADY}),\n        .s_axi_awsize({s01_couplers_to_xbar_AWSIZE,s00_couplers_to_xbar_AWSIZE}),\n        .s_axi_awvalid({s01_couplers_to_xbar_AWVALID,s00_couplers_to_xbar_AWVALID}),\n        .s_axi_bid({s01_couplers_to_xbar_BID,s00_couplers_to_xbar_BID}),\n        .s_axi_bready({s01_couplers_to_xbar_BREADY,s00_couplers_to_xbar_BREADY}),\n        .s_axi_bresp({s01_couplers_to_xbar_BRESP,s00_couplers_to_xbar_BRESP}),\n        .s_axi_bvalid({s01_couplers_to_xbar_BVALID,s00_couplers_to_xbar_BVALID}),\n        .s_axi_rdata({s01_couplers_to_xbar_RDATA,s00_couplers_to_xbar_RDATA}),\n        .s_axi_rid({s01_couplers_to_xbar_RID,s00_couplers_to_xbar_RID}),\n        .s_axi_rlast({s01_couplers_to_xbar_RLAST,s00_couplers_to_xbar_RLAST}),\n        .s_axi_rready({s01_couplers_to_xbar_RREADY,s00_couplers_to_xbar_RREADY}),\n        .s_axi_rresp({s01_couplers_to_xbar_RRESP,s00_couplers_to_xbar_RRESP}),\n        .s_axi_rvalid({s01_couplers_to_xbar_RVALID,s00_couplers_to_xbar_RVALID}),\n        .s_axi_wdata({s01_couplers_to_xbar_WDATA,s00_couplers_to_xbar_WDATA}),\n        .s_axi_wlast({s01_couplers_to_xbar_WLAST,s00_couplers_to_xbar_WLAST}),\n        .s_axi_wready({s01_couplers_to_xbar_WREADY,s00_couplers_to_xbar_WREADY}),\n        .s_axi_wstrb({s01_couplers_to_xbar_WSTRB,s00_couplers_to_xbar_WSTRB}),\n        .s_axi_wvalid({s01_couplers_to_xbar_WVALID,s00_couplers_to_xbar_WVALID}));\nendmodule\n\nmodule m00_couplers_imp_1QBJ6U2\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m00_couplers_to_m00_regslice_ARADDR;\n  wire [1:0]m00_couplers_to_m00_regslice_ARBURST;\n  wire [3:0]m00_couplers_to_m00_regslice_ARCACHE;\n  wire [6:0]m00_couplers_to_m00_regslice_ARID;\n  wire [7:0]m00_couplers_to_m00_regslice_ARLEN;\n  wire [0:0]m00_couplers_to_m00_regslice_ARLOCK;\n  wire [2:0]m00_couplers_to_m00_regslice_ARPROT;\n  wire [3:0]m00_couplers_to_m00_regslice_ARQOS;\n  wire m00_couplers_to_m00_regslice_ARREADY;\n  wire [3:0]m00_couplers_to_m00_regslice_ARREGION;\n  wire [2:0]m00_couplers_to_m00_regslice_ARSIZE;\n  wire m00_couplers_to_m00_regslice_ARVALID;\n  wire [63:0]m00_couplers_to_m00_regslice_AWADDR;\n  wire [1:0]m00_couplers_to_m00_regslice_AWBURST;\n  wire [3:0]m00_couplers_to_m00_regslice_AWCACHE;\n  wire [6:0]m00_couplers_to_m00_regslice_AWID;\n  wire [7:0]m00_couplers_to_m00_regslice_AWLEN;\n  wire [0:0]m00_couplers_to_m00_regslice_AWLOCK;\n  wire [2:0]m00_couplers_to_m00_regslice_AWPROT;\n  wire [3:0]m00_couplers_to_m00_regslice_AWQOS;\n  wire m00_couplers_to_m00_regslice_AWREADY;\n  wire [3:0]m00_couplers_to_m00_regslice_AWREGION;\n  wire [2:0]m00_couplers_to_m00_regslice_AWSIZE;\n  wire m00_couplers_to_m00_regslice_AWVALID;\n  wire [6:0]m00_couplers_to_m00_regslice_BID;\n  wire m00_couplers_to_m00_regslice_BREADY;\n  wire [1:0]m00_couplers_to_m00_regslice_BRESP;\n  wire m00_couplers_to_m00_regslice_BVALID;\n  wire [511:0]m00_couplers_to_m00_regslice_RDATA;\n  wire [6:0]m00_couplers_to_m00_regslice_RID;\n  wire m00_couplers_to_m00_regslice_RLAST;\n  wire m00_couplers_to_m00_regslice_RREADY;\n  wire [1:0]m00_couplers_to_m00_regslice_RRESP;\n  wire m00_couplers_to_m00_regslice_RVALID;\n  wire [511:0]m00_couplers_to_m00_regslice_WDATA;\n  wire m00_couplers_to_m00_regslice_WLAST;\n  wire m00_couplers_to_m00_regslice_WREADY;\n  wire [63:0]m00_couplers_to_m00_regslice_WSTRB;\n  wire m00_couplers_to_m00_regslice_WVALID;\n  wire [63:0]m00_regslice_to_m00_couplers_ARADDR;\n  wire [1:0]m00_regslice_to_m00_couplers_ARBURST;\n  wire [3:0]m00_regslice_to_m00_couplers_ARCACHE;\n  wire [6:0]m00_regslice_to_m00_couplers_ARID;\n  wire [7:0]m00_regslice_to_m00_couplers_ARLEN;\n  wire [0:0]m00_regslice_to_m00_couplers_ARLOCK;\n  wire [2:0]m00_regslice_to_m00_couplers_ARPROT;\n  wire [3:0]m00_regslice_to_m00_couplers_ARQOS;\n  wire m00_regslice_to_m00_couplers_ARREADY;\n  wire [3:0]m00_regslice_to_m00_couplers_ARREGION;\n  wire [2:0]m00_regslice_to_m00_couplers_ARSIZE;\n  wire m00_regslice_to_m00_couplers_ARVALID;\n  wire [63:0]m00_regslice_to_m00_couplers_AWADDR;\n  wire [1:0]m00_regslice_to_m00_couplers_AWBURST;\n  wire [3:0]m00_regslice_to_m00_couplers_AWCACHE;\n  wire [6:0]m00_regslice_to_m00_couplers_AWID;\n  wire [7:0]m00_regslice_to_m00_couplers_AWLEN;\n  wire [0:0]m00_regslice_to_m00_couplers_AWLOCK;\n  wire [2:0]m00_regslice_to_m00_couplers_AWPROT;\n  wire [3:0]m00_regslice_to_m00_couplers_AWQOS;\n  wire m00_regslice_to_m00_couplers_AWREADY;\n  wire [3:0]m00_regslice_to_m00_couplers_AWREGION;\n  wire [2:0]m00_regslice_to_m00_couplers_AWSIZE;\n  wire m00_regslice_to_m00_couplers_AWVALID;\n  wire [6:0]m00_regslice_to_m00_couplers_BID;\n  wire m00_regslice_to_m00_couplers_BREADY;\n  wire [1:0]m00_regslice_to_m00_couplers_BRESP;\n  wire m00_regslice_to_m00_couplers_BVALID;\n  wire [511:0]m00_regslice_to_m00_couplers_RDATA;\n  wire [6:0]m00_regslice_to_m00_couplers_RID;\n  wire m00_regslice_to_m00_couplers_RLAST;\n  wire m00_regslice_to_m00_couplers_RREADY;\n  wire [1:0]m00_regslice_to_m00_couplers_RRESP;\n  wire m00_regslice_to_m00_couplers_RVALID;\n  wire [511:0]m00_regslice_to_m00_couplers_WDATA;\n  wire m00_regslice_to_m00_couplers_WLAST;\n  wire m00_regslice_to_m00_couplers_WREADY;\n  wire [63:0]m00_regslice_to_m00_couplers_WSTRB;\n  wire m00_regslice_to_m00_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m00_regslice_to_m00_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m00_regslice_to_m00_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m00_regslice_to_m00_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m00_regslice_to_m00_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m00_regslice_to_m00_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m00_regslice_to_m00_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m00_regslice_to_m00_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m00_regslice_to_m00_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m00_regslice_to_m00_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m00_regslice_to_m00_couplers_ARSIZE;\n  assign M_AXI_arvalid = m00_regslice_to_m00_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m00_regslice_to_m00_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m00_regslice_to_m00_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m00_regslice_to_m00_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m00_regslice_to_m00_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m00_regslice_to_m00_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m00_regslice_to_m00_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m00_regslice_to_m00_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m00_regslice_to_m00_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m00_regslice_to_m00_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m00_regslice_to_m00_couplers_AWSIZE;\n  assign M_AXI_awvalid = m00_regslice_to_m00_couplers_AWVALID;\n  assign M_AXI_bready = m00_regslice_to_m00_couplers_BREADY;\n  assign M_AXI_rready = m00_regslice_to_m00_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m00_regslice_to_m00_couplers_WDATA;\n  assign M_AXI_wlast = m00_regslice_to_m00_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m00_regslice_to_m00_couplers_WSTRB;\n  assign M_AXI_wvalid = m00_regslice_to_m00_couplers_WVALID;\n  assign S_AXI_arready = m00_couplers_to_m00_regslice_ARREADY;\n  assign S_AXI_awready = m00_couplers_to_m00_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m00_couplers_to_m00_regslice_BID;\n  assign S_AXI_bresp[1:0] = m00_couplers_to_m00_regslice_BRESP;\n  assign S_AXI_bvalid = m00_couplers_to_m00_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m00_couplers_to_m00_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m00_couplers_to_m00_regslice_RID;\n  assign S_AXI_rlast = m00_couplers_to_m00_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m00_couplers_to_m00_regslice_RRESP;\n  assign S_AXI_rvalid = m00_couplers_to_m00_regslice_RVALID;\n  assign S_AXI_wready = m00_couplers_to_m00_regslice_WREADY;\n  assign m00_couplers_to_m00_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m00_couplers_to_m00_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m00_couplers_to_m00_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m00_couplers_to_m00_regslice_ARID = S_AXI_arid[6:0];\n  assign m00_couplers_to_m00_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m00_couplers_to_m00_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m00_couplers_to_m00_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m00_couplers_to_m00_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m00_couplers_to_m00_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m00_couplers_to_m00_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m00_couplers_to_m00_regslice_ARVALID = S_AXI_arvalid;\n  assign m00_couplers_to_m00_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m00_couplers_to_m00_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m00_couplers_to_m00_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m00_couplers_to_m00_regslice_AWID = S_AXI_awid[6:0];\n  assign m00_couplers_to_m00_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m00_couplers_to_m00_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m00_couplers_to_m00_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m00_couplers_to_m00_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m00_couplers_to_m00_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m00_couplers_to_m00_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m00_couplers_to_m00_regslice_AWVALID = S_AXI_awvalid;\n  assign m00_couplers_to_m00_regslice_BREADY = S_AXI_bready;\n  assign m00_couplers_to_m00_regslice_RREADY = S_AXI_rready;\n  assign m00_couplers_to_m00_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m00_couplers_to_m00_regslice_WLAST = S_AXI_wlast;\n  assign m00_couplers_to_m00_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m00_couplers_to_m00_regslice_WVALID = S_AXI_wvalid;\n  assign m00_regslice_to_m00_couplers_ARREADY = M_AXI_arready;\n  assign m00_regslice_to_m00_couplers_AWREADY = M_AXI_awready;\n  assign m00_regslice_to_m00_couplers_BID = M_AXI_bid[6:0];\n  assign m00_regslice_to_m00_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m00_regslice_to_m00_couplers_BVALID = M_AXI_bvalid;\n  assign m00_regslice_to_m00_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m00_regslice_to_m00_couplers_RID = M_AXI_rid[6:0];\n  assign m00_regslice_to_m00_couplers_RLAST = M_AXI_rlast;\n  assign m00_regslice_to_m00_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m00_regslice_to_m00_couplers_RVALID = M_AXI_rvalid;\n  assign m00_regslice_to_m00_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m00_regslice_0 m00_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m00_regslice_to_m00_couplers_ARADDR),\n        .m_axi_arburst(m00_regslice_to_m00_couplers_ARBURST),\n        .m_axi_arcache(m00_regslice_to_m00_couplers_ARCACHE),\n        .m_axi_arid(m00_regslice_to_m00_couplers_ARID),\n        .m_axi_arlen(m00_regslice_to_m00_couplers_ARLEN),\n        .m_axi_arlock(m00_regslice_to_m00_couplers_ARLOCK),\n        .m_axi_arprot(m00_regslice_to_m00_couplers_ARPROT),\n        .m_axi_arqos(m00_regslice_to_m00_couplers_ARQOS),\n        .m_axi_arready(m00_regslice_to_m00_couplers_ARREADY),\n        .m_axi_arregion(m00_regslice_to_m00_couplers_ARREGION),\n        .m_axi_arsize(m00_regslice_to_m00_couplers_ARSIZE),\n        .m_axi_arvalid(m00_regslice_to_m00_couplers_ARVALID),\n        .m_axi_awaddr(m00_regslice_to_m00_couplers_AWADDR),\n        .m_axi_awburst(m00_regslice_to_m00_couplers_AWBURST),\n        .m_axi_awcache(m00_regslice_to_m00_couplers_AWCACHE),\n        .m_axi_awid(m00_regslice_to_m00_couplers_AWID),\n        .m_axi_awlen(m00_regslice_to_m00_couplers_AWLEN),\n        .m_axi_awlock(m00_regslice_to_m00_couplers_AWLOCK),\n        .m_axi_awprot(m00_regslice_to_m00_couplers_AWPROT),\n        .m_axi_awqos(m00_regslice_to_m00_couplers_AWQOS),\n        .m_axi_awready(m00_regslice_to_m00_couplers_AWREADY),\n        .m_axi_awregion(m00_regslice_to_m00_couplers_AWREGION),\n        .m_axi_awsize(m00_regslice_to_m00_couplers_AWSIZE),\n        .m_axi_awvalid(m00_regslice_to_m00_couplers_AWVALID),\n        .m_axi_bid(m00_regslice_to_m00_couplers_BID),\n        .m_axi_bready(m00_regslice_to_m00_couplers_BREADY),\n        .m_axi_bresp(m00_regslice_to_m00_couplers_BRESP),\n        .m_axi_bvalid(m00_regslice_to_m00_couplers_BVALID),\n        .m_axi_rdata(m00_regslice_to_m00_couplers_RDATA),\n        .m_axi_rid(m00_regslice_to_m00_couplers_RID),\n        .m_axi_rlast(m00_regslice_to_m00_couplers_RLAST),\n        .m_axi_rready(m00_regslice_to_m00_couplers_RREADY),\n        .m_axi_rresp(m00_regslice_to_m00_couplers_RRESP),\n        .m_axi_rvalid(m00_regslice_to_m00_couplers_RVALID),\n        .m_axi_wdata(m00_regslice_to_m00_couplers_WDATA),\n        .m_axi_wlast(m00_regslice_to_m00_couplers_WLAST),\n        .m_axi_wready(m00_regslice_to_m00_couplers_WREADY),\n        .m_axi_wstrb(m00_regslice_to_m00_couplers_WSTRB),\n        .m_axi_wvalid(m00_regslice_to_m00_couplers_WVALID),\n        .s_axi_araddr(m00_couplers_to_m00_regslice_ARADDR),\n        .s_axi_arburst(m00_couplers_to_m00_regslice_ARBURST),\n        .s_axi_arcache(m00_couplers_to_m00_regslice_ARCACHE),\n        .s_axi_arid(m00_couplers_to_m00_regslice_ARID),\n        .s_axi_arlen(m00_couplers_to_m00_regslice_ARLEN),\n        .s_axi_arlock(m00_couplers_to_m00_regslice_ARLOCK),\n        .s_axi_arprot(m00_couplers_to_m00_regslice_ARPROT),\n        .s_axi_arqos(m00_couplers_to_m00_regslice_ARQOS),\n        .s_axi_arready(m00_couplers_to_m00_regslice_ARREADY),\n        .s_axi_arregion(m00_couplers_to_m00_regslice_ARREGION),\n        .s_axi_arsize(m00_couplers_to_m00_regslice_ARSIZE),\n        .s_axi_arvalid(m00_couplers_to_m00_regslice_ARVALID),\n        .s_axi_awaddr(m00_couplers_to_m00_regslice_AWADDR),\n        .s_axi_awburst(m00_couplers_to_m00_regslice_AWBURST),\n        .s_axi_awcache(m00_couplers_to_m00_regslice_AWCACHE),\n        .s_axi_awid(m00_couplers_to_m00_regslice_AWID),\n        .s_axi_awlen(m00_couplers_to_m00_regslice_AWLEN),\n        .s_axi_awlock(m00_couplers_to_m00_regslice_AWLOCK),\n        .s_axi_awprot(m00_couplers_to_m00_regslice_AWPROT),\n        .s_axi_awqos(m00_couplers_to_m00_regslice_AWQOS),\n        .s_axi_awready(m00_couplers_to_m00_regslice_AWREADY),\n        .s_axi_awregion(m00_couplers_to_m00_regslice_AWREGION),\n        .s_axi_awsize(m00_couplers_to_m00_regslice_AWSIZE),\n        .s_axi_awvalid(m00_couplers_to_m00_regslice_AWVALID),\n        .s_axi_bid(m00_couplers_to_m00_regslice_BID),\n        .s_axi_bready(m00_couplers_to_m00_regslice_BREADY),\n        .s_axi_bresp(m00_couplers_to_m00_regslice_BRESP),\n        .s_axi_bvalid(m00_couplers_to_m00_regslice_BVALID),\n        .s_axi_rdata(m00_couplers_to_m00_regslice_RDATA),\n        .s_axi_rid(m00_couplers_to_m00_regslice_RID),\n        .s_axi_rlast(m00_couplers_to_m00_regslice_RLAST),\n        .s_axi_rready(m00_couplers_to_m00_regslice_RREADY),\n        .s_axi_rresp(m00_couplers_to_m00_regslice_RRESP),\n        .s_axi_rvalid(m00_couplers_to_m00_regslice_RVALID),\n        .s_axi_wdata(m00_couplers_to_m00_regslice_WDATA),\n        .s_axi_wlast(m00_couplers_to_m00_regslice_WLAST),\n        .s_axi_wready(m00_couplers_to_m00_regslice_WREADY),\n        .s_axi_wstrb(m00_couplers_to_m00_regslice_WSTRB),\n        .s_axi_wvalid(m00_couplers_to_m00_regslice_WVALID));\nendmodule\n\nmodule m01_couplers_imp_10IMR9A\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m01_couplers_to_m01_regslice_ARADDR;\n  wire [1:0]m01_couplers_to_m01_regslice_ARBURST;\n  wire [3:0]m01_couplers_to_m01_regslice_ARCACHE;\n  wire [6:0]m01_couplers_to_m01_regslice_ARID;\n  wire [7:0]m01_couplers_to_m01_regslice_ARLEN;\n  wire [0:0]m01_couplers_to_m01_regslice_ARLOCK;\n  wire [2:0]m01_couplers_to_m01_regslice_ARPROT;\n  wire [3:0]m01_couplers_to_m01_regslice_ARQOS;\n  wire m01_couplers_to_m01_regslice_ARREADY;\n  wire [3:0]m01_couplers_to_m01_regslice_ARREGION;\n  wire [2:0]m01_couplers_to_m01_regslice_ARSIZE;\n  wire m01_couplers_to_m01_regslice_ARVALID;\n  wire [63:0]m01_couplers_to_m01_regslice_AWADDR;\n  wire [1:0]m01_couplers_to_m01_regslice_AWBURST;\n  wire [3:0]m01_couplers_to_m01_regslice_AWCACHE;\n  wire [6:0]m01_couplers_to_m01_regslice_AWID;\n  wire [7:0]m01_couplers_to_m01_regslice_AWLEN;\n  wire [0:0]m01_couplers_to_m01_regslice_AWLOCK;\n  wire [2:0]m01_couplers_to_m01_regslice_AWPROT;\n  wire [3:0]m01_couplers_to_m01_regslice_AWQOS;\n  wire m01_couplers_to_m01_regslice_AWREADY;\n  wire [3:0]m01_couplers_to_m01_regslice_AWREGION;\n  wire [2:0]m01_couplers_to_m01_regslice_AWSIZE;\n  wire m01_couplers_to_m01_regslice_AWVALID;\n  wire [6:0]m01_couplers_to_m01_regslice_BID;\n  wire m01_couplers_to_m01_regslice_BREADY;\n  wire [1:0]m01_couplers_to_m01_regslice_BRESP;\n  wire m01_couplers_to_m01_regslice_BVALID;\n  wire [511:0]m01_couplers_to_m01_regslice_RDATA;\n  wire [6:0]m01_couplers_to_m01_regslice_RID;\n  wire m01_couplers_to_m01_regslice_RLAST;\n  wire m01_couplers_to_m01_regslice_RREADY;\n  wire [1:0]m01_couplers_to_m01_regslice_RRESP;\n  wire m01_couplers_to_m01_regslice_RVALID;\n  wire [511:0]m01_couplers_to_m01_regslice_WDATA;\n  wire m01_couplers_to_m01_regslice_WLAST;\n  wire m01_couplers_to_m01_regslice_WREADY;\n  wire [63:0]m01_couplers_to_m01_regslice_WSTRB;\n  wire m01_couplers_to_m01_regslice_WVALID;\n  wire [63:0]m01_regslice_to_m01_couplers_ARADDR;\n  wire [1:0]m01_regslice_to_m01_couplers_ARBURST;\n  wire [3:0]m01_regslice_to_m01_couplers_ARCACHE;\n  wire [6:0]m01_regslice_to_m01_couplers_ARID;\n  wire [7:0]m01_regslice_to_m01_couplers_ARLEN;\n  wire [0:0]m01_regslice_to_m01_couplers_ARLOCK;\n  wire [2:0]m01_regslice_to_m01_couplers_ARPROT;\n  wire [3:0]m01_regslice_to_m01_couplers_ARQOS;\n  wire m01_regslice_to_m01_couplers_ARREADY;\n  wire [3:0]m01_regslice_to_m01_couplers_ARREGION;\n  wire [2:0]m01_regslice_to_m01_couplers_ARSIZE;\n  wire m01_regslice_to_m01_couplers_ARVALID;\n  wire [63:0]m01_regslice_to_m01_couplers_AWADDR;\n  wire [1:0]m01_regslice_to_m01_couplers_AWBURST;\n  wire [3:0]m01_regslice_to_m01_couplers_AWCACHE;\n  wire [6:0]m01_regslice_to_m01_couplers_AWID;\n  wire [7:0]m01_regslice_to_m01_couplers_AWLEN;\n  wire [0:0]m01_regslice_to_m01_couplers_AWLOCK;\n  wire [2:0]m01_regslice_to_m01_couplers_AWPROT;\n  wire [3:0]m01_regslice_to_m01_couplers_AWQOS;\n  wire m01_regslice_to_m01_couplers_AWREADY;\n  wire [3:0]m01_regslice_to_m01_couplers_AWREGION;\n  wire [2:0]m01_regslice_to_m01_couplers_AWSIZE;\n  wire m01_regslice_to_m01_couplers_AWVALID;\n  wire [6:0]m01_regslice_to_m01_couplers_BID;\n  wire m01_regslice_to_m01_couplers_BREADY;\n  wire [1:0]m01_regslice_to_m01_couplers_BRESP;\n  wire m01_regslice_to_m01_couplers_BVALID;\n  wire [511:0]m01_regslice_to_m01_couplers_RDATA;\n  wire [6:0]m01_regslice_to_m01_couplers_RID;\n  wire m01_regslice_to_m01_couplers_RLAST;\n  wire m01_regslice_to_m01_couplers_RREADY;\n  wire [1:0]m01_regslice_to_m01_couplers_RRESP;\n  wire m01_regslice_to_m01_couplers_RVALID;\n  wire [511:0]m01_regslice_to_m01_couplers_WDATA;\n  wire m01_regslice_to_m01_couplers_WLAST;\n  wire m01_regslice_to_m01_couplers_WREADY;\n  wire [63:0]m01_regslice_to_m01_couplers_WSTRB;\n  wire m01_regslice_to_m01_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m01_regslice_to_m01_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m01_regslice_to_m01_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m01_regslice_to_m01_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m01_regslice_to_m01_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m01_regslice_to_m01_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m01_regslice_to_m01_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m01_regslice_to_m01_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m01_regslice_to_m01_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m01_regslice_to_m01_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m01_regslice_to_m01_couplers_ARSIZE;\n  assign M_AXI_arvalid = m01_regslice_to_m01_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m01_regslice_to_m01_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m01_regslice_to_m01_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m01_regslice_to_m01_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m01_regslice_to_m01_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m01_regslice_to_m01_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m01_regslice_to_m01_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m01_regslice_to_m01_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m01_regslice_to_m01_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m01_regslice_to_m01_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m01_regslice_to_m01_couplers_AWSIZE;\n  assign M_AXI_awvalid = m01_regslice_to_m01_couplers_AWVALID;\n  assign M_AXI_bready = m01_regslice_to_m01_couplers_BREADY;\n  assign M_AXI_rready = m01_regslice_to_m01_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m01_regslice_to_m01_couplers_WDATA;\n  assign M_AXI_wlast = m01_regslice_to_m01_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m01_regslice_to_m01_couplers_WSTRB;\n  assign M_AXI_wvalid = m01_regslice_to_m01_couplers_WVALID;\n  assign S_AXI_arready = m01_couplers_to_m01_regslice_ARREADY;\n  assign S_AXI_awready = m01_couplers_to_m01_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m01_couplers_to_m01_regslice_BID;\n  assign S_AXI_bresp[1:0] = m01_couplers_to_m01_regslice_BRESP;\n  assign S_AXI_bvalid = m01_couplers_to_m01_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m01_couplers_to_m01_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m01_couplers_to_m01_regslice_RID;\n  assign S_AXI_rlast = m01_couplers_to_m01_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m01_couplers_to_m01_regslice_RRESP;\n  assign S_AXI_rvalid = m01_couplers_to_m01_regslice_RVALID;\n  assign S_AXI_wready = m01_couplers_to_m01_regslice_WREADY;\n  assign m01_couplers_to_m01_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m01_couplers_to_m01_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m01_couplers_to_m01_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m01_couplers_to_m01_regslice_ARID = S_AXI_arid[6:0];\n  assign m01_couplers_to_m01_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m01_couplers_to_m01_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m01_couplers_to_m01_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m01_couplers_to_m01_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m01_couplers_to_m01_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m01_couplers_to_m01_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m01_couplers_to_m01_regslice_ARVALID = S_AXI_arvalid;\n  assign m01_couplers_to_m01_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m01_couplers_to_m01_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m01_couplers_to_m01_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m01_couplers_to_m01_regslice_AWID = S_AXI_awid[6:0];\n  assign m01_couplers_to_m01_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m01_couplers_to_m01_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m01_couplers_to_m01_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m01_couplers_to_m01_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m01_couplers_to_m01_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m01_couplers_to_m01_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m01_couplers_to_m01_regslice_AWVALID = S_AXI_awvalid;\n  assign m01_couplers_to_m01_regslice_BREADY = S_AXI_bready;\n  assign m01_couplers_to_m01_regslice_RREADY = S_AXI_rready;\n  assign m01_couplers_to_m01_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m01_couplers_to_m01_regslice_WLAST = S_AXI_wlast;\n  assign m01_couplers_to_m01_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m01_couplers_to_m01_regslice_WVALID = S_AXI_wvalid;\n  assign m01_regslice_to_m01_couplers_ARREADY = M_AXI_arready;\n  assign m01_regslice_to_m01_couplers_AWREADY = M_AXI_awready;\n  assign m01_regslice_to_m01_couplers_BID = M_AXI_bid[6:0];\n  assign m01_regslice_to_m01_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m01_regslice_to_m01_couplers_BVALID = M_AXI_bvalid;\n  assign m01_regslice_to_m01_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m01_regslice_to_m01_couplers_RID = M_AXI_rid[6:0];\n  assign m01_regslice_to_m01_couplers_RLAST = M_AXI_rlast;\n  assign m01_regslice_to_m01_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m01_regslice_to_m01_couplers_RVALID = M_AXI_rvalid;\n  assign m01_regslice_to_m01_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m01_regslice_0 m01_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m01_regslice_to_m01_couplers_ARADDR),\n        .m_axi_arburst(m01_regslice_to_m01_couplers_ARBURST),\n        .m_axi_arcache(m01_regslice_to_m01_couplers_ARCACHE),\n        .m_axi_arid(m01_regslice_to_m01_couplers_ARID),\n        .m_axi_arlen(m01_regslice_to_m01_couplers_ARLEN),\n        .m_axi_arlock(m01_regslice_to_m01_couplers_ARLOCK),\n        .m_axi_arprot(m01_regslice_to_m01_couplers_ARPROT),\n        .m_axi_arqos(m01_regslice_to_m01_couplers_ARQOS),\n        .m_axi_arready(m01_regslice_to_m01_couplers_ARREADY),\n        .m_axi_arregion(m01_regslice_to_m01_couplers_ARREGION),\n        .m_axi_arsize(m01_regslice_to_m01_couplers_ARSIZE),\n        .m_axi_arvalid(m01_regslice_to_m01_couplers_ARVALID),\n        .m_axi_awaddr(m01_regslice_to_m01_couplers_AWADDR),\n        .m_axi_awburst(m01_regslice_to_m01_couplers_AWBURST),\n        .m_axi_awcache(m01_regslice_to_m01_couplers_AWCACHE),\n        .m_axi_awid(m01_regslice_to_m01_couplers_AWID),\n        .m_axi_awlen(m01_regslice_to_m01_couplers_AWLEN),\n        .m_axi_awlock(m01_regslice_to_m01_couplers_AWLOCK),\n        .m_axi_awprot(m01_regslice_to_m01_couplers_AWPROT),\n        .m_axi_awqos(m01_regslice_to_m01_couplers_AWQOS),\n        .m_axi_awready(m01_regslice_to_m01_couplers_AWREADY),\n        .m_axi_awregion(m01_regslice_to_m01_couplers_AWREGION),\n        .m_axi_awsize(m01_regslice_to_m01_couplers_AWSIZE),\n        .m_axi_awvalid(m01_regslice_to_m01_couplers_AWVALID),\n        .m_axi_bid(m01_regslice_to_m01_couplers_BID),\n        .m_axi_bready(m01_regslice_to_m01_couplers_BREADY),\n        .m_axi_bresp(m01_regslice_to_m01_couplers_BRESP),\n        .m_axi_bvalid(m01_regslice_to_m01_couplers_BVALID),\n        .m_axi_rdata(m01_regslice_to_m01_couplers_RDATA),\n        .m_axi_rid(m01_regslice_to_m01_couplers_RID),\n        .m_axi_rlast(m01_regslice_to_m01_couplers_RLAST),\n        .m_axi_rready(m01_regslice_to_m01_couplers_RREADY),\n        .m_axi_rresp(m01_regslice_to_m01_couplers_RRESP),\n        .m_axi_rvalid(m01_regslice_to_m01_couplers_RVALID),\n        .m_axi_wdata(m01_regslice_to_m01_couplers_WDATA),\n        .m_axi_wlast(m01_regslice_to_m01_couplers_WLAST),\n        .m_axi_wready(m01_regslice_to_m01_couplers_WREADY),\n        .m_axi_wstrb(m01_regslice_to_m01_couplers_WSTRB),\n        .m_axi_wvalid(m01_regslice_to_m01_couplers_WVALID),\n        .s_axi_araddr(m01_couplers_to_m01_regslice_ARADDR),\n        .s_axi_arburst(m01_couplers_to_m01_regslice_ARBURST),\n        .s_axi_arcache(m01_couplers_to_m01_regslice_ARCACHE),\n        .s_axi_arid(m01_couplers_to_m01_regslice_ARID),\n        .s_axi_arlen(m01_couplers_to_m01_regslice_ARLEN),\n        .s_axi_arlock(m01_couplers_to_m01_regslice_ARLOCK),\n        .s_axi_arprot(m01_couplers_to_m01_regslice_ARPROT),\n        .s_axi_arqos(m01_couplers_to_m01_regslice_ARQOS),\n        .s_axi_arready(m01_couplers_to_m01_regslice_ARREADY),\n        .s_axi_arregion(m01_couplers_to_m01_regslice_ARREGION),\n        .s_axi_arsize(m01_couplers_to_m01_regslice_ARSIZE),\n        .s_axi_arvalid(m01_couplers_to_m01_regslice_ARVALID),\n        .s_axi_awaddr(m01_couplers_to_m01_regslice_AWADDR),\n        .s_axi_awburst(m01_couplers_to_m01_regslice_AWBURST),\n        .s_axi_awcache(m01_couplers_to_m01_regslice_AWCACHE),\n        .s_axi_awid(m01_couplers_to_m01_regslice_AWID),\n        .s_axi_awlen(m01_couplers_to_m01_regslice_AWLEN),\n        .s_axi_awlock(m01_couplers_to_m01_regslice_AWLOCK),\n        .s_axi_awprot(m01_couplers_to_m01_regslice_AWPROT),\n        .s_axi_awqos(m01_couplers_to_m01_regslice_AWQOS),\n        .s_axi_awready(m01_couplers_to_m01_regslice_AWREADY),\n        .s_axi_awregion(m01_couplers_to_m01_regslice_AWREGION),\n        .s_axi_awsize(m01_couplers_to_m01_regslice_AWSIZE),\n        .s_axi_awvalid(m01_couplers_to_m01_regslice_AWVALID),\n        .s_axi_bid(m01_couplers_to_m01_regslice_BID),\n        .s_axi_bready(m01_couplers_to_m01_regslice_BREADY),\n        .s_axi_bresp(m01_couplers_to_m01_regslice_BRESP),\n        .s_axi_bvalid(m01_couplers_to_m01_regslice_BVALID),\n        .s_axi_rdata(m01_couplers_to_m01_regslice_RDATA),\n        .s_axi_rid(m01_couplers_to_m01_regslice_RID),\n        .s_axi_rlast(m01_couplers_to_m01_regslice_RLAST),\n        .s_axi_rready(m01_couplers_to_m01_regslice_RREADY),\n        .s_axi_rresp(m01_couplers_to_m01_regslice_RRESP),\n        .s_axi_rvalid(m01_couplers_to_m01_regslice_RVALID),\n        .s_axi_wdata(m01_couplers_to_m01_regslice_WDATA),\n        .s_axi_wlast(m01_couplers_to_m01_regslice_WLAST),\n        .s_axi_wready(m01_couplers_to_m01_regslice_WREADY),\n        .s_axi_wstrb(m01_couplers_to_m01_regslice_WSTRB),\n        .s_axi_wvalid(m01_couplers_to_m01_regslice_WVALID));\nendmodule\n\nmodule m02_couplers_imp_APDUS2\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m02_couplers_to_m02_regslice_ARADDR;\n  wire [1:0]m02_couplers_to_m02_regslice_ARBURST;\n  wire [3:0]m02_couplers_to_m02_regslice_ARCACHE;\n  wire [6:0]m02_couplers_to_m02_regslice_ARID;\n  wire [7:0]m02_couplers_to_m02_regslice_ARLEN;\n  wire [0:0]m02_couplers_to_m02_regslice_ARLOCK;\n  wire [2:0]m02_couplers_to_m02_regslice_ARPROT;\n  wire [3:0]m02_couplers_to_m02_regslice_ARQOS;\n  wire m02_couplers_to_m02_regslice_ARREADY;\n  wire [3:0]m02_couplers_to_m02_regslice_ARREGION;\n  wire [2:0]m02_couplers_to_m02_regslice_ARSIZE;\n  wire m02_couplers_to_m02_regslice_ARVALID;\n  wire [63:0]m02_couplers_to_m02_regslice_AWADDR;\n  wire [1:0]m02_couplers_to_m02_regslice_AWBURST;\n  wire [3:0]m02_couplers_to_m02_regslice_AWCACHE;\n  wire [6:0]m02_couplers_to_m02_regslice_AWID;\n  wire [7:0]m02_couplers_to_m02_regslice_AWLEN;\n  wire [0:0]m02_couplers_to_m02_regslice_AWLOCK;\n  wire [2:0]m02_couplers_to_m02_regslice_AWPROT;\n  wire [3:0]m02_couplers_to_m02_regslice_AWQOS;\n  wire m02_couplers_to_m02_regslice_AWREADY;\n  wire [3:0]m02_couplers_to_m02_regslice_AWREGION;\n  wire [2:0]m02_couplers_to_m02_regslice_AWSIZE;\n  wire m02_couplers_to_m02_regslice_AWVALID;\n  wire [6:0]m02_couplers_to_m02_regslice_BID;\n  wire m02_couplers_to_m02_regslice_BREADY;\n  wire [1:0]m02_couplers_to_m02_regslice_BRESP;\n  wire m02_couplers_to_m02_regslice_BVALID;\n  wire [511:0]m02_couplers_to_m02_regslice_RDATA;\n  wire [6:0]m02_couplers_to_m02_regslice_RID;\n  wire m02_couplers_to_m02_regslice_RLAST;\n  wire m02_couplers_to_m02_regslice_RREADY;\n  wire [1:0]m02_couplers_to_m02_regslice_RRESP;\n  wire m02_couplers_to_m02_regslice_RVALID;\n  wire [511:0]m02_couplers_to_m02_regslice_WDATA;\n  wire m02_couplers_to_m02_regslice_WLAST;\n  wire m02_couplers_to_m02_regslice_WREADY;\n  wire [63:0]m02_couplers_to_m02_regslice_WSTRB;\n  wire m02_couplers_to_m02_regslice_WVALID;\n  wire [63:0]m02_regslice_to_m02_couplers_ARADDR;\n  wire [1:0]m02_regslice_to_m02_couplers_ARBURST;\n  wire [3:0]m02_regslice_to_m02_couplers_ARCACHE;\n  wire [6:0]m02_regslice_to_m02_couplers_ARID;\n  wire [7:0]m02_regslice_to_m02_couplers_ARLEN;\n  wire [0:0]m02_regslice_to_m02_couplers_ARLOCK;\n  wire [2:0]m02_regslice_to_m02_couplers_ARPROT;\n  wire [3:0]m02_regslice_to_m02_couplers_ARQOS;\n  wire m02_regslice_to_m02_couplers_ARREADY;\n  wire [3:0]m02_regslice_to_m02_couplers_ARREGION;\n  wire [2:0]m02_regslice_to_m02_couplers_ARSIZE;\n  wire m02_regslice_to_m02_couplers_ARVALID;\n  wire [63:0]m02_regslice_to_m02_couplers_AWADDR;\n  wire [1:0]m02_regslice_to_m02_couplers_AWBURST;\n  wire [3:0]m02_regslice_to_m02_couplers_AWCACHE;\n  wire [6:0]m02_regslice_to_m02_couplers_AWID;\n  wire [7:0]m02_regslice_to_m02_couplers_AWLEN;\n  wire [0:0]m02_regslice_to_m02_couplers_AWLOCK;\n  wire [2:0]m02_regslice_to_m02_couplers_AWPROT;\n  wire [3:0]m02_regslice_to_m02_couplers_AWQOS;\n  wire m02_regslice_to_m02_couplers_AWREADY;\n  wire [3:0]m02_regslice_to_m02_couplers_AWREGION;\n  wire [2:0]m02_regslice_to_m02_couplers_AWSIZE;\n  wire m02_regslice_to_m02_couplers_AWVALID;\n  wire [6:0]m02_regslice_to_m02_couplers_BID;\n  wire m02_regslice_to_m02_couplers_BREADY;\n  wire [1:0]m02_regslice_to_m02_couplers_BRESP;\n  wire m02_regslice_to_m02_couplers_BVALID;\n  wire [511:0]m02_regslice_to_m02_couplers_RDATA;\n  wire [6:0]m02_regslice_to_m02_couplers_RID;\n  wire m02_regslice_to_m02_couplers_RLAST;\n  wire m02_regslice_to_m02_couplers_RREADY;\n  wire [1:0]m02_regslice_to_m02_couplers_RRESP;\n  wire m02_regslice_to_m02_couplers_RVALID;\n  wire [511:0]m02_regslice_to_m02_couplers_WDATA;\n  wire m02_regslice_to_m02_couplers_WLAST;\n  wire m02_regslice_to_m02_couplers_WREADY;\n  wire [63:0]m02_regslice_to_m02_couplers_WSTRB;\n  wire m02_regslice_to_m02_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m02_regslice_to_m02_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m02_regslice_to_m02_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m02_regslice_to_m02_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m02_regslice_to_m02_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m02_regslice_to_m02_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m02_regslice_to_m02_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m02_regslice_to_m02_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m02_regslice_to_m02_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m02_regslice_to_m02_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m02_regslice_to_m02_couplers_ARSIZE;\n  assign M_AXI_arvalid = m02_regslice_to_m02_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m02_regslice_to_m02_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m02_regslice_to_m02_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m02_regslice_to_m02_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m02_regslice_to_m02_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m02_regslice_to_m02_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m02_regslice_to_m02_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m02_regslice_to_m02_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m02_regslice_to_m02_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m02_regslice_to_m02_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m02_regslice_to_m02_couplers_AWSIZE;\n  assign M_AXI_awvalid = m02_regslice_to_m02_couplers_AWVALID;\n  assign M_AXI_bready = m02_regslice_to_m02_couplers_BREADY;\n  assign M_AXI_rready = m02_regslice_to_m02_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m02_regslice_to_m02_couplers_WDATA;\n  assign M_AXI_wlast = m02_regslice_to_m02_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m02_regslice_to_m02_couplers_WSTRB;\n  assign M_AXI_wvalid = m02_regslice_to_m02_couplers_WVALID;\n  assign S_AXI_arready = m02_couplers_to_m02_regslice_ARREADY;\n  assign S_AXI_awready = m02_couplers_to_m02_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m02_couplers_to_m02_regslice_BID;\n  assign S_AXI_bresp[1:0] = m02_couplers_to_m02_regslice_BRESP;\n  assign S_AXI_bvalid = m02_couplers_to_m02_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m02_couplers_to_m02_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m02_couplers_to_m02_regslice_RID;\n  assign S_AXI_rlast = m02_couplers_to_m02_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m02_couplers_to_m02_regslice_RRESP;\n  assign S_AXI_rvalid = m02_couplers_to_m02_regslice_RVALID;\n  assign S_AXI_wready = m02_couplers_to_m02_regslice_WREADY;\n  assign m02_couplers_to_m02_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m02_couplers_to_m02_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m02_couplers_to_m02_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m02_couplers_to_m02_regslice_ARID = S_AXI_arid[6:0];\n  assign m02_couplers_to_m02_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m02_couplers_to_m02_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m02_couplers_to_m02_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m02_couplers_to_m02_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m02_couplers_to_m02_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m02_couplers_to_m02_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m02_couplers_to_m02_regslice_ARVALID = S_AXI_arvalid;\n  assign m02_couplers_to_m02_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m02_couplers_to_m02_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m02_couplers_to_m02_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m02_couplers_to_m02_regslice_AWID = S_AXI_awid[6:0];\n  assign m02_couplers_to_m02_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m02_couplers_to_m02_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m02_couplers_to_m02_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m02_couplers_to_m02_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m02_couplers_to_m02_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m02_couplers_to_m02_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m02_couplers_to_m02_regslice_AWVALID = S_AXI_awvalid;\n  assign m02_couplers_to_m02_regslice_BREADY = S_AXI_bready;\n  assign m02_couplers_to_m02_regslice_RREADY = S_AXI_rready;\n  assign m02_couplers_to_m02_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m02_couplers_to_m02_regslice_WLAST = S_AXI_wlast;\n  assign m02_couplers_to_m02_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m02_couplers_to_m02_regslice_WVALID = S_AXI_wvalid;\n  assign m02_regslice_to_m02_couplers_ARREADY = M_AXI_arready;\n  assign m02_regslice_to_m02_couplers_AWREADY = M_AXI_awready;\n  assign m02_regslice_to_m02_couplers_BID = M_AXI_bid[6:0];\n  assign m02_regslice_to_m02_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m02_regslice_to_m02_couplers_BVALID = M_AXI_bvalid;\n  assign m02_regslice_to_m02_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m02_regslice_to_m02_couplers_RID = M_AXI_rid[6:0];\n  assign m02_regslice_to_m02_couplers_RLAST = M_AXI_rlast;\n  assign m02_regslice_to_m02_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m02_regslice_to_m02_couplers_RVALID = M_AXI_rvalid;\n  assign m02_regslice_to_m02_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m02_regslice_0 m02_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m02_regslice_to_m02_couplers_ARADDR),\n        .m_axi_arburst(m02_regslice_to_m02_couplers_ARBURST),\n        .m_axi_arcache(m02_regslice_to_m02_couplers_ARCACHE),\n        .m_axi_arid(m02_regslice_to_m02_couplers_ARID),\n        .m_axi_arlen(m02_regslice_to_m02_couplers_ARLEN),\n        .m_axi_arlock(m02_regslice_to_m02_couplers_ARLOCK),\n        .m_axi_arprot(m02_regslice_to_m02_couplers_ARPROT),\n        .m_axi_arqos(m02_regslice_to_m02_couplers_ARQOS),\n        .m_axi_arready(m02_regslice_to_m02_couplers_ARREADY),\n        .m_axi_arregion(m02_regslice_to_m02_couplers_ARREGION),\n        .m_axi_arsize(m02_regslice_to_m02_couplers_ARSIZE),\n        .m_axi_arvalid(m02_regslice_to_m02_couplers_ARVALID),\n        .m_axi_awaddr(m02_regslice_to_m02_couplers_AWADDR),\n        .m_axi_awburst(m02_regslice_to_m02_couplers_AWBURST),\n        .m_axi_awcache(m02_regslice_to_m02_couplers_AWCACHE),\n        .m_axi_awid(m02_regslice_to_m02_couplers_AWID),\n        .m_axi_awlen(m02_regslice_to_m02_couplers_AWLEN),\n        .m_axi_awlock(m02_regslice_to_m02_couplers_AWLOCK),\n        .m_axi_awprot(m02_regslice_to_m02_couplers_AWPROT),\n        .m_axi_awqos(m02_regslice_to_m02_couplers_AWQOS),\n        .m_axi_awready(m02_regslice_to_m02_couplers_AWREADY),\n        .m_axi_awregion(m02_regslice_to_m02_couplers_AWREGION),\n        .m_axi_awsize(m02_regslice_to_m02_couplers_AWSIZE),\n        .m_axi_awvalid(m02_regslice_to_m02_couplers_AWVALID),\n        .m_axi_bid(m02_regslice_to_m02_couplers_BID),\n        .m_axi_bready(m02_regslice_to_m02_couplers_BREADY),\n        .m_axi_bresp(m02_regslice_to_m02_couplers_BRESP),\n        .m_axi_bvalid(m02_regslice_to_m02_couplers_BVALID),\n        .m_axi_rdata(m02_regslice_to_m02_couplers_RDATA),\n        .m_axi_rid(m02_regslice_to_m02_couplers_RID),\n        .m_axi_rlast(m02_regslice_to_m02_couplers_RLAST),\n        .m_axi_rready(m02_regslice_to_m02_couplers_RREADY),\n        .m_axi_rresp(m02_regslice_to_m02_couplers_RRESP),\n        .m_axi_rvalid(m02_regslice_to_m02_couplers_RVALID),\n        .m_axi_wdata(m02_regslice_to_m02_couplers_WDATA),\n        .m_axi_wlast(m02_regslice_to_m02_couplers_WLAST),\n        .m_axi_wready(m02_regslice_to_m02_couplers_WREADY),\n        .m_axi_wstrb(m02_regslice_to_m02_couplers_WSTRB),\n        .m_axi_wvalid(m02_regslice_to_m02_couplers_WVALID),\n        .s_axi_araddr(m02_couplers_to_m02_regslice_ARADDR),\n        .s_axi_arburst(m02_couplers_to_m02_regslice_ARBURST),\n        .s_axi_arcache(m02_couplers_to_m02_regslice_ARCACHE),\n        .s_axi_arid(m02_couplers_to_m02_regslice_ARID),\n        .s_axi_arlen(m02_couplers_to_m02_regslice_ARLEN),\n        .s_axi_arlock(m02_couplers_to_m02_regslice_ARLOCK),\n        .s_axi_arprot(m02_couplers_to_m02_regslice_ARPROT),\n        .s_axi_arqos(m02_couplers_to_m02_regslice_ARQOS),\n        .s_axi_arready(m02_couplers_to_m02_regslice_ARREADY),\n        .s_axi_arregion(m02_couplers_to_m02_regslice_ARREGION),\n        .s_axi_arsize(m02_couplers_to_m02_regslice_ARSIZE),\n        .s_axi_arvalid(m02_couplers_to_m02_regslice_ARVALID),\n        .s_axi_awaddr(m02_couplers_to_m02_regslice_AWADDR),\n        .s_axi_awburst(m02_couplers_to_m02_regslice_AWBURST),\n        .s_axi_awcache(m02_couplers_to_m02_regslice_AWCACHE),\n        .s_axi_awid(m02_couplers_to_m02_regslice_AWID),\n        .s_axi_awlen(m02_couplers_to_m02_regslice_AWLEN),\n        .s_axi_awlock(m02_couplers_to_m02_regslice_AWLOCK),\n        .s_axi_awprot(m02_couplers_to_m02_regslice_AWPROT),\n        .s_axi_awqos(m02_couplers_to_m02_regslice_AWQOS),\n        .s_axi_awready(m02_couplers_to_m02_regslice_AWREADY),\n        .s_axi_awregion(m02_couplers_to_m02_regslice_AWREGION),\n        .s_axi_awsize(m02_couplers_to_m02_regslice_AWSIZE),\n        .s_axi_awvalid(m02_couplers_to_m02_regslice_AWVALID),\n        .s_axi_bid(m02_couplers_to_m02_regslice_BID),\n        .s_axi_bready(m02_couplers_to_m02_regslice_BREADY),\n        .s_axi_bresp(m02_couplers_to_m02_regslice_BRESP),\n        .s_axi_bvalid(m02_couplers_to_m02_regslice_BVALID),\n        .s_axi_rdata(m02_couplers_to_m02_regslice_RDATA),\n        .s_axi_rid(m02_couplers_to_m02_regslice_RID),\n        .s_axi_rlast(m02_couplers_to_m02_regslice_RLAST),\n        .s_axi_rready(m02_couplers_to_m02_regslice_RREADY),\n        .s_axi_rresp(m02_couplers_to_m02_regslice_RRESP),\n        .s_axi_rvalid(m02_couplers_to_m02_regslice_RVALID),\n        .s_axi_wdata(m02_couplers_to_m02_regslice_WDATA),\n        .s_axi_wlast(m02_couplers_to_m02_regslice_WLAST),\n        .s_axi_wready(m02_couplers_to_m02_regslice_WREADY),\n        .s_axi_wstrb(m02_couplers_to_m02_regslice_WSTRB),\n        .s_axi_wvalid(m02_couplers_to_m02_regslice_WVALID));\nendmodule\n\nmodule m03_couplers_imp_JAYOMU\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m03_couplers_to_m03_regslice_ARADDR;\n  wire [1:0]m03_couplers_to_m03_regslice_ARBURST;\n  wire [3:0]m03_couplers_to_m03_regslice_ARCACHE;\n  wire [6:0]m03_couplers_to_m03_regslice_ARID;\n  wire [7:0]m03_couplers_to_m03_regslice_ARLEN;\n  wire [0:0]m03_couplers_to_m03_regslice_ARLOCK;\n  wire [2:0]m03_couplers_to_m03_regslice_ARPROT;\n  wire [3:0]m03_couplers_to_m03_regslice_ARQOS;\n  wire m03_couplers_to_m03_regslice_ARREADY;\n  wire [3:0]m03_couplers_to_m03_regslice_ARREGION;\n  wire [2:0]m03_couplers_to_m03_regslice_ARSIZE;\n  wire m03_couplers_to_m03_regslice_ARVALID;\n  wire [63:0]m03_couplers_to_m03_regslice_AWADDR;\n  wire [1:0]m03_couplers_to_m03_regslice_AWBURST;\n  wire [3:0]m03_couplers_to_m03_regslice_AWCACHE;\n  wire [6:0]m03_couplers_to_m03_regslice_AWID;\n  wire [7:0]m03_couplers_to_m03_regslice_AWLEN;\n  wire [0:0]m03_couplers_to_m03_regslice_AWLOCK;\n  wire [2:0]m03_couplers_to_m03_regslice_AWPROT;\n  wire [3:0]m03_couplers_to_m03_regslice_AWQOS;\n  wire m03_couplers_to_m03_regslice_AWREADY;\n  wire [3:0]m03_couplers_to_m03_regslice_AWREGION;\n  wire [2:0]m03_couplers_to_m03_regslice_AWSIZE;\n  wire m03_couplers_to_m03_regslice_AWVALID;\n  wire [6:0]m03_couplers_to_m03_regslice_BID;\n  wire m03_couplers_to_m03_regslice_BREADY;\n  wire [1:0]m03_couplers_to_m03_regslice_BRESP;\n  wire m03_couplers_to_m03_regslice_BVALID;\n  wire [511:0]m03_couplers_to_m03_regslice_RDATA;\n  wire [6:0]m03_couplers_to_m03_regslice_RID;\n  wire m03_couplers_to_m03_regslice_RLAST;\n  wire m03_couplers_to_m03_regslice_RREADY;\n  wire [1:0]m03_couplers_to_m03_regslice_RRESP;\n  wire m03_couplers_to_m03_regslice_RVALID;\n  wire [511:0]m03_couplers_to_m03_regslice_WDATA;\n  wire m03_couplers_to_m03_regslice_WLAST;\n  wire m03_couplers_to_m03_regslice_WREADY;\n  wire [63:0]m03_couplers_to_m03_regslice_WSTRB;\n  wire m03_couplers_to_m03_regslice_WVALID;\n  wire [63:0]m03_regslice_to_m03_couplers_ARADDR;\n  wire [1:0]m03_regslice_to_m03_couplers_ARBURST;\n  wire [3:0]m03_regslice_to_m03_couplers_ARCACHE;\n  wire [6:0]m03_regslice_to_m03_couplers_ARID;\n  wire [7:0]m03_regslice_to_m03_couplers_ARLEN;\n  wire [0:0]m03_regslice_to_m03_couplers_ARLOCK;\n  wire [2:0]m03_regslice_to_m03_couplers_ARPROT;\n  wire [3:0]m03_regslice_to_m03_couplers_ARQOS;\n  wire m03_regslice_to_m03_couplers_ARREADY;\n  wire [3:0]m03_regslice_to_m03_couplers_ARREGION;\n  wire [2:0]m03_regslice_to_m03_couplers_ARSIZE;\n  wire m03_regslice_to_m03_couplers_ARVALID;\n  wire [63:0]m03_regslice_to_m03_couplers_AWADDR;\n  wire [1:0]m03_regslice_to_m03_couplers_AWBURST;\n  wire [3:0]m03_regslice_to_m03_couplers_AWCACHE;\n  wire [6:0]m03_regslice_to_m03_couplers_AWID;\n  wire [7:0]m03_regslice_to_m03_couplers_AWLEN;\n  wire [0:0]m03_regslice_to_m03_couplers_AWLOCK;\n  wire [2:0]m03_regslice_to_m03_couplers_AWPROT;\n  wire [3:0]m03_regslice_to_m03_couplers_AWQOS;\n  wire m03_regslice_to_m03_couplers_AWREADY;\n  wire [3:0]m03_regslice_to_m03_couplers_AWREGION;\n  wire [2:0]m03_regslice_to_m03_couplers_AWSIZE;\n  wire m03_regslice_to_m03_couplers_AWVALID;\n  wire [6:0]m03_regslice_to_m03_couplers_BID;\n  wire m03_regslice_to_m03_couplers_BREADY;\n  wire [1:0]m03_regslice_to_m03_couplers_BRESP;\n  wire m03_regslice_to_m03_couplers_BVALID;\n  wire [511:0]m03_regslice_to_m03_couplers_RDATA;\n  wire [6:0]m03_regslice_to_m03_couplers_RID;\n  wire m03_regslice_to_m03_couplers_RLAST;\n  wire m03_regslice_to_m03_couplers_RREADY;\n  wire [1:0]m03_regslice_to_m03_couplers_RRESP;\n  wire m03_regslice_to_m03_couplers_RVALID;\n  wire [511:0]m03_regslice_to_m03_couplers_WDATA;\n  wire m03_regslice_to_m03_couplers_WLAST;\n  wire m03_regslice_to_m03_couplers_WREADY;\n  wire [63:0]m03_regslice_to_m03_couplers_WSTRB;\n  wire m03_regslice_to_m03_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m03_regslice_to_m03_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m03_regslice_to_m03_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m03_regslice_to_m03_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m03_regslice_to_m03_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m03_regslice_to_m03_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m03_regslice_to_m03_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m03_regslice_to_m03_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m03_regslice_to_m03_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m03_regslice_to_m03_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m03_regslice_to_m03_couplers_ARSIZE;\n  assign M_AXI_arvalid = m03_regslice_to_m03_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m03_regslice_to_m03_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m03_regslice_to_m03_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m03_regslice_to_m03_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m03_regslice_to_m03_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m03_regslice_to_m03_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m03_regslice_to_m03_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m03_regslice_to_m03_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m03_regslice_to_m03_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m03_regslice_to_m03_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m03_regslice_to_m03_couplers_AWSIZE;\n  assign M_AXI_awvalid = m03_regslice_to_m03_couplers_AWVALID;\n  assign M_AXI_bready = m03_regslice_to_m03_couplers_BREADY;\n  assign M_AXI_rready = m03_regslice_to_m03_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m03_regslice_to_m03_couplers_WDATA;\n  assign M_AXI_wlast = m03_regslice_to_m03_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m03_regslice_to_m03_couplers_WSTRB;\n  assign M_AXI_wvalid = m03_regslice_to_m03_couplers_WVALID;\n  assign S_AXI_arready = m03_couplers_to_m03_regslice_ARREADY;\n  assign S_AXI_awready = m03_couplers_to_m03_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m03_couplers_to_m03_regslice_BID;\n  assign S_AXI_bresp[1:0] = m03_couplers_to_m03_regslice_BRESP;\n  assign S_AXI_bvalid = m03_couplers_to_m03_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m03_couplers_to_m03_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m03_couplers_to_m03_regslice_RID;\n  assign S_AXI_rlast = m03_couplers_to_m03_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m03_couplers_to_m03_regslice_RRESP;\n  assign S_AXI_rvalid = m03_couplers_to_m03_regslice_RVALID;\n  assign S_AXI_wready = m03_couplers_to_m03_regslice_WREADY;\n  assign m03_couplers_to_m03_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m03_couplers_to_m03_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m03_couplers_to_m03_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m03_couplers_to_m03_regslice_ARID = S_AXI_arid[6:0];\n  assign m03_couplers_to_m03_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m03_couplers_to_m03_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m03_couplers_to_m03_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m03_couplers_to_m03_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m03_couplers_to_m03_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m03_couplers_to_m03_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m03_couplers_to_m03_regslice_ARVALID = S_AXI_arvalid;\n  assign m03_couplers_to_m03_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m03_couplers_to_m03_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m03_couplers_to_m03_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m03_couplers_to_m03_regslice_AWID = S_AXI_awid[6:0];\n  assign m03_couplers_to_m03_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m03_couplers_to_m03_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m03_couplers_to_m03_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m03_couplers_to_m03_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m03_couplers_to_m03_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m03_couplers_to_m03_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m03_couplers_to_m03_regslice_AWVALID = S_AXI_awvalid;\n  assign m03_couplers_to_m03_regslice_BREADY = S_AXI_bready;\n  assign m03_couplers_to_m03_regslice_RREADY = S_AXI_rready;\n  assign m03_couplers_to_m03_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m03_couplers_to_m03_regslice_WLAST = S_AXI_wlast;\n  assign m03_couplers_to_m03_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m03_couplers_to_m03_regslice_WVALID = S_AXI_wvalid;\n  assign m03_regslice_to_m03_couplers_ARREADY = M_AXI_arready;\n  assign m03_regslice_to_m03_couplers_AWREADY = M_AXI_awready;\n  assign m03_regslice_to_m03_couplers_BID = M_AXI_bid[6:0];\n  assign m03_regslice_to_m03_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m03_regslice_to_m03_couplers_BVALID = M_AXI_bvalid;\n  assign m03_regslice_to_m03_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m03_regslice_to_m03_couplers_RID = M_AXI_rid[6:0];\n  assign m03_regslice_to_m03_couplers_RLAST = M_AXI_rlast;\n  assign m03_regslice_to_m03_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m03_regslice_to_m03_couplers_RVALID = M_AXI_rvalid;\n  assign m03_regslice_to_m03_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m03_regslice_0 m03_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m03_regslice_to_m03_couplers_ARADDR),\n        .m_axi_arburst(m03_regslice_to_m03_couplers_ARBURST),\n        .m_axi_arcache(m03_regslice_to_m03_couplers_ARCACHE),\n        .m_axi_arid(m03_regslice_to_m03_couplers_ARID),\n        .m_axi_arlen(m03_regslice_to_m03_couplers_ARLEN),\n        .m_axi_arlock(m03_regslice_to_m03_couplers_ARLOCK),\n        .m_axi_arprot(m03_regslice_to_m03_couplers_ARPROT),\n        .m_axi_arqos(m03_regslice_to_m03_couplers_ARQOS),\n        .m_axi_arready(m03_regslice_to_m03_couplers_ARREADY),\n        .m_axi_arregion(m03_regslice_to_m03_couplers_ARREGION),\n        .m_axi_arsize(m03_regslice_to_m03_couplers_ARSIZE),\n        .m_axi_arvalid(m03_regslice_to_m03_couplers_ARVALID),\n        .m_axi_awaddr(m03_regslice_to_m03_couplers_AWADDR),\n        .m_axi_awburst(m03_regslice_to_m03_couplers_AWBURST),\n        .m_axi_awcache(m03_regslice_to_m03_couplers_AWCACHE),\n        .m_axi_awid(m03_regslice_to_m03_couplers_AWID),\n        .m_axi_awlen(m03_regslice_to_m03_couplers_AWLEN),\n        .m_axi_awlock(m03_regslice_to_m03_couplers_AWLOCK),\n        .m_axi_awprot(m03_regslice_to_m03_couplers_AWPROT),\n        .m_axi_awqos(m03_regslice_to_m03_couplers_AWQOS),\n        .m_axi_awready(m03_regslice_to_m03_couplers_AWREADY),\n        .m_axi_awregion(m03_regslice_to_m03_couplers_AWREGION),\n        .m_axi_awsize(m03_regslice_to_m03_couplers_AWSIZE),\n        .m_axi_awvalid(m03_regslice_to_m03_couplers_AWVALID),\n        .m_axi_bid(m03_regslice_to_m03_couplers_BID),\n        .m_axi_bready(m03_regslice_to_m03_couplers_BREADY),\n        .m_axi_bresp(m03_regslice_to_m03_couplers_BRESP),\n        .m_axi_bvalid(m03_regslice_to_m03_couplers_BVALID),\n        .m_axi_rdata(m03_regslice_to_m03_couplers_RDATA),\n        .m_axi_rid(m03_regslice_to_m03_couplers_RID),\n        .m_axi_rlast(m03_regslice_to_m03_couplers_RLAST),\n        .m_axi_rready(m03_regslice_to_m03_couplers_RREADY),\n        .m_axi_rresp(m03_regslice_to_m03_couplers_RRESP),\n        .m_axi_rvalid(m03_regslice_to_m03_couplers_RVALID),\n        .m_axi_wdata(m03_regslice_to_m03_couplers_WDATA),\n        .m_axi_wlast(m03_regslice_to_m03_couplers_WLAST),\n        .m_axi_wready(m03_regslice_to_m03_couplers_WREADY),\n        .m_axi_wstrb(m03_regslice_to_m03_couplers_WSTRB),\n        .m_axi_wvalid(m03_regslice_to_m03_couplers_WVALID),\n        .s_axi_araddr(m03_couplers_to_m03_regslice_ARADDR),\n        .s_axi_arburst(m03_couplers_to_m03_regslice_ARBURST),\n        .s_axi_arcache(m03_couplers_to_m03_regslice_ARCACHE),\n        .s_axi_arid(m03_couplers_to_m03_regslice_ARID),\n        .s_axi_arlen(m03_couplers_to_m03_regslice_ARLEN),\n        .s_axi_arlock(m03_couplers_to_m03_regslice_ARLOCK),\n        .s_axi_arprot(m03_couplers_to_m03_regslice_ARPROT),\n        .s_axi_arqos(m03_couplers_to_m03_regslice_ARQOS),\n        .s_axi_arready(m03_couplers_to_m03_regslice_ARREADY),\n        .s_axi_arregion(m03_couplers_to_m03_regslice_ARREGION),\n        .s_axi_arsize(m03_couplers_to_m03_regslice_ARSIZE),\n        .s_axi_arvalid(m03_couplers_to_m03_regslice_ARVALID),\n        .s_axi_awaddr(m03_couplers_to_m03_regslice_AWADDR),\n        .s_axi_awburst(m03_couplers_to_m03_regslice_AWBURST),\n        .s_axi_awcache(m03_couplers_to_m03_regslice_AWCACHE),\n        .s_axi_awid(m03_couplers_to_m03_regslice_AWID),\n        .s_axi_awlen(m03_couplers_to_m03_regslice_AWLEN),\n        .s_axi_awlock(m03_couplers_to_m03_regslice_AWLOCK),\n        .s_axi_awprot(m03_couplers_to_m03_regslice_AWPROT),\n        .s_axi_awqos(m03_couplers_to_m03_regslice_AWQOS),\n        .s_axi_awready(m03_couplers_to_m03_regslice_AWREADY),\n        .s_axi_awregion(m03_couplers_to_m03_regslice_AWREGION),\n        .s_axi_awsize(m03_couplers_to_m03_regslice_AWSIZE),\n        .s_axi_awvalid(m03_couplers_to_m03_regslice_AWVALID),\n        .s_axi_bid(m03_couplers_to_m03_regslice_BID),\n        .s_axi_bready(m03_couplers_to_m03_regslice_BREADY),\n        .s_axi_bresp(m03_couplers_to_m03_regslice_BRESP),\n        .s_axi_bvalid(m03_couplers_to_m03_regslice_BVALID),\n        .s_axi_rdata(m03_couplers_to_m03_regslice_RDATA),\n        .s_axi_rid(m03_couplers_to_m03_regslice_RID),\n        .s_axi_rlast(m03_couplers_to_m03_regslice_RLAST),\n        .s_axi_rready(m03_couplers_to_m03_regslice_RREADY),\n        .s_axi_rresp(m03_couplers_to_m03_regslice_RRESP),\n        .s_axi_rvalid(m03_couplers_to_m03_regslice_RVALID),\n        .s_axi_wdata(m03_couplers_to_m03_regslice_WDATA),\n        .s_axi_wlast(m03_couplers_to_m03_regslice_WLAST),\n        .s_axi_wready(m03_couplers_to_m03_regslice_WREADY),\n        .s_axi_wstrb(m03_couplers_to_m03_regslice_WSTRB),\n        .s_axi_wvalid(m03_couplers_to_m03_regslice_WVALID));\nendmodule\n\nmodule s00_couplers_imp_QICM5G\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [5:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [5:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [5:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [5:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [5:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [5:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire S_ACLK_1;\n  wire S_ARESETN_1;\n  wire [63:0]s00_couplers_to_s00_regslice_ARADDR;\n  wire [1:0]s00_couplers_to_s00_regslice_ARBURST;\n  wire [3:0]s00_couplers_to_s00_regslice_ARCACHE;\n  wire [5:0]s00_couplers_to_s00_regslice_ARID;\n  wire [7:0]s00_couplers_to_s00_regslice_ARLEN;\n  wire [0:0]s00_couplers_to_s00_regslice_ARLOCK;\n  wire [2:0]s00_couplers_to_s00_regslice_ARPROT;\n  wire [3:0]s00_couplers_to_s00_regslice_ARQOS;\n  wire s00_couplers_to_s00_regslice_ARREADY;\n  wire [3:0]s00_couplers_to_s00_regslice_ARREGION;\n  wire [2:0]s00_couplers_to_s00_regslice_ARSIZE;\n  wire s00_couplers_to_s00_regslice_ARVALID;\n  wire [63:0]s00_couplers_to_s00_regslice_AWADDR;\n  wire [1:0]s00_couplers_to_s00_regslice_AWBURST;\n  wire [3:0]s00_couplers_to_s00_regslice_AWCACHE;\n  wire [5:0]s00_couplers_to_s00_regslice_AWID;\n  wire [7:0]s00_couplers_to_s00_regslice_AWLEN;\n  wire [0:0]s00_couplers_to_s00_regslice_AWLOCK;\n  wire [2:0]s00_couplers_to_s00_regslice_AWPROT;\n  wire [3:0]s00_couplers_to_s00_regslice_AWQOS;\n  wire s00_couplers_to_s00_regslice_AWREADY;\n  wire [3:0]s00_couplers_to_s00_regslice_AWREGION;\n  wire [2:0]s00_couplers_to_s00_regslice_AWSIZE;\n  wire s00_couplers_to_s00_regslice_AWVALID;\n  wire [5:0]s00_couplers_to_s00_regslice_BID;\n  wire s00_couplers_to_s00_regslice_BREADY;\n  wire [1:0]s00_couplers_to_s00_regslice_BRESP;\n  wire s00_couplers_to_s00_regslice_BVALID;\n  wire [511:0]s00_couplers_to_s00_regslice_RDATA;\n  wire [5:0]s00_couplers_to_s00_regslice_RID;\n  wire s00_couplers_to_s00_regslice_RLAST;\n  wire s00_couplers_to_s00_regslice_RREADY;\n  wire [1:0]s00_couplers_to_s00_regslice_RRESP;\n  wire s00_couplers_to_s00_regslice_RVALID;\n  wire [511:0]s00_couplers_to_s00_regslice_WDATA;\n  wire s00_couplers_to_s00_regslice_WLAST;\n  wire s00_couplers_to_s00_regslice_WREADY;\n  wire [63:0]s00_couplers_to_s00_regslice_WSTRB;\n  wire s00_couplers_to_s00_regslice_WVALID;\n  wire [63:0]s00_regslice_to_s00_couplers_ARADDR;\n  wire [1:0]s00_regslice_to_s00_couplers_ARBURST;\n  wire [3:0]s00_regslice_to_s00_couplers_ARCACHE;\n  wire [5:0]s00_regslice_to_s00_couplers_ARID;\n  wire [7:0]s00_regslice_to_s00_couplers_ARLEN;\n  wire [0:0]s00_regslice_to_s00_couplers_ARLOCK;\n  wire [2:0]s00_regslice_to_s00_couplers_ARPROT;\n  wire [3:0]s00_regslice_to_s00_couplers_ARQOS;\n  wire s00_regslice_to_s00_couplers_ARREADY;\n  wire [2:0]s00_regslice_to_s00_couplers_ARSIZE;\n  wire s00_regslice_to_s00_couplers_ARVALID;\n  wire [63:0]s00_regslice_to_s00_couplers_AWADDR;\n  wire [1:0]s00_regslice_to_s00_couplers_AWBURST;\n  wire [3:0]s00_regslice_to_s00_couplers_AWCACHE;\n  wire [5:0]s00_regslice_to_s00_couplers_AWID;\n  wire [7:0]s00_regslice_to_s00_couplers_AWLEN;\n  wire [0:0]s00_regslice_to_s00_couplers_AWLOCK;\n  wire [2:0]s00_regslice_to_s00_couplers_AWPROT;\n  wire [3:0]s00_regslice_to_s00_couplers_AWQOS;\n  wire s00_regslice_to_s00_couplers_AWREADY;\n  wire [2:0]s00_regslice_to_s00_couplers_AWSIZE;\n  wire s00_regslice_to_s00_couplers_AWVALID;\n  wire [6:0]s00_regslice_to_s00_couplers_BID;\n  wire s00_regslice_to_s00_couplers_BREADY;\n  wire [1:0]s00_regslice_to_s00_couplers_BRESP;\n  wire s00_regslice_to_s00_couplers_BVALID;\n  wire [511:0]s00_regslice_to_s00_couplers_RDATA;\n  wire [6:0]s00_regslice_to_s00_couplers_RID;\n  wire s00_regslice_to_s00_couplers_RLAST;\n  wire s00_regslice_to_s00_couplers_RREADY;\n  wire [1:0]s00_regslice_to_s00_couplers_RRESP;\n  wire s00_regslice_to_s00_couplers_RVALID;\n  wire [511:0]s00_regslice_to_s00_couplers_WDATA;\n  wire s00_regslice_to_s00_couplers_WLAST;\n  wire s00_regslice_to_s00_couplers_WREADY;\n  wire [63:0]s00_regslice_to_s00_couplers_WSTRB;\n  wire s00_regslice_to_s00_couplers_WVALID;\n\n  assign M_AXI_araddr[63:0] = s00_regslice_to_s00_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = s00_regslice_to_s00_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = s00_regslice_to_s00_couplers_ARCACHE;\n  assign M_AXI_arid[5:0] = s00_regslice_to_s00_couplers_ARID;\n  assign M_AXI_arlen[7:0] = s00_regslice_to_s00_couplers_ARLEN;\n  assign M_AXI_arlock[0] = s00_regslice_to_s00_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = s00_regslice_to_s00_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = s00_regslice_to_s00_couplers_ARQOS;\n  assign M_AXI_arsize[2:0] = s00_regslice_to_s00_couplers_ARSIZE;\n  assign M_AXI_arvalid = s00_regslice_to_s00_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = s00_regslice_to_s00_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = s00_regslice_to_s00_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = s00_regslice_to_s00_couplers_AWCACHE;\n  assign M_AXI_awid[5:0] = s00_regslice_to_s00_couplers_AWID;\n  assign M_AXI_awlen[7:0] = s00_regslice_to_s00_couplers_AWLEN;\n  assign M_AXI_awlock[0] = s00_regslice_to_s00_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = s00_regslice_to_s00_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = s00_regslice_to_s00_couplers_AWQOS;\n  assign M_AXI_awsize[2:0] = s00_regslice_to_s00_couplers_AWSIZE;\n  assign M_AXI_awvalid = s00_regslice_to_s00_couplers_AWVALID;\n  assign M_AXI_bready = s00_regslice_to_s00_couplers_BREADY;\n  assign M_AXI_rready = s00_regslice_to_s00_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = s00_regslice_to_s00_couplers_WDATA;\n  assign M_AXI_wlast = s00_regslice_to_s00_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = s00_regslice_to_s00_couplers_WSTRB;\n  assign M_AXI_wvalid = s00_regslice_to_s00_couplers_WVALID;\n  assign S_ACLK_1 = S_ACLK;\n  assign S_ARESETN_1 = S_ARESETN;\n  assign S_AXI_arready = s00_couplers_to_s00_regslice_ARREADY;\n  assign S_AXI_awready = s00_couplers_to_s00_regslice_AWREADY;\n  assign S_AXI_bid[5:0] = s00_couplers_to_s00_regslice_BID;\n  assign S_AXI_bresp[1:0] = s00_couplers_to_s00_regslice_BRESP;\n  assign S_AXI_bvalid = s00_couplers_to_s00_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = s00_couplers_to_s00_regslice_RDATA;\n  assign S_AXI_rid[5:0] = s00_couplers_to_s00_regslice_RID;\n  assign S_AXI_rlast = s00_couplers_to_s00_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = s00_couplers_to_s00_regslice_RRESP;\n  assign S_AXI_rvalid = s00_couplers_to_s00_regslice_RVALID;\n  assign S_AXI_wready = s00_couplers_to_s00_regslice_WREADY;\n  assign s00_couplers_to_s00_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign s00_couplers_to_s00_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign s00_couplers_to_s00_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign s00_couplers_to_s00_regslice_ARID = S_AXI_arid[5:0];\n  assign s00_couplers_to_s00_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign s00_couplers_to_s00_regslice_ARLOCK = S_AXI_arlock[0];\n  assign s00_couplers_to_s00_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign s00_couplers_to_s00_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign s00_couplers_to_s00_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign s00_couplers_to_s00_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign s00_couplers_to_s00_regslice_ARVALID = S_AXI_arvalid;\n  assign s00_couplers_to_s00_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign s00_couplers_to_s00_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign s00_couplers_to_s00_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign s00_couplers_to_s00_regslice_AWID = S_AXI_awid[5:0];\n  assign s00_couplers_to_s00_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign s00_couplers_to_s00_regslice_AWLOCK = S_AXI_awlock[0];\n  assign s00_couplers_to_s00_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign s00_couplers_to_s00_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign s00_couplers_to_s00_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign s00_couplers_to_s00_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign s00_couplers_to_s00_regslice_AWVALID = S_AXI_awvalid;\n  assign s00_couplers_to_s00_regslice_BREADY = S_AXI_bready;\n  assign s00_couplers_to_s00_regslice_RREADY = S_AXI_rready;\n  assign s00_couplers_to_s00_regslice_WDATA = S_AXI_wdata[511:0];\n  assign s00_couplers_to_s00_regslice_WLAST = S_AXI_wlast;\n  assign s00_couplers_to_s00_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign s00_couplers_to_s00_regslice_WVALID = S_AXI_wvalid;\n  assign s00_regslice_to_s00_couplers_ARREADY = M_AXI_arready;\n  assign s00_regslice_to_s00_couplers_AWREADY = M_AXI_awready;\n  assign s00_regslice_to_s00_couplers_BID = M_AXI_bid[6:0];\n  assign s00_regslice_to_s00_couplers_BRESP = M_AXI_bresp[1:0];\n  assign s00_regslice_to_s00_couplers_BVALID = M_AXI_bvalid;\n  assign s00_regslice_to_s00_couplers_RDATA = M_AXI_rdata[511:0];\n  assign s00_regslice_to_s00_couplers_RID = M_AXI_rid[6:0];\n  assign s00_regslice_to_s00_couplers_RLAST = M_AXI_rlast;\n  assign s00_regslice_to_s00_couplers_RRESP = M_AXI_rresp[1:0];\n  assign s00_regslice_to_s00_couplers_RVALID = M_AXI_rvalid;\n  assign s00_regslice_to_s00_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_s00_regslice_0 s00_regslice\n       (.aclk(S_ACLK_1),\n        .aresetn(S_ARESETN_1),\n        .m_axi_araddr(s00_regslice_to_s00_couplers_ARADDR),\n        .m_axi_arburst(s00_regslice_to_s00_couplers_ARBURST),\n        .m_axi_arcache(s00_regslice_to_s00_couplers_ARCACHE),\n        .m_axi_arid(s00_regslice_to_s00_couplers_ARID),\n        .m_axi_arlen(s00_regslice_to_s00_couplers_ARLEN),\n        .m_axi_arlock(s00_regslice_to_s00_couplers_ARLOCK),\n        .m_axi_arprot(s00_regslice_to_s00_couplers_ARPROT),\n        .m_axi_arqos(s00_regslice_to_s00_couplers_ARQOS),\n        .m_axi_arready(s00_regslice_to_s00_couplers_ARREADY),\n        .m_axi_arsize(s00_regslice_to_s00_couplers_ARSIZE),\n        .m_axi_arvalid(s00_regslice_to_s00_couplers_ARVALID),\n        .m_axi_awaddr(s00_regslice_to_s00_couplers_AWADDR),\n        .m_axi_awburst(s00_regslice_to_s00_couplers_AWBURST),\n        .m_axi_awcache(s00_regslice_to_s00_couplers_AWCACHE),\n        .m_axi_awid(s00_regslice_to_s00_couplers_AWID),\n        .m_axi_awlen(s00_regslice_to_s00_couplers_AWLEN),\n        .m_axi_awlock(s00_regslice_to_s00_couplers_AWLOCK),\n        .m_axi_awprot(s00_regslice_to_s00_couplers_AWPROT),\n        .m_axi_awqos(s00_regslice_to_s00_couplers_AWQOS),\n        .m_axi_awready(s00_regslice_to_s00_couplers_AWREADY),\n        .m_axi_awsize(s00_regslice_to_s00_couplers_AWSIZE),\n        .m_axi_awvalid(s00_regslice_to_s00_couplers_AWVALID),\n        .m_axi_bid(s00_regslice_to_s00_couplers_BID[5:0]),\n        .m_axi_bready(s00_regslice_to_s00_couplers_BREADY),\n        .m_axi_bresp(s00_regslice_to_s00_couplers_BRESP),\n        .m_axi_bvalid(s00_regslice_to_s00_couplers_BVALID),\n        .m_axi_rdata(s00_regslice_to_s00_couplers_RDATA),\n        .m_axi_rid(s00_regslice_to_s00_couplers_RID[5:0]),\n        .m_axi_rlast(s00_regslice_to_s00_couplers_RLAST),\n        .m_axi_rready(s00_regslice_to_s00_couplers_RREADY),\n        .m_axi_rresp(s00_regslice_to_s00_couplers_RRESP),\n        .m_axi_rvalid(s00_regslice_to_s00_couplers_RVALID),\n        .m_axi_wdata(s00_regslice_to_s00_couplers_WDATA),\n        .m_axi_wlast(s00_regslice_to_s00_couplers_WLAST),\n        .m_axi_wready(s00_regslice_to_s00_couplers_WREADY),\n        .m_axi_wstrb(s00_regslice_to_s00_couplers_WSTRB),\n        .m_axi_wvalid(s00_regslice_to_s00_couplers_WVALID),\n        .s_axi_araddr(s00_couplers_to_s00_regslice_ARADDR),\n        .s_axi_arburst(s00_couplers_to_s00_regslice_ARBURST),\n        .s_axi_arcache(s00_couplers_to_s00_regslice_ARCACHE),\n        .s_axi_arid(s00_couplers_to_s00_regslice_ARID),\n        .s_axi_arlen(s00_couplers_to_s00_regslice_ARLEN),\n        .s_axi_arlock(s00_couplers_to_s00_regslice_ARLOCK),\n        .s_axi_arprot(s00_couplers_to_s00_regslice_ARPROT),\n        .s_axi_arqos(s00_couplers_to_s00_regslice_ARQOS),\n        .s_axi_arready(s00_couplers_to_s00_regslice_ARREADY),\n        .s_axi_arregion(s00_couplers_to_s00_regslice_ARREGION),\n        .s_axi_arsize(s00_couplers_to_s00_regslice_ARSIZE),\n        .s_axi_arvalid(s00_couplers_to_s00_regslice_ARVALID),\n        .s_axi_awaddr(s00_couplers_to_s00_regslice_AWADDR),\n        .s_axi_awburst(s00_couplers_to_s00_regslice_AWBURST),\n        .s_axi_awcache(s00_couplers_to_s00_regslice_AWCACHE),\n        .s_axi_awid(s00_couplers_to_s00_regslice_AWID),\n        .s_axi_awlen(s00_couplers_to_s00_regslice_AWLEN),\n        .s_axi_awlock(s00_couplers_to_s00_regslice_AWLOCK),\n        .s_axi_awprot(s00_couplers_to_s00_regslice_AWPROT),\n        .s_axi_awqos(s00_couplers_to_s00_regslice_AWQOS),\n        .s_axi_awready(s00_couplers_to_s00_regslice_AWREADY),\n        .s_axi_awregion(s00_couplers_to_s00_regslice_AWREGION),\n        .s_axi_awsize(s00_couplers_to_s00_regslice_AWSIZE),\n        .s_axi_awvalid(s00_couplers_to_s00_regslice_AWVALID),\n        .s_axi_bid(s00_couplers_to_s00_regslice_BID),\n        .s_axi_bready(s00_couplers_to_s00_regslice_BREADY),\n        .s_axi_bresp(s00_couplers_to_s00_regslice_BRESP),\n        .s_axi_bvalid(s00_couplers_to_s00_regslice_BVALID),\n        .s_axi_rdata(s00_couplers_to_s00_regslice_RDATA),\n        .s_axi_rid(s00_couplers_to_s00_regslice_RID),\n        .s_axi_rlast(s00_couplers_to_s00_regslice_RLAST),\n        .s_axi_rready(s00_couplers_to_s00_regslice_RREADY),\n        .s_axi_rresp(s00_couplers_to_s00_regslice_RRESP),\n        .s_axi_rvalid(s00_couplers_to_s00_regslice_RVALID),\n        .s_axi_wdata(s00_couplers_to_s00_regslice_WDATA),\n        .s_axi_wlast(s00_couplers_to_s00_regslice_WLAST),\n        .s_axi_wready(s00_couplers_to_s00_regslice_WREADY),\n        .s_axi_wstrb(s00_couplers_to_s00_regslice_WSTRB),\n        .s_axi_wvalid(s00_couplers_to_s00_regslice_WVALID));\nendmodule\n\nmodule s01_couplers_imp_GSTXQ8\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [5:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [5:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [5:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [5:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [5:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [5:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire S_ACLK_1;\n  wire S_ARESETN_1;\n  wire [63:0]s01_couplers_to_s01_regslice_ARADDR;\n  wire [1:0]s01_couplers_to_s01_regslice_ARBURST;\n  wire [3:0]s01_couplers_to_s01_regslice_ARCACHE;\n  wire [5:0]s01_couplers_to_s01_regslice_ARID;\n  wire [7:0]s01_couplers_to_s01_regslice_ARLEN;\n  wire [0:0]s01_couplers_to_s01_regslice_ARLOCK;\n  wire [2:0]s01_couplers_to_s01_regslice_ARPROT;\n  wire [3:0]s01_couplers_to_s01_regslice_ARQOS;\n  wire s01_couplers_to_s01_regslice_ARREADY;\n  wire [3:0]s01_couplers_to_s01_regslice_ARREGION;\n  wire [2:0]s01_couplers_to_s01_regslice_ARSIZE;\n  wire s01_couplers_to_s01_regslice_ARVALID;\n  wire [63:0]s01_couplers_to_s01_regslice_AWADDR;\n  wire [1:0]s01_couplers_to_s01_regslice_AWBURST;\n  wire [3:0]s01_couplers_to_s01_regslice_AWCACHE;\n  wire [5:0]s01_couplers_to_s01_regslice_AWID;\n  wire [7:0]s01_couplers_to_s01_regslice_AWLEN;\n  wire [0:0]s01_couplers_to_s01_regslice_AWLOCK;\n  wire [2:0]s01_couplers_to_s01_regslice_AWPROT;\n  wire [3:0]s01_couplers_to_s01_regslice_AWQOS;\n  wire s01_couplers_to_s01_regslice_AWREADY;\n  wire [3:0]s01_couplers_to_s01_regslice_AWREGION;\n  wire [2:0]s01_couplers_to_s01_regslice_AWSIZE;\n  wire s01_couplers_to_s01_regslice_AWVALID;\n  wire [5:0]s01_couplers_to_s01_regslice_BID;\n  wire s01_couplers_to_s01_regslice_BREADY;\n  wire [1:0]s01_couplers_to_s01_regslice_BRESP;\n  wire s01_couplers_to_s01_regslice_BVALID;\n  wire [511:0]s01_couplers_to_s01_regslice_RDATA;\n  wire [5:0]s01_couplers_to_s01_regslice_RID;\n  wire s01_couplers_to_s01_regslice_RLAST;\n  wire s01_couplers_to_s01_regslice_RREADY;\n  wire [1:0]s01_couplers_to_s01_regslice_RRESP;\n  wire s01_couplers_to_s01_regslice_RVALID;\n  wire [511:0]s01_couplers_to_s01_regslice_WDATA;\n  wire s01_couplers_to_s01_regslice_WLAST;\n  wire s01_couplers_to_s01_regslice_WREADY;\n  wire [63:0]s01_couplers_to_s01_regslice_WSTRB;\n  wire s01_couplers_to_s01_regslice_WVALID;\n  wire [63:0]s01_regslice_to_s01_couplers_ARADDR;\n  wire [1:0]s01_regslice_to_s01_couplers_ARBURST;\n  wire [3:0]s01_regslice_to_s01_couplers_ARCACHE;\n  wire [5:0]s01_regslice_to_s01_couplers_ARID;\n  wire [7:0]s01_regslice_to_s01_couplers_ARLEN;\n  wire [0:0]s01_regslice_to_s01_couplers_ARLOCK;\n  wire [2:0]s01_regslice_to_s01_couplers_ARPROT;\n  wire [3:0]s01_regslice_to_s01_couplers_ARQOS;\n  wire s01_regslice_to_s01_couplers_ARREADY;\n  wire [2:0]s01_regslice_to_s01_couplers_ARSIZE;\n  wire s01_regslice_to_s01_couplers_ARVALID;\n  wire [63:0]s01_regslice_to_s01_couplers_AWADDR;\n  wire [1:0]s01_regslice_to_s01_couplers_AWBURST;\n  wire [3:0]s01_regslice_to_s01_couplers_AWCACHE;\n  wire [5:0]s01_regslice_to_s01_couplers_AWID;\n  wire [7:0]s01_regslice_to_s01_couplers_AWLEN;\n  wire [0:0]s01_regslice_to_s01_couplers_AWLOCK;\n  wire [2:0]s01_regslice_to_s01_couplers_AWPROT;\n  wire [3:0]s01_regslice_to_s01_couplers_AWQOS;\n  wire s01_regslice_to_s01_couplers_AWREADY;\n  wire [2:0]s01_regslice_to_s01_couplers_AWSIZE;\n  wire s01_regslice_to_s01_couplers_AWVALID;\n  wire [6:0]s01_regslice_to_s01_couplers_BID;\n  wire s01_regslice_to_s01_couplers_BREADY;\n  wire [1:0]s01_regslice_to_s01_couplers_BRESP;\n  wire s01_regslice_to_s01_couplers_BVALID;\n  wire [511:0]s01_regslice_to_s01_couplers_RDATA;\n  wire [6:0]s01_regslice_to_s01_couplers_RID;\n  wire s01_regslice_to_s01_couplers_RLAST;\n  wire s01_regslice_to_s01_couplers_RREADY;\n  wire [1:0]s01_regslice_to_s01_couplers_RRESP;\n  wire s01_regslice_to_s01_couplers_RVALID;\n  wire [511:0]s01_regslice_to_s01_couplers_WDATA;\n  wire s01_regslice_to_s01_couplers_WLAST;\n  wire s01_regslice_to_s01_couplers_WREADY;\n  wire [63:0]s01_regslice_to_s01_couplers_WSTRB;\n  wire s01_regslice_to_s01_couplers_WVALID;\n\n  assign M_AXI_araddr[63:0] = s01_regslice_to_s01_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = s01_regslice_to_s01_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = s01_regslice_to_s01_couplers_ARCACHE;\n  assign M_AXI_arid[5:0] = s01_regslice_to_s01_couplers_ARID;\n  assign M_AXI_arlen[7:0] = s01_regslice_to_s01_couplers_ARLEN;\n  assign M_AXI_arlock[0] = s01_regslice_to_s01_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = s01_regslice_to_s01_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = s01_regslice_to_s01_couplers_ARQOS;\n  assign M_AXI_arsize[2:0] = s01_regslice_to_s01_couplers_ARSIZE;\n  assign M_AXI_arvalid = s01_regslice_to_s01_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = s01_regslice_to_s01_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = s01_regslice_to_s01_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = s01_regslice_to_s01_couplers_AWCACHE;\n  assign M_AXI_awid[5:0] = s01_regslice_to_s01_couplers_AWID;\n  assign M_AXI_awlen[7:0] = s01_regslice_to_s01_couplers_AWLEN;\n  assign M_AXI_awlock[0] = s01_regslice_to_s01_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = s01_regslice_to_s01_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = s01_regslice_to_s01_couplers_AWQOS;\n  assign M_AXI_awsize[2:0] = s01_regslice_to_s01_couplers_AWSIZE;\n  assign M_AXI_awvalid = s01_regslice_to_s01_couplers_AWVALID;\n  assign M_AXI_bready = s01_regslice_to_s01_couplers_BREADY;\n  assign M_AXI_rready = s01_regslice_to_s01_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = s01_regslice_to_s01_couplers_WDATA;\n  assign M_AXI_wlast = s01_regslice_to_s01_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = s01_regslice_to_s01_couplers_WSTRB;\n  assign M_AXI_wvalid = s01_regslice_to_s01_couplers_WVALID;\n  assign S_ACLK_1 = S_ACLK;\n  assign S_ARESETN_1 = S_ARESETN;\n  assign S_AXI_arready = s01_couplers_to_s01_regslice_ARREADY;\n  assign S_AXI_awready = s01_couplers_to_s01_regslice_AWREADY;\n  assign S_AXI_bid[5:0] = s01_couplers_to_s01_regslice_BID;\n  assign S_AXI_bresp[1:0] = s01_couplers_to_s01_regslice_BRESP;\n  assign S_AXI_bvalid = s01_couplers_to_s01_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = s01_couplers_to_s01_regslice_RDATA;\n  assign S_AXI_rid[5:0] = s01_couplers_to_s01_regslice_RID;\n  assign S_AXI_rlast = s01_couplers_to_s01_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = s01_couplers_to_s01_regslice_RRESP;\n  assign S_AXI_rvalid = s01_couplers_to_s01_regslice_RVALID;\n  assign S_AXI_wready = s01_couplers_to_s01_regslice_WREADY;\n  assign s01_couplers_to_s01_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign s01_couplers_to_s01_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign s01_couplers_to_s01_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign s01_couplers_to_s01_regslice_ARID = S_AXI_arid[5:0];\n  assign s01_couplers_to_s01_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign s01_couplers_to_s01_regslice_ARLOCK = S_AXI_arlock[0];\n  assign s01_couplers_to_s01_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign s01_couplers_to_s01_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign s01_couplers_to_s01_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign s01_couplers_to_s01_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign s01_couplers_to_s01_regslice_ARVALID = S_AXI_arvalid;\n  assign s01_couplers_to_s01_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign s01_couplers_to_s01_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign s01_couplers_to_s01_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign s01_couplers_to_s01_regslice_AWID = S_AXI_awid[5:0];\n  assign s01_couplers_to_s01_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign s01_couplers_to_s01_regslice_AWLOCK = S_AXI_awlock[0];\n  assign s01_couplers_to_s01_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign s01_couplers_to_s01_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign s01_couplers_to_s01_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign s01_couplers_to_s01_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign s01_couplers_to_s01_regslice_AWVALID = S_AXI_awvalid;\n  assign s01_couplers_to_s01_regslice_BREADY = S_AXI_bready;\n  assign s01_couplers_to_s01_regslice_RREADY = S_AXI_rready;\n  assign s01_couplers_to_s01_regslice_WDATA = S_AXI_wdata[511:0];\n  assign s01_couplers_to_s01_regslice_WLAST = S_AXI_wlast;\n  assign s01_couplers_to_s01_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign s01_couplers_to_s01_regslice_WVALID = S_AXI_wvalid;\n  assign s01_regslice_to_s01_couplers_ARREADY = M_AXI_arready;\n  assign s01_regslice_to_s01_couplers_AWREADY = M_AXI_awready;\n  assign s01_regslice_to_s01_couplers_BID = M_AXI_bid[6:0];\n  assign s01_regslice_to_s01_couplers_BRESP = M_AXI_bresp[1:0];\n  assign s01_regslice_to_s01_couplers_BVALID = M_AXI_bvalid;\n  assign s01_regslice_to_s01_couplers_RDATA = M_AXI_rdata[511:0];\n  assign s01_regslice_to_s01_couplers_RID = M_AXI_rid[6:0];\n  assign s01_regslice_to_s01_couplers_RLAST = M_AXI_rlast;\n  assign s01_regslice_to_s01_couplers_RRESP = M_AXI_rresp[1:0];\n  assign s01_regslice_to_s01_couplers_RVALID = M_AXI_rvalid;\n  assign s01_regslice_to_s01_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_s01_regslice_0 s01_regslice\n       (.aclk(S_ACLK_1),\n        .aresetn(S_ARESETN_1),\n        .m_axi_araddr(s01_regslice_to_s01_couplers_ARADDR),\n        .m_axi_arburst(s01_regslice_to_s01_couplers_ARBURST),\n        .m_axi_arcache(s01_regslice_to_s01_couplers_ARCACHE),\n        .m_axi_arid(s01_regslice_to_s01_couplers_ARID),\n        .m_axi_arlen(s01_regslice_to_s01_couplers_ARLEN),\n        .m_axi_arlock(s01_regslice_to_s01_couplers_ARLOCK),\n        .m_axi_arprot(s01_regslice_to_s01_couplers_ARPROT),\n        .m_axi_arqos(s01_regslice_to_s01_couplers_ARQOS),\n        .m_axi_arready(s01_regslice_to_s01_couplers_ARREADY),\n        .m_axi_arsize(s01_regslice_to_s01_couplers_ARSIZE),\n        .m_axi_arvalid(s01_regslice_to_s01_couplers_ARVALID),\n        .m_axi_awaddr(s01_regslice_to_s01_couplers_AWADDR),\n        .m_axi_awburst(s01_regslice_to_s01_couplers_AWBURST),\n        .m_axi_awcache(s01_regslice_to_s01_couplers_AWCACHE),\n        .m_axi_awid(s01_regslice_to_s01_couplers_AWID),\n        .m_axi_awlen(s01_regslice_to_s01_couplers_AWLEN),\n        .m_axi_awlock(s01_regslice_to_s01_couplers_AWLOCK),\n        .m_axi_awprot(s01_regslice_to_s01_couplers_AWPROT),\n        .m_axi_awqos(s01_regslice_to_s01_couplers_AWQOS),\n        .m_axi_awready(s01_regslice_to_s01_couplers_AWREADY),\n        .m_axi_awsize(s01_regslice_to_s01_couplers_AWSIZE),\n        .m_axi_awvalid(s01_regslice_to_s01_couplers_AWVALID),\n        .m_axi_bid(s01_regslice_to_s01_couplers_BID[5:0]),\n        .m_axi_bready(s01_regslice_to_s01_couplers_BREADY),\n        .m_axi_bresp(s01_regslice_to_s01_couplers_BRESP),\n        .m_axi_bvalid(s01_regslice_to_s01_couplers_BVALID),\n        .m_axi_rdata(s01_regslice_to_s01_couplers_RDATA),\n        .m_axi_rid(s01_regslice_to_s01_couplers_RID[5:0]),\n        .m_axi_rlast(s01_regslice_to_s01_couplers_RLAST),\n        .m_axi_rready(s01_regslice_to_s01_couplers_RREADY),\n        .m_axi_rresp(s01_regslice_to_s01_couplers_RRESP),\n        .m_axi_rvalid(s01_regslice_to_s01_couplers_RVALID),\n        .m_axi_wdata(s01_regslice_to_s01_couplers_WDATA),\n        .m_axi_wlast(s01_regslice_to_s01_couplers_WLAST),\n        .m_axi_wready(s01_regslice_to_s01_couplers_WREADY),\n        .m_axi_wstrb(s01_regslice_to_s01_couplers_WSTRB),\n        .m_axi_wvalid(s01_regslice_to_s01_couplers_WVALID),\n        .s_axi_araddr(s01_couplers_to_s01_regslice_ARADDR),\n        .s_axi_arburst(s01_couplers_to_s01_regslice_ARBURST),\n        .s_axi_arcache(s01_couplers_to_s01_regslice_ARCACHE),\n        .s_axi_arid(s01_couplers_to_s01_regslice_ARID),\n        .s_axi_arlen(s01_couplers_to_s01_regslice_ARLEN),\n        .s_axi_arlock(s01_couplers_to_s01_regslice_ARLOCK),\n        .s_axi_arprot(s01_couplers_to_s01_regslice_ARPROT),\n        .s_axi_arqos(s01_couplers_to_s01_regslice_ARQOS),\n        .s_axi_arready(s01_couplers_to_s01_regslice_ARREADY),\n        .s_axi_arregion(s01_couplers_to_s01_regslice_ARREGION),\n        .s_axi_arsize(s01_couplers_to_s01_regslice_ARSIZE),\n        .s_axi_arvalid(s01_couplers_to_s01_regslice_ARVALID),\n        .s_axi_awaddr(s01_couplers_to_s01_regslice_AWADDR),\n        .s_axi_awburst(s01_couplers_to_s01_regslice_AWBURST),\n        .s_axi_awcache(s01_couplers_to_s01_regslice_AWCACHE),\n        .s_axi_awid(s01_couplers_to_s01_regslice_AWID),\n        .s_axi_awlen(s01_couplers_to_s01_regslice_AWLEN),\n        .s_axi_awlock(s01_couplers_to_s01_regslice_AWLOCK),\n        .s_axi_awprot(s01_couplers_to_s01_regslice_AWPROT),\n        .s_axi_awqos(s01_couplers_to_s01_regslice_AWQOS),\n        .s_axi_awready(s01_couplers_to_s01_regslice_AWREADY),\n        .s_axi_awregion(s01_couplers_to_s01_regslice_AWREGION),\n        .s_axi_awsize(s01_couplers_to_s01_regslice_AWSIZE),\n        .s_axi_awvalid(s01_couplers_to_s01_regslice_AWVALID),\n        .s_axi_bid(s01_couplers_to_s01_regslice_BID),\n        .s_axi_bready(s01_couplers_to_s01_regslice_BREADY),\n        .s_axi_bresp(s01_couplers_to_s01_regslice_BRESP),\n        .s_axi_bvalid(s01_couplers_to_s01_regslice_BVALID),\n        .s_axi_rdata(s01_couplers_to_s01_regslice_RDATA),\n        .s_axi_rid(s01_couplers_to_s01_regslice_RID),\n        .s_axi_rlast(s01_couplers_to_s01_regslice_RLAST),\n        .s_axi_rready(s01_couplers_to_s01_regslice_RREADY),\n        .s_axi_rresp(s01_couplers_to_s01_regslice_RRESP),\n        .s_axi_rvalid(s01_couplers_to_s01_regslice_RVALID),\n        .s_axi_wdata(s01_couplers_to_s01_regslice_WDATA),\n        .s_axi_wlast(s01_couplers_to_s01_regslice_WLAST),\n        .s_axi_wready(s01_couplers_to_s01_regslice_WREADY),\n        .s_axi_wstrb(s01_couplers_to_s01_regslice_WSTRB),\n        .s_axi_wvalid(s01_couplers_to_s01_regslice_WVALID));\nendmodule\n", "num_lines": 5426}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Tool Version: Vivado v.2017.4.op (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017\n//Date        : Tue May 22 11:47:32 2018\n//Host        : ip-10-206-20-46 running 64-bit CentOS release 6.5 (Final)\n//Command     : generate_target cl_axi_interconnect.bd\n//Design      : cl_axi_interconnect\n//Purpose     : IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=cl_axi_interconnect,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=14,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_BD}\" *) (* HW_HANDOFF = \"cl_axi_interconnect.hwdef\" *) \nmodule cl_axi_interconnect\n   (ACLK,\n    ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.ACLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF S00_AXI:M00_AXI:M01_AXI:M02_AXI:M03_AXI:S01_AXI, ASSOCIATED_RESET ARESETN, CLK_DOMAIN cl_axi_interconnect_ACLK, FREQ_HZ 250000000, PHASE 0.000\" *) input ACLK;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.ARESETN RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.ARESETN, POLARITY ACTIVE_LOW\" *) input ARESETN;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M00_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M00_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARBURST\" *) output [1:0]M00_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE\" *) output [3:0]M00_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARID\" *) output [6:0]M00_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLEN\" *) output [7:0]M00_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK\" *) output [0:0]M00_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARPROT\" *) output [2:0]M00_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARQOS\" *) output [3:0]M00_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREADY\" *) input M00_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREGION\" *) output [3:0]M00_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE\" *) output [2:0]M00_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARVALID\" *) output M00_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWADDR\" *) output [63:0]M00_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWBURST\" *) output [1:0]M00_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE\" *) output [3:0]M00_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWID\" *) output [6:0]M00_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLEN\" *) output [7:0]M00_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK\" *) output [0:0]M00_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWPROT\" *) output [2:0]M00_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWQOS\" *) output [3:0]M00_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREADY\" *) input M00_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREGION\" *) output [3:0]M00_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE\" *) output [2:0]M00_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWVALID\" *) output M00_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BID\" *) input [6:0]M00_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BREADY\" *) output M00_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BRESP\" *) input [1:0]M00_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BVALID\" *) input M00_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RDATA\" *) input [511:0]M00_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RID\" *) input [6:0]M00_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RLAST\" *) input M00_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RREADY\" *) output M00_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RRESP\" *) input [1:0]M00_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RVALID\" *) input M00_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WDATA\" *) output [511:0]M00_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WLAST\" *) output M00_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WREADY\" *) input M00_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WSTRB\" *) output [63:0]M00_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WVALID\" *) output M00_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M01_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M01_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARBURST\" *) output [1:0]M01_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE\" *) output [3:0]M01_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARID\" *) output [6:0]M01_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARLEN\" *) output [7:0]M01_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK\" *) output [0:0]M01_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARPROT\" *) output [2:0]M01_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARQOS\" *) output [3:0]M01_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARREADY\" *) input M01_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARREGION\" *) output [3:0]M01_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE\" *) output [2:0]M01_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARVALID\" *) output M01_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWADDR\" *) output [63:0]M01_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWBURST\" *) output [1:0]M01_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE\" *) output [3:0]M01_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWID\" *) output [6:0]M01_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWLEN\" *) output [7:0]M01_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK\" *) output [0:0]M01_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWPROT\" *) output [2:0]M01_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWQOS\" *) output [3:0]M01_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWREADY\" *) input M01_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWREGION\" *) output [3:0]M01_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE\" *) output [2:0]M01_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWVALID\" *) output M01_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BID\" *) input [6:0]M01_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BREADY\" *) output M01_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BRESP\" *) input [1:0]M01_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BVALID\" *) input M01_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RDATA\" *) input [511:0]M01_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RID\" *) input [6:0]M01_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RLAST\" *) input M01_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RREADY\" *) output M01_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RRESP\" *) input [1:0]M01_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RVALID\" *) input M01_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WDATA\" *) output [511:0]M01_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WLAST\" *) output M01_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WREADY\" *) input M01_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WSTRB\" *) output [63:0]M01_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WVALID\" *) output M01_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M02_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M02_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARBURST\" *) output [1:0]M02_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE\" *) output [3:0]M02_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARID\" *) output [6:0]M02_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARLEN\" *) output [7:0]M02_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK\" *) output [0:0]M02_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARPROT\" *) output [2:0]M02_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARQOS\" *) output [3:0]M02_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARREADY\" *) input M02_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARREGION\" *) output [3:0]M02_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE\" *) output [2:0]M02_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARVALID\" *) output M02_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWADDR\" *) output [63:0]M02_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWBURST\" *) output [1:0]M02_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE\" *) output [3:0]M02_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWID\" *) output [6:0]M02_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWLEN\" *) output [7:0]M02_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK\" *) output [0:0]M02_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWPROT\" *) output [2:0]M02_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWQOS\" *) output [3:0]M02_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWREADY\" *) input M02_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWREGION\" *) output [3:0]M02_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE\" *) output [2:0]M02_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWVALID\" *) output M02_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BID\" *) input [6:0]M02_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BREADY\" *) output M02_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BRESP\" *) input [1:0]M02_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BVALID\" *) input M02_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RDATA\" *) input [511:0]M02_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RID\" *) input [6:0]M02_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RLAST\" *) input M02_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RREADY\" *) output M02_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RRESP\" *) input [1:0]M02_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RVALID\" *) input M02_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WDATA\" *) output [511:0]M02_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WLAST\" *) output M02_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WREADY\" *) input M02_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WSTRB\" *) output [63:0]M02_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WVALID\" *) output M02_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M03_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M03_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARBURST\" *) output [1:0]M03_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE\" *) output [3:0]M03_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARID\" *) output [6:0]M03_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARLEN\" *) output [7:0]M03_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK\" *) output [0:0]M03_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARPROT\" *) output [2:0]M03_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARQOS\" *) output [3:0]M03_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARREADY\" *) input M03_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARREGION\" *) output [3:0]M03_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE\" *) output [2:0]M03_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARVALID\" *) output M03_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWADDR\" *) output [63:0]M03_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWBURST\" *) output [1:0]M03_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE\" *) output [3:0]M03_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWID\" *) output [6:0]M03_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWLEN\" *) output [7:0]M03_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK\" *) output [0:0]M03_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWPROT\" *) output [2:0]M03_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWQOS\" *) output [3:0]M03_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWREADY\" *) input M03_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWREGION\" *) output [3:0]M03_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE\" *) output [2:0]M03_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWVALID\" *) output M03_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BID\" *) input [6:0]M03_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BREADY\" *) output M03_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BRESP\" *) input [1:0]M03_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BVALID\" *) input M03_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RDATA\" *) input [511:0]M03_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RID\" *) input [6:0]M03_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RLAST\" *) input M03_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RREADY\" *) output M03_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RRESP\" *) input [1:0]M03_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RVALID\" *) input M03_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WDATA\" *) output [511:0]M03_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WLAST\" *) output M03_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WREADY\" *) input M03_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WSTRB\" *) output [63:0]M03_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WVALID\" *) output M03_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S00_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 6, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 32, NUM_READ_THREADS 16, NUM_WRITE_OUTSTANDING 32, NUM_WRITE_THREADS 16, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) input [63:0]S00_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARBURST\" *) input [1:0]S00_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE\" *) input [3:0]S00_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARID\" *) input [5:0]S00_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLEN\" *) input [7:0]S00_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK\" *) input [0:0]S00_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARPROT\" *) input [2:0]S00_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARQOS\" *) input [3:0]S00_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREADY\" *) output S00_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREGION\" *) input [3:0]S00_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE\" *) input [2:0]S00_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARVALID\" *) input S00_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWADDR\" *) input [63:0]S00_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWBURST\" *) input [1:0]S00_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE\" *) input [3:0]S00_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWID\" *) input [5:0]S00_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLEN\" *) input [7:0]S00_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK\" *) input [0:0]S00_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWPROT\" *) input [2:0]S00_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWQOS\" *) input [3:0]S00_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREADY\" *) output S00_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREGION\" *) input [3:0]S00_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE\" *) input [2:0]S00_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWVALID\" *) input S00_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BID\" *) output [5:0]S00_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BREADY\" *) input S00_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BRESP\" *) output [1:0]S00_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BVALID\" *) output S00_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RDATA\" *) output [511:0]S00_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RID\" *) output [5:0]S00_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RLAST\" *) output S00_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RREADY\" *) input S00_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RRESP\" *) output [1:0]S00_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RVALID\" *) output S00_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WDATA\" *) input [511:0]S00_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WLAST\" *) input S00_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WREADY\" *) output S00_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WSTRB\" *) input [63:0]S00_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WVALID\" *) input S00_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S01_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 6, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 32, NUM_READ_THREADS 16, NUM_WRITE_OUTSTANDING 32, NUM_WRITE_THREADS 16, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) input [63:0]S01_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARBURST\" *) input [1:0]S01_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE\" *) input [3:0]S01_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARID\" *) input [5:0]S01_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARLEN\" *) input [7:0]S01_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK\" *) input [0:0]S01_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARPROT\" *) input [2:0]S01_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARQOS\" *) input [3:0]S01_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARREADY\" *) output S01_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARREGION\" *) input [3:0]S01_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE\" *) input [2:0]S01_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARVALID\" *) input S01_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWADDR\" *) input [63:0]S01_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWBURST\" *) input [1:0]S01_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE\" *) input [3:0]S01_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWID\" *) input [5:0]S01_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWLEN\" *) input [7:0]S01_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK\" *) input [0:0]S01_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWPROT\" *) input [2:0]S01_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWQOS\" *) input [3:0]S01_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWREADY\" *) output S01_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWREGION\" *) input [3:0]S01_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE\" *) input [2:0]S01_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWVALID\" *) input S01_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BID\" *) output [5:0]S01_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BREADY\" *) input S01_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BRESP\" *) output [1:0]S01_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BVALID\" *) output S01_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RDATA\" *) output [511:0]S01_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RID\" *) output [5:0]S01_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RLAST\" *) output S01_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RREADY\" *) input S01_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RRESP\" *) output [1:0]S01_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RVALID\" *) output S01_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WDATA\" *) input [511:0]S01_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WLAST\" *) input S01_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WREADY\" *) output S01_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WSTRB\" *) input [63:0]S01_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WVALID\" *) input S01_AXI_wvalid;\n\n  wire ACLK_1;\n  wire ARESETN_1;\n  wire [63:0]S00_AXI_1_ARADDR;\n  wire [1:0]S00_AXI_1_ARBURST;\n  wire [3:0]S00_AXI_1_ARCACHE;\n  wire [5:0]S00_AXI_1_ARID;\n  wire [7:0]S00_AXI_1_ARLEN;\n  wire [0:0]S00_AXI_1_ARLOCK;\n  wire [2:0]S00_AXI_1_ARPROT;\n  wire [3:0]S00_AXI_1_ARQOS;\n  wire S00_AXI_1_ARREADY;\n  wire [3:0]S00_AXI_1_ARREGION;\n  wire [2:0]S00_AXI_1_ARSIZE;\n  wire S00_AXI_1_ARVALID;\n  wire [63:0]S00_AXI_1_AWADDR;\n  wire [1:0]S00_AXI_1_AWBURST;\n  wire [3:0]S00_AXI_1_AWCACHE;\n  wire [5:0]S00_AXI_1_AWID;\n  wire [7:0]S00_AXI_1_AWLEN;\n  wire [0:0]S00_AXI_1_AWLOCK;\n  wire [2:0]S00_AXI_1_AWPROT;\n  wire [3:0]S00_AXI_1_AWQOS;\n  wire S00_AXI_1_AWREADY;\n  wire [3:0]S00_AXI_1_AWREGION;\n  wire [2:0]S00_AXI_1_AWSIZE;\n  wire S00_AXI_1_AWVALID;\n  wire [5:0]S00_AXI_1_BID;\n  wire S00_AXI_1_BREADY;\n  wire [1:0]S00_AXI_1_BRESP;\n  wire S00_AXI_1_BVALID;\n  wire [511:0]S00_AXI_1_RDATA;\n  wire [5:0]S00_AXI_1_RID;\n  wire S00_AXI_1_RLAST;\n  wire S00_AXI_1_RREADY;\n  wire [1:0]S00_AXI_1_RRESP;\n  wire S00_AXI_1_RVALID;\n  wire [511:0]S00_AXI_1_WDATA;\n  wire S00_AXI_1_WLAST;\n  wire S00_AXI_1_WREADY;\n  wire [63:0]S00_AXI_1_WSTRB;\n  wire S00_AXI_1_WVALID;\n  wire [63:0]S01_AXI_1_ARADDR;\n  wire [1:0]S01_AXI_1_ARBURST;\n  wire [3:0]S01_AXI_1_ARCACHE;\n  wire [5:0]S01_AXI_1_ARID;\n  wire [7:0]S01_AXI_1_ARLEN;\n  wire [0:0]S01_AXI_1_ARLOCK;\n  wire [2:0]S01_AXI_1_ARPROT;\n  wire [3:0]S01_AXI_1_ARQOS;\n  wire S01_AXI_1_ARREADY;\n  wire [3:0]S01_AXI_1_ARREGION;\n  wire [2:0]S01_AXI_1_ARSIZE;\n  wire S01_AXI_1_ARVALID;\n  wire [63:0]S01_AXI_1_AWADDR;\n  wire [1:0]S01_AXI_1_AWBURST;\n  wire [3:0]S01_AXI_1_AWCACHE;\n  wire [5:0]S01_AXI_1_AWID;\n  wire [7:0]S01_AXI_1_AWLEN;\n  wire [0:0]S01_AXI_1_AWLOCK;\n  wire [2:0]S01_AXI_1_AWPROT;\n  wire [3:0]S01_AXI_1_AWQOS;\n  wire S01_AXI_1_AWREADY;\n  wire [3:0]S01_AXI_1_AWREGION;\n  wire [2:0]S01_AXI_1_AWSIZE;\n  wire S01_AXI_1_AWVALID;\n  wire [5:0]S01_AXI_1_BID;\n  wire S01_AXI_1_BREADY;\n  wire [1:0]S01_AXI_1_BRESP;\n  wire S01_AXI_1_BVALID;\n  wire [511:0]S01_AXI_1_RDATA;\n  wire [5:0]S01_AXI_1_RID;\n  wire S01_AXI_1_RLAST;\n  wire S01_AXI_1_RREADY;\n  wire [1:0]S01_AXI_1_RRESP;\n  wire S01_AXI_1_RVALID;\n  wire [511:0]S01_AXI_1_WDATA;\n  wire S01_AXI_1_WLAST;\n  wire S01_AXI_1_WREADY;\n  wire [63:0]S01_AXI_1_WSTRB;\n  wire S01_AXI_1_WVALID;\n  wire [63:0]axi_interconnect_0_M00_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M00_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M00_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M00_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M00_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M00_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARQOS;\n  wire axi_interconnect_0_M00_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M00_AXI_ARSIZE;\n  wire axi_interconnect_0_M00_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M00_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M00_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M00_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M00_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M00_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M00_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWQOS;\n  wire axi_interconnect_0_M00_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M00_AXI_AWSIZE;\n  wire axi_interconnect_0_M00_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M00_AXI_BID;\n  wire axi_interconnect_0_M00_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M00_AXI_BRESP;\n  wire axi_interconnect_0_M00_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M00_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M00_AXI_RID;\n  wire axi_interconnect_0_M00_AXI_RLAST;\n  wire axi_interconnect_0_M00_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M00_AXI_RRESP;\n  wire axi_interconnect_0_M00_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M00_AXI_WDATA;\n  wire axi_interconnect_0_M00_AXI_WLAST;\n  wire axi_interconnect_0_M00_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M00_AXI_WSTRB;\n  wire axi_interconnect_0_M00_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M01_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M01_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M01_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M01_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M01_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M01_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARQOS;\n  wire axi_interconnect_0_M01_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M01_AXI_ARSIZE;\n  wire axi_interconnect_0_M01_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M01_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M01_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M01_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M01_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M01_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M01_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWQOS;\n  wire axi_interconnect_0_M01_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M01_AXI_AWSIZE;\n  wire axi_interconnect_0_M01_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M01_AXI_BID;\n  wire axi_interconnect_0_M01_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M01_AXI_BRESP;\n  wire axi_interconnect_0_M01_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M01_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M01_AXI_RID;\n  wire axi_interconnect_0_M01_AXI_RLAST;\n  wire axi_interconnect_0_M01_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M01_AXI_RRESP;\n  wire axi_interconnect_0_M01_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M01_AXI_WDATA;\n  wire axi_interconnect_0_M01_AXI_WLAST;\n  wire axi_interconnect_0_M01_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M01_AXI_WSTRB;\n  wire axi_interconnect_0_M01_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M02_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M02_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M02_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M02_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M02_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M02_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARQOS;\n  wire axi_interconnect_0_M02_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M02_AXI_ARSIZE;\n  wire axi_interconnect_0_M02_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M02_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M02_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M02_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M02_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M02_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M02_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWQOS;\n  wire axi_interconnect_0_M02_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M02_AXI_AWSIZE;\n  wire axi_interconnect_0_M02_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M02_AXI_BID;\n  wire axi_interconnect_0_M02_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M02_AXI_BRESP;\n  wire axi_interconnect_0_M02_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M02_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M02_AXI_RID;\n  wire axi_interconnect_0_M02_AXI_RLAST;\n  wire axi_interconnect_0_M02_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M02_AXI_RRESP;\n  wire axi_interconnect_0_M02_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M02_AXI_WDATA;\n  wire axi_interconnect_0_M02_AXI_WLAST;\n  wire axi_interconnect_0_M02_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M02_AXI_WSTRB;\n  wire axi_interconnect_0_M02_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M03_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M03_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M03_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M03_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M03_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M03_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARQOS;\n  wire axi_interconnect_0_M03_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M03_AXI_ARSIZE;\n  wire axi_interconnect_0_M03_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M03_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M03_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M03_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M03_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M03_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M03_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWQOS;\n  wire axi_interconnect_0_M03_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M03_AXI_AWSIZE;\n  wire axi_interconnect_0_M03_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M03_AXI_BID;\n  wire axi_interconnect_0_M03_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M03_AXI_BRESP;\n  wire axi_interconnect_0_M03_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M03_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M03_AXI_RID;\n  wire axi_interconnect_0_M03_AXI_RLAST;\n  wire axi_interconnect_0_M03_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M03_AXI_RRESP;\n  wire axi_interconnect_0_M03_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M03_AXI_WDATA;\n  wire axi_interconnect_0_M03_AXI_WLAST;\n  wire axi_interconnect_0_M03_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M03_AXI_WSTRB;\n  wire axi_interconnect_0_M03_AXI_WVALID;\n\n  assign ACLK_1 = ACLK;\n  assign ARESETN_1 = ARESETN;\n  assign M00_AXI_araddr[63:0] = axi_interconnect_0_M00_AXI_ARADDR;\n  assign M00_AXI_arburst[1:0] = axi_interconnect_0_M00_AXI_ARBURST;\n  assign M00_AXI_arcache[3:0] = axi_interconnect_0_M00_AXI_ARCACHE;\n  assign M00_AXI_arid[6:0] = axi_interconnect_0_M00_AXI_ARID;\n  assign M00_AXI_arlen[7:0] = axi_interconnect_0_M00_AXI_ARLEN;\n  assign M00_AXI_arlock[0] = axi_interconnect_0_M00_AXI_ARLOCK;\n  assign M00_AXI_arprot[2:0] = axi_interconnect_0_M00_AXI_ARPROT;\n  assign M00_AXI_arqos[3:0] = axi_interconnect_0_M00_AXI_ARQOS;\n  assign M00_AXI_arregion[3:0] = axi_interconnect_0_M00_AXI_ARREGION;\n  assign M00_AXI_arsize[2:0] = axi_interconnect_0_M00_AXI_ARSIZE;\n  assign M00_AXI_arvalid = axi_interconnect_0_M00_AXI_ARVALID;\n  assign M00_AXI_awaddr[63:0] = axi_interconnect_0_M00_AXI_AWADDR;\n  assign M00_AXI_awburst[1:0] = axi_interconnect_0_M00_AXI_AWBURST;\n  assign M00_AXI_awcache[3:0] = axi_interconnect_0_M00_AXI_AWCACHE;\n  assign M00_AXI_awid[6:0] = axi_interconnect_0_M00_AXI_AWID;\n  assign M00_AXI_awlen[7:0] = axi_interconnect_0_M00_AXI_AWLEN;\n  assign M00_AXI_awlock[0] = axi_interconnect_0_M00_AXI_AWLOCK;\n  assign M00_AXI_awprot[2:0] = axi_interconnect_0_M00_AXI_AWPROT;\n  assign M00_AXI_awqos[3:0] = axi_interconnect_0_M00_AXI_AWQOS;\n  assign M00_AXI_awregion[3:0] = axi_interconnect_0_M00_AXI_AWREGION;\n  assign M00_AXI_awsize[2:0] = axi_interconnect_0_M00_AXI_AWSIZE;\n  assign M00_AXI_awvalid = axi_interconnect_0_M00_AXI_AWVALID;\n  assign M00_AXI_bready = axi_interconnect_0_M00_AXI_BREADY;\n  assign M00_AXI_rready = axi_interconnect_0_M00_AXI_RREADY;\n  assign M00_AXI_wdata[511:0] = axi_interconnect_0_M00_AXI_WDATA;\n  assign M00_AXI_wlast = axi_interconnect_0_M00_AXI_WLAST;\n  assign M00_AXI_wstrb[63:0] = axi_interconnect_0_M00_AXI_WSTRB;\n  assign M00_AXI_wvalid = axi_interconnect_0_M00_AXI_WVALID;\n  assign M01_AXI_araddr[63:0] = axi_interconnect_0_M01_AXI_ARADDR;\n  assign M01_AXI_arburst[1:0] = axi_interconnect_0_M01_AXI_ARBURST;\n  assign M01_AXI_arcache[3:0] = axi_interconnect_0_M01_AXI_ARCACHE;\n  assign M01_AXI_arid[6:0] = axi_interconnect_0_M01_AXI_ARID;\n  assign M01_AXI_arlen[7:0] = axi_interconnect_0_M01_AXI_ARLEN;\n  assign M01_AXI_arlock[0] = axi_interconnect_0_M01_AXI_ARLOCK;\n  assign M01_AXI_arprot[2:0] = axi_interconnect_0_M01_AXI_ARPROT;\n  assign M01_AXI_arqos[3:0] = axi_interconnect_0_M01_AXI_ARQOS;\n  assign M01_AXI_arregion[3:0] = axi_interconnect_0_M01_AXI_ARREGION;\n  assign M01_AXI_arsize[2:0] = axi_interconnect_0_M01_AXI_ARSIZE;\n  assign M01_AXI_arvalid = axi_interconnect_0_M01_AXI_ARVALID;\n  assign M01_AXI_awaddr[63:0] = axi_interconnect_0_M01_AXI_AWADDR;\n  assign M01_AXI_awburst[1:0] = axi_interconnect_0_M01_AXI_AWBURST;\n  assign M01_AXI_awcache[3:0] = axi_interconnect_0_M01_AXI_AWCACHE;\n  assign M01_AXI_awid[6:0] = axi_interconnect_0_M01_AXI_AWID;\n  assign M01_AXI_awlen[7:0] = axi_interconnect_0_M01_AXI_AWLEN;\n  assign M01_AXI_awlock[0] = axi_interconnect_0_M01_AXI_AWLOCK;\n  assign M01_AXI_awprot[2:0] = axi_interconnect_0_M01_AXI_AWPROT;\n  assign M01_AXI_awqos[3:0] = axi_interconnect_0_M01_AXI_AWQOS;\n  assign M01_AXI_awregion[3:0] = axi_interconnect_0_M01_AXI_AWREGION;\n  assign M01_AXI_awsize[2:0] = axi_interconnect_0_M01_AXI_AWSIZE;\n  assign M01_AXI_awvalid = axi_interconnect_0_M01_AXI_AWVALID;\n  assign M01_AXI_bready = axi_interconnect_0_M01_AXI_BREADY;\n  assign M01_AXI_rready = axi_interconnect_0_M01_AXI_RREADY;\n  assign M01_AXI_wdata[511:0] = axi_interconnect_0_M01_AXI_WDATA;\n  assign M01_AXI_wlast = axi_interconnect_0_M01_AXI_WLAST;\n  assign M01_AXI_wstrb[63:0] = axi_interconnect_0_M01_AXI_WSTRB;\n  assign M01_AXI_wvalid = axi_interconnect_0_M01_AXI_WVALID;\n  assign M02_AXI_araddr[63:0] = axi_interconnect_0_M02_AXI_ARADDR;\n  assign M02_AXI_arburst[1:0] = axi_interconnect_0_M02_AXI_ARBURST;\n  assign M02_AXI_arcache[3:0] = axi_interconnect_0_M02_AXI_ARCACHE;\n  assign M02_AXI_arid[6:0] = axi_interconnect_0_M02_AXI_ARID;\n  assign M02_AXI_arlen[7:0] = axi_interconnect_0_M02_AXI_ARLEN;\n  assign M02_AXI_arlock[0] = axi_interconnect_0_M02_AXI_ARLOCK;\n  assign M02_AXI_arprot[2:0] = axi_interconnect_0_M02_AXI_ARPROT;\n  assign M02_AXI_arqos[3:0] = axi_interconnect_0_M02_AXI_ARQOS;\n  assign M02_AXI_arregion[3:0] = axi_interconnect_0_M02_AXI_ARREGION;\n  assign M02_AXI_arsize[2:0] = axi_interconnect_0_M02_AXI_ARSIZE;\n  assign M02_AXI_arvalid = axi_interconnect_0_M02_AXI_ARVALID;\n  assign M02_AXI_awaddr[63:0] = axi_interconnect_0_M02_AXI_AWADDR;\n  assign M02_AXI_awburst[1:0] = axi_interconnect_0_M02_AXI_AWBURST;\n  assign M02_AXI_awcache[3:0] = axi_interconnect_0_M02_AXI_AWCACHE;\n  assign M02_AXI_awid[6:0] = axi_interconnect_0_M02_AXI_AWID;\n  assign M02_AXI_awlen[7:0] = axi_interconnect_0_M02_AXI_AWLEN;\n  assign M02_AXI_awlock[0] = axi_interconnect_0_M02_AXI_AWLOCK;\n  assign M02_AXI_awprot[2:0] = axi_interconnect_0_M02_AXI_AWPROT;\n  assign M02_AXI_awqos[3:0] = axi_interconnect_0_M02_AXI_AWQOS;\n  assign M02_AXI_awregion[3:0] = axi_interconnect_0_M02_AXI_AWREGION;\n  assign M02_AXI_awsize[2:0] = axi_interconnect_0_M02_AXI_AWSIZE;\n  assign M02_AXI_awvalid = axi_interconnect_0_M02_AXI_AWVALID;\n  assign M02_AXI_bready = axi_interconnect_0_M02_AXI_BREADY;\n  assign M02_AXI_rready = axi_interconnect_0_M02_AXI_RREADY;\n  assign M02_AXI_wdata[511:0] = axi_interconnect_0_M02_AXI_WDATA;\n  assign M02_AXI_wlast = axi_interconnect_0_M02_AXI_WLAST;\n  assign M02_AXI_wstrb[63:0] = axi_interconnect_0_M02_AXI_WSTRB;\n  assign M02_AXI_wvalid = axi_interconnect_0_M02_AXI_WVALID;\n  assign M03_AXI_araddr[63:0] = axi_interconnect_0_M03_AXI_ARADDR;\n  assign M03_AXI_arburst[1:0] = axi_interconnect_0_M03_AXI_ARBURST;\n  assign M03_AXI_arcache[3:0] = axi_interconnect_0_M03_AXI_ARCACHE;\n  assign M03_AXI_arid[6:0] = axi_interconnect_0_M03_AXI_ARID;\n  assign M03_AXI_arlen[7:0] = axi_interconnect_0_M03_AXI_ARLEN;\n  assign M03_AXI_arlock[0] = axi_interconnect_0_M03_AXI_ARLOCK;\n  assign M03_AXI_arprot[2:0] = axi_interconnect_0_M03_AXI_ARPROT;\n  assign M03_AXI_arqos[3:0] = axi_interconnect_0_M03_AXI_ARQOS;\n  assign M03_AXI_arregion[3:0] = axi_interconnect_0_M03_AXI_ARREGION;\n  assign M03_AXI_arsize[2:0] = axi_interconnect_0_M03_AXI_ARSIZE;\n  assign M03_AXI_arvalid = axi_interconnect_0_M03_AXI_ARVALID;\n  assign M03_AXI_awaddr[63:0] = axi_interconnect_0_M03_AXI_AWADDR;\n  assign M03_AXI_awburst[1:0] = axi_interconnect_0_M03_AXI_AWBURST;\n  assign M03_AXI_awcache[3:0] = axi_interconnect_0_M03_AXI_AWCACHE;\n  assign M03_AXI_awid[6:0] = axi_interconnect_0_M03_AXI_AWID;\n  assign M03_AXI_awlen[7:0] = axi_interconnect_0_M03_AXI_AWLEN;\n  assign M03_AXI_awlock[0] = axi_interconnect_0_M03_AXI_AWLOCK;\n  assign M03_AXI_awprot[2:0] = axi_interconnect_0_M03_AXI_AWPROT;\n  assign M03_AXI_awqos[3:0] = axi_interconnect_0_M03_AXI_AWQOS;\n  assign M03_AXI_awregion[3:0] = axi_interconnect_0_M03_AXI_AWREGION;\n  assign M03_AXI_awsize[2:0] = axi_interconnect_0_M03_AXI_AWSIZE;\n  assign M03_AXI_awvalid = axi_interconnect_0_M03_AXI_AWVALID;\n  assign M03_AXI_bready = axi_interconnect_0_M03_AXI_BREADY;\n  assign M03_AXI_rready = axi_interconnect_0_M03_AXI_RREADY;\n  assign M03_AXI_wdata[511:0] = axi_interconnect_0_M03_AXI_WDATA;\n  assign M03_AXI_wlast = axi_interconnect_0_M03_AXI_WLAST;\n  assign M03_AXI_wstrb[63:0] = axi_interconnect_0_M03_AXI_WSTRB;\n  assign M03_AXI_wvalid = axi_interconnect_0_M03_AXI_WVALID;\n  assign S00_AXI_1_ARADDR = S00_AXI_araddr[63:0];\n  assign S00_AXI_1_ARBURST = S00_AXI_arburst[1:0];\n  assign S00_AXI_1_ARCACHE = S00_AXI_arcache[3:0];\n  assign S00_AXI_1_ARID = S00_AXI_arid[5:0];\n  assign S00_AXI_1_ARLEN = S00_AXI_arlen[7:0];\n  assign S00_AXI_1_ARLOCK = S00_AXI_arlock[0];\n  assign S00_AXI_1_ARPROT = S00_AXI_arprot[2:0];\n  assign S00_AXI_1_ARQOS = S00_AXI_arqos[3:0];\n  assign S00_AXI_1_ARREGION = S00_AXI_arregion[3:0];\n  assign S00_AXI_1_ARSIZE = S00_AXI_arsize[2:0];\n  assign S00_AXI_1_ARVALID = S00_AXI_arvalid;\n  assign S00_AXI_1_AWADDR = S00_AXI_awaddr[63:0];\n  assign S00_AXI_1_AWBURST = S00_AXI_awburst[1:0];\n  assign S00_AXI_1_AWCACHE = S00_AXI_awcache[3:0];\n  assign S00_AXI_1_AWID = S00_AXI_awid[5:0];\n  assign S00_AXI_1_AWLEN = S00_AXI_awlen[7:0];\n  assign S00_AXI_1_AWLOCK = S00_AXI_awlock[0];\n  assign S00_AXI_1_AWPROT = S00_AXI_awprot[2:0];\n  assign S00_AXI_1_AWQOS = S00_AXI_awqos[3:0];\n  assign S00_AXI_1_AWREGION = S00_AXI_awregion[3:0];\n  assign S00_AXI_1_AWSIZE = S00_AXI_awsize[2:0];\n  assign S00_AXI_1_AWVALID = S00_AXI_awvalid;\n  assign S00_AXI_1_BREADY = S00_AXI_bready;\n  assign S00_AXI_1_RREADY = S00_AXI_rready;\n  assign S00_AXI_1_WDATA = S00_AXI_wdata[511:0];\n  assign S00_AXI_1_WLAST = S00_AXI_wlast;\n  assign S00_AXI_1_WSTRB = S00_AXI_wstrb[63:0];\n  assign S00_AXI_1_WVALID = S00_AXI_wvalid;\n  assign S00_AXI_arready = S00_AXI_1_ARREADY;\n  assign S00_AXI_awready = S00_AXI_1_AWREADY;\n  assign S00_AXI_bid[5:0] = S00_AXI_1_BID;\n  assign S00_AXI_bresp[1:0] = S00_AXI_1_BRESP;\n  assign S00_AXI_bvalid = S00_AXI_1_BVALID;\n  assign S00_AXI_rdata[511:0] = S00_AXI_1_RDATA;\n  assign S00_AXI_rid[5:0] = S00_AXI_1_RID;\n  assign S00_AXI_rlast = S00_AXI_1_RLAST;\n  assign S00_AXI_rresp[1:0] = S00_AXI_1_RRESP;\n  assign S00_AXI_rvalid = S00_AXI_1_RVALID;\n  assign S00_AXI_wready = S00_AXI_1_WREADY;\n  assign S01_AXI_1_ARADDR = S01_AXI_araddr[63:0];\n  assign S01_AXI_1_ARBURST = S01_AXI_arburst[1:0];\n  assign S01_AXI_1_ARCACHE = S01_AXI_arcache[3:0];\n  assign S01_AXI_1_ARID = S01_AXI_arid[5:0];\n  assign S01_AXI_1_ARLEN = S01_AXI_arlen[7:0];\n  assign S01_AXI_1_ARLOCK = S01_AXI_arlock[0];\n  assign S01_AXI_1_ARPROT = S01_AXI_arprot[2:0];\n  assign S01_AXI_1_ARQOS = S01_AXI_arqos[3:0];\n  assign S01_AXI_1_ARREGION = S01_AXI_arregion[3:0];\n  assign S01_AXI_1_ARSIZE = S01_AXI_arsize[2:0];\n  assign S01_AXI_1_ARVALID = S01_AXI_arvalid;\n  assign S01_AXI_1_AWADDR = S01_AXI_awaddr[63:0];\n  assign S01_AXI_1_AWBURST = S01_AXI_awburst[1:0];\n  assign S01_AXI_1_AWCACHE = S01_AXI_awcache[3:0];\n  assign S01_AXI_1_AWID = S01_AXI_awid[5:0];\n  assign S01_AXI_1_AWLEN = S01_AXI_awlen[7:0];\n  assign S01_AXI_1_AWLOCK = S01_AXI_awlock[0];\n  assign S01_AXI_1_AWPROT = S01_AXI_awprot[2:0];\n  assign S01_AXI_1_AWQOS = S01_AXI_awqos[3:0];\n  assign S01_AXI_1_AWREGION = S01_AXI_awregion[3:0];\n  assign S01_AXI_1_AWSIZE = S01_AXI_awsize[2:0];\n  assign S01_AXI_1_AWVALID = S01_AXI_awvalid;\n  assign S01_AXI_1_BREADY = S01_AXI_bready;\n  assign S01_AXI_1_RREADY = S01_AXI_rready;\n  assign S01_AXI_1_WDATA = S01_AXI_wdata[511:0];\n  assign S01_AXI_1_WLAST = S01_AXI_wlast;\n  assign S01_AXI_1_WSTRB = S01_AXI_wstrb[63:0];\n  assign S01_AXI_1_WVALID = S01_AXI_wvalid;\n  assign S01_AXI_arready = S01_AXI_1_ARREADY;\n  assign S01_AXI_awready = S01_AXI_1_AWREADY;\n  assign S01_AXI_bid[5:0] = S01_AXI_1_BID;\n  assign S01_AXI_bresp[1:0] = S01_AXI_1_BRESP;\n  assign S01_AXI_bvalid = S01_AXI_1_BVALID;\n  assign S01_AXI_rdata[511:0] = S01_AXI_1_RDATA;\n  assign S01_AXI_rid[5:0] = S01_AXI_1_RID;\n  assign S01_AXI_rlast = S01_AXI_1_RLAST;\n  assign S01_AXI_rresp[1:0] = S01_AXI_1_RRESP;\n  assign S01_AXI_rvalid = S01_AXI_1_RVALID;\n  assign S01_AXI_wready = S01_AXI_1_WREADY;\n  assign axi_interconnect_0_M00_AXI_ARREADY = M00_AXI_arready;\n  assign axi_interconnect_0_M00_AXI_AWREADY = M00_AXI_awready;\n  assign axi_interconnect_0_M00_AXI_BID = M00_AXI_bid[6:0];\n  assign axi_interconnect_0_M00_AXI_BRESP = M00_AXI_bresp[1:0];\n  assign axi_interconnect_0_M00_AXI_BVALID = M00_AXI_bvalid;\n  assign axi_interconnect_0_M00_AXI_RDATA = M00_AXI_rdata[511:0];\n  assign axi_interconnect_0_M00_AXI_RID = M00_AXI_rid[6:0];\n  assign axi_interconnect_0_M00_AXI_RLAST = M00_AXI_rlast;\n  assign axi_interconnect_0_M00_AXI_RRESP = M00_AXI_rresp[1:0];\n  assign axi_interconnect_0_M00_AXI_RVALID = M00_AXI_rvalid;\n  assign axi_interconnect_0_M00_AXI_WREADY = M00_AXI_wready;\n  assign axi_interconnect_0_M01_AXI_ARREADY = M01_AXI_arready;\n  assign axi_interconnect_0_M01_AXI_AWREADY = M01_AXI_awready;\n  assign axi_interconnect_0_M01_AXI_BID = M01_AXI_bid[6:0];\n  assign axi_interconnect_0_M01_AXI_BRESP = M01_AXI_bresp[1:0];\n  assign axi_interconnect_0_M01_AXI_BVALID = M01_AXI_bvalid;\n  assign axi_interconnect_0_M01_AXI_RDATA = M01_AXI_rdata[511:0];\n  assign axi_interconnect_0_M01_AXI_RID = M01_AXI_rid[6:0];\n  assign axi_interconnect_0_M01_AXI_RLAST = M01_AXI_rlast;\n  assign axi_interconnect_0_M01_AXI_RRESP = M01_AXI_rresp[1:0];\n  assign axi_interconnect_0_M01_AXI_RVALID = M01_AXI_rvalid;\n  assign axi_interconnect_0_M01_AXI_WREADY = M01_AXI_wready;\n  assign axi_interconnect_0_M02_AXI_ARREADY = M02_AXI_arready;\n  assign axi_interconnect_0_M02_AXI_AWREADY = M02_AXI_awready;\n  assign axi_interconnect_0_M02_AXI_BID = M02_AXI_bid[6:0];\n  assign axi_interconnect_0_M02_AXI_BRESP = M02_AXI_bresp[1:0];\n  assign axi_interconnect_0_M02_AXI_BVALID = M02_AXI_bvalid;\n  assign axi_interconnect_0_M02_AXI_RDATA = M02_AXI_rdata[511:0];\n  assign axi_interconnect_0_M02_AXI_RID = M02_AXI_rid[6:0];\n  assign axi_interconnect_0_M02_AXI_RLAST = M02_AXI_rlast;\n  assign axi_interconnect_0_M02_AXI_RRESP = M02_AXI_rresp[1:0];\n  assign axi_interconnect_0_M02_AXI_RVALID = M02_AXI_rvalid;\n  assign axi_interconnect_0_M02_AXI_WREADY = M02_AXI_wready;\n  assign axi_interconnect_0_M03_AXI_ARREADY = M03_AXI_arready;\n  assign axi_interconnect_0_M03_AXI_AWREADY = M03_AXI_awready;\n  assign axi_interconnect_0_M03_AXI_BID = M03_AXI_bid[6:0];\n  assign axi_interconnect_0_M03_AXI_BRESP = M03_AXI_bresp[1:0];\n  assign axi_interconnect_0_M03_AXI_BVALID = M03_AXI_bvalid;\n  assign axi_interconnect_0_M03_AXI_RDATA = M03_AXI_rdata[511:0];\n  assign axi_interconnect_0_M03_AXI_RID = M03_AXI_rid[6:0];\n  assign axi_interconnect_0_M03_AXI_RLAST = M03_AXI_rlast;\n  assign axi_interconnect_0_M03_AXI_RRESP = M03_AXI_rresp[1:0];\n  assign axi_interconnect_0_M03_AXI_RVALID = M03_AXI_rvalid;\n  assign axi_interconnect_0_M03_AXI_WREADY = M03_AXI_wready;\n  cl_axi_interconnect_axi_interconnect_0_0 axi_interconnect_0\n       (.ACLK(ACLK_1),\n        .ARESETN(ARESETN_1),\n        .M00_ACLK(ACLK_1),\n        .M00_ARESETN(ARESETN_1),\n        .M00_AXI_araddr(axi_interconnect_0_M00_AXI_ARADDR),\n        .M00_AXI_arburst(axi_interconnect_0_M00_AXI_ARBURST),\n        .M00_AXI_arcache(axi_interconnect_0_M00_AXI_ARCACHE),\n        .M00_AXI_arid(axi_interconnect_0_M00_AXI_ARID),\n        .M00_AXI_arlen(axi_interconnect_0_M00_AXI_ARLEN),\n        .M00_AXI_arlock(axi_interconnect_0_M00_AXI_ARLOCK),\n        .M00_AXI_arprot(axi_interconnect_0_M00_AXI_ARPROT),\n        .M00_AXI_arqos(axi_interconnect_0_M00_AXI_ARQOS),\n        .M00_AXI_arready(axi_interconnect_0_M00_AXI_ARREADY),\n        .M00_AXI_arregion(axi_interconnect_0_M00_AXI_ARREGION),\n        .M00_AXI_arsize(axi_interconnect_0_M00_AXI_ARSIZE),\n        .M00_AXI_arvalid(axi_interconnect_0_M00_AXI_ARVALID),\n        .M00_AXI_awaddr(axi_interconnect_0_M00_AXI_AWADDR),\n        .M00_AXI_awburst(axi_interconnect_0_M00_AXI_AWBURST),\n        .M00_AXI_awcache(axi_interconnect_0_M00_AXI_AWCACHE),\n        .M00_AXI_awid(axi_interconnect_0_M00_AXI_AWID),\n        .M00_AXI_awlen(axi_interconnect_0_M00_AXI_AWLEN),\n        .M00_AXI_awlock(axi_interconnect_0_M00_AXI_AWLOCK),\n        .M00_AXI_awprot(axi_interconnect_0_M00_AXI_AWPROT),\n        .M00_AXI_awqos(axi_interconnect_0_M00_AXI_AWQOS),\n        .M00_AXI_awready(axi_interconnect_0_M00_AXI_AWREADY),\n        .M00_AXI_awregion(axi_interconnect_0_M00_AXI_AWREGION),\n        .M00_AXI_awsize(axi_interconnect_0_M00_AXI_AWSIZE),\n        .M00_AXI_awvalid(axi_interconnect_0_M00_AXI_AWVALID),\n        .M00_AXI_bid(axi_interconnect_0_M00_AXI_BID),\n        .M00_AXI_bready(axi_interconnect_0_M00_AXI_BREADY),\n        .M00_AXI_bresp(axi_interconnect_0_M00_AXI_BRESP),\n        .M00_AXI_bvalid(axi_interconnect_0_M00_AXI_BVALID),\n        .M00_AXI_rdata(axi_interconnect_0_M00_AXI_RDATA),\n        .M00_AXI_rid(axi_interconnect_0_M00_AXI_RID),\n        .M00_AXI_rlast(axi_interconnect_0_M00_AXI_RLAST),\n        .M00_AXI_rready(axi_interconnect_0_M00_AXI_RREADY),\n        .M00_AXI_rresp(axi_interconnect_0_M00_AXI_RRESP),\n        .M00_AXI_rvalid(axi_interconnect_0_M00_AXI_RVALID),\n        .M00_AXI_wdata(axi_interconnect_0_M00_AXI_WDATA),\n        .M00_AXI_wlast(axi_interconnect_0_M00_AXI_WLAST),\n        .M00_AXI_wready(axi_interconnect_0_M00_AXI_WREADY),\n        .M00_AXI_wstrb(axi_interconnect_0_M00_AXI_WSTRB),\n        .M00_AXI_wvalid(axi_interconnect_0_M00_AXI_WVALID),\n        .M01_ACLK(ACLK_1),\n        .M01_ARESETN(ARESETN_1),\n        .M01_AXI_araddr(axi_interconnect_0_M01_AXI_ARADDR),\n        .M01_AXI_arburst(axi_interconnect_0_M01_AXI_ARBURST),\n        .M01_AXI_arcache(axi_interconnect_0_M01_AXI_ARCACHE),\n        .M01_AXI_arid(axi_interconnect_0_M01_AXI_ARID),\n        .M01_AXI_arlen(axi_interconnect_0_M01_AXI_ARLEN),\n        .M01_AXI_arlock(axi_interconnect_0_M01_AXI_ARLOCK),\n        .M01_AXI_arprot(axi_interconnect_0_M01_AXI_ARPROT),\n        .M01_AXI_arqos(axi_interconnect_0_M01_AXI_ARQOS),\n        .M01_AXI_arready(axi_interconnect_0_M01_AXI_ARREADY),\n        .M01_AXI_arregion(axi_interconnect_0_M01_AXI_ARREGION),\n        .M01_AXI_arsize(axi_interconnect_0_M01_AXI_ARSIZE),\n        .M01_AXI_arvalid(axi_interconnect_0_M01_AXI_ARVALID),\n        .M01_AXI_awaddr(axi_interconnect_0_M01_AXI_AWADDR),\n        .M01_AXI_awburst(axi_interconnect_0_M01_AXI_AWBURST),\n        .M01_AXI_awcache(axi_interconnect_0_M01_AXI_AWCACHE),\n        .M01_AXI_awid(axi_interconnect_0_M01_AXI_AWID),\n        .M01_AXI_awlen(axi_interconnect_0_M01_AXI_AWLEN),\n        .M01_AXI_awlock(axi_interconnect_0_M01_AXI_AWLOCK),\n        .M01_AXI_awprot(axi_interconnect_0_M01_AXI_AWPROT),\n        .M01_AXI_awqos(axi_interconnect_0_M01_AXI_AWQOS),\n        .M01_AXI_awready(axi_interconnect_0_M01_AXI_AWREADY),\n        .M01_AXI_awregion(axi_interconnect_0_M01_AXI_AWREGION),\n        .M01_AXI_awsize(axi_interconnect_0_M01_AXI_AWSIZE),\n        .M01_AXI_awvalid(axi_interconnect_0_M01_AXI_AWVALID),\n        .M01_AXI_bid(axi_interconnect_0_M01_AXI_BID),\n        .M01_AXI_bready(axi_interconnect_0_M01_AXI_BREADY),\n        .M01_AXI_bresp(axi_interconnect_0_M01_AXI_BRESP),\n        .M01_AXI_bvalid(axi_interconnect_0_M01_AXI_BVALID),\n        .M01_AXI_rdata(axi_interconnect_0_M01_AXI_RDATA),\n        .M01_AXI_rid(axi_interconnect_0_M01_AXI_RID),\n        .M01_AXI_rlast(axi_interconnect_0_M01_AXI_RLAST),\n        .M01_AXI_rready(axi_interconnect_0_M01_AXI_RREADY),\n        .M01_AXI_rresp(axi_interconnect_0_M01_AXI_RRESP),\n        .M01_AXI_rvalid(axi_interconnect_0_M01_AXI_RVALID),\n        .M01_AXI_wdata(axi_interconnect_0_M01_AXI_WDATA),\n        .M01_AXI_wlast(axi_interconnect_0_M01_AXI_WLAST),\n        .M01_AXI_wready(axi_interconnect_0_M01_AXI_WREADY),\n        .M01_AXI_wstrb(axi_interconnect_0_M01_AXI_WSTRB),\n        .M01_AXI_wvalid(axi_interconnect_0_M01_AXI_WVALID),\n        .M02_ACLK(ACLK_1),\n        .M02_ARESETN(ARESETN_1),\n        .M02_AXI_araddr(axi_interconnect_0_M02_AXI_ARADDR),\n        .M02_AXI_arburst(axi_interconnect_0_M02_AXI_ARBURST),\n        .M02_AXI_arcache(axi_interconnect_0_M02_AXI_ARCACHE),\n        .M02_AXI_arid(axi_interconnect_0_M02_AXI_ARID),\n        .M02_AXI_arlen(axi_interconnect_0_M02_AXI_ARLEN),\n        .M02_AXI_arlock(axi_interconnect_0_M02_AXI_ARLOCK),\n        .M02_AXI_arprot(axi_interconnect_0_M02_AXI_ARPROT),\n        .M02_AXI_arqos(axi_interconnect_0_M02_AXI_ARQOS),\n        .M02_AXI_arready(axi_interconnect_0_M02_AXI_ARREADY),\n        .M02_AXI_arregion(axi_interconnect_0_M02_AXI_ARREGION),\n        .M02_AXI_arsize(axi_interconnect_0_M02_AXI_ARSIZE),\n        .M02_AXI_arvalid(axi_interconnect_0_M02_AXI_ARVALID),\n        .M02_AXI_awaddr(axi_interconnect_0_M02_AXI_AWADDR),\n        .M02_AXI_awburst(axi_interconnect_0_M02_AXI_AWBURST),\n        .M02_AXI_awcache(axi_interconnect_0_M02_AXI_AWCACHE),\n        .M02_AXI_awid(axi_interconnect_0_M02_AXI_AWID),\n        .M02_AXI_awlen(axi_interconnect_0_M02_AXI_AWLEN),\n        .M02_AXI_awlock(axi_interconnect_0_M02_AXI_AWLOCK),\n        .M02_AXI_awprot(axi_interconnect_0_M02_AXI_AWPROT),\n        .M02_AXI_awqos(axi_interconnect_0_M02_AXI_AWQOS),\n        .M02_AXI_awready(axi_interconnect_0_M02_AXI_AWREADY),\n        .M02_AXI_awregion(axi_interconnect_0_M02_AXI_AWREGION),\n        .M02_AXI_awsize(axi_interconnect_0_M02_AXI_AWSIZE),\n        .M02_AXI_awvalid(axi_interconnect_0_M02_AXI_AWVALID),\n        .M02_AXI_bid(axi_interconnect_0_M02_AXI_BID),\n        .M02_AXI_bready(axi_interconnect_0_M02_AXI_BREADY),\n        .M02_AXI_bresp(axi_interconnect_0_M02_AXI_BRESP),\n        .M02_AXI_bvalid(axi_interconnect_0_M02_AXI_BVALID),\n        .M02_AXI_rdata(axi_interconnect_0_M02_AXI_RDATA),\n        .M02_AXI_rid(axi_interconnect_0_M02_AXI_RID),\n        .M02_AXI_rlast(axi_interconnect_0_M02_AXI_RLAST),\n        .M02_AXI_rready(axi_interconnect_0_M02_AXI_RREADY),\n        .M02_AXI_rresp(axi_interconnect_0_M02_AXI_RRESP),\n        .M02_AXI_rvalid(axi_interconnect_0_M02_AXI_RVALID),\n        .M02_AXI_wdata(axi_interconnect_0_M02_AXI_WDATA),\n        .M02_AXI_wlast(axi_interconnect_0_M02_AXI_WLAST),\n        .M02_AXI_wready(axi_interconnect_0_M02_AXI_WREADY),\n        .M02_AXI_wstrb(axi_interconnect_0_M02_AXI_WSTRB),\n        .M02_AXI_wvalid(axi_interconnect_0_M02_AXI_WVALID),\n        .M03_ACLK(ACLK_1),\n        .M03_ARESETN(ARESETN_1),\n        .M03_AXI_araddr(axi_interconnect_0_M03_AXI_ARADDR),\n        .M03_AXI_arburst(axi_interconnect_0_M03_AXI_ARBURST),\n        .M03_AXI_arcache(axi_interconnect_0_M03_AXI_ARCACHE),\n        .M03_AXI_arid(axi_interconnect_0_M03_AXI_ARID),\n        .M03_AXI_arlen(axi_interconnect_0_M03_AXI_ARLEN),\n        .M03_AXI_arlock(axi_interconnect_0_M03_AXI_ARLOCK),\n        .M03_AXI_arprot(axi_interconnect_0_M03_AXI_ARPROT),\n        .M03_AXI_arqos(axi_interconnect_0_M03_AXI_ARQOS),\n        .M03_AXI_arready(axi_interconnect_0_M03_AXI_ARREADY),\n        .M03_AXI_arregion(axi_interconnect_0_M03_AXI_ARREGION),\n        .M03_AXI_arsize(axi_interconnect_0_M03_AXI_ARSIZE),\n        .M03_AXI_arvalid(axi_interconnect_0_M03_AXI_ARVALID),\n        .M03_AXI_awaddr(axi_interconnect_0_M03_AXI_AWADDR),\n        .M03_AXI_awburst(axi_interconnect_0_M03_AXI_AWBURST),\n        .M03_AXI_awcache(axi_interconnect_0_M03_AXI_AWCACHE),\n        .M03_AXI_awid(axi_interconnect_0_M03_AXI_AWID),\n        .M03_AXI_awlen(axi_interconnect_0_M03_AXI_AWLEN),\n        .M03_AXI_awlock(axi_interconnect_0_M03_AXI_AWLOCK),\n        .M03_AXI_awprot(axi_interconnect_0_M03_AXI_AWPROT),\n        .M03_AXI_awqos(axi_interconnect_0_M03_AXI_AWQOS),\n        .M03_AXI_awready(axi_interconnect_0_M03_AXI_AWREADY),\n        .M03_AXI_awregion(axi_interconnect_0_M03_AXI_AWREGION),\n        .M03_AXI_awsize(axi_interconnect_0_M03_AXI_AWSIZE),\n        .M03_AXI_awvalid(axi_interconnect_0_M03_AXI_AWVALID),\n        .M03_AXI_bid(axi_interconnect_0_M03_AXI_BID),\n        .M03_AXI_bready(axi_interconnect_0_M03_AXI_BREADY),\n        .M03_AXI_bresp(axi_interconnect_0_M03_AXI_BRESP),\n        .M03_AXI_bvalid(axi_interconnect_0_M03_AXI_BVALID),\n        .M03_AXI_rdata(axi_interconnect_0_M03_AXI_RDATA),\n        .M03_AXI_rid(axi_interconnect_0_M03_AXI_RID),\n        .M03_AXI_rlast(axi_interconnect_0_M03_AXI_RLAST),\n        .M03_AXI_rready(axi_interconnect_0_M03_AXI_RREADY),\n        .M03_AXI_rresp(axi_interconnect_0_M03_AXI_RRESP),\n        .M03_AXI_rvalid(axi_interconnect_0_M03_AXI_RVALID),\n        .M03_AXI_wdata(axi_interconnect_0_M03_AXI_WDATA),\n        .M03_AXI_wlast(axi_interconnect_0_M03_AXI_WLAST),\n        .M03_AXI_wready(axi_interconnect_0_M03_AXI_WREADY),\n        .M03_AXI_wstrb(axi_interconnect_0_M03_AXI_WSTRB),\n        .M03_AXI_wvalid(axi_interconnect_0_M03_AXI_WVALID),\n        .S00_ACLK(ACLK_1),\n        .S00_ARESETN(ARESETN_1),\n        .S00_AXI_araddr(S00_AXI_1_ARADDR),\n        .S00_AXI_arburst(S00_AXI_1_ARBURST),\n        .S00_AXI_arcache(S00_AXI_1_ARCACHE),\n        .S00_AXI_arid(S00_AXI_1_ARID),\n        .S00_AXI_arlen(S00_AXI_1_ARLEN),\n        .S00_AXI_arlock(S00_AXI_1_ARLOCK),\n        .S00_AXI_arprot(S00_AXI_1_ARPROT),\n        .S00_AXI_arqos(S00_AXI_1_ARQOS),\n        .S00_AXI_arready(S00_AXI_1_ARREADY),\n        .S00_AXI_arregion(S00_AXI_1_ARREGION),\n        .S00_AXI_arsize(S00_AXI_1_ARSIZE),\n        .S00_AXI_arvalid(S00_AXI_1_ARVALID),\n        .S00_AXI_awaddr(S00_AXI_1_AWADDR),\n        .S00_AXI_awburst(S00_AXI_1_AWBURST),\n        .S00_AXI_awcache(S00_AXI_1_AWCACHE),\n        .S00_AXI_awid(S00_AXI_1_AWID),\n        .S00_AXI_awlen(S00_AXI_1_AWLEN),\n        .S00_AXI_awlock(S00_AXI_1_AWLOCK),\n        .S00_AXI_awprot(S00_AXI_1_AWPROT),\n        .S00_AXI_awqos(S00_AXI_1_AWQOS),\n        .S00_AXI_awready(S00_AXI_1_AWREADY),\n        .S00_AXI_awregion(S00_AXI_1_AWREGION),\n        .S00_AXI_awsize(S00_AXI_1_AWSIZE),\n        .S00_AXI_awvalid(S00_AXI_1_AWVALID),\n        .S00_AXI_bid(S00_AXI_1_BID),\n        .S00_AXI_bready(S00_AXI_1_BREADY),\n        .S00_AXI_bresp(S00_AXI_1_BRESP),\n        .S00_AXI_bvalid(S00_AXI_1_BVALID),\n        .S00_AXI_rdata(S00_AXI_1_RDATA),\n        .S00_AXI_rid(S00_AXI_1_RID),\n        .S00_AXI_rlast(S00_AXI_1_RLAST),\n        .S00_AXI_rready(S00_AXI_1_RREADY),\n        .S00_AXI_rresp(S00_AXI_1_RRESP),\n        .S00_AXI_rvalid(S00_AXI_1_RVALID),\n        .S00_AXI_wdata(S00_AXI_1_WDATA),\n        .S00_AXI_wlast(S00_AXI_1_WLAST),\n        .S00_AXI_wready(S00_AXI_1_WREADY),\n        .S00_AXI_wstrb(S00_AXI_1_WSTRB),\n        .S00_AXI_wvalid(S00_AXI_1_WVALID),\n        .S01_ACLK(ACLK_1),\n        .S01_ARESETN(ARESETN_1),\n        .S01_AXI_araddr(S01_AXI_1_ARADDR),\n        .S01_AXI_arburst(S01_AXI_1_ARBURST),\n        .S01_AXI_arcache(S01_AXI_1_ARCACHE),\n        .S01_AXI_arid(S01_AXI_1_ARID),\n        .S01_AXI_arlen(S01_AXI_1_ARLEN),\n        .S01_AXI_arlock(S01_AXI_1_ARLOCK),\n        .S01_AXI_arprot(S01_AXI_1_ARPROT),\n        .S01_AXI_arqos(S01_AXI_1_ARQOS),\n        .S01_AXI_arready(S01_AXI_1_ARREADY),\n        .S01_AXI_arregion(S01_AXI_1_ARREGION),\n        .S01_AXI_arsize(S01_AXI_1_ARSIZE),\n        .S01_AXI_arvalid(S01_AXI_1_ARVALID),\n        .S01_AXI_awaddr(S01_AXI_1_AWADDR),\n        .S01_AXI_awburst(S01_AXI_1_AWBURST),\n        .S01_AXI_awcache(S01_AXI_1_AWCACHE),\n        .S01_AXI_awid(S01_AXI_1_AWID),\n        .S01_AXI_awlen(S01_AXI_1_AWLEN),\n        .S01_AXI_awlock(S01_AXI_1_AWLOCK),\n        .S01_AXI_awprot(S01_AXI_1_AWPROT),\n        .S01_AXI_awqos(S01_AXI_1_AWQOS),\n        .S01_AXI_awready(S01_AXI_1_AWREADY),\n        .S01_AXI_awregion(S01_AXI_1_AWREGION),\n        .S01_AXI_awsize(S01_AXI_1_AWSIZE),\n        .S01_AXI_awvalid(S01_AXI_1_AWVALID),\n        .S01_AXI_bid(S01_AXI_1_BID),\n        .S01_AXI_bready(S01_AXI_1_BREADY),\n        .S01_AXI_bresp(S01_AXI_1_BRESP),\n        .S01_AXI_bvalid(S01_AXI_1_BVALID),\n        .S01_AXI_rdata(S01_AXI_1_RDATA),\n        .S01_AXI_rid(S01_AXI_1_RID),\n        .S01_AXI_rlast(S01_AXI_1_RLAST),\n        .S01_AXI_rready(S01_AXI_1_RREADY),\n        .S01_AXI_rresp(S01_AXI_1_RRESP),\n        .S01_AXI_rvalid(S01_AXI_1_RVALID),\n        .S01_AXI_wdata(S01_AXI_1_WDATA),\n        .S01_AXI_wlast(S01_AXI_1_WLAST),\n        .S01_AXI_wready(S01_AXI_1_WREADY),\n        .S01_AXI_wstrb(S01_AXI_1_WSTRB),\n        .S01_AXI_wvalid(S01_AXI_1_WVALID));\nendmodule\n\nmodule cl_axi_interconnect_axi_interconnect_0_0\n   (ACLK,\n    ARESETN,\n    M00_ACLK,\n    M00_ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_ACLK,\n    M01_ARESETN,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_ACLK,\n    M02_ARESETN,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_ACLK,\n    M03_ARESETN,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_ACLK,\n    S00_ARESETN,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_ACLK,\n    S01_ARESETN,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  input ACLK;\n  input ARESETN;\n  input M00_ACLK;\n  input M00_ARESETN;\n  output [63:0]M00_AXI_araddr;\n  output [1:0]M00_AXI_arburst;\n  output [3:0]M00_AXI_arcache;\n  output [6:0]M00_AXI_arid;\n  output [7:0]M00_AXI_arlen;\n  output [0:0]M00_AXI_arlock;\n  output [2:0]M00_AXI_arprot;\n  output [3:0]M00_AXI_arqos;\n  input M00_AXI_arready;\n  output [3:0]M00_AXI_arregion;\n  output [2:0]M00_AXI_arsize;\n  output M00_AXI_arvalid;\n  output [63:0]M00_AXI_awaddr;\n  output [1:0]M00_AXI_awburst;\n  output [3:0]M00_AXI_awcache;\n  output [6:0]M00_AXI_awid;\n  output [7:0]M00_AXI_awlen;\n  output [0:0]M00_AXI_awlock;\n  output [2:0]M00_AXI_awprot;\n  output [3:0]M00_AXI_awqos;\n  input M00_AXI_awready;\n  output [3:0]M00_AXI_awregion;\n  output [2:0]M00_AXI_awsize;\n  output M00_AXI_awvalid;\n  input [6:0]M00_AXI_bid;\n  output M00_AXI_bready;\n  input [1:0]M00_AXI_bresp;\n  input M00_AXI_bvalid;\n  input [511:0]M00_AXI_rdata;\n  input [6:0]M00_AXI_rid;\n  input M00_AXI_rlast;\n  output M00_AXI_rready;\n  input [1:0]M00_AXI_rresp;\n  input M00_AXI_rvalid;\n  output [511:0]M00_AXI_wdata;\n  output M00_AXI_wlast;\n  input M00_AXI_wready;\n  output [63:0]M00_AXI_wstrb;\n  output M00_AXI_wvalid;\n  input M01_ACLK;\n  input M01_ARESETN;\n  output [63:0]M01_AXI_araddr;\n  output [1:0]M01_AXI_arburst;\n  output [3:0]M01_AXI_arcache;\n  output [6:0]M01_AXI_arid;\n  output [7:0]M01_AXI_arlen;\n  output [0:0]M01_AXI_arlock;\n  output [2:0]M01_AXI_arprot;\n  output [3:0]M01_AXI_arqos;\n  input M01_AXI_arready;\n  output [3:0]M01_AXI_arregion;\n  output [2:0]M01_AXI_arsize;\n  output M01_AXI_arvalid;\n  output [63:0]M01_AXI_awaddr;\n  output [1:0]M01_AXI_awburst;\n  output [3:0]M01_AXI_awcache;\n  output [6:0]M01_AXI_awid;\n  output [7:0]M01_AXI_awlen;\n  output [0:0]M01_AXI_awlock;\n  output [2:0]M01_AXI_awprot;\n  output [3:0]M01_AXI_awqos;\n  input M01_AXI_awready;\n  output [3:0]M01_AXI_awregion;\n  output [2:0]M01_AXI_awsize;\n  output M01_AXI_awvalid;\n  input [6:0]M01_AXI_bid;\n  output M01_AXI_bready;\n  input [1:0]M01_AXI_bresp;\n  input M01_AXI_bvalid;\n  input [511:0]M01_AXI_rdata;\n  input [6:0]M01_AXI_rid;\n  input M01_AXI_rlast;\n  output M01_AXI_rready;\n  input [1:0]M01_AXI_rresp;\n  input M01_AXI_rvalid;\n  output [511:0]M01_AXI_wdata;\n  output M01_AXI_wlast;\n  input M01_AXI_wready;\n  output [63:0]M01_AXI_wstrb;\n  output M01_AXI_wvalid;\n  input M02_ACLK;\n  input M02_ARESETN;\n  output [63:0]M02_AXI_araddr;\n  output [1:0]M02_AXI_arburst;\n  output [3:0]M02_AXI_arcache;\n  output [6:0]M02_AXI_arid;\n  output [7:0]M02_AXI_arlen;\n  output [0:0]M02_AXI_arlock;\n  output [2:0]M02_AXI_arprot;\n  output [3:0]M02_AXI_arqos;\n  input M02_AXI_arready;\n  output [3:0]M02_AXI_arregion;\n  output [2:0]M02_AXI_arsize;\n  output M02_AXI_arvalid;\n  output [63:0]M02_AXI_awaddr;\n  output [1:0]M02_AXI_awburst;\n  output [3:0]M02_AXI_awcache;\n  output [6:0]M02_AXI_awid;\n  output [7:0]M02_AXI_awlen;\n  output [0:0]M02_AXI_awlock;\n  output [2:0]M02_AXI_awprot;\n  output [3:0]M02_AXI_awqos;\n  input M02_AXI_awready;\n  output [3:0]M02_AXI_awregion;\n  output [2:0]M02_AXI_awsize;\n  output M02_AXI_awvalid;\n  input [6:0]M02_AXI_bid;\n  output M02_AXI_bready;\n  input [1:0]M02_AXI_bresp;\n  input M02_AXI_bvalid;\n  input [511:0]M02_AXI_rdata;\n  input [6:0]M02_AXI_rid;\n  input M02_AXI_rlast;\n  output M02_AXI_rready;\n  input [1:0]M02_AXI_rresp;\n  input M02_AXI_rvalid;\n  output [511:0]M02_AXI_wdata;\n  output M02_AXI_wlast;\n  input M02_AXI_wready;\n  output [63:0]M02_AXI_wstrb;\n  output M02_AXI_wvalid;\n  input M03_ACLK;\n  input M03_ARESETN;\n  output [63:0]M03_AXI_araddr;\n  output [1:0]M03_AXI_arburst;\n  output [3:0]M03_AXI_arcache;\n  output [6:0]M03_AXI_arid;\n  output [7:0]M03_AXI_arlen;\n  output [0:0]M03_AXI_arlock;\n  output [2:0]M03_AXI_arprot;\n  output [3:0]M03_AXI_arqos;\n  input M03_AXI_arready;\n  output [3:0]M03_AXI_arregion;\n  output [2:0]M03_AXI_arsize;\n  output M03_AXI_arvalid;\n  output [63:0]M03_AXI_awaddr;\n  output [1:0]M03_AXI_awburst;\n  output [3:0]M03_AXI_awcache;\n  output [6:0]M03_AXI_awid;\n  output [7:0]M03_AXI_awlen;\n  output [0:0]M03_AXI_awlock;\n  output [2:0]M03_AXI_awprot;\n  output [3:0]M03_AXI_awqos;\n  input M03_AXI_awready;\n  output [3:0]M03_AXI_awregion;\n  output [2:0]M03_AXI_awsize;\n  output M03_AXI_awvalid;\n  input [6:0]M03_AXI_bid;\n  output M03_AXI_bready;\n  input [1:0]M03_AXI_bresp;\n  input M03_AXI_bvalid;\n  input [511:0]M03_AXI_rdata;\n  input [6:0]M03_AXI_rid;\n  input M03_AXI_rlast;\n  output M03_AXI_rready;\n  input [1:0]M03_AXI_rresp;\n  input M03_AXI_rvalid;\n  output [511:0]M03_AXI_wdata;\n  output M03_AXI_wlast;\n  input M03_AXI_wready;\n  output [63:0]M03_AXI_wstrb;\n  output M03_AXI_wvalid;\n  input S00_ACLK;\n  input S00_ARESETN;\n  input [63:0]S00_AXI_araddr;\n  input [1:0]S00_AXI_arburst;\n  input [3:0]S00_AXI_arcache;\n  input [5:0]S00_AXI_arid;\n  input [7:0]S00_AXI_arlen;\n  input [0:0]S00_AXI_arlock;\n  input [2:0]S00_AXI_arprot;\n  input [3:0]S00_AXI_arqos;\n  output S00_AXI_arready;\n  input [3:0]S00_AXI_arregion;\n  input [2:0]S00_AXI_arsize;\n  input S00_AXI_arvalid;\n  input [63:0]S00_AXI_awaddr;\n  input [1:0]S00_AXI_awburst;\n  input [3:0]S00_AXI_awcache;\n  input [5:0]S00_AXI_awid;\n  input [7:0]S00_AXI_awlen;\n  input [0:0]S00_AXI_awlock;\n  input [2:0]S00_AXI_awprot;\n  input [3:0]S00_AXI_awqos;\n  output S00_AXI_awready;\n  input [3:0]S00_AXI_awregion;\n  input [2:0]S00_AXI_awsize;\n  input S00_AXI_awvalid;\n  output [5:0]S00_AXI_bid;\n  input S00_AXI_bready;\n  output [1:0]S00_AXI_bresp;\n  output S00_AXI_bvalid;\n  output [511:0]S00_AXI_rdata;\n  output [5:0]S00_AXI_rid;\n  output S00_AXI_rlast;\n  input S00_AXI_rready;\n  output [1:0]S00_AXI_rresp;\n  output S00_AXI_rvalid;\n  input [511:0]S00_AXI_wdata;\n  input S00_AXI_wlast;\n  output S00_AXI_wready;\n  input [63:0]S00_AXI_wstrb;\n  input S00_AXI_wvalid;\n  input S01_ACLK;\n  input S01_ARESETN;\n  input [63:0]S01_AXI_araddr;\n  input [1:0]S01_AXI_arburst;\n  input [3:0]S01_AXI_arcache;\n  input [5:0]S01_AXI_arid;\n  input [7:0]S01_AXI_arlen;\n  input [0:0]S01_AXI_arlock;\n  input [2:0]S01_AXI_arprot;\n  input [3:0]S01_AXI_arqos;\n  output S01_AXI_arready;\n  input [3:0]S01_AXI_arregion;\n  input [2:0]S01_AXI_arsize;\n  input S01_AXI_arvalid;\n  input [63:0]S01_AXI_awaddr;\n  input [1:0]S01_AXI_awburst;\n  input [3:0]S01_AXI_awcache;\n  input [5:0]S01_AXI_awid;\n  input [7:0]S01_AXI_awlen;\n  input [0:0]S01_AXI_awlock;\n  input [2:0]S01_AXI_awprot;\n  input [3:0]S01_AXI_awqos;\n  output S01_AXI_awready;\n  input [3:0]S01_AXI_awregion;\n  input [2:0]S01_AXI_awsize;\n  input S01_AXI_awvalid;\n  output [5:0]S01_AXI_bid;\n  input S01_AXI_bready;\n  output [1:0]S01_AXI_bresp;\n  output S01_AXI_bvalid;\n  output [511:0]S01_AXI_rdata;\n  output [5:0]S01_AXI_rid;\n  output S01_AXI_rlast;\n  input S01_AXI_rready;\n  output [1:0]S01_AXI_rresp;\n  output S01_AXI_rvalid;\n  input [511:0]S01_AXI_wdata;\n  input S01_AXI_wlast;\n  output S01_AXI_wready;\n  input [63:0]S01_AXI_wstrb;\n  input S01_AXI_wvalid;\n\n  wire axi_interconnect_0_ACLK_net;\n  wire axi_interconnect_0_ARESETN_net;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_ARADDR;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_ARBURST;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARCACHE;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_ARID;\n  wire [7:0]axi_interconnect_0_to_s00_couplers_ARLEN;\n  wire [0:0]axi_interconnect_0_to_s00_couplers_ARLOCK;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_ARPROT;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARQOS;\n  wire axi_interconnect_0_to_s00_couplers_ARREADY;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARREGION;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_ARSIZE;\n  wire axi_interconnect_0_to_s00_couplers_ARVALID;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_AWADDR;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_AWBURST;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWCACHE;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_AWID;\n  wire [7:0]axi_interconnect_0_to_s00_couplers_AWLEN;\n  wire [0:0]axi_interconnect_0_to_s00_couplers_AWLOCK;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_AWPROT;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWQOS;\n  wire axi_interconnect_0_to_s00_couplers_AWREADY;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWREGION;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_AWSIZE;\n  wire axi_interconnect_0_to_s00_couplers_AWVALID;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_BID;\n  wire axi_interconnect_0_to_s00_couplers_BREADY;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_BRESP;\n  wire axi_interconnect_0_to_s00_couplers_BVALID;\n  wire [511:0]axi_interconnect_0_to_s00_couplers_RDATA;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_RID;\n  wire axi_interconnect_0_to_s00_couplers_RLAST;\n  wire axi_interconnect_0_to_s00_couplers_RREADY;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_RRESP;\n  wire axi_interconnect_0_to_s00_couplers_RVALID;\n  wire [511:0]axi_interconnect_0_to_s00_couplers_WDATA;\n  wire axi_interconnect_0_to_s00_couplers_WLAST;\n  wire axi_interconnect_0_to_s00_couplers_WREADY;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_WSTRB;\n  wire axi_interconnect_0_to_s00_couplers_WVALID;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_ARADDR;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_ARBURST;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARCACHE;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_ARID;\n  wire [7:0]axi_interconnect_0_to_s01_couplers_ARLEN;\n  wire [0:0]axi_interconnect_0_to_s01_couplers_ARLOCK;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_ARPROT;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARQOS;\n  wire axi_interconnect_0_to_s01_couplers_ARREADY;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARREGION;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_ARSIZE;\n  wire axi_interconnect_0_to_s01_couplers_ARVALID;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_AWADDR;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_AWBURST;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWCACHE;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_AWID;\n  wire [7:0]axi_interconnect_0_to_s01_couplers_AWLEN;\n  wire [0:0]axi_interconnect_0_to_s01_couplers_AWLOCK;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_AWPROT;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWQOS;\n  wire axi_interconnect_0_to_s01_couplers_AWREADY;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWREGION;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_AWSIZE;\n  wire axi_interconnect_0_to_s01_couplers_AWVALID;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_BID;\n  wire axi_interconnect_0_to_s01_couplers_BREADY;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_BRESP;\n  wire axi_interconnect_0_to_s01_couplers_BVALID;\n  wire [511:0]axi_interconnect_0_to_s01_couplers_RDATA;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_RID;\n  wire axi_interconnect_0_to_s01_couplers_RLAST;\n  wire axi_interconnect_0_to_s01_couplers_RREADY;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_RRESP;\n  wire axi_interconnect_0_to_s01_couplers_RVALID;\n  wire [511:0]axi_interconnect_0_to_s01_couplers_WDATA;\n  wire axi_interconnect_0_to_s01_couplers_WLAST;\n  wire axi_interconnect_0_to_s01_couplers_WREADY;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_WSTRB;\n  wire axi_interconnect_0_to_s01_couplers_WVALID;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m00_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m00_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARQOS;\n  wire m00_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m00_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m00_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m00_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWQOS;\n  wire m00_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m00_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_BID;\n  wire m00_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_BRESP;\n  wire m00_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m00_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_RID;\n  wire m00_couplers_to_axi_interconnect_0_RLAST;\n  wire m00_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_RRESP;\n  wire m00_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m00_couplers_to_axi_interconnect_0_WDATA;\n  wire m00_couplers_to_axi_interconnect_0_WLAST;\n  wire m00_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_WSTRB;\n  wire m00_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m01_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m01_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARQOS;\n  wire m01_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m01_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m01_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m01_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWQOS;\n  wire m01_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m01_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_BID;\n  wire m01_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_BRESP;\n  wire m01_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m01_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_RID;\n  wire m01_couplers_to_axi_interconnect_0_RLAST;\n  wire m01_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_RRESP;\n  wire m01_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m01_couplers_to_axi_interconnect_0_WDATA;\n  wire m01_couplers_to_axi_interconnect_0_WLAST;\n  wire m01_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_WSTRB;\n  wire m01_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m02_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m02_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARQOS;\n  wire m02_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m02_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m02_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m02_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWQOS;\n  wire m02_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m02_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_BID;\n  wire m02_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_BRESP;\n  wire m02_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m02_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_RID;\n  wire m02_couplers_to_axi_interconnect_0_RLAST;\n  wire m02_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_RRESP;\n  wire m02_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m02_couplers_to_axi_interconnect_0_WDATA;\n  wire m02_couplers_to_axi_interconnect_0_WLAST;\n  wire m02_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_WSTRB;\n  wire m02_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m03_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m03_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARQOS;\n  wire m03_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m03_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m03_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m03_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWQOS;\n  wire m03_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m03_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_BID;\n  wire m03_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_BRESP;\n  wire m03_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m03_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_RID;\n  wire m03_couplers_to_axi_interconnect_0_RLAST;\n  wire m03_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_RRESP;\n  wire m03_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m03_couplers_to_axi_interconnect_0_WDATA;\n  wire m03_couplers_to_axi_interconnect_0_WLAST;\n  wire m03_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_WSTRB;\n  wire m03_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]s00_couplers_to_xbar_ARADDR;\n  wire [1:0]s00_couplers_to_xbar_ARBURST;\n  wire [3:0]s00_couplers_to_xbar_ARCACHE;\n  wire [5:0]s00_couplers_to_xbar_ARID;\n  wire [7:0]s00_couplers_to_xbar_ARLEN;\n  wire [0:0]s00_couplers_to_xbar_ARLOCK;\n  wire [2:0]s00_couplers_to_xbar_ARPROT;\n  wire [3:0]s00_couplers_to_xbar_ARQOS;\n  wire [0:0]s00_couplers_to_xbar_ARREADY;\n  wire [2:0]s00_couplers_to_xbar_ARSIZE;\n  wire s00_couplers_to_xbar_ARVALID;\n  wire [63:0]s00_couplers_to_xbar_AWADDR;\n  wire [1:0]s00_couplers_to_xbar_AWBURST;\n  wire [3:0]s00_couplers_to_xbar_AWCACHE;\n  wire [5:0]s00_couplers_to_xbar_AWID;\n  wire [7:0]s00_couplers_to_xbar_AWLEN;\n  wire [0:0]s00_couplers_to_xbar_AWLOCK;\n  wire [2:0]s00_couplers_to_xbar_AWPROT;\n  wire [3:0]s00_couplers_to_xbar_AWQOS;\n  wire [0:0]s00_couplers_to_xbar_AWREADY;\n  wire [2:0]s00_couplers_to_xbar_AWSIZE;\n  wire s00_couplers_to_xbar_AWVALID;\n  wire [6:0]s00_couplers_to_xbar_BID;\n  wire s00_couplers_to_xbar_BREADY;\n  wire [1:0]s00_couplers_to_xbar_BRESP;\n  wire [0:0]s00_couplers_to_xbar_BVALID;\n  wire [511:0]s00_couplers_to_xbar_RDATA;\n  wire [6:0]s00_couplers_to_xbar_RID;\n  wire [0:0]s00_couplers_to_xbar_RLAST;\n  wire s00_couplers_to_xbar_RREADY;\n  wire [1:0]s00_couplers_to_xbar_RRESP;\n  wire [0:0]s00_couplers_to_xbar_RVALID;\n  wire [511:0]s00_couplers_to_xbar_WDATA;\n  wire s00_couplers_to_xbar_WLAST;\n  wire [0:0]s00_couplers_to_xbar_WREADY;\n  wire [63:0]s00_couplers_to_xbar_WSTRB;\n  wire s00_couplers_to_xbar_WVALID;\n  wire [63:0]s01_couplers_to_xbar_ARADDR;\n  wire [1:0]s01_couplers_to_xbar_ARBURST;\n  wire [3:0]s01_couplers_to_xbar_ARCACHE;\n  wire [5:0]s01_couplers_to_xbar_ARID;\n  wire [7:0]s01_couplers_to_xbar_ARLEN;\n  wire [0:0]s01_couplers_to_xbar_ARLOCK;\n  wire [2:0]s01_couplers_to_xbar_ARPROT;\n  wire [3:0]s01_couplers_to_xbar_ARQOS;\n  wire [1:1]s01_couplers_to_xbar_ARREADY;\n  wire [2:0]s01_couplers_to_xbar_ARSIZE;\n  wire s01_couplers_to_xbar_ARVALID;\n  wire [63:0]s01_couplers_to_xbar_AWADDR;\n  wire [1:0]s01_couplers_to_xbar_AWBURST;\n  wire [3:0]s01_couplers_to_xbar_AWCACHE;\n  wire [5:0]s01_couplers_to_xbar_AWID;\n  wire [7:0]s01_couplers_to_xbar_AWLEN;\n  wire [0:0]s01_couplers_to_xbar_AWLOCK;\n  wire [2:0]s01_couplers_to_xbar_AWPROT;\n  wire [3:0]s01_couplers_to_xbar_AWQOS;\n  wire [1:1]s01_couplers_to_xbar_AWREADY;\n  wire [2:0]s01_couplers_to_xbar_AWSIZE;\n  wire s01_couplers_to_xbar_AWVALID;\n  wire [13:7]s01_couplers_to_xbar_BID;\n  wire s01_couplers_to_xbar_BREADY;\n  wire [3:2]s01_couplers_to_xbar_BRESP;\n  wire [1:1]s01_couplers_to_xbar_BVALID;\n  wire [1023:512]s01_couplers_to_xbar_RDATA;\n  wire [13:7]s01_couplers_to_xbar_RID;\n  wire [1:1]s01_couplers_to_xbar_RLAST;\n  wire s01_couplers_to_xbar_RREADY;\n  wire [3:2]s01_couplers_to_xbar_RRESP;\n  wire [1:1]s01_couplers_to_xbar_RVALID;\n  wire [511:0]s01_couplers_to_xbar_WDATA;\n  wire s01_couplers_to_xbar_WLAST;\n  wire [1:1]s01_couplers_to_xbar_WREADY;\n  wire [63:0]s01_couplers_to_xbar_WSTRB;\n  wire s01_couplers_to_xbar_WVALID;\n  wire [63:0]xbar_to_m00_couplers_ARADDR;\n  wire [1:0]xbar_to_m00_couplers_ARBURST;\n  wire [3:0]xbar_to_m00_couplers_ARCACHE;\n  wire [6:0]xbar_to_m00_couplers_ARID;\n  wire [7:0]xbar_to_m00_couplers_ARLEN;\n  wire [0:0]xbar_to_m00_couplers_ARLOCK;\n  wire [2:0]xbar_to_m00_couplers_ARPROT;\n  wire [3:0]xbar_to_m00_couplers_ARQOS;\n  wire xbar_to_m00_couplers_ARREADY;\n  wire [3:0]xbar_to_m00_couplers_ARREGION;\n  wire [2:0]xbar_to_m00_couplers_ARSIZE;\n  wire [0:0]xbar_to_m00_couplers_ARVALID;\n  wire [63:0]xbar_to_m00_couplers_AWADDR;\n  wire [1:0]xbar_to_m00_couplers_AWBURST;\n  wire [3:0]xbar_to_m00_couplers_AWCACHE;\n  wire [6:0]xbar_to_m00_couplers_AWID;\n  wire [7:0]xbar_to_m00_couplers_AWLEN;\n  wire [0:0]xbar_to_m00_couplers_AWLOCK;\n  wire [2:0]xbar_to_m00_couplers_AWPROT;\n  wire [3:0]xbar_to_m00_couplers_AWQOS;\n  wire xbar_to_m00_couplers_AWREADY;\n  wire [3:0]xbar_to_m00_couplers_AWREGION;\n  wire [2:0]xbar_to_m00_couplers_AWSIZE;\n  wire [0:0]xbar_to_m00_couplers_AWVALID;\n  wire [6:0]xbar_to_m00_couplers_BID;\n  wire [0:0]xbar_to_m00_couplers_BREADY;\n  wire [1:0]xbar_to_m00_couplers_BRESP;\n  wire xbar_to_m00_couplers_BVALID;\n  wire [511:0]xbar_to_m00_couplers_RDATA;\n  wire [6:0]xbar_to_m00_couplers_RID;\n  wire xbar_to_m00_couplers_RLAST;\n  wire [0:0]xbar_to_m00_couplers_RREADY;\n  wire [1:0]xbar_to_m00_couplers_RRESP;\n  wire xbar_to_m00_couplers_RVALID;\n  wire [511:0]xbar_to_m00_couplers_WDATA;\n  wire [0:0]xbar_to_m00_couplers_WLAST;\n  wire xbar_to_m00_couplers_WREADY;\n  wire [63:0]xbar_to_m00_couplers_WSTRB;\n  wire [0:0]xbar_to_m00_couplers_WVALID;\n  wire [127:64]xbar_to_m01_couplers_ARADDR;\n  wire [3:2]xbar_to_m01_couplers_ARBURST;\n  wire [7:4]xbar_to_m01_couplers_ARCACHE;\n  wire [13:7]xbar_to_m01_couplers_ARID;\n  wire [15:8]xbar_to_m01_couplers_ARLEN;\n  wire [1:1]xbar_to_m01_couplers_ARLOCK;\n  wire [5:3]xbar_to_m01_couplers_ARPROT;\n  wire [7:4]xbar_to_m01_couplers_ARQOS;\n  wire xbar_to_m01_couplers_ARREADY;\n  wire [7:4]xbar_to_m01_couplers_ARREGION;\n  wire [5:3]xbar_to_m01_couplers_ARSIZE;\n  wire [1:1]xbar_to_m01_couplers_ARVALID;\n  wire [127:64]xbar_to_m01_couplers_AWADDR;\n  wire [3:2]xbar_to_m01_couplers_AWBURST;\n  wire [7:4]xbar_to_m01_couplers_AWCACHE;\n  wire [13:7]xbar_to_m01_couplers_AWID;\n  wire [15:8]xbar_to_m01_couplers_AWLEN;\n  wire [1:1]xbar_to_m01_couplers_AWLOCK;\n  wire [5:3]xbar_to_m01_couplers_AWPROT;\n  wire [7:4]xbar_to_m01_couplers_AWQOS;\n  wire xbar_to_m01_couplers_AWREADY;\n  wire [7:4]xbar_to_m01_couplers_AWREGION;\n  wire [5:3]xbar_to_m01_couplers_AWSIZE;\n  wire [1:1]xbar_to_m01_couplers_AWVALID;\n  wire [6:0]xbar_to_m01_couplers_BID;\n  wire [1:1]xbar_to_m01_couplers_BREADY;\n  wire [1:0]xbar_to_m01_couplers_BRESP;\n  wire xbar_to_m01_couplers_BVALID;\n  wire [511:0]xbar_to_m01_couplers_RDATA;\n  wire [6:0]xbar_to_m01_couplers_RID;\n  wire xbar_to_m01_couplers_RLAST;\n  wire [1:1]xbar_to_m01_couplers_RREADY;\n  wire [1:0]xbar_to_m01_couplers_RRESP;\n  wire xbar_to_m01_couplers_RVALID;\n  wire [1023:512]xbar_to_m01_couplers_WDATA;\n  wire [1:1]xbar_to_m01_couplers_WLAST;\n  wire xbar_to_m01_couplers_WREADY;\n  wire [127:64]xbar_to_m01_couplers_WSTRB;\n  wire [1:1]xbar_to_m01_couplers_WVALID;\n  wire [191:128]xbar_to_m02_couplers_ARADDR;\n  wire [5:4]xbar_to_m02_couplers_ARBURST;\n  wire [11:8]xbar_to_m02_couplers_ARCACHE;\n  wire [20:14]xbar_to_m02_couplers_ARID;\n  wire [23:16]xbar_to_m02_couplers_ARLEN;\n  wire [2:2]xbar_to_m02_couplers_ARLOCK;\n  wire [8:6]xbar_to_m02_couplers_ARPROT;\n  wire [11:8]xbar_to_m02_couplers_ARQOS;\n  wire xbar_to_m02_couplers_ARREADY;\n  wire [11:8]xbar_to_m02_couplers_ARREGION;\n  wire [8:6]xbar_to_m02_couplers_ARSIZE;\n  wire [2:2]xbar_to_m02_couplers_ARVALID;\n  wire [191:128]xbar_to_m02_couplers_AWADDR;\n  wire [5:4]xbar_to_m02_couplers_AWBURST;\n  wire [11:8]xbar_to_m02_couplers_AWCACHE;\n  wire [20:14]xbar_to_m02_couplers_AWID;\n  wire [23:16]xbar_to_m02_couplers_AWLEN;\n  wire [2:2]xbar_to_m02_couplers_AWLOCK;\n  wire [8:6]xbar_to_m02_couplers_AWPROT;\n  wire [11:8]xbar_to_m02_couplers_AWQOS;\n  wire xbar_to_m02_couplers_AWREADY;\n  wire [11:8]xbar_to_m02_couplers_AWREGION;\n  wire [8:6]xbar_to_m02_couplers_AWSIZE;\n  wire [2:2]xbar_to_m02_couplers_AWVALID;\n  wire [6:0]xbar_to_m02_couplers_BID;\n  wire [2:2]xbar_to_m02_couplers_BREADY;\n  wire [1:0]xbar_to_m02_couplers_BRESP;\n  wire xbar_to_m02_couplers_BVALID;\n  wire [511:0]xbar_to_m02_couplers_RDATA;\n  wire [6:0]xbar_to_m02_couplers_RID;\n  wire xbar_to_m02_couplers_RLAST;\n  wire [2:2]xbar_to_m02_couplers_RREADY;\n  wire [1:0]xbar_to_m02_couplers_RRESP;\n  wire xbar_to_m02_couplers_RVALID;\n  wire [1535:1024]xbar_to_m02_couplers_WDATA;\n  wire [2:2]xbar_to_m02_couplers_WLAST;\n  wire xbar_to_m02_couplers_WREADY;\n  wire [191:128]xbar_to_m02_couplers_WSTRB;\n  wire [2:2]xbar_to_m02_couplers_WVALID;\n  wire [255:192]xbar_to_m03_couplers_ARADDR;\n  wire [7:6]xbar_to_m03_couplers_ARBURST;\n  wire [15:12]xbar_to_m03_couplers_ARCACHE;\n  wire [27:21]xbar_to_m03_couplers_ARID;\n  wire [31:24]xbar_to_m03_couplers_ARLEN;\n  wire [3:3]xbar_to_m03_couplers_ARLOCK;\n  wire [11:9]xbar_to_m03_couplers_ARPROT;\n  wire [15:12]xbar_to_m03_couplers_ARQOS;\n  wire xbar_to_m03_couplers_ARREADY;\n  wire [15:12]xbar_to_m03_couplers_ARREGION;\n  wire [11:9]xbar_to_m03_couplers_ARSIZE;\n  wire [3:3]xbar_to_m03_couplers_ARVALID;\n  wire [255:192]xbar_to_m03_couplers_AWADDR;\n  wire [7:6]xbar_to_m03_couplers_AWBURST;\n  wire [15:12]xbar_to_m03_couplers_AWCACHE;\n  wire [27:21]xbar_to_m03_couplers_AWID;\n  wire [31:24]xbar_to_m03_couplers_AWLEN;\n  wire [3:3]xbar_to_m03_couplers_AWLOCK;\n  wire [11:9]xbar_to_m03_couplers_AWPROT;\n  wire [15:12]xbar_to_m03_couplers_AWQOS;\n  wire xbar_to_m03_couplers_AWREADY;\n  wire [15:12]xbar_to_m03_couplers_AWREGION;\n  wire [11:9]xbar_to_m03_couplers_AWSIZE;\n  wire [3:3]xbar_to_m03_couplers_AWVALID;\n  wire [6:0]xbar_to_m03_couplers_BID;\n  wire [3:3]xbar_to_m03_couplers_BREADY;\n  wire [1:0]xbar_to_m03_couplers_BRESP;\n  wire xbar_to_m03_couplers_BVALID;\n  wire [511:0]xbar_to_m03_couplers_RDATA;\n  wire [6:0]xbar_to_m03_couplers_RID;\n  wire xbar_to_m03_couplers_RLAST;\n  wire [3:3]xbar_to_m03_couplers_RREADY;\n  wire [1:0]xbar_to_m03_couplers_RRESP;\n  wire xbar_to_m03_couplers_RVALID;\n  wire [2047:1536]xbar_to_m03_couplers_WDATA;\n  wire [3:3]xbar_to_m03_couplers_WLAST;\n  wire xbar_to_m03_couplers_WREADY;\n  wire [255:192]xbar_to_m03_couplers_WSTRB;\n  wire [3:3]xbar_to_m03_couplers_WVALID;\n\n  assign M00_AXI_araddr[63:0] = m00_couplers_to_axi_interconnect_0_ARADDR;\n  assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_interconnect_0_ARBURST;\n  assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M00_AXI_arid[6:0] = m00_couplers_to_axi_interconnect_0_ARID;\n  assign M00_AXI_arlen[7:0] = m00_couplers_to_axi_interconnect_0_ARLEN;\n  assign M00_AXI_arlock[0] = m00_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_interconnect_0_ARPROT;\n  assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_interconnect_0_ARQOS;\n  assign M00_AXI_arregion[3:0] = m00_couplers_to_axi_interconnect_0_ARREGION;\n  assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M00_AXI_arvalid = m00_couplers_to_axi_interconnect_0_ARVALID;\n  assign M00_AXI_awaddr[63:0] = m00_couplers_to_axi_interconnect_0_AWADDR;\n  assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_interconnect_0_AWBURST;\n  assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M00_AXI_awid[6:0] = m00_couplers_to_axi_interconnect_0_AWID;\n  assign M00_AXI_awlen[7:0] = m00_couplers_to_axi_interconnect_0_AWLEN;\n  assign M00_AXI_awlock[0] = m00_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_interconnect_0_AWPROT;\n  assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_interconnect_0_AWQOS;\n  assign M00_AXI_awregion[3:0] = m00_couplers_to_axi_interconnect_0_AWREGION;\n  assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M00_AXI_awvalid = m00_couplers_to_axi_interconnect_0_AWVALID;\n  assign M00_AXI_bready = m00_couplers_to_axi_interconnect_0_BREADY;\n  assign M00_AXI_rready = m00_couplers_to_axi_interconnect_0_RREADY;\n  assign M00_AXI_wdata[511:0] = m00_couplers_to_axi_interconnect_0_WDATA;\n  assign M00_AXI_wlast = m00_couplers_to_axi_interconnect_0_WLAST;\n  assign M00_AXI_wstrb[63:0] = m00_couplers_to_axi_interconnect_0_WSTRB;\n  assign M00_AXI_wvalid = m00_couplers_to_axi_interconnect_0_WVALID;\n  assign M01_AXI_araddr[63:0] = m01_couplers_to_axi_interconnect_0_ARADDR;\n  assign M01_AXI_arburst[1:0] = m01_couplers_to_axi_interconnect_0_ARBURST;\n  assign M01_AXI_arcache[3:0] = m01_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M01_AXI_arid[6:0] = m01_couplers_to_axi_interconnect_0_ARID;\n  assign M01_AXI_arlen[7:0] = m01_couplers_to_axi_interconnect_0_ARLEN;\n  assign M01_AXI_arlock[0] = m01_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M01_AXI_arprot[2:0] = m01_couplers_to_axi_interconnect_0_ARPROT;\n  assign M01_AXI_arqos[3:0] = m01_couplers_to_axi_interconnect_0_ARQOS;\n  assign M01_AXI_arregion[3:0] = m01_couplers_to_axi_interconnect_0_ARREGION;\n  assign M01_AXI_arsize[2:0] = m01_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M01_AXI_arvalid = m01_couplers_to_axi_interconnect_0_ARVALID;\n  assign M01_AXI_awaddr[63:0] = m01_couplers_to_axi_interconnect_0_AWADDR;\n  assign M01_AXI_awburst[1:0] = m01_couplers_to_axi_interconnect_0_AWBURST;\n  assign M01_AXI_awcache[3:0] = m01_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M01_AXI_awid[6:0] = m01_couplers_to_axi_interconnect_0_AWID;\n  assign M01_AXI_awlen[7:0] = m01_couplers_to_axi_interconnect_0_AWLEN;\n  assign M01_AXI_awlock[0] = m01_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M01_AXI_awprot[2:0] = m01_couplers_to_axi_interconnect_0_AWPROT;\n  assign M01_AXI_awqos[3:0] = m01_couplers_to_axi_interconnect_0_AWQOS;\n  assign M01_AXI_awregion[3:0] = m01_couplers_to_axi_interconnect_0_AWREGION;\n  assign M01_AXI_awsize[2:0] = m01_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M01_AXI_awvalid = m01_couplers_to_axi_interconnect_0_AWVALID;\n  assign M01_AXI_bready = m01_couplers_to_axi_interconnect_0_BREADY;\n  assign M01_AXI_rready = m01_couplers_to_axi_interconnect_0_RREADY;\n  assign M01_AXI_wdata[511:0] = m01_couplers_to_axi_interconnect_0_WDATA;\n  assign M01_AXI_wlast = m01_couplers_to_axi_interconnect_0_WLAST;\n  assign M01_AXI_wstrb[63:0] = m01_couplers_to_axi_interconnect_0_WSTRB;\n  assign M01_AXI_wvalid = m01_couplers_to_axi_interconnect_0_WVALID;\n  assign M02_AXI_araddr[63:0] = m02_couplers_to_axi_interconnect_0_ARADDR;\n  assign M02_AXI_arburst[1:0] = m02_couplers_to_axi_interconnect_0_ARBURST;\n  assign M02_AXI_arcache[3:0] = m02_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M02_AXI_arid[6:0] = m02_couplers_to_axi_interconnect_0_ARID;\n  assign M02_AXI_arlen[7:0] = m02_couplers_to_axi_interconnect_0_ARLEN;\n  assign M02_AXI_arlock[0] = m02_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M02_AXI_arprot[2:0] = m02_couplers_to_axi_interconnect_0_ARPROT;\n  assign M02_AXI_arqos[3:0] = m02_couplers_to_axi_interconnect_0_ARQOS;\n  assign M02_AXI_arregion[3:0] = m02_couplers_to_axi_interconnect_0_ARREGION;\n  assign M02_AXI_arsize[2:0] = m02_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M02_AXI_arvalid = m02_couplers_to_axi_interconnect_0_ARVALID;\n  assign M02_AXI_awaddr[63:0] = m02_couplers_to_axi_interconnect_0_AWADDR;\n  assign M02_AXI_awburst[1:0] = m02_couplers_to_axi_interconnect_0_AWBURST;\n  assign M02_AXI_awcache[3:0] = m02_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M02_AXI_awid[6:0] = m02_couplers_to_axi_interconnect_0_AWID;\n  assign M02_AXI_awlen[7:0] = m02_couplers_to_axi_interconnect_0_AWLEN;\n  assign M02_AXI_awlock[0] = m02_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M02_AXI_awprot[2:0] = m02_couplers_to_axi_interconnect_0_AWPROT;\n  assign M02_AXI_awqos[3:0] = m02_couplers_to_axi_interconnect_0_AWQOS;\n  assign M02_AXI_awregion[3:0] = m02_couplers_to_axi_interconnect_0_AWREGION;\n  assign M02_AXI_awsize[2:0] = m02_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M02_AXI_awvalid = m02_couplers_to_axi_interconnect_0_AWVALID;\n  assign M02_AXI_bready = m02_couplers_to_axi_interconnect_0_BREADY;\n  assign M02_AXI_rready = m02_couplers_to_axi_interconnect_0_RREADY;\n  assign M02_AXI_wdata[511:0] = m02_couplers_to_axi_interconnect_0_WDATA;\n  assign M02_AXI_wlast = m02_couplers_to_axi_interconnect_0_WLAST;\n  assign M02_AXI_wstrb[63:0] = m02_couplers_to_axi_interconnect_0_WSTRB;\n  assign M02_AXI_wvalid = m02_couplers_to_axi_interconnect_0_WVALID;\n  assign M03_AXI_araddr[63:0] = m03_couplers_to_axi_interconnect_0_ARADDR;\n  assign M03_AXI_arburst[1:0] = m03_couplers_to_axi_interconnect_0_ARBURST;\n  assign M03_AXI_arcache[3:0] = m03_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M03_AXI_arid[6:0] = m03_couplers_to_axi_interconnect_0_ARID;\n  assign M03_AXI_arlen[7:0] = m03_couplers_to_axi_interconnect_0_ARLEN;\n  assign M03_AXI_arlock[0] = m03_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M03_AXI_arprot[2:0] = m03_couplers_to_axi_interconnect_0_ARPROT;\n  assign M03_AXI_arqos[3:0] = m03_couplers_to_axi_interconnect_0_ARQOS;\n  assign M03_AXI_arregion[3:0] = m03_couplers_to_axi_interconnect_0_ARREGION;\n  assign M03_AXI_arsize[2:0] = m03_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M03_AXI_arvalid = m03_couplers_to_axi_interconnect_0_ARVALID;\n  assign M03_AXI_awaddr[63:0] = m03_couplers_to_axi_interconnect_0_AWADDR;\n  assign M03_AXI_awburst[1:0] = m03_couplers_to_axi_interconnect_0_AWBURST;\n  assign M03_AXI_awcache[3:0] = m03_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M03_AXI_awid[6:0] = m03_couplers_to_axi_interconnect_0_AWID;\n  assign M03_AXI_awlen[7:0] = m03_couplers_to_axi_interconnect_0_AWLEN;\n  assign M03_AXI_awlock[0] = m03_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M03_AXI_awprot[2:0] = m03_couplers_to_axi_interconnect_0_AWPROT;\n  assign M03_AXI_awqos[3:0] = m03_couplers_to_axi_interconnect_0_AWQOS;\n  assign M03_AXI_awregion[3:0] = m03_couplers_to_axi_interconnect_0_AWREGION;\n  assign M03_AXI_awsize[2:0] = m03_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M03_AXI_awvalid = m03_couplers_to_axi_interconnect_0_AWVALID;\n  assign M03_AXI_bready = m03_couplers_to_axi_interconnect_0_BREADY;\n  assign M03_AXI_rready = m03_couplers_to_axi_interconnect_0_RREADY;\n  assign M03_AXI_wdata[511:0] = m03_couplers_to_axi_interconnect_0_WDATA;\n  assign M03_AXI_wlast = m03_couplers_to_axi_interconnect_0_WLAST;\n  assign M03_AXI_wstrb[63:0] = m03_couplers_to_axi_interconnect_0_WSTRB;\n  assign M03_AXI_wvalid = m03_couplers_to_axi_interconnect_0_WVALID;\n  assign S00_AXI_arready = axi_interconnect_0_to_s00_couplers_ARREADY;\n  assign S00_AXI_awready = axi_interconnect_0_to_s00_couplers_AWREADY;\n  assign S00_AXI_bid[5:0] = axi_interconnect_0_to_s00_couplers_BID;\n  assign S00_AXI_bresp[1:0] = axi_interconnect_0_to_s00_couplers_BRESP;\n  assign S00_AXI_bvalid = axi_interconnect_0_to_s00_couplers_BVALID;\n  assign S00_AXI_rdata[511:0] = axi_interconnect_0_to_s00_couplers_RDATA;\n  assign S00_AXI_rid[5:0] = axi_interconnect_0_to_s00_couplers_RID;\n  assign S00_AXI_rlast = axi_interconnect_0_to_s00_couplers_RLAST;\n  assign S00_AXI_rresp[1:0] = axi_interconnect_0_to_s00_couplers_RRESP;\n  assign S00_AXI_rvalid = axi_interconnect_0_to_s00_couplers_RVALID;\n  assign S00_AXI_wready = axi_interconnect_0_to_s00_couplers_WREADY;\n  assign S01_AXI_arready = axi_interconnect_0_to_s01_couplers_ARREADY;\n  assign S01_AXI_awready = axi_interconnect_0_to_s01_couplers_AWREADY;\n  assign S01_AXI_bid[5:0] = axi_interconnect_0_to_s01_couplers_BID;\n  assign S01_AXI_bresp[1:0] = axi_interconnect_0_to_s01_couplers_BRESP;\n  assign S01_AXI_bvalid = axi_interconnect_0_to_s01_couplers_BVALID;\n  assign S01_AXI_rdata[511:0] = axi_interconnect_0_to_s01_couplers_RDATA;\n  assign S01_AXI_rid[5:0] = axi_interconnect_0_to_s01_couplers_RID;\n  assign S01_AXI_rlast = axi_interconnect_0_to_s01_couplers_RLAST;\n  assign S01_AXI_rresp[1:0] = axi_interconnect_0_to_s01_couplers_RRESP;\n  assign S01_AXI_rvalid = axi_interconnect_0_to_s01_couplers_RVALID;\n  assign S01_AXI_wready = axi_interconnect_0_to_s01_couplers_WREADY;\n  assign axi_interconnect_0_ACLK_net = ACLK;\n  assign axi_interconnect_0_ARESETN_net = ARESETN;\n  assign axi_interconnect_0_to_s00_couplers_ARADDR = S00_AXI_araddr[63:0];\n  assign axi_interconnect_0_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];\n  assign axi_interconnect_0_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARID = S00_AXI_arid[5:0];\n  assign axi_interconnect_0_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0];\n  assign axi_interconnect_0_to_s00_couplers_ARLOCK = S00_AXI_arlock[0];\n  assign axi_interconnect_0_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];\n  assign axi_interconnect_0_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARREGION = S00_AXI_arregion[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];\n  assign axi_interconnect_0_to_s00_couplers_ARVALID = S00_AXI_arvalid;\n  assign axi_interconnect_0_to_s00_couplers_AWADDR = S00_AXI_awaddr[63:0];\n  assign axi_interconnect_0_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];\n  assign axi_interconnect_0_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWID = S00_AXI_awid[5:0];\n  assign axi_interconnect_0_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0];\n  assign axi_interconnect_0_to_s00_couplers_AWLOCK = S00_AXI_awlock[0];\n  assign axi_interconnect_0_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];\n  assign axi_interconnect_0_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWREGION = S00_AXI_awregion[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];\n  assign axi_interconnect_0_to_s00_couplers_AWVALID = S00_AXI_awvalid;\n  assign axi_interconnect_0_to_s00_couplers_BREADY = S00_AXI_bready;\n  assign axi_interconnect_0_to_s00_couplers_RREADY = S00_AXI_rready;\n  assign axi_interconnect_0_to_s00_couplers_WDATA = S00_AXI_wdata[511:0];\n  assign axi_interconnect_0_to_s00_couplers_WLAST = S00_AXI_wlast;\n  assign axi_interconnect_0_to_s00_couplers_WSTRB = S00_AXI_wstrb[63:0];\n  assign axi_interconnect_0_to_s00_couplers_WVALID = S00_AXI_wvalid;\n  assign axi_interconnect_0_to_s01_couplers_ARADDR = S01_AXI_araddr[63:0];\n  assign axi_interconnect_0_to_s01_couplers_ARBURST = S01_AXI_arburst[1:0];\n  assign axi_interconnect_0_to_s01_couplers_ARCACHE = S01_AXI_arcache[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARID = S01_AXI_arid[5:0];\n  assign axi_interconnect_0_to_s01_couplers_ARLEN = S01_AXI_arlen[7:0];\n  assign axi_interconnect_0_to_s01_couplers_ARLOCK = S01_AXI_arlock[0];\n  assign axi_interconnect_0_to_s01_couplers_ARPROT = S01_AXI_arprot[2:0];\n  assign axi_interconnect_0_to_s01_couplers_ARQOS = S01_AXI_arqos[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARREGION = S01_AXI_arregion[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARSIZE = S01_AXI_arsize[2:0];\n  assign axi_interconnect_0_to_s01_couplers_ARVALID = S01_AXI_arvalid;\n  assign axi_interconnect_0_to_s01_couplers_AWADDR = S01_AXI_awaddr[63:0];\n  assign axi_interconnect_0_to_s01_couplers_AWBURST = S01_AXI_awburst[1:0];\n  assign axi_interconnect_0_to_s01_couplers_AWCACHE = S01_AXI_awcache[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWID = S01_AXI_awid[5:0];\n  assign axi_interconnect_0_to_s01_couplers_AWLEN = S01_AXI_awlen[7:0];\n  assign axi_interconnect_0_to_s01_couplers_AWLOCK = S01_AXI_awlock[0];\n  assign axi_interconnect_0_to_s01_couplers_AWPROT = S01_AXI_awprot[2:0];\n  assign axi_interconnect_0_to_s01_couplers_AWQOS = S01_AXI_awqos[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWREGION = S01_AXI_awregion[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWSIZE = S01_AXI_awsize[2:0];\n  assign axi_interconnect_0_to_s01_couplers_AWVALID = S01_AXI_awvalid;\n  assign axi_interconnect_0_to_s01_couplers_BREADY = S01_AXI_bready;\n  assign axi_interconnect_0_to_s01_couplers_RREADY = S01_AXI_rready;\n  assign axi_interconnect_0_to_s01_couplers_WDATA = S01_AXI_wdata[511:0];\n  assign axi_interconnect_0_to_s01_couplers_WLAST = S01_AXI_wlast;\n  assign axi_interconnect_0_to_s01_couplers_WSTRB = S01_AXI_wstrb[63:0];\n  assign axi_interconnect_0_to_s01_couplers_WVALID = S01_AXI_wvalid;\n  assign m00_couplers_to_axi_interconnect_0_ARREADY = M00_AXI_arready;\n  assign m00_couplers_to_axi_interconnect_0_AWREADY = M00_AXI_awready;\n  assign m00_couplers_to_axi_interconnect_0_BID = M00_AXI_bid[6:0];\n  assign m00_couplers_to_axi_interconnect_0_BRESP = M00_AXI_bresp[1:0];\n  assign m00_couplers_to_axi_interconnect_0_BVALID = M00_AXI_bvalid;\n  assign m00_couplers_to_axi_interconnect_0_RDATA = M00_AXI_rdata[511:0];\n  assign m00_couplers_to_axi_interconnect_0_RID = M00_AXI_rid[6:0];\n  assign m00_couplers_to_axi_interconnect_0_RLAST = M00_AXI_rlast;\n  assign m00_couplers_to_axi_interconnect_0_RRESP = M00_AXI_rresp[1:0];\n  assign m00_couplers_to_axi_interconnect_0_RVALID = M00_AXI_rvalid;\n  assign m00_couplers_to_axi_interconnect_0_WREADY = M00_AXI_wready;\n  assign m01_couplers_to_axi_interconnect_0_ARREADY = M01_AXI_arready;\n  assign m01_couplers_to_axi_interconnect_0_AWREADY = M01_AXI_awready;\n  assign m01_couplers_to_axi_interconnect_0_BID = M01_AXI_bid[6:0];\n  assign m01_couplers_to_axi_interconnect_0_BRESP = M01_AXI_bresp[1:0];\n  assign m01_couplers_to_axi_interconnect_0_BVALID = M01_AXI_bvalid;\n  assign m01_couplers_to_axi_interconnect_0_RDATA = M01_AXI_rdata[511:0];\n  assign m01_couplers_to_axi_interconnect_0_RID = M01_AXI_rid[6:0];\n  assign m01_couplers_to_axi_interconnect_0_RLAST = M01_AXI_rlast;\n  assign m01_couplers_to_axi_interconnect_0_RRESP = M01_AXI_rresp[1:0];\n  assign m01_couplers_to_axi_interconnect_0_RVALID = M01_AXI_rvalid;\n  assign m01_couplers_to_axi_interconnect_0_WREADY = M01_AXI_wready;\n  assign m02_couplers_to_axi_interconnect_0_ARREADY = M02_AXI_arready;\n  assign m02_couplers_to_axi_interconnect_0_AWREADY = M02_AXI_awready;\n  assign m02_couplers_to_axi_interconnect_0_BID = M02_AXI_bid[6:0];\n  assign m02_couplers_to_axi_interconnect_0_BRESP = M02_AXI_bresp[1:0];\n  assign m02_couplers_to_axi_interconnect_0_BVALID = M02_AXI_bvalid;\n  assign m02_couplers_to_axi_interconnect_0_RDATA = M02_AXI_rdata[511:0];\n  assign m02_couplers_to_axi_interconnect_0_RID = M02_AXI_rid[6:0];\n  assign m02_couplers_to_axi_interconnect_0_RLAST = M02_AXI_rlast;\n  assign m02_couplers_to_axi_interconnect_0_RRESP = M02_AXI_rresp[1:0];\n  assign m02_couplers_to_axi_interconnect_0_RVALID = M02_AXI_rvalid;\n  assign m02_couplers_to_axi_interconnect_0_WREADY = M02_AXI_wready;\n  assign m03_couplers_to_axi_interconnect_0_ARREADY = M03_AXI_arready;\n  assign m03_couplers_to_axi_interconnect_0_AWREADY = M03_AXI_awready;\n  assign m03_couplers_to_axi_interconnect_0_BID = M03_AXI_bid[6:0];\n  assign m03_couplers_to_axi_interconnect_0_BRESP = M03_AXI_bresp[1:0];\n  assign m03_couplers_to_axi_interconnect_0_BVALID = M03_AXI_bvalid;\n  assign m03_couplers_to_axi_interconnect_0_RDATA = M03_AXI_rdata[511:0];\n  assign m03_couplers_to_axi_interconnect_0_RID = M03_AXI_rid[6:0];\n  assign m03_couplers_to_axi_interconnect_0_RLAST = M03_AXI_rlast;\n  assign m03_couplers_to_axi_interconnect_0_RRESP = M03_AXI_rresp[1:0];\n  assign m03_couplers_to_axi_interconnect_0_RVALID = M03_AXI_rvalid;\n  assign m03_couplers_to_axi_interconnect_0_WREADY = M03_AXI_wready;\n  m00_couplers_imp_1QBJ6U2 m00_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m00_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m00_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m00_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m00_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m00_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m00_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m00_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m00_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m00_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m00_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m00_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m00_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m00_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m00_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m00_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m00_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m00_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m00_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m00_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m00_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m00_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m00_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m00_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m00_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m00_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m00_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m00_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m00_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m00_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m00_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m00_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m00_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m00_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m00_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m00_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m00_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m00_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m00_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m00_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m00_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m00_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m00_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m00_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m00_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m00_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m00_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m00_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m00_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m00_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m00_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m00_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m00_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m00_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m00_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m00_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m00_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m00_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m00_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m00_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m00_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m00_couplers_BID),\n        .S_AXI_bready(xbar_to_m00_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m00_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m00_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m00_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m00_couplers_RID),\n        .S_AXI_rlast(xbar_to_m00_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m00_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m00_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m00_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m00_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m00_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m00_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m00_couplers_WVALID));\n  m01_couplers_imp_10IMR9A m01_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m01_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m01_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m01_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m01_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m01_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m01_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m01_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m01_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m01_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m01_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m01_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m01_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m01_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m01_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m01_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m01_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m01_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m01_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m01_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m01_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m01_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m01_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m01_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m01_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m01_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m01_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m01_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m01_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m01_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m01_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m01_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m01_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m01_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m01_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m01_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m01_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m01_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m01_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m01_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m01_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m01_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m01_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m01_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m01_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m01_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m01_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m01_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m01_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m01_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m01_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m01_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m01_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m01_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m01_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m01_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m01_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m01_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m01_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m01_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m01_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m01_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m01_couplers_BID),\n        .S_AXI_bready(xbar_to_m01_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m01_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m01_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m01_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m01_couplers_RID),\n        .S_AXI_rlast(xbar_to_m01_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m01_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m01_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m01_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m01_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m01_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m01_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m01_couplers_WVALID));\n  m02_couplers_imp_APDUS2 m02_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m02_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m02_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m02_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m02_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m02_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m02_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m02_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m02_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m02_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m02_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m02_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m02_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m02_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m02_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m02_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m02_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m02_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m02_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m02_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m02_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m02_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m02_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m02_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m02_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m02_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m02_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m02_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m02_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m02_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m02_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m02_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m02_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m02_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m02_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m02_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m02_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m02_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m02_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m02_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m02_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m02_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m02_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m02_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m02_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m02_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m02_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m02_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m02_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m02_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m02_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m02_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m02_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m02_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m02_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m02_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m02_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m02_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m02_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m02_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m02_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m02_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m02_couplers_BID),\n        .S_AXI_bready(xbar_to_m02_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m02_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m02_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m02_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m02_couplers_RID),\n        .S_AXI_rlast(xbar_to_m02_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m02_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m02_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m02_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m02_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m02_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m02_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m02_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m02_couplers_WVALID));\n  m03_couplers_imp_JAYOMU m03_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m03_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m03_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m03_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m03_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m03_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m03_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m03_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m03_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m03_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m03_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m03_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m03_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m03_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m03_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m03_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m03_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m03_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m03_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m03_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m03_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m03_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m03_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m03_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m03_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m03_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m03_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m03_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m03_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m03_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m03_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m03_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m03_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m03_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m03_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m03_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m03_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m03_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m03_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m03_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m03_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m03_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m03_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m03_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m03_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m03_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m03_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m03_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m03_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m03_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m03_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m03_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m03_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m03_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m03_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m03_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m03_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m03_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m03_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m03_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m03_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m03_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m03_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m03_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m03_couplers_BID),\n        .S_AXI_bready(xbar_to_m03_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m03_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m03_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m03_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m03_couplers_RID),\n        .S_AXI_rlast(xbar_to_m03_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m03_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m03_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m03_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m03_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m03_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m03_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m03_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m03_couplers_WVALID));\n  s00_couplers_imp_QICM5G s00_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(s00_couplers_to_xbar_ARADDR),\n        .M_AXI_arburst(s00_couplers_to_xbar_ARBURST),\n        .M_AXI_arcache(s00_couplers_to_xbar_ARCACHE),\n        .M_AXI_arid(s00_couplers_to_xbar_ARID),\n        .M_AXI_arlen(s00_couplers_to_xbar_ARLEN),\n        .M_AXI_arlock(s00_couplers_to_xbar_ARLOCK),\n        .M_AXI_arprot(s00_couplers_to_xbar_ARPROT),\n        .M_AXI_arqos(s00_couplers_to_xbar_ARQOS),\n        .M_AXI_arready(s00_couplers_to_xbar_ARREADY),\n        .M_AXI_arsize(s00_couplers_to_xbar_ARSIZE),\n        .M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),\n        .M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),\n        .M_AXI_awburst(s00_couplers_to_xbar_AWBURST),\n        .M_AXI_awcache(s00_couplers_to_xbar_AWCACHE),\n        .M_AXI_awid(s00_couplers_to_xbar_AWID),\n        .M_AXI_awlen(s00_couplers_to_xbar_AWLEN),\n        .M_AXI_awlock(s00_couplers_to_xbar_AWLOCK),\n        .M_AXI_awprot(s00_couplers_to_xbar_AWPROT),\n        .M_AXI_awqos(s00_couplers_to_xbar_AWQOS),\n        .M_AXI_awready(s00_couplers_to_xbar_AWREADY),\n        .M_AXI_awsize(s00_couplers_to_xbar_AWSIZE),\n        .M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),\n        .M_AXI_bid(s00_couplers_to_xbar_BID),\n        .M_AXI_bready(s00_couplers_to_xbar_BREADY),\n        .M_AXI_bresp(s00_couplers_to_xbar_BRESP),\n        .M_AXI_bvalid(s00_couplers_to_xbar_BVALID),\n        .M_AXI_rdata(s00_couplers_to_xbar_RDATA),\n        .M_AXI_rid(s00_couplers_to_xbar_RID),\n        .M_AXI_rlast(s00_couplers_to_xbar_RLAST),\n        .M_AXI_rready(s00_couplers_to_xbar_RREADY),\n        .M_AXI_rresp(s00_couplers_to_xbar_RRESP),\n        .M_AXI_rvalid(s00_couplers_to_xbar_RVALID),\n        .M_AXI_wdata(s00_couplers_to_xbar_WDATA),\n        .M_AXI_wlast(s00_couplers_to_xbar_WLAST),\n        .M_AXI_wready(s00_couplers_to_xbar_WREADY),\n        .M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),\n        .M_AXI_wvalid(s00_couplers_to_xbar_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(axi_interconnect_0_to_s00_couplers_ARADDR),\n        .S_AXI_arburst(axi_interconnect_0_to_s00_couplers_ARBURST),\n        .S_AXI_arcache(axi_interconnect_0_to_s00_couplers_ARCACHE),\n        .S_AXI_arid(axi_interconnect_0_to_s00_couplers_ARID),\n        .S_AXI_arlen(axi_interconnect_0_to_s00_couplers_ARLEN),\n        .S_AXI_arlock(axi_interconnect_0_to_s00_couplers_ARLOCK),\n        .S_AXI_arprot(axi_interconnect_0_to_s00_couplers_ARPROT),\n        .S_AXI_arqos(axi_interconnect_0_to_s00_couplers_ARQOS),\n        .S_AXI_arready(axi_interconnect_0_to_s00_couplers_ARREADY),\n        .S_AXI_arregion(axi_interconnect_0_to_s00_couplers_ARREGION),\n        .S_AXI_arsize(axi_interconnect_0_to_s00_couplers_ARSIZE),\n        .S_AXI_arvalid(axi_interconnect_0_to_s00_couplers_ARVALID),\n        .S_AXI_awaddr(axi_interconnect_0_to_s00_couplers_AWADDR),\n        .S_AXI_awburst(axi_interconnect_0_to_s00_couplers_AWBURST),\n        .S_AXI_awcache(axi_interconnect_0_to_s00_couplers_AWCACHE),\n        .S_AXI_awid(axi_interconnect_0_to_s00_couplers_AWID),\n        .S_AXI_awlen(axi_interconnect_0_to_s00_couplers_AWLEN),\n        .S_AXI_awlock(axi_interconnect_0_to_s00_couplers_AWLOCK),\n        .S_AXI_awprot(axi_interconnect_0_to_s00_couplers_AWPROT),\n        .S_AXI_awqos(axi_interconnect_0_to_s00_couplers_AWQOS),\n        .S_AXI_awready(axi_interconnect_0_to_s00_couplers_AWREADY),\n        .S_AXI_awregion(axi_interconnect_0_to_s00_couplers_AWREGION),\n        .S_AXI_awsize(axi_interconnect_0_to_s00_couplers_AWSIZE),\n        .S_AXI_awvalid(axi_interconnect_0_to_s00_couplers_AWVALID),\n        .S_AXI_bid(axi_interconnect_0_to_s00_couplers_BID),\n        .S_AXI_bready(axi_interconnect_0_to_s00_couplers_BREADY),\n        .S_AXI_bresp(axi_interconnect_0_to_s00_couplers_BRESP),\n        .S_AXI_bvalid(axi_interconnect_0_to_s00_couplers_BVALID),\n        .S_AXI_rdata(axi_interconnect_0_to_s00_couplers_RDATA),\n        .S_AXI_rid(axi_interconnect_0_to_s00_couplers_RID),\n        .S_AXI_rlast(axi_interconnect_0_to_s00_couplers_RLAST),\n        .S_AXI_rready(axi_interconnect_0_to_s00_couplers_RREADY),\n        .S_AXI_rresp(axi_interconnect_0_to_s00_couplers_RRESP),\n        .S_AXI_rvalid(axi_interconnect_0_to_s00_couplers_RVALID),\n        .S_AXI_wdata(axi_interconnect_0_to_s00_couplers_WDATA),\n        .S_AXI_wlast(axi_interconnect_0_to_s00_couplers_WLAST),\n        .S_AXI_wready(axi_interconnect_0_to_s00_couplers_WREADY),\n        .S_AXI_wstrb(axi_interconnect_0_to_s00_couplers_WSTRB),\n        .S_AXI_wvalid(axi_interconnect_0_to_s00_couplers_WVALID));\n  s01_couplers_imp_GSTXQ8 s01_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(s01_couplers_to_xbar_ARADDR),\n        .M_AXI_arburst(s01_couplers_to_xbar_ARBURST),\n        .M_AXI_arcache(s01_couplers_to_xbar_ARCACHE),\n        .M_AXI_arid(s01_couplers_to_xbar_ARID),\n        .M_AXI_arlen(s01_couplers_to_xbar_ARLEN),\n        .M_AXI_arlock(s01_couplers_to_xbar_ARLOCK),\n        .M_AXI_arprot(s01_couplers_to_xbar_ARPROT),\n        .M_AXI_arqos(s01_couplers_to_xbar_ARQOS),\n        .M_AXI_arready(s01_couplers_to_xbar_ARREADY),\n        .M_AXI_arsize(s01_couplers_to_xbar_ARSIZE),\n        .M_AXI_arvalid(s01_couplers_to_xbar_ARVALID),\n        .M_AXI_awaddr(s01_couplers_to_xbar_AWADDR),\n        .M_AXI_awburst(s01_couplers_to_xbar_AWBURST),\n        .M_AXI_awcache(s01_couplers_to_xbar_AWCACHE),\n        .M_AXI_awid(s01_couplers_to_xbar_AWID),\n        .M_AXI_awlen(s01_couplers_to_xbar_AWLEN),\n        .M_AXI_awlock(s01_couplers_to_xbar_AWLOCK),\n        .M_AXI_awprot(s01_couplers_to_xbar_AWPROT),\n        .M_AXI_awqos(s01_couplers_to_xbar_AWQOS),\n        .M_AXI_awready(s01_couplers_to_xbar_AWREADY),\n        .M_AXI_awsize(s01_couplers_to_xbar_AWSIZE),\n        .M_AXI_awvalid(s01_couplers_to_xbar_AWVALID),\n        .M_AXI_bid(s01_couplers_to_xbar_BID),\n        .M_AXI_bready(s01_couplers_to_xbar_BREADY),\n        .M_AXI_bresp(s01_couplers_to_xbar_BRESP),\n        .M_AXI_bvalid(s01_couplers_to_xbar_BVALID),\n        .M_AXI_rdata(s01_couplers_to_xbar_RDATA),\n        .M_AXI_rid(s01_couplers_to_xbar_RID),\n        .M_AXI_rlast(s01_couplers_to_xbar_RLAST),\n        .M_AXI_rready(s01_couplers_to_xbar_RREADY),\n        .M_AXI_rresp(s01_couplers_to_xbar_RRESP),\n        .M_AXI_rvalid(s01_couplers_to_xbar_RVALID),\n        .M_AXI_wdata(s01_couplers_to_xbar_WDATA),\n        .M_AXI_wlast(s01_couplers_to_xbar_WLAST),\n        .M_AXI_wready(s01_couplers_to_xbar_WREADY),\n        .M_AXI_wstrb(s01_couplers_to_xbar_WSTRB),\n        .M_AXI_wvalid(s01_couplers_to_xbar_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(axi_interconnect_0_to_s01_couplers_ARADDR),\n        .S_AXI_arburst(axi_interconnect_0_to_s01_couplers_ARBURST),\n        .S_AXI_arcache(axi_interconnect_0_to_s01_couplers_ARCACHE),\n        .S_AXI_arid(axi_interconnect_0_to_s01_couplers_ARID),\n        .S_AXI_arlen(axi_interconnect_0_to_s01_couplers_ARLEN),\n        .S_AXI_arlock(axi_interconnect_0_to_s01_couplers_ARLOCK),\n        .S_AXI_arprot(axi_interconnect_0_to_s01_couplers_ARPROT),\n        .S_AXI_arqos(axi_interconnect_0_to_s01_couplers_ARQOS),\n        .S_AXI_arready(axi_interconnect_0_to_s01_couplers_ARREADY),\n        .S_AXI_arregion(axi_interconnect_0_to_s01_couplers_ARREGION),\n        .S_AXI_arsize(axi_interconnect_0_to_s01_couplers_ARSIZE),\n        .S_AXI_arvalid(axi_interconnect_0_to_s01_couplers_ARVALID),\n        .S_AXI_awaddr(axi_interconnect_0_to_s01_couplers_AWADDR),\n        .S_AXI_awburst(axi_interconnect_0_to_s01_couplers_AWBURST),\n        .S_AXI_awcache(axi_interconnect_0_to_s01_couplers_AWCACHE),\n        .S_AXI_awid(axi_interconnect_0_to_s01_couplers_AWID),\n        .S_AXI_awlen(axi_interconnect_0_to_s01_couplers_AWLEN),\n        .S_AXI_awlock(axi_interconnect_0_to_s01_couplers_AWLOCK),\n        .S_AXI_awprot(axi_interconnect_0_to_s01_couplers_AWPROT),\n        .S_AXI_awqos(axi_interconnect_0_to_s01_couplers_AWQOS),\n        .S_AXI_awready(axi_interconnect_0_to_s01_couplers_AWREADY),\n        .S_AXI_awregion(axi_interconnect_0_to_s01_couplers_AWREGION),\n        .S_AXI_awsize(axi_interconnect_0_to_s01_couplers_AWSIZE),\n        .S_AXI_awvalid(axi_interconnect_0_to_s01_couplers_AWVALID),\n        .S_AXI_bid(axi_interconnect_0_to_s01_couplers_BID),\n        .S_AXI_bready(axi_interconnect_0_to_s01_couplers_BREADY),\n        .S_AXI_bresp(axi_interconnect_0_to_s01_couplers_BRESP),\n        .S_AXI_bvalid(axi_interconnect_0_to_s01_couplers_BVALID),\n        .S_AXI_rdata(axi_interconnect_0_to_s01_couplers_RDATA),\n        .S_AXI_rid(axi_interconnect_0_to_s01_couplers_RID),\n        .S_AXI_rlast(axi_interconnect_0_to_s01_couplers_RLAST),\n        .S_AXI_rready(axi_interconnect_0_to_s01_couplers_RREADY),\n        .S_AXI_rresp(axi_interconnect_0_to_s01_couplers_RRESP),\n        .S_AXI_rvalid(axi_interconnect_0_to_s01_couplers_RVALID),\n        .S_AXI_wdata(axi_interconnect_0_to_s01_couplers_WDATA),\n        .S_AXI_wlast(axi_interconnect_0_to_s01_couplers_WLAST),\n        .S_AXI_wready(axi_interconnect_0_to_s01_couplers_WREADY),\n        .S_AXI_wstrb(axi_interconnect_0_to_s01_couplers_WSTRB),\n        .S_AXI_wvalid(axi_interconnect_0_to_s01_couplers_WVALID));\n  cl_axi_interconnect_xbar_0 xbar\n       (.aclk(axi_interconnect_0_ACLK_net),\n        .aresetn(axi_interconnect_0_ARESETN_net),\n        .m_axi_araddr({xbar_to_m03_couplers_ARADDR,xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),\n        .m_axi_arburst({xbar_to_m03_couplers_ARBURST,xbar_to_m02_couplers_ARBURST,xbar_to_m01_couplers_ARBURST,xbar_to_m00_couplers_ARBURST}),\n        .m_axi_arcache({xbar_to_m03_couplers_ARCACHE,xbar_to_m02_couplers_ARCACHE,xbar_to_m01_couplers_ARCACHE,xbar_to_m00_couplers_ARCACHE}),\n        .m_axi_arid({xbar_to_m03_couplers_ARID,xbar_to_m02_couplers_ARID,xbar_to_m01_couplers_ARID,xbar_to_m00_couplers_ARID}),\n        .m_axi_arlen({xbar_to_m03_couplers_ARLEN,xbar_to_m02_couplers_ARLEN,xbar_to_m01_couplers_ARLEN,xbar_to_m00_couplers_ARLEN}),\n        .m_axi_arlock({xbar_to_m03_couplers_ARLOCK,xbar_to_m02_couplers_ARLOCK,xbar_to_m01_couplers_ARLOCK,xbar_to_m00_couplers_ARLOCK}),\n        .m_axi_arprot({xbar_to_m03_couplers_ARPROT,xbar_to_m02_couplers_ARPROT,xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}),\n        .m_axi_arqos({xbar_to_m03_couplers_ARQOS,xbar_to_m02_couplers_ARQOS,xbar_to_m01_couplers_ARQOS,xbar_to_m00_couplers_ARQOS}),\n        .m_axi_arready({xbar_to_m03_couplers_ARREADY,xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),\n        .m_axi_arregion({xbar_to_m03_couplers_ARREGION,xbar_to_m02_couplers_ARREGION,xbar_to_m01_couplers_ARREGION,xbar_to_m00_couplers_ARREGION}),\n        .m_axi_arsize({xbar_to_m03_couplers_ARSIZE,xbar_to_m02_couplers_ARSIZE,xbar_to_m01_couplers_ARSIZE,xbar_to_m00_couplers_ARSIZE}),\n        .m_axi_arvalid({xbar_to_m03_couplers_ARVALID,xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),\n        .m_axi_awaddr({xbar_to_m03_couplers_AWADDR,xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),\n        .m_axi_awburst({xbar_to_m03_couplers_AWBURST,xbar_to_m02_couplers_AWBURST,xbar_to_m01_couplers_AWBURST,xbar_to_m00_couplers_AWBURST}),\n        .m_axi_awcache({xbar_to_m03_couplers_AWCACHE,xbar_to_m02_couplers_AWCACHE,xbar_to_m01_couplers_AWCACHE,xbar_to_m00_couplers_AWCACHE}),\n        .m_axi_awid({xbar_to_m03_couplers_AWID,xbar_to_m02_couplers_AWID,xbar_to_m01_couplers_AWID,xbar_to_m00_couplers_AWID}),\n        .m_axi_awlen({xbar_to_m03_couplers_AWLEN,xbar_to_m02_couplers_AWLEN,xbar_to_m01_couplers_AWLEN,xbar_to_m00_couplers_AWLEN}),\n        .m_axi_awlock({xbar_to_m03_couplers_AWLOCK,xbar_to_m02_couplers_AWLOCK,xbar_to_m01_couplers_AWLOCK,xbar_to_m00_couplers_AWLOCK}),\n        .m_axi_awprot({xbar_to_m03_couplers_AWPROT,xbar_to_m02_couplers_AWPROT,xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}),\n        .m_axi_awqos({xbar_to_m03_couplers_AWQOS,xbar_to_m02_couplers_AWQOS,xbar_to_m01_couplers_AWQOS,xbar_to_m00_couplers_AWQOS}),\n        .m_axi_awready({xbar_to_m03_couplers_AWREADY,xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),\n        .m_axi_awregion({xbar_to_m03_couplers_AWREGION,xbar_to_m02_couplers_AWREGION,xbar_to_m01_couplers_AWREGION,xbar_to_m00_couplers_AWREGION}),\n        .m_axi_awsize({xbar_to_m03_couplers_AWSIZE,xbar_to_m02_couplers_AWSIZE,xbar_to_m01_couplers_AWSIZE,xbar_to_m00_couplers_AWSIZE}),\n        .m_axi_awvalid({xbar_to_m03_couplers_AWVALID,xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),\n        .m_axi_bid({xbar_to_m03_couplers_BID,xbar_to_m02_couplers_BID,xbar_to_m01_couplers_BID,xbar_to_m00_couplers_BID}),\n        .m_axi_bready({xbar_to_m03_couplers_BREADY,xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),\n        .m_axi_bresp({xbar_to_m03_couplers_BRESP,xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),\n        .m_axi_bvalid({xbar_to_m03_couplers_BVALID,xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),\n        .m_axi_rdata({xbar_to_m03_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),\n        .m_axi_rid({xbar_to_m03_couplers_RID,xbar_to_m02_couplers_RID,xbar_to_m01_couplers_RID,xbar_to_m00_couplers_RID}),\n        .m_axi_rlast({xbar_to_m03_couplers_RLAST,xbar_to_m02_couplers_RLAST,xbar_to_m01_couplers_RLAST,xbar_to_m00_couplers_RLAST}),\n        .m_axi_rready({xbar_to_m03_couplers_RREADY,xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),\n        .m_axi_rresp({xbar_to_m03_couplers_RRESP,xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),\n        .m_axi_rvalid({xbar_to_m03_couplers_RVALID,xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),\n        .m_axi_wdata({xbar_to_m03_couplers_WDATA,xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),\n        .m_axi_wlast({xbar_to_m03_couplers_WLAST,xbar_to_m02_couplers_WLAST,xbar_to_m01_couplers_WLAST,xbar_to_m00_couplers_WLAST}),\n        .m_axi_wready({xbar_to_m03_couplers_WREADY,xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),\n        .m_axi_wstrb({xbar_to_m03_couplers_WSTRB,xbar_to_m02_couplers_WSTRB,xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),\n        .m_axi_wvalid({xbar_to_m03_couplers_WVALID,xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),\n        .s_axi_araddr({s01_couplers_to_xbar_ARADDR,s00_couplers_to_xbar_ARADDR}),\n        .s_axi_arburst({s01_couplers_to_xbar_ARBURST,s00_couplers_to_xbar_ARBURST}),\n        .s_axi_arcache({s01_couplers_to_xbar_ARCACHE,s00_couplers_to_xbar_ARCACHE}),\n        .s_axi_arid({1'b0,s01_couplers_to_xbar_ARID,1'b0,s00_couplers_to_xbar_ARID}),\n        .s_axi_arlen({s01_couplers_to_xbar_ARLEN,s00_couplers_to_xbar_ARLEN}),\n        .s_axi_arlock({s01_couplers_to_xbar_ARLOCK,s00_couplers_to_xbar_ARLOCK}),\n        .s_axi_arprot({s01_couplers_to_xbar_ARPROT,s00_couplers_to_xbar_ARPROT}),\n        .s_axi_arqos({s01_couplers_to_xbar_ARQOS,s00_couplers_to_xbar_ARQOS}),\n        .s_axi_arready({s01_couplers_to_xbar_ARREADY,s00_couplers_to_xbar_ARREADY}),\n        .s_axi_arsize({s01_couplers_to_xbar_ARSIZE,s00_couplers_to_xbar_ARSIZE}),\n        .s_axi_arvalid({s01_couplers_to_xbar_ARVALID,s00_couplers_to_xbar_ARVALID}),\n        .s_axi_awaddr({s01_couplers_to_xbar_AWADDR,s00_couplers_to_xbar_AWADDR}),\n        .s_axi_awburst({s01_couplers_to_xbar_AWBURST,s00_couplers_to_xbar_AWBURST}),\n        .s_axi_awcache({s01_couplers_to_xbar_AWCACHE,s00_couplers_to_xbar_AWCACHE}),\n        .s_axi_awid({1'b0,s01_couplers_to_xbar_AWID,1'b0,s00_couplers_to_xbar_AWID}),\n        .s_axi_awlen({s01_couplers_to_xbar_AWLEN,s00_couplers_to_xbar_AWLEN}),\n        .s_axi_awlock({s01_couplers_to_xbar_AWLOCK,s00_couplers_to_xbar_AWLOCK}),\n        .s_axi_awprot({s01_couplers_to_xbar_AWPROT,s00_couplers_to_xbar_AWPROT}),\n        .s_axi_awqos({s01_couplers_to_xbar_AWQOS,s00_couplers_to_xbar_AWQOS}),\n        .s_axi_awready({s01_couplers_to_xbar_AWREADY,s00_couplers_to_xbar_AWREADY}),\n        .s_axi_awsize({s01_couplers_to_xbar_AWSIZE,s00_couplers_to_xbar_AWSIZE}),\n        .s_axi_awvalid({s01_couplers_to_xbar_AWVALID,s00_couplers_to_xbar_AWVALID}),\n        .s_axi_bid({s01_couplers_to_xbar_BID,s00_couplers_to_xbar_BID}),\n        .s_axi_bready({s01_couplers_to_xbar_BREADY,s00_couplers_to_xbar_BREADY}),\n        .s_axi_bresp({s01_couplers_to_xbar_BRESP,s00_couplers_to_xbar_BRESP}),\n        .s_axi_bvalid({s01_couplers_to_xbar_BVALID,s00_couplers_to_xbar_BVALID}),\n        .s_axi_rdata({s01_couplers_to_xbar_RDATA,s00_couplers_to_xbar_RDATA}),\n        .s_axi_rid({s01_couplers_to_xbar_RID,s00_couplers_to_xbar_RID}),\n        .s_axi_rlast({s01_couplers_to_xbar_RLAST,s00_couplers_to_xbar_RLAST}),\n        .s_axi_rready({s01_couplers_to_xbar_RREADY,s00_couplers_to_xbar_RREADY}),\n        .s_axi_rresp({s01_couplers_to_xbar_RRESP,s00_couplers_to_xbar_RRESP}),\n        .s_axi_rvalid({s01_couplers_to_xbar_RVALID,s00_couplers_to_xbar_RVALID}),\n        .s_axi_wdata({s01_couplers_to_xbar_WDATA,s00_couplers_to_xbar_WDATA}),\n        .s_axi_wlast({s01_couplers_to_xbar_WLAST,s00_couplers_to_xbar_WLAST}),\n        .s_axi_wready({s01_couplers_to_xbar_WREADY,s00_couplers_to_xbar_WREADY}),\n        .s_axi_wstrb({s01_couplers_to_xbar_WSTRB,s00_couplers_to_xbar_WSTRB}),\n        .s_axi_wvalid({s01_couplers_to_xbar_WVALID,s00_couplers_to_xbar_WVALID}));\nendmodule\n\nmodule m00_couplers_imp_1QBJ6U2\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m00_couplers_to_m00_regslice_ARADDR;\n  wire [1:0]m00_couplers_to_m00_regslice_ARBURST;\n  wire [3:0]m00_couplers_to_m00_regslice_ARCACHE;\n  wire [6:0]m00_couplers_to_m00_regslice_ARID;\n  wire [7:0]m00_couplers_to_m00_regslice_ARLEN;\n  wire [0:0]m00_couplers_to_m00_regslice_ARLOCK;\n  wire [2:0]m00_couplers_to_m00_regslice_ARPROT;\n  wire [3:0]m00_couplers_to_m00_regslice_ARQOS;\n  wire m00_couplers_to_m00_regslice_ARREADY;\n  wire [3:0]m00_couplers_to_m00_regslice_ARREGION;\n  wire [2:0]m00_couplers_to_m00_regslice_ARSIZE;\n  wire m00_couplers_to_m00_regslice_ARVALID;\n  wire [63:0]m00_couplers_to_m00_regslice_AWADDR;\n  wire [1:0]m00_couplers_to_m00_regslice_AWBURST;\n  wire [3:0]m00_couplers_to_m00_regslice_AWCACHE;\n  wire [6:0]m00_couplers_to_m00_regslice_AWID;\n  wire [7:0]m00_couplers_to_m00_regslice_AWLEN;\n  wire [0:0]m00_couplers_to_m00_regslice_AWLOCK;\n  wire [2:0]m00_couplers_to_m00_regslice_AWPROT;\n  wire [3:0]m00_couplers_to_m00_regslice_AWQOS;\n  wire m00_couplers_to_m00_regslice_AWREADY;\n  wire [3:0]m00_couplers_to_m00_regslice_AWREGION;\n  wire [2:0]m00_couplers_to_m00_regslice_AWSIZE;\n  wire m00_couplers_to_m00_regslice_AWVALID;\n  wire [6:0]m00_couplers_to_m00_regslice_BID;\n  wire m00_couplers_to_m00_regslice_BREADY;\n  wire [1:0]m00_couplers_to_m00_regslice_BRESP;\n  wire m00_couplers_to_m00_regslice_BVALID;\n  wire [511:0]m00_couplers_to_m00_regslice_RDATA;\n  wire [6:0]m00_couplers_to_m00_regslice_RID;\n  wire m00_couplers_to_m00_regslice_RLAST;\n  wire m00_couplers_to_m00_regslice_RREADY;\n  wire [1:0]m00_couplers_to_m00_regslice_RRESP;\n  wire m00_couplers_to_m00_regslice_RVALID;\n  wire [511:0]m00_couplers_to_m00_regslice_WDATA;\n  wire m00_couplers_to_m00_regslice_WLAST;\n  wire m00_couplers_to_m00_regslice_WREADY;\n  wire [63:0]m00_couplers_to_m00_regslice_WSTRB;\n  wire m00_couplers_to_m00_regslice_WVALID;\n  wire [63:0]m00_regslice_to_m00_couplers_ARADDR;\n  wire [1:0]m00_regslice_to_m00_couplers_ARBURST;\n  wire [3:0]m00_regslice_to_m00_couplers_ARCACHE;\n  wire [6:0]m00_regslice_to_m00_couplers_ARID;\n  wire [7:0]m00_regslice_to_m00_couplers_ARLEN;\n  wire [0:0]m00_regslice_to_m00_couplers_ARLOCK;\n  wire [2:0]m00_regslice_to_m00_couplers_ARPROT;\n  wire [3:0]m00_regslice_to_m00_couplers_ARQOS;\n  wire m00_regslice_to_m00_couplers_ARREADY;\n  wire [3:0]m00_regslice_to_m00_couplers_ARREGION;\n  wire [2:0]m00_regslice_to_m00_couplers_ARSIZE;\n  wire m00_regslice_to_m00_couplers_ARVALID;\n  wire [63:0]m00_regslice_to_m00_couplers_AWADDR;\n  wire [1:0]m00_regslice_to_m00_couplers_AWBURST;\n  wire [3:0]m00_regslice_to_m00_couplers_AWCACHE;\n  wire [6:0]m00_regslice_to_m00_couplers_AWID;\n  wire [7:0]m00_regslice_to_m00_couplers_AWLEN;\n  wire [0:0]m00_regslice_to_m00_couplers_AWLOCK;\n  wire [2:0]m00_regslice_to_m00_couplers_AWPROT;\n  wire [3:0]m00_regslice_to_m00_couplers_AWQOS;\n  wire m00_regslice_to_m00_couplers_AWREADY;\n  wire [3:0]m00_regslice_to_m00_couplers_AWREGION;\n  wire [2:0]m00_regslice_to_m00_couplers_AWSIZE;\n  wire m00_regslice_to_m00_couplers_AWVALID;\n  wire [6:0]m00_regslice_to_m00_couplers_BID;\n  wire m00_regslice_to_m00_couplers_BREADY;\n  wire [1:0]m00_regslice_to_m00_couplers_BRESP;\n  wire m00_regslice_to_m00_couplers_BVALID;\n  wire [511:0]m00_regslice_to_m00_couplers_RDATA;\n  wire [6:0]m00_regslice_to_m00_couplers_RID;\n  wire m00_regslice_to_m00_couplers_RLAST;\n  wire m00_regslice_to_m00_couplers_RREADY;\n  wire [1:0]m00_regslice_to_m00_couplers_RRESP;\n  wire m00_regslice_to_m00_couplers_RVALID;\n  wire [511:0]m00_regslice_to_m00_couplers_WDATA;\n  wire m00_regslice_to_m00_couplers_WLAST;\n  wire m00_regslice_to_m00_couplers_WREADY;\n  wire [63:0]m00_regslice_to_m00_couplers_WSTRB;\n  wire m00_regslice_to_m00_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m00_regslice_to_m00_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m00_regslice_to_m00_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m00_regslice_to_m00_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m00_regslice_to_m00_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m00_regslice_to_m00_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m00_regslice_to_m00_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m00_regslice_to_m00_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m00_regslice_to_m00_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m00_regslice_to_m00_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m00_regslice_to_m00_couplers_ARSIZE;\n  assign M_AXI_arvalid = m00_regslice_to_m00_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m00_regslice_to_m00_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m00_regslice_to_m00_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m00_regslice_to_m00_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m00_regslice_to_m00_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m00_regslice_to_m00_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m00_regslice_to_m00_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m00_regslice_to_m00_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m00_regslice_to_m00_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m00_regslice_to_m00_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m00_regslice_to_m00_couplers_AWSIZE;\n  assign M_AXI_awvalid = m00_regslice_to_m00_couplers_AWVALID;\n  assign M_AXI_bready = m00_regslice_to_m00_couplers_BREADY;\n  assign M_AXI_rready = m00_regslice_to_m00_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m00_regslice_to_m00_couplers_WDATA;\n  assign M_AXI_wlast = m00_regslice_to_m00_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m00_regslice_to_m00_couplers_WSTRB;\n  assign M_AXI_wvalid = m00_regslice_to_m00_couplers_WVALID;\n  assign S_AXI_arready = m00_couplers_to_m00_regslice_ARREADY;\n  assign S_AXI_awready = m00_couplers_to_m00_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m00_couplers_to_m00_regslice_BID;\n  assign S_AXI_bresp[1:0] = m00_couplers_to_m00_regslice_BRESP;\n  assign S_AXI_bvalid = m00_couplers_to_m00_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m00_couplers_to_m00_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m00_couplers_to_m00_regslice_RID;\n  assign S_AXI_rlast = m00_couplers_to_m00_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m00_couplers_to_m00_regslice_RRESP;\n  assign S_AXI_rvalid = m00_couplers_to_m00_regslice_RVALID;\n  assign S_AXI_wready = m00_couplers_to_m00_regslice_WREADY;\n  assign m00_couplers_to_m00_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m00_couplers_to_m00_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m00_couplers_to_m00_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m00_couplers_to_m00_regslice_ARID = S_AXI_arid[6:0];\n  assign m00_couplers_to_m00_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m00_couplers_to_m00_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m00_couplers_to_m00_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m00_couplers_to_m00_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m00_couplers_to_m00_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m00_couplers_to_m00_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m00_couplers_to_m00_regslice_ARVALID = S_AXI_arvalid;\n  assign m00_couplers_to_m00_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m00_couplers_to_m00_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m00_couplers_to_m00_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m00_couplers_to_m00_regslice_AWID = S_AXI_awid[6:0];\n  assign m00_couplers_to_m00_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m00_couplers_to_m00_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m00_couplers_to_m00_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m00_couplers_to_m00_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m00_couplers_to_m00_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m00_couplers_to_m00_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m00_couplers_to_m00_regslice_AWVALID = S_AXI_awvalid;\n  assign m00_couplers_to_m00_regslice_BREADY = S_AXI_bready;\n  assign m00_couplers_to_m00_regslice_RREADY = S_AXI_rready;\n  assign m00_couplers_to_m00_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m00_couplers_to_m00_regslice_WLAST = S_AXI_wlast;\n  assign m00_couplers_to_m00_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m00_couplers_to_m00_regslice_WVALID = S_AXI_wvalid;\n  assign m00_regslice_to_m00_couplers_ARREADY = M_AXI_arready;\n  assign m00_regslice_to_m00_couplers_AWREADY = M_AXI_awready;\n  assign m00_regslice_to_m00_couplers_BID = M_AXI_bid[6:0];\n  assign m00_regslice_to_m00_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m00_regslice_to_m00_couplers_BVALID = M_AXI_bvalid;\n  assign m00_regslice_to_m00_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m00_regslice_to_m00_couplers_RID = M_AXI_rid[6:0];\n  assign m00_regslice_to_m00_couplers_RLAST = M_AXI_rlast;\n  assign m00_regslice_to_m00_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m00_regslice_to_m00_couplers_RVALID = M_AXI_rvalid;\n  assign m00_regslice_to_m00_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m00_regslice_0 m00_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m00_regslice_to_m00_couplers_ARADDR),\n        .m_axi_arburst(m00_regslice_to_m00_couplers_ARBURST),\n        .m_axi_arcache(m00_regslice_to_m00_couplers_ARCACHE),\n        .m_axi_arid(m00_regslice_to_m00_couplers_ARID),\n        .m_axi_arlen(m00_regslice_to_m00_couplers_ARLEN),\n        .m_axi_arlock(m00_regslice_to_m00_couplers_ARLOCK),\n        .m_axi_arprot(m00_regslice_to_m00_couplers_ARPROT),\n        .m_axi_arqos(m00_regslice_to_m00_couplers_ARQOS),\n        .m_axi_arready(m00_regslice_to_m00_couplers_ARREADY),\n        .m_axi_arregion(m00_regslice_to_m00_couplers_ARREGION),\n        .m_axi_arsize(m00_regslice_to_m00_couplers_ARSIZE),\n        .m_axi_arvalid(m00_regslice_to_m00_couplers_ARVALID),\n        .m_axi_awaddr(m00_regslice_to_m00_couplers_AWADDR),\n        .m_axi_awburst(m00_regslice_to_m00_couplers_AWBURST),\n        .m_axi_awcache(m00_regslice_to_m00_couplers_AWCACHE),\n        .m_axi_awid(m00_regslice_to_m00_couplers_AWID),\n        .m_axi_awlen(m00_regslice_to_m00_couplers_AWLEN),\n        .m_axi_awlock(m00_regslice_to_m00_couplers_AWLOCK),\n        .m_axi_awprot(m00_regslice_to_m00_couplers_AWPROT),\n        .m_axi_awqos(m00_regslice_to_m00_couplers_AWQOS),\n        .m_axi_awready(m00_regslice_to_m00_couplers_AWREADY),\n        .m_axi_awregion(m00_regslice_to_m00_couplers_AWREGION),\n        .m_axi_awsize(m00_regslice_to_m00_couplers_AWSIZE),\n        .m_axi_awvalid(m00_regslice_to_m00_couplers_AWVALID),\n        .m_axi_bid(m00_regslice_to_m00_couplers_BID),\n        .m_axi_bready(m00_regslice_to_m00_couplers_BREADY),\n        .m_axi_bresp(m00_regslice_to_m00_couplers_BRESP),\n        .m_axi_bvalid(m00_regslice_to_m00_couplers_BVALID),\n        .m_axi_rdata(m00_regslice_to_m00_couplers_RDATA),\n        .m_axi_rid(m00_regslice_to_m00_couplers_RID),\n        .m_axi_rlast(m00_regslice_to_m00_couplers_RLAST),\n        .m_axi_rready(m00_regslice_to_m00_couplers_RREADY),\n        .m_axi_rresp(m00_regslice_to_m00_couplers_RRESP),\n        .m_axi_rvalid(m00_regslice_to_m00_couplers_RVALID),\n        .m_axi_wdata(m00_regslice_to_m00_couplers_WDATA),\n        .m_axi_wlast(m00_regslice_to_m00_couplers_WLAST),\n        .m_axi_wready(m00_regslice_to_m00_couplers_WREADY),\n        .m_axi_wstrb(m00_regslice_to_m00_couplers_WSTRB),\n        .m_axi_wvalid(m00_regslice_to_m00_couplers_WVALID),\n        .s_axi_araddr(m00_couplers_to_m00_regslice_ARADDR),\n        .s_axi_arburst(m00_couplers_to_m00_regslice_ARBURST),\n        .s_axi_arcache(m00_couplers_to_m00_regslice_ARCACHE),\n        .s_axi_arid(m00_couplers_to_m00_regslice_ARID),\n        .s_axi_arlen(m00_couplers_to_m00_regslice_ARLEN),\n        .s_axi_arlock(m00_couplers_to_m00_regslice_ARLOCK),\n        .s_axi_arprot(m00_couplers_to_m00_regslice_ARPROT),\n        .s_axi_arqos(m00_couplers_to_m00_regslice_ARQOS),\n        .s_axi_arready(m00_couplers_to_m00_regslice_ARREADY),\n        .s_axi_arregion(m00_couplers_to_m00_regslice_ARREGION),\n        .s_axi_arsize(m00_couplers_to_m00_regslice_ARSIZE),\n        .s_axi_arvalid(m00_couplers_to_m00_regslice_ARVALID),\n        .s_axi_awaddr(m00_couplers_to_m00_regslice_AWADDR),\n        .s_axi_awburst(m00_couplers_to_m00_regslice_AWBURST),\n        .s_axi_awcache(m00_couplers_to_m00_regslice_AWCACHE),\n        .s_axi_awid(m00_couplers_to_m00_regslice_AWID),\n        .s_axi_awlen(m00_couplers_to_m00_regslice_AWLEN),\n        .s_axi_awlock(m00_couplers_to_m00_regslice_AWLOCK),\n        .s_axi_awprot(m00_couplers_to_m00_regslice_AWPROT),\n        .s_axi_awqos(m00_couplers_to_m00_regslice_AWQOS),\n        .s_axi_awready(m00_couplers_to_m00_regslice_AWREADY),\n        .s_axi_awregion(m00_couplers_to_m00_regslice_AWREGION),\n        .s_axi_awsize(m00_couplers_to_m00_regslice_AWSIZE),\n        .s_axi_awvalid(m00_couplers_to_m00_regslice_AWVALID),\n        .s_axi_bid(m00_couplers_to_m00_regslice_BID),\n        .s_axi_bready(m00_couplers_to_m00_regslice_BREADY),\n        .s_axi_bresp(m00_couplers_to_m00_regslice_BRESP),\n        .s_axi_bvalid(m00_couplers_to_m00_regslice_BVALID),\n        .s_axi_rdata(m00_couplers_to_m00_regslice_RDATA),\n        .s_axi_rid(m00_couplers_to_m00_regslice_RID),\n        .s_axi_rlast(m00_couplers_to_m00_regslice_RLAST),\n        .s_axi_rready(m00_couplers_to_m00_regslice_RREADY),\n        .s_axi_rresp(m00_couplers_to_m00_regslice_RRESP),\n        .s_axi_rvalid(m00_couplers_to_m00_regslice_RVALID),\n        .s_axi_wdata(m00_couplers_to_m00_regslice_WDATA),\n        .s_axi_wlast(m00_couplers_to_m00_regslice_WLAST),\n        .s_axi_wready(m00_couplers_to_m00_regslice_WREADY),\n        .s_axi_wstrb(m00_couplers_to_m00_regslice_WSTRB),\n        .s_axi_wvalid(m00_couplers_to_m00_regslice_WVALID));\nendmodule\n\nmodule m01_couplers_imp_10IMR9A\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m01_couplers_to_m01_regslice_ARADDR;\n  wire [1:0]m01_couplers_to_m01_regslice_ARBURST;\n  wire [3:0]m01_couplers_to_m01_regslice_ARCACHE;\n  wire [6:0]m01_couplers_to_m01_regslice_ARID;\n  wire [7:0]m01_couplers_to_m01_regslice_ARLEN;\n  wire [0:0]m01_couplers_to_m01_regslice_ARLOCK;\n  wire [2:0]m01_couplers_to_m01_regslice_ARPROT;\n  wire [3:0]m01_couplers_to_m01_regslice_ARQOS;\n  wire m01_couplers_to_m01_regslice_ARREADY;\n  wire [3:0]m01_couplers_to_m01_regslice_ARREGION;\n  wire [2:0]m01_couplers_to_m01_regslice_ARSIZE;\n  wire m01_couplers_to_m01_regslice_ARVALID;\n  wire [63:0]m01_couplers_to_m01_regslice_AWADDR;\n  wire [1:0]m01_couplers_to_m01_regslice_AWBURST;\n  wire [3:0]m01_couplers_to_m01_regslice_AWCACHE;\n  wire [6:0]m01_couplers_to_m01_regslice_AWID;\n  wire [7:0]m01_couplers_to_m01_regslice_AWLEN;\n  wire [0:0]m01_couplers_to_m01_regslice_AWLOCK;\n  wire [2:0]m01_couplers_to_m01_regslice_AWPROT;\n  wire [3:0]m01_couplers_to_m01_regslice_AWQOS;\n  wire m01_couplers_to_m01_regslice_AWREADY;\n  wire [3:0]m01_couplers_to_m01_regslice_AWREGION;\n  wire [2:0]m01_couplers_to_m01_regslice_AWSIZE;\n  wire m01_couplers_to_m01_regslice_AWVALID;\n  wire [6:0]m01_couplers_to_m01_regslice_BID;\n  wire m01_couplers_to_m01_regslice_BREADY;\n  wire [1:0]m01_couplers_to_m01_regslice_BRESP;\n  wire m01_couplers_to_m01_regslice_BVALID;\n  wire [511:0]m01_couplers_to_m01_regslice_RDATA;\n  wire [6:0]m01_couplers_to_m01_regslice_RID;\n  wire m01_couplers_to_m01_regslice_RLAST;\n  wire m01_couplers_to_m01_regslice_RREADY;\n  wire [1:0]m01_couplers_to_m01_regslice_RRESP;\n  wire m01_couplers_to_m01_regslice_RVALID;\n  wire [511:0]m01_couplers_to_m01_regslice_WDATA;\n  wire m01_couplers_to_m01_regslice_WLAST;\n  wire m01_couplers_to_m01_regslice_WREADY;\n  wire [63:0]m01_couplers_to_m01_regslice_WSTRB;\n  wire m01_couplers_to_m01_regslice_WVALID;\n  wire [63:0]m01_regslice_to_m01_couplers_ARADDR;\n  wire [1:0]m01_regslice_to_m01_couplers_ARBURST;\n  wire [3:0]m01_regslice_to_m01_couplers_ARCACHE;\n  wire [6:0]m01_regslice_to_m01_couplers_ARID;\n  wire [7:0]m01_regslice_to_m01_couplers_ARLEN;\n  wire [0:0]m01_regslice_to_m01_couplers_ARLOCK;\n  wire [2:0]m01_regslice_to_m01_couplers_ARPROT;\n  wire [3:0]m01_regslice_to_m01_couplers_ARQOS;\n  wire m01_regslice_to_m01_couplers_ARREADY;\n  wire [3:0]m01_regslice_to_m01_couplers_ARREGION;\n  wire [2:0]m01_regslice_to_m01_couplers_ARSIZE;\n  wire m01_regslice_to_m01_couplers_ARVALID;\n  wire [63:0]m01_regslice_to_m01_couplers_AWADDR;\n  wire [1:0]m01_regslice_to_m01_couplers_AWBURST;\n  wire [3:0]m01_regslice_to_m01_couplers_AWCACHE;\n  wire [6:0]m01_regslice_to_m01_couplers_AWID;\n  wire [7:0]m01_regslice_to_m01_couplers_AWLEN;\n  wire [0:0]m01_regslice_to_m01_couplers_AWLOCK;\n  wire [2:0]m01_regslice_to_m01_couplers_AWPROT;\n  wire [3:0]m01_regslice_to_m01_couplers_AWQOS;\n  wire m01_regslice_to_m01_couplers_AWREADY;\n  wire [3:0]m01_regslice_to_m01_couplers_AWREGION;\n  wire [2:0]m01_regslice_to_m01_couplers_AWSIZE;\n  wire m01_regslice_to_m01_couplers_AWVALID;\n  wire [6:0]m01_regslice_to_m01_couplers_BID;\n  wire m01_regslice_to_m01_couplers_BREADY;\n  wire [1:0]m01_regslice_to_m01_couplers_BRESP;\n  wire m01_regslice_to_m01_couplers_BVALID;\n  wire [511:0]m01_regslice_to_m01_couplers_RDATA;\n  wire [6:0]m01_regslice_to_m01_couplers_RID;\n  wire m01_regslice_to_m01_couplers_RLAST;\n  wire m01_regslice_to_m01_couplers_RREADY;\n  wire [1:0]m01_regslice_to_m01_couplers_RRESP;\n  wire m01_regslice_to_m01_couplers_RVALID;\n  wire [511:0]m01_regslice_to_m01_couplers_WDATA;\n  wire m01_regslice_to_m01_couplers_WLAST;\n  wire m01_regslice_to_m01_couplers_WREADY;\n  wire [63:0]m01_regslice_to_m01_couplers_WSTRB;\n  wire m01_regslice_to_m01_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m01_regslice_to_m01_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m01_regslice_to_m01_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m01_regslice_to_m01_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m01_regslice_to_m01_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m01_regslice_to_m01_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m01_regslice_to_m01_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m01_regslice_to_m01_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m01_regslice_to_m01_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m01_regslice_to_m01_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m01_regslice_to_m01_couplers_ARSIZE;\n  assign M_AXI_arvalid = m01_regslice_to_m01_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m01_regslice_to_m01_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m01_regslice_to_m01_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m01_regslice_to_m01_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m01_regslice_to_m01_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m01_regslice_to_m01_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m01_regslice_to_m01_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m01_regslice_to_m01_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m01_regslice_to_m01_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m01_regslice_to_m01_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m01_regslice_to_m01_couplers_AWSIZE;\n  assign M_AXI_awvalid = m01_regslice_to_m01_couplers_AWVALID;\n  assign M_AXI_bready = m01_regslice_to_m01_couplers_BREADY;\n  assign M_AXI_rready = m01_regslice_to_m01_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m01_regslice_to_m01_couplers_WDATA;\n  assign M_AXI_wlast = m01_regslice_to_m01_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m01_regslice_to_m01_couplers_WSTRB;\n  assign M_AXI_wvalid = m01_regslice_to_m01_couplers_WVALID;\n  assign S_AXI_arready = m01_couplers_to_m01_regslice_ARREADY;\n  assign S_AXI_awready = m01_couplers_to_m01_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m01_couplers_to_m01_regslice_BID;\n  assign S_AXI_bresp[1:0] = m01_couplers_to_m01_regslice_BRESP;\n  assign S_AXI_bvalid = m01_couplers_to_m01_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m01_couplers_to_m01_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m01_couplers_to_m01_regslice_RID;\n  assign S_AXI_rlast = m01_couplers_to_m01_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m01_couplers_to_m01_regslice_RRESP;\n  assign S_AXI_rvalid = m01_couplers_to_m01_regslice_RVALID;\n  assign S_AXI_wready = m01_couplers_to_m01_regslice_WREADY;\n  assign m01_couplers_to_m01_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m01_couplers_to_m01_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m01_couplers_to_m01_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m01_couplers_to_m01_regslice_ARID = S_AXI_arid[6:0];\n  assign m01_couplers_to_m01_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m01_couplers_to_m01_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m01_couplers_to_m01_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m01_couplers_to_m01_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m01_couplers_to_m01_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m01_couplers_to_m01_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m01_couplers_to_m01_regslice_ARVALID = S_AXI_arvalid;\n  assign m01_couplers_to_m01_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m01_couplers_to_m01_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m01_couplers_to_m01_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m01_couplers_to_m01_regslice_AWID = S_AXI_awid[6:0];\n  assign m01_couplers_to_m01_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m01_couplers_to_m01_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m01_couplers_to_m01_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m01_couplers_to_m01_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m01_couplers_to_m01_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m01_couplers_to_m01_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m01_couplers_to_m01_regslice_AWVALID = S_AXI_awvalid;\n  assign m01_couplers_to_m01_regslice_BREADY = S_AXI_bready;\n  assign m01_couplers_to_m01_regslice_RREADY = S_AXI_rready;\n  assign m01_couplers_to_m01_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m01_couplers_to_m01_regslice_WLAST = S_AXI_wlast;\n  assign m01_couplers_to_m01_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m01_couplers_to_m01_regslice_WVALID = S_AXI_wvalid;\n  assign m01_regslice_to_m01_couplers_ARREADY = M_AXI_arready;\n  assign m01_regslice_to_m01_couplers_AWREADY = M_AXI_awready;\n  assign m01_regslice_to_m01_couplers_BID = M_AXI_bid[6:0];\n  assign m01_regslice_to_m01_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m01_regslice_to_m01_couplers_BVALID = M_AXI_bvalid;\n  assign m01_regslice_to_m01_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m01_regslice_to_m01_couplers_RID = M_AXI_rid[6:0];\n  assign m01_regslice_to_m01_couplers_RLAST = M_AXI_rlast;\n  assign m01_regslice_to_m01_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m01_regslice_to_m01_couplers_RVALID = M_AXI_rvalid;\n  assign m01_regslice_to_m01_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m01_regslice_0 m01_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m01_regslice_to_m01_couplers_ARADDR),\n        .m_axi_arburst(m01_regslice_to_m01_couplers_ARBURST),\n        .m_axi_arcache(m01_regslice_to_m01_couplers_ARCACHE),\n        .m_axi_arid(m01_regslice_to_m01_couplers_ARID),\n        .m_axi_arlen(m01_regslice_to_m01_couplers_ARLEN),\n        .m_axi_arlock(m01_regslice_to_m01_couplers_ARLOCK),\n        .m_axi_arprot(m01_regslice_to_m01_couplers_ARPROT),\n        .m_axi_arqos(m01_regslice_to_m01_couplers_ARQOS),\n        .m_axi_arready(m01_regslice_to_m01_couplers_ARREADY),\n        .m_axi_arregion(m01_regslice_to_m01_couplers_ARREGION),\n        .m_axi_arsize(m01_regslice_to_m01_couplers_ARSIZE),\n        .m_axi_arvalid(m01_regslice_to_m01_couplers_ARVALID),\n        .m_axi_awaddr(m01_regslice_to_m01_couplers_AWADDR),\n        .m_axi_awburst(m01_regslice_to_m01_couplers_AWBURST),\n        .m_axi_awcache(m01_regslice_to_m01_couplers_AWCACHE),\n        .m_axi_awid(m01_regslice_to_m01_couplers_AWID),\n        .m_axi_awlen(m01_regslice_to_m01_couplers_AWLEN),\n        .m_axi_awlock(m01_regslice_to_m01_couplers_AWLOCK),\n        .m_axi_awprot(m01_regslice_to_m01_couplers_AWPROT),\n        .m_axi_awqos(m01_regslice_to_m01_couplers_AWQOS),\n        .m_axi_awready(m01_regslice_to_m01_couplers_AWREADY),\n        .m_axi_awregion(m01_regslice_to_m01_couplers_AWREGION),\n        .m_axi_awsize(m01_regslice_to_m01_couplers_AWSIZE),\n        .m_axi_awvalid(m01_regslice_to_m01_couplers_AWVALID),\n        .m_axi_bid(m01_regslice_to_m01_couplers_BID),\n        .m_axi_bready(m01_regslice_to_m01_couplers_BREADY),\n        .m_axi_bresp(m01_regslice_to_m01_couplers_BRESP),\n        .m_axi_bvalid(m01_regslice_to_m01_couplers_BVALID),\n        .m_axi_rdata(m01_regslice_to_m01_couplers_RDATA),\n        .m_axi_rid(m01_regslice_to_m01_couplers_RID),\n        .m_axi_rlast(m01_regslice_to_m01_couplers_RLAST),\n        .m_axi_rready(m01_regslice_to_m01_couplers_RREADY),\n        .m_axi_rresp(m01_regslice_to_m01_couplers_RRESP),\n        .m_axi_rvalid(m01_regslice_to_m01_couplers_RVALID),\n        .m_axi_wdata(m01_regslice_to_m01_couplers_WDATA),\n        .m_axi_wlast(m01_regslice_to_m01_couplers_WLAST),\n        .m_axi_wready(m01_regslice_to_m01_couplers_WREADY),\n        .m_axi_wstrb(m01_regslice_to_m01_couplers_WSTRB),\n        .m_axi_wvalid(m01_regslice_to_m01_couplers_WVALID),\n        .s_axi_araddr(m01_couplers_to_m01_regslice_ARADDR),\n        .s_axi_arburst(m01_couplers_to_m01_regslice_ARBURST),\n        .s_axi_arcache(m01_couplers_to_m01_regslice_ARCACHE),\n        .s_axi_arid(m01_couplers_to_m01_regslice_ARID),\n        .s_axi_arlen(m01_couplers_to_m01_regslice_ARLEN),\n        .s_axi_arlock(m01_couplers_to_m01_regslice_ARLOCK),\n        .s_axi_arprot(m01_couplers_to_m01_regslice_ARPROT),\n        .s_axi_arqos(m01_couplers_to_m01_regslice_ARQOS),\n        .s_axi_arready(m01_couplers_to_m01_regslice_ARREADY),\n        .s_axi_arregion(m01_couplers_to_m01_regslice_ARREGION),\n        .s_axi_arsize(m01_couplers_to_m01_regslice_ARSIZE),\n        .s_axi_arvalid(m01_couplers_to_m01_regslice_ARVALID),\n        .s_axi_awaddr(m01_couplers_to_m01_regslice_AWADDR),\n        .s_axi_awburst(m01_couplers_to_m01_regslice_AWBURST),\n        .s_axi_awcache(m01_couplers_to_m01_regslice_AWCACHE),\n        .s_axi_awid(m01_couplers_to_m01_regslice_AWID),\n        .s_axi_awlen(m01_couplers_to_m01_regslice_AWLEN),\n        .s_axi_awlock(m01_couplers_to_m01_regslice_AWLOCK),\n        .s_axi_awprot(m01_couplers_to_m01_regslice_AWPROT),\n        .s_axi_awqos(m01_couplers_to_m01_regslice_AWQOS),\n        .s_axi_awready(m01_couplers_to_m01_regslice_AWREADY),\n        .s_axi_awregion(m01_couplers_to_m01_regslice_AWREGION),\n        .s_axi_awsize(m01_couplers_to_m01_regslice_AWSIZE),\n        .s_axi_awvalid(m01_couplers_to_m01_regslice_AWVALID),\n        .s_axi_bid(m01_couplers_to_m01_regslice_BID),\n        .s_axi_bready(m01_couplers_to_m01_regslice_BREADY),\n        .s_axi_bresp(m01_couplers_to_m01_regslice_BRESP),\n        .s_axi_bvalid(m01_couplers_to_m01_regslice_BVALID),\n        .s_axi_rdata(m01_couplers_to_m01_regslice_RDATA),\n        .s_axi_rid(m01_couplers_to_m01_regslice_RID),\n        .s_axi_rlast(m01_couplers_to_m01_regslice_RLAST),\n        .s_axi_rready(m01_couplers_to_m01_regslice_RREADY),\n        .s_axi_rresp(m01_couplers_to_m01_regslice_RRESP),\n        .s_axi_rvalid(m01_couplers_to_m01_regslice_RVALID),\n        .s_axi_wdata(m01_couplers_to_m01_regslice_WDATA),\n        .s_axi_wlast(m01_couplers_to_m01_regslice_WLAST),\n        .s_axi_wready(m01_couplers_to_m01_regslice_WREADY),\n        .s_axi_wstrb(m01_couplers_to_m01_regslice_WSTRB),\n        .s_axi_wvalid(m01_couplers_to_m01_regslice_WVALID));\nendmodule\n\nmodule m02_couplers_imp_APDUS2\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m02_couplers_to_m02_regslice_ARADDR;\n  wire [1:0]m02_couplers_to_m02_regslice_ARBURST;\n  wire [3:0]m02_couplers_to_m02_regslice_ARCACHE;\n  wire [6:0]m02_couplers_to_m02_regslice_ARID;\n  wire [7:0]m02_couplers_to_m02_regslice_ARLEN;\n  wire [0:0]m02_couplers_to_m02_regslice_ARLOCK;\n  wire [2:0]m02_couplers_to_m02_regslice_ARPROT;\n  wire [3:0]m02_couplers_to_m02_regslice_ARQOS;\n  wire m02_couplers_to_m02_regslice_ARREADY;\n  wire [3:0]m02_couplers_to_m02_regslice_ARREGION;\n  wire [2:0]m02_couplers_to_m02_regslice_ARSIZE;\n  wire m02_couplers_to_m02_regslice_ARVALID;\n  wire [63:0]m02_couplers_to_m02_regslice_AWADDR;\n  wire [1:0]m02_couplers_to_m02_regslice_AWBURST;\n  wire [3:0]m02_couplers_to_m02_regslice_AWCACHE;\n  wire [6:0]m02_couplers_to_m02_regslice_AWID;\n  wire [7:0]m02_couplers_to_m02_regslice_AWLEN;\n  wire [0:0]m02_couplers_to_m02_regslice_AWLOCK;\n  wire [2:0]m02_couplers_to_m02_regslice_AWPROT;\n  wire [3:0]m02_couplers_to_m02_regslice_AWQOS;\n  wire m02_couplers_to_m02_regslice_AWREADY;\n  wire [3:0]m02_couplers_to_m02_regslice_AWREGION;\n  wire [2:0]m02_couplers_to_m02_regslice_AWSIZE;\n  wire m02_couplers_to_m02_regslice_AWVALID;\n  wire [6:0]m02_couplers_to_m02_regslice_BID;\n  wire m02_couplers_to_m02_regslice_BREADY;\n  wire [1:0]m02_couplers_to_m02_regslice_BRESP;\n  wire m02_couplers_to_m02_regslice_BVALID;\n  wire [511:0]m02_couplers_to_m02_regslice_RDATA;\n  wire [6:0]m02_couplers_to_m02_regslice_RID;\n  wire m02_couplers_to_m02_regslice_RLAST;\n  wire m02_couplers_to_m02_regslice_RREADY;\n  wire [1:0]m02_couplers_to_m02_regslice_RRESP;\n  wire m02_couplers_to_m02_regslice_RVALID;\n  wire [511:0]m02_couplers_to_m02_regslice_WDATA;\n  wire m02_couplers_to_m02_regslice_WLAST;\n  wire m02_couplers_to_m02_regslice_WREADY;\n  wire [63:0]m02_couplers_to_m02_regslice_WSTRB;\n  wire m02_couplers_to_m02_regslice_WVALID;\n  wire [63:0]m02_regslice_to_m02_couplers_ARADDR;\n  wire [1:0]m02_regslice_to_m02_couplers_ARBURST;\n  wire [3:0]m02_regslice_to_m02_couplers_ARCACHE;\n  wire [6:0]m02_regslice_to_m02_couplers_ARID;\n  wire [7:0]m02_regslice_to_m02_couplers_ARLEN;\n  wire [0:0]m02_regslice_to_m02_couplers_ARLOCK;\n  wire [2:0]m02_regslice_to_m02_couplers_ARPROT;\n  wire [3:0]m02_regslice_to_m02_couplers_ARQOS;\n  wire m02_regslice_to_m02_couplers_ARREADY;\n  wire [3:0]m02_regslice_to_m02_couplers_ARREGION;\n  wire [2:0]m02_regslice_to_m02_couplers_ARSIZE;\n  wire m02_regslice_to_m02_couplers_ARVALID;\n  wire [63:0]m02_regslice_to_m02_couplers_AWADDR;\n  wire [1:0]m02_regslice_to_m02_couplers_AWBURST;\n  wire [3:0]m02_regslice_to_m02_couplers_AWCACHE;\n  wire [6:0]m02_regslice_to_m02_couplers_AWID;\n  wire [7:0]m02_regslice_to_m02_couplers_AWLEN;\n  wire [0:0]m02_regslice_to_m02_couplers_AWLOCK;\n  wire [2:0]m02_regslice_to_m02_couplers_AWPROT;\n  wire [3:0]m02_regslice_to_m02_couplers_AWQOS;\n  wire m02_regslice_to_m02_couplers_AWREADY;\n  wire [3:0]m02_regslice_to_m02_couplers_AWREGION;\n  wire [2:0]m02_regslice_to_m02_couplers_AWSIZE;\n  wire m02_regslice_to_m02_couplers_AWVALID;\n  wire [6:0]m02_regslice_to_m02_couplers_BID;\n  wire m02_regslice_to_m02_couplers_BREADY;\n  wire [1:0]m02_regslice_to_m02_couplers_BRESP;\n  wire m02_regslice_to_m02_couplers_BVALID;\n  wire [511:0]m02_regslice_to_m02_couplers_RDATA;\n  wire [6:0]m02_regslice_to_m02_couplers_RID;\n  wire m02_regslice_to_m02_couplers_RLAST;\n  wire m02_regslice_to_m02_couplers_RREADY;\n  wire [1:0]m02_regslice_to_m02_couplers_RRESP;\n  wire m02_regslice_to_m02_couplers_RVALID;\n  wire [511:0]m02_regslice_to_m02_couplers_WDATA;\n  wire m02_regslice_to_m02_couplers_WLAST;\n  wire m02_regslice_to_m02_couplers_WREADY;\n  wire [63:0]m02_regslice_to_m02_couplers_WSTRB;\n  wire m02_regslice_to_m02_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m02_regslice_to_m02_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m02_regslice_to_m02_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m02_regslice_to_m02_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m02_regslice_to_m02_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m02_regslice_to_m02_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m02_regslice_to_m02_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m02_regslice_to_m02_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m02_regslice_to_m02_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m02_regslice_to_m02_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m02_regslice_to_m02_couplers_ARSIZE;\n  assign M_AXI_arvalid = m02_regslice_to_m02_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m02_regslice_to_m02_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m02_regslice_to_m02_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m02_regslice_to_m02_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m02_regslice_to_m02_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m02_regslice_to_m02_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m02_regslice_to_m02_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m02_regslice_to_m02_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m02_regslice_to_m02_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m02_regslice_to_m02_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m02_regslice_to_m02_couplers_AWSIZE;\n  assign M_AXI_awvalid = m02_regslice_to_m02_couplers_AWVALID;\n  assign M_AXI_bready = m02_regslice_to_m02_couplers_BREADY;\n  assign M_AXI_rready = m02_regslice_to_m02_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m02_regslice_to_m02_couplers_WDATA;\n  assign M_AXI_wlast = m02_regslice_to_m02_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m02_regslice_to_m02_couplers_WSTRB;\n  assign M_AXI_wvalid = m02_regslice_to_m02_couplers_WVALID;\n  assign S_AXI_arready = m02_couplers_to_m02_regslice_ARREADY;\n  assign S_AXI_awready = m02_couplers_to_m02_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m02_couplers_to_m02_regslice_BID;\n  assign S_AXI_bresp[1:0] = m02_couplers_to_m02_regslice_BRESP;\n  assign S_AXI_bvalid = m02_couplers_to_m02_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m02_couplers_to_m02_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m02_couplers_to_m02_regslice_RID;\n  assign S_AXI_rlast = m02_couplers_to_m02_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m02_couplers_to_m02_regslice_RRESP;\n  assign S_AXI_rvalid = m02_couplers_to_m02_regslice_RVALID;\n  assign S_AXI_wready = m02_couplers_to_m02_regslice_WREADY;\n  assign m02_couplers_to_m02_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m02_couplers_to_m02_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m02_couplers_to_m02_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m02_couplers_to_m02_regslice_ARID = S_AXI_arid[6:0];\n  assign m02_couplers_to_m02_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m02_couplers_to_m02_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m02_couplers_to_m02_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m02_couplers_to_m02_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m02_couplers_to_m02_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m02_couplers_to_m02_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m02_couplers_to_m02_regslice_ARVALID = S_AXI_arvalid;\n  assign m02_couplers_to_m02_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m02_couplers_to_m02_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m02_couplers_to_m02_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m02_couplers_to_m02_regslice_AWID = S_AXI_awid[6:0];\n  assign m02_couplers_to_m02_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m02_couplers_to_m02_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m02_couplers_to_m02_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m02_couplers_to_m02_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m02_couplers_to_m02_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m02_couplers_to_m02_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m02_couplers_to_m02_regslice_AWVALID = S_AXI_awvalid;\n  assign m02_couplers_to_m02_regslice_BREADY = S_AXI_bready;\n  assign m02_couplers_to_m02_regslice_RREADY = S_AXI_rready;\n  assign m02_couplers_to_m02_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m02_couplers_to_m02_regslice_WLAST = S_AXI_wlast;\n  assign m02_couplers_to_m02_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m02_couplers_to_m02_regslice_WVALID = S_AXI_wvalid;\n  assign m02_regslice_to_m02_couplers_ARREADY = M_AXI_arready;\n  assign m02_regslice_to_m02_couplers_AWREADY = M_AXI_awready;\n  assign m02_regslice_to_m02_couplers_BID = M_AXI_bid[6:0];\n  assign m02_regslice_to_m02_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m02_regslice_to_m02_couplers_BVALID = M_AXI_bvalid;\n  assign m02_regslice_to_m02_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m02_regslice_to_m02_couplers_RID = M_AXI_rid[6:0];\n  assign m02_regslice_to_m02_couplers_RLAST = M_AXI_rlast;\n  assign m02_regslice_to_m02_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m02_regslice_to_m02_couplers_RVALID = M_AXI_rvalid;\n  assign m02_regslice_to_m02_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m02_regslice_0 m02_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m02_regslice_to_m02_couplers_ARADDR),\n        .m_axi_arburst(m02_regslice_to_m02_couplers_ARBURST),\n        .m_axi_arcache(m02_regslice_to_m02_couplers_ARCACHE),\n        .m_axi_arid(m02_regslice_to_m02_couplers_ARID),\n        .m_axi_arlen(m02_regslice_to_m02_couplers_ARLEN),\n        .m_axi_arlock(m02_regslice_to_m02_couplers_ARLOCK),\n        .m_axi_arprot(m02_regslice_to_m02_couplers_ARPROT),\n        .m_axi_arqos(m02_regslice_to_m02_couplers_ARQOS),\n        .m_axi_arready(m02_regslice_to_m02_couplers_ARREADY),\n        .m_axi_arregion(m02_regslice_to_m02_couplers_ARREGION),\n        .m_axi_arsize(m02_regslice_to_m02_couplers_ARSIZE),\n        .m_axi_arvalid(m02_regslice_to_m02_couplers_ARVALID),\n        .m_axi_awaddr(m02_regslice_to_m02_couplers_AWADDR),\n        .m_axi_awburst(m02_regslice_to_m02_couplers_AWBURST),\n        .m_axi_awcache(m02_regslice_to_m02_couplers_AWCACHE),\n        .m_axi_awid(m02_regslice_to_m02_couplers_AWID),\n        .m_axi_awlen(m02_regslice_to_m02_couplers_AWLEN),\n        .m_axi_awlock(m02_regslice_to_m02_couplers_AWLOCK),\n        .m_axi_awprot(m02_regslice_to_m02_couplers_AWPROT),\n        .m_axi_awqos(m02_regslice_to_m02_couplers_AWQOS),\n        .m_axi_awready(m02_regslice_to_m02_couplers_AWREADY),\n        .m_axi_awregion(m02_regslice_to_m02_couplers_AWREGION),\n        .m_axi_awsize(m02_regslice_to_m02_couplers_AWSIZE),\n        .m_axi_awvalid(m02_regslice_to_m02_couplers_AWVALID),\n        .m_axi_bid(m02_regslice_to_m02_couplers_BID),\n        .m_axi_bready(m02_regslice_to_m02_couplers_BREADY),\n        .m_axi_bresp(m02_regslice_to_m02_couplers_BRESP),\n        .m_axi_bvalid(m02_regslice_to_m02_couplers_BVALID),\n        .m_axi_rdata(m02_regslice_to_m02_couplers_RDATA),\n        .m_axi_rid(m02_regslice_to_m02_couplers_RID),\n        .m_axi_rlast(m02_regslice_to_m02_couplers_RLAST),\n        .m_axi_rready(m02_regslice_to_m02_couplers_RREADY),\n        .m_axi_rresp(m02_regslice_to_m02_couplers_RRESP),\n        .m_axi_rvalid(m02_regslice_to_m02_couplers_RVALID),\n        .m_axi_wdata(m02_regslice_to_m02_couplers_WDATA),\n        .m_axi_wlast(m02_regslice_to_m02_couplers_WLAST),\n        .m_axi_wready(m02_regslice_to_m02_couplers_WREADY),\n        .m_axi_wstrb(m02_regslice_to_m02_couplers_WSTRB),\n        .m_axi_wvalid(m02_regslice_to_m02_couplers_WVALID),\n        .s_axi_araddr(m02_couplers_to_m02_regslice_ARADDR),\n        .s_axi_arburst(m02_couplers_to_m02_regslice_ARBURST),\n        .s_axi_arcache(m02_couplers_to_m02_regslice_ARCACHE),\n        .s_axi_arid(m02_couplers_to_m02_regslice_ARID),\n        .s_axi_arlen(m02_couplers_to_m02_regslice_ARLEN),\n        .s_axi_arlock(m02_couplers_to_m02_regslice_ARLOCK),\n        .s_axi_arprot(m02_couplers_to_m02_regslice_ARPROT),\n        .s_axi_arqos(m02_couplers_to_m02_regslice_ARQOS),\n        .s_axi_arready(m02_couplers_to_m02_regslice_ARREADY),\n        .s_axi_arregion(m02_couplers_to_m02_regslice_ARREGION),\n        .s_axi_arsize(m02_couplers_to_m02_regslice_ARSIZE),\n        .s_axi_arvalid(m02_couplers_to_m02_regslice_ARVALID),\n        .s_axi_awaddr(m02_couplers_to_m02_regslice_AWADDR),\n        .s_axi_awburst(m02_couplers_to_m02_regslice_AWBURST),\n        .s_axi_awcache(m02_couplers_to_m02_regslice_AWCACHE),\n        .s_axi_awid(m02_couplers_to_m02_regslice_AWID),\n        .s_axi_awlen(m02_couplers_to_m02_regslice_AWLEN),\n        .s_axi_awlock(m02_couplers_to_m02_regslice_AWLOCK),\n        .s_axi_awprot(m02_couplers_to_m02_regslice_AWPROT),\n        .s_axi_awqos(m02_couplers_to_m02_regslice_AWQOS),\n        .s_axi_awready(m02_couplers_to_m02_regslice_AWREADY),\n        .s_axi_awregion(m02_couplers_to_m02_regslice_AWREGION),\n        .s_axi_awsize(m02_couplers_to_m02_regslice_AWSIZE),\n        .s_axi_awvalid(m02_couplers_to_m02_regslice_AWVALID),\n        .s_axi_bid(m02_couplers_to_m02_regslice_BID),\n        .s_axi_bready(m02_couplers_to_m02_regslice_BREADY),\n        .s_axi_bresp(m02_couplers_to_m02_regslice_BRESP),\n        .s_axi_bvalid(m02_couplers_to_m02_regslice_BVALID),\n        .s_axi_rdata(m02_couplers_to_m02_regslice_RDATA),\n        .s_axi_rid(m02_couplers_to_m02_regslice_RID),\n        .s_axi_rlast(m02_couplers_to_m02_regslice_RLAST),\n        .s_axi_rready(m02_couplers_to_m02_regslice_RREADY),\n        .s_axi_rresp(m02_couplers_to_m02_regslice_RRESP),\n        .s_axi_rvalid(m02_couplers_to_m02_regslice_RVALID),\n        .s_axi_wdata(m02_couplers_to_m02_regslice_WDATA),\n        .s_axi_wlast(m02_couplers_to_m02_regslice_WLAST),\n        .s_axi_wready(m02_couplers_to_m02_regslice_WREADY),\n        .s_axi_wstrb(m02_couplers_to_m02_regslice_WSTRB),\n        .s_axi_wvalid(m02_couplers_to_m02_regslice_WVALID));\nendmodule\n\nmodule m03_couplers_imp_JAYOMU\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m03_couplers_to_m03_regslice_ARADDR;\n  wire [1:0]m03_couplers_to_m03_regslice_ARBURST;\n  wire [3:0]m03_couplers_to_m03_regslice_ARCACHE;\n  wire [6:0]m03_couplers_to_m03_regslice_ARID;\n  wire [7:0]m03_couplers_to_m03_regslice_ARLEN;\n  wire [0:0]m03_couplers_to_m03_regslice_ARLOCK;\n  wire [2:0]m03_couplers_to_m03_regslice_ARPROT;\n  wire [3:0]m03_couplers_to_m03_regslice_ARQOS;\n  wire m03_couplers_to_m03_regslice_ARREADY;\n  wire [3:0]m03_couplers_to_m03_regslice_ARREGION;\n  wire [2:0]m03_couplers_to_m03_regslice_ARSIZE;\n  wire m03_couplers_to_m03_regslice_ARVALID;\n  wire [63:0]m03_couplers_to_m03_regslice_AWADDR;\n  wire [1:0]m03_couplers_to_m03_regslice_AWBURST;\n  wire [3:0]m03_couplers_to_m03_regslice_AWCACHE;\n  wire [6:0]m03_couplers_to_m03_regslice_AWID;\n  wire [7:0]m03_couplers_to_m03_regslice_AWLEN;\n  wire [0:0]m03_couplers_to_m03_regslice_AWLOCK;\n  wire [2:0]m03_couplers_to_m03_regslice_AWPROT;\n  wire [3:0]m03_couplers_to_m03_regslice_AWQOS;\n  wire m03_couplers_to_m03_regslice_AWREADY;\n  wire [3:0]m03_couplers_to_m03_regslice_AWREGION;\n  wire [2:0]m03_couplers_to_m03_regslice_AWSIZE;\n  wire m03_couplers_to_m03_regslice_AWVALID;\n  wire [6:0]m03_couplers_to_m03_regslice_BID;\n  wire m03_couplers_to_m03_regslice_BREADY;\n  wire [1:0]m03_couplers_to_m03_regslice_BRESP;\n  wire m03_couplers_to_m03_regslice_BVALID;\n  wire [511:0]m03_couplers_to_m03_regslice_RDATA;\n  wire [6:0]m03_couplers_to_m03_regslice_RID;\n  wire m03_couplers_to_m03_regslice_RLAST;\n  wire m03_couplers_to_m03_regslice_RREADY;\n  wire [1:0]m03_couplers_to_m03_regslice_RRESP;\n  wire m03_couplers_to_m03_regslice_RVALID;\n  wire [511:0]m03_couplers_to_m03_regslice_WDATA;\n  wire m03_couplers_to_m03_regslice_WLAST;\n  wire m03_couplers_to_m03_regslice_WREADY;\n  wire [63:0]m03_couplers_to_m03_regslice_WSTRB;\n  wire m03_couplers_to_m03_regslice_WVALID;\n  wire [63:0]m03_regslice_to_m03_couplers_ARADDR;\n  wire [1:0]m03_regslice_to_m03_couplers_ARBURST;\n  wire [3:0]m03_regslice_to_m03_couplers_ARCACHE;\n  wire [6:0]m03_regslice_to_m03_couplers_ARID;\n  wire [7:0]m03_regslice_to_m03_couplers_ARLEN;\n  wire [0:0]m03_regslice_to_m03_couplers_ARLOCK;\n  wire [2:0]m03_regslice_to_m03_couplers_ARPROT;\n  wire [3:0]m03_regslice_to_m03_couplers_ARQOS;\n  wire m03_regslice_to_m03_couplers_ARREADY;\n  wire [3:0]m03_regslice_to_m03_couplers_ARREGION;\n  wire [2:0]m03_regslice_to_m03_couplers_ARSIZE;\n  wire m03_regslice_to_m03_couplers_ARVALID;\n  wire [63:0]m03_regslice_to_m03_couplers_AWADDR;\n  wire [1:0]m03_regslice_to_m03_couplers_AWBURST;\n  wire [3:0]m03_regslice_to_m03_couplers_AWCACHE;\n  wire [6:0]m03_regslice_to_m03_couplers_AWID;\n  wire [7:0]m03_regslice_to_m03_couplers_AWLEN;\n  wire [0:0]m03_regslice_to_m03_couplers_AWLOCK;\n  wire [2:0]m03_regslice_to_m03_couplers_AWPROT;\n  wire [3:0]m03_regslice_to_m03_couplers_AWQOS;\n  wire m03_regslice_to_m03_couplers_AWREADY;\n  wire [3:0]m03_regslice_to_m03_couplers_AWREGION;\n  wire [2:0]m03_regslice_to_m03_couplers_AWSIZE;\n  wire m03_regslice_to_m03_couplers_AWVALID;\n  wire [6:0]m03_regslice_to_m03_couplers_BID;\n  wire m03_regslice_to_m03_couplers_BREADY;\n  wire [1:0]m03_regslice_to_m03_couplers_BRESP;\n  wire m03_regslice_to_m03_couplers_BVALID;\n  wire [511:0]m03_regslice_to_m03_couplers_RDATA;\n  wire [6:0]m03_regslice_to_m03_couplers_RID;\n  wire m03_regslice_to_m03_couplers_RLAST;\n  wire m03_regslice_to_m03_couplers_RREADY;\n  wire [1:0]m03_regslice_to_m03_couplers_RRESP;\n  wire m03_regslice_to_m03_couplers_RVALID;\n  wire [511:0]m03_regslice_to_m03_couplers_WDATA;\n  wire m03_regslice_to_m03_couplers_WLAST;\n  wire m03_regslice_to_m03_couplers_WREADY;\n  wire [63:0]m03_regslice_to_m03_couplers_WSTRB;\n  wire m03_regslice_to_m03_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m03_regslice_to_m03_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m03_regslice_to_m03_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m03_regslice_to_m03_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m03_regslice_to_m03_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m03_regslice_to_m03_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m03_regslice_to_m03_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m03_regslice_to_m03_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m03_regslice_to_m03_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m03_regslice_to_m03_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m03_regslice_to_m03_couplers_ARSIZE;\n  assign M_AXI_arvalid = m03_regslice_to_m03_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m03_regslice_to_m03_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m03_regslice_to_m03_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m03_regslice_to_m03_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m03_regslice_to_m03_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m03_regslice_to_m03_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m03_regslice_to_m03_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m03_regslice_to_m03_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m03_regslice_to_m03_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m03_regslice_to_m03_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m03_regslice_to_m03_couplers_AWSIZE;\n  assign M_AXI_awvalid = m03_regslice_to_m03_couplers_AWVALID;\n  assign M_AXI_bready = m03_regslice_to_m03_couplers_BREADY;\n  assign M_AXI_rready = m03_regslice_to_m03_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m03_regslice_to_m03_couplers_WDATA;\n  assign M_AXI_wlast = m03_regslice_to_m03_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m03_regslice_to_m03_couplers_WSTRB;\n  assign M_AXI_wvalid = m03_regslice_to_m03_couplers_WVALID;\n  assign S_AXI_arready = m03_couplers_to_m03_regslice_ARREADY;\n  assign S_AXI_awready = m03_couplers_to_m03_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m03_couplers_to_m03_regslice_BID;\n  assign S_AXI_bresp[1:0] = m03_couplers_to_m03_regslice_BRESP;\n  assign S_AXI_bvalid = m03_couplers_to_m03_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m03_couplers_to_m03_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m03_couplers_to_m03_regslice_RID;\n  assign S_AXI_rlast = m03_couplers_to_m03_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m03_couplers_to_m03_regslice_RRESP;\n  assign S_AXI_rvalid = m03_couplers_to_m03_regslice_RVALID;\n  assign S_AXI_wready = m03_couplers_to_m03_regslice_WREADY;\n  assign m03_couplers_to_m03_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m03_couplers_to_m03_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m03_couplers_to_m03_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m03_couplers_to_m03_regslice_ARID = S_AXI_arid[6:0];\n  assign m03_couplers_to_m03_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m03_couplers_to_m03_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m03_couplers_to_m03_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m03_couplers_to_m03_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m03_couplers_to_m03_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m03_couplers_to_m03_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m03_couplers_to_m03_regslice_ARVALID = S_AXI_arvalid;\n  assign m03_couplers_to_m03_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m03_couplers_to_m03_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m03_couplers_to_m03_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m03_couplers_to_m03_regslice_AWID = S_AXI_awid[6:0];\n  assign m03_couplers_to_m03_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m03_couplers_to_m03_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m03_couplers_to_m03_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m03_couplers_to_m03_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m03_couplers_to_m03_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m03_couplers_to_m03_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m03_couplers_to_m03_regslice_AWVALID = S_AXI_awvalid;\n  assign m03_couplers_to_m03_regslice_BREADY = S_AXI_bready;\n  assign m03_couplers_to_m03_regslice_RREADY = S_AXI_rready;\n  assign m03_couplers_to_m03_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m03_couplers_to_m03_regslice_WLAST = S_AXI_wlast;\n  assign m03_couplers_to_m03_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m03_couplers_to_m03_regslice_WVALID = S_AXI_wvalid;\n  assign m03_regslice_to_m03_couplers_ARREADY = M_AXI_arready;\n  assign m03_regslice_to_m03_couplers_AWREADY = M_AXI_awready;\n  assign m03_regslice_to_m03_couplers_BID = M_AXI_bid[6:0];\n  assign m03_regslice_to_m03_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m03_regslice_to_m03_couplers_BVALID = M_AXI_bvalid;\n  assign m03_regslice_to_m03_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m03_regslice_to_m03_couplers_RID = M_AXI_rid[6:0];\n  assign m03_regslice_to_m03_couplers_RLAST = M_AXI_rlast;\n  assign m03_regslice_to_m03_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m03_regslice_to_m03_couplers_RVALID = M_AXI_rvalid;\n  assign m03_regslice_to_m03_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m03_regslice_0 m03_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m03_regslice_to_m03_couplers_ARADDR),\n        .m_axi_arburst(m03_regslice_to_m03_couplers_ARBURST),\n        .m_axi_arcache(m03_regslice_to_m03_couplers_ARCACHE),\n        .m_axi_arid(m03_regslice_to_m03_couplers_ARID),\n        .m_axi_arlen(m03_regslice_to_m03_couplers_ARLEN),\n        .m_axi_arlock(m03_regslice_to_m03_couplers_ARLOCK),\n        .m_axi_arprot(m03_regslice_to_m03_couplers_ARPROT),\n        .m_axi_arqos(m03_regslice_to_m03_couplers_ARQOS),\n        .m_axi_arready(m03_regslice_to_m03_couplers_ARREADY),\n        .m_axi_arregion(m03_regslice_to_m03_couplers_ARREGION),\n        .m_axi_arsize(m03_regslice_to_m03_couplers_ARSIZE),\n        .m_axi_arvalid(m03_regslice_to_m03_couplers_ARVALID),\n        .m_axi_awaddr(m03_regslice_to_m03_couplers_AWADDR),\n        .m_axi_awburst(m03_regslice_to_m03_couplers_AWBURST),\n        .m_axi_awcache(m03_regslice_to_m03_couplers_AWCACHE),\n        .m_axi_awid(m03_regslice_to_m03_couplers_AWID),\n        .m_axi_awlen(m03_regslice_to_m03_couplers_AWLEN),\n        .m_axi_awlock(m03_regslice_to_m03_couplers_AWLOCK),\n        .m_axi_awprot(m03_regslice_to_m03_couplers_AWPROT),\n        .m_axi_awqos(m03_regslice_to_m03_couplers_AWQOS),\n        .m_axi_awready(m03_regslice_to_m03_couplers_AWREADY),\n        .m_axi_awregion(m03_regslice_to_m03_couplers_AWREGION),\n        .m_axi_awsize(m03_regslice_to_m03_couplers_AWSIZE),\n        .m_axi_awvalid(m03_regslice_to_m03_couplers_AWVALID),\n        .m_axi_bid(m03_regslice_to_m03_couplers_BID),\n        .m_axi_bready(m03_regslice_to_m03_couplers_BREADY),\n        .m_axi_bresp(m03_regslice_to_m03_couplers_BRESP),\n        .m_axi_bvalid(m03_regslice_to_m03_couplers_BVALID),\n        .m_axi_rdata(m03_regslice_to_m03_couplers_RDATA),\n        .m_axi_rid(m03_regslice_to_m03_couplers_RID),\n        .m_axi_rlast(m03_regslice_to_m03_couplers_RLAST),\n        .m_axi_rready(m03_regslice_to_m03_couplers_RREADY),\n        .m_axi_rresp(m03_regslice_to_m03_couplers_RRESP),\n        .m_axi_rvalid(m03_regslice_to_m03_couplers_RVALID),\n        .m_axi_wdata(m03_regslice_to_m03_couplers_WDATA),\n        .m_axi_wlast(m03_regslice_to_m03_couplers_WLAST),\n        .m_axi_wready(m03_regslice_to_m03_couplers_WREADY),\n        .m_axi_wstrb(m03_regslice_to_m03_couplers_WSTRB),\n        .m_axi_wvalid(m03_regslice_to_m03_couplers_WVALID),\n        .s_axi_araddr(m03_couplers_to_m03_regslice_ARADDR),\n        .s_axi_arburst(m03_couplers_to_m03_regslice_ARBURST),\n        .s_axi_arcache(m03_couplers_to_m03_regslice_ARCACHE),\n        .s_axi_arid(m03_couplers_to_m03_regslice_ARID),\n        .s_axi_arlen(m03_couplers_to_m03_regslice_ARLEN),\n        .s_axi_arlock(m03_couplers_to_m03_regslice_ARLOCK),\n        .s_axi_arprot(m03_couplers_to_m03_regslice_ARPROT),\n        .s_axi_arqos(m03_couplers_to_m03_regslice_ARQOS),\n        .s_axi_arready(m03_couplers_to_m03_regslice_ARREADY),\n        .s_axi_arregion(m03_couplers_to_m03_regslice_ARREGION),\n        .s_axi_arsize(m03_couplers_to_m03_regslice_ARSIZE),\n        .s_axi_arvalid(m03_couplers_to_m03_regslice_ARVALID),\n        .s_axi_awaddr(m03_couplers_to_m03_regslice_AWADDR),\n        .s_axi_awburst(m03_couplers_to_m03_regslice_AWBURST),\n        .s_axi_awcache(m03_couplers_to_m03_regslice_AWCACHE),\n        .s_axi_awid(m03_couplers_to_m03_regslice_AWID),\n        .s_axi_awlen(m03_couplers_to_m03_regslice_AWLEN),\n        .s_axi_awlock(m03_couplers_to_m03_regslice_AWLOCK),\n        .s_axi_awprot(m03_couplers_to_m03_regslice_AWPROT),\n        .s_axi_awqos(m03_couplers_to_m03_regslice_AWQOS),\n        .s_axi_awready(m03_couplers_to_m03_regslice_AWREADY),\n        .s_axi_awregion(m03_couplers_to_m03_regslice_AWREGION),\n        .s_axi_awsize(m03_couplers_to_m03_regslice_AWSIZE),\n        .s_axi_awvalid(m03_couplers_to_m03_regslice_AWVALID),\n        .s_axi_bid(m03_couplers_to_m03_regslice_BID),\n        .s_axi_bready(m03_couplers_to_m03_regslice_BREADY),\n        .s_axi_bresp(m03_couplers_to_m03_regslice_BRESP),\n        .s_axi_bvalid(m03_couplers_to_m03_regslice_BVALID),\n        .s_axi_rdata(m03_couplers_to_m03_regslice_RDATA),\n        .s_axi_rid(m03_couplers_to_m03_regslice_RID),\n        .s_axi_rlast(m03_couplers_to_m03_regslice_RLAST),\n        .s_axi_rready(m03_couplers_to_m03_regslice_RREADY),\n        .s_axi_rresp(m03_couplers_to_m03_regslice_RRESP),\n        .s_axi_rvalid(m03_couplers_to_m03_regslice_RVALID),\n        .s_axi_wdata(m03_couplers_to_m03_regslice_WDATA),\n        .s_axi_wlast(m03_couplers_to_m03_regslice_WLAST),\n        .s_axi_wready(m03_couplers_to_m03_regslice_WREADY),\n        .s_axi_wstrb(m03_couplers_to_m03_regslice_WSTRB),\n        .s_axi_wvalid(m03_couplers_to_m03_regslice_WVALID));\nendmodule\n\nmodule s00_couplers_imp_QICM5G\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [5:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [5:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [5:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [5:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [5:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [5:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire S_ACLK_1;\n  wire S_ARESETN_1;\n  wire [63:0]s00_couplers_to_s00_regslice_ARADDR;\n  wire [1:0]s00_couplers_to_s00_regslice_ARBURST;\n  wire [3:0]s00_couplers_to_s00_regslice_ARCACHE;\n  wire [5:0]s00_couplers_to_s00_regslice_ARID;\n  wire [7:0]s00_couplers_to_s00_regslice_ARLEN;\n  wire [0:0]s00_couplers_to_s00_regslice_ARLOCK;\n  wire [2:0]s00_couplers_to_s00_regslice_ARPROT;\n  wire [3:0]s00_couplers_to_s00_regslice_ARQOS;\n  wire s00_couplers_to_s00_regslice_ARREADY;\n  wire [3:0]s00_couplers_to_s00_regslice_ARREGION;\n  wire [2:0]s00_couplers_to_s00_regslice_ARSIZE;\n  wire s00_couplers_to_s00_regslice_ARVALID;\n  wire [63:0]s00_couplers_to_s00_regslice_AWADDR;\n  wire [1:0]s00_couplers_to_s00_regslice_AWBURST;\n  wire [3:0]s00_couplers_to_s00_regslice_AWCACHE;\n  wire [5:0]s00_couplers_to_s00_regslice_AWID;\n  wire [7:0]s00_couplers_to_s00_regslice_AWLEN;\n  wire [0:0]s00_couplers_to_s00_regslice_AWLOCK;\n  wire [2:0]s00_couplers_to_s00_regslice_AWPROT;\n  wire [3:0]s00_couplers_to_s00_regslice_AWQOS;\n  wire s00_couplers_to_s00_regslice_AWREADY;\n  wire [3:0]s00_couplers_to_s00_regslice_AWREGION;\n  wire [2:0]s00_couplers_to_s00_regslice_AWSIZE;\n  wire s00_couplers_to_s00_regslice_AWVALID;\n  wire [5:0]s00_couplers_to_s00_regslice_BID;\n  wire s00_couplers_to_s00_regslice_BREADY;\n  wire [1:0]s00_couplers_to_s00_regslice_BRESP;\n  wire s00_couplers_to_s00_regslice_BVALID;\n  wire [511:0]s00_couplers_to_s00_regslice_RDATA;\n  wire [5:0]s00_couplers_to_s00_regslice_RID;\n  wire s00_couplers_to_s00_regslice_RLAST;\n  wire s00_couplers_to_s00_regslice_RREADY;\n  wire [1:0]s00_couplers_to_s00_regslice_RRESP;\n  wire s00_couplers_to_s00_regslice_RVALID;\n  wire [511:0]s00_couplers_to_s00_regslice_WDATA;\n  wire s00_couplers_to_s00_regslice_WLAST;\n  wire s00_couplers_to_s00_regslice_WREADY;\n  wire [63:0]s00_couplers_to_s00_regslice_WSTRB;\n  wire s00_couplers_to_s00_regslice_WVALID;\n  wire [63:0]s00_regslice_to_s00_couplers_ARADDR;\n  wire [1:0]s00_regslice_to_s00_couplers_ARBURST;\n  wire [3:0]s00_regslice_to_s00_couplers_ARCACHE;\n  wire [5:0]s00_regslice_to_s00_couplers_ARID;\n  wire [7:0]s00_regslice_to_s00_couplers_ARLEN;\n  wire [0:0]s00_regslice_to_s00_couplers_ARLOCK;\n  wire [2:0]s00_regslice_to_s00_couplers_ARPROT;\n  wire [3:0]s00_regslice_to_s00_couplers_ARQOS;\n  wire s00_regslice_to_s00_couplers_ARREADY;\n  wire [2:0]s00_regslice_to_s00_couplers_ARSIZE;\n  wire s00_regslice_to_s00_couplers_ARVALID;\n  wire [63:0]s00_regslice_to_s00_couplers_AWADDR;\n  wire [1:0]s00_regslice_to_s00_couplers_AWBURST;\n  wire [3:0]s00_regslice_to_s00_couplers_AWCACHE;\n  wire [5:0]s00_regslice_to_s00_couplers_AWID;\n  wire [7:0]s00_regslice_to_s00_couplers_AWLEN;\n  wire [0:0]s00_regslice_to_s00_couplers_AWLOCK;\n  wire [2:0]s00_regslice_to_s00_couplers_AWPROT;\n  wire [3:0]s00_regslice_to_s00_couplers_AWQOS;\n  wire s00_regslice_to_s00_couplers_AWREADY;\n  wire [2:0]s00_regslice_to_s00_couplers_AWSIZE;\n  wire s00_regslice_to_s00_couplers_AWVALID;\n  wire [6:0]s00_regslice_to_s00_couplers_BID;\n  wire s00_regslice_to_s00_couplers_BREADY;\n  wire [1:0]s00_regslice_to_s00_couplers_BRESP;\n  wire s00_regslice_to_s00_couplers_BVALID;\n  wire [511:0]s00_regslice_to_s00_couplers_RDATA;\n  wire [6:0]s00_regslice_to_s00_couplers_RID;\n  wire s00_regslice_to_s00_couplers_RLAST;\n  wire s00_regslice_to_s00_couplers_RREADY;\n  wire [1:0]s00_regslice_to_s00_couplers_RRESP;\n  wire s00_regslice_to_s00_couplers_RVALID;\n  wire [511:0]s00_regslice_to_s00_couplers_WDATA;\n  wire s00_regslice_to_s00_couplers_WLAST;\n  wire s00_regslice_to_s00_couplers_WREADY;\n  wire [63:0]s00_regslice_to_s00_couplers_WSTRB;\n  wire s00_regslice_to_s00_couplers_WVALID;\n\n  assign M_AXI_araddr[63:0] = s00_regslice_to_s00_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = s00_regslice_to_s00_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = s00_regslice_to_s00_couplers_ARCACHE;\n  assign M_AXI_arid[5:0] = s00_regslice_to_s00_couplers_ARID;\n  assign M_AXI_arlen[7:0] = s00_regslice_to_s00_couplers_ARLEN;\n  assign M_AXI_arlock[0] = s00_regslice_to_s00_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = s00_regslice_to_s00_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = s00_regslice_to_s00_couplers_ARQOS;\n  assign M_AXI_arsize[2:0] = s00_regslice_to_s00_couplers_ARSIZE;\n  assign M_AXI_arvalid = s00_regslice_to_s00_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = s00_regslice_to_s00_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = s00_regslice_to_s00_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = s00_regslice_to_s00_couplers_AWCACHE;\n  assign M_AXI_awid[5:0] = s00_regslice_to_s00_couplers_AWID;\n  assign M_AXI_awlen[7:0] = s00_regslice_to_s00_couplers_AWLEN;\n  assign M_AXI_awlock[0] = s00_regslice_to_s00_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = s00_regslice_to_s00_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = s00_regslice_to_s00_couplers_AWQOS;\n  assign M_AXI_awsize[2:0] = s00_regslice_to_s00_couplers_AWSIZE;\n  assign M_AXI_awvalid = s00_regslice_to_s00_couplers_AWVALID;\n  assign M_AXI_bready = s00_regslice_to_s00_couplers_BREADY;\n  assign M_AXI_rready = s00_regslice_to_s00_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = s00_regslice_to_s00_couplers_WDATA;\n  assign M_AXI_wlast = s00_regslice_to_s00_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = s00_regslice_to_s00_couplers_WSTRB;\n  assign M_AXI_wvalid = s00_regslice_to_s00_couplers_WVALID;\n  assign S_ACLK_1 = S_ACLK;\n  assign S_ARESETN_1 = S_ARESETN;\n  assign S_AXI_arready = s00_couplers_to_s00_regslice_ARREADY;\n  assign S_AXI_awready = s00_couplers_to_s00_regslice_AWREADY;\n  assign S_AXI_bid[5:0] = s00_couplers_to_s00_regslice_BID;\n  assign S_AXI_bresp[1:0] = s00_couplers_to_s00_regslice_BRESP;\n  assign S_AXI_bvalid = s00_couplers_to_s00_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = s00_couplers_to_s00_regslice_RDATA;\n  assign S_AXI_rid[5:0] = s00_couplers_to_s00_regslice_RID;\n  assign S_AXI_rlast = s00_couplers_to_s00_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = s00_couplers_to_s00_regslice_RRESP;\n  assign S_AXI_rvalid = s00_couplers_to_s00_regslice_RVALID;\n  assign S_AXI_wready = s00_couplers_to_s00_regslice_WREADY;\n  assign s00_couplers_to_s00_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign s00_couplers_to_s00_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign s00_couplers_to_s00_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign s00_couplers_to_s00_regslice_ARID = S_AXI_arid[5:0];\n  assign s00_couplers_to_s00_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign s00_couplers_to_s00_regslice_ARLOCK = S_AXI_arlock[0];\n  assign s00_couplers_to_s00_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign s00_couplers_to_s00_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign s00_couplers_to_s00_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign s00_couplers_to_s00_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign s00_couplers_to_s00_regslice_ARVALID = S_AXI_arvalid;\n  assign s00_couplers_to_s00_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign s00_couplers_to_s00_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign s00_couplers_to_s00_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign s00_couplers_to_s00_regslice_AWID = S_AXI_awid[5:0];\n  assign s00_couplers_to_s00_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign s00_couplers_to_s00_regslice_AWLOCK = S_AXI_awlock[0];\n  assign s00_couplers_to_s00_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign s00_couplers_to_s00_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign s00_couplers_to_s00_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign s00_couplers_to_s00_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign s00_couplers_to_s00_regslice_AWVALID = S_AXI_awvalid;\n  assign s00_couplers_to_s00_regslice_BREADY = S_AXI_bready;\n  assign s00_couplers_to_s00_regslice_RREADY = S_AXI_rready;\n  assign s00_couplers_to_s00_regslice_WDATA = S_AXI_wdata[511:0];\n  assign s00_couplers_to_s00_regslice_WLAST = S_AXI_wlast;\n  assign s00_couplers_to_s00_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign s00_couplers_to_s00_regslice_WVALID = S_AXI_wvalid;\n  assign s00_regslice_to_s00_couplers_ARREADY = M_AXI_arready;\n  assign s00_regslice_to_s00_couplers_AWREADY = M_AXI_awready;\n  assign s00_regslice_to_s00_couplers_BID = M_AXI_bid[6:0];\n  assign s00_regslice_to_s00_couplers_BRESP = M_AXI_bresp[1:0];\n  assign s00_regslice_to_s00_couplers_BVALID = M_AXI_bvalid;\n  assign s00_regslice_to_s00_couplers_RDATA = M_AXI_rdata[511:0];\n  assign s00_regslice_to_s00_couplers_RID = M_AXI_rid[6:0];\n  assign s00_regslice_to_s00_couplers_RLAST = M_AXI_rlast;\n  assign s00_regslice_to_s00_couplers_RRESP = M_AXI_rresp[1:0];\n  assign s00_regslice_to_s00_couplers_RVALID = M_AXI_rvalid;\n  assign s00_regslice_to_s00_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_s00_regslice_0 s00_regslice\n       (.aclk(S_ACLK_1),\n        .aresetn(S_ARESETN_1),\n        .m_axi_araddr(s00_regslice_to_s00_couplers_ARADDR),\n        .m_axi_arburst(s00_regslice_to_s00_couplers_ARBURST),\n        .m_axi_arcache(s00_regslice_to_s00_couplers_ARCACHE),\n        .m_axi_arid(s00_regslice_to_s00_couplers_ARID),\n        .m_axi_arlen(s00_regslice_to_s00_couplers_ARLEN),\n        .m_axi_arlock(s00_regslice_to_s00_couplers_ARLOCK),\n        .m_axi_arprot(s00_regslice_to_s00_couplers_ARPROT),\n        .m_axi_arqos(s00_regslice_to_s00_couplers_ARQOS),\n        .m_axi_arready(s00_regslice_to_s00_couplers_ARREADY),\n        .m_axi_arsize(s00_regslice_to_s00_couplers_ARSIZE),\n        .m_axi_arvalid(s00_regslice_to_s00_couplers_ARVALID),\n        .m_axi_awaddr(s00_regslice_to_s00_couplers_AWADDR),\n        .m_axi_awburst(s00_regslice_to_s00_couplers_AWBURST),\n        .m_axi_awcache(s00_regslice_to_s00_couplers_AWCACHE),\n        .m_axi_awid(s00_regslice_to_s00_couplers_AWID),\n        .m_axi_awlen(s00_regslice_to_s00_couplers_AWLEN),\n        .m_axi_awlock(s00_regslice_to_s00_couplers_AWLOCK),\n        .m_axi_awprot(s00_regslice_to_s00_couplers_AWPROT),\n        .m_axi_awqos(s00_regslice_to_s00_couplers_AWQOS),\n        .m_axi_awready(s00_regslice_to_s00_couplers_AWREADY),\n        .m_axi_awsize(s00_regslice_to_s00_couplers_AWSIZE),\n        .m_axi_awvalid(s00_regslice_to_s00_couplers_AWVALID),\n        .m_axi_bid(s00_regslice_to_s00_couplers_BID[5:0]),\n        .m_axi_bready(s00_regslice_to_s00_couplers_BREADY),\n        .m_axi_bresp(s00_regslice_to_s00_couplers_BRESP),\n        .m_axi_bvalid(s00_regslice_to_s00_couplers_BVALID),\n        .m_axi_rdata(s00_regslice_to_s00_couplers_RDATA),\n        .m_axi_rid(s00_regslice_to_s00_couplers_RID[5:0]),\n        .m_axi_rlast(s00_regslice_to_s00_couplers_RLAST),\n        .m_axi_rready(s00_regslice_to_s00_couplers_RREADY),\n        .m_axi_rresp(s00_regslice_to_s00_couplers_RRESP),\n        .m_axi_rvalid(s00_regslice_to_s00_couplers_RVALID),\n        .m_axi_wdata(s00_regslice_to_s00_couplers_WDATA),\n        .m_axi_wlast(s00_regslice_to_s00_couplers_WLAST),\n        .m_axi_wready(s00_regslice_to_s00_couplers_WREADY),\n        .m_axi_wstrb(s00_regslice_to_s00_couplers_WSTRB),\n        .m_axi_wvalid(s00_regslice_to_s00_couplers_WVALID),\n        .s_axi_araddr(s00_couplers_to_s00_regslice_ARADDR),\n        .s_axi_arburst(s00_couplers_to_s00_regslice_ARBURST),\n        .s_axi_arcache(s00_couplers_to_s00_regslice_ARCACHE),\n        .s_axi_arid(s00_couplers_to_s00_regslice_ARID),\n        .s_axi_arlen(s00_couplers_to_s00_regslice_ARLEN),\n        .s_axi_arlock(s00_couplers_to_s00_regslice_ARLOCK),\n        .s_axi_arprot(s00_couplers_to_s00_regslice_ARPROT),\n        .s_axi_arqos(s00_couplers_to_s00_regslice_ARQOS),\n        .s_axi_arready(s00_couplers_to_s00_regslice_ARREADY),\n        .s_axi_arregion(s00_couplers_to_s00_regslice_ARREGION),\n        .s_axi_arsize(s00_couplers_to_s00_regslice_ARSIZE),\n        .s_axi_arvalid(s00_couplers_to_s00_regslice_ARVALID),\n        .s_axi_awaddr(s00_couplers_to_s00_regslice_AWADDR),\n        .s_axi_awburst(s00_couplers_to_s00_regslice_AWBURST),\n        .s_axi_awcache(s00_couplers_to_s00_regslice_AWCACHE),\n        .s_axi_awid(s00_couplers_to_s00_regslice_AWID),\n        .s_axi_awlen(s00_couplers_to_s00_regslice_AWLEN),\n        .s_axi_awlock(s00_couplers_to_s00_regslice_AWLOCK),\n        .s_axi_awprot(s00_couplers_to_s00_regslice_AWPROT),\n        .s_axi_awqos(s00_couplers_to_s00_regslice_AWQOS),\n        .s_axi_awready(s00_couplers_to_s00_regslice_AWREADY),\n        .s_axi_awregion(s00_couplers_to_s00_regslice_AWREGION),\n        .s_axi_awsize(s00_couplers_to_s00_regslice_AWSIZE),\n        .s_axi_awvalid(s00_couplers_to_s00_regslice_AWVALID),\n        .s_axi_bid(s00_couplers_to_s00_regslice_BID),\n        .s_axi_bready(s00_couplers_to_s00_regslice_BREADY),\n        .s_axi_bresp(s00_couplers_to_s00_regslice_BRESP),\n        .s_axi_bvalid(s00_couplers_to_s00_regslice_BVALID),\n        .s_axi_rdata(s00_couplers_to_s00_regslice_RDATA),\n        .s_axi_rid(s00_couplers_to_s00_regslice_RID),\n        .s_axi_rlast(s00_couplers_to_s00_regslice_RLAST),\n        .s_axi_rready(s00_couplers_to_s00_regslice_RREADY),\n        .s_axi_rresp(s00_couplers_to_s00_regslice_RRESP),\n        .s_axi_rvalid(s00_couplers_to_s00_regslice_RVALID),\n        .s_axi_wdata(s00_couplers_to_s00_regslice_WDATA),\n        .s_axi_wlast(s00_couplers_to_s00_regslice_WLAST),\n        .s_axi_wready(s00_couplers_to_s00_regslice_WREADY),\n        .s_axi_wstrb(s00_couplers_to_s00_regslice_WSTRB),\n        .s_axi_wvalid(s00_couplers_to_s00_regslice_WVALID));\nendmodule\n\nmodule s01_couplers_imp_GSTXQ8\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [5:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [5:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [5:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [5:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [5:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [5:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire S_ACLK_1;\n  wire S_ARESETN_1;\n  wire [63:0]s01_couplers_to_s01_regslice_ARADDR;\n  wire [1:0]s01_couplers_to_s01_regslice_ARBURST;\n  wire [3:0]s01_couplers_to_s01_regslice_ARCACHE;\n  wire [5:0]s01_couplers_to_s01_regslice_ARID;\n  wire [7:0]s01_couplers_to_s01_regslice_ARLEN;\n  wire [0:0]s01_couplers_to_s01_regslice_ARLOCK;\n  wire [2:0]s01_couplers_to_s01_regslice_ARPROT;\n  wire [3:0]s01_couplers_to_s01_regslice_ARQOS;\n  wire s01_couplers_to_s01_regslice_ARREADY;\n  wire [3:0]s01_couplers_to_s01_regslice_ARREGION;\n  wire [2:0]s01_couplers_to_s01_regslice_ARSIZE;\n  wire s01_couplers_to_s01_regslice_ARVALID;\n  wire [63:0]s01_couplers_to_s01_regslice_AWADDR;\n  wire [1:0]s01_couplers_to_s01_regslice_AWBURST;\n  wire [3:0]s01_couplers_to_s01_regslice_AWCACHE;\n  wire [5:0]s01_couplers_to_s01_regslice_AWID;\n  wire [7:0]s01_couplers_to_s01_regslice_AWLEN;\n  wire [0:0]s01_couplers_to_s01_regslice_AWLOCK;\n  wire [2:0]s01_couplers_to_s01_regslice_AWPROT;\n  wire [3:0]s01_couplers_to_s01_regslice_AWQOS;\n  wire s01_couplers_to_s01_regslice_AWREADY;\n  wire [3:0]s01_couplers_to_s01_regslice_AWREGION;\n  wire [2:0]s01_couplers_to_s01_regslice_AWSIZE;\n  wire s01_couplers_to_s01_regslice_AWVALID;\n  wire [5:0]s01_couplers_to_s01_regslice_BID;\n  wire s01_couplers_to_s01_regslice_BREADY;\n  wire [1:0]s01_couplers_to_s01_regslice_BRESP;\n  wire s01_couplers_to_s01_regslice_BVALID;\n  wire [511:0]s01_couplers_to_s01_regslice_RDATA;\n  wire [5:0]s01_couplers_to_s01_regslice_RID;\n  wire s01_couplers_to_s01_regslice_RLAST;\n  wire s01_couplers_to_s01_regslice_RREADY;\n  wire [1:0]s01_couplers_to_s01_regslice_RRESP;\n  wire s01_couplers_to_s01_regslice_RVALID;\n  wire [511:0]s01_couplers_to_s01_regslice_WDATA;\n  wire s01_couplers_to_s01_regslice_WLAST;\n  wire s01_couplers_to_s01_regslice_WREADY;\n  wire [63:0]s01_couplers_to_s01_regslice_WSTRB;\n  wire s01_couplers_to_s01_regslice_WVALID;\n  wire [63:0]s01_regslice_to_s01_couplers_ARADDR;\n  wire [1:0]s01_regslice_to_s01_couplers_ARBURST;\n  wire [3:0]s01_regslice_to_s01_couplers_ARCACHE;\n  wire [5:0]s01_regslice_to_s01_couplers_ARID;\n  wire [7:0]s01_regslice_to_s01_couplers_ARLEN;\n  wire [0:0]s01_regslice_to_s01_couplers_ARLOCK;\n  wire [2:0]s01_regslice_to_s01_couplers_ARPROT;\n  wire [3:0]s01_regslice_to_s01_couplers_ARQOS;\n  wire s01_regslice_to_s01_couplers_ARREADY;\n  wire [2:0]s01_regslice_to_s01_couplers_ARSIZE;\n  wire s01_regslice_to_s01_couplers_ARVALID;\n  wire [63:0]s01_regslice_to_s01_couplers_AWADDR;\n  wire [1:0]s01_regslice_to_s01_couplers_AWBURST;\n  wire [3:0]s01_regslice_to_s01_couplers_AWCACHE;\n  wire [5:0]s01_regslice_to_s01_couplers_AWID;\n  wire [7:0]s01_regslice_to_s01_couplers_AWLEN;\n  wire [0:0]s01_regslice_to_s01_couplers_AWLOCK;\n  wire [2:0]s01_regslice_to_s01_couplers_AWPROT;\n  wire [3:0]s01_regslice_to_s01_couplers_AWQOS;\n  wire s01_regslice_to_s01_couplers_AWREADY;\n  wire [2:0]s01_regslice_to_s01_couplers_AWSIZE;\n  wire s01_regslice_to_s01_couplers_AWVALID;\n  wire [6:0]s01_regslice_to_s01_couplers_BID;\n  wire s01_regslice_to_s01_couplers_BREADY;\n  wire [1:0]s01_regslice_to_s01_couplers_BRESP;\n  wire s01_regslice_to_s01_couplers_BVALID;\n  wire [511:0]s01_regslice_to_s01_couplers_RDATA;\n  wire [6:0]s01_regslice_to_s01_couplers_RID;\n  wire s01_regslice_to_s01_couplers_RLAST;\n  wire s01_regslice_to_s01_couplers_RREADY;\n  wire [1:0]s01_regslice_to_s01_couplers_RRESP;\n  wire s01_regslice_to_s01_couplers_RVALID;\n  wire [511:0]s01_regslice_to_s01_couplers_WDATA;\n  wire s01_regslice_to_s01_couplers_WLAST;\n  wire s01_regslice_to_s01_couplers_WREADY;\n  wire [63:0]s01_regslice_to_s01_couplers_WSTRB;\n  wire s01_regslice_to_s01_couplers_WVALID;\n\n  assign M_AXI_araddr[63:0] = s01_regslice_to_s01_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = s01_regslice_to_s01_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = s01_regslice_to_s01_couplers_ARCACHE;\n  assign M_AXI_arid[5:0] = s01_regslice_to_s01_couplers_ARID;\n  assign M_AXI_arlen[7:0] = s01_regslice_to_s01_couplers_ARLEN;\n  assign M_AXI_arlock[0] = s01_regslice_to_s01_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = s01_regslice_to_s01_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = s01_regslice_to_s01_couplers_ARQOS;\n  assign M_AXI_arsize[2:0] = s01_regslice_to_s01_couplers_ARSIZE;\n  assign M_AXI_arvalid = s01_regslice_to_s01_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = s01_regslice_to_s01_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = s01_regslice_to_s01_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = s01_regslice_to_s01_couplers_AWCACHE;\n  assign M_AXI_awid[5:0] = s01_regslice_to_s01_couplers_AWID;\n  assign M_AXI_awlen[7:0] = s01_regslice_to_s01_couplers_AWLEN;\n  assign M_AXI_awlock[0] = s01_regslice_to_s01_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = s01_regslice_to_s01_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = s01_regslice_to_s01_couplers_AWQOS;\n  assign M_AXI_awsize[2:0] = s01_regslice_to_s01_couplers_AWSIZE;\n  assign M_AXI_awvalid = s01_regslice_to_s01_couplers_AWVALID;\n  assign M_AXI_bready = s01_regslice_to_s01_couplers_BREADY;\n  assign M_AXI_rready = s01_regslice_to_s01_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = s01_regslice_to_s01_couplers_WDATA;\n  assign M_AXI_wlast = s01_regslice_to_s01_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = s01_regslice_to_s01_couplers_WSTRB;\n  assign M_AXI_wvalid = s01_regslice_to_s01_couplers_WVALID;\n  assign S_ACLK_1 = S_ACLK;\n  assign S_ARESETN_1 = S_ARESETN;\n  assign S_AXI_arready = s01_couplers_to_s01_regslice_ARREADY;\n  assign S_AXI_awready = s01_couplers_to_s01_regslice_AWREADY;\n  assign S_AXI_bid[5:0] = s01_couplers_to_s01_regslice_BID;\n  assign S_AXI_bresp[1:0] = s01_couplers_to_s01_regslice_BRESP;\n  assign S_AXI_bvalid = s01_couplers_to_s01_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = s01_couplers_to_s01_regslice_RDATA;\n  assign S_AXI_rid[5:0] = s01_couplers_to_s01_regslice_RID;\n  assign S_AXI_rlast = s01_couplers_to_s01_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = s01_couplers_to_s01_regslice_RRESP;\n  assign S_AXI_rvalid = s01_couplers_to_s01_regslice_RVALID;\n  assign S_AXI_wready = s01_couplers_to_s01_regslice_WREADY;\n  assign s01_couplers_to_s01_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign s01_couplers_to_s01_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign s01_couplers_to_s01_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign s01_couplers_to_s01_regslice_ARID = S_AXI_arid[5:0];\n  assign s01_couplers_to_s01_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign s01_couplers_to_s01_regslice_ARLOCK = S_AXI_arlock[0];\n  assign s01_couplers_to_s01_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign s01_couplers_to_s01_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign s01_couplers_to_s01_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign s01_couplers_to_s01_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign s01_couplers_to_s01_regslice_ARVALID = S_AXI_arvalid;\n  assign s01_couplers_to_s01_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign s01_couplers_to_s01_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign s01_couplers_to_s01_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign s01_couplers_to_s01_regslice_AWID = S_AXI_awid[5:0];\n  assign s01_couplers_to_s01_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign s01_couplers_to_s01_regslice_AWLOCK = S_AXI_awlock[0];\n  assign s01_couplers_to_s01_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign s01_couplers_to_s01_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign s01_couplers_to_s01_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign s01_couplers_to_s01_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign s01_couplers_to_s01_regslice_AWVALID = S_AXI_awvalid;\n  assign s01_couplers_to_s01_regslice_BREADY = S_AXI_bready;\n  assign s01_couplers_to_s01_regslice_RREADY = S_AXI_rready;\n  assign s01_couplers_to_s01_regslice_WDATA = S_AXI_wdata[511:0];\n  assign s01_couplers_to_s01_regslice_WLAST = S_AXI_wlast;\n  assign s01_couplers_to_s01_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign s01_couplers_to_s01_regslice_WVALID = S_AXI_wvalid;\n  assign s01_regslice_to_s01_couplers_ARREADY = M_AXI_arready;\n  assign s01_regslice_to_s01_couplers_AWREADY = M_AXI_awready;\n  assign s01_regslice_to_s01_couplers_BID = M_AXI_bid[6:0];\n  assign s01_regslice_to_s01_couplers_BRESP = M_AXI_bresp[1:0];\n  assign s01_regslice_to_s01_couplers_BVALID = M_AXI_bvalid;\n  assign s01_regslice_to_s01_couplers_RDATA = M_AXI_rdata[511:0];\n  assign s01_regslice_to_s01_couplers_RID = M_AXI_rid[6:0];\n  assign s01_regslice_to_s01_couplers_RLAST = M_AXI_rlast;\n  assign s01_regslice_to_s01_couplers_RRESP = M_AXI_rresp[1:0];\n  assign s01_regslice_to_s01_couplers_RVALID = M_AXI_rvalid;\n  assign s01_regslice_to_s01_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_s01_regslice_0 s01_regslice\n       (.aclk(S_ACLK_1),\n        .aresetn(S_ARESETN_1),\n        .m_axi_araddr(s01_regslice_to_s01_couplers_ARADDR),\n        .m_axi_arburst(s01_regslice_to_s01_couplers_ARBURST),\n        .m_axi_arcache(s01_regslice_to_s01_couplers_ARCACHE),\n        .m_axi_arid(s01_regslice_to_s01_couplers_ARID),\n        .m_axi_arlen(s01_regslice_to_s01_couplers_ARLEN),\n        .m_axi_arlock(s01_regslice_to_s01_couplers_ARLOCK),\n        .m_axi_arprot(s01_regslice_to_s01_couplers_ARPROT),\n        .m_axi_arqos(s01_regslice_to_s01_couplers_ARQOS),\n        .m_axi_arready(s01_regslice_to_s01_couplers_ARREADY),\n        .m_axi_arsize(s01_regslice_to_s01_couplers_ARSIZE),\n        .m_axi_arvalid(s01_regslice_to_s01_couplers_ARVALID),\n        .m_axi_awaddr(s01_regslice_to_s01_couplers_AWADDR),\n        .m_axi_awburst(s01_regslice_to_s01_couplers_AWBURST),\n        .m_axi_awcache(s01_regslice_to_s01_couplers_AWCACHE),\n        .m_axi_awid(s01_regslice_to_s01_couplers_AWID),\n        .m_axi_awlen(s01_regslice_to_s01_couplers_AWLEN),\n        .m_axi_awlock(s01_regslice_to_s01_couplers_AWLOCK),\n        .m_axi_awprot(s01_regslice_to_s01_couplers_AWPROT),\n        .m_axi_awqos(s01_regslice_to_s01_couplers_AWQOS),\n        .m_axi_awready(s01_regslice_to_s01_couplers_AWREADY),\n        .m_axi_awsize(s01_regslice_to_s01_couplers_AWSIZE),\n        .m_axi_awvalid(s01_regslice_to_s01_couplers_AWVALID),\n        .m_axi_bid(s01_regslice_to_s01_couplers_BID[5:0]),\n        .m_axi_bready(s01_regslice_to_s01_couplers_BREADY),\n        .m_axi_bresp(s01_regslice_to_s01_couplers_BRESP),\n        .m_axi_bvalid(s01_regslice_to_s01_couplers_BVALID),\n        .m_axi_rdata(s01_regslice_to_s01_couplers_RDATA),\n        .m_axi_rid(s01_regslice_to_s01_couplers_RID[5:0]),\n        .m_axi_rlast(s01_regslice_to_s01_couplers_RLAST),\n        .m_axi_rready(s01_regslice_to_s01_couplers_RREADY),\n        .m_axi_rresp(s01_regslice_to_s01_couplers_RRESP),\n        .m_axi_rvalid(s01_regslice_to_s01_couplers_RVALID),\n        .m_axi_wdata(s01_regslice_to_s01_couplers_WDATA),\n        .m_axi_wlast(s01_regslice_to_s01_couplers_WLAST),\n        .m_axi_wready(s01_regslice_to_s01_couplers_WREADY),\n        .m_axi_wstrb(s01_regslice_to_s01_couplers_WSTRB),\n        .m_axi_wvalid(s01_regslice_to_s01_couplers_WVALID),\n        .s_axi_araddr(s01_couplers_to_s01_regslice_ARADDR),\n        .s_axi_arburst(s01_couplers_to_s01_regslice_ARBURST),\n        .s_axi_arcache(s01_couplers_to_s01_regslice_ARCACHE),\n        .s_axi_arid(s01_couplers_to_s01_regslice_ARID),\n        .s_axi_arlen(s01_couplers_to_s01_regslice_ARLEN),\n        .s_axi_arlock(s01_couplers_to_s01_regslice_ARLOCK),\n        .s_axi_arprot(s01_couplers_to_s01_regslice_ARPROT),\n        .s_axi_arqos(s01_couplers_to_s01_regslice_ARQOS),\n        .s_axi_arready(s01_couplers_to_s01_regslice_ARREADY),\n        .s_axi_arregion(s01_couplers_to_s01_regslice_ARREGION),\n        .s_axi_arsize(s01_couplers_to_s01_regslice_ARSIZE),\n        .s_axi_arvalid(s01_couplers_to_s01_regslice_ARVALID),\n        .s_axi_awaddr(s01_couplers_to_s01_regslice_AWADDR),\n        .s_axi_awburst(s01_couplers_to_s01_regslice_AWBURST),\n        .s_axi_awcache(s01_couplers_to_s01_regslice_AWCACHE),\n        .s_axi_awid(s01_couplers_to_s01_regslice_AWID),\n        .s_axi_awlen(s01_couplers_to_s01_regslice_AWLEN),\n        .s_axi_awlock(s01_couplers_to_s01_regslice_AWLOCK),\n        .s_axi_awprot(s01_couplers_to_s01_regslice_AWPROT),\n        .s_axi_awqos(s01_couplers_to_s01_regslice_AWQOS),\n        .s_axi_awready(s01_couplers_to_s01_regslice_AWREADY),\n        .s_axi_awregion(s01_couplers_to_s01_regslice_AWREGION),\n        .s_axi_awsize(s01_couplers_to_s01_regslice_AWSIZE),\n        .s_axi_awvalid(s01_couplers_to_s01_regslice_AWVALID),\n        .s_axi_bid(s01_couplers_to_s01_regslice_BID),\n        .s_axi_bready(s01_couplers_to_s01_regslice_BREADY),\n        .s_axi_bresp(s01_couplers_to_s01_regslice_BRESP),\n        .s_axi_bvalid(s01_couplers_to_s01_regslice_BVALID),\n        .s_axi_rdata(s01_couplers_to_s01_regslice_RDATA),\n        .s_axi_rid(s01_couplers_to_s01_regslice_RID),\n        .s_axi_rlast(s01_couplers_to_s01_regslice_RLAST),\n        .s_axi_rready(s01_couplers_to_s01_regslice_RREADY),\n        .s_axi_rresp(s01_couplers_to_s01_regslice_RRESP),\n        .s_axi_rvalid(s01_couplers_to_s01_regslice_RVALID),\n        .s_axi_wdata(s01_couplers_to_s01_regslice_WDATA),\n        .s_axi_wlast(s01_couplers_to_s01_regslice_WLAST),\n        .s_axi_wready(s01_couplers_to_s01_regslice_WREADY),\n        .s_axi_wstrb(s01_couplers_to_s01_regslice_WSTRB),\n        .s_axi_wvalid(s01_couplers_to_s01_regslice_WVALID));\nendmodule\n", "num_lines": 5426}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 250000000, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'H00),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 433}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_15_axi_register_slice,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_m00_regslice_0,axi_register_slice_v2_1_15_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_m00_regslice_0,axi_register_slice_v2_1_15_axi_register_slice,{x_ipProduct=Vivado 2017.4.op,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=6,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7\\\n,C_REG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 250000000, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'H00),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 435}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_a493_wrapper.bd\n//Design : bd_a493_wrapper\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule bd_a493_wrapper\n   (S_BSCAN_bscanid_en,\n    S_BSCAN_capture,\n    S_BSCAN_drck,\n    S_BSCAN_reset,\n    S_BSCAN_runtest,\n    S_BSCAN_sel,\n    S_BSCAN_shift,\n    S_BSCAN_tck,\n    S_BSCAN_tdi,\n    S_BSCAN_tdo,\n    S_BSCAN_tms,\n    S_BSCAN_update,\n    clk);\n  input S_BSCAN_bscanid_en;\n  input S_BSCAN_capture;\n  input S_BSCAN_drck;\n  input S_BSCAN_reset;\n  input S_BSCAN_runtest;\n  input S_BSCAN_sel;\n  input S_BSCAN_shift;\n  input S_BSCAN_tck;\n  input S_BSCAN_tdi;\n  output S_BSCAN_tdo;\n  input S_BSCAN_tms;\n  input S_BSCAN_update;\n  input clk;\n\n  wire S_BSCAN_bscanid_en;\n  wire S_BSCAN_capture;\n  wire S_BSCAN_drck;\n  wire S_BSCAN_reset;\n  wire S_BSCAN_runtest;\n  wire S_BSCAN_sel;\n  wire S_BSCAN_shift;\n  wire S_BSCAN_tck;\n  wire S_BSCAN_tdi;\n  wire S_BSCAN_tdo;\n  wire S_BSCAN_tms;\n  wire S_BSCAN_update;\n  wire clk;\n\n  bd_a493 bd_a493_i\n       (.S_BSCAN_bscanid_en(S_BSCAN_bscanid_en),\n        .S_BSCAN_capture(S_BSCAN_capture),\n        .S_BSCAN_drck(S_BSCAN_drck),\n        .S_BSCAN_reset(S_BSCAN_reset),\n        .S_BSCAN_runtest(S_BSCAN_runtest),\n        .S_BSCAN_sel(S_BSCAN_sel),\n        .S_BSCAN_shift(S_BSCAN_shift),\n        .S_BSCAN_tck(S_BSCAN_tck),\n        .S_BSCAN_tdi(S_BSCAN_tdi),\n        .S_BSCAN_tdo(S_BSCAN_tdo),\n        .S_BSCAN_tms(S_BSCAN_tms),\n        .S_BSCAN_update(S_BSCAN_update),\n        .clk(clk));\nendmodule\n", "num_lines": 66}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nYugOLIF1XBreTDYRaNSWelgjmV3GIQ3y7FKiDB9UiIB++fAUC4TXcrfthfgN8befqwACkO3Q4k0c\nvJxv/aokgQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nP86BhFBNNa0qr9Q2+Wo0KACiIyDg4VPZdSis8bLUVn6FrcCD6TyMD6qWsX7GqSzkSyajfw5KoNS5\nrAZcRWAMv14anbm7VDJCIblrxr97wW1wDK0tJz6KsyHENdmS+W0PhSl0PyC6LE8TbUq4mev1WMPa\ne8qt1TLduNZhmfYNEEg=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\ngWBenVTIP5Q+rcNXfn1zPEjuUtszskvpUVNF25Xh81JnRdMPCp/0AGJPx+mPKwQ62keEUCK7jImu\n0uCqq7uEhg8CAhGkckxz0ziMi5p3crim/FOPfZSxzcfVA0myImyw/jA25kK2gqWItxmETSoXCqJJ\nxjTH/Kdlxzn5v3BlGFnjUMmgDpw+7ZlRLWclsVDPWcyttlqzmOpUVNRybjmRjQ047dZKoaEnV7aL\nJadzAQ1SqJzBdkDtBC4ls9rDZ0efLPq2CaHSH2lKmJWzqvjdbahTe/uDqwZlM/3ri9uvioLaock3\nBYN0ATxKAINgg8QSBFGOvETVtbNj0tmio/74Jg==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUA332GmFKmVHrrGry7Cyuflehk/VbtxlBHEATtE4ZDxpaTPEmq4fqpuW3/eIdDceGsGBiaQuMN9K\nWHRjmvo00KBUbhMYtfB1gjlmZEboE2pGVM53sCnoWcRuUcFptlHy3SPD43x91G4s/5AG3W+1+WfG\ndqqfUNJVltc7+nD/QSz52JWyt2BKcwXzXUegWHFyWPlXXyRha6uiHm5A3aFVX9XSCQMUBVg9KOgQ\nr17LLKqYda/v6o1fu2DbIpPXqeviObYOGtxIlZlCKEQ0WQ16wVhC7M7JMUM8K1ajQIP6aFm+lH0T\nT0TAEilCZfV2IBv8ZeVngUGkozMdcE2q607VAg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nJkclL4oQ89VKThgpnFORp4DkQ+l+oHyNRU+cUXBcYSussbqYTJL6YmJORdubTTO26u6Gzu7Zi8eR\nCof7Krp+GgFdv/lyHLisqmpxJDZ7fQJTFSmWQ1sN09PbMajgp5uypgG17Qqsv6Efx7DaBK5bWBFL\nzYY4TfY8F27SWO7q+F4ZXrJVV+ljd3jMxOp0CO33BlH7VTdJmnHbnGwVoy7NS7ktTu5O4mtjSy5B\nim8NDWKOPmwonslxiaCWWhRcIUWJMoS3RW+hbISleB+u2f6Hv6Cq0ewXO8bpInYwlzrVk138Qwn8\nPZory2IpEEHyD3/RAkNZjAO5MGkRMmlC6knbhg==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nP0095JhTyRSuAcV3jYJyGhT1pAQ63Ikz2jcw/xarWfO4myeR2ki2IxiL2BogiBQPifhiQ+8e/taC\nZCqKABC2nUd7sP5K5FMLxqEqvaSGhMtRO2Qx+bTN2vfUmVhFmm5F0IDL69aSPE0VUYhlP+Aw6isG\nmHBHYBCtHhMlBBTHiBI=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfVKST5L4zOIHEw8rTePPdwZAh4xL2unQREo9UhjWF63YVGB1vNoHQzJFNQi2s74hnMxp4aeUGW3A\nnhI/ztVR4LEwZ7XH7wwwmLntNjOp08e4L0SwqDu4k9wj2Mq4P87tHDh2OlNiLNBP9KNGLRKuh6L7\nrvsNzCz5uZW5s7nBY60UupCfWM5iYb05yX1fiPvYksz5uEon77IwhleTgsDLGSjDpO/3MsRecpOY\n6zxdY0uNkfRy/e+huHZvIRI9Tgx9p4p5MHkKiVX5pzmTHVFHILH/8jpxbyunuxTvGsgkRSrn/BzR\nCr6wvT7hHeY/W1F7h1vfxGVI4Ek5baJkO9T+vg==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64336)\n`pragma protect data_block\nkE3zh5FB1r3vI8ZJiCJ6FWF+XzfFQVQgnzQJ/PJpjvgCXoAs4Zjsl6nmvDpPHpRl1X32r55UNGOi\nrzvS7eJCMJeieiUb8KcN1+k9krnT6S4qk6dWAtm57amEO8+SlPVtgy1tkIGJYbb8LomTrg6JKf1q\nmpnSuP6AyfZHl1hcXlpc6bd4uJId9F/xcZnJaMEQTk2Xkh0YZwzFzeJiYXNXkaANr2sFv7jst1E1\nwJT0/zDSlQMmJHtvHYgqniLGO0LTUERIJn2n3LlE+Nb1n6im8tMfUK9/omKdJrvVZAmHwm6y1KfX\nSR5hA5hizsxzuEmVhhICN34dve/ajVFv00CqzpxQcnSBCirgk/Od85aRxbLRw7wKTDQVTqkGC5vk\n8B71OWlKiZ/nHzlwZ9hkKlT5HkYDPZN426UwuQXkSdSoit7sDolGhTt4BUWi4BL1gUE1DZ/7H+Pc\nOIDFwGjTInrdA+MN85INFgXppeRHIfUeeJV6PNisW2AElJtcXF97zM77KR0g2IiTqapwRFlRAMpQ\ndmybCFy78g+H+cfr3d76Eo7sgOSPiULbuDnW5OocD16sTNjQBvfOBZ1a8fcYC0eVM/MPfFqAJMX8\nhzpp+YLA1YWJ8/mAVQhlhjc4KKcIn0RiMbw1LSTX142bdXJMBujGVnYH2QwtVCJwtuERXFtiBcHK\nU7EKh6EAIU9yCp58uJMNIub6tmkKj3b3pO5oAxbD2T1vOSfaQzg0TsmrVL6y+n+rXPnEyvrgMtw7\nDlQ8o1tq4vjKbXAMiP3VHX9luvJQB5yRoanW10HoSFcPyGhuyvBscFIWTC+BEA3hNGyk5czChKPF\n+vMFqE5wtBfiuGKEi4YBS4B6ZwpMPspnZwYf2NHSNQqfLSp1Y8r9RY/RbhF3Hc9AAXs29XP2YY2R\nDt8z15QRDaBBCVYRckMMTmGpOJ26zR/MWF3F5a9Qf5IghfFoimkitsN8O4mGDH1avgkPNpfc/5oq\nrh8goxqhDyYi9r6oAZxul3ymzQaklgK8XVa9W2wYLPQ5HVUIzH+fx7yOryc/b0XpcAYDhsiA55uW\nxPOsFmqwrzhGoEM6/sPeESOzKxGqAuWArX1dYw3B1NIRwc/SiICNy0gVTvq67BOMMfU2jEfH1zss\n907/tTkECdjUTaTA+D9QGzdlwAnxMLZS/5Jp7CaJduYxlS3SjEgCALpp8pO3FrG3dvCbzob3X6l/\nHywXPt6zQeozZUD9te+GbwL4nVBJQoDFFiKpciE0aFKU2H6IF0YZ9bQKJKYkBkYI6Lg68EPLAPfi\nHgpWSGcq0sr03CFqAvZIennPxsmwghVPPQBDInhSRM7ogh6JVSa3wYiW90Im3BjhIeZuTVwWoejY\nZtDwCn1vqNjdVK1h0k+6sZkoAJx/tKymMzQ79DNfKptG48yUmhC/F7A6bL9CZ4J0xKpJAT+0rmtd\nwEym2mskpzCcOGgRltbipx2L0w5kmRXMdyjEta4eXyFEMAzsWznDHXMv2vq5XwM0savwMfuWTyY4\nXXPdS5QFO94+jhMoG9DQ1+S+LR69rqNM/jCH6/Zgk9+GUebipjHT3BHiNgq3pjhrhoBCNVW+k8Ra\nikrBqwm62uE0Kvj7UIagh8ZVrswAyXSLIof3/bVQAJhZmB3055LH2U/4a+fEsD4mlboFaa6zet2t\nAhSATWM5T2Rxo27bt59Gb3ZUMBPTojqEfgvWWMBvawl1GlesvaxdtH3t7LjvwoXN9tdEdhdIoXW7\ncnPRYqV9hD+jSj/wDAHBKCAqn/06LxSxEo1v06AkDTali2Ibu/LpGRg+v42BQSTALzWzxmp9OZ+G\nQBOmW0FWoBr3Np7cOgqb1y5OI+hODFfRwREojfbzTDLy7ZR3RTOCEdwJ83BGogbKuZHCe4F8fVy/\nEzUHRrXI9Glt4cEZiFsJDXxf8DrBbMCe47ZO/4Vb8CQwK0Zp1ur0bGW6eZJLvm2CZDenu+smqHyM\n8cNa+X5ZWUSZdAky0ggxJvYzGj1NLWRkA3m+yU+dKGGtlf/ZyyKW8UFiemUtcK14bXza4wz86bh6\nbsEzG2TRvNc6sbZMVnkxLHYnx/xPQrWFNhKNcb16XcXCaB6WFYv+E6+GM/mR8raMgI0K1rSj7Cni\nWyKsBmpgxTKkNy540JxNPM1vmm48rjCWehZwR/BFn/eNpQZlRe261hIosBDqnVgUvGphdsrJk2tP\nuvtY6UHx4FoZy42AjlxAG9fTbwMZP/GKLN2Wn+uc6iDBnGswOQTOQl0glpbfKEJnkxuscJBlzVXK\nbIAc516dj2fAc4P8qSHMIIMMmrRtKlyoKbGUpuCdDAGCwNiB8e2ZkD3Z18aQUYjYXrudHUOsg5jn\nIoIQN89ZyPNR6r6l7HM3EmnD2I7C4nxEzYwSOaIKPYClX6pE2lH4j3BfWEH6sEd/Ff/H2P8j3/jW\nIbBz30hNDupx7kOjNavnbibhcWayZ8dsA9bmGHm0bVu6SOuXd5uKev9QnYaVITu/jLI61Wkmpcsp\nYHhaVaSFaRUStXZIcYv3VNPkuxE2az0Z9VNN0Mi73rrXGMw4pp9YL65ByzJgP3fG97U38ltLHgKS\nn5Itl199gb7ZMl0lsAh83uPfA4iGuOv2sBn7g3pyREGWaEYieHfHKq+ju38etYApkb22FnsjfVD2\ni/YIM15a0/JUEGc64KHZASi8A4NiUntFmVDG7YkPNdOXQ5BqsqprUqtMd/b17Bm0nkxc8e426Me6\nUbOlAHlZce+4uAmZvy+E4ghu6RTfGS1y2gVO/RFbNEKDLQmvXGS0//UZVhj+TNSiInw25dxsDuCV\n6utZNSIb92gOGTuKghxb07yu8yXyZy9A4biLLqaVQU0vb/PW4EP049J7YYdO9sQwrJCoeFtVEaPf\nwo2nIVX6hOpH1aFEkrg9ERiPnt1UUXlgrQTkKdlkJvC5wQSP2ZNIRveY6jHSw1gVBWkr9k0daovZ\nz0G04BIfsbm+NtmkVJ7OoDEv4XuZ4Il00Ap9vBN8bSHNO/PsMj2JNKVH3v/Xx8eisuCdeN4Hu3Xs\nzsUtx0nJQggOIjEbi1WrdnD95V5yipfY1V/ZC5V7ii5zHDUDkP+p14NMbuE9sjfsL51Rfoty0wsl\n+MoLxpOr4NcXnX7QOWmy4aGdL8C3ZikuPP00WhtKRG4p6H6MkrAttXHz6L5wCnUV4O2kGfhkhYjf\n3yQJVii52aRvT7Lv6S/BAOJFByUGl4wpHoyfLS8dLrarEOyI1mnoeOsjefSUTMceLOKuPWkMk0I+\nLR/T838qusGpX/26srrf80SWxKr7ch0YEK9xGGHAO7cgvPQTlncT37QvLwfutO2xOZT+81H22NiZ\n13z31W0LurQciFfxyNz3bOQeKWnQHIqtFv3JGGJnux7/cOP614w/LW/aL7/YOzC8F0xM3YhaMeUW\n9UA+GBxyn9FtuQ0/g8hs0RhuccMBjsnxQzSBS603FlXaUQV2FfsfMLBL7TasPZ4rIHuUWTEu9mYL\nfWz2rZbpwwfRq35JbtQKwphJScZVbTaLWyH2Isjcm3GRFrOK9OpEZwYx/HTc9n/EtRmmZFwdUe4J\nlDnueKc/fDmoU4G3+Zw6rm3p3XTOo9DXUArS/uSnCylnmGrAaBLaKnFsQKd8kCmJX12Uj/xdyOF9\nOpIg19vrcrSE0ejJQ5dUcLrb3i0Rk8eLyGew8jmMMtFOBRmqVwscepGRMPG03RMp4W3rEJn8UXb1\neP5XFWhrxazaFOY5ljiIWHk9hYQOnH/Vt8DG01HUbQNcvQH1xHNwUIooc0fbM+PgxMn2hQ0pM6+c\n0wPfDIKABiNmKLhcHnljST+ofM0yPaynaEkePqVxWiKlmFSgAsBtBcerrFImky4wOHdJwOLvldx3\n4dVj6HduJgYtLUQGVl0tI3IbmvX6s0MKeONdhJKp69hWLHhEiYl/t1cPpLJB+SUFp/r1x1s+MzD+\ncKZW7hNtDThOdBJjoeAKmavGBoh4VHBtQqDP0lL+EwpSg25V6X9XW+dFUEpwaZ0CuVXWHBtwGuce\nMaku0HU9yyOJSHRk7R5AzoBM0QCbfNIwoEqrpTgUW78VzRjekms34MQvc6/VWtqoA6IIgPs8ybLJ\n1pXEw/utkcwR/tMBVJvyKzEp9b6Dc0sotuhEJRY553G31bb6xa7Y7PG38YByPiqfJPK4AuPhcaO4\nN8WILCcgXuWL93xjqu0/Ew6z+GNqQm3Jz4ntiHysc/AluO6K7vtwO4UcS8ccMt5z4bpA4T5arE4/\nb1eHDWK6JT2gX5/4lOlR7pJLy5qwKyffyaH/Nqz7AsCVsPZi3Qwvygy7NndJ5ubyVcHxyItssjGq\nDNBwkJOOVIQtsmfxXko9LsA2I6zOgj51rqOlqXg2Gk7DDJjUk66K8JUFHjHbyUHJoAgAJXbcvFfs\njDDBZ6zps82PHgzQSOWlueInlKXLUvswdqg8Szm9Rmfe07P0jivX7y1UdWGu42d2G9+SbnpVwkAY\nd1j6kvNq/oN/n3VLX3UuBoSfGik63mKL3qmADCS+UFhJpi4xHFbwZh7pqoTDSA81OoplAD6RtIk2\nxTHfTfakM+NDXKgW5LVuaFtBz+6XsG5LuuVK324YlMwuHsdtjt6EchzSz/yYaMPHCFdNxyRgcbqD\nSIm/1x9m9ypB7i8tHeuJrv5TiGMrS9fK/EjFDH9s0XHcvfmBsVMUNdJPggy2rEwjwRnqEXo66at/\nAfc7We4AA8PDP1d76rGrBczWskspbNfVGtzLYmsuK1aMAzAGE2VnjMJ/OJqy2qkF5qntyuXtWXp1\nXYYHmfMdE0HqigV/1OZ1p6fodgR3cMw7dqDD4xSvY3zej5zcUNWAw6yrxJEPGUhaUjPtNS7+r2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fRoNqOEwbphWrnFxpR1uQtlznt7NunmA/HAq9QD0jc3VCyUGLK1m9jzfR+MiOxGkvi40fGIh\no5q6cp6WZYQE5sG2u1HePNz260XW98o1SKmGAnVADmN9oRH+kJs27wjueapaewwDVg8pnq6kJUOh\njQd0RkYcTMItDGvp+sFqeIIdADsTHRvr1h+M+pYqq9sLbwUoz1Alak51hZNlSXhSEVXzQLkppmeO\ntB13Z6wglCy2BICINwlSr/7HP1cYop92mfeTXL3QGuFjsDOYJeT9Igcq+fS6YIfWCA08MY5r7yVk\nVPB84f/igRg5ddrxoxTIiw6w7GWDOhG+zTxF1zyp5jJA3yKcpqPzSQpf9MKcNt+PzeKm+wneK6Jo\nhpoN/97lq7oMjwcqj4fYDI3pT7J8WHKkZCIdUVNrv0PtjsuMpkuTQbOr8hbWLJNy8UKFlgHOcfrj\nOvGAARiIQRbgB0ehYmzYwrLOYCEEGz6BajWpYh+QjcQz68HI9uD0KJTeFrxECsQhCkd+nhXmR6Fd\nTuqTwMlfvUxKMpfl+zweX6F5NmHmeyPDY7Z3diHFdJVtYNhc+jcelDo1qmERGZj0HjhlAXvpn27V\nveZu3AVSpka5ElIwtvHc/TpRzjvbeQHF5yFv9E3VhZftw6+ajD4mjDYjGCqQeNasu/oomGN+bD06\nLx4hi4Wsc5ABDp9+84vB9wTN4vdXWfDxjG6e8iiMfWuezpQtLWJtxG2XnhaF3oXBpRIS2VVSE3h9\nz+2gpVoEZT3vzJjOS8nL57iPKloZn6rbf5gWqxxUAtYbGct7VUgqevGHgWDGl0dAqT8VpJaQ21q6\nFkr/uOy+vbpdI3AICEPSgGKQQMnk1kAfWxfgJ/kaxhZc4f5XlC0ZGSh+C2CWzhNE/JAksw0YQmsi\nne+rOYuBn6qvg4VY/SXyC6jNTUu4fEhiqCBJKvOpstSpQS2jYVyQK6GIEoOtvRL+AeqOwN4ylvak\nQVkg+2A6cwY7T1x3wkcNeZMXbEpORaOJMy9wXl09aJXky2uN9qgpXHXgPTZNWf+saMNRN+uBGVzs\nZjhjfEYYTVSnY0pqS+gpfbtlNOxXo7TL8OvbkRAThNpVfqwQtupoPNk2HHNbdmWP1tZGcqPsQf6c\nCPJwuj8fcPCQUh1HIZMnT9DYnr+Z1+9YVL/Rz7jLHyA2rFlsPXsEC9hUanPqMe7CAAEbjTq0PKon\n6vcDhC4OeDhfHkwfTiOS9fxMjBLTcaoTqPWTZt8ChH4gnVvPWfUBK7kvIhw+dKvaxIvX9bk/BH/Y\nB6uSJzU7imXZJLx07cEcU/6LrWAx6BrPF2/b6Su1t6eCb+t1Q3QZIS/1RXup1A8KEnaMO28WsZcw\nZQ5vCfX86ljiIl+HfGiLBpKoa7+SdP/+q0BolGpFDPCce56LZLDSOjBraFCS81FH07TgMpEW/Koe\n73WJ43JWWkZBQNZzN+JlfWtwo4qAocwsQJX0w6MOAIE+RO9Iwh1IPv1zbtcWHBpWy1yK1K+qVbiT\nkI8txebAMYWE1fJJdK/cP/tTZXiQLhiPzBsl9ezZjJsjAPcq3dbWErzH6ZEEnAKTv6PShy3Znw3q\nOT6++Nsz6N/njj6GqwN1E2zfnMNA9tFHXPkjpOfSbyTnzGEEZwPile3fiO38kzzHEjoAkb37KavT\no8WtZsohsnfTezPzzWxB9cFMtrTKv+u3cIIlr3mM8PZGdN2ZSq9ahQfTqRYp5KGtKnkkBIfsbqqM\n6M/SBVm5RMtrKRYp3/ey+lutDPtoUKLWJMnsv76her8S4uek1nzv4wTizdqJoCHy04vb5HAcgpVC\nfcWHgEVDqREje1ZKN9cggmiVpXRsjmWDBU/wAg8c14gohHPFlXNZgAA+ytO9js8szFDnt/0cCj7Z\nkDd0C21SAR1LHBI9KUf497LL8Tu6L6XEd7Tm3XEXeAS5OgHmGdAHyGPiqI9u8ClEt6BkfXamciI6\nlfeQj+z1nCxMPEJCjjzMwvV+3Ah7f/pMVMzaycr537MfD4P9+Ch+Y0vIsYpwt4zU/30BNXnQqfs7\n67i6Wfe/ptu3NRiQFhoPNGZytUbv/evSNDXxFaqwfruUEUqn0eUopvcwacq1XD9XaRIAXBGNpSoS\nKKesrN7Q6LZ+PG/cPTdT84w/+X0t954GdIewb65IP9dwf17eYtg2FQZyM5t0f3iNHe0pojKIaM1a\nmcTIJ8FIFYHoORq8DSEu6tyA3X53jjGyQRjVmLNIZdZSbRVoyoBsiZ36Zh4U4aW+U1leOK18co4C\nxLB2Om7MWuPJT3VKJMuG8psZ0iW9z0Zxrl1RyfZ9Lk3hYM0VRdpLKgxqEDiEeCVqfhlGlFXUj3wu\nacVLRH6dhSEBumjFuWq/lHbTsYfS2PGWkPdKedT/skbFeOsHLU4V1O84M8q9+qmppce19MSMwXeO\nQ2jn8v1qDqQoaq9r7Jvksqp/+A8wClhvUJmaqnTcDX+MLOJSbHG2ZNR/3PvUYpDVUrL6FwJJEASQ\nPfeLTPm7SGxsfS/ZVEf5pC70NwkE/6UEcyIx7xiVjxXhDxpA1pBvp9PRueOVwllHhE6dRkC/iGjc\nY8YKShjZxisO3URdOWXpt8F8PTMjnWoGzvbX4aIve+X5KKntuaYeQxKXCf8OJaSDgRc27KSBsG77\nFYG6/6BcH6AAXrtXc/OMZ5Hu9pwGsV20Zxo2xAGLOFRpmnHdImjGCwHmcTrhQpQH8Br0AYr8Dchr\nzb/JJoGRA3WukUlj+NanwbgVkpDoHAJD1a4ftoDvHJVleoDf867gupHQThJhVF6z8LcDtafpRVrE\nSHNxS9sSGI31+aTuQ/0YqhEiBI0k38xXFesQY1mW/zireb4cohUmw/0Nx4uTsUCRUE3WLfpwBeb4\nMp8qasvOM4Uf9kQqF+GnmseyoR8jF+xEaBjyzrsJ7WpU6EQqH7Cs2y+0nkw7vULcWZ7PtxCkTi+y\nl+KY1Ss3um8ryMQYGvKj7L2/zAzwrarkjBW4JAtWsM1SrwqZe6veUIqe3Z4G6jiNsQ4NTDb8oypf\nuYa8F3nzw3hTgsLTGVQU9pMPE08BjCvQKFqc57jBAj6RXHMnE3TWWc73XS/zYTiQ/OmvpnxjZ8lu\nvX+/r/dA5KdxINswaLmFPw3KzzuWJBz/nVwLRbAGp9IHQYa6bgjjJRm5ZmLKGmzzyuRrQXUPKOTn\ncopnuL/JvlWnSdn90TMc2Tzzm7TXaIcgX9EDepTRW4sN2XWdc4AmncQYlE3Pc3mjMKKgB95f5TEm\nSgoHGZwRKlzoBLvmO6GOz1aatdeR50BMPUt7pSJwIgfBdLnvzstov1W42zn7AgW7Su/pfCewVOQc\ntZ3KuOMYDHtAQmPMuM620hdwLoXkyIatvRSwpr0SFvGi6O8B6kQ+5QxGad7VgcpGZArl8TiH6QY8\nUrI26KJkzhP9OikTZ6om4ZAs0bloMAPotwByB7KXegEUUn/G7uE2JTlScgVp8fNt08IHyAO9ubEL\ndk6s6Dfr0H5HdXOKdMAGD3C2jl0fudKu4zYcx0s+KraQSQgLXI1G2qoLzPeW4fGtztn4k6iTlSBg\nRGAbX+gnK/iuGfb+++nrxTBI8qFUX6YIlcOAkg//OSKGJJjat28UHn7BITZnedR7Lf2K2lu2q4yM\nUFzK+WcQU2KYHp8iy1VQ7x84oZsD1hpSPIvo8xCeiXIPtrxEHjRh9OZp7jAHNkZxhB53ii81SHB/\njEzrBHa4MLE/6WMisOhbmjPDUtQLtgnO86q7gzdmJX0C1jvl0VzQx+0ISJcZc1limXckLBS3F+rI\nMi8MGBfMyw+BygdEr2f6yRlYvJdRZJhXOXmHT77UlUuCfmArP6UIswPKplZN7Q+XLflYU+I7OUPp\n3qMXyzrC5ko38DucoiwqvsXMSMVx3U4vLK9VKA3sPt/QP1E0S7tFJB6lDoYQbdTI/vUgNy3iAmmw\nLl5BmdtFBDWdwEMFan9pvoDEbzNfFkIUBGuzvnjKtAFBwA67RYWKtqglvto8q74Btd/PMxWugAs2\nRDrpHJWYNh1j5vrsdRj6sRpJRMQ9FpQRBFbz8fol8FWWJFG0S8M+zbG317tUs/p0GjHB+hTwItqR\nv15KlK1LZfgIy6o7gd1a/8MIRTXjAVUuVviJ68d44vkkJr3mh1OphI4SBhUhzOaf+44CoHK2dorL\n9MyTI6q2dacNJIgHdhaJF+ebOKOMQ0olKCeLvE1KmN4SbPr9dHBv/d7cupOKbz1XYMcK66m5e/El\nRWsYMbQf2uawzWEs8cZBm585waVMQtfAQNoE7/Rs2/2SY+vnUPguioY+EDwZsTxfJWkI8zHk2a9+\nrJrYuXiNAW4sd3i5EDq/+2Ak2GPpRmfpxb7u6NIBKlwXugW8ktrqwlNqYCtg5vVaseU+FGNiVsvF\nFIuNWu1U7GpZ8HtnZu6aFs7IBPIoYMl7vu3aDQpZG9I7sSkjhPjg7s+ijQIJ3BGlmyuljXClWhZL\nJIDVQLnzS1pM0pvibM+4youBOCPFCx3sFuvQJZk3DpKOy2HX8XmKOtbKgZHL2FBjFFosaGOqcL05\nIgcxAvuqHB/0PhosWC4fcQy9X0ohWgMLrtpWE8mEqH+l/idgHAn3azKZjNDZTlrOZEPh5Y71cZak\npKgDUjLW4WthFcIERr+HL9L9PI43LQ0EKDsQTa6UW3qJFAXgUMTYgZtO2S8RQB23wPZI6bncN69z\ncEU5z6OZdFP2CgLvdInA1tFbRhPanE7dmxgxqPwFREzFyPLMwVsw9YgzsxSxbhJODZvVY1Bp6C4e\nf8VmwXIAZt+OfsTInDC+dttMHHHCvtu8TBUbI+ZLgsD0HzsESIpV/BFvQsRAJyfHJ1Qu2kByntgu\nauKads6lHHGN1Tz23/hFq7PVfLwm2Rv+/yx5DUv8Uj7PLsaHqrCdZkVzr0ECfIwPFt7nW50xCqQK\nxMu8QoV4cuZFAJzIhqj5t05ByOQPFRcxOQEfZrShvvNR9GdpYtghDBF0fU7BDHiagP5xDQ+UrHtz\nka7nRo1FHnm5QoYRJoEBABCLmeYI2KoWtLqx/CHi30vFLoru7CkCPX2Ll5A5mIHnjWmu/VKJrgNa\ntThK/it4atG3Inp2n1vlkQJQNib7fEUdfuFjiiCQRuNtmJX+MqELiPQnVEY9VWHNKjBPREYUQKnP\nJkfsG+QfkgAOqxHLM6oCfy2FFrS9aHOTMK/+PdNJLxa769Vi1zeXV0kwzsjTsJp6LwEAdQ4xKPck\n5bRahBrDgSJfUTcQYR+fbWtE8OdbPM/FWuaIc9SEfNMEebsH/lUKGSB86OWHZNz4CMk5ebH3R5JV\n6DdoBjfP4Atab/RbwcQqnZG0UdOPbBy2c7wTzqK1i+/C1l3+nDVheGhizstvKZZdm6XehGdOgf90\nOPsGrNckYz2jn61FOH0PY9mFh1FLr+59tTVOFZ8+6G/JJcGGo8HJhb6b5sCjXHSsT78/4ldD51uE\nJDiwF+PKeYLd+bhW7XjkVvG7+LYAG5h34M4tD8XHnDUKzWkpzBJ97ZFr8lV/euLpwJ/XlVImBXwp\nwZCzDdGwiTrZC+ogqcsGqoZxLQ0lv7VhpBL8skkTAYlBc2XQufABCHG+gWEuy3TJvqodDuGo0iZz\nQzftJFbueGn7t2+s/eYkOYS6arOhlDNJX2nYR5xtrB1FbV8m+jaHEiJbQc7h1G4HB07HukZZp/9P\nLFvsRYJ6uqex6hCbbqMMHQGrId6QGSH6/q5SVMSgN2/gJFrr5scKkIFUDU79QyiUDCNwsC5hwA/Q\n52vnU3pPU6vXy2f5Q7ZwUWdsJFEI6O0jxqL+Ga7+MIwsqnVb4GlFZdjTH+jRLEyw039RgVDhgKFx\nliWSLpSVpJs1r/645DGyzIbsFE6cPjg38+CcoAWYla+Gp7OtVF5Aqtp7iC2fGffTn7TvJOPCsVjY\n5MHx5QGSiT/mOGO5OVGVbXQzgTu/3GVWMajEmAq7T3+Ddw+yw94k9rT6IDk1t3lnruZSEJTPTyok\nw+bsJPG7RO6DcD66Igd1WzLO5JiNwENjJVrvbbBMYTJCgVPc3hJvvFQvfkLiuZsa03mylgBXKHAX\ng1TT+hvmb6ZTIuNi6x63/487ZXtXCLFNhUfNlssg6Z7KCyDb+mOiA/8aaC12vb51w7SWXNrmZCWd\n7wJVMUngtcinyUXoTuPe67Tbwu7Y3zQ3ZBvKMzu/YFyR0SsSeD+/yJ1siLMoqudSse4aThJOdPbm\n/YEW/tF7aovwdtXP+40gIRqfPjqUfFDJzhIh5XTJx+5XI6b1ZNJdT1+zC9ZCv0wpUCNzcYDWP2v2\n+73X+DI2B9Hk+GQUz/uV+HUBxDiALLNqS2pBnu03BRN2K3Ae6udAdykdB3XrMGU3apddVfl2Qzxp\nIMqedE5qxJzRw+S8ghl7CQ/HLPmeR4VLqSCR+4vWCWIw/nWGOStxbAxslLYMvqSQqcOh9SyzCdy4\ns+S2RDRsuoiRadrTnFE9DK9AV7YVbx1TL/4UsryqKTyD6TZgb3LhhYOUcpIpv4eGF6c886m7YxCy\n2UDtdlk5mzEa450taWmN0KN6rx09qVH7bTyCrbrVUDBIPLqFlGt6zsHsfsvCJAI3c9lNyy/K4Csx\nnVy11QZ2mZmv5FNhUpC9/LR77nEsEfKmmY+ZvmK6ZHudJHG1/VfBI8FoBMT/fDIUDwW+BhOel/Mr\nViAUiihouIkWJnuBu1qd0eyhHAEwYLpl67lU9OZtC+Hw4nRKD7xL4yeaFxYMdBRfHT536DpZkC91\nDyLn1w51UXVeDMGmEk5w/suYHhiKKlsSF4c+HVkT4yWcG6HjE+nqeKji/CAw5c+5piMrQDdaQcJW\n3nb0iIj0gXRBN+Eotil3B7bIpwe2t+faDTQec05jrigHMr3ZgWGPMkTWRs4Qir553sMKABMSYkcR\nnG1bX1HCd5Umeid7Ko9w+QAO4nPsP5d0GRtDcIyTVJxEMoOOJPe6s5d3iX9a55AGR4JeQOBinV5c\nvQTaqc7NHTeR4spVOyNLX0Vt4r4xYeQPAv/7STKb3KraVueUbYH++IptBnYURSH+JYRUgLc3wOAY\nvaIiWiWgsMJN4S9Tj57MZ21MxkcOD4n+daasVl9bXICg5bV/qCKv8GLgLa75Lmkb/q5ZMWqIh9oE\nBXG7qwnhfQdr1GBfNX5e2CHlpmAsJSuPYxfplnTe9x7rmzk1saELs+J5Zod3BW8s9PqEOytiKyFp\nNgIyYxnpDHg3KfkpBCzAqsNwFrRhkG0cNj6GW0rXcjnK5XVsm5EJsIpUIuwUUCM9FS4M4tQvHqzr\n1S0Rwfa/ZmOL+3kwiLwUF5yWFKNs9N2uwmJT5wYI/8PK/4X7jfYBxLNFiM1d7/Ot/0CD2Ygqno20\nGjj8idQj+8zcvopFkqmlICXcCSsY1CN8ytSbrd2KnMUs733/3JrtKjQJchP9IvaMZn4C8GZRjQ6B\n2FQEh8t7rEVQECSOxQ4L5fKxi4VjvlFFV5om0bkmX9dxai9YM/IwxOrmiEVbScRlOGYie5dHSd5V\nk90VtMGSxisAx3kJM2aVn69wCxymu0VbpXmPT+80tJOSJSASfShtKF9vvaTCkQlfQzw6bL7yoPjh\nwEpRBVB8nS+srJxgzTpzxf6kWSrfKwaXXevwejax6otuoFF3YEUOCVQgG2aUWnXPnlQBNC9MPtAr\nmChzvfkMA49tIz4Ra/kpvwGya9myjGuIQ+DpHiMvJrcsopWNYHjXYldeCzHaIWvnSOHGMM7nBGD6\nboOM+PIpyOs0dw3ymADCy1T+tsTasU62qNcuquHRip5asAz3bozJHUulZhGOlVgRZUNdbA/meTnk\n/sjtLjzMLOoPyFtPJUmnUvTECUkmGukcIMhdEnWfA+OgOzrM61GTUK5bwGME8XNRsprWjCchp57f\nxii8cEiyhO9Nm1pmdrMnxiPCjIW2WSFsnp1BUNnQEWDbigo95ithoSdZejaydDJCNHQMVMB7BgbH\nJVUUva0f/ZGTwU3kz+FTzsT6PT+E2GNMZm6rzSz1Q3yNoH4OXUbJwQ/vRFtTpicFPDJoLzVZKQ8T\npYc5LFd897P0DLzZ8yT219GrhNpk8PgFDRC+bylWmXrFl+BbEfkaO9VEr+LIfaNoM8p0/YLHLo0l\nMrvk/FTzdn5XhFvxyS+Sky7a8fU9qLu5xKvwZGoA2MbCvP/9924WG5xmAmsvN7gJQ5JylMq+lFvT\n9vBEEkmXTi/zMkw0f9CycHzh0eBomR3kzWnpWRJ8aBj76yXKuWdrSZi8qbVdo8wh8eb5xoIV0ir3\nEqgdL7Zjn1IcBmqhcr3AfwkhQEaXeBA6hqImHgPIpyxviqMTA0xjkebO9YGuzZAUIa6uCCzR8XPj\nbYJjNkm+wZNwzr79+h2XV6wDs4JS8VDdZcAVCwvmjHY8WHHb0jZTF+cMbLcUDsGNXONUc06UzHa4\njGjOviVfcTwRaVwQs82CNgjt5OHwna+Fj+b2mGBEyENynvXGlAo4ECvuBzpI8LU+ABqJINwvANwS\n44b0GVEJNVekwlMSByybrdYq2Lca3a9BtZmGtoxI5vIDG8U8CGIe/HaNFpFIvuyGDgYAGr2eb2tc\nhbOnJu4LASxc2GdEl6I0f/Z0R7seDGa895BuyGGcT/HYktcCq70sTyk8r6H0klX8wc2w+1UT9sPp\n13PTlh3zLdvGFzKPfIx0Bovn0nIoViJ/W+tgIbtcCnPhaL4gh3QePzoLOGoIWzrZKrfXdQUkepGM\nnGqctZ3+0XpR/XS7seqRDlstOjCXkPam6oFji3lfLKqM8ABKgItNsWesmVaCeblTHDPu+zmR3Swj\n3XSa7hlf1r2EC1jqZ+oubGX9WZjOz1p0gsINsM9ZgUPOKlzt+VBwtUQGbtj29NqAdJ2m+hFTMnXL\nwnUTOLl4CkzQ/3PrqSxqEMLrVcMbDav1VqHyySeQ9SUXcPePCnXTp88Ns0q+RqrpL9STvlzfv43d\nQWoOfT+y5jzqBr99d34ltSn1jq5Mk5kfg331aVBVDGP8CPubrq/MjnUyQ2o2sw0VX2JfGMN2BjHw\nfFEQGRoV/qgnxP+Yg/hdQHYj+r8qrXledHrHiSIHvAPs4IQgUCb7GIaSaT8McI1pg/MxpBTzTrLO\nHedJ4drTUgQ0yZ/iYK1+QT4h4+42fAkQ1PTj0z825aLEk1E6e1O4mTyuokRi5lFL0i4Xo2nnJmcg\nY2HAeYmkS26cU2mggoFsRs/ZxkSkF1qMN7lvHplO+1XTHO0DVfLkBuhEnnqTZn8rhmPL7cnoZaUH\nZ+WcnLY2VJJpEsl14KAieVLy0ABlPd+RP5UZna1k+42P6i95rcEg3jt0xbOAbrd3GZ10GT4chHwX\nZCLWJjslyLcbPGL1XdWjgDMZ3dtfG0z3hucdHb6/ueD5YQwPMdQIir9TjhHok4WPalVXcz9OwrDv\nkkUDrWxC6S8tuOFRsk6jqShA+Nv1loaSF+IqNB9sfeSGW8EsyVZIuI1fnErGqbXf2i3DInx/KFau\nWTBKYaTk6krZM9fG1+OzTGuQ4ubpSMe6o30MtzdVl/db9M7hv27LYlU0miFi0OmEUVGOOZDK+gSW\nYVlr43tdFyGvXHSuVyUe8+IhswC9IOCUS+h418D19ZNCQT6af/VQDeVmfOTnnZpP6DOc5p+hPFvn\nn/ISPeLm5qeknJULbDWxnHSxTeKqsw6FsTlJo72ZuEd1zLdA0lJqNxSH7YKQEawd8S0tE50OyfKP\nJjTDQ09tW/9msny5f6YFRscHzIbThNRsbQX1saPn1Gu4rhrY5lijfWRBI18U06gYijFIC5rZDP01\nVBYwmOnQa+ODOGfcUiQmM5pZVc0/4xmoHedHdwn4afREXvUzDZpKM2ZwPhNdB/Bf1RFqcRr9sgEf\nIub20BMNkJYzK5VVtGRXanivzfdoCbqJo4V8P/5J/jpsiDuZrb6BRaaYsv6z0mpEcr4RDQLHVkHN\nuy/UCVRX4N5yYskMUYbh+yf9ItFGH9xiMcWEvuCIcyyyXxQdjN8M72SBJ7rSGqi/iT7lD6zS9rCt\nQ25SxFqFjyMFb3/PCyopcf+doCoAKth86socVbKc8wQxwpfsjnsmDg6VfStQW3j6HbTJRR6cBKWg\no4hq5QyH4OzFyrWlze3EVjvAIRNo80YsifUXn/YmjqXkqejTAMs5rvnQMXvCCx5iTbO8GIqe1ZIO\n6g9nf6cdH8rgKjU2irIjf8wuR6WdAKliC5HyFO8HHKQ+o6jDL3Gp3V28RPoZe/ggfrNdJXuljh2p\nxgmoX0sLC4F1b8ary0X9O5Uk4Rm6NbJpHEMhDyFLk1/DSblBMxjOyWf69ua/+JJBU1aCUg73Ef5C\nKAF+0i0bW7wQ+1F6T3OIrZADAm3G0/7kCMyEk/pFhEeiyRgxWwHJyu8Lq3uncIQ6F+BT7fiZp8Lb\nzeD7TYdel7zVmCJayJKdXAqYfe4tHf2ggNiRQtb6rW7zzuDWxC6j9MOehd+wYLkKuWxcheZiDDGY\nXoW8Dn3gDgb6qmAR+aoQ6SUd0NHC2KkR9FKyVg+bhUh+gryvAjrRb/wdpK17v8W0/2ConYAt5qvV\nSx9opD6CbxukzGkKByTs+VXu8lWI81F+WVfosuLsrM3FC7WwGAbBF9jP7DkjemdKvZgK9sQ7+E/w\nykL8i/agCWoq9h+u27h1mXU6LVJOUIupwTkiLc4gn+eMXDqL1Zs0XW4Ft6C5zRmojOAbLVdpcML9\ncO8kViI9Uir6g48iHpcD7UCRyJ9cYSxliNW/0Rb9paOHITEcA0vN+6M2stDiWjLaznLsiRPKqFdo\nrfGWs887UdLqjo8r5gfiIx3q6dJCU+McJNwPj2I3Jch/01qA1AnDeFImKz1P1Q3HCe1YUpwzVdVf\nPkhvqIK1pUei69jyfiI5P4YZY6+RsP2tTebP3EhStUcOU/D0JIBRQ3VQrJa7Jzg7XWISFhF95Ti7\n3z2sHCcTzbDUqq+3k6gp4LymdHgAeI7RRHTNZ1hM3gc+e2Uv7wdyHBjADM7L9XBxGBNcR4RN5X/O\nwHBTw2vsQLZ+ETCgA03rkxnuHqpDB0M1lN0U7rKFUSuPu3NDS4bkCedhAckj6irfUrxnUC0QgoTs\ntFKAHU4pGb6keU3Kg7myTPkUugg3IWlMW9CYcpswzcYlzxnplzkXmUsTb7yUni/FzJOxd2qE3yTt\nWQa9KaZrnpU1W5773WQ03FUrxVsCIZefTOPmIur8T7txGR8gnCqsv6QBEWRakWYYXlNDPF2o7A4r\ncVeo8ba3lyADQB+lGcry8YqZvA2wzuQ59Ct4i0KA9Mb2LF9KQ7bB1/9OTdfRZWE8PslluZPYlEzU\nGIiorzNfpWh8X4UZP3wT2l3N9GODYuwlA54ZzhLwHUMEGM/utYMeZ4VrLFEqJHjqnVqVqEm0obrN\nPZqP5mgXq3WGmC5pYfblJggRYFU1uHNmMHxPLzFUwLZgD7GeQfZGvj2C13G3y26TPQRTpuhDb35A\nvsAETZta7bv79C8GhKUuszAXdEQqSt1AoFC0iB1GHCSIayhEsCwyn0tZAjwF4K71go9RPoIkdhxL\nkDi3AoLRdpPebNp0ZkA9jEvHY5jXMLUERzVAQloyXoj2mtsRNxGVEfImCoMq2ZVf389ZlS6517uC\n4F4WcDbMyf0BmdD6i/dLuCSP+aCs2mm8HWSoppsZuy2SM+34/m/fZC3KiLWa61trhcRHNacVqLWM\nM1ySVSUKbL8qF/lX5NNiyWlQ/hIKgo5zbSVAjFIuGdhB47cwhr9qYQOyQP4KYaqkT8bOk0gV608H\n9Su7bdsKfB78LbLtQvLgcdNmpq12lLrtp9JGg/aWPRjjRaXmzfcImW6wBiDh0AY6WYpGq6NDGwpA\nhLfZGiij/5kgTLLcNTwUpioAt8QzoLhp2p84Ra3LcHOeoAkKE+yMQ4mK09MSzL3P8Ld3KD0QDPou\n1mkPSzbvEsAv4b6WlnAkHgE2C1liHlCCPEIbY9RLAAIFGGASnOKMf/JBTcFSO9khlVSyREctfL/+\n+2sm5V5I000OI6HLT4IQGxsyKIQvLst4SWJd8GdsMkxBNNQIYLCFd+M0FLfYVnhAzTiCmhTAdxgY\nRnLY7sYZmGyfqmehgJkb1ErB7sPfr8vyZ0Z0qTGm6pysX+dmnzDmfCExQjMKu2kaH/Jnkf/0K2QE\n0mcQe+kaAC78lUWAaER1hQxg/ftOI+igRhks1sWXY8MhssSIc7iGfYiaSX5yUYwzEYIHyeamk+D4\nBGZ+YPTRPzSmZn6JHsKxCpVHspJambLKzdn9L1iverJbe9RBJ67u0pDof6txNi6q6cx9UXuddpCI\nADEaNB0dJMRmsoCj/fzzaSGw17nmnS+BC3WaBGJJ0aCoAnc7XqxprYwTNjCwcfmnuTnz1ll4P6KP\nR+tCsMDxVPxLH/eOccJdv0WR697d04aU2f4TlS+gELkIjB7NOCRbsRGhdrgC41wGRaA+u+ADhUP7\nfgqEuPYH+Xlvsr5QZvd0mPJRtUhqeR2AuVxy+G+kreN/F08X6X8tMFL6Avnl939hF6Tg7+BCy/Kx\nsrsD7ivYDRBQnMEoH7qkapYrGwu2L/ehj7ukBgOh/3Ejp1E+c1s1tWHeKPFMNpF2yx01Jy+5AhDZ\nPSdTYZFa7GgCvLmaicDHdeUnz3cvuYB2rZDX7nVooQnhB8Rf+6UTzaLdWwGrNu6c81vDrNUZGidl\nQpQwK1Ec1ecQqUWRK/KRYcg6m1Ot+IeGKFnPa/63sxwZ9w5pVjXJPGPrKvbZa+Pia3+MyDaMUQhw\nBm7TiPETp8qNL5v2hc4ybZJ1/NoEc6gdnGO9J8VQT/rE0pdpllH9k8vOItKpkEd0jdM2GPJK7ZuN\ngT4VCNV6rhNPeauuN4NuXgK+v3g/K4wTktuiZM36cOktYWhuiMZu+ZjnMmX/A5QrpZY+t9Xt2bxy\nbHncUMvFL14jNC6856bBlk5GSJjHRntBzQZMCIPtVN/C7jb/kxC/Q7mQMrWGDUbmc86VpIqxeQJW\nzEbg6DHJt4qOKlU6bzOt8FHPe3nnL37FuSrsjXpMBPVMzU6CF7izUOh5UBzaFpu5fbh/g4VrqznQ\nSEQ5WlWoVXW4ZN/ojhEvPD67BMdowjFSWDwe9HlddgB5BC49PAYRBh+jjeP9WdnkJ6GMfTXpMvgJ\n26AvgS3NcETqckZHSEGXEL/OPVvIwi8nyhmM/7l2ITTs1PcfqQdiKkc+COW6I/hfYNUYQTh2Aifb\nDt5iI9OZplitDHVxotoP5baEwDpoUsYSWH4r+9DsqjnnDi7BzEOGahmcDVhlbI6rjq2uhPt+/p38\n+LkfOBeCYUg9lxYke403tx9nNLtpnFQ+qSkNG+pUBDWPYGdMnrduCCwJnxaR20CQJOegEZCtYDGD\n2Pz7oh3uP06B+ju74IrcowxofXDERrXjwd6aL2u1rgWhjNv/qvk3swUVmQ2VnYZVN2u1qvFFwOLo\n8xArvHTfDmfdrv+mnz6ewWhBNZHVrK6zR44f5wUhX3ohSyWzCmey+ygAmJrPygJtZw9dvtjXPfkP\nmq6gwA+UUZ2D/1HAOpktggmARU0cJShJJl/ZQbfEq82hZjpZo4tj2wQquzt3CtJJ1biCnMf7MQLu\nxD5o0THKOO7mjLvlVn1vM3tTUc4TgSqw79cpS2caat1pA6PVms/BbFd7QjoHad+W5Vxhj/3Wdva9\n+rbOmR2Hr8d3OazwSj7QDN+4RyMmE12o2q4Wn8ZIxoD3tJCCKuOhqSWPDKASZv/IkLTin6nfXule\nIs2eVAEvlNHa3yVruUydEwXXk81lM5Uw+tSdYhQuqPKwBTGysUzTYknJlqjnyiJoXPUd9YTrcDuh\nwFtFWGr8LHDBhe8GRsZMvaYVZ16IRpnWVDZXGMMXqJNZhBDZMowW7UiEdpYqEBpvKHYMG5ASHsOq\nH2eZFgW7h1wB2fWRp3zq+htPMYw1HPP+PNgsCtaRQubfV2+g8YN7JSdRuJVQRKB7HfbRlfal4MbO\nQob2YcOhWtM3Tkow+j+pMAfbns+amYldYEUnaKZZKXgICtzUe+8tc6c9xgVYa/sNKoIeW0nQBgNM\n4rCru5DDjI6BMNPTgpTdVNWaZG8SR5DzenlSrkXBFykWTQ4LjxfY9iSBnutE8jbzjzwPekKq0wC4\nGfTVpOKVUaTaZo5wkojWs42LwU+Fh2ieJ0FEh24ZgSmFkbiiKAU+zrc3dANLGSgsgvCfVs/nP9OU\nJ1hObUY9Wo98gIoZr3Gz0C18ojCwZEb/dDxvyJM56jypCZsl61dYEVTjoW4z8i9chA1Mzbxs9eCQ\nB/SAYWddeyQDiHx6tFAi0C5AhuE8RktZjQ2yt9UFiouVgJZ6wAl/my9J6gKj2Am8k7CzKhlfV9F/\nVXJXNDBDxuDiqSec9vv8heMTxQL2hvtaZRbS4Nm2UH6mj2L5VmngiqZpUahulzswui8rW1Y4Wnfs\nKRTh1jiCT3mA0NfnDcq01KTgR38nkQ32gdQ42NUQGHAie8oiq3p6WSea/2JzXYXpKZb+cH45ODro\ndyUi4j/yaktRND+QJjGGrC4CC8qT5iwirtXKo9X67CllayE6G25mEe9A+huiY0thk+QYib0Lmnk1\nc5S1eJxEg6Gq0HMfuOIW8ogQTs++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qvZJ+ZCMnS4whysx+BCN7ma6YkyIFNzyLTBKHcjS\nE4yr0tuw3kDPz5v78ORBOVhPwizhH/dYdZV6B4mpONFDbGpxkNkVK9fLeTarpzCabmO1Cn4BjkIp\niiT9kovJnycvCa/1N5GHTOyUxMQ7cIlR8GyuJ9G9vjXMwxgt/iu6Nhs8Xf3iefAXLo2vTG778wZG\niKCTTviNxG6RCk8eWCflhdYo1C27j+Rqirx/r19s5oysIyqAS+9JIvOVLIg8jHsKyFqJoA/bNCFW\n0Ygrq/HNoWa48zWRfKr+os8ajBpjXRLOUeJhAxUEyFZWwKTJX5nTylPs+PHtuQ1bmgj4YfnGYxvl\nKvPBm/3LmGttISWgPjv3bic5rgM/YbQJWlKrDbIbTkJM9dGIVqw26kNaoKEGhqo5MGof42C6lrXE\nqRv3QktEZnMKBxdGhro9rM+0/4QV+aqX1Mk8X2EShfFeGJrur3mnwzkou97INnrS+JcpT7To5jQU\n8Ig/dgCx60pkXDh9dcoI+//AXBmIMTNEgpsdZ6wXK8vuSIKnMPcr0ID+Ztxy3w8MRNBtswnCnLsp\nhBP2QoArHvrGmhDZjvRiFpzhslgdPyiMeHyaQCICXKOF55QZ6sa+C9DkTJugfp2EZQIga5LrSTc6\n3rppuK6lJ1j1+cYnKipG2R5TcJtZYEWShSakYrnc7XPyQej0Wmb8qjCXO+hZmkIwnMTyoiWGBcYM\n09bc7DVHXvI+nlwPUh2GB0OIBveYyuUVzALBfiNkLkfMZ4Rqt8xNNMrsmVGziDMhoQ6nUl57Io/e\nlClBb+8fioCu5h7vDGc2/iMQLvtjWVYutiTPp36vtvUG/FoMa5MrJ6s5MCEAqI85DRmzUcebGP4v\na/K9n6bF6KBPBtScqz8oZlfhCGDyFCldXyqteMR6RZyV1yKKAXiBunsqmukS0xXpk/0BUbHgCbDd\nWWxClazeNUXUabl4DDzfN82FipbyFe8ShlLA80QBEES3Qp/u2bRb2cx+nnqcV48ReQsr4Pi9H68u\nY4jtp/sti345Av+WI96CPNYanltsmSKatJe4mN4X04++5oxfI0B2IOB6ZrHLPPB4LAPKz8/FiqsA\nKrIeX7V6Rw3X6sqlox+6PvJcpK/xrO7wCPcz33aZT87UVbK+rFka1xcQL+8T0yUDvGoKsX+1SygW\nWOu5fA6jInKD1e6gct0HWVj85CMVGApFoaCYCY+wKsvxUnJpbYgdRUMDayFyYOcSvPcuWrlc30NT\nzHXrPRalxD56Ym6Q3gTiEtvwj8PegDnb7EtcZ0uwjK8OCt/U3HrmFEscrH8i1q6alcAPKtq9WK1B\n0nwlZSUaYz+DnXD+fdlzQl4B6DGP+z65+kJ23NNlQ3O4FBsE3CVPVS1jInQYFN1R/MZ/NDsNKcT2\n/9HOVf54MFx4y4KYpD12c6rt3mrL03cr0AqQpOjfGPOzxZAOsxsGx5pydhpitDOsT+YLpdDok65f\neaRNQOciBmskv3OvgyoedBPWUtssp4dZRWivjakHQ4nyzSB6LPBzdHKugKM7Hiagzp3TqwoBg03e\nocqaUwsmLbrrweIw/zClSv0Ybb4PA11ZEnYLUTtBEF5Nvzl7ygkiFthizCzrS7TZkkJYYB8ltUUs\nzcOKgYFoNkTomQdhNHo3sWyNjhqeCijCSV/5+PllquArtqQuzLrMaQkCdQ68163mfRWsbzKIUbuY\nLAM/FnMX8/HTvqZl8gSN1yOdYrn5yUM00CeA+ShEd2TiKPWygLaUZ2MTv1YbNQJTZJRT/XYKjJQ3\nPCmoXiiSpSvl1Xh8mrDaeqZI/CR5Xo+7ItoX/fwwHs9nhipM6AOPthpsCJGNSpl95Qd3V7BZ53FL\nDAc0aOuivhvZCafQo2FPwjV+wmeEEBvTX8fZ0KYdJ9juXbCU83XRxu37KZxX6UieHu5H9sDi3v7y\nlMOmlu+PZvNPh0YPNzUXb89xjhl/XkrP5GQB/Puv9O3TAheVV2l4vi/GbfC93y/h1eLsSzkIHVAq\nDQKexnt5GJrnKmPCE0z6exBRrNPLJRxivLXsgEfcNg40OJAxbtsiL57zWkswvcdymPifzKbue5b1\na+sAZQZNc0yCKa5H8zy5gqK2epyicY483zdRS/BDHGdi+H2zwcOinQEbWt1uv6iKjOin15tbfsvv\n7PidT58wPRvkJKx9xaeJApmPB0x/z/UQwCGQCSp2PriFN8Yqv3vrUlA2A97FbW8rAoNtU8l1PgPm\n67G92DFxvYzMsjrFLicOXoAq0jWkESzbR0DKPmaZKkIShNKFlJigWGDVNPpMox1bNvDMH5J7LPZ4\n1wWixDY/ZS16rUbmxHdvfir1t89trPgVxF4jXaQcsnokQwDLQjjj41WUeZR80CcrJ927rx+f7tHr\npWhF31kQEDHgBvQBT8/POvhWv4f/mAfNwYSWylKvRAH6+sPoo361/wxXsq2q8Tc5m36wCxhyKS9L\ng2Wgjd/tDIGqlKNVTMaROSrU8YX9sZDpIJp9sMvnO4p818XDslDKxx1yNDIG/WxWuS+1SajgzUpe\nihK4Q6cnKrw22SD76yZE7Q4vtl4EwPNAisrd1ooqjIpsbW62kz7zPQFK0I6otG0rwwZ5YidX8FCa\no5M3MgSB+gDNka6ulGapZFd0IpvK4uRo+QQMULNO7QIM29KsTg27G6vFaAOPAjJm9gt+1WYOE1XS\nnw9EOd13mvBVZ+t4t+TY7SwE8ThnyRJ1gZ2L7Sg//93GTdbdEDlFiPnIzARxJzBudVU+3QEXE/RH\nNCnfuh3DaThukZSnjIEG3hNae1YBonjqFdbQfd47oOPybmPm9X1U+mKxmuPF5OQ/GuNe8oxKnu5C\nWdufrxecSlWnGMusxb7gbzcFE7dDL/grNTD9vQ/JPVDYfXmsBbGUZm9unK3Vun0XjadGgvRH+rfy\nC65jgpDIrKeWZr+oQW6dRLHBuYKMAbwSJE3BoT55PXuOH/dL/QvfZN4kgnFmo1yI9wgh1SSvF0Xz\nHrdg1nZp0NStwjiZURc8+UtEyOO3lNFjC8djdRtJDYf44YQZjyDZQtd7jdIl+TXJD/GcWnzhynwN\nTGmG+RFMk81Hr42hNMuaghElfpVbtIJnJMYlvmxT72ptojCXy7hczYP5vFEW0g++4dz7DZyk0sNM\nUJimDy3CDpgimqEq+KtxF0vMeWWTt+pWI2pAwsd4GfxrDcn/8ApWymuXE2ev6QGhkHLWwvVP0jHX\nwQjnUKDfHwhhe5WrWbCdPHGiDLEZ0ad9baM8ZWRhoilq81aalMGswIzIEzluihzHoobJ/nwjm24+\n9Gr7OS80DeyNDBc0+dtxoCu7ro+OWvfxl7myvwwnvq+AfPzWUcPNnI0K6xgIVpngiSqcjaGVFudV\nQrunp8i+ykRRyNhN+sH7p1Z5bWV0RI++6WWCOO55zp3fINIipPizzRWzQaq4pS415l+BVYgFiF/y\neQPnEFN0XhL4MlRRZQ2C5cVkej4hQJoTFbXMCCGzCos+M/6WVnK0RgBYp1uK0hcpwPz5yEeRb5Zg\nYLbRBoqhm8M5Gc2PfSRW5LWeT1NVikspCC+zO0c+2XEcl74GBIM/Os7d2YPYnQIwphJ6tcGd6kJ/\n6zwtKae0LKo2p4X8J2/LXPKxhHToHjnZheRJN+Ws7bhWQb0awbS4RjoAgxQQ4Uq0atWMLjk0ui5J\nO6HXgVWzY+jzCoh6shHixW1+BvGwxUy/Iy+iUwU9AYeG5W9S4ZMOP0FKCDu/DhHOWn6AHJxhRDbJ\ngZsCnwtrzo1teetnUOZfEc2eqto9SeuZxuHeofUJRFiimCVDXSer9XnIc94XzK3r5aGLtlQdVqXE\nrXR58StHCXah+7I2Igw+8Yp918fUg5/ARHntXb2ToyiogzGS7wLlx0ZRPZ777PmBHNwDGr5D22uW\nEylrVhpmlgJfARtHEke46DXR+vcLzW1K1Z5GSyvnOQVOYaPE/VSF0chC1L8aXm8TykNWOsqqFHqa\nizB9aKBGwoBrzzLirm6b4zIbDOMD4bBsmTTVjn51LN57+7gUwWR0hF6KmUNuGDDJsPb12o5jdpC5\nhuzsXk/+le5CG90IcxAN1aL0w6s36e8xoDnShTDihHvu9Npu2hMrXXYIAc28kSLww2HdK5Yi3BgN\ne1zSyMky4ACs+RnGYvWHmP0lN59X/+mLcZRnObeYLRKpAzRrSNi72f7AU7LpdsxxQAQ6q6jKYEs+\nA5fhmyuUW3G+AaF52mpaRE1OJ+YKw/qLj4R7boI5jZ5P40Z1K1fVRCenPEFX6IEb2NcOlgNjLNCf\nfiMF5mYFGz0eamcRhM0RItlZkWNJe2Iakazklay7mW/V42pensipU39nBMx5fq8myPltRu6F3AH9\n+zWDsJpDTn4bTYZXpOwTmtNiSm9XnTZbviehgqe0OHUHFby+i0XtJmTqoqQHlJSEt7vJuZX643wx\nqEnZrxMcCR6p6psZwcxMv3qfVsMQtWp4UB4w5T1OGtxY5ACFqjDFli1CChYwcHDdP+LnMOWoJReb\nmrJPq1Yp98ZTUpmEAeIU9CCgfbLLa9oyCcHfVa6Lm2ZT33E/eeFer0L+PPV8hloIiWXjWvjIyKjx\nInZpJy47H011IlrofI5xNkU7Pun5+/cabxuuL6bFc7Di6dNJwwgrU/FBcutPz6mUQ9ATroMac7OG\nn8xMFAdWEXH05T4KcdPP1Yo4jKE77NYu1JOtTxbSKIciRZGFBKUXwkMfmkVSrio/6ZvPUSO1ATxm\nD8rndadTmvy5U4N4uwE0LDNlbzRBrQEpJQV8kX6Yi3njGLHUes0x6NIgE2ou0eMnsNiXggENmqbR\nXq/UGbY0yHLg5mnmEXQX2aJu2kj73Jqxnf1ie9QhkqxPTt9hDIcb5/xqpdnlQQCfdmXPz5BAHuMy\nyTpHpGLeAp7Q2VyDM+6T/k4QWVtnnQd4yR9oJFdO5c1caLTt5T+W1wBwgGhKtmqYsdb3dfnfuI7P\nnccUl9cC0cLt8jOVnbVVklyrsryIvWClOEhTSaOwmmsU7sQsFBPLDRswYednMSaz3Fr/ldTHIH/l\nRNf/5rPL/sepbycc1cnYhL4lMI8PuuF3TpikP5aV822eIq/itmBp5FeWOFTlsPpExv6FN1KtextJ\nlm8ikFNPEI/rvndxBE+5kqTA7Ut7SiK5OwIWlDxbFKX8GwaSkh6gxecLTN8/DjhU2R/uuTAZgWRY\nAHughyKHd4V4LKBLK/VNlu6xGLmu2RPpAlV5t32adrb9OdBS2BSqwHc34tYnzT8F5JnIiYqdjlX0\nCFtcql4nv5ea9dSEaTZm1TWJIl8yJanGq4vbxLknl/vgtBrCc9OF/ENyqUhEop4c45UYDpCLaAvO\nCDU+eJ9/5Q8DxVE9cht55IaKxVEhUAQjahx0UMIc9zzQWo36xPFw6efhpXmCPHzDgY3CirPIST9U\nZtJNO7hsvkRXUi6UF9k3SMoQHugIltuGT4oaN2ie8q4hWQAAFlHDbeNSIO/OzTZJFwRltUzW+eP2\nL6SjbIXFBbYeeGDutFw6WZHmhNTePMBDL/YWxwEDjtq1fD6ZOZYfWHxo5Sbrj5h3AKqAvjfooQdZ\nNXZ/UI5HRrK8LkB3d3OS7+8QedJy0l0hBuNdKW/9ZSV6v/aPaq73P5Hsxwub6HppOTdpuhc79mGQ\n/BL9pDmndVUjWyHcgyNkt+zcO9z6QD7PVAuNSZyCb2mI+Bff5GXfNbfpDPMpONpx7ky9z2+yr1dc\nXauIT4xqFGOXmBIPXbiJqIdb7ZHM9Gi3/k+4PBHgUknBatmkDJ5eecnrjZ26gwas6Oe5lVS5KLOg\nGqXTIVVFFpiYzK3ljzoiT0yeBqaJNI4pbjLfcboRyIF8VIWqoO2IfYdEhoC3o+i0Yl3keAXcLh+S\n/AXycHMCysu/X788u4qjRxfaxD0xjZGm9dunBZOgWm/yfFpUUIZE2ozu5nF8DUaEFp6vXVjSE7OC\n02fb7LzkwSuroCbayLt++NlPwDysNXHq0BbIC8BUW+7COg9Qq2NB2AUh03NHpEWm1uBZuBVXJxoI\naKTHQ3t6wWxYxXNg6z4TLgc170rTOlgGGp3YovVUcjXTRTHomEB78mYyHPLuCRrYEW2NQ4J0urgJ\nnzWCUwF0042xITA7DBxUAmoH41LK8eL/DYk2qg61L3MJAJUX3AAr98caLhagCUn01UX6enPIKQb5\nnWUVB56bgpQYcLifI2EwlpY7hK7HFeWXrHyhTZQnGd0p8gRSS8KuVRpyH7z0GeetQ/+myE/r3aOY\n9plLEK6QPf+vNoK30hqRzbsnu3cys/K1TggUEVmS4N2c7i7OcTTRe7S/VDkSc8ZgoQXnOpJVTsiN\n1v+5FUfsmi12db2BlUXAtUM9Iz+r/XxaciAzOgFgFHQfl+exQV34Ney9FwNtVJpwXFa0q4nIfts2\nekxTFNLzEAyhDYtgVffuOl4VnPF9BSHN6y508ESUrPdBJwXfHzV+jflurF1MCqX8G80p9xDud75a\nmnGZPak1w+6EfxPOhAgPm+NonRFVRM0ki3B3HZW5HKs0HGPiLl9Q3ZQP/fUlfHDCeKbvT0xWPKXU\nXXgxtu1ZNmEvyud/3jvhFDfmjh6AaCKi2XXMsh1BkT2a87E56X0VGZmscW8gdPzx2UvCqsOa67y6\nnIiWH+wTfx7jzcaZEY9tJhBxicXzVAkpbL7hh2Do2hGc83L4n+tKZ6IN2tq1FXxdUJmkVh2cLX2z\n/Jn1ixyJ9VdzWIdzkFKwLsA2QD7ns7QMs/dl8UMxO/RtjKahl4TZl8BTyQfFd3sQLIlQECEzfKX6\nJDKfd6WAXaTYDedLRVf4TCuwjx1rLab5XU4zhO8Q1Yku2qeKD+hth7Spsn+0i5ocMLoBSiCTpZ9h\nXn8ds3geBGqt2SPd4eyMefSzBIGx/Q00rnMIHHUVN3jQ2oxmAbAOTgsqd5GgrLdsLwRQrwpBZqsK\n3J6LAW5bFThJ8G66/rlxbFInnGCQ4yXlpbHslAgsDBcmk0nHvM9oG/RmlySbKcQ2zAlOxVrA2hGf\n+SWPpsoPahzsXFFJuAXtHzIM78ErCC2jCojJaoej3YR63BqdghIaE9nFiYcVBQmNBJCybtRZJT2N\nB2pPbfAVXCbVS9SFGQyAmmyOtB4sgXG4LYaMSgLYWttbh+Bq9gGUJaYRur19ZmwEqYUAWu4ACyAs\nHTjhc602LAuPwH9ZGwCO3EbfbFMT0AyaCqY0u6qW2OIOhNDjGVMooNmLyj2RZEuzlJcNNDOs9GYv\nKNrrEuZXcqkjZ5v0MjIkm8CXX9EpU/pslZMYmIYHuxUFOD4ZCC5htF4KHvR64VAfy8eJZnjElbQb\n+h9ZFi918azIWgSoWm5mPnDYXQUQhA37JFZMdLrBGVWd5J5zhrnOeweKYUsJOVz2UhrKIOZWpNV4\n1XboWeIC39bRJQh4+9g8KY8keLAK6avgMPrp9Y3+RV+gzucUzb8S14/b4UsFcVv0FLDeJr1qeYnn\n77ASlZSJ8MZZlEy5PH5iLp8xF4/Jcib7bXU0DgSOHqppPU01FWFAAFQ3pdS2vIaSH0ON07RDG9Qy\nDmlmF/n7ek/vZIjfOXU55wrDl0II6bocsUVBvIqMki5b5JqGzm28HY5AGgN+nNIEw+N1n4gzKNGR\ndOIN9g7gMcmFTls5wuBWvWHP8awlMGRvasNMXrgM1HkIis+Dm8TQAJ4eRFgDj9Iogn6wvT+qgShM\np1iCgj70yAabS6Ohq3JZtCernQSX13/S92WHEVe0YKTT0mH6HSdoodhQctB3XY4D0iiNZJpC8zqB\nHlnlP/RZft0zTU+v2hmkGePJb2ia/jfiGu20DZd6WM+8Q6cifUTUwureuHURzyZsx5zyUb9WAekK\nRW1xl21z+xTacEK2L8qi3EdLgEsZXUzhvr27O1QV+uIuL/V+/YLdwleK2RAqn5ROW42Y3Q56r/dV\ngawH4Wl0ANU6S2JwbGBais2O+2nLVwhLQriUcyYNXhuWc+7xPwsAyHw2R9M6vb3Kkdg4Wcfk21NJ\nMyVY6REt/UBtqkC/hYVNoE5n2qhGSpoRWVQQFCkbew8WzBWOZdyzmISJQDyy3b3BA237ujhb/uJR\nzRuzsGaaKnA/cog1unB1GU2VUljglPDy7n3Hesx5xosdn/gxURO79XFk5S/jzWaPBJuvpenaFFxr\nyESg/K2qR0dEvEDJihX+2a/GkpGghU+ZhezhnC/mapM0ykkmzBxUwUrSc/IMUWmpZCpVJrNLVYOF\nnJSPS3KIxdL1diiYh64ICDSHr9i7pqKueTjsEK67qlhAIYCk6xXck4I5C2kRjRThjv2EHQxOR5dX\nVe8XbzrBwIiyJvvCxm3g5+EPCt0b6EwYALvCH8WAZ91lCtTCFqomRB6/dUS23DP+Sx0y/QYdr15T\nRZTWH8LGyO1E1W08SYbUFZtMUnNPzcykFRMCYI1IUWLBJXMMPtiTWlyEltXCCL3kMn0AIwnYyFvJ\nn7SxCiA1qUsD7CWrhRpOU49dneEphwxJeNyz9bOUGxcuqUwJbnum1eH7rAtSANIQtNZaBQ2Ke6oJ\nlzJdhJE12MRV65B4Nsd2fZWUUTBQM2uXE1k3NQPO3xQ7bngSv1sJ5so2zKPo7iMSdH626ljtmqmQ\n4K6QlEtlWL0ryLMVOe8ywCbeCs0+KF6DlQTPjvaRIFgSf+/XUxGSNDAP67Ww6HJGJvhnJeA/bOtW\nkC1vPFANG0f0HbgdV/VGUIEMPfTvVWQI5mO8xP2mooXHRsBUytHDx6Xaqc/F56+ERQd3bsJ0U05A\nGY73sBTAXcfT80bail6td4LXnB6q0mGIcoRpavQcXpT/crKmwSJau6UOwwVeuKIBtvh72mAKOXFI\nD4jy7sk43ZbMnS+4o8p4lneUY8fHwRlAYDs1OFhi5nvGUjqRfrW4W7D6NjF/ao2Q+RWVwZYgPhmu\nc/QpJsPsoyTZyPYiSI6X5gQQRwgy6PujvtJR2cllkLm0y2X4BnRNbQthFy2DGmlXwV9jKpwHwCkQ\nNUudN5MZ7wkx/S9/gtj2iaAZzFSlyGE83QahJLMkTHh99PnViB1VScVdloR0E/9zj6HyijTBtz5c\nTvpFgdEm1VltojHW0yR3KPsfXBPNvV3qxZGcine3CYB38XNAoOpwQ+m9KiaMjpS+Z3g5jVSvEPRz\nI6Swyc2GHSslRqysHLDmqIFkPYMglv6rb3SP4MPqxcHdDQ42D2QUrIg5QGSsCFVKWYNzuMHNS7MG\n0q9S/CRSYZI6pd+BdxF7QMfYvTxG/z7SX1Y4He65yVsu0BUGxVAycgESC0yqDb/mPS5gu8ICCL/U\nKFYEMO8VavxBguJHpSOZqgfn9uQPdQKICYTyk3gkYwquOIgMeAzUERFY9rDolU/bFQBcrEE04bCl\nGbT1w4HHb2SwKQtCKUFOU/iz1/RQhSELBLKUUWiylPcK8ah60oQCSYEw5Fp/BmjNb6AtVYKSP5lu\n5OCzixPZqSYs/qpGhwGoFduI5ihI6wWRCEmtDWr4fn/VaQEIhnrCOaWyCB7dopkGrzthw/KTqugv\naPwLPvra19o4S7x9snvKUE38ohqiZ3jxQqQhD1jzOVB2BL5T2OlqTN20EzxkwlLulKoNVmKAloLu\nK81FvAwebD4TJBam7Dj09uvH7Vc4ovQsnweC5ZGwKQHDr5l+KYUTpuzAV56b1L4mWVv9KC1AuoWR\n1+u1AypMa7rfYuU8J/YBsH3L2l90hyykLH38XhVxAMQfE+rppwXmCK50Opvfu+3464I40J41o3/U\n2ukQgp2CV4cEALbpyBdHPBeTVEsGU7XgzZjhL8ywTq2g0uOMdr/GUHvajFz5WmKBD1Kn2/A48CSp\nNOF7aTFa1MO+YxEGpsbEGFzGwB/8DZSAS44NI2IJwsH+Pqdb5mDPEp99GepNImg4ax3xuQ5/fmM1\niCvyST6YzO9vDztRrx6DVty4yCz18qh/CBLLq2VO5mQjtLwx3EEoU5WRzivutrc7rYh7fYKPzW6u\ncMCbmpHfD4KjmtbzdCp0jbtSJ702e3alBxvL3fNxgtubgy1qwi8RdognRQaW3lJmodwMVdrO7qL2\nATWjJoDQ7N1vlYlF7a5JdHlqQdFmmyEZOcyxul/lb+66+qwRWiA+s/AxFe3OmsWkfQrkzcrm3bBM\nYCgq7RiGK/Nyg5CqZcFt6sIPEbjDril9Rk9eyfW6+rg2ti5qirauu6GTi89nmG90XFTqbWa2INSi\nu/+J87FDqz6mNQjHTpylfV+unw/2zp2uejZSOmCYg6slgJ5VzEmbLA/loWbbF169Jss2HKsqkJU1\nFDucH9pO1HhVVLLAgvzdWWSWVqHggZ7fdGPKKbND/q0DJS/MlSC4K9wc4d+a7LVqf7YfcArWJBSw\nb/CDJopZa8X7vfppRshZdLKB65dkiC71qdw45IYggV30dDfgL4Y6lqB0d83MFZ2fWmFGA1k+6opi\nCCFPqhmIsVyJwa8YQWio6rNR1n3Kf+cb5LMmmvDH08KeKeBi94wzMkfx8HbU3C4pNA3tFI8HU5lu\n2zYjSejh21ePxj8+f7hNOWHj53eIVwlGFJbeHtuOPKRCUR0ofAhhjWRTTqd91EmVEEKVQGqTsv+X\n0Ofoh1RZyKvBRJFf2qKEDx5HrHBNDup38TtEIQw5seyIR2VVWs7VfqMlt1PMiNCEK5djB6+o6Vq/\nPx0LnlJneHZ4aPg+7Jdx1UYG072d4qEzCB1Xqg37CLd3Y+xHDV+7QDYT75oX/2vO/RsHH8+4CwRy\nrw0knqI4mwfuKMWauSJU5fNvt6owB+BumMxKi6CJn8q/Ahp/Qkye13tRKneKn9RIxeKkXX4bdp3U\nPOdPMfTsdf5FfIIT9fsBZk1q+DN584O8YXhQ/vwoYlxkO03yFQy0t+v98xYVtoBWsnIGcVXZNaGl\nFp1BakMoraD+DIttVaUf0wB36pUfnDLTDvuHLmpgk2XG1LmVRvfdZ52WboncKChN3klluk0pt/AS\nKBTVmhloAwycTXnHnam5GBIjPwPDtu4qEf+m1DyGAo4egZXTy/t8J7tOICSHhwa0V4icen50x4mi\nF+80cHQS+r6jwF0I6P1+0waqv711ZoZ9e8OEeCKtD9cg3UxIbQHJ//qPhG5GqYQ79nNCUcxL0COr\nSihjFJOyM1HcroFKCiJuOCu56NDvE64S/ohFW/8B1RyBPYqcsGOHDusP3PPujuXmd9wra9whktlS\nDiBxU69cPygcHZGCAXvFCc6/4qczdg5RBWeH+cTSnEQ+LQqWVNL4KQSshKyGpjX1CQtCARE3/khz\no0pMSYSst5xKLVspDiAYAYwmHaMhq30l8dct7s5EfvE3vTEOpYsUgzkK5FnMpTMQm080koGudP7x\nS04xhfKQ6LW4wSxG0WxmHIr3hmuVc9tsRFZ9T1mIH5KgBBhi7XEvYeFSvhdw5utdWBc9yE1bV/IJ\n0vrEHBdEJQQ1jC3JHiDeNsWkxk/8VV3v1QMAB8N793KXxgQ/1jEoCwo4r+DgCws300qN53E2O69u\nJKMVjejhty9xQp2+lHRIZ36dvXnVTUpvw4PjnRr6nvdxbkar40A1xSTwZtOv035brN6W7IDeKByR\n9CV6S2CH6CocTKT9Zt8vPpltk8xGtfZvL6iP8+E7DEyTKpJNSbto6tPn78lb2k5J+EbZgbkvLq8M\nTagu9wcsOPFmD6zm8ytmIjLDQnJX7Ly06AkqKfoEgCv/RX3sJDmhLxuUrYN2P/XZyZEXHtLmfjYB\nsIWtLwccXsmc3oVsi2Pq7OJa6yyIdyX0Vag1r3cBSfGMXuhqSEbsGPpHGQAb1bemX6ZL+eaRR8Ir\n/eZQNuhoWG52LpqKtzgzdwYD4dXnawZEgrqPm6go4nMxHajMMT9x+EPRWMRCblVLMU1luSH9kaS8\nMkIoiifAeNimveh9mQ9+m9uCae7DWwiSrDtGe5S0aFDcbg5demK9BS6oJ2C3dBToRiv6isyitqJ1\nK4hru5Lh0iC4ja53Qd1Vl1IsNzYAQ9eEtiubhzCW0UnxLC9l1YlHe0Okqfplx0X85fEe2NfClZkN\nMVvns0Q6cI1RCZoehNR7MEbMUb9sf+YE/zd78entJAGGQcMvgDqc8GPH3Ph5iq6REzmUCizdjv0I\nQuRHIwhl2tSwe3c7oALp7AMb0UEUcEEa7yNBMnSZAwJHxxIcLHifNZnM03He4c7JsB4yGdsZlDmm\nzZoBCJNcbpyRnlvDk7moNefE4BJO/fNaReEAiICWIlZxQA9zDxlf0qEz2FZgadqLiPvXKd0SRjA4\n6iDTL+0XdstQT0EMQUdeOAiDZ+gMhw8gXB9TUZ2KzJmzbfZUOKnt4Dk3S7ZP5reZ67wa9T0Iow/r\nK6VXvm9MDYeTLJlHKJb26IFas/UWABGe7CEM3RCFR5ryVylbEh2frp60MtSfC0mHZIPj4PZVdoNI\nNiG8ls6YxLThfFsXWp20HODlp8vhiepNTHOGoXXKgqoP4qHxUDqUcc0RwU3Qppj3tAK4RurMczSz\nhhlq8xWyWv5vlyJxmJzk7hfCkbradsEVNkfl6K9Oahz0QpXDpQf2iFIk6sdPbjligmhJi1mM1nkw\nG1OXII9kBqnpENv9N9RSHAqqC2EZ0rpCoo86Ow5r0oOJiUmcc65rAomtlFdRFu978TKuwgSK9C0+\nlvBiOfqqfF1RXBAt3OP8BIZgKX0duUVG6lxYs7unXE7WrDkaG3V/VbM8WbHectyWnEAvRcw0S9mS\nDdiKwWKoS0qbSDhtaCGXzhWMnM28+4kegOOYPbRk/Ztu6Uz4g76nX9OiU9zuNUq1WLLjEKfHhK8a\nGSK7TjD0XfBFlJBN6zICribUSvhRDQzFzH7HC5lKMwntykOMgHH5PeJ5U6E5npyoaAjscpk+WPXA\nO7umsA3PQlzkImQmqtskI30+FAMhso1bisaFVT2D0o3MCcuLkhHfMWr+6sIBgfjsPS3K/nIc79Q9\nW78xWZMkiRzh/66GAojp5UtmS+9z0Yefinic4ll5BWvFt8Nji6T5qr3JNbmRxSLIrWy6SEQYWFbk\nuvDa9GkoamiLQGh8cxjQYiz4sGUOXLRClIx0n/r+aCLxc1osC4zXCCC/H656dE9KpcyrxrxNNjGg\n2Q/qsDxIDgLGrTldEhfzYQxCutaJFSxO5+lBXt/b35vFIgu9EBtQDrf4Yb/vRBnwosJ4EXFzhc3t\nCGxZRFmfJk2EolT7/9M5D6mI5D69lbzOGLfsas8scb1Fu5WzV/LVcuhOFhwOfbhxdKjynFeYJIlM\nMg2Y8V8wIoqQqw/LaPQs50OVfuhNZMfG9jmA+ExAZe/ucokZeZna/5j8jVI/rtQkEIg3A9fboOJs\nI3w+MI485SEWZ775L/kBv3b+b5mquXpb/LxY4Zzek05EvFEWOdHaJHOx53f320jbIAufGGFQ7S+r\nMLP5o3+SIoY8UWBBcJL/pLJPPMXYzHLYwo9sUUSrSNf91mMHDv+HU0Wh2eySI5i0INK9gBkxx1fe\nOnym/qYScFhvYPMDuq+TPTH0iEWD46s7Nv4wuIOAq5xV9O3uryeKpUQziY+T6z//hsGBBWNbBl8w\nILc8gwYVkfUv/2L46Ne4F0DRSMim/kOuxiN/MLiwivYwaMYLPCHBYTLCq5EqNIO7UnifZgY8GmPv\n+dI7bySys73tXKSYwPwdbvMeqWjgnm15QxWxPxnL31tSCh69yHnuR/2UDjSIAvziXETZPI1wgtzH\n4zNfH60m1Y4fzEgIkEhWL20v/86j2eS8LajMp6wG+zX/SH0ofwqc4WEYNTUUVt0txzLsY6vccknj\nAMiGAZ9WGwk3ltiCXvSiA37xd/64b7OTSOxdAKC4lCMw32HOZK16d/EHl772X/CW65LGXjBwz+g0\noKGa2hjFuaO6U8i2AJDZO+yb5Md2Cr5tLRbRSWmk81RoMVUqIUbpNRAsjbXUGZpNblzYOeQe0vt1\nf6PxfYHe7oPrkpdbVGRb6G25F5Js82fbjUpzX2HDdU7Il1twenLOBN4cdD6eLejdhO+pwQdYX1pB\nQYJ438wpPpXiwEpSgmIMlspfG1mNSTxfdEUAHgFRWzDvdbBaWM8XFSyfjpZSVh3K0/L5Oz1KaHMK\nmlL84qRPVU6Rp+NoD29VfZb4OyRsO4UNd4pduIp4FeB0TQVM95pQ6okMDeNIceKcw1O91PWKden7\nflkLY+RgDV691cdU4QbC2BRx5asY+ZiKu0bEWOhkJH2/KmRJITdtA+7xavT839GCEWYZCM3YHo6B\ncuw/VqDedEV4xND7mx0bYG9x9guBtGVTHiDTyb7phXjVe7Fyi/x5t8VufShAgo/rtyoswiJ8BhlJ\niPsuCwoul5MxCFqHLK5B+UZJqSIR9/1VIFuGceMk5Ubv0d1H8Z5bPpQwCvdfLL07qvjUEvpa5mUB\nuJJkNEG5juaNM0/IUY2FxPzrNx/PTRIjl9LuV5dlE6NhxpbJtZRWPj0lE8jjK1chUV+6+2I9lrTc\nrJ5rmF7L+wbi4C9Dnp2x2xYaS/tE0F+VimsBt7l7B9bAarIiivHNFgTe2qE/+Kb1M3H1ct1Hqjm5\nAL1YaKcUqsQLLnEvw5cPBqQ8QW32XBuof6yn+xxK1EOpb7J8gdZC9ud9Atb/F+rDUY3Zk042VOJ9\n+38BfXth0Ew8oVZmdThyt5KDvzgcpYhgHwKbx8cB7uW0LcTT3DG+SLkqMgun6MwLUownC1+r4G+k\nPOYQgyWZ2hwdrVfUEm2FQ8T7jIjofPdRiOV6vMIyo1LQtEHryCdfVlFdMVkX+zEa1uMOonNlIG6F\nqlwAOm8pi+/BvGuB+BRrikGczOJB0Wg/rgpg72XrFf3i1rneXsCsO+VpQRvcvl0H7+GloQpZ8e4/\nL6/LM7YId2uE/6LP5MJwBkwdYhnQeIBRDsaT4SqBqvFFGUwo9XHQ7BX9hvDKJNNr2WJx/TN4DGSc\nQSXf7zNQkznf33MkIXuht7XWfQq0F2JDmeO2vQWLYbSyGuKMoCeZqlWTINTX0kKL2gXogQo0CSFu\nl3yJUjzzXg8kxWRp881QDeoh0QXJzkJlSK9RcBJyAPoGq8MGVQnhqlZCaCtKwWjxXPJMod56Ofz9\n6d5QEnLnZTdUaNX5elPnAy//gVbggUKwOQ/skaVSauu/sHjK5FOnEBYk65Rd7tYGD0NeBXwgdzq7\nZjElbS8KS/Cefr+77JrYrMx0aZBZJ7PQi9t6EAB8LJx3ynPMFiOi1mFRiRTnoOunlquPz+IQPZCz\nMGnV/sBJnYWAFfT6SVllXQSioS/rUjluR4vovLgImmCkRQKUSj5xnZdY4AVssYcDjdo02+On7piN\n8qNFmcN5E7Yf/TncOjvzUDpXawtm4XcUunz6fz+TAFwd6SFGP3I6tLXK7Ell/AJ6615QZubiMzMy\n5isLZteUKQdn5qY5SU487hB+j5EiF/KIGAbITt3VhdHrimshB5ya4LsOjyuKLV8kB/V2FxEcrVP5\nlPsWo8vJ/pCG1SE+UmhSQrWcx4/NM1rtR7bCmMtSfeu3ZhArzYJK2EjxCmwxqxivMXGcsAByH55s\nRNnTvl30k066eZStn34hQlok8+Uj4MJAmSuHpOlft5Cw/TOrk1MOZFdyyX5HyQGbCwAhDElXG7Np\nNtIBPPZERmcalGEy/Owm1PoUFZGrD0ygMaJgnLTHY6MLYf5DaqbqAsq33MOscg/qw0ro97IvQveu\nbVHyQ8dKOw0H4XCakKKp59qL+Lo06pAmqctYoqEAI6NyA5PBetT83h7XnqI61qecb+efcMBgjAHx\njfy4b1SDC/HxaiPhae5rVoY4Mii9nQB7tuiNNT6Gmu1Vwwpg+FqVEjv+kwb5pFPKdcoYZP+5TaCc\npfDutBLUv54hLF1z9ZTSVfm8dhinFIriv3FGv9/qh+OBVnE05kFf0guuqhsiraGuH03jxhZjWfyS\nOaM8SAV0mGwdime6bWsWIdynqw2HAyQx5ZB4Y4WQMUkJTUZZqfnyJoiPtmujk+CkRIbdfqOinQVP\nO07DTJxDEzoF7uhPsOTK3EFXwpS8pYBJ6rBUpkDv2cdF+nkS/+/cAXKl/YHTpBgNyZhjRpWyxHsn\niFcLNNJfu2sWWDKVydWGDedDKCGcvqLPUsStmaG3e0WUzqYcTIcOw4FcGgqM5B7L1taswxouzywa\nIj0O+yHtm4lcDaUaPBH1jpC3Tx1teYcGoV9p1KGhmnqYHidnh8j5RR7mQphYOBTEDhrfxBok0oZp\nxEb5R0n0lHsnE5wR+R4TmYpqKaUpaZOnnhRH5vBWzpvNoXJZHsCXpiaDJFAEE6vHItaTa0n+jLX3\nsAKceIWi2N0ON80jpDAKDd8n2CWy5iOPEydoKV62sboxWYLHelvWFOVdHFqza9cLsXbUMPH/vDsB\n8zUXcORUvcn7XjjuxPfPOc0t/Q0dPFlQIuhEr08hTBnRjrrlpX7+x6ZTY+fPNHR9F91Pv0fPWCIy\nbROzbw3bSzeY6s15+qHzXfdfy24+QkpwFfNxBLscbYdYMJuaHRfUkYdyiSvy88tiTke0cWsJIgL8\nb6LF55Fl+0MmwuU9qJt6LFzPlqMjg3MTJMUSxs+oM8M2Y5lbhwQwyifFyhKYtLmLusjTARMM25Y6\nukzQRYRNI3Oxe5UbT7SrcwTUy1Lzewof6EN8wyjkP5FSWkYNXeMzogCzF/M5OPrEz3P23auJXL5f\nPSwxg5GwtiAddrpoxwVq7t/SXomVKF8qrK6QHhSEkffLcH8rFeij+Eex34jAGjtyYThMr2yAKAjQ\nvo4wSdK/C8Znry4ZN2XvcUYAMID1n0uTpMVXdijFIGLqamf0k6GmXzQ3UpVfSzrDS8bynQPdLLGI\nuxvSeQyS5cbAMWmj6MtbyYyhYMLNeIGeHc1Ble5JKk9XcBOCCFgzOOv31ocUMajLFqBtSfkqRVra\nFJiVtRF38mFRo9WKRHhb8sdoITC8hS2CTMQSsxPCAmNaVD2bJ/qFT0p1EZZq6BoZITEqjyAZmtZx\nXqR5qhQI4oxW96jPl+BN8zN6fFGwSg8Uc/RdDO4jXwwJaU3DhK6+dMf6pj/dlOYkkqJWJ5zvJtdI\nN/rpUYECSK50BXCzYV95c0h8TYbjLL07Bo0wAZsx9en9mAAJjFeW5J9b6bw8wSryqIlFuv/vii/8\n0NeNbQ3HukqaJ6WS8ig24kNpl9AaJTw1mevhFDSLwa3iuPULC+87SJhRoIKk7u5faUsPh5M+BdS3\nnwwNBqnyAL/eoOxdZGIbuQgqWGGzqOOHbG1kV1nNYc7Xp33yYYqiV7WseZtb4ifQcYtnIMXRuCPs\n0HNXHhr7bZxfYss+z0D8ocASvnpOL8w4nlKT2PiLsJ+jpVGuGS67p7kyScbgWATTr1CCJkP8hlGI\nMX4ceG7sdnxo3SvwA743LtMPEDxxTJV+J/+6w03IxGuA5NzYdhkU5Br4pGMfka9XTP8KCa/gkIs2\nw9HFq5FtvyOmvpOL4+vO90uK7rMdlqzeGa/PolqIB6YyPVJKLa4IIK9yih6/HfL4Dr+t/VMfsX6r\nwVNKcvxe0cS/qHRNS5g613kQ6UhUK6nbWfngwumJfxEVujPsHnfwLImvXV+Z0lpohVidsRwRstCl\nypmA///VlWrIIEfM9ztYImxJ+QCWHceJt6eh32pSrS1Y7CAJmjnpYkmyNQzNY63+27caRFAiePJe\ntSVGh1aHXEvlFIm5wia01tXhKIajPWowqppLHpWsZQkS1rJJUM4r0e11wGleAGGxpzLFv++3rRZV\n2E7P0LyqAMCVXwuJgbDCIUjKBeXleHsoXTjsTJ0RcfA16W2S7LwZUHCmJVq4hjScokm5x4LP6eKu\nnW7YbxZKQNnAIWffjZAbiPXmq2NpSzKlWV7VBEHvhB3WX+EGeM3dY6Fg0rL393oyDKouyjUWwtJK\nKkxwPWhTHPfGtMQHZyUM25PNCS9dRLKFvj+8Yuv+Cjbmf1HTxuUHNkIppVMhe3pp/EoYQdCKYkf4\nNmIqgPEpc1Xw53xrv3c2+5Qe2RPVMCBF8XCVGS08pfg+iaC35dIcxw6Arwcub7q1AJUHYWWH3e17\n++/sVHV8krkistFmP10E1UX/+MJ9cPXKZtgTdfX1nP1wgv2fZiV86BE76jaU7foSkNjoqQztHEvH\nvnjg5wHfIOBGVzLQvSsux2gimvtklrdrQeNtEAOAQpNS+C53UQWER5i7GMN1FpWJmOMX0AnM0fdP\nN+AUFHdOIyVfThnj/V74mNf8KRQZT8nQUqmy3LgdGQ7uPX4esG3SBEeLh2JSQd7DG8Rzy7bzFHcT\nR/lPn6HC2RR7J+MiEZbxOgXfw5CazrPTtOwGqDjFroba3fEyK6BRmL6ltjB2nnNbZ3QMS84Tngu0\nztlVsUNRQ0vVqF0YHm5Xzu/LFsbmB7GIOauNfKOdAPUZ9+FyQsOahJKfbgvle/vzDZKF7dJBesQR\n7G6ng9CIXGpMPYE0Je+/agXWFSxCKueeO+bxz3ykBrwSkZqafIocSh2im4U+LUrsdQ6Qg5KHNbvA\n+2ko1mWue4ZHKFv3GFIz6qy8sSdD4o1YWaRzp6QR6CuG/L0GNdQmSRM22JvOQ9ORJ8zEvxHKtsnC\nDDxX0UtcYsOlNPodlxY2wv52fihmfKKbhbhMpFY9wB8xvbiq2ZD4NKhflfFlzzNjsaAJtm07xKlJ\nvemry435VhaDY+TdxjrGnAKY8dtM50Zuw5GkpQQl8/L7DdmvUu0b4+ozCk3HZICokDOSzb1zTgvU\ngwko9mlZjy6Ro+IL6CNR27Huwainy4TT/R0u8/+5Fv179JNlvHyGxYXUa5rJRKrKic7H2nf4dykH\npcfDPpPIdH1kEIrpLaMjMoIsf9ypnvIpIO6RdGv6+Q6txwVGizW36oyiNd3BGZXe5F2CH4ImOqdT\nzMQ3d6iYRlIvqU9Kw5Ul/e++X+NLUudXHoAMRCPNbvPhB7hOYnKeR40UYNCDjm3KNgvMxzKh4Dd3\neQKaZuo7/YToyzwW/jjo35H8jGygVz0cA4hssv3j0DESJpsjI4uINFEqYK45Jn4fRPDMBxpU0V6Y\niAEQF54vjRcFgtShdk019k5MuVKNoQ+6ioiLfV0VtqEfVItvGAa9IlriFbDStqq4/rmdvZSArMUk\n+uF0EFdygH6DTJhAGoF6uE3zm+O7VytcdokHJmfnvl+LCSqwm2E9nVmqp/LTVl3GOKTP5PHZPyHE\nKCi06jAtv4vqhcRfdpwIt5LhZiXTuDrW/LJOqRdZXN5Lf4RO5T2gjYjgq+1ujG4JBq8ayr4Jhmky\nRSYp9fjRtfWn9lJAN8k+AdmkvXs8jy7wF2739kvWDAN/un1R/jxWygm4VjmCETmc3tgWZTBsyj3h\ndS7ip9ZGkO9ob6spwsAgTdxMfvK1vrx+UtwMbTZXoYLsDRtOHOpZtSlwqzdwlfTfP8wqu2owh4NY\nIMFNw2uV7x8Z19AnwHVSVg/+LRFyuUaDGsY0Tx2w+AWOhecrWJh18NUOCcw6WYG+/zLfHMsOy0Jw\nzbwdo+ynwtdG7mf4UVXSsr8vvwXKUGLzH/u7HLX6ri89GzLPTloHlsDEKlwnHWE+ElKuvbcbSNLz\n7MAhzh77MOCAOzn1JWSviNo9oDwCiru+wmYkeVGBLPncm+tbZi33xvyqZBmfdAiF26M8iEdZ0fC2\n9yNPdv8S/uO19rku7PiiqZvBEsudotq/zr7KC4V4r4Be4Fi1bhMPs17pJKEbnnZRV95jnZZBbWVl\nB8dCXMdwhms4DwWuimrqylqqF0BkHLvolrJ1PF4O/vId65g+6REAfD0mWExq5NMxA6QraCswyXBM\njO5ogsRfcuZw4y/Uft/kFMIM83hr6URIolvB7wRczzYNd/L/rUCnaBE2JIX+ZGd/Agmvy6lyaeSg\nQDDJ+ud46UMBCh7q2VG6ShlCYR4MyG+vuI9eUoHQ6OXuK+5XogDKPl1ThMXtIbZR37r3hWwh1axd\nlmfN8x31WfLCjsSFuBJExJkMZ5INe4PrSVpnMhT/MPhDbvh3TfPx9q/rDwDpqNlXg/4wsen236QP\nfqYOepmKZ/R5cPOjQsQp1EdDmykoEBb5vKZC+wJ2Ni7GDDTyuIUczE5uoWPFaOeHshGDmqpAyi0C\nYF3y8L311F3BT0yRTvNn18HPzKtJTn/lava4O4X0UK9gmPS9IUpRzvG535glq+TPTBeNNmMmjpoF\ncK043+6zBszbg1lgYMvoV403GptiT72C7uIAvpG0g3jR8ktV8ITtR8Ho36g3WEjUWFxurrhR5I/3\nMa4Igyi43BjEzm7f6cmxIh3L6OaadG2DZ38XUSedfRuMRuwWT60QG0FmYXdeGFv4215blbNsymcm\nk2mIDQbGDk/Qybmsoc7LPxjQV4G98NugY3JbxzfgqetsT99VhDmj0GBIG+LC1hlb++vcKjraa/C8\njN6NZRKehIkIZC4+vQS6gw27OP4PJrkOkXASle88FbbPhxozfa1WyIQrOq1xIqmLOHigv/faefeW\nAxTVyv8ScMVWcpI+jLJLLy4a1Ch7/HJ/igiVmCHlJm7ckJMbgtBVztLXQmXnjJTL6Pynsx6MKv0l\n8BVbVKIE16HLCsUqMPkgg0arbqf7yDPlygpesUhx0cUmFWse8vcOA+1H06P+4dycC80KWTsmPS6B\n5EGvU3RjL2y74HpjqP3MRfZBswhULeDpxvyXTaudo8034t8jEmw2Rp5ffDKcalxJbexN0612mGqK\nXqkLlz70YN9vIddrjYU26o3OdmYoBfN5cTWD72Re4pVTTuUqJ1HEE8xye8F24YDscQOv/4SaVieW\n8xM1S9bv0ifD1RYJymN5BCskUXl/bB/maR9C0MzQ47TZprWfZ8Zdhg9whQ54UgBUNuESTH+6DGs2\nACGSy1Dns4Y1955iy1Q8actfsbkIxYi2/oNqHZ02D2Xvwg3tHecFHzolEI6SlfAbGebSE8zOPlnO\nDk5WFDm7R7Ya9Wzde1ycw2/dEPIiNXKlzF14E2Q5XodVnrcpMwAWMhgnnuHIE49vs6jmYNq3GQis\nlhQUwP/dNeK3tPco+bLYIdxZJ7pWhl6d05lMr3MGDeem4/Cpl2QjnO3aBmxJ8J0XA9RR8gUjA23l\n3vpbX7HbQi51qCNjyhGK1Tmn2en0/fGcEOGhZyyCvJH4Qo6zB9uGykWijrxVWG4RmvxqKqqag0FJ\nDlk12cU1XziDHfGXtE4VhXARzXiF6esJwhhcSD4ZrgY1ji1RUxpWB+b4TuzJKPDpWO79abKalORo\nC/stTdrUrz/piO2okmJ8sOj74MQPCPxN9rpJdhy2k4LrMMhDh1kaspAmkqlclPY1falbZE7cfe/0\nin7NtWeOPQrKTl/qhE1qao7k6Ua4ZeGWC5GHaS2ipHen6ikeqettySwzRKBmkdDQSHamPY/wDQo/\nVo5THKpvcnZFmnuRDI9gsWrl2HV8Cnu3cziisYvsdFyyjFJlLwQI080Hm7YI3tK2ujDpuxu37bkd\nVnshVjH6Lm3O9gsdW5jBFwOx23KmV5lftiKdYyRkiF2iMjSw3tLSSlHQ2n29KzYnL1G/26FjOuI6\nmThzBJljDQuqaE3P8+F0mWoEBHmZCjrTaPb/too5PFL5RvZtiGun/PNgZX/pUEuzDeQeX08IRmek\nEKmkvHTs/bc7f9diRmuKuZ0H6KhygPZAuIP+2JJ8Zcy94C0B3pNqkm7GypUhQXN7SZe4ND/q67LO\nmfiUWXZhCIigT7LLJt8OkggXTxYdk0ArF5AA/dHoUgKcvhfFXSnNFzcF4C42BPgt5D5lWQUDipZ3\nQ8715I9sCHyxQVihVdsS/jzu8jW7ZiT9fmouvloW+afVRWXnzp4xWrqsHwJes5dBP+OMnR5K9XyV\nwpOQXuAExmx/sSUECT2cwytphepaK9GB4+yxMNZU8XIqfaawkSCeupH1jiH5ztVfu01WsSVZL0Vt\nZ9G2/wCR77e+YWHiga0WAuSbN0Sm/kAOZTbRQ3Iqu2L6xEwsAt5OufgkCG3QWEA6ZFCgt/11FtNo\nWCg8dspVc7wjJGcaQh62kkHOHeKyQP/GPfc6zfn8ojkU6lx6BtJUzVc9+5iSeiziOxJVcg+XiNfm\nry1bTBPVqs9V7GfXZMNMeTPpqgwy/SDSL7PSaaGXTc51e2rpsZPCv4PWW+k/3SAK4kBHSFsXoFai\nlWnFbldiXTkPzBByW64STapLmZt/db23NfGWmSAgnfeLy077nTB6S5VN3QJaubOw+sUFq8QDZWhq\nJlxIh/AxMOu9CnXuhl5COX2kO9MnYp2ibQXZjYB2Uz8GzbRh3KOr6O9O6W3eiJS0HmB8DwT3eBwt\niH4rzeVRFdnU9sZW7iCshmVvJV+XW7oEo5D+mVIWBfKFAxW2CN0E7mi2blglmwl/uUoXwiZWTQHN\nkhag0uDa1dx9iDbItFz0ff9B2+bFpQ8AkwoXj77KoRfnZlVXLC+351BetTTY9QZUbC9jM5kBy01H\nTMWQkj5fvhJ9zuXsRqN/ZPhdJDq6JQuiEcgl4fc7vL6BcDmgAMISZNEBSA8QIcAwmMU9Z0K6SvzL\nNAwuXYfobpCOxANwrbOXWCIRHi0LUYEAp0zpK3AeyOedeZ68F9Dx0fhcv7R5k4sHHwUeJ8QWMJl4\nuqJXzDcHIn54qJtSVy2yQ36u4QGuUmRMJ1QDFwxXSrRk4ewO5n6ndJrxupnl+yw9N8jpv0rFyy8x\nv6tNb1KSNcA65G38Uk+f9pXDFVAm9yVMVmNARfZzNrQybf4G+K193zlQGV+SrzXvvGpmOAfRhgox\nHa0Gj16eO+vvj9fYyRY0sOv+3uwbC1pn85cfGt8zdhHAShA/eICI6mnWYE+luL8oTUPFjbA6JuTg\nfWgf6iE/NXQSL2DBUMw5RF9/G3yfPOT8oYWbJZqL/s2pDbLW9hNGYXFQpXD1iH7/dJeQ1tdJipcu\nXGlb3slj/kcLiggxed89F/4aDEvVs0e6Ln27lb0ihd7NmvZrkbjT7vY8qISWtBVA7tNKlVV00HvZ\n0qvK87ftjk92FJK4fSekoReIxDjO50jci6dwOEqmYM16fIkvpBIllveCmSgWyYQxJoOrTBhPJJtf\nXfZ6PPmEUUvXU2cz8AnKfLRCcN/Cf29cKf549Q98BDW9jyemH6WdntrxM71+Hhjv4S5TtU0U0g0V\n0+t2NEX2ofWopXzTd7xXyQWW+2FlEeHbIg6Yi7LuQwhxTEUHKro+BW4SDMa8Zmib3qrPzVE1roWa\nMlCU552UI7bRNUR67/3lL2I9V5OF2EUctqNmUS1uRRUduiEN98Ni5WnO9pj7dC/aEx5fYbprxuUP\ntYj6TxMUAK4EpYp2EU81lidmWfGE+PSltOYjZqwp0eX2VQG8gtQ5XLQ5VDL5EmdTdG94MAZ3KWl4\n71qGiCGftP1gc02JOeebdCLPs9RB01Qamz/7qRrtLZqfjEm7vFGnZjrPbvouq6aLrTrkSoQ9Rku9\nBq7sCRWpZJHwIQW3joU6vIKWqovqZrmuMZEMt50iADknpPAcVttuorkxIhrY8EMGTVLaeiKc6+aC\nw90fEP2IluyabL4KCB9IP5YRud8Vem80dhNNefrYqAytpEjcQQMbkigJA71KxdxCMLHjPZhIqf9P\n1FOlQfDEyWStjz45PhUvBsWGfNfY4e7RP7t/msJ7F3wQoa9QKpj9K/iurRXNZN2eKT6Hj7SGkUn0\nACtUn9Zun7Ua1be3Kb+uXxXfvj7+T0Uz3jlSydytD55UnuDAYq+K2gAwynXtc6841qezeIxadr37\nLq8AbB4IT5X/oDEUDdtuxJhziiuLroU27SrBYnAx3ZoKLS6XfVF7wXS4LTlEOGi4AzkJlFgbtjDN\n0n2EsteXDHoJpKSx1AqY+vi7VY3JpoxH1RemFZ4Rbxr3Xmzsdx4BaO8hsfUOAXD/iq2b3VP/iWhB\n8XRPiTNtsAKVeSMyRv+E/9K5cMsB+gFtd1En27yHSX5qBO9M1g4ncHw+EIhgU0Tg1aEZlnpBXn1f\n8KAdY+kh8PwqGgcbkRdJC3bttZ/g9xR3roFPxpAZ+boxGrp2jE40Fcr3X4g44jgrA4IRgiUDIWTX\nqR8lxjalxvMOV3ATBs+7cP/BSaFzc7AbNgflKhebuvoh9OVDpfPv5+tJj/Ucv9iEIo7eCoyA4QTT\noY1enrvni6ko5gsAxgyanuHdkjnMV9qdVIMntJDRkt0cWEfdAEj8z4tYB/hGCMz103rrnFkX+aid\n3cFFPfSGptu7BMWqfuRmrduQ2xdKKgZPaj+yLnReK/vEbKIkBYZl8MlESCeAWwf1nzu1G6V7xSXU\nFruXmDy+vFG1QwwK2CMJKGUq1PintY4siRuRBhjdR8bY/v9Dppoqiq0GbWCnEnoeZ0lgvS53Avh+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GcA9Zn6JSJxTUCwYs8aQ3SIm8x3etRqToWjYKTAbZmvRezqKjuhJ1htlHyPt+p\ngxFYba0DOIa5737BxwzgTL+BM/X75cddRAx9O1zRk7WcZscO4nKsuVed5vzVpY5fUeeam4wpEreH\ndf5fZo+i2TN8VR099r6xe3IuXjepLpUDSqgz1s6fjumUU49h8B5VogWCzI/Sng4e2ySs3DuudcTN\neTbO7F7hocbaR4Ja+OHzwSKcERs2tKt3SKOZaqCzh1C4cN7icnZeSfmDXVkJyB9mTWl/6wSahflp\neg4bS3CxHvVHBxc1wTPp6ZwEbCNJZ1GeG3MurB9i3JbnUDzmOFhwg7eOaFurXoGiv45RB8vQKvjc\ngyyFG8V0I0UxUmA9cFlbilM6mXKs0c7bvXdGnxv2DQpmqWwHJafqZ9Ub7GIRP2nIw0yClX3C5UaC\nyf/tjtAnY/dw/5LntI5BBunmuEC6fBhZSntF7uXrDWv1s+C859IbUO234tYG7dJFDQHZH29sVYfg\nQYZDwlOgb8VuP8Lpo6c88I1UFVYFMgCF3P5SQ+v1m63bfe3bay4HUTISeVJUy8JV8sfADq2wubcG\nuWcfUD5AShQOLmrpWHHJ7kOetd/o40exAcRpY6ruMZpAbw/XTk3w+IZeYAjXvoV4HsxbneA/j/6v\nRCzoW5P3UuUoaB5PgGjjGV5hyDlRE22MnFsaD1Edp4Aaazf6x/abJR+gEuiOjIkZdFyslNkczRoD\nu7By43V/wCySOAnWyFDHOhN+Rk2yxZXouQu7q4FFldEH1iFrGHvxaAEezrQSskVgSBq5s+L59ioU\neO9CS8jae071lEKSz2D/g93/OL82GyJlZWj+PeSbqzhShQ+oX05Il2Hif0Nxbu2fUZVIMzIa9VDD\nf0JX96UWWVTDr3evRvYoh7RwhDS82OKImfwBmSzxFjawoemFpUn6yy4AdrgWom6pB82BOMrWyxCm\nr0baPyGumEcnivasXzu3Ghg7l4NtwjlcTuSrDJyiIIqWlD01qFIT/NSe8XGEUU3cnSBqQfMnb1rY\ni9O0ljhYVL8fURPadXIpnmspDZRBbO/9U5PDuTLIDUARR58h3mS92o8oG+2mYSEHMk9Yt23OoVZN\naP/TqOTjA3bB1PM7YulgzasFE+gl9SAFP7u9cTy07ik7Z6RqLfrweuEgZzZGPgnx+HDSN6clM4mE\nVHYMRJf5jlERFhrV8NNEHb+dJ1cy1o+50SKlrf2bfrsA1sMfqwFFA7WTEXfXopqTuOy2pS6YuTzn\nLtt8mp+m9VBSNQNLGSuPeVQKDL2c/GFdlc6tWG5msBw+rNDavwUIHfgdxQT3krhLdr0g/Xg3vX10\nmVcpqzA8cPWZU/PuRqdqDxxY+pCqDWMuX9X7UVKrPye75k4QcLary7mM+LoUhbsrfeeVgHdXbQQM\nzMhNtPA4SoBi7w0scbWfeGmkJixU8Sj4L6lA3ZvMrp/M8AR+++6EBCX9ttW8OQssFTRvoTnGA4Jn\n2kCJwehXlV5jwMSToYsyFFZIfrJxAUbo/+5sJXPMGPJIZRxRvhgucH3WnPrzojvDrhoDhR9WTn/D\nUIlyqa4FG7wIMST9OtD7LQ2xc2zji5zZN9DmxSdSMDQA/03HnR0gcY5xRBuJZ1lVW93DRflHAlIE\ndxPAtrUw4T1wgmfkkOnNCKxOsSAufvMYEchVBCXPVSTCIUgCl1WDz1FztJXRkZhd7VubxRZycQbb\n7F0xSiDk4EP7d4d1bLSz4fXRdkVa7inKtRAzuHfrKZes8NViU4Hb0i39UaHG/0rHCiWuEqEaemNZ\nta6O+8TeqDy5mRWmtS04oiQBIqj/a+YJjajeqKkJo5PwXbtHvSQh8grTm2jifLLDtyc7quNULvHe\ncOm9lfFtaaA9EHzxLtTm2U+5jwj6VdaXu/Ui+MVFI0xsQHgjT2wK5sk2yH071CVmBEItMF1tRgQd\nQIH/aNQjpXW0VHg7b+/8rumUFrN+pmkyUxhN2563muCP4KBJd0JQrKwU7s1O3br5fHuueVJAe9LR\nyXRESLNfzc+gr9SgamtzGojIrCBDOUdjjM6J49tE5jD0h77qR7N0SyxngO1MjZbfnYlh0TiZkDrO\nSn6LQCdtHe8jRfHGsS0T3MouZqBxtTrH1h/5Wg9xfQiQNzbjFdKkT5KfBmXj5IMkhLC+nYB2DwNu\nSJ3tFGNeOhrevRvFD3kUC7fsFE/ZwDgMmeDRMbfPY/Lb4XcSd2iIZBORBSlcLw+e83D2PnE6mkza\nnmnmKneUB+XbLJ5SGoG2x3n3eYD1iqpgIRRjPc9+6cuqbbkDWi4/eLtllVND026fbWEIF7PSYUK0\nwh1664zeBZIErMhQYj2uSBUZUWLIb2ys6q64oBSI5R7dLu3h3FuVojFnfAKueZRqbC9twker0itL\nIMphRzQ97vqXPOpQwskpiS+j4989IJOhDe4UTwtvUFVPhujGAfnowG3xIolbZ07V4VTbTzi61amj\n29GzddvermmeN/WW4di+c798HQaVMAPlLpjdy5BwGUk0SINd/oPNbjC3LeDtSSBdv9jld6nDeIjT\nNOVG8bBSqDP+0SDTjI0VlDlLKXh3KmZKpG+OA/z3ssNWrlyCFOgq6ZD/BUQCb3CLl7yKAVDswePh\nnK5UpUiGqm79YFthbWwOedumd7lJPMBxNYnJmAmZtSqcx38lGLipvw3ZMIEBliw4TlSRjPOodnCj\n5uztSEunBm5DjF2YJrzC/eZ7ea8lkj2HjtFZOrVG1eLYgh9Xi2PTJn3eCiZZBLMyEIGbpmrAHEEt\nDir1mN23gE9E3gGAm5AIQd0X/ZM5UBNPXpYcT4QMDGFeR8CC502+5jQ68swFIiwkynNbXW7v85kP\ngNi6PG3pHfS7G8j5+v0eyr4z87SXr+0wQ7+YrKvAjVHMKwTGds7JZSrwY/xbyS41jfuL4BK0XGi4\nGKhXRrAV6L4csIatF/43SQRMQAYQTLkSdDlWFrYmimVcttsF3Nb/V6BRPKOMZf/AIRfl2g25CdOh\n8t4wi8f2wZ/6vvyVQ3JjUs1GtUYeFEY2jWTfc1nfqrw6YJmSZExzhFIq5LVEZ9hcIQ/mWBgf4VfF\nldlM3cF86EoYz2hdMw/bPSu8pHqYAOWsZvsPVeLvR5bf+ugQYrAbCzBTFgM4SHoJsfINe6+0nnZW\nfkR1pXXII24Nn1y/HuBasCbvkzcHQwFyLWOi1PcOxspjoOrteHd+nv1PwUwED5QpalSFP5gx0j/F\nP6OQXBmrcu8HNETcC5BNbjUUgxVH8NmEx0vYKQka2u9RIWNOY86IY1UCKu4wT5U1nRyTpAy96rY1\nCUY2eeSu15cl3mFEsc9cR2SaZp7oGFiGkOeASbDfact9JWvN8TRyKi8cuY8jnRLtMh8w6wkHUW+F\noAxhkhQG48kdBvp3WBM4eJC/FhAoYDpTS3VrpOPFn7cHPRte76xha7ph35Pmy2bw6sY+BQ99Yk6h\n9vmke0+Iyb0+XXIHT2rKEiFSiu8dRJ6l+AqhZidZgZkJhwWP6y3ecQwmJVAhV+qEd0wPaFwMQoVI\nrzJC7r4gIi5KpEF26KGVAz/C0/Cj9x5E11XzeRsFpyYKNmgKzN2jhUC5+yg2/QIQ5A8h7Kg4dieQ\ntCofAS5iA+FaHtsY/jn5rX+UwExiVSxZRm7UjJbNW83QQwfFcfsW8O/bvA5lU1tk58Ii8KbxIvek\naLGlNnWFN8WThhNIHLSDeHRq2zxLQ8tG40cLPkNsyz+rMRzi/zjKmRbDejskopG5i/lb499GmbXr\n2C4NU1qBCMI4HfUZ5Mr9joo7/9FzpKG/HWLSct91DJ1rOP/RoZv4rbb9zKm+zlwL76OYPF9yA5Ma\nZe0asLuYZRnc/l/2AeEAdQVhjZCwsrClN22r88vb16gNFKtjTExjrzsDtDjZ38VXUOkOveq4mhYn\n4vnLjumrZBCz7y+6ZCszoIOjULEXOLchdJYytt2ysJfcaHDBPBxcJn+WKQ7xUvPyzh5WgRMUdsim\nDuVT+D7JaCvgAT2j1VfqyHMGXgfq5ph5OLNiOevTUYgC1V5HA70U8xcLfS4RYJI6WJCHWC9Wbngz\nzNLDlUD69JGv7uThe26LzvY/ivOrbkXghyYbkN4VT4GLqOsWMCYEtyAxmvgWAqIhNSPw0NSJjE5x\nxO2zQm1FoNF5mu+nCWJdUPtx70u0a8e5jdN9GFlj0EYq8DNB1X0nZZoBnNM/W7TUMATH/6CXWzd0\n498UFlvIFo2HQrBaKisdbEQ1Qb007Rp6TCnkkwgEHAcKg6AJiU/DZLXeYF60Biwb6N4KrGT3PWbt\nf0Kmi1vBxjXBTZbQXGjHwCQ5D6b5cYFeRxyCBrMFOUv8qbAKJEjRmrVW2MuIwIBgNbqnWIRstX03\nI5zhAC0x0EWpvNz4BOglCPcHaYYzo76rjSDZh4aQlyQmEiCxXT06Jv2NYSW0tU39elbVs4GHgI4T\nym3nR1zd9r7mOP4orAjs574aT/9ikdzavVr1NoMgeyyPCkPAIT7IxIce9jz6PdNk6zDEySO/wwdI\nCOV0YVAH8zQKQZLiL4bx5xvT3KZbcAHR1SsaJeuBZ8Lga1pt/5pLF36+kIJ9mqMHR18nWmcyeBNL\ncJEQH1ntn5eN1jpnbbQWsPwozLdy48vcXxr7N+qr9eUL8XPBcUpq43UZWMr+XUhhbgimqWxbY/NV\nfuSLs0MZQYkqzSennveOAr5UkIRGGlsWXubl8MxTBCT+GUtanJRS9duOH1yU+l8Lh8/orNoh7Nrv\nc1FaI7GMH9dMRFNACBQILarMsF7GoiZaxVxfCgQZMv2meRqmfLlgJ8HupWxkyoCgnlZLndHInG9y\n7Hs7zUmIhAGYuwtq9HnuBcKJzUP6hi82F7qk88GLhmoWaGDy+9WlFirxxJj9q5kYRwok79jIwzx/\no0ZQQUUtE1ZYANeGBMwhPqW86Ltz+DOq0vA/z8rOS2GDPEfNq/zALAuz9Wgmfp2XmtwiMCk9wXRA\nn0NajGKBfnpxQhGvH6Kt6j6GX4ZePX92brl37hhv+v3goAezP8T05xCAO3ENq58hojoRpLskhm2q\neGZIZA7RMgLk1EOC4eXqf4gyTW/XzzZphuSs3NBT4PvNCbJweAzuRW2koJNRXexyhIMu/uOSuyNB\ndtKF3ndxgqvrzqFVmxk0eyVDB1YxZW9xE2fGTDOgCvXURap9QR8KZM4J9nrn1Ogzt7jBEfj704HZ\nVL8HU2WnafB+1NDxgugtg31MWoZs7+giC5VUC5hoa7dc9vsbU9FNT5fR5ozf3v3797tYGsmcH2Fg\nBi2aS/mM6JqJ4rSaK6oFh+5Wnqc9pEtpsucK/lxY7dtCcWQ0t8pHncn7E1jhJyb8SqUXGzUXbo1B\nCyT8jRoNNy23C2KPdfcFdjUmnbnp7AUtpwN62qySlv3Xz0U5EXU97y8tdFxE0cnjt153zSfb3OMS\nrDlVGh/Qwsi9CyoBK5YapXAeceF8PZ9xlL1yT8la2l+ZO8oZsBW/PIV7k8XBWXeWzjtyWjjkXogp\nC2Lm+SenlvnxblFP5MjHdLkLIhRChOx8UFJcwPVGKWVLLVGpIdZ8VNsih0z4E+8g28p1tUC4wMRa\nhTAxtupzWMdOflDIVg9KeDAMPXp9zX7ZJHykJWRxR6q+3Y9PVIaJ53118LYjbT5kA6t3dHjfr4ga\n6sqPWD3DDpfagbv0tUyujVlnxaXTUCPu3tzOIEoPC9sIuCYESsSkquOFkoWAnE+2GEkSzPxgGDM7\nvLjNRbflPpBjjD7xsDSf/E7LDMCtiopSM521w2KOc+kCS9QcRDIGhLkYCFnxICp2SqEvoFAjSe9o\nTYG41/kG1FuDm+R+VFxytSo6hKqkhqIt8dtb0dDsY30Mlci13Rcd+MS05Bkihxs+hx/MHusmBKOm\nMcXWSABJJeJzN1ID+bRm565QsBExStKd1TmzjAsdljAUPv24FISbs5iz1ruSFpaRugTX0vIHGAWb\nvG87IsgEaDzpNSnFPVlWWb3Ae1kcMx2LlRb7534qDRmszfq8fgmYIwZQrsLjY2WjdhrsiHAMwmVh\nj289MTKDn9SH2Aq8pcgbc797NRoZvcxtJ0hD0yHoPpWJI+YmG128Pp/E0A/GLhZCfd9dPwhXprJK\n60DQduAqe0JXJZUhh4ziuj+sYnoQjandEFhZGa0cLdl3CZ+Tgs9w3FiHQ9o+KK67QgGrOT/N71tk\nr5TsA7eIZWGwk01L8o9+qmH2JnRrG+zQEEzjEK1FAz664FHDeqTSGHOpHHw4lR5PELHyFxVBRkqN\neIzgX9sV68iuU8n0DfDKic996LdsiexJexW9WLfH3DXMO8cwO5Abb6S1T5kFK4Sksh0sDSt3Escf\nArHXyYGyjOtQJXSZW38Ldjmje3CpMA/HYzl5aXruIhqnzy0L9tnGrNHIPThnvpk1CVEQA+1eMusG\nMZIyNx1nyaZ+GHA+pkdcdP90dDpHKZwqsPZVHf3kKHY0u1jqeTGchDgTlz8mFXE0HTq3HbzfKnMG\nY4zbW2OP4nzYZWPS0pgl2IcLCrPAA85AAWVMa6Ceg7mYLxdrMm0Ln/tOgzauSvkKI/ViZs1ahKOr\n2WeG7lAVi52tQpol+rSeDks6zGvoP+ePTUgYap9zCWUfTadF9/i3UdFf69hTsDZmD0YQrT/fC0mx\nhKHChOT2KdWe5TIrnbOpJ+I84InHqS1QLscyRhBYy5vOsM+XA5bxcpDSjulcZsRMdY++KfgzvGiJ\najuh9zs3L3sLdv9tCsf+elYA+GbduF7WdmxEGpEa7iKfjeJY4zU4oazPjTzVIdR6JqOFhIhziKmO\nsjU2IhcGEuVu0ogfcgl05hvDseGWlLz5oVJU6yXQSmyr7O6l1MRqaqPyKLBIMLYpXcqhMq0/R/ab\ninKhZtKEP7YnWJMq1CH91hQFThZ4vwmO9zVI9fxlfHMUoKxTIwsTHDXoyw0FdD2hfdXNZxhe/f72\n4Wkgp2qTz90wVlz1lYM+jJvggFVY+7WEQaCoHUu05e+ljIcie5sErvk0ueTOFywdM7iGowcO7d7e\nuhLyo+BAtsxpcGkBGtqomxgkZlyY7RePmNKMBesg6ouC4tmKlrOycTjVGljWsaY4mPLSKGFs13Ra\nGSwSEX53xGzieC4mFPwvJxIcirobSwW4pdubhvbdMEosfL6boa8QnLBz/2mETCSFBiJbu+Nb46H6\niGuD2cLAIuwbx8am8NAyM698phBwoPVElhRwpmZeeVpwbWfVWoMWq2v7t1oHEBH/VMcZ6PpzTcc7\ncp/vmAcidEHGZDVDjL+fl/tIQXVdSMRpJJlPqb1wALZTuVkD97DejftYg+7qTx0/nIjJtDAUI54d\nyMgtysL/yZlNf4EHhXvLz1XncBT5XlN1DiUVSNYQZGCUhU8UzCVbMCS49jY6IBUDzOVJnAOuPF6/\nHMf2nZcr5x5WnkZyCN/cm6ZZIkgwOgZd5I20Tk8LL0w1+tVygB6/J77LT1Th22rHnaGEDZEbKKIi\nEEMBRJ2zsprpglgMScv3wLsEiREmKu8lKuIYiP+IeHEJJgQy36vrSzm4Q3dLPSDLjqR8/ZOKCn3d\npgDbg5/XGvIVsThfR0tXjQuUKdw81GrqUM0MuYXkRjtzLsy6rMbTxOhCGtoIvWbkZ3ssP3xj2RMg\nzfUoGSj0PZNY6l9lCwpnuIJ7cWGYs90MGL8HLMAfCPGIPUtm6GGY7nfeHS4KIjKA4RVAXWqx+SiW\nZxSdxmiYIP/Hvl51ndadC7pc60ttuS06NeYHXDOO0S3vRQ1rMaA1jakkTxF47o+Jzcza7CiNSktj\nEXb3DfuBJlztT3vvicAdnTOu20Gk9HYImFU+V1l/7aGLrH4/rSSwmdoczLdNzpbPA2hNeLWpRTPd\nnt4lF7BZRk3h4ZwjdtQp4S0xFB3VdV9jJvtgJicwK1dzB0H3zAbJTvRTzN46JGxdDXOLV9Plgmhc\n3lK7uzj1V8wDQnncaKGeiLzwyK94e45MybepGzrp3DoeHM8I4HgjPTcRt7qL0nPWX1LvcGwaMdJy\nk3Z7nH2hrilPTCD0VbiNxfG6Du0uTixzYusHNlfx8ghsn0AHQec+Qe4dYvyN/8+uAb9ZIGOJPbAa\nwK9XZk7oblrvouXXXFBfbzsjWrOWnX+GL7ohONrsy8kJjey1WHiulVvVwSLudcs4F3gwYa1QN2JZ\n8bRw60FZz56Ne6LkeKXCfZOh0FOiTm0cRwrzrWUMTrM7CIT/YXJuJsqr/0mw2ZZ7NBFqXHLsxihZ\neFB61egffeahE+lhoLQpiZs1e33waVVLxDfY/evj3FocdMGNoQMQK/nWPz2KxxQXBtQHVZOjNrdh\nsx7U/Wnia3HajdqoupouLpo60fgJXgzGUlw8Nw8xfqgoJVF9jI7VDkdebQRUTW8U7XSVXMXF1wF9\ncPiYqw99dhUqF/Dqn38W7ivfQ+4pRrdLESpuSJ3k1DQGXMaSrmVUTgdaC40qBl3HLDKLCCHFiyw5\nHaHsZvKQ4IwKZ9p8uvWQiNYgzB/dywmnnWdg01VvpSWfMPsaIXN+TZOjB3x7At3FLyCvqU0KDBcP\nNSLmiavag9CucAQ5X0a4CbO4zq2rHFvb84VRgV7X/igswCO86CPlH+OTjiXC+98PSbQyv3Yt7yjN\nwu0vs76r90T1nhqxFoi+c82OdInCNUEyQIyMJJH1ub9t6qBHzXXy1lf2qd+S+lqoceDEDqwwc46v\neT7zK9dsLyQ8OVg6qprjyOXF+KPyYj8pvCgXrWzL46iuWuIGmQGhIjY5ctoN0taZPkzYnBpexaSK\nplkhhI675tI07CXRNHAYJ9V4WU04ItWkJcraQMbPh9pQd9jVjpeb156ehydxPUL5aUTpP4UWbDiQ\n6v3XwS04kaMW4C1S73RsASKsDIGwDxpUWkE/Fx/xjGazT2O9XC2tF/HfFu09QnBwAEv3xgxCsSgG\nhVYJmi+uSU7Pi0yk1UAx9CIBJZfvXCOBSSeqfbZQznoPl6VUDETyAtFWk++1ikObWg/mxDHhHMMs\nxxa/A/VfI6lDgdQWlRsDVfzhDYEuoBMA0A4FWpgfr9hkcsI6UjGOSyN8vGGPWfSf1kjG+4Hzkofl\n620EcndQrjZ/dZvi8FeOcveao7y3JpYdSlF2FJQpUfvrBcdHMu5PHvrjgysK9rHHuKLSrkLBU8/s\nARpzA/e6gYZoH0HpWEYwD48tt16u8tRvblN/h5H7g1tmLXRp6u77LuzB8AsUtEPspLTA7AjTXJ6g\n5T/wROxlhGKoJZC9/+si0e86GYGpR+iim1BlYnv02qIx6mX482NtCSam6G+6VbYpVdyX3t2Lm0qC\nOSdh+hlPvlsHAciO3AbGMXHS2MJMV7JVX9IQvBu7D++EeTrzHGEBigjDN2R/GdKaq7QBpwQrhv9Y\nQB1SI+U6pyEG7T5xpAw/BOsMczH5JwLlaSrljxEgzk6CkjR5t1JlKntP1W2tc/QOTiNJdAfLDJ36\nJcEywJ4KCMoDcSrl8NTApf71iPxqy38aNuehOuG8CAcC7twSHMW+1PdIlTOX/JGw5ydU0MlRxFFM\nw5PBJ2kA+0TPwLjn//9Wc/Z6jMvVS8yJ1hSLH4w7pJFT5ZhBUQXfcZMRp171i3T3Aw08GkfoUZzr\nyIQ6aItW860T2VbybbseJ+5ksBUs++IuROqDkR7JXmMXdZYpF6dcioHHU7F3r8/PSCZehCbLX8eL\nzeS2cyP103uUmRO+7BIJydB88XMvw8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KN00hsde0eeOkdqPrtftqokXUy33SJ\nZbshfcM9iXCOi/GS3dqGc3fCyjdBBxIVWlShdWbaqjD1l2P9eLlI4ruM9HngXXTYZ9fNW043CnU6\nxnLVSOiig6rg+YoekE5yPw2JfdFS0XAEa15FkArXYRsCd2jcsOgMt2NZ6H7ga4vjMlHRdoRuy405\nLNbHYWWGUQ+N0O+DX9Yn2ttYDSnMl48GEeElmsQqU+dS/kEc50y+JCtmg6HPbAsAmR8zLSSTeXv2\nCUklz/+ZnYeFXL5bO3Ijo5UiNSUFdRLG/spt1ZuayyWtOfSgh9nu5wmfO1mvHK2MOmHP9cBLPnJs\nGTVX2y/36GjxmxkwbaK0Jr4PyOEjTWpbMSkQNr4joMOVhfY2oa6FUEShiMbvI1dvig09SGjwyWMZ\nJFc7g/Z4UnDi6NJS1VqjhoXo+qAE1anZfx45QLECAFtkGe0K6H18OWYyKVj57jVc+BMu1Z1rLicS\nXiKP9Lq0r18bvP1EY/9SITN0d3jXoAjGHSoY98oYDSW5+tdSuYuCXStC8+sS/3QcmQFAPUhKszdN\niIjEK2OilFgj/l5xZOa1cFRzNbKDHYv9RWnfczn2pN0RxmxkYeYB2WNr3ajUchD259W88mYJeHjg\nKZXB90jRGEGk+Gfda5F7WWCbWBuIdj4CuqtigTPSvMezxvk6iiv0NnOzcWmx0XhipCks7MaVcafa\nT+5QT4jF06cxDH0BQwXrvmi/E9dDVxybT4xYgPrD5BhL2v2bsqT1qJfpMMPT8TZfMjoZtd2M6aHS\neZHU/6Eg7hacPOYnFC2PbvcHvREVaaYJeVpdstaKFD7GqGJV8ZrkLEilkQwRODgTDUfes8FvXMCf\nhTp5H+RKd0yIwflJaYnu0yLMWjSboQuDWaAkDN2ls6o7F7JIGZ1nKcZlO3xutBgZrXyolkUVSYVb\n1/soZrcOOMCRtOwgD/Xlh+U5Ly7gv/AP9nb35VHMdtMpu1RdYc9qTctOOAUiaTxcw2skQn5mjzn/\noJ1cfjocNsDgjkTqvZRReYaxTorfsEI3h3z+AErrs3ul84U2aNf3s7QmsOUTzzp/TgOnmprA+1Vj\nAVkM6+gFXCNsRu2Abm8q1yje//N3cktmF8xRG72M3ulanHhpPfCu94UCZQqvRTEeR1S1yM30/VDe\n2tj9lvEPgH8i0cEU9OmGpBr6Khld0HCxMEs3kLXLmOUkfU/Rwcyf84mbx541cFZ8+HuAwsMnn1mB\nDYJcMoUbxRQL35GyxWo+HM/ptUFpjVjCDRWP2PcHK1SPnc9V5B7uB3GqNwcUYvhz+oZy/drqykYS\n8BGRHP0jC7kf5gA9SR42c+jQ2Oe4TTNfdE1LlMeZhIFjNy4VhOari5K6kky1F3zHNxGi4/HZyj/L\nf6mSf2ngO9jCatQYf+mbO1R8KmNNWDoHwvZYeMkhkfx3ernqOjXnfAjL4acxxvCzjo51gn+5nX4l\ndKUmc1EkmvVJhh7mJkGlSoLesr2CmjSkSt/iKQke2btotfv5WLLOVghCLSW8QickpQut4SDfk6LY\nu3FrXyBsgiaghK+aS0vdOENw1uI1/SUwiEI0zG6oW9KOAYdKshyu2eZh5vgWMr7ag3lrZXKeStSX\n6gLHqC5lIjrBrLc4hq5kXMOh7m4XJ0272NiTpschMJtQnO7+2NbL7xa5vqSx5AwMCgthC5Jnvf1n\nfKm6zopUtLUNnadU8NUvNBnB/VmDmLKXNroHEWL/KMNzr0fwb2/8+pdNSTvAMNIHj+wRdwnHUrYd\nEVbP576EGK0b3DTFN0RWFULqV5fQI9ZeXBgcHLcWgBtQxs39jGtPsZFgydiIZhGd66xDyqx2oMiO\nwJakGoyw9hXxn0IIW8Fn2ZN80NIROhabctfaiFMPKkwpQmxZh4kvDk/53BFBxUhHWjSAwUnSELG7\nw0trKEjf/G84cdtr59zyYry6TpUtYX3j5Ys8K2MFCAYiudfN6deQQlhdd5ZYDMn2GsRWDov3pA5B\nCEK0qSAfDa2DRVj5J/6PRiTmbUzzOmV3OVD1QXMDDSa6hAAgjMHFSTWBAj/20bW3nqk8c6h5rAXZ\nZWRE5qVotrAAAwM0/n9ApGSkgsCOOHxC+OSa4Y9j7Z0NNxDqWYvI+r6PwwjFG0gWKnsK48H3tb25\nn68f/soywMWR+BM5F0JjjiGcKD/pv/3Abg10pZxVtBX83paDz5j1uYR0Y222XW72F1SiKtu/DnYA\nUIMao1Gh6ejeMSakK28zOoPGqvSNxDjwkevqrb6oPVU0oPrBXt7EX/6WF5jGyox//MVLIllo6+Ae\nL6L/ZCRxhx8CEBQbH2L7Ng7/4u+NElGTj+MPsb+rS/NBxJedyc3K9Jd7CH+r6ChWv0uZOx4rUx/J\nGBq4mAZbC91twRgCl+xaVvQ1Nt20gWt3czBEz1PWk96x6YXJ2darLuuHNHntDJ+1rSU+ZVNwfsOE\nR7+/DkJpaZHKlSXOC01fZgaO2MDURqrmUrybPSxLlMIX+6gnR5lINKkgKqHFTC7ZRxSn0SyE8TQX\nil5+QYFoIbroPojWcKdGPm76URGCeOjNEloIOgHOiFQN0PPv4NADhxq11UByyvvQMx1/YLPXb6wy\nxKFYQI1Eu8bmI8yLnSribXoLbzzaS8jH/UUjp5k+rt2fuQpcHVPkAwZFkYq4uiTzjpIsZJTXLpju\nGDCr/zC44VRhviZRGykB4Av+ZZUH911UmO+SDuX3Ecl6qrYMThnMqhad85OZ4hID25qtFYZF/VoP\niWPJaC8t+8gI9+1QeYpocdwJHVcIurz01RN5/SoBR7qmRCSYvUvMWoXMCh4oOfjfPAMWlQ1IJRWc\n3CbFFHfAFFfX6EqDTZQqNlcZ6e35ikMUgDZhP9ujxlysGt5ymKomFdGyFDMCWdochCXlIJH59cHs\nS7fQrTHBWye7HNoTuW/HGe2Q0Eo9j+ieBzeQdYm/om7MAmWHtc0aQQ==\n`pragma protect end_protected\n", "num_lines": 1194}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:xsdbm:3.0\n// IP Revision: 0\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_a493_xsdbm_0 (\n  update,\n  capture,\n  reset,\n  runtest,\n  tck,\n  tms,\n  tdi,\n  sel,\n  shift,\n  drck,\n  tdo,\n  bscanid_en,\n  clk\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan UPDATE\" *)\ninput wire update;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan CAPTURE\" *)\ninput wire capture;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RESET\" *)\ninput wire reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RUNTEST\" *)\ninput wire runtest;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TCK\" *)\ninput wire tck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TMS\" *)\ninput wire tms;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDI\" *)\ninput wire tdi;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SEL\" *)\ninput wire sel;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SHIFT\" *)\ninput wire shift;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan DRCK\" *)\ninput wire drck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDO\" *)\noutput wire tdo;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan BSCANID_EN\" *)\ninput wire bscanid_en;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME signal_clock, FREQ_HZ 100000000, PHASE 0.000\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 signal_clock CLK\" *)\ninput wire clk;\n\n  xsdbm_v3_0_0_xsdbm #(\n    .C_FIFO_STYLE(\"SUBCORE\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_MAJOR_VERSION(14),\n    .C_MINOR_VERSION(1),\n    .C_BUILD_REVISION(0),\n    .C_CORE_MAJOR_VER(1),\n    .C_CORE_MINOR_VER(0),\n    .C_CORE_MINOR_ALPHA_VER(97),\n    .C_XSDB_NUM_SLAVES(0),\n    .C_XSDB_PERIOD_INT(10),\n    .C_XSDB_PERIOD_FRC(0),\n    .C_USE_BUFR(0),\n    .C_DCLK_HAS_RESET(0),\n    .C_EN_INT_SIM(1),\n    .C_CORE_TYPE(1),\n    .C_USER_SCAN_CHAIN(1),\n    .C_CLKFBOUT_MULT_F(4.000),\n    .C_DIVCLK_DIVIDE(1),\n    .C_CLKOUT0_DIVIDE_F(12.000),\n    .C_CLK_INPUT_FREQ_HZ(300000000),\n    .C_ENABLE_CLK_DIVIDER(0),\n    .C_USE_EXT_BSCAN(1),\n    .C_USE_STARTUP_CLK(0),\n    .C_EN_BSCANID_VEC(0),\n    .C_TWO_PRIM_MODE(0),\n    .C_USER_SCAN_CHAIN1(1),\n    .C_BSCANID(76546592),\n    .C_BSCAN_MODE(0),\n    .C_BSCAN_MODE_WITH_CORE(0),\n    .C_NUM_BSCAN_MASTER_PORTS(0)\n  ) inst (\n    .sl_iport0_o(),\n    .sl_iport1_o(),\n    .sl_iport2_o(),\n    .sl_iport3_o(),\n    .sl_iport4_o(),\n    .sl_iport5_o(),\n    .sl_iport6_o(),\n    .sl_iport7_o(),\n    .sl_iport8_o(),\n    .sl_iport9_o(),\n    .sl_iport10_o(),\n    .sl_iport11_o(),\n    .sl_iport12_o(),\n    .sl_iport13_o(),\n    .sl_iport14_o(),\n    .sl_iport15_o(),\n    .sl_iport16_o(),\n    .sl_iport17_o(),\n    .sl_iport18_o(),\n    .sl_iport19_o(),\n    .sl_iport20_o(),\n    .sl_iport21_o(),\n    .sl_iport22_o(),\n    .sl_iport23_o(),\n    .sl_iport24_o(),\n    .sl_iport25_o(),\n    .sl_iport26_o(),\n    .sl_iport27_o(),\n    .sl_iport28_o(),\n    .sl_iport29_o(),\n    .sl_iport30_o(),\n    .sl_iport31_o(),\n    .sl_iport32_o(),\n    .sl_iport33_o(),\n    .sl_iport34_o(),\n    .sl_iport35_o(),\n    .sl_iport36_o(),\n    .sl_iport37_o(),\n    .sl_iport38_o(),\n    .sl_iport39_o(),\n    .sl_iport40_o(),\n    .sl_iport41_o(),\n    .sl_iport42_o(),\n    .sl_iport43_o(),\n    .sl_iport44_o(),\n    .sl_iport45_o(),\n    .sl_iport46_o(),\n    .sl_iport47_o(),\n    .sl_iport48_o(),\n    .sl_iport49_o(),\n    .sl_iport50_o(),\n    .sl_iport51_o(),\n    .sl_iport52_o(),\n    .sl_iport53_o(),\n    .sl_iport54_o(),\n    .sl_iport55_o(),\n    .sl_iport56_o(),\n    .sl_iport57_o(),\n    .sl_iport58_o(),\n    .sl_iport59_o(),\n    .sl_iport60_o(),\n    .sl_iport61_o(),\n    .sl_iport62_o(),\n    .sl_iport63_o(),\n    .sl_iport64_o(),\n    .sl_iport65_o(),\n    .sl_iport66_o(),\n    .sl_iport67_o(),\n    .sl_iport68_o(),\n    .sl_iport69_o(),\n    .sl_iport70_o(),\n    .sl_iport71_o(),\n    .sl_iport72_o(),\n    .sl_iport73_o(),\n    .sl_iport74_o(),\n    .sl_iport75_o(),\n    .sl_iport76_o(),\n    .sl_iport77_o(),\n    .sl_iport78_o(),\n    .sl_iport79_o(),\n    .sl_iport80_o(),\n    .sl_iport81_o(),\n    .sl_iport82_o(),\n    .sl_iport83_o(),\n    .sl_iport84_o(),\n    .sl_iport85_o(),\n    .sl_iport86_o(),\n    .sl_iport87_o(),\n    .sl_iport88_o(),\n    .sl_iport89_o(),\n    .sl_iport90_o(),\n    .sl_iport91_o(),\n    .sl_iport92_o(),\n    .sl_iport93_o(),\n    .sl_iport94_o(),\n    .sl_iport95_o(),\n    .sl_iport96_o(),\n    .sl_iport97_o(),\n    .sl_iport98_o(),\n    .sl_iport99_o(),\n    .sl_iport100_o(),\n    .sl_iport101_o(),\n    .sl_iport102_o(),\n    .sl_iport103_o(),\n    .sl_iport104_o(),\n    .sl_iport105_o(),\n    .sl_iport106_o(),\n    .sl_iport107_o(),\n    .sl_iport108_o(),\n    .sl_iport109_o(),\n    .sl_iport110_o(),\n    .sl_iport111_o(),\n    .sl_iport112_o(),\n    .sl_iport113_o(),\n    .sl_iport114_o(),\n    .sl_iport115_o(),\n    .sl_iport116_o(),\n    .sl_iport117_o(),\n    .sl_iport118_o(),\n    .sl_iport119_o(),\n    .sl_iport120_o(),\n    .sl_iport121_o(),\n    .sl_iport122_o(),\n    .sl_iport123_o(),\n    .sl_iport124_o(),\n    .sl_iport125_o(),\n    .sl_iport126_o(),\n    .sl_iport127_o(),\n    .sl_iport128_o(),\n    .sl_iport129_o(),\n    .sl_iport130_o(),\n    .sl_iport131_o(),\n    .sl_iport132_o(),\n    .sl_iport133_o(),\n    .sl_iport134_o(),\n    .sl_iport135_o(),\n    .sl_iport136_o(),\n    .sl_iport137_o(),\n    .sl_iport138_o(),\n    .sl_iport139_o(),\n    .sl_iport140_o(),\n    .sl_iport141_o(),\n    .sl_iport142_o(),\n    .sl_iport143_o(),\n    .sl_iport144_o(),\n    .sl_iport145_o(),\n    .sl_iport146_o(),\n    .sl_iport147_o(),\n    .sl_iport148_o(),\n    .sl_iport149_o(),\n    .sl_iport150_o(),\n    .sl_iport151_o(),\n    .sl_iport152_o(),\n    .sl_iport153_o(),\n    .sl_iport154_o(),\n    .sl_iport155_o(),\n    .sl_iport156_o(),\n    .sl_iport157_o(),\n    .sl_iport158_o(),\n    .sl_iport159_o(),\n    .sl_iport160_o(),\n    .sl_iport161_o(),\n    .sl_iport162_o(),\n    .sl_iport163_o(),\n    .sl_iport164_o(),\n    .sl_iport165_o(),\n    .sl_iport166_o(),\n    .sl_iport167_o(),\n    .sl_iport168_o(),\n    .sl_iport169_o(),\n    .sl_iport170_o(),\n    .sl_iport171_o(),\n    .sl_iport172_o(),\n    .sl_iport173_o(),\n    .sl_iport174_o(),\n    .sl_iport175_o(),\n    .sl_iport176_o(),\n    .sl_iport177_o(),\n    .sl_iport178_o(),\n    .sl_iport179_o(),\n    .sl_iport180_o(),\n    .sl_iport181_o(),\n    .sl_iport182_o(),\n    .sl_iport183_o(),\n    .sl_iport184_o(),\n    .sl_iport185_o(),\n    .sl_iport186_o(),\n    .sl_iport187_o(),\n    .sl_iport188_o(),\n    .sl_iport189_o(),\n    .sl_iport190_o(),\n    .sl_iport191_o(),\n    .sl_iport192_o(),\n    .sl_iport193_o(),\n    .sl_iport194_o(),\n    .sl_iport195_o(),\n    .sl_iport196_o(),\n    .sl_iport197_o(),\n    .sl_iport198_o(),\n    .sl_iport199_o(),\n    .sl_iport200_o(),\n    .sl_iport201_o(),\n    .sl_iport202_o(),\n    .sl_iport203_o(),\n    .sl_iport204_o(),\n    .sl_iport205_o(),\n    .sl_iport206_o(),\n    .sl_iport207_o(),\n    .sl_iport208_o(),\n    .sl_iport209_o(),\n    .sl_iport210_o(),\n    .sl_iport211_o(),\n    .sl_iport212_o(),\n    .sl_iport213_o(),\n    .sl_iport214_o(),\n    .sl_iport215_o(),\n    .sl_iport216_o(),\n    .sl_iport217_o(),\n    .sl_iport218_o(),\n    .sl_iport219_o(),\n    .sl_iport220_o(),\n    .sl_iport221_o(),\n    .sl_iport222_o(),\n    .sl_iport223_o(),\n    .sl_iport224_o(),\n    .sl_iport225_o(),\n    .sl_iport226_o(),\n    .sl_iport227_o(),\n    .sl_iport228_o(),\n    .sl_iport229_o(),\n    .sl_iport230_o(),\n    .sl_iport231_o(),\n    .sl_iport232_o(),\n    .sl_iport233_o(),\n    .sl_iport234_o(),\n    .sl_iport235_o(),\n    .sl_iport236_o(),\n    .sl_iport237_o(),\n    .sl_iport238_o(),\n    .sl_iport239_o(),\n    .sl_iport240_o(),\n    .sl_iport241_o(),\n    .sl_iport242_o(),\n    .sl_iport243_o(),\n    .sl_iport244_o(),\n    .sl_iport245_o(),\n    .sl_iport246_o(),\n    .sl_iport247_o(),\n    .sl_iport248_o(),\n    .sl_iport249_o(),\n    .sl_iport250_o(),\n    .sl_iport251_o(),\n    .sl_iport252_o(),\n    .sl_iport253_o(),\n    .sl_iport254_o(),\n    .sl_iport255_o(),\n    .sl_oport0_i(1'B0),\n    .sl_oport1_i(1'B0),\n    .sl_oport2_i(1'B0),\n    .sl_oport3_i(1'B0),\n    .sl_oport4_i(1'B0),\n    .sl_oport5_i(1'B0),\n    .sl_oport6_i(1'B0),\n    .sl_oport7_i(1'B0),\n    .sl_oport8_i(1'B0),\n    .sl_oport9_i(1'B0),\n    .sl_oport10_i(1'B0),\n    .sl_oport11_i(1'B0),\n    .sl_oport12_i(1'B0),\n    .sl_oport13_i(1'B0),\n    .sl_oport14_i(1'B0),\n    .sl_oport15_i(1'B0),\n    .sl_oport16_i(1'B0),\n    .sl_oport17_i(1'B0),\n    .sl_oport18_i(1'B0),\n    .sl_oport19_i(1'B0),\n    .sl_oport20_i(1'B0),\n    .sl_oport21_i(1'B0),\n    .sl_oport22_i(1'B0),\n    .sl_oport23_i(1'B0),\n    .sl_oport24_i(1'B0),\n    .sl_oport25_i(1'B0),\n    .sl_oport26_i(1'B0),\n    .sl_oport27_i(1'B0),\n    .sl_oport28_i(1'B0),\n    .sl_oport29_i(1'B0),\n    .sl_oport30_i(1'B0),\n    .sl_oport31_i(1'B0),\n    .sl_oport32_i(1'B0),\n    .sl_oport33_i(1'B0),\n    .sl_oport34_i(1'B0),\n    .sl_oport35_i(1'B0),\n    .sl_oport36_i(1'B0),\n    .sl_oport37_i(1'B0),\n    .sl_oport38_i(1'B0),\n    .sl_oport39_i(1'B0),\n    .sl_oport40_i(1'B0),\n    .sl_oport41_i(1'B0),\n    .sl_oport42_i(1'B0),\n    .sl_oport43_i(1'B0),\n    .sl_oport44_i(1'B0),\n    .sl_oport45_i(1'B0),\n    .sl_oport46_i(1'B0),\n    .sl_oport47_i(1'B0),\n    .sl_oport48_i(1'B0),\n    .sl_oport49_i(1'B0),\n    .sl_oport50_i(1'B0),\n    .sl_oport51_i(1'B0),\n    .sl_oport52_i(1'B0),\n    .sl_oport53_i(1'B0),\n    .sl_oport54_i(1'B0),\n    .sl_oport55_i(1'B0),\n    .sl_oport56_i(1'B0),\n    .sl_oport57_i(1'B0),\n    .sl_oport58_i(1'B0),\n    .sl_oport59_i(1'B0),\n    .sl_oport60_i(1'B0),\n    .sl_oport61_i(1'B0),\n    .sl_oport62_i(1'B0),\n    .sl_oport63_i(1'B0),\n    .sl_oport64_i(1'B0),\n    .sl_oport65_i(1'B0),\n    .sl_oport66_i(1'B0),\n    .sl_oport67_i(1'B0),\n    .sl_oport68_i(1'B0),\n    .sl_oport69_i(1'B0),\n    .sl_oport70_i(1'B0),\n    .sl_oport71_i(1'B0),\n    .sl_oport72_i(1'B0),\n    .sl_oport73_i(1'B0),\n    .sl_oport74_i(1'B0),\n    .sl_oport75_i(1'B0),\n    .sl_oport76_i(1'B0),\n    .sl_oport77_i(1'B0),\n    .sl_oport78_i(1'B0),\n    .sl_oport79_i(1'B0),\n    .sl_oport80_i(1'B0),\n    .sl_oport81_i(1'B0),\n    .sl_oport82_i(1'B0),\n    .sl_oport83_i(1'B0),\n    .sl_oport84_i(1'B0),\n    .sl_oport85_i(1'B0),\n    .sl_oport86_i(1'B0),\n    .sl_oport87_i(1'B0),\n    .sl_oport88_i(1'B0),\n    .sl_oport89_i(1'B0),\n    .sl_oport90_i(1'B0),\n    .sl_oport91_i(1'B0),\n    .sl_oport92_i(1'B0),\n    .sl_oport93_i(1'B0),\n    .sl_oport94_i(1'B0),\n    .sl_oport95_i(1'B0),\n    .sl_oport96_i(1'B0),\n    .sl_oport97_i(1'B0),\n    .sl_oport98_i(1'B0),\n    .sl_oport99_i(1'B0),\n    .sl_oport100_i(1'B0),\n    .sl_oport101_i(1'B0),\n    .sl_oport102_i(1'B0),\n    .sl_oport103_i(1'B0),\n    .sl_oport104_i(1'B0),\n    .sl_oport105_i(1'B0),\n    .sl_oport106_i(1'B0),\n    .sl_oport107_i(1'B0),\n    .sl_oport108_i(1'B0),\n    .sl_oport109_i(1'B0),\n    .sl_oport110_i(1'B0),\n    .sl_oport111_i(1'B0),\n    .sl_oport112_i(1'B0),\n    .sl_oport113_i(1'B0),\n    .sl_oport114_i(1'B0),\n    .sl_oport115_i(1'B0),\n    .sl_oport116_i(1'B0),\n    .sl_oport117_i(1'B0),\n    .sl_oport118_i(1'B0),\n    .sl_oport119_i(1'B0),\n    .sl_oport120_i(1'B0),\n    .sl_oport121_i(1'B0),\n    .sl_oport122_i(1'B0),\n    .sl_oport123_i(1'B0),\n    .sl_oport124_i(1'B0),\n    .sl_oport125_i(1'B0),\n    .sl_oport126_i(1'B0),\n    .sl_oport127_i(1'B0),\n    .sl_oport128_i(1'B0),\n    .sl_oport129_i(1'B0),\n    .sl_oport130_i(1'B0),\n    .sl_oport131_i(1'B0),\n    .sl_oport132_i(1'B0),\n    .sl_oport133_i(1'B0),\n    .sl_oport134_i(1'B0),\n    .sl_oport135_i(1'B0),\n    .sl_oport136_i(1'B0),\n    .sl_oport137_i(1'B0),\n    .sl_oport138_i(1'B0),\n    .sl_oport139_i(1'B0),\n    .sl_oport140_i(1'B0),\n    .sl_oport141_i(1'B0),\n    .sl_oport142_i(1'B0),\n    .sl_oport143_i(1'B0),\n    .sl_oport144_i(1'B0),\n    .sl_oport145_i(1'B0),\n    .sl_oport146_i(1'B0),\n    .sl_oport147_i(1'B0),\n    .sl_oport148_i(1'B0),\n    .sl_oport149_i(1'B0),\n    .sl_oport150_i(1'B0),\n    .sl_oport151_i(1'B0),\n    .sl_oport152_i(1'B0),\n    .sl_oport153_i(1'B0),\n    .sl_oport154_i(1'B0),\n    .sl_oport155_i(1'B0),\n    .sl_oport156_i(1'B0),\n    .sl_oport157_i(1'B0),\n    .sl_oport158_i(1'B0),\n    .sl_oport159_i(1'B0),\n    .sl_oport160_i(1'B0),\n    .sl_oport161_i(1'B0),\n    .sl_oport162_i(1'B0),\n    .sl_oport163_i(1'B0),\n    .sl_oport164_i(1'B0),\n    .sl_oport165_i(1'B0),\n    .sl_oport166_i(1'B0),\n    .sl_oport167_i(1'B0),\n    .sl_oport168_i(1'B0),\n    .sl_oport169_i(1'B0),\n    .sl_oport170_i(1'B0),\n    .sl_oport171_i(1'B0),\n    .sl_oport172_i(1'B0),\n    .sl_oport173_i(1'B0),\n    .sl_oport174_i(1'B0),\n    .sl_oport175_i(1'B0),\n    .sl_oport176_i(1'B0),\n    .sl_oport177_i(1'B0),\n    .sl_oport178_i(1'B0),\n    .sl_oport179_i(1'B0),\n    .sl_oport180_i(1'B0),\n    .sl_oport181_i(1'B0),\n    .sl_oport182_i(1'B0),\n    .sl_oport183_i(1'B0),\n    .sl_oport184_i(1'B0),\n    .sl_oport185_i(1'B0),\n    .sl_oport186_i(1'B0),\n    .sl_oport187_i(1'B0),\n    .sl_oport188_i(1'B0),\n    .sl_oport189_i(1'B0),\n    .sl_oport190_i(1'B0),\n    .sl_oport191_i(1'B0),\n    .sl_oport192_i(1'B0),\n    .sl_oport193_i(1'B0),\n    .sl_oport194_i(1'B0),\n    .sl_oport195_i(1'B0),\n    .sl_oport196_i(1'B0),\n    .sl_oport197_i(1'B0),\n    .sl_oport198_i(1'B0),\n    .sl_oport199_i(1'B0),\n    .sl_oport200_i(1'B0),\n    .sl_oport201_i(1'B0),\n    .sl_oport202_i(1'B0),\n    .sl_oport203_i(1'B0),\n    .sl_oport204_i(1'B0),\n    .sl_oport205_i(1'B0),\n    .sl_oport206_i(1'B0),\n    .sl_oport207_i(1'B0),\n    .sl_oport208_i(1'B0),\n    .sl_oport209_i(1'B0),\n    .sl_oport210_i(1'B0),\n    .sl_oport211_i(1'B0),\n    .sl_oport212_i(1'B0),\n    .sl_oport213_i(1'B0),\n    .sl_oport214_i(1'B0),\n    .sl_oport215_i(1'B0),\n    .sl_oport216_i(1'B0),\n    .sl_oport217_i(1'B0),\n    .sl_oport218_i(1'B0),\n    .sl_oport219_i(1'B0),\n    .sl_oport220_i(1'B0),\n    .sl_oport221_i(1'B0),\n    .sl_oport222_i(1'B0),\n    .sl_oport223_i(1'B0),\n    .sl_oport224_i(1'B0),\n    .sl_oport225_i(1'B0),\n    .sl_oport226_i(1'B0),\n    .sl_oport227_i(1'B0),\n    .sl_oport228_i(1'B0),\n    .sl_oport229_i(1'B0),\n    .sl_oport230_i(1'B0),\n    .sl_oport231_i(1'B0),\n    .sl_oport232_i(1'B0),\n    .sl_oport233_i(1'B0),\n    .sl_oport234_i(1'B0),\n    .sl_oport235_i(1'B0),\n    .sl_oport236_i(1'B0),\n    .sl_oport237_i(1'B0),\n    .sl_oport238_i(1'B0),\n    .sl_oport239_i(1'B0),\n    .sl_oport240_i(1'B0),\n    .sl_oport241_i(1'B0),\n    .sl_oport242_i(1'B0),\n    .sl_oport243_i(1'B0),\n    .sl_oport244_i(1'B0),\n    .sl_oport245_i(1'B0),\n    .sl_oport246_i(1'B0),\n    .sl_oport247_i(1'B0),\n    .sl_oport248_i(1'B0),\n    .sl_oport249_i(1'B0),\n    .sl_oport250_i(1'B0),\n    .sl_oport251_i(1'B0),\n    .sl_oport252_i(1'B0),\n    .sl_oport253_i(1'B0),\n    .sl_oport254_i(1'B0),\n    .sl_oport255_i(1'B0),\n    .update_0(),\n    .capture_0(),\n    .reset_0(),\n    .runtest_0(),\n    .tms_0(),\n    .tck_0(),\n    .tdi_0(),\n    .sel_0(),\n    .shift_0(),\n    .drck_0(),\n    .tdo_0(1'B0),\n    .update_1(),\n    .capture_1(),\n    .reset_1(),\n    .runtest_1(),\n    .tms_1(),\n    .tck_1(),\n    .tdi_1(),\n    .sel_1(),\n    .shift_1(),\n    .drck_1(),\n    .tdo_1(1'B0),\n    .update_2(),\n    .capture_2(),\n    .reset_2(),\n    .runtest_2(),\n    .tms_2(),\n    .tck_2(),\n    .tdi_2(),\n    .sel_2(),\n    .shift_2(),\n    .drck_2(),\n    .tdo_2(1'B0),\n    .update_3(),\n    .capture_3(),\n    .reset_3(),\n    .runtest_3(),\n    .tms_3(),\n    .tck_3(),\n    .tdi_3(),\n    .sel_3(),\n    .shift_3(),\n    .drck_3(),\n    .tdo_3(1'B0),\n    .update_4(),\n    .capture_4(),\n    .reset_4(),\n    .runtest_4(),\n    .tms_4(),\n    .tck_4(),\n    .tdi_4(),\n    .sel_4(),\n    .shift_4(),\n    .drck_4(),\n    .tdo_4(1'B0),\n    .update_5(),\n    .capture_5(),\n    .reset_5(),\n    .runtest_5(),\n    .tms_5(),\n    .tck_5(),\n    .tdi_5(),\n    .sel_5(),\n    .shift_5(),\n    .drck_5(),\n    .tdo_5(1'B0),\n    .update_6(),\n    .capture_6(),\n    .reset_6(),\n    .runtest_6(),\n    .tms_6(),\n    .tck_6(),\n    .tdi_6(),\n    .sel_6(),\n    .shift_6(),\n    .drck_6(),\n    .tdo_6(1'B0),\n    .update_7(),\n    .capture_7(),\n    .reset_7(),\n    .runtest_7(),\n    .tms_7(),\n    .tck_7(),\n    .tdi_7(),\n    .sel_7(),\n    .shift_7(),\n    .drck_7(),\n    .tdo_7(1'B0),\n    .update_8(),\n    .capture_8(),\n    .reset_8(),\n    .runtest_8(),\n    .tms_8(),\n    .tck_8(),\n    .tdi_8(),\n    .sel_8(),\n    .shift_8(),\n    .drck_8(),\n    .tdo_8(1'B0),\n    .update_9(),\n    .capture_9(),\n    .reset_9(),\n    .runtest_9(),\n    .tms_9(),\n    .tck_9(),\n    .tdi_9(),\n    .sel_9(),\n    .shift_9(),\n    .drck_9(),\n    .tdo_9(1'B0),\n    .update_10(),\n    .capture_10(),\n    .reset_10(),\n    .runtest_10(),\n    .tms_10(),\n    .tck_10(),\n    .tdi_10(),\n    .sel_10(),\n    .shift_10(),\n    .drck_10(),\n    .tdo_10(1'B0),\n    .update_11(),\n    .capture_11(),\n    .reset_11(),\n    .runtest_11(),\n    .tms_11(),\n    .tck_11(),\n    .tdi_11(),\n    .sel_11(),\n    .shift_11(),\n    .drck_11(),\n    .tdo_11(1'B0),\n    .update_12(),\n    .capture_12(),\n    .reset_12(),\n    .runtest_12(),\n    .tms_12(),\n    .tck_12(),\n    .tdi_12(),\n    .sel_12(),\n    .shift_12(),\n    .drck_12(),\n    .tdo_12(1'B0),\n    .update_13(),\n    .capture_13(),\n    .reset_13(),\n    .runtest_13(),\n    .tms_13(),\n    .tck_13(),\n    .tdi_13(),\n    .sel_13(),\n    .shift_13(),\n    .drck_13(),\n    .tdo_13(1'B0),\n    .update_14(),\n    .capture_14(),\n    .reset_14(),\n    .runtest_14(),\n    .tms_14(),\n    .tck_14(),\n    .tdi_14(),\n    .sel_14(),\n    .shift_14(),\n    .drck_14(),\n    .tdo_14(1'B0),\n    .update_15(),\n    .capture_15(),\n    .reset_15(),\n    .runtest_15(),\n    .tms_15(),\n    .tck_15(),\n    .tdi_15(),\n    .sel_15(),\n    .shift_15(),\n    .drck_15(),\n    .tdo_15(1'B0),\n    .bscanid_en_0(),\n    .bscanid_en_1(),\n    .bscanid_en_2(),\n    .bscanid_en_3(),\n    .bscanid_en_4(),\n    .bscanid_en_5(),\n    .bscanid_en_6(),\n    .bscanid_en_7(),\n    .bscanid_en_8(),\n    .bscanid_en_9(),\n    .bscanid_en_10(),\n    .bscanid_en_11(),\n    .bscanid_en_12(),\n    .bscanid_en_13(),\n    .bscanid_en_14(),\n    .bscanid_en_15(),\n    .bscanid_0(32'B0),\n    .bscanid_1(32'B0),\n    .bscanid_2(32'B0),\n    .bscanid_3(32'B0),\n    .bscanid_4(32'B0),\n    .bscanid_5(32'B0),\n    .bscanid_6(32'B0),\n    .bscanid_7(32'B0),\n    .bscanid_8(32'B0),\n    .bscanid_9(32'B0),\n    .bscanid_10(32'B0),\n    .bscanid_11(32'B0),\n    .bscanid_12(32'B0),\n    .bscanid_13(32'B0),\n    .bscanid_14(32'B0),\n    .bscanid_15(32'B0),\n    .update(update),\n    .capture(capture),\n    .reset(reset),\n    .runtest(runtest),\n    .tck(tck),\n    .tms(tms),\n    .tdi(tdi),\n    .sel(sel),\n    .shift(shift),\n    .drck(drck),\n    .tdo(tdo),\n    .bscanid_en(bscanid_en),\n    .bscanid(),\n    .clk(clk)\n  );\nendmodule\n", "num_lines": 868}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:xsdbm:3.0\n// IP Revision: 0\n\n(* X_CORE_INFO = \"xsdbm_v3_0_0_xsdbm,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"bd_a493_xsdbm_0,xsdbm_v3_0_0_xsdbm,{}\" *)\n(* CORE_GENERATION_INFO = \"bd_a493_xsdbm_0,xsdbm_v3_0_0_xsdbm,{x_ipProduct=Vivado 2017.4.op,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xsdbm,x_ipVersion=3.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FIFO_STYLE=SUBCORE,C_XDEVICEFAMILY=virtexuplus,C_MAJOR_VERSION=14,C_MINOR_VERSION=1,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=1,C_CORE_MINOR_VER=0,C_CORE_MINOR_ALPHA_VER=97,C_XSDB_NUM_SLAVES=0,C_XSDB_PERIOD_INT=10,C_XSDB_PERIOD_FRC=0,C_USE_BUFR=0,C_DCLK_HAS_RESET=0,C_EN_INT_SIM=1,C_CORE_TYPE=1,C_USER_SCAN_CH\\\nAIN=1,C_CLKFBOUT_MULT_F=4.000,C_DIVCLK_DIVIDE=1,C_CLKOUT0_DIVIDE_F=12.000,C_CLK_INPUT_FREQ_HZ=300000000,C_ENABLE_CLK_DIVIDER=0,C_USE_EXT_BSCAN=1,C_USE_STARTUP_CLK=0,C_EN_BSCANID_VEC=0,C_TWO_PRIM_MODE=0,C_USER_SCAN_CHAIN1=1,C_BSCANID=76546592,C_BSCAN_MODE=0,C_BSCAN_MODE_WITH_CORE=0,C_NUM_BSCAN_MASTER_PORTS=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_a493_xsdbm_0 (\n  update,\n  capture,\n  reset,\n  runtest,\n  tck,\n  tms,\n  tdi,\n  sel,\n  shift,\n  drck,\n  tdo,\n  bscanid_en,\n  clk\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan UPDATE\" *)\ninput wire update;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan CAPTURE\" *)\ninput wire capture;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RESET\" *)\ninput wire reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RUNTEST\" *)\ninput wire runtest;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TCK\" *)\ninput wire tck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TMS\" *)\ninput wire tms;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDI\" *)\ninput wire tdi;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SEL\" *)\ninput wire sel;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SHIFT\" *)\ninput wire shift;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan DRCK\" *)\ninput wire drck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDO\" *)\noutput wire tdo;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan BSCANID_EN\" *)\ninput wire bscanid_en;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME signal_clock, FREQ_HZ 100000000, PHASE 0.000\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 signal_clock CLK\" *)\ninput wire clk;\n\n  xsdbm_v3_0_0_xsdbm #(\n    .C_FIFO_STYLE(\"SUBCORE\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_MAJOR_VERSION(14),\n    .C_MINOR_VERSION(1),\n    .C_BUILD_REVISION(0),\n    .C_CORE_MAJOR_VER(1),\n    .C_CORE_MINOR_VER(0),\n    .C_CORE_MINOR_ALPHA_VER(97),\n    .C_XSDB_NUM_SLAVES(0),\n    .C_XSDB_PERIOD_INT(10),\n    .C_XSDB_PERIOD_FRC(0),\n    .C_USE_BUFR(0),\n    .C_DCLK_HAS_RESET(0),\n    .C_EN_INT_SIM(1),\n    .C_CORE_TYPE(1),\n    .C_USER_SCAN_CHAIN(1),\n    .C_CLKFBOUT_MULT_F(4.000),\n    .C_DIVCLK_DIVIDE(1),\n    .C_CLKOUT0_DIVIDE_F(12.000),\n    .C_CLK_INPUT_FREQ_HZ(300000000),\n    .C_ENABLE_CLK_DIVIDER(0),\n    .C_USE_EXT_BSCAN(1),\n    .C_USE_STARTUP_CLK(0),\n    .C_EN_BSCANID_VEC(0),\n    .C_TWO_PRIM_MODE(0),\n    .C_USER_SCAN_CHAIN1(1),\n    .C_BSCANID(76546592),\n    .C_BSCAN_MODE(0),\n    .C_BSCAN_MODE_WITH_CORE(0),\n    .C_NUM_BSCAN_MASTER_PORTS(0)\n  ) inst (\n    .sl_iport0_o(),\n    .sl_iport1_o(),\n    .sl_iport2_o(),\n    .sl_iport3_o(),\n    .sl_iport4_o(),\n    .sl_iport5_o(),\n    .sl_iport6_o(),\n    .sl_iport7_o(),\n    .sl_iport8_o(),\n    .sl_iport9_o(),\n    .sl_iport10_o(),\n    .sl_iport11_o(),\n    .sl_iport12_o(),\n    .sl_iport13_o(),\n    .sl_iport14_o(),\n    .sl_iport15_o(),\n    .sl_iport16_o(),\n    .sl_iport17_o(),\n    .sl_iport18_o(),\n    .sl_iport19_o(),\n    .sl_iport20_o(),\n    .sl_iport21_o(),\n    .sl_iport22_o(),\n    .sl_iport23_o(),\n    .sl_iport24_o(),\n    .sl_iport25_o(),\n    .sl_iport26_o(),\n    .sl_iport27_o(),\n    .sl_iport28_o(),\n    .sl_iport29_o(),\n    .sl_iport30_o(),\n    .sl_iport31_o(),\n    .sl_iport32_o(),\n    .sl_iport33_o(),\n    .sl_iport34_o(),\n    .sl_iport35_o(),\n    .sl_iport36_o(),\n    .sl_iport37_o(),\n    .sl_iport38_o(),\n    .sl_iport39_o(),\n    .sl_iport40_o(),\n    .sl_iport41_o(),\n    .sl_iport42_o(),\n    .sl_iport43_o(),\n    .sl_iport44_o(),\n    .sl_iport45_o(),\n    .sl_iport46_o(),\n    .sl_iport47_o(),\n    .sl_iport48_o(),\n    .sl_iport49_o(),\n    .sl_iport50_o(),\n    .sl_iport51_o(),\n    .sl_iport52_o(),\n    .sl_iport53_o(),\n    .sl_iport54_o(),\n    .sl_iport55_o(),\n    .sl_iport56_o(),\n    .sl_iport57_o(),\n    .sl_iport58_o(),\n    .sl_iport59_o(),\n    .sl_iport60_o(),\n    .sl_iport61_o(),\n    .sl_iport62_o(),\n    .sl_iport63_o(),\n    .sl_iport64_o(),\n    .sl_iport65_o(),\n    .sl_iport66_o(),\n    .sl_iport67_o(),\n    .sl_iport68_o(),\n    .sl_iport69_o(),\n    .sl_iport70_o(),\n    .sl_iport71_o(),\n    .sl_iport72_o(),\n    .sl_iport73_o(),\n    .sl_iport74_o(),\n    .sl_iport75_o(),\n    .sl_iport76_o(),\n    .sl_iport77_o(),\n    .sl_iport78_o(),\n    .sl_iport79_o(),\n    .sl_iport80_o(),\n    .sl_iport81_o(),\n    .sl_iport82_o(),\n    .sl_iport83_o(),\n    .sl_iport84_o(),\n    .sl_iport85_o(),\n    .sl_iport86_o(),\n    .sl_iport87_o(),\n    .sl_iport88_o(),\n    .sl_iport89_o(),\n    .sl_iport90_o(),\n    .sl_iport91_o(),\n    .sl_iport92_o(),\n    .sl_iport93_o(),\n    .sl_iport94_o(),\n    .sl_iport95_o(),\n    .sl_iport96_o(),\n    .sl_iport97_o(),\n    .sl_iport98_o(),\n    .sl_iport99_o(),\n    .sl_iport100_o(),\n    .sl_iport101_o(),\n    .sl_iport102_o(),\n    .sl_iport103_o(),\n    .sl_iport104_o(),\n    .sl_iport105_o(),\n    .sl_iport106_o(),\n    .sl_iport107_o(),\n    .sl_iport108_o(),\n    .sl_iport109_o(),\n    .sl_iport110_o(),\n    .sl_iport111_o(),\n    .sl_iport112_o(),\n    .sl_iport113_o(),\n    .sl_iport114_o(),\n    .sl_iport115_o(),\n    .sl_iport116_o(),\n    .sl_iport117_o(),\n    .sl_iport118_o(),\n    .sl_iport119_o(),\n    .sl_iport120_o(),\n    .sl_iport121_o(),\n    .sl_iport122_o(),\n    .sl_iport123_o(),\n    .sl_iport124_o(),\n    .sl_iport125_o(),\n    .sl_iport126_o(),\n    .sl_iport127_o(),\n    .sl_iport128_o(),\n    .sl_iport129_o(),\n    .sl_iport130_o(),\n    .sl_iport131_o(),\n    .sl_iport132_o(),\n    .sl_iport133_o(),\n    .sl_iport134_o(),\n    .sl_iport135_o(),\n    .sl_iport136_o(),\n    .sl_iport137_o(),\n    .sl_iport138_o(),\n    .sl_iport139_o(),\n    .sl_iport140_o(),\n    .sl_iport141_o(),\n    .sl_iport142_o(),\n    .sl_iport143_o(),\n    .sl_iport144_o(),\n    .sl_iport145_o(),\n    .sl_iport146_o(),\n    .sl_iport147_o(),\n    .sl_iport148_o(),\n    .sl_iport149_o(),\n    .sl_iport150_o(),\n    .sl_iport151_o(),\n    .sl_iport152_o(),\n    .sl_iport153_o(),\n    .sl_iport154_o(),\n    .sl_iport155_o(),\n    .sl_iport156_o(),\n    .sl_iport157_o(),\n    .sl_iport158_o(),\n    .sl_iport159_o(),\n    .sl_iport160_o(),\n    .sl_iport161_o(),\n    .sl_iport162_o(),\n    .sl_iport163_o(),\n    .sl_iport164_o(),\n    .sl_iport165_o(),\n    .sl_iport166_o(),\n    .sl_iport167_o(),\n    .sl_iport168_o(),\n    .sl_iport169_o(),\n    .sl_iport170_o(),\n    .sl_iport171_o(),\n    .sl_iport172_o(),\n    .sl_iport173_o(),\n    .sl_iport174_o(),\n    .sl_iport175_o(),\n    .sl_iport176_o(),\n    .sl_iport177_o(),\n    .sl_iport178_o(),\n    .sl_iport179_o(),\n    .sl_iport180_o(),\n    .sl_iport181_o(),\n    .sl_iport182_o(),\n    .sl_iport183_o(),\n    .sl_iport184_o(),\n    .sl_iport185_o(),\n    .sl_iport186_o(),\n    .sl_iport187_o(),\n    .sl_iport188_o(),\n    .sl_iport189_o(),\n    .sl_iport190_o(),\n    .sl_iport191_o(),\n    .sl_iport192_o(),\n    .sl_iport193_o(),\n    .sl_iport194_o(),\n    .sl_iport195_o(),\n    .sl_iport196_o(),\n    .sl_iport197_o(),\n    .sl_iport198_o(),\n    .sl_iport199_o(),\n    .sl_iport200_o(),\n    .sl_iport201_o(),\n    .sl_iport202_o(),\n    .sl_iport203_o(),\n    .sl_iport204_o(),\n    .sl_iport205_o(),\n    .sl_iport206_o(),\n    .sl_iport207_o(),\n    .sl_iport208_o(),\n    .sl_iport209_o(),\n    .sl_iport210_o(),\n    .sl_iport211_o(),\n    .sl_iport212_o(),\n    .sl_iport213_o(),\n    .sl_iport214_o(),\n    .sl_iport215_o(),\n    .sl_iport216_o(),\n    .sl_iport217_o(),\n    .sl_iport218_o(),\n    .sl_iport219_o(),\n    .sl_iport220_o(),\n    .sl_iport221_o(),\n    .sl_iport222_o(),\n    .sl_iport223_o(),\n    .sl_iport224_o(),\n    .sl_iport225_o(),\n    .sl_iport226_o(),\n    .sl_iport227_o(),\n    .sl_iport228_o(),\n    .sl_iport229_o(),\n    .sl_iport230_o(),\n    .sl_iport231_o(),\n    .sl_iport232_o(),\n    .sl_iport233_o(),\n    .sl_iport234_o(),\n    .sl_iport235_o(),\n    .sl_iport236_o(),\n    .sl_iport237_o(),\n    .sl_iport238_o(),\n    .sl_iport239_o(),\n    .sl_iport240_o(),\n    .sl_iport241_o(),\n    .sl_iport242_o(),\n    .sl_iport243_o(),\n    .sl_iport244_o(),\n    .sl_iport245_o(),\n    .sl_iport246_o(),\n    .sl_iport247_o(),\n    .sl_iport248_o(),\n    .sl_iport249_o(),\n    .sl_iport250_o(),\n    .sl_iport251_o(),\n    .sl_iport252_o(),\n    .sl_iport253_o(),\n    .sl_iport254_o(),\n    .sl_iport255_o(),\n    .sl_oport0_i(1'B0),\n    .sl_oport1_i(1'B0),\n    .sl_oport2_i(1'B0),\n    .sl_oport3_i(1'B0),\n    .sl_oport4_i(1'B0),\n    .sl_oport5_i(1'B0),\n    .sl_oport6_i(1'B0),\n    .sl_oport7_i(1'B0),\n    .sl_oport8_i(1'B0),\n    .sl_oport9_i(1'B0),\n    .sl_oport10_i(1'B0),\n    .sl_oport11_i(1'B0),\n    .sl_oport12_i(1'B0),\n    .sl_oport13_i(1'B0),\n    .sl_oport14_i(1'B0),\n    .sl_oport15_i(1'B0),\n    .sl_oport16_i(1'B0),\n    .sl_oport17_i(1'B0),\n    .sl_oport18_i(1'B0),\n    .sl_oport19_i(1'B0),\n    .sl_oport20_i(1'B0),\n    .sl_oport21_i(1'B0),\n    .sl_oport22_i(1'B0),\n    .sl_oport23_i(1'B0),\n    .sl_oport24_i(1'B0),\n    .sl_oport25_i(1'B0),\n    .sl_oport26_i(1'B0),\n    .sl_oport27_i(1'B0),\n    .sl_oport28_i(1'B0),\n    .sl_oport29_i(1'B0),\n    .sl_oport30_i(1'B0),\n    .sl_oport31_i(1'B0),\n    .sl_oport32_i(1'B0),\n    .sl_oport33_i(1'B0),\n    .sl_oport34_i(1'B0),\n    .sl_oport35_i(1'B0),\n    .sl_oport36_i(1'B0),\n    .sl_oport37_i(1'B0),\n    .sl_oport38_i(1'B0),\n    .sl_oport39_i(1'B0),\n    .sl_oport40_i(1'B0),\n    .sl_oport41_i(1'B0),\n    .sl_oport42_i(1'B0),\n    .sl_oport43_i(1'B0),\n    .sl_oport44_i(1'B0),\n    .sl_oport45_i(1'B0),\n    .sl_oport46_i(1'B0),\n    .sl_oport47_i(1'B0),\n    .sl_oport48_i(1'B0),\n    .sl_oport49_i(1'B0),\n    .sl_oport50_i(1'B0),\n    .sl_oport51_i(1'B0),\n    .sl_oport52_i(1'B0),\n    .sl_oport53_i(1'B0),\n    .sl_oport54_i(1'B0),\n    .sl_oport55_i(1'B0),\n    .sl_oport56_i(1'B0),\n    .sl_oport57_i(1'B0),\n    .sl_oport58_i(1'B0),\n    .sl_oport59_i(1'B0),\n    .sl_oport60_i(1'B0),\n    .sl_oport61_i(1'B0),\n    .sl_oport62_i(1'B0),\n    .sl_oport63_i(1'B0),\n    .sl_oport64_i(1'B0),\n    .sl_oport65_i(1'B0),\n    .sl_oport66_i(1'B0),\n    .sl_oport67_i(1'B0),\n    .sl_oport68_i(1'B0),\n    .sl_oport69_i(1'B0),\n    .sl_oport70_i(1'B0),\n    .sl_oport71_i(1'B0),\n    .sl_oport72_i(1'B0),\n    .sl_oport73_i(1'B0),\n    .sl_oport74_i(1'B0),\n    .sl_oport75_i(1'B0),\n    .sl_oport76_i(1'B0),\n    .sl_oport77_i(1'B0),\n    .sl_oport78_i(1'B0),\n    .sl_oport79_i(1'B0),\n    .sl_oport80_i(1'B0),\n    .sl_oport81_i(1'B0),\n    .sl_oport82_i(1'B0),\n    .sl_oport83_i(1'B0),\n    .sl_oport84_i(1'B0),\n    .sl_oport85_i(1'B0),\n    .sl_oport86_i(1'B0),\n    .sl_oport87_i(1'B0),\n    .sl_oport88_i(1'B0),\n    .sl_oport89_i(1'B0),\n    .sl_oport90_i(1'B0),\n    .sl_oport91_i(1'B0),\n    .sl_oport92_i(1'B0),\n    .sl_oport93_i(1'B0),\n    .sl_oport94_i(1'B0),\n    .sl_oport95_i(1'B0),\n    .sl_oport96_i(1'B0),\n    .sl_oport97_i(1'B0),\n    .sl_oport98_i(1'B0),\n    .sl_oport99_i(1'B0),\n    .sl_oport100_i(1'B0),\n    .sl_oport101_i(1'B0),\n    .sl_oport102_i(1'B0),\n    .sl_oport103_i(1'B0),\n    .sl_oport104_i(1'B0),\n    .sl_oport105_i(1'B0),\n    .sl_oport106_i(1'B0),\n    .sl_oport107_i(1'B0),\n    .sl_oport108_i(1'B0),\n    .sl_oport109_i(1'B0),\n    .sl_oport110_i(1'B0),\n    .sl_oport111_i(1'B0),\n    .sl_oport112_i(1'B0),\n    .sl_oport113_i(1'B0),\n    .sl_oport114_i(1'B0),\n    .sl_oport115_i(1'B0),\n    .sl_oport116_i(1'B0),\n    .sl_oport117_i(1'B0),\n    .sl_oport118_i(1'B0),\n    .sl_oport119_i(1'B0),\n    .sl_oport120_i(1'B0),\n    .sl_oport121_i(1'B0),\n    .sl_oport122_i(1'B0),\n    .sl_oport123_i(1'B0),\n    .sl_oport124_i(1'B0),\n    .sl_oport125_i(1'B0),\n    .sl_oport126_i(1'B0),\n    .sl_oport127_i(1'B0),\n    .sl_oport128_i(1'B0),\n    .sl_oport129_i(1'B0),\n    .sl_oport130_i(1'B0),\n    .sl_oport131_i(1'B0),\n    .sl_oport132_i(1'B0),\n    .sl_oport133_i(1'B0),\n    .sl_oport134_i(1'B0),\n    .sl_oport135_i(1'B0),\n    .sl_oport136_i(1'B0),\n    .sl_oport137_i(1'B0),\n    .sl_oport138_i(1'B0),\n    .sl_oport139_i(1'B0),\n    .sl_oport140_i(1'B0),\n    .sl_oport141_i(1'B0),\n    .sl_oport142_i(1'B0),\n    .sl_oport143_i(1'B0),\n    .sl_oport144_i(1'B0),\n    .sl_oport145_i(1'B0),\n    .sl_oport146_i(1'B0),\n    .sl_oport147_i(1'B0),\n    .sl_oport148_i(1'B0),\n    .sl_oport149_i(1'B0),\n    .sl_oport150_i(1'B0),\n    .sl_oport151_i(1'B0),\n    .sl_oport152_i(1'B0),\n    .sl_oport153_i(1'B0),\n    .sl_oport154_i(1'B0),\n    .sl_oport155_i(1'B0),\n    .sl_oport156_i(1'B0),\n    .sl_oport157_i(1'B0),\n    .sl_oport158_i(1'B0),\n    .sl_oport159_i(1'B0),\n    .sl_oport160_i(1'B0),\n    .sl_oport161_i(1'B0),\n    .sl_oport162_i(1'B0),\n    .sl_oport163_i(1'B0),\n    .sl_oport164_i(1'B0),\n    .sl_oport165_i(1'B0),\n    .sl_oport166_i(1'B0),\n    .sl_oport167_i(1'B0),\n    .sl_oport168_i(1'B0),\n    .sl_oport169_i(1'B0),\n    .sl_oport170_i(1'B0),\n    .sl_oport171_i(1'B0),\n    .sl_oport172_i(1'B0),\n    .sl_oport173_i(1'B0),\n    .sl_oport174_i(1'B0),\n    .sl_oport175_i(1'B0),\n    .sl_oport176_i(1'B0),\n    .sl_oport177_i(1'B0),\n    .sl_oport178_i(1'B0),\n    .sl_oport179_i(1'B0),\n    .sl_oport180_i(1'B0),\n    .sl_oport181_i(1'B0),\n    .sl_oport182_i(1'B0),\n    .sl_oport183_i(1'B0),\n    .sl_oport184_i(1'B0),\n    .sl_oport185_i(1'B0),\n    .sl_oport186_i(1'B0),\n    .sl_oport187_i(1'B0),\n    .sl_oport188_i(1'B0),\n    .sl_oport189_i(1'B0),\n    .sl_oport190_i(1'B0),\n    .sl_oport191_i(1'B0),\n    .sl_oport192_i(1'B0),\n    .sl_oport193_i(1'B0),\n    .sl_oport194_i(1'B0),\n    .sl_oport195_i(1'B0),\n    .sl_oport196_i(1'B0),\n    .sl_oport197_i(1'B0),\n    .sl_oport198_i(1'B0),\n    .sl_oport199_i(1'B0),\n    .sl_oport200_i(1'B0),\n    .sl_oport201_i(1'B0),\n    .sl_oport202_i(1'B0),\n    .sl_oport203_i(1'B0),\n    .sl_oport204_i(1'B0),\n    .sl_oport205_i(1'B0),\n    .sl_oport206_i(1'B0),\n    .sl_oport207_i(1'B0),\n    .sl_oport208_i(1'B0),\n    .sl_oport209_i(1'B0),\n    .sl_oport210_i(1'B0),\n    .sl_oport211_i(1'B0),\n    .sl_oport212_i(1'B0),\n    .sl_oport213_i(1'B0),\n    .sl_oport214_i(1'B0),\n    .sl_oport215_i(1'B0),\n    .sl_oport216_i(1'B0),\n    .sl_oport217_i(1'B0),\n    .sl_oport218_i(1'B0),\n    .sl_oport219_i(1'B0),\n    .sl_oport220_i(1'B0),\n    .sl_oport221_i(1'B0),\n    .sl_oport222_i(1'B0),\n    .sl_oport223_i(1'B0),\n    .sl_oport224_i(1'B0),\n    .sl_oport225_i(1'B0),\n    .sl_oport226_i(1'B0),\n    .sl_oport227_i(1'B0),\n    .sl_oport228_i(1'B0),\n    .sl_oport229_i(1'B0),\n    .sl_oport230_i(1'B0),\n    .sl_oport231_i(1'B0),\n    .sl_oport232_i(1'B0),\n    .sl_oport233_i(1'B0),\n    .sl_oport234_i(1'B0),\n    .sl_oport235_i(1'B0),\n    .sl_oport236_i(1'B0),\n    .sl_oport237_i(1'B0),\n    .sl_oport238_i(1'B0),\n    .sl_oport239_i(1'B0),\n    .sl_oport240_i(1'B0),\n    .sl_oport241_i(1'B0),\n    .sl_oport242_i(1'B0),\n    .sl_oport243_i(1'B0),\n    .sl_oport244_i(1'B0),\n    .sl_oport245_i(1'B0),\n    .sl_oport246_i(1'B0),\n    .sl_oport247_i(1'B0),\n    .sl_oport248_i(1'B0),\n    .sl_oport249_i(1'B0),\n    .sl_oport250_i(1'B0),\n    .sl_oport251_i(1'B0),\n    .sl_oport252_i(1'B0),\n    .sl_oport253_i(1'B0),\n    .sl_oport254_i(1'B0),\n    .sl_oport255_i(1'B0),\n    .update_0(),\n    .capture_0(),\n    .reset_0(),\n    .runtest_0(),\n    .tms_0(),\n    .tck_0(),\n    .tdi_0(),\n    .sel_0(),\n    .shift_0(),\n    .drck_0(),\n    .tdo_0(1'B0),\n    .update_1(),\n    .capture_1(),\n    .reset_1(),\n    .runtest_1(),\n    .tms_1(),\n    .tck_1(),\n    .tdi_1(),\n    .sel_1(),\n    .shift_1(),\n    .drck_1(),\n    .tdo_1(1'B0),\n    .update_2(),\n    .capture_2(),\n    .reset_2(),\n    .runtest_2(),\n    .tms_2(),\n    .tck_2(),\n    .tdi_2(),\n    .sel_2(),\n    .shift_2(),\n    .drck_2(),\n    .tdo_2(1'B0),\n    .update_3(),\n    .capture_3(),\n    .reset_3(),\n    .runtest_3(),\n    .tms_3(),\n    .tck_3(),\n    .tdi_3(),\n    .sel_3(),\n    .shift_3(),\n    .drck_3(),\n    .tdo_3(1'B0),\n    .update_4(),\n    .capture_4(),\n    .reset_4(),\n    .runtest_4(),\n    .tms_4(),\n    .tck_4(),\n    .tdi_4(),\n    .sel_4(),\n    .shift_4(),\n    .drck_4(),\n    .tdo_4(1'B0),\n    .update_5(),\n    .capture_5(),\n    .reset_5(),\n    .runtest_5(),\n    .tms_5(),\n    .tck_5(),\n    .tdi_5(),\n    .sel_5(),\n    .shift_5(),\n    .drck_5(),\n    .tdo_5(1'B0),\n    .update_6(),\n    .capture_6(),\n    .reset_6(),\n    .runtest_6(),\n    .tms_6(),\n    .tck_6(),\n    .tdi_6(),\n    .sel_6(),\n    .shift_6(),\n    .drck_6(),\n    .tdo_6(1'B0),\n    .update_7(),\n    .capture_7(),\n    .reset_7(),\n    .runtest_7(),\n    .tms_7(),\n    .tck_7(),\n    .tdi_7(),\n    .sel_7(),\n    .shift_7(),\n    .drck_7(),\n    .tdo_7(1'B0),\n    .update_8(),\n    .capture_8(),\n    .reset_8(),\n    .runtest_8(),\n    .tms_8(),\n    .tck_8(),\n    .tdi_8(),\n    .sel_8(),\n    .shift_8(),\n    .drck_8(),\n    .tdo_8(1'B0),\n    .update_9(),\n    .capture_9(),\n    .reset_9(),\n    .runtest_9(),\n    .tms_9(),\n    .tck_9(),\n    .tdi_9(),\n    .sel_9(),\n    .shift_9(),\n    .drck_9(),\n    .tdo_9(1'B0),\n    .update_10(),\n    .capture_10(),\n    .reset_10(),\n    .runtest_10(),\n    .tms_10(),\n    .tck_10(),\n    .tdi_10(),\n    .sel_10(),\n    .shift_10(),\n    .drck_10(),\n    .tdo_10(1'B0),\n    .update_11(),\n    .capture_11(),\n    .reset_11(),\n    .runtest_11(),\n    .tms_11(),\n    .tck_11(),\n    .tdi_11(),\n    .sel_11(),\n    .shift_11(),\n    .drck_11(),\n    .tdo_11(1'B0),\n    .update_12(),\n    .capture_12(),\n    .reset_12(),\n    .runtest_12(),\n    .tms_12(),\n    .tck_12(),\n    .tdi_12(),\n    .sel_12(),\n    .shift_12(),\n    .drck_12(),\n    .tdo_12(1'B0),\n    .update_13(),\n    .capture_13(),\n    .reset_13(),\n    .runtest_13(),\n    .tms_13(),\n    .tck_13(),\n    .tdi_13(),\n    .sel_13(),\n    .shift_13(),\n    .drck_13(),\n    .tdo_13(1'B0),\n    .update_14(),\n    .capture_14(),\n    .reset_14(),\n    .runtest_14(),\n    .tms_14(),\n    .tck_14(),\n    .tdi_14(),\n    .sel_14(),\n    .shift_14(),\n    .drck_14(),\n    .tdo_14(1'B0),\n    .update_15(),\n    .capture_15(),\n    .reset_15(),\n    .runtest_15(),\n    .tms_15(),\n    .tck_15(),\n    .tdi_15(),\n    .sel_15(),\n    .shift_15(),\n    .drck_15(),\n    .tdo_15(1'B0),\n    .bscanid_en_0(),\n    .bscanid_en_1(),\n    .bscanid_en_2(),\n    .bscanid_en_3(),\n    .bscanid_en_4(),\n    .bscanid_en_5(),\n    .bscanid_en_6(),\n    .bscanid_en_7(),\n    .bscanid_en_8(),\n    .bscanid_en_9(),\n    .bscanid_en_10(),\n    .bscanid_en_11(),\n    .bscanid_en_12(),\n    .bscanid_en_13(),\n    .bscanid_en_14(),\n    .bscanid_en_15(),\n    .bscanid_0(32'B0),\n    .bscanid_1(32'B0),\n    .bscanid_2(32'B0),\n    .bscanid_3(32'B0),\n    .bscanid_4(32'B0),\n    .bscanid_5(32'B0),\n    .bscanid_6(32'B0),\n    .bscanid_7(32'B0),\n    .bscanid_8(32'B0),\n    .bscanid_9(32'B0),\n    .bscanid_10(32'B0),\n    .bscanid_11(32'B0),\n    .bscanid_12(32'B0),\n    .bscanid_13(32'B0),\n    .bscanid_14(32'B0),\n    .bscanid_15(32'B0),\n    .update(update),\n    .capture(capture),\n    .reset(reset),\n    .runtest(runtest),\n    .tck(tck),\n    .tms(tms),\n    .tdi(tdi),\n    .sel(sel),\n    .shift(shift),\n    .drck(drck),\n    .tdo(tdo),\n    .bscanid_en(bscanid_en),\n    .bscanid(),\n    .clk(clk)\n  );\nendmodule\n", "num_lines": 870}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nYpfMx9GvesTR0nGdN/CyBECjW9iz+5g/YsUCkmLyfcl9kUguiUzzNwVg3ON/A4BrqXdSVCEc4oc9\njf3mXlpRVA==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\ncsN9JMXmg9BJlgjFcEph5gOv1+p3hZIqsmwL5z2Czw9ZfUoTeQK8FE1D4XRyaYorfGhXvVrScPSF\n14EXvUeXM4z8gXl7ggoHA3zrbps1E0fuKYuJVXPPM4YvEgQ09ApyfPThDlQ60osC/OzCsb7WAWU6\n3ppy//9UC055RD8QArg=\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nEMnukfw+EF6W7W68TalTatBqzkeWepH6qfewzeutG3Q+uulyg7ZBqD9VY6MkOWr/5PVt3VvwPTv0\ncTqcPlL+v5/amIsFL6u84fyqMWdVKV+/QEiQiBDjGctlcblh2c8OMk6DpQaTNwhyN3D23UxA8+w7\niiVSaZ0o+KPcB6mYhbU=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nENtcLOHCNxDYI9wIzYepJfjNyw7YNxm9g2EJL0jkt9SXZIAPCKrT6yX7EgSe8KWiPlvUcB5Xf6lt\nXInmua4ZJi+zLfCh9FxCEZt27Funifdm0/53JKR79McWrEE1XHWqcwq0XDL8ZPDBILgHyz+l8d+R\nv/722mxUdGqIcEefgyNZATx1aHURCY9XO4KN9s0KEkVk/SaBeMo9HAxLkOm12jBFIZobuIc7GydH\nreLCALybcg3Td+1K/U8mDaPpzLbfOSZlmeXOUfvRxYANrnuJzcmqR+Kk6bIzQ2Zld9unF35AM6nu\nl73TF1pvbs8jZU9uKDkqqOpIesBTQUBjAU18Tw==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\ng98f31KFk932yZSp44BGJiVI84eiNM0aomH1rJ10xqNbK7Ace/1VwJ1bChweO2Olr46vTnnXLi86\npChf5tfT3of2mBtxgJk7aHrA6oA1NWlJT5SGAkTYtqJqmYfIoJsedjSjgN92lkePNbASK31ecyQo\n+pkILfAlx20IHRX7vRRotxahNFAzn39Si5+eLONMqhkPrLNXaKAJi2Lq2bZ8FpKeolihf6dLsFf8\nBr8Xd1s9cpRAAHDoE9OkdICG9MeUb755cRZovBOuJYFBSSvSDmx1bk1pXFWSxDG4Z7kQ78Cr4AAq\n2pSeJ+//Owp2/n0gWP+phsgpA3zegics2/gpRw==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinx_2016_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nSJKBkZFw7Efj+9dJLkxk1jngEsHj0sd8fIn4WQTY4TcrYB3t0c6gxiQubxvLLEJg4QgsvsgSLnD6\niFfpfDF5nj5X/fP3btucB79804nSQ2iTm2UxEOwbHTwKwaXqs0OIRH3AexAv6pYTksMqC6OPQi5/\nYJwjAqN+/W4Q1Yno+OKjz9/1vURz26EHmEcun6zS9kFfW08h9R57AWuSasizu2vGSd3THmF1+Sx5\ncvngOfWiK5CjeInipR9ydR6F4Ky87RfDTJmYSJKHrUne5+DadfO+yLtBH9UFKu4OcZA3ryLTKzXR\nyWltCNxGczDM62TEU1auvaKD9/cuoEdZHiKZvg==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 2368)\n`pragma protect data_block\ni9xS00la1AKc+pJxWfZRqs0vdEkUthXwAPplov4xkH6M1Oy3c17Ein1DprC9vsLj/Kix6nguoJkj\nKCod6CkRJgG9tSxBeQA7Z/oUhYIf7mvdK+6F5Kpd25sD1cB99b+wcRo1wX4AT/ryVDDJQ9r8w10n\nG32bDB64yxCmBb6jbg8UFFqCIP/s0r3d7HiC2IJHu81lSirXOnE0PBG597aHI1PvEhtreezy3KDB\nGEG5yVba/WMSPkiqzYE1L/YU73FuELj68OhfvcAbl3JLD5hqh6Wa0zLB0kpVIVbBjhgLErreoZRI\nTtlbCyjxPD7LIsrs0H08tqRMFbV2zi7ag2k0DLKA8z7uEvXfgWRqBLmwR5n68aiF7MJxWeYIPZ2k\neP1lhUPJAdpHbSUIbHeKrA85leRnmAIx4AjMV5ehyAfy1wFi6lTbzA1qRfy+bRi2YkIDaUR9+4+C\nbO8LnO6todEvhJ6NYaP/AukCAoaG+PjsaBBa7I43ylsdaxqAzRiPHN76FWfV5cCp+YYCED3MqXeK\nP9kWVzXnR50I7lMenjuhFCrbPDdSHGnSJE1/jNOIIwfXiWSkG45VRPxFaGmqZTownaT40ltJ+Uz8\n8QBnTao9a371YgNTVzMkvh+CxUb9O60aWXRC4Fl1l86tceST+blaHaHoU8wh8onQo0ag8cJdUeex\nul4iE+iaZH5Pq9PqQL+0JyY+ScclVTjn3lWgYgLYLBs2O4noyV7o8E8iDl8kNx5oyOq6nWrk8vJ6\n0rYffch66ELbnAkKJ7+HxuSIiNan856Ev/jDaj8arA96bInqV4Hyou/zhO0pNtZ8BofBSXII3KVv\nmUr9np+UC6PeIEl4ERCkoO725dESs6agRczlN3U3zi06YtKF4NHnNQF6Q5k/yFRDATvJFntSa5cX\nCq2riSlI5fD7HZ7AptAQ94GWFNE2vRKG/+7VqwXnvCJKhKXsUbkDulcIf34AbI7r7s7Bggm8vK1Q\nTxCGOHb7/txQtTj9kih0FQUbV68Wpcq8r2aXRFMa4xR9oJ6n/uON5rpZaTG0oWQubxKZ7vVhH6Bw\ngMA3qKO7tHqkQyarIZNw6rxijluCcVTlBw1Nv+A3WAZtZmiprqmbgmELrb//6VTWtOiwa5FayqfT\nOCvhEz0X61jHQ/bJQpQ8flkTToiL9Pnx++NvFRaTb9OL51VO4VV0A/WFyCmp9NZEFaQMuAdiiyi3\n8IU9vxp7jPvoBKCmvVcSbCnbylujhBT1j7hKlIFnwbdtdEGP+P3irmAfInLukus8V4vleb8yuZwc\nRJbxZsssfmdJgOp/T+xYcVUzTDRvBEgyl+6pvy9I/Neb8phhKPl5/JPGWj+jnWsh9QI7MG+W8kQC\n8gv8+Cw3E5qqdtHfQNIXNRqYZ9XvpxEXIo3GRBvfeZ36eoscT6C2sdA5sGMkDPTzTgPfKPDXFO75\nnuVOy/jeNaDHMbJdYKnpsW1IciGj/OyrhXQLw2OVWC4613A/RCXB/+IvUAwTO8TcAPN7fJZarIgg\nhRszeUDEbVlB/uvsptOs9WqbpYNmknXaqo4nl/lbhxCokfgjf6J9aCjZ6giiRZQhjraYsTTmgOR0\nmq8Z1cRwNjiEp5TB9CA2DOS4Oq5Jbupig1xdKM8QBsSfuG2pvmT2bcICutejSjadlgRpXBumeqdl\np5FxiBFjAyE0c/JkbHoUYXFTEWpwCndGVxtz+pU4uOHQiun8HME0Qp0d+60ECE8r+TtfFAVTK1Au\n0AW+/HbKSlWGTSYdIhpEvCXHyUbRZWyjjkttSvSyVbGey2fb7DcGkOIEhJ3EOjVaCiyL8iZPSiiu\nqk2HKfl04mGQ86Mk+NRgpxNsKnGsK0zU8gQO68bN2B3y8leN9y64VvO8FKnpe8Tg955t5LKNuDyE\nPuhgiOwXLPZGcvd1+vCJp0w1ykY9crDzlCcFhieGrLtqQvRLamarNoeVpAAWIebNPsULqskg8r9i\nP1M9To2EfMtFRIvqpa62MDBjCmO7JJSaExLI1ln5FrGUKnwPVqrD9TDw7tR/2/peBK/yH4aIMu0b\npauK4r7gzQV4ttelqKpGpKcv/nY3GaVPPLfS0sw6zXO8AepcgXn1BYoy74kPoeUAp+6HASxfwlS+\nyq/FAc/mSnKEykRQJf7b93w6hUOV1djXkg/gTUQP30vmrjLdz23bQBR6kFqB/IaYqUbnLnUdQdF+\nN0L43kGHdODb49/jQIPmUtPRF+2eOamdWnhI8He+tHC74whG1noCMH+vt/J/hOAlwR70V6P6r5C2\nxii06A18tR7AFDqOcHywfQ0SG66MJ1wfcK4WfmCeXptdl4MRr4yM6cjw5vwfOs7pXsPi8UcbDnxk\nQbI/K2zU75AQAKL8CnAkfQpaxWSbssrWEYtItkDsJ/g5iKO0v7a4XaFOEjZo0BIA/BglSJP2FK/o\n2cRqlWqdUQRq1zUfpT7T324k+yv9QHUpqIax6w0r7SklsNt9HqXZUrPphKA4qa7iOgFFI6b32zLJ\n3Tj/5UJcTEQHv1UDu71qoy0ogdwd53UD+X47b6YFP/2IQ/5kbtI9p0xy1uSkSRUEJh7tvTIaen49\nOk3sdK6UHd9DkD/Mp7zmfXmbKvruKMxgZh7siZsRhFhiug8DPXBo0+9llnkzPdgCuy+fnojuTmKH\nurAWObrpux7rdscEd6OoR26GxTudav49B9TpCQ/VI0OzaaAiHo7EYHa9TkW7x4n2sIyS1QioDcqS\nHqcIz7uaK/mn9i77fElGAObB2yfUPvV9lppH+1iWz2VPlFX5FWFUsSi1+52r4jhiIZkrqfZEpYQk\nMXjoJX860HOVFwRmDviJUzr9DTkU8KI2zuElz6AmLHvnIjuhvznKEFNPvHPINrqmRAn0CyLw0zSb\nnG2NHdM+uHlzEdCb4tCXaNUpI6cvsYadbkYFhR0yIV263LL4kHeL3hrnsd34TQBZ7cWbtpi3y47b\n2KZtkvJvMeM0uYgXXMC0B3BOewXOy3GQGB6gBeQoqKGj2lOJ5H/MfDxW6j1uH2uGy8qNYjPeSzCW\nGGQuiREDn9GNj3Vj6qN3IjPwi4qOwRqoPfMf0HHs8nJm00XYEmk0tda12Gu26T4+Uh+BCySqUnAC\nR1AkQAGI8bOcy4o+pmcjyoXC1nBZY0XGTNDKRbP8hg==\n`pragma protect end_protected\n", "num_lines": 98}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:lut_buffer:2.0\n// IP Revision: 0\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_a493_lut_buffer_0 (\n  tdi_i,\n  tms_i,\n  tck_i,\n  drck_i,\n  sel_i,\n  shift_i,\n  update_i,\n  capture_i,\n  runtest_i,\n  reset_i,\n  bscanid_en_i,\n  tdo_o,\n  tdi_o,\n  tms_o,\n  tck_o,\n  drck_o,\n  sel_o,\n  shift_o,\n  update_o,\n  capture_o,\n  runtest_o,\n  reset_o,\n  bscanid_en_o,\n  tdo_i\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDI\" *)\ninput wire tdi_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TMS\" *)\ninput wire tms_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TCK\" *)\ninput wire tck_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan DRCK\" *)\ninput wire drck_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SEL\" *)\ninput wire sel_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SHIFT\" *)\ninput wire shift_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan UPDATE\" *)\ninput wire update_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan CAPTURE\" *)\ninput wire capture_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RUNTEST\" *)\ninput wire runtest_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RESET\" *)\ninput wire reset_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan BSCANID_EN\" *)\ninput wire bscanid_en_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDO\" *)\noutput wire tdo_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TDI\" *)\noutput wire tdi_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TMS\" *)\noutput wire tms_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TCK\" *)\noutput wire tck_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan DRCK\" *)\noutput wire drck_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan SEL\" *)\noutput wire sel_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan SHIFT\" *)\noutput wire shift_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan UPDATE\" *)\noutput wire update_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan CAPTURE\" *)\noutput wire capture_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan RUNTEST\" *)\noutput wire runtest_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan RESET\" *)\noutput wire reset_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan BSCANID_EN\" *)\noutput wire bscanid_en_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TDO\" *)\ninput wire tdo_i;\n\n  lut_buffer_v2_0_0_lut_buffer #(\n    .C_EN_BSCANID_VEC(0)\n  ) inst (\n    .tdi_i(tdi_i),\n    .tms_i(tms_i),\n    .tck_i(tck_i),\n    .drck_i(drck_i),\n    .sel_i(sel_i),\n    .shift_i(shift_i),\n    .update_i(update_i),\n    .capture_i(capture_i),\n    .runtest_i(runtest_i),\n    .reset_i(reset_i),\n    .bscanid_en_i(bscanid_en_i),\n    .tdo_o(tdo_o),\n    .bscanid_o(),\n    .tdi_o(tdi_o),\n    .tms_o(tms_o),\n    .tck_o(tck_o),\n    .drck_o(drck_o),\n    .sel_o(sel_o),\n    .shift_o(shift_o),\n    .update_o(update_o),\n    .capture_o(capture_o),\n    .runtest_o(runtest_o),\n    .reset_o(reset_o),\n    .bscanid_en_o(bscanid_en_o),\n    .tdo_i(tdo_i),\n    .bscanid_i(32'B0)\n  );\nendmodule\n", "num_lines": 163}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:lut_buffer:2.0\n// IP Revision: 0\n\n(* X_CORE_INFO = \"lut_buffer_v2_0_0_lut_buffer,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"bd_a493_lut_buffer_0,lut_buffer_v2_0_0_lut_buffer,{}\" *)\n(* CORE_GENERATION_INFO = \"bd_a493_lut_buffer_0,lut_buffer_v2_0_0_lut_buffer,{x_ipProduct=Vivado 2017.4.op,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lut_buffer,x_ipVersion=2.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_BSCANID_VEC=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_a493_lut_buffer_0 (\n  tdi_i,\n  tms_i,\n  tck_i,\n  drck_i,\n  sel_i,\n  shift_i,\n  update_i,\n  capture_i,\n  runtest_i,\n  reset_i,\n  bscanid_en_i,\n  tdo_o,\n  tdi_o,\n  tms_o,\n  tck_o,\n  drck_o,\n  sel_o,\n  shift_o,\n  update_o,\n  capture_o,\n  runtest_o,\n  reset_o,\n  bscanid_en_o,\n  tdo_i\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDI\" *)\ninput wire tdi_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TMS\" *)\ninput wire tms_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TCK\" *)\ninput wire tck_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan DRCK\" *)\ninput wire drck_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SEL\" *)\ninput wire sel_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SHIFT\" *)\ninput wire shift_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan UPDATE\" *)\ninput wire update_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan CAPTURE\" *)\ninput wire capture_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RUNTEST\" *)\ninput wire runtest_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RESET\" *)\ninput wire reset_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan BSCANID_EN\" *)\ninput wire bscanid_en_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDO\" *)\noutput wire tdo_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TDI\" *)\noutput wire tdi_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TMS\" *)\noutput wire tms_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TCK\" *)\noutput wire tck_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan DRCK\" *)\noutput wire drck_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan SEL\" *)\noutput wire sel_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan SHIFT\" *)\noutput wire shift_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan UPDATE\" *)\noutput wire update_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan CAPTURE\" *)\noutput wire capture_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan RUNTEST\" *)\noutput wire runtest_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan RESET\" *)\noutput wire reset_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan BSCANID_EN\" *)\noutput wire bscanid_en_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TDO\" *)\ninput wire tdo_i;\n\n  lut_buffer_v2_0_0_lut_buffer #(\n    .C_EN_BSCANID_VEC(0)\n  ) inst (\n    .tdi_i(tdi_i),\n    .tms_i(tms_i),\n    .tck_i(tck_i),\n    .drck_i(drck_i),\n    .sel_i(sel_i),\n    .shift_i(shift_i),\n    .update_i(update_i),\n    .capture_i(capture_i),\n    .runtest_i(runtest_i),\n    .reset_i(reset_i),\n    .bscanid_en_i(bscanid_en_i),\n    .tdo_o(tdo_o),\n    .bscanid_o(),\n    .tdi_o(tdi_o),\n    .tms_o(tms_o),\n    .tck_o(tck_o),\n    .drck_o(drck_o),\n    .sel_o(sel_o),\n    .shift_o(shift_o),\n    .update_o(update_o),\n    .capture_o(capture_o),\n    .runtest_o(runtest_o),\n    .reset_o(reset_o),\n    .bscanid_en_o(bscanid_en_o),\n    .tdo_i(tdo_i),\n    .bscanid_i(32'B0)\n  );\nendmodule\n", "num_lines": 164}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_a493.bd\n//Design : bd_a493\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_a493,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_a493,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}\" *) (* HW_HANDOFF = \"cl_debug_bridge.hwdef\" *) \nmodule bd_a493\n   (S_BSCAN_bscanid_en,\n    S_BSCAN_capture,\n    S_BSCAN_drck,\n    S_BSCAN_reset,\n    S_BSCAN_runtest,\n    S_BSCAN_sel,\n    S_BSCAN_shift,\n    S_BSCAN_tck,\n    S_BSCAN_tdi,\n    S_BSCAN_tdo,\n    S_BSCAN_tms,\n    S_BSCAN_update,\n    clk);\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN BSCANID_EN\" *) input S_BSCAN_bscanid_en;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN CAPTURE\" *) input S_BSCAN_capture;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN DRCK\" *) input S_BSCAN_drck;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RESET\" *) input S_BSCAN_reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RUNTEST\" *) input S_BSCAN_runtest;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SEL\" *) input S_BSCAN_sel;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SHIFT\" *) input S_BSCAN_shift;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TCK\" *) input S_BSCAN_tck;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDI\" *) input S_BSCAN_tdi;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDO\" *) output S_BSCAN_tdo;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TMS\" *) input S_BSCAN_tms;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN UPDATE\" *) input S_BSCAN_update;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, FREQ_HZ 100000000, PHASE 0.000\" *) input clk;\n\n  wire S_BSCAN_1_BSCANID_EN;\n  wire S_BSCAN_1_CAPTURE;\n  wire S_BSCAN_1_DRCK;\n  wire S_BSCAN_1_RESET;\n  wire S_BSCAN_1_RUNTEST;\n  wire S_BSCAN_1_SEL;\n  wire S_BSCAN_1_SHIFT;\n  wire S_BSCAN_1_TCK;\n  wire S_BSCAN_1_TDI;\n  wire S_BSCAN_1_TDO;\n  wire S_BSCAN_1_TMS;\n  wire S_BSCAN_1_UPDATE;\n  wire clk_1;\n  wire lut_buffer_m_bscan_BSCANID_EN;\n  wire lut_buffer_m_bscan_CAPTURE;\n  wire lut_buffer_m_bscan_DRCK;\n  wire lut_buffer_m_bscan_RESET;\n  wire lut_buffer_m_bscan_RUNTEST;\n  wire lut_buffer_m_bscan_SEL;\n  wire lut_buffer_m_bscan_SHIFT;\n  wire lut_buffer_m_bscan_TCK;\n  wire lut_buffer_m_bscan_TDI;\n  wire lut_buffer_m_bscan_TDO;\n  wire lut_buffer_m_bscan_TMS;\n  wire lut_buffer_m_bscan_UPDATE;\n\n  assign S_BSCAN_1_BSCANID_EN = S_BSCAN_bscanid_en;\n  assign S_BSCAN_1_CAPTURE = S_BSCAN_capture;\n  assign S_BSCAN_1_DRCK = S_BSCAN_drck;\n  assign S_BSCAN_1_RESET = S_BSCAN_reset;\n  assign S_BSCAN_1_RUNTEST = S_BSCAN_runtest;\n  assign S_BSCAN_1_SEL = S_BSCAN_sel;\n  assign S_BSCAN_1_SHIFT = S_BSCAN_shift;\n  assign S_BSCAN_1_TCK = S_BSCAN_tck;\n  assign S_BSCAN_1_TDI = S_BSCAN_tdi;\n  assign S_BSCAN_1_TMS = S_BSCAN_tms;\n  assign S_BSCAN_1_UPDATE = S_BSCAN_update;\n  assign S_BSCAN_tdo = S_BSCAN_1_TDO;\n  assign clk_1 = clk;\n  bd_a493_lut_buffer_0 lut_buffer\n       (.bscanid_en_i(S_BSCAN_1_BSCANID_EN),\n        .bscanid_en_o(lut_buffer_m_bscan_BSCANID_EN),\n        .capture_i(S_BSCAN_1_CAPTURE),\n        .capture_o(lut_buffer_m_bscan_CAPTURE),\n        .drck_i(S_BSCAN_1_DRCK),\n        .drck_o(lut_buffer_m_bscan_DRCK),\n        .reset_i(S_BSCAN_1_RESET),\n        .reset_o(lut_buffer_m_bscan_RESET),\n        .runtest_i(S_BSCAN_1_RUNTEST),\n        .runtest_o(lut_buffer_m_bscan_RUNTEST),\n        .sel_i(S_BSCAN_1_SEL),\n        .sel_o(lut_buffer_m_bscan_SEL),\n        .shift_i(S_BSCAN_1_SHIFT),\n        .shift_o(lut_buffer_m_bscan_SHIFT),\n        .tck_i(S_BSCAN_1_TCK),\n        .tck_o(lut_buffer_m_bscan_TCK),\n        .tdi_i(S_BSCAN_1_TDI),\n        .tdi_o(lut_buffer_m_bscan_TDI),\n        .tdo_i(lut_buffer_m_bscan_TDO),\n        .tdo_o(S_BSCAN_1_TDO),\n        .tms_i(S_BSCAN_1_TMS),\n        .tms_o(lut_buffer_m_bscan_TMS),\n        .update_i(S_BSCAN_1_UPDATE),\n        .update_o(lut_buffer_m_bscan_UPDATE));\n  bd_a493_xsdbm_0 xsdbm\n       (.bscanid_en(lut_buffer_m_bscan_BSCANID_EN),\n        .capture(lut_buffer_m_bscan_CAPTURE),\n        .clk(clk_1),\n        .drck(lut_buffer_m_bscan_DRCK),\n        .reset(lut_buffer_m_bscan_RESET),\n        .runtest(lut_buffer_m_bscan_RUNTEST),\n        .sel(lut_buffer_m_bscan_SEL),\n        .shift(lut_buffer_m_bscan_SHIFT),\n        .tck(lut_buffer_m_bscan_TCK),\n        .tdi(lut_buffer_m_bscan_TDI),\n        .tdo(lut_buffer_m_bscan_TDO),\n        .tms(lut_buffer_m_bscan_TMS),\n        .update(lut_buffer_m_bscan_UPDATE));\nendmodule\n", "num_lines": 117}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_a493.bd\n//Design : bd_a493\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_a493,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_a493,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}\" *) (* HW_HANDOFF = \"cl_debug_bridge.hwdef\" *) \nmodule bd_a493\n   (S_BSCAN_bscanid_en,\n    S_BSCAN_capture,\n    S_BSCAN_drck,\n    S_BSCAN_reset,\n    S_BSCAN_runtest,\n    S_BSCAN_sel,\n    S_BSCAN_shift,\n    S_BSCAN_tck,\n    S_BSCAN_tdi,\n    S_BSCAN_tdo,\n    S_BSCAN_tms,\n    S_BSCAN_update,\n    clk);\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN BSCANID_EN\" *) input S_BSCAN_bscanid_en;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN CAPTURE\" *) input S_BSCAN_capture;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN DRCK\" *) input S_BSCAN_drck;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RESET\" *) input S_BSCAN_reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RUNTEST\" *) input S_BSCAN_runtest;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SEL\" *) input S_BSCAN_sel;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SHIFT\" *) input S_BSCAN_shift;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TCK\" *) input S_BSCAN_tck;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDI\" *) input S_BSCAN_tdi;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDO\" *) output S_BSCAN_tdo;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TMS\" *) input S_BSCAN_tms;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN UPDATE\" *) input S_BSCAN_update;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, FREQ_HZ 100000000, PHASE 0.000\" *) input clk;\n\n  wire S_BSCAN_1_BSCANID_EN;\n  wire S_BSCAN_1_CAPTURE;\n  wire S_BSCAN_1_DRCK;\n  wire S_BSCAN_1_RESET;\n  wire S_BSCAN_1_RUNTEST;\n  wire S_BSCAN_1_SEL;\n  wire S_BSCAN_1_SHIFT;\n  wire S_BSCAN_1_TCK;\n  wire S_BSCAN_1_TDI;\n  wire S_BSCAN_1_TDO;\n  wire S_BSCAN_1_TMS;\n  wire S_BSCAN_1_UPDATE;\n  wire clk_1;\n  wire lut_buffer_m_bscan_BSCANID_EN;\n  wire lut_buffer_m_bscan_CAPTURE;\n  wire lut_buffer_m_bscan_DRCK;\n  wire lut_buffer_m_bscan_RESET;\n  wire lut_buffer_m_bscan_RUNTEST;\n  wire lut_buffer_m_bscan_SEL;\n  wire lut_buffer_m_bscan_SHIFT;\n  wire lut_buffer_m_bscan_TCK;\n  wire lut_buffer_m_bscan_TDI;\n  wire lut_buffer_m_bscan_TDO;\n  wire lut_buffer_m_bscan_TMS;\n  wire lut_buffer_m_bscan_UPDATE;\n\n  assign S_BSCAN_1_BSCANID_EN = S_BSCAN_bscanid_en;\n  assign S_BSCAN_1_CAPTURE = S_BSCAN_capture;\n  assign S_BSCAN_1_DRCK = S_BSCAN_drck;\n  assign S_BSCAN_1_RESET = S_BSCAN_reset;\n  assign S_BSCAN_1_RUNTEST = S_BSCAN_runtest;\n  assign S_BSCAN_1_SEL = S_BSCAN_sel;\n  assign S_BSCAN_1_SHIFT = S_BSCAN_shift;\n  assign S_BSCAN_1_TCK = S_BSCAN_tck;\n  assign S_BSCAN_1_TDI = S_BSCAN_tdi;\n  assign S_BSCAN_1_TMS = S_BSCAN_tms;\n  assign S_BSCAN_1_UPDATE = S_BSCAN_update;\n  assign S_BSCAN_tdo = S_BSCAN_1_TDO;\n  assign clk_1 = clk;\n  bd_a493_lut_buffer_0 lut_buffer\n       (.bscanid_en_i(S_BSCAN_1_BSCANID_EN),\n        .bscanid_en_o(lut_buffer_m_bscan_BSCANID_EN),\n        .capture_i(S_BSCAN_1_CAPTURE),\n        .capture_o(lut_buffer_m_bscan_CAPTURE),\n        .drck_i(S_BSCAN_1_DRCK),\n        .drck_o(lut_buffer_m_bscan_DRCK),\n        .reset_i(S_BSCAN_1_RESET),\n        .reset_o(lut_buffer_m_bscan_RESET),\n        .runtest_i(S_BSCAN_1_RUNTEST),\n        .runtest_o(lut_buffer_m_bscan_RUNTEST),\n        .sel_i(S_BSCAN_1_SEL),\n        .sel_o(lut_buffer_m_bscan_SEL),\n        .shift_i(S_BSCAN_1_SHIFT),\n        .shift_o(lut_buffer_m_bscan_SHIFT),\n        .tck_i(S_BSCAN_1_TCK),\n        .tck_o(lut_buffer_m_bscan_TCK),\n        .tdi_i(S_BSCAN_1_TDI),\n        .tdi_o(lut_buffer_m_bscan_TDI),\n        .tdo_i(lut_buffer_m_bscan_TDO),\n        .tdo_o(S_BSCAN_1_TDO),\n        .tms_i(S_BSCAN_1_TMS),\n        .tms_o(lut_buffer_m_bscan_TMS),\n        .update_i(S_BSCAN_1_UPDATE),\n        .update_o(lut_buffer_m_bscan_UPDATE));\n  bd_a493_xsdbm_0 xsdbm\n       (.bscanid_en(lut_buffer_m_bscan_BSCANID_EN),\n        .capture(lut_buffer_m_bscan_CAPTURE),\n        .clk(clk_1),\n        .drck(lut_buffer_m_bscan_DRCK),\n        .reset(lut_buffer_m_bscan_RESET),\n        .runtest(lut_buffer_m_bscan_RUNTEST),\n        .sel(lut_buffer_m_bscan_SEL),\n        .shift(lut_buffer_m_bscan_SHIFT),\n        .tck(lut_buffer_m_bscan_TCK),\n        .tdi(lut_buffer_m_bscan_TDI),\n        .tdo(lut_buffer_m_bscan_TDO),\n        .tms(lut_buffer_m_bscan_TMS),\n        .update(lut_buffer_m_bscan_UPDATE));\nendmodule\n", "num_lines": 117}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:debug_bridge:3.0\n// IP Revision: 1\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_debug_bridge (\n  clk,\n  S_BSCAN_bscanid_en,\n  S_BSCAN_capture,\n  S_BSCAN_drck,\n  S_BSCAN_reset,\n  S_BSCAN_runtest,\n  S_BSCAN_sel,\n  S_BSCAN_shift,\n  S_BSCAN_tck,\n  S_BSCAN_tdi,\n  S_BSCAN_tdo,\n  S_BSCAN_tms,\n  S_BSCAN_update\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.clk, FREQ_HZ 100000000, PHASE 0.000\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.clk CLK\" *)\ninput wire clk;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN BSCANID_EN\" *)\ninput wire S_BSCAN_bscanid_en;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN CAPTURE\" *)\ninput wire S_BSCAN_capture;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN DRCK\" *)\ninput wire S_BSCAN_drck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RESET\" *)\ninput wire S_BSCAN_reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RUNTEST\" *)\ninput wire S_BSCAN_runtest;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SEL\" *)\ninput wire S_BSCAN_sel;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SHIFT\" *)\ninput wire S_BSCAN_shift;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TCK\" *)\ninput wire S_BSCAN_tck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDI\" *)\ninput wire S_BSCAN_tdi;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDO\" *)\noutput wire S_BSCAN_tdo;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TMS\" *)\ninput wire S_BSCAN_tms;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN UPDATE\" *)\ninput wire S_BSCAN_update;\n\n  bd_a493 inst (\n    .clk(clk),\n    .S_BSCAN_bscanid_en(S_BSCAN_bscanid_en),\n    .S_BSCAN_capture(S_BSCAN_capture),\n    .S_BSCAN_drck(S_BSCAN_drck),\n    .S_BSCAN_reset(S_BSCAN_reset),\n    .S_BSCAN_runtest(S_BSCAN_runtest),\n    .S_BSCAN_sel(S_BSCAN_sel),\n    .S_BSCAN_shift(S_BSCAN_shift),\n    .S_BSCAN_tck(S_BSCAN_tck),\n    .S_BSCAN_tdi(S_BSCAN_tdi),\n    .S_BSCAN_tdo(S_BSCAN_tdo),\n    .S_BSCAN_tms(S_BSCAN_tms),\n    .S_BSCAN_update(S_BSCAN_update)\n  );\nendmodule\n", "num_lines": 116}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:debug_bridge:3.0\n// IP Revision: 1\n\n(* X_CORE_INFO = \"bd_a493,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"cl_debug_bridge,bd_a493,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_debug_bridge,bd_a493,{x_ipProduct=Vivado 2017.4.op,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=debug_bridge,x_ipVersion=3.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_DEBUG_MODE=1,C_NUM_BS_MASTER=0,C_BSCAN_MUX=1,C_EN_BSCANID_VEC=false,C_USE_EXT_BSCAN=true,C_USE_STARTUP_CLK=false,C_ENABLE_CLK_DIVIDER=false,C_TWO_PRIM_MODE=false,C_USER_SCAN_CHAIN=1,C_CORE_TYPE=1,C_EN_INT_SIM=1,C_DCLK_HAS_RESET=0,C_USE_BUFR=0,C_XSDB_NUM_SLAVES=0,C_CORE_MINOR_ALPHA_VER=97,C_CORE_MINOR_VER=0\\\n,C_CORE_MAJOR_VER=1,C_BUILD_REVISION=0,C_MINOR_VERSION=1,C_MAJOR_VERSION=14,C_FIFO_STYLE=SUBCORE,C_DESIGN_TYPE=0,C_MASTER_INTF_TYPE=1,C_EN_PASSTHROUGH=0,C_XVC_HW_ID=0x0001,C_XVC_SW_ID=0x0001,C_PCIE_EXT_CFG_BASE_ADDR=0x400,C_PCIE_EXT_CFG_VSEC_REV_ID=0x0,C_PCIE_EXT_CFG_VSEC_LENGTH=0x020,C_PCIE_EXT_CFG_NEXT_PTR=0x000,C_PCIE_EXT_CFG_VSEC_ID=0x0008,Component_Name=cl_debug_bridge,C_CLK_INPUT_FREQ_HZ=300000000,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ADDR_WIDTH=5,C_TCK_CLOCK_RATIO=8,C_USE_SOFTBSCAN=1,C_DEVICE_FAM\\\nILY=0,C_IR_WIDTH=0,C_CHIP_ID=0,C_IR_ID_INSTR=0,C_IR_USER1_INSTR=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_debug_bridge (\n  clk,\n  S_BSCAN_bscanid_en,\n  S_BSCAN_capture,\n  S_BSCAN_drck,\n  S_BSCAN_reset,\n  S_BSCAN_runtest,\n  S_BSCAN_sel,\n  S_BSCAN_shift,\n  S_BSCAN_tck,\n  S_BSCAN_tdi,\n  S_BSCAN_tdo,\n  S_BSCAN_tms,\n  S_BSCAN_update\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.clk, FREQ_HZ 100000000, PHASE 0.000\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.clk CLK\" *)\ninput wire clk;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN BSCANID_EN\" *)\ninput wire S_BSCAN_bscanid_en;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN CAPTURE\" *)\ninput wire S_BSCAN_capture;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN DRCK\" *)\ninput wire S_BSCAN_drck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RESET\" *)\ninput wire S_BSCAN_reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RUNTEST\" *)\ninput wire S_BSCAN_runtest;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SEL\" *)\ninput wire S_BSCAN_sel;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SHIFT\" *)\ninput wire S_BSCAN_shift;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TCK\" *)\ninput wire S_BSCAN_tck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDI\" *)\ninput wire S_BSCAN_tdi;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDO\" *)\noutput wire S_BSCAN_tdo;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TMS\" *)\ninput wire S_BSCAN_tms;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN UPDATE\" *)\ninput wire S_BSCAN_update;\n\n  bd_a493 inst (\n    .clk(clk),\n    .S_BSCAN_bscanid_en(S_BSCAN_bscanid_en),\n    .S_BSCAN_capture(S_BSCAN_capture),\n    .S_BSCAN_drck(S_BSCAN_drck),\n    .S_BSCAN_reset(S_BSCAN_reset),\n    .S_BSCAN_runtest(S_BSCAN_runtest),\n    .S_BSCAN_sel(S_BSCAN_sel),\n    .S_BSCAN_shift(S_BSCAN_shift),\n    .S_BSCAN_tck(S_BSCAN_tck),\n    .S_BSCAN_tdi(S_BSCAN_tdi),\n    .S_BSCAN_tdo(S_BSCAN_tdo),\n    .S_BSCAN_tms(S_BSCAN_tms),\n    .S_BSCAN_update(S_BSCAN_update)\n  );\nendmodule\n", "num_lines": 119}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_bf3f_wrapper.bd\n//Design : bd_bf3f_wrapper\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule bd_bf3f_wrapper\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  input Clk;\n  output IO_addr_strobe;\n  output [31:0]IO_address;\n  output [3:0]IO_byte_enable;\n  input [31:0]IO_read_data;\n  output IO_read_strobe;\n  input IO_ready;\n  output [31:0]IO_write_data;\n  output IO_write_strobe;\n  input Reset;\n  output TRACE_data_access;\n  output [0:31]TRACE_data_address;\n  output [0:3]TRACE_data_byte_enable;\n  output TRACE_data_read;\n  output TRACE_data_write;\n  output [0:31]TRACE_data_write_value;\n  output TRACE_dcache_hit;\n  output TRACE_dcache_rdy;\n  output TRACE_dcache_read;\n  output TRACE_dcache_req;\n  output TRACE_delay_slot;\n  output TRACE_ex_piperun;\n  output [0:4]TRACE_exception_kind;\n  output TRACE_exception_taken;\n  output TRACE_icache_hit;\n  output TRACE_icache_rdy;\n  output TRACE_icache_req;\n  output [0:31]TRACE_instruction;\n  output TRACE_jump_hit;\n  output TRACE_jump_taken;\n  output TRACE_mb_halted;\n  output TRACE_mem_piperun;\n  output [0:14]TRACE_msr_reg;\n  output [0:31]TRACE_new_reg_value;\n  output TRACE_of_piperun;\n  output [0:31]TRACE_pc;\n  output [0:7]TRACE_pid_reg;\n  output [0:4]TRACE_reg_addr;\n  output TRACE_reg_write;\n  output TRACE_valid_instr;\n\n  wire Clk;\n  wire IO_addr_strobe;\n  wire [31:0]IO_address;\n  wire [3:0]IO_byte_enable;\n  wire [31:0]IO_read_data;\n  wire IO_read_strobe;\n  wire IO_ready;\n  wire [31:0]IO_write_data;\n  wire IO_write_strobe;\n  wire Reset;\n  wire TRACE_data_access;\n  wire [0:31]TRACE_data_address;\n  wire [0:3]TRACE_data_byte_enable;\n  wire TRACE_data_read;\n  wire TRACE_data_write;\n  wire [0:31]TRACE_data_write_value;\n  wire TRACE_dcache_hit;\n  wire TRACE_dcache_rdy;\n  wire TRACE_dcache_read;\n  wire TRACE_dcache_req;\n  wire TRACE_delay_slot;\n  wire TRACE_ex_piperun;\n  wire [0:4]TRACE_exception_kind;\n  wire TRACE_exception_taken;\n  wire TRACE_icache_hit;\n  wire TRACE_icache_rdy;\n  wire TRACE_icache_req;\n  wire [0:31]TRACE_instruction;\n  wire TRACE_jump_hit;\n  wire TRACE_jump_taken;\n  wire TRACE_mb_halted;\n  wire TRACE_mem_piperun;\n  wire [0:14]TRACE_msr_reg;\n  wire [0:31]TRACE_new_reg_value;\n  wire TRACE_of_piperun;\n  wire [0:31]TRACE_pc;\n  wire [0:7]TRACE_pid_reg;\n  wire [0:4]TRACE_reg_addr;\n  wire TRACE_reg_write;\n  wire TRACE_valid_instr;\n\n  bd_bf3f bd_bf3f_i\n       (.Clk(Clk),\n        .IO_addr_strobe(IO_addr_strobe),\n        .IO_address(IO_address),\n        .IO_byte_enable(IO_byte_enable),\n        .IO_read_data(IO_read_data),\n        .IO_read_strobe(IO_read_strobe),\n        .IO_ready(IO_ready),\n        .IO_write_data(IO_write_data),\n        .IO_write_strobe(IO_write_strobe),\n        .Reset(Reset),\n        .TRACE_data_access(TRACE_data_access),\n        .TRACE_data_address(TRACE_data_address),\n        .TRACE_data_byte_enable(TRACE_data_byte_enable),\n        .TRACE_data_read(TRACE_data_read),\n        .TRACE_data_write(TRACE_data_write),\n        .TRACE_data_write_value(TRACE_data_write_value),\n        .TRACE_dcache_hit(TRACE_dcache_hit),\n        .TRACE_dcache_rdy(TRACE_dcache_rdy),\n        .TRACE_dcache_read(TRACE_dcache_read),\n        .TRACE_dcache_req(TRACE_dcache_req),\n        .TRACE_delay_slot(TRACE_delay_slot),\n        .TRACE_ex_piperun(TRACE_ex_piperun),\n        .TRACE_exception_kind(TRACE_exception_kind),\n        .TRACE_exception_taken(TRACE_exception_taken),\n        .TRACE_icache_hit(TRACE_icache_hit),\n        .TRACE_icache_rdy(TRACE_icache_rdy),\n        .TRACE_icache_req(TRACE_icache_req),\n        .TRACE_instruction(TRACE_instruction),\n        .TRACE_jump_hit(TRACE_jump_hit),\n        .TRACE_jump_taken(TRACE_jump_taken),\n        .TRACE_mb_halted(TRACE_mb_halted),\n        .TRACE_mem_piperun(TRACE_mem_piperun),\n        .TRACE_msr_reg(TRACE_msr_reg),\n        .TRACE_new_reg_value(TRACE_new_reg_value),\n        .TRACE_of_piperun(TRACE_of_piperun),\n        .TRACE_pc(TRACE_pc),\n        .TRACE_pid_reg(TRACE_pid_reg),\n        .TRACE_reg_addr(TRACE_reg_addr),\n        .TRACE_reg_write(TRACE_reg_write),\n        .TRACE_valid_instr(TRACE_valid_instr));\nendmodule\n", "num_lines": 174}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 1\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_bf3f_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_1 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_bf3f_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(16384),\n    .C_READ_DEPTH_A(16384),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(16384),\n    .C_READ_DEPTH_B(16384),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"16\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     19.660986 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 248}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_1.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_1) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_1_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_1_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_1_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_1\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_1\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_1_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_1_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_1_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_1_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_1\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_1\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_1_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_1_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_1_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_1_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_1_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_1_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4521}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 1\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_bf3f_second_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_1 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_bf3f_second_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(8192),\n    .C_READ_DEPTH_A(8192),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(8192),\n    .C_READ_DEPTH_B(8192),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"8\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     17.246228 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 248}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_1.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_1) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_1_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_1_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_1_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_1\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_1\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_1_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_1_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_1_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_1_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_1\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_1\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_1_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_1_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_1_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_1_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_1_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_1_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4521}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_bf3f.bd\n//Design : bd_bf3f\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_bf3f,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_bf3f,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_microblaze_mcs.hwdef\" *) \nmodule bd_bf3f\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, FREQ_HZ 100000000, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_bf3f_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_bf3f lmb_bram_I bd_bf3f second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_bf3f_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_bf3f_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_bf3f_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_bf3f_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_bf3f_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_bf3f dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_bf3f_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_bf3f_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_bf3f_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_bf3f_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_bf3f_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_bf3f.bd\n//Design : bd_bf3f\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_bf3f,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_bf3f,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_microblaze_mcs.hwdef\" *) \nmodule bd_bf3f\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, FREQ_HZ 100000000, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_bf3f_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_bf3f lmb_bram_I bd_bf3f second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_bf3f_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_bf3f_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_bf3f_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_bf3f_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_bf3f_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_bf3f dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_bf3f_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_bf3f_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_bf3f_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_bf3f_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_bf3f_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 7\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, PHASE 0.000, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_bf3f inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 225}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 7\n\n(* X_CORE_INFO = \"bd_bf3f,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"ddr4_core_microblaze_mcs,bd_bf3f,{}\" *)\n(* CORE_GENERATION_INFO = \"ddr4_core_microblaze_mcs,bd_bf3f,{x_ipProduct=Vivado 2017.4.op,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze_mcs,x_ipVersion=3.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,JTAG_CHAIN=2,MICROBLAZE_INSTANCE=microblaze_0,AVOID_PRIMITIVES=0,PATH=mcs_0,FREQ=100.0,OPTIMIZATION=1,DEBUG_ENABLED=0,TRACE=1,ECC=0,MEMSIZE=98304,USE_IO_BUS=1,USE_UART_RX=0,USE_UART_TX=0,UART_BAUDRATE=9600,UART_PROG_BAUDRATE=0,UART_DATA_BITS=8,UART_USE_PARITY=0,UART_ODD_PARITY=0,UART_RX_INTERRUPT=\\\n0,UART_TX_INTERRUPT=0,UART_ERROR_INTERRUPT=0,USE_FIT1=0,FIT1_No_CLOCKS=6216,FIT1_INTERRUPT=0,USE_FIT2=0,FIT2_No_CLOCKS=6216,FIT2_INTERRUPT=0,USE_FIT3=0,FIT3_No_CLOCKS=6216,FIT3_INTERRUPT=0,USE_FIT4=0,FIT4_No_CLOCKS=6216,FIT4_INTERRUPT=0,USE_PIT1=0,PIT1_SIZE=32,PIT1_READABLE=1,PIT1_PRESCALER=0,PIT1_INTERRUPT=0,USE_PIT2=0,PIT2_SIZE=32,PIT2_READABLE=1,PIT2_PRESCALER=0,PIT2_INTERRUPT=0,USE_PIT3=0,PIT3_SIZE=32,PIT3_READABLE=1,PIT3_PRESCALER=0,PIT3_INTERRUPT=0,USE_PIT4=0,PIT4_SIZE=32,PIT4_READABLE=1,P\\\nIT4_PRESCALER=0,PIT4_INTERRUPT=0,USE_GPO1=0,GPO1_SIZE=32,GPO1_INIT=0x00000000,USE_GPO2=0,GPO2_SIZE=32,GPO2_INIT=0x00000000,USE_GPO3=0,GPO3_SIZE=32,GPO3_INIT=0x00000000,USE_GPO4=0,GPO4_SIZE=32,GPO4_INIT=0x00000000,USE_GPI1=0,GPI1_SIZE=32,GPI1_INTERRUPT=0,USE_GPI2=0,GPI2_SIZE=32,GPI2_INTERRUPT=0,USE_GPI3=0,GPI3_SIZE=32,GPI3_INTERRUPT=0,USE_GPI4=0,GPI4_SIZE=32,GPI4_INTERRUPT=0,INTC_USE_EXT_INTR=0,INTC_INTR_SIZE=1,INTC_LEVEL_EDGE=0x0000,INTC_POSITIVE=0xFFFF,INTC_ASYNC_INTR=0xFFFF,INTC_NUM_SYNC_FF=2,\\\nComponent_Name=ddr4_core_microblaze_mcs,USE_BOARD_FLOW=false,CLK_BOARD_INTERFACE=Custom,RESET_BOARD_INTERFACE=Custom,GPIO1_BOARD_INTERFACE=Custom,GPIO2_BOARD_INTERFACE=Custom,GPIO3_BOARD_INTERFACE=Custom,GPIO4_BOARD_INTERFACE=Custom,UART_BOARD_INTERFACE=Custom}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, PHASE 0.000, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_bf3f inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 229}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_15_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      (* max_fanout = 66 *) reg s_valid_d;\n      (* max_fanout = 66 *) reg s_ready_d = 1'b0;\n      (* max_fanout = 66 *) reg s_ready_reg = 1'b0;\n      (* max_fanout = 66 *) reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_15_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS==2) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS==2) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_15_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      // System Signals\n      .ACLK(ACLK),\n      .ARESET(ARESET),\n\n      // Slave side\n      .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n      .S_VALID(S_VALID),\n      .S_READY(S_READY),\n\n      // Master side\n      .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n      .M_VALID(M_VALID),\n      .M_READY(M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK           ( ACLK ) ,\n        .ARESET         ( ARESET ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK           ( ACLK ) ,\n        .ARESET         ( ARESET ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (1) begin : common\n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    (* dont_touch=\"true\" *)  reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_handshake_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg [((C_PIPELINES>0)?(C_PIPELINES-1):0):0] ready_d = 0;\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0; \n        laguna_m_ready_d <= 1'b0; \n        ready_d <= 0;\n      end else begin\n        laguna_m_ready_d <= laguna_m_ready; \n        if (C_PIPELINES==0) begin\n          laguna_s_ready_i <= laguna_m_ready_d;\n        end else if (C_PIPELINES==1) begin\n          ready_d <= laguna_m_ready_d; \n          laguna_s_ready_i <= ready_d;\n        end else begin\n          ready_d <= {ready_d, laguna_m_ready_d}; \n          laguna_s_ready_i <= ready_d[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n        end\n      end\n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_d : payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, laguna_m_ready_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{laguna_m_ready_d}};\n            payload_valid_enable <= laguna_m_ready_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==0) begin\n                laguna_s_payload_d[i] <= laguna_s_payload[i];\n              end else if (p==C_PIPELINES+1) begin\n                laguna_m_payload_i[i] <= payload_i[C_PIPELINES*C_DATA_WIDTH + i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          if (areset_d) begin\n            laguna_s_handshake_d <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_s_handshake_d <= laguna_s_handshake;\n          end\n        end else if (p==C_PIPELINES+1) begin\n          if (areset_d) begin\n            laguna_m_handshake_i <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_m_handshake_i <= handshake_i[C_PIPELINES];\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (C_REG_CONFIG == 13) begin : tdm\n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* dont_touch=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_15_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_LATENCY = (C_PIPELINES>0) ? C_PIPELINES : 1;\n     \n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    (* dont_touch=\"true\" *)  reg laguna_m_handshake_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] ready_d = 0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_LATENCY-1];\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_ready_d <= 1'b0; \n        ready_d <= 0;\n      end else begin\n        laguna_m_ready_d <= laguna_m_ready; \n        if (C_PIPELINES>0) begin\n          ready_d <= {ready_d, laguna_m_ready_d}; \n        end\n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, laguna_m_ready_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{laguna_m_ready_d}};\n            payload_valid_enable <= laguna_m_ready_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (C_PIPELINES==0) begin\n          if (laguna_m_ready_d) begin\n            laguna_m_payload_i <= S_PAYLOAD_DATA;\n          end\n        end else begin\n          for (r=0; r<P_REPLICATION; r=r+1) begin\n            if (payload_data_enable[r]) begin\n              for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n                if (p==C_PIPELINES) begin\n                  laguna_m_payload_i[i] <= payload_i[((C_PIPELINES>0)?(C_PIPELINES-1):0)*C_DATA_WIDTH + i];\n                end else if (p==0) begin\n                  payload_data[i] <= S_PAYLOAD_DATA[i];\n                end else begin\n                  payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n                end\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (C_PIPELINES==0) begin\n          if (areset_d) begin\n            laguna_m_handshake_i <= 1'b0;\n          end else if (laguna_m_ready_d) begin\n            laguna_m_handshake_i <= S_VALID;\n          end\n        end else begin\n          if (p==C_PIPELINES) begin\n            if (areset_d) begin\n              laguna_m_handshake_i <= 1'b0;\n            end else if (payload_valid_enable) begin\n              laguna_m_handshake_i <= handshake_i[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n            end\n          end else if (p==0) begin\n            if (areset_d) begin\n              payload_valid <= 1'b0;\n            end else if (payload_valid_enable) begin\n              payload_valid <= S_VALID;\n            end\n          end else begin\n            if (areset_d) begin\n              payload_valid <= 1'b0;\n            end else if (payload_valid_enable) begin\n              payload_valid <= handshake_i[((p>0)?(p-1):0)];\n            end\n          end\n        end\n      end\n    end\n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_15_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (C_REG_CONFIG == 13) begin : tdm\n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n     \n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* dont_touch=\"true\" *)  reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg [((C_PIPELINES>0)?(C_PIPELINES-1):0):0] ready_d = 0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] push_enable_d = 0;\n    (* dont_touch=\"true\" *)  reg root_enable_d = 1'b0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    wire push_enable;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push_enable = push_enable_d[P_PIPE_LATENCY-1];\n    assign push = handshake_i[C_PIPELINES] & push_enable;      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0; \n        ready_d <= 0;\n        push_enable_d <= 0;\n        root_enable_d <= 1'b0; \n      end else begin\n        push_enable_d <= {push_enable_d, root_enable_d};\n        root_enable_d <= M_READY | ~m_valid_i;\n        if (C_PIPELINES==0) begin\n          laguna_s_ready_i <= root_enable_d;\n        end else if (C_PIPELINES==1) begin\n          ready_d <= root_enable_d; \n          laguna_s_ready_i <= ready_d;\n        end else begin\n          ready_d <= {ready_d, root_enable_d}; \n          laguna_s_ready_i <= ready_d[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n        end\n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_d : payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, root_enable_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{root_enable_d}};\n            payload_valid_enable <= root_enable_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==0) begin\n                laguna_s_payload_d[i] <= laguna_s_payload[i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          if (areset_d) begin\n            laguna_s_handshake_d <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_s_handshake_d <= laguna_s_handshake;\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n    if ((C_PIPELINES==0) && (C_SOURCE_LATENCY<=1)) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        ); \n  \n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_15_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_LATENCY = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (1) begin : common\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] ready_d = 0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] push_enable_d = 0;\n    (* dont_touch=\"true\" *)  reg root_enable_d = 1'b0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire s_ready_i;\n    wire push;\n    wire pop;\n    wire push_enable;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push_enable = (C_PIPELINES == 0) ? root_enable_d : push_enable_d[P_PIPE_LATENCY-1];\n    assign push = handshake_i[C_PIPELINES] & push_enable;      \n    assign M_VALID = m_valid_i;\n    assign s_ready_i = (C_PIPELINES == 0) ? root_enable_d : ready_d[P_PIPE_LATENCY-1];\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        ready_d <= 0;\n        push_enable_d <= 0;\n        root_enable_d <= 1'b0;\n      end else begin\n        root_enable_d <= M_READY | ~m_valid_i;\n        if (C_PIPELINES > 0) begin\n          ready_d <= {ready_d, root_enable_d}; \n          push_enable_d <= {push_enable_d, root_enable_d};\n        end\n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, root_enable_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{root_enable_d}};\n            payload_valid_enable <= root_enable_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==1) begin\n                payload_data[i] <= S_PAYLOAD_DATA[i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= S_VALID;\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n    if (C_PIPELINES<=1) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    (* fsm_encoding = \"none\" *) reg [1:0] state = K_EMPTY;  // State vector register\n    reg [1:0] next;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    \n    assign m_valid = state[0];  // Drive m_valid from state vector\n    assign m_mesg  = mesg_reg;\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid) begin\n            next = K_HAS1;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin\n      if (areset) begin\n        state <= K_EMPTY;\n      end else begin\n        state <= next;\n      end\n    end\n            \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      axi_register_slice_v2_1_15_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n\n  axi_infrastructure_v1_1_0_axi2vector #( \n    .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n    .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n    .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n    .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n    .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n    .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n    .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n    .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n    .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n    .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n    .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n    .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n    .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n    .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n    .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n    .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n  )\n  axi2vector_0 ( \n    .s_axi_awid      ( s_axi_awid      ) ,\n    .s_axi_awaddr    ( s_axi_awaddr    ) ,\n    .s_axi_awlen     ( s_axi_awlen     ) ,\n    .s_axi_awsize    ( s_axi_awsize    ) ,\n    .s_axi_awburst   ( s_axi_awburst   ) ,\n    .s_axi_awlock    ( s_axi_awlock    ) ,\n    .s_axi_awcache   ( s_axi_awcache   ) ,\n    .s_axi_awprot    ( s_axi_awprot    ) ,\n    .s_axi_awqos     ( s_axi_awqos     ) ,\n    .s_axi_awuser    ( s_axi_awuser    ) ,\n    .s_axi_awregion  ( s_axi_awregion  ) ,\n    .s_axi_wid       ( s_axi_wid       ) ,\n    .s_axi_wdata     ( s_axi_wdata     ) ,\n    .s_axi_wstrb     ( s_axi_wstrb     ) ,\n    .s_axi_wlast     ( s_axi_wlast     ) ,\n    .s_axi_wuser     ( s_axi_wuser     ) ,\n    .s_axi_bid       ( s_axi_bid       ) ,\n    .s_axi_bresp     ( s_axi_bresp     ) ,\n    .s_axi_buser     ( s_axi_buser     ) ,\n    .s_axi_arid      ( s_axi_arid      ) ,\n    .s_axi_araddr    ( s_axi_araddr    ) ,\n    .s_axi_arlen     ( s_axi_arlen     ) ,\n    .s_axi_arsize    ( s_axi_arsize    ) ,\n    .s_axi_arburst   ( s_axi_arburst   ) ,\n    .s_axi_arlock    ( s_axi_arlock    ) ,\n    .s_axi_arcache   ( s_axi_arcache   ) ,\n    .s_axi_arprot    ( s_axi_arprot    ) ,\n    .s_axi_arqos     ( s_axi_arqos     ) ,\n    .s_axi_aruser    ( s_axi_aruser    ) ,\n    .s_axi_arregion  ( s_axi_arregion  ) ,\n    .s_axi_rid       ( s_axi_rid       ) ,\n    .s_axi_rdata     ( s_axi_rdata     ) ,\n    .s_axi_rresp     ( s_axi_rresp     ) ,\n    .s_axi_rlast     ( s_axi_rlast     ) ,\n    .s_axi_ruser     ( s_axi_ruser     ) ,\n    .s_awpayload ( s_awpayload ) ,\n    .s_wpayload  ( s_wpayload  ) ,\n    .s_bpayload  ( s_bpayload  ) ,\n    .s_arpayload ( s_arpayload ) ,\n    .s_rpayload  ( s_rpayload  ) \n  );\n    \n  if (C_REG_CONFIG_AW <= 9) begin : aw\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_REG_CONFIG_AW == 15) begin : aw15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if (C_REG_CONFIG_W <= 9) begin : w\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_REG_CONFIG_W == 15) begin : w15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if (C_REG_CONFIG_B <= 9) begin : b\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if (C_REG_CONFIG_B == 15) begin : b15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if (C_REG_CONFIG_AR <= 9) begin : ar\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_REG_CONFIG_AR == 15) begin : ar15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if (C_REG_CONFIG_R <= 9) begin : r\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_REG_CONFIG_R == 15) begin : r15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\n  axi_infrastructure_v1_1_0_vector2axi #( \n    .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n    .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n    .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n    .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n    .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n    .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n    .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n    .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n    .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n    .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n    .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n    .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n    .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n    .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n    .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n    .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n  )\n  vector2axi_0 ( \n    .m_awpayload    ( m_awpayload    ) ,\n    .m_wpayload     ( m_wpayload     ) ,\n    .m_bpayload     ( m_bpayload     ) ,\n    .m_arpayload    ( m_arpayload    ) ,\n    .m_rpayload     ( m_rpayload     ) ,\n    .m_axi_awid     ( m_axi_awid     ) ,\n    .m_axi_awaddr   ( m_axi_awaddr   ) ,\n    .m_axi_awlen    ( m_axi_awlen    ) ,\n    .m_axi_awsize   ( m_axi_awsize   ) ,\n    .m_axi_awburst  ( m_axi_awburst  ) ,\n    .m_axi_awlock   ( m_axi_awlock   ) ,\n    .m_axi_awcache  ( m_axi_awcache  ) ,\n    .m_axi_awprot   ( m_axi_awprot   ) ,\n    .m_axi_awqos    ( m_axi_awqos    ) ,\n    .m_axi_awuser   ( m_axi_awuser   ) ,\n    .m_axi_awregion ( m_axi_awregion ) ,\n    .m_axi_wid      ( m_axi_wid      ) ,\n    .m_axi_wdata    ( m_axi_wdata    ) ,\n    .m_axi_wstrb    ( m_axi_wstrb    ) ,\n    .m_axi_wlast    ( m_axi_wlast    ) ,\n    .m_axi_wuser    ( m_axi_wuser    ) ,\n    .m_axi_bid      ( m_axi_bid      ) ,\n    .m_axi_bresp    ( m_axi_bresp    ) ,\n    .m_axi_buser    ( m_axi_buser    ) ,\n    .m_axi_arid     ( m_axi_arid     ) ,\n    .m_axi_araddr   ( m_axi_araddr   ) ,\n    .m_axi_arlen    ( m_axi_arlen    ) ,\n    .m_axi_arsize   ( m_axi_arsize   ) ,\n    .m_axi_arburst  ( m_axi_arburst  ) ,\n    .m_axi_arlock   ( m_axi_arlock   ) ,\n    .m_axi_arcache  ( m_axi_arcache  ) ,\n    .m_axi_arprot   ( m_axi_arprot   ) ,\n    .m_axi_arqos    ( m_axi_arqos    ) ,\n    .m_axi_aruser   ( m_axi_aruser   ) ,\n    .m_axi_arregion ( m_axi_arregion ) ,\n    .m_axi_rid      ( m_axi_rid      ) ,\n    .m_axi_rdata    ( m_axi_rdata    ) ,\n    .m_axi_rresp    ( m_axi_rresp    ) ,\n    .m_axi_rlast    ( m_axi_rlast    ) ,\n    .m_axi_ruser    ( m_axi_ruser    ) \n  );\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 3108}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule dest_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 10000000, PHASE 0.000\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(9),\n    .C_REG_CONFIG_W(9),\n    .C_REG_CONFIG_B(1),\n    .C_REG_CONFIG_AR(9),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 433}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_15_axi_register_slice,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"dest_register_slice,axi_register_slice_v2_1_15_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"dest_register_slice,axi_register_slice_v2_1_15_axi_register_slice,{x_ipProduct=Vivado 2017.4.op,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=16,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=9,C_REG_CONFIG_\\\nW=9,C_REG_CONFIG_B=1,C_REG_CONFIG_AR=9,C_REG_CONFIG_R=1,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule dest_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 10000000, PHASE 0.000\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(9),\n    .C_REG_CONFIG_W(9),\n    .C_REG_CONFIG_B(1),\n    .C_REG_CONFIG_AR(9),\n    .C_REG_CONFIG_R(1),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 435}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nYugOLIF1XBreTDYRaNSWelgjmV3GIQ3y7FKiDB9UiIB++fAUC4TXcrfthfgN8befqwACkO3Q4k0c\nvJxv/aokgQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nP86BhFBNNa0qr9Q2+Wo0KACiIyDg4VPZdSis8bLUVn6FrcCD6TyMD6qWsX7GqSzkSyajfw5KoNS5\nrAZcRWAMv14anbm7VDJCIblrxr97wW1wDK0tJz6KsyHENdmS+W0PhSl0PyC6LE8TbUq4mev1WMPa\ne8qt1TLduNZhmfYNEEg=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\ngWBenVTIP5Q+rcNXfn1zPEjuUtszskvpUVNF25Xh81JnRdMPCp/0AGJPx+mPKwQ62keEUCK7jImu\n0uCqq7uEhg8CAhGkckxz0ziMi5p3crim/FOPfZSxzcfVA0myImyw/jA25kK2gqWItxmETSoXCqJJ\nxjTH/Kdlxzn5v3BlGFnjUMmgDpw+7ZlRLWclsVDPWcyttlqzmOpUVNRybjmRjQ047dZKoaEnV7aL\nJadzAQ1SqJzBdkDtBC4ls9rDZ0efLPq2CaHSH2lKmJWzqvjdbahTe/uDqwZlM/3ri9uvioLaock3\nBYN0ATxKAINgg8QSBFGOvETVtbNj0tmio/74Jg==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUA332GmFKmVHrrGry7Cyuflehk/VbtxlBHEATtE4ZDxpaTPEmq4fqpuW3/eIdDceGsGBiaQuMN9K\nWHRjmvo00KBUbhMYtfB1gjlmZEboE2pGVM53sCnoWcRuUcFptlHy3SPD43x91G4s/5AG3W+1+WfG\ndqqfUNJVltc7+nD/QSz52JWyt2BKcwXzXUegWHFyWPlXXyRha6uiHm5A3aFVX9XSCQMUBVg9KOgQ\nr17LLKqYda/v6o1fu2DbIpPXqeviObYOGtxIlZlCKEQ0WQ16wVhC7M7JMUM8K1ajQIP6aFm+lH0T\nT0TAEilCZfV2IBv8ZeVngUGkozMdcE2q607VAg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nJkclL4oQ89VKThgpnFORp4DkQ+l+oHyNRU+cUXBcYSussbqYTJL6YmJORdubTTO26u6Gzu7Zi8eR\nCof7Krp+GgFdv/lyHLisqmpxJDZ7fQJTFSmWQ1sN09PbMajgp5uypgG17Qqsv6Efx7DaBK5bWBFL\nzYY4TfY8F27SWO7q+F4ZXrJVV+ljd3jMxOp0CO33BlH7VTdJmnHbnGwVoy7NS7ktTu5O4mtjSy5B\nim8NDWKOPmwonslxiaCWWhRcIUWJMoS3RW+hbISleB+u2f6Hv6Cq0ewXO8bpInYwlzrVk138Qwn8\nPZory2IpEEHyD3/RAkNZjAO5MGkRMmlC6knbhg==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nP0095JhTyRSuAcV3jYJyGhT1pAQ63Ikz2jcw/xarWfO4myeR2ki2IxiL2BogiBQPifhiQ+8e/taC\nZCqKABC2nUd7sP5K5FMLxqEqvaSGhMtRO2Qx+bTN2vfUmVhFmm5F0IDL69aSPE0VUYhlP+Aw6isG\nmHBHYBCtHhMlBBTHiBI=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfVKST5L4zOIHEw8rTePPdwZAh4xL2unQREo9UhjWF63YVGB1vNoHQzJFNQi2s74hnMxp4aeUGW3A\nnhI/ztVR4LEwZ7XH7wwwmLntNjOp08e4L0SwqDu4k9wj2Mq4P87tHDh2OlNiLNBP9KNGLRKuh6L7\nrvsNzCz5uZW5s7nBY60UupCfWM5iYb05yX1fiPvYksz5uEon77IwhleTgsDLGSjDpO/3MsRecpOY\n6zxdY0uNkfRy/e+huHZvIRI9Tgx9p4p5MHkKiVX5pzmTHVFHILH/8jpxbyunuxTvGsgkRSrn/BzR\nCr6wvT7hHeY/W1F7h1vfxGVI4Ek5baJkO9T+vg==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64336)\n`pragma protect data_block\nkE3zh5FB1r3vI8ZJiCJ6FWF+XzfFQVQgnzQJ/PJpjvgCXoAs4Zjsl6nmvDpPHpRl1X32r55UNGOi\nrzvS7eJCMJeieiUb8KcN1+k9krnT6S4qk6dWAtm57amEO8+SlPVtgy1tkIGJYbb8LomTrg6JKf1q\nmpnSuP6AyfZHl1hcXlpc6bd4uJId9F/xcZnJaMEQTk2Xkh0YZwzFzeJiYXNXkaANr2sFv7jst1E1\nwJT0/zDSlQMmJHtvHYgqniLGO0LTUERIJn2n3LlE+Nb1n6im8tMfUK9/omKdJrvVZAmHwm6y1KfX\nSR5hA5hizsxzuEmVhhICN34dve/ajVFv00CqzpxQcnSBCirgk/Od85aRxbLRw7wKTDQVTqkGC5vk\n8B71OWlKiZ/nHzlwZ9hkKlT5HkYDPZN426UwuQXkSdSoit7sDolGhTt4BUWi4BL1gUE1DZ/7H+Pc\nOIDFwGjTInrdA+MN85INFgXppeRHIfUeeJV6PNisW2AElJtcXF97zM77KR0g2IiTqapwRFlRAMpQ\ndmybCFy78g+H+cfr3d76Eo7sgOSPiULbuDnW5OocD16sTNjQBvfOBZ1a8fcYC0eVM/MPfFqAJMX8\nhzpp+YLA1YWJ8/mAVQhlhjc4KKcIn0RiMbw1LSTX142bdXJMBujGVnYH2QwtVCJwtuERXFtiBcHK\nU7EKh6EAIU9yCp58uJMNIub6tmkKj3b3pO5oAxbD2T1vOSfaQzg0TsmrVL6y+n+rXPnEyvrgMtw7\nDlQ8o1tq4vjKbXAMiP3VHX9luvJQB5yRoanW10HoSFcPyGhuyvBscFIWTC+BEA3hNGyk5czChKPF\n+vMFqE5wtBfiuGKEi4YBS4B6ZwpMPspnZwYf2NHSNQqfLSp1Y8r9RY/RbhF3Hc9AAXs29XP2YY2R\nDt8z15QRDaBBCVYRckMMTmGpOJ26zR/MWF3F5a9Qf5IghfFoimkitsN8O4mGDH1avgkPNpfc/5oq\nrh8goxqhDyYi9r6oAZxul3ymzQaklgK8XVa9W2wYLPQ5HVUIzH+fx7yOryc/b0XpcAYDhsiA55uW\nxPOsFmqwrzhGoEM6/sPeESOzKxGqAuWArX1dYw3B1NIRwc/SiICNy0gVTvq67BOMMfU2jEfH1zss\n907/tTkECdjUTaTA+D9QGzdlwAnxMLZS/5Jp7CaJduYxlS3SjEgCALpp8pO3FrG3dvCbzob3X6l/\nHywXPt6zQeozZUD9te+GbwL4nVBJQoDFFiKpciE0aFKU2H6IF0YZ9bQKJKYkBkYI6Lg68EPLAPfi\nHgpWSGcq0sr03CFqAvZIennPxsmwghVPPQBDInhSRM7ogh6JVSa3wYiW90Im3BjhIeZuTVwWoejY\nZtDwCn1vqNjdVK1h0k+6sZkoAJx/tKymMzQ79DNfKptG48yUmhC/F7A6bL9CZ4J0xKpJAT+0rmtd\nwEym2mskpzCcOGgRltbipx2L0w5kmRXMdyjEta4eXyFEMAzsWznDHXMv2vq5XwM0savwMfuWTyY4\nXXPdS5QFO94+jhMoG9DQ1+S+LR69rqNM/jCH6/Zgk9+GUebipjHT3BHiNgq3pjhrhoBCNVW+k8Ra\nikrBqwm62uE0Kvj7UIagh8ZVrswAyXSLIof3/bVQAJhZmB3055LH2U/4a+fEsD4mlboFaa6zet2t\nAhSATWM5T2Rxo27bt59Gb3ZUMBPTojqEfgvWWMBvawl1GlesvaxdtH3t7LjvwoXN9tdEdhdIoXW7\ncnPRYqV9hD+jSj/wDAHBKCAqn/06LxSxEo1v06AkDTali2Ibu/LpGRg+v42BQSTALzWzxmp9OZ+G\nQBOmW0FWoBr3Np7cOgqb1y5OI+hODFfRwREojfbzTDLy7ZR3RTOCEdwJ83BGogbKuZHCe4F8fVy/\nEzUHRrXI9Glt4cEZiFsJDXxf8DrBbMCe47ZO/4Vb8CQwK0Zp1ur0bGW6eZJLvm2CZDenu+smqHyM\n8cNa+X5ZWUSZdAky0ggxJvYzGj1NLWRkA3m+yU+dKGGtlf/ZyyKW8UFiemUtcK14bXza4wz86bh6\nbsEzG2TRvNc6sbZMVnkxLHYnx/xPQrWFNhKNcb16XcXCaB6WFYv+E6+GM/mR8raMgI0K1rSj7Cni\nWyKsBmpgxTKkNy540JxNPM1vmm48rjCWehZwR/BFn/eNpQZlRe261hIosBDqnVgUvGphdsrJk2tP\nuvtY6UHx4FoZy42AjlxAG9fTbwMZP/GKLN2Wn+uc6iDBnGswOQTOQl0glpbfKEJnkxuscJBlzVXK\nbIAc516dj2fAc4P8qSHMIIMMmrRtKlyoKbGUpuCdDAGCwNiB8e2ZkD3Z18aQUYjYXrudHUOsg5jn\nIoIQN89ZyPNR6r6l7HM3EmnD2I7C4nxEzYwSOaIKPYClX6pE2lH4j3BfWEH6sEd/Ff/H2P8j3/jW\nIbBz30hNDupx7kOjNavnbibhcWayZ8dsA9bmGHm0bVu6SOuXd5uKev9QnYaVITu/jLI61Wkmpcsp\nYHhaVaSFaRUStXZIcYv3VNPkuxE2az0Z9VNN0Mi73rrXGMw4pp9YL65ByzJgP3fG97U38ltLHgKS\nn5Itl199gb7ZMl0lsAh83uPfA4iGuOv2sBn7g3pyREGWaEYieHfHKq+ju38etYApkb22FnsjfVD2\ni/YIM15a0/JUEGc64KHZASi8A4NiUntFmVDG7YkPNdOXQ5BqsqprUqtMd/b17Bm0nkxc8e426Me6\nUbOlAHlZce+4uAmZvy+E4ghu6RTfGS1y2gVO/RFbNEKDLQmvXGS0//UZVhj+TNSiInw25dxsDuCV\n6utZNSIb92gOGTuKghxb07yu8yXyZy9A4biLLqaVQU0vb/PW4EP049J7YYdO9sQwrJCoeFtVEaPf\nwo2nIVX6hOpH1aFEkrg9ERiPnt1UUXlgrQTkKdlkJvC5wQSP2ZNIRveY6jHSw1gVBWkr9k0daovZ\nz0G04BIfsbm+NtmkVJ7OoDEv4XuZ4Il00Ap9vBN8bSHNO/PsMj2JNKVH3v/Xx8eisuCdeN4Hu3Xs\nzsUtx0nJQggOIjEbi1WrdnD95V5yipfY1V/ZC5V7ii5zHDUDkP+p14NMbuE9sjfsL51Rfoty0wsl\n+MoLxpOr4NcXnX7QOWmy4aGdL8C3ZikuPP00WhtKRG4p6H6MkrAttXHz6L5wCnUV4O2kGfhkhYjf\n3yQJVii52aRvT7Lv6S/BAOJFByUGl4wpHoyfLS8dLrarEOyI1mnoeOsjefSUTMceLOKuPWkMk0I+\nLR/T838qusGpX/26srrf80SWxKr7ch0YEK9xGGHAO7cgvPQTlncT37QvLwfutO2xOZT+81H22NiZ\n13z31W0LurQciFfxyNz3bOQeKWnQHIqtFv3JGGJnux7/cOP614w/LW/aL7/YOzC8F0xM3YhaMeUW\n9UA+GBxyn9FtuQ0/g8hs0RhuccMBjsnxQzSBS603FlXaUQV2FfsfMLBL7TasPZ4rIHuUWTEu9mYL\nfWz2rZbpwwfRq35JbtQKwphJScZVbTaLWyH2Isjcm3GRFrOK9OpEZwYx/HTc9n/EtRmmZFwdUe4J\nlDnueKc/fDmoU4G3+Zw6rm3p3XTOo9DXUArS/uSnCylnmGrAaBLaKnFsQKd8kCmJX12Uj/xdyOF9\nOpIg19vrcrSE0ejJQ5dUcLrb3i0Rk8eLyGew8jmMMtFOBRmqVwscepGRMPG03RMp4W3rEJn8UXb1\neP5XFWhrxazaFOY5ljiIWHk9hYQOnH/Vt8DG01HUbQNcvQH1xHNwUIooc0fbM+PgxMn2hQ0pM6+c\n0wPfDIKABiNmKLhcHnljST+ofM0yPaynaEkePqVxWiKlmFSgAsBtBcerrFImky4wOHdJwOLvldx3\n4dVj6HduJgYtLUQGVl0tI3IbmvX6s0MKeONdhJKp69hWLHhEiYl/t1cPpLJB+SUFp/r1x1s+MzD+\ncKZW7hNtDThOdBJjoeAKmavGBoh4VHBtQqDP0lL+EwpSg25V6X9XW+dFUEpwaZ0CuVXWHBtwGuce\nMaku0HU9yyOJSHRk7R5AzoBM0QCbfNIwoEqrpTgUW78VzRjekms34MQvc6/VWtqoA6IIgPs8ybLJ\n1pXEw/utkcwR/tMBVJvyKzEp9b6Dc0sotuhEJRY553G31bb6xa7Y7PG38YByPiqfJPK4AuPhcaO4\nN8WILCcgXuWL93xjqu0/Ew6z+GNqQm3Jz4ntiHysc/AluO6K7vtwO4UcS8ccMt5z4bpA4T5arE4/\nb1eHDWK6JT2gX5/4lOlR7pJLy5qwKyffyaH/Nqz7AsCVsPZi3Qwvygy7NndJ5ubyVcHxyItssjGq\nDNBwkJOOVIQtsmfxXko9LsA2I6zOgj51rqOlqXg2Gk7DDJjUk66K8JUFHjHbyUHJoAgAJXbcvFfs\njDDBZ6zps82PHgzQSOWlueInlKXLUvswdqg8Szm9Rmfe07P0jivX7y1UdWGu42d2G9+SbnpVwkAY\nd1j6kvNq/oN/n3VLX3UuBoSfGik63mKL3qmADCS+UFhJpi4xHFbwZh7pqoTDSA81OoplAD6RtIk2\nxTHfTfakM+NDXKgW5LVuaFtBz+6XsG5LuuVK324YlMwuHsdtjt6EchzSz/yYaMPHCFdNxyRgcbqD\nSIm/1x9m9ypB7i8tHeuJrv5TiGMrS9fK/EjFDH9s0XHcvfmBsVMUNdJPggy2rEwjwRnqEXo66at/\nAfc7We4AA8PDP1d76rGrBczWskspbNfVGtzLYmsuK1aMAzAGE2VnjMJ/OJqy2qkF5qntyuXtWXp1\nXYYHmfMdE0HqigV/1OZ1p6fodgR3cMw7dqDD4xSvY3zej5zcUNWAw6yrxJEPGUhaUjPtNS7+r2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fRoNqOEwbphWrnFxpR1uQtlznt7NunmA/HAq9QD0jc3VCyUGLK1m9jzfR+MiOxGkvi40fGIh\no5q6cp6WZYQE5sG2u1HePNz260XW98o1SKmGAnVADmN9oRH+kJs27wjueapaewwDVg8pnq6kJUOh\njQd0RkYcTMItDGvp+sFqeIIdADsTHRvr1h+M+pYqq9sLbwUoz1Alak51hZNlSXhSEVXzQLkppmeO\ntB13Z6wglCy2BICINwlSr/7HP1cYop92mfeTXL3QGuFjsDOYJeT9Igcq+fS6YIfWCA08MY5r7yVk\nVPB84f/igRg5ddrxoxTIiw6w7GWDOhG+zTxF1zyp5jJA3yKcpqPzSQpf9MKcNt+PzeKm+wneK6Jo\nhpoN/97lq7oMjwcqj4fYDI3pT7J8WHKkZCIdUVNrv0PtjsuMpkuTQbOr8hbWLJNy8UKFlgHOcfrj\nOvGAARiIQRbgB0ehYmzYwrLOYCEEGz6BajWpYh+QjcQz68HI9uD0KJTeFrxECsQhCkd+nhXmR6Fd\nTuqTwMlfvUxKMpfl+zweX6F5NmHmeyPDY7Z3diHFdJVtYNhc+jcelDo1qmERGZj0HjhlAXvpn27V\nveZu3AVSpka5ElIwtvHc/TpRzjvbeQHF5yFv9E3VhZftw6+ajD4mjDYjGCqQeNasu/oomGN+bD06\nLx4hi4Wsc5ABDp9+84vB9wTN4vdXWfDxjG6e8iiMfWuezpQtLWJtxG2XnhaF3oXBpRIS2VVSE3h9\nz+2gpVoEZT3vzJjOS8nL57iPKloZn6rbf5gWqxxUAtYbGct7VUgqevGHgWDGl0dAqT8VpJaQ21q6\nFkr/uOy+vbpdI3AICEPSgGKQQMnk1kAfWxfgJ/kaxhZc4f5XlC0ZGSh+C2CWzhNE/JAksw0YQmsi\nne+rOYuBn6qvg4VY/SXyC6jNTUu4fEhiqCBJKvOpstSpQS2jYVyQK6GIEoOtvRL+AeqOwN4ylvak\nQVkg+2A6cwY7T1x3wkcNeZMXbEpORaOJMy9wXl09aJXky2uN9qgpXHXgPTZNWf+saMNRN+uBGVzs\nZjhjfEYYTVSnY0pqS+gpfbtlNOxXo7TL8OvbkRAThNpVfqwQtupoPNk2HHNbdmWP1tZGcqPsQf6c\nCPJwuj8fcPCQUh1HIZMnT9DYnr+Z1+9YVL/Rz7jLHyA2rFlsPXsEC9hUanPqMe7CAAEbjTq0PKon\n6vcDhC4OeDhfHkwfTiOS9fxMjBLTcaoTqPWTZt8ChH4gnVvPWfUBK7kvIhw+dKvaxIvX9bk/BH/Y\nB6uSJzU7imXZJLx07cEcU/6LrWAx6BrPF2/b6Su1t6eCb+t1Q3QZIS/1RXup1A8KEnaMO28WsZcw\nZQ5vCfX86ljiIl+HfGiLBpKoa7+SdP/+q0BolGpFDPCce56LZLDSOjBraFCS81FH07TgMpEW/Koe\n73WJ43JWWkZBQNZzN+JlfWtwo4qAocwsQJX0w6MOAIE+RO9Iwh1IPv1zbtcWHBpWy1yK1K+qVbiT\nkI8txebAMYWE1fJJdK/cP/tTZXiQLhiPzBsl9ezZjJsjAPcq3dbWErzH6ZEEnAKTv6PShy3Znw3q\nOT6++Nsz6N/njj6GqwN1E2zfnMNA9tFHXPkjpOfSbyTnzGEEZwPile3fiO38kzzHEjoAkb37KavT\no8WtZsohsnfTezPzzWxB9cFMtrTKv+u3cIIlr3mM8PZGdN2ZSq9ahQfTqRYp5KGtKnkkBIfsbqqM\n6M/SBVm5RMtrKRYp3/ey+lutDPtoUKLWJMnsv76her8S4uek1nzv4wTizdqJoCHy04vb5HAcgpVC\nfcWHgEVDqREje1ZKN9cggmiVpXRsjmWDBU/wAg8c14gohHPFlXNZgAA+ytO9js8szFDnt/0cCj7Z\nkDd0C21SAR1LHBI9KUf497LL8Tu6L6XEd7Tm3XEXeAS5OgHmGdAHyGPiqI9u8ClEt6BkfXamciI6\nlfeQj+z1nCxMPEJCjjzMwvV+3Ah7f/pMVMzaycr537MfD4P9+Ch+Y0vIsYpwt4zU/30BNXnQqfs7\n67i6Wfe/ptu3NRiQFhoPNGZytUbv/evSNDXxFaqwfruUEUqn0eUopvcwacq1XD9XaRIAXBGNpSoS\nKKesrN7Q6LZ+PG/cPTdT84w/+X0t954GdIewb65IP9dwf17eYtg2FQZyM5t0f3iNHe0pojKIaM1a\nmcTIJ8FIFYHoORq8DSEu6tyA3X53jjGyQRjVmLNIZdZSbRVoyoBsiZ36Zh4U4aW+U1leOK18co4C\nxLB2Om7MWuPJT3VKJMuG8psZ0iW9z0Zxrl1RyfZ9Lk3hYM0VRdpLKgxqEDiEeCVqfhlGlFXUj3wu\nacVLRH6dhSEBumjFuWq/lHbTsYfS2PGWkPdKedT/skbFeOsHLU4V1O84M8q9+qmppce19MSMwXeO\nQ2jn8v1qDqQoaq9r7Jvksqp/+A8wClhvUJmaqnTcDX+MLOJSbHG2ZNR/3PvUYpDVUrL6FwJJEASQ\nPfeLTPm7SGxsfS/ZVEf5pC70NwkE/6UEcyIx7xiVjxXhDxpA1pBvp9PRueOVwllHhE6dRkC/iGjc\nY8YKShjZxisO3URdOWXpt8F8PTMjnWoGzvbX4aIve+X5KKntuaYeQxKXCf8OJaSDgRc27KSBsG77\nFYG6/6BcH6AAXrtXc/OMZ5Hu9pwGsV20Zxo2xAGLOFRpmnHdImjGCwHmcTrhQpQH8Br0AYr8Dchr\nzb/JJoGRA3WukUlj+NanwbgVkpDoHAJD1a4ftoDvHJVleoDf867gupHQThJhVF6z8LcDtafpRVrE\nSHNxS9sSGI31+aTuQ/0YqhEiBI0k38xXFesQY1mW/zireb4cohUmw/0Nx4uTsUCRUE3WLfpwBeb4\nMp8qasvOM4Uf9kQqF+GnmseyoR8jF+xEaBjyzrsJ7WpU6EQqH7Cs2y+0nkw7vULcWZ7PtxCkTi+y\nl+KY1Ss3um8ryMQYGvKj7L2/zAzwrarkjBW4JAtWsM1SrwqZe6veUIqe3Z4G6jiNsQ4NTDb8oypf\nuYa8F3nzw3hTgsLTGVQU9pMPE08BjCvQKFqc57jBAj6RXHMnE3TWWc73XS/zYTiQ/OmvpnxjZ8lu\nvX+/r/dA5KdxINswaLmFPw3KzzuWJBz/nVwLRbAGp9IHQYa6bgjjJRm5ZmLKGmzzyuRrQXUPKOTn\ncopnuL/JvlWnSdn90TMc2Tzzm7TXaIcgX9EDepTRW4sN2XWdc4AmncQYlE3Pc3mjMKKgB95f5TEm\nSgoHGZwRKlzoBLvmO6GOz1aatdeR50BMPUt7pSJwIgfBdLnvzstov1W42zn7AgW7Su/pfCewVOQc\ntZ3KuOMYDHtAQmPMuM620hdwLoXkyIatvRSwpr0SFvGi6O8B6kQ+5QxGad7VgcpGZArl8TiH6QY8\nUrI26KJkzhP9OikTZ6om4ZAs0bloMAPotwByB7KXegEUUn/G7uE2JTlScgVp8fNt08IHyAO9ubEL\ndk6s6Dfr0H5HdXOKdMAGD3C2jl0fudKu4zYcx0s+KraQSQgLXI1G2qoLzPeW4fGtztn4k6iTlSBg\nRGAbX+gnK/iuGfb+++nrxTBI8qFUX6YIlcOAkg//OSKGJJjat28UHn7BITZnedR7Lf2K2lu2q4yM\nUFzK+WcQU2KYHp8iy1VQ7x84oZsD1hpSPIvo8xCeiXIPtrxEHjRh9OZp7jAHNkZxhB53ii81SHB/\njEzrBHa4MLE/6WMisOhbmjPDUtQLtgnO86q7gzdmJX0C1jvl0VzQx+0ISJcZc1limXckLBS3F+rI\nMi8MGBfMyw+BygdEr2f6yRlYvJdRZJhXOXmHT77UlUuCfmArP6UIswPKplZN7Q+XLflYU+I7OUPp\n3qMXyzrC5ko38DucoiwqvsXMSMVx3U4vLK9VKA3sPt/QP1E0S7tFJB6lDoYQbdTI/vUgNy3iAmmw\nLl5BmdtFBDWdwEMFan9pvoDEbzNfFkIUBGuzvnjKtAFBwA67RYWKtqglvto8q74Btd/PMxWugAs2\nRDrpHJWYNh1j5vrsdRj6sRpJRMQ9FpQRBFbz8fol8FWWJFG0S8M+zbG317tUs/p0GjHB+hTwItqR\nv15KlK1LZfgIy6o7gd1a/8MIRTXjAVUuVviJ68d44vkkJr3mh1OphI4SBhUhzOaf+44CoHK2dorL\n9MyTI6q2dacNJIgHdhaJF+ebOKOMQ0olKCeLvE1KmN4SbPr9dHBv/d7cupOKbz1XYMcK66m5e/El\nRWsYMbQf2uawzWEs8cZBm585waVMQtfAQNoE7/Rs2/2SY+vnUPguioY+EDwZsTxfJWkI8zHk2a9+\nrJrYuXiNAW4sd3i5EDq/+2Ak2GPpRmfpxb7u6NIBKlwXugW8ktrqwlNqYCtg5vVaseU+FGNiVsvF\nFIuNWu1U7GpZ8HtnZu6aFs7IBPIoYMl7vu3aDQpZG9I7sSkjhPjg7s+ijQIJ3BGlmyuljXClWhZL\nJIDVQLnzS1pM0pvibM+4youBOCPFCx3sFuvQJZk3DpKOy2HX8XmKOtbKgZHL2FBjFFosaGOqcL05\nIgcxAvuqHB/0PhosWC4fcQy9X0ohWgMLrtpWE8mEqH+l/idgHAn3azKZjNDZTlrOZEPh5Y71cZak\npKgDUjLW4WthFcIERr+HL9L9PI43LQ0EKDsQTa6UW3qJFAXgUMTYgZtO2S8RQB23wPZI6bncN69z\ncEU5z6OZdFP2CgLvdInA1tFbRhPanE7dmxgxqPwFREzFyPLMwVsw9YgzsxSxbhJODZvVY1Bp6C4e\nf8VmwXIAZt+OfsTInDC+dttMHHHCvtu8TBUbI+ZLgsD0HzsESIpV/BFvQsRAJyfHJ1Qu2kByntgu\nauKads6lHHGN1Tz23/hFq7PVfLwm2Rv+/yx5DUv8Uj7PLsaHqrCdZkVzr0ECfIwPFt7nW50xCqQK\nxMu8QoV4cuZFAJzIhqj5t05ByOQPFRcxOQEfZrShvvNR9GdpYtghDBF0fU7BDHiagP5xDQ+UrHtz\nka7nRo1FHnm5QoYRJoEBABCLmeYI2KoWtLqx/CHi30vFLoru7CkCPX2Ll5A5mIHnjWmu/VKJrgNa\ntThK/it4atG3Inp2n1vlkQJQNib7fEUdfuFjiiCQRuNtmJX+MqELiPQnVEY9VWHNKjBPREYUQKnP\nJkfsG+QfkgAOqxHLM6oCfy2FFrS9aHOTMK/+PdNJLxa769Vi1zeXV0kwzsjTsJp6LwEAdQ4xKPck\n5bRahBrDgSJfUTcQYR+fbWtE8OdbPM/FWuaIc9SEfNMEebsH/lUKGSB86OWHZNz4CMk5ebH3R5JV\n6DdoBjfP4Atab/RbwcQqnZG0UdOPbBy2c7wTzqK1i+/C1l3+nDVheGhizstvKZZdm6XehGdOgf90\nOPsGrNckYz2jn61FOH0PY9mFh1FLr+59tTVOFZ8+6G/JJcGGo8HJhb6b5sCjXHSsT78/4ldD51uE\nJDiwF+PKeYLd+bhW7XjkVvG7+LYAG5h34M4tD8XHnDUKzWkpzBJ97ZFr8lV/euLpwJ/XlVImBXwp\nwZCzDdGwiTrZC+ogqcsGqoZxLQ0lv7VhpBL8skkTAYlBc2XQufABCHG+gWEuy3TJvqodDuGo0iZz\nQzftJFbueGn7t2+s/eYkOYS6arOhlDNJX2nYR5xtrB1FbV8m+jaHEiJbQc7h1G4HB07HukZZp/9P\nLFvsRYJ6uqex6hCbbqMMHQGrId6QGSH6/q5SVMSgN2/gJFrr5scKkIFUDU79QyiUDCNwsC5hwA/Q\n52vnU3pPU6vXy2f5Q7ZwUWdsJFEI6O0jxqL+Ga7+MIwsqnVb4GlFZdjTH+jRLEyw039RgVDhgKFx\nliWSLpSVpJs1r/645DGyzIbsFE6cPjg38+CcoAWYla+Gp7OtVF5Aqtp7iC2fGffTn7TvJOPCsVjY\n5MHx5QGSiT/mOGO5OVGVbXQzgTu/3GVWMajEmAq7T3+Ddw+yw94k9rT6IDk1t3lnruZSEJTPTyok\nw+bsJPG7RO6DcD66Igd1WzLO5JiNwENjJVrvbbBMYTJCgVPc3hJvvFQvfkLiuZsa03mylgBXKHAX\ng1TT+hvmb6ZTIuNi6x63/487ZXtXCLFNhUfNlssg6Z7KCyDb+mOiA/8aaC12vb51w7SWXNrmZCWd\n7wJVMUngtcinyUXoTuPe67Tbwu7Y3zQ3ZBvKMzu/YFyR0SsSeD+/yJ1siLMoqudSse4aThJOdPbm\n/YEW/tF7aovwdtXP+40gIRqfPjqUfFDJzhIh5XTJx+5XI6b1ZNJdT1+zC9ZCv0wpUCNzcYDWP2v2\n+73X+DI2B9Hk+GQUz/uV+HUBxDiALLNqS2pBnu03BRN2K3Ae6udAdykdB3XrMGU3apddVfl2Qzxp\nIMqedE5qxJzRw+S8ghl7CQ/HLPmeR4VLqSCR+4vWCWIw/nWGOStxbAxslLYMvqSQqcOh9SyzCdy4\ns+S2RDRsuoiRadrTnFE9DK9AV7YVbx1TL/4UsryqKTyD6TZgb3LhhYOUcpIpv4eGF6c886m7YxCy\n2UDtdlk5mzEa450taWmN0KN6rx09qVH7bTyCrbrVUDBIPLqFlGt6zsHsfsvCJAI3c9lNyy/K4Csx\nnVy11QZ2mZmv5FNhUpC9/LR77nEsEfKmmY+ZvmK6ZHudJHG1/VfBI8FoBMT/fDIUDwW+BhOel/Mr\nViAUiihouIkWJnuBu1qd0eyhHAEwYLpl67lU9OZtC+Hw4nRKD7xL4yeaFxYMdBRfHT536DpZkC91\nDyLn1w51UXVeDMGmEk5w/suYHhiKKlsSF4c+HVkT4yWcG6HjE+nqeKji/CAw5c+5piMrQDdaQcJW\n3nb0iIj0gXRBN+Eotil3B7bIpwe2t+faDTQec05jrigHMr3ZgWGPMkTWRs4Qir553sMKABMSYkcR\nnG1bX1HCd5Umeid7Ko9w+QAO4nPsP5d0GRtDcIyTVJxEMoOOJPe6s5d3iX9a55AGR4JeQOBinV5c\nvQTaqc7NHTeR4spVOyNLX0Vt4r4xYeQPAv/7STKb3KraVueUbYH++IptBnYURSH+JYRUgLc3wOAY\nvaIiWiWgsMJN4S9Tj57MZ21MxkcOD4n+daasVl9bXICg5bV/qCKv8GLgLa75Lmkb/q5ZMWqIh9oE\nBXG7qwnhfQdr1GBfNX5e2CHlpmAsJSuPYxfplnTe9x7rmzk1saELs+J5Zod3BW8s9PqEOytiKyFp\nNgIyYxnpDHg3KfkpBCzAqsNwFrRhkG0cNj6GW0rXcjnK5XVsm5EJsIpUIuwUUCM9FS4M4tQvHqzr\n1S0Rwfa/ZmOL+3kwiLwUF5yWFKNs9N2uwmJT5wYI/8PK/4X7jfYBxLNFiM1d7/Ot/0CD2Ygqno20\nGjj8idQj+8zcvopFkqmlICXcCSsY1CN8ytSbrd2KnMUs733/3JrtKjQJchP9IvaMZn4C8GZRjQ6B\n2FQEh8t7rEVQECSOxQ4L5fKxi4VjvlFFV5om0bkmX9dxai9YM/IwxOrmiEVbScRlOGYie5dHSd5V\nk90VtMGSxisAx3kJM2aVn69wCxymu0VbpXmPT+80tJOSJSASfShtKF9vvaTCkQlfQzw6bL7yoPjh\nwEpRBVB8nS+srJxgzTpzxf6kWSrfKwaXXevwejax6otuoFF3YEUOCVQgG2aUWnXPnlQBNC9MPtAr\nmChzvfkMA49tIz4Ra/kpvwGya9myjGuIQ+DpHiMvJrcsopWNYHjXYldeCzHaIWvnSOHGMM7nBGD6\nboOM+PIpyOs0dw3ymADCy1T+tsTasU62qNcuquHRip5asAz3bozJHUulZhGOlVgRZUNdbA/meTnk\n/sjtLjzMLOoPyFtPJUmnUvTECUkmGukcIMhdEnWfA+OgOzrM61GTUK5bwGME8XNRsprWjCchp57f\nxii8cEiyhO9Nm1pmdrMnxiPCjIW2WSFsnp1BUNnQEWDbigo95ithoSdZejaydDJCNHQMVMB7BgbH\nJVUUva0f/ZGTwU3kz+FTzsT6PT+E2GNMZm6rzSz1Q3yNoH4OXUbJwQ/vRFtTpicFPDJoLzVZKQ8T\npYc5LFd897P0DLzZ8yT219GrhNpk8PgFDRC+bylWmXrFl+BbEfkaO9VEr+LIfaNoM8p0/YLHLo0l\nMrvk/FTzdn5XhFvxyS+Sky7a8fU9qLu5xKvwZGoA2MbCvP/9924WG5xmAmsvN7gJQ5JylMq+lFvT\n9vBEEkmXTi/zMkw0f9CycHzh0eBomR3kzWnpWRJ8aBj76yXKuWdrSZi8qbVdo8wh8eb5xoIV0ir3\nEqgdL7Zjn1IcBmqhcr3AfwkhQEaXeBA6hqImHgPIpyxviqMTA0xjkebO9YGuzZAUIa6uCCzR8XPj\nbYJjNkm+wZNwzr79+h2XV6wDs4JS8VDdZcAVCwvmjHY8WHHb0jZTF+cMbLcUDsGNXONUc06UzHa4\njGjOviVfcTwRaVwQs82CNgjt5OHwna+Fj+b2mGBEyENynvXGlAo4ECvuBzpI8LU+ABqJINwvANwS\n44b0GVEJNVekwlMSByybrdYq2Lca3a9BtZmGtoxI5vIDG8U8CGIe/HaNFpFIvuyGDgYAGr2eb2tc\nhbOnJu4LASxc2GdEl6I0f/Z0R7seDGa895BuyGGcT/HYktcCq70sTyk8r6H0klX8wc2w+1UT9sPp\n13PTlh3zLdvGFzKPfIx0Bovn0nIoViJ/W+tgIbtcCnPhaL4gh3QePzoLOGoIWzrZKrfXdQUkepGM\nnGqctZ3+0XpR/XS7seqRDlstOjCXkPam6oFji3lfLKqM8ABKgItNsWesmVaCeblTHDPu+zmR3Swj\n3XSa7hlf1r2EC1jqZ+oubGX9WZjOz1p0gsINsM9ZgUPOKlzt+VBwtUQGbtj29NqAdJ2m+hFTMnXL\nwnUTOLl4CkzQ/3PrqSxqEMLrVcMbDav1VqHyySeQ9SUXcPePCnXTp88Ns0q+RqrpL9STvlzfv43d\nQWoOfT+y5jzqBr99d34ltSn1jq5Mk5kfg331aVBVDGP8CPubrq/MjnUyQ2o2sw0VX2JfGMN2BjHw\nfFEQGRoV/qgnxP+Yg/hdQHYj+r8qrXledHrHiSIHvAPs4IQgUCb7GIaSaT8McI1pg/MxpBTzTrLO\nHedJ4drTUgQ0yZ/iYK1+QT4h4+42fAkQ1PTj0z825aLEk1E6e1O4mTyuokRi5lFL0i4Xo2nnJmcg\nY2HAeYmkS26cU2mggoFsRs/ZxkSkF1qMN7lvHplO+1XTHO0DVfLkBuhEnnqTZn8rhmPL7cnoZaUH\nZ+WcnLY2VJJpEsl14KAieVLy0ABlPd+RP5UZna1k+42P6i95rcEg3jt0xbOAbrd3GZ10GT4chHwX\nZCLWJjslyLcbPGL1XdWjgDMZ3dtfG0z3hucdHb6/ueD5YQwPMdQIir9TjhHok4WPalVXcz9OwrDv\nkkUDrWxC6S8tuOFRsk6jqShA+Nv1loaSF+IqNB9sfeSGW8EsyVZIuI1fnErGqbXf2i3DInx/KFau\nWTBKYaTk6krZM9fG1+OzTGuQ4ubpSMe6o30MtzdVl/db9M7hv27LYlU0miFi0OmEUVGOOZDK+gSW\nYVlr43tdFyGvXHSuVyUe8+IhswC9IOCUS+h418D19ZNCQT6af/VQDeVmfOTnnZpP6DOc5p+hPFvn\nn/ISPeLm5qeknJULbDWxnHSxTeKqsw6FsTlJo72ZuEd1zLdA0lJqNxSH7YKQEawd8S0tE50OyfKP\nJjTDQ09tW/9msny5f6YFRscHzIbThNRsbQX1saPn1Gu4rhrY5lijfWRBI18U06gYijFIC5rZDP01\nVBYwmOnQa+ODOGfcUiQmM5pZVc0/4xmoHedHdwn4afREXvUzDZpKM2ZwPhNdB/Bf1RFqcRr9sgEf\nIub20BMNkJYzK5VVtGRXanivzfdoCbqJo4V8P/5J/jpsiDuZrb6BRaaYsv6z0mpEcr4RDQLHVkHN\nuy/UCVRX4N5yYskMUYbh+yf9ItFGH9xiMcWEvuCIcyyyXxQdjN8M72SBJ7rSGqi/iT7lD6zS9rCt\nQ25SxFqFjyMFb3/PCyopcf+doCoAKth86socVbKc8wQxwpfsjnsmDg6VfStQW3j6HbTJRR6cBKWg\no4hq5QyH4OzFyrWlze3EVjvAIRNo80YsifUXn/YmjqXkqejTAMs5rvnQMXvCCx5iTbO8GIqe1ZIO\n6g9nf6cdH8rgKjU2irIjf8wuR6WdAKliC5HyFO8HHKQ+o6jDL3Gp3V28RPoZe/ggfrNdJXuljh2p\nxgmoX0sLC4F1b8ary0X9O5Uk4Rm6NbJpHEMhDyFLk1/DSblBMxjOyWf69ua/+JJBU1aCUg73Ef5C\nKAF+0i0bW7wQ+1F6T3OIrZADAm3G0/7kCMyEk/pFhEeiyRgxWwHJyu8Lq3uncIQ6F+BT7fiZp8Lb\nzeD7TYdel7zVmCJayJKdXAqYfe4tHf2ggNiRQtb6rW7zzuDWxC6j9MOehd+wYLkKuWxcheZiDDGY\nXoW8Dn3gDgb6qmAR+aoQ6SUd0NHC2KkR9FKyVg+bhUh+gryvAjrRb/wdpK17v8W0/2ConYAt5qvV\nSx9opD6CbxukzGkKByTs+VXu8lWI81F+WVfosuLsrM3FC7WwGAbBF9jP7DkjemdKvZgK9sQ7+E/w\nykL8i/agCWoq9h+u27h1mXU6LVJOUIupwTkiLc4gn+eMXDqL1Zs0XW4Ft6C5zRmojOAbLVdpcML9\ncO8kViI9Uir6g48iHpcD7UCRyJ9cYSxliNW/0Rb9paOHITEcA0vN+6M2stDiWjLaznLsiRPKqFdo\nrfGWs887UdLqjo8r5gfiIx3q6dJCU+McJNwPj2I3Jch/01qA1AnDeFImKz1P1Q3HCe1YUpwzVdVf\nPkhvqIK1pUei69jyfiI5P4YZY6+RsP2tTebP3EhStUcOU/D0JIBRQ3VQrJa7Jzg7XWISFhF95Ti7\n3z2sHCcTzbDUqq+3k6gp4LymdHgAeI7RRHTNZ1hM3gc+e2Uv7wdyHBjADM7L9XBxGBNcR4RN5X/O\nwHBTw2vsQLZ+ETCgA03rkxnuHqpDB0M1lN0U7rKFUSuPu3NDS4bkCedhAckj6irfUrxnUC0QgoTs\ntFKAHU4pGb6keU3Kg7myTPkUugg3IWlMW9CYcpswzcYlzxnplzkXmUsTb7yUni/FzJOxd2qE3yTt\nWQa9KaZrnpU1W5773WQ03FUrxVsCIZefTOPmIur8T7txGR8gnCqsv6QBEWRakWYYXlNDPF2o7A4r\ncVeo8ba3lyADQB+lGcry8YqZvA2wzuQ59Ct4i0KA9Mb2LF9KQ7bB1/9OTdfRZWE8PslluZPYlEzU\nGIiorzNfpWh8X4UZP3wT2l3N9GODYuwlA54ZzhLwHUMEGM/utYMeZ4VrLFEqJHjqnVqVqEm0obrN\nPZqP5mgXq3WGmC5pYfblJggRYFU1uHNmMHxPLzFUwLZgD7GeQfZGvj2C13G3y26TPQRTpuhDb35A\nvsAETZta7bv79C8GhKUuszAXdEQqSt1AoFC0iB1GHCSIayhEsCwyn0tZAjwF4K71go9RPoIkdhxL\nkDi3AoLRdpPebNp0ZkA9jEvHY5jXMLUERzVAQloyXoj2mtsRNxGVEfImCoMq2ZVf389ZlS6517uC\n4F4WcDbMyf0BmdD6i/dLuCSP+aCs2mm8HWSoppsZuy2SM+34/m/fZC3KiLWa61trhcRHNacVqLWM\nM1ySVSUKbL8qF/lX5NNiyWlQ/hIKgo5zbSVAjFIuGdhB47cwhr9qYQOyQP4KYaqkT8bOk0gV608H\n9Su7bdsKfB78LbLtQvLgcdNmpq12lLrtp9JGg/aWPRjjRaXmzfcImW6wBiDh0AY6WYpGq6NDGwpA\nhLfZGiij/5kgTLLcNTwUpioAt8QzoLhp2p84Ra3LcHOeoAkKE+yMQ4mK09MSzL3P8Ld3KD0QDPou\n1mkPSzbvEsAv4b6WlnAkHgE2C1liHlCCPEIbY9RLAAIFGGASnOKMf/JBTcFSO9khlVSyREctfL/+\n+2sm5V5I000OI6HLT4IQGxsyKIQvLst4SWJd8GdsMkxBNNQIYLCFd+M0FLfYVnhAzTiCmhTAdxgY\nRnLY7sYZmGyfqmehgJkb1ErB7sPfr8vyZ0Z0qTGm6pysX+dmnzDmfCExQjMKu2kaH/Jnkf/0K2QE\n0mcQe+kaAC78lUWAaER1hQxg/ftOI+igRhks1sWXY8MhssSIc7iGfYiaSX5yUYwzEYIHyeamk+D4\nBGZ+YPTRPzSmZn6JHsKxCpVHspJambLKzdn9L1iverJbe9RBJ67u0pDof6txNi6q6cx9UXuddpCI\nADEaNB0dJMRmsoCj/fzzaSGw17nmnS+BC3WaBGJJ0aCoAnc7XqxprYwTNjCwcfmnuTnz1ll4P6KP\nR+tCsMDxVPxLH/eOccJdv0WR697d04aU2f4TlS+gELkIjB7NOCRbsRGhdrgC41wGRaA+u+ADhUP7\nfgqEuPYH+Xlvsr5QZvd0mPJRtUhqeR2AuVxy+G+kreN/F08X6X8tMFL6Avnl939hF6Tg7+BCy/Kx\nsrsD7ivYDRBQnMEoH7qkapYrGwu2L/ehj7ukBgOh/3Ejp1E+c1s1tWHeKPFMNpF2yx01Jy+5AhDZ\nPSdTYZFa7GgCvLmaicDHdeUnz3cvuYB2rZDX7nVooQnhB8Rf+6UTzaLdWwGrNu6c81vDrNUZGidl\nQpQwK1Ec1ecQqUWRK/KRYcg6m1Ot+IeGKFnPa/63sxwZ9w5pVjXJPGPrKvbZa+Pia3+MyDaMUQhw\nBm7TiPETp8qNL5v2hc4ybZJ1/NoEc6gdnGO9J8VQT/rE0pdpllH9k8vOItKpkEd0jdM2GPJK7ZuN\ngT4VCNV6rhNPeauuN4NuXgK+v3g/K4wTktuiZM36cOktYWhuiMZu+ZjnMmX/A5QrpZY+t9Xt2bxy\nbHncUMvFL14jNC6856bBlk5GSJjHRntBzQZMCIPtVN/C7jb/kxC/Q7mQMrWGDUbmc86VpIqxeQJW\nzEbg6DHJt4qOKlU6bzOt8FHPe3nnL37FuSrsjXpMBPVMzU6CF7izUOh5UBzaFpu5fbh/g4VrqznQ\nSEQ5WlWoVXW4ZN/ojhEvPD67BMdowjFSWDwe9HlddgB5BC49PAYRBh+jjeP9WdnkJ6GMfTXpMvgJ\n26AvgS3NcETqckZHSEGXEL/OPVvIwi8nyhmM/7l2ITTs1PcfqQdiKkc+COW6I/hfYNUYQTh2Aifb\nDt5iI9OZplitDHVxotoP5baEwDpoUsYSWH4r+9DsqjnnDi7BzEOGahmcDVhlbI6rjq2uhPt+/p38\n+LkfOBeCYUg9lxYke403tx9nNLtpnFQ+qSkNG+pUBDWPYGdMnrduCCwJnxaR20CQJOegEZCtYDGD\n2Pz7oh3uP06B+ju74IrcowxofXDERrXjwd6aL2u1rgWhjNv/qvk3swUVmQ2VnYZVN2u1qvFFwOLo\n8xArvHTfDmfdrv+mnz6ewWhBNZHVrK6zR44f5wUhX3ohSyWzCmey+ygAmJrPygJtZw9dvtjXPfkP\nmq6gwA+UUZ2D/1HAOpktggmARU0cJShJJl/ZQbfEq82hZjpZo4tj2wQquzt3CtJJ1biCnMf7MQLu\nxD5o0THKOO7mjLvlVn1vM3tTUc4TgSqw79cpS2caat1pA6PVms/BbFd7QjoHad+W5Vxhj/3Wdva9\n+rbOmR2Hr8d3OazwSj7QDN+4RyMmE12o2q4Wn8ZIxoD3tJCCKuOhqSWPDKASZv/IkLTin6nfXule\nIs2eVAEvlNHa3yVruUydEwXXk81lM5Uw+tSdYhQuqPKwBTGysUzTYknJlqjnyiJoXPUd9YTrcDuh\nwFtFWGr8LHDBhe8GRsZMvaYVZ16IRpnWVDZXGMMXqJNZhBDZMowW7UiEdpYqEBpvKHYMG5ASHsOq\nH2eZFgW7h1wB2fWRp3zq+htPMYw1HPP+PNgsCtaRQubfV2+g8YN7JSdRuJVQRKB7HfbRlfal4MbO\nQob2YcOhWtM3Tkow+j+pMAfbns+amYldYEUnaKZZKXgICtzUe+8tc6c9xgVYa/sNKoIeW0nQBgNM\n4rCru5DDjI6BMNPTgpTdVNWaZG8SR5DzenlSrkXBFykWTQ4LjxfY9iSBnutE8jbzjzwPekKq0wC4\nGfTVpOKVUaTaZo5wkojWs42LwU+Fh2ieJ0FEh24ZgSmFkbiiKAU+zrc3dANLGSgsgvCfVs/nP9OU\nJ1hObUY9Wo98gIoZr3Gz0C18ojCwZEb/dDxvyJM56jypCZsl61dYEVTjoW4z8i9chA1Mzbxs9eCQ\nB/SAYWddeyQDiHx6tFAi0C5AhuE8RktZjQ2yt9UFiouVgJZ6wAl/my9J6gKj2Am8k7CzKhlfV9F/\nVXJXNDBDxuDiqSec9vv8heMTxQL2hvtaZRbS4Nm2UH6mj2L5VmngiqZpUahulzswui8rW1Y4Wnfs\nKRTh1jiCT3mA0NfnDcq01KTgR38nkQ32gdQ42NUQGHAie8oiq3p6WSea/2JzXYXpKZb+cH45ODro\ndyUi4j/yaktRND+QJjGGrC4CC8qT5iwirtXKo9X67CllayE6G25mEe9A+huiY0thk+QYib0Lmnk1\nc5S1eJxEg6Gq0HMfuOIW8ogQTs++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qvZJ+ZCMnS4whysx+BCN7ma6YkyIFNzyLTBKHcjS\nE4yr0tuw3kDPz5v78ORBOVhPwizhH/dYdZV6B4mpONFDbGpxkNkVK9fLeTarpzCabmO1Cn4BjkIp\niiT9kovJnycvCa/1N5GHTOyUxMQ7cIlR8GyuJ9G9vjXMwxgt/iu6Nhs8Xf3iefAXLo2vTG778wZG\niKCTTviNxG6RCk8eWCflhdYo1C27j+Rqirx/r19s5oysIyqAS+9JIvOVLIg8jHsKyFqJoA/bNCFW\n0Ygrq/HNoWa48zWRfKr+os8ajBpjXRLOUeJhAxUEyFZWwKTJX5nTylPs+PHtuQ1bmgj4YfnGYxvl\nKvPBm/3LmGttISWgPjv3bic5rgM/YbQJWlKrDbIbTkJM9dGIVqw26kNaoKEGhqo5MGof42C6lrXE\nqRv3QktEZnMKBxdGhro9rM+0/4QV+aqX1Mk8X2EShfFeGJrur3mnwzkou97INnrS+JcpT7To5jQU\n8Ig/dgCx60pkXDh9dcoI+//AXBmIMTNEgpsdZ6wXK8vuSIKnMPcr0ID+Ztxy3w8MRNBtswnCnLsp\nhBP2QoArHvrGmhDZjvRiFpzhslgdPyiMeHyaQCICXKOF55QZ6sa+C9DkTJugfp2EZQIga5LrSTc6\n3rppuK6lJ1j1+cYnKipG2R5TcJtZYEWShSakYrnc7XPyQej0Wmb8qjCXO+hZmkIwnMTyoiWGBcYM\n09bc7DVHXvI+nlwPUh2GB0OIBveYyuUVzALBfiNkLkfMZ4Rqt8xNNMrsmVGziDMhoQ6nUl57Io/e\nlClBb+8fioCu5h7vDGc2/iMQLvtjWVYutiTPp36vtvUG/FoMa5MrJ6s5MCEAqI85DRmzUcebGP4v\na/K9n6bF6KBPBtScqz8oZlfhCGDyFCldXyqteMR6RZyV1yKKAXiBunsqmukS0xXpk/0BUbHgCbDd\nWWxClazeNUXUabl4DDzfN82FipbyFe8ShlLA80QBEES3Qp/u2bRb2cx+nnqcV48ReQsr4Pi9H68u\nY4jtp/sti345Av+WI96CPNYanltsmSKatJe4mN4X04++5oxfI0B2IOB6ZrHLPPB4LAPKz8/FiqsA\nKrIeX7V6Rw3X6sqlox+6PvJcpK/xrO7wCPcz33aZT87UVbK+rFka1xcQL+8T0yUDvGoKsX+1SygW\nWOu5fA6jInKD1e6gct0HWVj85CMVGApFoaCYCY+wKsvxUnJpbYgdRUMDayFyYOcSvPcuWrlc30NT\nzHXrPRalxD56Ym6Q3gTiEtvwj8PegDnb7EtcZ0uwjK8OCt/U3HrmFEscrH8i1q6alcAPKtq9WK1B\n0nwlZSUaYz+DnXD+fdlzQl4B6DGP+z65+kJ23NNlQ3O4FBsE3CVPVS1jInQYFN1R/MZ/NDsNKcT2\n/9HOVf54MFx4y4KYpD12c6rt3mrL03cr0AqQpOjfGPOzxZAOsxsGx5pydhpitDOsT+YLpdDok65f\neaRNQOciBmskv3OvgyoedBPWUtssp4dZRWivjakHQ4nyzSB6LPBzdHKugKM7Hiagzp3TqwoBg03e\nocqaUwsmLbrrweIw/zClSv0Ybb4PA11ZEnYLUTtBEF5Nvzl7ygkiFthizCzrS7TZkkJYYB8ltUUs\nzcOKgYFoNkTomQdhNHo3sWyNjhqeCijCSV/5+PllquArtqQuzLrMaQkCdQ68163mfRWsbzKIUbuY\nLAM/FnMX8/HTvqZl8gSN1yOdYrn5yUM00CeA+ShEd2TiKPWygLaUZ2MTv1YbNQJTZJRT/XYKjJQ3\nPCmoXiiSpSvl1Xh8mrDaeqZI/CR5Xo+7ItoX/fwwHs9nhipM6AOPthpsCJGNSpl95Qd3V7BZ53FL\nDAc0aOuivhvZCafQo2FPwjV+wmeEEBvTX8fZ0KYdJ9juXbCU83XRxu37KZxX6UieHu5H9sDi3v7y\nlMOmlu+PZvNPh0YPNzUXb89xjhl/XkrP5GQB/Puv9O3TAheVV2l4vi/GbfC93y/h1eLsSzkIHVAq\nDQKexnt5GJrnKmPCE0z6exBRrNPLJRxivLXsgEfcNg40OJAxbtsiL57zWkswvcdymPifzKbue5b1\na+sAZQZNc0yCKa5H8zy5gqK2epyicY483zdRS/BDHGdi+H2zwcOinQEbWt1uv6iKjOin15tbfsvv\n7PidT58wPRvkJKx9xaeJApmPB0x/z/UQwCGQCSp2PriFN8Yqv3vrUlA2A97FbW8rAoNtU8l1PgPm\n67G92DFxvYzMsjrFLicOXoAq0jWkESzbR0DKPmaZKkIShNKFlJigWGDVNPpMox1bNvDMH5J7LPZ4\n1wWixDY/ZS16rUbmxHdvfir1t89trPgVxF4jXaQcsnokQwDLQjjj41WUeZR80CcrJ927rx+f7tHr\npWhF31kQEDHgBvQBT8/POvhWv4f/mAfNwYSWylKvRAH6+sPoo361/wxXsq2q8Tc5m36wCxhyKS9L\ng2Wgjd/tDIGqlKNVTMaROSrU8YX9sZDpIJp9sMvnO4p818XDslDKxx1yNDIG/WxWuS+1SajgzUpe\nihK4Q6cnKrw22SD76yZE7Q4vtl4EwPNAisrd1ooqjIpsbW62kz7zPQFK0I6otG0rwwZ5YidX8FCa\no5M3MgSB+gDNka6ulGapZFd0IpvK4uRo+QQMULNO7QIM29KsTg27G6vFaAOPAjJm9gt+1WYOE1XS\nnw9EOd13mvBVZ+t4t+TY7SwE8ThnyRJ1gZ2L7Sg//93GTdbdEDlFiPnIzARxJzBudVU+3QEXE/RH\nNCnfuh3DaThukZSnjIEG3hNae1YBonjqFdbQfd47oOPybmPm9X1U+mKxmuPF5OQ/GuNe8oxKnu5C\nWdufrxecSlWnGMusxb7gbzcFE7dDL/grNTD9vQ/JPVDYfXmsBbGUZm9unK3Vun0XjadGgvRH+rfy\nC65jgpDIrKeWZr+oQW6dRLHBuYKMAbwSJE3BoT55PXuOH/dL/QvfZN4kgnFmo1yI9wgh1SSvF0Xz\nHrdg1nZp0NStwjiZURc8+UtEyOO3lNFjC8djdRtJDYf44YQZjyDZQtd7jdIl+TXJD/GcWnzhynwN\nTGmG+RFMk81Hr42hNMuaghElfpVbtIJnJMYlvmxT72ptojCXy7hczYP5vFEW0g++4dz7DZyk0sNM\nUJimDy3CDpgimqEq+KtxF0vMeWWTt+pWI2pAwsd4GfxrDcn/8ApWymuXE2ev6QGhkHLWwvVP0jHX\nwQjnUKDfHwhhe5WrWbCdPHGiDLEZ0ad9baM8ZWRhoilq81aalMGswIzIEzluihzHoobJ/nwjm24+\n9Gr7OS80DeyNDBc0+dtxoCu7ro+OWvfxl7myvwwnvq+AfPzWUcPNnI0K6xgIVpngiSqcjaGVFudV\nQrunp8i+ykRRyNhN+sH7p1Z5bWV0RI++6WWCOO55zp3fINIipPizzRWzQaq4pS415l+BVYgFiF/y\neQPnEFN0XhL4MlRRZQ2C5cVkej4hQJoTFbXMCCGzCos+M/6WVnK0RgBYp1uK0hcpwPz5yEeRb5Zg\nYLbRBoqhm8M5Gc2PfSRW5LWeT1NVikspCC+zO0c+2XEcl74GBIM/Os7d2YPYnQIwphJ6tcGd6kJ/\n6zwtKae0LKo2p4X8J2/LXPKxhHToHjnZheRJN+Ws7bhWQb0awbS4RjoAgxQQ4Uq0atWMLjk0ui5J\nO6HXgVWzY+jzCoh6shHixW1+BvGwxUy/Iy+iUwU9AYeG5W9S4ZMOP0FKCDu/DhHOWn6AHJxhRDbJ\ngZsCnwtrzo1teetnUOZfEc2eqto9SeuZxuHeofUJRFiimCVDXSer9XnIc94XzK3r5aGLtlQdVqXE\nrXR58StHCXah+7I2Igw+8Yp918fUg5/ARHntXb2ToyiogzGS7wLlx0ZRPZ777PmBHNwDGr5D22uW\nEylrVhpmlgJfARtHEke46DXR+vcLzW1K1Z5GSyvnOQVOYaPE/VSF0chC1L8aXm8TykNWOsqqFHqa\nizB9aKBGwoBrzzLirm6b4zIbDOMD4bBsmTTVjn51LN57+7gUwWR0hF6KmUNuGDDJsPb12o5jdpC5\nhuzsXk/+le5CG90IcxAN1aL0w6s36e8xoDnShTDihHvu9Npu2hMrXXYIAc28kSLww2HdK5Yi3BgN\ne1zSyMky4ACs+RnGYvWHmP0lN59X/+mLcZRnObeYLRKpAzRrSNi72f7AU7LpdsxxQAQ6q6jKYEs+\nA5fhmyuUW3G+AaF52mpaRE1OJ+YKw/qLj4R7boI5jZ5P40Z1K1fVRCenPEFX6IEb2NcOlgNjLNCf\nfiMF5mYFGz0eamcRhM0RItlZkWNJe2Iakazklay7mW/V42pensipU39nBMx5fq8myPltRu6F3AH9\n+zWDsJpDTn4bTYZXpOwTmtNiSm9XnTZbviehgqe0OHUHFby+i0XtJmTqoqQHlJSEt7vJuZX643wx\nqEnZrxMcCR6p6psZwcxMv3qfVsMQtWp4UB4w5T1OGtxY5ACFqjDFli1CChYwcHDdP+LnMOWoJReb\nmrJPq1Yp98ZTUpmEAeIU9CCgfbLLa9oyCcHfVa6Lm2ZT33E/eeFer0L+PPV8hloIiWXjWvjIyKjx\nInZpJy47H011IlrofI5xNkU7Pun5+/cabxuuL6bFc7Di6dNJwwgrU/FBcutPz6mUQ9ATroMac7OG\nn8xMFAdWEXH05T4KcdPP1Yo4jKE77NYu1JOtTxbSKIciRZGFBKUXwkMfmkVSrio/6ZvPUSO1ATxm\nD8rndadTmvy5U4N4uwE0LDNlbzRBrQEpJQV8kX6Yi3njGLHUes0x6NIgE2ou0eMnsNiXggENmqbR\nXq/UGbY0yHLg5mnmEXQX2aJu2kj73Jqxnf1ie9QhkqxPTt9hDIcb5/xqpdnlQQCfdmXPz5BAHuMy\nyTpHpGLeAp7Q2VyDM+6T/k4QWVtnnQd4yR9oJFdO5c1caLTt5T+W1wBwgGhKtmqYsdb3dfnfuI7P\nnccUl9cC0cLt8jOVnbVVklyrsryIvWClOEhTSaOwmmsU7sQsFBPLDRswYednMSaz3Fr/ldTHIH/l\nRNf/5rPL/sepbycc1cnYhL4lMI8PuuF3TpikP5aV822eIq/itmBp5FeWOFTlsPpExv6FN1KtextJ\nlm8ikFNPEI/rvndxBE+5kqTA7Ut7SiK5OwIWlDxbFKX8GwaSkh6gxecLTN8/DjhU2R/uuTAZgWRY\nAHughyKHd4V4LKBLK/VNlu6xGLmu2RPpAlV5t32adrb9OdBS2BSqwHc34tYnzT8F5JnIiYqdjlX0\nCFtcql4nv5ea9dSEaTZm1TWJIl8yJanGq4vbxLknl/vgtBrCc9OF/ENyqUhEop4c45UYDpCLaAvO\nCDU+eJ9/5Q8DxVE9cht55IaKxVEhUAQjahx0UMIc9zzQWo36xPFw6efhpXmCPHzDgY3CirPIST9U\nZtJNO7hsvkRXUi6UF9k3SMoQHugIltuGT4oaN2ie8q4hWQAAFlHDbeNSIO/OzTZJFwRltUzW+eP2\nL6SjbIXFBbYeeGDutFw6WZHmhNTePMBDL/YWxwEDjtq1fD6ZOZYfWHxo5Sbrj5h3AKqAvjfooQdZ\nNXZ/UI5HRrK8LkB3d3OS7+8QedJy0l0hBuNdKW/9ZSV6v/aPaq73P5Hsxwub6HppOTdpuhc79mGQ\n/BL9pDmndVUjWyHcgyNkt+zcO9z6QD7PVAuNSZyCb2mI+Bff5GXfNbfpDPMpONpx7ky9z2+yr1dc\nXauIT4xqFGOXmBIPXbiJqIdb7ZHM9Gi3/k+4PBHgUknBatmkDJ5eecnrjZ26gwas6Oe5lVS5KLOg\nGqXTIVVFFpiYzK3ljzoiT0yeBqaJNI4pbjLfcboRyIF8VIWqoO2IfYdEhoC3o+i0Yl3keAXcLh+S\n/AXycHMCysu/X788u4qjRxfaxD0xjZGm9dunBZOgWm/yfFpUUIZE2ozu5nF8DUaEFp6vXVjSE7OC\n02fb7LzkwSuroCbayLt++NlPwDysNXHq0BbIC8BUW+7COg9Qq2NB2AUh03NHpEWm1uBZuBVXJxoI\naKTHQ3t6wWxYxXNg6z4TLgc170rTOlgGGp3YovVUcjXTRTHomEB78mYyHPLuCRrYEW2NQ4J0urgJ\nnzWCUwF0042xITA7DBxUAmoH41LK8eL/DYk2qg61L3MJAJUX3AAr98caLhagCUn01UX6enPIKQb5\nnWUVB56bgpQYcLifI2EwlpY7hK7HFeWXrHyhTZQnGd0p8gRSS8KuVRpyH7z0GeetQ/+myE/r3aOY\n9plLEK6QPf+vNoK30hqRzbsnu3cys/K1TggUEVmS4N2c7i7OcTTRe7S/VDkSc8ZgoQXnOpJVTsiN\n1v+5FUfsmi12db2BlUXAtUM9Iz+r/XxaciAzOgFgFHQfl+exQV34Ney9FwNtVJpwXFa0q4nIfts2\nekxTFNLzEAyhDYtgVffuOl4VnPF9BSHN6y508ESUrPdBJwXfHzV+jflurF1MCqX8G80p9xDud75a\nmnGZPak1w+6EfxPOhAgPm+NonRFVRM0ki3B3HZW5HKs0HGPiLl9Q3ZQP/fUlfHDCeKbvT0xWPKXU\nXXgxtu1ZNmEvyud/3jvhFDfmjh6AaCKi2XXMsh1BkT2a87E56X0VGZmscW8gdPzx2UvCqsOa67y6\nnIiWH+wTfx7jzcaZEY9tJhBxicXzVAkpbL7hh2Do2hGc83L4n+tKZ6IN2tq1FXxdUJmkVh2cLX2z\n/Jn1ixyJ9VdzWIdzkFKwLsA2QD7ns7QMs/dl8UMxO/RtjKahl4TZl8BTyQfFd3sQLIlQECEzfKX6\nJDKfd6WAXaTYDedLRVf4TCuwjx1rLab5XU4zhO8Q1Yku2qeKD+hth7Spsn+0i5ocMLoBSiCTpZ9h\nXn8ds3geBGqt2SPd4eyMefSzBIGx/Q00rnMIHHUVN3jQ2oxmAbAOTgsqd5GgrLdsLwRQrwpBZqsK\n3J6LAW5bFThJ8G66/rlxbFInnGCQ4yXlpbHslAgsDBcmk0nHvM9oG/RmlySbKcQ2zAlOxVrA2hGf\n+SWPpsoPahzsXFFJuAXtHzIM78ErCC2jCojJaoej3YR63BqdghIaE9nFiYcVBQmNBJCybtRZJT2N\nB2pPbfAVXCbVS9SFGQyAmmyOtB4sgXG4LYaMSgLYWttbh+Bq9gGUJaYRur19ZmwEqYUAWu4ACyAs\nHTjhc602LAuPwH9ZGwCO3EbfbFMT0AyaCqY0u6qW2OIOhNDjGVMooNmLyj2RZEuzlJcNNDOs9GYv\nKNrrEuZXcqkjZ5v0MjIkm8CXX9EpU/pslZMYmIYHuxUFOD4ZCC5htF4KHvR64VAfy8eJZnjElbQb\n+h9ZFi918azIWgSoWm5mPnDYXQUQhA37JFZMdLrBGVWd5J5zhrnOeweKYUsJOVz2UhrKIOZWpNV4\n1XboWeIC39bRJQh4+9g8KY8keLAK6avgMPrp9Y3+RV+gzucUzb8S14/b4UsFcVv0FLDeJr1qeYnn\n77ASlZSJ8MZZlEy5PH5iLp8xF4/Jcib7bXU0DgSOHqppPU01FWFAAFQ3pdS2vIaSH0ON07RDG9Qy\nDmlmF/n7ek/vZIjfOXU55wrDl0II6bocsUVBvIqMki5b5JqGzm28HY5AGgN+nNIEw+N1n4gzKNGR\ndOIN9g7gMcmFTls5wuBWvWHP8awlMGRvasNMXrgM1HkIis+Dm8TQAJ4eRFgDj9Iogn6wvT+qgShM\np1iCgj70yAabS6Ohq3JZtCernQSX13/S92WHEVe0YKTT0mH6HSdoodhQctB3XY4D0iiNZJpC8zqB\nHlnlP/RZft0zTU+v2hmkGePJb2ia/jfiGu20DZd6WM+8Q6cifUTUwureuHURzyZsx5zyUb9WAekK\nRW1xl21z+xTacEK2L8qi3EdLgEsZXUzhvr27O1QV+uIuL/V+/YLdwleK2RAqn5ROW42Y3Q56r/dV\ngawH4Wl0ANU6S2JwbGBais2O+2nLVwhLQriUcyYNXhuWc+7xPwsAyHw2R9M6vb3Kkdg4Wcfk21NJ\nMyVY6REt/UBtqkC/hYVNoE5n2qhGSpoRWVQQFCkbew8WzBWOZdyzmISJQDyy3b3BA237ujhb/uJR\nzRuzsGaaKnA/cog1unB1GU2VUljglPDy7n3Hesx5xosdn/gxURO79XFk5S/jzWaPBJuvpenaFFxr\nyESg/K2qR0dEvEDJihX+2a/GkpGghU+ZhezhnC/mapM0ykkmzBxUwUrSc/IMUWmpZCpVJrNLVYOF\nnJSPS3KIxdL1diiYh64ICDSHr9i7pqKueTjsEK67qlhAIYCk6xXck4I5C2kRjRThjv2EHQxOR5dX\nVe8XbzrBwIiyJvvCxm3g5+EPCt0b6EwYALvCH8WAZ91lCtTCFqomRB6/dUS23DP+Sx0y/QYdr15T\nRZTWH8LGyO1E1W08SYbUFZtMUnNPzcykFRMCYI1IUWLBJXMMPtiTWlyEltXCCL3kMn0AIwnYyFvJ\nn7SxCiA1qUsD7CWrhRpOU49dneEphwxJeNyz9bOUGxcuqUwJbnum1eH7rAtSANIQtNZaBQ2Ke6oJ\nlzJdhJE12MRV65B4Nsd2fZWUUTBQM2uXE1k3NQPO3xQ7bngSv1sJ5so2zKPo7iMSdH626ljtmqmQ\n4K6QlEtlWL0ryLMVOe8ywCbeCs0+KF6DlQTPjvaRIFgSf+/XUxGSNDAP67Ww6HJGJvhnJeA/bOtW\nkC1vPFANG0f0HbgdV/VGUIEMPfTvVWQI5mO8xP2mooXHRsBUytHDx6Xaqc/F56+ERQd3bsJ0U05A\nGY73sBTAXcfT80bail6td4LXnB6q0mGIcoRpavQcXpT/crKmwSJau6UOwwVeuKIBtvh72mAKOXFI\nD4jy7sk43ZbMnS+4o8p4lneUY8fHwRlAYDs1OFhi5nvGUjqRfrW4W7D6NjF/ao2Q+RWVwZYgPhmu\nc/QpJsPsoyTZyPYiSI6X5gQQRwgy6PujvtJR2cllkLm0y2X4BnRNbQthFy2DGmlXwV9jKpwHwCkQ\nNUudN5MZ7wkx/S9/gtj2iaAZzFSlyGE83QahJLMkTHh99PnViB1VScVdloR0E/9zj6HyijTBtz5c\nTvpFgdEm1VltojHW0yR3KPsfXBPNvV3qxZGcine3CYB38XNAoOpwQ+m9KiaMjpS+Z3g5jVSvEPRz\nI6Swyc2GHSslRqysHLDmqIFkPYMglv6rb3SP4MPqxcHdDQ42D2QUrIg5QGSsCFVKWYNzuMHNS7MG\n0q9S/CRSYZI6pd+BdxF7QMfYvTxG/z7SX1Y4He65yVsu0BUGxVAycgESC0yqDb/mPS5gu8ICCL/U\nKFYEMO8VavxBguJHpSOZqgfn9uQPdQKICYTyk3gkYwquOIgMeAzUERFY9rDolU/bFQBcrEE04bCl\nGbT1w4HHb2SwKQtCKUFOU/iz1/RQhSELBLKUUWiylPcK8ah60oQCSYEw5Fp/BmjNb6AtVYKSP5lu\n5OCzixPZqSYs/qpGhwGoFduI5ihI6wWRCEmtDWr4fn/VaQEIhnrCOaWyCB7dopkGrzthw/KTqugv\naPwLPvra19o4S7x9snvKUE38ohqiZ3jxQqQhD1jzOVB2BL5T2OlqTN20EzxkwlLulKoNVmKAloLu\nK81FvAwebD4TJBam7Dj09uvH7Vc4ovQsnweC5ZGwKQHDr5l+KYUTpuzAV56b1L4mWVv9KC1AuoWR\n1+u1AypMa7rfYuU8J/YBsH3L2l90hyykLH38XhVxAMQfE+rppwXmCK50Opvfu+3464I40J41o3/U\n2ukQgp2CV4cEALbpyBdHPBeTVEsGU7XgzZjhL8ywTq2g0uOMdr/GUHvajFz5WmKBD1Kn2/A48CSp\nNOF7aTFa1MO+YxEGpsbEGFzGwB/8DZSAS44NI2IJwsH+Pqdb5mDPEp99GepNImg4ax3xuQ5/fmM1\niCvyST6YzO9vDztRrx6DVty4yCz18qh/CBLLq2VO5mQjtLwx3EEoU5WRzivutrc7rYh7fYKPzW6u\ncMCbmpHfD4KjmtbzdCp0jbtSJ702e3alBxvL3fNxgtubgy1qwi8RdognRQaW3lJmodwMVdrO7qL2\nATWjJoDQ7N1vlYlF7a5JdHlqQdFmmyEZOcyxul/lb+66+qwRWiA+s/AxFe3OmsWkfQrkzcrm3bBM\nYCgq7RiGK/Nyg5CqZcFt6sIPEbjDril9Rk9eyfW6+rg2ti5qirauu6GTi89nmG90XFTqbWa2INSi\nu/+J87FDqz6mNQjHTpylfV+unw/2zp2uejZSOmCYg6slgJ5VzEmbLA/loWbbF169Jss2HKsqkJU1\nFDucH9pO1HhVVLLAgvzdWWSWVqHggZ7fdGPKKbND/q0DJS/MlSC4K9wc4d+a7LVqf7YfcArWJBSw\nb/CDJopZa8X7vfppRshZdLKB65dkiC71qdw45IYggV30dDfgL4Y6lqB0d83MFZ2fWmFGA1k+6opi\nCCFPqhmIsVyJwa8YQWio6rNR1n3Kf+cb5LMmmvDH08KeKeBi94wzMkfx8HbU3C4pNA3tFI8HU5lu\n2zYjSejh21ePxj8+f7hNOWHj53eIVwlGFJbeHtuOPKRCUR0ofAhhjWRTTqd91EmVEEKVQGqTsv+X\n0Ofoh1RZyKvBRJFf2qKEDx5HrHBNDup38TtEIQw5seyIR2VVWs7VfqMlt1PMiNCEK5djB6+o6Vq/\nPx0LnlJneHZ4aPg+7Jdx1UYG072d4qEzCB1Xqg37CLd3Y+xHDV+7QDYT75oX/2vO/RsHH8+4CwRy\nrw0knqI4mwfuKMWauSJU5fNvt6owB+BumMxKi6CJn8q/Ahp/Qkye13tRKneKn9RIxeKkXX4bdp3U\nPOdPMfTsdf5FfIIT9fsBZk1q+DN584O8YXhQ/vwoYlxkO03yFQy0t+v98xYVtoBWsnIGcVXZNaGl\nFp1BakMoraD+DIttVaUf0wB36pUfnDLTDvuHLmpgk2XG1LmVRvfdZ52WboncKChN3klluk0pt/AS\nKBTVmhloAwycTXnHnam5GBIjPwPDtu4qEf+m1DyGAo4egZXTy/t8J7tOICSHhwa0V4icen50x4mi\nF+80cHQS+r6jwF0I6P1+0waqv711ZoZ9e8OEeCKtD9cg3UxIbQHJ//qPhG5GqYQ79nNCUcxL0COr\nSihjFJOyM1HcroFKCiJuOCu56NDvE64S/ohFW/8B1RyBPYqcsGOHDusP3PPujuXmd9wra9whktlS\nDiBxU69cPygcHZGCAXvFCc6/4qczdg5RBWeH+cTSnEQ+LQqWVNL4KQSshKyGpjX1CQtCARE3/khz\no0pMSYSst5xKLVspDiAYAYwmHaMhq30l8dct7s5EfvE3vTEOpYsUgzkK5FnMpTMQm080koGudP7x\nS04xhfKQ6LW4wSxG0WxmHIr3hmuVc9tsRFZ9T1mIH5KgBBhi7XEvYeFSvhdw5utdWBc9yE1bV/IJ\n0vrEHBdEJQQ1jC3JHiDeNsWkxk/8VV3v1QMAB8N793KXxgQ/1jEoCwo4r+DgCws300qN53E2O69u\nJKMVjejhty9xQp2+lHRIZ36dvXnVTUpvw4PjnRr6nvdxbkar40A1xSTwZtOv035brN6W7IDeKByR\n9CV6S2CH6CocTKT9Zt8vPpltk8xGtfZvL6iP8+E7DEyTKpJNSbto6tPn78lb2k5J+EbZgbkvLq8M\nTagu9wcsOPFmD6zm8ytmIjLDQnJX7Ly06AkqKfoEgCv/RX3sJDmhLxuUrYN2P/XZyZEXHtLmfjYB\nsIWtLwccXsmc3oVsi2Pq7OJa6yyIdyX0Vag1r3cBSfGMXuhqSEbsGPpHGQAb1bemX6ZL+eaRR8Ir\n/eZQNuhoWG52LpqKtzgzdwYD4dXnawZEgrqPm6go4nMxHajMMT9x+EPRWMRCblVLMU1luSH9kaS8\nMkIoiifAeNimveh9mQ9+m9uCae7DWwiSrDtGe5S0aFDcbg5demK9BS6oJ2C3dBToRiv6isyitqJ1\nK4hru5Lh0iC4ja53Qd1Vl1IsNzYAQ9eEtiubhzCW0UnxLC9l1YlHe0Okqfplx0X85fEe2NfClZkN\nMVvns0Q6cI1RCZoehNR7MEbMUb9sf+YE/zd78entJAGGQcMvgDqc8GPH3Ph5iq6REzmUCizdjv0I\nQuRHIwhl2tSwe3c7oALp7AMb0UEUcEEa7yNBMnSZAwJHxxIcLHifNZnM03He4c7JsB4yGdsZlDmm\nzZoBCJNcbpyRnlvDk7moNefE4BJO/fNaReEAiICWIlZxQA9zDxlf0qEz2FZgadqLiPvXKd0SRjA4\n6iDTL+0XdstQT0EMQUdeOAiDZ+gMhw8gXB9TUZ2KzJmzbfZUOKnt4Dk3S7ZP5reZ67wa9T0Iow/r\nK6VXvm9MDYeTLJlHKJb26IFas/UWABGe7CEM3RCFR5ryVylbEh2frp60MtSfC0mHZIPj4PZVdoNI\nNiG8ls6YxLThfFsXWp20HODlp8vhiepNTHOGoXXKgqoP4qHxUDqUcc0RwU3Qppj3tAK4RurMczSz\nhhlq8xWyWv5vlyJxmJzk7hfCkbradsEVNkfl6K9Oahz0QpXDpQf2iFIk6sdPbjligmhJi1mM1nkw\nG1OXII9kBqnpENv9N9RSHAqqC2EZ0rpCoo86Ow5r0oOJiUmcc65rAomtlFdRFu978TKuwgSK9C0+\nlvBiOfqqfF1RXBAt3OP8BIZgKX0duUVG6lxYs7unXE7WrDkaG3V/VbM8WbHectyWnEAvRcw0S9mS\nDdiKwWKoS0qbSDhtaCGXzhWMnM28+4kegOOYPbRk/Ztu6Uz4g76nX9OiU9zuNUq1WLLjEKfHhK8a\nGSK7TjD0XfBFlJBN6zICribUSvhRDQzFzH7HC5lKMwntykOMgHH5PeJ5U6E5npyoaAjscpk+WPXA\nO7umsA3PQlzkImQmqtskI30+FAMhso1bisaFVT2D0o3MCcuLkhHfMWr+6sIBgfjsPS3K/nIc79Q9\nW78xWZMkiRzh/66GAojp5UtmS+9z0Yefinic4ll5BWvFt8Nji6T5qr3JNbmRxSLIrWy6SEQYWFbk\nuvDa9GkoamiLQGh8cxjQYiz4sGUOXLRClIx0n/r+aCLxc1osC4zXCCC/H656dE9KpcyrxrxNNjGg\n2Q/qsDxIDgLGrTldEhfzYQxCutaJFSxO5+lBXt/b35vFIgu9EBtQDrf4Yb/vRBnwosJ4EXFzhc3t\nCGxZRFmfJk2EolT7/9M5D6mI5D69lbzOGLfsas8scb1Fu5WzV/LVcuhOFhwOfbhxdKjynFeYJIlM\nMg2Y8V8wIoqQqw/LaPQs50OVfuhNZMfG9jmA+ExAZe/ucokZeZna/5j8jVI/rtQkEIg3A9fboOJs\nI3w+MI485SEWZ775L/kBv3b+b5mquXpb/LxY4Zzek05EvFEWOdHaJHOx53f320jbIAufGGFQ7S+r\nMLP5o3+SIoY8UWBBcJL/pLJPPMXYzHLYwo9sUUSrSNf91mMHDv+HU0Wh2eySI5i0INK9gBkxx1fe\nOnym/qYScFhvYPMDuq+TPTH0iEWD46s7Nv4wuIOAq5xV9O3uryeKpUQziY+T6z//hsGBBWNbBl8w\nILc8gwYVkfUv/2L46Ne4F0DRSMim/kOuxiN/MLiwivYwaMYLPCHBYTLCq5EqNIO7UnifZgY8GmPv\n+dI7bySys73tXKSYwPwdbvMeqWjgnm15QxWxPxnL31tSCh69yHnuR/2UDjSIAvziXETZPI1wgtzH\n4zNfH60m1Y4fzEgIkEhWL20v/86j2eS8LajMp6wG+zX/SH0ofwqc4WEYNTUUVt0txzLsY6vccknj\nAMiGAZ9WGwk3ltiCXvSiA37xd/64b7OTSOxdAKC4lCMw32HOZK16d/EHl772X/CW65LGXjBwz+g0\noKGa2hjFuaO6U8i2AJDZO+yb5Md2Cr5tLRbRSWmk81RoMVUqIUbpNRAsjbXUGZpNblzYOeQe0vt1\nf6PxfYHe7oPrkpdbVGRb6G25F5Js82fbjUpzX2HDdU7Il1twenLOBN4cdD6eLejdhO+pwQdYX1pB\nQYJ438wpPpXiwEpSgmIMlspfG1mNSTxfdEUAHgFRWzDvdbBaWM8XFSyfjpZSVh3K0/L5Oz1KaHMK\nmlL84qRPVU6Rp+NoD29VfZb4OyRsO4UNd4pduIp4FeB0TQVM95pQ6okMDeNIceKcw1O91PWKden7\nflkLY+RgDV691cdU4QbC2BRx5asY+ZiKu0bEWOhkJH2/KmRJITdtA+7xavT839GCEWYZCM3YHo6B\ncuw/VqDedEV4xND7mx0bYG9x9guBtGVTHiDTyb7phXjVe7Fyi/x5t8VufShAgo/rtyoswiJ8BhlJ\niPsuCwoul5MxCFqHLK5B+UZJqSIR9/1VIFuGceMk5Ubv0d1H8Z5bPpQwCvdfLL07qvjUEvpa5mUB\nuJJkNEG5juaNM0/IUY2FxPzrNx/PTRIjl9LuV5dlE6NhxpbJtZRWPj0lE8jjK1chUV+6+2I9lrTc\nrJ5rmF7L+wbi4C9Dnp2x2xYaS/tE0F+VimsBt7l7B9bAarIiivHNFgTe2qE/+Kb1M3H1ct1Hqjm5\nAL1YaKcUqsQLLnEvw5cPBqQ8QW32XBuof6yn+xxK1EOpb7J8gdZC9ud9Atb/F+rDUY3Zk042VOJ9\n+38BfXth0Ew8oVZmdThyt5KDvzgcpYhgHwKbx8cB7uW0LcTT3DG+SLkqMgun6MwLUownC1+r4G+k\nPOYQgyWZ2hwdrVfUEm2FQ8T7jIjofPdRiOV6vMIyo1LQtEHryCdfVlFdMVkX+zEa1uMOonNlIG6F\nqlwAOm8pi+/BvGuB+BRrikGczOJB0Wg/rgpg72XrFf3i1rneXsCsO+VpQRvcvl0H7+GloQpZ8e4/\nL6/LM7YId2uE/6LP5MJwBkwdYhnQeIBRDsaT4SqBqvFFGUwo9XHQ7BX9hvDKJNNr2WJx/TN4DGSc\nQSXf7zNQkznf33MkIXuht7XWfQq0F2JDmeO2vQWLYbSyGuKMoCeZqlWTINTX0kKL2gXogQo0CSFu\nl3yJUjzzXg8kxWRp881QDeoh0QXJzkJlSK9RcBJyAPoGq8MGVQnhqlZCaCtKwWjxXPJMod56Ofz9\n6d5QEnLnZTdUaNX5elPnAy//gVbggUKwOQ/skaVSauu/sHjK5FOnEBYk65Rd7tYGD0NeBXwgdzq7\nZjElbS8KS/Cefr+77JrYrMx0aZBZJ7PQi9t6EAB8LJx3ynPMFiOi1mFRiRTnoOunlquPz+IQPZCz\nMGnV/sBJnYWAFfT6SVllXQSioS/rUjluR4vovLgImmCkRQKUSj5xnZdY4AVssYcDjdo02+On7piN\n8qNFmcN5E7Yf/TncOjvzUDpXawtm4XcUunz6fz+TAFwd6SFGP3I6tLXK7Ell/AJ6615QZubiMzMy\n5isLZteUKQdn5qY5SU487hB+j5EiF/KIGAbITt3VhdHrimshB5ya4LsOjyuKLV8kB/V2FxEcrVP5\nlPsWo8vJ/pCG1SE+UmhSQrWcx4/NM1rtR7bCmMtSfeu3ZhArzYJK2EjxCmwxqxivMXGcsAByH55s\nRNnTvl30k066eZStn34hQlok8+Uj4MJAmSuHpOlft5Cw/TOrk1MOZFdyyX5HyQGbCwAhDElXG7Np\nNtIBPPZERmcalGEy/Owm1PoUFZGrD0ygMaJgnLTHY6MLYf5DaqbqAsq33MOscg/qw0ro97IvQveu\nbVHyQ8dKOw0H4XCakKKp59qL+Lo06pAmqctYoqEAI6NyA5PBetT83h7XnqI61qecb+efcMBgjAHx\njfy4b1SDC/HxaiPhae5rVoY4Mii9nQB7tuiNNT6Gmu1Vwwpg+FqVEjv+kwb5pFPKdcoYZP+5TaCc\npfDutBLUv54hLF1z9ZTSVfm8dhinFIriv3FGv9/qh+OBVnE05kFf0guuqhsiraGuH03jxhZjWfyS\nOaM8SAV0mGwdime6bWsWIdynqw2HAyQx5ZB4Y4WQMUkJTUZZqfnyJoiPtmujk+CkRIbdfqOinQVP\nO07DTJxDEzoF7uhPsOTK3EFXwpS8pYBJ6rBUpkDv2cdF+nkS/+/cAXKl/YHTpBgNyZhjRpWyxHsn\niFcLNNJfu2sWWDKVydWGDedDKCGcvqLPUsStmaG3e0WUzqYcTIcOw4FcGgqM5B7L1taswxouzywa\nIj0O+yHtm4lcDaUaPBH1jpC3Tx1teYcGoV9p1KGhmnqYHidnh8j5RR7mQphYOBTEDhrfxBok0oZp\nxEb5R0n0lHsnE5wR+R4TmYpqKaUpaZOnnhRH5vBWzpvNoXJZHsCXpiaDJFAEE6vHItaTa0n+jLX3\nsAKceIWi2N0ON80jpDAKDd8n2CWy5iOPEydoKV62sboxWYLHelvWFOVdHFqza9cLsXbUMPH/vDsB\n8zUXcORUvcn7XjjuxPfPOc0t/Q0dPFlQIuhEr08hTBnRjrrlpX7+x6ZTY+fPNHR9F91Pv0fPWCIy\nbROzbw3bSzeY6s15+qHzXfdfy24+QkpwFfNxBLscbYdYMJuaHRfUkYdyiSvy88tiTke0cWsJIgL8\nb6LF55Fl+0MmwuU9qJt6LFzPlqMjg3MTJMUSxs+oM8M2Y5lbhwQwyifFyhKYtLmLusjTARMM25Y6\nukzQRYRNI3Oxe5UbT7SrcwTUy1Lzewof6EN8wyjkP5FSWkYNXeMzogCzF/M5OPrEz3P23auJXL5f\nPSwxg5GwtiAddrpoxwVq7t/SXomVKF8qrK6QHhSEkffLcH8rFeij+Eex34jAGjtyYThMr2yAKAjQ\nvo4wSdK/C8Znry4ZN2XvcUYAMID1n0uTpMVXdijFIGLqamf0k6GmXzQ3UpVfSzrDS8bynQPdLLGI\nuxvSeQyS5cbAMWmj6MtbyYyhYMLNeIGeHc1Ble5JKk9XcBOCCFgzOOv31ocUMajLFqBtSfkqRVra\nFJiVtRF38mFRo9WKRHhb8sdoITC8hS2CTMQSsxPCAmNaVD2bJ/qFT0p1EZZq6BoZITEqjyAZmtZx\nXqR5qhQI4oxW96jPl+BN8zN6fFGwSg8Uc/RdDO4jXwwJaU3DhK6+dMf6pj/dlOYkkqJWJ5zvJtdI\nN/rpUYECSK50BXCzYV95c0h8TYbjLL07Bo0wAZsx9en9mAAJjFeW5J9b6bw8wSryqIlFuv/vii/8\n0NeNbQ3HukqaJ6WS8ig24kNpl9AaJTw1mevhFDSLwa3iuPULC+87SJhRoIKk7u5faUsPh5M+BdS3\nnwwNBqnyAL/eoOxdZGIbuQgqWGGzqOOHbG1kV1nNYc7Xp33yYYqiV7WseZtb4ifQcYtnIMXRuCPs\n0HNXHhr7bZxfYss+z0D8ocASvnpOL8w4nlKT2PiLsJ+jpVGuGS67p7kyScbgWATTr1CCJkP8hlGI\nMX4ceG7sdnxo3SvwA743LtMPEDxxTJV+J/+6w03IxGuA5NzYdhkU5Br4pGMfka9XTP8KCa/gkIs2\nw9HFq5FtvyOmvpOL4+vO90uK7rMdlqzeGa/PolqIB6YyPVJKLa4IIK9yih6/HfL4Dr+t/VMfsX6r\nwVNKcvxe0cS/qHRNS5g613kQ6UhUK6nbWfngwumJfxEVujPsHnfwLImvXV+Z0lpohVidsRwRstCl\nypmA///VlWrIIEfM9ztYImxJ+QCWHceJt6eh32pSrS1Y7CAJmjnpYkmyNQzNY63+27caRFAiePJe\ntSVGh1aHXEvlFIm5wia01tXhKIajPWowqppLHpWsZQkS1rJJUM4r0e11wGleAGGxpzLFv++3rRZV\n2E7P0LyqAMCVXwuJgbDCIUjKBeXleHsoXTjsTJ0RcfA16W2S7LwZUHCmJVq4hjScokm5x4LP6eKu\nnW7YbxZKQNnAIWffjZAbiPXmq2NpSzKlWV7VBEHvhB3WX+EGeM3dY6Fg0rL393oyDKouyjUWwtJK\nKkxwPWhTHPfGtMQHZyUM25PNCS9dRLKFvj+8Yuv+Cjbmf1HTxuUHNkIppVMhe3pp/EoYQdCKYkf4\nNmIqgPEpc1Xw53xrv3c2+5Qe2RPVMCBF8XCVGS08pfg+iaC35dIcxw6Arwcub7q1AJUHYWWH3e17\n++/sVHV8krkistFmP10E1UX/+MJ9cPXKZtgTdfX1nP1wgv2fZiV86BE76jaU7foSkNjoqQztHEvH\nvnjg5wHfIOBGVzLQvSsux2gimvtklrdrQeNtEAOAQpNS+C53UQWER5i7GMN1FpWJmOMX0AnM0fdP\nN+AUFHdOIyVfThnj/V74mNf8KRQZT8nQUqmy3LgdGQ7uPX4esG3SBEeLh2JSQd7DG8Rzy7bzFHcT\nR/lPn6HC2RR7J+MiEZbxOgXfw5CazrPTtOwGqDjFroba3fEyK6BRmL6ltjB2nnNbZ3QMS84Tngu0\nztlVsUNRQ0vVqF0YHm5Xzu/LFsbmB7GIOauNfKOdAPUZ9+FyQsOahJKfbgvle/vzDZKF7dJBesQR\n7G6ng9CIXGpMPYE0Je+/agXWFSxCKueeO+bxz3ykBrwSkZqafIocSh2im4U+LUrsdQ6Qg5KHNbvA\n+2ko1mWue4ZHKFv3GFIz6qy8sSdD4o1YWaRzp6QR6CuG/L0GNdQmSRM22JvOQ9ORJ8zEvxHKtsnC\nDDxX0UtcYsOlNPodlxY2wv52fihmfKKbhbhMpFY9wB8xvbiq2ZD4NKhflfFlzzNjsaAJtm07xKlJ\nvemry435VhaDY+TdxjrGnAKY8dtM50Zuw5GkpQQl8/L7DdmvUu0b4+ozCk3HZICokDOSzb1zTgvU\ngwko9mlZjy6Ro+IL6CNR27Huwainy4TT/R0u8/+5Fv179JNlvHyGxYXUa5rJRKrKic7H2nf4dykH\npcfDPpPIdH1kEIrpLaMjMoIsf9ypnvIpIO6RdGv6+Q6txwVGizW36oyiNd3BGZXe5F2CH4ImOqdT\nzMQ3d6iYRlIvqU9Kw5Ul/e++X+NLUudXHoAMRCPNbvPhB7hOYnKeR40UYNCDjm3KNgvMxzKh4Dd3\neQKaZuo7/YToyzwW/jjo35H8jGygVz0cA4hssv3j0DESJpsjI4uINFEqYK45Jn4fRPDMBxpU0V6Y\niAEQF54vjRcFgtShdk019k5MuVKNoQ+6ioiLfV0VtqEfVItvGAa9IlriFbDStqq4/rmdvZSArMUk\n+uF0EFdygH6DTJhAGoF6uE3zm+O7VytcdokHJmfnvl+LCSqwm2E9nVmqp/LTVl3GOKTP5PHZPyHE\nKCi06jAtv4vqhcRfdpwIt5LhZiXTuDrW/LJOqRdZXN5Lf4RO5T2gjYjgq+1ujG4JBq8ayr4Jhmky\nRSYp9fjRtfWn9lJAN8k+AdmkvXs8jy7wF2739kvWDAN/un1R/jxWygm4VjmCETmc3tgWZTBsyj3h\ndS7ip9ZGkO9ob6spwsAgTdxMfvK1vrx+UtwMbTZXoYLsDRtOHOpZtSlwqzdwlfTfP8wqu2owh4NY\nIMFNw2uV7x8Z19AnwHVSVg/+LRFyuUaDGsY0Tx2w+AWOhecrWJh18NUOCcw6WYG+/zLfHMsOy0Jw\nzbwdo+ynwtdG7mf4UVXSsr8vvwXKUGLzH/u7HLX6ri89GzLPTloHlsDEKlwnHWE+ElKuvbcbSNLz\n7MAhzh77MOCAOzn1JWSviNo9oDwCiru+wmYkeVGBLPncm+tbZi33xvyqZBmfdAiF26M8iEdZ0fC2\n9yNPdv8S/uO19rku7PiiqZvBEsudotq/zr7KC4V4r4Be4Fi1bhMPs17pJKEbnnZRV95jnZZBbWVl\nB8dCXMdwhms4DwWuimrqylqqF0BkHLvolrJ1PF4O/vId65g+6REAfD0mWExq5NMxA6QraCswyXBM\njO5ogsRfcuZw4y/Uft/kFMIM83hr6URIolvB7wRczzYNd/L/rUCnaBE2JIX+ZGd/Agmvy6lyaeSg\nQDDJ+ud46UMBCh7q2VG6ShlCYR4MyG+vuI9eUoHQ6OXuK+5XogDKPl1ThMXtIbZR37r3hWwh1axd\nlmfN8x31WfLCjsSFuBJExJkMZ5INe4PrSVpnMhT/MPhDbvh3TfPx9q/rDwDpqNlXg/4wsen236QP\nfqYOepmKZ/R5cPOjQsQp1EdDmykoEBb5vKZC+wJ2Ni7GDDTyuIUczE5uoWPFaOeHshGDmqpAyi0C\nYF3y8L311F3BT0yRTvNn18HPzKtJTn/lava4O4X0UK9gmPS9IUpRzvG535glq+TPTBeNNmMmjpoF\ncK043+6zBszbg1lgYMvoV403GptiT72C7uIAvpG0g3jR8ktV8ITtR8Ho36g3WEjUWFxurrhR5I/3\nMa4Igyi43BjEzm7f6cmxIh3L6OaadG2DZ38XUSedfRuMRuwWT60QG0FmYXdeGFv4215blbNsymcm\nk2mIDQbGDk/Qybmsoc7LPxjQV4G98NugY3JbxzfgqetsT99VhDmj0GBIG+LC1hlb++vcKjraa/C8\njN6NZRKehIkIZC4+vQS6gw27OP4PJrkOkXASle88FbbPhxozfa1WyIQrOq1xIqmLOHigv/faefeW\nAxTVyv8ScMVWcpI+jLJLLy4a1Ch7/HJ/igiVmCHlJm7ckJMbgtBVztLXQmXnjJTL6Pynsx6MKv0l\n8BVbVKIE16HLCsUqMPkgg0arbqf7yDPlygpesUhx0cUmFWse8vcOA+1H06P+4dycC80KWTsmPS6B\n5EGvU3RjL2y74HpjqP3MRfZBswhULeDpxvyXTaudo8034t8jEmw2Rp5ffDKcalxJbexN0612mGqK\nXqkLlz70YN9vIddrjYU26o3OdmYoBfN5cTWD72Re4pVTTuUqJ1HEE8xye8F24YDscQOv/4SaVieW\n8xM1S9bv0ifD1RYJymN5BCskUXl/bB/maR9C0MzQ47TZprWfZ8Zdhg9whQ54UgBUNuESTH+6DGs2\nACGSy1Dns4Y1955iy1Q8actfsbkIxYi2/oNqHZ02D2Xvwg3tHecFHzolEI6SlfAbGebSE8zOPlnO\nDk5WFDm7R7Ya9Wzde1ycw2/dEPIiNXKlzF14E2Q5XodVnrcpMwAWMhgnnuHIE49vs6jmYNq3GQis\nlhQUwP/dNeK3tPco+bLYIdxZJ7pWhl6d05lMr3MGDeem4/Cpl2QjnO3aBmxJ8J0XA9RR8gUjA23l\n3vpbX7HbQi51qCNjyhGK1Tmn2en0/fGcEOGhZyyCvJH4Qo6zB9uGykWijrxVWG4RmvxqKqqag0FJ\nDlk12cU1XziDHfGXtE4VhXARzXiF6esJwhhcSD4ZrgY1ji1RUxpWB+b4TuzJKPDpWO79abKalORo\nC/stTdrUrz/piO2okmJ8sOj74MQPCPxN9rpJdhy2k4LrMMhDh1kaspAmkqlclPY1falbZE7cfe/0\nin7NtWeOPQrKTl/qhE1qao7k6Ua4ZeGWC5GHaS2ipHen6ikeqettySwzRKBmkdDQSHamPY/wDQo/\nVo5THKpvcnZFmnuRDI9gsWrl2HV8Cnu3cziisYvsdFyyjFJlLwQI080Hm7YI3tK2ujDpuxu37bkd\nVnshVjH6Lm3O9gsdW5jBFwOx23KmV5lftiKdYyRkiF2iMjSw3tLSSlHQ2n29KzYnL1G/26FjOuI6\nmThzBJljDQuqaE3P8+F0mWoEBHmZCjrTaPb/too5PFL5RvZtiGun/PNgZX/pUEuzDeQeX08IRmek\nEKmkvHTs/bc7f9diRmuKuZ0H6KhygPZAuIP+2JJ8Zcy94C0B3pNqkm7GypUhQXN7SZe4ND/q67LO\nmfiUWXZhCIigT7LLJt8OkggXTxYdk0ArF5AA/dHoUgKcvhfFXSnNFzcF4C42BPgt5D5lWQUDipZ3\nQ8715I9sCHyxQVihVdsS/jzu8jW7ZiT9fmouvloW+afVRWXnzp4xWrqsHwJes5dBP+OMnR5K9XyV\nwpOQXuAExmx/sSUECT2cwytphepaK9GB4+yxMNZU8XIqfaawkSCeupH1jiH5ztVfu01WsSVZL0Vt\nZ9G2/wCR77e+YWHiga0WAuSbN0Sm/kAOZTbRQ3Iqu2L6xEwsAt5OufgkCG3QWEA6ZFCgt/11FtNo\nWCg8dspVc7wjJGcaQh62kkHOHeKyQP/GPfc6zfn8ojkU6lx6BtJUzVc9+5iSeiziOxJVcg+XiNfm\nry1bTBPVqs9V7GfXZMNMeTPpqgwy/SDSL7PSaaGXTc51e2rpsZPCv4PWW+k/3SAK4kBHSFsXoFai\nlWnFbldiXTkPzBByW64STapLmZt/db23NfGWmSAgnfeLy077nTB6S5VN3QJaubOw+sUFq8QDZWhq\nJlxIh/AxMOu9CnXuhl5COX2kO9MnYp2ibQXZjYB2Uz8GzbRh3KOr6O9O6W3eiJS0HmB8DwT3eBwt\niH4rzeVRFdnU9sZW7iCshmVvJV+XW7oEo5D+mVIWBfKFAxW2CN0E7mi2blglmwl/uUoXwiZWTQHN\nkhag0uDa1dx9iDbItFz0ff9B2+bFpQ8AkwoXj77KoRfnZlVXLC+351BetTTY9QZUbC9jM5kBy01H\nTMWQkj5fvhJ9zuXsRqN/ZPhdJDq6JQuiEcgl4fc7vL6BcDmgAMISZNEBSA8QIcAwmMU9Z0K6SvzL\nNAwuXYfobpCOxANwrbOXWCIRHi0LUYEAp0zpK3AeyOedeZ68F9Dx0fhcv7R5k4sHHwUeJ8QWMJl4\nuqJXzDcHIn54qJtSVy2yQ36u4QGuUmRMJ1QDFwxXSrRk4ewO5n6ndJrxupnl+yw9N8jpv0rFyy8x\nv6tNb1KSNcA65G38Uk+f9pXDFVAm9yVMVmNARfZzNrQybf4G+K193zlQGV+SrzXvvGpmOAfRhgox\nHa0Gj16eO+vvj9fYyRY0sOv+3uwbC1pn85cfGt8zdhHAShA/eICI6mnWYE+luL8oTUPFjbA6JuTg\nfWgf6iE/NXQSL2DBUMw5RF9/G3yfPOT8oYWbJZqL/s2pDbLW9hNGYXFQpXD1iH7/dJeQ1tdJipcu\nXGlb3slj/kcLiggxed89F/4aDEvVs0e6Ln27lb0ihd7NmvZrkbjT7vY8qISWtBVA7tNKlVV00HvZ\n0qvK87ftjk92FJK4fSekoReIxDjO50jci6dwOEqmYM16fIkvpBIllveCmSgWyYQxJoOrTBhPJJtf\nXfZ6PPmEUUvXU2cz8AnKfLRCcN/Cf29cKf549Q98BDW9jyemH6WdntrxM71+Hhjv4S5TtU0U0g0V\n0+t2NEX2ofWopXzTd7xXyQWW+2FlEeHbIg6Yi7LuQwhxTEUHKro+BW4SDMa8Zmib3qrPzVE1roWa\nMlCU552UI7bRNUR67/3lL2I9V5OF2EUctqNmUS1uRRUduiEN98Ni5WnO9pj7dC/aEx5fYbprxuUP\ntYj6TxMUAK4EpYp2EU81lidmWfGE+PSltOYjZqwp0eX2VQG8gtQ5XLQ5VDL5EmdTdG94MAZ3KWl4\n71qGiCGftP1gc02JOeebdCLPs9RB01Qamz/7qRrtLZqfjEm7vFGnZjrPbvouq6aLrTrkSoQ9Rku9\nBq7sCRWpZJHwIQW3joU6vIKWqovqZrmuMZEMt50iADknpPAcVttuorkxIhrY8EMGTVLaeiKc6+aC\nw90fEP2IluyabL4KCB9IP5YRud8Vem80dhNNefrYqAytpEjcQQMbkigJA71KxdxCMLHjPZhIqf9P\n1FOlQfDEyWStjz45PhUvBsWGfNfY4e7RP7t/msJ7F3wQoa9QKpj9K/iurRXNZN2eKT6Hj7SGkUn0\nACtUn9Zun7Ua1be3Kb+uXxXfvj7+T0Uz3jlSydytD55UnuDAYq+K2gAwynXtc6841qezeIxadr37\nLq8AbB4IT5X/oDEUDdtuxJhziiuLroU27SrBYnAx3ZoKLS6XfVF7wXS4LTlEOGi4AzkJlFgbtjDN\n0n2EsteXDHoJpKSx1AqY+vi7VY3JpoxH1RemFZ4Rbxr3Xmzsdx4BaO8hsfUOAXD/iq2b3VP/iWhB\n8XRPiTNtsAKVeSMyRv+E/9K5cMsB+gFtd1En27yHSX5qBO9M1g4ncHw+EIhgU0Tg1aEZlnpBXn1f\n8KAdY+kh8PwqGgcbkRdJC3bttZ/g9xR3roFPxpAZ+boxGrp2jE40Fcr3X4g44jgrA4IRgiUDIWTX\nqR8lxjalxvMOV3ATBs+7cP/BSaFzc7AbNgflKhebuvoh9OVDpfPv5+tJj/Ucv9iEIo7eCoyA4QTT\noY1enrvni6ko5gsAxgyanuHdkjnMV9qdVIMntJDRkt0cWEfdAEj8z4tYB/hGCMz103rrnFkX+aid\n3cFFPfSGptu7BMWqfuRmrduQ2xdKKgZPaj+yLnReK/vEbKIkBYZl8MlESCeAWwf1nzu1G6V7xSXU\nFruXmDy+vFG1QwwK2CMJKGUq1PintY4siRuRBhjdR8bY/v9Dppoqiq0GbWCnEnoeZ0lgvS53Avh+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GcA9Zn6JSJxTUCwYs8aQ3SIm8x3etRqToWjYKTAbZmvRezqKjuhJ1htlHyPt+p\ngxFYba0DOIa5737BxwzgTL+BM/X75cddRAx9O1zRk7WcZscO4nKsuVed5vzVpY5fUeeam4wpEreH\ndf5fZo+i2TN8VR099r6xe3IuXjepLpUDSqgz1s6fjumUU49h8B5VogWCzI/Sng4e2ySs3DuudcTN\neTbO7F7hocbaR4Ja+OHzwSKcERs2tKt3SKOZaqCzh1C4cN7icnZeSfmDXVkJyB9mTWl/6wSahflp\neg4bS3CxHvVHBxc1wTPp6ZwEbCNJZ1GeG3MurB9i3JbnUDzmOFhwg7eOaFurXoGiv45RB8vQKvjc\ngyyFG8V0I0UxUmA9cFlbilM6mXKs0c7bvXdGnxv2DQpmqWwHJafqZ9Ub7GIRP2nIw0yClX3C5UaC\nyf/tjtAnY/dw/5LntI5BBunmuEC6fBhZSntF7uXrDWv1s+C859IbUO234tYG7dJFDQHZH29sVYfg\nQYZDwlOgb8VuP8Lpo6c88I1UFVYFMgCF3P5SQ+v1m63bfe3bay4HUTISeVJUy8JV8sfADq2wubcG\nuWcfUD5AShQOLmrpWHHJ7kOetd/o40exAcRpY6ruMZpAbw/XTk3w+IZeYAjXvoV4HsxbneA/j/6v\nRCzoW5P3UuUoaB5PgGjjGV5hyDlRE22MnFsaD1Edp4Aaazf6x/abJR+gEuiOjIkZdFyslNkczRoD\nu7By43V/wCySOAnWyFDHOhN+Rk2yxZXouQu7q4FFldEH1iFrGHvxaAEezrQSskVgSBq5s+L59ioU\neO9CS8jae071lEKSz2D/g93/OL82GyJlZWj+PeSbqzhShQ+oX05Il2Hif0Nxbu2fUZVIMzIa9VDD\nf0JX96UWWVTDr3evRvYoh7RwhDS82OKImfwBmSzxFjawoemFpUn6yy4AdrgWom6pB82BOMrWyxCm\nr0baPyGumEcnivasXzu3Ghg7l4NtwjlcTuSrDJyiIIqWlD01qFIT/NSe8XGEUU3cnSBqQfMnb1rY\ni9O0ljhYVL8fURPadXIpnmspDZRBbO/9U5PDuTLIDUARR58h3mS92o8oG+2mYSEHMk9Yt23OoVZN\naP/TqOTjA3bB1PM7YulgzasFE+gl9SAFP7u9cTy07ik7Z6RqLfrweuEgZzZGPgnx+HDSN6clM4mE\nVHYMRJf5jlERFhrV8NNEHb+dJ1cy1o+50SKlrf2bfrsA1sMfqwFFA7WTEXfXopqTuOy2pS6YuTzn\nLtt8mp+m9VBSNQNLGSuPeVQKDL2c/GFdlc6tWG5msBw+rNDavwUIHfgdxQT3krhLdr0g/Xg3vX10\nmVcpqzA8cPWZU/PuRqdqDxxY+pCqDWMuX9X7UVKrPye75k4QcLary7mM+LoUhbsrfeeVgHdXbQQM\nzMhNtPA4SoBi7w0scbWfeGmkJixU8Sj4L6lA3ZvMrp/M8AR+++6EBCX9ttW8OQssFTRvoTnGA4Jn\n2kCJwehXlV5jwMSToYsyFFZIfrJxAUbo/+5sJXPMGPJIZRxRvhgucH3WnPrzojvDrhoDhR9WTn/D\nUIlyqa4FG7wIMST9OtD7LQ2xc2zji5zZN9DmxSdSMDQA/03HnR0gcY5xRBuJZ1lVW93DRflHAlIE\ndxPAtrUw4T1wgmfkkOnNCKxOsSAufvMYEchVBCXPVSTCIUgCl1WDz1FztJXRkZhd7VubxRZycQbb\n7F0xSiDk4EP7d4d1bLSz4fXRdkVa7inKtRAzuHfrKZes8NViU4Hb0i39UaHG/0rHCiWuEqEaemNZ\nta6O+8TeqDy5mRWmtS04oiQBIqj/a+YJjajeqKkJo5PwXbtHvSQh8grTm2jifLLDtyc7quNULvHe\ncOm9lfFtaaA9EHzxLtTm2U+5jwj6VdaXu/Ui+MVFI0xsQHgjT2wK5sk2yH071CVmBEItMF1tRgQd\nQIH/aNQjpXW0VHg7b+/8rumUFrN+pmkyUxhN2563muCP4KBJd0JQrKwU7s1O3br5fHuueVJAe9LR\nyXRESLNfzc+gr9SgamtzGojIrCBDOUdjjM6J49tE5jD0h77qR7N0SyxngO1MjZbfnYlh0TiZkDrO\nSn6LQCdtHe8jRfHGsS0T3MouZqBxtTrH1h/5Wg9xfQiQNzbjFdKkT5KfBmXj5IMkhLC+nYB2DwNu\nSJ3tFGNeOhrevRvFD3kUC7fsFE/ZwDgMmeDRMbfPY/Lb4XcSd2iIZBORBSlcLw+e83D2PnE6mkza\nnmnmKneUB+XbLJ5SGoG2x3n3eYD1iqpgIRRjPc9+6cuqbbkDWi4/eLtllVND026fbWEIF7PSYUK0\nwh1664zeBZIErMhQYj2uSBUZUWLIb2ys6q64oBSI5R7dLu3h3FuVojFnfAKueZRqbC9twker0itL\nIMphRzQ97vqXPOpQwskpiS+j4989IJOhDe4UTwtvUFVPhujGAfnowG3xIolbZ07V4VTbTzi61amj\n29GzddvermmeN/WW4di+c798HQaVMAPlLpjdy5BwGUk0SINd/oPNbjC3LeDtSSBdv9jld6nDeIjT\nNOVG8bBSqDP+0SDTjI0VlDlLKXh3KmZKpG+OA/z3ssNWrlyCFOgq6ZD/BUQCb3CLl7yKAVDswePh\nnK5UpUiGqm79YFthbWwOedumd7lJPMBxNYnJmAmZtSqcx38lGLipvw3ZMIEBliw4TlSRjPOodnCj\n5uztSEunBm5DjF2YJrzC/eZ7ea8lkj2HjtFZOrVG1eLYgh9Xi2PTJn3eCiZZBLMyEIGbpmrAHEEt\nDir1mN23gE9E3gGAm5AIQd0X/ZM5UBNPXpYcT4QMDGFeR8CC502+5jQ68swFIiwkynNbXW7v85kP\ngNi6PG3pHfS7G8j5+v0eyr4z87SXr+0wQ7+YrKvAjVHMKwTGds7JZSrwY/xbyS41jfuL4BK0XGi4\nGKhXRrAV6L4csIatF/43SQRMQAYQTLkSdDlWFrYmimVcttsF3Nb/V6BRPKOMZf/AIRfl2g25CdOh\n8t4wi8f2wZ/6vvyVQ3JjUs1GtUYeFEY2jWTfc1nfqrw6YJmSZExzhFIq5LVEZ9hcIQ/mWBgf4VfF\nldlM3cF86EoYz2hdMw/bPSu8pHqYAOWsZvsPVeLvR5bf+ugQYrAbCzBTFgM4SHoJsfINe6+0nnZW\nfkR1pXXII24Nn1y/HuBasCbvkzcHQwFyLWOi1PcOxspjoOrteHd+nv1PwUwED5QpalSFP5gx0j/F\nP6OQXBmrcu8HNETcC5BNbjUUgxVH8NmEx0vYKQka2u9RIWNOY86IY1UCKu4wT5U1nRyTpAy96rY1\nCUY2eeSu15cl3mFEsc9cR2SaZp7oGFiGkOeASbDfact9JWvN8TRyKi8cuY8jnRLtMh8w6wkHUW+F\noAxhkhQG48kdBvp3WBM4eJC/FhAoYDpTS3VrpOPFn7cHPRte76xha7ph35Pmy2bw6sY+BQ99Yk6h\n9vmke0+Iyb0+XXIHT2rKEiFSiu8dRJ6l+AqhZidZgZkJhwWP6y3ecQwmJVAhV+qEd0wPaFwMQoVI\nrzJC7r4gIi5KpEF26KGVAz/C0/Cj9x5E11XzeRsFpyYKNmgKzN2jhUC5+yg2/QIQ5A8h7Kg4dieQ\ntCofAS5iA+FaHtsY/jn5rX+UwExiVSxZRm7UjJbNW83QQwfFcfsW8O/bvA5lU1tk58Ii8KbxIvek\naLGlNnWFN8WThhNIHLSDeHRq2zxLQ8tG40cLPkNsyz+rMRzi/zjKmRbDejskopG5i/lb499GmbXr\n2C4NU1qBCMI4HfUZ5Mr9joo7/9FzpKG/HWLSct91DJ1rOP/RoZv4rbb9zKm+zlwL76OYPF9yA5Ma\nZe0asLuYZRnc/l/2AeEAdQVhjZCwsrClN22r88vb16gNFKtjTExjrzsDtDjZ38VXUOkOveq4mhYn\n4vnLjumrZBCz7y+6ZCszoIOjULEXOLchdJYytt2ysJfcaHDBPBxcJn+WKQ7xUvPyzh5WgRMUdsim\nDuVT+D7JaCvgAT2j1VfqyHMGXgfq5ph5OLNiOevTUYgC1V5HA70U8xcLfS4RYJI6WJCHWC9Wbngz\nzNLDlUD69JGv7uThe26LzvY/ivOrbkXghyYbkN4VT4GLqOsWMCYEtyAxmvgWAqIhNSPw0NSJjE5x\nxO2zQm1FoNF5mu+nCWJdUPtx70u0a8e5jdN9GFlj0EYq8DNB1X0nZZoBnNM/W7TUMATH/6CXWzd0\n498UFlvIFo2HQrBaKisdbEQ1Qb007Rp6TCnkkwgEHAcKg6AJiU/DZLXeYF60Biwb6N4KrGT3PWbt\nf0Kmi1vBxjXBTZbQXGjHwCQ5D6b5cYFeRxyCBrMFOUv8qbAKJEjRmrVW2MuIwIBgNbqnWIRstX03\nI5zhAC0x0EWpvNz4BOglCPcHaYYzo76rjSDZh4aQlyQmEiCxXT06Jv2NYSW0tU39elbVs4GHgI4T\nym3nR1zd9r7mOP4orAjs574aT/9ikdzavVr1NoMgeyyPCkPAIT7IxIce9jz6PdNk6zDEySO/wwdI\nCOV0YVAH8zQKQZLiL4bx5xvT3KZbcAHR1SsaJeuBZ8Lga1pt/5pLF36+kIJ9mqMHR18nWmcyeBNL\ncJEQH1ntn5eN1jpnbbQWsPwozLdy48vcXxr7N+qr9eUL8XPBcUpq43UZWMr+XUhhbgimqWxbY/NV\nfuSLs0MZQYkqzSennveOAr5UkIRGGlsWXubl8MxTBCT+GUtanJRS9duOH1yU+l8Lh8/orNoh7Nrv\nc1FaI7GMH9dMRFNACBQILarMsF7GoiZaxVxfCgQZMv2meRqmfLlgJ8HupWxkyoCgnlZLndHInG9y\n7Hs7zUmIhAGYuwtq9HnuBcKJzUP6hi82F7qk88GLhmoWaGDy+9WlFirxxJj9q5kYRwok79jIwzx/\no0ZQQUUtE1ZYANeGBMwhPqW86Ltz+DOq0vA/z8rOS2GDPEfNq/zALAuz9Wgmfp2XmtwiMCk9wXRA\nn0NajGKBfnpxQhGvH6Kt6j6GX4ZePX92brl37hhv+v3goAezP8T05xCAO3ENq58hojoRpLskhm2q\neGZIZA7RMgLk1EOC4eXqf4gyTW/XzzZphuSs3NBT4PvNCbJweAzuRW2koJNRXexyhIMu/uOSuyNB\ndtKF3ndxgqvrzqFVmxk0eyVDB1YxZW9xE2fGTDOgCvXURap9QR8KZM4J9nrn1Ogzt7jBEfj704HZ\nVL8HU2WnafB+1NDxgugtg31MWoZs7+giC5VUC5hoa7dc9vsbU9FNT5fR5ozf3v3797tYGsmcH2Fg\nBi2aS/mM6JqJ4rSaK6oFh+5Wnqc9pEtpsucK/lxY7dtCcWQ0t8pHncn7E1jhJyb8SqUXGzUXbo1B\nCyT8jRoNNy23C2KPdfcFdjUmnbnp7AUtpwN62qySlv3Xz0U5EXU97y8tdFxE0cnjt153zSfb3OMS\nrDlVGh/Qwsi9CyoBK5YapXAeceF8PZ9xlL1yT8la2l+ZO8oZsBW/PIV7k8XBWXeWzjtyWjjkXogp\nC2Lm+SenlvnxblFP5MjHdLkLIhRChOx8UFJcwPVGKWVLLVGpIdZ8VNsih0z4E+8g28p1tUC4wMRa\nhTAxtupzWMdOflDIVg9KeDAMPXp9zX7ZJHykJWRxR6q+3Y9PVIaJ53118LYjbT5kA6t3dHjfr4ga\n6sqPWD3DDpfagbv0tUyujVlnxaXTUCPu3tzOIEoPC9sIuCYESsSkquOFkoWAnE+2GEkSzPxgGDM7\nvLjNRbflPpBjjD7xsDSf/E7LDMCtiopSM521w2KOc+kCS9QcRDIGhLkYCFnxICp2SqEvoFAjSe9o\nTYG41/kG1FuDm+R+VFxytSo6hKqkhqIt8dtb0dDsY30Mlci13Rcd+MS05Bkihxs+hx/MHusmBKOm\nMcXWSABJJeJzN1ID+bRm565QsBExStKd1TmzjAsdljAUPv24FISbs5iz1ruSFpaRugTX0vIHGAWb\nvG87IsgEaDzpNSnFPVlWWb3Ae1kcMx2LlRb7534qDRmszfq8fgmYIwZQrsLjY2WjdhrsiHAMwmVh\nj289MTKDn9SH2Aq8pcgbc797NRoZvcxtJ0hD0yHoPpWJI+YmG128Pp/E0A/GLhZCfd9dPwhXprJK\n60DQduAqe0JXJZUhh4ziuj+sYnoQjandEFhZGa0cLdl3CZ+Tgs9w3FiHQ9o+KK67QgGrOT/N71tk\nr5TsA7eIZWGwk01L8o9+qmH2JnRrG+zQEEzjEK1FAz664FHDeqTSGHOpHHw4lR5PELHyFxVBRkqN\neIzgX9sV68iuU8n0DfDKic996LdsiexJexW9WLfH3DXMO8cwO5Abb6S1T5kFK4Sksh0sDSt3Escf\nArHXyYGyjOtQJXSZW38Ldjmje3CpMA/HYzl5aXruIhqnzy0L9tnGrNHIPThnvpk1CVEQA+1eMusG\nMZIyNx1nyaZ+GHA+pkdcdP90dDpHKZwqsPZVHf3kKHY0u1jqeTGchDgTlz8mFXE0HTq3HbzfKnMG\nY4zbW2OP4nzYZWPS0pgl2IcLCrPAA85AAWVMa6Ceg7mYLxdrMm0Ln/tOgzauSvkKI/ViZs1ahKOr\n2WeG7lAVi52tQpol+rSeDks6zGvoP+ePTUgYap9zCWUfTadF9/i3UdFf69hTsDZmD0YQrT/fC0mx\nhKHChOT2KdWe5TIrnbOpJ+I84InHqS1QLscyRhBYy5vOsM+XA5bxcpDSjulcZsRMdY++KfgzvGiJ\najuh9zs3L3sLdv9tCsf+elYA+GbduF7WdmxEGpEa7iKfjeJY4zU4oazPjTzVIdR6JqOFhIhziKmO\nsjU2IhcGEuVu0ogfcgl05hvDseGWlLz5oVJU6yXQSmyr7O6l1MRqaqPyKLBIMLYpXcqhMq0/R/ab\ninKhZtKEP7YnWJMq1CH91hQFThZ4vwmO9zVI9fxlfHMUoKxTIwsTHDXoyw0FdD2hfdXNZxhe/f72\n4Wkgp2qTz90wVlz1lYM+jJvggFVY+7WEQaCoHUu05e+ljIcie5sErvk0ueTOFywdM7iGowcO7d7e\nuhLyo+BAtsxpcGkBGtqomxgkZlyY7RePmNKMBesg6ouC4tmKlrOycTjVGljWsaY4mPLSKGFs13Ra\nGSwSEX53xGzieC4mFPwvJxIcirobSwW4pdubhvbdMEosfL6boa8QnLBz/2mETCSFBiJbu+Nb46H6\niGuD2cLAIuwbx8am8NAyM698phBwoPVElhRwpmZeeVpwbWfVWoMWq2v7t1oHEBH/VMcZ6PpzTcc7\ncp/vmAcidEHGZDVDjL+fl/tIQXVdSMRpJJlPqb1wALZTuVkD97DejftYg+7qTx0/nIjJtDAUI54d\nyMgtysL/yZlNf4EHhXvLz1XncBT5XlN1DiUVSNYQZGCUhU8UzCVbMCS49jY6IBUDzOVJnAOuPF6/\nHMf2nZcr5x5WnkZyCN/cm6ZZIkgwOgZd5I20Tk8LL0w1+tVygB6/J77LT1Th22rHnaGEDZEbKKIi\nEEMBRJ2zsprpglgMScv3wLsEiREmKu8lKuIYiP+IeHEJJgQy36vrSzm4Q3dLPSDLjqR8/ZOKCn3d\npgDbg5/XGvIVsThfR0tXjQuUKdw81GrqUM0MuYXkRjtzLsy6rMbTxOhCGtoIvWbkZ3ssP3xj2RMg\nzfUoGSj0PZNY6l9lCwpnuIJ7cWGYs90MGL8HLMAfCPGIPUtm6GGY7nfeHS4KIjKA4RVAXWqx+SiW\nZxSdxmiYIP/Hvl51ndadC7pc60ttuS06NeYHXDOO0S3vRQ1rMaA1jakkTxF47o+Jzcza7CiNSktj\nEXb3DfuBJlztT3vvicAdnTOu20Gk9HYImFU+V1l/7aGLrH4/rSSwmdoczLdNzpbPA2hNeLWpRTPd\nnt4lF7BZRk3h4ZwjdtQp4S0xFB3VdV9jJvtgJicwK1dzB0H3zAbJTvRTzN46JGxdDXOLV9Plgmhc\n3lK7uzj1V8wDQnncaKGeiLzwyK94e45MybepGzrp3DoeHM8I4HgjPTcRt7qL0nPWX1LvcGwaMdJy\nk3Z7nH2hrilPTCD0VbiNxfG6Du0uTixzYusHNlfx8ghsn0AHQec+Qe4dYvyN/8+uAb9ZIGOJPbAa\nwK9XZk7oblrvouXXXFBfbzsjWrOWnX+GL7ohONrsy8kJjey1WHiulVvVwSLudcs4F3gwYa1QN2JZ\n8bRw60FZz56Ne6LkeKXCfZOh0FOiTm0cRwrzrWUMTrM7CIT/YXJuJsqr/0mw2ZZ7NBFqXHLsxihZ\neFB61egffeahE+lhoLQpiZs1e33waVVLxDfY/evj3FocdMGNoQMQK/nWPz2KxxQXBtQHVZOjNrdh\nsx7U/Wnia3HajdqoupouLpo60fgJXgzGUlw8Nw8xfqgoJVF9jI7VDkdebQRUTW8U7XSVXMXF1wF9\ncPiYqw99dhUqF/Dqn38W7ivfQ+4pRrdLESpuSJ3k1DQGXMaSrmVUTgdaC40qBl3HLDKLCCHFiyw5\nHaHsZvKQ4IwKZ9p8uvWQiNYgzB/dywmnnWdg01VvpSWfMPsaIXN+TZOjB3x7At3FLyCvqU0KDBcP\nNSLmiavag9CucAQ5X0a4CbO4zq2rHFvb84VRgV7X/igswCO86CPlH+OTjiXC+98PSbQyv3Yt7yjN\nwu0vs76r90T1nhqxFoi+c82OdInCNUEyQIyMJJH1ub9t6qBHzXXy1lf2qd+S+lqoceDEDqwwc46v\neT7zK9dsLyQ8OVg6qprjyOXF+KPyYj8pvCgXrWzL46iuWuIGmQGhIjY5ctoN0taZPkzYnBpexaSK\nplkhhI675tI07CXRNHAYJ9V4WU04ItWkJcraQMbPh9pQd9jVjpeb156ehydxPUL5aUTpP4UWbDiQ\n6v3XwS04kaMW4C1S73RsASKsDIGwDxpUWkE/Fx/xjGazT2O9XC2tF/HfFu09QnBwAEv3xgxCsSgG\nhVYJmi+uSU7Pi0yk1UAx9CIBJZfvXCOBSSeqfbZQznoPl6VUDETyAtFWk++1ikObWg/mxDHhHMMs\nxxa/A/VfI6lDgdQWlRsDVfzhDYEuoBMA0A4FWpgfr9hkcsI6UjGOSyN8vGGPWfSf1kjG+4Hzkofl\n620EcndQrjZ/dZvi8FeOcveao7y3JpYdSlF2FJQpUfvrBcdHMu5PHvrjgysK9rHHuKLSrkLBU8/s\nARpzA/e6gYZoH0HpWEYwD48tt16u8tRvblN/h5H7g1tmLXRp6u77LuzB8AsUtEPspLTA7AjTXJ6g\n5T/wROxlhGKoJZC9/+si0e86GYGpR+iim1BlYnv02qIx6mX482NtCSam6G+6VbYpVdyX3t2Lm0qC\nOSdh+hlPvlsHAciO3AbGMXHS2MJMV7JVX9IQvBu7D++EeTrzHGEBigjDN2R/GdKaq7QBpwQrhv9Y\nQB1SI+U6pyEG7T5xpAw/BOsMczH5JwLlaSrljxEgzk6CkjR5t1JlKntP1W2tc/QOTiNJdAfLDJ36\nJcEywJ4KCMoDcSrl8NTApf71iPxqy38aNuehOuG8CAcC7twSHMW+1PdIlTOX/JGw5ydU0MlRxFFM\nw5PBJ2kA+0TPwLjn//9Wc/Z6jMvVS8yJ1hSLH4w7pJFT5ZhBUQXfcZMRp171i3T3Aw08GkfoUZzr\nyIQ6aItW860T2VbybbseJ+5ksBUs++IuROqDkR7JXmMXdZYpF6dcioHHU7F3r8/PSCZehCbLX8eL\nzeS2cyP103uUmRO+7BIJydB88XMvw8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5BPlgv0Ysd+eSR+SctxdgsIGfUYDU11OM0zbr/\nWzLoM1Oq+kbqKRimCRPQavzTq28qw2vNV76NgLf+Mi4voQMXDED873/xvIVY9TQsjopYhTTJgQ7T\nDYAvw4caDJO2T69XIDBCS5MwBLxZp7dspfoN/4oGjaDljcUVf52RQHBD0be6K7+UgXh3e722sNlr\nGIWdCtUs2ieNFcswyUkhb+J/TQcA3Q/BQjg525rpirxX/935A7IqWEBSrSJUyQ6bR/6RI178+VoP\nb+nZ31dSV5cLusb3bgBEdqMgFpIZQ04+C2h3rT66h+w8lgB1i8lDhFJYj6Z914taI7u7XrL9hdWk\nnS+oZs+XLf2TEHM6XhtWY0UfGTB4gk81QcHMPBR7FSj3PPjs6NfrpN8PnEta5+m7Bw8yWJ8hEufG\n6GNBPRuCN+ST78w728pgI2Aj77qgmO4bfF2EIh3e6jnqiqqKZvpottUU+wOnw0FfbAyzdkZHKegD\ntYerAldliSEsyacASt5YCPbQ2tBOlTdWlpRKGK5jhAdSN6XMihXy+VfCBF+iu55vsDQpKODwBf/l\nB8ttqqB8/6nZfoXzhq/Pgq6dwlP2EvSsHywtVGlAv/1vlQl1lWqIB0YX39bQW0bL61gJtp7dIyJN\nGXTGXiLo5VjnKbEblEGRVajzzcIM29VWYOsxCrtzGGusMJRb1cdgRqy49yWsGih068zm2wuMn/fg\noAhj5GcjxA7ozuv/6so6Csemv4QKW0vWEsu5LBWrPlIP4vocr3NsGTixATur/amAbbTeFCIGYoaS\nSjoM44N3wDyqsx/UFjyLFnf9A99T+by/+5RHIeoNkEG8Ghax53GNSvtO42NXxbhJJmixJNswdKVg\nrefi1rMLQQIDBFMeXpZctKcGDYHnTa6qWsI2Xxz8s44DR6MMt1MsroC9xPrPDUdujxc4s4h6R6Tx\nb4avq0fk/TlXz4ay7Wcgeldi8emJ5XtM/1MLpbTI5e+rGvBBJZn2f3R4FN1XVaK1leID3H8+MPhr\n72Xl7ZxK1k34nugWgEF7KkgInRkOy08AUeTUF8rIEIXHpXm6PzsCJIgJgNh9PrfxDGoh9XFHzHPo\n95su+nlqpTVGpiCjjD6GZ+YE1OZPhae8S3cdoeM4FgcVXsF1NP7PIy5DJ/R9pQ27TJvx5PdeDcrq\n5P4jynMDt/WXG5SmHtNJV+WD0q1vQMIkdeSX5wzCHcBDiWVqjER96rpl2Qwbdpo/W367GH8KPvUf\nAitgUV8GOu8TN4BBXonsdv684d89itGwwRGrKuVoUZtt+y/SwlhSTwA72MH4a9QWBe/jZpuc5eW0\np5DSHEiITaA/lyEk08vTfYQe0gsbQTg2dvpUbshMmvAWeWd6RoxDkEVNp20ryoGQJ9utSaixLGtR\nyKaaO8q4EwLtIjey5YKY0a/3Qn7OLrNo1W8xkOTYeRhC5E+kCtLKeve2NtgVQaSMiYr6SuYyk4HA\nTVxnfpuozhoMblkqkkj+JtQkbwJuxCBzRB8cLs2Xxd+Aul/LIjAAr183pTtklyhzIwnfiMNLW444\nc0/9McUB7gL+/gks92ElnH8khm4fpLUp/DwCEFKDend6hDZ7X3Cp5Wo4svtWu/v3fw1kgz6M9bUW\nJ9A61uWMsoS2wRbMsgifchp/N9DMHA9++hvfdpxBqXGOIw0VmqNAmPKrG0X4JEIU/6SKZRNNOG5E\nY2uVsHIfAYgw/4n8mv2fF7gvKyUSoHTbURYbZcKmmVv4q64b2x9J8+IZx6XZmLLBU+XJ5NxJsW6A\nTg6MU88JjupiEyYLylToCFKqyik7AWoTVJC/p2Xrt0MiHG5QRpKPsfMkhjb7gBS2PrvNBP00ee6P\nVSElr/CEpazyvPPZIuF6u6ze/u8Zhj1w0aneXH+14KnaFc1B1k2gl84kK+7MadGPCJxFy0HNW2zL\nsCOV74lcGAUuSqkLylCXZiiGtsicrnSiyTRstEasEvEkx+V+kbd8R/wO9Y0EQ5a6o3IFIwJzO0sB\n6KJeYHUhNr65982JC6t9Hoxt6agDzUeijvPjWMRhTu2CK0iKcmGyXsVdYQgI1YfBnQIOTXJZzY0O\neNTS8hH5fIPuWrBg6F9lwL5FPZd9APt5Wkv5fo+RC47fWbhQBmxpdUXF6HLjzGuq8GBLkcfkzGC9\n/ArWqnKORSiu8GUHX6crwulCXqSvYjc9Hypjw7TPuTVvnZKSiPHGRAaREIspT1dEiZHFaDF0Z1mg\ndn2tK03yOJ169Ud0SUyzXsOmi+JRIMM35oolbfoV+uW7YomtxUzbnIzt963yB2eN/GuMQQYpXXxK\ni7tsbvfSJNE3WE6xrJIq6MV30YgsQdPl/2DyCy1oAu2HIdIBAHwXptE5U3SFKDIr0aP24ePPJFXZ\nrY5YWECy6t+ORaljfEW/OAWSt6EKEx9LBJSAHyZRXz2oMrV9qUImx4xa8doClkt/i4zWMwbCsT3X\nDLxxvqAK32Nc+7kxkOtjbAYSVU3E2fMUSQV8s9CrmI/UELunLGXFd6HE6q1HgjODgnM/ZQ1vJcMc\neYpleSccQNtFsdHo796N82J74xCsK7uXVn7Q+0I3tJ2WDwPZvuZizHh39LkRwQQmdVDc/J4OSoky\nDsVgjI0p+2PatJf8L9EPyFtQmQ0JApa5FD/MKz1u9czJavCX8cEDPvGAGAczTWw2uWYgANc5p4UF\nl2p584ecb9ssVvKqGcKk/YaN1QQ/43AG8ut8UtlQxmxQXpjZqNrY06Vr1tuRj6mEjzJ2ijDFBdCS\naSlPbp1cld9hYjIdXm+u36IheCLV4JAjyQlfENRN5ctVJQ65A34472DzYIEMWaOevpdz8LpwMDrb\nomcM9KS+IZcT2FP+FpPQGXx2tGz9IySsDsNw9FmyJjyPSCVhpX91n06Bm/TcIbWasCWgo8LCvra7\nV8A8lh1qYPYC0T6+PFPJbTz/SA/59IjS0EpwAz2Nh08OLhek4atEM2Q1fVVNml9qj3ecByeuj4vM\n2LIxdpGoWAiusFpbmhQKOwqw3GAtXMQj4isIg0+uLjC8TCGBK06j3P+QQH4sSzR+yRzn2vthMXfp\nHGb6shHBzxIUcUgEvXPlfRUKvuVCRqjv8YE1eQQ52QGrqgudZiRiaPKFJW75ddXYlOlBr5ZVMSNY\nBWGoulXjstXKWx+SJs7Bzm8Zm8MKSf44HLYgw6h5r1v8JFtiw2tMxNvce68O5qF5+arcIB/4Tm5X\nCNPdJv2DyMnAr0TnFgqM/vhYPt5dPqDtSajak7mXYNjaBRdhDkenWytBOccR8UOfInk06KmRCdYn\n/DU3FiBgJ+AKdlDf41m248j/KcteFR07COdXIkvQohKy8egbvc4sTpjgIaaETRQ7/l8WtgtIi0BL\nd0EVC1t3zDqWlEZYBBZsuXzC4ma7BvqOOTSe0qKePROklF6IUVpmiQWQkH5aTETOJ9XJgJKKFbJa\ncmUpaDWhISKweR5Xv9EZmeowJxVP90+N4JBDhfZZbdtK5hhYYeAb5qYznhkPD6kgi7mZJR+kxCOx\n4nQCYaSxKwdMdyNciGoev/CclCZ3k/Cb4NSfadqiJAkCSfCUnbRFG/vUC/wICZJki+/C8JunjzQk\nJ90d+klizyWMuzr+5bYf+vIHjCGHOxHArWLAWPkRf5WH3vlGZgTnVL3f/fMk832dHFj6UnGUj0wx\nGxP5gWFpwUro6Men/V8AYtf1y7nW64E7F7fOJBOWJ/DlPBSYJS3RCBnA5LaskopBso435CmmPC1P\ny+Tjs0FpULQ69Bf47RHXv+V9AXgTK12IdFwqZCX6euUungXT3WuvAIGzkz97OWRGaGqetAh1ecn6\n4yaKh3rC82y+tgJYpWt6mLdj9raleyQBJ1uFwdWVUnsf/+dfEC2sOn1IWMliGEpBZWCKlOEk3QQb\ncZMwetiYbzXTOBKfN9RZTF7aj9LkbqS/H3c+qQAYbplKQeCg3XHop49pc2+fwYD49dkguyPfUHZl\nFgbzOZeQW/j8lIvrs75f1kG2RXfrSipSYqvqGp8SjPDvHL3wd/NZ2mG0LHaIG0mg/ciih9+qn7Hw\nEXPYWhJFOswmiLgdoUyiK4YBKlVLhb6m9I2hU2K9HfpcK3JyHMzJbn2I5SJWQAE9+b0DjyUKAj6j\nMfHC+a52JEKkvAne05p02nnaGk/1MXvd5CCXk9OXdUma2uvP4SW0e0lOUtY1DfpF3AKGUjyRI87U\nRlguRxedaDyIv/Er+OyN11YZwEfvDi4MqE1o816W0+OeL8tPBCzytBVnWuhkc9wnijE18uqCfSb8\n8odutiu9uDFz8d+JXSjV7LSOu5QjouGbsmIfe+WEt+7vPkB2ULnV/sA3W37eHvat9uf/6lrXbEMB\nscgvH9gj7gfnVY66tGVIvLl2ICHvsPIYwO08FGz7lcER3h8no0g8nelO2qKdHYFkKmy+NhSzGziS\n3dAISETXF4/ezAjVj9/S1GdQwyuIqwttvsZ762j+iVf0dbRWt1NVCi3xGOH2vR7Jk8FnjbY6Di7S\nVQa2Jf/A74o4lpaemRlYMfwpkIApjX8D3se1h4buv3OnK1gOZjauVk5A2Yng5eq96IAK0ndd47PS\nXmvIy6nR5I1RRn1nIfdDkTr3Lng/f9q8etL17YXrxtM3l+lRFl+GNfYKjTcjAi+B+2JxcAtZfDxm\nW2lmBY0AWPm90geNxjKI/KGTVLHszKI/e5HOEUeXYQKcif0hMNpubhQvtSPhsCZESv1UmtIzfbq1\n9k58zlNq6rXzF8DP87ksk/vrtgHLm/4VTfbgjXg/xX/A0rePI2O1TUUZchLtgrkaYjiYR3AFi5Zc\nACktDnPXn3jFYyiRZaduSkoob/bZ/aLaWKGOvsPUi8wRYw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protect end_protected\n", "num_lines": 1194}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nSS96R7wwFQ/awBJYajmb1uyxVW7Dxe+Arw4icTEGgmn49jUuwRsWmvS+gH97qfjXRux0tm4UqqDx\ntyk4/LtkUg==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nA+Z7s4sYG1dC1S/OLd5onaqChDDoqDKxIH0wDyu0FbLuPuh2W2mXAUgA6ygUDyPxGR1xLs3AnLf5\n3U/y+fEPvjbByjgXYRdoaB1qwaS5zdnv6ZIRFF0LC1q8dbQM70j2RSMZ6Bs31wvj0c4OYXETbX2h\nDtNML4rTAuRM+iAVpLk=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\np880H0PUjXmUBTEI3c/dRMxRl/IL+XvlWrRVCBPlh6HVE/9bghIS/wvhgyOQ1mp4fyEUGZHgNQPX\n25j3cqsyfDCSGvVGO/rQ3RvIhdjhXBbmfxZXGx5UxofTc+/fp7JQTUPxhKk+Zmp3B6J8UpkkRaQ+\nTlbH9Glza9Jhze+cKRbGwVPrfS4Rk6pzkwHnm+iB+WGLJnSJVBVgXGfhp+ygbrBv+U3zrTXgsOb3\nxSJhSd/AWJ+PCYXQ27sJJr74LZYIQx/gg5QzMyTEoCqxw75cGP3bD2xXz+cFe0EdDkJH8sFvd1LG\n7SPcDQ9xmFnq3WPw2Ghv6DnJe4/yMXGiVRDxCw==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nej7XPZ5hWPkq70QwibQmqqDg1SWNzBrsMbYSFestfs+BR9J7xzmVMkCeifHuWqh/wSvpJXMW8pOX\n6HsD+kakwLfs8E+v/+QJqlLtBdlE3y4Pqmiw2GNPbakNzU8DMNQXOTe2AmJmoqO1VEHW3S//PRDJ\nqs4qvgIM1HXRfRRIgECiAHz7eGE358gw007G2YwbitOL3cveSqDocjOGV3jV5HepWYKXINH11Reh\nBMkGynjTuYTMJY/92mdl1ZV87kDCsW8+FHqKhOA1FfPvj1RPIfsKuqgUkZvW2pAYk5eBuA+vJEkN\nxVCniFgVwsrAdlKrWnw46FoutQ+m90CDu8Kygg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nLMe3TxzR1Zx/ByHI5/w6/SqhTVkyqBbjVaIILoDGOy4Y/RehV35vNFgESx+MOdmetaV1j08wlqer\nDz3Rfr2Gfq6hgHMLEHPCaIF/5SymT5AVpwhkmFaQdge1sI373fv8K78kRC8JGM9DNSFOClhGJDQC\nXB+yastK7IXkt+VYwM7nXa0xSHywkBIAeivPY/BwBX8XfbLzv9zV6rh2SAW84YIp2jb4kcYm1Mqj\nYgWPATpqkdqbBqii+7aziLQkRP/MSmF7cT5UKQiHxn/Ns1lKMenELV8RgHq6jdkdBs1uaoi1JQKQ\nfqmUv9kYnWWDKWW+rc0V9APlL62HYOLDnbo4+Q==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nq6xSi+pTFm18WzGq+65YbFhiK1j9sHarfxu6mSyjDniOO2/jW7gfvXXrv+B56wzSE9P0346jIlVL\n/B4h/Z+ac0SVqu+wV8pg+OJDyBvWhtnNYZI/7k1BSUWzzR6flVJw+lEcue42YZ9yoX/3JUlz26Zq\nBi2/4jMu3LmppUWsrAo=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nOQtIJXostrr6X7QDA+MBULvA7CIKk70kDF2hMqsQ2sI/8QR9LMuap/TXdjn0XLAZTkxLKNLqD11T\nxAlasu0+U1hOXgMBxoOPU/EUG1bM7wR1UF83Qhigm2Qm0c5xtp78LF89EgU/YOJtHjCcMSpExbax\nGFg3QnSgmE/7yqaeLbA8DKDWxW05qT8jxOwcDuZ3zIdkL3n1NxrWQjM3U5py6K5PTmC+vcoEptq+\n7ZI2ka+SP+NX5R9IadM4lpUB6CqAxroG6xIUBcSx5r2BQ2CrzH4EcZiQVNCUwYx8tyBREplKIsC0\no21e6uMpC5pDqqckCzSWGZns3l40rTQV8PP6hQ==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25328)\n`pragma protect data_block\nomU0F4cB12yO2ZdV+t8D/whbbDWmycZw/StDHYdtlxBQqHD2Rt979k5WQq+7+dcCL3+IPJmrHRVW\nGmVBB+3psg2CMKD8dWV8+f1duqdQ1ruc9IDTn3kyrMv8WzUZr2BsXVR7LoT/8ARttZYBzN9SlXOB\nIu5fROLcXGXIC69mZclXZ3kqw6gKbDdcIPTYaARyazI1N1JT6MpiPeX0B2e9dgibZS4NLoFf1C+8\n4lKKRF3P6Ms14sMsxNaM1rVifA4iQ/Ak5XeKnn27tB72RmlJm4ojRMRkD7cqreK6a2V7DXB0zAWw\nD7/HzKVzqh1lZF/69Z53r8BDyCI3oRPiIo9/2kpnZMcnV87uI6FNq1UsblfLwnFVkv2E1TroogPQ\noUVZd48nZKP6G3hipN1IkHU5wYHpG7S1px7d8HSx5vZKl3pFpv28aN5BxEuhvJV9FBghlpwG57HM\nQYhtJs3QjvuUXcTQo6mt6uaJkEmGMltqmMlwvreBEPDAzXivRCwBt4lZjduB8i1eYRSuMv0nI/Qx\noswjFa0lFt6divro4C8AxVAJIiIIEzOrht0zHz9Ss0+qCELQPEGk5lc3IDAHgjbCPWmObsbEidaS\nx7t0E/Jz7yoYsInuJGfETjIEklMYJJhVHJH1GgtFiwCDIXtjIG7Sv93vg8+dTBX2fVHjOswe3xhc\nlJcoB8yU+RvIb4FuwVwKcNAPT/0Py8wp2Pis/gDA1dsSpGioBjVoz90+AOI7ltbVQYEYqMCTLtJ8\nFmzXBx2tt+iWxg+co9z8phmO8gLRzjKzWoLbGSZBBw7G+/VWR6G6lGo4ZvKAtDdFvu3H0Lk06rJW\nTeOr2wSeT/Kd+gQCC8o2Cf/8PyI3xP+tzcDP+L/jkEdaFrHo2Z7v+LzFwcprHqiZldZmlCwK78ks\nVjmAujF9tHZe3H3Y+tr78xko8hSvvPzSklNvrskK6bA6f7i7LNvPXEu3FV0hY4/9kDRar+ls9hff\nDSRygqt1uAtTYP/7REZfujc+wsurY+MbzHHxp6jq3EOwSgRyL2cHXx4Vmo62A7wgKyTWk5EdPIPd\nr6n847VMqI15sXBo8nYyLWEkzrNVtVQEvWpeA5oqeDEHaduoNXyXlyRSwDv0duY7A3m1BAFlglvR\n0N2sjqwWzKhYFj5Ns5HQQBtHh9Zw21QqT1laFBjSz7cAsrFrpDoB8SDQCefHnKEzSHYnfb3WRQQs\nxCjXR4TlJRnLnZMyHVfyYtH7USi2/l9V/Yrd/PO4+NmUgdIxGbToTlQIBx5gigJGs0XoaWvVskwf\nNXlK3UaoOJ85tDPYp9Ejz86GyMYerWLlf1u9Hn1BCIDeuOMqiHVvTkLMoY2uQf/g9NOChlcWM+hW\n5AZH9uc91mLwBKTrHi1k4EM6CVoDhS5i88eLGDj7WUosHcAYcjaiNhkZ97tZbVK3yKkVFEtdjoL7\nh4Bum8rQwYxHNx2gWytbEbl8qIT1k0uisTMGRDOmApn7rixESdulVbMR9qGrvrPLqY8EtDH7jJY1\nlS+kchhLcPKLemI+liKF7h5VSUNsc+PGwK4Poi/2EFa7XfIpHc8E6l0gZt+qwW+qsA4aH16FPrxe\nsPlGeRTRqQDdA2OwzUgpbcvKx2JTx5qswVjgMW5mHt2EnLjW6SHvLc/Vzy7fr/O3kiV3uy4dyWGO\noloO64jspiFBJnLbb6eaTNqyAvbpj+ZF/Bw+QrCdIb0EdsWj9GmUUmsmiWLI+Lz81KUCzEc4H+Hh\nGglDloivAeynD9N8HFp8OpgQFagNeWtfAonUqCDV3B+hsNXo+x3Nj49PDKdY5aesqlaahKr1fAHT\nfierHFNbvOT41MYGioKDQPLwon8ptmydyahnP5MmlDi3knIlULZ8de+mnbKISNCyvzua9eAc994K\n6B4Kj8/swf/hAOZxTJ+HqtpK/DgmCA9FiU3JYIsSB3rhufuLP+mFayZ1tK7d2t3i+FZt7TbMxR3w\nuZgEVxQBf6VU4vQ+r6EHuytjSggM/20/7CtQ6JVqeRD65+i4n1E7b/yeCapiKyLEHcF5+TolHg4N\n2IN8M3DjZGThrN/W4aFXsyj4YqaVr87z3w3GM8FGp7rDv5JqVehoF+ATrA0OcYRvBVPsgnnvlPOg\nWuMIIahHuKGHwW50zPwsNaUod1E2fk8gLhkqMqiE3SQU2y1T3hmK6MZXN9GSwJ5IIw5eyyO1FWGr\nbcgG3rsONmih7ecMwUp42jLQ5vSszqiQ+yHXepZzC0e2VcYZhWWEGgQ2qAP/mX+y+xDfZ5e//Dp9\n1vw1SwFlk48f3CJcsRXrWfDocPNxPWQEcFtYDHSPNwEAWpRDWrd1jQdLRZ7riiKEwygrvCTBTy66\nWshkAAe+V5my9AeXa0Ml2QTFJnaGjonlt4LTbDpP6lrDNO48TxYvwTeeqfPcLaHr0uKQt7YHP6Lz\niQFo8+yjuc0zEfQzoaETRrimF1qol1PWK3Qpfih9XrskpouGoT/zEL9vl3TEyQopv4PUZPj0Ynk5\ngLrEEhd5zkdYa0GWHcoa4Fot3qrp3UwIaXp3J0srL6FzrCXbDBf2Mo5NN+P8lk095AJm7GbHDjvE\ncDphpGwBKdvmbBEGbh6fHIOHTAhf+Vc8cPPX6BHmHbNOHZD0JlWZppGdjhHNpBNPnIBYS3tfqeR0\nfpgTvVPYXHmM322F7ZoQ/fwObdQAoj+tk3q0RroBJxQWakMIeQLVoja31p0u56OMldxuQgfF/7kr\npJIVirx6SAQcDVwcFSqf13qBuM+0Ol/D3mNr7ZjwWtpprSUZlH21ailV+zw2WyvthkiTp8YWVQBy\n1q09ZacNze6Y1ElACgh58iPN4woxeuIgISJzdoXdZHKr2rmaCQ72e80pFTsQDzTlRLDVRkpqAnDC\nxN+Mwpe+Fkm7f7w6HD9kr73bageDnyHcFZXpA468LRFJPWYg6wq9iFZ4TJAxrhk7MUFsxJtUscnr\nxLex9FDXv5JNgmR/UE/CD/ih5AN+x6gWb6/W3lszhJtU5l4b4IoAIBzFNDGa48+PO6Tl/fTG2S7N\nNWLwVUe5S3/022dgOuBphepqPGBaEk9aWfzhttADsYbd+EEH0DLjYEUNdOy0L0wxxD+dTHWxJZSV\n0ChMWF8mHSAFDH5fO+Hy1cRtVcPIRrjGMzyyvJjDaKoXzOfyN4HKL0d2Zjm/gFo8lez/ydTkt/CS\nxYar4AEGp/BN7QDDP5IH+BMU2l+zrhxqwQPo4bLd65LBxuQDXhUginwDEo82bBweomEKB5ujxPvH\nkuKtvrIWHrfWIsK10kpV2kY1erMU26KgDhIsF6eqON5qRijRBS4IWa4trUlIKxFe0tR1G+0lTAnA\n2b2zENNs3Owv+ZV3WgEeJpcYOOwbsG7qq3snQYse5j0ltcLyBO+dYgzePpcE55rg3YWCCn4hjKVN\n0vSNNutZw9QqsPBhK0qUZEvot0e3Awajv6HKZPq73c6PpUOaaFCTRl7V70cOsdlrUwteXMQJV3F3\n1Qszx9GyIwFkBAfl5tn7jsQzd2tUlf+3rxISOSF4by79j8FsMlkJW+++qk29OrwkSW/XexL+uk5x\nDWSc2fgm68pygKu/3KtuFKMEnPktko2ej3qtKmVvRPolck9fuCxtkXDMY/lRA/cMCbVJdOST8PNH\nltx8N3OjAHjF7qztXIGEbTgETs6qdtIS8Aaec2vMw8sZrpkkrCd83yeYgg89AlK1PMMWYpKw37mq\nTeNpJu+HCa81ry2c3bCvCvpF74Sll6oEliNJLH1QXvcQWLSiz6bAPjPvZNysBOkqwipQO7FIFujc\nH1i9gsKzAISZqDQ4COwcFkxKsZqQ+3+9LWF/SyoBGXGllUl7fn6Y1xtEzEcb3vTq2Sqz32OVeKu+\nLWl+IaE2DFDUpnM3NlaxYilLHTm/OtF29z+8txLIi56qb1wlsAsobeLHB8KpgUKsEzE/Edpzr+k4\nykpmm8XtbKx+rz1FpVqtx7C8k4J7ebUClTt9AaE+jJujIyeR6IIX9uzQBNiB2+o2Tb4XsG9P9SMb\nGbauD0yjImseltwlb22KCPcxWEUe2/7VOir1DkE9/wbtk6Q8eF02TJxwTZv/epiH8p09Zns7H33/\ngS6CyE0neXPK839SOHGZCftWF36xqrP1yS17/OA6PI3s/CTLfTs7YTx2codFR4imZz29y71VIoEB\nxtUhCuqGobdRNa2lmU42q3mPHQLOU1UisLPDeDI8qxbUi5FfabTKeFW8+xirZfgTs10x10q7KGnp\nbd0QGVaqot1rOHQ0HlG1SiSDeBp+s8HaYAdx9PmjO4bwDtiQdZ0aMJafmmYAYDSiRxKXnWvwtwJv\nkDDIMdqVSgH9shOr2WCOVuD4hebJ4kxzvxLQQYK3OsKY1CUdS6LMg1EBJ5fzEPsGHi2w0Eh2srkc\nkFRoCpIPylVJ01RZzkM7BHiJ7SsmbDucJMBZCFb8KFsmi6QZ4vhiXdTczreE7AXWtxd2/bUiG4vk\n+rP8o411sER8+1SpV3MujyYSJIwyGRA97P3vw8pDfsF+Ktr4FQ1M5S/UvCCDYU1c1fwEXhRTig9x\n8kRj/i/4u19Y7f8pW+4TRIfXSmqpxQLvlViUn89CBFT6NLiVqBHxzowlhoWrhi5zpYXxw5SRXBPZ\nsPxr44yLN8Onh2QMGqi/H00xNhG5pB31BEfTeuisYQiVZsCmsDMNFCZSUIZJ/+qQK5aL6ASPafTH\n35NsiMMmEtBVPcun5MPDeCi/5Yak2R3SSylLb62ucpJCFEiNSW9XXihs4lvRiD0m9Q35QHQaqlWN\na8FAdZpgxcb9I9bO7md4qPV/TFLA9Fbfw/ttXdf1LSjH9WiYpKiNsii9ttBH1On7jV9IE5ZlK9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G9UB4lpGFa3EvQQylVj7gEIapdNZX+/KvWDE1Uw+Mx1ch19lMWPerej3V2JsR60z8FZDuZBI\nrMa1yIuu3scJW/W9+zxr1+L71th+wD0N0930H0FW77WXKD73hpu0itMeJl1kTLX0C+4du/oXwiPP\nkKFMnSlhnmADk5Nzs4kXX56QHHCbRnr6eMuvZblXK0EZHGXSb4pQePS8267+j8iT4e78/dD60NSn\n3kcUWmiDaD6B8DhgaHuHl3jgJoT7tgyerSxV1v1ywnD+ooBqWrUAsYnJXP35pM9lvw9shjKGAAX7\njCObOS8VJZci9eTJcmygBtQacBP0AzSh8d0ZMgtsEerarYOHl0VaqrURAHTNs1zfXZ6atogVW572\naPtBaqUaUJB4BnKzRoP+YM/+HbN+k5jn6HFPg/wFHeOOsIPE4dpfWM76Fj9OndYwBoJrRfjLOqsu\n4QbnGR3BRAD5bq9p9CIqMna7zaj6r1Kh8y3bz0JLMChWeZWjoOnjrSOb3n0S0OcprlGZwIkSPhD9\n5e7JOYw8xSO/acOGMOr7XhVwxsvj5N71yDY9oIIxCmp2i5mKFvjdFKT7b3ivsMqpU6ooUNL1cB3B\nct1l8a3kFj0xj3Vjz0ipLbKBkR/JC+iOtZk5LGHDKd1jaSTRl9nSuO+bV9kLdDxwvYHAm3PP+PD+\nzXW0fPnQVICDYqkZG1xto1it9QOrHjy2vBNh/0ETekywdX5BIejkFzloAAm2ddh6NFnynQ81RPOp\nB6Ei5sZhxqlniMTJQNFN+PNXyW2lrwNTLew+TNDyj9rIZ6ETik2SHQpVEwsfSVmzfDCWqm0kta9i\nAjvtzWWnW+IsuGEsEL2hoy4He54jqi2mtn5jgFPt8o/zfixB4kuNpqBIoSoWJqkPuB6IQ/KJWlFC\nszg1J5hey/xx856i3HzxFJd9mVXALJY1cvYVCa3JSMQEP0sUcICrI0GoEYQ7pi3w1mAa8bB78jMD\nrfvLju0deZS0V3tBedhCRm9yt9XbJCp1F+62+qLtP8hSRUC/gOs9rvVULoMDmyAEgrf1nsbcBaRM\nQX/2dEMQzcBUd2mMjdpR0nCeJ5oxvFymHSOvlBYVhLq4CaROMreoChqIuejDpaErVFOfvu3lq30l\ngiYyAdBlGI+/GenmbO8fLK2EtGigHy8pIzuFQvaj350cfHLlcO2jHrl6UbUnMLdM/S+aBXd2Dg2E\nFKbI8PeZwIJrbP6987aJSwhWKLNgMNNjCkUqfYJ/NRB2eSOiC40TgfhufZuYh1fA7Q32tdQqW/Xy\nNv5slA2fH5SgHmwS9Uqxfc4jvp7SUOc7EToDWJKkVHzNtxfk+PpKRbG7gledErTqMBqWRm7rkwhC\n3jsX/qzzTT0uawrfLEtK5qRoYxdoZzMRcK6ix0rVWema9+AZIkOkf2eQ1XIts9qHSuNKuze2RXJt\n7XTiojoorg+kyigvlSv1D+o8cAQrd78YiWvhEj0QphJmFmC6jy6xpe/6eGwfy0a+fsjgc0ZCdt0o\nA4sV8eOhNsGrSsGhMLickahQrinsXh/8ILbGqvKtKAbNVNLyJk+6w9BTy8HoYPwRccXIahYFpgS0\n7pjDe1Gyor2dlKT72Rs9SvooqSu5tkPK3AFc6o8oQIzNtMx5dKNBHmDyeQntb/GTk8d4H6TAExAo\nsrSIFYwaxyXWQsgbStzgbi1/n6R3kvBFDAMD9ttwZ4hmPlj4sygAgzv6c6CfyuMZpH/keY20cVAJ\nOXijLo3hPgVD0p4n6FOUdu/JYgrTsHnOzGhUcEGws6R51FcuHxqXcBA57apz8QY31Jr8lbuhCmpj\nTNvGlI0SX6VE/NSoJli7V68oxvxAR58toqGrfJU+/YwnuIenC07xeN+mOIKyGO3P+4F7UuNDCPYH\nseoQxJua5/0RsZTGA9NHNAdpXJzze6l0n52PzQItK4epiSZiE7ZHGKz1YfRLvAFBrpIT1ArDhLFw\ndOB1iZgy9GNqwH8pNMvbfuz/+FeP1oM8/SIDdLSv0WDwM33gsrenitpREzjdByQjjFRtunJe2kyk\neQ4GhszWY0Dhm3qNNUlvlMc0xXvIiPl/w/QE8JJ6KgtMUdzTXgWd43HK+VjPyg1yJm9SC1+o6xlP\npEt6awJB3VCzxpu7jVf2OMsrQjiF4W728yfUJwPQUfr7VR2E97zmjsbiHbf1fo14acawqG5MHQW2\nZsMwfep7N5NAIX5rav2q5ZC3g9rfOUVkwnvp2F1HSNOWxKV+jJz7B6Xb5o+YhzoDd2Y3u9mZF/cD\n14Q3uTuV9Y/ufXtAhC372DYtV4oSeLNkdvW+eOTDr/k0eKWqnidKW9xIeLpCtmtUEhv+gSYNMZ4u\ndj1KJgp7/bMQMYReDRLQJIZTkcDnKvrEc8ObcYZ4GV1OwvpdWTtkiszhRjsUWD4YA3ir81byw1gt\nZKff6VWwZakXMdmcY0gcEhHqjdELSZFplYxqXNFX4LV5x+7eFjRz0S0IbvsVKlu5RD/Stma5/ZA9\nG5dOyFeuG5u5jQ1wu149LA4HvM0m0lg8BEG1MMOo9vjgOYEgfRz3sYRtSz2M+SnoWlt+o73somiM\nS8u+Sfiz3Nyg1GNSWlT3LLhfK8pxIEkDKkLPjRDkvjsBfkIr9jYYnK4PjvOHmKaPH0ZTSQzVm4M/\nvMz48765bXGQd4xL77svOl5rK8uyJoMmyQq76t/aXV1iCMNLgIiZDHa9eodbgsJTeLDB92bf3zgb\nkHDPhp/5Y96aH08BelfvO9ZsntgDvmOi0++IymB9PI2l3eMx8LjleptsWU81WDExuENmSPn5b9V7\nww0PkB4L+OrwEVDHPmgQvzOp/S5lY86506IzyZk+EFaoisJPL4Ix7TXgo7u2wHc8Kssp0X5YZFj+\ntUOk8kYsuNRrd81CR6V+ukNkM89t+W4aw/ajKDTT0LmUqRhMGQvh2hOqw9UksTCdMr6/WgIz5pbm\nKniZXfCh3cMZu2TysZd0Gmg/MbZ6ohsBnlsnrft6p/E88NNo66e9qomw1v7eVWGswqmbDwalyPv1\nxBVjkSxrxfkyLQB1YfibsLY/wqmdq7CHSlB0eY3D5meq6O7XDf7jcjnKVJ3lnx8bvmKf6aT8I1cj\nHtPVm31bdpptslWZUHTXnDl5VYP4NJJQN/JJQ+GcRra/Ik+SxQ4vqTeRuhOtQb3NjBm4FpDEKSSH\nj3/IaA/l3KdxVNAbLRenx7/pEnd94HpKkLGiH9J++D+WtogNWlV5Ran0qN9ZVxtMgYRQ2CfhS+M8\nOoVZJYYvVWBFHmhz0Mng5gkK7LODy7ij23SNkqmbfMzeniulSE1jAHHSIgqxdMSNQ4Q4AwN1m4YH\nQ/xsFz07AK9LzQIQDv7U9Wr+nglKxlsXV4hcMSdcPHy6cOcH1+LQihIVUm4XUhH+8jEFRcwVzbKI\nGfP3Qa4PE3o6CHTTLgjitYN9jl/G7Y4dTuIWbIu9jgPWY/Z9eP0EIIj0WKWsFBD24E/QTfUUgNxH\nGe1uU+XisJ+7XHwnFN1GVgqCja43OyD+CIWdiYhsTWjUgpJ5E0fxc+AHqzHFY2a9Xj1wfDPyxyoA\nW1S9e0KjBPXF8hTpLMATGsbXCltlAQxJlttlBFZKCCAsI7R5cW+xpMyW/mU7SgBUJ2lPHybFdvIS\n/kkKwhO/kHKUXCYtD5Fvgg33/UXIA8UcEHrhUraEik9Cv0YEmwcEdEM+b6CMPDjwUqHMLLWJvB/r\nYZOfvrPtNP97tOh+Gzilb3WkMDsLHUw1HwbErVEhj11lziLbaej7JqgEO9/M8AC27Al7FXaRqDYP\nCuxwoB43b8tGyEmDFLCCjC8Kk1ztEP/gVA+n8Q5l5sev/rTz30Zxgwc5ZZ1d227+TLCP21iPo4O/\n1ZwVEJ0/mri5mBLBOP3qpG1jjuxhpb6xsDRuvbXY/bu6nxERErD1bIVcywy+vBTa65irGR6PBNhZ\nRLtGiZQ9eVfYdXcOnzksALgbMY3RihTlYwNLoDhz/KfMFGTo/3Gah8gk4zf8cCFZO+jFWjQ7l6nV\nZaFpZHFkxLWZxdn+9jKXsFEObkKPKJ01RmnwsIrgcszIiDb5qUx41z0djy6IcBO0+CJ2IigVN/XL\nADeVMeG/d55n0yNPBJtXwU0HxKtT95amNObp/i3V/o7cGrc1TfIfD6ucXn6RtcPGYh6v6pTh0wsn\nmitC17c2iHIWWU/b1+kGcN6VSOkti/66NmUcNWTQHUiQ2I/pD8RWfbxqGNXn2QQhSwST+hAve3p9\n3CqIBPuTqPwBNNWr2jH6IeaRn3adw9H+MCX1QYAF7v/zF2gaYnQVDTduzTN25/V8vUg4lPbOQqG8\n2KCc8NqRPN+trTzRMrh0HIeK8q/+G6pncDXe3PngfyXmfFpCIJUF9RiAs4/J/Yu4ZUd7Nso57o+9\nIA6EVndlXVZlK6nkkZRzhAdYfso8SfpArimn/HYTgGUpfs35MOvKk7zmKqXAxPZkcurMVQ01YS8u\nONptVvI0ZpoDxl/FyLoSGTPo0BzKwwj4UnI6xVjdsT0V5swbEFntLW9IArikjcP7AbfVyOXSats6\nTNoO3qGEve+FXkt/onl8a41AgCWlL00twIoOs6AasHipMeQkOgS0ipUaGjDKcn5ceCWM6+jm2JdC\npbP+MOMtLYYdCyLcULAkhpPwRQIkGQeDcRnsPAjuZWfUHPBWkwkzIHYn2fDi84yh2FvppMqxrLWH\ntNcrGlgWvpHDCdojVWATJI60DjXrYDvJwXNW2kNUC6ZIBr917ItTlQ5surQtNdLCMVKXEWoQNU7q\n5vXU4Cj19Cb84ao5ZpC1dWAI/CNtZyV+9D8HsSf1oISFMRwY4cOAnTDekXrOj/Zj/1qLeXU0HPw/\nuyNcYPiG2qitycy1Df7+/FuFDukKiLkrUsbkdvhOeFQ/LOBWfbBPtNd3m+/57kevqzQpwSQ3q1JL\nAfhHcE29kLQb6ZkrFywzimdO1QUhQLrDxd2C7A+H+0ErTsLOBt8mTIf0bHXUMG8jo8SF3fH3dcW0\ni9VqjocNa8gvtiDGpX4ejz2/hkdEgc50Nsogn1Yop21X8oNvDFJ9Z+2S46IilYBArzBIMhPc7GK7\nTzaIknEGcVckL+lip1TqCZOkxBQdWju+T9/x2rLovnQJScWz/DRT3QKfMf117zA83RxVQrZxfQw4\n15AcEPVUkobhsGOyWd/uonrJ18Chkp6zj8VX8Ha5smr+QpVq3eLzlb9br/VOnrAnUSZ0bvPvjQl1\nI6+lK7EaYF1Lef2z/LfRBTYgqXAewf3nzpmM0wdzIBK4+WCChRBH25ieuAj6DhGU/4dNd5iYkNKw\n5UFjIH0w/7U/+ugyHgDp+nC6JDYtfubj0m0KJJ87RJMmQ1mTNarOu0urmlikkD7+HDMSgYyLEtuQ\nGaSH5vSHsJNe1baNRTA9VZqhlK0zAIBSMEOEhwUqnE1As8+bX9mBFw1Yisk7M/bpzK1mIF1ayLiJ\nGtRL+mvAF7ogzydkw6AZq49ZnkRye/Rc3FSP0qOsX0GAdCjMyaPoSZ919BBXkDatQplglrL5Ap7G\nC9SnQ+UEph9gWx619N+OqIaVd0Sy4GHMXVNXZoWzCGStmOBFx5wU/Whmf+CQQC00fC5T2zyRX0X3\n8TKMKhvJpwWVNtsQv13de3iiNlO1r33Rr6Rz90IILkiLnaaOlZn0gsuUdQQFv5nAq9ZklwQU7St0\nUuSwd+CMyM3cBpYc0HdW3qNwu+ekYlkNKdIFoJ3e0E7qqdNgrYC3Gf12pJiH4lzbRTPZeJzMtMiJ\nS/W+W2H7pW8uOJhZtvIHy/r6/12etJ58zmR/j3PTISTH+55NnYBSGQhXfLN/PrZxEkqeUV44ke+K\ntGWb4cvQD9qBtaL/2JvQzWdwPwTNnq/VOMDHujxwxkazRZQLoavtItyYdaNm1gt8xEzjW2jnxkHL\n7KbB5ZaBXIktxcKqBK64RnziU/bgmFdkLltLuHI55XJSKFd6m/eTU2FmwVMg2rvrgS5i4TwtpL/a\nrsSKWWQCHSIYhb9xTqrzYigYpHuKDjayBqK9+OuA2rTgDdKq9oaxyR/jXySiUxcDh6/az9/NMLQe\n+KGX2bvG3wWdxOs215xclv2w75gXDDOqmYINX+R6Roj/5aUgY1dVU4YCrTi6JGSdprum/c8R6r3K\nBuNzCsiwGCuC+B8q8n8awIiiACjqG/gTisr2FnyUMF19VU65vml2ClFxMEIgiDsG+7uVpVF7Ks5f\nybAZ75BxISPCu2Liw27/nEs4H4aIfBZFm9ffGbAJBal071TlBZhk4rtNqVmQHiEou4C/NvmxcFNm\nZdBkKqo+rmrY3o+/7PrhbZPAZmgUbjAtMHtVne+vge0EF0uj/h3Sq9/2W6bgen0xIv/fzQVSGlPd\n46ZekLfUr6UsLfTrPd3ZFy1yrg8VGInFaN11yTTkTPzcD5p6MzOwLm7UJp18wmNmjk/BlTQ1zvvg\n7e9NX6SRJyF7YdaKwCQYxTQKm5lvUiBxrCcChQJdg6/BG+zVTZT+8x5ShfbbzcXnrfZXMB1RKLuv\nQilDIlQD5VNRgP2K/nbYxsMDjoPRRuQduQ9AG2NyeDT3fGzcxnaUhF6cMSgXV18yfbNBKrl/ie0/\nH7CkmgeL55l3iV2HtsERAx5kEki5NSNovvtZ+jLzxOiuMFxGe2YRpHttIX0l9YscBYzcuESoumlj\nRp6KFFo224Mw8LZSYX0+QLN/W8SRrww56eKNDbbiVU8DBgXEWLXhS/1q/+SoMLbvnr00BDAfbScp\nMOlo9rgdLsOBwD90jQAAvWVk42DxTWfqs/2Q6sE5CHHDEeytdzchnA+2sHM1Ua5LyW8R735BypzF\nyS7tDnyBRxdi8fLOqvDT+LrkjyQsdeCPaZ5HyGpPW55Mmqg00U78uV99LQOwL3Lu+klhr205h/Vh\nyqRvrSBDsjXlBcERGNTb874qY4U2oIdRTqkR8JatCImB6tOG4z4OGkZnCaMespRfx0xh1h/b8c4U\n0m3cjfx+GyjuXBXKNzK0L5f26aA4HLeOMwHuQtRxmhUth92jdHCtkyV5fzbr19dt3PdWn+DnghNw\nmvRsWnJq1pTlpo9aeDt3NDSHra0iEsRfxb3UD9AeHjI0+AkahdLHzNLPRihKpE4llriErZtBC09Y\n1pZq82vu7ZAyYxw9UowxtlJZJ+RcLopN9S34fJ9APRQ66/uuYuD68W+7tTiTNyZHoKkS7FY1Uu6W\nHFyanD61UeLyH9apnXw9DwRQisUpKCy3q21CqCEiWvQ5+C/vy5qC2N8WwBSqj61aW1yQyiYWkBXO\n4xQU+j7sgnBN81KG0kSJXHWcFk/h7X4X1tLr5Ggr890jmGDv7DA+VzdZ7Q3fTJofXmuTIgU1iE0B\neJdgyl1EXsPbo7hUVFVd2EgQRtj3vkHwSCjFVF0gMLaNVf9LcazqIvW4HFFI2tt8+9MFEyenBEgB\nh2xqefXa5q97T4n7zl52mZa4apuhFg21ZyMgeHFgcvbyMJ+BkFVkeKcVVLVyBkZ33V1fcKy90Lv1\nEQIYUQyIACjaEpO+V8EzSUHzmbiWHkouuOe7aRlkH8lTQFjwNnFjhii5SN7T/HR2gqfQoRpSLNoX\n11xPlONY3eNXFfbyVaOKUMCenFuAqN4TTcGrdAeKnFQHvGSbS8wuxr0L6LwRRtmN25YOmq9n5BxF\npV9Chlz3Nhtm+6T4ei3j3vremc2G9BTq8PZ1YLQZqJRyh3Tb2IMQ23HCLb3yoQ4ZpPg1ZZNymmug\nVql8TPMelPFuU3IEXjpgy0SDbqUvZKcP5PKHTuVpdY5eRizzWbn7a6akaK67C//8IU6pBT6WkpLA\nVDG7HQ5KKlwvriaieUvWovcdt+7QusnnssrSWlMdK9jrZ82u9HUYHVKV8Xd5hDB1jYVu6Px36hQ2\n0v1g782llhV76QhcNlBHkDU2CsK3X555FSOcdMTD8BI+n5h0GROXkhSGlodgZTbWppO5QN3jaeWZ\n9a1HLU6dNMfTCEeOUe88KwDZPEFqSG4p0VtwrI863aJ04foZhZDyAjI1PDUNtgBZO2Oz+DJyhXaa\nKSEoR2Yj36JwX9JPzW8mkGxRb5Wx9N9I1/Szbje9t4KwPjOml4qWWpMqrBbpyrs2396STi4KCNLQ\n8dD2nwuApS26e6KvA3swEStkmcg4lPaHt73uL6N1VQxViQ2EEy4rbFy0S2AJzYqERyU+GtstUOcW\nh04cyB/2ofzso/h7nK59EXXXc8lmeFNNll2++rzh4sKZqQajxs/8Gcj65TLhk+uPqyAaFKmmSZeW\nd6jvCOCCgywB1EHAYOnOb9vwGGRCO3JGCLmC7QDTjTOm0FkqGoMUKYsee9Jqd+AtP+t17eVGuIVY\ntAr571S/EkWBcgDYPevACCxmnBp9OjNNBOskcVRUg5XMIim40rW6rv7bFDEDgpcXtBTw5dz7m505\nEJTbnrS+//j8NK4fgaIOl5bKD5x2qP1Z5CcPQc1rxLrkLFrTy8XlEptKXR0t1lQXd0Wkef55TxMT\nqs89vIeZfvIhprc2C9fK2RVjSYAhkj6Iu7TCimjFyr+HmsOsOQQZdQ50WNhAid1TjahlCJ9yCSM2\nSFk2oFhu/qBAvz5cPs0x6lrrRmRIoxvX3WA+IElb9TyFBPyP4BWdTcbfqnQ6XGDijou91uAVawoD\n27aFmoq2OCWPF/Fp+D8dcmb/XoPpK0SOEHaBU1ILRJkdRd6Ys4bq4isO3Sg8vkyA2iNcEZ2DtGkV\nH9IgbGEg1Mv8sPc/wjFMhb4BEqxNWQEKiYgDyA9+0VdYpJdy5X5gZnJxYxhzpEOLZpbbnjd3UeK0\nEKkNXwA41V21GqTZrrUlF76kn367l0KZTNgiNodIaDhxBkTPLMOtpDt75KoJ4Mrtz7HxeJXlUMLs\nj3HezUvOkrRldg1d/XonaIPRDgjcQFhIRTjOEald59tKjB5scFlrOqdI9zQycV4HLXdjifdfH/Dr\nfrQHwLor3niSXfIlsq9V9vLUCFDTNCRYzaE+LlNQbFITqmDUqy70neszXu3lowOaugZOrCx/xLiP\nss7Ja4qppT2Ctc13JZXtKVL6TKDel2VCx7xv0TxpPluSpiKZKUTQwzEb//Cf3o8HRx2YSwZM+kXo\ndb6T5DfBGcLWIujpgWhXW1i1aawHOLQMRqa/bpKAA5En4IfdYbHy0jt2k40ZG11elMVI6RKAtaZb\niRfZ9R5+Q/n0q/XlsbqpiOST0JUqHw3TQzIUl3a/GTAEM1B7E4/aXxOBXoEIBgR+lDXq59z+aZ6V\na/qDF6Cq85iXpIprWSu5PAw2ImEaHr3kZMg5pBYq2xjpYIX0L+FWB+/rlaegVs8JRRX8w7TjuPiI\nldwrcr8nj1s9l18z3ZjIvvfO6i9F8v61PVCGw+cJMCffOL1DUXz2/A4LdTO0Qq63fsJBzfrwNPyM\n4L9m0il1+TVxHhXVoSuSoXNhiIJbWut7GbW+rvTCQJjWk9HIPTN9xKxKFZsH/oRcWIyUI3ogahdW\nH9NEjMeVGwKaYqs85ai7US4jnVmxeYqc6sL6b4AI8zQW9lDAoyygkqC5NsuGZrbk5/GwdIpbCUza\nlV4lvoWrT2nzlCPdE7HqdofSVI/GPQ7EIhG0S9jqrL83rET779F7bWP9oFwAM3WXq2FD3zm2vtbh\nc2dLOEuB32W9sPfobiDEuqaCkrDTI60b+AgewQJcZ9mzktJhauyA5bDFxm/U0ffkqJaEswDtl8AD\nmAo2U8WeHnyMJEqkxx5ld5cLyF2UAMmCM6lGPtpgvknUUkNYs/lD2XhqxuM3cNCLZuvieJKxtFvM\nLbd0bNRMCX6bSVLjKfv+IW0WDBrtuJ17aCr50G1IvprZKzT/xRPVIu0p6p8hNH4953J/ghs9oo7c\nlKQ8loRvT6zSp3GyffPZJOVn9gu8lInMpJwWkFydpk0q/59aiHDXSoigjSM50xfZkM2xB7PXVYTd\nQEfibQ8bp33CVYbaynaCCaQqHVGy+9ML5q0Dsu1Mgs7ttCcpp3W5akyYcO5d8+GUxBMUe0sNq4tl\npVZNNwltEOiqD+QngAx6UkKw0PCg2lxyNyCQZ/E/symhb7OauoiCzQZVF02qMdopaQmGiY/ODvoh\nYtacenkASzgbBSOk0fOO8SsKAaWfuD6KRT0n8bSgZSPboejfoQpVOEmcxM1fFfIbZn60elHh0TWB\nclK+JftnN+AWkwQfTB/JKniwZ+lvqCsuieW1NmyUSR7ykBcRXXSA/0az0coEL/9bCmUeJje42E7X\n3q948+DGDEJc3wvWBANApYi3T8dvHoSv/xB3Sg3uVrCc6Q+vzOhQ1zgvY16rPkvBghqXZg4f/ibO\nGUrA30eB9dJYQkpT6sAhBVevG7t2YLCNsCNH/EpX88wA24JkJNBICyrhs/fbTQI5l86rmfxDybaZ\nV+C5cLUfrLvS74A9KOm8LzImz38+RE9naZuWIUwEKZtI/IqDkLJksZiw7jp+r1Rt7CnpJ9kUQ/ZY\nxwC6FwKaMOPLuelslAkGiig+MUGK8U8q/0wzWTJQgRZBSfu2Md+jmJQdLrdN4HfPGddtNg/rkqpZ\nGnTqmDTCNZHKaKyh8av5iZgAl4C5nsLhKmLgbbDFzsnrzKEv/IoHy9a2gtR2q2q9+ZmZ+TI9YeuG\nVfTbvZgjNKN+nNiL2kT1tpRoHf07mpdAkuAWMrXqddkcn9QyHYLlNOp0dRup0GM1yx0nHY/0hNZS\ngSJkzkBSDJu8fLjwG48jloXCrLjLGo/IUBDwOwUhyCk9ZJtLg5AefO1JndkWU33X+0y1xJGhoK6X\nt6FG7I4nyaqrsoFB6Ha0+UWSqsM/H+hyWWejJpBaI5nHPEZBbLwwaVm10hAFZdZ7oWB2Ve0Dbnyc\npOrPOVUmWOxTiIt5+hkylvrkGu1sQfRU1kBh7ynYIRKOvgljxP/AY0TI7Xs5ZxGJEJn2Y2H1PseT\nxvStZw5RwT5vYJxk/4tT+g9K3BU0LtE0UyGwpIDNlHpLPIT6CIYXNO/GC6vUfCrJh3qh8Pnyd0sX\nNEktZgvb5zGBYxGF46EU9bBwCX0s84fJ97aaxn/gTVv0Hcwq3cUb7U35uO5LHLjrlnUCh29jH0C4\nldzTqhf4Ch9XicZ/uJPVEONESBUmYskm2Y4EuudYmwvVcwEKCAOpmOVSfIHqvjU6EtHuvL2cdO8D\nx41OztnDd/549tkkn/p5SAcs25RZf0vBjrsl9Y1Iezqa3V8z0ZhE3rNUhNB5Oon2IkuC0Rvvltt0\np98veNeUyJDoO2k+hmaWflAEhX1e1RCZNLYx0xSquZxXD0VeaFUEObTKXdejMa7v597GFmoVPkPh\nYKH6ST9ati0TjVdJf+dNVqBRcaHkEzJcAMZLSdNRhPRTOB8J2OM71ealSLZ2lR31089Zlq2QZNaj\nK/viSQPz9ANHmXy4Y9WozP0JCYvMvkRgeF6hmpUEozNEh6efj09VSvAQ80lRJEP4pkFKJoahZ3Wh\nsGB5Z+pR90jHHKeMmQM6lKnUbSlr5YUmqeaSnY2FH60mUkKudlzklCc093iBPlN9fpdkbyQYXbZx\nfa5JtVZLHRLhAJVlIE/gR0js7KeS6d9pKkTFPRPbBwhFPPmZ1TZH//Z99ZlfRf0puhG2nMjqC8Aj\npYZlQ3yB3QR4fmEtLxIjdpY2/IsBNuR4WMI9P7scb/3S9L29X8bwzpVCBQy6WgdogzCZwX/KSInT\nqudwNMs34MHNXvRRBpzB4PVypZOD2LPg4A/JFwAe4PaD7f12CqAISeKEDLQJ8mgfGXEgYzOkRrI/\n3+YV8GNHuTH111rUwy5EO/xyhuMQCnKcUeTbg4hNXfYVdHTr/rsDNAhZg4RfYg2qBoBQblA+Hgoh\nkbvSH9IxR3JbuZGgoS9Dtsr3ichy2pHeO+wsbz1+EFBXE2+Nv1o27Ctl9YTjZy1FkA4F4DugCwI5\nJwmp4CSxlR5V9SDaFHV+Vu1TwBdQY3ttVnuAN6i7awhN1Ad1tIIaF8TH5pERQd5S0fYyxWgjLhn9\npHWVDFC2G+fhIL3BhQUohuHk4oCLQ6L5awnrPPLRqRn4zQDlebCN+fK9J0gdnvHyNyYQ/kaeXF9x\n4QhjVofyFnwwGIIh+pEx3UggaiMCTfm12/JPErbaC2cWkqNJaBKJ+kZUBwTutslEOVEue6ZPibBC\nlvVbw1M+zU3xyPx4SY/MzPQav6MEvRbaT7aTZcFf9la1TtyYvLgsQIB+uB1Jki8vLi6HOMcBThQv\nemw1tXDJlwv/TYh78mMNpllnTGG2prieiBG9cResrv5mEZRJS1RjRyTk9AGQ9GaqTIs0MAVikqco\neK2iSkNM0GWEjHtSluZrD/SzfyYXZsSzJKzD/RmeX2pJmqBaZ1KHgSOzUJC3O6GAQiLE2SDYrQfc\noA14lbLXgYldDUXJX5nrM6EhnNcaT5xBYelhPiqIG/qOsAt4HWOm3SdtK9P6COkCKAWUXhHTeukL\nmKEVwZsqRLRbu0SdhxgItkILQs0JHSpLRmuJfkmZgm53NthwkWNu2unlsZdzeNpVDXL9ilhT2iO1\nNH7HurARdw83ECxK3Who2IcWtdm9+cJ8LNR925XkNJKhHJhhQXGa4GesfJTlLwa0J3J1olAv7dJD\nIVeq5XnXOyW6gzhDzTpK2afgLW3Thq9EY8cM2oWk+vjabJ5i094lTotFRSv9B2lzbIuWBxF3JH0I\nudYhXIW6B9qFceaPBMQM793OUBQSBOi3WGu/Lm0k0FUyRzsTPr/9d1BRWD9b5YqxnWniN/mzDQmA\nYZpqnFuhZFS83FJ7EriLaOJXoisxsE2uVFxQZ7E3c0/WVyt9Pyk+Rq9vxE2c7PUmojV3Rewu3xgC\nHUxvS/q4yXuSWMwqLEbhRt8KyDGB2EcHrMGojI9A0ILuJiueXyd++NuiozOyn33QRNg79tDZH3mv\ni+8I7tqNxp3T0CfBA9QeH1tn6GHvkNBaiaZJ4ioqg2EiNpcbn5nNy33NT53S9uSlyB0Gzkqj9wf8\n0hR3wtkRcGA248PtuON0okzf7rE1mJDI5+hfpRgGyJjEbfJixeU7Lhk1PobdVkkGahSBtTqc2Ldk\noQMllEOGJTuXu46HY55ne9BLbK29u+3MMBz1KAZ58qKCo7sPv5eDsexOr/w3IGHx6Kdyme9VC4gI\nHpr/JGRH5gXt8I9AjgOObZ8YzWCs/KErnh5vKjYPgooq9PMFmD0MKcDUxefsPGCZbtJmcVefKM6h\nBlmVXH28KYc1/71keR1eZBOfhZN5H4IKnWJvnGSPEPWlNmkHDCmMBA/arDVDvUljsoTjFZDXP7T0\n+TjMu/o/7F+zMcZWiYKhgVKkKdWexgpiHXrV/jzlxFhT9fPcBL331pgw832rrR3zn2xBtdx3s/Ag\nK1Cob56W+pntouKPOSBv235PCfPB6A6/Ccw7rvfYZk8LHxle4Y1/PzsISmSD/LVo4cm/Exalc3bJ\n+jWv5iO6jmO2H94k1iA0Nv/3zHgy5iIpqr1Mv6JDpEAtk7Fh/Vh31tsj8vm7ypdcArVQLrZwKYjX\nULh2r6jJOaE8J4PZIgVVGLE9YOmo7BFmfeOhlhkettJhttRcLQdBg126cn1h07bgI2/R4A8FI5ux\nEaWY3u77/vSyaIdQhCF/P3CDABPg+NUyB2mOZkueZZLn5WcQXi/qsIaWa/tXDAGrSaNPF0BUpr0D\nNORQ2oB+sPYpR+iCKvBonHa0hnYsrGlwdwEsz3yguKJpXImkzHAzuYg4Liz6ePZcCW2ZhCSATfZC\nnsGKryGfcDacjk9bvdnNyM0GErMfMbCStu5PZ2r7tRBl+JAYLs0q4OUbr3pX0ne4yoJ31nWSCsl/\no6uk+txkgX3mufLWDGXeNyfaar2RWSKXXQNY1ypDhVTMGj8kPYvQq5HkaZ11Xme0QHgfuRwJqtqh\n8lzVdEQqR1iXV4T6JXENbyBJKTdtkWgcHSzL2s489b3ObCag7j8FPZT5bw+8FliIPY0yxkAr0cRR\ndaKSqx8MxxqntzyJSv66i46SMpCdBKRq0RxZxkv+pHlbESDlhJnZATCho6xuoLk3LI/X2BFR4VX0\numzxeRO/zPXvZWEFgvWb7vPucX5mlBx4j/13u9aZVNcv8qzODK5Tvgdgwc5TSSZq49U0v+9FJFNu\nvSxtSDPPL0b52168r8Kj8O5EgF745J7FdO8n+gu+ma79Qfo/v3LNezC1Q7phWk+RLwYWEB/fC44v\nDbkUkzn7niBiRc+gffcMBzcWNXXMg6ym6FHOMi+xkiVFXFvLIc39i1tT+PyocfD9Yf2DSG2WtUXb\nrExRkxKCe/O/375k4LLknHaBoJmB7m4FcgFZl6WZcgL7Ak78RhFXrmeGuxcuGW4b2njWh+RwOFuD\n1tPq/OWTREvGcq4/OCyOPhuOmLuJuFbKroZYZQKxLS9rTBBVudy8Lm6wygRT4cNoQgO0Ft6wE7Dk\nLVV5SkjkW1wCKNuC32+quUYlwToikg8OX9hqMxp8EAryEIAkhcYpC4+WBh682E/q+e3UzWLiutoy\nxserP8cf15U6aL4UT7nL/Nxmwhw6EzKtHC8JgJevouggntc2V+PvI6qi9bqstuyZu2ogmWkrB9O/\n0vwCkKjyNJMOY9w4Ltb+Jc3mm6sZ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{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_0 (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [63 : 0] probe1;\ninput [0 : 0] probe2;\ninput [0 : 0] probe3;\ninput [63 : 0] probe4;\ninput [0 : 0] probe5;\n\n\nendmodule\n", "num_lines": 73}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"ila_0,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_0,ila,{x_ipProduct=Vivado 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PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1,C_PROBE0_TYPE=0,C_PROBE1_TYPE=0,C_PROBE2_TYPE=0,C_PROBE3_TYPE=0,C_PROBE4_TYPE=0,C_PROBE5_TYPE=0,\\\nC_PROBE6_TYPE=1,C_PROBE7_TYPE=1,C_PROBE8_TYPE=1,C_PROBE9_TYPE=1,C_PROBE10_TYPE=1,C_PROBE11_TYPE=1,C_PROBE12_TYPE=1,C_PROBE13_TYPE=1,C_PROBE14_TYPE=1,C_PROBE15_TYPE=1,C_PROBE16_TYPE=1,C_PROBE17_TYPE=1,C_PROBE18_TYPE=1,C_PROBE19_TYPE=1,C_PROBE20_TYPE=1,C_PROBE21_TYPE=1,C_PROBE22_TYPE=1,C_PROBE23_TYPE=1,C_PROBE24_TYPE=1,C_PROBE25_TYPE=1,C_PROBE26_TYPE=1,C_PROBE27_TYPE=1,C_PROBE28_TYPE=1,C_PROBE29_TYPE=1,C_PROBE30_TYPE=1,C_PROBE31_TYPE=1,C_PROBE32_TYPE=1,C_PROBE33_TYPE=1,C_PROBE34_TYPE=1,C_PROBE35_TYPE=1,C_PROBE36_TYPE=1,C_PROBE37_TYPE=1,C_PROBE38_TYPE=1,C_PROBE39_TYPE=1,C_PROBE40_TYPE=1,C_PROBE41_TYPE=1,C_PROBE42_TYPE=1,C_PROBE43_TYPE=1,C_PROBE44_TYPE=1,C_PROBE45_TYPE=1,C_PROBE46_TYPE=1,C_PROBE47_TYPE=1,C_PROBE48_TYPE=1,C_PROBE49_TYPE=1,C_PROBE50_TYPE=1,C_PROBE51_TYPE=1,C_PROBE52_TYPE=1,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,\\\nC_PROBE106_TYPE=1,C_PROBE107_TYPE=1,C_PROBE108_TYPE=1,C_PROBE109_TYPE=1,C_PROBE110_TYPE=1,C_PROBE111_TYPE=1,C_PROBE112_TYPE=1,C_PROBE113_TYPE=1,C_PROBE114_TYPE=1,C_PROBE115_TYPE=1,C_PROBE116_TYPE=1,C_PROBE117_TYPE=1,C_PROBE118_TYPE=1,C_PROBE119_TYPE=1,C_PROBE120_TYPE=1,C_PROBE121_TYPE=1,C_PROBE122_TYPE=1,C_PROBE123_TYPE=1,C_PROBE124_TYPE=1,C_PROBE125_TYPE=1,C_PROBE126_TYPE=1,C_PROBE127_TYPE=1,C_PROBE128_TYPE=1,C_PROBE129_TYPE=1,C_PROBE130_TYPE=1,C_PROBE131_TYPE=1,C_PROBE132_TYPE=1,C_PROBE133_TYPE=1,C_PROBE134_TYPE=1,C_PROBE135_TYPE=1,C_PROBE136_TYPE=1,C_PROBE137_TYPE=1,C_PROBE138_TYPE=1,C_PROBE139_TYPE=1,C_PROBE140_TYPE=1,C_PROBE141_TYPE=1,C_PROBE142_TYPE=1,C_PROBE143_TYPE=1,C_PROBE144_TYPE=1,C_PROBE145_TYPE=1,C_PROBE146_TYPE=1,C_PROBE147_TYPE=1,C_PROBE148_TYPE=1,C_PROBE149_TYPE=1,C_PROBE150_TYPE=1,C_PROBE151_TYPE=1,C_PROBE152_TYPE=1,C_PROBE153_TYPE=1,C_PROBE154_TYPE=1,C_PROBE155_TYPE=1,C_PROBE156_TYPE=1,C_PROBE157_TYPE=1,C_PROBE158_TYPE=1,C_PROBE159_TYPE=1,C_PROBE160_TYPE=1,C_PROBE161_TYPE=1,C_PROBE162_TYPE=1,C_PROBE163_TYPE=1,C_PROBE164_TYPE=1,C_PROBE165_TYPE=1,C_PROBE166_TYPE=1,C_PROBE167_TYPE=1,C_PROBE168_TYPE=1,C_PROBE169_TYPE=1,C_PROBE170_TYPE=1,C_PROBE171_TYPE=1,C_PROBE172_TYPE=1,C_PROBE173_TYPE=1,C_PROBE174_TYPE=1,C_PROBE175_TYPE=1,C_PROBE176_TYPE=1,C_PROBE177_TYPE=1,C_PROBE178_TYPE=1,C_PROBE179_TYPE=1,C_PROBE180_TYPE=1,C_PROBE181_TYPE=1,C_PROBE182_TYPE=1,C_PROBE183_TYPE=1,C_PROBE184_TYPE=1,C_PROBE185_TYPE=1,C_PROBE186_TYPE=1,C_PROBE187_TYPE=1,C_PROBE188_TYPE=1,C_PROBE189_TYPE=1,C_PROBE190_TYPE=1,C_PROBE191_TYPE=1,C_PROBE192_TYPE=1,C_PROBE193_TYPE=1,C_PROBE194_TYPE=1,C_PROBE195_TYPE=1,C_PROBE196_TYPE=1,C_PROBE197_TYPE=1,C_PROBE198_TYPE=1,C_PROBE199_TYPE=1,C_PROBE200_TYPE=1,C_PROBE201_TYPE=1,C_PROBE202_TYPE=1,C_PROBE203_TYPE=1,C_PROBE204_TYPE=1,C_PROBE205_TYPE=1,\\\nC_PROBE206_TYPE=1,C_PROBE207_TYPE=1,C_PROBE208_TYPE=1,C_PROBE209_TYPE=1,C_PROBE210_TYPE=1,C_PROBE211_TYPE=1,C_PROBE212_TYPE=1,C_PROBE213_TYPE=1,C_PROBE214_TYPE=1,C_PROBE215_TYPE=1,C_PROBE216_TYPE=1,C_PROBE217_TYPE=1,C_PROBE218_TYPE=1,C_PROBE219_TYPE=1,C_PROBE220_TYPE=1,C_PROBE221_TYPE=1,C_PROBE222_TYPE=1,C_PROBE223_TYPE=1,C_PROBE224_TYPE=1,C_PROBE225_TYPE=1,C_PROBE226_TYPE=1,C_PROBE227_TYPE=1,C_PROBE228_TYPE=1,C_PROBE229_TYPE=1,C_PROBE230_TYPE=1,C_PROBE231_TYPE=1,C_PROBE232_TYPE=1,C_PROBE233_TYPE=1,C_PROBE234_TYPE=1,C_PROBE235_TYPE=1,C_PROBE236_TYPE=1,C_PROBE237_TYPE=1,C_PROBE238_TYPE=1,C_PROBE239_TYPE=1,C_PROBE240_TYPE=1,C_PROBE241_TYPE=1,C_PROBE242_TYPE=1,C_PROBE243_TYPE=1,C_PROBE244_TYPE=1,C_PROBE245_TYPE=1,C_PROBE246_TYPE=1,C_PROBE247_TYPE=1,C_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OBE525_TYPE=1,C_PROBE526_TYPE=1,C_PROBE527_TYPE=1,C_PROBE528_TYPE=1,C_PROBE529_TYPE=1,C_PROBE530_TYPE=1,C_PROBE531_TYPE=1,C_PROBE532_TYPE=1,C_PROBE533_TYPE=1,C_PROBE534_TYPE=1,C_PROBE535_TYPE=1,C_PROBE536_TYPE=1,C_PROBE537_TYPE=1,C_PROBE538_TYPE=1,C_PROBE539_TYPE=1,C_PROBE540_TYPE=1,C_PROBE541_TYPE=1,C_PROBE542_TYPE=1,C_PROBE543_TYPE=1,C_PROBE544_TYPE=1,C_PROBE545_TYPE=1,C_PROBE546_TYPE=1,C_PROBE547_TYPE=1,C_PROBE548_TYPE=1,C_PROBE549_TYPE=1,C_PROBE550_TYPE=1,C_PROBE551_TYPE=1,C_PROBE552_TYPE=1,C_PROBE553_TYPE=1,C_PROBE554_TYPE=1,C_PROBE555_TYPE=1,C_PROBE556_TYPE=1,C_PROBE557_TYPE=1,C_PROBE558_TYPE=1,C_PROBE559_TYPE=1,C_PROBE560_TYPE=1,C_PROBE561_TYPE=1,C_PROBE562_TYPE=1,C_PROBE563_TYPE=1,C_PROBE564_TYPE=1,C_PROBE565_TYPE=1,C_PROBE566_TYPE=1,C_PROBE567_TYPE=1,C_PROBE568_TYPE=1,C_PROBE569_TYPE=1,C_PROBE570_TYPE=1,C_PROBE571_TYPE=1,C_PROBE572_TYPE=1,C_PROBE573_TYPE=1,C_PROBE574_TYPE=1,C_PROBE575_TYPE=1,C_PROBE576_TYPE=1,C_PROBE577_TYPE=1,C_PROBE578_TYPE=1,C_PROBE579_TYPE=1,C_PROBE580_TYPE=1,C_PROBE581_TYPE=1,C_PROBE582_TYPE=1,C_PROBE583_TYPE=1,C_PROBE584_TYPE=1,C_PROBE585_TYPE=1,C_PROBE586_TYPE=1,C_PROBE587_TYPE=1,C_PROBE588_TYPE=1,C_PROBE589_TYPE=1,C_PROBE590_TYPE=1,C_PROBE591_TYPE=1,C_PROBE592_TYPE=1,C_PROBE593_TYPE=1,C_PROBE594_TYPE=1,C_PROBE595_TYPE=1,C_PROBE596_TYPE=1,C_PROBE597_TYPE=1,C_PROBE598_TYPE=1,C_PROBE599_TYPE=1,C_PROBE600_TYPE=1,C_PROBE601_TYPE=1,C_PROBE602_TYPE=1,C_PROBE603_TYPE=1,C_PROBE604_TYPE=1,C_PROBE605_TYPE=1,\\\nC_PROBE606_TYPE=1,C_PROBE607_TYPE=1,C_PROBE608_TYPE=1,C_PROBE609_TYPE=1,C_PROBE610_TYPE=1,C_PROBE611_TYPE=1,C_PROBE612_TYPE=1,C_PROBE613_TYPE=1,C_PROBE614_TYPE=1,C_PROBE615_TYPE=1,C_PROBE616_TYPE=1,C_PROBE617_TYPE=1,C_PROBE618_TYPE=1,C_PROBE619_TYPE=1,C_PROBE620_TYPE=1,C_PROBE621_TYPE=1,C_PROBE622_TYPE=1,C_PROBE623_TYPE=1,C_PROBE624_TYPE=1,C_PROBE625_TYPE=1,C_PROBE626_TYPE=1,C_PROBE627_TYPE=1,C_PROBE628_TYPE=1,C_PROBE629_TYPE=1,C_PROBE630_TYPE=1,C_PROBE631_TYPE=1,C_PROBE632_TYPE=1,C_PROBE633_TYPE=1,C_PROBE634_TYPE=1,C_PROBE635_TYPE=1,C_PROBE636_TYPE=1,C_PROBE637_TYPE=1,C_PROBE638_TYPE=1,C_PROBE639_TYPE=1,C_PROBE640_TYPE=1,C_PROBE641_TYPE=1,C_PROBE642_TYPE=1,C_PROBE643_TYPE=1,C_PROBE644_TYPE=1,C_PROBE645_TYPE=1,C_PROBE646_TYPE=1,C_PROBE647_TYPE=1,C_PROBE648_TYPE=1,C_PROBE649_TYPE=1,C_PROBE650_TYPE=1,C_PROBE651_TYPE=1,C_PROBE652_TYPE=1,C_PROBE653_TYPE=1,C_PROBE654_TYPE=1,C_PROBE655_TYPE=1,C_PROBE656_TYPE=1,C_PROBE657_TYPE=1,C_PROBE658_TYPE=1,C_PROBE659_TYPE=1,C_PROBE660_TYPE=1,C_PROBE661_TYPE=1,C_PROBE662_TYPE=1,C_PROBE663_TYPE=1,C_PROBE664_TYPE=1,C_PROBE665_TYPE=1,C_PROBE666_TYPE=1,C_PROBE667_TYPE=1,C_PROBE668_TYPE=1,C_PROBE669_TYPE=1,C_PROBE670_TYPE=1,C_PROBE671_TYPE=1,C_PROBE672_TYPE=1,C_PROBE673_TYPE=1,C_PROBE674_TYPE=1,C_PROBE675_TYPE=1,C_PROBE676_TYPE=1,C_PROBE677_TYPE=1,C_PROBE678_TYPE=1,C_PROBE679_TYPE=1,C_PROBE680_TYPE=1,C_PROBE681_TYPE=1,C_PROBE682_TYPE=1,C_PROBE683_TYPE=1,C_PROBE684_TYPE=1,C_PROBE685_TYPE=1,C_PROBE686_TYPE=1,C_PROBE687_TYPE=1,C_PROBE688_TYPE=1,C_PROBE689_TYPE=1,C_PROBE690_TYPE=1,C_PROBE691_TYPE=1,C_PROBE692_TYPE=1,C_PROBE693_TYPE=1,C_PROBE694_TYPE=1,C_PROBE695_TYPE=1,C_PROBE696_TYPE=1,C_PROBE697_TYPE=1,C_PROBE698_TYPE=1,C_PROBE699_TYPE=1,C_PROBE700_TYPE=1,C_PROBE701_TYPE=1,C_PROBE702_TYPE=1,C_PROBE703_TYPE=1,C_PROBE704_TYPE=1,C_PROBE705_TYPE=1,\\\nC_PROBE706_TYPE=1,C_PROBE707_TYPE=1,C_PROBE708_TYPE=1,C_PROBE709_TYPE=1,C_PROBE710_TYPE=1,C_PROBE711_TYPE=1,C_PROBE712_TYPE=1,C_PROBE713_TYPE=1,C_PROBE714_TYPE=1,C_PROBE715_TYPE=1,C_PROBE716_TYPE=1,C_PROBE717_TYPE=1,C_PROBE718_TYPE=1,C_PROBE719_TYPE=1,C_PROBE720_TYPE=1,C_PROBE721_TYPE=1,C_PROBE722_TYPE=1,C_PROBE723_TYPE=1,C_PROBE724_TYPE=1,C_PROBE725_TYPE=1,C_PROBE726_TYPE=1,C_PROBE727_TYPE=1,C_PROBE728_TYPE=1,C_PROBE729_TYPE=1,C_PROBE730_TYPE=1,C_PROBE731_TYPE=1,C_PROBE732_TYPE=1,C_PROBE733_TYPE=1,C_PROBE734_TYPE=1,C_PROBE735_TYPE=1,C_PROBE736_TYPE=1,C_PROBE737_TYPE=1,C_PROBE738_TYPE=1,C_PROBE739_TYPE=1,C_PROBE740_TYPE=1,C_PROBE741_TYPE=1,C_PROBE742_TYPE=1,C_PROBE743_TYPE=1,C_PROBE744_TYPE=1,C_PROBE745_TYPE=1,C_PROBE746_TYPE=1,C_PROBE747_TYPE=1,C_PROBE748_TYPE=1,C_PROBE749_TYPE=1,C_PROBE750_TYPE=1,C_PROBE751_TYPE=1,C_PROBE752_TYPE=1,C_PROBE753_TYPE=1,C_PROBE754_TYPE=1,C_PROBE755_TYPE=1,C_PROBE756_TYPE=1,C_PROBE757_TYPE=1,C_PROBE758_TYPE=1,C_PROBE759_TYPE=1,C_PROBE760_TYPE=1,C_PROBE761_TYPE=1,C_PROBE762_TYPE=1,C_PROBE763_TYPE=1,C_PROBE764_TYPE=1,C_PROBE765_TYPE=1,C_PROBE766_TYPE=1,C_PROBE767_TYPE=1,C_PROBE768_TYPE=1,C_PROBE769_TYPE=1,C_PROBE770_TYPE=1,C_PROBE771_TYPE=1,C_PROBE772_TYPE=1,C_PROBE773_TYPE=1,C_PROBE774_TYPE=1,C_PROBE775_TYPE=1,C_PROBE776_TYPE=1,C_PROBE777_TYPE=1,C_PROBE778_TYPE=1,C_PROBE779_TYPE=1,C_PROBE780_TYPE=1,C_PROBE781_TYPE=1,C_PROBE782_TYPE=1,C_PROBE783_TYPE=1,C_PROBE784_TYPE=1,C_PROBE785_TYPE=1,C_PROBE786_TYPE=1,C_PROBE787_TYPE=1,C_PROBE788_TYPE=1,C_PROBE789_TYPE=1,C_PROBE790_TYPE=1,C_PROBE791_TYPE=1,C_PROBE792_TYPE=1,C_PROBE793_TYPE=1,C_PROBE794_TYPE=1,C_PROBE795_TYPE=1,C_PROBE796_TYPE=1,C_PROBE797_TYPE=1,C_PROBE798_TYPE=1,C_PROBE799_TYPE=1,C_PROBE800_TYPE=1,C_PROBE801_TYPE=1,C_PROBE802_TYPE=1,C_PROBE803_TYPE=1,C_PROBE804_TYPE=1,C_PROBE805_TYPE=1,\\\nC_PROBE806_TYPE=1,C_PROBE807_TYPE=1,C_PROBE808_TYPE=1,C_PROBE809_TYPE=1,C_PROBE810_TYPE=1,C_PROBE811_TYPE=1,C_PROBE812_TYPE=1,C_PROBE813_TYPE=1,C_PROBE814_TYPE=1,C_PROBE815_TYPE=1,C_PROBE816_TYPE=1,C_PROBE817_TYPE=1,C_PROBE818_TYPE=1,C_PROBE819_TYPE=1,C_PROBE820_TYPE=1,C_PROBE821_TYPE=1,C_PROBE822_TYPE=1,C_PROBE823_TYPE=1,C_PROBE824_TYPE=1,C_PROBE825_TYPE=1,C_PROBE826_TYPE=1,C_PROBE827_TYPE=1,C_PROBE828_TYPE=1,C_PROBE829_TYPE=1,C_PROBE830_TYPE=1,C_PROBE831_TYPE=1,C_PROBE832_TYPE=1,C_PROBE833_TYPE=1,C_PROBE834_TYPE=1,C_PROBE835_TYPE=1,C_PROBE836_TYPE=1,C_PROBE837_TYPE=1,C_PROBE838_TYPE=1,C_PROBE839_TYPE=1,C_PROBE840_TYPE=1,C_PROBE841_TYPE=1,C_PROBE842_TYPE=1,C_PROBE843_TYPE=1,C_PROBE844_TYPE=1,C_PROBE845_TYPE=1,C_PROBE846_TYPE=1,C_PROBE847_TYPE=1,C_PROBE848_TYPE=1,C_PROBE849_TYPE=1,C_PROBE850_TYPE=1,C_PROBE851_TYPE=1,C_PROBE852_TYPE=1,C_PROBE853_TYPE=1,C_PROBE854_TYPE=1,C_PROBE855_TYPE=1,C_PROBE856_TYPE=1,C_PROBE857_TYPE=1,C_PROBE858_TYPE=1,C_PROBE859_TYPE=1,C_PROBE860_TYPE=1,C_PROBE861_TYPE=1,C_PROBE862_TYPE=1,C_PROBE863_TYPE=1,C_PROBE864_TYPE=1,C_PROBE865_TYPE=1,C_PROBE866_TYPE=1,C_PROBE867_TYPE=1,C_PROBE868_TYPE=1,C_PROBE869_TYPE=1,C_PROBE870_TYPE=1,C_PROBE871_TYPE=1,C_PROBE872_TYPE=1,C_PROBE873_TYPE=1,C_PROBE874_TYPE=1,C_PROBE875_TYPE=1,C_PROBE876_TYPE=1,C_PROBE877_TYPE=1,C_PROBE878_TYPE=1,C_PROBE879_TYPE=1,C_PROBE880_TYPE=1,C_PROBE881_TYPE=1,C_PROBE882_TYPE=1,C_PROBE883_TYPE=1,C_PROBE884_TYPE=1,C_PROBE885_TYPE=1,C_PROBE886_TYPE=1,C_PROBE887_TYPE=1,C_PROBE888_TYPE=1,C_PROBE889_TYPE=1,C_PROBE890_TYPE=1,C_PROBE891_TYPE=1,C_PROBE892_TYPE=1,C_PROBE893_TYPE=1,C_PROBE894_TYPE=1,C_PROBE895_TYPE=1,C_PROBE896_TYPE=1,C_PROBE897_TYPE=1,C_PROBE898_TYPE=1,C_PROBE899_TYPE=1,C_PROBE900_TYPE=1,C_PROBE901_TYPE=1,C_PROBE902_TYPE=1,C_PROBE903_TYPE=1,C_PROBE904_TYPE=1,C_PROBE905_TYPE=1,\\\nC_PROBE906_TYPE=1,C_PROBE907_TYPE=1,C_PROBE908_TYPE=1,C_PROBE909_TYPE=1,C_PROBE910_TYPE=1,C_PROBE911_TYPE=1,C_PROBE912_TYPE=1,C_PROBE913_TYPE=1,C_PROBE914_TYPE=1,C_PROBE915_TYPE=1,C_PROBE916_TYPE=1,C_PROBE917_TYPE=1,C_PROBE918_TYPE=1,C_PROBE919_TYPE=1,C_PROBE920_TYPE=1,C_PROBE921_TYPE=1,C_PROBE922_TYPE=1,C_PROBE923_TYPE=1,C_PROBE924_TYPE=1,C_PROBE925_TYPE=1,C_PROBE926_TYPE=1,C_PROBE927_TYPE=1,C_PROBE928_TYPE=1,C_PROBE929_TYPE=1,C_PROBE930_TYPE=1,C_PROBE931_TYPE=1,C_PROBE932_TYPE=1,C_PROBE933_TYPE=1,C_PROBE934_TYPE=1,C_PROBE935_TYPE=1,C_PROBE936_TYPE=1,C_PROBE937_TYPE=1,C_PROBE938_TYPE=1,C_PROBE939_TYPE=1,C_PROBE940_TYPE=1,C_PROBE941_TYPE=1,C_PROBE942_TYPE=1,C_PROBE943_TYPE=1,C_PROBE944_TYPE=1,C_PROBE945_TYPE=1,C_PROBE946_TYPE=1,C_PROBE947_TYPE=1,C_PROBE948_TYPE=1,C_PROBE949_TYPE=1,C_PROBE950_TYPE=1,C_PROBE951_TYPE=1,C_PROBE952_TYPE=1,C_PROBE953_TYPE=1,C_PROBE954_TYPE=1,C_PROBE955_TYPE=1,C_PROBE956_TYPE=1,C_PROBE957_TYPE=1,C_PROBE958_TYPE=1,C_PROBE959_TYPE=1,C_PROBE960_TYPE=1,C_PROBE961_TYPE=1,C_PROBE962_TYPE=1,C_PROBE963_TYPE=1,C_PROBE964_TYPE=1,C_PROBE965_TYPE=1,C_PROBE966_TYPE=1,C_PROBE967_TYPE=1,C_PROBE968_TYPE=1,C_PROBE969_TYPE=1,C_PROBE970_TYPE=1,C_PROBE971_TYPE=1,C_PROBE972_TYPE=1,C_PROBE973_TYPE=1,C_PROBE974_TYPE=1,C_PROBE975_TYPE=1,C_PROBE976_TYPE=1,C_PROBE977_TYPE=1,C_PROBE978_TYPE=1,C_PROBE979_TYPE=1,C_PROBE980_TYPE=1,C_PROBE981_TYPE=1,C_PROBE982_TYPE=1,C_PROBE983_TYPE=1,C_PROBE984_TYPE=1,C_PROBE985_TYPE=1,C_PROBE986_TYPE=1,C_PROBE987_TYPE=1,C_PROBE988_TYPE=1,C_PROBE989_TYPE=1,C_PROBE990_TYPE=1,C_PROBE991_TYPE=1,C_PROBE992_TYPE=1,C_PROBE993_TYPE=1,C_PROBE994_TYPE=1,C_PROBE995_TYPE=1,C_PROBE996_TYPE=1,C_PROBE997_TYPE=1,C_PROBE998_TYPE=1,C_PROBE999_TYPE=1,C_PROBE1000_TYPE=1,C_PROBE1001_TYPE=1,C_PROBE1002_TYPE=1,C_PROBE1003_TYPE=1,C_PROBE1004_TYPE=1,C_PROBE1005_TYPE=1,\\\nC_PROBE1006_TYPE=1,C_PROBE1007_TYPE=1,C_PROBE1008_TYPE=1,C_PROBE1009_TYPE=1,C_PROBE1010_TYPE=1,C_PROBE1011_TYPE=1,C_PROBE1012_TYPE=1,C_PROBE1013_TYPE=1,C_PROBE1014_TYPE=1,C_PROBE1015_TYPE=1,C_PROBE1016_TYPE=1,C_PROBE1017_TYPE=1,C_PROBE1018_TYPE=1,C_PROBE1019_TYPE=1,C_PROBE1020_TYPE=1,C_PROBE1021_TYPE=1,C_PROBE1022_TYPE=1,C_PROBE1023_TYPE=1}\" *)\n\nmodule ila_0 (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [63 : 0] probe1;\ninput [0 : 0] probe2;\ninput [0 : 0] probe3;\ninput [63 : 0] probe4;\ninput [0 : 0] probe5;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_5_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(6),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2017),\n.C_MINOR_VERSION(4),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(0),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(4),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH (32),\n.C_ILA_CLK_FREQ(2000000),\n.C_PROBE0_WIDTH(1),\n.C_PROBE1_WIDTH(64),\n.C_PROBE2_WIDTH(1),\n.C_PROBE3_WIDTH(1),\n.C_PROBE4_WIDTH(64),\n.C_PROBE5_WIDTH(1),\n.C_PROBE6_WIDTH(1),\n.C_PROBE7_WIDTH(1),\n.C_PROBE8_WIDTH(1),\n.C_PROBE9_WIDTH(1),\n.C_PROBE10_WIDTH(1),\n.C_PROBE11_WIDTH(1),\n.C_PROBE12_WIDTH(1),\n.C_PROBE13_WIDTH(1),\n.C_PROBE14_WIDTH(1),\n.C_PROBE15_WIDTH(1),\n.C_PROBE16_WIDTH(1),\n.C_PROBE17_WIDTH(1),\n.C_PROBE18_WIDTH(1),\n.C_PROBE19_WIDTH(1),\n.C_PROBE20_WIDTH(1),\n.C_PROBE21_WIDTH(1),\n.C_PROBE22_WIDTH(1),\n.C_PROBE23_WIDTH(1),\n.C_PROBE24_WIDTH(1),\n.C_PROBE25_WIDTH(1),\n.C_PROBE26_WIDTH(1),\n.C_PROBE27_WIDTH(1),\n.C_PROBE28_WIDTH(1),\n.C_PROBE29_WIDTH(1),\n.C_PROBE30_WIDTH(1),\n.C_PROBE31_WIDTH(1),\n.C_PROBE32_WIDTH(1),\n.C_PROBE33_WIDTH(1),\n.C_PROBE34_WIDTH(1),\n.C_PROBE35_WIDTH(1),\n.C_PROBE36_WIDTH(1),\n.C_PROBE37_WIDTH(1),\n.C_PROBE38_WIDTH(1),\n.C_PROBE39_WIDTH(1),\n.C_PROBE40_WIDTH(1),\n.C_PROBE41_WIDTH(1),\n.C_PROBE42_WIDTH(1),\n.C_PROBE43_WIDTH(1),\n.C_PROBE44_WIDTH(1),\n.C_PROBE45_WIDTH(1),\n.C_PROBE46_WIDTH(1),\n.C_PROBE47_WIDTH(1),\n.C_PROBE48_WIDTH(1),\n.C_PROBE49_WIDTH(1),\n.C_PROBE50_WIDTH(1),\n.C_PROBE51_WIDTH(1),\n.C_PROBE52_WIDTH(1),\n.C_PROBE53_WIDTH(1),\n.C_PROBE54_WIDTH(1),\n.C_PROBE55_WIDTH(1),\n.C_PROBE56_WIDTH(1),\n.C_PROBE57_WIDTH(1),\n.C_PROBE58_WIDTH(1),\n.C_PROBE59_WIDTH(1),\n.C_PROBE60_WIDTH(1),\n.C_PROBE61_WIDTH(1),\n.C_PROBE62_WIDTH(1),\n.C_PROBE63_WIDTH(1),\n.C_PROBE64_WIDTH(1),\n.C_PROBE65_WIDTH(1),\n.C_PROBE66_WIDTH(1),\n.C_PROBE67_WIDTH(1),\n.C_PROBE68_WIDTH(1),\n.C_PROBE69_WIDTH(1),\n.C_PROBE70_WIDTH(1),\n.C_PROBE71_WIDTH(1),\n.C_PROBE72_WIDTH(1),\n.C_PROBE73_WIDTH(1),\n.C_PROBE74_WIDTH(1),\n.C_PROBE75_WIDTH(1),\n.C_PROBE76_WIDTH(1),\n.C_PROBE77_WIDTH(1),\n.C_PROBE78_WIDTH(1),\n.C_PROBE79_WIDTH(1),\n.C_PROBE80_WIDTH(1),\n.C_PROBE81_WIDTH(1),\n.C_PROBE82_WIDTH(1),\n.C_PROBE83_WIDTH(1),\n.C_PROBE84_WIDTH(1),\n.C_PROBE85_WIDTH(1),\n.C_PROBE86_WIDTH(1),\n.C_PROBE87_WIDTH(1),\n.C_PROBE88_WIDTH(1),\n.C_PROBE89_WIDTH(1),\n.C_PROBE90_WIDTH(1),\n.C_PROBE91_WIDTH(1),\n.C_PROBE92_WIDTH(1),\n.C_PROBE93_WIDTH(1),\n.C_PROBE94_WIDTH(1),\n.C_PROBE95_WIDTH(1),\n.C_PROBE96_WIDTH(1),\n.C_PROBE97_WIDTH(1),\n.C_PROBE98_WIDTH(1),\n.C_PROBE99_WIDTH(1),\n.C_PROBE100_WIDTH(1),\n.C_PROBE101_WIDTH(1),\n.C_PROBE102_WIDTH(1),\n.C_PROBE103_WIDTH(1),\n.C_PROBE104_WIDTH(1),\n.C_PROBE105_WIDTH(1),\n.C_PROBE106_WIDTH(1),\n.C_PROBE107_WIDTH(1),\n.C_PROBE108_WIDTH(1),\n.C_PROBE109_WIDTH(1),\n.C_PROBE110_WIDTH(1),\n.C_PROBE111_WIDTH(1),\n.C_PROBE112_WIDTH(1),\n.C_PROBE113_WIDTH(1),\n.C_PROBE114_WIDTH(1),\n.C_PROBE115_WIDTH(1),\n.C_PROBE116_WIDTH(1),\n.C_PROBE117_WIDTH(1),\n.C_PROBE118_WIDTH(1),\n.C_PROBE119_WIDTH(1),\n.C_PROBE120_WIDTH(1),\n.C_PROBE121_WIDTH(1),\n.C_PROBE122_WIDTH(1),\n.C_PROBE123_WIDTH(1),\n.C_PROBE124_WIDTH(1),\n.C_PROBE125_WIDTH(1),\n.C_PROBE126_WIDTH(1),\n.C_PROBE127_WIDTH(1),\n.C_PROBE128_WIDTH(1),\n.C_PROBE129_WIDTH(1),\n.C_PROBE130_WIDTH(1),\n.C_PROBE131_WIDTH(1),\n.C_PROBE132_WIDTH(1),\n.C_PROBE133_WIDTH(1),\n.C_PROBE134_WIDTH(1),\n.C_PROBE135_WIDTH(1),\n.C_PROBE136_WIDTH(1),\n.C_PROBE137_WIDTH(1),\n.C_PROBE138_WIDTH(1),\n.C_PROBE139_WIDTH(1),\n.C_PROBE140_WIDTH(1),\n.C_PROBE141_WIDTH(1),\n.C_PROBE142_WIDTH(1),\n.C_PROBE143_WIDTH(1),\n.C_PROBE144_WIDTH(1),\n.C_PROBE145_WIDTH(1),\n.C_PROBE146_WIDTH(1),\n.C_PROBE147_WIDTH(1),\n.C_PROBE148_WIDTH(1),\n.C_PROBE149_WIDTH(1),\n.C_PROBE150_WIDTH(1),\n.C_PROBE151_WIDTH(1),\n.C_PROBE152_WIDTH(1),\n.C_PROBE153_WIDTH(1),\n.C_PROBE154_WIDTH(1),\n.C_PROBE155_WIDTH(1),\n.C_PROBE156_WIDTH(1),\n.C_PROBE157_WIDTH(1),\n.C_PROBE158_WIDTH(1),\n.C_PROBE159_WIDTH(1),\n.C_PROBE160_WIDTH(1),\n.C_PROBE161_WIDTH(1),\n.C_PROBE162_WIDTH(1),\n.C_PROBE163_WIDTH(1),\n.C_PROBE164_WIDTH(1),\n.C_PROBE165_WIDTH(1),\n.C_PROBE166_WIDTH(1),\n.C_PROBE167_WIDTH(1),\n.C_PROBE168_WIDTH(1),\n.C_PROBE169_WIDTH(1),\n.C_PROBE170_WIDTH(1),\n.C_PROBE171_WIDTH(1),\n.C_PROBE172_WIDTH(1),\n.C_PROBE173_WIDTH(1),\n.C_PROBE174_WIDTH(1),\n.C_PROBE175_WIDTH(1),\n.C_PROBE176_WIDTH(1),\n.C_PROBE177_WIDTH(1),\n.C_PROBE178_WIDTH(1),\n.C_PROBE179_WIDTH(1),\n.C_PROBE180_WIDTH(1),\n.C_PROBE181_WIDTH(1),\n.C_PROBE182_WIDTH(1),\n.C_PROBE183_WIDTH(1),\n.C_PROBE184_WIDTH(1),\n.C_PROBE185_WIDTH(1),\n.C_PROBE186_WIDTH(1),\n.C_PROBE187_WIDTH(1),\n.C_PROBE188_WIDTH(1),\n.C_PROBE189_WIDTH(1),\n.C_PROBE190_WIDTH(1),\n.C_PROBE191_WIDTH(1),\n.C_PROBE192_WIDTH(1),\n.C_PROBE193_WIDTH(1),\n.C_PROBE194_WIDTH(1),\n.C_PROBE195_WIDTH(1),\n.C_PROBE196_WIDTH(1),\n.C_PROBE197_WIDTH(1),\n.C_PROBE198_WIDTH(1),\n.C_PROBE199_WIDTH(1),\n.C_PROBE200_WIDTH(1),\n.C_PROBE201_WIDTH(1),\n.C_PROBE202_WIDTH(1),\n.C_PROBE203_WIDTH(1),\n.C_PROBE204_WIDTH(1),\n.C_PROBE205_WIDTH(1),\n.C_PROBE206_WIDTH(1),\n.C_PROBE207_WIDTH(1),\n.C_PROBE208_WIDTH(1),\n.C_PROBE209_WIDTH(1),\n.C_PROBE210_WIDTH(1),\n.C_PROBE211_WIDTH(1),\n.C_PROBE212_WIDTH(1),\n.C_PROBE213_WIDTH(1),\n.C_PROBE214_WIDTH(1),\n.C_PROBE215_WIDTH(1),\n.C_PROBE216_WIDTH(1),\n.C_PROBE217_WIDTH(1),\n.C_PROBE218_WIDTH(1),\n.C_PROBE219_WIDTH(1),\n.C_PROBE220_WI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_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT(1),\n.C_PROBE275_MU_CNT(1),\n.C_PROBE276_MU_CNT(1),\n.C_PROBE277_MU_CNT(1),\n.C_PROBE278_MU_CNT(1),\n.C_PROBE279_MU_CNT(1),\n.C_PROBE280_MU_CNT(1),\n.C_PROBE281_MU_CNT(1),\n.C_PROBE282_MU_CNT(1),\n.C_PROBE283_MU_CNT(1),\n.C_PROBE284_MU_CNT(1),\n.C_PROBE285_MU_CNT(1),\n.C_PROBE286_MU_CNT(1),\n.C_PROBE287_MU_CNT(1),\n.C_PROBE288_MU_CNT(1),\n.C_PROBE289_MU_CNT(1),\n.C_PROBE290_MU_CNT(1),\n.C_PROBE291_MU_CNT(1),\n.C_PROBE292_MU_CNT(1),\n.C_PROBE293_MU_CNT(1),\n.C_PROBE294_MU_CNT(1),\n.C_PROBE295_MU_CNT(1),\n.C_PROBE296_MU_CNT(1),\n.C_PROBE297_MU_CNT(1),\n.C_PROBE298_MU_CNT(1),\n.C_PROBE299_MU_CNT(1),\n.C_PROBE300_MU_CNT(1),\n.C_PROBE301_MU_CNT(1),\n.C_PROBE302_MU_CNT(1),\n.C_PROBE303_MU_CNT(1),\n.C_PROBE304_MU_CNT(1),\n.C_PROBE305_MU_CNT(1),\n.C_PROBE306_MU_CNT(1),\n.C_PROBE307_MU_CNT(1),\n.C_PROBE308_MU_CNT(1),\n.C_PROBE309_MU_CNT(1),\n.C_PROBE310_MU_CNT(1),\n.C_PROBE311_MU_CNT(1),\n.C_PROBE312_MU_CNT(1),\n.C_PROBE313_MU_CNT(1),\n.C_PROBE314_MU_CNT(1),\n.C_PROBE315_MU_CNT(1),\n.C_PROBE316_MU_CNT(1),\n.C_PROBE317_MU_CNT(1),\n.C_PROBE318_MU_CNT(1),\n.C_PROBE319_MU_CNT(1),\n.C_PROBE320_MU_CNT(1),\n.C_PROBE321_MU_CNT(1),\n.C_PROBE322_MU_CNT(1),\n.C_PROBE323_MU_CNT(1),\n.C_PROBE324_MU_CNT(1),\n.C_PROBE325_MU_CNT(1),\n.C_PROBE326_MU_CNT(1),\n.C_PROBE327_MU_CNT(1),\n.C_PROBE328_MU_CNT(1),\n.C_PROBE329_MU_CNT(1),\n.C_PROBE330_MU_CNT(1),\n.C_PROBE331_MU_CNT(1),\n.C_PROBE332_MU_CNT(1),\n.C_PROBE333_MU_CNT(1),\n.C_PROBE334_MU_CNT(1),\n.C_PROBE335_MU_CNT(1),\n.C_PROBE336_MU_CNT(1),\n.C_PROBE337_MU_CNT(1),\n.C_PROBE338_MU_CNT(1),\n.C_PROBE339_MU_CNT(1),\n.C_PROBE340_MU_CNT(1),\n.C_PROBE341_MU_CNT(1),\n.C_PROBE342_MU_CNT(1),\n.C_PROBE343_MU_CNT(1),\n.C_PROBE344_MU_CNT(1),\n.C_PROBE345_MU_CNT(1),\n.C_PROBE346_MU_CNT(1),\n.C_PROBE347_MU_CNT(1),\n.C_PROBE348_MU_CNT(1),\n.C_PROBE349_MU_CNT(1),\n.C_PROBE350_MU_CNT(1),\n.C_PROBE351_MU_CNT(1),\n.C_PROBE352_MU_CNT(1),\n.C_PROBE353_MU_CNT(1),\n.C_PROBE354_MU_CNT(1),\n.C_PROBE355_MU_CNT(1),\n.C_PROBE356_MU_CNT(1),\n.C_PROBE357_MU_CNT(1),\n.C_PROBE358_MU_CNT(1),\n.C_PROBE359_MU_CNT(1),\n.C_PROBE360_MU_CNT(1),\n.C_PROBE361_MU_CNT(1),\n.C_PROBE362_MU_CNT(1),\n.C_PROBE363_MU_CNT(1),\n.C_PROBE364_MU_CNT(1),\n.C_PROBE365_MU_CNT(1),\n.C_PROBE366_MU_CNT(1),\n.C_PROBE367_MU_CNT(1),\n.C_PROBE368_MU_CNT(1),\n.C_PROBE369_MU_CNT(1),\n.C_PROBE370_MU_CNT(1),\n.C_PROBE371_MU_CNT(1),\n.C_PROBE372_MU_CNT(1),\n.C_PROBE373_MU_CNT(1),\n.C_PROBE374_MU_CNT(1),\n.C_PROBE375_MU_CNT(1),\n.C_PROBE376_MU_CNT(1),\n.C_PROBE377_MU_CNT(1),\n.C_PROBE378_MU_CNT(1),\n.C_PROBE379_MU_CNT(1),\n.C_PROBE380_MU_CNT(1),\n.C_PROBE381_MU_CNT(1),\n.C_PROBE382_MU_CNT(1),\n.C_PROBE383_MU_CNT(1),\n.C_PROBE384_MU_CNT(1),\n.C_PROBE385_MU_CNT(1),\n.C_PROBE386_MU_CNT(1),\n.C_PROBE387_MU_CNT(1),\n.C_PROBE388_MU_CNT(1),\n.C_PROBE389_MU_CNT(1),\n.C_PROBE390_MU_CNT(1),\n.C_PROBE391_MU_CNT(1),\n.C_PROBE392_MU_CNT(1),\n.C_PROBE393_MU_CNT(1),\n.C_PROBE394_MU_CNT(1),\n.C_PROBE395_MU_CNT(1),\n.C_PROBE396_MU_CNT(1),\n.C_PROBE397_MU_CNT(1),\n.C_PROBE398_MU_CNT(1),\n.C_PROBE399_MU_CNT(1),\n.C_PROBE400_MU_CNT(1),\n.C_PROBE401_MU_CNT(1),\n.C_PROBE402_MU_CNT(1),\n.C_PROBE403_MU_CNT(1),\n.C_PROBE404_MU_CNT(1),\n.C_PROBE405_MU_CNT(1),\n.C_PROBE406_MU_CNT(1),\n.C_PROBE407_MU_CNT(1),\n.C_PROBE408_MU_CNT(1),\n.C_PROBE409_MU_CNT(1),\n.C_PROBE410_MU_CNT(1),\n.C_PROBE411_MU_CNT(1),\n.C_PROBE412_MU_CNT(1),\n.C_PROBE413_MU_CNT(1),\n.C_PROBE414_MU_CNT(1),\n.C_PROBE415_MU_CNT(1),\n.C_PROBE416_MU_CNT(1),\n.C_PROBE417_MU_CNT(1),\n.C_PROBE418_MU_CNT(1),\n.C_PROBE419_MU_CNT(1),\n.C_PROBE420_MU_CNT(1),\n.C_PROBE421_MU_CNT(1),\n.C_PROBE422_MU_CNT(1),\n.C_PROBE423_MU_CNT(1),\n.C_PROBE424_MU_CNT(1),\n.C_PROBE425_MU_CNT(1),\n.C_PROBE426_MU_CNT(1),\n.C_PROBE427_MU_CNT(1),\n.C_PROBE428_MU_CNT(1),\n.C_PROBE429_MU_CNT(1),\n.C_PROBE430_MU_CNT(1),\n.C_PROBE431_MU_CNT(1),\n.C_PROBE432_MU_CNT(1),\n.C_PROBE433_MU_CNT(1),\n.C_PROBE434_MU_CNT(1),\n.C_PROBE435_MU_CNT(1),\n.C_PROBE436_MU_CNT(1),\n.C_PROBE437_MU_CNT(1),\n.C_PROBE438_MU_CNT(1),\n.C_PROBE439_MU_CNT(1),\n.C_PROBE440_MU_CNT(1),\n.C_PROBE441_MU_CNT(1),\n.C_PROBE442_MU_CNT(1),\n.C_PROBE443_MU_CNT(1),\n.C_PROBE444_MU_CNT(1),\n.C_PROBE445_MU_CNT(1),\n.C_PROBE446_MU_CNT(1),\n.C_PROBE447_MU_CNT(1),\n.C_PROBE448_MU_CNT(1),\n.C_PROBE449_MU_CNT(1),\n.C_PROBE450_MU_CNT(1),\n.C_PROBE451_MU_CNT(1),\n.C_PROBE452_MU_CNT(1),\n.C_PROBE453_MU_CNT(1),\n.C_PROBE454_MU_CNT(1),\n.C_PROBE455_MU_CNT(1),\n.C_PROBE456_MU_CNT(1),\n.C_PROBE457_MU_CNT(1),\n.C_PROBE458_MU_CNT(1),\n.C_PROBE459_MU_CNT(1),\n.C_PROBE460_MU_CNT(1),\n.C_PROBE461_MU_CNT(1),\n.C_PROBE462_MU_CNT(1),\n.C_PROBE463_MU_CNT(1),\n.C_PROBE464_MU_CNT(1),\n.C_PROBE465_MU_CNT(1),\n.C_PROBE466_MU_CNT(1),\n.C_PROBE467_MU_CNT(1),\n.C_PROBE468_MU_CNT(1),\n.C_PROBE469_MU_CNT(1),\n.C_PROBE470_MU_CNT(1),\n.C_PROBE471_MU_CNT(1),\n.C_PROBE472_MU_CNT(1),\n.C_PROBE473_MU_CNT(1),\n.C_PROBE474_MU_CNT(1),\n.C_PROBE475_MU_CNT(1),\n.C_PROBE476_MU_CNT(1),\n.C_PROBE477_MU_CNT(1),\n.C_PROBE478_MU_CNT(1),\n.C_PROBE479_MU_CNT(1),\n.C_PROBE480_MU_CNT(1),\n.C_PROBE481_MU_CNT(1),\n.C_PROBE482_MU_CNT(1),\n.C_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1),\n.C_PROBE691_MU_CNT(1),\n.C_PROBE692_MU_CNT(1),\n.C_PROBE693_MU_CNT(1),\n.C_PROBE694_MU_CNT(1),\n.C_PROBE695_MU_CNT(1),\n.C_PROBE696_MU_CNT(1),\n.C_PROBE697_MU_CNT(1),\n.C_PROBE698_MU_CNT(1),\n.C_PROBE699_MU_CNT(1),\n.C_PROBE700_MU_CNT(1),\n.C_PROBE701_MU_CNT(1),\n.C_PROBE702_MU_CNT(1),\n.C_PROBE703_MU_CNT(1),\n.C_PROBE704_MU_CNT(1),\n.C_PROBE705_MU_CNT(1),\n.C_PROBE706_MU_CNT(1),\n.C_PROBE707_MU_CNT(1),\n.C_PROBE708_MU_CNT(1),\n.C_PROBE709_MU_CNT(1),\n.C_PROBE710_MU_CNT(1),\n.C_PROBE711_MU_CNT(1),\n.C_PROBE712_MU_CNT(1),\n.C_PROBE713_MU_CNT(1),\n.C_PROBE714_MU_CNT(1),\n.C_PROBE715_MU_CNT(1),\n.C_PROBE716_MU_CNT(1),\n.C_PROBE717_MU_CNT(1),\n.C_PROBE718_MU_CNT(1),\n.C_PROBE719_MU_CNT(1),\n.C_PROBE720_MU_CNT(1),\n.C_PROBE721_MU_CNT(1),\n.C_PROBE722_MU_CNT(1),\n.C_PROBE723_MU_CNT(1),\n.C_PROBE724_MU_CNT(1),\n.C_PROBE725_MU_CNT(1),\n.C_PROBE726_MU_CNT(1),\n.C_PROBE727_MU_CNT(1),\n.C_PROBE728_MU_CNT(1),\n.C_PROBE729_MU_CNT(1),\n.C_PROBE730_MU_CNT(1),\n.C_PROBE731_MU_CNT(1),\n.C_PROBE732_MU_CNT(1),\n.C_PROBE733_MU_CNT(1),\n.C_PROBE734_MU_CNT(1),\n.C_PROBE735_MU_CNT(1),\n.C_PROBE736_MU_CNT(1),\n.C_PROBE737_MU_CNT(1),\n.C_PROBE738_MU_CNT(1),\n.C_PROBE739_MU_CNT(1),\n.C_PROBE740_MU_CNT(1),\n.C_PROBE741_MU_CNT(1),\n.C_PROBE742_MU_CNT(1),\n.C_PROBE743_MU_CNT(1),\n.C_PROBE744_MU_CNT(1),\n.C_PROBE745_MU_CNT(1),\n.C_PROBE746_MU_CNT(1),\n.C_PROBE747_MU_CNT(1),\n.C_PROBE748_MU_CNT(1),\n.C_PROBE749_MU_CNT(1),\n.C_PROBE750_MU_CNT(1),\n.C_PROBE751_MU_CNT(1),\n.C_PROBE752_MU_CNT(1),\n.C_PROBE753_MU_CNT(1),\n.C_PROBE754_MU_CNT(1),\n.C_PROBE755_MU_CNT(1),\n.C_PROBE756_MU_CNT(1),\n.C_PROBE757_MU_CNT(1),\n.C_PROBE758_MU_CNT(1),\n.C_PROBE759_MU_CNT(1),\n.C_PROBE760_MU_CNT(1),\n.C_PROBE761_MU_CNT(1),\n.C_PROBE762_MU_CNT(1),\n.C_PROBE763_MU_CNT(1),\n.C_PROBE764_MU_CNT(1),\n.C_PROBE765_MU_CNT(1),\n.C_PROBE766_MU_CNT(1),\n.C_PROBE767_MU_CNT(1),\n.C_PROBE768_MU_CNT(1),\n.C_PROBE769_MU_CNT(1),\n.C_PROBE770_MU_CNT(1),\n.C_PROBE771_MU_CNT(1),\n.C_PROBE772_MU_CNT(1),\n.C_PROBE773_MU_CNT(1),\n.C_PROBE774_MU_CNT(1),\n.C_PROBE775_MU_CNT(1),\n.C_PROBE776_MU_CNT(1),\n.C_PROBE777_MU_CNT(1),\n.C_PROBE778_MU_CNT(1),\n.C_PROBE779_MU_CNT(1),\n.C_PROBE780_MU_CNT(1),\n.C_PROBE781_MU_CNT(1),\n.C_PROBE782_MU_CNT(1),\n.C_PROBE783_MU_CNT(1),\n.C_PROBE784_MU_CNT(1),\n.C_PROBE785_MU_CNT(1),\n.C_PROBE786_MU_CNT(1),\n.C_PROBE787_MU_CNT(1),\n.C_PROBE788_MU_CNT(1),\n.C_PROBE789_MU_CNT(1),\n.C_PROBE790_MU_CNT(1),\n.C_PROBE791_MU_CNT(1),\n.C_PROBE792_MU_CNT(1),\n.C_PROBE793_MU_CNT(1),\n.C_PROBE794_MU_CNT(1),\n.C_PROBE795_MU_CNT(1),\n.C_PROBE796_MU_CNT(1),\n.C_PROBE797_MU_CNT(1),\n.C_PROBE798_MU_CNT(1),\n.C_PROBE799_MU_CNT(1),\n.C_PROBE800_MU_CNT(1),\n.C_PROBE801_MU_CNT(1),\n.C_PROBE802_MU_CNT(1),\n.C_PROBE803_MU_CNT(1),\n.C_PROBE804_MU_CNT(1),\n.C_PROBE805_MU_CNT(1),\n.C_PROBE806_MU_CNT(1),\n.C_PROBE807_MU_CNT(1),\n.C_PROBE808_MU_CNT(1),\n.C_PROBE809_MU_CNT(1),\n.C_PROBE810_MU_CNT(1),\n.C_PROBE811_MU_CNT(1),\n.C_PROBE812_MU_CNT(1),\n.C_PROBE813_MU_CNT(1),\n.C_PROBE814_MU_CNT(1),\n.C_PROBE815_MU_CNT(1),\n.C_PROBE816_MU_CNT(1),\n.C_PROBE817_MU_CNT(1),\n.C_PROBE818_MU_CNT(1),\n.C_PROBE819_MU_CNT(1),\n.C_PROBE820_MU_CNT(1),\n.C_PROBE821_MU_CNT(1),\n.C_PROBE822_MU_CNT(1),\n.C_PROBE823_MU_CNT(1),\n.C_PROBE824_MU_CNT(1),\n.C_PROBE825_MU_CNT(1),\n.C_PROBE826_MU_CNT(1),\n.C_PROBE827_MU_CNT(1),\n.C_PROBE828_MU_CNT(1),\n.C_PROBE829_MU_CNT(1),\n.C_PROBE830_MU_CNT(1),\n.C_PROBE831_MU_CNT(1),\n.C_PROBE832_MU_CNT(1),\n.C_PROBE833_MU_CNT(1),\n.C_PROBE834_MU_CNT(1),\n.C_PROBE835_MU_CNT(1),\n.C_PROBE836_MU_CNT(1),\n.C_PROBE837_MU_CNT(1),\n.C_PROBE838_MU_CNT(1),\n.C_PROBE839_MU_CNT(1),\n.C_PROBE840_MU_CNT(1),\n.C_PROBE841_MU_CNT(1),\n.C_PROBE842_MU_CNT(1),\n.C_PROBE843_MU_CNT(1),\n.C_PROBE844_MU_CNT(1),\n.C_PROBE845_MU_CNT(1),\n.C_PROBE846_MU_CNT(1),\n.C_PROBE847_MU_CNT(1),\n.C_PROBE848_MU_CNT(1),\n.C_PROBE849_MU_CNT(1),\n.C_PROBE850_MU_CNT(1),\n.C_PROBE851_MU_CNT(1),\n.C_PROBE852_MU_CNT(1),\n.C_PROBE853_MU_CNT(1),\n.C_PROBE854_MU_CNT(1),\n.C_PROBE855_MU_CNT(1),\n.C_PROBE856_MU_CNT(1),\n.C_PROBE857_MU_CNT(1),\n.C_PROBE858_MU_CNT(1),\n.C_PROBE859_MU_CNT(1),\n.C_PROBE860_MU_CNT(1),\n.C_PROBE861_MU_CNT(1),\n.C_PROBE862_MU_CNT(1),\n.C_PROBE863_MU_CNT(1),\n.C_PROBE864_MU_CNT(1),\n.C_PROBE865_MU_CNT(1),\n.C_PROBE866_MU_CNT(1),\n.C_PROBE867_MU_CNT(1),\n.C_PROBE868_MU_CNT(1),\n.C_PROBE869_MU_CNT(1),\n.C_PROBE870_MU_CNT(1),\n.C_PROBE871_MU_CNT(1),\n.C_PROBE872_MU_CNT(1),\n.C_PROBE873_MU_CNT(1),\n.C_PROBE874_MU_CNT(1),\n.C_PROBE875_MU_CNT(1),\n.C_PROBE876_MU_CNT(1),\n.C_PROBE877_MU_CNT(1),\n.C_PROBE878_MU_CNT(1),\n.C_PROBE879_MU_CNT(1),\n.C_PROBE880_MU_CNT(1),\n.C_PROBE881_MU_CNT(1),\n.C_PROBE882_MU_CNT(1),\n.C_PROBE883_MU_CNT(1),\n.C_PROBE884_MU_CNT(1),\n.C_PROBE885_MU_CNT(1),\n.C_PROBE886_MU_CNT(1),\n.C_PROBE887_MU_CNT(1),\n.C_PROBE888_MU_CNT(1),\n.C_PROBE889_MU_CNT(1),\n.C_PROBE890_MU_CNT(1),\n.C_PROBE891_MU_CNT(1),\n.C_PROBE892_MU_CNT(1),\n.C_PROBE893_MU_CNT(1),\n.C_PROBE894_MU_CNT(1),\n.C_PROBE895_MU_CNT(1),\n.C_PROBE896_MU_CNT(1),\n.C_PROBE897_MU_CNT(1),\n.C_PROBE898_MU_CNT(1),\n.C_PROBE899_MU_CNT(1),\n.C_PROBE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synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4251}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nYugOLIF1XBreTDYRaNSWelgjmV3GIQ3y7FKiDB9UiIB++fAUC4TXcrfthfgN8befqwACkO3Q4k0c\nvJxv/aokgQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nP86BhFBNNa0qr9Q2+Wo0KACiIyDg4VPZdSis8bLUVn6FrcCD6TyMD6qWsX7GqSzkSyajfw5KoNS5\nrAZcRWAMv14anbm7VDJCIblrxr97wW1wDK0tJz6KsyHENdmS+W0PhSl0PyC6LE8TbUq4mev1WMPa\ne8qt1TLduNZhmfYNEEg=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\ngWBenVTIP5Q+rcNXfn1zPEjuUtszskvpUVNF25Xh81JnRdMPCp/0AGJPx+mPKwQ62keEUCK7jImu\n0uCqq7uEhg8CAhGkckxz0ziMi5p3crim/FOPfZSxzcfVA0myImyw/jA25kK2gqWItxmETSoXCqJJ\nxjTH/Kdlxzn5v3BlGFnjUMmgDpw+7ZlRLWclsVDPWcyttlqzmOpUVNRybjmRjQ047dZKoaEnV7aL\nJadzAQ1SqJzBdkDtBC4ls9rDZ0efLPq2CaHSH2lKmJWzqvjdbahTe/uDqwZlM/3ri9uvioLaock3\nBYN0ATxKAINgg8QSBFGOvETVtbNj0tmio/74Jg==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUA332GmFKmVHrrGry7Cyuflehk/VbtxlBHEATtE4ZDxpaTPEmq4fqpuW3/eIdDceGsGBiaQuMN9K\nWHRjmvo00KBUbhMYtfB1gjlmZEboE2pGVM53sCnoWcRuUcFptlHy3SPD43x91G4s/5AG3W+1+WfG\ndqqfUNJVltc7+nD/QSz52JWyt2BKcwXzXUegWHFyWPlXXyRha6uiHm5A3aFVX9XSCQMUBVg9KOgQ\nr17LLKqYda/v6o1fu2DbIpPXqeviObYOGtxIlZlCKEQ0WQ16wVhC7M7JMUM8K1ajQIP6aFm+lH0T\nT0TAEilCZfV2IBv8ZeVngUGkozMdcE2q607VAg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nJkclL4oQ89VKThgpnFORp4DkQ+l+oHyNRU+cUXBcYSussbqYTJL6YmJORdubTTO26u6Gzu7Zi8eR\nCof7Krp+GgFdv/lyHLisqmpxJDZ7fQJTFSmWQ1sN09PbMajgp5uypgG17Qqsv6Efx7DaBK5bWBFL\nzYY4TfY8F27SWO7q+F4ZXrJVV+ljd3jMxOp0CO33BlH7VTdJmnHbnGwVoy7NS7ktTu5O4mtjSy5B\nim8NDWKOPmwonslxiaCWWhRcIUWJMoS3RW+hbISleB+u2f6Hv6Cq0ewXO8bpInYwlzrVk138Qwn8\nPZory2IpEEHyD3/RAkNZjAO5MGkRMmlC6knbhg==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nP0095JhTyRSuAcV3jYJyGhT1pAQ63Ikz2jcw/xarWfO4myeR2ki2IxiL2BogiBQPifhiQ+8e/taC\nZCqKABC2nUd7sP5K5FMLxqEqvaSGhMtRO2Qx+bTN2vfUmVhFmm5F0IDL69aSPE0VUYhlP+Aw6isG\nmHBHYBCtHhMlBBTHiBI=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfVKST5L4zOIHEw8rTePPdwZAh4xL2unQREo9UhjWF63YVGB1vNoHQzJFNQi2s74hnMxp4aeUGW3A\nnhI/ztVR4LEwZ7XH7wwwmLntNjOp08e4L0SwqDu4k9wj2Mq4P87tHDh2OlNiLNBP9KNGLRKuh6L7\nrvsNzCz5uZW5s7nBY60UupCfWM5iYb05yX1fiPvYksz5uEon77IwhleTgsDLGSjDpO/3MsRecpOY\n6zxdY0uNkfRy/e+huHZvIRI9Tgx9p4p5MHkKiVX5pzmTHVFHILH/8jpxbyunuxTvGsgkRSrn/BzR\nCr6wvT7hHeY/W1F7h1vfxGVI4Ek5baJkO9T+vg==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64336)\n`pragma protect data_block\nkE3zh5FB1r3vI8ZJiCJ6FWF+XzfFQVQgnzQJ/PJpjvgCXoAs4Zjsl6nmvDpPHpRl1X32r55UNGOi\nrzvS7eJCMJeieiUb8KcN1+k9krnT6S4qk6dWAtm57amEO8+SlPVtgy1tkIGJYbb8LomTrg6JKf1q\nmpnSuP6AyfZHl1hcXlpc6bd4uJId9F/xcZnJaMEQTk2Xkh0YZwzFzeJiYXNXkaANr2sFv7jst1E1\nwJT0/zDSlQMmJHtvHYgqniLGO0LTUERIJn2n3LlE+Nb1n6im8tMfUK9/omKdJrvVZAmHwm6y1KfX\nSR5hA5hizsxzuEmVhhICN34dve/ajVFv00CqzpxQcnSBCirgk/Od85aRxbLRw7wKTDQVTqkGC5vk\n8B71OWlKiZ/nHzlwZ9hkKlT5HkYDPZN426UwuQXkSdSoit7sDolGhTt4BUWi4BL1gUE1DZ/7H+Pc\nOIDFwGjTInrdA+MN85INFgXppeRHIfUeeJV6PNisW2AElJtcXF97zM77KR0g2IiTqapwRFlRAMpQ\ndmybCFy78g+H+cfr3d76Eo7sgOSPiULbuDnW5OocD16sTNjQBvfOBZ1a8fcYC0eVM/MPfFqAJMX8\nhzpp+YLA1YWJ8/mAVQhlhjc4KKcIn0RiMbw1LSTX142bdXJMBujGVnYH2QwtVCJwtuERXFtiBcHK\nU7EKh6EAIU9yCp58uJMNIub6tmkKj3b3pO5oAxbD2T1vOSfaQzg0TsmrVL6y+n+rXPnEyvrgMtw7\nDlQ8o1tq4vjKbXAMiP3VHX9luvJQB5yRoanW10HoSFcPyGhuyvBscFIWTC+BEA3hNGyk5czChKPF\n+vMFqE5wtBfiuGKEi4YBS4B6ZwpMPspnZwYf2NHSNQqfLSp1Y8r9RY/RbhF3Hc9AAXs29XP2YY2R\nDt8z15QRDaBBCVYRckMMTmGpOJ26zR/MWF3F5a9Qf5IghfFoimkitsN8O4mGDH1avgkPNpfc/5oq\nrh8goxqhDyYi9r6oAZxul3ymzQaklgK8XVa9W2wYLPQ5HVUIzH+fx7yOryc/b0XpcAYDhsiA55uW\nxPOsFmqwrzhGoEM6/sPeESOzKxGqAuWArX1dYw3B1NIRwc/SiICNy0gVTvq67BOMMfU2jEfH1zss\n907/tTkECdjUTaTA+D9QGzdlwAnxMLZS/5Jp7CaJduYxlS3SjEgCALpp8pO3FrG3dvCbzob3X6l/\nHywXPt6zQeozZUD9te+GbwL4nVBJQoDFFiKpciE0aFKU2H6IF0YZ9bQKJKYkBkYI6Lg68EPLAPfi\nHgpWSGcq0sr03CFqAvZIennPxsmwghVPPQBDInhSRM7ogh6JVSa3wYiW90Im3BjhIeZuTVwWoejY\nZtDwCn1vqNjdVK1h0k+6sZkoAJx/tKymMzQ79DNfKptG48yUmhC/F7A6bL9CZ4J0xKpJAT+0rmtd\nwEym2mskpzCcOGgRltbipx2L0w5kmRXMdyjEta4eXyFEMAzsWznDHXMv2vq5XwM0savwMfuWTyY4\nXXPdS5QFO94+jhMoG9DQ1+S+LR69rqNM/jCH6/Zgk9+GUebipjHT3BHiNgq3pjhrhoBCNVW+k8Ra\nikrBqwm62uE0Kvj7UIagh8ZVrswAyXSLIof3/bVQAJhZmB3055LH2U/4a+fEsD4mlboFaa6zet2t\nAhSATWM5T2Rxo27bt59Gb3ZUMBPTojqEfgvWWMBvawl1GlesvaxdtH3t7LjvwoXN9tdEdhdIoXW7\ncnPRYqV9hD+jSj/wDAHBKCAqn/06LxSxEo1v06AkDTali2Ibu/LpGRg+v42BQSTALzWzxmp9OZ+G\nQBOmW0FWoBr3Np7cOgqb1y5OI+hODFfRwREojfbzTDLy7ZR3RTOCEdwJ83BGogbKuZHCe4F8fVy/\nEzUHRrXI9Glt4cEZiFsJDXxf8DrBbMCe47ZO/4Vb8CQwK0Zp1ur0bGW6eZJLvm2CZDenu+smqHyM\n8cNa+X5ZWUSZdAky0ggxJvYzGj1NLWRkA3m+yU+dKGGtlf/ZyyKW8UFiemUtcK14bXza4wz86bh6\nbsEzG2TRvNc6sbZMVnkxLHYnx/xPQrWFNhKNcb16XcXCaB6WFYv+E6+GM/mR8raMgI0K1rSj7Cni\nWyKsBmpgxTKkNy540JxNPM1vmm48rjCWehZwR/BFn/eNpQZlRe261hIosBDqnVgUvGphdsrJk2tP\nuvtY6UHx4FoZy42AjlxAG9fTbwMZP/GKLN2Wn+uc6iDBnGswOQTOQl0glpbfKEJnkxuscJBlzVXK\nbIAc516dj2fAc4P8qSHMIIMMmrRtKlyoKbGUpuCdDAGCwNiB8e2ZkD3Z18aQUYjYXrudHUOsg5jn\nIoIQN89ZyPNR6r6l7HM3EmnD2I7C4nxEzYwSOaIKPYClX6pE2lH4j3BfWEH6sEd/Ff/H2P8j3/jW\nIbBz30hNDupx7kOjNavnbibhcWayZ8dsA9bmGHm0bVu6SOuXd5uKev9QnYaVITu/jLI61Wkmpcsp\nYHhaVaSFaRUStXZIcYv3VNPkuxE2az0Z9VNN0Mi73rrXGMw4pp9YL65ByzJgP3fG97U38ltLHgKS\nn5Itl199gb7ZMl0lsAh83uPfA4iGuOv2sBn7g3pyREGWaEYieHfHKq+ju38etYApkb22FnsjfVD2\ni/YIM15a0/JUEGc64KHZASi8A4NiUntFmVDG7YkPNdOXQ5BqsqprUqtMd/b17Bm0nkxc8e426Me6\nUbOlAHlZce+4uAmZvy+E4ghu6RTfGS1y2gVO/RFbNEKDLQmvXGS0//UZVhj+TNSiInw25dxsDuCV\n6utZNSIb92gOGTuKghxb07yu8yXyZy9A4biLLqaVQU0vb/PW4EP049J7YYdO9sQwrJCoeFtVEaPf\nwo2nIVX6hOpH1aFEkrg9ERiPnt1UUXlgrQTkKdlkJvC5wQSP2ZNIRveY6jHSw1gVBWkr9k0daovZ\nz0G04BIfsbm+NtmkVJ7OoDEv4XuZ4Il00Ap9vBN8bSHNO/PsMj2JNKVH3v/Xx8eisuCdeN4Hu3Xs\nzsUtx0nJQggOIjEbi1WrdnD95V5yipfY1V/ZC5V7ii5zHDUDkP+p14NMbuE9sjfsL51Rfoty0wsl\n+MoLxpOr4NcXnX7QOWmy4aGdL8C3ZikuPP00WhtKRG4p6H6MkrAttXHz6L5wCnUV4O2kGfhkhYjf\n3yQJVii52aRvT7Lv6S/BAOJFByUGl4wpHoyfLS8dLrarEOyI1mnoeOsjefSUTMceLOKuPWkMk0I+\nLR/T838qusGpX/26srrf80SWxKr7ch0YEK9xGGHAO7cgvPQTlncT37QvLwfutO2xOZT+81H22NiZ\n13z31W0LurQciFfxyNz3bOQeKWnQHIqtFv3JGGJnux7/cOP614w/LW/aL7/YOzC8F0xM3YhaMeUW\n9UA+GBxyn9FtuQ0/g8hs0RhuccMBjsnxQzSBS603FlXaUQV2FfsfMLBL7TasPZ4rIHuUWTEu9mYL\nfWz2rZbpwwfRq35JbtQKwphJScZVbTaLWyH2Isjcm3GRFrOK9OpEZwYx/HTc9n/EtRmmZFwdUe4J\nlDnueKc/fDmoU4G3+Zw6rm3p3XTOo9DXUArS/uSnCylnmGrAaBLaKnFsQKd8kCmJX12Uj/xdyOF9\nOpIg19vrcrSE0ejJQ5dUcLrb3i0Rk8eLyGew8jmMMtFOBRmqVwscepGRMPG03RMp4W3rEJn8UXb1\neP5XFWhrxazaFOY5ljiIWHk9hYQOnH/Vt8DG01HUbQNcvQH1xHNwUIooc0fbM+PgxMn2hQ0pM6+c\n0wPfDIKABiNmKLhcHnljST+ofM0yPaynaEkePqVxWiKlmFSgAsBtBcerrFImky4wOHdJwOLvldx3\n4dVj6HduJgYtLUQGVl0tI3IbmvX6s0MKeONdhJKp69hWLHhEiYl/t1cPpLJB+SUFp/r1x1s+MzD+\ncKZW7hNtDThOdBJjoeAKmavGBoh4VHBtQqDP0lL+EwpSg25V6X9XW+dFUEpwaZ0CuVXWHBtwGuce\nMaku0HU9yyOJSHRk7R5AzoBM0QCbfNIwoEqrpTgUW78VzRjekms34MQvc6/VWtqoA6IIgPs8ybLJ\n1pXEw/utkcwR/tMBVJvyKzEp9b6Dc0sotuhEJRY553G31bb6xa7Y7PG38YByPiqfJPK4AuPhcaO4\nN8WILCcgXuWL93xjqu0/Ew6z+GNqQm3Jz4ntiHysc/AluO6K7vtwO4UcS8ccMt5z4bpA4T5arE4/\nb1eHDWK6JT2gX5/4lOlR7pJLy5qwKyffyaH/Nqz7AsCVsPZi3Qwvygy7NndJ5ubyVcHxyItssjGq\nDNBwkJOOVIQtsmfxXko9LsA2I6zOgj51rqOlqXg2Gk7DDJjUk66K8JUFHjHbyUHJoAgAJXbcvFfs\njDDBZ6zps82PHgzQSOWlueInlKXLUvswdqg8Szm9Rmfe07P0jivX7y1UdWGu42d2G9+SbnpVwkAY\nd1j6kvNq/oN/n3VLX3UuBoSfGik63mKL3qmADCS+UFhJpi4xHFbwZh7pqoTDSA81OoplAD6RtIk2\nxTHfTfakM+NDXKgW5LVuaFtBz+6XsG5LuuVK324YlMwuHsdtjt6EchzSz/yYaMPHCFdNxyRgcbqD\nSIm/1x9m9ypB7i8tHeuJrv5TiGMrS9fK/EjFDH9s0XHcvfmBsVMUNdJPggy2rEwjwRnqEXo66at/\nAfc7We4AA8PDP1d76rGrBczWskspbNfVGtzLYmsuK1aMAzAGE2VnjMJ/OJqy2qkF5qntyuXtWXp1\nXYYHmfMdE0HqigV/1OZ1p6fodgR3cMw7dqDD4xSvY3zej5zcUNWAw6yrxJEPGUhaUjPtNS7+r2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fRoNqOEwbphWrnFxpR1uQtlznt7NunmA/HAq9QD0jc3VCyUGLK1m9jzfR+MiOxGkvi40fGIh\no5q6cp6WZYQE5sG2u1HePNz260XW98o1SKmGAnVADmN9oRH+kJs27wjueapaewwDVg8pnq6kJUOh\njQd0RkYcTMItDGvp+sFqeIIdADsTHRvr1h+M+pYqq9sLbwUoz1Alak51hZNlSXhSEVXzQLkppmeO\ntB13Z6wglCy2BICINwlSr/7HP1cYop92mfeTXL3QGuFjsDOYJeT9Igcq+fS6YIfWCA08MY5r7yVk\nVPB84f/igRg5ddrxoxTIiw6w7GWDOhG+zTxF1zyp5jJA3yKcpqPzSQpf9MKcNt+PzeKm+wneK6Jo\nhpoN/97lq7oMjwcqj4fYDI3pT7J8WHKkZCIdUVNrv0PtjsuMpkuTQbOr8hbWLJNy8UKFlgHOcfrj\nOvGAARiIQRbgB0ehYmzYwrLOYCEEGz6BajWpYh+QjcQz68HI9uD0KJTeFrxECsQhCkd+nhXmR6Fd\nTuqTwMlfvUxKMpfl+zweX6F5NmHmeyPDY7Z3diHFdJVtYNhc+jcelDo1qmERGZj0HjhlAXvpn27V\nveZu3AVSpka5ElIwtvHc/TpRzjvbeQHF5yFv9E3VhZftw6+ajD4mjDYjGCqQeNasu/oomGN+bD06\nLx4hi4Wsc5ABDp9+84vB9wTN4vdXWfDxjG6e8iiMfWuezpQtLWJtxG2XnhaF3oXBpRIS2VVSE3h9\nz+2gpVoEZT3vzJjOS8nL57iPKloZn6rbf5gWqxxUAtYbGct7VUgqevGHgWDGl0dAqT8VpJaQ21q6\nFkr/uOy+vbpdI3AICEPSgGKQQMnk1kAfWxfgJ/kaxhZc4f5XlC0ZGSh+C2CWzhNE/JAksw0YQmsi\nne+rOYuBn6qvg4VY/SXyC6jNTUu4fEhiqCBJKvOpstSpQS2jYVyQK6GIEoOtvRL+AeqOwN4ylvak\nQVkg+2A6cwY7T1x3wkcNeZMXbEpORaOJMy9wXl09aJXky2uN9qgpXHXgPTZNWf+saMNRN+uBGVzs\nZjhjfEYYTVSnY0pqS+gpfbtlNOxXo7TL8OvbkRAThNpVfqwQtupoPNk2HHNbdmWP1tZGcqPsQf6c\nCPJwuj8fcPCQUh1HIZMnT9DYnr+Z1+9YVL/Rz7jLHyA2rFlsPXsEC9hUanPqMe7CAAEbjTq0PKon\n6vcDhC4OeDhfHkwfTiOS9fxMjBLTcaoTqPWTZt8ChH4gnVvPWfUBK7kvIhw+dKvaxIvX9bk/BH/Y\nB6uSJzU7imXZJLx07cEcU/6LrWAx6BrPF2/b6Su1t6eCb+t1Q3QZIS/1RXup1A8KEnaMO28WsZcw\nZQ5vCfX86ljiIl+HfGiLBpKoa7+SdP/+q0BolGpFDPCce56LZLDSOjBraFCS81FH07TgMpEW/Koe\n73WJ43JWWkZBQNZzN+JlfWtwo4qAocwsQJX0w6MOAIE+RO9Iwh1IPv1zbtcWHBpWy1yK1K+qVbiT\nkI8txebAMYWE1fJJdK/cP/tTZXiQLhiPzBsl9ezZjJsjAPcq3dbWErzH6ZEEnAKTv6PShy3Znw3q\nOT6++Nsz6N/njj6GqwN1E2zfnMNA9tFHXPkjpOfSbyTnzGEEZwPile3fiO38kzzHEjoAkb37KavT\no8WtZsohsnfTezPzzWxB9cFMtrTKv+u3cIIlr3mM8PZGdN2ZSq9ahQfTqRYp5KGtKnkkBIfsbqqM\n6M/SBVm5RMtrKRYp3/ey+lutDPtoUKLWJMnsv76her8S4uek1nzv4wTizdqJoCHy04vb5HAcgpVC\nfcWHgEVDqREje1ZKN9cggmiVpXRsjmWDBU/wAg8c14gohHPFlXNZgAA+ytO9js8szFDnt/0cCj7Z\nkDd0C21SAR1LHBI9KUf497LL8Tu6L6XEd7Tm3XEXeAS5OgHmGdAHyGPiqI9u8ClEt6BkfXamciI6\nlfeQj+z1nCxMPEJCjjzMwvV+3Ah7f/pMVMzaycr537MfD4P9+Ch+Y0vIsYpwt4zU/30BNXnQqfs7\n67i6Wfe/ptu3NRiQFhoPNGZytUbv/evSNDXxFaqwfruUEUqn0eUopvcwacq1XD9XaRIAXBGNpSoS\nKKesrN7Q6LZ+PG/cPTdT84w/+X0t954GdIewb65IP9dwf17eYtg2FQZyM5t0f3iNHe0pojKIaM1a\nmcTIJ8FIFYHoORq8DSEu6tyA3X53jjGyQRjVmLNIZdZSbRVoyoBsiZ36Zh4U4aW+U1leOK18co4C\nxLB2Om7MWuPJT3VKJMuG8psZ0iW9z0Zxrl1RyfZ9Lk3hYM0VRdpLKgxqEDiEeCVqfhlGlFXUj3wu\nacVLRH6dhSEBumjFuWq/lHbTsYfS2PGWkPdKedT/skbFeOsHLU4V1O84M8q9+qmppce19MSMwXeO\nQ2jn8v1qDqQoaq9r7Jvksqp/+A8wClhvUJmaqnTcDX+MLOJSbHG2ZNR/3PvUYpDVUrL6FwJJEASQ\nPfeLTPm7SGxsfS/ZVEf5pC70NwkE/6UEcyIx7xiVjxXhDxpA1pBvp9PRueOVwllHhE6dRkC/iGjc\nY8YKShjZxisO3URdOWXpt8F8PTMjnWoGzvbX4aIve+X5KKntuaYeQxKXCf8OJaSDgRc27KSBsG77\nFYG6/6BcH6AAXrtXc/OMZ5Hu9pwGsV20Zxo2xAGLOFRpmnHdImjGCwHmcTrhQpQH8Br0AYr8Dchr\nzb/JJoGRA3WukUlj+NanwbgVkpDoHAJD1a4ftoDvHJVleoDf867gupHQThJhVF6z8LcDtafpRVrE\nSHNxS9sSGI31+aTuQ/0YqhEiBI0k38xXFesQY1mW/zireb4cohUmw/0Nx4uTsUCRUE3WLfpwBeb4\nMp8qasvOM4Uf9kQqF+GnmseyoR8jF+xEaBjyzrsJ7WpU6EQqH7Cs2y+0nkw7vULcWZ7PtxCkTi+y\nl+KY1Ss3um8ryMQYGvKj7L2/zAzwrarkjBW4JAtWsM1SrwqZe6veUIqe3Z4G6jiNsQ4NTDb8oypf\nuYa8F3nzw3hTgsLTGVQU9pMPE08BjCvQKFqc57jBAj6RXHMnE3TWWc73XS/zYTiQ/OmvpnxjZ8lu\nvX+/r/dA5KdxINswaLmFPw3KzzuWJBz/nVwLRbAGp9IHQYa6bgjjJRm5ZmLKGmzzyuRrQXUPKOTn\ncopnuL/JvlWnSdn90TMc2Tzzm7TXaIcgX9EDepTRW4sN2XWdc4AmncQYlE3Pc3mjMKKgB95f5TEm\nSgoHGZwRKlzoBLvmO6GOz1aatdeR50BMPUt7pSJwIgfBdLnvzstov1W42zn7AgW7Su/pfCewVOQc\ntZ3KuOMYDHtAQmPMuM620hdwLoXkyIatvRSwpr0SFvGi6O8B6kQ+5QxGad7VgcpGZArl8TiH6QY8\nUrI26KJkzhP9OikTZ6om4ZAs0bloMAPotwByB7KXegEUUn/G7uE2JTlScgVp8fNt08IHyAO9ubEL\ndk6s6Dfr0H5HdXOKdMAGD3C2jl0fudKu4zYcx0s+KraQSQgLXI1G2qoLzPeW4fGtztn4k6iTlSBg\nRGAbX+gnK/iuGfb+++nrxTBI8qFUX6YIlcOAkg//OSKGJJjat28UHn7BITZnedR7Lf2K2lu2q4yM\nUFzK+WcQU2KYHp8iy1VQ7x84oZsD1hpSPIvo8xCeiXIPtrxEHjRh9OZp7jAHNkZxhB53ii81SHB/\njEzrBHa4MLE/6WMisOhbmjPDUtQLtgnO86q7gzdmJX0C1jvl0VzQx+0ISJcZc1limXckLBS3F+rI\nMi8MGBfMyw+BygdEr2f6yRlYvJdRZJhXOXmHT77UlUuCfmArP6UIswPKplZN7Q+XLflYU+I7OUPp\n3qMXyzrC5ko38DucoiwqvsXMSMVx3U4vLK9VKA3sPt/QP1E0S7tFJB6lDoYQbdTI/vUgNy3iAmmw\nLl5BmdtFBDWdwEMFan9pvoDEbzNfFkIUBGuzvnjKtAFBwA67RYWKtqglvto8q74Btd/PMxWugAs2\nRDrpHJWYNh1j5vrsdRj6sRpJRMQ9FpQRBFbz8fol8FWWJFG0S8M+zbG317tUs/p0GjHB+hTwItqR\nv15KlK1LZfgIy6o7gd1a/8MIRTXjAVUuVviJ68d44vkkJr3mh1OphI4SBhUhzOaf+44CoHK2dorL\n9MyTI6q2dacNJIgHdhaJF+ebOKOMQ0olKCeLvE1KmN4SbPr9dHBv/d7cupOKbz1XYMcK66m5e/El\nRWsYMbQf2uawzWEs8cZBm585waVMQtfAQNoE7/Rs2/2SY+vnUPguioY+EDwZsTxfJWkI8zHk2a9+\nrJrYuXiNAW4sd3i5EDq/+2Ak2GPpRmfpxb7u6NIBKlwXugW8ktrqwlNqYCtg5vVaseU+FGNiVsvF\nFIuNWu1U7GpZ8HtnZu6aFs7IBPIoYMl7vu3aDQpZG9I7sSkjhPjg7s+ijQIJ3BGlmyuljXClWhZL\nJIDVQLnzS1pM0pvibM+4youBOCPFCx3sFuvQJZk3DpKOy2HX8XmKOtbKgZHL2FBjFFosaGOqcL05\nIgcxAvuqHB/0PhosWC4fcQy9X0ohWgMLrtpWE8mEqH+l/idgHAn3azKZjNDZTlrOZEPh5Y71cZak\npKgDUjLW4WthFcIERr+HL9L9PI43LQ0EKDsQTa6UW3qJFAXgUMTYgZtO2S8RQB23wPZI6bncN69z\ncEU5z6OZdFP2CgLvdInA1tFbRhPanE7dmxgxqPwFREzFyPLMwVsw9YgzsxSxbhJODZvVY1Bp6C4e\nf8VmwXIAZt+OfsTInDC+dttMHHHCvtu8TBUbI+ZLgsD0HzsESIpV/BFvQsRAJyfHJ1Qu2kByntgu\nauKads6lHHGN1Tz23/hFq7PVfLwm2Rv+/yx5DUv8Uj7PLsaHqrCdZkVzr0ECfIwPFt7nW50xCqQK\nxMu8QoV4cuZFAJzIhqj5t05ByOQPFRcxOQEfZrShvvNR9GdpYtghDBF0fU7BDHiagP5xDQ+UrHtz\nka7nRo1FHnm5QoYRJoEBABCLmeYI2KoWtLqx/CHi30vFLoru7CkCPX2Ll5A5mIHnjWmu/VKJrgNa\ntThK/it4atG3Inp2n1vlkQJQNib7fEUdfuFjiiCQRuNtmJX+MqELiPQnVEY9VWHNKjBPREYUQKnP\nJkfsG+QfkgAOqxHLM6oCfy2FFrS9aHOTMK/+PdNJLxa769Vi1zeXV0kwzsjTsJp6LwEAdQ4xKPck\n5bRahBrDgSJfUTcQYR+fbWtE8OdbPM/FWuaIc9SEfNMEebsH/lUKGSB86OWHZNz4CMk5ebH3R5JV\n6DdoBjfP4Atab/RbwcQqnZG0UdOPbBy2c7wTzqK1i+/C1l3+nDVheGhizstvKZZdm6XehGdOgf90\nOPsGrNckYz2jn61FOH0PY9mFh1FLr+59tTVOFZ8+6G/JJcGGo8HJhb6b5sCjXHSsT78/4ldD51uE\nJDiwF+PKeYLd+bhW7XjkVvG7+LYAG5h34M4tD8XHnDUKzWkpzBJ97ZFr8lV/euLpwJ/XlVImBXwp\nwZCzDdGwiTrZC+ogqcsGqoZxLQ0lv7VhpBL8skkTAYlBc2XQufABCHG+gWEuy3TJvqodDuGo0iZz\nQzftJFbueGn7t2+s/eYkOYS6arOhlDNJX2nYR5xtrB1FbV8m+jaHEiJbQc7h1G4HB07HukZZp/9P\nLFvsRYJ6uqex6hCbbqMMHQGrId6QGSH6/q5SVMSgN2/gJFrr5scKkIFUDU79QyiUDCNwsC5hwA/Q\n52vnU3pPU6vXy2f5Q7ZwUWdsJFEI6O0jxqL+Ga7+MIwsqnVb4GlFZdjTH+jRLEyw039RgVDhgKFx\nliWSLpSVpJs1r/645DGyzIbsFE6cPjg38+CcoAWYla+Gp7OtVF5Aqtp7iC2fGffTn7TvJOPCsVjY\n5MHx5QGSiT/mOGO5OVGVbXQzgTu/3GVWMajEmAq7T3+Ddw+yw94k9rT6IDk1t3lnruZSEJTPTyok\nw+bsJPG7RO6DcD66Igd1WzLO5JiNwENjJVrvbbBMYTJCgVPc3hJvvFQvfkLiuZsa03mylgBXKHAX\ng1TT+hvmb6ZTIuNi6x63/487ZXtXCLFNhUfNlssg6Z7KCyDb+mOiA/8aaC12vb51w7SWXNrmZCWd\n7wJVMUngtcinyUXoTuPe67Tbwu7Y3zQ3ZBvKMzu/YFyR0SsSeD+/yJ1siLMoqudSse4aThJOdPbm\n/YEW/tF7aovwdtXP+40gIRqfPjqUfFDJzhIh5XTJx+5XI6b1ZNJdT1+zC9ZCv0wpUCNzcYDWP2v2\n+73X+DI2B9Hk+GQUz/uV+HUBxDiALLNqS2pBnu03BRN2K3Ae6udAdykdB3XrMGU3apddVfl2Qzxp\nIMqedE5qxJzRw+S8ghl7CQ/HLPmeR4VLqSCR+4vWCWIw/nWGOStxbAxslLYMvqSQqcOh9SyzCdy4\ns+S2RDRsuoiRadrTnFE9DK9AV7YVbx1TL/4UsryqKTyD6TZgb3LhhYOUcpIpv4eGF6c886m7YxCy\n2UDtdlk5mzEa450taWmN0KN6rx09qVH7bTyCrbrVUDBIPLqFlGt6zsHsfsvCJAI3c9lNyy/K4Csx\nnVy11QZ2mZmv5FNhUpC9/LR77nEsEfKmmY+ZvmK6ZHudJHG1/VfBI8FoBMT/fDIUDwW+BhOel/Mr\nViAUiihouIkWJnuBu1qd0eyhHAEwYLpl67lU9OZtC+Hw4nRKD7xL4yeaFxYMdBRfHT536DpZkC91\nDyLn1w51UXVeDMGmEk5w/suYHhiKKlsSF4c+HVkT4yWcG6HjE+nqeKji/CAw5c+5piMrQDdaQcJW\n3nb0iIj0gXRBN+Eotil3B7bIpwe2t+faDTQec05jrigHMr3ZgWGPMkTWRs4Qir553sMKABMSYkcR\nnG1bX1HCd5Umeid7Ko9w+QAO4nPsP5d0GRtDcIyTVJxEMoOOJPe6s5d3iX9a55AGR4JeQOBinV5c\nvQTaqc7NHTeR4spVOyNLX0Vt4r4xYeQPAv/7STKb3KraVueUbYH++IptBnYURSH+JYRUgLc3wOAY\nvaIiWiWgsMJN4S9Tj57MZ21MxkcOD4n+daasVl9bXICg5bV/qCKv8GLgLa75Lmkb/q5ZMWqIh9oE\nBXG7qwnhfQdr1GBfNX5e2CHlpmAsJSuPYxfplnTe9x7rmzk1saELs+J5Zod3BW8s9PqEOytiKyFp\nNgIyYxnpDHg3KfkpBCzAqsNwFrRhkG0cNj6GW0rXcjnK5XVsm5EJsIpUIuwUUCM9FS4M4tQvHqzr\n1S0Rwfa/ZmOL+3kwiLwUF5yWFKNs9N2uwmJT5wYI/8PK/4X7jfYBxLNFiM1d7/Ot/0CD2Ygqno20\nGjj8idQj+8zcvopFkqmlICXcCSsY1CN8ytSbrd2KnMUs733/3JrtKjQJchP9IvaMZn4C8GZRjQ6B\n2FQEh8t7rEVQECSOxQ4L5fKxi4VjvlFFV5om0bkmX9dxai9YM/IwxOrmiEVbScRlOGYie5dHSd5V\nk90VtMGSxisAx3kJM2aVn69wCxymu0VbpXmPT+80tJOSJSASfShtKF9vvaTCkQlfQzw6bL7yoPjh\nwEpRBVB8nS+srJxgzTpzxf6kWSrfKwaXXevwejax6otuoFF3YEUOCVQgG2aUWnXPnlQBNC9MPtAr\nmChzvfkMA49tIz4Ra/kpvwGya9myjGuIQ+DpHiMvJrcsopWNYHjXYldeCzHaIWvnSOHGMM7nBGD6\nboOM+PIpyOs0dw3ymADCy1T+tsTasU62qNcuquHRip5asAz3bozJHUulZhGOlVgRZUNdbA/meTnk\n/sjtLjzMLOoPyFtPJUmnUvTECUkmGukcIMhdEnWfA+OgOzrM61GTUK5bwGME8XNRsprWjCchp57f\nxii8cEiyhO9Nm1pmdrMnxiPCjIW2WSFsnp1BUNnQEWDbigo95ithoSdZejaydDJCNHQMVMB7BgbH\nJVUUva0f/ZGTwU3kz+FTzsT6PT+E2GNMZm6rzSz1Q3yNoH4OXUbJwQ/vRFtTpicFPDJoLzVZKQ8T\npYc5LFd897P0DLzZ8yT219GrhNpk8PgFDRC+bylWmXrFl+BbEfkaO9VEr+LIfaNoM8p0/YLHLo0l\nMrvk/FTzdn5XhFvxyS+Sky7a8fU9qLu5xKvwZGoA2MbCvP/9924WG5xmAmsvN7gJQ5JylMq+lFvT\n9vBEEkmXTi/zMkw0f9CycHzh0eBomR3kzWnpWRJ8aBj76yXKuWdrSZi8qbVdo8wh8eb5xoIV0ir3\nEqgdL7Zjn1IcBmqhcr3AfwkhQEaXeBA6hqImHgPIpyxviqMTA0xjkebO9YGuzZAUIa6uCCzR8XPj\nbYJjNkm+wZNwzr79+h2XV6wDs4JS8VDdZcAVCwvmjHY8WHHb0jZTF+cMbLcUDsGNXONUc06UzHa4\njGjOviVfcTwRaVwQs82CNgjt5OHwna+Fj+b2mGBEyENynvXGlAo4ECvuBzpI8LU+ABqJINwvANwS\n44b0GVEJNVekwlMSByybrdYq2Lca3a9BtZmGtoxI5vIDG8U8CGIe/HaNFpFIvuyGDgYAGr2eb2tc\nhbOnJu4LASxc2GdEl6I0f/Z0R7seDGa895BuyGGcT/HYktcCq70sTyk8r6H0klX8wc2w+1UT9sPp\n13PTlh3zLdvGFzKPfIx0Bovn0nIoViJ/W+tgIbtcCnPhaL4gh3QePzoLOGoIWzrZKrfXdQUkepGM\nnGqctZ3+0XpR/XS7seqRDlstOjCXkPam6oFji3lfLKqM8ABKgItNsWesmVaCeblTHDPu+zmR3Swj\n3XSa7hlf1r2EC1jqZ+oubGX9WZjOz1p0gsINsM9ZgUPOKlzt+VBwtUQGbtj29NqAdJ2m+hFTMnXL\nwnUTOLl4CkzQ/3PrqSxqEMLrVcMbDav1VqHyySeQ9SUXcPePCnXTp88Ns0q+RqrpL9STvlzfv43d\nQWoOfT+y5jzqBr99d34ltSn1jq5Mk5kfg331aVBVDGP8CPubrq/MjnUyQ2o2sw0VX2JfGMN2BjHw\nfFEQGRoV/qgnxP+Yg/hdQHYj+r8qrXledHrHiSIHvAPs4IQgUCb7GIaSaT8McI1pg/MxpBTzTrLO\nHedJ4drTUgQ0yZ/iYK1+QT4h4+42fAkQ1PTj0z825aLEk1E6e1O4mTyuokRi5lFL0i4Xo2nnJmcg\nY2HAeYmkS26cU2mggoFsRs/ZxkSkF1qMN7lvHplO+1XTHO0DVfLkBuhEnnqTZn8rhmPL7cnoZaUH\nZ+WcnLY2VJJpEsl14KAieVLy0ABlPd+RP5UZna1k+42P6i95rcEg3jt0xbOAbrd3GZ10GT4chHwX\nZCLWJjslyLcbPGL1XdWjgDMZ3dtfG0z3hucdHb6/ueD5YQwPMdQIir9TjhHok4WPalVXcz9OwrDv\nkkUDrWxC6S8tuOFRsk6jqShA+Nv1loaSF+IqNB9sfeSGW8EsyVZIuI1fnErGqbXf2i3DInx/KFau\nWTBKYaTk6krZM9fG1+OzTGuQ4ubpSMe6o30MtzdVl/db9M7hv27LYlU0miFi0OmEUVGOOZDK+gSW\nYVlr43tdFyGvXHSuVyUe8+IhswC9IOCUS+h418D19ZNCQT6af/VQDeVmfOTnnZpP6DOc5p+hPFvn\nn/ISPeLm5qeknJULbDWxnHSxTeKqsw6FsTlJo72ZuEd1zLdA0lJqNxSH7YKQEawd8S0tE50OyfKP\nJjTDQ09tW/9msny5f6YFRscHzIbThNRsbQX1saPn1Gu4rhrY5lijfWRBI18U06gYijFIC5rZDP01\nVBYwmOnQa+ODOGfcUiQmM5pZVc0/4xmoHedHdwn4afREXvUzDZpKM2ZwPhNdB/Bf1RFqcRr9sgEf\nIub20BMNkJYzK5VVtGRXanivzfdoCbqJo4V8P/5J/jpsiDuZrb6BRaaYsv6z0mpEcr4RDQLHVkHN\nuy/UCVRX4N5yYskMUYbh+yf9ItFGH9xiMcWEvuCIcyyyXxQdjN8M72SBJ7rSGqi/iT7lD6zS9rCt\nQ25SxFqFjyMFb3/PCyopcf+doCoAKth86socVbKc8wQxwpfsjnsmDg6VfStQW3j6HbTJRR6cBKWg\no4hq5QyH4OzFyrWlze3EVjvAIRNo80YsifUXn/YmjqXkqejTAMs5rvnQMXvCCx5iTbO8GIqe1ZIO\n6g9nf6cdH8rgKjU2irIjf8wuR6WdAKliC5HyFO8HHKQ+o6jDL3Gp3V28RPoZe/ggfrNdJXuljh2p\nxgmoX0sLC4F1b8ary0X9O5Uk4Rm6NbJpHEMhDyFLk1/DSblBMxjOyWf69ua/+JJBU1aCUg73Ef5C\nKAF+0i0bW7wQ+1F6T3OIrZADAm3G0/7kCMyEk/pFhEeiyRgxWwHJyu8Lq3uncIQ6F+BT7fiZp8Lb\nzeD7TYdel7zVmCJayJKdXAqYfe4tHf2ggNiRQtb6rW7zzuDWxC6j9MOehd+wYLkKuWxcheZiDDGY\nXoW8Dn3gDgb6qmAR+aoQ6SUd0NHC2KkR9FKyVg+bhUh+gryvAjrRb/wdpK17v8W0/2ConYAt5qvV\nSx9opD6CbxukzGkKByTs+VXu8lWI81F+WVfosuLsrM3FC7WwGAbBF9jP7DkjemdKvZgK9sQ7+E/w\nykL8i/agCWoq9h+u27h1mXU6LVJOUIupwTkiLc4gn+eMXDqL1Zs0XW4Ft6C5zRmojOAbLVdpcML9\ncO8kViI9Uir6g48iHpcD7UCRyJ9cYSxliNW/0Rb9paOHITEcA0vN+6M2stDiWjLaznLsiRPKqFdo\nrfGWs887UdLqjo8r5gfiIx3q6dJCU+McJNwPj2I3Jch/01qA1AnDeFImKz1P1Q3HCe1YUpwzVdVf\nPkhvqIK1pUei69jyfiI5P4YZY6+RsP2tTebP3EhStUcOU/D0JIBRQ3VQrJa7Jzg7XWISFhF95Ti7\n3z2sHCcTzbDUqq+3k6gp4LymdHgAeI7RRHTNZ1hM3gc+e2Uv7wdyHBjADM7L9XBxGBNcR4RN5X/O\nwHBTw2vsQLZ+ETCgA03rkxnuHqpDB0M1lN0U7rKFUSuPu3NDS4bkCedhAckj6irfUrxnUC0QgoTs\ntFKAHU4pGb6keU3Kg7myTPkUugg3IWlMW9CYcpswzcYlzxnplzkXmUsTb7yUni/FzJOxd2qE3yTt\nWQa9KaZrnpU1W5773WQ03FUrxVsCIZefTOPmIur8T7txGR8gnCqsv6QBEWRakWYYXlNDPF2o7A4r\ncVeo8ba3lyADQB+lGcry8YqZvA2wzuQ59Ct4i0KA9Mb2LF9KQ7bB1/9OTdfRZWE8PslluZPYlEzU\nGIiorzNfpWh8X4UZP3wT2l3N9GODYuwlA54ZzhLwHUMEGM/utYMeZ4VrLFEqJHjqnVqVqEm0obrN\nPZqP5mgXq3WGmC5pYfblJggRYFU1uHNmMHxPLzFUwLZgD7GeQfZGvj2C13G3y26TPQRTpuhDb35A\nvsAETZta7bv79C8GhKUuszAXdEQqSt1AoFC0iB1GHCSIayhEsCwyn0tZAjwF4K71go9RPoIkdhxL\nkDi3AoLRdpPebNp0ZkA9jEvHY5jXMLUERzVAQloyXoj2mtsRNxGVEfImCoMq2ZVf389ZlS6517uC\n4F4WcDbMyf0BmdD6i/dLuCSP+aCs2mm8HWSoppsZuy2SM+34/m/fZC3KiLWa61trhcRHNacVqLWM\nM1ySVSUKbL8qF/lX5NNiyWlQ/hIKgo5zbSVAjFIuGdhB47cwhr9qYQOyQP4KYaqkT8bOk0gV608H\n9Su7bdsKfB78LbLtQvLgcdNmpq12lLrtp9JGg/aWPRjjRaXmzfcImW6wBiDh0AY6WYpGq6NDGwpA\nhLfZGiij/5kgTLLcNTwUpioAt8QzoLhp2p84Ra3LcHOeoAkKE+yMQ4mK09MSzL3P8Ld3KD0QDPou\n1mkPSzbvEsAv4b6WlnAkHgE2C1liHlCCPEIbY9RLAAIFGGASnOKMf/JBTcFSO9khlVSyREctfL/+\n+2sm5V5I000OI6HLT4IQGxsyKIQvLst4SWJd8GdsMkxBNNQIYLCFd+M0FLfYVnhAzTiCmhTAdxgY\nRnLY7sYZmGyfqmehgJkb1ErB7sPfr8vyZ0Z0qTGm6pysX+dmnzDmfCExQjMKu2kaH/Jnkf/0K2QE\n0mcQe+kaAC78lUWAaER1hQxg/ftOI+igRhks1sWXY8MhssSIc7iGfYiaSX5yUYwzEYIHyeamk+D4\nBGZ+YPTRPzSmZn6JHsKxCpVHspJambLKzdn9L1iverJbe9RBJ67u0pDof6txNi6q6cx9UXuddpCI\nADEaNB0dJMRmsoCj/fzzaSGw17nmnS+BC3WaBGJJ0aCoAnc7XqxprYwTNjCwcfmnuTnz1ll4P6KP\nR+tCsMDxVPxLH/eOccJdv0WR697d04aU2f4TlS+gELkIjB7NOCRbsRGhdrgC41wGRaA+u+ADhUP7\nfgqEuPYH+Xlvsr5QZvd0mPJRtUhqeR2AuVxy+G+kreN/F08X6X8tMFL6Avnl939hF6Tg7+BCy/Kx\nsrsD7ivYDRBQnMEoH7qkapYrGwu2L/ehj7ukBgOh/3Ejp1E+c1s1tWHeKPFMNpF2yx01Jy+5AhDZ\nPSdTYZFa7GgCvLmaicDHdeUnz3cvuYB2rZDX7nVooQnhB8Rf+6UTzaLdWwGrNu6c81vDrNUZGidl\nQpQwK1Ec1ecQqUWRK/KRYcg6m1Ot+IeGKFnPa/63sxwZ9w5pVjXJPGPrKvbZa+Pia3+MyDaMUQhw\nBm7TiPETp8qNL5v2hc4ybZJ1/NoEc6gdnGO9J8VQT/rE0pdpllH9k8vOItKpkEd0jdM2GPJK7ZuN\ngT4VCNV6rhNPeauuN4NuXgK+v3g/K4wTktuiZM36cOktYWhuiMZu+ZjnMmX/A5QrpZY+t9Xt2bxy\nbHncUMvFL14jNC6856bBlk5GSJjHRntBzQZMCIPtVN/C7jb/kxC/Q7mQMrWGDUbmc86VpIqxeQJW\nzEbg6DHJt4qOKlU6bzOt8FHPe3nnL37FuSrsjXpMBPVMzU6CF7izUOh5UBzaFpu5fbh/g4VrqznQ\nSEQ5WlWoVXW4ZN/ojhEvPD67BMdowjFSWDwe9HlddgB5BC49PAYRBh+jjeP9WdnkJ6GMfTXpMvgJ\n26AvgS3NcETqckZHSEGXEL/OPVvIwi8nyhmM/7l2ITTs1PcfqQdiKkc+COW6I/hfYNUYQTh2Aifb\nDt5iI9OZplitDHVxotoP5baEwDpoUsYSWH4r+9DsqjnnDi7BzEOGahmcDVhlbI6rjq2uhPt+/p38\n+LkfOBeCYUg9lxYke403tx9nNLtpnFQ+qSkNG+pUBDWPYGdMnrduCCwJnxaR20CQJOegEZCtYDGD\n2Pz7oh3uP06B+ju74IrcowxofXDERrXjwd6aL2u1rgWhjNv/qvk3swUVmQ2VnYZVN2u1qvFFwOLo\n8xArvHTfDmfdrv+mnz6ewWhBNZHVrK6zR44f5wUhX3ohSyWzCmey+ygAmJrPygJtZw9dvtjXPfkP\nmq6gwA+UUZ2D/1HAOpktggmARU0cJShJJl/ZQbfEq82hZjpZo4tj2wQquzt3CtJJ1biCnMf7MQLu\nxD5o0THKOO7mjLvlVn1vM3tTUc4TgSqw79cpS2caat1pA6PVms/BbFd7QjoHad+W5Vxhj/3Wdva9\n+rbOmR2Hr8d3OazwSj7QDN+4RyMmE12o2q4Wn8ZIxoD3tJCCKuOhqSWPDKASZv/IkLTin6nfXule\nIs2eVAEvlNHa3yVruUydEwXXk81lM5Uw+tSdYhQuqPKwBTGysUzTYknJlqjnyiJoXPUd9YTrcDuh\nwFtFWGr8LHDBhe8GRsZMvaYVZ16IRpnWVDZXGMMXqJNZhBDZMowW7UiEdpYqEBpvKHYMG5ASHsOq\nH2eZFgW7h1wB2fWRp3zq+htPMYw1HPP+PNgsCtaRQubfV2+g8YN7JSdRuJVQRKB7HfbRlfal4MbO\nQob2YcOhWtM3Tkow+j+pMAfbns+amYldYEUnaKZZKXgICtzUe+8tc6c9xgVYa/sNKoIeW0nQBgNM\n4rCru5DDjI6BMNPTgpTdVNWaZG8SR5DzenlSrkXBFykWTQ4LjxfY9iSBnutE8jbzjzwPekKq0wC4\nGfTVpOKVUaTaZo5wkojWs42LwU+Fh2ieJ0FEh24ZgSmFkbiiKAU+zrc3dANLGSgsgvCfVs/nP9OU\nJ1hObUY9Wo98gIoZr3Gz0C18ojCwZEb/dDxvyJM56jypCZsl61dYEVTjoW4z8i9chA1Mzbxs9eCQ\nB/SAYWddeyQDiHx6tFAi0C5AhuE8RktZjQ2yt9UFiouVgJZ6wAl/my9J6gKj2Am8k7CzKhlfV9F/\nVXJXNDBDxuDiqSec9vv8heMTxQL2hvtaZRbS4Nm2UH6mj2L5VmngiqZpUahulzswui8rW1Y4Wnfs\nKRTh1jiCT3mA0NfnDcq01KTgR38nkQ32gdQ42NUQGHAie8oiq3p6WSea/2JzXYXpKZb+cH45ODro\ndyUi4j/yaktRND+QJjGGrC4CC8qT5iwirtXKo9X67CllayE6G25mEe9A+huiY0thk+QYib0Lmnk1\nc5S1eJxEg6Gq0HMfuOIW8ogQTs++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qvZJ+ZCMnS4whysx+BCN7ma6YkyIFNzyLTBKHcjS\nE4yr0tuw3kDPz5v78ORBOVhPwizhH/dYdZV6B4mpONFDbGpxkNkVK9fLeTarpzCabmO1Cn4BjkIp\niiT9kovJnycvCa/1N5GHTOyUxMQ7cIlR8GyuJ9G9vjXMwxgt/iu6Nhs8Xf3iefAXLo2vTG778wZG\niKCTTviNxG6RCk8eWCflhdYo1C27j+Rqirx/r19s5oysIyqAS+9JIvOVLIg8jHsKyFqJoA/bNCFW\n0Ygrq/HNoWa48zWRfKr+os8ajBpjXRLOUeJhAxUEyFZWwKTJX5nTylPs+PHtuQ1bmgj4YfnGYxvl\nKvPBm/3LmGttISWgPjv3bic5rgM/YbQJWlKrDbIbTkJM9dGIVqw26kNaoKEGhqo5MGof42C6lrXE\nqRv3QktEZnMKBxdGhro9rM+0/4QV+aqX1Mk8X2EShfFeGJrur3mnwzkou97INnrS+JcpT7To5jQU\n8Ig/dgCx60pkXDh9dcoI+//AXBmIMTNEgpsdZ6wXK8vuSIKnMPcr0ID+Ztxy3w8MRNBtswnCnLsp\nhBP2QoArHvrGmhDZjvRiFpzhslgdPyiMeHyaQCICXKOF55QZ6sa+C9DkTJugfp2EZQIga5LrSTc6\n3rppuK6lJ1j1+cYnKipG2R5TcJtZYEWShSakYrnc7XPyQej0Wmb8qjCXO+hZmkIwnMTyoiWGBcYM\n09bc7DVHXvI+nlwPUh2GB0OIBveYyuUVzALBfiNkLkfMZ4Rqt8xNNMrsmVGziDMhoQ6nUl57Io/e\nlClBb+8fioCu5h7vDGc2/iMQLvtjWVYutiTPp36vtvUG/FoMa5MrJ6s5MCEAqI85DRmzUcebGP4v\na/K9n6bF6KBPBtScqz8oZlfhCGDyFCldXyqteMR6RZyV1yKKAXiBunsqmukS0xXpk/0BUbHgCbDd\nWWxClazeNUXUabl4DDzfN82FipbyFe8ShlLA80QBEES3Qp/u2bRb2cx+nnqcV48ReQsr4Pi9H68u\nY4jtp/sti345Av+WI96CPNYanltsmSKatJe4mN4X04++5oxfI0B2IOB6ZrHLPPB4LAPKz8/FiqsA\nKrIeX7V6Rw3X6sqlox+6PvJcpK/xrO7wCPcz33aZT87UVbK+rFka1xcQL+8T0yUDvGoKsX+1SygW\nWOu5fA6jInKD1e6gct0HWVj85CMVGApFoaCYCY+wKsvxUnJpbYgdRUMDayFyYOcSvPcuWrlc30NT\nzHXrPRalxD56Ym6Q3gTiEtvwj8PegDnb7EtcZ0uwjK8OCt/U3HrmFEscrH8i1q6alcAPKtq9WK1B\n0nwlZSUaYz+DnXD+fdlzQl4B6DGP+z65+kJ23NNlQ3O4FBsE3CVPVS1jInQYFN1R/MZ/NDsNKcT2\n/9HOVf54MFx4y4KYpD12c6rt3mrL03cr0AqQpOjfGPOzxZAOsxsGx5pydhpitDOsT+YLpdDok65f\neaRNQOciBmskv3OvgyoedBPWUtssp4dZRWivjakHQ4nyzSB6LPBzdHKugKM7Hiagzp3TqwoBg03e\nocqaUwsmLbrrweIw/zClSv0Ybb4PA11ZEnYLUTtBEF5Nvzl7ygkiFthizCzrS7TZkkJYYB8ltUUs\nzcOKgYFoNkTomQdhNHo3sWyNjhqeCijCSV/5+PllquArtqQuzLrMaQkCdQ68163mfRWsbzKIUbuY\nLAM/FnMX8/HTvqZl8gSN1yOdYrn5yUM00CeA+ShEd2TiKPWygLaUZ2MTv1YbNQJTZJRT/XYKjJQ3\nPCmoXiiSpSvl1Xh8mrDaeqZI/CR5Xo+7ItoX/fwwHs9nhipM6AOPthpsCJGNSpl95Qd3V7BZ53FL\nDAc0aOuivhvZCafQo2FPwjV+wmeEEBvTX8fZ0KYdJ9juXbCU83XRxu37KZxX6UieHu5H9sDi3v7y\nlMOmlu+PZvNPh0YPNzUXb89xjhl/XkrP5GQB/Puv9O3TAheVV2l4vi/GbfC93y/h1eLsSzkIHVAq\nDQKexnt5GJrnKmPCE0z6exBRrNPLJRxivLXsgEfcNg40OJAxbtsiL57zWkswvcdymPifzKbue5b1\na+sAZQZNc0yCKa5H8zy5gqK2epyicY483zdRS/BDHGdi+H2zwcOinQEbWt1uv6iKjOin15tbfsvv\n7PidT58wPRvkJKx9xaeJApmPB0x/z/UQwCGQCSp2PriFN8Yqv3vrUlA2A97FbW8rAoNtU8l1PgPm\n67G92DFxvYzMsjrFLicOXoAq0jWkESzbR0DKPmaZKkIShNKFlJigWGDVNPpMox1bNvDMH5J7LPZ4\n1wWixDY/ZS16rUbmxHdvfir1t89trPgVxF4jXaQcsnokQwDLQjjj41WUeZR80CcrJ927rx+f7tHr\npWhF31kQEDHgBvQBT8/POvhWv4f/mAfNwYSWylKvRAH6+sPoo361/wxXsq2q8Tc5m36wCxhyKS9L\ng2Wgjd/tDIGqlKNVTMaROSrU8YX9sZDpIJp9sMvnO4p818XDslDKxx1yNDIG/WxWuS+1SajgzUpe\nihK4Q6cnKrw22SD76yZE7Q4vtl4EwPNAisrd1ooqjIpsbW62kz7zPQFK0I6otG0rwwZ5YidX8FCa\no5M3MgSB+gDNka6ulGapZFd0IpvK4uRo+QQMULNO7QIM29KsTg27G6vFaAOPAjJm9gt+1WYOE1XS\nnw9EOd13mvBVZ+t4t+TY7SwE8ThnyRJ1gZ2L7Sg//93GTdbdEDlFiPnIzARxJzBudVU+3QEXE/RH\nNCnfuh3DaThukZSnjIEG3hNae1YBonjqFdbQfd47oOPybmPm9X1U+mKxmuPF5OQ/GuNe8oxKnu5C\nWdufrxecSlWnGMusxb7gbzcFE7dDL/grNTD9vQ/JPVDYfXmsBbGUZm9unK3Vun0XjadGgvRH+rfy\nC65jgpDIrKeWZr+oQW6dRLHBuYKMAbwSJE3BoT55PXuOH/dL/QvfZN4kgnFmo1yI9wgh1SSvF0Xz\nHrdg1nZp0NStwjiZURc8+UtEyOO3lNFjC8djdRtJDYf44YQZjyDZQtd7jdIl+TXJD/GcWnzhynwN\nTGmG+RFMk81Hr42hNMuaghElfpVbtIJnJMYlvmxT72ptojCXy7hczYP5vFEW0g++4dz7DZyk0sNM\nUJimDy3CDpgimqEq+KtxF0vMeWWTt+pWI2pAwsd4GfxrDcn/8ApWymuXE2ev6QGhkHLWwvVP0jHX\nwQjnUKDfHwhhe5WrWbCdPHGiDLEZ0ad9baM8ZWRhoilq81aalMGswIzIEzluihzHoobJ/nwjm24+\n9Gr7OS80DeyNDBc0+dtxoCu7ro+OWvfxl7myvwwnvq+AfPzWUcPNnI0K6xgIVpngiSqcjaGVFudV\nQrunp8i+ykRRyNhN+sH7p1Z5bWV0RI++6WWCOO55zp3fINIipPizzRWzQaq4pS415l+BVYgFiF/y\neQPnEFN0XhL4MlRRZQ2C5cVkej4hQJoTFbXMCCGzCos+M/6WVnK0RgBYp1uK0hcpwPz5yEeRb5Zg\nYLbRBoqhm8M5Gc2PfSRW5LWeT1NVikspCC+zO0c+2XEcl74GBIM/Os7d2YPYnQIwphJ6tcGd6kJ/\n6zwtKae0LKo2p4X8J2/LXPKxhHToHjnZheRJN+Ws7bhWQb0awbS4RjoAgxQQ4Uq0atWMLjk0ui5J\nO6HXgVWzY+jzCoh6shHixW1+BvGwxUy/Iy+iUwU9AYeG5W9S4ZMOP0FKCDu/DhHOWn6AHJxhRDbJ\ngZsCnwtrzo1teetnUOZfEc2eqto9SeuZxuHeofUJRFiimCVDXSer9XnIc94XzK3r5aGLtlQdVqXE\nrXR58StHCXah+7I2Igw+8Yp918fUg5/ARHntXb2ToyiogzGS7wLlx0ZRPZ777PmBHNwDGr5D22uW\nEylrVhpmlgJfARtHEke46DXR+vcLzW1K1Z5GSyvnOQVOYaPE/VSF0chC1L8aXm8TykNWOsqqFHqa\nizB9aKBGwoBrzzLirm6b4zIbDOMD4bBsmTTVjn51LN57+7gUwWR0hF6KmUNuGDDJsPb12o5jdpC5\nhuzsXk/+le5CG90IcxAN1aL0w6s36e8xoDnShTDihHvu9Npu2hMrXXYIAc28kSLww2HdK5Yi3BgN\ne1zSyMky4ACs+RnGYvWHmP0lN59X/+mLcZRnObeYLRKpAzRrSNi72f7AU7LpdsxxQAQ6q6jKYEs+\nA5fhmyuUW3G+AaF52mpaRE1OJ+YKw/qLj4R7boI5jZ5P40Z1K1fVRCenPEFX6IEb2NcOlgNjLNCf\nfiMF5mYFGz0eamcRhM0RItlZkWNJe2Iakazklay7mW/V42pensipU39nBMx5fq8myPltRu6F3AH9\n+zWDsJpDTn4bTYZXpOwTmtNiSm9XnTZbviehgqe0OHUHFby+i0XtJmTqoqQHlJSEt7vJuZX643wx\nqEnZrxMcCR6p6psZwcxMv3qfVsMQtWp4UB4w5T1OGtxY5ACFqjDFli1CChYwcHDdP+LnMOWoJReb\nmrJPq1Yp98ZTUpmEAeIU9CCgfbLLa9oyCcHfVa6Lm2ZT33E/eeFer0L+PPV8hloIiWXjWvjIyKjx\nInZpJy47H011IlrofI5xNkU7Pun5+/cabxuuL6bFc7Di6dNJwwgrU/FBcutPz6mUQ9ATroMac7OG\nn8xMFAdWEXH05T4KcdPP1Yo4jKE77NYu1JOtTxbSKIciRZGFBKUXwkMfmkVSrio/6ZvPUSO1ATxm\nD8rndadTmvy5U4N4uwE0LDNlbzRBrQEpJQV8kX6Yi3njGLHUes0x6NIgE2ou0eMnsNiXggENmqbR\nXq/UGbY0yHLg5mnmEXQX2aJu2kj73Jqxnf1ie9QhkqxPTt9hDIcb5/xqpdnlQQCfdmXPz5BAHuMy\nyTpHpGLeAp7Q2VyDM+6T/k4QWVtnnQd4yR9oJFdO5c1caLTt5T+W1wBwgGhKtmqYsdb3dfnfuI7P\nnccUl9cC0cLt8jOVnbVVklyrsryIvWClOEhTSaOwmmsU7sQsFBPLDRswYednMSaz3Fr/ldTHIH/l\nRNf/5rPL/sepbycc1cnYhL4lMI8PuuF3TpikP5aV822eIq/itmBp5FeWOFTlsPpExv6FN1KtextJ\nlm8ikFNPEI/rvndxBE+5kqTA7Ut7SiK5OwIWlDxbFKX8GwaSkh6gxecLTN8/DjhU2R/uuTAZgWRY\nAHughyKHd4V4LKBLK/VNlu6xGLmu2RPpAlV5t32adrb9OdBS2BSqwHc34tYnzT8F5JnIiYqdjlX0\nCFtcql4nv5ea9dSEaTZm1TWJIl8yJanGq4vbxLknl/vgtBrCc9OF/ENyqUhEop4c45UYDpCLaAvO\nCDU+eJ9/5Q8DxVE9cht55IaKxVEhUAQjahx0UMIc9zzQWo36xPFw6efhpXmCPHzDgY3CirPIST9U\nZtJNO7hsvkRXUi6UF9k3SMoQHugIltuGT4oaN2ie8q4hWQAAFlHDbeNSIO/OzTZJFwRltUzW+eP2\nL6SjbIXFBbYeeGDutFw6WZHmhNTePMBDL/YWxwEDjtq1fD6ZOZYfWHxo5Sbrj5h3AKqAvjfooQdZ\nNXZ/UI5HRrK8LkB3d3OS7+8QedJy0l0hBuNdKW/9ZSV6v/aPaq73P5Hsxwub6HppOTdpuhc79mGQ\n/BL9pDmndVUjWyHcgyNkt+zcO9z6QD7PVAuNSZyCb2mI+Bff5GXfNbfpDPMpONpx7ky9z2+yr1dc\nXauIT4xqFGOXmBIPXbiJqIdb7ZHM9Gi3/k+4PBHgUknBatmkDJ5eecnrjZ26gwas6Oe5lVS5KLOg\nGqXTIVVFFpiYzK3ljzoiT0yeBqaJNI4pbjLfcboRyIF8VIWqoO2IfYdEhoC3o+i0Yl3keAXcLh+S\n/AXycHMCysu/X788u4qjRxfaxD0xjZGm9dunBZOgWm/yfFpUUIZE2ozu5nF8DUaEFp6vXVjSE7OC\n02fb7LzkwSuroCbayLt++NlPwDysNXHq0BbIC8BUW+7COg9Qq2NB2AUh03NHpEWm1uBZuBVXJxoI\naKTHQ3t6wWxYxXNg6z4TLgc170rTOlgGGp3YovVUcjXTRTHomEB78mYyHPLuCRrYEW2NQ4J0urgJ\nnzWCUwF0042xITA7DBxUAmoH41LK8eL/DYk2qg61L3MJAJUX3AAr98caLhagCUn01UX6enPIKQb5\nnWUVB56bgpQYcLifI2EwlpY7hK7HFeWXrHyhTZQnGd0p8gRSS8KuVRpyH7z0GeetQ/+myE/r3aOY\n9plLEK6QPf+vNoK30hqRzbsnu3cys/K1TggUEVmS4N2c7i7OcTTRe7S/VDkSc8ZgoQXnOpJVTsiN\n1v+5FUfsmi12db2BlUXAtUM9Iz+r/XxaciAzOgFgFHQfl+exQV34Ney9FwNtVJpwXFa0q4nIfts2\nekxTFNLzEAyhDYtgVffuOl4VnPF9BSHN6y508ESUrPdBJwXfHzV+jflurF1MCqX8G80p9xDud75a\nmnGZPak1w+6EfxPOhAgPm+NonRFVRM0ki3B3HZW5HKs0HGPiLl9Q3ZQP/fUlfHDCeKbvT0xWPKXU\nXXgxtu1ZNmEvyud/3jvhFDfmjh6AaCKi2XXMsh1BkT2a87E56X0VGZmscW8gdPzx2UvCqsOa67y6\nnIiWH+wTfx7jzcaZEY9tJhBxicXzVAkpbL7hh2Do2hGc83L4n+tKZ6IN2tq1FXxdUJmkVh2cLX2z\n/Jn1ixyJ9VdzWIdzkFKwLsA2QD7ns7QMs/dl8UMxO/RtjKahl4TZl8BTyQfFd3sQLIlQECEzfKX6\nJDKfd6WAXaTYDedLRVf4TCuwjx1rLab5XU4zhO8Q1Yku2qeKD+hth7Spsn+0i5ocMLoBSiCTpZ9h\nXn8ds3geBGqt2SPd4eyMefSzBIGx/Q00rnMIHHUVN3jQ2oxmAbAOTgsqd5GgrLdsLwRQrwpBZqsK\n3J6LAW5bFThJ8G66/rlxbFInnGCQ4yXlpbHslAgsDBcmk0nHvM9oG/RmlySbKcQ2zAlOxVrA2hGf\n+SWPpsoPahzsXFFJuAXtHzIM78ErCC2jCojJaoej3YR63BqdghIaE9nFiYcVBQmNBJCybtRZJT2N\nB2pPbfAVXCbVS9SFGQyAmmyOtB4sgXG4LYaMSgLYWttbh+Bq9gGUJaYRur19ZmwEqYUAWu4ACyAs\nHTjhc602LAuPwH9ZGwCO3EbfbFMT0AyaCqY0u6qW2OIOhNDjGVMooNmLyj2RZEuzlJcNNDOs9GYv\nKNrrEuZXcqkjZ5v0MjIkm8CXX9EpU/pslZMYmIYHuxUFOD4ZCC5htF4KHvR64VAfy8eJZnjElbQb\n+h9ZFi918azIWgSoWm5mPnDYXQUQhA37JFZMdLrBGVWd5J5zhrnOeweKYUsJOVz2UhrKIOZWpNV4\n1XboWeIC39bRJQh4+9g8KY8keLAK6avgMPrp9Y3+RV+gzucUzb8S14/b4UsFcVv0FLDeJr1qeYnn\n77ASlZSJ8MZZlEy5PH5iLp8xF4/Jcib7bXU0DgSOHqppPU01FWFAAFQ3pdS2vIaSH0ON07RDG9Qy\nDmlmF/n7ek/vZIjfOXU55wrDl0II6bocsUVBvIqMki5b5JqGzm28HY5AGgN+nNIEw+N1n4gzKNGR\ndOIN9g7gMcmFTls5wuBWvWHP8awlMGRvasNMXrgM1HkIis+Dm8TQAJ4eRFgDj9Iogn6wvT+qgShM\np1iCgj70yAabS6Ohq3JZtCernQSX13/S92WHEVe0YKTT0mH6HSdoodhQctB3XY4D0iiNZJpC8zqB\nHlnlP/RZft0zTU+v2hmkGePJb2ia/jfiGu20DZd6WM+8Q6cifUTUwureuHURzyZsx5zyUb9WAekK\nRW1xl21z+xTacEK2L8qi3EdLgEsZXUzhvr27O1QV+uIuL/V+/YLdwleK2RAqn5ROW42Y3Q56r/dV\ngawH4Wl0ANU6S2JwbGBais2O+2nLVwhLQriUcyYNXhuWc+7xPwsAyHw2R9M6vb3Kkdg4Wcfk21NJ\nMyVY6REt/UBtqkC/hYVNoE5n2qhGSpoRWVQQFCkbew8WzBWOZdyzmISJQDyy3b3BA237ujhb/uJR\nzRuzsGaaKnA/cog1unB1GU2VUljglPDy7n3Hesx5xosdn/gxURO79XFk5S/jzWaPBJuvpenaFFxr\nyESg/K2qR0dEvEDJihX+2a/GkpGghU+ZhezhnC/mapM0ykkmzBxUwUrSc/IMUWmpZCpVJrNLVYOF\nnJSPS3KIxdL1diiYh64ICDSHr9i7pqKueTjsEK67qlhAIYCk6xXck4I5C2kRjRThjv2EHQxOR5dX\nVe8XbzrBwIiyJvvCxm3g5+EPCt0b6EwYALvCH8WAZ91lCtTCFqomRB6/dUS23DP+Sx0y/QYdr15T\nRZTWH8LGyO1E1W08SYbUFZtMUnNPzcykFRMCYI1IUWLBJXMMPtiTWlyEltXCCL3kMn0AIwnYyFvJ\nn7SxCiA1qUsD7CWrhRpOU49dneEphwxJeNyz9bOUGxcuqUwJbnum1eH7rAtSANIQtNZaBQ2Ke6oJ\nlzJdhJE12MRV65B4Nsd2fZWUUTBQM2uXE1k3NQPO3xQ7bngSv1sJ5so2zKPo7iMSdH626ljtmqmQ\n4K6QlEtlWL0ryLMVOe8ywCbeCs0+KF6DlQTPjvaRIFgSf+/XUxGSNDAP67Ww6HJGJvhnJeA/bOtW\nkC1vPFANG0f0HbgdV/VGUIEMPfTvVWQI5mO8xP2mooXHRsBUytHDx6Xaqc/F56+ERQd3bsJ0U05A\nGY73sBTAXcfT80bail6td4LXnB6q0mGIcoRpavQcXpT/crKmwSJau6UOwwVeuKIBtvh72mAKOXFI\nD4jy7sk43ZbMnS+4o8p4lneUY8fHwRlAYDs1OFhi5nvGUjqRfrW4W7D6NjF/ao2Q+RWVwZYgPhmu\nc/QpJsPsoyTZyPYiSI6X5gQQRwgy6PujvtJR2cllkLm0y2X4BnRNbQthFy2DGmlXwV9jKpwHwCkQ\nNUudN5MZ7wkx/S9/gtj2iaAZzFSlyGE83QahJLMkTHh99PnViB1VScVdloR0E/9zj6HyijTBtz5c\nTvpFgdEm1VltojHW0yR3KPsfXBPNvV3qxZGcine3CYB38XNAoOpwQ+m9KiaMjpS+Z3g5jVSvEPRz\nI6Swyc2GHSslRqysHLDmqIFkPYMglv6rb3SP4MPqxcHdDQ42D2QUrIg5QGSsCFVKWYNzuMHNS7MG\n0q9S/CRSYZI6pd+BdxF7QMfYvTxG/z7SX1Y4He65yVsu0BUGxVAycgESC0yqDb/mPS5gu8ICCL/U\nKFYEMO8VavxBguJHpSOZqgfn9uQPdQKICYTyk3gkYwquOIgMeAzUERFY9rDolU/bFQBcrEE04bCl\nGbT1w4HHb2SwKQtCKUFOU/iz1/RQhSELBLKUUWiylPcK8ah60oQCSYEw5Fp/BmjNb6AtVYKSP5lu\n5OCzixPZqSYs/qpGhwGoFduI5ihI6wWRCEmtDWr4fn/VaQEIhnrCOaWyCB7dopkGrzthw/KTqugv\naPwLPvra19o4S7x9snvKUE38ohqiZ3jxQqQhD1jzOVB2BL5T2OlqTN20EzxkwlLulKoNVmKAloLu\nK81FvAwebD4TJBam7Dj09uvH7Vc4ovQsnweC5ZGwKQHDr5l+KYUTpuzAV56b1L4mWVv9KC1AuoWR\n1+u1AypMa7rfYuU8J/YBsH3L2l90hyykLH38XhVxAMQfE+rppwXmCK50Opvfu+3464I40J41o3/U\n2ukQgp2CV4cEALbpyBdHPBeTVEsGU7XgzZjhL8ywTq2g0uOMdr/GUHvajFz5WmKBD1Kn2/A48CSp\nNOF7aTFa1MO+YxEGpsbEGFzGwB/8DZSAS44NI2IJwsH+Pqdb5mDPEp99GepNImg4ax3xuQ5/fmM1\niCvyST6YzO9vDztRrx6DVty4yCz18qh/CBLLq2VO5mQjtLwx3EEoU5WRzivutrc7rYh7fYKPzW6u\ncMCbmpHfD4KjmtbzdCp0jbtSJ702e3alBxvL3fNxgtubgy1qwi8RdognRQaW3lJmodwMVdrO7qL2\nATWjJoDQ7N1vlYlF7a5JdHlqQdFmmyEZOcyxul/lb+66+qwRWiA+s/AxFe3OmsWkfQrkzcrm3bBM\nYCgq7RiGK/Nyg5CqZcFt6sIPEbjDril9Rk9eyfW6+rg2ti5qirauu6GTi89nmG90XFTqbWa2INSi\nu/+J87FDqz6mNQjHTpylfV+unw/2zp2uejZSOmCYg6slgJ5VzEmbLA/loWbbF169Jss2HKsqkJU1\nFDucH9pO1HhVVLLAgvzdWWSWVqHggZ7fdGPKKbND/q0DJS/MlSC4K9wc4d+a7LVqf7YfcArWJBSw\nb/CDJopZa8X7vfppRshZdLKB65dkiC71qdw45IYggV30dDfgL4Y6lqB0d83MFZ2fWmFGA1k+6opi\nCCFPqhmIsVyJwa8YQWio6rNR1n3Kf+cb5LMmmvDH08KeKeBi94wzMkfx8HbU3C4pNA3tFI8HU5lu\n2zYjSejh21ePxj8+f7hNOWHj53eIVwlGFJbeHtuOPKRCUR0ofAhhjWRTTqd91EmVEEKVQGqTsv+X\n0Ofoh1RZyKvBRJFf2qKEDx5HrHBNDup38TtEIQw5seyIR2VVWs7VfqMlt1PMiNCEK5djB6+o6Vq/\nPx0LnlJneHZ4aPg+7Jdx1UYG072d4qEzCB1Xqg37CLd3Y+xHDV+7QDYT75oX/2vO/RsHH8+4CwRy\nrw0knqI4mwfuKMWauSJU5fNvt6owB+BumMxKi6CJn8q/Ahp/Qkye13tRKneKn9RIxeKkXX4bdp3U\nPOdPMfTsdf5FfIIT9fsBZk1q+DN584O8YXhQ/vwoYlxkO03yFQy0t+v98xYVtoBWsnIGcVXZNaGl\nFp1BakMoraD+DIttVaUf0wB36pUfnDLTDvuHLmpgk2XG1LmVRvfdZ52WboncKChN3klluk0pt/AS\nKBTVmhloAwycTXnHnam5GBIjPwPDtu4qEf+m1DyGAo4egZXTy/t8J7tOICSHhwa0V4icen50x4mi\nF+80cHQS+r6jwF0I6P1+0waqv711ZoZ9e8OEeCKtD9cg3UxIbQHJ//qPhG5GqYQ79nNCUcxL0COr\nSihjFJOyM1HcroFKCiJuOCu56NDvE64S/ohFW/8B1RyBPYqcsGOHDusP3PPujuXmd9wra9whktlS\nDiBxU69cPygcHZGCAXvFCc6/4qczdg5RBWeH+cTSnEQ+LQqWVNL4KQSshKyGpjX1CQtCARE3/khz\no0pMSYSst5xKLVspDiAYAYwmHaMhq30l8dct7s5EfvE3vTEOpYsUgzkK5FnMpTMQm080koGudP7x\nS04xhfKQ6LW4wSxG0WxmHIr3hmuVc9tsRFZ9T1mIH5KgBBhi7XEvYeFSvhdw5utdWBc9yE1bV/IJ\n0vrEHBdEJQQ1jC3JHiDeNsWkxk/8VV3v1QMAB8N793KXxgQ/1jEoCwo4r+DgCws300qN53E2O69u\nJKMVjejhty9xQp2+lHRIZ36dvXnVTUpvw4PjnRr6nvdxbkar40A1xSTwZtOv035brN6W7IDeKByR\n9CV6S2CH6CocTKT9Zt8vPpltk8xGtfZvL6iP8+E7DEyTKpJNSbto6tPn78lb2k5J+EbZgbkvLq8M\nTagu9wcsOPFmD6zm8ytmIjLDQnJX7Ly06AkqKfoEgCv/RX3sJDmhLxuUrYN2P/XZyZEXHtLmfjYB\nsIWtLwccXsmc3oVsi2Pq7OJa6yyIdyX0Vag1r3cBSfGMXuhqSEbsGPpHGQAb1bemX6ZL+eaRR8Ir\n/eZQNuhoWG52LpqKtzgzdwYD4dXnawZEgrqPm6go4nMxHajMMT9x+EPRWMRCblVLMU1luSH9kaS8\nMkIoiifAeNimveh9mQ9+m9uCae7DWwiSrDtGe5S0aFDcbg5demK9BS6oJ2C3dBToRiv6isyitqJ1\nK4hru5Lh0iC4ja53Qd1Vl1IsNzYAQ9eEtiubhzCW0UnxLC9l1YlHe0Okqfplx0X85fEe2NfClZkN\nMVvns0Q6cI1RCZoehNR7MEbMUb9sf+YE/zd78entJAGGQcMvgDqc8GPH3Ph5iq6REzmUCizdjv0I\nQuRHIwhl2tSwe3c7oALp7AMb0UEUcEEa7yNBMnSZAwJHxxIcLHifNZnM03He4c7JsB4yGdsZlDmm\nzZoBCJNcbpyRnlvDk7moNefE4BJO/fNaReEAiICWIlZxQA9zDxlf0qEz2FZgadqLiPvXKd0SRjA4\n6iDTL+0XdstQT0EMQUdeOAiDZ+gMhw8gXB9TUZ2KzJmzbfZUOKnt4Dk3S7ZP5reZ67wa9T0Iow/r\nK6VXvm9MDYeTLJlHKJb26IFas/UWABGe7CEM3RCFR5ryVylbEh2frp60MtSfC0mHZIPj4PZVdoNI\nNiG8ls6YxLThfFsXWp20HODlp8vhiepNTHOGoXXKgqoP4qHxUDqUcc0RwU3Qppj3tAK4RurMczSz\nhhlq8xWyWv5vlyJxmJzk7hfCkbradsEVNkfl6K9Oahz0QpXDpQf2iFIk6sdPbjligmhJi1mM1nkw\nG1OXII9kBqnpENv9N9RSHAqqC2EZ0rpCoo86Ow5r0oOJiUmcc65rAomtlFdRFu978TKuwgSK9C0+\nlvBiOfqqfF1RXBAt3OP8BIZgKX0duUVG6lxYs7unXE7WrDkaG3V/VbM8WbHectyWnEAvRcw0S9mS\nDdiKwWKoS0qbSDhtaCGXzhWMnM28+4kegOOYPbRk/Ztu6Uz4g76nX9OiU9zuNUq1WLLjEKfHhK8a\nGSK7TjD0XfBFlJBN6zICribUSvhRDQzFzH7HC5lKMwntykOMgHH5PeJ5U6E5npyoaAjscpk+WPXA\nO7umsA3PQlzkImQmqtskI30+FAMhso1bisaFVT2D0o3MCcuLkhHfMWr+6sIBgfjsPS3K/nIc79Q9\nW78xWZMkiRzh/66GAojp5UtmS+9z0Yefinic4ll5BWvFt8Nji6T5qr3JNbmRxSLIrWy6SEQYWFbk\nuvDa9GkoamiLQGh8cxjQYiz4sGUOXLRClIx0n/r+aCLxc1osC4zXCCC/H656dE9KpcyrxrxNNjGg\n2Q/qsDxIDgLGrTldEhfzYQxCutaJFSxO5+lBXt/b35vFIgu9EBtQDrf4Yb/vRBnwosJ4EXFzhc3t\nCGxZRFmfJk2EolT7/9M5D6mI5D69lbzOGLfsas8scb1Fu5WzV/LVcuhOFhwOfbhxdKjynFeYJIlM\nMg2Y8V8wIoqQqw/LaPQs50OVfuhNZMfG9jmA+ExAZe/ucokZeZna/5j8jVI/rtQkEIg3A9fboOJs\nI3w+MI485SEWZ775L/kBv3b+b5mquXpb/LxY4Zzek05EvFEWOdHaJHOx53f320jbIAufGGFQ7S+r\nMLP5o3+SIoY8UWBBcJL/pLJPPMXYzHLYwo9sUUSrSNf91mMHDv+HU0Wh2eySI5i0INK9gBkxx1fe\nOnym/qYScFhvYPMDuq+TPTH0iEWD46s7Nv4wuIOAq5xV9O3uryeKpUQziY+T6z//hsGBBWNbBl8w\nILc8gwYVkfUv/2L46Ne4F0DRSMim/kOuxiN/MLiwivYwaMYLPCHBYTLCq5EqNIO7UnifZgY8GmPv\n+dI7bySys73tXKSYwPwdbvMeqWjgnm15QxWxPxnL31tSCh69yHnuR/2UDjSIAvziXETZPI1wgtzH\n4zNfH60m1Y4fzEgIkEhWL20v/86j2eS8LajMp6wG+zX/SH0ofwqc4WEYNTUUVt0txzLsY6vccknj\nAMiGAZ9WGwk3ltiCXvSiA37xd/64b7OTSOxdAKC4lCMw32HOZK16d/EHl772X/CW65LGXjBwz+g0\noKGa2hjFuaO6U8i2AJDZO+yb5Md2Cr5tLRbRSWmk81RoMVUqIUbpNRAsjbXUGZpNblzYOeQe0vt1\nf6PxfYHe7oPrkpdbVGRb6G25F5Js82fbjUpzX2HDdU7Il1twenLOBN4cdD6eLejdhO+pwQdYX1pB\nQYJ438wpPpXiwEpSgmIMlspfG1mNSTxfdEUAHgFRWzDvdbBaWM8XFSyfjpZSVh3K0/L5Oz1KaHMK\nmlL84qRPVU6Rp+NoD29VfZb4OyRsO4UNd4pduIp4FeB0TQVM95pQ6okMDeNIceKcw1O91PWKden7\nflkLY+RgDV691cdU4QbC2BRx5asY+ZiKu0bEWOhkJH2/KmRJITdtA+7xavT839GCEWYZCM3YHo6B\ncuw/VqDedEV4xND7mx0bYG9x9guBtGVTHiDTyb7phXjVe7Fyi/x5t8VufShAgo/rtyoswiJ8BhlJ\niPsuCwoul5MxCFqHLK5B+UZJqSIR9/1VIFuGceMk5Ubv0d1H8Z5bPpQwCvdfLL07qvjUEvpa5mUB\nuJJkNEG5juaNM0/IUY2FxPzrNx/PTRIjl9LuV5dlE6NhxpbJtZRWPj0lE8jjK1chUV+6+2I9lrTc\nrJ5rmF7L+wbi4C9Dnp2x2xYaS/tE0F+VimsBt7l7B9bAarIiivHNFgTe2qE/+Kb1M3H1ct1Hqjm5\nAL1YaKcUqsQLLnEvw5cPBqQ8QW32XBuof6yn+xxK1EOpb7J8gdZC9ud9Atb/F+rDUY3Zk042VOJ9\n+38BfXth0Ew8oVZmdThyt5KDvzgcpYhgHwKbx8cB7uW0LcTT3DG+SLkqMgun6MwLUownC1+r4G+k\nPOYQgyWZ2hwdrVfUEm2FQ8T7jIjofPdRiOV6vMIyo1LQtEHryCdfVlFdMVkX+zEa1uMOonNlIG6F\nqlwAOm8pi+/BvGuB+BRrikGczOJB0Wg/rgpg72XrFf3i1rneXsCsO+VpQRvcvl0H7+GloQpZ8e4/\nL6/LM7YId2uE/6LP5MJwBkwdYhnQeIBRDsaT4SqBqvFFGUwo9XHQ7BX9hvDKJNNr2WJx/TN4DGSc\nQSXf7zNQkznf33MkIXuht7XWfQq0F2JDmeO2vQWLYbSyGuKMoCeZqlWTINTX0kKL2gXogQo0CSFu\nl3yJUjzzXg8kxWRp881QDeoh0QXJzkJlSK9RcBJyAPoGq8MGVQnhqlZCaCtKwWjxXPJMod56Ofz9\n6d5QEnLnZTdUaNX5elPnAy//gVbggUKwOQ/skaVSauu/sHjK5FOnEBYk65Rd7tYGD0NeBXwgdzq7\nZjElbS8KS/Cefr+77JrYrMx0aZBZJ7PQi9t6EAB8LJx3ynPMFiOi1mFRiRTnoOunlquPz+IQPZCz\nMGnV/sBJnYWAFfT6SVllXQSioS/rUjluR4vovLgImmCkRQKUSj5xnZdY4AVssYcDjdo02+On7piN\n8qNFmcN5E7Yf/TncOjvzUDpXawtm4XcUunz6fz+TAFwd6SFGP3I6tLXK7Ell/AJ6615QZubiMzMy\n5isLZteUKQdn5qY5SU487hB+j5EiF/KIGAbITt3VhdHrimshB5ya4LsOjyuKLV8kB/V2FxEcrVP5\nlPsWo8vJ/pCG1SE+UmhSQrWcx4/NM1rtR7bCmMtSfeu3ZhArzYJK2EjxCmwxqxivMXGcsAByH55s\nRNnTvl30k066eZStn34hQlok8+Uj4MJAmSuHpOlft5Cw/TOrk1MOZFdyyX5HyQGbCwAhDElXG7Np\nNtIBPPZERmcalGEy/Owm1PoUFZGrD0ygMaJgnLTHY6MLYf5DaqbqAsq33MOscg/qw0ro97IvQveu\nbVHyQ8dKOw0H4XCakKKp59qL+Lo06pAmqctYoqEAI6NyA5PBetT83h7XnqI61qecb+efcMBgjAHx\njfy4b1SDC/HxaiPhae5rVoY4Mii9nQB7tuiNNT6Gmu1Vwwpg+FqVEjv+kwb5pFPKdcoYZP+5TaCc\npfDutBLUv54hLF1z9ZTSVfm8dhinFIriv3FGv9/qh+OBVnE05kFf0guuqhsiraGuH03jxhZjWfyS\nOaM8SAV0mGwdime6bWsWIdynqw2HAyQx5ZB4Y4WQMUkJTUZZqfnyJoiPtmujk+CkRIbdfqOinQVP\nO07DTJxDEzoF7uhPsOTK3EFXwpS8pYBJ6rBUpkDv2cdF+nkS/+/cAXKl/YHTpBgNyZhjRpWyxHsn\niFcLNNJfu2sWWDKVydWGDedDKCGcvqLPUsStmaG3e0WUzqYcTIcOw4FcGgqM5B7L1taswxouzywa\nIj0O+yHtm4lcDaUaPBH1jpC3Tx1teYcGoV9p1KGhmnqYHidnh8j5RR7mQphYOBTEDhrfxBok0oZp\nxEb5R0n0lHsnE5wR+R4TmYpqKaUpaZOnnhRH5vBWzpvNoXJZHsCXpiaDJFAEE6vHItaTa0n+jLX3\nsAKceIWi2N0ON80jpDAKDd8n2CWy5iOPEydoKV62sboxWYLHelvWFOVdHFqza9cLsXbUMPH/vDsB\n8zUXcORUvcn7XjjuxPfPOc0t/Q0dPFlQIuhEr08hTBnRjrrlpX7+x6ZTY+fPNHR9F91Pv0fPWCIy\nbROzbw3bSzeY6s15+qHzXfdfy24+QkpwFfNxBLscbYdYMJuaHRfUkYdyiSvy88tiTke0cWsJIgL8\nb6LF55Fl+0MmwuU9qJt6LFzPlqMjg3MTJMUSxs+oM8M2Y5lbhwQwyifFyhKYtLmLusjTARMM25Y6\nukzQRYRNI3Oxe5UbT7SrcwTUy1Lzewof6EN8wyjkP5FSWkYNXeMzogCzF/M5OPrEz3P23auJXL5f\nPSwxg5GwtiAddrpoxwVq7t/SXomVKF8qrK6QHhSEkffLcH8rFeij+Eex34jAGjtyYThMr2yAKAjQ\nvo4wSdK/C8Znry4ZN2XvcUYAMID1n0uTpMVXdijFIGLqamf0k6GmXzQ3UpVfSzrDS8bynQPdLLGI\nuxvSeQyS5cbAMWmj6MtbyYyhYMLNeIGeHc1Ble5JKk9XcBOCCFgzOOv31ocUMajLFqBtSfkqRVra\nFJiVtRF38mFRo9WKRHhb8sdoITC8hS2CTMQSsxPCAmNaVD2bJ/qFT0p1EZZq6BoZITEqjyAZmtZx\nXqR5qhQI4oxW96jPl+BN8zN6fFGwSg8Uc/RdDO4jXwwJaU3DhK6+dMf6pj/dlOYkkqJWJ5zvJtdI\nN/rpUYECSK50BXCzYV95c0h8TYbjLL07Bo0wAZsx9en9mAAJjFeW5J9b6bw8wSryqIlFuv/vii/8\n0NeNbQ3HukqaJ6WS8ig24kNpl9AaJTw1mevhFDSLwa3iuPULC+87SJhRoIKk7u5faUsPh5M+BdS3\nnwwNBqnyAL/eoOxdZGIbuQgqWGGzqOOHbG1kV1nNYc7Xp33yYYqiV7WseZtb4ifQcYtnIMXRuCPs\n0HNXHhr7bZxfYss+z0D8ocASvnpOL8w4nlKT2PiLsJ+jpVGuGS67p7kyScbgWATTr1CCJkP8hlGI\nMX4ceG7sdnxo3SvwA743LtMPEDxxTJV+J/+6w03IxGuA5NzYdhkU5Br4pGMfka9XTP8KCa/gkIs2\nw9HFq5FtvyOmvpOL4+vO90uK7rMdlqzeGa/PolqIB6YyPVJKLa4IIK9yih6/HfL4Dr+t/VMfsX6r\nwVNKcvxe0cS/qHRNS5g613kQ6UhUK6nbWfngwumJfxEVujPsHnfwLImvXV+Z0lpohVidsRwRstCl\nypmA///VlWrIIEfM9ztYImxJ+QCWHceJt6eh32pSrS1Y7CAJmjnpYkmyNQzNY63+27caRFAiePJe\ntSVGh1aHXEvlFIm5wia01tXhKIajPWowqppLHpWsZQkS1rJJUM4r0e11wGleAGGxpzLFv++3rRZV\n2E7P0LyqAMCVXwuJgbDCIUjKBeXleHsoXTjsTJ0RcfA16W2S7LwZUHCmJVq4hjScokm5x4LP6eKu\nnW7YbxZKQNnAIWffjZAbiPXmq2NpSzKlWV7VBEHvhB3WX+EGeM3dY6Fg0rL393oyDKouyjUWwtJK\nKkxwPWhTHPfGtMQHZyUM25PNCS9dRLKFvj+8Yuv+Cjbmf1HTxuUHNkIppVMhe3pp/EoYQdCKYkf4\nNmIqgPEpc1Xw53xrv3c2+5Qe2RPVMCBF8XCVGS08pfg+iaC35dIcxw6Arwcub7q1AJUHYWWH3e17\n++/sVHV8krkistFmP10E1UX/+MJ9cPXKZtgTdfX1nP1wgv2fZiV86BE76jaU7foSkNjoqQztHEvH\nvnjg5wHfIOBGVzLQvSsux2gimvtklrdrQeNtEAOAQpNS+C53UQWER5i7GMN1FpWJmOMX0AnM0fdP\nN+AUFHdOIyVfThnj/V74mNf8KRQZT8nQUqmy3LgdGQ7uPX4esG3SBEeLh2JSQd7DG8Rzy7bzFHcT\nR/lPn6HC2RR7J+MiEZbxOgXfw5CazrPTtOwGqDjFroba3fEyK6BRmL6ltjB2nnNbZ3QMS84Tngu0\nztlVsUNRQ0vVqF0YHm5Xzu/LFsbmB7GIOauNfKOdAPUZ9+FyQsOahJKfbgvle/vzDZKF7dJBesQR\n7G6ng9CIXGpMPYE0Je+/agXWFSxCKueeO+bxz3ykBrwSkZqafIocSh2im4U+LUrsdQ6Qg5KHNbvA\n+2ko1mWue4ZHKFv3GFIz6qy8sSdD4o1YWaRzp6QR6CuG/L0GNdQmSRM22JvOQ9ORJ8zEvxHKtsnC\nDDxX0UtcYsOlNPodlxY2wv52fihmfKKbhbhMpFY9wB8xvbiq2ZD4NKhflfFlzzNjsaAJtm07xKlJ\nvemry435VhaDY+TdxjrGnAKY8dtM50Zuw5GkpQQl8/L7DdmvUu0b4+ozCk3HZICokDOSzb1zTgvU\ngwko9mlZjy6Ro+IL6CNR27Huwainy4TT/R0u8/+5Fv179JNlvHyGxYXUa5rJRKrKic7H2nf4dykH\npcfDPpPIdH1kEIrpLaMjMoIsf9ypnvIpIO6RdGv6+Q6txwVGizW36oyiNd3BGZXe5F2CH4ImOqdT\nzMQ3d6iYRlIvqU9Kw5Ul/e++X+NLUudXHoAMRCPNbvPhB7hOYnKeR40UYNCDjm3KNgvMxzKh4Dd3\neQKaZuo7/YToyzwW/jjo35H8jGygVz0cA4hssv3j0DESJpsjI4uINFEqYK45Jn4fRPDMBxpU0V6Y\niAEQF54vjRcFgtShdk019k5MuVKNoQ+6ioiLfV0VtqEfVItvGAa9IlriFbDStqq4/rmdvZSArMUk\n+uF0EFdygH6DTJhAGoF6uE3zm+O7VytcdokHJmfnvl+LCSqwm2E9nVmqp/LTVl3GOKTP5PHZPyHE\nKCi06jAtv4vqhcRfdpwIt5LhZiXTuDrW/LJOqRdZXN5Lf4RO5T2gjYjgq+1ujG4JBq8ayr4Jhmky\nRSYp9fjRtfWn9lJAN8k+AdmkvXs8jy7wF2739kvWDAN/un1R/jxWygm4VjmCETmc3tgWZTBsyj3h\ndS7ip9ZGkO9ob6spwsAgTdxMfvK1vrx+UtwMbTZXoYLsDRtOHOpZtSlwqzdwlfTfP8wqu2owh4NY\nIMFNw2uV7x8Z19AnwHVSVg/+LRFyuUaDGsY0Tx2w+AWOhecrWJh18NUOCcw6WYG+/zLfHMsOy0Jw\nzbwdo+ynwtdG7mf4UVXSsr8vvwXKUGLzH/u7HLX6ri89GzLPTloHlsDEKlwnHWE+ElKuvbcbSNLz\n7MAhzh77MOCAOzn1JWSviNo9oDwCiru+wmYkeVGBLPncm+tbZi33xvyqZBmfdAiF26M8iEdZ0fC2\n9yNPdv8S/uO19rku7PiiqZvBEsudotq/zr7KC4V4r4Be4Fi1bhMPs17pJKEbnnZRV95jnZZBbWVl\nB8dCXMdwhms4DwWuimrqylqqF0BkHLvolrJ1PF4O/vId65g+6REAfD0mWExq5NMxA6QraCswyXBM\njO5ogsRfcuZw4y/Uft/kFMIM83hr6URIolvB7wRczzYNd/L/rUCnaBE2JIX+ZGd/Agmvy6lyaeSg\nQDDJ+ud46UMBCh7q2VG6ShlCYR4MyG+vuI9eUoHQ6OXuK+5XogDKPl1ThMXtIbZR37r3hWwh1axd\nlmfN8x31WfLCjsSFuBJExJkMZ5INe4PrSVpnMhT/MPhDbvh3TfPx9q/rDwDpqNlXg/4wsen236QP\nfqYOepmKZ/R5cPOjQsQp1EdDmykoEBb5vKZC+wJ2Ni7GDDTyuIUczE5uoWPFaOeHshGDmqpAyi0C\nYF3y8L311F3BT0yRTvNn18HPzKtJTn/lava4O4X0UK9gmPS9IUpRzvG535glq+TPTBeNNmMmjpoF\ncK043+6zBszbg1lgYMvoV403GptiT72C7uIAvpG0g3jR8ktV8ITtR8Ho36g3WEjUWFxurrhR5I/3\nMa4Igyi43BjEzm7f6cmxIh3L6OaadG2DZ38XUSedfRuMRuwWT60QG0FmYXdeGFv4215blbNsymcm\nk2mIDQbGDk/Qybmsoc7LPxjQV4G98NugY3JbxzfgqetsT99VhDmj0GBIG+LC1hlb++vcKjraa/C8\njN6NZRKehIkIZC4+vQS6gw27OP4PJrkOkXASle88FbbPhxozfa1WyIQrOq1xIqmLOHigv/faefeW\nAxTVyv8ScMVWcpI+jLJLLy4a1Ch7/HJ/igiVmCHlJm7ckJMbgtBVztLXQmXnjJTL6Pynsx6MKv0l\n8BVbVKIE16HLCsUqMPkgg0arbqf7yDPlygpesUhx0cUmFWse8vcOA+1H06P+4dycC80KWTsmPS6B\n5EGvU3RjL2y74HpjqP3MRfZBswhULeDpxvyXTaudo8034t8jEmw2Rp5ffDKcalxJbexN0612mGqK\nXqkLlz70YN9vIddrjYU26o3OdmYoBfN5cTWD72Re4pVTTuUqJ1HEE8xye8F24YDscQOv/4SaVieW\n8xM1S9bv0ifD1RYJymN5BCskUXl/bB/maR9C0MzQ47TZprWfZ8Zdhg9whQ54UgBUNuESTH+6DGs2\nACGSy1Dns4Y1955iy1Q8actfsbkIxYi2/oNqHZ02D2Xvwg3tHecFHzolEI6SlfAbGebSE8zOPlnO\nDk5WFDm7R7Ya9Wzde1ycw2/dEPIiNXKlzF14E2Q5XodVnrcpMwAWMhgnnuHIE49vs6jmYNq3GQis\nlhQUwP/dNeK3tPco+bLYIdxZJ7pWhl6d05lMr3MGDeem4/Cpl2QjnO3aBmxJ8J0XA9RR8gUjA23l\n3vpbX7HbQi51qCNjyhGK1Tmn2en0/fGcEOGhZyyCvJH4Qo6zB9uGykWijrxVWG4RmvxqKqqag0FJ\nDlk12cU1XziDHfGXtE4VhXARzXiF6esJwhhcSD4ZrgY1ji1RUxpWB+b4TuzJKPDpWO79abKalORo\nC/stTdrUrz/piO2okmJ8sOj74MQPCPxN9rpJdhy2k4LrMMhDh1kaspAmkqlclPY1falbZE7cfe/0\nin7NtWeOPQrKTl/qhE1qao7k6Ua4ZeGWC5GHaS2ipHen6ikeqettySwzRKBmkdDQSHamPY/wDQo/\nVo5THKpvcnZFmnuRDI9gsWrl2HV8Cnu3cziisYvsdFyyjFJlLwQI080Hm7YI3tK2ujDpuxu37bkd\nVnshVjH6Lm3O9gsdW5jBFwOx23KmV5lftiKdYyRkiF2iMjSw3tLSSlHQ2n29KzYnL1G/26FjOuI6\nmThzBJljDQuqaE3P8+F0mWoEBHmZCjrTaPb/too5PFL5RvZtiGun/PNgZX/pUEuzDeQeX08IRmek\nEKmkvHTs/bc7f9diRmuKuZ0H6KhygPZAuIP+2JJ8Zcy94C0B3pNqkm7GypUhQXN7SZe4ND/q67LO\nmfiUWXZhCIigT7LLJt8OkggXTxYdk0ArF5AA/dHoUgKcvhfFXSnNFzcF4C42BPgt5D5lWQUDipZ3\nQ8715I9sCHyxQVihVdsS/jzu8jW7ZiT9fmouvloW+afVRWXnzp4xWrqsHwJes5dBP+OMnR5K9XyV\nwpOQXuAExmx/sSUECT2cwytphepaK9GB4+yxMNZU8XIqfaawkSCeupH1jiH5ztVfu01WsSVZL0Vt\nZ9G2/wCR77e+YWHiga0WAuSbN0Sm/kAOZTbRQ3Iqu2L6xEwsAt5OufgkCG3QWEA6ZFCgt/11FtNo\nWCg8dspVc7wjJGcaQh62kkHOHeKyQP/GPfc6zfn8ojkU6lx6BtJUzVc9+5iSeiziOxJVcg+XiNfm\nry1bTBPVqs9V7GfXZMNMeTPpqgwy/SDSL7PSaaGXTc51e2rpsZPCv4PWW+k/3SAK4kBHSFsXoFai\nlWnFbldiXTkPzBByW64STapLmZt/db23NfGWmSAgnfeLy077nTB6S5VN3QJaubOw+sUFq8QDZWhq\nJlxIh/AxMOu9CnXuhl5COX2kO9MnYp2ibQXZjYB2Uz8GzbRh3KOr6O9O6W3eiJS0HmB8DwT3eBwt\niH4rzeVRFdnU9sZW7iCshmVvJV+XW7oEo5D+mVIWBfKFAxW2CN0E7mi2blglmwl/uUoXwiZWTQHN\nkhag0uDa1dx9iDbItFz0ff9B2+bFpQ8AkwoXj77KoRfnZlVXLC+351BetTTY9QZUbC9jM5kBy01H\nTMWQkj5fvhJ9zuXsRqN/ZPhdJDq6JQuiEcgl4fc7vL6BcDmgAMISZNEBSA8QIcAwmMU9Z0K6SvzL\nNAwuXYfobpCOxANwrbOXWCIRHi0LUYEAp0zpK3AeyOedeZ68F9Dx0fhcv7R5k4sHHwUeJ8QWMJl4\nuqJXzDcHIn54qJtSVy2yQ36u4QGuUmRMJ1QDFwxXSrRk4ewO5n6ndJrxupnl+yw9N8jpv0rFyy8x\nv6tNb1KSNcA65G38Uk+f9pXDFVAm9yVMVmNARfZzNrQybf4G+K193zlQGV+SrzXvvGpmOAfRhgox\nHa0Gj16eO+vvj9fYyRY0sOv+3uwbC1pn85cfGt8zdhHAShA/eICI6mnWYE+luL8oTUPFjbA6JuTg\nfWgf6iE/NXQSL2DBUMw5RF9/G3yfPOT8oYWbJZqL/s2pDbLW9hNGYXFQpXD1iH7/dJeQ1tdJipcu\nXGlb3slj/kcLiggxed89F/4aDEvVs0e6Ln27lb0ihd7NmvZrkbjT7vY8qISWtBVA7tNKlVV00HvZ\n0qvK87ftjk92FJK4fSekoReIxDjO50jci6dwOEqmYM16fIkvpBIllveCmSgWyYQxJoOrTBhPJJtf\nXfZ6PPmEUUvXU2cz8AnKfLRCcN/Cf29cKf549Q98BDW9jyemH6WdntrxM71+Hhjv4S5TtU0U0g0V\n0+t2NEX2ofWopXzTd7xXyQWW+2FlEeHbIg6Yi7LuQwhxTEUHKro+BW4SDMa8Zmib3qrPzVE1roWa\nMlCU552UI7bRNUR67/3lL2I9V5OF2EUctqNmUS1uRRUduiEN98Ni5WnO9pj7dC/aEx5fYbprxuUP\ntYj6TxMUAK4EpYp2EU81lidmWfGE+PSltOYjZqwp0eX2VQG8gtQ5XLQ5VDL5EmdTdG94MAZ3KWl4\n71qGiCGftP1gc02JOeebdCLPs9RB01Qamz/7qRrtLZqfjEm7vFGnZjrPbvouq6aLrTrkSoQ9Rku9\nBq7sCRWpZJHwIQW3joU6vIKWqovqZrmuMZEMt50iADknpPAcVttuorkxIhrY8EMGTVLaeiKc6+aC\nw90fEP2IluyabL4KCB9IP5YRud8Vem80dhNNefrYqAytpEjcQQMbkigJA71KxdxCMLHjPZhIqf9P\n1FOlQfDEyWStjz45PhUvBsWGfNfY4e7RP7t/msJ7F3wQoa9QKpj9K/iurRXNZN2eKT6Hj7SGkUn0\nACtUn9Zun7Ua1be3Kb+uXxXfvj7+T0Uz3jlSydytD55UnuDAYq+K2gAwynXtc6841qezeIxadr37\nLq8AbB4IT5X/oDEUDdtuxJhziiuLroU27SrBYnAx3ZoKLS6XfVF7wXS4LTlEOGi4AzkJlFgbtjDN\n0n2EsteXDHoJpKSx1AqY+vi7VY3JpoxH1RemFZ4Rbxr3Xmzsdx4BaO8hsfUOAXD/iq2b3VP/iWhB\n8XRPiTNtsAKVeSMyRv+E/9K5cMsB+gFtd1En27yHSX5qBO9M1g4ncHw+EIhgU0Tg1aEZlnpBXn1f\n8KAdY+kh8PwqGgcbkRdJC3bttZ/g9xR3roFPxpAZ+boxGrp2jE40Fcr3X4g44jgrA4IRgiUDIWTX\nqR8lxjalxvMOV3ATBs+7cP/BSaFzc7AbNgflKhebuvoh9OVDpfPv5+tJj/Ucv9iEIo7eCoyA4QTT\noY1enrvni6ko5gsAxgyanuHdkjnMV9qdVIMntJDRkt0cWEfdAEj8z4tYB/hGCMz103rrnFkX+aid\n3cFFPfSGptu7BMWqfuRmrduQ2xdKKgZPaj+yLnReK/vEbKIkBYZl8MlESCeAWwf1nzu1G6V7xSXU\nFruXmDy+vFG1QwwK2CMJKGUq1PintY4siRuRBhjdR8bY/v9Dppoqiq0GbWCnEnoeZ0lgvS53Avh+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GcA9Zn6JSJxTUCwYs8aQ3SIm8x3etRqToWjYKTAbZmvRezqKjuhJ1htlHyPt+p\ngxFYba0DOIa5737BxwzgTL+BM/X75cddRAx9O1zRk7WcZscO4nKsuVed5vzVpY5fUeeam4wpEreH\ndf5fZo+i2TN8VR099r6xe3IuXjepLpUDSqgz1s6fjumUU49h8B5VogWCzI/Sng4e2ySs3DuudcTN\neTbO7F7hocbaR4Ja+OHzwSKcERs2tKt3SKOZaqCzh1C4cN7icnZeSfmDXVkJyB9mTWl/6wSahflp\neg4bS3CxHvVHBxc1wTPp6ZwEbCNJZ1GeG3MurB9i3JbnUDzmOFhwg7eOaFurXoGiv45RB8vQKvjc\ngyyFG8V0I0UxUmA9cFlbilM6mXKs0c7bvXdGnxv2DQpmqWwHJafqZ9Ub7GIRP2nIw0yClX3C5UaC\nyf/tjtAnY/dw/5LntI5BBunmuEC6fBhZSntF7uXrDWv1s+C859IbUO234tYG7dJFDQHZH29sVYfg\nQYZDwlOgb8VuP8Lpo6c88I1UFVYFMgCF3P5SQ+v1m63bfe3bay4HUTISeVJUy8JV8sfADq2wubcG\nuWcfUD5AShQOLmrpWHHJ7kOetd/o40exAcRpY6ruMZpAbw/XTk3w+IZeYAjXvoV4HsxbneA/j/6v\nRCzoW5P3UuUoaB5PgGjjGV5hyDlRE22MnFsaD1Edp4Aaazf6x/abJR+gEuiOjIkZdFyslNkczRoD\nu7By43V/wCySOAnWyFDHOhN+Rk2yxZXouQu7q4FFldEH1iFrGHvxaAEezrQSskVgSBq5s+L59ioU\neO9CS8jae071lEKSz2D/g93/OL82GyJlZWj+PeSbqzhShQ+oX05Il2Hif0Nxbu2fUZVIMzIa9VDD\nf0JX96UWWVTDr3evRvYoh7RwhDS82OKImfwBmSzxFjawoemFpUn6yy4AdrgWom6pB82BOMrWyxCm\nr0baPyGumEcnivasXzu3Ghg7l4NtwjlcTuSrDJyiIIqWlD01qFIT/NSe8XGEUU3cnSBqQfMnb1rY\ni9O0ljhYVL8fURPadXIpnmspDZRBbO/9U5PDuTLIDUARR58h3mS92o8oG+2mYSEHMk9Yt23OoVZN\naP/TqOTjA3bB1PM7YulgzasFE+gl9SAFP7u9cTy07ik7Z6RqLfrweuEgZzZGPgnx+HDSN6clM4mE\nVHYMRJf5jlERFhrV8NNEHb+dJ1cy1o+50SKlrf2bfrsA1sMfqwFFA7WTEXfXopqTuOy2pS6YuTzn\nLtt8mp+m9VBSNQNLGSuPeVQKDL2c/GFdlc6tWG5msBw+rNDavwUIHfgdxQT3krhLdr0g/Xg3vX10\nmVcpqzA8cPWZU/PuRqdqDxxY+pCqDWMuX9X7UVKrPye75k4QcLary7mM+LoUhbsrfeeVgHdXbQQM\nzMhNtPA4SoBi7w0scbWfeGmkJixU8Sj4L6lA3ZvMrp/M8AR+++6EBCX9ttW8OQssFTRvoTnGA4Jn\n2kCJwehXlV5jwMSToYsyFFZIfrJxAUbo/+5sJXPMGPJIZRxRvhgucH3WnPrzojvDrhoDhR9WTn/D\nUIlyqa4FG7wIMST9OtD7LQ2xc2zji5zZN9DmxSdSMDQA/03HnR0gcY5xRBuJZ1lVW93DRflHAlIE\ndxPAtrUw4T1wgmfkkOnNCKxOsSAufvMYEchVBCXPVSTCIUgCl1WDz1FztJXRkZhd7VubxRZycQbb\n7F0xSiDk4EP7d4d1bLSz4fXRdkVa7inKtRAzuHfrKZes8NViU4Hb0i39UaHG/0rHCiWuEqEaemNZ\nta6O+8TeqDy5mRWmtS04oiQBIqj/a+YJjajeqKkJo5PwXbtHvSQh8grTm2jifLLDtyc7quNULvHe\ncOm9lfFtaaA9EHzxLtTm2U+5jwj6VdaXu/Ui+MVFI0xsQHgjT2wK5sk2yH071CVmBEItMF1tRgQd\nQIH/aNQjpXW0VHg7b+/8rumUFrN+pmkyUxhN2563muCP4KBJd0JQrKwU7s1O3br5fHuueVJAe9LR\nyXRESLNfzc+gr9SgamtzGojIrCBDOUdjjM6J49tE5jD0h77qR7N0SyxngO1MjZbfnYlh0TiZkDrO\nSn6LQCdtHe8jRfHGsS0T3MouZqBxtTrH1h/5Wg9xfQiQNzbjFdKkT5KfBmXj5IMkhLC+nYB2DwNu\nSJ3tFGNeOhrevRvFD3kUC7fsFE/ZwDgMmeDRMbfPY/Lb4XcSd2iIZBORBSlcLw+e83D2PnE6mkza\nnmnmKneUB+XbLJ5SGoG2x3n3eYD1iqpgIRRjPc9+6cuqbbkDWi4/eLtllVND026fbWEIF7PSYUK0\nwh1664zeBZIErMhQYj2uSBUZUWLIb2ys6q64oBSI5R7dLu3h3FuVojFnfAKueZRqbC9twker0itL\nIMphRzQ97vqXPOpQwskpiS+j4989IJOhDe4UTwtvUFVPhujGAfnowG3xIolbZ07V4VTbTzi61amj\n29GzddvermmeN/WW4di+c798HQaVMAPlLpjdy5BwGUk0SINd/oPNbjC3LeDtSSBdv9jld6nDeIjT\nNOVG8bBSqDP+0SDTjI0VlDlLKXh3KmZKpG+OA/z3ssNWrlyCFOgq6ZD/BUQCb3CLl7yKAVDswePh\nnK5UpUiGqm79YFthbWwOedumd7lJPMBxNYnJmAmZtSqcx38lGLipvw3ZMIEBliw4TlSRjPOodnCj\n5uztSEunBm5DjF2YJrzC/eZ7ea8lkj2HjtFZOrVG1eLYgh9Xi2PTJn3eCiZZBLMyEIGbpmrAHEEt\nDir1mN23gE9E3gGAm5AIQd0X/ZM5UBNPXpYcT4QMDGFeR8CC502+5jQ68swFIiwkynNbXW7v85kP\ngNi6PG3pHfS7G8j5+v0eyr4z87SXr+0wQ7+YrKvAjVHMKwTGds7JZSrwY/xbyS41jfuL4BK0XGi4\nGKhXRrAV6L4csIatF/43SQRMQAYQTLkSdDlWFrYmimVcttsF3Nb/V6BRPKOMZf/AIRfl2g25CdOh\n8t4wi8f2wZ/6vvyVQ3JjUs1GtUYeFEY2jWTfc1nfqrw6YJmSZExzhFIq5LVEZ9hcIQ/mWBgf4VfF\nldlM3cF86EoYz2hdMw/bPSu8pHqYAOWsZvsPVeLvR5bf+ugQYrAbCzBTFgM4SHoJsfINe6+0nnZW\nfkR1pXXII24Nn1y/HuBasCbvkzcHQwFyLWOi1PcOxspjoOrteHd+nv1PwUwED5QpalSFP5gx0j/F\nP6OQXBmrcu8HNETcC5BNbjUUgxVH8NmEx0vYKQka2u9RIWNOY86IY1UCKu4wT5U1nRyTpAy96rY1\nCUY2eeSu15cl3mFEsc9cR2SaZp7oGFiGkOeASbDfact9JWvN8TRyKi8cuY8jnRLtMh8w6wkHUW+F\noAxhkhQG48kdBvp3WBM4eJC/FhAoYDpTS3VrpOPFn7cHPRte76xha7ph35Pmy2bw6sY+BQ99Yk6h\n9vmke0+Iyb0+XXIHT2rKEiFSiu8dRJ6l+AqhZidZgZkJhwWP6y3ecQwmJVAhV+qEd0wPaFwMQoVI\nrzJC7r4gIi5KpEF26KGVAz/C0/Cj9x5E11XzeRsFpyYKNmgKzN2jhUC5+yg2/QIQ5A8h7Kg4dieQ\ntCofAS5iA+FaHtsY/jn5rX+UwExiVSxZRm7UjJbNW83QQwfFcfsW8O/bvA5lU1tk58Ii8KbxIvek\naLGlNnWFN8WThhNIHLSDeHRq2zxLQ8tG40cLPkNsyz+rMRzi/zjKmRbDejskopG5i/lb499GmbXr\n2C4NU1qBCMI4HfUZ5Mr9joo7/9FzpKG/HWLSct91DJ1rOP/RoZv4rbb9zKm+zlwL76OYPF9yA5Ma\nZe0asLuYZRnc/l/2AeEAdQVhjZCwsrClN22r88vb16gNFKtjTExjrzsDtDjZ38VXUOkOveq4mhYn\n4vnLjumrZBCz7y+6ZCszoIOjULEXOLchdJYytt2ysJfcaHDBPBxcJn+WKQ7xUvPyzh5WgRMUdsim\nDuVT+D7JaCvgAT2j1VfqyHMGXgfq5ph5OLNiOevTUYgC1V5HA70U8xcLfS4RYJI6WJCHWC9Wbngz\nzNLDlUD69JGv7uThe26LzvY/ivOrbkXghyYbkN4VT4GLqOsWMCYEtyAxmvgWAqIhNSPw0NSJjE5x\nxO2zQm1FoNF5mu+nCWJdUPtx70u0a8e5jdN9GFlj0EYq8DNB1X0nZZoBnNM/W7TUMATH/6CXWzd0\n498UFlvIFo2HQrBaKisdbEQ1Qb007Rp6TCnkkwgEHAcKg6AJiU/DZLXeYF60Biwb6N4KrGT3PWbt\nf0Kmi1vBxjXBTZbQXGjHwCQ5D6b5cYFeRxyCBrMFOUv8qbAKJEjRmrVW2MuIwIBgNbqnWIRstX03\nI5zhAC0x0EWpvNz4BOglCPcHaYYzo76rjSDZh4aQlyQmEiCxXT06Jv2NYSW0tU39elbVs4GHgI4T\nym3nR1zd9r7mOP4orAjs574aT/9ikdzavVr1NoMgeyyPCkPAIT7IxIce9jz6PdNk6zDEySO/wwdI\nCOV0YVAH8zQKQZLiL4bx5xvT3KZbcAHR1SsaJeuBZ8Lga1pt/5pLF36+kIJ9mqMHR18nWmcyeBNL\ncJEQH1ntn5eN1jpnbbQWsPwozLdy48vcXxr7N+qr9eUL8XPBcUpq43UZWMr+XUhhbgimqWxbY/NV\nfuSLs0MZQYkqzSennveOAr5UkIRGGlsWXubl8MxTBCT+GUtanJRS9duOH1yU+l8Lh8/orNoh7Nrv\nc1FaI7GMH9dMRFNACBQILarMsF7GoiZaxVxfCgQZMv2meRqmfLlgJ8HupWxkyoCgnlZLndHInG9y\n7Hs7zUmIhAGYuwtq9HnuBcKJzUP6hi82F7qk88GLhmoWaGDy+9WlFirxxJj9q5kYRwok79jIwzx/\no0ZQQUUtE1ZYANeGBMwhPqW86Ltz+DOq0vA/z8rOS2GDPEfNq/zALAuz9Wgmfp2XmtwiMCk9wXRA\nn0NajGKBfnpxQhGvH6Kt6j6GX4ZePX92brl37hhv+v3goAezP8T05xCAO3ENq58hojoRpLskhm2q\neGZIZA7RMgLk1EOC4eXqf4gyTW/XzzZphuSs3NBT4PvNCbJweAzuRW2koJNRXexyhIMu/uOSuyNB\ndtKF3ndxgqvrzqFVmxk0eyVDB1YxZW9xE2fGTDOgCvXURap9QR8KZM4J9nrn1Ogzt7jBEfj704HZ\nVL8HU2WnafB+1NDxgugtg31MWoZs7+giC5VUC5hoa7dc9vsbU9FNT5fR5ozf3v3797tYGsmcH2Fg\nBi2aS/mM6JqJ4rSaK6oFh+5Wnqc9pEtpsucK/lxY7dtCcWQ0t8pHncn7E1jhJyb8SqUXGzUXbo1B\nCyT8jRoNNy23C2KPdfcFdjUmnbnp7AUtpwN62qySlv3Xz0U5EXU97y8tdFxE0cnjt153zSfb3OMS\nrDlVGh/Qwsi9CyoBK5YapXAeceF8PZ9xlL1yT8la2l+ZO8oZsBW/PIV7k8XBWXeWzjtyWjjkXogp\nC2Lm+SenlvnxblFP5MjHdLkLIhRChOx8UFJcwPVGKWVLLVGpIdZ8VNsih0z4E+8g28p1tUC4wMRa\nhTAxtupzWMdOflDIVg9KeDAMPXp9zX7ZJHykJWRxR6q+3Y9PVIaJ53118LYjbT5kA6t3dHjfr4ga\n6sqPWD3DDpfagbv0tUyujVlnxaXTUCPu3tzOIEoPC9sIuCYESsSkquOFkoWAnE+2GEkSzPxgGDM7\nvLjNRbflPpBjjD7xsDSf/E7LDMCtiopSM521w2KOc+kCS9QcRDIGhLkYCFnxICp2SqEvoFAjSe9o\nTYG41/kG1FuDm+R+VFxytSo6hKqkhqIt8dtb0dDsY30Mlci13Rcd+MS05Bkihxs+hx/MHusmBKOm\nMcXWSABJJeJzN1ID+bRm565QsBExStKd1TmzjAsdljAUPv24FISbs5iz1ruSFpaRugTX0vIHGAWb\nvG87IsgEaDzpNSnFPVlWWb3Ae1kcMx2LlRb7534qDRmszfq8fgmYIwZQrsLjY2WjdhrsiHAMwmVh\nj289MTKDn9SH2Aq8pcgbc797NRoZvcxtJ0hD0yHoPpWJI+YmG128Pp/E0A/GLhZCfd9dPwhXprJK\n60DQduAqe0JXJZUhh4ziuj+sYnoQjandEFhZGa0cLdl3CZ+Tgs9w3FiHQ9o+KK67QgGrOT/N71tk\nr5TsA7eIZWGwk01L8o9+qmH2JnRrG+zQEEzjEK1FAz664FHDeqTSGHOpHHw4lR5PELHyFxVBRkqN\neIzgX9sV68iuU8n0DfDKic996LdsiexJexW9WLfH3DXMO8cwO5Abb6S1T5kFK4Sksh0sDSt3Escf\nArHXyYGyjOtQJXSZW38Ldjmje3CpMA/HYzl5aXruIhqnzy0L9tnGrNHIPThnvpk1CVEQA+1eMusG\nMZIyNx1nyaZ+GHA+pkdcdP90dDpHKZwqsPZVHf3kKHY0u1jqeTGchDgTlz8mFXE0HTq3HbzfKnMG\nY4zbW2OP4nzYZWPS0pgl2IcLCrPAA85AAWVMa6Ceg7mYLxdrMm0Ln/tOgzauSvkKI/ViZs1ahKOr\n2WeG7lAVi52tQpol+rSeDks6zGvoP+ePTUgYap9zCWUfTadF9/i3UdFf69hTsDZmD0YQrT/fC0mx\nhKHChOT2KdWe5TIrnbOpJ+I84InHqS1QLscyRhBYy5vOsM+XA5bxcpDSjulcZsRMdY++KfgzvGiJ\najuh9zs3L3sLdv9tCsf+elYA+GbduF7WdmxEGpEa7iKfjeJY4zU4oazPjTzVIdR6JqOFhIhziKmO\nsjU2IhcGEuVu0ogfcgl05hvDseGWlLz5oVJU6yXQSmyr7O6l1MRqaqPyKLBIMLYpXcqhMq0/R/ab\ninKhZtKEP7YnWJMq1CH91hQFThZ4vwmO9zVI9fxlfHMUoKxTIwsTHDXoyw0FdD2hfdXNZxhe/f72\n4Wkgp2qTz90wVlz1lYM+jJvggFVY+7WEQaCoHUu05e+ljIcie5sErvk0ueTOFywdM7iGowcO7d7e\nuhLyo+BAtsxpcGkBGtqomxgkZlyY7RePmNKMBesg6ouC4tmKlrOycTjVGljWsaY4mPLSKGFs13Ra\nGSwSEX53xGzieC4mFPwvJxIcirobSwW4pdubhvbdMEosfL6boa8QnLBz/2mETCSFBiJbu+Nb46H6\niGuD2cLAIuwbx8am8NAyM698phBwoPVElhRwpmZeeVpwbWfVWoMWq2v7t1oHEBH/VMcZ6PpzTcc7\ncp/vmAcidEHGZDVDjL+fl/tIQXVdSMRpJJlPqb1wALZTuVkD97DejftYg+7qTx0/nIjJtDAUI54d\nyMgtysL/yZlNf4EHhXvLz1XncBT5XlN1DiUVSNYQZGCUhU8UzCVbMCS49jY6IBUDzOVJnAOuPF6/\nHMf2nZcr5x5WnkZyCN/cm6ZZIkgwOgZd5I20Tk8LL0w1+tVygB6/J77LT1Th22rHnaGEDZEbKKIi\nEEMBRJ2zsprpglgMScv3wLsEiREmKu8lKuIYiP+IeHEJJgQy36vrSzm4Q3dLPSDLjqR8/ZOKCn3d\npgDbg5/XGvIVsThfR0tXjQuUKdw81GrqUM0MuYXkRjtzLsy6rMbTxOhCGtoIvWbkZ3ssP3xj2RMg\nzfUoGSj0PZNY6l9lCwpnuIJ7cWGYs90MGL8HLMAfCPGIPUtm6GGY7nfeHS4KIjKA4RVAXWqx+SiW\nZxSdxmiYIP/Hvl51ndadC7pc60ttuS06NeYHXDOO0S3vRQ1rMaA1jakkTxF47o+Jzcza7CiNSktj\nEXb3DfuBJlztT3vvicAdnTOu20Gk9HYImFU+V1l/7aGLrH4/rSSwmdoczLdNzpbPA2hNeLWpRTPd\nnt4lF7BZRk3h4ZwjdtQp4S0xFB3VdV9jJvtgJicwK1dzB0H3zAbJTvRTzN46JGxdDXOLV9Plgmhc\n3lK7uzj1V8wDQnncaKGeiLzwyK94e45MybepGzrp3DoeHM8I4HgjPTcRt7qL0nPWX1LvcGwaMdJy\nk3Z7nH2hrilPTCD0VbiNxfG6Du0uTixzYusHNlfx8ghsn0AHQec+Qe4dYvyN/8+uAb9ZIGOJPbAa\nwK9XZk7oblrvouXXXFBfbzsjWrOWnX+GL7ohONrsy8kJjey1WHiulVvVwSLudcs4F3gwYa1QN2JZ\n8bRw60FZz56Ne6LkeKXCfZOh0FOiTm0cRwrzrWUMTrM7CIT/YXJuJsqr/0mw2ZZ7NBFqXHLsxihZ\neFB61egffeahE+lhoLQpiZs1e33waVVLxDfY/evj3FocdMGNoQMQK/nWPz2KxxQXBtQHVZOjNrdh\nsx7U/Wnia3HajdqoupouLpo60fgJXgzGUlw8Nw8xfqgoJVF9jI7VDkdebQRUTW8U7XSVXMXF1wF9\ncPiYqw99dhUqF/Dqn38W7ivfQ+4pRrdLESpuSJ3k1DQGXMaSrmVUTgdaC40qBl3HLDKLCCHFiyw5\nHaHsZvKQ4IwKZ9p8uvWQiNYgzB/dywmnnWdg01VvpSWfMPsaIXN+TZOjB3x7At3FLyCvqU0KDBcP\nNSLmiavag9CucAQ5X0a4CbO4zq2rHFvb84VRgV7X/igswCO86CPlH+OTjiXC+98PSbQyv3Yt7yjN\nwu0vs76r90T1nhqxFoi+c82OdInCNUEyQIyMJJH1ub9t6qBHzXXy1lf2qd+S+lqoceDEDqwwc46v\neT7zK9dsLyQ8OVg6qprjyOXF+KPyYj8pvCgXrWzL46iuWuIGmQGhIjY5ctoN0taZPkzYnBpexaSK\nplkhhI675tI07CXRNHAYJ9V4WU04ItWkJcraQMbPh9pQd9jVjpeb156ehydxPUL5aUTpP4UWbDiQ\n6v3XwS04kaMW4C1S73RsASKsDIGwDxpUWkE/Fx/xjGazT2O9XC2tF/HfFu09QnBwAEv3xgxCsSgG\nhVYJmi+uSU7Pi0yk1UAx9CIBJZfvXCOBSSeqfbZQznoPl6VUDETyAtFWk++1ikObWg/mxDHhHMMs\nxxa/A/VfI6lDgdQWlRsDVfzhDYEuoBMA0A4FWpgfr9hkcsI6UjGOSyN8vGGPWfSf1kjG+4Hzkofl\n620EcndQrjZ/dZvi8FeOcveao7y3JpYdSlF2FJQpUfvrBcdHMu5PHvrjgysK9rHHuKLSrkLBU8/s\nARpzA/e6gYZoH0HpWEYwD48tt16u8tRvblN/h5H7g1tmLXRp6u77LuzB8AsUtEPspLTA7AjTXJ6g\n5T/wROxlhGKoJZC9/+si0e86GYGpR+iim1BlYnv02qIx6mX482NtCSam6G+6VbYpVdyX3t2Lm0qC\nOSdh+hlPvlsHAciO3AbGMXHS2MJMV7JVX9IQvBu7D++EeTrzHGEBigjDN2R/GdKaq7QBpwQrhv9Y\nQB1SI+U6pyEG7T5xpAw/BOsMczH5JwLlaSrljxEgzk6CkjR5t1JlKntP1W2tc/QOTiNJdAfLDJ36\nJcEywJ4KCMoDcSrl8NTApf71iPxqy38aNuehOuG8CAcC7twSHMW+1PdIlTOX/JGw5ydU0MlRxFFM\nw5PBJ2kA+0TPwLjn//9Wc/Z6jMvVS8yJ1hSLH4w7pJFT5ZhBUQXfcZMRp171i3T3Aw08GkfoUZzr\nyIQ6aItW860T2VbybbseJ+5ksBUs++IuROqDkR7JXmMXdZYpF6dcioHHU7F3r8/PSCZehCbLX8eL\nzeS2cyP103uUmRO+7BIJydB88XMvw8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5BPlgv0Ysd+eSR+SctxdgsIGfUYDU11OM0zbr/\nWzLoM1Oq+kbqKRimCRPQavzTq28qw2vNV76NgLf+Mi4voQMXDED873/xvIVY9TQsjopYhTTJgQ7T\nDYAvw4caDJO2T69XIDBCS5MwBLxZp7dspfoN/4oGjaDljcUVf52RQHBD0be6K7+UgXh3e722sNlr\nGIWdCtUs2ieNFcswyUkhb+J/TQcA3Q/BQjg525rpirxX/935A7IqWEBSrSJUyQ6bR/6RI178+VoP\nb+nZ31dSV5cLusb3bgBEdqMgFpIZQ04+C2h3rT66h+w8lgB1i8lDhFJYj6Z914taI7u7XrL9hdWk\nnS+oZs+XLf2TEHM6XhtWY0UfGTB4gk81QcHMPBR7FSj3PPjs6NfrpN8PnEta5+m7Bw8yWJ8hEufG\n6GNBPRuCN+ST78w728pgI2Aj77qgmO4bfF2EIh3e6jnqiqqKZvpottUU+wOnw0FfbAyzdkZHKegD\ntYerAldliSEsyacASt5YCPbQ2tBOlTdWlpRKGK5jhAdSN6XMihXy+VfCBF+iu55vsDQpKODwBf/l\nB8ttqqB8/6nZfoXzhq/Pgq6dwlP2EvSsHywtVGlAv/1vlQl1lWqIB0YX39bQW0bL61gJtp7dIyJN\nGXTGXiLo5VjnKbEblEGRVajzzcIM29VWYOsxCrtzGGusMJRb1cdgRqy49yWsGih068zm2wuMn/fg\noAhj5GcjxA7ozuv/6so6Csemv4QKW0vWEsu5LBWrPlIP4vocr3NsGTixATur/amAbbTeFCIGYoaS\nSjoM44N3wDyqsx/UFjyLFnf9A99T+by/+5RHIeoNkEG8Ghax53GNSvtO42NXxbhJJmixJNswdKVg\nrefi1rMLQQIDBFMeXpZctKcGDYHnTa6qWsI2Xxz8s44DR6MMt1MsroC9xPrPDUdujxc4s4h6R6Tx\nb4avq0fk/TlXz4ay7Wcgeldi8emJ5XtM/1MLpbTI5e+rGvBBJZn2f3R4FN1XVaK1leID3H8+MPhr\n72Xl7ZxK1k34nugWgEF7KkgInRkOy08AUeTUF8rIEIXHpXm6PzsCJIgJgNh9PrfxDGoh9XFHzHPo\n95su+nlqpTVGpiCjjD6GZ+YE1OZPhae8S3cdoeM4FgcVXsF1NP7PIy5DJ/R9pQ27TJvx5PdeDcrq\n5P4jynMDt/WXG5SmHtNJV+WD0q1vQMIkdeSX5wzCHcBDiWVqjER96rpl2Qwbdpo/W367GH8KPvUf\nAitgUV8GOu8TN4BBXonsdv684d89itGwwRGrKuVoUZtt+y/SwlhSTwA72MH4a9QWBe/jZpuc5eW0\np5DSHEiITaA/lyEk08vTfYQe0gsbQTg2dvpUbshMmvAWeWd6RoxDkEVNp20ryoGQJ9utSaixLGtR\nyKaaO8q4EwLtIjey5YKY0a/3Qn7OLrNo1W8xkOTYeRhC5E+kCtLKeve2NtgVQaSMiYr6SuYyk4HA\nTVxnfpuozhoMblkqkkj+JtQkbwJuxCBzRB8cLs2Xxd+Aul/LIjAAr183pTtklyhzIwnfiMNLW444\nc0/9McUB7gL+/gks92ElnH8khm4fpLUp/DwCEFKDend6hDZ7X3Cp5Wo4svtWu/v3fw1kgz6M9bUW\nJ9A61uWMsoS2wRbMsgifchp/N9DMHA9++hvfdpxBqXGOIw0VmqNAmPKrG0X4JEIU/6SKZRNNOG5E\nY2uVsHIfAYgw/4n8mv2fF7gvKyUSoHTbURYbZcKmmVv4q64b2x9J8+IZx6XZmLLBU+XJ5NxJsW6A\nTg6MU88JjupiEyYLylToCFKqyik7AWoTVJC/p2Xrt0MiHG5QRpKPsfMkhjb7gBS2PrvNBP00ee6P\nVSElr/CEpazyvPPZIuF6u6ze/u8Zhj1w0aneXH+14KnaFc1B1k2gl84kK+7MadGPCJxFy0HNW2zL\nsCOV74lcGAUuSqkLylCXZiiGtsicrnSiyTRstEasEvEkx+V+kbd8R/wO9Y0EQ5a6o3IFIwJzO0sB\n6KJeYHUhNr65982JC6t9Hoxt6agDzUeijvPjWMRhTu2CK0iKcmGyXsVdYQgI1YfBnQIOTXJZzY0O\neNTS8hH5fIPuWrBg6F9lwL5FPZd9APt5Wkv5fo+RC47fWbhQBmxpdUXF6HLjzGuq8GBLkcfkzGC9\n/ArWqnKORSiu8GUHX6crwulCXqSvYjc9Hypjw7TPuTVvnZKSiPHGRAaREIspT1dEiZHFaDF0Z1mg\ndn2tK03yOJ169Ud0SUyzXsOmi+JRIMM35oolbfoV+uW7YomtxUzbnIzt963yB2eN/GuMQQYpXXxK\ni7tsbvfSJNE3WE6xrJIq6MV30YgsQdPl/2DyCy1oAu2HIdIBAHwXptE5U3SFKDIr0aP24ePPJFXZ\nrY5YWECy6t+ORaljfEW/OAWSt6EKEx9LBJSAHyZRXz2oMrV9qUImx4xa8doClkt/i4zWMwbCsT3X\nDLxxvqAK32Nc+7kxkOtjbAYSVU3E2fMUSQV8s9CrmI/UELunLGXFd6HE6q1HgjODgnM/ZQ1vJcMc\neYpleSccQNtFsdHo796N82J74xCsK7uXVn7Q+0I3tJ2WDwPZvuZizHh39LkRwQQmdVDc/J4OSoky\nDsVgjI0p+2PatJf8L9EPyFtQmQ0JApa5FD/MKz1u9czJavCX8cEDPvGAGAczTWw2uWYgANc5p4UF\nl2p584ecb9ssVvKqGcKk/YaN1QQ/43AG8ut8UtlQxmxQXpjZqNrY06Vr1tuRj6mEjzJ2ijDFBdCS\naSlPbp1cld9hYjIdXm+u36IheCLV4JAjyQlfENRN5ctVJQ65A34472DzYIEMWaOevpdz8LpwMDrb\nomcM9KS+IZcT2FP+FpPQGXx2tGz9IySsDsNw9FmyJjyPSCVhpX91n06Bm/TcIbWasCWgo8LCvra7\nV8A8lh1qYPYC0T6+PFPJbTz/SA/59IjS0EpwAz2Nh08OLhek4atEM2Q1fVVNml9qj3ecByeuj4vM\n2LIxdpGoWAiusFpbmhQKOwqw3GAtXMQj4isIg0+uLjC8TCGBK06j3P+QQH4sSzR+yRzn2vthMXfp\nHGb6shHBzxIUcUgEvXPlfRUKvuVCRqjv8YE1eQQ52QGrqgudZiRiaPKFJW75ddXYlOlBr5ZVMSNY\nBWGoulXjstXKWx+SJs7Bzm8Zm8MKSf44HLYgw6h5r1v8JFtiw2tMxNvce68O5qF5+arcIB/4Tm5X\nCNPdJv2DyMnAr0TnFgqM/vhYPt5dPqDtSajak7mXYNjaBRdhDkenWytBOccR8UOfInk06KmRCdYn\n/DU3FiBgJ+AKdlDf41m248j/KcteFR07COdXIkvQohKy8egbvc4sTpjgIaaETRQ7/l8WtgtIi0BL\nd0EVC1t3zDqWlEZYBBZsuXzC4ma7BvqOOTSe0qKePROklF6IUVpmiQWQkH5aTETOJ9XJgJKKFbJa\ncmUpaDWhISKweR5Xv9EZmeowJxVP90+N4JBDhfZZbdtK5hhYYeAb5qYznhkPD6kgi7mZJR+kxCOx\n4nQCYaSxKwdMdyNciGoev/CclCZ3k/Cb4NSfadqiJAkCSfCUnbRFG/vUC/wICZJki+/C8JunjzQk\nJ90d+klizyWMuzr+5bYf+vIHjCGHOxHArWLAWPkRf5WH3vlGZgTnVL3f/fMk832dHFj6UnGUj0wx\nGxP5gWFpwUro6Men/V8AYtf1y7nW64E7F7fOJBOWJ/DlPBSYJS3RCBnA5LaskopBso435CmmPC1P\ny+Tjs0FpULQ69Bf47RHXv+V9AXgTK12IdFwqZCX6euUungXT3WuvAIGzkz97OWRGaGqetAh1ecn6\n4yaKh3rC82y+tgJYpWt6mLdj9raleyQBJ1uFwdWVUnsf/+dfEC2sOn1IWMliGEpBZWCKlOEk3QQb\ncZMwetiYbzXTOBKfN9RZTF7aj9LkbqS/H3c+qQAYbplKQeCg3XHop49pc2+fwYD49dkguyPfUHZl\nFgbzOZeQW/j8lIvrs75f1kG2RXfrSipSYqvqGp8SjPDvHL3wd/NZ2mG0LHaIG0mg/ciih9+qn7Hw\nEXPYWhJFOswmiLgdoUyiK4YBKlVLhb6m9I2hU2K9HfpcK3JyHMzJbn2I5SJWQAE9+b0DjyUKAj6j\nMfHC+a52JEKkvAne05p02nnaGk/1MXvd5CCXk9OXdUma2uvP4SW0e0lOUtY1DfpF3AKGUjyRI87U\nRlguRxedaDyIv/Er+OyN11YZwEfvDi4MqE1o816W0+OeL8tPBCzytBVnWuhkc9wnijE18uqCfSb8\n8odutiu9uDFz8d+JXSjV7LSOu5QjouGbsmIfe+WEt+7vPkB2ULnV/sA3W37eHvat9uf/6lrXbEMB\nscgvH9gj7gfnVY66tGVIvLl2ICHvsPIYwO08FGz7lcER3h8no0g8nelO2qKdHYFkKmy+NhSzGziS\n3dAISETXF4/ezAjVj9/S1GdQwyuIqwttvsZ762j+iVf0dbRWt1NVCi3xGOH2vR7Jk8FnjbY6Di7S\nVQa2Jf/A74o4lpaemRlYMfwpkIApjX8D3se1h4buv3OnK1gOZjauVk5A2Yng5eq96IAK0ndd47PS\nXmvIy6nR5I1RRn1nIfdDkTr3Lng/f9q8etL17YXrxtM3l+lRFl+GNfYKjTcjAi+B+2JxcAtZfDxm\nW2lmBY0AWPm90geNxjKI/KGTVLHszKI/e5HOEUeXYQKcif0hMNpubhQvtSPhsCZESv1UmtIzfbq1\n9k58zlNq6rXzF8DP87ksk/vrtgHLm/4VTfbgjXg/xX/A0rePI2O1TUUZchLtgrkaYjiYR3AFi5Zc\nACktDnPXn3jFYyiRZaduSkoob/bZ/aLaWKGOvsPUi8wRYw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protect end_protected\n", "num_lines": 1194}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nSS96R7wwFQ/awBJYajmb1uyxVW7Dxe+Arw4icTEGgmn49jUuwRsWmvS+gH97qfjXRux0tm4UqqDx\ntyk4/LtkUg==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nA+Z7s4sYG1dC1S/OLd5onaqChDDoqDKxIH0wDyu0FbLuPuh2W2mXAUgA6ygUDyPxGR1xLs3AnLf5\n3U/y+fEPvjbByjgXYRdoaB1qwaS5zdnv6ZIRFF0LC1q8dbQM70j2RSMZ6Bs31wvj0c4OYXETbX2h\nDtNML4rTAuRM+iAVpLk=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\np880H0PUjXmUBTEI3c/dRMxRl/IL+XvlWrRVCBPlh6HVE/9bghIS/wvhgyOQ1mp4fyEUGZHgNQPX\n25j3cqsyfDCSGvVGO/rQ3RvIhdjhXBbmfxZXGx5UxofTc+/fp7JQTUPxhKk+Zmp3B6J8UpkkRaQ+\nTlbH9Glza9Jhze+cKRbGwVPrfS4Rk6pzkwHnm+iB+WGLJnSJVBVgXGfhp+ygbrBv+U3zrTXgsOb3\nxSJhSd/AWJ+PCYXQ27sJJr74LZYIQx/gg5QzMyTEoCqxw75cGP3bD2xXz+cFe0EdDkJH8sFvd1LG\n7SPcDQ9xmFnq3WPw2Ghv6DnJe4/yMXGiVRDxCw==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nej7XPZ5hWPkq70QwibQmqqDg1SWNzBrsMbYSFestfs+BR9J7xzmVMkCeifHuWqh/wSvpJXMW8pOX\n6HsD+kakwLfs8E+v/+QJqlLtBdlE3y4Pqmiw2GNPbakNzU8DMNQXOTe2AmJmoqO1VEHW3S//PRDJ\nqs4qvgIM1HXRfRRIgECiAHz7eGE358gw007G2YwbitOL3cveSqDocjOGV3jV5HepWYKXINH11Reh\nBMkGynjTuYTMJY/92mdl1ZV87kDCsW8+FHqKhOA1FfPvj1RPIfsKuqgUkZvW2pAYk5eBuA+vJEkN\nxVCniFgVwsrAdlKrWnw46FoutQ+m90CDu8Kygg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nLMe3TxzR1Zx/ByHI5/w6/SqhTVkyqBbjVaIILoDGOy4Y/RehV35vNFgESx+MOdmetaV1j08wlqer\nDz3Rfr2Gfq6hgHMLEHPCaIF/5SymT5AVpwhkmFaQdge1sI373fv8K78kRC8JGM9DNSFOClhGJDQC\nXB+yastK7IXkt+VYwM7nXa0xSHywkBIAeivPY/BwBX8XfbLzv9zV6rh2SAW84YIp2jb4kcYm1Mqj\nYgWPATpqkdqbBqii+7aziLQkRP/MSmF7cT5UKQiHxn/Ns1lKMenELV8RgHq6jdkdBs1uaoi1JQKQ\nfqmUv9kYnWWDKWW+rc0V9APlL62HYOLDnbo4+Q==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nq6xSi+pTFm18WzGq+65YbFhiK1j9sHarfxu6mSyjDniOO2/jW7gfvXXrv+B56wzSE9P0346jIlVL\n/B4h/Z+ac0SVqu+wV8pg+OJDyBvWhtnNYZI/7k1BSUWzzR6flVJw+lEcue42YZ9yoX/3JUlz26Zq\nBi2/4jMu3LmppUWsrAo=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nOQtIJXostrr6X7QDA+MBULvA7CIKk70kDF2hMqsQ2sI/8QR9LMuap/TXdjn0XLAZTkxLKNLqD11T\nxAlasu0+U1hOXgMBxoOPU/EUG1bM7wR1UF83Qhigm2Qm0c5xtp78LF89EgU/YOJtHjCcMSpExbax\nGFg3QnSgmE/7yqaeLbA8DKDWxW05qT8jxOwcDuZ3zIdkL3n1NxrWQjM3U5py6K5PTmC+vcoEptq+\n7ZI2ka+SP+NX5R9IadM4lpUB6CqAxroG6xIUBcSx5r2BQ2CrzH4EcZiQVNCUwYx8tyBREplKIsC0\no21e6uMpC5pDqqckCzSWGZns3l40rTQV8PP6hQ==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25328)\n`pragma protect data_block\nomU0F4cB12yO2ZdV+t8D/whbbDWmycZw/StDHYdtlxBQqHD2Rt979k5WQq+7+dcCL3+IPJmrHRVW\nGmVBB+3psg2CMKD8dWV8+f1duqdQ1ruc9IDTn3kyrMv8WzUZr2BsXVR7LoT/8ARttZYBzN9SlXOB\nIu5fROLcXGXIC69mZclXZ3kqw6gKbDdcIPTYaARyazI1N1JT6MpiPeX0B2e9dgibZS4NLoFf1C+8\n4lKKRF3P6Ms14sMsxNaM1rVifA4iQ/Ak5XeKnn27tB72RmlJm4ojRMRkD7cqreK6a2V7DXB0zAWw\nD7/HzKVzqh1lZF/69Z53r8BDyCI3oRPiIo9/2kpnZMcnV87uI6FNq1UsblfLwnFVkv2E1TroogPQ\noUVZd48nZKP6G3hipN1IkHU5wYHpG7S1px7d8HSx5vZKl3pFpv28aN5BxEuhvJV9FBghlpwG57HM\nQYhtJs3QjvuUXcTQo6mt6uaJkEmGMltqmMlwvreBEPDAzXivRCwBt4lZjduB8i1eYRSuMv0nI/Qx\noswjFa0lFt6divro4C8AxVAJIiIIEzOrht0zHz9Ss0+qCELQPEGk5lc3IDAHgjbCPWmObsbEidaS\nx7t0E/Jz7yoYsInuJGfETjIEklMYJJhVHJH1GgtFiwCDIXtjIG7Sv93vg8+dTBX2fVHjOswe3xhc\nlJcoB8yU+RvIb4FuwVwKcNAPT/0Py8wp2Pis/gDA1dsSpGioBjVoz90+AOI7ltbVQYEYqMCTLtJ8\nFmzXBx2tt+iWxg+co9z8phmO8gLRzjKzWoLbGSZBBw7G+/VWR6G6lGo4ZvKAtDdFvu3H0Lk06rJW\nTeOr2wSeT/Kd+gQCC8o2Cf/8PyI3xP+tzcDP+L/jkEdaFrHo2Z7v+LzFwcprHqiZldZmlCwK78ks\nVjmAujF9tHZe3H3Y+tr78xko8hSvvPzSklNvrskK6bA6f7i7LNvPXEu3FV0hY4/9kDRar+ls9hff\nDSRygqt1uAtTYP/7REZfujc+wsurY+MbzHHxp6jq3EOwSgRyL2cHXx4Vmo62A7wgKyTWk5EdPIPd\nr6n847VMqI15sXBo8nYyLWEkzrNVtVQEvWpeA5oqeDEHaduoNXyXlyRSwDv0duY7A3m1BAFlglvR\n0N2sjqwWzKhYFj5Ns5HQQBtHh9Zw21QqT1laFBjSz7cAsrFrpDoB8SDQCefHnKEzSHYnfb3WRQQs\nxCjXR4TlJRnLnZMyHVfyYtH7USi2/l9V/Yrd/PO4+NmUgdIxGbToTlQIBx5gigJGs0XoaWvVskwf\nNXlK3UaoOJ85tDPYp9Ejz86GyMYerWLlf1u9Hn1BCIDeuOMqiHVvTkLMoY2uQf/g9NOChlcWM+hW\n5AZH9uc91mLwBKTrHi1k4EM6CVoDhS5i88eLGDj7WUosHcAYcjaiNhkZ97tZbVK3yKkVFEtdjoL7\nh4Bum8rQwYxHNx2gWytbEbl8qIT1k0uisTMGRDOmApn7rixESdulVbMR9qGrvrPLqY8EtDH7jJY1\nlS+kchhLcPKLemI+liKF7h5VSUNsc+PGwK4Poi/2EFa7XfIpHc8E6l0gZt+qwW+qsA4aH16FPrxe\nsPlGeRTRqQDdA2OwzUgpbcvKx2JTx5qswVjgMW5mHt2EnLjW6SHvLc/Vzy7fr/O3kiV3uy4dyWGO\noloO64jspiFBJnLbb6eaTNqyAvbpj+ZF/Bw+QrCdIb0EdsWj9GmUUmsmiWLI+Lz81KUCzEc4H+Hh\nGglDloivAeynD9N8HFp8OpgQFagNeWtfAonUqCDV3B+hsNXo+x3Nj49PDKdY5aesqlaahKr1fAHT\nfierHFNbvOT41MYGioKDQPLwon8ptmydyahnP5MmlDi3knIlULZ8de+mnbKISNCyvzua9eAc994K\n6B4Kj8/swf/hAOZxTJ+HqtpK/DgmCA9FiU3JYIsSB3rhufuLP+mFayZ1tK7d2t3i+FZt7TbMxR3w\nuZgEVxQBf6VU4vQ+r6EHuytjSggM/20/7CtQ6JVqeRD65+i4n1E7b/yeCapiKyLEHcF5+TolHg4N\n2IN8M3DjZGThrN/W4aFXsyj4YqaVr87z3w3GM8FGp7rDv5JqVehoF+ATrA0OcYRvBVPsgnnvlPOg\nWuMIIahHuKGHwW50zPwsNaUod1E2fk8gLhkqMqiE3SQU2y1T3hmK6MZXN9GSwJ5IIw5eyyO1FWGr\nbcgG3rsONmih7ecMwUp42jLQ5vSszqiQ+yHXepZzC0e2VcYZhWWEGgQ2qAP/mX+y+xDfZ5e//Dp9\n1vw1SwFlk48f3CJcsRXrWfDocPNxPWQEcFtYDHSPNwEAWpRDWrd1jQdLRZ7riiKEwygrvCTBTy66\nWshkAAe+V5my9AeXa0Ml2QTFJnaGjonlt4LTbDpP6lrDNO48TxYvwTeeqfPcLaHr0uKQt7YHP6Lz\niQFo8+yjuc0zEfQzoaETRrimF1qol1PWK3Qpfih9XrskpouGoT/zEL9vl3TEyQopv4PUZPj0Ynk5\ngLrEEhd5zkdYa0GWHcoa4Fot3qrp3UwIaXp3J0srL6FzrCXbDBf2Mo5NN+P8lk095AJm7GbHDjvE\ncDphpGwBKdvmbBEGbh6fHIOHTAhf+Vc8cPPX6BHmHbNOHZD0JlWZppGdjhHNpBNPnIBYS3tfqeR0\nfpgTvVPYXHmM322F7ZoQ/fwObdQAoj+tk3q0RroBJxQWakMIeQLVoja31p0u56OMldxuQgfF/7kr\npJIVirx6SAQcDVwcFSqf13qBuM+0Ol/D3mNr7ZjwWtpprSUZlH21ailV+zw2WyvthkiTp8YWVQBy\n1q09ZacNze6Y1ElACgh58iPN4woxeuIgISJzdoXdZHKr2rmaCQ72e80pFTsQDzTlRLDVRkpqAnDC\nxN+Mwpe+Fkm7f7w6HD9kr73bageDnyHcFZXpA468LRFJPWYg6wq9iFZ4TJAxrhk7MUFsxJtUscnr\nxLex9FDXv5JNgmR/UE/CD/ih5AN+x6gWb6/W3lszhJtU5l4b4IoAIBzFNDGa48+PO6Tl/fTG2S7N\nNWLwVUe5S3/022dgOuBphepqPGBaEk9aWfzhttADsYbd+EEH0DLjYEUNdOy0L0wxxD+dTHWxJZSV\n0ChMWF8mHSAFDH5fO+Hy1cRtVcPIRrjGMzyyvJjDaKoXzOfyN4HKL0d2Zjm/gFo8lez/ydTkt/CS\nxYar4AEGp/BN7QDDP5IH+BMU2l+zrhxqwQPo4bLd65LBxuQDXhUginwDEo82bBweomEKB5ujxPvH\nkuKtvrIWHrfWIsK10kpV2kY1erMU26KgDhIsF6eqON5qRijRBS4IWa4trUlIKxFe0tR1G+0lTAnA\n2b2zENNs3Owv+ZV3WgEeJpcYOOwbsG7qq3snQYse5j0ltcLyBO+dYgzePpcE55rg3YWCCn4hjKVN\n0vSNNutZw9QqsPBhK0qUZEvot0e3Awajv6HKZPq73c6PpUOaaFCTRl7V70cOsdlrUwteXMQJV3F3\n1Qszx9GyIwFkBAfl5tn7jsQzd2tUlf+3rxISOSF4by79j8FsMlkJW+++qk29OrwkSW/XexL+uk5x\nDWSc2fgm68pygKu/3KtuFKMEnPktko2ej3qtKmVvRPolck9fuCxtkXDMY/lRA/cMCbVJdOST8PNH\nltx8N3OjAHjF7qztXIGEbTgETs6qdtIS8Aaec2vMw8sZrpkkrCd83yeYgg89AlK1PMMWYpKw37mq\nTeNpJu+HCa81ry2c3bCvCvpF74Sll6oEliNJLH1QXvcQWLSiz6bAPjPvZNysBOkqwipQO7FIFujc\nH1i9gsKzAISZqDQ4COwcFkxKsZqQ+3+9LWF/SyoBGXGllUl7fn6Y1xtEzEcb3vTq2Sqz32OVeKu+\nLWl+IaE2DFDUpnM3NlaxYilLHTm/OtF29z+8txLIi56qb1wlsAsobeLHB8KpgUKsEzE/Edpzr+k4\nykpmm8XtbKx+rz1FpVqtx7C8k4J7ebUClTt9AaE+jJujIyeR6IIX9uzQBNiB2+o2Tb4XsG9P9SMb\nGbauD0yjImseltwlb22KCPcxWEUe2/7VOir1DkE9/wbtk6Q8eF02TJxwTZv/epiH8p09Zns7H33/\ngS6CyE0neXPK839SOHGZCftWF36xqrP1yS17/OA6PI3s/CTLfTs7YTx2codFR4imZz29y71VIoEB\nxtUhCuqGobdRNa2lmU42q3mPHQLOU1UisLPDeDI8qxbUi5FfabTKeFW8+xirZfgTs10x10q7KGnp\nbd0QGVaqot1rOHQ0HlG1SiSDeBp+s8HaYAdx9PmjO4bwDtiQdZ0aMJafmmYAYDSiRxKXnWvwtwJv\nkDDIMdqVSgH9shOr2WCOVuD4hebJ4kxzvxLQQYK3OsKY1CUdS6LMg1EBJ5fzEPsGHi2w0Eh2srkc\nkFRoCpIPylVJ01RZzkM7BHiJ7SsmbDucJMBZCFb8KFsmi6QZ4vhiXdTczreE7AXWtxd2/bUiG4vk\n+rP8o411sER8+1SpV3MujyYSJIwyGRA97P3vw8pDfsF+Ktr4FQ1M5S/UvCCDYU1c1fwEXhRTig9x\n8kRj/i/4u19Y7f8pW+4TRIfXSmqpxQLvlViUn89CBFT6NLiVqBHxzowlhoWrhi5zpYXxw5SRXBPZ\nsPxr44yLN8Onh2QMGqi/H00xNhG5pB31BEfTeuisYQiVZsCmsDMNFCZSUIZJ/+qQK5aL6ASPafTH\n35NsiMMmEtBVPcun5MPDeCi/5Yak2R3SSylLb62ucpJCFEiNSW9XXihs4lvRiD0m9Q35QHQaqlWN\na8FAdZpgxcb9I9bO7md4qPV/TFLA9Fbfw/ttXdf1LSjH9WiYpKiNsii9ttBH1On7jV9IE5ZlK9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G9UB4lpGFa3EvQQylVj7gEIapdNZX+/KvWDE1Uw+Mx1ch19lMWPerej3V2JsR60z8FZDuZBI\nrMa1yIuu3scJW/W9+zxr1+L71th+wD0N0930H0FW77WXKD73hpu0itMeJl1kTLX0C+4du/oXwiPP\nkKFMnSlhnmADk5Nzs4kXX56QHHCbRnr6eMuvZblXK0EZHGXSb4pQePS8267+j8iT4e78/dD60NSn\n3kcUWmiDaD6B8DhgaHuHl3jgJoT7tgyerSxV1v1ywnD+ooBqWrUAsYnJXP35pM9lvw9shjKGAAX7\njCObOS8VJZci9eTJcmygBtQacBP0AzSh8d0ZMgtsEerarYOHl0VaqrURAHTNs1zfXZ6atogVW572\naPtBaqUaUJB4BnKzRoP+YM/+HbN+k5jn6HFPg/wFHeOOsIPE4dpfWM76Fj9OndYwBoJrRfjLOqsu\n4QbnGR3BRAD5bq9p9CIqMna7zaj6r1Kh8y3bz0JLMChWeZWjoOnjrSOb3n0S0OcprlGZwIkSPhD9\n5e7JOYw8xSO/acOGMOr7XhVwxsvj5N71yDY9oIIxCmp2i5mKFvjdFKT7b3ivsMqpU6ooUNL1cB3B\nct1l8a3kFj0xj3Vjz0ipLbKBkR/JC+iOtZk5LGHDKd1jaSTRl9nSuO+bV9kLdDxwvYHAm3PP+PD+\nzXW0fPnQVICDYqkZG1xto1it9QOrHjy2vBNh/0ETekywdX5BIejkFzloAAm2ddh6NFnynQ81RPOp\nB6Ei5sZhxqlniMTJQNFN+PNXyW2lrwNTLew+TNDyj9rIZ6ETik2SHQpVEwsfSVmzfDCWqm0kta9i\nAjvtzWWnW+IsuGEsEL2hoy4He54jqi2mtn5jgFPt8o/zfixB4kuNpqBIoSoWJqkPuB6IQ/KJWlFC\nszg1J5hey/xx856i3HzxFJd9mVXALJY1cvYVCa3JSMQEP0sUcICrI0GoEYQ7pi3w1mAa8bB78jMD\nrfvLju0deZS0V3tBedhCRm9yt9XbJCp1F+62+qLtP8hSRUC/gOs9rvVULoMDmyAEgrf1nsbcBaRM\nQX/2dEMQzcBUd2mMjdpR0nCeJ5oxvFymHSOvlBYVhLq4CaROMreoChqIuejDpaErVFOfvu3lq30l\ngiYyAdBlGI+/GenmbO8fLK2EtGigHy8pIzuFQvaj350cfHLlcO2jHrl6UbUnMLdM/S+aBXd2Dg2E\nFKbI8PeZwIJrbP6987aJSwhWKLNgMNNjCkUqfYJ/NRB2eSOiC40TgfhufZuYh1fA7Q32tdQqW/Xy\nNv5slA2fH5SgHmwS9Uqxfc4jvp7SUOc7EToDWJKkVHzNtxfk+PpKRbG7gledErTqMBqWRm7rkwhC\n3jsX/qzzTT0uawrfLEtK5qRoYxdoZzMRcK6ix0rVWema9+AZIkOkf2eQ1XIts9qHSuNKuze2RXJt\n7XTiojoorg+kyigvlSv1D+o8cAQrd78YiWvhEj0QphJmFmC6jy6xpe/6eGwfy0a+fsjgc0ZCdt0o\nA4sV8eOhNsGrSsGhMLickahQrinsXh/8ILbGqvKtKAbNVNLyJk+6w9BTy8HoYPwRccXIahYFpgS0\n7pjDe1Gyor2dlKT72Rs9SvooqSu5tkPK3AFc6o8oQIzNtMx5dKNBHmDyeQntb/GTk8d4H6TAExAo\nsrSIFYwaxyXWQsgbStzgbi1/n6R3kvBFDAMD9ttwZ4hmPlj4sygAgzv6c6CfyuMZpH/keY20cVAJ\nOXijLo3hPgVD0p4n6FOUdu/JYgrTsHnOzGhUcEGws6R51FcuHxqXcBA57apz8QY31Jr8lbuhCmpj\nTNvGlI0SX6VE/NSoJli7V68oxvxAR58toqGrfJU+/YwnuIenC07xeN+mOIKyGO3P+4F7UuNDCPYH\nseoQxJua5/0RsZTGA9NHNAdpXJzze6l0n52PzQItK4epiSZiE7ZHGKz1YfRLvAFBrpIT1ArDhLFw\ndOB1iZgy9GNqwH8pNMvbfuz/+FeP1oM8/SIDdLSv0WDwM33gsrenitpREzjdByQjjFRtunJe2kyk\neQ4GhszWY0Dhm3qNNUlvlMc0xXvIiPl/w/QE8JJ6KgtMUdzTXgWd43HK+VjPyg1yJm9SC1+o6xlP\npEt6awJB3VCzxpu7jVf2OMsrQjiF4W728yfUJwPQUfr7VR2E97zmjsbiHbf1fo14acawqG5MHQW2\nZsMwfep7N5NAIX5rav2q5ZC3g9rfOUVkwnvp2F1HSNOWxKV+jJz7B6Xb5o+YhzoDd2Y3u9mZF/cD\n14Q3uTuV9Y/ufXtAhC372DYtV4oSeLNkdvW+eOTDr/k0eKWqnidKW9xIeLpCtmtUEhv+gSYNMZ4u\ndj1KJgp7/bMQMYReDRLQJIZTkcDnKvrEc8ObcYZ4GV1OwvpdWTtkiszhRjsUWD4YA3ir81byw1gt\nZKff6VWwZakXMdmcY0gcEhHqjdELSZFplYxqXNFX4LV5x+7eFjRz0S0IbvsVKlu5RD/Stma5/ZA9\nG5dOyFeuG5u5jQ1wu149LA4HvM0m0lg8BEG1MMOo9vjgOYEgfRz3sYRtSz2M+SnoWlt+o73somiM\nS8u+Sfiz3Nyg1GNSWlT3LLhfK8pxIEkDKkLPjRDkvjsBfkIr9jYYnK4PjvOHmKaPH0ZTSQzVm4M/\nvMz48765bXGQd4xL77svOl5rK8uyJoMmyQq76t/aXV1iCMNLgIiZDHa9eodbgsJTeLDB92bf3zgb\nkHDPhp/5Y96aH08BelfvO9ZsntgDvmOi0++IymB9PI2l3eMx8LjleptsWU81WDExuENmSPn5b9V7\nww0PkB4L+OrwEVDHPmgQvzOp/S5lY86506IzyZk+EFaoisJPL4Ix7TXgo7u2wHc8Kssp0X5YZFj+\ntUOk8kYsuNRrd81CR6V+ukNkM89t+W4aw/ajKDTT0LmUqRhMGQvh2hOqw9UksTCdMr6/WgIz5pbm\nKniZXfCh3cMZu2TysZd0Gmg/MbZ6ohsBnlsnrft6p/E88NNo66e9qomw1v7eVWGswqmbDwalyPv1\nxBVjkSxrxfkyLQB1YfibsLY/wqmdq7CHSlB0eY3D5meq6O7XDf7jcjnKVJ3lnx8bvmKf6aT8I1cj\nHtPVm31bdpptslWZUHTXnDl5VYP4NJJQN/JJQ+GcRra/Ik+SxQ4vqTeRuhOtQb3NjBm4FpDEKSSH\nj3/IaA/l3KdxVNAbLRenx7/pEnd94HpKkLGiH9J++D+WtogNWlV5Ran0qN9ZVxtMgYRQ2CfhS+M8\nOoVZJYYvVWBFHmhz0Mng5gkK7LODy7ij23SNkqmbfMzeniulSE1jAHHSIgqxdMSNQ4Q4AwN1m4YH\nQ/xsFz07AK9LzQIQDv7U9Wr+nglKxlsXV4hcMSdcPHy6cOcH1+LQihIVUm4XUhH+8jEFRcwVzbKI\nGfP3Qa4PE3o6CHTTLgjitYN9jl/G7Y4dTuIWbIu9jgPWY/Z9eP0EIIj0WKWsFBD24E/QTfUUgNxH\nGe1uU+XisJ+7XHwnFN1GVgqCja43OyD+CIWdiYhsTWjUgpJ5E0fxc+AHqzHFY2a9Xj1wfDPyxyoA\nW1S9e0KjBPXF8hTpLMATGsbXCltlAQxJlttlBFZKCCAsI7R5cW+xpMyW/mU7SgBUJ2lPHybFdvIS\n/kkKwhO/kHKUXCYtD5Fvgg33/UXIA8UcEHrhUraEik9Cv0YEmwcEdEM+b6CMPDjwUqHMLLWJvB/r\nYZOfvrPtNP97tOh+Gzilb3WkMDsLHUw1HwbErVEhj11lziLbaej7JqgEO9/M8AC27Al7FXaRqDYP\nCuxwoB43b8tGyEmDFLCCjC8Kk1ztEP/gVA+n8Q5l5sev/rTz30Zxgwc5ZZ1d227+TLCP21iPo4O/\n1ZwVEJ0/mri5mBLBOP3qpG1jjuxhpb6xsDRuvbXY/bu6nxERErD1bIVcywy+vBTa65irGR6PBNhZ\nRLtGiZQ9eVfYdXcOnzksALgbMY3RihTlYwNLoDhz/KfMFGTo/3Gah8gk4zf8cCFZO+jFWjQ7l6nV\nZaFpZHFkxLWZxdn+9jKXsFEObkKPKJ01RmnwsIrgcszIiDb5qUx41z0djy6IcBO0+CJ2IigVN/XL\nADeVMeG/d55n0yNPBJtXwU0HxKtT95amNObp/i3V/o7cGrc1TfIfD6ucXn6RtcPGYh6v6pTh0wsn\nmitC17c2iHIWWU/b1+kGcN6VSOkti/66NmUcNWTQHUiQ2I/pD8RWfbxqGNXn2QQhSwST+hAve3p9\n3CqIBPuTqPwBNNWr2jH6IeaRn3adw9H+MCX1QYAF7v/zF2gaYnQVDTduzTN25/V8vUg4lPbOQqG8\n2KCc8NqRPN+trTzRMrh0HIeK8q/+G6pncDXe3PngfyXmfFpCIJUF9RiAs4/J/Yu4ZUd7Nso57o+9\nIA6EVndlXVZlK6nkkZRzhAdYfso8SfpArimn/HYTgGUpfs35MOvKk7zmKqXAxPZkcurMVQ01YS8u\nONptVvI0ZpoDxl/FyLoSGTPo0BzKwwj4UnI6xVjdsT0V5swbEFntLW9IArikjcP7AbfVyOXSats6\nTNoO3qGEve+FXkt/onl8a41AgCWlL00twIoOs6AasHipMeQkOgS0ipUaGjDKcn5ceCWM6+jm2JdC\npbP+MOMtLYYdCyLcULAkhpPwRQIkGQeDcRnsPAjuZWfUHPBWkwkzIHYn2fDi84yh2FvppMqxrLWH\ntNcrGlgWvpHDCdojVWATJI60DjXrYDvJwXNW2kNUC6ZIBr917ItTlQ5surQtNdLCMVKXEWoQNU7q\n5vXU4Cj19Cb84ao5ZpC1dWAI/CNtZyV+9D8HsSf1oISFMRwY4cOAnTDekXrOj/Zj/1qLeXU0HPw/\nuyNcYPiG2qitycy1Df7+/FuFDukKiLkrUsbkdvhOeFQ/LOBWfbBPtNd3m+/57kevqzQpwSQ3q1JL\nAfhHcE29kLQb6ZkrFywzimdO1QUhQLrDxd2C7A+H+0ErTsLOBt8mTIf0bHXUMG8jo8SF3fH3dcW0\ni9VqjocNa8gvtiDGpX4ejz2/hkdEgc50Nsogn1Yop21X8oNvDFJ9Z+2S46IilYBArzBIMhPc7GK7\nTzaIknEGcVckL+lip1TqCZOkxBQdWju+T9/x2rLovnQJScWz/DRT3QKfMf117zA83RxVQrZxfQw4\n15AcEPVUkobhsGOyWd/uonrJ18Chkp6zj8VX8Ha5smr+QpVq3eLzlb9br/VOnrAnUSZ0bvPvjQl1\nI6+lK7EaYF1Lef2z/LfRBTYgqXAewf3nzpmM0wdzIBK4+WCChRBH25ieuAj6DhGU/4dNd5iYkNKw\n5UFjIH0w/7U/+ugyHgDp+nC6JDYtfubj0m0KJJ87RJMmQ1mTNarOu0urmlikkD7+HDMSgYyLEtuQ\nGaSH5vSHsJNe1baNRTA9VZqhlK0zAIBSMEOEhwUqnE1As8+bX9mBFw1Yisk7M/bpzK1mIF1ayLiJ\nGtRL+mvAF7ogzydkw6AZq49ZnkRye/Rc3FSP0qOsX0GAdCjMyaPoSZ919BBXkDatQplglrL5Ap7G\nC9SnQ+UEph9gWx619N+OqIaVd0Sy4GHMXVNXZoWzCGStmOBFx5wU/Whmf+CQQC00fC5T2zyRX0X3\n8TKMKhvJpwWVNtsQv13de3iiNlO1r33Rr6Rz90IILkiLnaaOlZn0gsuUdQQFv5nAq9ZklwQU7St0\nUuSwd+CMyM3cBpYc0HdW3qNwu+ekYlkNKdIFoJ3e0E7qqdNgrYC3Gf12pJiH4lzbRTPZeJzMtMiJ\nS/W+W2H7pW8uOJhZtvIHy/r6/12etJ58zmR/j3PTISTH+55NnYBSGQhXfLN/PrZxEkqeUV44ke+K\ntGWb4cvQD9qBtaL/2JvQzWdwPwTNnq/VOMDHujxwxkazRZQLoavtItyYdaNm1gt8xEzjW2jnxkHL\n7KbB5ZaBXIktxcKqBK64RnziU/bgmFdkLltLuHI55XJSKFd6m/eTU2FmwVMg2rvrgS5i4TwtpL/a\nrsSKWWQCHSIYhb9xTqrzYigYpHuKDjayBqK9+OuA2rTgDdKq9oaxyR/jXySiUxcDh6/az9/NMLQe\n+KGX2bvG3wWdxOs215xclv2w75gXDDOqmYINX+R6Roj/5aUgY1dVU4YCrTi6JGSdprum/c8R6r3K\nBuNzCsiwGCuC+B8q8n8awIiiACjqG/gTisr2FnyUMF19VU65vml2ClFxMEIgiDsG+7uVpVF7Ks5f\nybAZ75BxISPCu2Liw27/nEs4H4aIfBZFm9ffGbAJBal071TlBZhk4rtNqVmQHiEou4C/NvmxcFNm\nZdBkKqo+rmrY3o+/7PrhbZPAZmgUbjAtMHtVne+vge0EF0uj/h3Sq9/2W6bgen0xIv/fzQVSGlPd\n46ZekLfUr6UsLfTrPd3ZFy1yrg8VGInFaN11yTTkTPzcD5p6MzOwLm7UJp18wmNmjk/BlTQ1zvvg\n7e9NX6SRJyF7YdaKwCQYxTQKm5lvUiBxrCcChQJdg6/BG+zVTZT+8x5ShfbbzcXnrfZXMB1RKLuv\nQilDIlQD5VNRgP2K/nbYxsMDjoPRRuQduQ9AG2NyeDT3fGzcxnaUhF6cMSgXV18yfbNBKrl/ie0/\nH7CkmgeL55l3iV2HtsERAx5kEki5NSNovvtZ+jLzxOiuMFxGe2YRpHttIX0l9YscBYzcuESoumlj\nRp6KFFo224Mw8LZSYX0+QLN/W8SRrww56eKNDbbiVU8DBgXEWLXhS/1q/+SoMLbvnr00BDAfbScp\nMOlo9rgdLsOBwD90jQAAvWVk42DxTWfqs/2Q6sE5CHHDEeytdzchnA+2sHM1Ua5LyW8R735BypzF\nyS7tDnyBRxdi8fLOqvDT+LrkjyQsdeCPaZ5HyGpPW55Mmqg00U78uV99LQOwL3Lu+klhr205h/Vh\nyqRvrSBDsjXlBcERGNTb874qY4U2oIdRTqkR8JatCImB6tOG4z4OGkZnCaMespRfx0xh1h/b8c4U\n0m3cjfx+GyjuXBXKNzK0L5f26aA4HLeOMwHuQtRxmhUth92jdHCtkyV5fzbr19dt3PdWn+DnghNw\nmvRsWnJq1pTlpo9aeDt3NDSHra0iEsRfxb3UD9AeHjI0+AkahdLHzNLPRihKpE4llriErZtBC09Y\n1pZq82vu7ZAyYxw9UowxtlJZJ+RcLopN9S34fJ9APRQ66/uuYuD68W+7tTiTNyZHoKkS7FY1Uu6W\nHFyanD61UeLyH9apnXw9DwRQisUpKCy3q21CqCEiWvQ5+C/vy5qC2N8WwBSqj61aW1yQyiYWkBXO\n4xQU+j7sgnBN81KG0kSJXHWcFk/h7X4X1tLr5Ggr890jmGDv7DA+VzdZ7Q3fTJofXmuTIgU1iE0B\neJdgyl1EXsPbo7hUVFVd2EgQRtj3vkHwSCjFVF0gMLaNVf9LcazqIvW4HFFI2tt8+9MFEyenBEgB\nh2xqefXa5q97T4n7zl52mZa4apuhFg21ZyMgeHFgcvbyMJ+BkFVkeKcVVLVyBkZ33V1fcKy90Lv1\nEQIYUQyIACjaEpO+V8EzSUHzmbiWHkouuOe7aRlkH8lTQFjwNnFjhii5SN7T/HR2gqfQoRpSLNoX\n11xPlONY3eNXFfbyVaOKUMCenFuAqN4TTcGrdAeKnFQHvGSbS8wuxr0L6LwRRtmN25YOmq9n5BxF\npV9Chlz3Nhtm+6T4ei3j3vremc2G9BTq8PZ1YLQZqJRyh3Tb2IMQ23HCLb3yoQ4ZpPg1ZZNymmug\nVql8TPMelPFuU3IEXjpgy0SDbqUvZKcP5PKHTuVpdY5eRizzWbn7a6akaK67C//8IU6pBT6WkpLA\nVDG7HQ5KKlwvriaieUvWovcdt+7QusnnssrSWlMdK9jrZ82u9HUYHVKV8Xd5hDB1jYVu6Px36hQ2\n0v1g782llhV76QhcNlBHkDU2CsK3X555FSOcdMTD8BI+n5h0GROXkhSGlodgZTbWppO5QN3jaeWZ\n9a1HLU6dNMfTCEeOUe88KwDZPEFqSG4p0VtwrI863aJ04foZhZDyAjI1PDUNtgBZO2Oz+DJyhXaa\nKSEoR2Yj36JwX9JPzW8mkGxRb5Wx9N9I1/Szbje9t4KwPjOml4qWWpMqrBbpyrs2396STi4KCNLQ\n8dD2nwuApS26e6KvA3swEStkmcg4lPaHt73uL6N1VQxViQ2EEy4rbFy0S2AJzYqERyU+GtstUOcW\nh04cyB/2ofzso/h7nK59EXXXc8lmeFNNll2++rzh4sKZqQajxs/8Gcj65TLhk+uPqyAaFKmmSZeW\nd6jvCOCCgywB1EHAYOnOb9vwGGRCO3JGCLmC7QDTjTOm0FkqGoMUKYsee9Jqd+AtP+t17eVGuIVY\ntAr571S/EkWBcgDYPevACCxmnBp9OjNNBOskcVRUg5XMIim40rW6rv7bFDEDgpcXtBTw5dz7m505\nEJTbnrS+//j8NK4fgaIOl5bKD5x2qP1Z5CcPQc1rxLrkLFrTy8XlEptKXR0t1lQXd0Wkef55TxMT\nqs89vIeZfvIhprc2C9fK2RVjSYAhkj6Iu7TCimjFyr+HmsOsOQQZdQ50WNhAid1TjahlCJ9yCSM2\nSFk2oFhu/qBAvz5cPs0x6lrrRmRIoxvX3WA+IElb9TyFBPyP4BWdTcbfqnQ6XGDijou91uAVawoD\n27aFmoq2OCWPF/Fp+D8dcmb/XoPpK0SOEHaBU1ILRJkdRd6Ys4bq4isO3Sg8vkyA2iNcEZ2DtGkV\nH9IgbGEg1Mv8sPc/wjFMhb4BEqxNWQEKiYgDyA9+0VdYpJdy5X5gZnJxYxhzpEOLZpbbnjd3UeK0\nEKkNXwA41V21GqTZrrUlF76kn367l0KZTNgiNodIaDhxBkTPLMOtpDt75KoJ4Mrtz7HxeJXlUMLs\nj3HezUvOkrRldg1d/XonaIPRDgjcQFhIRTjOEald59tKjB5scFlrOqdI9zQycV4HLXdjifdfH/Dr\nfrQHwLor3niSXfIlsq9V9vLUCFDTNCRYzaE+LlNQbFITqmDUqy70neszXu3lowOaugZOrCx/xLiP\nss7Ja4qppT2Ctc13JZXtKVL6TKDel2VCx7xv0TxpPluSpiKZKUTQwzEb//Cf3o8HRx2YSwZM+kXo\ndb6T5DfBGcLWIujpgWhXW1i1aawHOLQMRqa/bpKAA5En4IfdYbHy0jt2k40ZG11elMVI6RKAtaZb\niRfZ9R5+Q/n0q/XlsbqpiOST0JUqHw3TQzIUl3a/GTAEM1B7E4/aXxOBXoEIBgR+lDXq59z+aZ6V\na/qDF6Cq85iXpIprWSu5PAw2ImEaHr3kZMg5pBYq2xjpYIX0L+FWB+/rlaegVs8JRRX8w7TjuPiI\nldwrcr8nj1s9l18z3ZjIvvfO6i9F8v61PVCGw+cJMCffOL1DUXz2/A4LdTO0Qq63fsJBzfrwNPyM\n4L9m0il1+TVxHhXVoSuSoXNhiIJbWut7GbW+rvTCQJjWk9HIPTN9xKxKFZsH/oRcWIyUI3ogahdW\nH9NEjMeVGwKaYqs85ai7US4jnVmxeYqc6sL6b4AI8zQW9lDAoyygkqC5NsuGZrbk5/GwdIpbCUza\nlV4lvoWrT2nzlCPdE7HqdofSVI/GPQ7EIhG0S9jqrL83rET779F7bWP9oFwAM3WXq2FD3zm2vtbh\nc2dLOEuB32W9sPfobiDEuqaCkrDTI60b+AgewQJcZ9mzktJhauyA5bDFxm/U0ffkqJaEswDtl8AD\nmAo2U8WeHnyMJEqkxx5ld5cLyF2UAMmCM6lGPtpgvknUUkNYs/lD2XhqxuM3cNCLZuvieJKxtFvM\nLbd0bNRMCX6bSVLjKfv+IW0WDBrtuJ17aCr50G1IvprZKzT/xRPVIu0p6p8hNH4953J/ghs9oo7c\nlKQ8loRvT6zSp3GyffPZJOVn9gu8lInMpJwWkFydpk0q/59aiHDXSoigjSM50xfZkM2xB7PXVYTd\nQEfibQ8bp33CVYbaynaCCaQqHVGy+9ML5q0Dsu1Mgs7ttCcpp3W5akyYcO5d8+GUxBMUe0sNq4tl\npVZNNwltEOiqD+QngAx6UkKw0PCg2lxyNyCQZ/E/symhb7OauoiCzQZVF02qMdopaQmGiY/ODvoh\nYtacenkASzgbBSOk0fOO8SsKAaWfuD6KRT0n8bSgZSPboejfoQpVOEmcxM1fFfIbZn60elHh0TWB\nclK+JftnN+AWkwQfTB/JKniwZ+lvqCsuieW1NmyUSR7ykBcRXXSA/0az0coEL/9bCmUeJje42E7X\n3q948+DGDEJc3wvWBANApYi3T8dvHoSv/xB3Sg3uVrCc6Q+vzOhQ1zgvY16rPkvBghqXZg4f/ibO\nGUrA30eB9dJYQkpT6sAhBVevG7t2YLCNsCNH/EpX88wA24JkJNBICyrhs/fbTQI5l86rmfxDybaZ\nV+C5cLUfrLvS74A9KOm8LzImz38+RE9naZuWIUwEKZtI/IqDkLJksZiw7jp+r1Rt7CnpJ9kUQ/ZY\nxwC6FwKaMOPLuelslAkGiig+MUGK8U8q/0wzWTJQgRZBSfu2Md+jmJQdLrdN4HfPGddtNg/rkqpZ\nGnTqmDTCNZHKaKyh8av5iZgAl4C5nsLhKmLgbbDFzsnrzKEv/IoHy9a2gtR2q2q9+ZmZ+TI9YeuG\nVfTbvZgjNKN+nNiL2kT1tpRoHf07mpdAkuAWMrXqddkcn9QyHYLlNOp0dRup0GM1yx0nHY/0hNZS\ngSJkzkBSDJu8fLjwG48jloXCrLjLGo/IUBDwOwUhyCk9ZJtLg5AefO1JndkWU33X+0y1xJGhoK6X\nt6FG7I4nyaqrsoFB6Ha0+UWSqsM/H+hyWWejJpBaI5nHPEZBbLwwaVm10hAFZdZ7oWB2Ve0Dbnyc\npOrPOVUmWOxTiIt5+hkylvrkGu1sQfRU1kBh7ynYIRKOvgljxP/AY0TI7Xs5ZxGJEJn2Y2H1PseT\nxvStZw5RwT5vYJxk/4tT+g9K3BU0LtE0UyGwpIDNlHpLPIT6CIYXNO/GC6vUfCrJh3qh8Pnyd0sX\nNEktZgvb5zGBYxGF46EU9bBwCX0s84fJ97aaxn/gTVv0Hcwq3cUb7U35uO5LHLjrlnUCh29jH0C4\nldzTqhf4Ch9XicZ/uJPVEONESBUmYskm2Y4EuudYmwvVcwEKCAOpmOVSfIHqvjU6EtHuvL2cdO8D\nx41OztnDd/549tkkn/p5SAcs25RZf0vBjrsl9Y1Iezqa3V8z0ZhE3rNUhNB5Oon2IkuC0Rvvltt0\np98veNeUyJDoO2k+hmaWflAEhX1e1RCZNLYx0xSquZxXD0VeaFUEObTKXdejMa7v597GFmoVPkPh\nYKH6ST9ati0TjVdJf+dNVqBRcaHkEzJcAMZLSdNRhPRTOB8J2OM71ealSLZ2lR31089Zlq2QZNaj\nK/viSQPz9ANHmXy4Y9WozP0JCYvMvkRgeF6hmpUEozNEh6efj09VSvAQ80lRJEP4pkFKJoahZ3Wh\nsGB5Z+pR90jHHKeMmQM6lKnUbSlr5YUmqeaSnY2FH60mUkKudlzklCc093iBPlN9fpdkbyQYXbZx\nfa5JtVZLHRLhAJVlIE/gR0js7KeS6d9pKkTFPRPbBwhFPPmZ1TZH//Z99ZlfRf0puhG2nMjqC8Aj\npYZlQ3yB3QR4fmEtLxIjdpY2/IsBNuR4WMI9P7scb/3S9L29X8bwzpVCBQy6WgdogzCZwX/KSInT\nqudwNMs34MHNXvRRBpzB4PVypZOD2LPg4A/JFwAe4PaD7f12CqAISeKEDLQJ8mgfGXEgYzOkRrI/\n3+YV8GNHuTH111rUwy5EO/xyhuMQCnKcUeTbg4hNXfYVdHTr/rsDNAhZg4RfYg2qBoBQblA+Hgoh\nkbvSH9IxR3JbuZGgoS9Dtsr3ichy2pHeO+wsbz1+EFBXE2+Nv1o27Ctl9YTjZy1FkA4F4DugCwI5\nJwmp4CSxlR5V9SDaFHV+Vu1TwBdQY3ttVnuAN6i7awhN1Ad1tIIaF8TH5pERQd5S0fYyxWgjLhn9\npHWVDFC2G+fhIL3BhQUohuHk4oCLQ6L5awnrPPLRqRn4zQDlebCN+fK9J0gdnvHyNyYQ/kaeXF9x\n4QhjVofyFnwwGIIh+pEx3UggaiMCTfm12/JPErbaC2cWkqNJaBKJ+kZUBwTutslEOVEue6ZPibBC\nlvVbw1M+zU3xyPx4SY/MzPQav6MEvRbaT7aTZcFf9la1TtyYvLgsQIB+uB1Jki8vLi6HOMcBThQv\nemw1tXDJlwv/TYh78mMNpllnTGG2prieiBG9cResrv5mEZRJS1RjRyTk9AGQ9GaqTIs0MAVikqco\neK2iSkNM0GWEjHtSluZrD/SzfyYXZsSzJKzD/RmeX2pJmqBaZ1KHgSOzUJC3O6GAQiLE2SDYrQfc\noA14lbLXgYldDUXJX5nrM6EhnNcaT5xBYelhPiqIG/qOsAt4HWOm3SdtK9P6COkCKAWUXhHTeukL\nmKEVwZsqRLRbu0SdhxgItkILQs0JHSpLRmuJfkmZgm53NthwkWNu2unlsZdzeNpVDXL9ilhT2iO1\nNH7HurARdw83ECxK3Who2IcWtdm9+cJ8LNR925XkNJKhHJhhQXGa4GesfJTlLwa0J3J1olAv7dJD\nIVeq5XnXOyW6gzhDzTpK2afgLW3Thq9EY8cM2oWk+vjabJ5i094lTotFRSv9B2lzbIuWBxF3JH0I\nudYhXIW6B9qFceaPBMQM793OUBQSBOi3WGu/Lm0k0FUyRzsTPr/9d1BRWD9b5YqxnWniN/mzDQmA\nYZpqnFuhZFS83FJ7EriLaOJXoisxsE2uVFxQZ7E3c0/WVyt9Pyk+Rq9vxE2c7PUmojV3Rewu3xgC\nHUxvS/q4yXuSWMwqLEbhRt8KyDGB2EcHrMGojI9A0ILuJiueXyd++NuiozOyn33QRNg79tDZH3mv\ni+8I7tqNxp3T0CfBA9QeH1tn6GHvkNBaiaZJ4ioqg2EiNpcbn5nNy33NT53S9uSlyB0Gzkqj9wf8\n0hR3wtkRcGA248PtuON0okzf7rE1mJDI5+hfpRgGyJjEbfJixeU7Lhk1PobdVkkGahSBtTqc2Ldk\noQMllEOGJTuXu46HY55ne9BLbK29u+3MMBz1KAZ58qKCo7sPv5eDsexOr/w3IGHx6Kdyme9VC4gI\nHpr/JGRH5gXt8I9AjgOObZ8YzWCs/KErnh5vKjYPgooq9PMFmD0MKcDUxefsPGCZbtJmcVefKM6h\nBlmVXH28KYc1/71keR1eZBOfhZN5H4IKnWJvnGSPEPWlNmkHDCmMBA/arDVDvUljsoTjFZDXP7T0\n+TjMu/o/7F+zMcZWiYKhgVKkKdWexgpiHXrV/jzlxFhT9fPcBL331pgw832rrR3zn2xBtdx3s/Ag\nK1Cob56W+pntouKPOSBv235PCfPB6A6/Ccw7rvfYZk8LHxle4Y1/PzsISmSD/LVo4cm/Exalc3bJ\n+jWv5iO6jmO2H94k1iA0Nv/3zHgy5iIpqr1Mv6JDpEAtk7Fh/Vh31tsj8vm7ypdcArVQLrZwKYjX\nULh2r6jJOaE8J4PZIgVVGLE9YOmo7BFmfeOhlhkettJhttRcLQdBg126cn1h07bgI2/R4A8FI5ux\nEaWY3u77/vSyaIdQhCF/P3CDABPg+NUyB2mOZkueZZLn5WcQXi/qsIaWa/tXDAGrSaNPF0BUpr0D\nNORQ2oB+sPYpR+iCKvBonHa0hnYsrGlwdwEsz3yguKJpXImkzHAzuYg4Liz6ePZcCW2ZhCSATfZC\nnsGKryGfcDacjk9bvdnNyM0GErMfMbCStu5PZ2r7tRBl+JAYLs0q4OUbr3pX0ne4yoJ31nWSCsl/\no6uk+txkgX3mufLWDGXeNyfaar2RWSKXXQNY1ypDhVTMGj8kPYvQq5HkaZ11Xme0QHgfuRwJqtqh\n8lzVdEQqR1iXV4T6JXENbyBJKTdtkWgcHSzL2s489b3ObCag7j8FPZT5bw+8FliIPY0yxkAr0cRR\ndaKSqx8MxxqntzyJSv66i46SMpCdBKRq0RxZxkv+pHlbESDlhJnZATCho6xuoLk3LI/X2BFR4VX0\numzxeRO/zPXvZWEFgvWb7vPucX5mlBx4j/13u9aZVNcv8qzODK5Tvgdgwc5TSSZq49U0v+9FJFNu\nvSxtSDPPL0b52168r8Kj8O5EgF745J7FdO8n+gu+ma79Qfo/v3LNezC1Q7phWk+RLwYWEB/fC44v\nDbkUkzn7niBiRc+gffcMBzcWNXXMg6ym6FHOMi+xkiVFXFvLIc39i1tT+PyocfD9Yf2DSG2WtUXb\nrExRkxKCe/O/375k4LLknHaBoJmB7m4FcgFZl6WZcgL7Ak78RhFXrmeGuxcuGW4b2njWh+RwOFuD\n1tPq/OWTREvGcq4/OCyOPhuOmLuJuFbKroZYZQKxLS9rTBBVudy8Lm6wygRT4cNoQgO0Ft6wE7Dk\nLVV5SkjkW1wCKNuC32+quUYlwToikg8OX9hqMxp8EAryEIAkhcYpC4+WBh682E/q+e3UzWLiutoy\nxserP8cf15U6aL4UT7nL/Nxmwhw6EzKtHC8JgJevouggntc2V+PvI6qi9bqstuyZu2ogmWkrB9O/\n0vwCkKjyNJMOY9w4Ltb+Jc3mm6sZ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protect end_protected\n", "num_lines": 510}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_1 (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26,\nprobe27,\nprobe28,\nprobe29,\nprobe30,\nprobe31,\nprobe32,\nprobe33,\nprobe34,\nprobe35,\nprobe36,\nprobe37,\nprobe38,\nprobe39,\nprobe40,\nprobe41,\nprobe42,\nprobe43\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [63 : 0] probe1;\ninput [1 : 0] probe2;\ninput [0 : 0] probe3;\ninput [0 : 0] probe4;\ninput [63 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [0 : 0] probe8;\ninput [0 : 0] probe9;\ninput [511 : 0] probe10;\ninput [0 : 0] probe11;\ninput [0 : 0] probe12;\ninput [1 : 0] probe13;\ninput [511 : 0] probe14;\ninput [63 : 0] probe15;\ninput [0 : 0] probe16;\ninput [2 : 0] probe17;\ninput [2 : 0] probe18;\ninput [4 : 0] probe19;\ninput [4 : 0] probe20;\ninput [7 : 0] probe21;\ninput [0 : 0] probe22;\ninput [2 : 0] probe23;\ninput [1 : 0] probe24;\ninput [4 : 0] probe25;\ninput [0 : 0] probe26;\ninput [7 : 0] probe27;\ninput [2 : 0] probe28;\ninput [1 : 0] probe29;\ninput [0 : 0] probe30;\ninput [3 : 0] probe31;\ninput [3 : 0] probe32;\ninput [3 : 0] probe33;\ninput [3 : 0] probe34;\ninput [0 : 0] probe35;\ninput [3 : 0] probe36;\ninput [3 : 0] probe37;\ninput [4 : 0] probe38;\ninput [0 : 0] probe39;\ninput [0 : 0] probe40;\ninput [0 : 0] probe41;\ninput [0 : 0] probe42;\ninput [0 : 0] probe43;\n\n\nendmodule\n", "num_lines": 149}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"ila_1,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_1,ila,{x_ipProduct=Vivado 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=1,C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1,C_PROBE0_TYPE=0,C_PROBE1_TYPE=0,C_PROBE2_TYPE=0,C_PROBE3_TYPE=0,C_PROBE4_TYPE=0,C_PROBE5_TYPE=0,\\\nC_PROBE6_TYPE=0,C_PROBE7_TYPE=0,C_PROBE8_TYPE=0,C_PROBE9_TYPE=0,C_PROBE10_TYPE=0,C_PROBE11_TYPE=0,C_PROBE12_TYPE=0,C_PROBE13_TYPE=0,C_PROBE14_TYPE=0,C_PROBE15_TYPE=0,C_PROBE16_TYPE=0,C_PROBE17_TYPE=0,C_PROBE18_TYPE=0,C_PROBE19_TYPE=0,C_PROBE20_TYPE=0,C_PROBE21_TYPE=0,C_PROBE22_TYPE=0,C_PROBE23_TYPE=0,C_PROBE24_TYPE=0,C_PROBE25_TYPE=0,C_PROBE26_TYPE=0,C_PROBE27_TYPE=0,C_PROBE28_TYPE=0,C_PROBE29_TYPE=0,C_PROBE30_TYPE=0,C_PROBE31_TYPE=0,C_PROBE32_TYPE=0,C_PROBE33_TYPE=0,C_PROBE34_TYPE=0,C_PROBE35_TYPE=0,C_PROBE36_TYPE=0,C_PROBE37_TYPE=0,C_PROBE38_TYPE=0,C_PROBE39_TYPE=0,C_PROBE40_TYPE=0,C_PROBE41_TYPE=0,C_PROBE42_TYPE=0,C_PROBE43_TYPE=0,C_PROBE44_TYPE=1,C_PROBE45_TYPE=1,C_PROBE46_TYPE=1,C_PROBE47_TYPE=1,C_PROBE48_TYPE=1,C_PROBE49_TYPE=1,C_PROBE50_TYPE=1,C_PROBE51_TYPE=1,C_PROBE52_TYPE=1,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,\\\nC_PROBE106_TYPE=1,C_PROBE107_TYPE=1,C_PROBE108_TYPE=1,C_PROBE109_TYPE=1,C_PROBE110_TYPE=1,C_PROBE111_TYPE=1,C_PROBE112_TYPE=1,C_PROBE113_TYPE=1,C_PROBE114_TYPE=1,C_PROBE115_TYPE=1,C_PROBE116_TYPE=1,C_PROBE117_TYPE=1,C_PROBE118_TYPE=1,C_PROBE119_TYPE=1,C_PROBE120_TYPE=1,C_PROBE121_TYPE=1,C_PROBE122_TYPE=1,C_PROBE123_TYPE=1,C_PROBE124_TYPE=1,C_PROBE125_TYPE=1,C_PROBE126_TYPE=1,C_PROBE127_TYPE=1,C_PROBE128_TYPE=1,C_PROBE129_TYPE=1,C_PROBE130_TYPE=1,C_PROBE131_TYPE=1,C_PROBE132_TYPE=1,C_PROBE133_TYPE=1,C_PROBE134_TYPE=1,C_PROBE135_TYPE=1,C_PROBE136_TYPE=1,C_PROBE137_TYPE=1,C_PROBE138_TYPE=1,C_PROBE139_TYPE=1,C_PROBE140_TYPE=1,C_PROBE141_TYPE=1,C_PROBE142_TYPE=1,C_PROBE143_TYPE=1,C_PROBE144_TYPE=1,C_PROBE145_TYPE=1,C_PROBE146_TYPE=1,C_PROBE147_TYPE=1,C_PROBE148_TYPE=1,C_PROBE149_TYPE=1,C_PROBE150_TYPE=1,C_PROBE151_TYPE=1,C_PROBE152_TYPE=1,C_PROBE153_TYPE=1,C_PROBE154_TYPE=1,C_PROBE155_TYPE=1,C_PROBE156_TYPE=1,C_PROBE157_TYPE=1,C_PROBE158_TYPE=1,C_PROBE159_TYPE=1,C_PROBE160_TYPE=1,C_PROBE161_TYPE=1,C_PROBE162_TYPE=1,C_PROBE163_TYPE=1,C_PROBE164_TYPE=1,C_PROBE165_TYPE=1,C_PROBE166_TYPE=1,C_PROBE167_TYPE=1,C_PROBE168_TYPE=1,C_PROBE169_TYPE=1,C_PROBE170_TYPE=1,C_PROBE171_TYPE=1,C_PROBE172_TYPE=1,C_PROBE173_TYPE=1,C_PROBE174_TYPE=1,C_PROBE175_TYPE=1,C_PROBE176_TYPE=1,C_PROBE177_TYPE=1,C_PROBE178_TYPE=1,C_PROBE179_TYPE=1,C_PROBE180_TYPE=1,C_PROBE181_TYPE=1,C_PROBE182_TYPE=1,C_PROBE183_TYPE=1,C_PROBE184_TYPE=1,C_PROBE185_TYPE=1,C_PROBE186_TYPE=1,C_PROBE187_TYPE=1,C_PROBE188_TYPE=1,C_PROBE189_TYPE=1,C_PROBE190_TYPE=1,C_PROBE191_TYPE=1,C_PROBE192_TYPE=1,C_PROBE193_TYPE=1,C_PROBE194_TYPE=1,C_PROBE195_TYPE=1,C_PROBE196_TYPE=1,C_PROBE197_TYPE=1,C_PROBE198_TYPE=1,C_PROBE199_TYPE=1,C_PROBE200_TYPE=1,C_PROBE201_TYPE=1,C_PROBE202_TYPE=1,C_PROBE203_TYPE=1,C_PROBE204_TYPE=1,C_PROBE205_TYPE=1,\\\nC_PROBE206_TYPE=1,C_PROBE207_TYPE=1,C_PROBE208_TYPE=1,C_PROBE209_TYPE=1,C_PROBE210_TYPE=1,C_PROBE211_TYPE=1,C_PROBE212_TYPE=1,C_PROBE213_TYPE=1,C_PROBE214_TYPE=1,C_PROBE215_TYPE=1,C_PROBE216_TYPE=1,C_PROBE217_TYPE=1,C_PROBE218_TYPE=1,C_PROBE219_TYPE=1,C_PROBE220_TYPE=1,C_PROBE221_TYPE=1,C_PROBE222_TYPE=1,C_PROBE223_TYPE=1,C_PROBE224_TYPE=1,C_PROBE225_TYPE=1,C_PROBE226_TYPE=1,C_PROBE227_TYPE=1,C_PROBE228_TYPE=1,C_PROBE229_TYPE=1,C_PROBE230_TYPE=1,C_PROBE231_TYPE=1,C_PROBE232_TYPE=1,C_PROBE233_TYPE=1,C_PROBE234_TYPE=1,C_PROBE235_TYPE=1,C_PROBE236_TYPE=1,C_PROBE237_TYPE=1,C_PROBE238_TYPE=1,C_PROBE239_TYPE=1,C_PROBE240_TYPE=1,C_PROBE241_TYPE=1,C_PROBE242_TYPE=1,C_PROBE243_TYPE=1,C_PROBE244_TYPE=1,C_PROBE245_TYPE=1,C_PROBE246_TYPE=1,C_PROBE247_TYPE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*)\n\nmodule ila_1 (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26,\nprobe27,\nprobe28,\nprobe29,\nprobe30,\nprobe31,\nprobe32,\nprobe33,\nprobe34,\nprobe35,\nprobe36,\nprobe37,\nprobe38,\nprobe39,\nprobe40,\nprobe41,\nprobe42,\nprobe43\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [63 : 0] probe1;\ninput [1 : 0] probe2;\ninput [0 : 0] probe3;\ninput [0 : 0] probe4;\ninput [63 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [0 : 0] probe8;\ninput [0 : 0] probe9;\ninput [511 : 0] probe10;\ninput [0 : 0] probe11;\ninput [0 : 0] probe12;\ninput [1 : 0] probe13;\ninput [511 : 0] probe14;\ninput [63 : 0] probe15;\ninput [0 : 0] probe16;\ninput [2 : 0] probe17;\ninput [2 : 0] probe18;\ninput [4 : 0] probe19;\ninput [4 : 0] probe20;\ninput [7 : 0] probe21;\ninput [0 : 0] probe22;\ninput [2 : 0] probe23;\ninput [1 : 0] probe24;\ninput [4 : 0] probe25;\ninput [0 : 0] probe26;\ninput [7 : 0] probe27;\ninput [2 : 0] probe28;\ninput [1 : 0] probe29;\ninput [0 : 0] probe30;\ninput [3 : 0] probe31;\ninput [3 : 0] probe32;\ninput [3 : 0] probe33;\ninput [3 : 0] probe34;\ninput [0 : 0] probe35;\ninput [3 : 0] probe36;\ninput [3 : 0] probe37;\ninput [4 : 0] probe38;\ninput [0 : 0] probe39;\ninput [0 : 0] probe40;\ninput [0 : 0] probe41;\ninput [0 : 0] probe42;\ninput [0 : 0] probe43;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_5_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(44),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2017),\n.C_MINOR_VERSION(4),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(0),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(4),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH 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65_MU_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT(1),\n.C_PROBE275_MU_CNT(1),\n.C_PROBE276_MU_CNT(1),\n.C_PROBE277_MU_CNT(1),\n.C_PROBE278_MU_CNT(1),\n.C_PROBE279_MU_CNT(1),\n.C_PROBE280_MU_CNT(1),\n.C_PROBE281_MU_CNT(1),\n.C_PROBE282_MU_CNT(1),\n.C_PROBE283_MU_CNT(1),\n.C_PROBE284_MU_CNT(1),\n.C_PROBE285_MU_CNT(1),\n.C_PROBE286_MU_CNT(1),\n.C_PROBE287_MU_CNT(1),\n.C_PROBE288_MU_CNT(1),\n.C_PROBE289_MU_CNT(1),\n.C_PROBE290_MU_CNT(1),\n.C_PROBE291_MU_CNT(1),\n.C_PROBE292_MU_CNT(1),\n.C_PROBE293_MU_CNT(1),\n.C_PROBE294_MU_CNT(1),\n.C_PROBE295_MU_CNT(1),\n.C_PROBE296_MU_CNT(1),\n.C_PROBE297_MU_CNT(1),\n.C_PROBE298_MU_CNT(1),\n.C_PROBE299_MU_CNT(1),\n.C_PROBE300_MU_CNT(1),\n.C_PROBE301_MU_CNT(1),\n.C_PROBE302_MU_CNT(1),\n.C_PROBE303_MU_CNT(1),\n.C_PROBE304_MU_CNT(1),\n.C_PROBE305_MU_CNT(1),\n.C_PROBE306_MU_CNT(1),\n.C_PROBE307_MU_CNT(1),\n.C_PROBE308_MU_CNT(1),\n.C_PROBE309_MU_CNT(1),\n.C_PROBE310_MU_CNT(1),\n.C_PROBE311_MU_CNT(1),\n.C_PROBE312_MU_CNT(1),\n.C_PROBE313_MU_CNT(1),\n.C_PROBE314_MU_CNT(1),\n.C_PROBE315_MU_CNT(1),\n.C_PROBE316_MU_CNT(1),\n.C_PROBE317_MU_CNT(1),\n.C_PROBE318_MU_CNT(1),\n.C_PROBE319_MU_CNT(1),\n.C_PROBE320_MU_CNT(1),\n.C_PROBE321_MU_CNT(1),\n.C_PROBE322_MU_CNT(1),\n.C_PROBE323_MU_CNT(1),\n.C_PROBE324_MU_CNT(1),\n.C_PROBE325_MU_CNT(1),\n.C_PROBE326_MU_CNT(1),\n.C_PROBE327_MU_CNT(1),\n.C_PROBE328_MU_CNT(1),\n.C_PROBE329_MU_CNT(1),\n.C_PROBE330_MU_CNT(1),\n.C_PROBE331_MU_CNT(1),\n.C_PROBE332_MU_CNT(1),\n.C_PROBE333_MU_CNT(1),\n.C_PROBE334_MU_CNT(1),\n.C_PROBE335_MU_CNT(1),\n.C_PROBE336_MU_CNT(1),\n.C_PROBE337_MU_CNT(1),\n.C_PROBE338_MU_CNT(1),\n.C_PROBE339_MU_CNT(1),\n.C_PROBE340_MU_CNT(1),\n.C_PROBE341_MU_CNT(1),\n.C_PROBE342_MU_CNT(1),\n.C_PROBE343_MU_CNT(1),\n.C_PROBE344_MU_CNT(1),\n.C_PROBE345_MU_CNT(1),\n.C_PROBE346_MU_CNT(1),\n.C_PROBE347_MU_CNT(1),\n.C_PROBE348_MU_CNT(1),\n.C_PROBE349_MU_CNT(1),\n.C_PROBE350_MU_CNT(1),\n.C_PROBE351_MU_CNT(1),\n.C_PROBE352_MU_CNT(1),\n.C_PROBE353_MU_CNT(1),\n.C_PROBE354_MU_CNT(1),\n.C_PROBE355_MU_CNT(1),\n.C_PROBE356_MU_CNT(1),\n.C_PROBE357_MU_CNT(1),\n.C_PROBE358_MU_CNT(1),\n.C_PROBE359_MU_CNT(1),\n.C_PROBE360_MU_CNT(1),\n.C_PROBE361_MU_CNT(1),\n.C_PROBE362_MU_CNT(1),\n.C_PROBE363_MU_CNT(1),\n.C_PROBE364_MU_CNT(1),\n.C_PROBE365_MU_CNT(1),\n.C_PROBE366_MU_CNT(1),\n.C_PROBE367_MU_CNT(1),\n.C_PROBE368_MU_CNT(1),\n.C_PROBE369_MU_CNT(1),\n.C_PROBE370_MU_CNT(1),\n.C_PROBE371_MU_CNT(1),\n.C_PROBE372_MU_CNT(1),\n.C_PROBE373_MU_CNT(1),\n.C_PROBE374_MU_CNT(1),\n.C_PROBE375_MU_CNT(1),\n.C_PROBE376_MU_CNT(1),\n.C_PROBE377_MU_CNT(1),\n.C_PROBE378_MU_CNT(1),\n.C_PROBE379_MU_CNT(1),\n.C_PROBE380_MU_CNT(1),\n.C_PROBE381_MU_CNT(1),\n.C_PROBE382_MU_CNT(1),\n.C_PROBE383_MU_CNT(1),\n.C_PROBE384_MU_CNT(1),\n.C_PROBE385_MU_CNT(1),\n.C_PROBE386_MU_CNT(1),\n.C_PROBE387_MU_CNT(1),\n.C_PROBE388_MU_CNT(1),\n.C_PROBE389_MU_CNT(1),\n.C_PROBE390_MU_CNT(1),\n.C_PROBE391_MU_CNT(1),\n.C_PROBE392_MU_CNT(1),\n.C_PROBE393_MU_CNT(1),\n.C_PROBE394_MU_CNT(1),\n.C_PROBE395_MU_CNT(1),\n.C_PROBE396_MU_CNT(1),\n.C_PROBE397_MU_CNT(1),\n.C_PROBE398_MU_CNT(1),\n.C_PROBE399_MU_CNT(1),\n.C_PROBE400_MU_CNT(1),\n.C_PROBE401_MU_CNT(1),\n.C_PROBE402_MU_CNT(1),\n.C_PROBE403_MU_CNT(1),\n.C_PROBE404_MU_CNT(1),\n.C_PROBE405_MU_CNT(1),\n.C_PROBE406_MU_CNT(1),\n.C_PROBE407_MU_CNT(1),\n.C_PROBE408_MU_CNT(1),\n.C_PROBE409_MU_CNT(1),\n.C_PROBE410_MU_CNT(1),\n.C_PROBE411_MU_CNT(1),\n.C_PROBE412_MU_CNT(1),\n.C_PROBE413_MU_CNT(1),\n.C_PROBE414_MU_CNT(1),\n.C_PROBE415_MU_CNT(1),\n.C_PROBE416_MU_CNT(1),\n.C_PROBE417_MU_CNT(1),\n.C_PROBE418_MU_CNT(1),\n.C_PROBE419_MU_CNT(1),\n.C_PROBE420_MU_CNT(1),\n.C_PROBE421_MU_CNT(1),\n.C_PROBE422_MU_CNT(1),\n.C_PROBE423_MU_CNT(1),\n.C_PROBE424_MU_CNT(1),\n.C_PROBE425_MU_CNT(1),\n.C_PROBE426_MU_CNT(1),\n.C_PROBE427_MU_CNT(1),\n.C_PROBE428_MU_CNT(1),\n.C_PROBE429_MU_CNT(1),\n.C_PROBE430_MU_CNT(1),\n.C_PROBE431_MU_CNT(1),\n.C_PROBE432_MU_CNT(1),\n.C_PROBE433_MU_CNT(1),\n.C_PROBE434_MU_CNT(1),\n.C_PROBE435_MU_CNT(1),\n.C_PROBE436_MU_CNT(1),\n.C_PROBE437_MU_CNT(1),\n.C_PROBE438_MU_CNT(1),\n.C_PROBE439_MU_CNT(1),\n.C_PROBE440_MU_CNT(1),\n.C_PROBE441_MU_CNT(1),\n.C_PROBE442_MU_CNT(1),\n.C_PROBE443_MU_CNT(1),\n.C_PROBE444_MU_CNT(1),\n.C_PROBE445_MU_CNT(1),\n.C_PROBE446_MU_CNT(1),\n.C_PROBE447_MU_CNT(1),\n.C_PROBE448_MU_CNT(1),\n.C_PROBE449_MU_CNT(1),\n.C_PROBE450_MU_CNT(1),\n.C_PROBE451_MU_CNT(1),\n.C_PROBE452_MU_CNT(1),\n.C_PROBE453_MU_CNT(1),\n.C_PROBE454_MU_CNT(1),\n.C_PROBE455_MU_CNT(1),\n.C_PROBE456_MU_CNT(1),\n.C_PROBE457_MU_CNT(1),\n.C_PROBE458_MU_CNT(1),\n.C_PROBE459_MU_CNT(1),\n.C_PROBE460_MU_CNT(1),\n.C_PROBE461_MU_CNT(1),\n.C_PROBE462_MU_CNT(1),\n.C_PROBE463_MU_CNT(1),\n.C_PROBE464_MU_CNT(1),\n.C_PROBE465_MU_CNT(1),\n.C_PROBE466_MU_CNT(1),\n.C_PROBE467_MU_CNT(1),\n.C_PROBE468_MU_CNT(1),\n.C_PROBE469_MU_CNT(1),\n.C_PROBE470_MU_CNT(1),\n.C_PROBE471_MU_CNT(1),\n.C_PROBE472_MU_CNT(1),\n.C_PROBE473_MU_CNT(1),\n.C_PROBE474_MU_CNT(1),\n.C_PROBE475_MU_CNT(1),\n.C_PROBE476_MU_CNT(1),\n.C_PROBE477_MU_CNT(1),\n.C_PROBE478_MU_CNT(1),\n.C_PROBE479_MU_CNT(1),\n.C_PROBE480_MU_CNT(1),\n.C_PROBE481_MU_CNT(1),\n.C_PROBE482_MU_CNT(1),\n.C_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1),\n.C_PROBE691_MU_CNT(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synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4327}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nYugOLIF1XBreTDYRaNSWelgjmV3GIQ3y7FKiDB9UiIB++fAUC4TXcrfthfgN8befqwACkO3Q4k0c\nvJxv/aokgQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nP86BhFBNNa0qr9Q2+Wo0KACiIyDg4VPZdSis8bLUVn6FrcCD6TyMD6qWsX7GqSzkSyajfw5KoNS5\nrAZcRWAMv14anbm7VDJCIblrxr97wW1wDK0tJz6KsyHENdmS+W0PhSl0PyC6LE8TbUq4mev1WMPa\ne8qt1TLduNZhmfYNEEg=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\ngWBenVTIP5Q+rcNXfn1zPEjuUtszskvpUVNF25Xh81JnRdMPCp/0AGJPx+mPKwQ62keEUCK7jImu\n0uCqq7uEhg8CAhGkckxz0ziMi5p3crim/FOPfZSxzcfVA0myImyw/jA25kK2gqWItxmETSoXCqJJ\nxjTH/Kdlxzn5v3BlGFnjUMmgDpw+7ZlRLWclsVDPWcyttlqzmOpUVNRybjmRjQ047dZKoaEnV7aL\nJadzAQ1SqJzBdkDtBC4ls9rDZ0efLPq2CaHSH2lKmJWzqvjdbahTe/uDqwZlM/3ri9uvioLaock3\nBYN0ATxKAINgg8QSBFGOvETVtbNj0tmio/74Jg==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUA332GmFKmVHrrGry7Cyuflehk/VbtxlBHEATtE4ZDxpaTPEmq4fqpuW3/eIdDceGsGBiaQuMN9K\nWHRjmvo00KBUbhMYtfB1gjlmZEboE2pGVM53sCnoWcRuUcFptlHy3SPD43x91G4s/5AG3W+1+WfG\ndqqfUNJVltc7+nD/QSz52JWyt2BKcwXzXUegWHFyWPlXXyRha6uiHm5A3aFVX9XSCQMUBVg9KOgQ\nr17LLKqYda/v6o1fu2DbIpPXqeviObYOGtxIlZlCKEQ0WQ16wVhC7M7JMUM8K1ajQIP6aFm+lH0T\nT0TAEilCZfV2IBv8ZeVngUGkozMdcE2q607VAg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nJkclL4oQ89VKThgpnFORp4DkQ+l+oHyNRU+cUXBcYSussbqYTJL6YmJORdubTTO26u6Gzu7Zi8eR\nCof7Krp+GgFdv/lyHLisqmpxJDZ7fQJTFSmWQ1sN09PbMajgp5uypgG17Qqsv6Efx7DaBK5bWBFL\nzYY4TfY8F27SWO7q+F4ZXrJVV+ljd3jMxOp0CO33BlH7VTdJmnHbnGwVoy7NS7ktTu5O4mtjSy5B\nim8NDWKOPmwonslxiaCWWhRcIUWJMoS3RW+hbISleB+u2f6Hv6Cq0ewXO8bpInYwlzrVk138Qwn8\nPZory2IpEEHyD3/RAkNZjAO5MGkRMmlC6knbhg==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nP0095JhTyRSuAcV3jYJyGhT1pAQ63Ikz2jcw/xarWfO4myeR2ki2IxiL2BogiBQPifhiQ+8e/taC\nZCqKABC2nUd7sP5K5FMLxqEqvaSGhMtRO2Qx+bTN2vfUmVhFmm5F0IDL69aSPE0VUYhlP+Aw6isG\nmHBHYBCtHhMlBBTHiBI=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfVKST5L4zOIHEw8rTePPdwZAh4xL2unQREo9UhjWF63YVGB1vNoHQzJFNQi2s74hnMxp4aeUGW3A\nnhI/ztVR4LEwZ7XH7wwwmLntNjOp08e4L0SwqDu4k9wj2Mq4P87tHDh2OlNiLNBP9KNGLRKuh6L7\nrvsNzCz5uZW5s7nBY60UupCfWM5iYb05yX1fiPvYksz5uEon77IwhleTgsDLGSjDpO/3MsRecpOY\n6zxdY0uNkfRy/e+huHZvIRI9Tgx9p4p5MHkKiVX5pzmTHVFHILH/8jpxbyunuxTvGsgkRSrn/BzR\nCr6wvT7hHeY/W1F7h1vfxGVI4Ek5baJkO9T+vg==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64336)\n`pragma protect data_block\nkE3zh5FB1r3vI8ZJiCJ6FWF+XzfFQVQgnzQJ/PJpjvgCXoAs4Zjsl6nmvDpPHpRl1X32r55UNGOi\nrzvS7eJCMJeieiUb8KcN1+k9krnT6S4qk6dWAtm57amEO8+SlPVtgy1tkIGJYbb8LomTrg6JKf1q\nmpnSuP6AyfZHl1hcXlpc6bd4uJId9F/xcZnJaMEQTk2Xkh0YZwzFzeJiYXNXkaANr2sFv7jst1E1\nwJT0/zDSlQMmJHtvHYgqniLGO0LTUERIJn2n3LlE+Nb1n6im8tMfUK9/omKdJrvVZAmHwm6y1KfX\nSR5hA5hizsxzuEmVhhICN34dve/ajVFv00CqzpxQcnSBCirgk/Od85aRxbLRw7wKTDQVTqkGC5vk\n8B71OWlKiZ/nHzlwZ9hkKlT5HkYDPZN426UwuQXkSdSoit7sDolGhTt4BUWi4BL1gUE1DZ/7H+Pc\nOIDFwGjTInrdA+MN85INFgXppeRHIfUeeJV6PNisW2AElJtcXF97zM77KR0g2IiTqapwRFlRAMpQ\ndmybCFy78g+H+cfr3d76Eo7sgOSPiULbuDnW5OocD16sTNjQBvfOBZ1a8fcYC0eVM/MPfFqAJMX8\nhzpp+YLA1YWJ8/mAVQhlhjc4KKcIn0RiMbw1LSTX142bdXJMBujGVnYH2QwtVCJwtuERXFtiBcHK\nU7EKh6EAIU9yCp58uJMNIub6tmkKj3b3pO5oAxbD2T1vOSfaQzg0TsmrVL6y+n+rXPnEyvrgMtw7\nDlQ8o1tq4vjKbXAMiP3VHX9luvJQB5yRoanW10HoSFcPyGhuyvBscFIWTC+BEA3hNGyk5czChKPF\n+vMFqE5wtBfiuGKEi4YBS4B6ZwpMPspnZwYf2NHSNQqfLSp1Y8r9RY/RbhF3Hc9AAXs29XP2YY2R\nDt8z15QRDaBBCVYRckMMTmGpOJ26zR/MWF3F5a9Qf5IghfFoimkitsN8O4mGDH1avgkPNpfc/5oq\nrh8goxqhDyYi9r6oAZxul3ymzQaklgK8XVa9W2wYLPQ5HVUIzH+fx7yOryc/b0XpcAYDhsiA55uW\nxPOsFmqwrzhGoEM6/sPeESOzKxGqAuWArX1dYw3B1NIRwc/SiICNy0gVTvq67BOMMfU2jEfH1zss\n907/tTkECdjUTaTA+D9QGzdlwAnxMLZS/5Jp7CaJduYxlS3SjEgCALpp8pO3FrG3dvCbzob3X6l/\nHywXPt6zQeozZUD9te+GbwL4nVBJQoDFFiKpciE0aFKU2H6IF0YZ9bQKJKYkBkYI6Lg68EPLAPfi\nHgpWSGcq0sr03CFqAvZIennPxsmwghVPPQBDInhSRM7ogh6JVSa3wYiW90Im3BjhIeZuTVwWoejY\nZtDwCn1vqNjdVK1h0k+6sZkoAJx/tKymMzQ79DNfKptG48yUmhC/F7A6bL9CZ4J0xKpJAT+0rmtd\nwEym2mskpzCcOGgRltbipx2L0w5kmRXMdyjEta4eXyFEMAzsWznDHXMv2vq5XwM0savwMfuWTyY4\nXXPdS5QFO94+jhMoG9DQ1+S+LR69rqNM/jCH6/Zgk9+GUebipjHT3BHiNgq3pjhrhoBCNVW+k8Ra\nikrBqwm62uE0Kvj7UIagh8ZVrswAyXSLIof3/bVQAJhZmB3055LH2U/4a+fEsD4mlboFaa6zet2t\nAhSATWM5T2Rxo27bt59Gb3ZUMBPTojqEfgvWWMBvawl1GlesvaxdtH3t7LjvwoXN9tdEdhdIoXW7\ncnPRYqV9hD+jSj/wDAHBKCAqn/06LxSxEo1v06AkDTali2Ibu/LpGRg+v42BQSTALzWzxmp9OZ+G\nQBOmW0FWoBr3Np7cOgqb1y5OI+hODFfRwREojfbzTDLy7ZR3RTOCEdwJ83BGogbKuZHCe4F8fVy/\nEzUHRrXI9Glt4cEZiFsJDXxf8DrBbMCe47ZO/4Vb8CQwK0Zp1ur0bGW6eZJLvm2CZDenu+smqHyM\n8cNa+X5ZWUSZdAky0ggxJvYzGj1NLWRkA3m+yU+dKGGtlf/ZyyKW8UFiemUtcK14bXza4wz86bh6\nbsEzG2TRvNc6sbZMVnkxLHYnx/xPQrWFNhKNcb16XcXCaB6WFYv+E6+GM/mR8raMgI0K1rSj7Cni\nWyKsBmpgxTKkNy540JxNPM1vmm48rjCWehZwR/BFn/eNpQZlRe261hIosBDqnVgUvGphdsrJk2tP\nuvtY6UHx4FoZy42AjlxAG9fTbwMZP/GKLN2Wn+uc6iDBnGswOQTOQl0glpbfKEJnkxuscJBlzVXK\nbIAc516dj2fAc4P8qSHMIIMMmrRtKlyoKbGUpuCdDAGCwNiB8e2ZkD3Z18aQUYjYXrudHUOsg5jn\nIoIQN89ZyPNR6r6l7HM3EmnD2I7C4nxEzYwSOaIKPYClX6pE2lH4j3BfWEH6sEd/Ff/H2P8j3/jW\nIbBz30hNDupx7kOjNavnbibhcWayZ8dsA9bmGHm0bVu6SOuXd5uKev9QnYaVITu/jLI61Wkmpcsp\nYHhaVaSFaRUStXZIcYv3VNPkuxE2az0Z9VNN0Mi73rrXGMw4pp9YL65ByzJgP3fG97U38ltLHgKS\nn5Itl199gb7ZMl0lsAh83uPfA4iGuOv2sBn7g3pyREGWaEYieHfHKq+ju38etYApkb22FnsjfVD2\ni/YIM15a0/JUEGc64KHZASi8A4NiUntFmVDG7YkPNdOXQ5BqsqprUqtMd/b17Bm0nkxc8e426Me6\nUbOlAHlZce+4uAmZvy+E4ghu6RTfGS1y2gVO/RFbNEKDLQmvXGS0//UZVhj+TNSiInw25dxsDuCV\n6utZNSIb92gOGTuKghxb07yu8yXyZy9A4biLLqaVQU0vb/PW4EP049J7YYdO9sQwrJCoeFtVEaPf\nwo2nIVX6hOpH1aFEkrg9ERiPnt1UUXlgrQTkKdlkJvC5wQSP2ZNIRveY6jHSw1gVBWkr9k0daovZ\nz0G04BIfsbm+NtmkVJ7OoDEv4XuZ4Il00Ap9vBN8bSHNO/PsMj2JNKVH3v/Xx8eisuCdeN4Hu3Xs\nzsUtx0nJQggOIjEbi1WrdnD95V5yipfY1V/ZC5V7ii5zHDUDkP+p14NMbuE9sjfsL51Rfoty0wsl\n+MoLxpOr4NcXnX7QOWmy4aGdL8C3ZikuPP00WhtKRG4p6H6MkrAttXHz6L5wCnUV4O2kGfhkhYjf\n3yQJVii52aRvT7Lv6S/BAOJFByUGl4wpHoyfLS8dLrarEOyI1mnoeOsjefSUTMceLOKuPWkMk0I+\nLR/T838qusGpX/26srrf80SWxKr7ch0YEK9xGGHAO7cgvPQTlncT37QvLwfutO2xOZT+81H22NiZ\n13z31W0LurQciFfxyNz3bOQeKWnQHIqtFv3JGGJnux7/cOP614w/LW/aL7/YOzC8F0xM3YhaMeUW\n9UA+GBxyn9FtuQ0/g8hs0RhuccMBjsnxQzSBS603FlXaUQV2FfsfMLBL7TasPZ4rIHuUWTEu9mYL\nfWz2rZbpwwfRq35JbtQKwphJScZVbTaLWyH2Isjcm3GRFrOK9OpEZwYx/HTc9n/EtRmmZFwdUe4J\nlDnueKc/fDmoU4G3+Zw6rm3p3XTOo9DXUArS/uSnCylnmGrAaBLaKnFsQKd8kCmJX12Uj/xdyOF9\nOpIg19vrcrSE0ejJQ5dUcLrb3i0Rk8eLyGew8jmMMtFOBRmqVwscepGRMPG03RMp4W3rEJn8UXb1\neP5XFWhrxazaFOY5ljiIWHk9hYQOnH/Vt8DG01HUbQNcvQH1xHNwUIooc0fbM+PgxMn2hQ0pM6+c\n0wPfDIKABiNmKLhcHnljST+ofM0yPaynaEkePqVxWiKlmFSgAsBtBcerrFImky4wOHdJwOLvldx3\n4dVj6HduJgYtLUQGVl0tI3IbmvX6s0MKeONdhJKp69hWLHhEiYl/t1cPpLJB+SUFp/r1x1s+MzD+\ncKZW7hNtDThOdBJjoeAKmavGBoh4VHBtQqDP0lL+EwpSg25V6X9XW+dFUEpwaZ0CuVXWHBtwGuce\nMaku0HU9yyOJSHRk7R5AzoBM0QCbfNIwoEqrpTgUW78VzRjekms34MQvc6/VWtqoA6IIgPs8ybLJ\n1pXEw/utkcwR/tMBVJvyKzEp9b6Dc0sotuhEJRY553G31bb6xa7Y7PG38YByPiqfJPK4AuPhcaO4\nN8WILCcgXuWL93xjqu0/Ew6z+GNqQm3Jz4ntiHysc/AluO6K7vtwO4UcS8ccMt5z4bpA4T5arE4/\nb1eHDWK6JT2gX5/4lOlR7pJLy5qwKyffyaH/Nqz7AsCVsPZi3Qwvygy7NndJ5ubyVcHxyItssjGq\nDNBwkJOOVIQtsmfxXko9LsA2I6zOgj51rqOlqXg2Gk7DDJjUk66K8JUFHjHbyUHJoAgAJXbcvFfs\njDDBZ6zps82PHgzQSOWlueInlKXLUvswdqg8Szm9Rmfe07P0jivX7y1UdWGu42d2G9+SbnpVwkAY\nd1j6kvNq/oN/n3VLX3UuBoSfGik63mKL3qmADCS+UFhJpi4xHFbwZh7pqoTDSA81OoplAD6RtIk2\nxTHfTfakM+NDXKgW5LVuaFtBz+6XsG5LuuVK324YlMwuHsdtjt6EchzSz/yYaMPHCFdNxyRgcbqD\nSIm/1x9m9ypB7i8tHeuJrv5TiGMrS9fK/EjFDH9s0XHcvfmBsVMUNdJPggy2rEwjwRnqEXo66at/\nAfc7We4AA8PDP1d76rGrBczWskspbNfVGtzLYmsuK1aMAzAGE2VnjMJ/OJqy2qkF5qntyuXtWXp1\nXYYHmfMdE0HqigV/1OZ1p6fodgR3cMw7dqDD4xSvY3zej5zcUNWAw6yrxJEPGUhaUjPtNS7+r2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fRoNqOEwbphWrnFxpR1uQtlznt7NunmA/HAq9QD0jc3VCyUGLK1m9jzfR+MiOxGkvi40fGIh\no5q6cp6WZYQE5sG2u1HePNz260XW98o1SKmGAnVADmN9oRH+kJs27wjueapaewwDVg8pnq6kJUOh\njQd0RkYcTMItDGvp+sFqeIIdADsTHRvr1h+M+pYqq9sLbwUoz1Alak51hZNlSXhSEVXzQLkppmeO\ntB13Z6wglCy2BICINwlSr/7HP1cYop92mfeTXL3QGuFjsDOYJeT9Igcq+fS6YIfWCA08MY5r7yVk\nVPB84f/igRg5ddrxoxTIiw6w7GWDOhG+zTxF1zyp5jJA3yKcpqPzSQpf9MKcNt+PzeKm+wneK6Jo\nhpoN/97lq7oMjwcqj4fYDI3pT7J8WHKkZCIdUVNrv0PtjsuMpkuTQbOr8hbWLJNy8UKFlgHOcfrj\nOvGAARiIQRbgB0ehYmzYwrLOYCEEGz6BajWpYh+QjcQz68HI9uD0KJTeFrxECsQhCkd+nhXmR6Fd\nTuqTwMlfvUxKMpfl+zweX6F5NmHmeyPDY7Z3diHFdJVtYNhc+jcelDo1qmERGZj0HjhlAXvpn27V\nveZu3AVSpka5ElIwtvHc/TpRzjvbeQHF5yFv9E3VhZftw6+ajD4mjDYjGCqQeNasu/oomGN+bD06\nLx4hi4Wsc5ABDp9+84vB9wTN4vdXWfDxjG6e8iiMfWuezpQtLWJtxG2XnhaF3oXBpRIS2VVSE3h9\nz+2gpVoEZT3vzJjOS8nL57iPKloZn6rbf5gWqxxUAtYbGct7VUgqevGHgWDGl0dAqT8VpJaQ21q6\nFkr/uOy+vbpdI3AICEPSgGKQQMnk1kAfWxfgJ/kaxhZc4f5XlC0ZGSh+C2CWzhNE/JAksw0YQmsi\nne+rOYuBn6qvg4VY/SXyC6jNTUu4fEhiqCBJKvOpstSpQS2jYVyQK6GIEoOtvRL+AeqOwN4ylvak\nQVkg+2A6cwY7T1x3wkcNeZMXbEpORaOJMy9wXl09aJXky2uN9qgpXHXgPTZNWf+saMNRN+uBGVzs\nZjhjfEYYTVSnY0pqS+gpfbtlNOxXo7TL8OvbkRAThNpVfqwQtupoPNk2HHNbdmWP1tZGcqPsQf6c\nCPJwuj8fcPCQUh1HIZMnT9DYnr+Z1+9YVL/Rz7jLHyA2rFlsPXsEC9hUanPqMe7CAAEbjTq0PKon\n6vcDhC4OeDhfHkwfTiOS9fxMjBLTcaoTqPWTZt8ChH4gnVvPWfUBK7kvIhw+dKvaxIvX9bk/BH/Y\nB6uSJzU7imXZJLx07cEcU/6LrWAx6BrPF2/b6Su1t6eCb+t1Q3QZIS/1RXup1A8KEnaMO28WsZcw\nZQ5vCfX86ljiIl+HfGiLBpKoa7+SdP/+q0BolGpFDPCce56LZLDSOjBraFCS81FH07TgMpEW/Koe\n73WJ43JWWkZBQNZzN+JlfWtwo4qAocwsQJX0w6MOAIE+RO9Iwh1IPv1zbtcWHBpWy1yK1K+qVbiT\nkI8txebAMYWE1fJJdK/cP/tTZXiQLhiPzBsl9ezZjJsjAPcq3dbWErzH6ZEEnAKTv6PShy3Znw3q\nOT6++Nsz6N/njj6GqwN1E2zfnMNA9tFHXPkjpOfSbyTnzGEEZwPile3fiO38kzzHEjoAkb37KavT\no8WtZsohsnfTezPzzWxB9cFMtrTKv+u3cIIlr3mM8PZGdN2ZSq9ahQfTqRYp5KGtKnkkBIfsbqqM\n6M/SBVm5RMtrKRYp3/ey+lutDPtoUKLWJMnsv76her8S4uek1nzv4wTizdqJoCHy04vb5HAcgpVC\nfcWHgEVDqREje1ZKN9cggmiVpXRsjmWDBU/wAg8c14gohHPFlXNZgAA+ytO9js8szFDnt/0cCj7Z\nkDd0C21SAR1LHBI9KUf497LL8Tu6L6XEd7Tm3XEXeAS5OgHmGdAHyGPiqI9u8ClEt6BkfXamciI6\nlfeQj+z1nCxMPEJCjjzMwvV+3Ah7f/pMVMzaycr537MfD4P9+Ch+Y0vIsYpwt4zU/30BNXnQqfs7\n67i6Wfe/ptu3NRiQFhoPNGZytUbv/evSNDXxFaqwfruUEUqn0eUopvcwacq1XD9XaRIAXBGNpSoS\nKKesrN7Q6LZ+PG/cPTdT84w/+X0t954GdIewb65IP9dwf17eYtg2FQZyM5t0f3iNHe0pojKIaM1a\nmcTIJ8FIFYHoORq8DSEu6tyA3X53jjGyQRjVmLNIZdZSbRVoyoBsiZ36Zh4U4aW+U1leOK18co4C\nxLB2Om7MWuPJT3VKJMuG8psZ0iW9z0Zxrl1RyfZ9Lk3hYM0VRdpLKgxqEDiEeCVqfhlGlFXUj3wu\nacVLRH6dhSEBumjFuWq/lHbTsYfS2PGWkPdKedT/skbFeOsHLU4V1O84M8q9+qmppce19MSMwXeO\nQ2jn8v1qDqQoaq9r7Jvksqp/+A8wClhvUJmaqnTcDX+MLOJSbHG2ZNR/3PvUYpDVUrL6FwJJEASQ\nPfeLTPm7SGxsfS/ZVEf5pC70NwkE/6UEcyIx7xiVjxXhDxpA1pBvp9PRueOVwllHhE6dRkC/iGjc\nY8YKShjZxisO3URdOWXpt8F8PTMjnWoGzvbX4aIve+X5KKntuaYeQxKXCf8OJaSDgRc27KSBsG77\nFYG6/6BcH6AAXrtXc/OMZ5Hu9pwGsV20Zxo2xAGLOFRpmnHdImjGCwHmcTrhQpQH8Br0AYr8Dchr\nzb/JJoGRA3WukUlj+NanwbgVkpDoHAJD1a4ftoDvHJVleoDf867gupHQThJhVF6z8LcDtafpRVrE\nSHNxS9sSGI31+aTuQ/0YqhEiBI0k38xXFesQY1mW/zireb4cohUmw/0Nx4uTsUCRUE3WLfpwBeb4\nMp8qasvOM4Uf9kQqF+GnmseyoR8jF+xEaBjyzrsJ7WpU6EQqH7Cs2y+0nkw7vULcWZ7PtxCkTi+y\nl+KY1Ss3um8ryMQYGvKj7L2/zAzwrarkjBW4JAtWsM1SrwqZe6veUIqe3Z4G6jiNsQ4NTDb8oypf\nuYa8F3nzw3hTgsLTGVQU9pMPE08BjCvQKFqc57jBAj6RXHMnE3TWWc73XS/zYTiQ/OmvpnxjZ8lu\nvX+/r/dA5KdxINswaLmFPw3KzzuWJBz/nVwLRbAGp9IHQYa6bgjjJRm5ZmLKGmzzyuRrQXUPKOTn\ncopnuL/JvlWnSdn90TMc2Tzzm7TXaIcgX9EDepTRW4sN2XWdc4AmncQYlE3Pc3mjMKKgB95f5TEm\nSgoHGZwRKlzoBLvmO6GOz1aatdeR50BMPUt7pSJwIgfBdLnvzstov1W42zn7AgW7Su/pfCewVOQc\ntZ3KuOMYDHtAQmPMuM620hdwLoXkyIatvRSwpr0SFvGi6O8B6kQ+5QxGad7VgcpGZArl8TiH6QY8\nUrI26KJkzhP9OikTZ6om4ZAs0bloMAPotwByB7KXegEUUn/G7uE2JTlScgVp8fNt08IHyAO9ubEL\ndk6s6Dfr0H5HdXOKdMAGD3C2jl0fudKu4zYcx0s+KraQSQgLXI1G2qoLzPeW4fGtztn4k6iTlSBg\nRGAbX+gnK/iuGfb+++nrxTBI8qFUX6YIlcOAkg//OSKGJJjat28UHn7BITZnedR7Lf2K2lu2q4yM\nUFzK+WcQU2KYHp8iy1VQ7x84oZsD1hpSPIvo8xCeiXIPtrxEHjRh9OZp7jAHNkZxhB53ii81SHB/\njEzrBHa4MLE/6WMisOhbmjPDUtQLtgnO86q7gzdmJX0C1jvl0VzQx+0ISJcZc1limXckLBS3F+rI\nMi8MGBfMyw+BygdEr2f6yRlYvJdRZJhXOXmHT77UlUuCfmArP6UIswPKplZN7Q+XLflYU+I7OUPp\n3qMXyzrC5ko38DucoiwqvsXMSMVx3U4vLK9VKA3sPt/QP1E0S7tFJB6lDoYQbdTI/vUgNy3iAmmw\nLl5BmdtFBDWdwEMFan9pvoDEbzNfFkIUBGuzvnjKtAFBwA67RYWKtqglvto8q74Btd/PMxWugAs2\nRDrpHJWYNh1j5vrsdRj6sRpJRMQ9FpQRBFbz8fol8FWWJFG0S8M+zbG317tUs/p0GjHB+hTwItqR\nv15KlK1LZfgIy6o7gd1a/8MIRTXjAVUuVviJ68d44vkkJr3mh1OphI4SBhUhzOaf+44CoHK2dorL\n9MyTI6q2dacNJIgHdhaJF+ebOKOMQ0olKCeLvE1KmN4SbPr9dHBv/d7cupOKbz1XYMcK66m5e/El\nRWsYMbQf2uawzWEs8cZBm585waVMQtfAQNoE7/Rs2/2SY+vnUPguioY+EDwZsTxfJWkI8zHk2a9+\nrJrYuXiNAW4sd3i5EDq/+2Ak2GPpRmfpxb7u6NIBKlwXugW8ktrqwlNqYCtg5vVaseU+FGNiVsvF\nFIuNWu1U7GpZ8HtnZu6aFs7IBPIoYMl7vu3aDQpZG9I7sSkjhPjg7s+ijQIJ3BGlmyuljXClWhZL\nJIDVQLnzS1pM0pvibM+4youBOCPFCx3sFuvQJZk3DpKOy2HX8XmKOtbKgZHL2FBjFFosaGOqcL05\nIgcxAvuqHB/0PhosWC4fcQy9X0ohWgMLrtpWE8mEqH+l/idgHAn3azKZjNDZTlrOZEPh5Y71cZak\npKgDUjLW4WthFcIERr+HL9L9PI43LQ0EKDsQTa6UW3qJFAXgUMTYgZtO2S8RQB23wPZI6bncN69z\ncEU5z6OZdFP2CgLvdInA1tFbRhPanE7dmxgxqPwFREzFyPLMwVsw9YgzsxSxbhJODZvVY1Bp6C4e\nf8VmwXIAZt+OfsTInDC+dttMHHHCvtu8TBUbI+ZLgsD0HzsESIpV/BFvQsRAJyfHJ1Qu2kByntgu\nauKads6lHHGN1Tz23/hFq7PVfLwm2Rv+/yx5DUv8Uj7PLsaHqrCdZkVzr0ECfIwPFt7nW50xCqQK\nxMu8QoV4cuZFAJzIhqj5t05ByOQPFRcxOQEfZrShvvNR9GdpYtghDBF0fU7BDHiagP5xDQ+UrHtz\nka7nRo1FHnm5QoYRJoEBABCLmeYI2KoWtLqx/CHi30vFLoru7CkCPX2Ll5A5mIHnjWmu/VKJrgNa\ntThK/it4atG3Inp2n1vlkQJQNib7fEUdfuFjiiCQRuNtmJX+MqELiPQnVEY9VWHNKjBPREYUQKnP\nJkfsG+QfkgAOqxHLM6oCfy2FFrS9aHOTMK/+PdNJLxa769Vi1zeXV0kwzsjTsJp6LwEAdQ4xKPck\n5bRahBrDgSJfUTcQYR+fbWtE8OdbPM/FWuaIc9SEfNMEebsH/lUKGSB86OWHZNz4CMk5ebH3R5JV\n6DdoBjfP4Atab/RbwcQqnZG0UdOPbBy2c7wTzqK1i+/C1l3+nDVheGhizstvKZZdm6XehGdOgf90\nOPsGrNckYz2jn61FOH0PY9mFh1FLr+59tTVOFZ8+6G/JJcGGo8HJhb6b5sCjXHSsT78/4ldD51uE\nJDiwF+PKeYLd+bhW7XjkVvG7+LYAG5h34M4tD8XHnDUKzWkpzBJ97ZFr8lV/euLpwJ/XlVImBXwp\nwZCzDdGwiTrZC+ogqcsGqoZxLQ0lv7VhpBL8skkTAYlBc2XQufABCHG+gWEuy3TJvqodDuGo0iZz\nQzftJFbueGn7t2+s/eYkOYS6arOhlDNJX2nYR5xtrB1FbV8m+jaHEiJbQc7h1G4HB07HukZZp/9P\nLFvsRYJ6uqex6hCbbqMMHQGrId6QGSH6/q5SVMSgN2/gJFrr5scKkIFUDU79QyiUDCNwsC5hwA/Q\n52vnU3pPU6vXy2f5Q7ZwUWdsJFEI6O0jxqL+Ga7+MIwsqnVb4GlFZdjTH+jRLEyw039RgVDhgKFx\nliWSLpSVpJs1r/645DGyzIbsFE6cPjg38+CcoAWYla+Gp7OtVF5Aqtp7iC2fGffTn7TvJOPCsVjY\n5MHx5QGSiT/mOGO5OVGVbXQzgTu/3GVWMajEmAq7T3+Ddw+yw94k9rT6IDk1t3lnruZSEJTPTyok\nw+bsJPG7RO6DcD66Igd1WzLO5JiNwENjJVrvbbBMYTJCgVPc3hJvvFQvfkLiuZsa03mylgBXKHAX\ng1TT+hvmb6ZTIuNi6x63/487ZXtXCLFNhUfNlssg6Z7KCyDb+mOiA/8aaC12vb51w7SWXNrmZCWd\n7wJVMUngtcinyUXoTuPe67Tbwu7Y3zQ3ZBvKMzu/YFyR0SsSeD+/yJ1siLMoqudSse4aThJOdPbm\n/YEW/tF7aovwdtXP+40gIRqfPjqUfFDJzhIh5XTJx+5XI6b1ZNJdT1+zC9ZCv0wpUCNzcYDWP2v2\n+73X+DI2B9Hk+GQUz/uV+HUBxDiALLNqS2pBnu03BRN2K3Ae6udAdykdB3XrMGU3apddVfl2Qzxp\nIMqedE5qxJzRw+S8ghl7CQ/HLPmeR4VLqSCR+4vWCWIw/nWGOStxbAxslLYMvqSQqcOh9SyzCdy4\ns+S2RDRsuoiRadrTnFE9DK9AV7YVbx1TL/4UsryqKTyD6TZgb3LhhYOUcpIpv4eGF6c886m7YxCy\n2UDtdlk5mzEa450taWmN0KN6rx09qVH7bTyCrbrVUDBIPLqFlGt6zsHsfsvCJAI3c9lNyy/K4Csx\nnVy11QZ2mZmv5FNhUpC9/LR77nEsEfKmmY+ZvmK6ZHudJHG1/VfBI8FoBMT/fDIUDwW+BhOel/Mr\nViAUiihouIkWJnuBu1qd0eyhHAEwYLpl67lU9OZtC+Hw4nRKD7xL4yeaFxYMdBRfHT536DpZkC91\nDyLn1w51UXVeDMGmEk5w/suYHhiKKlsSF4c+HVkT4yWcG6HjE+nqeKji/CAw5c+5piMrQDdaQcJW\n3nb0iIj0gXRBN+Eotil3B7bIpwe2t+faDTQec05jrigHMr3ZgWGPMkTWRs4Qir553sMKABMSYkcR\nnG1bX1HCd5Umeid7Ko9w+QAO4nPsP5d0GRtDcIyTVJxEMoOOJPe6s5d3iX9a55AGR4JeQOBinV5c\nvQTaqc7NHTeR4spVOyNLX0Vt4r4xYeQPAv/7STKb3KraVueUbYH++IptBnYURSH+JYRUgLc3wOAY\nvaIiWiWgsMJN4S9Tj57MZ21MxkcOD4n+daasVl9bXICg5bV/qCKv8GLgLa75Lmkb/q5ZMWqIh9oE\nBXG7qwnhfQdr1GBfNX5e2CHlpmAsJSuPYxfplnTe9x7rmzk1saELs+J5Zod3BW8s9PqEOytiKyFp\nNgIyYxnpDHg3KfkpBCzAqsNwFrRhkG0cNj6GW0rXcjnK5XVsm5EJsIpUIuwUUCM9FS4M4tQvHqzr\n1S0Rwfa/ZmOL+3kwiLwUF5yWFKNs9N2uwmJT5wYI/8PK/4X7jfYBxLNFiM1d7/Ot/0CD2Ygqno20\nGjj8idQj+8zcvopFkqmlICXcCSsY1CN8ytSbrd2KnMUs733/3JrtKjQJchP9IvaMZn4C8GZRjQ6B\n2FQEh8t7rEVQECSOxQ4L5fKxi4VjvlFFV5om0bkmX9dxai9YM/IwxOrmiEVbScRlOGYie5dHSd5V\nk90VtMGSxisAx3kJM2aVn69wCxymu0VbpXmPT+80tJOSJSASfShtKF9vvaTCkQlfQzw6bL7yoPjh\nwEpRBVB8nS+srJxgzTpzxf6kWSrfKwaXXevwejax6otuoFF3YEUOCVQgG2aUWnXPnlQBNC9MPtAr\nmChzvfkMA49tIz4Ra/kpvwGya9myjGuIQ+DpHiMvJrcsopWNYHjXYldeCzHaIWvnSOHGMM7nBGD6\nboOM+PIpyOs0dw3ymADCy1T+tsTasU62qNcuquHRip5asAz3bozJHUulZhGOlVgRZUNdbA/meTnk\n/sjtLjzMLOoPyFtPJUmnUvTECUkmGukcIMhdEnWfA+OgOzrM61GTUK5bwGME8XNRsprWjCchp57f\nxii8cEiyhO9Nm1pmdrMnxiPCjIW2WSFsnp1BUNnQEWDbigo95ithoSdZejaydDJCNHQMVMB7BgbH\nJVUUva0f/ZGTwU3kz+FTzsT6PT+E2GNMZm6rzSz1Q3yNoH4OXUbJwQ/vRFtTpicFPDJoLzVZKQ8T\npYc5LFd897P0DLzZ8yT219GrhNpk8PgFDRC+bylWmXrFl+BbEfkaO9VEr+LIfaNoM8p0/YLHLo0l\nMrvk/FTzdn5XhFvxyS+Sky7a8fU9qLu5xKvwZGoA2MbCvP/9924WG5xmAmsvN7gJQ5JylMq+lFvT\n9vBEEkmXTi/zMkw0f9CycHzh0eBomR3kzWnpWRJ8aBj76yXKuWdrSZi8qbVdo8wh8eb5xoIV0ir3\nEqgdL7Zjn1IcBmqhcr3AfwkhQEaXeBA6hqImHgPIpyxviqMTA0xjkebO9YGuzZAUIa6uCCzR8XPj\nbYJjNkm+wZNwzr79+h2XV6wDs4JS8VDdZcAVCwvmjHY8WHHb0jZTF+cMbLcUDsGNXONUc06UzHa4\njGjOviVfcTwRaVwQs82CNgjt5OHwna+Fj+b2mGBEyENynvXGlAo4ECvuBzpI8LU+ABqJINwvANwS\n44b0GVEJNVekwlMSByybrdYq2Lca3a9BtZmGtoxI5vIDG8U8CGIe/HaNFpFIvuyGDgYAGr2eb2tc\nhbOnJu4LASxc2GdEl6I0f/Z0R7seDGa895BuyGGcT/HYktcCq70sTyk8r6H0klX8wc2w+1UT9sPp\n13PTlh3zLdvGFzKPfIx0Bovn0nIoViJ/W+tgIbtcCnPhaL4gh3QePzoLOGoIWzrZKrfXdQUkepGM\nnGqctZ3+0XpR/XS7seqRDlstOjCXkPam6oFji3lfLKqM8ABKgItNsWesmVaCeblTHDPu+zmR3Swj\n3XSa7hlf1r2EC1jqZ+oubGX9WZjOz1p0gsINsM9ZgUPOKlzt+VBwtUQGbtj29NqAdJ2m+hFTMnXL\nwnUTOLl4CkzQ/3PrqSxqEMLrVcMbDav1VqHyySeQ9SUXcPePCnXTp88Ns0q+RqrpL9STvlzfv43d\nQWoOfT+y5jzqBr99d34ltSn1jq5Mk5kfg331aVBVDGP8CPubrq/MjnUyQ2o2sw0VX2JfGMN2BjHw\nfFEQGRoV/qgnxP+Yg/hdQHYj+r8qrXledHrHiSIHvAPs4IQgUCb7GIaSaT8McI1pg/MxpBTzTrLO\nHedJ4drTUgQ0yZ/iYK1+QT4h4+42fAkQ1PTj0z825aLEk1E6e1O4mTyuokRi5lFL0i4Xo2nnJmcg\nY2HAeYmkS26cU2mggoFsRs/ZxkSkF1qMN7lvHplO+1XTHO0DVfLkBuhEnnqTZn8rhmPL7cnoZaUH\nZ+WcnLY2VJJpEsl14KAieVLy0ABlPd+RP5UZna1k+42P6i95rcEg3jt0xbOAbrd3GZ10GT4chHwX\nZCLWJjslyLcbPGL1XdWjgDMZ3dtfG0z3hucdHb6/ueD5YQwPMdQIir9TjhHok4WPalVXcz9OwrDv\nkkUDrWxC6S8tuOFRsk6jqShA+Nv1loaSF+IqNB9sfeSGW8EsyVZIuI1fnErGqbXf2i3DInx/KFau\nWTBKYaTk6krZM9fG1+OzTGuQ4ubpSMe6o30MtzdVl/db9M7hv27LYlU0miFi0OmEUVGOOZDK+gSW\nYVlr43tdFyGvXHSuVyUe8+IhswC9IOCUS+h418D19ZNCQT6af/VQDeVmfOTnnZpP6DOc5p+hPFvn\nn/ISPeLm5qeknJULbDWxnHSxTeKqsw6FsTlJo72ZuEd1zLdA0lJqNxSH7YKQEawd8S0tE50OyfKP\nJjTDQ09tW/9msny5f6YFRscHzIbThNRsbQX1saPn1Gu4rhrY5lijfWRBI18U06gYijFIC5rZDP01\nVBYwmOnQa+ODOGfcUiQmM5pZVc0/4xmoHedHdwn4afREXvUzDZpKM2ZwPhNdB/Bf1RFqcRr9sgEf\nIub20BMNkJYzK5VVtGRXanivzfdoCbqJo4V8P/5J/jpsiDuZrb6BRaaYsv6z0mpEcr4RDQLHVkHN\nuy/UCVRX4N5yYskMUYbh+yf9ItFGH9xiMcWEvuCIcyyyXxQdjN8M72SBJ7rSGqi/iT7lD6zS9rCt\nQ25SxFqFjyMFb3/PCyopcf+doCoAKth86socVbKc8wQxwpfsjnsmDg6VfStQW3j6HbTJRR6cBKWg\no4hq5QyH4OzFyrWlze3EVjvAIRNo80YsifUXn/YmjqXkqejTAMs5rvnQMXvCCx5iTbO8GIqe1ZIO\n6g9nf6cdH8rgKjU2irIjf8wuR6WdAKliC5HyFO8HHKQ+o6jDL3Gp3V28RPoZe/ggfrNdJXuljh2p\nxgmoX0sLC4F1b8ary0X9O5Uk4Rm6NbJpHEMhDyFLk1/DSblBMxjOyWf69ua/+JJBU1aCUg73Ef5C\nKAF+0i0bW7wQ+1F6T3OIrZADAm3G0/7kCMyEk/pFhEeiyRgxWwHJyu8Lq3uncIQ6F+BT7fiZp8Lb\nzeD7TYdel7zVmCJayJKdXAqYfe4tHf2ggNiRQtb6rW7zzuDWxC6j9MOehd+wYLkKuWxcheZiDDGY\nXoW8Dn3gDgb6qmAR+aoQ6SUd0NHC2KkR9FKyVg+bhUh+gryvAjrRb/wdpK17v8W0/2ConYAt5qvV\nSx9opD6CbxukzGkKByTs+VXu8lWI81F+WVfosuLsrM3FC7WwGAbBF9jP7DkjemdKvZgK9sQ7+E/w\nykL8i/agCWoq9h+u27h1mXU6LVJOUIupwTkiLc4gn+eMXDqL1Zs0XW4Ft6C5zRmojOAbLVdpcML9\ncO8kViI9Uir6g48iHpcD7UCRyJ9cYSxliNW/0Rb9paOHITEcA0vN+6M2stDiWjLaznLsiRPKqFdo\nrfGWs887UdLqjo8r5gfiIx3q6dJCU+McJNwPj2I3Jch/01qA1AnDeFImKz1P1Q3HCe1YUpwzVdVf\nPkhvqIK1pUei69jyfiI5P4YZY6+RsP2tTebP3EhStUcOU/D0JIBRQ3VQrJa7Jzg7XWISFhF95Ti7\n3z2sHCcTzbDUqq+3k6gp4LymdHgAeI7RRHTNZ1hM3gc+e2Uv7wdyHBjADM7L9XBxGBNcR4RN5X/O\nwHBTw2vsQLZ+ETCgA03rkxnuHqpDB0M1lN0U7rKFUSuPu3NDS4bkCedhAckj6irfUrxnUC0QgoTs\ntFKAHU4pGb6keU3Kg7myTPkUugg3IWlMW9CYcpswzcYlzxnplzkXmUsTb7yUni/FzJOxd2qE3yTt\nWQa9KaZrnpU1W5773WQ03FUrxVsCIZefTOPmIur8T7txGR8gnCqsv6QBEWRakWYYXlNDPF2o7A4r\ncVeo8ba3lyADQB+lGcry8YqZvA2wzuQ59Ct4i0KA9Mb2LF9KQ7bB1/9OTdfRZWE8PslluZPYlEzU\nGIiorzNfpWh8X4UZP3wT2l3N9GODYuwlA54ZzhLwHUMEGM/utYMeZ4VrLFEqJHjqnVqVqEm0obrN\nPZqP5mgXq3WGmC5pYfblJggRYFU1uHNmMHxPLzFUwLZgD7GeQfZGvj2C13G3y26TPQRTpuhDb35A\nvsAETZta7bv79C8GhKUuszAXdEQqSt1AoFC0iB1GHCSIayhEsCwyn0tZAjwF4K71go9RPoIkdhxL\nkDi3AoLRdpPebNp0ZkA9jEvHY5jXMLUERzVAQloyXoj2mtsRNxGVEfImCoMq2ZVf389ZlS6517uC\n4F4WcDbMyf0BmdD6i/dLuCSP+aCs2mm8HWSoppsZuy2SM+34/m/fZC3KiLWa61trhcRHNacVqLWM\nM1ySVSUKbL8qF/lX5NNiyWlQ/hIKgo5zbSVAjFIuGdhB47cwhr9qYQOyQP4KYaqkT8bOk0gV608H\n9Su7bdsKfB78LbLtQvLgcdNmpq12lLrtp9JGg/aWPRjjRaXmzfcImW6wBiDh0AY6WYpGq6NDGwpA\nhLfZGiij/5kgTLLcNTwUpioAt8QzoLhp2p84Ra3LcHOeoAkKE+yMQ4mK09MSzL3P8Ld3KD0QDPou\n1mkPSzbvEsAv4b6WlnAkHgE2C1liHlCCPEIbY9RLAAIFGGASnOKMf/JBTcFSO9khlVSyREctfL/+\n+2sm5V5I000OI6HLT4IQGxsyKIQvLst4SWJd8GdsMkxBNNQIYLCFd+M0FLfYVnhAzTiCmhTAdxgY\nRnLY7sYZmGyfqmehgJkb1ErB7sPfr8vyZ0Z0qTGm6pysX+dmnzDmfCExQjMKu2kaH/Jnkf/0K2QE\n0mcQe+kaAC78lUWAaER1hQxg/ftOI+igRhks1sWXY8MhssSIc7iGfYiaSX5yUYwzEYIHyeamk+D4\nBGZ+YPTRPzSmZn6JHsKxCpVHspJambLKzdn9L1iverJbe9RBJ67u0pDof6txNi6q6cx9UXuddpCI\nADEaNB0dJMRmsoCj/fzzaSGw17nmnS+BC3WaBGJJ0aCoAnc7XqxprYwTNjCwcfmnuTnz1ll4P6KP\nR+tCsMDxVPxLH/eOccJdv0WR697d04aU2f4TlS+gELkIjB7NOCRbsRGhdrgC41wGRaA+u+ADhUP7\nfgqEuPYH+Xlvsr5QZvd0mPJRtUhqeR2AuVxy+G+kreN/F08X6X8tMFL6Avnl939hF6Tg7+BCy/Kx\nsrsD7ivYDRBQnMEoH7qkapYrGwu2L/ehj7ukBgOh/3Ejp1E+c1s1tWHeKPFMNpF2yx01Jy+5AhDZ\nPSdTYZFa7GgCvLmaicDHdeUnz3cvuYB2rZDX7nVooQnhB8Rf+6UTzaLdWwGrNu6c81vDrNUZGidl\nQpQwK1Ec1ecQqUWRK/KRYcg6m1Ot+IeGKFnPa/63sxwZ9w5pVjXJPGPrKvbZa+Pia3+MyDaMUQhw\nBm7TiPETp8qNL5v2hc4ybZJ1/NoEc6gdnGO9J8VQT/rE0pdpllH9k8vOItKpkEd0jdM2GPJK7ZuN\ngT4VCNV6rhNPeauuN4NuXgK+v3g/K4wTktuiZM36cOktYWhuiMZu+ZjnMmX/A5QrpZY+t9Xt2bxy\nbHncUMvFL14jNC6856bBlk5GSJjHRntBzQZMCIPtVN/C7jb/kxC/Q7mQMrWGDUbmc86VpIqxeQJW\nzEbg6DHJt4qOKlU6bzOt8FHPe3nnL37FuSrsjXpMBPVMzU6CF7izUOh5UBzaFpu5fbh/g4VrqznQ\nSEQ5WlWoVXW4ZN/ojhEvPD67BMdowjFSWDwe9HlddgB5BC49PAYRBh+jjeP9WdnkJ6GMfTXpMvgJ\n26AvgS3NcETqckZHSEGXEL/OPVvIwi8nyhmM/7l2ITTs1PcfqQdiKkc+COW6I/hfYNUYQTh2Aifb\nDt5iI9OZplitDHVxotoP5baEwDpoUsYSWH4r+9DsqjnnDi7BzEOGahmcDVhlbI6rjq2uhPt+/p38\n+LkfOBeCYUg9lxYke403tx9nNLtpnFQ+qSkNG+pUBDWPYGdMnrduCCwJnxaR20CQJOegEZCtYDGD\n2Pz7oh3uP06B+ju74IrcowxofXDERrXjwd6aL2u1rgWhjNv/qvk3swUVmQ2VnYZVN2u1qvFFwOLo\n8xArvHTfDmfdrv+mnz6ewWhBNZHVrK6zR44f5wUhX3ohSyWzCmey+ygAmJrPygJtZw9dvtjXPfkP\nmq6gwA+UUZ2D/1HAOpktggmARU0cJShJJl/ZQbfEq82hZjpZo4tj2wQquzt3CtJJ1biCnMf7MQLu\nxD5o0THKOO7mjLvlVn1vM3tTUc4TgSqw79cpS2caat1pA6PVms/BbFd7QjoHad+W5Vxhj/3Wdva9\n+rbOmR2Hr8d3OazwSj7QDN+4RyMmE12o2q4Wn8ZIxoD3tJCCKuOhqSWPDKASZv/IkLTin6nfXule\nIs2eVAEvlNHa3yVruUydEwXXk81lM5Uw+tSdYhQuqPKwBTGysUzTYknJlqjnyiJoXPUd9YTrcDuh\nwFtFWGr8LHDBhe8GRsZMvaYVZ16IRpnWVDZXGMMXqJNZhBDZMowW7UiEdpYqEBpvKHYMG5ASHsOq\nH2eZFgW7h1wB2fWRp3zq+htPMYw1HPP+PNgsCtaRQubfV2+g8YN7JSdRuJVQRKB7HfbRlfal4MbO\nQob2YcOhWtM3Tkow+j+pMAfbns+amYldYEUnaKZZKXgICtzUe+8tc6c9xgVYa/sNKoIeW0nQBgNM\n4rCru5DDjI6BMNPTgpTdVNWaZG8SR5DzenlSrkXBFykWTQ4LjxfY9iSBnutE8jbzjzwPekKq0wC4\nGfTVpOKVUaTaZo5wkojWs42LwU+Fh2ieJ0FEh24ZgSmFkbiiKAU+zrc3dANLGSgsgvCfVs/nP9OU\nJ1hObUY9Wo98gIoZr3Gz0C18ojCwZEb/dDxvyJM56jypCZsl61dYEVTjoW4z8i9chA1Mzbxs9eCQ\nB/SAYWddeyQDiHx6tFAi0C5AhuE8RktZjQ2yt9UFiouVgJZ6wAl/my9J6gKj2Am8k7CzKhlfV9F/\nVXJXNDBDxuDiqSec9vv8heMTxQL2hvtaZRbS4Nm2UH6mj2L5VmngiqZpUahulzswui8rW1Y4Wnfs\nKRTh1jiCT3mA0NfnDcq01KTgR38nkQ32gdQ42NUQGHAie8oiq3p6WSea/2JzXYXpKZb+cH45ODro\ndyUi4j/yaktRND+QJjGGrC4CC8qT5iwirtXKo9X67CllayE6G25mEe9A+huiY0thk+QYib0Lmnk1\nc5S1eJxEg6Gq0HMfuOIW8ogQTs++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qvZJ+ZCMnS4whysx+BCN7ma6YkyIFNzyLTBKHcjS\nE4yr0tuw3kDPz5v78ORBOVhPwizhH/dYdZV6B4mpONFDbGpxkNkVK9fLeTarpzCabmO1Cn4BjkIp\niiT9kovJnycvCa/1N5GHTOyUxMQ7cIlR8GyuJ9G9vjXMwxgt/iu6Nhs8Xf3iefAXLo2vTG778wZG\niKCTTviNxG6RCk8eWCflhdYo1C27j+Rqirx/r19s5oysIyqAS+9JIvOVLIg8jHsKyFqJoA/bNCFW\n0Ygrq/HNoWa48zWRfKr+os8ajBpjXRLOUeJhAxUEyFZWwKTJX5nTylPs+PHtuQ1bmgj4YfnGYxvl\nKvPBm/3LmGttISWgPjv3bic5rgM/YbQJWlKrDbIbTkJM9dGIVqw26kNaoKEGhqo5MGof42C6lrXE\nqRv3QktEZnMKBxdGhro9rM+0/4QV+aqX1Mk8X2EShfFeGJrur3mnwzkou97INnrS+JcpT7To5jQU\n8Ig/dgCx60pkXDh9dcoI+//AXBmIMTNEgpsdZ6wXK8vuSIKnMPcr0ID+Ztxy3w8MRNBtswnCnLsp\nhBP2QoArHvrGmhDZjvRiFpzhslgdPyiMeHyaQCICXKOF55QZ6sa+C9DkTJugfp2EZQIga5LrSTc6\n3rppuK6lJ1j1+cYnKipG2R5TcJtZYEWShSakYrnc7XPyQej0Wmb8qjCXO+hZmkIwnMTyoiWGBcYM\n09bc7DVHXvI+nlwPUh2GB0OIBveYyuUVzALBfiNkLkfMZ4Rqt8xNNMrsmVGziDMhoQ6nUl57Io/e\nlClBb+8fioCu5h7vDGc2/iMQLvtjWVYutiTPp36vtvUG/FoMa5MrJ6s5MCEAqI85DRmzUcebGP4v\na/K9n6bF6KBPBtScqz8oZlfhCGDyFCldXyqteMR6RZyV1yKKAXiBunsqmukS0xXpk/0BUbHgCbDd\nWWxClazeNUXUabl4DDzfN82FipbyFe8ShlLA80QBEES3Qp/u2bRb2cx+nnqcV48ReQsr4Pi9H68u\nY4jtp/sti345Av+WI96CPNYanltsmSKatJe4mN4X04++5oxfI0B2IOB6ZrHLPPB4LAPKz8/FiqsA\nKrIeX7V6Rw3X6sqlox+6PvJcpK/xrO7wCPcz33aZT87UVbK+rFka1xcQL+8T0yUDvGoKsX+1SygW\nWOu5fA6jInKD1e6gct0HWVj85CMVGApFoaCYCY+wKsvxUnJpbYgdRUMDayFyYOcSvPcuWrlc30NT\nzHXrPRalxD56Ym6Q3gTiEtvwj8PegDnb7EtcZ0uwjK8OCt/U3HrmFEscrH8i1q6alcAPKtq9WK1B\n0nwlZSUaYz+DnXD+fdlzQl4B6DGP+z65+kJ23NNlQ3O4FBsE3CVPVS1jInQYFN1R/MZ/NDsNKcT2\n/9HOVf54MFx4y4KYpD12c6rt3mrL03cr0AqQpOjfGPOzxZAOsxsGx5pydhpitDOsT+YLpdDok65f\neaRNQOciBmskv3OvgyoedBPWUtssp4dZRWivjakHQ4nyzSB6LPBzdHKugKM7Hiagzp3TqwoBg03e\nocqaUwsmLbrrweIw/zClSv0Ybb4PA11ZEnYLUTtBEF5Nvzl7ygkiFthizCzrS7TZkkJYYB8ltUUs\nzcOKgYFoNkTomQdhNHo3sWyNjhqeCijCSV/5+PllquArtqQuzLrMaQkCdQ68163mfRWsbzKIUbuY\nLAM/FnMX8/HTvqZl8gSN1yOdYrn5yUM00CeA+ShEd2TiKPWygLaUZ2MTv1YbNQJTZJRT/XYKjJQ3\nPCmoXiiSpSvl1Xh8mrDaeqZI/CR5Xo+7ItoX/fwwHs9nhipM6AOPthpsCJGNSpl95Qd3V7BZ53FL\nDAc0aOuivhvZCafQo2FPwjV+wmeEEBvTX8fZ0KYdJ9juXbCU83XRxu37KZxX6UieHu5H9sDi3v7y\nlMOmlu+PZvNPh0YPNzUXb89xjhl/XkrP5GQB/Puv9O3TAheVV2l4vi/GbfC93y/h1eLsSzkIHVAq\nDQKexnt5GJrnKmPCE0z6exBRrNPLJRxivLXsgEfcNg40OJAxbtsiL57zWkswvcdymPifzKbue5b1\na+sAZQZNc0yCKa5H8zy5gqK2epyicY483zdRS/BDHGdi+H2zwcOinQEbWt1uv6iKjOin15tbfsvv\n7PidT58wPRvkJKx9xaeJApmPB0x/z/UQwCGQCSp2PriFN8Yqv3vrUlA2A97FbW8rAoNtU8l1PgPm\n67G92DFxvYzMsjrFLicOXoAq0jWkESzbR0DKPmaZKkIShNKFlJigWGDVNPpMox1bNvDMH5J7LPZ4\n1wWixDY/ZS16rUbmxHdvfir1t89trPgVxF4jXaQcsnokQwDLQjjj41WUeZR80CcrJ927rx+f7tHr\npWhF31kQEDHgBvQBT8/POvhWv4f/mAfNwYSWylKvRAH6+sPoo361/wxXsq2q8Tc5m36wCxhyKS9L\ng2Wgjd/tDIGqlKNVTMaROSrU8YX9sZDpIJp9sMvnO4p818XDslDKxx1yNDIG/WxWuS+1SajgzUpe\nihK4Q6cnKrw22SD76yZE7Q4vtl4EwPNAisrd1ooqjIpsbW62kz7zPQFK0I6otG0rwwZ5YidX8FCa\no5M3MgSB+gDNka6ulGapZFd0IpvK4uRo+QQMULNO7QIM29KsTg27G6vFaAOPAjJm9gt+1WYOE1XS\nnw9EOd13mvBVZ+t4t+TY7SwE8ThnyRJ1gZ2L7Sg//93GTdbdEDlFiPnIzARxJzBudVU+3QEXE/RH\nNCnfuh3DaThukZSnjIEG3hNae1YBonjqFdbQfd47oOPybmPm9X1U+mKxmuPF5OQ/GuNe8oxKnu5C\nWdufrxecSlWnGMusxb7gbzcFE7dDL/grNTD9vQ/JPVDYfXmsBbGUZm9unK3Vun0XjadGgvRH+rfy\nC65jgpDIrKeWZr+oQW6dRLHBuYKMAbwSJE3BoT55PXuOH/dL/QvfZN4kgnFmo1yI9wgh1SSvF0Xz\nHrdg1nZp0NStwjiZURc8+UtEyOO3lNFjC8djdRtJDYf44YQZjyDZQtd7jdIl+TXJD/GcWnzhynwN\nTGmG+RFMk81Hr42hNMuaghElfpVbtIJnJMYlvmxT72ptojCXy7hczYP5vFEW0g++4dz7DZyk0sNM\nUJimDy3CDpgimqEq+KtxF0vMeWWTt+pWI2pAwsd4GfxrDcn/8ApWymuXE2ev6QGhkHLWwvVP0jHX\nwQjnUKDfHwhhe5WrWbCdPHGiDLEZ0ad9baM8ZWRhoilq81aalMGswIzIEzluihzHoobJ/nwjm24+\n9Gr7OS80DeyNDBc0+dtxoCu7ro+OWvfxl7myvwwnvq+AfPzWUcPNnI0K6xgIVpngiSqcjaGVFudV\nQrunp8i+ykRRyNhN+sH7p1Z5bWV0RI++6WWCOO55zp3fINIipPizzRWzQaq4pS415l+BVYgFiF/y\neQPnEFN0XhL4MlRRZQ2C5cVkej4hQJoTFbXMCCGzCos+M/6WVnK0RgBYp1uK0hcpwPz5yEeRb5Zg\nYLbRBoqhm8M5Gc2PfSRW5LWeT1NVikspCC+zO0c+2XEcl74GBIM/Os7d2YPYnQIwphJ6tcGd6kJ/\n6zwtKae0LKo2p4X8J2/LXPKxhHToHjnZheRJN+Ws7bhWQb0awbS4RjoAgxQQ4Uq0atWMLjk0ui5J\nO6HXgVWzY+jzCoh6shHixW1+BvGwxUy/Iy+iUwU9AYeG5W9S4ZMOP0FKCDu/DhHOWn6AHJxhRDbJ\ngZsCnwtrzo1teetnUOZfEc2eqto9SeuZxuHeofUJRFiimCVDXSer9XnIc94XzK3r5aGLtlQdVqXE\nrXR58StHCXah+7I2Igw+8Yp918fUg5/ARHntXb2ToyiogzGS7wLlx0ZRPZ777PmBHNwDGr5D22uW\nEylrVhpmlgJfARtHEke46DXR+vcLzW1K1Z5GSyvnOQVOYaPE/VSF0chC1L8aXm8TykNWOsqqFHqa\nizB9aKBGwoBrzzLirm6b4zIbDOMD4bBsmTTVjn51LN57+7gUwWR0hF6KmUNuGDDJsPb12o5jdpC5\nhuzsXk/+le5CG90IcxAN1aL0w6s36e8xoDnShTDihHvu9Npu2hMrXXYIAc28kSLww2HdK5Yi3BgN\ne1zSyMky4ACs+RnGYvWHmP0lN59X/+mLcZRnObeYLRKpAzRrSNi72f7AU7LpdsxxQAQ6q6jKYEs+\nA5fhmyuUW3G+AaF52mpaRE1OJ+YKw/qLj4R7boI5jZ5P40Z1K1fVRCenPEFX6IEb2NcOlgNjLNCf\nfiMF5mYFGz0eamcRhM0RItlZkWNJe2Iakazklay7mW/V42pensipU39nBMx5fq8myPltRu6F3AH9\n+zWDsJpDTn4bTYZXpOwTmtNiSm9XnTZbviehgqe0OHUHFby+i0XtJmTqoqQHlJSEt7vJuZX643wx\nqEnZrxMcCR6p6psZwcxMv3qfVsMQtWp4UB4w5T1OGtxY5ACFqjDFli1CChYwcHDdP+LnMOWoJReb\nmrJPq1Yp98ZTUpmEAeIU9CCgfbLLa9oyCcHfVa6Lm2ZT33E/eeFer0L+PPV8hloIiWXjWvjIyKjx\nInZpJy47H011IlrofI5xNkU7Pun5+/cabxuuL6bFc7Di6dNJwwgrU/FBcutPz6mUQ9ATroMac7OG\nn8xMFAdWEXH05T4KcdPP1Yo4jKE77NYu1JOtTxbSKIciRZGFBKUXwkMfmkVSrio/6ZvPUSO1ATxm\nD8rndadTmvy5U4N4uwE0LDNlbzRBrQEpJQV8kX6Yi3njGLHUes0x6NIgE2ou0eMnsNiXggENmqbR\nXq/UGbY0yHLg5mnmEXQX2aJu2kj73Jqxnf1ie9QhkqxPTt9hDIcb5/xqpdnlQQCfdmXPz5BAHuMy\nyTpHpGLeAp7Q2VyDM+6T/k4QWVtnnQd4yR9oJFdO5c1caLTt5T+W1wBwgGhKtmqYsdb3dfnfuI7P\nnccUl9cC0cLt8jOVnbVVklyrsryIvWClOEhTSaOwmmsU7sQsFBPLDRswYednMSaz3Fr/ldTHIH/l\nRNf/5rPL/sepbycc1cnYhL4lMI8PuuF3TpikP5aV822eIq/itmBp5FeWOFTlsPpExv6FN1KtextJ\nlm8ikFNPEI/rvndxBE+5kqTA7Ut7SiK5OwIWlDxbFKX8GwaSkh6gxecLTN8/DjhU2R/uuTAZgWRY\nAHughyKHd4V4LKBLK/VNlu6xGLmu2RPpAlV5t32adrb9OdBS2BSqwHc34tYnzT8F5JnIiYqdjlX0\nCFtcql4nv5ea9dSEaTZm1TWJIl8yJanGq4vbxLknl/vgtBrCc9OF/ENyqUhEop4c45UYDpCLaAvO\nCDU+eJ9/5Q8DxVE9cht55IaKxVEhUAQjahx0UMIc9zzQWo36xPFw6efhpXmCPHzDgY3CirPIST9U\nZtJNO7hsvkRXUi6UF9k3SMoQHugIltuGT4oaN2ie8q4hWQAAFlHDbeNSIO/OzTZJFwRltUzW+eP2\nL6SjbIXFBbYeeGDutFw6WZHmhNTePMBDL/YWxwEDjtq1fD6ZOZYfWHxo5Sbrj5h3AKqAvjfooQdZ\nNXZ/UI5HRrK8LkB3d3OS7+8QedJy0l0hBuNdKW/9ZSV6v/aPaq73P5Hsxwub6HppOTdpuhc79mGQ\n/BL9pDmndVUjWyHcgyNkt+zcO9z6QD7PVAuNSZyCb2mI+Bff5GXfNbfpDPMpONpx7ky9z2+yr1dc\nXauIT4xqFGOXmBIPXbiJqIdb7ZHM9Gi3/k+4PBHgUknBatmkDJ5eecnrjZ26gwas6Oe5lVS5KLOg\nGqXTIVVFFpiYzK3ljzoiT0yeBqaJNI4pbjLfcboRyIF8VIWqoO2IfYdEhoC3o+i0Yl3keAXcLh+S\n/AXycHMCysu/X788u4qjRxfaxD0xjZGm9dunBZOgWm/yfFpUUIZE2ozu5nF8DUaEFp6vXVjSE7OC\n02fb7LzkwSuroCbayLt++NlPwDysNXHq0BbIC8BUW+7COg9Qq2NB2AUh03NHpEWm1uBZuBVXJxoI\naKTHQ3t6wWxYxXNg6z4TLgc170rTOlgGGp3YovVUcjXTRTHomEB78mYyHPLuCRrYEW2NQ4J0urgJ\nnzWCUwF0042xITA7DBxUAmoH41LK8eL/DYk2qg61L3MJAJUX3AAr98caLhagCUn01UX6enPIKQb5\nnWUVB56bgpQYcLifI2EwlpY7hK7HFeWXrHyhTZQnGd0p8gRSS8KuVRpyH7z0GeetQ/+myE/r3aOY\n9plLEK6QPf+vNoK30hqRzbsnu3cys/K1TggUEVmS4N2c7i7OcTTRe7S/VDkSc8ZgoQXnOpJVTsiN\n1v+5FUfsmi12db2BlUXAtUM9Iz+r/XxaciAzOgFgFHQfl+exQV34Ney9FwNtVJpwXFa0q4nIfts2\nekxTFNLzEAyhDYtgVffuOl4VnPF9BSHN6y508ESUrPdBJwXfHzV+jflurF1MCqX8G80p9xDud75a\nmnGZPak1w+6EfxPOhAgPm+NonRFVRM0ki3B3HZW5HKs0HGPiLl9Q3ZQP/fUlfHDCeKbvT0xWPKXU\nXXgxtu1ZNmEvyud/3jvhFDfmjh6AaCKi2XXMsh1BkT2a87E56X0VGZmscW8gdPzx2UvCqsOa67y6\nnIiWH+wTfx7jzcaZEY9tJhBxicXzVAkpbL7hh2Do2hGc83L4n+tKZ6IN2tq1FXxdUJmkVh2cLX2z\n/Jn1ixyJ9VdzWIdzkFKwLsA2QD7ns7QMs/dl8UMxO/RtjKahl4TZl8BTyQfFd3sQLIlQECEzfKX6\nJDKfd6WAXaTYDedLRVf4TCuwjx1rLab5XU4zhO8Q1Yku2qeKD+hth7Spsn+0i5ocMLoBSiCTpZ9h\nXn8ds3geBGqt2SPd4eyMefSzBIGx/Q00rnMIHHUVN3jQ2oxmAbAOTgsqd5GgrLdsLwRQrwpBZqsK\n3J6LAW5bFThJ8G66/rlxbFInnGCQ4yXlpbHslAgsDBcmk0nHvM9oG/RmlySbKcQ2zAlOxVrA2hGf\n+SWPpsoPahzsXFFJuAXtHzIM78ErCC2jCojJaoej3YR63BqdghIaE9nFiYcVBQmNBJCybtRZJT2N\nB2pPbfAVXCbVS9SFGQyAmmyOtB4sgXG4LYaMSgLYWttbh+Bq9gGUJaYRur19ZmwEqYUAWu4ACyAs\nHTjhc602LAuPwH9ZGwCO3EbfbFMT0AyaCqY0u6qW2OIOhNDjGVMooNmLyj2RZEuzlJcNNDOs9GYv\nKNrrEuZXcqkjZ5v0MjIkm8CXX9EpU/pslZMYmIYHuxUFOD4ZCC5htF4KHvR64VAfy8eJZnjElbQb\n+h9ZFi918azIWgSoWm5mPnDYXQUQhA37JFZMdLrBGVWd5J5zhrnOeweKYUsJOVz2UhrKIOZWpNV4\n1XboWeIC39bRJQh4+9g8KY8keLAK6avgMPrp9Y3+RV+gzucUzb8S14/b4UsFcVv0FLDeJr1qeYnn\n77ASlZSJ8MZZlEy5PH5iLp8xF4/Jcib7bXU0DgSOHqppPU01FWFAAFQ3pdS2vIaSH0ON07RDG9Qy\nDmlmF/n7ek/vZIjfOXU55wrDl0II6bocsUVBvIqMki5b5JqGzm28HY5AGgN+nNIEw+N1n4gzKNGR\ndOIN9g7gMcmFTls5wuBWvWHP8awlMGRvasNMXrgM1HkIis+Dm8TQAJ4eRFgDj9Iogn6wvT+qgShM\np1iCgj70yAabS6Ohq3JZtCernQSX13/S92WHEVe0YKTT0mH6HSdoodhQctB3XY4D0iiNZJpC8zqB\nHlnlP/RZft0zTU+v2hmkGePJb2ia/jfiGu20DZd6WM+8Q6cifUTUwureuHURzyZsx5zyUb9WAekK\nRW1xl21z+xTacEK2L8qi3EdLgEsZXUzhvr27O1QV+uIuL/V+/YLdwleK2RAqn5ROW42Y3Q56r/dV\ngawH4Wl0ANU6S2JwbGBais2O+2nLVwhLQriUcyYNXhuWc+7xPwsAyHw2R9M6vb3Kkdg4Wcfk21NJ\nMyVY6REt/UBtqkC/hYVNoE5n2qhGSpoRWVQQFCkbew8WzBWOZdyzmISJQDyy3b3BA237ujhb/uJR\nzRuzsGaaKnA/cog1unB1GU2VUljglPDy7n3Hesx5xosdn/gxURO79XFk5S/jzWaPBJuvpenaFFxr\nyESg/K2qR0dEvEDJihX+2a/GkpGghU+ZhezhnC/mapM0ykkmzBxUwUrSc/IMUWmpZCpVJrNLVYOF\nnJSPS3KIxdL1diiYh64ICDSHr9i7pqKueTjsEK67qlhAIYCk6xXck4I5C2kRjRThjv2EHQxOR5dX\nVe8XbzrBwIiyJvvCxm3g5+EPCt0b6EwYALvCH8WAZ91lCtTCFqomRB6/dUS23DP+Sx0y/QYdr15T\nRZTWH8LGyO1E1W08SYbUFZtMUnNPzcykFRMCYI1IUWLBJXMMPtiTWlyEltXCCL3kMn0AIwnYyFvJ\nn7SxCiA1qUsD7CWrhRpOU49dneEphwxJeNyz9bOUGxcuqUwJbnum1eH7rAtSANIQtNZaBQ2Ke6oJ\nlzJdhJE12MRV65B4Nsd2fZWUUTBQM2uXE1k3NQPO3xQ7bngSv1sJ5so2zKPo7iMSdH626ljtmqmQ\n4K6QlEtlWL0ryLMVOe8ywCbeCs0+KF6DlQTPjvaRIFgSf+/XUxGSNDAP67Ww6HJGJvhnJeA/bOtW\nkC1vPFANG0f0HbgdV/VGUIEMPfTvVWQI5mO8xP2mooXHRsBUytHDx6Xaqc/F56+ERQd3bsJ0U05A\nGY73sBTAXcfT80bail6td4LXnB6q0mGIcoRpavQcXpT/crKmwSJau6UOwwVeuKIBtvh72mAKOXFI\nD4jy7sk43ZbMnS+4o8p4lneUY8fHwRlAYDs1OFhi5nvGUjqRfrW4W7D6NjF/ao2Q+RWVwZYgPhmu\nc/QpJsPsoyTZyPYiSI6X5gQQRwgy6PujvtJR2cllkLm0y2X4BnRNbQthFy2DGmlXwV9jKpwHwCkQ\nNUudN5MZ7wkx/S9/gtj2iaAZzFSlyGE83QahJLMkTHh99PnViB1VScVdloR0E/9zj6HyijTBtz5c\nTvpFgdEm1VltojHW0yR3KPsfXBPNvV3qxZGcine3CYB38XNAoOpwQ+m9KiaMjpS+Z3g5jVSvEPRz\nI6Swyc2GHSslRqysHLDmqIFkPYMglv6rb3SP4MPqxcHdDQ42D2QUrIg5QGSsCFVKWYNzuMHNS7MG\n0q9S/CRSYZI6pd+BdxF7QMfYvTxG/z7SX1Y4He65yVsu0BUGxVAycgESC0yqDb/mPS5gu8ICCL/U\nKFYEMO8VavxBguJHpSOZqgfn9uQPdQKICYTyk3gkYwquOIgMeAzUERFY9rDolU/bFQBcrEE04bCl\nGbT1w4HHb2SwKQtCKUFOU/iz1/RQhSELBLKUUWiylPcK8ah60oQCSYEw5Fp/BmjNb6AtVYKSP5lu\n5OCzixPZqSYs/qpGhwGoFduI5ihI6wWRCEmtDWr4fn/VaQEIhnrCOaWyCB7dopkGrzthw/KTqugv\naPwLPvra19o4S7x9snvKUE38ohqiZ3jxQqQhD1jzOVB2BL5T2OlqTN20EzxkwlLulKoNVmKAloLu\nK81FvAwebD4TJBam7Dj09uvH7Vc4ovQsnweC5ZGwKQHDr5l+KYUTpuzAV56b1L4mWVv9KC1AuoWR\n1+u1AypMa7rfYuU8J/YBsH3L2l90hyykLH38XhVxAMQfE+rppwXmCK50Opvfu+3464I40J41o3/U\n2ukQgp2CV4cEALbpyBdHPBeTVEsGU7XgzZjhL8ywTq2g0uOMdr/GUHvajFz5WmKBD1Kn2/A48CSp\nNOF7aTFa1MO+YxEGpsbEGFzGwB/8DZSAS44NI2IJwsH+Pqdb5mDPEp99GepNImg4ax3xuQ5/fmM1\niCvyST6YzO9vDztRrx6DVty4yCz18qh/CBLLq2VO5mQjtLwx3EEoU5WRzivutrc7rYh7fYKPzW6u\ncMCbmpHfD4KjmtbzdCp0jbtSJ702e3alBxvL3fNxgtubgy1qwi8RdognRQaW3lJmodwMVdrO7qL2\nATWjJoDQ7N1vlYlF7a5JdHlqQdFmmyEZOcyxul/lb+66+qwRWiA+s/AxFe3OmsWkfQrkzcrm3bBM\nYCgq7RiGK/Nyg5CqZcFt6sIPEbjDril9Rk9eyfW6+rg2ti5qirauu6GTi89nmG90XFTqbWa2INSi\nu/+J87FDqz6mNQjHTpylfV+unw/2zp2uejZSOmCYg6slgJ5VzEmbLA/loWbbF169Jss2HKsqkJU1\nFDucH9pO1HhVVLLAgvzdWWSWVqHggZ7fdGPKKbND/q0DJS/MlSC4K9wc4d+a7LVqf7YfcArWJBSw\nb/CDJopZa8X7vfppRshZdLKB65dkiC71qdw45IYggV30dDfgL4Y6lqB0d83MFZ2fWmFGA1k+6opi\nCCFPqhmIsVyJwa8YQWio6rNR1n3Kf+cb5LMmmvDH08KeKeBi94wzMkfx8HbU3C4pNA3tFI8HU5lu\n2zYjSejh21ePxj8+f7hNOWHj53eIVwlGFJbeHtuOPKRCUR0ofAhhjWRTTqd91EmVEEKVQGqTsv+X\n0Ofoh1RZyKvBRJFf2qKEDx5HrHBNDup38TtEIQw5seyIR2VVWs7VfqMlt1PMiNCEK5djB6+o6Vq/\nPx0LnlJneHZ4aPg+7Jdx1UYG072d4qEzCB1Xqg37CLd3Y+xHDV+7QDYT75oX/2vO/RsHH8+4CwRy\nrw0knqI4mwfuKMWauSJU5fNvt6owB+BumMxKi6CJn8q/Ahp/Qkye13tRKneKn9RIxeKkXX4bdp3U\nPOdPMfTsdf5FfIIT9fsBZk1q+DN584O8YXhQ/vwoYlxkO03yFQy0t+v98xYVtoBWsnIGcVXZNaGl\nFp1BakMoraD+DIttVaUf0wB36pUfnDLTDvuHLmpgk2XG1LmVRvfdZ52WboncKChN3klluk0pt/AS\nKBTVmhloAwycTXnHnam5GBIjPwPDtu4qEf+m1DyGAo4egZXTy/t8J7tOICSHhwa0V4icen50x4mi\nF+80cHQS+r6jwF0I6P1+0waqv711ZoZ9e8OEeCKtD9cg3UxIbQHJ//qPhG5GqYQ79nNCUcxL0COr\nSihjFJOyM1HcroFKCiJuOCu56NDvE64S/ohFW/8B1RyBPYqcsGOHDusP3PPujuXmd9wra9whktlS\nDiBxU69cPygcHZGCAXvFCc6/4qczdg5RBWeH+cTSnEQ+LQqWVNL4KQSshKyGpjX1CQtCARE3/khz\no0pMSYSst5xKLVspDiAYAYwmHaMhq30l8dct7s5EfvE3vTEOpYsUgzkK5FnMpTMQm080koGudP7x\nS04xhfKQ6LW4wSxG0WxmHIr3hmuVc9tsRFZ9T1mIH5KgBBhi7XEvYeFSvhdw5utdWBc9yE1bV/IJ\n0vrEHBdEJQQ1jC3JHiDeNsWkxk/8VV3v1QMAB8N793KXxgQ/1jEoCwo4r+DgCws300qN53E2O69u\nJKMVjejhty9xQp2+lHRIZ36dvXnVTUpvw4PjnRr6nvdxbkar40A1xSTwZtOv035brN6W7IDeKByR\n9CV6S2CH6CocTKT9Zt8vPpltk8xGtfZvL6iP8+E7DEyTKpJNSbto6tPn78lb2k5J+EbZgbkvLq8M\nTagu9wcsOPFmD6zm8ytmIjLDQnJX7Ly06AkqKfoEgCv/RX3sJDmhLxuUrYN2P/XZyZEXHtLmfjYB\nsIWtLwccXsmc3oVsi2Pq7OJa6yyIdyX0Vag1r3cBSfGMXuhqSEbsGPpHGQAb1bemX6ZL+eaRR8Ir\n/eZQNuhoWG52LpqKtzgzdwYD4dXnawZEgrqPm6go4nMxHajMMT9x+EPRWMRCblVLMU1luSH9kaS8\nMkIoiifAeNimveh9mQ9+m9uCae7DWwiSrDtGe5S0aFDcbg5demK9BS6oJ2C3dBToRiv6isyitqJ1\nK4hru5Lh0iC4ja53Qd1Vl1IsNzYAQ9eEtiubhzCW0UnxLC9l1YlHe0Okqfplx0X85fEe2NfClZkN\nMVvns0Q6cI1RCZoehNR7MEbMUb9sf+YE/zd78entJAGGQcMvgDqc8GPH3Ph5iq6REzmUCizdjv0I\nQuRHIwhl2tSwe3c7oALp7AMb0UEUcEEa7yNBMnSZAwJHxxIcLHifNZnM03He4c7JsB4yGdsZlDmm\nzZoBCJNcbpyRnlvDk7moNefE4BJO/fNaReEAiICWIlZxQA9zDxlf0qEz2FZgadqLiPvXKd0SRjA4\n6iDTL+0XdstQT0EMQUdeOAiDZ+gMhw8gXB9TUZ2KzJmzbfZUOKnt4Dk3S7ZP5reZ67wa9T0Iow/r\nK6VXvm9MDYeTLJlHKJb26IFas/UWABGe7CEM3RCFR5ryVylbEh2frp60MtSfC0mHZIPj4PZVdoNI\nNiG8ls6YxLThfFsXWp20HODlp8vhiepNTHOGoXXKgqoP4qHxUDqUcc0RwU3Qppj3tAK4RurMczSz\nhhlq8xWyWv5vlyJxmJzk7hfCkbradsEVNkfl6K9Oahz0QpXDpQf2iFIk6sdPbjligmhJi1mM1nkw\nG1OXII9kBqnpENv9N9RSHAqqC2EZ0rpCoo86Ow5r0oOJiUmcc65rAomtlFdRFu978TKuwgSK9C0+\nlvBiOfqqfF1RXBAt3OP8BIZgKX0duUVG6lxYs7unXE7WrDkaG3V/VbM8WbHectyWnEAvRcw0S9mS\nDdiKwWKoS0qbSDhtaCGXzhWMnM28+4kegOOYPbRk/Ztu6Uz4g76nX9OiU9zuNUq1WLLjEKfHhK8a\nGSK7TjD0XfBFlJBN6zICribUSvhRDQzFzH7HC5lKMwntykOMgHH5PeJ5U6E5npyoaAjscpk+WPXA\nO7umsA3PQlzkImQmqtskI30+FAMhso1bisaFVT2D0o3MCcuLkhHfMWr+6sIBgfjsPS3K/nIc79Q9\nW78xWZMkiRzh/66GAojp5UtmS+9z0Yefinic4ll5BWvFt8Nji6T5qr3JNbmRxSLIrWy6SEQYWFbk\nuvDa9GkoamiLQGh8cxjQYiz4sGUOXLRClIx0n/r+aCLxc1osC4zXCCC/H656dE9KpcyrxrxNNjGg\n2Q/qsDxIDgLGrTldEhfzYQxCutaJFSxO5+lBXt/b35vFIgu9EBtQDrf4Yb/vRBnwosJ4EXFzhc3t\nCGxZRFmfJk2EolT7/9M5D6mI5D69lbzOGLfsas8scb1Fu5WzV/LVcuhOFhwOfbhxdKjynFeYJIlM\nMg2Y8V8wIoqQqw/LaPQs50OVfuhNZMfG9jmA+ExAZe/ucokZeZna/5j8jVI/rtQkEIg3A9fboOJs\nI3w+MI485SEWZ775L/kBv3b+b5mquXpb/LxY4Zzek05EvFEWOdHaJHOx53f320jbIAufGGFQ7S+r\nMLP5o3+SIoY8UWBBcJL/pLJPPMXYzHLYwo9sUUSrSNf91mMHDv+HU0Wh2eySI5i0INK9gBkxx1fe\nOnym/qYScFhvYPMDuq+TPTH0iEWD46s7Nv4wuIOAq5xV9O3uryeKpUQziY+T6z//hsGBBWNbBl8w\nILc8gwYVkfUv/2L46Ne4F0DRSMim/kOuxiN/MLiwivYwaMYLPCHBYTLCq5EqNIO7UnifZgY8GmPv\n+dI7bySys73tXKSYwPwdbvMeqWjgnm15QxWxPxnL31tSCh69yHnuR/2UDjSIAvziXETZPI1wgtzH\n4zNfH60m1Y4fzEgIkEhWL20v/86j2eS8LajMp6wG+zX/SH0ofwqc4WEYNTUUVt0txzLsY6vccknj\nAMiGAZ9WGwk3ltiCXvSiA37xd/64b7OTSOxdAKC4lCMw32HOZK16d/EHl772X/CW65LGXjBwz+g0\noKGa2hjFuaO6U8i2AJDZO+yb5Md2Cr5tLRbRSWmk81RoMVUqIUbpNRAsjbXUGZpNblzYOeQe0vt1\nf6PxfYHe7oPrkpdbVGRb6G25F5Js82fbjUpzX2HDdU7Il1twenLOBN4cdD6eLejdhO+pwQdYX1pB\nQYJ438wpPpXiwEpSgmIMlspfG1mNSTxfdEUAHgFRWzDvdbBaWM8XFSyfjpZSVh3K0/L5Oz1KaHMK\nmlL84qRPVU6Rp+NoD29VfZb4OyRsO4UNd4pduIp4FeB0TQVM95pQ6okMDeNIceKcw1O91PWKden7\nflkLY+RgDV691cdU4QbC2BRx5asY+ZiKu0bEWOhkJH2/KmRJITdtA+7xavT839GCEWYZCM3YHo6B\ncuw/VqDedEV4xND7mx0bYG9x9guBtGVTHiDTyb7phXjVe7Fyi/x5t8VufShAgo/rtyoswiJ8BhlJ\niPsuCwoul5MxCFqHLK5B+UZJqSIR9/1VIFuGceMk5Ubv0d1H8Z5bPpQwCvdfLL07qvjUEvpa5mUB\nuJJkNEG5juaNM0/IUY2FxPzrNx/PTRIjl9LuV5dlE6NhxpbJtZRWPj0lE8jjK1chUV+6+2I9lrTc\nrJ5rmF7L+wbi4C9Dnp2x2xYaS/tE0F+VimsBt7l7B9bAarIiivHNFgTe2qE/+Kb1M3H1ct1Hqjm5\nAL1YaKcUqsQLLnEvw5cPBqQ8QW32XBuof6yn+xxK1EOpb7J8gdZC9ud9Atb/F+rDUY3Zk042VOJ9\n+38BfXth0Ew8oVZmdThyt5KDvzgcpYhgHwKbx8cB7uW0LcTT3DG+SLkqMgun6MwLUownC1+r4G+k\nPOYQgyWZ2hwdrVfUEm2FQ8T7jIjofPdRiOV6vMIyo1LQtEHryCdfVlFdMVkX+zEa1uMOonNlIG6F\nqlwAOm8pi+/BvGuB+BRrikGczOJB0Wg/rgpg72XrFf3i1rneXsCsO+VpQRvcvl0H7+GloQpZ8e4/\nL6/LM7YId2uE/6LP5MJwBkwdYhnQeIBRDsaT4SqBqvFFGUwo9XHQ7BX9hvDKJNNr2WJx/TN4DGSc\nQSXf7zNQkznf33MkIXuht7XWfQq0F2JDmeO2vQWLYbSyGuKMoCeZqlWTINTX0kKL2gXogQo0CSFu\nl3yJUjzzXg8kxWRp881QDeoh0QXJzkJlSK9RcBJyAPoGq8MGVQnhqlZCaCtKwWjxXPJMod56Ofz9\n6d5QEnLnZTdUaNX5elPnAy//gVbggUKwOQ/skaVSauu/sHjK5FOnEBYk65Rd7tYGD0NeBXwgdzq7\nZjElbS8KS/Cefr+77JrYrMx0aZBZJ7PQi9t6EAB8LJx3ynPMFiOi1mFRiRTnoOunlquPz+IQPZCz\nMGnV/sBJnYWAFfT6SVllXQSioS/rUjluR4vovLgImmCkRQKUSj5xnZdY4AVssYcDjdo02+On7piN\n8qNFmcN5E7Yf/TncOjvzUDpXawtm4XcUunz6fz+TAFwd6SFGP3I6tLXK7Ell/AJ6615QZubiMzMy\n5isLZteUKQdn5qY5SU487hB+j5EiF/KIGAbITt3VhdHrimshB5ya4LsOjyuKLV8kB/V2FxEcrVP5\nlPsWo8vJ/pCG1SE+UmhSQrWcx4/NM1rtR7bCmMtSfeu3ZhArzYJK2EjxCmwxqxivMXGcsAByH55s\nRNnTvl30k066eZStn34hQlok8+Uj4MJAmSuHpOlft5Cw/TOrk1MOZFdyyX5HyQGbCwAhDElXG7Np\nNtIBPPZERmcalGEy/Owm1PoUFZGrD0ygMaJgnLTHY6MLYf5DaqbqAsq33MOscg/qw0ro97IvQveu\nbVHyQ8dKOw0H4XCakKKp59qL+Lo06pAmqctYoqEAI6NyA5PBetT83h7XnqI61qecb+efcMBgjAHx\njfy4b1SDC/HxaiPhae5rVoY4Mii9nQB7tuiNNT6Gmu1Vwwpg+FqVEjv+kwb5pFPKdcoYZP+5TaCc\npfDutBLUv54hLF1z9ZTSVfm8dhinFIriv3FGv9/qh+OBVnE05kFf0guuqhsiraGuH03jxhZjWfyS\nOaM8SAV0mGwdime6bWsWIdynqw2HAyQx5ZB4Y4WQMUkJTUZZqfnyJoiPtmujk+CkRIbdfqOinQVP\nO07DTJxDEzoF7uhPsOTK3EFXwpS8pYBJ6rBUpkDv2cdF+nkS/+/cAXKl/YHTpBgNyZhjRpWyxHsn\niFcLNNJfu2sWWDKVydWGDedDKCGcvqLPUsStmaG3e0WUzqYcTIcOw4FcGgqM5B7L1taswxouzywa\nIj0O+yHtm4lcDaUaPBH1jpC3Tx1teYcGoV9p1KGhmnqYHidnh8j5RR7mQphYOBTEDhrfxBok0oZp\nxEb5R0n0lHsnE5wR+R4TmYpqKaUpaZOnnhRH5vBWzpvNoXJZHsCXpiaDJFAEE6vHItaTa0n+jLX3\nsAKceIWi2N0ON80jpDAKDd8n2CWy5iOPEydoKV62sboxWYLHelvWFOVdHFqza9cLsXbUMPH/vDsB\n8zUXcORUvcn7XjjuxPfPOc0t/Q0dPFlQIuhEr08hTBnRjrrlpX7+x6ZTY+fPNHR9F91Pv0fPWCIy\nbROzbw3bSzeY6s15+qHzXfdfy24+QkpwFfNxBLscbYdYMJuaHRfUkYdyiSvy88tiTke0cWsJIgL8\nb6LF55Fl+0MmwuU9qJt6LFzPlqMjg3MTJMUSxs+oM8M2Y5lbhwQwyifFyhKYtLmLusjTARMM25Y6\nukzQRYRNI3Oxe5UbT7SrcwTUy1Lzewof6EN8wyjkP5FSWkYNXeMzogCzF/M5OPrEz3P23auJXL5f\nPSwxg5GwtiAddrpoxwVq7t/SXomVKF8qrK6QHhSEkffLcH8rFeij+Eex34jAGjtyYThMr2yAKAjQ\nvo4wSdK/C8Znry4ZN2XvcUYAMID1n0uTpMVXdijFIGLqamf0k6GmXzQ3UpVfSzrDS8bynQPdLLGI\nuxvSeQyS5cbAMWmj6MtbyYyhYMLNeIGeHc1Ble5JKk9XcBOCCFgzOOv31ocUMajLFqBtSfkqRVra\nFJiVtRF38mFRo9WKRHhb8sdoITC8hS2CTMQSsxPCAmNaVD2bJ/qFT0p1EZZq6BoZITEqjyAZmtZx\nXqR5qhQI4oxW96jPl+BN8zN6fFGwSg8Uc/RdDO4jXwwJaU3DhK6+dMf6pj/dlOYkkqJWJ5zvJtdI\nN/rpUYECSK50BXCzYV95c0h8TYbjLL07Bo0wAZsx9en9mAAJjFeW5J9b6bw8wSryqIlFuv/vii/8\n0NeNbQ3HukqaJ6WS8ig24kNpl9AaJTw1mevhFDSLwa3iuPULC+87SJhRoIKk7u5faUsPh5M+BdS3\nnwwNBqnyAL/eoOxdZGIbuQgqWGGzqOOHbG1kV1nNYc7Xp33yYYqiV7WseZtb4ifQcYtnIMXRuCPs\n0HNXHhr7bZxfYss+z0D8ocASvnpOL8w4nlKT2PiLsJ+jpVGuGS67p7kyScbgWATTr1CCJkP8hlGI\nMX4ceG7sdnxo3SvwA743LtMPEDxxTJV+J/+6w03IxGuA5NzYdhkU5Br4pGMfka9XTP8KCa/gkIs2\nw9HFq5FtvyOmvpOL4+vO90uK7rMdlqzeGa/PolqIB6YyPVJKLa4IIK9yih6/HfL4Dr+t/VMfsX6r\nwVNKcvxe0cS/qHRNS5g613kQ6UhUK6nbWfngwumJfxEVujPsHnfwLImvXV+Z0lpohVidsRwRstCl\nypmA///VlWrIIEfM9ztYImxJ+QCWHceJt6eh32pSrS1Y7CAJmjnpYkmyNQzNY63+27caRFAiePJe\ntSVGh1aHXEvlFIm5wia01tXhKIajPWowqppLHpWsZQkS1rJJUM4r0e11wGleAGGxpzLFv++3rRZV\n2E7P0LyqAMCVXwuJgbDCIUjKBeXleHsoXTjsTJ0RcfA16W2S7LwZUHCmJVq4hjScokm5x4LP6eKu\nnW7YbxZKQNnAIWffjZAbiPXmq2NpSzKlWV7VBEHvhB3WX+EGeM3dY6Fg0rL393oyDKouyjUWwtJK\nKkxwPWhTHPfGtMQHZyUM25PNCS9dRLKFvj+8Yuv+Cjbmf1HTxuUHNkIppVMhe3pp/EoYQdCKYkf4\nNmIqgPEpc1Xw53xrv3c2+5Qe2RPVMCBF8XCVGS08pfg+iaC35dIcxw6Arwcub7q1AJUHYWWH3e17\n++/sVHV8krkistFmP10E1UX/+MJ9cPXKZtgTdfX1nP1wgv2fZiV86BE76jaU7foSkNjoqQztHEvH\nvnjg5wHfIOBGVzLQvSsux2gimvtklrdrQeNtEAOAQpNS+C53UQWER5i7GMN1FpWJmOMX0AnM0fdP\nN+AUFHdOIyVfThnj/V74mNf8KRQZT8nQUqmy3LgdGQ7uPX4esG3SBEeLh2JSQd7DG8Rzy7bzFHcT\nR/lPn6HC2RR7J+MiEZbxOgXfw5CazrPTtOwGqDjFroba3fEyK6BRmL6ltjB2nnNbZ3QMS84Tngu0\nztlVsUNRQ0vVqF0YHm5Xzu/LFsbmB7GIOauNfKOdAPUZ9+FyQsOahJKfbgvle/vzDZKF7dJBesQR\n7G6ng9CIXGpMPYE0Je+/agXWFSxCKueeO+bxz3ykBrwSkZqafIocSh2im4U+LUrsdQ6Qg5KHNbvA\n+2ko1mWue4ZHKFv3GFIz6qy8sSdD4o1YWaRzp6QR6CuG/L0GNdQmSRM22JvOQ9ORJ8zEvxHKtsnC\nDDxX0UtcYsOlNPodlxY2wv52fihmfKKbhbhMpFY9wB8xvbiq2ZD4NKhflfFlzzNjsaAJtm07xKlJ\nvemry435VhaDY+TdxjrGnAKY8dtM50Zuw5GkpQQl8/L7DdmvUu0b4+ozCk3HZICokDOSzb1zTgvU\ngwko9mlZjy6Ro+IL6CNR27Huwainy4TT/R0u8/+5Fv179JNlvHyGxYXUa5rJRKrKic7H2nf4dykH\npcfDPpPIdH1kEIrpLaMjMoIsf9ypnvIpIO6RdGv6+Q6txwVGizW36oyiNd3BGZXe5F2CH4ImOqdT\nzMQ3d6iYRlIvqU9Kw5Ul/e++X+NLUudXHoAMRCPNbvPhB7hOYnKeR40UYNCDjm3KNgvMxzKh4Dd3\neQKaZuo7/YToyzwW/jjo35H8jGygVz0cA4hssv3j0DESJpsjI4uINFEqYK45Jn4fRPDMBxpU0V6Y\niAEQF54vjRcFgtShdk019k5MuVKNoQ+6ioiLfV0VtqEfVItvGAa9IlriFbDStqq4/rmdvZSArMUk\n+uF0EFdygH6DTJhAGoF6uE3zm+O7VytcdokHJmfnvl+LCSqwm2E9nVmqp/LTVl3GOKTP5PHZPyHE\nKCi06jAtv4vqhcRfdpwIt5LhZiXTuDrW/LJOqRdZXN5Lf4RO5T2gjYjgq+1ujG4JBq8ayr4Jhmky\nRSYp9fjRtfWn9lJAN8k+AdmkvXs8jy7wF2739kvWDAN/un1R/jxWygm4VjmCETmc3tgWZTBsyj3h\ndS7ip9ZGkO9ob6spwsAgTdxMfvK1vrx+UtwMbTZXoYLsDRtOHOpZtSlwqzdwlfTfP8wqu2owh4NY\nIMFNw2uV7x8Z19AnwHVSVg/+LRFyuUaDGsY0Tx2w+AWOhecrWJh18NUOCcw6WYG+/zLfHMsOy0Jw\nzbwdo+ynwtdG7mf4UVXSsr8vvwXKUGLzH/u7HLX6ri89GzLPTloHlsDEKlwnHWE+ElKuvbcbSNLz\n7MAhzh77MOCAOzn1JWSviNo9oDwCiru+wmYkeVGBLPncm+tbZi33xvyqZBmfdAiF26M8iEdZ0fC2\n9yNPdv8S/uO19rku7PiiqZvBEsudotq/zr7KC4V4r4Be4Fi1bhMPs17pJKEbnnZRV95jnZZBbWVl\nB8dCXMdwhms4DwWuimrqylqqF0BkHLvolrJ1PF4O/vId65g+6REAfD0mWExq5NMxA6QraCswyXBM\njO5ogsRfcuZw4y/Uft/kFMIM83hr6URIolvB7wRczzYNd/L/rUCnaBE2JIX+ZGd/Agmvy6lyaeSg\nQDDJ+ud46UMBCh7q2VG6ShlCYR4MyG+vuI9eUoHQ6OXuK+5XogDKPl1ThMXtIbZR37r3hWwh1axd\nlmfN8x31WfLCjsSFuBJExJkMZ5INe4PrSVpnMhT/MPhDbvh3TfPx9q/rDwDpqNlXg/4wsen236QP\nfqYOepmKZ/R5cPOjQsQp1EdDmykoEBb5vKZC+wJ2Ni7GDDTyuIUczE5uoWPFaOeHshGDmqpAyi0C\nYF3y8L311F3BT0yRTvNn18HPzKtJTn/lava4O4X0UK9gmPS9IUpRzvG535glq+TPTBeNNmMmjpoF\ncK043+6zBszbg1lgYMvoV403GptiT72C7uIAvpG0g3jR8ktV8ITtR8Ho36g3WEjUWFxurrhR5I/3\nMa4Igyi43BjEzm7f6cmxIh3L6OaadG2DZ38XUSedfRuMRuwWT60QG0FmYXdeGFv4215blbNsymcm\nk2mIDQbGDk/Qybmsoc7LPxjQV4G98NugY3JbxzfgqetsT99VhDmj0GBIG+LC1hlb++vcKjraa/C8\njN6NZRKehIkIZC4+vQS6gw27OP4PJrkOkXASle88FbbPhxozfa1WyIQrOq1xIqmLOHigv/faefeW\nAxTVyv8ScMVWcpI+jLJLLy4a1Ch7/HJ/igiVmCHlJm7ckJMbgtBVztLXQmXnjJTL6Pynsx6MKv0l\n8BVbVKIE16HLCsUqMPkgg0arbqf7yDPlygpesUhx0cUmFWse8vcOA+1H06P+4dycC80KWTsmPS6B\n5EGvU3RjL2y74HpjqP3MRfZBswhULeDpxvyXTaudo8034t8jEmw2Rp5ffDKcalxJbexN0612mGqK\nXqkLlz70YN9vIddrjYU26o3OdmYoBfN5cTWD72Re4pVTTuUqJ1HEE8xye8F24YDscQOv/4SaVieW\n8xM1S9bv0ifD1RYJymN5BCskUXl/bB/maR9C0MzQ47TZprWfZ8Zdhg9whQ54UgBUNuESTH+6DGs2\nACGSy1Dns4Y1955iy1Q8actfsbkIxYi2/oNqHZ02D2Xvwg3tHecFHzolEI6SlfAbGebSE8zOPlnO\nDk5WFDm7R7Ya9Wzde1ycw2/dEPIiNXKlzF14E2Q5XodVnrcpMwAWMhgnnuHIE49vs6jmYNq3GQis\nlhQUwP/dNeK3tPco+bLYIdxZJ7pWhl6d05lMr3MGDeem4/Cpl2QjnO3aBmxJ8J0XA9RR8gUjA23l\n3vpbX7HbQi51qCNjyhGK1Tmn2en0/fGcEOGhZyyCvJH4Qo6zB9uGykWijrxVWG4RmvxqKqqag0FJ\nDlk12cU1XziDHfGXtE4VhXARzXiF6esJwhhcSD4ZrgY1ji1RUxpWB+b4TuzJKPDpWO79abKalORo\nC/stTdrUrz/piO2okmJ8sOj74MQPCPxN9rpJdhy2k4LrMMhDh1kaspAmkqlclPY1falbZE7cfe/0\nin7NtWeOPQrKTl/qhE1qao7k6Ua4ZeGWC5GHaS2ipHen6ikeqettySwzRKBmkdDQSHamPY/wDQo/\nVo5THKpvcnZFmnuRDI9gsWrl2HV8Cnu3cziisYvsdFyyjFJlLwQI080Hm7YI3tK2ujDpuxu37bkd\nVnshVjH6Lm3O9gsdW5jBFwOx23KmV5lftiKdYyRkiF2iMjSw3tLSSlHQ2n29KzYnL1G/26FjOuI6\nmThzBJljDQuqaE3P8+F0mWoEBHmZCjrTaPb/too5PFL5RvZtiGun/PNgZX/pUEuzDeQeX08IRmek\nEKmkvHTs/bc7f9diRmuKuZ0H6KhygPZAuIP+2JJ8Zcy94C0B3pNqkm7GypUhQXN7SZe4ND/q67LO\nmfiUWXZhCIigT7LLJt8OkggXTxYdk0ArF5AA/dHoUgKcvhfFXSnNFzcF4C42BPgt5D5lWQUDipZ3\nQ8715I9sCHyxQVihVdsS/jzu8jW7ZiT9fmouvloW+afVRWXnzp4xWrqsHwJes5dBP+OMnR5K9XyV\nwpOQXuAExmx/sSUECT2cwytphepaK9GB4+yxMNZU8XIqfaawkSCeupH1jiH5ztVfu01WsSVZL0Vt\nZ9G2/wCR77e+YWHiga0WAuSbN0Sm/kAOZTbRQ3Iqu2L6xEwsAt5OufgkCG3QWEA6ZFCgt/11FtNo\nWCg8dspVc7wjJGcaQh62kkHOHeKyQP/GPfc6zfn8ojkU6lx6BtJUzVc9+5iSeiziOxJVcg+XiNfm\nry1bTBPVqs9V7GfXZMNMeTPpqgwy/SDSL7PSaaGXTc51e2rpsZPCv4PWW+k/3SAK4kBHSFsXoFai\nlWnFbldiXTkPzBByW64STapLmZt/db23NfGWmSAgnfeLy077nTB6S5VN3QJaubOw+sUFq8QDZWhq\nJlxIh/AxMOu9CnXuhl5COX2kO9MnYp2ibQXZjYB2Uz8GzbRh3KOr6O9O6W3eiJS0HmB8DwT3eBwt\niH4rzeVRFdnU9sZW7iCshmVvJV+XW7oEo5D+mVIWBfKFAxW2CN0E7mi2blglmwl/uUoXwiZWTQHN\nkhag0uDa1dx9iDbItFz0ff9B2+bFpQ8AkwoXj77KoRfnZlVXLC+351BetTTY9QZUbC9jM5kBy01H\nTMWQkj5fvhJ9zuXsRqN/ZPhdJDq6JQuiEcgl4fc7vL6BcDmgAMISZNEBSA8QIcAwmMU9Z0K6SvzL\nNAwuXYfobpCOxANwrbOXWCIRHi0LUYEAp0zpK3AeyOedeZ68F9Dx0fhcv7R5k4sHHwUeJ8QWMJl4\nuqJXzDcHIn54qJtSVy2yQ36u4QGuUmRMJ1QDFwxXSrRk4ewO5n6ndJrxupnl+yw9N8jpv0rFyy8x\nv6tNb1KSNcA65G38Uk+f9pXDFVAm9yVMVmNARfZzNrQybf4G+K193zlQGV+SrzXvvGpmOAfRhgox\nHa0Gj16eO+vvj9fYyRY0sOv+3uwbC1pn85cfGt8zdhHAShA/eICI6mnWYE+luL8oTUPFjbA6JuTg\nfWgf6iE/NXQSL2DBUMw5RF9/G3yfPOT8oYWbJZqL/s2pDbLW9hNGYXFQpXD1iH7/dJeQ1tdJipcu\nXGlb3slj/kcLiggxed89F/4aDEvVs0e6Ln27lb0ihd7NmvZrkbjT7vY8qISWtBVA7tNKlVV00HvZ\n0qvK87ftjk92FJK4fSekoReIxDjO50jci6dwOEqmYM16fIkvpBIllveCmSgWyYQxJoOrTBhPJJtf\nXfZ6PPmEUUvXU2cz8AnKfLRCcN/Cf29cKf549Q98BDW9jyemH6WdntrxM71+Hhjv4S5TtU0U0g0V\n0+t2NEX2ofWopXzTd7xXyQWW+2FlEeHbIg6Yi7LuQwhxTEUHKro+BW4SDMa8Zmib3qrPzVE1roWa\nMlCU552UI7bRNUR67/3lL2I9V5OF2EUctqNmUS1uRRUduiEN98Ni5WnO9pj7dC/aEx5fYbprxuUP\ntYj6TxMUAK4EpYp2EU81lidmWfGE+PSltOYjZqwp0eX2VQG8gtQ5XLQ5VDL5EmdTdG94MAZ3KWl4\n71qGiCGftP1gc02JOeebdCLPs9RB01Qamz/7qRrtLZqfjEm7vFGnZjrPbvouq6aLrTrkSoQ9Rku9\nBq7sCRWpZJHwIQW3joU6vIKWqovqZrmuMZEMt50iADknpPAcVttuorkxIhrY8EMGTVLaeiKc6+aC\nw90fEP2IluyabL4KCB9IP5YRud8Vem80dhNNefrYqAytpEjcQQMbkigJA71KxdxCMLHjPZhIqf9P\n1FOlQfDEyWStjz45PhUvBsWGfNfY4e7RP7t/msJ7F3wQoa9QKpj9K/iurRXNZN2eKT6Hj7SGkUn0\nACtUn9Zun7Ua1be3Kb+uXxXfvj7+T0Uz3jlSydytD55UnuDAYq+K2gAwynXtc6841qezeIxadr37\nLq8AbB4IT5X/oDEUDdtuxJhziiuLroU27SrBYnAx3ZoKLS6XfVF7wXS4LTlEOGi4AzkJlFgbtjDN\n0n2EsteXDHoJpKSx1AqY+vi7VY3JpoxH1RemFZ4Rbxr3Xmzsdx4BaO8hsfUOAXD/iq2b3VP/iWhB\n8XRPiTNtsAKVeSMyRv+E/9K5cMsB+gFtd1En27yHSX5qBO9M1g4ncHw+EIhgU0Tg1aEZlnpBXn1f\n8KAdY+kh8PwqGgcbkRdJC3bttZ/g9xR3roFPxpAZ+boxGrp2jE40Fcr3X4g44jgrA4IRgiUDIWTX\nqR8lxjalxvMOV3ATBs+7cP/BSaFzc7AbNgflKhebuvoh9OVDpfPv5+tJj/Ucv9iEIo7eCoyA4QTT\noY1enrvni6ko5gsAxgyanuHdkjnMV9qdVIMntJDRkt0cWEfdAEj8z4tYB/hGCMz103rrnFkX+aid\n3cFFPfSGptu7BMWqfuRmrduQ2xdKKgZPaj+yLnReK/vEbKIkBYZl8MlESCeAWwf1nzu1G6V7xSXU\nFruXmDy+vFG1QwwK2CMJKGUq1PintY4siRuRBhjdR8bY/v9Dppoqiq0GbWCnEnoeZ0lgvS53Avh+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GcA9Zn6JSJxTUCwYs8aQ3SIm8x3etRqToWjYKTAbZmvRezqKjuhJ1htlHyPt+p\ngxFYba0DOIa5737BxwzgTL+BM/X75cddRAx9O1zRk7WcZscO4nKsuVed5vzVpY5fUeeam4wpEreH\ndf5fZo+i2TN8VR099r6xe3IuXjepLpUDSqgz1s6fjumUU49h8B5VogWCzI/Sng4e2ySs3DuudcTN\neTbO7F7hocbaR4Ja+OHzwSKcERs2tKt3SKOZaqCzh1C4cN7icnZeSfmDXVkJyB9mTWl/6wSahflp\neg4bS3CxHvVHBxc1wTPp6ZwEbCNJZ1GeG3MurB9i3JbnUDzmOFhwg7eOaFurXoGiv45RB8vQKvjc\ngyyFG8V0I0UxUmA9cFlbilM6mXKs0c7bvXdGnxv2DQpmqWwHJafqZ9Ub7GIRP2nIw0yClX3C5UaC\nyf/tjtAnY/dw/5LntI5BBunmuEC6fBhZSntF7uXrDWv1s+C859IbUO234tYG7dJFDQHZH29sVYfg\nQYZDwlOgb8VuP8Lpo6c88I1UFVYFMgCF3P5SQ+v1m63bfe3bay4HUTISeVJUy8JV8sfADq2wubcG\nuWcfUD5AShQOLmrpWHHJ7kOetd/o40exAcRpY6ruMZpAbw/XTk3w+IZeYAjXvoV4HsxbneA/j/6v\nRCzoW5P3UuUoaB5PgGjjGV5hyDlRE22MnFsaD1Edp4Aaazf6x/abJR+gEuiOjIkZdFyslNkczRoD\nu7By43V/wCySOAnWyFDHOhN+Rk2yxZXouQu7q4FFldEH1iFrGHvxaAEezrQSskVgSBq5s+L59ioU\neO9CS8jae071lEKSz2D/g93/OL82GyJlZWj+PeSbqzhShQ+oX05Il2Hif0Nxbu2fUZVIMzIa9VDD\nf0JX96UWWVTDr3evRvYoh7RwhDS82OKImfwBmSzxFjawoemFpUn6yy4AdrgWom6pB82BOMrWyxCm\nr0baPyGumEcnivasXzu3Ghg7l4NtwjlcTuSrDJyiIIqWlD01qFIT/NSe8XGEUU3cnSBqQfMnb1rY\ni9O0ljhYVL8fURPadXIpnmspDZRBbO/9U5PDuTLIDUARR58h3mS92o8oG+2mYSEHMk9Yt23OoVZN\naP/TqOTjA3bB1PM7YulgzasFE+gl9SAFP7u9cTy07ik7Z6RqLfrweuEgZzZGPgnx+HDSN6clM4mE\nVHYMRJf5jlERFhrV8NNEHb+dJ1cy1o+50SKlrf2bfrsA1sMfqwFFA7WTEXfXopqTuOy2pS6YuTzn\nLtt8mp+m9VBSNQNLGSuPeVQKDL2c/GFdlc6tWG5msBw+rNDavwUIHfgdxQT3krhLdr0g/Xg3vX10\nmVcpqzA8cPWZU/PuRqdqDxxY+pCqDWMuX9X7UVKrPye75k4QcLary7mM+LoUhbsrfeeVgHdXbQQM\nzMhNtPA4SoBi7w0scbWfeGmkJixU8Sj4L6lA3ZvMrp/M8AR+++6EBCX9ttW8OQssFTRvoTnGA4Jn\n2kCJwehXlV5jwMSToYsyFFZIfrJxAUbo/+5sJXPMGPJIZRxRvhgucH3WnPrzojvDrhoDhR9WTn/D\nUIlyqa4FG7wIMST9OtD7LQ2xc2zji5zZN9DmxSdSMDQA/03HnR0gcY5xRBuJZ1lVW93DRflHAlIE\ndxPAtrUw4T1wgmfkkOnNCKxOsSAufvMYEchVBCXPVSTCIUgCl1WDz1FztJXRkZhd7VubxRZycQbb\n7F0xSiDk4EP7d4d1bLSz4fXRdkVa7inKtRAzuHfrKZes8NViU4Hb0i39UaHG/0rHCiWuEqEaemNZ\nta6O+8TeqDy5mRWmtS04oiQBIqj/a+YJjajeqKkJo5PwXbtHvSQh8grTm2jifLLDtyc7quNULvHe\ncOm9lfFtaaA9EHzxLtTm2U+5jwj6VdaXu/Ui+MVFI0xsQHgjT2wK5sk2yH071CVmBEItMF1tRgQd\nQIH/aNQjpXW0VHg7b+/8rumUFrN+pmkyUxhN2563muCP4KBJd0JQrKwU7s1O3br5fHuueVJAe9LR\nyXRESLNfzc+gr9SgamtzGojIrCBDOUdjjM6J49tE5jD0h77qR7N0SyxngO1MjZbfnYlh0TiZkDrO\nSn6LQCdtHe8jRfHGsS0T3MouZqBxtTrH1h/5Wg9xfQiQNzbjFdKkT5KfBmXj5IMkhLC+nYB2DwNu\nSJ3tFGNeOhrevRvFD3kUC7fsFE/ZwDgMmeDRMbfPY/Lb4XcSd2iIZBORBSlcLw+e83D2PnE6mkza\nnmnmKneUB+XbLJ5SGoG2x3n3eYD1iqpgIRRjPc9+6cuqbbkDWi4/eLtllVND026fbWEIF7PSYUK0\nwh1664zeBZIErMhQYj2uSBUZUWLIb2ys6q64oBSI5R7dLu3h3FuVojFnfAKueZRqbC9twker0itL\nIMphRzQ97vqXPOpQwskpiS+j4989IJOhDe4UTwtvUFVPhujGAfnowG3xIolbZ07V4VTbTzi61amj\n29GzddvermmeN/WW4di+c798HQaVMAPlLpjdy5BwGUk0SINd/oPNbjC3LeDtSSBdv9jld6nDeIjT\nNOVG8bBSqDP+0SDTjI0VlDlLKXh3KmZKpG+OA/z3ssNWrlyCFOgq6ZD/BUQCb3CLl7yKAVDswePh\nnK5UpUiGqm79YFthbWwOedumd7lJPMBxNYnJmAmZtSqcx38lGLipvw3ZMIEBliw4TlSRjPOodnCj\n5uztSEunBm5DjF2YJrzC/eZ7ea8lkj2HjtFZOrVG1eLYgh9Xi2PTJn3eCiZZBLMyEIGbpmrAHEEt\nDir1mN23gE9E3gGAm5AIQd0X/ZM5UBNPXpYcT4QMDGFeR8CC502+5jQ68swFIiwkynNbXW7v85kP\ngNi6PG3pHfS7G8j5+v0eyr4z87SXr+0wQ7+YrKvAjVHMKwTGds7JZSrwY/xbyS41jfuL4BK0XGi4\nGKhXRrAV6L4csIatF/43SQRMQAYQTLkSdDlWFrYmimVcttsF3Nb/V6BRPKOMZf/AIRfl2g25CdOh\n8t4wi8f2wZ/6vvyVQ3JjUs1GtUYeFEY2jWTfc1nfqrw6YJmSZExzhFIq5LVEZ9hcIQ/mWBgf4VfF\nldlM3cF86EoYz2hdMw/bPSu8pHqYAOWsZvsPVeLvR5bf+ugQYrAbCzBTFgM4SHoJsfINe6+0nnZW\nfkR1pXXII24Nn1y/HuBasCbvkzcHQwFyLWOi1PcOxspjoOrteHd+nv1PwUwED5QpalSFP5gx0j/F\nP6OQXBmrcu8HNETcC5BNbjUUgxVH8NmEx0vYKQka2u9RIWNOY86IY1UCKu4wT5U1nRyTpAy96rY1\nCUY2eeSu15cl3mFEsc9cR2SaZp7oGFiGkOeASbDfact9JWvN8TRyKi8cuY8jnRLtMh8w6wkHUW+F\noAxhkhQG48kdBvp3WBM4eJC/FhAoYDpTS3VrpOPFn7cHPRte76xha7ph35Pmy2bw6sY+BQ99Yk6h\n9vmke0+Iyb0+XXIHT2rKEiFSiu8dRJ6l+AqhZidZgZkJhwWP6y3ecQwmJVAhV+qEd0wPaFwMQoVI\nrzJC7r4gIi5KpEF26KGVAz/C0/Cj9x5E11XzeRsFpyYKNmgKzN2jhUC5+yg2/QIQ5A8h7Kg4dieQ\ntCofAS5iA+FaHtsY/jn5rX+UwExiVSxZRm7UjJbNW83QQwfFcfsW8O/bvA5lU1tk58Ii8KbxIvek\naLGlNnWFN8WThhNIHLSDeHRq2zxLQ8tG40cLPkNsyz+rMRzi/zjKmRbDejskopG5i/lb499GmbXr\n2C4NU1qBCMI4HfUZ5Mr9joo7/9FzpKG/HWLSct91DJ1rOP/RoZv4rbb9zKm+zlwL76OYPF9yA5Ma\nZe0asLuYZRnc/l/2AeEAdQVhjZCwsrClN22r88vb16gNFKtjTExjrzsDtDjZ38VXUOkOveq4mhYn\n4vnLjumrZBCz7y+6ZCszoIOjULEXOLchdJYytt2ysJfcaHDBPBxcJn+WKQ7xUvPyzh5WgRMUdsim\nDuVT+D7JaCvgAT2j1VfqyHMGXgfq5ph5OLNiOevTUYgC1V5HA70U8xcLfS4RYJI6WJCHWC9Wbngz\nzNLDlUD69JGv7uThe26LzvY/ivOrbkXghyYbkN4VT4GLqOsWMCYEtyAxmvgWAqIhNSPw0NSJjE5x\nxO2zQm1FoNF5mu+nCWJdUPtx70u0a8e5jdN9GFlj0EYq8DNB1X0nZZoBnNM/W7TUMATH/6CXWzd0\n498UFlvIFo2HQrBaKisdbEQ1Qb007Rp6TCnkkwgEHAcKg6AJiU/DZLXeYF60Biwb6N4KrGT3PWbt\nf0Kmi1vBxjXBTZbQXGjHwCQ5D6b5cYFeRxyCBrMFOUv8qbAKJEjRmrVW2MuIwIBgNbqnWIRstX03\nI5zhAC0x0EWpvNz4BOglCPcHaYYzo76rjSDZh4aQlyQmEiCxXT06Jv2NYSW0tU39elbVs4GHgI4T\nym3nR1zd9r7mOP4orAjs574aT/9ikdzavVr1NoMgeyyPCkPAIT7IxIce9jz6PdNk6zDEySO/wwdI\nCOV0YVAH8zQKQZLiL4bx5xvT3KZbcAHR1SsaJeuBZ8Lga1pt/5pLF36+kIJ9mqMHR18nWmcyeBNL\ncJEQH1ntn5eN1jpnbbQWsPwozLdy48vcXxr7N+qr9eUL8XPBcUpq43UZWMr+XUhhbgimqWxbY/NV\nfuSLs0MZQYkqzSennveOAr5UkIRGGlsWXubl8MxTBCT+GUtanJRS9duOH1yU+l8Lh8/orNoh7Nrv\nc1FaI7GMH9dMRFNACBQILarMsF7GoiZaxVxfCgQZMv2meRqmfLlgJ8HupWxkyoCgnlZLndHInG9y\n7Hs7zUmIhAGYuwtq9HnuBcKJzUP6hi82F7qk88GLhmoWaGDy+9WlFirxxJj9q5kYRwok79jIwzx/\no0ZQQUUtE1ZYANeGBMwhPqW86Ltz+DOq0vA/z8rOS2GDPEfNq/zALAuz9Wgmfp2XmtwiMCk9wXRA\nn0NajGKBfnpxQhGvH6Kt6j6GX4ZePX92brl37hhv+v3goAezP8T05xCAO3ENq58hojoRpLskhm2q\neGZIZA7RMgLk1EOC4eXqf4gyTW/XzzZphuSs3NBT4PvNCbJweAzuRW2koJNRXexyhIMu/uOSuyNB\ndtKF3ndxgqvrzqFVmxk0eyVDB1YxZW9xE2fGTDOgCvXURap9QR8KZM4J9nrn1Ogzt7jBEfj704HZ\nVL8HU2WnafB+1NDxgugtg31MWoZs7+giC5VUC5hoa7dc9vsbU9FNT5fR5ozf3v3797tYGsmcH2Fg\nBi2aS/mM6JqJ4rSaK6oFh+5Wnqc9pEtpsucK/lxY7dtCcWQ0t8pHncn7E1jhJyb8SqUXGzUXbo1B\nCyT8jRoNNy23C2KPdfcFdjUmnbnp7AUtpwN62qySlv3Xz0U5EXU97y8tdFxE0cnjt153zSfb3OMS\nrDlVGh/Qwsi9CyoBK5YapXAeceF8PZ9xlL1yT8la2l+ZO8oZsBW/PIV7k8XBWXeWzjtyWjjkXogp\nC2Lm+SenlvnxblFP5MjHdLkLIhRChOx8UFJcwPVGKWVLLVGpIdZ8VNsih0z4E+8g28p1tUC4wMRa\nhTAxtupzWMdOflDIVg9KeDAMPXp9zX7ZJHykJWRxR6q+3Y9PVIaJ53118LYjbT5kA6t3dHjfr4ga\n6sqPWD3DDpfagbv0tUyujVlnxaXTUCPu3tzOIEoPC9sIuCYESsSkquOFkoWAnE+2GEkSzPxgGDM7\nvLjNRbflPpBjjD7xsDSf/E7LDMCtiopSM521w2KOc+kCS9QcRDIGhLkYCFnxICp2SqEvoFAjSe9o\nTYG41/kG1FuDm+R+VFxytSo6hKqkhqIt8dtb0dDsY30Mlci13Rcd+MS05Bkihxs+hx/MHusmBKOm\nMcXWSABJJeJzN1ID+bRm565QsBExStKd1TmzjAsdljAUPv24FISbs5iz1ruSFpaRugTX0vIHGAWb\nvG87IsgEaDzpNSnFPVlWWb3Ae1kcMx2LlRb7534qDRmszfq8fgmYIwZQrsLjY2WjdhrsiHAMwmVh\nj289MTKDn9SH2Aq8pcgbc797NRoZvcxtJ0hD0yHoPpWJI+YmG128Pp/E0A/GLhZCfd9dPwhXprJK\n60DQduAqe0JXJZUhh4ziuj+sYnoQjandEFhZGa0cLdl3CZ+Tgs9w3FiHQ9o+KK67QgGrOT/N71tk\nr5TsA7eIZWGwk01L8o9+qmH2JnRrG+zQEEzjEK1FAz664FHDeqTSGHOpHHw4lR5PELHyFxVBRkqN\neIzgX9sV68iuU8n0DfDKic996LdsiexJexW9WLfH3DXMO8cwO5Abb6S1T5kFK4Sksh0sDSt3Escf\nArHXyYGyjOtQJXSZW38Ldjmje3CpMA/HYzl5aXruIhqnzy0L9tnGrNHIPThnvpk1CVEQA+1eMusG\nMZIyNx1nyaZ+GHA+pkdcdP90dDpHKZwqsPZVHf3kKHY0u1jqeTGchDgTlz8mFXE0HTq3HbzfKnMG\nY4zbW2OP4nzYZWPS0pgl2IcLCrPAA85AAWVMa6Ceg7mYLxdrMm0Ln/tOgzauSvkKI/ViZs1ahKOr\n2WeG7lAVi52tQpol+rSeDks6zGvoP+ePTUgYap9zCWUfTadF9/i3UdFf69hTsDZmD0YQrT/fC0mx\nhKHChOT2KdWe5TIrnbOpJ+I84InHqS1QLscyRhBYy5vOsM+XA5bxcpDSjulcZsRMdY++KfgzvGiJ\najuh9zs3L3sLdv9tCsf+elYA+GbduF7WdmxEGpEa7iKfjeJY4zU4oazPjTzVIdR6JqOFhIhziKmO\nsjU2IhcGEuVu0ogfcgl05hvDseGWlLz5oVJU6yXQSmyr7O6l1MRqaqPyKLBIMLYpXcqhMq0/R/ab\ninKhZtKEP7YnWJMq1CH91hQFThZ4vwmO9zVI9fxlfHMUoKxTIwsTHDXoyw0FdD2hfdXNZxhe/f72\n4Wkgp2qTz90wVlz1lYM+jJvggFVY+7WEQaCoHUu05e+ljIcie5sErvk0ueTOFywdM7iGowcO7d7e\nuhLyo+BAtsxpcGkBGtqomxgkZlyY7RePmNKMBesg6ouC4tmKlrOycTjVGljWsaY4mPLSKGFs13Ra\nGSwSEX53xGzieC4mFPwvJxIcirobSwW4pdubhvbdMEosfL6boa8QnLBz/2mETCSFBiJbu+Nb46H6\niGuD2cLAIuwbx8am8NAyM698phBwoPVElhRwpmZeeVpwbWfVWoMWq2v7t1oHEBH/VMcZ6PpzTcc7\ncp/vmAcidEHGZDVDjL+fl/tIQXVdSMRpJJlPqb1wALZTuVkD97DejftYg+7qTx0/nIjJtDAUI54d\nyMgtysL/yZlNf4EHhXvLz1XncBT5XlN1DiUVSNYQZGCUhU8UzCVbMCS49jY6IBUDzOVJnAOuPF6/\nHMf2nZcr5x5WnkZyCN/cm6ZZIkgwOgZd5I20Tk8LL0w1+tVygB6/J77LT1Th22rHnaGEDZEbKKIi\nEEMBRJ2zsprpglgMScv3wLsEiREmKu8lKuIYiP+IeHEJJgQy36vrSzm4Q3dLPSDLjqR8/ZOKCn3d\npgDbg5/XGvIVsThfR0tXjQuUKdw81GrqUM0MuYXkRjtzLsy6rMbTxOhCGtoIvWbkZ3ssP3xj2RMg\nzfUoGSj0PZNY6l9lCwpnuIJ7cWGYs90MGL8HLMAfCPGIPUtm6GGY7nfeHS4KIjKA4RVAXWqx+SiW\nZxSdxmiYIP/Hvl51ndadC7pc60ttuS06NeYHXDOO0S3vRQ1rMaA1jakkTxF47o+Jzcza7CiNSktj\nEXb3DfuBJlztT3vvicAdnTOu20Gk9HYImFU+V1l/7aGLrH4/rSSwmdoczLdNzpbPA2hNeLWpRTPd\nnt4lF7BZRk3h4ZwjdtQp4S0xFB3VdV9jJvtgJicwK1dzB0H3zAbJTvRTzN46JGxdDXOLV9Plgmhc\n3lK7uzj1V8wDQnncaKGeiLzwyK94e45MybepGzrp3DoeHM8I4HgjPTcRt7qL0nPWX1LvcGwaMdJy\nk3Z7nH2hrilPTCD0VbiNxfG6Du0uTixzYusHNlfx8ghsn0AHQec+Qe4dYvyN/8+uAb9ZIGOJPbAa\nwK9XZk7oblrvouXXXFBfbzsjWrOWnX+GL7ohONrsy8kJjey1WHiulVvVwSLudcs4F3gwYa1QN2JZ\n8bRw60FZz56Ne6LkeKXCfZOh0FOiTm0cRwrzrWUMTrM7CIT/YXJuJsqr/0mw2ZZ7NBFqXHLsxihZ\neFB61egffeahE+lhoLQpiZs1e33waVVLxDfY/evj3FocdMGNoQMQK/nWPz2KxxQXBtQHVZOjNrdh\nsx7U/Wnia3HajdqoupouLpo60fgJXgzGUlw8Nw8xfqgoJVF9jI7VDkdebQRUTW8U7XSVXMXF1wF9\ncPiYqw99dhUqF/Dqn38W7ivfQ+4pRrdLESpuSJ3k1DQGXMaSrmVUTgdaC40qBl3HLDKLCCHFiyw5\nHaHsZvKQ4IwKZ9p8uvWQiNYgzB/dywmnnWdg01VvpSWfMPsaIXN+TZOjB3x7At3FLyCvqU0KDBcP\nNSLmiavag9CucAQ5X0a4CbO4zq2rHFvb84VRgV7X/igswCO86CPlH+OTjiXC+98PSbQyv3Yt7yjN\nwu0vs76r90T1nhqxFoi+c82OdInCNUEyQIyMJJH1ub9t6qBHzXXy1lf2qd+S+lqoceDEDqwwc46v\neT7zK9dsLyQ8OVg6qprjyOXF+KPyYj8pvCgXrWzL46iuWuIGmQGhIjY5ctoN0taZPkzYnBpexaSK\nplkhhI675tI07CXRNHAYJ9V4WU04ItWkJcraQMbPh9pQd9jVjpeb156ehydxPUL5aUTpP4UWbDiQ\n6v3XwS04kaMW4C1S73RsASKsDIGwDxpUWkE/Fx/xjGazT2O9XC2tF/HfFu09QnBwAEv3xgxCsSgG\nhVYJmi+uSU7Pi0yk1UAx9CIBJZfvXCOBSSeqfbZQznoPl6VUDETyAtFWk++1ikObWg/mxDHhHMMs\nxxa/A/VfI6lDgdQWlRsDVfzhDYEuoBMA0A4FWpgfr9hkcsI6UjGOSyN8vGGPWfSf1kjG+4Hzkofl\n620EcndQrjZ/dZvi8FeOcveao7y3JpYdSlF2FJQpUfvrBcdHMu5PHvrjgysK9rHHuKLSrkLBU8/s\nARpzA/e6gYZoH0HpWEYwD48tt16u8tRvblN/h5H7g1tmLXRp6u77LuzB8AsUtEPspLTA7AjTXJ6g\n5T/wROxlhGKoJZC9/+si0e86GYGpR+iim1BlYnv02qIx6mX482NtCSam6G+6VbYpVdyX3t2Lm0qC\nOSdh+hlPvlsHAciO3AbGMXHS2MJMV7JVX9IQvBu7D++EeTrzHGEBigjDN2R/GdKaq7QBpwQrhv9Y\nQB1SI+U6pyEG7T5xpAw/BOsMczH5JwLlaSrljxEgzk6CkjR5t1JlKntP1W2tc/QOTiNJdAfLDJ36\nJcEywJ4KCMoDcSrl8NTApf71iPxqy38aNuehOuG8CAcC7twSHMW+1PdIlTOX/JGw5ydU0MlRxFFM\nw5PBJ2kA+0TPwLjn//9Wc/Z6jMvVS8yJ1hSLH4w7pJFT5ZhBUQXfcZMRp171i3T3Aw08GkfoUZzr\nyIQ6aItW860T2VbybbseJ+5ksBUs++IuROqDkR7JXmMXdZYpF6dcioHHU7F3r8/PSCZehCbLX8eL\nzeS2cyP103uUmRO+7BIJydB88XMvw8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5BPlgv0Ysd+eSR+SctxdgsIGfUYDU11OM0zbr/\nWzLoM1Oq+kbqKRimCRPQavzTq28qw2vNV76NgLf+Mi4voQMXDED873/xvIVY9TQsjopYhTTJgQ7T\nDYAvw4caDJO2T69XIDBCS5MwBLxZp7dspfoN/4oGjaDljcUVf52RQHBD0be6K7+UgXh3e722sNlr\nGIWdCtUs2ieNFcswyUkhb+J/TQcA3Q/BQjg525rpirxX/935A7IqWEBSrSJUyQ6bR/6RI178+VoP\nb+nZ31dSV5cLusb3bgBEdqMgFpIZQ04+C2h3rT66h+w8lgB1i8lDhFJYj6Z914taI7u7XrL9hdWk\nnS+oZs+XLf2TEHM6XhtWY0UfGTB4gk81QcHMPBR7FSj3PPjs6NfrpN8PnEta5+m7Bw8yWJ8hEufG\n6GNBPRuCN+ST78w728pgI2Aj77qgmO4bfF2EIh3e6jnqiqqKZvpottUU+wOnw0FfbAyzdkZHKegD\ntYerAldliSEsyacASt5YCPbQ2tBOlTdWlpRKGK5jhAdSN6XMihXy+VfCBF+iu55vsDQpKODwBf/l\nB8ttqqB8/6nZfoXzhq/Pgq6dwlP2EvSsHywtVGlAv/1vlQl1lWqIB0YX39bQW0bL61gJtp7dIyJN\nGXTGXiLo5VjnKbEblEGRVajzzcIM29VWYOsxCrtzGGusMJRb1cdgRqy49yWsGih068zm2wuMn/fg\noAhj5GcjxA7ozuv/6so6Csemv4QKW0vWEsu5LBWrPlIP4vocr3NsGTixATur/amAbbTeFCIGYoaS\nSjoM44N3wDyqsx/UFjyLFnf9A99T+by/+5RHIeoNkEG8Ghax53GNSvtO42NXxbhJJmixJNswdKVg\nrefi1rMLQQIDBFMeXpZctKcGDYHnTa6qWsI2Xxz8s44DR6MMt1MsroC9xPrPDUdujxc4s4h6R6Tx\nb4avq0fk/TlXz4ay7Wcgeldi8emJ5XtM/1MLpbTI5e+rGvBBJZn2f3R4FN1XVaK1leID3H8+MPhr\n72Xl7ZxK1k34nugWgEF7KkgInRkOy08AUeTUF8rIEIXHpXm6PzsCJIgJgNh9PrfxDGoh9XFHzHPo\n95su+nlqpTVGpiCjjD6GZ+YE1OZPhae8S3cdoeM4FgcVXsF1NP7PIy5DJ/R9pQ27TJvx5PdeDcrq\n5P4jynMDt/WXG5SmHtNJV+WD0q1vQMIkdeSX5wzCHcBDiWVqjER96rpl2Qwbdpo/W367GH8KPvUf\nAitgUV8GOu8TN4BBXonsdv684d89itGwwRGrKuVoUZtt+y/SwlhSTwA72MH4a9QWBe/jZpuc5eW0\np5DSHEiITaA/lyEk08vTfYQe0gsbQTg2dvpUbshMmvAWeWd6RoxDkEVNp20ryoGQJ9utSaixLGtR\nyKaaO8q4EwLtIjey5YKY0a/3Qn7OLrNo1W8xkOTYeRhC5E+kCtLKeve2NtgVQaSMiYr6SuYyk4HA\nTVxnfpuozhoMblkqkkj+JtQkbwJuxCBzRB8cLs2Xxd+Aul/LIjAAr183pTtklyhzIwnfiMNLW444\nc0/9McUB7gL+/gks92ElnH8khm4fpLUp/DwCEFKDend6hDZ7X3Cp5Wo4svtWu/v3fw1kgz6M9bUW\nJ9A61uWMsoS2wRbMsgifchp/N9DMHA9++hvfdpxBqXGOIw0VmqNAmPKrG0X4JEIU/6SKZRNNOG5E\nY2uVsHIfAYgw/4n8mv2fF7gvKyUSoHTbURYbZcKmmVv4q64b2x9J8+IZx6XZmLLBU+XJ5NxJsW6A\nTg6MU88JjupiEyYLylToCFKqyik7AWoTVJC/p2Xrt0MiHG5QRpKPsfMkhjb7gBS2PrvNBP00ee6P\nVSElr/CEpazyvPPZIuF6u6ze/u8Zhj1w0aneXH+14KnaFc1B1k2gl84kK+7MadGPCJxFy0HNW2zL\nsCOV74lcGAUuSqkLylCXZiiGtsicrnSiyTRstEasEvEkx+V+kbd8R/wO9Y0EQ5a6o3IFIwJzO0sB\n6KJeYHUhNr65982JC6t9Hoxt6agDzUeijvPjWMRhTu2CK0iKcmGyXsVdYQgI1YfBnQIOTXJZzY0O\neNTS8hH5fIPuWrBg6F9lwL5FPZd9APt5Wkv5fo+RC47fWbhQBmxpdUXF6HLjzGuq8GBLkcfkzGC9\n/ArWqnKORSiu8GUHX6crwulCXqSvYjc9Hypjw7TPuTVvnZKSiPHGRAaREIspT1dEiZHFaDF0Z1mg\ndn2tK03yOJ169Ud0SUyzXsOmi+JRIMM35oolbfoV+uW7YomtxUzbnIzt963yB2eN/GuMQQYpXXxK\ni7tsbvfSJNE3WE6xrJIq6MV30YgsQdPl/2DyCy1oAu2HIdIBAHwXptE5U3SFKDIr0aP24ePPJFXZ\nrY5YWECy6t+ORaljfEW/OAWSt6EKEx9LBJSAHyZRXz2oMrV9qUImx4xa8doClkt/i4zWMwbCsT3X\nDLxxvqAK32Nc+7kxkOtjbAYSVU3E2fMUSQV8s9CrmI/UELunLGXFd6HE6q1HgjODgnM/ZQ1vJcMc\neYpleSccQNtFsdHo796N82J74xCsK7uXVn7Q+0I3tJ2WDwPZvuZizHh39LkRwQQmdVDc/J4OSoky\nDsVgjI0p+2PatJf8L9EPyFtQmQ0JApa5FD/MKz1u9czJavCX8cEDPvGAGAczTWw2uWYgANc5p4UF\nl2p584ecb9ssVvKqGcKk/YaN1QQ/43AG8ut8UtlQxmxQXpjZqNrY06Vr1tuRj6mEjzJ2ijDFBdCS\naSlPbp1cld9hYjIdXm+u36IheCLV4JAjyQlfENRN5ctVJQ65A34472DzYIEMWaOevpdz8LpwMDrb\nomcM9KS+IZcT2FP+FpPQGXx2tGz9IySsDsNw9FmyJjyPSCVhpX91n06Bm/TcIbWasCWgo8LCvra7\nV8A8lh1qYPYC0T6+PFPJbTz/SA/59IjS0EpwAz2Nh08OLhek4atEM2Q1fVVNml9qj3ecByeuj4vM\n2LIxdpGoWAiusFpbmhQKOwqw3GAtXMQj4isIg0+uLjC8TCGBK06j3P+QQH4sSzR+yRzn2vthMXfp\nHGb6shHBzxIUcUgEvXPlfRUKvuVCRqjv8YE1eQQ52QGrqgudZiRiaPKFJW75ddXYlOlBr5ZVMSNY\nBWGoulXjstXKWx+SJs7Bzm8Zm8MKSf44HLYgw6h5r1v8JFtiw2tMxNvce68O5qF5+arcIB/4Tm5X\nCNPdJv2DyMnAr0TnFgqM/vhYPt5dPqDtSajak7mXYNjaBRdhDkenWytBOccR8UOfInk06KmRCdYn\n/DU3FiBgJ+AKdlDf41m248j/KcteFR07COdXIkvQohKy8egbvc4sTpjgIaaETRQ7/l8WtgtIi0BL\nd0EVC1t3zDqWlEZYBBZsuXzC4ma7BvqOOTSe0qKePROklF6IUVpmiQWQkH5aTETOJ9XJgJKKFbJa\ncmUpaDWhISKweR5Xv9EZmeowJxVP90+N4JBDhfZZbdtK5hhYYeAb5qYznhkPD6kgi7mZJR+kxCOx\n4nQCYaSxKwdMdyNciGoev/CclCZ3k/Cb4NSfadqiJAkCSfCUnbRFG/vUC/wICZJki+/C8JunjzQk\nJ90d+klizyWMuzr+5bYf+vIHjCGHOxHArWLAWPkRf5WH3vlGZgTnVL3f/fMk832dHFj6UnGUj0wx\nGxP5gWFpwUro6Men/V8AYtf1y7nW64E7F7fOJBOWJ/DlPBSYJS3RCBnA5LaskopBso435CmmPC1P\ny+Tjs0FpULQ69Bf47RHXv+V9AXgTK12IdFwqZCX6euUungXT3WuvAIGzkz97OWRGaGqetAh1ecn6\n4yaKh3rC82y+tgJYpWt6mLdj9raleyQBJ1uFwdWVUnsf/+dfEC2sOn1IWMliGEpBZWCKlOEk3QQb\ncZMwetiYbzXTOBKfN9RZTF7aj9LkbqS/H3c+qQAYbplKQeCg3XHop49pc2+fwYD49dkguyPfUHZl\nFgbzOZeQW/j8lIvrs75f1kG2RXfrSipSYqvqGp8SjPDvHL3wd/NZ2mG0LHaIG0mg/ciih9+qn7Hw\nEXPYWhJFOswmiLgdoUyiK4YBKlVLhb6m9I2hU2K9HfpcK3JyHMzJbn2I5SJWQAE9+b0DjyUKAj6j\nMfHC+a52JEKkvAne05p02nnaGk/1MXvd5CCXk9OXdUma2uvP4SW0e0lOUtY1DfpF3AKGUjyRI87U\nRlguRxedaDyIv/Er+OyN11YZwEfvDi4MqE1o816W0+OeL8tPBCzytBVnWuhkc9wnijE18uqCfSb8\n8odutiu9uDFz8d+JXSjV7LSOu5QjouGbsmIfe+WEt+7vPkB2ULnV/sA3W37eHvat9uf/6lrXbEMB\nscgvH9gj7gfnVY66tGVIvLl2ICHvsPIYwO08FGz7lcER3h8no0g8nelO2qKdHYFkKmy+NhSzGziS\n3dAISETXF4/ezAjVj9/S1GdQwyuIqwttvsZ762j+iVf0dbRWt1NVCi3xGOH2vR7Jk8FnjbY6Di7S\nVQa2Jf/A74o4lpaemRlYMfwpkIApjX8D3se1h4buv3OnK1gOZjauVk5A2Yng5eq96IAK0ndd47PS\nXmvIy6nR5I1RRn1nIfdDkTr3Lng/f9q8etL17YXrxtM3l+lRFl+GNfYKjTcjAi+B+2JxcAtZfDxm\nW2lmBY0AWPm90geNxjKI/KGTVLHszKI/e5HOEUeXYQKcif0hMNpubhQvtSPhsCZESv1UmtIzfbq1\n9k58zlNq6rXzF8DP87ksk/vrtgHLm/4VTfbgjXg/xX/A0rePI2O1TUUZchLtgrkaYjiYR3AFi5Zc\nACktDnPXn3jFYyiRZaduSkoob/bZ/aLaWKGOvsPUi8wRYw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protect end_protected\n", "num_lines": 1194}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nSS96R7wwFQ/awBJYajmb1uyxVW7Dxe+Arw4icTEGgmn49jUuwRsWmvS+gH97qfjXRux0tm4UqqDx\ntyk4/LtkUg==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nA+Z7s4sYG1dC1S/OLd5onaqChDDoqDKxIH0wDyu0FbLuPuh2W2mXAUgA6ygUDyPxGR1xLs3AnLf5\n3U/y+fEPvjbByjgXYRdoaB1qwaS5zdnv6ZIRFF0LC1q8dbQM70j2RSMZ6Bs31wvj0c4OYXETbX2h\nDtNML4rTAuRM+iAVpLk=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\np880H0PUjXmUBTEI3c/dRMxRl/IL+XvlWrRVCBPlh6HVE/9bghIS/wvhgyOQ1mp4fyEUGZHgNQPX\n25j3cqsyfDCSGvVGO/rQ3RvIhdjhXBbmfxZXGx5UxofTc+/fp7JQTUPxhKk+Zmp3B6J8UpkkRaQ+\nTlbH9Glza9Jhze+cKRbGwVPrfS4Rk6pzkwHnm+iB+WGLJnSJVBVgXGfhp+ygbrBv+U3zrTXgsOb3\nxSJhSd/AWJ+PCYXQ27sJJr74LZYIQx/gg5QzMyTEoCqxw75cGP3bD2xXz+cFe0EdDkJH8sFvd1LG\n7SPcDQ9xmFnq3WPw2Ghv6DnJe4/yMXGiVRDxCw==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nej7XPZ5hWPkq70QwibQmqqDg1SWNzBrsMbYSFestfs+BR9J7xzmVMkCeifHuWqh/wSvpJXMW8pOX\n6HsD+kakwLfs8E+v/+QJqlLtBdlE3y4Pqmiw2GNPbakNzU8DMNQXOTe2AmJmoqO1VEHW3S//PRDJ\nqs4qvgIM1HXRfRRIgECiAHz7eGE358gw007G2YwbitOL3cveSqDocjOGV3jV5HepWYKXINH11Reh\nBMkGynjTuYTMJY/92mdl1ZV87kDCsW8+FHqKhOA1FfPvj1RPIfsKuqgUkZvW2pAYk5eBuA+vJEkN\nxVCniFgVwsrAdlKrWnw46FoutQ+m90CDu8Kygg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nLMe3TxzR1Zx/ByHI5/w6/SqhTVkyqBbjVaIILoDGOy4Y/RehV35vNFgESx+MOdmetaV1j08wlqer\nDz3Rfr2Gfq6hgHMLEHPCaIF/5SymT5AVpwhkmFaQdge1sI373fv8K78kRC8JGM9DNSFOClhGJDQC\nXB+yastK7IXkt+VYwM7nXa0xSHywkBIAeivPY/BwBX8XfbLzv9zV6rh2SAW84YIp2jb4kcYm1Mqj\nYgWPATpqkdqbBqii+7aziLQkRP/MSmF7cT5UKQiHxn/Ns1lKMenELV8RgHq6jdkdBs1uaoi1JQKQ\nfqmUv9kYnWWDKWW+rc0V9APlL62HYOLDnbo4+Q==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nq6xSi+pTFm18WzGq+65YbFhiK1j9sHarfxu6mSyjDniOO2/jW7gfvXXrv+B56wzSE9P0346jIlVL\n/B4h/Z+ac0SVqu+wV8pg+OJDyBvWhtnNYZI/7k1BSUWzzR6flVJw+lEcue42YZ9yoX/3JUlz26Zq\nBi2/4jMu3LmppUWsrAo=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nOQtIJXostrr6X7QDA+MBULvA7CIKk70kDF2hMqsQ2sI/8QR9LMuap/TXdjn0XLAZTkxLKNLqD11T\nxAlasu0+U1hOXgMBxoOPU/EUG1bM7wR1UF83Qhigm2Qm0c5xtp78LF89EgU/YOJtHjCcMSpExbax\nGFg3QnSgmE/7yqaeLbA8DKDWxW05qT8jxOwcDuZ3zIdkL3n1NxrWQjM3U5py6K5PTmC+vcoEptq+\n7ZI2ka+SP+NX5R9IadM4lpUB6CqAxroG6xIUBcSx5r2BQ2CrzH4EcZiQVNCUwYx8tyBREplKIsC0\no21e6uMpC5pDqqckCzSWGZns3l40rTQV8PP6hQ==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25328)\n`pragma protect data_block\nomU0F4cB12yO2ZdV+t8D/whbbDWmycZw/StDHYdtlxBQqHD2Rt979k5WQq+7+dcCL3+IPJmrHRVW\nGmVBB+3psg2CMKD8dWV8+f1duqdQ1ruc9IDTn3kyrMv8WzUZr2BsXVR7LoT/8ARttZYBzN9SlXOB\nIu5fROLcXGXIC69mZclXZ3kqw6gKbDdcIPTYaARyazI1N1JT6MpiPeX0B2e9dgibZS4NLoFf1C+8\n4lKKRF3P6Ms14sMsxNaM1rVifA4iQ/Ak5XeKnn27tB72RmlJm4ojRMRkD7cqreK6a2V7DXB0zAWw\nD7/HzKVzqh1lZF/69Z53r8BDyCI3oRPiIo9/2kpnZMcnV87uI6FNq1UsblfLwnFVkv2E1TroogPQ\noUVZd48nZKP6G3hipN1IkHU5wYHpG7S1px7d8HSx5vZKl3pFpv28aN5BxEuhvJV9FBghlpwG57HM\nQYhtJs3QjvuUXcTQo6mt6uaJkEmGMltqmMlwvreBEPDAzXivRCwBt4lZjduB8i1eYRSuMv0nI/Qx\noswjFa0lFt6divro4C8AxVAJIiIIEzOrht0zHz9Ss0+qCELQPEGk5lc3IDAHgjbCPWmObsbEidaS\nx7t0E/Jz7yoYsInuJGfETjIEklMYJJhVHJH1GgtFiwCDIXtjIG7Sv93vg8+dTBX2fVHjOswe3xhc\nlJcoB8yU+RvIb4FuwVwKcNAPT/0Py8wp2Pis/gDA1dsSpGioBjVoz90+AOI7ltbVQYEYqMCTLtJ8\nFmzXBx2tt+iWxg+co9z8phmO8gLRzjKzWoLbGSZBBw7G+/VWR6G6lGo4ZvKAtDdFvu3H0Lk06rJW\nTeOr2wSeT/Kd+gQCC8o2Cf/8PyI3xP+tzcDP+L/jkEdaFrHo2Z7v+LzFwcprHqiZldZmlCwK78ks\nVjmAujF9tHZe3H3Y+tr78xko8hSvvPzSklNvrskK6bA6f7i7LNvPXEu3FV0hY4/9kDRar+ls9hff\nDSRygqt1uAtTYP/7REZfujc+wsurY+MbzHHxp6jq3EOwSgRyL2cHXx4Vmo62A7wgKyTWk5EdPIPd\nr6n847VMqI15sXBo8nYyLWEkzrNVtVQEvWpeA5oqeDEHaduoNXyXlyRSwDv0duY7A3m1BAFlglvR\n0N2sjqwWzKhYFj5Ns5HQQBtHh9Zw21QqT1laFBjSz7cAsrFrpDoB8SDQCefHnKEzSHYnfb3WRQQs\nxCjXR4TlJRnLnZMyHVfyYtH7USi2/l9V/Yrd/PO4+NmUgdIxGbToTlQIBx5gigJGs0XoaWvVskwf\nNXlK3UaoOJ85tDPYp9Ejz86GyMYerWLlf1u9Hn1BCIDeuOMqiHVvTkLMoY2uQf/g9NOChlcWM+hW\n5AZH9uc91mLwBKTrHi1k4EM6CVoDhS5i88eLGDj7WUosHcAYcjaiNhkZ97tZbVK3yKkVFEtdjoL7\nh4Bum8rQwYxHNx2gWytbEbl8qIT1k0uisTMGRDOmApn7rixESdulVbMR9qGrvrPLqY8EtDH7jJY1\nlS+kchhLcPKLemI+liKF7h5VSUNsc+PGwK4Poi/2EFa7XfIpHc8E6l0gZt+qwW+qsA4aH16FPrxe\nsPlGeRTRqQDdA2OwzUgpbcvKx2JTx5qswVjgMW5mHt2EnLjW6SHvLc/Vzy7fr/O3kiV3uy4dyWGO\noloO64jspiFBJnLbb6eaTNqyAvbpj+ZF/Bw+QrCdIb0EdsWj9GmUUmsmiWLI+Lz81KUCzEc4H+Hh\nGglDloivAeynD9N8HFp8OpgQFagNeWtfAonUqCDV3B+hsNXo+x3Nj49PDKdY5aesqlaahKr1fAHT\nfierHFNbvOT41MYGioKDQPLwon8ptmydyahnP5MmlDi3knIlULZ8de+mnbKISNCyvzua9eAc994K\n6B4Kj8/swf/hAOZxTJ+HqtpK/DgmCA9FiU3JYIsSB3rhufuLP+mFayZ1tK7d2t3i+FZt7TbMxR3w\nuZgEVxQBf6VU4vQ+r6EHuytjSggM/20/7CtQ6JVqeRD65+i4n1E7b/yeCapiKyLEHcF5+TolHg4N\n2IN8M3DjZGThrN/W4aFXsyj4YqaVr87z3w3GM8FGp7rDv5JqVehoF+ATrA0OcYRvBVPsgnnvlPOg\nWuMIIahHuKGHwW50zPwsNaUod1E2fk8gLhkqMqiE3SQU2y1T3hmK6MZXN9GSwJ5IIw5eyyO1FWGr\nbcgG3rsONmih7ecMwUp42jLQ5vSszqiQ+yHXepZzC0e2VcYZhWWEGgQ2qAP/mX+y+xDfZ5e//Dp9\n1vw1SwFlk48f3CJcsRXrWfDocPNxPWQEcFtYDHSPNwEAWpRDWrd1jQdLRZ7riiKEwygrvCTBTy66\nWshkAAe+V5my9AeXa0Ml2QTFJnaGjonlt4LTbDpP6lrDNO48TxYvwTeeqfPcLaHr0uKQt7YHP6Lz\niQFo8+yjuc0zEfQzoaETRrimF1qol1PWK3Qpfih9XrskpouGoT/zEL9vl3TEyQopv4PUZPj0Ynk5\ngLrEEhd5zkdYa0GWHcoa4Fot3qrp3UwIaXp3J0srL6FzrCXbDBf2Mo5NN+P8lk095AJm7GbHDjvE\ncDphpGwBKdvmbBEGbh6fHIOHTAhf+Vc8cPPX6BHmHbNOHZD0JlWZppGdjhHNpBNPnIBYS3tfqeR0\nfpgTvVPYXHmM322F7ZoQ/fwObdQAoj+tk3q0RroBJxQWakMIeQLVoja31p0u56OMldxuQgfF/7kr\npJIVirx6SAQcDVwcFSqf13qBuM+0Ol/D3mNr7ZjwWtpprSUZlH21ailV+zw2WyvthkiTp8YWVQBy\n1q09ZacNze6Y1ElACgh58iPN4woxeuIgISJzdoXdZHKr2rmaCQ72e80pFTsQDzTlRLDVRkpqAnDC\nxN+Mwpe+Fkm7f7w6HD9kr73bageDnyHcFZXpA468LRFJPWYg6wq9iFZ4TJAxrhk7MUFsxJtUscnr\nxLex9FDXv5JNgmR/UE/CD/ih5AN+x6gWb6/W3lszhJtU5l4b4IoAIBzFNDGa48+PO6Tl/fTG2S7N\nNWLwVUe5S3/022dgOuBphepqPGBaEk9aWfzhttADsYbd+EEH0DLjYEUNdOy0L0wxxD+dTHWxJZSV\n0ChMWF8mHSAFDH5fO+Hy1cRtVcPIRrjGMzyyvJjDaKoXzOfyN4HKL0d2Zjm/gFo8lez/ydTkt/CS\nxYar4AEGp/BN7QDDP5IH+BMU2l+zrhxqwQPo4bLd65LBxuQDXhUginwDEo82bBweomEKB5ujxPvH\nkuKtvrIWHrfWIsK10kpV2kY1erMU26KgDhIsF6eqON5qRijRBS4IWa4trUlIKxFe0tR1G+0lTAnA\n2b2zENNs3Owv+ZV3WgEeJpcYOOwbsG7qq3snQYse5j0ltcLyBO+dYgzePpcE55rg3YWCCn4hjKVN\n0vSNNutZw9QqsPBhK0qUZEvot0e3Awajv6HKZPq73c6PpUOaaFCTRl7V70cOsdlrUwteXMQJV3F3\n1Qszx9GyIwFkBAfl5tn7jsQzd2tUlf+3rxISOSF4by79j8FsMlkJW+++qk29OrwkSW/XexL+uk5x\nDWSc2fgm68pygKu/3KtuFKMEnPktko2ej3qtKmVvRPolck9fuCxtkXDMY/lRA/cMCbVJdOST8PNH\nltx8N3OjAHjF7qztXIGEbTgETs6qdtIS8Aaec2vMw8sZrpkkrCd83yeYgg89AlK1PMMWYpKw37mq\nTeNpJu+HCa81ry2c3bCvCvpF74Sll6oEliNJLH1QXvcQWLSiz6bAPjPvZNysBOkqwipQO7FIFujc\nH1i9gsKzAISZqDQ4COwcFkxKsZqQ+3+9LWF/SyoBGXGllUl7fn6Y1xtEzEcb3vTq2Sqz32OVeKu+\nLWl+IaE2DFDUpnM3NlaxYilLHTm/OtF29z+8txLIi56qb1wlsAsobeLHB8KpgUKsEzE/Edpzr+k4\nykpmm8XtbKx+rz1FpVqtx7C8k4J7ebUClTt9AaE+jJujIyeR6IIX9uzQBNiB2+o2Tb4XsG9P9SMb\nGbauD0yjImseltwlb22KCPcxWEUe2/7VOir1DkE9/wbtk6Q8eF02TJxwTZv/epiH8p09Zns7H33/\ngS6CyE0neXPK839SOHGZCftWF36xqrP1yS17/OA6PI3s/CTLfTs7YTx2codFR4imZz29y71VIoEB\nxtUhCuqGobdRNa2lmU42q3mPHQLOU1UisLPDeDI8qxbUi5FfabTKeFW8+xirZfgTs10x10q7KGnp\nbd0QGVaqot1rOHQ0HlG1SiSDeBp+s8HaYAdx9PmjO4bwDtiQdZ0aMJafmmYAYDSiRxKXnWvwtwJv\nkDDIMdqVSgH9shOr2WCOVuD4hebJ4kxzvxLQQYK3OsKY1CUdS6LMg1EBJ5fzEPsGHi2w0Eh2srkc\nkFRoCpIPylVJ01RZzkM7BHiJ7SsmbDucJMBZCFb8KFsmi6QZ4vhiXdTczreE7AXWtxd2/bUiG4vk\n+rP8o411sER8+1SpV3MujyYSJIwyGRA97P3vw8pDfsF+Ktr4FQ1M5S/UvCCDYU1c1fwEXhRTig9x\n8kRj/i/4u19Y7f8pW+4TRIfXSmqpxQLvlViUn89CBFT6NLiVqBHxzowlhoWrhi5zpYXxw5SRXBPZ\nsPxr44yLN8Onh2QMGqi/H00xNhG5pB31BEfTeuisYQiVZsCmsDMNFCZSUIZJ/+qQK5aL6ASPafTH\n35NsiMMmEtBVPcun5MPDeCi/5Yak2R3SSylLb62ucpJCFEiNSW9XXihs4lvRiD0m9Q35QHQaqlWN\na8FAdZpgxcb9I9bO7md4qPV/TFLA9Fbfw/ttXdf1LSjH9WiYpKiNsii9ttBH1On7jV9IE5ZlK9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G9UB4lpGFa3EvQQylVj7gEIapdNZX+/KvWDE1Uw+Mx1ch19lMWPerej3V2JsR60z8FZDuZBI\nrMa1yIuu3scJW/W9+zxr1+L71th+wD0N0930H0FW77WXKD73hpu0itMeJl1kTLX0C+4du/oXwiPP\nkKFMnSlhnmADk5Nzs4kXX56QHHCbRnr6eMuvZblXK0EZHGXSb4pQePS8267+j8iT4e78/dD60NSn\n3kcUWmiDaD6B8DhgaHuHl3jgJoT7tgyerSxV1v1ywnD+ooBqWrUAsYnJXP35pM9lvw9shjKGAAX7\njCObOS8VJZci9eTJcmygBtQacBP0AzSh8d0ZMgtsEerarYOHl0VaqrURAHTNs1zfXZ6atogVW572\naPtBaqUaUJB4BnKzRoP+YM/+HbN+k5jn6HFPg/wFHeOOsIPE4dpfWM76Fj9OndYwBoJrRfjLOqsu\n4QbnGR3BRAD5bq9p9CIqMna7zaj6r1Kh8y3bz0JLMChWeZWjoOnjrSOb3n0S0OcprlGZwIkSPhD9\n5e7JOYw8xSO/acOGMOr7XhVwxsvj5N71yDY9oIIxCmp2i5mKFvjdFKT7b3ivsMqpU6ooUNL1cB3B\nct1l8a3kFj0xj3Vjz0ipLbKBkR/JC+iOtZk5LGHDKd1jaSTRl9nSuO+bV9kLdDxwvYHAm3PP+PD+\nzXW0fPnQVICDYqkZG1xto1it9QOrHjy2vBNh/0ETekywdX5BIejkFzloAAm2ddh6NFnynQ81RPOp\nB6Ei5sZhxqlniMTJQNFN+PNXyW2lrwNTLew+TNDyj9rIZ6ETik2SHQpVEwsfSVmzfDCWqm0kta9i\nAjvtzWWnW+IsuGEsEL2hoy4He54jqi2mtn5jgFPt8o/zfixB4kuNpqBIoSoWJqkPuB6IQ/KJWlFC\nszg1J5hey/xx856i3HzxFJd9mVXALJY1cvYVCa3JSMQEP0sUcICrI0GoEYQ7pi3w1mAa8bB78jMD\nrfvLju0deZS0V3tBedhCRm9yt9XbJCp1F+62+qLtP8hSRUC/gOs9rvVULoMDmyAEgrf1nsbcBaRM\nQX/2dEMQzcBUd2mMjdpR0nCeJ5oxvFymHSOvlBYVhLq4CaROMreoChqIuejDpaErVFOfvu3lq30l\ngiYyAdBlGI+/GenmbO8fLK2EtGigHy8pIzuFQvaj350cfHLlcO2jHrl6UbUnMLdM/S+aBXd2Dg2E\nFKbI8PeZwIJrbP6987aJSwhWKLNgMNNjCkUqfYJ/NRB2eSOiC40TgfhufZuYh1fA7Q32tdQqW/Xy\nNv5slA2fH5SgHmwS9Uqxfc4jvp7SUOc7EToDWJKkVHzNtxfk+PpKRbG7gledErTqMBqWRm7rkwhC\n3jsX/qzzTT0uawrfLEtK5qRoYxdoZzMRcK6ix0rVWema9+AZIkOkf2eQ1XIts9qHSuNKuze2RXJt\n7XTiojoorg+kyigvlSv1D+o8cAQrd78YiWvhEj0QphJmFmC6jy6xpe/6eGwfy0a+fsjgc0ZCdt0o\nA4sV8eOhNsGrSsGhMLickahQrinsXh/8ILbGqvKtKAbNVNLyJk+6w9BTy8HoYPwRccXIahYFpgS0\n7pjDe1Gyor2dlKT72Rs9SvooqSu5tkPK3AFc6o8oQIzNtMx5dKNBHmDyeQntb/GTk8d4H6TAExAo\nsrSIFYwaxyXWQsgbStzgbi1/n6R3kvBFDAMD9ttwZ4hmPlj4sygAgzv6c6CfyuMZpH/keY20cVAJ\nOXijLo3hPgVD0p4n6FOUdu/JYgrTsHnOzGhUcEGws6R51FcuHxqXcBA57apz8QY31Jr8lbuhCmpj\nTNvGlI0SX6VE/NSoJli7V68oxvxAR58toqGrfJU+/YwnuIenC07xeN+mOIKyGO3P+4F7UuNDCPYH\nseoQxJua5/0RsZTGA9NHNAdpXJzze6l0n52PzQItK4epiSZiE7ZHGKz1YfRLvAFBrpIT1ArDhLFw\ndOB1iZgy9GNqwH8pNMvbfuz/+FeP1oM8/SIDdLSv0WDwM33gsrenitpREzjdByQjjFRtunJe2kyk\neQ4GhszWY0Dhm3qNNUlvlMc0xXvIiPl/w/QE8JJ6KgtMUdzTXgWd43HK+VjPyg1yJm9SC1+o6xlP\npEt6awJB3VCzxpu7jVf2OMsrQjiF4W728yfUJwPQUfr7VR2E97zmjsbiHbf1fo14acawqG5MHQW2\nZsMwfep7N5NAIX5rav2q5ZC3g9rfOUVkwnvp2F1HSNOWxKV+jJz7B6Xb5o+YhzoDd2Y3u9mZF/cD\n14Q3uTuV9Y/ufXtAhC372DYtV4oSeLNkdvW+eOTDr/k0eKWqnidKW9xIeLpCtmtUEhv+gSYNMZ4u\ndj1KJgp7/bMQMYReDRLQJIZTkcDnKvrEc8ObcYZ4GV1OwvpdWTtkiszhRjsUWD4YA3ir81byw1gt\nZKff6VWwZakXMdmcY0gcEhHqjdELSZFplYxqXNFX4LV5x+7eFjRz0S0IbvsVKlu5RD/Stma5/ZA9\nG5dOyFeuG5u5jQ1wu149LA4HvM0m0lg8BEG1MMOo9vjgOYEgfRz3sYRtSz2M+SnoWlt+o73somiM\nS8u+Sfiz3Nyg1GNSWlT3LLhfK8pxIEkDKkLPjRDkvjsBfkIr9jYYnK4PjvOHmKaPH0ZTSQzVm4M/\nvMz48765bXGQd4xL77svOl5rK8uyJoMmyQq76t/aXV1iCMNLgIiZDHa9eodbgsJTeLDB92bf3zgb\nkHDPhp/5Y96aH08BelfvO9ZsntgDvmOi0++IymB9PI2l3eMx8LjleptsWU81WDExuENmSPn5b9V7\nww0PkB4L+OrwEVDHPmgQvzOp/S5lY86506IzyZk+EFaoisJPL4Ix7TXgo7u2wHc8Kssp0X5YZFj+\ntUOk8kYsuNRrd81CR6V+ukNkM89t+W4aw/ajKDTT0LmUqRhMGQvh2hOqw9UksTCdMr6/WgIz5pbm\nKniZXfCh3cMZu2TysZd0Gmg/MbZ6ohsBnlsnrft6p/E88NNo66e9qomw1v7eVWGswqmbDwalyPv1\nxBVjkSxrxfkyLQB1YfibsLY/wqmdq7CHSlB0eY3D5meq6O7XDf7jcjnKVJ3lnx8bvmKf6aT8I1cj\nHtPVm31bdpptslWZUHTXnDl5VYP4NJJQN/JJQ+GcRra/Ik+SxQ4vqTeRuhOtQb3NjBm4FpDEKSSH\nj3/IaA/l3KdxVNAbLRenx7/pEnd94HpKkLGiH9J++D+WtogNWlV5Ran0qN9ZVxtMgYRQ2CfhS+M8\nOoVZJYYvVWBFHmhz0Mng5gkK7LODy7ij23SNkqmbfMzeniulSE1jAHHSIgqxdMSNQ4Q4AwN1m4YH\nQ/xsFz07AK9LzQIQDv7U9Wr+nglKxlsXV4hcMSdcPHy6cOcH1+LQihIVUm4XUhH+8jEFRcwVzbKI\nGfP3Qa4PE3o6CHTTLgjitYN9jl/G7Y4dTuIWbIu9jgPWY/Z9eP0EIIj0WKWsFBD24E/QTfUUgNxH\nGe1uU+XisJ+7XHwnFN1GVgqCja43OyD+CIWdiYhsTWjUgpJ5E0fxc+AHqzHFY2a9Xj1wfDPyxyoA\nW1S9e0KjBPXF8hTpLMATGsbXCltlAQxJlttlBFZKCCAsI7R5cW+xpMyW/mU7SgBUJ2lPHybFdvIS\n/kkKwhO/kHKUXCYtD5Fvgg33/UXIA8UcEHrhUraEik9Cv0YEmwcEdEM+b6CMPDjwUqHMLLWJvB/r\nYZOfvrPtNP97tOh+Gzilb3WkMDsLHUw1HwbErVEhj11lziLbaej7JqgEO9/M8AC27Al7FXaRqDYP\nCuxwoB43b8tGyEmDFLCCjC8Kk1ztEP/gVA+n8Q5l5sev/rTz30Zxgwc5ZZ1d227+TLCP21iPo4O/\n1ZwVEJ0/mri5mBLBOP3qpG1jjuxhpb6xsDRuvbXY/bu6nxERErD1bIVcywy+vBTa65irGR6PBNhZ\nRLtGiZQ9eVfYdXcOnzksALgbMY3RihTlYwNLoDhz/KfMFGTo/3Gah8gk4zf8cCFZO+jFWjQ7l6nV\nZaFpZHFkxLWZxdn+9jKXsFEObkKPKJ01RmnwsIrgcszIiDb5qUx41z0djy6IcBO0+CJ2IigVN/XL\nADeVMeG/d55n0yNPBJtXwU0HxKtT95amNObp/i3V/o7cGrc1TfIfD6ucXn6RtcPGYh6v6pTh0wsn\nmitC17c2iHIWWU/b1+kGcN6VSOkti/66NmUcNWTQHUiQ2I/pD8RWfbxqGNXn2QQhSwST+hAve3p9\n3CqIBPuTqPwBNNWr2jH6IeaRn3adw9H+MCX1QYAF7v/zF2gaYnQVDTduzTN25/V8vUg4lPbOQqG8\n2KCc8NqRPN+trTzRMrh0HIeK8q/+G6pncDXe3PngfyXmfFpCIJUF9RiAs4/J/Yu4ZUd7Nso57o+9\nIA6EVndlXVZlK6nkkZRzhAdYfso8SfpArimn/HYTgGUpfs35MOvKk7zmKqXAxPZkcurMVQ01YS8u\nONptVvI0ZpoDxl/FyLoSGTPo0BzKwwj4UnI6xVjdsT0V5swbEFntLW9IArikjcP7AbfVyOXSats6\nTNoO3qGEve+FXkt/onl8a41AgCWlL00twIoOs6AasHipMeQkOgS0ipUaGjDKcn5ceCWM6+jm2JdC\npbP+MOMtLYYdCyLcULAkhpPwRQIkGQeDcRnsPAjuZWfUHPBWkwkzIHYn2fDi84yh2FvppMqxrLWH\ntNcrGlgWvpHDCdojVWATJI60DjXrYDvJwXNW2kNUC6ZIBr917ItTlQ5surQtNdLCMVKXEWoQNU7q\n5vXU4Cj19Cb84ao5ZpC1dWAI/CNtZyV+9D8HsSf1oISFMRwY4cOAnTDekXrOj/Zj/1qLeXU0HPw/\nuyNcYPiG2qitycy1Df7+/FuFDukKiLkrUsbkdvhOeFQ/LOBWfbBPtNd3m+/57kevqzQpwSQ3q1JL\nAfhHcE29kLQb6ZkrFywzimdO1QUhQLrDxd2C7A+H+0ErTsLOBt8mTIf0bHXUMG8jo8SF3fH3dcW0\ni9VqjocNa8gvtiDGpX4ejz2/hkdEgc50Nsogn1Yop21X8oNvDFJ9Z+2S46IilYBArzBIMhPc7GK7\nTzaIknEGcVckL+lip1TqCZOkxBQdWju+T9/x2rLovnQJScWz/DRT3QKfMf117zA83RxVQrZxfQw4\n15AcEPVUkobhsGOyWd/uonrJ18Chkp6zj8VX8Ha5smr+QpVq3eLzlb9br/VOnrAnUSZ0bvPvjQl1\nI6+lK7EaYF1Lef2z/LfRBTYgqXAewf3nzpmM0wdzIBK4+WCChRBH25ieuAj6DhGU/4dNd5iYkNKw\n5UFjIH0w/7U/+ugyHgDp+nC6JDYtfubj0m0KJJ87RJMmQ1mTNarOu0urmlikkD7+HDMSgYyLEtuQ\nGaSH5vSHsJNe1baNRTA9VZqhlK0zAIBSMEOEhwUqnE1As8+bX9mBFw1Yisk7M/bpzK1mIF1ayLiJ\nGtRL+mvAF7ogzydkw6AZq49ZnkRye/Rc3FSP0qOsX0GAdCjMyaPoSZ919BBXkDatQplglrL5Ap7G\nC9SnQ+UEph9gWx619N+OqIaVd0Sy4GHMXVNXZoWzCGStmOBFx5wU/Whmf+CQQC00fC5T2zyRX0X3\n8TKMKhvJpwWVNtsQv13de3iiNlO1r33Rr6Rz90IILkiLnaaOlZn0gsuUdQQFv5nAq9ZklwQU7St0\nUuSwd+CMyM3cBpYc0HdW3qNwu+ekYlkNKdIFoJ3e0E7qqdNgrYC3Gf12pJiH4lzbRTPZeJzMtMiJ\nS/W+W2H7pW8uOJhZtvIHy/r6/12etJ58zmR/j3PTISTH+55NnYBSGQhXfLN/PrZxEkqeUV44ke+K\ntGWb4cvQD9qBtaL/2JvQzWdwPwTNnq/VOMDHujxwxkazRZQLoavtItyYdaNm1gt8xEzjW2jnxkHL\n7KbB5ZaBXIktxcKqBK64RnziU/bgmFdkLltLuHI55XJSKFd6m/eTU2FmwVMg2rvrgS5i4TwtpL/a\nrsSKWWQCHSIYhb9xTqrzYigYpHuKDjayBqK9+OuA2rTgDdKq9oaxyR/jXySiUxcDh6/az9/NMLQe\n+KGX2bvG3wWdxOs215xclv2w75gXDDOqmYINX+R6Roj/5aUgY1dVU4YCrTi6JGSdprum/c8R6r3K\nBuNzCsiwGCuC+B8q8n8awIiiACjqG/gTisr2FnyUMF19VU65vml2ClFxMEIgiDsG+7uVpVF7Ks5f\nybAZ75BxISPCu2Liw27/nEs4H4aIfBZFm9ffGbAJBal071TlBZhk4rtNqVmQHiEou4C/NvmxcFNm\nZdBkKqo+rmrY3o+/7PrhbZPAZmgUbjAtMHtVne+vge0EF0uj/h3Sq9/2W6bgen0xIv/fzQVSGlPd\n46ZekLfUr6UsLfTrPd3ZFy1yrg8VGInFaN11yTTkTPzcD5p6MzOwLm7UJp18wmNmjk/BlTQ1zvvg\n7e9NX6SRJyF7YdaKwCQYxTQKm5lvUiBxrCcChQJdg6/BG+zVTZT+8x5ShfbbzcXnrfZXMB1RKLuv\nQilDIlQD5VNRgP2K/nbYxsMDjoPRRuQduQ9AG2NyeDT3fGzcxnaUhF6cMSgXV18yfbNBKrl/ie0/\nH7CkmgeL55l3iV2HtsERAx5kEki5NSNovvtZ+jLzxOiuMFxGe2YRpHttIX0l9YscBYzcuESoumlj\nRp6KFFo224Mw8LZSYX0+QLN/W8SRrww56eKNDbbiVU8DBgXEWLXhS/1q/+SoMLbvnr00BDAfbScp\nMOlo9rgdLsOBwD90jQAAvWVk42DxTWfqs/2Q6sE5CHHDEeytdzchnA+2sHM1Ua5LyW8R735BypzF\nyS7tDnyBRxdi8fLOqvDT+LrkjyQsdeCPaZ5HyGpPW55Mmqg00U78uV99LQOwL3Lu+klhr205h/Vh\nyqRvrSBDsjXlBcERGNTb874qY4U2oIdRTqkR8JatCImB6tOG4z4OGkZnCaMespRfx0xh1h/b8c4U\n0m3cjfx+GyjuXBXKNzK0L5f26aA4HLeOMwHuQtRxmhUth92jdHCtkyV5fzbr19dt3PdWn+DnghNw\nmvRsWnJq1pTlpo9aeDt3NDSHra0iEsRfxb3UD9AeHjI0+AkahdLHzNLPRihKpE4llriErZtBC09Y\n1pZq82vu7ZAyYxw9UowxtlJZJ+RcLopN9S34fJ9APRQ66/uuYuD68W+7tTiTNyZHoKkS7FY1Uu6W\nHFyanD61UeLyH9apnXw9DwRQisUpKCy3q21CqCEiWvQ5+C/vy5qC2N8WwBSqj61aW1yQyiYWkBXO\n4xQU+j7sgnBN81KG0kSJXHWcFk/h7X4X1tLr5Ggr890jmGDv7DA+VzdZ7Q3fTJofXmuTIgU1iE0B\neJdgyl1EXsPbo7hUVFVd2EgQRtj3vkHwSCjFVF0gMLaNVf9LcazqIvW4HFFI2tt8+9MFEyenBEgB\nh2xqefXa5q97T4n7zl52mZa4apuhFg21ZyMgeHFgcvbyMJ+BkFVkeKcVVLVyBkZ33V1fcKy90Lv1\nEQIYUQyIACjaEpO+V8EzSUHzmbiWHkouuOe7aRlkH8lTQFjwNnFjhii5SN7T/HR2gqfQoRpSLNoX\n11xPlONY3eNXFfbyVaOKUMCenFuAqN4TTcGrdAeKnFQHvGSbS8wuxr0L6LwRRtmN25YOmq9n5BxF\npV9Chlz3Nhtm+6T4ei3j3vremc2G9BTq8PZ1YLQZqJRyh3Tb2IMQ23HCLb3yoQ4ZpPg1ZZNymmug\nVql8TPMelPFuU3IEXjpgy0SDbqUvZKcP5PKHTuVpdY5eRizzWbn7a6akaK67C//8IU6pBT6WkpLA\nVDG7HQ5KKlwvriaieUvWovcdt+7QusnnssrSWlMdK9jrZ82u9HUYHVKV8Xd5hDB1jYVu6Px36hQ2\n0v1g782llhV76QhcNlBHkDU2CsK3X555FSOcdMTD8BI+n5h0GROXkhSGlodgZTbWppO5QN3jaeWZ\n9a1HLU6dNMfTCEeOUe88KwDZPEFqSG4p0VtwrI863aJ04foZhZDyAjI1PDUNtgBZO2Oz+DJyhXaa\nKSEoR2Yj36JwX9JPzW8mkGxRb5Wx9N9I1/Szbje9t4KwPjOml4qWWpMqrBbpyrs2396STi4KCNLQ\n8dD2nwuApS26e6KvA3swEStkmcg4lPaHt73uL6N1VQxViQ2EEy4rbFy0S2AJzYqERyU+GtstUOcW\nh04cyB/2ofzso/h7nK59EXXXc8lmeFNNll2++rzh4sKZqQajxs/8Gcj65TLhk+uPqyAaFKmmSZeW\nd6jvCOCCgywB1EHAYOnOb9vwGGRCO3JGCLmC7QDTjTOm0FkqGoMUKYsee9Jqd+AtP+t17eVGuIVY\ntAr571S/EkWBcgDYPevACCxmnBp9OjNNBOskcVRUg5XMIim40rW6rv7bFDEDgpcXtBTw5dz7m505\nEJTbnrS+//j8NK4fgaIOl5bKD5x2qP1Z5CcPQc1rxLrkLFrTy8XlEptKXR0t1lQXd0Wkef55TxMT\nqs89vIeZfvIhprc2C9fK2RVjSYAhkj6Iu7TCimjFyr+HmsOsOQQZdQ50WNhAid1TjahlCJ9yCSM2\nSFk2oFhu/qBAvz5cPs0x6lrrRmRIoxvX3WA+IElb9TyFBPyP4BWdTcbfqnQ6XGDijou91uAVawoD\n27aFmoq2OCWPF/Fp+D8dcmb/XoPpK0SOEHaBU1ILRJkdRd6Ys4bq4isO3Sg8vkyA2iNcEZ2DtGkV\nH9IgbGEg1Mv8sPc/wjFMhb4BEqxNWQEKiYgDyA9+0VdYpJdy5X5gZnJxYxhzpEOLZpbbnjd3UeK0\nEKkNXwA41V21GqTZrrUlF76kn367l0KZTNgiNodIaDhxBkTPLMOtpDt75KoJ4Mrtz7HxeJXlUMLs\nj3HezUvOkrRldg1d/XonaIPRDgjcQFhIRTjOEald59tKjB5scFlrOqdI9zQycV4HLXdjifdfH/Dr\nfrQHwLor3niSXfIlsq9V9vLUCFDTNCRYzaE+LlNQbFITqmDUqy70neszXu3lowOaugZOrCx/xLiP\nss7Ja4qppT2Ctc13JZXtKVL6TKDel2VCx7xv0TxpPluSpiKZKUTQwzEb//Cf3o8HRx2YSwZM+kXo\ndb6T5DfBGcLWIujpgWhXW1i1aawHOLQMRqa/bpKAA5En4IfdYbHy0jt2k40ZG11elMVI6RKAtaZb\niRfZ9R5+Q/n0q/XlsbqpiOST0JUqHw3TQzIUl3a/GTAEM1B7E4/aXxOBXoEIBgR+lDXq59z+aZ6V\na/qDF6Cq85iXpIprWSu5PAw2ImEaHr3kZMg5pBYq2xjpYIX0L+FWB+/rlaegVs8JRRX8w7TjuPiI\nldwrcr8nj1s9l18z3ZjIvvfO6i9F8v61PVCGw+cJMCffOL1DUXz2/A4LdTO0Qq63fsJBzfrwNPyM\n4L9m0il1+TVxHhXVoSuSoXNhiIJbWut7GbW+rvTCQJjWk9HIPTN9xKxKFZsH/oRcWIyUI3ogahdW\nH9NEjMeVGwKaYqs85ai7US4jnVmxeYqc6sL6b4AI8zQW9lDAoyygkqC5NsuGZrbk5/GwdIpbCUza\nlV4lvoWrT2nzlCPdE7HqdofSVI/GPQ7EIhG0S9jqrL83rET779F7bWP9oFwAM3WXq2FD3zm2vtbh\nc2dLOEuB32W9sPfobiDEuqaCkrDTI60b+AgewQJcZ9mzktJhauyA5bDFxm/U0ffkqJaEswDtl8AD\nmAo2U8WeHnyMJEqkxx5ld5cLyF2UAMmCM6lGPtpgvknUUkNYs/lD2XhqxuM3cNCLZuvieJKxtFvM\nLbd0bNRMCX6bSVLjKfv+IW0WDBrtuJ17aCr50G1IvprZKzT/xRPVIu0p6p8hNH4953J/ghs9oo7c\nlKQ8loRvT6zSp3GyffPZJOVn9gu8lInMpJwWkFydpk0q/59aiHDXSoigjSM50xfZkM2xB7PXVYTd\nQEfibQ8bp33CVYbaynaCCaQqHVGy+9ML5q0Dsu1Mgs7ttCcpp3W5akyYcO5d8+GUxBMUe0sNq4tl\npVZNNwltEOiqD+QngAx6UkKw0PCg2lxyNyCQZ/E/symhb7OauoiCzQZVF02qMdopaQmGiY/ODvoh\nYtacenkASzgbBSOk0fOO8SsKAaWfuD6KRT0n8bSgZSPboejfoQpVOEmcxM1fFfIbZn60elHh0TWB\nclK+JftnN+AWkwQfTB/JKniwZ+lvqCsuieW1NmyUSR7ykBcRXXSA/0az0coEL/9bCmUeJje42E7X\n3q948+DGDEJc3wvWBANApYi3T8dvHoSv/xB3Sg3uVrCc6Q+vzOhQ1zgvY16rPkvBghqXZg4f/ibO\nGUrA30eB9dJYQkpT6sAhBVevG7t2YLCNsCNH/EpX88wA24JkJNBICyrhs/fbTQI5l86rmfxDybaZ\nV+C5cLUfrLvS74A9KOm8LzImz38+RE9naZuWIUwEKZtI/IqDkLJksZiw7jp+r1Rt7CnpJ9kUQ/ZY\nxwC6FwKaMOPLuelslAkGiig+MUGK8U8q/0wzWTJQgRZBSfu2Md+jmJQdLrdN4HfPGddtNg/rkqpZ\nGnTqmDTCNZHKaKyh8av5iZgAl4C5nsLhKmLgbbDFzsnrzKEv/IoHy9a2gtR2q2q9+ZmZ+TI9YeuG\nVfTbvZgjNKN+nNiL2kT1tpRoHf07mpdAkuAWMrXqddkcn9QyHYLlNOp0dRup0GM1yx0nHY/0hNZS\ngSJkzkBSDJu8fLjwG48jloXCrLjLGo/IUBDwOwUhyCk9ZJtLg5AefO1JndkWU33X+0y1xJGhoK6X\nt6FG7I4nyaqrsoFB6Ha0+UWSqsM/H+hyWWejJpBaI5nHPEZBbLwwaVm10hAFZdZ7oWB2Ve0Dbnyc\npOrPOVUmWOxTiIt5+hkylvrkGu1sQfRU1kBh7ynYIRKOvgljxP/AY0TI7Xs5ZxGJEJn2Y2H1PseT\nxvStZw5RwT5vYJxk/4tT+g9K3BU0LtE0UyGwpIDNlHpLPIT6CIYXNO/GC6vUfCrJh3qh8Pnyd0sX\nNEktZgvb5zGBYxGF46EU9bBwCX0s84fJ97aaxn/gTVv0Hcwq3cUb7U35uO5LHLjrlnUCh29jH0C4\nldzTqhf4Ch9XicZ/uJPVEONESBUmYskm2Y4EuudYmwvVcwEKCAOpmOVSfIHqvjU6EtHuvL2cdO8D\nx41OztnDd/549tkkn/p5SAcs25RZf0vBjrsl9Y1Iezqa3V8z0ZhE3rNUhNB5Oon2IkuC0Rvvltt0\np98veNeUyJDoO2k+hmaWflAEhX1e1RCZNLYx0xSquZxXD0VeaFUEObTKXdejMa7v597GFmoVPkPh\nYKH6ST9ati0TjVdJf+dNVqBRcaHkEzJcAMZLSdNRhPRTOB8J2OM71ealSLZ2lR31089Zlq2QZNaj\nK/viSQPz9ANHmXy4Y9WozP0JCYvMvkRgeF6hmpUEozNEh6efj09VSvAQ80lRJEP4pkFKJoahZ3Wh\nsGB5Z+pR90jHHKeMmQM6lKnUbSlr5YUmqeaSnY2FH60mUkKudlzklCc093iBPlN9fpdkbyQYXbZx\nfa5JtVZLHRLhAJVlIE/gR0js7KeS6d9pKkTFPRPbBwhFPPmZ1TZH//Z99ZlfRf0puhG2nMjqC8Aj\npYZlQ3yB3QR4fmEtLxIjdpY2/IsBNuR4WMI9P7scb/3S9L29X8bwzpVCBQy6WgdogzCZwX/KSInT\nqudwNMs34MHNXvRRBpzB4PVypZOD2LPg4A/JFwAe4PaD7f12CqAISeKEDLQJ8mgfGXEgYzOkRrI/\n3+YV8GNHuTH111rUwy5EO/xyhuMQCnKcUeTbg4hNXfYVdHTr/rsDNAhZg4RfYg2qBoBQblA+Hgoh\nkbvSH9IxR3JbuZGgoS9Dtsr3ichy2pHeO+wsbz1+EFBXE2+Nv1o27Ctl9YTjZy1FkA4F4DugCwI5\nJwmp4CSxlR5V9SDaFHV+Vu1TwBdQY3ttVnuAN6i7awhN1Ad1tIIaF8TH5pERQd5S0fYyxWgjLhn9\npHWVDFC2G+fhIL3BhQUohuHk4oCLQ6L5awnrPPLRqRn4zQDlebCN+fK9J0gdnvHyNyYQ/kaeXF9x\n4QhjVofyFnwwGIIh+pEx3UggaiMCTfm12/JPErbaC2cWkqNJaBKJ+kZUBwTutslEOVEue6ZPibBC\nlvVbw1M+zU3xyPx4SY/MzPQav6MEvRbaT7aTZcFf9la1TtyYvLgsQIB+uB1Jki8vLi6HOMcBThQv\nemw1tXDJlwv/TYh78mMNpllnTGG2prieiBG9cResrv5mEZRJS1RjRyTk9AGQ9GaqTIs0MAVikqco\neK2iSkNM0GWEjHtSluZrD/SzfyYXZsSzJKzD/RmeX2pJmqBaZ1KHgSOzUJC3O6GAQiLE2SDYrQfc\noA14lbLXgYldDUXJX5nrM6EhnNcaT5xBYelhPiqIG/qOsAt4HWOm3SdtK9P6COkCKAWUXhHTeukL\nmKEVwZsqRLRbu0SdhxgItkILQs0JHSpLRmuJfkmZgm53NthwkWNu2unlsZdzeNpVDXL9ilhT2iO1\nNH7HurARdw83ECxK3Who2IcWtdm9+cJ8LNR925XkNJKhHJhhQXGa4GesfJTlLwa0J3J1olAv7dJD\nIVeq5XnXOyW6gzhDzTpK2afgLW3Thq9EY8cM2oWk+vjabJ5i094lTotFRSv9B2lzbIuWBxF3JH0I\nudYhXIW6B9qFceaPBMQM793OUBQSBOi3WGu/Lm0k0FUyRzsTPr/9d1BRWD9b5YqxnWniN/mzDQmA\nYZpqnFuhZFS83FJ7EriLaOJXoisxsE2uVFxQZ7E3c0/WVyt9Pyk+Rq9vxE2c7PUmojV3Rewu3xgC\nHUxvS/q4yXuSWMwqLEbhRt8KyDGB2EcHrMGojI9A0ILuJiueXyd++NuiozOyn33QRNg79tDZH3mv\ni+8I7tqNxp3T0CfBA9QeH1tn6GHvkNBaiaZJ4ioqg2EiNpcbn5nNy33NT53S9uSlyB0Gzkqj9wf8\n0hR3wtkRcGA248PtuON0okzf7rE1mJDI5+hfpRgGyJjEbfJixeU7Lhk1PobdVkkGahSBtTqc2Ldk\noQMllEOGJTuXu46HY55ne9BLbK29u+3MMBz1KAZ58qKCo7sPv5eDsexOr/w3IGHx6Kdyme9VC4gI\nHpr/JGRH5gXt8I9AjgOObZ8YzWCs/KErnh5vKjYPgooq9PMFmD0MKcDUxefsPGCZbtJmcVefKM6h\nBlmVXH28KYc1/71keR1eZBOfhZN5H4IKnWJvnGSPEPWlNmkHDCmMBA/arDVDvUljsoTjFZDXP7T0\n+TjMu/o/7F+zMcZWiYKhgVKkKdWexgpiHXrV/jzlxFhT9fPcBL331pgw832rrR3zn2xBtdx3s/Ag\nK1Cob56W+pntouKPOSBv235PCfPB6A6/Ccw7rvfYZk8LHxle4Y1/PzsISmSD/LVo4cm/Exalc3bJ\n+jWv5iO6jmO2H94k1iA0Nv/3zHgy5iIpqr1Mv6JDpEAtk7Fh/Vh31tsj8vm7ypdcArVQLrZwKYjX\nULh2r6jJOaE8J4PZIgVVGLE9YOmo7BFmfeOhlhkettJhttRcLQdBg126cn1h07bgI2/R4A8FI5ux\nEaWY3u77/vSyaIdQhCF/P3CDABPg+NUyB2mOZkueZZLn5WcQXi/qsIaWa/tXDAGrSaNPF0BUpr0D\nNORQ2oB+sPYpR+iCKvBonHa0hnYsrGlwdwEsz3yguKJpXImkzHAzuYg4Liz6ePZcCW2ZhCSATfZC\nnsGKryGfcDacjk9bvdnNyM0GErMfMbCStu5PZ2r7tRBl+JAYLs0q4OUbr3pX0ne4yoJ31nWSCsl/\no6uk+txkgX3mufLWDGXeNyfaar2RWSKXXQNY1ypDhVTMGj8kPYvQq5HkaZ11Xme0QHgfuRwJqtqh\n8lzVdEQqR1iXV4T6JXENbyBJKTdtkWgcHSzL2s489b3ObCag7j8FPZT5bw+8FliIPY0yxkAr0cRR\ndaKSqx8MxxqntzyJSv66i46SMpCdBKRq0RxZxkv+pHlbESDlhJnZATCho6xuoLk3LI/X2BFR4VX0\numzxeRO/zPXvZWEFgvWb7vPucX5mlBx4j/13u9aZVNcv8qzODK5Tvgdgwc5TSSZq49U0v+9FJFNu\nvSxtSDPPL0b52168r8Kj8O5EgF745J7FdO8n+gu+ma79Qfo/v3LNezC1Q7phWk+RLwYWEB/fC44v\nDbkUkzn7niBiRc+gffcMBzcWNXXMg6ym6FHOMi+xkiVFXFvLIc39i1tT+PyocfD9Yf2DSG2WtUXb\nrExRkxKCe/O/375k4LLknHaBoJmB7m4FcgFZl6WZcgL7Ak78RhFXrmeGuxcuGW4b2njWh+RwOFuD\n1tPq/OWTREvGcq4/OCyOPhuOmLuJuFbKroZYZQKxLS9rTBBVudy8Lm6wygRT4cNoQgO0Ft6wE7Dk\nLVV5SkjkW1wCKNuC32+quUYlwToikg8OX9hqMxp8EAryEIAkhcYpC4+WBh682E/q+e3UzWLiutoy\nxserP8cf15U6aL4UT7nL/Nxmwhw6EzKtHC8JgJevouggntc2V+PvI6qi9bqstuyZu2ogmWkrB9O/\n0vwCkKjyNJMOY9w4Ltb+Jc3mm6sZ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protect end_protected\n", "num_lines": 510}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_vio_counter (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [0 : 0] probe1;\ninput [7 : 0] probe2;\ninput [15 : 0] probe3;\ninput [0 : 0] probe4;\ninput [0 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [7 : 0] probe8;\ninput [15 : 0] probe9;\ninput [15 : 0] probe10;\n\n\nendmodule\n", "num_lines": 83}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"ila_vio_counter,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_vio_counter,ila,{x_ipProduct=Vivado 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_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_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ROBE525_TYPE=1,C_PROBE526_TYPE=1,C_PROBE527_TYPE=1,C_PROBE528_TYPE=1,C_PROBE529_TYPE=1,C_PROBE530_TYPE=1,C_PROBE531_TYPE=1,C_PROBE532_TYPE=1,C_PROBE533_TYPE=1,C_PROBE534_TYPE=1,C_PROBE535_TYPE=1,C_PROBE536_TYPE=1,C_PROBE537_TYPE=1,C_PROBE538_TYPE=1,C_PROBE539_TYPE=1,C_PROBE540_TYPE=1,C_PROBE541_TYPE=1,C_PROBE542_TYPE=1,C_PROBE543_TYPE=1,C_PROBE544_TYPE=1,C_PROBE545_TYPE=1,C_PROBE546_TYPE=1,C_PROBE547_TYPE=1,C_PROBE548_TYPE=1,C_PROBE549_TYPE=1,C_PROBE550_TYPE=1,C_PROBE551_TYPE=1,C_PROBE552_TYPE=1,C_PROBE553_TYPE=1,C_PROBE554_TYPE=1,C_PROBE555_TYPE=1,C_PROBE556_TYPE=1,C_PROBE557_TYPE=1,C_PROBE558_TYPE=1,C_PROBE559_TYPE=1,C_PROBE560_TYPE=1,C_PROBE561_TYPE=1,C_PROBE562_TYPE=1,C_PROBE563_TYPE=1,C_PROBE564_TYPE=1,C_PROBE565_TYPE=1,C_PROBE566_TYPE=1,C_PROBE567_TYPE=1,C_PROBE568_TYPE=1,C_PROBE569_TYPE=1,C_PROBE570_TYPE=1,C_PROBE571_TYPE=1,C_PROBE572_TYPE=1,C_PROBE573_TYPE=1,C_PROBE574_TYPE=1,C_PROBE575_TYPE=1,C_PROBE576_TYPE=1,C_PROBE577_TYPE=1,C_PROBE578_TYPE=1,C_PROBE579_TYPE=1,C_PROBE580_TYPE=1,C_PROBE581_TYPE=1,C_PROBE582_TYPE=1,C_PROBE583_TYPE=1,C_PROBE584_TYPE=1,C_PROBE585_TYPE=1,C_PROBE586_TYPE=1,C_PROBE587_TYPE=1,C_PROBE588_TYPE=1,C_PROBE589_TYPE=1,C_PROBE590_TYPE=1,C_PROBE591_TYPE=1,C_PROBE592_TYPE=1,C_PROBE593_TYPE=1,C_PROBE594_TYPE=1,C_PROBE595_TYPE=1,C_PROBE596_TYPE=1,C_PROBE597_TYPE=1,C_PROBE598_TYPE=1,C_PROBE599_TYPE=1,C_PROBE600_TYPE=1,C_PROBE601_TYPE=1,C_PROBE602_TYPE=1,C_PROBE603_TYPE=1,C_PROBE604_TYPE=1,C_PROBE605_TYPE=1,\\\nC_PROBE606_TYPE=1,C_PROBE607_TYPE=1,C_PROBE608_TYPE=1,C_PROBE609_TYPE=1,C_PROBE610_TYPE=1,C_PROBE611_TYPE=1,C_PROBE612_TYPE=1,C_PROBE613_TYPE=1,C_PROBE614_TYPE=1,C_PROBE615_TYPE=1,C_PROBE616_TYPE=1,C_PROBE617_TYPE=1,C_PROBE618_TYPE=1,C_PROBE619_TYPE=1,C_PROBE620_TYPE=1,C_PROBE621_TYPE=1,C_PROBE622_TYPE=1,C_PROBE623_TYPE=1,C_PROBE624_TYPE=1,C_PROBE625_TYPE=1,C_PROBE626_TYPE=1,C_PROBE627_TYPE=1,C_PROBE628_TYPE=1,C_PROBE629_TYPE=1,C_PROBE630_TYPE=1,C_PROBE631_TYPE=1,C_PROBE632_TYPE=1,C_PROBE633_TYPE=1,C_PROBE634_TYPE=1,C_PROBE635_TYPE=1,C_PROBE636_TYPE=1,C_PROBE637_TYPE=1,C_PROBE638_TYPE=1,C_PROBE639_TYPE=1,C_PROBE640_TYPE=1,C_PROBE641_TYPE=1,C_PROBE642_TYPE=1,C_PROBE643_TYPE=1,C_PROBE644_TYPE=1,C_PROBE645_TYPE=1,C_PROBE646_TYPE=1,C_PROBE647_TYPE=1,C_PROBE648_TYPE=1,C_PROBE649_TYPE=1,C_PROBE650_TYPE=1,C_PROBE651_TYPE=1,C_PROBE652_TYPE=1,C_PROBE653_TYPE=1,C_PROBE654_TYPE=1,C_PROBE655_TYPE=1,C_PROBE656_TYPE=1,C_PROBE657_TYPE=1,C_PROBE658_TYPE=1,C_PROBE659_TYPE=1,C_PROBE660_TYPE=1,C_PROBE661_TYPE=1,C_PROBE662_TYPE=1,C_PROBE663_TYPE=1,C_PROBE664_TYPE=1,C_PROBE665_TYPE=1,C_PROBE666_TYPE=1,C_PROBE667_TYPE=1,C_PROBE668_TYPE=1,C_PROBE669_TYPE=1,C_PROBE670_TYPE=1,C_PROBE671_TYPE=1,C_PROBE672_TYPE=1,C_PROBE673_TYPE=1,C_PROBE674_TYPE=1,C_PROBE675_TYPE=1,C_PROBE676_TYPE=1,C_PROBE677_TYPE=1,C_PROBE678_TYPE=1,C_PROBE679_TYPE=1,C_PROBE680_TYPE=1,C_PROBE681_TYPE=1,C_PROBE682_TYPE=1,C_PROBE683_TYPE=1,C_PROBE684_TYPE=1,C_PROBE685_TYPE=1,C_PROBE686_TYPE=1,C_PROBE687_TYPE=1,C_PROBE688_TYPE=1,C_PROBE689_TYPE=1,C_PROBE690_TYPE=1,C_PROBE691_TYPE=1,C_PROBE692_TYPE=1,C_PROBE693_TYPE=1,C_PROBE694_TYPE=1,C_PROBE695_TYPE=1,C_PROBE696_TYPE=1,C_PROBE697_TYPE=1,C_PROBE698_TYPE=1,C_PROBE699_TYPE=1,C_PROBE700_TYPE=1,C_PROBE701_TYPE=1,C_PROBE702_TYPE=1,C_PROBE703_TYPE=1,C_PROBE704_TYPE=1,C_PROBE705_TYPE=1,\\\nC_PROBE706_TYPE=1,C_PROBE707_TYPE=1,C_PROBE708_TYPE=1,C_PROBE709_TYPE=1,C_PROBE710_TYPE=1,C_PROBE711_TYPE=1,C_PROBE712_TYPE=1,C_PROBE713_TYPE=1,C_PROBE714_TYPE=1,C_PROBE715_TYPE=1,C_PROBE716_TYPE=1,C_PROBE717_TYPE=1,C_PROBE718_TYPE=1,C_PROBE719_TYPE=1,C_PROBE720_TYPE=1,C_PROBE721_TYPE=1,C_PROBE722_TYPE=1,C_PROBE723_TYPE=1,C_PROBE724_TYPE=1,C_PROBE725_TYPE=1,C_PROBE726_TYPE=1,C_PROBE727_TYPE=1,C_PROBE728_TYPE=1,C_PROBE729_TYPE=1,C_PROBE730_TYPE=1,C_PROBE731_TYPE=1,C_PROBE732_TYPE=1,C_PROBE733_TYPE=1,C_PROBE734_TYPE=1,C_PROBE735_TYPE=1,C_PROBE736_TYPE=1,C_PROBE737_TYPE=1,C_PROBE738_TYPE=1,C_PROBE739_TYPE=1,C_PROBE740_TYPE=1,C_PROBE741_TYPE=1,C_PROBE742_TYPE=1,C_PROBE743_TYPE=1,C_PROBE744_TYPE=1,C_PROBE745_TYPE=1,C_PROBE746_TYPE=1,C_PROBE747_TYPE=1,C_PROBE748_TYPE=1,C_PROBE749_TYPE=1,C_PROBE750_TYPE=1,C_PROBE751_TYPE=1,C_PROBE752_TYPE=1,C_PROBE753_TYPE=1,C_PROBE754_TYPE=1,C_PROBE755_TYPE=1,C_PROBE756_TYPE=1,C_PROBE757_TYPE=1,C_PROBE758_TYPE=1,C_PROBE759_TYPE=1,C_PROBE760_TYPE=1,C_PROBE761_TYPE=1,C_PROBE762_TYPE=1,C_PROBE763_TYPE=1,C_PROBE764_TYPE=1,C_PROBE765_TYPE=1,C_PROBE766_TYPE=1,C_PROBE767_TYPE=1,C_PROBE768_TYPE=1,C_PROBE769_TYPE=1,C_PROBE770_TYPE=1,C_PROBE771_TYPE=1,C_PROBE772_TYPE=1,C_PROBE773_TYPE=1,C_PROBE774_TYPE=1,C_PROBE775_TYPE=1,C_PROBE776_TYPE=1,C_PROBE777_TYPE=1,C_PROBE778_TYPE=1,C_PROBE779_TYPE=1,C_PROBE780_TYPE=1,C_PROBE781_TYPE=1,C_PROBE782_TYPE=1,C_PROBE783_TYPE=1,C_PROBE784_TYPE=1,C_PROBE785_TYPE=1,C_PROBE786_TYPE=1,C_PROBE787_TYPE=1,C_PROBE788_TYPE=1,C_PROBE789_TYPE=1,C_PROBE790_TYPE=1,C_PROBE791_TYPE=1,C_PROBE792_TYPE=1,C_PROBE793_TYPE=1,C_PROBE794_TYPE=1,C_PROBE795_TYPE=1,C_PROBE796_TYPE=1,C_PROBE797_TYPE=1,C_PROBE798_TYPE=1,C_PROBE799_TYPE=1,C_PROBE800_TYPE=1,C_PROBE801_TYPE=1,C_PROBE802_TYPE=1,C_PROBE803_TYPE=1,C_PROBE804_TYPE=1,C_PROBE805_TYPE=1,\\\nC_PROBE806_TYPE=1,C_PROBE807_TYPE=1,C_PROBE808_TYPE=1,C_PROBE809_TYPE=1,C_PROBE810_TYPE=1,C_PROBE811_TYPE=1,C_PROBE812_TYPE=1,C_PROBE813_TYPE=1,C_PROBE814_TYPE=1,C_PROBE815_TYPE=1,C_PROBE816_TYPE=1,C_PROBE817_TYPE=1,C_PROBE818_TYPE=1,C_PROBE819_TYPE=1,C_PROBE820_TYPE=1,C_PROBE821_TYPE=1,C_PROBE822_TYPE=1,C_PROBE823_TYPE=1,C_PROBE824_TYPE=1,C_PROBE825_TYPE=1,C_PROBE826_TYPE=1,C_PROBE827_TYPE=1,C_PROBE828_TYPE=1,C_PROBE829_TYPE=1,C_PROBE830_TYPE=1,C_PROBE831_TYPE=1,C_PROBE832_TYPE=1,C_PROBE833_TYPE=1,C_PROBE834_TYPE=1,C_PROBE835_TYPE=1,C_PROBE836_TYPE=1,C_PROBE837_TYPE=1,C_PROBE838_TYPE=1,C_PROBE839_TYPE=1,C_PROBE840_TYPE=1,C_PROBE841_TYPE=1,C_PROBE842_TYPE=1,C_PROBE843_TYPE=1,C_PROBE844_TYPE=1,C_PROBE845_TYPE=1,C_PROBE846_TYPE=1,C_PROBE847_TYPE=1,C_PROBE848_TYPE=1,C_PROBE849_TYPE=1,C_PROBE850_TYPE=1,C_PROBE851_TYPE=1,C_PROBE852_TYPE=1,C_PROBE853_TYPE=1,C_PROBE854_TYPE=1,C_PROBE855_TYPE=1,C_PROBE856_TYPE=1,C_PROBE857_TYPE=1,C_PROBE858_TYPE=1,C_PROBE859_TYPE=1,C_PROBE860_TYPE=1,C_PROBE861_TYPE=1,C_PROBE862_TYPE=1,C_PROBE863_TYPE=1,C_PROBE864_TYPE=1,C_PROBE865_TYPE=1,C_PROBE866_TYPE=1,C_PROBE867_TYPE=1,C_PROBE868_TYPE=1,C_PROBE869_TYPE=1,C_PROBE870_TYPE=1,C_PROBE871_TYPE=1,C_PROBE872_TYPE=1,C_PROBE873_TYPE=1,C_PROBE874_TYPE=1,C_PROBE875_TYPE=1,C_PROBE876_TYPE=1,C_PROBE877_TYPE=1,C_PROBE878_TYPE=1,C_PROBE879_TYPE=1,C_PROBE880_TYPE=1,C_PROBE881_TYPE=1,C_PROBE882_TYPE=1,C_PROBE883_TYPE=1,C_PROBE884_TYPE=1,C_PROBE885_TYPE=1,C_PROBE886_TYPE=1,C_PROBE887_TYPE=1,C_PROBE888_TYPE=1,C_PROBE889_TYPE=1,C_PROBE890_TYPE=1,C_PROBE891_TYPE=1,C_PROBE892_TYPE=1,C_PROBE893_TYPE=1,C_PROBE894_TYPE=1,C_PROBE895_TYPE=1,C_PROBE896_TYPE=1,C_PROBE897_TYPE=1,C_PROBE898_TYPE=1,C_PROBE899_TYPE=1,C_PROBE900_TYPE=1,C_PROBE901_TYPE=1,C_PROBE902_TYPE=1,C_PROBE903_TYPE=1,C_PROBE904_TYPE=1,C_PROBE905_TYPE=1,\\\nC_PROBE906_TYPE=1,C_PROBE907_TYPE=1,C_PROBE908_TYPE=1,C_PROBE909_TYPE=1,C_PROBE910_TYPE=1,C_PROBE911_TYPE=1,C_PROBE912_TYPE=1,C_PROBE913_TYPE=1,C_PROBE914_TYPE=1,C_PROBE915_TYPE=1,C_PROBE916_TYPE=1,C_PROBE917_TYPE=1,C_PROBE918_TYPE=1,C_PROBE919_TYPE=1,C_PROBE920_TYPE=1,C_PROBE921_TYPE=1,C_PROBE922_TYPE=1,C_PROBE923_TYPE=1,C_PROBE924_TYPE=1,C_PROBE925_TYPE=1,C_PROBE926_TYPE=1,C_PROBE927_TYPE=1,C_PROBE928_TYPE=1,C_PROBE929_TYPE=1,C_PROBE930_TYPE=1,C_PROBE931_TYPE=1,C_PROBE932_TYPE=1,C_PROBE933_TYPE=1,C_PROBE934_TYPE=1,C_PROBE935_TYPE=1,C_PROBE936_TYPE=1,C_PROBE937_TYPE=1,C_PROBE938_TYPE=1,C_PROBE939_TYPE=1,C_PROBE940_TYPE=1,C_PROBE941_TYPE=1,C_PROBE942_TYPE=1,C_PROBE943_TYPE=1,C_PROBE944_TYPE=1,C_PROBE945_TYPE=1,C_PROBE946_TYPE=1,C_PROBE947_TYPE=1,C_PROBE948_TYPE=1,C_PROBE949_TYPE=1,C_PROBE950_TYPE=1,C_PROBE951_TYPE=1,C_PROBE952_TYPE=1,C_PROBE953_TYPE=1,C_PROBE954_TYPE=1,C_PROBE955_TYPE=1,C_PROBE956_TYPE=1,C_PROBE957_TYPE=1,C_PROBE958_TYPE=1,C_PROBE959_TYPE=1,C_PROBE960_TYPE=1,C_PROBE961_TYPE=1,C_PROBE962_TYPE=1,C_PROBE963_TYPE=1,C_PROBE964_TYPE=1,C_PROBE965_TYPE=1,C_PROBE966_TYPE=1,C_PROBE967_TYPE=1,C_PROBE968_TYPE=1,C_PROBE969_TYPE=1,C_PROBE970_TYPE=1,C_PROBE971_TYPE=1,C_PROBE972_TYPE=1,C_PROBE973_TYPE=1,C_PROBE974_TYPE=1,C_PROBE975_TYPE=1,C_PROBE976_TYPE=1,C_PROBE977_TYPE=1,C_PROBE978_TYPE=1,C_PROBE979_TYPE=1,C_PROBE980_TYPE=1,C_PROBE981_TYPE=1,C_PROBE982_TYPE=1,C_PROBE983_TYPE=1,C_PROBE984_TYPE=1,C_PROBE985_TYPE=1,C_PROBE986_TYPE=1,C_PROBE987_TYPE=1,C_PROBE988_TYPE=1,C_PROBE989_TYPE=1,C_PROBE990_TYPE=1,C_PROBE991_TYPE=1,C_PROBE992_TYPE=1,C_PROBE993_TYPE=1,C_PROBE994_TYPE=1,C_PROBE995_TYPE=1,C_PROBE996_TYPE=1,C_PROBE997_TYPE=1,C_PROBE998_TYPE=1,C_PROBE999_TYPE=1,C_PROBE1000_TYPE=1,C_PROBE1001_TYPE=1,C_PROBE1002_TYPE=1,C_PROBE1003_TYPE=1,C_PROBE1004_TYPE=1,C_PROBE1005_TYPE=1,\\\nC_PROBE1006_TYPE=1,C_PROBE1007_TYPE=1,C_PROBE1008_TYPE=1,C_PROBE1009_TYPE=1,C_PROBE1010_TYPE=1,C_PROBE1011_TYPE=1,C_PROBE1012_TYPE=1,C_PROBE1013_TYPE=1,C_PROBE1014_TYPE=1,C_PROBE1015_TYPE=1,C_PROBE1016_TYPE=1,C_PROBE1017_TYPE=1,C_PROBE1018_TYPE=1,C_PROBE1019_TYPE=1,C_PROBE1020_TYPE=1,C_PROBE1021_TYPE=1,C_PROBE1022_TYPE=1,C_PROBE1023_TYPE=1}\" *)\n\nmodule ila_vio_counter (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [0 : 0] probe1;\ninput [7 : 0] probe2;\ninput [15 : 0] probe3;\ninput [0 : 0] probe4;\ninput [0 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [7 : 0] probe8;\ninput [15 : 0] probe9;\ninput [15 : 0] probe10;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_5_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(11),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2017),\n.C_MINOR_VERSION(4),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(0),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(4),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH (32),\n.C_ILA_CLK_FREQ(2000000),\n.C_PROBE0_WIDTH(1),\n.C_PROBE1_WIDTH(1),\n.C_PROBE2_WIDTH(8),\n.C_PROBE3_WIDTH(16),\n.C_PROBE4_WIDTH(1),\n.C_PROBE5_WIDTH(1),\n.C_PROBE6_WIDTH(1),\n.C_PROBE7_WIDTH(1),\n.C_PROBE8_WIDTH(8),\n.C_PROBE9_WIDTH(16),\n.C_PROBE10_WIDTH(16),\n.C_PROBE11_WIDTH(1),\n.C_PROBE12_WIDTH(1),\n.C_PROBE13_WIDTH(1),\n.C_PROBE14_WIDTH(1),\n.C_PROBE15_WIDTH(1),\n.C_PROBE16_WIDTH(1),\n.C_PROBE17_WIDTH(1),\n.C_PROBE18_WIDTH(1),\n.C_PROBE19_WIDTH(1),\n.C_PROBE20_WIDTH(1),\n.C_PROBE21_WIDTH(1),\n.C_PROBE22_WIDTH(1),\n.C_PROBE23_WIDTH(1),\n.C_PROBE24_WIDTH(1),\n.C_PROBE25_WIDTH(1),\n.C_PROBE26_WIDTH(1),\n.C_PROBE27_WIDTH(1),\n.C_PROBE28_WIDTH(1),\n.C_PROBE29_WIDTH(1),\n.C_PROBE30_WIDTH(1),\n.C_PROBE31_WIDTH(1),\n.C_PROBE32_WIDTH(1),\n.C_PROBE33_WIDTH(1),\n.C_PROBE34_WIDTH(1),\n.C_PROBE35_WIDTH(1),\n.C_PROBE36_WIDTH(1),\n.C_PROBE37_WIDTH(1),\n.C_PROBE38_WIDTH(1),\n.C_PROBE39_WIDTH(1),\n.C_PROBE40_WIDTH(1),\n.C_PROBE41_WIDTH(1),\n.C_PROBE42_WIDTH(1),\n.C_PROBE43_WIDTH(1),\n.C_PROBE44_WIDTH(1),\n.C_PROBE45_WIDTH(1),\n.C_PROBE46_WIDTH(1),\n.C_PROBE47_WIDTH(1),\n.C_PROBE48_WIDTH(1),\n.C_PROBE49_WIDTH(1),\n.C_PROBE50_WIDTH(1),\n.C_PROBE51_WIDTH(1),\n.C_PROBE52_WIDTH(1),\n.C_PROBE53_WIDTH(1),\n.C_PROBE54_WIDTH(1),\n.C_PROBE55_WIDTH(1),\n.C_PROBE56_WIDTH(1),\n.C_PROBE57_WIDTH(1),\n.C_PROBE58_WIDTH(1),\n.C_PROBE59_WIDTH(1),\n.C_PROBE60_WIDTH(1),\n.C_PROBE61_WIDTH(1),\n.C_PROBE62_WIDTH(1),\n.C_PROBE63_WIDTH(1),\n.C_PROBE64_WIDTH(1),\n.C_PROBE65_WIDTH(1),\n.C_PROBE66_WIDTH(1),\n.C_PROBE67_WIDTH(1),\n.C_PROBE68_WIDTH(1),\n.C_PROBE69_WIDTH(1),\n.C_PROBE70_WIDTH(1),\n.C_PROBE71_WIDTH(1),\n.C_PROBE72_WIDTH(1),\n.C_PROBE73_WIDTH(1),\n.C_PROBE74_WIDTH(1),\n.C_PROBE75_WIDTH(1),\n.C_PROBE76_WIDTH(1),\n.C_PROBE77_WIDTH(1),\n.C_PROBE78_WIDTH(1),\n.C_PROBE79_WIDTH(1),\n.C_PROBE80_WIDTH(1),\n.C_PROBE81_WIDTH(1),\n.C_PROBE82_WIDTH(1),\n.C_PROBE83_WIDTH(1),\n.C_PROBE84_WIDTH(1),\n.C_PROBE85_WIDTH(1),\n.C_PROBE86_WIDTH(1),\n.C_PROBE87_WIDTH(1),\n.C_PROBE88_WIDTH(1),\n.C_PROBE89_WIDTH(1),\n.C_PROBE90_WIDTH(1),\n.C_PROBE91_WIDTH(1),\n.C_PROBE92_WIDTH(1),\n.C_PROBE93_WIDTH(1),\n.C_PROBE94_WIDTH(1),\n.C_PROBE95_WIDTH(1),\n.C_PROBE96_WIDTH(1),\n.C_PROBE97_WIDTH(1),\n.C_PROBE98_WIDTH(1),\n.C_PROBE99_WIDTH(1),\n.C_PROBE100_WIDTH(1),\n.C_PROBE101_WIDTH(1),\n.C_PROBE102_WIDTH(1),\n.C_PROBE103_WIDTH(1),\n.C_PROBE104_WIDTH(1),\n.C_PROBE105_WIDTH(1),\n.C_PROBE106_WIDTH(1),\n.C_PROBE107_WIDTH(1),\n.C_PROBE108_WIDTH(1),\n.C_PROBE109_WIDTH(1),\n.C_PROBE110_WIDTH(1),\n.C_PROBE111_WIDTH(1),\n.C_PROBE112_WIDTH(1),\n.C_PROBE113_WIDTH(1),\n.C_PROBE114_WIDTH(1),\n.C_PROBE115_WIDTH(1),\n.C_PROBE116_WIDTH(1),\n.C_PROBE117_WIDTH(1),\n.C_PROBE118_WIDTH(1),\n.C_PROBE119_WIDTH(1),\n.C_PROBE120_WIDTH(1),\n.C_PROBE121_WIDTH(1),\n.C_PROBE122_WIDTH(1),\n.C_PROBE123_WIDTH(1),\n.C_PROBE124_WIDTH(1),\n.C_PROBE125_WIDTH(1),\n.C_PROBE126_WIDTH(1),\n.C_PROBE127_WIDTH(1),\n.C_PROBE128_WIDTH(1),\n.C_PROBE129_WIDTH(1),\n.C_PROBE130_WIDTH(1),\n.C_PROBE131_WIDTH(1),\n.C_PROBE132_WIDTH(1),\n.C_PROBE133_WIDTH(1),\n.C_PROBE134_WIDTH(1),\n.C_PROBE135_WIDTH(1),\n.C_PROBE136_WIDTH(1),\n.C_PROBE137_WIDTH(1),\n.C_PROBE138_WIDTH(1),\n.C_PROBE139_WIDTH(1),\n.C_PROBE140_WIDTH(1),\n.C_PROBE141_WIDTH(1),\n.C_PROBE142_WIDTH(1),\n.C_PROBE143_WIDTH(1),\n.C_PROBE144_WIDTH(1),\n.C_PROBE145_WIDTH(1),\n.C_PROBE146_WIDTH(1),\n.C_PROBE147_WIDTH(1),\n.C_PROBE148_WIDTH(1),\n.C_PROBE149_WIDTH(1),\n.C_PROBE150_WIDTH(1),\n.C_PROBE151_WIDTH(1),\n.C_PROBE152_WIDTH(1),\n.C_PROBE153_WIDTH(1),\n.C_PROBE154_WIDTH(1),\n.C_PROBE155_WIDTH(1),\n.C_PROBE156_WIDTH(1),\n.C_PROBE157_WIDTH(1),\n.C_PROBE158_WIDTH(1),\n.C_PROBE159_WIDTH(1),\n.C_PROBE160_WIDTH(1),\n.C_PROBE161_WIDTH(1),\n.C_PROBE162_WIDTH(1),\n.C_PROBE163_WIDTH(1),\n.C_PROBE164_WIDTH(1),\n.C_PROBE165_WIDTH(1),\n.C_PROBE166_WIDTH(1),\n.C_PROBE167_WIDTH(1),\n.C_PROBE168_WIDTH(1),\n.C_PROBE169_WIDTH(1),\n.C_PROBE170_WIDTH(1),\n.C_PROBE171_WIDTH(1),\n.C_PROBE172_WIDTH(1),\n.C_PROBE173_WIDTH(1),\n.C_PROBE174_WIDTH(1),\n.C_PROBE175_WIDTH(1),\n.C_PROBE176_WIDTH(1),\n.C_PROBE177_WIDTH(1),\n.C_PROBE178_WIDTH(1),\n.C_PROBE179_WIDTH(1),\n.C_PROBE180_WIDTH(1),\n.C_PROBE181_WIDTH(1),\n.C_PROBE182_WIDTH(1),\n.C_PROBE183_WIDTH(1),\n.C_PROBE184_WIDTH(1),\n.C_PROBE185_WIDTH(1),\n.C_PROBE186_WIDTH(1),\n.C_PROBE187_WIDTH(1),\n.C_PROBE188_WIDTH(1),\n.C_PROBE189_WIDTH(1),\n.C_PROBE190_WIDTH(1),\n.C_PROBE191_WIDTH(1),\n.C_PROBE192_WIDTH(1),\n.C_PROBE193_WIDTH(1),\n.C_PROBE194_WIDTH(1),\n.C_PROBE195_WIDTH(1),\n.C_PROBE196_WIDTH(1),\n.C_PROBE197_WIDTH(1),\n.C_PROBE198_WIDTH(1),\n.C_PROBE199_WIDTH(1),\n.C_PROBE200_WIDTH(1),\n.C_PROBE201_WIDTH(1),\n.C_PROBE202_WIDTH(1),\n.C_PROBE203_WIDTH(1),\n.C_PROBE204_WIDTH(1),\n.C_PROBE205_WIDTH(1),\n.C_PROBE206_WIDTH(1),\n.C_PROBE207_WIDTH(1),\n.C_PROBE208_WIDTH(1),\n.C_PROBE209_WIDTH(1),\n.C_PROBE210_WIDTH(1),\n.C_PROBE211_WIDTH(1),\n.C_PROBE212_WIDTH(1),\n.C_PROBE213_WIDTH(1),\n.C_PROBE214_WIDTH(1),\n.C_PROBE215_WIDTH(1),\n.C_PROBE216_WIDTH(1),\n.C_PROBE217_WIDTH(1),\n.C_PROBE218_WIDTH(1),\n.C_PROBE219_WIDTH(1),\n.C_PROBE220_W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U_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT(1),\n.C_PROBE275_MU_CNT(1),\n.C_PROBE276_MU_CNT(1),\n.C_PROBE277_MU_CNT(1),\n.C_PROBE278_MU_CNT(1),\n.C_PROBE279_MU_CNT(1),\n.C_PROBE280_MU_CNT(1),\n.C_PROBE281_MU_CNT(1),\n.C_PROBE282_MU_CNT(1),\n.C_PROBE283_MU_CNT(1),\n.C_PROBE284_MU_CNT(1),\n.C_PROBE285_MU_CNT(1),\n.C_PROBE286_MU_CNT(1),\n.C_PROBE287_MU_CNT(1),\n.C_PROBE288_MU_CNT(1),\n.C_PROBE289_MU_CNT(1),\n.C_PROBE290_MU_CNT(1),\n.C_PROBE291_MU_CNT(1),\n.C_PROBE292_MU_CNT(1),\n.C_PROBE293_MU_CNT(1),\n.C_PROBE294_MU_CNT(1),\n.C_PROBE295_MU_CNT(1),\n.C_PROBE296_MU_CNT(1),\n.C_PROBE297_MU_CNT(1),\n.C_PROBE298_MU_CNT(1),\n.C_PROBE299_MU_CNT(1),\n.C_PROBE300_MU_CNT(1),\n.C_PROBE301_MU_CNT(1),\n.C_PROBE302_MU_CNT(1),\n.C_PROBE303_MU_CNT(1),\n.C_PROBE304_MU_CNT(1),\n.C_PROBE305_MU_CNT(1),\n.C_PROBE306_MU_CNT(1),\n.C_PROBE307_MU_CNT(1),\n.C_PROBE308_MU_CNT(1),\n.C_PROBE309_MU_CNT(1),\n.C_PROBE310_MU_CNT(1),\n.C_PROBE311_MU_CNT(1),\n.C_PROBE312_MU_CNT(1),\n.C_PROBE313_MU_CNT(1),\n.C_PROBE314_MU_CNT(1),\n.C_PROBE315_MU_CNT(1),\n.C_PROBE316_MU_CNT(1),\n.C_PROBE317_MU_CNT(1),\n.C_PROBE318_MU_CNT(1),\n.C_PROBE319_MU_CNT(1),\n.C_PROBE320_MU_CNT(1),\n.C_PROBE321_MU_CNT(1),\n.C_PROBE322_MU_CNT(1),\n.C_PROBE323_MU_CNT(1),\n.C_PROBE324_MU_CNT(1),\n.C_PROBE325_MU_CNT(1),\n.C_PROBE326_MU_CNT(1),\n.C_PROBE327_MU_CNT(1),\n.C_PROBE328_MU_CNT(1),\n.C_PROBE329_MU_CNT(1),\n.C_PROBE330_MU_CNT(1),\n.C_PROBE331_MU_CNT(1),\n.C_PROBE332_MU_CNT(1),\n.C_PROBE333_MU_CNT(1),\n.C_PROBE334_MU_CNT(1),\n.C_PROBE335_MU_CNT(1),\n.C_PROBE336_MU_CNT(1),\n.C_PROBE337_MU_CNT(1),\n.C_PROBE338_MU_CNT(1),\n.C_PROBE339_MU_CNT(1),\n.C_PROBE340_MU_CNT(1),\n.C_PROBE341_MU_CNT(1),\n.C_PROBE342_MU_CNT(1),\n.C_PROBE343_MU_CNT(1),\n.C_PROBE344_MU_CNT(1),\n.C_PROBE345_MU_CNT(1),\n.C_PROBE346_MU_CNT(1),\n.C_PROBE347_MU_CNT(1),\n.C_PROBE348_MU_CNT(1),\n.C_PROBE349_MU_CNT(1),\n.C_PROBE350_MU_CNT(1),\n.C_PROBE351_MU_CNT(1),\n.C_PROBE352_MU_CNT(1),\n.C_PROBE353_MU_CNT(1),\n.C_PROBE354_MU_CNT(1),\n.C_PROBE355_MU_CNT(1),\n.C_PROBE356_MU_CNT(1),\n.C_PROBE357_MU_CNT(1),\n.C_PROBE358_MU_CNT(1),\n.C_PROBE359_MU_CNT(1),\n.C_PROBE360_MU_CNT(1),\n.C_PROBE361_MU_CNT(1),\n.C_PROBE362_MU_CNT(1),\n.C_PROBE363_MU_CNT(1),\n.C_PROBE364_MU_CNT(1),\n.C_PROBE365_MU_CNT(1),\n.C_PROBE366_MU_CNT(1),\n.C_PROBE367_MU_CNT(1),\n.C_PROBE368_MU_CNT(1),\n.C_PROBE369_MU_CNT(1),\n.C_PROBE370_MU_CNT(1),\n.C_PROBE371_MU_CNT(1),\n.C_PROBE372_MU_CNT(1),\n.C_PROBE373_MU_CNT(1),\n.C_PROBE374_MU_CNT(1),\n.C_PROBE375_MU_CNT(1),\n.C_PROBE376_MU_CNT(1),\n.C_PROBE377_MU_CNT(1),\n.C_PROBE378_MU_CNT(1),\n.C_PROBE379_MU_CNT(1),\n.C_PROBE380_MU_CNT(1),\n.C_PROBE381_MU_CNT(1),\n.C_PROBE382_MU_CNT(1),\n.C_PROBE383_MU_CNT(1),\n.C_PROBE384_MU_CNT(1),\n.C_PROBE385_MU_CNT(1),\n.C_PROBE386_MU_CNT(1),\n.C_PROBE387_MU_CNT(1),\n.C_PROBE388_MU_CNT(1),\n.C_PROBE389_MU_CNT(1),\n.C_PROBE390_MU_CNT(1),\n.C_PROBE391_MU_CNT(1),\n.C_PROBE392_MU_CNT(1),\n.C_PROBE393_MU_CNT(1),\n.C_PROBE394_MU_CNT(1),\n.C_PROBE395_MU_CNT(1),\n.C_PROBE396_MU_CNT(1),\n.C_PROBE397_MU_CNT(1),\n.C_PROBE398_MU_CNT(1),\n.C_PROBE399_MU_CNT(1),\n.C_PROBE400_MU_CNT(1),\n.C_PROBE401_MU_CNT(1),\n.C_PROBE402_MU_CNT(1),\n.C_PROBE403_MU_CNT(1),\n.C_PROBE404_MU_CNT(1),\n.C_PROBE405_MU_CNT(1),\n.C_PROBE406_MU_CNT(1),\n.C_PROBE407_MU_CNT(1),\n.C_PROBE408_MU_CNT(1),\n.C_PROBE409_MU_CNT(1),\n.C_PROBE410_MU_CNT(1),\n.C_PROBE411_MU_CNT(1),\n.C_PROBE412_MU_CNT(1),\n.C_PROBE413_MU_CNT(1),\n.C_PROBE414_MU_CNT(1),\n.C_PROBE415_MU_CNT(1),\n.C_PROBE416_MU_CNT(1),\n.C_PROBE417_MU_CNT(1),\n.C_PROBE418_MU_CNT(1),\n.C_PROBE419_MU_CNT(1),\n.C_PROBE420_MU_CNT(1),\n.C_PROBE421_MU_CNT(1),\n.C_PROBE422_MU_CNT(1),\n.C_PROBE423_MU_CNT(1),\n.C_PROBE424_MU_CNT(1),\n.C_PROBE425_MU_CNT(1),\n.C_PROBE426_MU_CNT(1),\n.C_PROBE427_MU_CNT(1),\n.C_PROBE428_MU_CNT(1),\n.C_PROBE429_MU_CNT(1),\n.C_PROBE430_MU_CNT(1),\n.C_PROBE431_MU_CNT(1),\n.C_PROBE432_MU_CNT(1),\n.C_PROBE433_MU_CNT(1),\n.C_PROBE434_MU_CNT(1),\n.C_PROBE435_MU_CNT(1),\n.C_PROBE436_MU_CNT(1),\n.C_PROBE437_MU_CNT(1),\n.C_PROBE438_MU_CNT(1),\n.C_PROBE439_MU_CNT(1),\n.C_PROBE440_MU_CNT(1),\n.C_PROBE441_MU_CNT(1),\n.C_PROBE442_MU_CNT(1),\n.C_PROBE443_MU_CNT(1),\n.C_PROBE444_MU_CNT(1),\n.C_PROBE445_MU_CNT(1),\n.C_PROBE446_MU_CNT(1),\n.C_PROBE447_MU_CNT(1),\n.C_PROBE448_MU_CNT(1),\n.C_PROBE449_MU_CNT(1),\n.C_PROBE450_MU_CNT(1),\n.C_PROBE451_MU_CNT(1),\n.C_PROBE452_MU_CNT(1),\n.C_PROBE453_MU_CNT(1),\n.C_PROBE454_MU_CNT(1),\n.C_PROBE455_MU_CNT(1),\n.C_PROBE456_MU_CNT(1),\n.C_PROBE457_MU_CNT(1),\n.C_PROBE458_MU_CNT(1),\n.C_PROBE459_MU_CNT(1),\n.C_PROBE460_MU_CNT(1),\n.C_PROBE461_MU_CNT(1),\n.C_PROBE462_MU_CNT(1),\n.C_PROBE463_MU_CNT(1),\n.C_PROBE464_MU_CNT(1),\n.C_PROBE465_MU_CNT(1),\n.C_PROBE466_MU_CNT(1),\n.C_PROBE467_MU_CNT(1),\n.C_PROBE468_MU_CNT(1),\n.C_PROBE469_MU_CNT(1),\n.C_PROBE470_MU_CNT(1),\n.C_PROBE471_MU_CNT(1),\n.C_PROBE472_MU_CNT(1),\n.C_PROBE473_MU_CNT(1),\n.C_PROBE474_MU_CNT(1),\n.C_PROBE475_MU_CNT(1),\n.C_PROBE476_MU_CNT(1),\n.C_PROBE477_MU_CNT(1),\n.C_PROBE478_MU_CNT(1),\n.C_PROBE479_MU_CNT(1),\n.C_PROBE480_MU_CNT(1),\n.C_PROBE481_MU_CNT(1),\n.C_PROBE482_MU_CNT(1),\n.C_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1),\n.C_PROBE691_MU_CNT(1),\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synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4261}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_15_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      (* max_fanout = 66 *) reg s_valid_d;\n      (* max_fanout = 66 *) reg s_ready_d = 1'b0;\n      (* max_fanout = 66 *) reg s_ready_reg = 1'b0;\n      (* max_fanout = 66 *) reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_15_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS==2) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS==2) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_15_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      // System Signals\n      .ACLK(ACLK),\n      .ARESET(ARESET),\n\n      // Slave side\n      .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n      .S_VALID(S_VALID),\n      .S_READY(S_READY),\n\n      // Master side\n      .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n      .M_VALID(M_VALID),\n      .M_READY(M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK           ( ACLK ) ,\n        .ARESET         ( ARESET ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK           ( ACLK ) ,\n        .ARESET         ( ARESET ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (1) begin : common\n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    (* dont_touch=\"true\" *)  reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_handshake_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg [((C_PIPELINES>0)?(C_PIPELINES-1):0):0] ready_d = 0;\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0; \n        laguna_m_ready_d <= 1'b0; \n        ready_d <= 0;\n      end else begin\n        laguna_m_ready_d <= laguna_m_ready; \n        if (C_PIPELINES==0) begin\n          laguna_s_ready_i <= laguna_m_ready_d;\n        end else if (C_PIPELINES==1) begin\n          ready_d <= laguna_m_ready_d; \n          laguna_s_ready_i <= ready_d;\n        end else begin\n          ready_d <= {ready_d, laguna_m_ready_d}; \n          laguna_s_ready_i <= ready_d[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n        end\n      end\n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_d : payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, laguna_m_ready_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{laguna_m_ready_d}};\n            payload_valid_enable <= laguna_m_ready_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==0) begin\n                laguna_s_payload_d[i] <= laguna_s_payload[i];\n              end else if (p==C_PIPELINES+1) begin\n                laguna_m_payload_i[i] <= payload_i[C_PIPELINES*C_DATA_WIDTH + i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          if (areset_d) begin\n            laguna_s_handshake_d <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_s_handshake_d <= laguna_s_handshake;\n          end\n        end else if (p==C_PIPELINES+1) begin\n          if (areset_d) begin\n            laguna_m_handshake_i <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_m_handshake_i <= handshake_i[C_PIPELINES];\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (C_REG_CONFIG == 13) begin : tdm\n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* dont_touch=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_15_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_LATENCY = (C_PIPELINES>0) ? C_PIPELINES : 1;\n     \n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    (* dont_touch=\"true\" *)  reg laguna_m_handshake_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] ready_d = 0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_LATENCY-1];\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_ready_d <= 1'b0; \n        ready_d <= 0;\n      end else begin\n        laguna_m_ready_d <= laguna_m_ready; \n        if (C_PIPELINES>0) begin\n          ready_d <= {ready_d, laguna_m_ready_d}; \n        end\n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, laguna_m_ready_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{laguna_m_ready_d}};\n            payload_valid_enable <= laguna_m_ready_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (C_PIPELINES==0) begin\n          if (laguna_m_ready_d) begin\n            laguna_m_payload_i <= S_PAYLOAD_DATA;\n          end\n        end else begin\n          for (r=0; r<P_REPLICATION; r=r+1) begin\n            if (payload_data_enable[r]) begin\n              for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n                if (p==C_PIPELINES) begin\n                  laguna_m_payload_i[i] <= payload_i[((C_PIPELINES>0)?(C_PIPELINES-1):0)*C_DATA_WIDTH + i];\n                end else if (p==0) begin\n                  payload_data[i] <= S_PAYLOAD_DATA[i];\n                end else begin\n                  payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n                end\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (C_PIPELINES==0) begin\n          if (areset_d) begin\n            laguna_m_handshake_i <= 1'b0;\n          end else if (laguna_m_ready_d) begin\n            laguna_m_handshake_i <= S_VALID;\n          end\n        end else begin\n          if (p==C_PIPELINES) begin\n            if (areset_d) begin\n              laguna_m_handshake_i <= 1'b0;\n            end else if (payload_valid_enable) begin\n              laguna_m_handshake_i <= handshake_i[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n            end\n          end else if (p==0) begin\n            if (areset_d) begin\n              payload_valid <= 1'b0;\n            end else if (payload_valid_enable) begin\n              payload_valid <= S_VALID;\n            end\n          end else begin\n            if (areset_d) begin\n              payload_valid <= 1'b0;\n            end else if (payload_valid_enable) begin\n              payload_valid <= handshake_i[((p>0)?(p-1):0)];\n            end\n          end\n        end\n      end\n    end\n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_15_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (C_REG_CONFIG == 13) begin : tdm\n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n     \n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* dont_touch=\"true\" *)  reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg [((C_PIPELINES>0)?(C_PIPELINES-1):0):0] ready_d = 0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] push_enable_d = 0;\n    (* dont_touch=\"true\" *)  reg root_enable_d = 1'b0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    wire push_enable;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push_enable = push_enable_d[P_PIPE_LATENCY-1];\n    assign push = handshake_i[C_PIPELINES] & push_enable;      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0; \n        ready_d <= 0;\n        push_enable_d <= 0;\n        root_enable_d <= 1'b0; \n      end else begin\n        push_enable_d <= {push_enable_d, root_enable_d};\n        root_enable_d <= M_READY | ~m_valid_i;\n        if (C_PIPELINES==0) begin\n          laguna_s_ready_i <= root_enable_d;\n        end else if (C_PIPELINES==1) begin\n          ready_d <= root_enable_d; \n          laguna_s_ready_i <= ready_d;\n        end else begin\n          ready_d <= {ready_d, root_enable_d}; \n          laguna_s_ready_i <= ready_d[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n        end\n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_d : payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, root_enable_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{root_enable_d}};\n            payload_valid_enable <= root_enable_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==0) begin\n                laguna_s_payload_d[i] <= laguna_s_payload[i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          if (areset_d) begin\n            laguna_s_handshake_d <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_s_handshake_d <= laguna_s_handshake;\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n    if ((C_PIPELINES==0) && (C_SOURCE_LATENCY<=1)) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        ); \n  \n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_15_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_LATENCY = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (1) begin : common\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] ready_d = 0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] push_enable_d = 0;\n    (* dont_touch=\"true\" *)  reg root_enable_d = 1'b0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire s_ready_i;\n    wire push;\n    wire pop;\n    wire push_enable;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push_enable = (C_PIPELINES == 0) ? root_enable_d : push_enable_d[P_PIPE_LATENCY-1];\n    assign push = handshake_i[C_PIPELINES] & push_enable;      \n    assign M_VALID = m_valid_i;\n    assign s_ready_i = (C_PIPELINES == 0) ? root_enable_d : ready_d[P_PIPE_LATENCY-1];\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        ready_d <= 0;\n        push_enable_d <= 0;\n        root_enable_d <= 1'b0;\n      end else begin\n        root_enable_d <= M_READY | ~m_valid_i;\n        if (C_PIPELINES > 0) begin\n          ready_d <= {ready_d, root_enable_d}; \n          push_enable_d <= {push_enable_d, root_enable_d};\n        end\n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, root_enable_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{root_enable_d}};\n            payload_valid_enable <= root_enable_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==1) begin\n                payload_data[i] <= S_PAYLOAD_DATA[i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= S_VALID;\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n    if (C_PIPELINES<=1) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    (* fsm_encoding = \"none\" *) reg [1:0] state = K_EMPTY;  // State vector register\n    reg [1:0] next;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    \n    assign m_valid = state[0];  // Drive m_valid from state vector\n    assign m_mesg  = mesg_reg;\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid) begin\n            next = K_HAS1;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin\n      if (areset) begin\n        state <= K_EMPTY;\n      end else begin\n        state <= next;\n      end\n    end\n            \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      axi_register_slice_v2_1_15_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n\n  axi_infrastructure_v1_1_0_axi2vector #( \n    .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n    .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n    .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n    .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n    .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n    .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n    .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n    .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n    .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n    .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n    .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n    .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n    .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n    .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n    .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n    .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n  )\n  axi2vector_0 ( \n    .s_axi_awid      ( s_axi_awid      ) ,\n    .s_axi_awaddr    ( s_axi_awaddr    ) ,\n    .s_axi_awlen     ( s_axi_awlen     ) ,\n    .s_axi_awsize    ( s_axi_awsize    ) ,\n    .s_axi_awburst   ( s_axi_awburst   ) ,\n    .s_axi_awlock    ( s_axi_awlock    ) ,\n    .s_axi_awcache   ( s_axi_awcache   ) ,\n    .s_axi_awprot    ( s_axi_awprot    ) ,\n    .s_axi_awqos     ( s_axi_awqos     ) ,\n    .s_axi_awuser    ( s_axi_awuser    ) ,\n    .s_axi_awregion  ( s_axi_awregion  ) ,\n    .s_axi_wid       ( s_axi_wid       ) ,\n    .s_axi_wdata     ( s_axi_wdata     ) ,\n    .s_axi_wstrb     ( s_axi_wstrb     ) ,\n    .s_axi_wlast     ( s_axi_wlast     ) ,\n    .s_axi_wuser     ( s_axi_wuser     ) ,\n    .s_axi_bid       ( s_axi_bid       ) ,\n    .s_axi_bresp     ( s_axi_bresp     ) ,\n    .s_axi_buser     ( s_axi_buser     ) ,\n    .s_axi_arid      ( s_axi_arid      ) ,\n    .s_axi_araddr    ( s_axi_araddr    ) ,\n    .s_axi_arlen     ( s_axi_arlen     ) ,\n    .s_axi_arsize    ( s_axi_arsize    ) ,\n    .s_axi_arburst   ( s_axi_arburst   ) ,\n    .s_axi_arlock    ( s_axi_arlock    ) ,\n    .s_axi_arcache   ( s_axi_arcache   ) ,\n    .s_axi_arprot    ( s_axi_arprot    ) ,\n    .s_axi_arqos     ( s_axi_arqos     ) ,\n    .s_axi_aruser    ( s_axi_aruser    ) ,\n    .s_axi_arregion  ( s_axi_arregion  ) ,\n    .s_axi_rid       ( s_axi_rid       ) ,\n    .s_axi_rdata     ( s_axi_rdata     ) ,\n    .s_axi_rresp     ( s_axi_rresp     ) ,\n    .s_axi_rlast     ( s_axi_rlast     ) ,\n    .s_axi_ruser     ( s_axi_ruser     ) ,\n    .s_awpayload ( s_awpayload ) ,\n    .s_wpayload  ( s_wpayload  ) ,\n    .s_bpayload  ( s_bpayload  ) ,\n    .s_arpayload ( s_arpayload ) ,\n    .s_rpayload  ( s_rpayload  ) \n  );\n    \n  if (C_REG_CONFIG_AW <= 9) begin : aw\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_REG_CONFIG_AW == 15) begin : aw15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if (C_REG_CONFIG_W <= 9) begin : w\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_REG_CONFIG_W == 15) begin : w15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if (C_REG_CONFIG_B <= 9) begin : b\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if (C_REG_CONFIG_B == 15) begin : b15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if (C_REG_CONFIG_AR <= 9) begin : ar\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_REG_CONFIG_AR == 15) begin : ar15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if (C_REG_CONFIG_R <= 9) begin : r\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_REG_CONFIG_R == 15) begin : r15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\n  axi_infrastructure_v1_1_0_vector2axi #( \n    .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n    .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n    .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n    .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n    .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n    .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n    .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n    .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n    .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n    .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n    .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n    .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n    .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n    .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n    .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n    .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n  )\n  vector2axi_0 ( \n    .m_awpayload    ( m_awpayload    ) ,\n    .m_wpayload     ( m_wpayload     ) ,\n    .m_bpayload     ( m_bpayload     ) ,\n    .m_arpayload    ( m_arpayload    ) ,\n    .m_rpayload     ( m_rpayload     ) ,\n    .m_axi_awid     ( m_axi_awid     ) ,\n    .m_axi_awaddr   ( m_axi_awaddr   ) ,\n    .m_axi_awlen    ( m_axi_awlen    ) ,\n    .m_axi_awsize   ( m_axi_awsize   ) ,\n    .m_axi_awburst  ( m_axi_awburst  ) ,\n    .m_axi_awlock   ( m_axi_awlock   ) ,\n    .m_axi_awcache  ( m_axi_awcache  ) ,\n    .m_axi_awprot   ( m_axi_awprot   ) ,\n    .m_axi_awqos    ( m_axi_awqos    ) ,\n    .m_axi_awuser   ( m_axi_awuser   ) ,\n    .m_axi_awregion ( m_axi_awregion ) ,\n    .m_axi_wid      ( m_axi_wid      ) ,\n    .m_axi_wdata    ( m_axi_wdata    ) ,\n    .m_axi_wstrb    ( m_axi_wstrb    ) ,\n    .m_axi_wlast    ( m_axi_wlast    ) ,\n    .m_axi_wuser    ( m_axi_wuser    ) ,\n    .m_axi_bid      ( m_axi_bid      ) ,\n    .m_axi_bresp    ( m_axi_bresp    ) ,\n    .m_axi_buser    ( m_axi_buser    ) ,\n    .m_axi_arid     ( m_axi_arid     ) ,\n    .m_axi_araddr   ( m_axi_araddr   ) ,\n    .m_axi_arlen    ( m_axi_arlen    ) ,\n    .m_axi_arsize   ( m_axi_arsize   ) ,\n    .m_axi_arburst  ( m_axi_arburst  ) ,\n    .m_axi_arlock   ( m_axi_arlock   ) ,\n    .m_axi_arcache  ( m_axi_arcache  ) ,\n    .m_axi_arprot   ( m_axi_arprot   ) ,\n    .m_axi_arqos    ( m_axi_arqos    ) ,\n    .m_axi_aruser   ( m_axi_aruser   ) ,\n    .m_axi_arregion ( m_axi_arregion ) ,\n    .m_axi_rid      ( m_axi_rid      ) ,\n    .m_axi_rdata    ( m_axi_rdata    ) ,\n    .m_axi_rresp    ( m_axi_rresp    ) ,\n    .m_axi_rlast    ( m_axi_rlast    ) ,\n    .m_axi_ruser    ( m_axi_ruser    ) \n  );\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 3108}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule src_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 10000000, PHASE 0.000\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(1),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(9),\n    .C_REG_CONFIG_AR(1),\n    .C_REG_CONFIG_R(9),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 433}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 15\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_15_axi_register_slice,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"src_register_slice,axi_register_slice_v2_1_15_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"src_register_slice,axi_register_slice_v2_1_15_axi_register_slice,{x_ipProduct=Vivado 2017.4.op,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=16,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=1,C_REG_CONFIG_W\\\n=1,C_REG_CONFIG_B=9,C_REG_CONFIG_AR=1,C_REG_CONFIG_R=9,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule src_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, FREQ_HZ 10000000, PHASE 0.000\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_15_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(1),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(9),\n    .C_REG_CONFIG_AR(1),\n    .C_REG_CONFIG_R(9),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'H0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 435}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nYugOLIF1XBreTDYRaNSWelgjmV3GIQ3y7FKiDB9UiIB++fAUC4TXcrfthfgN8befqwACkO3Q4k0c\nvJxv/aokgQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nP86BhFBNNa0qr9Q2+Wo0KACiIyDg4VPZdSis8bLUVn6FrcCD6TyMD6qWsX7GqSzkSyajfw5KoNS5\nrAZcRWAMv14anbm7VDJCIblrxr97wW1wDK0tJz6KsyHENdmS+W0PhSl0PyC6LE8TbUq4mev1WMPa\ne8qt1TLduNZhmfYNEEg=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\ngWBenVTIP5Q+rcNXfn1zPEjuUtszskvpUVNF25Xh81JnRdMPCp/0AGJPx+mPKwQ62keEUCK7jImu\n0uCqq7uEhg8CAhGkckxz0ziMi5p3crim/FOPfZSxzcfVA0myImyw/jA25kK2gqWItxmETSoXCqJJ\nxjTH/Kdlxzn5v3BlGFnjUMmgDpw+7ZlRLWclsVDPWcyttlqzmOpUVNRybjmRjQ047dZKoaEnV7aL\nJadzAQ1SqJzBdkDtBC4ls9rDZ0efLPq2CaHSH2lKmJWzqvjdbahTe/uDqwZlM/3ri9uvioLaock3\nBYN0ATxKAINgg8QSBFGOvETVtbNj0tmio/74Jg==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUA332GmFKmVHrrGry7Cyuflehk/VbtxlBHEATtE4ZDxpaTPEmq4fqpuW3/eIdDceGsGBiaQuMN9K\nWHRjmvo00KBUbhMYtfB1gjlmZEboE2pGVM53sCnoWcRuUcFptlHy3SPD43x91G4s/5AG3W+1+WfG\ndqqfUNJVltc7+nD/QSz52JWyt2BKcwXzXUegWHFyWPlXXyRha6uiHm5A3aFVX9XSCQMUBVg9KOgQ\nr17LLKqYda/v6o1fu2DbIpPXqeviObYOGtxIlZlCKEQ0WQ16wVhC7M7JMUM8K1ajQIP6aFm+lH0T\nT0TAEilCZfV2IBv8ZeVngUGkozMdcE2q607VAg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nJkclL4oQ89VKThgpnFORp4DkQ+l+oHyNRU+cUXBcYSussbqYTJL6YmJORdubTTO26u6Gzu7Zi8eR\nCof7Krp+GgFdv/lyHLisqmpxJDZ7fQJTFSmWQ1sN09PbMajgp5uypgG17Qqsv6Efx7DaBK5bWBFL\nzYY4TfY8F27SWO7q+F4ZXrJVV+ljd3jMxOp0CO33BlH7VTdJmnHbnGwVoy7NS7ktTu5O4mtjSy5B\nim8NDWKOPmwonslxiaCWWhRcIUWJMoS3RW+hbISleB+u2f6Hv6Cq0ewXO8bpInYwlzrVk138Qwn8\nPZory2IpEEHyD3/RAkNZjAO5MGkRMmlC6knbhg==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nP0095JhTyRSuAcV3jYJyGhT1pAQ63Ikz2jcw/xarWfO4myeR2ki2IxiL2BogiBQPifhiQ+8e/taC\nZCqKABC2nUd7sP5K5FMLxqEqvaSGhMtRO2Qx+bTN2vfUmVhFmm5F0IDL69aSPE0VUYhlP+Aw6isG\nmHBHYBCtHhMlBBTHiBI=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfVKST5L4zOIHEw8rTePPdwZAh4xL2unQREo9UhjWF63YVGB1vNoHQzJFNQi2s74hnMxp4aeUGW3A\nnhI/ztVR4LEwZ7XH7wwwmLntNjOp08e4L0SwqDu4k9wj2Mq4P87tHDh2OlNiLNBP9KNGLRKuh6L7\nrvsNzCz5uZW5s7nBY60UupCfWM5iYb05yX1fiPvYksz5uEon77IwhleTgsDLGSjDpO/3MsRecpOY\n6zxdY0uNkfRy/e+huHZvIRI9Tgx9p4p5MHkKiVX5pzmTHVFHILH/8jpxbyunuxTvGsgkRSrn/BzR\nCr6wvT7hHeY/W1F7h1vfxGVI4Ek5baJkO9T+vg==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64336)\n`pragma protect data_block\nkE3zh5FB1r3vI8ZJiCJ6FWF+XzfFQVQgnzQJ/PJpjvgCXoAs4Zjsl6nmvDpPHpRl1X32r55UNGOi\nrzvS7eJCMJeieiUb8KcN1+k9krnT6S4qk6dWAtm57amEO8+SlPVtgy1tkIGJYbb8LomTrg6JKf1q\nmpnSuP6AyfZHl1hcXlpc6bd4uJId9F/xcZnJaMEQTk2Xkh0YZwzFzeJiYXNXkaANr2sFv7jst1E1\nwJT0/zDSlQMmJHtvHYgqniLGO0LTUERIJn2n3LlE+Nb1n6im8tMfUK9/omKdJrvVZAmHwm6y1KfX\nSR5hA5hizsxzuEmVhhICN34dve/ajVFv00CqzpxQcnSBCirgk/Od85aRxbLRw7wKTDQVTqkGC5vk\n8B71OWlKiZ/nHzlwZ9hkKlT5HkYDPZN426UwuQXkSdSoit7sDolGhTt4BUWi4BL1gUE1DZ/7H+Pc\nOIDFwGjTInrdA+MN85INFgXppeRHIfUeeJV6PNisW2AElJtcXF97zM77KR0g2IiTqapwRFlRAMpQ\ndmybCFy78g+H+cfr3d76Eo7sgOSPiULbuDnW5OocD16sTNjQBvfOBZ1a8fcYC0eVM/MPfFqAJMX8\nhzpp+YLA1YWJ8/mAVQhlhjc4KKcIn0RiMbw1LSTX142bdXJMBujGVnYH2QwtVCJwtuERXFtiBcHK\nU7EKh6EAIU9yCp58uJMNIub6tmkKj3b3pO5oAxbD2T1vOSfaQzg0TsmrVL6y+n+rXPnEyvrgMtw7\nDlQ8o1tq4vjKbXAMiP3VHX9luvJQB5yRoanW10HoSFcPyGhuyvBscFIWTC+BEA3hNGyk5czChKPF\n+vMFqE5wtBfiuGKEi4YBS4B6ZwpMPspnZwYf2NHSNQqfLSp1Y8r9RY/RbhF3Hc9AAXs29XP2YY2R\nDt8z15QRDaBBCVYRckMMTmGpOJ26zR/MWF3F5a9Qf5IghfFoimkitsN8O4mGDH1avgkPNpfc/5oq\nrh8goxqhDyYi9r6oAZxul3ymzQaklgK8XVa9W2wYLPQ5HVUIzH+fx7yOryc/b0XpcAYDhsiA55uW\nxPOsFmqwrzhGoEM6/sPeESOzKxGqAuWArX1dYw3B1NIRwc/SiICNy0gVTvq67BOMMfU2jEfH1zss\n907/tTkECdjUTaTA+D9QGzdlwAnxMLZS/5Jp7CaJduYxlS3SjEgCALpp8pO3FrG3dvCbzob3X6l/\nHywXPt6zQeozZUD9te+GbwL4nVBJQoDFFiKpciE0aFKU2H6IF0YZ9bQKJKYkBkYI6Lg68EPLAPfi\nHgpWSGcq0sr03CFqAvZIennPxsmwghVPPQBDInhSRM7ogh6JVSa3wYiW90Im3BjhIeZuTVwWoejY\nZtDwCn1vqNjdVK1h0k+6sZkoAJx/tKymMzQ79DNfKptG48yUmhC/F7A6bL9CZ4J0xKpJAT+0rmtd\nwEym2mskpzCcOGgRltbipx2L0w5kmRXMdyjEta4eXyFEMAzsWznDHXMv2vq5XwM0savwMfuWTyY4\nXXPdS5QFO94+jhMoG9DQ1+S+LR69rqNM/jCH6/Zgk9+GUebipjHT3BHiNgq3pjhrhoBCNVW+k8Ra\nikrBqwm62uE0Kvj7UIagh8ZVrswAyXSLIof3/bVQAJhZmB3055LH2U/4a+fEsD4mlboFaa6zet2t\nAhSATWM5T2Rxo27bt59Gb3ZUMBPTojqEfgvWWMBvawl1GlesvaxdtH3t7LjvwoXN9tdEdhdIoXW7\ncnPRYqV9hD+jSj/wDAHBKCAqn/06LxSxEo1v06AkDTali2Ibu/LpGRg+v42BQSTALzWzxmp9OZ+G\nQBOmW0FWoBr3Np7cOgqb1y5OI+hODFfRwREojfbzTDLy7ZR3RTOCEdwJ83BGogbKuZHCe4F8fVy/\nEzUHRrXI9Glt4cEZiFsJDXxf8DrBbMCe47ZO/4Vb8CQwK0Zp1ur0bGW6eZJLvm2CZDenu+smqHyM\n8cNa+X5ZWUSZdAky0ggxJvYzGj1NLWRkA3m+yU+dKGGtlf/ZyyKW8UFiemUtcK14bXza4wz86bh6\nbsEzG2TRvNc6sbZMVnkxLHYnx/xPQrWFNhKNcb16XcXCaB6WFYv+E6+GM/mR8raMgI0K1rSj7Cni\nWyKsBmpgxTKkNy540JxNPM1vmm48rjCWehZwR/BFn/eNpQZlRe261hIosBDqnVgUvGphdsrJk2tP\nuvtY6UHx4FoZy42AjlxAG9fTbwMZP/GKLN2Wn+uc6iDBnGswOQTOQl0glpbfKEJnkxuscJBlzVXK\nbIAc516dj2fAc4P8qSHMIIMMmrRtKlyoKbGUpuCdDAGCwNiB8e2ZkD3Z18aQUYjYXrudHUOsg5jn\nIoIQN89ZyPNR6r6l7HM3EmnD2I7C4nxEzYwSOaIKPYClX6pE2lH4j3BfWEH6sEd/Ff/H2P8j3/jW\nIbBz30hNDupx7kOjNavnbibhcWayZ8dsA9bmGHm0bVu6SOuXd5uKev9QnYaVITu/jLI61Wkmpcsp\nYHhaVaSFaRUStXZIcYv3VNPkuxE2az0Z9VNN0Mi73rrXGMw4pp9YL65ByzJgP3fG97U38ltLHgKS\nn5Itl199gb7ZMl0lsAh83uPfA4iGuOv2sBn7g3pyREGWaEYieHfHKq+ju38etYApkb22FnsjfVD2\ni/YIM15a0/JUEGc64KHZASi8A4NiUntFmVDG7YkPNdOXQ5BqsqprUqtMd/b17Bm0nkxc8e426Me6\nUbOlAHlZce+4uAmZvy+E4ghu6RTfGS1y2gVO/RFbNEKDLQmvXGS0//UZVhj+TNSiInw25dxsDuCV\n6utZNSIb92gOGTuKghxb07yu8yXyZy9A4biLLqaVQU0vb/PW4EP049J7YYdO9sQwrJCoeFtVEaPf\nwo2nIVX6hOpH1aFEkrg9ERiPnt1UUXlgrQTkKdlkJvC5wQSP2ZNIRveY6jHSw1gVBWkr9k0daovZ\nz0G04BIfsbm+NtmkVJ7OoDEv4XuZ4Il00Ap9vBN8bSHNO/PsMj2JNKVH3v/Xx8eisuCdeN4Hu3Xs\nzsUtx0nJQggOIjEbi1WrdnD95V5yipfY1V/ZC5V7ii5zHDUDkP+p14NMbuE9sjfsL51Rfoty0wsl\n+MoLxpOr4NcXnX7QOWmy4aGdL8C3ZikuPP00WhtKRG4p6H6MkrAttXHz6L5wCnUV4O2kGfhkhYjf\n3yQJVii52aRvT7Lv6S/BAOJFByUGl4wpHoyfLS8dLrarEOyI1mnoeOsjefSUTMceLOKuPWkMk0I+\nLR/T838qusGpX/26srrf80SWxKr7ch0YEK9xGGHAO7cgvPQTlncT37QvLwfutO2xOZT+81H22NiZ\n13z31W0LurQciFfxyNz3bOQeKWnQHIqtFv3JGGJnux7/cOP614w/LW/aL7/YOzC8F0xM3YhaMeUW\n9UA+GBxyn9FtuQ0/g8hs0RhuccMBjsnxQzSBS603FlXaUQV2FfsfMLBL7TasPZ4rIHuUWTEu9mYL\nfWz2rZbpwwfRq35JbtQKwphJScZVbTaLWyH2Isjcm3GRFrOK9OpEZwYx/HTc9n/EtRmmZFwdUe4J\nlDnueKc/fDmoU4G3+Zw6rm3p3XTOo9DXUArS/uSnCylnmGrAaBLaKnFsQKd8kCmJX12Uj/xdyOF9\nOpIg19vrcrSE0ejJQ5dUcLrb3i0Rk8eLyGew8jmMMtFOBRmqVwscepGRMPG03RMp4W3rEJn8UXb1\neP5XFWhrxazaFOY5ljiIWHk9hYQOnH/Vt8DG01HUbQNcvQH1xHNwUIooc0fbM+PgxMn2hQ0pM6+c\n0wPfDIKABiNmKLhcHnljST+ofM0yPaynaEkePqVxWiKlmFSgAsBtBcerrFImky4wOHdJwOLvldx3\n4dVj6HduJgYtLUQGVl0tI3IbmvX6s0MKeONdhJKp69hWLHhEiYl/t1cPpLJB+SUFp/r1x1s+MzD+\ncKZW7hNtDThOdBJjoeAKmavGBoh4VHBtQqDP0lL+EwpSg25V6X9XW+dFUEpwaZ0CuVXWHBtwGuce\nMaku0HU9yyOJSHRk7R5AzoBM0QCbfNIwoEqrpTgUW78VzRjekms34MQvc6/VWtqoA6IIgPs8ybLJ\n1pXEw/utkcwR/tMBVJvyKzEp9b6Dc0sotuhEJRY553G31bb6xa7Y7PG38YByPiqfJPK4AuPhcaO4\nN8WILCcgXuWL93xjqu0/Ew6z+GNqQm3Jz4ntiHysc/AluO6K7vtwO4UcS8ccMt5z4bpA4T5arE4/\nb1eHDWK6JT2gX5/4lOlR7pJLy5qwKyffyaH/Nqz7AsCVsPZi3Qwvygy7NndJ5ubyVcHxyItssjGq\nDNBwkJOOVIQtsmfxXko9LsA2I6zOgj51rqOlqXg2Gk7DDJjUk66K8JUFHjHbyUHJoAgAJXbcvFfs\njDDBZ6zps82PHgzQSOWlueInlKXLUvswdqg8Szm9Rmfe07P0jivX7y1UdWGu42d2G9+SbnpVwkAY\nd1j6kvNq/oN/n3VLX3UuBoSfGik63mKL3qmADCS+UFhJpi4xHFbwZh7pqoTDSA81OoplAD6RtIk2\nxTHfTfakM+NDXKgW5LVuaFtBz+6XsG5LuuVK324YlMwuHsdtjt6EchzSz/yYaMPHCFdNxyRgcbqD\nSIm/1x9m9ypB7i8tHeuJrv5TiGMrS9fK/EjFDH9s0XHcvfmBsVMUNdJPggy2rEwjwRnqEXo66at/\nAfc7We4AA8PDP1d76rGrBczWskspbNfVGtzLYmsuK1aMAzAGE2VnjMJ/OJqy2qkF5qntyuXtWXp1\nXYYHmfMdE0HqigV/1OZ1p6fodgR3cMw7dqDD4xSvY3zej5zcUNWAw6yrxJEPGUhaUjPtNS7+r2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fRoNqOEwbphWrnFxpR1uQtlznt7NunmA/HAq9QD0jc3VCyUGLK1m9jzfR+MiOxGkvi40fGIh\no5q6cp6WZYQE5sG2u1HePNz260XW98o1SKmGAnVADmN9oRH+kJs27wjueapaewwDVg8pnq6kJUOh\njQd0RkYcTMItDGvp+sFqeIIdADsTHRvr1h+M+pYqq9sLbwUoz1Alak51hZNlSXhSEVXzQLkppmeO\ntB13Z6wglCy2BICINwlSr/7HP1cYop92mfeTXL3QGuFjsDOYJeT9Igcq+fS6YIfWCA08MY5r7yVk\nVPB84f/igRg5ddrxoxTIiw6w7GWDOhG+zTxF1zyp5jJA3yKcpqPzSQpf9MKcNt+PzeKm+wneK6Jo\nhpoN/97lq7oMjwcqj4fYDI3pT7J8WHKkZCIdUVNrv0PtjsuMpkuTQbOr8hbWLJNy8UKFlgHOcfrj\nOvGAARiIQRbgB0ehYmzYwrLOYCEEGz6BajWpYh+QjcQz68HI9uD0KJTeFrxECsQhCkd+nhXmR6Fd\nTuqTwMlfvUxKMpfl+zweX6F5NmHmeyPDY7Z3diHFdJVtYNhc+jcelDo1qmERGZj0HjhlAXvpn27V\nveZu3AVSpka5ElIwtvHc/TpRzjvbeQHF5yFv9E3VhZftw6+ajD4mjDYjGCqQeNasu/oomGN+bD06\nLx4hi4Wsc5ABDp9+84vB9wTN4vdXWfDxjG6e8iiMfWuezpQtLWJtxG2XnhaF3oXBpRIS2VVSE3h9\nz+2gpVoEZT3vzJjOS8nL57iPKloZn6rbf5gWqxxUAtYbGct7VUgqevGHgWDGl0dAqT8VpJaQ21q6\nFkr/uOy+vbpdI3AICEPSgGKQQMnk1kAfWxfgJ/kaxhZc4f5XlC0ZGSh+C2CWzhNE/JAksw0YQmsi\nne+rOYuBn6qvg4VY/SXyC6jNTUu4fEhiqCBJKvOpstSpQS2jYVyQK6GIEoOtvRL+AeqOwN4ylvak\nQVkg+2A6cwY7T1x3wkcNeZMXbEpORaOJMy9wXl09aJXky2uN9qgpXHXgPTZNWf+saMNRN+uBGVzs\nZjhjfEYYTVSnY0pqS+gpfbtlNOxXo7TL8OvbkRAThNpVfqwQtupoPNk2HHNbdmWP1tZGcqPsQf6c\nCPJwuj8fcPCQUh1HIZMnT9DYnr+Z1+9YVL/Rz7jLHyA2rFlsPXsEC9hUanPqMe7CAAEbjTq0PKon\n6vcDhC4OeDhfHkwfTiOS9fxMjBLTcaoTqPWTZt8ChH4gnVvPWfUBK7kvIhw+dKvaxIvX9bk/BH/Y\nB6uSJzU7imXZJLx07cEcU/6LrWAx6BrPF2/b6Su1t6eCb+t1Q3QZIS/1RXup1A8KEnaMO28WsZcw\nZQ5vCfX86ljiIl+HfGiLBpKoa7+SdP/+q0BolGpFDPCce56LZLDSOjBraFCS81FH07TgMpEW/Koe\n73WJ43JWWkZBQNZzN+JlfWtwo4qAocwsQJX0w6MOAIE+RO9Iwh1IPv1zbtcWHBpWy1yK1K+qVbiT\nkI8txebAMYWE1fJJdK/cP/tTZXiQLhiPzBsl9ezZjJsjAPcq3dbWErzH6ZEEnAKTv6PShy3Znw3q\nOT6++Nsz6N/njj6GqwN1E2zfnMNA9tFHXPkjpOfSbyTnzGEEZwPile3fiO38kzzHEjoAkb37KavT\no8WtZsohsnfTezPzzWxB9cFMtrTKv+u3cIIlr3mM8PZGdN2ZSq9ahQfTqRYp5KGtKnkkBIfsbqqM\n6M/SBVm5RMtrKRYp3/ey+lutDPtoUKLWJMnsv76her8S4uek1nzv4wTizdqJoCHy04vb5HAcgpVC\nfcWHgEVDqREje1ZKN9cggmiVpXRsjmWDBU/wAg8c14gohHPFlXNZgAA+ytO9js8szFDnt/0cCj7Z\nkDd0C21SAR1LHBI9KUf497LL8Tu6L6XEd7Tm3XEXeAS5OgHmGdAHyGPiqI9u8ClEt6BkfXamciI6\nlfeQj+z1nCxMPEJCjjzMwvV+3Ah7f/pMVMzaycr537MfD4P9+Ch+Y0vIsYpwt4zU/30BNXnQqfs7\n67i6Wfe/ptu3NRiQFhoPNGZytUbv/evSNDXxFaqwfruUEUqn0eUopvcwacq1XD9XaRIAXBGNpSoS\nKKesrN7Q6LZ+PG/cPTdT84w/+X0t954GdIewb65IP9dwf17eYtg2FQZyM5t0f3iNHe0pojKIaM1a\nmcTIJ8FIFYHoORq8DSEu6tyA3X53jjGyQRjVmLNIZdZSbRVoyoBsiZ36Zh4U4aW+U1leOK18co4C\nxLB2Om7MWuPJT3VKJMuG8psZ0iW9z0Zxrl1RyfZ9Lk3hYM0VRdpLKgxqEDiEeCVqfhlGlFXUj3wu\nacVLRH6dhSEBumjFuWq/lHbTsYfS2PGWkPdKedT/skbFeOsHLU4V1O84M8q9+qmppce19MSMwXeO\nQ2jn8v1qDqQoaq9r7Jvksqp/+A8wClhvUJmaqnTcDX+MLOJSbHG2ZNR/3PvUYpDVUrL6FwJJEASQ\nPfeLTPm7SGxsfS/ZVEf5pC70NwkE/6UEcyIx7xiVjxXhDxpA1pBvp9PRueOVwllHhE6dRkC/iGjc\nY8YKShjZxisO3URdOWXpt8F8PTMjnWoGzvbX4aIve+X5KKntuaYeQxKXCf8OJaSDgRc27KSBsG77\nFYG6/6BcH6AAXrtXc/OMZ5Hu9pwGsV20Zxo2xAGLOFRpmnHdImjGCwHmcTrhQpQH8Br0AYr8Dchr\nzb/JJoGRA3WukUlj+NanwbgVkpDoHAJD1a4ftoDvHJVleoDf867gupHQThJhVF6z8LcDtafpRVrE\nSHNxS9sSGI31+aTuQ/0YqhEiBI0k38xXFesQY1mW/zireb4cohUmw/0Nx4uTsUCRUE3WLfpwBeb4\nMp8qasvOM4Uf9kQqF+GnmseyoR8jF+xEaBjyzrsJ7WpU6EQqH7Cs2y+0nkw7vULcWZ7PtxCkTi+y\nl+KY1Ss3um8ryMQYGvKj7L2/zAzwrarkjBW4JAtWsM1SrwqZe6veUIqe3Z4G6jiNsQ4NTDb8oypf\nuYa8F3nzw3hTgsLTGVQU9pMPE08BjCvQKFqc57jBAj6RXHMnE3TWWc73XS/zYTiQ/OmvpnxjZ8lu\nvX+/r/dA5KdxINswaLmFPw3KzzuWJBz/nVwLRbAGp9IHQYa6bgjjJRm5ZmLKGmzzyuRrQXUPKOTn\ncopnuL/JvlWnSdn90TMc2Tzzm7TXaIcgX9EDepTRW4sN2XWdc4AmncQYlE3Pc3mjMKKgB95f5TEm\nSgoHGZwRKlzoBLvmO6GOz1aatdeR50BMPUt7pSJwIgfBdLnvzstov1W42zn7AgW7Su/pfCewVOQc\ntZ3KuOMYDHtAQmPMuM620hdwLoXkyIatvRSwpr0SFvGi6O8B6kQ+5QxGad7VgcpGZArl8TiH6QY8\nUrI26KJkzhP9OikTZ6om4ZAs0bloMAPotwByB7KXegEUUn/G7uE2JTlScgVp8fNt08IHyAO9ubEL\ndk6s6Dfr0H5HdXOKdMAGD3C2jl0fudKu4zYcx0s+KraQSQgLXI1G2qoLzPeW4fGtztn4k6iTlSBg\nRGAbX+gnK/iuGfb+++nrxTBI8qFUX6YIlcOAkg//OSKGJJjat28UHn7BITZnedR7Lf2K2lu2q4yM\nUFzK+WcQU2KYHp8iy1VQ7x84oZsD1hpSPIvo8xCeiXIPtrxEHjRh9OZp7jAHNkZxhB53ii81SHB/\njEzrBHa4MLE/6WMisOhbmjPDUtQLtgnO86q7gzdmJX0C1jvl0VzQx+0ISJcZc1limXckLBS3F+rI\nMi8MGBfMyw+BygdEr2f6yRlYvJdRZJhXOXmHT77UlUuCfmArP6UIswPKplZN7Q+XLflYU+I7OUPp\n3qMXyzrC5ko38DucoiwqvsXMSMVx3U4vLK9VKA3sPt/QP1E0S7tFJB6lDoYQbdTI/vUgNy3iAmmw\nLl5BmdtFBDWdwEMFan9pvoDEbzNfFkIUBGuzvnjKtAFBwA67RYWKtqglvto8q74Btd/PMxWugAs2\nRDrpHJWYNh1j5vrsdRj6sRpJRMQ9FpQRBFbz8fol8FWWJFG0S8M+zbG317tUs/p0GjHB+hTwItqR\nv15KlK1LZfgIy6o7gd1a/8MIRTXjAVUuVviJ68d44vkkJr3mh1OphI4SBhUhzOaf+44CoHK2dorL\n9MyTI6q2dacNJIgHdhaJF+ebOKOMQ0olKCeLvE1KmN4SbPr9dHBv/d7cupOKbz1XYMcK66m5e/El\nRWsYMbQf2uawzWEs8cZBm585waVMQtfAQNoE7/Rs2/2SY+vnUPguioY+EDwZsTxfJWkI8zHk2a9+\nrJrYuXiNAW4sd3i5EDq/+2Ak2GPpRmfpxb7u6NIBKlwXugW8ktrqwlNqYCtg5vVaseU+FGNiVsvF\nFIuNWu1U7GpZ8HtnZu6aFs7IBPIoYMl7vu3aDQpZG9I7sSkjhPjg7s+ijQIJ3BGlmyuljXClWhZL\nJIDVQLnzS1pM0pvibM+4youBOCPFCx3sFuvQJZk3DpKOy2HX8XmKOtbKgZHL2FBjFFosaGOqcL05\nIgcxAvuqHB/0PhosWC4fcQy9X0ohWgMLrtpWE8mEqH+l/idgHAn3azKZjNDZTlrOZEPh5Y71cZak\npKgDUjLW4WthFcIERr+HL9L9PI43LQ0EKDsQTa6UW3qJFAXgUMTYgZtO2S8RQB23wPZI6bncN69z\ncEU5z6OZdFP2CgLvdInA1tFbRhPanE7dmxgxqPwFREzFyPLMwVsw9YgzsxSxbhJODZvVY1Bp6C4e\nf8VmwXIAZt+OfsTInDC+dttMHHHCvtu8TBUbI+ZLgsD0HzsESIpV/BFvQsRAJyfHJ1Qu2kByntgu\nauKads6lHHGN1Tz23/hFq7PVfLwm2Rv+/yx5DUv8Uj7PLsaHqrCdZkVzr0ECfIwPFt7nW50xCqQK\nxMu8QoV4cuZFAJzIhqj5t05ByOQPFRcxOQEfZrShvvNR9GdpYtghDBF0fU7BDHiagP5xDQ+UrHtz\nka7nRo1FHnm5QoYRJoEBABCLmeYI2KoWtLqx/CHi30vFLoru7CkCPX2Ll5A5mIHnjWmu/VKJrgNa\ntThK/it4atG3Inp2n1vlkQJQNib7fEUdfuFjiiCQRuNtmJX+MqELiPQnVEY9VWHNKjBPREYUQKnP\nJkfsG+QfkgAOqxHLM6oCfy2FFrS9aHOTMK/+PdNJLxa769Vi1zeXV0kwzsjTsJp6LwEAdQ4xKPck\n5bRahBrDgSJfUTcQYR+fbWtE8OdbPM/FWuaIc9SEfNMEebsH/lUKGSB86OWHZNz4CMk5ebH3R5JV\n6DdoBjfP4Atab/RbwcQqnZG0UdOPbBy2c7wTzqK1i+/C1l3+nDVheGhizstvKZZdm6XehGdOgf90\nOPsGrNckYz2jn61FOH0PY9mFh1FLr+59tTVOFZ8+6G/JJcGGo8HJhb6b5sCjXHSsT78/4ldD51uE\nJDiwF+PKeYLd+bhW7XjkVvG7+LYAG5h34M4tD8XHnDUKzWkpzBJ97ZFr8lV/euLpwJ/XlVImBXwp\nwZCzDdGwiTrZC+ogqcsGqoZxLQ0lv7VhpBL8skkTAYlBc2XQufABCHG+gWEuy3TJvqodDuGo0iZz\nQzftJFbueGn7t2+s/eYkOYS6arOhlDNJX2nYR5xtrB1FbV8m+jaHEiJbQc7h1G4HB07HukZZp/9P\nLFvsRYJ6uqex6hCbbqMMHQGrId6QGSH6/q5SVMSgN2/gJFrr5scKkIFUDU79QyiUDCNwsC5hwA/Q\n52vnU3pPU6vXy2f5Q7ZwUWdsJFEI6O0jxqL+Ga7+MIwsqnVb4GlFZdjTH+jRLEyw039RgVDhgKFx\nliWSLpSVpJs1r/645DGyzIbsFE6cPjg38+CcoAWYla+Gp7OtVF5Aqtp7iC2fGffTn7TvJOPCsVjY\n5MHx5QGSiT/mOGO5OVGVbXQzgTu/3GVWMajEmAq7T3+Ddw+yw94k9rT6IDk1t3lnruZSEJTPTyok\nw+bsJPG7RO6DcD66Igd1WzLO5JiNwENjJVrvbbBMYTJCgVPc3hJvvFQvfkLiuZsa03mylgBXKHAX\ng1TT+hvmb6ZTIuNi6x63/487ZXtXCLFNhUfNlssg6Z7KCyDb+mOiA/8aaC12vb51w7SWXNrmZCWd\n7wJVMUngtcinyUXoTuPe67Tbwu7Y3zQ3ZBvKMzu/YFyR0SsSeD+/yJ1siLMoqudSse4aThJOdPbm\n/YEW/tF7aovwdtXP+40gIRqfPjqUfFDJzhIh5XTJx+5XI6b1ZNJdT1+zC9ZCv0wpUCNzcYDWP2v2\n+73X+DI2B9Hk+GQUz/uV+HUBxDiALLNqS2pBnu03BRN2K3Ae6udAdykdB3XrMGU3apddVfl2Qzxp\nIMqedE5qxJzRw+S8ghl7CQ/HLPmeR4VLqSCR+4vWCWIw/nWGOStxbAxslLYMvqSQqcOh9SyzCdy4\ns+S2RDRsuoiRadrTnFE9DK9AV7YVbx1TL/4UsryqKTyD6TZgb3LhhYOUcpIpv4eGF6c886m7YxCy\n2UDtdlk5mzEa450taWmN0KN6rx09qVH7bTyCrbrVUDBIPLqFlGt6zsHsfsvCJAI3c9lNyy/K4Csx\nnVy11QZ2mZmv5FNhUpC9/LR77nEsEfKmmY+ZvmK6ZHudJHG1/VfBI8FoBMT/fDIUDwW+BhOel/Mr\nViAUiihouIkWJnuBu1qd0eyhHAEwYLpl67lU9OZtC+Hw4nRKD7xL4yeaFxYMdBRfHT536DpZkC91\nDyLn1w51UXVeDMGmEk5w/suYHhiKKlsSF4c+HVkT4yWcG6HjE+nqeKji/CAw5c+5piMrQDdaQcJW\n3nb0iIj0gXRBN+Eotil3B7bIpwe2t+faDTQec05jrigHMr3ZgWGPMkTWRs4Qir553sMKABMSYkcR\nnG1bX1HCd5Umeid7Ko9w+QAO4nPsP5d0GRtDcIyTVJxEMoOOJPe6s5d3iX9a55AGR4JeQOBinV5c\nvQTaqc7NHTeR4spVOyNLX0Vt4r4xYeQPAv/7STKb3KraVueUbYH++IptBnYURSH+JYRUgLc3wOAY\nvaIiWiWgsMJN4S9Tj57MZ21MxkcOD4n+daasVl9bXICg5bV/qCKv8GLgLa75Lmkb/q5ZMWqIh9oE\nBXG7qwnhfQdr1GBfNX5e2CHlpmAsJSuPYxfplnTe9x7rmzk1saELs+J5Zod3BW8s9PqEOytiKyFp\nNgIyYxnpDHg3KfkpBCzAqsNwFrRhkG0cNj6GW0rXcjnK5XVsm5EJsIpUIuwUUCM9FS4M4tQvHqzr\n1S0Rwfa/ZmOL+3kwiLwUF5yWFKNs9N2uwmJT5wYI/8PK/4X7jfYBxLNFiM1d7/Ot/0CD2Ygqno20\nGjj8idQj+8zcvopFkqmlICXcCSsY1CN8ytSbrd2KnMUs733/3JrtKjQJchP9IvaMZn4C8GZRjQ6B\n2FQEh8t7rEVQECSOxQ4L5fKxi4VjvlFFV5om0bkmX9dxai9YM/IwxOrmiEVbScRlOGYie5dHSd5V\nk90VtMGSxisAx3kJM2aVn69wCxymu0VbpXmPT+80tJOSJSASfShtKF9vvaTCkQlfQzw6bL7yoPjh\nwEpRBVB8nS+srJxgzTpzxf6kWSrfKwaXXevwejax6otuoFF3YEUOCVQgG2aUWnXPnlQBNC9MPtAr\nmChzvfkMA49tIz4Ra/kpvwGya9myjGuIQ+DpHiMvJrcsopWNYHjXYldeCzHaIWvnSOHGMM7nBGD6\nboOM+PIpyOs0dw3ymADCy1T+tsTasU62qNcuquHRip5asAz3bozJHUulZhGOlVgRZUNdbA/meTnk\n/sjtLjzMLOoPyFtPJUmnUvTECUkmGukcIMhdEnWfA+OgOzrM61GTUK5bwGME8XNRsprWjCchp57f\nxii8cEiyhO9Nm1pmdrMnxiPCjIW2WSFsnp1BUNnQEWDbigo95ithoSdZejaydDJCNHQMVMB7BgbH\nJVUUva0f/ZGTwU3kz+FTzsT6PT+E2GNMZm6rzSz1Q3yNoH4OXUbJwQ/vRFtTpicFPDJoLzVZKQ8T\npYc5LFd897P0DLzZ8yT219GrhNpk8PgFDRC+bylWmXrFl+BbEfkaO9VEr+LIfaNoM8p0/YLHLo0l\nMrvk/FTzdn5XhFvxyS+Sky7a8fU9qLu5xKvwZGoA2MbCvP/9924WG5xmAmsvN7gJQ5JylMq+lFvT\n9vBEEkmXTi/zMkw0f9CycHzh0eBomR3kzWnpWRJ8aBj76yXKuWdrSZi8qbVdo8wh8eb5xoIV0ir3\nEqgdL7Zjn1IcBmqhcr3AfwkhQEaXeBA6hqImHgPIpyxviqMTA0xjkebO9YGuzZAUIa6uCCzR8XPj\nbYJjNkm+wZNwzr79+h2XV6wDs4JS8VDdZcAVCwvmjHY8WHHb0jZTF+cMbLcUDsGNXONUc06UzHa4\njGjOviVfcTwRaVwQs82CNgjt5OHwna+Fj+b2mGBEyENynvXGlAo4ECvuBzpI8LU+ABqJINwvANwS\n44b0GVEJNVekwlMSByybrdYq2Lca3a9BtZmGtoxI5vIDG8U8CGIe/HaNFpFIvuyGDgYAGr2eb2tc\nhbOnJu4LASxc2GdEl6I0f/Z0R7seDGa895BuyGGcT/HYktcCq70sTyk8r6H0klX8wc2w+1UT9sPp\n13PTlh3zLdvGFzKPfIx0Bovn0nIoViJ/W+tgIbtcCnPhaL4gh3QePzoLOGoIWzrZKrfXdQUkepGM\nnGqctZ3+0XpR/XS7seqRDlstOjCXkPam6oFji3lfLKqM8ABKgItNsWesmVaCeblTHDPu+zmR3Swj\n3XSa7hlf1r2EC1jqZ+oubGX9WZjOz1p0gsINsM9ZgUPOKlzt+VBwtUQGbtj29NqAdJ2m+hFTMnXL\nwnUTOLl4CkzQ/3PrqSxqEMLrVcMbDav1VqHyySeQ9SUXcPePCnXTp88Ns0q+RqrpL9STvlzfv43d\nQWoOfT+y5jzqBr99d34ltSn1jq5Mk5kfg331aVBVDGP8CPubrq/MjnUyQ2o2sw0VX2JfGMN2BjHw\nfFEQGRoV/qgnxP+Yg/hdQHYj+r8qrXledHrHiSIHvAPs4IQgUCb7GIaSaT8McI1pg/MxpBTzTrLO\nHedJ4drTUgQ0yZ/iYK1+QT4h4+42fAkQ1PTj0z825aLEk1E6e1O4mTyuokRi5lFL0i4Xo2nnJmcg\nY2HAeYmkS26cU2mggoFsRs/ZxkSkF1qMN7lvHplO+1XTHO0DVfLkBuhEnnqTZn8rhmPL7cnoZaUH\nZ+WcnLY2VJJpEsl14KAieVLy0ABlPd+RP5UZna1k+42P6i95rcEg3jt0xbOAbrd3GZ10GT4chHwX\nZCLWJjslyLcbPGL1XdWjgDMZ3dtfG0z3hucdHb6/ueD5YQwPMdQIir9TjhHok4WPalVXcz9OwrDv\nkkUDrWxC6S8tuOFRsk6jqShA+Nv1loaSF+IqNB9sfeSGW8EsyVZIuI1fnErGqbXf2i3DInx/KFau\nWTBKYaTk6krZM9fG1+OzTGuQ4ubpSMe6o30MtzdVl/db9M7hv27LYlU0miFi0OmEUVGOOZDK+gSW\nYVlr43tdFyGvXHSuVyUe8+IhswC9IOCUS+h418D19ZNCQT6af/VQDeVmfOTnnZpP6DOc5p+hPFvn\nn/ISPeLm5qeknJULbDWxnHSxTeKqsw6FsTlJo72ZuEd1zLdA0lJqNxSH7YKQEawd8S0tE50OyfKP\nJjTDQ09tW/9msny5f6YFRscHzIbThNRsbQX1saPn1Gu4rhrY5lijfWRBI18U06gYijFIC5rZDP01\nVBYwmOnQa+ODOGfcUiQmM5pZVc0/4xmoHedHdwn4afREXvUzDZpKM2ZwPhNdB/Bf1RFqcRr9sgEf\nIub20BMNkJYzK5VVtGRXanivzfdoCbqJo4V8P/5J/jpsiDuZrb6BRaaYsv6z0mpEcr4RDQLHVkHN\nuy/UCVRX4N5yYskMUYbh+yf9ItFGH9xiMcWEvuCIcyyyXxQdjN8M72SBJ7rSGqi/iT7lD6zS9rCt\nQ25SxFqFjyMFb3/PCyopcf+doCoAKth86socVbKc8wQxwpfsjnsmDg6VfStQW3j6HbTJRR6cBKWg\no4hq5QyH4OzFyrWlze3EVjvAIRNo80YsifUXn/YmjqXkqejTAMs5rvnQMXvCCx5iTbO8GIqe1ZIO\n6g9nf6cdH8rgKjU2irIjf8wuR6WdAKliC5HyFO8HHKQ+o6jDL3Gp3V28RPoZe/ggfrNdJXuljh2p\nxgmoX0sLC4F1b8ary0X9O5Uk4Rm6NbJpHEMhDyFLk1/DSblBMxjOyWf69ua/+JJBU1aCUg73Ef5C\nKAF+0i0bW7wQ+1F6T3OIrZADAm3G0/7kCMyEk/pFhEeiyRgxWwHJyu8Lq3uncIQ6F+BT7fiZp8Lb\nzeD7TYdel7zVmCJayJKdXAqYfe4tHf2ggNiRQtb6rW7zzuDWxC6j9MOehd+wYLkKuWxcheZiDDGY\nXoW8Dn3gDgb6qmAR+aoQ6SUd0NHC2KkR9FKyVg+bhUh+gryvAjrRb/wdpK17v8W0/2ConYAt5qvV\nSx9opD6CbxukzGkKByTs+VXu8lWI81F+WVfosuLsrM3FC7WwGAbBF9jP7DkjemdKvZgK9sQ7+E/w\nykL8i/agCWoq9h+u27h1mXU6LVJOUIupwTkiLc4gn+eMXDqL1Zs0XW4Ft6C5zRmojOAbLVdpcML9\ncO8kViI9Uir6g48iHpcD7UCRyJ9cYSxliNW/0Rb9paOHITEcA0vN+6M2stDiWjLaznLsiRPKqFdo\nrfGWs887UdLqjo8r5gfiIx3q6dJCU+McJNwPj2I3Jch/01qA1AnDeFImKz1P1Q3HCe1YUpwzVdVf\nPkhvqIK1pUei69jyfiI5P4YZY6+RsP2tTebP3EhStUcOU/D0JIBRQ3VQrJa7Jzg7XWISFhF95Ti7\n3z2sHCcTzbDUqq+3k6gp4LymdHgAeI7RRHTNZ1hM3gc+e2Uv7wdyHBjADM7L9XBxGBNcR4RN5X/O\nwHBTw2vsQLZ+ETCgA03rkxnuHqpDB0M1lN0U7rKFUSuPu3NDS4bkCedhAckj6irfUrxnUC0QgoTs\ntFKAHU4pGb6keU3Kg7myTPkUugg3IWlMW9CYcpswzcYlzxnplzkXmUsTb7yUni/FzJOxd2qE3yTt\nWQa9KaZrnpU1W5773WQ03FUrxVsCIZefTOPmIur8T7txGR8gnCqsv6QBEWRakWYYXlNDPF2o7A4r\ncVeo8ba3lyADQB+lGcry8YqZvA2wzuQ59Ct4i0KA9Mb2LF9KQ7bB1/9OTdfRZWE8PslluZPYlEzU\nGIiorzNfpWh8X4UZP3wT2l3N9GODYuwlA54ZzhLwHUMEGM/utYMeZ4VrLFEqJHjqnVqVqEm0obrN\nPZqP5mgXq3WGmC5pYfblJggRYFU1uHNmMHxPLzFUwLZgD7GeQfZGvj2C13G3y26TPQRTpuhDb35A\nvsAETZta7bv79C8GhKUuszAXdEQqSt1AoFC0iB1GHCSIayhEsCwyn0tZAjwF4K71go9RPoIkdhxL\nkDi3AoLRdpPebNp0ZkA9jEvHY5jXMLUERzVAQloyXoj2mtsRNxGVEfImCoMq2ZVf389ZlS6517uC\n4F4WcDbMyf0BmdD6i/dLuCSP+aCs2mm8HWSoppsZuy2SM+34/m/fZC3KiLWa61trhcRHNacVqLWM\nM1ySVSUKbL8qF/lX5NNiyWlQ/hIKgo5zbSVAjFIuGdhB47cwhr9qYQOyQP4KYaqkT8bOk0gV608H\n9Su7bdsKfB78LbLtQvLgcdNmpq12lLrtp9JGg/aWPRjjRaXmzfcImW6wBiDh0AY6WYpGq6NDGwpA\nhLfZGiij/5kgTLLcNTwUpioAt8QzoLhp2p84Ra3LcHOeoAkKE+yMQ4mK09MSzL3P8Ld3KD0QDPou\n1mkPSzbvEsAv4b6WlnAkHgE2C1liHlCCPEIbY9RLAAIFGGASnOKMf/JBTcFSO9khlVSyREctfL/+\n+2sm5V5I000OI6HLT4IQGxsyKIQvLst4SWJd8GdsMkxBNNQIYLCFd+M0FLfYVnhAzTiCmhTAdxgY\nRnLY7sYZmGyfqmehgJkb1ErB7sPfr8vyZ0Z0qTGm6pysX+dmnzDmfCExQjMKu2kaH/Jnkf/0K2QE\n0mcQe+kaAC78lUWAaER1hQxg/ftOI+igRhks1sWXY8MhssSIc7iGfYiaSX5yUYwzEYIHyeamk+D4\nBGZ+YPTRPzSmZn6JHsKxCpVHspJambLKzdn9L1iverJbe9RBJ67u0pDof6txNi6q6cx9UXuddpCI\nADEaNB0dJMRmsoCj/fzzaSGw17nmnS+BC3WaBGJJ0aCoAnc7XqxprYwTNjCwcfmnuTnz1ll4P6KP\nR+tCsMDxVPxLH/eOccJdv0WR697d04aU2f4TlS+gELkIjB7NOCRbsRGhdrgC41wGRaA+u+ADhUP7\nfgqEuPYH+Xlvsr5QZvd0mPJRtUhqeR2AuVxy+G+kreN/F08X6X8tMFL6Avnl939hF6Tg7+BCy/Kx\nsrsD7ivYDRBQnMEoH7qkapYrGwu2L/ehj7ukBgOh/3Ejp1E+c1s1tWHeKPFMNpF2yx01Jy+5AhDZ\nPSdTYZFa7GgCvLmaicDHdeUnz3cvuYB2rZDX7nVooQnhB8Rf+6UTzaLdWwGrNu6c81vDrNUZGidl\nQpQwK1Ec1ecQqUWRK/KRYcg6m1Ot+IeGKFnPa/63sxwZ9w5pVjXJPGPrKvbZa+Pia3+MyDaMUQhw\nBm7TiPETp8qNL5v2hc4ybZJ1/NoEc6gdnGO9J8VQT/rE0pdpllH9k8vOItKpkEd0jdM2GPJK7ZuN\ngT4VCNV6rhNPeauuN4NuXgK+v3g/K4wTktuiZM36cOktYWhuiMZu+ZjnMmX/A5QrpZY+t9Xt2bxy\nbHncUMvFL14jNC6856bBlk5GSJjHRntBzQZMCIPtVN/C7jb/kxC/Q7mQMrWGDUbmc86VpIqxeQJW\nzEbg6DHJt4qOKlU6bzOt8FHPe3nnL37FuSrsjXpMBPVMzU6CF7izUOh5UBzaFpu5fbh/g4VrqznQ\nSEQ5WlWoVXW4ZN/ojhEvPD67BMdowjFSWDwe9HlddgB5BC49PAYRBh+jjeP9WdnkJ6GMfTXpMvgJ\n26AvgS3NcETqckZHSEGXEL/OPVvIwi8nyhmM/7l2ITTs1PcfqQdiKkc+COW6I/hfYNUYQTh2Aifb\nDt5iI9OZplitDHVxotoP5baEwDpoUsYSWH4r+9DsqjnnDi7BzEOGahmcDVhlbI6rjq2uhPt+/p38\n+LkfOBeCYUg9lxYke403tx9nNLtpnFQ+qSkNG+pUBDWPYGdMnrduCCwJnxaR20CQJOegEZCtYDGD\n2Pz7oh3uP06B+ju74IrcowxofXDERrXjwd6aL2u1rgWhjNv/qvk3swUVmQ2VnYZVN2u1qvFFwOLo\n8xArvHTfDmfdrv+mnz6ewWhBNZHVrK6zR44f5wUhX3ohSyWzCmey+ygAmJrPygJtZw9dvtjXPfkP\nmq6gwA+UUZ2D/1HAOpktggmARU0cJShJJl/ZQbfEq82hZjpZo4tj2wQquzt3CtJJ1biCnMf7MQLu\nxD5o0THKOO7mjLvlVn1vM3tTUc4TgSqw79cpS2caat1pA6PVms/BbFd7QjoHad+W5Vxhj/3Wdva9\n+rbOmR2Hr8d3OazwSj7QDN+4RyMmE12o2q4Wn8ZIxoD3tJCCKuOhqSWPDKASZv/IkLTin6nfXule\nIs2eVAEvlNHa3yVruUydEwXXk81lM5Uw+tSdYhQuqPKwBTGysUzTYknJlqjnyiJoXPUd9YTrcDuh\nwFtFWGr8LHDBhe8GRsZMvaYVZ16IRpnWVDZXGMMXqJNZhBDZMowW7UiEdpYqEBpvKHYMG5ASHsOq\nH2eZFgW7h1wB2fWRp3zq+htPMYw1HPP+PNgsCtaRQubfV2+g8YN7JSdRuJVQRKB7HfbRlfal4MbO\nQob2YcOhWtM3Tkow+j+pMAfbns+amYldYEUnaKZZKXgICtzUe+8tc6c9xgVYa/sNKoIeW0nQBgNM\n4rCru5DDjI6BMNPTgpTdVNWaZG8SR5DzenlSrkXBFykWTQ4LjxfY9iSBnutE8jbzjzwPekKq0wC4\nGfTVpOKVUaTaZo5wkojWs42LwU+Fh2ieJ0FEh24ZgSmFkbiiKAU+zrc3dANLGSgsgvCfVs/nP9OU\nJ1hObUY9Wo98gIoZr3Gz0C18ojCwZEb/dDxvyJM56jypCZsl61dYEVTjoW4z8i9chA1Mzbxs9eCQ\nB/SAYWddeyQDiHx6tFAi0C5AhuE8RktZjQ2yt9UFiouVgJZ6wAl/my9J6gKj2Am8k7CzKhlfV9F/\nVXJXNDBDxuDiqSec9vv8heMTxQL2hvtaZRbS4Nm2UH6mj2L5VmngiqZpUahulzswui8rW1Y4Wnfs\nKRTh1jiCT3mA0NfnDcq01KTgR38nkQ32gdQ42NUQGHAie8oiq3p6WSea/2JzXYXpKZb+cH45ODro\ndyUi4j/yaktRND+QJjGGrC4CC8qT5iwirtXKo9X67CllayE6G25mEe9A+huiY0thk+QYib0Lmnk1\nc5S1eJxEg6Gq0HMfuOIW8ogQTs++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qvZJ+ZCMnS4whysx+BCN7ma6YkyIFNzyLTBKHcjS\nE4yr0tuw3kDPz5v78ORBOVhPwizhH/dYdZV6B4mpONFDbGpxkNkVK9fLeTarpzCabmO1Cn4BjkIp\niiT9kovJnycvCa/1N5GHTOyUxMQ7cIlR8GyuJ9G9vjXMwxgt/iu6Nhs8Xf3iefAXLo2vTG778wZG\niKCTTviNxG6RCk8eWCflhdYo1C27j+Rqirx/r19s5oysIyqAS+9JIvOVLIg8jHsKyFqJoA/bNCFW\n0Ygrq/HNoWa48zWRfKr+os8ajBpjXRLOUeJhAxUEyFZWwKTJX5nTylPs+PHtuQ1bmgj4YfnGYxvl\nKvPBm/3LmGttISWgPjv3bic5rgM/YbQJWlKrDbIbTkJM9dGIVqw26kNaoKEGhqo5MGof42C6lrXE\nqRv3QktEZnMKBxdGhro9rM+0/4QV+aqX1Mk8X2EShfFeGJrur3mnwzkou97INnrS+JcpT7To5jQU\n8Ig/dgCx60pkXDh9dcoI+//AXBmIMTNEgpsdZ6wXK8vuSIKnMPcr0ID+Ztxy3w8MRNBtswnCnLsp\nhBP2QoArHvrGmhDZjvRiFpzhslgdPyiMeHyaQCICXKOF55QZ6sa+C9DkTJugfp2EZQIga5LrSTc6\n3rppuK6lJ1j1+cYnKipG2R5TcJtZYEWShSakYrnc7XPyQej0Wmb8qjCXO+hZmkIwnMTyoiWGBcYM\n09bc7DVHXvI+nlwPUh2GB0OIBveYyuUVzALBfiNkLkfMZ4Rqt8xNNMrsmVGziDMhoQ6nUl57Io/e\nlClBb+8fioCu5h7vDGc2/iMQLvtjWVYutiTPp36vtvUG/FoMa5MrJ6s5MCEAqI85DRmzUcebGP4v\na/K9n6bF6KBPBtScqz8oZlfhCGDyFCldXyqteMR6RZyV1yKKAXiBunsqmukS0xXpk/0BUbHgCbDd\nWWxClazeNUXUabl4DDzfN82FipbyFe8ShlLA80QBEES3Qp/u2bRb2cx+nnqcV48ReQsr4Pi9H68u\nY4jtp/sti345Av+WI96CPNYanltsmSKatJe4mN4X04++5oxfI0B2IOB6ZrHLPPB4LAPKz8/FiqsA\nKrIeX7V6Rw3X6sqlox+6PvJcpK/xrO7wCPcz33aZT87UVbK+rFka1xcQL+8T0yUDvGoKsX+1SygW\nWOu5fA6jInKD1e6gct0HWVj85CMVGApFoaCYCY+wKsvxUnJpbYgdRUMDayFyYOcSvPcuWrlc30NT\nzHXrPRalxD56Ym6Q3gTiEtvwj8PegDnb7EtcZ0uwjK8OCt/U3HrmFEscrH8i1q6alcAPKtq9WK1B\n0nwlZSUaYz+DnXD+fdlzQl4B6DGP+z65+kJ23NNlQ3O4FBsE3CVPVS1jInQYFN1R/MZ/NDsNKcT2\n/9HOVf54MFx4y4KYpD12c6rt3mrL03cr0AqQpOjfGPOzxZAOsxsGx5pydhpitDOsT+YLpdDok65f\neaRNQOciBmskv3OvgyoedBPWUtssp4dZRWivjakHQ4nyzSB6LPBzdHKugKM7Hiagzp3TqwoBg03e\nocqaUwsmLbrrweIw/zClSv0Ybb4PA11ZEnYLUTtBEF5Nvzl7ygkiFthizCzrS7TZkkJYYB8ltUUs\nzcOKgYFoNkTomQdhNHo3sWyNjhqeCijCSV/5+PllquArtqQuzLrMaQkCdQ68163mfRWsbzKIUbuY\nLAM/FnMX8/HTvqZl8gSN1yOdYrn5yUM00CeA+ShEd2TiKPWygLaUZ2MTv1YbNQJTZJRT/XYKjJQ3\nPCmoXiiSpSvl1Xh8mrDaeqZI/CR5Xo+7ItoX/fwwHs9nhipM6AOPthpsCJGNSpl95Qd3V7BZ53FL\nDAc0aOuivhvZCafQo2FPwjV+wmeEEBvTX8fZ0KYdJ9juXbCU83XRxu37KZxX6UieHu5H9sDi3v7y\nlMOmlu+PZvNPh0YPNzUXb89xjhl/XkrP5GQB/Puv9O3TAheVV2l4vi/GbfC93y/h1eLsSzkIHVAq\nDQKexnt5GJrnKmPCE0z6exBRrNPLJRxivLXsgEfcNg40OJAxbtsiL57zWkswvcdymPifzKbue5b1\na+sAZQZNc0yCKa5H8zy5gqK2epyicY483zdRS/BDHGdi+H2zwcOinQEbWt1uv6iKjOin15tbfsvv\n7PidT58wPRvkJKx9xaeJApmPB0x/z/UQwCGQCSp2PriFN8Yqv3vrUlA2A97FbW8rAoNtU8l1PgPm\n67G92DFxvYzMsjrFLicOXoAq0jWkESzbR0DKPmaZKkIShNKFlJigWGDVNPpMox1bNvDMH5J7LPZ4\n1wWixDY/ZS16rUbmxHdvfir1t89trPgVxF4jXaQcsnokQwDLQjjj41WUeZR80CcrJ927rx+f7tHr\npWhF31kQEDHgBvQBT8/POvhWv4f/mAfNwYSWylKvRAH6+sPoo361/wxXsq2q8Tc5m36wCxhyKS9L\ng2Wgjd/tDIGqlKNVTMaROSrU8YX9sZDpIJp9sMvnO4p818XDslDKxx1yNDIG/WxWuS+1SajgzUpe\nihK4Q6cnKrw22SD76yZE7Q4vtl4EwPNAisrd1ooqjIpsbW62kz7zPQFK0I6otG0rwwZ5YidX8FCa\no5M3MgSB+gDNka6ulGapZFd0IpvK4uRo+QQMULNO7QIM29KsTg27G6vFaAOPAjJm9gt+1WYOE1XS\nnw9EOd13mvBVZ+t4t+TY7SwE8ThnyRJ1gZ2L7Sg//93GTdbdEDlFiPnIzARxJzBudVU+3QEXE/RH\nNCnfuh3DaThukZSnjIEG3hNae1YBonjqFdbQfd47oOPybmPm9X1U+mKxmuPF5OQ/GuNe8oxKnu5C\nWdufrxecSlWnGMusxb7gbzcFE7dDL/grNTD9vQ/JPVDYfXmsBbGUZm9unK3Vun0XjadGgvRH+rfy\nC65jgpDIrKeWZr+oQW6dRLHBuYKMAbwSJE3BoT55PXuOH/dL/QvfZN4kgnFmo1yI9wgh1SSvF0Xz\nHrdg1nZp0NStwjiZURc8+UtEyOO3lNFjC8djdRtJDYf44YQZjyDZQtd7jdIl+TXJD/GcWnzhynwN\nTGmG+RFMk81Hr42hNMuaghElfpVbtIJnJMYlvmxT72ptojCXy7hczYP5vFEW0g++4dz7DZyk0sNM\nUJimDy3CDpgimqEq+KtxF0vMeWWTt+pWI2pAwsd4GfxrDcn/8ApWymuXE2ev6QGhkHLWwvVP0jHX\nwQjnUKDfHwhhe5WrWbCdPHGiDLEZ0ad9baM8ZWRhoilq81aalMGswIzIEzluihzHoobJ/nwjm24+\n9Gr7OS80DeyNDBc0+dtxoCu7ro+OWvfxl7myvwwnvq+AfPzWUcPNnI0K6xgIVpngiSqcjaGVFudV\nQrunp8i+ykRRyNhN+sH7p1Z5bWV0RI++6WWCOO55zp3fINIipPizzRWzQaq4pS415l+BVYgFiF/y\neQPnEFN0XhL4MlRRZQ2C5cVkej4hQJoTFbXMCCGzCos+M/6WVnK0RgBYp1uK0hcpwPz5yEeRb5Zg\nYLbRBoqhm8M5Gc2PfSRW5LWeT1NVikspCC+zO0c+2XEcl74GBIM/Os7d2YPYnQIwphJ6tcGd6kJ/\n6zwtKae0LKo2p4X8J2/LXPKxhHToHjnZheRJN+Ws7bhWQb0awbS4RjoAgxQQ4Uq0atWMLjk0ui5J\nO6HXgVWzY+jzCoh6shHixW1+BvGwxUy/Iy+iUwU9AYeG5W9S4ZMOP0FKCDu/DhHOWn6AHJxhRDbJ\ngZsCnwtrzo1teetnUOZfEc2eqto9SeuZxuHeofUJRFiimCVDXSer9XnIc94XzK3r5aGLtlQdVqXE\nrXR58StHCXah+7I2Igw+8Yp918fUg5/ARHntXb2ToyiogzGS7wLlx0ZRPZ777PmBHNwDGr5D22uW\nEylrVhpmlgJfARtHEke46DXR+vcLzW1K1Z5GSyvnOQVOYaPE/VSF0chC1L8aXm8TykNWOsqqFHqa\nizB9aKBGwoBrzzLirm6b4zIbDOMD4bBsmTTVjn51LN57+7gUwWR0hF6KmUNuGDDJsPb12o5jdpC5\nhuzsXk/+le5CG90IcxAN1aL0w6s36e8xoDnShTDihHvu9Npu2hMrXXYIAc28kSLww2HdK5Yi3BgN\ne1zSyMky4ACs+RnGYvWHmP0lN59X/+mLcZRnObeYLRKpAzRrSNi72f7AU7LpdsxxQAQ6q6jKYEs+\nA5fhmyuUW3G+AaF52mpaRE1OJ+YKw/qLj4R7boI5jZ5P40Z1K1fVRCenPEFX6IEb2NcOlgNjLNCf\nfiMF5mYFGz0eamcRhM0RItlZkWNJe2Iakazklay7mW/V42pensipU39nBMx5fq8myPltRu6F3AH9\n+zWDsJpDTn4bTYZXpOwTmtNiSm9XnTZbviehgqe0OHUHFby+i0XtJmTqoqQHlJSEt7vJuZX643wx\nqEnZrxMcCR6p6psZwcxMv3qfVsMQtWp4UB4w5T1OGtxY5ACFqjDFli1CChYwcHDdP+LnMOWoJReb\nmrJPq1Yp98ZTUpmEAeIU9CCgfbLLa9oyCcHfVa6Lm2ZT33E/eeFer0L+PPV8hloIiWXjWvjIyKjx\nInZpJy47H011IlrofI5xNkU7Pun5+/cabxuuL6bFc7Di6dNJwwgrU/FBcutPz6mUQ9ATroMac7OG\nn8xMFAdWEXH05T4KcdPP1Yo4jKE77NYu1JOtTxbSKIciRZGFBKUXwkMfmkVSrio/6ZvPUSO1ATxm\nD8rndadTmvy5U4N4uwE0LDNlbzRBrQEpJQV8kX6Yi3njGLHUes0x6NIgE2ou0eMnsNiXggENmqbR\nXq/UGbY0yHLg5mnmEXQX2aJu2kj73Jqxnf1ie9QhkqxPTt9hDIcb5/xqpdnlQQCfdmXPz5BAHuMy\nyTpHpGLeAp7Q2VyDM+6T/k4QWVtnnQd4yR9oJFdO5c1caLTt5T+W1wBwgGhKtmqYsdb3dfnfuI7P\nnccUl9cC0cLt8jOVnbVVklyrsryIvWClOEhTSaOwmmsU7sQsFBPLDRswYednMSaz3Fr/ldTHIH/l\nRNf/5rPL/sepbycc1cnYhL4lMI8PuuF3TpikP5aV822eIq/itmBp5FeWOFTlsPpExv6FN1KtextJ\nlm8ikFNPEI/rvndxBE+5kqTA7Ut7SiK5OwIWlDxbFKX8GwaSkh6gxecLTN8/DjhU2R/uuTAZgWRY\nAHughyKHd4V4LKBLK/VNlu6xGLmu2RPpAlV5t32adrb9OdBS2BSqwHc34tYnzT8F5JnIiYqdjlX0\nCFtcql4nv5ea9dSEaTZm1TWJIl8yJanGq4vbxLknl/vgtBrCc9OF/ENyqUhEop4c45UYDpCLaAvO\nCDU+eJ9/5Q8DxVE9cht55IaKxVEhUAQjahx0UMIc9zzQWo36xPFw6efhpXmCPHzDgY3CirPIST9U\nZtJNO7hsvkRXUi6UF9k3SMoQHugIltuGT4oaN2ie8q4hWQAAFlHDbeNSIO/OzTZJFwRltUzW+eP2\nL6SjbIXFBbYeeGDutFw6WZHmhNTePMBDL/YWxwEDjtq1fD6ZOZYfWHxo5Sbrj5h3AKqAvjfooQdZ\nNXZ/UI5HRrK8LkB3d3OS7+8QedJy0l0hBuNdKW/9ZSV6v/aPaq73P5Hsxwub6HppOTdpuhc79mGQ\n/BL9pDmndVUjWyHcgyNkt+zcO9z6QD7PVAuNSZyCb2mI+Bff5GXfNbfpDPMpONpx7ky9z2+yr1dc\nXauIT4xqFGOXmBIPXbiJqIdb7ZHM9Gi3/k+4PBHgUknBatmkDJ5eecnrjZ26gwas6Oe5lVS5KLOg\nGqXTIVVFFpiYzK3ljzoiT0yeBqaJNI4pbjLfcboRyIF8VIWqoO2IfYdEhoC3o+i0Yl3keAXcLh+S\n/AXycHMCysu/X788u4qjRxfaxD0xjZGm9dunBZOgWm/yfFpUUIZE2ozu5nF8DUaEFp6vXVjSE7OC\n02fb7LzkwSuroCbayLt++NlPwDysNXHq0BbIC8BUW+7COg9Qq2NB2AUh03NHpEWm1uBZuBVXJxoI\naKTHQ3t6wWxYxXNg6z4TLgc170rTOlgGGp3YovVUcjXTRTHomEB78mYyHPLuCRrYEW2NQ4J0urgJ\nnzWCUwF0042xITA7DBxUAmoH41LK8eL/DYk2qg61L3MJAJUX3AAr98caLhagCUn01UX6enPIKQb5\nnWUVB56bgpQYcLifI2EwlpY7hK7HFeWXrHyhTZQnGd0p8gRSS8KuVRpyH7z0GeetQ/+myE/r3aOY\n9plLEK6QPf+vNoK30hqRzbsnu3cys/K1TggUEVmS4N2c7i7OcTTRe7S/VDkSc8ZgoQXnOpJVTsiN\n1v+5FUfsmi12db2BlUXAtUM9Iz+r/XxaciAzOgFgFHQfl+exQV34Ney9FwNtVJpwXFa0q4nIfts2\nekxTFNLzEAyhDYtgVffuOl4VnPF9BSHN6y508ESUrPdBJwXfHzV+jflurF1MCqX8G80p9xDud75a\nmnGZPak1w+6EfxPOhAgPm+NonRFVRM0ki3B3HZW5HKs0HGPiLl9Q3ZQP/fUlfHDCeKbvT0xWPKXU\nXXgxtu1ZNmEvyud/3jvhFDfmjh6AaCKi2XXMsh1BkT2a87E56X0VGZmscW8gdPzx2UvCqsOa67y6\nnIiWH+wTfx7jzcaZEY9tJhBxicXzVAkpbL7hh2Do2hGc83L4n+tKZ6IN2tq1FXxdUJmkVh2cLX2z\n/Jn1ixyJ9VdzWIdzkFKwLsA2QD7ns7QMs/dl8UMxO/RtjKahl4TZl8BTyQfFd3sQLIlQECEzfKX6\nJDKfd6WAXaTYDedLRVf4TCuwjx1rLab5XU4zhO8Q1Yku2qeKD+hth7Spsn+0i5ocMLoBSiCTpZ9h\nXn8ds3geBGqt2SPd4eyMefSzBIGx/Q00rnMIHHUVN3jQ2oxmAbAOTgsqd5GgrLdsLwRQrwpBZqsK\n3J6LAW5bFThJ8G66/rlxbFInnGCQ4yXlpbHslAgsDBcmk0nHvM9oG/RmlySbKcQ2zAlOxVrA2hGf\n+SWPpsoPahzsXFFJuAXtHzIM78ErCC2jCojJaoej3YR63BqdghIaE9nFiYcVBQmNBJCybtRZJT2N\nB2pPbfAVXCbVS9SFGQyAmmyOtB4sgXG4LYaMSgLYWttbh+Bq9gGUJaYRur19ZmwEqYUAWu4ACyAs\nHTjhc602LAuPwH9ZGwCO3EbfbFMT0AyaCqY0u6qW2OIOhNDjGVMooNmLyj2RZEuzlJcNNDOs9GYv\nKNrrEuZXcqkjZ5v0MjIkm8CXX9EpU/pslZMYmIYHuxUFOD4ZCC5htF4KHvR64VAfy8eJZnjElbQb\n+h9ZFi918azIWgSoWm5mPnDYXQUQhA37JFZMdLrBGVWd5J5zhrnOeweKYUsJOVz2UhrKIOZWpNV4\n1XboWeIC39bRJQh4+9g8KY8keLAK6avgMPrp9Y3+RV+gzucUzb8S14/b4UsFcVv0FLDeJr1qeYnn\n77ASlZSJ8MZZlEy5PH5iLp8xF4/Jcib7bXU0DgSOHqppPU01FWFAAFQ3pdS2vIaSH0ON07RDG9Qy\nDmlmF/n7ek/vZIjfOXU55wrDl0II6bocsUVBvIqMki5b5JqGzm28HY5AGgN+nNIEw+N1n4gzKNGR\ndOIN9g7gMcmFTls5wuBWvWHP8awlMGRvasNMXrgM1HkIis+Dm8TQAJ4eRFgDj9Iogn6wvT+qgShM\np1iCgj70yAabS6Ohq3JZtCernQSX13/S92WHEVe0YKTT0mH6HSdoodhQctB3XY4D0iiNZJpC8zqB\nHlnlP/RZft0zTU+v2hmkGePJb2ia/jfiGu20DZd6WM+8Q6cifUTUwureuHURzyZsx5zyUb9WAekK\nRW1xl21z+xTacEK2L8qi3EdLgEsZXUzhvr27O1QV+uIuL/V+/YLdwleK2RAqn5ROW42Y3Q56r/dV\ngawH4Wl0ANU6S2JwbGBais2O+2nLVwhLQriUcyYNXhuWc+7xPwsAyHw2R9M6vb3Kkdg4Wcfk21NJ\nMyVY6REt/UBtqkC/hYVNoE5n2qhGSpoRWVQQFCkbew8WzBWOZdyzmISJQDyy3b3BA237ujhb/uJR\nzRuzsGaaKnA/cog1unB1GU2VUljglPDy7n3Hesx5xosdn/gxURO79XFk5S/jzWaPBJuvpenaFFxr\nyESg/K2qR0dEvEDJihX+2a/GkpGghU+ZhezhnC/mapM0ykkmzBxUwUrSc/IMUWmpZCpVJrNLVYOF\nnJSPS3KIxdL1diiYh64ICDSHr9i7pqKueTjsEK67qlhAIYCk6xXck4I5C2kRjRThjv2EHQxOR5dX\nVe8XbzrBwIiyJvvCxm3g5+EPCt0b6EwYALvCH8WAZ91lCtTCFqomRB6/dUS23DP+Sx0y/QYdr15T\nRZTWH8LGyO1E1W08SYbUFZtMUnNPzcykFRMCYI1IUWLBJXMMPtiTWlyEltXCCL3kMn0AIwnYyFvJ\nn7SxCiA1qUsD7CWrhRpOU49dneEphwxJeNyz9bOUGxcuqUwJbnum1eH7rAtSANIQtNZaBQ2Ke6oJ\nlzJdhJE12MRV65B4Nsd2fZWUUTBQM2uXE1k3NQPO3xQ7bngSv1sJ5so2zKPo7iMSdH626ljtmqmQ\n4K6QlEtlWL0ryLMVOe8ywCbeCs0+KF6DlQTPjvaRIFgSf+/XUxGSNDAP67Ww6HJGJvhnJeA/bOtW\nkC1vPFANG0f0HbgdV/VGUIEMPfTvVWQI5mO8xP2mooXHRsBUytHDx6Xaqc/F56+ERQd3bsJ0U05A\nGY73sBTAXcfT80bail6td4LXnB6q0mGIcoRpavQcXpT/crKmwSJau6UOwwVeuKIBtvh72mAKOXFI\nD4jy7sk43ZbMnS+4o8p4lneUY8fHwRlAYDs1OFhi5nvGUjqRfrW4W7D6NjF/ao2Q+RWVwZYgPhmu\nc/QpJsPsoyTZyPYiSI6X5gQQRwgy6PujvtJR2cllkLm0y2X4BnRNbQthFy2DGmlXwV9jKpwHwCkQ\nNUudN5MZ7wkx/S9/gtj2iaAZzFSlyGE83QahJLMkTHh99PnViB1VScVdloR0E/9zj6HyijTBtz5c\nTvpFgdEm1VltojHW0yR3KPsfXBPNvV3qxZGcine3CYB38XNAoOpwQ+m9KiaMjpS+Z3g5jVSvEPRz\nI6Swyc2GHSslRqysHLDmqIFkPYMglv6rb3SP4MPqxcHdDQ42D2QUrIg5QGSsCFVKWYNzuMHNS7MG\n0q9S/CRSYZI6pd+BdxF7QMfYvTxG/z7SX1Y4He65yVsu0BUGxVAycgESC0yqDb/mPS5gu8ICCL/U\nKFYEMO8VavxBguJHpSOZqgfn9uQPdQKICYTyk3gkYwquOIgMeAzUERFY9rDolU/bFQBcrEE04bCl\nGbT1w4HHb2SwKQtCKUFOU/iz1/RQhSELBLKUUWiylPcK8ah60oQCSYEw5Fp/BmjNb6AtVYKSP5lu\n5OCzixPZqSYs/qpGhwGoFduI5ihI6wWRCEmtDWr4fn/VaQEIhnrCOaWyCB7dopkGrzthw/KTqugv\naPwLPvra19o4S7x9snvKUE38ohqiZ3jxQqQhD1jzOVB2BL5T2OlqTN20EzxkwlLulKoNVmKAloLu\nK81FvAwebD4TJBam7Dj09uvH7Vc4ovQsnweC5ZGwKQHDr5l+KYUTpuzAV56b1L4mWVv9KC1AuoWR\n1+u1AypMa7rfYuU8J/YBsH3L2l90hyykLH38XhVxAMQfE+rppwXmCK50Opvfu+3464I40J41o3/U\n2ukQgp2CV4cEALbpyBdHPBeTVEsGU7XgzZjhL8ywTq2g0uOMdr/GUHvajFz5WmKBD1Kn2/A48CSp\nNOF7aTFa1MO+YxEGpsbEGFzGwB/8DZSAS44NI2IJwsH+Pqdb5mDPEp99GepNImg4ax3xuQ5/fmM1\niCvyST6YzO9vDztRrx6DVty4yCz18qh/CBLLq2VO5mQjtLwx3EEoU5WRzivutrc7rYh7fYKPzW6u\ncMCbmpHfD4KjmtbzdCp0jbtSJ702e3alBxvL3fNxgtubgy1qwi8RdognRQaW3lJmodwMVdrO7qL2\nATWjJoDQ7N1vlYlF7a5JdHlqQdFmmyEZOcyxul/lb+66+qwRWiA+s/AxFe3OmsWkfQrkzcrm3bBM\nYCgq7RiGK/Nyg5CqZcFt6sIPEbjDril9Rk9eyfW6+rg2ti5qirauu6GTi89nmG90XFTqbWa2INSi\nu/+J87FDqz6mNQjHTpylfV+unw/2zp2uejZSOmCYg6slgJ5VzEmbLA/loWbbF169Jss2HKsqkJU1\nFDucH9pO1HhVVLLAgvzdWWSWVqHggZ7fdGPKKbND/q0DJS/MlSC4K9wc4d+a7LVqf7YfcArWJBSw\nb/CDJopZa8X7vfppRshZdLKB65dkiC71qdw45IYggV30dDfgL4Y6lqB0d83MFZ2fWmFGA1k+6opi\nCCFPqhmIsVyJwa8YQWio6rNR1n3Kf+cb5LMmmvDH08KeKeBi94wzMkfx8HbU3C4pNA3tFI8HU5lu\n2zYjSejh21ePxj8+f7hNOWHj53eIVwlGFJbeHtuOPKRCUR0ofAhhjWRTTqd91EmVEEKVQGqTsv+X\n0Ofoh1RZyKvBRJFf2qKEDx5HrHBNDup38TtEIQw5seyIR2VVWs7VfqMlt1PMiNCEK5djB6+o6Vq/\nPx0LnlJneHZ4aPg+7Jdx1UYG072d4qEzCB1Xqg37CLd3Y+xHDV+7QDYT75oX/2vO/RsHH8+4CwRy\nrw0knqI4mwfuKMWauSJU5fNvt6owB+BumMxKi6CJn8q/Ahp/Qkye13tRKneKn9RIxeKkXX4bdp3U\nPOdPMfTsdf5FfIIT9fsBZk1q+DN584O8YXhQ/vwoYlxkO03yFQy0t+v98xYVtoBWsnIGcVXZNaGl\nFp1BakMoraD+DIttVaUf0wB36pUfnDLTDvuHLmpgk2XG1LmVRvfdZ52WboncKChN3klluk0pt/AS\nKBTVmhloAwycTXnHnam5GBIjPwPDtu4qEf+m1DyGAo4egZXTy/t8J7tOICSHhwa0V4icen50x4mi\nF+80cHQS+r6jwF0I6P1+0waqv711ZoZ9e8OEeCKtD9cg3UxIbQHJ//qPhG5GqYQ79nNCUcxL0COr\nSihjFJOyM1HcroFKCiJuOCu56NDvE64S/ohFW/8B1RyBPYqcsGOHDusP3PPujuXmd9wra9whktlS\nDiBxU69cPygcHZGCAXvFCc6/4qczdg5RBWeH+cTSnEQ+LQqWVNL4KQSshKyGpjX1CQtCARE3/khz\no0pMSYSst5xKLVspDiAYAYwmHaMhq30l8dct7s5EfvE3vTEOpYsUgzkK5FnMpTMQm080koGudP7x\nS04xhfKQ6LW4wSxG0WxmHIr3hmuVc9tsRFZ9T1mIH5KgBBhi7XEvYeFSvhdw5utdWBc9yE1bV/IJ\n0vrEHBdEJQQ1jC3JHiDeNsWkxk/8VV3v1QMAB8N793KXxgQ/1jEoCwo4r+DgCws300qN53E2O69u\nJKMVjejhty9xQp2+lHRIZ36dvXnVTUpvw4PjnRr6nvdxbkar40A1xSTwZtOv035brN6W7IDeKByR\n9CV6S2CH6CocTKT9Zt8vPpltk8xGtfZvL6iP8+E7DEyTKpJNSbto6tPn78lb2k5J+EbZgbkvLq8M\nTagu9wcsOPFmD6zm8ytmIjLDQnJX7Ly06AkqKfoEgCv/RX3sJDmhLxuUrYN2P/XZyZEXHtLmfjYB\nsIWtLwccXsmc3oVsi2Pq7OJa6yyIdyX0Vag1r3cBSfGMXuhqSEbsGPpHGQAb1bemX6ZL+eaRR8Ir\n/eZQNuhoWG52LpqKtzgzdwYD4dXnawZEgrqPm6go4nMxHajMMT9x+EPRWMRCblVLMU1luSH9kaS8\nMkIoiifAeNimveh9mQ9+m9uCae7DWwiSrDtGe5S0aFDcbg5demK9BS6oJ2C3dBToRiv6isyitqJ1\nK4hru5Lh0iC4ja53Qd1Vl1IsNzYAQ9eEtiubhzCW0UnxLC9l1YlHe0Okqfplx0X85fEe2NfClZkN\nMVvns0Q6cI1RCZoehNR7MEbMUb9sf+YE/zd78entJAGGQcMvgDqc8GPH3Ph5iq6REzmUCizdjv0I\nQuRHIwhl2tSwe3c7oALp7AMb0UEUcEEa7yNBMnSZAwJHxxIcLHifNZnM03He4c7JsB4yGdsZlDmm\nzZoBCJNcbpyRnlvDk7moNefE4BJO/fNaReEAiICWIlZxQA9zDxlf0qEz2FZgadqLiPvXKd0SRjA4\n6iDTL+0XdstQT0EMQUdeOAiDZ+gMhw8gXB9TUZ2KzJmzbfZUOKnt4Dk3S7ZP5reZ67wa9T0Iow/r\nK6VXvm9MDYeTLJlHKJb26IFas/UWABGe7CEM3RCFR5ryVylbEh2frp60MtSfC0mHZIPj4PZVdoNI\nNiG8ls6YxLThfFsXWp20HODlp8vhiepNTHOGoXXKgqoP4qHxUDqUcc0RwU3Qppj3tAK4RurMczSz\nhhlq8xWyWv5vlyJxmJzk7hfCkbradsEVNkfl6K9Oahz0QpXDpQf2iFIk6sdPbjligmhJi1mM1nkw\nG1OXII9kBqnpENv9N9RSHAqqC2EZ0rpCoo86Ow5r0oOJiUmcc65rAomtlFdRFu978TKuwgSK9C0+\nlvBiOfqqfF1RXBAt3OP8BIZgKX0duUVG6lxYs7unXE7WrDkaG3V/VbM8WbHectyWnEAvRcw0S9mS\nDdiKwWKoS0qbSDhtaCGXzhWMnM28+4kegOOYPbRk/Ztu6Uz4g76nX9OiU9zuNUq1WLLjEKfHhK8a\nGSK7TjD0XfBFlJBN6zICribUSvhRDQzFzH7HC5lKMwntykOMgHH5PeJ5U6E5npyoaAjscpk+WPXA\nO7umsA3PQlzkImQmqtskI30+FAMhso1bisaFVT2D0o3MCcuLkhHfMWr+6sIBgfjsPS3K/nIc79Q9\nW78xWZMkiRzh/66GAojp5UtmS+9z0Yefinic4ll5BWvFt8Nji6T5qr3JNbmRxSLIrWy6SEQYWFbk\nuvDa9GkoamiLQGh8cxjQYiz4sGUOXLRClIx0n/r+aCLxc1osC4zXCCC/H656dE9KpcyrxrxNNjGg\n2Q/qsDxIDgLGrTldEhfzYQxCutaJFSxO5+lBXt/b35vFIgu9EBtQDrf4Yb/vRBnwosJ4EXFzhc3t\nCGxZRFmfJk2EolT7/9M5D6mI5D69lbzOGLfsas8scb1Fu5WzV/LVcuhOFhwOfbhxdKjynFeYJIlM\nMg2Y8V8wIoqQqw/LaPQs50OVfuhNZMfG9jmA+ExAZe/ucokZeZna/5j8jVI/rtQkEIg3A9fboOJs\nI3w+MI485SEWZ775L/kBv3b+b5mquXpb/LxY4Zzek05EvFEWOdHaJHOx53f320jbIAufGGFQ7S+r\nMLP5o3+SIoY8UWBBcJL/pLJPPMXYzHLYwo9sUUSrSNf91mMHDv+HU0Wh2eySI5i0INK9gBkxx1fe\nOnym/qYScFhvYPMDuq+TPTH0iEWD46s7Nv4wuIOAq5xV9O3uryeKpUQziY+T6z//hsGBBWNbBl8w\nILc8gwYVkfUv/2L46Ne4F0DRSMim/kOuxiN/MLiwivYwaMYLPCHBYTLCq5EqNIO7UnifZgY8GmPv\n+dI7bySys73tXKSYwPwdbvMeqWjgnm15QxWxPxnL31tSCh69yHnuR/2UDjSIAvziXETZPI1wgtzH\n4zNfH60m1Y4fzEgIkEhWL20v/86j2eS8LajMp6wG+zX/SH0ofwqc4WEYNTUUVt0txzLsY6vccknj\nAMiGAZ9WGwk3ltiCXvSiA37xd/64b7OTSOxdAKC4lCMw32HOZK16d/EHl772X/CW65LGXjBwz+g0\noKGa2hjFuaO6U8i2AJDZO+yb5Md2Cr5tLRbRSWmk81RoMVUqIUbpNRAsjbXUGZpNblzYOeQe0vt1\nf6PxfYHe7oPrkpdbVGRb6G25F5Js82fbjUpzX2HDdU7Il1twenLOBN4cdD6eLejdhO+pwQdYX1pB\nQYJ438wpPpXiwEpSgmIMlspfG1mNSTxfdEUAHgFRWzDvdbBaWM8XFSyfjpZSVh3K0/L5Oz1KaHMK\nmlL84qRPVU6Rp+NoD29VfZb4OyRsO4UNd4pduIp4FeB0TQVM95pQ6okMDeNIceKcw1O91PWKden7\nflkLY+RgDV691cdU4QbC2BRx5asY+ZiKu0bEWOhkJH2/KmRJITdtA+7xavT839GCEWYZCM3YHo6B\ncuw/VqDedEV4xND7mx0bYG9x9guBtGVTHiDTyb7phXjVe7Fyi/x5t8VufShAgo/rtyoswiJ8BhlJ\niPsuCwoul5MxCFqHLK5B+UZJqSIR9/1VIFuGceMk5Ubv0d1H8Z5bPpQwCvdfLL07qvjUEvpa5mUB\nuJJkNEG5juaNM0/IUY2FxPzrNx/PTRIjl9LuV5dlE6NhxpbJtZRWPj0lE8jjK1chUV+6+2I9lrTc\nrJ5rmF7L+wbi4C9Dnp2x2xYaS/tE0F+VimsBt7l7B9bAarIiivHNFgTe2qE/+Kb1M3H1ct1Hqjm5\nAL1YaKcUqsQLLnEvw5cPBqQ8QW32XBuof6yn+xxK1EOpb7J8gdZC9ud9Atb/F+rDUY3Zk042VOJ9\n+38BfXth0Ew8oVZmdThyt5KDvzgcpYhgHwKbx8cB7uW0LcTT3DG+SLkqMgun6MwLUownC1+r4G+k\nPOYQgyWZ2hwdrVfUEm2FQ8T7jIjofPdRiOV6vMIyo1LQtEHryCdfVlFdMVkX+zEa1uMOonNlIG6F\nqlwAOm8pi+/BvGuB+BRrikGczOJB0Wg/rgpg72XrFf3i1rneXsCsO+VpQRvcvl0H7+GloQpZ8e4/\nL6/LM7YId2uE/6LP5MJwBkwdYhnQeIBRDsaT4SqBqvFFGUwo9XHQ7BX9hvDKJNNr2WJx/TN4DGSc\nQSXf7zNQkznf33MkIXuht7XWfQq0F2JDmeO2vQWLYbSyGuKMoCeZqlWTINTX0kKL2gXogQo0CSFu\nl3yJUjzzXg8kxWRp881QDeoh0QXJzkJlSK9RcBJyAPoGq8MGVQnhqlZCaCtKwWjxXPJMod56Ofz9\n6d5QEnLnZTdUaNX5elPnAy//gVbggUKwOQ/skaVSauu/sHjK5FOnEBYk65Rd7tYGD0NeBXwgdzq7\nZjElbS8KS/Cefr+77JrYrMx0aZBZJ7PQi9t6EAB8LJx3ynPMFiOi1mFRiRTnoOunlquPz+IQPZCz\nMGnV/sBJnYWAFfT6SVllXQSioS/rUjluR4vovLgImmCkRQKUSj5xnZdY4AVssYcDjdo02+On7piN\n8qNFmcN5E7Yf/TncOjvzUDpXawtm4XcUunz6fz+TAFwd6SFGP3I6tLXK7Ell/AJ6615QZubiMzMy\n5isLZteUKQdn5qY5SU487hB+j5EiF/KIGAbITt3VhdHrimshB5ya4LsOjyuKLV8kB/V2FxEcrVP5\nlPsWo8vJ/pCG1SE+UmhSQrWcx4/NM1rtR7bCmMtSfeu3ZhArzYJK2EjxCmwxqxivMXGcsAByH55s\nRNnTvl30k066eZStn34hQlok8+Uj4MJAmSuHpOlft5Cw/TOrk1MOZFdyyX5HyQGbCwAhDElXG7Np\nNtIBPPZERmcalGEy/Owm1PoUFZGrD0ygMaJgnLTHY6MLYf5DaqbqAsq33MOscg/qw0ro97IvQveu\nbVHyQ8dKOw0H4XCakKKp59qL+Lo06pAmqctYoqEAI6NyA5PBetT83h7XnqI61qecb+efcMBgjAHx\njfy4b1SDC/HxaiPhae5rVoY4Mii9nQB7tuiNNT6Gmu1Vwwpg+FqVEjv+kwb5pFPKdcoYZP+5TaCc\npfDutBLUv54hLF1z9ZTSVfm8dhinFIriv3FGv9/qh+OBVnE05kFf0guuqhsiraGuH03jxhZjWfyS\nOaM8SAV0mGwdime6bWsWIdynqw2HAyQx5ZB4Y4WQMUkJTUZZqfnyJoiPtmujk+CkRIbdfqOinQVP\nO07DTJxDEzoF7uhPsOTK3EFXwpS8pYBJ6rBUpkDv2cdF+nkS/+/cAXKl/YHTpBgNyZhjRpWyxHsn\niFcLNNJfu2sWWDKVydWGDedDKCGcvqLPUsStmaG3e0WUzqYcTIcOw4FcGgqM5B7L1taswxouzywa\nIj0O+yHtm4lcDaUaPBH1jpC3Tx1teYcGoV9p1KGhmnqYHidnh8j5RR7mQphYOBTEDhrfxBok0oZp\nxEb5R0n0lHsnE5wR+R4TmYpqKaUpaZOnnhRH5vBWzpvNoXJZHsCXpiaDJFAEE6vHItaTa0n+jLX3\nsAKceIWi2N0ON80jpDAKDd8n2CWy5iOPEydoKV62sboxWYLHelvWFOVdHFqza9cLsXbUMPH/vDsB\n8zUXcORUvcn7XjjuxPfPOc0t/Q0dPFlQIuhEr08hTBnRjrrlpX7+x6ZTY+fPNHR9F91Pv0fPWCIy\nbROzbw3bSzeY6s15+qHzXfdfy24+QkpwFfNxBLscbYdYMJuaHRfUkYdyiSvy88tiTke0cWsJIgL8\nb6LF55Fl+0MmwuU9qJt6LFzPlqMjg3MTJMUSxs+oM8M2Y5lbhwQwyifFyhKYtLmLusjTARMM25Y6\nukzQRYRNI3Oxe5UbT7SrcwTUy1Lzewof6EN8wyjkP5FSWkYNXeMzogCzF/M5OPrEz3P23auJXL5f\nPSwxg5GwtiAddrpoxwVq7t/SXomVKF8qrK6QHhSEkffLcH8rFeij+Eex34jAGjtyYThMr2yAKAjQ\nvo4wSdK/C8Znry4ZN2XvcUYAMID1n0uTpMVXdijFIGLqamf0k6GmXzQ3UpVfSzrDS8bynQPdLLGI\nuxvSeQyS5cbAMWmj6MtbyYyhYMLNeIGeHc1Ble5JKk9XcBOCCFgzOOv31ocUMajLFqBtSfkqRVra\nFJiVtRF38mFRo9WKRHhb8sdoITC8hS2CTMQSsxPCAmNaVD2bJ/qFT0p1EZZq6BoZITEqjyAZmtZx\nXqR5qhQI4oxW96jPl+BN8zN6fFGwSg8Uc/RdDO4jXwwJaU3DhK6+dMf6pj/dlOYkkqJWJ5zvJtdI\nN/rpUYECSK50BXCzYV95c0h8TYbjLL07Bo0wAZsx9en9mAAJjFeW5J9b6bw8wSryqIlFuv/vii/8\n0NeNbQ3HukqaJ6WS8ig24kNpl9AaJTw1mevhFDSLwa3iuPULC+87SJhRoIKk7u5faUsPh5M+BdS3\nnwwNBqnyAL/eoOxdZGIbuQgqWGGzqOOHbG1kV1nNYc7Xp33yYYqiV7WseZtb4ifQcYtnIMXRuCPs\n0HNXHhr7bZxfYss+z0D8ocASvnpOL8w4nlKT2PiLsJ+jpVGuGS67p7kyScbgWATTr1CCJkP8hlGI\nMX4ceG7sdnxo3SvwA743LtMPEDxxTJV+J/+6w03IxGuA5NzYdhkU5Br4pGMfka9XTP8KCa/gkIs2\nw9HFq5FtvyOmvpOL4+vO90uK7rMdlqzeGa/PolqIB6YyPVJKLa4IIK9yih6/HfL4Dr+t/VMfsX6r\nwVNKcvxe0cS/qHRNS5g613kQ6UhUK6nbWfngwumJfxEVujPsHnfwLImvXV+Z0lpohVidsRwRstCl\nypmA///VlWrIIEfM9ztYImxJ+QCWHceJt6eh32pSrS1Y7CAJmjnpYkmyNQzNY63+27caRFAiePJe\ntSVGh1aHXEvlFIm5wia01tXhKIajPWowqppLHpWsZQkS1rJJUM4r0e11wGleAGGxpzLFv++3rRZV\n2E7P0LyqAMCVXwuJgbDCIUjKBeXleHsoXTjsTJ0RcfA16W2S7LwZUHCmJVq4hjScokm5x4LP6eKu\nnW7YbxZKQNnAIWffjZAbiPXmq2NpSzKlWV7VBEHvhB3WX+EGeM3dY6Fg0rL393oyDKouyjUWwtJK\nKkxwPWhTHPfGtMQHZyUM25PNCS9dRLKFvj+8Yuv+Cjbmf1HTxuUHNkIppVMhe3pp/EoYQdCKYkf4\nNmIqgPEpc1Xw53xrv3c2+5Qe2RPVMCBF8XCVGS08pfg+iaC35dIcxw6Arwcub7q1AJUHYWWH3e17\n++/sVHV8krkistFmP10E1UX/+MJ9cPXKZtgTdfX1nP1wgv2fZiV86BE76jaU7foSkNjoqQztHEvH\nvnjg5wHfIOBGVzLQvSsux2gimvtklrdrQeNtEAOAQpNS+C53UQWER5i7GMN1FpWJmOMX0AnM0fdP\nN+AUFHdOIyVfThnj/V74mNf8KRQZT8nQUqmy3LgdGQ7uPX4esG3SBEeLh2JSQd7DG8Rzy7bzFHcT\nR/lPn6HC2RR7J+MiEZbxOgXfw5CazrPTtOwGqDjFroba3fEyK6BRmL6ltjB2nnNbZ3QMS84Tngu0\nztlVsUNRQ0vVqF0YHm5Xzu/LFsbmB7GIOauNfKOdAPUZ9+FyQsOahJKfbgvle/vzDZKF7dJBesQR\n7G6ng9CIXGpMPYE0Je+/agXWFSxCKueeO+bxz3ykBrwSkZqafIocSh2im4U+LUrsdQ6Qg5KHNbvA\n+2ko1mWue4ZHKFv3GFIz6qy8sSdD4o1YWaRzp6QR6CuG/L0GNdQmSRM22JvOQ9ORJ8zEvxHKtsnC\nDDxX0UtcYsOlNPodlxY2wv52fihmfKKbhbhMpFY9wB8xvbiq2ZD4NKhflfFlzzNjsaAJtm07xKlJ\nvemry435VhaDY+TdxjrGnAKY8dtM50Zuw5GkpQQl8/L7DdmvUu0b4+ozCk3HZICokDOSzb1zTgvU\ngwko9mlZjy6Ro+IL6CNR27Huwainy4TT/R0u8/+5Fv179JNlvHyGxYXUa5rJRKrKic7H2nf4dykH\npcfDPpPIdH1kEIrpLaMjMoIsf9ypnvIpIO6RdGv6+Q6txwVGizW36oyiNd3BGZXe5F2CH4ImOqdT\nzMQ3d6iYRlIvqU9Kw5Ul/e++X+NLUudXHoAMRCPNbvPhB7hOYnKeR40UYNCDjm3KNgvMxzKh4Dd3\neQKaZuo7/YToyzwW/jjo35H8jGygVz0cA4hssv3j0DESJpsjI4uINFEqYK45Jn4fRPDMBxpU0V6Y\niAEQF54vjRcFgtShdk019k5MuVKNoQ+6ioiLfV0VtqEfVItvGAa9IlriFbDStqq4/rmdvZSArMUk\n+uF0EFdygH6DTJhAGoF6uE3zm+O7VytcdokHJmfnvl+LCSqwm2E9nVmqp/LTVl3GOKTP5PHZPyHE\nKCi06jAtv4vqhcRfdpwIt5LhZiXTuDrW/LJOqRdZXN5Lf4RO5T2gjYjgq+1ujG4JBq8ayr4Jhmky\nRSYp9fjRtfWn9lJAN8k+AdmkvXs8jy7wF2739kvWDAN/un1R/jxWygm4VjmCETmc3tgWZTBsyj3h\ndS7ip9ZGkO9ob6spwsAgTdxMfvK1vrx+UtwMbTZXoYLsDRtOHOpZtSlwqzdwlfTfP8wqu2owh4NY\nIMFNw2uV7x8Z19AnwHVSVg/+LRFyuUaDGsY0Tx2w+AWOhecrWJh18NUOCcw6WYG+/zLfHMsOy0Jw\nzbwdo+ynwtdG7mf4UVXSsr8vvwXKUGLzH/u7HLX6ri89GzLPTloHlsDEKlwnHWE+ElKuvbcbSNLz\n7MAhzh77MOCAOzn1JWSviNo9oDwCiru+wmYkeVGBLPncm+tbZi33xvyqZBmfdAiF26M8iEdZ0fC2\n9yNPdv8S/uO19rku7PiiqZvBEsudotq/zr7KC4V4r4Be4Fi1bhMPs17pJKEbnnZRV95jnZZBbWVl\nB8dCXMdwhms4DwWuimrqylqqF0BkHLvolrJ1PF4O/vId65g+6REAfD0mWExq5NMxA6QraCswyXBM\njO5ogsRfcuZw4y/Uft/kFMIM83hr6URIolvB7wRczzYNd/L/rUCnaBE2JIX+ZGd/Agmvy6lyaeSg\nQDDJ+ud46UMBCh7q2VG6ShlCYR4MyG+vuI9eUoHQ6OXuK+5XogDKPl1ThMXtIbZR37r3hWwh1axd\nlmfN8x31WfLCjsSFuBJExJkMZ5INe4PrSVpnMhT/MPhDbvh3TfPx9q/rDwDpqNlXg/4wsen236QP\nfqYOepmKZ/R5cPOjQsQp1EdDmykoEBb5vKZC+wJ2Ni7GDDTyuIUczE5uoWPFaOeHshGDmqpAyi0C\nYF3y8L311F3BT0yRTvNn18HPzKtJTn/lava4O4X0UK9gmPS9IUpRzvG535glq+TPTBeNNmMmjpoF\ncK043+6zBszbg1lgYMvoV403GptiT72C7uIAvpG0g3jR8ktV8ITtR8Ho36g3WEjUWFxurrhR5I/3\nMa4Igyi43BjEzm7f6cmxIh3L6OaadG2DZ38XUSedfRuMRuwWT60QG0FmYXdeGFv4215blbNsymcm\nk2mIDQbGDk/Qybmsoc7LPxjQV4G98NugY3JbxzfgqetsT99VhDmj0GBIG+LC1hlb++vcKjraa/C8\njN6NZRKehIkIZC4+vQS6gw27OP4PJrkOkXASle88FbbPhxozfa1WyIQrOq1xIqmLOHigv/faefeW\nAxTVyv8ScMVWcpI+jLJLLy4a1Ch7/HJ/igiVmCHlJm7ckJMbgtBVztLXQmXnjJTL6Pynsx6MKv0l\n8BVbVKIE16HLCsUqMPkgg0arbqf7yDPlygpesUhx0cUmFWse8vcOA+1H06P+4dycC80KWTsmPS6B\n5EGvU3RjL2y74HpjqP3MRfZBswhULeDpxvyXTaudo8034t8jEmw2Rp5ffDKcalxJbexN0612mGqK\nXqkLlz70YN9vIddrjYU26o3OdmYoBfN5cTWD72Re4pVTTuUqJ1HEE8xye8F24YDscQOv/4SaVieW\n8xM1S9bv0ifD1RYJymN5BCskUXl/bB/maR9C0MzQ47TZprWfZ8Zdhg9whQ54UgBUNuESTH+6DGs2\nACGSy1Dns4Y1955iy1Q8actfsbkIxYi2/oNqHZ02D2Xvwg3tHecFHzolEI6SlfAbGebSE8zOPlnO\nDk5WFDm7R7Ya9Wzde1ycw2/dEPIiNXKlzF14E2Q5XodVnrcpMwAWMhgnnuHIE49vs6jmYNq3GQis\nlhQUwP/dNeK3tPco+bLYIdxZJ7pWhl6d05lMr3MGDeem4/Cpl2QjnO3aBmxJ8J0XA9RR8gUjA23l\n3vpbX7HbQi51qCNjyhGK1Tmn2en0/fGcEOGhZyyCvJH4Qo6zB9uGykWijrxVWG4RmvxqKqqag0FJ\nDlk12cU1XziDHfGXtE4VhXARzXiF6esJwhhcSD4ZrgY1ji1RUxpWB+b4TuzJKPDpWO79abKalORo\nC/stTdrUrz/piO2okmJ8sOj74MQPCPxN9rpJdhy2k4LrMMhDh1kaspAmkqlclPY1falbZE7cfe/0\nin7NtWeOPQrKTl/qhE1qao7k6Ua4ZeGWC5GHaS2ipHen6ikeqettySwzRKBmkdDQSHamPY/wDQo/\nVo5THKpvcnZFmnuRDI9gsWrl2HV8Cnu3cziisYvsdFyyjFJlLwQI080Hm7YI3tK2ujDpuxu37bkd\nVnshVjH6Lm3O9gsdW5jBFwOx23KmV5lftiKdYyRkiF2iMjSw3tLSSlHQ2n29KzYnL1G/26FjOuI6\nmThzBJljDQuqaE3P8+F0mWoEBHmZCjrTaPb/too5PFL5RvZtiGun/PNgZX/pUEuzDeQeX08IRmek\nEKmkvHTs/bc7f9diRmuKuZ0H6KhygPZAuIP+2JJ8Zcy94C0B3pNqkm7GypUhQXN7SZe4ND/q67LO\nmfiUWXZhCIigT7LLJt8OkggXTxYdk0ArF5AA/dHoUgKcvhfFXSnNFzcF4C42BPgt5D5lWQUDipZ3\nQ8715I9sCHyxQVihVdsS/jzu8jW7ZiT9fmouvloW+afVRWXnzp4xWrqsHwJes5dBP+OMnR5K9XyV\nwpOQXuAExmx/sSUECT2cwytphepaK9GB4+yxMNZU8XIqfaawkSCeupH1jiH5ztVfu01WsSVZL0Vt\nZ9G2/wCR77e+YWHiga0WAuSbN0Sm/kAOZTbRQ3Iqu2L6xEwsAt5OufgkCG3QWEA6ZFCgt/11FtNo\nWCg8dspVc7wjJGcaQh62kkHOHeKyQP/GPfc6zfn8ojkU6lx6BtJUzVc9+5iSeiziOxJVcg+XiNfm\nry1bTBPVqs9V7GfXZMNMeTPpqgwy/SDSL7PSaaGXTc51e2rpsZPCv4PWW+k/3SAK4kBHSFsXoFai\nlWnFbldiXTkPzBByW64STapLmZt/db23NfGWmSAgnfeLy077nTB6S5VN3QJaubOw+sUFq8QDZWhq\nJlxIh/AxMOu9CnXuhl5COX2kO9MnYp2ibQXZjYB2Uz8GzbRh3KOr6O9O6W3eiJS0HmB8DwT3eBwt\niH4rzeVRFdnU9sZW7iCshmVvJV+XW7oEo5D+mVIWBfKFAxW2CN0E7mi2blglmwl/uUoXwiZWTQHN\nkhag0uDa1dx9iDbItFz0ff9B2+bFpQ8AkwoXj77KoRfnZlVXLC+351BetTTY9QZUbC9jM5kBy01H\nTMWQkj5fvhJ9zuXsRqN/ZPhdJDq6JQuiEcgl4fc7vL6BcDmgAMISZNEBSA8QIcAwmMU9Z0K6SvzL\nNAwuXYfobpCOxANwrbOXWCIRHi0LUYEAp0zpK3AeyOedeZ68F9Dx0fhcv7R5k4sHHwUeJ8QWMJl4\nuqJXzDcHIn54qJtSVy2yQ36u4QGuUmRMJ1QDFwxXSrRk4ewO5n6ndJrxupnl+yw9N8jpv0rFyy8x\nv6tNb1KSNcA65G38Uk+f9pXDFVAm9yVMVmNARfZzNrQybf4G+K193zlQGV+SrzXvvGpmOAfRhgox\nHa0Gj16eO+vvj9fYyRY0sOv+3uwbC1pn85cfGt8zdhHAShA/eICI6mnWYE+luL8oTUPFjbA6JuTg\nfWgf6iE/NXQSL2DBUMw5RF9/G3yfPOT8oYWbJZqL/s2pDbLW9hNGYXFQpXD1iH7/dJeQ1tdJipcu\nXGlb3slj/kcLiggxed89F/4aDEvVs0e6Ln27lb0ihd7NmvZrkbjT7vY8qISWtBVA7tNKlVV00HvZ\n0qvK87ftjk92FJK4fSekoReIxDjO50jci6dwOEqmYM16fIkvpBIllveCmSgWyYQxJoOrTBhPJJtf\nXfZ6PPmEUUvXU2cz8AnKfLRCcN/Cf29cKf549Q98BDW9jyemH6WdntrxM71+Hhjv4S5TtU0U0g0V\n0+t2NEX2ofWopXzTd7xXyQWW+2FlEeHbIg6Yi7LuQwhxTEUHKro+BW4SDMa8Zmib3qrPzVE1roWa\nMlCU552UI7bRNUR67/3lL2I9V5OF2EUctqNmUS1uRRUduiEN98Ni5WnO9pj7dC/aEx5fYbprxuUP\ntYj6TxMUAK4EpYp2EU81lidmWfGE+PSltOYjZqwp0eX2VQG8gtQ5XLQ5VDL5EmdTdG94MAZ3KWl4\n71qGiCGftP1gc02JOeebdCLPs9RB01Qamz/7qRrtLZqfjEm7vFGnZjrPbvouq6aLrTrkSoQ9Rku9\nBq7sCRWpZJHwIQW3joU6vIKWqovqZrmuMZEMt50iADknpPAcVttuorkxIhrY8EMGTVLaeiKc6+aC\nw90fEP2IluyabL4KCB9IP5YRud8Vem80dhNNefrYqAytpEjcQQMbkigJA71KxdxCMLHjPZhIqf9P\n1FOlQfDEyWStjz45PhUvBsWGfNfY4e7RP7t/msJ7F3wQoa9QKpj9K/iurRXNZN2eKT6Hj7SGkUn0\nACtUn9Zun7Ua1be3Kb+uXxXfvj7+T0Uz3jlSydytD55UnuDAYq+K2gAwynXtc6841qezeIxadr37\nLq8AbB4IT5X/oDEUDdtuxJhziiuLroU27SrBYnAx3ZoKLS6XfVF7wXS4LTlEOGi4AzkJlFgbtjDN\n0n2EsteXDHoJpKSx1AqY+vi7VY3JpoxH1RemFZ4Rbxr3Xmzsdx4BaO8hsfUOAXD/iq2b3VP/iWhB\n8XRPiTNtsAKVeSMyRv+E/9K5cMsB+gFtd1En27yHSX5qBO9M1g4ncHw+EIhgU0Tg1aEZlnpBXn1f\n8KAdY+kh8PwqGgcbkRdJC3bttZ/g9xR3roFPxpAZ+boxGrp2jE40Fcr3X4g44jgrA4IRgiUDIWTX\nqR8lxjalxvMOV3ATBs+7cP/BSaFzc7AbNgflKhebuvoh9OVDpfPv5+tJj/Ucv9iEIo7eCoyA4QTT\noY1enrvni6ko5gsAxgyanuHdkjnMV9qdVIMntJDRkt0cWEfdAEj8z4tYB/hGCMz103rrnFkX+aid\n3cFFPfSGptu7BMWqfuRmrduQ2xdKKgZPaj+yLnReK/vEbKIkBYZl8MlESCeAWwf1nzu1G6V7xSXU\nFruXmDy+vFG1QwwK2CMJKGUq1PintY4siRuRBhjdR8bY/v9Dppoqiq0GbWCnEnoeZ0lgvS53Avh+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GcA9Zn6JSJxTUCwYs8aQ3SIm8x3etRqToWjYKTAbZmvRezqKjuhJ1htlHyPt+p\ngxFYba0DOIa5737BxwzgTL+BM/X75cddRAx9O1zRk7WcZscO4nKsuVed5vzVpY5fUeeam4wpEreH\ndf5fZo+i2TN8VR099r6xe3IuXjepLpUDSqgz1s6fjumUU49h8B5VogWCzI/Sng4e2ySs3DuudcTN\neTbO7F7hocbaR4Ja+OHzwSKcERs2tKt3SKOZaqCzh1C4cN7icnZeSfmDXVkJyB9mTWl/6wSahflp\neg4bS3CxHvVHBxc1wTPp6ZwEbCNJZ1GeG3MurB9i3JbnUDzmOFhwg7eOaFurXoGiv45RB8vQKvjc\ngyyFG8V0I0UxUmA9cFlbilM6mXKs0c7bvXdGnxv2DQpmqWwHJafqZ9Ub7GIRP2nIw0yClX3C5UaC\nyf/tjtAnY/dw/5LntI5BBunmuEC6fBhZSntF7uXrDWv1s+C859IbUO234tYG7dJFDQHZH29sVYfg\nQYZDwlOgb8VuP8Lpo6c88I1UFVYFMgCF3P5SQ+v1m63bfe3bay4HUTISeVJUy8JV8sfADq2wubcG\nuWcfUD5AShQOLmrpWHHJ7kOetd/o40exAcRpY6ruMZpAbw/XTk3w+IZeYAjXvoV4HsxbneA/j/6v\nRCzoW5P3UuUoaB5PgGjjGV5hyDlRE22MnFsaD1Edp4Aaazf6x/abJR+gEuiOjIkZdFyslNkczRoD\nu7By43V/wCySOAnWyFDHOhN+Rk2yxZXouQu7q4FFldEH1iFrGHvxaAEezrQSskVgSBq5s+L59ioU\neO9CS8jae071lEKSz2D/g93/OL82GyJlZWj+PeSbqzhShQ+oX05Il2Hif0Nxbu2fUZVIMzIa9VDD\nf0JX96UWWVTDr3evRvYoh7RwhDS82OKImfwBmSzxFjawoemFpUn6yy4AdrgWom6pB82BOMrWyxCm\nr0baPyGumEcnivasXzu3Ghg7l4NtwjlcTuSrDJyiIIqWlD01qFIT/NSe8XGEUU3cnSBqQfMnb1rY\ni9O0ljhYVL8fURPadXIpnmspDZRBbO/9U5PDuTLIDUARR58h3mS92o8oG+2mYSEHMk9Yt23OoVZN\naP/TqOTjA3bB1PM7YulgzasFE+gl9SAFP7u9cTy07ik7Z6RqLfrweuEgZzZGPgnx+HDSN6clM4mE\nVHYMRJf5jlERFhrV8NNEHb+dJ1cy1o+50SKlrf2bfrsA1sMfqwFFA7WTEXfXopqTuOy2pS6YuTzn\nLtt8mp+m9VBSNQNLGSuPeVQKDL2c/GFdlc6tWG5msBw+rNDavwUIHfgdxQT3krhLdr0g/Xg3vX10\nmVcpqzA8cPWZU/PuRqdqDxxY+pCqDWMuX9X7UVKrPye75k4QcLary7mM+LoUhbsrfeeVgHdXbQQM\nzMhNtPA4SoBi7w0scbWfeGmkJixU8Sj4L6lA3ZvMrp/M8AR+++6EBCX9ttW8OQssFTRvoTnGA4Jn\n2kCJwehXlV5jwMSToYsyFFZIfrJxAUbo/+5sJXPMGPJIZRxRvhgucH3WnPrzojvDrhoDhR9WTn/D\nUIlyqa4FG7wIMST9OtD7LQ2xc2zji5zZN9DmxSdSMDQA/03HnR0gcY5xRBuJZ1lVW93DRflHAlIE\ndxPAtrUw4T1wgmfkkOnNCKxOsSAufvMYEchVBCXPVSTCIUgCl1WDz1FztJXRkZhd7VubxRZycQbb\n7F0xSiDk4EP7d4d1bLSz4fXRdkVa7inKtRAzuHfrKZes8NViU4Hb0i39UaHG/0rHCiWuEqEaemNZ\nta6O+8TeqDy5mRWmtS04oiQBIqj/a+YJjajeqKkJo5PwXbtHvSQh8grTm2jifLLDtyc7quNULvHe\ncOm9lfFtaaA9EHzxLtTm2U+5jwj6VdaXu/Ui+MVFI0xsQHgjT2wK5sk2yH071CVmBEItMF1tRgQd\nQIH/aNQjpXW0VHg7b+/8rumUFrN+pmkyUxhN2563muCP4KBJd0JQrKwU7s1O3br5fHuueVJAe9LR\nyXRESLNfzc+gr9SgamtzGojIrCBDOUdjjM6J49tE5jD0h77qR7N0SyxngO1MjZbfnYlh0TiZkDrO\nSn6LQCdtHe8jRfHGsS0T3MouZqBxtTrH1h/5Wg9xfQiQNzbjFdKkT5KfBmXj5IMkhLC+nYB2DwNu\nSJ3tFGNeOhrevRvFD3kUC7fsFE/ZwDgMmeDRMbfPY/Lb4XcSd2iIZBORBSlcLw+e83D2PnE6mkza\nnmnmKneUB+XbLJ5SGoG2x3n3eYD1iqpgIRRjPc9+6cuqbbkDWi4/eLtllVND026fbWEIF7PSYUK0\nwh1664zeBZIErMhQYj2uSBUZUWLIb2ys6q64oBSI5R7dLu3h3FuVojFnfAKueZRqbC9twker0itL\nIMphRzQ97vqXPOpQwskpiS+j4989IJOhDe4UTwtvUFVPhujGAfnowG3xIolbZ07V4VTbTzi61amj\n29GzddvermmeN/WW4di+c798HQaVMAPlLpjdy5BwGUk0SINd/oPNbjC3LeDtSSBdv9jld6nDeIjT\nNOVG8bBSqDP+0SDTjI0VlDlLKXh3KmZKpG+OA/z3ssNWrlyCFOgq6ZD/BUQCb3CLl7yKAVDswePh\nnK5UpUiGqm79YFthbWwOedumd7lJPMBxNYnJmAmZtSqcx38lGLipvw3ZMIEBliw4TlSRjPOodnCj\n5uztSEunBm5DjF2YJrzC/eZ7ea8lkj2HjtFZOrVG1eLYgh9Xi2PTJn3eCiZZBLMyEIGbpmrAHEEt\nDir1mN23gE9E3gGAm5AIQd0X/ZM5UBNPXpYcT4QMDGFeR8CC502+5jQ68swFIiwkynNbXW7v85kP\ngNi6PG3pHfS7G8j5+v0eyr4z87SXr+0wQ7+YrKvAjVHMKwTGds7JZSrwY/xbyS41jfuL4BK0XGi4\nGKhXRrAV6L4csIatF/43SQRMQAYQTLkSdDlWFrYmimVcttsF3Nb/V6BRPKOMZf/AIRfl2g25CdOh\n8t4wi8f2wZ/6vvyVQ3JjUs1GtUYeFEY2jWTfc1nfqrw6YJmSZExzhFIq5LVEZ9hcIQ/mWBgf4VfF\nldlM3cF86EoYz2hdMw/bPSu8pHqYAOWsZvsPVeLvR5bf+ugQYrAbCzBTFgM4SHoJsfINe6+0nnZW\nfkR1pXXII24Nn1y/HuBasCbvkzcHQwFyLWOi1PcOxspjoOrteHd+nv1PwUwED5QpalSFP5gx0j/F\nP6OQXBmrcu8HNETcC5BNbjUUgxVH8NmEx0vYKQka2u9RIWNOY86IY1UCKu4wT5U1nRyTpAy96rY1\nCUY2eeSu15cl3mFEsc9cR2SaZp7oGFiGkOeASbDfact9JWvN8TRyKi8cuY8jnRLtMh8w6wkHUW+F\noAxhkhQG48kdBvp3WBM4eJC/FhAoYDpTS3VrpOPFn7cHPRte76xha7ph35Pmy2bw6sY+BQ99Yk6h\n9vmke0+Iyb0+XXIHT2rKEiFSiu8dRJ6l+AqhZidZgZkJhwWP6y3ecQwmJVAhV+qEd0wPaFwMQoVI\nrzJC7r4gIi5KpEF26KGVAz/C0/Cj9x5E11XzeRsFpyYKNmgKzN2jhUC5+yg2/QIQ5A8h7Kg4dieQ\ntCofAS5iA+FaHtsY/jn5rX+UwExiVSxZRm7UjJbNW83QQwfFcfsW8O/bvA5lU1tk58Ii8KbxIvek\naLGlNnWFN8WThhNIHLSDeHRq2zxLQ8tG40cLPkNsyz+rMRzi/zjKmRbDejskopG5i/lb499GmbXr\n2C4NU1qBCMI4HfUZ5Mr9joo7/9FzpKG/HWLSct91DJ1rOP/RoZv4rbb9zKm+zlwL76OYPF9yA5Ma\nZe0asLuYZRnc/l/2AeEAdQVhjZCwsrClN22r88vb16gNFKtjTExjrzsDtDjZ38VXUOkOveq4mhYn\n4vnLjumrZBCz7y+6ZCszoIOjULEXOLchdJYytt2ysJfcaHDBPBxcJn+WKQ7xUvPyzh5WgRMUdsim\nDuVT+D7JaCvgAT2j1VfqyHMGXgfq5ph5OLNiOevTUYgC1V5HA70U8xcLfS4RYJI6WJCHWC9Wbngz\nzNLDlUD69JGv7uThe26LzvY/ivOrbkXghyYbkN4VT4GLqOsWMCYEtyAxmvgWAqIhNSPw0NSJjE5x\nxO2zQm1FoNF5mu+nCWJdUPtx70u0a8e5jdN9GFlj0EYq8DNB1X0nZZoBnNM/W7TUMATH/6CXWzd0\n498UFlvIFo2HQrBaKisdbEQ1Qb007Rp6TCnkkwgEHAcKg6AJiU/DZLXeYF60Biwb6N4KrGT3PWbt\nf0Kmi1vBxjXBTZbQXGjHwCQ5D6b5cYFeRxyCBrMFOUv8qbAKJEjRmrVW2MuIwIBgNbqnWIRstX03\nI5zhAC0x0EWpvNz4BOglCPcHaYYzo76rjSDZh4aQlyQmEiCxXT06Jv2NYSW0tU39elbVs4GHgI4T\nym3nR1zd9r7mOP4orAjs574aT/9ikdzavVr1NoMgeyyPCkPAIT7IxIce9jz6PdNk6zDEySO/wwdI\nCOV0YVAH8zQKQZLiL4bx5xvT3KZbcAHR1SsaJeuBZ8Lga1pt/5pLF36+kIJ9mqMHR18nWmcyeBNL\ncJEQH1ntn5eN1jpnbbQWsPwozLdy48vcXxr7N+qr9eUL8XPBcUpq43UZWMr+XUhhbgimqWxbY/NV\nfuSLs0MZQYkqzSennveOAr5UkIRGGlsWXubl8MxTBCT+GUtanJRS9duOH1yU+l8Lh8/orNoh7Nrv\nc1FaI7GMH9dMRFNACBQILarMsF7GoiZaxVxfCgQZMv2meRqmfLlgJ8HupWxkyoCgnlZLndHInG9y\n7Hs7zUmIhAGYuwtq9HnuBcKJzUP6hi82F7qk88GLhmoWaGDy+9WlFirxxJj9q5kYRwok79jIwzx/\no0ZQQUUtE1ZYANeGBMwhPqW86Ltz+DOq0vA/z8rOS2GDPEfNq/zALAuz9Wgmfp2XmtwiMCk9wXRA\nn0NajGKBfnpxQhGvH6Kt6j6GX4ZePX92brl37hhv+v3goAezP8T05xCAO3ENq58hojoRpLskhm2q\neGZIZA7RMgLk1EOC4eXqf4gyTW/XzzZphuSs3NBT4PvNCbJweAzuRW2koJNRXexyhIMu/uOSuyNB\ndtKF3ndxgqvrzqFVmxk0eyVDB1YxZW9xE2fGTDOgCvXURap9QR8KZM4J9nrn1Ogzt7jBEfj704HZ\nVL8HU2WnafB+1NDxgugtg31MWoZs7+giC5VUC5hoa7dc9vsbU9FNT5fR5ozf3v3797tYGsmcH2Fg\nBi2aS/mM6JqJ4rSaK6oFh+5Wnqc9pEtpsucK/lxY7dtCcWQ0t8pHncn7E1jhJyb8SqUXGzUXbo1B\nCyT8jRoNNy23C2KPdfcFdjUmnbnp7AUtpwN62qySlv3Xz0U5EXU97y8tdFxE0cnjt153zSfb3OMS\nrDlVGh/Qwsi9CyoBK5YapXAeceF8PZ9xlL1yT8la2l+ZO8oZsBW/PIV7k8XBWXeWzjtyWjjkXogp\nC2Lm+SenlvnxblFP5MjHdLkLIhRChOx8UFJcwPVGKWVLLVGpIdZ8VNsih0z4E+8g28p1tUC4wMRa\nhTAxtupzWMdOflDIVg9KeDAMPXp9zX7ZJHykJWRxR6q+3Y9PVIaJ53118LYjbT5kA6t3dHjfr4ga\n6sqPWD3DDpfagbv0tUyujVlnxaXTUCPu3tzOIEoPC9sIuCYESsSkquOFkoWAnE+2GEkSzPxgGDM7\nvLjNRbflPpBjjD7xsDSf/E7LDMCtiopSM521w2KOc+kCS9QcRDIGhLkYCFnxICp2SqEvoFAjSe9o\nTYG41/kG1FuDm+R+VFxytSo6hKqkhqIt8dtb0dDsY30Mlci13Rcd+MS05Bkihxs+hx/MHusmBKOm\nMcXWSABJJeJzN1ID+bRm565QsBExStKd1TmzjAsdljAUPv24FISbs5iz1ruSFpaRugTX0vIHGAWb\nvG87IsgEaDzpNSnFPVlWWb3Ae1kcMx2LlRb7534qDRmszfq8fgmYIwZQrsLjY2WjdhrsiHAMwmVh\nj289MTKDn9SH2Aq8pcgbc797NRoZvcxtJ0hD0yHoPpWJI+YmG128Pp/E0A/GLhZCfd9dPwhXprJK\n60DQduAqe0JXJZUhh4ziuj+sYnoQjandEFhZGa0cLdl3CZ+Tgs9w3FiHQ9o+KK67QgGrOT/N71tk\nr5TsA7eIZWGwk01L8o9+qmH2JnRrG+zQEEzjEK1FAz664FHDeqTSGHOpHHw4lR5PELHyFxVBRkqN\neIzgX9sV68iuU8n0DfDKic996LdsiexJexW9WLfH3DXMO8cwO5Abb6S1T5kFK4Sksh0sDSt3Escf\nArHXyYGyjOtQJXSZW38Ldjmje3CpMA/HYzl5aXruIhqnzy0L9tnGrNHIPThnvpk1CVEQA+1eMusG\nMZIyNx1nyaZ+GHA+pkdcdP90dDpHKZwqsPZVHf3kKHY0u1jqeTGchDgTlz8mFXE0HTq3HbzfKnMG\nY4zbW2OP4nzYZWPS0pgl2IcLCrPAA85AAWVMa6Ceg7mYLxdrMm0Ln/tOgzauSvkKI/ViZs1ahKOr\n2WeG7lAVi52tQpol+rSeDks6zGvoP+ePTUgYap9zCWUfTadF9/i3UdFf69hTsDZmD0YQrT/fC0mx\nhKHChOT2KdWe5TIrnbOpJ+I84InHqS1QLscyRhBYy5vOsM+XA5bxcpDSjulcZsRMdY++KfgzvGiJ\najuh9zs3L3sLdv9tCsf+elYA+GbduF7WdmxEGpEa7iKfjeJY4zU4oazPjTzVIdR6JqOFhIhziKmO\nsjU2IhcGEuVu0ogfcgl05hvDseGWlLz5oVJU6yXQSmyr7O6l1MRqaqPyKLBIMLYpXcqhMq0/R/ab\ninKhZtKEP7YnWJMq1CH91hQFThZ4vwmO9zVI9fxlfHMUoKxTIwsTHDXoyw0FdD2hfdXNZxhe/f72\n4Wkgp2qTz90wVlz1lYM+jJvggFVY+7WEQaCoHUu05e+ljIcie5sErvk0ueTOFywdM7iGowcO7d7e\nuhLyo+BAtsxpcGkBGtqomxgkZlyY7RePmNKMBesg6ouC4tmKlrOycTjVGljWsaY4mPLSKGFs13Ra\nGSwSEX53xGzieC4mFPwvJxIcirobSwW4pdubhvbdMEosfL6boa8QnLBz/2mETCSFBiJbu+Nb46H6\niGuD2cLAIuwbx8am8NAyM698phBwoPVElhRwpmZeeVpwbWfVWoMWq2v7t1oHEBH/VMcZ6PpzTcc7\ncp/vmAcidEHGZDVDjL+fl/tIQXVdSMRpJJlPqb1wALZTuVkD97DejftYg+7qTx0/nIjJtDAUI54d\nyMgtysL/yZlNf4EHhXvLz1XncBT5XlN1DiUVSNYQZGCUhU8UzCVbMCS49jY6IBUDzOVJnAOuPF6/\nHMf2nZcr5x5WnkZyCN/cm6ZZIkgwOgZd5I20Tk8LL0w1+tVygB6/J77LT1Th22rHnaGEDZEbKKIi\nEEMBRJ2zsprpglgMScv3wLsEiREmKu8lKuIYiP+IeHEJJgQy36vrSzm4Q3dLPSDLjqR8/ZOKCn3d\npgDbg5/XGvIVsThfR0tXjQuUKdw81GrqUM0MuYXkRjtzLsy6rMbTxOhCGtoIvWbkZ3ssP3xj2RMg\nzfUoGSj0PZNY6l9lCwpnuIJ7cWGYs90MGL8HLMAfCPGIPUtm6GGY7nfeHS4KIjKA4RVAXWqx+SiW\nZxSdxmiYIP/Hvl51ndadC7pc60ttuS06NeYHXDOO0S3vRQ1rMaA1jakkTxF47o+Jzcza7CiNSktj\nEXb3DfuBJlztT3vvicAdnTOu20Gk9HYImFU+V1l/7aGLrH4/rSSwmdoczLdNzpbPA2hNeLWpRTPd\nnt4lF7BZRk3h4ZwjdtQp4S0xFB3VdV9jJvtgJicwK1dzB0H3zAbJTvRTzN46JGxdDXOLV9Plgmhc\n3lK7uzj1V8wDQnncaKGeiLzwyK94e45MybepGzrp3DoeHM8I4HgjPTcRt7qL0nPWX1LvcGwaMdJy\nk3Z7nH2hrilPTCD0VbiNxfG6Du0uTixzYusHNlfx8ghsn0AHQec+Qe4dYvyN/8+uAb9ZIGOJPbAa\nwK9XZk7oblrvouXXXFBfbzsjWrOWnX+GL7ohONrsy8kJjey1WHiulVvVwSLudcs4F3gwYa1QN2JZ\n8bRw60FZz56Ne6LkeKXCfZOh0FOiTm0cRwrzrWUMTrM7CIT/YXJuJsqr/0mw2ZZ7NBFqXHLsxihZ\neFB61egffeahE+lhoLQpiZs1e33waVVLxDfY/evj3FocdMGNoQMQK/nWPz2KxxQXBtQHVZOjNrdh\nsx7U/Wnia3HajdqoupouLpo60fgJXgzGUlw8Nw8xfqgoJVF9jI7VDkdebQRUTW8U7XSVXMXF1wF9\ncPiYqw99dhUqF/Dqn38W7ivfQ+4pRrdLESpuSJ3k1DQGXMaSrmVUTgdaC40qBl3HLDKLCCHFiyw5\nHaHsZvKQ4IwKZ9p8uvWQiNYgzB/dywmnnWdg01VvpSWfMPsaIXN+TZOjB3x7At3FLyCvqU0KDBcP\nNSLmiavag9CucAQ5X0a4CbO4zq2rHFvb84VRgV7X/igswCO86CPlH+OTjiXC+98PSbQyv3Yt7yjN\nwu0vs76r90T1nhqxFoi+c82OdInCNUEyQIyMJJH1ub9t6qBHzXXy1lf2qd+S+lqoceDEDqwwc46v\neT7zK9dsLyQ8OVg6qprjyOXF+KPyYj8pvCgXrWzL46iuWuIGmQGhIjY5ctoN0taZPkzYnBpexaSK\nplkhhI675tI07CXRNHAYJ9V4WU04ItWkJcraQMbPh9pQd9jVjpeb156ehydxPUL5aUTpP4UWbDiQ\n6v3XwS04kaMW4C1S73RsASKsDIGwDxpUWkE/Fx/xjGazT2O9XC2tF/HfFu09QnBwAEv3xgxCsSgG\nhVYJmi+uSU7Pi0yk1UAx9CIBJZfvXCOBSSeqfbZQznoPl6VUDETyAtFWk++1ikObWg/mxDHhHMMs\nxxa/A/VfI6lDgdQWlRsDVfzhDYEuoBMA0A4FWpgfr9hkcsI6UjGOSyN8vGGPWfSf1kjG+4Hzkofl\n620EcndQrjZ/dZvi8FeOcveao7y3JpYdSlF2FJQpUfvrBcdHMu5PHvrjgysK9rHHuKLSrkLBU8/s\nARpzA/e6gYZoH0HpWEYwD48tt16u8tRvblN/h5H7g1tmLXRp6u77LuzB8AsUtEPspLTA7AjTXJ6g\n5T/wROxlhGKoJZC9/+si0e86GYGpR+iim1BlYnv02qIx6mX482NtCSam6G+6VbYpVdyX3t2Lm0qC\nOSdh+hlPvlsHAciO3AbGMXHS2MJMV7JVX9IQvBu7D++EeTrzHGEBigjDN2R/GdKaq7QBpwQrhv9Y\nQB1SI+U6pyEG7T5xpAw/BOsMczH5JwLlaSrljxEgzk6CkjR5t1JlKntP1W2tc/QOTiNJdAfLDJ36\nJcEywJ4KCMoDcSrl8NTApf71iPxqy38aNuehOuG8CAcC7twSHMW+1PdIlTOX/JGw5ydU0MlRxFFM\nw5PBJ2kA+0TPwLjn//9Wc/Z6jMvVS8yJ1hSLH4w7pJFT5ZhBUQXfcZMRp171i3T3Aw08GkfoUZzr\nyIQ6aItW860T2VbybbseJ+5ksBUs++IuROqDkR7JXmMXdZYpF6dcioHHU7F3r8/PSCZehCbLX8eL\nzeS2cyP103uUmRO+7BIJydB88XMvw8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5BPlgv0Ysd+eSR+SctxdgsIGfUYDU11OM0zbr/\nWzLoM1Oq+kbqKRimCRPQavzTq28qw2vNV76NgLf+Mi4voQMXDED873/xvIVY9TQsjopYhTTJgQ7T\nDYAvw4caDJO2T69XIDBCS5MwBLxZp7dspfoN/4oGjaDljcUVf52RQHBD0be6K7+UgXh3e722sNlr\nGIWdCtUs2ieNFcswyUkhb+J/TQcA3Q/BQjg525rpirxX/935A7IqWEBSrSJUyQ6bR/6RI178+VoP\nb+nZ31dSV5cLusb3bgBEdqMgFpIZQ04+C2h3rT66h+w8lgB1i8lDhFJYj6Z914taI7u7XrL9hdWk\nnS+oZs+XLf2TEHM6XhtWY0UfGTB4gk81QcHMPBR7FSj3PPjs6NfrpN8PnEta5+m7Bw8yWJ8hEufG\n6GNBPRuCN+ST78w728pgI2Aj77qgmO4bfF2EIh3e6jnqiqqKZvpottUU+wOnw0FfbAyzdkZHKegD\ntYerAldliSEsyacASt5YCPbQ2tBOlTdWlpRKGK5jhAdSN6XMihXy+VfCBF+iu55vsDQpKODwBf/l\nB8ttqqB8/6nZfoXzhq/Pgq6dwlP2EvSsHywtVGlAv/1vlQl1lWqIB0YX39bQW0bL61gJtp7dIyJN\nGXTGXiLo5VjnKbEblEGRVajzzcIM29VWYOsxCrtzGGusMJRb1cdgRqy49yWsGih068zm2wuMn/fg\noAhj5GcjxA7ozuv/6so6Csemv4QKW0vWEsu5LBWrPlIP4vocr3NsGTixATur/amAbbTeFCIGYoaS\nSjoM44N3wDyqsx/UFjyLFnf9A99T+by/+5RHIeoNkEG8Ghax53GNSvtO42NXxbhJJmixJNswdKVg\nrefi1rMLQQIDBFMeXpZctKcGDYHnTa6qWsI2Xxz8s44DR6MMt1MsroC9xPrPDUdujxc4s4h6R6Tx\nb4avq0fk/TlXz4ay7Wcgeldi8emJ5XtM/1MLpbTI5e+rGvBBJZn2f3R4FN1XVaK1leID3H8+MPhr\n72Xl7ZxK1k34nugWgEF7KkgInRkOy08AUeTUF8rIEIXHpXm6PzsCJIgJgNh9PrfxDGoh9XFHzHPo\n95su+nlqpTVGpiCjjD6GZ+YE1OZPhae8S3cdoeM4FgcVXsF1NP7PIy5DJ/R9pQ27TJvx5PdeDcrq\n5P4jynMDt/WXG5SmHtNJV+WD0q1vQMIkdeSX5wzCHcBDiWVqjER96rpl2Qwbdpo/W367GH8KPvUf\nAitgUV8GOu8TN4BBXonsdv684d89itGwwRGrKuVoUZtt+y/SwlhSTwA72MH4a9QWBe/jZpuc5eW0\np5DSHEiITaA/lyEk08vTfYQe0gsbQTg2dvpUbshMmvAWeWd6RoxDkEVNp20ryoGQJ9utSaixLGtR\nyKaaO8q4EwLtIjey5YKY0a/3Qn7OLrNo1W8xkOTYeRhC5E+kCtLKeve2NtgVQaSMiYr6SuYyk4HA\nTVxnfpuozhoMblkqkkj+JtQkbwJuxCBzRB8cLs2Xxd+Aul/LIjAAr183pTtklyhzIwnfiMNLW444\nc0/9McUB7gL+/gks92ElnH8khm4fpLUp/DwCEFKDend6hDZ7X3Cp5Wo4svtWu/v3fw1kgz6M9bUW\nJ9A61uWMsoS2wRbMsgifchp/N9DMHA9++hvfdpxBqXGOIw0VmqNAmPKrG0X4JEIU/6SKZRNNOG5E\nY2uVsHIfAYgw/4n8mv2fF7gvKyUSoHTbURYbZcKmmVv4q64b2x9J8+IZx6XZmLLBU+XJ5NxJsW6A\nTg6MU88JjupiEyYLylToCFKqyik7AWoTVJC/p2Xrt0MiHG5QRpKPsfMkhjb7gBS2PrvNBP00ee6P\nVSElr/CEpazyvPPZIuF6u6ze/u8Zhj1w0aneXH+14KnaFc1B1k2gl84kK+7MadGPCJxFy0HNW2zL\nsCOV74lcGAUuSqkLylCXZiiGtsicrnSiyTRstEasEvEkx+V+kbd8R/wO9Y0EQ5a6o3IFIwJzO0sB\n6KJeYHUhNr65982JC6t9Hoxt6agDzUeijvPjWMRhTu2CK0iKcmGyXsVdYQgI1YfBnQIOTXJZzY0O\neNTS8hH5fIPuWrBg6F9lwL5FPZd9APt5Wkv5fo+RC47fWbhQBmxpdUXF6HLjzGuq8GBLkcfkzGC9\n/ArWqnKORSiu8GUHX6crwulCXqSvYjc9Hypjw7TPuTVvnZKSiPHGRAaREIspT1dEiZHFaDF0Z1mg\ndn2tK03yOJ169Ud0SUyzXsOmi+JRIMM35oolbfoV+uW7YomtxUzbnIzt963yB2eN/GuMQQYpXXxK\ni7tsbvfSJNE3WE6xrJIq6MV30YgsQdPl/2DyCy1oAu2HIdIBAHwXptE5U3SFKDIr0aP24ePPJFXZ\nrY5YWECy6t+ORaljfEW/OAWSt6EKEx9LBJSAHyZRXz2oMrV9qUImx4xa8doClkt/i4zWMwbCsT3X\nDLxxvqAK32Nc+7kxkOtjbAYSVU3E2fMUSQV8s9CrmI/UELunLGXFd6HE6q1HgjODgnM/ZQ1vJcMc\neYpleSccQNtFsdHo796N82J74xCsK7uXVn7Q+0I3tJ2WDwPZvuZizHh39LkRwQQmdVDc/J4OSoky\nDsVgjI0p+2PatJf8L9EPyFtQmQ0JApa5FD/MKz1u9czJavCX8cEDPvGAGAczTWw2uWYgANc5p4UF\nl2p584ecb9ssVvKqGcKk/YaN1QQ/43AG8ut8UtlQxmxQXpjZqNrY06Vr1tuRj6mEjzJ2ijDFBdCS\naSlPbp1cld9hYjIdXm+u36IheCLV4JAjyQlfENRN5ctVJQ65A34472DzYIEMWaOevpdz8LpwMDrb\nomcM9KS+IZcT2FP+FpPQGXx2tGz9IySsDsNw9FmyJjyPSCVhpX91n06Bm/TcIbWasCWgo8LCvra7\nV8A8lh1qYPYC0T6+PFPJbTz/SA/59IjS0EpwAz2Nh08OLhek4atEM2Q1fVVNml9qj3ecByeuj4vM\n2LIxdpGoWAiusFpbmhQKOwqw3GAtXMQj4isIg0+uLjC8TCGBK06j3P+QQH4sSzR+yRzn2vthMXfp\nHGb6shHBzxIUcUgEvXPlfRUKvuVCRqjv8YE1eQQ52QGrqgudZiRiaPKFJW75ddXYlOlBr5ZVMSNY\nBWGoulXjstXKWx+SJs7Bzm8Zm8MKSf44HLYgw6h5r1v8JFtiw2tMxNvce68O5qF5+arcIB/4Tm5X\nCNPdJv2DyMnAr0TnFgqM/vhYPt5dPqDtSajak7mXYNjaBRdhDkenWytBOccR8UOfInk06KmRCdYn\n/DU3FiBgJ+AKdlDf41m248j/KcteFR07COdXIkvQohKy8egbvc4sTpjgIaaETRQ7/l8WtgtIi0BL\nd0EVC1t3zDqWlEZYBBZsuXzC4ma7BvqOOTSe0qKePROklF6IUVpmiQWQkH5aTETOJ9XJgJKKFbJa\ncmUpaDWhISKweR5Xv9EZmeowJxVP90+N4JBDhfZZbdtK5hhYYeAb5qYznhkPD6kgi7mZJR+kxCOx\n4nQCYaSxKwdMdyNciGoev/CclCZ3k/Cb4NSfadqiJAkCSfCUnbRFG/vUC/wICZJki+/C8JunjzQk\nJ90d+klizyWMuzr+5bYf+vIHjCGHOxHArWLAWPkRf5WH3vlGZgTnVL3f/fMk832dHFj6UnGUj0wx\nGxP5gWFpwUro6Men/V8AYtf1y7nW64E7F7fOJBOWJ/DlPBSYJS3RCBnA5LaskopBso435CmmPC1P\ny+Tjs0FpULQ69Bf47RHXv+V9AXgTK12IdFwqZCX6euUungXT3WuvAIGzkz97OWRGaGqetAh1ecn6\n4yaKh3rC82y+tgJYpWt6mLdj9raleyQBJ1uFwdWVUnsf/+dfEC2sOn1IWMliGEpBZWCKlOEk3QQb\ncZMwetiYbzXTOBKfN9RZTF7aj9LkbqS/H3c+qQAYbplKQeCg3XHop49pc2+fwYD49dkguyPfUHZl\nFgbzOZeQW/j8lIvrs75f1kG2RXfrSipSYqvqGp8SjPDvHL3wd/NZ2mG0LHaIG0mg/ciih9+qn7Hw\nEXPYWhJFOswmiLgdoUyiK4YBKlVLhb6m9I2hU2K9HfpcK3JyHMzJbn2I5SJWQAE9+b0DjyUKAj6j\nMfHC+a52JEKkvAne05p02nnaGk/1MXvd5CCXk9OXdUma2uvP4SW0e0lOUtY1DfpF3AKGUjyRI87U\nRlguRxedaDyIv/Er+OyN11YZwEfvDi4MqE1o816W0+OeL8tPBCzytBVnWuhkc9wnijE18uqCfSb8\n8odutiu9uDFz8d+JXSjV7LSOu5QjouGbsmIfe+WEt+7vPkB2ULnV/sA3W37eHvat9uf/6lrXbEMB\nscgvH9gj7gfnVY66tGVIvLl2ICHvsPIYwO08FGz7lcER3h8no0g8nelO2qKdHYFkKmy+NhSzGziS\n3dAISETXF4/ezAjVj9/S1GdQwyuIqwttvsZ762j+iVf0dbRWt1NVCi3xGOH2vR7Jk8FnjbY6Di7S\nVQa2Jf/A74o4lpaemRlYMfwpkIApjX8D3se1h4buv3OnK1gOZjauVk5A2Yng5eq96IAK0ndd47PS\nXmvIy6nR5I1RRn1nIfdDkTr3Lng/f9q8etL17YXrxtM3l+lRFl+GNfYKjTcjAi+B+2JxcAtZfDxm\nW2lmBY0AWPm90geNxjKI/KGTVLHszKI/e5HOEUeXYQKcif0hMNpubhQvtSPhsCZESv1UmtIzfbq1\n9k58zlNq6rXzF8DP87ksk/vrtgHLm/4VTfbgjXg/xX/A0rePI2O1TUUZchLtgrkaYjiYR3AFi5Zc\nACktDnPXn3jFYyiRZaduSkoob/bZ/aLaWKGOvsPUi8wRYw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protect end_protected\n", "num_lines": 1194}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\njrmEoJVd4FCdq+6JWlpwvRU7QGZiK/hswKjicsqYT2c9IPveUYVIomyna8nr/kSxWkcALFwHk2Fw\noHVNAKOKVw==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\ngZP3m6IFxxJnF+R0cE/FTTayH+tKpHRZo2dZrxVN1DCPNO/4u2mriORX3MF/jAx4p8aCQf/uTsls\nN4GKAd8ThvS4Puyf5usQ2Jchm2pg1TfLen2niQU6E+3pqNaaqrJ2kG1cBiKJxhChwiG4nqGvV+Rb\niUdStJv9vgU/g/b/v1A=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nGMeJdvbWhBXcc0a2U1S6nxP7cC6roo3RazOyvYcS4S6sN7whNF3WnAqvh7y8isE0wNPMW2h249SI\njw1BIae7gkTvQeCJwdRaPC2LG3/r9+tsTXE8wOD/DMt1eVNOcxuWIRpoMf7YaTmgBkrUvIm04Flx\n3kwsGk9LEgwz+w82gzD6ZG6Io09+6xNwj8oJZuEnxY9vivRsRJXn7fL4mbDR2oMp9TXUCWyNOXWU\nfj+gotIsfT+kJO0Mexa+vlClVXcPso/jZtLq2SODPMwuLfu2E04Ks05OHrqhTCLQ3qSTXXs8LUN6\nWsYJ+f0hbB1ykpjkxAREf/ZNG4mtRug7yLadkg==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nMJzcepxYrSqmgf1bLwGjwg+MB2F+06FMvoVuPjhEwWifRJ8Q6DmTrsu/Cyvb33vdgKvd0fAABGZa\n9/XMf4/wKBWb7DenkDidY4I1qzj1OiRnPBBPCwvCOdfNCbpO2DqFQKwjhM0qZ5AuaAeUbEdc1PjD\nxgGk2e5d5ZlL5X1spHfOOGSSi+WCz4mwlllvjZF09s+wkY/9RVtmBszX7YuIX1eKFbdkDRBDxFfQ\nqcorPYP+Rec307GJa9MYsJS5/y6sEmgH8cEpYYxMBYykBz8Rwu0eD6BeBk7joJWw8PXWEqPv+DcM\noXoLtWYHau0NQD1IRkZRgWFrBuevGGJKHGeMCQ==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nBuEnx6LbINy2H3nlMwzG2l4ax8Vxc2dZZebOK/D/PSRONgLTntExmvNdCfQLUMbj/d86OU19Mb4b\nSfH6/9ZyX2MEXcotgxon5A/j9uf3ZHGyRrjuWXz851QnAt+a1nsGHXOTBveaVHSCiI7yBv8WCvHy\nenlFc+GV+CQM6zktFuOC1U47dy4j68Px6kGORl5yqJoDuiLZ/xf/MAVPlGnWFC55TFbU9IroEyTL\nhu/ix+TWMiqr93kgevxPz24HGsovS0S8MT33oQlmOKRMqetO4Nc+K5zorwoAAjkowTqdwrBEsV5d\nAXIhEnJe+5AXpDT3y4FrCFCem0xpnqKP9BSGOg==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nXYmIvG2z2AlsVw/Z/5pyqeMRgyd3nLy7lR1L9ml+ZGzHIJcIuxDlb3lb/xSMB0BgGQFV31k7tIXQ\nSWOETSrxNvxomc7XfDRlbTQ9slGUFzC3iMAwn1dl+SKy8d0XnUSz7NdHzSgBwTeD6uvvaYxuw8C9\n2RAk6QyfrA+1zhqWfsw=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nTXcZuW0R1QuX8VeTBymb/gNlK/KjlBlqUNKlGKs97uGhjfOvGTmXjNJMKPOVVbFs6d9wxYvTsogW\n8mF04RvvZUsMDyCjezxg/wvPSXQQGlJ9r8uaD8qz4a+9Iix8RSCdlHnbNtpCFkDrkCdiVPO5uPrS\nx+kJSBrQezY3nlHjuEeEKOrbjNiQ4i4HkuEgd7amVFkNdLe2UF5Sxjgr4iNH/7QNUQI6tY4VTY34\nFrGp1hLXlzT8BUcgYSDEj3qHlQXdB8z7fsraP4oEgBuxYTd6e4KcZZWxlpwYB66zoy9Vql/CT4SZ\nV71DEEi0VUnff65xJvak+Yy6Oh5igFmZTdPxEA==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 12464)\n`pragma protect data_block\nQI5uaZJYcjht7wCU8TXCVIWhMI2zzOyX+FMvJISLuDQ3wTQUGaSBsOrovK6GT5dSlE9ZLay8htqK\n+hYB8uUFtbzwuuApCtp0uIi86Sfdez6Zn8UA4Kxg/c6f8BlH/HQqFuCBE5mgGSEikjT63d9kS4Y+\nTgW9wXSLize21pPZFD/2TC1DmMHowOofNpv/OIbs1Xi+yZHMx50zu0OucQlRknGwN+3jJYI0RHOP\nlZU8sBK2lssoHeF18BMsukimUj5hjULU4NQPxIeJR6JFeqwM/q0LwSnUERzI6V6aC0udrM06hxSg\nl//udhUY66b2PLPBUB8xr4a39Mn3iIKt84eQ1tztcOuQWK3PfF6oytJKsiGYg4tq0fR7R/Uc/Bwm\nSRliPs10i65hZCjWsO0VByFd948IYIsn1gZoeDn+rLbi5M5amW+RSLRkgtwivIYuP78bACPvjRPf\nmurcPy3v80LEXz3KzBW+hrqHu7dNvseY3N54y8XoX8QlnC8RKlAa8oc1NcTxwuFiB4jGyoOSMWxW\n8Qvcip9APzed14raMvr90vImfeOfBIohVBvRk+6BXop64SwOzNdCQoyyDht0yBIEoa7imuVD0LCa\nLj4pNKluKOg+LJBGL3s4QgBhozCYKwA1NNI4NGPbyr3PeXzakVTMkc4cowyNlPwLn0bzomDPNfVr\nRZ0Do9/5SWYk8uZ4kQwGDtjoZ0DKDuUrSUoY8pxvdgY5TbLVoauBhHjzDCJyNqTlXkpUvRTo7nfi\nqdvr7ugDnwgcNidM8JQkbNLeFNG4tUKlBAv38umlsep0im6N3qEBnGnpy2JJIQ7gcYsjgrqrQkkL\nj7bcOUsoX/snCxWS52FilLnWfUAc8jCfQjQoVcNmePlWnz7T5Pkf65rOXIynEeDaaTO+YJY0BKv5\n20wN5C5Tzzqzu9xKHZ/xMYpM/+dXOvRlyajp0J53BK13TSJWSIx0OSXrFrvzZILGzRVaNZc+t/P0\nXV424pR8cirn/MRryTweaSR3bF6XppM80s16h+AsdKKbuscPbuq7FYhRhFFTjS/PUolVxpBUM88u\n9CkwLMrycxd96N4JwyNbUmzoF7wEoVsYcsA/BQFfV7pjzATEXN7U7OyhJ2zl15miYGNQkdEqyJAm\nkINEY3mtOzyjggKs9bobTaDQDc0r2yVGZzkaGzJBi+1xOY+DQuA2OUqiTZJV8XXqRpCOanpzW+oh\nwMEM1kDSGNVsJT0VhiQmCYSDvAHWNWDH1lJQBRQRI8OxiJ3yRsiwYIyy3eYHIgfkBMixp/YujV6V\n01HMMVzBUqY6r3Yn58as/LyPnTRk/2ZqnDN1fLCbTYITTBPNfcvv8AtIoykF4ujhVCqpq9ilQobW\nUqvXDiARLc0fd0PNdKmP6zmpYKxCRLwyVjKIHyvsU4uwecSiNnMAOpCJEtXa15r+DRaWbl57egyf\n8JEvWXwg4EuW00R4g4QS/hkcNFSixWrG1JSo66QztrZ+M9slM+pALATvklFSK5/n2gubjDYHxrMy\nE/5VmG4UPCaE8RnYHyTUi3HHp+Icu5qFccTUcBwrRszzFSk1f5GIfoy8GUdWeFS1uNIE9SESBEkP\nt2YY8eYN9rRVCy0jefEZEjgUMnwt7l4TNpcPh5NFQgO0tXYDMi5DihqzjFA6QWF9LUDtSEip/6AF\n1TzyZDs0TgUCAQFOPKNzyz3Eu5uMY/1AJwlnyvU7+1OqDpYNcdxYftLb0pPTRssCC6T/9+UcWoxB\nE2/7myErQRIpRH8Nzcuf52Mu/346cnD3Y4VjGWGPKtF/tanEgNR8XiytsDYRFjBDRLuRkzrrFsM0\nBoy3UdT3xmUwozDaOCdYcpciYOntNTDOSFgW2USkzzFDpjUAu0h2iqLt1Vh3DMZMvpGeiu7RDnnE\nUClI5ryiphOc3Yr2HRyoOSI+v/f4wrC5ubFNUgAiyy1BetkWh8Tj4r8JSMJNqwM6rkZ/R3TaKMED\nFvhmdvyrzupOydXSLeWZXrM0EOHhCreO6d17LbVB7eH4+Wu5ENs6nl7vcNzvFNKUEt/13+boBwjp\n94mfvu5Lt22YFmEMv5uuyK3DVg6Wz51dVsBbLwqd3gTS9BlWgGtkMMFkmpPEkqJTWBLJRqiE7Ti2\nvyj0ReymZ7+fexZa/xn3GWa1Y3ypZ3P0a8nMiz5OGBisZf3IAgwgC6G82LplFHU79cXs05msL+xW\n+WHYAr58XhbfnvuVZE++2Lugu08YF/XBxC760WFyWibH2ZlCUUhgqhhqCccgPvJwULvmp3J84nVp\noRF+VISLBp+1NPbxXahygeWuYp06CsQhHRt23VkUK8N6PTbDssVZYw2j0/cqzbb/J2HIAfPSEbqV\nlYrHReoxBwhK6SDrhERBwqlgA6T+sd3ud0GLyRXENWX05hZ55nUUnKIUMLMmUQ0x8eNLKgCINZfH\nXI0vRAfzBfM5nuaHiAAs0JFnbWcY8FRrSwLtfAqggAL6zrDH2FLBNa5dLjqJGcps/xfMNmVckl4p\nZmvJw9L4JQVHLLc0zZ11f6g+Qp5mmgI9WXCdM3dOQBII+EmHSxf3y9xzFgj8XTvbiDuSuVlK/kNv\nD3TVgk0rUwDtnOOrID+3wptTz0kRovE8x5OUT2WUJOCzxWEw/SlbxP25kQMFNLk6blgrRd/5Zg25\naj9QLUzBJSPSfmk3LjPUiGhoWsOzKefZmU0VIDo1ntqN9if68tkFKyAFnIjnY4QpjwNBt9OdKTIi\n6bauyHHXniQXQePKvVMSxGk2HHEUK2DN1EHpZAMUUrfsNBPFZmJKK9tiYzUAB5ccOOC41+CSem0K\nBBNVT8HQwoxLetkitOW12u7YeyPvERR3xbNkqJ/ebtkCme7UqHFpoqFkCeLEzBhja9Qqv2xhc5Vd\nDDPo9GG+f5fPAWNx13TlfzyUiZwYImR+YHY7guyvIWyxvLEQevmKPWZpOLRWT8Qakca2YJnlVW2l\nhnsoTDrWrctxkQzAaDRkvGMp6fCX4Js8RLuMXo4iI1EszCXWPWO9qAYrfz8N+rL4I41xQEIPzKy/\nzmI4WpMq/XP1+/U2sYXRZx3eQzKYom5JC7RtV+7Uz5JgqstiiqzJK9BsTjGtBt7FCG69hR9On48T\ng520UrpWx8vVIw7dU0dZMiObWkJhfSGzIGj9xkJ2zMQTH8cAA3V+EQ9NvP1G4QPeuf7yWCtWLGIw\nw/hGd8cwdpTr5w34mcz33fuIejDEYFjIxGngZyOtB9UAyNe7T8CpDcuAdsBrnCLE/qi89nUypTpe\n99RqPn9y0YlW3dlWu3J3laBNaS4hwNoHIwYnzKgPFa6UdZwPocKEZx1LmjuDwaf0eYu9f8duh6tl\nnz0sWOpIjd15OOeaDF/REGUOgL1UQrTpMta/HPUhptfiqJVatfxkpoiU//Jpy0LwKzRhuYxvL5DV\nHX88HST5QlIv968cpHIlIdode901gDJix1cAIbWdGZUyZhjQnB1zMniKiS+Z/ZfVLCKikj04K9Wf\nRMt+MWy6RSq3XJ6X2oL2boATraVxdElz1KmtafDBmxsW5jbqMW/FMUeW7g2pZM0rmOFep5NhV5My\n4hi8hp4/kx8ky+98aUTE9SaHKX8Cg7OPemGWB3efub+YSSmppbSLQHTYZYyGmOEAXxSTQN2GqXXE\naz6BOHrv13ikpXtwOQcJV48eidtfHAVBQ42XPia7EyiDHuGFt+ATPVftLUUriqKv6hDoJED7HZ4b\nRFqE+Ye0t8aJDBN3nKmxzISyM3HExIgRThbxRtLZVcD0cFAbkZxgv428eJDwfySPH5mOy6k6+bNT\nSs1DYD9ijTsGsC5/6u8r4U7+iGf8QPWrkdo7BRkDwgwQpZJrNDpgH7ukr6qSlquJhDwm6L2aTZRb\n6kFyJGdMjTOFj1+MdiAcSJb81AWGW3Jp4zL7Pfo0tKkxOEODovcZuahxiqhhTrxkz45pNcu2M83i\naPv18qwg0OjJtdRZFNcnsq7q5+L0onyooP6i8+r/Pe6b7TQG5l0datkQCWU7b+W9FGbUWXC4DHv1\nfqguBHoMas1rU8OKKiDxvTzcvYWC3joGPAVdyw4aVRmpf5RRDxR3zJa1pphKKfSzgDPsAuTio6tM\nV6vl47kJ0FWWXRfaxxIs+9V0zLEGy2iH5DoUI9utl2gJx6xpPK/QylMSxRkeZ44wpvxy07ByNAxQ\nPTrsy5zElYqWdfFui/2HlKPUGnN1El9dezk/BWQ4ouwTheN3t14vovG/XXSVhS5sXK2RqTJXlCPK\nS1ckoCj025CBBZyO/3eTE7hzXNRVl2j92iqttJJxxHzmfSimm0QM1LOXThrlNbPypKDCuxrSFKoP\nEEXWetvZnZoKrMmVOWpPGYge8FEsEiLs1J+q/dj9xnJvWLjpW/3egThC8H7Gni9KV2Ucu2x45iCf\nEna7Ki1ddH3eWrKhApII3E7NQ6To5aVBGUJPEgWvHFLCI12aVROAlhWP+4gXP+unEQ1ru9qIbRTX\ndLt6YCNZlPXz4XSSexkllnhrSBgI443xLgpw5np6/hV9WIAxhW46CeLKsmP2Y3CEOSznpUWLS5Pm\n05XMsqIToAdfGOTjl6NOmJELcWHGlvhLgUHHIQ2A72G9eQa6L00tLIH2x1niGUxtc+kBuXOVb90i\nCa3OV+Cszly9KQ6tyZSt1eBPVFwJinb7XMOuToHj0wnnsH7wpBHKY7gwfoXvrR3H10IzjJ4doYGD\n0qC/rMEhByl4Q7aIfwrnuVuhqBhiAIYYBfXDrjcxtjANqUsXkrQBYTzlMAVhJFTBPfdxKpYLHm4q\nM3WIh32fxdO96heTeYbMEnXZ2YyuEQ4IGRFp3ZP9lsMB4g0X2vxvnZB3swzRXZ13swYrcUFpuC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brtE5TcAQfauyjvhgTfouB2xkTkBDnQVqrIDk6XfQGIJdbjePhf0p1/G/UDejVH8nuNzMXBN\nAEo4IfhBcVBS319AQimjbUj+xG4w7pbm1N2fpDfzazilz2tedvXcEpVNDoGgTq0EMoTJJZcgvyyy\nr3QYza0jWUOk4EMVuge1h9K+QvBKf/FfYSYypFgIIxKINr0v/GPTkMfg3Brv32w+Ud4CmpsotP64\npNELYqeu89/n4VwueyhCqcNcn3wChN4oL/z77VyoSt7AMazr+oXaUfGrBS4rilZR10TgWEntAFDl\nX75bDM0xxBIBVWf+rfHLdRiji2uo1IDcLdB2ROfJOuVybwysskgq3fdsrOWiXMbi4pj0wLvhAPp9\n/TADeRCcK7emhQtsUTgkxtiMPSi8nadAdJzz56/9korEuSlyygSX6JuC3YBbIXAJk1oFFrW/BO8I\npZob6R4kbeUd2soMDPPFut1pEecl6njInWR6KFIRyDxiWZVp8/5qhn1syHUtMEIAzO5ndj/OSNSX\nENJw8oU7NKSdphMpuW2PSv21V7NzCiFfw7n4v/PC9S4ZRsDpaS9a9xfr8zMd4oyou+ZiaSBoWCbk\npRW6y1ViUsWysaWdIjqMxTRlDP8QMCIQSeDikhKP/IXMM8S9p9iGoCqPuwfDIvD1liryGutO0Rru\n0kofG6XzePxKIQcxLwnFN+4DaQqKwKKDvgItgLwVtZAwbogzq0QkvR1knkGOO00jctYLF3cVrQoK\nKCecCIbmLSbJQHiCoKJWUY9Csf/JD5JIup0KBzdDysOygWzpOYmG//rEjQjgG4ibjRtYUApoj58c\nYPrNr9sBpiVIrrvN9v88/TlcEecnyXRs5hTqYxika7dRUMLMuWKRB7FwWpMXkTpafqD8zItZs2oy\ngK7QZVNeDfBKrJ65x3KRVtdbrLoKdwkYZLnreHF1g7wG8WnaA+sFemu4VQoAbN2/7qFPgs79foC7\ndsgAKA8cwG+MXvyp+2eS4v+pICpvaZWGYrI1oMYJ7S2m6JHQnrRyd+qUtAkim4FE2BUZSrysOmdg\n8Z/dohEXioIzjcIYv+BX2yAKnUyIPSBoffYz5p9ui9dFb+q1IKIqgTBiaONtNsKAWwJPzYNSn5o1\nTkHr7jDAxqawh1ptctBjoaqv474zvgMUYN4pmWZUWqhz93ozBu3ynJA6QIZHX7kP8GjIlPdD00N6\nm1xsxVZXaMqCyScvpo8oK9dAE7cNVSN4sLxEuqttPX76c0qmnapUKJ6gLsvWyk/8R8brOs3aerrp\newVmFPuvWHCAk+ca/wE7PuRhWdE9PuegQDyxGTXrmA1pKDeDvXTEbaCJ8P+2Mq4Dxi000e69+3yA\nlan7GR4O5kn0pkCO4XJOEd3fycgI+RW6nf6NoCMZe1oCxTUeFtXR97RGlmPn7AAugrG2J8AnWNl2\n7WN6CoStYLXNMBFLEuEx3Be66bBQpc6Zw11yGmB3uKyBAm/NSgZ3bqmycpLNC3Q/KwdEZ6wk0xGj\nSz+ksCjMrPnVV9va2V7+G3ZQAfDFCfDv9oYWtiy8N94G7YClQaXVR6gUIPJaU4dY/YoNzz6vJnQK\naZOWBWHaZdVum92Cy79VjVZl+c7HJQvZBKYsdgk+zJymE1woDncJHiwupTmtxoqGWGWBIYPuU4I4\nFYvCuiU911VaTTx5OokNnSNP4VNUQNi99JGkiz/R1h1hxBuvdImvZlpt3WcQpqXfNtWUAXr6nQ7L\n4qZ/cJ8xzbB72/ylMcUp7bk8kqCfkxKoHpJtb2LTiNwXNnbw5hYFjG/h72N40RLI1AcVTsY6Zx0Z\nglyO7nVlCWQEejOMO17H3PCEGsGsox+GS0BlOWcPNcVn6XsueqR6BFcBdc5nzrylS23dGFl9n49v\nu2EsUq1pq0q0Lu+sRbbEnbg0NEWQ2xQXJbufEDwCOAiewn9vkT+gtF0xHgK/6zv62g2LCBADT+vn\nDNtoAQndipPTKHbnF+Ue7Lt6JJ1evkabMiDJukW7s3Cq2ywyZcL34QffzM4YS8trCbGUcQW1ox7P\nlYjKNOj4yT/b+DVDGl3f4AWUCI5mIvr2fTYwr8073scJYzoiBjbEY1zJOoGfJR8d/dUhBFcRuxdh\nDWbTzRh8p5feyVZZQw/7P5dEpxMO0azxfXETUxzFcu6wQXqHXswUdsxzVjGo6JCTD19AUX/LuHdi\nyhdog8SUSh1HYid2Y5VK5sysQB63fSKVhIQajQfwmcWlD6ugCOsyc/TeX+4oIZWNTq/vtZsYe7PC\nE4ST4QMdwGUdoWiW7q0e90Mkcs/fOjlXkYIv4A8PKcrNPU2gKuuHoR6or4JO59P1vZ1Q+sqSFABT\nE7SNmfLET7e891BNApnIlaCL/KVeQWcVnR6vQnJsDGmcsQs1Fe4lxx8AOBj0ErttCZM2lbUcVhTm\nwQVKe12WZ4ipV+XGSvz92zCuO9xLluezm+o6k8uixYxz684Nv2w5X9IcE5LXdvgxpBrRrH2GjtQR\nsoKoiyUHaqf9Z89zkaVhrXIwj8HPrv81Nj0KEmZacei+5/XeUQ0Ghk4sCaJAlZUIuKLzHIOCjhXq\nFIVeuIqLi4uSzk+/fwAax8+z2KTj8yHghwi6GJSGBsVoyWQ9FjYeOVyMUbUgZbterO0/CdGRDA8n\nzU3b9avyc3OzAPWKijl26pXCCkckP51L3SSEsv+XfzhIZ7oZQtK3xcJyD0ojrd5XJYl0GpSttjLA\nNZloNZTXlj8sjBozPKnzqYrGrkQYkUZ1zE43dCU/IlPUUs+ns1tjonlWFs/hPzsytVv5VG/7yww/\nADS/yZAtXSFMfGpVaV4u5hjoLtSL3Q8GzdiMZ23Ww8defxVECH2lkP5nhZrQjapnfQZlQ26tew9V\nbUxmDUAy9PYJ2oAN3HJUGfOAW6i+QmixCB2xO+qb+YdxkYMFIBhM0c6LyNyIzcJPJO/3S08eJJAR\nfB3SbOP2/iN1PYCusOPvxmvOz8k5LYrJLgr8KI1dc1M7NhZpjAzumFEOvAMhKGmPATVnqm7phHq+\nu+zQZ5vi8lLzrLqa6ryDkmY+Y9RnT9YhIIWkLcyi57wkiFZ8mhVBREHDfhVV7q4KuwWMC8s9s9qk\nqU/jz1IMYoQOLwoQF0XV7m+B3PfeOw3ffHgFcha1YL8QdSF1oC/r3pUJyV2ull7Luh0oX0+bUk1f\nGEM4RC/bR0Grne6/xk40rORos+5iErFck0zxPe4pyJFSR+xC8lG2xtSSlYzFnD43zvR7kqrrlryU\n40KgA84Ljy6cTYiyD+2Cp0iRW/X8gRVr9ya1o96sNbiujOc6VrsUZWRIXvEkOibgQ2WcvI4q6qkT\nPwqiNXwe/SqmU7zz+OjOecaAO31kcBNmMnfLS8iKuFNgIxedXg4gnBzbiP7hTHq9KDMA5Nxjili0\nDM0quUOoqAU+Z+gNDxKb0gOLS+q7XzNXu1Ve/XDLO9vgcIBPNZgh9kbBhze4P+cJFerBcv0jFTPM\nkQp3KgQXoc0gAxJI6FRTOTKFB0Vl0aStOFLjhCiIJKXJDVENmiFi7iVSdIvgIGVfA3AtYyUBLLaK\nNYg8QdCTpQmDIZtjinEV0jg0g8y/pB3+AIpTYk1V0VB73MiJbbt4AXC+O75PuVOqkfp1WF5NtbUj\n6xakuQL4+9f4k83afd/TAbwzZ0OY3R6+8870qfSXRlW+VnaAflnYwNXa2q9x5px7CR+CbUNrPwWI\nrzMZBJ3uNJ1mkPZbDFRu09yhDUDfXUoz4sB+bC3mQF5HCLQCyL9GL44fgdmR+O4TsntThfcZGSZG\nsFTZKKklFVPckU6Ik4gRRc7oMb3YE+irSPzX0XS33syS1XC/x8zGEYKWXDrLyg/SElz++lM/bmdn\nMIEBgWNBlH24D4wfSwK5gY2N7tqMKQAlloHnx0B3nr7DKIvUfhBOSeXWf3BPRD6O3j0FU+E5liC3\nKZijTSmrCVflwFVeYmi25vHr3LmkiZY7jeDUDsyydEsBNvsfAxA3tRs3JKe+5eh3MJctfILSQ8ka\noV3z46lKdvITpo1ALWH9usW8rJKCYTDjFMFcSCj810RNfQNmDOhnL887W+T1+lYZZiHnKoUaORTR\nfcMAfEQicOYKCNMWGd3d3ypXGFBv89g9/+UtfYiL+HDwKl09GTjhS3Awp4x14+boI6L4uz5FPX5/\nEj5xm0wMQyts/IU/BycQ7vqA2jxleJ3Q5w4mtJs8E42IlorMsJLLEz7p1PbL1eeuR/dxArr73B6l\nLpeDIC/n4fHxpZpvOGrn0hxhOh5Ovj/BaK63Zzjc3QNCjThRWJoFlup8XVpZZH59Tlli+XvFZBxv\n9WOUZhVVINTQ1zFrS2lt2pZVbm0Ww5760m5psoer/6ySxByZG0GLqCPBB5KYGEp9hZlN0LrsKZIS\nEDXaYgZgf1vDMeT157q2FkqttL1M0VKgvVWDxKyLT4ikr29L03JvuWnxzovXtF3S/XgwYX7LFOHJ\nqm4+BMDjNIvNKT4RcPxqLZ/iBGPNwqiWDxhE8qSvWYzMsMrjUpjZKpqT9RgO1qDJnlpFsD9uVsnb\nj5VhWgxN/OQJ37F8CAyyn72O5bS9A3twTHUYsCMz3ShVua0Ydwlx0kpv6mtGzZUtHS+yITWD0zD/\nCyWVtNDZirP8g+rzzPA2p2s3EsPZIiuWRPoWl5w0DItQMRc8J4LdbPJyhzGKxars+5rcqFMfHBOM\n3bCBJYz0XyXyBUdKZ0he7rESkaNIgwwmiHTm4fEW4WUzIAKXUEXial6+IkOnxViw+0O3fWO95uTs\nrDc2NlMo2dVFAuYC39HXEgWJ8qhFxehyT5bCr45M7ey67RhGwuIgJE8/qlQzI/lodjBFcUXECAq8\nLDr1yunJxMqbU3msRDCkKzKsPrEF6cOdoIlaDs+GMCfMczlto14jMS18Mu738jTI21+CvJRjzz0B\nB4NSCMYPiIrgwQlYCtIJWBnYkL5DvvkuLT1K/vcyA6FpJBMR/ez+AzATI79+lydIkIpd8SKMzlck\njBqzKAXytao6WMIbXoMpdlkI2vD1sjRYuG08HZ6REg0adlwtz2mAzN+SazC/5w0n26rv3BRX2wqx\nBoTj8yHDUjcBdpX6tW7HNVf5H8c3JFh642Q/136Nq3Bg1dE6n6ZiRkSZnupKA7Q2RUnhKDsvZRGO\nsU+J2Wg9BeBdyXUHM88eUXJr8CwwGA0eaBmVr26qEZVqEe2+uUyTPIp1vwtwCrVNzVzqolwGNGH5\n6EORWenFdcrWN+D6NA8J3bAWGyuG+ZHzPrN0pl/+wFDa5nzaXQrpACUbab0I69hngWap8MY4qKE0\nsu7HMPCkr42UTaD954EnVji4lhPhSzw2APiJEmWYSRS1sSBTj2LHKOXIYh9nim8bfl0TUaBCoffm\ndh2QojPkUCtqNilw7rE2511FkttQ8CHmU741FEo5zX4KYHVNXenmwE4ys2nqdgnsbdI7RbFA5MH6\nImy3EmyOXw7hGP1JXR6clZ8/xrB1AGljQloq7P64oSsLyUVVfzZFJrd9G1CnNfmx27XRzkdhgj+v\nTvvQV5r1dbQ/MVaplTNLQo9fDkLhI7Zp4SbmZiQ+Vq2p8sbvDpeGiQ+gktvog/2QSTqBGpwIP00E\n5JHSenWz4duVtsi3+pduaxzM/M2jM83WgOKk76zzKkIgSPA5lMdPTzhvEWic0EceD6DNSkVKqUrr\nCz96hnUEFTBXjInCT/mQv+G7x93NUKoTK9KdIwLenOSsTV91AN23V3urUoIwzkGN1dgvjexKDncx\nE+6s6ZEva1+DEo1qIcYX7Ycb9QOjpRvDd45apng2mQomJ2TWO2WX8TlPNikCEFZ5aCW0z0oq+uaw\n8OUIqVuT7yrsO8a3vUQIzvg5xSxjMldecmet846Z//QrAFrZOXaMjn+/j6yKFdH5evSlBswvzFtK\nxgkNPUju3chCUxdeA0btzzzxqNSQwwv40ZfxdS0be2yEvgpqjXFOt4qXxMf/BTW2dj0YKYYDiPnt\nJhEqdiI/ajbbm4OO/iAEw2D6qTpYz/N2WjQ4f0rQ8dCgW0AGhJqeTTh1Jky3pGfS462Xx+xMFlbY\nNnjqwY3zrbRsvkz7REl662hxtYH0ZZgi91dR/9QZgM5ItaC+Yidh7kW6Vsa5yw73DW+HpBzHTmTD\nCSHeRPjfO0kgIORWKCcpy7p+hJnbAKT6c1CZzG2+yFoqbgWvt0iwGprf9gW7CUCZJP6+Fo81dYNt\ng79c8s9mN4v7+Kz3nY/nofPpt6AUwrRCOiL+tflSo+kxTu+Jv3Y9FRLs9vDVoyMvylUXZDG6kEQR\neX/31jg7wsgPRPRN+QoaM6n+nTpo+MJAIeqGGFvoNRCpItJyMp7wbST+r5HAWQEDBBLz3VrZMBuA\n62laJ+wowoI4GupyLoxMyAlr06H0UpIdSlNifdp8k+jRm8x3SCAtAEZYw2eOaFPPT7bQ1fHdY+Y2\nMP6OEPaCAFHget5vIOFmZeaD+bf3V/VnCYTkCkanKFjr6pfetvXHPT3HLet67FQM5M18mZoNBqch\nGwF4hnacIVWE5JHJ5JkXPMMy51HtmwUCwvspmI16+H7le/S7UmfqNQT3Edx0rPuzH+3nzPHtV+Em\n9jL8IlUygzLbuunWFdI2zQOozXX9X1Kr+ecbiOJX7bKkgL7acXgDN+Ip6MlA2dXVQp2QW3SDVgzI\nfvEMb8S1nDfwzA6b3LME+idwsUOL9LV4sGyQVUUs/fk9kYsGAtnJrTiVmCsm0hav4Bssiu81PxiF\n+vHCOoD+wx/6643IStWQ0oJs7w7hWqn9HIf29msdzhgn2z4WYGfbo/6ZZuTzpnjy1CY6S3VxYm8H\n+M91/wDvgp2kxLBp8V9u3d1/9444+8bjKYCK26Un5Y2/KyIT0UY=\n`pragma protect end_protected\n", "num_lines": 284}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nKC3LkUS6ogIgjGO5TAn0Nzs889TR+SQH4qggu85MStwpXtCwvndfI3liHcD8e9YnkugkaJmGkOag\nhL9VJsK4/Q==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nK2b1yBE+1Yl6F4dcgijelpEa0U8aLmBi3OdSi3B3Bz1A1Ywd9gazWVmkJu5dH6ro3pbu23AKFhsg\nojr6SNQkJM8mKy/06t5XUFz3fXudiYcOUHMm7lrJfbrSx9gfQHo4L3/rBDCIZdrlwUUIsmRMIQQ/\n5grJJqDKqDikckziW90=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nYLJ9CLnTUWztRO3cr11axdnV+fmNzfbcwvPafQ/zz56d/3oe9mK9wqRi2t0QiFAjpriDllP6eZcE\nYOhZmFdX6rCXNdgUM7lLUPg/rEhtfBGsaUiX1jWm2loop1eIsWMl/P8b9nBOPposdlIjBlxpCL6d\n10Tw98dz7/ehpSfaM1L+e7g2qYykNHhXtLBtO9Jz90jUpxfVwGfb12W2d9XWTplFlX87Ug1MOsqZ\n9LyKjbwwCCXj/qBWB9+rbL4G5qTKguSldDBQeFeAXj2iLjWaAG5rivM1ZHQyJitQuyMStwsTDB7D\n0Ap0aGehh+4jJnGH80c/y3Zn9WpZXajMoOqx2Q==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nT+i4xGFAONCQP8fWrroASufz8hgghIjazP1/YbRORMp5jrcu+Y/htN3SRy+IZK0/6/T6p2wAuXKm\nWiS1/8A6Z5caqYdxEp70zFw61Ltk4hVieEMSInNWf7Dn3DeiuqorvJFKM4PhK14C7WidGsR54CWr\n9/UiQwIFITi61+BTGY+YyBkH0BHErk6p0pkVEpUfc/JmqU9a/Dr5m7OR/J3QSmX1F8BHWhNo+o2S\nHXT9j1ZW4vSOCo/t+piAhU3Ze6TegU8LfFN7eXGU9TEUH+PjoWlKOvagyWyuiOIqrpKCk+TN0oJU\n25Q4XqShNSMcaj4Pd2ZNBRyx3KtD9K/WHz4+mw==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nPT4411yXwhygJDAD1Y7e3nXckrAM1kjLy5ts6y1lIbXPJTgEYP6g713qyBCe2xOFOaRgTDiEDDaF\n2ZnwqeUs34bzSDroiHs56BhZhgtirJVLi9Ndy2LAiAgQfRVbTIhAlIMyke8QqkraiaWgV5r+0lci\nyWp1Kg+ui0HmS+Y/iPBhs5Gadqww5qn8pBG6HWzw05YgpZrVTQ3hAYBXuBNjXt/eAvWnPhIrsogo\npkLUTd8ciSKNTXhq18D9EmJ+k1BQN+iXWkmKoOTa4Bo1rA6/+n6YrTJ8FLM3NH0Z7B2Nk5PTh4jo\nHzecZJSN8LEs+WQHCdfJmlOoaB26wccs2VWBjg==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nORSg8Mlt7/3I4qfMbM3DaXEBe2XuDYF2aLeze2u3gIMMGQWMVGk+2iGGhGO0IOPaZUBYrcRn5oGh\n4fIdv63lvTbEn6Uu58N5OVGKCYKWAhLWxCW5eCpkwC6LEk6d9v1aTC0IYuHXB5iq74KuhRZ3ERcG\niK6K1vkWI5igXT6qaf0=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nHjC931Y64abnel/dW3gL/kqBMvWhr1yHM/m422BIwg3OUgjrcBb8jGsPzqzFJtbE2G2NMnAMmldw\ncytB9oBMNS97QBlmTUY6iR+46PVqNcEYsIDMLMKgCx82mq25B2YD9KeHTr5pzwsyC0WmGvQMOzAN\nUX8hJ3r1rYs/Jj+zuOLJV4SO37lJMHuheXhUUp/lHr77tZVlFBrqtZFePJZnJKBK7JiL6kYJjSYq\nPc7LhWRZehvfTe/vp6tlKzu/a6SOBbUH9CzOk7pSe02pQxp/9h6SMCPWkaMGeZKYGajEmw7csJpv\ny0NUdP0BchBqiX+Mvix4g7H93dyPHJc2RGNYEw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 281152)\n`pragma protect data_block\n+um4pbXSPC7/CBT9EeE8yAyGwRsYAOpZv8nY+MKwO+HWTOOcayGtj+IGsDVpoGkQL2ZGFuQ6GIVc\nDFpXYvEDE0R+qLVCIRW+YSGC/OUbiFcIwQW1FDS1XP63URX/DT9Xg7x4HCuzweTayVH4zAdc0vjk\ngBFhjvtlLTZsZ1odJH1ho2kYyQWMpNdj/ltLsSHV9Q3F2sQ0NvySi1xlHAotChBXpvF8+3ka72A0\nVq3zBdyu7BtJO+7J0Z5RKepH2yNhml5gh4eVW2sfkEORCua5iByCWMCSRkqg9RJADZbYe74mgbMt\n779ELHV2sAJPwPAwq0f12i9JX6yFTifWiA6cQ9zIkFyPr6hSKEsnFSDYlsqncAPOm7ai07HQAKuS\nxtkNHGzJouGe7SF9VyN6kjwA8sD/tuW+QctwQuzjFDtc7WYvFYRhONOwHQF1JSCrzj8Gdl7o5boS\nPgQTJ+XCZ7EXPsJzmhyIQCCX4apnejYMtypplFqL7FhS6U+oU4hTKc+f9E9JVAMKTjB+Y4fC6SD+\n32TeiEs/ioiH22tHnTL9Vamgql2kKGxv7r920MLqow72kGQkq2ZYBlDvf+ylKg3/LQUC4ERjb5Ve\neVjDSIjEWr1/egTX8rb4cDufY6M0nMWvFNPbLaaRM93w7f0KT1HxSibYOCJ8OxzUN60nJ4yMV5s9\nY5wuszMXX7vJCREAV+1eqNVp7Rh1hNAmap/JBj8DfCVU5twoKYFZAiihagfMhQBO4fG9DdYLcNuJ\nsmgvLglKsVQQfixWPReTgRLEAgo+vmbiGTCP13e0PVL4m17jOG+lp3HiRCpYZbd9Cba5PP+8s/Jg\natbaBaS326M52phYQCt/7MEZeCJJrPpt259lWnSDsC1LTroGqzv99L5aGcI37GfTCbjSSjpet0hD\nT+la8VaDJaRroz4v2AKwmx3lOGKMuq5AC476jmT1soHpTSQsIB00ad6iTYKbYX5UV8eQcBm/3KoU\n9CKH3YSfUvIISbJXjfs+nX6WjkwBy83rvG4s37rV1jVR2gqxImlaRIL7fv4xl8+bYdSn1dbpFxwx\nSCtlT9lHJf05JxgCdgbvb8rjVXW/EWbR65trAeamt3T2150N9lL1NiSCm+9wV0PD3joM2f2lfcFL\ntBk+NTgEOz2JAMfG74QRTbmvv5Do4AfFRKa+scM0zj79VPkMLt9FP87jm/igxO8LHr/kYcC33vB+\na5glhnpQltFg1NrgMxBOprarISGi2lWpSBAcwKLekRntvdqp1pgbgnfEdQ/OgesHoXrDWpnFQBAB\nqkjX2hHnV3C+N57t+lrn5Kmo5wVlFwE43dTAXM3rUJTOeOIggvLaC1koPQ1i7rAOepw2Fqyog520\nN7GKzEtRI+OO7a/VjQNyst8R2mavT+U2T5VhHBOWlO01pSLqd+e+SegNJp1/JbyR22L/2glrQDqG\niAawgbkTLuX3NYDUG/LIslH3iFj8whC5DIHWVCd6Hfocga0LZKE5av67XdDBxGoe4bBICCG5XPK6\n7URQSiZj4Bom4nq11Dr/PftFqwRmyU+RIc5cg/V9P4PSR8HlrDSKOXQjqDNNrtQsVfTaOUWsgXHG\nFg1jBVdJIJ4Hemnfscm8GtqPSv7SkyPDgi7IACWhhkQlR5npHymZQ16Ll81sOFRuGvlqKznAML6P\nmCm0YMXalei6fqGz1C4gFjjr7ZmuLTyqugTSALFCZdqt7F3fGF0bRrfLjTf1FPKBIK2UsQQWSCkD\nqTMhQtpXHHhiAb1+18xXb6xTUhEt3eZn05bmraf9Sd5GkcUy59HZSDzaAq5nCojRi866QLKjrwsz\nyejk06OwGJ2q6eZZxnBFEolaNeWcBySFp9WCLnR70gphtY0LCOw6wN/3WwrrMUBNYMvH86xLMHGX\noHnnVFfa9xud0pEqfek++QCc4BCD5ZEykd3ZWO4IJyFXGlcEYRMSJfEH//hpZMiaKTGALJCW8fVR\nacpz9+HXfbFhJYIS6EAvD2YOCb6sNQgDhiU12bCJSDm/+ceo2y2QP22yYWTKAhKZQ1g4YiXDEh33\nV+BIVAVeIY6lhAh3PyMhPpfJ7nMvbT/VdwhGTyD527wbmMzJWhYgYMf+xAIGtC2rwhAMU57PHnle\ntVZ7/m28b7Gy0ZduNVE946ST9hf8Jq3PJSrg8NZCDJanqsSf82lH1ZgqsOs99x0cJ2vRjxtKMfGS\n8wubsOnljYi72gfS5R0s4NzlEsjG9KINXzL5daOjBgj9rJSPSNMe4lchEU+uGeNFpirXy1L1c9Sz\nHOvN9CN2+eP2pic04zZ+Z0O9p4kfFyaRp4GXjUMzlUETzVfQzyMDj8GMeCcgo3kLfO/lgE26ma9f\nIH0Rl+xQLTeqC+98CIVnwYHz/mFl/K3n9XBtEZazQoGzDsnlBue+vGJSjoMI4ercbK4Fn1S0DlXq\nrTdpyz/R9diDbdfkrgVacoUjCX+RuYTHp4p0Krz5xy9Emd9lcyNaGhJEN+UvGPAm3b0QYH2o3+/8\nQVxwcP6xhfG0uRu5fI0Jrj/OVaYEx+0ATKtztlK7+HYsKg7cqJnQo0ju0l2JXu9yj9CMKP/VpdO/\ndpqKhAtZOEHNRoxnmtpJIdpEaV7wIULQyrSAMHoKkFc7rt3+LeWzFNb1hotyqtdnSp0MhMf8XaYt\nWFu7PpNG1UzdA8aQMgKOVEpOwQPeb5qheqgnVsHaEwZraRH5ahTXAG/orvObx2W0ACQisPP0rzii\nmJXbBfUOoSFUK++OKYaTo3uhmcSIn2opYhpaDR5dAZI7rHvPetaejmUqhs/AL0FvhmvgXkzfBdnc\ncV7bgh/rfddfF67ddy4cleyk6LhSIUBVOcVNgqge6yVV8GkyqXF83ISfzAsTBbvSt7evDsd7mGae\nYdpYeyQA2xcRaIByGCpzYRsfP3CPEHNoxpKkQtJEk1V6+Dw482nRgrQbxScQoK9s67+EkML4gqza\nmdu1lwm50IQQBQfwQqVTzHiHEiGpuJI3+jRf9J6PYVr+ggbAA8EufONiUryoORQriX6z7d7DLIoO\n+xXRsZZk3hC/vFM2GrKMnoC51YhHF/2rocChNXLIFp64V/1b2spz9T4woIy8idps1iFwQPSQkwvt\nRh+QXg68hUwNCePfmNAdo76j8zwRfLMj+VbuCViN33hIxF5Tf+iEeG1cm3pDyrj/c0G8DSkApnqq\ndIFxVtDHAlKKef07F17igx26Qy0LrszKiF97ZFfi0ncP0AV0KzA1s24Fs4sdHnAf9TEqrt7NfMiU\nq9+gqgAzBSs1l8bQQbv7Wu59xCudIbuEuvBAWBrBjaIMPeFHCq0pG1yc+Jkx2XQFyZESAPHJJS/q\nL0oBzQ9ZWiqwYYbMR6diEp9qSS6+D3i66V0E21mQoiNbFYIviwp1eKABESPMElyRvQmojuhrKpYv\n/aGMV+8INB035KRGwR4ZXaJ40OdEfZDSAsPDcOfunILAq8W+fu0AEUFexOzRRfzYT9+dODtDl8N8\nd16TgTPLksZKkGVjUtF5Uxvhh3rUC6ZUPKI+Khs07B/l3lbCjUmlGrmMX0fTN7z0+YlTM8xnCoxO\n5xqiuFTQHo3qAQjbkZiGdvFVjVKMLUf7xnRtRvUq+V1WQdkQb3pIDimd4yCegVdM4wJxSJmzfnQS\nc3AWq0U5I/fdmlsiqxL+1AGm+ao0Pig9Pa1uYmCarH/jq8XJF65ODOAbD0UY0FKWoBmct1b1c6OL\ndwL4RrdScIScwHyMNHZMRkn0kwLUnZZNP6K9AoJnmJmK1pg8Kv27T8jX7v6nD7wpdljmDcot9B/y\nbvt2OTP8Ykg12jNHHTIWXU/7LOqBGZ/jridX3nrpmblhiT5H6jeVyCDufYSMSbJLmgCDaTmyx+aI\nKctpwsPYXrHRmsF412GHHhXERlNq8HsLUee8YfhH2Je/uu7emdcd8Tm5NL117jxmbR0QeujfLO87\nZcjPN7RzNeqCz8rAtM5hCqPclmQBlFAa88e8qUww7QrEiX++R+7VIwiqebwNmqc+ETuU0QmhFmX8\nvtprm419Sp/ShTgFZ44TmGiYTC3qergd50O86m4bLcWA5CDLQ3hg8S3umyRk0rYcueMpHIbCbGAw\nxiAJfOVBy8wBZnLo4uHfgUDzIUp+4rDIsUz5ZJFt89x9o8FJgDtBEx40Ls7j1VyUWyXVMfFeJjIH\np5kVcr84G/daZxxlJRn5OSlwbdhyCbo798YJzuJH/UVVZybwowgl2zILPgWsHonpLwRsq91QOyJ9\nzMPfWO314CDcIslNHZxqkfUrHNGoHU9gi2xJCdJqCMdyTRG8fBibZuVLskgY4+B6F9YfRZbunD6j\ntf0itYgmy3EEPoNn+hl0eQKRXvyDWO78XaD+WRsA4BE2zYMZyNFyIYrbLNEkBDRp+S5VSQYli511\nCvAQAR4/BPYehGl8NLDzjXXxkYYHmKhPO292BSaV6OAm+ea88D2nHbF3KAQ+envijjtnQINlSO3v\nCo249ounazxHCauh+Rwd1m48MPgA1duN6MYI0rnMh35Ws1hXn19zJnepoa/vNNv4myDJGwtttx6Z\nDNZjlW+LylNZ6jJ0H1SvsvkYBxlAwQ4y3S5pm3B0bnDcV5j6optwosyk1wl2crBMLftdpyC4GyT6\n5FGnrwE9flP0ZZxbY243WN2J0THC9jRvpwpSA2kO/Mjv1sJRHvMkWoZRB1dWVYJDtIwIgmmAx7n6\ngBhDcHlJ9O6DGe9AtCeg1mMVoX5pcGWpkUI3W6cvF8VH3F2u3VXOhTyAosiNtirH5by7qWi9NOmL\nmXE2Qm1o2ON1ZYLNQ0ogVQcKXyCf8iesBFjS3wFRCgqLurb7bSZRg/XKg+mXLSanGid3twAOGP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zehj0LPBaUl2WpJM3RbgkOtBxEUZls6kvx3p0407QofFT5OxeYyCBvepiX9WZ6mYeucdmDAy\nqlQZ3IqOMJtQo8DpjFkRIfN1C/eLTeC1oBQwtd6nAI3GzqAoF0xxo8Y4dzXk7+rC2AWY88GGvUON\nq9S/iSqGpq7u5uvKQoZ0yqZuvmiEJPx5jjRPQP0iIlDQPe3sfrf/5Jqw4b3DI0PQcLbhAn5vhCR/\nik2TpFfWbntXGTGl76a8ObTJQR6d0elyPRUbWGlRn2PClPJlSGfZJniua9Y/GbimxxYI835ksIoL\nas3Dc6ubwKrFljUiHazdrnfTOk21ibVjJTKc9U4iYwqiEPYO247OzBKqU0nq3BH6UnJa2EwYVHnk\neAH7NrHwNv8nTX1AthJoxRXRa+NBgu5oB1dC2IbGN+o6Vqtj4P3SxskuC2kBC89NBoOsbGVJfmXZ\nTryWMSS5VKj8+Hx0Ws0AICSZPGUEtfRB2n8gMLiy6NZCRAn5o5bk5HI9n1wBDo4dS6rU5BTvV19f\nCjMq2/QcnCl5FS1Z6n+GWPCe04OvMzSpcOv2Y8UhNywjHLaBSXxZEL0ND74g9cSpDS4QZAeCDmiX\n8+UzPeYV9mIWAhFIuGQb+deYueotMrvRdOu9Anq3xG8/M8dtnknRj6PY//OIf6EDIb1c6aCF994j\nuBrntJTBz9fTUf9s26HVn0DPLP9Q2CgfLEfh9mHfdNMaRE1sNnNk/8uxMREof4ULF2QBkRX7/pZc\nPJFtYUPqCZcFMmTofU8ZsTg5H6R6LvRQK7CzqbGHyCn3AdKQ7q75bk0eMG1qS7+nHt4gG9j4zo0I\nYMKZfDzXmUU02TK37fB3NgIY9EE1O1gdohNXBEENDHLsKModlByIsBKN+nD7yMA1Z+u0PruGJdyH\ne0ERY2Hb2Fa6eo7IWh/1gnA9Su4r+M85igsSee4FdXk6rOGMIwwZHj+eQmwtoMtZax30NT713Ay6\ndptjuA7JWJAXnscnefxzaAW1aTtsREUKUYJGnVIX4HTXK/qAwHrAIKGp82eXBVAw2DRCTX6hCIeH\n74CCGOGhl+fvbsJJl74z0qONeuwLRGLj/qiW77RjIL5vNkbTWx5QJXq4BVWDGb4jc685FcEvu9wt\nXHeQZSwaodN7CrZ7hySjh6Lf6N6NQT2VvDsAOOJ/PZmmBhXlV8baWou876PEmkyXWgJsVDGvwHao\nQ1M03naOmbNvqZwUudaVr6URp2DdfwHQrRnMBoAc0pcMkt7SDtrtJZl9miEb/OlHXSoIby7Qxzfr\n+hxtKr18JXZFRgNzHf9yA2QLmgjiN+MXC3un8rvTZNAEUJdksNOkVtC0FsfKxB9I1Mo9VLrU5nmg\n6B2M9InH+gLjfvvYJs9/lg5r7ayaUOOp2bOpMnsJHVeYiTHyL5suuZi9Xpz2vQIdBCjmhebZTjLB\njtcTRmJWMqbUGgmpIURIm0ahfBk6JYSSz3iVC933Y/u6LLXUrk3TY8pvELmmo9HLT6RMq9LMasbI\nxo0I/l5opQ0RKOLBBQe1obcLvky7QyvPJThkm5txudv7IOKAhnXhgtkJU7Yy7QDdo/STlScNu6L6\n70+nB31lyvgzuKOB/s4QEyYNcJlvjIMo8OdP7zREyhmKbYIW9yiPOuI1D0ODnSVNlvmpxnGwCK3U\nLbPBJ084nSvRF09qQZHayncmjNQojAUbX6EaahgsGycO4HlzLggdEW+qJXNHGgwwSNswTN8vjSWe\nx/euktbkwv3ElyzdXvPLLwOWo0D+f8zlbQI9/DdkaGgLsNLIbPTcAZMQ3JJXsdbvNJ9nsOMh4pcA\n7cTJgsv+lz+2cBAg4HmzY/6lvzfF9MRpzFyPp+wJGIK0uLSb5tRvN+ppXiRpcuFfkpHkfluYEQ08\nQQhISHo4vVpSa/xt6ro/0IdQz9ibx96GWqTuIJ3pnpZwtlqCt9iwG5iEpmIKoSVIWe4Kb8/p/jUe\noQwmcP2BJmW+1yIRjpONFOhIT8hQIzaHBsHw/+8vRAxNxksQjli3/PNJQv/HqG3srp0U62Qk617C\nZey8zG2S8xjfT/i9Plfg2i1NGIYPlm9noav/27YLRvQBxUUzMj46D8DjMs/PIWSvSO851QNLfAr6\n/ACZE3/GyjyMkBofZzSs1VJV7mYRHHVYi00sMIJ/43jSEUABMNZfZVEXKgX9dCz4zk1tHgyJpedX\n+dJL+uEzMHQ8rRIDt6XF5ClEWgT0a3zZ9C8lCaMEDIX9LSzjpFDSaaR4JRWOsP6ZYQGX94uwkmgz\nm6kpUN/4mOs04JIlGAYNas4NqsFHUcbvtEX0LLnLAyxi5W0FnwTO9XpOxjzB2rY5kyffh2W2d305\nqaJ/Me7bghx95FeiZSlY8zF59PJ4LNj12+Ytyw2GvBQruYGBAnQk9zkxUQ/6Os1QubDdnzmtICO/\npF/vrL7agFQtIFvT0nCBqH72wagnMY+NQkwJKhI7rbL9tmW2EwCX/herlO+yzS0W8Pwe7Fzm7hBc\nNAYmgq8zk+ZtQ9pWC0HQT2ryOsbJyWfApYVDwdZgDGKdIMAJplqbO2mLnwCQf+vJk5DDGiVRqz2g\npALue6rEf0cJb3OgIw9/vbEIqYKXtk/RW3tdqdICk/cVmyQZqsyO6+1F4nJuTwd2I5I8TWAhe2Hw\n5GY1ka1cL36D2aZ+LjFRSYDJI9mIu/Is8Kr5+D9zM/Y0LSQ8l1u1wF6Hi5FPHuhUUjVjBYnDqnpX\n6POc6awab8thKZOExehZ+6vllyBV5GbqdHe260mQ9S3dgC1yQxkwuciz1n7WXB5a+HoxKzvFsacj\n2N7eyHIDEXOp70UxZG7jAWqv1D1lZcCl6uB48Q0hp7m/A7sOqDnVKKzmAJCGQqKZph1bx0tYl1pp\naD5WvG93oIJvETcVvN9jgs/OrUrY9/vv1EfAgNfE+hwmmKcnnq+PPQ1jbCeLduBOdTHV1dtsscbl\nPfhqk+CIRd9iVRXIiN1aTPCNjYnQHtJqEjJvBtYG5c/0hWZ3u/G7hGppDNWG8kVw+fnLrb8Af8IG\n5T8LULoSWqBEWNsrFzzn3zpbabfKgQuP/cBcAYuoCgg2SKKmcQjrFKKdwYXyRCS9MBKCgjLQuky5\nMz7Y6H1VvPnljJlItM+Y+GGax3D2MS8J6UECwpDiy9OOsUXZwUabYz+MrMDqYOCFYOHvTr2u2QYk\n3eD3XmimivORgBWhJRVhU+Rggeh7sUuNfLG1rkkGfSNeEkE4u6fnNyWHSX51Z7eYH2aEYWAEWx2U\n8UVk7xH9SntzZQIBNyqFMJitUqaUwTMlG5wE5gIDRB0aoLsVifBpim8viugBRm7czpK+SlpQ5erO\nrgF4kjA8juQ6kSvs6sMQAwypxFiArqSEuojExJXUdcmGfcFrybn38Ff9c52JJI2LhlT793xq5OLF\nre4aKFLPhI34cW+rjavl2qrDbOBsGIqTeTtxlxmL64Oo56W+kneAKsYng3TaoPlyMR2Y4W5LCofq\nMCalf6KMF0MGMWyBiw/vxhn9SZ4JNk++9MC6nVzQ+OmM6F9oxIX4mdvoanxb8quaJxPMoRp/mzZp\nM1OuTmX6/4YIVdzBja+SHHvwqbfSvZuR4eOMmX0rl+LwNjBxRgCUx0ObSlrvO6+zpybVs92ff3Nu\ncFmXQZVJjWD0zaFxLdTMTb4pFEWIwKzH1KtlzYSZxJkmnrG56q+g7TAkozvHNifa8E+qMU+EUfpA\nvQxWnMvZRImsq6EX1A6Z3AON8sG7yvslPHZ2LRvtRtindZxdir0mAcKSiD6psnNMnFZEZrRsAOqV\nqc+hgC9Iw/BSFLKBCF5SutatSQ3oSAgUjbnlZOc1cJbpJo7xQ6Z6phT2vR2dqC9+9gJrAEi4jAPu\nkNC1WTDw/LmM4LJmksMhGr09vkzFwri7xFTrFlRhU/7rPcC1WKmP1GKf/zn8ZkbjB2nlKwtLMj2k\nCrzkPUlR9mY6Zj1oTdPHeoXtPGMu6psdcWo2zKGJQB8vsYVRQPoHx7D7HALr6OsfwOvkyva8i0Zy\nDxhFz+3PenoM7+Xk0P0041CcwQ5EQSYP298VdFZsOtssYI4pSsDjotoi6oQKUkts3N7LRacJzIZX\nyjYNSrqZRUVfTzDxb8mj0cCVDOC7r+8lFLrnEHzWWUrdecFI+xkQ7oIr9IvA8yFP5PJZBsWEtg5M\nLqCtEDfMRLVUwFGIrcPoNfcwOPBHeZpd9lGzdQYaH6xRsluE/L8SYsMnWok5WumBAXy3Vmx5zdxq\n1i+Zg7ZyY6tbb1ualseTZjX0Q/QSB/D8G6DvR78qH4cPKZFaCBlCJDtD+V8MS9E7UjvVurrap63r\nI2RwS7YmeQ8hVXxfWi4x6ZQa7tOiMrlqoi4kwqlsVvOLf85Mmkwdw5+N8WAdIjZ8MjmfUcv0KBNB\nOcP1gDVKcrmy1hZ2BI/h5B3gAzxY+AYQ0w9PquQT3aS/UkP5w0tsskw0OvLeqBLBikEwarnrDHt4\nIA5AnH+C3PtRYHUvSTsRkvb4D6x796WOPdrcMyg3LvpECQDicvJkaiseAgT/OnujVrMbt+qSHpFZ\nIDUG6ubKltPL53FoirAEmgMOTBERQ79ELxb5w154vhGQEZMr/rjW3eFML02IcQAPLP/KJuellCBE\nR6FfWTFacFUQKWVnwWG4RIu5RQ3ARkE5EsR8jvOkcwscJwcQiU7HTwN+cgm+Sp59ofplwvdnQW+m\ns3csSedmJuVrCrkNQPyXKB9jxvMDs3ZFiOKS05nO41XMVBbanm5pCALtgynqFsRaBAc5qioocBRO\nKbOzU2vebwRQyaJe3okv9spoDHV3K1MTGOvnbQEID2gkw3dk72476YWtzmStTaFfDRJgB533lKgU\nU75ltkT5aJPjgTkI65ToYYNqE2Hm38ssPP7DQ8IJpunS42zBVEzvhb6NlvzDvMfaI/Yoq/1a1PK0\nLSd4LNarOahrukuwe2CpfcSFoJl9STjPc+sQiFFYEqYkq756VSb/yuCkr5FPx0orvWfL3Q6hEgD3\ng9KW+s4JS4++V9m2abJQvCMSpq+oLHaqUqipo4L8XzgiQDewW5L1Pt/GSlCa7KZukrvJI6heo18T\nKeA988+MlLE/enVsqA8R3k31BII8rxnkBlnrm/3mqbH8nEzBQQPx93tDa4yc95xNjCNFVEOy8JEA\nbKodn63siviMSpvMzxqDci17JnGAin5aEIILSj6lMt0DwJjyjhlrPxthikTcxrwJBS0PEkUVbAk6\nn65Q2oRu04IxQABLffz5/S5uugS3F89Ypj9wZrxox+1bzKsxBhypNTnVTeDi3PtcvyoekSgjgzHw\ny8av9YOIbTPsDGCWzMivx6PrVAqGAzrYsXEzK6AtlfStFP5F9HO31XXTq6vIT5X3vdIMxYBBQyYs\ndw9F7rTIfpPhIUgJyiKM7TZaYXDdaAhYIvzWdiGWMP/X/tOzjfbhCoEygzbPqsbFbKOHCDRwQ7im\nEp49e5wCXGwg7mSK1dEU8evazd1Fgw36SIdvEYUz0h96HcDtZQU13NSIjMmj3Xh+PSKhmdIUgaPl\nJFoizD7y2u3BjN9te48T3g5Lbv8CoQA2vk2ETEjLjOPcbLjjE56gugpkhHqIaVnZw8IiseaJEeoz\nnxeoEvI6HkMKgfvc8Tn2Oe6C1Xdu0rbnDeGxVAO/CkvPKPmqpN4NnijLLUxqcCuk6DIBHlB+Sdq2\ndOYRg/hhvCQGTqN1DmIrMA8q+WK2Hs0mSXdCRmSaZ8Vc2cLtbVlAd5ek9QijLgVV/WbiEa6kJ2HH\n3VzZGjkx9wfMTl1twEG31tltyfQbKL3Y8TERtRXQBn4z231/jpf7dvFwn19nT0cYSQ2j3yrkY/M4\n9A6kr6GnuIndecO5u1/sh5nGJpA8Ok9y2GGVLK/koQPLUwI4jNyTX3PlUqJnNB/ygxEXgh9xQ5uC\nx2ZLUlCyxg5YFlpxieRmudts7G2MUq/XHWgSdvBexh395W4p/QZcOfFAVFp6ZxSzXLlvyBibqKXw\npRMUTguwB9jrQycduqNjo18JBCIpoqoMWlWfo0n/XtmvivfUC5X1IoRwByu8pvgfSnqV4MrQZoka\n/8xGutX80vD+MSlIaEFYXYd4aGfEHPx6eJ704ZhxkmM1M3i0lcYncPZMu/msZD3GuJ2z+/Cj4YTc\nRWqSRj0mkgURHzWJ0vZYOuYDpcu9YEYz22E8zaXGY1QW8Z1XWWRfiLIAn+qIXI5wUR4WFLg2QEe+\nbUtD8OU0qPje3qE4V7sDkRuxV5FmICloS7fblMqEFjLuwTEbGu1lVq3Lp/1PF9Q62/eHD7ex/9MX\ndfY2gQJAP262PAAMl/7ffyzZVBNkGkEZZZWgWpZELOzf2gCxCo07EA8p8O8LWzHMWbKzGnAJMqDJ\n8e4IUF9qp/noRg/Vo6rchlD0VFJmB1Lmm0oyxppH2oVSbswJIwiqgdZhtL/A++4XkkC95V0G9B59\n2Q2SWfDPnCWM3jvh3BWa2QWXP/5FYqp3jjKksYIOrr+YZVEGfxtdyic3vzbKvu1Oq9j4qeI2uvaC\n1WmBP5LXDVKJkGLdzJhBVc0OMGjfc/gtg9BqAzQPNafw713n8BkkilGkKl/UM7KVdZn5AnGQmwuq\nlVRVezt5susmbNryhn35A8ZO4xOeURkZxTexU2vLbPMpCQlHrwzIwqCkijw5dce1dMmNT4oEljiB\nBDD2I/KDxz1nSKsXYTSHoOADGST0vIL8oxKI8orLUVOzprbJXDubvByeG/ktCji7ekVVre2GOrHY\n5EbaPhpXy9HMQdMJyahjo8i+qrllnoOYxh1O6W5CwJ1rMV66s6d3qeoDz6eyDNoHRmOrSbjbRRp9\nP7v2dpbO1MH7GE/KLrRwaOH4cQv83vFFjUEr0UQkzRAK2nzAKAfser28K5/XinukYQVKYNQw58+4\ncPRrL/JdQZvetSposQkKQPhqrO85xvQWN7g2I8yD0oYTz2keLB8LrYpwf7xA+3/IdSOAj+bXbMiT\nwiumSlcVOeognGwoSNkbZX4GkxlPiVtFo73oKwwHoL3FW+58PUQCZgkNRfg6nlaaOsH79ODFOWKh\nWlbEYhIdMPbvvm9mheuUeS1SgYoqLAnVQu8Hbk8ywesumARTHZ6z8ZQEaJB6dkzFHxT2/pt/EEHH\nM+OokA8g+gynf71Q18WDveRl3HTG7EMQsq0odI3QpinNYrFIeO8dOEEn+Ei+i9lLjyBHD+RLs/y4\nDZcrFjipH6SKaeLCGJkKIcqD09umOy8FsFnk7cwRbeQk35qUuDdEO6Nuj3Ha0wv/0S8JkB5+pKXo\nyxMRxy+eUmbGCGTWwsENA8H41rbbKBqY7knuIg2lLKOmbLLw9X7Ndx2utZQY6ECQNps3Otlj+jsF\nspqloYe1MWVlomQphFItqG51CgBAwaHQwitCcm5OP8EYyZIcS4q8b3VFQ2SS53JCcGcxV4yBEdbx\nRojDt4NfDkrPFVlwbts0Wh4fpWQJ158pPg4C60zI1q67EwstJ51z/i1XN2/JNOCDuCrbr5RvjWIY\nChw+vO3r6p19eap7j6aKq4P6OxAjbuz/D8rjtj0w+t4fpj/ofd0OBnB8Fcol42VD2mlUM1SQiM6F\nF5eQeyevaBpVIeIDYt4DiYkpfRvy2QcaHDnHBVCymb+rkwjIMfpJzh1IBeB8SBhF2NMLPAqAyWW/\nTcLWPmxKVO2tHalDPkkBzQcKpqUkFnR4mCoT3oNjwfrlMvqiBQdOn+TaLi6sp3ItyHNTvuh6daLE\n1kOr47LzbRqtFtdtDDp2XES8tOdtz356WnW9XD49QKp4ixtT6UPzve6oh2lKG6dowIbSoF6vdqyb\ngFMK62MGlSvpbPWkR4E+GBoQco+ry5lrdCNSyUrQ7ro66m6DgNq7CA736RabcEeUKPyOvHdgspYi\nSDWMr8VTenu0dQ5eP3ttkJD2h+Z8/1OxQP6bsTliEcWGB57CIVN3azqSLgdPGH2Z3lnXbQhDChKL\nlTg2keXgE9yTtVWHy/TOV0gWiGaZbSRvSJBbLYYnDSCldER1ph9inWLOzP4xht/TM6uPMbrRQ4e5\nPytvRMA7S0F3syh4CDYmLTvqh+ma8e6fQr8i/qXP761v6L75mIOe5qNDPDNuZfVqaBEyKPXVNX6V\nj0e6J8atl92LRWBr8W6SbFhC8OrUjheT5JhyZ1Fn2R7c7tAYxfbdp4gFEaQtsNmF38xy9HnAlH7h\nWLYh2BzkP7jvHPHX/9oKAC/M8I5IjTE6kq1PclhTS/uumIfPoSvZpyMEoEget9UtACxgrjJ905Oy\n4SFIa120ZPFsXxHvAlhiab7igay+6LUC8W+D/Tk4MTQCBlGpz4NDKCAbFGzHuHSjSFP+ojeaCjF0\n5yUd4vnFF6WMOwk27Ju6t0wPfuZO0XO7OYUZCjhsVNvMc8hn0OFJnLcYJvFx8STs2kyYgTyoNFR6\nKnYEKQQeaqOGY9UhdqV8pCNnkQX64PaGMrL47w5+fi9WOFG9w5GkQY3TJRcxpj54WAgJXthFq1GZ\nrJVCE+SBa0SUuI5dYUiVjl4AccyQZbBtr2+64KifR/QqaXQc97K82gSWUeBqtBZuwekuhEb8+TwN\n/QlNK9QmfBsfZIKzuYST2r318eWZWogq4IPIak2shRAfj1UVtNSjed0C443On4XdXLp/OfChL5Dj\nyxNl3KajZN2YtyXvmqDe/GEzwV72NSlYrUKwSIKlkIK08Xxq19MDi/TJoT3NqBYVD2Nd9mPJw6nr\nkozRlOny/Bq2IAIa/ojub0a3TTtUp3fwPvVd1tAXubM5WnuJN6/WJP26N52T7MPeULu+Vb5zjiTo\n+06odaxs49HnQj92qSC+Y8TWM8egFOcbJ0osAFLpVHxyyGkxJ0VyRds5v+pG2ZG7Zfclc4203arr\ne72ww7CJ0rTocdseHEGne4uNA5C1LqFpPg0H91evd5xW6PKt9VSJVBJmUkWs7atj8qmjKknBIR+b\nxYt2ITDBNGJxs/7We1hAUxW716mcwoq8YIauIb3/tKqRePlAoAUK3S8Fdl/VhAx+tBeLb+ghbvv2\nrY2JCG4iDVx1WRHx1yuOQM29a3iFjF4e/8S46Vmqmct1M3WCJo8D1ErdF+MimEBUMPVAxiPsF152\nMbPuHNujsolIHTAr1Cxrh0EIjWOvthn1GBBw+ctUI6RVEYYXFtuBkHp4Bi1ZLWc06Ta4rCve3Tcn\nAn0z6xvw60L5fk5XCJZRg1M2QF/yf0Q5njQdeNtPbkU2u0KRqG7+n8L20sfLg7p+c5rIQOmwmyH0\ngabO/AICgFmJcDv7U5GpY4NuQDa/ey2trqMKKxONNqW4D/+sA7b3pmFaL+qMniuq3MPpsZcOI0Ol\nPLiTEJTxpHp79VJD8FrO4cr+mcY6Eia8QNIF26tYrI17c5hUItuuBIW8a7KSxLIIsNaP6V2DAS/H\nstfOEW5YpXCoQ3VySYm2q9pAEFpptnCkuL5LcBruO2dK1BfHa2RD6N/HvyGYmhkWhoYKDNBla8Rr\nCMLqCPskjYj+v6aONi797YXr4lBVQKYdrvN72NvEbwibfPSh4ZV+xrwGidKJUYb9hlVWm4dGnHJp\nYp5QtfnTOOP49JM9PMQtEZYv5/b3sFmtTYeFV8qjQn109NaiPOGH8TlHnYs77QKJHx1HbTsEDY1A\nQgf59e8fJn24WCd1TH8aqoQR4utYrFt+nSGPbqgCPR7YHVmCasIZnv750r9EBTG05+E3qIrBM54d\nhVZ2UE5nFONE509dxNVlCtniFd2NOk6FOUIu0nlsjsudVbZL25TRntoIvDxUCvsooaSLxZFGIKjc\nSQh7YmP/hNfeLW4jgSDoJovultkbxUQfSIexGZyJpIVek0liBFbUKLkY6iL891MLQcn2G/lfVbIf\n4R65Nq2dYVhQsiYY0hHLi86RpLg+ZyOm4HDrqkCU67NSt12pat15XbjdG8oxawUyv7VC+v/JAF20\nkvm7WJpnzU2whRr/zXB7wds/Bt/seMXOOz7XFOXjrEzuisvKuMzX765JDS8nvwt3uj0RsY8K7fGd\nR+EPvaDMQwiE/L23IPONviWZluZAJCrESq2EuObspUTmaFVaFy75mQgObj4cpPnfzUDY6WO9g68a\n7+yXE0ob5YOCxsNCbMMCuhmhwRT1+zkQMPvXSjl8viBP+XYyTY570NP7FDJFoLKi3ZkUdMx9hFCs\nA+k9IiuTOihC7RGH0xhLutikXxgk3+zPnqnbheKcJpszYBvPnauS4+Tdfs81QIltiQRclmvVieXi\nM24XhHRG6KqoeKNvgs7kiX1WU5f1D7M77OZ/g0n4rNvCjnAZhwwPjRgEWtOwVwlCXuUzNwFNYddN\nZXdD57OTa+s4O55uwQeuU2RYQToRifv0lUGSLdEYfy/Dxs3iF5CB45olcyxrqYxafiojgX0mSocO\nb7wreijS4TXTn6gFnrMRSCVg069yeCagstFC3OLm85a3pMSyXitLpY7YC0/eNqoOpa9SjoH5Oc4H\nUO5BCp71C3od27P/kRBYOdJF4Qh6gkeueVW6ykIanE8pnjNvxhudIl/pAoW2GmRO12ozVF+nc1Ua\nHq38E70JZH1Dy2Mg7sklPdEpDwV/VTfkxmxI2ZwpFD8z03122MxDptq8uNSqrXGsocr7CBs7vf3g\nkBPqNZ5Pp4KnHx/6UWS0eq9Qbe07yLENi8kLj4P3MZD8TnVmruOClVQZfDNQp1Hn2+FljdcbENzp\nuhNJ24jEhTZg/lTpZ3m7erlcUxF9a4EqpjWjX7KqdeuMfWoB+TN0pTs/0iLrgyP7F+I1Zlw262kK\n82muHRH9C0p21QC4GL3SUvD998B2nFqSTKMNSZnW2snkT32q+Cl7/+lUkU4AmR3uuRw5/I6V1k0B\nqZK+6Vfm8GohTeqOG6VYsFN9RgtOfe3dclk5gWSvne1lQ3My/neij2/zuwqAVQaZE8IA2qddUl+h\ncnAWlXa2/nvmclDFasQ+RwUJsbDvONYLRKijkJvS0QXwG7O+WxDv82BVpSGb0ZgvjeqRP9gcQ+tY\npIAcgmTMpQY2lUVoyQp/ljtls3/B0PN30payN6XCNwQ7IXsMmKkhb8UM/rDJVWiB19MjvdWcJnWh\nCpj/g+lgr5UNfjAhZ2pB3jmoXcEgoXA2ZWiraQgelJxTU5ueFAmpXfOp6H4vlAPsWhlMvg8R39Fg\n0QWJ02f8zRUTcxptV03j7Nkn4n7ls71OM8mDphmqXpkEYxmHmhh4oWMaJq9Yu2/5XmWBVw5JJ47u\nowQx7ufQiZ9HgvaHv5iGAG/g3Va7+CLdLeQSoasM3AmQHzv1KT8E32w7letyasvZXH7HC6vvnTMl\nQ4B8aSDQzUFQb/OQkwcSLeGaLNYLEucPVos88TwRA8VecSNmkoPT/gAFHXMCp1f92ilKVDTrupjT\nYEeJWOIPMbXWwql6b6Q8mr9TFWBFZQiNvYmviyJzJZekWvrhgS5YjUTq1XJlWEQFU8VDjneneThF\nj6ZqMwEp9eGj46XaEt0zdbuCaoWhk/5TREO4a1VOxkzetnwSHCaERTSC3cBUSLRFTsBgvCF13IhB\n/GFZP0rlmhkJaNQ7s2QCcJCYGbJcZObCHbLOW0wXvoWlJqXPTKMBBh2UTGmILBQHsAGDgNiytuTP\nYXrKbXij7Kt4aCUM8C0zmNEI1V2zmVkhD2dqItotbE9a5ZaVNIHh9WZ3tqG/8+VcoE6D0kbFAPm6\n6k3a2BxJMWwZ+/stekAvv//GBOzdKXunHFOOMwadevvOuY2ArIy7peKRQ7SFTslPIhyXjJGUrwKl\ng5eqJ19dO1I+3nWIbCuaT4DNQxeps3L84hmgh20qx4zC3eSNi/zzPWX90aZZufMMmKtgoaWVpZZv\nuIoMryjUA9hJaZixxaC8xI7LjSYjWWYwWQ0wXETqTLiBSV25oru28NTlLIHMNKO/U+59o7wocTOz\ntYmzoY+f27MCXewpal1YatUn0a0oET+to5K1DjiDCPHHcMyisaSjj0l+GVFinNi0AJeU2gIMrVTV\nxWAszRVHOsZFGrQ5NqO+jswR4OR7uSIJ65DXARbas7PFiWLiyCLqsspoJW0RV0+d01mW5GXJMAiA\nlin8jKu/ZIa1L2M5R9eoxppUAQSZrOQ5bcaObmtGSDvZjzRgqHl1zJVnroLaOC6kuGs3QT4ndOHV\n/HOVFdzFBX3y7ybGPmIuBwZrJiFmM/B8h7pzkt9Kv+rXz7oHB8dckU/ls5IALnKugMGDghiT2zoH\njkGugRJNwJ/nMjhPGS7j9uyUjZd+LY/dS2SaqSRX92NQWLLw7TrbTHl6T9QHHpSCcnEuY3gKwtjw\n9Yjm//TKEv2tnyyiKLuvyIgGb2ZqnsRzOGb5ImnCVgOzGnPid+8MDkkJTDwMiLJL2895VGjxMofN\nnAOiRpvxU5SnOl49mMjGKjdHxWlcFj9dcvDbGDtWTzluGL2dV9c+LHS5dX29a26N0doFVBAjU1uw\nx0hfVfFb6GaUkQRBNSz3JoE8sFTl8+aq+ZbYBIWbyeOs8EMhWlCyAbAFENoU4Djd0jwf/C/IQ4DT\n6Cidtxf0v8B1IDY8McLgtQyggRy7uXAJ9KZDFaq17EUVuJxjKt/jk3d3W4ObXlalkz6jgcAFoCT3\nXTKxBPVEsnJjswv4mpzrus8s5atkf5SESn+CUjOX++VynH744163WJqEP/1jeunFg0Te9lOCMrC/\nV1q5nsek6EOCnBv1Zv/JKd+TRFZ1s4dvUWOXyAcaObsA/xfpErZv6fvmbX1ju987kO+7ZacxvKE5\nNRKDZ6uTi4otC+wm8LVW5AJwBjNKU96Gq7wyjYrn6XismzJon5QiZURSCORu3ZwiIxF6ei8E7cJs\nO9KL/+Qqd6tF6BlpuxAb3WyOE9lG2vZneRCoY3ZNf+eQKMr86LiT1x79xhUOx+dmKKliT/voaTjN\nJMvO9WU3u8kkF6VT7bXM8GxM8xKl0znGIrXtJUgBgZrVFyFND02P9ClDaGMOe4T6/DYPEbqXMLl3\n8S4kZAQTKBPqVO+hSm4Lj0Fqo6uC3uIbPW3J4XelNi+gjcJ04OFmXvfsR/3bgGEHI/1aI7thKnut\nFZMyzLGBeyLUlU6Zcmoh+yUUvCLEokpYGiIR0LULtOp9fj7OPzVvBRmH05i5lprdbtvMicjp9PI2\nqFTfJfUVVQyd4fRKEG8zt/dpj2jOiDQj0tRvBGIyEBKIxk8QNTcANnOrB+aLNg/LWslyRdeEOTFJ\nPaRYz8GdeVlZdOkKfr94CL/pHmvdi/1T2zrCJfnVWXTprzjT1om1WkunRUllzXzznANqLipQvk27\nPxlGA0hbg7H/egZ/rZAi6EzrJ1pVgSqBWRPLCEk3T6mSbtqXLNdiMhg4LMEjhKGG0tXMnaWf+y4j\nTVpOTvNI5I+k7WejL8gLDa8ARlhhHQzSSKJJrDVeAtD2hTdFbypP32///fIpAVrkrMtiIOtjbTgv\nDt2gXSXVpICUmF56mZ4EQaZbI3LTydvgbqtB8UMHo8MXwfL1uhCOFZJJSBba/KWQ3Ima1XswSVBE\nXmhPkrZ4dbo08BejphyeF05ZfsG08yrMHvNK+AEL9Spr8m75nZqeIRfYnLZwNRCXcG8cHu5gWD58\nFAKNYs1evpQgFTIAfMhVhtOMcM30nwrdE9wQfxvbVpR+UH7sGrpo4KnpBe58d2LS9SsPfANEFsxs\n0Sn0QC6stDPMUf5HBdjCOJs3IovkFJgoxaE5yoZOK8LggD1jd398yMqlHKDO3/1xZa5gxvIgIFBg\n1qkZarQiRPQNuYd7NhinKinqOygUiRMRvsADwuQ9B59lvxTd93tW+iptO5rdzuk/3WBgl/MaJvCA\nhtcadod3h1/QFl/DZR7PQPb/CdnqYruC234sMVuK+ZiQDE71BCffgbSE4NoPDV9V/uAFm16E0bcR\nl4CJZ1XJgiCmbkGNjTUKv+9AsAAVRORjtP4RDOn8wckOP+YUyzn8P5c4Z0Cp5FOb/k6p3j2sTRbw\nIG9oCZVWKjIrwb/1vyWFHTDBAI9ArKFD79jo0uIMSm57owL65b1fbiGPcioumOiMVMdx3X0+11TJ\ns4XLUY6v/cb5D5Ou1OPbzGv6nF/E8PYBNkhzg2mUBU3M2vrP6NMjMuqdeAwb72WPrLRIyRL6i2Aj\ns3Al8YPlkTJ8eqWI+BbeZb3Dgb/LDlRgNVy+ZU2T4eH1QAtHaMJiwXdBlf42DurcdY3YoR4UThi2\niqEpahbF4B5ou1Mt7Qd6z/DOKYPzOhn11/lTtnSr6TWuNuZAM3+HzE5DzMxXfSAoiNdrQXl8FomS\nmtPoNXMzmc/VsZs9D2qzX/cjj3YCx8MqI6PBhWtfBx2q5h+lvwRtBIMrBnzM0SCF/JFtZHbhkUpy\nqWaGMIaU978OXu7ZRqxAA8xKxiL+QTUwxCid/ScW0yqEZ1RMrz3+XtvDpWwr/z6yDQsB6LN9K5JX\n0TK5xFBt5a0CuYGYG9id9T1jfF7zYl6Wz4JjwSpR7kTetGeENmpTYuG8tvv6cAGB3dAD59D2aTC1\nLTKtBivhU2uMCZviHQGEGUh/IyqCDwB5GN5zgSKoLkzh9FCK3Ui4oVgkkt22I3eDJE/oD1mBPulL\ntE9arXqHNJPKaoltk8fLNHBtjPv6+GTrS6NoRNn3VgkZk5f5HrBUU2OmF6O8nr8lGgTnQFnOgAxE\nZPSZ0e1r0F5EziDdHj39zBztTPqtjUMAPHpNQAn8R9sFOZjFIlkdJe0BgaJ66KR3foEHYTvBOlQx\npVSjRROS/6xPFhYoldjqZJbgB9lGpcmjUyvxaTN3sb9UXr//Rn5GfCU6ippVNPk2ETrsCwxEiE70\nZZ4yZb49prJFfT8tD7xz8MnvC9+Bv5rue/z60BON2S2Xip25j39qaRQPxV+/8XLLJ8O0rHnsM2SK\nzDgbos6DlCy20z9ZQO/dY9UHAzksdkZrA4zEjy7AWjRq5x9odCQEZXD49ZKchOk1jzV10Y5cgHOX\nrBGTdKWELTOaQiTP7AvxL/xh0gNzMIWWjyQFrrF5QY1n2WQxwRwk5tSnn4nFyhlaJiyFgfqpjqr8\newCHFTE4M3Vuk2JyJT5z9cpf8AIWXhwzpivXgC2LkKjF7J5bTBHLJIihqcoQLukD1P1hFx7m7l+j\nyL8e/UIc1QSm2icaPSV0jg5n5Rhazdc/x+4Lxe4B/3+Qtu+5cS6xlyYPuEW2guPUfGeyFCbDXzMl\nD0TExVFe4wHGCim1G6cE28lVXkWu+qIb1RmGLQvQQBnnCvvxLtZRMl7ZuP7TbGNcVD6o7trzHtxC\nSQkGSMMo/7axd0EvQ2qPjiefinP/A8Xo/TRbElSlwE+mWgVfFk+82KJtq8vHTRXwFJUwVRcNErqO\n5p9FBoQyX7Vh90zuEGv3bU8vgSYjmKRZUT8RfhaUwpQRt3R/XwhiCAIzPIvurWfaICWCjkPT6XML\nDQCNGuyRA3eqz+k9c+9J+Pwa7guSw/wd7xUOHjOy9BNftFXDWfTCC9Shmx9WKbLTHUl+G8h1EUo5\nkFbBoDH5Y6NfPiC2Aj+HthggMb/K8eNPhs5G+mf+8T3bOVlZPD0PhjVEQnO3O2Ntb4RxvhR+v+Q8\nqulifb4Ib5ZN0FJzjxvl0YdnD+xBhxYiFGaTMVQx+7oMUAMjwEpJPkl5+2zsDgXbmEnlyAzBUZ8N\nyDJo9iKG+EExnIO1kjG+6HWwaNUMHc95wmxHqk5lW2fXGvrKgg6G/dne0X1X4GqUxjzQWYuT/Rza\nDVrMBNjTbwzODIpx/nfdtVVrZp0ICJOQnutYyar6rL4cxJ+2XrOvTiU7JAeTVTnJEcnRMim10Iog\nZv1v2WgsaigJ9YuRfiZr96zYK38xLjpVEjsNuXI3LMjblJ2OcR/gXdO6+OG/R8rM9Xr8LC8adaA7\nSstvs8WRvn/M+OAMMP3bRPHPTls9jM38YmZY03A5uik84I4bxPITerQDuWx840BPwmvvH4TRtXb3\n/CA64zaiU5KgjpljO2a3WcsZDiONDGRDO2S2WPOdOeXAzAAwwKGiV1hG0uTwF4M/sEexORWbOB6u\nFSjv7RoJFjPo2AxqL/nmg9Kdy4Qyh+T39l3mKjzXEbgI3Pek4T4mQYJde+umD7/nSeyVRMRwHnqZ\nJmLAt36rYHQonaaH3Bgg0lN9AiqTzrOlgbacxiToeZ/TqLPizetvsDh3w9b/WGvJu47dT/lPTdJR\nifcbUBpWJFBSh0qvMXW9L7gQCZppCxGKPrmdGttz5OvcjzhC6ja/j6eVKpdddO2gjl5ZnXMqVEGD\nsTQL/OXLNZ7tjqhXmwRq8ESrdYdYQ5OQi5kcIWhRAs34bLHker3Q/mUf6zxcQCPgbf2tKwgZbqNn\nKSWPJjF11MgWXmDqYxpw3haKqt8xriP7U2vpImZttp/mYoHXNCFwN5ULQyoxhAwr5DnsE8rWEwDo\nASU/KsYzgy4iGk9GIE+PHJC4L5Le5BvR3KVcaugpW7TpQE6S9RPpTSdfX61o5UXQ3f9ULIrupdRQ\na1g7aFfi/kgSF0kg3hy8/lt2zoDSZEULSB5TxbqJJlOGBvI9yfsh9KRR63RTXqCA0tcrQKfJ7R2T\ndEZJyGgTJCxuLkBjiG/GugSDiMOeSwH2Q4P4sUrusxu6jQAUwx7T9Gd+FOR31hNz0x3li50AiVFh\nRZG4cvhHGNvYP10FYmPrKBQHuX3SLLWlgm9sYV0ifmAlrTw05Q40QwPFL4TTDZUTaNKkwEjFK7Ye\nCEbeU/iNwoht4w/wtTUogaYIJi7+oXWh151GKlHeHpvcuvxS4CkTlCFDbiAvJ6ltHOQbrHGh00ve\nE55u+6dT9YAIM2FDJIGYeemDbO67CLEjMqmOM7oXpTYNWBzRmctbLfIRB84D9+VBGL5/wTbAVftW\nH29QtMpvksWntSDUBaJKVnwOy/Ag1gRKMJX3Aa7kyJ/9pMj7IAktNlryj0DtMBXoz0vBd0vcyjiZ\nvScZNIjWRkVwabPMULg5HF4sZccHnwnGuhDMqOIqrMOIyATagkGQYShIrpGW05G3HSyoISozlFsw\nJgW8kbP2lTntaYkA2Vp/fy44x8i/ebTFl1uS520EBbDPQev7nei8LVyet1DJQs5KmcJm+eQeMCxf\nowQWRKug+KiM0NO4twn7En4P04Sle2ipI91ekj2tBCoTlTGlE6Ek+cLlxDoHIVp3ANbp5kI8oFOn\nEuH0hZ17VuhRk6QxWhW7EHFXack1vFvN+Cp1M9F4zU3hRojevNqqNEVjGjvWYSrVlxsOhVkhto54\nTfcNPQJ+CnzySL5CePzgh6wTFaC6Ff+WdbAgHzoTMZLicV6zisklGEgYJq9P+ktl/Po28xmOKm/q\nqaFS1hl9B8GNINpN2DkwRe5kXIFtjHx7IOewYqeEq9P4FrmfUF2a70fv1Y2xXqXpANmlKWuzDx56\nRtdiAAtoc9NBxDEF3LLSIWtVepZW97aizJwP7NWGcQkSSym6lkXGBWsbq3plhxolEUi0Hb35OnI8\nCoSFvimY9veVLdmhJHR+6eANLxxtNXjbyr/pWsJWrKwiwsL15/EdvXhGi2kU6kfYiE45xRf66kpH\npVKf1R1TRqg/qMaSibLrBfhhifROmc8x9g6Mpu4T1IRghOeM2mmriXLL+0/+daB4m6Sq6EfQD7ZD\n1bRdVphDbGKV+Pjg30edF6njHji5jbnOifU3ePJD7dyLSEeb082BVcC91XsQ6Ru5vQQ0cCCcjb0X\nfUOIx5zq1btgL9l/FJDuvtNVtRp2VRzWNYML7irekGZCr4hosk1hjU+8cKZNu1TIaN4YpdL//4XQ\nXYVgiqpe23pHB+BP4kCWyXo1FR5unohu0HH+IgRJVYcs/bn5j/MCfDT/iKn/o4pkDb52hbgo6JRL\nuayAVjrsxotRsNAwUjgE6JPdpNMVO2GCPBs0rRk8JF0TMmCiMOaAk7oNJVlq8KxBxyLgSFjjnIGb\nWBysCOBRzok/U09MTHaxt19HCubtfws/qriBj8cxIWgSOcGVG0/PiA6KejZD1VvPowBr1rivT1Ry\nbqPWDgrHsYlaHwZgQ3Rujm8s/hJpnKxpBFLKoid+T0OT+rbUTDzTPXWWDoCdkrP7wu89O2R54IUp\nVSPd+o0uHwAEz5uxTtgtSmxzKhblVHHMBjKqYAEswVr+rGVBThC20Kqp3NQyiFQ9YOxtyvSfBtXQ\nKLOroiPNb/IGbu+RwbHjjkl72BjNKj+yGnZLT+JahWukT+wkylpbMUIafxEJG3u5+P7yzB1XXe00\ndT0xYwTfyyte1Pf5GwDHmH+yX+AMoGU7sLbeVW9dfKHHLZZ/Ff929BPshv0hXSyqn6OR3oW7JgL5\nvoM5SRke8qkYln2bDUlIjzK3+a1ZwE8vF/hR+Onoqa/3a0PWhnhZgbh3ubKq93sqSU6wTICWJ5ZY\ndS1XpPFvA7AJk3FSck1HxkFBte/pzeZmwl4DbKumacvKY/b+Zj61SVlU+EtuG9KzWKhCQs7ODZNl\nDnys6BmlDqKto2A2RUEJCs4zGpN7rbdM2mfgWv3yTEQMKBYDfbKCLfbS88hz0IrO+Cd3lDp4ptZ3\nUwq/YpBR35tPJ/EpDTZXOtQfxjdnGkfahqyxWfQvpXscWUKRGhubq8bJebOyQpbiXOIAPCSjDqVY\nPP0oRwgmfNHHbcE+eGuAFx+60yOfqidZVQJKdA0eVxrAfzbPujJHOr1MJGpa9zAcZjstZ9Oely9Z\nll+DeTORTCo+cxtqNCh48ifjynU4RhSVWgwFMMOz0wkOzPh7IOlctUqqtsHF9Qe6Zpao6arxTWuN\nyl0c3MWFzom7ScqB0k/rU8yzoGnQ5X6bdqhCSfR0QwggmC6Fe8A01dSEebaTHRIcFbn5BozaB7fh\np3C9VQ69zfzvD5z7Xl28IexwhTalimBYvwWq/udKyBOzVubu9ubjoLUjpbzeooiI9STYY8Gw05l4\nU0tdf5NjZS5qfGeBWxJZ51WfFq2lFlrFmnS5jGsmBK53jr5sNmBg8hDIA4acWM9vuwm9t5vkxsym\nvdwFbnP71KRPjbaqKm+mQTh6ofm5UuqckOpiETuEdD9fsWkyGj+Dpeex3QFA041nPQ5v8STiGOnq\n0gHfsOkzkIFvElA20TC7pq8QNRkYATdK5OJM1ctAxDdVU7hVTE3aohyxZ1dnZH4PrF4g2KaKHlmW\nZIwP5vQLS71VQSb8ajekWQrpWRIwsQuvFsoU1Ypuy3ZhNiGUgO+O3w+jdQsElOBd2lmoKZvqk7P4\nyTVEziifSGt0l0LCekBsWZ9vn1ABSnkyU/q4G55yaQKgkZgbAUV0vdLWgt6IH6w0uQ8Ui2dq35wm\nJgdO0x45vwwcwlUZMMaJctcxS1XPtTsbCD80oPZyPhF0C3DMzjq99CXY1CvJ2Fz69aGboYqJF+lr\nYuW1QO2zs+fU/uLHOXImw2xvts+Pw8v4YbncqjCDUZfDHIGQj0fCUikpYy/Iix1MKS64a9KlQmgX\nspPBuW+1mZapHEDAzHOK1JAYMvs2V51IP6AVM+Cy5fXdj2UlwOYG8+PLQc1Hwum3pEnI/S/WAZVR\nBINbK5SXuNFVSeDCOAqy5iKvxM+hXsGfIly4wPZm8zMPraWMtbidOZDSgHTNuAs2gKh4L83tW0Pu\nCKChze9NCHymddCYJCN09Isl+32riVPBLhRe3EgufHLSJ0QAHf8D2zzS8YmbFoI4GlkGlyiMw6O2\nJXE7w4qD67qq4oyj/crqyoAQT+UTc2nIx1czXlum/YqO0RdfI5CqkgXhvplWiNZ4TmVzoyUEdXOS\njnNs57hJPiHXdHSefoNX1ssfPNzf9DNPh3umkNVXq9HcvuY9JjJfoNbjcxn3bbOBdfUEHuU4lyUL\n+JJt5AEDu9p/Dl9snkckCROGr3S4tM7XZgEk5uKYOrlSK3z+l2QR661Rs0eEpmluBl90XAg9UOCA\n/6oh3D+orXv5Gf75LIaBU8hfmOAlKH0hOb31KOgVMqB32FjNx9TKCGvL4IXAVjOx/RM8HygQqXRS\nYyvCDw9uHUY8fnhOfycuM1z7J9fJFDt7gxwQzpTvBRmGTV1ycUt45THA/K97qN3Gt99fd9xdJLf4\nxz8IfHt9LmmQhyMfaOTH6mnMwf4niDn9XGj1lR23HFKAXnvp5/r6rZVRHz71rcHO41sQlmcimpHJ\nZg5r7ErPLAz6AXx+8Fk29Q8wYDUuyoMPfD0kCYAVeJWsJj3xkzdqLJkt6YhPNGBnJN0RU/5KI/yg\nP4Ug27Y1ayk5VZvkjM97LFOJwTG9E4xTmc6hXuzn7emDZvF57nO3x8h4K9F5CkIJevnNu9p3HnO+\nXcneeRJ1rjOSC1mZZWHcU3fNETkEU2rXw9UgMLZp38chnQGYNLJafC2Vkw0n60U9b13jrVJTUpqk\njNJOEhRibgUPLm+t/sBegM4yKxeKJpCMvhs5cMgObtA1xZrrJvHywij08jqRyG1Sj1kZ4byrWwcK\n/DEYnjPeF2v/YczLDqNOXtj74T10CeBH9VshVmuxJmgfjQxScWXM/P6yehy8zIdzTdQKxUAb5uGj\n5w4acrdjFRxMMvUmCBjpEHdeF9xhtRvUrGzy2p7c090jkpdvPGF9K0O0gL1ucHs5fWkHR1qBpCIB\nIV0UkZHOo0YXcb+tbYvnXTCxE0La7L2CZSkwOu7bdnqF7hMRPjrjAMBuliHNmwHcHq1K+/QH5fKB\nSVcn66OEDgJ8y2v/fiPzlSxOBy89VH5MupF8g0TYexmc13rvgkXtw63dsrAutY5p6h/wf95lEXeA\naEeSb7cCvz/vGwWBphoPUFIeBMTSoiwdx6QK44I5tzzNETgPUWusUQ76jghHxg6bLO4MK+DkJNZ8\nNCFZvApdgKnb3Pgw7YDiN4EvjpiiHzmSPyxy/8TvF1SVaYOY1B+t6RSEA647vTB2dri8s5JtKJ2Y\nAYbySyCZJwoZrkrbpWW04xcQiAYv3HcbFYDYq80YI0c03J5Y9tGhep/Klgv3KMXrHFHKL4fTgP1E\nxB/MhvZPcr76BKgfoTf9t966OXFlsIyDTcQqKOq8eAaqlJsncHBa7ZZJS4LdTVo2Fso3j6ZPXr+q\nAq1yHrNme6aHlRMSj2dlZMx9bYHxFFTo209c6v7mNWXfFsS2clOuw+QM2awoeuVX8bVb01cCWMsz\ng3lk+Ur7cghyQ6jNEQIXezEhj3NXlAhTlj/Nh7B0Sa++9+hD4BkLd9PGMunXYzPvLOzoR3VDwPGM\n3FwD1ohd/+9OzbZDQNdy4AaGDXiiODrbcjoVATIKS3/FLUph/OMxeICyNArxhi4cCUn+dFi/J4+v\nzC5w9AowC4Wq3LSVInHEJ0S0EJ+SMfXZ/hewngL0MMJCfiqS4PRr+sJTP4rvv1CfY9lyqksTSGZ9\nUZlyc/0k42XflosoOQL9Oh6xl41MnND1pZcOw1TP7dS3ppFDDWaIsAUb/E5vy2vmDYN9ukzOlvWD\nDZAeD2uhLgSGQuVSJcN6dYSPDcjK7S0/5RZah0MIGdi2XtofMiKv0VE1COPPtnt9PpzXGOZy14Kb\nlw4s2nBO+AnxlcnVnRosWqgBO8i5ds+H9i1UnZgHYdeDIpyXSwhvOotXqJgJXFEY2bsGrzRYe18M\ndIdoiehnp3wCUYO7kcx0iXoXUpskFEjIkigSiJhLY1ds+S6e/0S0JP94KUzqDk3pMRpQYEhn8FH/\nAqf+5yqHSUgtLyMyy1VKTJ/Jb6kAmkkOQ2lX2A8b+tQSiK/eJOwbOaMyJ6K5cZ8DCmUgMXz0LoaJ\nuVSPLh5+TeJLsN/h4ncmApStc1S2LWxX0GXNwvQNJcI61e6JzcJG0t27NRDKi/qT6JWCiX8Ejskv\n/PGAjbKZRZniUdHAsYV0/F1M3aeQd1TCmaC7jBopuUpRn5p6lcRPMpZrAEUIaEWsWktVyitutULT\nd/Jr5CQN9kELK8Hzxsb5YQGcf51FflffDTqUKsGeL4K86cEirnCR5lG9KHO3RB+rFUb1lDjod61K\nIWY2A7R5Ewpk01RrYbH6OL8GtEtsOxwVEJDOwKR+oFbTwfojcttJA1Ja9A8DwmVPyY9QUlNual44\nbJ/JXUVkV0Qcp9Q1WOOEUEBkEWBsvjvuu+3tsARxsLAWp835dmNQMgsi+grspb6uk+A3ASNid/xk\ndJ4dfBzR/twj9B5KpJjjwpwWPF6eV22a0n2DtqalHZJx86HSUgEqKOKEE2Za7UW26+DzJBrVef+x\nSKI16UrZR+4cGW4T5ASBgoWiZ90f46YCG3ltrG6C3Uz4GI9l8s6qfzW5/+WFLFs8q5JwUmgWYGcV\nSrhTg6CCwBzUvjb2ZtD56i/hjmQbySjIBBNIz1NpGOnHg30cYGS+pvUQC1KzeSl2E/2Z4FS6E+jv\nkATmW5FdwTCuF4rCSRXrZSEeCWGE01f2QR46CbvHCgw1BivWBCjOxWxRE03+JMc/Ie9gLH/Ye4W9\nElNcIkQsFpvDHMv4e6Kh6Ij+9XgCTmmWVktCeRHib7ujtUlueX6NcBz+Dx5I+xIE2oAZcCMAka6b\nFPYYXrIoSof3CXKhjmAbgEbszsVz+AdyGsYsi6cy7xuN9G/m5w6b5xGliltritjlRx/hdVIBoUQK\npAEyOymDWwpgCbGkBsZRJZdZqjLTsOSM9ulKaCHXoNQ/sKTnQkRwY/nikC0kDYH2LQEOMYvKQxxJ\nNNuSV+L1OG9pw0UXtOGV2+dxIZXySRY5hwSPLQRLF+tCkrZnCf+YROjiPBOwDZlc9Grq/ZY3UnOi\nZRyp5yTgUmfKb64z+t7Mq66RMwlLf0NM6KOTBzfY8ggSQm8y8kiY/mZzFejQeqabbQqOfyZ2YGqD\nN/DSdqFhsLw8a6ipCGUoSwYyulbWP4zDDAW/HhtyDhgGuiC3FzvABR0XkmEC3Gm5DCBF8NAxhxUc\ndqqJZ5co2XuaivCdHcDuiygkgHMdcEb8TsNi35r04n3T3zl0oo+aVv4bGwHJiyqVr4q7ATCIEg1Q\nfJW1nZ3K90LVpr7fhzLenXgi9MLIZYSYmZVV9fw1pzVhY38e7YliPHLc/g5+Cb8MLJxBJQrNsWCo\nhD9lj7f1fAfgjyZRFwtMv4FXld6QsfJwHEBjxc6zmTGFFLUbbSTlQ3T6cIbP988soja2hUpvKnXe\nD/Fy9HYvp3pfHHd2NsFigeHdpROtUKuqy2Mo1kXhs8SCYO0Q0paORGPv3FtNrC7k8YxKFErQltr7\nRrpofipYvxDw1zwepoZL8mF4gYOfxpa423HFQgktfLxmtvFIpN1zrkCM2xlENs9y5fLPbDxZWUBB\nntRBpUJbi26urdFeTvDqvLM2TieIixLN+zch+i1f2NDjDgz+9vj4xN9g7D1fWCsy6Rq2iq1qExKA\nK+CJoxXCnDRfX6Lg9ArHiHldTJU2GG08FBEaB/7ohXcVG/+rKd/mzW+u9d9tCvWicPxUaoC8Wzyg\nyHHBHNAsp3hPtEu5USdnwS0B37WhgUCwDTcHGgEe+oHND5nXOC9BbHAzznm4klc9yPm4qwKsriJx\nVfP2YPJ5lFH9BaenxRgLCEfrsUrxZhudZyj5mLjcxh2UDAO1gHo4IEGH+9iDMxkWCguPGFGTcAYm\nZj0wAKvCII2oqsTF1ncicxa/1H6AxtzBA4QbwkLv5kCCrUbPtbjJ03cosEWoswzJ4Svq88EAQAKs\ncn4xq6a4UHeEuxY0JEs+u4ANTxuiCjfWsoJWH0Hm6BJU1pqIqVChVrN8lFkpW7G/HaV8Bq7W8i/0\nmPfqXtdcCRCXDI2ZcGiLqp/f92ZbVeLuX7uQ33HOBdzAo7X9+1eK6jkw6+YeFOszvXckV1VWLq7r\nT4hOuiB1k6eJaM3X+hCwuyv1DOysexCR6c2Yl6Mj3e8NWdXKZ9GCwfEzoPgiXtBw2UR+k7dsgC3g\nFHCqSwB5IoXq6kIfkxwamLieUzO0UoCvk6+M5sM8kMbCC8BCMQrVs9QMZEOPJHLWWTxT3fq/s8p1\nmtLTFmhNtvD1JgmXbg0SJQ/uk0XTvH37xYb9gqHjrGLA7ZacMJC+KrtE2KYE0gW6gmIPMUzr73E2\nRPAsNzU9Z3uhWM5FAkmCxEcjg9kMGaFE+vxx3KZwAoAZ4CwIek93hePCFZU2rSYzjFu2m0Ge/X7q\nWB+BfDRJdVTkfGPWS5WFhjiN8vVEzeAjVDVF+j094DAPWQpatE+LHjSLiSlZdhqL2A5aKebjUr8P\n6XDJUD8AWzgwCOUd4A0/vpcACPgFdwGv2731ojeqZfRnO29Oy0YidrYcx9o9qzdfrZR610L9nE4k\nQ1zpcxJrRzQ9cgSXuVFB4hGoFIV/KIE3CM6YyLrvFh38X3SkVwcG3P0D4bSPEHICLJMTDqVbr8OS\n02x4uRKdqxbCV6ysx2c+d+03aAWG4t3mrCZYt0sRuEISjnbMGExYK2B2zk7pk+KMFWvyp/+pk/yW\ntfi+UWYHjT8/ETcRhiW4kizVXbuRZnC0Pof+jNzO+pwJrxPW6A9kh1p6/XF3V7+8Jncz78pTGGRZ\nLnPn2iN4y4nQeRL23kIqmtzEph1n6eBq3OxHL8ZJeD5Q1VO1kcvrm7EDVPrzdfh4VAsh5R0xY+cG\nz1Vu4/5V/0Uo0TbM1F9K5w70/TG9C0KxabrM7Ib5DzOYLK4wCTgY41WyF1Hj9N7TqKJxNf8U2Oer\niZgInStXAU2LiFVVGY20o+s1a/2hVw739LrxjF4pP5jXhfdZIqzDCMi2gC8Ha7GzpuM5gDH8Mu3D\ngq7hAgCmRw5pbxFBSwZb6hEsKazdBQ4EayNMsGdtdPlbZmllYRwCR5zOnk363AdQ3XtdBoY8d9N1\nM2a7Ddo/6//pH9dkKoIMveBzx+/ZKEzX6s6n86ghkoBXsv3kGvhmTvpKrnPL7VtdVBhBPuvFQpo5\nmm02uGeNi2iONlLiJ12y1AbkPAq0q1ZXQWeVFkApo6DSmSV4hVv2uchTtkByHRfKYEVQM8waQOEO\nGy5gPRLCunaws5fgTvt0nhEnjDmKHtzsWFk3tclMYThzA6SH0rvr6fLyglu2CvXDLq0fLdnBss4L\nCIBOPPS/uDUYBB6cnDaem9ksgtmhow8L95BUA4ywK/twITQWdW+n90a7nPMdz4aBOaq2ZwKuIS7n\ntwv9v5hOJXOP7XfRDnb7AdwGN2SZA9PCkVpKFKhmRzE1mGdYqTcj9sWJLU2jZim+xhb/QxhysFDz\nQMUi3qmSqwqXFd6ziq+UESxLJ+j+S8Q05Krc5j47pnwDRMYeVEoxAY8iGAn40mgPV5UQzgRjjRuZ\n2aA7ZTUdtrC21zBZeGdAlMG+LR0d38Nt3jJnDPsjJpwx3A8qUhi8Q4lZiQ2KzNHduEY6mgG03H6x\noPC6N/8wGDndUFxoPgY+Axk/iVBWPWOvYbl/GyedlM4vLFNW8gdK5K67gfPSKBJVMNX3TBejeHWO\nOe9FKqlGjmNveurbmPpHVW1WAbneqv4+mJ3ACiIstHsfe0Kxu+DZYDbu2G9p2WcR3lrd/i10jLzx\nfNlFot+r2Jei+P3CwKcG7AvECsXNmy4rB/+8JyO+DhlGDWFI0GZYePg4KfjoMCf7v8P2nG1bu9oy\n7dlwIGpnhtcUybimbTO2WyY+gnOdMpoVMonYyIAxlrzEJlsjipVk5DoV4PfgO96/ORFbDlxZlbaw\ns/exzNtCawNBAJyIutadElNDgM/d8QVDtaPDMBgvBmWZTPdEofPfspOXpJ4WfnPKmnKvMm9Iz2uk\nKk8Hl7FYqz4GLFWrYRYohtYgRQBnZ7xreMC1nePr9qyV75iCWrRF2XiPQBru8fVeKhC9rzDP4TWU\n4vY1tZ8lpskjiuvMAn22Sd7T6o3LheIY1BRZ0NQ1KeWsVrd0R37jcqBLoz6e9CE6iEd1hemztMZR\nlej9u/saptb7yiUGsSwVPLNrnyg7DzK4eeGEyXmofoM9sGYKLXVtFEszFM9KiM9gG2qVy9xk/4/2\nGfycrohdswh0lPRjApCd3nmmXJQwD4rvjcLFiqFXq4SrS2FHTaxwnhYq5CfihiaYQSZV5GZAXzzN\n04nXeTUhOSmAGXZdVL4grYaNtuUdplqIWcJdli1Wgmm0maSW0PePozgD+VeQ94UdNu8G9jhy+GLH\nVN6d2/XWRTq5lyS/5H/WNINomXfX0sfOtzOuU3Yk0HBsZB9+XCa1ES/eygnPA2cPjJMXVBtwLplD\ngQ9lGbKsZJGJ1MYFkP+HB2bOF82To57cX5rEaDLw1N7ZP+9x+4BzehDv3LARI455MOFKsmyeTKpq\n2boLWIx1T5/ijc8uYyNprbAvTfO73lkZekEH6Ln/q3akzgR/5Rez00TVjMD/6bIp0BoPCrdCNIzd\ntL/z6yA/PhjPB4ZtgTVsNqfdTVtbxfdZqizUgm9Zem3VmJhjH5GaHyjNL1CE+CN3gzeqUIVgY6fw\n2ppVeBPDBhXnVNEqeaSRE5beQMP+naHlZeU9OsjTZi4cbZeACG0+cKLjEiGPqbz9xebGzQu7doeZ\nfx2vPcKymRoEFNKdLkcdO0DunRYKGUgvfU0j8un3qU05Idn/rCP/YBBJgdTjxaTjP/zNuHX8xkDD\nT+/CujD1JdXeakWC8eV8SI033F7M9u24lHRjecf+/fkTNGIs3o0vwcK2uqTz5l3zdsBkZ1gwj1gE\n/24TJjklGSAdN3zmbsIU6ptv1REfPyg9a2UZvOLifCpz8sDqYwoU2wdlDB7Z2MRyrn4DHFTI7+yS\nxOPvgZxMWISSJGc9SferyXa3K9l4g7CiL68iV6w0IQbOlHfGVV/wu7SVZZOushOpkt76pm7mokv3\nCXApZFIZsw9Ug8JOK6+qBlblhhOyx2TXNwUZxiVmFD54eN0GKx6HI7REuw/sOlTkrTarTaRYfuAi\naQoal+QMw7num55JL3rOdoVGXCrw4Dbpu36+yuSpU7pVUotuw8KFydui8zWRuxihAIPF2EjaLnNN\nvqO/sSgYc4EeQqMblWmcik/ke5t8F1m98ZjzAfcaxWkpaBlzS0wctP9gH9TrymQGLaXaGZh6oodq\neZfztRHMyZLvHpM2lSg2P2uLL6mrMPvK2Vl7HhgcEDnFtQGmub86Phm6jeiJj8jkEN106A6CKjjT\n9FdEulYB4Ifv+W07td1UjEFVvxFp0BXCUs/LTjlqGZ4rQ56b8/tkvMnbeVXDevYVY1x7ZtJBtmfg\naqaIhJd0pbsS053LZcXq5FxMKU79jvGs50btVBtTWtPm7+g/Y0L315QcaT5x7I8tqClT8tW9Wvne\n8MjD0see4tW2zp4aJje74vci3UaDDahvnRl1uUEALb7/nlFchxmj2fQA0aqbK/QQxHVA0ZsolzXP\n3CXhttkXkpSLRfNI3IviACLPDN6JRfnK0gUxitm90NaVQUHjSRpowa+VeKTtXFSxXEEmYTd3t46H\n4IXysiIt20uoneg2hV+18OP2I9oxvTo6bHfBNnbQcvz/IbBcP6DsTAJSyTrJ7LNGro9Uxt/kKDBA\nrRfw12+aYaAhG+ZptS47q25j9nufg2vIPTFB4reMOxemQdG0Ii4AmyhMOhaSAfu6j/kGSRZ8m8KO\nqnrUTPGGFWyWpMhK+cdmibGzlepLTBg/IXKOdHdi1cJd/7xK8ikFPC2a5HJi83rxXo3/+VvD9Z6i\naXc6iO+H1XvS4O9Au0XVd/G3i9cJGdFmNQDy8dN1A/KXLOvikXIFQxydBHTcx5DlaTO9n0KxFXoi\nYFoQJmFx7LWQynfa6/7myIjx5VhbmsEzHtfyhYnlM/aldlcfMtMxIBukBOGfoFIggNjTUs/vQZnj\nKYWNConZMdSj2s/Dt8n7GusQQJ+QTfQ9Ovp5GuiKBnGwVo0StlPhF+pisXCKedGHrlnNU4okZuY6\nvYvGDU1oqn8N+63FgWc/XEsQiXPOlYjnKYpdN8qxlYgdX/0YiqfXWx1fkv5FAHOF4HEOt4MLsaXX\nsi6+oPDbnassSrO9ATm1s8s1Jbq5LNOJenRFhVVcxBbPcuv8OaauRQfcRVGh052dDRl4mvb4Ybbm\nzxSVq5EUdIa6Bi2OIbThyPjz9kDcTm5SLj0q2BP7mGLB9n4z6lYU1h3M+Vc+I/vpI2aAk7qEqOk/\nSo/fkPPLds6E3MUGmhxIVy5VC59AEfBne7NA4vxPHyZ5Bir0LYZfNy5Pj+hbgoKwAoqREwVuSHR3\nN6uSwqhNHOAJ5CirGFYyOy8XjjQeqagrpuiXHi+56EicNLClWnywYoRogj1fQj1XiPPLLFiFBVRL\nsmFGLu6CPsaAXW0v7r+dgL6LQTaylIOQoSqdxEHo1jTfS5kcyoAcdeXC7wXfsOuVG8H2zoc9+YN+\nSUfK+WG3e8wIThhP1ggswMQEQ8wX0oHCDPxttjFl5BVU5iSvpdqnktfb8r7OcvtAGglhX4S0BHbw\ntk4RmKMuw0otjyvlP63Dr3JwpI/aZWTxH9ob658i/zQn0Fg8FnmKU4A+ooUoyp4A/e7U6rzT6Rjy\nPQHddEkiQn9SdW5tbkvPPR6MayOLj+CHvdztSLP9CblwyQxiJrYhAe8LiJo4orHHAFKMo7WGaPPs\nCgHFlEUhhfgHGQ3pfPp5yQAr+rIw6C8i4PFu5jEBs3fEIaws3rQDQO/eqjQXguzqQVpsbHkn0m7m\n9+WOZI1pn0Xhfl1c1REMPqkuQ1bTHE/8WN+MGrxx5cdoC8rSeCcLMTY0zqMc5n9nRYjLhaK4q1X/\ng5BMSNXJ9UQ+6t92l4SSPVcoWA4L5R6rR89T48e42UyryxJpviC+nx//MS/ySrORFQTBBuPnLLaP\nCr3OCRb2Ra/eDYpGLugTzb1AOL/kRW/FlEueZyNFDnjvzpSI5kUWoRWy6rtYoIPKqqNuwg2c/s2J\nvO+I0fhR1aLssLC/pbEgfwlgFFDZdYHhewxSnr6WfxM+enuPDXi0evIxQxj5VSbygnWExjuhCkyt\nchRXr+qY9ER09OBOrs0p2eG7WlNmLNP6OYvDeYrrosWL1t+kl38fS4R6CgL3wQyCOM2nqIB5Y7aB\nZaSA7+sAkp+myRcclGl8AtvoR3bvwMatPaHSe/ffxoVsktZ91NgwWQtQzh7JQkCugtJsd5UiOcuh\nJ8qiXy1jF/4F+hrv/exa2O/Su6Y+UX0SBQfxamFIIl4OshvbBfoEgLBF7dnX54G6RNTmKwYaTZyk\nxB2MOnhWCt3kA2YYW/OtDij1exxkS/Pk8i9/9scGuRlm8pXVE8zEfWpU3P3MTJECzpze+PUwqDmg\nfyH263e4zN6kIt+MAmasHA3dwWkKbte8d4quRuQ4wDUMrnNxcBu20P/FoHxNg9zm+XQz7lHAyR1b\nkdUEgtx1m/LW1P1Tl/ROpqqLspOd+sYJl0NZayLXZ56gZxXG/eAAf5dFFK+dwmCigo8knr6k4Tyy\nUUI7gt5We5jR8KmBGXpX7ZCEvqnkqZSDLriGiCRZyKIksPQ5jmcLIGs39/Vl7IVBrNznVfvXAD6Z\nS/SGM+/QzZhAG3DIfWYw9URGTZe/IHtaUzh/YUavKKhUOrZNJ+VuhQT1gHquYiYUXgeOj5NuHP6G\n0s6ejK9/vSQ0ZSe+SnWBGFhjFwHnttBK6Q03SbyAFx54AZgQP0tfYnTGxXga1g83mGaTBo8+MrYs\n1Oif1e7fjs9AlREWsxtNzaRCkCw1QCKQ0fJMJTM25KF2HUheIh+sWv+gjXUPsTIlQzdfmBqsTMwh\n+kw+LbBddWFPJiufARqLgeCkAv2zNF1KgQfV7+fSUFvgkcm+n0dvhGxmXArvOwPhCsWeY9niE+fd\nEHMJQZ0zUwpD5uJyANhW2b/iXlmkoZFCo3qtkNqRsi+QTVqu2Dqsu38O4uRcDXdr8svrwBO9zhCK\nfBYqDkkds2aFUeuPRyPfaEpJZE9Eex8k9/rFxirIRuoU6ZqQOFLzNl7mGb+KVbldClgT/+DjL5wn\naA3TEimAro62F7MI+8fBtHGMFDapVDQdbIBiVxfJ6Ft4s2r0fnZst1uKm3f72zsMN2p0sWF2v7/n\nJI/a8KNAeS6254o+R/psQX53BC9oWzVpmNpAxLIuV5WQ2pNbK/zkf+9cMqM5Jov8zFvOQv/hSo9H\niYIHflYz3LgLU9LRTNAUp6wyZR/qMQlihryuGaKCjO8X6qiKPsvoaRZgyJYVx64itFEvamwNc2aN\nWXisN+G+PKNgpav+R+cXtefPSx+r/hAsBUrJ6ICTMFO7Q7ZiwXo/gcVTkrKbe7DMpLcu+Ei0w/4f\nII2glqJYNLKDJOb5L5Q4UBwKZfAIUDxrus0JoZ9D2fqcGZWDCrlLtIo+JkysUQJrQAmcAU66wuGY\nqSParq/+UKANwRh9HXz9iKcm81BWApDzSnCovVKK7OQnnwIoSrtr/v217Srz+MkcQq1W98sOjilj\nESiu8edY9Y8fNpnwMt1x0q+uqA6mLHwY2tP3kOSugtjOqJfHLkUw1DtXLpYO17F/sZFcGZmvXxnk\nzayLn0rEkYYC2KR4A8ZCvOw+KwWTuacMkl4DCXGs+aIg9ZjSqGQJoU1VK7AN0WDdVTQp/gRKA1iu\nuUGJFglGDy+knk6CBLGLAdrXgsDRJFWqVraFmHa3VlvLTNYtC866LrBu/q4McM8ge/efev14B7v0\nizMmsQp/r9PakemnGIpCbotHiFOlCvEkJtTCRcXjjtpMluv1XO76HdyjZB0ngPXW6zNSsIkrD8he\n6q88Lgj5WXtlBxiQDMKXj8KCOcLrxHNe63zpbOWYfeO0weyjZiitodKCWm1w+rFl6Zu3hjUH/zai\nMAh8ZbWpPYzWS5KKU2ZVSH28s806Z0RHlLYZuYlvBa0V3JXFegnhUp750T4HE3kVpAjLgPOvveh+\nkaLgAdhPlfhru80CQH3jSRu5TExgMNUq6BGbEklf0rD2N196qARcyCY2OMNeR15JHVv3FuknH7Tu\nU8T6N5hcusNC3FtuaBMCtwh0G4Ux3UtxBI2Bl49yUH74Mvlg78IPyeRwY9QpslYQ/yJ8itqzoLFC\nToouZ3uVjuo+henifnFv+rCw8wBTEK5YJQWbHEgrRHpNmUOrvZFTmwVQZOyn+met/LKY8FTrevtY\nq5haXur2hwQIUpVtH5AX/USBXx99p8n8JLfUeW1OIlmm5xpj20hgZMlYD0prtWzYQvff2nT1r9vy\n1Rq4mqO/kTreZnrImanT8ibZAf0Fda6rzbF7harzabjreKXacCaVs23n4dancSlATeXvUST2XL9F\ndJlBO/+MpPUSj4v7AkxSIQo8jYYhgUubYGFrTkcL3uZtvAGhCygdoPBmnY9WkqRoM7PYLZsm9z8H\nob4mKEmvP3ZiSemKxhbKdyFm/bq6mJMinffhu2Q7yQyHH3pBLvajPKwidWGQufPk2GeiIFkZN960\n2oWhTtVtLtmNTaC9ZOSttKf3Jx7lMMEXhqHiCMN2SVjKvHGfJB+0ZAdYYx3RvJU2Ra6sXPmwmctO\nZb/1RxkAGX+qF8JFYr7Q3+OjmWGSIFDV4lF4isQKL/xfAswlMN/Xbp9yQHdmDFDL4iOpx892kIkC\nh+mFKlFjjquGBfcQaIaZ7+kDBooJrcFnOZluxR2cARsu3bozVgh54+wEJQBlVXipwgClavpyBg0p\nHaET/cvdCXAmczBYJdqI4AFgDdXHQhMkmzsCPOGhTaQi1K4HwKquWHIfXpqaPgpW9lmmXbBc6nNN\nKJS0Lk9fP0Itw7YoN7ujUfWVUETZ1c855Hct+jMjrjJrjkFEfLSbEiLHcHjmB4PjwZQyz4KS/XJH\n7bTKRTTKVyAc0SB7oz5cF44wiNW04/aQWB04jOo6+Bc/NxHGMFfJQFtkSu+l3+OEL4Cvirj0/H1o\nPL3kB0IACNQYajDXp3LJJIv3sTZA1vbrtVo7yDNjEiv/ZYaGiwWF7DwUd6uAt3FCqZ+bA1rMCpBM\nIF2inktNuNXnVOozi17IMt5z7/He37YvKv6vTZNA5Og7FXp+b/lekqE/u5rj4+it82qRb3x8h9kD\nd6MN1DSh6XLD7jDWzSyfkpSB9EeTeuWCpfT2TsOjs1Iyz6FlHvBixXGpJ1J8Eft/GfMD6+jQNitT\nCcyqzM2OZfo2xVZLxHxZNKwSo7Y+YSvTEvzafSqvmWGZAeicbtu/55mS8TOfPLJVlVRVbesDRr5T\ngPz3FCLEMcuAFN48UYbxTob9FnHrFWQoG1vFF0Ht85XkFDcKzxCZk1XGZSeSd55MxwcYqhJGJO/U\nzwMlLrpSFEXEnYBO5Rn8mOmhHlon+RE7SzjsoHfLV9S0jUrLcgR677NzJdxmGYfcl68atS99PtMb\nGDyVHIwmRCLFVwVCdlLilcPcut9y+OFG3+OAJDcmEFabOG/+qlAXY7AZ/bJ733TeIDiWkgFDqfxh\nJ+Vrxl6z9LGt2k3nwHcF4slS/SEVt+PA+SwjeVrCgsP52gjDJ/wGQDSQw0+mti9GAAOAw6R0Uajm\na6Dlt211CJ6m6i53SdXBHqeCmI9N83HmyIG4ho9osNqP8ZC5bl4bUbSbOWpnoY6zQKrYpzH2MWjP\nx5eJ/W/gd2eLPZGnf+HNw7dhaRcHjWzv+gNd19G6yViKbqyLMbsmzOcwiYjC+znZLgrkLNlhGoCv\nzp6oajOn/GUxHZ6eZNnpQWCKYmRaBXiYgeK/7zA2v1sQapmOmLlbnBYnoQG9Qx4/39vbvqJZynUR\nkrpQORXjzTwLWLi7Xi/3fNT71Un1o/3GYHhmor12e0vGj9m0IRyXQLdbcflosyYdrchDvSzUXHCg\nq2uavnlhSrGvKYeq26F8R0frJkHy1IxI4FQ5UbB4ZRuN3ZRdW+6JbRD3jzdx/g7fjOOac2MpLkgp\na/Kfy8jDSnKELyKa0/S3uElqyF7v+ajPBNSUgq4d+l+cum1H8qCTPdke5no7wr+ii+8tZb82oGyL\nHCx4bYe035TEqvBSM+gH/rC+SHbogHTsM/HTOaNTBtdCASu67gWn9rfpGhVsHwGLq1e3K2//A0F4\n1Vogit3NhRcZvmc/TQP/ILochX02aywvXcenu8WJaq9EM57j2K4EASvZUC/UOZGuvududaJO1j04\nJbiyNNS0OeKfX16H2+JRf6h16ltg95bIUDGlBrSRMd0geUiBZdpGRkRQpd8qUU0r97nI6XkFe7dQ\nChjE0W0XHgmmBrxONKoTKxoidyMVcYQJ39trYbyEW2r6ppz58epjlPGuTaxPpbJ3wRArNuarcQOA\n2KZvGDmWuw4KQ/W2WvDm2KyoJhUIufS14ORYhKnphlfHbFAutH1PCB8HIt621onL/Q8LFyl3saec\nQUUH00cr2Rr8DiaMzHaytXAH7YKKssEVjChugKKlpj+T7MaNMnpLoA+gqFJvkICBbP/GoZRRzAwC\nZoMs5OAPV1Lw9RmdIppeajy+oQhJoRnISB5Ck09NIx95xGgVgxfHW6OTeDKGvGDpt+MLTNhyzH3H\nwHCAbWfGsZPnReeWbAkXu/ruQ1kMzjHpO/pyARZviwacuqRg6Xt1GNIzRngW1a/Jg3hDyZuRXSm7\nM+2Ujr625ds06X9Joc/MpjZQ6PiyKB2JZcM5E6g6pqwgGfBPT0rBLlwHuAfiClyCe1xPVVsIxkDZ\nOufCe4ajqwB/IapXd+kUonMj6TKTQNAoqL5/FuE5yZlrCYguPA50n9fk51VQJO+wumPgmsm4rNJR\n2HSTlghwdILqxPnWsPFiL5/V4Daiz8PsoSVfd40nNmC2tHIo7uY4f+zAAJlpxBzFBOI0Q1y+5LVY\n1kOEPBMQYmB88VdJ4QscnjgDyiUx+ByRgMlM52h/jvZZuc72TJc5IMUnpzwMMmjGWYghQWDTNOlL\nbhw7RuYaseyncfe3AvY4KrB01OreYmABBJdHH5RD0TZ5wNjv55lyGv/IrKmoALcRa1YA76zjeG7d\nJirBbQ9iXUPRQo1AWW6YpTU9r5vZuzaVNGwdkHn9uO2nt9Xf3eNg1TTGC+2hnjS5MDAnmJJyAzOO\nR7bI0YBrvkd7f2LK6spYMR4OcScc8uelLGYG0L19mjenB5r4VzJwjvuPQX6NsYBITRf9JXwCtLhl\n13TkBYSzmOkKpeLd1o60EMvr+FHeJHe8PVlaFuvhh+32RQplBQsuSa4DLAg7/Yq0DrpUpwK7aI6T\ngpAcdk4YNH+//kerGMZouMD1p7Oh8venM7SRXvH+D1pKw61WDVtTbLMQ5mQpftyXGZL2DS8Bcfxm\nRu257y29/QmocKr5NE2QmPNWeJk7MPTNsECwoy8J/Te+JdX9lM+jpUsnKHWCP6UKwArTYBO/9g0q\nAUXxv3Y1HlkkQJnR7oYEpGLFgHWBcJY7cOZIJsOEin81J2KndJvolQHJXk/bFEKF5BrGOwRHPr+T\n16ZGnqchFfbdDpyJTB4a7RWShHytRj7YxxcNEuH0Cecga7xTearFxdIPmvEYqeCWphFmAdUCIplX\na2ZBLa0AZskNxfxp2cifSFqiDl+zE5Ze7KMnnFYvsEd/Kk8ImwAohU4Wj2EZ0YL04YmjYMttmEsR\nnUpEUDM441Y5qN9IRjbHlUzlbmiN2Bq3j0ByEMQmIyav84boKY4hQ2liMM0ovxkHD9QXK0Pjpjvi\n2IMybfgR0JNoH62C0FxPksn23SktMxVVaoX9fKAtxGAd8pq71q/rbdJib57gXoSo8Ep0nhB95xo0\n9mtLfgSW9S1L1msE+HyTf6MdQ7C9aUZisfAx7zskfMzDRsAPv1x5szbib3MGJ7fUZ7JZbRajNJZt\nEwYM+gpa2F1D8wos0/vcPpM8xf+MLg3K2K4+B9Otu1nxgKqfc1/3bYCLEZrhGmN8JNU6yAQZ0Xzb\nIV8IftLC6Z+ngTs5CSAIGbsKGhbHUFI2V0qt/c/yy6tfVXIv2LNVLBtDNZi984AgKcbEFT6JPtof\n9ro6Mk+++fGfqq4M6OCFSOhVAD2ItsuPC/+eFgvF8Jm+KCtwxaJhyxpJ4Nj3qN809JCPR6UfhdEf\nRwTzAdRj6J3HOeUekRH12pzbUUCgzLBcawXmpaq81Jc2WDnU62yTUS668RripmZVZvR66fW+pI5u\nu7TM2vgdtVpnvrIwI5nsKtL4I88Y0+Gabs4095HcNa/kMF/iiwyIPxUAnC1fnBKzisUNa5AzwhfA\nFJT4I3lLYHq/TAiyWJga0xWu0IsLXKIBLkTE8Z2bRwHtip3+nB0FfmExLdVtBgqiAxyKmDH5PRqE\n4qIy12CGg4qkyyovZCSdaGNv1fM/66idpMoTRGs6pdCR9aKhDmBpiSk3YjRYeDGm4UUmxKtwOLvB\nJdnjhAH4wkMylwhP1nx4pIeF4JXm00LkbCNrRsK5UY1IS0qQxBEEQkR2PdMSFmaIPJmLPMatVwbI\nEd5+Spr2NKwkO99vptJJWoT3ng/DTGIEYE7fQx+hx9kQYb1vljW3Kpz05GiY4vzOI6Zqc38ael2w\n/npRL7jRaISqZvVixhhvuy9yVGFZBH02aPDDOvb0DxSzQxnzlIz7rU07nxho24rOMh5FZFrmgaTC\njyGtZfC9gX6jXQO05M/HFaOSwoWByenf7ghhYL1TP5FkcZR7QI1DrWKw+rU20vGWtumC9ajnL/uC\n4FbwzIhcA8eyc8sF3Zhj1J7nv/l7E/17Rm3wHpEMfo0LzO1K4Scg4TIVN+Lws5XptiegGeEvGTpZ\nW03s3nf4wfE3GW/TxdWWTKQ2P1oCu33BYI+ELNLQ4GnJXwre6+4JHzNPI7EAuQHJb/QjYoy2cONz\nDWcHjAN7JK7OW/nWyh3g9l67ZyAKOYvv8lTOanhpLISsLE+GyXYtBwoAQYkZjf1JKJNgF6AOtAMV\nSHGnpSiOjiNg65uhdlL3OggvJ6sa7tMHMs6//k3dN+pAzy4pjUGAutrcKex2+ENo0tryClHyish8\nW8/DFYFtqwc4v4uvkiTQW4rJKDWMyjZnpErCkefDU0q/8USzypOzufOB3wliQles44pRWm1OjIJg\n/uuRkXPUbsScTLC8ku4RVStXGXCYlc7IUbiZNNNpMC2d8Gwn/yAFsgxH8wlo3nRjrWMxMHye9DeN\nd7x6Xpccgx1693Y7Q/qJIBRztrnnr5VsH1wItTjcKgrFkmHoW1ymrPmQFcen/Itkla4Hjximrht9\nH3DwRGrPBE8bG23zRKfe7D5p917w1l3MnCzE35+AG6ZYDaPO6/jtVzb+rPgaf3AXxdo0cbxCdf46\nR5YBucD/kfb3cpivZQDkyGU5jggOudM6G07CA9JsmBDbilYXAeAwHYOt1A2JZc+d3hwFMyGQgVJb\ndS5GcrcaO2xDcTlyPSEkN4q69L1icg9xrnW1BrfDIwu346aZrG0YvKw0WzfqVdtf4ODSJI6JqH83\nRIZ1R88GC8qtOUhB7Sz68wk5OP7uK4GChFiksk6nA6S/JvH/FXlFGTgfRek/MeBqxT21VWVc5rLc\nOfdOHphGFophAwXOOYSfqhvUAXz9Y3PLMRuMi7rPeq0taVexlXqtwX8CpzvrPfsuFZzQhu66eiNH\nSdDQmc8/wSfC4+nXkPWMOLwLidduU1CPie0MN5W5XoiULUVN0DrKZpK11LzfL23aDKmDpdg0fDLe\n80GBdD8/mr40jro+RZTr2CDIt/qDYv8E4iKYgTu8/1N860XTc20EBdkjJyNDSAmjON2S4Nyp5r49\ntntgi6DdWzwfL8AOxAThQpDSKM/71z1KEhFQgnwOSzuVRmPbolz6qrT94nWhRdxcOd2sOkTYtEOy\nOK226JlWerJXXQ0fQzB1dezhZA3gk9LeB+42FnjBozMID5RUgg5R9y5M9ozBOO4mq90sBwgT0I7D\nE8Q2uzZb6yuX3h1Ob4mwJkBo0VTapJPBAp7yIfFzQO+ANXKq98pAERDaYXaLIWwpPBC4l9VYWV8t\ns7oLz7UQWB40RQnlPdbJMKGhfWdpBIrtQtD2T7nh8LlLMH157GQf/tGFgTBYhZ8bLx7mRNxSckhK\nQSIjkFXByqLOmy2bmtq54sPLYKYHUk1DA3QAwgDdYdBs2c8bRTf6su+LovO0hGxg/JIZvX0fg+Rb\nminqNTfqx510aOcwcrxKu4JJFP8V3q6S9ZDkw7uhBarrg58jkuvhHEpxu0Uq3rO7hApsIKZHwG3f\nSOo8q4DhdyExMNpVIIGWhP/Z7p2C54T4kxupLG1ramXFxUhmDe2133/SA7KWg4WgA4rde1SjwhOC\n98WlK0DkCoZo3IdTdQy2OAhcmm+6fR2Bbiz6OLCJD14LVZz2WCwrCfIh49Vc3zpy2JmDc/71Hsl3\n2pz68l5edGcRV/Uxtyb89OrNHGOhuWt6gDk98IonypRb/7ON819k5rMXy3mqYM2GFUs5hRbG/aKM\nyHIujsol2DxhnQE8rRZdZPi1GKd9daHa0AqaBn+slsxqKHztk4TsRO0LZcRmJMLvXbw99IyAlnpz\nA+sHsdRsUHwfy4E6T6xygoZ5j91hYQh4V9VGtJVCcGBTJVvbwt24cfJ1l83+GSbhYnYLGv0CVbCo\nN3oYZSlMBOt2b5nOBIpHxSF7NfRdhu7EvEGw8F26w0VzgATnuU22HiaJwnBwvGpRf3HZFVCaEQYI\nNe4x/RBOzp2pHsHno/8Xse1UI14DgPfMrDxoyfFLeIv3rnhaY0r3hprmsnce3mEYnk72BdxlTkaH\nms6ab6M0HHJGyn5PMRLs8f7xdehlPEEFR/XJQrZrwOOlFOfRxH99x0ZAfKOC3tIbxqeZ3aQS7K/n\nKxPx3MaWyS1aN3rEORkSsvESOJ7BGX/YryYeCoCaTBkT/WkuieDn9j/TtmT/ZwFKwRSX29vzONrD\nDUcE2y2KgaS+npnDsq6smbR/Grd8UtAg6QykTmOdzyFa29fNvNXS+zvtSdn9eEPxMkMBTssyc50E\nbqtMHZQcIoulCKGwDKlljzwC7LN0I383bxsZbvh/M/5vDcQUQiViB7kObVm9g/8nAS1Gb4dbxqwH\njKGspzJtaW7nXM51z1+Yia+1rddY+tpFTqkVXVFqauRayfqOSL9quhMbaOnYFQQZz2U6i/Ql+SqY\nf3PDsZwHhbq2Qyuhh/l+wrnWsCpH3L/sLpIcOe60gV/tDKR+pXu474WCCGHwnTzZTRCXQ632Liy8\nd/Pp0iFf26B+m16KRQ2T0jSRZs1ITaavKYPFcmzFf0hmFb6cNuw1BVGAEGNJu2vp0nyVf2y7+atU\ntVXDh6umPzRzh2i3yUHjSFYfQ6UjlZ4TLQi8TO2IJwPVpbJ8kG+SKFws+b6wO6MWRAHWqig1gqbG\ns6nr4wsliFVvXh/Sh06NfDUftcn1pOXanPK/rEBBTsdQfEUwmRHmuepDABUVagk/JNWXAqJYFRcJ\nIGB6zSpqA/rCaJzHg5mlKNHSeOfW9Dk7AENlVo+2DTPkGlLbvaY6UcC702W4s9dT9es3BubSzQKn\n6sDuSt7nI5iVk7kroNTOy92SCfGymwEJ4VFNtVDb95+hEs9gYO16HVeNKyR4M5GPY7P9YnnutwQ6\nL4V3MckbTKnfARWaZHjbgVgjG+iqSvyjvSdscX9uQMj1XSYN+0asm49wLr/cDAdA+9kJUH2iuRy2\nlymOnEEmK+YPGPvmTitZ1ksTtP0QN05uALqA2Xu+vsgqsJs18ytuJO6C4MuOgzMTOrDtSgwXwL6P\n465uzMWYgzS4RWq1R7DKR1HfNkNcsWRZr/v4beDSsPPeavMNqyBXlXycXWeS9trG+eMuEHHr7coq\nTUWa2FQx5vyogBckbG7NqtWhXiaP0+5244PK/R7OZK3tca3b8jUzIbyhYXX7sg0nriyZjxQibK3e\nBUqfLSrWWc5ThwWcBExTk8JCovy/qnijbqQzmCtEBze/rE93IPeQTDBknQaXnadWonvrn5hxabEi\nHQKSagyd/wF5V6I4Za03RjJeqmuUC9aheb6hoVeCS7wZElgyqVzinlBCtEN7d/LvOeW0X4vNfrcc\nxDNU8DspJNoXEAMqNwOeMtZDp3n4NvQVtqEWjCDXyuIgu6O/BE7/AWTNoMhW817fqyNqH9kTQz0Z\nLdwYHz+/wOueZttUF7N7SLxMkT6SBo27K5cmqreNF0bRDTaU8kT58/0yQg12Fcuur6vaQ0Ld/liz\nSi2PnKnYAgNqzCYbcJn5ZBL4CbMItcf11yJ9u0B0ubTL3FVUW2SIlw7dKEj+7jUCParsTjidJQUV\nNhO6xQySjXz7HkWF9vHCcxsFUEnQDW1+pgnuRsOTX6TA03ulZsXPYX3Ur42TCqmIjIAHSFNpXsn0\n/yzpPRPXto74NO1hb99tAmk99aw9fzVGrZI6kPjZSdrfQweRIOcID4PhOwLyD3w31nOErw22dUBt\nPr+xlx0JYXtcYpxnCiOKZ/G9/WVWiKq2HzkTrbqml2DJCA6SNGIr+IDH2EwqwCmDHmQ6nqMxWS0v\nTn8h2dfivq9DNVOzrcOol2GIoers2h8czq3jc0MKuHg6yZUAfibPSo+fL4ckxfEIcuUcaPa2kXgZ\nZgI5Wo7N/6a1OcPJiZxLEAYtELlqYn6LeibdgC/vwuE1mLSW17/iKRMpFvHSuNF3BYnmRJm8+B8i\nyKmzfPix6R388OdQkE7EQYleA6xp/fIrOZ3EWUvavbMWf3H0h63n/0o5rFwWy7mp+D9SuK6SNLGs\nxKyUA41Ku0w8Mn2AqwRxNip1c4MvNBKhz9LG1HHhNbdQfzQan6dFdnrG+KjI/1s0Bh4LRq7558bt\nv1QmqYDsGXo+kcR4S7KAf8BoAEmvsUrMc0oIptn/D0pruLBZj16EUgK6rq5a/I9paQGDfPe0wpWZ\nrm/HNduD7k0EH48UY8G9p3yzC/y3KMzN7gA/bTHacow2JgCgAfmDBeeev2e5SBSSiT4oXJbbmM0V\nrO+/lgIwT7BIXGx3yKnZSTEZUXKhQwTslHtkaYPRFoIYjvtUdQqTzEXEhqiu5QZweaqpO2wUc8KI\nxrOc82grnP0uZ0LDLJDuajc4rwccvgGi6rfm6lzn/ReF5lNln9jzrH1tD+LKjGP22Qd8xkkoP5Ty\nL03TJOd9c/RWwkTfA4sL7Z1CGYvyRgkETmolpT168g+/q7mteMrgIgF+A6Ee1IbGOrPwSe4HD3j0\ndGmuWx7rmIdQ6rLqTklOoswywd4RvdZHYDXS6uZwMbFNWy5Q+0fEjbf4+qim+cqBlvF0XOxtoLW9\n8lJOlAWXmQQIrZlEiKq7Gn9NQuWBtmL8AbLF/y+hk0QSg9fdhqMg+r3U9F3y0Enwhy1WY43rxm+T\nh+qU2XaZmrxoxGPXIKY3zs9B5RZ3svJlWMXoHfEBgbLSFy6nM8wH/QekPNXv6lUoX6HN2L19biqf\n/d7Q4iVZrfjF/muZTs5K3ZPwXMfiVcyf2wygVcB7ZYXO/VokO3vVmas1B3zfmV2HSk5vQRYdiC2k\n8Q5rUdL02SDNhMmhRXQ8GI0z4XlUJyz8xm7b0ZUFSKCmg2EXsNk3fxKnrIh+/asMjrH4LWUf/bZO\nG4Js8tDgfcFjKLXsr9e2/UbIUD0DDirwBXg+ZSskNlRvw3YeDo/yH4mn4XV4HzQ9GXEXItxq20UN\nU2F3I69k2rRBmZOS6S0Ij0w3kzNroUdjK/JjU2b4EX9gxD7DAc2BTfTwl6IqvVV3+LawYdQ+gw4O\nMQpAjkv9IYN0Vwxgfde91MRZayH6D6GEzNIIc8sU+7xXPkLRozH3/E1a/YHWF7/LiCKXP1GUjTvA\nMeoTYQLma2dS4Bq3/JcQH0j2eFW+6AaENd+939OOsgMoeqbQseg58b9tfS6ltlUc7oCBGeQpReIL\n7io0B5L/j38AppXpd9htJ2K59BBlM78KU8P0+e+gxk6MLI+8BLlJWTp6b9aRDM5+FkNM1XCIOF2b\n/YY/gyDAWmrHFkBS5EYsMumyzN2L8+lJuqLwm6tSwY3dhp9BrRnfKcY5Zkxx/rE2o0jrBtqg2m5X\n7vIb6emHEs9CAPIHw4I700sm60cANFG0PsZaaC2QWuxnSHfoT+w2NgR7rZq8cPiRhKRkVa64DhL9\nIqfhvw2vVFpuy4pQFo/gzgaFV6S+vbz7Edv12fcddlLqCtZXCtrTapNAbRXTuKtJ8EJBlxlIFohT\noABdwieahhKqy9o2sStCh1fM8tPTsApzmZy7D83VSE8YtNdvUvr/EWsmZVFlAN/t/nPoE3rmEBMZ\nNJ+eJCN7aLzE93MFV72oFnaVFav4reg6iFYgp7u3q711gz03kH+VM36t7PGlX1JPFDbTzDWp3L65\nVfmBKH7VGog9qKbQxe7MJvYXBjST1djQrlByy8IlwAbzvGg67GK9Mw48REmafKsJGd1MzS1B4PiC\nXmAi7XSpQd4wR/yk2oi8LrD9JfDDxhpKW1Uf15J0aVRj8S7nmOqnvUPppAQBjfuXlbMaWiF1AwyO\nXzJzVhM5SNm5cY2gnKOdWIDnLqzUWYsj7FtBVp0M6Ww+x21pN646gaDJBOSHmNccPa1z7gcf/VjZ\nWcLzO0WDOQZ/5CuLjJcbPt77KZTVlUFMBXc11dACmAA8J1yr0003BdxrrILu2n0Mmwo9iDURuRJ9\nCADCfjYQ/cxC6t/wKDPvQoSI5GLsXvv+CvN9zYVhIUhj6Eg0bBbBVBsunqxGLcxWluNIPP8B4BKk\ncx8fhsN2tDxE4WjPUQwSMNvLW8B7XnADDEAwwxIklQfghTPAGEw3yVOA6z++s1l5WPU+s/+f+1CW\n+MWZIMonbtgHSFQQf9jjQJ2GI3R26/8h2+td+6a2B2smOwBV08nY/JY6qrMt8u5N/Br8CjxrBIlr\nc76fNRdGut7LoP2Jhcer/jrkxlFe7DksTxGBUOM5/v4WvBPQ1SBZGATjlc3/FkTPV/H9Mh1iRNFl\nX7b8FmKV05djOBkIs97a52VaejJD/nfKvySmhjHAGFKyXWbDl+KN9h9uoayc/01ujSXwiDGN9L0h\ni09vvo8ZFv5TzElheK5uWS9jXDkOvyLRkXhoENdGLEa0NPF+AxN5ox5dCby9RP6k9Ilxt1KZYV4a\n9WaNTsd1O6I37tzGArD6BZ8KUQ4DG6YCw4Bf4UEDJAVEoBTmgotKJD0kVfktgdzUBcojEEAcv9oY\nuoLrb00sBqsIz5XWrYeKRGGkXuGNPvwpHk2OrKcl6z90ImO4Naara5rwti3oif4JyY8b6huETNBE\nGhZ5JjQFt8JwVdDM+G7SfYNUkhWeu7qfUGddyoH1hcfEEpG9dlKOaIGv+81T8n7IrBGyBqLZkpcV\nqq+cpo1bt5PoAk6GK4rSDFZYecrAIvZAPC9D2EibFajGU+oL/5InGsBtrRzyUEAQbX44NSobNnJf\nqCih3PSazXtC1lYR9eiyra00BHcRnyQf2DdQFOAN6qjU8xlEMN35cCwPBlVuRa8/h+aoH/aeENWP\nbH9i3dQ40KPPawNxwCy4jB6hLnxw7xoLTlmXW7I60P+fUKn0x9m4VkUzEhYJOMjkbFIijAjE8vWo\nZWjW75JotHesY1KUjGl9hpJd/zkDvLSan28fvcwOtXZnwh2TmIysuqmMXinLTjJDvVlbnjUwad7Q\nMFFfexVE0Jm9JjO+BkwSzvS0MH1KbixbVUqFyj++GARARRQguejBLOj0wvJJkFaDLp4pcn/9IFMH\nZQJ35U/tMNyOX5RyzKULyeDUH6QQuJhrHIKqwU6iAAv8ym9xqdmvrUaqG/zoRNDJ+zCT4T9MrZ1G\nICbSUJDmI1mNO+G8zIbk8w1q3v3uIW7iLWXPoSALKH6O2wo68yksUp5hDS8APcTliFxDv6gdn/Mg\nEoOF3M9IiNEmQC371FJ6RhC4rYCLzmU65eO2bFkId+zJwMPZRYN6z4ko5ByDZo/nUUoJCNuLCrml\nV1zW4oMtBrsLwouHtfpbD8mxoD89xCeteNSzjDFPi7/CnU9QvFKjsnjWi7CT35P6nKJoy64yL3os\n/yfTltkC+fS488EdbxZg0A/icSCYSewG6fzIenzpWeGe1uyk3rPPS/p8RYcAU5V+dHkBjeDaho5E\nSxVlEnPEtU+Id8UZtocQD/JoC+Jy6J8y5VXKzZ+90YS5wAB0NFV1rRFByPVaD+6TvD7TGkhgEVP7\nrXSviDEfK+Y8/n1w//aigpMNiUbjq0Rqk7FM7Txq4neQu5QgwFaMA/LeXX5lnvAsZto05yNiHtm6\nu4NBfIhL14727BT6XlNHGOqSSg9Efd4TKiwwXOBUnGjkUNAYSyQXYOji/OUWKsUHmwR2a/zLfQi5\nuMsIrkLm2ga1rEZJ8QLSGtMh+GOELZjQA2AUxzYJZswt5vwn/YCYUqKGiy39aRmpgo3z5nlA3jW5\ndLcZBzkuD59ZbgSZAC7Bbi8mblCDEqKNEmjNO3Q3Glj2is6a+ynxbQ0oCGnD31BzH6TEVGxniQAn\nBJ2pnVhxDJtoW2jP4VLzRu5PKCv7yeIIgj6R8IU3X89PeTNt71jrqFtYI7F6sYR38Jpx11axwXob\ndlhirZ8zKOgLdc2wadGwY6ZYYrlLEzsby3ke7B7/DSCGr9ozBrnq776gf5bix9rXGYHPY0ZUexWF\n2ldDob8g47+MfMGpnAjeR3eHL7P3tvbpVVN5aDhQYqD5S20B79/ZsdfKioZpPkccsU3FzYXzqTmy\nS4gMFKDe6b8pO9UXDsUud17TAifp7/DXrlXckgwU69/lZyuWi780OMKZ1jjX7jSg9TmvPawYireU\ndxmPZ8R250hxXtJEYP36yiNMNvyMig3B075TryvKd5AXDRWGHLDqE51w7BCyWy8mvDghzNHx0HUl\no3GjnWtbK3JZfa39UG//UZItiEuzNfJiFq0FgqVx6TGrJPCeS69FoyX6a2tYpHPJ9HhkDFmoytse\nvfJl/WTb3epjHjdgdypnxW41jHbk15zguem1YZf+WuiMkZQXUXCXxoIi/Z7FESUybbkzdTFa48Yj\n/N7+rmRmLTbD++Ena07X8uv4klDtKJ4oR4AaXJkzDZtT9Eo2E8/fJZKsbcRifljwAB1fO9NHaFUv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871jlcjFqA/PLCEg3B0RWMtCu9d3Xv6QzdxYOnfIFE6yiHwai10O+Cyh8sii0hE6qqUpFv\noKAqur7qTAVtiwa5uL/kUHuzkdNVuaFjJ6rGw6V2O2IgBM8jJkyu1uH3hHDKi7Yo1iKSpv3ESR+I\nEmA4lLBT3jRhd3jq1oQ0TffDEGgaLLvrTxknTvryiebK49YyjR13kIa5/WIT9OUA9BKuav6sB61E\nbu74GoPd+Q2shZ13ySqT5IaD/Ietu/kxxzIaHS+3XuLFyxQpsCInykz9W4humq057zbf9ELQ6ocl\nXvbIa3VADEFZBXrDXefxsFnppCzmxyyEH29YhbApy+w39htYrv1Jt77Ud/Nj6gg7jQYnU/nbUoXY\ndA6QWolkilSAZ5iBB0XtpdJ4hHf32iPikyXrPIziCvq5JmycB3+51RD8sX7VdlWQP9XdJ3FV4FpP\nAoiLSLMKcTZ+vyprd4hAqbo0NbKBRfqTkF8qix8zrT53I2uaj9tMCQ0R0l1OiHu8TatrMV88+pkK\nxK9xps8Q/jfB5irYptrMzejlgGFqcrV0yqWo6tuwXAlWcFQ+0Blj/wbUocFjIE8MKfFI5Ia0tw/+\nJKeWz9FnStDsrxaCAP19sow2aXR8sYexTN0mBLFGcoVXLKircjko0Zx/7nLiMaHYNqt96250UU8f\nlkoI2OflhGUZPQCJKJEumsM5GvGhjeM9JG4Q8m/lpApys5TJSMggYkn/mq8eDTpJE7h7nvu/9kLY\nf4vaGSaB/OrobMivgn8I6O7xNamCYNPEBxTy16ASXaKCjj6/OqZjhvX10DokHR8CgbTwNrWJj8NS\n9c5TepT7o2wobsoYfVmDpSCXW7JUVR0IoFVWslyleZ/eqqiCMiM4Hdsr7MYcvBYcCLhtQ8FOPxq8\nJSrLbQLET2WcCUea9vq5dS1MLa5EXfgIYbxeWTPN4bi1eXzP6B6HVOBOvJhR6cv8QExmuZQ+URr3\n0I9kmq2zXfFmj2OexIIqP790XlAMzDHo+sheo718mEnIs/lhesLPEc/AbcFZ3F+2EAcI96zXQzKf\nz7F1Bn8W7ck2pfPkiA4LLGbNK6ya1Pu3K/5nGaGgcbsKoaaCRjKo2h2DG1sJTZj/Mr+Jzk8UQ80L\nzENBIslQswxiItnlC4YLfxJQxrYXLEifOWp5WChJoHgY9wnINST7VTyQ772KOqG8LKQZBSSBGGf5\npycd9ZxWYhmXWHfQuO+DuTjJlLdI54mox3teJIxBtYPrerP5OUTVY/NGYPce0sTQJN/l587lt5V+\nGxDsrJMxzLu0z+cpxy+GW4CXSmyEYhZhn84/+rjmYSYc+YPwxWQethneeAEbihSP5oegok6yd6pK\nMq3IwBUicnOchjjXJJBKATBKNylrmi85x85AC6EzsbupFlYmCjuHnHVzjLyoVilrSYmPdur7DIyO\nna455tBB+7mBNbD+pVwh6OB/Dwa939ei3Jcyt1SMLWA5KwJhkn0IAKT9w03IdDTX5H809nXBr0LK\nx/p8gDEWkT78WtXE09yLFUczL7V9T41J5iMGQYFprGHvzlL1/TAR0mNcvQyqtpieH5aCdW2L5Eso\n+D1rI8w99ciuLJDMv57DtDKFSEvJoEFa+lBAsLKUAex+UYZTA5oIuE54PcJAzxXSu+Yv7/SI0QtE\nwKmxI2dG1D5YtZ9RfjRXOUXWmF/1Pec3KyqFeqpsGlbqLPzMOpWdq+svfvE7vzCyrV0Gh22Jy2c2\nGuEWs5dK56vWXP+Q1lUlMJPeQiVQKWGDpPunEZybTmrmpnRdGp15lt1XrIcnJuBwixnbgUQBS7AC\nJlC3UKGPSRREiHgkaLeO7+RiI4TYibfI2lJq5qCwemUavcMTJJE+P+r6sV11vBuch0KGERwIDA/i\nTfmNVJyj+ObTwXLS3hbnX1jYU+4zOZMbQsstfu79SR9t1s5/VlWDjojOJQaUMMjmO+AA+s0Mn8uG\nTCjVIvKb9rhasrIXbSjL8z0JFOWPtHHR/Q/fUbFrQtd6dDXrK5752OS2/ndtIWT09LtNAftVX2ah\nZurqYC1IG2Vz9xd2zxrQYDwLOKbNX/LAJGqBJYD17+DGADLo2Gff6s1nQoiONG+lKT9XdrHg8dov\naSUapIPUwpqTm9VFfp3Eaggu8wj8H6OLEYAKFRjZP6TEN7RzHYPUZaxogIvCdc0L7HuhNpXIpt/J\nsYbtnuaKSlB3VIOqWIqu3qsnyi46MCYPDgqcXs4TKPK268+aO5JAG6L1IUCsBJHLGZ+fwxmvmFLY\nOW9gtt1XmOwaOK6OgFIKZR106K0BCfihC6P8NMRTjBt5aQRqu/YbrRRXym1gyhZjzlXCL/sqeoHZ\nMylmn0oDYenV9o18x+MAnkJpQgGsy9dVNzCPbx2biyu6xGmLFTp8ASt4D2RLBFDXbF7Nq9g8rGKk\nLFfD3OAXpgT5FZk4MBg5LY72utpP3RwiXa1OUpmX9ogX7SYldNiLZrgm1T114SfQ7IkzRaqg7eV9\n8Vfy/HMLWSu+PtQXw/5sRS+Pit5L+qAcH93t7UpqqLoZdTfLMgbiijKmL/sbpH4PGz/EMfdnXLvK\nQx+0K4XyOfTYMmSEXjIhkF2mn04rlduwsISvKQeeBzuet21oMAvjfNAC4ldbj/GKmm1bvvGjOnZo\n+oA/3c/cNxyaDBjjNLHDhhD3zlL3KomEt39gnXqPeaS2vNP1KJZcVk1FRviYn+u/4YxOnigKzsQo\nEBGWDU2a1viVAERxx8ZqCsx4QevxiasvJac5sHAN1gzLgQxtn84zsoFK8HKE/36NhsfHNrecpB3O\nT0p8YLdhFVsMWz2lkrSh1dF1iQwXSCElN8MjB3A/ecIqJc7rIVi9gv4+oJtpHktdhyX0WZ3ta9CQ\nTOtaMCAJEFptuAKWqLq/dIL85sdaYwDBqoeFK0AWD2H8mPHBUdYS4LISeyJLfczVpuxeTWGx6z9l\n81SzzDIFpoMDHdanWqbIEKLzo7yfwlEWhDhiWhIuXVYn7idZrtY51vaEzPGvA162hERvxLqmc425\ngXz5HrHz+5UmyGr17t5LXErS9rDmBbnmiZELTXjDKirqBJ3STsbwNNa4+EJetWRg4WoYCzAzZ4k/\nvj2u0GNFrtbAEGIN4w3Q0sbRnJXJw6+nZXVz13xLXrRVb6R3OTAZ+IxL3GBAjIWuP/oyRCax/WGq\n6eC7/WzX3iFqO1xXqHyip73yOJjAQyvlZuATUcDKdPyvAwbC1byIMmRzTjUdplNdTncuxMiId8pB\nRc+qZ2aoU1TGYx0Nn7kQs3hcHLUOhrcVifkcrsgLjlLepEmuw3JvU96H7Y+04CaY6y0ixdr4M1Zj\nxD6O+loKE95lVfICOD+vM4P0MiY02eok8vc1ghewZQJ7KbdXL2DDGXELnZgC9T53y2qa2xX1IiR+\nrxXJk7a9X62IjVupmLVyqLJ80lu4KUIe3S7tfWWPVjQ0NapfGMK8ZtVW7aqNUVXdyDuq3By9sT2I\n0LfmkuPeXdQWpqSpOOEBEIcFR8RsrQqXHIm5lw9goMfS6UQqDDmr5QVhysgupl0gRe4r1DyzRi+f\n3pBrYfV0K28ATn8OYZ031pfFmKo4TuiE9LZJfyAN1c5/B27mJ5hpSwOe+HxRE9Dx4Xh617jcZZxz\nWZY38wlpKJfazyEj9Wi5WOvpTHyeM7E/kYtfFRJk0mpzcqO1oUah88BGOWkvRwgy39nks3nS+OAb\nVwnSbYXZm+ff/wh2Fwxnr+02wrmccWf+XkaT/WnBVCz+vHcMctEuKRbiVlC6kD973ApTrawGe/UI\n/a5OGTDOUzd1628v10QlkLiQ3iJWj0L3PGS2B+M1nDwJjmOh04Dh/zbVaBGpHI1YbKRXJcMkRfFj\n3tJVm/gQh7p0tMaV4kMeknkW/pVhuhtWcpkpRbNhzrSc0Nrf32wl3Ev8xZFSuvbcDUZFB0FVzHUP\nwD/D/hyulFOOEHxulzx4UbIVcRorInajCfObFjDWHg0h/+g8l9A14ArAO07t0YM2dLUIww9Pf4mz\nBU4//bulTXB4++r/6/J7jIn+thDIzHMZWqX/F9DP3xsMTo7Oblh2J21pvW35jrgajYEmvDZoLZCr\ntztW6drP9zpcIPBjbLh2ZM1KTuu0xtRlaCZUmtqW/ktLyzkievKeiSuMypWBD/x5fbdvoG8jDS0W\n4K4GN8whnc5DwEHrVxAgo+lZUixi6483Z5gpfjrd321P3tZNvRsnoxeLjitQZv244xFSVOGkWD1g\nK3vVHyn+69/q7npBE/w47cJghCQKbOwck85pYwLp6v8pFucPZ8UP81hdjHluXgtTUyYGGklkcdVe\nSmlTwqf49c6yLOOOPiCbMdAb90C1o5ihAMvYJiRa08SKogr/gkh3y4Ujigpu+iHBS7G67LFWDhgU\nrzhU6Q9KHZvaauslnIGcNWgMBNMv/PpZMKHw47ubmGTv9TdK5cxheuNPLKh3S9vk0rtFK3xNVawA\n+B7Ic6J+JhDVdfrHO4bFMy6POqyTlLIj8a1L29yHRBaOlhVulWOJ9RElXy6naCLDxnoP3x2PKVEv\nmuJ5uF1yG9MxcQldB9LoU1v1cAevDT1h0o8gBkvrwlgCTRtscavJ42wGvutroCRmL6tOSnAUEAEt\nm2dWoSLGXQhfolSb/SBA6J5Wy3c35FCH649Cr/r2EW3tLWXGA47Npq5bYwN1s4NLNsZXQtlJXwUx\ni/9L1el42dGyLu0xT31/YqpPRVxL8rdQbxtLAZGXNVhSVhryeptPJ56jQsr3AR93mw9wkSzkXt3M\nfYeYnxCEbCaUrIeeT46TJts1LY2qqS9VFk0bsElFX0Khd8Ls1kSFHPPs/Zdpt5D6khQ7l33UgPUR\nfL+lY9YBV8+6H4uv06JD/TY2yOfJgFNtaFo+garspI3iyWKflob0wwB+KVJ8p33m/ntz1XBD28gf\nfYC9qJqbK3a6v/lPyF+LbBCV70U+MA8+uUh5FL58rBMF6CkxfuaJacLV5ZFX7xhqAUtndtmbMwhQ\nKjC1S/BzGJG6MNYVldhMdrLCoBozVj/tbRElgp5zHI9zi7b9v06JCqsZW7ZlnOVGDB1NnIV6cEp3\nvhMx2QiTVzSSXzy1VuI14+AESS5dNpbz2KV8e+IsBPQNCV5NT6tOCV6C6uiUOSBBaJchq/KcOIcx\n945wieAJ7zajUIC7XVJXQd3yHm1tRRPfYRcPk95zIKp0z9CCc8tV57uUSADSxLkugMs6e61QhW9b\nKBqdUkdMNln1pS3dqk7Fz/uNo4jD6Scy8sZd71tkyaIzKo+BC+roK7gojCjfFYz1Hd5IV7uTrJil\nwTMj4fFhnZdZ59m67FIluAJ0ik3Rhf07zdPli/y8L0ETuD0UbcQDT1rCee7SnO+VN/vLQ7JGS6KK\nspzOcIcd7+61v7MTK7z64hnci65mBIJi/doy5/mTKMPivNCV/YfACsEOnsuOO7g9eiwinCgFM0dm\ndicBCfQOtwocrRk/Y+TjEcAXFvqJjvZWdh7IlY4cGiznK3Gr/jl2+CXeFOe9uDYYSCfYpzIZN3Of\nPoxpSLaoo/NjC+GkQNyuvhy9C8cfbPdY7Ib1ycqVZvM/bpwpaRgc+73rdyoAhN0gsJku8x2PkfA3\nwsn6WGV0GlFOSr8dU3Poojuzl1hzbPnDSpz0I2sJswmX1YNPBbcbac8E7l5WwKyQLKi6ofxIofVR\nk7vBYQNlYb2BJPYV0gwRQzxa1ypKYr47wJHWVjhVPJZd8KzfkonZe35wnq0KisbhQTn8u9swGZpV\nM04/cR9yDjkSRr4zhqEsT8sJIgwnwOZT4XNjC/6xcoi2nKVdKkcX44694+T50u3NAqF3liGPPmUI\nkzL9VTMaq7vdfMilGbQiOTDcRshcbYKj4XaAf0LP7JIed1cuxKTkki5gueZQzfusg6Kcli/Pvoqf\nhq52NEa3N/RC+CfZhiUHuToVUhOJLnni/UPjo6ZIHX+6MCH+dBM3UQAqqnAOj2PtJTunZVNYb24C\n9qF3Q1dQhhVtaAD4C/+3SZK1Y5ll5ykz2GRp9QDPF5LyKWWwQscDEu8x42W2Aktm1ObmOazkQo8z\nPZ6yTCRHErFoW8iRab+Jd7Ql7h7h/OnYiRO8ENfChsA8AcJM2Nldcz8/stMATe/otVMZ6+4DVe7o\natBZC0Z9JDh+8HLDx9mI9WpuL7MLDFtiq2n1KKQ/7+Ng0Oz3SJiBHPRHX1GiAX5jZT4ozoyISmwd\nsl5cMHiQEmcJuZqsI590vlHYIsBWcjQezjuSHS6TZS9dObR0nUoRBHsbKGm5W82WgY/AqxKefxFf\nx/4L/7NT3x2CXcP8av6FD5DE4WZ+e8JNqC3ewzQMjQPs52dPVkOnO3+iDLXwpnfwbIPlFXGxmOK/\ntoc8AN6eZdeAy6QA8ME2QnabDvylhzWZTKrks8Tkt4lqyPQHioSAG8AjuplfWQFXj8Nxb05x0aJE\nu4YXgmj8alZ3rUmbi335+MStpfu6B5jIIYwVGjrGf8bZ13TLuOknzOlxbfO34XVrNoAcYHr5V06W\n0QD7yQle2UK5HJO7gb0qkOBdyTCPr5bnYMUA7oAd+R+R4MSR8ZMJMKq08/LH8BbiRcGt3r3JgyMI\ndO8rjpqUYWA5lqqNM3gKQmz84H6+6E+k4eKGv5+y8XBTjsLiCC5SF5frOGZ8vQZi2tCIstBVFxoI\nNX2zqul5tBvcbSXLNoiL8SPUvOKL/Y0bmM0Dr9I+AH2yaRD/1vz+j/yVhuMm8WqRLTLNt6AybCxy\n+cumuAidQMWm02m8pYcV5rDmispq+Q2fVz40HxoEfu2riqP85elLLcj6eGFUtthcbwgPauqwgBs8\nktePheXOM9ej5tPoDzmKWfxmxEj8nOFoBDzL3cU6yTaYy7hvd0QLtMzt980XSziYakVcxnnVS+on\nYYccwjV96d833rr8+/zpFUT2t/LgnE5PNccsKFTqYn1iik3Ry4KJgUhTQHB16WwT3SzZ8TH9y3cX\nH1TGZbNV7/wQgv/hbG0tX2sc2TeYK0WtW0DORJ2W5C4MeRIAp6OgN/CkyCu++0mJpfTKvTIREW4k\n0qU+ing9zwc24rV7TvoM24lEORpeNVKG2fHb+DwIARRUJS7SztXE6a3I/JtSVmvBsGiUCv527HDf\nSdKKrMjsZWlyr0QX0IFWlsl3zSoZAQFPmhKynaZw1+UO8eThOJY2jKsuGTRBr7gpXnGsNsJwC743\ncX1T5fQ3B+2hUeM7WDKc6gKZ92vJuUG8rmgi7/Yho9LRNTNwEu5I6X2QBo+A1r8ObSyG2kr527H5\nd3FTjs1l6LVy992OGGth6gMKowEpgqQmqRU1qAOYAjIE7LxfIwaCuXrBwBwYCnrhnJuKMRuSTw8x\nY/Q+MBY8mrZcNx++n8ET5eI5t6NKPKa3g2urfqVnOt7T75cWB8FaSW59s/+hXeO9GwSbQ/VSGL+t\n9vc5oDg09ybWlDeD9yKOmc0daioVeMsB2KrKjdKEDyCQ1BDJYAr8AkfkqJSd6IZ1ulBfURb5cFIr\nbuCyLrexn6vJcxLSCMUYaACw8y+5HO58FaYNCfz4mMY4vwkdn2l+Yi+jkibtOEXdVqHyvJxCd9T+\nei7SvFMX3EX/uSlAjp3uWg9qDb3Af1AIrtHWtO5nEDvRbkbipA+4xBTJWVJBjuC+nqV8LWfSPAPs\n+U3b5MwRMjSlug5YiBN4E1FnbEGg8tCXKLxznkn5koViAwRTPWAp+mmf7/CFVz/uqbmE7KPlNOtL\niiRFnkTzIPRmsZjGE3bKw/Z3HGyYquL1ZEbjJTh/+ECbeswVOvsiH5iNMyJdWCWb9Vi4NfUbTjgv\ngd58REYMvxVEO1Y71nkI+lLuRAl+dVtky+LkQXwuk+cukH2NvfxvZ1Jci7fQVZi3Z4ozvAYPf81d\nCNT/BWcD9LLAeg/d0vbYLbY/hcSejtWcUInc0yGnx9EogzYpijuOoYHYuDu8mWFkkmM0q3cX1DnU\npylhN7KhqblSM0gePF+YSUiCJLezROBz1f7xeG5YUghnl9VaLKEQNi0HtaN7o1O2z7fk1xDFFmWb\n0+MyuM4tf7BxMpz532QG3l2zv+lUOu6frdctIOSXQIJwakhMSJqKQx1nxheCmRusNZVc+hbdoU73\nxMP7OUHoEAC1zm0JvornIADXwHjydR6kYCDHIEU6O1r8F6m2iI1Q10vYIugScUhj5G0GzFA1r48O\nMTePEol8N75IchHTA9Co99QzbATol4vnRHcZtn0Hj7Q+qo+22EmVK+4/Zt16Adc3JiLK8c1lpHyD\n8qrIV0OSl8xAlKHOTgZFoQ2+nPnjmRsAJbxeZm41j3DLKvTSWBBUut1MdZQ6E7ES/fLOUj8tuEFN\nbzzyycYz1GZ1SXhe/VCgME2ytGhAXZVVLY2QQhqz5hDMzRrTCF5apyVv7QPFbopgD/Q171u6liAo\njNB5QbxX0KUA32ljaqFEuv4kNCB5G6sh2RcOFFmN9wufQYvVDMGqgbEgn7VexL/7V3XotFoIvN0x\n+04Bs1+rhS2YyVDXFlI/Q32VwvAO8OmKi0zBjIRk/sYImOtwI2+kH+KQjZ7TuLSxHGfRJAEqJkh6\naN87X6nSf7P+3/E885XiTDf3r4X3YB/x3Qemekc880jWzxsw4HvBqO3DcHdk/VYEk6QjEwtgLBJ+\nCrsqD04t4F+BaY+9Fbi7F5J9ClmNTecZ7+un3PYnizjsxe0XdEloBzPnW1ey1NsJAJEMo8iOWqxM\nUwWDNA98CSt/cReUsDBi521rGIqQm1EI8a6AzfwUa3q7WYvRX94SUB/mbR4/lYJ6cWjvkh2SgcSC\n2sqkHlGMAcvCMiTcAHONIx0tYYLEDR7luDrlgaAippJvVx5N505Ds9swEXx8WIcBfXqzcV5yw5GU\nAGBgcpdjcJLTTSUQMv9r4Z4ZKkZmZ385jmFVgvJq7Gc6ZMegJECM+NtZlHwkXhg6QmLOCw4VXWNZ\nKLCOWbn/PTXK6ZPo/tjrF4adpQ+6BhoyaPrbXaGa3UF+nRpoHubSttPybKDgejNpjDvdQqQcOXtg\n/IVpYWaZiDnHYsPgqRJTQ1ain14IEXWEq/yd//0E0yeDmIIPzPch1fP3BqwIj83bGYkGqKF7TX5B\n3utvXxwp1kXlXvxRKV5KmABsrIbCKma+PxoGOawIFPsvoT85SwuDTkqqSVjsmMMxc9LTq5IFojKx\n5gDD2nN9h94m4YLhR67iN1ZmlATr3oZvZkVFmRKF8VSSDpZYiuQlvkqYPg7D9i8s5JUe2rX/QDM8\np+fpDLCJmHZUatvr1G0aXSORPtPhw/cGUdnt9YJOxtfMzxDuhDpOebQ0zaF1SfsOput99oOrvn4/\nCGQ1v0Xa28WmpUhZk6dpoJYfjITu7KMxJ6m2d6kRD37n+bdNxiOzlTNVZh969Wcaq6wu2nRtsBvt\nYw7AtxD/MhwsKOKcmWzTsTQP/pyh9j9VdAoqiHAq9uMWFWnAatRF2DWli4Vn1FMflFFY/OCFPS90\nw8DPvlIdVNasXWYh6eCbBo5N+tEs09p24TSpMwPEuYS/DXQcOsCrMlpgzDaeSVhkjifPeMGycPyh\nRrYra+6DiVTTY7JzRvM8SAcYw0r+1Q/3MLkyyzSqT4Zrg3gXZDp8JIByZsfUqKDm8n4TPpcu5nmL\nm6bvwqWjNCAl9vbFD9/zVG7uscVqbBAjXNsuNHcwwrz5kuuSPXzjxx2kB6lvIYSWhocQBBMA/5BP\nkAW+DHjsp/DhGXXIwXiOMhsJ2dgJPQBmiyexAd4jiFI5FI99uDa4YpVE4wADtvdQboix+uiKBicd\nOtnlXDu9pNV+ZH+vxoYL/ddZE4YjgwFMN0x92uZQ2dm8xK9l9L1FddwJ6m6UWaw66yVAJ2boDNl3\nixtShrmuj0WkRSLTUEoDiubPS6V7aGL1xzTQiYmj2OFTvP+ZSuoQd8hevomTCFV3eMu9Afh+4T68\nlp/KrZdDR4Z/9oL+iaDxb0Htxn01l7Ewf7sblI5+cxqFp5Bo961om55q/LmhQAAqw0akWiYizkz0\n6xgQrIQ8XtLQDFEJdZiTCrWr6sbr92YT3jHn4kcO/V5ZJUWyGXV7b/uSa3IvkPapD2AiV4S1jqdC\nFbN3bTFXp7w1LpUD3ul7FxUAbh3gG2+GKYSAvCEoROLRvj6/Hd8JAS6wo4GF6G0GKS4Oz4nCEfvW\nu8sp47WkHeeU0G45SSxSJGzIz0TYRmpZZlJIkmNZ3+Z8zTefY2qyrvkA3gyXF/99vOMA2MgYkRz/\n5EZi12vgPxZVV8apyOopTcmrYbS692fDKN/NBEOJgZ3Lg3aiA5FyJLBRU08XncTrj95CMaadm5vX\ncfh6xkN8yjlITEhJUm469ANHe7RtPhRVzbxCIgpjnCgfhkTwRvK6LKUTX+JuFNkzP0VpfdNXNUJP\n9nHSzHFnj9kjV+SNs2lFv4FWobp4UaSdkUSVUlOZgjcGRT6WKwkk/1vsTu8TvvlIesw5+W8CCcUI\ngw5Ry61CiRFSWxJDCx7hujCSjsAfSpPu00AQHAJ69M6j9l4wzlhOI/3rXIYBk6aq/Jus4tAyPc/K\nQPuhyUlNaImgfNyTCV89Ddy4c63U0E/DMCRYARTaRuY399Wbw+H9H8VcJdpM/oFxSGIRe6A+3ZvZ\nmqopJRdB2xXn+ushBABUZ7xa2Z2LWLjVzfJQ5ZZ7kgVt+gXdEw2FROWmyAKbInfMKu0VR/o+46Hd\nwZ0m7U24tJ8GdxmE3fPEibFiTjfuAbjrBbA5KhBQQbuqEIGPSmqcHuIrwgCB1vEtOMDMtyeSNL0r\nx/0XpSMHp5eucX+BLPJn246e/Nx7YbL/IypjSgp2F0kRfYIU6vwiYq24xgwm70Vk9zPrVvw5Hgqu\nk/DpKE6KrC3nLef6gCy0tdzt+9rEu/F0usx2jJJQ+BJTpmLaQLh4IHXJfX80iggvI3PkQ0j5c5o6\nihfnq4ZqCNsXvFgYFBgdB1LVQnMCKPvAzGz1FS86k0S4TPFxyXghAOlVvAJ5iqICgxkKXAlUBvdl\np4d5A3oHvEILNWodBDPEeJkC3PpR6MPAPquIFyjzPC6SwUg/BaLRBu7ML2OXb+/OnewiFdJVOCMK\nYwg2XaCDZLW5ukfH4c9xQ7mp5lNV3xwCaj8b4sz+b3+mNULe8idbFY7kEtgESHJ4TOm7CBjNWl59\nioI+IuEbRR6BF3Qw81HmX3wuERA0E4WQiOT+kIrBniXmpqkHR0zOsqXo2gnKLHtsyJsVYGlS7nLA\nIi6uiVh1ZXFtRhYs8oQz+EHSCtKBYcH5nKAZ5HyHcAFESdBTJmeOb6LwwYVGf2ZhvaPhzHsPdKI/\nM62NTstZEAG0mIZP352UQA/ImSufkSOnGs5mD6Du92Qh73II8F4226xyPTvgW2TzSv2b3Y0Ulmlm\n/kbQrviauSC7fjEnoUCMJvsDbt4gihMgtMvJItu4ON9juWBom4NbHYZQRoWUsmItTx0309mjSv1A\nctPqO7EgWJwz1s0G0zqQ/o+x1/bW2HplEmTTSehkKIyVUgFtO4FuBgkC5dYIp9BGfbslo4vrxPH1\nA0EYsCLTDilWSK6tb0UO3I7OFGuCd3xzg2lKPfV785YYGdI9zsQo7w17K8XZUJLi+03ShwWIPQsQ\nyJpnsX10KQQCRIXC0NLA1PKYizN4wqjxg3blsFOgw7fHckaYwBJF5RQCyKmnM5q9xluKZBJbCd4P\nU3S+O0R8WZCemcueXbVLgYNznld1C3NKOTn/AcqkPBSljz9VsCKVzZTdE/V8olKnckhft2mPoYLe\n7QbFt1aw0DhdOYPFioPHogH0ssaLrHJNJGhglOWWBMohbbIbII8oK3UqcjnAKKZDvtoIJE/V0WLm\nQITHv+HEMFFmq1NvRwd+ixXAOdpyVk4ze/X+VTE69IwP1AjTAGbSNe45m0PNaz3geI8+ahx85P3x\naUYHvU/apnchaB/TROvjKI35GZF4VF4ajl7lr1gR16WNuUDZWAqnuxYlP+qHf2uzmFDDW3k1O92A\nhnYg2CVg8oEoy7Yk0z9JTKEMySpUjm+xWtTNh/c5I7qCwqK80sKBGwWDjFTGUxS+8WZsSf/wOE7J\nInUNW+2hK71wx4g1sYorE3573lWUetHBl7ZDQuf7Akb/ENtmstfo9Daqhy4Iwpp9Qi/YWYUY3NAA\noMfw93nypLzf5UMfYkMQgjPmMOEqYMAuDLYBaVrdkCdJTY86VcqXjid8KQKUwDOPtvfXAjFMeA3M\nHYqq3qmbdFNrz619LY50PMXC/+65n1GhE4r6uj4Li1d8KQKB3PqPe1b9ZVzS6AIvSR2THSobwmgB\na6CU7tIhweDTueYPM0dQT0sqs9d7xG+kqY5JqidrzlQHRyaqD/1l0IWF/zPIZiPC+j4Uqlj3Yaz6\nelnWW+yCN62v2JmM5SshFUi3dnmsMUkVLz74oQJp26yw4kwfxiXQwb+/INT0opszwcs5sDbfIeAL\n49+g4OTZXtGSkGX5jK+mtIorhtsb3akmf46N/vKkfJ3+N4Im8EsHtZumWzulKBOB6Hm4ec2OGi0l\nSB6K/NxN3o+LFh+WHuB4E5uACR7MWoF6Auan0C+8QbqGfs/ra6495ltYhmkqQmOoEkJocFSFz+It\n5Ev+PAgctO6fma3qYoqfP98b2RInXv3Auyood4QehkrAe1w5S8YtV7YTpgGTlcntA1f7CSrxpg5D\n85fA6MjFXLaJjPoozoYZpOwHdHaCk+0L/CzjMpOZYaBCFU6KZSq1rL2SRYtYavSOLM3AxhzOihnJ\np4+9+xzvzUyK6X4I2uEB+bdaba+ySyKQs8LczPFs2zRFgGGVjaqrtYkGKl//TRez6a0edWga1DdQ\nWNS5tn3NN8QyeC0E6mhkckrkwWNjH21TeSQ+M+d1xEG/i8rklvv/DkNG786ivYszwNk2K49Zp/kq\n0Of1f+WmLl939Uvw/cT6SySdElIHWzYg3b5MB9H9uzOiiSPop370viIc6mDq+1rfn52n2VkBR9S6\nlRXKQ5wSTbQ1AzfRNZJwZYvhlcUh+Ml+NgA66d3VwKlLl3wNeIglQ/y/lhy3l+CVz9w5jGdUFmcK\nlizl3vdBXDZW1UGNfL28a6KZrYo0FAv3NlhVLRGNRJnhrKYmcz4l2UdEnnl+i1Oel1GGVo6k1cDs\nASf1h8RNkIl/m4kEk7+eHokTuCOuiExyc7Q30DnSxoQd8GUDKp1qxfv9ZXkZzSqoLQBj8hwm09Ff\nfXe08fYR6NWb3fT06Wq9N2aJbwCmtxba6ZUoTm52Tf1+nDz15aZWGVh/9KLAJO0FtGtvrWE0CHIl\ndh8aOdXV8mEgI70mQvRngmX32co49fY0/SmH57nerLdY6f7GVtqAK5fDnJanP3YdzCqYxLNJ15BT\nVCwczeT3AiQuliL3g+4dsbdpOpPie9rHUw3WiPdU1Lt42Ku5+u7+PHqXMbwJRey6lX2UpdCcvsZS\nQElLexV0caGBnC+N4f2niZlPTg0cTwzw7HJp2xJ0uvO/dEQDcK6Nr8WUyWRPC10wpP/ZsPSj7jCc\np/J+/XmfwLq0V2RSzUZCvly6Aki6yOIScbvC3U6Agdo3oacOzkfrsde8p9UPjDj5tO0D+eEk52Fe\n261a0xJYlwm2W/4SppeiKlhEtym8/BHT4lXmewV29cZnHczqK5Ejri5yjNEajgc5RwJVKla8kDtt\nAxxCd52jRwH6kBMl0l2bIzP5zD8sIy61+xxKIVfEwPR3O/HhWjhbRrLtPgK+r3MjMvr/EJpHahI/\nB276BCCkPagzBnMits3xp5wFKs/TIGyBUw921jcLdX6sMXr3I6sHQAqqsc5qbHi7EDjMaxxRjROt\nQJR6dIxAaZkfIixwFIcxAMTFRIf5U3Wmqze5Sg/LSTgyJ/5Xp+5rNd9wDfgA49pH/mk3QLqLCuSX\nwyYn/H4tVn6EG8oBBTm4OjBuQrtork2ddn98tKehrMzPeU8kyXSA2QT4vGEkf0+NQ69/P5iruPnX\nkcLfi50Q0Kp0ui93TRIUjWcI0xr/U1F9rhMzYslHMs0uH3D2ceQGT3SMy8bqSj7w7iLAj8W9fwFJ\nDHFLvbPU80lC4gD+a/GQVkdyPS95PcYL1goNlNCB4D8U/oSFzeI4edgdvjPdnpWiwswik0tueUUo\nIO98WIo5Kf8yV7ha2N2IhMW9byOFFYXDvPL8dzdOVsTFwmqka+oGlrWgV4wQeFtXhSEMLtKd7WxZ\nydItxn1BBi9kNCTdzBJOexNmfbQ4Q0l+uLFAnGvTi5axi3aUoHxLhdE5NzGbTIiz+Jv6rr+0slOE\nArpPi3XPCMNtg3c0ToddrSr1y4c1y9HzgvFSqsB6kS+RTdoA+smPYSVU4A7zOmiaCTE7lobAEmxv\n0j8xFlnlu9lJPjBZvY4viDSendYvAt9GrzmrNvfDcqbg4b8+w1haTwWH8o2vyc5RYlk1e7ZsZviQ\neWLOfpl3CuJospsaUCaIP8YlXQqruUFTC9ruFFWWA+idmXWUh1InXlzDWpU8ezS6mNc6/NRCzH8W\nZ/5NrE6BJaZt70b5N4apO8ZCoHVbyxdi6AiEE8UdGXjCJtf1a6Nyoknqk798g0hxLLCyTflhCWel\n7XgIYL9xpJKKGOWpyle2XzkoBuZRuOOQ20Kivu1gYZ67ChZB+Rp8va2/xXRdZYkblLjldFSeshvz\nP6lQnyZJ/BMp+2XNdsByC1+ggcPY97acTd7P1rje3tsi7xQJ/Y5wgbo0Lpz0M915bVlgRV1CfMMN\nKm05Wk9mwU1w7FK3dRqrKOPCOs0E8Sot/zf0446pM+kUrAdRVnJAjeICEIALmCESxjMmSmoScZVa\n0D2ZBhqHk77e3dkyPQgNTakHABXrhjrPX6BSOASdscMgMrxJQAa9I2k0U1C7j69Mv71odU2t+PWr\nMlv4gm1qw+DmGgPtrUtXSQe0If39fDchQ8l+9Z9bmqv7QMbimLvNmOYMvSDeQmMt18okM8qAGt7u\nnjux543I2fhZu0FYdAqV0tgUhp0Vxi7oJnB7OyOsENYcVimz1/eHWFjC0kHNgud1cGXDjgGlU4s6\n+wQJXgJ5Tkhdqf9JujhJlHfzwz2oYMFm1TAQQfdnepIuxu5yHULYLAZHbaQ2sgUPu/d9Ls1j7hWC\n9khWLWzoueiiGf3U+BTDyjxpad4HyCkC+vQMpvln49dbfyQGX8qyjIACEwcpC4A4mFe7qnlR/jTZ\nAOk64H07UytvUm43Sg8zHa7zD1Rzi4efkGbNHtKd9iA4SzcbD3Fom/0iSo9VSVxHzqeOfHcOmBTR\na8+iXYCD1pDflA2Ah1M3cIaX4eEVmoDbS7WKGjPpjtAm+8szTTXVBO7drKoMtMsLd2cHbibTuDwt\njoHQ392iWxNDKeK92uE5CNpmfEPgLeLm1BYyFoXGt3R9BLmI8qMcg+BDdu4dQPlzri5rIei3I2+b\nL+XYHA91AVZxDkeN9st8zm/g9qfLamzeRiCQcPQK4y4NYlcVA6Tu7Nx2nMWOhRv9od+xDRcp3P2Y\nBO/9u/mMiIxJaHLI288Don9cww6jExLSdxto+E9hmVwFoQS5frb61Pmz0XOQhdvEC+vayTCnmYXm\n7ZI1qL0OjXUxQ9U731W6jkrPD23Aum28wlWW7Wlr9uB99DrqQWogbaCYgctobxAYvnOw27lU3QlP\n2zPoazPjEBjy/jS+oEsz4hkkStIov/IvmFXYhmJBwjQrjzWN4/RujLv3xpAxj0RlmEHUULqPYCRo\nWoKfkQAuiGmtO2oCQxmIw4i2v1+2Ov/0wKfx3RA+eZjKlusriN3uM7vKHqJt/rGTunNMr+xf07uO\nXyYjya0M0oY6+yAuK7a+CvC9umZeFrQdg3uuxtvhk+MfFTcHlk5phnADbQOYID1fyz2VWR2KQJhf\nhIJUNPUy8t5UIZ+8a28xH+3X4lO5gy9ikAzkST7ulxPU058v98Jyc53e/LkD/xMHTO0hRRTenOuu\nbNy55BLOap7Vx9SZ5n3fPazSt0+XCsSWyp+Zf8SqJeZD+gM8tFhutLsL9/K6R4v3FMABj1OsMpgk\nBH3UAlP2uxlg3JqCr2+WMTt8bJTJTfNnu3r2O3MflwlKzq5yOob4BiNEzYx15eUGVgbKgC/V287Q\nmbHBc06vvrnffJZYjX3poZVuZcz6MpyYOBnWGHMbPrhm7MlvPgiWG+MSTRM1Idsced3yfsYkjMYb\nkEwVzutX2ari9AOeUc5fOezVyAmtI8oRHw1wcFfVZ7cFwR0J705aXTYU4y0zA7G52Jn1jRYb1xft\niwc9HtqHL259ct2rL5TsrMO6+/TrNqIDMgBYeMwTl7hlmy5Xl680WdFT0FuJHytqR5SOLSaiI7UA\nm4fX1HBOodGHC4uy8rIVvGJQyYJ2+vQi6Q9hx28btIArbwPAFvXfyehqsXxvBoSa1qVTr3erDZ+V\n6VGNggn6I6CPt2axGlax24mCGQjkR4UcplLZENRaIt8BRUNBwvDfRW8/3tbTIBTCbdu17RYyoBQ7\nu8NToHh5lwF79Wei4Tj90GjNtl95TmbjJvKS4cxAiy7wzNUfuiyURew4p8S8h0tLpUcD4iGjh8El\nIJ1qUhzDOupPvO/+9Ysv/TzOPlwi8mMm21ORx13grvGrEzF1TxE4UGAPEg1tXr0G8qjD45933mrR\nkPydFDVqioyFLHfLyjf6xYwl2zds6qvL/D4pm75tfIV0mR8YHOkPMfSwc28kJpV/ahFJIzhHo3nX\nP454IjGkaG7kIaNEivrHm6qE6UA8fwZ40ko6NyW6Nggi0X/dMRBSln3SzLgSaiHNXmmn3eGc4uA0\nJQ6aKfm3wpuWr0qMHzSFJ7HTbxUK0IEZxeKUN/vFirazEsOWMxtiQ4Tjmk8dr6q/5977nARafqnN\npwwOvWFUDyKW0snNoiuWujAtX3UJA9VCfTnIRnmfCfawWT6Du55JS2Qy1UXPU5Eepdyebn69CHyF\nUd+mrK+0cdc7x6KJYvB0DZHsVVhbMTEOqBdG4HNh+0D+REHaYJFVSVbU7FR7+OlEwDumjbl0ysHj\n4cQ57DFO2ibOHznZzQITIIVK9cr0YngqJ2mg8lzdoWBV7YQeXLz10ENj7AzsOqaG1suBf4it8HFf\nZ9izvdXWEb/hCKgFdVAbbdtple+nuQLICEbpT2UKj2D2GRG9dHmTkhXsbUfKfPeWLluYr867ZEkR\ndRPWPMi2TJ8DvrBgdOf6BTnQJkBNNYJ7IreyewOEkebnyX3vwtaKvG+mwbV3JaeFFo2TZE/wyLSv\nGxGwFBoGdjgCNSi+CuyNii9j4IvcJy5ELHq55WHVM+ApQmcNce5MR76WIO6gHBHlyZWfn8FpRqal\n3rS4o4/nGWwlyGQ1eD9VoqIoUe6Ra3n+lcgtYYFkJheSXOSKk8NnLCvl580qoW5FjxqumDE0DZOF\nKMTNx5rTNtXBOrj0vrZms+kyBJY4fummd2GbHj5KfHp3HGO0eUQim3knVh6VgVP9trB+OmjTVS04\nCkmlDmlH4p1V3o6Tm5QRKd7Ets9TWJW0X9iKnc+7vkTEq8eD4ltvdoakJRH8NQR2sz17zONT44fM\nu/zkiHgNA1cW/aBFl4hAhasfSGzJmvcFO12kBUZo9hMuE2RH24/G3JRt6hfr9YRtq2H8cgHgWUQe\nl+s4Y+la+JQ8GeZuKwSFrbSzgpJDU7YGslWVK4+WLYDrFi+vRzLr3lZIYb89VlnQzERvLx87D/X4\nvim0uPnsxXGRnNuqtHnMBM2+qER1/pAxNr0u6A5fvr1LXdD9Lx0rN4pzozuBxQBxCOBty35hh6dX\neayf6n/2yR85Fqz5hcFpy5NFKphDbnB9u6XbnIxFcyw3U+La4cIAjV+ktGdUYIvbGyFOXnsuONPe\no89lECRq7EstPPAu4Zh78esEsNwVXKXjrx1VPhhIa4vebou8ROwjqIfmAASoKxcB7VH7CwKqyctk\nNQazxj/0vkhsuDXi1loa9UhibfGI29zNqNxDIh7AphdD711vEslJTBUPsm6cWPFKGcWobXlUKLW5\n+yviyKcEXx+Z0J6+54smavdkFZhRZ54sWoDqU4DUd2+DaO442kZHPdJn+1jIkqoGAS3YED7ech9o\n+ahNMGMtUJdyFcz4npTD+o2l/QcAVfi8k43ypc9U2BH6GldWTW9oB68QGRBKxxNnp85tpNFDkeRD\nqn8/PXYjJ4ukvbSKDTCv5S8cK/i0l96TU9qq3lfHBOu3HGWvtZBKbXbVzxQG/33Lo0GaX6XZKjff\nnM2ch+teuHLj3ahOyI/BylC/vFjnNBC47ZncjbYYwWQtHN4qA3TCmJjCqGhPQESTC5Zbl8KyTDrU\ne6pYkr4BQij3EKjQkU6n5aEcfAawR2DH5Wv9HzWWSt2b5Haa0ZQW/AnD3e0T3WEPADoDINH3kiFI\nsiWk5cp5WbAmPwwdEmAR02A2UetOn94KR4rsJf6FdtIHUUOZcEc5YEzT6w1ltFFv7lkq0pZr1tVr\nUf7u4PPkAvTs2AOiP6J8GKBCJFQ8gYwrxF5BdHNoMJy2CK1wIrUzfg6ohJ8FNF0+cw4YuhXE9DL7\nug6fy/VyawN+EPyJ/00UF0c7Y297W876yX8x/1m1io9SsvWd4YktO97/E/0VzlONz/X81DQjwoek\nT6k33di99/rC/GPuD4LBW7+vkLApvAoK6I9qq0HrQqbZGeZKzZ452PE030WJN0BDkPzfcPVpWEi0\nFDmLcTD9BYSnBhiwBw2WoPsYPjazNAesKjbEUgIyL+R6Rmi7RbBMawFs31GuAMll2OVBihEqYPXj\nivT8D8ejpiXOqSfDTr7TsCUJj3uDSwAU6QJyI+SHCDyceDR+of9tSm6pIAWuwvG9IDwynBGhqarl\nQpArcXc6Rd4tLa2jPByo98BuBusA/V0kGFxvWzRiXOuiIim4SANOc+OokAElQQ3iA+uy+qBn9TuW\nryVRp/im0Fu7Gky+10Hpa/m190wVdqkMo9c1Oec6JRseGbXS996HcOZI4lCx00xCCWqePfVuA5LK\nLtw1Y8egVN1gz3jtjL8qLC8cxdR37vMITBxsmV65eGcW7/+T4Ioy7Kk1quQKZsmKQaoDtBc+V5Pt\ngBUoDETrtNxwrOH+KNYTwmDwqAOVZ9zRSUF+hlj7FuAfMFO301kjeHV26G/IScnnfA3W5YzmQTPn\noJk/6nIPlMPUKuk2A/lmf+IR/bjQjltS6vdgQwtRgKCwE+r/19f+rfSsQCFCPZKD6vKP2IfDIs74\nwJ7omRN8Gb66fcxa8kQxDZ325Xsmigw4TdesmD3UERSKf9WJB8zZHR7dAWBurrbtzBqjlwzZYzCU\n/ZojmJpesNHpN4RTFsyWjFC5XZ/8HCNHldMGntm11SS21kH/ixF11UphYkeplRLztvbmg+3b1T8d\neyIgcWnqcpfWCVhXs9YsANSahCdMixfvu43LSXdY16Cso7qGWfMelBZSHV3sqmEeCnQw+C2OyZAN\nWT8g8by0JkpqKlGSJIhdWDylFLhQICxfxnVh8BHoF6qY2MP3DmoNNn+3ZZw4ihEuzDrIKV8Dq0V/\ntWA/w/RNnZhCkRPDbnkSE3eoUYUEkGLcgapkv5C9nxhC4y9yAosLVySqIVmDm/DuvKhLYlUZMTjF\nfWOeeGQj62mVz/D4IYknq2gtm7X/I3cgx6iWY17EvENN8m4mhUUoZFSCx64AJI4dez+uBEWMmzd3\nsA284+B79XMVxXOK2ddrOVjsgmm/xJATzy80tu4FtE2gy95Za9Qrq2SoF/Rp1ey/mvyn6O7GYiBu\nwLovNfbU1s/7smwAwe5aND4CLvGz+flDcQhbQDCI20iMHot6B/vCE73eErWiO/m5eLI3TUbzk6Bx\nyB0PnpNBC6Ssbo2rQQq7Ebp3W5wu0Byn/qVrlaHW/ugCcpULcjNgIDtbfg2HQfnMlNq9s7c5Z97E\nHYjeE1EMEKv46MlMkyUG4WzoOwQHfOm8QiUwAmhLnXSN+991m98HIt0j33GnODynzlDZ/399/tN6\n64lk2GODlQB6lao7ac4KTi6eXDatd+Tcivs7QjtZ9J4VlPAozOI7nWiNlQp+DozIrICikrKZxMvq\n0AJRkXqW0v8u8VtZ/v/PtFtAMTmkthu9eaO7xCvKswwXAtVU1zRjp8jXI0Kuh8mh7cwXFUqMO7cB\nCvCEYGZWQCITvg/G4n0/yO6VHa+rpUOyaSZZBYj3as8t3QSvDfd9mk05f5I456+iT6tkdwXFfoai\nQRojfMqvItrgROeoz+fuHVz8Enzbp3y0Wv3lmuEwMV/lfempDh9Pf/CK1/BRFI3EO16AsS7KkpEM\ntdsev3/V+p54ZtobbbEZmVV1zrDZdSKXClm+CjKHhyZ6cYRiW1SHBj2kmw/IjfR9LZzr+yTTUl9V\nBefljGXwtRc+3nSYmsz64x5N9UDz14mvIwy3Q8+3UbYIfHHxrHbEV34bVGpJ+gMIUzARrXMUIg6V\n4dChPy4oMnOjm429O0V+uaKkNIyGN3sXLGWk1hNAl+mnxL4ZW7/FRYz8qlx46JOnrZ9ty3lK/Agz\n/Fzgmtz4ElWbXFo5eZsdbE2TADXf9a7W46ZyFHOHLvGfKpt0+vFX6DD53RPQRcq7Fu2Zcixd+Xoj\nzH8VuqCogv69gYHO8vHFOE4tKHcZ9ewl+WiXA+G7ysHA1WkOvr3DQ6L5X0mr0L/+MEz1xY/R8RMy\nBI2fkhNgJAPjdy+UZXk/SKJFFpxzAvngE+uECZK+1DuisUXfpe6siFQMqxQdviOTreRRk0AuByWr\nIYyT/1ROkMCAwEr38lhNsMgVw/OeD0MZdg4niYYBNnNsFzR7Ru9pyudrb7M6LO2wqj0Rsfg/lB4B\nOFqANV/VUBlAkWDMwqJPy1ExQ+/T2zgG6gCXt99P+xkVui1plnTqcnH/y7Vf6VvNXn08+X/vUfLb\nfydS3Pd1miY6M151tTrM8b5RQBaeo0DadwHYJqPhAmtswvHtIb475xF6+2eQyfgkPy3KLzwqMc2q\nKPidclRrg55apLaFdWhm7smozPzzByIm1xugStw5Ge6dfflCWv/DF0j8gFtFmta1zu0SPCOiJ5YP\nPz0SWHlfuTWEOpx58ETbdMOgV8lz+QlSAGIRh2SihHjQNHhq1V5y+NC4M7YULxTs8terg3JMfMRo\n9/1F08+ZxupKwFdrNaOOtXWpU1Zyyo+YgVZfhqVL565cWIc4SbYL0BZIziXWq2Jr9uYn+IxuPp1H\nHS1pXAE7FEkDuOi3P8Uz8AfxJEye5KNSsSCpmGABQCxYBmhSJ8aHdNy1buAGam9kKI7d9X+MwcL1\nfalFKWqSP0SRR9yvy0bsTxbocjO71zEyG05E6xE2nl/po1IfShxNwNkTeRmxB39ZrfrkTgQ1q5vp\nIutAIbqfGf22vdxAXKb6+29E0Puv78ia9G9fwDkX2oaW7Ri3cdfMyPk+cudkV7nStlUV0SP2QbnN\n9jcqVpSmW+M8MGcpJqzxMoBeLyB5+nnehFgY3gYWGQDc/6F/k98m5UYtYUNV3uNJtSNky7b9kjsH\nDjqjc++RBKH7Oq1emXfh9m75OJ5aCJ5MkXE4Rc0amuI7850ElXt9FIsrKVeY6czQzEttCn5Qh16L\n+URy1A1i1FRh0oMu1okRQYAeeYHIkCoEMnIya1iYR1wM/u2K5VCU3hLLfLfp6/BMo7yw0CnGWFVH\nUa9r7tNIKhkyThH81t+uGMde0Zw/dOtGgVpe9kYs8mBhgtPMFBDQ5fMtRp1u8hUQPu9XeoU5M0Mz\n8NJQ+pZJbscGlMmfBhocilW0Zua3o5rS4a/JldI8+Dq6dAu27/5//M0fQ8jQ5qJ5OTJkuL778xmJ\nUNPF0KawwN4+DhRjpG+xr0AnN+mgaFT2qkR9C/+LWnI8P7XRLlPr20VXOuvRWm7WRQ439qqiOAId\nL13yUdSev0OyV6fMAbUC9yvljeXVJWaIAa0aM8kWjmFCc0DDsqFTlSxId5zGQFwzLBKhTb3e7dr7\n2qWrDBn0ETjV//Ru73VnqosVvzVrPZ8a9hkTkR/un39bq8DiI4IMB0PLbfh3MCBYOtEXxAoY7dna\nllbk0YG159jCvPfUNwG+lZjTh/G8lxY27uvuov/i63dHSRjKLfKXmFgpvlKYt4VvL0I3bSR2gyCu\n8d3gyBFXn7xS/fyMVHdUsbYBUniMMEH5S2GHQkW5wyNybzrBW97GY3gV/b+mIKRd99FQF9LEgH8v\n3qCwISN0w1DFvvp7GREpNEEYNOnP2ugtFdoOc2gJLbySBLH5eti9JiqfPYB6lG0QftAwU+RQROYU\nndQzdaGbC1iyGnQQgE3YEkJX0i0g+/mTrmWQL9CcYBQFc9m9mDltZSKSmrYIxwoz5HceSqLWCAA1\nXspWPVhrVSY0TuKNy9qc08ARwk8LCEIfX7X0sZfIj2xNjKPp7r7II9gq1cI4zRQ9LIbr2RCq7waf\nAhHbqar9Xj20TTYrLxDzxlkwHrMeikIuU2nDPjsqijOTyfJrbi+0s3EbI0MgeUdY78JLgPt4HD1f\n5GKJ9p1ySyUcfoFGZRPtmWCbbIkfo3SixtzpvNe/Kuc+9dwOHc3ljWNi9Dzx+RgxfHJ9dW+k9qQ5\nZlf2bUYqOF4r62+PhoLb6P9+YY9WPHj1ksNHcJqnmtIvYe7L7kb94VYtwv0RR4U5WFCCV3lOQl1m\n9SEr/j65ifSSu372W8hLLYs8LSOnYvgOxfVbM90MW6nylNCZ3jI5tsfteft27fvXyEW8VRf6yTzK\nkvCc+71TOKQTDkhg+j4l6PKVF6uTHaF+UBFEtnP4IpsjSqyUxygXven4TdZPTcn4inTKVX71sfdp\nxyNDrVQ0z3qDl/4IkM9iI7QbC+7BTNPBsqs7a3A4dXvfsMbsPi95vxjACIBKAHRRl130ABbrPqQc\nvPsSNMjhLY2iZ52S6Z1nf+RzcRrFhkJqtrwbP/zjEvxqLzcQCCT1ft8FovzaGkpdsxrW2+mT4oIU\n7dcbQkdmBBowGHvClk80rnU8W9oCQ9hhC/P+3ys73qjku+ocfP89RuNINJKgS8qEzggQRaEhgPQS\naRkGJUH8WiXgarsgtc+tHvN+pKQZVAww9EHOLeJre952sebqd05EELsUKzAUToe6rY8bEbAfD8rZ\nzZ/LNLuWJJbfFAdVahesQp7Upu4NatjNi6BwrDTDh9uTTUeF2Rsp7p1+J8CibT/bTSfPmdvRXvqo\nYotsnTnqbcFmyN70fD/LaCe2hF02byJX9zaV+Fc8yj/ChFQ6wY5wAWhYbMOAds0+ul6xDiSk2rHH\nAXEgLzkXLfHkZPzEFwZ3vZcdwQgCTO4KOWsxsUGSwu+gQjfXOcsrvN0pm+nNi1ISRXYx1ymYVxqH\niy7cTu5zByEZvSUTrNXdkuBuLuLI9bFrkTeXztbu0+1vXE7q2DS1cS6itHVHv8lwN5g1usX1vtmy\nclAW3+NU82/jyitcCDe321GLC7etImTWiALs3hIzPrW1znYLFIG4RjmY31K+drNBojTTdyzZLYt8\nI67cIkw4559y2DlqfSFZy1mt5fX6XmrIV/jCZ3Sk0C8SOYtbaX2jIwiYra+9gFd8Sd7Yq7Xe4wAY\nOfQB13pvwjhjx3HMyGatCOELxLe/gLBr7+9B+bAFehqD82INchw/6UQy0SV9E/uSJa8fCB9Psj2e\nf9Ok1xVZIdJmEi2MjgdEUehLKNz5on121L+pc1fB6P6HGOG2JGSfyCtEmAlzxJS6OHX3+0OjZj+/\nU39iyGfDq+SsoaRyEo1B9+NzUlY3QN3WrogTf252tnx32yQwAq/DC9IRMcjyRtY/2+fa37+n2cbr\npOgRuAcFSZg0oLbuBFGrjLA+zPaIP+6w+p6TfdUdyVvmX6/BzVGEUsxKBCMgiExf6Vg0QNYWrUCM\nVOwuGtXjJakGq3SsAEO0LNfcpHdH9/hNSvAd5ZmNMs7Gl0/mS5QTQGr9Q6Lt0Nx9jh5xpqH1iLcq\nIEEimc0sE1fZyCHkYjXXZf6DyYm+MMT7pqoIa5SpSKd6K+QSRlvCS8HIDgi1o8U2BK9iIW9i6lE+\n+V3epBLcpzO5E4HGfmyOkTElVCjxIs9uYGHnYAPZI9Kp0mudq8dtj0EpOrQudCQWoib9cIdsvIBt\nWiH9czGo0gFqbyJFytJKL5CLk8wRBC4DHJR8zV1DizeXfAPvDerSWC2C0xaeeNEJPsxZ9IZSb2X6\n/uJAgmvxgZdY2872hO/X5gFdibgDCnedktjjTOuX3YWEECuzmDfzFfyIC6a0KVrKQa8XoE9mlUQf\ngVcqCLoWZj3HqI7BHrf2gC3puykjcKiXG90Sg54yrlRHDrIniqL4mW2MECj/ZlUt0ufHZ2fV2QRl\niKB7XkJwjoJWLArlKC0113DSRREK72rp2KX1Br4pdndddGjtcDkKg/gJjwTvMxfba9XzJcgG53My\ns6chH0DR0nidc94ClsOXPxOl+w7y4ZvtyVYrfkh57SEGr+hRWzTd/3EiSN26TYVitszFddHm6eNT\ngo0iZiGD5uLBIef9O1qzI6WxFbMuLoDbTJBmdYm08r5KTFJEWszpehlG5yZdZCGTTbA5+14i7nLB\nrzfjxZF19Ei2kGgGtyxZz0+1knIQYughD9nEkC22DIDSQePIAfvF44zg4505ytUaHPMIVpkfcZhX\ng0gbNLXU5kPrOyNtnOn9tZMzAbFHunTXH0h4Djvyz1n+ne40sPSW4KcTUo3gGkoN4Kgjx2vmin93\nQvLBTcMqoiTtjeT8NavE/rCr0dDtiP1dj+kHdIxMHSxtKFe/JO15ri7X2xcSlVqb2qMtPd8cnD4I\ne/zGzulM8S18aK/yaC9BN2IDTvLMtN2o4Ibirv4T8mm+wC96kPsY3WLlwLb6Qrv0B8IKtgrWPGhG\nzFxQZI+t0dRPZ66b4/CDiv9K3rP+Z27kf2wAgh32aLMc8wi9bdhdC9cQT4QxOakbM2Jqwj+rV0MG\nADX8ae0yI6PbECRksxhSgblPFCLD+ahB/zfMZHdmASlgeerHrJdaSpQAnmq8TCmxEFs45NFS82qC\nNpwdN7pS2d2d4x4MtSWC11NqlZmpBySHtzmPIo1r70I3tm+Sfx4BGC0M44Qz6S6og4/M+PYQrFcS\nlCHPNQL/rzUhOjf1BcGDRNqaged8bcS+fpT0WSXeQv3Mn49pvVy90e+sbh9DvR9wecMRgr3e93Xh\nkaUbHgl/2mu3Wuxs9yt4aZqAzlJkTgzDBAe3wwTGxJJvepRE/hk5OKm2Hqry11nUfdkMgGdmrM1D\nTzQ7rbrtxKnNIApf+cOAokS+OWaFBfsYjhw0VPkTVam6cVdIgUfAaT44/q4s3YY251wslXKJLIGN\nUGBiZlK9cUDLi7vuBy0EgzzN8SZNczgwQYtthCWaLkjvW86jSKKtREkhFqm2VMpiLDAQfBLgKeDg\nx7GRj+ebb9wc6G5d080vzGmG2IrD3lz3kYtPh6LugPeK5pN+QEhmlUYeu3tK+v0Tb8yboG6msPUi\n3rguBR1KsHzOvS98QZ5XU1jI3aQJE5z1w/xxfRhkGUAxOW+2xnGh1RrmK+i6z8DfYYvrbDIYnKbM\n4qxz/lkWFsY8z4slX3hG2f9bz1IL+X7u23W+KFY5W5xDpyKzawQvjGuNEYtz2BYUexRSK57Usj0L\nujjjPYzbTSTqva3jcaHUJjajqJu9De0RhujVIkSYcbnHHk14M0RZj50jJ0Wq9TCG97qx6a2xrda2\nM11DV0rd62OcZKH9BHMgymS0ia4MuDa3EfFzf56PPE7rjpALa8+fXXPxdxcG3s6NIwk7UFa6QMvy\nnK2qiAy5cizDImh3OS+OZ1nmiExsEeT5FvQU5SwNwZRCAm4ywJOlhcVbSZ41bYe28XuRFjaKaTJ2\niIMVNM2G7fI+4PKdSwOJYFglzWXwlo+NoaVKTb2uwyWjBGUHqSnMT7G43A68vdWoQnh32Ctq6AVd\niAs0dg66zpJeT28hj8/1SXxm+3ccJnSf3rpR9mDrfcgo5tZaa6VBnMvGAPPFSTzknAueXe5Z1scT\nmg/dWPBOKNaIaKF+5W1epWHmfG/Gb2M6ISbw7t/N02ZUbqoqNv7mB75/+Zrv3WTLwK7qKWV4t/jH\nGoxt4n17hjBmOrVlmmCbAnkE5nUmEGTH8EbGJzGoVsgQ8dEayO5BGn/j04eSWJT4KTKEKpwAGHCq\nPFqq3M9MuUX7WTKfCtBeQPdZUxwl0mzExxP+ZdKcC53MsYOhX2hldCHnzd6D64AhWkD6JWrOjgH3\naBgnPkr2gfh3PCBVYVCQErVcf5SmXLUhrxaNuRxEU1joDT7jutyW0ymMfDy3teS6rOiXLZA5FLiJ\nnWmX5ZVneXxxoFTfctKm6PtXgA/EMga/nHIUa2anHlTLRmjUrPsfjJgg9VLi9uZi2jBWTrBHty6C\nrrpbjceaP8eFh5A6EuipbEqqX3ssWMcDT596eiGpCM/9gzSX9fo0f9KeswLQwELQfrvtvK7fDdER\nYh5Jat5hlZiGCii7C0P/3b84hOxy2Tnh7nWJlP2Lsb/4tU/P0pbMV9iDOhCHvHOcDmXUnEV49Mp5\nTtq5VcIzF/AjNNqwV5O1ZUa340J7rsDcvOvEfIgg0fzgpOG1Fb95R/8ArHmkSMckTvxxKKFk11qG\nncFHoeFNMY7UlQ1GVCaenIhOxmL8EFaosaYAfl8CkZQKPRImGQu28qFf/a4THunJH0QAj0ShIo5s\nqWY5yMjUAbP4I37rf2O0Ro0af1eWhhSXhAherWa2EFrQ7b2LzD82MQ3m7b4YsfPGmqaabf9ke/nw\nvCvFvgAaxnQCU8zluCIhgDadQks5ca9zcQ682t1yI67v0eTQNIviXpS7TEURZJk+/W5cx27Xuqji\nsd0amKqgh/O8edOMw0WM0PIa7v5zP9aF5b9nTRzWBjKzeqZl0TX8T5vYoV6Eg36tYHVeGBvfxGSU\nUOeiH2i7F+0cRV+4miBhSoDOupIZdvZCorUdJCF09VZ3KfV07dQ1V7J6StF5UA6mFtFeZPRd85WF\no0fPkOEb+wSbr1mnZpJsYY5gx2S2tF2pNhLvrYIlhRplA887q4riYsonu1XtD6VdjhpBsEZ+yNeO\nNMGltKPhthyw9anjsKC9ASEhvwY+xrkA1CJcHkEe9MOJbQsIYvEkFjUD/pst4ILVTfpW6M9Cbw/2\nxUw41T6qckE5axZToE67hQiMDqsb/DnhVmcvk4dGaIGRwPNEokfihMBFRMwdQ9yrT1/tfgXVogJx\nYHf35Tx9iprS2SeOnyCGqPydha9VPoeewGaOdAYgHD234iHX57UF6aAtHEsDyIcZ2G/LUOcbKUr+\nE6rKXk4nLj1RHZal1ODEMmWnCs0cOHmnIyr8jW7wP0LA+Zal48sJtfe7X+WiLiTr8boN2cS5hrRm\nfndWGQRlMscIFA81VPJgx0yefz6AznKZJW/AJG+PbJH5LhozwQsCczsVUJFgCgW8BZkkTUlfVWFQ\n7282YTr0uo/xmkb+dBxnGdbYa4W9b7V93a8HI4A3bhddfiuycHULEFPZrLgXyDb1UpXxJnxsWDgu\nJuwA6JxrrXeMttutlCX65Orf+xaS8U8LFPLfDbqdk0R4qvxlX01gismoJOy7QsHa2HZ+P23APQdp\n48f8FFXwAp1x3zB+xZ4/POg7j9CsghPruYfWn0BFx/I+/i842DBUdNP5tOlNruuC09MV8xPVbIFX\nZOfzsx7fISVnTicLChCcsIVpXFJckSdfZ6cXZvkbsArdBuFSP80z2jSHLXz4vUe0u5/Q0Flf3xA/\n05f/WbUR5VZrRBT5d7JzuwYY5Q0tVN+TEcpCojYxvLMhEZyCKNFuednuKSnSri5T4MzlsshzwSDe\nEL4VxfzlMibVAu+micgCVNA3NfItD5YY2eD2i+qx2LxZCmLGPktM9FRDwaYlXtFBcQqLLTfzw4w2\nQqA2kZv5xZn75RocDu01D4vJ23WQiRx3mzKUx9uNvORrXEOXmf1mp2J9EMFuRhgyBfltuTbLwAY1\nY8BnYvtYmpaPooK0JazyK3oSjlg2KWBgwQTJz8VhCkW+g8yZjAKQN6Jrb7+vis8SJPv5QvmdGTHJ\nElijCvfXe3eMD4QAgrujgPjY9G/CL0dqAxirGAgQBu582ekrdVp1XL4E47PNqq5fzD9T01G+mcQD\nSYYk+oe67bhy7tJx7XufPQR8MWQZTPPBAEBC6iY4AFeIAc8l/3by3N75Dv2QhZCLp6sjWnoz7Q8z\nFw7BiFlvN22sromyyMy+gl5UH9Ok0sjefcC5XfThnGyjQCl+VhiyPoSCNdknFpFogXh4bnwwdsCT\np+cn+W8BicoABLdaAm7xvE787XZkw0vqW96gqEKGvPLJB4N5uRbqI4Jw75iVh3X0atDyNBoDRfIO\ndx4+jkQnbrzwUjizP5+VhOZOUk676NwPKI1LI2wq8fOMwWUZT99toINyRFNPTzqPgDIEv5AtxWFf\nerunFyumfUu0IGQZdozmeUuyrgjE+8C43FAaCeUKIYk4+yee5qrljHma0peBJAiyU0QCevieNWxh\n0iXmC/6zd/+rsotkPEhiiwUMIA+g6yn5Pdt2lAPkBoWcP385OrG1KYnhiu0jyCbcA42PjEm51LCw\n47IwfQurxqgfGl32nlX8yCH3EKuS97DWCY6uxginobDyYTZ3Dfgtl4lHxuxibnVAx/nuyhwed2XP\ngmqdpR9brkuHCKUBR/+MACZhDG1GAt8h0altbXRka1IPPVK1wzVaKD5QVfGpOfR9ayzYKP/V4ite\n3jQMlkafRlOSDbCYrBZ28XnObLjVDOEEPAJ8/pNak46I5hpx56Ht1sOMNc3tfsyaNcbBn+gMmliL\nBcYQ0OtXt+5VtRNQT9xsjjbpHImJGwmwxH3GsRnHZ3RmVT8OF5bSuEK2Kyo2PaplIjVGtrXCOY9s\nReUpviTv+Nyjc2yshEXX0y4lIsJMMv0dukFfrOBa9i/vOM5eO6X0O24hYZnPsh/FCSf0nbUVoRJo\ngP7oElfiJuD/Pg7r4czx9mvzzeILbzhJGIVxDBESysuWN+tAVBW/eJr/DSv3pXh/lr4bL46IeYc1\ngt4xvbB50WoTt7i0EKT5EHtloyUlUvofu/4Sd8if97EWSAVfbc8GwJbdBi+6ZWP2TB9JUiF9hWzf\n6TcAjmaJRZLKmLh9oLOiBlIq+ceKHHUDyu9l21J+rBEm7UxO2b0LeD1w5TTMrC633UL0EJiU9jm4\ngAoKnrrDN63vua+XPIn+IpDnLt00+unkok3sLmn2NI5ggCzIKgm5UZ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qFyTLFodkQm+tk\nh5kkMvAnlH5T9HZywAQGEMoETL5WBA47kjaOg16LcajzThDUbIEoZsIxQ6zkcHAkmZOt/DuVzj+O\nirRcmAYOyWsHeHQH6ydZC9PIAGHYDXrQr+edgTNR2zNddzFz9q80noqbJjEfle/xKUwjuH+yQmDo\nd65JMfg8uKX9k05/JJbfI1TK2ipD4+9qOx2AD2KNhyWrijCWzYaW6Br2bGjuFjJQbyX3F5ugiq18\nI3xuqW8cXZvgAQ7mKdQLTg3DNgN1mLy8sReSU/qBmMcNF0JGtJZjhCihzCmrTV0e2bSXX3wW7co1\njzk6W5NV2HLYdSxjG+wg3h2uFz1brl+FrQ4u8/6O+prNDCmORrQxwOv4shCTTDL7IJZPNTWlnDLr\nQqO9w14jzEcHgnO7ANstGGoHhFb9P3t1g+sWrDUm3G52nzJujs2dQET8nyvfbv21fUv+5kEBaCWW\nGBx7rvikH9GjfYJrwhYoju+RDA/nDE9r4cRdGobcGgiqJuznul9BRp3/ZAlDdHxm9ASEl8mZjUix\nIW+8m3g7foy4vcEtFo0oGeT1e9w2t8PpIc4q3ZLy6fcLnCM8G4kWja8tlhwUcGwfATFYezYOOFpv\n99y5BL3PUJPYDwQcKYbBNVv8V/5NVrqKMuWLVNYA+8aWcNqd37V5DQlOPEHFVqGj1MprGMtjFi6T\nHMd3J7m5ppGZNfZB9Ie44eg0Gkhg3ahOkkr5uiEqp4OeYSnk9cBY4uEGJVg0QeW3MHo/TIdnzApc\nYxtpiK6GUvjDEJBiCvj5DIU4jBQ5tir4oY1BQ+LqlbOOPaR81WnmVowjE4vKbLbKRVnpjP2pe3PW\nBZOQ/sIZpDAKh0zd7s9cuql2500KW9+LnabNecqKJVxLHsbAQZ6gIa/zpD0FfV5a0RIjG8zNF+mW\npNHAXj6L6FTmwcWw/lBdKZPEE5RpwYShooNmlND3C+iU+9neOgNwdVx5MLFzxKh2hxszohXSxr1r\nTR+fFl4ZJ2/He2KccDTun3L29NUDwtI8CsZ5dWUbHW/Uj4DbngIIBGdNFEfnKmdQUuMGg00l8Ye3\nyrF1qWwPtqOGvKO9tmEuyw9EOXxMgMK8ErvshQeCVmVcDJ0tqdn+erhdkmnmd/k0UiKQos0njS+b\n6MxmaiBhHnrCaX6O9euu/NhmA8Jq3xHvxfjsq24P5atoCQMsVhVHQ58523gQ7wjeBbcj3SJNewfG\nFzMp4Xksm0H+ISXJKT/+vze0vEgXE+m0xIQsruKZsaC8dIl10Aq/kFNfUASoiartcfMQeQiVb8MA\nauBGIUOPesK65t/D1iSyl+jfD8jhgrdNB/2QPUsMRPIucP3Nny/3ywO3WS6CU3drTAhvgevu4AsX\nqp/wpKHShR7DCy2o678hZnpNqBTSaagoUaxl2VJVcj1PwB5DLgZpnHYD5Oa35tyhzoDH4wTgrMs4\nbHo3O/d3dArlEOGYlfu8Z/TcQxEan/KsnigQ1sK1gZNEWS0nK5bavRob5kdzJkofHeA1Lg72yDJX\nNJEJXbAEa81udZhqrjox/85PtIx+CqyM2LAICFoDWuyBuyHaX1+CYFYpxh41rWPWrd7/wT++vTEy\n2b2u5/Gcub9H3B3Zql1LsQO03qboZVJtOTWOvQ5NJAEfroKkqWQLwPY30D+K7rnnw0ZjeaVhqRoA\nbTrzAo3v9wupuilN/TSuLYEHEWLi4p1m5AVFHejTfceEn7HQwK/YZVuN/8DUWdVP5mhXyudIyH6Y\nlwdYVHR/gjoBCSebV64l2BN9g200tX6n2gliCf1zpWBg8fN9GHz/FNiMUf9XdofbBsjF47Nyc5l5\nAAIU+uh7HYSawY+fvInEh/4w0uvOPkZq8o+EfP1SsStaAtUA6fD956Amq6nCdo9zjQz5cGIGZDK/\nMWk//04mMtW6giJe1D+Z45HefI4q6dO2kdR4LhY+c8fWULiF7J2MYuns+HlMbySLa4QD6qIn4xRJ\nyLZ2iUgmb8fmqKsjZdNJBj3U6LgRkqvOuTNHPGYD2DhLcFLV58Mwx7zN4DwmioteD1xRZCp3iDuS\nGDXD+dpfmisjQk22/WfkvNZAOEb4Z/rFcZ/O8PTfNw79vj8wFDzkjZ0NkH/vRaS1jFUje4d2V5Ar\nMhCPsGlqAqoSElOCPiMkequluJVk0PNGYutTHUiWdE57W6eKrJMZVv01oGDGLj23Qle9BWMrVJLP\nkM50loOCwtPDVpNmP+k/BGwVBjOHyGwpSWKZlDSbuWiBQESlUM8WSzlnbSQ5szoPjY0ijsJHZ3ip\nd6rRlY/P/mDW6oJOpJ36CZkGB6LbfrRy8vHZkmkQ72trxtwN51lW+LSVPeWJ+bdVkKCTNN59x6j5\nAqbzZc2vv9KLcD7CM3eZaKkREIXJ5QEQMgh1nRYJGhBu6VSSMQEhEarHWrJthH6ZXAUB3N3DmF2I\nTOPK23InC2akfxGEzC1bWvCmyHh7wICbDry9MWRmLzZgrP/Thr3+csP4BpulCD1lQo64NsV+QSZW\nodDRLn/QhXiPveUcIpEqeZKVyDuDvosSS6xyiOo7qJ9A4ipBGQ6N2jAVxPsChhXjlVUXbtKnwaY9\nb86iZVSv5fboB5msf2nFsT9diK4LKnOFrcT120cDPDbee2qQYP26d8tx87+ac1kz7VDyOdopPGwE\nElVO2vl51u/17/D3FxloOiemNy+tq2SeTIoT2doktxb2npiZzhbNQJ6Wj1guEy2nV49xIsVuQ7Ct\n/irTnUYWl+Zt+6hpbHN35J1NEzV4IdLHhOy1J48maQzjFN+yxftQxj80Jc6/8MDo2Tm0Uz3Z2epC\n3wFDaqoR7YWIefy2svrUdl3EaXDPCSmySC/qHcGGTJiMezYg95kldpy4JMLR8F4sFlgmHdMF7fbc\n3IBf15Vw/sFXwtuzo6bxit7clTHnaY4wXKRBXc7u1oKbuIPPIrWnOFXS6B1ksHYzGCh0RJ+Xumoy\ne39iwb6K6dr8N57pE4tpka5hxg5kdWvvLCBARPBBgPv7yXyVGa0wTeHJL/BnsLN5F8+xnIUh+0lU\nly9zDfFZqLlXp7SnJMFJ/1QGafqgNrMRBFhRPyRuvaPkNnat/vKx6kbZS6zvHMHaKl+Doe2LvgpN\nM3F88DyZZsjHGlu2xgtlzI+xEIhJBVWbgU3pM2rTg8HfVnao2RfseyAArQlzfYWNaQXhzs+dfkFe\ncNgCr7lPPofkPL5u0vQLszfdZxNLXxH4/Sois+T74dG/5XDF2CAQVi57WOJMBb5MJk07ncNv3hdS\n3+5RWseTqv6sUIQUQ3TlRNzlQFQtzwGJU1gfTd8ydkV2nnOR+NhOh4OiRKspN8lA0j/wNI6EUELR\nbvSRQ6ZTj1Y4uzX4AiXPh7V5bhB60bnqF49RqBLJodpZxF2TsoohvjTzkEv/EskL5mlwuSbvlXDi\nGFOk4/jSB25RfEqO57T2uoCd7gJVIj7SDcKTD3WZYNtriDve3eGEGiIYx4QlDKQZXjIuu6NO6OU3\nWY10AOjj2/SYXk/oCGt98NeW3K4Ab+fZakw6Dn8+Oww4Iyh1D7qRdqxIQChOprcGa8gXUUS/Im3p\nqG+bMBrallR0AzUJXadHldjRbA85Ng6MLAQAN6bi99Dt9JnN9TZqpgDMTbpfThZGMeJ0qQxgeCMz\nUjAiVsS9SmApsH+qh0l08Dg9oWQFICPGqp+VYdcGbbubLyBAdWykfQ2XLvXuD27OHwl4cToLKAxg\nfW8I6isXfWd8xchNtO6qKnM1/v/1Yf2GATGMU9dXSBhmSf9tj7HbTiz/LkX2FD+EwE1wtsUsldJi\nAPTrmbMeAfRiX654Kg9dXm7fC0uqUgKq1eGjl0vDSVAwfjTgVDCJv0AeR7YE/8DQAShJOfh6kom5\njAiXpOTsbfJ7BmyIfDzNH97gg5/Pu1s1FNpoVki3mtNXw6alHbeAFCp44/dYZvVGlRNqiZ8eKk44\nzAwXv6VcbGFj9EdBZcQ7WhTMd5jgh2rlhC5Oq5P1DASVnqctqYGBJbHxSUqr9uBPXsW++QNc7QX2\nZgcl7xRps7fQdNma97bQZQH9Wa0KyP+JufQy7LwxmWxJEgl3LiZBOJKXpwHrFHzCTBNZ7+rtJ+j+\nNEeuschl+8YjCWDI167Z+QNVv2obAKPOf+wVROT9l30XlVMMTewBwkKWa4R/Z5nUIIt6KhIEIzUu\nm79qFPW84wgUrCVTgyvC0/5SWL4gaOYegWWPQEHnHJRsX4p3geHi3FOng8dDSVf44SjmtS55TWF/\nvgVemHbnrIFf4p2Oz6EAA7+RzQIetilZW2AnuwzLuPg/8gYdzbuUqtjfspgYmRzKGiKjTeXZ5qZp\nhbfDlvdMm3/uKUGC3DCSRP2jw+sC0Jzapa4WqTSEgEgLaxNSK1eBhJCoT67jjWidIDFuUArcsBSK\n/4y9+3FZ9KuHrLPfsO7QVTklIKgwqXyZsChW9D8j8tXeWhIBLBb9rEMUa7/a537leTEmqSYxmr6l\nOeMgUQqvf3w1jH5vz/pcSaxQcR+MgIyA9F4zFuPDafe97wnfNKwu4fBpVM0F59Awep41axEBc1jS\nRhLVxFedPyrPzyYkNLh0asqRLFRrHYfOjWtf0Yaibc4mt+tUEaJTusP13+bk3T6/S10ygdxzpVvk\ndd23553468/tY2elilzYAmCioqJxRiF2LTWpIALMrZ/7Md8oDhRArOaZnGifcgES8dyb/JBgObUD\n/E6Vxr4rM95QZZ4F0L9/jf100NXxMdZCNTT9Ezdm5rL+drRkbe5iuGv8H4eD3t7nqvMrVXKrY2Qg\nEK6b3M3Z4BEAU6LlPSmE7VKiXSFUzIkexY/SnVu6v39K+8UAY1oFJiXDbNhrt58VgPH1UtndMm0m\nXPd9z+Xzfy7DahEXdIJcdCb1LYfqLvYDdRL8U52sEfc0QK93591YIGCnLz1eS1eHPi4K6uWldHHL\nwkzukobiq75fJ5VkYl/zm1bA1C1SS45vDHRf396iZmzVXGIx/Kr0xYApDwmEl045aDJZM8P/WmEg\nBPBdGYZKB+qruL34vu0kXx9r1wqStZ+ECWT3fB+cwATT3WMQTTOaS050MdXdLkxih0+L9YnT8pym\nQZ/tY0GuM2AKrJZzGnZoOL3iiPS/cgyImKmFosvVPXzZalkyF9s9A66mM7ZwYYjqlVopmlds6A/B\nWOxpQWRfBKS2iQ+6O9ABcTcu5hE+iGYKQIRHSUe294jPVsQg03krY0dMDxOLh32x3pzyDjlk40Ld\nVrkaZ946e+Ud0e5vGbSNg60NSNplCYFytHquGHhHOXp9BpzdXI98+cNEwwpG2KfaYqR+Pv7WcAeH\nofX0hNgMNayc5CLiQRIxigpK3TOKQIe6cE+f6/+IGo5ZMyJmUbtx/ObvL5ob+gPogs70032vvqdo\na9Yk3BVjvoVA1BWRIAVwY6l3gCVONPzjvpZtusdbB3s7RlSYtCFpC1bWfn6+90T6e2YDVRuL70Yq\n0GNe4vI5ixF4N5YoMfZyR6AzgTA7hDMOZ+YysQBDlXU5ko7yyuK6W3P0xirHZd/f/zed4IhXSTkm\nhowDwWu7BGDvfisB1GLLcbz3hBC4KaUFWhEYUyAB1B32M4fJZlVzMaPSwn7KAmUIymABr63Vx/1f\n6LdvxgJ79HgnNeuSzhCqcEUdEBG0reJ16umH10e+1LdqbwQ+2a9xpkRuTQ6AKls5kZ1Vp1OUFmRj\n4a6jRnqLlD8zVUaGnPJFf1pG38A6WgC2VpClR4gp7Z4yGOOsVitodr5yxW/3CKpYm6vVo6CUw3zF\nyXlGYr4aKRLLCTeU8GT7houTqai089zAOrSM5oiWM7cfNWV+IIcP2vWucw8RDBJk06MAQBQDUoRm\nx1Hac45K18PzGVXZgrNFNOXmKuteVssbCHzFrud7SURxXWe+8K+dC+Tc1pjpiU3eGyvpMavnMg+/\n9qQ836a27qU2dBtTzmXlSFE4EcDpJHmo9mKoEEbK87kWNEPLiv8OqErUnSJ2zTvmMB+E0Htdj3F/\n5I/WWTlQzGwJlIk4TOXHAFM/0iZGktKOZeQhyX4Xx/7FAj2z/TVZ5YrkljqHw25Pfa1VGDWX4I/E\nfZuFcAq1pQ/j3WgUmlb9oSwmuZrh4zjB1Hl2H5YLQYZlm7QUlPqaO4JHzubI7o8PSFzxQKnalbPf\nR1/eU4OVpiDsjbSue265khg9/YzE3N1+2TTckBI7hnFmfFwyv32nDIRZF7Y3AE9ph8yXbf5nlcDP\nz9C2gLrwt/9pwTOotLDMa08BTGVYcNGZSwRaG1ZanqvL/71m9bFt63aPb3J9i9nxhSo1EBjVYDsP\nqqorfdeQsYynWDPr/J1QV8Go5u/vqv3rqAdsyR2T98GJ221rbbygJmiNhvhZqix4Ux52dtxu2JKg\ntdaun8y8mp3RbkPcUctkHvCAn1EVgum79ALF2ZUwvAEzNIa+F00dDJDgXG1KY3ixlTacihmWrLXF\nd/SdYxH68+GEN5PrbeMPQ4rfuEE4py/sLCeekdjrB97Yw86SJx4rDVpT3B7b2D/4WR3sJpNSfhwQ\ni5ncsbvbDVbFHCMNKKLmqM4+2m8U+5GcZoXT02vhDU1kBqMg43NXgo2krmlbeICx6zF8yoBEDv4p\n+pYVNZ5griEa6nSxEJaoAUexiWVAN47a1KxKCLFG4dyTqEup6ybxI/vMGzXqzdWts4E9xE2/AWLM\n9M1hepuXCb7L93xo4hZ8EU7v1nLoRn+8SUpsF5xdczHbJIlzfeLNo3Or2yOuQTkDG8AHpzrhu9Ha\nASU3GCrc0z1PeB+0mp6oQ/NtaYWSObsXBxL9CTrU5jApkfC+yzYlTF9wmb10sj7Tr9SnUNP8Osbf\nbHxL8RJrfot0s09Et730CMpdOn08GqZ8cRobgAwBLKp2sdcNQURrb6JEzZk0Ozica1fEEq0hrzEL\nvplG7UJDWLq4hvtDjawagtxeUU9G+ul4IrfCsgAyuGaz+jHDqbBCyzUP0DNf1KA8+WpEYRxp2XEN\nZnDSv3VE6WAnk6D8vMsNc6GfVsD3AvUXoiKsA+7K7crBX7tNAv+Y18ilfSeNiZy4cXbpfBx18fuq\nVtRjX6gu8nzWpKELlxu07IwwO285Cm/C1sByalx1+f/W9Vx0A/GqrOy7TMydB1ziL4oYrhemON2l\nTZOht2Z5mGopGCHMP89yf91M3OYTQVbkfjpbfM8F94UChBq5dBV1eECKUcGN8Y9JELExjrBQe7kM\nQb8UFpmF/krhsZUzFw+0FKesDYxUkTEcezfFLnd1gKQfd8mJJyt8bfxpXCYJblE9VAJlq4hWDUiG\nNU5IpLpmMHnlgZaYykkKBU8uGsVRqfWVhqYiGHIRfVOraRLdJ9/3aq3xZG4NrZQJWO58tosOqp3e\nu9v0oH0YLOb/ZmD95MJvmL+yuwgrgVgKMSzrfaBocyrtegTpsJN7VzBIQnAV2APduGMxp00GSMqO\n0bSCLtDY2V2KlqQcKkGf4h4lk5T7mczhlH9XpqMtN36ku0PzmY+ajwXOeGUw1qY6NDB77EDSpFEF\n4xLSxFhMALRWbjuzZsijDacqjK9aeSsbAWq+oCoR45UbIvkZGCNzrjC/eHAu1V7OJX/0vY3ZijHY\nmIw+ZQHrZnYNNwHzkyRuLjb82roYZrx3T6R1S8IrY7wnAiM6QbFY1hkHlTIQIbI1oNAFqrfCNCry\nlUNdAkmgqbCMMx8OMqeqrvYCetKqv4mmmgXXaiwbAAV7rY7kPpDi8XAR6nlj2vUgR1r+z3Yj+a9b\n0msbRfwF18+iE7+DyjazYO/o7WaxQZ+BXbjQN0wMNlZyWW7s8miXfgGUJIUVdORXG5u1eFmXBI4A\nxotrfvJFQneHLoYvSqbW1F2PTKw6a9Yjv7twhzn1NemNuKdGjAZI+XfP2CeuhJOeR0eU5X/lhaaj\nxhTFiRu/LR+jQuH7/27LxpIDqRtVlObPmySKMnx+e7+9reAt5ESvZFqWhFVXVMttElc34bSybEzS\n6bCIy3xYzMZOw+ubZ5Y35zUP4tWa45cWsCAW1OTiMmBTDsQD7rDTelVvpZ5FjO+mX/3YUyEWD45Z\nDurmoKB/2Ygo7k4e2c8ELfYvvkFyJCYuNmLPcp/x7GpUt7tFn0bGziKoUBPFA1HPYDCYJrj5UEZr\ncK/cK0cj5l40xIFQ1nTzRI5e/EtCUrgfm1NeVO0hai0DUJGimVP9/wTrsmXBRaGVhY33OGdIV6WE\n/cRJ23WDNqya+YocyJqS261CQBRE38x57+rM6Vu562CTDD7ySNiWmgWdCI6JLjFWNZxBHLZedz72\nQ9CxadWP7MsY3qjOeOOhiMCux4uz/kifXpxnqecPbIP5IwZfJ4tzbygfrCk9/dKlDr0WMfeulf92\nqq8AIPUCV4ILgLuNSiuK8vYsWGxn7AEicXT0UJjhhMbgouw1X4/cHqANIg63UYX9cfbaYqudYptQ\nBQ/7VDmuu5kQPLMIXjmWiyQ1HvLC0hlDlsy3scsqzT71Ue+T+YY5ges5w74U+Lig6YgJK3BiepW5\nDcYZcUOUku07wHOzzUdYhPur5VDb63sI1uswnNWRnM6lKtVrN7k2SQ6g6JH0zaWoEFRgMhb+Onjm\nA1qK6CZDYSWRi6jMduuH4EKFqXxpyoCcEne+FBRqkNyHKt2i7d9XNJnU8g1bcq/5vAjA5IGyypZF\nw5BVDNNJ9Yj1Gvk7bWog2QnnApiqUbMgEpLGjbbkQiUPzqCm+9bLm8MsvaGpjVlW/RMehsmiorcK\nKFC8MbUQRfxjquy2WWRf66pe+TAXliQWmKs2jtw2oQWiSizXUCum4JRA77bWSnSIlRGmsVDxFSkd\n9VjoLvC+JFJ4K9fECKYzy6UxC2X8MakRxP/auX/SxuHuFwHt32LIdV5jtTtBrQUlr28ljhfOphgw\nbKb40dXemk4Q7JfA+f7zr3m1o2XCc8bIvnim6MfYjOCk4mqHKjV2OLnp5yWVqgJW4uwj0YXrUJR1\n3QSDEohDDL2XnAKM7as/msL6eBn4+SvSPpzLjYKGufsCA/5+BSDeDujr8JhZeOuNlkkTlxCx24hB\nuaPlA4qekVdAno+E9wDuyLApb1/xVZ9R9T4Fnzxid/qnQ6pyWIUtXvW1DIDcR7dBh+eco++SO/S6\nRmi5klvy2s0FuA/MPPS1TP5eWTsjz5Xp+8Xvp5Rm29OuME8+oNU6yX20Ti6iF/tCul9+mWSb0pLE\nKsYo9LLUThkVtguVGWGv1U9gqzQnkZ/ETsKhEOkk3HmPegDw10OPb4yxjx1sqPd7bpyelhb5LwTp\nP4ZoSae/8/SMIFmowinkkftvNg3/OW0ynbpTN6Fv96d4/ZFGde542ARGv42lnrKtSfehlI8BT/zk\nlxEdea3aO/4P1FfFMOBka5fn8ac7uTFe82Y4ncu5HsC6ykKi4Wn2xxyzSlaLGekHDQnUNM8QkEcP\nPJtdI04G6FymeM4VTuNmjLAvzKvUgXoylbEt3ah0BPbvOllMA4lZQW4yuRIiiWct5xSXY9ZZlUCj\n9o0TjvhxlUd2ZMaj/dp4FRnnNOrtAh41ELyDbSuk7N8D5L9NGNzfa8rQflB/WoMiHH8MK6ZSDTUR\n2N5fpHESPec/rEviwFPta7S6Up1FVDMiSq8KsAnOciHCuPoXfwNecb2Clp8C9z+6w+sqfxAn/wzD\nxSIZ/3ph8w70j45BfTlvMtPVidj/RZp6xZjsd/OZX8OPa+IvgCXZ6p21ZG8ukDePzCA+SlqxDoIo\neKe4+da2qmpVY6ziStnpHxxAUe6W1ncC+oUstNr0hhrOvRfG64J7ySOFvBGfPx79jQgM2tF/+zue\nbrkcvHwyEqOMoMgfNDeUsZr8dDtKeLmCY607VKMAvUbT4RmAOUfplVO8CZOk55Z3Cx5Mqdfv0+qE\neFof16F+MiZXpTgfVNMMsHAA029ply4dnL9UA3v1/Q4CuasTfHRIeg4dfDNpGha4YOzrNPFQ+rLX\n+EPt0ECL5kSO39QFe/O2XvGepbKiUE7KQ4dLDv/yOgjje/MgCvlIRk21ff3JXUEunql6U8XJjQma\nm85Gn0u3uFamypCeRyfyaxFqcKHlc9mIZVLg0AVJuLsrJ+K8Ftdvt9SOEbzPuOy5owvProIZBSir\nSHuLWpuOeA33Fj2crsvxVs0JatMMBPFtDy2/HXVjblFLg9+Px87plBB9dQpoqr8AfqNhhEq+kG/2\nX/1GcdqLpqvW2UuvHvPfmxXhtuCtn1CI3K921cPGh9xEUVfI/llA5AZjpFgrBFHCsEdAPVSksraQ\nnRJgngkTlzujz/SRqvPDOZ32zX045ZDDYzqEGsm2SnU8MO8g13ZiNnCg3rIx35i8bcPbM+5woWLY\nw6y7aExkpKuvZeDoeU+eFi0JpJ43TbV381G4m5+QVmUeGnMi/NJiqrNWdreOQEFR53LK2bDCLGgZ\ncXjPE9Y5A8r4FrT+aWlxLa8r6uu755g54hC2A85+ZOgjegsjhfQabCI7pSwykmriLMam0GrLQJDh\n2HZFdbrjgeyI8iwl15m2YLlhN+PCVAX6V2JhH+o4fgyBw15C1yJDJEXRT1Ahcw9NIdGsh27ahcKo\nEbbTQASzivHno+vWmmHEkHV9ZgyqsDx95FYsZv5CrzMNAGQ2RBLDOGZ7TLXP5/xI6OjJB9AFcYsV\nqkeZA52ZUNM9Fltx99hSRTfer5Q8nRrbntcCdn8mA3u9ZOIn8fSL77UiLeqtXWzxRyZuQ64v50QE\nqOuTlkMOVk2OxofxpHc8yFm8zECadLCFE/DZKzfIHursmsQlHeQG53sfMP0W10DQCfHgQLahhgFL\n3fbVPzOsGvs7pe6YKfBM+rEaijVBdczFWIKYocqoV6IyYPlxZGCBdbBryt8N8Sc9KYuJgbqyD8tN\nmDB/glRbw9V8OrM+pOS/hlFXneQ/FH5V8BbAWwKHrjyA7ycJAMm6v1OAgsHsFyls5bX3XT0uxalT\n6O4NgiErBviNOnHsS07Hd2bfRJvlTj+kuV9aaxDx6PGB0J41tzdjHSVHt9rLEXZocCvsRGKw5Y/Z\nagBVi36SbDdCzf/5DJvJCKsEVk0HQd/hJs/QDlGn4Wx5wBEH9VbT4lplbrQ1x73x3pYQHC5qg58p\ndHzUA+RKINJT+8XTEOb6Fzsu/ZSdjvorVqKEooNFReMCn+FpZt613fhDXwJ4z6JiOc8lSogUejU4\nMnXqI63n8aTtWIGuRK5PAMHPrlS8Brq+4MPDnwp6TIXO9NZl3uz75vp5EAdlHK8Y1FjlrH2IYjDg\n3/fgqCzjc5aheiUOx+HRXw+44CX2ci+tz+TN9/3Zd9b06CDQ5ZpYzOXQrX8DLy8KVYGlnosHMi0c\nhkJtWIXYByP+Ssn01Hh5rnQ4X/ntZ277Tq73YQkaShzE1YxCaqwc5oifF9I2fOY1y+N7r/N3bbq+\nNCTxqRTWWsL6WCmrkltjUYcJMNemfSH1fswvDVU0qAngF9y5PGBmpJ8IHeaMbH2/mk12zJYJ1v7L\nw/yKV1b4Yihl87ByqSFcxwIig3bjVMkOOxZeKI3nCuyOUkuABijpQm3+nfZGYIWj6eTa8BQCIoa9\nU/RpsMtt0EK9cccHh+UJCoEA6nyq7EJMst7wGM9Gn2fP7BBogSDt4rKKsAERQT7NB2XyYY2mAnkd\nwo0c5NOQYZLO1UZc9n/MPXZQalw+tq0BWsHLnjh9RknEe9m0vrBlbnZSzrnSYGwt4MddZol4irhV\nULzG3LJaPSSkUUfxN4Vl5sazzK+tkN4YHqOSQDhyEyaLYScWU0ZmNKWmCqPfX5S9kMpeb5OnYW35\ngETbgF4qTWm5BEyl1QKWM3BTJf6S4dSeDmJSjMQZ657qPFa0eauczVGa/o1XXffPMdT/XEsz2EmV\n2N1OLIdTZ2qAKTLGNcl6ZvL7v07xYQilLWMYbwcc7LGkZuaknZijacjcaDJrkYx4HTrod8iirZux\nqNBStN2Vrxb5KXnxrGFlw0eqoVwp4rvT9C1M4RmIaRN9I5SKwoLCIeyA5ZVkgfYTsfA5p9YjJ9Jz\nzU8qkvcybUlL/SS4n/5FCvDdtO963c6GjtkJLf/2sNudoKYiu+0XnvwN0FEs+6f5BIBC3dlgUDST\nns11G85fxeCr6zIxaFXFx/deLcKiIPnB+xPos3DUBU/I9I+OdB7hqMDqgHXvzopla/V2IbFyVfBT\ny7jErE9hrYplqhsEaoARt7eCylXZXkhBGbC4Kx6ndZQGOoJAHGALwjR5DiQaVIsk9fX49m34Nl5y\nL5Cn3zUCp4nsvJCIixX2AVWZ+fl/XQd7GD8OmGfzlFHeIh0cgg0xMEf3nW2xoM/+6hoYeZIwi6oQ\n+qAus9fDjj9g9ucviLf5IJI6d6zErXWJQqvApLwj56QOunVzhAZqJKbYOQxretNikHEJBSut2Iie\n50UVKLIVtwK6e7D9delZu+RezgyARP58jUiMSx6wPwWLvsn9pWUlceeDUjrSmS921bhFvAWum7Dl\n9IR2DcTy2l6Mbp5TrYzzcGx90YqyPYW63USl/80+0gZlYrrmb+wScvXTY+ISBahFulcJB4sKHCAv\nlFdTzgPJ1FcQS0v5SakkuVEP2ywrFbNVBlb+nEgxivT0BL16u5eSf14OAG8H7ZBmT23JSyKuUNYa\ng8oD3grXPPWNRxIvc1lY05ciKvDho+AD1vRiEqpYukts/B/MaK70I8Jv3+Yuqi53/3/XPIgPLy2D\nZBDpMsGVoObKdshaOHEnM6zXA4BeDeXhpWA4FjkkBZEiY6KuIrwSqBlkBR1F1jZ/0cRiDv+/5u3w\ngHKWeYNcHSaGa49zR/MOQyfGt+LDm54bQAJSJ57jV2G3PQE0d5FglA1B4j6GaTp1f5WLJYAPxbjP\nf3+OmQm1A5pD6MtUGP+x7RKmhDOIKbcOdb6mo4XEMvbZmev72vjEYT1230ZYXO+g1+GqBcJ/PgDW\nBixqG33qNuPiWbJ1gzIboFNThOaqcXTQcyOGyURGW4IoUDVrt2tTjJUJUIZvNhcRRuUQ/RB2NZew\n2XEI+LfhpbgQcuD9bBlOFZA3WiVNP/bd7X7iqSyOgkQPnV2NVxdddESKkip7RAZ8FXKE+d5h6aNd\nEjS3jJIuAeTwJ9XyMtJZheNRaZnJP9i3o5Qr14exZ25xy+lv0uKWIpOCVvXzU4io0dTB8cq++6V3\nz9yrJ/iy1diq6jxEUD4Kw1E1j/y6XKG8mx62Nr7vjKyN5kE9uhDeVtAuFVXazAlowCX3xzQSbDHv\nLaOTec0jypKI/H2dvkw8WdbIxJltbrJDeJ4nu5uPMZzfowjNFB0oKR5VRHMFk/grfH/O8E+bvmSn\ncowuI9tOPDegsepkGEIDli8GIHUCxLydGJgxVGrL91vhf4hUjJybpAQyUe+H0qrskHq/H75Qrxu3\nM1davXgUsXbVnzfWy2iTJHd4vBxn6pTLAOfPs3Aqw25BeDczUF5ebfhME64gX+gtw4PA0aN499Va\nrwsppyXMRbR+7uQ7brLtNFBHMfT6BvJHxd9SxbFs/77XB09796gTNdejfL5cuxgOzO7ocCFZKsx7\nDtOtceAuIB34b+5SIvp3M1cX1sSoTVDs1SXXp2GkKL+3BlltdnrbjuRp6KZA4JHfxhx3b9+u2WvL\nOvegmGzgrKD7B82EiCSPOZipVKpNxYVvFGLf7DRn/7c4Nc3GVCyS4Y8L9sScazdeC5HgEqMcZLtZ\n5ciP88tqm140BumHB4lw2AeoNO1z0mXEfSoLLiT+eGpCseDxALyhfxwjAzArQBNGcrp+gdXM4AXJ\n8Ckjt7hYLjVw4WI3HxVAnQHvPukVu7IA3+oHGVJxjxgdH7FMy+2Z43vdDr7Fz+M8kXbVPYD4UbFy\nE+YM6SWZKsFsypepvRATBaffIKlbkcFsvOtlARJE1zBZv6sYcYXydzVQr4MC4EYgPSphrsXtCLmU\nB/WTgMO5eUZZCrBY2+MPirnn+IbvF0mrq5dBQ4mZ2YrD30u+Z/wnD3l2hwaws0SkdaSbuayyXRe+\n6W1Vrf41W4xic30efGnSzGEXA6bqpVY/IwywonfcvmE8KgPIkcdH71YxwReT9+qdg7KJXJPpw2vY\nWdcXhtD6kSoHKx7SsFlnWdexW2VHnHvGRo4WE/q9gCtwkx1+oNIE+12ZG0/f7XpH1yh0y3VzBr9G\ndKx0aiDcXlj/YDCezd8ISH+VWYCMjRJbdn0ttOezfUnbwt6djVcb76++0Hr7qsQIOMf6u9sz0u2G\nTvM20R1pNpfQBrRsVzsakx5AtMdx0pm33rxDPJTZuzVjPG2VcWZmnOOANLTlDrAfN49GRzBGltIQ\n9n8vK7y0os4inqxCb17r69W1CsPuKOh12uZapkC4yex2fCKhoiyZ3vbzNMT9X9HIdpozu6mKAz/x\n4NyVHOWpazOhwPNz/MBueXfbQTwIdafNGAz52/AkHKUmH48eH6e5br4j+pGOWHlPqdvuE2k7zOmw\nU8Hmy/Okys9o9gWco79+NyYKLKRaEKpSxQcAVk7jwYDFu2sUCD0o3jyRTJvnsyCXxEl6HvQMIBKj\nmV8f26nRk3Z/nu8Q78PrQtWrIUkpaejzplzKvBwZ3FzllYvSzCcbgyggzqp5DPUFb9bDhXNS/GZT\nCdKzzCzDVe0RYUXtT+yEiO2zBPfH4L5ZCsTO2b3p8sS/zmAW5BInHFtAd2AbFYj2Ba9YVZHF4AoH\nVMezmYOumq1h/dducCJyK7qud5wzVCwK6wGkQlZErTxO9z+02wPzBymUgtFdIVbryjtCLgr9ziVF\n8+c7Hpv6KRNvIcTBimIHAvKvaz1TK++7gK6NOHkUSj/0ASvDs2puT+J3rHmkjKdQlXMvZZdNhtRT\n8MTlVEkljj7KaVaE1IhTvJV9M11ZPgPtecssOzx1AQSP2yaCR2qcbkEZyjIq8rOzs2ufAxHxVd14\n2Yn5EGcSWd0D2GTrRyyy0JLqgGXvWQdTn2TTLnhg3LJtHUNVpI6c8WKTXkSWLf4wMGxIwfzlxwpZ\nF2fAA5V5FcDpTPZUm+B+WyYpcaMQZ9L2/fjW01obFuM0augTXlvEmFvS9Q2a30rhYf2v4dKPvJCe\nyejc6PnRPIpChgJMQGMajWAqnLCxn++4QAzPz5a0rSfSyWjvlMElqXNGGPh1qknGZ7xdqx2eoap+\nmaioXsCTemAmyHQXezoFWKnBlqhkAZzv3o1YOlEGDty8xIviV3vfZn7DdjTtEpdUd2j9iMHSs4Bs\nfFf96y6yAGYjAXFxjske5Mkphkc6CxSnKbzJwYsXhRBv3ybcs3CbAXZYBrMjykKwgnKeHgvwB6Fe\nbLxlLx8ivLVpyGjdTU2+BEOkYnkLm7uOy3N6Wy/wXJ5WEiBPt4AVZmzVSD67FOU0e/+epCV2jNpS\n4KFv2hhGOzGYQlcyoxZBVCBMroksp9pI3TtQi/quMvYJzWKHnV3fhiO4K2ZxWmK+CBHv8MQ8l01h\nFHbSE3v/iu37mPpAODMreuhgXK2gCQI3r79uhkxHwlyDDt2XFoq6XKBwXuZ2UKAmqWJDnWpGBT1S\nQv9Am/eBrbe1hcW69KsWacmc2F3rwfGVZKFPgau7EbehjYc+lXH4zL6W/d1dzJC5B6gj7Du5Xf+a\nt44Gnhqmm0GT2sW0iy1K26HTkwsyTnivvthJfLdzbbDXijP5FM6QYeE7KIK9IiOttRmE7mTxQOiu\nJIUe3kgY5Rf7C1XeZqV2k/n8eNrlhPtBRua1sM9W5d5iwrUYSqe6AcZuZQ57rFFq0b5x6Dysmezw\nipIw693pGZoHv6PhP1NqbIWLqbpTQKyf2jIB9y2pchBa6HUV7RFAKTahsOWfMlaHIANKOAnwyklW\nYhG2pUNPWNUWa7NIWJ+ZI6dhu9tUPC2qdMEqS9Kh2Sp4ZN1LdTq270bjDAMVax5sfUiQuhSs8xcS\nshiZoXEGyPOXbooR0/8eukM4Me735rwvaGPpnA4hTyQPw7wK9dPI9rL0R71GKCd9+apWXGbzsRCv\nhZQCtf24CEO+M14giNIy/WLa8JlYWDAip2at1oNZmbC77y9+KWxVvojD973qdrKdM/TQY9IPxBX+\nmm+wnxA1AkFtuqT6IYADzkMMKE+1KT2iGAR9tGzHdoD4EBp6HK9rTkJdJlG7EQo5dsoaxlXxgXq5\nGuiMFJhPgrME4UUx7NJ25bVtLv24i+muRdVXlgUbRpadmjK9RAhRywN54B+wWy/sTPJl6SA/EWOD\n7FLA8p8JVWER3u+4dShmkMoCj+fg3gP49Of5yR0N3vWVFkZNhaPDigq4Mao3pJjPOrRcn/0jYOsH\nAkEXLkU2uW8vCf8mqkHroLSiHvfIxbINxZm3J24gaDP7ir38oPtPE4KIiURvqbBxRSJBQ2cxkyVY\nPhssnSbgZXd0uf/FmkLuUAmRG7YJQIkUlRUaFa9pWnvgz3T6YHQvdze1YOfgt7VXRYjCwJiXCnss\nqxCz8fbrT93H9P/VRgZNCtuIZpcY3GYI5jMoYuwXghjOnKMEN1WP/jTCXWQ8v0Kus6Zv4G1XR8s5\nSVMM1hMGAKrbLeLWUaWB4YFjks7it7/1ZYCpAwTQ1mC3MQ46xvA3UL2JXwSwyIvBtr2Fwf1y+FaH\nropsHkB4ubt+vyO0pH4nafIMXqjp+8h+Fd0ogqGBKMu8rfFvv8LEaFUfWYJgUig1gf6AUPdZ/Qh4\nC1ftZut3ZGkOjYfZlEdBWjQ60RxuY8X3EY+ehOufVAKqY2aSDGoVoHBxixZi5MX+0i4tZo1mAiNO\npscUjyfqPjKqjHjU4Wq0dPZKBFPCHkThM1eJy/3+oYpllBgo+t0km1S2BzOuNTtIVFsTu1y1TSeL\nKgIWBzRF5Xw2cKJqPzEjlp0MmjZrnXcebblZnVKx4ueJB1zaZKp8TIe1Opvk7vSHZ1Wj+63aUUNu\no8MOB/udka8YN1ZDc3zVMP9xy0CMiYWMKp5e04JvltCgfF40JROAJB9gH/nFZ3jkjgB0Cs7SPgK4\nrvzj4YG+coM6rDV9mxbMbZoODA/ZSuUdnvCZt9XwQMQq4xVqi+8/BAUZyBsvpcuOVlSyb2vuZgeh\nVeGJSGrutVzSYOMoRjjBGW/18lEccXXBb79HHh6GjzmyHyFDxnOO8zNKAz68/Oc79DBHQslfY2Xd\nduBojjroXbmJn0rF1QptHHfWOAqcXz7hWnX6jTe7ET9T7pkB6bdPhmX3Ifyle8+uYdJq3eZ5facQ\nQOgDiWMvFYfeLFGkifeFiwsty0hR0iSaaaXUTUq2/Idvrl6q2OEEhIknRhOGgxSIx8kX0MfW2pfU\ndfB+d/QyVLJos5RltzBnxozWLhgTa0/DK4k+uuzWp+QKkSAAiw3f8+VDRmurSGrbaklhMw31bgGW\npS5EiL8tXGbKhKoOKsd0EflKSAfGdR8IlPV8VrSRiUrLyF66/9ea27LNi4b0xtXgwDpm2GRAQLH2\nPwpPD4W32yMmaS9yUW8ziBGFRWC/oER056Y9u7K7e3npiJFLIwmSib4vtryrOIiAoOj3xM8+6D4X\nMJmjS8D21esmxTCTGv79vu73EZj9IO1dSWxq1l2d+BYFI6SD/Yq0/sP9eL7e+Q1l/NQSPEM5v3Oy\nSv/M8ZQyPnvgeFWIMReCCzntYmIU8vBsp/kzqG6Vja/07vwe8AI22ft6SL+DQ2WMmFEk8W0yyMIQ\nrPsATzQJx+5+UVJkhYvRTREPQolKI+sBVH5zWIa/D40waS7+9sBj9C7Cko4KszMw3ZHW6wyZsJTy\n4SvZfazOMGSYujpsVC1nkvjeVxeNjWszNxytrlePXV2br+NfQQEYpl7HKVmW4tcV5cxdq5ldJME/\nWxZM7sLLEZK+LH+glE8yRdt0nKST0FDcvCq0H4Y6mreTklybPM/sUGx4mAQVIYw9TO5t/fiTDNPB\nWxNrf1Cc+n4EG8HLJu/tEju9TIEXAYQe9Z1NinSrhCCOLc+F6Hg0hLmcPEw4jC/06L5bshytKE0y\nLqi4PtnFFH6q/BYTCNNtPgpzns8hEeiaKIiAVIOk69ZbPVgWK2deP9HYKHJlnGoyrTYC+7GVdBfO\nvViS6zVgbhW8+xY/Zyzu1MdqWc9x84M8Bnp8xFKaRMfKPAzjGTUBXtBg7x5GDbsWspG3Ukqv5ps0\nXHXiWAFDdnuUDhnzpIjmUdxRbs0hrU/YgjzIUICWk/kxbvcjEOsZN1Z+CLM3okvxn+2M526K7gyU\nYJ/4c1GNovDnn1x50T1Gj9cFb54FwHyWqOqjUDRAeqSzEwfio0jWCJPo9LZPeIDi+mMxgzVisS15\nS18i3J6nGHEfR9PGNwkN15i5FuSTsPtPrU+FS5eB16Ges2rxYWMH8BE2dt4kDRWrFXDVqFqV+kJH\nWnbI5MBmhAiO/DBzjiEhdYBT88hL+9boTmW22jicviQaRo6tc08kiK23GaoSnXg/+qOGSQppOO3w\nYQoR4fFht+L8FItgYu0wDyvQT+TkHTGV1e5wywQbLMp0awshO+4l+cI0IKsEsTA54brDbh0980nd\nnXCPt+1lOHW58ynTpwPmdev4MYU9Se8nwb4unZ20YQ8uwqZJxP6tZtIOVqAi6hC5EEjks2rmtX+F\ny/vr7x4XwO56/8yv6ULYeuleseS43oCbbKK6xz/9Y2NgSArREgxh2IfE57Q5Ub8QzX8nW3LiCiKR\nxdSM7S2dcHheRmRHY1gJsjXRlikue6pmrVgHvs31bbW6P/QqxexyaHvHtG2kuADQWhC0GoEthXyk\nF0sygHhz+pS9FXOPZ4SneIiLG5b7CUWxrthB/JHV+38OSl5fZXVL3MzJDwcvet8x5g47x8QVM3Tj\nqGkk4+60mqABYS4EqZgR6ywP7fiRPsoKI+Kl8APdfVZAQPyvp3c4UOuhidiKUcBbsa7IH1fW7QNw\nVervioG9IJlebTTRa4A0PKLYWr+8nby7zFH3Kiul8oao2VrjCB7KDtdImvWPknaXUpU3in+HHZ8Q\nkmHgWa4hX1DX5YC/8ONUQQ2dRqn8EVMUkWevPR7rPP/grZz/8uw2z0/f4cHYzaeSzDKUy57rALZ9\nQqQek7d1mIv//MGaiRspNhyMKvL0Htc2BH6T3SPwI+EcxpXX/+AFZzemha8NrooHrfN6cGWmmkjE\n6yMluyTGyruqQOxbH/htMAQUTz/KwEHBS+wI1ewRLCR4qiw1C8DvjSIZDQut7UxsYA+fcmLIs2b3\n+ZCZ7JyzDh0fw6Tu8eyoxMNVgGreEEhJOL6mAKJeCMby8j+9cgA/fx+GWrJGJGdfaeu1VjObz8HR\nXhC8CKQOl/CbEc/9rXbGjDjEUpQOg1aTz5OWXE7s2TtXQRIqpwbYiyHzkD8dJzEPoKajZion3t7u\n0KveZHyVfH5w8nCLAIR0vpxyQjLE30+ir02gquCBy3QOYfM/QTLDT4djPdMosZ8yknLNgasguzr4\n8AyRg94+WuwVajY7zxEy7Lz0EB7A5qBFtbDpqessOYhtxdjWgNQ3LGuygO0Fn0zLuOpAn4svhBIf\nOtv1JD/deOhnimwnB0XqVrpOqRcwIYVezq70ji1kSFdd6pgoYbWcR/1MwMedjoUXcmc9D+7q9lU5\noDBQ1nm1In9Tlv6lSkHrb0sRVd8PHzw1lW1OoY9DTpoiLsVkj+xAZcqaXiMskBpsav/eKaMoQWvk\nz4EKdUqEfB3G/zMYe7lzdWiCNqOyRIiJ1dAunfOrckNKmCoDJsvArPyuzLRHpZnhIWNEKKRNz5O1\nyNiga1dHhWSYpNaUR2MvxHHAtJ7STYVxiFtQghn5eIp/7evXWFwohMcSLd6lQ5WCeshAhxcgg5LO\nmwX4vd5TjOudM9X5rsF+F+QCgISw9LMbk7wbHQzlJXe6xc4nZ6swm3JQZaaekL5f9P66j4S1L5Ap\nE3Y84Vik7ka5DNThFnXKhm8owh+lMZc5/2CpAtlGqTC6AjvxdAjvx78zdIDCWdFVeN8r3AdECrj4\nLuRyOoqKJg/XhmvFy42TDxl2i3AAW7dT/fWxthyGa38+HiqE4u4ta38OU69+MVaLh6mCW+7RUBo/\nmfSzahY8y/hkGOJHZpYlg6vKdWX2FokGmxGcaRGDKhttyCFTpJnD8re4e9cgkFedmbLLHHHiS0Bk\nEUW5aOOEX1OkHOGelZ60VQ6+dNHt/bFPLkKxEe5z1ZW7sUVZhCA/wPHKF1xgormv8xetG91l+a1D\nAg+8L4/bpDSjcAS9TkOXRFH+Z4jTtUzO6yn8bUHlt7YY5fBD5Le+P2ccTcSgNpvdBOBqfRS9EJMx\nDFJYNNmRPprfBXo2qseHAfaOXlem1NwUgss3sGcGA6kg5v5+GCIRYlmrJEtb9geATcBtByMOnxY8\n8PB6D+eA5BYQ17ix0I9iKoPL2fFqcS7TGK0U6yCPBOHfx1MYWURRtIIf0nBNYxiCOt4bs4D9NgeG\nkZaS3P/WNKRpjOKGOFyRVGO5g6VDoUy9pOPTYuh+0B3QTyCJfrcFGvWwqOU0FnKx2NKpW8qMJvBE\nsTJmoEzluyXl2DeFPbLeod313lvPb9S7J2GVS9zVjKS4BJEMvT19AE6sDMZRAARAnalhXYhjkLoj\nUJn+kKk4Gk8Jd/ecSEy2RYjMvt+t9AsgetF0IqieoOBwmLEvTPqnKIa6WvjCTkeOLCzbhFFXyBuJ\npPuQvauJrjTHDToOKflMwUMzXohVJ4JzFa1p7FpxSQNBoxup8R8XrxPZb2c5KPHBEm0RBnWc4mgD\nVIHaqlGFPV3nEoP7H4VIdf/eQg5s+H+0Ri9ZMwHC7sbAKXC0xgcn9uwlpstkBDNGxfCQF/g+9uo2\ntP9KgphdiztXtU8LrQTjy4Fy9/c8UuPqJIfnR7QZG+70qYUnKlrwW57w5z1Dg9JDp/BGxzas6L/f\nXNQnHYgUZD93BjOkyXLRXh+SVBBxyz1/z+ldUW5PAS3AUADQedthvQGxSsuGajjkM0up7p8Je0X4\nHnPko19DLKe5tRoxeilICZ7qH/khL2Z4CsjkbbDEO3uXw2onpI/JTYjEncMQSi/UEK5vW9PuRSpl\ncbWiK/M9VhAAjEKu1ACF/61SW/3pYKkCSxK9YrviAZdox5wdVNk9xmOulf27bBk/y/5yPjNNXbnC\nHwdZsDRZ4UUL/VEAfbqI5RQLXfOrU9rY6KSMLfsB8uSE5dnecPxE8eXu+QRrgOY9mF4kokJNbqDu\nKQbvr9FWHFPcG7ISMIlaWWlsfY0Er7Ssqv05ceTYSJIFNNQ7QYVCaDPrhwqG2C8jrisy2SpheqrV\nTyHaBsDVTbPDr6OoDJDmltk/wyUZbky9LK4COkQ1GPKUm7oEDfOi6DzkzXkekaJGgkIV4HvBN/w/\nOL2l7CXRJqZkjSkQE+kaO0yvc8L3FaKyuQijd7rvyfbCO8mRvd7VhTa5CyVmmkQzeWIcMiQgW+Bg\nsdClmBgF1bOnVP1hSBxjmkvB204KaBnb58sATqw45X2ciZeekcKxQ+ij9WNpFHvhMjVGAAitXRtW\niZ1/5r92afY3UxSdBGXcXT65iH7UFPJThAYQdUzL8bEnIh7tmi6YHV5Fpr5B0iIYdkVYYRdFBjuP\nqbU4ZbBszVxBMiCgjPnFoAn0NwG5lCYXxWdX9+xoEO3p/optvKIUqhgSRtpZaDMfcHgsEYInqnUF\nype1KMm4+dowDvvQL8HNYKlKHST/eBgKtyDv6zMyZC8N1nF1UozMaDN6VqBI09+YbJiTGv65knlL\n7LJpHeUuwDaFa93SVsMLLz9TzybhSe4Fmz239Guc9gmCGdKmj8+D65k6YlZgBj55a4h09Fn4WA/S\nSMoSGuHsSgK0Pa87igKtkEpaPLKeR07A3ydFAE4cIGCePOxXQktpEiLLmrehjNgZ+F7KyrOFPOtZ\nZI3YKzmiMser2rfa5QBqnNVggDLG90KdPfhei1qiDNSio8ervaSO7sTUxV1LnxM4CvsBx7gpCUaO\nketElJm7attR5IEoABfEWENofP3dJtPVwUCe9YNALkSUz7rnrR56gH4kbBDZSABxon13DqpYgRva\n5ErYKsRwjgX7R45M61g8kqPkYiWJjDNfQ9FLY3SL0B/fLLf2IBuXIffsrbOO+Scse5Cn8csEfp8p\nEjlDKyh3SmUANjiC7Ct90HHzcWm+Bw8Gsba+ebYOL4RYZSL3+d6mJ0wYVHv6ewtkV0sbCw2t1oSh\nBi38uhXBqy9x5PDvuA7c82O8bPKKi0yZlRq7UfYgpiHcsY3CyfDxwPHZjr5N8CPN/Ku2+fNU4unJ\n60TEb2Q6VuE/a0ISbYMudB89Tg14pkgBxml2Fs4lwt221ok8KTKXTmZYIDddfdDarL3hE8wymRw5\naOdph8pZ2XsBf0c7ENKuWcMD9kpQytMJug/M2EETAR/lDjZGhTIMRj55sAyaHHHSz0foJhU88XSX\nHuHA0E23uh/NiKabIuuzMfmoNRSvufIdwytDjCke6tGePDpcOb/YqSyYT3cZ7dgWVt60hmJo0yyn\n8mw1ES1hSIAuBskOs7L0rIzfDHv33OCvNdzYL4GLp5dWJdVNYa+m/DF49hsd+G1J5AhvIp7oxaRa\ni0GaZT0LHCqnkOuNBUKzQSA+Jd2NdhL96/92ficQLbnxa+u5qTICz4Vwo62tj/tqof5c/LcPWjav\nedvisPxJQUDMCHCH10JsXV1L8jbvfYEdUv2q9kTUxMMO2t4BJitVwtopq/ImP6ZmYkU1baH6sfPk\n1V7Jr2abUCqfJu3H4rhOKEhtDRdE9OBGyyoq3oiinNQo7A97D3+GPNInWdFREDo0SwnHSTfep+1T\nt1oV66P7/oMA1LC7e/Z3kT8eR+n4RTx1cCeyLFbqEc4igSRVFvbU5yJMbERCZf9Wvv3PkVSO1ayj\nUDpo0uOf3ROIyoP+va0dpOQOuY+CpHFQdHaR0gfx5Pz10YsJD3IqAy63vcxQ6lphZxErLQsoYsTh\nXgGZk1QNtFeZZ8jHvJ90jZZNhKoDzF6wXKgKAT+eIbq+p8DILm9fnJWYeRPC69+B52XLi7S2ULAJ\nDG4g/F09q+WhvIjC6jbWMJEARgG+Oh35uUjIBEWr0o4Rm688xm4YFA44//B0f/IJeVNeco680YmQ\nyw5Hqt8ulfY4APNHyhhiJMM2faLLnLn0QfBNtOGraup8Bd8L/tlDwmt7ZKP6DTwhn6SCVJRV9+00\nJw8gCfq3rEXCA9crWg06Bp8vZEdyQaa9MhShK99smwx2/bO8TWICBP4G6eR+HQUg4ids+euKfp4r\ncqFp7gCYgfjJyigiqPj+V6MODmVtHl6vYPT7hzh4jrCpQKYhyPM0zh+f0DNig0ZImuAQbLPlZyAY\noz2tpgQiGQcdzZtqKzJo5w07ddkCBXnxE0nwzJcSUV4Q8V6J4bstSNB1UiKDAixYkNuY9uWaBIRh\n1dDM1ZEwAnK8CgyQriTRrBk67URd56uQzZZUbngxtphO+cz8owlmcuUuD3SYTyH9L1Fp+/5lcSEo\nL31bQganLYIkovaer9K+MpXL9tf9UjajFh4R4aMfcmgu3qCd0D+m2j8NMj1BW+Ib3aDBYxmZwCm5\nQu5yO3jrui9spzEKsUQ/xJjw4x1fQyDf0+oL6LpHFDnUsF1+Sto1/hN8dea9UhvIw9UXbvKGejka\nfWeubmYzh/OcBSKYncHzoSzvpM/D/9fNkhE+Ztt8zoBDHTlIzMbkaOUsvyd4lKgCx/3TZhsIGfVt\nZhYBby1P55jMvWaEUM5YyT0Uh2pPPjWK44gjnPXVA6MKqYW81lTE+q7QODqJgeuwuyemCyaQczB7\nsoWF+UaZY15rQuEc8RAT1lgMhIynJkvVfJS+K+P8SA/CfDcOlfiL72NfNMeA4AQ5KWTUmBlkqJSi\nMCK9R2mda95lR0rkPMQ/8Oe0VAsybLFML5XUFziYmbK7lLTMxS8hcLoUwmeyJ7UTPlqeEeBtBHAI\n1E15cpwVelVl+q0CO1jD90VSck5ScYcr+ReWF4Qrab9ayVvWj5bdn+Khh7FnVDkNuyNvBGu/Xcup\nIYoK3b+lSZtIdG6z6RL1KOjsorsZvg9snQxp2KBmA29NWfFp2FtYrfJqtPN/PGAQC6u0YCo/VMql\ntqztyWADbP9a6Bm0v6WEPtl1i8hmNkCEPl+loWLBx5mKgXwSx3WKPOzRMs+BRpT01irZJ9xQHbII\n+2YaIHzmTAg2m82nqcsl/3JjVcA7MDC5gqboOdIrIaYFjV5wu1VUWCdKSH44ssWMmlvyH85UAVPI\nKl6dfK3HxYP08PJY+4hnFajFJ6Xh59kuiBBBhDlyim4yaMDSsOZz7AJ5PRBqElpsfGSUoWbMCoge\nDSdnpM6vJHxx8uEnquRkP4X8Jadn4oGXotwPGDxYNWwN2Atc4/kZWv/YNEPOGGtswGeqUMhX1oCs\ntrQ9nBCCONoj6pKN+mp4/qxFZ7Ha26NIP+cj+Rz1D1SWSdqfLkQ/00elrSocV39sVvbufXdOsQ40\nw2OqVbVSMVl1d+8NclLWGgWHOsy7x9KLTBhOrG5G6R36jWtM7gTQ8wR+DBSxXCtE7VmUBlYHDQ4P\nGMW0Ic6OLoVjnQCNbtHoZZ1NVBEONeBvbpNs2reajEKmpYWDqJYyzEs1XZJ/MGLPGBtKe4uX52uI\nZ9dwIoaQQ/0VzIdTIKTEmZ+nwnEjStmRT+zle9KuhR90hsOJfeAFDeuCrJWIEdYasnft6VJMTv7v\nEnW6Ru8OupEScIIcWSUvAz9O0Bvij1f6FDb3n/5JKNJPH1yORtTp/7j6fy0L2oalWbhpGR0LVcic\nLeHeh9u9gH7QG5TCOCp9ZcbNuDtJxrqOjkW4rrgGlv6RlE9MGwhbtZCGnwAqX8ftNqpbkHg1gkZV\n+/d+M5oZFIUPNNzorviyLOlRfTx/xqhUDzVRyaSuJwjtZRjHpNwKCjzhugneuWot7awc0cK5SxuU\n9SqtOb5hVHu5MILhBX+ZAQKHAquLKjdgsYxX3jeSTbt+ea+BQdAgsWHcv2s1m/lkWycd8Ho/2DfB\nz9mz2UZDtvmJVOewZgXc404QJ17q8N85cKqecRh493Yuyc56ev5bMQST+CnxmDnY49iEKdkanzTx\nGiK+6OXwGSkrJGIqi3SwQJiWFm6OvyAehgqAz8hjm7w5wzBLHi4evDfXqH0dcTB4sUjuujXcxALK\nFedDjsxv5FCMkqon3sxjdHl3Knj94Pj/wqk7Chf7YUyFwgjijDo/FEyg000kVAu7/BIQwecV3TUm\n5L0X68Uk9TS4X9H+B2f0U54zzKyomXpK0eVSOPjaNHQ//QyrIuHvJDtj5TjZy6Jx1x/f3ap/+jcR\nNh9FSr+LAjyrcpSr4kTm8aoUnDCB5gRL3dcjNF+b4LHSgHcnsDj9D9DtnbsirExVEbEO1GwWJxRq\nhSL556XGcvM0Wv4z8CYc244Jg/n//zpcHaS0ZaCLnMEn+pKxlshyC5X3U0TICiQFiTkVpu3KrTET\n+z+6a5/PochCZVReH6KFBDS6D3rU05n4wL6CkkMlKtGrZRyhP99xa+dTJDw3SRXJWunKXC9XJD4J\nBGwTWl0Tg9h/ekUlF+VjdwdHcZsjuGr/4lTfnZEgHNPBZwemG3r/PJ08gB4UEEMfEWCcoNT+znzI\njeGa1aC1dnrQhq+UoDtKJLWzNIYZrPap71QA4wCFcTCtA4UCwxNuDP4yOsl2LoLnAlMpcBZH+lFm\n7mKy23yEj5w7i3oOhCj84sK4uha+Y6mwsvh6cqkjBT8/LvECWxnU8MJhrrPvHnUjKLnWRlWeLyL8\n1KW1PMrDq4HtjHec7XEWRdJ/ZqRnfnYVHbwJ+AJFiPGJvl8hnC3yrnnz6FgYO+BhhgUU7Y6r2klv\nyCRc+WvPtmL1HQmINwP/HYL6UThJRab3C+FDrNLM0Ugas2Qf0tWAjBiT4I3m305ORJVyfYiL5NY5\nIKVpm7rnvyxpdhfINjagX6LzSYiLjHc737zbMkG+RwECbCIZR0VNRGXNN6bMf4LkO/jGRjO9TqrI\nLDCbPWO6STecGvR8b9GtquBZRfbdgGAC49zAq0x+bZiuXxRpR1lwKADdnOPh417alzMRsgfZaZer\ndkGsnwFIajcchix9cMbihVuPjSq3/aT4SCZZBvaz4iZ6xDy6jI7szGG5xT0Atz2fsS0vUj+IYn80\nqNMQ2EANfDqxdbr7h+B+biO0CnLyQNARh0hoNvlJDSWkOOZJWr8tAPWpl5nRsFvEv+Y4dhrbMcH/\nnz6OhgwWvSqbohtKpdUJdrQOAYsC551V9HdrwIbkipI38KEy1ApA9qaIRU1sPsQSC8Z+CPtSCTQW\n1hpTsw41hzWyBM17I3AKVKsT8ih2keO/iJrmtPZrpBPybiZlBwa9LE7t9+ijA6Miv/MBDw6L+avc\nxQYcJQQbgL1Fl8/H0CyMDOcXVIXqGTeMqq6ORsD4TylHjLwaoMylc+ygMJoRu1vjJIeJlFPFaGAI\nPjn5jp260LT74ruhrMxfHy/o4zzvPIEL2yOoTq8Wzznjp1wqz7uYbJL8C0VEP/Mxg5ES36HwGKdN\nynVMvv8qozbpQGBrnv6jN7x/fYV1JdNt2joW0OpNd5N4atx10OBP71SWNvrASDrl6oYzoWPoNVqD\n9t186p+Qey17JZegjFWol6S3JTzy5wzdjUx/+9KRd/TLdlU1H65v1BCepXn6LSl7qjdRgyOJoA3K\nj3hnKuaMzVbVN5i5EOC18NrHb/02YwTPtoMJITIrDegfKppAQhDwGotOWjmJDCiIzCcfqruwVYZn\nds9r00VpXrXcIWw27+DuqGWmR0bStuQK2IEkCybnGbvOZGWRU/+ZhSDUZjWihRmJlDm/KqXkhMob\nyFWkTEka8RO30PCHsYUU+vCD3VYu/iKJmHEcbmxOAuuLx19ftfy02sZ/NMnZCw0P8HHzVgGisDm5\nyHKXi9VFeVTX+b75BnY1K5wCg1obhAZ/ENSpAJ6mAucEWO24wRp7ZzQrm9DbmvEF66WEdbGknwG3\nPW0kShtKD8Y5LfnQD+R2341J/qJa9XggCrdOIFiwTxMWjBB2b94Gr7RkTqldByfsZAqo/YeybH/x\nx5RCftYGrmhj6N0KgIL7KQ3gTuW/RaujPzD8AoM0bW1bNxZ9e8/mXiQUYQwXbe+FIRYt/aSJFdOz\nrWpBAJp//L9as9QqWmVP256ugflyBGA66D92OW/uIjD1MDpXEulL/zlLSvJHeuhPkR/3ZT0xqCYE\ngvKzISbXOstBwGSOXqIpWPObJ2XeYAy9fZemuabVflq8uhSsAYDGZCZ06e/LrAwLaWvH3sY83ZQJ\n7nSdvfA8qzBbUP0i3wV84YjTif6DkdK5FM2W0dMSTlW1+ei868TDCLgr+pFqQfjSjEmooJ9ReFc1\nPFVWFIDl2PtF35dHyFF00Fz56xEF7iU6fKpjN5TLTD4h/g2BKmxXr59NSxMhsesAO6hGEQcnd4Qc\nYxYor74F3NoYNQZM2W5b/YJwLopvZVi64/vd6YR6dpO8GYg38hL5uOuz2uRfUEpfqxO/bPdzGE0P\niI6fHR0U6jFug3OKEWA6Gdvj2naGIPqsBVaSNPfrycBiJ9Z/fS1flwa+rKlZyX2aJ0L4GvJrwEUL\nJexcucVjVgTY4hFZgg9HHWBZt0XuFP6JNIDwrUbUvkTqQq0U22GAB8UfzyqYRSVefaucVWwyH9rb\nlA6BACTOmY0fTxqqqpBYhb4LD05vd61Wec9KlplvKdlHiMpfiR6kNlPkz/kXhRn4kh1GRAc1fbsI\ntIy5a8tDqHQlrMAkjfaZud/STLsLswPNGlfcJumIrOJVO190DNy09I00IsCRhPG4Kp0qsj6uMYMD\nDIY2j22Q6c59pApa9Zdq+Xnuaii8eIlp7xh430zdDM4sBuIqZ/eTpm+lmAloHtQHgE+Y3rqlN7Jx\n+aJNuauPTPIgUGkDyIxRZ1kte5Qa7g5DveHI6qr+P3PJdMO8HBcQeRCGS5irKEp96m6tNml6wBBD\nswOGPFJN1biASrk/enoyU/1xDhPQSNgwgeeIaVvd7bXKPKoyrGvGgcTxA5BZMyFaHKQqEgqcN96A\n6nvm717QA6Us1n+VQleN5zs499o3Y0SL7kXhnbEr+IYh/Oh1WBbhjM9Hc6D0xcNxb9TzAPin/UuW\nxXFKq1SHGOc8F6Pw4LUwsgdwHzTd1nFyFsXZoCHtko6v7LmqOrlvfOUJ6iRKWChxaD2loSHShOBQ\ntGERbBpdax6zzPU7hBjp1TWzdIiUOCTAaxsG1wQ9inw+OpxAj+96yVcFkuOnF3bQVg+k+d68k4XZ\nJWUsQUPDYlQCSV0cC41LFihcd8zOEcsRVyuVFbJgT1vZ5UvcbUgaltF9sghZ+42F+0Mr9Ru3zImb\np5IhwxrIfmIdSvpbe7EQzg5aY8bTKvwfFP+r1RGyTv+goox0WYVgv8eFo/PSWRklKKiZ1Cq4jRDG\nR0mzL57fzIcoFPeFfpLHPJe8kN7R+ojKRBvTU+VwuvKjJ+cp5THxXIskKLmPBLN34E1qPP8ycd+e\n5xYasWYNqlj5z4ZvWFeYViZPVVQC3sXQA8NBAhwgzMwGire1XLsuZ5xnp1h4oe0DLJVSCuzCIJ10\nBEp+y30/wxc7BRMxjcktz3qqKFRmG/H+GkGob1KvmbFeOtvGnXfbrciY33B0xsnQ8hlfiJOaBmPE\nub8Olcdhw7pOyeaMc7nlu287F/lspAEN2InuV9pKP89wGfD2KZoh/sjrHIU4czCRmt2NMTVvXKpf\n3dh6pu1ykmYsu8Za8wfONcgSEuwXlFR0WrwTRkvFjOqc377mSttWqTdioLpCLvyCK8gvXIhEtAbm\ncvCg55leklYBZkS0ps5G7HrIielJP+Oj4U01kpzy12vYJuVa63cqetyNqUoqdQR3hSbtL7joQ1kp\nST4IXvbiS+TBlF6FjiDP6apU+tgF+beKss2P7YhHgY8NC3FJZtlmMLlLgoJyq/KggJI0WnjxZa4O\nIOMFoRSXfxMgNcQokeDfDgbI61nbcZPJutg+fEL141SQhQCIt3USB6V8JF0LejoD5fAgPpQDorCI\n963+5jaqgloP1GupsPSuVMwpPYIZTD3RSiyLnN38s0/Ji6f2ioOIikDq5rxDONprjAyHyT8pz4PC\nk7EjTS5KpRq3v6kcAxJq2NKw+dzHrd+UQDsqIJavOLdQZ9r0RuB2vSYhJ94JwDPXnBh++9DKr3e+\ngVFWx/VW9j1mD4NU2oTbqhkQXVs1/7jrD+CLo+Vfy1TRe9nCSa+zZDFUGTsN1EHNyQBacZzk/eIj\nOpFdyXwRJhJpY594eKutRxwueZZJ7v695vgqA82M3CpFTPL2z+UVTTdZS7DOfuQMu5DdBfq5Fom/\nVgGaw46lRPnZUaZGkpyvQxgjvkpKWG6oNQRYQDxDI+HJBi9iy4FQ7c9yZdyighYrhFl8tl2H7erf\nGkDsIWp/v5wU08SLj3wAISzq6p57RTajq7p45zXJoga9t3ARt3yB1bsbzK02u3xdyGq/X2LGTS+m\naUg2TXgYAjHGSTxSD7Jc4YcP/45GcFdU/YFwSYv9+c8/XcxqalQx+OIqNOiGV4a1zD2Z+ROHQsS+\nreaUZvKcnXNULcFUKh85+D/agxOFlcYxZUXXq5oX4GY3dASBxOTJWXvIE+cuKAIjxc2KwLcZVXdf\n1PQmeSM37rlE45xUPw5NyoMObVM2fuZrgwrDi3+ZcEoHGhKkcIkj8EmY2ymPjkOhUhNYDnA3fRXI\nO6QBWx2/ZW51jhcuxcF7rgNJ4cUMfvQMIN1+4p0+nNAXNTJjbPCDKvL3sgAu17yJXq/UUkJenlde\nKsvHhY6OAsiYcLp7hY2Nra3B1CwIlHF91HppagcL3s9+aVpN7J1LanumPSWYiFbROfWx9SnUtyKm\njlXbyfZntHLlp1E5TApcIe7N/HM3167vGxOd0SbA2TbZE/yu1j5haf7+7BtK61wBWHDqmDR/UVCn\n+Ani6Wexdw2K1smlvchW5RyNzHdLTAbVNXcVp8GU7k7Y57zemzQBOsh3c9jF9ZJzincbdZ0tlBwR\n4Yo4eNRfmCFwWkA4emfkirdI0HYncUDqAdXTr++4JMSabwtfIWrpBtn0KKMIBG+t4E2umZuTAi8G\nok76h+G+EIDSHAmaYtUhVQlIkhCPGmbmgOxKR/rUeSYznlMmaclnfey4dHIioII/UNnmR0fFGSOY\nS/GFM8/Qs0cFAkigZ1thWNAloont7JGYDCozywKfKZ+Y5RxMhnAp2rCLm4qWWsbDL0Jac+MNQvp8\nhRpiwmsV+AHjt1SJUIQh8KZmJi4HhkejamYP4OyEpte3DQ2v1QI24GvKFf3PLQItBVJV6hCzWcX/\nRyTBEqKwpXHd86fsWWuyPqg+3exFYWzFsQsPlmFLdQhaIitaS0KgySksQvXUHFwQ6izzdZ1tup9g\nvocBe910UGrlJWhGRttOZei5RosbuxKewH+8Fzn2XKmAgnVGJ6wPCNP/47E7WByZCYOlXeWkprSi\njxW3jKSAAhjb+mU5V1F8ZJD/m+or3NA9YtGyILdWDoJo6lVoI8BhrKQeOmrKRirLeggR0oVQnGqO\n4s9D6JT1OwqS9vslOKYXbbVfEoHiAAeulbIItQZqhidttXIrjzifgmjL0LmnroCVNmtblf2Ikx/m\ns9ITGNZ/mhtapWuiGipe352VEfM4ULGaYFSKMfpJw8tSoITAxhEx1Jez+Ksyd07mu25XhD6b8xIs\nE/O+5oTB3d7Q7begVy0tgn7PPrTQldHO6KOu2eeWqFwXCcGV0SE+dWOADxay2KD7nvoSxWiKYK7q\nYk+kLjfnw8oWWhJB6DMtNc3iw1mIGWKSkDlVayOTRsIwH40LlF5fOPWZWU4OAMxVjBdZe/7b686k\nLCT7Ucf2qQqgmSHBZA83Dtb/9IrWvcLQBK2EsKS6qdW8ufG5FwoajBG3xAfjypgan8olfZGOej9K\n73nTZvBkR+MR2Uu25oIINPJ9O3jcboJnMYB4WcElXuoSnTk6o4cYakr79f6vPcQy3I3vuuuU3KHn\nFaQw7y6k8UAJVEhzTiQc6PQJC1vEwTbJLwf7bsMiF5sSPbatJt1DWvzyvIeuemO63deRuvWUGxe7\nhOAGz52FRW5M3vztGS1rALU/YvXMheqRl6rIPnOncu7sdA3MoKBMkyQ/6iZvgarQCf8q5H82g8hF\nW7VpHBDKd4rAgcboWdwzsb0xOuF0gYkHtawiXbrWMFOvKxFP30HmG4VrPWPglVB10gO8DgjJ9gPe\nDb0WozgPZIXCnIgeEf9s1Mhn8YQ/+iAv++ysi+Yv7IRIp1904w2yyosiGgZt11n0+8lebqRBMKp7\nKI1eLFy6NQ58Tgu9W3zg4jvyvr5NrqMC/FjdzkRaeQ5flGSvbWPq0ezI6hZTVyq9HMp9GE4EWL/d\nKAlOaT7f2B6nZZ3yKB0es49t4NdF53sfo98Boct6mFhAfmez/cTV5C4pWPgLwuh6viLxKZ0k52Zz\nqJO29UnvGFW9vbYkxkCrM+0fB+dzJm1AHvr6G+aGrdfZKWY8+O+emPaauaK/cMRyzhVx/b9Prt6t\nWkafcPNgulVZQRm74FwxWd6DvpSuvAsPRcNqODNBhdq+6O+rYD0S6BIDjBQRwCPmB/CV3XuTCyLT\nZSlxoOe3PXKYhc35qXGm8VNS7SR3GSrd1RxVrsrwiN2wybGnPqU491klZcwHbVXcIDNP2yc0Le8G\nSLt8KNJBAFtxpx2rHHHCsr7NZO481PBRErYBmM82XwQj6ikix0dxGQNrhSzyd+mjCfD4ojSldhBz\nx9KFfWl2ZHzSvauXWGjxCscnl3Vr3Qo+eLetVOYVITTV9+1XBk0SC46wgJlU86wT5ncSkwEi8HHQ\n4BvBHtfeZu3WeTZRI0PXL16EmytfD2FwXYk/5pPXWa5mrpBE1Y4yon9WXiB/d8fTFjDmjMGuMuHG\nuU0yYdj1fpxB+V2QomDndjUKlIFf1aUyB1RjwNtfNSn5GAZczee5twEQnrkjbcZ1+Qjgg4i35grl\nR+6k8+2FDWxax+wMunBWUAVVzr4otM5TaQptq3SP3gLUFbxx50N8gmnBghxmjuZRadb7UDtMV36M\nKJKecRVjkOeFVEm9bFtR+ksmICsSWJ5KKzHu1f4K105UHqdHgxcaA4tNOavKT7IiJLOtdsBfz0Dj\nv0A9VG2uwbCj5cwFrsNPJAYkMxRvTDCVKLeECmdMoWWu3VKFBmCM0+pg5OFXqnXVcgjEfSDBbWO+\nj3/PLa3TqY5znK6CqCxELWwQRgIgsGtD8RSOhdrrV/MQPQZbxxkZ+zFjWM/Ejk7yj0oHdn+GJtEW\ng0Ek5Uj+8Jhxd/K71+2IuDm2SAW77ikTTXALW312sEPb5bZEo4uWAFlUnHlXSIVdKDFdqHrJj1He\ntC9tKQpFx+ILFqJQ8ynPVE6oMnkmtTA1njHij1njpPp4ecipkwqpfzoTo8Q+Y32fBViPl6Fw5gNc\nXu3TPMDoDfyXR7/H98+zvXiX41UegKs8mtNiS7hI7qU3yA1kdLGmGoVuglAqAJuCD9UwqdUWlXfI\nzPGRWUSeswqGjje26QCTAAzUVwhMqsV127ugyrlU1Q5WLzAvvNB11gCTKTnpBitxYY7E7lvaQ+eM\nxFHdH9zv10CEorXDWqWC84KNmASywgudS6VFfFuyLstdmnR4BQM0WKP2TT8U25m4h9BbqjNDAtWA\nPH6lZuU2B+zqy86rReD/irno6wXVLnyaq2EKmY6ge5cfudeK5HaJZXyVPk84D/cL593gR8ca/Gbr\n22snTt0qngZCHRQ1PlebyCtvxMsOCCFyFIhGM7Yoo52jNBWkWGPVPI9DfhZV34H+jtDXrq0ByUfb\nYQ33qVomT/s+HyAOs33klHbB60zq+l5+kc6m1UVUS176wHDPUU0C5FueWTDg9zoBjo76eLSeZZae\nSI2tqIDT/huyzrnpha4i87Tk3p2+uzwPY7bnhlKk6ehZRaXriMM9XdDUpjR9F8yT1NKVZo27GX6A\nRpqNhcBPElmb8lOUu0ysEVMLZuHzPG/3Oc9WLZPPg4Uy6XXcroe/MFyFpNFhR3voJohGEA8seM5h\nsB9NlGzuLuj6u4fLgpRmqTzKA2XA7c4kyxWU+ePDjmNclixFKz2IB33sy7imxleooyDiKcY18Jh1\nuSFyoRJ1NKLvaJE/Xpi6WkIyxMVzWlEGyqlh5q5acGpz9cr4WIIMtQPNEpXieR84YmElJKx7bMcC\n+cL3gH7zfsOXWo7CQNahKZKA/YV392CzsYQ8yfGwbKyvDeGv4tdhC4OGDZLZjV1Wf853//8bIfK2\nu9Q7tFbqNZ5+dD512Psod5HjqqAX8XdI501BgnpgK47xfiGWExMKLlr5AkSQ2+OvxTQdZg+tPglB\nKI+XATpoe4sY5z+0G1I0wMsunRdEEExwy9uq03oHxsOQq7q6knei4wcVk8dRuPFCGgY9NQiCrKLx\nloM/b9JZENjqqi+O5gerh/5WVP4vn/0qbHPpENIYqWxchvtw4ktTzf8CDcJUxfp9WPjJokpdYcWA\nKtEANIesMWWkje2rDAUb3r1x0AgLt9aPyQ/n4LlNG1PDisqdzSVr0Bit5DGhXzQTQuxHBLVFhddu\nprKponkamPk736VRLD7o1LLUbo4nOKyWgD2q2HR9X5Grm/qJdrbYPr7FVkNuGE418zp6m3zhdjxm\nSMhOPzvL2XUHKz6NPziEPIWON6AjOiPAqawG+bCMf9guQLGuSYu5iiOEuofKQyQ5MQDWnQnB9qY2\nnmtaJim4vKxl/B3gQsIZlOAloLWhHY5qL9s1Z3GDWa8te25u625JE8qDBYi+cKqRX7kPPv7ap+cB\nmbGhIKNWMyXl4vG8VkTMuZ9EDtpuZQlQHnJfJ+WPeUP16K3RrIG/2RfNj4eKTf/ch34Q/9Xomc8r\nz2z7YEV8yVM1E10oUrh8V91bFMGJekX7VtYiyRgpAagU5xSQVv0xq5v0Bqb5rfSq8I1DgAYzYZOn\n2TjC5Qr1QRs6ucpbP1ur38k0vY6mphYMSG/eN3Cnm3jYupaQMgu+QfH1zRAB9ckFAn9ikjMGepV8\nsyPHitzdCI2DXykbgId8HBExcnDUJvjD1lebZj8bc4h32DkpWkLBxc6167H99tcgnj6dFdvoFTi/\nY/6B/Q1N8kN0QYwrQlpKT0ysSqjwRCvJAjAioUeFUsOLaDnfakecL+KNMsMxZFHd3AxjytLWxMTL\nHduRuHYoRCIxw5ntaTVBraM8z8Ux7klmLPkK1xDLBNsuR9WgFAB9ThqI38K5gGtYSOhc2+Jz7T+2\n5dPCphbTHfDy2lJHbPwsK3mMFzrvqaAB32RGTVdRy+1EAZRonvCZfeh+yJIYW8eu0qHF5bF0LZBY\na2ZiO6xYpk0j9Kjs+YTcC9zOeYkHCvRtTQsiUw7dI0K44+5PVp2qQUxRBcsgjW6+DkElPV7cIyfW\nY42SJTD0Eamd3OHOwDrZLd/NfLxUsHZWhqrbtgIC983EtZGG8Pl0YFhT4k396BHCqtMDDv7PgbKf\nBQDw1kn+w20H0dPInAvxD8gVh8wiU31HOugdD/URvCT2/5CNS1TEja5hRhCjTGbVNNOx+KNYIr2a\n4TE7ZFz5Rr55plVRHaFAI8o8pMJaEqZ4PpkOH6PRK9FaHbGSzp7zdWwaiIc4oAEjOR2c5tqwTh2m\n0EACE6Gy8sFREiIR/h2gOAG5naphqIHhhObOYalVBD9R4dR03Whprl3udQBNX/Vv+6nf1+KYa1+4\nR2jPZWBxDfFrGnxx+/C5KQOE0GAYQQq2jdh4JKM88Q7GLYk3OiBy3MstoSKNkrXTGVmhf65taWyC\nSP3VFhupEb2qMSZh4Dzf/ILAr8+RcOQy2jId/hXjUO95ldDodZE1dlJdBnSHhWuctqUCONY7lq5s\nDx1A/ptVAdQtI3oLADoq5zK2XE5QkdFlD9FYpshlKZKe+ENDwfIwACMTYV/4jr8ZOysEdXkdJ+2b\nmfkuVU1B1JpzLnGDJzAYxn1y6Nz1RZ8mZFJQAldfFWYZ5SwblgqgKr17NH65ppoW7+YV7E+XGsES\nMpnZ0oJXwXqs7sUSZ8SvcPmwvaMM68HxP2Ox1ZtzCwzNXgo9UivE945mmC/qtbqcOeffT7fJerrn\nxCxY5GlYbs0srpwbGj8qDMZL0RyVV0bYSJAQXu45KpTMHqdojJC6HwfyzQ06bVHvxUUyGpbj0Sze\nV/z3N5u2Be9z+CZBN6U6ZQvMFOc+nY+LQT1X0UezZ4OQD4J9h5QhBlNxFS0z+U2lB7R8/+w6dvKw\n8o6VCSaqDiHwws02RvgIYrZFv5m0pBwQ2/OatZ4pR151ZrdcuFXEwJq2iAzvTwLJWBNHO0uDqcNh\n2pMYbIn8XOqkA4uqblrMXp8ZsR3YlR/HqqZEz0j9H7YJ5DTdtdyp1Qooynx5Cq8yGfEmYrLlo1eW\nh1NgGyTrklE5KMHEFVeDQGW5+2DBGDETHR3QsOQsXA99R0Y+r0ivrLsfY4liWGVWVBUmP5LQW02D\nuuk8+l6WmPhE9ANTA2VRk9AVgzDshjSBMt8RehAhRouGSe2NCOiQtbON6bdgF2LhExSac6BRWZPX\nDEh03UQb/bSPERF2EpYjvDmU25afBztF3B9QtnacSNNmFl3XMn0n5XK6PpGhX1gXBh2pDQg1x332\nsQcIyEDTY0LEoRrwRx6dhULnr+b9/UdzDuDzcA3wxbqoXLno4cfRllIf48pBihgCry+PZ9TtCZ/B\nf3dF7BleRJep2xVtBXD2/x4LxAjZxB333b9eskOAKn9y5i0eHo+K3qcAB429nDYIK41UWVS4QEUu\nEIOouDTnts4Xl10x7c0fsukiQ2gTrKp7FWg70Z0aQG6aQPBJuWwEL2Ue8tUcsXdZahNrYNifhmlp\nWxRJs89gEx1Rw0575I5RrAXl8mgc0OiCFx/BPNbvv7WJwUhO+hrb1vaHVUYncXI7C83iK3zVlT5n\nH4z2KU9xpelBC7vwYvBShNuBULIKCRkGemQ9RrEHQ9OMmaBNzdy7TGsXq0d67W4AByc2gqOKplnn\nKvcr/uF2lkN9IZNBG2EW3k4VbrzEnd+O5b1tsHumRJw/T3RrnqNgmFarqO2jNMdmObR8Jno0MUtw\nc7WlgIhyUGf2FJntZ6rglAPMS/DJ2cfgu6rr1QKrE/9emyNO0Q6uVnQzOz1oF3bxZM8eTqupa8R7\n5CaEqggXsNyxN4rfqKitj1VmuLojKUpD93xFJe0Yd++/lyq1OlrMwb3Wa5r1QIfk9Yd6NDWNg7Ik\nghhJOG0CGwdG4oObyxynsx4a6V8vHhfTyzRMtC/JrsUsnAhN5+KWnHuBF/0sSL4VGJM5PgcvqXLB\nwssH28VC7kR0daVMwLE0trhD/bo5mmFVshHrsW/BGffFJVsHUY/AXzjy0gaqkXVwsYXWMevHRHIv\nJTZ3i8PgZxeUz89i2zjyOvs4bj5udamhdFlys+db/u2x5JWa1xobp2Y+K1WDpRxuwU/yNnFDDlwb\n8M+FBqHvvIXc37RCROK5p/1JlZU4h1R2N1x6UTnFIB2vkh+L3UbKh2rJi9KJSpkFochecaV8pfBt\njI1ibNcM3YXnLvYxJOqnalaHDACsC8lMVwGNg4Tuc/2OAOGfso200pBHxoJ/n8/VE2a7J6uHm0kP\nxSzwOFIqtayZfsA88w1CMm8yNeITXgnlDtqxclI4uDOSQgSAhZ5zy+LazrvSEnaufHsvzBIkOrqP\nLEQEfFJVGL7Qj5UB4anEBmpnJumCZXR7Sy0R4g1WqxWvLu9jmzsy2IbBFIVnw+oOPb07ALgcEL1s\n7wKgI77l45oTlXRomQbrmBy8CghssObFOyT0J76pMhTRkCyDTrlDEMrp4RiVXrguyKJOyvjHApkx\nL9U0DeI5D4nCJiT+K63Du5NpITDnhiHuYRbTrvqqp/Hz4BZXyAKurYlW9fF7VRsyt8+YcbzZDnnQ\nE3teFIIpknP1zVGuVGyhI2vQ7CRBl2aGxbI3jmpYhxRZ9gHrL2ANkpliCnl2h+JxoCj6Oa/WCFpr\nU7w4L+bf9l39IVSWcc1et54ODsyHTVw2gQd6cqtqOCRnRfUMXfkss2EzalDvM+0Da70US8MIHk8f\nHOtrb4cLiWfRP/+fn+K7oVdjPfmy8Zf6UeB2nK5NV0aPUyYIy2R817kUFtIEGKDmsywPEO2qAlnd\nXL+ph/k2HtrFZ69itfP0ddP6i9hKvHUhm1bhLhYgkP135tpGN3IE1WkiG4uYGZiqbssoJzlz43aP\nwHTLvOzw3VphuB5lEpgk5lu9EeSce0xTRawi+aP+8x5/ShuA+GLdtns/Y+z1/UOWkrWYKTQrUgKO\nFby1F1ELutmwVWSGnN0hGUd9xWrp1saXQN7XoTOA8X5aKGA4vvmt60dTwCiz4u69WP1eARwDx6gn\nkWDteO48sl/tI82dlq0qIoS+v6owkJ+Eyh3RAx9fpDbU8YI+XOnZHOhtPABKFbqa+olRWZOr3e/S\nydki8HWPLQMNI2dsUa997SDD1YiA3NOq6SNRUk8jpL+aWBgK00xOdBt1KwBISSPwq8+cieqaFg32\nvxVSC0OCtePSFbfp7J+FDC5PYMFonoQ9I1cfLiCz3kGInQziMRf8r205vIg0k+5pRDnX13wy8n9S\nzuawH25I/2jgQI12LlaWsmCnapls1weLT4VCRj4ZDjBjvJut+2/3sNW8fcbvuLU+yp2pyYnmzveX\n1hpgSyRt133hpoVEanIilN0HpSrd078Ll8b8sQivOxkvAHiRD10SdbfbI5sxT1AB5JIPojAB3nAl\n/B5NX9bfGmj5172SXdJkUlMFumlTR24zCSzVyC8A64rI0DX1OlDiYMDL/mzfoodbatqbFpeClb/v\nuGUAIHSZu2vqwnSkGJ60RN5foYLOVuTuvsfyXaxqX7LGPzFEvXpUZ2pY81Jq0MPbrQVELCVQ7hLt\nyQbPEQ9dJNrRnG7nuFF5IVHYpaGm/TzU4z7YldFT3c6vHNIj5yn8Qolp/IFwVcxV/oNmycsIJGRP\ntx0KYlcf8xzOX/XTo4O/Zo5P6mgE2gPZ/0hF0l1xbvE6XI64gLsdVMY58+JeATRtQg/BYn+4ttO1\ndyCoTBzk+9VyoHe2TLbEyE7iPI45gnePKWH9eOexxuiUpZAscEAx7Zyc6rffqz7Db99jv43qjWJZ\n63/En3j0GnLF1EUBIyx37RN5iX7brZkO+VdouJ3fZVHJd/64/KlKXWKk4Ehy88tqYbXOGswj/qGb\ntkQBg6o8KGelZF5n3u39KS4OsfveDlo0Oto5UInJM3MS0Y3H1AoTNAFOxJN5eIhJub202Euh7Dd8\nk7ZwWevi2F8BVAzagzt8yA8qjc7tHTUniXLNI7NiMMU4/KRIqdo+H5fUe0BGrikuY7tcEtQkCj3K\nSrX+8v8nBnnJow2wub4qC8/2v1XrQ/Ues2dUUeaxmpN0yOG+hTlQjd2l4/5lR29k+plUpUV4hlTv\n+aEFxYUPG8X1QoIi0udJFj34ZPms9fr+Vy/vV0NtxIDuAdoqdm39I4U22v5mx/HQ3t4ia5siibXv\nV861eEw2Uznl2n+Ob8noCV+y+1pmXeyxsIEqM/LqhxcphmflnszmKZy4FKyIba0wTKjk/zm6xYwQ\nsuJ6PfGVtOq4DDeXmLS3rv8gJJa5LGp4gMVKNp4ii9GewtNQ0k18GegQWFW5Gbv0TXhkGAXoxbP3\ndciYElRpBPIL2IQgtFgTM3oLeT86nCAbh9Y1mlgOm+XbJWEjsHJpMgUsDavVid/0Csaps4QqNvTD\nZxb7kTmsxtFAMyvod1qSsLnjVBfoaaQUzsmDYq5o4ICzqOi1EFe1Zs++6hTDkgQnhKQY5wXdhWQ1\nqjA3JOAc01hAPQnFbnEz2MUkQ3pIxExlfmvj4OM+7NuQVQtttyJT728u0ox7vN411gj2UUM2QvhS\nIDQnXnFIwemD3k0SnBB5+pUZhGD8ku9xYJpKJiuOqSuhM7GPtUyZnt7KAsBQtEOyrgH7lNIBLYIf\n2uJ1lVtZr9DCRRzy4BQdRetsmYUgxB9nGlVD/ZM/MfG10GRctJgnCHVHDwLPLMwZT3tTY+nXrF9T\nMfOTtahlxQj8a9JKRy+2WPTYwr//jPrUNgbw0bTWkRI6pXH+pc207KMvaL2dkN2wDDdbp/aKxJ38\nTaCbVcMKFIbnz6dvPoVxd+4rt59CUZwV/GdvNQYIR50otPQCAsB4mdnUoKbGMTlvV8tEwYaUBvBP\nNUivPNFclb0hlrHWN1GSUwsQuipEeTiqIdN3/0x/Ny5SxDyA3O4JtxPvNXx2BTJQf4WLbyFXzjnM\nGY1sVutG9P8puXdrFXFo0a31bY9w0Z9bWDg7ZHURxAdYRmT22Qd58HJVkESE4ghoG2vKc2qqC+lS\nMEsUnM60PSOs/hAgb2K6Bf6bMqv+WWkqmNs9XZK1Yr1p4gaQTGCUGw7bk6Bpok8xobDTOBAm2SjR\nUcEL0tI5MAY6ikodajp+Pf1LvoUdSyBaVNb/pDIviFTaG2K9D8krmfuLyooAGctkCjivMvgbc4lK\nayzWuZRf1fsxr9DI7pq+9Rj0JpiKfSMxK5KMd3xP2PSUvTIg8BkH/x8eCFdMWQQtj4yfCE7N0VE8\nv51sdN4OEYBwEPfD/IuT6h3FEZdvxZgdjqjVFA+QAC4G2JREZLz0Njb3gWKgaYBjV66LL9eTm/P1\nMyyXkRaovXKbK/NkgiJyFMfT+DuRbUJ49KsNA0AtJhMFjxYpHzyRXdd0F/cjtMl+qwgWbLd7y9SP\nIxJp8pvLgZssRxZAdsYtU45bm2r77WM9HXLZo7llrBpjCkGWcAuMc+LeOlrcIH6lEysbO/B6GILD\nR4g8g23eKfXJp+xhhqHCiixRxXk8m+Wb3PHKrVagfOLm/8L90umoSvbtsL9FUT9dXwuyeJjh/JW0\nmPau/IetQmZb4ax6S+ZZwL0dOe75KVG6lGgoH3DbnAblSUeoJyGFsNSKhd1R/LGFaa7Uv06G/1aT\nwuYMX3sNDQTEqkKk2QdnpTiylnKierbe5q0T87fPOCgIDtbFE2upgbtAkvR2WC0wnU2/2oODguw1\nnLUSkq5EReuxKDWQWgsEG0gWcl3BtPd+YPytO0Tb6IqcqueCVmuvTJ+8q7I19s0cYr/NLlXXcDfu\ncO+yO0V1ah26k55f4wO/Uj4QA+R+lEfIhNDoigMBZber97IWfDrtETTQSmnik1k/vvemoafhAko2\nlhdrPxr58Ymv/8Jk8Ajt8v1+CmIeuH6yJ5HfDXWp7H/qsXx3L4vi7ESeQYjnR3thTakSQDdcZumo\nBg0j24SE7SnUQhUB+/RPadesJ818uByA6UWQRK2oNhWanY40LOZbwAB+K4PT5k1z27mxpHjHbhzX\nAdf3XpRe5hb2GmG3jMg1a6+LPrttYwwEqsgOeIPR0ka5pjBj4FzluOki/PoPwQdic9wyJm2WdWO6\nHB3BSOBfDzy0qHI+crRyPIX5mf3uZy+DbB4B6WyzLoYg8l+BeSxMyXGS8U/pJOshzJO/aUqb0iBF\n/CDtJyVMW0eX7a4dNE/QbCVrZ1snmAa9wXPSK9N4xrysHHitQVX/v83gOjb+VQFKcNU6CZaiffbv\nmzYrT/H59squxk31uLlb/9+hPHx3+OfhaluqBTPpNfTxyc9uqzhHs+MFGtYXchbot0ax3ZaWqy6u\nw1NEsVtGt3mDJatwuthfkM+EPFs4Hxi3bvifMylBqyy68ncT0a48JPdHQwMmEa/8NfsciNdYNwvy\nA748mTZzaCBQiCGzNcFEeUpknatB4fAI6NrLmPZDbY9lIbPiU/XhllmjGhac+ieNlRLma9iQcrDX\nEhrKgTbOI1vNBajA45sfWHD9ajIl7iG64/W15/n21pdgtYgGeJdXck7efwJBDRcyshGQfENOh2XV\nGvRhkcoZldL/tlq/pI4jKTRtfKUpMUNOiub4/YDXJMrYh616X/AbIwG/eUUKROZyB2ckJuTwl7k6\nNsq052zMHIpUslLybNLdMvlfskpZIi3jiaxESQX1cbTjq7iknXpOfYGH3w2q7PBACRSOlfoLL7gZ\n4bumt4ud15iStkM3gcB8lBtaLmbLL/VaUCApJiXP/yU/3GubXbl+qBHzGC78WrBeMV/gq9k2J+UR\nFFy2M6sk6kviQyXoUXKrfC7XFVNtOQvWQnDqaxNl/cJb9Qz5rs+KvhVvEooF6ilZ9b9KFeCqLQ5P\nnLd7rqPzHmKB54vawYCNCF71SPj/eYNbS+FgHO8PlufqD+7go2v9scAczj1DVSo2NnajBuZMIe+X\nZTOD2JsED1mikoPqHXfW5BYkUQLn366j3PxzSpe9Hx9ybKNTo4Nol3VO5YyDpclQtaOOJjiR8f3B\n8UtRz+TZhte9rwFxjFfAFoG2a0ELSSbSghGT8PoTRIC+/yiLp8KkFjM5K/QKH7LEpuUwkY7garW4\nFR5gXzh6kO26+qnvw9PbKZ7QwIDnZrxsWOFIW+8QPy92G6QQYrg1QIXjvR4A3XMCoK0c0Vq6f8ec\n6nqb8bLbhda2WBHP6cveCU++Wibqo6duS54wNctsyxAVhfCAs5rR4t/tLmjRw2PeOPyHlQ2b1JUw\nVvJUgyZYDHc6wvHx7LRw1Q6MaxVDud+LXXeKyPOtW088XzUHK+aGOvj7AvszVbXYEIG7LzRclS0r\nY8yXs6xC8IBUi/FHLdhB/fLTuwlXl6WBAyrOmOvVjSs2IT0Qgk+8ldKcOFqGOs0kvWjbTgT/tniE\n8zhv8Pi1C8/U8tsmyad2tnIjG2KhHasRR/v+WMLDRdKeLUE0sG1W5RhMl4qXYl1HpsW4HQkYXZaH\nttGtLswe2IQDalnFdIFJodhXuFnc1W7KqihJAr9kjynts70hlIpmZ8hETT3FDA/JpRkzBNEq9tHD\nsDayCdEkaq96dDm8nhoUF9cLFSW/VBg7ze0inpJB3yEAcAx49GpWYl9u0JiBzUpvVVOJr7kBvcSu\nT2mRH+Cv6yn/xRhFoY358mdX83HRM9QNQCLrm442gafce9kjPg7LF+nuWBgC6V5RSULlIlcpyUsF\n6IHshem72hmFOtJm0N9xqWKaz5xPYKo3/AjGQou7QcLIjNZTf0EQU2bxAxJRZzFwNVKyDyP+lWP0\nDAmNFvqgxJPC/yD7pu5H+nYOKLOWQ5DV+XhkQn6Oqgc0ozs6ZDXNYIKRZhdjXeV7RuGEYrhVz+yI\nnQVz296PN9RogptpirK/+RrTMi997KeWfaGVAEB/YzVeEyK0dWANL09HcUg5xS7pc5sMc5BgkbMP\n86v8xxM2ueRJ8IEuX4dtN5pLthNaoXceHgwvvY0+mzx9qXek6PlIf3acRnjuX+EdYh6juAxq+qWq\n3w4TVVSYrW0nfJh6u94+9pZQtMsZ0owGP1EM7GgKESTZBULXJrmVF3Mmjdvu1VKNgr2ul6itxenC\n57fO0fFqOKW18nyK9VPcsiOsRdqcMGXgDHtnCW1CakLLfXZYTCMEPzs/s9qJnv/k/PKNo4YL6eYq\n6nvzObedr/aCW9HICggTTn1tExK5sZo8GuAyxzaWiaH5L+Quunlz/9MnTJa6yuyWjgztE+l8sLuw\n7kMoOxKYZFf6sb2y7nCi5+MOc+jdrofiO/zDTompjBnOZZE9La3RA78ZZ+VJz+c2ji4xe/wEn0ja\nM0Mcrc49uht7S0nmpdvr5Ih8HTyym5Syi5LpJwEQPLbd+hZHjoflZcVTSnHKnVgIYTQyhfxNmkUv\nDa1X+TJLdEmxuJd7tu6Fc2E4FDWELgm+u6cs4AubDxLg77h0FWhJ9by7eMIGmRTrFTlvTjNgk3dv\nyVuUau6slGv+IS0QmoC+alYLqi9+AHeS23uN37Pe9HN5ep9LnWyUBorvEP7CRX38Diyb1M6oAiG5\nUZFC7SqXoTZazVjwdf86qzQ92fctB0GSr3NMEAlBkQFYqQ4oNQ/Aiopqpv6KF8Qe85pOrB43Yy7s\niMwJARo3UoeNKGBHaeYLonnjgf7UVwXQEeVu03aa0clSy1aBH9IhznH68aWGyz0c1pCerWY/EdeM\n0gxRjbMoQtZEuZHoPJvfG0ztjpCmsDvodj70AD9Q38esdJCQvXD0nOZJ7kZWfFw9CuCVJG++3+96\nf/FKPjAkSJUsul/ul2/g5AkrXQCbH412yJwtW1SlBoGwAhA4Qeqpv8iS7KGFtJZZl9hB+kJs0rAZ\ndKFdKpCXR2NaL4DbHJwrSGfKXu8uSi8LUJVc0XHmu8yFnMuV6UMViXHBVCodlZE9ZxrzS6FjBZ+0\n3wgt7uUsnmAGA41Z5SOxamryPL3zK/KWYtHcC4+oJaJ+3nq0nlmaG4NDA0iS6wQQePW5zlNtneN1\nxt1yhxpnizmLoClVvzo3dLJ0N+JTMFAFbiDP3JDedfdisd6Nm6BVAtTBe/cXq3CtbXY4O30vRQy+\nemqOyUdCmvSnxrHXbqSWMQNaPQDgJ3lH/9rUa5R/mdSwPVW00i71C+jP5SGfUU/qr2l9i4HmXfhg\nIYNgxBQnnnjLX7Z0DL5b++IwGErTKGoxvBpVLpOK5YgM6jAjfDN5z9lBtJUZMqkRJgkiLLXpWrk2\nOEfc43Ow1vfx9awQgVJngHLx1hI7WloldD2ITLgjGjk78Gnx3tzoC+LTrg7xQnNjghCrzBVdNPHh\nao5auGhbhg/+NcuPW3vO61EfCCyIhAot/9bi9pcd2k51Jb3OiMIpWRjWuHnvG5qyHtQmhHgC8WoK\nk9ttMUpHJnGdr2xMzjDqUHkY7Fa5XAkqU4C2tYLe6sFmJ3pJ1VeESSmCgT7xxEW7dvUoXZsTYdqu\nYvBfIooVeh+Y+wxfbeDQotu+kZpOOig4ZNMocYBiXsKTfbysVEL891hRC4hjBxb3qUM6EptoRyng\nQxGVuWN7n5BqMAEy6doVaF9wkHK/f4xTxzAxODn9AF11M1FFn7MV31T29o1qzFwHwRAtAd3NhBit\nme3mQcBvh7h3EZEKG90GZIyY9Tv+rt3GmF1KLLrqjWPyPMWHQBTMBoiTZg3rcyRsdgVE3wjauaAu\nxna9b2D2XrnfP4UetkLXrfAc//joM7kKwZGAT6TjlYksZNQ3C2SSkKHiTxereNMqEXvMqX0TnMPE\nMI9Vqd8xbP9WHUNHrLk0VEpN0CsG3uorWxFAATHYzXwu3bna4IMp+KAA2ac7FqQimf9j59Y7r+/R\n/77wWqVTaTSn7ebXs1lL/fmbPdlTWcZLgqiukg/1+BZUm2e0+V8/g+aKDSu+gFBvf3bdK66aQ3T+\n4B6wvjRhM/FDHmf2Zu+ITpy3GDlIn1eNkHJRWtL6bdrJuHuKs84nvnFmlELaFK8j07ehiaawOyON\nGERVfufYkSJ0pBvsExuRqllmTd9U8BhQf46f1/zmrxgp1wDcrn3l+m2V4EB1W97125LTVy6cG2ZK\nN0KLUkEkuiTm+PTDK6RVMc0H8OkCopfBBJRg7WozCmlbsx9oA8BMGS4YT5zx2bspeeh60FDsrI3F\nq9m0prT0YnQSt3P0clGEpKIg6AsNvdJh2bi0qJ4IYkk58OH31MakF6nHexavG69by5D0hvseR11f\nll3bbXLr652kL/ZA1SKtJ4u8XV6cx0Ye4iZvq6+TQVQFUn472IMKzv6Q/omnqjDjwnY5N25q9Qhq\nUlz2SwUC6sHzgzwJ7yTPCdpLfNpCNUpIRD64U4aJAMtP1+prfN8sugWtgoz4vQsqO+NOJPubBNDx\ntQAwAQU/9axhO1I9nspJbRSu8YslxvI9dajD93SxcqbHeYo+fZiPdoRVHtfyUziYpvDywFuLA393\n0q4cJ7PFqsFx/CKBxwBr9429CUUO2THSNdQhdpp+thAR8ISTKBV9uKpLmhiqFLR5Q/cHDoZrhpVD\nEBNNmourvFR2eNSut3mFAlNp2UaI6kv354gab0lEAzoYkUn9BN4jgN5+rFm9cgmMOyBfA6eW99zr\n+i5VVkFLaY6971Sg0jOukpLfAKy1ExEuxKsoEXVeTNUCpxNkzWW5k/i7YAUekHdX1nwwfPRBnd8f\nGZnyyqD/uu50ANTWR3fMrPm7slqQ1VEbYVsKcRcwSXBkrgwzGdEJSNH7KK9XO8w8YEWlYz70T7mE\nHkYtOudrvqZOEfgwXkxUffF2mpUDADBQYlujBWAWOMbWd01UK6Xsa7ZsCMc8h4A9vOVMhJnETCOK\nHAfx1/jxK7HdUgE3ZZ3K+AkGDe93Gj4Y46mo89fEDRUQGvo3yPPif/8y5pg9guPWNcrpg7t0cdT6\nrP2gf8V2lmg499jIR0tz3IMwtFcofUWaHWuFte4KKTPJEx8nvrzSZKKJRBMa0/WrtnG4/icObm9s\nJiG2M4Esr3hFBYrbu5OXq82pQUbNEQed1WI5mxh4N3DztOq3rZ4/VqEFM4XfqSxkRii3PGn5hbbH\n4PqdJS0oiGHuWGVewy4kVX/c0l2rd4MDXggOjAJuO6V4It1l3Lki3wDmrx+Ok+ltdHH9YHdUQptG\nTWM7JDkff9xm5wNmHJqw2CFUxWuVHs4o0KrCTmGyiDBbiPafDOfs3TsTq/wZJbsJ4Ov2LvRsu3vB\nXHmTdydWZp2Q8ErXNPp1gU27Ha+MXGe4VIEYP42G8clXAm3VQtW4upqzdpUMraT0IsYwrjP31a6R\nFxe+VGB3rfpWYr3BmHIkVFrtqUfMc0fnDLkYV1iRbLP1xjsjMRFeNmhYSHfq95KD61mTQlMxgAPJ\nUdJyqdgw+QdkJSVoL5EIP133qU4cG+UiempgbXrUAzM795sLu0aELWJZAm/2QCc0pB1sks8T9ZFP\neULii/i04bguIfh2gwq+Xm4PXAhsKGYSd31uEe2sYGmL5KR6TFWHocPHRBOvt7k6lbeDtZoNx0ru\n9KyCjF6rAhGBc895d+CPCur0EohIKMpO0bWd0zWPw5Zp+HVC/s9lSGDUL57Xx8+p2w7BeYcQ9yfA\nX+ZKtB3/xOnu44j4HXRv3tGdUXjYt+CJVlF0n2/PTJ8jBanAR41HvkPOKYOp3uYKCnDBNRBIzzik\nvvR6mgQl7Mg90l3derFM2k7ToSSXAmM40O11VtaRcp13SenVecBa6erybM/yrGKSP/Gws095Ow75\n+17NqOsUyotyZCH7QPneHxv+Uhwv9689MvGvRGKw7kd66Q4gUE7gDwa09c+pPwBHwyas3SzdctsV\nP11J9reXU1byrTp57bIVEcT8mi+VLRROobfcjSpiJY103mcx6ax4E9Vl3abBLa/u71A9/JvXSshk\n5y90j2bMtFhWftP6+h1kpXdqXM+vQyn0S4JqLCMZ/3fv8ATP8DodknjMyg1Uc/Nk7a9mGSnDNYWw\nsf6otR3FUVO7CGnhl0DfckCkh+1qHDRFKVGPybrJufQoKs4X4zHINK5RlYTVL+FvKlVssJ8JL9m/\nXGXSRBSDTQTVIMhdd0Jh8nbKFnpSZOKHz9MBFvuCxHTtKWJrF3QvTvxVXU2lcEfqwW6jN+2mj8Di\nc9XxEuXYUf+XZZAnbcqWWxIR/hu320cLdS94jSTw7n0CqXq3sgkXrDfUFgObfY+I/aem64lq2sBu\nDiLYX3H9bhe+c/6o5FoYItSIo5gouzxK+QvrL1U8q/lIpldErVGYA5eyTSBFPcBFIf0vL/BV36k2\nHcf2/Xr4ofXq5PaCZ0trkSckdyAhjreBLkWPbaOf1wjynhYd4aaP5FEjuCEvIUz65iNJttlLRnuT\nSWCFpqC6UO5VU4dHGc5UOIu+kFHhFPqZtoYKkcyqfm1PEk/C5YGG6hMG/IeC95yQdsO9R8Zylghs\nZasjq9dHt5K25vr6h2SaDO/rUe1Ocsqo6i1Tq9qe93i9CHCys2bmldRnWhWVTlV6q90qYPNjGv+o\nGC+eQIZoUqydXCZpq6l8H4jKN7AAkmBPVw6iZQ7jvmmyneOFEE5bOT8sqAdXil4EDFnqsVDzPxLB\nXAKfPyuDpmohKJJBkpwUoilAF0aG+Rd9P+lOWv9jF4xiRMe6kwMiSEv5Df1yZ/+vIC96BxELp/59\nQb9dw/uc0HUhhgli9SmbIpr5AG2tDKChQSp8ClErkFBDV/PJPphWPrs5MQQmnHCL7iCGElD0jImd\njEctICiHnCWGZbivxlNaYNenKuOW6H9ZgealGobVhW8+ji5LOWYVOyjL58VcqhqJxDLzVG4bzC0d\n2+jJishkr9dju2SVeB4ScwaabTYq8b6RwDmn4sqBc3ussg6soGjOvNdnjA9MYqnwyXAi9wgbuX+D\n2qna6uxq6/+tcqxyOnj5P36eQcYpitAkEPs7/NrqsqYuIfvFmWXzF86bdhwrbgqjZTB1VOhe9O26\noNG0+b7LLFj7NNeHSpPygP1YhAcUhU/7I1nv5DhQh8627140XLcjBJUk4N8jD9Fm1hPFYSxOlkV4\nQIuxtVa2jdoQyikSWnshLDITAUI2uHd57yH+NAnTAqlwLxizRstBogiPFDov9YlGPoA9eQ1niMbI\nQY1xL2r38D3s4cksVfMRTzD1xQCoP2YCaJwCHXKtYzpUiovOXcG1YST+JQy0P90Hlm/QaKngFMt5\nS376eqVBb1yCqiCruOErnLu8oBXAmjor/XZr/6E77tuNdbPExFQapG5E86YLa9eLNpNK7WweLoYB\nINHmAOr0+V3993Tt0snYng81bMNBYfnOl8GMEvqF1ELs9C9O99ijLkJZ4LBtcXFXOs8uD9kwgTsa\niP/gKIS0M3E6cYjQA6pUdh5zXl/cPMJ1BiPM8hNkzJhfkF610MKP4KhhsdZ24SBHhqSEFdS42Sg2\nz5lW3oHVbl6T5cvYnA9KK5sr7/iAYNJp+unFC2WVGhdAWWXeN9OUMHTfyNQ5D4C7pt4tiNTg5sq9\nN0NGbnKHkhO4VVUQR9yIZzmSzVzceOZAx4F67KRuxDacp2zh+gjltVLeIOkeO6TI6xYiOMHAQoeN\nab5G52XduVR3pyWkxVDjzToQbnMQAuAOqLapz84vE0IR4L77Baj0m8aYIXxe2qkJbOJeiuaumefc\nbv50GhenAWxrXrFeK98vubR3EHKFpF1GObKWXx5d9x0bvkf8SlptC2IRd/5r/MH7gTfYlv/8+gK4\n+sYKpeLNlr+akRtbwfDTLV3mwM3mkAvFzAFxSCODYcXrH0Z+rPgAzfsWm+phe65IhcFcv4BPlpBv\nWrUq64JjShUFVZBeySEe4gO7AizaWcFlPxsFQ7UKvNDwvROR47OdEokl0QU0mxLoeSwdRoa2AoHi\nh9DEqW1Z6dHwYG90WRG6DhTFfQA2kbBc2gk0NkSbDom4ILk3HNDgeUqcO07nOgOsAa0NXRLD5hdX\nRy8jepbFwrJMKLlZLUquzeIhNK+fL6KO+QkHN2W0C0aQqzovyGUyx8nqgxWLS9BLtMlhpVMhQPMa\n6vJddPckC12CjCzylNCkZ6oVDwhoprp5ynJyjoB4qFvvbvgyHNZ1T6nKNh7+bCkaS5dpvjcDugWx\n3ubdqv9W+e2nxCeOVO8YfO0mgjPnWcWeHIkHmeK363wpDsyz2+DZBSFO7lIUNhk1n26ywJnYizfq\nKJCu3fJ+gwiW13ZV3MkNuotcOZfCOp8bboXmIzrrj6bIbDHB+X4IXNd0EjH/MStuOPoQpQy2iqeh\nq8MXlZZHOGACiAExB/LJ+k0+4dNt0bsk8PACtIHzcnN0raqC54u4Ffu/L44jBE+LqtS9lIpYHfnw\nHWOYDMAVLEfEoXHheqHaj5UiubVbkLSrTjSIHVaP3h7sh6hsKCdOJdoHtTeIhP+bz7ZLeazPvbwA\nC+wEisSpdYb6J7vvruHW8FqWaOuqppELuuPWlzujq/iM96nHYaKer+xNxy/JbXAKmT88Eh9LAGTW\nCcIHJZjy2S6Fxb1s3m72PVxg8MTnH1S9PHfipmkijh7VNwGJxPsegssfqyCL/oGYJIsdUyTkRQXR\ntUAG/a2xm+5FerLIukGJAOE26J1zGX9cuTJTN/+sSzLT7NpN5yf932uK1Wgj2fHf4plhNro0vSNQ\nonr9h+lEvQLp83kApF3HcoIxzphPU7hsYbJaZB0OjkG6X58bu88MipXM4SixC4ntYJR9kr/r1nbp\nJ32IDHXDAQbhqMT5PFv+u/ZoLZezdwONMjH6zFSiFXJqfORX3K3RYM08FKX3MiXrAVHP5QlJyjrR\nUzLOU0ZBg0mDrb6XEJRV4RtgKuMDPgVwzPOugpXDd0Zsrl9DNypytXzTs8UX1s75SBrt5hA1hPEb\nN2xfO2UbxvBz9W8JRSqIYU22gWUeTQG7G1ZcPDWMBKTCAQYTtTHKdKYc07m/us/7kZDHyN58BQAL\nh8hJBNPuk6t/yTOl8xU/1cUvHqvIH6Q08XQJhOOvM6C++NxNTSFdlb0vwqu55moKce8F8wWl1Wun\nZOxMHiPaln8zIzWQNr/cxOgHobDutwN79ju3vUOaz1H+DEs19MNjm4kjVmdwZt7VFBo7tDXjFnyk\nBrUQHzim05NF5xZWT8wFjIPVdS6QCpJmyX3c8KQdYUczORmoD5jCgXUwhnRwHVGYAGCDWzaZO3e+\n83LnRkKKQrfPm1UuLir547VI+4GSDHcvAGeqKsLTRUpsR11w3bx95hbi2EbNofWd+PxGv98KbqL9\nRXUb5i79p9qk9ppWW2Dlzz12VaH1nhvMv+DTrynFhVM0UaOmD5+o5bB6A80U2lF/a7xqXQP6lDvT\nz5VebcFwBl98jOqywxKc2rL7HAYPSXM4arStlkE54/2dxZZZ6PYINlqovQMediCAQ7W9tIhvax3F\nhBExHR1OuBhbft8HXh7y0n+fixAbJtbzGdjQ8eAt4QhL3ZprOHnEzCPAu0Z6tfGpvhwIAgnC5y9j\nZOfuESAuC6dFfmItiWVn8MZOlNzJDmhGhZjRnvsH6sY66UCsIbp3UKxgwN2JpSjhbRIW368cv7Qy\ndmwPqBsbFH4YEVjW85JpmjvczlcgoLihLCDz/gbdzqOUmF9ld27J7tKTvYW433KZ9vCPfJRUSMsQ\nWwfaF6A+2Defw7QlRld9aR17Ejn1Ox6qvfqymPlpn6QrDpbj5y1evYy0T8EASH5Fl7qmcpM5vzI/\ndH6S94xAcVWkI6RosYTjd5gE/QtwlgnFnM/lJK2k8V/KnTvjE9wO/82AEZ8VLkcsqffEW4gBQxbY\nu2h6r0hWUMU7cXEurst/L78Kib4COWu6nWraWjqnbU6FWqOjSYXwYZ+/xciD7rXU2DH4sI0Ncu5K\nvOznq7OkE0oBP6Bp9mq+oHMqWXrxoIqlrZgR1co+t5qvnlhQSNNCGd/j4Y3ZfBnmHSOibLJrIK7g\nnJOtXfqZif2WazoNAwfhe/KnbP4t9TywG6zcO/8AuHPEKACKPicxuqaCJxG0+yG9SbgTJJZxpYdx\nhcdlfLSLOjsIuGhYhJdblKWN0wlyxGKWhRsZ8VB+DqiP9bkqcAISlp6IWTISQjImpfnHmxWd1HoJ\n3qHYm25meGDrFRP8rNjGBevpiNYDnoa64Az3EUNSdOYlRm7GW+KeO+EF6r0lsmAI0H+kr6tDYGRE\nfiKOG7JDINd4PYXsThwviNKDkU4ctEoLAnJIntoNwmkTUkn5+A8xF6IHYW//4Szc1iR6X6I4kpgj\n7w/6KPpK/z8i8Ne0d4ujhMYD6dFhG8UliuQ0R35HulWbhD2+sarpfuf8Jko2RenovxICkuaCKUl+\nGYnoxmpxCmy3iGe7gT1UTG4Bs05s+EhNL38FuwhMTq2fZ0gV6ZG4xY7FMWKdE6+ma1LPIfhrxHcr\nnLt3TOweH4CER54SHY4t01+IGppmGBrfySMddSuCT7cOX6FEb85rjJr+DfzrwdtoEqyr39mJXpPp\nPp0gdtEglfCH8UtYIWAAGnJYxK16tXlyDgmjYE8SoR961A4jNciKw/u85KXqi7xrGc6aR3VycHp1\naEtpbp7Ggj7Bfk817oyB1MCNJZsnw10dxSKtguykSaSl42mDzR5p2YcpQwvojgMt4voX0wF8rh1d\nym588LC8B/Gnhki9eSIxTD1d6QngSiJfHEDfLWYeFYMq7z30t9J8mJhhcjwBH/hsuY78l7Is9+0L\nrG14hpWDPazAhD/DwEHu4gTULDZfnSt2TgU92R+tcpiYUWigfXJ5JTd9x9MeGbdN0kHZV4B1n+eA\n8fF1cajC50UHrSnmZJtTLuYf30MCyZ2B5YHTUAxfBUdWQmXQcPISYr4T/KpXYK/IGupCM4ubvK9g\nFQbq058Ae7U6xuY+imgsMKjylzwWxBDUxokuqE/S5ZkQtNztuFvE1T2k+I7E1EWexrZEWLRkb2ki\nn62NrXKaJ54wiGqPa2zOcvI3tk1FPu1IZ+E0ZP3Y7kBfhIxKKN6awqmCdkxdf6iSCsnYwhD/t4b4\nXapsQOlsN/3o15WoP3jyLStrsAXaavjBXPj4bYDRsxynJXW5JLtvZCDrMjzlJmyNfKkEtEuCKehI\ntitgHaIYordzzXGVrs5H4B35SxOQuUUAkW0clkmmXiut0MgOPmD517H6jaL5XB8LZw//pBDJLzQ8\nFn7gflO5OcxYsry5wv4a+OWUmdixvyIbEXj36atyAoohPraV82WGilkCwl0ORv8VYfQqS0l28UG9\nUwLQK/kCkDrlQb2wqWrIE1XlksTzoY2lwpy/Coq2SsFZ2tQOtphNmW42rvJ4dAHPqzYAHyO0+juZ\npxtBHYPjtvU3CFO14/w3fEvLzk4seLvztFL71fSv+9r5OWoF9apx4AltXidqOQhaCuPo6l27BpNq\nrlgnEzgM2YmHbbeep8GNa3O2uMnWSCJOERpGK6wuboMEdKzM+P816I84x9iVY0A+1aqxvbhHCFlg\ni85b56eSwM3jMiAz7cm1zQKRbtW1Virzt/gOqU9G8eqqflvOquao2a+hG/EkBloL92mepxhGekuZ\nCCk20b2MhD6flhwVm+/AGiXYaDB6cmCX3dHd8y4lcpnX/FiSql1KUc4627hVDXVUG5MN7i/nUrri\n60R+VdjBiLns2QKq4NqOZr/Ri/7PTN4jPTUYRLKcSIQPjAcmGl4EfXq0egzsIV9IUL7NYDxcsMeA\nEvLgIl3xkuZFlBDiVLH7foJXfx/LmFIcfxe5xXZ+V84DHuWUk/s4XpMiVw9I+8BFnIbYRusxwlHl\n6dxGKyQU917KzJa0PFqLfe/eE1r1Y/HDjb5UF75DAYul0AS0bsPVfrj0SdLHidTEfqgJh/VoW9lm\ngqTm7yAtNPfV+4caNXRpahXUDp+wRpTLSwRfaHT+hJk/TNrBDLh4vl3NXedNCK4EnQBbyC1iGlGz\nPaSw8CEd5CkoUSp6KeWkE6Iiky3G6ydDYT+cKPhglTCC61uB4k45W10FP/mx1L5M+WN6QrM9qVV0\n5sUIdLBYtYsFm1R4+ahhK5Rw7SbGOJW+22w0/PoEkjJsDhXEiGtbTgjYn47jAk7hPSgwgMmA6XTI\nVKu9hnHNiQK5AouKKUNFjvVkTX3e3FmATSD/9jXMK/Pbq4bWy0riZQnv8EW3kisdtzLS274jHr99\n3jn6aw5I1/fvMGuFT5GlsLatT8nRWqtCXNFNYsUGghMeO+9UIvvumA9+9WngRZW+Tfsmpk3459ke\n3ef/ucNUWbjHynut15FbEP+uaU5Y0XNtT4VOswaC4OZEzlorBAk2RqtGIZr03BTT4xJhbh2+pfrC\nwM7qBrcgwT28ZyfHbkC2CQ45Ghw/Rcrk2duAMy2TyxBCXQZ1iifei/ZbL+euZIFIvc4AmwLOZV7k\nYHGNWV+AR+LJ+MkiPCK83efCBN+j7ajBmIFcBf4PdFEb6QGcilCxO2l4CgpXZKd2GMbImEF/TX8g\naFGZuKSpiqQtBoE6rnQf3pAVTV+aiKNdmdhdegAdU0hUO2LXLNVAE7YICBxGjv7NkgHc/dZKcFVP\nVWG8OsyirEMS1TCWn0T4Ouv+QHaqx6xY9eDZ/K39pweHDlXmrwd+njnskIrwu3Mk2U8WIQq2kK6f\nk5lHJRZBnQHVKBZnqsfWV8vyieQUzd8ll2ncpX+RAYRVk6C1bryUpnKFFkBvhZomS9eZVE9rYxYz\n7sHkmpMkeZA4nVo4QJ7ta9U6b6StZtdlmpV5CF8jfns3Q43IyVfRs2PSI4yzoWATdb7LerJdUoLM\n2Yht6OdSLii2tca7r3dsm5u+EqxqqOzX0ECxS4efhzEYdz3QcgRCHlDcOxL/8+bylJhb26xBpdK6\nQOqfAEqvE9Q0yeAcVGAN2hEOoB38J5Etx9whbTLk4nU7NVy4ynvH1Pi8loT1HdcHch2ZojxUVJoy\nWVyJE8jr8Kk2IRi5XLEnxzHL/W6gaAbTliXJFoUuaUi9KMPDCtXLVvF9JIhiTWPvXFoR6mFZYbSB\nhC5IX1TGlNdoofG13B/wKduT0hAsD9M9gTlcfbu1KCVjtuUCJvVabWzE5gm3JgM835dIR1IhHilh\n0FlFYESWkJ23pN532oHXPVx6uoBRUABoBAuLOeuhUaWljy1KAgaUIsKf0ZvRDfvOBP17fl6vBfF6\n2hGYywwOMS3Z5QOgpT7tDnGCqF6gKVbSqDQxXYRL0j2qvbdtDUULQNXud7pOxTckuyMB71vXRcKA\nFmq9tCU7wFIWht6VnnEE5Jf2cUph6yp3A67YuGIgcczxRYh/biq4dj8y6yoeOeI9CoE08+uXyZDp\nTZ4KobK1GHUGw6recpGD3GCg5XJAS6PUOjHPWCRQbqMKWG3QBsB26L5315v3jVybFaYfmz0w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QPDwS+9yfovudzC0qFzlQ/5WgMX9tflb2oCsodUk8xwSEtXxGFFMqRbntOfa3IW5mOdVveiNVe\njmmXzOwqszJMKBNdeB1pehFF2nTAy/FibFDJawAKwq8a4h135qBCvlG1Cm6C3+zUaNhon5M18m0T\nocD8UUb3kB1UXD1qO1JdFOv9vpgI082mtAiahmqeu5gSbrws2KUr7CZpP61CQHbBeR6jKlxEobOf\nI33o0oraJIs8ztxvspjoXSWDR82s5+HMQEJpD0RmiPEQdjLMYtxC0Q50wsT+AF9dipvrbENTk9K5\nH0Uazcem+9PaxrenetHL/wFzyt5iM+V3F3sBwpRDKvSye6tVXaL8sAUhQoM9+o0Y5XOFySP+qi7k\nvUjz4ToxQMveqCXytK9JAdaYYWQXU8gBgB1oR/B2IbzSmXgvYRcpwmAxJMpnHUdALw5N5BC6NKjV\nlKw6prUvtVL/9ZEyKfYlrx8Li7caUrY0rcfUyU7MMReJYIQGhH5SKZm8KcQBpUt6wWxQNtqrb0yQ\npSET3xO7N3f1+gjjUoWeUBi+EqpOncX+pkzTzv63R119uepd9cs9pML/ao3tKedeM3hgI62TR99i\npb2LzzOkGPCpvEjTkHG1OimTLVYrfg1GPCouf+5YQyP951LM7g5vlY2PYAYZCZsXLkXZLf1VgWVi\nXntpsTQwKbVs/an7JjYk6Rzy0fFFi/MuzM1ICO+UAp7S/xlyzJf4RmA/+gKi5qDG8B1kQLQ7HJuk\n804XSrZ14yF2HdxNi8gS+78ZdwGzTZpg1T62OdbR3IwUDEGJst6smf/gfyHWf2/384LEpRbRiMre\nilsxh8W6mmdVJDDAJ9PiQCRnKNran8xdMMF6nSeW+N2cs9ktanHCrn5RanlAaP2aXPjKSUjCe739\n8A7zvctqNvE156DEEtfk8WuAwwI/BohMVoWd3lSlLIKMhM8THcXZGodEHbyd85Jz7e5/2cyEec75\n+xbyYb75CLASJpNUJqIIaHjxjIa9siiJ4CWAH6gWapbXH5uKpypSQq/MYuCqgFnex+WGvEbe3t1/\nT8SSwxki+49E2UUcVIUaCwDZajTKIa6rVuUk2OqTviKpnzbDZ9HbaSQrEe2n9jRkQ3QZ7WKNzR/D\nwtQHJMnHzrYfOR9Yz7J/9fJtjYzN94cCRwH7i1aU0TDI8fBhIsFSKZVVLWsvbObEX+uQyRB46OK2\naHvRJ9+U/xeI0P0Pzkgs5TJcjLEEUlbNjRaYCylexrXWtJMmRFR2LiPk6PIOBltXq3+d8YIgo1Gs\noj8t7J9S02jZrXX3nl6OeFCso7wf2MlxMblEt3WvDd9f5WYIZQFDhSry/Jr4uR/9ZCzB3jQHBIXp\nT4vuCfvvMvDGIe107wWjY2zcChxQTlN1qaVFkb9C+GWjdmqUca+MMQEDCP9OAe0RqVY3FApxs++W\n0okGdZe1VGY1Fa6YSPevSikXev0tvPvzj1nYehflkjddMPoBal7ulIUMPyPOm+D2fcugyKp1ZERx\niD7SvB+Nq+Uw5Y5EKyw+PLI7+wPmv0aa0pcEf6kefyj92wqOo80oHEQV+Oofgj1IJSmbArjzRFzr\nKvLoYbsxQVNGOG9BRPRUdCsXqlpzlNqmDxkBUQMJKNLvhemAIY6JOjEGMNl7ddM5+J7UvbhneMqi\nIoOiy9AFk0mwflcflYlarKbuc3/H0ACuM7hI3vgb2T0emmDzEomLuUwPgvNtQy4nIAVDvmP6zO3X\n07Ka2TFXz9OJwkXC+MU/nlfdSbUHbTqFQUILanJb46u5JyAD4xjOaShvd0MxZZqqAw8+59wbZ36B\n/q3Uz2T2fIGl76xg9lZhW79ztBeqVpkacnpVqRfzsacLzzSHYQO3NerN/AVCyxRK8MZwmZISJzxX\ni1V41vl2UN67vSnzsIHe2PLh63oFs1TFcAiSZHWO/6D9zp6+j5FWYiZXkKpfY9WK410x113DOMEn\nMwNKCuzUYQVF6fbPRyQmgVqEH/ri+vnr4/ObsT5gwBK2VZVXaHNeAk0jd8oIsKHqvNB7YAUqRng4\nyviUjvMd4dNj/JQHoOwC8RSreloRNvtP9icKurlu9v4ZGBtEzMAwXl9ch+WPu0RpHUQqMseVcHKI\nQmxuSq33Eqntwqv18J4A7E9PoXej+muE60VDponBQMM3sjKjFlzka+1nqwRbLSPbEWh7I4WJSY2i\nBzfDmu+I7XWbv761OLgiZnNrEiI8vOwCge1FIh3jjV9Z8kkoa6nTGXZgZ5HBSWq9cRBxwA1TNjp8\n1/DIRWOZNcpNX2sTSTe76uGlzwpMDPeFIT2N3ZHd0YQSWmyHzQi6dvJdqSrza6ldNLgT5GMIAWqS\nEq2AmfmO9UF6UD23eT8BWA4Zs7jIspBh1Gi4i1E2E+24ca3GMgHmMsMxwtxoyg3/EpBeWaCC3VEJ\nOGem/582KEYq6FQwBlgqF0rCbdtjGlk5y9zpzJZblHOGLQwFMkXu3lXgWeXVpkEIepIEWTKPZT2y\n3xxK7kxw+/5QGjvVc6k46e4tToWIC0igecBLTITEvYdV4BdEgqNQA6LFHZHWlhouOXKp2zCzCsm1\nCoznwcCpdkXrt+uCgfsNEJSnP6JIC51CcpmosEtfvvTRO20aSsSVfx4aosrf2SvDwUmp1Wrq0h34\n1Z1iEYpr/kc/8p29pxW8Z2hzpHh2DbBuMn2aGgGv/QtiHPoZyei4PEy+HueqyJUyH8zYNHjuDzZN\nE93nz417AV4nSwYJH81tfe/fK0uCLDsYZ6Zvv2ZEGieL+73FEsSaD79xtcFuBG4Aq2wA+4d9VKUY\nDrt4/WDeNZO5xu9P6oCuwr89wHhlqszWh3pQlQZrH40IgyxW9dwfOaQwq+prme9dZeLej+c9a/28\nC3SqImIDIJEP8MqZaBq269HtsRA/dUp75m76mvayuXCAjS06QwMY3NVJOWhMgp6cHjkjLeV0DFXh\nucYaY/3H/IP2KO6ZJNEPgIfw/xlJaMhORpg3AEJQ8Cxn1sszjtK2qjhWoTdm+ZscGwwXcCuCZ7Fi\n8tFs/hkPxB9w/nemlfdyS19zQZGDmsQn3zb1A6QaklBTAzXkJJz7SYg3cXrjlFrxzIU/ioKCVh+d\nuY8UE7q0ENLE3ImnjrnBRMTsFtqM21G7mFBK8n1ZeMQAGY+a0etGe3R5dqRTwlrBAS0+IenvFfSK\nTXQiPr6Ym8nM09oA+4d7TGzsMlDhnPKXdbDjowPVTP2mepphXzC7Kdg3gpOph4lsUA2e1dfNSIz4\nROPbltfGtNYo/gDFgAu+0TkoYp6jYoaaSC0VZb85GW3EElMR0PHI/6VLne1YnoORHSz5xouhAKa0\nL+LJ5FJce6Jcny29D5VKGu5reeD8bsAgZmsiaXfMiKwOHh4+MxdnTmd6dGAWhQF3+lTrGkMWs9Bq\nhXiyXTcd4vM3xkBAbUD1KWJehZaBPB97CMo7xycYYQNF39XVf/hdFqb7/jrZcaD2Ld5hwhALW/sh\nezqyKc6+y0Gc8Jui2n02GdN52ldVbZPTViBl3QVk4SRaelGWfkBJGlIql9YXCjdqUQh4kqcu2lFv\nVWe9axwv8QRJjVruvjJQo8/i3DWRJJRaBJSHodkQG9OOw3tkxJpJEjNVWBHERAQc+2u8dspqaciG\nF/jRs0Gk+YqqG90n2wMz8ZdN9AOj0E9qitUNy8PSRyoGOYrD/0CaGrhNop6vwUVFuGDEWlP52WjX\nbtXPKRfANhYm6D8Qx/Nwzxwyad8RcZ/xv9pV/y3q8+F2aE3gUFIIb+fJ0sxkmW4gpNkF7SmFPrwO\nUqsCg7q5GdZNNAEhQ6Upu0QQoesBE97uqPHYbfLJLb+LcfwTw9qd0ra5voD7s0jNjKvSlqjz+WHC\nBlvJnRRRibLR4LY82oWndjfOfyYnI5pX7Sy8xIQ/a8l/89uj+7Jt1OlnXl35C3Rd+5ggftbe3O8B\n5eVlk6nvk7i/USZynhL6tI5VBTqwjsRB9iVT6oTmYpg8ONcU5JMHR83mzoDgzGsmci64XbrICD3Q\nX2wvwRj/sm3D7pEyPw8x9n+vOv+yQBJnmfO9zQGU1Qx7dbsJEujWrcKelpWCMjIRP5ElDh5KrCiI\nBCzc9VLwjWlWItxvggkcCkJ2XjUSHUo7zkpNcbIoby5YKv/cWF08Kcz4dFgXcT4C1TJUGH04GTyc\nJba/trXywxNcE7jpJoEQT9a1q4rWeeRTSjKg21nYWt9LU9Pis4DB+ETdzqzG6mAhx1Eu3DlH461w\n6zcWQIy5fXcSeAUrSU0bJqbP/7BhcbII4ZJBhwgZd+jvE3lwRpJbR1vvtr3wfUY9MOSK6HXzzewu\n7T5KH4qJ0nnCg69EK1I1te/El8XCdswc1UIv/euE0ZsC8QU2ij+BjlIJJb9cLeRV3Gh5nYDlPUZu\nXw1OHdsh9Qsnk7fKsHO5jGDxWRos5nQJmoudwdek2Tpr3oyaIl7ub3LkraX8Gvnisa1Ik5SyuPnv\nyJWc/PzbOjLMSERApn1doiscJsHep7aS3vkLNJf9DqfNGrsS/3mbF66pmG8qMeWYM6XGJnEWfDJu\n1zFkEE+yUsnVmN5w8iTbn08VKq0V9iRG5ItavzyHYC+Il3olgWAFjSd26MLlz3kg1JhB8ae/YbLH\n6nhaxlZBie+88vl3nkEeiu6EbV8ntKeAFVvJ+5p8V+qpIh+MhKg7YiAgzWPypI4dOkiz8c8gPW6B\nC1g02YhOyEcY7pqodnhJ7jKAvBOCoAZxkZ8t1/4Fe9hDJYZTmJrBCBrOr7lTT+SYyO5K93+9eIK/\nwbKL4r6dt4EYdrTin+dt1FldE8z435dQNloKXkd6/vUwa84K7AA/u9x+DWgJ37xLQS6zPuc+X7Fn\n1B7Jal2tLB8qL9fQxfcks9S0abI2JO32D9yblpD6mQQs4kV89X4/rHcD+Wb4BG3vJM2eSofHkBW9\nYU6puB4J9+Tt+vmReDSUnuN3etlTGdfkPW7TqWRkZlsbCvgXaok8nVY91fuxUBDywmm+0t7sE+ln\nDV2sod//FYP00nYSMCircfMeIHhJhj87p1h1ifMsVOyj4xpcayGRU1s0G/kY22YLHC0ehgAQW8CL\nVS3gsXeN9ghsKj8E+31iuhXsOnP1/CVrxmkpILCeLdiQGhkdeOLSWO+ZmAqMFzbTgWNSVnn7IvAq\ngfOcl2fBrfm8G74NhxQXqeqoR7t04QQ47xWHHGsk0QX/REc9wb4fbMgwKRQxGYQ08k42RY6ISsCL\nXWzF/aSdurtKx+85LUIF1xV1+xCNEA+8qt0ygo/GJF9ry6+MKMsqHjQ9XttpaIQY7PjIT1DcRgsa\nYYnhmiFrMV3tHfuw0uepKLY1vBx86257hetScTmc+Uk61b+DScvAVOXMfaPSFyUVCUUcrc+JoaDq\ne+Wbz3bh6OhISOdhOR8ybicA6/gfhJERhrhfZeBqqwONfbIgB7lFftKjIIs7jePP4iQE662fQxl3\nLtHPEoUwB0QdWhyitzYoqZjgaZTsfzFzcJCp6KlavcyDfZTUq/+mZ4IWzB49QzuxCeTVXpQMwAFA\nWb7VdzauUCdB6/gHOnwQfr7rXS2JuGq8IODgT8WS09xvtB/E3fIU7cJ6VPi+N+wp94KFQ3Lu+7Nt\n331g1vbJwMCvgJ1PK7d0qObjLJJ88IbLivjaZpdgecissEFvrqYIUbRwXfmF8E2jhuEmwWchDj+o\nIUug4zzjjNHuHMXP6G6MgjyNoFURp1HQnzBMDQOnC6rte+nbC0+Kjcxl8KUmWdhiVaq/Qdabq7le\nIu8aqCK36CBkPt5OYslshtzBraPiLOWhrXkSslVye1a6euWG2stYsv121Vk0idQRVc114RVIHzGU\nyAReYqXycu8h+GLwHQ1jjJMBWlf48r/0SLgElGCthJqwi2mWAD30VU4OxDlQubE3T0jY1mSdhp1H\nWb7we8EXaQpVk3eLNHNc99JB++HZN7s9JPlplTH7sxt6F1/CJt9DfMUsA89OSP+do0ft27FgHorr\nSjZe/pOUzEEmuA9hJSDeK6Qi/brJyr0Imo1kDMk9KMQTkukgJGDZYuxhUkZTs444Qph5lDDlx/tK\nAGW6cvSFLvFf/tCzf/KuTNNKypIhQ683I+FWtL9A2sXtM6LAVVyfHfEtSEMuA/mFvc33bzRuZQdp\nN0zHigUAcPiUONWeZC1/iV4WkZPD8zJRhAaUsN65+lV5IuxRhf7Yua3KyZw5Dctse6MWeIA8PK8l\np5daz4X4Kr6NID+FRb51b6G5UFOHqACbb9TVvrMVK6WjmYcy6tK4ckK9rZXxmgp2ilonSrEXKdaK\nE4zVeWp88xlHBW/bDVzZsV7tmSjj8PGvbbXCDnzzobRy8pHIJecrnjqJf6rmKxcFm4jBvaYN6mDa\n0YaMgMFiNrZyAF0F4VlssdJli2U/LZ3ShQqI9FkEO9p/H+21uhdWmEeB/EEf/2Gox/L/ihzXPe43\nj8m/MLkcsZruqpLVTuWck8B1dZ/5dI5ng+uZgsQDstt6qVE+za2EE7l/+PAAkxWxZrhr2lQs2z4O\nImGPilzXMGdUd5DyoAS32ACon7+nApUUou1Y4XQaAVTkYl+RCbf9OX93QcgBjUVlNfmYY0zDLWY+\nz4W4pPVN9YYIwPMNTKzEJp7G2Vuur4izl9Zf3S9h6yNPLdXwopJHl/rNbbGJY2pnK4h6BSSxEe0n\nSbXOG5vEr+DzogdIqeHScTA6ZrdZ9XobKBO0gCEmpzmCoj1xoTUZNbfmIbzEGic2olK19G3KMPkF\nVcRUcHk1xfK8mkr6SJSy0yIs8GqwvMuoan0cssKOtzXPMte2wtGEL0mQWG7ke6viKdNZ+uj3OgY2\nq3XHTkiCYMbKLJ2QlYTwkXkcjy4OqrcCLdQK2D2lEK6DMa0XBeU/GUMBtTThHLkz/sI5pHtj2Yv2\nSTdk1pg5pOJlLLrxznm7Y4MjCwQn/4YsHWf7a6IGaXBcjataruQorWy0fNUVUciufnRXGA3W1sTX\nsEh0A6bBTli+MJipbrCwhKcV22OQ6CcYNqBlNxR5Y7SLT+vjcRxjf+0Wr+0DhHEsZNSqzloum9YL\niSXL/FqGedX7sNnxMW6XLrwTTcIuA9yHMrQtqhq7LrqdjN9PyeWDWlUcKQqEFEq9yEVTu2iA5cOZ\nYVEh8MNesy5LYu7E+WyMiZo8eQwklt5RHTlDTmHV29Rdn2sqZH5v6BMDjf/zviCJ/xsGOGXBNRti\nctJ9sUNyrtz2gA8JNzNgy4x6XG3tD/4m/87u9C6kSssWxE+Reo0JmT13ewGFCJOidPhgtrAFh8oE\nxBaUGCGbuuhyLl+U1nZK2jYDPQGea2f2zXUG8I21PNdMhjxpy/4obxj0IakEGLfJfFXBO+N0gBiL\n0Njx5YzzyUB4zYQYGO7NAAHsoO5o5j/VWLr81guljgyu/us17aReNdj7PVYAd8R/2sg+Jspfet3P\n1qhTgCfoUMhjIB/MsS79HAprXOfPDrucrRn3HB9K0ggXVgNBpNVr5NxCqe/Qcj/SGexGj87vQupj\nlLPVFka5iIVXh3GOT42rzcBZr1QFDswFyIBK1QAlnnCKETBnsLAt74OG1UBu+oH1rBNmecVK1qJ0\nmMOlghAxZ3KWV8+s9jK88B9872HUx8RRFE7IG+ahnbfnK6mjDjGDMX/5FxJ+4W+yNbbCa/2dyR41\nXoaQv74d5YPgv2fLWnp8dmDXLfyKnMoXMp7kXtoScpmYA9CL8JSRAOBG0NsihK7DAMMY8Am/ApaA\niaR31/MPSSknDJ32LTgQ5aHRtWEd7GR+ndfc0prXTCJ4w6mFsy2xcBwJeD/wlh9ZcRmNZ53LMGNB\nzwOsFK58GJRDU0spV6p0HjRCi1YhETy29w7EuJ1MqybiXke9WZ8Nnwuzxk6ltvtviGZINAqlRmbS\nYoXRemf6VF9lk8xh6EKH+c751ax4n21i/CZFpLryCIPunf06zE2AYoAUtnOgO25Mwl+NN+hV7Av7\n+JMARGr+a5cb74ldJCEJoWApTPefYBvskFDzJ13a5rclSFB3cMpvtzmFgafCL9x3NnXrfXgwsCX/\nDpVuBLCrq/UluJgpfgVvAyY4m174hMLCyQt5ZVlGkXDICTg1gRJmbFo3Jwe/coU9CJbGUWkSzBkZ\nfbwr3jS9jIRYAOkwqKvHslZFcbbtYK+HvYtNXugF7Wr2ALDiReHOm+C637+YCF2qjicEWJGZdBHP\ndIFeJYbJE/k4drb75lJuGMLYsLqJKr5IFMfLUt2LVve0kLEAoH4PuFk1ZByZ1EgP8+ypuMFoPMPi\numiQRTvotVfY9/bipB5FP38jV1zA/ZZCChWxewqSE3rL0I0+JKbUZZwacjYN6xgsmDOdo/mfUO/C\nEPnCjCq/LYhRoVpDaAeb62WL/gPGlg5heP0S1j94W101SOAPKVB6kz0gmndqXWgJd2AuzvYPm8g/\n2438pV0FfQUeE4Sp1bUe7nPZr7AHqi6F6PltfUIW9o9k7VrP0gYvYqcPufmfgfQ69nh/HOXNd95R\nq+qKX39aDf/9ANuDV8txpHj8zq190YbGUQyoPL5WELuDF8f+gfyR1uhnl5N4IudV59WMAfv5RFOn\n9/Vk7IG2GGoCf3hb9gNF65LYHH3Ssi9FOlDzZ5U8feQIudK/AEQnDnsRDLFxWtnNM9TiJG/ZdPZm\nqWLz4etFj8Z8Jw/tJKLgwPepIX2UdjWR5J1U71mjvXAVgCHbuGK0JLdUNxEtWhg+g2DAC9clOFN6\nu4kfVbZWJePT9wiR1azFmVz0xvlWVxPlo0EPYQL1Dc/aRoV8uoeGoG4uZtynTMU31BK95hacUB7a\nW3yW9Rq2+S8N6ptc8popVuLLIAK69t4FnAnqwT7Fgv4TbqH/fWkuWMq+9QNjcYmc/ASolw90Trqh\nTwnhGKmSA7rIWct0tUmyPAC2vLoai3uq5tKIr9TykrF7DR6UUu/u7bZNEYFQFKgBlH+gU1Qn3Ouv\npAs/vqOCrKPwDHJgHgMx3/UIxv26YRaBVLY8nII6EuWLzJAlNYo2RZz6Lf6OA9tTjg9B6rw4gATg\nrenIE2YUXfmdI2KweWSuC4UmrLbuSgM1NR4MU/0xQCX/Uzwp0caLsA+PE8g4DOCsFgVE34P5jzD4\nZnJcEVFb2zd7SnPizlSrw4GN1A2N72UQjiSXTZg/8RlcyO14omqIERgdJM8/l7fCfE1++PSXbWhx\nD8I9pbGadGHDtL8WOfi0yXzFx+hZRfPVuWQQXhlbUX9/vklEJU7RM2xWTKbqq7XPZqIlAtOYBFBO\n/sCcTJl+ZE5SJo6jklVn4tYdDEQyM6rExBXBT8qebTFc7bjnU8TJhkhV+lDIIXz6AR1OycmN61+n\nzT+wdsN0TOSgaReHlgrOgt0bgq5oo2r9VsrFcRUhHt2bBGrZU7sRLOJBQCYRt/X8poeEFTSdnhG8\neCbi2G/o75YJjLzIlXWkJwSdPwzYT5Osn/VkrN6oUuA2CHDbS3n3MONJIwjvrjw0Mhm0DTvGarG0\nfoxXdM/feuSh6ZWm57j+aYakbtCcH6UZl12bLQeysLSB54968pwt/ZPSqIH2BqpLLeA7PIhF1BIY\n9THyMYV21tPr8MOSpfQwmPbgZ0MhnUt/UcWaLWeJvwJpEwxlSq0NZngXlwje7S3YU8eNc4vaj1JC\nvL651e8z2pK2mOYZZElPLjc00R7Inm/uB48mHb6lo5h+Op3xPEy2GLinFRkU2cv5q4lB7WCg6G5U\nL/b0s3ztby/hGukO6TkusRCgfF1+bYjQpCoUJCBO2oksT15bMZFACkdfhlAaTRwTFU9GXcrJNDEU\nCWahNHqDsfIsYwv+8eHxxqchzDnSu2mQRGSBYW5bOThpUDmvPGYBFu/pP+uzBeXRFtW7zmowJtx3\ngVoSxU+7LPC3y3wjeJS2/Id0tcEN7OhMz6UCNpRN2kYFZFkYfcD3BrPf3WtvlHymHIKDkY2hWnsx\nYWhngN9uq57gyaXE+DymSnqnJPDj0SZUu+pijxW9RZn6boSdKBwQP3+ZeVPZhyzjsrBy0EEBPFa7\nMvCz2UiMFGkabEf3wUOtKk+TrAyQYOeT4qnIDV+8acbVgsd58oQxuDkEBQZxoq02BEKoZ5TRkQm9\nwY8Nb+g87yzNO1WSTNxjdPzIk3QnHSK+TVy2jBR3NV6vStsUfiAf17jDAj66NCbvUu9qFya05Jcr\nmsF42W7LDRZs573bp+sqUj42z8uTh5slFSNXX7E6uFyN/5j9ekj4h5hud3pAHEfLC5212697DG2k\nSrhcomAwCsTbd83lGGZ3fbVM4rJGQBX3J8iYQWw+S0UiYrqCVCnggcFjUBUwZhtHWt0fEUt4U/py\nHi0o4E9P4j4Tpvnyv0XKg5jaP5Fh1Ir7fqsnuc0NAxr/m0xmih2m12OuEZRyRqCn1dd+36XxPJVu\nIfYx9GdV0na/XYMBQQAOYAMZtv+ber1of4B7wX5uL6/fI0nBXQo36SXYIUiTsY+yjFkhyWf0C9lE\nFpKm4Udx+dxFd3NSPQKGqdKuMsv1FI+5XobFksGC53A54hyTDIwrzbwcXvPLtsbqu5gwG+TsHYzg\n2yozfvKJnTGe2yqlOiYv+T7Z/tYp273bv8fBJWNPvCVF23Cq7bWQInSs0qMpSeSEsrV+lTHmZtah\nlrcLTu6QUm57BMD+o/N8R1Phn59HMb2SJv9KdGwqBBhqIr+5IO53E6OPKsYB5p6tsnsXNVURbD7d\nQc0d8Mle2GwTjCWSDQRzCZKTNJFggLVfCIlHVjQL+0/5WAE6sL1Eoy+HpnxMd9EY4ZIUAqO8axzF\nyhK0wk81Rh0XBysXQl/65CtZ7cRE6dOhNR0f1/TzXNHtWMzEdPhZ8YC0iuiB2i+TPuwnmS9EkC4o\nUkWxbHLU6P/LTQHfxKegFq577cRtGGP/sxoGQMB4Vbk+WUR8gbOeihGbGPFIR+YrrAwsO4UlB0Q+\nCQZ3LLZcExoLpLz+yLodOvZVSmLNdwAjGKSfwRZumX8lJFKNZYv3FqfMnkQYRxwHFx7cZ5Nc0tiR\nLmAaFXGV1/SDMAnc20xYOdOc1uYiv0SDdxWD1ju4aq9/WUur7IpFwUFeitxAq1yAWD7fiIWkVWVz\nJf+Y8RUB8AGxmjdcIRkQQRyI2rwOL+PxjVi1ZZabQx6XuDBCW5F8EhnX7GehneXlYboUvr/EXOGa\nEiBzwDc8U6Zh0ElXWHwtPbHMx9SWRJo41aaw6I70OnZEGUjYeQZrKluCJt65BUrwwPaVejpzuHs8\nxxZSMixm7bhkNH892H6l//sFxBzH5FZrH09JXG339Mxe9AUHd3XVLFWiJPyCv3aDJOPpSGQSXZ24\ngKlHmgk9zZu40ZIE4V4F+aynxVuKcGjV2xfQTPqYcirhlI2CTgDdp80gGSFb8eyxtt1LrcskdebU\nZOLSKnusTmZFbppa8BYUOkTngL7r4XU0QVItJTunzxwvLXM8x4zSjq4SkyoqpkJAPa57bLiX4yJk\nFVWWA/P83tb6hB843mi2qfFh1jD5/uUOvy/kGDuQ/1P46wGFEqfJ1cXaWd/1+AstbKuf8bUDE0Uo\nNP7LVvd3Hupd3HoxAYn7hoYeLFOU8vdYlQB83SxbqzBcil5S2Xob6hti9QPV7vL5ZM8nk/7wAHmq\nJb7U8lXdQsfMeUpZ400OjhJoMwnykoK0u/NhZ3sma5hBtPHoEJBEy0AQx9s3WhPU6fFRkm/+/kYh\ngg+wLniKMJwrBT0ooUjh2536ULP++sMLXprok/tTTW8FwXRvewXQwhhhUW7gzlkWvPvRxfUAuKf0\natd2gZwn5eI4KQkL9ZN8slxJOOB6oZ/cdc5bapV8fMFCeCbjU75Jxaua5J01pLHGUa//NSKVKLU0\noMprnXQlfRmQHQn2Ee1e8Rg3UIffZPCbSHzBJslI/enfel1Zyp5yB/bsiRBrk7nsnmiQ8Q7a/puk\nk/khvxQMe46TeN7kQHeaJguFLPKvMtgPm05NxZ1EsAAJKs6OLz4R9pIte6B4xQwgH9hWOMZeE02j\nzMu+qbUzoSXabVzo3yXtKArpEKLpas6mdxJWyEb7nzLUJ4qL2Uc6PpgmGHupq+26zvwd8PY4+f/k\nuzG2A5gGG3TGzDjd9aQoz/LNUtW7btZ/vDA5651lmyZaWXeQMkC9f29zX6jg+D1oRhfOXOgynz+y\naC3Hq8Xskt5ShhQPxQR8UQe3b5RH5B5653/ohxB2DGpOaS2pkMWtWM8zYOXFlnZ7S7VvGfr4aWJo\nUfm5+cGEV3a7PdyYsgSQJ/s/1Nu3IOuA5rj5TaL63qgKdeIWfDpBldGX8QQcAistd3sjbmmWMdYA\nYnlRUdmbWpqJXwzP4KGhqkRADlJMEmrr1XF1eqT44WCfSYcGVQtSuSRvvnqrZlFbuxe0uQWCy/P/\npoTmGpfAkzSG/dXNdIFSGl5AQl5ajUJKLyTGt0qhP6+N0qXSQUjjzHvcQHoHPAFG7LTogn9OEkc5\njOPqJ2AusmMjkUeTyRAWkTW2DBwANs+HSP8UJFMKES/6fw2rSOXYkXZusIcMZjUHh+6F3LE5HLM1\nl62SFTy2OsKy+yHagX0mgjI3XX1RP3Hm77qx6cC231//pGAGsqOhozPb7mdKtUbA53cxzHYhVynw\nMMOy9C3dO1l7z4Bhwa16Q1o88EzvVmreiTyQDkBXAKt813Q3i2adP2lIpnwglqx/K1H3PgS8VaTN\n6NuZN4mm/fn6UuRY4oco19h643T5iBCcvN5ckt1iU0SDQ234x4eHrAfUod9f1slDoSacTwzmQ81t\n5JREOKe80j2+kwjJ2vhJGsPqa2+hKDhfqneafHJDOFTbPelVUI7gTj4favlQSnsU15BcXydcyQhh\npyOAzWqv7YxOWQh3ZPrLETJ7pZaPoVPYBROkGmBIRj7wrIeseve/2Dcqr2goVuez6B7sFyQBsS3K\nYzrkPQE1HgKg+MZ0VkUVB9EaQv47Cug5Sv3537v4PdSecI2VhxZw2iT+XyB5I69w9Ahknfq+Hav6\nTFVCWvH1116rilrLmor/9dSwsYvtTbFhkUEBZqoPul5o5FoYBSvZSd5ksaPJhtsp2UgzdJm59V2f\nz+xksfvZ6GYVQIq5jABWsW4qi24dtPuV8WKbsHP6HYEMoc9u8JtcMGPdB+KT43m17bBZzZnhRhmC\nazhdWfbELsJmhQubnfP49+NyRVRtG9/e8nqja8SsHHWrA2ki4X+H1fkkloT2IQXNX+e15ynir41X\nN+BOhFIPaO+ot4bS2VlY08PuhSlpMdcJlFqWfQ4d5vaa6BM1RQUXYD6uF5Vpd9nZ8kUetVj9d6li\nvL47VR/tNe9A3xxdqImy+sTHg/qu7sVhx2hqkJ50ZmkS6c+hjwwE+yLGpzqCWFxdIKCkVZC9nPzJ\nbPfZ7CFFEumy3mkvWUBZsHg+Rb0ZmNEIDnveKDxcyhJQUZyvKNytA5U4qtBJqm7iWLif6DVzFlg4\nBFxNosKOLpq83rShWot0LPZRhPTPfGE0hL9x+PrA3vdmavbc4GY0wKJN4iaXhtkpyCEmLGr0795H\njyxkPzTgnP5DRZLK9+7MEE2XgkQK7kvnLaR+QEuB2+qvS52qC6po6ECWnDMIK3Zep4ueH0bGK3+3\nkuwFIZflESCbiMQK1M2FCX0HsDdTrQAKi+Ff914Vyjnaux9k70qC6+m0jZ/95omXXt8kCeujCAXO\nG9xVVuKCSyCHrxsjoKfbzrV6BsoPCkKCg6KC7Kt3Jv6s9yTvYQdIN4YoMYhUA81t1lYRJJNgmt8q\nf8A/4LJPJwoKhCXCj7JU0LIJ32PNpXJgJF4CQ0HtWh5pa3+443fu10tH+Egc4P4Lbviq4f8715lH\nGKLGOEuLx4u6DgdPvVWKQobjNAadqd/4xYfGKGIReihL6xSeJVDjrrD6rEsnBJY+v7aIgBzZFRM7\nsIflUU8JdpdV8mL9tBn9Se27Es9v3c7CF4DtrQCZsOsTkG7GymeFHcgsuTLahkxhe9GOKsjLFFpq\nrq/wzCdIqzM0aCELtSh2c2Ji60db63XvzCjx/SRMlh22brkG0iYUMlf+faTtlRdv6DJ80GJxuutK\nWPPQBHOse/Ro9tAQvBTkBhGbMdeK8mSRhIXScQxxffPUJ0Fz5TPl5sJwss8O3m0kdCmjd3K4Swb2\nhiR1wDfP4dEBK8Xk3rDE2NkBp0ocAGI73l9ZUOVqAEm/+bREE2onksf4X4yhyjFt9Lj4pO5/KxVe\nMzvOA8fOYJBexEpU3e/eqU/jmMncW6ctsToGRiX/eX+amJ/gPwAroSDn9o/mAOxpmuKbHA695Rj0\ndCa2vUHL3uaKmU417hbZ3IzCEgTRYwmb8ZNkY3HwNXhBCpD94QhL+u0WepQRWXGaVmyV5LBo4WNz\nF6RGExDCdT64EPEYGEzOxkUigUOpD3Ckf4s67RhzTUmqnzEccCvprc0L0b3WLQorZTdGa8bRnu3R\nQMsTWvrlfvl3P98GDrbyCHT4h5XrYDEvTtlLBqnBNtbkQhP3EQRjdP0otqbvOKcZgeztuZI7gmHz\ni4VJhbFVQu3as0y2kkwHtHZV9dpHO9cXRhu8w7D7e+FBJ9FzJmVDPuR+67D8EME2Mh0o5bgt5jiL\nfqIG+4BfyuVJWouGAafa0YlNG6Ud7QPUVS5g8RFaVPO3QsOKsaE/G9Y+A0XFShgLyG6R3mEDeoFH\nOZnw+AIjyDyp7UpSX/jWJ0FnynXDRx2YRClBGJZNGYJsvk74tCzJ1mXsBPLUT/OjD8sq/giPgd/K\n22aHpXYk17WD2SPSA6L+ZjBowwEgGlSN4bXfMlpJbO4Bb9moAkTog1Gl4hq+zbkdubchX+F2wpD1\nLSK/mdG5Cp4wmEHiOQpcPs17G0bp2To8mt8++rNeFLGjp3BXRF/o3hblPZsKvSaPF2RSuQAnVDae\nJPWYZJHJG7H/MUnn/Zq8Vk5gydNr39oOgZB+iYvOsE4ZjevXiP+g4sE+81nwEhX9YDyPmDy8SKlH\njm6ZyhRUhzDCoNsyOP0tIBNYMWFZJemXjSof37wdrVO+IW3v2MPWmbnB7e0SzKfVACgeOm/tWPNR\n9F96QDrbS6FvJde17J8jFVRCYWyz8QXAprC1xvuNlqGfieLX0WtBPRlnOLwOvWvq75PU97Uc0r5r\nf4OwwG71wQl92Zn2AyLX/V9750ht48/0VtYBT+FLXf6OqRV22S7KGod5BXUw+qTDcP4gRlzGH6AO\nQYldmRYQ6TSf7k+LI25lKkYFhiiTcC/kQalEWi/wjQIjwagMW2RcE72HBu9AUT8EzHQTzbJRqdYq\nlUjvy5fFQY5ls1lxJotT67Xq8ECht7/LNagA5VCOHv6J8skugChqOe+8FZionQnaxhXDt08oVmKo\nGrJdF5iZhjY8235aOpKgazD2QAhKl7YVB8vTgqMmT3rVaKRA0HCkJzWnslbHMVaxmUsAoxlL+QgU\nHpqjSkIJQya+ABv3jA7IlNFOw16JBj6+Qrie9+6uu+AyskDHmUq+vyDIGFwVwmvEpIRDk4kV6j8L\nydpPHiHIgZAPm7HRthoaPKCZ7YNUcWnzoub2OZrASACL6mQmB9HH+B0CqelbCbowiYuxHD54xmY3\nnwoYU9QclZo30AacKyGBkfK7yV5Lvv+GftmlxpSp2leGaGMsok2gd3U0e+ra/hcNKFSfzLHkvcEP\nzMeQshhsZGZN4MsJL83UqNy26NeAOEDde+sCLonrip22YH2ipOIIGZ77tHCX6Q7zCj2b+Pj7dT6i\nGiB/ORqCzoclv8xWDFyiVEjnPxLzWKwmarMHRYJLQN8o+IwqSQCEXJdqkjXYctrA3Q/0NnAYx2Dw\nvulAlivniNQo9Q1iNm7ApZwnKXA4zbGaKJHrC+HRu6DyZmeMLquhAgYPToyzWwTxHcLJbvGFiG7U\nFaLPIjMvXxXoMAD036/wc25ECUY9XGr0CeVqtEHGzIriCNAnnpFc1Ri9Kr3WzNMIwTuzPaH25g/U\ntEE3JzEYFPKlynhCDQtxcTkNA0BDYjX9BIYwNR3U7jO37hzNzxR2RGk8vY2ppmbBsaklW+ClJ7cN\nR9Lb4vQcxZ/LatZTEQhBKsT+2VRw6Ncy6agn6/iXQM5RRLj/Swg89aTg4RATjAtjMcLhe2Cun4Z4\nBLH5gpSHB6BrRh0KB//2m6EYpMNuf0+wc2+9/E20xgbBfB6dX90oEHB303NBm4FzaledsslbL0rf\n86IuSf/x5EoofXMt9nWVGtM3DogwUf5W+5Wg3GXaEpBzg0nedFnsCHIHjdMQwAjA2JgiE/4BDgFK\nyfTBU82wTYAx3YvqsT+HMnn8J/4Zt7vip9ZpEgTSHK7ahktvLDJ/anjJ4ye4CSCp59FQz3m7wElF\nm3hVJDVyXcoA586/fMijkvrkg8vyKtyUM/NntN4NeAATqIMzl9rGr24TjgovNiW/D+6x9CDCEPMP\nj5aEKcAX+Enhu9qTmaeyj9OXUHmYP7bSXSxXNshn8F2QKzJo2aspcwhT5XvCDfeMqUNtAGC1GsWZ\ny/pp0Kqn4JArPg/3DFL8CeQBE7aXbLu1/5CZCuAgaW3CKJseutBqNuwMxqJVsjE1qt7EL3K1ihjK\nZNrpQAZ1kHElMsCpTZlTKoQUxDr4+0ZWXgnNKrB9DcswI5B6TpEJ/zXwCJUyXPuKmMQfhsloPNeX\nlYwy02U6E3dq76O2vR0rFIosaa5pkLxmstmy0glDDK1rvmp8CLzh6FS9yKf1NZHaxac03DofE6X5\nkRS4c6OrxllgDMisQixbVOTtaOTNfJ1KCjzHMytUyf0bZmEwWWUNFJORTs+9o6jnZWL1RfsJYhBd\nSf8lFRr2E8PoQqHT6s55oNR4B2nvqg8X/E83IHv5zREIoNFA0KzdV61cmcpL8YDn9zGBkfJFR7PI\nhV4tCs1LzTGS2Y8ZD79CA6UsDB819iAk4UvggA25GNd9nLXTQpFCKmQ0uHIOf1/G6s3xsonjWJOZ\nWjMXa1mJwSDfZWXBsXy0YUiSxsLYtDn217WcebHWSjJk1iz8dLNPwXocb7BqRnArB0+GeAtRoDVx\nCiQbyPdFXvu628GaQb0YwVzb1/I+0f5+BXiBALzy47ZPqCbkAMShOw/zqKDc3oHrEElfr9/xcs+y\naIN2Fut6nAFbgjNI3mT68fCwhgf8OILn2gNyJngtH/kiMG1w+r+rOs3D5/34xPjjsLuyxDYld6ax\n7ttlh2i7yG0RuEDf+U5dOAbmMqveoc/3EjIdONTlzGukTkV1zi5QMXKmILjebgUybzFRMxVJx7/C\nBfOoKBYqFH2Pap5BDaoTmF19w1jZCfs76MILoMTbp52XASM2v1R/2z48/R/OPzumvaNZpr3YpvtB\nP7KzoLvKSHg1GDjdAMPMmICS1L9s+gB4IYf8FBqYQvx5ziK/N6laxCaoBo1J8C7du+Yuay7+qSuN\nDZfCE7UukHMpjBix572Wsnmo4weKfM4RvdIh448L83N+jWvFmAPr9SMiejWINhoWfnH3CacTC+LQ\nMxw5SnghNYBHx8sLg7aOCpECRaq6Ve2saYje87AQlpptGyWInV0rbN3V+2U0Jxpxal5cdqmVoEaV\nek3BOAjADpwu2qFAWE1HzPRuazjG5m0IoXQ1izYy0NLLnnMJyZHsF3yV/08aCmVeW70vj/4bExdv\n+2qAKsUWLTxu8wCZ1kGooELUiPuNb5LQATxw1bqTGN2wiPQK1IKooEe2Zz2iZhYQpotPHw2pTDmI\nWjppfmM+S3ZkVUsfbZj7vveD5THasDqfjcFXN2SZOAjwfiYRlqN2d9ah79a91xU16PByOHOM49Eq\nItrSaqsNpaEqteNBMIj/2AdAMiRq/sHC79AAdtKSGMJHSvdoD12OdpFUFFP33Ykh4gDbjqrGmhTw\n54qd91IMclxDTlKEmyXhXr7+vUOWV2yRIb9kGBLH80wycKGujk/zokbmjRd/vgaxUUHA8om89kTW\nBuJTGtVuOVtzxlFeQVCWKj3atcZJSjPGdvZl/rzmbB9Y0lo/eXN6OHYVQPGBicQ/BlxmobUIZTkV\njyO98ajmWtAPC8ko0uT0GLqfN9BDeDWrnqrr4QUzP7KFG3Z6uXr4NAbskTMUxBMQLj/9cEmhrZKv\n8oq9zwLUh0FW1FlPCDP7EqmDsbfkkkZT4rK4l4Ggj2wGhJX8Nl9d2Bb8+LD/c6CoWdL3dxO15nSN\nBPIVQqFyadXO0FJrDKljsxNh1Fj3+cmOvi2/wuJb9Inm5tC4dGvkqCAhqp6KhwJLFW41+GDK7gj7\niiQ1iaEuTxbvgxtrzRiTnV2k7WNfXq1PQyosaBxgkwTBtl6vUGUPve0B9PDI71OmgO0zpjgff3pt\nv7Zlz6KX/hvcJMWwtt5OtxAGBNPbqJ2OXyKKS8YCuUJxbZDII/m1A6hUNW2sbe8qNJSUiA9arYao\nqzPHf9vzuPkgbLyq/LajKqwpQIzrBoQ+Nta0wRuRByq2jK4ad+OpTL0xyxXCyCB09ZrvvkAr99NT\ngV8fYiDvyZB4LfuXJKxYz8qmYXGtbwXNI8mPY+o1z6fbOT86d9x+88hABHXRtbAgdfuS6EsazEuc\nJ/y/K190LclghWUxNW7IkCN3m6Xud6mfpiv1VG0Y0+ICGzbEgsbSNPMoV1aSVhETnZD6YeWZ2Nej\nyrimIkpCMMHd1HqfRMBK3vL+VWxkkP7/ovwdBDP3eGaB0g/EO/Vb0GjU9o6j7FIq61HoXws/p7fb\n0GoSamfdYwwtwwCCbYUX3iWdYhz7BRxZMvEHHBSO1yAJNU9eXUfveEpgiS30iyuRecqONnTh1GLB\nNbwn+zGSufUNn+0K2FNHny85IqwtPY+mUtUJyBmY00TMhkO7I9iGZafFmpSWaUw28YuCMR4Co1Xu\n69q8Yo8efCDvrvoMT8pLR0guiyiszvCNZfPq9UdBxa7bINYo5F0YejTJ719T2NsG5B0efQaBAg+Q\nCsGDN1bXfLLXumilM4vd9KEAqazs92QYNWYP9TyN1u5CPxHOuBXbEPQQMCJtBiV8iZnQPndCnnH4\nz6y74HUiMgk/utb9VBcc0fuglvpZhqe85fianGNz5+1arayP5+4qABdZbbys89NkAG/T3fap9GKv\n/2DAJ71wmdMXDHZihHBxPsuobLXXXGY3hBP6tJcqEySeL+a0P4PcHM9NOJJAtN3ndkQAfmXuZ6xS\noOmcMT/zjPD690EWOMH2fLXB8E4GMYS/E796PRAfBIGqABGlMIr1PCZTYlNcGos1x60ev7BREjS7\nMmSoPL1yGRJBRdU6dhPErRsrr60iHk0NWtwo9o6v0++7lyg8QCd99SXGsgwGrlFpcGgI/INh2wVN\nbwUWbVEr5tDj9GxUWtlHZzDqy52nZeMMNnVxnaqRl3FZY6UsdR+nYyI+Iaw0KAEUBUmUJy2x9L6X\ncraRJ+gfG/n9PN1Rb3/djd/aHhs9a21J74gnypCZySM8tZAup848EhtcLmwRqbeQMHT1g6YCd6WW\nYhkg+0+Lb08jDmY4m9imhEIpIa7eY5Q/hLUFfqyOSy1xA1n8rud6leqkusYGOuzkTg5cDl0W8i8f\n2yTsa+hU5Hti7wA3N2v7HlkdGHNRp8t0zVBES/S9n1OeAGcVNzB/r3OPPhsOqPnVUW1a2bUxVZvC\n6YoIFlBlmmV2ZKVqjPWP1GuUaqdkN/k28WScustVjlKFbNA0lJukTa1RLjP7umPsKHXDO4LqJnJo\nD3cSlxyesoyuP6zSVaqT8gNnoe7iZreCN577Yw9mXcUENdsg1h3UlePvBr/qqmK7KS5VW/XzO50z\nF8i0fq8Omt1EVaDHgibPSDg/DtdgLNC7uN+mAkm1gU8BOQkEhMMnFjHlHfPIasjKj+4ARai5F4WM\n02EZ8KSyYoBnxwk7qM/blHeiBqkFCs1YhOl5q4kyyyBDcdPq9FA5WxE4mpd1DFI0qIVmwJl0zTqg\nUvv+AwEklC/jZ6rmFVR/rpt1G7JDfocDE2Y62owpnjWhZXEuENR8CkPkSVQ7dLiMa+UPgDmwge3R\nFnXkOvPTqodG+xu0QUvCDr7ZgPeHxAXNNA9KxBez/ZsD67ayW5OZ8A7KQBAuRFRnx9F8SATYRgO2\ngvOdWLGA9PEGf+P10yBN3yPUtPgYXBWZznTWYhJMXY+ezMetgde98QPHbLVjqCc9nV/OO+SfPjt7\nLmdDUyrktb7m0rB3XuYM+sUsNXoeC6XRjTikLbxdwdQSjiKcuawUODCI08ZLqJ8rQGeiSBptZqf0\nqCR30x85iHd7DnFRk0xc2QNxf18mJ5aT7h7DYyno/RQv8oZmGFi7IeJEQj66+UQE42XwXoyB56KG\npMXAGc2pUKrK6x8luqJJK5OSItQdc32jPQOqaGEY2L5bTDfanAeUJcAW8OchpdgXJFqRzVpsWqMV\nBmokB4D+IObxcLpgFMmj/h6A5hWhNn12zV7FmK+XU1twKjtgNbhcGoAkmrGxMbPY3tv9sFRvOCbq\n5PV4RgaS6H7UBiwvs5NW0zDJtO4y/BUxBVHAU6C2U+RNyZiZe1EqKEC8hLU45+R1YdLWh4iRInZd\nucGQEu0mXfCG8Fpn9NMdxYEkFTeT3wnqbIu2RANfZ5qmXNDVb6BCvP51QWtkoZy/C9k3gEzHUXf8\n/xDfJRSN8nAowtD9OiNWRo6L9Ukwz4+qmiCztdamHDO9mRlO7q9fUqg2Oq/wKAxFaTlpNWKQlPGA\n63AQnsuTAuvRLMY165MyXTvQqjZH/Wdc65OCYZxet1nONnCUZjAIpV6DRqybpIg8DuOFlKROKVTz\nmD5H4/5xlcOxNn2GptBUW53VEozrkkHFUOjanLD7fWEKn5KFXgl3h6E8NMFaB7baD8aSVtmIaUBs\ntaVP+HFts2cRXiNjCjtLsukucMaXAo41t/qw1pBzK4t3FVRPkBDp7IvLm9/wg0szWyloJ476sPYr\nJDh6gwfs9ZdicfLnmMy+4A5knvUbgT9oHykR/byVjm+GEEl0vpsL8munaMW10rFVzekrOrvHaW/P\nDV6vcHMLGREjtUYZTsITm7PfYtY+obUB4x6UtJXEZNP6EJe0Sqbg3Hc3mra4tLyC5GnBWmrLILn8\nkq/mnNZ65FvChYdGDyO9DjNiQ0vgaTDPMtBg8+PxX4ukcs4LeWA840c/Pfr3OYqgTSn3EIC9u2Pw\nX+cXKTi/eaf5h5NADHayC+Bq3PG/0upaJoEcTAn4GKCg+Oja1I+tLJZC+i5/Rf6bEyZcQTVmTR1f\nQX4HpsjRSBGjlILv4rGXy9dPAf6BkdVpxMG9OcXhXwxduJAgWISBlMwpkODBLwIVITAmI07BoOKv\nW//RPTjgcAaRKD5YkfBWbNgpH+sDEHYTnGL0xqVAC5sEMWZIfRmdnLSTwnJQ8uskAq5cd13bY5yB\nbczHTFvnBwiLtTKO0rsES9wTLtwYUlSSxBoWDxiLrwIMYoTC300g6mvC/bpFOvdweiMfYKLUqR7p\nTJawfTSCZ7QjPtX0HSlIAeHty+ZhaevmN9RXQCLriQyfAqN0yTjO5u83FS+xR5NHH2Y6vMUCA1mr\nonDsviL/gq9vK1JH4WiSAO4GTFySa+K3uHtlarfShmu4gBrimKQ5FJYiegjMV8Xrzg1/cJ12UcbJ\ntUDTPKqPpwWdfv5Y/Y5QY4gYVyQHkNiHlplXtbeHsumy0p9Zqf6k7cSOzNfwP34Kmel5IbZHVdc4\nuzadaOP6ncTr8fOHDtjxRo0g6/lBExS8Auojt+wDIwR4aLOaihaZ5dCviD8q1KW7XsJkhklOHc/A\nKP2Btb0IaeIfl0912dqAhgaqnyYmFHlLH7Qy2g0shZRaHyJGO4G5YkKlBS042JkulQsiEKPfdxBB\n1Iv8Ev3TGdARkbyrsnkNB30Gh8k19n7hvEDoSYyorAPmQ11RWhqZsCeNgwRKgmIClph6vaA/bZFp\nzRDf0Mdy6Phb78yqWyMr6LcN9YiSPf8PcnA8duYuUCS+K5S6yCDXUsLkjtoDR240HfUHpIcvAioY\nT5knn6MkPKZyg9gR5gNposEh+LnIXyivicZJxbfWA3Lu2/iwi8fBqH44xKHfgXqtMLBPaBd8vZeM\niYamRBBgsmAs0Fpm60GadQL156Fj2NGAt4CNRALXmygWOPLe6GRJf00uN/vTZYm2apkgF1MkV7BY\njxyuCF+xtzEV32WC33KcsDU87N/fwxNo38MF35FFUTaTOUshK7ozQgbb3PTvtwM45fzpAsrpBLva\nwg0LeXztYuRr3GPxHQndX2UfW948t0i7nhWXxdhBsqfXYexy0x9vBGEWlLTNaOCFFGb2/aJ2Acoa\nsGLFqTTdRW+hIt7wkrexXhUf+uk/uvkrmTA5lco+sfLQvVzrLSnWnL67jMdZjRMm44PJiFVd/hjQ\nuxaGARZQUrWFPisCSeWHcVRFX5FqlPcT06CwCWXdV/yEelATKTIzmlus7Z4MswQSJCJ8jhlH3ChO\npDykno/gnkoho++JIqT1yosg5Fap5PZpBS2SIEgU/wxID765SEHLcFYy/k2E/wRKWTmzqa2JPpRm\nfk9By5UIlT+GZ+nXJ4+Br/x42lN48n13w318ndWttfJefHOiLaTIlMIbjcr5g1AixZj0Tvs2ch5O\nzvX5hNJmLvkcY+Z1xvp1lyngvhcjYIqKC5gZ3RcpaZCgXuEi4INnNlk915c/cUl31vbmdBpQJGkp\nl5pUggTTRMuJcmUqg055zvYw+9L0dBgOXePFDlrkxWSQ+BPMwf+Cg8fLzDMtCjiOu4jmq7W7wIqf\nK6T+yD9U0rgBCNGZf/E/BKudeIkqGtVd659EGALOVvalR0lc65vUzDJfmMAhjniNO+MfQ4wpiqcw\nDDGCxdosYHt/txyraQgstfgSfmDSTht0mvaPv1WD/5scfOReHK6ZuEHyMP8otj2axdk42065kqDc\n62Xz2IToYAFM41jc++Dtef2DA9MoiFmngkXLEG5PxqZGqL6WaZ+d6lH7AjWIKVgk3WNW0RCyvVTO\ns5O8+uDHbYGOjlaPibjAB7nKqNlvZb8bOQ7MQC3ZWjAXjryxO8fggyiM9tPNgd+FIEjQ+adhS9Kp\nDBEtK/qTow2cvZOCsJi1/qTLfcfWBseLWHnc3CP5OmYrwkmw/U/surJRcfQPg8VV6TvdbJaKFm+y\nmnkUqQbIWzMe9cJgfJ3wsla9eN9R6o0WMD6q91s7Webpkw2aUZLqKf3JF4oTXGOZcKTHmJ86HYDh\ny1n+W3opZNw69kFB3Xz6GX8KQtlqcn8MCKZjSCCiINJ50mUjLjHxHPId4maP4UNFymjKOKLcuB4C\nrfbIsRa4FOpFF+MBO2p1hyzQHSuMXrbYnSB0+h+pDhkFvB/fa1liM1OpFCIeiqTe0uFzZZpAa/+r\n44q8gkbrx35dcgGDcPR18LgQnsdLguqxZOid1A83x51k+X1QNlsn3V/9BEb/eSfJP8YxtxRUiTDd\nvKWCh9NPz79Pdbj9l7GqqTWA/kgkwYP0h/DAXwlvZUh61PTNpLGGBol5Q2E2LT3mHLLkyMQi45pR\n4X+UFdoobl6U7dnaPJsb7WGN/PsqD9h8GUx+KDfEWSMOJivDIhJB3ojkypT4EFpQOXgAzAWIB7uO\nyjqng0Z916FWbk+Jw74rNljRKHV5XwRqlKxaCfBUnwqz/cT/eF3+qE0MzOfOhibH91YFy5S7wFtJ\nPI8kpS68kQJAQ9NOEY8AzHVVE5Xo2F5wyU6LADxOs+Dz5uM4VZvqYKYJ07V7YJR286HBg54tInGz\nIaJVasfOIurcBo5z/umkMseHLbRLrn/2RXNM1DigFoC08fHMRLqIyv9zG1OIMPVX52+IoQA9tsfz\n77YWCFlSiWcuKaDDxbWzBYRWWVbd1XE0PRgjereqx6nvJhFewdCBOihHbFjMb9d1KFdOFJ9uyILc\nn5oCP1ALWoNj25Omr+oqFEMlHdiBCtqLRKpw5ZML/UlW3OiVUr2kMGRYpE6GcGfKdIL6cmi6Tsfw\nUPOXXYd4dTZbaUx67IlbUowigmt2SGjVLWguntaOPfOTz0zgamGksaihlxlgwRVdJTVpZfnTqztB\nGXOiuobhhAap5y1Q5zm+n03Lf1ik9dTNqMZ29H+PEp+Z+bk8b6lYDTJ4iJju/DeK0NZMpK1Xm5B+\n8VFSC8RcIPngnDx7zZycbbz2MWehrDjuZ8NhgopwD9BBOs3ljQhKgJXiFahlnyLv72/p/B+Cfb8u\nEBE0aQPsf5Gu19rdmhVqk0/ym2/+NMJFaKqQvydGWpzkoj+i02tZcK8cbzGLOfpAV6opIp9rPB7I\nLKPlVbsII/6t9U0UcqkDnm1he6swcMYX/Le1ahtMD6/c9Tth9H4rBGbT0sO8IvmLB6lLNyJksMEC\nI6ThYLjFeHyQRGn6Sgn7n5siWtzZoCv6HdCRNxxfmunuZc6bARlzPiTm+OPjPe5f1+w/nvc02Npn\nVXR0xmAnBDQ1XP5nBwgWYCygIhl25YuMCGJKCP2IiYkm5DjaV3SkxdlbqIEEava91wICzOmrfJhm\nqQdyLhaOO+urndGfbm/1iuACZrwXTDCi3AAKUPAGrRep2EWPBbMn0LvZNeQb4pMaHbjfAGSJJlK2\nw1ydrTWDxBMeczM1jw4YzkokoCtD8YKde6RTi+zoC/sqVovgJxzfMC6fAJbVY7SoqE0nBbKn9SAN\nqmJ+L7nMs31CsGDnFa6OhZW7yTQuTqNxzOpNC+JKZr4yNoZYW0mLAXIHBy+hr3mrzrV67aO+0UTh\nexc/IhOdKpRxwldm0vT63xEzRFI6JyFSgWCfcESnR8bLHcor1I1b4EUXEdqhufiUbBbD4T13ssXV\nbagqognOqnfzG1vN9A7yoRKMIuFlQzfH6MbAZn8OszBXUpeDGDO6S+F5DgoYGG7NbyzmqYDC09rc\ncWgA391W/F7iaYkU0kcZmzPR364tzikbEX1ckC8GgljehLFingmSF88ycCwaevBgqHy+MgPidja4\n8JbIytoS4TALh6Zw78hPd74NmF2p71gNDDimtZdEP11jiBOsV1uo5nzDYlke6cTZ89NVQv5V3nml\nkawxyUOOYlQ8nkuoGe4zKGuf/kWBvfPw0OzX0vylomCyo0Bsa7ILy9GSApnjBmxBlt6VtY9JR/Jw\nHga+m9OVPjUeGz6Jz40bZrPeTaKx7PYqhAehOR9ypJu1Aq1Ni3FJgPrSicUl3Zvv0Lkyz2wuunha\nSrg1F+/pHneuRKvMUDcFOp4NHJbsp3R4el+tTEzkaFOJMQS3acH3UFtedK4zJnIZzj0dpJicNYLG\nSfUAZPYbeCvoaNwAHWnl+yf9ho/RocWpZZaWm5Yl1nLJJFt+/w94S3mwixNvSj9+i7kmr+n0icQ8\n5Z5ra0/hLWvdWsMeHamDePAp0hpdjv6HdeZTAvqQrp2LFLG+00fZc2m8DEa45XS7PJlT/rqzl0Xs\nyBbJGYDnJ26fUSE97I5MmEsn2s8r5tAoT8R3YLqAUyrsyO9CHU6l1BgL48fgKqjV90+kfoaFdvJ2\nOMRJa6pPXozx4qnTlU1uyV4WsGLwfPixmo6Hn/TCRqlSo78UZevcFpsGiumqj16vhpqJCLp9/J00\nTbRnEXTsVShob7ApnYX1EyJW7rF0asFSBVHRk3GSJgv8REuq+Ac3b3bWKqzoZ94b309R9MmhPEhI\nLqc5QD8Um78fzQtVrqruvct5iPV2Wo3wrJT1JEiPPYibHf2NrCRpbi7+6bRs/I34oOJ0pW7D13sH\nLUoYxrif1b1Mh6s2x7IU45Uf30X26dXv5Ad9ml1DTITzJz+cFq87tc19ffmfQOWS5ndGxTGkOqBq\nH4egg5bwxW3tzjPGg01ZtVSLSuXeWhlSdUUPML9w/7WqVE8GG2URSISbBZxlf/5RB6NUaRhwVPUk\n0SWnsAGkQGcuPLY+m/E0Z1/ToOUMAIcXsjfzOvdccTumiIULzJk3ZsIXD86ZvpjaPrzXBPjBT7zU\n0yklYH2hcBWjPqGYVDwIDINkIgTJetFJDpu9saOi4blxHS/W1NXi+KbFeWLfDQadf93dK3uX6wfa\nK+Uy3GZat/defHDHbJkd7dfU8jgqm54r5bj3IQTfD9t8DuhBn4U7HVefeYOWEwSq6uG+Dw37YCF4\n6RFYQduyK2HQ6dUrOFGQ5jKiqy0eg91R2IDzG3dGZEgIi4Y5g7aA4Bq1FaPRwr4AMUNSLlP+2aaY\nORIjTenB2mZNrcMs5SgXZXuc7f41O1BfGfzTcGAPWyDC2sB0liZWEvkba/qNKLH484jZ1yod2Wx6\nqpw7+cJ5l7cBUXWbWZ+ZjKAwNP6HFRQmCXzboHiyw0W4+JcKZe7kL46MSm/kKS2QO6/IbZNET/ya\nnq8WhyLXqUvfleAw4S56KR4Jy9KcM8lS1GHdOdfUGAMnjlsYDQ7FdNqI8XzN6cdBslAUgqrWRpLK\nuMIFZ0zI0yEDklnW6454BKBv67IEjympZ4oKeqJOWtGd6qVLxVQLFEJwxXtRKjALkSr+q9ZK5mPw\nC/BEB2wU70/oUsp9FBXRqF5PgxtTE1ho7vBLLdNWFWm1ni6vfWjpghSLqvFijAuKOMwGTzXA/xIz\nE+QE2obFR2Ft0eroBBwwBYSp9IFmEbkoU407f3otoGTAzsf1ddEavhHcPVwSnPGo+7tLThPvKMY7\nbPpZIJ2r6UBvbib4WZSabp1YejQOZFJRc4uQrnWVQotNzZunsOIHrFNUhihoTaC+71XHObi49TYi\nawi8nlksuycHPTF+0x5G0E2VLMghrtQtoq7rk2aLBIlycUxm7x9erbo8ein+EGWvOlm/T8+18Neh\npZDL9pbFgrewdkvAP8N4h+pahA86y7IlEQDaBkBw0TxjSGTaPR4QzjVsNrsDmQgBZ5H6BjPZTbsB\n2NIAJQSg42GOtaUnyIdeCfiEH80DBRyhBkR6slQUwNBSmtnJFMLqLM70H5wb+1gAjW4wgJQOT0Un\nkahG9pK25nTL2kE6zHowAC/Kmv5NMWchf0eJn0vOl+AwHvxIhYz2Wtj9GfeeXEwg00s9o0dZlRl4\nVcPh45Z+ABKcMAXIYMKhzZtAJzGDpbAx5TihxKRm8rqUsAebikaCN9skZ3ss775S1HI9fpPw7N1v\noZwNHwv+j9Ij04h2H1qoFUSYszMm3w/494bmX7lFhNJgM5DFaFEnQBHaQ6b3taOqFLEtCBef0AbG\nfCS0wCh8bKkFqxRI1UfNSQK4u9EhlFxLn61F59Izk5BEZBIke1KG8nDpKuf7AjuEZ0GVTYurCS+w\nucmVaQuGXvA4hsN0+1lix9C6bI09ORxcWsC7Vn1aOQeMIpzXV8OedPXidBaSg5xFL56gkK0Qw/Fv\n372ckUsvlo+ecI3zXxTymOHg4swVfvdHR2Uh8zbNA06WmhfaUHKBRnrW1SPrgHswiPOBCkhUW46O\nHf8skympYn0f7PLEYLyyan2vjjMQWDPlEsw/uIsIOPMwS+JR2DFxXs3oogSs3dl/w9hhICz1kzrw\n5q91Etaxs5qhx5a1OtQsGO3tZ/XYk1sVRtuoe3xSVgaRc1zH59KurpIdQfuR1moP3vvDS8BhDjuk\nkwQV7HaJS9HhCVK1ddvsGJQwSgYoAZbTHw5RtgiZTSAkL7YWGxJa0qtfv/+cWEz9Rmt6UDRhYi29\nWiGytEm2xgLENNFUW20CXES5/GAV0nTlupL38MqVHP1FkROdj3SK8cyNeb4YOCoesEK/45YhZmmi\nRjQnLLVA27GTWoAqEAy1f/pqKEngt67CqtDFpXEJqBfApDTl/nQYuZsf7Wyie4vMK2E9KWekN38s\nP34WFZgrwd8Xi5S6lfBJ7yl8uwon1v8ZAcepGHVgfBWvVDURYnURn/+n83BUwUcih/V5KvxXQuaJ\n+Q1XK2rdc0qSa9kbLt6CyiGVSl6aoIXuncoXXEr/VEClMWQwioSwQS6OL+VAKZ5ZQ5/cYyj/jQXx\nxUlvpyTZuxrqIFt0x6FJ1Q5x8Mefo1b6UPCQSVymMxlsNX2FX/9vblMgDx3qXPKt6tV65ftUySpz\ng0pQD3bKyjinzR3OYvf/3OGhKhLWBEMKcETqct5mDFdZFAEYI5rWFpxFNEzLAjWNcGnB6Z/ixSeY\npIpENkBb4G7MPf2AzXViojbeaiIFFQmzKiMIT8dua6OsSR3bRSNhmDOHqQp+qF3nCV99oF47yOFp\nRQgkpkrRA//U5FP/G7Vf2KXvtfKdvcf1GG/G2XzLBBpncWCm1tk5AcxSP06dknThjPUW1cir5f0f\nBr0ZPz8E2HClgx+7HYT/5HwCE/Xhk7BtA9yHrEN7AwfM5Iea9mrWXdbySrJtsjQx9fHoLBSQM3f1\nToDA/yTK16YFwmfhddIq/lXaXcKaChF2+Z8JBzauAmofCuMVQdctnYINNaJNONJh8SnqNZ/RxdUj\nQQuvYO1SAiZ4hqvdbfAg/rY8cqp992DZwGGzh92fbf9jNZs2In2ZLXd0orsL//FbAvkFGo9CswkA\nttVseDnFyRuACFgwbpEpcTpkQ99pTFdNs/nFkzIM+BrYAcp439KEQTlMdqmvZnSmYbd1mqxABTMQ\nPTCHAk9vUfZUc7tC5BrCyq/qMSeHdIz8YcERIYHMHdASkwPTqmW0JxkKjTLUqQFSeDbz3dpyWCF1\nfvCugypY9Ws67XMgt3Rrs9kToa/tAXY6nAXTCKKv4M0LXgAiGb87H8CT8L/SsqKTNf39pW3GsFsx\nrXj0m2NgfgNa8Rgeilpo1VI75vrkX7QxX4d4V+O77p1VXa5pfFx3jcDxi48Y/t/jLAQ/0PAc95as\nDCTiGqdOxbmnqo2LJLQ/sXK1HuHoYmyYHJV/3Z4ESbMNPmz1vXMQ4VlWJsdul7hE60H4BLsXdhv5\npogL0iXZ3dJnc3vqslScxyeqm+C+6XSy3Yy1D/IjQJjBwAC9gjZUhyzAgWc3kPRPJls+KNEsk3Or\nnG3atMNOrJ9M2jMVfeEuCbaNKu1WyH3OdMr/CjRfFYgo8RazDVfRYIeSyIioOYLKv7jT6vjmWcg4\nSDm1crc2Kr2VaID2ElIANyRgNKXYknuaKfkwHQvDWyez82ncrboYguvRH7CKlJ3IDfBn+WbnVLsx\nHDVfcSqavRNw2TGRfDrPOYv7Y4ZAQH+HmE3a8hvzt+EhUqkQtpCE6TP9Fn2sH1DhRg1V10tyglNR\nb6rRoYZRAiDGuSHLvqWA9BVALOvD+p2kCnxMN2ryxEiTZcFgaSa6PspVrak+GJyIqBWWtb44T/pI\nt2mEEM7pSle16xSRxP8CzDJNvZ92u5kOOU1lMZYn+QdtbyQJSd7ljGPnqm0k436KGAGf2have6Lz\n35ltKktwuOtNRuP0Sph3qHGSYo+teAr0loAHp+5W8HZig4qLKpDYzdJuVQYAR1QGChVBhbxG49Au\ne/l5G72PQcxAeIyHrXjEZbCY9unMD9e+PiRvKJXJN71a9FkXn+0A9ThAV6ImGnwxdEg5KK3FpshU\nHWtIkdO2OEEOUMZ6VmGD5hfs+yH1TXSiXGHyKWiVa0BFEG4WyVvOdg5932hGYInuQL/EZ2Sz/l9i\n4IVGJxspoqo7FWQymR+g2673UdanRL5iil12rKxbRB1IXABz9untwOoPBRIKSdZeIMNQaoSm6aWc\nGwoarQTmKHFMzwlchGl3rFXwWeBIIAEHs0/f+g3fzj928E4vqoIU0dlBnUYFZoJ0NTT+hzPxbZ/k\njkxe8BtNWNYT6lhpu9I3VjhydehjRVbGKfbf7imfD9wXLQ4Zqf/coETXrugkeTU2fDq1Ig87ClCY\n2iG2gprwcpPcK7gD3QNbo+FrsvQPMU60pq4B2dBZ/aYbslfizM0o9fSTEsr9j2I2lXeavhfTR2qY\nZKhWbx/PeNqfGoE/BeawTV0wZz0eOYMkYWe7y5FYbgUaN1o++L+Rd2PNLdproDec2JsU/0smQzw+\nOh+gqB3mPz3HSlEE3LgtdRfL5XwxgP4Nupkw1VWJtp0UwCqsIFjnTDfWdH0OWOOYEI1pwWpRTc+U\na6l+YMiEwwaETSPgGUZcjwa6anskhwlbutnUy3C0vtusCqA0NssqaQsfYsby/hUExqdb7bErYUXZ\nT/jM5YpSSWXlE9OGujZIy9oaIpziBjR7e/3/4gsqtNGB29nwTIe7Q7s97L3Z9SnIDWgPUqC3XNm3\nEMGv0Y+bA0KA2U3IID+aKvfJ3Br+YxPdDxNXkljdTWxzKBrkfYT5H4/zoMKMn7MVXW59EMSeNAWu\nekiJXEv/vE58VcIEZ3wFbDRlMUg5W11dAOlfcu6T0FFS4+osPvhcF5zaTb690fq07avoMFKi2+1/\nDxZPE5dhUG92vTNq1eVFg07Fjx1MLVb5amffdJ+bA88TBZkqYxpqdhXmtsJvSGyvay1F8bbioS75\no3CVacgJaBuYEYOA7RtdESISa7TCNNGG7Maw8RRhOwBaw9KxxkRWo1Z6p4LwDer4TgQR1PXGxsHG\nV1aPGPcdZnm575wJvF8mG6CX6U1EII7MQimalSi4Mzp+c50CsrUFWKJxrtpsp9D/afxg4Hs3S1Ie\nXeoCCiAXCC5Ozgf4jw7o7iOzykdTjMy9n9V/lK3Vh7cPjxN5p5EBhpioSiIUK2PJJllVdGaF0Etq\nzBxPNAYWR3VvBijchM9wUT/ZhwzjkEuv2pk+CJSlfU9r3mJR3ZjT1WII1jPqosZN+dDnyu1Zj2gZ\nW9JHfdJ3RT+vwYUM7f6qBQufqFHtt6Xg8iq6BckZh5538ITdJMN29U2ibBze5+w7+JiTBzhG5/EM\nfwZ09FAVbKgsb0I9gZ9TGNSD5rlWJZmfkFOghv3mHEWm1HpNEtkgdPmr1gvpjl9INWFuFKy7GMzG\nha2aoY0Pe9r33CPCMDcXYR4Is/cImMOiobUPiDay5vqQyg/wnAjHGHCKu1USsLaXyOkBGdFII9rJ\n8x78ek2/PXrZD/cbJwjFD+8MSPvOcEB/EBGzFiQMHJL1W60SNGDB6V+ZD+6rDXiWRzAuO6GqihLS\n4ykFktmE3mftRTA6Y4Iy4SjmGQ76EzM9L6BsJrwH0zWF2Sea9ykOPNBxS4ypLFZToKYBwk18GvZB\n337zgkxv5MaDUn3EImgSVBxSWSGH0g/gs7074bxBicm3fD+jGuwXO29GytdBvo/yq0+vwBa29dvO\n7CT5ZTYslLyTdRSautCZkpzxbPVPfFou7+Zo6OxSXz08A30YlsYEXDDSxqZlFIEvTDXszB1/WjLr\ngTfmAbM2YWopl800AsO5iRZDsqlGWCAiV1r5QjEB2gvUi3GDxUYCjRco4Bqhd/WXStFAKmbJbkoy\nfbuj+o+SUIwbB+t3gHul98QkI0qQAAG6ZFGriTCr9TvSaz25QDWwq914WXZS4SHYx4FC6nBnGC7P\njRRwqHt3eg6HTKfCR0/+aTv6AaaI2gEVHR+qhANbl/Mb/R71JhbndY500YN8IboKzLrbY8gWNo6D\nKk8psGSJnLDYy92bKcXa3SWoKO4yQPDAmE9Py1CXbeK6tR216E6UHPcTy1VVbC7rY6a1AdXVjyyu\nL3nSqvrANwfuJ/P2/bETdqGKRLxeP+VxXmxEGYGYaUgU+/c51PUVt3IuW7EXu+xObWn7TlGJhtan\nFRnnza3cQD6Yw4DIN20Rp9uEzwVt7aM4hrV8dbtm5P2nB2tCDyQBzSav8+FO8X1+SZRqh4sX2oLj\nqdKjaR/RJcFU6dReqdiKgvwZ0MNXvNEeuEVfMoo5NUFjyqbnnJuFbPp05QcxfzksgGlgBB1w85pT\nJcbzU8R14nWCIWnlIpRiqOMo9TvrpLlMRQ/5qz7ii8JI+rFqsHfj5DJd1tBY4ozAbYR8E54uKm2g\n64J1iXpqtI3OBJaD2pWSZtcWejlkzYSjDCdtAutUe2WYU4adNae2ZhbBd2rtVBlyCFOnwyIbjRWp\n1Ffozu7SrIBS7KJCcefNczIUblZxT9gtEW7j0wEk6dJUNCLBcvjaObAbE/dv+mva10WfxvnNbsQA\nOWb+fTJdTcCA5gHZ8Qfz35dXwnRDSiKgY74J944K38nIcpy1KvuHU8sSUFQkh8B+1A32/84gKd02\nD4Zif7hl5ObHJENpKt8XU07nYM672Q3lpfFqRsYKZGTydMxtMVOtxBOmahvfmMj4J52gU3p5uwhK\noS5Jp+L2A2F6H7P2rbZBK4FGg4pmLQy9H5+fw5ehWHeiGf/MTYIBMTF782ip3zipHKyYBRy8N0mn\nk0/mFQ7SCp6ATBTJwN2v15xL1tvoIi90CrtN2hfR+Anwzzan5bdo6IleyN1BcuFsySDzm+14HIpb\niKvE3mluOMRBxevxfJxVLD/Ln1ju//gZraLdwsJ9wJ9W1reK+duiwqhBeNzOo+oq7HtVWQChPCJ6\nKLN8ikJRRS6luPpfY6m7G5hUp+6Is8c7HJLOAVZKitYbs4LkUusezrKJ/JD+Kly6NXa1JKsxOcOg\nuUldnSdIBVm0qKMGmOcYHxIDskO0BlcBKeig6pkQTPDW4/In2mmh0AFBtHh/H0oc+HbA6PNbjqvX\nD4aSskjT7ED/+OcOSjyNXLGdB3bfgDOgaCFBA9bX53UzbI5Usq7+xDFR2mSz9iPIy6krGH1inokX\nHyUS9YjhtLsQeKlmyFvzDkRIn9ElATYFlqdNQCMthEa+uwVNho0BV/H95H5LVNS6e3UbYQq2lTWT\nKOBsETaURthiuw8WcYvFG74lSwUlaYi/YoC0A/CqToTX8Ccj61vky8Nco6yKWs698/xD5CswgWOQ\nv7vuZWcYVvU4S5IYBYIasg29+r80Z+C3aEqpEAxSEuMwbTbiK39/cObXk5e20Q9Ne/mJB4auA6xK\nTn6Oufd5ucR5dTkgtyDj9PELRgQmXbWbIK3RcntCSJPdQJclGS/v5/Hv+JHvJY0I7J/LvJtdSNKy\nthf0QENqiMTLY2Gfi5se+HU1qmDAYoIQ4gdByG85dXDK323v4yg0zIjj7NehozDL8STzcuOyT2+2\nN3YMLWasvgmAGVAHCvnqje0GpmBX+MvtXjbe4MigDvoPuCl9KlRQJxZ1Fspgb7r/Fwh6pKLbvt7U\nGtKkWw+ORtEplWA5epDJ6cJw+aIrKVzk7TOk04FrdE6ZHviAcgVY7kNqW5VqA7nKrus4V8eZQlNe\nCxboSg+3123oY9mbWaRZn/+JzPrDXAvhT8JUpR+6pdXafdDyZ/1LB2m9Gb1aUg9rfjkoXxQxARZA\n2K7WFY/tTQWGbKeuGkSEBEpbIQZFbgvA02fCX7lrgVsiRkcbUEssmCj9Ev/qipJviRdMIv/hFlV/\ncu/UVo1BG9iGX/nysxJVhCYMtc8GynglpqFNkk5mvocV3ueTdk+0APMPhE5U8GClrz0ISFdvt+qb\nmD9osbs6Ldf2RVqRqd3Et3WVgKdom7lVoQgN9H02hcIORO+5E1NWdRzr538pVlAdYTjcf2I65J5+\n1YWyC6Ei39rIWnBEJNLS060QAYra42SuXMyWvOBMIBiHC7DZfFMobo6vpCwSbh7RFUinV61t+QCD\nuuhNj7X0zRILFJH0AUQjMm2PaMiabYRTkgeOpSxMnN+Q6fDLyZjipspJ6zCo/ZgCph+P8Q4mZihs\nrdS82dayVOkmcciZ7GFOSO8KMyq/tuGx/VuyU/BREDuxOyQqX/u0pBZNFh2sQHurqi+oM3j1QeA1\n5bJr9dAAy0sTvp6idB2o7E+CU0rsFMYW064lfK82ywl1p3f1Wc0ZWv0bzDnarT7AGtDBZBtaoANH\nyw2LummM/7DRJUbBGIYWkNhSP7N+46yJoAR6n4Vf8Gf5zqVMK/Tdf/YVkMGUBcyJ/zdX7wYzUPKO\nTvSWagFIgy+rpi7LJUhDhQQaUHG3K2EMqfCpWz2qD1+X8iGFx1Vnzch/CY4N+hWdvS3eol0dOkDZ\nGyf2FcHVDEBb7cbgnbgfbhNc4BmAcMcnwnPmNCtwxxhukBpUX2uAG+Sq+SHd74ZmBBiJlaD/YirS\n3IxCaKRwcquvKC8eyeFHoiXHlf+6O+lPy5PU1bC4398hNNgEKdq4zytncIQ3EwSuqNwY4wIc+s2S\n5UCtC3c2gLIhZPJ4dwfGVMprs+z08F381kfS86uEO6J04sYw2ugsam1iPyYYbDW/zqAgQe1vSorw\nKzV+dG7Ccg3zUttWnvpNBkTn70+1P6tLkaWYV5lT3erHE6Xlo0swIwNb2JlJVGmUjgypjEs2USOp\nWPorWCsOdn48O1WZHTgSxZH6qr/hZFxiCZw3b/jQUh6i0vF1e6amqK19W6SXokrRuaM6uqzLq8F1\nqycFOCNM3gw7tLbT7DZ3/mhBtb/pK3uyGV8wp8AV+ZezRWZvPSCkopzViOqELP2zqCPI3Atc00ln\n+nvuEjgO5M/93S8Si1IMe5PwQRU875p8vH4DzBjyiprm/rNnC2MDwfzSJKWhXc+J9WslmHGsX2Bs\nN8mWEvnVNsfri5w4ryJ8x8KLYmgYEVYASdc+8H83nCLRx29sREkJHkzauS8j3LJ9ISm0GRZfSFa8\nVgCQh8KpA+MqJPKMstvBInJXP4eeCCF9swp/9pCzKFiAwZ9PS98NTfMVzDNLs12J3pD0OkBbOXV8\nEKRCKyGH5vkjejfq38hJ86hrknbqut63faeqFQtzg5bYKKIGngzZDEkcp6SMcwRLqJktRvArGWky\nsv0DMqB+/Ou27K/HOjNmlGWYF7KBq3R1Ni/k4lMFY+AscsdpQYJTy3Z9qBXIwOL7iDT4lnFq1oXN\npVm3uhgmzGPRiHV72ERe0QLlbWNMuhcxl03qwWc/fiM0Rk5ArMJIr2nKAwtH2sFOFRXDRG8kjAET\neHgbJshpfnmemvrOV/J4zDJwC3L7BR7+rHxxvMNl7PgS85fI+nHFDNbBJMzUoZzrJE68qV8Ss3nh\n9LH9lk3g5RDApNU24TgdrajhafCkFeqzyn6Ie4ZwAdwR9vPD7tTr1XRZID5Ws7zilSrDSioTSxkq\nYkI/q08jhYIvCLjxlLdbdJleTZjj3wAwR8QZO+yoyEhVi08hWVoqFXqY1DLdI11qAquaJe0JnIMQ\n0gxvZzsJzYQ5tYebPH1YBHtDgBBU16Ykg6PNiInDJuTwXH1JgU5M+7yOIVLxq/q8MiSrn+QA2VtQ\nCgFlVIrH7IufP7PI1r62Tr/twZfemM70CnwxppuUP8TIO4kpEbBNjp3JDbILwLPEpZaGKYzasH9l\nX2IjREa42SwKV+RymwiY4F0qwj+FB0d0DzgJnNNcU8xLoClYIyJdKBH/FBo/xrrPHrYdCCdmW+Ky\npTC31BW6WhATUo1GX9dgJOqMcfl1fz+i5yt+gSjy4IIKmS5F0Zd7Dv+aGrexZ/a1K3o1dUguajhB\nABNMCN1ghP6C4s/TIcXEH6bAHnrow7+Xg9NGk8t6cuzdz7yvSCeGGfcxNf7Q5spop/pqYOKjNa+f\nHpy/V1RyBc/Ufw9OZBfg6TIKg5vr0BkQXiTGYizuYmkqXTgdNywi4Tf3wfXGNx9Ygui0qZv5wIyU\nGJuZfyp96fm+ZRUlZRJUCadufSKDeC7ojiPVPnsiOWMQcbGxhKAcZG9PWJx+u2ixNcHZoS5igHO8\nWru/z91bREGn0CZCG7q9u0ZjWBNsSbfRhV6AuINVXB3K5lkzjXlTi0mjh0/1dNMWjpMuBLwLx0qm\n2NOLkvGz9rQl436b0WezuKNyB/OEOnWJXV7Fbq/ofPNqEs3XXRRdXoh+aAobW+bkPZKy/5TLcnaK\ne7Dlxyjpq8fdxi4ILOIhEBB5GsNM+oGX6vEBogAjieDdd60yNxDJyrnJbrAgolwuoZdi5hQI0THg\n0IMqv//izJUzXTjdizpUYgUaiRpTxqElMpDrP9c0Q0lgltNHHAn/+4sjepNxAXMRL0RLqfzhcD0D\nAz04K2TWHXY4shZ7bKH9XP/uP7US7O1RhfTIcdJHWL2o6Lz6/stq4Iqt2iP2Rzj0z9FLGinNulku\nAo6ZeJt8AVXlLY6r+yo67CPcUAFKhi+1tjaRYS3HlKFdshjeSLw/3LShIIkCdtfB4uh/tFYZCH8U\nhxiqUAygzrKSUsO6ZJikFQUi3Qclbr3XTYDUUq1VVo4bg1brjETfkVxnIa0mLaPxKxTz81MK9/QJ\njy6cyzCUXjxY0Wc4S0OPGwSIFYVv7BCvv1ab3/eos0alsau1ed4TlRBxqRZFiKqc62+EJ37Yko0p\nvJwWov/ejTLj/BYwvwA7fFD1upiBKr3PSyJHL9VduPpd/2POmMEnce3VyNY753v2FxdOkBP3mpo4\n6S5Fwm3vSCuQIgLAltlj2RC5h8ysbUcU9qGaXLWawxnLVjIgqWqx0IaMZvZ17jvsbysrMIHjxOVh\n4xX0eQsfHnYafy0NDuQn8Inww1XteEmTrZRbD/tuIwl+7saSUHJPtQHeuYCw30faJB3geOZNnkYQ\nxA3yTUnia0CsaaKJtTrmCaF+xpwKMHQPKH/y+wsxE57y8DWUm+Npl2BOtS+yU8W5/Fi6d3l5lR6/\nCxZl9uPYYWm9rvfPHIAi4Hu9H3aCP83apQsfosbDz5PFdWxVMWLmGp6oItEHmF4gjxifgnv8U3B0\nBQNUp2ipGrjPez5xHMcVqu6bexboglQ1YHghQAuVfZuInqgQ/C8cjJXPhdLbLpxvqm1YePp1LWNM\ngltxKlc0iK8uxyXdkq5Y0GlqKUN8NFHXhqmfUnyX/SmUqkePGn0SN1983yJLBZp/wewe9/1T85b6\nUI/xwU8Je7zarYzy3TPDeYTUg7m8kpyzNW4zJDYDqnx4BXORRE4tf+5w9zYFoxzuFtZmDN9c0T7c\nJK7XitHKwbXj15eaXdWut0pzeMZNdXJrzlglVrdsoVOYa5M5QDftDRCCf0C7yTgUia7DJREeNwO7\nntZseu5+diXNvlbOi6O/kskkTwUkHNzwpS3mC+wx3Rsw/Y+UXRBEOqmmjU/rjrhjkiosSEg7NqDe\nwrsqvVAXMcbQ72+wOqUCcN1JhKpod6M1hYYSJOnemFO0utHaZDsUYK0LQRvulpq/zGrFhLruAXrF\ndtZ6UFT2O67qO5Wc63slVaWE5j/nQVdK/GZ8H821H71QLVnfA5xeTjjzrK7rdeYvWdHbuA9JKVfT\ng+f2imPOItub46Vu5I1AUuYQZ5sRRz83HC5uB6jc4HlsEe1/Znf6nUx7zAjYFYU4Xf8TuYMqNDke\nKbBL8GUy1ZRCg2zn3e+tVcsNP2dXGwX92PV/iBoqfH9tYSkXhsLtaZaH7SgcjIvNmHstR1PiN1MG\nsbkZVQlP1q0VWjPmwjTtKfbgPIBb7Anblbd0uUDpjzBxP/uGM1O/5zGVdPMniXyVGfPgaDkGUh3n\nEEE2S1YWKvsHLTozRtDxS0LRlFh/fI8OdAx14QYVSAe8/tDG2evNeyEyJZdVdVeJKF/LgaQ8TJ9j\nRKBMpl8La3wF1WpbEYorys+26WYP8hktXUWyU9O+UNeC/wf1fH+EIJeRJpFprpxHq1U3sRBE7AS+\nDwbpsb+1OCxQ5qJ0aUV49QHjwkrzHRraOBejsnWYaP2MP4BP2gP0ZIvlXWaL4XNWFN1gkBAUyHkd\nfzPTUEwF2d5B5fGL4aclJezyNe2WO8S9uk7bC7t19TKtkz5jojr9JP+Mpxdt+CZqKw7CgxsGFDPW\nAyslkvMtkSNfepuW70IOVsigETA242X7vWCv6bhM68vO9vmv+taMuWuhhzSBXp1WskeR+e6YAMpR\nzbN/hktQI9tntafqenXPDKkQxTO0Pup31PMgOPrdTreJoH8idRvZ2a2+Fx1ODYCg/AZElP5GfIB1\n7yQ1FAkb7Ux1SAbRL0sLi0Z03pKfKhBydHWlrlfjzsFTMc21q5rwmgCXS+PUp3DeaQGdeGbOs3vE\noFBk42DXd4fym3IAjfxU5rVIDHiwbmQBSV1gMwH74fGIZdVvatcnoYmj9z1BteDSBWXKpu/L5yAv\nQQIEgHcWH8ePbp8Z/b2urWtH4EIWIj8JRwBS5XLWAQKe4qz9+JB5QkK9t921F1BQE/GWUW3DBCGR\nEF5DthYc3nS3paBWyC0DAKJpL+iJQHEdmT72tOWlChxfbH5gD2sNImwnk7Ax3Hq9YjGIcESF36fm\nbMUQfFJW0iamtgTUFo/bSXRs5jCLWxVUdG43pA9NBmg1a2mIgPvLxAh7bYMR6vetC2XLwzpbrk4z\nb49LIkIQwzwDZPsgTvB1vgJ+DS/WrX6ydCdxA2Dyn4Ox25MMqnK1PjRRBsdXX7VNoYGvREG7o8jv\nXT/6ITtTNdDfbd2tbGcnUc4eB+eXdjGsBEzT3eSsuqJB+VctamVrlZb7LjfypRdUvYC62WjbuRey\nEjO/6AJaW0qtOQ+8wuv1kZpXOfZ2Whr7vNBQQ+EQaTTqa0JeB1F0UbnXxEYmIHu/et6K40jWPK9D\nf67BhTLypVB6xfuzDLv62KScE77SczuKswJRzZGG+BDj1AnnKcXqbaY6akYUqGia2iv/KWwMmrKm\niAfIWHUuZvvadMRMMJHK1NjnRq1XhQKxkCtxKGrz5jC9DLzQGfM/IwbHeT/TxvKgvRIUkaTM5sR/\nFQbdjcYH2Kefa9bVsxt2JB5t75WpLRlk6kummvd7yrPNV46YVZHFoaGtq10I4O/rjRK5DentrWfx\naJmLwxV9d80e3Ob2daR4NdwPFGsEvYWf/13s575Kc3ZJTou322ZlojazM3DJNKnYqgtusX3+qYDj\n65+6/KUSS6+09bmkFI/ZpsCOuVnKyXJmqh0B4JwLsLs+18AaAvhbYLCOU6H37t3nyYEKVfrLyceH\n9UBTshgaRadF6lYixAbhEUtwLuEN++FLiusMB77TRNaKAgtLo7eqyymEeFvRzkkxQgT9jdv7+zLD\ng90dSVQ9PZEa2U3CRj7cBt1a+P7TElDuAi1eTMaZIuLQp5N4fbFoYbz4WfUMThbZvqvWFm80IrRW\ngB+Xd0rEoGH25lYbaC1PFVdoKGnS8aL3A6r8zb9wHPKWDlJFw18Z5qXcFVVckpxfl3Z3g+Lx/9L1\nOhA59Ky2R/DRLtKV+ZeF/4wjeG5pGKD0AUAWoHTTfY8vgkcscqrI14Ku3oJSj/ojzwN65s05ZNJc\naUk5DZ1nZ6mabJS4XKG+ql0M5jIuoJWbNjnE+EA10sZ+YOFD6fSMpxiCx0nkKges9BBpWLcnLG9B\nB/dNLnm5zUsiGUVNxG7u1uAQ4qJP82OALoR0csTHRXuXo9zmOjv+lkW8nYuXhSLYNp2GEmKa1NPx\njtgbem3mIErRXBmqmNqnQt/Uxv+89cqgn5K+Cs5zaeAb3nHPCU1JQ7l91pRkWIT7dH0t+1tOeZZX\nQmwrPC+TTx6UtkkXtjl8v3HCuY8K3WnRSUmMVDI4e41LfI4cHSGHIatSwwt8P/Jklp0OT6Xi+kjU\nnytws1k41KGkxVl9VTOuZ+VQiqkDlCNYr/1CV9+yPvZqsbTxfJko3+jvDrEyUFAtrTgXpuPFL1EX\no3R2OGkEK1dvnsYcaPbvPvbJY2AjDWQZr1oSy+bevWPFpf0H4J61z1bl7F4/zLhA5q56iY97cjjk\nEaMC8jaKUy6CBPi9RyM1F2JhLMrIfgxoJDvEmh035VvuVKxoPabUeh+9+VmudrSxWP4kIJY/oeAg\niUo7gQPsOEdJIEwRnJpHH1wa89o+v3bi8e7hqqTJEo+Uhx6c7Ntm2hbW0AHs84eU/zx86zyyvzKE\nAS2eD9t1V46u6bPOuW4E6++hFXowDkc7hx9jM/VvfEnEgkGPo2FeQ/suznSPOQ50g67VO3m4CKGi\nBA1sOiMsx8j40D9JIcb1m/pC0GwKsNRRHc28nWp8aAcSg7EPeZPE65PCU1+zK6xbwz4k0LHQn5lP\nMFOKbfCs9txiXMmS7iK9qcdzh+ujtlBY5sLt16ZymXVaBgunA6eiQANacYj83AfyOMbjsHINzpeK\nXOTZh7vnoU/iFhgcfZt48evqpfpOg7OWlq/iTdwtQ3pUSBEwnV+4apiqbO3/R+GgxMr4WsYGGIaW\nPPMx8gIolDlMdl4EG8k61hk5skPb3dDDqkyf/TDsOQCtfO06BvFOgvJtuKLHJ0BpMbTAKi4i8OKG\nn2CIXM10uYqnw4VUXCtwvS+1S/mbmR5nnoLrV2j1zJRpIZXopqWTnXYAmPEdgjzVsNtCZoiiZrUQ\nXNhVqJFrp93kqtKrNvQE/hR+1FHVhfedmeaFNyVtuuXiuaO/MfLn5hOZl4wqMMrQBicTGkzlXdKP\nwpS1+5t54OQ+RQKM3oMbW0FdxJR2N06vchMswX6i0snthpOz7QbAfjqRcEq5jJQEoH019Yqxto1j\n1HYJfMWN2PkkTRWQwmTIV5KyZqmlzzl91smvbFcSI7Lbctg5UU/LnDxTK2583MtpRU6vM6J/evi9\nz7ZfmqV0EmF2RlwNROGvLWAAaKmQ8bd39h9/t+NYu3X3dXFURpvonlgbqMaUDQ88AVr2sqGZQN7/\nnxsVuzFRg4AlW963qfBiJjada9ofPkUlHqsUSpakOYdynW0ufEICytTdo9nqpYuPZxq0zGZAAKYN\n/n5GmZEWp9mcrB35yfIVFgHvELIw/RDD+1uTnPvQ1500POD0YRJej1WuHyO+8dJKjdZse0v50P8w\nd4GKiLqefHmQ1Yxoom47LiHN6VRsmeDr14EBbdxKDf5p2mbiJ63IfVifXUqQ2lILtO/5YB7aT/vn\niQHjRLxcdWscwm0Akqj5hLtn4nCtTZIidm/6cvXQRLtgVMo2ewXAFNbUYGKwkpamxfCyYZRFRqIq\niV/isBH+2vARliuh0TX7VrACNkPCFIexBngmv+GCcXzmF3mXNc4yovsKOYfCgqNlQIP/6QBFzviy\ntPIAtexL/jHOP9Np0gqO5AESbyjFSBm3WGBECwN/IuII2/lT+hz6ffiu+rnpNuNsPAa70FOn0qrX\nqufLUpM0vol2qwNt18GBrysYa8nVBbgDNh3qoPSrTtBUO4J1LnOK96Pswtp0acL0mlhn8c56eror\nJDaXyhzaGXucaVDi7xwnJwmYjsKszC/8taUN8crVsPolL0EuJxGJwy3oBod5NjiwTnKDj4/pWW5E\nYCG5s08p1B3fmAIdW/NAnxQ0HkDD80PvX8IchLc3cQIzIP4TMOgbs1lcDFwiSEXGqGWSWQup8kl/\nZKsLPMbryxLNMoTjfLpvrkEqoClPwV5BZMQSh2UF8CGcWt2/2l7UlgmdLnLeArAuGDCjtXW4xyGu\nMZwiDy7mN/i6GvuKTrYWPNNpskpO8dc/azoCcyPeo7eNDKHIvJ18JaMgrKaPl51eF3Ds4Awwn1cV\n12KhFYw5oi3GspeynGx3SkIg1ciXp2gk+rbQmOj2z37UzAXJj8/t8bRR2cZgWvOoDhu1YmFL1Yy5\nHMe5PMtx6yzGZWJU0hHqXH/wDSRKFGrr3E8k4xAul61g2SW6IV8nn8cwM3WrYqtyeDaX569gSY7a\npsXNBN3LKWZEk1fvYD7nvCkYwDykGuYHS2DBVkjlthvhygWfRoqABd/pmXRVl6F+A8plXwk/OV1c\ngrg8Cnp+HQ82c2C7D4CcrzpGrK49tDHSHWyiiVqLCU12Cmzef5AJOipTLof/ob3Yu/BrMVTEabjK\nkfzG9hptuJx5m/0SPZQFoC3yUjK1BMEnGT/C0pNrNiQDIgv8Z6oo0Lk8/XUmAE4QH+YBx7QsxA0m\nr3YkK1aXlsV6BKX6yTgSAEe7arwCWCwazSKJuP6p7t/s9Z77AKCSGg+8bCK2kRW7NCKTmpkVGERg\nGnY9bssFFXnAB8Mf5oTCsLuo8C9xKw5nXZ4Cs8H9RHWrA6dPOCqcVpBzcSwDL18v2fkIxXSmk0P8\nt8s29Fnnsw2T/0W4xtmNbzF5+Jjd3ul2UclkaxmfeIZ77RklqlM1BZMITvOwcYU0B2pN8G2uhI1k\n4mJ2LzzDPVgfOB6QRG/TLWAw7R45ZFvn3CAjehdriI9YD90OUN0KEohG0Y4cBpwnNdr+gYwRCzts\ndYHTg226DjyQRq3ouw9VnGR5e8SLMmXEpr/IlN8GKf2j8swGwCrsbYtSQnALFDZ0IvC3h0aefpJx\n9wEDzD/gfLrPmu+a1lW1kvmJxV+lXtGxRuxGgINPGEQwiYBtHV779KdaZ+dItydSVzTgRmEm/VG1\nDcifqEngPjHUa3h8ZmAUfmmFIp8w1LA4mvTmDcMy4D/2YVZS257B0xB9spvjudA65T5JYN/NwFA/\nR9djcwJIhc6yLmxxGkyWg/HpmP5SDn/DpuaxZicYgkJmQ9CWcBCiB5XYhkd6zrKEyRrth7ezA7nx\nfpIW8abCJYSkcWBWMYtjUL3Q8d3SAsT71JRgFBUe+VmPUJiGBs1A5v3Ncn/n7hZmlm9YGQi9kzsR\nsV6wn3pIXB/rAk7z9fYe8isiawUxFwBVSpdvvLuG5FqJf3qQ94aM+zJT/jh2fZGZ9hjKX4/tP/eO\nzb7Iw+gysitRMZqwUYxaWCJkRPLcNIW62KGMT0/jZlHuZ/TLqzSqiy2HaSJr/V2nQ+mRFC+JQW0A\nhSBEV+Y7xpKtm1i438Pzgu5kl4MdowYdmkYHh96Y4bPpy+h0saeQpXPpSXjILdUzzSJtja5eGiTd\nI+iLJBoQP+13EvhDXp4SOulvXSS3oWf4BYbChnWpPTqvqQ74LO10qhWZlMFG2xT/nNkxO6c8NiZM\nstGLs4XsknUg4kL2LcEe8LS3z7l3nIlHw+JgrnprVS3Ek00ARQ/oL8F2DCh24QHmZlyGJYaBpmAZ\nKhEqVrAEHAOim4pOe0x7h8MV8WaMsOxl4A7ho912OM+6mr7ETiwdBlDx0v+whSrQAJ8TUAPggBlG\no8DRZjPZ6T9iY2PhQhgsi2VBM4A/UZhYV1ijGiumm/VSEAsQ0DXjtcPlWDM2H7Mca5qpxEgoYNCl\nljYDZDZQNPjwG9xeIJY6e1i+Dnqf+ut6RHOSp1tpctS/dPv02ov7qvSpJAJ8VGxqddWnzyOXp/1G\nAEEOo+qpw0emO4gdzC6sRz70tfiMn5CFEt7mHxctzGQmUkx3PIfXFXxG5nRtxb6bSgi1DMeG9K8L\nbVAHL0CeMygN6rzIpU4ScwLWusl/FE864imdSZnxfUuIIyVgrR4wq3ST8NBLC+241acR5hvEUum9\nzMkhYOJ0hXqZSpS/SbkRtMooYcH1vxvSScIO/RdIhF/gtJA8Q2arCgYPU5GIPSFaRLXc6C6PMpWS\ntYpaOe+1owFjQwOB1cMpLWFk2GRW1Y75Q8JbNqn9+9EfSp+0eS/htqrozRscfUNvxXkgCtNzBRYm\naCv/OmFP8OsjaH/5T+1jdPsYfiKTPTP2AqTc9sIWeAqlreYeRjzPWhRpmudyqct2U0j2km5GigvW\nBHS54UKJ4fP6gYhBq68UNSqgTbBFriVAjxr2Jc+LMVykG1LG0WnpQOlUNealAZLP01agihevOg5q\nUWy2nqGI35nwzUiqpNICf2OARedmUDpUQifNPE1cS08JGUCMh6ZCM/JXc0oBAWE8or/r3OMuoT4E\nlqvh6zVGOsxpW9IVNMLtn34iQA1UtdrJ7EN8HtCYkIcO3VL+aefUblzvfcsxE3gPJGako3inbacw\nwAq2Z62Q6nFdTywjFj12Q3Lx1/U2wnOA1vkwMSs7zWF5RX2hvssdPs0Lc3XtunltAMyKVQ0XKjQn\nxSHjqxl7YFKKraBz+PEh21pTYfoNNdKiBXw21kQp/dI9LlCtyBGw4bLqnZ+5muXFObp4MU8VKLkQ\nwyPg7QyEjbINvicDw5wL+3rUSXYRzhxHSXgmjVBXroceTXOmrHMJZoSzCOT6BFawyHrjNu78nLrW\nvvP0OaElAGYc3NQwwWRWWOVt+GVDyidPzX9zF1S4Mw5OUbpLpwcT6bPE+FyUB93uNiZlNWtmxOHX\n3cflCnC1fC+xl4VXf7FNhsMT7+gm9GeBNp89E3BOkQgrTs+XujPCrMsZPEU65wAj3O9Tfn2q9K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R2LPwoU4+oOPzhaD1TNGv9ud/oMC83cSewKcPUV3relZs5HPXNF8Pz+YrKOGzGat4Swfxisq\n4++ITYzD3USou+ujcuHKRx/TND1z1QhW6/8a+RKa14CS/wc3GpAFjbvmrhks5rT1jvGGQMywP/It\nJTfHkQALwVIL262Zn3JfQWixASh8aTv/ZNmPfOIaUUt2PrWDF8kWoB8D9Q8bJGXeIGq6XibdkXjG\n1/8ykhwjSsM5fJC2qdDz4HHOfCvn9pALfys+XdD/I4EWQbXWRkt/KBpRNCzHoeI3jYm3wyK8MUlP\nq7Z4T4M7KXYoWRWbA0GO0Rq11MMAHGuX76LTd5JKSq31SgHhq3HZe8LUhKFWldkAfPvNODD6+Cp6\nlYNTt7yf3H8LllyV/oZjNEHxiS9ith6A9m693kR2JIJtVk5CVuRpQfdQ6g3nF/28Pi7vYhkV2nEV\nRI9OGVqY+8Z8ym4Lrz8ZbyDSkCmfwxH6xyUnJp6zRRR+OagwbF/RtC+0AjTgIZAxFBFKTp7RF9WE\neD0idqsEHJvMqrlyEiZYShsCO2et1zXjK+PTEhg0cmEsroqd5uQFLbR0TdDjaqSaRjbnbe0swwq6\n4f8cGFYpZJNSqgn89ltf9PQMgtwVlZinVJHWkLYksD1VYc9yW7MBOdrcDvMBOnQ+cLvEdVUbEMLn\nRcq87ydocR0OTr52lz+Z94qrwk97cdnIE0G1Z+Hlb7u9PDYKOCFHkmHFWPyV8oY2fsTfTQkJr+mF\ndIuexBLn0q87eIew1q5W7XjfzhLkkh+LAKeEp0gA3NxocTiPyuvgpq1WAbDD4+rt6BoXgT4yRnWO\n1PAjPsIQ7xbJINs2YtM3dhLRPx46VBTJ5GzivtKREfW/DQ/dEXrPeA/ygJzDfCQGXRwKEDEeWGcz\nF7K4RhtHBdv0Efm6Bhu5hqWEep/yNq8GyxvMNmSbQC9GSKbPhDZkJO9HY6CJPftOeF1V6tYctb5H\nhSHGYESJ7IFw6yOANhHDoWqESu3y2Rg+VoC2OQ/FN6sjuNv/Tq7EnQpbtf+URhrdn4aBQYqyTYM9\nAaznW8PxZ1ekxUsagIAEQS+VycO2RdYwySNe9jrjgv53ZwfLFCr6hocDpzn68udP0t+C11HgvLtU\nOdwb/s7hY85+6Pm6wCrwjsXAM9SCiTnedvk3ZcXgXRx2RXDZAd5MfWD4o3QelZ9iO93NGqqJOyLP\nkQf3ywTgVBPnLE6ubki5JAt+71jF4/BbgQal8L2cpmvOvANjW3+933vnTfkscfKHz3wSaUdV2lzY\nY8VqPuPCK3w+YXoBORYEAm0ess6c49cTeAs6c+gQeIzeflgXc898ZbCrDPNiWzvdWCLc4bfewyhS\nB6h4yo8CoG/3qyWl4aCqy8qC+eBJM5ykmpGqgJN0x02kzhTGWxPt1czdSk4J94jDK17BVsDWSnlB\nBAQ/KVV2jQEdP3OqzpthuFBjuJBVuBeKQ12jyz76gb9gIEIuC8JjmXj/Xb71Djd1s1G/cSjkV5hz\n/57X7ECZ6mTdWus7TSqfw+yNhFLKUxqrzgutqRHCpG6KgSoMicep1fT1t49UXbgZMhsqqGVOl7Gs\nlzv71DIwO7G9FCX+AQEBhIx7wSzLQ8IfV6Sn2eCIj5T2hOIScr3jh0XhtsrrGl2Gzpmoebok44Em\nqTf0/qzNDNyYbEnN57QGF4k2EAPZvcdeXTkR9SbtfZPmbEAUmsm5yuXbRq6/DFihaQ1uri7WjL7F\nHSPlM+vSHeeIqWEsgnL/a9ov1qCs1HleSh7/hMN38tMuBTN9qZhZ/iCS9CTDjAx///P7Qb9gQdXr\nGxmZGrI+O1akjs+Fc+vuW5z3H0wZNPcNu/DYxnVFTpf07rzgBpNXa7QVbbbE+37F/HdhTOlqlAJv\nGZiv0dxFSXni4z2wXmo2nP8rqM/sSfujJV3r0JfAxrWCT6IQ3fA3N5ZxCpFuDvqEhqaDaBNQJlwj\nhi4Z/hFeI0FQfxcv1VTgFlr2AoiONFJqkHDi1dpSfadCEbZoin19yk2HxVJm18vfbR9xjRCD/AJw\nSFdcClTGy2muA86B2cSjD2ikqv1X4lkRL8Kwxpf8X0PmiCguQdtAi8f2TS+6yErxXAaiBzL1oFjV\nZTOyBZslreoFJgZ75zx8BWy3EsDCU0sT5L/Gp1K4z8tJzJAptWS2mrJLmm8pVNKRejqwCjO2+1b2\nA5yOyhoy8Ui9g0g/eTGFwvZuC8baZsvuvLVu8puHGe2dueCvVavubMQxzKuRkKCi5m4bI87al1OP\ndP4O2810+LQYDiOVx6sP80A6QnGNuhZlraAgm69D4X5MJY6Dt6Hdf6lf+bMMhwBAtO7TBVGswdug\n2sLU3GL71QJ7Z2Cf85lJJRNwbs9G5VPQVMEWJ9Pm7pI5DiKxRf8ry8zwNDH3pQigcAxaiZ9UGJ+1\nWuwCwnO+H2I6/1GNmjdOtJJuC6tOSUWJpyy3BSgmV5ipXNAZnfFPmOt6lZHr1tTotlIk+NIi+3P+\n6gEvxtpCg/Ocd+yuWSscc+7Hm7Cdx26lzAyZEyBHHZ+c5dw2r+aW2ZEcs6AkWT8jcTiZct2WtPYw\n1P7UEKiYDASCIwwa1CTUEBD7Ymjq9MSbu+ltgBtwA+GFMA8c/jaHeJQm/qDaKYMMmhlpoEhuotbi\nhzI7Gsv7tjTIBi4mtCYbb0HT11ycWkHrULortMunSs5vs6v1tN2D/r5/kxzGDtb0aA5RZfh6aM5o\nGz8BLrxymlrpypvoes+TLZwSUD44vldTyMa9qmYK5wHfhnA/ZHBZORDk+nlWefQZpwG9kSXwms96\n7R+Y1cUFKlIA1XBnc7V757jBOgXrnauJQCyhxiBgUjE4Q0IURbXtwpzNEZjQ0IAboxG5U9Uhw0o9\nPdIuXRoWfnnDJFAUTMy9plFeOs090d3ySF6aYOXRLFjHgoDsID/y+G+sb75hcUjjdZK+Cr+x1WUn\nnMp3KM8blv3GjXQJF4ZPJwNEDAPtatiSAY1wWnI35pibaazhxPhWywuBgKowE6sI0MxLdr2jozsf\na8u+JWrqYU8Tse3j/iZ5zcFqv+kqNGWcqNuukcPb2YZJUQFiOOyrzLsDVjsBWvFynv5ofIiGG8K1\nxYVLXIlr4M1br+gmMGtxW/S/t4/TC7bzXIbYhji0Sd3wXNs1/Hd7YnsR1sX3ctcxEPuOYcpJLIzm\nWKIYDASkHLnUHrogVbV9Aaj64/7/YCpzHtmtwcyDYxbJHjIYzQYgN1eDzFbTE3ci1xPLGtDBJUQr\nV6yjmyW1DRrJGStkhWT/R79wiqXZgdwTZUVaaNwPIu9GJ62mWtzNyPxMAwxV2DOojEDGx2NIjHhf\n0XCMpqvLKjjca8+IpJbT71u9ZuOw+PCreKogQu1HjtiEzfadHxyOgK3GOVvms8NBgkTABGphCRpc\nchRiEZKstKvtpsKg9UiGefxKUHCrilNNPGPs4VQpCb44XOD+6aKypQ9NqyK5lFKMDzhwrtruKGGm\nJFC3DRmVUEDjbDAKQTBwk4riobzY+uqyVx/JUWsrredIF5NCLQ42h35C8R7d/z/y/FaO3Zd+KBQF\n7rPf9kVLSE39P0ZNe83gJHIuzCs57s/BJ2KOwe7HG1fU8W0PcIsfvw6L2K2cRJ1Y54G7x7h1vIRq\n7do+EKPFHKES9wkQgD1GheiR+E/dMRL0tHKIAO5AZvddNh9CtlkwsnZT1/oTtBDqFcMiNnd6d3Ow\nOAKJa+CrdhsKEvohgdN1zRZt1ZJHOmkiISusSAzbX4NfLikHPUpbibFTrNQNg/SoH/c4VO2yYfrB\nbQ1hEPyHGIuNBThIcWdxFAW07qKR9h1/pmLU09KhtAwXsih42/rdMYYZ6GBx0lMIjDDaG3dLGNSA\nvAOQHGPKdApSNiYhpwPE7YV6vAuGUsuYvi0HNZxX6WR8h7AKy1zt6+I0NCSIU79PZ/NrgBx72QV0\n6NNH5mfn20NfDYe3oIuvKGpQZea8/zceBniP4O6bxkJWg2HymCbYrGO1ufF1x2cFLbDmnuhj5ha7\nyfTtJ+LR/yDSK5TDrDuRQmn2mNUrrO7N3aXeaGMEqYUGcNNB7MOIuu8hLTLdD5LCl9pTCTEaaV9E\n66M8F5dOQUaQBGdjojbTKN8n6rjGkLzZSxnkjgASAYb0a6MMgjq+Iy0tGyXslN7Obfipet6LPMc2\nSDxPsy3h5hqHpdEfQHDoXRE5c8WVqUxIillrpNELY//DN4uNboioSX0fWahAxBW28xQ/F74BWQqE\nSJtl86MlA89EWG7W1A3VZEZvMDMBNOwkAG7Oy1Q30tIpJF6qxR71SMjjkHn2vSTqALwxsgAveS+m\nHVGEz8qm9io3WNeEJx9qVzq/3eaLY+0sMN4yrd/2IG23RgXY8wV319kZC7n23O3QuEukVLoqshIW\n/1frBlBR19l/WL6BoyzU3w5zXNABBu2vcrob616VmXj/YdJDm6eKrNDscvB6IbPXvdFusdRLzz3r\na5hTB6oo9YK4TxImEZ2mLqdz7YlmyKnAhDl+qT7gtq9O7Y15lk7GGTLuXTkbJK+O84kKnIy3QFcS\nLHbUElLvo+rEw9dzteaCMYBOzpYwoeVhk+1hERSOXNVk6IueJEdFPvcyMEWgJv4zp5LL9p1z9J+3\nPgnCMOe4uiKhCDoNV9Je1548ty5+i67Nz5xnTyUPT09ZNrpKbNI4FoVcKsj1uohZcxvfBdGIOf9E\nP2akZVPQGKAgeOaBcirBDCtUdEyx8GnV5mpUB6VX9r5eS5t8E8XLK45QtQn9l50eUqirB3lbrAWn\nMQl4WQk2kBhNwwaPP4fPeDdKFF3zUC5TfXtS/1/alQPKnGqXB0VYKvHw/FE3tSETyLxgq8Qx+3ad\nf3EbD9+SXizsZIpBpB72BfBpnz1H0mgCoey+XnI6ICLQmERAwZpruWXeK597aeaVgy0hx03hwij0\nQdCrVq6yIHPkF79y7ouLHA6H4n6WcAZwEmCbLuUF3T78v/MxTTUnSxdJ6lzFupHVC+IpzwW2Dz5N\nOPbWU4flxrK955NdJIUK5H4/VRraOGhlptgJMY1woOYeGEE7z/f0r+CC+LoF8Ph2STvfAk/GvdSz\nGe0zT7COVkTxoUHp2fN0xW+pkQl1sV79WNoxsAbuWWwFPa7F3qAgV5zU538iRjjgL5gd7rFilCHJ\nTMveBxvXdRXCPM2vP7E9o/CageMfvDsDh7uM2nCKlZugth2n09rU2nrgpBqFzoQfZMyvK6cYeAoS\nKsk7OUEmQVTyhIRmuQAY44FtfH52YT9s+lOqiGyxrW4wjjUYqp9xzmYg00bgu0nslK4geoW/Xian\nKfOTdMQZPYP+Fg0PXP2e864KwN0Xd7ZtWjtSEEqI5Z9YvfjJwSYt8x9bbF+Fwvok9BkgdrWpD4rR\nNEQ4xQBA25X+jhEeImX8fDlRhzl441OgnVAshDRt+C86+dE+Y1ImANmGw8Li3hdVniGc0HAtTJU+\n7WvnWW5qT5nBotKv6RNXkNYZLRGUPFftts3FzB2LNOgEEexvSvTxMIfH8HNsakPVVMtq34fxLsKY\nfDARXbYnb2NH0a8xKIVjvWMWvKISObnkeSN4pqscayyf0E/7JRqkMyrtAixyCCgQqEvq7K1vXVPy\n5c96/ElVNm6aZn19SAY51KGGxtFmq8EWuI5f9zlABWNJ7XayHk9ayXEdVAGuAwm7fQi6XaHH3eua\nzePrBqT+CzNw7RuX3UEYwL9XJBTxByPK0j+nzfRzHhBGHppURpcz4fQ4rwkkbreRFDqChhwiK3sj\nl1np49iGgjMTPV5aBYgp3AriwU8KIL32X8aF5uAfPalK0KazPpj4368sr66iSgNy/vwno+1Xps3P\nCBQrjEmcfcWCgxxK5oP5h1TN+JVhfv+IuvtK5w/Uk4A8vI5O+gGZLIdJtK2RZGiwk86fZ4X3GI43\nyQhFWmgF5/LQ8PWBOiHYMlchc7TGrB4SB6C0bIssvFK9itC5TIDGkEkOWi+6cbXLHhwQMGJ/pMtg\n5424ztPgRbtSFxxuL1oWOMC68BrUhz3ZuM7BBSm/caCf8ZcDp4IpHk6PtkP7ATLLoCTnPfTkWVLy\nTZkHLbsS1UskCl/evc0t6OaQEXqSeHXbc9vyj/s3HIkHGS8kgVViHdrhs6a0b6GMfI0uloHg69cN\nrN/ZQbcXP96sFe816bcgb8gvcvYEkQ52dt2xkIeTFyEkSfh8BTNeWVFMZjtuLfRDDx3trdLAs4pz\nimn7MKlukt7yvF1mqI5/WcnS/uiuYI9vxadSZJd0bIbBeA1XzfymKX0Reml6GaAXBEviqvtohf6L\nN6tJf9HS4Ig6SS7s5yThfp4Kq345OiXpNGapQklHD9jz5nOPU0N6dOMjZRCKQZUyp3q6wPyDiUAz\nPh4U+hiXM+ZRB1pbl+MxsVQWUB6ioHdsEXKc2ePJqk5iMi/F8JGnDIWHoMCfKy6nsj74ZUau9wwo\nWqZ5ITR7C+xlU7H2r7WnmAyrwsV2tvYPHe906t0T3WNfm/HX8lxf6RtXJ48vP0jCijOj2NKNITx8\n69NP5v/bcSpaLJHb1XueBco2eJQWE0Ij5AveVv/ywatgLeEXcMYrvqWQ5ChS/Pv0Uzyb+vpSRaN2\nSorl/fs3GEFf6UIh/t67BAugs636aBHA/yDsWxj3Zw/pY8NzuYsGzrhGiyvDkh8S/DYHHSbHbN3+\n9HIHR81E1QyTPrEfhYYf1ryNEGHJ0LEQ628EW8u/DBsvHJMd6MAOxJ9BdETETxbycIWg6XVNKNfs\nCEDurOHNQ+D7ILMkuWYITYHa5THRDD6tcsjHQgHvdwZvdL1gQKigeSQm+3cwIFnca6VYu5MAxQm5\nNVH7vpWu2PGAhl6hY+hw6Bwweqmlw2QfJ6xXyi446Enwmo5n+5jT1jqrc+SfmkxKW1Cb5A0pltGx\naCfg0F5l2QIatNViQqeYBSigLe0p0Agsk6hrV+pKmQmORM1U/WB0ajRkRskXkhVVS7QJ3lYt/Ciw\n10m/Pn+N27SkjoGDvm+f4FropvO+EMGlu6yoVKH8zx6cEmFDrQbrmAvVHld2J5cOhWkmFbDwL7na\nkWZFR3vOb9M8om1VbT/OoV8sMFu5W1PhyoZJR09bEg0IODYkI4RfL/bLdZYDWlGhfCzgKq92VoDl\n/R0WPPeeOLY9FIfdrRRFwLCRJW8IyfHJqVHmtfih7483jqALG6BIz8+6OI1hBnxMV0mGMTpJp4cT\nqXYCVO7d6nbCfyuEMqHb2UXXJq3JIEVM7H0qA4DSYc98S5A2myVzbouUaiaC8OxGIqV1OIydP5CB\nGGb0w7NxulVnrW5N9IPXREbNBxEXXyvlyaLQydBFFGwa/68fMLZO6m69es3Hu4NQhVMwGJ2qdvft\nl89UDpOZQlox/Kbtik6/ch4WPe2xKI0AYDEFJCJeOHptqUJSmafDy56wYkeTVDFseu2zTTp8+9li\nF5+y9TrcE3A1Yni/s+a8+v4CA4YtAUPpCwJq9kfk56xoIWQMA2i8scL6sVkKUv6W8n6bRDaWxi7H\nU6yk8L7AFqAZdogxvvb8nZfzWhg0wcqw4nN62NgQwQKxH30tLA6/1XenodIZ/+xWOXohR3+8bda9\nv/cVtm2iCr48zAyCBpiMQhomcEOMHhdGMekt9ki+Grsl/loYh1MeJ8aGJJEZLfWblxcmsRAfs0bz\nANA3euSXmB/LBRpP2BPQoOTCT2UKx5YFZzLx7U3TM8Rx5lnGFYFgf5XYOmHeTYLTEWWBskBd8KRT\nMRyt7QP4xITTNR2JLp02AYUKOR0krZAAiOU/yiUzEiE+f3OxPbSX40hvI+qJ/wZrQYJRc/PurYH8\nw5y++e2KLZQSHJrz7xuXGniNfdXCs/vjb+78eT1pH34JB1ypN5yRmNsMn7Ktkp61k11hrMe2je+n\neBbbPcG8JzZ2XxhTTbQM0XJEXSTaUT+sd8EjKJDFqE7VHA2RAGkw+l5r3hdXFT7ryDB66YNrwh9I\nXFcAs9ACpb0QxApSnBBTJRuDWDkxP3Zt3mO77B6UBg6L2tRQ1yCMppIJGOA+nsgfIjqOI8EzUuMq\nzu5eE22GOkJ0JrZiPe3ZuLRppEpkf89xvsMjyA+bphodVidAlj2ZApExw/FjAIgWcU67vLABDJAj\neteOsn5F+PqLqhpuFTBV9/gh9QiwmVr+l44NsQ2Urz5gUvlqe8eFaHUxvmlCBO3x4Ijr46qFSm/W\nBusYOQ4s+jo2dGJanYYDllgxlvj6yQ33HswWDsZUwYOqGpXxv38RJ+PZ8PhG5GyKCsUW3rKdIVuj\nMn/l+o7RmwyMQxqhPzUGgnt+2aCw9MdHaLmRII0klpxEG5/A08B9t1TtMhJQxT8N6dHZu0/HLUqA\n6VgjYBNPedZug1HmWv+R2ygD3O8lPUInIMqsD7FO1Rte+lDM83csMUj3HGkcDTzv1NAvd+peNSRz\nunMsE/avDLj4Eu83jCB8I8hZjpS4EBgnl5EMQkauNMq6bTKPC+33CaEc8Xnq6bAo7kgljbsCcmbz\ndFHIR/qba7B3FJrIVd7Lnjcqt6AemLxzm3eEBxi1v4S071MZpNs+4JXnXW6hYPh5yEeBZtjRTTp2\nQFrv1icqc7sjJNh0kiqo6onjzR6S2eX56vAhfBN6u3ZtsQH2CwpVy7dTZoFv3SupJd8YWNrSvhUs\npDP8+C21LkStwP4nYI6UHLJPR4/q2AEfU0om5HcIFTnLdEanT6n1Mde31KPffd/HpIGN8aWMjqPN\nedfeyqUYB7J+UkuOwdtr/nnViSLTVv3UBKSCtYyQF5tJY7+QJaQtm4VtOzcFgGGFNenfBURIGptv\nnwKytAwHS1YKoUgi5geP7LNXDf4vOuaW5ITaQsX0Vq3BQUa8LYgnDXD2xONH/wGmv3EoVZq1G95V\nzQ0zVQjDfYAcb4ziRnb87t38/90s2ybDHVc+aKS6vPO4x2mi1UejvH7Dof7ypzRmBsOVcfwmXwsk\nZ/Bbx0MHKJZx/Zv5o69kjccwGjCH2kNovh8OwIcRUYOl1zyao7G2F+ub6VIXrVWCKzxuVFW7ZIvK\nbtqh5B8/NFhWm+h9VGdsj8MzqAP2CggAfH6nmO9Ck+tT46jkhDFoWz4zuDToxUN7QImC5qbqFA2T\nBKM3JhDORhktAzJpGW+Knc6pjyPFo/tIBPIX12fi69q2aL10pw55syeANa6CmDoY1v8MBwe2tMwr\nKeEForGgmx3zgWAhjli5x2kK/uv6e2Cj6FrM/zDvwGXYpGmnpV7MeJ9kzDp/Ubb06n/PgMIm6i4M\nZJxIPuoYOBOsFNVUPwrpB2LOUW9m1bJhV1bZQkk2BikEz3FK7jHkywSCK87mkQj8m9ZScVGz8kYb\nn0qFrm/99+8lKfTAprE5123jLrhzbQP2QzL+n2YkXcfGCvX2IANvPs/sKxxsESPN+p8Jf9DYweHI\ntb/XwXTByf3dAbzCpEmkfW4WAVs2B36rAl/ZItEA//pV+0Pii1cV6xhCUtpb05AXxqIvT5M0fmAR\nBU+6S5Xv9IVfogmmtNSLI/P0V9yoomAXJbQ9wrGME3+CCi9/YZ+/hpPEy/1XfB2KcKsVTHlgMCjT\nJqZ2uE4hZbManTFbdm6TxPI7dROs/xaw0AQGFXGppK6YFW6cJcFm2tUrs6Qcu4ury70c1F2vNbBt\nM1xcJgrjfqmS8WfSa4jGA36usmLKcXKXP7FhA7KOodqjlt4ebFDH5cXL/6Pcnw2Jyw3Ta/yHXax1\nGBYWWff+WpotjTpmD8Gv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LVHGft+RVjB3IlStIqEE5T+V4VUOi/VvHUOEb838q8FSEO2g\ncTKF0Z+DAjg7p0Tem90IYuW7tOcfCQlAsbJ6o46eNl1SPOTkK7FdL0xF/8EEon2ANRvGIqzdyNdp\nxHL8SvoUrEmir4eXXuci2eQ0Qu3NJaNAWQhQ9E29kr66hyCr6erc9TvEs/e5XpqBNpLLpkT+0iSd\nnmiYKlCNWNUa//tGJrqGtDIRIKqk0kLII5nk9SawAQFJ1XpKm3a4lPKvqHKbEgTqKkABel7xPFFY\n3bvk9KwV/KlVQ5Qs215UjtON6jQtv10ouv23KaVcl1J2LYi86Yua2Ol2UJuJyi0Df87vg7l6h7HH\nC3PEx6qss6HWcnx3nigguw7o8F4DRok+DzizAo5Ixw+K/w7ja/cayi7z4CsWJNd3asw+yjZ0T1lZ\nCPJ+mL0sJWn3fzV4GrF0tCeGgBZjZkgheSXGxyOqYJuIGgYeLAT6hjgTsTjLUfjWaxCTab/glER1\nIF8f+SVmeMcn2q45VPKdkkGb4w6DjSkZW2uEqMIcFhEYQoJ4I4TXU5RUMQXur1Nhz+xx45nao9ue\ntl0ggZ5vfyoo2If1CUWvk1X8IsErSwkQYbj0qbDwC228jnxvGj+8C+mEa86o00Ruqo0UNgzK0rIH\nm5ZaHbzd8sTZAEFN/hUUZXoFHsxos2lhNYprexl0MY58AyvbmYwCwPcM3/Xd9RAXY2bEJr+NYqrA\ngatWdhNaCN8JTn6fSVft259MFukbxPHLa7F4rWRN7rE502eX7wOTl+NhIgRr0I87M9bJlcIIOq4g\nxdz4dvc/1oiXoeaNXnG25wxWlfm3z25i6XgoZKaLeu/rs1sNn8EJuMJ1Vp9AvtIAKyUHTCjf0Acv\nOHLEhewXJ4C0MlYp9G1G6w+Khexm08oiPh3nowT55ShfyOwdmps4YOQSIQQ1toHLKaJ+A6Og6SAz\nHWzO3JDyjq6jNADkpOM12jQpv8Leu4VTfuPVyLvJxvvjnEp3mDfLgrjvWCZOZpmOJyWsufhYoo2t\nLAs/wYiUTwNxObKF5XI4u/3IicGOzI8jRsOoUJZNAuTYkzEJ5XBuAbSLnS9nAkQGr6ErZLmxckpJ\n3O1ajpe5if+tkpSPXDFsF76MAxa+/YwEzpSBwlFQI82ZWsDrIxZzmQ3GFtvQ6vS4MD8kicj3qSGg\nA0+elVkfQm9Yp5sLh6WLhucYZvUqKAG/k15fSI7eZPXcVzRaE3GPGtRegHkSqpZrlRf4AbDveQot\nNx1bo28NsLXzSN+TuRRShRs0ABV2iq8NGZEx7YMaNfPztjJcKmeQL0E76bsN63e/oAmrvwVJysl6\nuPy+6mXwVEpw8tiFFk8BBbsP1j2J6+/laSTN0FCoptAkMUgk7d75ADOnXf7dwI2bep3LH7TYvUWr\n4AJeZUjsL/+nXY48A8jQGWcVJgTvaORE02PMO+QBl71wLP0R+iPzLns8KR+JwV1J18vfkG/1lu5q\nUxkB3Yuey8kFabv/IrYQZSGkb5cVTcVRXnRK97eWBD4gcVo0tc4iqjaeHpl9f/9YYzyokCxn/jpR\niVAuUP6XQgkoLJnrwds/rbZEvmK1OvTi04uXQTkm2oCR00+912TeuLq7DFGoxd3avIDTYwapDdy0\nf2LRsRy0W+eQzh2STvYNYocQE2FF8TJWL100h9R8DHh0Tv3emBC/2iXQdsPXzp9rGH6cMqMZCZHU\n27l8X0yfiv0Jj8jBxgw6WOIh84abtjLYCq0u6f4rUHiGZI78HDXKuC4/7S89omqR/B3YIZIH4zpz\n85jGu4Thj5u25M1qr34lZ1L3RFzKxKHNHeGi2Y8nTWwaRZf8O+mKvIPAqJSORS7mG3nZYH/RarGK\nJ3ZZhn41hR95CHA9M9ab1QlwrIfRu98ahehej5Ca5Fa58d/JY/OLIMrMtm6y5StSmVfHUcOjrUFf\nVavopiFXya3Rb1c024Sal/dToXEOycsnO7GSwxrgcDxd2kOGvL55dtfJZ1ZKfU2NIrQuD4UXTYfp\nLAXQMPaC1lRV9QetZjfP74S2gm07dhLTaqM8EEfqGbwp1LeZ8R30lTKjAC1Nv8Qxawh0+FFblQGv\nGpqcsqLNUEfvQyOHuXHidDYJd1on+t0CGf3Cnfte8aOZllnaUfFZ2igqh56k8G5UCxx8U97uBYk3\n2nxwsFZSMSFa9Xk3I8sffVT7i7qBILdgqW6Knxr8BP2RsCFNc2dotvO7FfPbfMd1Md93lP9CmHYz\nYDw8lEz1BaYJMjUrTjs0B5Ea/Rb+X8pnFmzSZKRgq/ErzyiMCRMKr7igKIIHLFGnltXXJsNxq4Om\nTw6cE/E3fGmEhOvS4pw20ofBeS5igW7GVjGecx4dhy0FWQdZDpzylblRWgI3MIVrWZUa9i/cO6Jx\ndbpYXZQOwZQWK/NtLYa5+hjVEV5FBFx+nWqBXcJBg9c99cxOw7N2FvkeszFtT5t2NIDdJqNztL2R\nku8eUqksk9mcDoxnEupyatUnvI1ouz6f4OSyG3npdRyrCnObrYa3FJmq4a1b+6fh6gAjufne2b19\nro5vkT9TRoL3UtSUZfd4G68KMK8V9pSBR9e008rbTLRqbi4S26KB1MOJi/KlqiCa+8U5IGhmfupG\nyvTbI1NWIzQGXPqDI9fsYfLsz+Gkid4PKfWEPbZewpKUyw94znNQ1Ltc/v2C20ezpu3jHeTMvwmQ\nVhemq232VGeQ9wOyqKd17VKzk5WbZA1BzORYR1JgglUZwOg4rlQnQnBqAicWmxrbf7ecAEEDWZm/\n6jgUDADnEiUDhLsTJkM+JvbTKFXx7dQlZt2lD+1ZgT03iu9MfM4MXJscBep60wtbk+zhBoxVDaqj\noWxMBrCJmIgYu1hN5WMxVgGrXO8QnE1B//El5z/cTXXe3lQkfRKUxDFRAbRpDj1ycrIGIOb7cIsF\nYVu1LVrmgXdij8OjAT/L/CixE0aspdrtcuneIq8T2Y8veZNbsyF01KWbPvO/+Mp1o4AC127If098\nyELBFMPVHifbNn7c2UEY91U4myZJ+xXko/v2VHEk/9ndIZ2IQjpLY2UTvlXhH7jbmuOvhesKmgHw\nlNVitMh5+uT5/zdGZvRU4TREpMZvNq1lS1yrHEU11EBG2qNC1rXt6Znbvopg+uiUKeahihi8K2IM\nln3hL2XkWnLFux2SvXVCwb1IPHxoCWDXVfX4WIMvqhDlKWuVRhyxznNdJ8vS+L4BY6k+mFBRSJyC\nWmLnAYYNNNgo3tLJDuPHWhZwwMjlYlmvXndp+bI1E6EdcBZVCtNzIVHTspUM8tVEP3BIZLdrs3dB\npSS1xmqqeUlvTpYhlbbbcw8BuW2NV+bSxN4AqnzbjbkvDTAYnlOFrfA/+mG03GCIJZQPceLlLaKm\n609IPVuBUFH5ZvqdtxcVql2T0DHtrSSKrhyeeCPQUcS6ktMYxftW1QNjFRJePGwycvQRB5S2D2UM\n0cql58QJg5doxTyxJby9jAUVccHPv1RAXjNqM5Q6Bo9AWWRWOF7iK/ObYhyZsMkp9+0lyhGvtV4o\nIjTJIzAZcMFFEljr6Pa8VSm3YOcl/m3OxAfNf+ikjyd7p1erBy3g3B91gHvygWJTK24FhAL4N8VP\ngDd3Awpo2vEaQahVSt0YpH8yQgMV2C5XI05x+awOVbPoiluihtHOkXdyw3OmWwJnaaiWES2ZrKhF\nWw5r0V0gd64oHwoC5bNh1Y3F2KDs7UbCTSs/gk4DB/UhkYaMauvEm0VByh0tjUkSODop6FJNEgyB\nupdR5hAkEFZwzXBvpaxOUaJbua2+WpQzff4SqFf1s/va5litZxXvok54p7Ggx97Sb4roR/mBJsvP\ndbzQG8YH4FRxEbpK/IHf3bkPop3m7Dw4gA0ndV4GEoVzgVY59xlFLe9kd2OE5reDzDQIbLixKNaT\nRNUKRe1KJJEzYFRpDLNAlqrkPidsS3Fa37prlCMgoVIKOzxXGvaRZu+sjXpWGx41bhs2tXsR3ojk\nytr4zv9uabQMrBzHYt5sriiIPWM5ReY8mp2ffC7crR7Ob9O05giE4P/FA9p3VYUhR3tOheQh/uiW\nZ6o2LgdTQTs1E0mFyEKdbuoUE1ouq7uzORH997u2Xd/DrDR9fDKeljl+tDXS97WhtCfbdpNym++m\n/sYFO0Usre0uN7gK7QS9FnPBbEwaeukdTh4bnERbIKV43wIM8pHcUyIGg3EMp72c75zdM8RPudf6\nR6E5lIKENdCiwadiZNll4UddHnSiD1pePEw0EiEmkwfcBu1urU4U3soi1u6Iol3bvSBNlOGRRpAE\nIzNo4gD69BsGDuJcGXoyn1pb63RD9jz1zSG1neDpHIRNsyJUtUOB4w7JMni+/nGlZtOEHe9q42oe\n74XiQflR4JpaocVjcfwJFoPT5NWlfdBMgzEjztcK9EBPf0zYdDPrErULy9WzAUx4kGbjiBZ2YOVO\nVu4P+tuNCXrsqNP0w596snS8udKgHm46XY2Snwgzn+nIXpIyUJ84Rteko6aHWH1NjUGL//CSmImz\nDh8oDws7H9dSki6SLbws82i7Jsy6hshlyOSVyF11v5WgkESQz7m/qpuukiTrPBFgylZOErQY76cD\nAtoN5h5gtK1mNB99D7AUy+RVBJz6hUtJ19o0KOdhglturaAHIU7qh5bc26ly3dOZ62qzBVLFrk4y\ni1PPgVDwJrM4JJ2hyHIEAVLkohfSv18E4Dba0ghd2+nrjdX5jta5Xsf5VdlfKcv7fLFUgEujMrKF\nFqpH6jTlYtUEEi4AgwdUhJgdu1AiQJM3G+QSkVlaKGTi5PtCY3o6i9kcsXLBuJqhzmtV/au8+UXX\nsxWEh4BBAzrrHTt7Ad/n8k5TKSSnlJjxgc9ufAr89oKLhg/hmQjaK+o9hKZgeR1nt5CO6m9VE8g0\nytGi12FHUj/xUOrdW2vxxVgpsmp2FsVtdGKOnZQTl5S2biGEJfcuVc4mVi76l8CWW5TE9yEBPUk6\n4ByQwCNoT6zAsqtTVD38oOZUKA1tk8YdanjxV9OMzaBl0IoIOFF1aqf/WYygjdd3p803rqdEBFMj\nA9+qKFIeC7j5vq18OMauIPSP7/gCS4Fs7ygerTDYsfjTCRjiC4qkjDuGk107p/t0bQD9/n/FPyai\nB+WL0DxnEKGOkMv+O0fTjuBGRR99vG+HiHgdTOeDzT0r51M4+gl5V05dfwrExUIzMkOt7hGazTbE\ndgF+RFVa3IWzu7NZ4g3WgD3+3k5DfM3EFbBK0LAVTqEOgmypSlP2+8zMb2cyoD5cPAsjtB/pXYCF\nkzgvwfjNbr834l6hnWgqNjYbJ9+2Rq2p60QUDrLnciHGPDY83Ha90KfkP1i48VP32goiBsqCjFZr\nQrzxC7+1VKBczxRjMVq/eoPm6D5jYEvQpFMNnN4Shee6oQrtGIv6M3BXnTydJikq5MbruaZ2u2b4\nezV1/MOhTE6bZnEaeix4gIVps9e5QMjubN2LMQUJxXw7TmDvxUgVtd2Pggko2qdYEUJHpKJjU5aW\ngdHJjRwGcgK6b0mmop5I+w/9xH3DtvW+vX5kkGe/X+9ykqXdrHMJE4oUaHI/00zg7z6VcfsQ9viL\nreyUB+6nnv37V00vjI6qyFUP9guzd3on8+ayV+NnzuY7q96pebo3eS5Xub2r2CJX/D9aJxyLOrvN\noV0smuTBcbb2XkWKmVYovYa1cNj//29EH0NAteQcAqA1ljBE517fN+qjrOQdVvr+Yr91bNeiDrvB\nId/tWJ4Zp7mGrqhGBiPyaOcWdKDJZZZod+Une5lr+iHdKaq57N8TdGrlDjJSUG7BMGe8jF3ob4Ni\nD6DoxqWtczl8HZc8eaJMkLNkS/OZDlo2oCpo2HjAZnkXdd01jw4OIVW7OqQ4A6yFCw5T88ctMFej\nq7mox1GuvIxtpg7+vxTpLZcODlwJDyoXaoTCs3Jh7FvKdtHvGyO6lWJ3oFLWWKo/PwetPcKmqIj9\ntYsDqp2lW6LJAjTW4gMczwiVuzMpsRGOz+55KUSmlUucyvj03Wry9YR02tmExJrNPYTs306XZJlo\nhHUKQKTC0IBkCJ1K/eocRmPzsPCUARH5c9n9dblhijsKfElMkD3P3+XMNFKbPhJELkuZg7DXXubN\n6d9YvW4a7PIogRxfvrcLynFDGJuOA9h1/54xc1I7bfLGfwMK8lJBNsHcmX5yxiEleemHtZ9KkchK\nfKmF6FGzEOdzNwQGd3NnbkQgYyi/QIJwRa35pINk9MABGCwO+WbILnDSAjmSuMyWaPQyXj30OE2i\nAcXug9jJMOuiRWpz24wHKctWS07CM6pIugMeCeOHmWTllJq57CBUarfwIJGm6CBqD4tQl7QZaKJ5\nY+jG5N8Ft1s1GkpJxtb75RkgPwDr5HRIiIzf6AKG44s2ZZjAxM8kv4GF23AsaYmZe7R5pxnFFZc+\nLooKLvo1WWc20ph2tXmGKWWyJND7+/GvttJ8oF09P5KZlGfTn8wYv3ScvqeeYT02CXX7ctYZcTXv\n387fBp+PfMZ+qu6FoSr/BylMsg4XgrZdCDPrtv+4RP6GOwJ5DfQZHKD5R7Kv2r8LBOn1xDas2cCk\nHmVHaRGbj5FTagtUQZRRKd6WUJwkAjVP2TWL4uY3jAm21PqEd3xDhl4E5y36rbyax8sN71ySQC4H\naEciatFuZhxM2kAEyHzfMLG1WtMSVwH0BHr12vopjA9OLaczMld3mKw09t2a5SQ4Mj26CtEifksN\nwFRbMMEuqwAQAOKvqEdpDxDCnBS8FyTKw5w83bxm2uWnFjg2YGfRYllB0n0BiVLAxD6XBpMhEBf8\na02o1+i6kFakFKUQRIo2nokEBdBEn3iACb16YOjxWMTsEJMf0dqn08EbFGHGPxuPUZMtle55wtpY\noGi3tXLFFkKLfKIzQYbdt7VmxBq2gn1c5P1ZCg1XBxtBArToGZPJ5HeDJh99dAW0eFY7q+AVreTg\ng1wUe5X7HQ6O+ddgVHwhUDyMdkmxi9JDRTo2R/MT6oGUSeQ44HDnaeZZd3z62tvILqHhtXJby1uR\nqYtFZTLW1bqh1/gRnkWoQ2aQ4idIezQTz+S1qHJx2mpUimuQHhStzOJpSxVR6rxbBuuyNIIuRuwH\na/Wgi4xcPX9hxwF7gXgbsDe4NkATNeSOTmFdtf4tZMxEwYKW+UFO+mF6k3Xpj3L6XtDGDE0LzYn/\njQDen405SrEM7hwYN2UlYE4JoEBxV58eH52ERiIK5mdgTXo9kmkK8tzTlnQ2AfYXI/XXAjBMS5ne\nXZoCXxgv7pTWJrhXX1yZRz51lBe2e/izbGnPFAYEhyIJxVkJlvnrPg6kyVTSYRC5xLjokoyiTcyU\neu0iPSGGE2AXDyoXxAXZLc05hbiHx1vnd1O4u2h9hq8A0rOubFJfR8EGaAbt6NzL1EbwN6+RkejL\nUg+WzdUCvjQRT83cIEniuiiHvAVxPfD0YF2hB/h6odWlU41A1gukTVNdRDu67GW+cEDUVbCfJhA1\nx8vlHcAVAhxQYLjASXxXCVzcHm2ZlINSJNC0RGqjKzLrKxadp6KT4F0ngc9bfJDtSg2YIVyLPwMU\nd+/j7RdhKoc91P0YKgK4Vxne0qhgEmwpmWMsy/HmkKohCwmVMHqTMYBJX9OA2KCfHbQGdmnkarW1\n7Rsa9i/OjW6qk2b9wTnrDxxlg6EIlQD69u0MgJ1NztvFeXT9Kk9n4WKEE+W2Lpre1na77z3U7TfS\n3lwlNaw11xbrxfOdC7pfaNOIGI6cbA7GAazRIA7Pam69Tesiqzmitn2WUw5y/qB01L0Ua5GkmmYI\nQYTsCGc3Xr8FoQcNjKK/Ju8hjok5ybRKHkTp+i9PvxnuwfkrCKP8Hp+QhoWPrx9zI7mLIanXNYxp\nO8hAJKFQFkZEZg/RkNSiy1lT8P0YA/pdOG2nWBAFC9OwR3BeoasG1yPkZfesJX9v5J8lPUffPYWU\nwjifxN/t6FVh12r6Vfx2AraA0yVW+GY6P+rdOVfT0xgLGR32c+IZ6tUGHk1XQOH8kU1YUcmuDAGi\nSLeslrIaNjxwPNHeYXArXlfKG79UUG7baXaBxn5CNAkDHTw64Okzh/7xAgIhgB6a3zyvU8LECAG/\nwWayYCLcSGamtZOQRQ/CwbIvARDzYArbJMAKb2lMvpzL/yHvhS3W3Mx5toua8ukrn1TDEK0ggOS0\ny6U+qP4FDGTR46XkvYOi6ZSs3Ft1tkM3gyauhdn+xhdq4XKANfVlBpQ0VJa0hNx6PnJGzU8rNzyj\nA/Z9gXj68JuZgVojGgM6oDu3x0pv6VWF3WQVN3HInudk+budBFz4RtfFXCDt/GWQLrbMzXPoDaQw\ni8Nq3qlKaqP6LpPrw8iZ5Au6hi4AlOBvjbrkrTzT8JCEAX40UMsQCe9EYt/tMUHElgsW4yUlEa1G\ntmNytS2Ic28+8YDXjy2f1QLBdTqWFO/iLU/CX1zOyz3aVnJv2vzPtUxRxlrNhmjUcmKArhzT/fqD\nmFDQQ9y9WFtrFSXxONs1MH37mwRYlBBfwoByMoXRZX8cg5LJHHsaZQjwzS/0wyu5dKWccdafDiF9\nxrob/JNp96RMu9lmBtMG8R4mn9LscXETy0O9KZAxzWVDK+7OXk7uC7wj7FNbjrvas1VSxRmZuaoa\n24kPfcyFeYgoyuEh2i90Otk+W26gBDu/mrlx540MY3UHvGJwfh2mbrXDFoUyj/beIOX53COAP51j\nUKb6st2qVnnJPo7cnGNCeKqJGtqh/NdA5vyG8/YtZVN46e5ufIBmLU3sZvOsfkXWygp5ht0VpeH/\n/xX7433HCbrbQsKIhdEkaw4yu+L39D6StBNZvejvSHyHXp3OAjl4OoCA/DQhTl2765r+Ke07f3qL\nkR8+QqEX5BVQpNt3m0tjRr3ZNUZmfckimRHYVBOMz7J2q2lGgQzEb7ebj3kFQC+T2g6A5IflUTOm\nvWVdNKB/XEowxIESa2zDXQ2EiYczxBv0y9threGHBjnWkmf4qFSgYjQGhvC9b9W6I2JbkC2O84LM\nHt2HetTt3vPrXFRZYYIwtX3D1GHPKKSt7HG+ckHjLUF9PXoxmiDsuspz+hpBgqS4Pbw6V0xYMdPJ\nInAZJ39358vK8pSYzBL3CnXhEGrx16rM3ALifwxhbde69bHIO7ib+XAmc4C4njnVi/N2qE5JIfbM\nRm1bOZHT7GngP+AdLUMc1shJhRJ2krYqTWqevNHpJKsq0Sa6TLnk62iqj0/L0A1a+dvMf60Y7pUd\nPIVc6WP/gN0Y+/Ac25IpMoSsK9lmi1lBH7ZYiz4JDezOAxO998ZRvpRdXOKLZVnORRezHdZJZfm3\n+wclIMccc8MGWwclIWj4KLEprNU0oPBRcgFU7ghfU1iphvLGQ9G37TUNfmU4U5Eyis4X7yULjEWU\n4r46spVKjxkvkLxKCOg5bFPm6wqrGq0l3gZQmgMGdFN51073Sj1BI3+/vIvDNCAR9p5IJFVkI59x\nWjJRkXvXP/ZH1RkbmAk+B5+nQJ9fvN4eh6eJDGJo4o/jeVSRI1wm/XUqmuVLl5ene9WKoujTyB4X\ncB+5d/Ta4aKCkYKpFjZXjQlQ6l1du8+QFTaue8hFUbQ0gVlOOj+cSWxRJlpZO99Rj6MLVum9qYXJ\nkcpsBn0P5x4n5nVW9MZdPdMsnsO7Fs1gD/2PbOG6sqn2i3RD+2VY59LGelNcpLYoZmeWt2bDl6r1\neyxOeqnJ/GrGfE2lbDWuHqY+BO8/asxYXtwb47flXWuzF/2RYvQHtwf+QA7I7GNF26NziGUTXBPV\nqQ0d9LcQSjzaGIrcfW7PZtoMs+d3LgT0wmddfXO/Xz1japen+JdVuNI0aKSA3uxeDM5VU5jFJEhC\nR4jL5/tD4xwNHO4bK+0SCKb9cWk4hUtxwTP01Rdj0jxrdKzjMcVUD47ah/SpkqXXXsOM90qjPxEn\niEyi8dkBXeofvcOxJ78pmFpFOuLTfgaG6qJq+348QvxFQSrAcwNJoWnbguJvyPtO/wduSxVZYiwf\nbI8nU+JaeddFu1P/wK2MHmgmDxNYds4CKOli2SoSECA5zlBbqPhAjEOUG40seQB/R+/jYaAQ9Z84\nJ+Qw9EHYiuXWsupqPfN+spgogPT/aa9cQs38WGP3DfcwcysGSLHvOrpIeUcniQOAgTpGJn+Sm8zt\nALB7w+jD6QFzwqYq3a8O8AfWoOzU20SomU8HfkETeYkbhr5RI0O0OPrDZv745wSWOUJgB09Ne894\nzIXzkA1MfZV2I8//BAkU6lzVqjLhDH5rf7oR4rqfHb7us8aCHD0S9ab97l88ovHgWZdt2bB4snt8\nVMzxLhITlT+SA2mEJmlTIjzytLO7Xn+CsKKJP4GQnc4M77heuwWlLwI9/IGe332jBCw1Q2ne3vYX\n9bt7uaM5Eh6ZkIRP2DoGps69eYoeGjkGmNwHuL6ChhHkqLQlpEuxDEHsqNEVQ/F1vGRcy5Y8E775\n3aItkNz5Cb0WETMXZ3sHA+PEdCQsk82EIBLwjnwHgnpfOVp/9tZ6/zxffdrqGq94Pq3wKi2A5nLn\nOJ3LfRIzPuS44mMVOr917NDkag5m/hkbOE8LrIfLdugL3FvMkCCqyQ/JahTQCLum1yf0zHWidTFY\n1L5YIrB6IAbT/o6ca3JAaf720Rzuo8eL0OiI6qOXcvJxuxKH9CCTffT8tVYFP50Vy7Z4NgGlJ0rd\n/ln0Fsf4fWuJvB7uLmMH3p/A/0dsFZPc5u1eGH+Jk2vFIFK0PIt9R8ngSbph3gfziUel6KlmNBfP\nTkQwV+4KwbZhK0Agv9sRGQgKwwkEqBkQzHbRjAitmbYXNbij5OqnngaX5c3Z9APFoXTCw55Zzhfc\nAlj9NTpp+Dz2Pl565OrUhxEHXRaGZ7+Q9UAxjHXA3iRgDmYLmLKQ+tusMHweU3FCO/57rqAYKAQk\n19z1c+hyQw8C2Dvu1rO/Qg9WiWHgZ2xmKEcbkCcs4Ic7aLC8ag+NOCaeU/Oy02Qg50S0+Gqdvz03\n/vtpiPmP5HqLj0FZRUJ9/cNED0pLqbzQhj8/T910mon8pAcS7ABsAVHqJ9w9eKfE2XVOJheTsCft\n6IzeLJg59wSJ13wIXdCz8r7HBpOZAs4/jRKTuboDxDqbwcZfqN7LQ4W4STORpdj4jLkpnh6gQ2MB\n7g7uC6jlPHLewuBoSCN6UZgSW+No/8cZFFu2YyCc7EYTun7eVg4QpWpeZQOxEQ66OIPMJB/HBQ2s\n0LxnlLf0P7SQ70SX91L1Pc74FZtpm3qVykiXUh7/x0jPvld85L+WpcGnC/emoBMeFpAH7U+jrM0u\nw6fTu53YtBy7Wu1nwDzZtJe6OBBpeAtPUdrlmbJlJel9x2WxoIMJ2mbLdHlhKyet7EwOxcn5q81F\nP6wtIelPfJ2c7ihuHZHFSOiNpCZE62QVXKdOZUEZmdnzjF0/aO/pbA9bnvDJQxVar9rRtCe/abOJ\nwRxwPtxBuJSCAnsD6kfTNo84zlGDjdgiF5govKZy5hIgyl5Aln90D2k/CJzeuxrLphpSvtCh+3k4\nMsc4P1iSmgUzcbT9vSXkHXOVbxRoT5R6voUM8izb6BkhkQpPh7+d+UXGW6Ncb4bBC2GAPwdQOUhO\n7mVMO5Bq/C1ULEDC5XdnkiUxFBAC01im4yjTzoDgaHIeO1ENRpzC3Ghfg7Ce5vrmjLBwPAozITJX\nwo7ljZytW/YS0zF/SCvjS/vSTCzCVR7lGyUIZuKWTlmnjRtg+b2EiqrBUcxTzW1LiL4NVGRn6/Qd\n+5ny2YogaUuWpCkXiyq67IAzb0naIA0gAYOWKTmJNXGr4xWUs4KYNLSBn71jL3X8hiTUhPnJ6rNq\n/tTERhQsZtsjP1Q/3yLl9LX71/51qc5JFiWBmnymJTq0Bxk5l65EIMt//YjyHgAYWvoxdQVJ31Lm\nI2WiI2LCgdUBcw07xwQVNl2RIKE5Q1KgbS5KZcn0H93WIqp42gqJQHyQ3vjjpaHxxbhhUstNhXoB\n6UqdYbjESskDVM5RNFuYYbZa4n48AQ9T1zZk5oSuXa8yXtCg6yBdefcypbgY1mpojJZs8O7pr0gB\nfrcFMxmp8s4+iSfhdEotlbu23LipNRh82RqJEk27K7OtoMnHWlzOs/AteQD/7lw5u9c/wAL96qXQ\nTln3zbjNQx0eVS6d1tzM0fkvlXNxDRrVRdXlshRudi5togW+Y4/bfI5ZN5HQmju+TfKlBuqaG3p2\n/YtZb+Y5Cldg96gyusulspJDzgz57ZivH5duQF6JMmoztmPUIU6YDxWnUKn6lAHmJrBUuomyhbsN\nZlqy2mxIhyfILuxHqgZbD5CyUEiw8Yr0s3SG8Pg1nnPgI+v1jUiUlSZtlB178xuObt28+Jp6jIs4\nT83getoKlgGabxT6rtvnwv6iANZKQ8EOKQIUi0VisBzFfZHq7B52g/Qqxi3lWimvNkl1fQZdWjLG\njETJehrsfQSJsrqBBmbNcHn+fWVVQ3WS47EjY3gxdQl8Gq4IQqO22lKSzmYPtN5At9dgvB46bWuM\nG0yZkm1Mx64kUESn5LRsm2FGHZE9vrhL1YBuYUGoT/IuIXeYwlNXxIZr2vgG+9p6EtgvCjK0+aiB\ndEMFja0MxDxa2hP2TFcd0HWgTDjFr5DBnh4piistRklZbRBbXaI7m5g4f4A+zeaNtEsCaC8EAKfJ\nkFBBrOW6P/Q1agMU6zDx62kpvZTktNFJcAUiveUVs3EJETmXpRLeAOeCzqlGLC6BbVFaRkNKs/dm\nafUW4KFHrhSbhlNLzZ8XR6bNPYeZdXlbx6jp7cQXt0kHqxpabZ9q9QH6S7Gpah1gLJKpLiro6lwS\n1aqEHURINvW8rt1a8q60qSPbk1rzgS7l8sq6afO4vgUCwrMkvxIuC8NZnCEgpZvxXRbTys3CdKev\n1/t4kIPTIys5HX3Oji5iL2g9x63KjT2EOdjZIRL9f3mVCSla/Iu0Ty6mvdc9gUExc3cjkv5IDSKI\nRVGngOkgRY6IEkEtBqaMnLoI4Z/JG8PZ62/3Vu9yJ5khyh4aDSp89b0x9MoWDuEfRQLKYohRMtCt\njmJcOEJfDkrp5LMcYHAt/tTP9t16k7OSIdAY89tlTLYrwlUDKTun9UqXcbeGVjzdKRa7SpLa/H/P\nHU2Smvx1/exJ8vsSj86pThUzmRCsOemjOrfWevqVlcwoeIWdXpXuWNYs39y/7/Fz24LJgUDmVfOp\n6zClIba5Gr2RGH1gEgrUCOS7aI67DaYjc84xiyTrUvT1mufr/FVkHd04Uq/ZLfVASV1KVrj0imxA\n5nsViqEVxVaGf89QOUCOX8Xoh3zq7PFyD/kl48ifAjynWb+7jAcS2nuty1qRhxPrzp39CYgs02Us\noeqgd29/RRkvFGAtLm0+/05Z1m/1RHWdtsMvDrnp0JxlhbZV0iA0mn54cmA1ghZx5sBHMFT7P27X\nHtvC47954nLPbr+/IiVlOUd/0Lr/zVGd3CMoiaYts8okVqGcnmskYTYC4BkTf1C3X3MpDR6IcRFN\neXRtKGz3A0e0nGoK0CyOcWS/dyOhlT0669VFU7NSDYoCInbrOYnAyc/QqTzqvPiQqYxC5ZSTnZDM\neeBglxvxG/usKBUCUfH2TPaT1sfVy7pG92KnxcEXY2BlEGsPKXNeTJIodLZWq+77lOq3AsdlFK2d\nwu/GsEMsOtuYlw2lW01B7TWqAtUFRqkAf6e1PXXPGk7YoBd7J19ASYO7nOnCZ7ELkb9EcTX+WC24\nVq5b3WmjYFKnf0olbd09f1vVZop6jYJNkK0r0YoJyMC9+XI3NVz8pAzp95NdUwThAL3/nU91hVxS\nBwGqV4zRl1gfy0uBUYaMMZnM28igHQTVJXnxOWjfrInpzTKJIIzQA9Hl0bLvdEQT2mAXSATzOukr\n7kNNGNudIjqGQ4Zuk9Oij3TaHA850HxWa+n4/obGN5Ehr3ct9tV7JAlqwHroS78k3ZrgaV+6FrH5\nAsLM2Ig2eAsHt+Ll56XoR9sYQq8Bn1yaXSEKcQyFldMxTbqIoXXMv1GCteD0Boj1q5hdj2pvpiy0\nCPIgMeL5NI5E5/6arekEw09xk+z7E2rDnndRmQ532gtAKjrJpwSI0wGIJNDdpAHCtESF4k2YHmI0\nf7UamcM116xyambqz/AspclbwIVIKgEAmTU7L/IH51ZnwTYlIe6K7WYzelX5JxKuFmpDhDbueMma\nG7lEQKK6/cVOxHTDxcBA91+OxOhCZym6Z6aQEIDhAc3p42+jJe6UjU2VyCuopa/4I0eT3MPCOpdM\nVcBHhT6R1AI6rOHS75WLCZF0cNEmluNZNYu3aVV7ABM6sWRo6rP/s7aEVdt/eTGiecvj+HnD7RSG\n9V44DzAQsVtGrIjh/jNG65nqB25L1swUkwv+hXXuTJfViZNgzqTDE9pT2huaE4cBSrSAziLNaa/3\n+r48G42adqXSUi0tPP5GCn0NpxYC+NezHYC64rInZXKoisqbLDtF8taAS0abQ8lqnwG55V/vUMtd\ndEmToO85Ap4x0MTmOO0f9aK4A4TYqGzLWHXQjBN+HHEfQBo01GCAReTS40wGTDeE0btW8IdZqgl0\neKRu8mvMK/W5RnSxR9dXRd91KLQJ85KZmnLHXK5wtn6Eh/d7jI6bqoreYm3dIMgSMJqv9shI419V\nP1jB2PYBq0ZflBua5TACP5ELKs0KFHc2FDKCF/i1w/AekkuUjHJCINeCd3ZmHJuEPPv6AHi2kQj/\n81HnPLXsGQAwwm9NsaDrOGrGfBeBi4QolIeiaZzpg/QjE6oT8/18z8OlsVq9OvJZvBga7hws/mm+\nl81f4OwfmUyD/hgno44Kc82J+PoMsCPQUhmW57a38PSgS2BAdm5/2zBnaImG7wcSi+XDKHaxoHG9\nu0wkKy7WDqnTIU7YrANquH2jq4QjFjFVo/+maFqhKfHiqd8tZLfrMLYHXK+vlRBw+RizEeKUBwwx\nreAbQbOlUHR7z2peoOPBWTdEfnre05yAT8/DhgJoBELDTqGCQzX6uU4fEWozrn8DKXcuJPrd/ulw\nQDWf0dX1gSTCyvoRzibToPxX+yoUEPOgogB2fRpytvRyS7LqSlrVnjig08njqT/1NhR3c0Kn3GUQ\nUMVcYxfGbaVoCn/3CN4TMfJBKV0REOlk4MkPXcB30wmzRQ/F1uUk1rHzTj1QLEWGHB0KQmo/zneB\noNNe+zIFHBwoEDuFrukoZ3WyfvJEcx+ZdarxbNKxbqUoWSmRJwr9FlpXpdFqfW2dcC6Kw2kMQmqr\n1IOn+c8pMOtpljJsOqbIKhK8DoEGoSqy/K6LiOGVnR+jO2lDMejCjIQdqflk/r3Wjd8vKbs502E6\n0mkjwlyGfGXfSuFAdTn0IR9leXejaRV9TWVeRfN807rJo1K/jvyqQBhuCT6hFawm6gYml4Jq3XBC\nNo/B1U8Q8Eb/7pWqQ2XNsaYhw1emk2PyJxvhV/VAi4nzGmZYnHbC/TBSybaEOkO3Q7gAHtoxYFs2\ne2VtynoUUp390ae1Miv1blvGlViw9v3CxfyZuctoM4uGVZdyzP+0I7eTJi0L/dIAnkVCrudEjRDX\nHCZQ/1wrCX1sB9vVt3WHCfDH9WfYpEBtZrnUn93a4FaS/QVQKteVtBYGIVwm/roTXQ2+NIhQPQqa\nrv/zPxWVWfBdj3uVijExRM6U+nY07b0cSM98mjL5X99CRqJ1BDgJTny/6O9qUgI0YLnx2B7VFyV7\nAmzSSymSuK2qeGXvWa09WMo1SB83yB0NUEa0//97gSxW2I98n4BzFM5/aZ0hjgZU45eR5jpohm93\njKIt/xyng+D4Ljif48EWek0rXD0jbJPHWoZ4i9X5Fpa7DUTAMUm2rW6wJbmbKOeHL+b8zssI22WI\nxo6vi1ArPj8K2w1Hxd9Krsd2Lwjl2pLM3grnomJirSZmNieAJggzSLRXSmPoRSKfh9a9NeasfIqb\nbkuaH8YnNPELP74bNL/PQjpQdRHOSab66je15aWtNz+zY6jWmDrlu8UCwxI+HgI/Jov+49278pMy\nnUpTheCYdUZAxfRbzKU5AEmF5lRU6Pf1uPR9SRMg6YQJhWviWFV2OinXX2jfEwtr1LxfHeJRWv/F\n/56KAdasRstcxZxjC07rIyxMPwMJcJ6K+nrUvaV7Ycya8u3n1g10nfk5YTMS5ed3EEGBqVFeM4CS\nRawazW17n1lrevtbJ3M8CGCk3/ax6PwB8fh8gyBYwdT4Qhe4nnlIavokghlBGOam/GUNJ8ZsuBS6\nNQuxGifo3InmcndgIQmxtUq8GsN2gChXIy1RnDwWFaAMO07WuATZONrjCv2PxkIQfSnXmRhSgDYK\nqmbDW4ojR0D9FD8juOkXb3NtZ5DGQGY+Q6RUR9EboEcQFsOiLnANwYlDgEsEMsed/8FxLg9wwHJc\nNS/IdoxwoEKWdYUy4Ucj/OHLrLO2UWgEpGYF5vcYOd72yI7QuptjgssFF4CK+6aqGLYN3GJD/kCh\nBJ/p3qCkmu596Yd3xjW7ljUrqE0BcgTIYCUb01kqcLTiUVefPsSMIK8OJ4xxzJ8W9rylE/SnHJAp\nO32FfM17lmYX3hyKqOvBESine5Hkdgg7OHRurZJHPa3BavVwueRFnA07L5+aGfogQvkdbFBTpKaf\n9MFH3sFQqlcUuZUXOsY/L1t7LPw2FSVvy9IsdlL9tS6iAdCbdAIA2OzXWh2cvFeEKePlOfSUHLTM\nLZWHQ0YDOo4Nm7bg53VeC0YDIPOF9ijFgY4mhMc3GrF07bIrMB0TUSrbtDU6S/nL70EZ5FYJhAaF\ngmZycTS6DMYG5pt48IzIGJaRCcpVUjXi9O5KGh4+lntg7PdfEXzGcDHpmyrMXxUOlOZqYps1ditm\nPmZjmQeWuE3X/Db4QVZhctkHxsjEv4GpaMM4sDcv48aRTmgjoIbn59TQMnQXf+CGp5JGiEVihiaA\nazcv7z84wKzLfChcQeNmNwxY/uFisSWpGgcZ0EzI1IffCoJpL2ZCdOJ8Q/7L0D6ys3gPUveBshCQ\nDW6L5ocdmusu4unbJ6z8ABjAGUAdJKooc9teATQNnpF/+oXESFJYTgXQX9S1lwXNVWPq4omTnqFO\nOhBuEOSHg0mJWxiefxe/ASSXAjBSK6TOnlMatC8beskoHXf/pwN5dQG2UyI7TWJBNrOCPUvq6pG3\nxJbKu0/EolfC8JLDlllnFfZ73wKKDSju2OlIo/9/kbeucWq3/5JLwMHOELF0tZdsMPR2xRjhUqlv\nYg/ITOkubej5FqURPRv5kH/u2JoqEQJ9WmUIm/Z0amWXl7BVhIFX5rlq0XSYzUxJ1YfjBwKDj+/t\nZZ09TFVq3xlL+UJBFD+LKR6iIlhbBWaz0AtZfI6VA8l9PesA0kqHo+KM1H/gswZImF4tDp/5R20t\naF23YIB7D+R2lIAM5CU1iVpQ9MI/bToGgPDrqkAshGYrnH9g+Gw0g8jC7bAADTzQ9rs5Lkv5LHTc\n/FT+bvVjDjtxErItEi+6qXcBGA0+gclJFvbVK1LycOXGE7LcyLLa34jKvpkh6kduSRk6/oU70WEj\ntF1cdRDtZj0cF2z2qZdGgmEHFUkUWXjRdDigT8oGsuJ3NFYyCGChS3xx6itJnc62Hp7HctqJGRg9\noD+6DbIa0Ey+dbjUOd9Edth8bC/EQpVZ3ltwH2KWkMXS/2tK4ilulzrP+PoYHlxs7ZG89ebnStdk\nvDHGBzV81JBrbsciTNV8y3togsxB3Jrqo59Osg0zDfKuVdWE0yt8RPvCOnjukr60K6UYcwgpxOX4\nMyXA05tCyBe2G/DuJwHpm6CZMBUn7/D8/CFiwiuN1NOlpPKg9RPhLPhKobj+e/AQnq4wOtbPuHGq\nsYBqOg8K8x/iDQaORXf1yvHM3zfQeDhLpqLg8iUFoKtN45Vf06I9IXxWKWhB4I5kbEo3cPlHuF1c\n9GJghc1orfNGi22VCHImoixVN7TTA2IBR1oJsKYN8LUu2eYIpCo3DnhGeExKfRGn6cG64+FRafw2\n6+plSkcazVCMbOeYtTluYfXaSr0fTreTcsimDVSX2dDAccL6OLhmDV67xTVz4sHJu1U7iaWSk+mH\nV6tQH8oULvTWTGuizn3IUFSMoqsCUJX1R5YIVd7jsrqVMIccYhMc8rNUXQMDf0o6pqPN3ggnaJtm\nNK5glbY212NsfGxTP1kc5yXEWZCI2eEs0n99VOR5cwmyFQhHm7I6uRtH980Svz53KAofpwGFozpK\nhefLf2H/xM5cUBDt9s7Cq5T6M2BkJ0Pt/f9RutjAsdy3QOaLDQutDKq+pDqN5xif+83byvH2jN9y\nc4Za7hahnpavRatYxG3Og7t2xZcYT6w3NM0ghjlg4UNu2B1MxhISz4bo/kmpcpT3cuEFUcTgXBuv\nNgIpmtjJLHlQn9HNnTAnRbDy707AlmjoInhXgvkSCtm9mNEUeQG7kOFfKTDz23T3GqCHz4ISANs0\nA+PJKu3PKeUxD9/R+OdqqIvoiSaej4QVh3JHsD9RVzNntE9KdIbv0a+ca64bsD7puw4kP07+52xM\n0eSphOQP5uJYkP6GP+ePfOy3SCkvQjFQUbwKZGMWo/dz3euX7bKgqmZ0xlI7sUYcMG4Am8jll7P6\nkI0gnPOPnfu2uhjaOahO0WP3QUmfzjGm76DmLyGroLN8qOUMh4YMF9wuSdo5lnMw8BdZRdHgb0v4\nDG3YKy7GGUIiosy88jdrbwQQw00+4U79QvYf7PsMmmlewKftIpeKoupioPbdtoSuUbaTYlrakfUA\nanqypd6zT2lIQpBAjiRBOJBPbOaAjPcIZ1FxGlPEvT5riKoIUoJVl5uwZgbdbJA81E2vk0FC7Jo9\nxSfcSrWD1tF9COtku3ir5PeC6EDJ3rz926+7rba174feHKGQLeyfhh+hf3nuAlPU2mbjfYeJ9jUL\nI9JegOD3ISzxtdF3pNdd/QV8mdi0J0htC5eYYhP14jj9PAbSjTcxiLQa5bTJ9xTCaYhtIF5Do1Ab\nNzxCqQgG0JApu5r/cueXvVEaerQ21GqJ2O0oMqR7FiSBUmpWIf+wyCZDgxXXVMNoKTvjh84ERvjP\nDqfjLmwr7Xd4Bpb1p5XE/Oz9RS1hy4mKScVJJhb1/eFV28SgnIok689DGw81LD2dCaG1XLx2Erjx\n6juXsAYlOL/xTnk4Bvqi1VOeW4MsnO67TScqxZrPRWVNKfEXs2DvPFnvx+XfSOezjK3ALfaWTQuh\nV9o/MMYQOig2aqd+M2pFJJmIn9yHvi3WRcQNZO0qvKNvBgr4KgK7Xo6wo7IELDeclgKpG5LwkrCD\nH5an9HmVCveIDDsk3j5FLWnHgXH5wUt17PC9VdLdpj2wsjHYUUkSDvwFeZ/cd6gvPhGc/5Ah60Vq\n6dx98+01sSRsVzArGSib3/fOGuYdhShIHu/6GuYXKA5dbjbX3Vi+BBsVX+LDcvbkKx6kWVCMU7wD\n8RdJ/oa9bPf15IwSD2TKE85kNbV3jcVIBsxT/uMXiIDyYikD1iN1AQvXwjCsj2ggcAajr7S9Zmss\neqYv4OKv8+sLB+osxdLd+OokqHt7muebwC6VsBdmy8oV90eXfuS31vdJ7wlHOMngB+8T1mPRj8EU\nPiTrjj24R/8wjlhcfbijfZYD9pPATUpGlD4SsZeguzeTWaZH4zpGaFqC36AeRbYmD3fE/i8WSTIV\nEZWiA272GoOVSm3ad7p8Bo3ZR6fw6458HENUTnMbMTrVqfWAesBapmD9tOQrb9HRuBQuU46px41K\nQmZZKSwPFNLVSJfFpDq8kM3nyWpywYMqdhQKdWkRCcH1uzopV0TeEuoiXKhaQj7zluZizJo9MHqq\n/dT/8xq/EBg2Pn6SqOd1W1m1XFlR5CDpmID6ESGqDHteFwURRrbWkMFQMfJcJlLqmYFKNd39qAa2\nugGMj/iF+AtBXjnuhpk2p/CwoPqRkLGRzg233k1fV49gGBCGHnzw5R2J98MBByzgblH5fQ4dL84y\n/XfghgkBCFkpMWMsvIDN39BQix6BWLBT0EuKkKkwLb1d72ueyAH5G/hANDCcBelghcn+ZNUosT78\n720C7LEl4onclujr4vJKmIe1DqsayQF0ky6Qe9fvzvviltzZW68KCPeRuuNDSuXpvwiA3lrPban2\n0N4FXDxkLXzd2k0CmEWASAzrxCUNHMCwL4GQvW+22kBVbQdAw7aKiHSxRgcvPx4ZTGkJ4KbpJhms\n2gEAzSuVKr1pdHebPcN11/Dl9ErY+AAMK9DppHThFtZz4qWj0JO8yK+7xnXAhcs0q4cxsIGP6rPx\nNqUC1zHvruH8jQakRQIcNywvHL054iGVqSLWUrNl8+2L0HnJRVu56hSMDkG4R3rN4MFpc64tLdz3\nL9v50Qv7GAKJzmBLuONfMC37tWV+mauuYKY4UYvyAd5zdVqYCja5z4ZNkY2KtjPItJrD9Dqq9O57\nKJkWTcpodP+kvLKrFwGZP2j4rXPwKl795UBpNVqJXZrMTHslixj+KM9sXEOqBLjVmPLP9F2H+zrG\ntoIAYK1pVto65y7BVGEXrZc2FYnDx7fM/Tb1RUD1Te1/a7qNcxhNSnYe6y4o+9Cb/Jp/tuMSToCR\nKcodo9OjLJ0gF9IKhXVJuW44pozQPEHECePPAcK8lo4z/cFN7FTuwnRCpjJ8wqXNnGfIc/2sSXDu\nCITtu++7nZ2mjmo1DjZOZEPgX8+z/Bkyux04g0JaJDqLwP5yaYva0CWWKfAje2PzcCDGiNC/BPkJ\n4kwyWrqvl1OPRhCX2/MKob2t5RUQ7/aAAY4NLT3/Q8FzMVf/Dpt7EtHUy71+k3gRE6qXr1pKlTjs\nCIbsHDJUCnUIsoorJiPR+6fFQoRclsJ/JMi+VvzabhPMc0L8zZIUsPP6JF+OqAfbk0PnWiLnbH4r\nrLbEwCp7azoJ0L3388N2WISYpbQpBm5rGJaPYByQKfahEBxRSO8CPB1FIZSd3a/j/rzSjdXafksj\n6mOyP2hanCyYpKhZObaa2ffpoyEA3MaBoiLoz9eN4WX5f9whWvGbvELTAvywc8zrik0kg1n5vJjO\nhoFY3e5nlM+/SCVSNvkgqo27LpPwv5yllYp3htd4q1xpQosrie4f9N3GcRFF57lNrybXDSD8ADFn\nmSmWcJq+IBCWT1QxL2k/j5bbRlzkamhoF50sK4LQxkSo2++saK32xOgoUkKD362X1ZovvkoEBbxB\nNUJW8O0MG0J5Pr1ga4e3CHfJpFK3Ak8t+NtdleEhU62uomWRn6+xadqjl1pJii/P53MnVIBLNrJ8\n/L+tlGcs82V9kNbV0eG78/0HxTEbToJwinBtWf0q/Up0WEabYoBZFjuL7mCJpSYEDsLUOlLFxK2A\n3xnMJnsixMrmEhmtA2kz/Y+wGgIaYKxgUmdQKh1hOxPbeVuijI9AsyFz09m0yGi+a9nsoFVhe8fb\nIhOT5Lrrxe1ZxqkNF/0GFybEVjvtqvnZabmhjMHf2y5wlp6o5L9C/Uues4Wg/wubVK0+IA2vuX4R\nQ5DdDgpuU6kd1RtGesxIjk6Ef8doNrFoS8ni0fZ/HMzdOvp0EjgYxgN/2XvMGg3mD2tctLYlM/7F\nbM85F7tCZqqhyKMx2Ah6hImleNdHtHIw6Utx2H0u7R6Cxd6M39p836buUn8EuJ1uKxeXlUkb1qYA\n/XIkwRFtBOQ8+63cHxF8NWGOgFCr2zJlmdl5r4+rag3ZFVo73NNH7lIrTpH5oTF8OSMrR56oyr2K\nP10pAzibYu0rP9+7Ub4E+vwGh45FqUkKQLEt6j9Nil2kZQtv8vtjakag8GZ9czGPP3p/Lg1y6IOP\nOdCyMCdfRC9zw1tGlgp5jUX8zXhpn7NiTLydYn47vftbW53DhiE/UqAZeFr2jthjduDMLuyyimDa\nQsN+5BQr5TpE1bDY/IZO/XMWMI0HNPHuK1xXiyqjraBz8OJuOvy3vq0DMAIvQLJcHXjHg2zK7646\nUjrN8D4J4v82MWuBTcdk1GK3He1f+EdU/JQZ9sha2EIUFlb46khEUFGs/+X6Yvo3HCgZslrX5WGb\nrXO+FElpjMi9sg3YS8aQPG0a+knf8NRT23KXORtKIvrBky1dQQoLJewJifLgratcsfP8edef2ygl\nvRdw34+vHdVVtFm7NwWnspLoi5I8HburbbzC3E2MZsw3/HSWBMXei2vxSptCsYTflCHsv853K4Kj\ncKFxUIEwh1Z2b5K8bJe8H3DMT4BwfAGeP5ROM4c7W2DRCZaSrFm1Z/IKogU67Gbsps+LvC7Shh0a\nNRx/JvaLsAVWqW8tDXeUAPb8cAGQn09UYeezuc7FCtUtCwvw1mmHPB5lcAPh/izFb8hOp2JYXfAp\nsOz9gtf++VfIWRjVss1sxox1yyLJwhTfNzz8EDqgQswGkRdVulfSl8xVqvVUSvJOwhmDKlWbQsl7\nj33e/R2adyriiKnz8pCDg/EyzEsJajstNZmoQCJqiLfvhwBkqcgT9VFH0UtKyH/MfHFP1WK1a22h\nG7UlzSK3fMPAk94zuy3XnF73jdplKRYJV4e5F83A50RRCX1PtIwacOwJuy51f38qvUfA9wGEvwXG\ndH6cqalwZjlzZSDtA9K6skLLaqCGMvBPVXWEuJAih8Zx1Gq2I20MAGaQDkAmffnA+8hLVY4YxzY4\nQm+8Ow3BNUPiDEjv4X56/J11zgo/ZrJNjwRL8I7EzO52F8L06cdHKuK/GjT3A3YY5+al9/pqmqLy\nXhusS0Ett6++6pfNJYaKzSSY/9FniDE+UF74Yj8IsCru9W/QjcEv76Yz6s9mCB+gpVKidzr7dFK9\nNgOBm+KdKhil9SEN1z/N6GH5QMmXWZEPcuBRcB0702aHBHg1cV6sY1emtddSWDBbNPDn/dKTFS14\nXbaQsrsY8DNz9Puzm/i5tV2l85W26AvU4TW/d/Ia9oBeRdebo6ReW3XROnRgQdA3Y7dpC8Bx9Q0q\nvXDDL85lixudyhMtqwT/1lTdbtDp5bvyGJDC+coUc+V0fpK/cOVeEIKVz3zMaSEKT4gQ08yBxHsh\ns+BXhjILKMz6sTHwkm4L66Zp9eTssZxjZWanrFhS8OQB7gtxRniHTz/atlJO1W5PaLZsO1jdesWm\nFKbVdBT+7aHbRkv9klOPgQ5gtf0ePUm8J1vjlH+lrYTWfDhyZvmFYnCmWd/k9q3yEx682HXrFtsh\nbHWPGScN/ApIA+sE/FCh67UBVlDl5gyDdqZPyhJZcX21i0hhz6+/zolji9Mnm94Cg9AGaK6EQ4KI\nQJdhuCY1ltHBwTiZh6836qKZwle4w72Ftfkf0s1Bld/c97FbtCyOWoiiB5P0+anD2MHgecfPNWTV\nEnJ1ZNRaA5iOOTjbbwuZh3m1zhbNMwBAfoSp9xqfAXWIyADsGAJxHjskZEp+Gm/DSruuWC30i57e\nZ+5q7/Ls1XrhHyK2GxQIaqv8Q+igsEs4K5PPWafV6PJ9w2/QfrUzb9DIBF/KM3yaYPw4J27Is65P\niVpqwjRptVuvXCTlzdf1VihzauxKx11TvEo85mPvruuGaGHZ6UJz+7BW8OqjCF4XikrbeDF5jqir\n9sHvNDgw/iIlco1uTdNJUH9Op9EnQZr9A7KzGWso2Iju8EzkY4K/TIiCGCsitTJOhWlxnGuWPXGp\n0WoI3SDwN8NguAzemC/M4+abpqIQ6xjID3TgVnpwGqv0SrJRg62HuHE5ntdFfkwKzOpvg+zz4Xbc\nBhNUXyLQIBhPM1AumF2JmLTo4ho9GPHnJEh0aPsLEIOPwLV7PBe9xlAnK5k06tSgIUL7iEednFZg\n4biSsB9LeixegPa+KpbkLcx+o1jCRVjQtwdFFS2fnC924AKk5Gjoeb20R/yJZi53iKYdo6uGMN8b\nv5Ofl/t0c+YBSBY5huboSNqzqbCZ8Bqsi6Xy2/rrfZrmThV0CQjLuJIr3caDPQJp2oRzlRTTuSYu\nNTZDOdaYvS0auDxq7WQLhBzeQrPVJWfPYOxKBwPBzhhTNl1QK1oPiHl1FaY/drhF9HKNv82pho2q\nAhPWVBaSLdwmd6d3XZV7mDAPE1eXjrTACXINV1gQGSNzh2EVg5eaCGgRGKn3Ur4M2CLCaDHUs3pB\n+qnFVNG1I7kEubldsvfM0BIoxTci6V5FVrENpsnwHN9AaohwCnCZeKJx6vbibHmwVOdfKz8huykI\nmb+pJRKS4AJ2BXiOeC8XLM+nQDXpIe+sKNNm2hhH0jhViXeamkaqHOWadfMqcwsvCdl2Jm+yTc4Y\nZJ2ExlhTSsXXDMfX19ZnVpSszN42/2LFtNHJ6gKbTXSiM0gWjtGopgM2dZCDBQCp17Gg7Co+m+N7\nCbOX3QkQnQGPbRAJnqXKan5A30Wgtz23HjWRCxtCPMxUTjTB+Ys9iFkCHLGpQuJpIcpTU2BHp/7m\nTAtRdXuNXxEGMezMD6CaKhkUkUIUIKitJLam9YFbtoB42WpbM3IDmECAiIl3GM/1Gk9dP3nh+g2X\ngdz339aBAezed7jjvrt5MjdkGZexjpyw/wvwYwzvdS1gHST9cMZKxozVUNNYt1ky5+vcT/t/roB8\nZZO4LlO1kiOxPczji+TFzRd5NTtfhwUNrvHfH3ggJoRCG8Xa/HCutWIrO4wCxeRgcJkjzrFtfpNU\nsZmpLPDpJq5imKnsATUNEqhj86vgBsRcY7I7630kV4S+y7tJV1nArNxY5P3q7IZzRLHlnCuTp5U/\nf7CywIvKcSc/mWbGrxqgmkIKjJCSfhiZB9w4x/Vh/xjKKDxm82UwylTcHDLU27U51/CrejQEjhBj\nucKjJxNyr6SAAKh8cO1YDT2RfwlHiAiopZCN5DcJR5QrfmRUvKCdNa/BTxDEdj5MjNqfceXBDS3I\nJyptF5nt746DUV3dhTcsjbHVZNXSaezWCFT7rm7Z2kTCX3+sQsQNexrXcb9kiyPd+kvjiF0cDteH\nAuwGtLW6/vFl+8z0eBiUVM3GTHr3l1+WTJjquZJjy/iwSCH3LXMkKC6jjCw49YkxB+wDcXD2DRai\nBgrmUv9NNnFsxY/Bx2fWPVZih6uw+kxXUKI1bPEnwk7+nbS4nfHxRtHZgojPScdvFzlyQzqv2Ipj\neDuTPTDDR/VSCMtn0i/r9kD+P+dBjKwVNeD5XmL3i/KqB/Ycjfwj84jt34U4N7vp4fpsWey+uRXi\nGkWiPH+4hPh/EgGA4GYWWSYAD3IpFwOQsfjJ3HFMlvOwpY7ZlSgjTYjX7zlUOPsTS8owDdwbCdrd\npRGbR81AWvwOJbt9Ahv6pk51OVKAMK0qH0RGLmy/sgGVvKGRylrtfwTaMIJGP4VRZHWTp0kYHuyb\ngA61EDQXAzOh8qNnCSR2yPwAbm4pNtetPuNTtcMgghnmkzxojsRHGXQFnxqTD8DSEvPy3Q6Jfn65\n3j52uznXgM15StY+gca50VRzakReOOyhoU9bgv+ndG0j9Jo+9WLWvd8ADcIWgXLRB8a7+vpVvpDE\naQNvbSfjLBZqh1sPz/F3gu5tMseKh16JOHnS4TGFFMJ4fDYZmIukX4/pqux2Kgn6R8PGeeG7qR7v\n9zbQNvKpZrLgUT933cL2/9D5KZX/cm9KNjayydUvKfukDB+0Aphzq+WiSgG8jbQd2RwesYWtQnP3\nw/JjTyFC5d7iEt3EUhSu9mie9vm8fW/ivhHn8CMVxPwBwehltT/VoMe/PK49tSujx1Yx7qCHerdh\ni6PKqLmfU+JQXHF+6VMVbfIYnLF3DFfK3BUMPRvkcsaFm6FPk71hJOMoUez/oSXycP/W350OaTmn\nEaPdqJcu0Eyg3/hWeM8VJk6zgXmFsV0rbgYAZQbqMH6KnPgfPrKfmeBFg2Ep+5LpDJ5MS4//cFQY\n0GcsQGHYkMNdte7fzbzkSZL4tEIojLpf6ykN4D5uuY7c9H+zTgX031z1mNvD9kGjHpy5yE64JcUN\nA3kbWRW59IJ7mofPBMTNtBlayLn235UKAZSYFCxPcaOUuSa0RB1aPkknzjL5uOStRktLMXRtw6jp\nXFDpk8Bc+dz3roe+cf9rox0Horj6gHDVepn6t1Z1am9vuW/9H/V3k9YTHIQO+G5x1ZJFD96QEUnv\nBqyv/Z6/sUZxM4qtCCrJ8oGI39/ecuUylPgMFtV9uyklyLPzto47nQEyBQvuXvmjwL3J5Uw36sMc\n86Ot5W8nUDzRih/pGq/60q+JEJtL+bEDBEXsbZWqKtRpNdTORbRiZ0vc8FyeP88npLQ8sWUKZCes\nVDBCpkRU4EbOS5sFp7/mybr7x7lXCvtPzWelJTAA+eCqRW6YizmKpIBZyxWipSGztEv4/tkkA2HA\nP4wNSxAtGVg6htiC601TYFQMzNRXAO26nekWYlGRXVZQ4mUYOb5kGCAkvSsN+mi5/A9qbBYdg7Mm\n/6N97oOFfmfyjMYDnc3SdOJRQvaY41hG4EE86XaX2FxuDHf3hl1YJUUXCYzevlt2vO+ASIUUFY7y\nH4sYN/ymCOMVHPFXbk2iB2bubiNZgxGJjkdBCfLIdvLVEvS45fNMMYNXgoZz248d7v+05/3V/31M\nUPaxsOqQ7aOlmGB0GMVPfjYvqU3wlNtA+4njGg6QqbWe+rkUtvT5rlzM6LX+58TPc846wfXms0ka\nHbFtL65R8WbxGHBaMSpsBEoVifjd+6HVc4gaQETvVDNq2fydPWbB6Vvo3H89TVyrGnxqi92miu+V\nG8DkyXQe7sjeWKA2Q83Fa8MoVoMRG72nXcvtEppjK5dGtmgRg0/+YBm5DU4Y66X0MrBXhfMk2Py1\nnFmxUBEd1SQ22ctdlY2d8b/g4/MKPZDUCjibIEXMZagX3411qkheQeXaugpXS5EQ2OpEJUM4tyGt\nbaEuSvgOb02XTWzDStHTdYkK75AagW3Y5jqupfML2gnFSgiNt+GJVs1Y6VKLxiQl/+m+gI0OpA/+\nxXJBaJF8V/sLy+b3xeISRrBgPB3xuw3WcnjeMF3wg/GA2omrPDoUbAMd+7E8B4YtoANh4H/L+TD7\nnb3b3b02hp/lnOPf1qEjojbQVGCssxsC0ecqe0tjssjaSRZsol8hQsftQpRyb1AewnJvj1JdbC0w\nt826J1tdgpOdXx2zLFmf59NlezfJAKbL5cTkw/PuEXXV+EtwlvMjHNlMnI1mYc+UJMvdi0Tsq7u7\nlHLi3sClFjnRCN8hyl+gtJXOVm6KC//QcmwVKOPQm2sUFSQLOa7nh7U8GSWkHD38c6k3D8bSTCEZ\ns/egji42npf2H6uKebjL3AjkiqPdTm1JgZuJFzIfxmIHsN5ZUO+cRHxUaAI9LEu0uGCqMKDDoICK\nINPT6Eaa9G0qgG269/WtJr8ypeVekA9jNv8q2FhxbDBVvRGQ3XhDzy87WIB1m/yqYmVUcWS/Y5mp\n+eflJQMnqw5Bx4JJ94TPrmxvIEOUGocb6qD0mNFL0zslwtfheWKoOXb8+t0jtuWP+WTK1oQQM5Nb\nbwBer2pHtgYETdMGn08Mw5DMbhyvUoS8povUpRLlW/nzbsNm8VHAqyxFpN30mU+wMAXnQx6X25C3\nmbTzIhK5jEYCZbjZjM8GFxoMyZkpx4hG2VuZ2/mXgYUE4Te4RAA5SLWQbbZ2jk1AE2HoCQEkItiZ\nPr9b825rbUJgdgUQNUsO6qHW0NTxzPtmDGHgeJtOnWKAZezfys8OYKWdsumQrDNciaLVXUp+4DKi\nw64PtnYityDJbonUB8eE7GmtJwA+SWntxwl7E+sF0w43+25TMN1/BZCX/QnHlkyMW/ZzGUNMUDRM\ntQ5nkVjXZ1lkpVzQSrmNkMf4ZVmZ6ysFuJ/kT3htDMlf7cgJZAMpypkDxFkLT61ffMX67/oPgJkO\nNDBSm8urdQCcdzgX3D82tSuJqdq5IQC61NdVzQwsF9b65bAEZUsVzFVSICrXZHHUHWfO1fojmzwn\np0/vUgNjDgB+FrkCXjMlhqJA82AehRPe4NsOaHdSrT+aIGw9d2N52jZo0P3Y7jX832B912tvHNt8\n9oUjRSi4NF/mImnwicze9xhGHR/jZ31K3M626DxswMp3qDcpRD5JysZ1Po1cse5JQW87dNBVR3f9\n4c2GQofwfhSEPv+j8JMGdILtioUSmrBlZE7DEBsX3GW2xIyLYeQnyuV+MekzXnPnxCO/rpyeBT4f\noMCN5mUWtR5hO5lTgOk3PRhGLFDENwWzIQYYWMs8yTARKmKSjV9xsFSlzytD3TxIoNcgO6mkA4rz\n/Hmjn6wAKC7MBe3PEdSe6kDUgy7AS5bvGGJjzHyzOYiEJVHyTqDRMEjvBsKc9RHe+Gnzt1xI3cxS\nwjRuafeAnA1n2FpUfwBfTz+fjddjeUWSUYT0f892M77Fekj68vgspnJdv8LaplA9a9mv/0KraOC2\nH7DfjeXI7QVp2QJwjMzP9nDmKSiUCdQR1heuLuY0OQ6/C9afrELfiAzG5pYLvcsF5aI9Xtt6c9Ge\nY89QelpmBNP6hY1rVslr8rdxTkCy8WnuEydUtD33hhLe15O/Q6buc4aPpdFEbM3p3nPlBPXS3Y/b\nQax2bqaBSgqFYoO85n4TQljbhRbe4MGkVCuVV4xjPxUnd67NeEaITG/UQtP56GJh8PIod/XHBbjj\nzInAQjKn28odXm3VDzVQmJPPFrfygZ8C+TZv6c1xeo6KLqHULHksaDE0qH3zIk3a/wE8hWfM7tSI\n6CpezRKP105kI5UKqyJb9zTHwLTGksJ2SfM67/WAc/9M/h/ssTSyxBC6WHrcrhYRPMYB5cWWegOa\nPTICKr3gdT4fNp6miKh3naEIKYjasZV27c1NK30RekJrEicgXgSRqRubukgfnsDoBUpOss/9Ddzm\nywW65XINkxT0bI5yWmcjKtLbfNOP5NuHLdSjDJpj3EOAs+DEUjDCTAhR8qJQ02uAj01SZRus0I9l\nqAteB9MI+dBG8FfMaWJhbwzRy1MRY92uNseCdZab3oAh+XtcLT1tGXeuG4FsbcSxdpzP7DTVRCri\nf7HC1neLGHxUBdRFW1+U34xG0siZpwRXV+HrGD7L1dwvYxFpQYgIWqTQ6seMDHA5L5Ks+x4DxoIS\n+ysuJeL4wSHyPc88pB4xBlIbop25KWlHRO9SCV8lasgJJpF8yxmbWBUsE5M+JlDsejbwokFjcvd1\nhxfA1mGaqsGy9E1OAqsAjM9xDyYruCKCyrD4pt6p3W9NB0iSCGsAOI9FYjlTSjdRdl42+w7GXSg9\nqRn8FzCe0kYO9AFnmakVNurjzC9UEhInRNoGvXWjY67VVQcCnNbB96Re4IUQPToRw/uU2GsSdOff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oa++RTrcoy9gVR4k4ph+YVvSM/ZMsBQTimZvmUFpZVXDqTDXXgX7uV9WHPJjXA\nNgoLSFlnWfTgRALGipeIwGqAjr1KF9+h8JDyd9ysCXBzL1vJqKtWB/hop9tcdXLS3eQPGAPgKK1L\nO7ep8v01o+uF08+TMczulLbf7DgbT9stMmzqjVYD/VCUnMMK9LviOZqDJH2y+ypHqKzibW/bEM0+\n5EG8v1DtaQyoCGIUGmZ4yK3qqh4SVtxmS34QTi0dmn/5v1XTiV8Nd79k0+B8xG1aoH438w0T4auo\ndMll9nFr19XyZo9jj3iZATwhOLtOEkF9ZWVGxuwYNxGjiOGS2p22YKCW+2VGe5/Wls+hoflocr9I\nBG9nVSfWS/rEMFCG9cicphGQ3o1KBXkoGGSTV6/Zgcr+JIjGyoiFItBCiNEmcrjQUoFQ4wynbB74\n67i7t8vpVX5eilemlzRxszPizxs6zb+eFFLVSO0lFhdZHOg3p+/xZG8GJqBa5GLBp0AMYBqNsKFk\nc+nl9KGBYUASSvrlcyvsbYtyjBuejJmN1puvth21BUY/2sqj9kHAuSZR+1qvmgtYjTiY7G1xO5A5\n7Dc8YpyikmJgh9LIpHi7T8ERpFVvMhnJUPYUhOjjMrYBHebhBnSQ5pSoNEjHwYhBoI2oN95d7zZ4\nKdEYnewn8cRXc/kByKSFWmTpv6CUbd2V6S6/BKOCFYWH0/VJcwh3Qu6seNNd0lF0E7MZTRKs9Et1\ne/KxMPIJGXiYVw+zOgaiEVJfSrZc6icHrF2TCjsXJzQNhaa4MwcRAJi7DkB7J4lJqCcF7aFYtyKy\novYmXPVsBxsMM7EiSO9rbh9inJja4HRcffS7uVaGvJ1x2hzzlDJdQXLatxxDWt83w6ztjCHbxNtK\nkQ31gpFWv0qEmfsyWBF+SbiJuULutuHbAJIOA9c7/wXlU1E/wkwqrvQIdE9+69EH0LCxskw1XuTe\ndEYABia+uloCe6AiywQhrgJ32p2cqnc1rvdeB/Had7jEfY3nKhhRV0cdIbmt4Q/pUX7YK9fd8juA\nGXpN9FvphVVZtUVw8ayRGEK1bwIT9fVrk/SV9W6rPepJGPriTv8e+3zBeQI9UI3Ux720kyKHP4I+\n2ZFX/84FdACDboknFLnwMwpVN4OpYm1hg1U+31xgOPflYbDxe2zcJ7cU6uSUBYCd5vqL4fUSXnGF\nquM1B9LPVKyevY/9usGdD/1pAjNJVuiDxC+QLGLDGmiSQ9yWEo9+tw58Ub1vQSwIcefdyiev0Vbf\nHgCjRrRFCad98dZKd4zMSGJZEXdBxh2RmJOUmvXnkEXlS28YsuXIIJ+4KAICGmZMAsk5jVkIuodW\nIRdqWdE8x/n5pXN52htyfwg1tjOP4XYZnFTlWoq2XXjtqDo59CKuJLSJ+qfJ2X6DlCbhcGVEPYmq\n2wm6C4nCj2xLdWmyZmeiWgAOy369YHd/IIsjTrP+h+NGng9JUYRHy/BlgcJVUTTT0pVWdaxeJmUj\n9s9OCqPxFzbsWDK6gRug+pHNF+SbWHpNcBU5K8bYQ33ni3yefYLrTAN5IbpF/bAUzROgIbULpOf1\n1HK7A4cGY5dDN4cefGUzTFwK9F51/22lFpzPpVjQ8N4sdW71jZ/C1ndyl95xsQJMOe//+REqOYho\nGB5CSLhPHK1HaBuWZTBMKhbc/QQYLzdjftwhHeQMamdAR9QaOuBPfEWcoviRxSdR3ooC5/gJkYou\n1p0JH/a2b/xfsYejgYCRAn4x5qzuXt+L8g+aUESjBFx7ruIlvFtAdxONjEIPWu2xGrLh4tHo9Uqm\nJuM3nOa1nSbTWYSEzv5gffvHgYxe/65oyo3b94wLsMjsl6hhxik86WA6mhtAfAlOC4bFO5zFFKv2\nDFLe4kN17FymNABefiLgjFWBqvyMnwAWozw0J8si1xG/1yITUhKTQlnrrfucfcu8+QXj98VSmPiY\nIbZpl8VV7yd6QLUJZ/ueqQMyD+4DUAt0lJHA7Jmsq8mZb3NlVYU7Xbo5fYezY4CfzlUBL8SMO67Y\nFqttqG89ql/I0J6VTHYvUyzbjoyL0qeaxK2N9LUbBtBUbkUy8xFWx6n76EnQeNIVlCZysNg3jOPp\n0TC7qdRLfxNvTVF9eVVGjwZP1dVO2v1mp7zreDuktRfT20Guur9Y5484skdYDBY6wr/vKQwYAnw6\nhIwwg08AMSZxbBz90yVT4ShztPxb735C4ioSm1XAZZVdT3V57yB0r6G50guiZ6e72nUnUkcKPm+t\nautw+x/DN2qCJAF9lc1IrPM1tS+T50IoVmh+WZPRRfwqw66/GTcMV9uJQgl05VtUMDInFRyrSaZC\n88xCkMSYavgvfuCF9OeRm6pfwCiD+X4T9fJaibG7MqbApD4YWhgJE9CLYH6msrh87/V9e4kyInp3\nNUvd31lYs0H8qD2sbtp/FTDm4a6rB+7Eoa5pRiJj9b568o0x2SI8UlMRw+kod6iKDyT8UB7KSCqh\n/1hca+Z9ucyCNPIFfAPM677WlurzJP8Ur2ZUj14E6CwG+dv8DRkIvcqC03mRH+W5xjkpSlQEszPT\n1fcMgfBryTympntRT1130xHp/GiCMndIABEVfWC99aw4I9bzM9/xJBXOHjmnGrvhEL9VGbxoudtX\nATO3geOUTYb6p4peJV0pukR9PKAo7pEZBC79/Ekh2IHV0A3lJEiSmFpZ4Be92fN2ZGRRhgJ/8jTZ\n95fyZOYB/6EpR5vAtw49RkIoRV8n6OYf9/GSQnretUg43vYkGiITpP+KLK/BVDjP1kWTKMEF30kc\nKgcW2o4SYWHj26C0ZFbOQdmxyCnvJWB6attPc/gFMsKbTFxapPqCH3Gvtldbhh0prZgDb/E7s+dJ\nCf6sIJs3pJp0oAwgds+hlu5UEBT4fhK0Uy2yJ31XyvwGqdEX1tl4g/yjNGcTuOYxOn0GN+Rgdb30\n5mSqtul7d1hwaDE0aJ9PSGarQw3b9kA8VPhh8GYtCPC8evYM6/gUHvWNbgaCqCHnXQVpIlq+61mf\n/UWMaabeYZineiPPk6bQV/b5FGWhviFybgXYqXrTNJtFi4Oq4jjq6cpmRbxIZ/l/7JQTm6DRi2Fo\n41iII/H3TppZgTDXlh5TtzVERBWMW3yrXrkfP4nmj/gzUTLmRbF6TogISV5r/GcMUnSgOnV/aHIL\nGCd9lAU/3TdNg3rhJYANCathoCMOWmEP3KHUVEcDqE+0RHb8Sn7jxiSij+rfXSL9+/iWVkdt0H8r\nM91tBfgiq9LbxCbTigRl07vVM+VSpP6BRJMBi1pbB8xcWT2SAcWHkeOE+yiIvsyr+txQkIFJY8fq\nz3EFa0OcZsYuDwllWdR6RSjF2u10U3OgfFDlKfTFJH1G4aW+xXq5Aoaw0axDH2TwqJrX7m0gHFPq\nUBYIZzYSG67XcVy3z0HW1PX2WgBzNiDbEZAjLV1Y8z9VO0gN2/S+SmUCjj4IywJs2kr1ta+y+m4p\nLz6PwTfrYV3aMImK2TH384egX66gB49vzbQd5ySYxUdRRJGYRf4qSWiva7OTPsBlv+zU1y6U4/qw\neBrmWY7aAUogznd9h6/G0UoYKzBu7sRVBJDv6Qw3cy8WMx/Yz6ayqK7bUZi7GdohueSem1sT6s/W\nyM2DW7CFER5WnjcK9Z2VIlbFQiZ7dbGqZWOHmbubNgJoVX+3VqF2rjnhpa8voOX9tpf6vh48Nh38\nJ57zcvvWRqTrNNpP3t1Q5FaBTkjpxin0vcyA/A19+O2Tvw50wVeU74P9fw1insSbVWAZJ6RhW2Wc\nZMBB3HUxPXrbYS4QuL8HLfOp6Vv381FEdxAMoaFskty6Hv/T1ycBhBTlgb5dNF1R8RK4d4Z7jLQ/\nEwaEHx04h0ADO2FA0SQIaBevhxheReGn2NVRytqlr45CEJ/swYdZqN/BCv565PVE5Qnh894sukhV\nQ2Y2/vICp64iAu8ATFd5Nv8XFQoeemGVkjixo0Q49nwPa+WYw8WWHbQkAyVOvhkB6MW9oSee1/jD\nXFuPdWQTc/mmCHLCvr3R8kqFGiHOyyUA5CjkyGxnFydf48kEr+rekE1z3wLxneqWcNBoT/7GQ/Hs\nu8UA4TpPXHgoPImivQmPVbKAAt3R3uIVXJPggi6/gvBmNOq8ns988Ghv2gXu4emMYVdrgmQ7HQUG\nT1bMSP54p8epAQPA2gV9kUvfrYvaQi0Ypg1prtl5OOpghtlamPETqgdka79sfozTy37l7DJPL286\nbTKZ6/qbP84zsB8O1jp7xy2ZfHQ1bXqV8t2yDpL0SMxJEI2dGY6+k0voTya5nSNP961268XphCEf\nmkO+SuZkKlvytdpNY15j8lWwk18iT48sIXIVZDHMmsgPhaO7vlRfNrNfqXpo1WDEToFpjoOsrLFb\no8eH6woO9zXN4BoJ/cEJVwa34sFdDdNja2yV9x7sfMfOP6rSm8wTz7t9MrtGyTHiKe/dn3qPvKd4\nTmLHAiZZJtd4M+gnukp22IBgfIfyaeSWGTebl/kDgXS9HF2oz+qQ9LiqcGNqbXsBLmvvC1Jf3poS\n9pyBcm+X0vWFZCJbkn6yMLHSP0QtlQoGJNZGwqw9MGUm642w5FwF/bKCvFngPVPbK5Yv+SnnIXEb\nPN7Sbc3693oMMOViTBsfTPV6/kQUB6uG1EDS4+gssivcXLKsKSTk5Xk4Uv6tBQp3a1sQM0373fEi\np9QUwDSShtSFjZTA3780Q9pOb/dNMlmsjifNp2tcZM56YlpAYzmZrIAQ3l+X8lU8OLpjfQQXVNkF\ntcPNxuya1wOPnLCkhVZp9mlLCzNlNtsQ0uEYfBbzh3E372kHdjF6Sr3wReeihlx0c+/qCBcZxTWq\noV2le+sw7fB9zRqP22Be2h7dezXoh/oBc6b8jupXcGgWgMKrhmTpFI1n9xWAL05JLHMMXNPLqlnk\n/MaLY8W6AwbEmSU5juAqwBqW5+oenoAsGSjgN+1xfHiepGDAefcz36FXx/HI0MRJMkbUkchyHEKP\n+1CWEROEqa4WRG+WND+v4fhw0wHyFxPkOhXGMXFFpALHh69n5WQvlMER1Rtv/wH+9cNfFyBumt0P\ndewHfkiFFi4j6WqAkEYGkUV4IWZdvZfF40d9gExr/5YGTLIA373jIbCrE7wGFnQbIcOKPUp1PZ2U\n9iRoxgV7upOOyEZIx2yqpf4OH8Mecldu448EkK6zc77LsuI0g3aH9KfLxgckCtse9bl09NI+2tGA\ngUAebVIz9rj+/c1Jyb775FnLsC7ujSQk7vwkQRRkxtEDDcln7jUs9Fe8hjyiFtqf/JdWjLskNd7W\nocKAfMVDnoVGiEYVui4dmgZCYhMvxkiU9oIg5k12wQ+B1F27iBHsZ7Q9C1iAFd3hGphFXFcnJT7s\nEg3NH+2EusRve7AeKq9e3/9iZpu5LdsOYlbbX8dEHYldMh9KCB12s+A+CWM27mYfnpe3jYe1Ajmu\nvcejt5YKqiv92Vue20Ef+SwoK609E0F8rMy0YQYSQH1FGkyS7MLfM4MKVJF3jTQR7X8Xd1yGqUva\nf0rxgp6ipilJn66SK22KKCL1SvR2LacJ8yBGVoh0McWZB8ZQuVxY3DajcJSvPNdbtF6JYWI4fP0o\ngAQCJpMEM68QRy00Sffff+27rgD95bVyLxHiaV5rYm5jT9uNqc/bFIyTHEFS0C/uD6ckXcLTMdwS\n8jsuvJxy0TA8YsaM6Z7pYEiMoTXCvvDDB0boLPI/9YR+JfP9F8axGheF+9x8UgrtH5KqsH11bNMq\nvk9SttEdsRhRjbhHjoDPJnQyQhFVpMIUMzXB9cmH3lR046/LJLDKMBVfXuHi5lCrgHhZc6GG7D5e\ns5X2tuXPyrU2YlP2EL32eL4ZMOXJFZO4e79taqb7W7oRzGEP4XVViy02OkXKgBTtQP5KA99opPOe\nkLVkvXoD86L5WTqtp5W2zfXjmlThUCudupryIx8Q5sllfA71XNc7HBsFCxJmW9sKtD9Fcf92fODS\nybeLHuKCq/u5oX5TUch1EBihIBbIAGFLalUcT/iy7bu4wkhlGrlIX+MHYkbOPGkGWcjsU1p+pBAq\nW/tGdg7goexiONRThoVl6B4dkymaa9IAWR//VSZ5XLPB6+FT0diZAJHVCixiWcqHfyh4iOtqELLl\nixa+mytfxV9oSOYy5Nsvdbp1+mWl32JBBFoZrC/UcK+kwdVb/w+u7yAAu+sqQOog79ETEA9ePYtL\nVoQlNUtx9JfC4GiDM4fo9XWhxEfBBEEmp76Zb5U81BHm+zLfIGsZSl77tVekxMfNbFKWqj0NPXMa\npJET2TRoj93HTNrfDYTdNazu1uMnOnuOpixonXmMTW35TRfNik5MNOQd10QRhMCEDVirShAt1XRB\n0uC49t8UTtndORWRuNazh1zItdJ+WgqFZoLSXwjV19LSRMXVAdltV+usVrCb2LJie7zTX9dxyh0S\n9uZvnFvLjlchA4V4xvVnlm8Z+egwVTUnTph76iNNHdFncN5CtrtuBcK+ewq9Fm6V/QYtjuN65+Bk\n7GoM+wuIo88+UMvjbwmK3ZT1I+GV2b8O2MN5Ltr6Imfju3blme4XcNlTOW3bRe79yd9kvqM/plvm\n1cCWRJquizpKITXJvYtfMa4YOcfv8z0vvWNhfVraYtylBxB/7RZeS886Hbp2Hf8cvZz3zYQK2N9g\nG0JcDpd1MHV+LZvz0sncUBMTNw2DWWj/RPFvzE5+MRw9Mdo9SpA24oRvoo2ve+kghl44eLAc7Ugu\nrQWhOhzW+WMDes9SmdZ/NQy8+U5apaFrpc21ffS3L1b/RDLW7xDq6ainOjKNBaxs7j2bT9Y/rRGJ\nKBR4n7Vk+R9tDvO58SU0OX+Rw2q8CPNUe3ioIuQPiwOoidaVPPFGQLILapq2O9JWxWylw/Ck+T3U\naEDocMPw0RXkce3ENeRX1nGULw+UYXKJRbFxMe9n3PLoDBdoMtEzijx/VvJKgkQ2FUZ41C8/h49L\nTVk8ijVRr6m9VWHXgOJ20Iny+0dXnLoXOgw0LXq7P0B3XOdHtsWGhwDn63KU+ku4AhOb7Yder34H\n5aFi8TKUnqVAzeifzeMFlTxJml8SEABAhGOz7Pnky1U+Vsov/OVbPx3klsxOm1DsWCjYXHoZKyi+\n8y1temwYH5HDLDe7MpJGfME94yQJjEkxop3+O9C5P9ubFqb1AsSer3YPM/0VYvdj2PXfl69MWjTv\n8qFMWq+RwbCvkFHnlEbn/1L++HQjHx0sqKJe7K+1VHVzihDlO50x1pAwiU4/GjQxT/DrodLM69w4\nYLuJjnX/WiMACj0BVG3ULw/hq19NX8DSRFqVkPToGFnnKk9/FDFWYqAXk49CMJdeY3wlRDFPEa/W\nCv7eogFpvwt/l/xvTQItnqlfImY65atQyD9M3G86oKpt0auwJzPCquaWp1ghwF5wCQdJ89l0dC8A\nBb/BIHNOxbWOJwsdHrF5huGR81/WJePNThfYVxYfUgg8fydMwsV/797ZkJcPElXThrAcveqWP6Fa\nLf5ucAw/0lkqgGwLRaBBJX9AJoY1AH3xcWLT47uQd8/ynvSbznN+vx7YeunVRMzxStCtX7laf1+E\nidLDONMHmjQQaxo9E28fvrNttm02ZW+EmsZawY4sflY6E6eFXhdqvRzLg01UBLQVQlm2GugHQwa4\nDWoDUfenkVefI+pvPlo5SD0xOxBD/ik7JxvhyvrKnta1C932HpDO2waIWtPVkWAH7YSNIRc+FinD\n2FLJdINSf0hskW8iYfidzElEolqexp4rOqPjqYh+djfrlvQNS5opYUU01OPan1X8QZ+JCCfzr4Dz\n4KAQe2GOXhwaCsX+hkTUuMFxOmN7h1fySzufCU1EulOEOdcGrGxSXOdH2qJZ3j1tRpezZpxgaUG9\ngA6VYpPXmYR8vw5w9AZEJB6UnMtBww1MbIIhV8fhoe5fu60mUvf/ojDkuKyd9Zot2xoKOvoXDsJm\nmmHM1K4kxOVSqKMQvlYBT1DJM+L6knXWrJeuuSaSV9SU+zpkRt5zdW/kPZojmZsP1wQVd1i95kHh\nLFI530WYLBu0CSdm92QGRQ9FBJ6we4E5u/PxFZ5a3+T2eRUwneNT5RhmHvkJtQ1YZN09eOQjfIoY\nMcuZPtvoJzhEhjVc6coOi69kGXV2HTvJafG3KhewOcXia3GC2KfrGauyuQAfogJyebNs9i/n1Nix\nAtOvduBlnIYxd0Jh2FgHuAgzaOX/nD1P56g/U08bgshpgtYsEX582P1W2uVyvZbShzzl4sApQUUM\n5ptV4dAxQ11sz4iAVUlvWH7zjwfquP3E24PhrWUG6LGkCFziEIHU6z9N/swLyvwmL+zRQE6u7rTO\n7lOXT42ub9y/t7Hppr8vjOFIUAnLsvPULfVy+I765HT8WS0LMSmm1A/gjpLIXTNvynI3xkVS2cpq\ncMMmwVRu5sPYIzTqfHt9jZPvqJJNeZWac8FHanGqKwzNcO3G7vPi6V3Xt43m59Zbscpms0SqhcO8\n+aLwk+nU9/nOoT9LbSRapNoxp0e5qdh1G3Pt7Kk9ipDMw3Kh22zGp52Mv4yLgPdyvoNHAnh4kF99\n/jAwrdKaRpUiQWsdQRt+7daSEa9iyRsgUJaSI/xU702xVnpx3f38p+f55TCpdrGrj5udPBsqGa3N\nhJsntIlX0Y8e5WzG1t86uP4q3sqkSq6v2nJso0spj82kKpIgCruh3o86Rcnl1LUyUoKe9xISxjR1\nPhKCAbRM+hussJPjUyPHSqRZDP0gN/esaRZZG5TOIDveDLe6frjNs8dUlBOOcceQizgjsJ0VyvGI\nry43ue6KJ+hKxRswtxIAXidavHV7lXMCq29Gj12500YfPlPZVpjhdAuji0kT5BlnTAG+QNtgyAW6\nbI04fNp7EEOygiyThOjqSO/kMvyu4jEMlJT+rXZr54S9lqQUwQQAq0ZHQGRqyRgk/MymsqB9XvfD\nI0KLj33AWDSVN2l0eITa9g04G8XkeXJaT77af3GC6MhGqYARTnfPKVkgi1d5kt/YydkrwhBjf4ki\nYyVDSr2ICjzHpkk1hhI6j2dpZ5fYubRzcNKWzrbpaSdwt1nLJ5pGHbX1D28O/gEB3flpfk3kjGl5\n6XX9jBbOIeQfGZ8crXHTsToicvaukAnCxbstPJNoBVlkj8Kn8mSdoZyROES0oFAqaoWgmxli2EBs\nAC9tSH/wtQ3t84JAKRXbfcPh5/Bfh/f6D5i9dcHsJUsDoZ1INUEpxwdvO0K55vhkLlHM5RFJf0Nu\ncmtmpWsEvyJQcuG45IHx0/zOP3WBbC3Rpz7ROV+VGmjjeNSMp+C4adFyQkG5oDUk7iARcOKgRrZy\n5mF/uFyk03AQMmsqJqUM+V+AQRB1Mo1IVIC/qBh2Mg5YQuj3DZjJsfOjgMTBtCDZYjLmcnuMTZ3M\n2EmYiV+xtfHgVLugAsgRdxbONCfbmXaJ2dkS0xwyU+yapNAgi/45qgQoL6+tBCmCuFfIxqqCtvGT\nCC8Se78Ge5hjy3/pkNxs5NFG9hNxZwl0dCkpNtxArx5La0IOfGLB40hP60U8nnXiconPC2DldHd3\nhq0U9Y0pO9um0eOVPlM9Hv8Bk0W3L93JlaoQyXDIao8ftYWLqTJt6h/2RsVgod/nsB8s8XeBIVqS\nScv2IX+w8Z3D6u+QTxo9ExEV+Zv4eDEFjkMUXNDFH3R+5NsbGTImsMGAt87MygvpGIYi/3HijD+O\nIkkxrGDyrgYv/Ksys+c65ieTz9Tq2WNt6RSMXX6gxmSsWtzMN7uKN1RzN8rgTOsHPNmtVDpv4VNN\n16n9AeOI2NQLuqeAdqFY6Vih95x2CKmhCDO1/a6XTEq6w0P81oKGtnKRh982KxfNW5P5QBb2OKRw\nB+XMki4FN6HnTk6wz7jwqw7lxjJX2Ti0BEVfEl8uTfMlhQvyJhDhNfnaoiQHT5717Rv5kphnvUDH\nkbu4lYKvhDeNNWZC7XyWAlXhy0VvD5qXEVZ+2+Tmdvw3Od+7aLH7F12ebmhtoh7yB+Xx0wOKwqBw\nb/2zwE4mo50x0HxaWwLVywyTXSB0mySD08bZrnJyXkgE8ksHj/EXAbMzicAR19Xt6eSjdT2JUayQ\nilULDB25U4YDpmr+93OiKBuEvca92AmvbOkzy983hUAQswxnI54BvUs5wgmOBLWGfvRPJR+qobN5\n8N8ExLoWaZVtUrzOWgD1vFzkAOSWkLJ5XOzYno7KvPZmqN4/cue43zCoECFgYJuhuGNWbP4YM1yU\nhfqnary6ZNHHukS3Jr35dMy02q5DZyKcpQO2gJ/rTg4aTTfST4V5UCja5Mv5zykLeVkhWxlNySYq\nsCpf2wxfNtu0YX6486qJ7JDa08uRSDsutDh7m28Ats6URyrNgq9HSJ/tuhJrPKAycS4zulBYe+3x\nFiwpjGZP3K2CSEe8M8RiflojOf4R2n+Dys15R80UsOZzuQRs9YhSOmHgjiCW/f3PEXsL9+qrzwLE\nyX3I3qQ2reMkXlhV5D5tHvBhZnOAqYIDlYS7siW8oWsm+zYYQz9KiKXJgrVH0kTFxFY8cQ4G6apO\n+7IM/VR58WrtyejNqEcVZKWFR9okcHcm2dEFE7EuxembZAAwRc2k/6P7kCDSHqJYu0cAkVQIMRBv\nnhGK8FOr5sS+wYrHzJHmoCqopivJHy8Vhaem9iqQU0UCqjKJIPVMgr8CRrH74VNdMaSSLQohlBfz\n1eLmVeA1lIR0bVu+o1pMXk/4xo978xcOM0uQ7SopGXb0QKKK6L4e9WUPQrOgEvMVFnNQe2/2giJ9\nJ6TZabyIOG8wAGLq/fjMXgPDhYHkGDKUGIRqkS5KJ5KM2BWsMYcHQcOexYGvqY5ufXJ/p0w3fP1n\nDowTTLyq/q4KpUcb4CFw6c0jOSZ78g9itwbhb62AQMcwDAoeYWaPHGUvMSFg1ycUXQPqfguL4J5F\nxlech34HgYc02t5dh6+uNYZYf1WK2qPnGbZ2cBDbJjFZGE30wThxEbJqD6slp8qsarEacKxdRc4t\nS/shFQ9cPLCi5BQBqg6oHB61uX1PVsV90mOoWY+HCcp3z/kbpEKZ28RkGZemK0Z6pRXr8jv3ewOD\nijin8ZjfKY/io+mfLnIDFLPrCImsu8xT/d9CCqd23R8cMyzgjOLXrMsYrM7buPJJoFrkb9CKqFJN\nhnnE2ScGq+BhPDjgKGqLgQ+t4aW01jxCBejNhng8FsQ1EHT2TKF/Y1/GxmwQA4f4FajQkyYmhr3y\nlSYBI3r/ZvnLgMBo09bKD0YRLcfOyurKRfWXSLSTOvsYyrvo4P0zbuFgE11BBz6g6JxeS6FdbwRh\nba/rEuNz2RWrx9zkkYW83WWi5uQ4cM2IDmPsnMxeMNQ1KnDFaq2n0l8eLsals+eNRuPAQ0FhKSLK\nCj4eu5PzGDZn1lNt+GcHT0Eg9Ou+OSUvOJUaRKxXaoGyBnE2+MRtnPSaQAS456j7p81t8KoXO5Cv\nDhuzgO+bTR6/a9YSliQe1O0NgA5KpwCNLwmJMkwTDfD0ciw5MC4/sdMAXjvn0ULW0lMCloqSAk+J\nGbR1eSmgfcSsCvmNi6dqBuBTzteXwMC28azgo9goXR2BmI0l2H4LkdHrPV9kb42go7KI3rOoculn\nXMOT6nFFJtYfjBOhy8xw40Q0vTfzc/F7TJNzfQKiaeJlNJM2yDDmVZvQIrs/9rxdbhbAtHfYLKWC\nEFL/fLb8BVimstaMrTEqj2S55mjZJqEr3LZrvWsWxs1vcDIeedpb6ScNgj5EGC4qkYtYxJhOGNPQ\nKaIpt5bDAs5mcsooxUCUhStVJkM8ZT8BaSzPqzPcDiKTRaffi/7Du9IIEvSJp4mGG+9siG1JYmyW\n1q4wv6vK07fvPdNGRddYZsEXXnZ/Qt4/7yrT0UzOY4Kl+jj9zUhzr5uyEfYIqGywhpq2+Ig5EzT8\nm9SV6qGOxEAZNfypKmZS53J2l+IbefxrwwsfAmv+cFkZ0ADYLpbtvCk+DNL3qhNBPufCtNYTy0AO\n5vaIg850QboSQLT4gEHyOrdBB7CMIjETVaqSRdpkAxhmayr+ixn6aOaBbWOeBL0+yA3sUvcrqm01\nGdLuE3gzJ//up5bwKBcqgWozWMoXDqSvPc/vNjEdphOXc2tCjUt9ha2jG96YlNNLXERlEt0pHVOB\ncmoQKq0i2S//wzR+4S3N8DNIQv7QfcvY3jSTXHkJBJC17w5t8h1qkxePmv/azeS+kdi2EfA4wl2c\nr9DwixDhMjMwHEhxL5Tl8ZpUhRPbzXzfhTZyya6svwm2TzheGltcaEUxo8VoQWNk+ZA/dOEdEWum\ndyJgUYUOR0iWBOYm5+AIubJwze/oU+UFlruHhCdQPy2SslYkZaRQXQx1QVEVJFSGlpF60OgMfB7J\nCJjYJRV+RpebVbndxOs7qi0Nc68q2QafeZhG0rSEW18b6eo10qKDfgaPMzHkJMwyQEAkiZIGPyda\nuQWmvh9coLJIZtlnsb99h8nRA+SbJArXd4lh+aJtVfDEf52t0EV8Wi0Go7H7/9AAxpgdiLM1biM0\nIFM9+PeepnpyhorQzLAo5SFcisr5C8RZFBTmvOL64BvbAgT5MafjeIOurnpkdw+wnUY6EV8DYzCJ\nYt1XNz048oB7B2Xe3pMSRXVyv33GVQqU2SdR71kQX2epVazru/9GVxQC4ZZeWVU10i5nrBfcS9GK\nJIKreD8m+tT2pn0WcHQM2L9STnQtxVNrr5VVeYgTWVLqZCJK8+sIhvlrvcCPNpDU2l0vO/YVdHSJ\nVNQWlPCdl4Zva8Nn4YHWk8B32OvxjdYGC2H2A5sMTnsjZIGH8drNuTzQYcy7r2vEARFtYruD3Fjo\nkq/5RkKTa+oh0M6xH3RU0BHjUgIID/31yrUeWgOFZIMJUiBZqC6P3+7zaPk0wXW4B2Pdi41uhSCF\nAe2XR8oO5aFWddW4AhP9o2aIswSjXu16a06C4SQVWQhLqhtR+i3PZ7nqWSW/re9ofcY7q+Cy8QZr\nsmd6hbjD2hsjJoZuWEyrVjJHoKxVlfija5tuYGiUBcHsr6QmgbeF8ZIJAMGHxu/jonO1MN/SiWND\nbHMGPF40yDg+FCds4QDaphrggRR9zWwQH3ZWd6N+yn09XEAeoBN+QkFOm3K8W3+7YUMHuii/OWtM\n8TGOYUXFyOHiOFQgqF6uhE1vJut5LdmsTTnHKWDUmi3eG8pUxGIehKXef+uM/EJIoPvZJKDCcezh\nRMSTldA0lkFAesIF0e2NdDCdfG4DivNzNUVOj32BMFtujPrd7JjeiKq2Xz0joXYixT4Vf1pjBePF\n4U0SC0ZS1MKJscwIeyt34AT5BwYKGxaSMHuFe1dHbArJUhcsjFV8fR0Xi467qX1/j1SOp28GCVqD\nCcvEsH0fx+9cs14M2GA+d2DQQwZPa3FHEfgUPdewkgdca+rql26/KaVMAO7Az6Q8DzsBdgYO6G0N\nCrbC6APYAIDHTLFc5jCHGYJbHSvVo61GaRmF3fdQLJ5RmGy+DE/XVZHycurbolcWfEHjIXoGLoLb\nESiE7KBO6MSA3IyOQ1aBAOsNMirsLa8b4sgBXZOkkanI0E01TRAsRuLkr3bFV64pqpUp+hbw8bUh\nV88YrmK45CtPNfXCKqf98KhU/vXQ9LsqGZRfEy/Bu6bIXNnDbRob8JrV2ybyadMyWSCXq7Tv67b7\nwo3ZAFHe5kQwvART5Hsci4o8kG/J67WIusbaj9Zigc8MT4EfCewyOf20Dd9Z0PEGwsOA+toLZFA8\nwPVIPPMMBVuNeLhb+1e/fBobRLebZenEvbgMGoWN2GW8St4eLWKLohcughEX2MkpmY/URMwUbTzj\nluIApCvFv1/KC+b8SNRcmSpHy/zYYT82re409kfcCtTi6TWWmUmcJ+TZtAbdhfsgAg6PkJIhZ07+\n3okT6q4ae4O18x2kJYwYsDeluDFWg3u+ruvBwvKbDf/gfRISQeEBtZRVM7PNwz/nkgihYYrSUU/Y\nZQCsujMy5+1Wq26kmVaacm+brYfQWdCiedXZLMrnZ8afsNO4NFLw+LzGirWAoMcKsUlPDnWCMLsF\nG2ahJELpgOCWC3Usl4r4SfWGoHUGtPHlP7h+lm+7UAFl1Ar8lo6RRMedRPKUGcnVoaRSJmnP3HTG\nvNcLMlY5TDN3j+7YqTJ/gfG+Gnm69c3u9YHavXKq2SojzMwV6QQCPrBdMiWaOt8ZlcuWNsFy0Ljv\n1E1WvtHX+cm5+hPfGtlehTiDESu5cMXOe1uhfTgrMcOXjZ7MkB7EPVyzO1xBMkPzrEW8nr12SLOh\neoiMwHbPdkV9ylSiuj6yPRSHmhDrsyNOVmP4Davl+ecXle9smEZkHB+iOpYPR/WgH/TVLBgcIb0R\nhcTM9290ZNMbOiKQ8hEFA7or2CSFULAVPf7mzw2blFjiN6arjRsGp/1XPTDJQRuK8SrTQLarbOSs\nnfPx7vhrwnER+R9eL1HeEtyCrC6dO+U5hcXaH5GCXhskTU3UA6xVX/reEhd+0QydV05C2Hb3A9XZ\npWkYE3iwvqbZnjqajTr3i+5xSRFEzUaafJoUrb2eYlY1HOewLpBMEEs3HGC+7DEDSvKbQX80Uw5S\nOQ9A71J2/oDlz9ROoJ9iSPSrwISJjrO2HZ+Mil2dczwR+7OixGxGL7l+8dnlF0mXQnUsu8BtYJZh\nV9/jWyUkGDvjXUJPj0fAaFXQmWe0bxf+OrZWoVbQZ9wZ8+BoG5uuAzCK8Q4Ksx5go9dvZe5RLg0F\neAfsVBHBQ1VJY+TPQLOWAtRgXAUXUD2dMiZqTamSrH440SbC+AkvJN8neOZ0UKube3NDtG2vYndB\n40RjHSeMMdI1ilpA+6gftUEU0h/DxZ/lqorf1nJOHU1nW0xDS0lVy+d4HUM2mGfxZzu8VjMDqzEp\n9Y7gAGD1HXjmFbEgQRTAwV++Aoy32EBy7ZOUpJFd8lItzU2GNmNx9XQ4+8yb3AGUhyW5ZJRltBTF\nQ4TcY7ogbB6bsVFl94gUDme1xem+tw8eqMowpJiXe7yNmQy/sLeh4fNpXUs13DaCmsmbc4KREhpm\nzrttgM0+A+gSjDA5FMdJEn8paOH+RzldnUCJf0sRaslybsTaplWiyhWHqcXLTs1or/elNCM+hiuy\nbYBdqiPvaPFG6M0MULuInUl29BG9Qo0B8itYvsBJAdqQgysUrIZfKOms2AwrEk3PEl6O91LphELz\nNNwVO2VV0VhhXdUsS3ub1nwzmzxiaIby9KPbidPPqHIj0cvTBmTl9xx0Zex21Osuxf2QA8xV4wlh\nmZkJj4Qp+eZfc+ZL6WeANkvmz/ZJauGrKlgtDUkjHle3wHDJkTzLTajqAdCapHTZSRWbgSFYKda8\nDJcmJp6gqlCY7eAS2jlqoSsCgf55B9wI2w/u1OBL5LdFoQCq/U5u63bD4hT6Gv8jrHUJmbjdjgxq\nnYavvdp86zNioMMZJryCc3erfy0P9qNE2u2Zo7sQ/SU8h8PhkBBgod9kW+P5PgXfo1BZWeukStvY\naIeZiWAM172OyD43JZlvNeuxlJTOngVYDK79xbRpT++pwbdxX5iqhbkYQYghUHY7xZd/Yy3Gp283\nEZzLWiHFuWcT0IteNCWnOWqGG/d4CVmMLenUSqKYNyWgvpH/PAahfZG65k82gR68oSdMeeFk7q23\nBkxt9GWdAQNBF1qBQbvBAvYB2vKwgRkiNXEPUKYrxDRIxD5Pn4ilXm8uy9+DwwuFSQTU7keeNdnt\nEqlIocrPN+aGAmBeXX7arf405ztQ7QhuBDYAOZrD3hWa0Kv1c5CfFYb3nvLRimSK1BTU7wggtVVZ\nh4Ls2SPpClkTJCzx5oIWmjJNYbsMp4GNoWBfueNJuLoxlh+SbpNgs+sZqnpdzGtFHXOxsInux3v2\nPwJSyPMvDz9yGyeP/LYlAB0MGvVkUxmzBTICjaP6rUgIXKqo7KkH/TaZ6I8HL4z47oFV7JogmGhO\nNSD8RvHFC8MZ72q5CQKorVuKGs1f7IAUzB42ciKwYOpB5MUEGOroTkAGGeYJiJIhOCyoTkPlWtgj\np+DHnqu+027ti9iCQ4v5EvAikMuXz76QANd2aC2gQDfRjqKwjvzcyT+uAh3nql21AUIhdkSB1HdE\ny7mEYJWVhG4kDsOQBKX8n7/x3yt2G1CZjbBA3l9HOIzWpc6bDZ4ryVfMoY2Mk89RDpm4DUC7ogzy\nQZsKtDmpJtXqXUQv+T/G76uB5xjlS6XTi7vn/0+QUHE0f/q8Tlc6rjDHKVmXDcJosG4UNbqSNuPV\n2UwvIpewHPXKrI2bnSePxHLQSRB3tZcr1CMI5iSc1j2DfFj7yOaHXOXwQ5CxjClO/ub/iNUIUrT9\nLcyK5fh3QdLPegX2Ve0XiNaNkVAd3ZrpbqDoGFyiP8PeAKiVsswAPDHGxuKZHQaznH3IH/QzEHbs\nNtLs3eF94++dg8dS+fhr5er1BgWQjT17cDmNzJkEH1fpD7iN5/CVmuzKXr2qPMVM8Hs421VGKplX\nMmpbKw6rt8pIpuLRZ0r308Bcnr93AXvuibq6pUb6NVBZhxGYYki87Jwza5PkVL7n0fMe+gQE4JAZ\n52tTHb+lZyB1NW6F6PUd1ljjqSc4kdCrtCzb0GLuWciFi2/MSbrVanZa5OdpPwmVoaN/TNdEOMVi\nA7QTnWcSPtToWwN3tPNkn3h8wHsgmVkZRr9fk2dVyZrXz01azhC7Qgrh9gka8IY2uxQRwU0U74Dr\nW2yptNnTPTeXCqmWcTNy7K9Z0iNsePQH5zV8Tsk3J3gFWzU+wVZ3NIYXMr0FxW4HJp3D1gGpW+o0\neqbk1A1A71YEXniafVPXk7fSj7tSuXJzluBs4G7W/reUzVCFv33pm/uZxBMKsqPlTbDkOmjz58Jn\nv17p1inHFuXglNXGNoPgTHS2vJFVSdzzCVphe8hWc+lZk6bVMvVMIYNIkQHUW3FmPeVl5o6U4Wt/\njji1D5c7S34bk328IvBzunHAYrGVwwL2iNcC5kvdEasTUutZPgPY3yFAJqmPM2aGfwEPGIYgSrW7\nmQ9lKLxGxBIH9T0n6NPm837aIchhjziv3jb04z45a3ktBTNMA0oZa7/1K8/FV2DKdWcgxRijWuFZ\nvWU4B88KdmCmQUaj1/B8km5el7bzsi2rmFhOyMCRRo6MXzFy4rO0kYHOeyQyE6UEQgQSOHi5Mbhz\nhPO/RlGqEPxTXi9wlRWFJOkUtn7JWmwLHMN4NM11z69Lzedm7YArMdGGIzEyDzYibON/21CuUpoJ\nq1pvzjg12zjohVmUD8zMJGxH+Yep77GwCY5kGwEhkYZqwAshMLS08/9atVVvl9oVZA0zqkDQ1hZe\nTVfiRPDHtDYDercrw6Lgl9FVETB0EjgmOUY9bwjnY7jp+6vs+Q15eq/ec8e0zOT5Nu9uTO+VYOn8\nAUy7mXM4p+0tnj+ST8yqiyx6T19CrORnBFJi+RGVKFYe9bICXpTN9mfN11qyG0vTZHLp1LGiHQ6V\n52jtBLyTzWYeQ4urJoryZRYZeWdL/auPTkLyWA7+6P8ZYC6xuuMQ5mjiBeNM49okPUT8/vdqvZbg\nMpX6fpqisQCIA0k2M86YwKQ+r7imhaY1MAxVSPB/gQUxDctuNfK1FY1yrO+plVXqzQUWW14VI36U\nz8v6m2dSUCRmOkTvPJguh5an8575zWXiYPTUu2XW3WdcP284nxUX93646frOEs8q0VUaSI9Ghbl8\nHSRODKdDPTXeG/txllxFeskxdre6N63x46i5LqNSHmXHb7y7K0PAGcnjA0OEyuMGsulBPRqJ6nEx\nlEtVFO3wCFY6QKbUqfHAMxHQ6Hk5efvMDMVol7t4BqGAeY84/2jaV43AKJ6RW3fkHVFI02TOi0J5\ncRpn36MNrBYJAAiTTgnjfM85DXIeLYmgLlyHrXbasruMYfWY32GN2DupkBKrazeJ0C0zhHltljAt\nKl025H5C3O9CICZwq0q3StCRMAN9qS8lWaeV6aO50JYLSDC1HYXZrWbSqbKrBnyrq4g/7ftl0b/y\nNPb02k/utC4mAuUVNv2VaqwS7Cf/uh/fb1Sz1VuAsMrBp90a0+v6tzhBlG1dySolOtpWVNu5s7vf\nb6t2ljddK2i/iLGxnQTQG/wBTueALq8cjxAv5FrBGPLQP99mVveC3cTY0QSiZvFqEybgu5ZWxyFN\n4LGIdkpl8svSqsv5I94VD0HtUmkDD+0LlTWJvK43tqLSeE7P3ujQOAkZH/sPe79Y7quy2DtRulLv\nsYV4XwW1R1b1Vj/GeSOUMk+WdWTzYHP0HVSEpNbMO+oUzcRmLyqpgTtWOKpKh1o1P84GgywDAExZ\nHHNI59lFXL8C5Yz+Ucke420AKpHlq36xtBxNYkhkhWj3IM7I0t96Nud1UGTadfSl8BYWfctvFXjZ\ntal8z16VVYFlMvWWsqLmZPiB+LaTz7llQAjxdPsRTdRo5TJSMca2PsnQWuUvbWfSU/vv+FvicplQ\njTct03vukdQ9hGMdgLsbV3cCkpJ7z8kBDIfcGaMNeFqScIKJFOjeqRMZohELOF7cRnyhVxOC+Kkb\ny0xctYfJz7q0Tz6nj/yL8mh5xTFp9iObdbGnlFo7PEuDvdl7TXLGxIuVU2txh1fYe5ljp9/20JdY\nA1zWobU/3GuPk8AVeBkflm9CRpykaAI4VJ272kMwVgbAydgoom31jzHtggpFouO+dLU+ksRCcdbt\nW4Skom79kr4IXAt0k5N15eX8eiedFyPO6/8t+7ue8ccz/1x3VYufKClup9fQzzuJbVQl4fO66TXT\nQX6TEsvxC5SZvGB6DNk/9nQVnjIdw0hsag5Hn/BpsxOZ5MC3YRs+P4quuWR+j8kS89doinFGQlPA\nBpZDoFhtKBTo5cERv6ufwX8ncQKOSlYD1P9M4GR+d9S9Wt0zPd+GeAytQiWs4bOWYEDgTch8fGCx\n4IJrNejGJQ98t9jkHpREHm0fsyZ55GLO/I0LMkw34iULlmqQrXvg0aFjSTe05n/4cUIap/a3JMvS\ncD7f5zs5po82Cw5uf6QCXigQqpeTK4zOy4De5h34I4dQNWrddR6A9O4Y3Wl7ozQAjMJv6FZqbK3A\nYK7aGwj29NygqdD+2OcdZjJPUDo6DOIjF2d4QCcWmoWMShYr/Xr48FoXofqqNyk+2YpUZz67JBic\nB2vvV+D9jimkTXVOb0GMn5EmV/hkP/V0KRr1PuGp+0wcCmXvC+UZjw2+IFo4s4GF7Gi6/jaZ2ihH\nLWq6poYxENtQDFAFDDYYiWFRX8yPPID9Q7Mlt3rKSxoJLWyswN2q8Tx5Tex1CDPm2KhIA2xa8D3L\netDuuhv2l8N1iVmqY0Hn/8Q0XF1cyBMkQSxmXqFx7yirSRZQnaWpyZeQRWic6MAJ1R9sZs2QGs++\nThGq50F/anOL6rRzFrjxkPofPq8dz52BGrKxdSqspSprOMZIy6nVuqQJiCQe3WgvE8m7soGsBHbC\niIZ2oD8gbxRKBLQXxFjwsNWhQQSdEUV7e6kCVo7pyJUAF6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Ph5PLh85zBX9vfbiuJXdDA\nFcV8QodXskx573UuaILr9G+O3ddIIqmH+nY4JFpjABPx0LnJ+I44ztW25uIpVRdNKHhO+KC9Z7A9\nfojbTs4W6Eq6nHdocmmat7Yso09zz5rDQWpoDRVoW7Tz7fzkBCGxmSba0yMkx/qTswpyn1axJwrq\niYNg9VVBFJdhTlwKYHaIMFgMy3bpm1xKi3qtRLqaPcYNWBmZRQ6ms/YKgv3bTFzPt8g0coEcVDp3\nyUWwZvtFzlWmgYeATpcjcIskxO97qZUBmv3Pzdg1LpMFVEfTMbZrDtC9mlMWfZKQWt/6Wp4K69NG\nCoNIZCUtrzJcNcflDBu4A7RQeOVGz5hqpKFXzi8K5LS4cG5/v8YjZqF04IrSfmMTDYp27iSIb6Jt\nSQxYouK+6eeSs61M8Qsa3jU/62lxVB3gMJvBYKfhPZ9KJU/Ck/yhFOKp1hIGSXmwsA4BmzH6fQ6N\n9IVHSq2YxkuyTDDquUnoVbqwK6lsklsgycICjnx0wXvG+zxIHMSN3yZoXeNi057hbjMdUf3NcEq1\n5FREIPmWhTgutFCSC4u5QiO0ExvFvmMcb4sxcKbK+0gYaH5oPi6cJDLy+YNJ9RypmFGExfo3cyHP\nDBBliHPNQjiszcfxIggKmX653Mzpn6fKB3UPJmWfuBBK8LmMybljlu2KUx4IuNfstPXeUVxKNtxA\ngGyJOvrtXDM87DlALHF6qi91hghpYqK+jFyjElQyycrc1CLyUtPnfBLY6imByeMJBeKMtrHf0K+P\nCuO2XPJzX4wD/95PTBgxZycxsmr9hK18inSzczps762HyfdF/omfxTPcQNq+NwUIQ2qkNN7oHsun\noff/DL4Zt53xHBSU93fpc0AjGeRWzdo7DTifc1rYtVPSkzmxCc0fWrvnshRtTxqcs0/ACUbkthf0\nBrxNqBvlLlenOwBCYqh1liw4rYPnUloWa5A0EjGFtHhXmnXNNKxXbtvw6zr+6YYT0YQzNgMD33ip\n0qQXS24sPXRVZR1YfEVn+yHNYo1oTaUcHgl/TAJtHrtGV5V8NPkJnlKrXLUwu8qVYbBhNk2vvkOI\nU8qRtFSlqRIPb8T/qQ+U+bSDJR8iynMWucTnqxPjp3vKfPzdFS206uxDpATSI0Suc3FXgSSoMMNb\nATVuKmQmKsFh+tLHJmwq/XbkxEWHJ2x5M/HT1Wc/jOKQ1M0EeQe8tM6a6oHcIFGmWxawtMHKHHlt\nWaeE6PJMwrOhNkoorc+72mos1R3KEDl7OGTGY2tcj2qMugo6E7LafvqsqgJR5CGi7mzj8ZUKhRMM\nrDzrLqSJDDjUwKVqeJup3rGowgHQ4uETCf3BIf/rWqeB8titImo08GLXcVgKVnryzW1zi1wpwFB8\nKawFl/4J4Zl7D9ENuDHxx1eN23aJTKj1f+hjt/ej+1SijZwsJ0RhpWb1gPECL5n1NXMe5ibq4Z1l\nNG890lo3fdrgdvDc67L0vfkD9mr79mvIVmLxS+S9P9bvk4SBjM1Q/EChu5cDY8s8M81+UJmDuai4\nUTJV/of+Z/LO1jsm8Gvi7eN9G06Ytbj3EOdFuZBjYZzi7rowjUhB9Ro0olfNZTF9svWa5UeQvB8n\nCyo5N5NRd3LMAdFiV7wWdapobpZWLc/Ea+9T4k3/vA5rL312vdiVM6EthgVaQUhPvct45bXlo5cZ\ncgdk4z8XGOgxDeJEYrjqEc/2O1LIl6nftR7Q5xC+9WYUGouPDFr/EP3M6hXBkTZdt8eHLWcTvELO\nu0/xLu9Ic2jrUcRBCcRLAB4TuB++5nU+o98hZnVSpQQLoVEGdDIYeHIv3aFxedeMs8npblhschZe\n/9eK7eRlzzBgJWbvkmdXws3A0eJicp6/6eFbB2zFmSpuQLnqm2YKbK6PVOnA67wjDRcTCvXZj61c\nnZPfYxcompwks4yI9JKyPmusGyKr3ieCoDCsN+8h00NjNmwsu3YAv6pGtCZTyyk4h2n5dNiQ6L8U\nShk75x4PMiRMAyOp+rico0fq9m1ahc2vGT+qY1xX1dpjTLh3lFUmd4kw7TYIDwGI/iWtOMDZ2U8A\nnSdvorpP/mxb1u/Kx6QazCPkGwIUQx6Mj5nPt9qeMd4XGUtf6YHnnSvubOXhj0ZxjlFKfH+3QH8z\nvG88rjC8iJB2g999IVS3zAkGg/3JXBmFPUCegSnt0BFWwj28zl2/lNjKbxRYMbL2oAGeja2QHwLe\n8zpj0o/uNwD4LZ2fuw06RyUI6hcsyZTkRuOhm5Vrl4c3wHzQQb9q8h7OqMRTR2ekgMOvDSxTK0H9\nzRk5e3SPbll6nvYdiPVOx8Axt23q9wQz+ldAPiHXbVP1JHZysxP5YO1OdUJ8arYGf1/ouBznjo13\nSmwqYD4BF4zgVO5zB1yDZJHCckMj4F5DvpXh9iYXgLTZ8kHxaOAVmeoAwE6h2oP90BxkGIMVCl0A\n8BN7sfZnyshFQBvzJsrG4f0WiANqaHle8v79lV6yitf7+5t9HhIMz7UTR/TkhQPkNGXQHdlj0dSm\nHOZoU2r5bt8gzjfI6yy+l0YpNx1x9Ahgdcy/za7mrzcp3ARacCI2R4Z+UZMV67ayXmlVPF+fbsOC\nMjEwVqR82zmmkWLGdhw+Tfg+7KHOMY5MKGU2LoLn2ZZ2PvOlxrI62rx+yz1sXYi28O1MMxpVAZI6\nBZFnwLJcoklaVtizkk2FzgPBCWUMgpjRBLeL3jvK/U9kcW1s+kPECCnzmyZC7BO87bJCbhcviRHy\nkyHZwHt4Zk2P6p5Y2LiAV2GraNbd782oEP5dCmvwioJ8djLsw0qemWH1iKktnwrWHk0D+pluBcTM\n3iPwkKNd4dFLoi/fSNwA9f89Jq6Qa1AP8dEX7tHGNYGLZhNCIsHnrUVtqrb/eW+3BEhnDxGW+cGN\nYmrNppUkj4myq6EZzt4siZFkXwQMUk5s+USgtB8VGPr+0K8zZ5I0+/zj6mh5ypNqq+Q2Y0hcwHL9\nDL6dQ7b5iQdQ7TMV6SOYqLtLweEjr+YIL8z6ZqP42AJ2KqsTY6zP/8qUPsuIsSdXrRHhDV7+wCVQ\n8C4Mj8LVMvRziwTC6Tpt/MT4DE72ikdmro87GwqCeWLBBKq0z2VNeMgMw8TiSYJmluiqUDht2gzo\n/z1kEC+LQXdwRspd13QQYdi4r1ZIAuw5uwzUEdV5+2exwBysctjMUGdKRTC2tuwZUXW0LUN97ekV\nz+w6KjAMg+1eYYKWNcJ1GaOK7lslVOnNIJVNlLtgIIPVfWNZgjQmMCNLDtCwQt3pwOzOvsRB1IJO\nBMFImAutQyO6X8ZCrNK3VcZx/Cz+rmGgkzIlEwpxrBHRzC/oWDn91ySXMvOj87JNySlUvyWrlVvo\ndu5OYF/DJF/oMqvb4RAsv93WgJXB+Wi1yrJY/kJYxwLk8rK6TkUmAQKDoOdgGovXSwQoULjxee/2\nZWWsC9afPfVs99U+6ITseBF+e70DQR0PeFL9Cb1ns3cTlWGkFhpmQDdAUw8mHv5fuSetNyxIzAUY\nyV0Jm6oDNcLBzPGZ4uOE95F3YhBAffzSYgP/+oGGlRTDj0Ih/iXNmBqLqofefya8KwB/uOg+ofk9\nFcE/NHDWGl58styE/9Nml5HPkqLakLFdFgxTvBBFykIHPLsd50rRzP6OxCftWxUh3lTq/Kheimif\nrfKtNOhfF3RrviwMzrOIfd2+QcjNmRYyJjqsGPCOvirkpTRhgQbTQwMdATfPFpuaMXTf1GzXL9SN\nhMsTXbTm7Cj2Kr1sEjkLvn3KeVFDGleB5lx/GQVvLeW7sHJlF5W8CDYU936kQAOk6ulb+Gd8rHmN\n4XLfot0bkSR6wiXbFdiA2RSpZzidzWlOsg/ezAk30D1JXPWOPw1dr00OlmToz2aMtbznfz+1btUM\nyQwhaRnBvuc/BV3wam1gWwoXMXfP+DhYgvIc8uZfzZ6InaFlI0c00p72IUosk1/S4dxqSbV/pHvM\nGRcO2kl3evOuxYN3lAa3G1k0YwuQi09lhLcklmsNyFAfxIYTh5XZKbpZF9Iibhqe6yVGteP3TQHW\nFPxjBXyJbTSpL5vrOwF364LoihYHwqjwn4CQetqzlWmLgzMuRoFTbZFRugsvJ+GtDNaJ2m7HDfP9\nIPeoDF+v23rqqUrZDwIQPZFiS/tEp5rTgekSeUs7laKdA+mptQOv197b3QR8Y8H6YcKLVBoVC84n\nEJ4RQjaN/pukrO/5gQ3X33yNSY+k4AZckLlBvN9dO/bowxTaFGfHZOluvMTMWCuU629XtmgVQhpS\nP2Ei5sfuWR5XT4m/fK9U9kjRowH7VlzkAxS2/cOIdNz+Y7ipidyZkl9L5NPNbpWWu3Bpl8DG6pZ2\nvCURIdbmnMQUZnCLxr21kylCb+i+y0VghO7T4OstYRH5rv4mVWqxP9PGEvcRIfBl5CBZY53559HQ\n2hnPPHQBw5MfJRzUJ4HzTMcfhTtzoujfP098USnQ0i+ZNOZ4+2kUqDnYgjHq5ZnSu0MyLS6tqJsN\njRyFzaRPxUD8TeasWlrs2QHfMc1EEzo7ZUrNgNnJqtsd9AXkE1xmU7hWtrflS4naFvgnKT80zm0S\npwJZ9aad/law0N+eAPkG0YooJ5PZWXNQuEJDu+AYcRiw82w1V6WtG6pQnz5HgGw06EFu8ZfXQ2HT\nKA81qbgzCLyvFh85IPMpOvi5s5Ut6JXoWVpM2LKxHdg8A+GHOHOzwAW/A28ZBVH09gZe6v2xTI1S\nJYmYn9gCBQBjkVa8q886kuEf7HhA70EaDApbMGmTmmLjz7uOeMAgCncWj2mK4+xKosG8YzxPL3YQ\nMzUmr1flNSBj85zf5MiBG1wqHgN4oLUvyGdaugSfytmLyB2ZKdcYZfV18r3dJkgGpDFtVynhzl2x\ngSnx2eznWEcYhMqOZh4hKtvl5rLGEiwePqGrtRsj7YiG4Lay1Nhm+7Gk/xEyZNWVEjdUJwtKYmao\nl+dBDV7NIjpxHtzqHbA+7PMzdJCSqjQP8A3yCAMOrFt7klYKHHKBrxtthbd3ILpIB30ltzvFX33D\nZTkX9QKXvKvC1f3R5g4i053CYTecIVvxsJcLpPidhDmv8W1efL3UJ1OWTpqraMvwNofV7+MjZvsk\nMPkh3Tj+VYzDugpdoS5MTumdNXz+OYUcpniqEl0WOawIUfq3CguJjtxU1G2aQXrM7mL8ja/V5gWY\nyqDxaLBfDzV5UlawPO3IbHeYhOAsA6c4bzhDqJjEytwWJSqaG5NzQgd9uLZhF2KhciGMlRqTzqkl\n9mJ3Zb8lv3koKMRrcJ8lqCiwrNVlvBn91vmN7IC9WAas736b7l+GAzRWNyG44VTNCstHtpVFJMQx\n64mDpaSbh4d9jTyDinYHaU0nxVFYbTvLchlmdxZN5Tykxh0dxuA2B4iph0nBTJ/NermBJO1ARSge\nRBDN1pAVO8WPurir/DuQg7daCCpHBAAxZOj04sSREpGj31Xb0b5PsfGKDFW1ldb6vpmfTCidQNl3\nSh2Av/s52eCM2fLQZNxi0PLnSeZWzEbU8mb4q7UJCs4WMvjn2CiVtSlqP/Z+UD1sxx1771M94HQD\nSNyMchC62zsrK8Hyp5iLOmzxYHIWsEISsTgSre4kSK6qXGwL6ZB5EsUGBLrNoj1uYlJbvTmJVIjL\nEoVeoRwlgQC+s7QORfS+y3san620Q+xEWZ/jE2D0AckGqYbtvGvE6+AbGg2vUpDC4WCCYG6xcn1w\nAtBk9n9Ev/kwGs1iXJNGugSMKgWL9oMVelZM7kONp7gHvClcPvpSYG2i/9yGhCWm0RIZ44y6Flu1\n7/inKtdkIaULdoky4kcVgpZpfvJvqIMQJmeiugxVuICsc2ZBOgS4lyaATd0ZsJcVSIHfuWm9Q/oo\nBTV2Iel3mM3ldT2iHTH6cuqVtNcA7PsmwHw9vCwMzK64U9JXPJOX2n/PNKPx61+6I83oqaF+rfAc\nAMGBSmITt9/tD6bupyoZ1Bp5uyX+o+CGrMD5jXnuEsMj/W47lldYI2aghUW3sWpGBMGg/PUlu6PB\ncCVrmfWS/qQU2m97UAk7GIv5e1nzxv4dbgaWg5yrnomnyaITMGigbUqRG2sN+jUUN+ToQuPR0N3I\noWtqrDa7z8vuP2xn+Wzt/VMohbblU0sOSf481T52QevZSRqK1ZrHlddpY/Cfe8V20o7Ue4qmU6nf\nd8vcESfAPftThKh0kNcklowS/j5rj49qrmiMkL00NhSDIWw6L2LVSteHrCHrKy3bjkz3BTNpHSts\nJxYhP2UgCTrUDtUD3hNuR7ZGxRTH23TU3TvE+4fxRBRM42Fr2eRy9sM8vJE3mAudmPuEHtlSp5XV\nmItBExNwIL/DUfn6Rw0u72zsqIX9R4k0R3PFOevjeDskEG7V7YPy6IMwZiwPYBacMxw+lHhkbBxC\n8Qy43ABtAcDyjn+DEDkpREfYKv8RBM654LkDbe9L3UEY/NMYkm4lrY0357hedllIsRpIHulByxvr\nedE0Bx53jAAUQkMUA+fscH5yWUmyiNdCAcOF2SaTeUrEw2eWO19xWwputdF7dTKqmSsaG0MFvSLz\ngEpkehEgq79REff1zzpFPjWZHFPgVYJBl/LgK1CRdA/ZiRuGObRBq6s3c14iUgSLdaDjy9xHHU0T\nYJ4QW+5j649RzcmjA+8/I2LZviLhhgKcqb2QxqGgXDYRHU0ojThkzF77dVY/VrtdJ8+twAR14QqF\n0dITTKNpb0BVEXuyHiYWnTHGG+oihi/q6gmZbv3u6nq+fMTUu4XVgoi8O1342vgfzqQUCM2X3uMt\nEJMc99fr72rDscgStZrd2BO4RzfdVtNjOjRk0WuqEFPqiiPDNJ+SAwVcVDCSeSSr+6BjDZCNl53A\nH4ZnRoNQaEhR1b69QMX/PexSWA3oWVcCNX14HR4jtY9WWrf5NDb0buKKEPPupodXoMqP2ZJv+AX0\n1JhxnyN9xnbjBwsSvRYmO0RkQuH7tug8dZFdootHyD+07j2Zs3Swb7rK2w7GVy85VwpwW5Ze8tvJ\nkVD0EIMuQf9Y8n1MayUyoBJBNMz8LQJSLCDqcUoaq0FevjTNffP6Da1ZckUFDIuPSADb/OHNPWR1\niMq9DZboq4WGKT8BlavVMPvfpuLKi/hy35hyLCebatQ7ywXq82xFkxJ2Y6NUSBzC9Xr8ksBBWNa6\nKaj3Bzg6j39GT7Y8GGR5QTPHVGSLfSQjjS/PWP+RJNEXlYKpW734gihGih8e3oyvCUzD2tSmnGG+\nYZ8EflxidwjI2XMyLTDuwYduD4t1HCpytPWXaD8RJ/YYRANakdEXNskVsHO3VSOQ8HGsZF1MJ6Dy\nvKseK4lbrTsYC1tDylAJDEEhRVl6LyzCucPoboZHikSMtstM2emzuTYb/arTUm/rq5AgSj0iiGRI\n67PWy5DmJ1VuPkxAWLFCj0424kzxAc8p1SFkgJ8RMog0R4hlw1fyO/jPq200XubPKM0qRkVQ3f4l\nC3zZqi11PDTiSzw42ixtJnrSKrtJmvVohXxu1k0Dc1hkBqYNoItPH1EtvZeCPp4eis1jvQQhnZbl\nGc42oB9qWzfcpGlYxvRGVXj7i4axgMOlmtcS1/VXE9thwRFocjoWYtMK7zsDHYS8nkNBSe5mq9tD\nv6aEwZGi1TI30DH4Aa7uVz1dTfo/4QAoUYJ43LAm8onEag7NvTw+jMS4ETRXVmEuk7uG/qXHVlmt\nv9TkFM/qdnUVvjkVGRVTokCq37j+MDZ3m4vzsKgh74+8XvUgUjUZDIx0QtzdmGvvAz2fI54JKb0n\n+rlW5vundu54/+pM5ORFhqDWFAH1u8L5Zu/LfHN5fdoIqBfh+3E0ybzBqPwXWABGl0+JBqQ9EN4Y\nwroUFBfHyBk5BI0cVFyQGcyrhjw8yMZFcsZCoX/AFhm0vuvq1xhZ2rYwxO7FULVhT5p35zjNZwEf\nb3liDUKBnGqk+QXZ2TluRT/9fr5bvCAcGxzB5duNJvGL1Otx7SxIpQ1ej6gGoAup3Y+6r33ihWsv\ntQK0C9dfMt0hwAGkJE1YOneNzg8GtQJ0MBu2QyBfUuWgGlDudi3qy+3Qwd5qiP2skxJ6WZrxyPwf\nGoXy5SPwa/0BAh6M0T/5iXlhd1jBvuM8v44+zhOQ5j0aW96wpOjj/Mm41t/El/Lk1F7f2PdyrT3s\nSUwdJzM7f6rmyZiSnvj6DNrM+C6/o/2oFmz/oxS2EwXJffVH1UoUMAe2myeq/6tA/RcjsGypZNHj\ncdxupJAkTQD1HpcYgR71492Ko2qcq3nz2A0frfr62GXSZ59org1H69pJKmqLazLX04i/jEDjMpUh\nk2vxhXFAR6SqjMkFNODi7XiammnYM71HTBvv9XmzDY2xVUjgEr+m4YucfEfbiM3oOmwt4xToWq/0\n/BoZkhOR5EdBic7U9VEl//sBRsTVaEuOiT49rrrI+03tg5qcSBbvPO3iJfKro/hrZiRJjqx+OxNm\nXQgDetA4Hn+BL77aCQP25rgRuBFT2H7oBoB7khTvlvIYcqIbpQIXKG5mV9XQc08ZB/d8dIRkWCSO\nESkLDLvD2rS+vSUttVOikghY0jsTGWsmKn+qfaZQmYAm5ZQX4+Vdfvp03hmZ+08TQ+1PfdVT7Lt+\nOxJrJb4ZaMwIeidxGWfd3PClS6XLd/piYDMkMG6pqu539Dw5J/BX9RWKULxMKyKcDNr0axDTArst\n7ua6XGVJxEAtECMu8cqACf0qY4rndEyWZF8vzdLWphQ9leQpzao3p6Mf59iNovCa9PuUg6i3IwIL\nfYc5sfcCVEhjenOsv7qk4WUl4UTspmkrP0UB4KgzUou+40xLjZ4PWhPvhS05oew3blUxpLhYoOhW\naJgkDnR/lwJflGcVLyxHJVVAUsJzFGfRf0NIC34aL++9kr/hAM/jzADLyP6NGkOGDWuOtDZSwkm+\nD6iktm1SfJx4+b5fljFQEYb7BBdFCQoEieSEtSoriWXrFqhDqoKGwt9Lg0t/GbwCMb/K8A75RsgH\n5sSL+gd8MFf2ozFVlQeF1bImsg/JMLDy9dE5+eU1xvDo1c2t0G0xghEqzEFhOXzfWb1hVW91daMt\nRW6bLbpL+aEyt9+hLRxNrdk7o6lL2jVpnDtlsDnJ2P9923u9MjJaXb6XdADHBiVz683hOm8P9dXp\nQ/maCCLiTMzzMQ4LyUV/J1HTIwSM3xhQRJoae0EFVT5vweLaqOAG7D1Wj/AszRRRFSPR114L6yIO\nz5cu1i/cZmQVEg5O7G8S8lOXHR/x3jV5m28tJLbwv7gTQLaLq7yh5kYDJfZOiDW1bM3y8HxSZTjs\nMYtk9kZYaZ0V8WG7yXudH6ZbiwdT7u3ztn08JzzMCU1v3FwHf+6nJpAkEy8LW4Xp6H3KaIyWva1U\nDLyo7GnCCXdr7vmMY2Bs79reOGibFTrNnFwobo8hYgFu+HvFEpH5M3jFi/5pxMFQi6kWrmMD9S57\nfeZzUHnbdNyeFkjiBKRt/hWuYAO6Vgvfd/e+yPuHy6qMDqRJzmpuLXZyGYoQYnVXc/bkVL4pXJXq\naLRiq3dvFzFhWuacc9NMBwtIClgplt5pCA7DaWj4xa8qdgRjuAee4Eh8uh/8LKl8cCDQjfyioTfe\n4Z8Bl/3BkShGdDjAXiw4L8uDurYFF0vSvsXDEoHoS9vUDqL59b0cvu3tCHc+yscE3YTBn7hvPvzK\no8gb27a6hijojpFOh/LZ6UqDQhVUUDQbEBQV4pNFDQIDw6q9MoBOwmudQpxcXXQ5O3sez2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nE0MKDuVih9c17BMz6LoWruc8pMC6vnNL0CANdTkOrp9JsmwWlv6FPvtu/AQL8U9M6Q1u8TDPcsg\nwRIHUNq1kUOCOXpCtVR/l/LSwIgBcQVJRr7RoFbAVWh6dk/gxsAH7PCohX1fTHoLDqWamUy4/NYr\nTs5k5p187aVZeXVP6VxrhHL+rLkb+u+peCtcI7niEglYjYwoiiJpB9Jd7K41Scv4VXJx7Dlv+Poz\nuftkesQfdJ7Le5NtNCohT5gQ25Cj7/rMUd3QogUlOcmJdKfaFXvrKHIsrGp7CeokC7Wec6SkGRoI\n/uZrr/UqzuMAm7JnBHKbdIyzwT/oHR/yplZ0/WYRFLbfOkPAbZ0TIcXC2yI6XY3LvrhaT5OkQ89G\npEHCuI9qasQCpTXtO4yCJfhAdtrE4kvTe16iOPkTiqAdR9XCNSf3w00tHsE/LJ/IIgxhDtiIsItq\n2wjOL8Y85qpOBwSyR4tkCW/zbPJUTGccgPq8JaxQbq3FX5dyyhZ7rvqKiTtQ3+80X6Oo8KqZJpEF\nkyza/rCAtHey7b7tmbYhUGb2Q24nUnI3UVZxQkY6FCljTXkLlI8dz5AdgzotVXjPtdJxD2+Q6emJ\nn+nhOy6xRRmb1KUuZErmBsF2hbcFuop3CYGwuGvmEEG8IABdx5POnFvgj2Eoi8DnsHAj7AHjpBY9\nOdZwoUEfRR6cxwX+c5apDW4PeGnPv82BZD6/YNgAb9gJTXAGUvEoNOQ1ZT+TuCxMRD42qOQDaHMI\n4JNYE59BmA0esd0Pg0f/Q2/xoxIRIpiQ9amZ+7jzGOwZMyBZCnB2Uj6U6B50c+IO7qnEb4arTVWa\nZCBaw214WABHn9Xzi5KIDSAGNcHsfuvL+NXEWDB3brgsVYTJG2N7254Q68RW+PLlDME5mzu7FFVd\nYFqoOnr+CuCf2ugxXSP8hl4foIDXDm1SssPebxytWKEWK7Es3acN5bLgTTazWWO5BAazgNycFiQG\nXGXqVngRq2sR78+tOi+eivGghTF6CcpmdEhLWvaN4sUNXhSdrZrR8rYyT8mVBcXZiWt+p/17m3cN\nN+dMgDh3dGMC2uOOMVySqs4IrcTxXQusx3XxWnPdRYJmnd1FgMgRcHEgxLh95Mz9JvowmE2d8GwM\nTx5A4KAkg6DlGmTfoapH3vyaPqCe9iGEoHb9Ww/si9Y3MbQWn0hfAPj2VNA7nlWP/GHTxQpqmv1Q\nMP2/vjVYp6jalQDJAyvSvk0SGMpN57BMizpva/adpDsoa6LDJcY60FOLzOhCFn7OfE7tb9Caui8m\nUzH2xI3r03RtcD6FPWjmdo1B8T6NaNOXrtvvKV75BMCvnPxcfNNI/+GJnx0wZ4+zju65DU2in54p\nkiFXpur22e5Y5VSdw81PBn3j+KOHHZdpOVkjqc0AgOo/5Us6YNuu/a33zKmHCQHXydTZmSBT5iGR\ngd6BJ9j+01HnQVK753204AcnmA5WgELz1trS+UJEeg7WGwhJCDzLyfDTfjliRERKKb4fksogWc8I\nY8COF+2iCS8mbA1zIbHDqalwDyrmIxbBSG3ig3/vx28oedC49G8V6j0WUX6pbHmlb45kJLXn8yrj\niXcbVpkolSc0beKXoktHjalcpNIid4jsQlP8FeHWy1i5s/U4aKfY2U4NJXM/ZHUHNcuCaPOVc3yY\n7xJnRsZHSBy3lKDnOnNkW9LuV3dkGE3V0jU/eOJbNykIlYr3uUfQSr01v6F7B+zSLbvB1EashJD4\nuWvf0s4IZFE64a2SPJnZpaw3ULqiIAAUwJwcTPCasi2mE1wdAdFLs6a2kCA5uKbidhxTrNexUb7I\nRpa5VESovd0J75zKuOCe7PTqe0I2fcTVq9cR2vs/L9C++tPvRzUfA0vovf02WrXS9YvftT7dkvJk\nzl2mhjbVKSpC7fTvD2jiQswv8n6kHyWdV92TBqNQMZLH1tb5swRSHqRhcanGGQzK9OjZht4a+s5l\noIIE7SBV7dE+m48qQ91MWIjU1DJy2l8iEpuKqPKuKB6XJcDPTyW6rMEDbsK1B003r2LASojbQ5YO\nMiQGttcnme3zHBCKgClSjD7SZi7Pw3WgD/erzDbN45jo5AAM3/m8Zu3qDsOpyGCutGz+aL88vZOD\n37KJZJv9mJOEd6jeXGoBSsLZ6MhULD5+EbNPE1T9/5H/xXABX0+41ry0K429Lm/OAgJt5Jkxt8OE\nLQMHyey2bAvLwf66Np4BdxhJtSevdCDtvOzeH+fbH7wEA2rA0CVFlXZo9Oj6JVs2BQEY+3VkNcBh\n4yEWRj2Um6LQzqukMj4qB/C+lyD5aG1uc6jvRs7c7LNPJAzopc0yKVe6rwMiuLTdMlAOTCCK9QFH\nzRazfEuhQINrQ589UrHWS9jumNn+j7KEYd6H4G1U5hts2tJSOjZXBuOzIp0Gaf6mshoi1hi+x1U6\nEwKz9p2M24wsK46cYv0vjua4iqTQzULgUKlsmTgQvGPD4EJFq/xk31NnldbATix0Zh0bCCHQHDMJ\nk9+vmAoynkZxM0sX9b5J23YKgfQW5WS5yv58lY3BHG/0cQWbI61SaRWr2JangykcGH13eyFboqKO\n6azrlHaSwXiDB+aiviv3hF1DUWXh1+MzA8I0mmqIYOxPiBbfeGxZO/5A+Vqf8Qqdw2ueywG2WFYD\nlGGCZepQbrajeJ60PaZGqTJLxl84/wgOxXDibqBwiC5uvqzlKOSRS2KOLH55N7gHzh2ntOSq3W4Q\nvtHhOF7Z/Wmtpx+XfuFdDxGQuDzI9UW+1JtDCN7cs7FrRK0Sc1CPb0AqcU7NK4eRXnF+iqCWtUwD\nibII4mu6gHe5Cr1p/NXu1CICWTCNbHy7xA6LGywPlZ3x+Og5rUGVnZNUpqyQmqmvkTRY4uQ9s2Qy\nCrkPhBwih39M9V/2tJmhLx4HOpWT6Hp3400JOzASfPtOnCV82avdUYpsY+vtFcS6h56+HPUIXLUP\nQhLBTsWg/mbKDQHgQymfIN6C0/KVolNwGeIgQBsnGWQJ6Wdao5uqDxRsGyxMqtbhoiTXFw2aIAmo\n8/UTeB9MP5oeQVuRg5KU81FFmEtisM32/mjL1Mmg25Ldhl2s7mKHti35bEj5e83Bps4HgjC/A7uN\nvYtBktYBBat9GKbW+y7YTMnUjQF6/3YFUHjEIIAuOdIVtmYKzMQMktgLmdyHDXzfqhjKtkI9yn2X\nfj1S5S1HAZiSzrZzjF/COE9JZeoKjdakscowKDNApaEl5QruJcrmbCFoO1XqdtHzQMTrkGR/ph84\n/wYK/+npZT6ixPCPB9GkOGchUWIVyZ9+XSsiuMAT8Bk+rO/BsK91MmO22W8WAwB0ICn+Z7sdcQTm\n4rIcpFBlrtYR6BPvl4gDCVXr7c91BscEx13E9jg1y3AatJxETEz+1DRf2VGNlK+sF3fJ4C822T9v\nRWvdYpgrVK7RXnkMs2aQ4kVukNhOUs1crPyA29tkhMmyNdKWqO6x20P4eENxpRy273IFFicuMdO6\nK4fvbdhRk40w7Jli1tj7anwJmcgXJrRkPGUyyRLcrmN9oZRsrdgdFBr5S29im6RY5f9jE8AAjlhp\n1ANh9NexWFZY/KgySpApw7hlzOgrBo3FJxA/JHC1i/l1RS/m/AyAkqb+NDOWh0hK9URqt2Zt1HMz\nOvQnnlpPyQD5devw0JVUdwaLteFwZTUfojcU1l0eHBl8abimnBZ3/vCNfJuks2fDaFTEa7l2YeYd\n2qlrPqM8u1wLp0GGcvY6ro+gixlbmi/cqHI0OjNpifnA9CuIktosXBaJWhUu1EWTJ2UkwX0rCqgk\nQcpjGVt2csu3GhNbS1sDTetOVnajOJezSuK7fnsVtYtObqGdl+Uwe1CpQpb4adxs2nIkbh6/QN2G\nXVSlIcYI4Wx5r0dG01NiAg6YoEvxikmOktflIT5bvArzrcgiZns1+eEnmv/DyccgHEE5Zbvjr2OB\nU5m2QcywgWBJN3y66rt5TEt3gxflqbB8t5xgQ/7xhd9D+qhv3L/jBSsy1S84R+ZPjZeNkQyH/Bg9\nIHavNl6/a0ycn04zw5fds/vbzH1MWx4Wuuv3UFI7Oe2llTsNt0uiU5Ih27JRpK/Vai+CcCbj9KBN\n78VpvfYMIlEp0/LVIRfN4xTfiLjOQdqCu50hT2auUYl0l4lu5zp/3bmcrwVnZf8IPLLsaQRtZsYa\nA2CCzlDrcRW90pyvuecc/9vgub4JhP/fSLMqMk3DbMuDRk3AAC2dNuT0wdeNHbYV7ZHdLBUF/usC\nR6UiOUogppp6Z6UU+Ujm8RaTKI5PmbU9v5k+4xWUcfkvH5GYjhrMS3T8poOAhJ24HqeqgnvqMt4v\nAsj89b0mV+B4MaUVZvjU2ixnp38rvd0p8i1lhh4aoVaWsp5nu4EZth5v6hzAqCZjO9DOvxsf5iN0\nkvif+Uf+fcpLK0Nzu6MC8+JnNoeMly9L/VkjgrpwawIg+JEkr9hKaPRAJRBNsnTMJksn7/30pCgY\nVHcVb8vt+UKLfWWo5ebJL1hDqATfUfyhzcD3534+aprGO7TJ7qxAKp5F9iDligmYrukA1e3mCrFK\nYOBnWDIfU2sXe2+7lZbj2td0XJ3Hw58EOd/qrK0KudWaSNDhJk5M/CtXFBvCErObwXSZhx4m+oyx\n9JPhjGGZUNl4R1Fs2CYXiqHRkU0FfWwYRSFhyi2FUg5dZlb1SI5w6get1LcmAcQxkMy62vWGu+gz\npPa8x3fZdn9Q0txdjwxwzUeN6G9kpSA36qwElemfa3nzt//Ejfqzn209lEvcREOtqVFDtAuXHv76\nsp0mfP8mW4ED8EoHAG7v12kW6fIsSrjIv2OF7NrJpi4p3hBl+wVu5CMsOTjHK1wpA7+mlzqzjypL\npbEJeJ+CVJzDEwxUrs4Ib0nFoJ3rRGlE7VvXrUC0Hx0pQpqeqArQZuGpMlCYWzfvpY20i5u0gkUM\nI4SMBEr6wLrjdku0FDUSdufp4mcTQ2/PHEfZ/FomL+s8D4pjbGNnUjIGj/JHaCZDhwAp08NoG7MH\n5FKrVtA4PF8i7DOHWbzZ4ZDjch/3rdbkpUmOwVRZOxr5AqUkotP6cke3TPiIjhQPW9uLNmYpnK27\nC8I+l/ToAvO/Q/8uEE+9pApw7EQYAyOvr4B7neIKL/lijgb6ik5+Z09nZnx1HraiTdlt/9sPxuSR\nIJ5i2/YlHv6asmPYmfUVysW8hFb7Ww5eha549IzYFv4pbbRIHa1GAetrU9TAOfUV7wc0jaN4v6ej\nGmeuw5OdbghR3f0UGvFEEDn1+p6BkZvCd8wTmK0yAvQe3gCYkDIjPfXDjj4Msxoj8h8AiHe87j1m\nWmGeRNtzb3V6eoarCV19x3KU8etZE5Hz2BaPAK1IuePMPDUnwVfxn6MkuwJSfLkogUGCcSIUAk8l\nhWm97rvv/D/90O4ou/8aloypXzEJQiSMql/du60rDdLOMr2WDXWOvC+2qFmjDuCLXUC9mKAhvAu1\nsbrzagkFH/zO5XuCbr6j2zAXi+7fp7wGChalYBMTpD2l++UueG5fLYKFONRCZ1cTEXFM+T5ESgWf\nFPvaEya2fILb+L/B6d1Ik1U5BzQobtxzO9zjUrq/oyhFSDm5s7UZ+vdfWfj4giXUnVWENVOe4LCt\nQbwjI41iup9N0M259oRMx5GK3eW4FoEqKRN0T0RzGK+RXjUqQFKxzHswyYmXzjZ4w/23BY7J3b9m\nhEJl/NJmG02PnrbRfhBrn19VGbwNcf2kohXB9tZlXCxRZv5J2eTXuoqV1X/+O4QDVj5P+dRYgLeR\nyojZEeaQSVcrclgT8mH+32YNDt0aM7BMabhry9LDDEYUgDHaVdYa4qYjXI5I1m9W6US2h6bPO1n2\nWB8qSaFNt8VgJQLNKHEMhAF0QXEVCpmfyD1i9DBpVDwz6aFMYuxA3ShNq1kaiBO9iRWNplZarRyZ\nixUwOILS4XL5H6ru8Tk361snvzvOTAauCNd8xqJGTxjtqIqApBYVjj3/fGZrhUY/OYq5QAeO1rVf\nuPw6n5dYVMNIlSzIzggiKP7ONrVZZwvDNbE3PSXLrhitWODIKSLXXl8Gmms+HquaWnAge8EDNpXf\nK/291DPzF6ctStlKVsR2EV3PP6F8QE8WqAXfoCVY724/L2KEHHH4wJlqL0g2vNm09Z5XTB9zkPOh\nWFxOX92SEVSY4VPz206/y3+CpnG1qSliJ5eOlILd+fOjxY5pu48E5OJNDQE0SwaMCUHnmLpiwMuF\nsh/e7vF6SBKufSn0VBEk1Ly4eMkNGLCrdtM4v5y35YfNg5eYNuQEHbORi6fmxduGNQ+6ITcewBa1\nH07WUR1nqYykQdX6coQuQt1NUKwjwoXN71yrZEGWOi7f+CY6Y12XVLS5I2hC0vx4wVK8Vnpcv4iY\nXcapfj2zyHAimYqTzU9kqdH+P9wWamSwF6XR1ghmEP+i+2q9CdG0e5qvzLpGC0CLKgnqUH7kG3Ms\nKSUo/WzZhZeqZsZiSthWHSJbqp4zZmwNwpGglOwZo9JJn9n0ejy7Kya3vU9chJhIZ7i0V20UEjLU\neyYyXowFPr9ROnOAwy0ZYPldH7BxrIwlVt18eEWQ3cpHyHjaGpSmxMjp0Crb+VhkRDe6PQYHdax8\nvTswtYWWqp+c/qmPg1jfl7cepZZi/Ii4S2MHdpn/p6fv2a55NPDbsU7vHY9VwPRvqJL622aIpjwv\nDihFdWFI11fr3gQOTmvq+/nKHfucI9p+eRkmNpaN/gFBNhPg8CtKQjt15o1edYxll9GFLMXLo73r\noJtLXeJBcvJo6n5p9cwgiLkvXKH3XKjyg6zbYuSvnF9et17cqrDfjPmGY7wh2XQ6PSmzmF0LyFEY\noGPFtDF4Mc2E3yD/q5sf6EgFqt5cjfqI5Am2NezY/t6rQNTAwcnnkpHh+aD8FPY0qUzGKmjnJTuq\nlgZVIRZLnS8a9hqIKgEHvYUu0KdapJRtq/6shtpMc1ThoRbNXSPbbEakhKBEzC0TsMSHA32vy/GR\nOa6oxBMvkePSO9WDBMNjDxkkrxJ3MfsOAKeN6KCpwabsc61IOrbV0SuaYRuKcrxwrk37v066NznI\nU++lLQL9rga8lVXmVI2E9/O8U1bk4Kc4R/DsLt/hwUCS50SGkvVieITENSs9CcOiIE44dgo+hdIn\nZRqvdHNqHK0lbmTSQJsC9/J8/8fM6PvcYlVX5py7qE7AB2zO+qr8tR1UeqPvqhCbgyRpDaCWue6m\nDK6EnL9H2UggWSp/h9+/51ocNWxZ/vAuDFToVkJDAEjApAnx3xZTc9dLHfSyhBP3w7DTCaQgVWFO\nAdlETIn20ZVI/RCim/kHpxtbKanTO2+xII6ItAO1WcJzWRXnekZ6009S8PmVg/hBp0d/8ccZz2Fr\n1VmzBqnsVxV7YGrV12ccZpe1lYZ8CRJhA49Er59ajFeQ25SFygnBLo9M1M2NWZqcwbCzOxjnPX8U\n+dMgx9wg8GjzH4TqzJfgNjY/QEV4QNBZf9GPOu1iyXidfEQp4C653tQIZOGfg/Lg6JpBCQf41sWm\nsq5kbdX42GxWG2WY2JB8C9ubbLWFgMKktS/qORiinDBhyTlLeOb/lzcYplzRptgM/b6di+9c4m4K\nso+8XUUyL1sm6KB0S4Nsyft1I2FJNs6A8qGjOyWhurPsocyT+EyYxMW++k0/GdP6LVcb+kO0tiWx\niEO6+OeOMWCtzKQDGTtaERLg8xCC3fXpC81zVhrnGj5vDjQiu1EfZFTR43K+cxRN2gUbLEwG4GVT\ny1oEi2EQY95bkU90AE/UvRNi30go7YelA82WosBv/bB1GPJEMli+LIJrLoLNe9lIu8v1t2XdIK74\ndbKhtblShbRBnIqWkd44TGcLGxhyYp23LHYt1dyWBcCgw5RPlUjicYiiVb7G9WgBLzaf0pLccRG9\nGTkf7nYbGVcRWtgV/32kya8AYk3Ew99H+lSVjGxM4UzmW0bPWUJdCQfwy7Lk0hAFH0RaeyGfdJJp\nwSkkfwj24oVBp8n2dLEkJNsiSOdSdXL3BDxDEc1/nqZGE2VUIppREW0M16HcpPi2U3gPoRLph0sK\nhADdePKa1jmsrQgWVRyXy8ylzNPshcu0aHQpkOvKum2a4f21CQHcnhD2CyYWfJXzqd/qm85BJaqq\nd9mnPCcpb9LU7I/RLOgqcWfQfu061FABd935TN+0kJweT/+O5l3AyA49cTfSKlsj5JdgwRygqooz\nzTfOE/Sp2kf9H14tY340oV5xLq2pRsp3HwfyOkVd+JAkbMCtwoKBMu6gIKc/fs1aOv0ERClqCp+f\nEoiYZYIVfUrghdUe5nvSD4+oBP7D6UxfqiQ0+VWvom/ed+hRIfxQkeYzsWq12hv3+WaobNLfXYWW\nTrXT1yR2DoowZ+BC6mGFZWaiZx+nL8Pddn2OBS+0TshXmacyR5q8HeMG2f3zKCzvUn41tZ6lY7LT\nXB4V5X03EZz/CyrtuSbvD51Y/D/vsu1N9dr2KGnikpojWCvwYiUidkg6Dr26RoKfvS4xY9xvwXaz\nHrAAppUJobEdlCn26FnPv2E3xqsPa8dfKGDl5oOp1XtT0ljb30MpSPuebacubEEb4lo8ig6zBmFa\n/wPx0RVrvhuFRL0gqGtncOnGLrBV29Uz0cXwKiBKC9b+aJQ+kskTXu7+yEVqoqYK7lluoYbtNDgh\n1dfzp7O/BQAQpS+/FQdXd5HredpY44g7RbyobZJBmZUL0oGD+RKFqJIPKPHR3sg2TB8ZL5zd6ft3\nfftKhXPnarbRPc+mqJpPG/ou/bNqRiHaMyEgII2sXsO74KANkOrrKPDl6IWtm4Axe/ZjKlD8e5PM\nKKKdybWGsdU711+febJKIyQqgPvyKr7yRKqaUTfj+mn4SqmQR3HKFLmnrF8ggCxrx0QfzaYogSIZ\njaORowKDlsSjJy0YNe+PNek0aFiqnMhcDekA9h0mZ4TTCyqU7RnoNG5yaB0SqNwwn8Ibhai/V+KR\nMAfELaiDAevSX6HtFGXu2asgF5qoevKXj402Hb+yL/kUOLy09xM2YIr3UhjmiLZ7Ke0RgEBcpnb5\nBgS+Zma0hek1IAUnPitttwVT71Syyu5cknuDwsuNe6nnRpWss4k8lV7L3BOM+5oBHNU1BExW/MfG\nK4S2xUjv6VyVSRujKA2WXHIjDwy3zkiKOyYEiK+NxMQiv2+iMht1f0KTKUYin9/bpmPwb1k4hAsX\nvY6+w6BclkzVOjBwOYpINFtY5nV+FjWqbPbdxVCUPBhz2EtjqDekQbKgK+7lzMKddbTAurEFIrjr\ndVXqWDiIujBU7PTo26x2bkHCi7sz1v+kipXJ4k1FU4GwaPBt/5LuhmAA1qmq4H9X5qaGtUuUA7c4\nVbeecf+hG6nTEjBMIYyKt2dO/NIXGW9sA8jGtCjG+ynStrjy1ouTrEDqfUR0XDs13M8aX3CoFckc\nl3kYS9XmPOwddOu4GrQAegdM4QRTPPaHuj5sk1dLVP37AAJoRMdbL6+8y710oopENYjO/vIAeNlT\nNUKF/9WiMhCW2iqmdWQvEL/SZ/Q9c+5HLkv8dWX7yeku8OTqEZfoqqt24eo1vAUNa+1WI46xcxrl\nLlSoZlgebM9fRQ77vbGvpbft/jQm77dDQedDkPVp/E4yidfD40K99x5zcIxBu+2tESLCd9LurP3U\nXY/PPKaIhnon7FSYzo+0TYM62iPRALUnM1cTz6brvP4+55IvoTHDZ3kP3F68dj+9fnVwe7ZCn/SF\nnHISpSYxALOYxe4xzcXaoNtVQew2xQimBNQUwyUD+7EYw337Vj8nHld7PGCKRfJFgq4nXgT9GGuB\ntSavOTubYbUV3/M+B2G0nU+9SNbJjAuh76qrivD41tq9ygvIkBkbsMzCL5MmeBR84wrnEDlrihvI\ntOR5XX9tfUMVMqeeaOSKD8bNemE1l4pz3DFRCuSPegMo82RBKNLE0kupDUnktZPfumUnGsjP1239\ne7M0iBCiYu1XlhM6sAhnvF6yj4CXJR3SFEMp1vA8fetFJYY9rlzxCIr+VBwCEEB4PiC5N/al81wT\nq0JS76KgsVnOpx5K+vdorf3m0qO/i+wLU2d5j+TXWluoDgs3Dj3oiZJ30hgTiRHNoomIHZfMjMeN\ncLZ8raC+EgBYRCTIY/MSeBuPMFZdqw9gSkgnVFl7zUS/oXiIurHXJXBImWwMIH7br/HUJ5RznnZI\nhGdvn17KCmbMUOGmxlvPy37mQC9hgm2RcHYUyl6oe3y6dZoehWe3ZnVRUqcVr1F5MejgPwYY32Cj\nq0FtdPsX0TqFXDfjFCFjqy84OvXwuuHb84rZGROJdSinVfIr6/1ODZM/nZZWL5RkksFH93ONs+v+\noARSPIoUwJa2H2iiOqONF6LF86/7b2mmxgj79pfxtPYcEXABlLQOVx72ulDfraoEokfQs/B0gVRM\n7L72S/2LznkOkVsbiz1P627QXslmWHkb9mSLhU5zve55pFDjgpVc8G7R5t28kPn/CkgVN+2Veu7i\n13TucClhPGYXaKRqOtErUvA8A9xiLCh4u3tTK3vpRVtEcP36dsKXiBemSuxvdOjvMmfp634ExwlW\nJGlU55gvr8mddAJqGfuHXJR0k/IrrjE1GydEhAoUEC9Rg07Qo80xQyfjuxn+x11KDWiSfwyFfHxp\nUq+GaQlKTnXmZG0g/LALN3RNH2lb4UM0W2CdC2pE34dMuglMExI3mm/PYoqwuGI4aHJyFV2zMmoO\nKqzGBDLv6IxbCk56Ah0+zG+1RbCAWd5g3SFITBlJxaD4Z/EE7/Kr7YygUBY36j5ngLNCDa2xdwUz\nhHIpqRxQpcUwEqwYxaqGQctADG3eNusU4+SWmBliBddj5TIWyx3+NzWZdbzCn7ZDMXuW7hMCnAz9\n5Bw3TJ62v6fAwDRAMm4kqo0ZRCI1oWd2aszU4q2BrGQDDpUR5wGnd9BCEzRHKozN4d7ls8dHsy7L\n6c1/JlN05ag9ZOYc9h2ku4sUonvUQJyrMZ0JEXNlWc2kYiupqCOjJZ661VD5xl7HYXUaz1JYjXwY\nz8ysQ4xisf+sAoExLsgnY9NoNUsEj0I3HOh61z8FxQLNAjbvjo0PsP2znDn6J8Ht6lPcErR+e8nU\nZxE+713pAg+lNM8irdWe/fwoBGlgl/ZnyVKarcxTyYKa1hxrPoYOvaDQNnqTj0B0UViNwBV/FIeI\nugiqHVq75+ZKKKInv8dTUp5JJe0ecVen5kMD48xUK2NcGKjx/R3ms/i0zXB2YA8CZ4c3+J/8BS+h\nE/GE7QgsbO9cMvno3XeaeRJhrqlm36QIs+gh/iERmJSWvbo/0JVWAlU1K9BY/GI8SmLNJmGTG/2F\nB3lhzRd3YA1ksDX8bOAl0UvhzHjuQXfXJ/F0ZWMae1GazdAxTDEk43P0cuUGJ6DxKxPpyuBsNjui\nziSYb54dOQu3UAQDYmwz8+qkEfCM2ZTwryH4nLxuhMl2ZCpZPaEWTH4SexyPuoLTbXwQD8d9FrO4\n3LdgpT9PYc8AeUSz5Bj0TSDdP9hLnglKMJ0u5SzktDRvQDcs7eSEUaCipefQ7TX8BYFpyYdn5dMB\nl7hNqJD+cIL8LOCYWgxKZJyhwEDHc1GrkU94Zu9rcFwXKwJPuBdlaB8kXYwiSZOIgkw+hYlA8AHL\nOqnYJc3YtbjDIswKwX38/cun1IBYjciomjGS8GF51Rxti9eLpDvi4+5jsx7vPnwojc1tNLwc6rr8\nXZgA6ZY6azGa13RxUCGLXeDAu+plUUnlUkshP8bsftAoQ9BlJSalOwglax1LvYWgOGlBOsQkpBxF\nd4JMbsAHZ44nmbbRjxZ67BfYSXqqnQbi/sHElOQZAgjcEFU5A2LipEQMvsl94TZNM3C7C9rshqY9\nnnyDLM2r/lZEZWSHRe86RqwVYIneHusTSFEuHpdOipQbLiiM3mnkGFqgzZ657SMOrxwkNpSmPe1f\neJSU8aT59HQXtL8HKSY3na8FVMXzZ1/IJi+DATbDdLd5zVCaKFfy/npPgqIIp5luTOkFIVX0157U\nWj9+i6xYKlUss8IfCRUmaZU3vbQfNC3ey+5tmSmGbhaMol/5pplhsSPfLvOR2VNUSB7h5G5k81I4\n7lMGXiq3a7ztm1Rs0V/u/wvaLvz130Iqq77C5qhEwLfusUi0fL27Uew9vjVbWNZxUktf+gxKoNYd\nL+/5f2VtIbe30JRtSr8CreqrSdrI8s2WIrDPTPovTqsSO32L0e5Bgji2wdbQM4qXZ0jwZ1rbPA/s\nBOfy9ba2cxpHpuoMmCVVG1q5qbSzXLsjHX/k57DbA4ktBwx3M5ZQXNmeW5OU1Qy7wGhtmiNOxovf\nM700XZ3nmImMKsmLmcjopynIjXCA7S9YlbmfjUJTYPV9LLD6HEC4yrBvCdIpJ4dF09Oawd6fW9jf\nIyzSPcNh1d7QOBeUPjcggRPGxfwCVWsUmQfuYIFhUNrUwmdUpW3vOGmsF/abeYq9XhPbSDjHWrjk\nk5U6BGqjSkiJ1YAANq07N1efMhxv1tSfqKIb7QtSbzXzyMtAW0Oq5FG/TSgdpoXOM9SBp5pHw3cS\naMW/FAOlcgzZ85rpDtuhomeQhmcaYXsCb1lBMuzhbFq+z/n1N6aN9Y9BF+V8xZO5Z6cjBaC5M3xS\nKNkhT0glZeRHozlGl7PIXiyrJQeUsdCovkUTplVtkO1FMTeWp0HWrCWrziHupS+TI99PqiXvzWzQ\n9YgRqnr5qgBoXeB7jtzhiVcxVy3IEYQDLC5g+PRc6ThA95bn7Ct6bH7UZhiZMVjSu3yUEecp7BBW\nSuoZKWI3jrrxBuV5Mwmah6j93pJHLp99cUTSK3ZXDXeZ6YETARJgwvMJEGZVwyBGi8ssxUR2e/nv\nFkGeCsI4epf1lq/pGC7ei5bWMsMRGmdClNIPbWEhp2KYiTvyHm8bKLI49IK38OIGxw2hlIus2oBH\n0xAZjQaPtpO2rdG5TeJEgn6ghUlFZ40U/9rHFS895pj30dlX46EItK9unD4aAX5FjWX73kgIUfDk\nrCouL8nlv/ANG9iYr7eEEvcVqx9FAby2IzAb08pTMkVPdYjUBQ1yPbcWsHNYd35FwxKhhKPzn6FK\nWW27J++CkxVgilqIUslHwK+Zq9jglJWE04dn7dCE6uyT3LMrCMAjxNQL0Wf3C4vEtxsPUcAObaD+\ndfHGeH67pETFRvq2JuVZ2KnFjRQT3ATfrOFuroBFVwlHl8KbSnpcOd/z0ERvORla9N4ZPFltbjuv\nqKBzSf+PNO2fD+7+FKFUGl9jNQxqiOYnzuoJDJb9S8BNdX/7+uf0hM+JMPgrL51lkazVQv2z+15Q\nb4vyHpoAIwWlgxl77ZHjyHXn4IHhHo7X4pO0T41dnMyXRVhAyd6U1rkbrOGYzHiGbA5o6wiScsvy\nGDObdwt9lAEagL3foE1AQ5xtrgWsKEbkthPCOMv7w2s8SvvHr5Labt+PYNRVZnGqCe8WNkQLnsHB\nIfVhk7Spl41nNy9TJWpYuEL75E8OYwdLTRBnlBPs061jxZD7GiNAcNPoL6G/lsi+VaPYwvxRsWu1\nnAZS8c1Ip6M+QR+CF+b50/4MA0cIBojERbZlLC8Cu2OzFB2APn4j1OoWrQ5IclSplIvW1/li2NiU\nGRVejaTWjXCiW1kvCmtNWHVRpJObAgCAN9uN5kpFOyQE2MniAMNu7HV0KCOUjF7w0xOopzI+qYfJ\nbto2Me7wN+ogz0MSdtid9hjXVF8As2mTtNIYbu1p2zVNyNBc8w8CkoDuf761BbNPPFT/oP5etLpD\n3EpycV2ffp8MvtXnDYB1kzghJG5Yp5C+MX+86kMxh+COgQVq4TRYprVKVv/RofCR9HihJ593HmFE\nEMJvFUIyy/Lpb7nl5vtzu7CgI5WideoPsYshrDUgwEnDEiZcD7Eqwi0o2tynznieCAJhYrR18Ea4\n6z7ZS37LrgkF/JT+NxwPRZXU2Rq1xYVgLFQHp+VHA+f2q1pyGpiP6OMSNratlvaz9D/sPSxPbURH\nPWWSby9v2yu6kEHtWU2pNuyxZdnHN5CfEbEKLg4bc+RgjG+jJrwTdUOKHayTDqfE9dQh6nTgYjln\nM34kDNN1wO9O95ZXyt7fJ+TTTCse54ofIGUiDhUm9mCroiCZhyv0NZawxGJ5q0tujcaA+4vK67c/\nHYjbsptTa8H0cQE86vuAYtyI/tXusXoXFHc+pQahIdFdCwGz5B4ccejw/3JsDb67dXjPt2v7VoBV\npzyVNR4HTsrC5SbymEaRbejeKl5KoTY5BArJF6MaPsLgpn/IjEdR0LqVKgLWfY0hQwOiGIYHLWlJ\ncx6IHlHTAAQ+mFtDj4cIvxud6zzkAJAyvhUMDNSRuab8XRbuhCTNeBrdlBDJ2D6P26liPCS4pyl4\nb8XgCwG2lTSrtT11EDqAB6h5Qhw9N09cETuhGlfccFzUhYoxd+s0pkxRJXR6/hphI5vjE340UuYV\nMMCP5SE+rFfRvsNkcIgGhQtxs35vHN0uduPPxGMteXmbZRG82rvfLPmXLG4nHusVfcbp95uUMfA2\nuqfSU0OFiQIgx8SdpkRRK3A7zwlsc2vOO9GKvefoqPCLeXfLFUEVga8pISZZElLDLNXQSUgGGWVT\nj2lt1h5XyltYagIY4TnpPZAZ4cXtpeXxSUk+xPdM2m4GnEvPE4S8bhkch9O1CWTbt9ehb4B9cZH9\n0goPkTDq31/d/m2kIgYKwNKbAIYDG8JcoBpta6eNouFSzzvcCoRUBVXELP9BvNAaEtdWQCRoHHN9\naZ/kYUBrl6VXGuEOZsLNDnrOjEEtIO65l13r9FC4mBuK0h2g9iQGQoTaybLqBw/5r1AtrcB29coJ\nFX3eC6W8legM8yo/f8X/j5oQxvngy5j2K0y2h9/4s3zPoeTB7qhrcgcMPu05Y8DzkHSVklgSVi2y\n5JujFL0/DCDv2KMjPPGRGUSTgxZLBkMUii+o1NQLlWC+EEleDdkJ8/ZKjtUMm5nX7bcST9R/Jdqe\nQNRD0o8aiOOEpqdhQ0oHFb2QzlacjCcytBGx9Zh53WK7WkcJU7yGyLuysyhAbLSpsrDu5Vj3BPhN\nfr3+OQQmcQ61b9sFz7zsllzJ1PtYDbOG7XcifdD4vdgj9cCkF3xzakCPms638k4kN3waeTOnLO0h\nPOGQjVbmFbUhchJqK6aK1fmWNmVZ9aGLJ964rZmies96oYPVkwjAOUSOtYrTpuwbRMEGb5HJ4Xc4\nQimyJvRs8oFfvf34ld4UuaA4/3SJqMgGdsn/COEnq3O5VqXHDiS1EmrrqsYW8VmaDCLYYkSkQ605\nJT8gskxOO+T5sUlz+3Gv5W/OV/A4GPGujvU102cSsjXMmDJoc99mSJtm9xUo5qDICfWJWGYHYAr1\nxtD3YRav2fI7pWqxH/wWuSgK2nRzMYx++z2obIYRyArUjInNFyDZ0G4lHbFmmOOJbwZr8FsRkFoZ\nN+n6xvVZ5hNTcxrhlqkeE8dY38yAmoWWfM1egTHmjvK8cYsskWpnLOYs8GZKmUH0N+D/FKN5UG04\nR1A+HTaCT7qAv7oPfZelMnT8vAEegGEGVLJ733cGxC8M8QOU0IhM0Va8x212qKJcxTaHHKJX3+A0\nh8hZuP1EybXwEqxoBW3nXdA+q+dKaPNMj/xOxCHYwuUkqkJZiPRHU2WgY/J6uM6vMXygZ/yY0nPq\nZMvv8dzj0nDZ0pkcxZc20f8VvKbGzEK1gOeWHH3IJAwLD2ilSZb9jUz9saf9hg4Y3n719Fl+EpTX\nqwBtNUCtQnSQkkNLk7BXg3a+nsDrfgA2vKkMfvCAfY6FDeH43rj6qKcFn7ctUJrFnr7OzbpnRlD1\n+sUKxI+iP6rZw7YrUKsagKPlF90XmuVAhe8HYdiKgLw/144FLorsuA/kXwQILP0eFfQuHBgJKpv9\nxswXThHb27iv/Mw4iRKhxUEUy6LipqcTeI7ST/Mdu8C0x/5qTYxHOI75F/cliKResUuH+ZpxqFnm\n6aXbFUGfcpAGuy1YCyXIu6qcsyBCMTwnfH94Ww4+YYq/FcHdk23+vZukS3gBRBiwKy1kMnIkgDhF\nQMud1TiROfnB8mXYutEB8SqkyxPwWwSoP2p4/6gqbiDuHxwHnXkwUtPTcYQ0UesLnAsfHIbLEKlX\n+Gjvk4HoWi8pa3eWJw4VUVT5LZLtvwWUkhP4aH3d8+qtDca9ZKMnbTZA0gHGtMCwI5i2wFer2lG7\nHdTQNRRVeKmen3Tx52o8Bpdr/6nT/wypawf919at0iv8RdsNdRzPCWo+j0CPV3tKjMlR2BYIXJOI\nRGflGbPjMHC7ep57G6BiKSMZNM47EXftYZOua7ybJ27Sy3Ydr6X0TBAIoN/vBCDzIatLzVmgM4MU\n9k2RgeVRqnmK+if5MEbDATlEpHYqgC4ADB2QzHVzZyNos5+enb8DVsXyUz3rV7HqpZ540XgtO1fu\noNM3yAf8fOU3VAeV5P4IYxN2C5Pgv7S5gPHpQHGeuz9hMAv4/CZo/iNHKo+Ptm9d4w1WWLGBa7WU\nrCzU2niJQcbx1QA+blSGedW9ukCmdIedZYREhN987n4lOPD3Hn2qnGbLZpQA0V0KFP1uJtqGcDi8\nbAmbuODTOUckmlBhFjZNGYEBGurI6gnHF8Y6kGM3Zw5dfYvr66knoa02caoTP6WBUmZ089CHv+k2\nIJ1wo1g1sTLCtvOljipzoq5Xbb9kuAn4cR6643e4VT4NpDHqarBIiqk8LdkYgFmLccEi5kuEaozx\nPKXh0MmfgLY9Zkawci7j6LBN6QbjMxqtzpufz5GNh7N+KQrOdFTvZSLP/dFP5dJMpesZXZwCSw8E\n4Q+O0UlgZMEnO6bIDzCNwsJuEeDjwPHN85MOD5YsHw7s8hrFQhndCoTcwXX4U9g+WH+jDtnoDOE8\nr7yYteBFfzioAR1QNyD/xTWW0gttZ6+QjWdFeLe2mk0MbTxughNVC6x8lBGvWre51FxGMRL1/PKs\n3kAlWqWObFLND1wZlLe0EZ9QiGrXUbFHLqIhKIz71mY1fVH+GSK3L0ScjN+HMgKJTiACs5Y0fDp5\nVLRQ6FFudmPMeEzpla/BkyyoDvqckbh6XVaJZBvgsQSMAq669h1113d3E3yn9UTsNijP16RgGLMC\nu5K7Z0uppA7TKLt+231s6BxOL8mHhEJ0kfIvXiH6oG8rlBAdJ1Aoq5cLORh0roxLZ623X8iVyB+o\nocg//CclEk4IZ9qw6eqH8sxUTuVlHl/DrgqntqkZG7rXrzZqU15OiwcCx+HgBdxEELJj2zz/gnq2\ncwqW96J8/G2KxAttS+LDavQHAd5Q3BWJkRAu1a10yYbKzZhP4luwCx6nZER5BVxyC6v6jVkhFTRy\nqzXA+JU64CflMFlvq3YBub14K4NWMTQ+W5QQP+5broI/2gdd8n8xt/oUgv2eypGzKBIxwCkCEulB\nAm/N5Y1messSH5MPXaFj5nlUtPEB5kx5nFWGDhOvyR8mLgLUWxh72luZ8Khp0wJKkkEUZBaDgjeF\nwoCsZEQtRgPDuUK/soHYfnxwzsETF8JW+JLEDxmdejms9LPxpg1VhaSrJEhd3ApKlHGb1bCu/ASy\nLcyPKDMjlL9eRtd3UAh39vX/XPUeB+CCUBWNODoHHBsB+/8tqf2NSSf7cscu16jNJqC3yQT+bjrI\nt2PnY0NmQjOdY/RQsLNfLcwYsMAfobVgbloH9Txtrtvtp7WB5vVdTV6zEnVwePRyUyLxvB7sI5c5\nX2Dpsk9QpkSNml+ZdaKFjeN0hf1nZRibjI+ZGgn6xJHRXrf4PRXPfOQVzm0676EkjS5XAgLsOpNO\nH2AU28l34REA2S+AuHce+EYqUDfgjE3MTE59eVPdWWA2Ljkn/aq0qHjQRl2S0yPN484UV9nBcGuM\nV3qp+TItosuDJ0OwCV0npwWumhAhk0YvIFfo/JViHttluhuJnIkA+qO81NtW7JcyJ8z+3vTySeXm\nL2cJMamDNJlpB56N1ekads8duufQsm/kin5RlNqQ/0jNCGXsZe2JujvSqJXOSzlEY8SL3etgAlEU\nkpSGQQ2hnFyWwMQAtBGJpGAQ6mDocAz0EmvzMjgDEOP0lRjLJGwJpVO36P52ARbCPJWn/XjLsUtI\n6u621dzfAXrtbmc6yLOTOF7TQ2yg0x28kdzg0ava3yhmGp9GPGb9WOFeakxPSztrBevKh7FngvY/\nkmnv7R1M2Se0v4YDQBbvG0hQ5Tv4BFMWxoaKXAetBTTVAC7buk0sPq5dvfSrawCoCZUcJu6y8dFj\n/C1oct0Bozcrp6SgdWq3sxuZ3m/nlEvqWLmPwpoc7AdXLisq/tF7rOAF5Nb0SKqhL+EpBaQsnXLj\nfz4CXFqBdxkFbXwDknbp9itvn7KPMo4l7j7kgv5rN7NB07piqg7MUqcVqrf7trAnTdl1YoFnDWOi\nOmuJCvZYrtnfHCDBKfl+oGpyBGyvrqicjWazr5wiASnhLKTyqoP6GUu0DgDP8f6VXpBUYkkCwUYT\nbjOuKU6KTXhH55ck8jv9z3vW2xIzyRQCQ2h3qb0fxBscvWQMAKE8KNPDXdEjkZ6w8qoQs//WdA0h\nP6v6+ff8dAW7hSwp54dRSI3Du+u7GjNGqJvLXykNL0RnCm7STKDPPVU2/apq0rns3DceKHVOjyxb\nP5YG6i5/b36thD9dkVaoR8YwMBOSO9uBHqdyvwSD3rUrYEb9/h5pNj6CMX8sRUdg0h0BPzBNEIZO\nBmyPU4tSAA/aPuc93N4kvm0hZpS4dc0J7j/KzvG9XpCeX1Ibf06fC+Wiu3R12m+jLPchAbhjvL5J\n6SXFOhJfZukaEpW/Qq/nGqq83B427ANgcw+NQdO9CIdPb+PmsEe1cj6hSc0G6aaxvbTpPF16zzRE\nU/Lq3nY4NNBGHLYvzGXPz5ZW0XmFvlgk068kxVOGLl/qONIC2DybaYz9kiW18iF458dw8m1zMYL4\nPqtwtZmHAoLtFZwgPjB2K+CrxCcq6QKJ0ykwYRDn8OT5gAK/Jqx0Ri4HnP1FFcQ5G4RYFcu4JE3V\nx22dgguYkhBcD+XFTrP7RAysM+sxAUBqTilJtwFK4057r6FjpPTXIl8iVG3Yt9ueeuz8Z0yWBsOK\nS3cUp86yaq+//6ffMQmca5zgi22WvzMc9oxQSqQd98yaYWmlQov2BdC4ntgfKjbVAdULX7BZWMge\nLBKyYij5DIk22i4Hh0QzDSeN/ACMv67caIIv/MpALGoyhsFq6r0u/hM2rqg+WkuWGIeabzEs4R/K\nqIEjpO5j+r+5iJ43cFocGkCzbVQlGmnJQLuD30Kb2cOvaDK95QtPp1lTXVP/TivAWnmKou2uDAFQ\nVs2oM0vViXWK8YsHM4vpQXREhYkt6R07H3R0ghHogWGMw07/lTSNk9eN0hvTQ9L7lIxdx1u99Hhx\nJN4AVHnNIbrORz7J/AQdNq8YJ2/7wkdZ9S1DvOlJ9p/mKdCIQdR/ZxvyUy6UbIZkpZj4y+rMYAzB\ntv4j9WVn5joJdv+8NA/O9k2OQ+P6bgoHvoQxoHlJNZuAVLtRjhZV8Q3Oly80A9ZpRQRXUuIJJcay\nTuGaMG2LAiXfUavfF9yyw9phcWH3VZcbSnTFOwgKRKWaoOcjYsrVAuc5t+jAuzlg9WqnPI+SerB6\nPIFpcPQ41MtAaCk5c8qUakoZm80k6yjm7jbuvBZb1IjOlrCtTCoQNF96Hdjc8qujWnJMU6BlHsoh\nrABeqAS8VMm1ownPTuLig/oN0WIlwSHqdp5jFRuKQwYgvFR6AF+ahM1A8NpxdO8m3ZEj8tWOrQJi\nUckJDTPSTZLZNBvCVqeqqEK0rHIUc2h9wjZ2UXASELul7XZC4WQg9mnm1c+nTG9rPIuWwegLpeQB\n3++pPpCIjpYIYATPU0ZRb0ClA49oXvo4j4QzKCB7tKxIZJDBtTcKuZyIZ+4EzBWgPwA0ZzU8hixe\niSCagnc/wjwI1h52mzN9+sxbIZCK+DlBY8OhSO7F2iTyA6+5aaMMoIsWZsMNWsa3Be8UBHsQDUfx\nNGn57yyhMJEICFrYessVSPaKknPGVWVLvVLMClR8WZPTauINFVaHN9yMMf+WxqFQsCiJ0aT6FWRh\nD5QDICFMf3LR5C2IsCzPh/xUf2Awbdc9UVBPYB06LRqaqsN8XRZVHPDtBo07GJCBQ+dpt6TyxjsH\nM+/yYQmswHDLOGROibzOCohQ4LvJInL0E5vdJ4VpttwIvbf+W90GLhNXqYzYSeb0Rn5BYj+Pa2rQ\n2THzK67A9J8+tf0+OXQ+AeJiFz6xfOdN11jdglIHctf0XEZcHjifZY1ZTCqEvsFVrzC1XRRiDLyg\nbxIvXlkFGU7It2eGchfRKoG+A/ZTUjwcmcDZvz72zaov4KRrXf+YNXYusnJmgxP/jr+dpcmTcq/V\nhhHk92TuHk2J5ZZNwpMbFIgKgCi8/GNYYw422E7uWdFe4LcyLiDQv1neCJ6W/h0dGB12unvv4YA6\n9+LrIG7jIcGwFJKMl7BavYyYNV1alm8qzzsTQlHIOHDglrQgncOvr4NEMsbV6o8QbuzyqjjJBKA6\n2VqJD3hAtUnlIlXOjhRlUG8XiMlGLj0kpcHIjsZs7Xg9U/Ta+GbLXxZ/mIbMgAh19/5TvlMEwKgV\npdwKyFC0u4xV+xmhuOg2e2fe9BoGlzSMFa/5s5R2LNwZgUyz5m88y59BWl3OzcjpjfJI1BV3Wmfl\nEb4MpMjZrbOyZk6s1ooOLHQwuEl0LjnecVBj3WYgmHt+ACeN6bSM4NIMCRId6qEirsd9ldkRyqUj\nsegSOxJFaduXIrJbDxuHdATQIm31zASzh/fZyUTDR0+NtNcmKv3nKeAgtQAT081AlEHfsToJzaec\nPHkzLZ2rn+IXSi3cPUyXYFs3dqqrrT9+E9LQU/fWZrGPkGs7HSr5ndvsZmpGlT/7qbukwa+DiVM+\ngoLqDQi1hqVngQEzsOHUsFK59BIBcG1awkhpg8TuALG/wdFGyBmq+HwQ6ThtSbJAsAtmqgzCn+8R\nmUmwFCVyIB6P6FgPKpV8VOC0UpsSZmbLyZNO7bvPm0vimuIyXLmc8SgVoanF0Wu/tEaka4fTPLXM\n2IU5vHZilvBa9LmR6dAXUEWUDVWrzOc50Z0cg4Qn5ugWX1xuTNs/05POV4naSgzIw2SOcD3jLcWA\nTcTYcpa5zpv0YEC/04VZiCqBgRj2ocRhwziTYstonhhl5UTT76EJOpdhe40T/LhFxnOr80hNKNzQ\nE+4Xq+q0dwGX2osYtTUT0PZripcSg+gTnJs9+tNy/57GQLwO0hK0vNea5hsI4FL4n2JW8PixMqxS\n/h5nYYvM4IU7kyGY5U3fDVhpwNHrzNokIYpGsZWwL2MIzEHfALatvqm4UXR176g72oSSnmblaubU\nwKGdISXxWhORKAoJKM4xOU05xvv9cPvVVa6uvv5WPBSz4CEq2HH46esNuaRFWldjP+9BQAqEiHH7\nWnlibRxc9WDYrV1r1tl9wIu6MaQRS/NQ/96Vv60MfMFRuBfgP1dzBXUiwPOpHJQ2gXHqnLkcEhWB\n0yjW5de6pn2K2S36zOSIqT1MDF6wEipjl6NfcOWj1egKzpxIAFlaB5l0VmA8enLL3rIp8ntpsadt\nSODKP1g1zjUU7f/FQG2HVFOQoKjT56otFPopTz8m7z1uLuzzO79/aAT1N5pO0cBYiDKIdAZkermm\n+9A4Dq0Fgjo/pNx4fwZtrUHViDgUFqwy15KIu0b1zPRGJKBgnRqenEewlOPjHxriq+ZkVYIkRb/H\nuBCdCQ7uvSNngOhhLHeOuI7vBzn9B2o1iavZTqvfRY2TGQDmoHl5+LScV4R+tX7Ij7ih6AtnDBJ6\n2KN5JRJv3EgwYSJZs0xoiRHL7J+AK1h6fGZv99GMIHNseS29deugzGieLUIGdarhSeHE0B5bPirp\n/A5Z7nIhRGYlu2G7zufbwtI2J1q+cgfZVj+MAIPanA1pdWAma5aRU29blz/FR51EoI4WbwX/9g2N\nmql/plNVeIdYqXY8poXhXV6Ok2OFewSlgkHgpuW/NZ9br+Q3cUlPg3ZZUn4l+rbbVzGfSleQyjPp\ncPemjt+wQC1x0/Sk8ouq4TwhXbV71om+mDN0yrXmGGbkbtdLpsPXv6X1pJrqb7cQw5CRpXwy1EDi\nEJOIwDQDRDz2D6RH5iXhXV7FOVDXhYgn94WrvVTk+I4HxIFegi0x1SFH6F4HNOG/d0IKeocDb/0Q\nOkLZY+XO3G/qzfi+cgQHT5fm5g0xHfO8FBRWh0aU0X/PoEmoke2vBitv4S3+nXkSQpyq9HZ+vcPr\nszhL0qDfIXryara79MLSY6cyDJsQtSC9wQN9XTl+3kgbnzEnlbzfKmGB2KcTLXkfKKDPx8cO76L0\n5u1BSaqEcKnyJoZ8E76/GPoqaUUTKZ7eKBxsN7lgeePSzmE7gNm+YDs3Vg8NJlLkfTbvkbH2dBsl\nFb0BD5HCHwHFxbNN2Phh8naN0be7BAwoh5D1bsZCWOpIkB68jSMyF8fV2keO27+1ZvsfQsi6kPUv\n6P+XMbK5qOWdxicucxoJEO58gg0oUo5nwF/oimmtmh9bS0dasObMcAjPEwo/pMKIEP8poXtgFsiz\nXyZbbw0Qgj9cpSPivcdjlGyv726SGXe6o+EzxdBExtnXp+zF7cJ5UDEt8p9Sx6Jvz9YHO3SdUHcc\nCI4ekC7mTtJKfw4etPKF9VbUzdLxvJJ3XhoXoEt2EuOyibQ/iev8OXViS3TE6zB8PP7O0QTQLZr+\nSWaL7EdQ2mQ8RPE58RhAPmpYwiZ61uWeNNijpcM+kwWqsi4ddlLznyuXqYyDAGqn7d7rtqrraFWO\nzBrwkTS4/Ntk6qjcUDSWj60C4EMU7IERfFKtp7HkfGIPSu4JJjTYr3g5sRtJaZgj7vIaNSQ/WPPl\nxBMkWQkblhuPrjfr53ivERv51T8j5UpND2YU8kGxk0EUict0fFitKc8ekhr1TZh6hfL/4qbB92tB\nrtsfdvjmPmjY/Iz2mmPOIU7J4eKGOixFQCeZ3bXwiuqF93luji3aRArkGbRdWgfa0H0uFXY6XP0c\nlYX4/lLzWS/ZB3B+5ErVZaYklTzXaIohiZxjOApDh6GpNttcQof4RKjAIFH9LG3k6HFXzSEs2P3/\n+vt6qYay99o7TMIiuyPWtn8J0uRabi8WLAOk7AXPBXE8TfBswXufrGAAilpQIii1ImTRFHQ44mNU\nTepmJFqybmEbNPTGBzppKBvlyi5SccgSJ3Kwbe8V3K2xvbsfyrVVxjeQDsyKXkvfJmU/rGy3/3lq\nuZYkiiGvD1zK8kd/0ueMrcvZA28qcfb222DGHicseWnhBMdxUPSrxifFlYozZf+nGAlwnqHdFar6\n3mABPgpg13eZSpT6fIMyx/Y1Bx3bfLnS1g8BSi6cLJZxMPncGNfBgDQmRNNNhnTZX0zdCc0vOMjN\nPMI4z8O7+76n86KDbBFIrC7ICz4tzeZXL/EC+EC5jXPiRXYcirJHyWZF2ERqt/MmR2AwaN4Fhh6v\noErQGRMa//5JFmUEldLIrDWg3kuuBvLTS3CuuC3Xw/31+BDYoWQlTJ0N8IX/cJSDhgocZbXMozEo\nj0UjgawVguKEv40qlp2MDxIRnQP5VUR9LjA9tbG18QkTvpfrVtvrZAMGLd9cH1bbYZ3zizn0hsXC\nW0kIqMNtdhEhIlHGDAn2r70IcHpBs3Swe7ShWBpKn+FCtvDqqda0HeBinM8fdXC7EjUliKqOHF+x\n/mqtFeP7ZA/P+AdehMqnmg6y/2qkoD24GqpOKrtimvi+y4IJJXii0YMEjXDxWuPFhl0awSxaIKAb\n0EFVRdqMFHrszU4xBWbvEEmC+0HHWienFUgyjdG8PCIIOlJMVxiwmDYXO7Ec76JsE+Q7Qe0PJxZM\nGf7d3k/tej+2LT3+aDjgYgQeuHklpJggLM9KwzqyfTeTyZ8budnCtVHQIR5ZqZtHS5fT/yo+CRkj\nkxgcEMQ8PYIEY9EzaqrJ6BgPcDktxc3gd46kQ8G1XYpExNVcrj7bHoqWAgeUesLKT35fAW/EDXuW\nPwnZ5+nOXUbxfRgSM6PtKfX49PqBzM963JD8rLwbD+3cg/oX0kj6Mf19U5brXexFti/oKNWuhvFh\noDnOO2QIqtrqcLuc+p65XHPEMtNT8wgntmqbTdtDTzlIVjXdXlYuGw0tSoEIuYchP7kcHbMOtPfL\nHC7OlWyRLTJJgU7VtM+ErbeesR2jxXyl5AcCXTLGHaLMEYuuLkjJ5DH4R2GC4KtAj+zF8vFXx7ks\nxWhplMMS2h4Ax2UFQD7JB0bjv1o+bGoMqIqtGWSveu+7AFFj5IkKXJw3tfo7jQSMwDmElnJIYuXB\n/ClVk4R3tWkXQ0ZIbzjvxDRY9/f2IWqgb2bxKbIkokgW1wM9FSXc0SEmdkMACygg7ec2kFBxKNQF\nXv1PuQPicPni7UYYkV1xXaILd3a46IOGgkIlwlnw1dZMLlBbEhqmgM20v8t8fnngSQYbitoCeTlo\nWv4vU1Lcs/M37c7kqVpN8wblTstIGNgRBig+IEmAIsiM1ZBi9gtuqJ8itVJWrrxLh4yL0yWEN+kt\nAbdAJb1kIZba5m6CVpwvp6jD4fOnLGYFfn8EnpXHvlfCIpvodAA913AQCkMi5z7riQTitDJBDAzq\n+RQUxKHWALxSFIER+WbQtYBp7sKOBQCIGcHQXzJoiVftUFiJDGXzXe3/MgsbMFy481zHE3bQ0Dgt\nFt8e1nGbvfT4w59gZIJVJY6BB7akz5oiliT1IkKZoxAVusPz1diVxfPmPBrQzsHoX+zjMxvvpwI0\namIjOAuF6wcVtCKv4oI0CzzX59y83c58QBxxgm2fN7+qwR0+joOZSTcLKbvd9+CEvCvdlZbCh3ZL\nVAVJItgycfbPLK9Owq2aB7HdiUTTnL9gkP3Z5ZBvC77XsnAGNSXKS7rv3kIktl2+/TZa/nqxYVX6\n+MIntjpQI4KqOzNwLLOZLKh5uUxuxwY91DeZPH7NsG6cc5Jn6jjUtMz9mSWTWn4pMOw30PEJ1JVG\ndiabkKm6faZyb02sDyU5GK4KRhUkmAQHTZCcLkkSiZkZ3h4U/om8pAAozuek2mYbwayMYtxQscE3\n2QZZkdc43PZ9rUiI10husLzbipkA1W0P4NbT5lzgmbV8s9Zd9WwhrrGpXjrY6hB3v74fBenX1Xrj\n7dmz1nfcncYv3ugIDlRuaiJEpu+NyM7jneL533YvMBnms1pDZCIs154UUvo+q8xFYi560ouNISue\no+OK5byKnXKMeCFTKw03O9bi5Ac/z/LAcTj97FIuuafbrZ5P4odmfTVZEoTJqtcd0x3AKbMrPKsa\nZysCwgi1+2mNtZExtZyP+jDwu0LOoPG57kafix70PY4RRdHzS6nLCUlpCWOxDwtXEAl+nYdzK8K+\n8PU1qFh463t/S48xWcAuKbm2UF37amL7uuIgDsvj+T84xVHKRZVCATWIEbuqaSjAheTVQ06ZOdru\nkKnsP9k0KivmAWAniLSLxecx8vq1E4i1yl/MLZ00NLWKCzsDXOGZ30/prCdouJMbusenJi1Dgxqo\nih+z9fwEdE+WkpZaRSbeL39XF27BNKrO+7C7khnpgbGnJrkaV2N0iW3exATefs8+L8/35BTgRBv7\n8CPObb7w7zjiXnGbj3FckEIryXtY6R3lYhwflNakAAZMyYOHjD6IbP7B752iGxf1W/wilO6h0rQE\nar+PcWiNQFxRHZDD3VvEPbjSxXmRPUwJyj3Jrb1z6LS3ER4z7+GLYycZLVklLI0fNR+7330dXT2v\npp8XHOI6V4K4kpct/hNLKEI8YQ3PwnV1UFzFBve9xmFtyQxTSNeBMr572CvnH7dVW4CVY2lmHHM1\nH2NjB3VhdSmOKNUhBgNp52Mx2AhD9YOyjvOLHkNtr8G2/mvlPp+iLFOTFC7Y6Ud4z1TAxxY8JXc7\noJ2O5uVobK9LDmrH3tmB853qcz45GJpWyH92qfjyulI4iyTnkFZF0xJnGTHmX4dOUeiwfH0E/jMC\no/DoBrpICv4LGWWR2SFY8uqIp3tCT6xPuFU71wD9XtkoGh1uG0bSjrg2gyl0rsEW9SrDUPoMelsm\n968J6XQ319HHTo2U3mEKckWlucYEyDzFdXCDxkuBYI59wyq7DPCzXbVUxRrTHcaq6O+g94f9pb4r\nSi7JUFwrF+iO2icsunqz8NmHWrOuB8Dz8sL49IQZAA1Rplb45QbMFht8481t+FNyIAXObDHM+6QP\niec4ITa7cquiXSvtFeHpxUQJRqtaHbzfLO53980dgQInfXBzIsOHhr3mAxh3Vv7+nYE6K+frn9bl\nDa4vBa0bo0+SAOXrEkak7IwAxSte7m6/cMzkK409SJ8dm2wyLLjoiKPTXJZkh1ZTz6VAsnwBLx3E\nOz8YHrtywmRoo5QYdONwpcA02G7gpaWRcqvyzfpTR58Q3VF89DYhv0/PXORB+M7TuwRxPWIUKIv/\nzgf4PWGWO3nMbbeQD7OJrdQI+H47G472ulm7DWGHPE5rMwWiKErH0J0ZvfXnFvRrJpBPoRtgof2r\nGXA0Y2f0KsTyUJNtMJt2CC6Vy+nu0DNhQ/sSgGjJ5SDgeezoxiWDiE1Cji0OQ9t9JStuzaqttV1i\ng0HSYjqyqxXnUd3ZifJ8mFZci52EPmZpSfkGINlfTqoqMBisY4cnal2ZSAprOkmaNQNWV7b1hexs\nIenvQGv13ArIfrzO+K272sgctMiCT7X2y6wghe/LmBAWpph76/TH4ylpxGNVFoAMm9wFYrHv1mn2\niYM404DJNHhvL2r/3VCXfXacSTjjIskNY84JKAOOj4JzZSfmeOMOiuH0E1QR84JcbMdSVKmL6ueE\n0BoByU0ebHm8qFl3JOckVe9Wx3Sd85KG20zTwXSQJi/KBnTYgWAVqSYefxh0j3IqlP+f8zsOMVq4\nwB/tK/Tffim2gkaazJFNxSyng3IYHCL6jA8aNrKwBSbAemxpCwhyUCWWepL5jC33N82LLOEZR99a\nBgQ94YdD6er1GxTSZxo1FGgnQdE8I0EySd+K2zL1+Vg/LdmHvGZ4+xholPCnO5TcIMRYUh3db1bK\nunfrQ/TkW4e0VMOHCyfsaWt+Li09EsSWppgBhEBFGE31WZUF5KT49WtZUyX9i4ym0htiVTUJLWK2\nYf211CugTXHZ32c8CqbivFj3gOKO5Ts5PAc2odjhinmiPJKMQRPhMpXaafTdnV+Uh6AJgtjrQiZH\nBBfyy1HULbQfhuKbXmptgEgwl8Py8poeqk4dLApc1TrXFO44bm0NtwztwsUl6kavgolaDp8kZFM7\ngGEgmMtCCbKU56mwoI/DpgXKTxXGor6G1U0CdDu5apPuo0qFD7w8YYVF36jujw/NThk8rIG/fzWI\nHsRXCiCVFa1wN0MLiMMadJicFk9wmBJGIHBZ++M0tK4a64y9SHjhhwkARKlk6oIvM+yQuTAo5e4H\nS6QZh+i3WIKah1BAvTVJ8ufUQRcgGSE0JL9/abFOzwyumzyOjH/z3kutQZWNBK4/K0ZQCqg8PlGc\n0APX5HAncrdGJwmizAlOyoV3WS4D88uDRhgwhsi5QzDsYPetf6fmJKtATZff2kzL3+Ddx3m7ipIy\nzrYSKq87577hQlekMU/Ka21VKEKu+slRICQlqOoF9kyg32N3BCU4fA7V6dAvzQmcsv4x5ckb2ge0\nmt8dFSXBOG8MYf1K+JULAmCUIzyiMCUqZlzavjRWabRoClkp0T3KIv8YafTk3HnlymMj18k0V54c\nXQgmtWAYoNubE6vbBSOjIlmbdhfKawy43lUfARTEDJd2bfKtxc4KQ4CjhbmPfLHVVGJuvy8oev6i\nU/cdda9waozs9fyVpYydHK1EhkRHamIA9gGoslvYftwxfj2ZGhu2j92cO/YqyTanUH2DOBOemrWJ\nllGPGFm8a9dhG9CxKgUenxufpGEOWwp6kzkkMPavKMrIB8N6jE/MVfFUTJGbAG0I+/kmKU8lR6ob\nDBZ3oTpGWi8gvN2vi/k2IMcBi6xCa4kj63NjUQ9yiNj0G8uf22mg11vQdWt+k+Ma98cCVoay28R1\nekp9RpYDpU0u0a7gg74CJaAOZ+EVZJRRWKYZ75t8tkUJFEv9x/sxodjr2Mb82d9eHfzo6TOLVK/B\nO8VdddTlwdw3op4/eJ5itv71gtpreeTE2a4Fd0NMRR3hFxYAI5m6rdDVOmlLTJBnPnh10uXd19/A\nBuJIYBJcR+BwWMDLceAHMr7O7JlLKB+YlsH2UuT7jsk7YrsODPkXXIVVltz7kbtjcvBV3WlnKOcs\njodaeZetolKxciwEV8kwsVR1phgdzcIJtzBtISlBY/xlR7vOI7bwrqERpnjptnIXIIfLnowBdwqJ\nIF8YfWr85dxfyh8h8Q96zeFUH+YQRTZof2DgrEb/rF+yFobl7dids1Fy2iQu/qpoZO/60rZSSDmK\ny89Ytm3Z7BzpO+gfcbKYF9Iq+2aXP4yflqOzZlJRzEHZZKQ47+0J73iJE7qQov4SUGnGFv06NdE8\nv6y1YDKw7uNTXNLg0grnvLiWlqV56hUdJ52pVcBJJuy3ViRAhFfZtK4ZM6y1YRO6D7SjEz0LNSHB\niQMjriE90SMA4xN4TJ3LvIOzRUXBRktygDFiBdTP+PuEQLfWOa2jld9c+/b1JI7S4SC4BWuJFrLU\nAC77TKAeIkRe3yBKfedjoDZBnheRHV29SbPhQNpN+qSBGeTz4w6+TDMHoQNGxBoTLVrTf4GpQpia\ntlTU3BkbiUwsZeY8+IJDCGgTE1nyj3Qulf/TCZYhiZgggz5K63FU6sHDVCk2824Me+ETWNoJ5uyl\n5GCMYu5oZDRlerwACdQqM47Py5IjHdOinXN67N9kRmw7g7fmidk9UCpbQNzr2cKo7coY6pZR88Fu\nXvTZHnqGCykCJzay6CTkqgNUVbcuhBo9x7mUFHrALFnOAOI6ZP+BgQ3lf5PbuXVGhUITheNNI5Z+\nMQ6TXkRxdLtR4X6+8VMdHK2oRuoGNmcMDYsKWFnTu3NlgBrGrWtJD1W9nsdJoPGCedjTMBcPbwpm\npwG0jHAGP9VpLyebi1ax3RPeotusAy5Vfl0YdFvl2nOZCPEcQ9Totu9f1x6QHqce2QboErvo+Vsw\nF8fZwrLCrl5BUlVINH+YfDzlTDfj8tpFbW+uRiTY3FafJ6DH79tAc/mCUfS7fJ/Fl1cxUUC/mpmo\nMiLW1gZdsOcCX3vZjdThPtQavOmZ8kTll2CT47BokKchz99LPfcaDs5uCj+ppsmSiN2/vkkvZzyF\nxHwUxOrxoZ7P7zOvGQJ4EjYzIhrlcJoiZXZH3GKfQcJJKDVnMj1G90z+uXRJUYzSO7Y0Qf2LUclp\n8ppNytLAURoQb7Ci9LkQWG9MC5RxJ920l9f3t4kQ5ImviRBfnwoak1lyOmwJ9/iwwbQgV8B/P6H7\n1D89FPsmzOQZeBoXVL5qVgw1v/801R4tvjBHYjOYglWXyoIeD7sxnZK+B3kD+ckFxdgcCzN+hiqb\noEGcG1ypG86oQkGiTW1Bs5skRlG0TA4BJTIerHvuoXZD7loCBnx3IIK4Kerk4/oHn1LQvwLS52Cn\n0yh0ZVs/0kjlGO3ZeHJWM0LVLP3v1PbAKcruQsGFrdT5u4f+YjDvCcP0H1S24OR/18ZnoeWBCoHp\nKzS4MvSZWv257mDjmPbmMqsPJVE6iztkyer7mS05XXi39amGp1Wz/eG6oZUwDSNEACEgHEr1RuZ2\npTKeVZU2Xbo7LaEDfQLKipJbFJSNuKRCr7vaWigMMJGOxAjON6trh/ZMTC9S4hzVxaBuZ9j2bNr7\nTYOLhMkQ9fkiYMcxcvNSjtQr57JQ95QyehEhX9qWXwaLqBTFiKBQYD50g58WoM+61JqEE5rJXMkX\nR8OxmC/duKipmS/pHVJysTzRPzM86g0oEqcN/bRnvwixCAYPHC8XWABeG4Pa/X88BbiZzLHE+9wb\nx4ar/oE25mWKttzkTkJ1E/5LGWo4m2BFF4GJLuiq9+cZspc4cdzB2Tyr1zX+f1GcC2y15OKkMKrK\nBFO8Icz7zAuAp37X5Fg61DVJGbUFdpYV6eToT+wvGwXGr0UWqPD5zgay/REuASBTyh9smWv2g0Up\n0et75HI0HKYU5McCvEv548MyFyPMwlABwRmwPe6k6VyTHztPs+IbHPDhsFmydVjPy6qgF/6QY2f5\nbjGot4XKqpX8id/khZtqpE4H25frHN1aB9lpuhzLXnoAflRIzL2YkbS4Y1XpHUeEfOyd0hltPUNi\noq0dkhb0QsDi0cKvFZKbP2TzDc6PeIBQ33ULbEgWTxox8NTCtIdtPVUaj5Sb3/VQiWJ2eNmt30wE\nnK6M1LroYy+jMNW196d4AhHKM3eX1mMBN4IcQ9Zhhsa9EkNXDtGc+21wm21R4G/h+CYmg/q0GWCy\nZ0HC7QUt3kIToROBd4ma2AoSAF2xM+xWANuA0YPmrRMlNDR+4W96DTTdYdBTaFZKruOrrMBDL3/7\nkS5vL6n7MTsiEMs9S6xSXGItlfuIc8iQPyjP8iwwxf2nQZ2Bp0waVv2ayeJA5PToawY9jCtSG2r8\nQNFTIrk4PWg1OK2ZmW4/QGork5EU9dojkhbWwJqxWTYEnStAGiYJ1AgSe52y8oB3jZAV95uhLU2g\n2TqrlgzbEVGUXvC2khQjdSQjP9juApXw8spNt1+AS+eNuURdbOP7oGBRa27mcB3PWl0CO60MLa3c\nRC6zbp4vzDp5p7xZU2GbKd9HAgWnnEdXl6Jup6yMO2BKPFFNmzhB271B3QPSyqVJWrEjqGi4Y/jv\nHilL/zyyQRVx4IED8ExwMNWYfV+5AC413JJ5FBKEkHAnrW9kfpth0GAxtdhy8e937Krox2qBHICv\nP97grv8M537HLgyfXUKnITjmqUQ7zgj87XeVHnwlL+/FBge0vSlS67cvn+rNrw0v6vu6Jp4NiOBl\n79pFxVspXOVALLLk0r2mwuNMMQbeatz3ciuMQgwyl44bpWakxirW36hTbZrIjFMOAch1h6bXSjf0\n+vqMttSTCAjWMsf7dhaRWrYY+ydiQbd4d6lOS8icFRBUV3wqTeozMGItjIEaB3LYEiDaiM1hNINu\nqcCBePD9T4zsRR6T3SBZNMD9LYxwB2vhfBn0k6Zyvdo7t4r5je6v3Wer0FEPeJw+JQvJ66Cs8X8t\nCyiT76tpfCeJFOkdy81ovqIB9FWVANzUNFbPVFouXw/VCV9b7zX9SakvhQtSFWyPZX+0nZQ4SGeW\nhooX/IcqN9EdIFhRGKtpMF4AhFm75FXB4mnaGmErdb5R/ulX0wq3y/4ZJcGK2VW3uKcbIkNLLvme\nAtcOiCgVjE+DBSjps0y2mtQHVZsMM84jM27VIt1AICZXieiD8eEP+lnIE1B2msNeR0Ib6bgrEkx0\nenW+/hMc1JCB1bcxJZ8U6h3PfrOT1/Yclrzg8MNTU+S1ARwv71HjwpuN/MNFrqocdNZeJBHBD8Lh\nE3nJPAgASUyi7EwWvCDUjcCNXwPEAP/I2tjs+AovNhpHljshFAmitVqORZUhRPUSPFRWc9xRuOYC\nTunfuGIfjRPaUG8IdN3VDm0RwWaHNXZ1GgkopZaHPhKRgSGIVO/arbDBNlLsmmrIA5zFjgVjGjdU\nbi3NTG6ATUh3AErcG3BR8Zp3f/jSqFBDuZkUGDxkkL7JMtXe8VxKSZeprgM+hICfwP7LAoQ1qxv4\nAYQqAl3gOWtfqpiavt9zOuVKZbdX72taoronsn255LPDkLnVy2mJwunzAyiOw0kALuGL0BfWlrKH\nad0IOJ48isxFYQyUubFetkH+aQGq3he4+GzWCotK+yj4ilz8qCrBCNODpsiUD+8bFrp2m3/x52QF\n7B3IWJIMqTWUTDT7wci+r1Ytm1TsKEcl7AAdRd1Ky7c1M+bX1IA8rkxqZ3kyz+QJRhl0C0LcTr2Q\nlJM1gt8inWL/ZIUg5aAihzc6M1IVKG5Xg/UGVsSGDAMaUbU9cYVjz/097Ptwq9SqyRRxhDUsAmFy\nw38p0OYD3UzrTUiOQidNFSqZ19Bx9IYGA+cHPZD5/bCctYPLFNQGYA+NicS4eliizsfKwNv5uTq5\n/jtj43oeHKF0BqbtGcI69+EFL4fOMHFqwnKXfVn8hRAIZUGDh8X6WZi3wkBiQlhcyNGVLO8wFHjD\npmFyL6GYeMQWuJwxX+a3uSVEVSTA4o+2baBZjz/3XwYZtQA++CgT0deSZ/GNmpoqgwKWMVTeftEd\ngG3Ley8bhiF9/bCanZKkWRjlHLO1jfvARzpRnzqF3YvyBmeFNF0Gv7h+6oP+SDJxkeaf4VMjXJ+w\nz1xN1rxkIvdO++jkIf2HE+R5/LgHo/ehAZ6TNl9MFTWOr0ztdLDzpfnkNcYd3uSRVtoBeM7DJU3j\nXEPvs8RgLrH0ylODWloSp2fkN3koIPNUbVSjUt3IHB5xpKCVCxFdhX1/OX3qF7RO755AwYsPhv2j\nS+zPhJ8v/HzSFBI7tL6UpnnB/5BdKM/XzqmnO2sdkT+d8Pf8ouA7FDx48DpM+PigfIkapTiH15nG\nluWWVgpN+A97NUxBG/ifyuQZLZHBtZZjUTpQbo+a8+CIwAmZFgSLrMoTRGEfFvj5W4AItZ/4/HCo\nrI7NPoUZhRaT81Ty4aqYEiDRhLyPzVrtxWQOR3MvKtMBS16Y6PZ35po0DSbP37qi9Nlw95fIBDC/\nJyESXxpkMFLjDdbyruaoONITF7IrlcJ33LHZ1JSO8LoJL6iwRa6Mcu3PxtfPkc0VLrAEVHH/QdtH\n3CySXW0eDLk2iYnjBjFznchMcvSpxIiimRnxlg59dLvDZVd+ahEPOYzxjW3ayMx1DoWoOGShls4H\n0fYSx5ITJBMnXqAcIQky47odSi/sejAeubqIHQ5Uu+usygQFdOAjXyXlUcNjWfcts1Me6C2eC40r\npCuFsEsyVU4HDpEPp14dA8KAmhNZsj5cm39Fys1cn3Yi365EDKACrY89/ZD3iy85lFv3Bh8/fy40\nJ0qPCzNcrpuHze4KKCpDZaaoFC5vZd32K3W5WnCST0DenoiHadOW2bEusXn0ukhwx09XLmG2wv3X\nzudIhDQvdU7SZtFrQCmD51OGETatg5TrqyDJhoAcIUKI8YmoppdgqfrdW0hi19KoNnaQPUWeJ54c\ng1bgs4LV9cx42Z0sj7F0m2HiW2zM5FFaX/kQghQQ4ua9wSQj96aHCjozXwzgvy/UGLMt1alChAX6\nLUNuEX9wnxRVdDr89ldRL9/5LgBKsQ/dFqyvJgo6fzWyUbe8gMbQoVlSgYY9N8tICCwcmwak8BJ8\n7/WtZy/lG4uJxIKU1dfXJodVDF2e9VPF2e79dXTE78YFvzJOLPQ4JVfStm4jNnIbpRdrEzP2lNB5\nI4n6jNH1jIS04/44lqcdGkve2vLScvSQWyEwWx3dabuLJtDZbBDpAVXbEhHjkvgURbItDfVdl1rm\npl0t5xzrC9WqzG6gaxcjGrcL3UQXoaF9+htC/BSXam0aXel/A86JVJAozMoE+c3Gyg4+x0ybV9nO\nRKkud8vhBxJMWXd0dMQkcVnRYjtr4/7nnd9GQHqCNMbytEv+0gVxEMdujGO6owYvsX/Yxd1rfEfD\nePRMkxDH/L4+18Bwa8SIMnzmgvNjpi5oLWjAIOZWJcQae+2b02XWKt+SHjA4vzk2mbJGzq2FvavC\nJSkVf5r+EZGRqwcLwS08PDoA6lFch6iMhX8sYP4lRhB7BKj60yB7lD4b0MQUUhb5Zt9tw+mV/8fy\nwKlG1Nc5V8/KpW9mLqAW8EUc6ahCJjEdGOwj4/x2h7m68tGYl32pJVZLVXDpsYdCjS9Hd5Nsn8fB\nxuIOMkcB0mSJhjTMfFI7gRWf4PftOq7WsqoWVUyt1KT0dV3MdFrCA7GlrZ11k6IoUPmDE2pVquil\n57YQQJKiKWL4PPp+Bz946kY4QWW2Arhi4s1bpWlQyMT/Pk+uux3mtAVusvWaOCHOba41Fcc3KJ7J\ntzyXAobuWUMEJKCNFH9fhfHbry8DF01OgVThe0spuATg4ESDgFtDV/cOfRToV6pAH8CJidNT8pOL\nbvppX+em5vH+G0fBcyhaVbLycNylgy7wDJsp4JrxlpJQU66HYkord7v/FfrbG+sKUNHyXoyoRsBf\nAX/NFgk5ydNSHZBU1O1tc3IkTcIk2D4ONSD6o1uw4NrlWkLwjLmoaQLTDv8bvYuUFfloaqzfWayB\nNxcHIoiDlJA/Br2JT6nAX+P+nO26dyC2Zz+pzRR/T5EitCadgFqRtHajuwWw0mXYFokmpSIssAcJ\noHET4w+2vjCxEk12CyHNI2OQ/AP2573P8y1tpCRS88djiYxIokhgbhr+Xq4p4dEqNAyA0lglvrkQ\niV/QTRsDTNDXmy2Q1HFJpxRXiLE305BcBrg9i5bqHXIGpc70DoxeTtAEc1XtE1BTCYXBF+Jma8XM\n8vc9qjTPMjQfRBzpxMuh57QYGFSa5+q7lSiHs20iybGRUmUqaukse412iAPlyHU0jNUnO90viNQs\nh3VjQpo75i0QWrG+Izdo7MJr1vVmgTHwPNri+PUetfMgaHKLw5Em/uQTAErSs8b2TlOtK44mXo0T\nzxchPEjQx+WB489sgNsD2f3arRJn+tpZf9F/otvvgfagJRr6QhSui45ChJJ4B7CAavnS/cCdHsF5\nsb2NdCAx7BUiv93XP8mM2ZLj/hWJ4KzZ3acvzU7pVhoxAB/X+RnVu4Kjpy8K/tPVBpkLzm4k2y1D\nksxlnOlBYyDSSzqUvYgoLwvmH9ZYNEcXNtKEJnVvcMOdwwysSsgWc1loxei0m7z3iKDXWVX66Zav\nzuPvL+/GiHeYq7JDLhlFDh9YP8GARcaaXNKGDjvywxIyNVtZyHruLiwebw5AcqfIdd3cECk99MdZ\nVS+DC6hVHmyWH1KxBxfTLSDedUBZHN3exz5eWMRCmtFdT2bBYDpgJwcRPu02IIEbp6/RstIqj6VG\n22Ao2rFnDn051BKYXAbGX2Hjmjsp3S2UI//N/eVSwI77A2NXSZR4PZ4NLPWJOVqE1adyn1pcReyg\nSwTpzAkCD9NCmlN2UbEdabHabHwIH6UncPc4Tnh+8W8QUZvpCivzbOwP4D3kclTBW+iMJ71icpMt\ntEDqkYWgPrsD4NUKTTE9xBxwt8BbtyqJ7EdYt3E9dSsRx+HDL0D2ef0N5o2ORntoSGL2hFBwJ1Xh\nfeElauHm6LfBDnDCe/m5yjjoP2OYRp8bMmBs0vyW8Z0Sp4Gl9XeNDK9SQyJPbInDH6SGNn60snfV\nn+nzcV4J7RI7UBk2C3YUkix2N7o4ZD9D4jaeCq6dWH2qvf9mh/7Xj8RmkLnELccA0w39+Uf3A63V\nAoG20VmX/Lb4aihJDMdKnOwvetZatsAI/YL6p4QGXmLp9YwGMoALOtg51ezF6Xy0uhccW53weRwt\n1ofTaUhRYxm3Gm4SoAu/c6ZJ1vftXmadLxJzrysbVPSx4ULTgfmFU5VIIeeFczZ5CaWZ/yXM4Qhk\nThyk98/lX9K4f/YBwQNmUHUpcRL5eoZxBh3/KCw7fNSX3hPmU1oGIW+KDG4KaQPvEU4/EUmR/UMy\nkyL5/Ro9i4Fz5O3ODZgIgf5TmzEU0wOVQNXFHXH/fP2uS8ZSAsqURLxESvBRNu6lpYEbeORrAeJ5\n+mINpupxxSa9au5AS5YLzjfCr2Pin7iOsnjbcQa0SzhP14frKnHtrnMAz+f0yZVHXoW6s1AASqYg\nvTNXgPV0U1Cmci2ja2FO4ZrDCRkYsaANuiF997OvalAnDb9opmE9FjdeccuQDDhFhhnDBMwdddH7\nBrFEbDnlTAHPc9kT2vVZWtNt4F0Cd1gk7M37hswlgTyCCY6jFH2OUxRjXabsrxjubftTL2X0rvHU\nWXNyNr2u7x9E2Y6GSev6M4QK0gV13LxEK3J1beM7IpoEhQCRZyeZL+immdfAhpYfpxWsC2Rf6XR4\nRUio5a+m8+cIflbO5zpxKary7+mRavpb1VvcXkV0BYgY+0kFigLb0qPnh7y5OW6HM9j2fgJm+RbV\nIQSVGZ4kCxZ6JX2PP2HyKobh+vcykiObYOqn+U6sz6FLOMwccg5A92IOesK+lqlaH8+ufZIWUpBy\nNfFySk8o59yF2fguL0iwRCH1FJ473lj/eaxQkdz+SPZK9hC7W5un8VFABNSQLXXmL2j9sAKjV3pQ\nPc+/Nd7vcF/6tGu1IMaMnu6WGfJ5gjROWoQxkYLKGHrFQUtmNTjKx6cDAPkPzm9XgJPVGjxngK4L\n+q1+Wa1loD1BdjOmVT43ADO5AKMw6hLPx0afbMwvFFNwBajgAfcWVE7BCs3qXHtYkaSjRUo4ohm/\nMNLZQcyFWxVdLdplHEnCiX5yWLUwZmcoHoDNXz9jlK7J3hIv2e7IwSCo/ThEdir/5JQ00nJIKjka\n+XjptMqhs2aSpT2lyiRrgrO4cb8Z/jAtG5VcfAM+Emvb0o3045bXr0G8NztsiMnusLbE+ubxV7JE\nNuLVJX5LxMhawXRo4hkntjyRZhsazw//IV0DAHXxVWfWCuch2Jf/E8w0MRGRMk9qOJLVUtykIyjt\nA3IoujKbeovtJzuk4QVZpQDr+JNibtsyVXweGEgnotItuWu6w086siPlRd4LyLw9tqS1ggPzWobq\noOwfd05u4a3FDIgOqNbHczeg+yM+TpTTQZZOefBFM8eA1/Fj3jyYHsfaurybxlM6QzV2Cuzzh498\nFS47VBPMVoG8mnirgD4mDcBk50akAwYf2V6Yz0YoycWFErw8tgSDgP4TIUKt04LiN7gQJzaab9kp\nL1uhmW6tGapXK4baARiwQqc+4YjdHLK7rhyEbemXKqPuCxh6AuGYVBVJqT1fTVFW4sxezAQXuSKL\nhfaKsks8nRF8iNdvrsSbAGM9HYpiWd4GyJCW/PhLgrqIJKgSXzqd9LWQPhvJ/nP3DJfi1qepXmfv\nH4jzudfKlqII/fbI2SE27vVVVueVTQlf3WnVaLi2S3X86ZS2GDjm3IjDI+Jr/S3gridvd3RJvQgQ\nPi4EV0RxtEKNZLTKFcae74QMQhird9O6NORuKTkuA8o0egPyhKjFDcleIo7Ubn41w9XKJRLXP5zL\n7En96KCQI/Yceaq2HZbGEvdB/dih5zmMRdzIZPpoOhkI9csHnmg2ZR0CKIgpAPg6www++wFsYoaG\nQNOgD85mNQqCzkL+mzvNJiGvZVAbkVOk4/6tmk18GqZcxsHcd5vaK6A43qaEeF8fOLCjXGe/WME6\nZNnUg1ysuai77IYKCQcOuOKofazbJJ92xyJ25n7+kw5po/Max2fmG572qhZ+10hJIqEiuH5oUpKg\nuy9lgZi0YRDssdP3LQUer3tQjLV0gDl6+a1RPngKc2fMIO3K8SA5KZ3qDvc4dBkNaFcreQrynm6U\ncrr9cXWR8G0weFuqqQRL90IuA1flLTzRvOiF6TOzMakbDCHw8LWQqG1iXFtviO4y8l4ej0CKc8E5\nrWgLOjLMOlKRqjulFynzBSrZCoT8crk3m0u1Qv9qL8p+cW89qehUpO4+mbvKbO+zqGSE4fZyWUN9\nKhzCMR/hPAFClKIeP0Y7vDvGZDRjiHpnOPJn19Hy3/CklHWGsOpSmS75OcaIdQkbKusZKp/HinIE\nEOT11iRKkfAEv6I1SjTTDmnSPlLP28aMKxrevr30RKNL0R/iLibVsy6Urj1DFQsnXMcZwTzbnLZB\nH37LbMO0FTczGHEz4wY7I42hgo5Jbo/Ok6n1aikZ2kzdIwPbRukW6NJg6bfLY1MuLB9on1nL+7eQ\n8emJHvExxSYwkh9cxdDqmt9pZjfFiNJ0q3CZnv0SK2iqWklbrTvTo1Yg1uHYe47FL6zofCptReGf\nSb+TWF/AfKc9+ZNaaumRS2BeLWwmkf+DxE1Cfiaen6L7zSK3I9pPWSUhB5F6sPUeX8dwNZqvSMkQ\n76GwRNweNWJopEGnUCsWkzL26TmqWhuOgTupGydKmu9AI72wfa6NnO5OhYlkWmgFrbz/hrxCCTXB\ndMDTDT5Fhox2h2cAFYVxPoUCbTHbKgsn6QAGXZgTze6M/oLO74nm5x5OZEDIKQyvCehCBvwNsDX+\nsX/iPMKgrArW4FqkMb8BlUrdjyh54AG5wrgPOj85r5uTfvvO5WRou62TRbX1gswqSK1HEk4if1CH\nDn2t8f8b2K7HdGIokRNNPeHaYMzYVwW6AmlqGN0g96SndBhz08ioxYGGoNJPD4v1znhFxkGqMSi1\nPpLU8sdPTZ4nj3JKccZ7rsCxHGk3nDdeHqAaDiw/1xYguaRMeGBOLSBLgNZM3nXDLleIoEOgoB+j\nWY33d4pOD5VFuuRuMfaJwI98pWXPkPQJ/vrulULCuDCwk08OzqR8FWMTtLY7n+Vnswx0y3v1lkNH\nyWWJdvzeX65qGh4uiYWSV6ZBhCyt+e2A4TuWvQJW5xY+UVE6h8Z52NWnCm9ueZcDYkiGd0mVeyHT\nNiwq9UDhrVZ0O5TIDZdAeST0JUT//Jp/44+P7MY6cGfUCvexb1RDCQ4X0if4W5id+ZLBLN1iiHr3\nn5hYFeDOU/pIy5T0PgOvrfHOm9L/rAAoGw3gf5+MOjy3nSWOCdoSKPb9MmrCrfUjupt8RhJQY0Om\n9T46fYvc4siUipXQVl4va1u8VfMheiCM24AhFbvv5fHoC3e5U1+RaUtqm9k+XjiqBFxJQQWbRNlh\nF35SwrQuQg0uO+nFFUzVJ2bsLg0eRBxvy8It3+oT7mBFcJHLRO5d3X62AV9S2q1w4EWZjNNzAUT4\nH1ObrM2PV+Xp/vVbPwxOISoSVR6tyz3xPvEROFFQPAHxkbHqO2eUG4ok5cGabSegvXWwui6DFXoA\ncK8vLZODula8IhNI8xpJMxODIukwXFnXusn5Yl50/t9jS/u3ak2ejgen6QFurdGhMhh1NyAieLJi\nNehT2apJ1QbjZIbABozMm0Naec8LIvo//538/mqDFuJVg7NrUpDE1PjJYo2XWiADB5lc1B6O86bB\nVhnhcXSQgSTW96K/2U1Na/vfKa+v/51le/VGtm+9qu1hoYl8POkrzMRa+5F+KzPGKza8w7fzRR7w\n2fmBn7D1YQu6uuZXAt7UQqZ8h4ooY4PDxeWvv+im23D0+JWjCMQ/rlY3W43GkROKICvVtHGI6SbX\nBH2D7LJhJ5TvDYb4oasc1tZKKASW3cPnPYuSGIhIPuYmxMMA7jd/KqtT8glFYVmZVnzW+/m9Riyv\n+REJldqTEl+pee/3iaZKTjJqozOzrekrcgRqbKyG/A3m1u0a4185WGOqNr/KxbwKJWrEyc76V5ie\nYqSl+3UDMbk/PeDGRZU0LztNnqqFNK38dlB3CQzU7IXC1Evzmg+c92AVpDl25/GcUdfc/hXrz3/+\n3bOGsQUzP++wrmVi64kkpmJRQyqVScOxfSIyRaTkavbdffy1Z9CceR5VA0g3KmuNGvAD7ledI2XD\n3mBZEC5pjafkq3LzWew/3vg0EP0CCcOujbNk/Ggf2bqUFwlMv/jng+mFUA3yJ4KNFKl1wFbGcel1\nqSb+jdSnDgcBZWsa526RulK/Yi3Sx5RKJ4iUxUEwZgSgQ4YNqvTrj+PAW3G4rY/DEIGMGpCzlKfQ\nxEoFmE5hKlo6ylqN49kjsTd3dPnT58hFxllPbTwmWiT8gtORt96vHPkSFLHVoMJJFPAkO2FgbHhv\n+aaBC1nvNVAqu3DgGSHV92HxU9a0ep4mFZG3zotXDhMZDDYN6jQXNMDBg/VaODOr8JKAPlt4IROu\nkrqrohpBWcbhpocO4Rvij3D8eALnzQKwku+PLBAfeTOwdrsK3N+LOud/MUMkuTcwBCI6s7Wqa+Mg\nX395X5s9I1FTOUO1fUuW3U8gvLql1dSt24jgzhEfGQxOkSASjHWoKPz84EPnuEAABuSPhWB0BVph\nKQnChT+FL5pcvawnM1oAINYHk0yrekcnMTqyxvKDE7sJ502fFeEPcK1i1JdmyPciWsc8/CrXEzFW\naoEORMtE/bzhTb/XgLv7BX57joNiwASKPqq+RceKw0o+l93YqXnHG1iS3iaKPPl+Mqv/FPWzpFMh\nQn8ytHYy6zV0T9+bf0lu7jioGLKbd9ksq8sHb6mVRweXMOsqy1wOsKredkuPtjRfIwCLirlLIJZ2\nrPcEb03bRoPrH+336P07nl3hpyGJ6hVeLibYtzBCX1HoFvgsOHu2CjEMtnjmUqNpcI6e068rUlMp\ncGvOnu3gS+hOFEPUPI5K3fYmGFexqS1cguN6GouEtiJilw82sIwcEzOyBu/SPDbtQTuO0b1Wtg7t\n0PvZI7gIghlnOo+afvpoOkc5ghIrbHClsXZDtPLa/o+H56jQhaDAmrszeV1Cv+zh3L6pS3dA+qKX\nlhSlLNSjcT4OKFtdK3Acuw9uiI1AAMy9zO60LUBOHMu6yriSDwZJVZCoFwJyjbt578KGE+vIVvnL\n0Mi6+4vZ0gFYWpvrjfw/qAAUSOBya7ijmBdfKNlG65/3LukquzfkCVGhpFZmL0XmIAFtNKRZQV2i\n5xc3nt2PXVqOeiCARjcv79AhhxVBEIX6Y5G+n0FT+cd2bko5HLpwaH0OyAMK11qweRHxeoK0S3Gi\n9Tf25pFRzr/mDJqsIzFMIAboHQJ1/mbKcIX5kQVkTosBMk1MgGQTGKizRmTYwMyfUsI3PW0biCY5\nkbFTjWSeujDzAf3FPOdgCm/I3r6yGZUH/aVH9VR+d5emYl6j+1j02eu42UfEQafGg2xDCEDUfH6n\nJwZKV6GgzzxWosPKt5ifkV/99UdsOD4U2p+y/D1yO2KLm5soItpx2AUL2QnBtUSqtezc3B/8Amd0\nvK8c5Qa66J8orkXHtprsCgk4YUpda7P89o8dObn/A2p8wnMCQBFggIim++4/4TS+0vsIFz3wGcdX\nzjn2QoCOKwV+aL/lMrqCMMxTLZY7rKWMjED1Zh4ywchs6wD6gAcubiywerF52Rq8XD8sk0VGauEI\nnO4sVNtpec4KPtZrD0KmchrNzZVa6fDxW7suDfbpZ+Gc/vFVEi52byFN/jwX7DHPK2RtFiYeF+G8\nnEMJyK0UsxzD/0NLofiO/6XVRRrJ/i5OoM0yb1PvdamvCUDbjLC2OK6n76vuene+9829qu2cl+1a\n9IkCMd3xho0Of/MlNFvkcdhz16AODMx+3EGBXPSD/dqjUkV7CnK79A/mjvIPm1cihPO2VgEXJ3ku\nNQrE+T/cXjgh0+VroP9xoVO6KGhjI8bQ9oVr9RUU1hyZ1I+VBvkVfAb7twsWDXK4NkKjvnE6XtiO\nGlCEthxmnMifR5Xltkh9BZ92VEZ2V/h5Xf0z71CjvnwZsVVeOQurAciM3/ePmxYPUT4Twk1YK7R0\nXQyjnpr7gha87JacsjbwKUFbj6ScFmF0fq7Spdz2CZB5RjU5JHLf9j1DzGGOLAreRiLyB9Uq7Lpq\nfmU96o/Ofn6xDWEhN/G27VnkbYox5V3eu89ehpLhloHHfNQ2gWupCZHkNQgMKy2QNEz4ip4gbtdo\nyueTkcX2rPrs3/EHfLRzFh43d/cxVSRSDhUu2fKpVeO4/Cwg5HnrUd1j8y/VD66IpURxy7HOW3dB\n3UlP+GNM7VKkG1FtaEy7S6xHmbrCmp4iXWCjb3C7fezLok9JPCAXRYDSg/cV0Jzsuf6YLRuzvvrf\nBqsg/pvrf4wcSoI9AdKTWeebLV01rlQKmOwmMBqH/OU38I0+75DBTm1DvcUb6K0I+OERYqpKQ39P\nkifVliRWIktcDum1xZP3X2H25Vw2gZ8dTbeBpuhNKhN1Uh2E5NIKReRSbmq296pnAy4Mfr2f0G5N\n5BcN5YGaucQo0bN3kHNl6z6G8PW5iRYFfbEQOSWHYlUGkFCloSH+s0RiSbTAV2l/Km4dFvU1M5UP\nsD6YrY4Phst+FfiFUTWrL8TN8iO02KFpKY1WCYA90kiM7To4CE+uoySnBQ8jgUA12uWHUQQvHVpm\nmREcKw/Ko1t2ammy77QpMbD3jQ0dPUjWuLgq4AKV5mpqSDTQdeZ0p0kcjH28evKoeysgEJs9iaZd\nuB5MkvKf4rDxM1jVHWOkv303ysAXEkQZh6zBTRcMaT1GuacgK6KDuLDLKVZ2QoWwFVU9fnWPbY7/\ngH5Ts2YMUUXmZsfxe/QYAtcCyvOh8V0KkQt+6UmCGaybI15Jrn+f6+D9gkg4/O9PIHebc7qHkzo7\nvclPG6D/pzNS3qHPQN8G/NNdZpHJrU/aFhw4oKHFSvnmThMCS2424HRPE9HFlgYYtG+X5SmDgNGD\n55m+9XLYwUYGHJOgKUydh4qXJd91LTuoE735vf+PXf4DuQ7wuXBecmd04o4Wttfwbo8Gz0dPQjw2\n5ik6uF1xCre+v7TthogH1yFghgqDpKORPiY/cGIwEFEDQljxzgamcYHiwFQDeR8mp4kUjczLt+xt\nDC8V1d4EZW6qQXnWBNvbLI3I6tmvnsKf34MXKfDHAd2P+rD5S2AKJtjOKfK9JLiYOfUWFhl2/dTR\nLZXJybBzjW8MfcJmLpg3e+l9drxnyth3rEmoO1thWxIChdkj8uXwyZ/V8miJEFokA+0wl3WhogDU\nD3QM8qGqyugMZdOUrKXLY3mJY5/QqkMNHynOTXCmEZ0MIIPODFIHIvt/EWpC6okyj7w6Z5Y/EJNc\n+7vj+kvxzsNMn943Isgsc3CBiIjhu0b2YSuBZTpfTpi6Ed0IG/v00nGpy0n2zIZHV5anWLT1ntve\nCZpb55HEf3E4HXqRaf58GGU7PkaydMqHTYAjryvSLzutyCDwqg+Z7XpcDQ8TCRzk+wuFNvSfQMcq\nfyn3l4l90/OKJMcPgVvnDrhrbeAEQhKLHbODT0Hy0I4yXqd9BbKCrXP0bGQ/9E/ZNLeyQWdsVt2/\no1f+6v2Xs0zhbuQnxuQOe5CPadNtuCG0/IXyyGNUv+Jjv4wGPXLduGDd9ZyM8KUD9I30n3S5tb0G\nTeugjQQNbXeKZQxTAaj6Q1Fkp+wh7qMiluZkNYS4nsPFUKhNgYCgTW8wt8ZntdKlWqjuB9hbe5Yj\nOA6bfw39HddcEmbOpaB+twkwcr6hxXz+uEKnGYJsLn5NSaEGGmm7KUDaOn2hZ1P8Y79Bp53DkEGM\nVZPq521OrT3CzNXFTwgw6BgeWhGN9nIHSYwmIdR5LGqwvXQGanDECT5w9Ev4ozypXaZM9/SzdPL0\n7afOtIkPfhEtgMgImH3Ic0d8cEmAEtKZnmiuACwVeSjhE+9BfEX9fP7xojDMuxRykTawLs0J19ga\n6Guo/KoKl239QJJAAzlilFpD2rWmyZLD12a3NIlgsoA18Lr+JaZS/r/7frs9YYSS+zzPwmFFb5SF\nTI4AaX048GRJazx48h4Gwfq0vgYimGzhmim/Z5bUAmy0rk4vEwwf+w8QPnJ5Kr7vkwNm8fbIEZid\nFIiEXB9WDEjVd+mTFjdAlXygWf5fLwW3eEr1gdqhiTJMBMTRiaaC3u/4xu3zwrOmxK9pmtrOSe16\nEAQNrThReBM9QaIRWhN6iLdhUcVL0I7XEs0SiGiQxER9z23j84wzXGjh5ZYOnkKufUauidk1R97b\n5/GBzzcwYH2lCegpxu0AMRZlaxpr1CV7KZCWvnwFL5KNwh7rxs8tqfkVchOoV5NRUnKG/M3oZrFg\nBt70m017cnkAA/ZKWox2iriNqz1bAh1MqhtVUuUzA5KzXj2hkx1j/NllL7foxCPvDJijXisk72SR\ni4W/3wgC6hDYZ9ooySDsHORe30hU7WZSjWiJ56ezbYu/ZZ5FQjUrqJnCiMcydrLh/hrRHaOyiEBs\nIipjErks1JgVqicAZmefDd1h/I8FPrMT7M09OhPo5W5HsQppo+ayFDuwP0y/9HRt0auiZG1NbJqg\n9WSUL+MAK2WL+QBhoSUOLvxdJEQ36oGkOT93lsss6ngy+iQpKW9Bqlg/gVUuKCn3kLNMiZKNAZMJ\ntm+MX6t7OIEbYycRlU7s3vs1VNVWdjbevdj2CaEr+/6cKLC5xw+sOMZzWmO/6GUJzToXmPrjnn/g\nqx4SI0ZG1yj+GzvrjxxQAwOWd8LrDnxIpiuY/n51gh0IWXWdhuYSL1AwF0X2RibH6YJhEq4QMNS2\ndV4QMMLd3YbFaDSrUo6V3llrfSy8JI7vXlsreKW9kYObqhJEkKjBIIHH5mSv29DPAEiWmNtl9nfl\nWSvus/Ny2zsRQS2if4zPVXucmj7UTNr1CjNKvyfnHenQ0nR8feDa2eDIbZCCn/RWpIpFbYyNhbfK\nrccggfUvEfjUrx1R/O14bx/sVLnl8smgyvDBod1dXue3F2BHtHqPc+sUglQy1jAIxfWRofAjZ3X2\n1aNaTMcI7A7r6VC3oPsn2lNk7ys0Jw7ikivMFsoyD6272mTzk8jca3h42nkXfwiJm11FD20D9Nje\nU428JKPtlDjx4eVzdc2/i/LFixIdTQxHoKt9XLFKRlgWRM/quVSAY3h/kJTgqfMAalZGDuvAKNLf\n7C3mRkNCRsyMggivcH6pMGz0/qUugT6OHAFaFb3yW9ZPNgY91yMvMMX8LTfZm4QvB46ghDgLK/XA\nUZnZFugsnWNiZo81cm+hCHy+dcK1GDoEYAR16V9SuoKtJHLiWt/ODO2em9S1nqjxdrPejiq28mKm\nkdRLN6FgFBdZINmoLhqPp5dQLSVH0DZf8kn6NcXU6NhQvCG94dxpQXgkA2TKlgdEdWqCmHhuoNWS\n/lEBxCnhfW/pMu+OM20VCZGS3krN8UQd2tTLbxc54cfJnZRabToPVvFSBxjQB9jabVJ8+14DDtIg\nKKu1ZpBudC+N2hY9JnInLplVzUn5+csYkJcnJwVqhiT/ujDE8aLGg7/ralNc+dcfsT3FQlwI6Gk/\nSBH82pLEKQ//1U+Qrk/BbuUeanJTkA/+z1rP/RqZr0IjJHz74tpWX4Y2fR6KNB0fLH54ai4k5pk2\n+KwIpkTzX0DB74lZeZsDY+cavOPEaVedigYQl5rWUXCPBqQiADZzA+gPJfsm2+Fh4P3Q7EJqZu07\nRKiDkoVXROhqr4EcgrDcmplA33LynqmL7yeTUoMYOYNOhoE6iT2//oML/5/KWfFVEISeBtVzsMXI\n6HAcqwKqYJNRrOd4dWDeBkGOVRRM1qp6Tv+/QHbkYigc2lBi2WohNMW+EUfg5yMuV903ne4EA8w7\nz4YzTLr4pHMI8k1TrNY5MjwTnNKQccUjlHawt/rqMtlat+ubaINzs2t6LGFBiRL02oiJNy1v+1tR\nF+ODcxG71ihuphGgPlvIAyW+uOpRh7PKq4H2KOVmu1uSOkemH5hwLaNbSpVELWYTHqyMHitEoSfj\nqqH1EBHnq/ky/7b+9g1pUGmacHViIT9ZN61ETq2tEheNz4DQ7jQLUnowWy5U4o4tYUtplpOwr89r\nx0e26LgInT87JMosfEnW482p3HD0SPbmCKFL8KAS+VzWmmKmSQucPP3rWYfy4La19BZgyk7PF7eV\nxdTrtjN83cBEnYza+tV1YLrzMYdXOTOvRBSmFupvacX6cWYK0Tjtxm14wtHPmNmf4zEADEOJOQII\nXqiizBwWm1qag7Ldx5ucGooSghFG3N9Ia9bTOLq4qagh+fSa4Kinhpzc16ZWisvwjPdX2wxgSY+z\nDQbrOG5tr3DiPBQ0txvbVdah5rNJ+IqZH+6QB1rAXAs8CeVMxGEa+49UoCcYu4aoVDolwquK9Km6\nT9403lzl7sM7k+RV8hsUv3pbWlhhYQfqfk/7uGtABx0nG+sGOu31N+tzpxTAsrofI0pk6YsTo8++\njKiKWGMK6s8fT0UVH/JwM0vUIcY8TyZQ5pKqi8eyLan1a5cOaWFU2hQhlegjpLq/d7zhV9rRQQYl\nj3b7ahZ8AlAd6N7oDtsmXCBo9P7BZcrGX2BwsZYvP4kSVXdCORbUToySzu8wHmYlOTkwheM4l7jc\nEvkqm4xkCx69gXuxnJILWEjN1mePpR2SSuc+/LvHe0ImpqEbV47o0MtF9W05CaeF4lmXaKQ7uQQQ\n3P/EQG3Rb3I4AtZMtJ9mG66Z2FtKNt8laXP5RXALVumzhC5+kUuGCz88uT1cGSWCBNEQrX1MCDTj\nbneHVptBZxJaVfpxdYWqMdzJ8VsX4vubTz/W/1wka1SavN9JPVABNdhQLCgYOW698chbqwI1OVzR\nTzkh9aKxhV5DnYFL7f17FwXChm+jubfOPLJ1UOTC4eGLUGgdECmrhuVbAuoteZ42mQTbuPY6JWsz\nyt2SDwPy4qVPjunFwxW0zt/C3p8urlTpb/YiH1tXbG3Vpy6cMH2fP/wepeh3QryzJuFzr+2yvSl3\ngqXCOLuZeWPE3n7p4IX0+2KE/7uL4IJZXuThKEs7KUz2Ip7IohmL58QJl14MHQQERQ92+8HwNARV\n+UCaZvOYZZhs6STQ1USkKIZgAYgNSLh2cQ5cde7eRYFwLCAW6xFbeaEBFb76C87NhTzLFMI4uPrQ\nngUr8+g5BOqezsNNMmJNBx6M7WBro2dRXLgWC4xQsquhuE/QabwMMjfEkxdGnN7TnKQZvQqiMlcd\ntVsqRTadIpCILviVOK8Y4dq0eRTEXwi9dUKXKkEK2pTkgxfR+onYwm6rFwIGyYth1J5sIktuwzC6\nNBfnQ1d5f+HLwHYwzSUFnhmfkmvS2bW+GmoEl8F52WpQVgYrdWgW7Ygd0Nmbu+Awm10SapCslw1v\n6GHeeYZVlg0f5Wq+CVXY9NvH6Si+pZivYddvGOiFaNuPdqLOXL+18NZE3tMs2qQUZcw0+JmaZc14\nH8Lc2FD+WdBF9Tw7SHW26z4H96yDwPSMdTa6XYrlHyfmYu8swKmEzh32ZfPje8E2B6MOt/u9xLet\nhcRG+/smy98Xg1SOxemqpoF9NR+7WiFZTdiblJRA/K/nsPa+JroAU6jMv5B2CB2U1gfMVwBD8uMS\n3gD0e5MPeZdVnpjJVuv3WsVBTfM8zEWTNk+nl9gMZo2czZ7gBDnzKgi5TJ1siwFWNxXNsBVwYWPJ\nJDJxmdqwMNJ5NNHWK9EuiqbL+JrGlszE6pA+9uXn9VTWBM93DMmlpaC9x1vJg5FoX6Eahtbb8HyV\nlPU7FAMikjpCL3B31GCCyrnnc3G5/+zbnf+Qr+00bfElXYkl0Yo4RqZ/WExjrZf3TMYmNCi871oA\n3+BKvmGEXkX+IkbUvTlJTxh+hDsJ7sqzClx79eE9OsEmB78IOekB5IlYu3RKYCS/33Iod1epiKhx\nb83oZSqAF5abVhSc/UWmujF3tXqkAP5atrnJN1LgogfMU5Doh8NpJKHlzGN/sAYsB3eIxB154ApH\nUDJ3KqGKPR/PvIrh2EMLV70r4r6ghZW5gtw5O4cQ21FBSiCNyi3on+CWS5Lb5qjIDW/HN8vgduNo\nQYoklMuBgFWhxhjl66DM3TUu1JzgHsYJfM0bDHOyWkU2NkrUhnBTDfgXNRET0gR8Z7h/2HOKC+bj\nurZOAPjRTI1lDSX/3LOlaEcmOLySlv5Oi5WokVPuMG0Z9NlGEbwBCkbfL2cSP6oYN79xCNSFi6XG\nWlM52w9bjIqZHIS1J6B6/uP7T0B/BvbuDhBZZE34aembE8xo9DMrUu6lIrI4zg3yYUpjBzIrFUOq\nhzUHqol0rf/YGj7mTPO8m6vtJyxS0Vmm5Wrr8h7Qa2ajMa+xG7rLZ17k2ayS6mOHuxHjbrMtGolO\npeHhdAyRMEDCqHnjBLj1IFWlfTA/9R8gchsy2Hi04mcjNCYWP0JEmJ0+IHyEZ8awPPulGiHJD65i\nEZHjtEE5/QaxxmYLFefpF3s6kxB+GWOOrAFcNlNWh4wBkv7qPNqxQ1G23xS3/GTX0OBm7lb7dxDx\nxSufWcaSQ15frI3x7sZZIcIX/s5L6NH4oBsDNrHX7kG/K9GdPT8NXxYneOUo8tWYzVdCJF3J70MH\nDSLfK8NhecVyTXGI9F1AWWO/jb/alwTLpr+GVL0ATJuLfSyNqoa8NRcpHgbOq+0UGtxkqDc7T0y7\n0XhX4HtcgjrsklUwyaKOOwcnjK/p3COboUUx8qHXGMboCSbEZ8TEIngCJPdY4JPwVGxbQjF9CUAe\n6McGTAgO3DnND2CGkkcPHgR/4fc5ZfscDHK9Sn/yu7lEK/i61ewWBRdXR3FP96MYVIujitlYrI26\nbxm69UjiwzoEraBECLbMzwPsZSDhxn3vhkbyPolP8drORt4KOsY0C64FzV/mewZf8pfl8asHjsEg\nWRfOlVsc/Vpd+HYnJTiQC+oQDRx6mJ/cD5+06SRULT/CHsmnv+ZHujiJTkXia9wif1ozeZHIhnwH\nxmt7kJuZImE2LG/8M+Ae5bsSsrkxUoVYEbbOvyEobwJczBRHFO59gsOcV3lBKPbsjWubMQxcz6YV\nkVX5PGRIKOAF0n5Zao4Lxsfxw2ZgGb0lcnwkxO9Wl6wb/yOypdO8eRLGbywva2Mck5QqTpTao7Lv\nILjrqow9+1q12cLHmUKHgMVxQBL3XCZBtj0ukmk7KN9agwypCT07EiDeL64bX5kkbMm8ckzAiif7\npDZ2O5jWRrIHyCf2UiDTiOHKhZQINpqwuUYrQlVIoFPNjnr2wDthdk63oNs6QDMZhCjEyYd+XC2F\naXThHdnmcH+mkIv73rea5jNhulb5l/dKes37BVlYcg6AzUF0YBeY2hkJxdety/jpeIfp4iPGaC0K\ngK1kqlFJcbogM4QB1RSnC2h5PEovDrW6G8dEXtdXDhdXz9QK/egx5Vup3CyaJ24XJKDbXyvO8NrP\nrOtvlEdqtsS1AZG/iKRDBq6w72Kmdvtf/xvieOENa+F7Dar2fZFE8HTKpcUyU50cGMN6+MRz3JyR\nuxTQQtVX+hdXOIup4a9kpBWkbo5IQf/Z8XB2+BasBo7BM8vXCbM8EtWhYpwOakeVpXRfSJfrAyE/\nNr40e8CufVdZAOc1o9u1QdqSiO0IYx0GWmYXalf2AlOFD85Cp3ccB+UNLd1Rcr0dy1nnP6KHtF7+\n7iFcY11h+c61mFdw/BKabN7PzBp0FUMmPSpx047kuDxx3CiZwwic1bcMaBYeOECDqode5cuuU5J5\nrUy2W05YGKfnxKEbRa4SCQbgUxsg6hFZ9Vu6qkis7PV2WSbJw64qYalyup6o/GnJr4grS7SCA62A\nDHZSn6EnNEQvNlDEMm7UAsvQbWVJfkF8yF9Dle0iyBWrHBRp+bumxymJKlVFnrbk3QSFpujMtTT7\nwqgTr9y999iXBPl1QBv0D9lt5KV3au8TJIOrUQDRsleA6kBbQAoXlrqPpFGbXMreLZXIHDcQK2Rs\n4LooLUiTn50CBcJkgtjc/ucXmJVp/eX8G3h2aQwzf3FuI+3OabWN7NFTGv0wSxSDAXvtFgWBXlEx\n/yxvC9sYcfRIRM01r3Y4VLw4mCiq45qk8xGxR38ZcwRHGEUl8WDBfCKSnXtNbaC2zfWqYT5EIFCR\nQZNm5zkJnDBLolyqAqG/HsouRZSUvyqq3zNTo7xXOHDS2EF1Lc8p1Esv8olRvW7a3OmSnohP0ppv\nhje4mIxNehkAM8qZHvE6liv4qQbivyBLE7PXaEIfeT32R6GHToy68N3x2aZ9BDL7yaa5u4l8wPqc\nogzyeagjUlEePhU77oOEWK/EUoa6A8X3CHFV4I9/U6Pr1ekYBzg0Uvgby0X4VDJycLLXYqigcorE\n12cITDHpwIZsuP1QWHDeiXuwcZpjwwo3WOAsREDvqdu3cDSLKj1zc92a5K4tUsfojyCmMZ0qsPUW\nPnwvan9YQgoyoieoQjFLEa/i6wvphqXdBFGPjG2t4IW6v+TyeUCmQlSnbk7kmXSxALheZhE288lE\n5AGamCYNpjgnt5u3D5QwJeIX6ueqnpHY/LAVn8g/yFW+06tr0jjxeI3akVF534NgSp5c7b0ftlsw\n7tcMxQDdLozWGbROAyjDXn+mqgAJh2tsN89/kVR1m/AMh+dGJXReyjGGWrByr9q7OaxP7Op+dj7a\nE0iYkWC2TqIVEqqxnTIAqPz3wa/fN6tMp/clKgG3VPW8UVCa1bHBYYTUqtiRh6hYkmB+kgVyXYcE\nHD+3kwTMYQNF2bDVWkzfRRBgNFdaAbipMTr4FMbMjlK7O4OVVwCyDJUHVp1eW01f1z9+FmYU+uwZ\nG2vYMIjEi+Wo5ZETUGaKi+0R3WIVxM4rOM1bMvYojgyUTn86ShjcLcz51G46xk8YGtxunPqGnwxO\n5aWKBx2mvtIoAOzLZjAIuTyCQudiCTyKPhKr0dUlIj5atHsGvBSsTkaOeDHAvcg5BQAyoJhy08lO\nz3DtIRXGw2WEZgOK0qHcyhrTIV7XHkVcxMfOP10jABUX4t7m+FaTcC7hXImjkH4dZqUzL7OnRWlL\nYgbQ230YyFGfD2gCDzzbtbhRwFc2Shml+sUXFaHHo2bH7SDAksDc/osdJ6VMMqYhbcqqtCOxciKE\nApQr7wyeozZxatvt134GIGIfogoc/J74CY7TssZ/lGo2h2My4pzeFYWerkXsdl7x7xXueErMyrD9\nu6wpxXbM01I+sd9SfklRWvacfGR8z/V39xz3XhAUH+8Zdd9A6yLEk43uBesu0lB+lFSVJkxJkuHs\n0JrYpZh3yuD0CWExkzDlWQ7IRKI18JyOuLYJ7YIA/9+mZHtM4V6uR1PnoaIcgYvxzCnS2KzUgtSo\ntujBbp8ZHMrcTurpFezE/ew/uqWxl3JlOxXV/YYPe90xc/nvLi8g38x8u0T5P5yG9xb4PhG3/96N\njJ2wGWGbr/LL+CyrbpzKV+2HW6inRkycifVz7kJhaCcZqKfXA5bTdPfjTwztEUdB+uNHHH/kvf8Q\n1+LdSbJB/spDnYyY8p20dDF1usrvwBbBVLdDYNzlQC66/0CXQOK3MtRmeIKP2MT0A1nImlleWVSx\n2DgdZhSGM3s6Etlo7ewpNI2lp4lYNJRE5n5g8/Zq/RrUo9UA5Z25pVInhzVGF7BH4mbyFfsdLgEJ\nQt11KzY8NSpjmbV7qk9n5yx9L1k3LaT/gJWJQCXtRt7dLxH5HNzgougW23vHYXegrffCbTFbKNdw\n4I85jf/qF6fp3N2Ihr2OU8epdGUUK0Y6F7zwHz0x4YFoqTPTrxsXwye4kfDq7DenWE+ZEfoQdW7c\ns+PLuepgqQrdl0k6nHlch6y+ME5qZEbZ5JRJS3PuwP+/p/Pma/o97Hkuw25i8qCQAkWXBPSJT4O7\ndpUZhH2TFgim2fd8SRpPMhKh7QACubnIpHZY89ed0B3N2h4zGSu1FSUG9V012iAYF1lFoYNcfixZ\nJ8ZNDT96S9GRWK74QLnKsdj5W6ZnszpbJgcVek3HheQtjRtaJ2L4Sb9uv5ELqy1dB5KoBLb4u9ez\noFJT69AEwMxRq7TkZORXu3V7iiiHa20w4db7HW4zWcpb+e6sHV/IJ4+6YXGt0PPSl9YbeGo2746g\niBSWAxFjcUuRkX3nKVXezDBOxTN1PxlkkjqQDYwTMTTWjajYI2nCtqtfDhaisALC3ti1jubdWKuS\ng3fYlDrdNE7EjLkSEBI41rpxMNyWp2lrXd5prsLlQSESAM3WuU9ddP6ieSEZDlenXOA99Wl24Lrx\nYVzJZqqZOOlhhH8Xkvk6mJ+soTIc4dFRFit16jUt49fuougWX5t3kGGiF5ubqqRET1j0LcUQztCZ\nV0gKCZEFD8Qz7N1pgceDXDRhvT8OMoWBfyqoi5HvzzYHx5RS9qd4STddFLBkDXJMvOjLa/fFpbgF\n6fIMiv8AqcsWdk9UmwIn7iJcamo8uf+V+9n+OnxrCg67Uz7iPs1dLZQm3E45AUB/tomQvKBNBXij\nkCAYvLDvBtVpXQE8xILN6uFRGzx0PSGghQwpcUlTbjb+BnF7irVe7ndmChc8g4CFd0LXo+/4LSbk\neByPcXnkbuSOZ3iScuzfnuxpNWYTMI1ZIxKV4+wZpuUtdlYoIQnNljAR4zxyvx3LVrw8kZA3uWiv\nftbLH+UmJ3ouer9k5jfMljfjTeDuYakqb3GIVcuW+Jguho+W7yYSB1Ama4yPnkTMIRaj34wXfnA0\nxuO7c4Tbms3F6b4b5hL6a7h8ShkdOOKwZ5JUgUAirAWYSrr5Gfhkpx4C22zTY0cGA3MCPrtRtedS\nu/7PlKLyajLanOUrBbx+CBpkvb9DsvRUFG69SYP376rhTFFty1l1Z5khKGpBjrMP0j/vKUOpelCk\n8ttjz5LSARM9YwHJGRUWWShbbdyiS39+5sGpPH9Q0zIATt3N0EqZD40v+kiLRWTKdC+jBemcIn8S\nXJkx37ZZW4dS697OR2DpDOTfAj954nl633eYLBE0W013LXc3CHNXe0AhMWG6GF7UVDLtdPqnCCMd\nRdwlg1lfcWgbS6Lfux8SlOyuEeuqstPe6bncI21OfK2AdDEEtB3d6B3yBYDbwQnoeeGZ/fubFn5o\nft9Lw1MAzL/mSbFY2sx/xVr0GjgL0TN4jbXMrodz+ujDwosd0JrzLiGJW/1pyAQGT+mJTa/KLK4Y\ngVZJIMtEsqBllVAFxNSI8u5wvCstBepuauQc2STwRzJXvWVCSDpJGF1DCyzaGQ6nZZ/BhfL9m0Va\nFm/7KV6bHLju9FAIMwFTpmqOqeCxp0kpxIcwDcn9PAGKkJcch5Se0mTMc/72xt0R+5lX+l4NIGWU\nQ6EaUaXz5v2J/4Jizj5S362Meb+FRCjxCfLAPWHmb74Gjk1gPlT4s++/OCqWWOZxhBSP82xHH6pc\nZp+YmcfcFGz6loMuci2lUaBPEx88o3UURQ9X/SCi0h4m3Q4RVDYYyJbo5GauzmCuIdhvaoKjbUv7\n5Tjdbev5HSe9VHWIWITK/tE3+/tTDgW02qcAiW5c3Pm9kG/QzOqRyJZsSGIz6hnETcHR4NFGVJT/\nil4GE9qq7qX0RtFeTc0kykdOgbZjftmx/XPbFEKZesFgiV5SKmFdqMO7ZI9yYkoiN9VhaKg1zcx/\nze4N10RMKPEKF74FyqHeIDB+pYVX1JqMB/0wzqkvOU7jPlJOwGsmgXlZDRpsIQsBg0H+esP2FSgM\nDLzO6gdE8Y8KHwnwmpF8/pNRyKAJYbZ5Nduq8n+Wf45b2LomROjN7+7FS7Mi5gPlIwBdNcT9T/+z\nbKRMjg/VaLeoseA4IqGYXIo44xAGNx84qGenYzT8vVTcyw6JP6egyQXs1qtr/ZW8bpUY9Dh4Aoh6\nXYiwEzM0sNZX9KMR/3mYP1HfIHW0+1IWdDS4NG25aNSefuKtFhYkg79E6NN0SHqvwMYnfT0A2UuD\ntrDrs7JCCvmgN6f9RNy22MQPzJtl64f/T9wYRQP19wA3esKtv7uvnL+xaHk3FrH5Dc/OT3jvplXZ\nEa9jwzZjVXRDnjG7BrTAxlOnmZ8hwfXHw3ucTHKyLEIIprEwpN5qDOP1KF/gG9sJcIcxs3pM7o1h\naHZL3aEVWoxlJ8+JxfMsPxdPY82fFZEJkHyNKC6ryLj8tehhBqSyTM7KiqpL+oX8NldHg6Vf3fz7\nWyS4ZfXar1MYCTweAxK2SA1NF54rQSIBiNXiQMm25jHdJnRc5S0k4GLsiENL/hu2kJ+lWzwnuMjy\n00wMlsZcTf3SlCCOJ2w6OjR5Wo4tCBtV/s8LuMlE3BIE0QJzI2Qh6SIvKXHyY9W1IbjPHD7dhqHo\nen31OR8tR9ZvXNShX9VZ7akE6iXUmazWnVRewfRRQ/3qD6/VZZnzbVKCy0MstqUcbzDsPGIq0Wlk\nIon9Ejczo8/fbnn7GOC49GIuE/e7PdfjGb44TkSPumyDXePZYQKit0Or7132ivY6+DMkr+3TlMmA\nH1tlGQMiCc0lZd8bapCs6vZSUy1eGNho4/JAdMOXpAkNo0Lk2s58NaSLSOwYKDtRCjQTQ6ydGa/f\nylu8ILAGpij4WeqNRTAS1LFtiJ1iMvG61SH7kKGt10Q/JEENKv1TOlh6MuVVAzPa3o6TvH4zNebx\nQRbusrIFdU+J4TYVeUJKsuJ1Bi5EN7QnuEW4bD6gD1KvEklr8ZCMu1aCGDHBb9SI0O4fZRaT4x6+\nlV/rNUqrtNa+IkrWwGlw+CRLWr7yANGvJDdfqU8ziWfgUQTN4DGdR7Z97zk4Yn0LnEErQW2+Tzew\nhYFgqYl2mqAr1xX5Hco9UVpHQqhpmN6ZiJmbKHBAHINErk4u3smkwkJI+kYnck+UQsCFAgGkYomX\nsf0JWFVxMdBVWzFWXsoS1xcWVl2+WeyweX6y0b3YB4a+XoyWlH9DHRrUAROtUTM0Jquba3zAbs81\nSTcc7KFVoaAGj3YS909SJ7WkXKyySBj1V1FWRkeUXLTyz8hX83Cfg6WAkvko8glEHDDlE409MDk6\ngeDkUk9qYOVzXwxhPfCGtRvas1L1NfzByavSvalFCYuDdP5wsy7DrEFiuKQRmXNyrWEkT3jyZ+zT\ntsOUFx+bvOPFEyuGNaTJiH4JFrG6re+NkdnCb8wPVWK+ExjGlNSZH44QYhEdVFlE0Gu95nGZeOIq\nQT1xSFmrEqdXxSSZlHpIa5WTKGj7AIOLQYzQIE59hRSf45Cv306/ZfgaOUJsnuhVl060xMGL5XPg\nsTQVbd7ByofDMsm91aKAG+4o/xauOl9QGJKoFEeWdVVh73cC+pORDxAgVzUB6432UTFGEzRbDgK2\nOEyFicjwKWyHtmqZvOSW8hnks+VzDSNUXf/d5SVyaQdSlv1qY9x5Tz2oFVH/M2fpu6NdpY5Ly0x6\nvRaqTBVFKVq2BLQr4sB62rgQkGedgDGA3QIip3hn9W892fIwvnCWQYwXtq973R4UEnAm0JBmzCtr\neGZtf+TxRj+/i6L9iNAzYxplz0U+/aqCD1+E3bjh7Z/BZWtlpw9gGMPST9zivjWbF82Fds3Ucnil\nGbJ/71GawF1PhdC9IG8SIuvgoLq0Wo0TUuWj3ZtU9VetLVFqjWmqYWYQAWP6uD5KdOvzyhlpGqix\n58f/08EjYvx5DzEJse1/mzlNN+QrpokqJ52nEOYlKF7PyDQD+i7GETOQ3LPFjHfYcLpyIWvgvs0k\nICx2LCRSSpjlL67qQ0VIipBNDI1PFiiQqrCvN/Tzmrr8ye1JUql7t33xKF8AXDhMtO4Nss6+vPQ5\naBsR/c8xmh8uuBm62dvfOupik0c/Hr+vQIVIxVmIRv7AiPwqJfQe6w2Q4xv21FyGvqHWmAfDbdVk\n2SK35qNGTz4zXxkzNlUaLnT/CnDGN+w8vhxd8C9Oid8JeDzbxExWnpw4Uk0dkPh1+oDUDcolIL2M\nVBrFgu7dp7kay1sFhWXDBs71JIllJ5a5AK2pZcAtRpBtjM6nbDHyCnnqAlnzofJsNaAExeI2FHl/\ntQDxbkFN8b828UPCCam5+scaQ9n0gAg69kOOLOo5Pnd70NrPCG31H0Flv0HvV5YmcjrRbXF2Wyr3\nwY30GdSGuankMViS3MH8eUmGb3bJ4oGIoRdFyRjBYINgnzkTrT+koFgYEo1HfFoTaFcIDsim5cxT\ngRYGf5yWmCUJJvQ1eoma/bCBxYPdHu+S5Wz5T9tfgzaXSszf+SEgZ/nNGEqMI4CtxZsHqKQ99Wfw\nOajJtVmR0+OuDPVY7Mdlbf+PWAR7thRR0IBdGvg1hkriLV6jTa/aimkGXX38xCWNnJF7hCP8Vp9O\nHZeO8QNtNN89LiXYR4V3SMAdwzxFayxJRrDSZba9sHvRpG6ri8f0Dkmo9Pbukwj34xRiZjrOHlO8\nEnRVmmg/j29l4QYZnIHKlp0Vusdph9ZWXT8hgkrbW3Xsvvwi0WDxU1OBwYMxp234VYAKN41k8xQB\nVlLJbsaZrqsEM7RzB47+yq88ijBfdNwWokLP5AfQxORon1S4hN1XkzIvmULiSMIptgkm0lQt4M1I\nA/umX2iwn1PEqSR9w5o6gX/ZPhGQhNzFRHkyVzcBy/y2blD2Ho64N8juNgo+jEAWRU7As+9PbO6z\np2yOmtxovJmDxinwjKR31DUe14j2EEj9Fn1ktj6BPp6AX1VjMW8QdHKavoASrxdZPH6y7Gd2J0tp\neOCUePlCqeEDe5VtcMH1DTI3my+bO11a4g0+TgTbilAxekoqbmc2LEJX8KUtAlGdZIBsZBS6p4Qj\nHanLlQjWnVDrJ9UBwUBiCIHYn1ZRGzmyFCS9SQbnp17+1z7hviHqGrZCth2xS8FqeyHCHvRoc1tX\nz9NDtNFp95ut4mUPhAH5TXP1g5JdLa7mGDa8wxyg75s667QULjWNKuPLmDnzGacDyQ0EZOsnHRCH\nx8cc83fdVWlbTTGWpbkwXiRo0+VK9ycOJMGUP4E/H1klZEy7JY9emPvc/HJd3wvHTivaX9DaVhOd\n7qtMNBiHhcdWp4xT9UOwbWVlSW/cUYst9WBjgd941UFolnCGVy2m9k1lEIXf5Td/35ViJDSw5IYN\noaPkRB4dQge5ESbzCxoo6IgUZ3zcxfecHVDMdKvi6su1uOMI0vqLZtvXGv7JMx0oFl7vG8bViF5B\nc8G+Xub0nJkrQ9ThXFJTvhinia9vC/Efa3qi4OJUdp4h7cioztEuT7l9NKVRwWDmrrIcn8aUR9tO\nL6u/aae0eBmLy7G0dTSytiPPcQlAZQKo2x+W79ZapM+Xj8T/0tllQc0sUru096Qy1TapCFrV4TdZ\n4oay/gA51ZAUoePcF8TfxxfaFp5DemBR2XOtY+SEL5PM08gtDCm8kQx58VBWU6bFI7tBVvDBFyAz\naEyozPnkqQwf0KfPRQ8LjmPtK4jgc9FmKM+VFP94KdHI9DNWApsOQcs66tWXH37QGPjcwErjy77q\nKkkQcNMGM9Rv1zjvp0sfUerTzw0rsi5tK4/P79h9/OU0S1SP/MVb3Pc7w1PhPL1gGvJ9WU3/p2/d\nm8qNbDt5de8ocs+6UhBml41eIrGrpEEirXBIi/35fmU6eAUmmzW+xtri+zfPp1HtQzcoNFpy3wTV\nl46L4l42YZdsycyUzKW6ek19CBIOpmcGtDnB5dMBCT30k3z7JQR37YxNm7IxCGHLjmuoRBNNkJF4\nVgSB/PvrL68Ha+e3qZ1yHp45JG6pKJRR1uCvYunALJUJEv15Y558kPjRuYisIzdZlEymAMt+aHEb\nILxcS0rrRvoje8rV3sKxwbFnWc3OJjnC8m3xhVEjgyWnaU8Lt56e+I40XHFw4tLHdwjj5sQXoNFk\nT338wKkuguDQl1b8zf9O//PJq/fzPRhGaL5nWXnyBBCjJJFcs/cyrUle89TG4E2WPn7ijxzBwnpg\nxTjdXu2u8AYIIEjjslyYGqFVhnrfaPPBJ4gC8rmrJkMLwRwFeNvpJRw4AHXYJzhqLBHEztrP9izs\nb64fyH4x/zqIBKnSElwHvf9wUI3VXKb2miXM7qYT595+uQS1PV4iS8ZZ4wJF75NwInBmfZf68Yp0\nxFbsp1p11A3iM3/1Aa3AKpNdpA6+Bec91jEIL1BknpsimmeBSDTFJVxk76DTMMdeDHtuX6MU0xTR\njQahzZTGWwPKxeSC/N8Ua4Wfqzo1FPZv/gtmlrs9aGB3XQkj9WRCAXi8BEUy4ZR47nSSEwL2h5VL\nKe4YxsXKGL38EzTwzer1AvqzwTHJgV7egCOZm/1r0XN1//5lXHZLSJRCZfc0TAQ14VSNxb9bO2gS\nTOTuOj9OxhBm6/1C/9YA2JDVt6HNNn8aZk7ZFV+d9MSaxwCRfes9jUTzoUYqPVbeJgq3JPeVn475\nIg049Mz/fXTUvRph7ONmsJewO64MikeSVOq7avO2xbK48aoW5adh5x/9Burdkwa6I+1hXCNMh+JE\nvwj/k9aDttR4BIRkJzk4Kvp8QKan0E9rUOXP3srWJPzP1YkGYU4OTpMO6oDDVFMNKqzUDLE7S4gv\nqoyqa52CuNJBAfuSaPHRSUe7vTEygDxJBJC3//t8oZj2+kBwPKXG8H7U1pjU1+XQJYbgG10F/IE3\n7F6mxv1OCq5ukQQrJvzZBjZfLq2/6uP3fxjJg6E7k2WXsXTDh+pXTQ49Bvv6EJTnkquIlQ0BYW1x\n2m9FLjC19tJcHxDUDuEQsMFDdQlUPF/nk5slMtowCQWL16OZWtzSHcnydmG3HS3ellCcLBrDp42K\n+coUHDk9ofiYHOEPADF3HmRHdP54BVN3ipeJhk6z6vA2amjIY2K3Lph5gCVpsqWUTk8iQp1AkZpi\n7qTrnFCG82ClzPw/mTa790MzuWRlzl25cwkECcjiKaJtzwXKw7gzaYlm5W5uhjKd8k0NSDCogG5w\nlqXs1fsvL9xrkItW9W2Bj7BW0GbT+ryNByRK8Czg/d+FTr37tXHoQeMJo9wCf+Do7B0lk2gOL5gj\nbJi7NpFrPMRzD9fsmmJlKy44u6GIQSfkisOHMnRBMYKaohmYzxttGPkR/QRgQIQoncY7b5cmQtzf\nsiiOtmK9/tg9zoy6OnBV4kfvWr4gxcnC47+RlnUTWXVaT3gJFR0BLQHdViw4IYIP/M+ys0ee4XfK\n2ZLGqrkUpKMfg5ru7ZU2zZd1jatLAKnm/xwLtTFNLQtZYAc60rYODl3us3afH/gepNmUrw2c0txa\nK6MLI+FWPQgz1ujF9wTftceYUjZ/H2jMJDhInkOEuRzuxe4RkaW3pNaNgtYo9Xv0Y9zO8smbWeXt\nhVCB65Mb6F+7VPtReE4/y4cUnOAMknR2LH/CBq1/VZW6nM9QgZaZ8mY3O6/TJxVn7ZaPzDQMScy0\nK4RVdqNP+nx3WTGbQ30TDNmX0L2LqMa3mcyGvWx4GLgOVkYnQR7F9GklxaG2M/hlI6cVLFlXr6t3\nTWoTIZjRhAeB/5hx60XDOWtRMSTrn/PwcQ0nsnfWz1p74WlPo+Q3DT2ugnrWXsdHzcrtpXIuiIqV\ngRhkZRhTtHQRxppXzPRXqkLGnx+5YBKmf1vztAqPNsdtFxBO9li+/rrApzGgXNBeRoHGFbb3z14g\nlJaULpy8oeZtjmBjRrSEMTsIxwbWVsOjdSyf9Owgzc/NHNWpUi29TC77GjstpvTl//cgJ4ISlTRh\nqK40rBu5vyuKws2uJNdyGnUrISNoLgteQbOtySF+uGz+V8CwvV3VzfMxfKg+/M9vY3468Blj1GXz\nkfkXgsn2yx8JruvurhINdSM3YE2H7lNDYYYeaXPYRTHT7yosYI8e8Ixn/YQoLVyo9hRau6Uu6DE8\nB9k0ItrncvItOUDKsRtdIqu6S9LuJdsGxCZxk6xXQmpWbb3p0/nyt9gGC1nZzRr7me8bpr3zQv3+\n0qxAI8IaZZ60KEZ8GzKdUr23peTzfUsShRBrHVrqmnROXslv5aBPDSidHqqkpSfxF8i5LjQfhHMo\nF1cuTnPyH6VruHsThs0tbSQKYt1NFXqAkaBGZszX0y/7GvXXTRdoYTW558d/FuVrYuJ76lGqT4Yj\nofUHt/vc26o9bEaCRmNFrx4E8tj3d0H8mbC1hOnph1bM/BhwKiwmayG0K8wYfQtd6sWIwBc0pQZ0\nG/UI5i+UR41l5YAlfnxvvBdbcVim6RlB/aVvQolzDAafgvLlcIK0Op2RIQn55M4UGGiY7nlLZBi/\noBllUfQm2AoV9BDA0RElRnVtO+GDSJhxkmJynic6PpVcExvLoUG8q07amoZXKpZ9awtgbT/xD8KJ\nPeh+6BF3AlUNylCTSt1kKFTyHZkBpJSRMLLLJUyhNmvFETR1opcqveFVEsri5IIeTyidUaM0tvHU\nC79QT/2WcnYTqdbLgFRC3VVDn+POIgRNsqF6GAKoaEz4nz7hmVsPAeNZjWMVpDAsccN5PkCyKcVQ\nWRTLXKeENN1yoFODNDw+D2yp8MSysBY7Yjac46jeJbmiJucbcb0FluxojEIPdW+azUYe2rnGF5Ik\nieTmZKQg5Fj0UShDKWKIHlzv8VsBaJszhsq7ahgo3n+ZKCGV6DkWW54TnrjEVpt+DsHxAJuRz5u/\njULbJFzf/nb+1dQYMDuxsrJWKvwovtBpQW8cU3OduPBBtQAim3tB7dspeXqk/3oBHp6K0js6v9qP\nmOhynrGAY75sb2YTjL9zZuc2GchbJYpcr2KPhaggx7UQmF09C9C1I/5mr482PAIHTd22FYQ/z4cw\nNb1sZypiyulAjF72sSpY5MiafjaUYwDAAVv1EuifPRFEz3Rpp+tef+qIl7DWgz1YL7uN5K4t2Szp\n+dfzXaQKA2Sh5/EtEi3LqpsBrLlk/W8k57CTzF0TTXJyO3alTHbMm5bETPqklkbqsWEa6UA4IaAj\nXwSXMbo3oHVLpSdF39qmDEfIeIfGNmz3x28prEfwDAbSzbF9U9Khy7ZlFuQjFauTHgGVfnG8pJwc\nUwtHDDkJtrBpCr5s60TEs2qTQclkEMbqibP6oRbl8dGQxkM9AQcUkJnXwn0L6rXL2D6K/9SOuaHz\nypFg9k6dMXx0MLJupY4BT6dVHhNQHTxFtHGjwCH733JK/roq2sH38jzNMhPhjln7jQ+QDNEnCA/i\nSyxDMTqUtOVZzmG6HpyAD48BXwksIs0ymszXMoBxMPp9j2hYOzqmo7A/WXV79lN3lrSqZTOcFt0V\n4Q1oMirLSdZ9e4AYcmicQ4HFkMp7u8uHm7VZ70EBCBVpCHWM4TBBl3WCoQPx6vpP4LykjUmuu6tH\nmEXibgDEWutBG80BKvq4q4oOBghEN2WFwSmUieb0PPJWF4gjgvshoUjFIc1MFM4j0pMsVckVl19i\nvHQRlZ0nDa7UthmeQr5MZdMv4Y/qw6UMTtv7mCzwQF1kJ29v6ajCzYhIPPPtOrsNyFE3ePrx2FEW\nZQ/XStCaK6WB3wloo60HfR+na95Lc+LvjKhqZAj2QoJyQz7EUUW7Ms/t3Xdl3+riS2whVvS5iX38\nUu+/bXmgQlY3oMMGZw5Vn8lInq1e2nw5hdXNPHohgw5WpTfvJzrWtvL9NCBZnd4XueMkmZPTjKuk\nM6OXUgEwy2sifrc8CPwqI32FoUS+KPJDWPseQzxl2Kzf65TBpCW3UOtqfegNC46YFPogDJeAS3ea\nSG/pLqpgPrN4pSwHvFMQE+fAAodJ5gFkRXIAO0Po7wjANMerY7uKe3tfQxbTq6k7BtjwS7Bo6uLS\nX+XgnyXdhUf0VOa8SRRDc2VCS7VPfgoDiysVaLoR3k/36EhZXFGtQ8VbYKYfSoobBt4TnYic5T5F\n12EeUC0lb9Op9DrbS4iSCPl2WC3ZxMnA4ggmdbTugwERq1uOk+ORaXZfXa7vxY7xilzIFCesq0Z1\nUlHLGbs+UgOlzEKXEpdULxTNHmY/abO7ERScu+te84u0F68ghXzTGyOAdRjHsZfi/fh5IarCpBIy\n1sv6Ha8UbJBdJLPCCyMSLImh0gfyK1LOuInyx4V/yh93+hAj2p42GIAX10+vw28NXsrmCwABtOKp\ncy1hPM/wKZt/hrWR+nmjdZEjnwNUer+U3fqWOvel+kd0KnC+FwLx4p30rjOhQn5Tr10LMlM9Bamr\nQMs/MnTtMiKLJKl2o7qBKnmmv5xZcMDM/eZqfyhdGvOfTmeFCtd5wpYKXpc4pXRRXAFAcLAdVjRO\nB+CrpKJgzS1ceynGT9ga6n/pVramSROvQMpV9LTx9I7sT7lG1QMVib+lis1a5HUmZdGf8fItouI9\n+h8hYe9uxDGo5m0PRCZWjMPMCe5YwRvgEP632b3+8VUEznsHEsTcxUt2C0vEr6gFAT8+vhhA6v0D\ns7I88UwzVXzd0uw0Wxo2+A98qRQwQIMrSzABFM90U/lPFdn0umUGh8f8lwbAgQ8ne8izMWyPvP7p\noHx+Cf+JrhOvBhlMut63E6QhEaxvDXUE3WGwMyLaPPro8HnfCQvZV5f9RgkrrNbSV5zxQjONavwv\nbp2MKEnTStKwEnz2c1h1tae1bynesB2l8QXUKJe2ezmggsj0D4IPAeTbaKf5Dfqwt7wFd/Pqa0UC\ntD5QAg8qzpLx1zasA5UG65ZDVGCQxrq2B6D217Lm6gDtJq6+adUJoFW131xyK6qFCgJuLQRokuru\ntEw1srY16ymSIthSyFcOWkBT5WTGGzuuLaAyf5wTRG6OKYNMnj1XgU3AtrTpQxUWQsdooSiRoLhk\nEhG9dkH2EsAEF13nb40XC0FJN82fDT6LhNR1Ip+zEPD+PyemeJTkTuFy7WTrgsljgEyd1+V/YVi1\nX+N6l1r/lovQjEkBjezNIl5VjV7rAWEIL4FIRnFDKWbLAbfedTmz9bRKjj4YngwOTiKOsBuJMwBj\nE2+j56GPWPgD1yuP/HBbAfEADAu8xftEZvS4bUWrS3lWPCCTB80dG1E88uA7+PibomC9Heua/qiX\nd8w2N3lZz4lNDqcKaaXKlY0zxCbx0KpypvOpsek6qkYH3IGB0zhCRL4SfVR59PrDeQTiig1z2iX8\n1u7JLX4z0BE/pcwJLOrA6uHPTOKzCSHYTkXf1vxafnhgWXE0xVSpOYIt1P5zAzV7Ge9k5GqMGId4\nVnBb840BnFIzFaJRdq+fhXnGgkZHyZHBCb2RHcksavxwlalf7eRccMSNsnce3iSPek0AAl1F08xW\nTBDaIp3HNLK6zaRj/GekFe3Q/STJJBcBLi5d0WXM6GXJbIwLCCNOUzieeUqRDt9Gaup+zh0/pdio\n6WxPY81nGCl0TmM6d2LoHMDephrQ455sAwjSoHaeoBH0ac+8Y5byZWpDluJV8KGYoV48EN9nsh10\nD9QCltsN5r2aEfMkqvx2lKf+F7OYDqeIILgXzm5AU7GuTD+ZjmZZG18UiJRT/b1TV/HaHnZbqpzZ\nopn8rRMc159r9GX3jRg/RZW69XMADrr63+M5VX1cOg6wJ/FGuKSUIombVsQRoQ9K4kfsppGIlRV+\nIjlsjgc2SeIQESYKik5VhGsIMYAUMwwTzWj8RKR8lvbTnD5+tw2J+JkPIFxvMWX7QWuvSw/5tY/O\nFZf1XmottS+nKB+JWOzRFXr1DgADy7peJsDQHcOp6ovWjXW5lJ2S5NsTEEJat2fh/Dp5lWzQp+ZC\nyorQGmvEigCUTJYWItD3sDjEQcfd56bsMsAoWp0PlVDHYtIm+97CdnDeCduPnOZVn9YkYWJNEYBF\nIMEpWWJ6+eySPuBmBe1MC+LAuquBNGxwBOPo16OIVmhDYWwkqqp+3OUQWki7Tmy/dFLc1KYMR9jc\n3EDieq34kKHw4yxQNTdBsxu9xsZi/Z1pVneo+YzJ+643PS5aOLd+dD5PPm/acHkAeee/c0/WKOZi\njbns7nXJRvh5P9oL8L/96ggYvN8p+EB6IOoV0Ktu4ByTNgqz7iiXzV0+KQ1R8sEKfbVhnYa30s0O\nJi+LOL6eedfArpeSKYXhpH98xor7Oe1mvhZRnVYCNSV4XYAULrfdTFQD9btIHy/eZP949Z3d8LxT\n4yEviaVypes+vP4njH4ThOcJUio1kO1uGRkrInD2npt2a7jTwDmZ3zTxfDFackgdaL1oQ7EYxuZK\nJUOufJiPF3yEIWxw6c1lGQvnKg1i/gX3KkHpbN6yo+8QCpVCqN/rFpeaI+uHhOsGXf7tL+Pg2u66\nzi8QOkJsQMBBONeIkrjP+8DbMzrfNjtlXDbYLN2Ua/biElx3jkaQtW1kZAETw/u8YHBaUc6dqC7+\nSqm2RQQHNjRxZyZ1/Qcwv3x9exQKTno/xH/s6cG0DHoWTu/V7d8tNIc+xNZ8BZlWkFbY9w58o3pD\n9urZ00JWmtKwoEIyevjLoPg8zs2braN8K7vTVSnE9jRrOd7/EKcUZ1k3vaYOKC03dM5ta+B2y+dQ\nNrkTspEIDb0fcKK+ZR9fs3eydgNJLHWOnmXtbJIM0emNabywr8nC8LSkJRHThxNxhhPJKl2JjY1M\nuR7MMV2N3Cm8fU2WBHn90OvT+TU5kUov3FiSnEOKxKzUZ1/xKjOhyQBlZ54zgQ1jgRW4cMPW7VOr\n/fQ0cVkITHQo9o+rmZOFD1M+qj/nkjQNAQINW10AQg8P96VbUQ+/oIOsaXJb/ZCgU8n36RzSxaHc\nz0tNWfHjkaykvSsdOBO/dwwq5zBWnObDWD/H4Wh7lfDyE0U9WaNLPuBU0F/VJSuMEWOHGeAz6AvX\nGHth5uBMZqhnXW9bbCm2idLAu3UW4CY8c7OpN192zf7VhLVwkuQpLMaOMAHX0g9aXPY2mB4h00i1\nWC4KLF9Eu9HbLhGukXyAlB4nQQ/emv5qNqrWPfDq7+nf4hw5MIYa/Ji6ksPLWtFuREgXi75iiOR4\nTjAsZ5Sv75gFFyTDQ+gkLhuNsiWp4/JrqJFucuwCRabnvvZ33BTQh75kxy3DKVogaVySrp2qzUc5\nJBK0lU7ZWSwvHi21pXiyf2duVqsvgM8v1Nnerl5bBijThDB5ybxEjnKj2A666kwj6XR+nqtNTY+K\nOyf84lDX3SqqbzenFqW2+f5dz1PC53WypTtwWHjFXOkGN6CIXL3+0NenWt3q4tWGKCV5MmD5N0gU\nlyVpBdklcVCpmqbOZJY+WktNKBay7oa2sBaHbapfFP6xT1otHviQvQ5EXK7hJl+2PJIi01ciKji5\ngNKXnYsAlnFgSknU9SGSbIioMvfQNk8xYRl6D4ODMQ5Cfk9Ihcgk9CpZKK5WW3Ky+/PJ2h714kFo\nm6MEnewCArwWfvkw8/cIvEteMS/7C0VHy6SaOlB6yU1vupt+rggWWMOI+8Buih8DElF1ZgNO5u+a\nxtUUeMSSeFIVczl0lCImFp66Lj+6k9Ej/WO5ZISjqa2lS7Mdv1aM3F3QH+XXvQ4w1IVuiYhfGdwy\n+5+j6/VYQXsAbSTMYzRCoh+S/+aXliVdBh23IRiQ/paB0C/VW+mfzMqQicPtMHdr5qYFZAy+3+Ix\nWQkWrhDDd/vysNCv6JD0201Jm8JjPlqa8lk+gEPmYfVGA1csIG0mN6lVZVrvUPQsVBMErT+xySOw\ndhfytsDxNI4a4okeEMVw/XCEvBh2F9cglPEz0HC7zD4gZXzq64WhfP0abCETs+KnXhhxSj9SFAAR\nSeyglxrZZTY9L9yqAsnPcUznxQOTAQgIk105NmXkoZZSIPgZeWGwckqh4O8rWWi9N4kdo7WnCXQy\nVkZlttyOSNCx8JmDiMCmdb6hHyNwUd3yqMgsbiFkFipKvgFuhfaZJwlGufK9cJqUkLjh4nvfwz2B\n2rPdTMN5guIp7rEcip1nRDVMbHd1qygS3J3zH9oeM0rreL9s5WtxvqLJ2RJ4H8Pf2VxsD2DWeW+K\nR+PV+ecL6LPa2h3dzepl1ONGMcwIurQOz+QBNoHE1fGDE8j+s0RKFtKoRLvjU/JtjWHM8+y879no\nR+4cd2pvmppWgcwb+1JZOkJ8hsNAaHYo77r8IEeHButc6QKpOhOM9D3WmaxlbkbUsg8Nq9aRodDQ\nhdoQ1zdx8DiABcMe3FzBxDmqREe3uRztXxD+jZJe32BUmYRqROtAVlk0ZZnKzkM15X02Ik9VPaeQ\nGIdBK0bBxzz44ZZ1kb4A6gBwxgYNXIgKfda5S7xntQSl0L0NF2/6p7pqKpfqEk5ZtYfISgyly/rC\nAdiIwk2C2rq75Lqlymd4/rq0mUpkLzu5GvIOz+SeUfmFi1U8sYURwZnrCimatK3+ubr2u/aJSQoK\n2TZEuBSeVjnBaR21KQJco6Sf92W3OYLI61HdJB//7gUYqeBphehv4pUyUs4xa9HMAOogU2nW027D\nzpcDbIxiYVUiy639kXzNj2zK5k/x3uGaRTKvzEvjRBPFVKY2v6cPBhOPTvyunQyGkv24D29f6zR+\nqV7/h2rwQ3ac2tN+LMZ487I6t3KH7rzVFtPd7ExqU18ip0HaDvJDAjDdDn/naHyHsWKgSUU2UE2O\nFWeKlYbRbIhBH2Ndn0Kjecwp/xshMc0kHCdMtojQdMLEG0i8vI6qEa+oZvF2SfLoP3RcEpHFR58z\nwE3EV4cw/OxyCRm8QKqYL9vJdypAcu1/tilU9x4vjIPXerxbow6rTa3PUqM0zBTfP0TmKzbX2dha\nOVIujVxU+bDmZtStk1FhrVwAZaqTYMqZXYX8dHspKheX4Rcdf5C+Pt/jnoOedBDOX1dda3+cbxeb\nKirvfJi2IeFjFtO/aAQsBHksBooLe0tDSw8ZCz2vNObOsEaEvU8R2kZh18mNzbct2Jk3CrrfPe3B\ntTKC3i7Ydli+iTxi8DtL+FsuMrL7YvyDY4F35BHeqhjFOPk+kVEoj2F8KByIy5wee5jn7J1GTc3U\n3I0xYaLwfY1PPUyzfL0hA3G4uM8MWYK5fAEp7Yn+9LHI8KqpriSBAyjCmWC03oDNxtyUORZPKvZP\nfOMpiYkg8W6N/jYIwE7uh4p6v1d1d3dmBZqKhXYktnJgeOR5TxFffmZ6RiUoVdPWVHqq8vn623Iw\n59jn66PmmjrmU1/sycc/9O14MEIUbVhor1WkJqF/RJ8/fWY8ZNo5weHLnsqVDJBv705MTW445Y5P\nIxaonztPf7Aq4w4DYlsbKY+7abzvw22fNdBQIzFh24OEVJzB5akHSvDVkRods8mnBHGwud+RdLg6\n9PacIEabXRameLpfYTTJxf7pET0BWGsZ9ML7LbyyIyGk6owxAiETIEyEm9U0pWimVAGH9TZbqFlP\ncctARHV4TBZWjpJuppl5HQrXLndfIj7viAK1F2/65dioBMu0Z84TMGH4iHjeUVo2+n/cX7JcTxkJ\nyrxD6Xm92flMsUrmP+7Ehpiunm/CgkkztJq4vbEgdlEqBSI35OzhmmKAfSuh1PY61yTYUNuNobGI\nEmgIgDP3YNdBbZqyR30MkQ5eUaVi29xs8u+OSGTPyTqvcEhLMwP0jMi4I4865TI94A8zhqc+GTLl\nQYFArUk/2xLk4xHCrks7VnDesBB7YJZW7vqSBYAWbj87iy/7opOI2buHzsmuLbTBXnPH/+PpOAOo\n8xxPs+U0MtWj5K4j3HS5m+Q5lZdTw5YBA0IK4C1XpUABn29aBNNtpZPV/1ZQhiiXfik4vAa5vwnh\n++ijaZC9Mi6hOdgjqjbBGI7jl2N6IMs6EBW7oDip7dEEkLRudrrSzoznToKoLiK085W8Mp91H7/4\nT6zlgz5CqrtnVByBOOJqg/g2MTeOz+zUE8XnZ+IyMGH/wJ1fvAXxEqbMLAA93oSFGviLmt+vU491\n0HeCptkzEE9z/LWkEP4ZR/Uj3YnALOnlNUEF0UFlh+QznwILdDUbgIhv28efoMHNYWe1QgH3FGfO\nWDli6BWZtw4ZHs2iBXkTix4swXAlZBPotB3MW3oafcvI76NWlzn6utFlcxFJSfkpuc+yq26ZgnpZ\nVNp+LYhaIJWCJ6r8Gs05yZtUMMQtqfLOerC3R5TyhfFMlJc2NqbAYq1AY1auJ0n0896340sQzA+F\nS/jbEn5DFV3ZimXMiKP3Z/87dYFRycr2LqToKo8Po7DJWVFdwy5nQZa//1EsSZJpKQNgXGtaOyb9\nPtg3oxsNgYtbcYmaY8W/sX1Lb55RhQX5tO46id7qakOKi6kypfztCxOpQi1Iz6KWTSEg387NNC03\nWnt6FQHPLA/elewkQCwNH8e51MN7Gz22tJKAlk/zXf9HvQL6QiHIZsegR82KaWG0Kez09v5seAuA\nA6YRCRjAS20AfBIji2r48iJaYesJ2yUXq3nnd/5ROAv+z9vn6aIlaH6TEAJmpb9yPbPU941mc7CY\nAVGP7zbhaMPB73+e7fMg8e/vsWYfp34W5x7nxJb+HKqfvlJyY584NYJUn0NlvKoeph16oTMgbBgL\nfnai2s7X03goJ88mJDCXIQmCWpW2SRA4e5tVCLNdnU1dfxNAPQ11C++gbe/IXxx50nOmQmof3EH1\nfIz7YHgRMCXv9KNhEJC/7o2mJIvqjO3TXRu3ZjhBvwFe0+P4vI3npgELQ6FjEl5xZCuft/XG9LpP\nmaKbJVDs9+mB4dFyRv/B+whQ90mCih/xnpax2q+lyNFVi7MQUbUtuTBM9la/gXCxZQhcTPhamd0M\nujbNYJF8L5IO6WsD+qmKTqszWemgatik80z2gv1ntE7LqWNWJNG9jPYemZLjAVoTwT7Ff2ZQymaI\nbco3xrlXTyhrQ0e59I6B4FRvfoT5BL+rywTViEAxaa+NmyjyjXoURzRJnwGrZ3nk4mtoXYiOwP8w\n4jxV3heAErO72FgEnsrqBFZBvB6ZB9iw0m1zQegMpoUMwfu8N4T5UnLh/7+KpQDoAUQnIihk3sEh\nGgvjQo4LNR0u8h2EIZu9Ru7q2R24q878mE6+8Szhc41WGIICuxK+VNgTsAzNya+mY+F2Ci8Bj7VA\n6J/Xhrvz60jtZtUPtp6OUCtA93yciJYsn02Ss4ixM5Aoulioydos/gUEKYHMl3kvFtpuUec3fd0r\nLKsG97/iCX+ntv2RO2ZpeVzECZ9TbN5ktOMIF0br6gD2t6u8wXc4+tuIEg4BseYC/7TkHwKsW1Tc\nL8XjEV5OJ+YrREkr6r7zHjkfDTdFlSBohsATkDiDopaMoPA1Fo6Fu0zEBP8Ln27/SnOLO+E9HOfn\niJBuumdhhtEx/5aWDY2ArJeDpFacJ/ku3r7NXkH+9b/yEVClNyOcgvwwEBa7sCHoBAN3D2OvHUoI\nw9v94BigxB6QO2uzjNDh9UWC55ZUlkljvK1F2XaOKnXSkLLzDCFcxZ6MOk9xkXaXf9TCne4ddZDR\nLiqqHOAYvwBliSRvEF2GX287gDq88AIGDYUlVgJ//vH6Ycn7Boko54JB1YPvbNsQYD4NXjVm4bRj\n55hHjDfcSjKX4bz89SfPfBLuNAhRnT1crVz6G0VHL4MDLqnj0RkpVQGhvSg+6Abb0SIYMAFUuw4s\nL460fpt7WDGvKbpTud0GYKFCNnwmq6TfzwoyPWfHZjcweDEmStc69tEbvXE0Gk61NG7AFv3roohN\n1uiZ3nlq6vWjre37Ts8NLmiDypmTeQVb1UvNZ/OHobL/8X4YGRfX2QaJwXWHm/6TvovdkgVtjUG3\noA/hkIzPLcI5F2TfMpZjDWlGgM4lZHd1qm4cGaUZuCMAMgO27vHTIDHYB3oY7DqKeZ/e6HYx4gnh\ng0boxnquBl0mbgm81GN36k1c3qo+EvUqmJzwJRMA267ms4Gy/aAE183vSJ3VWzhgcohoxSfE4Rb0\nmiJnHwws7Bob67840QAC99QWL4KWExF5tVWI3ur7elOqefE9SMJBaucsul6BluMqxSaWpAtbdrhP\nkKQN9KlQYK0srOO85kKvFMb9cYo0SmRoxtefrPighkA9S2dXSN/k64UUMT5ZR2dPRCx0g2T25enp\nyFZl7ob2OktaZWFmkV0zHp5RTemdgP4ILAlKs3EzaHaKilRUCqTFPci1n0oQ+QtBxT3P6QRxU5qe\nLwBufJT4FXh3iZMCC1ZmqkxZMonK6pn9jZhTf42iiE7aqX0Hq9A3/KyneFyRExGM96iRjg1ei8Ps\npwLrjQ46LrLyiWGrSJEi8U/zNJ2rJQWcfZoJyUtOPxTK8/wyPMo6x892bNzmwqj/S96cmACACfoE\n7vUcGohLQkuOMUxVygNomwdD1r1s1foCZrTXkDpOWq7DQmSgmdqBan70LHKfTByp4FnYQofPPIPH\nCL6qSsmI2APhOgx27ARyMKXtwWvj0YOuXAICFSiNE+30mkCC9SMFnHSTkeh++5Te4h0f78zpbrEi\ng7l/kVz/GNn6HePRDrx+PL5l4FrpdHzIbpJkAuqdR7KACQqRl8wOl2gLVf1kms90z32qxqx86x+J\njphbhGRRg1XQHNtHAalCTFLEunaql4tpwD1WUiw8/GY1yiTde3barDeWBmhGBDLtIXaKLDFQtWjX\nB4EYCqJYQXUMvXWWaweXNF4feILAAGzsM1HUH7W0YZlGbCHhjSHIbUCJZ6UjFAKewo7RzJhtxz5+\ny30MDIP6+SNBOsuBI4fIM3rbs1kEYUsAJlpJ6UZuDXe/VJfefsGky4yTHVq/x5GXLwzEKitbWL0N\nZfqBiXU8y3lz5UFs3ipf8pk2AgalhtRJsdJUrCPGf36Rq3AX2vAr0AM8wkuqxbLO3ZjC7a2sKnD3\nXze/7phRg2WfPcrOWEBldAGH5565KNpTv7m29QNKzE6I9+Hf8QVsmAOeQHcH5vHju36L37c7dkGm\nMLllnUlrePZQtFk+8u5JNAwROmCqsROpP4nCHpm6LtyAOqJ51RqE+oAY6DIJdr2axpr0TJcoE+QG\nVmo4AK50sUH+ZIUgRXSF35H7PijJtQv4RJIOJbOdF+PNB3a7e22fJK58RvzWkPYnpMnQuTmhmLzY\nVsCTuaxW1Ylr5EfPuqpci2IVWST1Xj+vCq2qN4GvCeplITNKah7tkqeDBu2ftns5nJdNIYys6oUM\niEOoTuqa6DOnC+R0DFE+Cc7QZG4bO5vFsz3erV0vooVz2JiIUlCFNAMBXPEUlD8SiLVIBWLZCr+8\nuriE+Y2sjNBBx8Hxft2GwO4yI3QbkgpqYWsb018whqToVC0Rz7EICV9Drs7rm3/ZtXvwDSZUnGV0\nYooL1XkD927hMKg9v/2FyDy/yX1VsxT371/zwcqbFWN6TS7l0UIvdnOujBl269Pp/E7v0C4CBwrD\nYOYHcrwsLhMKKlzMJiKlI0ELr6bA2pxhTfmikm40nwNNnZEmq7t8OHWdvBTwBg8pZO9bHzkkYPBl\n3gLNGS66sOw7DMvfP+tJxzFwl5KbBa2F4xQ9z7SVFBRUplhAGeW+2VjV+E3kOwep7IGA43xxGsO7\n/J0waD23gug+Xp4Ld8uINDiqe4ZpLohuaREaqq0CV52yeUtyAneFWtl/bCBD673V2FaDbXTXNcvt\nhOztg0XN9dEJNjC3QJJpJY9/35Osm1v6K8fJ0U2l8Tb+xmzyzUApJp5LzSqyge5fZDABxHJU1Ma/\nWVjO0YJxa2nVDVQX69FPxG67mRZkrHFIZtY4zccnmhkZMCt2rmAMv2JI4C8qzW0QgCn9xfeWPkHT\na55jZLLCxQOVWTrHWN1KYtT8BRvxU9XxPt0Wlmp8SYvR2oBZfc+ltu8EP72aSCqoYAF2DPIKrdyS\n3T92KqSMZ9wq/uVb/hSD7jJb8/MDjm6LAURkYv6mqaBH1fenzL54/eks6HZ4IDudGO5rElx/IK9y\n76CZnM0nTklCkvu7+Olri/+7ueRhQxj0KAkyNY640zPZHp3tR/AmTtdDTLuOAhcbzsqEw3+vR4tB\nb3cm3RSNTO0LtEBZMjt5LAisya6etNCjIgFZ/6maPAHzNXfNwSmzL27hsXArNy17iqqo9DkCeKcF\nR4pBoTXrURzvQZuS+w1Wzu3O22AtZ282KeHroTRXIxXnM4FLlevetX1AfGNB8oPeNzDqeN+deW8c\n7lYEijdsi4wIKdumx1QXE7ikDwIx1OpDCSxfY4zNLR1FEdIMNoDrmh7mbAgd7+i8TXXiRAm8YLBl\n5kx6ShseAFFgi95/da5c6UuHRI1FkFFvtGi/rtBg6dnUoMZmLY0U/J+0pfCFJSnk6cOZUZkxDh+t\nl0zst/p53GvEtlwTOXdl5swPKUd5xKkrxVD7xhdyV/q2P11iIh1agJqQI7ollht9fORWz9pBLhKM\nowTu9O+54WdDY9KM8G3SSOanSGI6qVzeRbHFOhyeniiYkfYmhkAMOREwE7xvdobKKWWaP3h+iy9W\nX7LHCPzQy1pR3tRDrTsaSG64G40/vx59/vxsYeXR9Vw9/s82dW8Z/ncYREAt7NcgbJCvX68p1AXx\n/lkXpY62hGWfwivaUujNhhSYpsWLzOV61fXgOmGB++A5PjsI5BwheH+bn8yf9bCKs60R9v9ZeZST\nhKuudg8euiq8vvgbtCLF10/ZRYLdSagJ7Ikadu7NNRS06XLtCdZINHEWflb8kP/iJNhwXLNf+68j\nTNYq7SQRlOp6QGgRsnKWcthQbns18tQ6wVsFDh/tcXVHz9m1yI11j34Vh4Wzi7ycZzRdjCofcHkh\nfLI8TyStqgurO+/Q6rtVXClgzdcr5ktZIdVm9RxUqQHou6BPPbYjAIQjoc7/OaRwAbdfltDs88bJ\n+FyrKGbeHi24Npd918Rt9baIfl0N0Yka+xtXXb8aAtPbHaRrpkO+Sa5zyAEd+Bk5KKy5iiLvYXKd\nf8PWCJdgQ+I1kab3a0OyGXg4nykSfpJFVJmU84S5qFKIt5HYw6vstPAjIpmuOq2uRP/IMFRR+uCj\nJOUaUcyMF2ofXPo4uJPDwCIsR0/yZYdxuT34TsjhCUhG6/0Ie13BhadwgJ/KSBza/wyXvO06Pv3n\n+of8VfeyHvRBFyOt0UhkErj1wW4VkGClY3iFzLnm4z+O1dWldGS6T+4uUKuYu49OfgLY/BNGi3cz\nJhp7PlaWcf9A0dnI83WHVRBesuKf7sQEGqyu0e8EhAyK3cYuIuKCuRjX2MxOe5MJcEupPBwpMmB2\n4rLARVwzAnmZ0yWXtfDafNPJYuBkJL78DucWSXcbT+OxwvyVN407cLYser8SxGT37zOtVRmNMoaT\n4WoBINNePTnAgxNiEWf8595SVYlFMLCel37X62Yr+ytj4pTgaSwYTsi/ziL0QWTqRlrGlXW81ImT\nDfqvM607lQozEoPEEts+0lgzRrkFesCxWObIB1EtLdnZT+Tg5fTdLd/4B6yN0SzR11jP5XvoMz4o\nU99OsArFDFMgxpf/RVtaHw8d0FYrhkYCFi7E3RXtRfhK2csVCeaDPUZbJ4gZX/dLT3XUWxPGU87+\nIuRGVueHC3Tj/dDYwwZ4Urk0L/8p5iDGFwOq64rz5xp5nuUD44Uku4HEB8NpkXduYZFoitdwRvnX\nqrOVRJ6MJ7V3iue6xZ16Vitw1VaMuHBLiAg3lAWxM7lejlc7skeLwSRidzPG9pCe7l74isHCZWqj\nYvXdIhWvw1gM5xCzGASWvV/nXdyhq+n2XveSDtoxydt6IKZs0a2CE++xVPqd5BfyR+VJC0uZc0QQ\nI7/TbeTL5FUr2pBb5yMbDZMCpTZabf6zeI9RFMmYItlUlxQL1Cm6t/OxiyM/D0R4uZWMVuKxoRtM\nJq6mrtxUb9+hlSY6COts7MBshM/BwLLd2yG9qi5ryEodZC/xMCy4htKvnWmb+GP0VbmMv+KgzH4y\n63lDAHFAEWKQuHiviRuMPooW9Z9AdvO5bnRorkKFYMcBI6WOaBUKv2oFHeLsaCQ69D0QbdXJiyMQ\nDFp72D5vj2WnDC+xndi+TaciZDBmbVkZqY6X7j/U3z8pBbx1uGu2iyBlrjdTcDm7InO2ZbDa0E4O\nw+SHZtUIbc6Hi+b74qE1uaGRl8Zlhrp1uAWkxROKhTbyFdTPIyz+YaWhpiU5HNjt/bk6H/61s6K9\nzCE8l4vudGC1QWacNvnZmODX4slPlEWQjpEPyE6tJOeNad3BUgnKD1sAK+OiGeVM6sikQgGSjU18\nQnnrBflRNvV6CX6gHrN8nCH1slRcguWJIjZGHSN3dPsWS0K85nSk8zhWeYX3qkKUTx69GGluVZ3D\n/dAfdiXR8fW9gfR7bVhCnrTVEVddlWA2aLFo45nEwPORc60DzMefkOtKC4lUzLPs3O/5hdOpLOMk\nn7Vl/wOzCg8sWUAqed/cALEYmwLTpqRt91POQRYJNVmLOefwB+GBR/Zy0pE0P9Kg1PKdOd81gAcE\nJ4SatPDH8+j0uvArxxzQAYLMBfzhh9p76FhGJawP/1rJ5McAqkRrH+n6GpLAydat6+Lpa79xvfio\nRFiVH9Rs/nuC6G0C5itARruFBfbKMph5Ns8EjiABUeIYJjDhiAI/ILZd3w+Gtw1Bin1jZruQa+io\nLSjVptv29ZhmL/r7DXBXcJ0bOxkDIwWAyoaKEaq4SkbhQ32tSx7zE37xLv5QYrzjRVMjLRR4++yR\nWDwZb7NKbxY9eslQaE16NYoVsOrM0L5tTOqp68DfP5Qju+sGWtDnbw5YrUsLioL29Xsih5befeYl\nv3w1KaJffYNTUca53OLE3W0nrpiEboJCws+6URgXvUy2cmaUizMpyRwCQx8YOrdfp2dMEBpZa7P4\njyNmCIrXspqIpWqPGsrtBTJt/FlujzSfDgZJpqoodfrBzaIJZCeOS0HDSHn5CSdFXiYvUdJF+gG0\n8Jh98mT9BlSh7sBiPuvom3ebo8nL6Ksiji33nAXEVPTDuHE6KsQnNb9pnIggjdK2FjjeQXcT3nQH\nzHIVXSNd8vfrZkQtPrpS58uw94tTAHj5QvWTw5rotBsiiS4eZux9GyEelPq9tqqcyO2JYy2KZF3p\n3B00yNIhyVcRIgJBn+6LNESvFYjm+io57NTc3TybJKyOxEYe5mJTXO44em7a1uvjo/w2cdOlsjhp\n1rY4uWjEIzH0Y32LsK2Fc3Zc3wHRsKAwbJksJbX/mfovZCJq12f5w3fcjno6dZOT2f7pFmfcDebc\nr5S5J7Bibx7PEP1R6bZDzj/qAfdB9P/uh//spcLMp/eRMr0Vy5ONAWaMvbtqeqIQ2L7aAZE0IzbE\nu8TiMBCTnvBqD4Vam7dpcc9fhlM6OjCrasFSs3Lx7Kq5AmcXRbIgNZwXesE3m/Xl4G2U2pk6xfAu\nqnGz6alVb2e5wa1ip7syTh2MFBkRFHbfD1zZiAl5QJJSoUM5gVdzt1iJCRkMaYTYjYmpgEAuU6zU\n6Ec59oHnG0sYBYhS/RP5oKY/STKKRin9JMy3iDfZJtq6SpOklwKNPX/1BGZu8AqkpDhxFI7K+vkU\n2OYFV2Bnc4XJKEiPXyZA9HEmNTEz5nzZ6OAuBzBSoZV5Wde8/7AmD7NTORNeEOxCUTTv898ZucKP\n+JCfMStxlkdHZ9bKnymI06J3iyTC0SRnXGfUxw+1jhgRlo4WK+Qy2ggcJlOfi1+/1SHFqf8zoqQC\nQyOEGcR5yIkHRk11VYVfYOf9WtiKjibUa6xNcW6yjfEsSkEDt6ScrD2RFt9wTMETXeEEXjZqfBzE\naW04KeoWAt9X5xdJJT1EDPmeTEsJCBRsODlli4DvCS7v5AIDZjCU/2WOSAolZNEWOsmcc/IVciQc\nHv4KbMV83jVUDd35WvYq6wi9oN8HPRwHyZ3X5wJWzmDPmjvclE5MsklUzLdnLLE8tIzzD6rOU5hd\nha09rPId1/rOH7XEdeX7pB3KSxcJN3TJj0JKl55CDnUnC7Ilyeeo4QVFYIKLtROvuSF0lPFbBc6t\noeyGcbZmMCXakul1JTdRND9ropFD01WTMYNJdlHY4IQEA1uHFroJ39ltO7IWIxJGwZa4mSWkqzLc\nhQmszVSwuy5G6enVk/1WH4N9HHk02P7KwgfJyJq5svPRLEPXXQ0S3GCQsgu1mGpTf+i5oT1OI/HY\nOu4pL+Z0r+d6hEGFDmV93iHiHB+HE44isgVnL621DNByHBMuHCWzP5qn04s+1QXNF8/Mg+vwj4Rk\nU7EWXqtUqOoO5uKZTYKz/CK9Nhi7BA9IcZPyMqok5kadC1Uh0nKs+SlNdX/jByF0OGXIolTwRusU\n2Xo18M2ZDlpjlhu88oeW6yjGD82h8RhoOm1SN6Y8GVOyB0mWn+/4n34cUXFtgAd8dKfSZCckgPBf\nWyk/2TqWhztDFdHYvWZruhcK786r44GBisXgRjlIEpXIF2mMqaUoe4eKw8N14vMFr2r7eDUIunDp\nsUZxpZUmBFybt8qNheXKrYs/9m61snQUF3J3s8t04JEVlhBxa3hDtUO2FEHTgFU9GMVMX7MdgSdd\nHjQt03y+7SmpPEY9pbI0KmbO5Yhkj6YAsD/XXTFiHP4RyTpb1sLstBk7s/448wW/DWnYDG7QkIpX\nABR8qRWQ+T/RRhdW0KRtrYWiCuRPITAA/mLfQU3jAP/qePHIAQX2aY10gu7x6Lwqf/9ZvaBLud8G\n6qLgIWwL+nI7514iINcYoOk47lE6ONepDvyDCv/9vDfULtXyaYsUFimK8/bjhqz3K40PfYmRxFDf\nzqsuS6976I/GvLhcyIH7j2bm700RDaotnKa7+gFXbSD0j3SWGSDpnjTjDK7KU10aZgZ18RKxx6h1\nOrAxTCyHY3mxH6SK5NI8FEXSTyktkWMdt809H55YLUbcrhqPiDnhmc4f79UOUuj89Y7KES4zrlJC\nDZfjrbVUJsn9OgkJsvKmQGb7yWr8dN0Jf36KWZsyL8+Jr5biM3+rLNAkdkokM08ot+m90pAs9ajo\n2zM5R/zxkxgnskpm/XP0KPv3uHCKU8dHpK7yiag3n+JwgBLh4MVzda83lSt4nlinuTobrvEHSUOG\n1eoZ4eP/mCYncQpVVkm8VDraQ9QK6oWGikUabAeduj+5EqSfXhKx7ekOUXBPhme4k5u2P2/nvRpU\ngs6ttg7AOabL8kypxzWS9HgxVZT5SE6dVhdAswoKEwBASqQxcttf3yS5MqYS54sLqlNMzg7IX2GG\n6noUiREQhkWj8N9Xb4tZf8r6lvd2ki1XJdktZtdFF8UIb8AFJMlCOjEgM1PBfiCVgoyUPCC/gHKL\nYEw9mdqjxI7rAb++8rtrF2u/kAZlhFTsqYa2UmhZfTlWsBcLcb6ZUYgja+Z/Jarbng4Lv+7S0zY1\nfosN5MIowIgNj2ncmGsl4ZybPQ0k+a8SuiATJbSFIY8jGhs5QHP6Y98FCnf3pOFUYev0K6XwoTFK\n8cK91Y+4urz0z3GoaRRv483/sFmEx8hb3D6t3uN5/6jTtJIgO5LdM2KgS4e/9zBuwcIqamveqs1M\nln2NV8jzRxMvFWEeMP0ue4/JAY2/oRdF5Npzq1NZYLyDWp6Dq6iYj9z98Kk0LcCR0lONY/ZGZEwS\nOMsKRFErxYjWag2pABTESgcto7SKDoEnkf6oEVrgvspUjnHTk/3n0tq0FVBO2NCoXClv+El4ASJE\ndv4nRbKP5at3pVH4AJvQU6eFUAYacAAX+V/s5lPhi30yM3jovcedjMQPx98MghC3ViNz/96fovb5\nKGg+8jib4qySjDJErtr2a7WU+UnyClqQ9NveqfMNK7adH5kFMTziRi1dWqkjLR8WgMo4uU7LVSZU\nj240VhdnFmV/i95MKT0BWUeRpboy6HpQ6ULqJmAGDtJGkBFsEAtHenAaAbofBtq5rUMNJ5PUQoFG\nrl3JT3ZfUcLu06DxKAsf9q4M+ree0bjPrKasFmsEWOG+Tr2Nq1uIztVtza7CDZx1RtzDo3ExyMn5\nadEanexDWchCPaa3j26H8BVf9LTQxyxsLMFoWEklkFB+3fqFGj8bmfQr5uA3lsgUcHupRipp42UW\nR/thIcUbv46eT8OWjGs7170sXNJta+IC0OAmRdEaOW3WMyXPVtApsHCrhZ9yg+cbF949/ocVZVFl\n61WOMBhpo6+/0HZBCjHoIfiZMO/YAv1EHk3eL2OOLusvNtFKibq44+jDuCHWRKEwPfWcg/nnzMLn\nTd8IRzLvsoFdUNLrBvMfQXszA4BHHps56mWztGKnTt0iWt+x12LiN+ULDzHBu57zoRXC8qwBvDl9\nS2rGBAhKX0kkJjM4OqLybRjeEEhQuEjfjwot2g00WIoDYt8YuAoSmi9SE1PsmS5P0F9vd0kk7uPF\n+lxs7H9Im7awjzIwGzMyr8Ay/AuHl0vaBckTIY9PT/V1LdlHLfofjcVj6RKDS5TZ4dx1AoeowvcW\no3QeU2xE2Q5gyp1+Bq7F+0soPcRAN1ZBWRzSJGbQazNg90t2vnfaQ5wl9E/lBN8appzjLSeqN0X3\nhNjsyJV2mq7yoFgBzJMNR05zfyc87rBvRy/xTHQ3HcZ2ehkdYDiYMCku4ITcSI8wXfrsxThXYMNp\nbRNCeaVl9nVvH/5cTJIkvlsenFd4Gcp4gFvziWfdkPAcx8lJVDr+Ri8dJ6v75GWQtR8C4BAjhkxf\nY7Raayp4CK5CXn9Ksnwkghlp9Z7TvIGdirPEAuoc39J01SKPqYdJQ9/x5FjAXvVwvBIj30Pk8qbu\nkGJUi7FGiHP0xMgryMjjIyJwqavNbnjpnj2jzTAeDGsQOd6lvzn5ZpUUMFilAMQhycuQF1awNd85\n/DlwgdGnjuQ9RkLTbvveCS2D5B7sJXDk7ttoD2n6UHXIXbkXywmrpFDY8JU8HjsvlYLFqa/Cn3+z\nzcdpTGFPUTCtfnoCDvRajf2AvwytPH9ykUHzU/Fh631c7b1HRl2es6N8V7ftOuNSOMEx6i0MpeFt\nX/6p+R21o9ytpcaz9L2DOIFcdTewgC0WtQPouyu2o0OPaF5JZ/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protect end_protected\n", "num_lines": 4998}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nOWlRM/xgttOdlQwhRsd+sfBzwtSLI9T5LNL/6L1A1dDOfb1GgeIGG7yZKHK0P9oTEjF6BaJ0bvdK\nUsn2hSJaKg==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nkv3fKcrYS+gn7YKBRgiR8KVAabhz8E86yaOTpN7Pc6SE8a+WN3foj6b6hwZIcWt9kui2hIOhxyDV\n/HU78vNiPZn/wbnxyZKEwZAb9+G5a36HefpbwgJ8VLIq2ynGayiWW9Di4EGy5C3ly4tUqKXx11sP\n989iNLUwT7v55DdFfAA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nMIkwmN0QPT7VKJdJWbdjvC7EAsB6q7S+BWpNianIGtcfw2HJhwmTsSydRVxpzgUrzuysjAmfic14\nnMZM2tnn4MPfB6HLqjTmx6wJ49K2sDZmlnsWUt1dbQ4QonQUab5LHriciNqplVFxsjzWD9UGLzBC\nsEbsNMWpikYD8MOEY2ISRAZf/I2TCgp8bUYSqenoDm4uO8R+I8aDGp23WMDY5bOk59MorNlJ04p+\nhKkxCxUI//23/XSVvHEEYyMpFw4BSoSI+OZ7FhAwSiSdCbWwO4SQRbAIF2co/uEWrmai6M1vFG94\nDl+vKMO1LVmZjakjKoIqNwktO7CfV5em21GMxA==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nnANNAIClhEtnll6vMBjYFCGY6eAWbZXVkS+mgh8Phomqnnd7cHS+OK2G8wlaGcipgT0aLyxUcew9\n/TwTxqw+n9+/F2cuaVwe1qXYzx5EWasRdJykDAnoIFm122N5LBbSw2zFtmeHJN5SKJC6SFh5/Ukd\njpbc1b7jnmEZPtf1NcMQNYR7zENQ6vUp1V6q6TgFdaoqsCLjqUISG7Xm7RZTFykrNeHYlmnP0vEp\nZ75xNrorCH/jUHLV2bbiNO4VkMoDTyr4dngSE35+bKOpSOjEi5EJZyrbkeGp3/854TI2mmKTH8u9\nWC0ZZultS5hA4LqUDoVgkylk3PbI/wCUkElIsA==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nOpNk1ZZYmxyIc9gd7LivLrFiI302GPJdp2axMiK/hCDfS6CAHlTfaE8sYj3hELNmQ2EdVs5b5tIe\nx9naA4FqGjjwKfjeLA8jG8AQTutSTb9sgDy6BaK61oTA+felWLEXQX2j79x5Qz4aOMFKcPURz9W9\nyCSKaWDRRAj8E+aSC0fJZ/dGAbFd1Ed3UNBkiqqQ3Wy5SCOb5uOGSo2pV8ODckzDD7Yiuh1VXJKL\nvxl3cScXdhL8Gpmv2ArCT2jtqCQgL4vWXQOD78UPUkdMoX2Blr4PFOgzf6GiJYLZgBSm2FEHQ7pv\na/za6K3dA93YC2LYTP9rEzfjS9mVHNzp2PFLJQ==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nEI4p+r0N9EWfOjcyTQWekQUq4/9kvzPQehqRBUIKiN6MeRoGOar0T7rAWmpaSuMjo37ePkBOTpUT\ntdzOueH4Auy4JxXFXkctWuvsTg9K+ksLWC14vZhXyKvmdVXYPtL/qlyCHfcpi6a48JoFM9UURT6j\ngMaMU/D7WWuagFHnQgk=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nSHxxy+4gZViRr96w5m6rCLxlMzMTCXoAAqHIL2TNO2eeBk0EWPabsOutyltoecq3EKNu/6H0jFY8\nSCIWbNfjaZ/UZ0dj42wGxrsgXkyMcmg+Bdh9isB/lEL4Xk7JFOdNCpTAX8LRG3QgUf2SlYLZ5W8x\n3uaa+EaRglC/6Gbdo3VkRicu57HuwLa/egPQgJ8uYDIP8avGUxSHuAFS1LvzD6sdq5YK8/NqfDBh\n18McQDxYGbOuyr1VYttG1lSEjXS1+DC5y0WapclHciWS+6NgKIeDCsUQdhjR9yJE4nK8Okan9TE4\nErkXjXy04XWO3V9RUiYECNSSRvI/RvIDzlyOgQ==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 278976)\n`pragma protect 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qdzt//sdgBGPJhtk7kj1hhsSH9PCoVyFTVyzE6X08/SsjMkUCVvkH6aZLo/5SxPX4MNCN2UX\nUdazlytspGXb4l7zx5x5XueSqojSPhlKYMpNj7kqPYZ/bob61Vnvp0Q9jSBhSPsylcEkswRCU/DS\n4ORAS2cXtG+2tEbPGiID0gfx1lnlqS8xNgTw2xnMek8C5osx0+KjXjQlev2cqhAIvXR8KTF9TS2T\nIpEqjhi+/5OYSBUzz0UwUtcKRSbdK4ds6fKg4fkSAtV7nU4EkSQetKp7FlnoCz5NI3H3o0oGNUXD\nYT+0I0jPoraAPh+9W92TJHv51QgEGikL8wyUM+qdO5VxnamhZkwR2u2QK6vsLUPDp1FLwk1R61xO\ndvTD0wGg+JyxrGdMbPvkLBl37LT40j8ugYfUy2VBahuW7fvcsTseMHfWVWcqrB+9tjyvkzFnRqkm\ntbownPJiviJfOK2A9iZwOailb1w1C3ViS4/z3UFhsaAkFj/jZWU209QDzkAv4fAZetEUG12hS1gl\nEPb26umz0iwgW9RGhYpp+ZFzc0rTHjxxV9Rw0uKhTPRCbLF+GfytXCQaFHOeCOjd3W6zD7Eg5ZZ3\nPs1erYl8WXEO0+MUzUGP4jz5KoQTqfEysZCCY4qQiXnsANMUu4s6PszYqPl/iPoN0c84Gj8PXADV\nbX+TJMFlRETfY43xXVOEp0YGREcwnrv2Na8KUT7Ykr0cdD//KZJQ7dTMmUXIiYDa9QiWE3mW1dM+\netcUQLzrbRQhbdnY1+ZlOCcMgQT43e0Rq7P37sTrJg690X275FrmvxGowI/2r4qqqV6p5dT4zlhN\nYO6K4GNmSMLNI1+g/hX7QRhoy1IXwhfARxUebhadupTYxeq7V1mIrBViwfAiLY703ILzPB4jiCOC\nq4oLYTympYhH2yHS4Zst/dg9dJFHW8BA8vghjS8pVZg4oIirxIuwUwhyEgdO0VL7rF3XJaSPPL65\nvZyHMlQWrGev3RH+9zEdgqJwlUCw/R9Z79ZXF4ZNQKGb/BdMWbBToT9QgmsMyxec+DCuO2iEDhEZ\nXYcZO7Sd5ZKEunzIsxfggC07Lsk5tU1Om3MHVW41+uJQgUv0fUVOmyZrollQQLUxkD7AMn0hbS5P\njmkcYqvTDw7VaqLi4x/zlawI/N2Rf7mFKG/AIlEeQsA/1Ra3UoDlCSu0E+S3B+l0hXILmcxoDUsx\nbeg3gkKh05YB8/lwQfcESbiLGizrC7ujAHZlaqbowKeMUPLwt/61GnHll/fdYRC+ZupcJs4LVVyV\nLVsi6WYWVWx3QGjnbm9eBPpS8bKbNH5UqOC+u9J1J4pD01lHDA0Y6P5JjHl04uQfZAjv8BSkzrAE\nDnTye7+v7AiOkdzqnhbdTgNIvVUMEgOT5iLk+ixcDx2hCvrtGZK9MRIraejCsRG8W5EhZKTTeu8N\n9Wqou8iWaCBN+1v98Sh9/WkEPHsTSUM5ojDm5qXeINlH6eNFndz31kntm2TJUQeXpv+PTvqY9P0c\nhyndkd1poulGhepvxNkn/SZlcEIMC7eTdSw1xLzqoFi81lKJDPJhNXFQoD/aYLFauHya4bGZWuYO\nvn87Nx2Eb29ZTK46bFG9uwQVl+rH4QUUUHo/d5BsdVfT1MN7swMaVm2rTT1bTjga8OXye0EZKBtx\nn1vWDlu8+NqOl1897gMnZXEPAqFJ6SPrQegZGqTL4DxA+6RLce4k1WAhDtYF1CYH+RCH37Z4YTMp\nQwFqR1+915Dx0LhXIi+pKYSBOgTwMr7epp+ZgVL7SdmSn4O6Yls7ih+eqTM0M9LBC1hF4QrXcvC/\nDUDJyXRj9wn34cIVznVOmxUh4S385zvcGyPDoDapUA53g7Fs3MmFFprNnrs/bDivQsR+u2UrBYnN\n7PT2iLdaBg5MEnIm0Z/QFIGGBRVDriRxOZnC/Kgga/GTcs1NOC+phxCPCkWlIYauMn8aK2cmHVX5\na81b+O6oXXJBjpmzER9Tsdmwu0rFNzF+UWqnYYFaKLiweYYDBwMGX0BYV/Oc/rOhWmSi7VUbCMK4\nIV+WBXZiQZWq+NJR3adlF84UZCdmw87biwgdA029mEzD+BHS429LbG4/BzYj2va+mYEuf8B7vXzG\nCPaUO5T920qfBIbFAQD8LGaDYoUL/D9XqoJipBPLWoKU5XqueRGyY7k/MVIhTAZYvT+2hlPQZgby\n3ALpxx8EXIwlpDsCdXNCJXCS4Tu0WUSFzAcaVS6QqGCLFcXHllj8JdFYCOXsjK+U74RzwU6xuipP\nxrG+c6U90IA4Xhc+40pzdA3cVOtpOM747u7bLr2bpqGu8q1i03OPWLCt0eeVLU3iAj17Qa1PRY5G\nYJWrZwIlw/gLd9m1Qnc6loMN6oxI57mARaXF2WwMzduapHe5VyKnkwKyt9ZsVzyRpp7sHtgxwqUn\na8T49yQJwhdboX/P3l4XGvXHaFbCArGx4NCcJhisx0MNk5XVic/G77qYM5uxent3Y24zISr/Ri2u\n0tjuT/Z31yla6byeXeI9Kqt/ADolTQnKssky5VCkVdpxyPUfFWmu4dgSlWfQr1amDJoWjNmGHYT4\nWECo7NezMM1cdLjpAcUA5nl9FClJ9xk9qe68g/Btn+1N/odxtzU+zB6zvJeO4khtsrfcclfQcHzM\n+hPBy8aMUjlcOPvhRYxRHTHgCNDQLjAlqRbREfRs7rG4P5HRPixLzAeOXXI3JKNTrGScfPmgsPNB\nCZJOKODiXKqUAu4bjZqPwp69Yyr9YytHlvrAphkf+UFFSCJNQnlZp4OHjhy9gGlflbbpsNMIGitg\nWvs8/EPF1tthVeByeNM2YrSZd13lWwOuJ8wVZm/3g/uYYaDxQHR1JcH35tMFf0UJLNPxavjgGbUF\nTWgboNHLO0gC7gH6l7aXp1Q1ajDJ/wc/5olXnp8/V6rHsx/q/AHzINoXMf0zMQ0I6dryM0ARr7Fy\nenmiKly7pjc7Y0sktyouXB6VBLTL0A0s+hR8beugQ48kYy1nnWJnlhgze4YGst43IhjOUSkIqwrw\nrcrJMll/Te2eS+mBQnB+dSQM9ehHE0BwBREzqAjLkGuIUVM0tCINqktfcW5JTCWq78w6T9uvTVJH\nQho4tKfKcrf5fvpzoXy9LcryIYxOUZgNTbg9XZIiHMElwZOr3N5Q3nMTwUSmNhqTBfkMkrNLs+LK\n+0DzPsiPQNATZxZdBzq6r6uzKZUaoWayweBLHimBx/6GU2ggU//VEnIwRwHgKew19DcY842iFF1P\nb6D2+Yd++yVQn7gJDAEWIHHsZ56ky+EWJf/DMVG1Q5NDjSvDGJBP92bDxuL94xcR009S/t/14h9f\nj/6u1S8arD4wgmibpKJlaEa4pxj7QlHfmdbG0DIo6kruNXvxF80Sq1N5lnsmmr6Mm+EeJNDbZDya\nmtxaLKVyS2nzTiMF8k5cuCZFol+NPUTehECZ75OGQOKfNucaHOhhv0w76J5k86rlZC805JFFX6EG\nriyeoz++zGIUDswiTqhmlExMoKqRUIjSF80h2Aa1jsOIHvTZ15TrzZkb1yAjg+/Fanj60yPcixfO\n81MjL+DrvmLniLujNBJtjPolH+mthBIDh+biJyXJqOjMPmgegSwEKeToF9plh4/bjS7UtO9ba365\nfZZ11fWf98NrtOeod899bs+vmqr1MdbtCUmyUmdQe5NutDXQ6imm785y6ZMTKNkNBBDCkWIGhFLK\nWAV3HFo5eBaebbOfNr4kBwEhzpfbBEV9AUhc2Gd/w1vdr5Wc2kuOZn5GzOHhUaLzup54LEK3KETk\n/xzn3I3q4XkH0qYReMtV/NkZQqOOrzhjz7K6Q8RhweKl3iVTHP+q/k7L49pWdGBjkPYcFSQSe4LI\nT2XN7JddIbORE7zWLqTXN6j8IHz38iVY3R7pJml3G79wIHRTROFpbb94MS4UdERwQhwN00WVLuEZ\nRUq8L5XBmAK9+wq2qusK/zi8jrVr3i+YxIcAkWfy8cLmEp+9T++RjxKmjfK7f64BBxnuJQKL2aOA\nt1lgn8wwEyv9ZQSFKgIRcx6n2fAMnIjauWtDBmLdk55Z+ntqhvVRJwxfko6Tuk0PusYGpg6ibX5C\n7DWrsfe8+/4ZK9eQjF/cmeIHXhJpeGyfrSruk0PrPVJXs6EQQtARW/5S9zA+bZCrrBI8Xb7CaYPv\nvxwPWpvOdKf3mCPx3hIkQEGCHbBbs5vWckdPWNV07BZjuGrxhKTQuuiEVnk/qOHLHDaJNb4k1kto\n5X5ohWjsJyfuR8lrG9zUa7qRjVFG6GMoxy1lhjB8e0aFWhgTHPj09sJ0E8FFXZPbes7RCZN8TSxy\nCqKhjqDbxi5OybZ9uHDQTKOhDEnIYtwRt2BvU9WZXxV5Pw2MzJPvpbGJ5PRpf5XsNBarBypgsyMz\nFC73Weh8yZP7Y1ZjLt1GYXHiTNb8hzqqLfgS3lwsc9IH3TlMbox5h/CzxrqKu7hrciTUvMnwVQ8l\nn34fa0lwAaAfSbWx6b+OLNnjO4y8rvfNagWup0OgivvaUAwvBt4VxFzN9VpZvpDd8ojjylAzvqx0\n1v76XKydXieD717NeoxkQYvryMoPVYXveVCSb41tx98PFd3QY6QZVGv9oASGL/bC1fXHEYnfBAbS\n2AnjyHtw54XZnodELu7qxxx7fwjYN8YV5UTTyegjVDwe9cxHHyJao2PF+zxhwm+FLVdlhB8r8Nqo\nc0XZihlf0xx7A8QVjej1TOh4MVeXZWyWEIiB3pesea2iHapc5C8aSX4yL4RqIVRB/4k2kN1rCLr6\nU/GvnHypS4DfrJBm3MXlEvZYtBEoVU23QXADarn3h+7HLyOs3AGcOEz1r3MJnQcn20OB2M18xqH6\nuqQG/wqbpNFOLX18aZGJLFDIihvgrGDq/qLEL2qYGibyhYnn9YcRbKIZsm6hXf6n1mBuNYaJ9At6\nghWQkCX/ST+m+fYh8Yr/3Om8HHbkb3XXYPE2t7cQ06Jn05miyUcspKFcFKaC2O4v3rxmmNyHsoFn\nMBMsh3l6Igi3jS+KK8pAgxli/q4rQiA80iClxvq0q/dVDwu3YAOV57VNo5cBlj/al1Wtu5sodR5t\ncgaQjMj891ro+P2a9ll8T+o83paONsjZsIgSzvTS/wdVC9GRieYz/NmkQRecrL3FsrTmTx2ABoMO\n9ga/Exo2p4XzgDTc9mBwpj8mky5yaX75BQA+xA27mB4L2WZdLpL8nFfxpSx98d2yf89NfeT9G0xo\n/4lYK0hNx1P3nJ5ZptAYbZHfz98D7PjlRbToNY73bYH7VYSTRikzBhxHIiBL9qCt4GUh4c/QaTkK\n27MJLyPptPwO2wcQFwvA/KNF1nvs013ZnP1ovo9CAu8lCgZtjrfUh/MwSO8t9fxMJmQeJ9gJrg1q\nKhRj2kWp7StByXaNi+UVNHGnVCklNx6+Fk5RiJA7NoVLd2jL18Gndoano5FUMXcZhkw0CBZISKbP\ng/b33GJYaiCHe6AD5jm62WbqZ9WNeem0Q9EA7Iym5bbuqci9CTnbj1lPNB3TMj2LiNSUgxxQO7YK\n7QzfBz861+kenUhEQEXYj2d/ZjTLEkSRFikbK6aSRGc5On596MBj1aR8UVpOJQV7xxgbAnXaTJpe\n00sEJ2dxNaJhlvhxiU9D4DJQQHThUlg/HsetgO+6F9w3ISGrG6vAcKFZWjbW9mjCsZOrhyi8o8yp\n3M0mkpIw1xin4H6XcJArjcJMuvNkduMU1Ns43aMxz0RxgnbU1nHO8jKjgTCM/962d3WiHVf7Fyax\nUujTrFUA4llfppyKcCOrdqvdwF4p4HwXWM4MXc6FCAU3+R/SHgzBrvNLbIH6/Vy+Yw3FFXQJrRLE\nL0NT8WJ7X7jbxrnFFzHuBgMBvZF3Oe/vqQ2Cza6h/0grH8rkYCz4ilss8CuuGD8qWQRNBuFRoDGl\nymRJPmrrRL2Os33Kuwxjz47u5xB4t768zLKlefUI6DYthCcgjUFfM6lWSc6bQFU7qctmXGPBmIkm\njHtqXFvu8YnwtFJp0ew3keK7r9619ay5uMvpE593q3xxyakJlYtbTfDwdhGdz3WU6yzQ/SV5AiUE\nI8iCOtC6My6/oWh3xd23tEpf7tJzWw5KtA6hHY0Fl6dR/7uuIosuDHS9P16VQPtRGUrcdp7/E+km\n/eMU1BFhRYJVku69sQUPp0pE73wbVaG3AqVqR6g/QBwa81wRQ55fI0cvjRoXyT8DrX/3BDHnsv5P\n0bXelHqVLrCecQi7mOd0kNPhODwCSbSupDiUJGk49xuWVk5/QbiVc/hot0W2X0Yr1Np2c863U91L\n8h1soEdcfwV7GXRfb9pTWA3jvHzA/Xhl5Mel804Ub2a9JteoIMvtNtTNneJ1pf4xpZ5eAiGbI1Xb\niaaYGSAgr2IbZwhpvqsPJXsF2rrupzLXr3rG5zwJgEr860ahHbNYv889O/CjL37DLYWNFEKetBor\nn10XU0AiZ4MRVBUwliccG411AaUbZJFOPhDGkHnDFWhZDp6BNL57UHKrTbJIUAdy21UkfRXd5Evy\ndi+H1bUU6Sp4vl0eV6HHMLS+wNuMGt3FiMhdxfXu0Zq3IMqhEOaAVyJ+xKPu4l4FaMicFG52oku7\nzqEPrtcO4VX9khBX6j8BOIwLOFRtx75zCYL7Z2h1UoQ8H6WwdMYdYaMg/fUoioADiHc8/V1q7U/u\nh1iXTnEhn/v7sMswH4Tb4UxrIaOXJFY8iH5Cps3Sw15qczUqLGHVz0zXOVm/xu+bJSkHE5ggls8W\ny0x7gk62tduiiRqQBdZB9GWB8E8Tesca0WBKka7gM/gytkuVLiYP3fXPb+HTm1Lfu+usSgM9ZTz3\n9QPfifeBLUNjbi+tRfw9NlhDx66iiUpa6hd2y/vyPHmW2vTjosPZOQxcPDqEGvYCSM9LtKxWUfJC\nmpckoPH0DOF8HZVklSbPnAq2Y+KjzPT6+3jIq2z0ASesCmq5qFdEeUOsG0T2wl++bk5YAf9TAqkU\nILdK4uC5WTqS+8KBgHdpcWi98tVye8gAQwWF8EL4TKJ5y8zLmVnDSAARicRdFM159Mmcjh1Io6r+\ngiPNYllYPjD9HFyXcWla6eXtAGPYCHiIHMn0E1jQPIvdKJ7diJHpnvYKsZZdY7ZK4WMGfkdKy/yM\ngDdDHY5DweotUxK3oKxhOPM785zR2dtfYwO2hQZelg07iwC+ugn3oi0dTPINtJh/xiH+g4UD6VX7\nQpiHciN5ZQVN1nZ9SyBhrMGYxLCLBTqFF/PNScA0XcXUIgramiNOsDN89BX2rplpxMTAXVb5NNIj\nkvGZthL6idIDq6Ekyetkc8k3rdByZpISunglms4xOn4I976xO61DTdLidkpYpFHhXKKfIhBoOxMq\nh1YPr88CDhy4N9Bu35+V+i8fWlaO+W4MSsCy6n33CCpRogL9klc84ASIdDHzH3/2/R43+E/ORmiW\nflFuwu2uxUSAnWU8iixyOu5QG6rewUVjaxtEZuT/q5Bkbc29YHR4942AvaTGBOp13rSq7lTBCVOy\nm8oce2J51ajeKB6O78Zr9iWk+wiZFCOyKpTxYq/t4QHHL/UcO3YksN260iyolSYPQrpfGUjpTWf2\nqFABOmP10G7Ki81UXw7B/4vMYJ8THqWGFJUFuMwigFDHD+eC4L451jc+PbJY/7fHmzrbBYI+tMol\nYl8d1hu1SlxU+MKPRP5Qhsn8olO0eP5k+mGDfNt91tJ3SDhptOxzpcqSVwbbVoZiH2FkBDqvwTqi\nLyvEpWOlBUqF61MxjQ/vTZBhIv+Xa8Cu+KFw1aE6pxMgaADHLNuDjB8p0KK8vPYxT2kvYx0h0+ZR\nXrkaX5pbyBcn1n+OSvcmAyM5VHslVrnarN8R3nIVCSZdvMJ+10i6/kJzV6oAnaEliLqrpwqXsRUa\nltYvdkQTMyyIz35IXmEy1yQPNHAfr13b8K0Ni+HzST4Apy+51sdH/czYWJgulSzhOgd7HRAmw/s1\n3C3SLcE5e3GfyGezDJLu/2Y9ejdND8mb0E90yJeD5We0OMAxOp23ywPIskdyyARlm0WId9+sEb4g\nhJMcGeI4ws0WesWBslOy02O7g698pI963efudQ8s78BltTDYthUN25U+wj14tZ0sGBEMf5PnYJET\nC0uyWojHTyzknPQsy78KN00q40vl0vRkmaCNxGD4Jrm+/kliBH8VX4xBnyYL9GC1Fc8aPmToqF3d\nLdtSDwSWb6n3aMk0uau6jhQtuObWeEWkew8he0AkfZD3XUxYNuiMoekuDzHY54tTJXPMy4K61/2c\nDWUZLWceDtsFBX9oUTh7L43Spfsn6WHa7dKCoacAAR8vbn5mkW7ZPCpj0t3lqUbiG4v0mQlDjbHJ\nbPPzC9UmDKpSKSwQFyi9phiHng615IuR/QSM8FQMIfqsnQV+FnGVsaHSVlNQadnW49/+7qi6o/Fg\nMTKEJmQ7Kq1vnq2gV0nPaKo4TeTo1tH1lsVmlS8MxjasdP5bePtyfo2wpXLArQvxpcoSOuYyzWdG\n12L55KBPDOMOB1kJxBGxWaZpVP65pnjv2TA68+jxcz3Ws88d3jpTCo674420IMsllhkKqYLYbHBB\nyj+DRbGOGFeb7NYlirNKMeSZQHrVbihzHimfAW1rIAeuPZA5ivEOcNOeUrL9nIl/EjlWaj8InNA0\nEZ1H/MyrQMpyXwp4oge4lN8pjZqG/rAwAdsxVg6sAYwv91IufRmJQsSk4uzFFqap7ivYaRJdr93q\nHv7Uh15Rrvn3IJKe2bDuQop4fZmRx0ExVtKqitVpgOYKkk4/mcNKA0vEThMA2VmY4MzbUL1ObsTc\nj3QBITj3qvKXdhPeTEv3dCX6Na8pfJuf02aOerWDS5EugipnPXdqlfRuOXXHlyICQYMv1adU0b9x\neM87fTGa5yaNzHoRbt9fWDsRfo8y6DxeOP5YhLp1fny5LM1bmJ1Q++uJORcWyHuw3jyKpesKUs1O\nPKaTfXIpmZKSjZlnTZsuDdAD8OeF2iXmIJRZBRnf++ywR1GSRjTJAYhL/JKM1YOjrEKNzmZ6kgI2\nApb0KbS5TUuPJ7tFHkayg2LXmEuPOuSys89jUFLzRRnWz4glxGsY+/sXXEyOzXWiB6kT88XTrVit\n0gL52XYI9r6D88Y/kLRvgzcXtGIX0K03mxYMvm/945tCKYyQyBf6NyemOdFvbdzNoUvSmMBk9tGQ\nbIyuV0Lsz78x1XY3snj9FR5yEufGrvHm9cj8JxhJ5FRTWK0XUtKIieU8dqVxatsd715WuZgkV0Fk\nDi5ulCOw6wHZy5D0lk77lYKWFh2TGGcn0/EITLRd8XGr1Z2cENFkbHL7BFsmeO0YLm8UHg5cNfpt\nFiHuKsgqKa3Dd8+3Acqy028QfluD5ZSo8fk46QhjTScyaMkd7AZKFHFu6LoVyLw9z6lfx+S55jl8\nFBwy0h1ZpjbOosVcqLt+XWaz3kfqQgCMN+S1X11zSXpkSYqor/D8SeaexmpqBE6lMIPYZEHoTQ4A\nHykD8pASfFTtoUIAHseSSMXTPwJf6hAvoEEsKn8k7On2uaHdkUJgQBj9Oeb970pLuQXmsN6T7vW7\nzcvzreZghU18/JGvLV2CoVb1t9cnw+/gRttXjSBWSX8FHN7V4mJcUDVmc8UQGbisulun1qtDDYyp\nUX3SjN8KmivdA0qJwEEyifYoJOrfM24Xo0etzx/nC1DxkfSw20yD3Ol7MNQ1nTohf2BWquM5lJ2V\nO1rXNrgLBQETq1dymXrTvwjNVgln8kLdid2dVBsWeGXXDPPwChA+bYE99pbiKsYQz121VTZijb8m\nXxE6wZ0WTUIQZjswBTMjRBRBkHooaUCIZDL0MakuKPZFOJAJu/a2pMcndcJsU7CLXog1kCkwHM41\nVmI9tYngjpYsZ7gHCFmYOwenTL/USoh2VEzhExB/T+dEHrS2npd3vsGrpmd99ShGVIuKLJjXAJYH\nfv44U4WhTWmYra4AZNFic8sKQqZuNOpzXLAoxINESNX6G+naVbhe3TA3ucPDyOtjmVuODKNKgSbG\npcQSakw+bugbPq+WsX2r58BW3YRgZUngUG1vk/JX9L7R8v7sdppH7a9YdtQSs7eWhB0jm/kmm2xe\nGS6GnruN5jE/lrNedKXDnbcc4bHam1SaphBtxyEzpfWCSoWznIg1Xwlwdp0JTGgjtUGigHDAScQs\n+20SwM19lZH4W6b7731PwYey/Fv0UqapGFE+5bM2olrb2KrfPajPd8gHezbqz2DlvOqDldFMyCer\nIuxhCK+LvkKhFIGhsWn548W0hNLEiHDDzejL3tio0zyQMpIByKPiVuw4GJwnaaF3rf5qXFwrHsoW\nKVBrqGNOydhX0EnPYpZ0Vpg2N+ChXloE4jK9ZtbTsykemE1GHQnTulLqlqJfRM49QXqNq+LrAnBa\nCo1clpU111Vzoqk0U5CDCMxeh0TId14Fk19U34FHIk9R1zAORsSenPN6uPjrneuS+xrAhJirvTmh\nc9bOOxI5pGO+9flM5Y48lfCmrq2qH0llyDFzlygzigt/VjsmWIVVzWi+zswIRZeqVoLWmwqE4xPd\n6S/WsLx9JKt0HGBuuPL64B5Cd7t9WA6MR4fZon//8AQt0m7NuEZHcLR0MW05z+4SVOL9BLLjVY7z\nRGiPcvFkOBoyzgsvfxVwupI/wEqzgGihiDYrepurGJqtf9Oe2PggChsyo0DkLUa6CjV9UFoPKRxk\n7TDQI+NnYH7OrUrnbaaonx8o3MHI+YsXfIrmyweq1MjeHv7LP9mvP4DRgkicQtGLV/pioW8HAbto\nOBedpAGxPOGDKSWeEjKG5uQzZU3FJFeC+P1+wIs/fNwq12s3GvTL4MZJ00IaMNGVLoVTjpoHiNzn\n5czFmA8QHTcSqHGquTrtdOAWdi33qKzdi1oV9cyupH0wR+UWXSF/qCTEJROVXVd+1z16JeBWj5Ld\nrUEIKPKw5i9qtJsGLpABrG9Yii0w53V2ejp2KziOjD9oviEJoPCAZt9V9rjoy5PkCrLr2KOrKPHq\nbBYUiJNmEQT6pBVaGpCSt85ImBUyJNJwaOkrumnleFggisGeiBEJUkyZXbY8v2YYJGTs6YzsEftc\nZlhVHD5JYkvF1SeRP1W66RnTocjFFh/rsp4KDAnHiH8Ac+9xhuAaZ+liKqKN3+9v6rJlmzAIicvN\nfSuVpEdItZOjFkgi6+RuGT9hQ2FtshJVq0Tpd3ODqxZ2JqELeb3oOJolGq7sTtplR9foPEvwT4Xt\n8wWSyLFiSO42Sc792OGP2EuYzonBYvB2bA7eWR2J1jEqtFHwHs+bGUypnDfg/3/mAU0JBiO6APsb\n3mZAVtDRLRrL5cRs1UJAnV0KzapiFt5g0e4w48gFnhvsrcA87UZLheikfy6WtwAu5GIS59fFMQhx\nqIVwWICJJYACrkHrIJTSL4XnL0z6RNTyS8yvy7nwpSedO1F96g+OkvTofRcfV/yhsobQNm2jEIw3\nuHe0qJ6+AxMmPSkvy970jNmpTve4TcrXkFqZon8Yobro6t5mX0rC6YtpwsmpzG7panII+Emmckjs\nc1TN9kjGDEeCBcYblOPk0NSgA4ccu5srUxQ+zI1S2TeoL9IewVy0yKMAbQkfKXNDITgEcU1P9dc8\nY93sjm1p1kRZ+DyD4wLqbw1QzWW1YVwuyNs9wP9BvGs7RCszV+wG+LCuePvNDshPo+yb9H3N2wC7\nrprvLhs3iVwTI53hJkAo+7A5gLvG+2rbRNi2tnbLY98MSo66UEPoOqzxSaQUKFsLFDwrYuo2MW3w\niREw2mYJZobMnW8CfmQUECdGJvmUV67GLTlAe1XIk/1ajF+NLIFBEz/0I8SLNnLQBBwP/wM5c4u0\n85Lx7YGZfq16RR1YqsLwSXGGwo087wOzpXPnMlOLvAIiLLGGFHv7KO8EbE1SVvkfP7gdb8GXmy6g\nCqzalCnpl+83HAWaDPJud2/eO7bOiU4PVY+5qFo94x8308rZ34s4kQwgTdubm3FbnVZ5I29A/esu\nBIEHDOJzjhmSlLw65IuUbEhGwAsdMMdwIW4jyFenvLel1EoKKzCuexqSKgdEqNygbl9uPabIE1/m\nCdny7Tb39OG79JmglarA73gWf8WyJV6Xo87c1hhDdTITOSutabpJrjrW19dJLWCW9YSicfuGpNIm\n5Y0lGsY6dSr9Bgy92vLOpQalzTviuBD1xyInpwQuoli/1gVRInOSk8lxb0tbJBd1kBle7K6iTJMF\n4n0f6LelL1+1xn50m1HQygFSnrMnqvW6SPWbipD2cXwtUN4ykMSP3KfW2Jo/N5bo/vrBHJsYX/Vh\nYzAuUx2HrtDgFjqlwfYAveXzpOes7HjCV9ZL98H/FT3otor1Ue2K3rgtvTnLqZk0+8pdH0sHdpSz\n/QlD7rfYkrKUZbJMKiAkRvwpTUi9Xc0Mcc+6Sov29xOjGHSd1Nt5F7vP9y3YZqLlyFkGOABa3oQA\nSl8F7K/DKwlofqTC/h9BCv+Ykl/mO1Ao+eMz2sLZERC2MT3pKJQeNCTGXwnXxA+P4y7tbHAJC23f\n/xq/Pf82FKOqgacrGpC9Dbm535fxLP9PcCKoAzcucZQusR4bupERnflAMXwo9wcfUnnFmvAaX39P\nu7Beja4skPMA1v/XmQ1M3I01v0TJrSwwg1pDGjFKvwHlhidkUco2Rm/0YFwo48TAGOcmTAHytINB\nty/fN3PT6kb1Fg3XXZ/8lOui3J1XU4tTtifANhqxnedlZa/3qfvmnnWxqYuvvxcMyMjdTOfx8OLX\nas6W6cpa7GJ/Q4wcY6BI1sk+9LpXEv7mab6nsxIYe+D9RK/pLHf7F4Rp1Ei+mLrMU8GCIDMOziF1\nuvSfD6GMS6Ca8ZdpHUvNDvuC4Iug2eSRX91vf+Ha7Duta1QybwyUeDTWAaLdMcEEG2tKwG3gFkRb\nB1Jk4tjSHve6QqU8DtwEgrzkwi4jzyVKXHo+rcMn/COLWz/hmJDE/Vd39j9PZ4xtj4G5V3D34p35\n3uCdQ6cap6LOlWT2ryZBcnhusmmVEvG33stN8wkY5g2tpZdY+B3uwnmqweJ/FVv1v0UaFSboxn0p\nwjVIDk1ro5lKh09JGpsOuTKxGzgWEQzpEwpfALtDAs/7gNrkTsDBeUDPu1N5+4042W0kpCCCD7+R\nM5uxYiEEPmExGNOLqPRmcj3hun5lea07VpS4VPO3Wu5EW+OWFwDETjEBUq8IqZasYqvpwdISLuB/\nWtwCN2/sUtf3EPUiEDqCpHFyHB5tW5oZF57dGxk6/qm5+3xAlEeuaKU6Mv+558aF44SEGrgVYBgB\n9HnU40sfVTqqT977YzMUtvpcCvH51vwrEgJbhHuhDw1cpSeoglZfsJ8E36KQljb4CibtMOiXEynO\nh63JCMx1JgS4ucnoo2YAgQ8NxM0bQqXoPYxksCfM1ktm9X9I0bpo/LZe/PE75HAdelgHVVuPbkhR\nokN3d7ChYpjX5U1O+SW1jNegw/OVoaABhI4StZWq8RjWhNMbiQMTzQTPcdn+tdu2S4cGD/tGkPMU\nlILGt7tMoTrr4djhOMq9EOPzgPrY4RAl2KHklbMMGcANCb0pNtHT07puDSLrd/x5Sq7fpHHXW8l4\n2Nx2d9T2Fj6JfYiwwkYutWQgb4m/8UDvrXDwNv7tnH4LcNbigbCLN1DnNaZkpDAD3EMtNOZ9tPWL\nlsejN/yz1q16MNTstm5Wzx9YQPw/GQn1CEaF7jR7VGqMZU6K3NgOaKhCL+i4AKYxu2EIal+OTzYQ\nyM1J3GBgnA9jgvkOaXpZCCiVWhfX65MtrbC97MM0jyyXuxtPGBSQFcn0DqakLTa0UzCpTeJU3NSb\n0obYllCbQQg+5AkFd1/aqXVV1Dp9Meb2To6dWbqttNfvgsA8M2WUapXWdevhUCWkdhdGZYcNEjuJ\nUTfeBfmV0n2CWHcDWcO8Yzc59gLkj+uVXFNXTphhKbPXVZVqOETV74ODg1dRXvNxGwRwjfIg9V69\nEj9QVaXeOAvN4dm10rITkftWSCc0NMIyFhXFDpjbEz9tUV/fJgAqMEWl8dZK7gzybC9lgPYZcReU\nPhPHkOB4HvC9Fn+GJ68NfC3O0tYTs/PmADMkZd6zZs5Lc4ShOuBgan+9aTq3Kbx1q7hWrCofmQEP\nHAnOGT4GrmmG/qicqfWGfWbYAD2sKwLNFnziVCcyWAmJVDGrsThIo3giM6pe+Gqv/OHnJbiSAICG\nKLoIxR/E6XZjNYdd+pzI/JyPWZPfjSzzwhQ0Fa9/iU5uASubLlAAVmTkqXT2Hk8/oUM5ViJMCCZl\neG8xmsyn5qWTL1y4oDBZOt7upM2JaXUulDKjW9vnsn//0UC8vIbznVB5RR1TR0r1bz23lWGYirq5\nEw37YXUSmo2gm33BTPgM/eMsJfrHXM+6M+jf7ePOav+O7VfwWvrSW+zyeuM4bPNWtS+ketnuhrQV\nf1hQgbzGCOJbySJQtFnA20vPACTSx4TPmv85WrM7k1pymXh7644OS+vCLiqZMmjmsEpxzXe5QjGN\n8AG9bcTni1OAgph9bL8PNPPaZpGT14muRBbbdu/R2pg33a2uIiI9kQjshezSVtfiB+Ig9ZIayBlO\nDDCBvcAud7iR1HNoFjbNklOqz10A5R39V2kQIaEm13i9lVBn5k0iCCjR+atUCJntvofvv+Glj0SW\nrDRasuLCAMjYM7rTvwum549oud/3pMYCOtVkNxpIXgFHikcd9VkDZSddR6cvaersklmGJvXGZsOf\nPknf9njgFc6DQytj/74aI9sXc/G0/gGsyULAWzBaW84hjlyLydFc+4WfU1MxG78Cd3aQDRk+6H5T\n7TuuudZvbfmZoZBRqGVtNy943Wj8yyUtQm3AWHp5H8RggUj2CdZZQ6Q6VU2icMvjGF9pqPnxZGif\nP27qcN7ygCeNPeEv18kaTW62V/Rw+KpKtv+EGt5blYvMQAY1Xxk3b3ysZek0zfKDo4Eu9qMEKlNv\nZd0wsG6KWuHXyj5gI8jcGmED727tNUnqTphoTPL6hr6+8rQPRQICg4ky/NJs0I4oolHPvj3K0Ejy\nZ3J2ydD+8DBwDnykl6tYrjUFEiTtDJyY2tEyQOBbcLfqpPnJmT/P7H6koWPdWllXRUV10JaNOqJF\nrqtpoSXi5MTYyRwzNKTUqLvpY79uFOg42+acpuTbdF1oKceZLrWewkmEjkPXYuk5MQrD0fbLSOE3\nKoCdjbavtQxsFZ+98zgQndVre36l+tmrNT2SQWihLhKdKSZ3m5NpyZ6OlOlWiKD8JsCmYTrZgDZv\nYmPwev0ZXhzopbeaLtyLgV75yb4jcryIFI1wE7AkfBGvQ5Hot11J6idvyny8d2X+opD2Z8Yi0KWO\nBPqvrrUyidCmy7E+mmF09lspnS5OrcNs2FQPzp0sd/SlSwiIFbzbSi20Kj9aM3VW3/jS403HBdAX\nodZF7P468pHSYCbYZsURw1SUmpAn5Ih+VRHXiiTZTTzNOiSQTId8IQmCYoR3jwRfvDafPX2oHqPm\nnetCotHPu3Y3VtRrSEd9wTmyilllvYEntjZm+5/nQgA514XRPM4Zk6w6NuXvjTbyJZNRjfc57qYq\nI9Tra9wzgPfdfbx0ohmMNUjz+L7xDrZ+KlOO9tKTu5BSe7Pcf5rXXKoTeT1yFJ2MTMGiaQ4iRX+y\nZd8kqWD8/vXNJBh6ULw7tLWXQeuOsjFICVxEf8w7SduHrJ0KVPpu1bHIp+3v15c8ubCylIxbsdgb\nrvAn1eDEnzaL67wf90K+INysmgmnMSzHCdyZkHf0qI6svNtjLNNszoJaG0JBEWaqHWVangoI42OL\nlmmU8pw5mOj6R2kwY5p/DQQM4GJ6440GLkvqeUWfrpAgOXbhpLcDG5geC6cUQOAocjaK7XGLSVrL\n1rw4k5n+tJw97rGjlaNLC0qybcm6NpSUAo1VibMMGnY46o+iMdkqNADcSFRKoVVMo3LJ9Mg9wkga\nYFeVgqPlUKN4bezN845wRIHujBb2mtdxdShjAePMPNPq898P70xsbVXIjb9YxBUIICh+VxHaY7Ox\nQTOe5kntC5P06F2NbrLLSgp4FWYIzd3t3Vtcf2QdCxgWe5T9wLchSWNy7KVc2Px4bHcN01XVeuB8\nqRMKxjKKNGPaS5DEKj9KGyczHwgq/0r7g+SohU03i4AWc+1CcXwtvKL1YLqDM52tTkJwgNoSMbtW\nkfzvjYDxfaRucCAqcxKNl6EV89OljaWLLSXgnFyiww5SVFArp59o/HqC60R4iaYYagDNy/hc8ysv\nYRgpVgXad4VzxDmr+Vg5gZ8jsiKiJ/PLbkdQGS2pwPqbKgwmG+9E5N66kyOxLMtBEuaRACnybaAw\n2Ow7ZhKOaZD5rj615Zp764hhdNiJQYxejh8FEwBvM38wImCvWXKas6Tae+LnVEzNKnVnJiFC7mlV\nMGTWfu+vVmJD7eTUED4FnT5fpqkkhS6lEVpP7tlAHlbJ9fy3CvAblR2pJJwYHNaL6dWJdEKh4EIf\nP6oV/XORwqD4tgAU93Sm+I6GUbufQf8eMaEUwc9wQcAx4c7Bn3gdVJ4Fdo2l50flOIss63l9Rkaf\nbTT6Id63oCk+5NuRnjB+zmkLw9VU5hTqMiK9lCrEMifFAztOVwh8DnJp7als8BJHxxxORj7MYMpO\nMZ2VKo7tWjdJjRctMSAh3zDiQRxTliizqOqE3eFqQfpk7C0us1tfJxuqdzrubBxNM28s2dC9NixW\nmsDSHjJDMdZdhSYw/sOGtHwG899F+BxrlyEeoE9frrTnAgI/dTV+X0YcSq2CkTckAFhEGlqaBFku\nr4m5xv812FAT4uSyu5jYZ3GpcXj05vtyGB4cth1cOhl40p38B/IZaR+Aykbzd/fMg+VQOvig6S0b\nyzNT2pkveGj++1ka91qKH8D7OnjwM+l+d/S1XfOwOj+pHm7a8ka/OpAvjBDUHb+ff5HIHRlP2Z1E\nrB8suOnaarEcRkNo5K/7xu4x04NLVUisWtsLGIwi0qK2Tio+StMtdy8GPOEjpFaIALZnXc7yMjJx\nI4xVmPqtKbhPnieEZP/V3imnAQzfl2y0i/azvG5VqKD3x5drih4SyL7x1UWSmlouYnlCDjC8Jwlu\nCVB4UYKYIvhqumxzDxdVMs3yZ1YUEbKPXFWkXdlserOwkHOcJ8Z3T51OKQ78joaBjLQmgUX7clmF\nyptTIw7fTFyJR+wyhfAqmgI/UhKTGgcEiCn6+gUjOGIzxR9iBGi0OlvrH/dFBWDw8nsL1auai4Xa\nd+LcXd+3L4iAK9hSL+aEjUu9aVb2n9cDJtTbJ68uMgRidsaJH50xPT7NmnNeNlH3ueC7VOV9vt5B\nzbwFXF3csiotWCe8mPIJV5xqj9r2dd9oIoEb5NNoJVZtX77cjIH8IKrpDq4VJshNEHGlBoFwIiQA\nN6YQUMfbpSga39sDe5Zc4162gHzYdABRz2sfSZx6tv1zuW7R2ZU3aXDqAmuIaVEojUTwFWz1J68M\nksIKHDX2AEO8DEQnmK7joxKWbjc1u4w0VamZ95yN1SBbZPyh7keCnC/8rCnrIdWPIYGgppvp2n2f\nZ65ZnrloE9ld39guH0FQucAlOaSEz/tqmckUsQDuV/+JPpYZFK+mqUbTw3Lf0RS0uOe7A3lAzz/q\nW9JIAvvF9PmN9PXvkf0YF62Rv4qeGlOXD6ONDJM5m0ogvcumQnGIqBLATJCx4CGmXLrZtKEkPwg9\nr+fJT/huN0e9u8RrMKfLlNcu6YVnOmtP4ocjlUECSIVn0LyQWt4qetw9FfLL855ZTQASirgiKK9P\nn3dFt50jkdqDmJMcUkdHGEASs8t5BTvauRTarnbu0xvXujG5AaJ+wkDCxcdwXNKXDRECPyyc9qIT\nVlGsGaCI8T35TCX0rr5DpaawBOHsxrXdfl6rI9vkA29WSqFPI2cJyzYqE4gsmqs8QnjwGc8c2DFp\ncX0zh10zKZujNlo8EaIaFmVQ3ZZcCU3UfNTTsXSflEeKY2uumwD1psDqwbWfEZK88d9yWBcobkFN\nj4of7gWLdT8gpkjeE6ErcM26tp2huew3tF2pETeH+QCijnumzLQCHuTLaeZzQVx+dWk+8fxw18p4\nNyAgHia3cgVDVBBfHsm1mHkg1RW8hzpX1UD/B+f4Q/OgrbWwQbiL/R6+DYgKO/pWpF3LJnlFBnWn\nWnzm8E2hRBeSnrlGRTs9w07zBAdEPvFFGZEL50UPI+6qhyuA/7j6TfEKIAU/Y/vC1fCDei/Y8EWB\nAjQqFtJFLfUqe7pq1lMoNkU6uA+s/ZFqJz5c7NG5ZILxTElWWmGC5uU3tKY18ctZgem3jLY2NgQd\nbRN70RfdsUWSpR0UV44oAZ3udNgCKrgKbM7eLoBDAdI1ltZrznsUXo30FppcWi6TK8xiunWsp/nb\nsdjK7Yrpdr1KXZ5otY5bY3TooJ1jYbjL7RXmcyXa6YQJMr+Ud9/raX8lSWgpcE5mNSAe4IRFn1ut\nPPom5qYFosDldpo4ha6SCw2u9JewjARwZvnR14or9CekD6J4T+WC6Ond+FT7LLZft/XhM7YheX33\nUXBh0JNl2r8Coj0A5qWFz1wu2J45bNhBpeRx+E8Ma1+aZZrwkkmXRm7mCTG6Waxtr9gd3PhLMxNe\nkSPN9zf4JkBqS++xcxDDwkGRtN3LZ2AyIXA5IxMG734zbzLREN/dc1wa8RGes3Z3YsCktwJRI6aB\nbsB0w75WklwCTZyuyI+/crCm9+68Zzor7u1XfHWMO33ZrMnTSGGeisWq5hsLGtOKd/YO8UPT5sts\nbmhtWGDXJ9k0zV9mVHlwLATyBvK6awznO3y0mTR+9eIyWt1LfL8LFd3EPRVjucthLqMf7io0D7aU\nTROeks0OYwlY0rnPwmu8kAyX7/GN7rHizDdlQ87hccE5d9HTVrUrzspd+0lcqk5wqfzarWvPZThg\nGs+7HdlWvfhSY7Lsx/DNKBfAe9Kvm7im4zcLFQh3nPw8Q5RfS4HfyujPSlMBY79cObo+8ef4XJ9Q\nJfh9StWLwkf7mBViEeW0GmWozAfdpb+vq5lwVSreVzqBjacVEfsf3IAnCxrNTGLEJ8gJMO3nObW5\naEGWl1OKH14h/b7g+CTJdWcEIGZM1F5R0gtzZ8r88S6rUuA30Jr2TxI0f/XUeNsfRG0LmKyGOPxC\nAxmVQPCkeInIEE5DK0/yo51jjvQX0T2wDFgYRy4qWWp4JnBBWraZDcknOXXJXwXGnKZnGdryoIxj\nM1TicgYQPHUgbqYQbSTg4YUUmBOLCO6chSsL/liUOmHPHWTv4Dhw/31BOcb+bluHLsYM9/7gCTeo\nYwQVSiIpbceNNlEROPT/cY5+PIo3HVMub+dxEqX9kb+/TeP3OcXzahcNAHJ/a55W2S/vIlj+QluT\nESQShQ0eoW71CacJ5oOlzO/VtCFVSgEoMoH9PnMT/cf1eAla1iAZHgi+ktaKIPu3lObmq1PRsw00\nl2l5uRkwynk53PIdkNs6KD73HTmT/dNeMMvZKn4aYgeH5oLym6MWfGNv9tSyNO4V0bqB/Y/VP9Aa\nxYGL9NpVU6k1uQYlAubu0SMEHPnpI2UdREgw29/xfkYZMbGaCDECPdQfP26jbxPXc19jEtEC0Y5u\nFsX7y9U5JgS7MwkJkuDkkeMpBeHHxTsYffemzdeGADxlve8JJUD0HLNUnCJu1XZO47K6OkdTH79m\nBWlf8WHHo06NFffgifT3UwA33JMok5V3TVwxftYRPYH4JLm94h6zUVAYVTVw+84I8499OINiozIY\nhKzcXdxo3PmI6CJhkT6bbGtW7n0J236tORO2wxogNt8PPRhX5JilFbiA9YJsH7WoitVUyRwWjcNB\n9fcrWjuxmFR2cH90oYzC3+72PLdRNgG/wXHd/5h/Aji/Wc3OALGgWi0HEI/oiRsKP609pIrqb/Ho\nBR7SQmHoc+VarQhcEnwWYWcS12DOJhWnms6ipEOkQ8o8sGMzgxFrDc9wi57RsnV3XPrpkib8l94Y\nRk1+9UPjAHk3h3tb2+3jPxAaLjYzw7PmsFjGtGAwtx8uBV5KZkc1h/q8YL5SdQHn50udI5HuksuT\nF52PbexEUXmzpe0PHZJINVAIF30Q/w7brVP24FfmgaHqiXJbhL3nW+sHORzZWL+vs/y/+vmNnN/k\nIcuMjp+tTDHtgM6LnyTp2KfQEVemEtA3P9d1+sGIeQWAC8sTj/Q77imqTWvwBI8ylwgjzYd0EK1I\nnJAanYjHkse1yYAnz7jaI9f7L0LwzXud1Cijd8jOmQ7/QWo8eQT61nyrA5D9YvTMwUunaQxKnIOY\nEoXVqUOrcsxjeJxh0pFn9FQLY3fziS+XahMuC8KoADMxRAb/2QtJHnJxL5iU2YFWlwo+o2Hn1uNG\nd+GwOB/Wo8HUkJdvis9NSv9GCdEsukrG+HknZ7cd0z+6SPCE3M/br82R3sc0ZcDFk8aWjAE5pUqH\nyNdJ8OPQ+oCwr5F22EmdJHrW21Jtmtb1zB+nzRPju4NHYy8H/7Aw4Q/RKPIV0wPQUIz8snOyip5v\nn00dGkt1N4QbE0SPFKjl482U4FJqI/2OG9mLnFYg/wOJWCZDppPTE5lK03b1Nz+UVjbcQVqVAkae\nBzlX3e0T6NMZdLklwEV1C1odQzKpib0iOzNb3CwTsqeyFrN4gLCZHkJPBhFbaZGnudwvvO2k69fG\nrxpG/Pv1yn5jEu4EjGWAXYE7Wpnq/86CApRNX4eOELg/L6cQUb7rvlrwX4nBbZD7JpOpeYvBVcXX\nlfId2rfPWKy2LvPLQHuBUI3w5Lu/O+nJ3GdXQ6DZ2y3aECfyVy9GYUBHEVLJQypOBroIJDbxVjmC\nUGQgSw+sMmL48+j2KYfhlCeO7/smZMQpKVys0/L+AZDksZbcEyhA5Qy9XazS4PzBqctyVX0+lQ/x\nZc7nftb9cK7qRxbMpaqT+m+olKKgK7Ul6bv/AzDgCJJZ9kK5c7Dz9j7werXwzsgfguYELkB6o/zb\nDY87iizDD5cMRY1dGMq1x+KmI+2/17n27So9NQ3IJuRnMpHCkQY79VHxC6z9ODExZjCqnOU39D2E\nqArQi1ch3zSkS+6WvJCCgMmj6JAg1caBSNLGasIa7XgzyHyplpSGHursDhtWviDw6eC7qH2R3J+m\naG5teNAcHFNPcxxbGegF3pRGdV8/Tb7sreaM4mndVsLgiUyKcPdvwNoMHb4jSPUQHC+sb1zNd9AI\nZMrpNOsVXcPwjuFyVoeVpOPWHqQYLODN2vYEKHjWFZcbHqIlTRrFhdC8vesEBXtECzCweParyOEA\n4p0T/t1EBbPkuuDVQE0KGC9/obVcNMveGNV1mNHI9Ix70PeJ5B2F8JtIHtg59BeANw7EI0oVOH7d\niguQKxB7J2z6Bo85hmvtI/BtaAS7dniYoW1gM11LSC1zlgJxltOdM/xOzLS8dXIc/KHxJLjomTdW\naJt5kWNyRcUujUwZo1C5ahlLS6v1/TztnN4gBruJyId1aKhGGhh6SMXKv9V91AbLouXQRFe/XK3C\n2eSBDh3mSr7IEcnjQoCfyTyL7vXoYJ4QY5J9Ktp99wujEIFB7A4mwzdBVzhUrE4S453oG4wFfxDN\nMFpUNg9ss3Fjotamg98tonYh6HzyWtDGbWj9rRxq5WgcJ7slur4nP4KD6n/c4Z5nuqZTn0NNe93B\nGHo6EdFvorG7AqlthvHMPi9LHocd/pInZoB2pv+ejPvUA6IcYhIEB/bYhqOrMGIMkIPbm10YSCfl\n5gyp5Z5vMUUrmzdd/LOxiqSzKjt7qW/ylGuZ9v78EnT5PTKFANwLEu+LFGlSnVOeoIXuCE74trum\nM1fs2UDFr3TOuoqv/8NB0OJ8wNyCPHiTkonucLeBXI64DPPrXI7rCH3UEqRW7a6xHsbuyOGyqTy/\nnIsDoaWgRTFQOuc+4ht9onP3DPEN2smIbmVp5P9qRdAqoKX4XN5ruIwJbYA4GvBMfFtdXF+0900i\nzC7CTPQhMHTcG4W1CNn5JHKKg5WlK4pZsM2tY9EUgaqcHAtVMmG3Q82Z1faLSJwGrsdVw9Ea0HRO\noiQna8TCyL/jA+dd8Rwux4soDOTl7ZX3T5Ye6aBJ+Phb+WgB5YrGk03B9KKr3PNSMNbX0p1F+x+P\nmHZOqOS5Ie5+slgJBQ8ni/K7I9BPPbUx1RzABXMIJ9Xq+/Iu71dBtvOCOl2Uc9sbOXilJ5TipzPO\n7RYPrgqIAudI6pIP31hoBrGOpbQ4LBkttp4YZxKQh1oTOEqMdLnQByer5ydwIGVHOkautlVWRfaX\nM5TQb6460hm+z8Sscbc/RLwzC4NxdEtpstiQyBcq6RVlFlJSDrYfnhW0BsY5XbbwT5E4eep3szzf\nnAkTq7YzYLdUFkvgKiSX4gtcAvezwkpP6EKpU41wFFuN8ulKP4GfPiqSSHP7iT22U7fVMUxo0H6o\neJtwotPRT9JcKIGXgF3uoITnmuBy+g+AvHsZEd/tErsjBBoOdiXOtgv52zFFtTlF03pRjWmxYOk3\n1orMLW9H5UFrj8+LLTTLMb9T483xKLrlK2V2cC8Zz1os3+NkLx4v7Vp8ph2UhHHTY8EFsHdfWqtW\nJh2ALHhKeCLi72/TX8eHb5HtK3OiTWDr7+Kq/GfhaeY+Pu5gH0W27PFhecAAc/m5lRzhKGPQE8rG\nD7fswDw+KUryjaZGROoUi33Ut0gOuNWS0KGf4gW02CRq0pOVZgw55xUSTokaeMn0pd4u6xcA4kDG\nQTNErNd6sv4QNxRM+GJ+6D58skFBli4NGDOCHcV24d2RpHMnTduWX+CBc9LTY5RQRDBzZQ6QqZ00\nnbPWmwbzz2l/ZoJ8FXxIrFBPO7/dUvq1HKHFDmPzrDWHZGjcRWD0jpbbaofivvmxnOoiTbZ7NXXe\n+xpE9lz9vuDJ5RHih1471EvZsgWuCSWn62pM5CH2A4j/SKl+/IQ90AvqL9VUsbDCvR4n8ge2NMMo\n5Yg+mn+RNwvkB+hxso/6zmuKPfpkl93kjNt7SngdeCapDtJQoLo16VfBjRhQtT5A9NSEIIzpKp1X\n9cbLrskbY1f9SYIrUyOA6T8v4XIbXqSHm/wGGKOc2+M7YE21t2sx5EqD9jZ1Ok52dEq9Afa+5ubA\nAezKqne+Ei4/O7xLpbUhIj2fTJCpUHl7ORBudETxXKNbDHzJyGoHBUjQcPVHvghi5m7LAtweA9yd\nus5A8/H4tDqev8e9ij6uJ2P497YYXihDvAMsfZ1Qg4Z/oNOC2BRScg8z2CwH3EkfV2n5+SmicbxT\nvJjh43wjmm2Z8oZVnAIOmaPqt1/l459e3n4P497mG0kH8YxBC4ALTidKMyr5ud2/b8wzblKWaZkX\nWptO+RwGC3tI6in0c/t50oqS0AyrbIzzpjETl7MdCeLrGHJpj62cI68jup0o32ANx/q935svLhOC\ndeeuGLs19ePw4cW4ikxGU0kbfN/fuFcxNO+LITcVUXOPIHBsZtsagFaGitSeseecKPqvfPCEI3ez\n/NeuNfQ04b+rzewV7UNNN2gQhBk85A7wT/EdldMhjKtY7HO9gUK1OKUlN6acRWSsXzf3FO3NrVaz\ndu0LFtVhuboN9gJlPTHogi+7jR23uV15lLOHzwvQ7HRahz77pfYw5TBzZ+9GIVwvSJx3v/27UU1i\nhVOv2GEPugzg2qRT4NCbVXnMGIUfBeyWpeDcJPcdgx0KVohreN8w3r0nG6o5syCS5qcVeWlncBHy\nBb+4ArzQOl61FLFUOvXScJ5qjXA7MH4U9H7Ik8tGCOOfkq+xwLKCLCMjUcrJEdAKbWoUziamCbrw\nUvNUb2x0wjc2stu3CXgNdCGxG6ZUPxtfmnZOFWXHpLb24wBqtDyfsFSdmGmvz6uN1/qKhImdRWPV\nlZQ8pVz7J+1oZPEjg7MasajTRvxB/W4UZtZ97cLVH1YZIkB609V1HtSALJPUIhm3lCiNDL0awfyK\nyne1a1agD2VwxDBrxnsyBVkxSnn2H4kGStt+NJM/XHWCsr7NoukfpAYVTWoMo/kBuQZghFwLdEFu\nbv3qlf6cQLJVqw9/b8hBsAd3esSdqqJaGmVTNSgL04R0mZWRxcwDTTLeT2j+mBeSZWLkaooaQtSk\nn0fqkt36l+FjhT4i6g/IwUWN8zrc08bdbo+lKpZobBzDeOfzpIduvDiAuWJ3Q9Iqpx+QhbWCTFi1\nKaU2+s1IMINUpPtwgkEj3Wvnzj1uZTIv7n0gddXvwjuiHsVXdAIQOYHjpmEUNeBvhMhORwYdKPL0\nq9+XIEWUZnjXA7WlbLTtIJ+7l4AmMjZdJ4fUO1XkAx5+8j0fOYKNwqcDbFCcsgV6ZeIM/2cs5YgF\noqCqxxYRs51Aqks5c/4W5JLvvqYDx7pJ8bt4hghdPgocAfowZ+x3zjuSNPF4pSNLGmE3kEvSx5BY\n7+65y7Pa1Ax1hb0bt0nG4L1/qIMMQFrOK6KucvH8fcFbaEm4xh0IIxhQhyo9JYM0i0BvLdRpQbet\nlkxndfSbix0qa5oTt+2BLOP/yilRTgKR8WKU60Wclfbpl2gsR8OKBTuTGyauzPdvjUz/QsmhasjY\n/HO5CtbUSgWZVDuOHysJ1X9TNkvck0d5ppBdhdSzhQnAMCeh0mczuZ9d3hq1XEniQPowCsT9P52O\nYYWlJ0/pldQfeeLcv/Rqb0zycRBE84/8pCxhmhVrYhEnbbbEEI16P4ybcpP6XajsBGLUPVZ45mgK\nxHet3zdaoW6EIoLsdpcs1WhzbXyHyl52gxd3GUEFxcnoDD6o8Jpz2vFNN0N/uplMFt6cs8akqKQk\nL/KRLwxyDtiyM2E6DyF5ZY1D6dr0IIJ6+zB04/4OmZUkddvaJpM9bqTqyEEjx2yod6viGmgAkpvs\nsLAItUHyP+MjGmnU8d9yQtIYXfFDzqC080AXsa1Y6abkCU2qnxZK7zV0yuckNTvC0q0xj90Blns4\nVf6EJRMcdBCXbbMf/e/BIZIzql9yk7NVW5gjGdRHjE/kEHfLaNKZ8+gsUzIkj76dzy5roXYtSXuU\n/r+SuwSbDCYh/tiO/Q+5/pQXNFP7aEd6xEXk20hLkk5lnlPYsyCJ5G2rSF8swJf5jpk2ClqfwKgM\n7x4G6aIZnlIU12dyoCTJwCTY7IJ6up70Sev3KJ+n0+Np/6324Gf1j/fhOclKxGnvsYkmaOaZTvhi\ni2P4J0z7hXtbvYjJiJCLw2LKebbSpcvJYq9AyG7zf3QuBzDzzQdUCq7hYOk3gzFlMFIrvn80dQ4u\n0fGCojZPxE/oJFWi6I0/u8q3qWNAMHVlX5nHx0083HURCB6MhhFilFHkI7ygDzsRqgmjWv5aUHXz\nfQH6/vnbWa4uCPn09x8DUlOcASId0iTPl0L9DqrDS+hYOuOMD0R4HJ1l97dZfz3lpsL+B6NQf3IG\njq3dUkZ/3HnSuslP2+2EJ2yEuuSxSYxYWAzi9mvNeESG0GpiVKfBZ4xxtStmyafn20HY5tuaxZeC\nLez5voUuDJ+KCqTYJEY3eCYNYX0tuDkDo4CEDV6E/WCl3fhGsLlCapSBIEyCRTnLZnTTy0ZJQlqa\nKyFZDDxx4gPbaGvWdqxswSzaeD6vrMjL2D94h6GGExzUe7yI/nSnunx3Ni8zzj95r/hF2JORe7Bw\nvdJzQaCM7duRt2Q7tGFj59m2aGwnrRJ27Qpann5Cv++ETvNF219xfg9gxAl5N0TmThV/YvPSmR9D\nWvNJ23mvRv0Mz7KFehB1GZ32LHiVHZ5xOj9jnmP9ogcIVMrDsUdgLslF5v3hsJiYJ0ulz12CID7T\ntef8/LHYkUaT8L9Ip9gT8xp6bOgRahZBiALCdnrTGUj4exebhZuA4ZCqZqrgzwxWY8hQzk1hcilQ\nn79DAxaS/OSHEPZrrCJaPeJnoCaTjKYyooeZXCO1l5N3sfUsgjmpROzKRtmjgDUEqEARNy4nvNd8\nnR5jyXPXpQYNLITzVMrJ0ssj5WKe3snxdipxHCIRm1jSnhM7L/bMmOGuHNm2FPG/bLB3JevPKzSE\nytK0HN9rGYNBsuoMIvV9b/SKVpnblynt+9qADGNOno2c7sLd4BCorTbbfRMpIE0VgTKyZL4np23t\nBebmTudkLSor7+NvkOAmQ3M1eW7bFkHQiXut/y9Klb+7a52H46q+J+ixLmZnly67PqLY2UuFPKjE\nN5kF3fi/c3n8t0iAphEq6HwejAW7PgoVe75rvo4prIFX+J+C/D0MacAr57gyyAgB3i04xpR6Z9QH\ntz4IOxaIH7ct4n7Kz/yaZNQwS7LRRnGlZokANe0+QUNeAvc41YzX+7X6dy2l6LPEmwZGo8lryC9e\nqTMV8J1o/M0fHDXU2x8L7pZDR90i0WXDk7D1x13CBBtlqTl+/4gAKbbyYrNPQGtxWlhK9g4yTdSV\nr5/ovmbQL+8i5NQNO36HuyNLfidJfJMHdVLLGAGhR9DRlCDLKObKChBNJO1XmEdUdAE1vmiMMfD+\njyoJIYQHQUdT7F48stkYeUidC81x+HJGwVUFCHN8GEGdvdkeBk+AkCCN96m0f5qji81ZJD3Yr6tb\n9FQptmy3gE+5ghGYSc9j9WFlxtoBKIfkPgzXovSXeE+zyEmq6ZKhcVyOWEqAhnQsY/jVGOhYs5m+\nuDx1mA7KNY+SNO38j2e9odY273CXTBOoX9OvWYrQPGywIQ1/bIBMRn4T5KkTRkmfpLI0FlFMwi2y\nZreNKOj9Sol1TYY1C+Hy8xiFKXntqMLqwIqy2Se6l6fHLu/FaXuL4cutZgZT7D+79DmfMNp/Pfpm\nLJKEZsz0iJ8OlX9mdB2GFJA1zpSuIjWLc07ysI3JVs1m6AfRRxZuq9EN19WqY1Egw9VRGC1DqZRW\ntdaFIk5sI/DAUuDLWoJTAM1bOX2vnwGpuW3hTY5AKmmQ3szbnd+xRC09JoJ0VjvTEK2eJtJMqpiY\nb3+OoMP9FswMnqN6kC0qZiJzzcsoWieOKikyadjUsrwv+b0OUwtyKUpBy6E9xWQq6babqe+Wh33E\nD5mn1QT91U1BP7QVw2tMRu9vCJb+5Zjecajvq1ptpjs908TAppALDClVIUz8JTDhNdwWhKnVT1DI\nsR4+2hyehQHAxq/835hNPM88EBGE52C19sKBd1j1vWOHJnkdKwX1cbild2U3kGQqEQVA4CUTmV9p\n8rPcNLDyr+oFaLJaDrMi6y+7qB8Fw69O8xcGtkTgra+A+h0KdEnz9s5kHycZPQI+TFWTx7ukz4Om\ns/O/ZYEtkY7HMtI/u1v0F4AH/sDJ52WY2eQQwTTDoxnsf0Ru0s7hxRDhQdwmzZhWAKlIDeYjY5H8\ndXXNW01/vy1GM2egqlo8sZZo6qhf6IR8l6XJjnpDvG7F4uieAbVQpDw+lazrgkCaJU4hvNNIOLr1\n+1J8FhEskxkf9BssKTz8MZy/jxyNWwKNMKx4Sc7TjuE+PgfzaeOroILBq4/uxyXYWkq/pneAPS2A\nuSkSqSXFembDfXhU88utq0dxKrndyUMYNL+RlpXkgrWuG60W3O//MgnZb8tFLf1QNNKH+O0mApog\ngbX+X0p7P97XeKVwW+sxGPQ3jZ7k45JTVWdH9F4CIocE4omOj3EasjCoiDOMokZrwzZID46zlAfO\n94tE1FfJoEDazHeHAV8LVFvJVjvbzyPLlnLitDlrBEzcC3YTzTHkD4eSa4AVk1GlDzcG/DYv+Lyn\nc81Z67GpfkMI9Hktdr7Rsc7PR9hUvHBFMSN3RPu74TpjsAqVXs8URl8v1pNu9j1UDvX4BOFN9wSM\nOVjN52yGAISFKyk4Ms8Ecw1HV4tF519PY+AUcLMBxCA/pQc/2dx5/i9TGby08Jh8cGJuTFyIl25O\nHYRwfiaXIJ+h7XS6+XX5pP0Wv/U1vyYDDrfRA3ig65KTmOkn3Zgh1dYIJEXxcrBeJPE19uprEZFa\nWGjEiH0GpT9xZXuql0jlZnTOP9GsV49JwiBriF8UeUqQyFIskag+A83RCkxS5vJsrQHPk9MoZiLg\nW5Vq0Ci3qvuG8zGmiKvfsKn+WYOOWDGR2L0uktSHLTESTO9Gq4F/lt6rxLA0Nycf67y9CNzjUxWu\nIUzGzlnFcslF/mS663Iay0GAnY0azrMcj4lcAtvshgUQYLBIFHVhsGRaGJLLIf4GKjgZipujAbJ4\nttyTVfPka09pwfQBRn27Emw7I4885gdlziqBvI6M0MepzTn9GC1cs3aHOnK2kpjzHnSNgVtmPAUH\nST19tLpv8JH0/F3z1nACYZqIH+HD/2tTmDJkzqjDR8/l4hEX0MW3EHFpcbo48uhKnPs4a5EsURRo\nNpbhcwFMePDEdRtdd6LpBeEroyTzE9LkNNcDnJoRuA76uqjCmQktuLJ+rl6M/mUMZCzVld+Si8Gh\ndNjF96JJqsAKT1Wtwm99mZJ4sHbVCgNdTwIK2SvHVqcwTndgZ/giaQclP/0wNDTOCt+q5V9cc+GF\n2SlvUt8CfuLpI//mwQp1aPw0+abPh4OcJ7rev0BqxCSCrBaitKVXreN6bVicquM1qUmLBlGSqNad\nLWGlyzncu5RyYusWo6Sru/jB8uNkX+iUftyLf6f2bEDb3Me5KbOg4zZCjLNsiHZSmMAhfbQgxCLn\nvs9pwTJVGA61nHfrTEd82+gWQgXUSelj8RUb10Sm+8Muzb5xMInX5yH2b2GNBirGJFCydRy4iJ/w\nrLC1PLGubZt9z1r8Ll/bELReh8lrx4r4CQQ2aq06sQOF0xX2HAMMH10Xsn9knNXRzPBqFvW3txYK\nP8Ot6LCWc3o/8/o0pds718bI5L7/PGDf6EA0mTc2nUGWikSjRYEKrtFVVFe6Fj/b5htC6wBd/1nJ\nDW+/N/jpT6VLMSFVxi2eYEbeHX7s85xqQdRG2/vzAWOximkjTvcs9i7whwdPW0rHk2X7AB3pXG28\n12BNY7Z5HmDa0ZVE6ZQ3QYvCccVHcnMKbsCtaVOhkkZalOGJI6P88Fhx0W4bsgnEOQJBqM/foALt\nPBLN5IGsxMytM85PpGe92gE/WDtDyfatUwQBArBRCA6XkepR/ZTb6Ox099OVA6eJGfIWOt84WXM0\nxNC8wyYnDOKWzqHnK814WAhPVHpOQOPGT9S+IY4l5+9pFYYxskDSQIxB0yHhMKOIRLz+GJrxYRpU\nzB80D7cMUaH0lpRM50jiUmlmkrKaQ5DffFD0LswazDVKInECs1zwLvKiRWDPGo9WIRvp6xjYnzDO\nypI8ssdmJHqhxD+kNLR8XfsYge3kjm/mqTeCLLkGmoZQ/pKq3Vle7l1bMPc2hb7dHuZySwPJnPyY\n5tHJN1/i82DhHak/YJ4w92oV7E9yNkQR3QsU1D1FWQlkjMMdtXXa00cGpX49BcEBkY8CCRDp9HHW\neKlldt+rQoN9pxyBohwtOPgND0fOaVBEs9WdZ8fSaQXAIwRf7Hshb5HoMiBUlemR26JJv/FK6aRe\n+nz4HUtaCGt2rHx+mldWDvvkJfsIT6mtgBM1FJwiMcRhd22y09ON7LsgUnwjf/JJLa7MpXxregz8\n49IeEFgJA7h7fXL7NfhdHqa2rl5zKosf0os66kPtJTtfxuiqBlD5EXq2pNuD+z8q5hsljTf6LOsm\nrZtQZ0Il97ko82gUh0WruzoufGvgOyV8zr1oeDBU3WpaEmu7kcgkTm+9Zq8NMQwmfbCiJQMMDTgg\nlkwt4jvgJ+xYg/QF6uQ4ECdugY5iZl8Iv7MA3eaUMuvgjSRiWcp3MSVgYTx+S8jse9Ho0J9BDex1\nVdsB65aoQ6cC+Otl2OeoMw/3dXSjuk+DJmFpD5UALLtaho3GmauoBrWp6upVYEJfdVtsKjLy9tBV\nXtP3g1ME9NlWJCwuIjURgUUhcXv1jC/NSJmDaNLNAKCQd6S84admg4VW5uEKxpDKJk750I/v1hWw\nYnPy62B/cgmYgAFgUbr6rz1If7qw4f1fgSydNtSyln4WLw1Cl73PsVbfq4EA/tJG0ZXuVR7wD0cq\nr7bjfYB9twk2Q38r95wRZyaG9ad6KBixMKHXmBIEOFKhYr5cpVsoXC3qpHHjQsLS+N2h3GYdvcs/\n7xxaNirKx3a2nel4/kXJp0n4LtD5zRsw8PEHUHSPbIvdj53VHhNSmUPXKNVPYUJZ4TcpM1JOATBl\nmK7GwGHoqme7t1kiG+JRArxI53wh+xBMx/DuSe9SuwtkAmPH4p6kTyKLF6Em8graZ9LegqPkDXRP\naZshoJbgUY627/ff4v17RKrH4Vwhti/+9DHH4CZhtfE1nmd9G137nByrZx3QkdoZuyLz6f2dLonm\nqjrD1Uxe7EW/199N/UkfR8KESBorxFxOqcY3fAmAIvwwOc1O54GeRtk5xjBp/X3fqvQAD2FpkXw9\nrXWyVxVLjQgOP9HgWLYThumcI6PcngfTNHIXEIP1Zo840iT6O/pFvQjHhAsYYFnxt4RYn/dNJaFb\nQbR8noyRIUSDy+Y6ziV7ltqLOr5XOPM26E7AjJ8yf42SZNavsGPaIv9KFbtDYLfAFmOsugS7zUmP\nDc3VHeS3sAg/tWcfSTuf/kPUmEtDOnT6d5KlwvOjyLPwVz9nWrkUAo50AS2gb7sYs7Vnnxc0iPQD\nJgvsdm49zv05SJ5Is2o5ZDPZi0mh9FmwxLh0pkiukfXLdHr+FWBBxsCZtnI9KsSjQNAZg/Fek9sA\n/POBW9r6xI61+PJP7yOz7olGcKW9+GMGbMq5vslhY3DMEtARpziTsCygpUHLy2e26HPuXlkv3pVW\ndmsExhKFjcwtHEOU80v2/xYx8hLEM0ifhPyiaNN9gjd5fXWmGdomZQ/0zHckS1x83AtYJgh9eTUQ\nm+58mTLskPs8dbxMYlN2tTe4bifwQtu6TUGFSnYwb59CqkPi+iR6xZrP1r3IYOoAbvno1Kr4tdIc\nxuNnPdh3LDClinsHwJOYNctCHsHPL14elkEV506eyS28fK6fuqOBwD+r6tK4wpjp0evK2btJ2pWj\n2mA9pdJ+xnZhZWHJzjh5JqSfntEhYedq3uiIfg9Z7KVRJcfXYe5PGva1qOj7EppwtwaIEuA2XnIU\nyv0DNBGBppfQm6Wm2EVbkMU+lWZxrIywlRlZfQ27YpRZqoo+sxBL09daE1NMxY+Nlx1ZB4INaVMo\nzxhu3smL6P2WwediJ0q9fuyfXvQ7NcsK4KECHxePFkz+I7jQQECtgbc1H/fhVg5YuQPEIeQCBCHB\nduE9tzXVVY/wzXIw/nse9BH9Um21Rj1MJHDiJL4+j5Jv25y+KXVE++DzUDOHXTgMfNg1SLqgR1pQ\nLAOCyZX+adhTAR7hYNWpWh6xam873YUWsU/F7qHKjDYshibGVFw0JdTz9Xfb5xlmisS9cBlE+s8z\nq95FvRseortxWjowtahA392kvWDvx9sccO+69hwzWNxuA8Y8906ZGihIUxBPJftVkg3FAvAxayXK\n54GT+MeG5jWlLV0q6BpNz6Qi4h6akhvSUmYPBCZt2i6RNHN4FgDi9m8UplnvriLgnTKYRV9rb7lM\nmuQzqv9EqMKc3Q9aEU+zpfPVNVhoL3W0XM5+iOAcyKWPFh2ai/GBK7RxptqHEWZJb/eOXkkiGXa5\nE4tyO8AieWHfUZPIEqql13jCsHXDtFwk5lrdtY+mt92+DMw0VIWoDQqx0mJ8tvOuYSYmvw5RRaM4\nyF8CsfajsrCorxLRdU0GJHKJ89643X9qT4mKxiOviBCRKJDSritLEhEBMqTIZVS9r0pe6Zhkspub\nEqtPqBpiLYvAG/qUXReh/O+TNHYfLDHUh9WvUbYLN9zt7LSPcSuxpImTu81MozqvhrFyUhFY8wkj\nKseidMD41i98/VuCybxkbKTGiwvL2agjvjSv0EyreK/sanyVI1f/TFn3qObafi/r8lQ5WmoiyaaL\nVFzgTZf7Qn1n4DieN6zlJAnYFdq8GM0t/aj/VaYw5/LYOe2qBjONuBq9H1oxFrabBbkCB8ySiqW5\nD5qwe3Js+yQD1l1A/NYSKq82b8arGxr2gDXjEtMYaTf1BG0KBzbVY4BL0WcRDSm/VDJae1mLkpqL\nlFC4gVRV7hD+mJTsrmU0EPmn1wy2gSFNxx1gUCzpqecOfAmQHqlBv7ZPJ6TTLVhVGAlA5LNbfNxu\nrgIj4MxvMnQMyiiAWE4mruKxehLthkx6pnwuuzKRjVSWg1k/2ygHhnmro8hK+uohAwehvWxhBd2N\n1FDjAKIVR/KaNE4nVOkwjilUu5iaMW0cxFL6cf2Br87R4bWewniL5/WVWCNbPVVUo2BeXvdz+wED\n4FvX1uY+5EjMuqGLoSBM5yKf7e1tHBpv35mtZ1mbfly4j9TZ97yF4QNOn0JhdacYADdLKa2KiSgT\nT5hL1B9EMg5ZbB57sKYUsBlR/5Ib61QXrDSmK5WMHJGHLXPIT7/ZtAzz8d6hI7qM99pLZLCFMNpn\nvgYx6BH4S51Dl9x7p708zZFs+6PUxRJ+Gddo895fe7xVPkpV1DY6vlsDd2M0U9TKFY3TFH77LgWK\nJCWKSW8Y0ResasT6udWGMegzvCptKfNiqOoXPd3n/nX53+ZxX58BIYaANSK6mTbZL6EbAPRHR9BV\n9fhBJ51raCdFrwVRfF6kiWCeEMNMvfRGqMIxphdFlqWs9x09Buc+u5404Vbvw/Cdwvb89a4NYJ3z\nqRfaX3/wIZAJKvr89CJfPBINJQgmi0MHO1eNyZzdgVjhBpmADM6hVOW+4M5RFvvJOHpLLcpFnGhs\nAZr0ADqj3ufkZ/OCpOp8Anh1vxduE3kmXi8ukDsHmQ5EADA3MQI3Vk9GYk9CvGKiD2GpYs5xC6+i\nDCum2ij3d+51eC8rxdEpOdZYfpO//T9LTfY7oaIqDnUJLSbLdEKWaNoqx6YcR5R5n28WsuM8uXb/\nCfRIPHKk4Ub99hprthuZ9Ik4ABCyBOacQ7CCf2eBe48a6nhQAhMcgE+dz79hpSkJpg566tYpdI+D\n+VrUUXevsuBhiZrMth+cmSrKBCIC/Kq1mzqYV7f0Xbw/dvKKjSM/0TE9PHd67Xd2CchbZ5c0nhZr\n8+1TcNovBsnuC6EC9DapaWlUHsrRGiGUmuOfNLJ8h6B/a/+f6BTDsA/4//SpkYuAa7dw2QEPycO7\nAi7+6yNLsAxw1BZGW+SwEYaZ0Ew12WVpO4dKT4LuuRSIQaKH6UWdv/By2Wuv+Yo/589HrIU9+2IW\ngLV0nxCu/NRAPbXYHQM063XDfFBtjvgQO1y95sukh9C04cFgwgtm+22bITkJNRq7n0ZUSwc26QG8\noBZdkYe2vOoUXn9ItFPpBzsv6wD9o3w8Bj/N3+umSwyR3QPWCMd7YDhm3UIcZXFAGvkumqSA1Pb/\njRUFNrsW/jv95R4WqlZIv2kFNll+Cak47jxuCCMDN6yUHBksdAFcIXcBOcRQDeClXcBX/FBUkdKE\nQuX2QcRx+ORboxNZOWs6uWNdjoAfeWAjZWdTEHNl/Sa/T6V6x7rctQ8+qq4Q2dTUgleRWbH1gAYM\nUDcUz+oTqhlIj9a+joWbfJ4PxcTRQMwhpVH4xt2Zb7fZ+7SdyL1g514e3QFfItG4BLnRcsgVV/UT\nU3hTrnJJgNng+ODjtvHqBZkjaWr39Mi6QddBWoZunvTjnNBt3kiv4LKPDBCbqvmXSCLEZZoCcO5N\n5JM0oLiOeUvp8toTRzUlFlodRkxkS9K11WovauUAxOWenY47ub6beBco7GJc8hkct/qI3kh732h8\nLMj3WBKsL1SFPR1BYUu5xALUTCWePV07cPxG+8p8KYRVKLkGmN14KweB0BB3LagCMIgkB/vVwBEu\nb710H5kdwMgkmcc2WQyuzj2IM8O5mHpnP58dAfnHYCpE+MzfhDpGkgcuyFzN743zzL6erlmmRDjx\n7NDx245JNqODt+VA2pU9iA1hpt4sa4b0dUAwTql0r2yUnRPxT/QDOFFJWOJZIjvZ7C8/4hg+1Ptb\nPK5il2UDKOVPvIzax/hUibSfCJ/xVOWy1gl960U3d+XAdsgOBQcojoY0E86hmTgFM47pO3Di3B8H\nO8F4pK1+Tg4HXCjbN20Y18F5l0+dxZW22JjqVkLNUv2slkUbq5Yxb6KVxqOdoddgUAIlqBcniDke\n2DgewvfEmoZZdD8GOU9iVZtE0d2km4XWKtdXKbf/i5chLtIM48Ale5j6GTL/pEUvHuhzHUbQbqOG\n9ZiCXU6tiMKFN4XNqgV2+ZJA6fOcO6nn87YQvOXt8/cCyFI1WrlU612j+FGzqc12zLiEvqexH5Xq\nPgmIIikmqUHlU4US9oS+oLd4bf0bxcWPkZjdyADtoOqFrEg17lUGBH2lkIKyG/s2YlHM6Fi7yAai\n/ZsEVSegPm2B2RsaKUXt8eMMwZJTo/oU7nXCFa8562ai1eIWs4cnkWq6FkkQqwYXhYECUO9YB5Xc\n72n+YIgvTRE+IrUO/e0U8qjeqrmMzEG+zoU7cYvQSzrmYuFK+cZePUu7/D5ZozPt7ryDizdvw26F\nNR2U+1/HUoJOf7Fo4/bAdkh7TbC5sbmXyT7tHRXp2rPCOR3GvLsRA7NX6/QbHNeOaSyF4ORR834o\nQ/i8kDCc5l3j/YYG3BrmoXxTdnoo5xdhlVybWgdvo1tQttty2vTds7ha685ee1zRVyUiKrvAw5I8\nCy9UXfuL+4LMtr5MYa3pLEOKuRsTPHvvW9d69j2S7WUWuhbTQXSPTQtlhn1dvjTxgXXppKgwIdBg\n5eFITgYP8VxVkrPbzRYGZtO1SDCr2vh1BdYaWylrbKFBdd4D/QgQeCth0owIjetxpd9XPLP50wnP\nPsm0f2pOAccjY0dOBlN1cKMQgmiXYI8osd4QXvt48/a/L024nik7f2OynctQxlCDWQMLMszMtPWR\nGwVQnJTTzPoO21JZPrf2jMQqeoGY558lxUDzpjtz9XUrhUwWmTdUWlXU+PfrYxAYc5G3YvmqsrCP\np6aQDCmRCcPvPnkySvEzmwps5aBiMsTHM7hDRjzalYJppmR5n53QKUeVLkcvYuPVKVUrimqEvJ5u\n3efyrgf3hl+k0YhmdcabjW1N8gd+bbGKhXv2XEI7UlN4wb8TSoh3yXOuDp/HoCirJY+FkHQRZ+35\nvKoZDDsNz6KHPVy0A3XVWNlAxQju3IlxduSSBAVQfkykdpIyWwdzjT+PdQ65CrmDLVdUXEMMVn4m\nXA0AiwCjuGrIB3mJRug42rJ22NU56GAANCDM+9wTh7gRWyPOm9C08CMol520wPyfUiKNvxaX7iLi\nTXtngrJUiKyRvFKjqQP4ItDlISDO8FxD1F07O+Ruy6ox8XnGUic433/4UgDSBV7DicVCj1r5BVHg\npuDIqG/HHuuXRUO55Y8YyXtnaeizYF7uqHyNkYyBAf6Eiw9dFeOPJENRIGjbnQkuD3TPdDDjnF3L\ngLwap6rUAxKCbXs+Gc5sneSjysiw+mRSezWv6/jADcmLzxFomNkeVduXwSkt6IrNGuclmvOfMWJl\nxC4gmvtS/0xuKVZ5c72lXL81Va4nhsYWKI75g+9ZfXB4bH4fl/vj86umMsP2jp3LX6WnRdcWeQdS\nx6xFLAeOTMeyTRUBsZq0Xsgh5YNrj+feOmwFzfCRf3oDIPHyBmkygxe3c+LWDStnpCGqzzD9ehQ2\n+Oij+YlzxUmGaGE9YbKCeZyHocGXJGAJugYA9XwqpL9boc3ua87HePJENt2nw22TvN13fzwXwc5t\nr6cA7ivcsborTupfFcr3KQgxetkqpfh8WLOph5vPh9i9NtQHfslIUbDF2o00CKx/mGaU58FBu0I+\nnELL3nHdxYIEm3iTs1RACHfPUkCP3cx+ubh+3TB6S7qMBIdSJNFaKM7hnDJnRSG5Q3nN+XG8aRa5\nfLBdzX0eDu/h3BI7/zSlWfNexPmqpvwPXijx0uJGwMhCsD/Ux5iv9CUTtSDPUEikt3wUFNGrbGKO\nYQAwZxzlzER3ZiaB+b2mrQxYn6OakT7Tn6wKaGNX31euY0AS1VvYlbP1L4sRJTcimgK+q6TQUfgd\nRa8/i2NCUUEt0RZgiwxVG6Dtzg55eftyWfNJucDLGLOLkrS1lwyUQ+/ZiG3KRh/HoNqkbJtzqmf0\nVoQpe+wq0rELO/Sh2n4iDBrpfJuGlFTT+Fcl/pobYf18yuzKWOK3PB368gGQEd5uSEHxyrJilH+5\nRjd+aGN98wbwHs0+CdzsV+F6N5G31FCbakbkwZSSff0V3VTp6t0mP4nhCDXzDpigMgc2dpDvxZLL\ng8ASBRP0UB38HQpkwNH6YeRKh1bBGJ1/K79284qJ7hMh2ktTGj1VheaSebz7Fjls7o3YkK2Dtx1k\ngO0wi9KmeCRJPfAXw4ua3ck3vd6iDRyHT/neCSb7fujVpGzAxjmN9bKB24a7Ht1m3y+ZYtLoGpWY\n+UrbrTrhN4UGVh0WB8V6W2VT3sm9qqVmTV8L2ek9BTYg0+nCN2scNqNrATeOFu3v66z4yBmNU7m6\nfl9fWHrGY4p9lL+lEp3xjHklPvYdIOXquohPvcf4AYN7JsdKv2+HAyhMFIeki2o/d2AtU5WxAmtI\njEofyNP7jH69ZSNa7xPCDqC3JifthCqy9BsJigXaYnNrXZuh+7GyHbAAP0H7q8gwluqQG24jAUWA\nBxLDCIAfPGV2wF2qukILqLZ5DUX191P8r/Iyvnv3eMKLG80ex+A/MPtd51QypdR3ccaxM6OeUErX\n2GNEswzpBPYMDpwsYcmJoyrXRD8jS1R/sFqqZW+wTK+LrVhGSMnOWbOyDG9GDJhseXbrycD0MLyA\nFHVq56WmCq4lrRyWNQLPrmMUZNjzAOeIlBAaf12hwNDizFH65hoadMIUh8gcA/y1ES8kOYwvkOPQ\nH7vA1keTQjKM981CHa30D6657/pk91YZb/f+uHl3GpauUxvkg2HUJNiIIkY4T5JuWyr4WB/nfHwi\nIQIg3L0psynemc6NeakDW8gYMdAxItshsoT7Bq7uOMxyH+5+1FRh5J+glC8iCuT1Ure+chniJsOS\neuHNFtTlRfyQjG0jJQ2q38aJ2f/jYlenRuwimth/ojY0Qq654XFO9csNhzWAcjWyY6Gfi6fK6NdQ\nMNe/YeGmxjxfV2SRDFms7feyEnyLjcRcM+o5BvIGSorTZoCkkv+JXItli6lKx7a8OZuF0EQ8igqb\nSMC9Q/Gv+QgnN8tjL7YnttyUvebWmjwAn7SbTmAq6ofCI1pgKHikr9Yeo03NNQVWeuVkinahK6zh\nIMuLiWMOr6uJIV9uGKAsgOxYvlnazg6OKPAwTLx3uaBmecK/ZPLGdO6qU4siaBMrXS79P/clqV7n\n15Duv5m+w2ff+ArXwv+6fMp0WaOUQljE+L/2QB/9jjYP/QcawFMIcc6mSQlNDXtjjA2XfDLhTy/Q\nbg/Bc2RmXP3qyCEP4l/SdZfK7Q2W/dqNMrsQBLldUefwckXX8kR6ZDb6pS0dnoM4lh7SpmgJBKFR\n2ha5dhq7OPl/ZxvCsCFDs7IE9S3eeoUr/oM2BPMpWbic52dIKJyHPvtE67mRGK52MTxm+6zRQ/ll\nOy5eEKNImADyS4U9rgxLWKSy6VEE3rlvJoZ98Bq1sYKv8VLH37WG/bKIAQIdiEnWK0fbQFE6Q0k6\nIupX/u3BUZAFKDRvXOdxtijFLW+KR3wj1Nrnooc/rZbYV0XUFJlTD7+YU4QZHPP6UirPJhDbnVju\nlbSIqZoigYdFiBu2KUhpGr94YPHkAA+fyYiRFVUoSAP70bqccLIgVcJYClmzp5aTFiODaiYx3epr\naNKV547YvErVjvX1jaQwKJsP1WqjAhR3xhdk02CQ24SmZoSiayEEaBgdP2LmCiYKPV8e4tZhgGsu\nBhvD5F3io7pgLRwTqzckFiommvGZD9+6Fs/LuxaseaQm3ueS3AWSJRx/4oIf7qOi4Gwq9JQl4p5A\n4UpxnsU6Ag/3vPH7676zw6PDfNnVQsJkSmF74/FaZPdxmAfVVKo1xLOp+pDE2nbyRrEi0aegCpet\ntCgPUNqLhkdBH0b4UYtc3Vyu/98qqPuZBBSKFNd6PhQuHihamE7M7+4EYb0OloBQGT2chFbi+A0R\ndnV9MvmO9cHCsiUsCpHOhOKUu228IwJsGVCo3+EPx3tLuPrycfsEkq8xOjLily3XIaDwRN1mBrS6\nBFZbip5HJ3JRSAlrbjYvdmAQPzw1QwH9EA5WYj7QDY+jEyVFYZu9fECSMicTf4KjM/b+nMaY1YEc\nZ0cOR2nrMCYVq2cjM5u2JbXrLuJ/8D6jkHpx5SzjoLW7ySJbRwr2jUOIhBfK2/Gya/UcIUI/12Sw\nkQdGa0GOUGyNHuAvozzJ1vCcXIZDhLM+i1Q04Gi3xU3cW5M+OGGscz1wSB2gzx/kxt0tOqFui/Bb\nKBrG9lQWOVvgjwGTAR8+JfnTYe72UnhhUpo5SMy6fORmKUs14oZGRcMKVG+lm4ILp0lFetAKAvgt\nERkwh5QkRNuwWW0SjXx1gSPgDGKrNkc2zewdRqs7MOePd64iTKIUix9778zHYzJm1cOP+r1frIUG\nYuen3r9C7CLN+X/oUUjXro1c6qbnre+nIGnAOhIOzaybDbF5C9t1KgfgNHiBM4tij9JLtNml6rtv\nvgGJxE11ISaZcQmFth91qjkK+NzvtW4TRWkP6nX9ebf4AUrA3MgT7jucGwZg3+IbhOwKQIuxj78R\nx0EIAVCwTNJf3DN7WME87frBdVNaKCfq0dML1ABlt49ciSq2hjONCmAz+dVj2C8QMF+T/9x1vbGD\ndL3QMM7SMaXwQ2dMAjJ08v5ldX/nyeW7VexkjByFDB0Gf+imAkujN4vG2/lWQX1cuvXeWawXlVUp\n2KYfAYC5D/HVzZVitswTmjlkq779ClABNSv0fGRVBa2Gaigz94SixO4vEGL7gxidzbCMtMoJWckg\nY9FYMbuHCbj8Ic0zJWtmuuttVuktJ5V4LPbKIVPvAm0y2I3v+ZyzlagNQ+Qqyj4B2ZjlbTDMLFPt\n9cHPQ3LxJCwiFS6PSers4g1LjZUsZzRq65uGOSqwaikvSXfJkeXrJR18J56tP22mv68Hsf7ivf/3\njRhQsKiom7+tHM/uLzHHnYu3ZGxcP1JuaBHFsR16pgZxds8VxgLD/J/4gcCgcE9EuU+YAWLX2dwz\nENVcKPVD28FAXfKJJvklo6V4pXiERtX39KqTnS0Qt/q4n4p/oVc6zu21rfsGZkrIOwtXFDy5mKTe\nGqSuoPh/g9G558Zy5Ecrt5xjvoYrXuunxeqI1SW8MkNWlR9RQtReG9qe+dGOIa0f/slqYYNBRbWi\nvBFcXl/gsxflgRHo41Xmaq4EYUUpz4/bWxSpp0VKbGR2L+Ns384Hi89g0a1QZ5exOF/cz1+93qGB\ngrTiarQVMO3Y1+NRfaJnU6kNIDv1aS34O5EVGDuz5zgUmobGk6scfZrn9OM+1aSLDARoS0Yl/+V7\ngZdnorUnvSw/v1wDBf5mpTFWlqS5VzepzZD050/T4W04quTNEkv4/zOJgsLX9sDLjN/VF2jD60Gk\nBzKiorrfFngFq/xi9m84o+X3qm06NRQNd2Lk7n+PdG+0MY5ECRLbNSJLvmvLdMYH9fdd60c+c6ss\nzLP/hyonAHEwKB3GhT7WHTb3J33Syw/oUApGupfrt4VuJz+mYngwQ1VKTkNYiYeA+zrWPmnURW9c\n8XP3BnbZFWmx7IMs2jM7Z55gLg/jdzECfI/xNu+aGfOBdBO5/qLvZAAExS9vL7l+hckZ5jPVids4\n8QzhVb/gN73IzdRYD4pQfSdfDgn9SI9pRUOzxqC1Gs3JGE4awxS9uImTvNuZ/P9mKsarT86+BlAd\nNbXBhlZEp3sOm45fqQ5EjX8BHn78HrBGpMvBqFl26iFL4E/imoRF1S6cgUkjwv8kxpCTEotQeKWb\nm1I0ufYVj6Xt3oHmA0CLSODBV++7EewNWj2JkhX2NjmiF9ZiQ3yySrQX5l1LLAtWVd+/oA+mvgPr\nl2Pu9Uu2BGeluQ5m5gU7DdsDbFrbPbGqyaWoPJ4+8n/gGqbKqyfI++Zx2tne6GPporaCq+FlPI0L\n81nabF6LAQlMNHYi8vSeFR7hnmQVUz0tPtEE2yF4Z2frogeVN5lB5qQh/I7Tp5sBYmrMdWt5Ie2z\np7OI1mXFDrCQxDZYogZRcXfdV+/roxHDbqAmCxt/QDaZK1J7Ef3LVfTuB/UojE1ZiEH6+m8jumC1\nHW011rttxH0UjdVf+osymxD0su/VLxj7/j5zB3ne2n8UMrGARp9h2KUJFIoHPMtiPEPyYE4Q3u5k\nJSXC2OBMGcZOJnMHiy2g2cGcdPYD9xQ/mawgPsQzNPjdpQGmvk5HDXFgipycl5zSHt0T4kef4Msc\nTn5RBoT5ADTHVgDrrYMzkOn0KnkCk6dSPR5TSVi9Q3qSnboXvDJqnJfhspqX8juO7f2d917Xq3mL\n4Pv6EaOhNnkCjlQItzD+TdHhWBsZhYX89oGzdinNCMAPXJtHKR8Vo+p+vp0SawLJA71HmoH2/z21\n54PWaqecT+n4iYUYCMmNu9IOsY/YZO/RZmM7abkwkzL1pRJqbjeOxCYU65FrqR60DCT0v68JMmSi\nmmaMUKSRSWLKljAvemtDaAX/fXO2pklODSzYU7XwMyO5x34JBa97+dnuUsKgCBIUt7itgNv+XAKn\nhP0N4vqgTF72CVudOKtHmXbnPmKLOzKJw3aV66r39GcK75S1FcFc26NC9qaJZFjgBOBtCrXxHki5\nJvUtGLQOz9bLm1xAU+CY9o8d8D9yjcyB3h1rLgJrAeQ+f0wzZOvpHWkT698HuF6GNihFbzBqOVwz\n7GUuFuGZS6XZ7r3CpYUnKSR0T4wVoRQfpDqxHqfkSS82v0a8EqzIxLrea9Z3BT3K9XMIZQlJilxK\n+7uY6NkJRL8TGD58aUffQW++F2vmpYBAw/n3YSHD9R0t6qaADZ0sWQoyCdcHbWiDAzBR0OfoQGsc\ny3VpctlVjFclcRo7JC/6hhzXseb4fCh7dXXkvuSuaw2eJ6rVL6Bbug3ytYlSC4GI17owANz1blRT\n5XKn6FtuL6k/qiB0vsgYEpSrOZwQKrpPj30Dl5gvIMiiFSpv5QKPe9Bv6fD/Rj68NKoPMLQoSY+x\nV8gzj4IV7rokYxU1ovRpauY14jT74Hu+bhpVyGxMU6jnxzNY6dYXAx6gf6sjW3bT3K6SDsn3ENYo\ngToj5WvAGhkeXC3mzN/nrqfTK5WZSPk2yHQ6eD8BLcAyIbx2g6G6SFxXFr19FOgMU7ds7XB9bDx2\nU/lwvYTEOJbmFG4W6TnkjiZdDSYyHxjRRnzDTluVAttsepO2q+OqUMeViogrRTnEIlBP0cUlWDPh\nrJJutybE0A6OWXlyNuE+eWAbdbVwKqp49iEKDEC29Tl0s9z7Xu3j7SSt/4oQrv5qLG9Bp5POHhdm\nJJzqb9kVIXAm9yrSqrqb9DzFoblW56t8eJZWay3ONMfm+7XnAMgdDOi1ghEdnUmx+aiSDzd60SqC\nqWOACIpIQEJJAnwcj1cLdD94oBdkRLhOqPBvqjJPASJDxNFhAeSv6M4o07FTRWz1ITS9A1PTHdM4\nXAUnv/o/ZJKC3vmhvox8GP1UeIPrkSvgo7eDtRyLJfj4qbj6F4XLKmpYFI2lmOgqg1PwnnC1nlgD\n6As33MEctBF9LiYo9B6kRFBVuS5MkN9Q/vwBmCHRXLGyUzufOJh5oVwvYUm1BCLWOOgTYC0a+1iD\nxKKzpyf5qRDEL/9wRZfELBE6+Z6iJ/oKxCG/GhWF3hdHHWhoOSIOMX4fhPrG4ws3CKbgHkILJQ74\nsPw/XIxlO3P0Izfa2nN+joNz3Kn4tM+ZrkVSSCDgNIAoZ+ib+COhwyry1BJsL+7GWXTOncGo4bAi\nU2qlImnffdyxm3rqLu88hGqaPV2VIKoRbZMCybvmKzlVKg2ZB3PC28RtcOD4bekpDXeCiVR0HURi\n03V46k9BCXJtdpgBQHbYKPK+Qd80RwBRpdHlu0Br22iyKeDg+a7g0+Am0U9scUDYfAw76W8Gfrjh\nRI0AGW/XUk+WFrHDo1GjkNwtCh5gn16JCQ4743jvnGhGfsmE27eW73tlurjKpRjX6FERC73bWq6J\nu5GwICeB1DoPuxm8GKzH+Xypunq54mj2HzUAeiLwQHVULkuqDgvJPeTSE9WoMf6oOnksTB+l6P+W\npSjiChREofmSQbbes5/Q5K5paWhG6nRyPw9yeDozMuXLgLuptDCkOjGTiX3viIZ8KFILFz1vDcCa\nL5uFRub60sU/Gn39pkQF7HLU46Wn7YbYKIww8GF1S57+eUOodDssC8GgWdKalTGbJTIcF64pa7HW\nlcUWjkOGrvIi+sALQHz9iPDFB3isLJMBNJt3cV6e765s5vBrKJiNOFDWxN8yZFk3g7cZ88VSj43z\nQYw8gK9B/Iu+Oeu7zNjTlWxv6dNmhrVmfmOuOtJgi+n+hrDedrOdveZT/oizJf4N729TwvUPADc5\nc0+2H5vE8ja/mbKgX96/oPoiRqOcr7xcYaLuNYVRdmfHPducVL9XtzeQnMFL6pCVeJxLc4Dtot4N\nx8+IBai8l4kdsJ4FcLY5CBr0tSCRcM0nl3x+BWkIN/cBNBnRobFsWccpzEOnxtGBSbuq5e84IkjK\nmgkeS9OBRw4YfDoyYlBRhf/M6tR0ldxPCo7OBEskKQcWHOe3EfnZzoTeBlegSP0MaMxmYnnP2xlV\nob6ggFZJBLxt8wfyJJ/at9wKadvh1F2Uz+Ac74m9t3jfqxKI/tsDfu/HeF7FX0jmRQG88ko3ICKh\n4CLzlh9Wg3Mf/byyNrV85cmj+XQvKJWZ/JtZJ6kmMHzXiwVheQ/LvlyAvDzIepqsQgryKHv+FYao\nfQcaOGHilrDN6jkIYl/bEjk3LnVR8tu6FwX6p1T7leIckG3VsyxqoptkbuNNaUlicNnvOWt74AvL\naKdbCOfFj4ZtTwHWxktfnw/ZOAivN1k1vhYTMvbrfKSF74EeFvlByaVdG7tqj816Y+88dsa1XXBZ\nBW3Df/Q0GvlE+Zi94Lzy8ufj9NXizrpMlpnFS/0IMIavASGyGoPIp+pbRvxU5gbzVVC5+AYk0oAq\nl4Bfiy8IG0aWCVMuEjHexA++rU3zNa1Esu6V6woAlrsRvO4vMryuxOjG09wB7SXsWTL2lHQzSf45\n1nZ+ZrIunugw74MXEvHgMihqWPJU0EUGlsOkCZBcvB94Rf8Pl1Zx9rBqXj4Ft6rfC5zpts2sDp+H\nA08wHW5WRLmPj322gEKR4G3/s0mi4A64nXimuH2ud5Vhkj5D7nauRIw2jUcZPhhV12VqLfRcN5sI\nx8WZuaQGIs2pzoVmyFE6dIJGmcvSvlPcaZfvQxqT7Zz9eDLUNY7rvQZJjCbW8RcJPR7WtqKro/iw\nWYk3DHF3eiVdWI4Kd2vvP3Ym9wgyNEZxTNDiEqqqXaSYBZyjkg8R1agvnYA4vHDbTlhJOW/9NSlr\nFA9nVJO4kT7rFcn2bJQW9fgK3Xv5D0rSe/HmiYWjKnnbQgxve9yeTEB7Tcwkzvk/leI4xcK+sZzh\nGsEZVKyze4ZWTmcQAj7REeB/qQaxGfXSpVZdnIX/vHnpKy0jEQM/KXL6eChYKboNl5INoOg8NLF+\ne8BaknmYNrcORt3mgs9Fi8ga7oajiwKqqiUcmPa2YlaMPQFFS8LpyqrBEFkCwaZrXTsWH6HSdpmt\nLmEOxeQA8zuLi3axuxlu6BoDYkRQ4At0Mwq1ek8dbeKO0+UedJWcXwvyGJ7SJNC4d6gvPy1HpJgW\nQvf+3xVtUw9YgL1ZOp2UPd0IRK26muoe7nI6U5iOq2eEiFEjt1ju0VydaMsvNgG9jDHvniaYki4E\nU4J2oey0L38uheI/CusgpEtaNlL9x+xsvd6fg+kcZ1UOjPx0uUCI71IJKV+2ooifTZPpanOQXoHg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rj8EAqkEeJBFWW8PmniVo7yJFt9kJOQQVt1aJ45bMTJcB1/u4X+QqHWvv/jtWo5FJdoq/w\njdbrsv6F8TGosfCl1BVzmtZT2pmrhfAkvGQeUZDinFuHa87HJ32MEQ8vZnGYDylf8htRIq4WvGtv\n5vfzbBIQjkKGjxGY3TwDfRM9bMKiVP87RwEKVyTs5pfGiyefvGvzswOt91IzhmBu3wwQZ0lzLzxQ\nAP9+I5GQklKujdITCEz4XMEq2sESeCL2P5FyDzYfPe+ugP/kTP34WYHxZcyGOlThzJ5ix3Se5GuJ\n5K2WVSkkMMaCsTBt4RUB9n6Qt3PgB5whnwPES+sPzAdtBKccs0DEoAFuCO5JRSBcfQa8nzEgQvjY\nhCk0TWgNSKvPPUG5zAmLBHIz8Btet5dT8y1CAg6TPiqOK0Q5YrWdSfmpwkFDf9LW7z3CJrDeYjuX\nO0gyPxZzks1YtX93/qpna52Pis7gks+bsLwkInNRema4s2winmCI2ieJUrTXx2J7dVmoUC/Mntgr\nZaHAUDClRfMtdJmtlV8Xk55wNS88QUknJP4nLp5G4ezd3TNrmrNLQ80ldu66uaes6cFWrBIrdvKI\nJZ+/t8+lnRp0kDkAKX3Q6etArG1F991w0BpOGbBs641WFmaMWdyi9Z968bHDZhiA1W5a83sliMAA\nWKwnMolUsS7ZO1QJqeC103U5Z52vEa2Kr7Cbj59YeqzdPvYsmJqsgpNSgrwJc70w+UbT4O3DxgwO\nE0RSDchJ/C7CR/ia1xaxG0LomftXna/dYb2OiEkqTY/cIXiQG4oY3DwavlWwWmKzdxnh4wJ/I+7c\niZ4qgV2Nw1DlKtlof+BnjU5iI0kn6VyDO0X4udjhDPc/fx9UE+r4RsedaWdOo/kz45A0aqeVHuTX\n0GqxbhGM6h2QeUAR20CF4hNXS+28uwrRl+AzTEyQJi3JrFChOH8l/SEC8DE1OaPuGjr/9dcleTQm\nXL7o8GtSiMnJGq1z0kk7vREVF4IE2ChOPO/5dC0lFPvxbUmVuidkU4yIeZTtJPVj3GVtOhrfAaDI\nMU7sldyWMEhOxEqwqwvZQJAxepT1kLSaeCAJCCR48pqTE18/CbUJb0yzolbrFWurfEY+vVTgl6s7\nlBNVEF6j1n8wrq7nxHpbzyJGvaMhzh6woRn4P4wSR6MVNHU7vRKEQBr+zZ5Rd4xCwUew0EEv+a3v\nbezk8obD1Zn88Ybn0IjC23+mR8uaq/QSsV7GNimEQ8epOMxKjHdYKePzWX8wBUrNCC5iQhxWd2rI\nyPw2v1qLo09t4fldJmGmYwDX5ZiPpqcU9XU2Vb6Tt3g67FtJ/oefboq0IXOkfyXQb/gDdfq3RwDE\npVU4VxHdT+RCKZqmKErXo7pw102/St8ShZRN/cBrg3KgBjBfeXq7JewWTP3eAYPBQUUAhCypqUGP\nk9E+F1/xCRNHHntq01F2c8aj4WGXHLV6b6A5KtKDjfBUAefjRvJqioPaLgtVaDUk8Gwj0ZcPdVN9\nsdl2GAfK/Xtr2hnLLDzPdPJa5kQxjOTWLPVsWdmFmCnd5/vUkkYEADGuDpE/hewguNU5gesowiac\nGa9Uv7hQuMELTASgH33Wx1D2s/ypyC3FmoPHiZOKkFqFHFjTTwGWfIyO24wAbDXqqh3L1vgWSl11\nnUZGK2eX6Vm/V0FMhLSdkm4sdZjTZsGtP9+Aul5OJWM82dgTrG923LBYLuQtiA9TJKdk0my4Pd1i\ny3U76rGQf8WxgfzofFvKT6Pa1Istln9FkeeiUDh+T0U8qAY8KI31Ecrb2WMa8nPaOfUBbGebKVFf\nVTGpLSEOIQi0G762sE62gjZPgHqxgCBLz6tIkLsx+oaygBEws18+HT6dHZiywYi9HoVYdde0EaQT\neWw/34zQMznSEWcJbIlap++IjJwok7IqKkaJryYIx86V85Wx8RlxYSTN9SlAuhWgwF5nMdk04iDO\n8fWtqXhTAesqNLLlgHzGsWeSJHjOceuhNi2ze8AOTmfbtTL5tFiwUCcM7xppEiyNMOu20BayT2q+\n9nminET2ZK6btQiSZnf1GQ11lFne2gw5vCQh5An3VjdhA3L4XbnD5Kri7ZgrvO5hhvQtYIEmIPs6\n96PUK+BlFtaSUOdPaDYJE5rz1ofiZQ3aFooAyEqyIEQag22Bvj9qyyONKW5efsKrG+36uAfWpWZW\nPIUzxRZMvjFNF7/4YdUsld4rESJ/b8KMyHq7Weo4aQ7NDedwQmYveiYCdBNy1Xxoy/HuI6WJUylI\n4utGqHj0ZeTRZ0O2jP+ZJj3ZUc7M3fx6MZL0AQo0bLriIGK+i5vJRFsVlQJs+40mbHC8DddIsg+H\npUKrjPa8xveuOuZO09cc1uyylQCs+9gF0W8JZWi0dBWyWm6iT0UHY4rduyb+IGYScgEtl5xQeNxb\nhk+e/E2UdKdscol1N+GCcmLufLiQxRWKHAt01K9vTl+TuA3LqAI8ZVFQaPj0SAoDApL24MpQqPoK\nFdW7tLYST1zKN7dbUGZtzTjzJkalLWWN2acrKuRNUVbeF9GDs8+Dw6f/u/mhf8MEpCA0jUQHypIO\nm4oZAxyamzrLwyvXGfYyFIDRj5u8XekdeDyez2whtEXWDAh4OQBOI1WDPdKoit4MuNoRBDv2CGVV\nSk87v6S68x7qpqSUxuCeLRAjfWX0RFaP+0HK+2lmEwRGPtNxBgVOmGX7JX5W7Akg0lVJk7cbfKcd\nYSGqwlW7khSY7Dq8MpLnl0NS4W4mqHOyqeer1DmfhgmvwBOteJa8j/UO3U1JwTX8uMg7AEFZfbLG\n92T5kExeUq3Sr7pVh6q0rj/2Gduv/n8yrbr8+cT0KYGWExu5BJKrSeYt6IeJXVJWpniCWmmXS+dE\niVo/zP2nRf79yDTjHLOORkj7gY6rISO+7kX5JnwQjhJyPyKy3kIytZcREPnGH8qqv1ikgZ2dv9ZA\nLLNA4CumNp7jQjDz/gJre/lrMRgl+ZnuKVJueqRhiP8GmeUvYP0nLy30HRCrw4EOm0pM/nW12QmJ\n9uF5A3VMXFXHWygJvmqL491Qh8DA8+RdAGk5OSqkykg4M9mq94vMXmw/qXsqwOQ++8utB0XWYRe1\nxlK6c2nbtKhbR3UFEN6ORIPHrFSJVs6SUIxDyb0DtIfsJU51OujRpBIP+F5it01ZQpSAcJA46MKL\nkZT7HFAGDW6RuBsxge4NRW3pMXPjOZYPlRKLC9MOumCYkMIzqQN+6kxzD8C1N/BmXmsddBjnsFxh\nV9F/90zg3o7/rIiaU4YwfkkrX95aGTgboYQr52b1J9w7ogNNDZ1ng6cSNo8KnlDr6pc/ALJA1CIY\nMb9u0AWOleV5bsb1z6wrpV7spCdyr+dZhnwnEd4rv86+1GTobSkZmL/dMWm0OagABAGxI9MOVPlw\nfT7PCuhaTOu/SI6wgKTfR7woi9JhCa/hq4Kuk9eDqOVD50KZA5IITvZuhKtxHpTHUsfbOfuDSJO+\nMPRIMTTWprxH+iqQGTmA8L4kkui39BSue74rhfAEeFw+wDqKvQMEzSlOttXZtiehOGHjrLRdluyw\n/TS9KfJqlQEdDQZE7V6YpspyESk8pSeVfth/ghiaTNya99OKww69Mgi8gijKUMmLmYyaLUU7GX8S\nZGrOx0+CI94icT99lZMeA+H8eECevDQe4Q48/QEcoGAZtjR1jUODpXPVzORs4CDUn6+DrglFVX2w\nbGQ6XLPh1veO6idNkDKWV9zaGzDbSq95Bn7MhVU2qy/gHlFK/pHtHUqUh4iJDF+MImPa66WY2wI0\nehC5G8tBvY7AxkIM0qVaChkaY9L24kKHeK9V1/obYggfyknZSOF4areH2KWDKFK/lH9d0N11wJ0u\nkFXfNXS48lxmmk5YtzkNzuyIIDVONyFHDW/kqZCL88OUMZANoLonnD6cgrFxhhq8X1e8dJV7+S7x\n0ipchce7JxAt6b5MLhjmUBu9WfE3QRU2zFeYRTI6EhyDBn+ZLVosHeoEeVvxGGw59N0h4h+bfp+9\n8RIzJsE+/1tOYNq7or60Qee1y6bOD2PHs4XP+RLBLBSXV4Lngbo3tiXCZetYYSLNjknONi27M3fc\nvI6qNpqUSxYKBjmqnBk4kKagCdxj3c96t4lQ02+uh1pdTlfgRL1b2r18RGlafhFJkq1Xvo+K2b4B\n0uivVAoEsugHgqr3xgTS+sWq2utmdCTpn+wSYVqBaLcI/SVQEH9tNCnRXxPLn5NmiCgV2xkRHQYA\nNZRHYZnFNWEnhmjNl+QHpp0lrpeoonQGmTK1KksTXrCraoYhY2tZSV3GYJlqbiM4Um4OS31Rr7Hh\ngdWQ4WKRzA/SDMdOxfDobCbEDdUkAI6GXbQ19A/EC2eNpYlX7Oqf8ieqs+UxIH8Qys9l/s63Q/h8\nzaiSRHi5lFl1ijGCV6/o0mgpd37kIfJCf5qZvzW3VA7aLs9f6i0gP8LN27ofSUVURVZED++YKEzJ\nKBCDEJM/yB+j7jknTRoVNn4Im0p2PZ42cgUKbLPZfuKvh0y0f7O36wCP3kvuAxQVX2L40G9yl7e0\naaO4jzFQcyTLM1GVm6qPyuftiTu4dw2orWRT4rS46yCiOTBvW3fB0YfHn9ycDJh8iGcYru6UHtK7\nFg0Jw96K4cIdDiNoRSgCeXTWjK4b2BzTBnb9h/dMbskod0VYmwEpsa0BRiiBH8hOrPYd4VBVKW0n\no01gKncq/X08DEvglLCf8paYA5nll1GzzOo8hl37hpEvVu9C39q2O4ETuaA2vqlsZnvxLj+RapzA\nFDK0EC/7hHLr5ZpDixTtD+/NABikNpfUievRnOht/co0PdchhMhJ3xzdrH0bO9L7euoH+6kieDnd\nJGgkJaHZSSGsVvDIk/LNdYrP7lynGx5DBJGjSrSPa8OIwabKgrtaYe5VpIA1M2Ux1wmwLEW0tqO3\nl87qcgGkd0cSoKNYVz83U1fMPjGnb66Gk3ZQ10d24rjSEYWWISYyZ/jpZ3j7+RVGkclj6vbq2Ho9\npS22YTliQlBJkKwmGNQixXcO6qzgkyWTukMkP+Qb7s/Iw/BDQkil1OGGRPFPA0rrIChhvNvyx6Y/\nOcaQAg9iJbVS5/bjN4wFsQHsuaNcwNDMQHKL1EufJNEVfWlQUipD663ATXceyHBS5HNqAGlgzFr6\nCRCgClezdpEMBGCKPIynAvgbKBaQVu24RtQh/0dVDiM8jkp96yYzUVINToCadGaDsC9Vj790VlNd\n++bJdy20tBdKU0r8ZH3/ggH9dnJSZsUYBjRX81ioqzTFxh7kTAqoOk3wTDS1KmaQyPGAyHay69rz\nTGej/VvOcrRmN5AP6YzZVksTiFW5Zq7mRlAXhgYAvXupceSpAhuGp6YBMhAootBR6zNcT9uYg5Hn\nXF0N0YMs168tGILRKtxLvpiiBPXtIT6DPX6e9HaWcfIolTfFp+BA0/NcFOrHAS+LrdHJDVF9gk98\nbjBMY8rN4A9LTZmlUtISvVVr4eGH85XXsdI709G/VDn1zWX8F0nlFkZY91Pu1gGf/ud8YjA5xxiu\n7YGV3KE5IdDNm4DgmDQ2KRGyfBEONQJE9y0p9MsftHxKHqSlsbRWM+T7YYb5Ip99jT2uCtDgs3up\nhcSqf4mpVl40MgwxLx6GDb7FBL6u6nkVacRj24hayDHE5Y8rsux0NENY8Xx85B9h+RaCElT9Q90g\nt58zRpGYVkvSZDrP+qQZxPxTwqdehJwv8NU0lzJtZbuE/IKGn5wHNCj+ZXY8sCT1FdqYT6ldzUYX\nm+u7nzKCQQyKeOBKDGqmrcX5BRhQvpRyFxaRrmULZed9zteQyrFBekKSMo4pis/CdHZLuk4RsZhI\naRWs0pLbO/MQID+UUTuTSQJiWNliYh39PGUDrtrE8buA7zTzDjDtfZ9x7PcipawkWzTHl4122Km8\n9HzymTnbXMoZmvyH/CcbW6qMHyQP+2oSaCp43e5IloNfFFWfAj/jQStGmbYTMzdFtpYgFx77J0OX\n5nO6B3fSZsWQ6y0ff3ML9OUpc7v6DsDMYr/2Vd2rxrfwuZLcf+VNS9w1h175oiJ0xjZT1UQJWjHc\n4xh8oe+1+4jQNc8V+rotQiXnr4rrJrVGJULwR130lg+QUh+EMxR573XW52pM6ceZYaCYP1c8vqZP\nOqDVx6PLTg4m+uLu1WAJMEG1zM5W6npkX4UD8h9IGYEA0TRzuV33mAeke5l9xlc6+kszzCf/1f+z\n1gsb7t8S6N7mN0HDIzqMNklXSlDPeTXhHHyA+Hsz9doyLmytS90XCYOs5ii9F6HoFJQjSrSBpMQ7\nCQhRZeMHp6Z03jDS1VYaA6oD4LpCtcmyicHKqyRaZf5S9B8VOiO3BFmlfKAY7583I397rbesoXZe\nv1KR1KKlT5Q9XH0DNlLn2IAQW+AQ8MdXZrylwzQKgMfl5Je3A1ZqbeCseDH69ZgWarCdZetPBgK2\n3/3tkajUGlJGea7YOGGMcEQju7EP/Fg7FRQXlHGFKT7OWkrhnPOZG7jpyVXBLNYAbKCMjk/F1EXd\nJqu0FoEc//LBvPUW11odZkAuXTvy7Q/zVxqgI+fsf+QtKryKoTRV8HKmr/vj2sH0mTFjo9IQV5JZ\n3tjpEpJ+wXbTDmd4gmEwTV+q8nlF4PZQSDLLLzQ3UV01GNS/vKbDbIYO6MnX87vsuMmcqMMp7ssj\n1Ep/vkUuxwWIibLVgmLjGcy+GEkFQyqIsN7QAbO1ACOjARrb68cTOEcvSVQ/cjHoBq5oqotu2Zuj\nEG7ter2NWuNBCkCZ9I3l1CMv2+UPCVtI5DNCqVYgHt1gTaO/KhWVju2PY4zWCWBDPDjdzgG+yuoY\ngIGNg08RFf5Dh/Lf3VnDRPB3cUyxuRI4Jqob1p8qIqJoClB7+E43WP8pZ4unXPxTgYaIDi4TN2aH\noUWINOXb7JZqALrNBwFXh6Hp10C9Rh0vBdIm6OSu2NRU2izl3MqcFn6Sz6thj8KlQ3ZEsuyVuz5h\nMSeccDBmhkFHszmncZXD+yU7+E1jyqSJ+jOp9WVfCaSX1RjjMFRVKEb3DOq/g3er5YBJwL32O58x\npoLDkYUuft1p4EAGjfYPsuTfWRDnTXTdMbZ9YkjU0AFAEjTSJrEldwuYHJG5jJKSiV6aMeeyZM4z\nR5z1cmDLYwdO+O5JalLQuaqGXUqzxgPXsDQedp5X+FmDZbl8ZeB/I/mT+Iq8IO3iNVEtmbS4yAVN\nVDN6O+xvlOGoaQ0LMCA7V+isjotw5BFgPk1ixwkSC3mR8T4JmlBKGtHfriVDNOZ3HfyL8QSIuYhc\nsYLEqNnMDRzhUNXNRC1PYTz8zpT3ajglvUrNE74Na09oQoyOGkVCspwOqnTzJa0NS5ZaR8Dd2m0h\nkdJnSayrdlA9+X0Hp8YPOrK9lx8b3d2wTtJCemBJ9RWLP3Su8WydsfyrNY+/eKoySTEtJtRFGGXI\npEH45GbHbzlTojUj3j9LdnxjZI4fzXW3/sxZjqRXpNdudJkFlejiVmd7xq4QsoUnVi5llBp3begr\nq+Vs1ltMbVS6oeqZJi5YPpbyI/bm6e9iZ9QFDZIr/ELU8RHCs56B7oroJC40Jv6s2GQGYSpffCKG\nCCTcR9aYCaFGK3VjMm5NPdVk1JpLqxNN+oRRU+FlbErheetfL7IwlzZmyYn+I4pN2WUg7yNWyHVK\n5xvMOydund/hcEAWF1oHXp5oUwYrY9BYpLUyDb2pajAMiqx5ZUwjwqtYOBqLXfjBjbRw96Kcn1Xq\nrG/LOzwCQ3URaAaP7Tn4Cd7lL73mPRTd4eRRiTbxsHSGSSXAhNmMRHNTcYM7dDKPRR43yPVeX49I\nBPF1G6ZiKMkYY5nIX3PUy+csx8yftxPZ3o20kUnSPtbN0SP9qN00Cf86eqCWO3qHj3Xlat3nHkxp\nBRsKtciHxV4i7hyiUICZ+EMLQ5SOtNumZP8Lr1iU07j6pV1qA4Jd0a5nX/1NpHIhFrgfSYGAyQu5\nTB6ZGiasGyEb86CoVSYmpyWf9YyERRm0Lbyf1njR4SK9EUmTgitj7AFzFmuWwA4wI9MY/QLPnCQv\nrpTtPxakpG7oXP2kDPHQ3Bnm/ZdbTR/f0FdKqLHRZGG5AFF+k43ekJGODgzCUodLpCTTqSdyTe8/\n2NR5UZuRbnuNuZQtL8LqUpWNLLyiDbRN20pH3Sac/kL5p41EckK1R2ayOQZEdhR/DLrDsCyH1f7t\nAwvPCenrmnzfewEzdwgg9kntc4d3tH5m2UnyK6D9u+vyCpzUvm+Wr9fP67RIev99gp6DWqrfx7jB\ngWAXEOd4qD6eTlZSl61wiacxR2f0c1FDC/XorTTCvvAphQjS1n7NQvK7YpLPBUw8rCLcsm2UuK0H\n3/W9UKeCzNPWptZxN1FsGSh6XHUPmhwCdW2Ny/ESYg43fLfNgDlSMf3Ea99pFn5GMAYI/A1s0jS0\nfU83X9ADrnsy/+jKPG+Mx+dn6QVWUx7RuR4hZd+a+AYkcvalQa8QMFOoec7vugI4alhnUY67kFzM\n8RDxTdNsRklOMUjtcy4nsvcQaAvmdfsKsp1zDPA0GyjU6+SvyqzNfny0MUMtyiqFiVRx1OQ2FNX6\nqzz0bdAd4lcCC5kEn5uhI470c+Q5+FlttVro4X57VxyCiOyHxIfdXYppk6gqF/VNPm64LicLS5ZX\nHWYCmK6uRJGZygnMglpf/ojlEGvYqGoLZJk07xzWrk2DUy7qEujNAy/7TQ+e72n38L/n7kd+gtXv\nEF1reiOUx2pk0N6RMwTTNQBPZeQHIovDiFZ/G8kzsZlTkOiGDjn4vX/qtj+WtA0FZ+O1khP+37ob\nwlt3BcGhyRQQkH/xnCk37tQA1rEpB8r5rugovoNuDSWH1wdMF+VAk8yfBhks9vD0wA8qtwUfR1zg\n7/HVnYYUCfiXpv13bbE+WBU6jhK2tOiIALQpVz9ep8EAqOJgMgVB9jIZakMgylYV16YpJQ3VN7qn\nxVo/60FIMf7ulNSDz2jRAJXrtJEe+xFg5jWvRnpBnKU08DfuenQ5GrhipjgK9K/jnvtCbItn1Tm6\nBkEIVnBX7mSAzA9VvWCiDK8woETYurf98OC0FGfRGEZbHmOT1rNkrKl4fDB7WBfur/P/SV29+DWh\nfHZ0bZLH+UQ6Diyv1V0+jKBm9g1qylNEUJaym8whGUTWnKydO6i3xoogMC8RTMzAC6IYuNCq5+Qd\nPtLxm1Z2IJSxXokt7ui2f3xuQejzj7EVt1EJNSa+eRLfeesYzr8MkjbPIEBUqFL5F0ShMHlmEY0k\nB0ElaTT0yVzLjmz6NbJJEadzGB+zPyeaKLGEn54w7sYWUeDK5/DBdR4vPCaCCQGZwGtgW3LGJ73E\nhJTyLrdQLONpMBpenzZEJhzft2/c4uDNGiaXaMYAuKDwX21LiZQMHMvpUClGg0fyrRLuyZXFkHls\nVg4nuOU568rBNZKR5bO5sXFhQoJFJLg2uN8eCLIey1ppJl4fSJGfgGqEiKRGe4i98oQ2NBHEnpPy\n9cFQ+U9dp1wp1v2BQvjNttH2I9wPL1j4PYHaUe56wdpcVgFCO1rV6jQ9D5NyVlGcQ9P3/Qiu6FCS\nAA2+3+470p4/d2nt8vQngLqPHiawMHnIqem0+kxDrMMJeC3x+jp7EJW6z9CEmlvhJY9ocCYIqq+g\n4q5iQH6I09YAeufSyc1x959eDBpRZNW5Q92gKCwNYrL6abPlFJwF7b7KONv0HC9cRs+xV/qkpv+j\nCL8xnNfXr7mSGQEfe+TuOcRz2IkeMsgl0hsC3szqt0Upl+aqdn+Xqn5l74hS+6Q36Pxo+d5lXucC\njU5VmcSDjRcqzeTbKeEverZAba8nWvjCIYsQ50xQXDbUFXip8yjvbwxw+KofYpAH7aoHTrcI67f1\nsjiCJL9jmtN8hebrNM7rsvB8lASjfpPCTbBI8IP9FlY1+gqpkaOGxbRfPWmi0s1c492Zp8QqNRab\nsvDXo0Aqi86ZnUCFHfVqUpc0Q+TIYJMzVcsnXGtTvZfskJBEXfiNPlyOvSX5rLYacDVYWv3YsPIO\nYNpSXr2Fp/5GgLACUUoeAw2d3ZwGBaEYvCHvs/8xln7npUJwVLc6H00rFO6JBGWV2rYim6PvZyrk\nbf6w6fddlmWnl4xgJXByPHLJWI2vrNvsxyxUUXdgDyu6q7TaM9/hdW4OtBI3OzqlTVzb/eJNMYk0\nTby2rhcyHc/jrGv9xXbvjLFjiw1TM6JKuXbobXeiEMnroXd5/hRgrQvirPQYKGrLgv2mApV0jQCm\nWvsD4GO+FqaTYmyblF3FgrCBGIeXTHwF9eau9Trvd30y1Xf7A6gX9kDj/PNozY0JSy8YXrc4lckq\nNH9cUQ6pf5rgg4LKKwwrrazEBUT2T52bsBFUDaSjqWzecB30Jr1HwKye77b2LxpOoACpRaW8DFPK\njBVoASpY+6+nstI1LZaHAMxKvJbHcfj+YDLL3iC6U1hjPX11SsyIe8fa4BG6Bjh7vMvGRT7riqF4\n7XTKujz2FMv/hG2vrZeqdhn0BblG9DvF7qtgj9JlePv5YCITu6GbeqKDfwINJVuoLeeeHGR1RRGO\nq+H4MA0X2I+AbMigP1CwhQA02w068Avpo8Mk5/hVdbnGYvF7HM5nKbpJgYeURYLFogpL42nPBawD\n+24XGgeDGjbNGCbSGKgnvwe0yrpBb9cQYu5vI+J+uigu38MR3QDQ6XxXW7eTu3Ph3gkS32CxxDY0\nZhKuodbnosJbLV+gppA6PewqhuQSPQIjqNYj7y+sze38a+nbgCA0vAzYkp3+NtCREOkeDMqIna6d\n2jxJpGQpfMhCDSveF54iiR7hNTzV7/1bWN20UEY7/pPip6FFtsU6D2gD/k0vYejbXyVGzMvV7lTB\nVZ/pDVp5EhPHmxcNF/tx3kRvPXqUz5c6+vqeDRaG3N5D5jPH1aEyT/TZcfU9asWlusxvLqn6XOL4\nWn3v5FZYOQ1j54bw1jL+mLDlUoqYJ1w93LwcXKT1d/6xfoJ+cWQ4EKj5DOcQVc/C4T5U+9K930EQ\ntCoaSJCGVwYTzFP9PdiX8Q2m8em2ceZx2YnrdhTewdJpy34UCFeM9Lse+3V0xkBqAB1t2eJ6vQAC\nCOPlicQhN+O4fF3KJcRQ0ZT/pYwnglLH9oWwwBFFxx72BhVI271IbugjDlyPgo5WlC4GWtvbKd4z\nGlqfdeSmIasPle8MH7WcM5wMTP+ekZocv4dGzyX7VQknGK6nSEqTeqOxoXDeHiVJEllM7K4ZxNSk\nOwGzHUl3e5QiG/QvXnFwiCmEwBT9r5tqi1zZRf9sTRm1hlSOnTsSFBakmUqV2Bc/mO227BHMfd58\nTsiJdSTY7lkEBvHuzDPhJqAWglhbqS3mX/b2714gkhxyhQ4C+4Z76t0zTVgisx0arfzlwQG/fiLJ\nF4pTPA7+YfitSQg8vJwa8J1d4xHIuBCfmO5BdEc7D1Vzhay5IOBQGM/LNRvtGa+VVrNz71BMa4pU\njZaTbChbRec6MPqhnbSbDZLgWdW4DE7WDglbzo+sqG5bE2MfP5CVCtrz3Oz41PkT/0UcNVGN0YWP\nECIdNh9lWIsbZ1VEScQUv+rlPHwddM+rs4NX4ve6dnTta3zmrn7tcMLOGXmHvGza2gOPziqVTS93\nLcNHdkwPAHfXyQuUFcFUX02Mx8dG/sM2D25AACjkJQpuBiJadh9pda4WxlsCrLimofzxW80cJ2aX\nU9XjwzGklNnIT/Wn/5r1HuJk37TrLSzeu80n3o79y3+HCjNbBsXrGPEQp7lMWwMOQv05hPKxdglR\nTo8gA7w7JMaRZgo1D0PnMtiuy2XkDuu1rk276vKAxR9EE5Efo9phpp0WwOrhA9rx3iBtvPeBiANU\nUDtt7LTshd6etOd0dWd00TwlzG8AJ4TpfMIBSCoY4M9Wk07VT6Rt6ZRQ1QEM/6lR4xDq3JVqYtnX\nwdo1I2g30jFpGnpWgw+6X/3wz3cldy6y+G0TZZrqa0j9G/UkuuNZsQv6lAhKjRKHCJCvAT8WyBDJ\nn1kvseEe/vk60baqdSKdXXQSrzLt8dsloOnrmsF8U/Vgs0fFnlmD5qwbaLi78Dw2rUdgBsFAISc0\nMilAQKItyVqVLp1mYY/JZXwS/T0WL1Rkf3EhnOz3OyNRc9ukXWxUY8avNOV8WSnBBbczOddbspVL\n/ddco2t1XLgSCiTlz7W2yXtMfcVs4MNIeuDCAYaIEDWL/2tVj3Qr5al/FLkQIwDSY4Sn0+ZF6rVG\nz453hCtaqFqF1cUdPQJXagQSit4oAxUGqATXvlOh11czu4VZcyj5tLN/URsEZKf+vpFcsBAxtCyu\nhFoYPBg2QQWnnpNltfa0b12LQln42nWR1ortQqYWsD0FimpyyCkQOwoisaA1iv5uvNCVKuntQeQg\njJOXGGYsHl4DDFm09mowpFd1yDCaMvtzwwJJPNI7EZc635sWvhu1+ykhy6CTJhx3nre8ajUdjvSc\nSUWqQOcX8GZk42Wr7iqDJLk560FoInzBpt6Fj+p2uBwxqb+BV8ZRftcSX++HgpFOWB9xvk5DIoGt\nWpzhDflGcRzMiCS1Ty2EepZxSmC2HUtfVdNgmBsETAbK5HEp+njdzZKWxWh6THouCVMMeNaMkS1M\n9zWluk4Ni18MR4rWpDfQkSSJuY/MDTctPgWfKRugx1jPWUi7A+vA+qugqdOw910DeYq1U8HvJ2Zj\nmghQYdwVlAP4FQxSY/QJjXT29R1UbUINQmK8ROgA6Cwc54puwxBLbSSjRT3+GKpJqgzTVjCQXnhs\nk+inbfSkw7mXaiowUVwt9MjeeQ0htKD1UVTyd4LQJmCuyqV9SIvDJV4O7Gu+WdDpOPObkQYp3/s8\noXu6L8HgucjKvBOtbOEm5WuuN6ZqsLHFEa/Jno+EQHgVAVYiREnjLbrb+LGBjukYKQujMUqOWt+P\n2YDkS+09jGvkuA5ZcRfRJ7Qe5yoh7wHj/W3/9Dghg3+23tbS3q28kR78rckmG8KAHtpICUrZoQxs\na89YkNwr4y/KIbK3+oINqbdaJ5aGpD8fsp/ZJkb53fTdS9muhWAz0cpoEO6oWGI0OJxERV3MfXpn\nFxT16eVZmsaBXukrzYsoa3Yr/YWL2MHA7aBtjOPHyP6y5379IdqbKM27lLW2qfDwXyyazAjWHUbs\n8PKNf4jvlTtZcyvHNlWj/LJXilFXIwNKsCFu8y9Dyn8EZ71uvMgJ8BfvWhmJwoU13QHLopCQ5oom\n+hacd1plA8xEjHogl3v5/m64tJYKpLf7O0/Ud2bOJfKzh2kxonua2c42tx8u0NphM6CFHerjTNjv\nRgQ07iFe0RUjZwwdKqQAdSPShdP2NbNjP/n1aMtfqgWPk2FCP4n6aTiaWodinQhrcYIQlUPsOAfS\n0IyAXkJ4qVf1/t/2bsGEznlWKd5EYTEDvT/fBWynPa+rknmaxxPgzqPRurJ8Cct/DxKuX++zaABm\nqmNiNIhP0dTQxuiPC7psfwht99darwuHTNSqbwiuIQnAnxlmsZthuAmTf7Qt+bxDEiGAQLzDYTGO\nSOWIHIHr6RdUEy+sg222IMW5ha0fH5GZQo4Z2krF/y6v4NV0p9hE5SJahv1XCU5+jZebCOXvTm2T\ndPSz9u686s0ClnRUD8v1rBt0LYE6JlbJAciRbyFNpVBnijc6QvEgogoeGnXOxU0UolAa7ec6N8CP\n1j30tjTO8aFS3bVqzJOdFw/9kr5nEidBsQ+0Y5DGe4dvL8DJB/quRz//Q8qa6MdlvilfdDxcjnyz\niVKoclgk1/FXptC9pBu6k1/+4LEjElNvOg7UHVEaq7LbmQMO05mDmBnt9xiqhG68LyAl0esyFT6U\nQfr7ykwYa4EaLbspzkPxlSf3G74jU2zogqj1O4G4fbxyNyIDoNMOEgwKcAUg6F7DA1vSSIKhnsxF\nkfrUUJaDEwoXhcjpO3teNslLNGIHOlrQU4Ajvzfr2bGPYa9DvbE3MjB2vombSfO32CwSr68tPR2X\nZ43xKk+WyQhz9hrP6bIz0LtsZivIHdPk1zzsbZ+vkVke533N0dwQEO2r+m5dutd0tE6qFwI4bJ/f\nBZ0yQ/dN5gekH8bvEbWWKxg13DwGNebR6ZPYG4klydqPgxARufJTdXpZI/fEOYceTEwEvwKwNt7M\nVrYgDT1ZnR119KEBMxxPcy49h1ksVCvA5aBIozaIXp4tOFujpWxT9tsTg97QA2JAj3RQ8HsdbvQ6\n4G1R56mPKoqstWZBuKSolVqLBS0EYndt716MwG71n/gKNueGXvohKEUxCoWNhh6zXh0yASjrVf1z\nAqyhznT6a/IxcMeZPIk6PgHuWmqKVGMzrQ9M6X78MGlFODFgNXJTUMX7k5VuqyVl+hOg008LKN//\nphYUQN8JIN1RtAtfRBbA0gisVG4kHRCHw66iP3FpOaCZ76SieEt7oOl4l+yYbf7/edqq95w6B4Be\nOSUJyt9lKtiI5M5F1m/Vb2z0aqo3PFVlFZIfs9Qom1MtF+WFav9SZRPeby5vxgEh0l4BM+M2nTp1\nfdDOcq24jSFunFMblx+ttx5sgsz6VUZ6+ebYCrYXiuu3xS0R4dK10na4F6trAm4JQnJdkQLnAsRW\nEbGmAlcmAb2XIwzWQwvjn9BxPSnH+kmj5c/EZeglyz/b0rgTlucEdbnfPYptqcgi4tEES8Sho0DO\ng5OTYNLv+2wI2iehogW+uByQXwQWZl5hkIScyls5EZU1O95PxDkx4hy1aHjKf2RNbbzrjEnQv5Xu\nccDO5hRTXqPfuPlTiuME1NlhgXwZB2Q7l/x8jxwuCkoctsq8sPtdtMxKPkZf14TUSiA80lgH2gLd\nycdvBtQK31Z8zUDjCoa0B26KFabKyVhIJcTG4gaui7hqGZQKj4S///GKHSyKFpIl+ZxPZY443bmv\neHLy3H7aeBXlUtb8aoGkMZz4t76UcUzTBW7uEtlS8evYrq5cW/Acv/jwknsAnN540iDzq8tVHR4s\nF5lL51wQfVzRDGOa6Hyb96Awi2B6dBssZg2GzLbrVt5NAL7SvTQbpN9DwS5cZuL+3E7oXu9NiAs6\nvxYpZCVvoXGSrLUFjsMQMTpZvut5vOUlxUVgf+mko3enwV6oGV/IDWxTU8AjXIbMJswji1mI/zoZ\nIZiLm3KWTCC09kfZKfqFuIVKW4vHt6vU5aZp7VDs6lrzLrm6krgiNqPjy1BeCQr3nUjt8ontDsSR\nIOb5YJ5QBT+6yYGEGQ7Q5fSLD41k5F/60xMXhTyqJsbFcrJ7sbXn/w9nBTQ9cvXO3lGTDfrAu6mA\n9i6N5ujZsKTynzAIrx/BcuCtyZ+yuHZjJ2QADf+9jJP0W2U1COSeWBTHWnPpZTxXNMZ8Zw4VTzDf\nr64UPC4gS5VtEr30GCv0gzDRpdyUrU1wQYn8GwtGr6DoIwNVwH9I8TFAC2/AX1RkqS1I2ngKci+Y\nvoCnQ8PJL1A1P3RQccpOMiTyxDykeknqs2kO9fmL1uRrEArWKBtrFEAdwv9Ws6EhTNns1SMa8KjE\n+7zGJVv4NoUjNpuLhuwJsgkdpr++zR3JiUnPcS9Z/fUpollACqYv+hQDzJn09zSOTCzelR4U2gjr\n7UryaPbzKsUYT4+L/7SuW6N/p3sTPFNlf0DASRdV9iVOMZNztEqD0Ef9YrNSIeSQTKfZeXj8goTd\n37A7gv2tdveQkZKLy9iX/rAEqmKnyQixuiBNXxvha3+Pkm9T2ZDGn/rk14nEjoyUOlOgOg4UP8Uk\nGgv1kHMzrT7YYEE6l59yptrFloHbtPN3EN1T/nK0E0Q9a6GRWYO25aDGEywg0RhJXPz/4DNZ7ydr\nzqZWVmVVkdN6fpXol6uZ4aGM49Cc7WqoF599CUwgro2Wmp1rsmORzVVx4L7RX8okTaMopgF8yvLy\nlXC2ha61eebHW/5agouDc3LjIDFbwhzsdWD4iVOPXJIEq6TsxunIpfQNpcUyfPLCbas0BdHtqgWs\nri12Q3IbLzwX/aSCPcxt0s7em4v0RW/xuCjnyNoSU4+vqFv1Jr5LEnoiZHGLeheJZKqNvjyLUb18\n/Ru+dogY9OOKXAMlNTTMEFcE+AlX95J2Qd/EocuYFqk5TliP38r9kuMWHEqSMsFGYY9/w6u8n8QS\n/N4pMlfDu2cq+7pDN/S09tNBzA/q7Pc6Sz3WwEU2vvtvkcbxal3ths3fXj/vtKZuiM9kHulOAdAo\n/V41FDCx5UeXAgMtPHgUCzIyFehAzwDDjxfd1bZsqWzB/Ash6au/ZUB4W33HtgSEjciJUTh/v3rT\nTeB05Db9cAsEepU3gkNNFopJQeBLgsOAycRF5eo4+sj6KPyhRSUnfiFwwTKaqcmM9hfl3PJxE41z\nn/V2x8j7bJc1DZGxiQ3+2fa0x9xsrUsec1lqe/3dSnAQ5Wrwk1+NCNNnBWhGaTtOVT/1fa619rpK\n9i3RZyFCITjZGO3KpzPRNSEAvkMBGT67fTekzZjgLyDQbV3e5HEfOeDdTTNjqCguBbzC9tMb+98y\nK0q/4+ASwOs3O98cbGmiCn7lMouvozN+nFdDzk6sBTXU8+VLhAPD2nObkwqKQzWORhC8F2jKI0Mu\nXcWxvhP2BR/mCLSN6iPRv21c4+hNWUO01xMg88Ie5YFOXlgNBkEhDeCGDmOTxYlj2ktpQOuuIY4P\nrlK9zGQ0RbI8Gr/rrAXQfAEM0GGSTXbR13PXgGinBhLK/bUNMU2mD9rQiFpu6yXA1/TCp8hqv5gp\n8zzpPw/FI4a5uOVqwaki8HcuFvc4bsfff9OwWw0AiddOnq5kTCh6WO2D1c52nXnrTsyb7VDmzDhq\n1V2mF6AH/hOEYKSiuPpkFD9vSjfGjWzw18LMKcuupoBo6pzxQEy1Dvu2RkRdEBqO4j/rfyetJPpM\nO+RZWmR5P4dnHRID9hTrzfobWahwBSvxl31R1ew/cqslyPhU3glYqGpIf5VLRLAqJyzzLe0A/8JH\noRYPtKrFi989P5CayrLipk2ABeRiiEuJeX8eTyaYbi8VrmiGcEsVA6cHgttkMTJDN05BEccnxceS\n1v9fuzf/uIxfqR+6vIbJJ9SRPvk4zFTFcRl5+UpU9WGTCPxF80P6vMSYXFOGMoaP+sUKr0ucbkh/\n5PXUSRZTPINAqYCXIkC8p/jWhx//5y+MbjJqzM/P1JqyCe8s17gy6Mlce5oBCvMdKdm4EBSeZi/B\nX2d3yVWCYNnCBXIcap9Oh45CcxjvIL0vjw8l5Kn0zmy8x33xZkHETedj/T2e6g51Sx5vA8y48XEl\nwntQ0HK+6yThmYtnl0WcYaDxEDhQ4wJbCq3xUoAmu869iwq1QuBy01Fd7VorSiQ2hn1K66Uom6z2\n0pTNNs80ioGwWKYENI87VAbBeytoRGh0uYyQOt6Mr3QYLvdbeJaRiF2nY+wOHQ5sg1ES/f9MGUD9\nrBd1Q6iUBWGAZsH9sLKpum8SF+3aOWzL/fc6khEefVqsxuj7AHfiTeDGbBv477GNMY3dBwpy1TvA\nUzhOsQAFUTz4a81ggdmd8zTjsLWOxIDo7YwNCWy0VciI01scu0rNy6KW9IlygLFATT+4ud8FA7Ev\nZBzOvEDi4Z84e36GfljZfTYokXGZXlTJc2ljhX6hv17srw9ndxdWv547py3LcZnDdtlunCTpGFSq\nCZn9LmwJPuksbU+NB8RZQROSShlWBXI1aYdungXNel6X1PZGQnkIyuo4CiwVxJcufOnLpn+wHd5E\n20W//ZA/cuoOnqTQHZI891OjZdOKy1drQIZ4WxNKmhLd9FZKtPAXuIRj8bJ83Jtcq5cpJrCSEJs1\nVjpSXywq3+3tiVCh1DI5MvGyXrrsZB7Dw4cpardcpQdyUi4sA5H/so5uvv+qxwiY0zQvKNZJRnRQ\nJCXyQhMh2i558El/tIzKdVaGeSwTaIy4ngiHuUWbUw1Vq9wPJUEBc+sK92Vh0I3NmDfbbt5qFVXj\n126A9XwHOCb15NNrATpWkeJ52cnZjWy0244tGzm9Io+3VK7fzfOR7k5bqRZd9nRP+xExUUsElkvi\nbz14b+E1P574Su+QvU1pZOnE9k4iJiOpNadrTqBirl1CCSWvkAzxJvCrNQC43IhbWnqen19YB1by\nm1+1xwlQI09cjkLTOPITxXMKrriTcPQsqXW4pAXgSaDlr89kyqlg5OUgE70BnUjXGxPSRw7Uqnrm\n0/V0/qbMJ4z/mmvGq9vA9QZCwIR7t18FJgZ4OQPR6moTvvUio5PkANj4aLo5MgvMzCOdy8ua3onx\nDYDVW27DO91F+PHXieuQqv/1wyvhdHdd/0WdBHNv/UtDTM7jfUkWUwRh5LmYiVUgb13sbyxIa/Un\nKlVMz86lZjHVwWJ5O/F8driZknxb/p83sYqMrjHzz6W7/NHuKZq+dybD5cD3+A8eJ0AfslCfDUoU\n8BmeMSW3CIvPEnWju182WVnbZVy97UQrSW7FtQ76I71qTSFy2vEM5DKeDit//xQ4fywwlG3kkZWF\nrejjwh3qlH440AmmSs2Ot9NrKvlp6uDq8QzlfTM/vHsuJESifLA4k5NHAlzil8tyiQFtwtPf0jnN\n2OzveJ8QRXMBLBGwhUbDm5q+Y+/rKzAji0/NCBOCAY7Pu7MPTkl1KroFIu+XheXSndQkiQQSHKf+\nAyMzK84q+i61QXbZDBG0xU6FloTxk+gt82nCsbfc28uDd9So8Dw+1OQB+OXviQpHsmAuZOZ3uGoU\nQ4LFs/7eQKkRhpsslSotQLhKMYYjQuGRbdl5EAD2uDssMn75r4FuDo9Kp9YdByzWq9au4XcdDMeg\nn8RDq/4QvhWFKEAftJLG1SBf4eK2Snp7Dt/G0CZxPBSKJIWh+YN6x5vydlaec/lymCdkoUs0RapA\nifF0RjrTPEd0acnf2tK0BCm3Xcbm00/6Ig7qwYScKP1frlbaEH3oqp5+JkaO8HxmNqY99zqL6V5l\noYCKZHF1o/Ob85LUwYLwWVvGUxRt3wPLYWXOhd63WJvrC2WVN82e2SQ/+lQ+ZHu8v24sdeTKPwFq\nGvzPvQQ53Ui41gWpdseKpp1g8pPEKBILjWFJd218pyRERipqYJHaIYAKUVB/+yQ+iGw91f//CJD2\nAp5D6tY0SUdCcCiOBvWo6aeTmIu4P8r1lCeAOudmXgDmXsweZ+vc7lLzQ+KwMAN1tPawfG4w46py\nN3FyoeGBEdHPHI4Jf7yCYKjQjg4UpDHx0J6yKNn5U2yQUoGEqB0DmJWUoEfxzFDGjNt5NpRFJ+z7\nvKt2uPPrrKgHXu0dn5Bo0kNcSgF7ZnwKdGQSw8zx6NgRCAgrwn+OrM394HSmmHr9EpQzkgBjwscA\n7Wka+hePHqdHbyCon3TyY+uF5TGFDXn+WfSqWJLpYkGukj9LxGFsgXFjWBlqp4L5TBBlArs0JTd7\ntZ1pkskvA3Lj75f6a1gYjkI+DhCZHKeOUq+s7tUaf5c40/XuW4p3o3XzE8kqD49+NWvTQS4uIvH3\nOgjMG/Ha5SC2/ATkC2B+yQCcQCxbCoF5aLhbwM9I0at/pr3f48XOZBRord+4u2W9atVcjHFMJvKP\nIBb5U9ujO4zyqIf29myGJ6HZ2UcBrPdo3VQqtaWy8A5WTSMTJBO8OPIdrPVzmdFs2JKX4xOjr/DF\n4tcFRKpsQjvYlmpKZhgYxwshT/GiuWsfvKLM9qfkHHbWcTIKxfPJR6876nmykqmNx23aCPl7nMrJ\nWB/beNnhs79m1jNqQWaWPojnZBX5RqZE51XtIUpbHLlPzUQ+hjEHfKVZSCe8slNny7n66F7H4C5v\nEj7sueRbKKQlDPT2vnuK3vRQvqa6E6isR+1U9wOaorktAqJ8kXwu7Jfk6cOilEbCegMvbb1C+OwS\nOex85MymMEtq2VapSz+6blpVjKzcu/aYfmYE3YQ3H7CDxTzjUxrLX6Z4yz3atcBfYCMosfu2yWK1\n+4j3QIssmfMK6KVDSCl6YAX13HJKas+Om3W/QEPpYMsTybhjBkhTiIpsfIH1B1g1OnqLcUsjnypj\n/DHAahjo+Dix536Rk3o7mQ3idaMyjE4LUgqRmT881sl5dLia2qfRQNdGHxusP2fu0JOslMmSVVTF\nCgMt8W+x0mJb6x0aircd5HZDaoUt+WyvHffdVsHU/Sbeiocham9/I7ZLR2aopVqjZpLlQboJ2Fl/\noe8ZxIBBLNofT7DSzeKdCldWMlM82VEEbtJm05Qj2OTALUvf82ZI62+ILlKtUjNB9FkXMjFVMcP0\ncRxvNshBYbESsO1TgBdVjELsaBz3pDG2U+6ZVSH7vm+k/RPlXyXtdnDjM7Lpf7oJcMri6MUVCEKu\n9aabPFo06yF4JHulguWWuYTdVH92ysVa2ONm6iCMOh1fG1hgNCASFY1Q6MP+mvFdUuCeObU12hXf\nQ8myCa/vx8bgIgm6IUM10KZw1nG/sN5KEyoPYNm8kh0t75E5nIXaUSXNpIr1NPLhW1h4xmKustH6\nrEjsKwY5lK6qHAEXoeHsdB9rjoPs9oiUM34XaZ3h0Kei9mEvW0NktW6VxOmQKga6LNZ32qKCz++l\nKqQ5/xci1VkFNvy3y7mb3jPNOuB+dMZb95LOO1oFPkPbwo4UZmj3grEa0yb4f3m/dDYXdiXAhT1j\n1YRhHlpm5/p1enFkIDgYnVYRrQwOqfrCm2HQFvr+M7FaR1FQV0s2hkt120jndGsrH+Ea4kyH6Sq9\nfvyAX3NnneN3uYnkwc7SE/aAca4bkkOewPE9vy4AhPW2b1oreppMy8C5wVEnARyiAG7GNRKtqYY/\niiTaQdjx5+h8orWWmgI0RNwNVJHw8bnJ6lbN8uzq/YZyoj+bKbWM9x8X++4SHZcWYfDNKbqniRR2\n8hPiwXfsRYKmJ3GcPanNDbQo8ZoRv9JicB1uAzBOmuwCUeVdSJ1ny+wwlmia07bE/HWR5Ke7TV9Z\nBhfx70JEzTRoWz0yp/maB38RKosGMmWcbhHh+goOnsrVS1dbKOA7SvoxhJmHoePntajcuYhCP/OX\nQpOOzDlJ52lNpgkBbNfJ7Flk9EdYxMpHttRmNGBn+HQFFBLoO4V746gNnVqHoyWyMIPQTlFIkpRC\nogjdFxWvYHWUv7wIWU2FCQgTpdtX5INykeM65TuNXOBwH8AerNK2qDKo2glcN0Sc0AmK3L6DRvtb\nA9Gj9hbON43l0oKfJNjiRfIrhXCrTY73+j7q4BewB+02sKzpx2Np+f1AaSe3qHrERsamJuS6e9NY\nYKuttwczeClS2TC+SvINJiUaDYB1IbwM4iu4GV8c6ZiL2GHhoFjrCmds2enkvYGdsC4fZRU0WV+Q\njkv3lmfwRoodkJbh57OEwcwcDoTbu0xHoeNDMaAE+1Rn1V1tGWZHbGtSvyMNV2OVX5Pwy3AFUEF3\nIhv9ohAz8yJKzTXjXYUpXLgzPpjQOBrrZ0HlWb5VROx/mkdTzWTPsXBsMDUbuOIt7ef0TgOi7Ccd\nEynFw9M9qACyFkaFafE0qycpAJoerC6YDqAgE0XnThIsLunUmjV8gNRzgaAzIKaD0eyzrRECdsnn\nTC2IyEOKwdcan3DxNde8umPrFzXdl1J7TZRPKFKDwpJ3rpt93aPfXmnmwXFkr0jeMjBtDWE14BFA\nEx2QLARcKKocreZZntfkAPVTHDEih7z/sQMkLo9d/EbF9dNI/KMOkAGWZF+5PSPoiVKKWe/tdEhN\nAClX7lntNNc9iNx2eIg/YSIn22zzuxL2MWXOoOHT91d8fY/qo3FXE31SiL+w/jrnWuovbGmt0R2K\nQYzRF2Uflztyoqgr7dvVJM/hy2j9pWldDhgIosw25+w4BpKdQxYNMU0LGJwRg4SVqN1Jdt62dGJC\nr/9ZjYen2yBstdQlq7XXyt7yimU7KQGu+h9bNmQ4dIJrbRtCcO+V8oBp0LYdDcv347GCEwPaKYkD\nd9dKhzJqQsyvFEdRxjwIYwC1o6HMWSL4i3lIFGktaoFHrmX1sYhN+UDPa3GzYCNoQWiLlUaIL0Ux\nf7yF1ludcRhGckjmO0pAjK1fsr/3RDQtiQntFHWNZqE7WpNWuVcLAi8+YvCNshxni4UW4eaygofi\n5nbzEeJgBTtLRPua9a0xCpVhHJr4A2PDoOzYbOYZgaD6oiEnaGJ4hCvJDV4vbctvpBr9/ujna9c3\n0PJ+yhW9arAPLupox02lH7DAWoU0wC6u/hR0M1VqFyQ9CUds0Sqm1cFWL49i3vMIkLKaaAMLLUJt\n3hXFObitdiCG0uPJ2zbeDjajfH5xbsImKVonQ56WjCB0tlcgX/lPuwFZ6xG+fgVCck371nFjusYz\nq/qn1vqi2Odtj/S0AKYzTgEDtOFw1SZIDKbOPwwEt4YqZkJEf17JOmcTU2eeFev6HNYoP8GOyigB\nThWTpFiDBcs4i8EIaymTu6GltP595gqrlUccr4yNEZxl65y0kGzq4OUCmp2O76n9BV0HUhsExvB9\nLrq9c/Wb7iAJorId9b1wj+iRw8QIvu5N2TH7zx9OBUpmWJmYhz8CPnXDM5An9NZ0xBMI9cJsSYvF\nSnfk3IcizmPO4xPLrb1rFAbG5gxLcLe8CU+SzLAWIp/YuLc7z7NGfWaktn24OMUpaRdZy9NTBVF4\n48r/zhgpM5MZmAA19kjchBVkN6twZ90223zvzKNtsHIs58LwMqcwVxHvblAMn9tHy134ETkJ5lHO\nbjSm+5KruSAs0VXgL6noG5MQUThN2AfNkmnbS/wkH+KPdG8JTO2O7gyfObWlSMIT5Lqlj3nMvzEm\nAyv10Jd+o9/lq0ivlL7E83rvubsaLEvxpQYdrjTVj3F7vSXbT0Fd5frYs4kD2gHK4n+AJ7YP51E1\nqTJmPHaVNprD7AIqxjJ+qnZDWwY2yIvQF0CBmKFBBX7x4zuZ0Z04fQXnqV3QfmRB98If0GKxJ0Ed\nuiGQRar9L5XWaY7tEQpdo3DpwrSKsSEuKiadhISLcXl6WmIRl0hW4Fn1wVUSAF3lyO9zsJ0gqOUa\nV27dGU5uMlCfP95BJSh+wUj6eYP1CgeZUO931bePuFFYqVb1dC6K2FoAsdgZfgHfz72P38ortK1S\nlLoSr2PjuoUXlfXTeYsRz6/j4doceLA6Y5fgoakA30EhMhpRvadhPmOe0b2tjmxuQ8PLpinymqUx\nFtD+fEWEHNamn85MycVh8MoYvt8WS2W0u8DJ6iUJLbUDfV9ieUWeu00UkLFwmd6akb9m0k2Eo1Fk\nXntNYQHddSsjCeGRldwvzgAjHEJuWyOY1WZbL4WCevt5eBR1jo7dnnH84UwGtJGsdY3yZ6cmp0ur\n4naMTa/Iuk2YyIcrSlR9EsAuEBGiatw+s4NVdBtK8W6eHytiiN4narF8s1QTMzwSpEbUSkFaKYbg\nAevBhsCFThTUIdEIUSY4X398azm6nvj+JnvjXSYQXmRgnbUn5CtB6QuQ+1zOBg8x9NHycyNT14PZ\ncK0EkznSBFOgzZ5rDedjUFwcVBZar4Vuz/HDJk1qtOpil/FktvMXtYP9Ny8GwCCnohAsdtj6J7tC\nKmFnjawuuJeC/p0QvfK382bHwFzp731IIUtLoVwea1JXAkFnO3xURnZnOe6U83bFDO4FCdFrzCkj\nUAVQSdCqtlMhKJBBiSY+gsMamZCqT8QuKM5mKmQo6BOz2Y++vLhiIy+F5X0jQeziBBaunE/8E1wW\nOY+FLUpCuWkpN8NUNWpN0FY8ly93I5D4QbRH2DCDjUkRtzN8CO6NERJ0hrbQarNyio99NX7dHGoI\nK130oktMyzfnj1WKp5cC4kg1zvHF4tRDPU0/Mz802ML3j1zNq2H6VhGxSwNOVGK8y4c3y7e1tS+f\nVwrY6vNMgPLXkfTj8b/yWapzkHODBWasyK5g07LW/Vas4aTVqZj3L1nFma75D64Aae6Z0S3Eisfb\n1ynUJx+LLrcjB0yAJTVX6HD0EI1D9Baig/JS7c5aI/uhZUb4RoyLMih6YUA4D2xu10Z9/86rSxWI\nW1lBMycQiDKjIRMzUh9G048OHciJate2dZPmhTuI/9J5ay36I8BQ23OyPmi28rooLYv8/UPjs9WQ\nUbIN5uQasYmlKoTteeWMyqN3CZ1GtY76OpYImOPibamdD0+qoUExeh/ruct00hpC/tYemxXKGzFJ\nMlsa4AxsFPESn8THLhYiwPFV43LnB3o8nt026DTqDi1reLtutmsQK8H+NKdbKjsQbsM0IUbMekV7\nqy3712GsgEPPdHwS7K9+Kk7WB4b0zoRwFA13+hXXBkt/BNlFqz24olY10OktsRaXimKoRL6Tiwiw\nMwbGgLXFxBA7d1KSFZD0BCJTZEELizDO2I3NKDCOxDkmsb+Vaz/aujJ97hlwLIop0qtjh4vdlWuc\nkAkxdNEFyj/UUJEuYgIQ7iXwPA94tPZa4HhkczRbP2pu8zD4aaxc8r3QXM1gtqFIbCpKl7dqx0B+\nWCnB2H8YArU8poLiOZcYJ7IBDD/JWX/O10xZZgd5P4WrGCDHejaiLevDJpyyP4ZIKcvqS4NvZOv7\nIPKxRtjR3nLNJjYW3Rnrej2Jt/veDuvGV5lTZ55t8fl1rBWhkhkdpErwVjLsIcd+EYGQ6L+lumzK\nCfQKTrrPQ11CspxxanVUgOirWzBZNxstCH673rdJQurroQ22ggFY8wU3PjrPiFFThVEAB2Tr3vDA\nRL+3qNKpvgqHFmJUiIrtuTjDhmqi2oBRIpGrG7zLDNMZadI6C3+6NNQHbXwyI2IXbSw3oeSzVuvk\na1T9h8RHY4uFqfwqUewyHIMt7MTiQUAYAoO5L6e/x5QCMUFd1hfJLjBDvk0nDzVXXPRaxM5jDjqZ\n2UalTNT4kO/AABdGCRcgiboGEmpyY8gjrGRvWPzBeYOCltf4zX5uBWaTz9PLPjARIaOGKNrz7svN\nvqF88WuFe3t/myWpXgRMO5RBBuj819F03S9hKQ6TfKQbY89RlAiLSmpQeZ4Kh4tWx61JviG9XkCY\nzzLtu26OIp1bp1aW7K3Lsw7hW382Q21nTUDRBYtE/pWHBigdvcePbMSIkFkNSrmAXppAznkE+Wpi\nk37H8XCQrbqXMv5jcp2d3njRghhdDh2kp3dZE9Nvk7XGd/NCTWke8vJlK1MeepldZdofPKe/lPCf\nYhCVUUFVCbT5W++7Ey7mkgoQUgayA8lULCkBDjVTwDr6iRk3Szv5mPm0g/TVtSELz+WWf9vBdH7D\neuVUu1Mv5ShezQu/kzEXVzQuVLSH9DSQfHV18ORji0J9I6kB+/17i4p3852V4yi33nu44VNigkOb\nlm7Ym2M8kx6xAXVEx9w0C3BPpkiyNRMQVYJ/0NVShcEiuDNb30lInjg9JHd4jztVNQNH7guWYLf/\noIkDs2lWNSdo023ZWXQ3q7U+gPOu+3mkwnPI7yxeuWvAooInMqZbQDfBuUTkcTbdYq9wa7kudtZ7\ndItVwqhGgr7wPRFN55uEspVv5RjHQUOhrRK/tSGe0Ou86wiQAD/vVyKp4pW6y3DCyPyCLvkFskpR\ngljtHU2gRCbJDZZnd94wVDdT7kh4sm0zy79jF6Z6X9mY+2d9/IZllVxuV444212EDZiQWVVSPn/5\nIXuRTOkQNjEsqeY7T8OsQCR05ylsI5zIGyttz7Dk9Q+bv9SBIdUoxw5D72k1kPwLW8rVMmc2hR/T\nXRVtwUIkHoynLDVAOFx2mfaiR452+CDqXnqHhxVK34myH8WFBlV7/w3YbLCxT5c4ZC2kMP8ta4Oy\niGoDc+voI5AljIMQupwHqJAQI+fXOsJM5ePrEv4kuxpIF9v5pmLP9xWrf038O0LueMps6HuwYihC\npg3uaWGj25IxBas+gzhTQyvtmyyl+aZxsKxgkhuJ7L3JIrMgIvxE2+dUZQIc6qH0EOPRr9pQqK0u\nhC5947m6XCKj5ARuYNdwwDaOwuOTh5M5l+3TpIDaf2aSJhwGbt9bx1AcRB3x2vsBQ7fj0r5wPaOD\n7st4yWIL3rve1TgOps1CAgBQfWPhkzCBi04ZLfOnvVO8WdUxTUFI6coVCe2J3vZvTZqMN+2WUh1b\nFZhSKNWfiV/RfOwf/+uzLhttb3+ENLrbKrfk6SQjyLHwQNfOJJK8x8mVoaJMbZJh4A1XaN1mDEiT\nj65pi9uJmlQHtT7a5X3nd6Crab7zYB1FDkc1AVW3DGYrUY7h6T2iXRuOX7UTcLVrhu7kfZ/GIT9k\nzHEkAATg+TSvzA8kqnbKS8nGTY7O26YaN3uqC8T/+4dXP3kYeSMto1UFOIsVrxf3OUrq1XhitaY9\nzF05xVB+SRcxlK3cwJjg7xQ1Avc4cR0EIB6XIoBHRI6/QnDo4hgmqgU3XbJ1ezFJ22E5miCOD4YG\nOdQBeSqeUb3uzm3bXpkyw+yPpXIfMfGekuGqWg8979Az+es+WMK9iv0KzcHWRDpw7r/kDV22yw2+\n1xbNA4YIHyCD2C+x1cV2nb1qCtVKRYciPa1VN/ff/tg96Q/FBoWzjQFvakaxd2ndgaqOLSypilFB\n5rEq/jIfYrsxXc5xH7ffkyaDZqyoF9QJTsZevxTB66FZiV+Wt6LTXQ+KxGzarn9IUbjv98fzdxd+\nvb2bVH2qNYqKL7BgoStgnasoe1icBiH8iHO8nI2lkClr4kqf6f6O0nvY0KzLSCBXCeJW4jhmQNLM\nziVoNJrn7x6AS6oZzyXTzeCTzoFO3BtBvgbIaDucr/rM/Qga4cBQkUgYbxY9IsgzApRo/OOWfh5I\nfPhHjWNAdhv7UGRCHtNkw6eCaOvbo2W1vP0vy/1blCTKj22SItao5n4U1oeXiGbFJESDu5VEom/q\nUtxAMxca7A5ASSZSlq3NR8TC39c4CVYCROuecW8W/9zKl4iNo6pd2PiFHeXKNIbzSEZcbJMDrr0/\nb3xOt5a5p8WY7m+g7XnYx5IUJadsg+JlsIb2YTmz0SGuk/8dnSv6W91IeoBMqKQZrhjEDxu7iii7\nl1WsrGqmpakSNy+83mok/QnbDO1682fw9OPVUUapFtoR9NJOF7jssxLt1D4jla0EpcHYItLRYrgE\nDBlSu1xugUr7/rr8H0gqpDWP5mZKYsT1UwwNMNH8m143qc9Z+spxta6lYaFZJ8Isstq+6H9c590j\nLzgZP6eALfFP9QjhJ1YShjBvXH1AjKL77uLQ42bhCPqaA2ihV4qfqvNsgjf0SHmLQgO69PTIK2W+\npKQlG1qlSak1j6A7nx1HZiNeZYn/XX0be3xT5ks77LGatKgxNKMaAJzY5sO6YnPSHPGeve04hFqO\n/tfZA38k3l9dpMZpD+oed/PiO6IboCNfpMgjT2YHmEJwNGVS6EPu/xPcgOa0Qdd34k9g9+4+XZvd\nqtPobtNYrLWWFtgwbRSB4qCQdGlsZY47z1599Ni/D0WZ6+nRi1n32+/UogGMJPFWMNVaG3/usnaf\nRim/3qaihPAbIgzeSWweFDO+3iw/IcCnltoaabZDU0qXeM0913VceKGzn2XzH5qnu5vUMAAB5tXW\nKxL7/162ghT1tpBrbGL3gqWPd/aXgwluUsyiFdbqk/rJcR58PTO1AdKxy0Gu49S7D5byn6mn3zf3\neRflMWaSiAuFG6XQ106DdX7ycXC0ZC4XfsUoMRLMfZ80vW8ccXFhtQwOydsWm8HAkT8RpAW9cBPj\nByY865Kbh3p02wB/cDScDSVvhn2+i48pWwavfoLw9G0o31AtnXQPkbqsAhJvujhu3WbOjjkhwVgv\nHgouzinl4XRGOuuNSE5Y5VEX22YjDwLHt9c0VEFbIfgr4POpIduX5jz16aLieVngYXU+f+YdMB0b\ncW8kh2SGezn2RTn3NlF/hdyQB1+W+AoBIYtC26P3fL8orTK9DMnFCrnrum709cHckeuOygq3DtZD\nhQQddQsUhwNmjU2VRYr8NWpwogd71hKAUn999lSlkZx8NFdVhm4QR0msBW5dufTmNsHWHv94UBF0\nJ7m6RLPiC9r9DuDwkb/8oJ4JOVEiSF+mNaCfYI7ylzr513vPzf2liAmTDVHwlU+V7eZr8RvX3HZY\nWmWIy8AvCYpASys8uJA2m+5Zn5EPl1f8Ip6nD8/4b1YREbS0YepYyjeMFEq78j/Eqy5r1aInatfQ\nHJv6N+SJ13ileMZmlbaE3BxGmqNfxXdDpeGPvAshfAWJlKyfmFfyzdsyJo4h6pcA/FuSkUE4KqJ0\nJFTxKe1NTm1h6qbTzUcLsjiLhzahhPIICQjJOraYlYzSkqbPrn4DqulCCRK/D7Zfc+XldWUxgn09\naa4KVX9p2glh4p2C+ZSv7T3PuMotinv8A+p6bx+XclTSc+Dz56gmN7s6EzPYGHbK/UdgewWSkbfE\nQgLsbYcm7mkr3pC6QfVXl331+zpu7vPmoXEf6l9RUuj1w4uVqHxhM+fhqwi5ZlPGPJX2KVENoCPO\nNY2hH/EGYzZ3cbi419jrPh805vSOODVL30IIAubF9Gzo9z+yqzo5RQF7zN1wwoNvFgBU60of7qZz\nmStPtOo4Do4uiwC0rpVFKiuzo99aDJDHXecgVlodbJKP7XaY6Z1MHYLZsb3iAoUd0V9gfHLYXH1Z\nhYLZbn7qiGL1n6t/0KqI+FF7MUkK6sPQbuQb9DBdMBSKOwXZ3Zkf2K5BIaUKR95zIPHOJzmHEoxH\nqblUOSRzHlMbu3kb4TMyos8BJvm9AsezQe5NPNgtyzKDufWzG2JLATajvmU4uSjMgIxZC2OS7D9H\nNPGzfotu/B68rN0jtkaYa/4Mz0qEXK8hOEHbEJFDYlOMqwmS8mV65t4SLGV04BQNJZnjfV9W9taq\nGwMuL5ok/5gdPBcKEUcnSp+Vtnk+YgH49Ux1LF7XY/I0RzO1ImakVrM7K65lsdY+tISXMypTmnTp\nGOW90iv0yM9fGsMZmFEoiE1fcN3WVQOwvx2nwpa4Uu0iIPm2BKx0VKG1TELUiRI35FSpw+Gmxs/d\nmbt7Jv4KEaPTWger3iaLPjV8l+hl9B18FnsGuQ/buCa1UrNH+mDTitVrzrNZZ/Y6teFjem5fFy/Z\nyo+q8orY1QaXfmVjJpaavRF1+REXEdlL5E27Kd+x3HtvU80esEZIM9cyamAsoMGfXFw2pA82OL6V\nHexam9CcuDYfTopVU4O6GvpviLCfFiAFZkcHPgaVNm9OjUtUD3BWsZKDMAZP5DJd5M4k/6awo7+f\nctGmx5dh/UeRABhUlUSY2pBcnLmYZljHuT1nN1DGU7co2VEnHqMqAFQRN9dF1F0yYDub2+W6pJxt\n2KiFjBO+g0G1zHLTfl3YSUvw84FeM7/gdBBkbuwsPqlqNi8cYi8d5nF11H67NwfxVH4S7YzllJMN\nQGfR9aQNN0SNz3DzTVLdLyz96Lnh52Nbwa9QcmOhL9GRWq6oj26KUO2sQYiiNMLXs0q7uw3vPZH8\nZHkdY5WHBFoZuShb+IqSilyVT5wrfZhAfZv826T4rerEOijurnFiKhj2RDpxbiS2Fqb9BEx6lVi8\nMTdHCjdevEXHXgaeTb4DGyWOOBNYPZDcbDVvviOkWcVBxEWQDWla6/YcKddP1wSDl4tW/nAkv/gR\n1EvDP/aMIx09lvTUZnsAfSuYqBKKW/TfCb98Ffluc56hd0h+MBhvoRfc4a/Q/ec4bgcwk7+EbLL2\nk9mpK3Q53SI/7lrBHyHV0Jw2WE/QskRW0GIhokd4GOKRnzVXzhcGFwOHRrHpdC4rKvORBHhh1Ir9\nRRLsLk3uxYwKskOuoiDDfWdFVdOrJZefSeFzov0bGEddViQ9hoqwRHH9RmnlYMATUrl3rG7qpLb9\nGMaZONYp6Sln6jMPRJ3kWFQhun5dQJ+dPyfMUmk9LQinGq+Cxqw1lTQ98YJqrDgNfl8Z0wMfaojO\nSSq/hhDtJRXtXBF8mB8e6W6mBoBnB65kln3RA/HqU4E4MvrrAPl7OCTN3MmPuctF6LKIAFwvR/YG\nlRZVkJDoGM9D4OHVv6zin2PIEOSINhT/ek9Ml78UTvlAaaOh1q9VBPddwS/dltm+EnVMOAUNuztX\nOmX/V8Lxw4obQz8NpiX3ZlpTCw3pHmEqgucvt8/6K2fH1IDGlZDlkF/MLoYgqtifQ14FtPQVpzRv\nd2y0WbGKJ5kXY8UhDw5wpjuE9C2FGhYYVlG1AZAYvpy6jl6Sc2nSkOzpMiXhm6qqSgS/g0N5I6oX\n/8pmsQAyX5SuYMOoAlq5S5roaafCTqOmEOXuzRXzb2E057zGKqd47yOs/z88Y8cvUWSlk2NO6zhM\nw3qBqjdNgmv9ZWbX7DtH46NfVmDVLqARoW/ApVbA82NcOAGLGmWYx2fWB1NYDfl/cRJTdzyz0ayM\niYqpQ+EuWvIW5x18op4Rr+xHBXEqnZ7cSHOt+10qphrG8r2gH/e68hXtwoROD8iDEdlGI9K8KSTH\nc5zbzQY5HNoGiy5QKyaUeGODQ2kN3bsEM3NdzJxF4XUmuSpUczLwN9HRli0VcF6vdx/+8nWHmp1B\n0o9K2E1+GQywqWmYSaT6sunSODczU4lmT1CbHK0DruU+53cB9mQgQw3wJGcERjIAWVML+z8XZv/d\nuJmazLf/3NUSBMGED5mIZXvxdEWlts1JathVUR/cXguFzSFp4VfFEb7S8Edpf2ZtXRgYEGk5hgnF\n80LkxGCt332Wx/ynlDLRXL2TjmT/t6damDCT+78cvVz8rxIJrCwVk47yaDEq/c+bbTQqRAvWe5q/\n8neBqOc779YJeuSmU3kOJrboz2une9Jol3mANOe2oiz6krxyUCJPYg6d3eUEptt2GIpnoOAEcvqZ\n2DXU2rRwRypxW1k6Tn8sElt+9CcdVugR9vck6yaRetYWe2RuaKWMCkY0wpWP2XQrYqemcLHEYZGT\n7hCs6E7B99j8pbV4QLet2n8CQIlPevSwaaz7cn0CUeMaFwvZb5ybSDD8dWIvAkrGTR+84YWUpyln\niqmnLWmnTT5oZc2Suiqkn7k33+EqJkBuNimeVrSTGxIeppj0ZhTz5ynJJU2hcphXRmtnVjalzH0p\nbHjLAMEf6i9Aa1Pu0dagd6O16V2ZZu8mdWXUPg4Zz7Qmlz9tLj9eA+4sv+VW+3eDcQa5+e+1kCSl\nWlx58GpQ3NSno1jFJe72xrpwKGev+q98IbuTWKzz3wztnWZTaQpTPcgtJzNEndu+23E/MtW9qxUJ\nQwQJSa7mQMgh9ZNQkvu4hNR3V35bTBS5J2cffTC3yfPY1BK+RA6hZ/ihu5qHNMrMCf9UwAkXyQnR\nVgUV5/NU+kBriY5KUj1O6kDBclZRqGaZNuoPc2nhjElvYqIZngkzqq97sLdEmQ5uaDAieBxmykzT\nmH6FndB9FauSF0C2ZcVbizIYWZI+PeXfAbOvufXfkAM68aBovlxH3oZjqqYWL7zevi7NteF+j8Uc\nFFJXV6XoEP2wI/mLVR95q7rI4tvaP0PoPUpVKzYZMg35n2yGDMvm/eEkzwc6GRnRa84BXWv+CRmO\nedD+LxtCWwkT5F543OZLwmbfe2HUfDoSphtg4QKufOWrIBHP3uzwHSQU+cY9duFdaqft3fg3tTsa\nhEsCC8MNnymvcKhx3ITxBQHjGUreGbJcFOCaY/prXxukKTS7N06gULiE8f1y4IxvzBYt5VcYo0ZY\n+wcOzjUUXz4r1jBib+CX6eQiz3WXT+8BUWFQhC68yFDStkhNm7WdzARsT4SJ7EnSVlWrpDO09e2q\n1uSOjEnUFjeuQIEKKZ31zIKwMvptb71AY1qQIhAp+6+BBwKyiMTNDWeNDqa81MO1spfj1JYaECpp\nhpmFfZOmlQdh7xeLQbL5VvPwqQIfmKhHyqgjlx9ipjzUjHn+bThP6d0iqmAMB17G8O2bcsyc/vLJ\nwJNYGXYp0CThAsT0InFpvRZ3EwIOnHqTtxSwaVbx0pqZgKUwO+1mR2JeNKAphHWnbvpVLhYyACwQ\nSBxjeKu61tvTV3Ost0+yuhxtw/Rf8e/329oNJtILp3c8vt4/KPQwy8LBT2ZKnkOgW9DCwP6CoYb0\nBAmrFh2/H2Sml7iOUVXiUnabq8rHWx4gbKA8NaySI+ZqB5lu4WG//09Z2GUl8U9MyHT/WFr0U5Et\nVuhHANw+kmBSWXj+FXbgeHVc8bynlH8xAUCToEe2SqKaXUgm63Xg8KImVs707JBl4Ph4KwkJbhyh\niy4i7m3dOy5CbDNYSBi4UAkJSjfkrX6y8NeuSmXPl7s1+L8cat+nV3GgeDp0s/SUbE4LQWhN8Om+\nIepmRiUSULXoNSqCYH9AsBMIsnTU/xekllqwej516g7lQrsrqjeru6f+qBRzSgLkMg3AKQefSZYR\nzbuW9VY6C7Sod/M1aBxIAta7wII5EKRmoYng+CqIaEwztB7+QaqeJ8o6JYi6XIVIh5VyERNZiQNy\n/VwSQeHAtMBSuDBtJiqwlZKyIHrzm/AihmqH8Im570ZuJ/C+fpXQ3cBuQQVHw5JEv93SMr7cVSwJ\n2d4J52fKY/3dua4SO/PQqLnkdSefuZNEnN9jO6JP7kTUuv0WO76YOiDd5TnE6rKGEz2Mq60hxmxn\nYFss5p2SMf3CKnkfLvSn28L4wXSFv7M/TkkRhQeKbn9W/ctnhibhL+1w9fnKG/fchMJHVRoGzjXD\nfXiOru51VLJwLMaHMU9iEsHbBFoNxjE9x5Wx2wO9qT1wu1dg/CRPfj444DwVwIJa7wT2UT84ymVZ\nZnkyFVsclnzPs1bNIzJEquI/ktKQjyNNeFYXAR1wIyvhU7sPntLwNE/qCvWm4R3Dlo0spd3XY4KR\nDjbxqpwxtReXeM56nS8F4wW7KABi6vw0LtxTgLmOTFc80KDO/gl555z77f8lSS5jJAEXuBlyQ9Jd\nm9RiOboFXsgFwwMzZaWi0vlrVXsmhWQIWzvbcPi+aDj9wuDlBBTr9o3BB2Cck3Np9LAqKo+hJet7\n1wlfugX5Pe9dgLcHFwlIwAkYEit/REtDci5L+2Ki9QiC+y4IA/4HjsnZTuszUfQKSsHV5zeLneqc\nx1zfO2orEoaHzHwC5sNubO1GWpD8r1hHaO/ON8mM6tPnDEBJkctoaRgI+g7EBkQin5tTG9FJlf21\nR6Ryd3Vd4aRqu4xiEwIwgXIJ4uGIXul5UueBOnqz1+TPlfwPrY2XFf0N3eDxE8LqQO7J8uzKWain\n84+nMMg1yJd/BlGh3t7VzTM6Dcr2awxMVVEbNwjVkq81z1RFFU9XPCfqZcjq7VxE3TasKgwivybl\n6wZp3/LMcs5L1ObAw8A3YXn3RWkFHE74J4f9n9B0+70BT0BH1v23IiYFJObSW2nc2PnMVBJ1MiLn\nvVWQyRItOLVVShHB2yW1qxFc8CRIUEvF8np6FR4uWd5mvslRYCdL5lakh4JzLYo97ZUqf1CruuRZ\nnwawJKY3wejxZSif+SQioftWkNQc4EVBEoyAKneBUuD8amzt+ChOVkQy6f/JlkfBw0i+pr422AeJ\nuewR8OzbI+NH8VnINHj0V2rC1t0LUSebHAus4xXa/mGQPDV6qZz6CmPAbWa+MjDN2w/oOb1myIDJ\npC5wU60aHQz7LwNRhpeYac4OPtS8AiR8A234lWGbJyOMn05Jct50dkFilH/eqvDtfxvTYTAyKkXO\nMKxX6llRbblsO1EjqYxVmkmQngFUlrg544VmxzWc9RMdm8Xo10Ws8U+/AQAD75vvboGXrym3Xy7P\nWqxsa5DDan9ABN3Mx0L3WkqYJHDT6qamU/cUcbzoivZBYbTNR3iqtClC7aVbszBBKphn2Ux8tDXd\nr2enn8qDvGrzxB8m9UaCElRIoJmJ4iHqHDD3MlEFq+L/I7h27tFX5rQIYTUDgibNqM5bl2O0Zdxd\nBrpVoB2qaaBB+7rm8Flh2iNyBaSxFCD1C2l1rXC9xnAJRXyoCnc/prSqqVXGuiUa9qEQ2dD9ntKZ\n9r8H3K8+KylB25GS4s6Iuu46Kxrqrs88DCZnvLPMFSn0to8/1aHreQHbm1qVT8ZJxTgz+UX75WyO\n3h3kvvOgvr+LOwC+Wrs2ijWH76rVsx4/2tl3uV1/Ohu2JcrVZq7pGWOXJAWmEh9dC+MHbbzRqDL/\n1kR5xTy6miKytYn4cDEx5UBdAoisUyj0Om/GqSakKtUnX6Ds2vshCBTMw9cjpDY+CE0d5M3ZeLBJ\nE06nEenzFG4om876NOJOWyuMqNy4Xh4RG8tRrqDxTLRXfr6cBZm0GAGRREPQXJdPnM8g+8w15z8n\nbglvfRopoLE3dFr9R9fJvWepFlvxJxWNiZGH6t/a8arYg3XJ4tfBlmF2/xG0EMBFOLQFEYmslPj/\nLP7eWFNggVSOVTGojpb1c/5jP/2QaVnCpZV7aRq6tV7X3ISLsSHn36CatDzSq5rJaDWe+gAC6S3x\nbJFgFXYt2CAlL7gKnvb1yztotVWKE4yUYFEl44HbtGUHrA4YYPAXUIXtnm2/KI4TlrFZ6WFfq4bW\nltgv1McuR6dqgVJ7D9KifI1r9RVyScduxvbujSohV0a9QWXBqhfyOq14pRj+vXwDAyROFwQBChOc\n/oDSbTs7OANBkFURxbolFQtJS1Y+lztRG/++FH3qLg4yRead1APGK+QabT0UF/tcKTZ/ncDu2BIW\nE2MMBzK5jWWo1zalVpGZ9N1nacGzaEdizBTZc3gW+3oK1rWuTQ8SPY46SbXvGdRUjOKM+UP5bran\n85yluKpwVjn5CGpB9bnOI2XLxi96PK+gXKFCRtRxCfQ0Qc6z7DOxiqNoBFjMzAQdGvqs8hOdq3ha\no4z7lNivBFWJzzWASTkPjjwT1ZNWRmuZSPEiqH8BmvmLHC7es9Sm678a10t6p3CqusGE7qQYSZd/\n2Tz2A6MDVEUiGxNkN7ubuUFX5aDuH49Hzd8PpObtj5tceLgH+/PnQIeVIZERz9+ASaPi37BLIx8D\nM+QhnWPpWpsivZ3PiXcYv/MbFOyaJVD4W+PY1F2dSJOrVBQ3kSdrat32PVJL48i+oX7kerVaBN+w\nfbwWDlT0hIEUhYFm+DnPGnwwUsJZYMLlJUT2h0TAre17Eanile1DvKO0B6cmQTqyOJDdmkk2uw8o\nfqmj+TlBEX02p7SaliOBVBrylmgQoeAqZCruSbMnmlTXnhgpc58+JnKMDd4IhnTs4kNtn0pjJWpg\n3STomdD87YOU6OXP5PapKKflDq7s8ejx5OSZNDh71IX5yNY5RoxYQH83VfxNuI5dhDle+3VQWtdc\nB0wjZES1gHD8X6/05Ou/xLHKsbrE9H/8Ab60AYkb0snpBcgT/V/U3DHZjp3gwtu3cbHSK4bKPElX\nniBpFsTVMI/o0wSUoM0wDedowOA7zf0LPMW2E2N+4dirnIJ1xQB5e4rg3bYpgNHjCc0Ir12Xozjl\nxNJ6CbYzmCerk7KvnZI93HJHWWCuNN5mNs5PyD7GuilvY+P3UTHJnSw9TUr6bK25BLpsajJW5kW8\nhaclM1RH8Hbu99/VDh3/RoPhm94dUytaeKvZ9GOUZsDMnljJ0Sn7tqFizuDddbocoV2FbPCYAMKR\nzhfmIhqmldBC+Pr3+cv0bXysYt2iuVjE/23tkBOQzk4D45Y/JIKeppVaMetrctkf5+GlUIiqkFBm\nmVazeTj01c7nMa8xtW+9FfP0CV8WCI7IHpPURGRz7wyE+/QphMPYh173ukWv0UE9xZyn0lV6oOUP\nyDD9m85ciX8SU+WEWZ4pKuwnvDdZeJ1eDTdYa/kEJ+HFujqDh+/OfPE2mlxG68JoPN0XH5My2LbK\nYakGTkPBiHxgepdkMCeesHOSpA+d/22Robhaok/Uxvsvg55N4ee6/jMkuuXEk/TEyuNRj0k7SrPN\n1YeAnTS10FbtdIbQDwbVbSv3JC1RRqYBA30NYbXw2lH1x0G1Ta/jERbHLdhA0Q4dv4Bh1xwpwenj\nSSYqYfbKS1CtxVCUutxNafTQPKlIw6RxLWMMjGrRc+AV4QoQe2H1mRCO/OIF0GVzfDYMB5VPEA2v\nFYcte8jLTXrSbJnl40CgzKbTFmRr+7F35bY+A1MYFOBTUmcOs4G334axYoFn/QMoy2YoCC1Ydcnp\n3gmxSNymVGlHR9oKyr19femRQ+RcrYz5M4F0ZI/OdSAOlkehU6GMnB4TqRD513hRyn7Kln2OfPxb\nsnmV3dnRNeu14EUX+e1ERN2QBM3fAIRpQJNDLbHR02hw+OA16aBhoJFHAOH6eZXjSbZ91nMh0Gu7\ndPuW/j9MEWLJu21Q3BJ0b52q6IL0Xi5x8lDxr+0hNnIo2Db7++4Njn3yRs1xsh4IgG4dL8cgt8hy\nokykdV/eOF/RLtyd4e0QrOguBEhB1391eo4ht85xAcGv5ulOJ/T1jGmkRzIEzJXxeVma9nW/EOfK\n/jRv75GalxomAjxCYtRmKtliyearXSGNyp2hSVhZfrHMVW4JpS06IKw2UxvXt00H87z1xPes1sYr\n6Ecpx33qyeLz1uttVwnmbluO9EEoOHATZNPmLaRxslaJyQUPgedV/IDinAWHZ179vj9uQuvchsz4\nn+ymIDRRXYmeFCtgUHxODS2danIMARCmIYZekw+oqhgEPd5zaQYFl50rXQ4iptHHehUOg9HbPNDW\nHnLNMwSRYAfHTcAKVOyYVTni7t0OajEp1ZhGo6562GKQnkngCugBzhxzvTncqLxa0n3Mc5wmCHwt\n/aWrEzBp/z4jnDjv+VPsPLOIDw9GuDTMG9ThtDV1YqLsFb+q4fRFxP4+gP2W/atO/cnk/MMvV+tx\nFL1p5l9s2sbHUptySsuOLPoRTbdKolzyjm6ORMb5aa/1nFb/jSEGFXlI43nPL82tYOjysBQFnb5v\nTikCPcb12659KOt5h3akMFVNCwmOuMElvembgXCCP2sDCj+AC+etxFAAWKHT1lpV9clagkSBdczf\n1Tbp7IAxPbCWKFj13Q+VoBGSwVvFbKWC5kmUhAjt3DdQpBXOwyP3lCHq60gIP5BPd62Rr+zrzDOi\n+11PpFsfxUm0VyU3PvQfvhS/f/P1QtCVlsGhUQwf2gUxkVV41+hok9UYOEXEjaFhUOH9ek0pdkxP\nv2NXEotEzDX9Jr2pFE5V32vA0X6K8OnyH0H3K5qcW8IsZ5pV+UMuItNfAc9ErqOai/gf7cZejO9X\nS6YGwuIB6tIecIaznXQ1u5U0EagVb9tVbucexmTzaDwr7XVMqEIGOLSJSeYwBW35sTD2dKqdM/Bi\nKDHe+16JlQ6NlDjFyy+bVQm9OM7BCHvVtYFBTldqEWNlFXUF/2opydMx/rrOENA8q920A8fYOt9m\nJHX/JMePG8DF5Pg3lYANqr7n84pOUugC47zwQOK4WMObh7IESlBPivtWfQswqTJGyaTl4Ridkhlo\n7ZIwDq2wDLKymh5lVwHD12YAZ1CZSLW+TGWXfmjFP6PZGnXTYoYdxHLLX8Y5nDTrLVCoQgvL+qSr\nyZDHvDWvDP8uqdk6ERWJBPdlitQ1UM9KDTmS+DUwaRzwo735rCtmChCQyzYzR1O52Kuh4nAPRClT\nzEVs8Nsih7WszUqQZWlPnz+VRoMsDqx5+8RF3GeTtN93R4xlkKKQhzBA+kjqQ+eTXIdYQ90WztQw\n5ZfKjVkoKGO/YpNqrKZab6tnOW9ijl7caviAiphC1wMtaxoWJ+uY9wN/AjVodltsHgZxVlhW0plA\nFHz4melcgUdFqV0bs3bDGYBq7zTk0/etT4/TBaZ4AOZd85JttVpUt4zFlAw55RcD/G4EnkIfOHQn\nUwDltA4PJInJEAiuvEfB/h9z5PcTaTuOFJkaXlJxLwkr04bd1nArYsEdo8hrbqHN6WZkdsrJj5vn\nrhFea5XmMOma7D+SxlGwZiszYhzE9EG7ykCLN07DM0Bijq1MEiwC81rfAELFeRKp40KAPbR6Dy0O\n4ll0V6ILM32eW67211KhpentGuSeGUkhahkM3C6BarXERUugAIGY9/zQyHv1NRq/53zdq3fTUu5j\nFHyGzxmzVFXfBjlU5kCA/j++5KntV/r2T0hS5lhXignjbZBXlVORgEpLtVcbbkSKyNbc2IXA1HeW\nf4WInqrrMgIzDMN/b0aZcl+zhsuvdSVzu6VGbxffDNHMhmrQqPfOkdNUfx0gczKI7v6KnqKf9Ucj\nv186Wxn4Z1ekpR6XF4GfgrSakP5IftfqPvz2DfzqsNCXp+NHn+27HWbaiyrPczEwRpBtPhhlCENm\nGE0r8akn+T7j/5jJZc2t3hOVUHrgkBHH8uDouPc6I2UT1m5jsTIe4v01EreSgU7sHKk5M+MVqYZZ\njOYGXB8HeQ6zbKPnN7qcozxhpsBhFbSe6MC4Q7h4eJkhMLjs3x3KaRSv8RUFVjhF8hRgnxSyBo3d\nEVK49l4cxc7JA1woYFEPu5hsMCjoIafFOUU7xMn8r80XnRSAks904RBEj3hWGXSUWAverPFbIuAL\nlGnoGaSn7p0EpOlFDZL6p0xovy3vqF5txRDN7Ewx4j+xnrX5DserTNwa878QRCiLol1MaGNlvPQq\noiv4Usdp2PZVMFBV1c0xstPw29BaPwCG93BYIdrePFZFsvuBuMwOlHoCywoHKDbqGL3mfNVQPyZ0\nFiRXixCBoU6nzPlgnNBoeilo4zrKvsS4eDkyOV7n146oNXN4dm2muRszepQEZ1QctOMzCgSmYj1z\n/thN0u+hFvCEFm6ypOpedDcrDcZfrFg/L2r2mQuYvbJMg8uJs5tFQkDczdNB/Y6O4i7r9MjQSEcW\n31azaFPiMn3VfZgj0J2N8OZc+H5oq3BwspB38Exdl0zD0ZxEukeEbEaEDAs8wLZVX1Kn+6/n4ws8\nOVBEu2JAHZ6QDaVGNeCnk/7+bUX6AI84MuvYmWS1OUpMDT4i8PSq75Whj2yKrr+T0ryDpDqum+qC\nk9BlXkB8vnKO7OWbsVI9VFLLVV2fJNHhILQYYixEAnuh6KkHtlF0iXeIueVyrkNf2P3VAWbgKn1I\np4DwhmztyZfkqDXIw359IWI0lGEQ1EIaiK4rgBD6zD/RsjUV+c/+F2GXYwHNym0qxZB0J/CQpITk\nC5xmsCaU6gwvRocfJIed1lGB0TENB2u6Sf13MOlLTTLMz8n5lJA9ZEYWvpylodIsVKRCm8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ZS7tdu7W8ffRhkzvJEMxee3pzmBtSyLwvsU6U10604vZi8q7DQUvAPETQ4An/P5mX8Ne6r0T89fG\n7A5hgsH1BpyHoTbTQzW5EViHx7sDIQB81XzUpCOd0gq/kFwe43DODmTeljHtUQgjaf0GP3mK2VCD\nmpKiMilEW7D4NFWyvwsgoBbMwK2TWGvCegrjKB7V0OaAE0aV2jLG7MHMkbBYVMZKWdC40vnS5VYr\nC6+4UDws8c1ojq2dd8z/OYlC/usHE5aaRm2L0ScbVt4fnOK8TE+/YdRJCpyRauWFK0Yx6ytIv2RQ\nG/AnQC3NU0BDSVir3I/ABNFYYekcGr//2mcfX9UauIBeAzjvL8wqkZvRMYAFGDq+vFhMNnuw7PlN\nZpiCjp075F5e7Xmeld/qdmbce+Q/CiNM0XaXHFCahSm5BKXoPkL5Nt2WhKajC5vvMtuLTMY+OU3e\nE/emxFND2XINmq7YsCo4TSsF7FLqVjcwBvl0tEJROrsSNsJoMuw6VXEYP3zD8vkj1xW92FULCtIM\nsLrfQ6vMv/fgPE8Z3oOe1CN0+EdhPgl7pjMtcERVZ62U0KXHqm8KLVC8ZooVMhl32AANIlAR7tKe\nAOI+kW6gmCA82cowN65WlwChI11wwpslVQFOqxJDwDl45hTF981am3Semy6Ftj9mgLdP9uNsEKFq\nZfTnwodhcg1U8PyIE1l3ePvbP9fnM1hw/VhUlMrpEzGnz/qekPwgJ5dqyyQg3xXU4+FGiwfylvuy\nGGGlurAoVwZ4c89ZcFS7T2mHLhVmdrugxM/Y0w/bcZNqCytdobPG2eB1lnLOxi7HXbcGPlT6obrd\nCMUi9SHdLz0u0JvwDjklZDXk3Oi5XHRSd834VGHC3OYa5LzD/l6VKtoPzLaAG1HzMLK9ezYGKnOV\nvD7pZxigckMQiwkWeaOi8PX0m8ibTrC8LN2232f4ySxJgs6+zhhq1G2DIqvpH6Qw0WmVizhwqdV+\nZQw9oU1WsNtoMsww3L4IxHKlgmwsSb4gqO/Z1igiTqOz9rwDJnSISFj3k9FUUHFq03FfKBsg5M6k\nqoobD26/legJaY0iZeDTJCSwLfQjoxSq4OcEbBfRV7o7o/6JAmkDyL09TeAcu8RCQrD317K4YCF9\n4njQVT/gLQ3VRX2u7TQi3MSOorqgAK2xdwb8r3WZJKaOwIOl1oLx+7HK612L8izgOFuzpsw4ut57\njfxuVx9Z7vjoLaTuQFOyiPki/xNH3fj39qoemIf3aYPkcZfFu+DgTUgb7X1y2tQJ9yvbd1PM3uqf\n4pyUGC1cJ7bPhgViMMUZRoH7t5xfvYZKAKqCnBcIkvhPSRmXEEhmSv0yviQ2NQB1DcLnk49JvhB+\n+5hcigT1w+2SqyRXqIvx4xPc+Ww/JQb70TA+IoTnKzlFdVeumZKlAFPJ57ZuQXFNHxCdLe4cYEXa\nn/ElUXwRckXgDQa8FtthkiyscTV5o9Zkgv/B8jLFN6CuaL5+wf+DUja3XdSPvqDPx93Uoalk7nj7\ny3rUZjLvz8Mg9YkYV7hVXAkxDKjuU9eVDvxsj8LKsMdF8g8ClfxwnlgZpFuo/APgewjvR7ODf/Ua\nw2FCX0Au+tVngET0vD0Ylj6mhzIQrpT6c/yrl/iIEi2CivoB0uODAwqcqs6S70LMtBPeYtrrjp/3\npirJVmYSXiZUv/5xDzSB9l2+Agta+/x8vrey6KeQfktwF+fqNhTPJxWdCcTtJYu3KcoZzyo0+fG6\nXaQ3twvWK2os9uzxHr2Jc4FWi+UHpYJI/mVasz7UYFP3a72Rukf2oUVF+B3MHIs7+tzpFpd+YMsP\ngoc5h9n5QhwxZQiKal4vBy+VRz0QwIg875qh9A9C5XOqOm4D97i59suNSur90gsQLX6LTKvkocEo\nn8AvSPQr9bhoMEJT1uQO/mMdRgcq7wY+2rmondJOZ4qSjWj368uBrr3yPVykELoU/oKu3m766G5e\nvlhcYlIrdu3pY6Vfvm+TH9MAjKScJsB3F/0VZQguyiv97MVG0+MIvrQF0D+2o6gZni/vrp6+224X\nlIUVgkizXyEU0SBACYd3JEh6Ul+aSmlOkC6B+A17c5PsZ2CHj14whCt7f730zPMuLG0cOi8BmyhD\nmfsNzTGHyFJeOzXQbYyJ/kQgHcDRoEn//6+7A971pMQ/2jE7iVATaaNKY+IhLg5EkRzvLTLlh5Vx\nbSO+0bRA3wHE7XG1q4ulP1ApHe+Vl9fXjt8iM9hv7nPuWlLyOuAvZYlGt80u557MDCuxDM6sLBvY\n4Z3MFdmKSH6ziyWz4bf7oKVHSyUXGim5+7E6bDB7YcA8h1N495naU7nATsrqT9mFXgFLJyo7B1VY\niMu/nD49HdVQ/OKXGbdxQu9CqAeQSbdAiA7/AOVpR+9ALJiaPB2URG338rs3JmTcCyEKJTvvamBL\nol7JenYkcqIspfNp9oKBgeWxbjpbaT+JH82LLriBoF65QEQE5iPSOUs7JWIa/JxmRDlS23m0xgrL\nVGJLSAMmVg629Em6QNkbCijnT1Xdn67HsPURDX1VgoCAJlWTC4zkB6z+JOr32/Y5o2usb5p15HwQ\nw0OgRQgrYb6Hiz7Zm7XY5RXkxMTmO2BOtKVLMN0MFu+2T4e0/+lZLT8y4LLqNfGyENhp3LIIUnyI\nB+bWkNk4QUcvkjadQrmme1+PG/dBL14FS3Su1BhBLELSiMfSIQQskrfv33SYHpFCsxjfmZXojKNH\nv0zKVTNY+ouByG8zL85jFB6QnnKBsggpQ2xkubOtIDl6uQWkogKrr2iMI0QjSDU32/di038NFfk4\nt1XAjzI7eLD4mFKIKFSV2uqBVfvq/m0h2Y06nzMENWYPBtjjACnhcI+1L8SR0fk87jXzRduvG4FU\nhGfaQSEKE78GNjnBOuxuIkL0Zfq3OnDenYVntQB+FpbB9ycciWO/oi99qwNJr69fh77f1Pw6i8n/\n2cFGpF7znvGhB3IT0DjARXSxHCR2q6pFbxGUhj0kjcH4Igzfzrc7ZRJwrK/BYvr2NENvJetHS+YY\nP08wrGQnOnDBrKzS12BeqqBUpFMBMAEwNR7+3FkEhHombutVIc3fykyFXRUk1RS2Drqfja+UDxfY\nGHnJRyLdXp6oXr+KWIJH1txa7il2uXA6r/SoPuKJ1E0Ve9PojESZqvgsl49X60lBK52Q5fOf3mlK\n7G+T5s6oPHx28tRyyUXd/Ub3ucYkQMCU4h4bZQAqPSQ/G+zb01nls11LRAA1FeYB/NbQPBn9azyo\n7cB95E7dpxaVHE4ItZtHYVYQJPYqyCso0t66MkmoSIP5oAFgWVkvdrf03QNFkfs6RtZtcitII5j3\nLSd4Zh9j1PA0a4VA6KHQMVLfys3NuZBiA/tjCou4qZVect3q8CB5CFKC1sXrWL8huKnoM+S/K4zI\nJmr7o4NJQHHJJ4I50AnfJnGA43Yb4kYTTp5qJgsmhNuF51VxTsMl0CUfUCHiiMrDKciu8Ktppb+Y\n6UoCL1w4969vcMWWwrkjDuRjc5CBIhhQ6jbcVUT0fK/nlfPqJrjxSd5BGbOJGD1YgQAKUUThAk05\n0qDhUxb0+5BrDil7XFsDrup/uZeah04wocecKc+hL5TCoSv4qNrSGnwcTSa/1cD1iDJsq8/psnig\nM8rGGUvpISh9wevUzPLUSubEJCnZ17yTgr3WvAoN03Y9Per9KGzSKMqGslXSMFAHgLhYKtA+jj9f\nFrKP+qQKZd14GcLyJnoPmrHTjcjQpAyqvZmjCB88HDyQDfS0Ypc8oTrtWVX1snMfA0NxqttvRGwW\nNN64itvrZ5Uyrvjff/I4ZTrl/f8VyC+RWALoOkT1r2nIyAlR8ojcygpfO+Eobafu+kC0hM3FpHr7\nOWTeSvz17lRCmy2pZ20OlW9uHUvzR0XelQM1QjEyu5665pY+6SBUuEwdxNLDwXKjdv/6AQHHJ2yA\nhJux5bpq3GzO0kY6ehcYxzM6Gvde8wvaLJrs8ghDvzTOOupGr8j+QTMfdrAy4UwdY2QWTOdsXs6W\nMfYNMrL8rRKWPs62ayZojw/fn1xSbXmw7TJjMye26jZm20IiNU9PKF4GLGnlHVVQHKhS/nVSaVg1\nAXmGub+hDbsZKe8wCSLpTyGwpZvckI/F7OQa6H+yaSuNC5ULoK240PM116983CVpw0SoNJ4eHVDE\no47n+9tg9/r5YWO4+odidjh8oyGnPEglZgcESnO1uZYatm574n5BkYXEnBlZ3Lvr4Co+2z/VO5Dp\nO787QSbIfgPy98MYjASVJj2tKI9CeVzZ0s0QMXHFOe0AsPhxza06RecvYTUdc14G1X+8h/92JQkz\nHer4p0qcIhrrZ0l400TyPei+x6yIoeHlRmtMQnEA/9abFTVXnRrewoIZqlnUMW2ppwkmbUAsqxlo\nyDr7GQ8ug8dNvt5A0K4vzPTfr49owVOtEEhNnP4m2v4M8Nm9nyr/dq4PIJqZN0SMtMXLhffbatmJ\nHrqfhPIXNPTlr5yOygLXTLyd9UXnKDwoOjQUHat27TtBR9EJaJW6AtkSwKiDPdWB/5/HET80mTVS\n7H+tCa29r7Fp4il3HzlJNm938ZG6HIg8UoSoNPJC53JE/k+C97isOIJxx6L7nHv1Q5OJ/jLXdQIw\nNrPde04xxmaU4jTyJDtdqsoaqZ5neQ3Y9fE4Ks7mu/eb40v3SMaAoDcpC5UCjJp78iu+NOCoAM+m\nLEyPEUHB4Lqa2E3w8MSXdAb+noXfpZJVCKzFCvwsJed5AvzO0j4dnuyYDWXTtRFBoag6dU1SEPvp\nMequcQ+brPWGxkipMzapMKvPRKUtV/gS9CZRX5cA2j++G1tknQxlBwEBN+CfGeAHe67N6BfjP+X4\n7Y/IftHX/bkQU4OBq62Rqv6MMM4IQHdkw6Uni4gzjbiN9Iec0buUozZjw8yLYLvLga/kYXHXTDNm\nVxJhfM92Omd0KNRSTjBria8Wz0EPLBZI/uIXqNJewoN2hA9nSuTLPfL+NlWYLPqwTVe3KvCFg7Jr\nPbh31fLhBte3sRbp6VpP7S0d83mOMw+Dh7RVgflDgjy7O/rbp1rsAZ4AePiCkRy0spk1/s7gmnc3\nsOaL2DKM1OrUycGXWgV/NMPm4gC3zsgJ/xCLxt9w+iW4WjyjCnYibdJoFeEuQHxstO93l1Pfsdw3\n15nMugm1f/+vRUEnsbR0jYWrbRvtzPP+X4G71ox2t4lczrOCUHEuaMrS81g5uFBKGxaO9qDVBguv\nbPAAYRriLdSD6xp118P1koOpL2NSyhAgFsULMqV2X/C5XFkMgKVuixZDJR8tOsYk/7empEm+NOcB\nWpgpgBJoICv/FQK5hSxuPviK9guDb7q5DfYZqzXt0/HRUIX4KqRb5Ie0c1Icw9RoScjWcYqnAnez\nOt4EMtmhSX6mZ1rVRoiHiR58hMBWkC3PIzYIizVR/1inVfnka7Lr+malwfEjpKnXLmCgpGAVEUbW\n8OV7Z1JSEJm259yKs1R5dqKw1iFO8Ny9DgWsyJOs8S9SiuVbOp9ZJLkqPBaQoAJbonbPgcEhMMhj\njQfhKiCjtXlX4UJlMwy1oIJQ6bpdQUpXNRSotwHv5f2PpxgVgsTUMQ7t5x4KSuOGoZuE0zJXCAaH\n2sno/Zf88Czaj9aw2tcscoMa0P/gVD4cdbIQ+h2138BVduCQP9wpIWavp2k0ATiZKhm3forho4GQ\nZd3N8EnyoNlYw17FDjWzfiNLqq/A50z17EqdhQHEGAF1ig7qI3kcoO0VjhD8FJmR+0pgsjqZ2MtX\n9nY+MFEGBDRP3qAabaAATF697pEDeR4B7jfWihOHOBKvrqcSEWsF8Kb68/No6GWV3P5CgDG73NB5\nX5AJRYsU4IJdYQdcmwc1KjBGep0TIraz1/Dp8MSPNWx+EvQSTWCi85C+uhI4plM+2CnCHx60BZ+Q\ngjdfg7nJ8gjMPQ5I0+gw1EdXKghllEkgWdR40ZsaEtOHI1F7DyoBTmxKWQXNNvLEtfuxENWeUEvw\n0jl9GFMddhMytMC8XH40Tm1Zp2ZBHpvGnnPpqFONHBF+19oJzT1usgJ/OFe4YSGuoDaX8P5Ufw28\n8pe6HntZF3BMUqDoRwcL1qOr9nYsBp97gipAdKuXGavJBG4pF9ZtdXgyXhBSMkROOBsd0F6XZRot\nHKeFy0TK5/8e1lLgu6x0wnbjeYQQL0eYwwxTZxGRXhn6Ilp5OmBKISmAFPFyKf1n3yo6RmZ+V8qs\n8sCh/84LHPfNx7uCCZQQhQKdwqjufd44mAxJj/iOMQVoBrXxXXkr9GUpzu/PTwkA8ThYM+X3dyO5\nNXPnZQH6Q8/XPqgOtmZu6uOfph2z4iPvaMTDEJBqf697Sa+DHW8x8XgCveQYxBVIU2jl+5B2PUbu\nCSJRPJi7z4mwl5O2eK+NqnzWNhribc28fbpgC7rD7YwjSGunmzJNiNCVAHV4ZFLQqZX15m1pR0V1\nahb+OpIgSqF9+BTHMQ10QbBSRVXtneGvBcYUAnYTilf+Ga797UKMgZxU3iW1wiOsVmBsYXSI6xvS\n6VqxB0QGzdEnTBDsMvriX8/UmlKz+OMQP6zD05fPPi8XeFvCq8Exaz6W+CTBvZSuRPyR4aLBVBjP\n6Su14r9lAun5EZPaVIwBlivVY+E/rhCFSPRL8UXiEaRP5pWL6VBrSdSj/+nNMpON6+xBXseoBMIR\n7hAqSXMjL3GFlwe78zzp1ldqBddkD4Be+kp4EfjHHGt0+2LoD6mM+bBL2AWZXqQsAExBk9mpQvl0\n0sU2rHC1pEh+fADeqA+62FCbJ68N9bS2Z6aUSQfbgmVb2BSod+U1H1FUgnIRT6o7RBAmGWqRi/di\nKGAESlArpA23PXYO7IZigl/bsIXR2UHLQP16FcGp+9rwRUTc7sU/s3TMQHCpgbKEdk0kKGKcazLu\nhCfpAp9CS4PczYax4RiE1ataZUTxOjhQRb+j7QU2+0zxQiX2ZeNw/cqAIVIW2TRheyLcxAJ9qSYK\nVqZY37lEAqOCyJFhBhGKrhYaijYr9Vfq4zAzuEqiXJ08u3B1wxbdNqXzlxygCDnRkMGujykVjlN5\nXrf29K4xNmi00IWfDAPYGGikKkgdJ+I60+QI77/Zj2XrLZLnYsLiCccuSa+y4ph2H7JUpbVghJTB\npPtQrYLpV34D5aN+WrNCfbjqj1GnCfC850cAo4DJW+fgVpbx8ggDnw2yrxuYcwg5kpFjzYq9QP6V\n7YbqnEs1G5vkwZI2gylUZwod5YhwUZ5784TyskbHKzuFo4zFcJ3gtxGN8/UGjZtyYMXk394YnMlT\nh8jcGsjbR/KbPTrsd1Ua2omITJevDqPqRtx0urCyioHZA/5efKn7f8u+CqDwbq0IREDsWJRE0Ppj\naZRP12vUUVyHcLyfJH+j61rmjbPZ7+FMSeolZWEZNkjjMrnoI1MjVDGnsQmxko/crdCTIh4ixpMo\nrGO3hf7TpxVR+p32M4meCzZ4yXf6dxeYWR60bOrhPLY0lXXbhQtKklWfLxAqBZM0msJVJsxtLYju\nCwEyE2ShgAc2KZi8Jbsv5kANk951oXn3tsfkAKK3jHm5JgfRnbdGbU7zxKGM7V5y3peEvc0kekr1\nUA0pYVZjXE04GPA66iY/7fjbZGYkNhoSFPsTV6eTrfUwhpzn2O4YQdtDpJTRlfnYiOAFXcGLaRx2\nzCYrSRjfpo5vJ9Oyt6M366umHrTXWSKiS75G6kfMKx9LlPdrq1Br/tcJ79gifJlda3SaC3+BGVHA\nFpZBMLGzIfBPI1pYLMwdrT5wb3jbrM5ORo1BRy5VTXWFw4E+8gR0c1xoTcWT43vXd/BdBpk/NWUt\nne2UU5WNhbYzrsdscaXs/eB/gZ69CTurIpsqXiZWzHSuv3bNEV4nThsnzA/mO2ZNd6En0oOOKr3b\nZ4etsCtC7UUBdJbj59UjNQ4/CQd959W8tBRJI8u4yAgsQJ/w2204rGrK8sknKaafM9eW+3LCwjn5\n3rFKJp7uThI6L7CZvcRcms8zF4OOm54Z72v64E5rXLgexQmR19YQe5A9xJMjutmrNzPg2wXBCBPt\nKkHs7xvGXiMnJ8loEhR5l7VwGssBHPATPgEJquHLiGtb7zRh0hCxxSzYVDXPXHX5D+6brv5FGv/0\nltedjzpqaoc276+PDuVTByn080hf8QI16/i7cBnpkcrjWTasTApxSjkJXZn04VI64RIXjp8zwxz2\n0X8bnkYVpHuNJRbWlLaso5BFIGtT5uw/C73UHfcJyaP4ekBxPLbTcgYv2UJHr6JaB2IFlcqJJpag\nSYW9Zg75nNpa0+snuuOtBsY8+YO4rSTa1pBh3Cv+onCeIS6YaDp4gTrFIy5G1y7FTOSzXxwmECMh\nkOHobc8mCkEaryZAXp1fsy5gprSruQhOmKtJqojXKcQHN5UwE6s9kdn3PbnX7+pGf8pGym61zWgM\nFr7vpEFl760ui+fioD8KlYEwZ03+gIubm0qT9iv6xGcBo7Ut2MRuVl0Sh5HmSUb8cW9qGjpG+T/0\nhLZish0ke/xnkIkqUMwEtm5vSlLMZ5wX7S0DGMPSxdKnw/f0GV3goZd9Iojbu5iCx2fMXj5mHirg\npiyg3HjFIVZLWvpXGa3sLCg4wqgUx2HIR9kFlqu2ZJHagY0XTic6K4Ta+5C7KF47TYXTFjr/cKch\nVzqqbPNxCQddZXP9Qzl3WnISDOk3Q/7fmIwxAUVtGZRwKBHtB1BblGnYIfz+iB/oqpwqq4ZXqNyu\nvvh5yZ3CcWca9CJa3EuuCwxCRUytwAT/Gxpj2LONUb/z+NJB8SvU2OJKC6d4nfatfgFNildZKaWa\nNP+0fXlFm8DjensUBCZ12+41qae3lHlk7yFbFlz15shlWmikyN/7g0ty+03xGEr/NZwW3fU1NdW2\nYohT7hnIoAB+7P8vqNvgDzfmaj4mYPPRn1a9Jf7++XxDGO9bEmnn07KH7eurowrrqh4YeohCy6NW\nWyXTTZzQCKT8oNZMg3ViCC+Jx422FWUbYULCbcVfUdRJgTi9SKW/kx8Qk4xtV0o8iCLo/VAyD9cM\nr4G0harUqejA9G375QKxKgHuiSRZyLH/k2NXXgcYrw0Nn5QmHOYy/ZY10W4fZU/To4JXxn4QD9X1\nufFgscGdd7kBH91HaVyvYDc6lM+74u6mxMHDQ0fKUsm3SdscK/5tsgRsA0aFguGX2pn96tWx9IwM\nQTZ2Y2+k/ZDAjHlYFiFvLBFfzFzYZOnaKATgNlT2vwkHEzFTOmxdoCUP4lTV2VFpbwOlKvgTiS/A\no9NqE27wKQwACvIxjtmLXJ2fETsSPqoW1B+W1QJq17qMrNPG57+kf3kOXz6h/qE0bc9Zo/B/QFEu\n4rA2mfdaS2CR4qBJeB86MV/VPCf3pNgIyX9On24bbGL3uZRRaQHiYuaCrD829ULOPhn/BZDQ+I1i\nZgyCshe35rmr9Pam/9NQagDY/ptOzi1zuxN/Qf2OcOIc4asPecJ6j/AInaI2O7Jlb4jAIOtaTKLD\nMjb5YbCPi/DBLpr4COXK4Rw6hJaW2XKCPAg+aQFSc4np1Cz+zBBxZhGUCI7njtCwVxsVDcPAyp71\n0jEPrFapqJGqxcltVt7kQGEOx+GT4DiCoOvHU/19WFsGy6MfW6OST+jlgnA7iIJivkkQJzkP7Bed\n+O/+9LndzSxaGTkkh5CKzIpXWkh9PvK/GBUXLxpvPOOSHl1zh3op54yv1yABAJXs24cG+bjwMPZT\nQqabTsnChNRYfr4VQNcKS2FZxU35Kv1hCY6MMXSbnFNlsIb83LkHIQrvPVFxEN9MO+0OUaNiaMaC\n77GBcM7X+sQ8vTSCjtEvmGqHze6Ki7SFxwdhUn2mQh/gRsOlPV9yuesq4cvCvrLy2UQrRheHkzjB\nrOw1Z0ime3AKxiW5TVoBsymYjXJoV7aQNThBMtmCv8BRYSRxCdl9QElhRe3MXPw4tMcgxLA+U6Rv\nu69UWog4hM8XGH71mI5CC1NuR2OjYUxCsY15N913ZVmcb6f7tiCZPVFbvspi8MmnwUjVDc/M7dOW\nNx+6YgdCY1rCXMqYOrfzOQpirVlIRr5DMt5YIWnIr85d2sKduaAASiLhf+NHAK8LdakDVh7xYtku\nl6SrBfuR7JfymNiq8IB8DpBh19X62MrIUXCLLhH2KpjXw/socWCR6g/z+PhrJ/heMaQ2a1kXy3Ne\nn9j4hMFo3NdpP/ZUaYbr/3nXcTtle/dVu3XvqK+rWxDfdzf2302xF+Z2IZFoRKURb6SqKa+VKX1f\nXi1JDeRwBD0pQTRa7ssizg9HSj1De67U/pQ0wTMnUdR97GF66Spaz0xRO6CaRQRmFj1i6UCtliRi\nnbgXqo14hd67u6qHPmMtMvIxCJIYA70ao/eB8Dx/ZmHHYz9tFr6FK5oP4yCdfRiC5pyGiew2rz3I\ng1dITRQbM+I6Mehr9BIpDtZOG8EM/ej5pJh8YMN66W3giC1E4iAYrw8XARWdSfeSMorrkAZOF74a\nRIjc5Tibb04RqFy81rjo9tT4pFXPgrBCa2Vf2k+01Jb59FDC+lAY4HaQbhMkAadQgIeejI21hZSY\nVfKLyXQQjJD8/apPKZlUQnJt+z0xaZcBdoujBpp3b3V4jLvEc/JtvsWdnpLpfnjckEBlf8BX9xZu\nsREFeYyO761XS2nqd/1HIjQrC7T4ia5jVpXXytUDkwbKJ9PgnUtQN4zThoqb0qd4aFk0bk/WRDji\n+7lVAYAsOpmmbRuaw6SxroIiokHKftnIAeGTHAjf0iNtVK4+5rFJRiA8vw9ovKuFVGAfsBzQASpu\nME4p49rIQoAOHNveQF58mSGHBotRerYM1SxQoBHizwSPuDw3kcKYiEp6VNqnC+gCLekhVma34PiQ\ntX3Plu/fkp0AEJbJoDAFtU0CcQkrzQwV4BhgA1iPfQiGjVYe5oABv7oZ6tt4WT+XE1at8U1XaVgF\n4lwEz9DGuQGyf2xP3t7WvmTDu6nLTWKTK+AbaoY5ZAedVeNq1D4XNxWMefiCtSzxqJ3f1CN/jGde\nWZJIfGQdNrQwJulnQ9FgQaRqAaNbtcn9I9Tg2qrBMGwzFP5Ii4HvVq2P5oXLKCyx21ec/yAXng/e\nctVHG+ANfsKMhl1aMiSGLmibbtkb8SYChQurQBj8v6adfviz1TRKjBl8tV6mLpxdZzmusHrQJi/G\n9yT4vUjR2UhZTzKpF9gHUeCIRbXjvyjnEB4iYmg8hYlLEq3gusEnnHamUTv6SFDR77Ifl/45UNa9\nzoKM/sND0oBgPUtTsXyMLfsurVDV87Ry3a0apxeEEVu3D5ttDX4TZLCxRVqNgORDJSV4D3VfcMI0\nJtQRo56c6jVlnI106JRztMDqr8gx1+BWtYOPP3VxWfcmoVqgtl/EZGfMm7zE0+zKCRIaebMV4V0k\nyHm9B0IuCB2FsQCsGWUFL7cPcGmvh9gn3ZawpzMJdZC7O3t94MsMsBW5PZpL/cEvgcIA4y3PU0rx\nuNjDnQ38vehYd8pM+HEDiifB/sAWXvvPPpSODKtdyHmM4hqic9KI2X4r1eG0t1JPpYam1SjpldLV\nlyMutLDmzIKQXf0tyh39HyoUcmWYwLhR2PRGujuM+II3U769h4lnTgz0GkOd5tNRsTSlSSvjOXZo\nAQ8/TDqahYuVWkIAl72T13E3mDEr1+gqE0bAu7XffBCf1J9ujoSWGi+M6bw+PzD0H9JJRmIOAKnR\ng24x6tSCKaVD0PHA8LOz7uh6zsD4W3jQrWlYyrLVuEji7S9jJI6to7hn+X+2N5NqM3p2KIFI0kzP\n/DehQrFAxcR21uRMIRARu0fu95llrQ4Kra2k1IHikQv8xUWhit3YFE7H/KDE36y22HeKgHtUvBgP\nCUaPYC6Wtl8MI0eT0CS26R3hfgIrdjl7NUiCyajKYkzygwBcXkVfHHTU9oN2b/B3wzHshKnrxpVM\nrIU4G05U8MgfC+cZv5l0BwGo44+ca4oB4cUJ/2N2NbHZvZmOnOSG2xqPWMQSH5YqhlVzFicmP+Pk\nBxsGssdXA67gcTQCxptULGBZQ0HNZOJZzJaRvTAcWTgHhf5eb/s0equH/eF7CRiuj+EkdBEh+0hr\nIgBYNLiZe7unWqk8MC+0lvRHybAvyaM8Js0l6BNYKy5Vo87WPHdjCjb18nW5WzsO6xvjU0yWEcS5\nxTWGy/mQSfZvpIbutHV8G2PehnYE0uO+KZ/pLNRpovpK1dg0cuelKwqJlLGJYX+eBEud/vRclTBS\nqjvUaAK6gzU1ctZ6ID3gW+2VDgdSyf+5G7gUDFg1KBiJ+FTUvXnxEyJkVmEye0RYmERXcP4D4FhK\nScFnhXrE3L9m/UhZrP1yyAKpafPdJBO/G7zSraDyjsH6xbIoRfp8tEksUIT0mjBatbtT6xHkf1ik\nV4z32aszlDdqwJL49TVzHU51KgWPffwXdteJd1UyPBRKfFhdTfR7bNq4PACzoWIDh3ljBBURXBAd\n6edcyrTmS6hCterE4ZCRnwVl1MmgQCXbWfYCVuYOgwwUTl0lfoMhiM57qSG5Hg1KJkBQoLQMHZ4V\nwNLZyOOutHXTHUR44aFhqn7svOnFEagWNfUTGmcSd6cspW1PhWI3Pf+EAHNzMHtx5g53ZHYuguwh\n/UwotsP9drI58i/OXpldsZqW/7u5PvCw9J573PjbYkAgX2D4HRiOIc/WDhS5LGWghoRmLyJWbv2Q\nFRTGfYlRzH4N4sjFP4nzOBBRVB9IlQiUHyzKUtsh+zYKw2TVndR8NcCdbN8s2pRdOt17zwAHtCCY\nbUi2l+AGIm+G83UnVMTlbJf/mIb4a99KKSi1M7DBf3FTCV2OVJCWXNhSHDDVLGTysQJkBXaGbEfZ\nNFW30Cb2MnqtoVyUzh398m0oCvOCynRcereUNH2QZAs+CBz0t0j5FTAyuXAXyTC5Aefb0eF2Xo4E\nGzO04hBz6RS4PENWCNvx+Yu/Dl6TP7GWj3PRcLfTk03ZQEv08J66+gIbeqBHKTWhbdj0viWVibLL\n89yvo2hIdBs2K7V67v0JxDIKeJck13L5nb7+rOS84azJcN6eJKDTd0+TwfO+vpy8Y6CjIjtv88xg\napQ8CKhgWtXM16VdDBrII5N2TO9/26QjUFuTCtMgBLnUWFDsGpIyi3JD08bTZeqhbx+QYlk6KkbK\ncFxng4RFxYTM8c2B07tYV3xKEI7cn2k27xOY/qqTWeG1OCn/WjlUv/D5AhBcYixhC8GsF5lOdwy8\naHvEnWAUUlZ7jjZ5Hj+jZ+TL8j5A8pEwWqmwei/IyfWontcI05i+iJmhFUYyZ2IUSNMooCRx8uq4\nf9ZbLGarICGEjEu3eT09jXj+TBHfhS1wQx7toIsTMtjwJh195jil+qeqTATjLtNdngbGrxNuIqzO\nh21xTEkFZJxBsWQfLP4t+3B5+9YhSAYwfSIxJD3a/EJNSh9WIPxQ/zDnTC7rSHlo0s/sfOsgM2Cm\nIqs+V/3E08MDqE+bnyKbOvzDk+Zz2eXa0lbyPhuCWiQpz30O4BAlay+3fuZdyHov3tqfSUt+JqvV\nLPOCIFCO8o7JRX3DPZ+esKGKUZiTHVjzBGEyaP9u7/bc7+GPTSxSvOx1rwvsv2hx3xnd6stTRJsr\n9i9qj5ATaPFL/ovSsoFqdy4DgwCMk1wML3lVW/HgTT6Kd89aSO8Y37lSlzzBQjRxwLuUQIM+ZVvA\nmYPrzAIvcK//KurVAi5WNG5XZ/0SRqi29zGu0yP/BXbWALliLSKJ/3stzkheMg8FxqK1mN+kmqSF\nrNayNzCkeweshAg5BipIvOQt5W1KC7FsjhJ2qGX6hfsPwicAdaOeeFy30zm7g/bl5ED0bTJJfYfW\nKijvibRnxT+ZICfjwrL9Cg9gLRjVVZxaQqKorSk4ddCQF3wa9ruwh73K5fudHbS79Be3NwAR7AxI\ndWRR4l27Q2KfTFKbTIs3eouXEu8UysHbU8p3WNfubqdzyl99g3t6gYpIsZST2dTOvzd+ys1e7g/w\n49//OvXs1yjYejk9hxbfRm2krroFB/Ipt67vV0gZvqTbCJo78qPjpbibbv+PFaPUyFzTv1y7qtJy\nyz8ODChI5IGZgV4VzpAYp1W5H+xAkBXE69mC2vz1YDCCRt19UC7yX05OmZl89c6BTkp+rDZeKPr7\nUCUO13f93VV6alkvDLd8PbXRANRaVwky3JhiJZZkik2bMuxp2PxxbyB/u0eFnuyGcaPHuc6Q7JuU\ncw+N5xPQOS6Oj/okSmYSNKmd8y9S5SjMGpuBAWJ73FBgAuLu1HzE0vM0P/ic40/AOYlMosWYLze+\nGOf45sy4D4Cieomz+971OtVyDDo1dJzZg8l0KWCx18Qyk2+gYfeqFsfmGHRFOGO7bVJK6tqfqqk7\nOE9gmBNF5p0CpbzuZI5iKy6OazvGFPF/vbdl5v8ACjUlGuT5aN+iKQkzDcrXKZXqRrdG8ofSwf65\n/ceBlPEvhXrN8TMbQnNkrRDJ4JlkQYDnMAdnyp4ixcDexlv+p2LOKb3oyxLY4MQcNRMGc6Q9jOIv\nT4dJGPfw57kcZUzXkLy4E+d0EWWZ/6q16UTO14Gw7FoO7+y4nXqvMd4fyuR2zfLWAEVWjjC3Bnbb\n13Iqf0aJu3odAhENJzsoG5CS5a/UTj0dRLvQ1LncKXROyQvk8Tpq1NGpen7DXOiUDHPGG+kDlwG1\nBoBLb2RmVNuhv69II3o80PUWsnM3xoAwukfN+nCrRVdWuM1f/HDYeeAKwyQRL00XW8FaDFA/Pn4Y\nBvqXgmldHLNkSj4Bg+DibEOGaY14P1SboGh47VFZH+ReTLDrkaOBnZfliOY/A6newWWR85bC63AN\nFDvgETcLkIqTqe8WesIQ7uHoIdX2FPr3bXvZhYDhNp5Ugtr3BjWQdNdjWqb1vnsdBH9bC89sc/k3\nUbJIbRciCxxD2zxzIUfWm0l1WXW8ahKh5WA9dD0xrTDmGRyy0GcNxlIsxUqcfWPCago+c61R1aym\nE15o+JOg/0W/Ax9IQX2l7kWnG7bpuP5KAzG1QIRhLT7r/2OwNve+udQjjcgiQ36M0A+GXBVQoqIt\nILdD2hSbBqMwUrMD+T7Wnq2Vq4SV2tLoMxb44R2j4Jt3liQ+l7/gRx5aHDR5uSbKC53PzS60wRek\nGU1gQHYzc6s5Qv+sWuKE+khAPVhr+PX4vYmtp265CPWA4v0FXAXgKYHEQ/J4c2mpaoHhBcDYrZ4t\n9Q7WY2zvAe1WzfGEKiyuZZ/2QTVw1K3rCrpnDsTZCqr1NZhcgW+SIX7x3RZbnl1ZHP4Zs6jG+9pJ\n7LBCtXu4irsuYg/acR/esllHIw0wYsmnN28A8gffzUXAZhJsa46Ppbs3C0kDAWvM3IIqSF21A0Xo\nZ1PIzYh6KgYMlXL/FEwXOHOPVmb9PMj+FLQHXzaYQdqnsOZLBJRmLuomGLoWy/xKYZZIrrqDjCHE\nV0V61iBZnjzUkMe+G5ZUb4uagKOXzGgL3ibdxnRQh+Ua6VmrWDZiUhbpvTEiBLk49ZYsUoM9AnyX\nZBrdSwbYslEK1bqsEgV/3E6dC0+h5+WHbnPGySRZKa25fFOnZFw9NZLZkC8AfFCz803ZS4/1+53+\nPfe9F2PJ9DIOryNvqOsdZn9ekAQVjoOSpdS1lONEuVRSwNxuoxvvH8VeXPcPGCW3EQHn8abig49r\n3M7xnq0nDMqt9y686hXRMKTRw1sl/2AKapxkF7ly6lH0YdkHeXsnTRIlVydDtGxUJblmLajxRrsp\nbflvu0x8QC44PeMc+0bbIddF/9aeLyAaWaaNg5Hv2TXQN1mYPRztp3YJnFmhF173hshaNIeYFXNv\nY9zY10Ac2nhRq4x5kdlAh2f0LcRYSbChZJXHgwBYfuuuzp4nvicr8mpCXjfgD1u0d1pIXb8th67t\nFCQjyGnHAJMwsmK6pG8KXd6aE2TUGawaONQz7dXD9ScYS8IOX10y2cnAjbnxFMyNHOG3xPbafjat\nGmZJusUH50EwzBv4Nd5QRNW5gO69J8vAU0q2eVjviGLK7Ie/BRx1BReTNCjY9RF00t9wiINUXjrr\n/hie5dsgiInbaJuBqwmbTiyY2y6QY9NGp+h8gAhSoAwSMigjk6PRnt90q9vCco5HzK+qDiEHHCI+\n5E/var04RkYqFSWi/3ZoyKPTXn0R4nQENbgYbvmBRKVEoDAp8DM1MF9f5OSjuVpJGWzx1qm/ELiR\nwklfWR1xb7rEiGU4pTbg4Fn4RxxCNgRqaWeJsKQh4X9kj3Q2LniB4siDaEj+q2Rgu56fL603PCpy\nDNq8M3Pwt1d/sjWDYa+W4aMHXy/gLJk5A3xMt7J+aSLk5+zjIHtHX250bvBElcTcVmk0Ocweb8BO\nGplz6tN0HY25SEm+1U7ZQ7K/f96xI9hSsrK9BnkmdXRGc8YOTm1Xfahe0ftDFH7TyLU9nlCkfkza\nm5DdFvreI9ujjEPlao3h0IL9CYnP5nXVQcm5kKsM8014shII3JfWB+sJvOW2nTe8yoww55kDAlRf\n4MMfZIt0rZ/1fFVxB6F6fjsudvq1K8/Fd8qOJVvxgbt9OeoJ75rEM1mWDfHj36Nbw0lb7Ck8PpqA\nPSL1FlkJ2d+++SrJFVZiW24R5A1CD22ZaiOwvgBDakoNmGzVVRgcGo68bojQVasyuIR9OWjXuWTj\ndqnEjd37r1rxa1YkvPCfQ80e0VCpvuW2cHAHJ5b3GumPT2sI8jNSB3f4Ke9e5MKWCp30XKAnAnr6\n9JvbWxQhHtv216IJ4AA5W/a8kiOCsVCAJJgYe5TzZYq8a7kPq50HfKnHv+IeeqOr1o+0GWCy5Ec/\nv6GglmncVGIkJjNPeMl6+w1zXNhWSLei4SKIFnUFqQ0Kt5uSrislWGH+nLuWk0Kk7nGYNbXjn8lX\nrZbu3ZnRNDE10ANGvF4BFCG16JbZdqvozKyd2VwUeCD6Ws4lWmnZI2ePoHYSG3zb9t/2eGFBDWln\nCxrkYsj3zoW1JNMIkwH9FEa0qHHuOvPDsu6xNxDx09v45tWSLwnYD40+oArKSTHCqCX3r/JVlCkj\no8YwMC0j57enVSm4LeV+mxB16oBGuZ/et3HnQESkGv+yY0Z5d2O7GwskFmhd6L4fk6U3vAkTv2Sq\nwkVAqiSn5kpWfySPKEOa9VUDmIeg3cBO896kibTK835Yho8ZN8q+xO+MgrIXfwMceSeVPRxesEKe\nuOXaQNcVxswn6HANS8WStBxb5/g3PMMx+SA3RKhgRS9OHChSIbwMcYSWznYDzNPVr/7jY0hNGpZq\nFWWu1ihs/afAON2dKYuBH41CZrjX7xMFH0ba/albPNfkyI7oLL74d5H1s79P0bLTS1NARumKajZ6\npyQuW4OJcvseI+l53Xkd38iUnBxQRbh6OTVTn37iuwd0ieYGjiZR3pU41cg06zXumFecbFLth6Pv\n2K2hzPEA8HmKBaJTFLOoHlHv+o393ukgeThg4LVbmGm7NUZfa8x33TcwzVn44G7DHGwvUBhk2Ky3\nBYbteQD9SfPlG4znEhPn3OfLy1fRTyjK1rR9oCwTBHAjhSN9MjGLfvUS3+N+dN94WgGcXQ7JIBFu\nvZ22JAXEdm+lvIwy24tVfGs9XI9HrFxAwHyMQcMekJ8Ati81QNNoTFORhjS2OpRVWN4jYJRj/9vn\nOf6BDsjsiEng9WJV6YHxMuoj6p070m1rU1hS2plIIyEY4CxkepHPa3gMZ+XyEJZ/QU0zU5C2TKTq\nxqK2GsvjTtWP/Phuv9w3QEbU9GZARFfPfSWdObjOZT9lakPt3md9rbHAjsNmSFWo6C/Gpv+e/EHb\nJTeNE3HrHKJcbSlkiGXjCcuUZgyR1/nxwIutBX+imO2U7DjLzMjBUMMBN4b3ZulK68UDb3u09Mxy\no/7BlmuzdmltGhh6pxkEkTNcjASIgsow6vsdN1bClk7ZeEPE8PMsp2TP0bIiTD3t2eJyNbgv/TAo\n+mgYLV6ofVCSOg7uRNa1sIMbxk/Gt2/WGYzYt7UTOfEEd9Ew97Zrp2EAIjaJcO38d0RmV2fUFZ6Q\nAY416TGexs0oGeR/Tpd0SdHz46g1f+JuPHel/R9S/gtL4dMM96hVlRo+EbvPnUv884s9PjxnARq9\nHa9+/3OZ2mL9so9Gg1atlgxUzFpK5Zx4xe4SXRjuslGkC8HFLy1+29eqRvnhgUlHgv+w93Ptdfog\nnv3ruf2iJlyIv8kHa+1gXBxN4+zsqdpZ1TF9RebxQ7loeqInvDbhL6ekwvNkTCG9XEZ3Ion497ia\nychZHLHV3x/MtOoWPUc/D6+r2MocIkVXfKwh7d03u2nu3AeoEK66wVml9MMTXQUixsPC1aT2LuQI\n5pCGmP7HX/9xaTZ/enpGH4x+2wyD7dUdoFUtu6QHSfCfSpG6jAwU4Iqm/oIrLNKrz2WOghrzy25I\ngD2mPOq/mz6sviqPy5WVITHegpIn17Su4OEpOwyn4z1zHMsgKLYvdWvA7tmbRCR6HUEW+6uKL9Hp\nugsRNbaVjNUlyvNSyxpLZelcWWEY44aklFJTyH/bIdp5YGPJ1q70i0ZBGjNEbjWwTkLwcy11dt6l\n4FIR6W/YLh7PKrS/0dkD1in010ffuvvbsVGlVyn88lVY0CgJsNSX9mcNvaqurs/VTcAtCaI+hlY+\n2JGXl+QV2XqOeL0bViM42/7FvSxQSBgio2T6KZHd3jmQh55+fkmcMV8OpCTGRJbQOmx+kEkf4/kT\nV563PPvZm93lzJpBgBZ2grdfCiPbUQx+WnkdLEuxL6pc/ydoZswLoETMJHWHaj0oWVych6fleXa+\n0kLlskh/kzyixAGQUVFM4SZZuCFk6YMBnBvzag0nalQKp2Tw3CgvmJZZln6Be7/5uIToMp/HpVw5\n+R2Q2pN8O1SzYRDRcqJS22dbAHkq0DxExo428Mdnwaq3B2XEHf3PufDoQy1aicdCS2XPzMMmVDTG\n1BEpJdonZtNbj1cVrHJyuDBGNCP/lGFK5QUs573iu/AALZPXzj8bWdd/GbAxvKrBUrgWOwZ22s1e\ngDJS5YSDUdhV7/jE0Qq8GdbvusXhi3yDZoB2gWFen6VTgIYNJB7+YuIIqUS8MJZ12OJkyysUGhhm\n6yP04pj2Ns9ejUkMViyc7/xUQ6VjIGL7oEWHqdCUqQeJmKV5Qf8TH4PYIGn3sNdlVG/zKGyWJqsW\naWzq6NiiosDdO7uQrqLTcUtrk0+ZPaAlW8RLX1PxANbfhTexwaT2uoxE2y9qnFPvatoaI/O6uehn\n/xtlsgvkHmUI0O59pw3NTqRTB5cfp+i+Tsad9nek7j63Lr1OZzri/wJjqT5s7kYtDRWQsffqDfEB\ncG0GFMIa9XW7OGFMA8/6jVCORbjYYQIYYsC7SikNocvFpUB929ND+kT/yJvgiJ45995Ww/Pn+D83\njhZRoe8gteBaguO4nTc0qoVttgZMu1RqNf4KkwI1vy0K+iPoxaEHFUR/aNNF2h4zbTwHdd4pPhuk\nFSRTtPYY5mqvB4XNnAiA220ZMb7i9lekpNAS9cmXqOHNKBCVqMB3NqrfNhEpIXj8bHLRLXTmPpPX\nGr26Nb5heFWHmQ8NHbGkSk+X2UpyUs3mpvMG3x3GBdrxKMj6IKPKJEhH2X8eJeZOudoN/nb5qtUI\n1b++CeUhxxRPVgUquIEWm8wuWaHzdZ4xr1Z/T0YF1gEVobqdbLnc24H0bR+tc9kDWpojUDcXNHus\nDVj4k4Pe++nT+3U4OvxFmMZFUVQNquSOzfN9m6v5BYoPr7XQtdO0Y/eNg9h3K7DrMwUap19VT5Mn\nvphlZh2yNiOBlyfUTgJ4G8to/XtZKM7XG40wa+nRW0kk2N7FD1PNEf+hVHk3h7vCsvwKil+NTrYX\nKbU4UfSV4lZpXxviy6Lg459+QjXmAjP7F89LWQqRd2zAn+tCU6Ulrjqnuv49Set8VEqpkAgZgugm\nefHMCAYsTlD98sR9ccdM/vwtjg6vVO3SJS8DIispHF5CvYQyTVA0tOUWvTQK7n9ftB5eKztKU94h\nEzm9lOL8L5y4zO8bqpFtkvSM7TfPauSP8INMn4vM76hNkNztzhVoyLxhOFF6d/bCjJDZ6+/oHUAr\nsiCxbLxSZI5Y2wyoXX2ntm94kydgDvwov3/QlESxwcz0q2QksN2s+82gQejpCA47yxkzH2kAOjEz\nEHRGAlUsGMfA8Lg8xxO9AbAR+da7yM8MuqqGU5cfuvw8zdhJXeVaUdw9vnw18Hv3H0fiMn8FTIbE\nEOPefk6JTxqL6x/gECr03YsvnRSvyuskvMMODzMsAIPKh606IGexIL8czS+SNYrGN6G8JgdQlQYm\nnHiVaJdgR6SWOEmu/h/a2rI2ew9+uW80Yxrqk/RwVd6f/ZcGN9J5/jUYR6GCNM24c1dSU+FpcJLB\nDorNRA+z7iZr+nAe/wqXVXKA4jwpDyrFu5yjiNL8mfwGZaeRcAyfywpZ1LYOTwlSigPVSX7Gf0TG\niwanieOCY8nXQ1xVv6d+eGcJ2JRg244zy8tUu8a8+cy0/1MstSX/v2P2syvXWM4DRRJX22yHn9DG\nF7wE3dIYDWE3qvJrbXnz1nRbzpUF5oQT/8HruQS+3icCAaZuUBBw0tLBxDGkRcwF7Afa+DFfBJ6w\ntMKvZN1qKnEagghGxNM36+NzUhaEJYJkHOpCIuT7+Q6iL7D5gnpLt3jVTdmtfED/LG+hzELVL5Yn\nSCDP+JzmTNhhfYfvx+vGIEJF9Y6vfriwMLgvUlfubo9FQQPncEjG2YoEtRYV6GMPBjoX7T3UVJA8\nMMgE40Dtp9YypHv5GaQZtIkjFeLSohtc7ecFhYkzHz4IbOcjrcl6QR8DVQM/J4sFOvw/wQDxvGZ+\n1D2LHYph0yf+LhC3l7JPDu/oSRFh3Q8L74fEwqGx7CCe5vP5HBeR478sUsvjn+pSmNCRY4ayVTu0\nS51cBZci2X8AuNB8Xf/E54RIGa4HJtTN7UpOjqRaHUdMLfrXowbjprENI0SSc42/VY3uuUCMhher\nj6O8arEE20aqydzKGPOBKXwQFbEDRMeoJWv9W4Mm8o52heIkBjHR3lLOupcK9TsBpaN4Fq/6qZR6\nq/JVN+AdqUb9Sbcty0VU2+DjxN3r5A7/ogP/T6s52dINPYcK8gSkb40FoHJdPfSfJrjZJsGc4EB7\nOEZJqI7vBHtgRWK5+spU5g/AzSu+P0jSbNgCnyKuCp3rgmqeR+KpuGRtVgAonfgk7vkum+YVUvUK\ngHvk2jr+z0Mpal0mnL8IDRyVMkkGyMM6zPUuBpJLDQi4uqXCm443a7fIyrqpunnImCJxWV17F3Ua\n5kUI0gz3vMpCVBHbrGosFVAcHjN6ioaW3JBB8Izc7PLrzFz11YGvpxURIbcktPyXK3wFz8ockzjP\nwuhS4Twtknk3OoqZUsssQBcVQMekcb8Nej/UkPoXG0qpr0DDXbBNX4vKz9Y+nKXWMUrVGEsvP2ym\nxmHSnKTe1x4UkYcAHRsOH4r/uuQLlqtnfYiPGAbEgyYq7m7zTa2146BeOLFaZjYziqVmpIS9MDwh\n0qIJW01F8UCM4NhzxSYPveG+uM+qSdNyHRiodBpzouGirYI/5lKHBiRg5EmIlAj2onYqi+8CnVuD\nBEkTzzIKQTeSqCjHYTFyCxIaFrEbNcKxi4yGZIm3m8TR2pTpkQ9HvwINfLhcJfzILnm1NqS1CNDS\n3rBZ4dp+RAG+R1wOdyPw3HHRKzuZuGF6d+2FtVAUAzwjicitGb36iFQG3/LigT2wj3Wkp03vgNmz\nTrsk5UThR4w6hWSP2Z/QwhiBUIcaCBFpPBEEPjGFMzKd6XEfN0EmafwfZfYKpXmt7mMolfgiSmN7\nkjnTYpvtgLlzh1Ra9PhRELpzyaAVvMw97OyztrvCJrPYtPiB0WjT2dfGY2p2oD3RANZh4rmeXvPR\nRn64PPFCb0S8Ijo+noCt0/0DurrBipQ/wT9Ed78lPctfysKMrNIA1gpr+ghglLr2bA5TDCOpDT+S\n0+cV37/YbPXHF1Bd0E0SqanS8FNgnog8PZSds9ZGOtxR4v+0KMX/CVaGObMcVClmiCnyUDlV1kCK\ndGYQTQa4cp0we32RahIvwzzTjNjZY5cFMdUyq2Fm5sdzBrEDZnOo9CRDI5Ch922QyLn1VGvXpJ6+\nawRV7PBQid4jKLQwXobwflrtAKESN029hkpk6zOc5vcqYlEPtNlqvROaIFwQfJNu2DlL+tQIr8JR\n8w5tyIuxrUP06uOiID125cBspXtXfRwL9d6MJmHzfDGUxRU0WV0svU3Xw9TMWAharWScRY+KGbfP\n5KF5kLG1T2CZFB8Ct1ylkODzljLeuuKc1GH0KqvcMqFDIBZFh9S3WR/uiqXw1NRaFJvGADyhPNbO\nKlPNb8SMnT1HisuYWFlOinzSRasL8txNazOu1PfPXyS8tNk8ad/l9Gy4YuZaE3HYDSv6+erQC5kl\n3gfsYV5jCiuVEXFvkJy+BxAhEEZHahLY4kivhRXaiNT9/Tl5idRx/BkGtN1RlDEECVCAYjG30Cx5\nvGSvZlcsbhYdp4WFtiFsdUY86IKMiEkrrwsJvlhNy9E0xpnsJ+KBwKwPG8lCxxnqRfXRC8G1pzK6\nnHoR/oPfx+ZGgDiiEaXEWm/QUuKL6EYSAUmQXj4Kbs/eOacn5GrsuWSm6U0qTtNz6zdSPn81E3Q9\nSZyqEfjpcdEyHVpt0WLh+XBv5OFaci2uwGVak3xTLW/IRjuF8lejNdTkhS8mnhZH2CndCYmIAKmX\n7+zaS38k0JdikpAu6Hmnffj5RAK9w4psy0766O0lSpB2dSwRjPRU+nDqfDyXR5vsyiAJga5X8n+z\nPjBCwrzpMe/5evFkDpF+vERuad/J/dNdxceq2B17VQna+20OhGl7Z5CS3iorcpltKpd/+CupY2eQ\nQSLiguHFNc88YFcwrDQQEl1IVr3aH5pZDfOuLzp6c/gi/rCVLEu2aJUP/kF4PUKYs3viTx2fvlQm\n5fMPmz4BMByOA/+aGXwUPEoEaLzsDFJ/CuotLGQ2IBp+VAPd0e9fhOZWi6hjbqTFU0ep2ECUXBn4\nL8MTaBVGIS8itmZu1r2FfUdjza7AWs+WcJaVhHbKJbU32XmwRDx6At+5I5HVbJ8R78/2yT0UGOVu\ns74az848ajJaCNNFCNbwr0ZqPBfwNecsIAyO+oevIryFbCkgtHJ8s4DrHvsOxrM7r3SPLbDBbrTI\nPV2erTpSvk/XOUtTAw864oEzX76PBdH746tFl96CdqLYOXq5kd4ssqfUHdMSwl8Jv/SJuD2CWGHv\n12K1IhsrXw4TJqENv+fEUfSOstebj1pPqMkDC8zmYhHM973Vqw29tz8ioyMF/lGPu7tE3N3z5So3\nGl2uB86plyb77St54IViQI5Vup1PBgYtn7hbe/O7vqSp/HlJauocHcUN0mWAebC4QhMYuIOTIo/F\nS/ObcsaxGeTsiXx2JPMYdpLYyO1yV89mJu1bkY+ZRUADAi1BH1t9zDFWf716ntCBeRAFhl1W3AMT\nTUKIBx7uP3SYRxiihu3K+mW7yc01zInHtjGCVHvRkTR8Y7s+T//lAB03o8RlVyEcRdNkmTOz98mc\neG2ieMoOyWvpi2JD31qN8HwN+GDYZZz57c9gDOolZeQE8ixyAsg2kcEEMzE941feENR9VYXBxUmN\nhSselGDae+GUiHiJxuFb4oh4FcBin6YBMnDzvd3+1HSppcGFbJ1qC/eXBHrGBbWNcj0XuxeV2ZFf\nSskD9Uv/Z57OJ3lvPpbBzW35siiv8xVtPn+mSEBkIFrY9zz3fKIZIeaH3zy3BcREofa+Bmmqwec2\ninuvUyDSzTWhE0LQ/gNV5hnmytHd1X7e9daJ2Gn1lmCCpev5AXVKk5/Rywy89sEb78T5JC5BheBi\n+xuP9tHskv74L9hA5XCOeGKRl7P9qHg71i5Ihg1NOKoxmN9SV8ltfiCBG4tQZwcyyMYVnoqa7NYC\n4hvjDVs5FvQYbRNkIfEnvW1hR/J68CRpnuU5cv3RKgPb31TaYXJInyOpdJ2pj31qYUkgjOZ4v3YI\nQHKLxgtWVAfunePx967lo69QwO5uba5VifPquLPsbTKu6HS5AAAVidTmvdnISa0Le4syaMWGQcY+\nS8KbiTiXypI4q9A+3B2xIaqsXfnML95xUIJ5gs1TRLQ9SLOnYBtbTVDb2T643XWFje91jWq7rmr7\nMEkr/pLk8oeYLvVU5peL99PfKB3sfH04WrejcXD0F2sGmO2dcqaaNbI+1Qf4hvW+2qpfVB+D0giX\noiTJjchLalymCv1watprrDEaKgs33RuG0NyHkxbn8CYU0hDHBh/59IxZYrDcYPWJuj4n4eZ6/Pdn\nFazj+eyH9r6AfZP5dwMJU3OiVR1uoLzE9Nnqd8gKrXZ7QN5BGHhJqQHUwVdB72pDUerevt2uP4f9\ncfiWALfByK20GuMn2XMHLw6peyuJhK4JaYMPnw8QRiogKHJOJ/R8SX75H3XQz8IqEvh/vifs12fl\nAHhtwCO7DwBsGIC/TOi/h6yRWQHMTOYq/Gxa6MS9EFVtmUkxnv0AHPd7RIMM2F379PKh8MszmjTq\n0lxkw4nUjsJj6nda5WR77+AvxXcNYXSLpSpow8vUdJ1wiz7Jd/QH1T9k3FrXGrPtdmyud1rck55+\njfixo2zV+c4Hzp40SH86+nvJ1jv0efMt0sur/96rkqf1Av4L3xRBoDxdn0mDMB5HZXNBbo4aXsxI\nJhCVX6ezz6uZA9b0ILJ90ElBVBqGtyiLFqQf2COiVcISLMR1qhSMaDZ693E3vmm9+vHVsQphvS3H\nUbEV77uCp9zqgXE+09chQ7LWuvSfjuO9oEF96OfqtW2670gvXtw/XUQ6y4Eqab4HRJodMmoPpw8x\nOJOqO+nn4Fyob5VxqEbvZdJILEiWevWAjXb9TewKb2DIqM3RdXWfR/LV3Elvsa6dqASEihNWyU4E\no/h21QXKBVWcgBjbEH/ZF2ashyW9v7WcqQJuvBCfT8vXeh6xz68c2etztg0XjXDvRDtI+lCRhmXP\nE9WORpfPUpWdAlZbAkNjupBmDN4a+3D/cEqkVqZNMT5LbDJPPBcqc5fArHAPccvLsLewRdulJfNy\nw5O0En4CBNJDL7KvAa0ZaS71HrLaDj5a/mAeyj1t6uVnbfYk259QvmY195fwG+Asqw4Nx5zKdpIS\nDnHYlV09K81xYwHzrMfQeMdzGeWs5cvMuxRSxxrJKzYCc9V5QZgWV2NdgYgQsOrs/CSe7n2ib2qM\n3/lobXLP1hXR6DUW9oPnF6HMvFzJvpObvV1fy0lmp5GLdcd3IgGNnYwQOG7ofdDCyvd+08JdXpBd\n1eU1CwHYwr/kgG/Q99N08aSxxb9zDWIMEYbNxoaodVtAhtdK1/kWF5UNC6XRrYeWKe28wsWDuGLI\n1nmL4AxGKyUzqGgSOmkyjAtys7Q0JhE4X7JBQwWLASC3bHiwu5wcRjBdJCpBnozWWClReYIBAC0C\nSOPmue7WY0M7QNrZkPq1zAz51kG6B16aMDg9V/1kjacJL344dXmoM0f5x4a2uv38EJidhuG0TJVb\n2H2wU8tjCBlSq9vl2hCl7NydKzW/QN94wDMyabnXmyY2hyzrYe3Rqt7nY4RnFd9fUjzarVw2TIEb\n8QeLp3meE87Pa+s5SV5c50ZH6/UC68AMJc2loxvkA5r6Qlc7jEdmWqiEyPbCpKfGbvmu2ZWblQ0A\nDPxWxEa/mOBUgHOKI9ZICaYNeF1wVuDUlJohKEkPFQ8hj5RvRFehNrjjdxyXL4xZKr5PxD/CSIr9\np0pT8jvr0XkXVKL2UcxRDxxfVEkCPoCoXBjl9qFQYY83DPQLOcUthGYSBJ4AFas5c0AZVp1hvkEM\n7lKEh0iSbkPMgg0TUSM0J/dNGumfZckksAe7ozGWfhD6XJI3kHEDq8ykpgsK2xHYE5hElyDF5tNE\nwj+ywjHk03BSWcd/A0vGrSALiStaoAb4JxtSEd29OAlGn1tN50E1IYjFpNZIcxsvSn+LwVqWjcLP\nW2UUknRS8hAgnkIgS//1N0wUkRMHWNcYE+JwvfDaWEpx6s+ni44gqFkURTWjQ4VW6CkAaTsJNGRL\n70z6Gr2sPLJidFWuNYRO+KJI+rFMfD521fmerHlGFXQSZJMXcHjeC2/TP3Z106ALB4ZZGFFL4fFm\nklnYacwkMiTpF5BtC4gu5MIFdyupdUKEIsyfQZUTnjU3QBxw0BCQSyeGts/EOhBSjE9K5CEVX5JA\nQg/Sq0wtcwFvvjFioi9UPjgLF6vzM3Eo5XlzWYUPJVSYkpglV5vceDVs48UKLsY8Z5Ca1sxVji2r\naD3ZBSLYxs13pq7+3dIB8JTKXNQqjDcsn1ivSpA+3EeAUkozm/4Vl33q+PzipvVviiR+jari+w6y\nrKjDp9R6xmlJhDxLiryMcDAKAl0S5tYgvua16GdArNVO8Yl3jS8s7W8o8LoZ4G63IBZtcDN/mEQv\ndsEvtFaWaodqhKCjLAinM1wyyYDKTNSA1RYH2DFXqa87Z+C47uWV2ENt138JIO+hK0qGWrIJ9LQz\nO2AagnUaDQ9rnx64ZESDndWNWMt781t19V/sylJaCmTH8Sbv5UjSaVWUAKfnNWTdDh/YMSh80dJb\nGRa+wLq62AwVd9wHqmAkdP2Wl+1Kc0wHOednICbtpA57AvHuBkcBtDKPLDNETSkESu5F6GZUuG3L\ntQftoP75qS1qlKRI5kfaHeRxRQv3WyqlrVLQ0LkNlslqJbwh/Urt6WQfzw8geKSZewMIntNh519P\nZOO+wUhiRBiSLCxS1n7oFo385eNox9lX/jKdhA+wEZPJtbq+AE16Ig1sZIgBbqAbAj9aifQN1P7R\ncNJIJ87mfiUCBY8XTtHjEWLiPzSeiyz7rNvfTbXjUL1dJGFVlhZhPi6zBkAVDY8lEUDXl9z1LA3q\nFw2aJyz8XI7ClI/HzF+xZxccIOQ+hYQwSlCibN0tsNJfTmDYKUS8L1EhhfqLx6ypiYI8hbCDcol1\nVpPLdHzmYvRaBM9fOZrXYP3tSfQS7BdiGDupbC7h38Oz2aTmMsd6GIYwrJ4Pr2FLPt3T1kWjjCpf\n9R355H7fvgE5Uafipd22bNPLAGtHdOrKpf3BPELw7dB24qou4qCevYdDgqIY5Xaf019F7HCJ6KRt\ndA9lv+yib7hHUUUMGIGjvieT3kGWya3qYfM1Go8hnL5kUIVslgq2hi+pDsvVVYeInL5l1A+uhkxq\nq7GZM1GguyUk+Efb4q9YjAbElcXl7RlLdEaKuCyFFpQBwedmRIExZw9s5ja+ulD/wwQg1594RWM0\n+w+ZeEslbG7kSNhT8TVHCl/o2Mj+nRpTqrp2m78e3uU0cWJ4wtW0rs4IJq50fBZK6XaKsxAJkKO2\nvZIq+nx9NxvPfM1okmBAIW8sEsqatxyNZLGUbK8v8wXxo5ZCWDPRGJDzq2sizFXolSpE2NCp+8TQ\n6IkX34esm9JL9YsW2by6RTYxUBGfm2zzCUrpEPto5fv2iC8/yW37Ciw5VZ583AAR3iVf2OmkMFys\n2XZ+YTeQYH2B7j9DSKBQ7JjVf6cVUO6HU7zlEEbrp2UQwrXhXgggxQ52IKFOPVVfrO2qvpRQlEbH\nS2pXlIHVxJI3kPAjbVCsMAtcaqtHIKq/QQVs77yXECmc7rg/kB0qlMtYu/yWF9ZcrGgC1buiSFPv\ng7RhtfHcCRQclyzOMwvDZmEkeIQWHzIh8VrjZAfWgiuOpxH2Z19uuCnRptjbiexTm0UdLL6ki9qh\n/lSgfzdc+G2S5SJcJhSIdmoITY5CJhe8J3GU3Nfr8vkpovh6ozrR0axvp3PIwRupdDCUnQYT3AMv\n+cmw7lqJOb48sZAziTEOeBDslZeiu+Rs7dgFLFppQsYZ0CtBppCM/2iFv25wFs06a7n3HDRhkeeD\nKQqfaJY/19WS/92YOotMkyzVT91l3s9Vw4OHVIHiSBUdIoaS6Q0TmJrb9Pd6pKHF7tGCxvxO+c6y\noxFNEy6aa+EXY7CD2XZvboKfOoGVC5VnZn/SRbI10dg25PB8C+kznajFdODm9/r/CxwA7gW6VWX5\nJzKsXMVdla4sVLZ6KRyAXO26eiSFsRQ1kJzs2JJU2Vabhyakt+azGEWHUh+/CFhu3WukCJMdyTht\nxEYP6nACWNn9ntnVGtrYcuVBTmS8cBJwmm1DQoI1JAI+l5NReO61CwzQuL27LqEDQI8gXtk1qv6i\nVxlbs/gvHD4/9+hywHZmnIHDJYA1Bh6bbhRl5cZ7iuu2AAeWVJ+AP0vvr1KNi/MiSGV8P+GyqClE\nozlrRaHqYZShFJ8wrToe0mcxHMrmusHcAvIOihlUy4clDwKAX9PTH1QU+tjY+SxokKqap5qwiwgF\npb9EJtQ+YBZjbi197sYjMX/IYfbhpNB06ND/1NRuVGy1s6nrF3dirIwaSl1wAHobSuquxcapbNsS\nTeb9LZccL+VYd+DV9V3Et+Gd0q95H03vWPg2wbTY71XFrKX9+ZnQFJxY9uyRvYK8MvPH28uAOo7l\nMivdwHIvLDhMff00HzhHduEPuNXvu4LMvfg4DJqoyW1HEqUzwJBGU4e8LI4n0UzOwsBaWte1Bi5u\n3wJA1uzV+n8Cfejgt0xXr/yu2qw3Kn4wHDwA+bGeNINyORK5UaRrHGktOwRxcp56CZ6BhFhH217D\nn4QPp2FIZ+3LfKx9JHQXY2F88IB6G27VuduxbUYl4viglFrkaxky0dX745qnpQxEzQTVliBrSc18\nvNu1A0u9lIi2ZT7u5BxN1HdOTf8rgcyATuCIeWVskgz+EekEw1fYNQLmrh0GVZbDBTLljYjOrliK\n7FiAS2pyRSFbg+t1BidIdeOJo+seEwC3ixSRgRqEZnfduXuYYeXQgmGGRyXj8c9KevqNHCBmHyco\nhZ2fql47uj3lXZ4CEtyOcwZAg48d2toYaz/VhSY0Jfq4AVbuDV4m+FnbFrtUky+I4+TNFVn9sKrD\nH3vB62+b5YZ/MOd2IGwfiq8pDPu6qDcrXbXb+qAeDVtmTcBVRPIfUYrWSn3QddJZxcQcuzSjSCNL\nx1IkSO/GbX8wrz3nqFVXYTBymVDrApyr6TE8rvDZSZ0CzZIdmxMYukpCM6AC/hfZ0ON3/ETS49UG\nWMTFDCof0qPqS09JwrLNOUZT69meNpv3UFnGZJ0V6q10Uk3v/9/Wpgryi6efxW4Fat/uWQycmt30\nOUI/Y9wOTn60pUi07QC1oiScX9XCdd99IU6tkxGdr//f0aIUHim9DpNKk9aOXNfvzVYFP0PzGXWE\n+sffIg47n8Ptw5Q/ObQNHNBnjGQLZWXavZy5Ody7WmGiueGga3AFmm4aCB3IVAvpJbELAEuwupit\nMUccg2VRtq/kXUjBZL25zZ51vMOni47PGpj9LBEJb6gUpd3tfPfOHi04N+oE9kBmTYVmGhFOC06R\nKp519cDXxr87Jzy9B/+WQeMVR4Aspa3S3WGyKqUOxpfex8DMgXYOHd88eej5nUO2i52/MMp9VHhH\n02p1gzHmGeSFW7ZAt8MnLSWSYwwt/vpXqpwImVc4GYjLtl+mQl6iSgrhSbsmXH3lzMfKR79l8CG4\nThjukTHmcjcJ6ppcawtFjBUmrhGqVh0mF1GyQlTSiQ+wHun34/oIG1NMnSCZ3EfdoKJXC2LrjHRQ\n9qP8dTlWHF2Ihw9nz/hoFR+WnrYfFKg6TI9/0sgSaBaXSwyiTiUWSS+LKfqw0XmaxZkFaw3SpPOT\n4PvFDGnEExDmRF/46Fr/9Pq0Lj8wJctiuqrf3I/R8LjxfefzuB1Hm+0X6T2m3EbFej/PAEGE0Cqg\n2YfnbNQLt4Etq6MeUir9o0ujuNlQ8mqQ1m2tZf6rZhLJ0ioKc3TMWuHxUYC9jWZz9a/7q8tjO9RF\n69ohazRm1ZNXyGP5Ajb8gWFXEr3lYxVGMw3IIg//GpR+8HHp30kq75kPYFdj0nYxvuQfdx/BhzGG\nHibkXsGpydnuP9Teh+TxxLEuTCBs0RxVgzzDp0FMteb49HaNOJhebWD81fmo6luScUcgC3rwhp8F\nWXhgcDCgVc/X4Asc6RzcAtRRX0WosfM0oYszLEB4qY4o8V8yv6JBrEipfZQxOkoMX/E0ElAUaB10\nFbZUnDL0pyEOrNQ+Bj+3CEwq+/VmQbAarXBJREEvZfYqhWFLaTn0mvCvPWcL4Rs0+13Ri7Ttzzva\nfljdsAVLZpJZ18Q7QVhmVYcPQfpCULQ84nfY8qa0oHOGvLM7qHdzqGF1ReAEpug/6GbWHCSIl7JI\nOPh5lvRuRKcmXUDJdyZhr0/y5ojHT2ZT+quQVp5PTZ8R/DEzWev3vbR5hxXnahOjbkpHhkzuhF8Q\nsoS3pxt7PlIH8Z7nOdTy+Jk36Cd/t+NfULiT+LTxulKbCJjj51oP0UzTt+UwGaxwlIn0xbCcdeuK\naAaM3w+bMnh/VqoFg0X8xwR0CnViS6d2+VKa6XpOYCQHiMp+a42G+YCcre8U0rLstzFgCS7b2HXD\nHquOS56YhURiKCeAQBsfOhXVDF6LZjEm//pb8iIlztjYRiyNTkCz3uMe/DSGM3d1KaSEKlTq0T0d\n/A658Ti2S3dK+yoecWzEN2Aq353u/ZXwsgwJRHAkTfcTD3jR7Az9Axc+lUoGKx3eXN1JSE/noLYk\niKFKy/x51ccSyP4zUcFaFiS5eV639VYTCh14RDHvRS+GffaZ58XE6Hae2R9DGIjfV/OrYjfnTamZ\ncYaInIwuVRfHXh5mumXLBRtcm9FYXUqDfqGtnCLn2rRtVgWANd0+9AVr0YSqc87/kziTke5xaCZw\nT5/h7PpuQha3qz3JJ/Rk+98VHkGaUWENQylBYwF752sV4OVOAFNIqHMtZtg5We0+vmupEDC6CfUJ\njVz9ShzoaLZ8g556uxLeCtOrLAfIVsUv8ogRH0dwdsvsNG7Af3mhSwLf7sN26cIDzjISpswyxIoS\nFw5avLasIFnFDFUieCdgUrgbFEwyXG+L1rir1MoeypvNzyJ8wwLSlXgd7DojnTQO30UwbJczlTRz\nFe4ueGmIISNM9oqaqSnPV5OKCZC79Ay0Rl5G6OpRyWQwL6hN2gVUcSTsn01fA49DMJ15dnOVhcnU\n+njjYXhSaMUhtH6FXu77m5qITyg2g2NXY1BVd81tAcfM/uthvyRNVMT0ZEB3KduBTGST6Bvhz8vB\nWDLM3zMGAZk6+FDI7bUKIFt7gpWmEt/yvzo9lEATLHhCXsDTKGnwcyY68fsPTWCn4/EoQlXJi7Gt\n/jZCIpI1LAIvZHAYH/fMBKiTZ2pUHSxMYWNnmV2hTpOIiKbFBZLjINyvZSr7ScKHKTKgQoMBdI9U\n9slUt9n+fTNTXgGP749FSfhEh5W6uCafa7mLarKOHQoudoaoCFTP80A0zhm+OKIE6KpxCr7oBt96\nNHfjqOqC6og5rZCmKS4zdebGzKPe7VTuUN7Bq5pncRT/94ULXntWY7ZIf91bL4S84PXCsDDoRdms\nyrjDF/EF7AYR7iSLUmbBNuBg2PJxKfnAhFRkG+S1Y6uVeM/KUIr2eNZFw9d2J+6yetAiEl40bOVF\nVvYfZRazQbhz9OKWdHzlV+CH+Brmc1bF3Cgx2hT8u4mQxVavJg4+GOQgXlKzq28Uy7r5mWRR0W+K\nwt3P9xidPC4dKDo5cIDz+sL3lfnV+OiXMEz8gnLV1iLLMPFDnwAxcEdyq5DZJOcubbKxFLh/itT+\nVykgfI7l1DCRJqsaeJtLfcd/Cb4JynKH+/bWdKFUtBsdYItwm4itnerPuSjegQ4hD4TD1KeLPCl8\nzOYytpFnLEZdf2Ux+e8ftofakpfyX7xDEbmZU6pZjGRYQ0cm5FbS0TEcin4PFSpUe0gzMiqDKez4\nEq6dTh12aTzbeLxbydriwhetg9lzxZ6XyIM9+llI/gymxhNvBNlYn+hVE40ozycikJ9EXpMH8vwS\n6DKe36N5R5ZAW8VK0/6ye0HC/ePODPI8od+EmIe+qcZA7WopsXpK8fAeIpZhKyUbYkTHcGSKzoq/\nmrmDvReqli3qvFVIWs9A0KX2OQ1OzE6zRSAPPD1lbbGiLUT6jBzTd+1O2RfBvCujc0PDIN3hQZIZ\nxEZWiA6XElouUEIZfYWe4QEHHMiHpcyN5Yp2bwfpVyTvBfMyxuI0uFn/aN2bxkC3EkMCeGQWnN4w\nJf23sDpOSTnZNM2Zd1ir9/yo4zael6PXvEQkF02HjZb4CaC0oN3z9JmHnkKw3QcLQkyqbsigOzHn\nVx3Z0GHJCHiVCGk+nGmFCsKl/qU78PpqIdglCs2dCI1f/Sl9+n7cCSAL5/6KIbgQ/4jCBHXgjc47\nDaKz/3KW8MnRR2u85GedhF3QCpaM77ZUZlTRG1VOQ6Hr9L9y3RI2LiyoZCdMrDk8+qcR5KYA37vI\ndeitINKDF37jXRKIkNjoYFIIzX+7jaVIKK4zInBwkTbXG9dER0Ic8XP/rtzLLyZH/Y0ldPKE69VF\nv0wP6sI4Pq2dojK13o3O0JpsBzOoqy78ynkmK+aEx1pJDVtfrJYxJv8U0z4Gn/s3SKfKvMBjgxj6\nNlRmMeEKnzNZzUFURaKYDINiQr44IWOs10Xpg0YnH43/fwB6eyhiRjmOS1o8EIKSp/ipd3s8t36t\nWpnvYigxCsr9MfQbI7bZR+fWYXrdlIhIAgTrjnvOJNSd43mdb1bXTvX3oxOgFhmcdjkUr3lxrjiv\nwVZvFvixjPmf6I2ETxmZi9jROEAZO23HiChR8vRuRkXMqq6Sci/VC25FHcOnF3dZB5UXU4sy+pQv\n0gBm1n5049Y2tikKsPd4hTC4yCL28FSRTTFgm33SDEee00b902IU5KIASf/1tpjQTbt1lWHM8v2z\n5CB7vTwYKUz3YKd0eJ4FrF3rzv9l+pMQj4JGQq7ilTHZvdOrzmSpfbjv58T2o1FWilUYWQUnHzja\nm9rDEuPeJIp4qN1MEMFJPsgP+np17sIiYNAzVBJF1Nuskf+dsgznT8GrrvYXFv4r/QqL3+w+uDoo\nN7aUwKc3M5X5XwrR21ZRRUFIp42XWoR/uOllDnEpOAs/S5wdnr/OmFpWgAeZfI4GNl8nCHNYy8m1\nQCgK9hXCvNJqjd+FSzkDKJrzyPUH5Uw/EoPlPWKYb8vTsw0KEkzYsjrLrnnDWRYJr4rZT51aJWN9\nzQ6XQiME8Ub7fAZN0zKcwvmLwYNBfOtxwetFvvnqShBuSbp5a+9VMb44cxSEeoHrzX+KjOcXo4yZ\nZn+DtSKFr4074kOpG8Nhdn1Yd1LAJuvTtWNuDBkovFG+iT9KDdWnDmL+lsKRq2poZwomyDroUjiY\nPLNAD/MWkYIZAqo79Gstsyb91v71BQP4aYtjZZ0igtOAsZGwLuioB50u8lSIgBubL3+YYsHveOPh\nhlYjlcQU/d6bIIFbbruXkcVXau65YufTQDQhNEW9U2DsuoZ5kUjN2vh/Ka3jaV/qgoXPFOiw3IhP\nZ0bxq2yK4ErwZHEwjZhC9Fh1azDa2CzR/IbNV0GvU845X4eHEDjgvGsyos56nO4P3w7weqEZ5Gcc\nVs2WOSPduAUVZ2wQwoDHeyf4OqVoyakZGusGM015VjHEqsjuCltAbqe7UaDGKuWfZ3T2h5Gb49SU\nKVx4cPSOrzD2KsdAfP65ZbsEJBEGxsW++jCXG80oge+6U1XDygpofVX3JAazTWSSZ4swNuqfCO7/\nB8h4k3RykWg4Q8+VVbkvOPoAEGm8WIGxiT5WVrxUIeUGnyGFWmpAIp7+YSt74cnG2b+y/svUXier\npenOxt2t2R5i/NPXjP2s2AjIRPaipQDmwiUQXu4Dvc1l6tgIGtOthBs0zQggEOR3YwRZiWzc/jsk\nsPPhRTcszgcY8OgD2u4JT026rkqDFwfraO3b3kyrIyq5rApwP+4uJitZS17Xpd92hVsANpDFHXS5\nZnOsYv7q0aLIF1h9pvs3VVTH9PYVpKiUSF/J1kTIoqvkLLjY5iiXBTmxE2skbS2tjAJf8N6wQcHS\n8PmMZ2B0Zsr9RIoDiWzA+oNaVmaHSSGNt6WmI/P8w0pVxv5Y1hRd16SrQfrNbP3Rv/Mypa+XOV+j\nnEY8t+kmMoGvMPm5ovJda7qTsdsDH+dU422qfsOa5Wsf2NiIPwsZEEiflRNTsd7bqKKeIJBX1mkr\nxLwRNgb6aDEEsMDFYjge3EROymVzcxaG/V/IByIg3LA9tVliS3Ot4xQL7WUClag0zp2+yy3Ss0Yh\nhKqDI6/tHFn4V6ZIdSegRM9tEo0mg80NmSMZ2BnWL9l4e9JDRlCj5LI5Ah4HGoluQ14bauDFY2kS\nCvGr9VCXd2uGXbic5vkd1o8a3dyz3nHcdPyvLObjuDBRKx19WGkzPU373QBb+8o63760SbfyszVa\nmCaI0DgP7iJmGuKkXeHT8r4ql6XlPperjDrs+H1+2pDMTjgHkTRXlHcYYzyBIjICOJRz9eemoJUn\nMK0j2OLFMVyEUHe/h5C4rp7uPLEQ++p4wMonpLUPTwxzwFSluBcUcJ5of26VMjZsUOY0DA4y5PNf\nJYK5o2lGyDg+4MIsWV0f06WR5Lwqa+bqJMRUZyP0q5TTtXFVkjPIjTgdjET0d8gWxIaohgfv3/ZH\ntMl4Bb8ichf+6samJ3s4WBoNINHdpcn7LaQieDoJrhsyF4Leo2KPJzEDWONym/UBBXgBNuidmUkN\n6wGHZWUAoGyi89ZYj5m8ZAhqHuBdH3Teba7N7bg4YVXIcNhv53VhBPRSSNGME/l1Jbt1J9GIPtq6\nQL2d2b9Qc9MMdDfRmXBIQevwG2Fo/Ln8I4uKXWtHz0+jGDUpzdo1gnitbvszNvJ/OEkx4tDWyet/\npy/n8GGB3FAsw+s5z1zCtJXetBOGGvjOlbCJX3nlrrt4HfBDV9sRx2kl6hXdqmoFyjWiQTISncot\nza2vhe0tGnn9KQX66QBop+JM8f4pcROH092UtBmQyIE3H8LTQRxNIz8Z8l94WY1mGzQ35KN7E2hV\nC5R4TCn1UBmY757nr4YU4UhDI5IW442z/uZgnJiOZW63w6+xo07FBTh+SwWR2d5ITJ7RWdfNrn/A\nXcmK6t8cO5iomzH0HYiBgKex74MJsm4ovrV5pKlLcRGlbTCU6ACY43jdIHbWh4HWIo4aNVMep9JL\ny0slIL7u3McGPDrk/3xjME/RJhGHiAMxEsVh9vLOdPbwK4ZpAxcY3VT50gdqlM9KOeEl48wzmAwb\nwnglyA8WUZ1wvXLVHNlyOuI0VpRrTndC4yLpfCbuvij5anvsgqCRjYTDaVgSXTHE3UcNMcJ5tcwI\nOR+QPX0FQ/1AWWGVEolH7ILP/CQ74jLbH53LvZ9Wmvxh0SAIBBPu1OIIoCc7uLiklXdSxkhCweOh\n6FGl07t302RGPiJq7OekUUTchqQkugubPaFiOwq2tJEJLZSyRoooLworzL56enUBh1+NTMQzdiBm\nlWPx86u5zM9sqs5HBUE/dkXzzSI2rj6r042RCBIhZjao2fwL5P9cU+zxcfD2sm982viho/j1tOGW\nGVP55bjvUXZj/Tvg/HCjoaW7ymhp9TGKAODv4pYw2CkcZmw3Ar5fjcTtTBzIH4mkrZd1WGS4hpXp\n1bLWa3uYMlj6Mn/Mz/2uqw0Gm7uCAYkg++JYwv7+Ghc7+TmDAGZXmKesPJgXWmgOP07nW2ghJJ25\nPnrbf9clbRHhY5GVGVWp+Dc0VIocRrOUI9KiVCoDNcDG0Ft0CptRJyKjuGx+xP9/fFhQwgXIp2X5\nzsx9B/8+9WZ5AQR1hC7jrL1V80vnQcL5hbPuMDI4ZNu9N6YmBlU5flxLByhpO531FLcvbfBSoQMB\nepP+mHm9Dn5+ZSXDOU+SLy/zGSIB6IKYqc4CKckTh/uGSe8pebyxZhGMBwPAMgycpEYyx0Rg08Tl\nc+mYu5VOUXNq8sqIVI7qODmEgkmgxaoufJGko2UFnBxNeHqgpHHx1I8iRLZxLzHGaW6IIN5v4M11\n2OEHTHgekGa5M3lmdbTqb12BmUP14lJ60NOmyJ488Ay4RRcO/+OrvQySDcGoNgFQWKispePVTeR4\nL0BFO2iAuWMPoSytgoooZkOyAJ4NA9dg94y5H/zkgVgC2JW0XNgv7/4P+z4wk/+5X/wTMwOUvGFC\nWhqhlzMzeSrVccPcjG9/c1t85DLsvlFIGK0dajCeFD2FysQ/qp9q+AjtB/7yP9icPT5zwMHIPVgA\nKer41AdrHdGaqlbkRK9C1ExmGnbfzxd5+BXRcUzcGAU5miRdvHy5FZOcdVeqVza28fD96N8vTaH9\nUyeqmK4uxgP1MQV3NAaStEU4EJusCHMVImPl7Yvcwqt4CXrCGm2B8ys1sx+He7XkaPaR0jL6beEW\n7C64DhAnYQbyuJYjhfm/LFSjYsGR8sPXLe9LPebNRb3+5YaAlBXWIBhDV0DHKoiCK6txtlG8V8ds\nez+5q/IWw1raRo+gSH/Dec6xWAVniNqudvyuRx/qEaTAULK037QGNYIdcfC51ikoO2moezfwZyoV\ng3T16J5AgbyE1CBmnTI1XmJYXUnori9vQIWJEFgWl/Qg47Gf1M+4xcs+hIRG0lwTAaQzgWz1PnS/\nSRO/VPNeuKAuKoZ4o1tpNTQOQV919vgOUYwb9p5ux13WQzTXwcDz6uFdoPVv7zr3YbbxQ0LJdy2c\nOdtE1Snnde6v+99wjf9cYqXNvhDf4I27aFL9ZrZbeUzcCfILpxlZ3puNAN1zMndz+REuaCJeQCZK\nxVBB/K831YQL/fsH63AmbapXw17KZtaC+fgXtrOYclhapbw4/WGkakKEkYUD0K5oK24AjjxZY3n6\ngUOfDGU4z+xJfApFJvHlMQGgsqOOrEe+496iym5h50DElwN3d6VV/Alc0u6b3EO3ycc2yxgZwRkz\na4y9IYgIqt33k5RPF7XNYMRWk59Hhtv9n/qSigaXM8XKEKUdYdhPAQC2nBNsJOMvRFFNPZG7rHcX\n//jd7nIqmAHZyKi27V0MZrkF/WMnGShV9zEjlqQqY1J2/vOOOUSDEX0SfxD706SvWK5yt2+c9Pob\nJA8j4s3YnEC2BX7rkpTu+AjPJrQ8LGxjHcr2cgVZkB2NQay+nEmkY6eDQONfb8RxaJaYOu6PTv1J\nWd3bPwzEl4naUlIGA/wl1pq71tzsY2WwU0l1DlyyyF3VxC3/8UJI8hhfZYeMq/RRFNEdlIoSLI2E\nP6je7MEknimqgo7eqXxmgpvCwAtFxbl8XuRtIE8b4xE6jQJz1WK2CT8FetVVT7vQ+Y6nfktnP3If\nLUYGYFTS7EYkPfp78bqWqGJYikwAX/EzoqGqCbDhbfeTVA9Jy7uyU/6sYHQVEMqoYqzQVgjs0V9j\nciKtvI53E2BwjhHnCi/T60bL3zrYAGonbwHtRPkzddMZd0U812eNgVG2F9+OiqM4juqHZycoZpn2\n7eIL9PS/747rdt8UlLqLxWYm/Kx3UD5adCQao+OVUEzdV2wNStA6yKhrx7BZVV1fsBkvK5cjFK4O\nAKeX4R+w01QDNRZO7C44sgjcoxqwErAZmHaTB0gGjU4k03kwBe78U6wTcccBbqMRm2eW+KA4wHPN\nLlQc99EAPdW8HOh+AWgf93i2VYxrupNQkuJS0qadQExlxOTr+NkWlP+AtwgBBURPJICvi9Ey3CkT\nC7texzRXSrljFyY0sA/ucO6+VeEG+cxtcBVNxAIBlaljGH1N0vnx1I0ycEe2n9vIWzpXn9iB7IjV\ncjpY1XRnYIAgKcEP9b1hA9+jtyIcmwDuzkuXwyWTPreHUvnO73Li2Qp3dAuA5QNZAKMXXTbpLK32\nEP7ICQEDYEW1IX3n/S3K+YzhbZDHiNQgpfSSjpQf0YcjDeQcAiyzalgvSwOupTNKyHYuvnDH9/re\nHcwDumxgPerueWmz5km7o2TeudPibucgI1vH8klw/SLoqI5o5buQk4prLmg7yqtCQNweS0oNcw1v\n7KuLgO6lOlFFxuTtLWmuX6xWXdzpY9cPufvgW+QSeFgQLmtJW8Um8478Z6mqamMCaAHNZMyYC/rg\nOVtFD7nSv/IBlqRD3SdzhPc6llFspql1MSK7kSm8QXmyQ0k8Obqak3HRTYzCPdDOlAt5WmJ6p6sk\nh1rSkvLuKdD+EVyXr2DmUY9b1sOsRMaJSiVuwvHNHJSF/DRd11WUW0jwdX7261wa8H9kh0brGuVd\n95WdhsMQaEfB+5/Hp0J4iwX0vkcPurHQ/ljcC0tDIXFxXCZlwOU/7Bgb0sE/bUTEc3E/RBnTpJGo\nCRDbus+B0oylNrmi4j1BY6rEtNOcDqsxPE4zoQRjMfcil8/bSWBGLzRXL2S0LUUPXkLfIC9++6y7\n16qudbtuVm4g9Z+qLkX4oFCuMwP6n9I1235TTIGM0yLLZdlTqo13oTKsbtxXI/kzBdeq5qvuKhAb\nvE94jjYBd2DIZiE0Z8ueZ6sD6vpl7EHzTChVKr7kLds9UzG7CcXO9LdRLcHERZxvM8bw3k1eR92e\n/E/L951Bjc2/vXAmHHD/QEy3BVc3N/ojAo6scRp2Ty9vuu1vn0CJz0LGdxDSKpAXbPY7228MLebw\naArZLYeU2GbKUfjPo4C/9v0svD3kTH0RjHhZ6GH6Nd07UHHvx8v+f/bleiAUx3Dz5EPpIvIfk72J\nFi/yoYTUhTFnHsnrp5c9Lly4zebbG+fF+lrGEZ1eH1hXV3jXwn+6liPWnIjRKLB4VeMYmtKTwk/5\nlFMqVnnTeDdvWoOMBxQdlZr2/nG2t7vMExO1RSZRX5VcdgToCFQDIhXiv6XNv2LeiJhK4lDf2KEW\nHPOeA0Dk2oymIGQ9FfnfjwqjHaz81fxKcz9ceZDVgauP7Jay9WhZVmmTC8ugjwao4CMGeUV6+/JV\n0IlcdLgvsbKlVvjO8RbATOIgFylF40y8JlOzLCfL8ZqUZcCcOWfRQstuUxacAhw6ltgj1D+KUPK9\njJzjP4Whge2pYCi+jxK0s6twn0eafZA+hPRr9BWStUzl8qBZjBGtJspSaPf0bQhaf+ZHo55yY/Ek\nkpOxnsNsR/XpSmI6mFxenqTRyAOGK2uZRWDufImAIPMHhDRMxiC64BIjDUxMgJNnbBKURfnvjRQy\nYlkb6yXkwpIrUB0rCQRPKoPCmnoEAzJ+oC79gbq8EUIld8o5IkkvWY3rwoLFK8t5Q6g18g3WoYXr\niuZZhUG1Gph1oSE3MJxrzotkwucD7Rl+EJJMkcywBqSYX4ZGEo90jOuqN7Fl+MUmknwhaykXVpRQ\n6WTMm8pEPM4FujW7zqWquEvNjumDVhG4Ri1RAgzTJA/z5h+B6ScoxIa/hsXfo8Co2JCie8f5zRwG\nimnak2nhFrUdD0+4rnBTt6LTl97T2j/L67lW2it9nobEY3C1aQgF9iviPBk/Y2ZHsi3P+52Mbown\nnIz84VfyTSlthOH9gRxBAVnnFCAho/RGK2MlTaG+eclfACUyQb8qoUAHGZRjHLvplUYsYfS0OC3w\n+MH52rFLNYCSrQmAwionC9ERH2DN55YIdry+6O+MREf0evy5ZrcGevBIYUd2lydJZJB6LQuIcmxz\nKxciVLi0NqG3aI14czaxHVIfSLr1kJNFG64p9n4DMClfDZdWtS0aIaMbEz9scZOvVanQDhdY5brs\nZDa6PKVNyUtk2EBdZbBYDFnJD5P18RY2M84H8HmF7PNZkRy2AApvnYYsYldZlpec202fHCuawKIM\nmOWYdWFQ4ISblYOYFFsL1SogvZvEsJUkxSpRTUloYGVYv420Zcm7YaBu5bp9V0kpm6FUilRlxtCp\nb6nyVxLIh1vAtbbmXY4+Xhw8i8hfcdC7K1EeYwIabd8HEViCHbmteAvi186+dF+xrRWe1t7hybow\nmbNApeEMWW2g8tsntULfkMrnlyg3i8qoPUgi8D8C8vpBwWrBHejp+MTLXyP3cdQhxMENFVgcwVe4\nCiqr3/5ePpzbm+du3NI43GJS8AMzAt39b9D1k3ARmG43hbSkfwBI3a9cmHKPTYc42zm/pz1Yte5Z\nun1U4YgrWyAd5b9+c+hflyV3I5c7Y7J5kCznxu5Vo6IIMPuRy/x1kxwPlxqwUTSXb577gC7xfO5x\n2Dyd7svtEuwnbfrsga3hKHqW5i3PZ25RCjwUQL9SfKy6g2QF2o/jx1VeQUzGJ9+2myKLmVe1v4+L\nyLo8fFO5B8A9pXl4ObB3xjEYcka/F6LkQJeWHdJSsMK4klMhOyzq3s8dZfsPiV+D7nH2f4KdG29+\nIxqe8bxuLfCNISzshUOKAozldqRYzfpokLw6TT3Cig7DyysuS7hPwXZgIKD+WVkcopszeYuTqpb0\nZ970tRIzxQonnJm9+Rrc+KPJCE7CD2asKQov0ONa+wRPbP4sABU6Kq4sKIG7PJZxbm8gjnhPKHQb\nvYGa63qN2Kx1C/6dIdGBxizO/e0eiut/SDG9VT5/O7eadhCLObxGid/hnf5p4D4UFIdn9gfp2UQB\nh3FPOaD7oIz4DDZhxWo5M6KpsRMpGN7h4ksAiprtxrPXhsFMF3hOKWR2lehZ50HinEqLLbfbW+iN\n3J+lHKliFKzjSjV/5IYmbR+y//Ji3QJCME06bD/RSiYaLsMpJ81gWj+Bu1jZMP7evkAycasKfclJ\nSieEkmjMdqJr+I1VzTIwRXIfSxRKgWEU8ayBun5gDgjBx2lQmG/WwyZwTCqXBDwv7JYG22xFmTdZ\nrFVvDPLmLrOPnclAhCwxEplbQvbB//6+xIdqdcA+jOsTxwIysOgW0cZg0B7f892h3M3+177GR9dP\nabvwpeObMcM7sohInNYXREhxrZ0sn/bzQbjBrjZRSJe7Lo9Y9yU0+wtiZb4hN+n8LklyqQQVHNu5\nckHcTV1zMajL4kmic0zwf+XSoXiU9aAq5/9B58X78Wupv/eZRwd3USpJucBxy2tSDP5YrdYkYhXz\n5UGJ4vifS1C35H2HK2hfPtCRRT6LQ8JxK7eeoKHWZR0l56fIV97NEnhTyNHMER2Sf/XXQVToHd+t\n2AdKEzZBN4ysG02eYKBLC52Ueo+t0zY6UUX/X6U4AL8ph00c4Ocm0xOxYCiWNlbGBzDT9vXJB6Hd\nHnLgqR2s9ExeJWFfo9iP2OHqssH4UTqdPhGAzlRr1S79D7blNlBMEltXpKx0vZncbuPR9fbCAdI/\nWx2q52nq+SwY8hieilyRZ+EMGYswIk3XQuDgYfS2vKiOD6vQ+nqjjLwcf1BRMKWlr2i2ojlllEzT\ndcQdmc0V3nSex26M3p+rT2UJK98CVGMhiiMAw2hc0ZR6aSrzGL5vdYW+QHqlWDVZYaSi1ZPN31oT\ncJR8D7PEMgelEOfwunNNQcWERn4kNdl4XDOIVm+dlbrNyqOoGpbiRc7ZG/TisObQMVHHvL7MYzj5\nWBbof6vdwySX/2S122ktv61wPmr20gn5W20mvLdlfjkv2tXC61iiEEJxnWdG+/uIXx4y7ha+l1Ho\nQoKVVW8V6G65ictDlm9xYo96WOWubjNHutz1OEZqayfoDw7DyY0TtiTTKFuUpvUNXxb+nAzInlWW\nMIYikl2z995jn856DGYXpD9mFS+UdZ7zBnBmlEpfYNyPofPAVT31dwDqyyMC+HkhLXukYbZjuMXU\n2Q/qaUjrnlMRhSFNLr1B6xko2dNvJBCfiP30iI7B23eJBAipXJmCjBKYcdqogv7Pm/cLUhIqSyt6\n5llWIN5Jta9dRnIYE2isMI3iImhX2lvTUgdI6Tre3N7qaSs6MCdCKh4t35PJgOFJG5rERKVxdap9\n56vJuAV/pwYVaKztaUNFqrm/gJCbG+UC9gcweJCG9mR6ZnXo6PJZz1g4mWpXZHIRhJZQ+WGFW78t\nFX9Ut2xfW5U9C50zEudOf5MVY7IYBqUgR6fa3nqRuBxxRQoiui5+6fIAzirWcMk5/PtZW578nJcY\nHrdOOCTZ9KYt9yJXywDYjlWS3diKTKZ9mdYwpdf+aJiVBB5QLGKLNxdK/ikVL45ASbGJ71rvSv5J\nc/iE3X3KpvNcQ7lmoZ/A0NhIGuimaAKXpmwgwLV0zCfuJQoLz3rfurlQuSkloo9Uob1MfWsP7CdN\neRg/2k8HF/j52+rRJIFgEXVhOV8ofyNzqFRDOxMk2Hn756kdvE6aiXORcHCdfPq/HAvAQHKfztI6\nWcl2G7Uy/XRNzUonNSjKPWcBzpzxaACjP600UU+NMUvzvY2WLlQ4g/tEHaeVrwjyp3q/9EWORwMa\nnyn9iLmeds283CuW4ZQLH3HNLlBJUYNHB1QRts+4yFMPrih2XsdO/s2ptGe5Qs2Ex6WBm6go6hOk\nTYJwckWhbwP3JIpJz4kOLI5JMIcZBQh8O5Q5hx4YWxq6akfFpVzM1+kSryM9TzsyNYbF7ZgRssgk\nqqZolFCpV8ttjiMT/k5w6RiDngKgDrmS09T/PMwfT/XiUOeq9DKJjwoKZmebBRS+btXWaOO7QYRa\nJUooITQl2d/5phfTvl705nr3WRSa5AglYUptwNxcIf+QWKzgim36lzf4yRqXPAypMwO26ZUQgxUb\nPffMjOmWGlImxuPjynzHYpkOLHltSTUbRlsIMAWNlDOtIxq4TfZm3hKRDfQq3SF/uKgvP7XAJWoM\natiWrITigWrr2SGZHyCNP4Aj6hp2tphIHZHMXyqf+S7KTwZ1rOWsP6JvBh+lY1S/qRV3ReKkxQ8d\nUVqL0KmPKZPke4WcXIlkPFguQw738Z8X8jhz7Gvp8LZJA/uE4szAOcdx91sLPH5wtWy0Sdyys3Y4\ndYVu2Ary+smN/+KX/hBypDJtVita1RjdyCcuxIYlxfoLwowI2/SHAYhb6AhkDpmATSKeVBih22zA\nMCE9XCPeWPgnV0/GFLo/2iRXAx5RBW14DlfsXV2UllF2Ksvu3LXWrKIOHY7hOditstDkMmy5S+la\n5T0YR47r5oeknf8R2Mx31FHYQJXi8OxhUzUZSCZfhFabY0OD+noh2AKoabJeAdUS3Vtm91lKkVi0\nE7MdWob+NEmzDRfKU0eGNhF0krj8Nh2lpOsHyvOsXujnfdFRwMROPmmGmJlEk5YSjV7KUj8ZCNt2\noUKrj2xQQ4e/L8Q2nTODynrdCgu2xcgiP624yh4LAPfUwEZYrhZvOKM+iWUMmFKXyBigQAUv7c99\nIbZ3V8zvPqgv8TdpG2ATjWhYMjL/vEBW3o775Plu+lKZorEOVcFPpczP/5r5GDrQV09iEhvBZJtW\ngu0rD+3lWA1bcu8dgVgj8VEL2/P+mP5hSNuOjoNG1hLhwfoBhOD0GqYcfw2Fw9XPEykR93r6T//z\nnwl9zQLP0+hrLpWAH5s7TNhVlBz1IzhW+NLO+F06ZZ+/xr+WEzF5uz4VwmyRytV+LywD1bk2mJhX\n0JLZED0U7+fv1VpROJXf91OavGztCcme+6hguAfuMpTsQGDG9zXPCioMa7Ftd0LiNSpV/Rlj0CaQ\ngs3q78c2U+ZXN0HTWkFffPvrXoeZGRS+qHowmRAJl4bKQM7hvj76FbNfrk73SUl38IFuV5lqIvkk\n2YMaG2y+0+9JOqtVaMZaAmg9Z5SI+ocT0vKzQysmSETiwQ/MI6xm2MLwMTTRAocL512jHJnm6ipw\nrWdLbAPuMNdVB3mqLUQOMtb3A1rfJ7nUK5QO5QKXTW3wjrYbjVoTYT+MbGggZUNeI3FVpX66Rc81\nhTW1+8xNYi5zZ3P4Cx1sVcD5g0lCiCuvqWdPDaTytvZD1scCMia9Sz8bvBRO4flhNIdrDM2YGd7j\nRziKjvVOqTGCVS5BeUH451hn68IoA3g+QGFLexaZZ4rdinzhthmA/fhjMwjXslMPaS9OXQf5lh9U\n5zS65HWuisXo4ZRvfYyMBhofsXDXny1J2bysnJooFOr19aug5bV/b7z9IHCoLxfMGaMneJvUPiCJ\nWxSZtOEjLqkj7SKbFqDvbwX6TicW+DTettkfo9HTY6x8r2jnmbGmEq01FGhb6+Ydkjo7WJhAHBVQ\n0IYIMHsyd8N5kPtPtKvodI23N3w6Wk+0HD+BeOB1LMLECKoVaa6+HIWcLrruGvpJZ08/eJk2mDWU\nep/L3VjKAEj6LmBtHszQZAEKMzwn3qDafylEJc8ACoLBidv7NGYBy4G0rxf7jnTZZfl+yai1LB3y\nTbelqlq6cMjhn+2CgZ8wWJ9hbQFBs6qotQPJ9A7KnMTG6ZS8LuaNkNB02VeBIMcCgBeg0Qh493fV\nSNUAkt8qPw80Ov/+d3XKN/T4GC3ca/4bpG5WZfFdMl9t77Cl7Fp1lDp8dbDe6JKY4vo5xYgXHvrY\nWD8B8PmCA4mf1VFIpIWAKw4C6WmzIWrNh5ls+0vsMpmCDyJU4qSN4Zn5DIJmpSaphuSIk4gcyq7v\n/vP6GUdW5weOjdAI/K54a5JPqdYw4+DfyYzWbpiaUw7zw7JkvEtyzOZNsLWxYeR8VwCHkr/h/XVf\nlMUoezXhN6HJVxje+cfIfVSAg52uE+j5vjSomz6RcYM0mTRbpU2NMdIQP5Ry4pcX3qVIoSJV1qzZ\nYXWFAUb7XeZEoh2KUjAZoe7t2FGdN41pCKB1JW4TexupFOVzgl5i5OjtYC4Q/aw4nobzGe4Cs5Ke\nynGLS9ySFQzWG1LcGxXiZY+rjMosPXQiCoklai9F5+AdF2Ml0hdrAWXyk4No2tpZldxgWx52ybDa\n9ShqpmQmHXt0THQkpe6SfGI837OidJ5JHMKs0LIkrbq9g1iQ5X14XhsAjSYjuW9c/7iB5zaK6fH1\nppGuw02aMCS5w3yDmZ7XCojHrZxNjlgAhuH2mb8QYi/0JK/gXNoizQGJrQlX+5FZ4JXaybSZYsjB\ngUKd3aKYiDY14HG7fi+cE+dHJaq7a7kSqbsdVbPv0rQrXWjMyF96XUCONVOklVJpLsFyPEaQVgRZ\n8f/YbPTQSsmjIj3a7B6JbyDO41T8txa29RAw+smayeZlDhwtWJbioHZDfrsz3S6cvBgGCR4TZYn9\n5HoxsSSaID4pJC9CWaR/YmQq5lrq+tlgSPw0u/DdycIk3aSYin8K26XojWC/qvnKcCab2TlPnAXH\neOXyD1mit/FYdP3FwhF9utNbaHr+IwOKxHdPntY9qtBlhFleZISrzzYBKyg6qrA7IENaBKGGusa5\nDG+16/bZQf+BXhniPd6sgC8Tw+FBxCpBAoJwvjfqZdFt0vBt7o9hk4vD4qrhewgeQIcsMO/H5QIz\nIUPZN29bpTM2Igwn7/Drv/C+I5Sj8eSUSqrOlA3ap9TehPf06ktHfaYuJuKHlM+AAuzwtWS4M/ge\n5je0Prlk0ftCNLhFkacSX2KZVGLcz2fLjHfApZHSlPjhXWWLZvThRZzcRM24SHvWGEu8VyKPwa83\n65quQ2p+CktE9/SHsXvA5Rg53pmPGbboUPxmECbedWJCcwdloQXbvs56gYcrs/Ro81Ew+ltErTY4\nrA4Z80DEoJsYAQT032Z8d2WV1j2KjTgWjY5S1nMIXXRCsK96MzlpQkGXTo4Xf5bIHmdeddAe++30\n3E0ALYu3EvX5Y/xhA38ZBQHJS3cl+TkVlBqADfOjtlYwheNovhCreNSE/r4NXqHh6ZyTuXiYId5D\nTLjAmvzbj9+8PwqTcETLTMec/jAeGggCfDXAjJsh6d7eSp1dxxwhS5I+IoppSqX9evhiEwSMBd+L\n1gbXunARAOaDytFW2EKhDG35xRMkgqAtL00B+N3rwoP31SDnIiy5U5ewBmensYodI5U7T4OE7RMf\nMCraBtKKQOBWIayvFIOWw+ZjohGjz1HM4Xf/ERdauKRV65uaEdG9WInY0n2OafoFjwJsliwYe1po\ngyAiShzP/DEuFj4OgHwSrFsLPvxMLmNau3m331i82rAWLADHh8Lksd5kFL53oD7KOjohPaISv6AS\nbe+XFY8kV1YcYOdysJN/H/+IdVRQLxpj7+NmchBYzOh5P71deWZfwl0eJlyTHuCAcxtxntdEFLTS\nKwpRQ8baz9OX/sOtPGaAFUteM+cYNiLiWZ5+pa8dpq34EhUQvQ9AP5VRuaOlwiSsRjOBYHwHrdqC\n9AW7zdlosiWc2NTORmMyplQmWY1p5F14PqKb7qKdgKte90qRAvz0kuvrzRRhWHR2K3Ou7uRog78A\ndTwTrY+55EdxDP+Y/rnFaNLHCnzPDl8ETaIs7D7Bfybf7HIexm56gM+9Lrn7STBo5GzLfGHq4Sgm\nyEZ0z2rK6FyzqgI4BoVflv1G7c7uYs3ZlkEUtW+lW3pLrG1FLIvq/sCZFDkXC3051l37AIGl9JTk\nnXfu9V6caWi5OD9NGqZoNquWQKaW7mGR1I0ZjYwWEN/MNF6ggkhUI/znQXnpnTGAaXJuOqiwvA/A\nLXds1qi3b+goY/8riaIZoEJsyTDzzuBHj84AUq4jQSVQgEaytQu90JNlOJCWdlRXxtjaQ5SqMqhY\nwOveUi3TPP9nMgckeHkZOkDDATqLESEpfcFGYMoSl6CigG2WaIxfPfU3u5OrYaw490e/l7cyLtZM\nZDvmYNF1AHCrpn9eAlp9bzL85DnW6PCFXyULKFBGoP/fLK215CtXJCd3gJR9eTojFVY5sLtRpLSl\nORLmPAJfXbunz1XEQk+B8jVx2W1fHNvkbQslFJ8+ti6zm6A3sx7G95sgpgnU6h2RImyTrOoXwrJZ\nYSdvEMRlFr5olLbOml7BgEE7Oq6FMjtHeNYjJ0iMibdTNhFXe8WT2USIsGWKBxFa/oxNxQhJSB1F\nSsoIvIoa41Wz3Y2B1xxw+wkfUTDvIGq/zzJM6pvaDgHCceU/ZaEKPAOy9usCN0ETpz3UgvkTGmfy\nxCrPFFKDWeVLFXJast53NyGYnGES0s+SMrqGOLWl9tBxuxqBoQRid5wW1kySlny2yprdyakcl9Fj\nkRaeVhVaeGVfTjUs09SWfSN+IZiGPqRk7LAiTpYVSpnRuXdoeTwDPl+QslheDjiRbZbULQW/JVJv\nU6++OVcBrfI4vfBHgTgpLD8eACa4vEoSzcrKXO/vHmWyinCaCtwM+GsotQrOvtG26Y+EC9tf3QoX\nTjzxhVuNDxy9T9G8agNxIpXOSsXg0LDLbrMy6U0+FG6q2JpodvDjIgEAcnMiYlRfskmLUNXH5EP3\ni692qv8Z0RbUqLQN/e9X0TMASOEYghAVF6bt9pPf7RMDh0E5K4/X6oipfBpyHawUyF8lUbLkTOaJ\nsTTT5d7v0h+zA5paBMqGq0o3nFIeuBWzIde9EnTl9IZTdfrvtQSaM3knyov2r5mnKL1pYkbvJhrh\nruBOCMjSSSdscPVQNCdoYjlkDnQijYablGIo2i8wvbrwaXgixpaUy18TPixxHErPxdHGHdua3Qa7\n2rjVl0ahdtPI8VAF+ZOL4/WjbqRBcw4nZtK0Xt/Dn/jXaSHnqB2nu68cEPrK8RF3uDCNal0YTJAk\npP1K+ceQXSDAQNX7LQSQNejbnDZKEqH+wd/5rU9X+FGNIF+GrV/UL9YVN+Z9v8mf9bAgTGa7u02+\nXE9sv9sgP98+NzrU/mhU0qbfCcEa/sf13mMJeQtxUTqTPS7xtvyzdUm7BB29fvp6ERFFR4XcSMqy\n+x5yUCWsY5oXEnlRSE1dycjo/WpcvbpsQXhh2FfenHWiXaPKPTc1NW4NStBqGgY6NwkBr3t/3DK9\nrZL/nPZE/FsM/cTw2a3tm8OiZBOs1v8HPdsaA5FFAfRphLbenEszRl49xX//R9RPdyKlJ2ajlHJa\nzM4hp57p7D0upXSaVpH4cvhJ1QqCyHMHtCObHg77B+Viwv1azHc8XVlQ6g6isy8ofgWLAuFgAhd/\nVkX4LcmR3J8eZTjeoCLjp3W3zLDl+cjQGeEDFhssYSkOeAZReUiofxDOK99TOBMC8iXDvfhqHy28\nZhEnwbGdw2bBWHaBsfLXBQ9EDTMdGcmQF5EKvwE85zN5wh3HfRXd97MeDOWHCx0Sn2k0nfckNnPb\nLK835PyYsa0YPeFsVLj3PnpvAhlPvhiSJoLxILfUN6MZorw3LQyDueLYDSERyVM0WQqun1wBTog9\nXjjv0wcH9yXMYo98X1TZNS8DsB336DwFF9ohJYB/30KHhNsWMBumsRmVg73r4KcakHpPUd92lo3g\nZTDfXX2ZM1QH+ofKq4T/aw3IYlIPXoMGRZbNU91FSGYpYK5Pif8Lfyvq/8kWjbqCd4O3LKmpIGqt\n3PE3o5J+L7iUdktIEY/9pisfUblm/yj139sLS0RUm/1ehxxoOFeKgfLIlM4TflP1YCTfsNtU/Xsv\nK57k0vI8Ky/G89m5ltD0ZEf7V5m7MC2fwVWGloRdwOnf80q/MYoDQP4AEnpDhPBfjZPPDI9Fq41h\nLpMgcJwnCvyCDkTG2JebZKohM8QESABLBZhiTy8AH0hmEkDMtLriNX4vYlhL0gwzmB7fOC3fAnVY\nfutueS3kI3a27V+CyymeJ2vh1V5+vSIKK+EJimc5hQ/6rakjHPnk3Zp9B8L4b30SxBIvRVtciwjz\nviN7q75FBImEMmfrBJHy2nxFD9jdfLa8kDOy0vFSis/P8OuRwYDJPgFwr/1P3X+axZldm6iyhDeb\nxPsxkwhPzyWELvSaeapRjZ7L2RVHyijzLgVjIxVuKH7aDOWTiOItcSNBqjX3fkpnTC2X1e+IHY4e\n9NOUI2GZNUaB2whM0QnF+5PgIiuY3GSFhOg0ZP8Aw8v+DsENNY9zOgMZLkcfUzJF25SOtEhfA6TW\n20vT/PycJRDpZtE5Dh26vp6YEWtW+liQGgLeBwsS1s9H2yEGxl6jgEjJ/YCjl6DzRUP396NYbxe9\nwUYxdCYsadDoggqVeqHgUr3Y4usZIR9YUfKG0YZl3AwtXyGxsrKjfJVxhXPYNuM6EgTTixkuJvhA\nUHQIPzaIizh9IiZ2YZVnyYP0Ja8g8ysNzaPOmxjLT/sc6Tbrzr+qo5tNq7zCZbKvdUYuC5KEiZuS\ntvQxqlZF9PlKQsMZrZo3ksjmygQNLM+ZQ8eXPVFUPhZQTFyMzfSjZDzDDGkZ7KwRlWxzwDcCGaS8\nJf0HZlDGYL9YWrymGuJ1IpwWmL6Jzmt/7Y7jOiVbm0iwfIwRgDB2Gnoyf5JPcRc1jvylU2HaGjL6\nVpUFClhT7jqUTaCN1l7VeuavubRkBu/OhiXRdHw5rZvBJmqkqFGlrbgS7FObmjBHc/Sz3I8P8Uxl\np+UlCvscTRo5pVImWuMiY+XawDeamXMoiGe/0dj8r+FvmwlZFwuKQOzQ64OQ334D/nk1DMroEKYX\n9TzNrji0rt8+qdFvHwZoputf4KOHNNfw3Iw+V+blfnY2VUVloEqhB5npjMcky+MwORxCi7+Ywlwj\nvLpKM8fdtoi9ifynOzVySGAAq2nWBzO1lNVsfZLmRosslUYO0KwdrfrQ4PtfeK10oZatytLwzm6p\nBWgLGO14TYw43bIIUmQVF2gxh5mW6jFE2lnqxZwtpyWrbJMIp0A6Pu+0n94qwgqybdKTbvowiuFh\n/M0YP6O+9n7JIUXSne1KEypwGvuThCg/UUAypgb3HjBGAk8eJ8mIgLwzKe8uQZGya2QK0L4tiN8m\nNmAbrjujjTrbjR3ZGoighqf80L5t6VGlCCqjAON/qXjZ/Y3yhgp5vHTTtQt/EiyXR0BG1LbVrDzU\noRZaeSxEDPM89fXw3HmBU1lmreuOOwkV6Vbvt+SslPxDyw1uthmVEvugq/5rKerNmrDpl2+nnz27\nuPOcbw7Jw9Z+xLsw8KVD51HvbDJHLHuDqtK4GTLtUQWZg0Qb1O9APa/05r8sIwnNnU8ILT57ncmK\nJAGCnKB8UuhC/em+M9g3V5lg6BCtFf6Wxc2gZ8t92o20lR0QZ7OxMOET8trA3WPu4XgXhrKxZhMN\nSRnKh52Zcw8/kKj1CgpO2zH9xr6OuULeRl4gwuRaQZtLyadvoWvzC2+WBV+AG2zD0XM8GSM2oXsS\nh6zsb5awQ07z+VKzYVZMVzJTKpfumYa8zsP9Ga0RX0QxLLgN/jECMRCaL+thzqTRp7lW3VPuRNWN\nm1zofrHN95idehhc+IK3AS912N4H91/nXObo1FJilPtexwrHV0bbF3Y2wFOwwaXCyE7JFu+jmV9t\na/QxYNlkSP5xt7poAABhqOoOdNOTlJlfenSAd+SYYVv5YlYUT9i6xjIuSn2xEnyS3DoNgMtLa6Ma\nkou1DKIiHVeMoPV3EdQZfvDHzMYMqNGrh3rPT/bPXPJOpwDWXzvqE2JDBJuHCODYBwMHKEQvWjua\n7VKtKrg9oqfgTsu58ptwMqojwpcM4RQD3MQGB2r4hReQFmt6SZXbonFp43+aDWsce/3/EdixXahu\no4nhoXfmst813aXYyWi6KblN6WBR9PBqVn1Fy8e5E2ngjrwfFHT4LUlGuYQuxT9jffx0jy9wr+9I\nCPKNVTqkMyYQ4tj/BcTsv7Xc781qj2ACZPEo7tNQYGAkGLERpAv+zlLFmwhNdhZovbassB4E3njX\nwWgs4BqlSwbEmzBJdugt2vjAVFd/jtC+Ajr2RnyZptrQofWQp9j9DXBrCa//xlKCXwVGo6FvTUeC\neyC1BsHI8RrqRwPr4qbqUsrX7emo+V4s+hT4qPR1jsXMOFJuU/lCdKiFh2DAdNdzJ0ga853JAjJ1\nck91jy3xJ98flP2GZgVeob3Mq93BbhYcEyii8kt8kCUa4BNIygdQs1cTw8ZHY1EJQi7Ui+pr6cFC\nHz9Qgzwfs7jAoXYbAElRC1nFDQoi8likeMK6v8rRRayoGx4Ck+f0Q6GoO/rAdzAUz1Ud3Jr2mdEw\ngxqkd4cDqEz9vgaoZvz6JUymicLGh6H6+zbu+eYj1RmfFgRXKHQJhyucYJjxV18aUv5xjS8FqfRP\nHUVOX26pL2MjvyCN5xCiDrCRwT6FsYyrAYcJxojb61yimZn9aSXH5uAChp7WSs4gMx57ry8NrsKU\n2LBrx7zkcrGs2UgedisPYSTpCaYR+Ya3OIl0aI6p0YnQlyCIw9hErjrRR38u1HzA3Za+hpNFjHS3\nWgsSGK0omqoCB2nJoQ1gzegDdTfJdlcdXeL6VYTh/R0SaWIxqxYCJ+Ig9YBLe0kVFP4aPh1754PZ\nbg2MlR8rKlmwTp6VDfIMo6Lu5faOWwfq0kDhMDNkfe8w1SOFKAGxfodZPe6AtvvG9XmWe7aNyxXk\nIIt8TLMt42mhJirusEfQv3ZLbkA4jJ0ApZMXd4a6Kbo5oWL/KqoR+rdVd2SO2UUtGp6rbtxoJa7i\nLltx1l8AGsSh8lz2MJs1ZmhqIrwxZkuiMyEfa5xDDS1wYyvhQOKa1YU+sq+zWVgYjrrsvTdr9uIS\nEO0xE5YPtD0uIGAoYR33dTE7ODoaHR1ehn9rFDmK+FnUB9huEtSqMCNLPQmZeKSSovMiakdbt9FE\nn6VdtVXE9PRHtRe/6gKJobe5H7xamtyx03OyZCYR/iYWo1++12mxJarNW+5b3QmuCIu1eUYBq6F4\n4lD3SKCTh480t4JoebJyiNAV1hFCzPgbWl/iwKEEtEvjaCJ75S+ySb/BDznV8bmic6nmBEtslD8C\nGv58823+NLLKRFeYTYiUde2hLurB5JZ9NvINTrhFPQ14JNmCA0ssUNjP/qplDwDSD5nyRG6Fkcc0\nArPVkoN6aA106b4WtcMy/xBiFym7QMPv462jMaYDzv7ffhvF34AuKPevcbkAaRyimYG+qmtm4BC+\nTRwDRQ2WU993G59PZ4RIFt0O+myJMSFu7o0PX8PJELQJ6Elp0QAigiltlU8wgJcbGYShhWRn83CM\nPP+PU95JwtcLjwfuJKYpz3e7OE01zykCqwSzIonCqRBr/9KhxNWfVCZ++h+tkriuBAwfVpgUcV79\n6hpe0sbMd7BLtuCzG2dQxjp9Ge80yZQeEGvDQf6l1N0gtgbG87jWADgjFY8y99DIWErgJwYeT21k\ndfN1qAQgiZw6J0795t/1W9L6jBTwLopcQIUSjSaYUzghPkNNNJy+n56sC85BmIhxaul4pq4mixLz\nFkT5jU3rvT3zbtt5ueQhU7rrAmiXTqDsq6eXuV+uvtJdHqRmtd3Rhj6ZpE4lJQirTCK2oEggFy8s\nO6xW7sJfnb9RcT13rZ38X7oksOCKU0RMse2UeIAr7uMUanCdO8MeSgIC8TTnvydl88Z5oR+gphgt\nOy4PMpcNnueKkAX+p1lMSxWSI9AFXpVeN0qawQQb8Vkx2U/gfWyI9pnTV7qwG9jSFW9S/nZ3gB68\nJwV3YfxyT6zXhWCc/Gkv7Tg8vpbiyO01W2Kyb7uEW6bfBOTOOr0T1HpDNldu0bII04R+aI/QxLiX\n44SzP5m69ONbVDCS0jIaMxZeCEf/DjMSdWu7JN73reKbeMS74C34If+VCLmiStIjhZNz/Xnv4z2o\nJmuIR4gDVVYRaIsFuukauijvE7owE46taQt+O1oKpC8dKMUEBfU11Ro88lX7ZQjXPkcn/yc+1GpJ\nfuq/SnvOjN4IBPju1bsZvQYQlga3VZdXoiOTxX3jc5XOTHhAMeQCyQTcyET1tnuLRBAwdv+Fc5kf\napPvcKextrh3awEE/G0iMqeMoKCraSW2MToO0beq8ro9BXiHZBzU2mBzFWD985CwN8sY3uiVnZ7c\nAuv83UmkmE+IAF4VcAdFvU3fuMe+jGBliDnuRlErmkCDD2CgnrZmKgFOHawDC6bVGwmLAjZepJys\nIyKUtiSS8xVyUcCSk1TQFbsGQcQukr6sTvOh50sdcSyeH7jCLI0WW0yXcIigQGItBcN0i46hbwz8\nfp0IyIM306EVmh9c9g1JTlG0XSglXwWSQ39h6KJ7dUmuHQgLPKTuhQp13CVhpSzfaVR65UfsXucs\nRqQWeiVBw9UTq+4v3JztKZY7rMVSUmSVfEUJOlcrlIKgm1TaLhZESxpeihir+yM9uMtYT6tdGAxn\np3ZA72zGjUFiLe2S55T3ZHmf17dAwlN4/zPZMQ9V0q2L0JhV/f4xbI8c70A6al8PgU93g7Xu+59k\nddkLOOFBrG4Eoyavn658keeFTkhzJVYLfLV/ID5o46kx1/fLlZaptLl9pNnZy0Z4SUwNHT17+mzI\nkC5mlLpuzilahog9fsRd1djuUf9bH+FWpCsGR8BaOdCCZq/5MSCi/35y1oPl8nwIl4/ZJiNDY/7x\nAUi6uM/fNdH3e72xqN2TGjC4RNSsAptB896J1Zb2VJLgNrFQ4mJKn0Booqp82UDI1Ka5iQIIUEut\n47SH0MQyM+/nALsM2CIWsNU4J4dNyNs0MSslK+U5KDVGOpAduzFNntdMZWb1ocNj6uJVEFFkR7e+\nArF9UD5Zl2JQ/Oloml5ojuBQwRYTKk1Dakimxd3hFFT0PaaDTVnubdaVpahyyvNxBM1jqwla4R2W\n8dKrvs8UC2WfaD2f5jpzkzwTJID6QUkGpadMvVrM04OCaHvIG+AHt3xogqTXA4vYCN5TcwqOGOJ8\nR/Rw52+LkZSSBNjTa52HNNXtlbY4E3xhjF8oCCJByBgLvFkEHi3kpd4e6DaJO+HRzrFF4W0jmc9E\nSzsV91wRPmJLyHN5AdSfDjK3EPquaXLjhplT3vt7w/ZAH/UrQ5i38uoSmzSFmqny4PgbAOLrrZfh\nuxcMk1G9731fVeSJfuRAfUQ+uWaDF2Gt0CWuF1AAgg+bkeIqmLlboqlgCYXu0vcQb3tJt81LmDUS\nc2XBFpqoZmd7/KHxmSV0ToLlsbpZT3fkQoLbSQylo2M+u/SLoPUuf3oCfwJu1mUra+ZJD/N9xiSQ\nzR3EjX8xBCtkmhBZImxbB4kHXwKXywNPyCxSRlabrlJNKM5cAv3Nkx5YpAbh+KxPGLRapy+L60x+\nKWXI2aGi5gmo24rDGUH/SuBZZBWPe0ziTAPRXHDkGFkZs47XO/ZmwVM1d7t8iIEUYuLrF2VFvgY6\ndLt0wSX8TeEz06NCK1VeQ0sqw0YyOHr9rM+H8ynO4l7MKov109wcX7tEvsf0ZHIIj9+PjVzo4hDu\njFAiG2Aw3dVyxqnJtGgDC+KUrpAj5y3r30D9ACDaPBMScjLW49bjiS9mmC9ldh0RSW19nGaxtiXV\nTf1SSAOlU4DzD/Oz3GrSrSkgESK4tsXy+x80N8AnKHdDTfXzS0i6ilQKHSGj3a3jIx3y1zT826jP\n2yiwRwO0gu5jcGz2pYVsLW2z6j3qmwwjXH51+4OM5yTRSuCDFO0TC5W85KJABo3McFQScT4TeuVH\nc+nohLIPn5jKks5Np8wKyD53Bsa+gjRBr966DxJUGEgqnl8Tueq9qltb6uRlu5HoZFgFR6buDv5q\nlvOvENo3AkhRcuwUzMNb10QGYmEGk+euxvePxchNmKPBgJKVkc0pfSveJjx2AAtiUHZCUxHCVdpp\noS+MY842EKiVB46mZhmw2swa9uy1gMOlvtC4u1gPevfuxlMAtM5bZNKF5lk4SUgifgQM77hBBcf1\nO9S6CUBRHHYSYiNf/FZpcB1XHmAGRLmfNlRD0y0wlevgVGWgkGyCB7TXcuKLWAvRa1pZahckCWjg\n7iBK6kxlYOEikZT98z7m52fwKyqp720UPQN35uyhwnouzVQ5Aq39qIzfjZm0Owa2SF0YY9fWBxql\nOhszVed2M54srk6V1cnVqPAx6vdhMJXU22QY76sNKnh6pshhcPaocUaX4CIdfd3iPo867+4SL9eZ\nXE+xMQb+cFuHxG2FYVxbRr9bgive0kzlrJL6rMhcvuz7NPsdBsV6S0/wQxx+VplPG91ygpCdMMkS\n3ccKyccKNnYukEU27DVe5BO0FdKP9yu7FlHe3yJLMPSAcitjisg3djCJok0RaZliZZu9ZzQ+C7ji\nKYPvW22vTboon3uA6yCiEkJiLl/a/I93I5R/0k+lacEMp8OEKrvVDChuwxyX7l5rPmmfb20tYA13\niKN2cS/4f5t0iCJ4/Tg9hnYvV4Sr5e+pLod950hEtx8AwWEECKMsCNSO+/kQwQh355QZHvKpQagP\nOkOtHuBK9mMBrCrM4SuQeDCzwTnJRnzXgRE+7bv24ZMXJr78VE+mSolMcOLMCvkhfjSODwLpinpd\n7mFkp7ucDtAr1Xmn7F5oXdQFzRIFI0Kyk6mBVtFaomvNrwFM08l3h9ho/HtxHt4d/EQzBgp4Or2x\nyMlQ3JBf0NjgvR+0dHYObmXQB7SyJ7ED7hyzN65ymwhDlsA8KR9whP+R1dR3bKdlRum/c/+QwGkL\nAN7s8pXR8JZA2gO8N0dVvZGHEg43AqRNCu706qju4yEXL/kjtoZOp1BvTZydtsgEjrKKLmxlccgE\nYr5UdZJBiDt8VHW2ZoUhpYj8HvwiGqRZ5QIwd5V/QoEZZsQgJ2Z/TPfuf7orP813p2BvUk/E5f99\ncrZOLTGYwjHgSzzI6ENicxxUpwfexXN/n7T8W4uTsYYAhzsQ4fiAahnzRw8O3d+VuGWdENHCn1Vi\nrDQVXGnGTh/CSCx5wQ0TSG0RPIiqldAEyfn/z89r8apAu7fV9yIOe1VSmAeLsBh1yDnnKtZtt3oL\nz+H4SD+qaOELAvjIdyLdJY44ptU9BwzcujNjqVuDyU8IrStp1WaisrFKYaN/9CTvDHk9ud157nvS\n8OdviDYtrXHSq+XKv2lAs9I6fA1ngpNqjXHI8lgbm/mTrtN8+dMXR534mBG3GolYWEGkIp4JBQnX\n6fgW8ARHGDlLMOnSdpUaUr2mXRBCMeNrPIVvz/LOCM4CjhSK/5iTvZOF0TwzhTyCfO4/AjN2GffX\nEW/+NEXl9yfrMomSg9xUDlUDkEujdfYe0AaIK+ybVyT4reLJD4ySKgj46WQV3SeiN7DS+Ow0gCv7\nvzv9BpgsoEuWcAU64h4buo0Kd6LVHgUzprxT2jWSjG8rCTqO4AMWVdhZiKAKudeQ+pv/NQh3Fz5y\nbohh/KzkZJeJEcB/hhOb2Xu80X435L0uTQ9XPmfDMcH5127Qa45dqUY1LJ80/856RoooZ5cq+WTr\nI2L6zsQw6Flm7z8HTjEHQb7ITkOM98lAzjtcfGMwV5ukP8Cw4YojFHilTmjU5FLfaDA7VTDdO9QZ\n7tZ06co1XeQF5T5asfhsh21MXaALj8Uow2rKzyiIkoy3yNE7CIcX38ysYrvlOk+YHLRjWsmt9dJk\ngipbPg40XA7eodEw8xTcPpUoYbhw3lZU2ncFNMijC/voeGpsQVyopBZvgeJkqLtrNeERPGAX0BNA\nnZh/74c7u3ZM7BOE9VeurDxc2uaI+5prh8EeT63X4Qo2RzzOewLSklya57wlTXbjGvl0Yf9VqlgX\nhJr9lqN7rhiMdB/nwV0A0CtTf5Lnhvu4OqVg7iTxyQEZBulrbVky8vyJ/rKxsF1H/Srw62GEh2wq\nSbks/iPuUPyAoeda8ZG6LLFpxdIoUGUK+EuhtIiNoYeszKD6Dh6oaDntkNmYagwiNapLQIlrm+Cg\nxgGDg8v1jmv2nolV2F0+Te9XB4iIifg7KYHM3Qe1wUB+zteVwY3AyS7QRJVvRhnkKGur2Q91u1Md\nHNXh4fPa0FflOyhBYY68L8W/JxXcm1F7F31SA/3Ve4GrsFCv1kY3Q8dWWTV3pbzhlByDEivtsCw9\nUVpv2OvYBa1X5mfkskTtA60EjAzTNC/1Xr0K1J7PFyktfEXJXXDdzic3yfFpm47fTbNrOr1F13Ky\nLdS8fVl1ik1TFX5lSbEDbkzNt774RamIvAC9fT42os2JqW8MS0Ph49M3J6a4OGBpYfC96+kpaH5I\nVufeJkMsSQnamNWmyMNWg4i4PTE//8aRi1M53yYfwqEex2ynsEiutz9Sd6bjnp/rElluBhtpiscW\nSNIFk4/cdDg9/kTH9biwCmEYekE2PuxJwdSCK10ZRbxITDiAtXEo50UrJmvihATmTOPh5UJFZ361\nAFdYz/Q0oeNLGUL/OYKDv9eAeYL17UOwBo1VeHoMM8q52Z5j8HxMzDGTzGm7GC74/70Us8ZCVnXM\nHet3UOI6T3+08Dn4/O1KhrG/gSvUjPevX3A812CC9lInrx2Kyd0Nk+9iIgy9jd4MIi1LCmKKzJ09\njV4vD57bm6N+A7FgbYIMUDSy4Dm1vDv5n824AD1EjExmaH8JrbgbGxHTKxw6WwadX87D+eihKmDG\n3tqS8NT80CtTBdhqgBU2gkFInXY9JR0L0XJJGn2dki8aDfMZ8whh57pM+5Z1tEGBIludf0WjIfzR\nX3nF+s2OgbDGWwxSiT/PSQ49ya1HWfeJv97SscyZrhkWHau/srNTa+6V9slWb9yf3G+ct4CuYMyL\nWnX4d753bG6DAw9wFaP+vehX4YlafGrJBL4X/JeOTgl9lV25EGSqh041GAyXWduani3ULqBfQhOM\nbKgtDb1Fc+D4550h0+zEiO2y2hylVzq1Bseys0mZhrXGqOFIDJPcIkx6lij28+0cQ5d4p2aHxhOD\nxWYfqfe/8JXMwR26EXHPDgOsQX2FeqQ76Hw2ufeEOCnRuhH/+OCbFdSlJP3JYPfQHYvHp6RfdMzA\nERWkkXQ8m+Ka12bDzohyI/cBrI3F3E1HPkptIBdZbrreZseo3r2zDOmKvqRb61LpP0fdeyeGBnGM\n+Q/XeTWjbOHcCVIJsHu8eRG1H1nuva/5pi3U93y8TiBJkEaHFefuet18R0FM6C+ZAj6sCBExAelr\nMuVqp96dxgAMj6aZ3yxibejjGsFXVIbuqWME/ckI7UbMcE2Yud5n5gMDfCHvqR9HsmKH4y3rg27b\nPgDPRbXKD4gVD2DSCkwKlVKg2joDLkEPfGG3QIV6+xh+YgOQEIVd5WBhkfnEnH6bl5Vgkvs5hueX\nyqPOJfZ51bufF0SmdBn3gaCu98IfC8AhMehoZqeZL/iUc9se3/lAdJrShkXrKy6tmWIley/RAG/z\nSfAgOLLLM1ArV6Y7USEbDiPahNYVjGV4dE9k8Ozwrs3raIFFIhf+PnZ180sVCwIDmsX5h83958mY\nVMrv3Q227mDx158EC3IbXw6ovu93FAbuFTzD91mk4I0I8OwsI9J8o65B5THkkz4XiBKdkCaqWvS/\nw1ife4PIKarCIWC/bRxRzGiMkIwMm33NubjXK/wHwkOzqeWYx3nUy5pB5AmVk2r3QdFZJoZBuGuG\nuFTTE78PkVxPTMaFHCRF0RbArTQ/6Zo2g4UXInLsB4PrEnQDYVQb+jJoVI/G3MQWWnlBe/ITNW9X\ny6YsahlGm/Z+aHk4mI98+RFhz6wp6SnO5nWGUQTadNVNka1L76D6mmnWcRptGK7Ixm4xgcyeO6uq\naxafgKZEPpBQF/fPG1jgiJFPqj3kPLW0HxzC7sYL5SthHnp1lsoP0DhWTua06ihKbqUyuhgnOzKc\nKXMprNfNj/qRTOR104fL2MOZ/YXr6LgCfqWBGKFwG+yWmiZ05cVbfWcdDecrjqnlw8q0Lc6HSfXR\nmFUBcG8mDJXizvX75gGxgrkctvNXVx0HYa4+7HmA9Xi5gRDQf2gYCDLuQzTXIKm/2uHNYLMcIHoh\nuIWEpNLasvjuBZY5m995FPJwc8CHB/rfxV+ItEjS+KJCTvEL9tHZsxepQ5ITYkNaplyKpWZYKDLU\nR9S0VeAvvSkVdPqGnhiGr/IAtcXyXhwbbDyl8hKxUm9+i/ckY0coh8oKKwyJuc9zIlmkwkeL5Hkh\nXGEy9x5bHckd3EPOFRhi85HRQTLEC3dhImlKt1X2SdF6P2DBFQoZqG1C5WskP09FchDVEh1AbPfs\nwLmwBBiaVqC1tkApitsg4P4+IdoDHjWU2B/kqWgiyen5DqAAWIDipRQQd68zZcfGHpINZQ+cKUh7\nORJDdx/xNKFxEJcSbQcPpTMQ1Vbg7zkMpYkWulZJK4ib4yxqtmnS+VVCQO6ntP8kjnlf5EezurjP\nos5NHM7fVJX0D18Yp3b9qnLH3zdK9H0enY2UJ1WTsbR3BM/a5J0BY+QC2V3qhKwClqMSDRHNT6Xk\nPk7lvhOCSKPwOHZnV3cCiuM0PfQO0xJbEkSFFO8x6r9wW+zHBTbMMghWDPrnMq20BSoz3NSKxGyS\nR0VSLeTqaXCAv4+xBKMGQe88R0BQp2L+EAlQBTHZ6y4GXE1jkPOScA537awOjlM/pEHGmWU+JcJU\nJsE7lOWn2txJMUt42mHiYeJ3BQhCM8NTPZHWIae92Z0eV8oiT7I70TNDTm7JZ4qPh0VQWdSL/CLK\nLVASudak9iVbWaMgHYRA/FbxICMmiI8hgyAJu9N4PUWNcwLuG2u6nJF+1wr0rOYF4PZDPeBtO4Yv\ns4HIuYhDgBM2lV7KvDxASqpjVZ36bSSnCU1wrGg7weop9F/A5sYOAMloyXvbxJXmH01AWoA4cVeL\n77o1PhySVRtNxOgXD6yZKcHim4Vq3VU9zm2QGQBS1c5B2p4X0T3mc4g6Aq6pAMxiwEMrwkc2FVBS\nmvcYxqywaWz/HSEQkbFCDM5WwwwnYMA2EJxim8/IxQmSRRzj22XkIJe641/L8E5B24krEHmML90K\nom0ellAs5FDm02YteTu3TgX3FSc1rWaOmze3A3GUwAb87uC0aj5w+c3A3W1kYaCYNW1J9RJKgBAc\nc4Swjc7cF/ojXZ8u5wFOdPjdLDrGbcKR1FlN0ABLOs6eMdSPx0Jsm6tXIaDiemtHEnOKI8w8zAAs\n/v+bgJVddre5l5aRfWToHS5nzcN/Yz0l57Dw3Wcu7LFok9KQyIE77qg9zbPG1zqN1INrMZVgi8yl\nsbP35/IHImO+C8+P4ZG5s246qHQQj8CXfyBNyeJgKiTtsE3tJVqCIGb7MDby6mN3aYW4wszIptEc\nHOvQAF3//tGYjkWRKWcLXKUwdUD8WOsWEftMHnlA2VB/EowAig3GZ8irMVpgGBvPDaXTN7hgrt26\nnr1HHZzk6pTJykuDicU41ShifbATGWZHVPe8NDzd+TyvZrBoM2USJ5mEM/Jte6gp2TDtCt0yvyBC\nJQGpfngnP4ew3b84ojIXIFEVCdqOVFLyPYhjQD5RV+Ayh8hUj9ZNrcTfGqPkqN8/9bB54eA6YVPd\nKYhIQygxyLyTCQTss/o3PWX3OJgSxs5tv/0kgQ0MgrkflcL0J9GkLj2ayS9ap8g5xlj0kz88sJr0\nR2s9lx7PeVrv9+nBHb2chLiwWrDrKSqoL0uKUDQ/02ogk+HnvdcHasBt+VTDuxIDBqoZO6ekCgb3\n/NsicOKj2OrsckXeMiRFKcn5msCLXDgyVQBAj9qJ2DuOPPiEaSB2+w+A3OblA/4bRaKG/jaNVWDz\nFQjphl0wPR2JgDFj0dB9p426Hq1OQd4Dk4eJXyqYFSduPjEq6WLJp7/0cBnBeSjxPRPLkTRYePfr\nUbelQHv8j3N4kEU1RMhjNWyAbOVKP3+/mwQntEXSxSy4j13lwEvztepzvV3TzV1Msi0rViuQ+haD\nQlqDoccyAF2IJ3Q4oawHBoE8cykyXfudeeev4rz7Q41YzB1aRTUdG4pQJzWzaQKyk/lSI5M2AsaL\nx/IJeso0X+2ukCwlWHN55mnH+a7wt4yrLyUJ5C/1qTlfRlQMMcrBT7M9sTp2+Q7dR+DlE/SFoWo1\nLpc4qP2TTWjxJ7PfJOlEGDdQOnstk4/KuEyG/ScyQrnmpPQkr3EFW06zBhGJ8KJWNQarVNw8iUiY\nhq/ZFTPWQwaRIzDUUWXoqx5dsFZkVnlgFnd0PuFFDCB6EA6lwXnrpqJfxPZP00I7XDgojlM/vOng\n17CGQJvbLvbiNeHKPOaK6vuPT+u9w9URDF7rkVxy8Mvw4tPxZkRvVJORQxY48sypCCkt5cjyrURD\nmN3/gBLnUNsfUx50IM3+0ghZ7dms8XyzyH/ZDWco+bbcmswjKRz38yi1DWmPrN1fDDyRltmxEC/M\nb2KOeZuRqQtixxGQtNscFeqqbx786OdXSG6yqP3PmeBCdgA0Y6ZuhHLpgtqBXm6iCKewV55uxQ7R\noXvHcNrXAj2NP8UhNqBuyKHBD8bRQ7hjXA7xxZt7++00xnt2UW6ooFTFv4gLKvodnKFz91Dx9jST\nZqw/vSZ3sGwAaB1hUEHla/6CwgIgLc2ItDXZlKb62rfsbiufQD1DShcvx0O8DOnDNCtnlencBlSv\n614OTvhq3kTLSoIL6BQP3GbUNzBeZ7uL2cRQqsg5NDhv8zV5FJq/DZy56pqFNj/GCO+Fj+T50cZs\n6ejfKseWMNbEM9mzwpJ21AihUFgnG9YIGckVBPC72xeyr6fW7WpIvRiH8rLBBgkpyMbQH0SN3Zxj\nMCLr21kE/j071X4QbhxkZmPLxQotAvI0RaoWTW1rDgJ6qSoSfYaRtnmRLOO0iKriuVnLVGg4K7IS\nfwm7TPsdTF/pQlbPxRtwrrUSUKEnltnRTWtXw7pOaHOG5rvipJ2y/6mGXgk+nhu6YvzfMpYOMCfs\nGGaxzSH19Mhi8eH47/4mEUCxzPD+8+B4L4WjNOtstm4vq8V91Q4vnMqs1kNw9DM7VtbWLc083cQp\nTjL1eQtoMCvT/solSdJGbWxXASbl7sEWlSj/aVJDsCgcikjio01ohNAEJWo13Uoo1mCjQJ8rtacP\nAJ3x5ruEHPKpj4ZWQgpb7T4mCInywube9pd4JpsinAj/tX+/Nqaa1G4ShTTTF9gt++vc1FwyfSEQ\npWszu3ErHYJf6Cn9USz16qYAkeDqbmHInarN+SUx9NeTpj0ses2MJ+IsnmrMaTf5V8e0zCbU/qlJ\nWCp0B6TPkIFqVL/3/YBmsOvFFru5OSPPgws4CWggDzR1eiN5gzI/nUbEZOz0pJ8Sb5ONIX6a2A3D\naarfIyqvK+7eGyf1Te+6YYqxNFO9i53CrKbEPsne7Y3Of46JdExa+rRgHC69lYfexpAgfpGjGFW+\nzDOKCQRPxyPst67XF88zZ7PcTDHGgaPAw/WqVZGqLdDSNyl52lAbpIiXRyVKoHy+Au7Dw7w9nLVY\nYIe5D9WAfS/o/KkU2YXrhFHZ0eSGmDnunXGXFQJiw5oiIwR23Lw3KZsL1KZgQmiLU6RnwWP8LlOL\n8fJ+QbMADPk/bw4hRWdQlkWQ0HpdjEyDFelHHyGFZYKxxVanPdP9nwdqeFEOdP5OClchS8XNoNu/\n+WflwZ4UNV+tbCdDeDgeTcQrzDt5V4ymVHh1bbxVVlTZ5fu6bdSqigATA0R0mPXk1kuHEnx9zvsD\nYpRFZj/Y6GJtPyuEhR6MJAaq3OraYVUkcg8clg9REAF0CCsT1IJXcuqUlY1xw1+bTNjnH/1DSGr1\nL8Mu1DlDhL1Rh6FH4XI4xgIcgGPMbdgbGf5y+ZHvgVoIN5v9l76mmRNN5jETh84Q/OqPuRoR2Ml1\n/dfjidDdC/vEg0dmjvU6V+KwVbPbey2EV3Mi7mrnkrJ8l8CnGUTlss4HfyPm9ClI41fpLWhpIUsA\nY14QuBAefdGXfWfxnRmPQcV9Y14HV8Mv34QrB+h+NUgJmVVYrG8k4OvJxfuWFhumEc7F27UqKjJa\n0ccjwMrOaGIwC1o56m7puSsdoMd+qPI30UOkIQ9crN2/lnzeC6cfeBe5ullgQPQt2TqDwQMBQH7C\n6RUgfRRmeQ78RRdbivNMfxI0ERd7EoVkN6eg65zg0w8nLZ4yl0RET9lq8KZp6G8HHBGINRV4Tohk\nj+x3jOjQyHs/ouGQ4t1ztQgazn7xM1cnevoCLO/y1xs/sPiuBCNvRwSW6ooqsCgKCQ5wGIYebEF7\nqH+bI6cXbGFtG3cjpRd050nKgzVGI9SqzOugSwtzPW0tlMJduOaQr4DpZLnD5B2j4bc7FJtNFUwa\n+ZtbKlJrwxVyfhCvU/zlFvxYMfdX0zhALKylw1RwGGKScPXqeJhbaaV9WxoUK6a3FyGG+uGYKI3M\n+H9e2aIuGjV1lXkVpGM+uuSpGr8FU7QgQvwKflCTJ0x+EKkmafzLuSJAoVQakMh8NMshGAUUrUNX\na9+TFRpYF4CUzQLttiBo/cWDVkgiJ1EgQQHSI8sQSYR4roNV5Rxb+Ix8kr4wOusgXNDojLnmdxQ3\ndhEHXr4H3Fue70mP+qH7DzsRWpxF0mMwLsO33p7OAIHnXz8cnlVbBphtPEyztzyBfvcub18GBShW\nY3ZUCOok1OZ3AMV5WAix4HKql+bNXDxpIpXYqpvQBfE4uXauglKRjqOhDes4IDYXO7dVtJeD19+W\nBJmJt2icFuYkiUukEfXd8zcXty3Etyhi7iS+rg557f/phXZW+0f+A3xU4jWws7SklEcHtNz4C41Y\niQCN854l9tBPIlRpv4Hyl4dwaZs0tkBX3zqWOQhjY1uV3GvA0wxXK9/cqXVUZpCrh2c13nLiJS6f\nnWgtGr+iwcGAEfprJkbJBtOUeoiWbvO1EdifwEW5XqevcewLFGf0XujrLwbng6XRLvAshFW6Dsgi\ncj9D7jtoRHbl26c1M5pVkmfLr0nkVSVPLgS3WS0EzacwcJ9qJZ8Cez6rLQ7TDZ8OR3VNmc/Fk82i\nNO7KNaS5lHEs62Y/HqSNmPVpAsVJi5n/NJMRQ2o/dWoqaO0U+dng7lO/b8jd36uwX/mZPQYCCeWk\n2cdm/bhGao6acj3XlHZyVDMr8yvoqy1MfA79ffb/CM7WGxXa7VH8Y/566NUpY2oKOIdRnHTGpLYq\nT4xKmLmwzEhWTtV44a+zyMrXsEn9MggnXk6y/opdPHNf0hi4xzJr5rVjJVO9vkg7EPr9mhut/vr0\nAe0nvScdeVkCzAmuG0XyimEbB+TgX3kQVt/Lwaow2X0kEfCTmmW/bUtPRzYoKooHOeZuQg0w1sl2\nS0/kK9p2OWBcQ3ZAyHERlkcpJQSuBDEWlR5+KPKG9YguShkRFOqapoVNLUu1yRE1+O7AhYQQ133u\nDR6rybw8BUMY8zbQrzuL3lWprSksm4mIpxD0rnpo0juvdlp/ugM/letW9M0qj5qy1prdtSe/A4QY\nc2QiVX+GXUQD5qD1Jb4EC6i86OSMQw5EvdehdSCqGdfnZGtxbba7I3xOe/S1pdVkluvcK4qSZBCT\nreCDpXyCFP1DzGRmVhhXfgYGct+xsCXSmk/COHVLNeDWhKHnkVR2zl+vwlnL6xMgAAC2Md/aEIuE\nPvprh8JJxdN3KbtQIXbg6pa6XG7joPMiJ/v/GLbvCwRrZG9V0uPwN1nOdbjG4XIS9Q/6slM5lQMN\nlQ3sgJBnl+XSA20N/8iMKNyyNFrdHQOyn12gi9/BmHYUpVroEmLmnuIL4F3CXrf/NkOoPuj9YzZp\nNajp8MTJj5FQDDdij5HAZLh8QRIxqhKFYLLlNr+9gLzjz5ZZ4K3mN3Hgd6hqpbBf40xaYVTp6+cE\nP+Xcqgl3YCLp4vMZqyE4SoHyF+0IFdQfITzjOLZX9koNwvSbkrVUTMPyTJlGECfw81D+/gYDGCB5\nLBRgKVOK1vciDZzDVq/6OJSOchKt8o7Qmsc3XMoxLJY00P6I8uRPZ5YpyAMzZcnTinda/2FUekhs\nOME4V7QROx+InLuYdJ8GJ5gXXlSMyJOoeg75au0n6mh4p12VPBOYQUpXuuPpZc/wAVY6ZZWkvABT\nilOaZbxGvV7z5kRuJapsIJ6RyKnb6/BSw7wats6hSbe6rkZJwedPP1QqqbPnN8dizr+u5bUklthS\nlaTPrj+7avOxIhlhEcHdnaWd1hNcdXMgccxiH1AyV+JXU4e69DJBj/fzPOiFkccwiJWxzjr2WLaT\neLSGV0EpeR7IDPXPMysdktJHcUk5lve5koHMe7Rs1YKLBQYjUhQ0gDHQCO04dWZYQRySzU+tl26z\nDZm9K2JIljdGAQFttVvNBT0BsRpc7sS+cICwC2/FmcwMhf7IKIHgHr+lHvT3Gs2HeLz+oTKvg4uj\nc4Kq88J9F/mPpL5ejHV718Zwf5ztqo8pNb3E21UcIrnIYt/BRVZdV+hGqemLvUStU1L9nxaFZ4j2\nN2I+HQmTfcDX4jQZ2koMxaKtM+AM1v1x6VUPPNaLvQbOYAymWqWFUiLmQpZEowu7mc+LgjQuZLfS\n68ehq4c04CE6+7gnO2+WBSfwoFY+3zTS87ruJGZ1JJvaNKAmmi3UtBRfZ+EtqgnaSmllVjR1r/Zx\nZStwchZIDI9rzBncOOEuIP5EY6PauAVl34zhF7Q4f1IF9bCw1mE8fhPDF82U5LVPkmj2nR9Eph3T\n485alj8a2xh6lwHx9f/6mBLhty0JGwF5gTefYwUMZwzF90D/aFkxP4FQeia8UiS3tqpf6Vbejxxc\nJwn3ShK4bmGKwNDsXeMf+lHuzD7utQFxXCNdTkRHzCe5d2jTtrzpxlJ0FSfzkJJmVPq4ZOkwycKI\ngerW6E6hfAWyOJ1tKBmNJg9/BXeHHT5O/B4PLBxbQT2Fys3GBmLCd/E4ixM5qlsZ6Srl7k3JhNgY\n+bTdd2XUNT9dic8a54yFhk5oGSGWDGoeKo+xB0Ymxs6IKAtTFiZSat1ZRU9bweRElmVuXzgi4fxb\n1N88g7ju05MeqGD2LWgK45svXJfulT+OaeDhT9XpRfwtfGpFgZ+RmGi20K9PDT5vr2q+jzi/h0I7\nOnYbgjSp1vFlm2+WD6g5Q1QY+43C7RvFUme2x+xug6wqGZyvjc5r3EtXGVVkR1akblVFZRS6Xtu8\nvkTdcXbUWQbzUJrntR3HCTVFWNP0T7no/MGyLWbB2dtXTvgwqM2tvoew6nk7MPqOb7RvOZZSr760\nU+WqC4pOwz8GrPmFDPB+q1lyQoTOm+EKZi3QDVYMaI5t64Z542BjrL9uwaXUalJMYJAXM9jJ9QOn\nj87qJ4dB51Wse5Xx6lGjVQ8dY7DDxvhLPTlyQA+nFTw+7CFMtk8+zZi5gycPf9e2J1KgROcZtVgK\nhr+h7vOqd5dT2XvGALOVqlL4i8Q7EEl/PikA0w7Fj5wi2PhmQ+5rU4d5WhvJE0tVMlAerdAocbGo\npgidQYlCbW4TTsVFPomC9rE6dajvmASz7g9lrWgvda69KN9JyplNnOjdPwN0/8W6jWAbwTdZA98c\n3QQw7uhF9buo5B6kjnwUIuJ+vqCdazW/o94UBej00ioB+XSvdDNCP6Vt9ADw5dfi1dZ4Ck8s1huH\naRf3VkcOWCiCJjgrsp4vgM9T8PD4WlRuKMuoFwoCqPT4AUGc6atJs0OULSdYGgNUJWtVuGPvBCoj\n3k9G6Narhv1GAA6cbUEQ+GfXkzQF4JkBVVckGXgPmLiNo9d6e6RzkbBXCCvKhwPkT4NpceVtBMEI\nshdIv6LGZbqJ+/AYY5LckLnhclYx/1x93zdKXqtUkm+XQtSH5n8s+BEfAifyO9JHXxdVmhb3av8L\ndEhTqD/X91tbujJMzcHEKYzHz2QMvuL5UgR18KmxfmkAtV7l3mxR/VVXP0HcUu5Zv0YcVWdYNQdK\ndCiKTSZl0g/W175D1pLli6izk6X06LSBfIsdqZOeFpisxY8BoCr+rQ5Dk0qDR2mMJqXEUZaqpL70\nmU9/KgVZDwvYXvluXvIlZ1TFC/2YhIEE8OZwzupa84TzyX4xaNmOPei+ajm+ggyFREQB3/6LlgIR\nQZ4H2xtQ1qeI56GcW3qvCwlO9IdQLcGGyEDKH0cxap1AxqKT4kV7rICfUugC9f/5uNwQIRdwgdoY\nxvu1i6HFMB8Oi6eQTFIsv6JhKsQ+tUw/5LUJUaM8Z1vPZk6PoGl//R7J2sLRJebtjTTS6pm/8skW\n+x0sipLLeoVnacmH+Y2VMElQA0pbNFV9ZGIt43rSOeO2g+438nsEpKBXTsDCyQwqS4vUKCW1F7kB\n0I51nHDegIGAVAdBsbvfWzz2YXvu+PBfHwpeY17GcIrLMc9f3QrNOIxfAr5UvX2prpJ02efkYbfj\n9YjvJXq14eQZj6FddP2lgHNvWhudT88r4D1ZYcVyn+nQikFDjGxwViMrvkX3Vtnse3JDAbjus7T0\nAP8f80Lis1UiWKxM4KnlZwONideuCOv4ZfGIV0Zqe6A1JrgL2NnMU0EV0cFF5QAEkZFge5xPYfSx\n5VMCbJscD2XShpBrGMuxnfSy/0yepo+Vuz7DREpzuoD7PO86hamWpy2Z2825Fxh21t2/eZmAlHhG\n+sbe/x5TPHySL9SoSmQGP2WNRd/J1zx59M/InvVdJTE3ZGny/Sdvi8u7KLaez02kbpHdSqLxHT7O\n4RQzY5zfuyr/dKVBqSxCf8qF+YUjzszzRDxhwYrhvM3GdDWXbqUzlE1BgUvTwWIynAmGHI9PTMGr\nBCM/CzHf58TvfmblVmNWZ8q0XYxHK0mDiMH7oT38OySg7r+OIfZ9Jn9hLwn/tIttB76De6qlh0by\nChtMOkNlR+yMMlxBQgoUMyxf353EklTB/W8o15WAizEBSvOpdiXI1hza/exODddtIA7Va2EkNSQD\nh0SRsvC7KTleO62Y4ghroTD+ntVVnAFNRLIvazp9d+xGowaMxwtZaKqG1zfUrk7Ei2HR0sgnpOrF\nFijrC0E5UoNx7kQ9MfuTodv4ZJz18Htcq/n08ccyGDJE1C7kFeC6QFOcWwnGwG2xnKtu11ftKcSY\nUoGtBO1OigXQctCld+dIPr8TUUD4PCpJsVHQME0+25VLd6qVilewIgnCknG20iUmxcyNjq8TX5eK\nralXTm9CNAZYct+j8/seajOpT0QUFPGGnpE1/oTxCG0VQFpsAuugQQqVG2aXuAOA2KlTTAR6RIsK\nwyFNAYba5iOOpcUfHHN0DqbvctXoUZ659zUuOilnyX2DH0gYLro7ul5NoCXefJaTBCBo5RXegX2r\nlE5T+/tNNXKmxSkWT+bcyK2oggNggjkx2uX06QCMNujsqOeMEbDfbui0zNrjXFJiwW0PmQrnHhYg\nHtqrqzOIPTRZD5EV+AdHLfqUaN+uupLJ4IoboK+o1X/BDRGmZa1xN32RVpEyWaWfNX8Gu9ilbByu\n1wQVwCE9wuPCYln4pPNI42ZlTQnJxQeAY7UQSvKpYu2wig+kbuvUCyMqpWK4P3Hoe73QLRzPGA27\nekI7Z2XTykCD5NWbgy2BAEGt9of09lqkpVECHCyd9bjCp3/UMjTS9DfXxj5vrep/PPK7b8jDkur0\nYGjcmei9TxdmaMnuLl92RGRl2nJP83nJ6DL0BRWsR/K5mdaKNPvZ5IuEbw4x/eF5bR8KIcppNV0X\nh9EsvXbj8kiePsDfwYGbCFiNpWFLzAOirIifCoSTGNyaFbEjP7w2sNYzketUv9iPrz+RlgBDTcT4\nE2jgu1YDAHX2W9Gcog1L0wyquLudxBXHMwAeJs1BmBFY7ip/BbfVFi9XisI/BXJZTXfwhlS0Fn1E\nmpQnTvoZQT2UFo8AO+dneLCCUT5CtbrgppSConCokjcKzzAVUxe8qg7d+IdxG1zkTIXODO65J4Wa\nFdMzPlv6Pq+YijQrEHiXvtRloPPYax3eINwvr7fiUpbxM6AXc+mP1hujYrZxHDB3ZoT4QEvLReKW\nuxzorN0ygbIWOAJZ12YVjBBVI8pJXamM7TOlv/84cptaM3qclAKhLXdIIKj63SLX4Q9hMOyUMKDx\nY67Ba7+mzbRLdOpZlWus+7tWOjBd5U2mWyPxko3OTR4cu69jnaku2CsGJ+TD4J0rr+49rjNxBr1H\nShQol6tRFiW5lvkUU+zo3FJedqvWUIO+yKeNJMfE7hwpMKEkwV5U1u4bFd+FMSjLCwIV2Y3g7O8N\nLDvdLWoUC+AtfDaeMN0ssuOk2Zr6XyMUC6kpu9eJL5HtTecuUZadjaa5/xgTi8Laz79i18mbuXec\n5GaTFcJuP5SJY9uaJgyxiXfeqWAO9cNcgcb4yF46c8MIbsjJbV1mUA0GSJT96Z9vryIJebQb/3sh\nUJsvAVX87qCeL/FeyL2GnSjaHkQr+iPPW+UB+5A/B0rXyN8/2kEJIYrSnEtCT9yUvpqT7kcEBTNw\nXRK/R9iiHpf/3IjDGpitd7kabSB8DtlYSCDnKpgDhiU7YJy6Ott/cYOOaXTrq961gI0YJ/pRFd3y\nRWebA4tvMjAhDetgwwsIJDUHK8ZEERRCUE8dYEcXzi85tL/r2ql26WY/mZVwIB3Klrx5fKky02+N\nTdIX3THEbTnH7QxMxJKGsPQlnF44xech4PkIgdHuRIUp5n/AzHoGCZoOayPG/0IU5iqT1qzNfiQ/\nc8ANBGDaxImqxIpAdNJ33fo72y1Bf9V/Xh3qaEScx8B1p/n8UmTCPgfK/V2/Rda0pV4bfAjUSm5c\nYv6FwDwo9sd/d8SFY+99IW7+OaB6Th0d2HELYd9gRZLeGlijwFHQhW1Dx6T0hpY7hRu1JAS1BCTM\nj/X/oNS+QZCTdllU0euoXU9qeonh4JKRUYIYAL58fK+3xHavyyponFvOELvsh2Qr6l5cg9d4MExw\nivN5U8PqJLaSmsQzrQI8flcUCesrge1OdwijTNgegqRSMT+zLq1UfMB8X9naIMfRyvdXSSotIv4i\n7Bqow5Ni35NQ7z4sfFuQXIBn0N+JBgatUPPXgCs2CzN0o9AWH2bhEGw9JNbnI6TNAiteuMfasJK6\n0mn4DHAvzSmA9l3obGmyn7t0/N2ijPlMKKRBeHwA0zbWtCMBjeiJCZRbuDWVBpVWzIek8A6GcFd0\nnqGy68uFa8UHGx0ueodWcjrYsJeLAHPAHoNakCFyxL8cl+cX4qVjfZ0+id1YxR9xZpoZ6Y8WeW0z\nX9UkM3FgLo9A+MD7iuP3SuKt0jJuTeSPQ6j/LOtsm5itIUuaGzSKUpCvI7LJ0r9WSnSvPizxbeDj\nhMeuqJ6IS78alRhb3FWm7xl3MSUpjE3b4d+v0vT/dIcDTkP7d8WAkspiikNFXmOJrVlwRB7x9xzb\ndlBCCz6jps2nuioZUGMvoCL3JRNImm0yZOncsKCBUNhK9lQxzpd3p6hXXIKfIe7kf0Xv94WzrdqP\nVW5+Prb71yNBucprgD0nz7Q5Cwn3yR8917CrNpWbwLn6gt4qIn0sdb38ICmSRIjmXv5S2/tAgt6F\n/HES/4bZujijQMbBdZla008Ea6Xf3zcGPrDKrUxqp5F8syviKLGIvR6gb7nnotWIS0gag7GojHF5\nlmt2MZvZz4XP5VApRlkW7kvFyHf28k7RFfaaZqVMQoSoaBotQZczXWc4dLQ2uCctjIEXk83ZfZKp\nq87nAjpOIqlQnwiuU2/c8arcIoHX5BWSeQdhEYkzeN/PhjvUgN1VHWvbHRsScPubbD/mHhQgyUtC\nZOb9mpK0BmifEuPkRUc+7a94MQRgqYW0GMYGhG+e8nd2VySh6PpB3MBiqQxpsvg9w7xuQDxppMtJ\n8ece6xnOGRxij+gGvbiuP7+vjUcIj5Lcltygp/zJkZ8FmDF2w5ccTICU4IeAnkGBtSI96HFB1plx\nXBhNbj87y1oti8FisfEOYutM5g5Xbncwod4htOGc9n7CuvIWi3KnbBH3lJB/S4f1uJBk5+DTJcS+\n2nJ/LOTmS5B+fOCkQM+h2B+KACyPdziIwyb06QuNAwRes9IRXKnh/VlQTvyAFpCLX6jBkuPAsHcM\ncC6tmyYR+iYFvJXyR4o1y55PitITBNgy3+ja+xD8o+psojyIxHiGYcdNUTaz4MUwsc7PU7XIaQ3Y\nb5tZcXJ9D7benopx7eOTVpHWHPnJ0qcN1pnfUtVauei6xQo7UJm3IkjX/Jlzk+nwbV/v6Uc7dWU9\nBWwmC6erwo2BNMrrb+cnWfWlGnnVX9umIr1LWRfLqhdxGg36hhub8JAVNeMAOvp3VzPFEgIEJPsv\nqTQUDUvbUtD6HihqoZo2fjo15rbWvkY0VsRZUHQBvKR/4VYwYVy4P66fibRoEBWWamPHqAn9fTMV\najTC5gC4oKfFhx7ayJtv6p2hhOHtoWY3TFpfta25J1enR0BYMAkDUt88MaWhZ/kXjaUJn0F8hUKq\nn5aixiR17XXLknjnUsPzl9rOAKThkK0Pqs1XoK2w6yY7tGKkdtDP3usFyr6aTrg3mWClgZIIvLCQ\n4NjhGctpk+NQWv0xeGoM41NDmss1Fe9Y7E5SxNWtfCOo3GV8X/lplnbqORhfpmcKcciGZ0Wu8aOO\ncRYEIubauXDNsDzBmS7CshI1OuMm6k/Ioj9wizASE+GIHo9IJ1e9eJCsS3UiAP7XHpKHtuUUucvf\nUuFmCDUiiNRUEcgfzCobdzFP/SScSb5Ke/V/hGJErrfWUdAQIOH/aTYuKropMeW6nVw4o7UDdRwB\nGRX7K3oybChQh4uW1LD2W3CSh3YmaUrLW0m2bHrO4Jm1PgYsXdAPFAkTwasopbqMrVwWBSZaYWEq\nDwPtgpSknKmKTSmrSk9MAPA+pb8Oq2x7ZyJh4SHKBBlYP4jpZ8gJPBrrC7gQPp3e5szklfHI2icr\nkqD/eRvTYXk6U8iW8yS57XqLpXNuF4Ms7VOGspoZY+YjFnl/YY+WNrpe+a9newwt/bNBIuwnrQY9\nO0BeHq+TVSkdQDjxusBrDvDrnvYjjYeyDjguQQFTqkCkEAtO8n9dP6/m670ov7RAvjWSQcpGUIOH\ny3ULEEc9Fzg462WdlrifwnnfhYuWInIiQAm+iUxySM8TWCwiztssjmZmbQafZVt9cQQyX89HOhQX\n2hbR4swVe0K+v1t8tfecg0QYggLjzWkFgmbUGuvSjoxjz67863GPvRcv3eJxk+Ml6Sn61jIx75gX\nITzsa1NOlBCBOaoUxc/aT2Ri5vH1yVyAoC/RuhIjUa8oiZyC0STF/o8cKlHPevm8uYy7OlbP3qga\nlV+VKZ4Iwqw5/MUCfMkvDDJdA6y3/BK4EFEHchLFrx8edGy+KEICYF9o1Mt0ziAbS3QqVtZM0unH\nQcFWNn4lKmIO1M6Edd/VHi2QNCj2rRRQbxpaQAE78wYftFs9ZrKwzylKAV4C1nDmRJrCTHl2kSQ2\npNZAtmSbeI6GYs8fWVZjeLfv/1TQ8Njllov1UirE8t8CsUgO8FuDJJ1hUv/AYB66pwlkfR/mk0V4\nb6n+0WdzJL5mhsI1hd76l0dh6ebhzCK4fOVlqbolM/DJB98DTkNthHbgKT1JftKNnL/mjqEf7fqd\npzA+VUQfLDtBTivPCNqmFJwZm9H7fIMihMsj9W1BdKzTN3ghdVe98zd8jDN++osIhI5Zygrw4Fp2\n9IXv09EFU17yv4AcFklRRtCFcVzxfjVZ49JCUMWiVZFdX24ByRdT/VYMX87weYwZgXxVwAhJyPWP\n2MCopWXrMExO38WcaBU2sMeaAqRQk2O9BXQ6w3TWP0lVIvkpAzY3Ob670gjQpTJ0BKq4f447uhJo\n2us6VKKF219wTExDBEH6WBow2irHMjHj4xnk/1aAunQI4Pstu+EkI3Wh6eAKnVAFwsVhh+35SmSM\nrnMFAXISNrdNc1rXm3Z3zH8FIyxQnQe3xKWYlsTkRtMmJ42kx8kN3EVDUjoox0X32h01a4BY38C7\nfzzSu8zRP+bJZvA1oKIZWCXFVLPOxIxTxnSYzzjr+1Jcfwcd4vmMEd7qKzlnimdWai0znBY6XicT\n9OdOG7UMwJ+j/R/GXDAb2UAVoL7iuZWeNF4uQ/AqChX41p46hLlA0wRUgopppe7IxPKs8V5LyT5y\nqk6VQc+xHpdOEINdDiGcTyOEJy9TlRSIHeDIFMC4QGtxv96MNfRkYwclA7TK55g5wkN4r4pHjz84\nm+UJySoawt+bxg4WHujqVOnwF9SWTTgKHclS3RPMtysasO90M+fTu6jmkitorMhJ39GxXPx92dhd\ncvK23ROvLOlU8KgA+kCTzFFw7IdilxOkjSSh3WqiH3M7AtQ+12gu00ozzrWlDP0QlabmgZEpPgVv\nj2AkWtKUwxvQ6isJKiU/Wyg94N51qNzF1AqiAao99vbgqDS5c76vvPoGBSBrHm7MAiiKMuicogeP\nxQC+XFsYmM9/PikJh9dH3u2pUuvlR6miwQQwgfIZT+AGbp7tp7AqolC25ACdLWfa11+TwGhYnLbr\nVfdFurLuHXs8T89cW0dA1Tlpraq5an3kpv0zpbrlanrYA3Y6RIU3CHdHHpAFYuL/Df6RNFkZYrHN\nUfxEVim5sMfo+V8Ai1llsbt1cMjF5MwPF3e6SN91KG/UGgY/SiDWVQ2Zi8TOcjwMSoOyCO36bw8Z\nAtRUfg2mOHFj/rsxIg9pEkFpJdZIXogNHarwl5la1CwRWjgNedGlBvJspxZ8tnRjPL8gc9TnbGjv\njcLlQG3VEhaqeU8i5jQcVwrYuP33/9X+AAkqkc/P/20tX5QQ1uAZtzjwo6yxVHxbaYJpnje4jUyc\nqQxYeSsM+PJhmUvGszY9Whe78miXc+RXjGWdv7WSPXYXYsGn71o7VHoxv8IldijWWwIve/6hVKWK\nbZXGKzSp16iIv+Wc8IfdsMVaj6nXQun4hyT+lP94QfHzL3Og+DsOinu+GJ6OOPi9RzZwlPXdlKyT\nP7nWcbeMfsFHh+CTAUgV8matwg794s95KWR3EhJOTb0Xk9+kYM/QaGTX8LDv+XASEmO8KEEgMhR9\ne+/kD2rOJ41a1KNeoX9eItXUAkHUX0QOu94bj5l1gemgDl4hQdWM5lPh50YzOJyv0BxiuZWswiN9\nAT4BKVX9HN2U0+0qbQ3fTj2yaqgxIBWqaCgleahUvsIz1iWugyghJuD6cjFGL5MzLx9ezyf0qz03\n7H3Q3hKgx5ntwMhm8os2hm2DkpdI+F1frPK98ESmNfSGOyS2FloGfHmx3B52oJ7wPhvpNVQHTD4/\nZGSXE7vWhinkoXHU9elCxzhACsaAjBXsDj8Zg5qdzQWlZuJ8TY5NAFzlZGKXSPAgZoEGvUrVaC5T\n6Gpi6PjQH+PXSNzx6KFyd8IlJMDJF4X/uSpR0kmyK3PKZ17e7NjUGgJ48So4iFOWqOPPltz9U5Ju\nt0XPPZTeSA9KVhOvdV4XAWeISw0gs5Au9JF3lbQazpn1VL4qyp/bQjP0d5AG5aTp0T8AEP0NFjPn\nU6UF/1k2wiJ29CL8mpw9FcdVyUweXuGTpOAO13Iq2ilxw4NhNiL/HL+ZbGaf3RZit7JK1hkrGvIN\nBdZETX/tS0t90BbohCKPI1MMjKlQod8IG0ByhhkJrESykIkjPhnS9f8o8+rDDceG/nXtxD+TtlIF\nTM6NRHP5MHCoHAzs8oMm7ZDR8S5jkeFY2MNIoP007geFXhO+LjWJvSIIAROHfvvTVaJB3cia+zpf\nj+PDYHB5IQhzwvqrcafmUzbN3ErG0Vcs96nRL6XPA0Ges/+Q/eKxTiZs82WReccKOmqXdEEVkSqx\nz+Sk+m78qc4cZHXKiDOwB2OSkdNiC+S9KmnzR3kZUtspSid0rJQ/ZW5mwWuS/AkCBe428zQpu18F\nP+yBzyRq03pF0XhtcU4Hvxe4AMZUpQb0As50j2fw388PKo7EXv7/JxPD82H089RuEidsYv8ztSVa\nbWdlrwUT0qQrV6FVW2rOIzGcis/r+wT97Z7zDQCxR3dwvW7S+Sbzek9VzPpIE0yZzFkdfdQ6ErJN\nPFNXW0C3LF0J1DrIBW68U6XsbjPiurJmKu3hx/fajHULrHVFKMz1Y6r7fRDjvdOWBMSYDkJbxt0E\njuWsWN7IBqapjR9s0+zAGjtDTd1WPR4URbxtmJaIZl2ZtqGxRL4kUp6qfbAlr7Ww7CYEPqut6BDE\n7KK8bcWUzyldI3wy4tpLwOZtprD6oLYbj/cYjwt8pdgdSrIa++6hfM3kObtEnsSAS6mOhTORhhjU\n+vCI1FAd21vdu7aQNeI8F3epFn6HEVJOl3dkjc8I5BkcGf1Lwz5hnQR7sDoHTGoiSlaVPyoZNaAe\nS/sc4OR/7MbgNF6aVc2sBsqJVd28vEHAoALKpdCy93Qbe6KdLas4plw+oDqiQT67Zs7zHbhlLYAK\nDD3AN656vqftWNaeQtx+++B/6frztz6/uy1YRuKQppiR6NduPlYzXj2+krdEWdKi2pe10jv2IOpL\nqIPiSu0z5//vUx48ccPO7U2ZRWvB+6U7ATWlWIpIrbZ/2K4HzX+CU0K+GVEUulcT2Bjf/Veqd+Jj\nVc+c4gGGKqyuxVTeXJMUR/ArD2X8beEhcoLcxKWjOtMf+gtmM0sJhJbZHyfd0EXHdAfT0e8wt00t\ntcs7A0GGk43+LAOYusErX53R09ao3tVIhR9jnrjz7AzbwBoKoMfPMpTAmkfyCA/h+tAjKuCPg2QF\nbhp3PO0iP1IjHnfWEnx6S1FjOlPN6vU0NShASYZNZ1Up6tfonwUa1iu9ZIoRjYptck14x40MKj65\nCcpisJh3oeHRZk42fJ9BtQ4cfXuMkfixLxnLXcpxcCxMBk4dqjXtz5IFozO3sOxZi8GdmIKK/Qne\n6znE6LJqrp0s7ziqi0iMvdxJgPuq3BxX4flEFaX0LMjGUL5zs21iTGNCNXvjX4ch4CGuUJpwIlDf\nLMu2newQHX9gKv+qpiGcbgRE7K9tiEM4QsbxcGifWTncZpRW0OYcFUpRSDpmbvscSaEAR7SeT+/r\nqP75XcnTgp8/iNHi5BKt7MJHTozFWCX7sp6gyewkNiQrPSgJjtk28yI0jTkiUmCJfDy7JTt1memU\nlVaAkIGpxRec4o1IrvjtifOu+CFpq8G91Gb2D8Xwhh/v4sshhmHAYc4GJGbzfYeiGvW36rM8SYw3\nIVT8odDt2Nxod1SgsHTOtV7IqSUi6kebflg83ktkX/RLcImBA3yWK76epsdCQfdPKfFB8i3WxcJw\nYBO76yuqjZjwR7LNsLQRCOyleIjzbqdMoNMKpjfKJzarIqjWFxhtHgTo0wFmKQOV1B+xS1EbXmix\nCpqZbuaqzB3k56dCrsK7tcHjtGm4trxiy1QHKisDVzMvyndUefDxzRFV9J41+u0cM9WFHUWQnVxU\n6iwbYCyvOjvGM7QTkSFYDqgCWHQWhdHz/7y/ZmTlZiDlUkerW9LCNHd/sUHXiugKYW/Sw2d8frFN\n1xHex01gUlSMXaPBC0MMl4wREO1/5bpBiJhNn1R11urNbiJ3eT+dcksaBw2xu6n16eF6gMK/utvC\nM8GQNOKBf4uSm4QLKKtov7/isBzv4LyBppX/HZ3RPj43hniQ5gVZCXIxJVmXt1Y+s5HYNlwOLGc/\nzqP5DhsoytuvznWsuXDUlN2zOboBNt0zwJVVUE2a6eYTOP2JHoEjhoIDKyikD7xVfVWiOlYCXZ8J\nGK1LiTMfz/LWrd9Duz/7wIuZJuwTzvK90vvT+DBWSj8ULEsI43rv8jyDwZaE1sJAsf+MDSMa1LT8\nzl3NgWOg0hBBl3bwYHHIV1aqfJHIsinLSY/0t0jReD7seAgWpTP+WFDtBtEyOcVQau3q7UjhH+zN\nXlcqyPpLHL+dzGstBsozsKhNUGLI/IDccsh5mr/l35IBokFVgNu384w5WiotqRulM3m8YD55ph41\nG8ya4wkDdtidHhr0T+F36XHRu9ugOlE+KocwNfFx+DXRVYj3JWl3RYuiAwiRdDTV00wHRsgNkBvF\nOvAktZ+ZBjmlwkVuruSdoM2NSra1u7W70f6NdbEtuMwU5Xxc0QXlYGGDS1QgrCHbu3TsSQfJi/CH\nCCZrJI1kFXxfbOKBEQetSPgsnlwNnj886o/rOJyH7ZgNp7hVtCW0PmKopLcA0fQCUtB4npv0Ng46\nB8M9YzEsP3rVTR30DHNgJDSDGfKezttm3/qeeFmKyTr+Sk8tBRs63tSM8Ikpo/ZooCx6ZeG73Ac5\nQhzTmgZyEdLwpTzo5oJbcpPMSmXxArksGPAkDoWAOLCAEz7m5NkQIo6cfN0H4e5AZv1o5kBPzNAV\nYtZvny3EkhLvcc/+ILec/jtRtKYJk93juP3I/bPQeAs1i5VNZXqf6xqISbGHGz0b1UNK+1hEj1g/\nbIGufwAvUj3pr8vCeAdOn4bYwqpOplwjHCWldO96UBpqwE6FOL2KgQX1yMhWuWiHowAXLygQszAx\nOLRHFvQDrM9TbD9PcztwSYYQZWyBvgK+S3bGgUJumLdlqour980q8cZyEHpDewehefuy07WHS+qQ\n1HWhsY3dDa736dYtejlYfg5rCS12JqscUIxJGRtt5ZYBT2eYrpaOUg3gqPV0eidplh+IBdqeizuV\noS/pl5/auOMnXzbu/eltEZN55W/vDMDYAdV26Zcr86IEndg8Zj/nceSC1KzPs6dG/dHDhQzWkU+c\nCIIUNHjynMCtozjDsUiAS2d1yQJmcIDZeBZjQBCXA4LKJ/Q9KkppeugZQHf5hw5p+oNhmmyYtspI\nLE5Sz8s92LFAUMKqNjBCRrh9t08gMYSZgnEOwyLgsZD7n6Z4Sj4dtRax0Ohn9wCZX1aTU4JncdgC\njNFZkvoVzEedBEJVWP5oxBCcncfVQoUzVCksjV6kMQm8AllJFZZtJppTGcrYsQ8JBFRybVULLQcz\nkmilE9qRhjxeRlwM62VnxQDT7vZ02NdvevqKbC4ugFPROKruapY3sPQcSijKlijLsE0d12yNg772\nojsX9SxQQYFJ56QCwOhgOWqJJYeyL22mFJhVfmGI7JQmGt1V8bp09F8N400pEZ+/K9PHB2M4mxVH\n+skAFkSDFKxer83Bx/ARJy4p+C15298uOS2DhtO9S9dy8kSGb0UK137YChxXirgZj3J7pWN8DQZJ\n6TJyNRtKE5UnOjqCbi5XvCGE3iogK0J51f+TYfU6Phw9SFnyN+7R6jndfgUanCf63NIEzk4ccMio\nL/2hG1gUbhvmNy8znbBsQvY8n/6PdgLyo3sDhSSbeAVCe3YO4ZTKSI44wumBvED21AqXzxplzFpW\n3L7q0/EDUG7xJE5RdSa8p6M+Fz6S2jMNbSbfFB1CO7QdI+73ycU7+EkQl/t9/UdEjn3qQuM1y5eG\njTObfZSwsXQ48+M6UUUoX0uFVUffKRDleMlQuQNDSp2r0mNlS/3U6mR8kQST/LWIVCLx2bSREyeE\nNYXqT8gcM7OvDBfOfpJHejK+m08UmGnujKKApfl7z7wdZgZaB8hX9C64xjejgZ+cYSULP3Wjqqve\nMiG+izhfZQ2vMeZOsv3Eli81FVp7aGk/ITqF7GVEg1xkNQMPvEo2STO6yRwS30fIaZqDbzdNa/xd\nXVvsZDWnZ/Nwle4CqGZHlfOLeVs1N9cqpLMoVNpF1UyUNzKtC/FQIWew/ME3KiMIWZQ5Zfm+u2Ys\nh5Eay/ZtbVNj86yvjimEx8iuDFh4WXUgZoY3L8qLqciuuBvJK615ZDd9fFhdtnkRxxxZ8LIHy9SD\nfUny/JEp75RlSU1u1AavLzW5ohjlh4zIFWvu4hX4vvDhRS/P2iy1PxVcj3pHfMebEMZ61YcQ61HY\nde9d4gm7ZYb4M1qR3xWclQMgMV7X2r25IIauYdXSpUKHPLHyxIrJk4kVFJMA9Me3aJ8r34ixUQJu\nbFQSSFDgRLWl7Jg2rxGtWBgn48nWBk53tzQHs/c6XjwDYkX2j2Jd7XNFmwZetk0EDoCMC8uKwzzT\ncc1nsbCjiTZWjKzDHXHDk8nDy+DXNNSdqQj+afgQPr1MBVkgj4Nus+Q87tWLt91klfE+ps+Zarae\nmxnuqaYsmUXlCOGFqWEglBnu4qKRAIE4MCki5ffQmBXTdetoREE6pJDbrJp19A2oCO+5LNJg/Jd5\nYjB1+eguKds14DSW3xHGZqPFFBu+ZON179BFP4Bitvs1C4G4mWijRxR3DODUhprMilKQa5yI6OGP\nUGJLMqTv2l6cZSilou/ViM973U6Lb1Pn8SZvFfif7IAyRe5CXtOAcDgNYp2W8p8Udar0dJNQ02B4\nGvNFszIKkIh+nr0OK3MKB2gfdzZzk6gGHCwkzdujKWbeRP0mbasTt8QnER4loQfq5WAVtPjxdrw5\n5EVDbP1c5jiNu30JGVSuRSrHOgDj0UiqlWJ89G4JFQT0UQg1BN6TWEnmxcnbmimH2FRiFS8i77xF\n0wzif2e3xE8ctZppZDxYMQwbiYL9LcIMo4GiHiJ2EHmgaMc269lcZqhKQiv4WNwQgnCqM3fu1rzO\nKUqwS/gVypGeL1hXg6jZvZkewDn9jSoZRH2vqfU7+uVmkTouYNpFcUmk24crwjy3xbKM1YuOSWca\nw+Btgd5/NU4O6j2W6QEF9emH/tZ9M9g4HzAqHtdsQ0RCpp5bdEyMBnRASsr90rywd09iVXORRFQv\n4eJDFzv43Cbs8GwCz+p3c2+M5goKokyWakDppmOgi+4OyPhlMv0VBLF/sCMNIpiFk8nAuk09Uj+K\n9T8IvqsPqywk5TAD3WE75ZszucEAC0yqS8rPt2w5UbwHpmRgMtl5zpMfLzY7aLl4McCw+yQcKStg\nPoKn/L8sxMO35ANYT56kHDC+s1T0LSm/KGuMYjOt80iIfTjcvWy3TNGYabi4ysMP8PfrZ9vlEzQK\nF8cJvG8BgztxlW09EeDIyJ9wC9H96L+aMljH166FReQeRprJpV1vMP2oW4anp9w+IrObfaHdEkiZ\nuVWtjh6J1v45utKFsKXu+C712jkYBwVxmOun+caZjvmO4PM2end+VF431HRPxisC4ZNrPTdWJY8U\nNiaapMC/2QOo/4bLHt5u3O2/9GeHdZoNSfl8Xbs8NG1Yu3gFLemF6pWNbItR9Lt+rZbNioVguhgp\nzk2uFhiw7Fxxu0oLsFTmRLPEFjIuq+hddgMUlWVCB2zZNFrDXCTqWneB0dh90dRRJPy1YBY//a4p\nMEcLWhzGS5CDXhBCaejx2A42ogFjEeUMbemyY614OhADE8d6ClnUrREoARTvGpjSorqHw+ZGhO2N\n27NCfZNkLw9BD1nDctkNOQyz4+VsUyLvT4HpkuSOHLJTM+GhB3guXpLPfKTSuigTiN8iKk3sVbZI\nej6XuCHtQ6fzWvlasrQ5awevXZ2RGhKzC0ctt5BrSKk1Jlf2ECefLQoje9Rvc0pQDlW7rCzbZuDg\n5QKjXsXN38CEqek71nA7SmNbEaTkHbauvuKUwkM3uvNTFF54poHFoW+LwsuTzzPj/PB4HY2XH4G9\n5HmIabfb09pQn5+RASXYn4uKzBbD7iVlP3+bLjGrZL5jCRq1HRTyvDY7tKogYXSsnsdq9i2mcya/\n+MHMFPmngcJfL4JmeKpFLIHhtFycPjV9MXcExXlBKxwjWbtPs42jzeZgRPJ1rVGfBObnmhdKdYq/\nqeo4bVzo/m3QHdCQplJarjKbsE0QeREL/Y9OKEg3A7i2F36p6Yt7p5fhrItTjDIh/alkFWoJMMBx\noSfaS1HFzgDTDKztscJihgurEnKhNyK4yNxj/BcY5+hAQiFvXxKGLokPX51opRBGQNU8qk0rveB4\nrmNjftEzodBomSKXl6pKq/kDbQpUmbTD625qkrKH7oLEpHryrRjm93Mo2ciu04zBNOfJlsn637PW\nTFt5AlzwxqrhlDoWYksj71/rPSd1FtEUFCh/EPEZzAgCDJOwPLHuO/srGPSBZjhxyMXQxVL5t+Rz\nEmaRCHJkunVXeLxeinldTXUsdHeRAXBcU5kE2+OX1z8GCf3BtK2HzgX7L0XvniCBnn+80f4v65kR\nv4r7X/xBGqpmDGryuZSwzBT/+Mc8T14CLPZ9yaPw5vxlsQq+/Te32BJKGqXw2WVs/dvTrQadfK+E\n6vkuChBy3jgCtMZBR7uSslIHRWzUQBslTVCTN6PUqG9YyK/R3bvmswtgmokK+1BoC+R5wqIXuaHw\ny0xdearW3oFhw2J+6WFDG5y7TXf3a9jXYn48h+0BWPlGZEo1dZNmOPUIBKM6e8LSRPN9E7byldmp\nPLreUYCMmGFU3vWObk9VGnYhH915gYDYEOoIoMnjEdf7+J6xTr4x1yi2+TM2vOv4DbDjhC3ZWKVz\n9d3Vj2eNI6r9HywNUZ0XtRSRxANiru7HlWHnc2DXTjk+3goRgZqFXWCPC24i/wclvwImTH26U50V\nBUv1oUAhjsz5j8VOOiZmAquCsf6i8LAOk2O+ZqhcFZUJyuRD+VfH9vu1Byw4I+FeWE7SEPhfvps0\ngJR0HIEWrVd4/POFhZGBTNdju+jXZSOJZINIMy/kFEEiT2Ci2U6wk9F0DTQSKGQ49Y/vXLLo6y2+\ngbLLG9eCwmwBxP28XlSeOCX5pRZODS1sTMaq+ox3KEEfK2pmmJIM+mQsD6Snidz5ldnATL8cI8te\neljCJEXTcIJHYfdq6+wC83mKYxnLN1ZGWy5vQuk/KxtkhzI940TT4mBjADR4VMUHQzKBJYW8WD2D\nwz4K9IitzjYBU4isXVnQvYPQPutyEmZBrxeDMGc71gQr9Lal8JBgXFwnGpgkqCOdfre/dbkMhOFW\nLa0EDUraBANiTKq3o56LUIrazoTyLWztuQLIjxw+FZ6VoVEoHzV6S/L8gIB85Mad4XpumxmyshTl\nHujOnClAYBETFDjA3OoeoncpnNJgvnurYaZlW0N9e1+inm5ibqYkVgUzJDZorHBNniF9X+D4SXCx\nOZA5Cvp+z0Q2id1/0UjH+zMu6/2YpS4vJlu97foTR8DYGzK0J0PV1zPCfPodGTR6+2UAZS4+Puu8\nQEh9tG0nI/kzWKL9sWXIs4rRVY5l/LxptRB03P8VFXCS2uw60c076GcjSPLDWBRuUp9vcMz3h1Sp\nXJoNnGeprV7IE6HB6KWQS1ukRwv2XEkMpoB0h8KbnAgMrnP84mUkxUAzvLowueTMym2X2eMEuy8z\nzoENqZKE5eoErNP7Zc3hhRUKB7BYS8UzCaOjVt11TgeZgBXjIawvV3DWudGurPT7ygeKMfYfTX8D\n75l/rl52KUGucM60rH3zZ2NnF6ynIt9F5aAr8Yjw8eTQ2aAVh5nme67t5kgdXQgOZQsoFKmrIuQC\neCpvs6fRpr6PLUrWiLdE2X2acfyL2qkQ/YZRE3GveGtHrFfawF6cwAhDHTTeazr5wQYM3LpKcwVd\n5cHmrUq+JZasVVfRsV64OAIY/oCqzEBEfpdhGh/AjRFgMZ+tI+HlW0w4Rrhn6fSBuBgop3/RjHte\nUW2078vdAadeSqPKc1VOUNoalYKs0cWdZfByO7SXBcqWwsPsR4YXgsG0Bpfc7aiEtRWdYS7uyijy\n8GVgD/yk6NaHWBvqlZkISHq25cPlMceGBdxYS3CHK4vn+k+AdKO+qW4plIXNVhNHie9kYVpHn8l0\nZIg6boJgiOIilWWlN17UnoO2vTRDUFq30cm8VcM92RU0Mjw8xNSDsZgXrLEghWd0rG62BcBbBsrT\nhrGfo9Qm1GacVZC3DJc0dV8fkVp7+NWq+8EUazWWLMko2I1fpeZaILC6k4XiZud6FhNi+NkAHbQ3\nv0HEv/e8nygTQkpEramhJs5eqLYthfcxGcMlA2G/g3tfiUY1BKQmNgygV33/985vBbgIWi/Ywx1Q\nFwxd9g/HqsmzrQ4BP/lJc29OAdmgGoyAA5ziJdBk5K6+tLlTkfv4zr42V5ENCIGsKw+wCzFa8uCz\nNSl4lmaQ3YTt4wDIBwhai07LZ9Yqb8zhEbWBBkO4iIAagAqWRyRtYWsYMu8DbWvlKTlo7j1Rj/wd\nTYPCoSwSKXQgk9PmAsZubdKfPRkhGiJ3yrlPZ/14FynY51rcbaiYMXWuUatXykalFLalzteYnGDV\n49bpDtYyxsf2IMp6KdJ6jOlnZKE3/5OU84Wg7vn8QXDySvynJkH+85JckCp5GzeDiOEhLZMlgRQv\nFOfFL1ohOqHrUrxuQ66NSifxjHIn7BonFxtLu/Bc0qFCSbaAXf2imUSUq+KfsL9qtlaYHXD6bVEA\nxhI/kzbRQe0in2pr27WAys8CWVxsI552lJRf4ELrcXy6kOvSpFqwEw7geObbyFO2a2Ni2uBIKq0m\nM5N/wo7iK8/v4GKPAOVExpLlFUBL7sg/RzYMOvJNs0th3R4MYa7jGFuYR+u7BMpwrVpw3i9MBqgB\nnWvQQRI1OR5w4+1kP1QkygOd1mxgrD30OdkjPEyfma89QhEzxFYO/4bT4skTR3+QF69s9v6LEsc8\nfepab70Cj34KF4jpadueW82mRo+XyOwoNQEB3NaGdxtZYiebaBdd+bBlXjrMYPeYyPzHcXcwLy0e\narlL2v6YchWkNYaM/JOPrNOV5zxIT4Y2ab5Y8yixJpgNDhk8S+U0zRtn5yhtjm1iWP97z+GounOn\nB3ypROH0L/R2IVI4pWsZgHiojOzKrufbtlxGvf9M4YAQq4VWtAy2j6UmqnXH6uTBTWKhbqw8coA9\nedNbUNxb2DYHSUF/fZHDVh+oOF/6rZPlBq35L+8GJTBLznkSaa/IFbHHkmGUJuQ0HW3WtrreBgX/\ntykE8loDrVodKOYmd4FdR0l8bht/BlZWJ4WQP44brC0edkHgdQgN1rrbK+AuxHclL/e1FOEL7OBc\nYTumAtxBIx6ZTkKgc9sl4EXfcmPRTYNHgsj/gABnVCRlSQUXwbvA+axtqIcmsGvQvRnA2AHiBaUT\nCcnYSRNESXh/70PgxmdDOAEj3DZY7fkDm80eTgWseY/VL7drOaJvgZ5JaTUUAPuH4RRmRzay5RcO\nnlWydO/xiibtCeGfnseCDdykDdPs6AnRJeXEd1cyWeK/gojbfuBRMRjLccyPWIw/qxK+wDotIKg9\nIMccWhEnZ9YhnlvdrXRle3Mz0MYOalKeJzv2kWongDtw8+MXEqbmFSRiDZ3rFrdiJ3vj3zOWUSHm\nSMng+YrdK6is9gMJiyz3HTLr4JPV28T1N2wwEsuDz3PBI52CTAEd2xWVanS1khx2F564bHXDYgau\nTtxd9r6fjtt8KhYTXEnx8EO72XwTylDqBAmc0Vnmqcbb0fJdt4YNBto+MujF5aK57b9ANd7U6T1j\nL2nBvoIdlxd17XblgcrePLIyLM+DUjZWCPaL0f9W8j7MgjJe1+Y+h+kKsPBzBYYB/ABIc7Ukc5Ix\nrF11IRSye4eD7lt8uboJCNjZT/YDaUMdzWLDH3qiM/IKVUnRBIuCfsnpQtOClLHnbEz8HaDMI+nR\nSU5lR9mfJzS3dTCgDWwq2QWpChzckeHwcbqRGRgQB6qRNAjoMuCMJEUblXBnzDFVLFb9+yMVub8t\n7F5wu+KftCA2Q2SA3T0CHXcb3CsGsQ8tXbDhu8vJ9K/k3VfqRmctpHr+MWWYPpXEQZ3iuaqW1tDS\ne8n8tQbFnmTlxTJEgnyw2cWMElOgpnwhLtO4Xmt6gLzapCLy6R1vaWQ4R01zqnvnoA0wDV+MY1QE\nl6zxFkcRiTBG2TKJ9GckQv1qQ3cvMX3E4AaEe1SIK6H9KKozwCbMPBlh9rCILbSReEuW67vLfkiH\nfqn3wlx5THw1Yc+VGsekXgmjL+D8WgodPbak5CmJc09I4XG08Ed75DNpLhV/n3VAuO0hDJ/VCTSv\n0j7ABMZ/aM5X+rjluqNI5I/cLHA8Nt0SCpb7GWzTgNAhAagTO9QbhTHOgTQV4G8+cMiuiM0RnD1v\nZRmyrTxdKKgTQPplr/qt/MgJyPWS25tnvlAp56ZhBnFf5OUyrFFnqS3dP8drGXR8Z3zOeiLGl/eo\nVFN0HMGCzjH+5QGGwMLdylKWXRiihmncWvOz4vN5GMzMVqiSZaDoaNCDOhAFM9YCcEZ2ZY60hxzU\nsBd2s6U4ZUcmAlRRrF54J5k2jzaPxH/9ykmE4kM5TIJocNOCejSNen5i6Z4DPjCvl4vjVcZP9uRd\n0fBDy0j4NlqwGitA1inANTYuj7UDfCf0nJs6jOiXRXJC/3YwAQWz9IVYYlKysMjafU9694S9aPtJ\nYMnRLRjcnY/gW1WYFFt3FGsuSdB3CXSjoaxJFqpNWTb1JwtZR64P8zUHcE1ALiA3UVUiEgpr4MEU\nEW+etDMPdvzc3zpU2bp5yovz35aWDvaj4vtxKmkk8VxnVgF0LNaXbmdDALu4+B6HejaqsFYKiQMQ\nwJDbFyErbKlzCvx4yICPDSY49qsQRBUEzVhOUa4+zzU2XxmtlDVwSjvFBbXZon+uNNA2UBkOk4a2\n5y+u3GDH1isTT7aFNHAYd3k4R9SSo9ZkIcSGfRGm9Y3dg486cXM1i7AycbRaueQbNDNjmXQJWQ6d\nDtTQ9ZJLn2ZzHoxBuBzprRT2cV44UgvVZZ+iRDhSmqk1FxxSgOrhFkWY6n58OQ0xMiAVG5VLVJVE\na/UvG+Apyi/kMgxRjxfJlB3INZNyf3IGNbb3J+a/DU74KWUBy8CsmQQmjbSTVNWOzkLKkVxC1Cnw\nzVsAButbX7QtkIm/xYWPJ6TRLwBMB3n86xrLb3kVgxUVH3D4yUUWRaqy9kJSJhpaH2iU1RaC8YSA\ng46Tinaytvg8DQiiAa3MrN8nKjyDqLjnEJVAca90wqGuLPbhXxUhl9Oztbj79brwjtwiCnGoW9R9\ntSHnHps8r3s4QqafOUsh+DCvcezWj1o2SZswP87k5UtmJ/Pfnk4YRGRFJR+BWSXIsK2WwQ/5v4bA\n5wfHh/Otyy1kjDOCHnAn0dT77xuDLg1wvsTdvVuBM8XrvBKQsR9UshGtjxebu/ZiQZaxgd1RnAfA\nCa1HUNNWC8SDMTn3fWl/ovSh2gjQVTXxwDEk6LIoYOVoBvfXvL5jKelQKH7VVi4NoOjfGHagR2fw\nUa24+8HolBpIpqA4iW5V4PWltOT7bpS/rMkReay6A8NndkHq3EY2Fi5engAwZDk88RzfvkzrPHOW\nrRxD9W8OYcIZIGaYcFcaxTAoe3kw8x80XuSUQ207Rz9D1rVUU9j/pWta88+lWWeSnU03hwhCxMMX\nFYSLOgoMh45RMB1yS3dxSWC93oJWObyfi6xQkLkt51hUvzPjaIplTU14XwiAP7m+x1bHgjVom3dz\n4vsm8IVRxPMKMbTvLW/nTGKhM4X9Insikhu0xO1lY+WFWfUWsjj8JccwPr9FnxlbVno0ZLI1tTvW\nRqscnY00GzNASVs9QLP2gfhltR7RCzNUl2CNxsBMKNyCv9yUU3JZaEFUBVuR+PaaeJnSl488qX/S\nOyh0unjmaL2G27KzZ2ofYt6bPBCq+gwZC+kUoPHWFD/3lufY4hrrxpqZ0l+SlPjhFw0sgEPLvzt5\n3atRO4yDQghStIFJuZWINBXaT7cDCx5QCKQKBbxu66AlgnYDODwoyPvVOZDaU7U1TLIfzXWDS3P9\ni/hSvRK//lUf58iX8Nj0tOMj4r8dmYOGzssEYvQPmXSBjpFtz003l4JG8XPjXxPsF2hcAgUSjDp7\n/CwQa10HzNWHEP//PoMkfcj7NHDv4RLE9eGBkzVW5yncqHr5DaAfLbFsddTXffx5gbNG4qS15/aw\nQ/SnjdCj8ulg0Fft3W+WrwK7VTNVfcK7DSk2BhLd0bfrzMXIPBleZcv+eKy5OnOx0fj2So9qQTsB\nC/kSjuogedYVOuzkNmAjxbaJrVS/D7rHeLYmwsGxglc7DqH84EK14RdbAhtqjG/D7MzIXfIwq+Fn\n/Ez8iHESJrbYxXrPtPeayPcR0/zhxUF/Bj8EUN2FWMPMPprMxoFG+ui7u0eRNtSGKXVu7nhYprll\nsVuZv07lDqsCvtRuIJNQ9FmI1vyar1a4l0O0P3i7iPEumWXld1trJe3VQ5uQ3/EzYYtVscDhUoAX\nJmEt5Df5Kq57lE5dRxJYfEQzGao0p9/2v+v+MXD9h7vR+hJYv0OMnGp8MJAovN0JJxmx9lo4rRNa\nDh5wACPf9vxhtZOEfoHIhKdtFLeD+gDgRXBKPoN1h+CXHSUICKLAJIBd+eoECPy3/FkPTOMxCXlo\nNKGsvvECD+DEu919+PsYWXHpOVXSijygsbGBHWjRpoZ6mABL0o0+gdTLFdNN56P+Ph2q1k4w90YA\nEup/dRFExN4yGjzI+y860M0hdGZyRqGq6fJoRbA61rN6GBOex7DABjeh5nzTp4UrOBrPpoJsNFSu\nq1FbUbdu3MwqrGexKS/9Ylt5P1ji8uhxH01RoRXYPvFoKkDjkGg0/FyXwW+ZR9v16lJZ2hqD3HY+\n0iTd0R2tLJGqVwMwGCAmbgjBwdAdssSlsesHHmBxB7viLhYUC0y89m7oLmgLHUeBz5jxmLkJNsb9\nd/2c+Pf+hNrbt4C6MulxpJdvrIwi6B9ryA++hFhA4jxDzh5yfVWOz+w65zll8/tkiloQB/qzF9sM\n9gTXaNYpu3LEK4ELaSTBXUNRC36KcZrkUPmlmyOQBJJVK+ucDDvGyI2YzG4aNpbQLSk29UGvXH6Q\nDjLqCdB0uyjppg+lFY0Jjn992gM/Ltz90juZL4/lC8nLHDyXlXuvZw7pFWpF0Bb0VyJ9DtmwNnQ2\nwvmdmBpfWWGlQYJPfRIKF64wa0qHM0TQys3BvP2lC0UwXdldLWmEruw1a7J0uGUw0LZWSv2jorXw\n5lz52Thrdmfmm0F/lSuK7lNaC53Iud74bUeRqbbd3fIf+49R963WD1j1ctUImkSETYaHYLaBZHxl\nbh8HDHG7GPtbYN178a3QpV1FR/RXgGrvpKRmsBPDHMygRvzufCQiA21qmgCPShvcAo4ssfm1us9m\nISsDkLlBIwlmM7p3CLTby1OoU/Uo9woKN9bS4OZN8OA5+QzDaxm5+SwaW/qrnW9OycBKk8lRJ0dF\nUV05jp/6p6uaCAFWdsFL9pJDPya6zNu3lunC9EBOpEo4aGgYipdXb0ThMCARcesmkp//uTPfxzKL\nNkhVoTptNRaMrOah+s8M27TQTHpvqmiLXXxTcNE38r/+nee+4FcZ+3BJNLUO7GbdtnGteDLFw3kE\n90ZY3g+BoYDp7U0tuSTb2/0w4cP9MuyUOlcG6iR57k0/yXiGB7Z7mJIV9bQQsbeRkUnqNIaSbaa3\nfFD9j1rx1iDOCih8uDIQAw+wpWr7MbOEy/9Kn9nH4do8DlZP13BiSqHjPfKfQ2F0hZJ7y/YwdOGt\ngwUHDLU3BHJwnVdfQU/maV88v3lROXQ9m20zV6wlTSZNtqcciFz7Fcxs4cY5UySoINatqUkjLFh4\nswFP0HnDNDtWSlZaZvmnL/oqYEqc/OQj6gu101N2HxiweUIsUvA1SgauhkTw7r1d3m5LrzJCKDBm\nMhBqF1CX4yuyt7tVjMavdw+TglmhjEcoNf4SeFmWkxMuOVzUFYwc2os/d59wmsm6GD3hmXInPvMa\nxrVyu+RAkejqP+DxERaVv5EIiVY0hHsuvYKgadr85CUe9sb8KnxtTHjlObLyA3eZPFDU4JfZQCAb\nsym0L1GCu0DIGJ3sUVR+djYcjzG91Ov6jbQOzpRFnN2Bdxzy8kujB6+gPSewkh09n3VR67nvb6pC\nVZX0+JAy78VIR7p6r5FlMuJgYArSX4JT8cmvpeXzT72EyK0Fo/hyLDz6TBlCobHBWkrhLkGqj8PA\nFyw7962mboo4ayuwYms9AuIG/6nRYHWPSdFUbFl/Nh9NtN7qZg7Tr9MAfWX9WKPJTYloBUS9CkIQ\niG+sH6qitBqgIo+//OwPm9CS45yoWNhxq1CKMTiv/L2WBRq0Q4MWpoglGzdjCBkh3CkbA9V5RFTI\n0peiv+gELwSnEaOL9dGao69RCx3+NvMUjHKEWyTSqOVXxkqFoz7UHmBeXymFBHgKclDQUskrxmwu\ncPkjTEGnnI8QukjwRJI+vm3N2ApqVlTlKK3Oi7FzY1jl6k/dZ4GhaDx5I/v8t8HrWjhcTl2f+KgV\nyn4KPag6RgcUNorwyiokVrDYv84C9qAWoL/fJ/Ugu6StrhUSUtBF9xUVTbAxpY1iODktLeJAchey\n7ZRiy0NT3Nc+0S+CqBdQmSK6Cmc7NGHY2t4CkqemYilc6eU0SKQSYgz6D939DsGbHToor4DpoXCm\nB1fQ1dcTN0Oh/inpk/qW0FmVkfPNWHkLz7NiswJRDOlroXscLGnE2bM0BMuJT1+M3YuiqgVjyjFd\nTaKJWsGGPBViAY5mcMt4/kod1kgkTqb4h/7vXi/RLfHxWGChuV7N0shIBBOIIcPao/8WMbvQPFBl\nGY6PxLp+OVFVgWQ5s8yy+7Y9gWvJ+WpUI+LHc/gIdCTQ6a4cqbiWUfF6YpLhz9Mni/Fpk1oP1gj2\nid1XcJoq2wRHotFa0dkdiEHIkhh2kuynbDOMEFdm09bgWVgZ6+FETEr0uZDb2ryHUASK6mjEaotG\nKOVAEKurx1Blm8DMkIFfMKsDou7231I+s1ywTBTvp5IeLDNx+99HlupIJHuJBnL/59DTTVlnWT9Q\n45BGyhdtxdedYXvj/TOdy7F5KrtHtfSxERXhlONZiv0PrEkNmhI0W+7iQbdTmmpbxOpaF+8Yl5Pt\n/5rFz/DlXAMZDWjlkKNABJ5VB12aL40NTUHu0C9TCtOWEQcB9tCLsVKJ4qjeSrq9zqoCaIzfOHXD\naLKN7Y4p37Q1L0untyBFAN93QvBOgohYyOSLw58zsk658+OkMGezEK+pz6YtTb+Ea0B7CCAr7c2e\nvgB4DtOTFu0X9ANNQ5w9zg5yeoY7hgIHWCMHWSPkK19ZmCFNi1pvDjsnodgh3+PFzgPiYMIbI/lZ\nsBkSajq5tBjTejOsubwP4/hLBqfY4mVRF5RVJrPTC28ckhdI7bIxJeaN5IRPSN8yiV3sTsnrRJ3E\neWvuHDlYR9yB1b9Y/qjPDiPrUqRxkKaVG7tDzFdiRNF2BFXfsIC2bJWgeSsl2P9dTDnkhQ4JdGPR\nNSO9MBsvNHA/bL1rlgFk0pYEG8TXopbE1oEbJOuCCidKgiH6eHGWu6t67adxPXRej0i7cA4YwRzJ\ncr7KPaK8mbWNGIdef6ko0td2VTSyQoEJZAzzF6E3/1eU2lsvSashew8jGQKqwV3AasvK5C28VEE4\nN476TbQNSypWKNUnIEUwFTtkBrlMT2Y7BVF+kKMhNanvc5FPZ4xP0P5PoVyBBzUR0HpVGqVmjjXe\n5qJPZT7/7zsP8jG/ADCeOGZWw0Arfg4wB1gqos79QoSvb437M1E+sPkvjtIR7mL8sPhgm7xBKbm+\nynTSB4CrVWdySJs9KSSPGcKhfovJzztM1ILQGgm7AZgkv6u5E/R7R5aa+iDrDo5CWD7SeR6fT1Nf\n/H8JI3TTHZU+xzmqRjgK+qhVa716I/S7hl5/2+LgjsCoNs54kZ6py3CPaPH4M6VJ1gHBDkktvNVe\ndFsguXMj3P9Wl9+4F/oAn6Xf2nHPOolpLjYZKBJv5uL6OxeuSBs+QGfyqp09GkO05Nn/a2JAcwbG\nM0yfw8VJodKQcxOw4bg/5n026OVQPr43CbL7q3KNOkT8dG34aexW9rHhbDEjjQ4UUHvXn2odsetc\nmLp/U+xuon1zNIahmAVOHxdRGxdDcSaM40NBkEPx6XY4XaH2ybDo41krvk1vKmbWr4N12MAjVdwf\nENNAq9Eqm7kZJnLUPLNj5aKzY+FHKhdRzLiGGGWXCgjT9my9g5myF6zj7YEFOwFlCGV05acoHNQl\np2h3sB1W/BaN8FvMHw1ybmxB3OGqzF08sOXvQyp+7YaEybMWLkiWPknYi7dKWVm7JM61Uh1cyxnO\nO0Hs7mrbOtEvvOArPwmBEtiEpQCCrnX0MPJMOdWlraqMJU+nvkJUZXVS9bIT5TllPnOMqVYdhnAH\nne51rNlXlecN3v3VL+AWahglj0PVrhSqtRm1mTFXxoW6litGG444YBxZuABm/YJMPBrFmcwrLqdZ\nCPQL7zgVOoZtVTYeWidvf5DeMRzTzdW5ARsIUNAW4IIq1gQjMcARxOA3y1yy/DNNjPYTyEZr9pYn\n3Xn5DoTohlocMppGKxhGWYI9dGxAh/G+s19sU4DPUvqCPhmzmlwI87nuNctxUIMP+SqqmSwGpNfx\nRn9ZhoGMh/6ufjmGKMS0sEY4sl19Up41qoz0p+7mpcSrje/hTVd6s6xaO9QYUGo+tYonLgGCl2VA\nJTT3A330M1YA8dUnr9OPlO/rRkU6oOfVcrObnxqohnWq9ZKjGdT/FS4W3pUwI/fJ1MxNvcajs53x\n+D8kgrJKr4KYDd303zTj6mh6V6+Tbp1FUrtYvckhYOHOmYjmhRUkWfUUSJpysUkA8cFljeolUAPN\nbqVkOBGa2B9Fl63WRFIdBY1Ztb7a0k19ERBUShl7GudZM2FejgxN3jdORyMXijPK/DSjXeDOR8Ia\ntWsZi4DCodjEuJ8AtD69wcP70KK6syPBoJONoIIRx0PWh9BsaWOzjds7PN5MbYKfgwbDoUqIlKk6\nJrHrhPgIlMifmzuiQ83b2CCA5WxY0GePxS8oQXffmktbLuc6+CS07Ftq6M7jLHMtREtCpkw0rrOi\nuFfMNK2wqLhpEOmX/bLo+LlU6/ObkObqT8LLmzihUadHwpizaPSEzdJdlgs4MRkkpZNXA2ZocrdQ\nUcAOU1bh2DVkzA7zUG0z9o3oyL7A+V9rKmqEW2gVEsgFCggyufqE4T54NxghzdVl+AefIPKMe+tu\nCuO7KmNTngSlnBZU4HVbXPvlDsNvW+CwL54UySlgHuoOgnicmGqpJWaFwO5X/j3UdHunZfZcyRv2\nkUOFs67RjAGo5VMp0jtCT+Oy45SUZ4MJM2/46enKaGYQQZUZ7GcA457aiqPHlazvUp5qIeYWE+dN\nIE9iM13jaj4r8+DLgcoO27sfPdtDj0H334fv7fntXjeql1DaKFeq/+XmWExHiIfxfT4WkgBUL5q7\nTTYpzyso/m/sxEgEkCUW0CmzsQXtxesN6ZnolMoVlPayEupy0y1kJ/5JOlmAHOS0A7J4bVM8yjvC\ncJzjg9/qTctnDqZJqfB2eFSdEQuIODYWegFOn0VcIp84DnU4oG3H//uKhfOzK2qqX8PzZ99AtvEr\naDdrQyjKSJwqN1uBii+5TL+7R2ebonlG5PYZ9N1qXgo5dG1TCNrAweCk1+TjNHsWUPjh+Pu00m8Y\n+XDWGXYONaxhyjgpassZOzPCL64flvsY5ozoZhBrqrdsWMcVLHbo2pEeD69WjALrasrVML83JQzs\nIWYj5Cet3IQKXVDg8hB7RhIgHmBjFVypi5EDjo5UgDRY3z6XjAQoxiw/VtI2iCPgr9f0tbHHYjck\n7HBy9hGSGw9KNcCCAiZfuc8BkUjLNw0++ucOAFYJBQtI/nVNknVYrcesO0Qg6rk/122h+2jHqUUw\nBPsfZ7Ok4MnzY6M1ZS2iWgJiaQdzhK+lSAleL2TzOD5F3nPZZ8EUL77D6Q5poMJ4tzgLLJxZ0PQH\nNMO3bgo499sLAAxpkcENo7qansMJ1c97uD/0kQ1BsJ+WiNXoms9dAQBypEP4BxxmxbipiGd6tJTV\n3AMkqrz+j2lT7vcf8LtPCtB6GamwoOAfxv6Qu+UvnLW0Lq/E5Xvuci6SgR/0DoA67jCybw0rPGLp\n8NrCtmlsDXzeqW5ZAMv6TTXn2dpKPfajN4OT5CDriV5n1lsQbkpjTx2g/lyQ4eB458iD3rcPGFdj\nOgI2knf7ge+e+z3IW0kp6lW8KpkTWf+wI/ERwwo+4zBT5a5XIrIzGnGGiA5yeODKeDrgjGU81Xid\ng4pjlec9IjbIv3xIqgEL9OtaJdgy9GURz30sJconE3BnSMaQtTrrYPoFcyMMOW4wvDMwK+QMntD4\nYnbwbFCupmVfEUvxnSBxj0UzYQ2ZV1kVwymVY6lKH7wsh51E/DWzYDkCQfTa1ME6iBDOy9ljM0vR\nYDJ0Ckp1Hw0eUbenVlpkTxj79emguDmfZrgVUfR2lNdkcKZEzXXKNDvtIK8IaW8lzpxkuoN5Tndc\nIb+wrVW3WwdLWbFMtrhh5znxI/yuDPKcG/V/VWzUFhb/f+ZjAIPqVDvV3CenZFYwCx/lSXmATqED\nOYJMqvvK/UTE86vBAZR9N2jl4QyAw1UqkBMh5Uk+93wQuoIfDk/E3xKkLBnoGDvCWJ9ZoY/5TqXV\nLFZFoDarrv9lJRo8UE1ZSSEzusclYyiQb5zRvbxl6y9FqVL+HtFXreFVR4zmttG7E8SnRewocfgx\n0rhe51rga+tY+pKGOrlzq6lujdFyN5t219p/4hKHZ5HyOfXoGMmzl/LgfBn9DNEfdOszxYPWLTEc\nxjmLPs3RBa76Tu1lrqu+9jHs43dg5OlA9MV2dNfMQRzeS3kG4xNy2oGJ5yFXBNryJG0wK/VAoPj4\nXwvmtmGP95sDfyeXNVxlV/bRe++myzjk0uz6ssnrpmzN2o9g321eze38w31yVn8H71ydfxn+eZF6\nbdhBtGrDxaIN8VlnezapqlB1CgYCXaf3v0Q7gqlwtI84qHMQwDvHleuDaiBjwuH3gZTL8DlQ4P9V\nerpnTCydm8MZaoT0weH8fD/4y+89Qx0iEkT2bH7TWYHG1Yb6NEi0r69a6xgQNA+431O0OaSaaI6E\nOXXS6ZSgcFtq3i9nHOQdYj7+Fyn+DUQ6HFV6VqAG+LWk10kMCQgakT554t8xMw+uK4L4RrsPlIys\njy/cUM2UvIUSmlwtLohe6n3QZeoUyBsXMeuZ4Mo1JbI+DKNrK4LbD3LqG8NBiGrDUy9zxWpa+x/p\nh/b3p5G9BJBsUMfEa3g42mhVZtXAw1YzFbdqhtcgEoVFRZtrjvM4MXQlWgtTVAcpaS9MmVGrm/VA\n1TqHnPCa0VfmV4azZQUiu6/KZwCncinVebhsg17w5pmN8gsa6CKmLJuqm6ArlWhVyDOu6VLIOpOS\nY6tixNcE2xWQP3RImJc5wQmLdGl9ioAPnxZfqUo4XFgiljkFkL+s8VbT19Wv1Z91R7PjPogFW9BY\nOsPgJ4315EDbIPYqThCeiRRbew78t61m5z1hQiXVUWDLqMd4QjriIx5ZrgxLRIeK3O/hsu3jZKrJ\nInVLjr0QrYmzy3gC0x89oMKtLrbyucOB6HYNDUnUGV27ejkPS11CKm0TpXrEAUOLBxNpArpn8nNv\nm602Poz7FcrVyuxiywW9GuwN5Waw4ksNWc7B77Nyjfj6nIsQOROZH4wFcNnQNd3fx8OSf4LzRW/O\ni9Mg79eUvBD4F7RAYhtPwEwF3whub2PrEyqfBNafpSY0x3mUoTPxjebXgGaJagnE6YLWodvHTpBq\n9+39S4ZTw1pkVNQeYrT97t3OPUjSlk7nN92xEXkyxCo2BTxEsZJu67Pq4IcGuwKQuS4dhragfIFA\ntNvbhVl4mhmbdRyZKI4Hgw/RTQsiGq0lEzIlEZXYaQRcG0uv0f4HSjnznqMFkuhT/I/+u1gre8Wg\nzH4GnRmR9j9ajYCqDysR8pe00dgijW2ekFArvRL8kPREFPbK0ZXdwYu7VDLbOtNBA3ET16E2Igvc\nrH+mZyNYRBBie+9SdKxI1Fiv3ceTUP1um7PTXP1N3j/rFbhD9wYhlC/6RJthCqKeR8btQU0jJ5vL\nLq4PwA63+EspNq5arQ7aA4TgJzpTlxFLY42GdpK82xm95M46Lrktq6LfwLWx0/vdOOyc8vxUJf46\nnxPDyD/kAEZpS3aYSYBivxR2MnhWg7r01bkzLb76V9nBEhFBEVfj3kGAYy9Inq0y8OwOIohaJ2Sa\ngViyAHHr9CfVaKDi4O88MUy7oaXgKEBKO1aAWsGsrSQl291YpgxY/lNwOwg3MXh/PuDb1JCl1ICO\nOIbcbJgc3Nj3tjk3y9MxCGGgj7qujYMGcGlfP94ZJZ71al8/hS/zCFSvDnF2BOkwTfjIgQHwm7dr\nrertM4w1sfxB9+VLmKHDpxBBteedaK26awtvU4f9gnqkqL4yKEsT50a3Ao6tPCW7Y72qvM0yC7gX\nofU1/rNTZNOLFcVT6VDDQDN7n2sUhvMwItM+KDFt2D7ZiFJ5tWVu0GTIkc93//XI/wW9ZRt6Q+aq\nbqKUG633QU9NtXUchTMl/CI3PIlMM3ok6TQi0k3DcNz79vYD6+m+GFC6f5/rJj2AGcncvzlWOOND\nORYWs6mU4/96XroaCPAbKA7yDGIOglBJSt2rW7LIQOYYrG5O+JK7Pme9bpT3+n7uol+2dcrxroL3\n1W5Z0Ce/0dZqr97gx2GMX4Fi6Nq5NmGLFQ7PPrR4+tVXWAwbB0rxe6iE6kcGthMWwRxRjgp8KMS7\nTOfQ31qHDCMduueEXoGw1cnAAkPEYzSn8lOW+5FVtiLuif3ZT4ORteSHG8BM39ebcqrl8iCQjiEV\ntlB9M73WMyYJtD7PBKY44bU2Z9obmLKXVrGRoR8UTPG1V6s92h1u/Yx14/voprVX9XBW1f01k1v7\nMTjCADIpdPCFsYgQv8aVSWKx8ZHx+4UcNz8mRLV8XhgVPl7aGwZN1JCYcQO/xk6rBsKaF/2UePU9\nRdZMwsmI4qatm760OXDsSDvx7BhJ4qAr59uNcmTW6jM2/IoRftS3YkjfcSQBtrkPUdSeVxKzie0g\nLRtyhcprF8AZ1C0P+IvLBWucNPmpjgOTf6+UX21+xcd8zjt57UbmSi88MOMm9++C26WAxLSSd2VL\nQ5lTVUbX13jIAJWUvvXvHC8e6zqTVLegG609uqqG5oDHnvF0WYeSha7SwxWrKRXmizE3KXkJW31V\nV7rjQUTz1Y+m1l6RbxVEEE1Gy1nqLCoXBZfZ9gD9zpQnY3iaqeYpHEAIWugkJwgy4NSKpAc3F/it\naFR4CQLY76CnpCHwS/u5+CFHsDNqyzr9K57H2gNXeEcFDYv1YoTVDkInmmdN/RXPHRXkm1pA7ziV\n3hWyK+fW7e0gagtqB1zYJS33B/3ImOBOWThLboqS1v4mFx+mhCBKzzabSZu5w4p48HevGAJV3qoF\nRRXux/1gzAl2Rx7iO2w8DNhE2MvPUQK9hEN1eP0JNAdEq3LpGXaCjh4k2RrR+zzII9WgLfWMY/jP\nspbqa4si9nkkd+pjwAbK6umZQZYASMVwFjzSmpIQObfsMPZD1JbC0keaCn0NJpIPCArjYN59BO8G\nuv5IiuFottExo33YDznKhx2UbXG6N0uBsV84G4a+DrkDqA2z+2onsUXsvbRxipe9xYJ20y5ZjjLH\n9vxr8H1kOwMGHWSvG9D68OW7+1i9kXdk84156OfOBMorXfxRX46rN5prc8kFHII8bGRcMtaU9WnV\n97+cds11CyWgOBg6ZxJItwVL88wae4wenJT3ep7DkwbYOjIHshXbSKiAUHjmYrE2SzTcN9loVHHO\ncF79Rtrbs/SSzxJuvJNCzAGQqYpdRBfxMTBGTZcqL6b1bVyel0lCFDa26FGrdRZ0TN5dkkh14QaB\nodRQgtpn5oVjCm0TCCUTQg7CbOXAM9Fk2GM2LNhCp9g2D88FWpi+oOjdbuCRyltSQ0asvYe2d4X3\ns4AHvtavyn+mNN24NHuoJ+QJV7mlA7kgDpxcvSs2malh7+r2Sa45UYdfkKX2m82M1XG+Ef7vzATd\n+b4EA0QvUor1dn2L4SVuISWqhCSdbdqLixqUaB/B4PpKbFQVN39XK16zq2942eVOZmKB6SbvVaDm\nCXQhQmcFGhDt11rGGj4//tNyI28FXdiCJP5Nlqp1zvTv1nXAJfTb3fpbykMOgUNKJEzTCqXm9+bF\nWZfd/7k/AytlwETFe8eRZkCgdjJs4VHGhpLhHdrU9GmNhr94dWReQhYDrTpCxoIOvLfpBp9IaDTK\nsTwFy1JI7CQT/v8CH4aeemdI8opzdgEA6Xu419jf3TqtOKGSu3j91Xc7c+0sb+du8/VZyo+UMeEY\nEH5IHFyElFYYit5bsPjulOC7VbViGtb0sSkd5KLwh/KiEq4CPrkfACKe6XMVO+38SP33eWCwFvWr\nFqDPaQBGTnvsSFl0DbJyTuE6Ipr3PODOcmJcR+pcP9TzEX2EUs5KIN0X2Rf2R+e9GbMUxuZn+K5c\nv5ao1T4EsuiN3pKRpYbhIeQ0LNgCaMFgsV2Le1jdZExsTQZKPB7Cnz/fwqa+4DyOuS8eyKm1lYxu\n1WuDx8U/Sz3k8Itc5xkxysx16CJBKm24E7SkPlGn+8IRbC4MMztl0VO2/y5VfwKg0wCudNWPT6//\n8YzQdwnCvVnBHNLcrtPJW+LOGNzPI7KlR2NRQuJldbhiYqXuLs8iySVRbpySCCE0okugN6XESinU\nPwiZyl6+YrYbHjRyVLI/TrAHFzkfSJWueqDdEzMCr3rUTXxT+RocLoj+sreLT5tppSfPOv6RC7sP\nTDDmZJO+Nf50yWwCsnDKi4/ZzRx/0lXRQLO3AwQ+znrjHuwglq5Sz3zNqJWKMDJ8N5SQVUa3gkgn\nMTbrjCS6vVschm7Yl6t8kWQPQSrlp1OXGU4pKDqjiDehrlRzSJp5Pbq1uEPdv0U0faenw8ZVeA4r\nH39Ncy1t5VHC54ChAw3anKAvWuwv/axTER7HriSnFX23nGsld31xm0Ii19hAQEj8pnoQiRUXYn5x\nf1hYm2Px4onPQI7TP5eJwUbgWin49S2rJy9Nb0ch4x+xpZ1sCOpVrO0u4N1MT6bmSLVxtYllDbVn\nIK3cnlP/pa9ZAQi1U5lJsvlvhl7NJMltrGXD2BE4jTo7vHvNQBG9MTwSwUHtw11B95BeMGMBJHXJ\nLPDtNOdTtCeHegmtT8gVhRAwgrxuy856KbSwjNemwXE+K3FTWNkJaZ1MtY+zSjtvXh0t5jmG9TMa\nnJNzArU3JN0jsDyqssdvyYei+DBSujoI7Ch240zkq0D32cpn7hpb4OzYhoxzFzbZ+fY7DhBG9KP6\nuMj/ouZgYaI1h/eMPIbGlJDHcHcJBj01zNifXUh5BYBmdpgRvdtB4J4i/kEav0CGzDgu9uEZ7MCa\nS+rUWwIEHt1QIRlslh0qrk/riIs/Yz4GwCIRDjANqaq6UUJhMGy0wL0yDlRvMLJtBVUxb8pfBRuw\nM4ilm7gdN+ThiEhJ5JK+FLddvkrjXxIxp7p/lNisA/GPkXMdRK2H85Ghqx2GWaVlchKOjaROz5nF\npQKGhplro37E9/3fUyMEMO5mh8K2rLQ9cU4jAtHstKn5CMUt6I5eqZ904Mr3emNe/Z+yYgWUxb4C\n7tu1GNWphQ2jJmVTGfs/IkUJ4cnFusThiWBpL8fmLmuutVYLsmNpO/J2wj86T1hcme/qEvBSvrkr\ncrs6a3XC27lWVHKRvhoFZjD/53lFqwKKqKFum5z4EFFY7h8Ycd+xCHWsS9d/S5IIwuk4wZDd34eK\nWKg3lc3O0vB7WP5NKDF2ltMYYcThljuogbWTA/BIKSDX2rlOyCIlJj8WUPiqnNTlVxG7bfb2wXP7\niAy8anmQrM2nsoJonHmeUNdEFv9Ds/wdcHIuLJG2i68HIt25u93nMKuuKrszZ/dgS+wF+Ep0fZCA\n1+02jhmhnqBO+a2JcnPfjKxNLYiFQHMkfJUUcF23+4/WNSZ25CaBBOKtnNlO09JmpCOJGt5eZunz\n3oLaMLJnjv+bdr8jaZrr/qaf340sW2zvdL4UmpMIZcdU8IdzoEjY4AXDi4vRXV6Z8YiM7bXq+Nbe\nukxlTS2xMz2FjnF80CoRQhtOu9aBVISWuVinW3MUmBrYlFAB7c92MDMwJ2oeeIdjio7piGU0aPS+\nSqxrJghRgVCx7N6rc6uqcc8U0n7pQG7JLzghKv53m6Q2OZlIIjXHMVtFRPzgV1r7F9Vfn4wAa2k3\nAsqbT0tGh9RkkNhBrhPeTPb6U3nTRhXjHJUBEyy0sjDffsM9UnaX2stsb7UtyGwZXZvKhe+5RC+t\n8P6Cvu3DTHCCDCGkjWsY0ppIcAqtWaaVBnrOqqliUWUpBZvH/1ffdUlOrHMp9vG+JVYaXtdCyWrd\nTs+zlho+jlCrJicubZNHvm1BKMAFWPzLOrYLjp8QCEEdFstg4t5pjUT8NOokcpLXuePU9mWyFw1m\nVXjMF3h4BoMFIM6CkpcjnjO6ck5m9faE0bWK4Wz7kK/6zmQEBFBxuKWGIWNkluxmOKknLyvmYn8S\n3zqc66Q/zipfainZxAIKS0GPRgyOg1ipo1HYfbMOVmZDU6jNcWt+rr9RDYLO/NPR8NOHZfDWaNGe\n0YlU76WZALLEu3fsTi8UDDqbQArrg+ohOFRFfld632jotth098n0D+tQbcRRq0OWzQejeEB5Mayf\nr/OOmp2LrPtG+EqZKEQ57XZdj/u8aNiizjfC49wDAjM0WzCbVckZIFv1FfHgRZAXat1oPFxAwzml\nr5Y6DFpcmZRsBv0axq+13YlRMaj9lD7105Rxxz+SqoFkNABmvve8QIPEesuZFRR52ouqPpuZxgbU\nTTM4hyzmiyh8ULYu4SbCUM2CZB8xWSNsMAmc1YPjOKBh3OTszVkzjoMp5kC4AdiCHcangT/Np9+b\nAb2a0C/2q41sVZaQsvAI/dpMwIO/7KtrPkdl7FYybBPzOX4skxrBpnZiUqATABxCkMD6pQd+wQxo\n8oqku7xQkKUs7x7IlF1R+sTBIm6wIIUdeb7rOACVqrw5EcZrU81SiHHrbY8xBX2jWU29nVDWDmfu\nuFiL3yDaiRpjQzBB/NuIDJhrFgLQJwUPovi3iQZdmDUVuuOP6WYvAw/SP8bDCC5WPhyHK9+Qck95\npZSu8I0j5UJ/ODj4wM/NHWQJ97LLozE3iyYNyAnkgPvQQ+d9uIa7PorGMgkKCfBSOlWqWjbWuB2j\nSvUTejydD60sAy/zkQ+mYHsvvUDE4s/X/wVvKjTnNdREwAefra+Yc6xiKIPHSvzG0whCepqZHZaa\nuDyodA3zp7wQ3d7lXdc1BBNw2EL+KPZyO6OyluLfG1JBm2hnhfNijwR3mxJ6bOaxwwAJZlm/xnc4\n2VBD1uIRptOKqaajA3BeR8csnCIY/6G1g1NBKyB1djwGWbBGG1nnSYAe82vKGdW8O8p8EqrhwHPi\ntZOM4eKkEbwo2nHXsPn5sC+6VYjlnrv3RkIcYkPH60wu7N9VRENGQcEAD4OArHpPeRSMwD5SDhHg\ntlFr904uXqhepADAmJBHBTN3j+l9esaUE/LH6/ju76nWhsEneaDUN1rcO6dkNfZGZ/Jb4Sf53+DO\niezZOj4RWYWiKS8cw5B85HtCvUbfSdGusbOOWbUYZGPUlp7eZF1L+rY6dQxwAk88D72FG6d0jnFZ\nZUJGHexAsLeVyLioQt39SkHqxyoUTo5Z3rWzC6oCVpBgdwVKem2kVf/cMGJGFuIX4aQr82ssYwga\n5zSsmdonZe5uyCpsFJ3zREIUisf9twR+kMOaDE+S8DVdEADQJtDUtkCuKr+Um04h/eXBJ/sgqGEe\nWO2D7gZZNLK+WpkjAh/tpkbnyDS0incDo61ZrhAA9sjCKT56v6rkxyXs7Ssfjdfa6zbTiIheRLNR\nyICMtt7dnMu5tZiIWXfRy/q0KtdMqMUWz4Yuk2aGR6yPuhtM5Kcd4C0o7AnKgjk5RT8FAl/EKMec\nqbGhStyqiVzPAKmjknMgG5PXx0BUQpYJMpDCHHNt8N9zwHpCMSuS8k0pEmr834Fg0T0s1HSFsx16\n8I5AyQxDuy39XMR+cvbJ2egeROz4OiCL6e549S1qvQNO86I8lF4L6HRqKikRikihraq4Q/6Dj00O\nvVR0gYPvUX9aNga65MEQN9NubMxxAtbNK9UOkmZl71d5TAr3+fUH+RVYpqCSzi68tQ5clKvCj6Hr\nW76xeZIj74P8fP1RRf2qfJzU79+9rG1dS9XMd30TlPeTTCbIq+0L32off94sNPo4R1MVNqi2km+X\n+v6wEqNo45Y1QtA3p2BS5UxYYz4zbCBLK6tQ9tQQIIyXMORv+umvcG7oCQvn2bJ9yW1i+m1EXEF/\nBgWvBlVDAiA+PJaDw2Vdx73uXoOwGtd6Rc1qz+TPnoebp85S+Pdmj7dNWzeN++lHsW59rQm/Xejn\nMVvFSHSw51/ABi3BKIZKbVvcGUPRtth7uShSRGg07esVgz3xGWUAPobqw7o/JZPlE39HGLJyKJla\nYYB9rcpniCojAZ9q+prxduhpGLq2FtcjGNKHcrt1lvVQq7rY4fAZWaisTBuF4Wqq4mW0VYFiU75w\nnZwJRKDNaHFVhF9dQ195PhlEvPHL2Apzk8Q1N2YbjDt1ipc1ED0zXCqPG3gWldkq7PNk9qACUCHi\nKFsSyqhZB3E7axPzeMJ4K9KHl/QZfvsevOX0cv2/cUul6BC9QtQWPcVj6RPiz9H3AiSZTHF6+P+N\nW7qpIvTl+vgt+wlJ//iZASZAKcXjlzAPVU+3wBRlgYSZsZC02BvqrBUP3O6b3UZBE5TJLKnz58EM\n1wTuJmozGNFhYHttqSZrO4QbLuEEQHoIuYbHitchqHF1f6SJmx18jDwaWg4lq9o7s/z9Yj2uBp90\n9we30DE+kD/8VKJuVVYvYTZoUp3pX1wj4a0kRhlC0QM7/ZcD27V9RfnDZs/oY8m7s8Iqb9JWb6e0\ncixtiTVBR2nb0iB69WBNnB+QGAywVM8yRBj67N669E3cImkrzzTLwJRxiwi8sJXXtp+o6altl+WG\nOHamMNVO0Xpzdv6ucWj8Fe8yvxRCeDXMjFtljOEv8DsGsw8fzSZ4bKZV9O6PxLgRp9EE7uWf+m7c\nfaf/3ovHHj1RCmWZUcepSpNl2dF2kQhCLX86ueaOQmYDnxGcPLGCiSWdFw+QGf6+5vyarR7MnJ4z\nhhAbyWOsd7hd29WAoM6dnaFwLtD8fT2FlcpbuiYYFbF0i2SucnqoFnA2Yi2vE95h1eZjfBGefRIc\n3OrIX2UZ9bhrcJiBiLNWEC26LyRph8yFLiucWv3ZWlvMV8rwlG9ydRdNmkIk4RU7ViMdYUX0QIcN\nGA925eyJRg2jv/rPQouM8CkoYNYsp78sSp3JOlSTzoNbl7dDBAHSn1iJvDhMxrDnjTFuuB1AeoxM\nMz7HsNPCA9pu6CrsG2nSCluAZ/sLD5+8omxqD1eF+NhyJElQTPaUXA0WOf+DjZgBd1dko24ka+1b\n95EduxvGjA7LJkgS4puNzju5C6Pl2qd6WjW2iqSvpjLZrYAjRJ+7xZHVLYBPnxhKL4o/VkNOJpop\ndI5Qm52SvXuw3ZjGW49ZurrpnK6/XuT+pbLzS6Z3pClUzgDrht/3j1CUASxenKpVZzR3DGF4kiyb\nJzIKLpzXvfKWtmOYLidnPZsWorr8GxL1KBeXe6gFX/wBxubu7oOsJh4haDld1f4rj47QHokgr0No\nbk4WhoqnNku++V9QtLa73k9a9j8bN+IcA8DZnEBRJ9TBzVswiQYzbsi2gm7sXRw/gkA9q+P/YMFC\n+KMkskbywdtc7mhsadlS7j7AUH8TzAQw6WftTTvOvteO7oTKlCi8gqlDHy8UWTbHa6JB67IRlJMx\nPqTbC5C3IELpbuocEU85RzHKmdUyV7/ghlux1pCba/0Gi7VUb4QMIiwj4su2T3rxZxzTYm/lyLY+\nR+q+kfd8IgsgrRbTFkzREuaEnWMPRT3Kp80SBZwYS6JzUE943sSN69xjFUFWxlcFVL41y5BJqSIV\ngjshoUybWCbZFXz9qmRGSAuUVe8mQzW37+kgufeiQSxAF1DD+VHPobCU8Jfn+aOd6YDyWPQkUe9q\nijpRLSWw+9jj5wZ93RWrD4B4C3RnXJCAZNxH01Q8QYkNdbddLutbA8hnplyTXv0p6mLBudBzgoqR\nehC4IhIMRuUJ/16WTdQjQwVuciXnZqHcaQRRFHNURsa+i7d+/88XX8P1DMqKI5joO34/pW2EeH/3\nSXMo+/gI7Ybyp0YTrzRehMuSzRTDDCnEat+knyHg9jzDyewpo9yFeepiMz4dkU0W5BryK8MuP8UE\nAgSvUaQqIrMCBuK82370Xtx18NYroYEBLBZhJSo0tFiyOkYLgr0/g6EH4o5UMbVYyUNYUVeQO/d/\n47IIibS56T4RtRez+P+oHB0whwoIqE5Z52gu8/I0juY0KL51C7qQTeI7Ch1iexIb4O9OmvbULPed\n8bBBFtdLtNsy5mFrWHfLM7HTpk6/nEikAujtxnPWqpDjO8pNXctQJ0NEjvwBh35YAqXcb6iFcxF1\nzS7fMaMpV6UiWJnDeUyHGm7pMcmssCugVrXNU89QVNvAQpAtHMREQccYipCVLhuM4aYdVXtxUPG7\nb1DDRxTelWgeWVT51he20Wi2kylO2hBIUzimuNO8sZDEZzszx/9zwby5mTFdIQ20dKiDJb4rksxi\nBDXXFgcCoEnerEWtgAuz4oDp+vneOenTpcvs1kZSRxXfol+GjvRGvqTW5pFYFq1IEjHzTubRLojf\nAZhNr6fT251dvh8XBBBWxys73/uby93p9tckTXKk6PoDcnDGa7aMDwhMwcWrxLTUmNiQPQrw+K9d\nVE3fSJeOPt4B3+nrZk4gJlDX290cClcbu64qOXNiZbvFQe2vUxTgRmsD3CfHAPAFzhX8h6iuTvYO\nR1bzGAsfEIvILkeR1PlWORFUhGkdrxTAtkizO8c8nF4AysO0MMPuSAa2jZJ8yARVMY/i9Q0uLKSa\ntszBt/YUNL5p7QTRXvrqHG1YtvRVqnxnzQ8N8eemajthoBEyUaQT/Ki7NzhTuDtsLaOq3oOGR4ww\neviexOWpcEBfJ+q5zHQyE/5s6gWeFLcMxgXt+u13KTvRhsP65fdCQTqfoybNJbU+34YVRQoGUcdW\n4s8CUrcsvmhZwjyyIRinERWQr1x/QrBp38N652wT5zlE8xlxmf1CGjTV0wnDhLGQQSSCy7pGdywh\nCY0m58QLGEaw7esfTGzlnwECEB6wIlPvZ67grrNxkm2aHKbh/ECFoKkoJ2UprANyXdIeBl5rRj9n\n51uao13ma8DorXPw8HxeSwaJQ1yzJBQpFtrJLY1gqCLQad3lMAzSYMzB+eMwCsyaLJupa1RTUHaG\nLPrzPHEEpfKw6jnVVajaFkcMN7p27b/yaksU12nH9LNSOQVndWhM+tdUhSR3UjypkAiJTEHuTZNK\nzkhJkVQavik2qslOxA0my7L3Dk4+F/CcspUoE/4sVpN8ZSHaRkSC0jHqPb1HD2LJj1bZ+s8L4UlH\ncBvyf46bE0bP/SeSZyOaMuLyWCAzBNeCL7EklfbRSKFpDpMNFyDecGWisqeL3p55MIZddpKiLSz5\nlsFiEYt5xi/sFdGoGnaIDl8mbsMfaykS3uDW835xr2v28QaHShq/iMqrLmPqwlhj6yN/H5RUqplj\n5q/wWK3XgYQIY5XMw2BVyJpZzGp2IEDOJkNhI9tjU78pVwNqDDXAcF0zlGTJtKjxok1vValXbW1N\nzfCgy7lLs3BFtYCpCOujuWQRfFHqslVexbiRYqTj9ut6AwKElW8i6N23/cUWoR0fOJlBdmVRv81N\njvZVRE8Ht2ow/nN9xykfJz+0lkPBU1ZvW9LvJ6rgVbSum67DWHMrMoLcJfZu31FRRFF9nJ+D8+Qc\nXkO0PcejiWqr9FiAGoo9wCDdRlKCvT4U5x35ZThRG4CPJJ44G5kmHDw8/Vy8p516jOtSqprd3RVd\nK9E+7YS+VfW32Eo/9T9tpzswL1w2YMMtt2f3WwNsDFlTUfnV2KLteQZViWnDkZ+nJ+LgWsag6e4W\nXDLHQYeknAzabAxIb3AKlG4gZDAl6NeBowfgIip0X98SUof/tSI9S5ZryH75K0+BoOsBUSjZphyZ\nZMimjs0oqPN1MnFUW3aZj6xOblNoKCNjwoeO31djAOD7o4cvMe/5SI69OWwXU9LpBglXukyhMAXq\nVTDjbWZKuZzrdplWqT4gWcpXuwF1OqA0nie7I2eIMaYcsmHWbIzhrvusYMqaFfea2IsOsQgSMNzF\nq17DI3LQXx+s4nfM7RkEcOU6KkK4TUvwBKp1pFIm3lnksbNGlHUcyoNU5juiJM3EJz4p9KUn8Zfm\n0u51Sd1MFcFc0S9AFxZH65GkPRcl8U9+FYddvenw3+1EhFQXt9T5IRrErcm5Nht2a6mw3fzVQEJI\naAm3kiXAYattUzxnZO5+1yEzM7G1FnPCOEENB3RrcIRxH4cu4hryJGZTBI1sFp4xAKs8MlsDZSeN\nl1TwbAVJQl74dA0XDFUFUr5TNVR74Ay0m6yTPVZTp+FHWXtrfj/SSOXsrv9SQI5OULnn4+ltBSCE\nh4CCKGpKMg+H8/z/DkrY1JOrXb0hOJFyS068ACQ+YOljAxwE4Lv1djoxbBLveTAFvKVJFrUp4o1W\nBhxd53OCDRmRYqNUnvsMZCNWS+zbq0JbtfjpTiRxgOwghIttrJDVSHCtjQDWowunt6O+4N3CQyRQ\nwE5dj/U++4qDo6bTxzbMQs2H8L4Kzl4gRwlWDe3XT1IBN/7WCDoxHbDOIzKxtyc9S/AaawWCQjaW\n8YNogaVr7LOG5oPg8dIivfJiV8X6yvdyEKuJ2AY60TIxUeV6RmJbfY1T/EDiKSlZwRzzJ9uxwTKB\nsZiArNVZNh7P5K47YIg4Ur+9UQH7+4/QkZLK/Xb6vvJPJ9+m38hmj2+0FBS5gmCe59nT6UjCsXed\no1A1OPrD+Fx7ikSdLvOeIWoSBlv8H5MgMzDG4JxWC66dFnzifMPnMIeIBFjww4WY9EKy1HSkbcSD\nOIxF9F/4pe84OpFjNWdUt+QZFPLHSmLFNKIpQotxI7Xn+ez0OqECSPYw0sHoEqYElOWHwHqZlVHy\npfPp2njdjx/GQ5j6lACLgakCks8g9dagYnlWmIl1SJgWvpGSwmAR9j42VS23JiXIRq+lqTd3D6jM\nDVuDAnaG45MJFH8F9jD0SMOl8RJD25tZOlD3HRGCFhS591HOH4refvO/D/6UcDYvlOYIJ3JXqMdi\ns+wkzl9BTRjh3eS44F7KxLZaGHKmnq9hu0iB7kmvOYF9AIeaRxHJ+qP71Zo6ukpuKeq6lrLKngWP\nQw6lYsh84cGEG605O+aKu54VMHjy5j9NsIHoq+sfYhgRTGbaPMgtjcNmqrOmvmNvxQO9zJJ9gYHU\nOBcd+Z8JR5nv3o02K4SXgYDacF9dSq3lFBJ95kpFSTBEXGzNPWktgK+x+u3D3Xh9ATEJ/JN5zyJg\nusEg5j9t/7OE5TwmRRapbzAgrNgcpQZwno0laUQHT/QGMDshRsklRVFMPpqUS0FW6IULgGkPYEcs\nOYfpeLEnDViX8pXSj7LIvmM+S2Syw24AW+nVJt9jC9vnxGAhVpI9hjo3p2KF+HJC5nbY3kcbTQDz\nWP83P2ZYAmm1eaMPgiige8aJbu6w1yPg0dBZH6E4tylLcaqS/O9hehAUy5S8FXSQrGsek00yT2L/\nzo5g/P3Nkhk7JrUjYhEGGN20OknuqUCYLv8YPBr380mqUwZRLZdX5GfGiNLgo1BlyzF1whVQiXxU\nAcAFlT5TmlPBCykSoQ8hl469jhaZnrAIq/oY4yGGiFPOTr9qRzNuMPeVfJadctbiv3V1iZFZs44k\nf0aGxwHewhpkSdKQYs7XfGSmgNo2IpYrXHULruJGFQrsGgdlDplkVR9OTQ4yTge0O1wgx6w9XKOh\n1eT7dZEUYIr/tfDahmbCwynlVKWiqT5YnIMhJC9K09Q8TrXSGbomBvIcshxcx4GVvdHvda5glBVY\nduNh6LBtrZu80oW1+rOpbe4kYqc1/9nLUVoB+I5qnEYHbxkRYvBnAcRQtvH5d9duQ+f3HL+G8ppb\nw0IF6ZT7xrt7NbUggQGNF5ajoGVyBt0a//13j0LGnLEPM0Lgu55dYSK++uNqSQ9NYkcQrWvQWiuq\nzCackXk4fYmfi2yDQGo7DWg8HTtqJtlNyL4//WKQeAshl6nqaTCawSkQqpXPCfEGhB6HdYAfmGSD\nUnllOuCyrooBKV2wtkfkv3HzBa05WppbEwJsYt0ZUKW5/Nuk8WuWcldmRLbvy0ac/gSlMieqH4tD\n9UZTgjp2iHwa9rYpgcy5GwfGv/8NUpGWWJb2E8NWlccwAgvQqvOvmi7fgT4A8F7QU2vJ7i6rHQls\nq7YTZ8jgcLMwuC4xe/l7KtNBusfuNDk6YId1X1d7SjPa0j3KFP4cYStopE4YttNOBKdosiEi2DUt\nsTJj6gsR1acBohVpNPFcOwP8ORCTqT8cXX/YgF2Mu6iTf7YpbAmLWC0uLGUKaKRZ8VKcjzfbwj8G\n9zGNybrw9/b+YMW2C5J82Z+3WRlv6KV62+xeqxLtyPEcpmG+9AHXR5SP1+NGR5kNOdyOiCgGbuAI\nZ5HI7J0ElBRFInMJKmAu+WD9HvTYvMSrhQzwKXT/dUJzC405daLQp2/WJu020+gBKDPkvQr7KnmZ\n6p3voR371lYuSOjQNfUkh+qNMD5TYSLBPIXvcV/xUMCrEoW1JHE7KRflasLg6I28oW9nrNClElHr\nw0Rcq8JSPCFntmJETR2TsFwRluDlHOPrhmhIaLA/xt0rC3UcrQSlGz1iAIVKlYh6IEemnSgPe9Ea\nVZFKhgxzR2NZei8mPMB9D9eatKlY5aMRpeH2INdozU1zTKXAKNMp1wJykTUpWXoQ+pKREDNVPQYt\ngrOhCDtAuUzwWJBIse5uuw3vxNjDazIrbskskHb+mB736eGdvYol/ONimr4WBOBfosZ6TUQ0SVM6\nm4z3TBPPgmdg7ohn9X23iLNz44p7UDUZCgpR5rvXBo04wbihn/Ly1tiOsYDtuIE6s4rRzEaBXm2T\nSdWnIyRrJ9gu0TekRHVs67wz8bswW6uQeCFeKORxShYG1+3bF/6zEjGiLhERHfMTHgGwoaiR/5xv\nASoOQwIy5FTUijMahvTX7PSgDQRO14VNfoZEo7fqmbP7S8SCidvFuDedMuVaEbPrXfDA3VuUW8UU\nRFFMtKsrDyzvFhRK7RLPkLwK6UMxm0I7TrJ8hwfcDEwGusQT4faK+o0E8ZruVBf7OgJOCAmPOzuS\nrjcS7ql6rq2eHZVrd5TNo68EblcNAY0jjyJJf5WTa0un5v81o+N7AvJQTkS7Q8vrFErYu/GO9K1o\nvZNIFJ68w0xmbfcJUV5LhetvelRjWBd60D/4HdsBgsveTYVGmN54ITB8Cb96KLY3D47DbUSXikPW\nT1l9oGUEjnSxgEq0Yz57AmfdDixM94E9phAL8SZxXDKLf4+35zSnMBg0Dgk9jlmKsbC+JSet6Bym\n54PaSt/QLgYhz/VosVeu3ah3FqGO3r6hnlM/PUMhVXTeP5NSGTztkfw+8ezJadOu4ClT5eqIs84/\nFelzmNYFkJPTaGOQkasoTTq36EpmdfUdZVw+Phb2d9rNrOEKl/Yb+qFGClP++GKcrw5zrNjDICBI\nuIbAaRq/pnj33UBbBLMzzKRxnTZVsedOTcBwQJsFz9wly/tnHw13yaWAzwfY5fVkV+S3paCMGPOB\nMzW+S1VuQuAc+Q50NBxdLwAFRSZ56J688MilUQBsrM0CCDlLweskjYNBWufwfF+kac2kMw2pvvg9\n5l9bE17SkBHcuLuJ3UKmqLnLB+eq5iUrYPOzzE2iyVP6S8Yh4PyT4l4uXnWbccSI4QeabX/ikmn/\nzSWcZusZtwKiSJZOag+1PniuBqgSF4adN3Cvt3TMHAEeNXeFv9a2KfsRPqAh/3dlxse1Ak/s1zj9\nzJ5J/bSJllnWjEGqU5iS4TU4iUxI+OG6LnkORL8bupZ5CovPXNWBC7QUItFlkwwIYRPWLMjdo0+w\nnQrHRdoc+JFm5BYvWX6OGNyCgq5ZoWeZJCqQ5fBYfD8e4UHfEEd9j/q/3Fte6AUrZR0MjMRoaOhY\nhJS8ZJbshRZrHtBf/GA6RpTHjxRP3B2XiD+maHlJAysSS42Q5IWgVSx5hTYNumgEdkfUfBi48aFk\nB3QjwnDr/7l27HC0PksE/8KYZd5a1jvv+vcibDggEZEEj258+9mNBKur3QNz72e37LUVy03eoGHY\nig60p72GKv0fizXYsNzNNXSmyIeP+oUm9Pz3dnYBQjt6+K3Heh3kDGd309nrvf1y+iUJYpvcw9sp\nu1uJXysWVi+nstkMCSGAAzpo0mR6Ej7P9xBe3K2lAn5tB6+JjyfdCVeUblnv9nCgIPWKRBUzW4gT\nopBItURM1Raf7jgB60ZL0SbD2ty7W3ULS4U3nzliYC2vNGBd5Oh8jeDa3ihJKbPqxt3ryt+nIlhE\nenAyk4jd+0z1CMMyTOD64Gn4RO2okdTzkRXV0sxlNrPUd4741WK2n+ARX7A0dSU0v/GyjRDfTnyI\nzdmVifjgkZsWre3vtdmqGM8HRACftWrUzW7xJnK9fXtfu6srX+BI8E91xaw+8cexbhmzZ/xdhEpe\nl3CFeINMefDmBHWBhTPh6dW8asz38Xnod4dR60xzFy9xVzfPCWgPmN30hjU3d9Uhzf63ApMWZw9N\npJzbujdtvKKhjeE5V9yW2rR2UCVmGFyFy7Fvi5LRD1QovL27o/EGZkZU3bPbyO9979fWSP2F1/yd\nanxcibgx6wrvBo5oe5+VADp5F3WOq6+JdrqLepMEgm5iiTxUu7L178e+MBAdMnspnb1MFYCheqX8\nbkTrbQzsaSyBotfac1y6pL2fg9FHc0mgAFYVCnF/l9wYgb80wjaweArC+PgIyOpEHgq4ZK/by68S\n7d3WOziVyXsNgGfZJf1e0g/UKvgtG85eAC2/2ccvpXJI2qkhCR8LjIHV3D3zLxONU+7X1uEDLtaL\nduw89S51lMXxGzWVdOMYTTLjwZ1BwRYZjHdLI4DKBRLmHtgeL7FWqqBm8I5o2Hgz3gBXbaK1L2a0\n0zpIM4oM6y0cG6Vf+q608ZNY0VUDmTrV2O03zXKYAqxTsIZc3n/yFoq8baOFqQg36epW/G0ZumkR\nI8sQRPOhOihcp7OcqvLpiEwzHiz0pW/B0GM6EUffNu1RXq7ZX8Bjfy+pHXp5cDNigN5U9rITmO4C\ntF/CaDgvu4SRYW0SqCaciu6qQs/a04iI740Gw1Yfvn0gEXES0Qh546LkMcto9XfvzbPThaWhkT/U\nrytisWC2krzCpTB1uyozgAERGPsGGQOiFbszAaSDz7FVKgvFR6wdcGlYtwuHq/CB7r77MFEWGCId\nUDqdk/hC4n/zIgcw9c6Iy4Wsq7KGG1tdk4fGipt++F/BJREw0Nw/nWVRt5lNdktpVRRiWYicsHMM\nUV2M0kzv5ARaYus0YgNi5GC2XLcvsxYe5LJda2EIYD5KhzZA/hOCm7VTPFPAmpkHOIuHPjsSQCUW\nYv8/mrvmxJK255xpQJeMo6MTzSOFT77lDR50STkGEyH/YAXz51Xv+QeZiEK1cY71HrUu2aCMP5yi\nGAlzctdq/Wdc0aEkT6vHMEKDN+9Z3IEl0MX5ejfMavk1rYb3ni2QEL1CTjKzp9aRRA2eQKBGH1HV\n4RqgIXUDk2032T1wgA2bTGpWsrPQabS9mHWPXO2CVbkwVrLFsjvVfh54BZGrTI0FmS5/28TFLAk5\nHPdTWyhwl5RFutGpBvQA/JPweT439GgPDkRykgKeOcvwIlaLNfzHne3qGZ3mC7qu+I44f1hE0/Ue\nMjBqSDhFJqg8GrucVKdMa9W6uKM1/Ct3h+K6PqKO8TzmcHLddDnf9NZ63yq1/agovroFEe2ib7Ma\nUM44T7R6ghspCItxp7fh2sd2Act+RpHGX5QRbo3KmLh0kGsRuDo7UDTIaISEK8WRV4n3kQUKjci2\njVKkqM584j9i8Y2FZamjkYs+SrITUI1b2cZ6DAfV+1IOC2HFq4JLADJMjdfWXtLWks0g7AvcWXmo\nESpADZCVsyce/Y8qwZYv7H6wIGtDmz0EQWjj2XvyHot1jaDCylsejfmRj69VYtbp5xa/Qt96aBj2\nEX7sw0aAzOF2KodJ2IuEzC33BZpfRoPwQFGDzG75LaEiRGsv4enIgKkdUrg/oUa1SVjMvqcAJeFp\n0X7rJ+DACK0KEw+JY7eXunf1LrkirGXdBsc2EqHQmhki3iN+xEs49ZtNzeGe1xl5ZFSrslUQGxHk\nRULBTVrm/sIv6x8nAnQGbhQGoxOIMU8STeNmp+LZ6iEwsKFTjgBEVniHIhBEEXT/cEQ86z452aDr\n8Inr3o31iy6ZVegJicqp3CU6FUD88dODWfq5e6JnysG/WEO8M2iaQq7fSWTU7pPc8xupQ0HiYP/D\n/TudOUFLrVm09PhamiRHRXl6TNae9QdqeeHKwbHFEr59lDkX/glwKlFur3YDd9IWYHa4aD7f7R7E\nlMmiaaphd/8Y9yjj3sH7X7E/jVW6edVeXzFQtFLDiRmwNsbaQrnSJVz37z5wDULdlAGH2TmKwDJR\ncxc8Gd7qB4et+/Grf3+EjMsRrT4XEHIT+NzgGP1wlamgXrJ65k3jdsFzbKU3akSjrZMQKPeL0Xqr\nXVxSjruXTVLq/avxcxdrtMB8QrEobpSUQhdgu+hjujAm98DxP/iyKlHApayVytCv/2zDERDIaCbb\nlAlPsg9dFGjD5vHKn9yKCeFhrNsaxcd7bp8cO4stOrSkkjUwAJPlv1UIYlQI03BTZ7uMiXBDKDgd\nBNSl3xLCMLku9J79cIsAl+3hV7c3gPizLL1Jak2LouIdBFRgPNKp5bnWtcsYaoHxkVuyGlWk6Zwa\nCAhj4VzQEME//q+9C6nypxaL6QapgtawfsWs0h/sFWD4kER1vr2d1RYg0tEKI/cMGbuWxmh2p3Xv\n1AYLdsAdQwd6c8D2aKR+OyzZuAtBbAYIrCGs1Ap7ebvcnkj2W7GfvyAg/3gXJEKDys7VLSpRJR4k\ncWrm+jhwCaRzStos7pij9EizV3IXR+48NkPrKvoIjgtwz0eCiotRILbB/jTTKyRoLMeS61hV4yEl\n/8SnBHsWXJboApPX+G9VOXH2tU1pcw0G6RX/F8x+KKPI+faODESgtiD8OurHJcSdRNRNvr0BfSI2\nGakykmpAaEfF84lzoeL9krXpn79dxx0Ar+lJSHue6ApexNAHkYZuRRyn/PG5KoLba9Nr7qaBx7AT\nAklV3BVMUFgDPNKYFaRdIYMO7QPRoweOaltIHg+wTz/TJltk8HgC6jnwmDSigz3oJjdxuI0R0HDk\nzIRyItvPEG2B8oYNuBRqpRn0O78sQbkyyaC3sRepgapSjUK8jvEgKrrXCp3W6C79dZY4FHb3qIEF\neFoAAJtjEARNsse1Hz+nLyzdDpmKQTTEx2EcAXDlJuyYr19+qnoIpXJEJch8isLdmIKAQHU+g858\nnBnH4nIpHsk34lgKO95+mZ5h89HPyOgV5d8GtGt12+iqDvAlAGXeVJucoujAHtoB1hpg3kgsPAVo\nZKTz47xzAtCGeo8IKl34ksMoNRehmZLFg8D+veou8DZtyXcOhcEEFOsqHgSlnwE4v27bj1PEHC9o\n7vmEHhLhQiJRTUee5IYJpPlnhHkRlBeUcaHqvP9w6E6DuHwW161kjyL+n08PmfWd/UPG4TOTS9hE\nmPIP6ASSlsHsHzQFT6654X4oe4HaXgg3McjvLFm8n/mFXbk81s2nHCI8eQXzFZZZs1qSwd9sOdWH\npmYZ9CO3nzyMr/tXN2e6LU1hdW+JJ1OISLJkDP8NlOdMnL+wzjN9+r5tCqHh+2VMXce06HU2Jeta\nWQX/S7Hfv7uPdojJ0ibNXpZniAI9ZD5BLm0FDDUfcclKDqfcxHUbcPqVHGfyuPe9dkLq6sVhAqW1\noudzjRgg+8aXigVTMVSVKY6SdMEdketoXu5Bs898uyk9QyIj/5uU8FsD7e+uWqCG4YOqxeB3y7eS\nHBXBqSo9eQYkp06WcobIo+9k5LwRAwMIGpQEqK2bQUyhOhL9v76fNAzqnZC/nI2l7ESAxZmLN2VZ\nBYKKq8A/FZYZKjjIytb7R9i+WfE++5ugn+KHAQxMUv8Ou7WHf+xaz1pWLLVObeAYhOBQKVwBqvFn\nnka3MO1y7Yenwc+FaTB+hThABzbPVaMiO+1gcIBsiKOdmeuuEZEpdr3sS2xyFGFQjcDaAJgc9Eh1\ns5hvSK2bSYmupIWaGZxW6lwm+1L1R2JtXnd4oefsZ6RND3Gwengz25sOx9dky+egqMkq97LmAaok\nq9eUFPCY4AxmgtTaNKbEza+Yb72dVIua4u4+zzL/t13PBQlF7aKkHI2zOUZ2HoGBqmRkytZZp6e4\nPKXKtQRzKV3/puqDoWJEFVIZjfwU65vMJCy2yrRdZF7EadUn15bxfeACPkbnDAg5iEF4INqRHZvP\nUnq4ok4T/gWvimrjBom4r838JJMrPKs3fDEeCIefLznygZ0x/WxUxcME3goDMT3Wdq3GcGZUWmFJ\nPDXT79OkTBj7eRavhdn8NRf1CGrpXMaGCaj9qIm/xNf8+Oj9OTo8LcGR7v7RPVOfs2DvM9TRAkXf\nFO5LUlQdJ9ueJpG5Fin3vA6iz/B/Y0y1TeKCQlsF33REXWtazdpRshXgsIoKQtOktgnt+DqGrgqM\nC8pyOispr2Y7K6Y0EFTbuDJ4WU2DxaV4QEj842nVMgp3SHp6QpgW9INqP2IiyT1atdYb8zP85Ofl\n8vOdhwg00Vh5e32vzucdZvlCJ0MfDOaCAHqidAEk+hiY8tLoxyqtdwNS2O5/Pg/4xz7q+baelX1n\nBTC53G/6k9QW3WAHR3E8miKW7oGwOMlbbzB9dVZnvUsJf+eN6Yp0x4uFl5nbjKuF/+L48sLO7RYz\nSLk/ddvG1OOKLMimHo8vj34dKP7MCTqR9SHPhGBPyCg3JfiguGaWZlkXK34AALkIAbMBfoGYv5Nv\nTpGsUXHYg9x8wkcfnV7Yz/Xi/PD3wOm16aITx5X45IZqyxidZGjhZD75tWvL1dxViT1rI6rr2JNd\n9shUwBtMKJdeiGkklnt8d75n3VbMbgsrp4zyOYdoWNrdkqD6/vRqaMY0XdJ65kkspYy+x/G+hk68\n78KI0bc7kLY7VYTJyBcr9508nKu7/NWTSkLyGmqqKdU7eTPOUawuSj+uN2+dbLe2Z6CodYuzKEio\nHncS7lv1YBRdq4Bgk2QQ/OOmVpXEomvhqZbELh+rSjGztZ2fBqvX0CXmsnC2ASABwVPp6sCWvuEo\nuMf/YmnHf5RKJJ2rbuu22eGUEfN37HaQBiw455Fpomz8S0HzPH8JRXkI+v+xDORO/6X+w5oEbSZb\nz2xdvXO83VLSeaTfkunDXaZQYQ13VXjiBT1p88VOk8BSpTZTehcNNVyC2zJDxshg0HOIsaVypmX9\nYqB5TXQejNdu0eFYLrFGfRQ3KN3mcGWNce/HzCRfIu2sb3iB3s9vXq0niU1rIlhz+NLc939JoA2R\ntuOCNwxyZr5cgjKmo9aK05GWL8sk/PEa08IYC2NuToxYuir00FQG7Nj/xYbXQAcaNToPXmy5ZYyk\nMM5DZPZBtk0Z1oeLB3B24GUDF0vmvkNkoQhMx3PNCXPtfFEDsvksfoH0vyyx0eUqvQK+kXxuozg0\nnjjUe0uct+sZFKs8KoSebSh9bgiaKgIsaM9DHS0SzHtn9okiQYmaKNV6LXRMBP5fX7kCRWA4vWOu\nOGLQDJkMomyXHEGVswTpiU7xRhuV9jVshD050m42WNXEwNZ7SYNdLEQUkmU0fTus5/qExykpjruc\nyWtpIyZjrW02xBsN0Djqd03RX6jYOG7AJZThhsFWujBiUQscgyJMzke7xxYGtE57Ijt5M1yoYz5J\n/zMQUrt8fA6+9BGsTjhx6qbuoRXIDy9F8Icjef6KjdbZpu0ANjkk1L+pL/+OK4Q38AOJ7YhljCuB\n3whFnpePJaIjXTVKB4tSBxL4lERfaDvrVptQOr9KMxIvZkrYJ/qgpzmev6zi7s8Ksd3QQ0AjT59R\nvmT43TR0XlcMQsfj8y1m16ppXdGtd09B2B0T22HwVDWCY6L42LcCr4piCToAVy5UWjhT+EitiBEf\nS/UTy7VtQsFhOMYTi8qNoeYZLMawVkEVt0I958C8y73G8jO1vg0FBd0FlYZaBRVsKHO7zSwDKKMn\nuwOsFA3LQq3QMq1BWQ6pQis71qAnYTjBFFh2gKUOCXhNLGVAbH0WdxwNsPnp5mirb+1cUyzurdsr\nGdeR+bG3JT7zQs/lYVYxwbyN3phVd9vMOSgLvIcjfsXHM3YAOqSJtP+MgROQV3e7zSGSQyiGNIRI\nX46RsxWQbgYtnfGNCcFj9KPU87AcQgM2G6igS3QU+xfpkz0cnU5LQEfGkA3lHPnYaux0UUsOA8MK\n8UPsI6dD6qxCfBzn8HrCkAIbu602Xqp5PMhi1H8N+najXS1s6MCn27kXDRMgklLnZHGbGZuoGeF8\nd3rY/Eulu6uhIv3GiZeVV1CzmRO1NWBKwVlNdZARov+4jA87ow45BiJpLmrUaCb3l0+ruHbkmuku\nd8Tce/CpJA4xck9yXCPzEV0J+C2gnYQ7Lc4Yiow+3qdWQ/b8RgW1DSBqmIB6gQ3avDldOqpHHl+J\nJqUOXL4MioXPKth8yyP10Ypy/jNNzV8OYuA7LCCO0jSxZXeSIAv+7MyWqunICIqnDTlc65LggElf\n3pUFgb1URxWLprSXASiy7dh3BH7iAFPHmotBP08TRbYUpybGad1+QbmgY2ZSJ8l1cHcAaZo43twg\nNBZKRxNPrqbXsxEhZ0rio6oGFDGq1U2qREIVp7CXRbNL4SRYeoJYY2+UmSD/mnf2pZkiTxPvpdGl\nmqBqzTmTJC+1pCOL6FQ95v+Xt0LMYi4vq6OLaAriP+QIbWW7nQdr8xLeRyKVAre8ZJx9CRkoxOO1\nHIEGEFS6/GctskWHTlxbTeYTLs1mi1s1Vh4SX/LDZXUXPejdP+cWoOWah/ko5FG7r/8AUnMEoFI1\nppzJCXRO5r3P68l08XFu5iX2jCpEzcTGYlR+2vKkbxz3ctNuU9+O0WnYqi5HWbZRekttCOmIUFgb\ny0JKIVDfe2QPqpXkeUAUMvmV4ZacYm0rp+/QA/BOK3qucFmLGwsLqI9wv8WCkYTLK/RpkbokpwPj\ncPrbE5XjwiSMxqFPCL9Ow9dKf3cf0V5/gfEh49byd1pT1g3jGPIDb+p+onvc/lKCETtKxACPLGLK\npHqeCaeIcl+JQVatAUVsN11hRsBKPWXsjBTBu4GMasCDLkQb65ngvjpIfpTgYkpNGkA9fIEOyApp\n8Lt6HihdVFewX+oAoEPClkHcKjkK1enfTD2nP1HCKSkLzKImNANv6htrwItM/yq37aAXuaarBk5S\n0CEU6TfKpcq9lM09AQYQ8h7XurKphNE9Z0au/DNlH6xY52xlFSr8MeGlxgAcgcPipHR6MMp7xqJf\nW3R0Ei3TSvHwEpzfkgaYnCLPttMB3jI3QGibLdjIWcy20JbtvpsNbRUOgPoMTfii9C0ODGFFuT8s\nII3shqeoUbxemr4Xtd1FewCK7OSwRqQOk44JcxgK38+zcWVdUc2zddd0wPdq7oh45qqWTWr1tYFC\nM+h9IsSUJBDQTIHLdUo3ymltrgj5YIrIGNj0gB4iG7j10RMUrnFV2Dk2ZHxWwuwqkPkXM9+xZRiZ\nKoJ0haGjgTrGOgsp+HfQSxtIIZZ62XDrFg+H79IrKG2eueZHKveg7o8i2rjzRI0Hearx2CEnSoxy\nBZWeac2LwZjjstkKdxAYhYUFewpMSmNNCwS5Q8InjwqLNsPtTAE1ILZbUcGUqiT4r5axc2Hdyh6o\nLndfb+s6t88OP3NEo8koLC8JjYUiTW9vdm6Z7D/libuM45mo2DOiGJO4H6U+9gx9CTmswoViz/or\nmHm9SYIgtTlcuJ2Flc33+ohWKFIH5RJPtz/+wxE1bow801rs1daQWblAb760wF+9vy8B2VeTBV5M\nsp2AOVRQUsPeFPBz7f7WXlphgiWgPL5Qi8HY8FTGNjo7w/ZSE9g/qCQHQTW7w+LI2SfpQSNnxnk9\n0J/C1NadV4o54B+PDjuQtt8jCwA1VK6rcnICLAM4R3wG2DLZJKxY8tPGfkqqMPivxs7wl6geEGKL\nQIVJ7qoM/fMjjPSVG6vWcUC/b3lZiUR5FT1nJRWqmtM+quDK9IeuwR88u4r41mEccIQcny/lzILB\nZHwmygOIsgkaFoC1Zl1XCmPOU6n345amPjKToMeuB+URuyChqeue1mrPcX57K6zDZMnYj0q91Mcr\nX8Zudy2aUWJBsB8igJ7vf35BWxzVJuWCuSPdYjLq/C8reQ2TDjmi/OTHqQvXFpe4PzvpLRV/eIDe\neQa18tjddsxQIm2U2hd22fFrtXHG+9V0I8qYDspSjOqLDNhxTBuTNeJ+nyQi/8TJxswdtYPQTAM2\nMgt8eBklygAsDKT/v1upLcwKXhE4CxBzdv5KvSP1IrxzVHwjfMTBtitUM5FvOiqKqyAXX65nh9jA\nxcfIeTSsrVK/rEWCIJ4FUb9i+a7iHVdLfDRQKwqWmWCp9wAOW5UnflUvCKZWnVzZxO73Qqi3wA5t\nSkYsdl+o3FVPbBYBB+oJj8Mb8dERcM7AGujFXlYLhg8vghYlvOTBsxxN4gkCM+8xV56HXoIshsdw\nhAYZ7+2WJQbyOSor6cn48q/hX+7rZqtBsKGEB2S6jHexkjXhsu6y+Ry7bqgaeSq1AMVdb9q4sDJ1\nx8F70PCCf+mMFRROvYrj/+S3TM2+LoPHR2fgZjS0+b/4tJcSork48oqA3oHJ9pIgkv1TPWmlhR/b\nkLJ59V0FsWstMRQiYJjhl74lnwvLNurAfkkZRPVZfSboM0+Z9D8HZxAU8nYbEP5imEAM9aN6eEFr\n9ko03uXbaoYCBcGgdPHOduOZjD/fTfwckfr6Q+lrjOtBPyX3dc/j13V5zOkw7pj/cr9IW6znD6lQ\ngk8Xx5wbneHieSt1bz0o5OnGUmnvwcU+MgTf6H8u0G+iDNFQ3ppFGsXl9NpdAZT0HolaRNOWDQmM\nYq2EgmolNpsCgIQMZxeh10Saw2Ph2WCO0/QQ5u72P4O9MoeCycmDT6ZKjzo0e1pSnz28bNj0nKak\nij5gQ16QFEpMS7/QtXFZ7rmw07QSfbn5z/Hvwya9Ex6dl0RRI1sdrSBNK17Zeg8aUbMdJzRd1i69\nPZxhyzn+xP4rIQ8hTWsJTITDre+oB8x6NKjnTjW3QX76Je4ApOd5QsbuPZCqIw5MGict3Ags3R2L\nK1/eVWC8WaSClJGs8X0mnCormD+V89gVhiNcHlwZ+FIkdajy1H4ZZrTFfskdM8uNNR4YXXoGh5fY\nDhoGrrXAn0TbwsPnD2eo1agdkMwwjj02J47qrVESjcjOs9/xfFMUHNLdDN7658FfKoxSrBZoU+y5\nq6TkBVf1Uq6wcjKHZpgf1EkWcRwCAmEtMwrV3wBZaNjZN7R3mrQhDABlJQqeMwFO6xfjFZIq+Nnv\nWwaeT/DaVGRHLoGPiekiIG4YySh6dR2wMNRMCTh3JU0huNCwbtrJoliEdR4cjMhhKL9YZ/CXZe1e\nCRPvZ/F+D3uMv898yHVs4hCZfa72qr5cKEc8QbVQYN6zWpmoGRVLcPh3hEALJUcmpPQRSWMzNNlp\nN9Xfxi2UaLFzxyE4+xXU2iaF66JCGaxQRkdVLfZNsP70NxtpZ0eILfwu3o418A6Tc6MD//eQ/lvx\ngPYKHZjiVifxeJ5SCG/xkjcNHHUVoUf8qR0vbUkOYegnjHTv3biiNN2smrQXSCxgVUccdWNw9CDh\n6MnXLCI66eMybHmL4zkYCYwxGGNDwh63Fo79GdCDt16509Xiacw1DPqIJyUJ9Q2gLhi3UHizWJhe\niVKGWMKvJzi1nQ0mcVDFKdVDbA+D/thPzKxn0E7k9xuZdyw1HJfIiAGz0wZ9TTRymB7rcbxSJhLU\nD/Gu1wZep6ybLIYGJsaIxNp+6WC50wyByR8KHEtmCPOUaRDN9harmOI4VI1lOcX+41ALq33G6cCl\n+w58yBhMFqN/WRlBn7V2R4Ff9837A9xWES9/3m9vIkWFVutDASNfzwNm3rncTJu5IHR5W8fFcKqB\nwjnaaDdb60XI9jt8Oxti+vPM04oFDlbHWRb26XZXYQO97Hv3Kdij2oN5PNhxVuh00WRdPQWliDF2\nAtrPtpg48cVX4P08Ozj0zZVCul1eZAOW7JBDgnaWzHkJE95dBJbutQDwKXETL7sATMMu5GAqt5Cm\nB7hB3Dy1VpmtwP0TVHDgsReZDYg1Kc+uIIWj26Dd3Tgt7/sdSLF/97zXh4Uxnr/4weIwnzH4cgHg\nMVwtIPkMGeDZHwWo9v7GRlrGM2g0c931vxpneLJKOsLbOT8xwIesbY0c4QPL8iSZoWcJYgTIpOhc\nhkC2yv90nHn4T2zfds8ZWUUMW05C5NzoT/LmBr7HJRj2LAIVHAeu338/OR1e2nzd50XYgantGYtP\nFBNxE0KKGBLcF/tqccDnZggXssBYKOX7/LbgA/nSfOJKo+HtZjMJM2yQFAUbfxNGyovOgiVpP3mc\n8Kn0s4HMiK3ibxd1mQEk7rJ4u2JgidMB5L/b842ai4yaomOw1Aiq84t3D48gWjAoQQAe62Ny/V2E\nkMztpj6yblnl5i566Bs7EMA12bD1BllnujIxMEjJOmiQ2wwQ1MyD2anVyW2UiwJnIV4y5wWMd6Ld\na5eEsqeuZmjDpCTEElVOgy1KmT/TxEcbqXQegHDN8nvTcqMuqPyuUUDbXYr9U43i05rPEzOgthZE\n6tOOyzBUADrVqCCogm/lsEFWiDh/wI7xLBstiyoB5R2Ms//G9BOrLiXuROPzQirS27sqgKvojI63\n3XWogLz5Z5oy4/FT/lgW+rLRlvzBqxh4z/fCxFArGf0n1UiLpShKzMT6lbIo+0LrU8htUe9IgZmM\newXcBpCUYovI83h9okr3XIA+8Y//g3t9+Cw3TF/KvQkxseiO712T/JDixAU2Oo7vRlI6Tzair2VH\nc9zNDXBN9b8opoYec0P2qPCuFmYTEzYy32sNVZCxvZDn91Y31qc6hKu5ONKPhQQ6GI6upSVsVJxV\nMPWI2QfZ8Pk4jYBPU/j8l41o4iTCJwlQm5A3oC8hccJ4KhtQKfcX+owQotwaBW3R0jNoFjvTMAym\nANTw7v7dH4yTcCp4i00R85jn6lV4Ti+j+XbDb3uwxbyTriQoGoF7XUofafc+IsdSLppY8rG/skOw\nZgUy3O3LTe1HpikSVWxzELJwTOS/4RChawbGlIPeSmI4tP3tew3438/zN2G2DbCxDLhmmK8HT63q\n9ZG+cLvwniC7V6C/lGi2gNTThqy1n4Cgpl5JrnDZYWClDUMRr2f6Mn8YfIyRraWeSZh3R8FpipbE\nEeDZWHCXlA2p6enQ5QHsAm+/ldyQRbEkJkpe/piHW51yuivH9h8JOybUSXbiU72zK7MYM7xOMv/u\nZt0t9a2fQKej43LJMuiPKE8sv7q9rBTz+dg18zNQHZe+LMCH155k9HdFava1/AwPcQIHffmYrBWm\nQ8v1bm8NA6F99tMc11QvAyNLiYcRQK8+0JGTgGDrdattk63sTKvz3MRm5vVvranS3ts3WF52hDZ5\nxabt+eUZeyxRViu9VrUksJoOriAjcRqkZBkniR2vZE3CDD0uQDVeVISpc1ovSk5RrXhmkpCDZkbL\ne/mxOImpconqtjiWHe7K5qm3jsJb5AX/FpntlcJqYw5zNcFskGRvuSH7jRrUzgLBvqdNGhon7qvZ\nslZaXZ8Dw4V/4wmimA6CW5EmQ1aQ8zESQalx6kHgVMBf52CM9U9iUPkNFZX9YFeiQlaUSA591754\nQxFff/S3NwKyjXlrdkVgSOTvtbNMSayzS9B+rVEEdhqxWZYnF/yc2oIhn7j/8J885MB7wN7cz9Jg\nJS4Dd6S2+MFhdMtpK5tsw+kllcZBBMNMtbvMJ0EnxunEIIsVRFscXBpIE7ToB/tO6jM5YyP2ww+M\n6B+9n9p0bgxrU2i8Ecq0g8R2gbfcC7s3AztoBgnsXczh8ApNnzQ6bcBFac1V8c1dtJbfKg5C4Xlw\nR6/2WDW4Oi6T4roAX6RyHcRH6SPJOBMVlLlmI1zH2ipVGdmpFxISJkDuYpcAo8F2hghsSj2RSPKB\nRQyLd4McHKC7M/4aWd9uajQJsQxgi4WWxG5jbeWgCVpFS3bx82D6sBE4tVowr30I1b1tEB3LTL3V\nBEWQnkSjdxcg6DqAk24Ou43/O+hFaBwAS+aZWiGRSEd9f6aIL/sUBQw8C/uHh4nLJustLA3QFomF\nKymcm9395XN5pXfpqd2/WyJzfw4nAu7XosgAOobNor/U0em3upnIQMQ9O+Zz8m6dOowAFX2FJekV\nTCE1EvHekK/iUwWL0qnRfxqe4pOSnsXpPlW3H2dfxXR9bqt3COTrhLzMP8g1SZ3tvoQudcjLc5s9\nXgi+Ce6hgyPx/1oIBxb9tKpbVn3t9YCqmZSFW5O3lY6hY0CYIv0mGy74FRLrnQ8K74eDyrl8+VYh\nIvHCin32EavmwiH5AYLJC6pkzxqSpoPEpYdDWz567nZk/bKSpoINPM9LFgb1E/+kEhWfTURx6KB9\nhNMwi2IebS4HHYfAud+uS8Yw9eTmKPLwDeCdigf5WaG3Cn7GZfzrBwMiGbDKqjfSxLY1Te2ZNDRr\nvfi3FEK8+E2nyndAmcBlPkAUYnO2sSRHdd87L47KEnrRj50FZPwZVJhJ3MwV37SAZD3lDRb57TmK\nn6z+PjUZ1APUQ9L85F2r7CHP7CXY6CBAFZb+LKnyyXFnMPaRr+rOIDJ4m0ChELjs1MFBWSaCgSuu\nqjCYX4RRw3ZD3JqFxd0Jb7th4e9a2YQNR1yNH1srUeGVbstwBOVsH17zsSa4SyLl0SaDeU7eqq05\nHS4oPJ1ssbJMIwZFLbgTYPIdh/0SdZgrzy/fmlMb3wmEntQXW8xhPurDQ2QLvRcSZUMhlmyEqNtq\nd3FGESCqnQpju++lPTX4MPZL4KNbs1Rs21xJ0ag9uTkcba/CYeaPFxN0GSDuvopi/RWpNYMHOIwD\nHU9O3qObT7uhlylRFYlNNLyOiVfrALryQ71ViYa47a2/IzHVgrIjAAUln/PlEK7CnWh/NoYro564\nzIaGNwP/fmJMZ/rMmWEJfJRg1T9NJ7U20Hfv4gqKF3OWV8DznFHRhta0afNlK8oFdknleNdARk81\nGHKcdBCDMHEhR64h2DnQf3hHJyERZaoaVg+3IVfWXAHaNkL59D0Ix0DriK3+nYXzfn7Fux00xNv3\nvX6quYrfSiGWKKphW1PyxFqPTBr/6nIaTQp/nSYF2XsWHWvqxuImTjjt4/e+vV0VyE0zLQhcrJeU\nYXHSUHGGgQcKle4m+Csh2JXuPRxnIkY+BosVq/7ux3iSaqB2heqdPpBMykTm1G1eYOstinmSLXCc\ngF4jBC7sgW4HEYJD4r9dOVIsqvRQ2+HA+4AS7VJvYIDJZR4bU6QyrT1JVFzSJ1VaQKHM+dqQetdE\nEISDBuitHJxlQOab4YAswGpqvK5qyJoDRRaWfFWeiTB34VyLPlkF1c56F3281UAwrlVY5ExEkN3p\nPpGb+WNGqvRS1MBy6zgf9aZSfxCXRrfuUKdQTcSgLI/XK/QTpwC6A7ccpYr8p9ltNSjeHz9v3jJ5\n50NsFUj0WLUz3L9Ub1pQK10RAeeqRC4RofSb1sJ54QRq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QbsHEZCgWUSSDlkXwx7qYeks\nI0Cl9iGof9LGJIoeACj95RvP8yrlUdnynR+AK8HKYSRy/W/ifdy/eUJNX1P316d/0vqIko4kyZpH\n0nKKJkNgESLqTg6ZqgDy0zXWjD/1A0VyhVIqThiKuVYyoGHQ0dbxJmL6xi+J83cLZA1hcrbnOvLi\nj1kHiwOr9xLZEFVsR3Kd6URev7AQxKLxK/5VeLpe5UDt+QezZPSGTDVct9GPX1/MZygwXfdQ4Ht1\nd1gjtcOhGKijlUIjH2ZeFscFsALVOsobFzs2qOeoCmNX/rdE0ofThxhRI+15kvrnlGmsM2CSXBiv\ntgL0ogGcpBNJS9pHbsgce9lNCgtXEub3Kglnsx2tIreplcGo4t5SlknsAxqno3cgvINOnv8oQCVN\nYWeIzoQl+ohhlk/cGCtzqaOh0qbi0uxSrw4ngcaxE3YgE5eit38kL5qghvhnbzmRaCMy/9CA7YnB\nrBL1a7olb1cjtYRaMEbHbZtJDIoVP57Er0g87av2C+qhrP2ZzhuXCEUcJTx9KGi9C39j6yDRZ3jm\nhV5ahINy4y9HKdUM9015UtzQ/6Zi+kSGuBA4eHiLhwwAB04/bSB0+0aJ/5D81+r/ubHpb8pNqutz\nKKnOHNdxcPcL4JAzJVYmG0w6bzEuyfWtKQmWZov3l//dCcaPnc28LOjmQDvzt3c/BHDZb/AHVmmU\n/Iwm4iwNX1WwnTgExp6BXESWq0RNJaG4uBFtdyX89bXe+FbiPFS28pWMV/u9ixikieuOtibDhSP5\nXO1nf+7ZSs54RBaoJuOaMCX79BHoHeoZcD0Qh59BfizlBY7VyB9OD8kbrRb8iMhbXyppkXig3t3A\n6mPBbnO/njXwEhvSgYue+6RrfTGUy4Otut6EY0ZGcEW01fde3HTu07tbKzWL1hkSc5snIwZEJNeR\nr5lBES4ooDWYf0WHA1w4qrQ1fmqaC5+HpgThrodI+nM6wCqObwDjhCbt/O6YIioZd3La5rpgLL4V\nMszl2gPNPB3sfo0rxpBPIGqfYUsiZz4cRzMnNCpPyEJ4Jj4cW44QoGrftZVrASXOhp52pdlVw7jm\nX/JLTAS3Xnf1fEhP0QXmU0zN97yg8gSgj5kYv6NHWeTbllAM3htyqn2hASIzmZK0NrgWEuZ92LCA\njknbxfUakul8PmgHpXu4O5DprPRCkzTssWGwt3aI6Qh3UVdJJNtcdM6SNBtFTtyJZeyO9VNGBkn5\nE6IPAiad5/atAevao8B1rILJkRJe4Ll0y468nISvLjK3BKSU/5wfyUf+hWHeo2Nho/7vmYMlTvKo\nzPas2bWSgNnlF29JdXIyji8iIw4IXYWDj0fTXQOyNOBERqihh1xtlAy0/hmrCnRZmbWJZjG9axhv\nHtPNvo0xuqkrlBUtN0FitGC+qhyou9Loc8/1qXSwjKTLOrGrD7q8qPopH97rn6PeRpFQ0B5VKmvJ\nKM8yyaKvH7y6zhaM+tl00iLZxar3y6ESP//x+dxx7DIdZ1dDX1/hOXxVqLtBhNTR9+MExnhr9XMs\nFm4suhZl80zKhrF501KFcwcR0I84lUiWQMt1xwQHulxR5xzP8X4emh0B5TNpOQcmb6aF8FevzutU\nVIu9QK4WAlutF5bJh3KGCr7Nkmn45p6b3G0JpfxK5AxmEbPo/DQbbu9q0jAefyL3ZOZ9YRVhObNm\nLM0ih7YA9ehJBqpAocPcEpOgk/5bQx3jSiPmdH9dIyIQZJrPXWG9zZVFp27HN0bS5NGdYo1lK1cF\nT549PGaIhinFYILwqDGB7c1wtt5DPC7NBQX2F8E5DHSGi78FObGqLNd6yop5C/HE9FlRmvSljFOw\nP00+cQz+m94bOAkIWsuxpVoA9J8+whXRqTESBiW/jK1xp71/CXvWlW2kKcxHjpRhEHPVwAnVESeb\njos4bsPTBQVe22wzMkWmjWFITKNwucJr8HT09P/ovgQSKIWKQYknDavLZ6wDp893fHGBrlEXnoWB\n7FYLzCyK2D7zezIsyxYXSLrMQdv3JJiRATqwscIumCi5IkOJFCNk5HHErUGwcCbATP0k1wdw5zSd\nejxTeZcArjnWlKpo5vCf9Jl/6EVy90pqU8QrfFeIjSMA8fjd+zPxNc7WVZuvIkFNgiMFAsgkLwOT\nwxSIZY028ATyc+S95Ls55OxGPUdhKrqHDDscXCCBTXENhWp+EHrMNl7SmBgiFOhElOLVXdRks7+7\ng7TPrE+shrHm0AF1OggRFIJtc4r19r7PahmJEMyxeA+FIR5r0dqtyVeMUJNA9Nq25IO6Y10YhNz/\n5v822VvDG2wQF6SWyGESagJ0NQVKTXcv9A3/f7meSix+z+gQO3VaDYJBjcvxTKzGExqbIEUhzOPI\nspUfQfWDjwZFgRUXwkLK74l3gchITJokOjBcKNYMVmzX0EN2V4cDy9ROQHUbvp2Lj6fVMldQEimh\nVBbHlqBRwkqDjb3EtZpRjmFiu8YMxre24BW/2L5/O+owmcVsdxTEWMhaw+BTy4ksGc/QAJmmCxhe\nQGSaHOMJF9XWe7lGTrLHPg/ioSvjB8vIbhKMuYhBuUmPAgv9u8P29rxwkwhVrXx46Bx1B7dT+MQU\nh2TsS76F7gR/MDdL9ybuFBKjSZDre2hbw7ALxCssUKfKa6QRtREfXZMEd1qN7wetM/d4RVh07JZt\n53Ywkitc0bXRPgMx+daG6DtNHbSXUUOQ/mxcgLW3KVLTDwyMY3Rm6h1Xtysy7uMEYTGUpoAx2uLt\nZupLU2MEvnsK6WL1ogk7VtIjM3UwNFkFD551eUytlMXd8eKoNny36sdd8PZRwrJhxwtLcoYlyR7S\n1AD5ELOidF0XOvN+uwqkMt+SRm0l7vny4K5hDASUnoxF3Gc2s4N2crcGgXlaDytwXjMGCvzq5uqO\nKHJ5CfZ5xNrRAPi36UypKbS/4ERYG8XRddYfBZSvK/mSHHyey8+i4vxbThoPQNeEsFalXXazHNpr\nlP06j7qKrdjDojXac649Rw8wch4eXsFC06WwqsqtfPyndS+cj5obbzkUkVmMDqfpk2J1n8LyYOY7\npcRGtiYRMKgaqiYTd+/fluCShUnT3eDlsH2ioX2P//7t6/adaqABmnPzT6Xh7WyDOvasGjkINJz4\ntsCIvpeXcO+btcg0w87aUWNtPHKApq9UM0pnf4lYv+/oZKmYjAG5564ftEbmwjcPJYoaLVySZOVf\nYys0qlGLoIjzrk5Pum08TsR27x5UjFTG3ASpryAEZpP6UOwFWI791pS/rUae8+ag4q7YSS5saqK9\nMpM1KGYmJCqDf9vgvQoyZHlseUMcgRGgXW2bTCIyyuDt/8W/2TVSy2xlpG9litx/KcMk9gjX/M7p\nK9rJX7NiJ1Uf3GA/a14vv1Acw7YrNe7TsQY5l8ZuIy2RLgc5lvpwuhChJjx1XYReoT+6os09jCAT\n/MdSRiCdxm+tDJVBI7zISuUD0Q5++iZmaHI+LfIiNUmEkmLDAtuCCH1oyKAY8nD61H0MUzRGGuJw\nMoPZx81QxkOGn3RvQxSjTucDtNSzMzBMd/9dYROSMWhsrU+zDoAJSUs4m/ba/VOxFpaImMm827vg\nzYeCv8sM+1/PHYhtKfhorxuU2hVwlVN4kem06pgmXWWd/5Y10eeylefYmgi8zom4odCIcpgZZsVS\nHCWFkSkMWaViAr0WLVuAWbGZPUDemtDBZkdNM8S1omiYRrecseaPZWma3VYA3QmCQmuGmRI6c9h/\nQXLJss0Wimi3YkKnnyXCA76fSU8uICnJN72NIYH31ghnx67M4zUhlVwpKYwSP9Lj0sbqnQcuDiTj\n3rMZb9vp63NC2Q3ctQ4j5TYlKsCvhuFqIHxSHdlYVyqgUksdmTCO8KZnEsCAjkM3b5g0ohzTO/VP\njKYBYk4UPqAZGqabY7kSeDgWSS26+idu6VmVC88V8DNXDiGRI7peVRtwHzWGtOQtk6zefu8iTNFQ\n0fYcuyojW06LioPFQTWpUVCDTyR04OZTjUZxjifaUwirdiIaTazUlZokVawJyw9fs+y1FyKbB6L+\nIomGJ2ph8nT6puB2CEGpTopODjbW4uerQ0MajSk62oxSBqIudez7Cv5EVoK4I4sltAPs7syGHOgW\nGT/p7x4k7wwR/e3UcwgkLQD88yeW/8hMndPVqE0IPk7ZDIbUizbz+GzeqcDNzpnik7kLmtRsrT/L\nmzKHjB6hf2Hsk1r3aslDnMLM8naGbpr2NR9Vab0OgIW2uSHEhzl+ATjB7POEQUJDuGt+2xzOh16n\nXKEVFeFSpr2Lo5GS4Q+T+Ml99Ox1A9f5zyyVustcrV1YPCi/vIXgMTvzgXCOML80eiAvk5E/B4eD\ni3lmC1jWHy13hIXK8GPB8hz9NK+nuCs+bgVHSrEKpN2YUzAOkvyhxig/xLP9DUtHvtYN81pFyzEz\nz+XBi5s6Ee8+hQXPJ5cLGKNWcg62UBHkDHYp2RH2efLrdmLAD5eZ7keV0DWVg1vuRNk68KPaYCle\n9XNbBGTLmWkP/iyr7tmJOD6c7NF4cw4G/qs+sTHwcLqGIHZmIwVCK0Oqgem0sW2oLpi5PXuS2eBe\nEjoNUl7OdVblgFQr7fx06qGyutvHyKYNXAnqa7iKqMcI8NgqHNG/55Nx1G1pud23fylm8xcq7+5R\nRmL9JMJHxJu+zraLGs5A2hpuqQJIL9IEcevFscIhooXgbRwuCnx0nGnNWwAxKEwBxFVxrWv/iT6z\nAZohqsKL7Ozjcjh15umWDF90sceYnmajQY8CCL2hwbz2SKFt04R6sx0Yy6f6WDrZjC4cmLk+CCD5\nJTaBwKrqmGaJjQlKt4bYT1M6r4dm/bkKvmomEcug2NX7DI6rqKHX3CWUkJm/pTr7LcToXHZ3Qtog\nFiybbAI6i8QHBuXDNKDRL3hNyNehNYRksVOIcJhqIbApnYRwEqLIphChgLLjfiJ2cwVvKt1Wn59p\nVLnqnBY1FFbYev7e8FERtM4/Ue9+ANTSa2Yox39/z8wsYub4NDeO2OnnawtQVL/bt2eV8m6l8qyC\n3dZPJXW/4p9t8UgcA1betYH3EBrvKGrSmJSWIwaKnrzyiZIx0cSQnK4pDxk+vSCYFvl3uX/fQbWA\ngXmVYTZwtkMGn0NL4lu5QsBvFTEwq9kzyPtIz8lf8huSjbX62P+6prVEaPcxNQQL81SBBi1lgEwf\ngPJ5P9Gq6IJ6rvjiorAm/Keb4n1RaKV73mIpifx/hmPK2mYvlyGDjXH0NfCasKzuSmvSjFFuWiIg\nRAA+1f2UT9FuCQNn0QxZF19uix80Lk57VsWWthS7Xflx/BeGiec9RVxPekeyZhVXAqOQH2kqyYA/\nIQX+nY7E1wV9gdsEp+iDLFa11lIzSngyXutdg0VnXuSDKelGsiPeX5LdhH9R/VQHly7UZyXdV/aU\nlfMu/CCxaBVWHEckpVU80IcfYxI/7Y4NapnOez/FXlHPDAwK7S4fSPtkG3z6xehea89sBYb11MTd\nH0o5SRMtwbgU0VGZPEBFJYf1UOS3oxgocdzvvPxWKTpcp4o7jEBotKTdRfJvkTTiNlGXsLkhITam\nPIjDVkp4nQ/FArZnjnD90hKJMrQJqiWZJ3k1InrSRmPVVJYTuJde1hw/kpIeakqOJH9q0T3K/32h\nka20ZnjBaX4fRxqlZWnUXxGB+eNBakmSADX7eoxiqLwWyZ4ytbq8gwkW6oxzlHZrvtAlpOdP7gj2\neSBfJmhDA0NwAzI6VhPQJNokvbrSBukTaYEa/RACkrNmJywCm1d6/vBUX/ZYVF8VJdIjCuiq5a4O\nHSDd+KLVT2u2PxxYgjUmUSvM/cVLcJNSUm77cHnNuBxDQEtud57YtXh+QfR6WTM+joQXjT9D5gzz\n8obtudUwdFuu5PqKpp1DHLhgCOqTq6pz7DjBZBJfofgyTN83/Urld2qCHDv6DU/1Eh9D36t3J3fK\nzI6LN1sSnIwYyWywttx/nzxhHHAB9IN7m5dU0E9AwRmWz8iRkSvZhDZbwBcTqzt4pnJOhybhCCKa\nATfF9qS4VkXnDjGDegKI9FytKiTmHcs1gCFWRC7Wuva+uuZLRhX6fb+5+fBuYwdwMuQN+OFKK9Gt\nDCg/CVLsJ3ZxI1S8cVmx9Fp2d8jZCiWNepmht4KZ87FWTBGLHhUEe4MUNUkCY/p46F3oNhD3m6my\nL7WTZeEQpzWz2uW8GgNQR9k1SU/jAMv89wKUYZWT7nvx9ivKAQat46feV2JXfQiAy6iTGlMqsCd3\nymuufdX/gwVnTyXfGf+KYyK8Kl2X6QZ7XIX3V0mWA/EiGVLGLP/srMTuVtTgqBi7njg6QRAJ8jJp\n8aFKR4RprjB6J5kbT3g/cC8R8+2hYFzrXwXOUhfJq9chHTTE8aVp3TbAy39R4IMc6Tj8Sn9HFThd\nTMF8iDbnKFDWJqvepGDw1DEk4oBSUIOylZLc+AJAMaZyyc9IY7o7MEgPP17H0YFVMFQaYakDek8Y\nct2FdYd/WqpsSbKg/TOknG6l3CfsKWyX+u5UjaoRA6ldwtL5OvNWIiK2M7/pvS66NxgcycI61Ql1\njW1mUa2MedyJtSCoIgfKv4ufy5lqn8M+SreZuDNEu4IU02JnNoVYv4oRL00qn/51PorskWFDQNld\nY8SrWftxTIGemLYoEH0AzTDRmFm2ampfqyRj+/uuGdNVjTz5s/opmMFat9HPwuI1bVYVRwS0Sik/\nSGsawpGxTLiK7xlgQpG2FwdLQCfWZegxPH7ELMNZJxHhGBn+W1J7Ip4Ssqd4HKkO4d1HYJmU91IK\nA73KeqZkNLZuoVT8jvjKPjW06VRbn5zdH4+cFPMTnxJvS5vHgSagHS1dTT40sRqELrXPU6HlS54X\ndBtsNjXcQofnXfrHkH0HuvFvVfNcElFoD5rLaPl0EIcPTuPz8bFkPDZbWxO0eSyj0U4ogiR7zL/Y\npOcTxynIUC7em8fA3pS5Gib0zOvHdwUZM6f1XUe/RBilxHRa9Vf64tX5W+OrZwlxHOMXVyTuVvNz\neGidYb0oU5y43OBMu9cYrTr1MP1UPlfgcp7Uiwb1ruw4wSijHqNgIGcQVdpblKBOeQ4RGr5LXpT1\njfpcyzSpS2m0/RqkObfk1Dl/GLLL2N6EPrBuRc1m2a9ZG2a2c9RYr+F8E4kfpnnSWRpkEF8mfew1\nXuAZ6Q2i5GZCqR7DvTIMZWwnnm9W2mlJ78KQRF/nfjF6S71wFDpGHTo5K2PEBXW7foaJ2I6cABYo\nt03BiX6WLRt5JylcUYS+TFKFUaBACkL6IZCY9ZTUmWsOJ9hSEN+ohfNAKUmcEEU5pSqxb7QSjfcL\nl17+fjWf88mGaePh477fojLKg/URdcOjqn4lvZRCT0sFo0ulX9nzkK1gNVhy30VOLAOE8vDzFoXN\nU68oEf0t81jxjQaPZ1xXSjgKWP8Z5mHXkw4ohWxE4S6O+Qs3H0ILqkxU4ktXIHdWs0cIlP2pykvK\nKO7ms/6mvCclAH8a/CiBLE2Uz7sFcMuIeZZEAzAXX3Cz54IGbEY1V07PzOOzDWLlpXSFc6zJDibp\nTw/E0yPDC90UHiHKWPhrLtTqw3umlta/mTUgpAjjpbeH5WGuSTyx2jw+AqV4aWtXUfRWScmRN45J\n11ggUpqnFXikWrD+anQ96YQ1+D3hkL65+L7HYSx6f0yAeO4ppvp+yfYdysxmzPawFlArXBIMyDOP\npI3xqsETfu6sA6wiBvz0ITKbm8Vi4zYH1cLRg60nitVw4HPic5Yrlh0JpSzt/bcPocHL8/MS9RAE\nNclzE8e2MOgEIj7OqhTvendE/gpF1lp11m82rPuVgryfbG2VHDzRMQmQ47f9yFToDZ4gFPtSnKyI\nj8Xjr2OjzX3qYIpGh0Tlok6TIQVlWX7EAxlRxYlNiyvGFREJt53cVmpvv2sgY5rN3SgEEdfgFRCK\nDEt/AjQItFWRJHxu+WzJmt7V4y/xOxHzVTbmyXZ788Aamz24bVmH+JPnUJ+Agmtq+MuDqMma0sGG\n14K+uw0xc77v2y6PwMXKYTl9keOrwPclYrIyTJF7cfMMSU86YY0vjYrELz7mXPfWa05tmYlpr1Ti\nFLiWk31Lm4CUSADH+sU7vDZE5/tS46i1IqE5t1Ug/H6dLFYt9HFks1tGFMa/3uDYwVN2Ap7xBhfC\nnJWb4f8nc8W8GsG8ELDdSq+Gf+o4Gebs8Gd2k2Sf4aCsKLq/cpstDiTPgih5PO/U/gvxoF7cJdaL\nwZlmUF/IyrLXwp+YwoOxvYMliQ3MvzPtTmZOFlz3MwQJyp5EEL4VYP3W/Z1kbAgm7iarfLi4xwVy\n0MqsLbup0Hxv9jNFuLoDFAQkwaAhCHX9lAMK6Ni+mdda86kfR86RvNgxiIN6RBO8J5BP2SUFR6s8\nCO4KP9dsfW3jU+zNYe2vosZXghuz+KhBDzUdlRwXSD8ZFcIgifZR1wsJDonQZRVxCEYyls/arz2b\nQJwDD8Xd5p3M4XwmIxNWuFggUL7ZO7vEqRQNni1E8zHpQvA0iAKh2LGoKhoqpf7EvlJ9rQHpVwk4\nnkAjCbzVPUWdUpeW3tYmY9M6nGPEymoM4W3uNwVKqKPQUbrhp8Yuzh3C0z9/IuWpy9bGiCWruZtC\nTeRcqyJq4yTeqj5+XFr6T8J4DciGwksKUL/MRV8YqXKdsJRPvWBNtcjqe3tHaAas8ZRWZ7YjmM5t\nv0I8Z2e0d1FqdsCZnY9okOJMgUEM1J2XZcCFFwPAQw0eP56F8rEZ93G7ve1rDHSpxMdUaVo4pkQQ\nYDiM+rwmGxONDwPWdQzdld9t2g+pku6rRWYOq3MnfeVYMo9dVlzK7RRAXP+TBeKw1B4u7j8hhxaa\n7O2P077S3YWYgySez5f3iCXVe1pybxBSqbvGAXYtVSRXKoGHBGwwkxL657SsHMcY15ZtLsdzKH+O\nvTvVZDpnFaN6u/UFnZSEPnZeSyoPclX+ir1nYLgG5YOw1IrcdSMA4k62y0m4Y+oRO4CS+sLCib5X\nTXqAdZ20KO5M7MpAW8H8gwe5ZjtDIDdL2To9a/662UdCrkOaU/8AAhCewaCJ4noHOYRBRxF/95gg\nOeHOmNqtUoaj7gTuUiqBdMqPT+xukP3T08sG3UzzYm7GBoOlf4Agrp62Sfp9sqAOfUNylgXONeUS\nQa2C0PeiEdHUjRB6Lrv9PuvNUhGcctf/wOY2AZLH94XCuG0MvDIKGJdKPq24GaO7SHLldL3DaK+t\n5euVBgLKoeOso4BVsARZwP97Bf3jA8FhcedpGArrIWsLFbJWOwd0MLVkJTP0xCzYd4OkmWeMd2yS\nKFa0oln5F2mGGlsmcu4yIt7e6ya6j937ZBa2WpmRD9uM8jy7bbXQMw/o1amWI39rjmBsT9O8XYGG\n1LIbZRx7VVjQd3h5OIAG6/iUGqm8s58EQzMT+YKsQ9Jxzokfx6IOAEqQ9T24obikTzPbeVLVy05c\nWzHGnzwwPm005r63oM6pxaJx2uF/CyAvnbqQsWssOVFFq9aIzSC5eaW/kGXyYZ1IdLx1RuwU3FE6\njMoMrrMz1MBJWjfHlJtfds0z2O0YcbGfdguDoPI0uBvI8PX95KAYZQQHycH336oPxMtjiwVIVkSz\n3s1rCWssb9dx54yCAUNib7NyoMkxuHFsiix32Y537UJoeOERJ3f01mbndxBXMTiNhZycutQ3q2uQ\nCh7eD4udU8gpHvUsDxoF6jI+YrxS8Bv3Edf/mGN1qNZH/ryMtNYJUCHHedJegdMi9puLCrUcc8Z1\nei+lBq/qCSs2J8wumPvntjlwOKRWQdZ+pxnxcXHoESAXjBRDJyz8vqM6rHwMRUErjuECRDEjwrRH\nyNl3Ofl6YhMfx1i+/+CsvXOqdpyByQwQ7Wo/zB7VsR215pZqLF6XmIjF0hVrQt+O72GqCSujDUwI\nfIxo6ndRzjPobBD8y7KkbR1BCPMgH5260vG7PKB+1U9J/1Ydl1vZfDpaus/DEwBkIX6cHQwgZRsP\neTcorb3jU6QhHvTfu1Awn2sEm7tox9HRkwGkoBzf0T4CrVAiDsgC+kp2/ct8pFs0FIaedgvDCld5\n1i22YpAwupu0X5r3e3+5EEuJrUhWIeUjxOetAVeAWY/0puvms0ilu5fQRyMCFKw85vBf0GA8y94K\nqEbOP6OrclpD/+D5yWJCy/7nJO/pALWq+CRJwmm87L5ZuJxDmHmt69y3CyNDmiCGlRA2x+cPl6kC\nv/UDtcaVc5lzCZ27rhlg6Bl3cJMxvewPGIibdG5gx0xw+OuPkSc6X7hhbgRq8y3SYhwMQq3MUj/f\nN8EDCwuqLJkDgYUhQXlYk+egrBJDgQqasX4bgLlGGFJwHlnlkson35jWb8tQsGdcTxDRinee9aIt\nT0QM/tP8sXRQ/UDLMFsYAL+kTfChx6bwYi5RHFbjN8R0owjYZvf3WmDroYmKL792Xg+rUud8uSeg\n5ozUwaEnoyDWrqMGh3qJNy0oX9mAKY4wX0y9/aupceanBBrp9NF0u6R3mPkj+gCcnYum0ZqvXDjp\n2nEeDdkAHcFtDP4Bxm1dwAy2YN2gWi1ClZd7msOjLM43RHWLOoaXU2m1e7zjmDuCmn5gaq36FGES\nUvAjgRhCgDLSFgIsd0YQQx8RJq4bbsTazCKNUdUTEyPvJ6weOpoqYEiNPTC8Z80yEKZe1//kCtAn\njz8LocBvgqnH7BmiwN07nAfC9myJ9ET2Ri72inX8/SfLW5zEG9tbQ5wAHk/ZUaaZd+iXxEPDIqXB\njcT4Jq2D4jtcx0ubCHSyH5SLXH6mKBawnEjZU+vub8UmhPakk5xlKp1jenHwd0np98gzk+58oUIv\nK9Qi2Yom7qrqOZr8YEKnwIQkzo7xeOihBt+nVkaTsaXvP4C70iYTB4AmCvz06UDxlztOCby3D6dP\nEn1s+SmxaGXyjf8ioU1H/HuwACv+shzOwNrMY96Bz653g6KIKnrFs3EfLHY20mRw455e5+wRn36l\n9+O8pPHh//IMcnqS/m7avMNDaDzF8pJJEvktiDBzIVL1z5IUX1tJbWKuP3obTYVrDgNtkAP0xRd/\nrI6w1LK33cbtP7R8IYVOks/xXgLflwy1Jhgl/n+L7vnPTUL48UnZ9UUrEm9DBGf8ZYAjRHzfMNBF\nbMHQLM1F6rbapUU3jEo9hT01YqBMCl7Q5hlENIvkApeF9Mi4vBzxzAHh8hW1oFEZq4jAawR1tM+l\ny/0OVOPI2HsVMWKxQBbcfD4G7Opnubep63s3x7SPDTpkQrV2mon65VLa6VOQdZe03XYodsi03pWF\nyR1Rcl1sNS4hQVmq8PLiSTSaL2QVCCxAvt/HBORBEiuhvobhyGyKiF77cx9nIhPJyJsthF7vpSes\nzYH92Wj6QY5mR3hbgwhNDnr2hNt+iEDm3mbsrPVybClHrdWDd+OIUoFEXMOaUSnL7nOh+z4ntkl/\nBvMIHaIP3IBiZD8mU82pg2bTBLxTadMqPp/ummxhBqB8XW1JPm5CizKd+43EUibe3JDzaPwE5/Ui\nIdZzwOpsuKSohsZkwnzOPhH5DK5NBZ8jk5OPvOCv/5/tOFbekW8bPYSEdOfagmDQoxUwlzQN7f5r\nQbv+UD1kFEW7HMqIIEAgRJ1jxNSW8b0PbxY1CZx3yQKJAhmhf+71lwOXOXDdddyEvZhGxlRXPLKu\nRVbXSmqjzOOdHymFrzTk7PnFEnAc4E/aB5d9WE6FysqJ6nzvgSbq5a3AlOf0JYUFHXkDNjKDg/E/\nC8MYqvpvKgUtBlL/8tp2Ww7N71oh0sgdek9hW9UFYoquKf9bcMo+SdDUqV3VgtRDc3gO0XLyWPnC\n7X2+6MYLvEpcBjwSMz4UcLfOvM9pSCtl2qNE7bwtEgBfbALGZh6VecosavuB0/EQHQu+5B2JR212\nI3muZMG1CLJ3hVvu8LWQUG5YHgTspnglCtbVUdWb2RP+omtaIA8m5JS5CbtVV7eRoQkk1BdRt+i+\n85frkmQhdRO/TzU/DwCp+MWnJaLLQPZSJ/MVwjNfBtcXtsLJ04ckTN3oV1+72d4PgXnb0TmZpvWb\nDFsBWsiXKeU9Wjm1jJNr+r/JYxjugx0SxOJK4FPeXIX7IkexhG9DSV00imvPygzisbDkU9rgi6SH\n75hLEfXtbRG4bHzy1Chhj3eoFaZr6wqJhXcgkCNTCVSerjYVppeoQX0R9JUqfvTvLYKSM7Amxslr\ncgBIeOAhzQYZom5+Et6XZhNWdN+tqWmUEgyPCPeP7+lUacCSq4VJtbgCsbGD7MxLXXYHDYfgChGQ\njk3pQr5W+XZKMgBvO3riI4R1Mf0cTK7nnJo3JB0NBFjofRdnNzUEJ3l2bGktXlBpP82xzd7lfHt5\n5imoK/jDiWqWw8kuCo9niOAcZ2Bx9lY7qjrpVzby8HsGKcNpIDgDUmMi+t99ev454LXDPV/9+ebq\nESLcBq7hivsDo+4FoEu2inTKPVBUoUAiPQwUEjYSwWquAp/CMIriZvWOvAZIG8f0nSPhRGC1qF5j\nM7hofAAh/zov/wLEZxcjqHKOJyZHaY5uMa3mPKL/6pKmGZAB6nHO3GHIiSisw46Z13M9Vn6iatE3\n3JE1sdAArBaUxcEI0sQwCsY1gaQ/4ZecNoKFSdTHvQx/A9cMbvLHL/CQoJ10+1Vv3yTPKTXlz7yg\nEY+OGscOjqXrRs9NHcsp7sDzBIG+BLd/7C6DZF0ZLvgsK98kczEfRuARCAaj0xAJLDDHzApTG6zB\nxUHvciK9nBZdhjGSb5lUPOMVzgEO1mYZvSWbtDh/dIqYFhnM+nOhUoqSpUwgytOOD77XdQ9C62Xg\nHQ2xnm1jbTzH3J0QHmh6Y1jPscwESjtFmKboWRctX9IW4srbKA3cnAhH7W1xYYQDuRFr9FVuD7UR\nbRA2PdVYBLN079aiao+I3PiJCfJQbc4ag/XoL1ATO2x/tkTPXpwl0JhDTL7veTHK/vbvlLJoZ2Ju\nIOMkEDHcIzVzIQkaRjC63AYkoaZE8k8yTElIBwxcMSkJqWxqihny5p+tArPgMKXPPE3PwZfAcg/K\nmvu7QuxfepXXs63rvUSxqJ494fNxapRpXcSLxGHpm8Rka+rLR7YYWmRDPzras1CEwxuBGtSPv3Vu\nzxuL5t6elFYobwHY+O0LySuYX2jqqkXLeZ3PDW6icy7pbKwW7ttJPN3Np3upDPo+IC6+ZYc/zfIA\noYreoqNXVjbEH6vzwTmdxqcIzuRA4GOsPYtI6Zf0LjNvmLph/qlWpdJR77EXjWQb12B97U+Yf1mi\nLNC91k/rNoUmGrDzpykAxJ9DtBWySS4Zy9PHt0+BYuHnrHnEEW8J0K8r+VyaVlA3i/HqtNsK3z4F\nxYO7YfCkzb+Rn12t9v2Rq3UVTPBqBH4mUnG/2hB2CAi4a8NHeJHoP6Wpuvn91le168qw5lgNetQG\nmMrUn/mZlCvASNEKoPfB1RYBWvYSAxPyVe99fXBEewFR5GE/llANugsI5M+MyEhwAJic08R85PGQ\nb3R+hneUp6IQkM5qj9oveXRrGRc19jLlM8RC238GyGk7sX1KCc0ZXOVCurfT2KwjKFGjmpa5z3ZV\nXGdrQEj9wVu4rG8qpfL+BUsNIyoPC82CNeWwu2Ia3FlRJ4kxW4h7l3iu4iairtQgilYpRVOoteeE\nTZXzC8I4xPJhrLCcakUJP6vFSWxeYaeTf7/0SI3suK4WHKXN4JJjaHAnArNPaaecpFNEG1NZIQst\nHq6BFXkLz/Suyiy2vv98fivP3NJoa8nT6e9pw8oaErq1HjbTUYvoznj/txIdpYU6OumKZUUtghI+\nGWViTV9E+AGqdpPT1ImMZGUyLw6195cWizXgG2Ydb6L64yMeG+3I084Xd8hGyMmypcUMGo4bUpSW\nlzXiP4LOtuREDy+ltI7Lc0j5/nV5+Cx+LDYpR9vtzgAJh5ofM6Ewe+p1uDmt8lLWslMVEL7TKce4\nWlFRESqf8G6gIcofC5wqgiGzeQPkocqkOBTIZzGyDg1ojBJ4RcitQt1XKDXD2Ukx82VmHaFb7Kui\nfmpDpustlgst6wkLhkTdlM9JT0T6KTq2Dk6Tk+UvbflRJ+pe+KnCrDrgpTWKVp25xgPk23gOG43t\nAnJOAIsM48ZHgOm0EZhiQvqtfAmLzLt5FgQ1wmElBJAeKw79b5QUPL6mHflBBiwu2BWCR4cg3Rib\ngvnmCYyj3+FykRhIRMmeVCrA+Qildx6Un2IE5T9MWDU201WDwb6SzKEaN+ajQNw6MqyLnlhEjgVn\n79CYPhwvk+9i2/DyoL2TpKU43qGJrpulLcUvxrOXn9dHYodTNpUMaMshQS7UXMXYT9q4+Uz4m8AI\nx82LhcsmA/XJVXIkBSeVFAyZpfUoC1FP9mGjHVDYg88lCNrDLly1BRjendFDetXhw6TNeKOE9o1S\nOTiMEfA/kiIJ1RV/AXD0B91V1WReDcn8fbWrAF2AugPDo9qkRdD1UR814DEdI7sbpqmlaW/7Wtrd\nYGIVn8gG3HgCFxQATAXqKCSCq9uJnZBSXtgsPBC+NTOtBFCp/Icz3YHHc+iDXQcF7EabYZGmeq2P\n2TUSGoDv9/iyAt4V9DF8Igl07+Zx4F58QB/AuvmeGaSu1a1AbMB8FHQFOMEgFM2VrUK0BJm0qZ5T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YsRMCgpE20uiE182AEBo5HXccz3EpCqMHhipS39Bwy9fYzSWivzrUO1BVhQFl/\n+ZwH0UTGzOpPLeVY2qHyelemCkB0W8e3Mjt8ZhHoytMemEwhCy7dcFEvHslXpOrv/c8+CQwqG5Jp\no8B4oRsCKuXUMuoCXmr95tTB00XiBFj0lYRJUIfGl8YfF+YtRfd2MNNIsQPRTpk+9T15jrNRJYMx\nrcKDkJgS1tHmfpFOnitiQ0VnpxWHGxQnMZOo+ODF0N08A33BhxEJ2WfaVTwbAC09K0VCAvPHtytU\nIwhbzCUfrwToUz3fQ2U8MvXczMpdFSCYxft/B3CYpG67/3Q0jDzSFFPVxFBzL0EOp0d8Q8pBMQsV\nRas87Ggq3Y2f7w5oLjWXmw+CXxRmIuPlR8GnaZbeQUP2SN9rPeEPNdUJb+kZGtHYu9MCyGHfWuRS\nbz/lm2gyWgdXha5FgUzBJXKFBgMbaCCfwfAqG9DkIKkuSV7bqgR402UHvX45FnsNfq314aAEkYIK\n+xAevHA4ErOXxYfH9uf+5UfOeeaQz9YlWypeAeLs/C+Sg6Qkb4F8X8nn3b5nBu1qb3R+H+S3ctlh\nU9G3Il5c33q1V17uVi7Olfo9mPQ2HjF/tWb5EK/cvAUrrTglCj1YOcWfx908C8+pEfPARLC7i9YG\nHINXtkx54YrWQrshUCimodFf/6tg6q6rNk4WySd9jjzS+RSRdbtxDQERBo1vPjwwEN+7x5F2SOaP\n5Ws/+CWHHNek61IZphiGgDnPOo/ayQr1BqkFFi1wwDISQ0oynmyPDn6xW6sM0f6tXRxFC+ggh8pM\nSw4cF2hDsb0vOaeAqVahOUDpjNz59BkbexP4KenUVsZfFeUwco/9zCaafEgq46LY1zgEPdP+hvXC\nfa+mcCxbKTtA+GZTWtUVQZqK17/2A2EUK0F98+EUcVs5rKQu9/NwmAnU/6DkepntjUmvOiUYqM9U\nqcbq5NeFzg52bfqUwkCaDrZtyOh2P5D+iXDwxlGq04jKNoKmkiUd7aoU8Q4xUnr2b4wpwDX6qh3r\neXCtkJuB9OFZ28CQahcj9QDpqlRLhP+4OKEDTLkXjV9T2YZ65pt1lx4eBMV66SWnhgPmTM0kzJQi\nZSv1FnOLP18WM/Ctj0sU1ThhGab1NPHlZuEzPg/Da4cUqL9+nukzxfRNzRjV9Zfg0cYP6hg8nPpJ\nHqTcp+BqVP+PZmDCXrnYuDknhYqooeObts6NTnV/KQN6H88R6lUl9jD+gzpqmvFLd0u5CY67FdMF\nRvyaWsWYSF7ULg9KlcgvW9yDSh2ez0ei3YT+RcaTDSxIv3Q06C+riPuQkt1IhP2znvIVfpyyxnh4\nEsFZ4rEZpH0ReQueTZMqh9z1yYaJtheC+759zC70TCkkGq7l478o1kpkLHel6VqOi+yVDeiH2Rpf\npRszGf4thH5gTgHim9VG0NEhYZ/3f7iE7KBREKzMF26R9uVRba0rdtcvZINz5WSPyaynrkMaPCXC\nZyP/HoWnl8o0P9El0bGXTsMFqBlM25hJFupOAaeiVqQJzyJo1roHbsvxk1N1/ArzNbVn9rKgjvsr\n0PwDl72aHa4uk+g0Igne/8m3DY8OFyglDiOcPC057zlX+QymIZGhsDp9hzTYc2fuSmMCQtwx9bKc\nTsR+zjqjWosNoeuTcIIUrTQXQC0EuLSsrkUeU1nN3BRQtHLyFlOpozujPFwln8ZlpBf7SgBF+AWp\nJS5JsbIEcwW+I6DkmoA53xIAp9xvrA9UsA9IA1xYxCLbFs/Sog7NMtxSyW7E0nOmhKlkCbZ8kAVX\nhrWBADWgeQl9C1beXZ2LdtRsxV//gm8NCNtysFPPbDhODeF4/X4RbeDYaFim8PE47JV5+r5Ytfup\n1H3sjlwSWG2c90R85DRxi48x1Ge58Ifkk7nSGcCiSiejvzLQ51HXoH+fGpCD02mvsG0I7o2TDyW+\nbncf6Hx6vFePPfk2EwJ1J0KU78hvKOiaaDY9fkacghiH/+weArzzHWdNqgpsu6uqdtddSoUTj3LO\ng+dBZee+FUl2Zps6JdDjpJoTWfOARUMAQxUxehWlKtGS04xmfnUw0tP9kkKo/03ebcz5cl/9tOgk\ndq2VUgp+CmcCz1v4uGMV/5Z4dN7ZuePUeYBsMEuUm8iCJO/TJBEqi9Y9K7N6vfMXGoEmCf/kl2dF\niDUbuz5YQkydHKY0hkhqTukCj4NcXzKzuj7Uc4DUlyVn+UW2Qz6RPZZwvpUesJjlQOfBiXIawnCA\nzdzjDXdUDswTRchKBMjL1J3uqEsynwqqpdokXONCaohSsfY47jpdfqoCWWtdmHjT3kURgkPC+sB+\nZgXB3dFci2wrMRsBulD9pWgzJmOEks3xenaYu3sbTFNGEasQjIqk495GfH3QZtXThzx73O+R9Jl8\nwby5Vl+Nr8fvrOlFck6+D4f6W6NrcxD4pLDjutTaYGtnemWKCYyVZjmNryjYDN4Hz31j8JGjDzi+\nGOb19FNIEDOM40eMSnAT0ydORtmzw/MgyXmJzTKwLo9oPW1WwzIwyofmqnip/shqgfezIhHMHu4y\nkvO2tGYGfV7tMFWi6vamukFNMc1p6S7GLAlu+0+fUPccSQFhLsJiXjbifpSJ23yYDsLtKgYygqMd\naaoEaHvEPvf4MsncnD6GCPGBynUhCvwC2kei3wMT2cxzPXBv5CgHZBKvvpyoyK47+HyBH1typiTx\n7nlNNGGyaGsl+F52rLqHUkaCakl5CN4SYCjBn8osMbnpWRHnDvwEY47ZS/oqO2GWz0Wi0mXhvQ+Y\n/y52vaaVM9332i4xGdUTuvWNxwv8lBtCPRtDynoE4DY5zim7cwGaEaKBXwGCnpfB8MYmD9OWpT+t\n7qROTN0qL8bfmmgA0ev6npRc8yf7eRow4gs0gNsL9RQK6hiLlKxsWjTv209gO75+C7l3AQqZRNVk\nol8EQetOmHxNzWE9QwRSLwBg+wtACNndPTOYINcnn++aumnTa6zWdVlWSxSWMlvfhGI9wgQa+uqk\nZElz0cEWeGFg2IeZX620XOhupzCZ1A4RYxOZE7g3b0kx7h2Ksjbc0KtwGmfZ30O74Bl9bMJpPSuj\nQDh4d+yEJTRE0F0Q3uweesL6uH8c2gKxrIVSlAtRwbz17GbbqSyOJ82Lcf8iAbaM1vQpPMPfAQs3\nbet3MC58QctaYsMS9Ik44d3Sk+Gu0/TuTuqrlmIpXXYoNB3JCB0py5R4Hf3ouHgBfTnW8buZb0aQ\njOrpVq5S02THHUABxVVFBM2hxnxcm8+gT58lQPZwN8in3VlXcP/4LM2xbamaIuYRoN4ORcbvlOCt\nwlrJ0tWzZk3NHEN7jc8DcNMdHDGWOb1kY4ZBohri9IG6sSIVDJnKDCxNKgWveamXl0F33xW4jTS1\nAB/sXxFawN6E/Bh8O2tOs0jpniY00A2UOZKL6Hv/bYe9OEZ3E7yg4Lnov4eD6qbXQmXVmgxTSSmE\nmG8Y/oGMuxab33QwPMbnN0CHCIqI8nb6mY7bQj9Bg0E7MfqduGo81qYZL7ttsvGW45/nApil6j0g\n6rmbuJdtYfQ8fTLstKq0+E0Vgfot9fXa/3n/WE7vaOtkrKFWMFftlc5s3bX1mnM6cnd11aNhc2ci\nMJ3PflLyRWXd5eqXpzPBdS9dOeho4ko1qWPd27dEhWOtfYKSXkW+gW3jKfZPPwxSszDTV817+Apf\noRQJ3UAxKaADD+P54P5imMVLF/d5IgZEYlhWY1swYVX4uWtYo8M+aNk6U/2dRobLxgkItXFmNn4/\nQ5rXUfdoVAQT4Q90DQRJJdTx2dFzFBt/YLK1rG83DjeIO5Ewh9k03BaeU+3z1xFmxcdSGuk+4bpV\nNdYkKus+bgjp1XAyQa+ZtzkWaqu/ZYfSvCtj6Emjf2REGSQpCyMIjI7xb1Dba2w/tkAGyC6BLf3b\nW8OJuZuuDo/iuSjDjdxnTk1kI7N3vWSPl9ytJJ2q27B9P8DT3iYNBdb3KlEzu1XgLr3Jn5lWxM8m\nmpN8X/P0s/FxX/QXewk8feTBnzBCxTaNRxEUeq9YJIOxfUULDFImXhxxNyUFVz8tUwmItzNb2R5D\njkYkgVm8mHcp7S/9z1v3Oti7/9C+Crszeb+MhEwDOPMm3NVQczTdNUmwPlFwbjomc6yiMLUQtDbF\n6mlbr22N3smMY0qsyAdkQdoOVR4Sap378SptqxuuiJPx2cjlnXKHh9fmRKxmKSwokw/r/EkmSgVc\nfaog0QWEGrDJWWT/wqPZvXQVt1U2HjP2KAUV9ReYjAIhTR4El0rVBhpP3QxFY2lL9hxVsi7iQI1E\nLcIaeHmgVsylysZOfEKglWjzdcMm6YOwPn2ij8cwz5o1+0NsDUFtsX4uZltQqMIJVsKCut7ZP8np\n6RRR2YIpx3vrzbNuZu+OAQGoQ38/sOdiAo20A7oqB0qFIr5s3oTmHr6/Zr0SIvSBlN7G9lacM2Wx\nmKbiuPdTHVwYa4J7XiGw7kbV95q/PnzOhFp6GSFr4yl7ncWQS90ZHYOds0apWMmjSIACNFf3teAU\nmpSnNideFhGDPFaiX1tXnRWNKnx9E4PvZ3N95MHe3+2Fb8tP11kNt9mVyUAoE+mCaBGSDLvAq2m0\nPjEcbIgX2FkpVTYuZ+3B5CMYRfrj8bEzfGqVwIcirUdlAShKv9pU6uq+U7spAYg23jkIjiC1Cu4z\np2WRZMY9p8SzvI5NF9JP+mJaU02JxwNseWEQ1slIhxeWhLvlDB7lIL8+WaXOdAXXRI09GrrDIQ+N\n8XVwis3+ZqDK8BvzCPV2Wb8qMqsKz2DdWeBJwm/z0qyjaK8rnEQkFeN9IUuYYY2iAzqDmB8iWlv1\n8P21cavfLYQWN8sMjWaO35cnlTYOdyUZ+J9u6drSwZwefB42d/ViszTI/qJM545V90AIIET5MZBk\nMCnSWEpOtoLKjTQQfYJgfDZ2Uf4106x1Y0FfEZVnqbQ1T8iBEaP9F9hGTpsnyLv4nl2480EZXTpu\nZqxsgQeRRymtCc4dR7o41uVBhFcYjLH4fXkOqgnqNbRMYe/kg6jOYoHArigmkrx1InApo/Jb+mjn\n1ANr8HDls9hhvbxhJB3ycf6ekZ8kWVRALi9VTDE1YkXRmbKNF3GlYBtJysUxZkrzVqPTeav+Clfq\nYctA8ry4YXPoQlWnEMDnIIgvl974Eezyw8/IPk1eb/dLJGXbs1G7lILBCJFM/Z0gLtdqZSh5LvGa\nEOEc0BGUQwdaQMydI1pqm4UPUmku0NIKmZd7b1fvBECRSRGIWvdEewKUh20xjt+WSFlfZqX1ztBM\nKcueHWH96hLMdmYrrELRZ3U0ohpAj1Zqwp6eUjhyKPMT5+J/x3tG5HxxcT15EDEzjlQKRvxtph4N\nmHc73bD/J9xYyPRvam+ACiczu2K+uao2OkfbARqy4fATDhdZvrpmaSA0PonwE4izao2PKrc3gi6j\n+xl+38zj/k6VBayW1JuG5Z2aVXedJR0JuAVMSunfOovLz7zINPQHDFSU9P3FvrA5eT+p0RLlRkG1\nR312S03BgaGz7qAMkRN8yv70ritbeaa7moL+99YyKo5tG0ccj6g48gokLQ1TWqtMB5f/llvelS1b\n/fvp4mVR/UuLZ57Mmk59E/jJRWQU1feOKJEsNAegyqO6u7kPLX2NJpveSamTcMmOFMU7LePXfebo\n8rGYcfd4I6ibn4+agWy7hDNYFGV+a6TPd7Zm4Nhh7BzBita1AyY6sEB+cWOjQOG/xdAXWlUXwUYh\nl8uWCwiilAK70ahiFtjSNlAShXDI79LTezLIOqTwvgSvDgDYICKB1xntpv8Fj66RzL+EgmZ0lzHN\ngyTdHt+4yLsR+vDtUjW6AZFwuZ2MdGtVhzhus7bQ9yXQNgCRMEdmGND2rU4D6d9zdMpuNKQIUg1N\nTF5XOm98pz7Jpfe79z4pQM6T51N66yfe0JfJmi4gdPcpjrMH016MEA+qMp5oUfTmftp/srXEFclY\nzGKjoVBt2zUtqudj7bb2qzp9BCbkZqwnz9Z6VQ2d2nwinnQoOicKHwvgXa+sR3hCvdHEofdGefhC\nUntP9zgRujbOCtBUcGlKIQetiA/pLJ2ZWXFgSdFs9RuYiufYZm3fsSELgbsOGCb0cfwDgc5JDZUh\n/IhWyZWfckk1GQ7qlzf3ZIocTctcltg7KRYFBHzT1f5hsG5RobfneaAFNIg5gfh5IElW0RuooClh\nS8fc6jKKSiTqmOKpPsPimTB6VvO+OYDS5HSqUirswa1QeNZnvgIMnwJtqeSS97LE/oQuWErm7u9x\nWogBB+0G2g98sW3uGvOgeqoUHlam9GS9ZAaDjeaFurwzvtNMbgcjFxxxxYvgGMvwnofestpMNhwS\nkgaL2RM85aNEOWz40zp3dm7l9Dtrom3bkWSs+NpxFV1RLJh/9z8HkEQRivlMUEHdMVCcqtkqsB9s\nfm1H6wvvK7kjW9j8ID8ZWyUMBhLlVD601lgT4H+k6bUhc8z8F6NhR2opsZ7/5WDMlbhatVfDKY5e\nf4jUqt0BiMtscRi1tjKa0mxrO5CcWcKyXYayn/Jl3hfLElZpRmTfg3xdpcYUVMOAygZ0pU5mGI2l\nPjvYZw011nCDZH8rBjZmPBQOxtD7/IGPwfhgeBIMMZ+r36O+g1WfBGe5NoLCqViXwoQtD6TzxhBS\n3e0LjGvY34qyScbcaQ552vjy4qySyJbfktaEQztzWEWW4nAj5Y+H4m3FnS9aD2vSi9xx091AZos3\ntI6Lje3K3CbALfyVISiygBypco1eLB7OgtAzV5uyFLfq+VjydhL7m84xGfImeZMBi2CFK+fq+PPf\npsJDo51FclAUv90UAHSWdsmTGv3Fuuv1Fn/euuByCvvmZp/8WRpcQi0g8HOC24cQlOW7fxt0liSf\nLip6TY4OHgkcncMGBEDphFk4eKJhGqtiLo3UbiGTq1gIE0rVcSuO0WuwrtLLBqKNqJ412WWsyLGH\nQZEIrp0s/xFR2/tz6cw5w/exWCW4zzvJDL/OE3BiMcAM9UVYALtnhmVyIgYQWbtfyEnPmLoF62fT\nl/c2sqloZPemD8nt4fAYamxUy6NJPBO7GRokFCE6MJ1+zf931QZkoPFLII2ZSKYUgK71+Xy6N9Mp\nDTDQd8beTuJUC4w1IAtJ0k+pJKbWEzCmIb4ZRk0ls9n8LjkBGxcGnH1bLYJsbW68psPgjyBbPToA\naDrwiNwZS8SXEwdrPgdqxjYxIF8w4jBUFulWHxkVk9jDwClfbG62jDs7gC9l/NtXQEu10x4WuIjG\nnEPiZKKraylh7PIUe8xFRjWps4c8J7R5cm16QcXcPOnlb/NBAy+qw74keSe+T2AtabPOXzuYNyoY\n/KUR5CZGQyxyycpuOgyNiGeFcS6XFFYG7+rRNDWabqqlARPYzQqA/9lNq1csrSRIYM4Nfc/eRmOJ\n5dhiyYDxltRVK6SZB11h5D1DdEdUIaGPfmU0sxv2q41rIe8/0xk1P4CPJ0GFj8qOwe71Vq0BTm0d\n/z/f6vLlWpcGfqnR1EAZEptLgp4aic/UY3+VMpJqKQ7/V2Z15WQrz8WZ9GZAl7Ca3G1lhvzyHGAu\nu3eGIyDgO6xh7mW50a7lCVtQx9H5s2GUQOrjk3DP2cRRFXN8i6hI/n0o8ZX+88yczmFkM5Yjc0aB\nKON+OY+uiOWz+Vver9bF4wVR1Z88+YZ8liFQS4DzwHyqtw5OhkYNRbP4QMVFGpo7Ar5ATLMJsLRL\n50S/9O2zNFE7RmcSomCd3VsP1VmsUyiUNc4vrYJYNkGamQFmcYAVqi63V+e+MjUGV/ekL9VDW2oz\no4vdEMddLx2CRnpHiehqdk/4jIcf/NUZc/JtWWwOiJEAT5hEpJbVNhc0lmFu0OEst0fGiqLrI8ab\nhSLHitUxHnRvboeQirw7qW1j4HBvtpAsXvlcwefWsSsNUh+LtMMVyYO+f2bn/URKjV1E/NPPXXZN\nqyEO1Dvg8iV9i4ex8RNN8FUGz9NT1ZznNdTa4ma/HtUUbTMjh5YUQmaPhNXzRx3qKrwpSME5Huhs\nDnyiRDwTRV0f5fRV3cvb/cA2703WkctgmNmpKayZ3koO1LECDs+wivGWmk9K2/D2j7VC0mGD+h1l\n2xVPDfq3AYOEKzqsHT+BMHjeh7TOi7qWcmyX19WJzwIiAi1Iil2y96Ftv+Nz3rd+peCTTzDXk4zD\n5/d2uiSxB++jq8OxUBcxJKshzgtwtcfmhsakd83SKcLffexyiOQEk2lKBOSpd0tgDur5wJlrjMn8\nrok5XuTzf1SUzoUNEEn+lVJwZAE6V0SQue/GZkSeRaiVhPi+St8yk6VekquL21EhhTNLbujAvlA5\nXZct5zCTEvPhCBHiqPnH9Gk5lrUozwYWqpiFev0Jzw2EvkySFKoARYfKmEhtY0JpK9EOuonP0I10\nIW5W50+eUs2prgL3WLCgqDZ0szHYe3PrrAk78QlEn0dUO3oIk3WhIuZIvGpUN+AvVPrB9syZ3RDC\nnFKlaHN5wwRbga8jcaeuJ1WRJh2Z7JS0K4gFiBPDmN2HTdpqtDpsB4jePfIEctKbOL8hUzRVLosl\nVO5W3lwA4c4Pw7uDvk0eHD03T0zBOOR/3ibojhlw0kjBKAMUxHcj6Mo5cKSTMerYZ+Fh4prTAQap\nUyHl1DgONvqEtwyDyE1PAVlJL3zpEmTXnQY5OJrhshP3IKGOnicpi82XAdWqlOf/g3oAMklUuXpu\nUZs/CgkQ+hQ0KCNCyh2cTzqaflEtOZEKy8M3M+TrJWdN/thPZjep0TcT9oD1j8/2Qe2BO4iMV0Qo\nKYuaSKPGLPwXa5YwuWqlzc+YR48PHWgs/deOXnLNKwNfCZopHd+u31C+pRwoQIKZo15tX5br0P0I\no2b4xhB2ETlR7SyEIlvNvQjow6AFeVjJAlLu5WdgB69hzo6lBOcYuDAJ7Ss6N6wlNpRTZYgeScJk\nPUC9RSke1F04VBcC/IMYBB3uCW33arGg+2Nsd6t9tkBKtpTuQthj2WTJqMI/ho1xTlgs07/Y1rWh\n4fg+QY/IIS+gdqD+KPB4ppc6Z7q4PCD1hanPLTBy2n7V6zGMlWfaCSMFoc67u4EekqA2/w6lTCGq\ncPdhXbFW1csCo5WhNcaIhEWG3xuTz9hGtsqvmlT2qoJBtMgaiGX+bE5qdlKX0vD1dOvynhLLjSB2\n2EFeSbrBZcaplIXhVfvTEC2enp8ZSUmfJmQSGxDyhNROBdywP7aBhRBgzMLpEglFDLVR0PYRwLzQ\n4dX8qQmH6roQ7Nzn0OWgIuk5T60BnZzQWnqPfcABrNseUxf8ktDgWTvC/d0k04OAwn+qVpmwkrGq\nkShfAqojpZDJ+EIv2VDX5N8paf7pkcunBuPEWRbMRT265Oqt6cyufjvELvc0eDpgrlrmqBvRSrPY\nFF8JCJVxhtmKyGIruXg/TEi3sDF0pKDEjIXLAS6V6jOibG3eCYpUM1I7WFjDX0BGNzR2wfcfdohk\ng6TyShyou1pbjxsjMet8M1nh2leKcE8tJ10oSw0eBvd1DL5OJ7+a5SpZEMYnrOno/WcpK9SfTbFg\ngBkx6g0w+SxQNNlF6fC3HWjtl9htmi5nnvPdCZA6EShvReyLOpB43wdKj+TyIUxRnyV7eSnKlSt4\ncpJ0a58tPEi/DtHljbSjDOUjCo8RL2ytCcewHWI2GPOdImjTnK/ZU6AJiilqWE+biXVSgwTpGign\nBxT6b1A0TpJN8iKFfWaVy3vq39UnbETTPaS3qBhZr7XJbTT5JtrNGxvyC8+mijYGbt0r1BrNUvGc\npVWMw53wGNWRRvVELI6D3BZ8sdgPG/gNyfS1p0cESgUIPSTuWjuoSOPIN+7hVouVA73TmPyoqxKa\nLblEU1+warqoOYSYBHLQ8KEtymLTu3nO28vkC6Tjz/tPnlv4PS2NT4GCQcRPIrQsFEtRoMwZHQks\nVTBKFTIKNwJXGrGIWfGyKNoeDEvU/Oy4ugDHY0alWCFkSkcddmACF2/kTZP8z0G6r3bfl/T0F/ed\nPKOOygOs/m+u3TW5TQ+lloytQPqOHyFozL11KzTPPavhYvsD61f4AfByQ14KrKh1lUNfs0gTBiRa\nQ66cnbWq91HNJ27Cdjq9YV1NWGfvZFshr/CXpY9v05ZSGTogxXRETu9HjlfajuhiSysFM7kxhEC4\nD0K2/XMcKnEL2VfRKjMNTbZ41pBdpidFcrhkGq1uWM9vxaHKeieOEmINNTsMkJoKKM4ITWs4DXJ6\nakN4Wd2nPKbaDdGP0SMLjb4wy9xAuzTTCDC/S8AFKosSaqOiHUy9xJVZEd7XYuutHlyDCTDRC/+m\npoojVFjk67h5tsSPSii/M5eGg84DhpOP3DeTJVyIjNLwD9Asu02nxSnsw38NbROfc1UvNsmZIoEj\ns3lvDJsL46KLqMgC/PZQbNkC4CfUsF4xI+92FMoOUspkw1PaC0IsvkCRvaDyIRAMA4YcMJdyhPEn\nu33TyKK8GE76WlN4c3YVcIAIoducvrcWL/ukfzxkNOdlN3Ml8g2C0UaAeiE2ft/idLZlVJJeY06K\nTXovOiIx6EjIc4DUD7HQWKV6Qqz8KEXsMcZS4FBjwdnixmQq/sEpytd6VGitam2iDu7dwXKnSLMP\ntG04g8KErbn3ni3WgX6YQk68tVC0EDtwqaclwRr3g0iutYesYnPu/VOevu244Lo4R8UzJI0R0gUt\nhoItbkyNMMdWhO4R/Mth5V8x/aGdyaEKToO6i9NNHCx88ReJ5GZMpr+oHLtVwdv+fFWvHcHfy4iD\nHSR48HQkd6jqyejhjo8967NsQHAPcJX+Odx+ibZcrGpyQZI/tT/Hb9WB/EYf1rCa6zPKttafG/cc\nnwF687YJCDZ0NmwSvBgiSIPybp7nLhIr8QAhq9iJoiNeVJMN0W1I5w4DDcymzXBUebPg8CCdLSTi\nl+kR5TU0xU2YWxuXlDdYSEeP2nqefZ3xlsQ27n6gRQID5uvFua+9BRlQzNT6g4VqZyOC6X8gYdN8\nwqDcVT796YyrTT4tmLVW0M5hoN0xRVwHiKuqr6WU71xiGDSuczMcNCGLRMXcTT+rr9bR5VCA5jY5\nL98iXddxVFDEdmSV2ySUUlsMLPZD8eQSVllAi6snm2Psmk7GAXh3775WXsbhHDff+HVnYh2U89Xh\nUIM7RMGroZh1/w1hrDpzHzbf6pjXv9K1Y7yyUx2FwmC/jyK28fFvzb0w6iNbuhBkFp2O+ll9xTJt\nuS2jFGCxT2bF+a+OhRF+J45Rl2Ky2PevU9KzxBIX/Uqj2FcXI06+oLitXLisELttxgk5H3pIYUk6\n8KljxXKwMbNaHCmu8+3UzhlOUum5zvsgcaL6p8aOffMPmbisD3J0NeDJlDqJQ8VypFLaBPnaoQbh\n+Lyn+RGgABDkhAO6yEuYsfDpE7CG8crg2lbgBWEFNQQcy6ONOVPNHxwNQb0MHvlqxHzqyzfg0wHh\nNtZsYu1PzQSqXwLYLm3ZK06/if/yJAcYBG3KA/pW3ZsgYK9zu/yi9PZzmPeLrekM3tiQ+ZYpAz8I\nRkzlfZIV9zBB8+7FqTpA+TK8ntvlZ2PcWS7ZBHAIEIRQ1CfLVE/icXkNkXN4m/hJbqDT/wtdIM8x\nFRkxEotBDXgTTOsh4oH3LrOoT/nYZHdgGH5JhsjrdIoj9XS0zrGPCMxTNdLSKJ8r8BO/R8HxbRDF\nvUQCZpITGeMf/h8HDZqbyislhYCmvIeXgKwvlBloY+ngawFt3kS0y5smoJ2FGhYtu60PS5hCUIB9\nNwuMNqHS6pWBM7IKS5Kjy0pEaADeUfWGZOzS2M+xuwBp6own1KqFVSyyOiCnfJqksOVpfp/lUFV5\nv8SDBfGx5Kb64tA81kNH0GQ+D3Wj1LjfPPGvc6hUcQbe7SULNkkjpmxHatvqyfwmHyz+XuC7vOl2\nXk1IYScgEliO7WsVVSLTyPZttxHO/gywnuZLj/QQzWqFmzHjk6gkSxpr/NcPxrerNdiiV/siALnA\nHDdw8SmcnGzzZGecDNdMAciB6eIP6XOZuPv8vxU7qX4zzbwoqfAcF+iW2rnp0d2nlMwKJ7qUZZ6F\nNEfzylak1BkmWn3Beh7n6bam7Zg0IEi8f2VEsVUdGc2NXQD80dITrXEEnN3LifxTCroH+w3CR8EZ\njBRLOYMcfeKNUbOV2R6sdIdTSZgRbd/cE8WrYwZIAje4pD46Skc/enCTvNEE7/F4XbUluAt/Lm2I\nun9pMOwF3Q2WZ6fnjqeLY0jRTLt1xbHlgP78DDb8hoO1FCFsypbqTGAPUW31Bv2qVEF/2i+Hzz2s\njBsWn4WbTTGf1xtqgq+QCNm7lQvCvy2QI9s4fDqc+cIJ1V+AnWJ3KE16GML2rBCQE/Imj/3JOMb0\nE7yvTkhb1T169ctYXwGppwnCe3W+nAuOfKAIYvl38kM0whccqTA5KEWn65xHDQHNDae7tO1DCNtb\nkqIDymj5nC60Qt6EVHx0yYEJoarCe/tBO8HOI007s/4FwjH9uUBfIm/nkKshhIbQePfCotezsIM0\n/OIwz4Oq/i970XxhcSVJzGjtzl+4ZnN8fYa6d38xScbaTbY0SLddZRYQJed/G1PVbQRTzab+1NbS\nz94THvgecTJ8yJV3rvH+niYSER/0VwuqiFL5C5KQtX3xn1CUyQhEGzd8EIW1zxBShquQ/bdN1x+r\nm8vJozYIWv1w9aZSMuHXCosU8OzSst6fdfQy832n5uBCQtlAXskL8zr2FPYEbZUR0Yq44XQU2P4O\n+l4gViYLO+yBOI5M4WsVGt7g8Zlw1cUJDBF89QXcNhan+8rPSpwisCyBMnJAXo8Ols0qOW7D8+Kr\nFvz6lVoHk25K1JfM+hLO6dcp8nm9cdxXeD+HYM15sctIk6u8LLZGDQuzGcNPholJTJN1dTuSPl1H\nbu+iYa32hip3bUjXNNX+qle/OLWTBh+MyAA7iwUC6u1aJrrtQs9lkcZpFzvl6HgOczHBq5rrfs7+\nDi0nJ2zJ5e+uJ5xvQAgXzfIpHyI4k6kdha1fcxLEcHqzjyahdS7W8RLHFdfosJdx5ORQ326i08ji\nWu4KMWA0h8OnIJ+LBkNhYA8j2W5TVY3MwgXjlnml0Zq6qjyZY99FN4JTMQ3uQcs5VFdmIJkelTeF\n07dMKgVXrHY7svlC0wWFRr34wWqJazW+Cdavm2mrQDb97WeHQXMhNYGOqeH1ju7gKHq6lnXVqwuU\njqtywLdOUsk1UM1GVMrIntqhi19+cWL2WJz0vZtWEflLAuKWNLNwLdYQ+5J0p31Xp5MbrCMCiYbA\ns/Qp28seei474Q+xmx6XX3gRJO6P8DDTSx8jtwfoMDd9pgi4Q8Zu6Ke1meVzPRM5y5lXW5VBZ5X8\nBaM/xo41Thk8gE1pn0K3ReaP/m5R+IybYrJIlNMqA1XY3cuQ1g1upqTIb0PqT/AhcS0IoNr+Hkza\nib8a/ruZeOElexeJrJZhu6F+M1QSgJUopX9Z37Va5qsCdeTEUBChRekI73I8ERsRqaO22deLsbFx\npMvQkc9P1HsZb9AAuVFQnh0a/cFy+5I6jXA5AIoJLuj+vafINViAVYp1apgetngzOytS1l5KW6/i\nFJS+UNd9472N84au9TFYRFkyUlf9VXvRrQEjKx5mLjfkJpCMBUg4mjU7PToYZ/UXRh9GHAaKtU2K\n5csZ40wJNM+S/S/jZrhLsGOmk02NFaLS4W1ma4ODpRRh/s2ZxR2CGcXFpY4wYmL+gYwE9PJOdM2h\nd2JCcZA0szDIFmD1VPgNNSo5XaO4zlf0uGGe0dmB9KRRND646eMkpwTddiEtAR19AUrap/ldvKxH\nzCJQ6UZyH0/2v+pdIV14iUycsMBvIM1eehtgbBURwPu9JB/LDwW/xbvMN0XrbbFi7vUOQkSx9weI\ntyhQUmobhf37qz7IMEJZfJ8qIoVMI7zCdar/GqiO2qVU4NrdcHWdmfZatuAoDs/wrB2dGlax7a8Y\ng5Xbf7ws8KQ3F5OJNVOsJCvDfi8ydRMTIP8TUO+Nv/9T/UVcUzmzqY20PyV7e+zeQQt5B6hbOGT3\nObsJnei4WUDNmG1aVkvLLFkMosvHshU/Qb8wWlneD1ixpwfekxjiNFRkakaNZAxr8YbG0wI9GbZC\nApyeFu2bxl1UhoB8As4ShRgb0dWTEspeE9OSqBJ80aqtQQAIOPPpP6p92f6byBFQmNqC9/qhmQ9z\nnPSc5wyMTNtoqcHT7mtmwN2aVzZShkTOmzjOTjI6KRnel5kJ0vIjyn2zpuop/3ChwmgEGQ27vkYA\ngAMjns65Vg0uuGEMkIaxE1TZy/voKQ1GsVXVfjE1uA2yug7Fv4AKRRJe8rRFD19V9NnFYbtBVWvu\nz+ur5O5x8herDMG8KOAPAQ2dBol/1S8Qn4FmByWTDo1QX8/E3qzYciArbQG5WwW8/CKW9GMKBfn1\n9PfPcHcXz9GpnaGZBvuQfDCbbmn3rgpA0WAXEk3ne4zna1rG47Ps7mTcbOqXbLvoFqtv3zgklJBH\nDc1QHjqDlN+kbM/jl/cEtGCLTacYN1jU/gPBcyUgZ3OW++YDlnMMoC+Ia7lKl2JmgabuIKeTdhtk\n9jRcJOLt4m9YxsPu2eqqShKUjqObOmJR8OA/J2VVtYE5wdBrLZMnbYNEidtOxbDmF8Y3kR+cvrnT\nOKmm81K69ykimihdbc9ayJGnVU0OSFs36QHbPAEiJDJsUutX3ZHeAOTH0ra0VMQ7Z11W4dI8zp+Y\noApAAmwPlCHAP7rX/swxfeXNEJUvpdhvHtytQRfOQf7qNzPw9QXHwYg9C9UtgB6P0lxt2Xh8diRo\nFvs67+nxLzbWSjCuFEP43VOZ5NlMeVl8bPJV5fbuXhcw4Gkv4R8Q3sNhsj5DFvs3G24VXSjgk+b2\nOpLWgMpIv5C3+Cjj8jlHhzU/enyhJzSCOh08VggXeRXBH726mAT3rxTXAfP6LCueYdf6AmTj3+SZ\nrrgzYFkGpudHFi3gyn4IjfbaIzU/gpfXT7feT7flj0gxL/LdcvuDhpEHfBdEH1Et0zgb8H4UlxIS\nM7iwjlRZHEvWUQrLmIzwl8dIdpqazejc9flcxrgREZr0S9qnwcLvJv5r12Ri7QgCvEK2tgHeXjeD\nx8teYRAe++fib1iK5+VM5pKinAsBYK2GIeFWbRscvx+WRConDeT91Nok7zq3+7xgyXHG5ANQrlPo\n3UeJzYQrAeHg0+7q2MI52S525hcbNpvFqnhTtlR/poGtezz9dCZtnaDNizPDc9SKrkYYofC/0Gik\nYVsJVmLYM5TxwVTIOVFaV8/o28C0oDWJjd0bahNTxrFiAKHaEDEWT5Tn0x+Uz8tw1BPGBArrxHBP\nuQZihZsORmIiYuvkd0RJlmSAXE0uK36MB45FNYzN1YPfwVze9PTY03JPZyWWjD2fiJiN1g1mzbX5\n3VpXiLA/5gbBZxJ0Qud/WDhxjFZ/WB95nYmWsndXlnnyvWZqTa+DFeY+qTJmCZssKsEDbiHuWjg9\ngwbnydRZe1J9rkacLHmhqTYavWJ6avQfRt4aZPERxu41xgqrhFBYtFBocw4hXHbvPzXRWrZsaj82\nhQ9Gqa2Q2NJQHq0MmxKdc4X+QwlGSjPq9QqJVTbZBtQNbWUuEkZ8ru8F3c4xw53LSYgnoD/LijbL\neH5v8VyZyv6cSxfDFrqZKebvqx56LZ21plILAxHfJXCwNSLEvgYN3RZIqgUt/CclmosEnCE15kJk\n35bgk8mlzzgtA8KXaMCGPiwC01sIuehOWcks0VOQcw71VduLGCGWhGeSRt8/sC/SE9OUQOGiesV/\nyfupOH+PfGc7as04KqHFxJEwQh35O1alPuveZWaGEWvgDNWrqqV11V5FZSfMLMFN6VTOrHU945rD\nV+peqFMCmz4wsDx/3w10wFHfMp1DlO3YD37lk2iJfSgVBkV4pIlHhhgQyCHtzHzRHLfyta0oggGS\nIFGgvqzyyL5s9hl7YjUQKJ7TFnmRGg4C6mYJ11PRV7Sc342BzpP65yLV+pSWyobC9hel9DQZz0ig\ncMuVQJ9o6fq12+o0TQmC2k/TZDsKqxN5y1CVFt6nGjuw7PXhCHaVfK1fWv1BnM/VI9EcT4FTYvXG\n2o7dyInIhf48PrT1wIKmMts9Z5tSNZ6ne8rEhOM0ofqb8iYFplZmcpTMS7+Z0FyiZ73yQMUyQqpg\nmPJRqjzmThTMOklM7ho0cLs3FX3/0r14iu6K+kcqZeErRJz6ttFV3WBh9wqkoLnbaQUPx2WuCW3p\nL4zT2+Go+sV4aQW6YCeKORsERf7bZpzUNG6yGG/Kw9RBhnYtp7zpHOyOIwxgF/4PLEoej+hIpVcL\nmsOy5auoivXJs1ZPXsvFKeUVPcOcJdHnDD3HqbdnEMcjZjOPbKyQr29IdopLNqd/tAZJIR9B9JUu\ne1LeLdSTnlfc/Iyp9Mgg4Ek+TqxAr4wEn1WU7yPqhnE0JVk+YrmbMZb9H2yN7EsI9dIumjUKQDjQ\nkYROKAltIU1Muo58HOxNqlDMxZy+tPSoP5ua4o0w7V8LaLhx/kELyhkUQvuMimuxkQfTLZ4ejr98\nwgB82UoFb0monAZ0TH+Tr/U9CXuOuQMVoejR2rzQMYOtIW7+8M9ChybaEa6AEu8gBveL9cMYqpZ2\nwZzVIAN7Espzn6mAVXFmxCv1g4/nTT2MBJY9B5O6azSkP5j4DrFMBydrH6daE6y6JUc4aEaP0PHC\nVv1Oz8dyzL81xmTN5hMmJIdyjTdtXORda55fGuoM+QcUj4uaX+hyIL4QiruQ0AFrVMc3LegT4qGY\nvLxXH834gX60SuWokq74T+pMpCcSfwawdMsHumgX48DccK0qyVPcQYnCO1bGboWJrTB3tviYcSPG\nDU2Y2E41QtpNDODYFUboE0Y2rgx58LYj7KJ7JfesW7pXuhLUpapryBJ+bMaq8eEEGRqK9i1l17AU\ng18Ln1rWecBnBp7NElLHC9/Dk+da3EE9UhxTluxVs/0kIeMobtrIbCMS5lOTb1tJ77RR6on7olKe\n5gq3u0AvR2T1srkrBMb37t0hO+4pcAEczJZAEaaRwaRbQnwBNeHVYTmfu7cqh1vG4tspR6NZ4S3y\nlQEcJskyKtCMLKE2N0dTdr4NPtONn4DQk+GC/Ur4VZSCEct5BvQu7o7sFVMlBb6f2y9cjbbRPge2\nWeXoaLy/mHQiN6rofABCfEzGqiBYhDZGGZLBehvrLM02LaqODoTUgUFFgzvAiKUwCSCVKbY7NoL3\nGVSKS37piPLjTIJCsjA1c0nqufK74ubS0/+NlOjKP9+adiYo5IPsXj/eIcu18MXJoxZpdEAfHQ4e\nhnbSzzR1GLKucPxX0rcYKa26VHfQFsHcmo2sqyKvkUINRDNUxSCnBIVQjiWfBEdprh199PSp/jyJ\nPs2Hb1TFMA38HRbtQDPDaZaERiipJOvikIsZFbAQMAT2hQYt4oHb61NvJhZKnYXh0ib3Ew/ntNwy\n+knTvlxK9DY00vJRF64NBgLYO3kpmqPVxshmgcNPqQmRS8GKl2JVr7AVkrrXDV82Z5Q1sbtSyt8X\nWmINiIvA6O8C1MqFmIQxx6LmfEUtTsNP4RjK7o8HasiXivqK4ikiAYaLGiEJAyJQzi5UcdHhYYqi\nPcPB2LzqZhd2c0I6RqsM385eudgvQE2GpRmtzFOx5vrGZQ8GtVY9PL62SZUiEvA5mFzLbzJd3c4x\nVzITXRl1RhvlAIV1vLHl9a3NlwdV6vrqzkhOqirU8Chwj2tXGV/sRsRCYQkohUFj5/vahQtnEDWb\n37IJd+PnfWiqTHRv8gtmsnfya1uS9TLhPQBkZkdS3BxLgxoxXYZ/Hb0OgCIPkfGYMDcfRXTsgL7X\ngeQgQhIXj4YQ5fqhuAlUmJLxRZClHwZ/JGq5hzOVQFYbyoAmyfexy8n8lyX7n0YkZ/gQsbAvi2k9\nD6S8cKvJaB5H9HGL6niTcnifc1ZbmZtYErcfAjy4hDo4hhDz6uSZe2UBYIdnnxxWDNFfuZTuUwNG\n7wk9VSIIKnL2iqUii1PlANPcHrAjEVJ0pZzaxUH8XusRymZyOc/HGNjgMMirpAovhQlESxtYLXDF\nAjZ47U17fGWWZfu9TgZTkfOymAIjNyLsi3pEn9VpEJrMwYV/YBWmXAPsHlCpsbXsn7Ok5wLf7IiV\nuOPuckdKxnBztf+o/DRnc6HYm7S1xJh+ASeF49/qaops+ZrYH/KZO395eypl4D0eoxFZXjJulVEc\niLB96enyZiZ/53hs7bC44PI5ZvjDdnCoyi4awnARLlss5tW0Oasc1JxGbvoLUfWyrwXe7GdV61lA\nkB+1U1EBVf5O2rs7kPwgtr9ngU378ajDlcaBJGA6OqxWrULy6fmhR8DZV2wYeu/R4m57AK1sTO9C\nHDUMVfLQ9kk/bDGEwjunj9eylYp770vg4kkOtjvg4i2VURyJVtVoynT/qeIoI9upsqc5wO7L0i6c\nqKYABDpM3RV3J9Cus0F+9GYmZ3D1LJrNhyz2zEd2iqHdbliu4pxkqSLjvJt6uaLyHwVbVj+WQZce\npX7XtHUlsU8PZPf4T6RkCvSQns+G1pTI/PZyKjOZVmYdIcff0DqrDnNVZiyBCzFpTtgUlnO1hoFf\nETDNVoQntcb8MMKqOiU7CYfjAfDCaeaYrgKEhaY4EsVkJh+WEJPEKeN3oCXucb5TUp0vmCxd7Ztw\nxXXu70zzeaqZddSe19svJA954Lnt6p4c4YDrC06MPll2LgcvD399Njhopzh1rr1m/nhOzdAHW7MN\n5lWD/SDNI2kFWoK481ZtznrS4elhsB49Q7H2oRCBDDzdDJZsCPYTB+QpuVNErXt0tWhhjRmysFbL\n5zWn68wuhkjgOldFyLLrtkg7kW/K50bOKdDruDD6ct9beg78n+nWlNBUXTXnwhZJbmeIicbTUy/7\nDLpsXLollMjg1cZVl4BjUM37kR5BYYw9dD+faJn5p7Viec4WBmL4Jshu+uPW6miPH3MXjnMw+vS/\n9ILNBLazHvTUG8FUuY8VZSVt1OLDVz7gQSROOQE86I8mZ7OC+mETerXz6IP0vEofLdvmr3Dleqf1\ncGm8fBZQNipa/jY49sHCy7ULOSAQNNK72mmCtPGR4shtx8i6I85yPV/HEqwBhcQTyTC/RgBzpOV6\n9zDQmwVhOQXX/ozGV9XfoiUcnxcNCa2yvwRS/HLQZONBwOSrUp1XCF/hK/q1N0wNLQYt48FVjidX\nFjiqQ9r9usTJpEj6MnGyOSJ6MOq6Npi0yg8LGlIRVvkmavMvnDGiWDnmBExtjaYGNKUY1vUBh4UO\nt0KRXPZK+3mPADbVB9TexPOWgBsTXqsddq7ho8Nyb2vo+rnQXjH3eoqXRRa/V5mjbTZqMndUhpuD\ndUqqjwAQyBnfWFuy11PYiLKbL2iSQZZ2pHI8LZHuL+ENKQaJuBROSZgdO5rtXUBZt9UwJw4tVxEo\nUF3Yx7lIQqmKZpFmTJOSGq8Zu/ZoL49zy/7VDB2O8JkayMBeoCSz1zjX1ajPUp2I4d411m5gCyXA\nLo4s1Otg+jhqr/RUKJLSmnDPxDMdIK5cC7jeD1D8vxBhPKbs0IT27112nCP6UzPdrgSvtus6RdyR\nLBMhoCL3ouJSGCuh8zcQcXOt7SnZBHdhkQwhklE1Vd6BaA7ceidn3j2hg8hKQ2BswxrzeIKCH1Aq\nzI70mzMpNCGmC1r3LEvKhEP4HY/pbDc9N7Jfn4m2vgqe5cCiWyITZm6RkUKwcPLGVr6nCccJ6ng+\nArCL/X1zSNTvajbTB45vHCPkRxa+K5GBvzG2HJCHX2nQRKQlXdxnQeydIno1Ojz6fImBzeTiDREs\nA67V3BtECFepulKNqyXrOJzE3KI3XWPTLi3TiuNMJaJ9WSB4RWQ72juYKnST69wkMJL1NQ6a+rlW\nYTBgMuh9f4yW+n86Ri4ApEwZ/kF82wOnTKrI71DwhL8Bc5UgnvZHyZktxFp4ATsiv1rbrbCCEHrl\nKXSVc6ZWgDdDq20Zy5GtMilBE3d7jw9RvrehqdhlYsrGCXXnCzievL3ro0KhZRsfQCLQrwjPUn3H\nmyoyD0HsfOCzXm9cvX8etU68ZEQafUOCAC/o6HGdNHY1eqLZK4Af04r27kUubK3av/8Dig+AgKX/\n6+1j1QXj0/0X9g/co/zahQfij780MaukLp2akiQ4VIy2Mavy+v47Z98F0sGBpAdLPg45/hiUzOo7\nE1KkhyR3ZUdNeFpVEs+ZWLB2wL8Ron44UDN5sCje3T1yA2u2N8ovDgXUCcSnI9LGvxTOGMWS7AW4\nbda0tgKqaI1iJkePdQCw5TvoDTCTJ9ohds3dzsxjhjm96CM8PsH/pV/YfB7CfZAfU6ut18uSNTd6\nh90EBXwgfcGzJ6zBqIn0FL8Mek7UPUgojtMHB5aNtq5iQ2YQQZWp+Zr+VFkg7GFMsMzN6RqAkjM+\nNRcApxULoOAGR//ODloQ/Ns5WY0jm7sjVEXPiRtM3IwI/U495GNrydaulAtuZMb7L3IeX8YHAGwj\ntq2Flxvip7D4//UHvICnh25rUbGQXu9Z7jzaAeJ1SyYbeHIkAAj8KE+iu1DzYit0BeUFktVhS0gz\nxJ8fZ5OqYltzM8XNAq4pJfZLpUX3Gyt2Q/QYANJQYhcT+RS9gpMEWMser14TzQXtjepNCB8DdF02\n8O8v8Ijow1eo/UJZeLqP2uSh2WTo7Ynmz/FyU3kvTgpJqO9JK8KGjgxEgnxyMIV8WhbV7hwjUlis\neerFqi0Vjdk4dVP3X7yWyfLSzZM/F/y6PkQoYgxdStur1YqU74QRivmA35bqGjR3TA//bZPF4Yr2\nLNouAie2tUeg/09QD0hrR9GVRrGE2M8Kx3rg3vZh4Ztuz3Idx8VTVFunVddYpN57ssOz5SiI3JR1\n/q9oGNPbGGbuuTgRRxBJTOLJw4INwJco7+RPcJRYHURIgGB6WKdibpHCEEcwKAJ+177HnG8C7fW2\n8WMVftOeB5FK1Nh+Xk27uxdIUDL4c2NGhCI/NLWfIgBkkrL3SgnAnBMHSvKJjxuPxEyCxMcOmhiB\nCUVQRfB6wlLm6aQMiKn0+Ol59aC1B13qTee8B9VJvYIGgfCKrwaaouahyKrWVrYCqhB4pyXccQS/\nwWk8ajQ3vTb9Lw6AwV71vEzEq183gGJZae5gcBI2bRJeET5eR/Jsi/0vwYlr2dxWL5g+kOeX7j6P\n2kJyV7He18AoEfoyP8qoz51GAO5gBE7Q6la872ekiDxivcdLrzmDfO4XNAKMa8/1TwhKQ0JMCa+I\n5DYl+S9GvxXe5/jsCQ0n9nyCtOe8F1n8jP3w9qQ1VOIV3byg7FuHgr13x0HEEtQi9No6LQEMsWHJ\nyUPPyUb/P6MqqsklHEXiYLE7hj7/UsgvbpABNS3DGAuJB88oudOb5ymQprJuA4BuGypVTJjEjPkL\nhBW24lj3yojW5K0ErZultNEGlpgagNZSQMMBHrnPQvWmt4JV/FQ21ygT9AG9ziKBUTxrvAwNkO+b\nwsunQ0qrlKGDIgdLpyftMlef6BbMlzivuuZQ0Fbf4aOUCSSjuuc1FNuwXFys3SEaRSRvrGsUmjYr\npIBTWSXqFAlczkNEd0JKomJH9hgU98jkSKcV6yS4OZchFtW7yhkoHzswINsCBoKgph/T66qIqkfa\nhhwyFqDPH4XiqlTu+anvrtVz/UY4/LmHXhN2hkcpZDS1zXVVGZOOdxKiSO3K/NGharXnbrIxU20h\nhhPODVnTe2ZzK+cPH0ilKvQB7pbuxhYEfrUhEZhqrlGEh/ligP31Jo32zGO1QjVeeyQairJfA5B2\nDj5GZC3vp0Fj1Igb9KRWeyqdZt9bismoF4WqzoKqp9I8t1DPHxF65v33frTxTm5dBIxWRymExJEl\ntS/ack1uzRD8s+OCdVJql+kTaVP2bgnsiV3h8Z/mqIEWeiblobYx4mqqM2twatwOJK8o/hujDUH9\nCCRffhj/Y6pNafspzVGXDOC3GwC5vqXDVm2IejvHZ2A6GEUQDRaz2dkK65ri/MIFRXvTKjdH058b\nSyTDQkbDxogxqbD6lABK9mMHaIAuNRQKzwRi8Sn+Af7fuhuI0cCRcnPSNiuxOyst5xq5dV72D1pf\npebOAKPuIR5F+SRtZu2Fx555/RV6dKGmLjI8vrVqJaS9mKb4tUW9aglYy3XiX+uAuyKbGFMipZKQ\nuFo6bCaXhVOYjMmIr6aOEtxOP5hr6AHsD+e+7oMEZvkBC3QoKPQ1A6wY2iPq5SzmKKsFG9GxB0i3\nOBggwrVE9XN+5wgzcZJMzuLzigVJrNDSskgy0wGBPV261mztiDQf2Kb5cK8OpzPez2aLWWwbIoe7\nVQqjc3YdXxpFbV8dNr7Bp7er7WtvIU+jF3/KPOls6krj7xf+DdU2TQePch9L6FmGWt4HzFDc+QDb\nhLKEF01ibdiHURy8sqg3yPW/jtC3YtreXtdiZMc9UDqXRvjmEKBUN8aqbnUdqoMvKM8UgUzfK9LW\nRWkcj3n1xMja69c3OxvB1OQ4uI4hsPvCgM17IF/Pf/UP2S2sWPBHnMRrxHISp1fhjbD/YIgunnzq\neFK1/LfLFCIQEpPSSYxj470j4tSpI2xNEJb96Zv/ZxFpKEDgkP5aCS44UinLPPHR1SCuiQxL5qmT\n92T+8KPyxymD/mxV+pE+mzSysdOEq80NL+ADi7MEtgkrTGeiYKCBaKzTs3R81aQrTAAYz6s++N5k\npfGtnm6X43GX1fSr5lOE8z/t3VXXFSKcPoYOtYanYnx2KfqUXeXIjPo+qGcs7YCzqX6qSWIB+zCo\nQXCZs5RQ3MPF2q6AJ6UEQesHW0b0um2k6Qi1LGXDmzrKXwOc3UkeqqSATbxFOjYfGWXV8/vJJxYZ\n/7PB/ZGuHcPDttx2tdtyGNBJMHXlV2ytMRByPAguZgnmFSmFgzii7OIBbMxD68GbfqejpOR2j7NU\nxvzZqNS16Ogt4bKHXjVXuqrbi51E1Z1cR0bklST5gVORKWkUo19vI5cmeIjJZ+rxgqbq5RkfeGZR\nGYHGYY9hERdigPpbZmM1NuuWhBil9TpxJ7DjVVrXjVxsJN2OJ1TFaE/rjSwI+c2DNsRaKbQJWbQ6\nMZuGDkXaW+sELHjwENqOTVS/TDoGK3suM3o/qz7kouORfJ68iMKzehMnH3Z/Pce1KRKvp10qY1+O\n8LkJ8AnQ1mxonF6u3yJ5Vc0kJe9DRgBRU4Aa67G8FbxUlFGoEc/g511DTBjAeT2L2F/QMl5BSWYi\ndgQcsTCWPVhTLL7PTdx1Mw+gFZLJtYbIkCxFtBQjdP0c1HE7p+0zJLYDdI7GIkKZgDVdWWuGUwdM\nn5GfbCtVMKR4qHg6lS0F2E7PWhAqhkclMINF/455sQB+RWfSceEdWBxve38YvCPC7EPZ9mxDc8NU\nBx1k3awhA2X91SDW7mpp0LXtFmWXldJeT3ziLu5aA1JdFvYOXm6ViUfys4vIKbXlR8dZ8ID1e566\nvX0zebAO9mizOsZOF9w0t/DB6rFOUok+CILiYQv0KUMp4J1+ZyAzCd+nJ7XCAQcbh94TAn1zsuup\nmXmw1K3Zhm/fPNveLgdEfNGMIdXswRPWGeFPVYOqm58BBbgEpW7VJ3tjf4MBy9VBXdkuvgiAP52X\nFaJCoNHp+Z+k0/sz6pocSQ+Rss2F2oGR668tl+60sBwuzlxfVogj8hZyLAmn/H71b+w6QxaCJ9XP\nzVrq1wLWSI5KFjQrwGw8CKU9GcYUxZ4xDXSPJvA7+ArssEQH3r1mUj6IVXRLHmTp6qLddb5blwpH\nKr15GCzF1IJyoNOwC2XBh0gKUsTra4pjYh5IozBR7lQQtehhJx/sxCSCtojMtH0Bv5DUBUorMk+o\nJLjWxb6A0SDOd3qiZJVmaTXEoT+OoFGCIrYYm8Pc6I5PbX7GBWltG0bLarMsi1wEJdTvoYHH5sV1\nZncW5IYvSvUixKVsbvdpIOOPX+nT+5NgzC9MQ+1dPQDztk26fM3XkblfjVt49ECiyjXm8zrHcBJE\nGKTWsyaTtP944oQYlZSss/Ilh+MaGR2ebfqphFN3HYF/Ya/+X8PHIUbQwjqS+DICqGkt5DAyhVwk\nOmOFC7Z8ac2xzdzdlEmdBZBe54rWkuKmjgmpxTW6oniJHR0RYmQOqu1kiVJXYFt9xGi7AeTT4qgY\nXTHA+d0aczjLsR/O1idcXFSLxjd09uv4OnYPwJRi+OLjp3vybE+j+Oi/brOW9et4WfWURHPHOU5I\nyd13Djdk7u76lY6o6Q7iF7VhaLWFeNteoN+kvhZBfPl0XKM7PRHJtLCINBxfSf0XYz73AhW1mGjm\nuOPGK+R8h/SEZdp49pA5gcsBstytpWHBOlSqWQZ0KOvKfeoeb7igOe/vJCJ4I/01cRg+Vq9FGyUJ\nCNf1n7sltWUMEBSUPfEnan5hjzdRSibOL4l50PwSo4uf3QMbFfPsjA0FKpb0VTTKzVnyYL0kz8P7\ncRX9TWlUI+N0TYukyVQ0Ebo20fUC9sBnD9VpOcZFUPiHdvat08wbJvCEacJuwQF2ViY7u8dKrnLy\npM2i0O/KcM1VXObFhVWj1Ke9hKaPiEdrLGxZ+DCkK5V72TMNWAnvFXQH3zi6UntBms1JtBl9mQ+D\nQyTu4WR6oOschFMZ35vUwvQ4e3izzIrREmfDtQHl4cPwxCXC6XnnW8EonKyMH9L/LGqu+jAAujQy\nK5AmwgCM4sudbd1NAeq3K9rn5aeZqg9veBJ779ARPaSJwyZL5WCp3jbWH7dkLPucAEYe2M4ZgpA9\nrAefqAbc8D/BSRyCLI3Yl85z+wTRZTVvCnYG7Uk+wv9/Q0ez/1qZO/Mu5AQnFZXtYZnAZBMGC97P\namYFgAtQzTzfjWXtUz2fwSSZIlwb0hRZZ1jzpuQD3Zxe4cj08o/ZQOtMriRFfm8+Xv0PX7zxp931\ncNOp4adVM8ASl0jepFM47HOhjhzizCrHLdC8qy/Y7uB0ICEiThzmNXzat6cT4pfYc5OYJvFZb5SY\n8sqdW4CXbZIpjr8A+bJWn27imA5c/u3rgm8Q8cI9t2dYlfC5Mmc4umRNxGtHRBw/nZysM8gNTirL\nKRTlPEsrtY+fCGcHMcwnkUDib60vb6Pv3hD2PXh7xEBQhIypPVO3FXKk0SBRxGZ6idsuFZ4yO49K\nDeJQhvzL/k6lVrSx4Vq9zoiOFgz79CKsIiZpOJkQqor5yWtabwsx8FQz8ebuNAMxEbhPjHh6en51\nIMGZCxTNyfrJq7sjO6M2eZsioZXol3XElNdo8encRfI2MMeYuT1F6DB6Rt2TtVqkEInQUPAQnLT+\nZatomi1ePvRa20yPHWmK7ovdRV5a4tMrl2aXHw3WnbouWcq3WDtpSjcpgAYD8Tv51gQP3KpZZxS5\nWIrcIPdaMnxhVncbmCiFbE2qwBIG/BR2cTdTAnJRzimcg6zQkEDqHr7oMKV+5km+7gWTSjyVoN+Q\n9n7DKQMdFMCXKd+1SR6pM0ZNDrTX5hDhlWmS+PF2WX2LxzMU25doMo1KGHM8l4O7sKW76HqtPGLC\nvtWMdjdxllTTdI6Ivy36E91Q7fFR3c9iyLY06EeogAWhZxgB1BrKpSAki833aKfE2lWsBRr2LXjG\nubiBBpHakP+n+khX9s2vvGcX8TMiVgGpjPCaCCqUVEo/PhQQGfujK6F5KrXaOcQakSPU7lFSvbsX\naeg3uhqRkBWthDA5NOLU8NGABBH7ywS5WTkYVHfVEAM6vN/aL90hhskL3nvoJVvn0Si0C669V1op\nv06UNqNlfE6iimUHx1+d75KQwGVe6xVSLRNw8vifin3pJll7xzvq5pJhBwl95LiQpQbB5bSW9+P0\npbeTLmhGPNLGU5ML2EcwD2GQEvUsQZa1p+qK2lt5Fq4FoREkecspEhmpZyM4dnLFQf0/hI9k/v6t\nb3w7FmYY4Ldkltr3DsGFq/bCI25bMLM1J9JhwQN6lhT3MG3fs9M/SE7IjzWDK6ottaMF4K9YtNBO\nba2o20zGs4KsZewBfyHcX3BqsEMSptD7RVdm5ri3/qs2wsheKjoguwHHXPpcNb1WKp2PIR/rtC1+\n317uQd6mO8zB+6vSzmdk7S7x89i6JN12cIaL+2SA/aV8h8mhAfAOHqm6W+6Pujtpcm/u6d5tgiG9\n4Hh7uwd4RsXDEn8V7Zn/p0vh4klr+7iKNhu9rMEu02T5WmxZctgb6iWf3GUnSje5b3w6bDsVCpqE\n5sy33NCwukCA9WryiomBfnaVrzrG/H8397VM3ny/JnlX1TfxtewyjwRwhEaPPXP5lh1aj9aMq1nO\nCAHw+X/cdabRlmcEc3vaAhVdVfC2Ac2UaSaJIhg9IigB15g+/vNA9P0UE57A2W77H36mW3fup10h\nxLR5i3RgrDVEWNCXtkJBUJT92ohh92VVcbMMyW9msLsE29sEqIy4IAXNkrnJVILXORsTfCCyNtJg\nhBuQygdIBk75EaOnItJ3luUK1aq8xDJSzNApqEoDL5qrCrmMOY59ZhnOOqAzL0Cs3zYtbESE6jo+\n9/gni3p6H5KaNAjc4Us8mNZcpVHeMpbnCRqMEawvOCVb9rb9DyqKDceACQC7nIsQm7y1u9TqdhL8\n348TFGulSdMxPGICw3Ob6PDfO9p7ZcjpMtYHlKXDuOeObNWxxLqSFTFLQFT6DxDrJvcewmt2KLkK\nLgaP19Nw0Od8kQ+/Fo6xcdfvj6KdsaJSnJa9ayb6Sen4Kei3qT9/UDwgKhNTtalV5+AGmbSYwePh\nF+wvXeYHv3q/ahcuH3COEWt5Wrn9Rza3nvLk1g7NYB0DFdCFrprOMP0L+QKr8I+h7yxiwuu1ymX6\neg1yLyw2Ixo57XyD13li1KfrlUjcKQwJXsOxftnZajHZVIVfOZKiUhvZP2DfrgwPFS8P1IKCHtMl\nST9FR7+hD9oouz+nntJqm0dAEbcYAON6PrctnZWIAzICjyPkr0Al6xOCfwSmsvj76YU513m8xy13\nWpUrUkXcyAml8W3x2rQ58LgZyIxeTQjtocc+hOeRUsId4BpRPqS3eLz98gJ/9BWhyHUu2ytzBNHS\ngruoAI8HfLKd6Dco1aMOEAWZ+T8djYZdFarYT1SLenrfLf1JNhySJwW1DFnEyC5je3KvnlpMGdWQ\nVJ5Yjluo62cDiijB2S9vkvzLkA23D8pXC8xcKjXXQQW3DrHZdJkMDSMcVSOckAi0aDsAFYAM+Hu9\no2ymtLfGjdJWBCfvbWiMPTpAbnCYw0P/FTGWhZOe4dk3rHShCzNgennxwA2xV2sbglWb2psIORFT\nCtJ92dVCh/g09VmZ2Rfhy0ZRHJSSJs+HrEqXtxCw8jZ3n5CNQER+3wmyKxnBQaYmvgFnM08iyIqY\na6FUu1mTuld5MC093OHzeuVDQh3m7/Aq22VveOvYdTshv0uGjVU5pYPEg4/1kaieyJrLzwzHZXVH\nzwKlGX6JqG26H2JpLE1U7ZCSNUGIM+2R+k4Qcms7Ygg6wdgvLarx50Kkq7hRi8BgtpOliwqH7DOX\nU6fGE8BytkIodB6s5862n6VCg0PeQcNtU1ZbvzoPaJB4vGtUjftxTf1E7k3iw3FI+hhu53wP/o1m\nEmnQBIgAVm7qqtCgCfFs15MAjwz59ZzmNg+w+BF60In/NTa50s/3iVzcFBJexrTdhkV54fQpOVob\nSr9R0ZctTGDRTT9cllHL9Kd8IObAWmpdIZHqW0Bwn6zazvcK7WJ9WDxG0QF1HgLPxI/dxd5oWwOY\ne8wZtiVXRdBb+O0AzmXENnptFRr1bOx3RiDzdrNTwmATclVaIhj9CO307EhdZXYYunOVuAMRl+sg\nzg2eGI3cO7QTWi+CTbN9uAcOI2k0UMTJ4TZ7BzJUnL20WXzWgqb0G3poPE4bdehOdN8txTEHLTVq\n6wcMUpOqvxewVz1JR7nD7/yQt9iYrePtujjbZc4qscD+gnHxYw62pj+vUXy8V8UgpmjTyJ+uvFWM\nRKlzfWMfPRWoYHmMNnxvmC4cFrtNi7rRPZz2F2Dz+siZjj2c40NaUWvLO94IbLNr7ymR1bMbIwik\nBtRxth/+ABU+nWqr199qQya+rPHTS8Z+lEazpLDaU42+R+UyGvHW6t27NqE1whkdotm6e+FktXtt\n0tf/KKqCnwyisAAnivTSGlgdAGb8bq7RwcS6khH0cl2vTPDlY9e6q7WBo8Qc4Glq5qa2Fw8NWQu8\nbM3RGY163Xl7atcAV2E7gvPb5mTQ/3nlDjGW81q00ba1vDCmS+xWc/LcJLxJyrr9+uJ7kZeOH6dV\n/lQxPwXhrmXY9OkXyxMB2MQJZy9uaOfhBx8zlZcijqwMVeWfk8TtK+U+p7X2asKh6ln5uTRHUOJP\nw2APFznjPHJLBPuOzybJdYlNBcdxvfeBRxktT7aJwUKHofp5x9fL2hh3QdY5rWBb8KLxUi67dq2O\nN85GTtA3bxhJTWD33hkH6Wz2MBTqwWLZtjRSrrq8bHvZ93KGwaH4EEaUfrCuuCBCg3Yk42J8RXPa\nzu/gICdUb+CFtz2X7sT87wmYCnCx0gtOP4mfSKqHi35jfpan9Ab8gRxPlEJMVdPczgvisv7bVXp0\n32UD/72iUDzFJQ4/WgG9UxGILQUQz3e4fI7jPy7vf5HzJiWeyFGrMOJFJKdn8ls2nSpTBzuBHTDr\nWX0tkCJEPUKyjDwD1YNamcXuveQreg105S5PaWif4vIK+ML2FzOTtZsg2PjjNvJwKxIChL5PXLEg\noKcutIjNWz0M9O78/4yZSlvk6BgEnPl+qTKCrCfwnH49eREej6cWp2TM3PrAoTEGgbwxg8PBVEk5\njojIMTEQqTurrW6p7alr9qKUrm++q+2Z+T1AwKKRRh7X0aOqm7BzVMDpZpf83UEryK+IhvVZT7hF\nbLb+74TB8EgjcUyHbGucntekBJbmkCrVwKNiZBynrnUeO8/Ozzd6t5WDSX8BHTaKY/HgqTsfFeE4\nw/o/tGy1ZiP/RcCao5ILRH1PN4oAlaND7b88ci+XeSAKQdaSkJ7qODUK2fDTQ1T+vrdV3djZ6N7L\nicRYBrUAWzays+xgZN2p3r1y9qnGKHplJij20nrdljt8rxwW0NYggPBHa/nW3UdbmtTHzId68gIb\njAZZpYOyxRwAzhoEEu6GMTSHIco0EW0we67/YuLcCT46tPMhTLruOutxgLFmLsFDC3VP6ruAesvj\nsOXRkU334eQnTs/RJLFloadHiPmLgySZFAJaIdA+yHRpGmsvQO1wxWxK+pBmlr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fTLYuxk6gKXqOkWp69thCDuLEIkJy6WhH9cfNB0fYJVnzHNJ4u3Xm3kR7G35arn8nvg0Zzo20JG3\nuVALxt6AOA1I/KTURTQ+i291WOljDEbU/rDdABEZlQsuXqXNd8Brm/fuBif0fsI2FTzeThcinivk\nxC8wRCMHADAz/y5tKeGH8WmQ0tVEbmdovTFHrnoZDJ4a8n2cBqsdh+yLJB0L0uS3+uWcO/tWICUJ\nIUoZnec4dS0CEpsn5Q9hr38oIo+p29DoVmL4NABbK7fdmNSP2SrZBV+CGIKHD1+s0tCknUOkodPY\nRAMs9bpvtLTnjx3Efui8kTwNQ6A08C3z42uNjK9k8LSxcDR0e5YSZODRI21enDZaIM76B7kALJia\nJFPYq4prZS5++3FJeeLPdXOnOmgKgkdRLFYwyA7Zt8rMiiPDj73x8aqKi3cbV5nUjZ3jxrXqFv0x\nxCteAs5OueCjSQ7UTaEsa1e355OTbelIjIRJz2IjXDgw9lTZ1+a4sJRHN98kHzGyzTLVPlgax1V2\nMe8zgTjCFhMrlcvk4cbJw2zshjWYikYU90y2RFQzFrjyribQQvLSugwUu68k8vSzQMYh0EOGUhIV\np52fJyDpPjcGWRReCJSbOsEDwvX977R7hYiMIuCH6L+Gajfq586QoMGYa61KFk/sdo/93kU7FbX6\nzSfcck/6+gowM5zHURqbRhzGitb9FjCKFf2RxVGlQBcht6NXjBG28deikyfmQObvaVKquZQ3kXUX\nVyFTw4j5DC9H/xUigjju+yEShqOyDDniIybgcdl/DR5JZUiz6PmMw9S5sZFiO0vHyJVDKxWIlue0\ncsWsjtwP5T+dUQs9U/Kdd1zu8JrU7EtKQ44uPHixQtWPz9x462cyxyCTqWGlhXVy0QYgtmARaiR2\ngrsd2R+bpK1iZIiLhkCyoy2A5dDeM+Ei/pdOeTZs1imEVvD4IN/DSZlDIf4Xk+DwC8WJkQVS2XOB\ncbGMQRObjQnkLeY9oDnFembo3ywebTBjay4ZApgYo7ceK0oOdMIyXIoShsfzosaIVdI05yy4YUSg\n+n6MSguwOT8WB4IrIzDddmiBQXKpMb7QjVE0m4jXKG9fodttz6p1vHkIPU8WZHLmQStszfzyjfH9\nqw/bsHtHjUS4vHkkUIZCCM5ragag0dAvH0wmj1kxMmhHHiPOofaA3zvdGnoA5af2VoMn+y5ijtz7\nKDOtY4EHofjkm6oPfF8vBi5Lwd0y7plZuZ3jVuEkcONm/mYE9ClaNNEcG5wGUaoIK3/G7T0f8uDs\nlGbkSK5dgm1Vxng8pDZy/lBY3aaDm0fqW2BpncIpeAd+qyl6rM3ZqrJTOtMIEquUyT2mLWLFDLZ8\np/33CrlHLUZypYUnffBUd4+pEWK+XRJ7opX257mAh4n5MNw8mxpU7aSY0R8uK5MChSEmBuRi2T7x\nnLMrjaWG08M+6rSVXwubhTuAvWDpaW2r/V64CWxjTaA+SCCUD44vN7BsLb8kkcVFW0d4Cn5WbBH6\nDdnB1HlVxsU/xIULfbp8rIWSex93H1AUJxvJeVKhhGHyjDRZQIjzPIYW4HmCvSEJaCYK/dPLIbUu\nymYo4NhsahybSXi7hGTnEzrRBdEHVz76fwHFWs+9HxMIfrT8UulA9TePd7QVSJuWD7hlKLTYuyIS\n4DfcKuEAXUbCOnntUGTpz0o1n3JiBghzASkk7f0WB9n+P55/ukSXF5ox6yNOVTIwwDocNLkyJMnn\n51IaZI3kCGZH3zjIFKUG+m8Pwqk4X7RY7SoLqWzqa/Xl5Zsjam2s1RXqxk8osr/dJJk22IB1idBL\nmQazLiqLpTeduhDjbxvoO38hsJfgR8fMkzjhExjIUwIhNULpBrDlzJE6DmDaA9B672n6d1nRuAG9\n/ajTYnT0rRbhxpNXx60AwcgZmkOSwZlW0WmKYxcrNtedPetbxWcuu27D231OWP2DBJKyEW1r+XOY\nZOxuddiglXQNCGlUUUWZ7pyTjziojy0JSQZzdY+OfGZEUR4ZQE1dBOWkCJh83/AVt/6mAZgAM5ja\nuWGJVfk8v8pX3i/lBtJAOcRkgOWLhH5kR28VexUoBKXSJptPflVqFBjO3ZWXQ00QwPWGEcqyAFOr\nnVczqjA/EP8CCQGrLVGYPdxTALnOiOcMHUE5a0Ozra+2Orx6/dhQ4NKX85ztPnRSY9LgDc9HLxYP\nejVHz1XMbHK6PZJNKlunKfIMMrqN7NUbr15x04ZSDkVOM4akl4kpjeG93DjcYMtndS1686zy4HX5\nJIK/wHYoWepHmm1jgTdAL4qmuykJOJYaIAmLg1/F4cRBt6ePnL/WyJ/869LdA2RgKMPrc59wqAn/\noXBwCdYkFfZY4QinN2YWngcXhr0kyBFPdeMLMSJPPWOS6dqaFY69bvXZ6KvXDsKXKZn3S0ZwUQb8\n0wnc1mPdl970mUbcp2zQ1l/+W/Y8joYFOJSj+k+sdsGMGhUqVWREmhB5UcC8Xo/6OtUcPT/pdUA1\nvxS2fpzjTAE7lu5AMMjYQqEcxg4bDDv4FHGSKhpiNA+BoJvRmTH9AbgvcAZvJg/HsEy8SmwKmdXu\n/lHefqaggvCkRpdqyfF7ev8/H41tdecmNk2g424B12Itv5KoEejPvFDTcA7J0S7XY0A8PeVKG9lA\n9TsJ4nFMD2e6WWadOtADcPtphJ3m2QqGsebqoqFATwg1DdltBNlrQvru6pHdkiXfluYb0ajtgLkR\nDD6RzZUFgpE7i9vvf+h97vDsWS63oK3dy7QnhwWNdvLg3kOAqFBZrkagwX4njmQrNbsNrotp4NmN\n4b8F7FhqArIftiMGJ7NPzVmH3K+g5ULqv6FW4XwBmdUMd1hwrTexICEZyWbEUSnmPP0I3UAwlvMo\nYf5gtI49hut4CQ0QXB6rH6/CjIWpkQAbc5RCzakYAXBfHWjoVmOic9BmGDztGdga87rzVLx9qdG0\n2R98yUoCCNw5J0s28zILdyAv/ge9sYy5UYswB4eGAR/xF1LO4rp3DrlmR2iKPCq6c9cmSbrLNPFF\nxe6k25kr2WiD3Z9AeTMXKYnA9FzGrrHVvDOBjMo/l7BUlI/nmuIrm62L4glUvBLWZKnY7xuva/pG\nauu5wP0WvqYwLxzFQc+Q0wKcQ8F0GeT7zC0wql/a9OQsevIxJd1rMlfjncunxVd2M58WqbBk08QX\nLYowdl8lCQA7cruvOMgfrbIKbelY+mVM+HR+Snt961UWKYHOeSOpDQ2pIesDJz0PLP/TSWgZ3gY1\nSb8nPdI6b4odikECv8xMUOc7oS21yq/r5yD+k5mMg7n4oA6g2s9j76mAaoyLityWz4ggiCUiV06k\nlgQVlL30rWFtR3vn+hUoLsZJQwX1sXrAk6U3Fdd7ZJsNo9JCoQkAD/bhRnRzmROLueQb8m6XzWtY\n/KsnDvoyXrw/anQ7HU79/C8jYz046Plfly1gsvV9SlP1OjqrVGzv/071JJObA5DAWxl4UQg3uAt4\nKtBqVngttMbifhbQ+wJXq7ofopjH0a31QOnCZf/V1m6zCZIu2j0lwtaZkhd3n9Bto1ou+69PKgfG\n1AkM3BpuSqpPaRSM6SAoXXZ02tImw8DmUqjQpXUlpZlGTVga4G5ONmGb+Td/MIz9CxqM+7GMNzJP\nrm8DSWjTXQbrUWT1m93Ry9/HszpCxgLKfzq5hZskuWNcsN3Hfy/Onm6ApARHLRv67n750LrqbSK8\nKoNylCv7tqe7kcwolIx4S0yJsB4A4NBQNrAInaBATdhBABOvuBra+bclsovgLQwJBdzj4hEhwryI\nFJB08HLqaxkXfF3Lp5kTxylPEYy3GKsbtEDKRFYQqJy9bo3zL5VQBCmezcUrXvexS9fp7qjydqJA\ndoGKyRNHlZ8HVO6y07bUGk0Fjxm0ZiCviEWBF8E54YBBkgMeKgkTBQDMo+nP+/91dHp6+bH80T+Q\nAdZY1k7w87StexBvDPolk4zY7BlLZu659yCtPmbpAXoe4Qvqzij+nk3AvZbmmb8TdKV1dsDz2kUN\n5NjHM9tmWNx4rlXtBoxXSOkqd4kUzIsorPODMlu4kfKoGXAzbjmIjDuM82PFSvsvkIFZ+E+9bqNa\nyxwqEUdRsWso9/xkMFE3yQZY2n8pldgPrFFFavtz+3MmHuBf1KSF6bY/wafdVj+0jTqHDAfeulo2\n9IKWaDr+bmHievDdlZBcFQJuzs3A7u/B0ePOkUN1AYAYli8KZB2LqsipN2dZPi1vL0aVvrunVsAF\nWTkhTfjENgZF/mIWhz6gKydGAy5nue2wWhteBn4fG52Upg3yjWeHWZUYq4kNm4DsVNHpz4zjRYIa\nZb8L7pz2AZZMvejEAtz05cYh7KYoeIIAUE+RGamjPecVfuCgjxUPdTg9F8DCL2Ym75/nVY9ju8X1\nBRhnpFQYlYmdm5+HpaDmOPrhGm+oiW9D4GNzudOOQk5ANJrWVV98I16wNpmb0ig15SF+m9cpU4AQ\nuz1p316RiMlWtFHyDUifB3xTwalr4tv9Fko+Ie1D41aAFsCsXuXzEn+ohJmDPlPj293CsN9v00NV\nPWvsQ8t7XidzLGw607oSmO1cHG8em2hXGIIvQakaFMOmWEffqfbK6kBSCKQTJAKyTrA+8Loqu9C1\nRZuabgpCGB1XveaJw3WeHi11Rc3BOH+knD94a6W8cT9KtlAKI9k0W/nbMrEqnZys2EmHkImsQNQg\nKsnyfV6/AF7I/pJeMzZ0orqXwUqhVUwgf5JmU/x57RbQ60ha4rqRsUyoiGy+RjIpC89gHijogAnK\nxz2a2rfGNDS+PcuePP1Y4X2ocyNCotbiRmXZ8akXEDQsV5vAe2OoA4vppz9ILUk4CEZpmd9bvP9a\nbdGKWTtg0nDGeeooPLpHdQzDOf6evzaHq51FWjVzdANGRztG3R/d8NWMbyrKmi/ohcU4GpV60rYd\n853EgnJLIemeCFkKOuj14FqlKIpMHmxkrTz69lR1r5uc4i7S4YhJqCceeurKBMayUaNtJRNAUPja\nIru+/qrNL/YuY2pwFzbPmAygVEzapJpcczXrokm4EK8nrxoySMb5jStuMltKI0j/35OATeGh4cv3\n+JD/PPWJrlL/ZJ1k/AypiD583lT0MYElXx+iMBgdQ6XrL0Ge4591kRznydAw4rUh3JjNOWsL4+br\npdLjszvQnYJhK6f0jjWeYxu+yjq6+H3I9swngLXN9EOXyyboifRgi4tpuzwIDkABAG7Fu63M9I+6\nCMvKVgKa3/Te0zjddzKvu7lJ4ABV77XrOQxhZVdIvkxBcnYy0dQ6p4iIsTjV3C5Mby9mVuS3jXJs\nY7dUHZ4FTQsHyEUoyNbPlUc5qopXhmMApOI962lwe1m2WKRJuGEEtmXVhrl7JKpo8KA6h48ADXuS\nAchXndwTFngLANtEty+vDOkD1U+8K+amEOyf3+YlvuLI6OPvfrSPuyLoUxtXDi7sWjWCpa04ByeC\nkM3RPxWe/F+ktlf8ZSJOxxUd1rxQ7kmPf4T5bRKNDcGMJiErNEZxltE8uR5wO410wODAxRElRSyK\ngE0uuwNdhGZDV3Eq6mLQjlLHUz63Py9THH2oCAXTzY/LMH21Hpv8GogZP5fgjKeE4zG2uvn0sOwl\nX3T5av5FWw0wo2V3WxiJa1xc2vOqtGL2cgdrl/G9iJsldq6k5pkQvOrVcC6edYFIyZ29ODATb2Mh\nYMYeb8aZfSLvaQ0ArYGIbUWs78/Z7cNd7Z5iZ4TxpOEcD1PdUhUkuuIm+rK+DkLyUNjQB8tnIUjT\n70cph7vsFD85XX5xivS/qik1ftsROrJUMBzAclwJR0x+DJFmvSPO9qhK9uo8inNbVSF09V3oTYc8\neXt70Evi/qBWsN9cQMTLi10BujYn5vWewh0z/wn8/CksOV70otdKclVoZHNo9OeJkCEiNBrIrNJ9\nxRKkm0TV45R6zUl606GS3GmAW6ZAh6ZwzqwleD3+IP6xxxiZgQ3H2BMiTksCQpSwfFTobUY20ATT\niHBWJ1AcdWui7/7UFkV3tLPuBEVrya95aNWqHmmPTjWiuSJMuBg6fW9+h7cAW8le+Yfq5hW4GLzW\nlkhJgFq/VnQryhZfKIhD+rnDeqGAndCJEsPGV6xQQmhzt7ptxaasrBoFtcUXgUq7Qfcn7Ge7wovS\nceylN2BOThdkqU7ByGKelw+Jafm4kRRli7PfdC/dFPEEJIceGCNSDYRARkvGarRe4F/sGD76jjX7\nizhmm4pS99Oh2gllWG7+gggHIn8qRbFIXl9M8LAfAxDJSqAtCJpKIoueCM/OmnrrFynviLk6ILQ4\nForQHUeHVf+WPDxXJVc54WzJ6V9sUo1VowbxAk9GKIJ3MtbSdHlHL+0QYXw9GQ3FIm9ncFqs0Glj\nWU5WpoceGfGwvBFMVq7/8LvLQFBNfn3hAYjQL/YGYO2sOGZ+B0DgMU5z2xeUKObqTeE5tmF/pAid\n9ydEusctnDJgYEfquppe5TlHRuQBadpe/72acAlHGeZOhdVC1pep5B6UBmpLVRnyA3LSvgzZp91X\naY1yUtqRPgWZvhOVYCLz+wtnbiy0RtLWKLBXjWSl4lrVsBZAxIHqExneu9QVWGYykSYrUDvcNkla\nR7+hwr10sq1tr/SheBdg4Bl71K2qoTqjTYnZQQ3niqtjTX6ncNlYi/Su80r+FD8k+y7/X5yK+26z\nsa0ZNTGiWfCqnmM3lLGEmkIDpKtr/luyYO0rI34saEuNTnfcaCmLXWhifu1+CHLcPOA+lzp1P/LC\nJqZzl1gGcoOjGKgZTL7t1bDVIdNC3IU0vRa8x/aJqKtVw59C+B0kL38iD14CDYVU74U5d6XzgWxE\nnHQ2/juhIFWEs0sboJ1ujJXVkm2W8gunQq+yrbx24d9af46pMzrBlcx5QeTPRLOF2ncEAxoMf/4I\nIllJRYoZRic0WqSDXN2REYPwPzl6divkUyCsvR0V8AgZi7DYepk8h4U1uirFMmi2VeR/35m2TjmQ\ngOeuYbvx8PWUM61hwqC7BfnMoBsLOxrlDgEFGMgFqSXCDS2oP/HMIASgpCjDLruUuqz/l4c9pDV4\n9L0Gwd8/Rq/R8icL3i5M0rYdaZosPvV15yIeKLGe4mg6rCDFt1y2T+/QNo6FR+IKCzWRku6CNaFk\nyU/pA1dAkmZBRwN/oHbtkOjkmD4yT0arS41DTvWVdftOze70X1GB7cJtz6zAwcQP9Q2jLEomUpoC\nzRWSMENLFtdjiDhK3oIujwkaDuxQQelcD/S1114Ir0HaeZzUY8J65MEzLhPYiNtBjUlNlbZkUnlb\n4jrrb8GNy/qav7Aziwr/ayNr/we/H0Ln7csEN/ut6K7pa/9RualN2sio0klVc/r217UMVxA+mqqY\nEQL+ikcG19JFOn67V4nZa9eqQDc+tpgjt6uffcdS8lotZ3YvfLIaZhhHLc+RIdrSJZLQgytWVmGp\nPUJW/dBVa5bPEKU84Od5sjz72u/O0c7IBttZmi0AH1q/UGs7eCZlOvo4ra4tC3g9hZDrbtazGOzl\nTj4bgR1nxJtmqjJcZper1Zm1Oc1/LH/ZpLBnw3fCxTu+Tpd1GabqctrdJhP+l2ZUaOQ2+GiiY/tz\na33cBGI77soZUqy46Pfpz+okWNZPpGDzPO15tp3hV+kK6vAfPaN/urmb656hQRRw6hhixr1aFs67\nkUS2QQOdkRmE+aLUrvDIhZo7MuSFw9TddhvilzkIWA7Tkp1/R2aNP4fgAsbHsWrhXuYZjIj43V+k\ndyCNlIWG+EaW6f6x3klYIH1iIc2hAi/o5g5JlQlQA0Ue93xLWOMZ9MHxutMjJA0GDr1q/+d2IerH\n2OICsilH3gtfMJomsAs27Rss0K18QMC633vYJ7657Cs7gMncvjvhxADuIo7kRjNv00d/cukmkUbe\nBukEAAzgfRFTu4CdaMQf+dAZjw2ijQKZNrZw0ZSI86svAESloK58SgCNxtwSjZoLmECuv6C6saYP\nXcfSAJ/BcAkQf+JpiuVFTzaJSBTKdcfN4dp9x9xA8asUvP362sLCmQk2sAJQdWUqZQ64JLmEmQEF\njdFgJuefUOFK069x5D4E83huN6cEu8/9m8Y0loNAjixKtrTc4P2B0Ph4+lciXB76uZFkhxQp7zh4\nvQFfS7PAfMsjyoiOQFFZm1sYsssqVRLAZxgRp0ZPDHUcMxwVjGZMvPsUTH0eoABo+3LN691s1ItO\nWRpicqdB0STf8yo5aear0Gvx8cVw83FaLN8mat0DIqZe35jh9+DCctJQopjqFoMKwSQrfq1ngWXl\n9fYbJrHWOBonjiFw9Edj+xNqK0M1Hw+Zlw+ALUpMRR5iK3QFh8PY6DFYUDWyeG+avv725D4WVZew\nRYBKHhlZK7R4ezeAMmnmMSbkig/HjhjNA0Y/oR4V4gFYqGWtn3YVG17ZUW8dzbaEZlzSMui5Q+QE\nvqb49fSkpVr+Fb3ZEF0DzeJjcoufeciRkyP2ELGTzAHWo3IcQXdXGDfCnHExg4sOLP5I+0n7Eeg+\n0o5rY2ydJjYRSjjKgVKO7rii8p/oqBCkjWhSUY4mL9Ye95b72lufZe2EdKpI+PfGoFOjR8ArXiYe\ng1GSmmpAJ3aFzt3lQjZIOtJsK6XHnCybSUovfM5pr6wwpwZSY3VF8HnQlZCzsddscQ6N/s8g0xxL\nE5sjrNtf3Y88+b1rdUwxQoCvXWqX3F/U/r1rrFS9Hfua/KhoKoGcybgujO9Ii9NRKYcjozeb9D0h\nfDoRonn2P7KStvJRKjGTOpIrxaqXlGcB4A/P0SzYICWaKjJf+SUbvLzmpx8buppymfmFZIAT1UMN\nSQSp+/8SR26PNiQO5LaxNj4w8HnTkF+7H+7eD0T/57jCkvhMMLZo8jIk4vPXnqlpKnUdrspht2BH\njam8PntSGIpc3K8F8hzNj83B0QOrJ9Qp8K7fIPR6c2VX0OBLJJg27kWGQHF2DRguro8Ww59kRJqK\nZDRNPSfmYHO/6uNeNFdj7Hnc4LSkJ8lgKMymA5D0VfopOjmnjTtRquwZQ1ziCx+mSeH7bSCiW2Dk\nzT0rg8rL2j6taSv327PtKyAQuLiA1JAsa7I3+DcRo6k34zwmGY+54QxsHTTNLbiFJJ20P1Zjd1rK\n99CR+5k48p24wn3okCF1Fr968+11vMOIzankgsZ8JeHp5lzOw13qBnAH9o9asTi7WParXFiaQfxo\nov90cRFmg/PqgjBY2T2oflc/JgFJtD0IQJMlNLSiw0+yFreKARxaqDZfH+7Y3A9JKvisEIvpb27B\nWuCuWZCcMP/ZZLrJ8Fa6vyN+wtu6DvijaGO6Iie1fsHPsXzuwLQIPa/1GGdeUVGFjs8UP14HuUw9\ncVy8lCtlryqTmhHUTu9xCm/YxuKlR9/06LVz5Vm9PvreJ3ymwlWUAEmZ5zTF0fW2aFgmk1RcYfBB\naEog/Bhzr9ImlcfRihAF7lDC7oXm4gMNlyOlhuatRhIODaBjau1h9uN8rbJnuBC/uTU+TprM++wW\nmBGjvYnevy68sVsIj2pEGN4YuWz1Oj0IvIikBP1GI9IK8CSN022IHyY6OcWc5+uTTaV1fOvEbDat\numl/aeqW93haJlUcp2O2DHd/Vg5J+vhBXGL+j8iDPHh3eMfn9Cnc2og7vQK+nApkKLE3d3Gn17jo\nAj0kx7KUxV9gzmYUj9tbu89GZls5oygNLZlwTocMWM1Sx4uFOFbOkd7JahzR+xvFYCmcwlHOYv4j\nLlP5/o8hV4fKjt7RsG3QuAwRjpVMc9qk4obr6c5SEmgonISrQjGjUqn55AD7Ia66yspHD2tnzJvr\ndSS/Oh4Em6W6AruL5KG+3y5cpNbGkjJiVeIsUEJfHQbBJXrt+dCsZahNroTqp++oabvr0PEDaLxq\n5ebkvdy6Id9M7YsNyw6qMHX7EBuK81xbIRwuIpJxKU3Wnm3/UNR/fCQGb2GYsMhOybahalaj7lrz\n2Fzs03U+CRaU0NhCem29c+/Dm5etEx+RJ6yqw5bgCGr2CLZADRyN2cmNEOrUHxOkP7mn3RJt34XK\nw0XpYxW6lV+L64Q+58XlmVQqDFRPYHhAKw9MYti5DMBROSDyUSMrSn5eJ6a7SoP5dXpL7gn8yHaH\nedoCiyserNqv7EtzO9fsAbqZti11EUCGht0NdnSNvMEoKGclfYCi0+scJSvD+E8uxAa9FLzpfLXd\noyCtRHLBLGifiHrEiQCoAZKWWR7EnAbcJYCraflxYCuS49JoaSiJfbnvQtU3zNycxRCdfU5nqg1D\n2NMgh2WT0MN7DnURjWIcVLKIo8SpTqvL/gICnKj94Fs3oHISq23SUNzsn+AefE0qJNBQZMvTj/RF\ng4J9ZIwrG+qIk4Hzuyhd4o/QEtbLnCbgiPAo0sd485XAVWrNk7ZgY9HBPRv6PZ4HR4Nok6HTnq+z\n/vGhIDZDJQ51iKDInx/aLK3rTS8h9d3KG/hMCPGwuAeb/KRLaTZJIc/wxcvgv/iqmqCGIDltv6rB\nBr/2MF0wCnUiqnAMCXnvXWegoftVa5lot8K2VrHMkbKCOCrkBYDLpv4ADf/JooBOEkeZjp65Fu8C\nX7/I1W2K+n4+950S6TjhJftEwjKmSCbFr/7mYH0YfdCF3Dx2ULwBZLzG7bURMePSL0pHm2ga6ndO\nrwDCA9UuYTIwAVtItYtUl+QNpyiye8JgxStsUY7ZD2W7Nvd0VkZwO/Skj56wMnnJ3uThcC64HN6+\nYUQz5PZZtHTYB4NfdU5oPIPZS0gIa6hTwQfRIIj4S5S2nydZKTqQA6zy5OOYNiHNo7DyYAF7eEG3\nHq1PieCZpaaAAzzbls0dAdrNsUv0q7Rx/rDKTGQMd4Vyq/U3GprIioIJ4oU9FOfO+QHxdrp8C/Ih\nciN4HEsBkxAl/r7UtfWAbCuk7OXtvtUCQL//B+v2pX9eYW/RGhjDIOVkC7kjvLI+ceaCMmy1Xl8v\ngCu8m+FwdSMZ1VuTWTmbVYGguWqnjG6QvkQn4M6ICA/aVEhWIxUM0zuM+vRFc5P2Z42fWne7ZpDH\nULoC9262H6uS0vIJQ+AWUYAI1WQ3fKoDb/6VeLvYt34gzRKJbUtbZhPLz/cch3EJmtUrU5n6Zs6n\ngY1DoSkE0fJdczF/Bz7+LimM6bmKUXODl6op6+CYLo2SbWmAM8UF1LkwbM/pfdZJA5aWGK2nEsde\nEdIJnp7zqFtjLVaqy3JamqAPViYHgAeGT6ikl4SiXRZMCacUt8mxCzKylZpRce7UlTF9E0BEJv7l\nwuFlPSMyDY33BB5iQPnbxxFVM8TghybByk4S2m8VfZk+WIctie3pGwYlS5CNKL6cG4E9dxXjp77G\nOCbqCSWtYImbY5oXn9Z/5IcN5uaaYkRXvPqX4i6WJ44YQzWNCuC1gnI2sZaJ2pkQ/wfmNu5YgVpn\nU01H8e1FV/iGnu4eajE4GRrscrb1IWks9DT0x95+z1OCZ+giMyZ6k8H5uxl5zaxV5+l+E8Gx15Ae\nguktQW2njukH3byPnAMm8Zo6/1p55v+J2thG/PUiBFy3SrzvzwRd8tRFm06Na7qKjCkNb6PuKi0q\nBkYDfifM10J2KMGqz7en99lDcTv1ktNv3+HSo8m4kZQ4Hg/0f1DpYSJoIKTfsuf5V76trCo2KlfR\nag1CUYMY80uDeCJDlNL+qMai/+U+Itq/LdpAVcwKaa+Inuc/A1zIMqb82vdUNez/X+QEbvN6olpI\nEKzIy0wZRPlLWHYgrLXqLcBbVMPuPUi8RqvNBbItK6+41q3DwrLQVNGaGoKbfCQcv/mIEpthAttF\n5dzbEjhR5jEno9DZ/cCVihucXoN49nLNiEh3zup0fNvKntKsvJ2C9wjHDBXnNT6+XDsdKwoCxYCH\nkRo/zH0EaIibhXR9kyj1+k5k5vanBTHGySnBgzyqqwSQheNFNj/PzcRFNkSP4kemOTNRMUoMRghE\nVx/jGm0wwcW58Zn52YlzEG8sFZRppz8WxvM36XKrJQvG1LtZxuhNTfljHSCAau8QL2cGOz74iwvu\nus1TcJGvqFYbCpGh6R/PZqnxbvFBhisIr+5k41gn5J2SAQhcssjPQRs41H75E26FwomUiEtGccve\nPShY/wcn1EARrFs3PZDZTm42WufebYQMeqvmUNSNcexnNEIPWMnVJg77dPeY6uUEQlLjEu6omQcj\nspScM0JtkKPZqVS4KCdPO1OU3KpWA0XnzILUKtvdXwN7oUwBJASmFMy8mjfDekrlPtK3pyt1OxPa\nzr/7ZCoeMrr9ABZ42hzHv5gPk/Z/T3CnbPzaruObYwtXx9SWcuxUYemlh0BBmRw9r34EinLo0e2W\nZU9bcydl4+q1o/2KzIH1Ls0Xc+DydNcH6np8iY4envHsyeSFzivL7VardAW1GaRvjSqpyfBVWIzq\nRFhsLYNgpwhXQKeb2PfmUPGRGQUj5CwwwwaW37tCYGFn+2ZAf4begbOXVayD2BSkVg79WO1cRW8D\nt8ApNv1h46ZDkMy5YQqnk8d6q4jTPRb8YHPVb+vWWTCq3beLR6jTSaFHf+l3t7V6LcQ4is2voRvF\neMgcGz1rTWn6Oj3z8wxPogxrMgm9kzCIXijBNEicGomYpIJpMVeZTjt7QbQVTOghogtg6lPPMTA6\nRqJLIIvfzWkUnxzBCQ73WTYmH4hUrzRRWL35bMATI5AsgzxG5r4TH4vGVkoTQ92WSxQd2vVq1XBB\n4o+0rw5IWfHFgmGLYvIpDrkhlbA3n8Hzt/ZNWgy7+fR4kO1TwHar2d9ssHn+QeV95AiRXRaorYtq\n6X+9OAsu4gO03Z5quP55u4+qEnQ0/bjlQhPA3oZp/ufVuzvWndbAyn1kJoeRr0KeHtrjqVoxUB6P\nnU1CoI/LOwsVPBdMjW8Ld3j6y1S+BkKeM0HOT4qUmxW/f1lnzafAyuZHLLVdpTBBw/sgo8eS0POW\nTa/GDv//jQcIFAlz1Pg7Se449YZIAigBI8keDkjqADgGMHjXlTvtck0ihQvkIZzzC3rU8qBukvhR\nasIQwgEnJehFn1DKyiXR9B0S0QiW2uJx6xSCxVdbefqWssY1pms5dwO+6LQMykn3nlLizl/8SIvx\neR9sfh9DEbewK734tbp/b5Oq9/48IWwN9/2PiQ8+doW6jV2d7XhgThzn8RJO/aCoQwsc47g9Wl2k\nV88jNJaVsUs+y0f5X8IuQ/pRm90yBOaFtoZnNOAqWkqai1lmXzk9qMzFOAzRIGVG0J+7t3Hx+AKL\nVEfLlPNN1f1PuaI79isOGjP9vIHLh59maYDKdSWvfMfyP+kBbwuhksHJW03L/uz3GjaR5xk1HFCc\nA6szO1oE8PM/Uvqpw9/0HQN1LuzSArO+YyLZ9P9/J5Ckloq8sCPgAjyI1dc28+uAH/jbkIYabbK1\ncqZNxEl6oJ6c/nBgDu8LVxQvkvf28PwF1gS3ZBokXtkjJJunzOuWa7lcmPSIuISLy7zNA5WXRIhe\n/hPqXyTcR0acuKhMVn4sK2dMwZPmfi6X8H2u9fbxI7A7AuaOXpJmyI+bovmA4DWpfGHov3gNfR83\nbRp8iwzOU1Mhag3zUA9XReveuZyEDNkgXtCxIuC79WCZB1bJ7lrs+GjTOxuCgS8K/GsQzHcidKYy\nALkteb7Cm7kH9OVdClj4dxd4HRzjP7rxXIWCo9VthOvIufhX1L0aRhaqQXnTZVb35cDvLqLZz7J8\nfD6l2+rbDVGpd58bsTS9Rv7pitv40mOp8SV0Y4vpe3NWm+I4HxOyi0CIhyAA8uSPYkgO7AEOgJHl\nKGYotkZJVco4eHHoFeLNuMp2orkvQmTZIW6Jac6mXtLG9cdqlXs2srk3e2LxH0Aah1XBEiJ0M/mq\nuWLa9VtgP+qspVZJpXd0EuTRK4s5SlhALS59tu2m/Ja0vE8mcp6Gb+68xzuiUC/KfdHRwnMCzJO+\nh9CnXrDDHzC093GPhpdosl3pt4W/eI8l4XKICnl7YNmK9olj03Z9Qw/3UOMYhh+MbIP8vIHoZqKs\nIefYkFLw0oYx+pYlJbVXimVLp9y5MGkiKtQPO8Tvym8Y7U+H0eQTM/WB254Jz1wmxL18utqcDdik\nwQj3FWH3CKxJtZ6EA3ikMgYrHgAXwDV5ECVHerI0v/fx4EwBkXazX16lRzfQPtcgdu9dkxduXW34\nMZxv4V7DHT83bQSECGI3b+i+r7ukhvczdncOfhotZ/4/6GyLzdNDu8jONlvyP0AeQlsX3v0W1ypP\nYGmpO7yMecL8VGcEeN6ZEeB//b16i4bV7Bf9ThfiW1wWkej4abAmFMOJlWie1WOqr9VUdDHj8BjF\nGbx4S+52y9UGanXRv84BDPw0bDJvuBbGw2E0/BcGJrhAsu91ucU1vxsFd/Xlo1XlbuOX6/W0FPHD\nPQakZYiHzFoLeoK8DxNjzO8VioPUdxbuIO/RePb79XQ9WqNmADbqsDdFOVZX0XlPGDEf8m0NSU0e\nB3lWYkkmsHyBuYVxV6XRVpf/RvmB8SgFDZz/jYuRd8/ashUEF+d/jyXawmgR+w0jc32PTMuGi43b\nhye+PEy6g4xrazqP0hE/mkC2IUaFyvN7eIE2sbGAXEjdjyUbtF/dgc2ZawZKt6K34VjxGX7WU9KJ\nR7yUxFdeGe0awUgtYo8uCh0C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WFes5Hczerdk4fPMOizrqGdEbUCzo5tEJng8EWCFDCPu\nSk6lrZR5Nb87PBfCunP7vwMIazcA3ncSZQqlc59jUcvI2dhkd7ZA3bMUmncxVrU3t+g5C5ApdCFm\nVXNWPNPN+Tw4C0e5jWtCU7dWSBvKb+PIhzWKehSi1TkyuJZVU0/kAZ4j8zgB0XO9CyI6xvVb8s2U\nQTJhVv9M7XjVYdICGEUIw0AGU+kXJiWAGtOh4LultMej2EtgLlRzaAPjvAVcP2/0x01OMgAlFjtG\nw0ReTUdHpoDgBby/ms1HL/FtYlndZzSwYSRsIoCeWXCj6YTQYprF5zUOzoj9vSwY7D6HWG4mYchw\nfD0pauEUqRJnFmXDwzmjg6llbRi+hWcFr5EmU+U1ETb5nNItsl2h0TRGUOK1kVBdZiBKwS3HxTzx\nY8hqMIkps3RYgEpXXYeU+E0g2fLkCw2XCcINAPR4uZoAD9SXzx2yvq2dLmRrP4FFsGdOBZVSPOZi\nJ9Sq8AutqRvOPFjM7Px9DhEc9M4Dfp0tlBn1gx6XGef9lkoTMBVxXgMHZdwol7lMY0IVy7TMKZV/\nGqOfET+uZnnc28nsrAOeXHJuS4tVID8n6YxQSaB3bg59dzAlmxOR2cfYqeh5rddMX23cx52Vvk1K\nwhfEZuR0ReyXp1DukBPGg4MtHzQC5v8kPgdiH+xWOaZ9fTOVCZEC+cq8Zd6WCahum3nbzWF+TxKS\nFOsgkkFf7kRBgkyLQeiFb34YJcisewsblyGeU6Tsm8NS+kkthyZRpBjI3OrV00ygs3KbTAhqmqoY\nQescj84bU81c+NrUXE5/5yIpj/Gpalu91w6gClXxZAaHD0qJmihSz1SFosF4KU5JbIODFZI18joJ\nHCs1t9zPL/KJm5J46fYXOhs82/yyWHY9dwMP5l61SDZlF7DHBRZsuL9JPqGtytmJlJlYyM+0PG35\n8S8DtleGAt/QYBjCj7fpW5GCcozUmPW35JMvaMkzH47dDN7f9bpyQhBihvGeQTQGmJomyLl0+l6o\nj9f7JqGAFTEJ9vVTT7PLYkilLuVFM/s4dcnvdOdNDChnv6JzpKqyDbFVf4Kfa4BvQIXsWpMNv8U1\nnAr5XCBCJXWOJJIyvTUBLaTjVUu5JOzi9P0dTKyahNv5bs2NTTptIH5IJG9EaCVIyYUP3u+DXnnY\nyULCxoNnPTAOlgMHWlR3MajG0AnS0fzT0S4eTQAxXAkcHafe0dhJ14pAqTFL/oqJdB9S6cX70bv/\n8OkfSAzMFb84SDJoNNin9gMuE43sLCZKipV4bIWfK5buZn/zzMIajA5LdBf8IZELb284dKpPOCcc\n17nAtC6gqUegXUgws5muaxYetUxQIEDh3eH/p9RTrx91zr9sAFxG393AEzfq1VC+NicHlUaE5A19\nmxP/Xq57LMKDMrXYAyfFmpyqv5Kai6O4bvHgjs6i9xPalPwckVDRYooFHMBR5Y4/ga6gyl0GoPyh\n6cc969sdenWAxCG2EKUyboQ8vFf4CKJV3G3AEGrGbY7HS7Ersx7FclHGIC3A1qHjV85dYruuZy7X\nJx4/1p+8s3iQL0BTGDAB7qs5faN+DYlPvyqvz5D1VwjQSfOuDq4kfXOtrLNI9soAxGZYxogbJeQ9\nlef4/JN+bufc3V9DfoFjep7CU+VXbppDXSQ1V+WLQmLzvvB0xts/rx/rGRG3vPya9+Nj36MUCxqJ\n+HhtacJULlpAbRydpO0ji1qR0F7+CvK+ZntP6V1QLRqaqi83njhJzM65Q10CCWs7CqB828u3X7N4\nPe+OORc00K1oaoQPCZ+c6yXwrvDG3Rbpsm4P7772goV8JhpcwpYhdwpC+4x++ohzkwJfKs8dZtKl\nrGh+kGXA0eeDC1E19AdYZAzEhH+0+embZ52tFf+LSOv8DrdORocz0FNztyLONj/aSljjc+KPlH8O\nD1I8b/Me+6ZC1yYbZnnV2YTSKyjhTagkjwlOmy9I8DoSidCXwXyvQcm4wdviE+QJMe50v/Bx6+Ys\nX2cHpexPFw3qknkNIRM86yZaUUPYs4iq1UbTwxyhG7IgDixjCFYWGO5scwIjD7fjAxN4nSgU8j3w\nQsupNAZQM7ftMJMfNvQbHdNbPxIaRhvAQSxCRa2yVjGeXAFROgQ0bhV8aDiD7KhaF83UoXoMZFOE\nfhkKYQMmp1maKWeGo2AygEN9FcsG0ydBvk4RdMT4yU0HcrGZPkjjLCXuujD8RPPK2zjevCt5ZB3L\nntvMem8DNjkDuNDRlDNJym1hu3/xd//fa3pg8Xwi6un8G2LxLoJrW2Zy54xvZkPe1nKREbKqEkK0\nhGgYidwWWxvxFdW/BzAFcMKaEcFpS3DnjhmVzFoW7+adQzT/mP2qOhWy0nDvR0Ke5aOMEOR73OYn\nTIuQdT33ejfd554DvxfRfoJJ0SbRB0Z6T8jmlcx1aSOVHfokkBGL8ZT7VR/8Pw7r6FhzAKsZko9+\nA+1IQFI5JhAq570Wav5KccTCP97NM42GMy40OzdBefK3+T6O7vf0NygDqxU0O7rvnyPm2/SfcN9Q\n13nZtnsqn17QWzWbOygBxs8VBBRQFqdfNmvOC/onn0Ggc0darVjMzG9TpPFONEKd2nc+h04ssGDA\nDQnvO796g60L4ao3XZOY6Obet6i4bXkKr/sVH8dgU3MMG+ZS3PMVu3CpyH58K3VTWgLnp3WD6Mby\nC7aFyabXQTriZr6RrtN+iXom60i0S3gNCkWPux1hPqOCmKRPbi0E36fvod/cAVxxu7DXrVi5TBD+\nqEggSP1sgPQ+4Xn6bM3tbPVRB3eLY7pzIKX78ibsvW3M0cEvfOtrysi1PBqONuPwgFwtHLE9wCGb\nU8RGLss85kl7LBGZsdjflSO5xWUrdUFBBjzvEyWUPCdD5/+3hPE4tNQ1xY6dIIkuEg9HEj3KLr34\nl631I/EjZipbJSRE+uTNtoQ9LK6qnAOAKw0ZNBKjoSUtZfKVzhVRuYSfkvRwZhomIZdCGQ7UsKVd\nKaWAJ8/cbneSWRR62q5fAdNex5+jjvQNS7FurfTP7TIdrOi1ivotHysCMXMOwE8B2vJk2yYoHfG5\nhx7244mj3RIm73ZP0FKF0PjUwfEWP3onENbndVzaqufxHkw2rftZC7nNkIgEfcv82pUM9vhx4X05\nk4f2aMUBGoCVbDCWPHijoKOquDvxdaz2SZqwguaq+b/ufClfSS4VC/IUzxYJZM8jb6L9uqUcuOmZ\nrwT/wy7B4tGDnTlLtLq0cw03qwQhB4+QMEMgfTGc5dHFjDVwseRfLi61VFmBAz+pNkCPvbQ9n2zY\naqscT8R8Ulkwub3fxwFeGDPn+zZ9NiC4nKYkTBLuPfulU462IK1WIIn5xypBZ6RRGxJZ5JC4vZLz\nW6ctbLdQNl2D7A16eCdnoQrUUFWnHGUnDzjfLk9tmPsiO9Td4AHF2J7zN01U6CXEiOxsLEYkgoag\nE6cis/SntaeNuvHk68uAd8yN1dbHddSyCgbwiMoii0/Cu1/pItmjnOevoY7TLzeQFho+GJoalpY9\nhQGfazMCLiY2Of4YJMquqF+yt1wNu1uXqxc78kSgXC6UnvKQgYkcuMMl4CNbDOPyiChOFl+gb9Jj\nO/5MfXXLkb9V0iRJECrQVXhXLzvvDclmd8r1rnyKt3/2ia+fKn3j6Ia+MxyOjHMfZYPgWk1nTBHF\nHa5GApLac4Zfh1ByhOSqvlBXDgI/KigdwEUadJARecc/FMghxML7o/3o1xQIFEcjygOLiK37Qvlw\nmqKElkH2jHAc9kUZitnakCGpa+x/ej1/tC+295FEQ0KEVE0+b1x9UgANIzG92ZqEP9JiYGEdd9GU\n7UdBI4XDj9RDR71mWB3dSxexYiFfTfxGrjUFlEjJJvMeFnD151/haL11wCJ0qzIEYqSbAsA4NDqs\nVuWbKbYLznwjRMm7eGkioICigdUScfUrOgPFTqX4bYVKC9SgDhdIxd1tr8c/7kUvd1uKacnyAIrp\nfs2qk5ioZGJGeLs28igNE4hZS8TW061okO6bG7KZwM2p485PsHJCoq8xf/UZaiRcrjTKThvPw4ft\nWZuQes4Vl80bBGeFW30x5j2nScLhr/eZBRshrftXlGsWeZcjaHbWb0RmtUgNPSRUTYNkqK6c8As2\nzaLCAwiVSGdYWnI4FpjXD8wFwmX2OMtuJVvOiho/iBdkfI8uRQ+kmBa1+kz8l3mjqUV4uL+gsiNZ\nTjadEnsBcMkRfnyN9C//G6xPANd0v86cRETVO8AwNNqt+Mi449XcZZOQlZNaVvUVnCYtGHCp6jFe\n+EMViqZ28qCyrLoqMNMi4xd3UaBGe/JY7oEMAkcKDOVvX2J1cXfLedxxTDSYxScI0TPCwZxdI6p3\nFNrS/sm15yGx6LhHiuzyqgds3uzEcnisMIB8bXseggqFItmFDzE1gnRLlN/W65ThRcrB/7TBZ509\nGLLAs3FNqlbenT1F1QvdDf+724QYQ7b1rStGxOi1QXFmrXicpMsl2YEkpDzoEANIEOr3+cPfHBgb\nMLgUhud3BsVGk6sssLxBVa8piVWQyEe5hluXYNqrOSk8qO0Y3aA3jfLrLorLtrqI2L5OG85yfmxo\nX5UiVnR7Xv42mVd6NmmIcS3vuaLTsUk1iCARx63Ge/zRi59otD1XNVhBrNUIGvNmMxaxjxNx0hMm\nQkZAXVI0dUrReUD7GXXkUHnw0K54YLj6S2b4heU/DJ9Qetglccqza7y/CtGxCHtou3vPCnGYZJjv\nYQszDADpRw5IUkAjGTGJPNpsJjM3mMeDSh6urgZKBuxbTq2eU20H7JSc/dzCmCXCCS0DDOldS0Ym\nnWM197Kq1zBhjuYehAQZ3OlF0C3nTBUhV9riCneDHtFpmZVkMM1xJfaeIp2gQUn43b0qc/wGM/Of\nw+tE8CzCWq/vjfkJ0+1bNptFZ+7TvHiRErGF+kjjtT24rPP9EmGA9s8MPRj/HUr8vxLnn+/j34ik\nV+9mx+xb/7oHYe78BoUvCIDPD3JukN2ro0ilw7E0aO/FivH+PkkhoOSiyD/Sf/KSait85pIOjN5f\n4MHseY1SrMNtFAjE8JyMZDDQ70Kg7you5Az9TIDftCQLGoJu+oAN3Jn6WWhzvNSm6EEy/5vZeKzg\n3V08WzUoeLhjdTPPerPv/duwMEVXMBSMyTJBgDgN/9fObKnbpD4mdnlSqGOOhKivQXS1meoTfrTA\nc9S9QkzpWOGSTigxiRzXRPVHopt102vRk46QOPJbCY+R2dnElbgbfHoRl2Q24abS1qoo2rohAuXO\nJUPXA+v2UTkZ/EqMtbY36D/DGjqQl6ZhJVrVV/NRtLRzTC1Ew9bjX+vC4vC7SWa0h43izbSR0Gcr\nNhE/lzp7kONLJOBD8GF8YtUrMj+Z6H0mTc2+o/wxHbdQmMXeQjH25pJxj6O/v1RL7oYrLVbXpmza\nkSAQY0FSHof8tQX5W8XwBDwS8+UqzE/EYvsa49k4JW+gWy7/bRVZj/fnGGSCaHPzHEp1OizQtrUt\nuN8BRPFvGBP+26tIAT3btEFU9bruf3O+89SOqQfCAWYCCTZEeWDe4kwpcRDrFJ0qcfmlZO0f+/vZ\nj6iGJm+Ikh9bMO8YhKgzowbSC8hvVszcmscP8SAgWA6w6GcBg3ErAJVjj44QpX3AVa37cs6SZDKp\n7DkeRsPyESWl89jJl9pwNX8qWmbYGa8Fs897lHkfEeGbCtqB5rV8oGWLmkyq223cUyk+766b8tlO\n0806cA12aXlRmlqhQzhbfy0h7BNCu34IsKjPoA8/vUkvdqK+n1gWA/CKFhRrudbb/bX/FbKivVA6\nB9SIM+wItQZgxzY9jcpCAyU/PSno9xGF94sX6ci5Kz1rjXoX8gM+GyeRDY3r/Z59kVq0yap7b9pk\n5sYn6Qi6DwRDL5+0RcE1M4Bh2SblJI11WyKt8roouORYqQ9ja2W19ukz7HRTrcN0MoXddTQ6bToC\nF9ktUWa5PCZGNUD82sKydxfAmAiVgFCr359r4Nqo5SeiU6FsEAEUdVcXvLmZXWKIujwJEAIvBzEv\nDwar1ZM7SAme/nr1MPITPBTeafDQ9j0xMmUVzIUFfhlLcP2OZLJx8hjUsN37PLVSUJIp7q9h/cDK\nlQmYXiIBTYw1/T7OVfsOJz86H6tnJIorzUxw7aOVhZSsTqut4iswQBSnp9xbWgy+LA4BZp6F+F4y\njlxtr/VWqujRQaWqeER6rPI7/rcRgH1hvvvp7eq2WBX6M/KVVr6onba1uvwbCU1+hhwV1Yzj4FxR\nqc4ht5o/ujxL9oZLDS3Ei5ZUlZMtlct60P3bUhKtJPojocsMnD45wubShthEKWB+MyQK/OGBRDwd\nUWYrDEYCJCc6KJC9m9wc6Cu/sFX95Xqk/2hHx3VtxIz9n2hG8yRU4Xc/y4CyzLtu+etqT6QKY7Hs\n2uSs1rcRbJUCmXD5ox7pIfy+PKsqid93gCwL2ton9x6Af4/biHhSAHs+ig7YiDu8RT8LPzS9lZwP\nZqdIpN8QYYcie8GySyYyphbFNL8bbNASz79u8BjstpHMKW1sQI0diXjRnZciaqVVtinzTmeBzO6E\nd+KH26g500b/SeTnrFS6Fs/aqGFxHP2nmvLCqH87mFcMx+yb7i17lNzuZVn4qvLt4PLKa7UpNSzo\nv3Fna1fnKMilm/Nvug9lbgY6k+LFnXXwfyMbDQMfIEUakF3TNxsjmL6ojJJ+dZJSIPl3cwIGCYXD\njUzoztgeqXhC0v6re5nXZExQOzpUK33adTcbjcGDzmIsMNFhG6DCT1139tYSoHdlrScjG/fVhqAY\ni+pxNEXItP0b/e8S41X5IvaJhnRhPZTuHbd7hjsMCYnzcELlT3/sE9FxWnHrQmGPTe8rqXkXbUoI\nbLpY1WxwVij4Rwvx2MlSM1mOzlh/BMB1YM4ZJnH8qIQLyoNR9GmS29CY2mToN0ryQ0ROglvatCzU\nqeSA1EQKqqGxVTQ/ZvjWZAaRMoO8HUtXwKSjVmFpopRP0/6ByUHkFc4llYVhcR8+qliMp1QC+mww\n3ZN35MC9IY2ftQ9uSAJuW9p0++s7Pw5jDFCuRG43a7gyG0XIDvK8r3PQ1ujY57BhhybegFwcKlUz\nIC9+2xnq5+vaz8UILQRWhGr5V8vjau+WtHrqF+kkLP6FVqjicebPDrInlottFvg7ERYqRIF0jadN\nXXiQ1zZqre1OdfYJ948+cYJL2rTrVz05K4rTLv6U8Kuytq2vc90SEa4IQqLwMUngwJ2w4xhsvLuR\nFt1MO8YrDzpipj9sUXKcdMojNM0uOfcnqRO/UZ7YXRbeOALynpw1wGPppXbSGO+/KJ4S2wZ5AkyT\n9QD/+onKN/AilKaTtx+oaUdCD/kuoGjwJ4YzTxGIN90ZuYJRmn9QLq1oQwyxu1WFpfYWLkc9E4vo\nlemgRXO7TJOAYuvBCO8NKIUeamP5WlwSmQ41LSOKFHwXPW5536UPzjiZIfluwBDXXfH/NXtBJx9E\nxOREiR8vjweReRdaLj8TXE0G7hN1MsfQvKcbj9t11gDSC8D92aoyeOsYxaSBo6x3IEP6oTddM4KL\n50Lg4U7FXXVbtAuxSDBJJ0z9zk9bQVFDUqISin0Mo7iyLU2Ko+RHJYDeTiAIuJwd4P1Acmlj9SgZ\nLSyRA2BopDWsmBJaHFvAAW0yz6wbLQJjHuxvJhwEJdDHViI/1jcAVb4ke2uXDHnS92MTIL6VHGpv\ni2E3ADhwho/X3fsrRjoObk8kiqgZ9FjahYnOz+O6gCzpMy8vd+/gwRVYZ+o8s2XLIkg7OfONvojy\nAYNrpqGaxGaUx2QLOH5d8RUTFtu58y4ASIi7ouI3w27i4gfG+ws1G9AvPQsymx4g/3/TLq2bw8Oa\nrQ0h/SJWVXDcJ4cR7z6jZiCqwOOvnhM2kmQkF4y7ghYV/vx7WCWXojzI7UoDVe6KOCZiS//Asl6i\nBgA9hvAIiRHDOUHt7nyb/pB2nAm1Ehb6q9Crmb551Mrzaj2j5XRT1i3XWpoYjHG83T1Wj5mt+JFJ\nzPld7OMBFvsQJgwWpXg3ZIvsJqq9MiNGzQe5CFcXw/RwSDMGpCoRuIn2CdHPm+r/wjyYxW0GatAw\nLj8qTBe8lgPjD4GoY7XIhY7P9Hqq3p1pvdzJEV2OXy1gekPR8+horjEZf76ebbmJSbfn3ABq+Zw6\nYDYKVsdtB0uxmxKpCqQSy3EFuEt40DMO28T2sEyOwQWQs+DqmwYr7hXAkzojWmebSbEZfTknaUp1\nNHB+WDxvB/rno0BZLVSEFUBxXypBwt/MfGzmvdFf007kq4+pc/8GF0y5ePPXVLNXSoMJJAVfY6Kl\noaL9MXfLpGr8zCJ3V2K48uPSkSnRGYIO+I/idzOkPNtyd78RyvOCT4yvsmr5wfBKWGvkdiuaFob1\n5zYoR9cQwuFlslIBqbWfgCwfTNkAp7a42w/LVwDe5Ft4W4vNUISc0vDZsrRaBqrmyuDdNbvczCKp\ntSNZRPHEdjPxb+FZhppbM8qlM3CUuVLbzIYiNiDDVnONf8ckDHZ3reDW9YgsQP+ZxF2+nTqHjzgz\n8gbIH3NxHnVKkm3fFAEGTFyVhjk875GZr3XcB6LHsaYScumQhF/5XOecatwd/gc9R/sOykr6nj/a\nADX94gCw+nepaTVJwZu/yLknOBvcyxiow4FXiq+VDP1H7STzt8JsFofnatFJCYnU5d01img6TfAD\nC+09p+NZc720a8eyhdS2pdnEk2iAH7ny8nigCJUDBJVIL+xegrtcOvG4OqgVfnMvXsSmuV2DRkvy\ncJR3iQVeMSvFjJobHfERzlaoaA88+vAQtsTgp1Veroy+DanSYHnh5FqaWU+ImFRCDR0yIsOjbL7s\nQYW4dtvGW0cKpygksLa+Un6UfBdVBfA07XVXB75z1qiNuXGQv03BzKzP3k5ExwBkLLmeDtOmsDEG\naroER8UUIS9CtbARPMMuh3vBjMsP1ATheJC1Hy1eXSuB7btjxsFrO7Cn0BwxLFrM5k1NzEw1mzXz\n+JtTXLplVo7qX3tr9AaLdqRPYjgJxdaVIRaUKbYiFEvu4sBbNZsHLjDAYMI5gyp/C7nEe/dwLFcR\nTvHhXK5FpnKJC2HSzgQDJDOkWwTDWpJFkhfO4/+7t0Yw7ZXYzIufgSPNulf0SWyQ+1uHEqDnjAwS\nLIZbWQcliyCPVtToI3NUNmOBmogDYWP9VcTEt3bdwKYU4ICqFAYWC6Vt6T3e92bJm2FdAd0eJXa2\nJ4xz396gXow9sl5OkMj+lOGl0BPY58sL22r46GW/YHt1FV77WIdAARxhgWKZO9FRDsVYJBKF4XEs\nAILVNsjpuyNu9fymn09tb2SrmUa3DSzSc0jOm0fMpa8rQ4E+YSEYdEKv/7XkJFGdJIrEThdxp2wt\nOAIsw7XnWWHU9aEYAErBCXlJF2IXD1EjrmdxWlBKbGEILVdTsEOMlBC/FnqYZLf+zxjZ8XhMQU35\nHiGAQKAEoCJ46BC18C77hCn5a6bjYio6JlX8jvBXstzXFZwI0FH1sW4SUCJ94iCf8Q4lk98nlPHz\n27njqmnxfWdFd6xd64fGgV1EEC0FIdSVjujEIpGADTj2zvVUqC52bf9q2TVizIGy3GrlcBP20ddp\nl4vgXSefdmwjPOTKwh2RHHTsN4FTBfksGQ9vmcXc5NL3zmW/SsmSk2bpsYnx3rAdiE8jVcHJLWtu\npcqqhGSaO4iX2E1nXnGBdWCmcPcVGjzn8DIqK+m2k8AMjXaPywZRnzeQYILatXi/aoG3RsJ6RQqf\nHF9K0gZLBR0Uk3q9qCAUSUaWbcPx/d9veH79+HC2OU8L7cDMHiQfLk2B+/TlcrnaM139chn3EPCs\n4IXwpveq8NWsqiICizkcpGIn9BsncM4q/PY97lLrCUJMmZpmcy5nRTHgx7KBaEmIMd2gbs6X6J31\nmevZ6K37hr330vHcffpN9QgXMytomqlq9q3QkVhgYLKNnRg0i8rqm4XXiNK1g2PG8y9TxuCn7GfS\nYMFStu5rZsWt/p/bP5fN3D5TQKVkLUSW0/Skx+ENVTxWL/Br3HdFGrAAOoSO2hN9wkyjc7vpMJL+\n5+2u59Bjgi7219bWUcug+oM2MBh7Y42xKzZ7kZIt46b2b5/JECcvU/z8sZwpwgEJgaUuoX9Nw671\nUQIDIrj9/U95tLhiFRh+Rl7oclZvpvz+bWEwWy4D+dMu8GECcTJNbvQVpxjBPSDsMw594s74l524\nDjQTA19zSh/kklRH6uzE2alfLquZsfcSLdBsBcCkiUVbkpiP9IH/frEdmZXQPSBA2plybfih92bj\nOmOjE3YvtnNbxLexlvmA/42NAwltSOqVm4QC5C95oUb1cxzRcDhO/QDVlI0fI3baP7sL1VQyoX7f\nVWINHdSKq5S1RIz5J1JxNSVYeYgNAdM7qFLW+c5kfP9vHpZZPeomOkwX+1FujAcVBnsjC550Eznz\nC5X856e6duPJKk5UZzJutn508EKRJsB3oG4LZ+HsEAH0aTQ4K2qLJdAWi+ZDxoZTiw+lyNOETjZl\nDeAY/X0n1N/FFJzMKJ9Y1L9jL4ikbvSSW6d3MToy3g8B9+03nb5AiU4hY+16JgVZos4NfEl5OOAa\nRLbgi75LnB/dLaH5S2IQsybcRoykSZ0Jy+0a5dXtz0OWJ7ZxXvvxIpRJUJhpOwYb0zhxWZG2mOyF\nF+dfGzlNfkuwDXrMG74vyqrYdtRTgFg1hQ9z/c1DKiRvPPiqGJ8s2xYF1D/fbgJPAPDHglg+nl79\nGS8W8w6baEaQ6w7ks+gzyjBf64ZT50/o4Pak4ycs5+/0f6lFctmeFMFCEd2S1vjmQ7J6o/sYdV23\nJIiclG2R41pj3Irg1gq2xVXeeWlri4GzjAJJ9BP6ykc9SGYPtkZ8tmnrwvFoZm3AwZvXxiDhFEZ9\nWOhbEs4XBvxRGJ7bffvUNndofuTnnzaM2NsaQNrsj7FBfXp6H+JptF4WnbOs9Y5jRaIey+2cMWhl\n4zYUU1VeMuphzebgNt1QmFBgCqCVmyp41WJpDoldjKpWFIe1LZzq20aRWpQis/upMoIctQJ8HMuj\n6elryzmgs1bWTk7hCGbQkzyYlbcBK34GT0DWUqcm4/6YvKrJBVdDUz2HSf2mNuV2+CcNBplZPG8J\niJ17vdN7QTY2j+kgC5o9wnaZVMS/xWLmDct+vYd209NB8YSi0aGcKcrLDiStCDD0Sb3rgq/RqqHT\n4auuDnVYkCm5Q2Lu8VCixrv1XkYpgBwpZHxEpR0qR8pQ9OqDaWkGSV/f5a5/hKw80e6sVPmPEvQs\nDBSiWAFhmDvRLqvZrzg4r5EFy9OyEMkgqAUpe1lKwUH2frD9/RFNUFEFTQx+r/B34xQLb/PzugDX\nnPuaXSvEmudbmSJcC8/svQleXXTLRJdX0FItr8GhzeO8o2p/3ad5aOvqQxGBcQYUuPCrbT3nWao9\nZvZcUyJMtb3XB1Gy9QXFWjLxitI8J+60ZN8BUIqafEk8itgiGElbiCoOS1oc84GzrHNeBg/YToRT\nN91++KANvvlXVfKABlYFiFqrool9VNV467Sa2aTxjoDmtt4x5EA9DDe40yh8z8lf/OFyfXyjQhrL\nlQYPP1y734lO0fEy6sJUdHTz6rYQ2W5f3HHe5LHpUi+s7mUfKjjHFLlLAJPftfJ0ciKb1U9UFqkB\nu3bVOpOvyrqYOC9UFk6L6kMf9SPlaG+kFITLlX1u+49NlJCwcapwkxHcy7alMkZ8VHgcL08Y9sVR\nPh/jbaQWwHFZ7XtA7xFF0lot6rSluHDReFveKwB221SjAODZ3K2bD/8jgcft/glh0pb2BENb40Ti\n31BHVUlExceSjVt+QIBkYbltfcWreE2Gj0O31ofxa4hVO5IJWmZ8if6IfG/SYe3I/pcp1sOeYihw\nc6e2JS4M2106oZrXetKEvJknKIeJmMS9RUjDo0ZSPZ+wvqBqiq5xeZ9gT+UOynpseicTa/6J3BST\noQ9w3uRVcha1gVOMDBHM4AfJn8tWpbgWVAB9z/lAI6C2j78nER5tv23nY66xv0c0klV25SnOpPAc\nM3Cp8P0gzWZHbhTQN0QKRrXCkbHuNIHD4/4cYQU/SmbeZDhZknU56vtLkwz2AqgCIBzNZeeWRUUo\nBXi/Kcxy6QWWN/G2TqF+m4IckhgzOjNJxgMAMKVcT6M7sZUL6d0somwMWFg5LBRB0lWR84epWivy\nzs+F+Of8RqWeoQYV29RgZSC9tLzE+CzckukUHVB+9NC5NViCckiNgbHh5Xc9N8C80iFaFkBDlQME\npTYniLeh1d09waFROb/Axyy59jxmyriNc9TgZgBy4WI5CawTktAIVj33WLuY2hq8DwxrXp6D+mIe\ndP9F/NxJYg9kKA+vzj5izJziC9ULMxg9NRXL7Am+CSzjXfEVOUdgbnHVBf/czI/+a9xWy9RVIG48\nyzARwHwWz/J+vQZZjMTJ5HIEKjtXl3xwVQAOaIDmDOMrx9WpcQtjOkYPydvpfDMiV6+71pRpUHsb\nZBJWjRXwwDNwrxmnwSqvqWxo8nY31N6YxVTlgcMiWMlEqAAcyDmgoTSPPVQymbmjZvTD3d4U4j8D\n3iW8OeZn/HoPs39R3YdnyLG0uwGwInfqiqoyfH+Awv5os4cpJb2oh/q2t5z1QFeHHrc2uMf+thvf\nvMLnttzrBkApa/MUHAeJ2M+i6METiG2htBR9udi9W0ptHp5VmHFW1yHYhdULYo5HpOY8ovhg3yjM\np/gW3b9+SHoNMHtpty9QMxCw67rdDKpZJKWHHUL9huUCQgjYj8wqyhUBPuXi37NbZC34gexpBpFh\nPYNG+ihfeZarFcyA9cWbhQPok+urCHKEWaXrZMUbBa1De1voGNa/IYFYBekyuzHLtCBlAU23RpBz\n/t6TY4XlcgKqZl4fmpMIrf1nyRv7awT2WN9JnSLYbgN0dTLIYlfXirYrflsJVKXniuHgWT3TnkDB\nl8zBF3qlovzPV+NXF+bZsf6Px+OlILUkGaqjHSVCeRQ6xDbpBXNuUWtUWrqU528ecEIeN602AczD\n1imKKm06utARJ6vY0pS0ECSanB1uQjmfx4c4EbOunvQIaN0MTYGOGZMD1qIMEEWpaYPCZZis8fk9\nAVmJimNNbc1TM+XdFECosMuuUWnRXFRvMjZf44yfO9nfAbOe7wezLFkXDEL2efxsvihShFAbykES\nLjoyFunFQZlyfMG61lK65Sst7dmxajf6Pxj6D8HcnZwDhSqCSJ1WQe7wE5sV3hPk+ENVwyoQiBKu\nHPJJyofRxG9Jj1SRsjM70Z5J+O5XxS/g7OhKI6278OExHW207AVFYnOzMxqkZ+Gfn2ZN16Q/ZJcY\nSz+ZYksn3wutH9rTdcQHx6WXVLatNFnIfG4NMTDxC76xYthqesJ6QfbSRoHJdTT+tqdGPAyTYIUA\nreSPAjpqkoeIW20toRdPd/qJMsFrzs/06Hk1+iGOhUA4FSvrbp/yjnrKeM0MjUgzi+deqlVh3RWW\nPs7T/YPE3GDhmTPtztql48D8FzD/Wb6gZueaOUvClXg6QnTO6IbChHayQLisxHesEDVB6wbfQhER\n6BEzgi/zMCC6nd4xvJqfkEmWeuml76FpMmmLTcytz22ew+vwTFyE80Wy40LhkPt+N7EBrXe3+N6u\n2+preSuO9ut96PwP/0f0Phlv0wYX6r/a6+BykwZ6CBwpEYknAcKvrVst5de/eZzi1YIXXBSTeX0Y\nbo3jBT9XCnM4muulqrO4cszXtlS2AB+Syh/zZHduc1BYCY9RliGVoCC35JTdxoonNThsfk2F87fR\nvdAEmkzflOzxG76pR9YFFMzLS+lVXpyaaHyz/UhPJUL2C4pgi+jhgMMgyGUPYX7MCwLPaZGRxq0O\nsZNbgH8+kWdwLXAAIjWRAC1T5xcc8p46BeMylQDsVrMckJyXQUvH22w34MxCSxo6mMN4ZPX+raCV\nkIX+UqDgd3cwX+eFgB/2CDUYUPXRzUYj7+ccM9DISGT6bagK2shmBWfi7qatx/wkSimPL2E/OoBC\nJrhpIqrLfneIRDNpF1HosB1FIUzQ8SPzz+FFOthQnOmLhlPvm6vCBoMcz0gjVg0diIQENTXyKu+L\nwKA2TEU5QQIS39XXH2oO+ytNu8FDu/yQrINQkOnwqd+25PQ0ZVO1CO4WOOwSgweXa52lh5hUYfwT\n6GDBzf8HikhojSas//CrAKCPNm0Wykpu1fbvXEfbeXZpckf5V+ooZhE58S0UxwfgHxkfbp79pYts\nI/jTZC/b+cYnpoGL2eb09w7Zt88BKNqdRqrFsuwegy/1BOxuPyx3THJcyIEFPla62gAyU1ImFJ7k\nSQthgvuXCWUUEZ/sgcgr3z5IkPAjaU4+VEBTLqI0QZ6c+rg6D+KpLFNdw9j5/lo8IYKn0PPUGDt+\nMpx7aQL6w8kjdEAWQasGIManoyueECgPQ4D8Aufgn+4EAuRDp4S9ptbjRQSGeWpPDHJ/pZG+dPde\n+lRL1D/QDMtwX85ziGQ9tptoff+LQE5Ltua8L7DHCr/pby0t5HFbw58kIuGHgc83uCcdbxIyYzcE\ncK55dIySYZGMj1g12Sqx8LrS1Ou9juW8j51f73gRtH99bHoBDiDNDzHOBXqh88h4d4Qe4PV3FkXF\nuJpZQjRLQpuVq/7tlbh8YA2Y4qZvQHTVUEoPY0ncWKpGNyMSkDbNyFpQWkibxtn6gcsTcH4Y+X4s\nX35JNE7jYDTotIVaJYl3i6jc+ZRjG86fDM0NaHhhninxYOkOH06bwag2ans5WGty2YbvWA6Qa9d7\nXcEBRhMcGZoxf6HopOmZyiYmUeWaz8ntGFbE+8p1XD0XAR218MU7E9I5P6rvrwLOwiC//cSUpdcc\n6Jv3nzrpghJwt7oAxomOTOsrrstEyJ5R85uIRonupTAzUaHdXQI0JcMLnggDbIgvzL1xiSgPuIZX\nTBTh7d5YRNBD6qyQ42WxV26Kh2EKDTk+m0ErC1T3+uDztL/Dd69zoOLCtnRIxvJS9N5InlmbWHet\nvO6wuI4Xj8c7Zvi9SBfaA4fDRnKZYiKUFLYWhfOAliRF28KUIDFYl+SbBwWGX9As/yjyWsX9hfU4\nXKOJYTEPs0zfxWMiDK5r1UFSL3T5twkTwkdgQYeUgBXDb8/9chbm9yPONqjPpL3wnZqgOORsugDv\n74LBwPuMzLsion1ziD0lmEU+CS/X6FIcBOM2MU4BLXSqYGiygHN3uAMbljBE4/EaFHYzBg0/PFEI\nKR6fosGvMpEPh1A+1gZou9iI1gCv4KbLkR65ihW7++ElL77W4Bx9Zt7wSyQ9y1Tfw9S75yKIyOkz\n9GzGSqR31D6SHUWNGp+//jL2qIzEDktJlODUN64R7DD0d+0ymxtU9fZn0E7HJX8VnpzHAQhP7mGP\nDS9EakBinOx9GgkxsAmDfugazWTKOsHr3dt5U7RyACp6oVwZgnazUh1yVISBWaJhqLMw7up1osUo\no7eS8mpDlSDbX/s3X4eXclSZNM0o0Gl1GjJxurvNiiFYkjax5z+BEZnPBaqSqRzTQYUcCXPpcW1I\nQLrbJ/KPTqRto/9GqhnGnE4P9L1ykfSMlOy8Krr/UTUKX3zkSMD80blIam6ahKnzxqp+9rrq4xPc\nTAg1YaU+LH0wXgK0bNBFu6ab8wJmifnGxGfp+ALB+W75Q2cAh7UZDRA82En04EsGOBc8MM67PZlK\ndBkJGxcgiq+4JYrdRwWdTM0i7QkVhEMdODc4I2VW9b/voO9Q1grnOJvypEv52HIjlMC0d3aAb7yU\noNBfpeKO8DIAZTt3KGiINypemyiS4K+vkTi0uVvX9ADDj/nub1q8aRd47gawGwhB/OHab7S+mRHJ\n+Oz/vg1Ruw+trzk0BoIT1IVixT1hXSDMrI+si2VvMDa1FDErkQsSpDgt9Dja+9+sk6NJ4VcY8fvb\nUPowD1LrFBlnSgj38TIenGyhtlPAGXm2kAvf6cJMDLrClRXlev73U8cP7+gRVodDmJHwkdrlsRNs\nBeKQ2Hwr7jDnq4ykVdjZDsBn2j9uS57cOGZZmDtdDEqlbURARH6RyWwpSFXpPQjLlzMRt4E1j7MB\nFoq/TkYRc2r6fzPxjoJU3IGDuxIFueDz5cZt8YiI195dmqF2dQVJ5ltpZYd/N66+HCZP9JJFk2mL\nEE4wXa72FS5xqrewnzVcNhTYHBlQG3VCVG3Vs+b/HFDw8b8wuhYV5q9wsD4N3HgG+jcxZVmAitMS\nyldTGt9SSmQTeRzx9eeclxkzg7VGLlFzvxscRYVrwshn+cKCbniJYe4Tpjl4Ju6Tqbokr7fTJE0y\nwuT+FnTjZlaVF0SUXHMOb3GBjwXiup4eNTL4fiAhfqsHqkDT1Z1THuAvtDKZ4ARpPvuEzSwuJmuW\n549ZhJEW/hd8LqXPNSOHOjgqIB8EvDcgWAPqTzvAJvcAjuiaCI4Qhm4552PNHdyCEQwWaL6IGz73\ni+fNq/8XxidTQeT4AcrbXQafPAGFW0TRJXPEGCZEvJgspI3HrX2DGwnu7T8pOyjKDOsjAmFQ83si\n5dablm6w2vra6DqhRRqaFLikZJku/am3rBzCjCVHu6uKaYfwdOaqFTKfNG+2FepgPECSM0SWUnaM\nnmrdy6pIFjUxKRtDPa2F1TDdOq/m+X92HG8DbD00lEKRRC4P0xjSir+GXjl4Htvn/3DyRVC6KX/j\nQBz3EqxL9KGfrajChz9sYnCBJaeIOlQgJr13prWT2EIs9vo/dQaCxeM+iiRhOm842KWo1LIlinx2\nRRwq9hotguY3cT1qNxCVXB9fveZwoTfTR/TDcQSW9vwcoGKoe+YXR6dJLFxqbkrMD6mgQnmzKeFj\ntR9rRWlSHIL3JaD4SXmvndLMru8J7Z4goeIKzxXifB2AyBbmhZJpkgab4jfAQpacJL28xRIM6vUU\nOrZS6cxj9e7E5QXTGWO7NcncZATybtitv8qY82c3hlH+JFI/HlhFS9ZKlNht6rFtAi2mENYk4O/d\n7qULphVZys/5XZMhK2g0OF5hHwZIsgmZvoIcF15cm44gKOW2A3sCMaa1jzM3lQwPMPZxf/VewgbV\nertWfixpA78EgaZFfLy0QT8+uHc/+QA9aNIQDBtEbJd1VETXngxDbhtdbZriE3/gdMibjpmtGcST\nLjUIDF3ohD27dbqexVH5qKMo+PVSHNIIx9cZL12lhwiYSY9yusdX8stuCchfIZBR3t9mCze7wWVP\nuJylGHqXSt5E9D7tMsspZ4JEl+1181KCQIfBq7bSm83ty5l/mOlxahkGzL4vyhunRukN/HmOoT2S\n1//8bT8k4u91JsdtZTdPFnfQ27cfkIcGQ5jOhUkbcm3iuHk+lwH5yxtbYXdXfmAZYU8BTtx9suJC\nrSD1b6MNl3zpmbFFH4twk6PR39GpmlcRr0YiViygWQUURAPh+Nv0Vl6nOdaINaKu95q6ALvUSDaQ\n9fcojm9yeKQ17hD294SIpulAOQS6x3s0vuimDtZaKJw2JSdTQihqE+a52ol8QxDfCwc7B4tjkqnJ\ncs6n6d1W1Af3gKyVQrClr2Qt8I6wfptMfVNXOXAC2UU1WnF5GEsO+daV/m+wKUHYoK0gbMutAocU\nfQyiZw84ImL10yD2RQi09+RIQppLSgA/zNZuHOVa1H+iz2hpcJg7qlLD5PF3W70lwU0XYDqOgH1d\nWzP3e2QUjkRPmspy1snLO0GHpJS46BjxzoqR/dX1pfJA740/KDvXHlBaXgeFEXCegQUG24N523sT\nYtjcOvAj46eVmnJrqK9xijWyjID3kwF9sIc7MNajbj2CSpjuCURJCc1ix6PZMlk7EeRIeEkNVUfd\nuepPRRfhYiidQzEPhlhotGREZ/cDXBi6o93IjpNWPfAQURK35++RiW7egozG04Krd4GQmwPkDATb\n0TjPlosE6880VZJIKGnAM93ltQi/sbAh1iUhEFOme7/y40quK5UXBwpIGPlplv4v3g81KnjYoRag\nFKR1VK0A4lvrYts5QluJpFpmhUIlu5UjVlav4TYinwk0VMxz4uBNIMRj/mOQ9Tlw4dca8v8FqLnC\nZzX6gh3D9BhXZVoNPH+woMY3iSapxn7OCQqly8DFwhAVLqy38k+mNw6y+QsDnEIYTZtfrBvVRE6C\nOlfBBwcB1WNxXugD/B22sxBBIJxyY7LTN1ny3hT7v9kCLKWr4pKbqYFrvtYKykmjtwF70nR2Hruj\npa8/LBLjlrtZZAasVSaMRfI12dMReicomQ514rl1G2homHaRgsuqsMMjvotsu8Ut3aIfP2oGRm5l\n3+cN6zh5J/gr5pPyPwKO69A97CvVCDTEaNo7vE6jmx8w8H1nkPGf+Jqu58zEqZPXqO86HipE9qev\n08+/lFGKwLZjc8lB0UsmUbxFzdqhYsoDu+9ZRUiADUX0e+g0rj+5PZs0+LILZywevVYahEH8BP3N\nKYsUgFC6a73sN44c2urbhJNhq2vYgMl4ADaWjFCwiPmsjMQoy/bcP6PybgRAmve1I8t8KxoIxeaA\ngAzgTYZAhXq9Sk4zqf2sTz2Wc/BWadVYO90B/ZYZu7Tu/6PTA36yTlZQi4e/Fbp9wMkKJA4cmmYy\nB+X9i3tqlQhmQgn68HrGxRJ/BjX0CWc89lUyciomfwGfHRQekDQnygRlnRq3ALaczsnT8NVm/xXe\nxSF434ehXPyddoTFe6q5shUg7yNc0p+xfhBivAFvRmZppQp5mNJc1zPPccr31TGcnRvO/9SFpPne\n6BbOIVoAE6yhUkDoIFeX9EQjekXAjwM1cx9p+FNQQRnflti6p3RyvVXYS3YNzVqWuHleM879hlhb\ngYjRO8yFxqWuBNuc3bk8I+sLtMBRWJ736U+WyGfh6IvQRmJ5uw2hEHtz+zd8MYv9u5PH/F4llsQe\noPRHnldhKlwV0MopDm3/IXeskoJJkP6dhtdyTNcxPvdLim0aWltudIGhe6P6Ye6lxdWVUxF7oRKq\ni2Mcajp3GSnxFEigq3jWYoGb7wdS/o53hv9jTsRtDvdlNZOo8N2J1vw60yreDBQy+/VDI+bBQtWI\naiyzxAg0G5LuP+eBVMQWd+in101fdbkLJj1D0Lv7LJj3VyajZmn2aLQGCRadJWmy0bw6FbkCdSjs\nZCbdcJX/MkRqeELrP2Jp61ShSh14H4acHH+euV1xJBrqS0Gdb2ZlXPCy/pZRPIIv9RFaGQNUQp2W\ntTFOiauHhndKFICo3cQ/mQgTeimiS+bhagHTY/6YkuhMIeazrYMgNZTynw6oDWueDfXVNEHStIfS\nlAs+BhyRgUYgSBIW3tOoj5AknkfFOH+l0Kmc7kUu/dnKFO1CIDv29Q3a5bYAFKn5tz/fbPm/CbLD\nfLSQrbzUZpCl0NUvb+uESID71o69Ar6CS/wLYaE3ROrTFav182/oN5iIXiROcKTeNZY1+ERHEcQc\n+Sysxmn95zodcXfYeXxJNJxZSSh168TmPs4VUJQ453zloytgCsipQymBDEnqURx4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pU8t\nH8eLdbh6y+ojHZlldKRAVzcZQsdP5ULmiQIir6SC/7vB0jhfwhuQM6EDsYG9DKz1DZ8KH7Xazm14\n/R2RIIV+rumIfG7TO1TRYDNHM0mvpprdLmIGPSUN6ErMoA5cHS/zFVW2mcUMxVbgXsPWr7MTozVB\n3KVcduDEXq4IpjLgILRduCNnkBBBdRnVU3bCGdObSzLHIbqWS3v+G4DJLgt/E2HKEaWLyASIOChN\nlAqyTPAVERW0juR+UmntIkja091IAKx68RyWWffGawJ0F7LHjuVeyiHCaiLAwozI8W+t07bX3j2S\nDVZO79GTARdBrBBtVtLm3ncbg96ZGu9oysxr/ygvc6CSjoVzvcPG+NY1wo87GphiPYNcHWDgsqIb\neLd3Hny7eISIFhzQdPneicsH39n2cE0ysw/vggq3CWTmrx4FrF2Hudx0S8bZ0Er3E0RPwOnVkEb/\naw54QJJzdd3M3p2Ezba6vQOBWdBem1IXa6e1jFgiV8+4ZSmeuHmg2Dj5Uwh+MbTXOjDtI6g68SCr\nsOjUf/yF+VXsy2WT3RvRx7FsgFrsRcUNlTtOqP9a+W835DuPYdOBmuN876lgWfdz0DxdofweysiF\n6WiEwovwe3GpdaJazuKNLjpNQJiuwjEGfaX7Nv8x8ANtHNsIZjKVxeCGR8WjZ6XXXbTGfSkszhC1\nYPHtSRAF3lEsYtEaA+5C2snot3Tt5l1mIJ796HrceO/MCZZslu5qivAUq8a+dVDDS7nworarg3FN\nc6DbTxBRbqmLyhsCC4nEwfQiyEdcp+IatuVGFC55foOQ+x6L0OH0dbtTUcQim4C2hoK5shMnrRkN\nVCP1MaQlnLGMLo5ykxdofRIIlHlQDd+zA9d1gEdicXLH7ZjneC3QEWNPKd4HpnOwMoYECEXwrAxO\nnyLjTkLTdXRabpHClkZLe86Kq5bw8p2HhsCilA+esQrzvdWaXgCB0Q+MV9nUfycssUwcjUQjLmJ6\n7XC8ZgkPOxPDZHCbjtM8Z5QcDuJ7kIo8tAe9OXvvlSys5W2LVYC9Pcm7nImFAu8ZDthRI/YYFAzq\nGZdiBxPE5Y5GTbJiFWdfMzXxp6LL9FUUu6yDyjg44dhR6fg/xw1IkSzNKBRFlmHSntzrYEDZ+lmA\n+QomgvNeEco4uLy4Et9d+Ei68M6DvQsKGbb/P14xeNgxixF3+iN3fJbQIqQmnwuxFTlH0Gt9PaVy\n96M4NwL/ToHfN6CA/ICIZkGZluwLFoPSMJNW7jAvPpFHkPOLWRMbH+Cb7wi/dV2esuJXY7HMpvqD\nK7/nHZ46Tt+AUb90VGPdS2L6tDNOcBUQnrQcRAKGAKh9gF0Vs2iNVXpOO4zHkBoCVFytnOdM1VWy\n39c6jjDy7GCtQ+V7cSMmDp9eU7/EB0hZJU+enoRMq5Yd/uLFY+nVkvYQJ45ISNW0xPqn1sweMyLe\n8Q+7Qavbo6pRYhNYRWc0hvLZtP99gHQDza2jEwR0sbNkLNPUq6imFR8Fqn49NrkvhQr7kIyEH9Lk\nP12uON3oEi8OOCYk5E8j+9dDhsQk4JC9d8OwZG+lEcrYyPtwK4068MWPvFNWWrtK+eBPJYYKz3LX\nGq0TI5k/RTVvpbCvODKjV6YlFU8En8jgiKgNRAiFUePI6roFqtuIhZE1Y9BMHmU8On1XwLCEryYs\nLfIAzH6V72Tvjn6U/yDWQkyB+m9Zag+DyTU84TqSqhF5OSFNT5Xm4c+iAo0ipcC1Ycd5VrEVDswt\nrfxDeiu4lg5Azw4AlK21ev3FLOYVU3m9NXWUFUmHyS+irJSGbkZTyx+kMUVEJuXIAy8Nxx6EN9iQ\n+ARvQoQBzHCvkrdceDm4+3jePXQ60sFmcu79VIfseVib2cOBzp93C0tyRFnU//fMMFFXZFvh9HMo\nO4+7HQmuKwiv0mEXy33Rum6grtGJLCOmfAwp9bbybMmnoYWp84kpOmU5xxBEiRyPAQH99gzGNGwH\nVPlx+FrYCpWnJZa/0qvBneZue8lQMpx8VU/+Rx1hJMNBfM6KD//pkaJtEQQjMukmU/7CiObhncw3\nl5N3IelyPFQdU5/BkpVo+ZLWot1ArIct6JpN1kReyaB8iz5UAXitCbzv4Vsj6a9UsbiNWWKN4Xaj\nPBfFZx1ODQqg2nzXJEEM/UCA1iK6+pvM5JgYc1QX16Ake0T8YpEvzOUA/lA3NChQof/lgEfoOAqb\ntcRmXlTmWCRyZ+iNcT6bmUFDIi7wriYrNbshpg+5uhWYPV3C1yT8n62FUa92cf4Pj5JMP1aHgX4s\nWalVghT1yRAg6dwBzMtqcjWkeGxASJFvyTeldUh72XKcJ6NorKhczY7RqaZz8fgTuZfR9ud8WUYg\nyWTAUxOw1zs1rvQDrm60HjyjkzmmyMTtOBGatjXijRw4PXbQypVTBZKtb4yYe57SuogvVEJoWmYB\nuIWALF7OQYqE9/J6wZ+d4gnehDB2NvC0ru6SjrmcmpgLFMW2vI4+e7GsMfGRpqFIKZQ1KYndt0Dp\nkhAcfJhbngz8VK4U48Kklu5P7SP60SH0ZIdK3oPwovXfUmkxGDwlhA7YbS0sh9MrpJzoW79ZlmTN\niQGhSrDibpX/zTon+7VHpZENr29o/UpCyz+hlx3PnMy+kfTrQx523TjqS4hzOh8y63uYCukCHAPd\ncWKfSa5bqJDokK+SSg4hE+ygsGgWdcZUvNg11jUfk2TnPYx7UUwjHitzmsq1ZntjaKA2j6pjBWpj\npGKfV3z3W/b8kVwfwl3sXmyP1UKZkHVRlAgiPwRjJNJZEuBrsJWP1/piS+7BIxAL6mfkBz1mYYek\nJETyV9oqkplDOhJ9X6j2yKn+9w3AuZZuRmVYqE3+OKW/uvAwDL4uyaNoZdDKt8ciP7TMTcHigCI1\n73WFJFLMbu3PXQZgMkycKH9nrPQxBc38PcYrPy9EeevYAu/Z0MVG4nFBUVJRJ9vv2agHh1gfp54i\nmNEX9JCEGD32nUdQDyfqtXEONecwjVasYciiGLYjJoC8SbY9xLsHNt4VOsfPcTz81rOm+bdg264g\nHxlu/4TB7NdJjqmaQimCjn4TRhzXb6Buk1wg79Yo2oQwgvljrJNogWQa8xB6OCDh02Br2CqTropE\nMTlN2Z8MEgq9V7svWIMc35imgFdQyX2aKfJGCa2jieWMALIX8Tz0/5M6MqxmZn6r+mywOkMVIYmP\nqsUJn/j0GtR6jTy1O5zfYEKWG6gM/uIHB+239J1x0MeLq31pMggg61WYJ3xjH9gUlBFkTxdAPfCS\nbrx0m75n9TtgQ9p8jcI5AGqY4bcro4CngRSRA0kXyskSRquZeG7lg9rjqGneEMGuCB7bSwxWB2WZ\n+clg9kAkwOJCLEoXwIctNnN9Qj2EPTazs1NXUtz59zI0QNTlO/p+3Uz327KNwwZ9//5x7NPeQ9ej\n6Qlpm4+AX1srnBtDePI60bRNoLkKtOa6cDFOEPLQURdieYbWFpRgmsFDMT1ihELx6kTAuqBlR3Pr\nN1LUki9JCs2//+wTOKBkZV/OmXR1+QaahOW74+Nl9n+vRlt6J+hEb/+HxOZEt8wMaimRm0Ftv4Fx\ngthK7ZwwmbNBxBaoDk+UaC5XpL61i2kYeug3Q47SDWGtPRy386xVTGJnN0vaXuUakx+Rn57iCWJb\nJScN4zfDzarxjEXsv3pQC3tthwS4vRP/uOMEzQvpFSfGWa/Urie0atcqEgi7ndQqobUutYN3s7by\neT81wf1MLaiD7Jo2fBXH5I8kjzO6oc5wREb+rxkPlGl53Os3H/14i36MairjvFD8kAvOc96jPIDf\nXrEnJycTUY+WnBfQqnHSGPeYhCvPaHAL9Lj+b9KGP9Mm5aTHTjMRjoYv5Lh0qLcaPXtkz6+1e9r2\n7MFK+fLltuUei/5ANFY4fhN7LowlKATeiREQnSFFg3BZ5q9sv6wUEwZBKaSsROja/i4fU2goTQ10\npgqHZx47dZuY766Y2rdhNF3rTP9yB/GSeY55+PfLslf7GgHmzGSzG9Tw+iJNLJQPOQkL0uPLbfPD\nhdDDGz+TfvpvIJ3hnSxFpvnXNZ9cN8zoVbvDU7VVkadvtdTHYHs/BH/pxAPh/H+58o3PojTSzF+F\nm+Ld45E3ym67glZV0YdpbvdDzhT4+urcW66872hCTSO+ORjO5ev1j2xJ8udRDuImZCQjZ1oP/on2\nPSxTQ/GUl4mU/dqBc5YhUdaKplZHpK6SWtx87mGOTgAVcflBlrIU6svbeBwfa7rSxOl5M+HZOX35\n45VGKuXtYRf480h3ixBugwgc5cdtwY1UvdSGhITgZNb4+mLyMGmkpa6cRAZZN3DqY4TwULaUiwBf\n3ZvyF3hLm/1BE/c05T9o2XoyfnZ7b32FQoWl75xSoYkcvfeYul39y/XEZRXa0Kz9Gdewp9g5J/Nw\nlSfVL8jF75+QHM9mxmIoxPjGkqwqO+w+0pZu9R6gmy+y/5IdlNGl1FUol57anRzaVU4T+7PKM+BR\nghk6iER9uN0d1cvsAH1oSdtOhewHEepQz2KoBYqzMbOODjmZpZJe0b3GOOxYnGpVsR2oxKPr4ecO\n5vcWTHXXzYa/90awNmt9wH8qe9bjW5/3QwCjyAin605iCdzUcuVd/rVEqPDPifhfosDdhB9cADry\nAld2YEZKIONotWx7rdhLl/WcXXFd5+CBINiqB6D/7fk/czqrEbHTX2+tA/aSVbRJM6+M4veyRN68\nTRK7Uk+aqfcxiqyuvicisL0pzTVHvAHVME83fR2F2RaI0GbijlRs4IruS9NGloJH6BPxubwIJYxK\n+fND9szy6xcryb/ElJ4zge5xKn6EBaQU+T3/o5s/dA+eA+A3eAA2kXhy9e9dwNbjH1BGKtxpx2so\njRvBQWdBHveGYo9huPUD8x2lgypcHB5J+Z2b5J0vyjs+iFKciuUZpsiLsGZIKVrH4T14XTjovSWv\nnyLA22GLCYxrAo8dGD3dIIsUqKKcbSS3bsZLf1dAyjuumIUWYHeimWc+OAfMMROtq3dB+w5I8A+k\np1DMYcYHqFzVnkWDequc+lloA8E/xtHxgWdjkOJZi7O0g5rPsQEgeMl3sBwZZcHwOa9dBlBn3WNN\nyZzLMC+P5Er2a9RBpHG1bhJoCIJBGXXWUyXvYsO4yoKuRAHf5M7IzZF7U5SdhcG2i2VYsAoqRwY9\nHW7VSlEvRNas8yUQVUcTSl9/ESZWAW6hDU/JgwY/v87HYM7wu04I7aDBiozUHnIaD1CK4qHpbX5h\n9PlxbVWT6NJ0cSFJCbyGqtQtX/y4Z3yF/e4cjdiWgg8GTrEA4VXwvl75UULS4FgDAxpLH0waFuD+\njQROR9toAg2S4nlhs8CR48URTFgc0kxbssGFsXrdk/jE5IDqKH8XSXUHCfhOUsAveJonYsFfOsYn\nO8qZkFtbnOQ5GIDnlwycpGSUFsInTF0tbMPfF46Red48hdhTmGEg066anMt6oMhS0muo0tvCYJ4B\n41AnUZ2sRI6HqW93F9g8VpErcFKS8NI6QEhxbz13ClSFUrVA/6WBW2NJ10aEE0GHqPcYGJNoNV8D\nkxFJ1t6taW7Ef+mdsQrgKHhKTqjaqusJB49drOOjzJ96hb3pE/eKEF/vLm7OYsyiXipKaZHKsPBa\nWQdPOSIWzvUko7pMw5LvPXm93gKr+emQBbvIEDC8P9Xkj/CqR1btZmmoHPlmJiEzt47UmSAiOUyL\nC5jxtIvpB5n1tvGwKHhcadp8DTgxcQQNNX07IPyAfh/aQJF8KnTSHe2SwjlJO4OIM2gtp8kkj3W6\n9NJjoi8BzrvxJR55CUbQY0pMOSKhJ912+CLDK7poNDwvjgIs2Cp5kEISUUVxYN408kD7sYB72DA9\nM7E72zvq3GVhyNt3uGPDFajYsBHtxd+xAAp0zXfplpYK4cxH0qvmgkctRSafESBOXb+vfwg0h+1K\nPBQ6XH4e5pE1kmKn9XXg/E0AJdQyUZw3zRjHkQmFBXRugjAEWrq2l8/mE+RlfV055akDFLvFV42t\nwOk4o/KXdZ+P2rI0HI4PG4XzbPMSxHuenxFXCrZLPNASO28382CS5DIndAIPuEXJCLkWoxuKDhvG\nR/dLnAkl+yocZw7TT66eKxgNaUUbdaLEdFtT0EiSJEBqxFfS9d0myM9SwbLHOHS7hjw2k8mmNCIe\n5baDieOXYOca6/vrZY7Td5TzwXMiXQsOBZoTwURrDTI6mcqUeCkL7Fw1EK3fO/4f1uUsCyZsdZDy\nyD+zgMRYFWQX/Yer1S/y4UKIbbJhye3ilo1eooHGwyhbi4AYFH7+yFMD21+qxQ+qYR4WWPPVMZEQ\nOSbcw0eQtXJnhX+J6QT/NcWknVjH+Cbe/KpOiKSjDkCvT83cT/dFpzIbHAWxe3lup4zviPH9JdIq\no6Z71MWS+TejRjX3fY4Mwk0uZnw2Ad+HrbpUlSq/MxnTRjo3nlTsFhO5dzlaFYtw47iWB3XAe5FH\nV+tWaCpEvI3gklF0eFCIpYADbeGiLyA0sfndF7QHUQUW1UgmOliTYmmEiu6LQVet+2ZJ4AZvfsHi\nXtmXohQBi7nvhOHlUt18uSI5T2fXqwZHhc+pCg8FSZN2nL+LinnNZ2ri1i0wOA5lNjEpBf5y2Az4\nslk7Wk63sFAXhSISHW1wU7wiR0nLdhEqZ3Md62F/brGu6RFlk6cBViyYXakOIHAq+Oy3b4P9ca8m\ns2JI77f1Sy7yszybSJcD4cQXxCwpA7BZr4T1PszboVW+MvRXOZhmZg0KBWr1qHR3K40H0D61rBGf\nNPLcAZv4N71qUPW071X0W3az0q2y8bbwqDvKNsRtwJEPuAgbfXh/awH7fmEN/ETXPQE1ffuaVqPD\n9cbOh7MWjLxtgjTH0NcczLEB90igySe7zj5MuL2cD6txamO7swv+7DNFuQQuSOanzQRuJkTbKLh+\nEEUmoOeWX3JCXXPeiPGubYHoT2zGHj39PGpn81F3rzfDi6frlWCwteQVmHzJEfGKPByzfOC5VG38\n/g+8MUJIwjZGDIHBwRLjXrSzmJwyZnZKpuX+++v3sEONgb90kwHi3Ev3tyPs0040wXgzfReQESGV\nTkwmHFH+/HR+KoyEJw5Q0q8G6s4tpIE1HpbZDvVE03yOOPDtOvaHXLzpwyahuASPQi94eAowgIXO\nUW+jtCd/cflXk+pbASxL0+cz8dwvF75fu5k6jj5ApPA3R6YQqu5zOpacke1G2wn30zxTe41ZYBD9\n71iaUEdZCtI5a3bgQzUx4NSJfxrRpjeB6AD6IcDXmsshLzGR0c7j0wjoiUlaNgpRTZMLJtEpK/T3\nPhaVN7zr5UH7fT2k0Z37bWV5C72Iy+hKsRsVDVUzpph2F228WG4PpKlJOdmchYpGGLjAF7/ogg4n\nQcF9HAJ2B7c/5Wle4dsUXOESplMDI5AzhhshabUpySu729IJW6cTrL/vh6/49WxnzqInRpS5E+r4\nTtir41K8T5ga3vxsOeTaAojGbVn/S5yihrKjXT0tQbvf9cs5+IT3tPdzJcoQwMub60md8XPtS475\nIxVmbbsLCnBRcnHvya6FEzFd0B+HDKqgI5rPacPrl6qfdzgz9JqGKMbH2gz8BzSaNzQMWHVzX0SS\nsNdDWg5i5NgTEwM8qMylX1ig2eJ4o7452QJw6vCk+yGed3cD/s7wnwkwneOTQSth0OHGqNwvRwf2\nyMfj62F5ByOuCV4PIMVMTJMhcgkOjeg6/XeAwuSy1TPZx8494l7YX7qsNWAmJJNcaYnDTp5IAHT5\nI5F687X0nfr8a05sJaE6QdzcwhX9CI16o06sAoJyLTuqRNcogU6uGVg+7Nc3De9MgaRn4c+utaGV\nyN2D8o6r/kuXwbMbrBhYEDBsaCKlEMWLy8IeiKn5qElG6bjJAVkzjwrdlT5uKHv3Dns1CVutlbTG\n9gx2jxNL1jHmZAAge+StSfVLd9eDAlm2tq5+sD/MNaARmVEKlUshcJ0lGAGt4qNs6G4tLE/Dp39y\nO+9u5BdkIxInUdBsNyhhQwoAz0IRsWgQzBe1hlgOkTWC4B5HYWsgKX15zXJdXZVJgtwbN4mthwJT\nFeNsyYRUL5rBjwqfuv/YYJHtLEvJkC6HdIYp6JrMP4YzY0xCgrJNNNIiW8oSEtKWneOjirs3zMZi\navdl1PewhRuHpZuZBqeNi1MMudnR6coJsAjRHNV33Wy139oZxEjh1xqctNfCX104FbKFApIhpfQQ\nkA+0KgIHBVcs/Cw4aLfvrlns8d0Okl9nFUpMjYvVTIWrxafY+JJC31n4RfPzNUL+Btugx2n2hSmX\nOUO1/U5Ab8tcasFPJY08fQKj5lOh88HOOF3tCvtxKOSoY/lw0l2onAZ4CaIbkgFtvEej0NtVdi39\nZjxpWExAQqD42r21kewPJqyL+mtcNy2TrViP/mPO/zpqu8zXzzMTa7BsZlcUAWIXRAnq+/k4wZm6\nAqqUMf2XXW2iQyRNeO0Mz8/Y+tDV2r5lRDZXrNaGKpYddryURz9Odl9GpGy6eKUln1K2d88f/dyy\nZKGYZqu+nLH2UrdnFKkH2ZJ0zscKltpoxWUuF6LNI1HsjruCrvuS2rUrG38tx44wnPpaAPJMLuAy\naem6dyV1NoaINdKWpimJIAWS/QFjjfegyjwZeZFnX5LydGxPSxz8btqIBK+eKlOJQm8mtkoGWZ2T\nJiYIepGBN3wKIz8AgKFavslwsSDjF06I6DavycvPltZ1tBmibQNqNYMIlOyD42fI7FPGHls3Bk4x\n3Gh+q4kZEoJzuI7NTt6abOy4O7yi3RuKVdXJlfrdci0AbGbmu2ElnH5XznTCQuyB94lFyS7KNdrf\ni+gY666lSI7tv2ADH6ih1u94YghU4SBXaUd7SUUad4CiC/TmNX7y/AG9JiQSFphapaZMMl0gaY4Z\naXv1xe5GfQAs9U354BdpMxq/sZcLkuy5JDAyGkdClWKLBnw2tOR6g8g95VIGB/oUlLVUDYfLtUoN\nEVZM+df7zbIGJYXmr+h8tHtjkkteHx5u6dFU3suf72lr8qfTe9cMG9UhaPiLrtd/B1ASG/NnfZMF\neFtsIAZhgOclITRHvygjOYsyjCgzYkTdGcI8mwiXQ5oj/kvv/oZMPsnlqCv/T0EgCNpor0oTIWR8\nwyIZHvUeg6Y01pmOdj65mt8FybaG/dpE7eJ31vCtRMMdBgBUsdxclOLr0IV5Nt6OB5I7LqMQ9BDw\nbPi3JQq6vsU1d8MvRTeQh0d7eEP4/GnznXd9iAqwDNzYvUujRJ5VUW25sRudtL+m6/m2zBhsbtKH\nfA8rAzsAPnQuj1RTVNdqhY9lfytbBKwfI0SR2SZ3c4OqrLwHaj8wPMJbqEGaQJUQ0JZ7st8qukxU\n5i3gGAC0kgM0JyvDH7d6GdnchzcvUQHjlK580gE/8UmzGTpZ+B2R/CI7Wk60hMQpO+rQYYMhTkaG\ncTo4/VW+7K7oVMobOj+qK8EMXoKyDYq8T6q6dH1KhiiFo8bPOvzI0x097353yIFL3cLWK21rTlcZ\nsrNzkA+N/FRmQmdal0PL8jJBPxJOFBXUdAKcpAM/GlAlkL93q/AeTzO+O67AUF6yvsKzpX8q5NXR\nZ/Zjq5uo+KqiJoBB/pX3ggXX9gGeVwL0eIxeUFUJW1j5gp6mm5WJxZX4P7qCmCrr/0xxKeJ+VYi0\nDWpyHnC5BfooQ3Ex0LLzcqbCZqy1uxt93oiMvWtHMEVnY9PLs4X0Pyst4m+TYyWKrYARn6HxziP3\nuf52x/4KoU/O1dsxeok+NwABkiT3+XwhapPEVC9r0dY/FbAA25eQ6hMTlBTyIyFwdD9/fw0+apE0\n4kyYtEt7Q4gOg/IL7GvFJMBG+r3hzweyyjfYrMI0vzNWNW1tcLTRvxk5znVxiX0dWjY0kG5tbhC3\nDqLixURuGMGsSM25g9kgESeaaHKpRKfVI8VMVl61zDS3iMbP/wprjoM96W3YMBtMljcrZz15OBfC\nTAB/qTE9Clz6FWL5WtMoJSC4LRLQr4Cg19mn9YyMAgyhdJRaDBfNeOm85oGbKpvNCGqgWMdEahsI\nEqkj9kHmG/U+jYrQj/vYwvJ6tPQvJihoZ1Lg6dRaaoMvyEbYX2uFskjajsIBpwDZLccAMJI1sGMl\nGUwd52rRXNnwLIvjewFnLlFnO8GX4Eo+dFfXi2Sfgl7y5A7wtg9LWQrUfMGVWBp11VFu/txXi7pT\nFO/iBXQuZurbMddR6PgKifqE9vEsQVDJBH5ccqKl12iOyVuEDUpHZkBu3JhY8XXp+DuCsWP5mGlE\nqnr7oxGhP8vFpLtvYMgtF4Baha11m/Wj9tMvjbyoxG5FbUQBjxB5yGGzwHjvcbDXwcZwZib9noP+\nt64Tdag3NT5mHUgEgEjbDsU6vfY3+V+DIhYo6e1xoVRu57RcyiY9+Gt+88zsYSFhGAEd2HI/25b/\nCoKLrt8SZI2M4zAlr2fl1ErrA7cjrknz6bD3eExpnDp/BEt6tzZd862hWet6r5zkMySzhEQ1iBfY\ns7uD1m0dnmpmaPywLOgToaxskNzpogKVKBWZAMU3d9f2xK7OVsqtNTkjoERLr9AqZFe8BzkTA9Di\nWMdPgWZZUXw1GOl8KfzPoify1VB9RPL8FmqTeF2lPUGFeauc/6K0F7Fjz7dx4GwcfbbtBEzKlNLr\nKIhLfC2TZ0GeMPUjAganQUYnFlWG3og8oS2w3vDyBXsKS7qn8Hl64WvQvL28TvlfozIxj/ySSwbz\nFNKLPYpkJJwte806FNpBkyf5dwQeyGBR5n7cogo7paU0dkFGASss5RldQoZD44v+v464w4XOZd35\n4xSvezQMFB0Dk3O4UMKi6JShZSpkK0r9ect29pOL5UXME+MYj8QQP2Ugg5XaSa/maOWExwBYlPib\nI/NBbSdnTaZoPAkpOaajK6fx/hMEWI8xhOeJeJs+PTTaDVa2g7PW0FqkHguILMtUv8+IzxEGw3aw\ntFkNEUqMwMlPdKFsNZ5bzBO8FzSoLnVifFvpdSX0k+cvtmvBjLdIfxirL5TUC3p4wFEr/thyfGLu\n/Th8kkWK0fqQg6Ahj4GCpCbQ7A2RjHrULAl6DsJo/i/3PL590NQAUlrTcL9lFSndhJRgtK0R45QA\nHJF40otsq7x5CwLdGaxBaoG2fDHAeLbGjd4zGtzj2Uc9lBNHr00Crwb08LHm2rdRKm+ex2uJmhe2\ny8IyR4BH5P0Cd5Mi39gwsNhY/9HGbjvbN/yf7WLCF9m9RZgWe56GgVwG09y13l/eJbzM+/Ky9jQH\nit0o3wsEFd22GXdtENVFRMIZ+ZusAc20TshiETt7CO8me/UdGQi7GsCsvhPyG0RF2qoe2XbOcaub\nKTIGIWRdrO5hq4JTwQnuJnMw++5XEiH8RZ3c2LLqMWPyKe3VBckH/C7yYnSezkJV91DhnExv18Er\nt8uI4YBi5qE5XZbRLom2w2A8qCYMydOCsG7/xMTLgpNaYZ2rvos/mEl/MfRTQgMjUcUrdFQ6N5lm\n/TQ7nq69E4qVOLKJlQDfRR9O7xIgAiljnkIHPxgSA4IusZQDIev5Deg/CYCK298eTmo47UrS50gd\n78c5gJOAnxX4GpiA4UulM/0PBvJ8jlBOx/MKFCikraM4aobx9rpfRP4BngC90C5y0puvveFNKnCc\nIqMt5cekHy1AXP/K0pNfEkhXW2OmSk6LEfaLFzRXm137SZqKa4fylZxcbbdZGJr6iRTLRjLsAiV6\n2QJbZfhAlb/QQjmfL84UITrNKA42XemMGZIDDEDjXZYFQrpIYjZdvaz0m2eo4IeejMJmqz+c5H5W\n4nAL9AE9RK7Fl49NmGGZuPP1KhJd8gltkWXbfBMF1OYK8kGeovTDfZxLqVvyEpK+vCXqEow3hAWd\nqzu9+ckvFRI1fsSy0E7vm78qa0dhqXy0y1eXe/44GeRsXNg8FOD8imTVb/b3H4UJD4HQiHDPcgu5\nsR/XbBUq4huE/psdsomPtxUHR+9hXzaQgzSykOQoaa5TVadsGMrQwgDaLUD0dlxOG7b6By02KwaR\njqyw8/KNn+TuRLalfpg8yR8u0bsbaQWxVMHil9jGvzyIeBb459q2iK7FYJEvhxAtIZ+wyND0A9aI\nTtWJqnKh4VptXjrde4Mm2LM3vuO3mKW9mnyErzvgb3CuURGEehfOICDNDxy48W+YsKUjWu+a6xrD\nPPT47z5R2Ad2QtEYsnrTPeKwZSYyQ6LGlJjaJoZ62EHJBx66hNGYtiKFEYUPbFrTTu7REAdozaLC\nhQkxdqYjSKVyUtzYVgqSSLwdVEz3hkqEPsgETi0dvW9CjSnw0TQbdT5jO8Rbt6+hQBFLZWpqvLwD\nI224J6/uEURNN/md1otLN1cWRMjrkee6YP1O3hOxJifmw9/BdME5Ix3XBqs/qNyZ9Gpx0prPBW8+\nWg9eXrHQLtTwOCtEtPSbxnAjXiSKs/3TGwj0LhtzNmTdAp3mUVkEw7LNs369Ir0wwi6e7tN6UBXi\nKmhiCUA2q9mmgSqnshwds9Hu/E+tm4pzRU2QNcWbP1A/n3Zs/M1TEvfEUjq4J0rd9QDiJoTOw6be\nalR+z2Ce0ZTTJhUjOeyRIcMFq5pCyD2kYSA1zgJGsesYSSH8c4HWw38eB0MX+PSGli5y3AT35roK\n6sdvC5VQX7VjzZLX7d9BZc+i9GxYdNUe2FZsG6u+idXhVCxTguHJHTGzVnjQem9736RvhUTL+lot\nlclUuQ83achGN80nRz5THqPM5B2hkqcdzxfaX+zk6DiEA7PBiksI3c3rYuqW7fcwXry32YX0hekv\n2Lw680PvBukMCpbG943v0za5rMVoTnTOSe18pFVYNulaQk6sYSUJyBK+RKe0he1pkRV0D9QJz1rd\nJH5kMZmew1SsGAUEOivYKBcsrOrXIvO5jELRIpchqLGocEndcCgsN8aahcnoyUwspmvhVQO+TEUP\nPLz/VVAV46BFFlN2HFJwT1Ecrxw9bzQbQo/nasestZJKVKfLlAg880RnxPY5KPvgjKJEVB4klG05\nFw9HX76R0F+Tz0jSBXeq8pRUu352ySOXsRVPM2PuyL5yfATrKv4d+nXJrd3RCYEHTVoVuAboXMCQ\nJL8DNcmthEVGQ1KoPIsMMYZxxPm7o5czrHewUKIBiGM75zUX58doEQIOVHsIIltjXFZDpgLDHTz4\ny81fyyR7cd/LrgsoTzUqun9TgPTHxazrri78XsFTRo4h6tL5eaqg/pnnXd2d/NLLniOtPWWel5HG\n+wdlpyO1qEMbGshf2EyW3gCfdgEqZcmrjHlqss73BgiUDc2ZhjSziesqADrDkKXAaHJwxrIqm6iW\nu8Gn/fYVwL6bFRqgDy/C37bDR6yCWDY1DHU24NdYyypvGUbZvUVC0y+mHsMH+qVjhZfjvzsPlf/C\n9sIvoVckKDk1TveYv6qZ4Hm1l4JSjZbAb6GNJ4TyExw5aZD0I+B0NrzooLuMq2jiy/d1q6XMm4iH\n5SD6+FDielW+4wbxfo4q2901kBQZbMTV608QIWJDM25XzHVGdwzMgw9w4VtoEOWj7OoAqCwHog0T\nuksMDVv2Vii93kxGuEGj48GV822GdZh1wV9rHKwo54mLPd/HnvXIaXcOKq8dj9Fw/OmF6C34UNZK\nLDhJ5IFweFg+8t3oeV6c0gcIXFzGZnivm6G5bRcIflYf6/WZvurhRcveDooguANJV3mwxcJhbSz6\np0EJnv7gq9MLZhxuRtjuDOabPP9QgGH9mu/C0gXm9qRMCXjjp9mgNcD7YpbrR23+YN1tXwm6mHpF\nS3d9KL4Rj64BYkWB1aA3hjcTTsH2euT3fet2jNrQdYFptJxTuTWmBuLnW/437T7m0XPHV8NgBoif\n0Dc6x1+gDh3f1vSHGF7CwDPDwXGTYm2zispIpi7yby0Tpc26FTvrXLXD1wJ/jCH5V6NZLNOdbHZa\nuE0miQ0ucFl5B+djsjrBBEuil3GO2JfXF3xiIeM2n85F/lFNTq/QXp5xX20V0izsQRhylg6eqf22\nUhxooZ4BUXkouFjS8hTSTCU77LTUNUQnczPfacs9dlNsFWT0EkNOEJ8mKGmQL11DdY9zNVyB9A5z\nQ3/tRo7MjBj1tE9j5JQ2IJdhcT6aJdKSzX98b1fudbPcWfJi1mdm/4E9Sd0+hxeI7QiYb3T6QQpD\n3j6FFncc8jFQ7Ir3Y9xgzWp/HHsRoyM6YzYPHkwR0lLkmi6PMdBnxiM6bdOhb4gttRRG00x7GzP3\n3qtX3mAIySdAyd9paPqVanJi+OEpViMXskl5Bp7/vUYwfoOjffC6lOGf9yqHFiVbQzV2JBV7zlUQ\nFCxecghSh+AvQqegnBHwYfZ2n10H9kia194tFJI/GFKpYE/kGfyIWO+njlJ/JoQcYoLlyHQZVx42\nRjnrM6f+iyjk/hnYILOIigh3vhHIabMwtvNbstOGXC9HF5y6QRGzSKiJQYcjZlRmcl0z9UY7D94Z\nMWT9hz3UWfPLKrxADSkFVu/RpZta7n1i8nPBbI6wKucOo3M6iNgJ3POFepRj7H55fsNFYo9hJbGo\nRXpLSamAsrCqPat6nyMuaYcQIi7sfUsxsT/SLby9T59LOGDdv+a/nwXmGKvDBoOFFJ/EJvk2S1iy\nHkqFYoHGYviVXdq39MdABxBt9dgQPFNQMXKg2NI0esEKSj1cvP44dAOzklnGPWdgn1s7GTbB36Zd\nPcfMazxu8X9WAsiDAI/ZULStSy4Wz7KJQUsxMUNVfg1N+95yCqosLl81OZA80tsv2xlvB2ztADLN\nOPhfaxD4UX1kfKrXxx9PsrCayVhKqn7co5WSeQ+O3oUSWRfCcm5M7OZJTzmfuZ+gM5gwZCWbXCIm\nzztR7SaSGD18SQxN9ycllBvli3qJt3Rbh2J3SKWbvhU7snLGpBqs4dro3euNSawoPptkyRGZ1BHc\naqkj4JGus9thXHYRSGXrIcbvd9MGEUmgdi+ejRh5yo8dpXcp+GBpJBzYod0voCnZH4G/00dyUP26\nylZvb5Hg1/JvqKnYa0wRvfnlJ4vs7Bpcg7qaWsCPxNJO6pffKoZU7t5CowS2WtO13TDo+xQuayAl\nEfsSNqPUNiBvZJkVDFaaKbg3J5+7mXRAX9D8dgSSWJVDPqtJRgkwVjNSHuu6Lm+8esrQmVCeecCU\nTXCd07PedYDUCg9YinYQPdUGnqQ3E0xnvMKsoaolxw8bxZcvOGujmYhov623KY0iuHbydPYHi7s2\nCngr5rOdrl6g7IE4JdduJ0qOTDkAKsPD6HypfuqVz9Xj/rGh52OTiXXxQGCjYXMMcpkKmYmKwV9X\nj116vtFi8BovbI1TZm/CMRH/fCZtvmZuWOYrWBsqJ5NpCDyumLUeqT8jTik/kJEKtOtpsXRXuQ9+\nMNzzgx3nLaynZgvskUyFf6Ea2OCUrhuqn5rIj9rKiVSVwQhZhKxkWYuFQ2xu93IX8tsd1TR84HkJ\nEqjHRS1unYqPanYwN+SJHU+wQI1ctZVKuuAwtSit1JWgx+VU1nS653T91Ak8LlkBvYLYUeJYZWhi\n0q8mrAwRetSYHYqDn1Oi6bEz2N1lV4KpZF6uTNFUVgWrfpKqSRIZPrqO4roPJ7jTkgIRsC9POO4G\nHFkKnXMpswMoQqmQeI+dzdlpItF3Z6cuC+7NsT67/qGEL3DpgQZz7ubrWmr7otpvEfWBg5lwvHOR\n02jKrm19Fio5Zhyn2bcvW84mzx03R05msXWtMH8RQcTxGoiXDf2NEWIAcy5sCvIRLDS5b+D+dMbg\nm588Q3tE0EuWDtkNGVbYiaE7Qvn2tdlMBuEm0LCMYgCqIIvKCtnkDgeeNZKZ9yRTyhusGq7zc0x5\nsgdUQ9T76nsNpKkReQXHk5z43LkK6cVkmGVbOu/WrlYTJrQcMpb+D0ZnuvaY8SzU66F01yFQBQqB\nd2tH9MOfFQ+fV+ym5Q7uN8XvdDnFFHmiY8bDuSk8zBGPXe0tGCgdlTsDMa4MC4M50a4Ath6kSsvG\neJGO8jWdMM7T/sSPiQPxq0iYq9Iy2nw1P2yiJ899yu+hct0on7xPQoBLLttqgPLxAMv09YANUOiH\n4DNylCTf1iDDTnXxGlhBGs4VsNCNDNnt2XbtaJ49X7kQqbriCzp6++brlBVW8KmIiG3wGChae9fV\nzU38Ie1Xm4Ku0J17Ilb5Z/IpTLv4vHq/1OsHFldTHE9caqUmc46/otaMgvHpUBVwJZmZf66X6lAj\n6fr5wJt1UsQOf/tW4SXF3XdY52QI2DCyCmP+dmj0wqSma+tJcufeyR2wrLNuwQTgOCoSiqlhjCXf\nSYhjWluS6jPTBPFwaCB2T31mtOG/lp5p54mSi7kSIf0e/nZ866E29vpJ9iLRRcQAxr0v3r2dusMx\nyAeq23VTcW2N9B4VLZo/mqrAuJiAVB3gY38w3KvW9bHBTjaPMZkb5uzI/3BBiuKaAGrQcbZ0RZOA\nGHFS/+PW8MxdOC7SzhBJSu3A5WtSi2jEZaxkHRaHgo9A+ei6ZKlFwSTkeN+W/vaRGEs9+Snt9X6H\nVvgYg+mZYJsFvXfPcQOekX6gNoANv9RPpGxIWJdx+ZnA7IZxpws2EYZqkVv4lpPWhrQEASfq0KTm\nITEaXcy8+CMj5YVndsDhTiLYiHOdpEF9R3riRK8h5kS2R3i2FYp4NXLAKJKcPLmUWyU7G7McgI7V\nKvVo298/SmOCyWm0aFq123Gv4uOrR6Iqz4i6DVOeIAH6CJMt+2uzER1D+CJTdHRUvI4ZNLK1v4kb\nIHUxK680o4ifkJ0+7VAmtp3xa+cpoeQf+5LeBtw9kWNmnVc3hX7Pe6ri9KxtJQB9U84dhArjiGep\nOSDF/dGt3uXPpwLPSMwuNBbLzLgwq6zIfFD2yc+fr1mB1nt56DndZa5muINlpBXYxpDlEG4KBE+c\n2+TfA48SqAWLj3L89Ab3gcliD99p4Ou6rnbR0MCh0OWOe7XxsOjPsUVf2f6Ttofc1u1u2YQqmUo3\nKN8pnIHOHsT0CFxtikqglUte8YS6R+xkG55YFN43BvO1ygLPyT+6e2xAv9TMR4hicHz94a1YqFGp\n8XQVa6jMlnZW7BlCcm4vILStW9+zuJNNyn2o48oo0XHOi+N/H6RqZvJoPR/t0wSb+6079HLWlf9W\ncOnYjLvlyjiLuQ4zzeJxKEH2fmhrUjPzdCQYpGDiT9pTP3/vTiNObc8aB1HgHoL3aiAVBUb/Bdne\nlxun4ApBav8RKF8tYc2TNbWUW3Iu1VJpLXeciOmtQKw/+/lrUHQQrPsY7f1bO2Cb6Q67UTpSX3sr\npbhK2VJ23icU0ocv/+yiveVQoLYmVWlMQenu0eCY3lk6NG2ztkd8mJ/TSMXSB5cv7uUnotL00fDi\nCCspAQWvM02yQbfbFBGbzp0RGhbomrooKVkuFlOs8fWwidHsN7EMB1DKsYnlye4Ohq3LE9rintzD\nOMX47S2fNLqz1QAgiMZeLBhKSbEhxwEaigGMsNyGFrjbH2OoF6aIfKVoDSm/BFHcojHRnYJIoeoe\natEKulQcw8q1VIk5TE83T2ve7Ib7wJQYEw1mJQzCg/gej+v5buUHjT+oOVyquUZeZAjcWITW5pSe\nTXjHwIxYw9uMoVSLOaY8yK7a88GsTJOiCcP4CEjQ9c58cicl1NgA686gTGalCba/hS8juKVSQkOm\naK+TESOhwuf/45iyVls8SvjBibuSgGt4LI5Bt8X1Jqm9X5x+GRCtCzF/2R67oWm+VzMSIsE7w+nu\n/1f9qA6RCfbZVCFGPU3dYvGFHNIF4H3kXz46dyf1A/+T2TxI8J+DojsuNP6MTPhPWSm9j6S4rNvJ\nhYQLsi90ex3FN2DbtydIICelGEz40BKef+auprfWXuGxhYERpBUnoq7rPJdVKxY9SiacK/8NOJby\nOzuXdCjKPJT2l2+SqEP0joQZMIcLm4lUdZWgtuTjPWf43aScyFKJGc3YZafqPJORBUQmnoHxoJw1\nJYeaWLfFi0aOAiVsdvYX6tSxSlGpVvtzFHAij7N/S0oJfnbbnaeNdIgcRuvnSs+g22GvpYvitAye\nmEFxxl0BoYKlmWJeDdK47xBueyHPwnW+I840Bb5I/iC+5UTmA9oXaeZRWPbZ+n7C5U4iZrZLca97\nEIsdEchHnFnrKZx4C40MrRLgBIo0PeKeexCoqhN1oHCONSDs/OaV1d37XuSp0RZp4Mc/PceoU1LN\nms03SC21LiaalzA6/B3Dp3MaBG1WaC7HrdEsTIMDKEtjZa3uJhGMrw1YuDoKvziD2jHqPqzO5QWa\nJYW1p9vsN3dp8qXNXDeYqb32UKbG//DbqW6R3Bodl1CGym6294QN3TTOj4LswGaFTM8GLmFL+1Y6\ne4EsdEtZy8aGJOdZ5hNeZy9RSdM7dt1vkudnNdTyhA1u9q7fk4xxw3EdOfe61qGyobdfmNeRjvas\nY7nLQLlf12bFe8bzQ7TFt/EQqdZl1V0JHdTjaP6fDBjG5vSBDp0XBVXeQ7alZy8w9rMc9UKSl170\nPR0CiEO5rEN3jrFG5Sbohhvh1ZQijqtuxocVPGDdadcF4cDUhRJNVJnejvlMr32JTSq7N94fQVwy\n/e9AiO9JhM0BXFCswcpOd7fYrwXULcxcqIRX3lMXLRzEmPOULXsGmjn2ErYEOmWCdUR0wIexG99I\n/FRwO12uPUUR/9nAF8Mun5dsw0Qmb8Dse9e6OQDUtUz6WvfLaEP6c1n7wHNnagzu1UcgjIg9X31u\nEeab9xpfomNZiPEKKLyd9xycF2tHDZktje3sxB8vIbFakZcUwHq6ZvSwAsF1+bKRJe9bKM7Mncxo\n5/tB5xY3RGWfN0EiJkizwyEGB++EdyHBnLkghA/p4BRv9KiXYFJfRrRffEwWFPHV0pOGLQAPdj4e\npkuO9f9Pzg60lsNERDC95CYE0hfkl98EFrYY9U3J/NgKDcO+jKaobbVYPVcPBDwECIlMl5eCkEvh\nCWAbAYau39x35zNaLUwu9EZBbNE0jde4w+XVltPlNhGhJMrdXZAkCteFZYUuUK8zYwlkEVSY9XLY\nRQSxGSrJx9fC0z1zsmSSV+e1eotaDDeg5lnq1+z0lIxIhlJQ0wTdkFs7yMJyNc9hrcwFQ0FQ8Z3I\nMAJlx6QZLMr0ifORPEuIrCfmVyRHb/Aj8Jlh6rq+wDlg2s3Af/D6WKr+aQg22WISSrUg6BZRoWHh\nUY3jKuXZMS9vJz4+fXYfIk8OFCDLEoDZMTZy8haepen7h/fKjsGWl5OFSNedTjA8aGoryrICCJX5\nFvl3WG/tTFXTtMHfOhwDf9xY5yh2jwm+tGy8T3Sdalf9Gc6jg3XanKlk5nCgJyU1QKr/bAEZ7xTV\nt6Pjy1tPHMMk7JvdcGm5wndR3r6YDGCdr0Knrn9+OqTILSVZmMYerfIDVcYCXN2fgXT/ctmiRX8n\ngjh76oTpSjDQ8V2RxhtiLGbTF3xLkL1YupaMaO2uZRBRsMvoYLQoBH7vT6U1mHku7tzpOMEcOotP\npn3Z+GVzGcmr0iZ9vYnJSs4ZwY4olPvmyY1PAbeYneofkDyFh+7sj2tL9nar6i/DLdRcpvdZkYKV\nv/a7dzF3aKk2u7q6kspKueA1Ahn/iUdJSNbE5KIHceQObFZuA8BMC4NsiwhMRLOUL2oKZORvedwr\nKDN3V8sxWzyACme4a/uxrLr3/ltOKzbsKMP8b98r1VKsuphp8yGnlBi4KqKJLSagUGqWxPjilqjm\nr6SvfteW7/wGEpcXbFab/nbNCREBlp7hiZ0BgjxcF6n9tLD5gkyV1aMyDYaGmf/JQ7bD93fj+vba\n61E0ckQl5hECQcl5Dz/WaK/Jp8E8TIa0PsTG83k6u6uAFwEBZtqEPjxsUW4531ZbicSTtI/D5w7o\n09DTCaKQoTo90115Pv9UJ12u/w8Hc4TSiwfQY2+/fIe4FcaqecHCQSG6Iv24KzW2XzTRZ8MU5OHB\nEvhKaufcxHbWv96xbAox/KamDmWsB4PwgxmCZNP/0WgB+P4meXenkdgNZGrpN9/Zf/WDhY5W7/GS\nr1DiI6QfV8MFIOvvYL7zKZYD7YP/b8i2Q2Q5s0ewhgC99otBgYVvBwd7RmRxRxZbkwrmFE9GM5Id\nftdVqj0w0/uwiwf+uthrNKMQTLoZY1eb5+3GE+3IFS2L9HafyElAe7JNn+by2PN1od5pjhmtIHGG\n4vOrvADcsyKyr/v8aWuAXc5VDC/UrEu1g6yMBKjsLyYHESh5MiexyYZaihY5OjPyhGefEscQQSbE\naGZEh6JdjBO9xKRBK6jn+z+gyLXS1CP2sRDeo1S1KfkaJg9yt2oDrBwtexu8pfjF0Zlm9wE78iU0\nC+WO7F5fK3znt2+A1F4+NL5WTxQWOL2i53frzyuMICy3fkOfm4R0SLDMMOa404WRtUs4ZIBI3B9Q\nQh/vNrsJfBtkK3AbWdJ5BGmtU8acXjPrAbvhmlKN6Seq42kX+WunGO3cIUidX4vhuCXUjcf770pi\nuJzjUFpqldpJkH+n3xVZPYN7/tBwHMKr9j1/ulqrR7edxEHW9v8Fgx+iQGG4j8fgtOrb2oEueCnw\nJF/mVIsGzYzx7Bc8nRoZPH7/0UKUNNSpYzykHBF/Jxd0tS5EhXpTfFEpipeGRTreurs/WWXQKY35\nlW5HhURngydIdY/W9chJRNvByBkV55jwb6Za5nHmYrBxeehglsKyZWQ3VJ+3czq6uKPxeuRs9sL4\n+Tlie+5n6k+JaiTwwrUjLnGYA93OQ+6EF52ue2J9m3MVlPWMuqfusDdiLH4K6a1nyQzRrnWLbgHU\nd/Mkh2RUvw1OTDNOQKeuGIaFyWjGmhwwh8zFz8qXmFKcVM546Mc9qejt9oQxA9Rst3ugftdiRwS0\n+z5sEt1C4MNdq+cRWkxitIV3NouDruhcZPcrHX7uEm27V1diCDZOgSewyEtT2M6R8aojq4TqlIFh\n6k/ojGvPeUA5wNz5AAs2cZYwg/yLI/aGVidlnASWMeS5onbNLZw6MgWzACnQybIzbNOjMuXYhIli\nsJ+70AmIvPaXgC6F7CCn2w4llfjCZCIIqHnJGirwBs1/JuXFtKYQ8MyWWyqbcTDzRrKvNUtQ/mdg\nx8GHf9SF+w8hpKH/JWZlROl2sQ/i6R1idUC/kMRNZCIKh6nhrchsPBkHPcEcIptoZD1xZ7bCvPRw\nR2MteyZTZJ60pbL+zT/k9mt0hGfhGeYfB2850R+hPQy425zma/6875fr6ao0U8HafnaGlQlhjSB2\nacdgMr3VUKy4iD+K69ZW/x8+ApxzNnVOSFhCDWjJpKKEccAcAoV/vmYkcs4WQ+oKhQIRO11MLYJN\nNm1YHESB4zZicmaR2QZMra475ZUmLbNx7vJi53kG3YgPHqBpJmXHtw9qSPqghjEkgBBUpmMMWji1\ngiA12BQizGvEVMYpDIdEgMHfTA5sN/ZpkTIUoXYN2jJH6X5ondjvWcUlvotn9TGWcCEur7bnZmTQ\nyMIhPA8Z6zyMaNZqFTcUC4DXlr3LFTHIMec4v+BclGtW1Z5TLmsCOfS9dijsO53Js2pydUyQNOvD\nRs0Y6zH2v+xmq2Cf+ByRFfPVl387HZHpXtNw5uMbkcpPduOs3vymAg32gm2SluQdeSNayyol8Qom\nGgNQqWAreGpIBWTho9zMD9mOxArVVKsRGNsNglimMlC+ADkLt9QxSxrnCyf9YERnz8M3SJQKxWAe\nlv9SjMLV2SQiKWZXClJP0bIE1QUsMAnfEj9QXjuY0y6dpRElKJR94PdedX2awmePnj2cUi+dxcic\nGqB3AwRZvpTM58AsYEN0q1HV/G8WnNPHjUu836l/h9u6nfhiogpjq0aaat+Ervw5hzabAwz7WPpK\nqmWriWTlsAtUWaBLS3/DYNLGtlfAe6V+1s3TF/A31OZyqKNbtCP5eFsD1e2X3rsN+9eeWZ24JxKy\n3goYLPnYb4T7WGLAyW8UAac7KOeef7E6I/RIPd4aZAoqQ6oQZFcToE0B+kiSB8e43W2YJu2FemJN\nQ4FZQZEukLhDdBlw/13/ym+C0p3nb361kjk1DJK+GJ9AU5DzT6sxwBg2qkGptRFyBOGEglUTnFrR\nfgNOhVPMTaTIDI8xly3iuwcETN7lHv0RjGkUD67OqODI/H7SJhnsFU64qqUVBkB/z4tKKBomU/8o\njiEYwYJMrfyNecxRceCFSFApY1eRfp0IcdHPp96fwDV14adp5jy8BMXb/2o/d/q+9JurgdM7R8TK\nJ2jOpAOuNj2L+Nk+w6OfPg9nUek5msaF/mKWlUg64gf4RJM/oLyA3j0kCJEvvhjsbeic7iQgVuHd\nb+uJVhlsTfLmqTjHubUUL8jdyhw1yffwksC7NUi+g7vERzSnTH1C7TuYYRYgm1JfnPH9G/peMyhT\nmLoYiv5se/pOdDK2syw7Wzm2ELPGdYfitcWgnpJi+IhREW3bMWtwLEuTeU4mklk+vWPl4ioYobY6\nliOaGyfZS8HFTNRgsfBUwIxYyggU6ITxPJnLiJjx2xaw91Fb2Ox11tEZr2IepxZyXMNUGHc0N/wx\nj1SKwZcovK3oddPhdNtVJ4kLN/RplSANKHJUEc+9r1ckAKkbfYaSArUPymrFkVHT0q2LslHiwHza\nuHCUkR/M0L22Fc4lG92sPvS93FLKhixbUW1Tg9R5lL3GzepXsNhZnMU8q4wamWM+y6ZULIYbNOk8\n+GErHh78Sx8aRgXkzcheTEDk3qda3xmQqJ6y4YHfd715vzzIvIOpIaMpyMDMXzqpKjQ1aYoYye9u\nf9W/00mmkjn7cWfuBcmbFlBYqaNJ1pC3KRU2Csefr6gtAlBM/fOWfWOK0mDM64Lj+NyxVKgCAFez\nlmRTEv0Rsgxo91pcX1oN2GXOymjSmGQZGNtWq1D1S+00UKSMpyYlEElw8jzurC+LvmvmnKHWu91x\niK2NTqOooh6iT7OeMxtLLKt/R4mZpQOXy+fhvVYOIIRwFUTzgwO3rsLNho8+bLCeaWbLnsq9Upy0\nVZbWCPoUJEHJdPT9nXySgpE9VCuYoee9SrVUFLCG+5+QgcmaZiC7K9VT8aqzIlqLGg3EjfeY9e3Y\nc2a+g+YnAA+OOMfoGPkoJuOjxpN4WbXPgny8yYfH/r5IB1PRiJMNTro8fOlei7TMdZUuEsF+OJIE\nCRMUCl50e+QCom6Ch7onXkb7tfXO4crDl6bpuHVxM8ftSfaEwTxHNKMbqQkSrS6Ron4YBEQapXKJ\nV8P3xNwlUpmKNaQWs4xXJaBvl6gjTBmwP17+/bWN0V62gZkXIV8+w6frkxnzpx4NTtjnuvZ/8x+t\n2/6+LmT7KySltIarJ3H3YYApUBhLYUvJmZ+pT9zabSF64/E2wdSUw1bAAPtC5dxUdSdkT+guA9YK\nwWp5+zYxSQfeBZtT9CoJqAzo/fkCHyPzAqhSRJX/Nv/qr6VXfxte53aYzVZY0hbPXCe3VAwBKqA5\nJ+9+KPD3jyY3okzzTsGbSpB1YZGJAfER7J+6AjovcGfBKASCdV9wr42qAimeF1UNY+zUyuiFuJHe\nfoz6OXQ87J5I84UdRZwXQrRIMPUyApJ903i+JMItjymfdPn2AX9tDZct7T0UdA/98IWdACbMwD79\nrUfmkVAYVLTlVURtp/DdRSDtOpgzuKdrz1k8YjjufATBhYS4SltKFpgUabVmiENBiRxndJy3zKEy\n1IOpkem7n9hx7JGpXkZnr81nhmYoTpeHllkvN/4D4309QX69ESJvV1GrUDLrtJueHgdUZ+GhHtRY\nynbiwgXh1rnhYS6Auis49Be2Hm2hxhUqiriejZ2U7tKp0Ue5Nr0XYs4mT6aAg8KyXcHImz7Y8+RH\nkgYo7BlhBUeJfIwtwIoxrq+9vccPrra+Iw65dzsC6F1zp7x9uR9Bd+k7VEO5E6zxQFfwBw6wSxGn\nNZrGEOMbdcqOOteGdMbr8GLam1k9TwK8tD3Y72BNCi/w8qLyR4LJdQBpoTkrSeSlXo/kEH45OyMc\nzU2Q0Tc3ADefEl6XRq7IaxZHVM4WFlOBpGTExF/n9oSnxkzvUoEF70sq5s9CJzeHWSb1/Ah7oUTq\nBD5wBL3fWpKeTuju0jQAXFSG2dFj3nqN5RS4NX5Kdv157ca8IVjb2pvtkD/TJVwbkmtVkWhYQ/Ln\nKEaRX4Zf/EOGrMXOD4AJAQeictvb/YowPkTygBuxw5RmThO2PeIaz7tDHqFFsbKcNtoX1i5p9qmG\nTdUYLL6GmMgFwW/V2BUGfzON0yu6rIk+UJqP9rjCMqb1tUz08oznYIFL3Rw1Cx9w7rhykMhBMOc1\nqLkYGJXuMjAvXyz5MsuABDdr0HHke+r8BKH25OiQ7jCNavgYFgVl4e3ZUJ4v6vvBoMiHsQrbTwp0\nvCnOLg6SJHpnfDQTynFo54NLHDRDfBbwAOfRUE3hn40mglp+79hDl2TqYktrwtz+PGZEesQRgc8+\nebzCI0EVSZw2CoQkK4g4lJNYNAz2QtVlCFcVkymDbAUql1ybNm/Uj6P0pQUr4CGvcgaROy2UXXW5\n3lj4SHNUgzVPQQbHEFnk8t21MjCrOLruPoqy28ed3hpPd3455Ibb6uNFWV0me8ZRKcgGA032C0GI\nphtGrFUt+ewC6D5RFMCTif7+bFX8LYZMvi8l5nBYCINw0SFa15TndErSJrQ7uHmz029t6O+SBZu+\nyyeOVy2JuCb14/pw+N1PmAnbaidPGiq8R/4UsoiZYbh924AlZYDdH+woCpcNOcUYwO/CuXg5VwvW\nAVhJbjGlEY0YeFMnqpW41Xb7Wb7Oy5wDyGjKz30EuUNiIV1wDCwZvCRHQi14wAyA+o5aa1x1lWwp\netuBTWYQasISt/oZtztu5KOGozvwnqG04O04ZAk7hfYU1PH+z+hrdyd2qONpod7OfT+GdmrA4vJj\nA0YoSq3GZup0cJRKdicNrd0BiPYcEH12qyP0Gt7Q2F7iwaJpknCIXAJO2vbuwJ9W/wZ1XajlJQu+\ny2YDa0ufEmISbi2Tqs7LZQmfADXCVdTMlb/BVrYvj9EmYjhcJUb44zfH75+4b8ZHw/a5aE4tTzN5\nApYzumUNDutNktDLdrkdx3E3c3nBPFuorbNEucwBq55dvuFBvz9Zu/X7/zh5WIzYVlF+s8QhQFUI\nh4CHHw6Er6hLjEveOHgjOySS/YxX8eKp/x96pMxYa9GDyocp55cM0aQqxx5MEVzo5R/YKTqdxZuY\nfPwdu9hrT9iLTAZUTIXgCCh9RweGH1/o2y+zA92aoIy8sJtM+4ndB/LynJJDkYNmQ04aXXG/b0Ge\nKTq/cmBU2VyzVHNosDKD4Vs6WQNKPSVjSomeZLwVjftEQ2gdAgjhaiGSCrEwY1Wcnm9UUhpgcKvZ\nteO3Lj86XPN2/Kpd5JnIhW7LtZFphmAdWEa6ZGX5JaZ4Gdwmirgds9rFgeJcUtIe33Xg3vAxOL7X\nF5fVs8Befve1q2QDgKzrflZPaq1e90B3tue5/MYvleVU6jm6K8kxf/q3njbcL8Qnx59YygzdYA4x\nb3+2c2Z7vrMJpJ8unxQfBEtUIoOcWAKF9d2ixdfDqYdt0leqPzSPvFCxFEHr0OilVcA0GDA2P0oR\nhImzb8tJZZJ4NqtEvEtav7H6VtwPcGFzg7xzPce8GbEsEIM4mrHbo6M2YiI9n19LFc/Mry2b1vCw\n2SeoXmnrPBqQXlgQwRyVl75u3IY0/Og/COM98voeGd+NbY+m3k3l1bILGAkGrvrmXfdKnpx0Zoc5\nr5o8r9LSsUdHPX80AH5KYowEFGDyF7UHEVyGN5vRC5w8QWdZ9hLhMxnTTPgYoeQFfY9NrF/wO24k\natL4kL+XLLzZM7dix71N+bBMgaTeDEXLIaRD6EvzBtu8AC4BfT2ywU8KSYtU65uwPyVsLMKKBIFr\nwROWeVGhKZXyxF61HJehpxD4YLjL7Zum2cSIByGHzh+E3+wISzr0XUx45RnxA3yBl1NWHGSXWQAi\nW2UkK3vFp9JdYPxEMQ1rUSYWID5LJwRPD9M9REMzrhgO2YPDI24erTX7kPEgNVIohMDAXzd+YQ7Y\nlZ3Gm4VH6J7BNvnB4oX1pr44u1H3Zt9+eN0V9S1P5heRUNv9ZydIGxIvI95iU04lhK63EJePHQ4M\nukbif+k1z6p9VN4m22RS2HfAzty2xZsuOeatrE5G2I+oKwolaG32BLtZmJufsSbhJlKFuOmnOzpN\nnQ4PmpalOjGM+7O0iERET4JMHTd8DMKOEdLvcbESd4+W2yEFsX3HMUqxh0oF2VHe/IdkgtCgKjrd\nV3FN31cfcTCp0FekwOu7nVJFtAssI982AF1eW8T/J+2ZwstcZeDCwLtPmfnc65Sr5Qu7136muElD\n++NE+iZnh/+phn4MA+v89LmMByrAnywXNpgBYfy/GFZUlsWRgG5BdYj0gJvaJx9ofugELelVJf4q\nq/T/i2ZFtcx2Qtp+r2Qdyvj2CjnOJS5RruvpR4yDa36mOgnWU6kx0cjx3XygpWjFYO6U4jXVCr2n\ni2y+7w5qgTKIo9BS9SwkTKGpIZplChHIZ8uUYuezbLVxvyZ/ImcoK9v38ae4guafgVqO1PHxtejy\nvINFMlDugQ9wVJxuzEPaDY+0dik/57tiKxnx7xal7+p8EqyX2GM2FKxkpz92a3QVQ83y8s0+HZMM\nKnMw5vPmFZxiH3HiOOy3N3WlmLnvK645bPvy+kgvsPWJDiqZTwlBtaf+vrSXuG0I1FhSwVJaqTFx\nUi7RL5Osv0LSoaqMWIFgQI4NqyTsUXMu5nzmXxR45E4RMsRyiZI0hwOeAa8Feyp2nff0TCYPB3PD\nmVegNwOS+mRqkqRBn+zu/5vTVigqq5uASCbdKr/MGT2xjYHsaN23Qgnm8BWhM1RmvHRoouhGaOPV\n9dnFR2Tf8NNcis83U0Ilm4rGcneTnWtTIdTWuNN2QAWNlSEgJMjiKcOzNi9XcRMI2wKphsBfaHok\nFGPI3mZuF03S2RlSbJ4EtVEGqGIHjH5qBeDe2I1hWCH8oIEPEDoDMQvzvqAkM6Bi4KzulzSJEFT6\nkBK1PjP3ulZn/MD46uP84vfv4VfquIYyTMDOYllrZHiDGbv+5YIp+BOmcRWzyt86ck8Jf9+XnCiB\nimYm8CHL9PuaMUQLX0R5S27oe0bx7n/8B4hf2DpXCaFvaXQudxQ6NZrcxIl4dIoqNfJf6EDRDZ6W\nSNLOjXZQ1eYHIseXxnzkl5nDEDo4Lh5S3IOHFdsUOTtXfK9zs1r6FlV1pvb7ddWkI2bq/eKZJOnl\nEOcN6i0ewGkMko9wRWNO3QImlBX6kouZXZxRUKNmDcr372C4X6ssfoFEtWU45O6hzNEMJ6l6ZXbs\nRQ/IG+qOCDdQdDfL6gpFKAHrLrPviYqCYmLEpwTK/RH6rw4Y1L3V3+VRAq2CIOk48fWxK2fWxNah\n2VA/M/7opLegi5hs7N+1gBAgGB5IUZj3gLu2zfmXZ4dNqBslGdMg9ZPJ9vo+uxHVPJiKvLN9EEHe\nVMDP7zAM1aawjOHvqE3dx597i4CbIibZfiK1sXNaUw2YuBneVn7/3pafxk4UADaB4i2MzlZnPin1\nhjslSuQfqE5ev92+395I5nR9ePvcE3+Z5ySPpBB1cNnEOUR+6gy/OPBCHWNYZn+0yCCCpzwg8lcU\neUq3rNyBENr7VvzbB3RllPQy87i8T2SqLD0Vhxh5ZE6Q5RWy7mjk2Onhr5SGuyJjlww7CYpzEOQj\nGXc3EmnaMH2Cn2THU52yIsfVxdM9UO5mwgoGWd4dZKrE1cPko1L+tEEuMC7PKxsF3KtpFlJqjSPv\nNLbhdKUxhCsm8gMC+7lnNPnP+A1nvY8rcG85MnrOulICpkIkurDli60m/KxmPb7E5i9vU53wDF66\ndetEqpaSfVzDiDqm+XuZzvpCfeDIuxFmsIrWseu/Ji33fBdf9qjo/3Yhczso98XRgGpK5pN3u3Sf\nGvMjuuyXPWih5+cfRSdY/l9H8C0BnoE/jvTT0vtE5+8daJbVixqtBIcFt/30GELUen+U1Im2LZ/4\nTVPUcgbxgwBOIRzj/jYVyIz9DToHZ0iVKwSkLOHbK3ToAIffitYz6vg7DnxOYcjWqncsbMYHcPSd\nkOAHEygv9YTbH7fnRDOfaf6J0mqeNEiszXi/5qMM8x4Ln0RfLmBxltoRHXMfGgwv9IaggWA8VI70\nA6duvpG/n78X9+G18JBp1NbrN6pUOPA511sXd8SFo8UVTNbe/nkPlCKTqGya7H3mnloWe8fITQeA\njlRwJ4kmUHzgR0+95ocJvN4hF5WHo88P6vyjn6nULNZH/6PKCOMdSELaisYhE9ldhvahQiLe6I0U\n2fQ5JvZB32+x1LbH9OThae3WlmCh6iuNe9pgVJOlyzvaC2MRyK9G2PTJm86sOMxHgGF82MDXVg62\n5cSW2kKuxP3BEiJo6cHuKUVCoYkvj+6t1zQ7kUJlEI/lBRWqWPcswNOeacGAZZ7JaVmoTo4atR6G\nRLOVusLS+nUE+SQJSs1Wm36aGn/vpFo+WWDZrrzve/g9yYO5Zs/5mZT+3+WGnOMe5nk10x9I0/6q\n1WM+ZLDNITnGVPFwvrjOA/N08lz3ZEZD6rrIV0jbyiW8wgMi1sDAZa4tHkKtbnb4Hb7IQm6pHlf4\nUbX1LwEvC2KMf4S7fwnVeHQuQtuP4zb7LOsYW/Sow+Z0lsZFRGmcjFHHq2HURer0nES9oK+JyMbX\nSXUjHNUswphRovSUS/Pa62RifMiO+gt5CRDUcO5RGBLQ2yaGdkJvqO9EqnYNKeD3eoHmpLqr9Tle\nHifGwzc88H+kY1+ct3mxKYKrXmWimD5JNmiZUXfbUFXColf5AKEkiOSOSmskcq23RIiiRIfMM5vL\nGsK6d+swn2S6WK09vPi3k91FVmubRh9js30yMAvEGNe+bh3C8js9v6qGhLqzdToNjl4Md+zKrlCJ\nOIcRguDusnoqR7R/ZLJANPgF+5edm0jLw4Y/br15IR1TE4Q6WUc4mAnGKTeXcjaKpnOiZ5SlEvtX\nxpO1yIWF4kKcXd3eVK1TvJjjp9dtqTx2WsHWaAu0mPFCaeZqXZEy36dpb61C6ZD9/yF3zl30/i9q\nXm+Rxzv5M0KOclOFqpfyn3jzKavpdMojoxbKQeZZHH3VgouTA8NTizclCVNE1tv870iMSWko0N6n\nOmcOiEnVv9pSq7PL/4rxmRADaC8nmNDymzRyTYiPlArhJRMtny5NBoYlKmrnDs8fCAGi0zlZDgTo\nC6PnxopRXWnJQkjoMBLOFSct0qw3LVB3uiYuDFJTiM/MPqybCVrg+NNRiy3X6cSGmw6FoX7kWNJP\ntgRkIcivaINkHZsv0HmlCYBG0bMy4vo7Rhjgm/vXBBP+UbY/XDy/OgoC9O5co+U2dYHM5lMnffF1\ny9QyocbXP7lh58GLxYnttrp4NNlIAOiLj0sf9HfUqmbZWFfJ/nUvFVflUW6ozlv3iK+w8G6AYP7o\n8lHiX4uBrdceRbtQJ8uFnqPqHSKcmVgGsn3WgzeknjnLNx7fd0gwoKCn/QTT7RmsbGMId7LrdCWt\nV0lZr3OG+Ecgrdw8pwPmThyiAPfehr/OEFs6+zcVBRj5f+uzUqXlPfeg6cbTxV+JKEbXoidkUYNh\nHDE4muIHRKkpkSbWH9M9X8KVLrlgpmf9oW9/sC8wKKvjtEakOkigKHM0tTr1kXBVWD/ioTeDy2Zj\nWdcHI6gsX7oOmUGvfwohbHH2Xo69b78Wq7AqpHiGUK3/uM5JVcaBIgrUq4Z53KD8nM+zBtAlbM6q\nE1RGrI9rVCJBGTCRIPv01bi0ccguI8gPb34KYSnJs9R5QU3dp7PSNBWeOD2CzXvPziMB8KcDoqQM\nA/MbTq9tuLpFySqOvlXTBkjF7iUTyOhsK1jqmWr4gaGU1n8EpaHXrVARmf/zGmLbb5ahLeHiUkPh\nJihN+En+kGk1HcxUtX0K7GKfzvc8DQD/FPAL+nmjnJ4523kcRl/3YA8xV1IQ2UO6P+YWpxAR8yF0\nw3LYediWRXbIIjAZ/lffDPbVc5CWsW37xIL4vPclGW1v3VuUBZlJIoRvPUOFglNMPQknD6zbRSag\nTFMcdPgHEGBy4EbynBMDWeZfy8ubMIoh1eMHj/evejDzcxPGqBOSrcx/vuYvCjriFI1+dzyZBzm7\nXqFUUoY1GLDYHnkJStJZD8II2q/9Ls2rIa38yny9JQYZOT0TtUPtQQA7pXRv6pOp3DEuc3lTka+0\nhBEpYxc4dLIZrOlYLXI1P99fjgrlea5bQ3s0KwAYdDewcJnBrM/bYhmi8S1KSg7tvFLJJyrjIvcX\nZQhDPyyWfHcaBJ5KeXsld5XiMoK07xGtc55+aGpmg1yMtJD2AVnSsiQZqFkCPIrf2nmK1r4JB0ft\nvux2gjGfpk0XHoVGTjwxiZJMKL1mwSY2gGujFNBbBD9AP9+vSvmmRVj9TjW+vzkqxZbsMMMJZ0m5\nFX/JhtzXdEhpzrgrnLggqeSt6z7nKmASnNP/QCfp6a1JKf1R5HH+pzkLlJ6X5TFYJgAx84JSIKk6\nVLsVWg6QPfvrjq+AqXiskW36HvtGcTVD7iVRxQM/yXtaQug1JFztsU3oEwq+Jw9g/capW8zgi12v\n4bt8ng2YnVnX1zZ6zzSow9jyWglUj3p/J6rsBkZzF6rGJU2x9refXOxad61ZHjgl9BTdDxf8Bexa\n/D5a2yGV0KsuAulAzOPfa/hALRFwulps1QTuVPt2BaJnfjtjHgl1Q3dCfjsIIIazUN3fmTrHrD1i\nTVk4wNJo5Y26KJ6wYgsIaT4zLSSL80aTGTJRpXI8pN85sAbQuA2eXLcV524HVROeE+k1dCPBpm+A\nCNt8zpPB5DjNoTSlYOyukZqb42i2BzANV6U2RSghv72eKlAqXp/jseJfWXuMqtHx7UDs+xrG391C\nzkDkY/z+PPktw61t4iwAn6/+0qolrD5Xj1mWxydEtK9RH1sef8jWovL3FVrOc+jFyyWA6hwahJOc\nABe8EljRYdrB6WJj+4Yl2MgQbUxRLSZhbp1xsjIPh5dhw81smowhKcbyCaTBAvCGBB7au/KJqtZr\nV5b5aF2RBffQtN3peayR6VFdapYbVHwbNwKmlvtIXuvQDOqZqQs0uPARqN9h2SEgp9IobsOQdmSL\nhk+2f0q+ngCEmLAW9McfmjVw5C3JbTl4Um9uyOVMp74TQ97WWw6FxkjVx4zBb4XxA5grvn8jdHK+\nYxm+YcCI4ycM0ZBSLQZqjAs9jYlW1n8zjZIAM6ySmYNM1htLjtnig+LWsayVkc7kqVojqNfV9AjS\nUA/uCTG2+IpBa8ZvLeFSNl39NWCNna5il59gOpGaxzigoeZ3YQF2N21r+gu4ZsIAqQshCgMxxyQV\n0tC9oJaxm5Z8tHpOHG8fnsQ6GNyZ4bXJIT9tzWhWe2vLr1SN4q8gHEQpNaz/gz6lPIAqirEP5Rwu\nuL+tKiDbvJnE5qpdXBCBPoLSzcmGMr4G3ynx9cPTtTHt0FK/mddjoATeYdJSSd4YG8JL+0dv4Qhd\nXizI03LtAl1Cia/USvjW5F8i8ueS97CI5vWT2EBLWXfUlkBht7KjykN5NEBs3640DW0OZwds3wsH\nX3D9HgBuQ8XnKbwarrwFyEGFK0UZC2EDbQ3mq3jzSMM30ymF/9tbUYAVxPkA70JDNOOnKGJ82Ly9\nVOLJAMJlGu9HFetXlXXkWzR/7ZsoDJUrSt2uzEdCYKT4GUSeRZlEGmL7c5CHYXMYd3Ij764VZQqC\n56evIMSer5EtSA/lM7x2WTveC8bpWMIWHLchUpSJdVodsUSKMtVZD4YGp2HaWYIzVPbl7yay0ZdG\nZGFYnOvJwNeewWqr/mX0UNP+UbBm7U/40mbcL5krygvun/WK4ZR+wu3/g22Yb1oqsJEhJ/dZyhPq\nglGuFfigldiCSd7rIg4pIWJD77DUIZ0cJsZdbANglQjduAtx7Rx3HNHyE4Mwxxog/NNQjvHi3KYq\npo9EMkv8DzR+ziaR0WhaalUYtc8LykMVFbPqy2XP1SHHWAHUAe9WzV/Rf+Bh3sfcB3e5S614hZBc\nwNNM682Jsh4zW5dSRwEAbUJs97BbYTQDl1gffHjJ2OFEM+/3LMd6IGF8MWMdDF69atsMqtbyaEuR\n30gweEHR+4+EBK0ylvzgXnY1NRhJkLPfEvtt5UhYD9ax0YW0h3w6khoGEfIuFd0+cvNlyDT3+aYE\na1lqzZpZqiE1Ddeyr/NKWm8lbmwoDqWu7cjPZy71yrUmAljitoRaC9jxLT/qmILQuA94VPs3btCf\nIvuXd/sUQRJYLyYiUqDqQXigWj7xn5tf6UGimMg+bV5OqhYg1ZlbSVtQ3CwD1yNgOuPiDo8x/P81\n2Mn64jodO03sg1bf8M5x6adzH0pcsyK+WBS8CHX+6u8YDyhZK3vjelmejsO+trMENKuO1wLepmyp\nufnCbSywb89DwRkcNabKCMjYpP2vPRSdvp10oTjrZtHJy/iQBVzYhNTDljPr6G8YntoCigzkMofS\nFmR4cjNua0eGR/wmxdOGiVa1nMg2l3OuE7MwM73n51p+vtUJ4EbkquXxCzp3M5P2OCjsJ1o+ghYE\nFS2vlHRgLLiyDyT+BU+7RQqfRADolRHGlb9wkJ5qH9XQAUOSxzDdLhsEEnrjHs1FgOzv2PMRK8tA\ntndAm05oq9I+hmAsfCvRH1J9pGI9OElz1vY3D8jLt0b2Cd0Zplz1p76DBQu3JwQDthtvqpf5nh7T\n6oTH4acwOPhFtxHYC5gqxKfx70x2HL/m8ynXlIrsLiDKa4sZbSsupCDZCHYOaJ79Ce6wW/c7ZmrY\nNYGPosgYVSCgD+IWqVgTmcpJK4NdhTMIlU+hqeW4cqqwb66o+B70ImNIj8bNI1p3IvUsOBzY2VYG\ncjzK3QVvo9iyqE5ge52kmN/zm8E7v+Hrx5Dp6ha37EFGkmc8j2TyVHpv27TzY51aRk5JZmTr8lIu\ns2WSIgLhDUgTJ2/WebMal6uTiE6aFGGVHK7Ay84jDCQ3JvnT9AHwj9pbtcS9YaFnuExVVSfNb/hV\nJPjBQdPC1I8QSgy3A7w/qYsps079J6X8MlbGNLXlcqzSzeK97dmxEBlfA6v+NF8z53W3/LblRmDO\nvwgx9OCOMKADYs5JITvuqXPsc55AqBqtofS+gDADa+WC3zxKe4GfPZ3IQ0NgEcwi/j7TNV48OXA8\niCiOBjA1NDz9v+9T4MxEctzPLN0ucY0dbpsu5yzYfiZW0bS3JQOY2e1aXdJiM3EkjURPYhGzKJ/F\nIKGvhEchQpVvPieM0TK5Xab+eqknM02C+PDwtSZMe+/HfAhsi0LK21wJTECnJGzmpcBVZIvyNMIB\niXFxwqyDUXn/Oeo5G9OFZbPuMfO3xf8D27ffJ/FTgusqh3iZPRyGnWGKKs09QPAL8hR9/muCcn4C\nCqYDHcBp9M85J81O1FJmkZsQntFqWWsiSR/VMO91733YLDPZFX5Uqm8Wyb3JEGWy902IROVTi+EK\noJ7UTITNnN3iY+f4hjVS9SYfhXW7Wsm9yj1OO3J4SAD68bc5yptLd1k1tzavthbTII0VFNYnvE4s\nQ2EgFAzk707leSMR67aaEsyOXFUz/WiheCTtfR4zYx0wVaNw0wY8WMUeF6SP8MulOF3f07W9d6Tv\nWsjJ5L0Pp+Ly6zztxVc+MVNqzhuraI/I8umqm3oH1mG+3Rh+++c1yC41I4EZ+dDimJKrR+3egrON\nkFJpktqowreq/mN/niz/ytkZtRkbdlpV7FKsNx9dWSKUmvOTw+z893gBZJnkHRlCqqms5aibXLR3\nKeko0+WOEM+5Owcax0M10peS+G45873aVPhvnjokFFmkttAowj5KCueGqUhXh17/F3WfwYyKCkEs\nScZzvj8ODpSLOeO1WrDtYAxN9xdDrBxFA0Ipxw9epkrplopQI6kcZN0KhRNp5gZqmLadkjEC2cjn\nsY3NqmVLlAyq+rWbpO0JajQrgClt/FWEB5wM6sZiDemQC5/StastgtM2Sh+Nh/ADTe1lgqUJMZbc\nuxF/MJ6n32Y8+1UZPsxoOLZ+nlehq+oivHz6CGzjKigY/YENlTyx5aA/b2BeUHdrs6mONSEgg97M\nFlawZ/xJOy0kp0VDu8RwjlUrMC0UXh9tQXuXTBTRWqBlfkr8CTo81AUupSdEz3RDR18egnvVUqEk\nUTnXvP1xC4nZb0ActlxiobHz5IVEg93UeVNZN409Ds95+2r+a6rsY2/QG5K0/rFoJ976hzobqjCX\n4KfNERR8Ez7gvDgQ/37iOX8NvsRA40+ozZrW9uz+ECecChRHrd6vqqBa912Nqm51pJq5ZPAy1xxG\nYiuj7cSzbDhvtgE6JkX27PRf2rjhqD4oe/kcWUv6/vBiT0FKXrKIuOmdu2s0MJLunOi074Jc6SQb\nmXu/Z/SqDbhq33GyDnPkyOhEa4cDVi3Js6a5kzp3kKgxQAl/3VTJIWN70O3ituCjLPCuHOT+jbCY\nLMQUoHt9T1bGofSnyR6ZQ7YYqYAzUCGV5HSWHb7AHxxiKyDa/z7w6bbfDGMbe74mrvqt/kRWeDKV\n966NGWhLAgKHmbrKKocaJzQLWB6lfE4oU6ofzkhrcLZHu5EdMZNiSSzU0hDJzr2nWwdVHwnutI0Q\nB4YHHC3nm1xeknFYiV80Z+aqrEQWq502E0kOP729V9At77AgtzIWh6RoLg/UfOPzrSkVEnZfqPHt\n2kICgwzTf/VhV8QFJOH5tKGH5I5xnDFA4dOO6Fy3EM1WTi5iHF2MkXPg8JQyUGY6E9eMEonvHVL1\nL43XYJEg1BSBqyhOL7zCo4dzXQqBzYVhyD5R3nIUDRsssjrKZu6bAanHGDi58n8i1bes2svS6Z1W\nc9WOBzsh91YaDdMc3hUiHkFZQwTRNAE4Xm1t8OTqYirmiLIpAsA8SEdwUHOyqsD4XCdLrPOYpy5C\nOA9EsociZM4mmmYKrpPIGGoVZnO2zgE0sGXLAeby0nw8Gzf556kVURTNxeFyYa9QxdMC79rowcZR\nwIipbJgHabJTaxucIeuUgmApi3eXSZZnH8zhSrYNtouvndvKjymsdvH7qzcib9VVfAcYrM3fgX5z\nKXfygu/KBCka3UA+s5ijhmJmLSWV8odfi4DqK8PFIY9438+IK4IbPTwaUigJasmDZaVS+RYysA0i\nzCYPogjI1DWgWEVkS8uu/wmHz2rl/IVa3NwYjtUm8aOxLtsNcHr5uRRa73SDmhd2qABwb0A1R1rK\nj+P/nf6/cUxBssQlqy0sBwKBlPTy2CVvhFZEGx4myCfFCYOgYbxCBPixcpmtSoWJpvlgkItALIWd\nSH48cR5ObSgKmwKCPdvNntPa+/w6/2GGLC1bkqs6j3RZZGjpJ1fgBN7eDc02QiVf2B+ZRQSPKkhJ\n/3+JaJyH5oZ1PO4lSDxhWepKgky9q4aHr6hnHQl7E3fOUtfOgmeaEp1chVvo9GHZTap3s5eJMZfl\nwjkjcODIcd8u1JnZIUEcS8NFuRfhDt58fFwQRnoyImyFcfnNvdlzP4d42o8FsXtGGbN7A73FMtAd\n8miRBM0hn6HEvz7YrybP5fOgHEIS4V663p12hyLPN6GYvm4VQcYsg+dq8ArZu9wD/2SK3rk21khy\nivxPQHPCwG4Mp8k3mRiJ4w9Xjm8KwNhNRSOuy6T6IcE4J8EGOVsN1XUi0k5mvjL0NYGXlzOB9Wf8\nH85pxZIkl2VPpNwi/ZMTAR4ilDzu5eNjH19nR4GveGY3Kz6RYznF4C08SaRGkO0CuWeMiVLIBMai\nL9D2m+Rj6D1LN41jnDMrP1hH1l85ybiwi+vrZJ7q9f/jlb7KyXFNwybt9/xKQtpA1346wJb443CV\no+byI7Ecl8oufc9/8DA/t49k\n`pragma protect end_protected\n", "num_lines": 4960}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nSS96R7wwFQ/awBJYajmb1uyxVW7Dxe+Arw4icTEGgmn49jUuwRsWmvS+gH97qfjXRux0tm4UqqDx\ntyk4/LtkUg==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nA+Z7s4sYG1dC1S/OLd5onaqChDDoqDKxIH0wDyu0FbLuPuh2W2mXAUgA6ygUDyPxGR1xLs3AnLf5\n3U/y+fEPvjbByjgXYRdoaB1qwaS5zdnv6ZIRFF0LC1q8dbQM70j2RSMZ6Bs31wvj0c4OYXETbX2h\nDtNML4rTAuRM+iAVpLk=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\np880H0PUjXmUBTEI3c/dRMxRl/IL+XvlWrRVCBPlh6HVE/9bghIS/wvhgyOQ1mp4fyEUGZHgNQPX\n25j3cqsyfDCSGvVGO/rQ3RvIhdjhXBbmfxZXGx5UxofTc+/fp7JQTUPxhKk+Zmp3B6J8UpkkRaQ+\nTlbH9Glza9Jhze+cKRbGwVPrfS4Rk6pzkwHnm+iB+WGLJnSJVBVgXGfhp+ygbrBv+U3zrTXgsOb3\nxSJhSd/AWJ+PCYXQ27sJJr74LZYIQx/gg5QzMyTEoCqxw75cGP3bD2xXz+cFe0EdDkJH8sFvd1LG\n7SPcDQ9xmFnq3WPw2Ghv6DnJe4/yMXGiVRDxCw==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nej7XPZ5hWPkq70QwibQmqqDg1SWNzBrsMbYSFestfs+BR9J7xzmVMkCeifHuWqh/wSvpJXMW8pOX\n6HsD+kakwLfs8E+v/+QJqlLtBdlE3y4Pqmiw2GNPbakNzU8DMNQXOTe2AmJmoqO1VEHW3S//PRDJ\nqs4qvgIM1HXRfRRIgECiAHz7eGE358gw007G2YwbitOL3cveSqDocjOGV3jV5HepWYKXINH11Reh\nBMkGynjTuYTMJY/92mdl1ZV87kDCsW8+FHqKhOA1FfPvj1RPIfsKuqgUkZvW2pAYk5eBuA+vJEkN\nxVCniFgVwsrAdlKrWnw46FoutQ+m90CDu8Kygg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nLMe3TxzR1Zx/ByHI5/w6/SqhTVkyqBbjVaIILoDGOy4Y/RehV35vNFgESx+MOdmetaV1j08wlqer\nDz3Rfr2Gfq6hgHMLEHPCaIF/5SymT5AVpwhkmFaQdge1sI373fv8K78kRC8JGM9DNSFOClhGJDQC\nXB+yastK7IXkt+VYwM7nXa0xSHywkBIAeivPY/BwBX8XfbLzv9zV6rh2SAW84YIp2jb4kcYm1Mqj\nYgWPATpqkdqbBqii+7aziLQkRP/MSmF7cT5UKQiHxn/Ns1lKMenELV8RgHq6jdkdBs1uaoi1JQKQ\nfqmUv9kYnWWDKWW+rc0V9APlL62HYOLDnbo4+Q==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nq6xSi+pTFm18WzGq+65YbFhiK1j9sHarfxu6mSyjDniOO2/jW7gfvXXrv+B56wzSE9P0346jIlVL\n/B4h/Z+ac0SVqu+wV8pg+OJDyBvWhtnNYZI/7k1BSUWzzR6flVJw+lEcue42YZ9yoX/3JUlz26Zq\nBi2/4jMu3LmppUWsrAo=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nOQtIJXostrr6X7QDA+MBULvA7CIKk70kDF2hMqsQ2sI/8QR9LMuap/TXdjn0XLAZTkxLKNLqD11T\nxAlasu0+U1hOXgMBxoOPU/EUG1bM7wR1UF83Qhigm2Qm0c5xtp78LF89EgU/YOJtHjCcMSpExbax\nGFg3QnSgmE/7yqaeLbA8DKDWxW05qT8jxOwcDuZ3zIdkL3n1NxrWQjM3U5py6K5PTmC+vcoEptq+\n7ZI2ka+SP+NX5R9IadM4lpUB6CqAxroG6xIUBcSx5r2BQ2CrzH4EcZiQVNCUwYx8tyBREplKIsC0\no21e6uMpC5pDqqckCzSWGZns3l40rTQV8PP6hQ==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25328)\n`pragma protect data_block\nomU0F4cB12yO2ZdV+t8D/whbbDWmycZw/StDHYdtlxBQqHD2Rt979k5WQq+7+dcCL3+IPJmrHRVW\nGmVBB+3psg2CMKD8dWV8+f1duqdQ1ruc9IDTn3kyrMv8WzUZr2BsXVR7LoT/8ARttZYBzN9SlXOB\nIu5fROLcXGXIC69mZclXZ3kqw6gKbDdcIPTYaARyazI1N1JT6MpiPeX0B2e9dgibZS4NLoFf1C+8\n4lKKRF3P6Ms14sMsxNaM1rVifA4iQ/Ak5XeKnn27tB72RmlJm4ojRMRkD7cqreK6a2V7DXB0zAWw\nD7/HzKVzqh1lZF/69Z53r8BDyCI3oRPiIo9/2kpnZMcnV87uI6FNq1UsblfLwnFVkv2E1TroogPQ\noUVZd48nZKP6G3hipN1IkHU5wYHpG7S1px7d8HSx5vZKl3pFpv28aN5BxEuhvJV9FBghlpwG57HM\nQYhtJs3QjvuUXcTQo6mt6uaJkEmGMltqmMlwvreBEPDAzXivRCwBt4lZjduB8i1eYRSuMv0nI/Qx\noswjFa0lFt6divro4C8AxVAJIiIIEzOrht0zHz9Ss0+qCELQPEGk5lc3IDAHgjbCPWmObsbEidaS\nx7t0E/Jz7yoYsInuJGfETjIEklMYJJhVHJH1GgtFiwCDIXtjIG7Sv93vg8+dTBX2fVHjOswe3xhc\nlJcoB8yU+RvIb4FuwVwKcNAPT/0Py8wp2Pis/gDA1dsSpGioBjVoz90+AOI7ltbVQYEYqMCTLtJ8\nFmzXBx2tt+iWxg+co9z8phmO8gLRzjKzWoLbGSZBBw7G+/VWR6G6lGo4ZvKAtDdFvu3H0Lk06rJW\nTeOr2wSeT/Kd+gQCC8o2Cf/8PyI3xP+tzcDP+L/jkEdaFrHo2Z7v+LzFwcprHqiZldZmlCwK78ks\nVjmAujF9tHZe3H3Y+tr78xko8hSvvPzSklNvrskK6bA6f7i7LNvPXEu3FV0hY4/9kDRar+ls9hff\nDSRygqt1uAtTYP/7REZfujc+wsurY+MbzHHxp6jq3EOwSgRyL2cHXx4Vmo62A7wgKyTWk5EdPIPd\nr6n847VMqI15sXBo8nYyLWEkzrNVtVQEvWpeA5oqeDEHaduoNXyXlyRSwDv0duY7A3m1BAFlglvR\n0N2sjqwWzKhYFj5Ns5HQQBtHh9Zw21QqT1laFBjSz7cAsrFrpDoB8SDQCefHnKEzSHYnfb3WRQQs\nxCjXR4TlJRnLnZMyHVfyYtH7USi2/l9V/Yrd/PO4+NmUgdIxGbToTlQIBx5gigJGs0XoaWvVskwf\nNXlK3UaoOJ85tDPYp9Ejz86GyMYerWLlf1u9Hn1BCIDeuOMqiHVvTkLMoY2uQf/g9NOChlcWM+hW\n5AZH9uc91mLwBKTrHi1k4EM6CVoDhS5i88eLGDj7WUosHcAYcjaiNhkZ97tZbVK3yKkVFEtdjoL7\nh4Bum8rQwYxHNx2gWytbEbl8qIT1k0uisTMGRDOmApn7rixESdulVbMR9qGrvrPLqY8EtDH7jJY1\nlS+kchhLcPKLemI+liKF7h5VSUNsc+PGwK4Poi/2EFa7XfIpHc8E6l0gZt+qwW+qsA4aH16FPrxe\nsPlGeRTRqQDdA2OwzUgpbcvKx2JTx5qswVjgMW5mHt2EnLjW6SHvLc/Vzy7fr/O3kiV3uy4dyWGO\noloO64jspiFBJnLbb6eaTNqyAvbpj+ZF/Bw+QrCdIb0EdsWj9GmUUmsmiWLI+Lz81KUCzEc4H+Hh\nGglDloivAeynD9N8HFp8OpgQFagNeWtfAonUqCDV3B+hsNXo+x3Nj49PDKdY5aesqlaahKr1fAHT\nfierHFNbvOT41MYGioKDQPLwon8ptmydyahnP5MmlDi3knIlULZ8de+mnbKISNCyvzua9eAc994K\n6B4Kj8/swf/hAOZxTJ+HqtpK/DgmCA9FiU3JYIsSB3rhufuLP+mFayZ1tK7d2t3i+FZt7TbMxR3w\nuZgEVxQBf6VU4vQ+r6EHuytjSggM/20/7CtQ6JVqeRD65+i4n1E7b/yeCapiKyLEHcF5+TolHg4N\n2IN8M3DjZGThrN/W4aFXsyj4YqaVr87z3w3GM8FGp7rDv5JqVehoF+ATrA0OcYRvBVPsgnnvlPOg\nWuMIIahHuKGHwW50zPwsNaUod1E2fk8gLhkqMqiE3SQU2y1T3hmK6MZXN9GSwJ5IIw5eyyO1FWGr\nbcgG3rsONmih7ecMwUp42jLQ5vSszqiQ+yHXepZzC0e2VcYZhWWEGgQ2qAP/mX+y+xDfZ5e//Dp9\n1vw1SwFlk48f3CJcsRXrWfDocPNxPWQEcFtYDHSPNwEAWpRDWrd1jQdLRZ7riiKEwygrvCTBTy66\nWshkAAe+V5my9AeXa0Ml2QTFJnaGjonlt4LTbDpP6lrDNO48TxYvwTeeqfPcLaHr0uKQt7YHP6Lz\niQFo8+yjuc0zEfQzoaETRrimF1qol1PWK3Qpfih9XrskpouGoT/zEL9vl3TEyQopv4PUZPj0Ynk5\ngLrEEhd5zkdYa0GWHcoa4Fot3qrp3UwIaXp3J0srL6FzrCXbDBf2Mo5NN+P8lk095AJm7GbHDjvE\ncDphpGwBKdvmbBEGbh6fHIOHTAhf+Vc8cPPX6BHmHbNOHZD0JlWZppGdjhHNpBNPnIBYS3tfqeR0\nfpgTvVPYXHmM322F7ZoQ/fwObdQAoj+tk3q0RroBJxQWakMIeQLVoja31p0u56OMldxuQgfF/7kr\npJIVirx6SAQcDVwcFSqf13qBuM+0Ol/D3mNr7ZjwWtpprSUZlH21ailV+zw2WyvthkiTp8YWVQBy\n1q09ZacNze6Y1ElACgh58iPN4woxeuIgISJzdoXdZHKr2rmaCQ72e80pFTsQDzTlRLDVRkpqAnDC\nxN+Mwpe+Fkm7f7w6HD9kr73bageDnyHcFZXpA468LRFJPWYg6wq9iFZ4TJAxrhk7MUFsxJtUscnr\nxLex9FDXv5JNgmR/UE/CD/ih5AN+x6gWb6/W3lszhJtU5l4b4IoAIBzFNDGa48+PO6Tl/fTG2S7N\nNWLwVUe5S3/022dgOuBphepqPGBaEk9aWfzhttADsYbd+EEH0DLjYEUNdOy0L0wxxD+dTHWxJZSV\n0ChMWF8mHSAFDH5fO+Hy1cRtVcPIRrjGMzyyvJjDaKoXzOfyN4HKL0d2Zjm/gFo8lez/ydTkt/CS\nxYar4AEGp/BN7QDDP5IH+BMU2l+zrhxqwQPo4bLd65LBxuQDXhUginwDEo82bBweomEKB5ujxPvH\nkuKtvrIWHrfWIsK10kpV2kY1erMU26KgDhIsF6eqON5qRijRBS4IWa4trUlIKxFe0tR1G+0lTAnA\n2b2zENNs3Owv+ZV3WgEeJpcYOOwbsG7qq3snQYse5j0ltcLyBO+dYgzePpcE55rg3YWCCn4hjKVN\n0vSNNutZw9QqsPBhK0qUZEvot0e3Awajv6HKZPq73c6PpUOaaFCTRl7V70cOsdlrUwteXMQJV3F3\n1Qszx9GyIwFkBAfl5tn7jsQzd2tUlf+3rxISOSF4by79j8FsMlkJW+++qk29OrwkSW/XexL+uk5x\nDWSc2fgm68pygKu/3KtuFKMEnPktko2ej3qtKmVvRPolck9fuCxtkXDMY/lRA/cMCbVJdOST8PNH\nltx8N3OjAHjF7qztXIGEbTgETs6qdtIS8Aaec2vMw8sZrpkkrCd83yeYgg89AlK1PMMWYpKw37mq\nTeNpJu+HCa81ry2c3bCvCvpF74Sll6oEliNJLH1QXvcQWLSiz6bAPjPvZNysBOkqwipQO7FIFujc\nH1i9gsKzAISZqDQ4COwcFkxKsZqQ+3+9LWF/SyoBGXGllUl7fn6Y1xtEzEcb3vTq2Sqz32OVeKu+\nLWl+IaE2DFDUpnM3NlaxYilLHTm/OtF29z+8txLIi56qb1wlsAsobeLHB8KpgUKsEzE/Edpzr+k4\nykpmm8XtbKx+rz1FpVqtx7C8k4J7ebUClTt9AaE+jJujIyeR6IIX9uzQBNiB2+o2Tb4XsG9P9SMb\nGbauD0yjImseltwlb22KCPcxWEUe2/7VOir1DkE9/wbtk6Q8eF02TJxwTZv/epiH8p09Zns7H33/\ngS6CyE0neXPK839SOHGZCftWF36xqrP1yS17/OA6PI3s/CTLfTs7YTx2codFR4imZz29y71VIoEB\nxtUhCuqGobdRNa2lmU42q3mPHQLOU1UisLPDeDI8qxbUi5FfabTKeFW8+xirZfgTs10x10q7KGnp\nbd0QGVaqot1rOHQ0HlG1SiSDeBp+s8HaYAdx9PmjO4bwDtiQdZ0aMJafmmYAYDSiRxKXnWvwtwJv\nkDDIMdqVSgH9shOr2WCOVuD4hebJ4kxzvxLQQYK3OsKY1CUdS6LMg1EBJ5fzEPsGHi2w0Eh2srkc\nkFRoCpIPylVJ01RZzkM7BHiJ7SsmbDucJMBZCFb8KFsmi6QZ4vhiXdTczreE7AXWtxd2/bUiG4vk\n+rP8o411sER8+1SpV3MujyYSJIwyGRA97P3vw8pDfsF+Ktr4FQ1M5S/UvCCDYU1c1fwEXhRTig9x\n8kRj/i/4u19Y7f8pW+4TRIfXSmqpxQLvlViUn89CBFT6NLiVqBHxzowlhoWrhi5zpYXxw5SRXBPZ\nsPxr44yLN8Onh2QMGqi/H00xNhG5pB31BEfTeuisYQiVZsCmsDMNFCZSUIZJ/+qQK5aL6ASPafTH\n35NsiMMmEtBVPcun5MPDeCi/5Yak2R3SSylLb62ucpJCFEiNSW9XXihs4lvRiD0m9Q35QHQaqlWN\na8FAdZpgxcb9I9bO7md4qPV/TFLA9Fbfw/ttXdf1LSjH9WiYpKiNsii9ttBH1On7jV9IE5ZlK9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G9UB4lpGFa3EvQQylVj7gEIapdNZX+/KvWDE1Uw+Mx1ch19lMWPerej3V2JsR60z8FZDuZBI\nrMa1yIuu3scJW/W9+zxr1+L71th+wD0N0930H0FW77WXKD73hpu0itMeJl1kTLX0C+4du/oXwiPP\nkKFMnSlhnmADk5Nzs4kXX56QHHCbRnr6eMuvZblXK0EZHGXSb4pQePS8267+j8iT4e78/dD60NSn\n3kcUWmiDaD6B8DhgaHuHl3jgJoT7tgyerSxV1v1ywnD+ooBqWrUAsYnJXP35pM9lvw9shjKGAAX7\njCObOS8VJZci9eTJcmygBtQacBP0AzSh8d0ZMgtsEerarYOHl0VaqrURAHTNs1zfXZ6atogVW572\naPtBaqUaUJB4BnKzRoP+YM/+HbN+k5jn6HFPg/wFHeOOsIPE4dpfWM76Fj9OndYwBoJrRfjLOqsu\n4QbnGR3BRAD5bq9p9CIqMna7zaj6r1Kh8y3bz0JLMChWeZWjoOnjrSOb3n0S0OcprlGZwIkSPhD9\n5e7JOYw8xSO/acOGMOr7XhVwxsvj5N71yDY9oIIxCmp2i5mKFvjdFKT7b3ivsMqpU6ooUNL1cB3B\nct1l8a3kFj0xj3Vjz0ipLbKBkR/JC+iOtZk5LGHDKd1jaSTRl9nSuO+bV9kLdDxwvYHAm3PP+PD+\nzXW0fPnQVICDYqkZG1xto1it9QOrHjy2vBNh/0ETekywdX5BIejkFzloAAm2ddh6NFnynQ81RPOp\nB6Ei5sZhxqlniMTJQNFN+PNXyW2lrwNTLew+TNDyj9rIZ6ETik2SHQpVEwsfSVmzfDCWqm0kta9i\nAjvtzWWnW+IsuGEsEL2hoy4He54jqi2mtn5jgFPt8o/zfixB4kuNpqBIoSoWJqkPuB6IQ/KJWlFC\nszg1J5hey/xx856i3HzxFJd9mVXALJY1cvYVCa3JSMQEP0sUcICrI0GoEYQ7pi3w1mAa8bB78jMD\nrfvLju0deZS0V3tBedhCRm9yt9XbJCp1F+62+qLtP8hSRUC/gOs9rvVULoMDmyAEgrf1nsbcBaRM\nQX/2dEMQzcBUd2mMjdpR0nCeJ5oxvFymHSOvlBYVhLq4CaROMreoChqIuejDpaErVFOfvu3lq30l\ngiYyAdBlGI+/GenmbO8fLK2EtGigHy8pIzuFQvaj350cfHLlcO2jHrl6UbUnMLdM/S+aBXd2Dg2E\nFKbI8PeZwIJrbP6987aJSwhWKLNgMNNjCkUqfYJ/NRB2eSOiC40TgfhufZuYh1fA7Q32tdQqW/Xy\nNv5slA2fH5SgHmwS9Uqxfc4jvp7SUOc7EToDWJKkVHzNtxfk+PpKRbG7gledErTqMBqWRm7rkwhC\n3jsX/qzzTT0uawrfLEtK5qRoYxdoZzMRcK6ix0rVWema9+AZIkOkf2eQ1XIts9qHSuNKuze2RXJt\n7XTiojoorg+kyigvlSv1D+o8cAQrd78YiWvhEj0QphJmFmC6jy6xpe/6eGwfy0a+fsjgc0ZCdt0o\nA4sV8eOhNsGrSsGhMLickahQrinsXh/8ILbGqvKtKAbNVNLyJk+6w9BTy8HoYPwRccXIahYFpgS0\n7pjDe1Gyor2dlKT72Rs9SvooqSu5tkPK3AFc6o8oQIzNtMx5dKNBHmDyeQntb/GTk8d4H6TAExAo\nsrSIFYwaxyXWQsgbStzgbi1/n6R3kvBFDAMD9ttwZ4hmPlj4sygAgzv6c6CfyuMZpH/keY20cVAJ\nOXijLo3hPgVD0p4n6FOUdu/JYgrTsHnOzGhUcEGws6R51FcuHxqXcBA57apz8QY31Jr8lbuhCmpj\nTNvGlI0SX6VE/NSoJli7V68oxvxAR58toqGrfJU+/YwnuIenC07xeN+mOIKyGO3P+4F7UuNDCPYH\nseoQxJua5/0RsZTGA9NHNAdpXJzze6l0n52PzQItK4epiSZiE7ZHGKz1YfRLvAFBrpIT1ArDhLFw\ndOB1iZgy9GNqwH8pNMvbfuz/+FeP1oM8/SIDdLSv0WDwM33gsrenitpREzjdByQjjFRtunJe2kyk\neQ4GhszWY0Dhm3qNNUlvlMc0xXvIiPl/w/QE8JJ6KgtMUdzTXgWd43HK+VjPyg1yJm9SC1+o6xlP\npEt6awJB3VCzxpu7jVf2OMsrQjiF4W728yfUJwPQUfr7VR2E97zmjsbiHbf1fo14acawqG5MHQW2\nZsMwfep7N5NAIX5rav2q5ZC3g9rfOUVkwnvp2F1HSNOWxKV+jJz7B6Xb5o+YhzoDd2Y3u9mZF/cD\n14Q3uTuV9Y/ufXtAhC372DYtV4oSeLNkdvW+eOTDr/k0eKWqnidKW9xIeLpCtmtUEhv+gSYNMZ4u\ndj1KJgp7/bMQMYReDRLQJIZTkcDnKvrEc8ObcYZ4GV1OwvpdWTtkiszhRjsUWD4YA3ir81byw1gt\nZKff6VWwZakXMdmcY0gcEhHqjdELSZFplYxqXNFX4LV5x+7eFjRz0S0IbvsVKlu5RD/Stma5/ZA9\nG5dOyFeuG5u5jQ1wu149LA4HvM0m0lg8BEG1MMOo9vjgOYEgfRz3sYRtSz2M+SnoWlt+o73somiM\nS8u+Sfiz3Nyg1GNSWlT3LLhfK8pxIEkDKkLPjRDkvjsBfkIr9jYYnK4PjvOHmKaPH0ZTSQzVm4M/\nvMz48765bXGQd4xL77svOl5rK8uyJoMmyQq76t/aXV1iCMNLgIiZDHa9eodbgsJTeLDB92bf3zgb\nkHDPhp/5Y96aH08BelfvO9ZsntgDvmOi0++IymB9PI2l3eMx8LjleptsWU81WDExuENmSPn5b9V7\nww0PkB4L+OrwEVDHPmgQvzOp/S5lY86506IzyZk+EFaoisJPL4Ix7TXgo7u2wHc8Kssp0X5YZFj+\ntUOk8kYsuNRrd81CR6V+ukNkM89t+W4aw/ajKDTT0LmUqRhMGQvh2hOqw9UksTCdMr6/WgIz5pbm\nKniZXfCh3cMZu2TysZd0Gmg/MbZ6ohsBnlsnrft6p/E88NNo66e9qomw1v7eVWGswqmbDwalyPv1\nxBVjkSxrxfkyLQB1YfibsLY/wqmdq7CHSlB0eY3D5meq6O7XDf7jcjnKVJ3lnx8bvmKf6aT8I1cj\nHtPVm31bdpptslWZUHTXnDl5VYP4NJJQN/JJQ+GcRra/Ik+SxQ4vqTeRuhOtQb3NjBm4FpDEKSSH\nj3/IaA/l3KdxVNAbLRenx7/pEnd94HpKkLGiH9J++D+WtogNWlV5Ran0qN9ZVxtMgYRQ2CfhS+M8\nOoVZJYYvVWBFHmhz0Mng5gkK7LODy7ij23SNkqmbfMzeniulSE1jAHHSIgqxdMSNQ4Q4AwN1m4YH\nQ/xsFz07AK9LzQIQDv7U9Wr+nglKxlsXV4hcMSdcPHy6cOcH1+LQihIVUm4XUhH+8jEFRcwVzbKI\nGfP3Qa4PE3o6CHTTLgjitYN9jl/G7Y4dTuIWbIu9jgPWY/Z9eP0EIIj0WKWsFBD24E/QTfUUgNxH\nGe1uU+XisJ+7XHwnFN1GVgqCja43OyD+CIWdiYhsTWjUgpJ5E0fxc+AHqzHFY2a9Xj1wfDPyxyoA\nW1S9e0KjBPXF8hTpLMATGsbXCltlAQxJlttlBFZKCCAsI7R5cW+xpMyW/mU7SgBUJ2lPHybFdvIS\n/kkKwhO/kHKUXCYtD5Fvgg33/UXIA8UcEHrhUraEik9Cv0YEmwcEdEM+b6CMPDjwUqHMLLWJvB/r\nYZOfvrPtNP97tOh+Gzilb3WkMDsLHUw1HwbErVEhj11lziLbaej7JqgEO9/M8AC27Al7FXaRqDYP\nCuxwoB43b8tGyEmDFLCCjC8Kk1ztEP/gVA+n8Q5l5sev/rTz30Zxgwc5ZZ1d227+TLCP21iPo4O/\n1ZwVEJ0/mri5mBLBOP3qpG1jjuxhpb6xsDRuvbXY/bu6nxERErD1bIVcywy+vBTa65irGR6PBNhZ\nRLtGiZQ9eVfYdXcOnzksALgbMY3RihTlYwNLoDhz/KfMFGTo/3Gah8gk4zf8cCFZO+jFWjQ7l6nV\nZaFpZHFkxLWZxdn+9jKXsFEObkKPKJ01RmnwsIrgcszIiDb5qUx41z0djy6IcBO0+CJ2IigVN/XL\nADeVMeG/d55n0yNPBJtXwU0HxKtT95amNObp/i3V/o7cGrc1TfIfD6ucXn6RtcPGYh6v6pTh0wsn\nmitC17c2iHIWWU/b1+kGcN6VSOkti/66NmUcNWTQHUiQ2I/pD8RWfbxqGNXn2QQhSwST+hAve3p9\n3CqIBPuTqPwBNNWr2jH6IeaRn3adw9H+MCX1QYAF7v/zF2gaYnQVDTduzTN25/V8vUg4lPbOQqG8\n2KCc8NqRPN+trTzRMrh0HIeK8q/+G6pncDXe3PngfyXmfFpCIJUF9RiAs4/J/Yu4ZUd7Nso57o+9\nIA6EVndlXVZlK6nkkZRzhAdYfso8SfpArimn/HYTgGUpfs35MOvKk7zmKqXAxPZkcurMVQ01YS8u\nONptVvI0ZpoDxl/FyLoSGTPo0BzKwwj4UnI6xVjdsT0V5swbEFntLW9IArikjcP7AbfVyOXSats6\nTNoO3qGEve+FXkt/onl8a41AgCWlL00twIoOs6AasHipMeQkOgS0ipUaGjDKcn5ceCWM6+jm2JdC\npbP+MOMtLYYdCyLcULAkhpPwRQIkGQeDcRnsPAjuZWfUHPBWkwkzIHYn2fDi84yh2FvppMqxrLWH\ntNcrGlgWvpHDCdojVWATJI60DjXrYDvJwXNW2kNUC6ZIBr917ItTlQ5surQtNdLCMVKXEWoQNU7q\n5vXU4Cj19Cb84ao5ZpC1dWAI/CNtZyV+9D8HsSf1oISFMRwY4cOAnTDekXrOj/Zj/1qLeXU0HPw/\nuyNcYPiG2qitycy1Df7+/FuFDukKiLkrUsbkdvhOeFQ/LOBWfbBPtNd3m+/57kevqzQpwSQ3q1JL\nAfhHcE29kLQb6ZkrFywzimdO1QUhQLrDxd2C7A+H+0ErTsLOBt8mTIf0bHXUMG8jo8SF3fH3dcW0\ni9VqjocNa8gvtiDGpX4ejz2/hkdEgc50Nsogn1Yop21X8oNvDFJ9Z+2S46IilYBArzBIMhPc7GK7\nTzaIknEGcVckL+lip1TqCZOkxBQdWju+T9/x2rLovnQJScWz/DRT3QKfMf117zA83RxVQrZxfQw4\n15AcEPVUkobhsGOyWd/uonrJ18Chkp6zj8VX8Ha5smr+QpVq3eLzlb9br/VOnrAnUSZ0bvPvjQl1\nI6+lK7EaYF1Lef2z/LfRBTYgqXAewf3nzpmM0wdzIBK4+WCChRBH25ieuAj6DhGU/4dNd5iYkNKw\n5UFjIH0w/7U/+ugyHgDp+nC6JDYtfubj0m0KJJ87RJMmQ1mTNarOu0urmlikkD7+HDMSgYyLEtuQ\nGaSH5vSHsJNe1baNRTA9VZqhlK0zAIBSMEOEhwUqnE1As8+bX9mBFw1Yisk7M/bpzK1mIF1ayLiJ\nGtRL+mvAF7ogzydkw6AZq49ZnkRye/Rc3FSP0qOsX0GAdCjMyaPoSZ919BBXkDatQplglrL5Ap7G\nC9SnQ+UEph9gWx619N+OqIaVd0Sy4GHMXVNXZoWzCGStmOBFx5wU/Whmf+CQQC00fC5T2zyRX0X3\n8TKMKhvJpwWVNtsQv13de3iiNlO1r33Rr6Rz90IILkiLnaaOlZn0gsuUdQQFv5nAq9ZklwQU7St0\nUuSwd+CMyM3cBpYc0HdW3qNwu+ekYlkNKdIFoJ3e0E7qqdNgrYC3Gf12pJiH4lzbRTPZeJzMtMiJ\nS/W+W2H7pW8uOJhZtvIHy/r6/12etJ58zmR/j3PTISTH+55NnYBSGQhXfLN/PrZxEkqeUV44ke+K\ntGWb4cvQD9qBtaL/2JvQzWdwPwTNnq/VOMDHujxwxkazRZQLoavtItyYdaNm1gt8xEzjW2jnxkHL\n7KbB5ZaBXIktxcKqBK64RnziU/bgmFdkLltLuHI55XJSKFd6m/eTU2FmwVMg2rvrgS5i4TwtpL/a\nrsSKWWQCHSIYhb9xTqrzYigYpHuKDjayBqK9+OuA2rTgDdKq9oaxyR/jXySiUxcDh6/az9/NMLQe\n+KGX2bvG3wWdxOs215xclv2w75gXDDOqmYINX+R6Roj/5aUgY1dVU4YCrTi6JGSdprum/c8R6r3K\nBuNzCsiwGCuC+B8q8n8awIiiACjqG/gTisr2FnyUMF19VU65vml2ClFxMEIgiDsG+7uVpVF7Ks5f\nybAZ75BxISPCu2Liw27/nEs4H4aIfBZFm9ffGbAJBal071TlBZhk4rtNqVmQHiEou4C/NvmxcFNm\nZdBkKqo+rmrY3o+/7PrhbZPAZmgUbjAtMHtVne+vge0EF0uj/h3Sq9/2W6bgen0xIv/fzQVSGlPd\n46ZekLfUr6UsLfTrPd3ZFy1yrg8VGInFaN11yTTkTPzcD5p6MzOwLm7UJp18wmNmjk/BlTQ1zvvg\n7e9NX6SRJyF7YdaKwCQYxTQKm5lvUiBxrCcChQJdg6/BG+zVTZT+8x5ShfbbzcXnrfZXMB1RKLuv\nQilDIlQD5VNRgP2K/nbYxsMDjoPRRuQduQ9AG2NyeDT3fGzcxnaUhF6cMSgXV18yfbNBKrl/ie0/\nH7CkmgeL55l3iV2HtsERAx5kEki5NSNovvtZ+jLzxOiuMFxGe2YRpHttIX0l9YscBYzcuESoumlj\nRp6KFFo224Mw8LZSYX0+QLN/W8SRrww56eKNDbbiVU8DBgXEWLXhS/1q/+SoMLbvnr00BDAfbScp\nMOlo9rgdLsOBwD90jQAAvWVk42DxTWfqs/2Q6sE5CHHDEeytdzchnA+2sHM1Ua5LyW8R735BypzF\nyS7tDnyBRxdi8fLOqvDT+LrkjyQsdeCPaZ5HyGpPW55Mmqg00U78uV99LQOwL3Lu+klhr205h/Vh\nyqRvrSBDsjXlBcERGNTb874qY4U2oIdRTqkR8JatCImB6tOG4z4OGkZnCaMespRfx0xh1h/b8c4U\n0m3cjfx+GyjuXBXKNzK0L5f26aA4HLeOMwHuQtRxmhUth92jdHCtkyV5fzbr19dt3PdWn+DnghNw\nmvRsWnJq1pTlpo9aeDt3NDSHra0iEsRfxb3UD9AeHjI0+AkahdLHzNLPRihKpE4llriErZtBC09Y\n1pZq82vu7ZAyYxw9UowxtlJZJ+RcLopN9S34fJ9APRQ66/uuYuD68W+7tTiTNyZHoKkS7FY1Uu6W\nHFyanD61UeLyH9apnXw9DwRQisUpKCy3q21CqCEiWvQ5+C/vy5qC2N8WwBSqj61aW1yQyiYWkBXO\n4xQU+j7sgnBN81KG0kSJXHWcFk/h7X4X1tLr5Ggr890jmGDv7DA+VzdZ7Q3fTJofXmuTIgU1iE0B\neJdgyl1EXsPbo7hUVFVd2EgQRtj3vkHwSCjFVF0gMLaNVf9LcazqIvW4HFFI2tt8+9MFEyenBEgB\nh2xqefXa5q97T4n7zl52mZa4apuhFg21ZyMgeHFgcvbyMJ+BkFVkeKcVVLVyBkZ33V1fcKy90Lv1\nEQIYUQyIACjaEpO+V8EzSUHzmbiWHkouuOe7aRlkH8lTQFjwNnFjhii5SN7T/HR2gqfQoRpSLNoX\n11xPlONY3eNXFfbyVaOKUMCenFuAqN4TTcGrdAeKnFQHvGSbS8wuxr0L6LwRRtmN25YOmq9n5BxF\npV9Chlz3Nhtm+6T4ei3j3vremc2G9BTq8PZ1YLQZqJRyh3Tb2IMQ23HCLb3yoQ4ZpPg1ZZNymmug\nVql8TPMelPFuU3IEXjpgy0SDbqUvZKcP5PKHTuVpdY5eRizzWbn7a6akaK67C//8IU6pBT6WkpLA\nVDG7HQ5KKlwvriaieUvWovcdt+7QusnnssrSWlMdK9jrZ82u9HUYHVKV8Xd5hDB1jYVu6Px36hQ2\n0v1g782llhV76QhcNlBHkDU2CsK3X555FSOcdMTD8BI+n5h0GROXkhSGlodgZTbWppO5QN3jaeWZ\n9a1HLU6dNMfTCEeOUe88KwDZPEFqSG4p0VtwrI863aJ04foZhZDyAjI1PDUNtgBZO2Oz+DJyhXaa\nKSEoR2Yj36JwX9JPzW8mkGxRb5Wx9N9I1/Szbje9t4KwPjOml4qWWpMqrBbpyrs2396STi4KCNLQ\n8dD2nwuApS26e6KvA3swEStkmcg4lPaHt73uL6N1VQxViQ2EEy4rbFy0S2AJzYqERyU+GtstUOcW\nh04cyB/2ofzso/h7nK59EXXXc8lmeFNNll2++rzh4sKZqQajxs/8Gcj65TLhk+uPqyAaFKmmSZeW\nd6jvCOCCgywB1EHAYOnOb9vwGGRCO3JGCLmC7QDTjTOm0FkqGoMUKYsee9Jqd+AtP+t17eVGuIVY\ntAr571S/EkWBcgDYPevACCxmnBp9OjNNBOskcVRUg5XMIim40rW6rv7bFDEDgpcXtBTw5dz7m505\nEJTbnrS+//j8NK4fgaIOl5bKD5x2qP1Z5CcPQc1rxLrkLFrTy8XlEptKXR0t1lQXd0Wkef55TxMT\nqs89vIeZfvIhprc2C9fK2RVjSYAhkj6Iu7TCimjFyr+HmsOsOQQZdQ50WNhAid1TjahlCJ9yCSM2\nSFk2oFhu/qBAvz5cPs0x6lrrRmRIoxvX3WA+IElb9TyFBPyP4BWdTcbfqnQ6XGDijou91uAVawoD\n27aFmoq2OCWPF/Fp+D8dcmb/XoPpK0SOEHaBU1ILRJkdRd6Ys4bq4isO3Sg8vkyA2iNcEZ2DtGkV\nH9IgbGEg1Mv8sPc/wjFMhb4BEqxNWQEKiYgDyA9+0VdYpJdy5X5gZnJxYxhzpEOLZpbbnjd3UeK0\nEKkNXwA41V21GqTZrrUlF76kn367l0KZTNgiNodIaDhxBkTPLMOtpDt75KoJ4Mrtz7HxeJXlUMLs\nj3HezUvOkrRldg1d/XonaIPRDgjcQFhIRTjOEald59tKjB5scFlrOqdI9zQycV4HLXdjifdfH/Dr\nfrQHwLor3niSXfIlsq9V9vLUCFDTNCRYzaE+LlNQbFITqmDUqy70neszXu3lowOaugZOrCx/xLiP\nss7Ja4qppT2Ctc13JZXtKVL6TKDel2VCx7xv0TxpPluSpiKZKUTQwzEb//Cf3o8HRx2YSwZM+kXo\ndb6T5DfBGcLWIujpgWhXW1i1aawHOLQMRqa/bpKAA5En4IfdYbHy0jt2k40ZG11elMVI6RKAtaZb\niRfZ9R5+Q/n0q/XlsbqpiOST0JUqHw3TQzIUl3a/GTAEM1B7E4/aXxOBXoEIBgR+lDXq59z+aZ6V\na/qDF6Cq85iXpIprWSu5PAw2ImEaHr3kZMg5pBYq2xjpYIX0L+FWB+/rlaegVs8JRRX8w7TjuPiI\nldwrcr8nj1s9l18z3ZjIvvfO6i9F8v61PVCGw+cJMCffOL1DUXz2/A4LdTO0Qq63fsJBzfrwNPyM\n4L9m0il1+TVxHhXVoSuSoXNhiIJbWut7GbW+rvTCQJjWk9HIPTN9xKxKFZsH/oRcWIyUI3ogahdW\nH9NEjMeVGwKaYqs85ai7US4jnVmxeYqc6sL6b4AI8zQW9lDAoyygkqC5NsuGZrbk5/GwdIpbCUza\nlV4lvoWrT2nzlCPdE7HqdofSVI/GPQ7EIhG0S9jqrL83rET779F7bWP9oFwAM3WXq2FD3zm2vtbh\nc2dLOEuB32W9sPfobiDEuqaCkrDTI60b+AgewQJcZ9mzktJhauyA5bDFxm/U0ffkqJaEswDtl8AD\nmAo2U8WeHnyMJEqkxx5ld5cLyF2UAMmCM6lGPtpgvknUUkNYs/lD2XhqxuM3cNCLZuvieJKxtFvM\nLbd0bNRMCX6bSVLjKfv+IW0WDBrtuJ17aCr50G1IvprZKzT/xRPVIu0p6p8hNH4953J/ghs9oo7c\nlKQ8loRvT6zSp3GyffPZJOVn9gu8lInMpJwWkFydpk0q/59aiHDXSoigjSM50xfZkM2xB7PXVYTd\nQEfibQ8bp33CVYbaynaCCaQqHVGy+9ML5q0Dsu1Mgs7ttCcpp3W5akyYcO5d8+GUxBMUe0sNq4tl\npVZNNwltEOiqD+QngAx6UkKw0PCg2lxyNyCQZ/E/symhb7OauoiCzQZVF02qMdopaQmGiY/ODvoh\nYtacenkASzgbBSOk0fOO8SsKAaWfuD6KRT0n8bSgZSPboejfoQpVOEmcxM1fFfIbZn60elHh0TWB\nclK+JftnN+AWkwQfTB/JKniwZ+lvqCsuieW1NmyUSR7ykBcRXXSA/0az0coEL/9bCmUeJje42E7X\n3q948+DGDEJc3wvWBANApYi3T8dvHoSv/xB3Sg3uVrCc6Q+vzOhQ1zgvY16rPkvBghqXZg4f/ibO\nGUrA30eB9dJYQkpT6sAhBVevG7t2YLCNsCNH/EpX88wA24JkJNBICyrhs/fbTQI5l86rmfxDybaZ\nV+C5cLUfrLvS74A9KOm8LzImz38+RE9naZuWIUwEKZtI/IqDkLJksZiw7jp+r1Rt7CnpJ9kUQ/ZY\nxwC6FwKaMOPLuelslAkGiig+MUGK8U8q/0wzWTJQgRZBSfu2Md+jmJQdLrdN4HfPGddtNg/rkqpZ\nGnTqmDTCNZHKaKyh8av5iZgAl4C5nsLhKmLgbbDFzsnrzKEv/IoHy9a2gtR2q2q9+ZmZ+TI9YeuG\nVfTbvZgjNKN+nNiL2kT1tpRoHf07mpdAkuAWMrXqddkcn9QyHYLlNOp0dRup0GM1yx0nHY/0hNZS\ngSJkzkBSDJu8fLjwG48jloXCrLjLGo/IUBDwOwUhyCk9ZJtLg5AefO1JndkWU33X+0y1xJGhoK6X\nt6FG7I4nyaqrsoFB6Ha0+UWSqsM/H+hyWWejJpBaI5nHPEZBbLwwaVm10hAFZdZ7oWB2Ve0Dbnyc\npOrPOVUmWOxTiIt5+hkylvrkGu1sQfRU1kBh7ynYIRKOvgljxP/AY0TI7Xs5ZxGJEJn2Y2H1PseT\nxvStZw5RwT5vYJxk/4tT+g9K3BU0LtE0UyGwpIDNlHpLPIT6CIYXNO/GC6vUfCrJh3qh8Pnyd0sX\nNEktZgvb5zGBYxGF46EU9bBwCX0s84fJ97aaxn/gTVv0Hcwq3cUb7U35uO5LHLjrlnUCh29jH0C4\nldzTqhf4Ch9XicZ/uJPVEONESBUmYskm2Y4EuudYmwvVcwEKCAOpmOVSfIHqvjU6EtHuvL2cdO8D\nx41OztnDd/549tkkn/p5SAcs25RZf0vBjrsl9Y1Iezqa3V8z0ZhE3rNUhNB5Oon2IkuC0Rvvltt0\np98veNeUyJDoO2k+hmaWflAEhX1e1RCZNLYx0xSquZxXD0VeaFUEObTKXdejMa7v597GFmoVPkPh\nYKH6ST9ati0TjVdJf+dNVqBRcaHkEzJcAMZLSdNRhPRTOB8J2OM71ealSLZ2lR31089Zlq2QZNaj\nK/viSQPz9ANHmXy4Y9WozP0JCYvMvkRgeF6hmpUEozNEh6efj09VSvAQ80lRJEP4pkFKJoahZ3Wh\nsGB5Z+pR90jHHKeMmQM6lKnUbSlr5YUmqeaSnY2FH60mUkKudlzklCc093iBPlN9fpdkbyQYXbZx\nfa5JtVZLHRLhAJVlIE/gR0js7KeS6d9pKkTFPRPbBwhFPPmZ1TZH//Z99ZlfRf0puhG2nMjqC8Aj\npYZlQ3yB3QR4fmEtLxIjdpY2/IsBNuR4WMI9P7scb/3S9L29X8bwzpVCBQy6WgdogzCZwX/KSInT\nqudwNMs34MHNXvRRBpzB4PVypZOD2LPg4A/JFwAe4PaD7f12CqAISeKEDLQJ8mgfGXEgYzOkRrI/\n3+YV8GNHuTH111rUwy5EO/xyhuMQCnKcUeTbg4hNXfYVdHTr/rsDNAhZg4RfYg2qBoBQblA+Hgoh\nkbvSH9IxR3JbuZGgoS9Dtsr3ichy2pHeO+wsbz1+EFBXE2+Nv1o27Ctl9YTjZy1FkA4F4DugCwI5\nJwmp4CSxlR5V9SDaFHV+Vu1TwBdQY3ttVnuAN6i7awhN1Ad1tIIaF8TH5pERQd5S0fYyxWgjLhn9\npHWVDFC2G+fhIL3BhQUohuHk4oCLQ6L5awnrPPLRqRn4zQDlebCN+fK9J0gdnvHyNyYQ/kaeXF9x\n4QhjVofyFnwwGIIh+pEx3UggaiMCTfm12/JPErbaC2cWkqNJaBKJ+kZUBwTutslEOVEue6ZPibBC\nlvVbw1M+zU3xyPx4SY/MzPQav6MEvRbaT7aTZcFf9la1TtyYvLgsQIB+uB1Jki8vLi6HOMcBThQv\nemw1tXDJlwv/TYh78mMNpllnTGG2prieiBG9cResrv5mEZRJS1RjRyTk9AGQ9GaqTIs0MAVikqco\neK2iSkNM0GWEjHtSluZrD/SzfyYXZsSzJKzD/RmeX2pJmqBaZ1KHgSOzUJC3O6GAQiLE2SDYrQfc\noA14lbLXgYldDUXJX5nrM6EhnNcaT5xBYelhPiqIG/qOsAt4HWOm3SdtK9P6COkCKAWUXhHTeukL\nmKEVwZsqRLRbu0SdhxgItkILQs0JHSpLRmuJfkmZgm53NthwkWNu2unlsZdzeNpVDXL9ilhT2iO1\nNH7HurARdw83ECxK3Who2IcWtdm9+cJ8LNR925XkNJKhHJhhQXGa4GesfJTlLwa0J3J1olAv7dJD\nIVeq5XnXOyW6gzhDzTpK2afgLW3Thq9EY8cM2oWk+vjabJ5i094lTotFRSv9B2lzbIuWBxF3JH0I\nudYhXIW6B9qFceaPBMQM793OUBQSBOi3WGu/Lm0k0FUyRzsTPr/9d1BRWD9b5YqxnWniN/mzDQmA\nYZpqnFuhZFS83FJ7EriLaOJXoisxsE2uVFxQZ7E3c0/WVyt9Pyk+Rq9vxE2c7PUmojV3Rewu3xgC\nHUxvS/q4yXuSWMwqLEbhRt8KyDGB2EcHrMGojI9A0ILuJiueXyd++NuiozOyn33QRNg79tDZH3mv\ni+8I7tqNxp3T0CfBA9QeH1tn6GHvkNBaiaZJ4ioqg2EiNpcbn5nNy33NT53S9uSlyB0Gzkqj9wf8\n0hR3wtkRcGA248PtuON0okzf7rE1mJDI5+hfpRgGyJjEbfJixeU7Lhk1PobdVkkGahSBtTqc2Ldk\noQMllEOGJTuXu46HY55ne9BLbK29u+3MMBz1KAZ58qKCo7sPv5eDsexOr/w3IGHx6Kdyme9VC4gI\nHpr/JGRH5gXt8I9AjgOObZ8YzWCs/KErnh5vKjYPgooq9PMFmD0MKcDUxefsPGCZbtJmcVefKM6h\nBlmVXH28KYc1/71keR1eZBOfhZN5H4IKnWJvnGSPEPWlNmkHDCmMBA/arDVDvUljsoTjFZDXP7T0\n+TjMu/o/7F+zMcZWiYKhgVKkKdWexgpiHXrV/jzlxFhT9fPcBL331pgw832rrR3zn2xBtdx3s/Ag\nK1Cob56W+pntouKPOSBv235PCfPB6A6/Ccw7rvfYZk8LHxle4Y1/PzsISmSD/LVo4cm/Exalc3bJ\n+jWv5iO6jmO2H94k1iA0Nv/3zHgy5iIpqr1Mv6JDpEAtk7Fh/Vh31tsj8vm7ypdcArVQLrZwKYjX\nULh2r6jJOaE8J4PZIgVVGLE9YOmo7BFmfeOhlhkettJhttRcLQdBg126cn1h07bgI2/R4A8FI5ux\nEaWY3u77/vSyaIdQhCF/P3CDABPg+NUyB2mOZkueZZLn5WcQXi/qsIaWa/tXDAGrSaNPF0BUpr0D\nNORQ2oB+sPYpR+iCKvBonHa0hnYsrGlwdwEsz3yguKJpXImkzHAzuYg4Liz6ePZcCW2ZhCSATfZC\nnsGKryGfcDacjk9bvdnNyM0GErMfMbCStu5PZ2r7tRBl+JAYLs0q4OUbr3pX0ne4yoJ31nWSCsl/\no6uk+txkgX3mufLWDGXeNyfaar2RWSKXXQNY1ypDhVTMGj8kPYvQq5HkaZ11Xme0QHgfuRwJqtqh\n8lzVdEQqR1iXV4T6JXENbyBJKTdtkWgcHSzL2s489b3ObCag7j8FPZT5bw+8FliIPY0yxkAr0cRR\ndaKSqx8MxxqntzyJSv66i46SMpCdBKRq0RxZxkv+pHlbESDlhJnZATCho6xuoLk3LI/X2BFR4VX0\numzxeRO/zPXvZWEFgvWb7vPucX5mlBx4j/13u9aZVNcv8qzODK5Tvgdgwc5TSSZq49U0v+9FJFNu\nvSxtSDPPL0b52168r8Kj8O5EgF745J7FdO8n+gu+ma79Qfo/v3LNezC1Q7phWk+RLwYWEB/fC44v\nDbkUkzn7niBiRc+gffcMBzcWNXXMg6ym6FHOMi+xkiVFXFvLIc39i1tT+PyocfD9Yf2DSG2WtUXb\nrExRkxKCe/O/375k4LLknHaBoJmB7m4FcgFZl6WZcgL7Ak78RhFXrmeGuxcuGW4b2njWh+RwOFuD\n1tPq/OWTREvGcq4/OCyOPhuOmLuJuFbKroZYZQKxLS9rTBBVudy8Lm6wygRT4cNoQgO0Ft6wE7Dk\nLVV5SkjkW1wCKNuC32+quUYlwToikg8OX9hqMxp8EAryEIAkhcYpC4+WBh682E/q+e3UzWLiutoy\nxserP8cf15U6aL4UT7nL/Nxmwhw6EzKtHC8JgJevouggntc2V+PvI6qi9bqstuyZu2ogmWkrB9O/\n0vwCkKjyNJMOY9w4Ltb+Jc3mm6sZ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protect end_protected\n", "num_lines": 510}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule vio_0 (\nclk,\nprobe_in0,probe_in1,probe_in2,probe_in3,\nprobe_out0,\nprobe_out1,\nprobe_out2,\nprobe_out3,\nprobe_out4,\nprobe_out5,\nprobe_out6\n);\n\ninput clk;\ninput [0 : 0] probe_in0;\ninput [0 : 0] probe_in1;\ninput [7 : 0] probe_in2;\ninput [15 : 0] probe_in3;\n\noutput reg [0 : 0] probe_out0 = 'h0 ;\noutput reg [0 : 0] probe_out1 = 'h0 ;\noutput reg [0 : 0] probe_out2 = 'h1 ;\noutput reg [0 : 0] probe_out3 = 'h0 ;\noutput reg [7 : 0] probe_out4 = 'h00 ;\noutput reg [15 : 0] probe_out5 = 'h0000 ;\noutput reg [15 : 0] probe_out6 = 'h0000 ;\n\n\nendmodule\n", "num_lines": 77}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n\n(* X_CORE_INFO = \"vio,Vivado 2017.4.op\" *)\n(* CHECK_LICENSE_TYPE = \"vio_0,vio,{}\" *)\n(* CORE_GENERATION_INFO = \"vio_0,vio,{x_ipProduct=Vivado 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TH=1,C_PROBE_IN211_WIDTH=1,C_PROBE_IN212_WIDTH=1,C_PROBE_IN213_WIDTH=1,C_PROBE_IN214_WIDTH=1,C_PROBE_IN215_WIDTH=1,C_PROBE_IN216_WIDTH=1,C_PROBE_IN217_WIDTH=1,C_PROBE_IN218_WIDTH=1,C_PROBE_IN219_WIDTH=1,C_PROBE_IN220_WIDTH=1,C_PROBE_IN221_WIDTH=1,C_PROBE_IN222_WIDTH=1,C_PROBE_IN223_WIDTH=1,C_PROBE_IN224_WIDTH=1,C_PROBE_IN225_WIDTH=1,C_PROBE_IN226_WIDTH=1,C_PROBE_IN227_WIDTH=1,C_PROBE_IN228_WIDTH=1,C_PROBE_IN229_WIDTH=1,C_PROBE_IN230_WIDTH=1,C_PROBE_IN231_WIDTH=1,C_PROBE_IN232_WIDTH=1,C_PROBE_IN233_WIDTH=1,C_PROBE_IN234_WIDTH=1,C_PROBE_IN235_WIDTH=1,C_PROBE_IN236_WIDTH=1,C_PROBE_IN237_WIDTH=1,C_PROBE_IN238_WIDTH=1,C_PROBE_IN239_WIDTH=1,C_PROBE_IN240_WIDTH=1,C_PROBE_IN241_WIDTH=1,C_PROBE_IN242_WIDTH=1,C_PROBE_IN243_WIDTH=1,C_PROBE_IN244_WIDTH=1,C_PROBE_IN245_WIDTH=1,C_PROBE_IN246_WIDTH=1,C_PROBE_IN247_WIDTH=1,C_PROBE_IN248_WIDTH=1,C_PROBE_IN249_WIDTH=1,C_PROBE_IN250_WIDTH=1,C_PROBE_IN251_WIDTH=1,C_PROBE_IN252_WIDTH=1,C_PROBE_IN253_WIDTH=1,C_PROBE_IN254_WIDTH=1,C_PROBE_IN255_WIDTH=1,C_PROBE_OUT0_WIDTH=1,C_PROBE_OUT1_WIDTH=1,C_PROBE_OUT2_WIDTH=1,C_PROBE_OUT3_WIDTH=1,C_PROBE_OUT4_WIDTH=8,C_PROBE_OUT5_WIDTH=16,C_PROBE_OUT6_WIDTH=16,C_PROBE_OUT7_WIDTH=1,C_PROBE_OUT8_WIDTH=1,C_PROBE_OUT9_WIDTH=1,C_PROBE_OUT10_WIDTH=1,C_PROBE_OUT11_WIDTH=1,C_PROBE_OUT12_WIDTH=1,C_PROBE_OUT13_WIDTH=1,C_PROBE_OUT14_WIDTH=1,C_PROBE_OUT15_WIDTH=1,C_PROBE_OUT16_WIDTH=1,\\\nC_PROBE_OUT17_WIDTH=1,C_PROBE_OUT18_WIDTH=1,C_PROBE_OUT19_WIDTH=1,C_PROBE_OUT20_WIDTH=1,C_PROBE_OUT21_WIDTH=1,C_PROBE_OUT22_WIDTH=1,C_PROBE_OUT23_WIDTH=1,C_PROBE_OUT24_WIDTH=1,C_PROBE_OUT25_WIDTH=1,C_PROBE_OUT26_WIDTH=1,C_PROBE_OUT27_WIDTH=1,C_PROBE_OUT28_WIDTH=1,C_PROBE_OUT29_WIDTH=1,C_PROBE_OUT30_WIDTH=1,C_PROBE_OUT31_WIDTH=1,C_PROBE_OUT32_WIDTH=1,C_PROBE_OUT33_WIDTH=1,C_PROBE_OUT34_WIDTH=1,C_PROBE_OUT35_WIDTH=1,C_PROBE_OUT36_WIDTH=1,C_PROBE_OUT37_WIDTH=1,C_PROBE_OUT38_WIDTH=1,C_PROBE_OUT39_WIDTH=1,C_PROBE_OUT40_WIDTH=1,C_PROBE_OUT41_WIDTH=1,C_PROBE_OUT42_WIDTH=1,C_PROBE_OUT43_WIDTH=1,C_PROBE_OUT44_WIDTH=1,C_PROBE_OUT45_WIDTH=1,C_PROBE_OUT46_WIDTH=1,C_PROBE_OUT47_WIDTH=1,C_PROBE_OUT48_WIDTH=1,C_PROBE_OUT49_WIDTH=1,C_PROBE_OUT50_WIDTH=1,C_PROBE_OUT51_WIDTH=1,C_PROBE_OUT52_WIDTH=1,C_PROBE_OUT53_WIDTH=1,C_PROBE_OUT54_WIDTH=1,C_PROBE_OUT55_WIDTH=1,C_PROBE_OUT56_WIDTH=1,C_PROBE_OUT57_WIDTH=1,C_PROBE_OUT58_WIDTH=1,C_PROBE_OUT59_WIDTH=1,C_PROBE_OUT60_WIDTH=1,C_PROBE_OUT61_WIDTH=1,C_PROBE_OUT62_WIDTH=1,C_PROBE_OUT63_WIDTH=1,C_PROBE_OUT64_WIDTH=1,C_PROBE_OUT65_WIDTH=1,C_PROBE_OUT66_WIDTH=1,C_PROBE_OUT67_WIDTH=1,C_PROBE_OUT68_WIDTH=1,C_PROBE_OUT69_WIDTH=1,C_PROBE_OUT70_WIDTH=1,C_PROBE_OUT71_WIDTH=1,C_PROBE_OUT72_WIDTH=1,C_PROBE_OUT73_WIDTH=1,C_PROBE_OUT74_WIDTH=1,C_PROBE_OUT75_WIDTH=1,C_PROBE_OUT76_WIDTH=1,C_PROBE_OUT77_WIDTH=1,C_PROBE_OUT78_WIDTH=1,C_PROBE_OUT79_WIDTH=1,C_PROBE_OUT80_WIDTH=1,C_PROBE_OUT81_WIDTH=1,C_PROBE_OUT82_WIDTH=1,C_PROBE_OUT83_WIDTH=1,C_PROBE_OUT84_WIDTH=1,C_PROBE_OUT85_WIDTH=1,C_PROBE_OUT86_WIDTH=1,C_PROBE_OUT87_WIDTH=1,C_PROBE_OUT88_WIDTH=1,C_PROBE_OUT89_WIDTH=1,C_PROBE_OUT90_WIDTH=1,C_PROBE_OUT91_WIDTH=1,C_PROBE_OUT92_WIDTH=1,C_PROBE_OUT93_WIDTH=1,C_PROBE_OUT94_WIDTH=1,C_PROBE_OUT95_WIDTH=1,C_PROBE_OUT96_WIDTH=1,C_PROBE_OUT97_WIDTH=1,C_PROBE_OUT98_WIDTH=1,C_PROBE_OUT99_WIDTH=1,C_PROBE_OUT100_WIDTH=1,C_PROBE_OUT101_WIDTH=1,C_PROBE_OUT102_WIDTH=1,C_PROBE_OUT103_WIDTH=1,C_PROBE_OUT104_WIDTH=1,C_PROBE_OUT105_WIDTH=1,C_PROBE_OUT106_WIDTH=1,C_PROBE_OUT107_WIDTH=1,C_PROBE_OUT108_WIDTH=1,C_PROBE_OUT109_WIDTH=1,C_PROBE_OUT110_WIDTH=1,C_PROBE_OUT111_WIDTH=1,C_PROBE_OUT112_WIDTH=1,C_PROBE_OUT113_WIDTH=1,C_PROBE_OUT114_WIDTH=1,C_PROBE_OUT115_WIDTH=1,C_PROBE_OUT116_WIDTH=1,\\\nC_PROBE_OUT117_WIDTH=1,C_PROBE_OUT118_WIDTH=1,C_PROBE_OUT119_WIDTH=1,C_PROBE_OUT120_WIDTH=1,C_PROBE_OUT121_WIDTH=1,C_PROBE_OUT122_WIDTH=1,C_PROBE_OUT123_WIDTH=1,C_PROBE_OUT124_WIDTH=1,C_PROBE_OUT125_WIDTH=1,C_PROBE_OUT126_WIDTH=1,C_PROBE_OUT127_WIDTH=1,C_PROBE_OUT128_WIDTH=1,C_PROBE_OUT129_WIDTH=1,C_PROBE_OUT130_WIDTH=1,C_PROBE_OUT131_WIDTH=1,C_PROBE_OUT132_WIDTH=1,C_PROBE_OUT133_WIDTH=1,C_PROBE_OUT134_WIDTH=1,C_PROBE_OUT135_WIDTH=1,C_PROBE_OUT136_WIDTH=1,C_PROBE_OUT137_WIDTH=1,C_PROBE_OUT138_WIDTH=1,C_PROBE_OUT139_WIDTH=1,C_PROBE_OUT140_WIDTH=1,C_PROBE_OUT141_WIDTH=1,C_PROBE_OUT142_WIDTH=1,C_PROBE_OUT143_WIDTH=1,C_PROBE_OUT144_WIDTH=1,C_PROBE_OUT145_WIDTH=1,C_PROBE_OUT146_WIDTH=1,C_PROBE_OUT147_WIDTH=1,C_PROBE_OUT148_WIDTH=1,C_PROBE_OUT149_WIDTH=1,C_PROBE_OUT150_WIDTH=1,C_PROBE_OUT151_WIDTH=1,C_PROBE_OUT152_WIDTH=1,C_PROBE_OUT153_WIDTH=1,C_PROBE_OUT154_WIDTH=1,C_PROBE_OUT155_WIDTH=1,C_PROBE_OUT156_WIDTH=1,C_PROBE_OUT157_WIDTH=1,C_PROBE_OUT158_WIDTH=1,C_PROBE_OUT159_WIDTH=1,C_PROBE_OUT160_WIDTH=1,C_PROBE_OUT161_WIDTH=1,C_PROBE_OUT162_WIDTH=1,C_PROBE_OUT163_WIDTH=1,C_PROBE_OUT164_WIDTH=1,C_PROBE_OUT165_WIDTH=1,C_PROBE_OUT166_WIDTH=1,C_PROBE_OUT167_WIDTH=1,C_PROBE_OUT168_WIDTH=1,C_PROBE_OUT169_WIDTH=1,C_PROBE_OUT170_WIDTH=1,C_PROBE_OUT171_WIDTH=1,C_PROBE_OUT172_WIDTH=1,C_PROBE_OUT173_WIDTH=1,C_PROBE_OUT174_WIDTH=1,C_PROBE_OUT175_WIDTH=1,C_PROBE_OUT176_WIDTH=1,C_PROBE_OUT177_WIDTH=1,C_PROBE_OUT178_WIDTH=1,C_PROBE_OUT179_WIDTH=1,C_PROBE_OUT180_WIDTH=1,C_PROBE_OUT181_WIDTH=1,C_PROBE_OUT182_WIDTH=1,C_PROBE_OUT183_WIDTH=1,C_PROBE_OUT184_WIDTH=1,C_PROBE_OUT185_WIDTH=1,C_PROBE_OUT186_WIDTH=1,C_PROBE_OUT187_WIDTH=1,C_PROBE_OUT188_WIDTH=1,C_PROBE_OUT189_WIDTH=1,C_PROBE_OUT190_WIDTH=1,C_PROBE_OUT191_WIDTH=1,C_PROBE_OUT192_WIDTH=1,C_PROBE_OUT193_WIDTH=1,C_PROBE_OUT194_WIDTH=1,C_PROBE_OUT195_WIDTH=1,C_PROBE_OUT196_WIDTH=1,C_PROBE_OUT197_WIDTH=1,C_PROBE_OUT198_WIDTH=1,C_PROBE_OUT199_WIDTH=1,C_PROBE_OUT200_WIDTH=1,C_PROBE_OUT201_WIDTH=1,C_PROBE_OUT202_WIDTH=1,C_PROBE_OUT203_WIDTH=1,C_PROBE_OUT204_WIDTH=1,C_PROBE_OUT205_WIDTH=1,C_PROBE_OUT206_WIDTH=1,C_PROBE_OUT207_WIDTH=1,C_PROBE_OUT208_WIDTH=1,C_PROBE_OUT209_WIDTH=1,C_PROBE_OUT210_WIDTH=1,C_PROBE_OUT211_WIDTH=1,C_PROBE_OUT212_WIDTH=1,C_PROBE_OUT213_WIDTH=1,C_PROBE_OUT214_WIDTH=1,C_PROBE_OUT215_WIDTH=1,C_PROBE_OUT216_WIDTH=1,\\\nC_PROBE_OUT217_WIDTH=1,C_PROBE_OUT218_WIDTH=1,C_PROBE_OUT219_WIDTH=1,C_PROBE_OUT220_WIDTH=1,C_PROBE_OUT221_WIDTH=1,C_PROBE_OUT222_WIDTH=1,C_PROBE_OUT223_WIDTH=1,C_PROBE_OUT224_WIDTH=1,C_PROBE_OUT225_WIDTH=1,C_PROBE_OUT226_WIDTH=1,C_PROBE_OUT227_WIDTH=1,C_PROBE_OUT228_WIDTH=1,C_PROBE_OUT229_WIDTH=1,C_PROBE_OUT230_WIDTH=1,C_PROBE_OUT231_WIDTH=1,C_PROBE_OUT232_WIDTH=1,C_PROBE_OUT233_WIDTH=1,C_PROBE_OUT234_WIDTH=1,C_PROBE_OUT235_WIDTH=1,C_PROBE_OUT236_WIDTH=1,C_PROBE_OUT237_WIDTH=1,C_PROBE_OUT238_WIDTH=1,C_PROBE_OUT239_WIDTH=1,C_PROBE_OUT240_WIDTH=1,C_PROBE_OUT241_WIDTH=1,C_PROBE_OUT242_WIDTH=1,C_PROBE_OUT243_WIDTH=1,C_PROBE_OUT244_WIDTH=1,C_PROBE_OUT245_WIDTH=1,C_PROBE_OUT246_WIDTH=1,C_PROBE_OUT247_WIDTH=1,C_PROBE_OUT248_WIDTH=1,C_PROBE_OUT249_WIDTH=1,C_PROBE_OUT250_WIDTH=1,C_PROBE_OUT251_WIDTH=1,C_PROBE_OUT252_WIDTH=1,C_PROBE_OUT253_WIDTH=1,C_PROBE_OUT254_WIDTH=1,C_PROBE_OUT255_WIDTH=1,C_PROBE_OUT0_INIT_VAL=0x0,C_PROBE_OUT1_INIT_VAL=0x0,C_PROBE_OUT2_INIT_VAL=0x1,C_PROBE_OUT3_INIT_VAL=0x0,C_PROBE_OUT4_INIT_VAL=0x00,C_PROBE_OUT5_INIT_VAL=0x0000,C_PROBE_OUT6_INIT_VAL=0x0000,C_PROBE_OUT7_INIT_VAL=0,C_PROBE_OUT8_INIT_VAL=0,C_PROBE_OUT9_INIT_VAL=0,C_PROBE_OUT10_INIT_VAL=0,C_PROBE_OUT11_INIT_VAL=0,C_PROBE_OUT12_INIT_VAL=0,C_PROBE_OUT13_INIT_VAL=0,C_PROBE_OUT14_INIT_VAL=0,C_PROBE_OUT15_INIT_VAL=0,C_PROBE_OUT16_INIT_VAL=0,C_PROBE_OUT17_INIT_VAL=0,C_PROBE_OUT18_INIT_VAL=0,C_PROBE_OUT19_INIT_VAL=0,C_PROBE_OUT20_INIT_VAL=0,C_PROBE_OUT21_INIT_VAL=0,C_PROBE_OUT22_INIT_VAL=0,C_PROBE_OUT23_INIT_VAL=0,C_PROBE_OUT24_INIT_VAL=0,C_PROBE_OUT25_INIT_VAL=0,C_PROBE_OUT26_INIT_VAL=0,C_PROBE_OUT27_INIT_VAL=0,C_PROBE_OUT28_INIT_VAL=0,C_PROBE_OUT29_INIT_VAL=0,C_PROBE_OUT30_INIT_VAL=0,C_PROBE_OUT31_INIT_VAL=0,C_PROBE_OUT32_INIT_VAL=0,C_PROBE_OUT33_INIT_VAL=0,C_PROBE_OUT34_INIT_VAL=0,C_PROBE_OUT35_INIT_VAL=0,C_PROBE_OUT36_INIT_VAL=0,C_PROBE_OUT37_INIT_VAL=0,C_PROBE_OUT38_INIT_VAL=0,C_PROBE_OUT39_INIT_VAL=0,C_PROBE_OUT40_INIT_VAL=0,C_PROBE_OUT41_INIT_VAL=0,C_PROBE_OUT42_INIT_VAL=0,C_PROBE_OUT43_INIT_VAL=0,C_PROBE_OUT44_INIT_VAL=0,C_PROBE_OUT45_INIT_VAL=0,C_PROBE_OUT46_INIT_VAL=0,C_PROBE_OUT47_INIT_VAL=0,C_PROBE_OUT48_INIT_VAL=0,C_PROBE_OUT49_INIT_VAL=0,C_PROBE_OUT50_INIT_VAL=0,C_PROBE_OUT51_INIT_VAL=0,C_PROBE_OUT52_INIT_VAL=0,C_PROBE_OUT53_INIT_VAL=0,C_PROBE_OUT54_INIT_VAL=0,C_PROBE_OUT55_INIT_VAL=0,C_PROBE_OUT56_INIT_VAL=0,C_PROBE_OUT57_INIT_VAL=0,C_PROBE_OUT58_INIT_VAL=0,C_PROBE_OUT59_INIT_VAL=0,C_PROBE_OUT60_INIT_VAL=0,\\\nC_PROBE_OUT61_INIT_VAL=0,C_PROBE_OUT62_INIT_VAL=0,C_PROBE_OUT63_INIT_VAL=0,C_PROBE_OUT64_INIT_VAL=0,C_PROBE_OUT65_INIT_VAL=0,C_PROBE_OUT66_INIT_VAL=0,C_PROBE_OUT67_INIT_VAL=0,C_PROBE_OUT68_INIT_VAL=0,C_PROBE_OUT69_INIT_VAL=0,C_PROBE_OUT70_INIT_VAL=0,C_PROBE_OUT71_INIT_VAL=0,C_PROBE_OUT72_INIT_VAL=0,C_PROBE_OUT73_INIT_VAL=0,C_PROBE_OUT74_INIT_VAL=0,C_PROBE_OUT75_INIT_VAL=0,C_PROBE_OUT76_INIT_VAL=0,C_PROBE_OUT77_INIT_VAL=0,C_PROBE_OUT78_INIT_VAL=0,C_PROBE_OUT79_INIT_VAL=0,C_PROBE_OUT80_INIT_VAL=0,C_PROBE_OUT81_INIT_VAL=0,C_PROBE_OUT82_INIT_VAL=0,C_PROBE_OUT83_INIT_VAL=0,C_PROBE_OUT84_INIT_VAL=0,C_PROBE_OUT85_INIT_VAL=0,C_PROBE_OUT86_INIT_VAL=0,C_PROBE_OUT87_INIT_VAL=0,C_PROBE_OUT88_INIT_VAL=0,C_PROBE_OUT89_INIT_VAL=0,C_PROBE_OUT90_INIT_VAL=0,C_PROBE_OUT91_INIT_VAL=0,C_PROBE_OUT92_INIT_VAL=0,C_PROBE_OUT93_INIT_VAL=0,C_PROBE_OUT94_INIT_VAL=0,C_PROBE_OUT95_INIT_VAL=0,C_PROBE_OUT96_INIT_VAL=0,C_PROBE_OUT97_INIT_VAL=0,C_PROBE_OUT98_INIT_VAL=0,C_PROBE_OUT99_INIT_VAL=0,C_PROBE_OUT100_INIT_VAL=0,C_PROBE_OUT101_INIT_VAL=0,C_PROBE_OUT102_INIT_VAL=0,C_PROBE_OUT103_INIT_VAL=0,C_PROBE_OUT104_INIT_VAL=0,C_PROBE_OUT105_INIT_VAL=0,C_PROBE_OUT106_INIT_VAL=0,C_PROBE_OUT107_INIT_VAL=0,C_PROBE_OUT108_INIT_VAL=0,C_PROBE_OUT109_INIT_VAL=0,C_PROBE_OUT110_INIT_VAL=0,C_PROBE_OUT111_INIT_VAL=0,C_PROBE_OUT112_INIT_VAL=0,C_PROBE_OUT113_INIT_VAL=0,C_PROBE_OUT114_INIT_VAL=0,C_PROBE_OUT115_INIT_VAL=0,C_PROBE_OUT116_INIT_VAL=0,C_PROBE_OUT117_INIT_VAL=0,C_PROBE_OUT118_INIT_VAL=0,C_PROBE_OUT119_INIT_VAL=0,C_PROBE_OUT120_INIT_VAL=0,C_PROBE_OUT121_INIT_VAL=0,C_PROBE_OUT122_INIT_VAL=0,C_PROBE_OUT123_INIT_VAL=0,C_PROBE_OUT124_INIT_VAL=0,C_PROBE_OUT125_INIT_VAL=0,C_PROBE_OUT126_INIT_VAL=0,C_PROBE_OUT127_INIT_VAL=0,C_PROBE_OUT128_INIT_VAL=0,C_PROBE_OUT129_INIT_VAL=0,C_PROBE_OUT130_INIT_VAL=0,C_PROBE_OUT131_INIT_VAL=0,C_PROBE_OUT132_INIT_VAL=0,C_PROBE_OUT133_INIT_VAL=0,C_PROBE_OUT134_INIT_VAL=0,C_PROBE_OUT135_INIT_VAL=0,C_PROBE_OUT136_INIT_VAL=0,C_PROBE_OUT137_INIT_VAL=0,C_PROBE_OUT138_INIT_VAL=0,C_PROBE_OUT139_INIT_VAL=0,C_PROBE_OUT140_INIT_VAL=0,C_PROBE_OUT141_INIT_VAL=0,C_PROBE_OUT142_INIT_VAL=0,C_PROBE_OUT143_INIT_VAL=0,C_PROBE_OUT144_INIT_VAL=0,C_PROBE_OUT145_INIT_VAL=0,C_PROBE_OUT146_INIT_VAL=0,C_PROBE_OUT147_INIT_VAL=0,C_PROBE_OUT148_INIT_VAL=0,C_PROBE_OUT149_INIT_VAL=0,C_PROBE_OUT150_INIT_VAL=0,C_PROBE_OUT151_INIT_VAL=0,C_PROBE_OUT152_INIT_VAL=0,C_PROBE_OUT153_INIT_VAL=0,C_PROBE_OUT154_INIT_VAL=0,C_PROBE_OUT155_INIT_VAL=0,C_PROBE_OUT156_INIT_VAL=0,C_PROBE_OUT157_INIT_VAL=0,C_PROBE_OUT158_INIT_VAL=0,C_PROBE_OUT159_INIT_VAL=0,C_PROBE_OUT160_INIT_VAL=0,\\\nC_PROBE_OUT161_INIT_VAL=0,C_PROBE_OUT162_INIT_VAL=0,C_PROBE_OUT163_INIT_VAL=0,C_PROBE_OUT164_INIT_VAL=0,C_PROBE_OUT165_INIT_VAL=0,C_PROBE_OUT166_INIT_VAL=0,C_PROBE_OUT167_INIT_VAL=0,C_PROBE_OUT168_INIT_VAL=0,C_PROBE_OUT169_INIT_VAL=0,C_PROBE_OUT170_INIT_VAL=0,C_PROBE_OUT171_INIT_VAL=0,C_PROBE_OUT172_INIT_VAL=0,C_PROBE_OUT173_INIT_VAL=0,C_PROBE_OUT174_INIT_VAL=0,C_PROBE_OUT175_INIT_VAL=0,C_PROBE_OUT176_INIT_VAL=0,C_PROBE_OUT177_INIT_VAL=0,C_PROBE_OUT178_INIT_VAL=0,C_PROBE_OUT179_INIT_VAL=0,C_PROBE_OUT180_INIT_VAL=0,C_PROBE_OUT181_INIT_VAL=0,C_PROBE_OUT182_INIT_VAL=0,C_PROBE_OUT183_INIT_VAL=0,C_PROBE_OUT184_INIT_VAL=0,C_PROBE_OUT185_INIT_VAL=0,C_PROBE_OUT186_INIT_VAL=0,C_PROBE_OUT187_INIT_VAL=0,C_PROBE_OUT188_INIT_VAL=0,C_PROBE_OUT189_INIT_VAL=0,C_PROBE_OUT190_INIT_VAL=0,C_PROBE_OUT191_INIT_VAL=0,C_PROBE_OUT192_INIT_VAL=0,C_PROBE_OUT193_INIT_VAL=0,C_PROBE_OUT194_INIT_VAL=0,C_PROBE_OUT195_INIT_VAL=0,C_PROBE_OUT196_INIT_VAL=0,C_PROBE_OUT197_INIT_VAL=0,C_PROBE_OUT198_INIT_VAL=0,C_PROBE_OUT199_INIT_VAL=0,C_PROBE_OUT200_INIT_VAL=0,C_PROBE_OUT201_INIT_VAL=0,C_PROBE_OUT202_INIT_VAL=0,C_PROBE_OUT203_INIT_VAL=0,C_PROBE_OUT204_INIT_VAL=0,C_PROBE_OUT205_INIT_VAL=0,C_PROBE_OUT206_INIT_VAL=0,C_PROBE_OUT207_INIT_VAL=0,C_PROBE_OUT208_INIT_VAL=0,C_PROBE_OUT209_INIT_VAL=0,C_PROBE_OUT210_INIT_VAL=0,C_PROBE_OUT211_INIT_VAL=0,C_PROBE_OUT212_INIT_VAL=0,C_PROBE_OUT213_INIT_VAL=0,C_PROBE_OUT214_INIT_VAL=0,C_PROBE_OUT215_INIT_VAL=0,C_PROBE_OUT216_INIT_VAL=0,C_PROBE_OUT217_INIT_VAL=0,C_PROBE_OUT218_INIT_VAL=0,C_PROBE_OUT219_INIT_VAL=0,C_PROBE_OUT220_INIT_VAL=0,C_PROBE_OUT221_INIT_VAL=0,C_PROBE_OUT222_INIT_VAL=0,C_PROBE_OUT223_INIT_VAL=0,C_PROBE_OUT224_INIT_VAL=0,C_PROBE_OUT225_INIT_VAL=0,C_PROBE_OUT226_INIT_VAL=0,C_PROBE_OUT227_INIT_VAL=0,C_PROBE_OUT228_INIT_VAL=0,C_PROBE_OUT229_INIT_VAL=0,C_PROBE_OUT230_INIT_VAL=0,C_PROBE_OUT231_INIT_VAL=0,C_PROBE_OUT232_INIT_VAL=0,C_PROBE_OUT233_INIT_VAL=0,C_PROBE_OUT234_INIT_VAL=0,C_PROBE_OUT235_INIT_VAL=0,C_PROBE_OUT236_INIT_VAL=0,C_PROBE_OUT237_INIT_VAL=0,C_PROBE_OUT238_INIT_VAL=0,C_PROBE_OUT239_INIT_VAL=0,C_PROBE_OUT240_INIT_VAL=0,C_PROBE_OUT241_INIT_VAL=0,C_PROBE_OUT242_INIT_VAL=0,C_PROBE_OUT243_INIT_VAL=0,C_PROBE_OUT244_INIT_VAL=0,C_PROBE_OUT245_INIT_VAL=0,C_PROBE_OUT246_INIT_VAL=0,C_PROBE_OUT247_INIT_VAL=0,C_PROBE_OUT248_INIT_VAL=0,C_PROBE_OUT249_INIT_VAL=0,C_PROBE_OUT250_INIT_VAL=0,C_PROBE_OUT251_INIT_VAL=0,C_PROBE_OUT252_INIT_VAL=0,C_PROBE_OUT253_INIT_VAL=0,C_PROBE_OUT254_INIT_VAL=0,C_PROBE_OUT255_INIT_VAL=0}\" *)\nmodule vio_0 (\nclk,\nprobe_in0,probe_in1,probe_in2,probe_in3,\nprobe_out0,\nprobe_out1,\nprobe_out2,\nprobe_out3,\nprobe_out4,\nprobe_out5,\nprobe_out6\n);\n\ninput clk;\ninput [0 : 0] probe_in0;\ninput [0 : 0] probe_in1;\ninput [7 : 0] probe_in2;\ninput [15 : 0] probe_in3;\n\noutput [0 : 0] probe_out0;\noutput [0 : 0] probe_out1;\noutput [0 : 0] probe_out2;\noutput [0 : 0] probe_out3;\noutput [7 : 0] probe_out4;\noutput [15 : 0] probe_out5;\noutput [15 : 0] probe_out6;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nvio_v3_0_17_vio #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexuplus\"),\n.C_CORE_TYPE(2),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_NUM_PROBE_IN(4),\n.C_EN_PROBE_IN_ACTIVITY(1),\n.C_NUM_PROBE_OUT(7),\n.C_MAJOR_VERSION(2013),\n.C_MINOR_VERSION(1),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(2),\n.C_CORE_MINOR_VER(0),\n.C_CORE_MINOR_ALPHA_VER(97),\n.C_XSDB_SLAVE_TYPE(33),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(1),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(0),\n.C_PROBE_IN0_WIDTH(1),\n.C_PROBE_IN1_WIDTH(1),\n.C_PROBE_IN2_WIDTH(8),\n.C_PROBE_IN3_WIDTH(16),\n.C_PROBE_IN4_WIDTH(1),\n.C_PROBE_IN5_WIDTH(1),\n.C_PROBE_IN6_WIDTH(1),\n.C_PROBE_IN7_WIDTH(1),\n.C_PROBE_IN8_WIDTH(1),\n.C_PROBE_IN9_WIDTH(1),\n.C_PROBE_IN10_WIDTH(1),\n.C_PROBE_IN11_WIDTH(1),\n.C_PROBE_IN12_WIDTH(1),\n.C_PROBE_IN13_WIDTH(1),\n.C_PROBE_IN14_WIDTH(1),\n.C_PROBE_IN15_WIDTH(1),\n.C_PROBE_IN16_WIDTH(1),\n.C_PROBE_IN17_WIDTH(1),\n.C_PROBE_IN18_WIDTH(1),\n.C_PROBE_IN19_WIDTH(1),\n.C_PROBE_IN20_WIDTH(1),\n.C_PROBE_IN21_WIDTH(1),\n.C_PROBE_IN22_WIDTH(1),\n.C_PROBE_IN23_WIDTH(1),\n.C_PROBE_IN24_WIDTH(1),\n.C_PROBE_IN25_WIDTH(1),\n.C_PROBE_IN26_WIDTH(1),\n.C_PROBE_IN27_WIDTH(1),\n.C_PROBE_IN28_WIDTH(1),\n.C_PROBE_IN29_WIDTH(1),\n.C_PROBE_IN30_WIDTH(1),\n.C_PROBE_IN31_WIDTH(1),\n.C_PROBE_IN32_WIDTH(1),\n.C_PROBE_IN33_WIDTH(1),\n.C_PROBE_IN34_WIDTH(1),\n.C_PROBE_IN35_WIDTH(1),\n.C_PROBE_IN36_WIDTH(1),\n.C_PROBE_IN37_WIDTH(1),\n.C_PROBE_IN38_WIDTH(1),\n.C_PROBE_IN39_WIDTH(1),\n.C_PROBE_IN40_WIDTH(1),\n.C_PROBE_IN41_WIDTH(1),\n.C_PROBE_IN42_WIDTH(1),\n.C_PROBE_IN43_WIDTH(1),\n.C_PROBE_IN44_WIDTH(1),\n.C_PROBE_IN45_WIDTH(1),\n.C_PROBE_IN46_WIDTH(1),\n.C_PROBE_IN47_WIDTH(1),\n.C_PROBE_IN48_WIDTH(1),\n.C_PROBE_IN49_WIDTH(1),\n.C_PROBE_IN50_WIDTH(1),\n.C_PROBE_IN51_WIDTH(1),\n.C_PROBE_IN52_WIDTH(1),\n.C_PROBE_IN53_WIDTH(1),\n.C_PROBE_IN54_WIDTH(1),\n.C_PROBE_IN55_WIDTH(1),\n.C_PROBE_IN56_WIDTH(1),\n.C_PROBE_IN57_WIDTH(1),\n.C_PROBE_IN58_WIDTH(1),\n.C_PROBE_IN59_WIDTH(1),\n.C_PROBE_IN60_WIDTH(1),\n.C_PROBE_IN61_WIDTH(1),\n.C_PROBE_IN62_WIDTH(1),\n.C_PROBE_IN63_WIDTH(1),\n.C_PROBE_IN64_WIDTH(1),\n.C_PROBE_IN65_WIDTH(1),\n.C_PROBE_IN66_WIDTH(1),\n.C_PROBE_IN67_WIDTH(1),\n.C_PROBE_IN68_WIDTH(1),\n.C_PROBE_IN69_WIDTH(1),\n.C_PROBE_IN70_WIDTH(1),\n.C_PROBE_IN71_WIDTH(1),\n.C_PROBE_IN72_WIDTH(1),\n.C_PROBE_IN73_WIDTH(1),\n.C_PROBE_IN74_WIDTH(1),\n.C_PROBE_IN75_WIDTH(1),\n.C_PROBE_IN76_WIDTH(1),\n.C_PROBE_IN77_WIDTH(1),\n.C_PROBE_IN78_WIDTH(1),\n.C_PROBE_IN79_WIDTH(1),\n.C_PROBE_IN80_WIDTH(1),\n.C_PROBE_IN81_WIDTH(1),\n.C_PROBE_IN82_WIDTH(1),\n.C_PROBE_IN83_WIDTH(1),\n.C_PROBE_IN84_WIDTH(1),\n.C_PROBE_IN85_WIDTH(1),\n.C_PROBE_IN86_WIDTH(1),\n.C_PROBE_IN87_WIDTH(1),\n.C_PROBE_IN88_WIDTH(1),\n.C_PROBE_IN89_WIDTH(1),\n.C_PROBE_IN90_WIDTH(1),\n.C_PROBE_IN91_WIDTH(1),\n.C_PROBE_IN92_WIDTH(1),\n.C_PROBE_IN93_WIDTH(1),\n.C_PROBE_IN94_WIDTH(1),\n.C_PROBE_IN95_WIDTH(1),\n.C_PROBE_IN96_WIDTH(1),\n.C_PROBE_IN97_WIDTH(1),\n.C_PROBE_IN98_WIDTH(1),\n.C_PROBE_IN99_WIDTH(1),\n.C_PROBE_IN100_WIDTH(1),\n.C_PROBE_IN101_WIDTH(1),\n.C_PROBE_IN102_WIDTH(1),\n.C_PROBE_IN103_WIDTH(1),\n.C_PROBE_IN104_WIDTH(1),\n.C_PROBE_IN105_WIDTH(1),\n.C_PROBE_IN106_WIDTH(1),\n.C_PROBE_IN107_WIDTH(1),\n.C_PROBE_IN108_WIDTH(1),\n.C_PROBE_IN109_WIDTH(1),\n.C_PROBE_IN110_WIDTH(1),\n.C_PROBE_IN111_WIDTH(1),\n.C_PROBE_IN112_WIDTH(1),\n.C_PROBE_IN113_WIDTH(1),\n.C_PROBE_IN114_WIDTH(1),\n.C_PROBE_IN115_WIDTH(1),\n.C_PROBE_IN116_WIDTH(1),\n.C_PROBE_IN117_WIDTH(1),\n.C_PROBE_IN118_WIDTH(1),\n.C_PROBE_IN119_WIDTH(1),\n.C_PROBE_IN120_WIDTH(1),\n.C_PROBE_IN121_WIDTH(1),\n.C_PROBE_IN122_WIDTH(1),\n.C_PROBE_IN123_WIDTH(1),\n.C_PROBE_IN124_WIDTH(1),\n.C_PROBE_IN125_WIDTH(1),\n.C_PROBE_IN126_WIDTH(1),\n.C_PROBE_IN127_WIDTH(1),\n.C_PROBE_IN128_WIDTH(1),\n.C_PROBE_IN129_WIDTH(1),\n.C_PROBE_IN130_WIDTH(1),\n.C_PROBE_IN131_WIDTH(1),\n.C_PROBE_IN132_WIDTH(1),\n.C_PROBE_IN133_WIDTH(1),\n.C_PROBE_IN134_WIDTH(1),\n.C_PROBE_IN135_WIDTH(1),\n.C_PROBE_IN136_WIDTH(1),\n.C_PROBE_IN137_WIDTH(1),\n.C_PROBE_IN138_WIDTH(1),\n.C_PROBE_IN139_WIDTH(1),\n.C_PROBE_IN140_WIDTH(1),\n.C_PROBE_IN141_WIDTH(1),\n.C_PROBE_IN142_WIDTH(1),\n.C_PROBE_IN143_WIDTH(1),\n.C_PROBE_IN144_WIDTH(1),\n.C_PROBE_IN145_WIDTH(1),\n.C_PROBE_IN146_WIDTH(1),\n.C_PROBE_IN147_WIDTH(1),\n.C_PROBE_IN148_WIDTH(1),\n.C_PROBE_IN149_WIDTH(1),\n.C_PROBE_IN150_WIDTH(1),\n.C_PROBE_IN151_WIDTH(1),\n.C_PROBE_IN152_WIDTH(1),\n.C_PROBE_IN153_WIDTH(1),\n.C_PROBE_IN154_WIDTH(1),\n.C_PROBE_IN155_WIDTH(1),\n.C_PROBE_IN156_WIDTH(1),\n.C_PROBE_IN157_WIDTH(1),\n.C_PROBE_IN158_WIDTH(1),\n.C_PROBE_IN159_WIDTH(1),\n.C_PROBE_IN160_WIDTH(1),\n.C_PROBE_IN161_WIDTH(1),\n.C_PROBE_IN162_WIDTH(1),\n.C_PROBE_IN163_WIDTH(1),\n.C_PROBE_IN164_WIDTH(1),\n.C_PROBE_IN165_WIDTH(1),\n.C_PROBE_IN166_WIDTH(1),\n.C_PROBE_IN167_WIDTH(1),\n.C_PROBE_IN168_WIDTH(1),\n.C_PROBE_IN169_WIDTH(1),\n.C_PROBE_IN170_WIDTH(1),\n.C_PROBE_IN171_WIDTH(1),\n.C_PROBE_IN172_WIDTH(1),\n.C_PROBE_IN173_WIDTH(1),\n.C_PROBE_IN174_WIDTH(1),\n.C_PROBE_IN175_WIDTH(1),\n.C_PROBE_IN176_WIDTH(1),\n.C_PROBE_IN177_WIDTH(1),\n.C_PROBE_IN178_WIDTH(1),\n.C_PROBE_IN179_WIDTH(1),\n.C_PROBE_IN180_WIDTH(1),\n.C_PROBE_IN181_WIDTH(1),\n.C_PROBE_IN182_WIDTH(1),\n.C_PROBE_IN183_WIDTH(1),\n.C_PROBE_IN184_WIDTH(1),\n.C_PROBE_IN185_WIDTH(1),\n.C_PROBE_IN186_WIDTH(1),\n.C_PROBE_IN187_WIDTH(1),\n.C_PROBE_IN188_WIDTH(1),\n.C_PROBE_IN189_WIDTH(1),\n.C_PROBE_IN190_WIDTH(1),\n.C_PROBE_IN191_WIDTH(1),\n.C_PROBE_IN192_WIDTH(1),\n.C_PROBE_IN193_WIDTH(1),\n.C_PROBE_IN194_WIDTH(1),\n.C_PROBE_IN195_WIDTH(1),\n.C_PROBE_IN196_WIDTH(1),\n.C_PROBE_IN197_WIDTH(1),\n.C_PROBE_IN198_WIDTH(1),\n.C_PROBE_IN199_WIDTH(1),\n.C_PROBE_IN200_WIDTH(1),\n.C_PROBE_IN201_WIDTH(1),\n.C_PROBE_IN202_WIDTH(1),\n.C_PROBE_IN203_WIDTH(1),\n.C_PROBE_IN204_WIDTH(1),\n.C_PROBE_IN205_WIDTH(1),\n.C_PROBE_IN206_WIDTH(1),\n.C_PROBE_IN207_WIDTH(1),\n.C_PROBE_IN208_WIDTH(1),\n.C_PROBE_IN209_WIDTH(1),\n.C_PROBE_IN210_WIDTH(1),\n.C_PROBE_IN211_WIDTH(1),\n.C_PROBE_IN212_WIDTH(1),\n.C_PROBE_IN213_WIDTH(1),\n.C_PROBE_IN214_WIDTH(1),\n.C_PROBE_IN215_WIDTH(1),\n.C_PROBE_IN216_WIDTH(1),\n.C_PROBE_IN217_WIDTH(1),\n.C_PROBE_IN218_WIDTH(1),\n.C_PROBE_IN219_WIDTH(1),\n.C_PROBE_IN220_WIDTH(1),\n.C_PROBE_IN221_WIDTH(1),\n.C_PROBE_IN222_WIDTH(1),\n.C_PROBE_IN223_WIDTH(1),\n.C_PROBE_IN224_WIDTH(1),\n.C_PROBE_IN225_WIDTH(1),\n.C_PROBE_IN226_WIDTH(1),\n.C_PROBE_IN227_WIDTH(1),\n.C_PROBE_IN228_WIDTH(1),\n.C_PROBE_IN229_WIDTH(1),\n.C_PROBE_IN230_WIDTH(1),\n.C_PROBE_IN231_WIDTH(1),\n.C_PROBE_IN232_WIDTH(1),\n.C_PROBE_IN233_WIDTH(1),\n.C_PROBE_IN234_WIDTH(1),\n.C_PROBE_IN235_WIDTH(1),\n.C_PROBE_IN236_WIDTH(1),\n.C_PROBE_IN237_WIDTH(1),\n.C_PROBE_IN238_WIDTH(1),\n.C_PROBE_IN239_WIDTH(1),\n.C_PROBE_IN240_WIDTH(1),\n.C_PROBE_IN241_WIDTH(1),\n.C_PROBE_IN242_WIDTH(1),\n.C_PROBE_IN243_WIDTH(1),\n.C_PROBE_IN244_WIDTH(1),\n.C_PROBE_IN245_WIDTH(1),\n.C_PROBE_IN246_WIDTH(1),\n.C_PROBE_IN247_WIDTH(1),\n.C_PROBE_IN248_WIDTH(1),\n.C_PROBE_IN249_WIDTH(1),\n.C_PROBE_IN250_WIDTH(1),\n.C_PROBE_IN251_WIDTH(1),\n.C_PROBE_IN252_WIDTH(1),\n.C_PROBE_IN253_WIDTH(1),\n.C_PROBE_IN254_WIDTH(1),\n.C_PROBE_IN255_WIDTH(1),\n.C_PROBE_OUT0_WIDTH(1),\n.C_PROBE_OUT1_WIDTH(1),\n.C_PROBE_OUT2_WIDTH(1),\n.C_PROBE_OUT3_WIDTH(1),\n.C_PROBE_OUT4_WIDTH(8),\n.C_PROBE_OUT5_WIDTH(16),\n.C_PROBE_OUT6_WIDTH(16),\n.C_PROBE_OUT7_WIDTH(1),\n.C_PROBE_OUT8_WIDTH(1),\n.C_PROBE_OUT9_WIDTH(1),\n.C_PROBE_OUT10_WIDTH(1),\n.C_PROBE_OUT11_WIDTH(1),\n.C_PROBE_OUT12_WIDTH(1),\n.C_PROBE_OUT13_WIDTH(1),\n.C_PROBE_OUT14_WIDTH(1),\n.C_PROBE_OUT15_WIDTH(1),\n.C_PROBE_OUT16_WIDTH(1),\n.C_PROBE_OUT17_WIDTH(1),\n.C_PROBE_OUT18_WIDTH(1),\n.C_PROBE_OUT19_WIDTH(1),\n.C_PROBE_OUT20_WIDTH(1),\n.C_PROBE_OUT21_WIDTH(1),\n.C_PROBE_OUT22_WIDTH(1),\n.C_PROBE_OUT23_WIDTH(1),\n.C_PROBE_OUT24_WIDTH(1),\n.C_PROBE_OUT25_WIDTH(1),\n.C_PROBE_OUT26_WIDTH(1),\n.C_PROBE_OUT27_WIDTH(1),\n.C_PROBE_OUT28_WIDTH(1),\n.C_PROBE_OUT29_WIDTH(1),\n.C_PROBE_OUT30_WIDTH(1),\n.C_PROBE_OUT31_WIDTH(1),\n.C_PROBE_OUT32_WIDTH(1),\n.C_PROBE_OUT33_WIDTH(1),\n.C_PROBE_OUT34_WIDTH(1),\n.C_PROBE_OUT35_WIDTH(1),\n.C_PROBE_OUT36_WIDTH(1),\n.C_PROBE_OUT37_WIDTH(1),\n.C_PROBE_OUT38_WIDTH(1),\n.C_PROBE_OUT39_WIDTH(1),\n.C_PROBE_OUT40_WIDTH(1),\n.C_PROBE_OUT41_WIDTH(1),\n.C_PROBE_OUT42_WIDTH(1),\n.C_PROBE_OUT43_WIDTH(1),\n.C_PROBE_OUT44_WIDTH(1),\n.C_PROBE_OUT45_WIDTH(1),\n.C_PROBE_OUT46_WIDTH(1),\n.C_PROBE_OUT47_WIDTH(1),\n.C_PROBE_OUT48_WIDTH(1),\n.C_PROBE_OUT49_WIDTH(1),\n.C_PROBE_OUT50_WIDTH(1),\n.C_PROBE_OUT51_WIDTH(1),\n.C_PROBE_OUT52_WIDTH(1),\n.C_PROBE_OUT53_WIDTH(1),\n.C_PROBE_OUT54_WIDTH(1),\n.C_PROBE_OUT55_WIDTH(1),\n.C_PROBE_OUT56_WIDTH(1),\n.C_PROBE_OUT57_WIDTH(1),\n.C_PROBE_OUT58_WIDTH(1),\n.C_PROBE_OUT59_WIDTH(1),\n.C_PROBE_OUT60_WIDTH(1),\n.C_PROBE_OUT61_WIDTH(1),\n.C_PROBE_OUT62_WIDTH(1),\n.C_PROBE_OUT63_WIDTH(1),\n.C_PROBE_OUT64_WIDTH(1),\n.C_PROBE_OUT65_WIDTH(1),\n.C_PROBE_OUT66_WIDTH(1),\n.C_PROBE_OUT67_WIDTH(1),\n.C_PROBE_OUT68_WIDTH(1),\n.C_PROBE_OUT69_WIDTH(1),\n.C_PROBE_OUT70_WIDTH(1),\n.C_PROBE_OUT71_WIDTH(1),\n.C_PROBE_OUT72_WIDTH(1),\n.C_PROBE_OUT73_WIDTH(1),\n.C_PROBE_OUT74_WIDTH(1),\n.C_PROBE_OUT75_WIDTH(1),\n.C_PROBE_OUT76_WIDTH(1),\n.C_PROBE_OUT77_WIDTH(1),\n.C_PROBE_OUT78_WIDTH(1),\n.C_PROBE_OUT79_WIDTH(1),\n.C_PROBE_OUT80_WIDTH(1),\n.C_PROBE_OUT81_WIDTH(1),\n.C_PROBE_OUT82_WIDTH(1),\n.C_PROBE_OUT83_WIDTH(1),\n.C_PROBE_OUT84_WIDTH(1),\n.C_PROBE_OUT85_WIDTH(1),\n.C_PROBE_OUT86_WIDTH(1),\n.C_PROBE_OUT87_WIDTH(1),\n.C_PROBE_OUT88_WIDTH(1),\n.C_PROBE_OUT89_WIDTH(1),\n.C_PROBE_OUT90_WIDTH(1),\n.C_PROBE_OUT91_WIDTH(1),\n.C_PROBE_OUT92_WIDTH(1),\n.C_PROBE_OUT93_WIDTH(1),\n.C_PROBE_OUT94_WIDTH(1),\n.C_PROBE_OUT95_WIDTH(1),\n.C_PROBE_OUT96_WIDTH(1),\n.C_PROBE_OUT97_WIDTH(1),\n.C_PROBE_OUT98_WIDTH(1),\n.C_PROBE_OUT99_WIDTH(1),\n.C_PROBE_OUT100_WIDTH(1),\n.C_PROBE_OUT101_WIDTH(1),\n.C_PROBE_OUT102_WIDTH(1),\n.C_PROBE_OUT103_WIDTH(1),\n.C_PROBE_OUT104_WIDTH(1),\n.C_PROBE_OUT105_WIDTH(1),\n.C_PROBE_OUT106_WIDTH(1),\n.C_PROBE_OUT107_WIDTH(1),\n.C_PROBE_OUT108_WIDTH(1),\n.C_PROBE_OUT109_WIDTH(1),\n.C_PROBE_OUT110_WIDTH(1),\n.C_PROBE_OUT111_WIDTH(1),\n.C_PROBE_OUT112_WIDTH(1),\n.C_PROBE_OUT113_WIDTH(1),\n.C_PROBE_OUT114_WIDTH(1),\n.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'h0),\n.C_PROBE_OUT197_INIT_VAL('h0),\n.C_PROBE_OUT198_INIT_VAL('h0),\n.C_PROBE_OUT199_INIT_VAL('h0),\n.C_PROBE_OUT200_INIT_VAL('h0),\n.C_PROBE_OUT201_INIT_VAL('h0),\n.C_PROBE_OUT202_INIT_VAL('h0),\n.C_PROBE_OUT203_INIT_VAL('h0),\n.C_PROBE_OUT204_INIT_VAL('h0),\n.C_PROBE_OUT205_INIT_VAL('h0),\n.C_PROBE_OUT206_INIT_VAL('h0),\n.C_PROBE_OUT207_INIT_VAL('h0),\n.C_PROBE_OUT208_INIT_VAL('h0),\n.C_PROBE_OUT209_INIT_VAL('h0),\n.C_PROBE_OUT210_INIT_VAL('h0),\n.C_PROBE_OUT211_INIT_VAL('h0),\n.C_PROBE_OUT212_INIT_VAL('h0),\n.C_PROBE_OUT213_INIT_VAL('h0),\n.C_PROBE_OUT214_INIT_VAL('h0),\n.C_PROBE_OUT215_INIT_VAL('h0),\n.C_PROBE_OUT216_INIT_VAL('h0),\n.C_PROBE_OUT217_INIT_VAL('h0),\n.C_PROBE_OUT218_INIT_VAL('h0),\n.C_PROBE_OUT219_INIT_VAL('h0),\n.C_PROBE_OUT220_INIT_VAL('h0),\n.C_PROBE_OUT221_INIT_VAL('h0),\n.C_PROBE_OUT222_INIT_VAL('h0),\n.C_PROBE_OUT223_INIT_VAL('h0),\n.C_PROBE_OUT224_INIT_VAL('h0),\n.C_PROBE_OUT225_INIT_VAL('h0),\n.C_PROBE_OUT226_INIT_VAL('h0),\n.C_PROBE_OUT227_INIT_VAL('h0),\n.C_PROBE_OUT228_INIT_VAL('h0),\n.C_PROBE_OUT229_INIT_VAL('h0),\n.C_PROBE_OUT230_INIT_VAL('h0),\n.C_PROBE_OUT231_INIT_VAL('h0),\n.C_PROBE_OUT232_INIT_VAL('h0),\n.C_PROBE_OUT233_INIT_VAL('h0),\n.C_PROBE_OUT234_INIT_VAL('h0),\n.C_PROBE_OUT235_INIT_VAL('h0),\n.C_PROBE_OUT236_INIT_VAL('h0),\n.C_PROBE_OUT237_INIT_VAL('h0),\n.C_PROBE_OUT238_INIT_VAL('h0),\n.C_PROBE_OUT239_INIT_VAL('h0),\n.C_PROBE_OUT240_INIT_VAL('h0),\n.C_PROBE_OUT241_INIT_VAL('h0),\n.C_PROBE_OUT242_INIT_VAL('h0),\n.C_PROBE_OUT243_INIT_VAL('h0),\n.C_PROBE_OUT244_INIT_VAL('h0),\n.C_PROBE_OUT245_INIT_VAL('h0),\n.C_PROBE_OUT246_INIT_VAL('h0),\n.C_PROBE_OUT247_INIT_VAL('h0),\n.C_PROBE_OUT248_INIT_VAL('h0),\n.C_PROBE_OUT249_INIT_VAL('h0),\n.C_PROBE_OUT250_INIT_VAL('h0),\n.C_PROBE_OUT251_INIT_VAL('h0),\n.C_PROBE_OUT252_INIT_VAL('h0),\n.C_PROBE_OUT253_INIT_VAL('h0),\n.C_PROBE_OUT254_INIT_VAL('h0),\n.C_PROBE_OUT255_INIT_VAL('h0)\n) inst (\n.clk(clk),\n.sl_iport0(sl_iport0),\n.sl_oport0(sl_oport0),\n.probe_in0(probe_in0),\n.probe_in1(probe_in1),\n.probe_in2(probe_in2),\n.probe_in3(probe_in3),\n.probe_in4(0),\n.probe_in5(0),\n.probe_in6(0),\n.probe_in7(0),\n.probe_in8(0),\n.probe_in9(0),\n.probe_in10(0),\n.probe_in11(0),\n.probe_in12(0),\n.probe_in13(0),\n.probe_in14(0),\n.probe_in15(0),\n.probe_in16(0),\n.probe_in17(0),\n.probe_in18(0),\n.probe_in19(0),\n.probe_in20(0),\n.probe_in21(0),\n.probe_in22(0),\n.probe_in23(0),\n.probe_in24(0),\n.probe_in25(0),\n.probe_in26(0),\n.probe_in27(0),\n.probe_in28(0),\n.probe_in29(0),\n.probe_in30(0),\n.probe_in31(0),\n.probe_in32(0),\n.probe_in33(0),\n.probe_in34(0),\n.probe_in35(0),\n.probe_in36(0),\n.probe_in37(0),\n.probe_in38(0),\n.probe_in39(0),\n.probe_in40(0),\n.probe_in41(0),\n.probe_in42(0),\n.probe_in43(0),\n.probe_in44(0),\n.probe_in45(0),\n.probe_in46(0),\n.probe_in47(0),\n.probe_in48(0),\n.probe_in49(0),\n.probe_in50(0),\n.probe_in51(0),\n.probe_in52(0),\n.probe_in53(0),\n.probe_in54(0),\n.probe_in55(0),\n.probe_in56(0),\n.probe_in57(0),\n.probe_in58(0),\n.probe_in59(0),\n.probe_in60(0),\n.probe_in61(0),\n.probe_in62(0),\n.probe_in63(0),\n.probe_in64(0),\n.probe_in65(0),\n.probe_in66(0),\n.probe_in67(0),\n.probe_in68(0),\n.probe_in69(0),\n.probe_in70(0),\n.probe_in71(0),\n.probe_in72(0),\n.probe_in73(0),\n.probe_in74(0),\n.probe_in75(0),\n.probe_in76(0),\n.probe_in77(0),\n.probe_in78(0),\n.probe_in79(0),\n.probe_in80(0),\n.probe_in81(0),\n.probe_in82(0),\n.probe_in83(0),\n.probe_in84(0),\n.probe_in85(0),\n.probe_in86(0),\n.probe_in87(0),\n.probe_in88(0),\n.probe_in89(0),\n.probe_in90(0),\n.probe_in91(0),\n.probe_in92(0),\n.probe_in93(0),\n.probe_in94(0),\n.probe_in95(0),\n.probe_in96(0),\n.probe_in97(0),\n.probe_in98(0),\n.probe_in99(0),\n.probe_in100(0),\n.probe_in101(0),\n.probe_in102(0),\n.probe_in103(0),\n.probe_in104(0),\n.probe_in105(0),\n.probe_in106(0),\n.probe_in107(0),\n.probe_in108(0),\n.probe_in109(0),\n.probe_in110(0),\n.probe_in111(0),\n.probe_in112(0),\n.probe_in113(0),\n.probe_in114(0),\n.probe_in115(0),\n.probe_in116(0),\n.probe_in117(0),\n.probe_in118(0),\n.probe_in119(0),\n.probe_in120(0),\n.probe_in121(0),\n.probe_in122(0),\n.probe_in123(0),\n.probe_in124(0),\n.probe_in125(0),\n.probe_in126(0),\n.probe_in127(0),\n.probe_in128(0),\n.probe_in129(0),\n.probe_in130(0),\n.probe_in131(0),\n.probe_in132(0),\n.probe_in133(0),\n.probe_in134(0),\n.probe_in135(0),\n.probe_in136(0),\n.probe_in137(0),\n.probe_in138(0),\n.probe_in139(0),\n.probe_in140(0),\n.probe_in141(0),\n.probe_in142(0),\n.probe_in143(0),\n.probe_in144(0),\n.probe_in145(0),\n.probe_in146(0),\n.probe_in147(0),\n.probe_in148(0),\n.probe_in149(0),\n.probe_in150(0),\n.probe_in151(0),\n.probe_in152(0),\n.probe_in153(0),\n.probe_in154(0),\n.probe_in155(0),\n.probe_in156(0),\n.probe_in157(0),\n.probe_in158(0),\n.probe_in159(0),\n.probe_in160(0),\n.probe_in161(0),\n.probe_in162(0),\n.probe_in163(0),\n.probe_in164(0),\n.probe_in165(0),\n.probe_in166(0),\n.probe_in167(0),\n.probe_in168(0),\n.probe_in169(0),\n.probe_in170(0),\n.probe_in171(0),\n.probe_in172(0),\n.probe_in173(0),\n.probe_in174(0),\n.probe_in175(0),\n.probe_in176(0),\n.probe_in177(0),\n.probe_in178(0),\n.probe_in179(0),\n.probe_in180(0),\n.probe_in181(0),\n.probe_in182(0),\n.probe_in183(0),\n.probe_in184(0),\n.probe_in185(0),\n.probe_in186(0),\n.probe_in187(0),\n.probe_in188(0),\n.probe_in189(0),\n.probe_in190(0),\n.probe_in191(0),\n.probe_in192(0),\n.probe_in193(0),\n.probe_in194(0),\n.probe_in195(0),\n.probe_in196(0),\n.probe_in197(0),\n.probe_in198(0),\n.probe_in199(0),\n.probe_in200(0),\n.probe_in201(0),\n.probe_in202(0),\n.probe_in203(0),\n.probe_in204(0),\n.probe_in205(0),\n.probe_in206(0),\n.probe_in207(0),\n.probe_in208(0),\n.probe_in209(0),\n.probe_in210(0),\n.probe_in211(0),\n.probe_in212(0),\n.probe_in213(0),\n.probe_in214(0),\n.probe_in215(0),\n.probe_in216(0),\n.probe_in217(0),\n.probe_in218(0),\n.probe_in219(0),\n.probe_in220(0),\n.probe_in221(0),\n.probe_in222(0),\n.probe_in223(0),\n.probe_in224(0),\n.probe_in225(0),\n.probe_in226(0),\n.probe_in227(0),\n.probe_in228(0),\n.probe_in229(0),\n.probe_in230(0),\n.probe_in231(0),\n.probe_in232(0),\n.probe_in233(0),\n.probe_in234(0),\n.probe_in235(0),\n.probe_in236(0),\n.probe_in237(0),\n.probe_in238(0),\n.probe_in239(0),\n.probe_in240(0),\n.probe_in241(0),\n.probe_in242(0),\n.probe_in243(0),\n.probe_in244(0),\n.probe_in245(0),\n.probe_in246(0),\n.probe_in247(0),\n.probe_in248(0),\n.probe_in249(0),\n.probe_in250(0),\n.probe_in251(0),\n.probe_in252(0),\n.probe_in253(0),\n.probe_in254(0),\n.probe_in255(0),\n.probe_out0(probe_out0),\n.probe_out1(probe_out1),\n.probe_out2(probe_out2),\n.probe_out3(probe_out3),\n.probe_out4(probe_out4),\n.probe_out5(probe_out5),\n.probe_out6(probe_out6),\n.probe_out7(),\n.probe_out8(),\n.probe_out9(),\n.probe_out10(),\n.probe_out11(),\n.probe_out12(),\n.probe_out13(),\n.probe_out14(),\n.probe_out15(),\n.probe_out16(),\n.probe_out17(),\n.probe_out18(),\n.probe_out19(),\n.probe_out20(),\n.probe_out21(),\n.probe_out22(),\n.probe_out23(),\n.probe_out24(),\n.probe_out25(),\n.probe_out26(),\n.probe_out27(),\n.probe_out28(),\n.probe_out29(),\n.probe_out30(),\n.probe_out31(),\n.probe_out32(),\n.probe_out33(),\n.probe_out34(),\n.probe_out35(),\n.probe_out36(),\n.probe_out37(),\n.probe_out38(),\n.probe_out39(),\n.probe_out40(),\n.probe_out41(),\n.probe_out42(),\n.probe_out43(),\n.probe_out44(),\n.probe_out45(),\n.probe_out46(),\n.probe_out47(),\n.probe_out48(),\n.probe_out49(),\n.probe_out50(),\n.probe_out51(),\n.probe_out52(),\n.probe_out53(),\n.probe_out54(),\n.probe_out55(),\n.probe_out56(),\n.probe_out57(),\n.probe_out58(),\n.probe_out59(),\n.probe_out60(),\n.probe_out61(),\n.probe_out62(),\n.probe_out63(),\n.probe_out64(),\n.probe_out65(),\n.probe_out66(),\n.probe_out67(),\n.probe_out68(),\n.probe_out69(),\n.probe_out70(),\n.probe_out71(),\n.probe_out72(),\n.probe_out73(),\n.probe_out74(),\n.probe_out75(),\n.probe_out76(),\n.probe_out77(),\n.probe_out78(),\n.probe_out79(),\n.probe_out80(),\n.probe_out81(),\n.probe_out82(),\n.probe_out83(),\n.probe_out84(),\n.probe_out85(),\n.probe_out86(),\n.probe_out87(),\n.probe_out88(),\n.probe_out89(),\n.probe_out90(),\n.probe_out91(),\n.probe_out92(),\n.probe_out93(),\n.probe_out94(),\n.probe_out95(),\n.probe_out96(),\n.probe_out97(),\n.probe_out98(),\n.probe_out99(),\n.probe_out100(),\n.probe_out101(),\n.probe_out102(),\n.probe_out103(),\n.probe_out104(),\n.probe_out105(),\n.probe_out106(),\n.probe_out107(),\n.probe_out108(),\n.probe_out109(),\n.probe_out110(),\n.probe_out111(),\n.probe_out112(),\n.probe_out113(),\n.probe_out114(),\n.probe_out115(),\n.probe_out116(),\n.probe_out117(),\n.probe_out118(),\n.probe_out119(),\n.probe_out120(),\n.probe_out121(),\n.probe_out122(),\n.probe_out123(),\n.probe_out124(),\n.probe_out125(),\n.probe_out126(),\n.probe_out127(),\n.probe_out128(),\n.probe_out129(),\n.probe_out130(),\n.probe_out131(),\n.probe_out132(),\n.probe_out133(),\n.probe_out134(),\n.probe_out135(),\n.probe_out136(),\n.probe_out137(),\n.probe_out138(),\n.probe_out139(),\n.probe_out140(),\n.probe_out141(),\n.probe_out142(),\n.probe_out143(),\n.probe_out144(),\n.probe_out145(),\n.probe_out146(),\n.probe_out147(),\n.probe_out148(),\n.probe_out149(),\n.probe_out150(),\n.probe_out151(),\n.probe_out152(),\n.probe_out153(),\n.probe_out154(),\n.probe_out155(),\n.probe_out156(),\n.probe_out157(),\n.probe_out158(),\n.probe_out159(),\n.probe_out160(),\n.probe_out161(),\n.probe_out162(),\n.probe_out163(),\n.probe_out164(),\n.probe_out165(),\n.probe_out166(),\n.probe_out167(),\n.probe_out168(),\n.probe_out169(),\n.probe_out170(),\n.probe_out171(),\n.probe_out172(),\n.probe_out173(),\n.probe_out174(),\n.probe_out175(),\n.probe_out176(),\n.probe_out177(),\n.probe_out178(),\n.probe_out179(),\n.probe_out180(),\n.probe_out181(),\n.probe_out182(),\n.probe_out183(),\n.probe_out184(),\n.probe_out185(),\n.probe_out186(),\n.probe_out187(),\n.probe_out188(),\n.probe_out189(),\n.probe_out190(),\n.probe_out191(),\n.probe_out192(),\n.probe_out193(),\n.probe_out194(),\n.probe_out195(),\n.probe_out196(),\n.probe_out197(),\n.probe_out198(),\n.probe_out199(),\n.probe_out200(),\n.probe_out201(),\n.probe_out202(),\n.probe_out203(),\n.probe_out204(),\n.probe_out205(),\n.probe_out206(),\n.probe_out207(),\n.probe_out208(),\n.probe_out209(),\n.probe_out210(),\n.probe_out211(),\n.probe_out212(),\n.probe_out213(),\n.probe_out214(),\n.probe_out215(),\n.probe_out216(),\n.probe_out217(),\n.probe_out218(),\n.probe_out219(),\n.probe_out220(),\n.probe_out221(),\n.probe_out222(),\n.probe_out223(),\n.probe_out224(),\n.probe_out225(),\n.probe_out226(),\n.probe_out227(),\n.probe_out228(),\n.probe_out229(),\n.probe_out230(),\n.probe_out231(),\n.probe_out232(),\n.probe_out233(),\n.probe_out234(),\n.probe_out235(),\n.probe_out236(),\n.probe_out237(),\n.probe_out238(),\n.probe_out239(),\n.probe_out240(),\n.probe_out241(),\n.probe_out242(),\n.probe_out243(),\n.probe_out244(),\n.probe_out245(),\n.probe_out246(),\n.probe_out247(),\n.probe_out248(),\n.probe_out249(),\n.probe_out250(),\n.probe_out251(),\n.probe_out252(),\n.probe_out253(),\n.probe_out254(),\n.probe_out255()\n)/* synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 1395}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// Amazon FPGA Hardware Development Kit\n//\n// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.\n//\n// Licensed under the Amazon Software License (the \"License\"). You may not use\n// this file except in compliance with the License. A copy of the License is\n// located at\n//\n//    http://aws.amazon.com/asl/\n//\n// or in the \"license\" file accompanying this file. This file is distributed on\n// an \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or\n// implied. See the License for the specific language governing permissions and\n// limitations under the License.\n`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nuVw5JhLL11X7sFlU0pAE+ly6TbXZG7ItJn3Ex9cXjSY7p1sc5OM17XcDMDqOEbaLgeEhUuwbGf++\nsY41qYpCyxKVTUSlo4RbifB6OdtPL5WbplRlVmZr6tVckowDKyf+KTfQD5yDuN/lqu/csQO2OWFG\n+FTZmZC2+4QJQc3yS24aV3ap6SiICL9zEXwFqFiBkzn/JHjRL0ul0SX2IlY2DGLf1ZP0frmZpeV5\njf+hw24P7s4xKjAFgaTp3id7hTx/VMEsA2ezH0GQbEMKybRgNRwMm93ZH7rKsmeh+vLM4uzdiiPH\nviyKgiHJcWlJF11UMelWbvVoYsF7uDJ90n/5Ww==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\ns7Yn4DABLzF4SLp/0V98P0CDCkZYnP8iqDei0IedIEX1lGPO+wDX247jQ5AIWSMu+s+1jQIMeWFm\nwwhaOWGt3o1acmXqPnf1xmu+ASh0sjaaro7Te7bhxTdbst8KbfW4m1RJX+UShZxi74/veNFylojR\nHiUek/GVQNWaepFc9Xo=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nSulZTeegbwtiqqiy6RNAoCNHsjD2rBzbr8ndOVV7AUZ0X/egfC2PVGUQ2Zwy0uxx/G5Py0ihEuGz\nMBiYAP/4TcshTSjLEVglOzGlp6fbSx9KYr1eCu1tcnF84602dfHBQHUV4WrLSSNvwXOKp/AKyOG7\n1ALfiTkaDf2vG5TjkzI=\n\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nVeIIJaaPUtlfe1VvZdR/BjuSRIXs9q5wYiTwm+LKSUDNMtXCl0A6nj2xESHweWlx4Lsjnho6VXem\n7zwg08AWnw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 7104)\n`pragma protect data_block\nwefYcOgqtn2tETmWi8Rbf/n6M5BAutN587juaTMCMKbYASYN238z7WFXImp+yjGBHm7wW2Qi2r+8\n4CRJlSWuxJt/0DjSKDEbzfKT3Ywf24s2HItiITNYHmiQcHbmwcaginWLJcD0kej9qvRWROT7Jdol\n6p1ceAC2CxqBZd8KtGKA1yOqZfjvM7YDupzNTlJ8EnI8spiXjcW/hk3QdzvAAT+3MvEBtuMYPwg9\n6lfyMWuzIMCb7mND59+z+A6Y9kmp4sJ1RgfrKaInNYqTVwGLVkKRUjCmdH7pptXLJFzQOfA5LFUW\nobrQsrQaXZr1Mz+i68t31XE12AhBmHbtN+SpVLApbX+A7sMdDFo2lpQqBa40lYnZyJF0g5cBx9eK\nu/YEW1iX6rq8HaTsVLk4BbMrZfJuq/ODD2Hp1/UIgsW2JSJqGaqwAQCFGNDS4mcRv8RLAnveqAZk\nQJ8psKOMHRMC4OGuZIkI4024u74khNdkgiCs1gth4R7narobPlg4Q1xuWpMbTFi7SaFjQWRMZYuD\nXCpsVXxX6vJGREZGrkT0uDJN8Q2kassteI7QYPLCqBCso1vuH8+WxUjwDI4MUv7K04VLAsg3wBK+\n0JIPZi/4FajT04MDy6kNpP+n0IuV23UORkPa5JOjr91sST7nORbqbnmCvN2fJXIJk7Fp9NQkdEwu\nxszleI12aemGZtWMSMo/Yw9cLBEm7dD+fyEi5AaB4AenenIBt0mhm/YqnEAVS5CyAJ4ZE7BiQ+i4\nlPsd5hxGf2V8/DRGh6IvQW83WVybzSIpKXqO6wZR7tsyNQi2AgJ+tz+mgLmCJ4qkHUYy2hX5liKy\nbPuyhZrK5eiNylPw6q423CflAgusNlPaO9suIp/Ta27JXKduOp/w4qos1f9BSXZ9DPBdjOcBbmQQ\nGKEYc4ykhwrSCAJbKyUc31uCRSR2vHBTA0uWvT1M8em3RURw8SEequIg8khij6hLbWSIZRqOVcBP\nqxurjqLk3i/fFqrn3BeY1wAlVCLZtKwtqZQ2Vm2JUaXy7kji2/DMv1EdIBqG4PjerdHcq1kLi8dz\nvQWrs7ahQcDnbtatpipQmYvFLSibcxgbv/Wy4zmPFBPxbDQ14gsIlGAGxSvfTAbdhz6aND0bYNAL\ng5AxZ7grqhvUL3vZLmRXTCr4E6K4B3SHixdvy1pjqydw4HWhrjRqYU/kYtbCbNP6Hu6T8bLYd3w/\neyGeXDpt3rX4qPYHFQh0CAJDQXBlfSgFRkGbUERcnTsFd4Kefn1ps1W1X86TjdD91zgxnVN00G7x\nQbiu2bMxC7GOXCb1dxT1qK3NCQnDZ+XmJbSRMR1V8WCT+zGUq6PAtBdtNsa6RgXpiQXQq+37FyoC\nHJEsBhWai0+IOpX0pp/Aj5uip51yQntzZYOPF0NEyXRRKkc+ApQjKOSfQPjp72Fz3Ssf6FRKD67Z\nHxpKJY+W5nNJWGckwAsl9xTFDX7i8J0KuFZnTjINILEHA2t3d+XPxSL/CBjqjYGwWr5tyet3UvOW\nvfpPXfNJEPcSDk2Tq/Ri3WnZMBs42waPIHQ5iEmPfqUSkJoRUbAQVZIMU1fuLLr3IU0Sm4NQsm7R\niBcGU3ZtCPjFCZ/JWLBtpVgS01bfyxn0w99Uw8hU6J5K7Nz4yC5rdWRo0f7JwzlMFK53HN/KerBc\nkk1UxRXXV7wMXPhAqh+7aaJuC5L4LLtPEqS6fnZpdmGeHPrsBAfGTOboziF33th9LNMlzfiCldSq\nI6Il8GGakTn5ITvWEK1zr247DtesEHNq2M/8CoP58Mjy+CXtVw9tdCVbqDikeDEMekaiA2ePeShx\n7MfcxfX1Uyio9Fel+QYF3/UlfS4wU6+gNlIvp6Kx7pwbr4NyOaZbPVsgw0apkRVga9J6O5ZuddBZ\nC8a9Iz4qs5NnSBaBDYVNu+o4RcupeeD7HaTcaOAB13glw5GYK/Ko97sTzBs+H4d+hU2dEMg78Meu\nD96CVhOJs8NdwBZrngVU1YhCZHNO1zguTlmltQQnRvVsmrKK2omvEWXhFnpifkhoxEMcARBXC6No\nGlmt/RT+zZJ1cq2e9hSUo7muggLroNn9LCdh24kSWKHLCPqQEDcs+VWql1s014FO8/YhAl+vgSOy\nMLKuB7ahyrHdqWxamWl2NjiEfqQbZhorqzecPvO3C+MIOjH+kc+8C2sjjeTlLvLEiNvSJUY2ScQq\n7k1w1wtXmnA5aCzy48N0W4dWyp4o6ggVYxUA3usZ62CEH3969mLAqKCH17d8NNiGAzTx9SvuqfH1\nPBIugYI8wdnk265EWMJ48pWELaJR84CUsyhrCdJcKZsWYFFwX0Xybptwcvdv3DrdgM1EtUw2T63a\nj52XnrbyMiLaL70QgAm1C9NM8wSkDd4p/3qJSFwm5nFZbxAT20sUjLX98hgjqgftnGHR0q1AX2vI\nGWS9EGeznXoeO0XKivK0RA2mWBAkSNmij5Ld/GIlvPk9rRtfj9f5Ea96eiOhhF5zBaI85OzzY7Xh\nHPwX4c88zzFHuo1fZAaNkKgl98ABmPOY5zA4O0wNaDZEaPZ1MYjryQWRBW25yQgBckj+lrUA2WLV\nAtKub0Syvb0DQOWSMHWbWZirghKqfXThee+BRsekENnno7s5JJaQAUKapZT5V9z0g6crTPyHR9xH\n0UR5hbvcjwVGuMKEqlS2asqpngEM1qA05Kyx3eGs0tH15B7oj7YHh9E4k0XflMmdYVhamgsxoNop\nBMfkbDLXN6Wd62I3UcksmvSKFEBT4X6wUZ7d0ee5xEqMorIiTL22CwJZEq2F2geLjXJw6nmkjmsQ\nuEoSQXdxsFzUD1DUsq/iYZXiqnoPsPOOqE7Wy7biuvztAApCx4bvTACdN5CrMbXyyijG0AB8x04C\nDvnnlL3R+YnzBPbhBOCWqOzPTDgPCWTKX7iqgxnUd/FN02uNTgBj/XfgEPYDfn6NSosMLGGO5jyK\n/EL5fWieF7VlM9Xw642jkqotOo5D1OEvpbok+gkLDUMi8uC7XRnG/+3VJpJI0xanVS4Wi67yb5DH\n15q6Q9iJ0QZ7m1eE7WxQzljO7VYDF7cPwUTRlSL1TWD62vbMcZXEY1JDOC3RUDpudW3kOA2v0MZd\nbizUm6VX34P8KVB+EoKiuW2u2lM+fuFJGRecdRHTdl9ma+WXYXrY6gHVYV9cPpwgR6QG6NgQ5h0U\nIt5jm/fEp/kp/bT/iAKAgWgwxQ7jNq7KnTdgWcudVm75OP8G7Kl36hUdVXRiRnh4F19jGHDQpOo9\nOcu2jggnXM5p1zo2+4pauk2pHmHkxbojSkSyuZDMw7NGALkigvsuTqArn9TMg2WpiiiBYP1W4fqp\nrzQRXJ0e32c9agUvg7n6iisaCrzBmamPHeBdNQvL7yVedfYyPkYuaAo+N1BfRWsj7UfA0hXExJXp\ns9SRL0BHvuDFV3IC0SLO41je/zPtegjXnwLF+r1MWLukp+D2+P6XSYAPJ+PbcpKs8Qyjqu2hj8aR\n+gs4UaHeltMKAp5YGD3eqLLrfrdVI1OhqNu6CdW6cr6ykNwIe9OivOfGrgQ0kpzi9tZ0ee99I6ij\nVpYa0Wcv7b5dMMQLLNTL+g4iXP7nOsFcOHWGAnz/V68vWUjbhAMxVypGQ1ZjMlRVvGaA+7NTG6DR\nARlTDjGD87LaapxJnCbZk7i/psXzrRKaxjqbLqtUexSO41esE/eWUSO8LoYXs4G32tyFgHuHSlTQ\nyJ2CYi+p/7E+TXbWhcWPpuxIALzg0E+nj34gYYvJ2TQqmmAmnktNBdOesvOPGUA0xWREY1KeYwl/\nnn+XI9NRI3zdWrGoWwVZcxZK+/fxGxFKR1o+yaS78liIadtPImR3vdRscgVWVBnNqiVzmdbH/qe2\nI3XKPkvviCY952zd6HPEY+2AqrK9G02vQC3EyMEIOAdIHoMhFh+j8woFa9I/dUWvZ5KMl0qd/ZBy\n5jx1Uh4Vhd1m1yVGO39Jr391I0qT80SfoFbqTMKP+cN3aY5SZR5n/v/gJ1mBuvGul5sJ4ckvn997\nPX8HxwG5r7+OpIEjM3jqRKs3SNcUaAQcZq47oaM3jYBbAcbmePUN+I0GT0XENdOx6fo9br/cSDXN\nrIrz7X+NgXR9xyjxzkxoo8LUMYGwfXa/LivuuCHd1ZY/oXLA4kkNX6wzz+EfS59w7YlQ1x6ym7/0\nlhL2fp5PLDL7Lutn6tEzDNLbQigU+AWiXbsVe9w//gq4J0rg0arJNpWk4bDTImBLn9JQrWZj7TCv\nTSPp7t/1Y+Ql8s4Zy738UcT16UGNjTkughC+eA3AwD0ue6EHENSybOw9xC8Jfn4EaF8RlD2APPV/\nT19fBHegE2NL2oSm5rJL5WvCbG+yzGJpA/1N0PlT30e1IZNWGrGHwzOZjy5LHbFQC9rb/5JcLl90\nPxNwiqyq7Y1wux6wZQAr0DQgQ2pQut2jPzMGEnRJDmv8+JFt63IZkv6sinlY548ReZpX945nKd25\n5ZIq7Cfek95Z8n3ULAnGHQrwVwOW0/VC2W6dA2qLZXt09TYWTG1PsMmZYovnoHEBsqlw9RxGfIJ6\nS3SxpXT3lX2jbLagMDjuxx3fYwMvJb6atVioJhSlysMNr8Hocg/B95SOuIK+jYAVBYbKvKNVF5Dx\nmFj9GdP4Q64FhYgUvehcWFHKGotEN+o6EIxrEi4UXphlXDJTxBtnZtpv2WIVhwq7k3AeiwW1V44/\nk4Vvaiyg2rttg6pl3VZZQfJXHpQKs1tDq7SbHxyTuawbM8NFisbhFNEZmdgPId4CUcNeeexSWAHM\n8SeRDlNWVd5h2NY0RzrpVyEl4R/VkGJsKks6mM1+rn1KgZVJ65EdnIMmWFCQJu3M8OKwIR/LRG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protect end_protected\n", "num_lines": 177}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// Amazon FPGA Hardware Development Kit\n//\n// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.\n//\n// Licensed under the Amazon Software License (the \"License\"). You may not use\n// this file except in compliance with the License. A copy of the License is\n// located at\n//\n//    http://aws.amazon.com/asl/\n//\n// or in the \"license\" file accompanying this file. This file is distributed on\n// an \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or\n// implied. See the License for the specific language governing permissions and\n// limitations under the License.\n`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nYzI6RhCTbTb6xat5gHIeU45bfm2pOxmnaHqAF/ihtojvH1fxm05ID+E4jV65ljsSxg5hk/XNYq68\n5CkBs8aMWX2C/dCynTYKfDqEpu1XOG5vhg2rSwLazHMgBBiUX8dd/TfHBU43+45Jtb+i6MJjiXIT\nLBsrAhuqqlguwXMgFHWIpVMes70PJFciS4hmicgXcR8ADn99xdNaECHKlsOyP4wal/3xETbCLOgz\nrY0WTcy6+DeDqM50GUbu/OwxE/H7hE1bcXDowM9dJ67aUow8Jz9FWmx9rnWha+w0R2idFxiRDIkF\nqo2Q/g7aiLrgZhYsdr48/+HQ+hZdLV1ht2cUCw==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nxSa4lDWJPFFHiwekdDATEy0KtH6thL6nQyd1iZiJLJlNN0m72osWSdzXVg5vlTAOLu1Djn8YfwAS\n8Ci1p8N1sdRHih0qs3bR8EdQIdQgSH6Jvo7IeitExQzPQSHZX2FFBNfeFMSNWqy7rAf966pPa8x4\nuVfwS3Iqq45mqDrB+Fo=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nMauTOqq1ePQoCVfMD6s8BkjRyvniNKLMVJv97eUg2GNKwdp6+Pq3ihUtha7atOOqdhLkbr2DWntz\nDGYI4P4MrI/o9m4u8NYO4xNDlwHAyMABzkf+86pzXRQGz9LFVwrluUGiWtQQ0Y6xlUjx0xJUwINH\nsPrEw3NmP7E+F1pVM2A=\n\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nT1wGXZJPz+3eyrBmcY4j5dqmG1h41cDh5HE8W3W6NQEuDP2Md6yWbAfQdk8OYIwa/nvJab58+7LM\nDngjbM3YwQ==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 2864)\n`pragma protect data_block\nvR7+IXoeIJpBd3RFIeE3dOK6BypJOZY90p1Ac8F+1N5uMKLd4HYmm/VAQzJiaiYp9plobe/jVyh7\nmQpaUK5vPpi7nd2BtL2p8GAoeQOQ2B+uzqNcTJSjA/yudJDdSSkw3xy3GDWxPvHsixMHDu1aDGfJ\n8+mwwNJdr7qEJ6MPXswuWq174H6HCrUpQSsWW6qveCd7SOSmP+m9kCj/KdoOlzEfBVqOxVVLDuHE\nmdotE8mGo5jbnsJgBE8IuVMnxgHmNq3bhYzIYusn+nX+X9XXBXD1Qupk1OQYf3Nwc8GYoCGPzCk3\nojQwxOvS541fF/xn9NAj3hj1T/tXwrlkkoInomWJ/JS9TdEbKyQBCtyKf59hSolXzqmLfxPRU1/i\n6AOKABIOTjDiwOrz2iwIaal/D7d72iPZTY3UExoy9YutY2AmVI0WbL29SyDQDAeiXJiOAEU/8img\nbRDyi0c1UO4F10eyBYoWBsW71tV5cBGjrszeS+H5GIS97UVOQ1qVw1mQpd3ZpLztce3VhziNRr5R\nL/FYl+AzceFYPLynkpfKUB1UyaZgNypdcNmlvTBb2AtZARRt8TFA5M5KGl1A7lP5Bap1c1HY1hgP\n9lZit/phjdAvayLwFKcoOFXpqNhcSGH75lsvcf2a8Cb48BSnfh3vgpRkoLjxoVcaekA6ZrUHTwbB\nX6jVLd61+QuRAYZ7f7Yl4dIskRKaYQctxxvT8867KeyNW/Q9xRaUaKS7M6uZRzpRbR2Hd7VaUtx+\nkxP7w5bSIASjBIctHZvWgtmvkUGiKHarC/OGkM6vIylCEYOLlBv5YgKX81CvNjZH/4CfAp7GMHdy\nrmmy12YztImSsxhrNfHTy1HGxLcnwS1kQxUNlEkq02ZEF+mEMxMumfAGlHdJbOBXn1EE2fMm5zhk\nJVI0rja3v33WlGb2R5NHArLna5PNh0UaZSC+exqb8sUxNS89jUypbtCJkBBhVMEHgv6+Iu+c3Orc\n4jkk87BGuZI8nnGUbOwO8KCeFUcbT3XrxhokwjpqlcblZ5+D+EbjvE2dAR2dreFckak3RXIuam5h\nzKjWbpv4g2qThgwWedMBFBuGEltpMNpZp1S/eng2cVDqrR0xam5E1EwEspWIZvXat+eke0hv5uDC\nrpp3/ipF0m/GgD2tmdmBsFNZNLWjK2vpFF5Y+19xYc00QpzR9td2M9pzcmboiA0JHaC4E2wVFabm\nwn4sI3BFJEiRj4F8ag8IneahRFxNinQqejokeDQQKMB+b6/TqG4KSnbL05AHAuBYmo93SwKmHlu9\niQXEOaws0ck0A/mWpinx5U4ADgASu7aqFx+7QXYYvepDs1WMF0Jhr1NU9TckcYlQ0aiP1pEKcO4+\ndbZanSWH9iolIFNGzBgZtQ+j4dVeSiCwPCyAu8c36i1/bjc+N9wiAJhheLmq6fYOSn3V19ATajp7\npM+hflNQ6GlRXV/FMbNuUM17SVqy+TjJ8LFWFQKUN9bddyJFavGHr30DlQ5U1AgCVVZLI2EuQiok\n27B45wfZ2UgyqUHaS2eJggqOS9jsDgjsES64hjIsjorQlyZyRV9nVejQk0L9+Kf6ScRxGD/joWuY\nQ9eGnJnkwq0t6nF5xWh5nlNkaBEtZeeaE7P0LqhuE9k2zskOFFF1XOzovKHBEfuCYgE/0KADYDnK\nDkDbnj2xDjaJ4qJ0Kh6HUNS/xy5CHRoQAUPJ7H9eJLm3dsWcJQ3PWQodYEKz7vilSsiy6ryMymRo\n8X0nQHDQb5vOoxwNOOn7C+LkNow4w4aKhdC2s12H5M7SRmpnQ8CcEsh50ZdxWWlSVrFXHcgPmXHE\nKE/y8isAA8ZABU5Wr4Mm+lh2lFyZe5tDT17kiQvkBiJfAoFb9nrc9kvtKxFcbtWAOYq83zVh7sw2\nkBaTJ2DxxKMWEKaXwl4xsMuCsZ6OaVhW6UcGIITe1KdfnoBTWBM+xDwv3ck5rKWGb3AUqRnbUMsK\n8DgVGU9D8My1BDQgiRzJ5c+abFZ6kTSugULXCEq9ERntrWG1M+kX0IzzMZTVMAvybi4i+lq7jTK4\n6tS2Bpzt891+3GezNjhRbQzxlZIsuZ5TQ61RU/j5H44mnEEM61nPmQPcFhcCPx/wnin4WbViJC5a\n+UT6qm5fNii4cuiJqEhTBzr0CmdFPfjnv6SSEGvYy+cOcQdo1+gQkEcKWGT5dL8IdCjZSsAQWAFC\n+x3MH32YBUYwixG/o1AV2Ko/a9N5LRIX954/UCeYOJCe5hFcD9NKhmprzKMz2xwopfnh4yoXcdMJ\ntkkrhoiNs0DjPu5mKH6hoCDZOJeAIiPoPPc01Vo8w0aoTwhCWBHYR9RSu78Dmy0+MSHhDzxzvZYF\nGTxyfwwkV1t8YkxY75K1AtaHHhQLmUNoddAFtKroQBuplzNQEYrDosfqC/CFODAVjNC6S9l3FS4T\nWbi+jtJ0lQErhQl2Xr2LEMlp/cN7o9YlZcbp5K+wlVbB4R2RHR+4mqPbm49XOdE97IeqRWR5F7tF\nOj+iOH6D9v0nKJKHLIPnUNmigwODed8KwZ09HI3FLuqIcUqTlTZABuxPhqOc8xXkXLxrH+bzJjyl\nGMuLGUwplfc2bLbueKeSWuOQitcyDYjKbPGSky8qrtl4RhW/4YI5Hn3KVmxIad1e9vrOf5Ux7LqL\nzRw7be2tFjtsqpKJ/zFMTtK56IN6FXWcisEAn9lkk+pYDkBIr/dQwZarBPmbXJQtrKEPt/iz50kN\n3JtjeFB1l3lTNEm4ki+S+kpY6PmLV2P8Xwg9eSMBe606GzPYqWZg9XOPRWuDnP71jx+Ahj5kBiRB\n83BM3i9ZyPODeLP6tz+JBiQPNaKRfdzGlBTDUVUM7xUwrRFxbqNYG6KYj+493GKo0Kcn8+yVs78m\nuMsPjwBGYieWKbse0kBY3p2T9/KtA39rxUt8p2eISqVordD1KV/vIenzYMqZDok0QHwx768MwWU6\n1q57GzzyB8hd+YPOlTz8B8BMrrL1AJId1nJfL0z4W6NNKifE0dZLB4qFxus4d2AXgfnEDT9ZHZiV\nwwi3LdybbzpsM2mseT9w2HBSIuTgqwX6kdSfRPLxc/bpn7ZqAODF2bZ/kmm+8o7YI+/CTqfj4TLF\nk2+r95/P+ce/2a2g8o+RxpYehSNSiG0BK4oa4Zd8z4zVk7DBde0Yena1bdDCid9GsPyTGcbCWMdP\nGRGhsUeNSBcWi1h9gY0V2CGUJAT/rWqV9wwXGQVV6jEfosieq+6DmNYVIav+xvxPshfeulHrknPu\nCx1u5uoilA+a8nCZxYMa8dUYCihg8Ca4ftPjbbTIH3R0+z+GlweFNkdLbSuOGomo97DYoAiuig1Y\nYMf9kHMxqu/lmj2fr8kRuDKmk7deHFbxD3TTdX3fa/FhHTCBUTs4zDhko5t1d8vSjSD1HmIiS6lk\nwVcYyWoJ8JZOq4D/TJTY3QUualQEE+Vlu6NsX7bTye24cdOhPM+Ou0szgCHhtpweGrPt0l46DKtb\nwKZVhN3jMfTSCeAbYN/RjA4Gyb7mlIDSsuKQog9l2jP8yb0dRD0NAZ/c7UPGggwWIX7G8Eei7c2V\nobqHNG9fmiQFr1sa4P1qjfM53NzWwEg2AZUaDTn1p0mkJ3YC/GfucgquVbIbz91FjD+m+ehmp3vg\nYDzcoZvNKpq5J2VBYs9iKqn9UE6FObH4YupmYYb/xcq7Nu+mjc8wMq+3g6L7cAsayrobefUwCIDP\nEoUxh8G2NibYTXadOPt7oH21Z3IDfjxOccCqE7LepfQzE/OH2E500qlTRdKJY/Tmgcekh2bUnwu3\nXlQJsZphGfJyyvZyppk=\n`pragma protect end_protected\n", "num_lines": 103}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// Amazon FPGA Hardware Development Kit\n//\n// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.\n//\n// Licensed under the Amazon Software License (the \"License\"). You may not use\n// this file except in compliance with the License. A copy of the License is\n// located at\n//\n//    http://aws.amazon.com/asl/\n//\n// or in the \"license\" file accompanying this file. This file is distributed on\n// an \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or\n// implied. See the License for the specific language governing permissions and\n// limitations under the License.\n\n`pragma protect begin_protected\n`pragma protect version = 2\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect begin_commonblock\n`pragma protect control error_handling=\"delegated\"\n`pragma protect end_commonblock\n`pragma protect begin_toolblock\n`pragma protect rights_digest_method=\"sha256\"\n`pragma protect key_keyowner = \"Xilinx\", key_keyname= \"xilinxt_2017_05\", key_method = \"rsa\", key_block\nEZ2tH3LeMVv7vukHaN/tv+pQmwZX81o7thyHVDWF7mM93FaXyNhCXTSyDdazJu7/59Py93a+cCj9\nEEEG/UMXcssv/u4GhJzoLhNbGUxPXLsX3SIGrTAhYMqUghm1uiPpNdST+Khvq3rfWs5cehEPvsWw\n8A52qamT0g71hscVONAjIadCoIAAQvF6wBVGan/xoUsiiuVj/StB/MRCaU1h33zJVnkJChMNuv1u\nGcwL2vTjF2mJSTLkMDWU4d3JqnNNe6JLK5eokUOlzu7E90SIv72KLBebeiWgyJXoUTk3vuN6RBcl\n1NLulevXSjI5J1IzTMQ8KdMirHBaVA6r1l2Wsw==\n\n`pragma protect control xilinx_configuration_visible = \"false\"\n`pragma protect control xilinx_enable_modification = \"false\"\n`pragma protect control xilinx_enable_probing = \"false\"\n`pragma protect end_toolblock=\"rUY20Sun5Njk38TaHPm9PEsmv9niNjWSTL+22BD4WpE=\"\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 7104)\n`pragma protect data_block\ns80ewUsMopuQpWnFB2sB+ONF6yKt/CFEoFhY8eN6Fd++8VwoecJwX+D+xdDD1B4a99zC2wgLlCPa\nLpG4B34md3a1iLti2ElPTT75bw6YhUJ3GFvtvWk43x4QV9jMJaVTQIQQC5q0jUynSr0bHfYCiI88\nyr6/+srQ6R6y+eENcHfUzONGqx+BfCa29/UbSZohsT1dVC59xufibiI0SvLZRvICksWXk9bL3dow\nWxrDptbLgNjVBIhyLPwiuQvDtZ5PMZWKKhwF8c2Kh4IGBpy4tY8doLEbF5CaNIcRp92hAQ/MOEYh\ni1gneLVYlLQiQR8nlBGPcYH4u7ymoTFvL+Sx0mMJSAxCrFziTeNdzNWf5te5fh2RxaZ+6l2QS9Zk\nOxAMKLy0ZmD/ND/8AXlSsLUughpPYFeij8vZmZ+WsDCp8B5ibGhpEZrjrZQNTgu0HU4wsgr3jbiv\nyDCQJIMTSWKKGwDHgVjti4ctxK+IjUu8zYEAdsjlLFKx0rGaJjnCGqD9L0DryHXvfojIT5xfvR8C\nqy5bTiLFSQawaXjWjJmXgdvIxazoE7yIsDENaKMCBdSafJsNkx+O/MR0plWJ/Pgx04t/pEP5Cy6W\notlG94pAmM47ogF4MnMHRF+rVpysu9p8m0sl3rUiPHfRhIOFWgHRKk1ZC3HOo4TQmeQaGWyTeWvM\n9OlrB+DE2U4vCjeoJV9O+vKiKC8tq3z9IfSvRqcW9Fhk7dEjs3qnCPaD1kYi8+UZCio/j6eYf7UN\nUKhq+I9qxsyR1BmhFNu6Af6B3hAY5Qeb6UH/KMbqHCoGlJEhXsfes2Kp8BvqBfl8/CdHhvLpK0aX\ntAfF+W+Uh/DfOmIE4/wtmA8TpolUsdEHfd6qFWx74M/+vi1cZgIN2YkyZ8GWTixSjIbciGE3+T5f\neVr2/IrDuPSuAn7sq89UGWxnDYMorw7GGSt1X28kEK3NaFs9f87SLlx0k/Z+/MFXs8PPrf5eIv2W\nLC0Y0bSmQY4Fk4j8+thYuNvWqXR/67m6PT0NlzZa5bDgn4+htU2HhH4eLs9ABfPQLT3pa2R5P2HP\nscuqY0NDBfGiyCKbUsAAqrURj+BP4avJ0C0mm2SM260c/HYpjQ+unBaY0G0yc9iXMTCmEDor4qav\nlQw2qFwUTFdc0WiZoeO80OZd27i9heulJJ301rqnlDvSz/9Fk7cUz7GFiKaHVCTqL+/u5J8xY+O9\nN/ahSBFZGwQR/ODX+M3OGTfJi3ZCKECD6qTDlmZqjqXd24O3YWSIo2+IT6QVV4XPZoXkLrOmVDnI\nr8LK+396XsuJ8HnkGihELPBRVQgg/Y2U/kCdTPFL9/+0rtJdAxLNGqJOdEeUz5gW9g7i+bvdSiyC\nvcYoq8wmOhoVRi+spru+R2/MUsriYLHXx24rxpeMNG04lEU10Hor/xAcwgmTI8tNwDJB4b0r80JM\nr+swUyO06BPv9ZsbHycD7I4g10HyBw/mu20EZ/yf5QcjEDjBrIdDIZPl+4FwDjq7McfG2NR6Vwau\nD5IS7YrxlAThTO0K1P2pE9MbOgfEQ1Rk4DZWkKil33leAcmvydIcK3HYtwtDU/YQPEcxWx448JRL\n+qaDsGmAxIA4wczgpXq7YKRq+f+3Hmu+PfOUTEUnwRQIjVl8R6IOpAh0WOMZQWCdOgrGPjGlCuRG\nSj34xTHAXX0+vONpgapnAJgA4gi493EuFeruDbwCdyanUOvJqUveFWtpF/0aJlHU/Df1tiLryl4G\n/GwLb58dMvdwNDSQrE0G3RroxyiyvK+EfLIKkCE+nHmsoBwCOn3V0+ZdOFfuj0Dr6dAyCYx6yDno\nyhkLi4iZLHxkUVs6Z8BKFIxza/StaoqYG8iGqRhRdGH0JfU1H7J/A+yjerNS61Ap4SQ7Vm1v/f7h\n2iRJeYDTWlK/2fL8HZBAG/PAjHDQf3E9YuObk+Xgu9fN1de5T5A1lQRGuneOwRHOofo/EXNtJAq/\nOl0V+IO/oPnzm9DMJrVbAVHm30VyzW9VxHsCliYJxoVEalwZJybjLwk+FdHFmb9246qlJwJbWnH4\ntXbVHikM/TbIGn4q8M4UCERAA1I/krb+5dLwu4egiG7NkuoUuuoABg4oN7dXc/r/Mm8NEFa+P4Hw\ne+1sp9vGpG+kHMIhaMTEDLIa/6KzlIXRsYsdYa0QpnyY06TR4l0Gy4ytHNPGLgqBD7PviK+eZzvf\nP8nygmraTiTwNwRtqoF5DkLMPY7KrNhHdsJTTgHFL/vhwfvTUgukqPrT5ehF3IK9BvQCfIRVdvDr\ngwbBGNbtI4SJJkYmHZH/m/KGnWlqoCOXNVvjVDavftAXr4mNtx5vSqVFx+9OMVmYlyn0EUCCGYtu\nEC3KGWAXVkH646lAaw8lNgp5NCLhLM6Hx3e+9V6h/Q6I/QDjA7/6NUF5Zf/Gcjobv2X/ey8c6eDl\n284v7ZAE1oBlpj8Y0/yDyt9KKkpq6RP70BnA+rfwWmLP4pygJWuO/cPHybgeC8CqCZ7GoeORZAXA\nU4r33uwqrqnIZSGSYXJMsnsybG/GrXXAIwRo3bH6SR0rX6gQJdotqEgabVXMX0P0hpouKaVn0M68\nuF9IZxrO+3PD+j1RpJ8LJHpEaJwyION/7PgQyBNXJ0SBSmbP1LLmxStNb4a9PMJ7VQO7xcHrVVXw\nlfMG4cbHHGmohg8vRFuAyWwTXUlQmISjk6tTQOsdVWJB/BoXku5d98fMhEEnHoZ0jJ1atIFuijgr\n828KNwZdmI3SZSmD5lVONV/zLFgtWrlNp7hcnl4q49r1tG8YgA71mEeB7XFAciZXDdRX10DdKQ/8\nueUhQ7XYmyKp+Yl5ILHf7G8htGitx9q5hDLIxDq8h3Z0R4PaX9WK87RP+mog7nObs8ajRs8bI5Rm\nu0hIk8VsLXzRr7pT92a89EPnBnGpkAEdBziznE+hxBHR5o4teEJvce0yQl52gWeO2dcql9BozfJE\nFL9If/OEfYyQdWi8qzS5fsl53esw7AH11jwoYPsxhQUUmeH1dAxMi+RkW3+WaQOgEJjRZxSIQJqL\n33lwu/jfnmRXWEII7s8SpUseLgIeo7HT6+ZmveNMOw8uguta78FJfrif6tpA1KBoCkNnb5bxhmb5\nzDhe/Q4Eg0UW7/VSpMZfi7ypuyIGzdWCY1KNWeDovzco0xeg13BFsxiVw29YpKKRcFQTLsJt6OWh\n87ouBHuJBg2984G5TcShmKAsBR8D0ZPEACu0MrWXeQw34UPWNdtrmvq996W5xNQHnqN8lPAWBvVI\n9rrYk6I2uook//PGmgLi/1WDq3Gix3OSNfPkDtUvbQJA1pEXOgYASEjgdyob1B5NpHQguqAqG/NP\nCBILzgyuQZ0/CDtPua+otMbnSz1hhu9UC8Na/QyhKNT0yHY0ug2C9+sruPezZJTWMnmEXRjxRPuz\n21KqzD4jhi/g6BMrG4QGVwUhahok3g5FtRrmVakP2xzBwhMX1cg/pKzY9ne9lAVLtwctLnxPlAzs\nGdi5Q7fg8K2NaopGE/r7Pv5DggEiCQ9Hi8nXlRSJMMKJwbFjikNyte8r4eQocIjYNj0UNQETMbk4\npe2gg2x7enboyWj99a97kTLiGsUF9TwCN287ECxoUJxcvX/1kbUGR+Xcp0y1L98rVe0eXeHsju3U\nUgzRncsty6h4r+hpjjBLgWmv5AJGYXEQ2BY9IvgZ24vfeM3HufVPfJdh/zmH/xq8f0MT5fPvMyVL\nle16t9riMoGhkW24elZpnNUmNLz4sByGsu23+ad/aelyWV4QEuFzRuUbM5E7bmkb1szuc0njsNcx\nLWcRDU7MTOM2fQ3FCQFxicl2wh+vW48qbL1ZT1JmiDqb8QYCEutTKcar6njaeXvBlFfiBTXdWp2C\n9X84Vc2EB5jCk1F7rUTlBtbGteCdD7P28n11GyVA+pJu5ixjtgg+tB9hxn6h/JBj8jChM+MC2PRB\nCZXXu5bTgSwmFO6yjYsFBkB145FV5v2dsyQFO9OgQZnZ21xVj2gik4U5hwFDrJtHeLUfmZ2cwR8P\ncoevnuwsBDXk4At8S24i8lNr4vgZRwV5SeMuVbH4V2ma6vze9/Ja8i4GxWzTlexnY4mdK6Bx7HFx\nWpAK3k5KxaKAUYf4H5I79b5ooSFwEhqeiVP5s/Ee3eGnqD50nAmNbwNVRfotlVzqtIljbTAPOHGP\nByBkZ/BRg4DqPQv/cn3Uw5zzE0jBTfisKxUrglduvQ2alHDWBbQbXcgI5VRf6HmZumEEnHzxByrm\n2EcwT3aOsJISSctNqu0oBvFtYuIFegeIfRZZ0HL50kRBPFsfJNmyukH9pWUsc89MqXDoA8MMJYdk\nHHbdKQeWkjL1tI4z4alE5OrwZeH49ome+bTTpxv02lLxfprer07a2Oq7k5q1Reql9rOR4QqiOMuM\nZyrwD1sLXYLE/6AmGYTArRQWEM0/9pehNoZvWq4Ilu8z8Yh8oydxsCCjEkTshdOUQ43xmPI+1/gZ\nBHpyvU12X7xqEd1HqLLFiGhilgpjSp/Fsbe4VQbfn4VZ/nUfYBGodDEK+gyjt/OT/atph4YN3JhS\nfuhY0wT3zaZbBXVXrt8yhz4IfVDN9d02WMFaBvPKYuGjiyDL8+CsYklbIhGZ8miP4nKqs1sUTyxZ\nn+K21cQoq7Ojc+A9Xo3KI00PBTw1lZA7EhzBOV2E9LjvwkadmwaRQvlFEk+Ocn5Hin0wkKeINBEo\n+SAMJFr8tRLPDnumTaH+zKX+VRFc3a78jKnRamRCqiZ+nVobBjl9sQT0rl6/J/Q+v6V4munc6L+/\n1Pdq84XnKdcQOj4fjFFVUzoyw2enbm0hc3ViDLtensCWwA0pa9d1mVjtgk8oweDzsRRtyCmCBX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protect end_protected\n", "num_lines": 165}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// Amazon FPGA Hardware Development Kit\n//\n// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.\n//\n// Licensed under the Amazon Software License (the \"License\"). You may not use\n// this file except in compliance with the License. A copy of the License is\n// located at\n//\n//    http://aws.amazon.com/asl/\n//\n// or in the \"license\" file accompanying this file. This file is distributed on\n// an \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or\n// implied. See the License for the specific language governing permissions and\n// limitations under the License.\n\n`pragma protect begin_protected\n`pragma protect version = 2\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect begin_commonblock\n`pragma protect control error_handling=\"delegated\"\n`pragma protect end_commonblock\n`pragma protect begin_toolblock\n`pragma protect rights_digest_method=\"sha256\"\n`pragma protect key_keyowner = \"Xilinx\", key_keyname= \"xilinxt_2017_05\", key_method = \"rsa\", key_block\nvxYrgyihqymJKAP1U28sgDSyhejSTPCyoUjaqdt5WpBI9R20BcLbWe1TkPoIfiLoe5JcYoh8zcEy\n0EJbDuzXNpMlUsLCLACJKyYPFgeXm3JJjqNgDHxdT4SnSA+6wAkcS7u+0KKbWdDKoDGvhR0h8tUN\nw3uYUVG4qKcNbH3Lj2AtVob8BETwf+2i9aj1O6RkfV8/w5fzT6nAZbgaFIeP2n5jyxDhbzUod7zq\nvpH2JIlIoFJiS2SJPVXJnOMeLJjESPv4qaVrQETlfkJzB6BM+S9FHJwwyltBkbbw9lu2CJhM67vz\nXaH48z6tgRVlzhHMwLlMvbLnZdz9VLTy0g6N/A==\n\n`pragma protect control xilinx_configuration_visible = \"false\"\n`pragma protect control xilinx_enable_modification = \"false\"\n`pragma protect control xilinx_enable_probing = \"false\"\n`pragma protect end_toolblock=\"x+L9+fi2J1WDHSxBWt5lueyga5qkA+vDtQM6hMKDc1E=\"\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 2864)\n`pragma protect data_block\n5taEktq50cRsA2FFJCoSas6h/TCKO1CVAPgsswMGXGhqo89jI3VrZTh7SQbXb6QW5t0Qsr3Qm8UA\nLM3S186QWkudLr+GQUVrHMdLFhNN2Iq5q4wm4UTrtKDiZnG6U8shDJV0wIx6iPF0qWV6rxPoWmJM\n6vMB1J2dmpnHqjvaDEVjrjMJqeVARsfjyZPMkKdOsdZ4JABmvQlvkB3awwuePZ/fmtoQYjy7BiVQ\nbRykXvYs7Zcu7s/tZYAULiw+XT+bzD9F3+/dUBmOb4MDnJdEfide9Hjb07FrSGHJhYsigWpSnV7E\npLZ4k2SUT9FImUFhdq+2uH6qaY5jjJHtS4Azh4O5PagpjFuTrxngrBALm+RLx4yzWvnikosgRTGB\nuMC5E743faQ1fXmzhJtsYiCjNw2U1NgzTahU3gdIpPXG4ng23qPBlFBVPPw5CSTLsgkfN3+dLrAn\nseCaDcswFoN6ircxRELdg8PQ+VNXc7QQzTB1s3RuFigVLqu5YZ7VjSgJ7C1/Wb/RfJUEzEioMB3J\n73SSim6WfdSOUfzck+kREOv9ncUyCk2g3gvCSl9R9+TSJF/OHvAzegxI7s3b5DoYCnl4X5pJ5y8s\n5bbkLzpxFdhwxWXokP2GJ7hUY2TymJWPOw0yydphTXzfbDiITc6IeMeG18Fa3Y8JAtKPTMfoYKZz\nbf4KajYP0SWreoTpr/tsXqJfwXqDUgnAqeySH9cPyZmdocS5K8qxtT/tgDF4fb5DEQjv4bnxnZoo\nGGjJangAk+DKFm9EaqmJnySi/eiBQ+IjX7pS+71GFFQXAbyky0xUwD4p0bGfJNOOGyP2vi3OP2hC\nxWTgfnghzTlwZUa49zWoyqLYAxe0RadRXo1ktTwQcqAyWxPz6aUFnFyzC4WgJSVYb1/xUK0FAhCv\nAWBsqO14dK256a1t7Fk7oAJKwWa4KgXWnQkg2ks2IbiWn4NXCcN6+wOtCEBEq5ubcahtYD71iVvx\nikpW8w1LwDvsf4wC7E8Emk4/nRaYEvqnuDOXWFVox6O7psO7tY9cJs80XXDRROEXVEKSnbL1cS7H\nfMuMags3AHXr+ylq14rwmKgAJRDSR0u0R6nLbXEL6KM1NLXSOcUjw3/LXEWRnfAkj6Yf6ub/C+ER\nr2KYiyq5/doLwcVIyAojamSNmWPg6LeMnE48RIBnzUPm87UHajCzraztpiVzn85brW/qqydwYOZB\nWuIDmrAPelZvgSiOYKGeL0j764Idfi+zRHHehnKhelB4GJJBwt0EsFxZ0DOOz+PWUvp32JDsdXfx\n8uKmWb5Gma9ylHp5FSkVZsQbkn4PmzK72UwaUQFx1LvrQ+fi5DEUpDmkrkapEhBmsMq4dQ25arLt\nO2aGbF+w4SqF2IygkHe6GbTJH+2xO3ezQ9Z5nzQUBEcdyYSwos2WYy7VjSJHmtitPQjD432boeQj\njg24Vv4WttYBdXKyQNpclDyDVeXFS4YtFr1YVDFu+DYHKsYP2w4Axh62q65xeK3do1cTpT2nIVyB\nslqUvk13qIH1WWUDTXOLvHuGg7GgqVhRl17G1AhAR+ivzxvn+BN+6apWIb3oZH/1Ig8BbjkechJG\nyqWZcpCGrcEEOh3Ld/b4ZfvAlEAk1L3uvW1qNMTjyOn96iMj88mGfoULkQlA1ynrUxAvi/u4BBVE\n0AHUmX4S93UaltYkZJAjRbnhWZV5Flhd87wWnbGidmqd1mJmyS75csuA6vZ1JlNr3GEZqY1a69bG\n2F5MFJ3Zlcs8U8D7mdCMCBfZGjoQ7PCIBZ3bWKWTCHfko039pH0ilSTz4Vr/mcKh05hX+Nzcs8t9\nTSD6y1DMWKMEJgGMcZADjQsIcIzOBcqcXWnc7S0RY1blKGkNNBcDz+MWZgdd6sf+JZTej9sblrue\nkJQ8PZfHrbK61Cb9RK4+oZg4fPtdNsBDDhlga6DVDJb0DbTHRFpDvUMQwMRbFq9Lfty+lAElnf7u\nTa+/S+uc0Gn18671sm1/Oe6HYROdOG+x4YNCxlwU6VzICpEcv7dXYOZL0fdRa8VG957QeoZvgiuv\nQ6cbSXf/evWVXtN/snCnsmrF44kSZxMwYtKVBIYQVm1V/ve1c1kD8eMUGu4BCOykD0ma25e0BboL\nYTwhJTeVkRHsUP7tL87gLyqfsMB2TxYCeMhZ4Sp+AzB6wQVgg1dbgRarT5tx3gUH92pf+PXNrGxt\nMWSyPLnCk3GS7OXK1Sgod+pmzwtlyCGhypTVYNXmIWyZzmPro/zjFG4aeVZ2qpAO3Ep12/YiN3uZ\nojJqdDy3PXPAwq8TUFasbVWAxZGdkS4rrPFx4zIKCZJh4FzM/DgiVStDvn7sNB2ZOyhVlQEuksAl\nEek3OL9PBqkcKmjByLM0ykjFcuI1WXfw1cT/ntVWvLNsLWH7MI5/anG+Yh07FNNhOCRu0sWec8hV\nbutTOkBWjm5UUV4AJSSvRWhgJ+/FMjXPQUvEL8IkAdtZpwNCQmdbvS5VmKMFC/4DTCHOnqpVQ+T2\nsIkWpbPqUrHSM4Af06D2PeiKHgI+Xl/rBmNLI/Lij142EAhapTf8U8ct61FEUupggAmQfjO7ijtM\n5xtKWVMnymCXH30kUgqzjmuBK/+o3a4kkmzMs0KzWMGJA45gM7N/K0FywSBBEJdIqG54fW6IsbpW\nm/Z6iOXVPFnDIg04hh8ny5B1XrGmsg/5hECNTDIj0iIzI7CKr8sE4dN8phQrwMlKQ53rOCdzuvTi\nCYLgF9GBa/NEFw0Jut2nHn90X2AITHpM4tRgGTDoWcJUQkKxhvoKFKogeo4S4OiPan/VuG96vvoy\n5vJwvqHNIGqEjrraUCHfSTRhmOAhMsndoJUbMeS1Yu+2fUCzp07aypRaA/+nXUEyP1wn6/h2sp+f\nrpc39ww6BK/ozcBRNVYth38sf3ql7ZbSsErm+Exbq2tivUVp5DsR1P//Kj1H6lPUkbPVj2kDvwTi\nzF+S+T+6rS18i/vKYqz7rggdQRX9xoYvw1as4tCRQSs3wSsgW17YzPW1L74LqgZMbMbPKQxJio3G\nlFcbHQdHNt80DX9wqDu++zDI9mF7CC/s6jxnZL5WNXmlxwXD8RQXQKl//K7pKN/LO2qxAWCqGzOh\nQq00M8IpLWaFMqpIDGS8oZQWIh74sPqstcpgTJN6vXMtSrvdSjrPxsgxEiVPbLbXCIduWyanCJnX\nJ2eFxR1N9hshNBNOPi9mrLlHOXUROpVkvvKMXMNCpeCoYRtXVZiBh0GXesz/kLYTYSSqQNjlKW4u\nIg8hXlP1uGW34eyrd7uifQpwQUHSLvXn18f1ldLYH9XoLp3qElinpFPm6dp1hTcNPtFULXYK64Fj\na+92yCnj7/stq+5UuDereuLSe3icjDZYIBo8Oz3YwHP9bOe+GWanG+AtuPqE1bU+k6OsMuuCkbAz\nv7MEUbMSxKQDzzq4ObJeu3pwHw6U6/UAzSdLtJiZ6bU2r2XrSkwW15/v3+Ren7nEXjUQSEReo2Fj\n31H8jinz+FpmNhEe2mhFIg0vbkzIznHJwIjrqNAVsX6LejMxubwI/TvbcgQruQvR4nMmlBV0txet\nl2fcLkt33a3wMFaS1i0GmjfY0zbZN0NaEPwO6xYKe4zIy99cJ/mIJT9KTHbyWd5JB2MaI3Hrue3N\nP0R+NXDfASQi/zgWQ76EuyLK8F3RDXC/PNpi5KlHxPgiac3aTNUAUp5Lr461CY4gk97xV68zDyOD\nFl/rZwacKC5ffSrSDC0RXeIpN4Mw1zRSBCvMnATTxknYmpVnbU/gP+6VgFVKlINOrTv2AOjbNIr1\nUvDXqRks7iP9II8C2V8=\n`pragma protect end_protected\n", "num_lines": 91}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// ==============================================================\n// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC\n// Version: 2016.3\n// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.\n// \n// ===========================================================\n\n`timescale 1 ns / 1 ps \n\n(* CORE_GENERATION_INFO=\"dds,hls_ip_2016_3,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xcku040-ffva1156-2-e,HLS_INPUT_CLOCK=2.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.100000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=6,HLS_SYN_DSP=2,HLS_SYN_FF=2200,HLS_SYN_LUT=2536}\" *)\n\nmodule dds (\n        ap_clk,\n        ap_rst_n,\n        m_axi_DDS_OUTPUT_AWVALID,\n        m_axi_DDS_OUTPUT_AWREADY,\n        m_axi_DDS_OUTPUT_AWADDR,\n        m_axi_DDS_OUTPUT_AWID,\n        m_axi_DDS_OUTPUT_AWLEN,\n        m_axi_DDS_OUTPUT_AWSIZE,\n        m_axi_DDS_OUTPUT_AWBURST,\n        m_axi_DDS_OUTPUT_AWLOCK,\n        m_axi_DDS_OUTPUT_AWCACHE,\n        m_axi_DDS_OUTPUT_AWPROT,\n        m_axi_DDS_OUTPUT_AWQOS,\n        m_axi_DDS_OUTPUT_AWREGION,\n        m_axi_DDS_OUTPUT_AWUSER,\n        m_axi_DDS_OUTPUT_WVALID,\n        m_axi_DDS_OUTPUT_WREADY,\n        m_axi_DDS_OUTPUT_WDATA,\n        m_axi_DDS_OUTPUT_WSTRB,\n        m_axi_DDS_OUTPUT_WLAST,\n        m_axi_DDS_OUTPUT_WID,\n        m_axi_DDS_OUTPUT_WUSER,\n        m_axi_DDS_OUTPUT_ARVALID,\n        m_axi_DDS_OUTPUT_ARREADY,\n        m_axi_DDS_OUTPUT_ARADDR,\n        m_axi_DDS_OUTPUT_ARID,\n        m_axi_DDS_OUTPUT_ARLEN,\n        m_axi_DDS_OUTPUT_ARSIZE,\n        m_axi_DDS_OUTPUT_ARBURST,\n        m_axi_DDS_OUTPUT_ARLOCK,\n        m_axi_DDS_OUTPUT_ARCACHE,\n        m_axi_DDS_OUTPUT_ARPROT,\n        m_axi_DDS_OUTPUT_ARQOS,\n        m_axi_DDS_OUTPUT_ARREGION,\n        m_axi_DDS_OUTPUT_ARUSER,\n        m_axi_DDS_OUTPUT_RVALID,\n        m_axi_DDS_OUTPUT_RREADY,\n        m_axi_DDS_OUTPUT_RDATA,\n        m_axi_DDS_OUTPUT_RLAST,\n        m_axi_DDS_OUTPUT_RID,\n        m_axi_DDS_OUTPUT_RUSER,\n        m_axi_DDS_OUTPUT_RRESP,\n        m_axi_DDS_OUTPUT_BVALID,\n        m_axi_DDS_OUTPUT_BREADY,\n        m_axi_DDS_OUTPUT_BRESP,\n        m_axi_DDS_OUTPUT_BID,\n        m_axi_DDS_OUTPUT_BUSER,\n        m_axi_DDS_OUTPUT1_AWVALID,\n        m_axi_DDS_OUTPUT1_AWREADY,\n        m_axi_DDS_OUTPUT1_AWADDR,\n        m_axi_DDS_OUTPUT1_AWID,\n        m_axi_DDS_OUTPUT1_AWLEN,\n        m_axi_DDS_OUTPUT1_AWSIZE,\n        m_axi_DDS_OUTPUT1_AWBURST,\n        m_axi_DDS_OUTPUT1_AWLOCK,\n        m_axi_DDS_OUTPUT1_AWCACHE,\n        m_axi_DDS_OUTPUT1_AWPROT,\n        m_axi_DDS_OUTPUT1_AWQOS,\n        m_axi_DDS_OUTPUT1_AWREGION,\n        m_axi_DDS_OUTPUT1_AWUSER,\n        m_axi_DDS_OUTPUT1_WVALID,\n        m_axi_DDS_OUTPUT1_WREADY,\n        m_axi_DDS_OUTPUT1_WDATA,\n        m_axi_DDS_OUTPUT1_WSTRB,\n        m_axi_DDS_OUTPUT1_WLAST,\n        m_axi_DDS_OUTPUT1_WID,\n        m_axi_DDS_OUTPUT1_WUSER,\n        m_axi_DDS_OUTPUT1_ARVALID,\n        m_axi_DDS_OUTPUT1_ARREADY,\n        m_axi_DDS_OUTPUT1_ARADDR,\n        m_axi_DDS_OUTPUT1_ARID,\n        m_axi_DDS_OUTPUT1_ARLEN,\n        m_axi_DDS_OUTPUT1_ARSIZE,\n        m_axi_DDS_OUTPUT1_ARBURST,\n        m_axi_DDS_OUTPUT1_ARLOCK,\n        m_axi_DDS_OUTPUT1_ARCACHE,\n        m_axi_DDS_OUTPUT1_ARPROT,\n        m_axi_DDS_OUTPUT1_ARQOS,\n        m_axi_DDS_OUTPUT1_ARREGION,\n        m_axi_DDS_OUTPUT1_ARUSER,\n        m_axi_DDS_OUTPUT1_RVALID,\n        m_axi_DDS_OUTPUT1_RREADY,\n        m_axi_DDS_OUTPUT1_RDATA,\n        m_axi_DDS_OUTPUT1_RLAST,\n        m_axi_DDS_OUTPUT1_RID,\n        m_axi_DDS_OUTPUT1_RUSER,\n        m_axi_DDS_OUTPUT1_RRESP,\n        m_axi_DDS_OUTPUT1_BVALID,\n        m_axi_DDS_OUTPUT1_BREADY,\n        m_axi_DDS_OUTPUT1_BRESP,\n        m_axi_DDS_OUTPUT1_BID,\n        m_axi_DDS_OUTPUT1_BUSER,\n        s_axi_PROG_BUS_AWVALID,\n        s_axi_PROG_BUS_AWREADY,\n        s_axi_PROG_BUS_AWADDR,\n        s_axi_PROG_BUS_WVALID,\n        s_axi_PROG_BUS_WREADY,\n        s_axi_PROG_BUS_WDATA,\n        s_axi_PROG_BUS_WSTRB,\n        s_axi_PROG_BUS_ARVALID,\n        s_axi_PROG_BUS_ARREADY,\n        s_axi_PROG_BUS_ARADDR,\n        s_axi_PROG_BUS_RVALID,\n        s_axi_PROG_BUS_RREADY,\n        s_axi_PROG_BUS_RDATA,\n        s_axi_PROG_BUS_RRESP,\n        s_axi_PROG_BUS_BVALID,\n        s_axi_PROG_BUS_BREADY,\n        s_axi_PROG_BUS_BRESP,\n        interrupt\n);\n\nparameter    ap_ST_fsm_state1 = 3'b1;\nparameter    ap_ST_fsm_state2 = 3'b10;\nparameter    ap_ST_fsm_state3 = 3'b100;\nparameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;\nparameter    C_S_AXI_PROG_BUS_DATA_WIDTH = 32;\nparameter    ap_const_int64_8 = 8;\nparameter    C_S_AXI_PROG_BUS_ADDR_WIDTH = 5;\nparameter    C_S_AXI_DATA_WIDTH = 32;\nparameter    C_M_AXI_DDS_OUTPUT_ID_WIDTH = 1;\nparameter    C_M_AXI_DDS_OUTPUT_ADDR_WIDTH = 32;\nparameter    C_M_AXI_DDS_OUTPUT_DATA_WIDTH = 32;\nparameter    C_M_AXI_DDS_OUTPUT_AWUSER_WIDTH = 1;\nparameter    C_M_AXI_DDS_OUTPUT_ARUSER_WIDTH = 1;\nparameter    C_M_AXI_DDS_OUTPUT_WUSER_WIDTH = 1;\nparameter    C_M_AXI_DDS_OUTPUT_RUSER_WIDTH = 1;\nparameter    C_M_AXI_DDS_OUTPUT_BUSER_WIDTH = 1;\nparameter    C_M_AXI_DATA_WIDTH = 32;\nparameter    C_M_AXI_DDS_OUTPUT_TARGET_ADDR = 0;\nparameter    C_M_AXI_DDS_OUTPUT_USER_VALUE = 0;\nparameter    C_M_AXI_DDS_OUTPUT_PROT_VALUE = 0;\nparameter    C_M_AXI_DDS_OUTPUT_CACHE_VALUE = 3;\nparameter    C_M_AXI_DDS_OUTPUT1_ID_WIDTH = 1;\nparameter    C_M_AXI_DDS_OUTPUT1_ADDR_WIDTH = 32;\nparameter    C_M_AXI_DDS_OUTPUT1_DATA_WIDTH = 32;\nparameter    C_M_AXI_DDS_OUTPUT1_AWUSER_WIDTH = 1;\nparameter    C_M_AXI_DDS_OUTPUT1_ARUSER_WIDTH = 1;\nparameter    C_M_AXI_DDS_OUTPUT1_WUSER_WIDTH = 1;\nparameter    C_M_AXI_DDS_OUTPUT1_RUSER_WIDTH = 1;\nparameter    C_M_AXI_DDS_OUTPUT1_BUSER_WIDTH = 1;\nparameter    C_M_AXI_DDS_OUTPUT1_TARGET_ADDR = 0;\nparameter    C_M_AXI_DDS_OUTPUT1_USER_VALUE = 0;\nparameter    C_M_AXI_DDS_OUTPUT1_PROT_VALUE = 0;\nparameter    C_M_AXI_DDS_OUTPUT1_CACHE_VALUE = 3;\nparameter    ap_const_lv32_1 = 32'b1;\nparameter    ap_const_lv32_2 = 32'b10;\nparameter    ap_const_lv3_0 = 3'b000;\nparameter    ap_const_lv2_0 = 2'b00;\nparameter    ap_const_lv4_0 = 4'b0000;\nparameter    ap_const_lv16_0 = 16'b0000000000000000;\n\nparameter C_S_AXI_PROG_BUS_WSTRB_WIDTH = (C_S_AXI_PROG_BUS_DATA_WIDTH / ap_const_int64_8);\nparameter C_S_AXI_WSTRB_WIDTH = (C_S_AXI_DATA_WIDTH / ap_const_int64_8);\nparameter C_M_AXI_DDS_OUTPUT_WSTRB_WIDTH = (C_M_AXI_DDS_OUTPUT_DATA_WIDTH / ap_const_int64_8);\nparameter C_M_AXI_WSTRB_WIDTH = (C_M_AXI_DATA_WIDTH / ap_const_int64_8);\nparameter C_M_AXI_DDS_OUTPUT1_WSTRB_WIDTH = (C_M_AXI_DDS_OUTPUT1_DATA_WIDTH / ap_const_int64_8);\n\ninput   ap_clk;\ninput   ap_rst_n;\noutput   m_axi_DDS_OUTPUT_AWVALID;\ninput   m_axi_DDS_OUTPUT_AWREADY;\noutput  [C_M_AXI_DDS_OUTPUT_ADDR_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_AWADDR;\noutput  [C_M_AXI_DDS_OUTPUT_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_AWID;\noutput  [7:0] m_axi_DDS_OUTPUT_AWLEN;\noutput  [2:0] m_axi_DDS_OUTPUT_AWSIZE;\noutput  [1:0] m_axi_DDS_OUTPUT_AWBURST;\noutput  [1:0] m_axi_DDS_OUTPUT_AWLOCK;\noutput  [3:0] m_axi_DDS_OUTPUT_AWCACHE;\noutput  [2:0] m_axi_DDS_OUTPUT_AWPROT;\noutput  [3:0] m_axi_DDS_OUTPUT_AWQOS;\noutput  [3:0] m_axi_DDS_OUTPUT_AWREGION;\noutput  [C_M_AXI_DDS_OUTPUT_AWUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_AWUSER;\noutput   m_axi_DDS_OUTPUT_WVALID;\ninput   m_axi_DDS_OUTPUT_WREADY;\noutput  [C_M_AXI_DDS_OUTPUT_DATA_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_WDATA;\noutput  [C_M_AXI_DDS_OUTPUT_WSTRB_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_WSTRB;\noutput   m_axi_DDS_OUTPUT_WLAST;\noutput  [C_M_AXI_DDS_OUTPUT_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_WID;\noutput  [C_M_AXI_DDS_OUTPUT_WUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_WUSER;\noutput   m_axi_DDS_OUTPUT_ARVALID;\ninput   m_axi_DDS_OUTPUT_ARREADY;\noutput  [C_M_AXI_DDS_OUTPUT_ADDR_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_ARADDR;\noutput  [C_M_AXI_DDS_OUTPUT_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_ARID;\noutput  [7:0] m_axi_DDS_OUTPUT_ARLEN;\noutput  [2:0] m_axi_DDS_OUTPUT_ARSIZE;\noutput  [1:0] m_axi_DDS_OUTPUT_ARBURST;\noutput  [1:0] m_axi_DDS_OUTPUT_ARLOCK;\noutput  [3:0] m_axi_DDS_OUTPUT_ARCACHE;\noutput  [2:0] m_axi_DDS_OUTPUT_ARPROT;\noutput  [3:0] m_axi_DDS_OUTPUT_ARQOS;\noutput  [3:0] m_axi_DDS_OUTPUT_ARREGION;\noutput  [C_M_AXI_DDS_OUTPUT_ARUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_ARUSER;\ninput   m_axi_DDS_OUTPUT_RVALID;\noutput   m_axi_DDS_OUTPUT_RREADY;\ninput  [C_M_AXI_DDS_OUTPUT_DATA_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_RDATA;\ninput   m_axi_DDS_OUTPUT_RLAST;\ninput  [C_M_AXI_DDS_OUTPUT_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_RID;\ninput  [C_M_AXI_DDS_OUTPUT_RUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_RUSER;\ninput  [1:0] m_axi_DDS_OUTPUT_RRESP;\ninput   m_axi_DDS_OUTPUT_BVALID;\noutput   m_axi_DDS_OUTPUT_BREADY;\ninput  [1:0] m_axi_DDS_OUTPUT_BRESP;\ninput  [C_M_AXI_DDS_OUTPUT_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_BID;\ninput  [C_M_AXI_DDS_OUTPUT_BUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_BUSER;\noutput   m_axi_DDS_OUTPUT1_AWVALID;\ninput   m_axi_DDS_OUTPUT1_AWREADY;\noutput  [C_M_AXI_DDS_OUTPUT1_ADDR_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_AWADDR;\noutput  [C_M_AXI_DDS_OUTPUT1_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_AWID;\noutput  [7:0] m_axi_DDS_OUTPUT1_AWLEN;\noutput  [2:0] m_axi_DDS_OUTPUT1_AWSIZE;\noutput  [1:0] m_axi_DDS_OUTPUT1_AWBURST;\noutput  [1:0] m_axi_DDS_OUTPUT1_AWLOCK;\noutput  [3:0] m_axi_DDS_OUTPUT1_AWCACHE;\noutput  [2:0] m_axi_DDS_OUTPUT1_AWPROT;\noutput  [3:0] m_axi_DDS_OUTPUT1_AWQOS;\noutput  [3:0] m_axi_DDS_OUTPUT1_AWREGION;\noutput  [C_M_AXI_DDS_OUTPUT1_AWUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_AWUSER;\noutput   m_axi_DDS_OUTPUT1_WVALID;\ninput   m_axi_DDS_OUTPUT1_WREADY;\noutput  [C_M_AXI_DDS_OUTPUT1_DATA_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_WDATA;\noutput  [C_M_AXI_DDS_OUTPUT1_WSTRB_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_WSTRB;\noutput   m_axi_DDS_OUTPUT1_WLAST;\noutput  [C_M_AXI_DDS_OUTPUT1_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_WID;\noutput  [C_M_AXI_DDS_OUTPUT1_WUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_WUSER;\noutput   m_axi_DDS_OUTPUT1_ARVALID;\ninput   m_axi_DDS_OUTPUT1_ARREADY;\noutput  [C_M_AXI_DDS_OUTPUT1_ADDR_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_ARADDR;\noutput  [C_M_AXI_DDS_OUTPUT1_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_ARID;\noutput  [7:0] m_axi_DDS_OUTPUT1_ARLEN;\noutput  [2:0] m_axi_DDS_OUTPUT1_ARSIZE;\noutput  [1:0] m_axi_DDS_OUTPUT1_ARBURST;\noutput  [1:0] m_axi_DDS_OUTPUT1_ARLOCK;\noutput  [3:0] m_axi_DDS_OUTPUT1_ARCACHE;\noutput  [2:0] m_axi_DDS_OUTPUT1_ARPROT;\noutput  [3:0] m_axi_DDS_OUTPUT1_ARQOS;\noutput  [3:0] m_axi_DDS_OUTPUT1_ARREGION;\noutput  [C_M_AXI_DDS_OUTPUT1_ARUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_ARUSER;\ninput   m_axi_DDS_OUTPUT1_RVALID;\noutput   m_axi_DDS_OUTPUT1_RREADY;\ninput  [C_M_AXI_DDS_OUTPUT1_DATA_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_RDATA;\ninput   m_axi_DDS_OUTPUT1_RLAST;\ninput  [C_M_AXI_DDS_OUTPUT1_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_RID;\ninput  [C_M_AXI_DDS_OUTPUT1_RUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_RUSER;\ninput  [1:0] m_axi_DDS_OUTPUT1_RRESP;\ninput   m_axi_DDS_OUTPUT1_BVALID;\noutput   m_axi_DDS_OUTPUT1_BREADY;\ninput  [1:0] m_axi_DDS_OUTPUT1_BRESP;\ninput  [C_M_AXI_DDS_OUTPUT1_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_BID;\ninput  [C_M_AXI_DDS_OUTPUT1_BUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_BUSER;\ninput   s_axi_PROG_BUS_AWVALID;\noutput   s_axi_PROG_BUS_AWREADY;\ninput  [C_S_AXI_PROG_BUS_ADDR_WIDTH - 1 : 0] s_axi_PROG_BUS_AWADDR;\ninput   s_axi_PROG_BUS_WVALID;\noutput   s_axi_PROG_BUS_WREADY;\ninput  [C_S_AXI_PROG_BUS_DATA_WIDTH - 1 : 0] s_axi_PROG_BUS_WDATA;\ninput  [C_S_AXI_PROG_BUS_WSTRB_WIDTH - 1 : 0] s_axi_PROG_BUS_WSTRB;\ninput   s_axi_PROG_BUS_ARVALID;\noutput   s_axi_PROG_BUS_ARREADY;\ninput  [C_S_AXI_PROG_BUS_ADDR_WIDTH - 1 : 0] s_axi_PROG_BUS_ARADDR;\noutput   s_axi_PROG_BUS_RVALID;\ninput   s_axi_PROG_BUS_RREADY;\noutput  [C_S_AXI_PROG_BUS_DATA_WIDTH - 1 : 0] s_axi_PROG_BUS_RDATA;\noutput  [1:0] s_axi_PROG_BUS_RRESP;\noutput   s_axi_PROG_BUS_BVALID;\ninput   s_axi_PROG_BUS_BREADY;\noutput  [1:0] s_axi_PROG_BUS_BRESP;\noutput   interrupt;\n\nreg    ap_rst_n_inv;\nwire    ap_start;\nreg    ap_done;\nreg    ap_idle;\n(* fsm_encoding = \"none\" *) reg   [2:0] ap_CS_fsm;\nwire   [0:0] ap_CS_fsm_state1;\nreg    ap_ready;\nwire   [31:0] nofSample;\nwire   [31:0] incr_V;\nreg    DDS_OUTPUT_AWVALID;\nwire    DDS_OUTPUT_AWREADY;\nreg    DDS_OUTPUT_WVALID;\nwire    DDS_OUTPUT_WREADY;\nwire    DDS_OUTPUT_ARREADY;\nwire    DDS_OUTPUT_RVALID;\nwire   [15:0] DDS_OUTPUT_RDATA;\nwire    DDS_OUTPUT_RLAST;\nwire   [0:0] DDS_OUTPUT_RID;\nwire   [0:0] DDS_OUTPUT_RUSER;\nwire   [1:0] DDS_OUTPUT_RRESP;\nwire    DDS_OUTPUT_BVALID;\nreg    DDS_OUTPUT_BREADY;\nwire   [1:0] DDS_OUTPUT_BRESP;\nwire   [0:0] DDS_OUTPUT_BID;\nwire   [0:0] DDS_OUTPUT_BUSER;\nreg    DDS_OUTPUT1_AWVALID;\nwire    DDS_OUTPUT1_AWREADY;\nreg    DDS_OUTPUT1_WVALID;\nwire    DDS_OUTPUT1_WREADY;\nwire    DDS_OUTPUT1_ARREADY;\nwire    DDS_OUTPUT1_RVALID;\nwire   [15:0] DDS_OUTPUT1_RDATA;\nwire    DDS_OUTPUT1_RLAST;\nwire   [0:0] DDS_OUTPUT1_RID;\nwire   [0:0] DDS_OUTPUT1_RUSER;\nwire   [1:0] DDS_OUTPUT1_RRESP;\nwire    DDS_OUTPUT1_BVALID;\nreg    DDS_OUTPUT1_BREADY;\nwire   [1:0] DDS_OUTPUT1_BRESP;\nwire   [0:0] DDS_OUTPUT1_BID;\nwire   [0:0] DDS_OUTPUT1_BUSER;\nreg   [31:0] incr_V_read_reg_68;\nreg   [31:0] nofSample_read_reg_73;\nwire    grp_process_frame_fu_52_ap_start;\nwire    grp_process_frame_fu_52_ap_done;\nwire    grp_process_frame_fu_52_ap_idle;\nwire    grp_process_frame_fu_52_ap_ready;\nwire    grp_process_frame_fu_52_m_axi_cos_out_V_AWVALID;\nwire   [31:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWADDR;\nwire   [0:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWID;\nwire   [31:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWLEN;\nwire   [2:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWSIZE;\nwire   [1:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWBURST;\nwire   [1:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWLOCK;\nwire   [3:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWCACHE;\nwire   [2:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWPROT;\nwire   [3:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWQOS;\nwire   [3:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWREGION;\nwire   [0:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWUSER;\nwire    grp_process_frame_fu_52_m_axi_cos_out_V_WVALID;\nwire   [15:0] grp_process_frame_fu_52_m_axi_cos_out_V_WDATA;\nwire   [1:0] grp_process_frame_fu_52_m_axi_cos_out_V_WSTRB;\nwire    grp_process_frame_fu_52_m_axi_cos_out_V_WLAST;\nwire   [0:0] grp_process_frame_fu_52_m_axi_cos_out_V_WID;\nwire   [0:0] grp_process_frame_fu_52_m_axi_cos_out_V_WUSER;\nwire    grp_process_frame_fu_52_m_axi_cos_out_V_ARVALID;\nwire   [31:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARADDR;\nwire   [0:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARID;\nwire   [31:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARLEN;\nwire   [2:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARSIZE;\nwire   [1:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARBURST;\nwire   [1:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARLOCK;\nwire   [3:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARCACHE;\nwire   [2:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARPROT;\nwire   [3:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARQOS;\nwire   [3:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARREGION;\nwire   [0:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARUSER;\nwire    grp_process_frame_fu_52_m_axi_cos_out_V_RREADY;\nwire    grp_process_frame_fu_52_m_axi_cos_out_V_BREADY;\nwire    grp_process_frame_fu_52_m_axi_sin_out_V_AWVALID;\nwire   [31:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWADDR;\nwire   [0:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWID;\nwire   [31:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWLEN;\nwire   [2:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWSIZE;\nwire   [1:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWBURST;\nwire   [1:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWLOCK;\nwire   [3:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWCACHE;\nwire   [2:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWPROT;\nwire   [3:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWQOS;\nwire   [3:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWREGION;\nwire   [0:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWUSER;\nwire    grp_process_frame_fu_52_m_axi_sin_out_V_WVALID;\nwire   [15:0] grp_process_frame_fu_52_m_axi_sin_out_V_WDATA;\nwire   [1:0] grp_process_frame_fu_52_m_axi_sin_out_V_WSTRB;\nwire    grp_process_frame_fu_52_m_axi_sin_out_V_WLAST;\nwire   [0:0] grp_process_frame_fu_52_m_axi_sin_out_V_WID;\nwire   [0:0] grp_process_frame_fu_52_m_axi_sin_out_V_WUSER;\nwire    grp_process_frame_fu_52_m_axi_sin_out_V_ARVALID;\nwire   [31:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARADDR;\nwire   [0:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARID;\nwire   [31:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARLEN;\nwire   [2:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARSIZE;\nwire   [1:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARBURST;\nwire   [1:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARLOCK;\nwire   [3:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARCACHE;\nwire   [2:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARPROT;\nwire   [3:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARQOS;\nwire   [3:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARREGION;\nwire   [0:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARUSER;\nwire    grp_process_frame_fu_52_m_axi_sin_out_V_RREADY;\nwire    grp_process_frame_fu_52_m_axi_sin_out_V_BREADY;\nreg    ap_reg_grp_process_frame_fu_52_ap_start;\nwire   [0:0] ap_CS_fsm_state2;\nwire   [0:0] ap_CS_fsm_state3;\nreg   [2:0] ap_NS_fsm;\n\n// power-on initialization\ninitial begin\n#0 ap_CS_fsm = 3'b1;\n#0 ap_reg_grp_process_frame_fu_52_ap_start = 1'b0;\nend\n\ndds_PROG_BUS_s_axi #(\n    .C_S_AXI_ADDR_WIDTH( C_S_AXI_PROG_BUS_ADDR_WIDTH ),\n    .C_S_AXI_DATA_WIDTH( C_S_AXI_PROG_BUS_DATA_WIDTH ))\ndds_PROG_BUS_s_axi_U(\n    .AWVALID(s_axi_PROG_BUS_AWVALID),\n    .AWREADY(s_axi_PROG_BUS_AWREADY),\n    .AWADDR(s_axi_PROG_BUS_AWADDR),\n    .WVALID(s_axi_PROG_BUS_WVALID),\n    .WREADY(s_axi_PROG_BUS_WREADY),\n    .WDATA(s_axi_PROG_BUS_WDATA),\n    .WSTRB(s_axi_PROG_BUS_WSTRB),\n    .ARVALID(s_axi_PROG_BUS_ARVALID),\n    .ARREADY(s_axi_PROG_BUS_ARREADY),\n    .ARADDR(s_axi_PROG_BUS_ARADDR),\n    .RVALID(s_axi_PROG_BUS_RVALID),\n    .RREADY(s_axi_PROG_BUS_RREADY),\n    .RDATA(s_axi_PROG_BUS_RDATA),\n    .RRESP(s_axi_PROG_BUS_RRESP),\n    .BVALID(s_axi_PROG_BUS_BVALID),\n    .BREADY(s_axi_PROG_BUS_BREADY),\n    .BRESP(s_axi_PROG_BUS_BRESP),\n    .ACLK(ap_clk),\n    .ARESET(ap_rst_n_inv),\n    .ACLK_EN(1'b1),\n    .ap_start(ap_start),\n    .interrupt(interrupt),\n    .ap_ready(ap_ready),\n    .ap_done(ap_done),\n    .ap_idle(ap_idle),\n    .nofSample(nofSample),\n    .incr_V(incr_V)\n);\n\ndds_DDS_OUTPUT_m_axi #(\n    .USER_DW( 16 ),\n    .USER_AW( 32 ),\n    .USER_MAXREQS( 5 ),\n    .NUM_READ_OUTSTANDING( 16 ),\n    .NUM_WRITE_OUTSTANDING( 16 ),\n    .MAX_READ_BURST_LENGTH( 16 ),\n    .MAX_WRITE_BURST_LENGTH( 16 ),\n    .C_M_AXI_ID_WIDTH( C_M_AXI_DDS_OUTPUT_ID_WIDTH ),\n    .C_M_AXI_ADDR_WIDTH( C_M_AXI_DDS_OUTPUT_ADDR_WIDTH ),\n    .C_M_AXI_DATA_WIDTH( C_M_AXI_DDS_OUTPUT_DATA_WIDTH ),\n    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_DDS_OUTPUT_AWUSER_WIDTH ),\n    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_DDS_OUTPUT_ARUSER_WIDTH ),\n    .C_M_AXI_WUSER_WIDTH( C_M_AXI_DDS_OUTPUT_WUSER_WIDTH ),\n    .C_M_AXI_RUSER_WIDTH( C_M_AXI_DDS_OUTPUT_RUSER_WIDTH ),\n    .C_M_AXI_BUSER_WIDTH( C_M_AXI_DDS_OUTPUT_BUSER_WIDTH ),\n    .C_TARGET_ADDR( C_M_AXI_DDS_OUTPUT_TARGET_ADDR ),\n    .C_USER_VALUE( C_M_AXI_DDS_OUTPUT_USER_VALUE ),\n    .C_PROT_VALUE( C_M_AXI_DDS_OUTPUT_PROT_VALUE ),\n    .C_CACHE_VALUE( C_M_AXI_DDS_OUTPUT_CACHE_VALUE ))\ndds_DDS_OUTPUT_m_axi_U(\n    .AWVALID(m_axi_DDS_OUTPUT_AWVALID),\n    .AWREADY(m_axi_DDS_OUTPUT_AWREADY),\n    .AWADDR(m_axi_DDS_OUTPUT_AWADDR),\n    .AWID(m_axi_DDS_OUTPUT_AWID),\n    .AWLEN(m_axi_DDS_OUTPUT_AWLEN),\n    .AWSIZE(m_axi_DDS_OUTPUT_AWSIZE),\n    .AWBURST(m_axi_DDS_OUTPUT_AWBURST),\n    .AWLOCK(m_axi_DDS_OUTPUT_AWLOCK),\n    .AWCACHE(m_axi_DDS_OUTPUT_AWCACHE),\n    .AWPROT(m_axi_DDS_OUTPUT_AWPROT),\n    .AWQOS(m_axi_DDS_OUTPUT_AWQOS),\n    .AWREGION(m_axi_DDS_OUTPUT_AWREGION),\n    .AWUSER(m_axi_DDS_OUTPUT_AWUSER),\n    .WVALID(m_axi_DDS_OUTPUT_WVALID),\n    .WREADY(m_axi_DDS_OUTPUT_WREADY),\n    .WDATA(m_axi_DDS_OUTPUT_WDATA),\n    .WSTRB(m_axi_DDS_OUTPUT_WSTRB),\n    .WLAST(m_axi_DDS_OUTPUT_WLAST),\n    .WID(m_axi_DDS_OUTPUT_WID),\n    .WUSER(m_axi_DDS_OUTPUT_WUSER),\n    .ARVALID(m_axi_DDS_OUTPUT_ARVALID),\n    .ARREADY(m_axi_DDS_OUTPUT_ARREADY),\n    .ARADDR(m_axi_DDS_OUTPUT_ARADDR),\n    .ARID(m_axi_DDS_OUTPUT_ARID),\n    .ARLEN(m_axi_DDS_OUTPUT_ARLEN),\n    .ARSIZE(m_axi_DDS_OUTPUT_ARSIZE),\n    .ARBURST(m_axi_DDS_OUTPUT_ARBURST),\n    .ARLOCK(m_axi_DDS_OUTPUT_ARLOCK),\n    .ARCACHE(m_axi_DDS_OUTPUT_ARCACHE),\n    .ARPROT(m_axi_DDS_OUTPUT_ARPROT),\n    .ARQOS(m_axi_DDS_OUTPUT_ARQOS),\n    .ARREGION(m_axi_DDS_OUTPUT_ARREGION),\n    .ARUSER(m_axi_DDS_OUTPUT_ARUSER),\n    .RVALID(m_axi_DDS_OUTPUT_RVALID),\n    .RREADY(m_axi_DDS_OUTPUT_RREADY),\n    .RDATA(m_axi_DDS_OUTPUT_RDATA),\n    .RLAST(m_axi_DDS_OUTPUT_RLAST),\n    .RID(m_axi_DDS_OUTPUT_RID),\n    .RUSER(m_axi_DDS_OUTPUT_RUSER),\n    .RRESP(m_axi_DDS_OUTPUT_RRESP),\n    .BVALID(m_axi_DDS_OUTPUT_BVALID),\n    .BREADY(m_axi_DDS_OUTPUT_BREADY),\n    .BRESP(m_axi_DDS_OUTPUT_BRESP),\n    .BID(m_axi_DDS_OUTPUT_BID),\n    .BUSER(m_axi_DDS_OUTPUT_BUSER),\n    .ACLK(ap_clk),\n    .ARESET(ap_rst_n_inv),\n    .ACLK_EN(1'b1),\n    .I_ARVALID(1'b0),\n    .I_ARREADY(DDS_OUTPUT_ARREADY),\n    .I_ARADDR(ap_const_lv32_0),\n    .I_ARID(1'b0),\n    .I_ARLEN(ap_const_lv32_0),\n    .I_ARSIZE(ap_const_lv3_0),\n    .I_ARLOCK(ap_const_lv2_0),\n    .I_ARCACHE(ap_const_lv4_0),\n    .I_ARQOS(ap_const_lv4_0),\n    .I_ARPROT(ap_const_lv3_0),\n    .I_ARUSER(1'b0),\n    .I_ARBURST(ap_const_lv2_0),\n    .I_ARREGION(ap_const_lv4_0),\n    .I_RVALID(DDS_OUTPUT_RVALID),\n    .I_RREADY(1'b0),\n    .I_RDATA(DDS_OUTPUT_RDATA),\n    .I_RID(DDS_OUTPUT_RID),\n    .I_RUSER(DDS_OUTPUT_RUSER),\n    .I_RRESP(DDS_OUTPUT_RRESP),\n    .I_RLAST(DDS_OUTPUT_RLAST),\n    .I_AWVALID(DDS_OUTPUT_AWVALID),\n    .I_AWREADY(DDS_OUTPUT_AWREADY),\n    .I_AWADDR(grp_process_frame_fu_52_m_axi_cos_out_V_AWADDR),\n    .I_AWID(grp_process_frame_fu_52_m_axi_cos_out_V_AWID),\n    .I_AWLEN(grp_process_frame_fu_52_m_axi_cos_out_V_AWLEN),\n    .I_AWSIZE(grp_process_frame_fu_52_m_axi_cos_out_V_AWSIZE),\n    .I_AWLOCK(grp_process_frame_fu_52_m_axi_cos_out_V_AWLOCK),\n    .I_AWCACHE(grp_process_frame_fu_52_m_axi_cos_out_V_AWCACHE),\n    .I_AWQOS(grp_process_frame_fu_52_m_axi_cos_out_V_AWQOS),\n    .I_AWPROT(grp_process_frame_fu_52_m_axi_cos_out_V_AWPROT),\n    .I_AWUSER(grp_process_frame_fu_52_m_axi_cos_out_V_AWUSER),\n    .I_AWBURST(grp_process_frame_fu_52_m_axi_cos_out_V_AWBURST),\n    .I_AWREGION(grp_process_frame_fu_52_m_axi_cos_out_V_AWREGION),\n    .I_WVALID(DDS_OUTPUT_WVALID),\n    .I_WREADY(DDS_OUTPUT_WREADY),\n    .I_WDATA(grp_process_frame_fu_52_m_axi_cos_out_V_WDATA),\n    .I_WID(grp_process_frame_fu_52_m_axi_cos_out_V_WID),\n    .I_WUSER(grp_process_frame_fu_52_m_axi_cos_out_V_WUSER),\n    .I_WLAST(grp_process_frame_fu_52_m_axi_cos_out_V_WLAST),\n    .I_WSTRB(grp_process_frame_fu_52_m_axi_cos_out_V_WSTRB),\n    .I_BVALID(DDS_OUTPUT_BVALID),\n    .I_BREADY(DDS_OUTPUT_BREADY),\n    .I_BRESP(DDS_OUTPUT_BRESP),\n    .I_BID(DDS_OUTPUT_BID),\n    .I_BUSER(DDS_OUTPUT_BUSER)\n);\n\ndds_DDS_OUTPUT1_m_axi #(\n    .USER_DW( 16 ),\n    .USER_AW( 32 ),\n    .USER_MAXREQS( 5 ),\n    .NUM_READ_OUTSTANDING( 16 ),\n    .NUM_WRITE_OUTSTANDING( 16 ),\n    .MAX_READ_BURST_LENGTH( 16 ),\n    .MAX_WRITE_BURST_LENGTH( 16 ),\n    .C_M_AXI_ID_WIDTH( C_M_AXI_DDS_OUTPUT1_ID_WIDTH ),\n    .C_M_AXI_ADDR_WIDTH( C_M_AXI_DDS_OUTPUT1_ADDR_WIDTH ),\n    .C_M_AXI_DATA_WIDTH( C_M_AXI_DDS_OUTPUT1_DATA_WIDTH ),\n    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_DDS_OUTPUT1_AWUSER_WIDTH ),\n    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_DDS_OUTPUT1_ARUSER_WIDTH ),\n    .C_M_AXI_WUSER_WIDTH( C_M_AXI_DDS_OUTPUT1_WUSER_WIDTH ),\n    .C_M_AXI_RUSER_WIDTH( C_M_AXI_DDS_OUTPUT1_RUSER_WIDTH ),\n    .C_M_AXI_BUSER_WIDTH( C_M_AXI_DDS_OUTPUT1_BUSER_WIDTH ),\n    .C_TARGET_ADDR( C_M_AXI_DDS_OUTPUT1_TARGET_ADDR ),\n    .C_USER_VALUE( C_M_AXI_DDS_OUTPUT1_USER_VALUE ),\n    .C_PROT_VALUE( C_M_AXI_DDS_OUTPUT1_PROT_VALUE ),\n    .C_CACHE_VALUE( C_M_AXI_DDS_OUTPUT1_CACHE_VALUE ))\ndds_DDS_OUTPUT1_m_axi_U(\n    .AWVALID(m_axi_DDS_OUTPUT1_AWVALID),\n    .AWREADY(m_axi_DDS_OUTPUT1_AWREADY),\n    .AWADDR(m_axi_DDS_OUTPUT1_AWADDR),\n    .AWID(m_axi_DDS_OUTPUT1_AWID),\n    .AWLEN(m_axi_DDS_OUTPUT1_AWLEN),\n    .AWSIZE(m_axi_DDS_OUTPUT1_AWSIZE),\n    .AWBURST(m_axi_DDS_OUTPUT1_AWBURST),\n    .AWLOCK(m_axi_DDS_OUTPUT1_AWLOCK),\n    .AWCACHE(m_axi_DDS_OUTPUT1_AWCACHE),\n    .AWPROT(m_axi_DDS_OUTPUT1_AWPROT),\n    .AWQOS(m_axi_DDS_OUTPUT1_AWQOS),\n    .AWREGION(m_axi_DDS_OUTPUT1_AWREGION),\n    .AWUSER(m_axi_DDS_OUTPUT1_AWUSER),\n    .WVALID(m_axi_DDS_OUTPUT1_WVALID),\n    .WREADY(m_axi_DDS_OUTPUT1_WREADY),\n    .WDATA(m_axi_DDS_OUTPUT1_WDATA),\n    .WSTRB(m_axi_DDS_OUTPUT1_WSTRB),\n    .WLAST(m_axi_DDS_OUTPUT1_WLAST),\n    .WID(m_axi_DDS_OUTPUT1_WID),\n    .WUSER(m_axi_DDS_OUTPUT1_WUSER),\n    .ARVALID(m_axi_DDS_OUTPUT1_ARVALID),\n    .ARREADY(m_axi_DDS_OUTPUT1_ARREADY),\n    .ARADDR(m_axi_DDS_OUTPUT1_ARADDR),\n    .ARID(m_axi_DDS_OUTPUT1_ARID),\n    .ARLEN(m_axi_DDS_OUTPUT1_ARLEN),\n    .ARSIZE(m_axi_DDS_OUTPUT1_ARSIZE),\n    .ARBURST(m_axi_DDS_OUTPUT1_ARBURST),\n    .ARLOCK(m_axi_DDS_OUTPUT1_ARLOCK),\n    .ARCACHE(m_axi_DDS_OUTPUT1_ARCACHE),\n    .ARPROT(m_axi_DDS_OUTPUT1_ARPROT),\n    .ARQOS(m_axi_DDS_OUTPUT1_ARQOS),\n    .ARREGION(m_axi_DDS_OUTPUT1_ARREGION),\n    .ARUSER(m_axi_DDS_OUTPUT1_ARUSER),\n    .RVALID(m_axi_DDS_OUTPUT1_RVALID),\n    .RREADY(m_axi_DDS_OUTPUT1_RREADY),\n    .RDATA(m_axi_DDS_OUTPUT1_RDATA),\n    .RLAST(m_axi_DDS_OUTPUT1_RLAST),\n    .RID(m_axi_DDS_OUTPUT1_RID),\n    .RUSER(m_axi_DDS_OUTPUT1_RUSER),\n    .RRESP(m_axi_DDS_OUTPUT1_RRESP),\n    .BVALID(m_axi_DDS_OUTPUT1_BVALID),\n    .BREADY(m_axi_DDS_OUTPUT1_BREADY),\n    .BRESP(m_axi_DDS_OUTPUT1_BRESP),\n    .BID(m_axi_DDS_OUTPUT1_BID),\n    .BUSER(m_axi_DDS_OUTPUT1_BUSER),\n    .ACLK(ap_clk),\n    .ARESET(ap_rst_n_inv),\n    .ACLK_EN(1'b1),\n    .I_ARVALID(1'b0),\n    .I_ARREADY(DDS_OUTPUT1_ARREADY),\n    .I_ARADDR(ap_const_lv32_0),\n    .I_ARID(1'b0),\n    .I_ARLEN(ap_const_lv32_0),\n    .I_ARSIZE(ap_const_lv3_0),\n    .I_ARLOCK(ap_const_lv2_0),\n    .I_ARCACHE(ap_const_lv4_0),\n    .I_ARQOS(ap_const_lv4_0),\n    .I_ARPROT(ap_const_lv3_0),\n    .I_ARUSER(1'b0),\n    .I_ARBURST(ap_const_lv2_0),\n    .I_ARREGION(ap_const_lv4_0),\n    .I_RVALID(DDS_OUTPUT1_RVALID),\n    .I_RREADY(1'b0),\n    .I_RDATA(DDS_OUTPUT1_RDATA),\n    .I_RID(DDS_OUTPUT1_RID),\n    .I_RUSER(DDS_OUTPUT1_RUSER),\n    .I_RRESP(DDS_OUTPUT1_RRESP),\n    .I_RLAST(DDS_OUTPUT1_RLAST),\n    .I_AWVALID(DDS_OUTPUT1_AWVALID),\n    .I_AWREADY(DDS_OUTPUT1_AWREADY),\n    .I_AWADDR(grp_process_frame_fu_52_m_axi_sin_out_V_AWADDR),\n    .I_AWID(grp_process_frame_fu_52_m_axi_sin_out_V_AWID),\n    .I_AWLEN(grp_process_frame_fu_52_m_axi_sin_out_V_AWLEN),\n    .I_AWSIZE(grp_process_frame_fu_52_m_axi_sin_out_V_AWSIZE),\n    .I_AWLOCK(grp_process_frame_fu_52_m_axi_sin_out_V_AWLOCK),\n    .I_AWCACHE(grp_process_frame_fu_52_m_axi_sin_out_V_AWCACHE),\n    .I_AWQOS(grp_process_frame_fu_52_m_axi_sin_out_V_AWQOS),\n    .I_AWPROT(grp_process_frame_fu_52_m_axi_sin_out_V_AWPROT),\n    .I_AWUSER(grp_process_frame_fu_52_m_axi_sin_out_V_AWUSER),\n    .I_AWBURST(grp_process_frame_fu_52_m_axi_sin_out_V_AWBURST),\n    .I_AWREGION(grp_process_frame_fu_52_m_axi_sin_out_V_AWREGION),\n    .I_WVALID(DDS_OUTPUT1_WVALID),\n    .I_WREADY(DDS_OUTPUT1_WREADY),\n    .I_WDATA(grp_process_frame_fu_52_m_axi_sin_out_V_WDATA),\n    .I_WID(grp_process_frame_fu_52_m_axi_sin_out_V_WID),\n    .I_WUSER(grp_process_frame_fu_52_m_axi_sin_out_V_WUSER),\n    .I_WLAST(grp_process_frame_fu_52_m_axi_sin_out_V_WLAST),\n    .I_WSTRB(grp_process_frame_fu_52_m_axi_sin_out_V_WSTRB),\n    .I_BVALID(DDS_OUTPUT1_BVALID),\n    .I_BREADY(DDS_OUTPUT1_BREADY),\n    .I_BRESP(DDS_OUTPUT1_BRESP),\n    .I_BID(DDS_OUTPUT1_BID),\n    .I_BUSER(DDS_OUTPUT1_BUSER)\n);\n\nprocess_frame grp_process_frame_fu_52(\n    .ap_clk(ap_clk),\n    .ap_rst(ap_rst_n_inv),\n    .ap_start(grp_process_frame_fu_52_ap_start),\n    .ap_done(grp_process_frame_fu_52_ap_done),\n    .ap_idle(grp_process_frame_fu_52_ap_idle),\n    .ap_ready(grp_process_frame_fu_52_ap_ready),\n    .nofSample(nofSample_read_reg_73),\n    .incr_V(incr_V_read_reg_68),\n    .m_axi_cos_out_V_AWVALID(grp_process_frame_fu_52_m_axi_cos_out_V_AWVALID),\n    .m_axi_cos_out_V_AWREADY(DDS_OUTPUT_AWREADY),\n    .m_axi_cos_out_V_AWADDR(grp_process_frame_fu_52_m_axi_cos_out_V_AWADDR),\n    .m_axi_cos_out_V_AWID(grp_process_frame_fu_52_m_axi_cos_out_V_AWID),\n    .m_axi_cos_out_V_AWLEN(grp_process_frame_fu_52_m_axi_cos_out_V_AWLEN),\n    .m_axi_cos_out_V_AWSIZE(grp_process_frame_fu_52_m_axi_cos_out_V_AWSIZE),\n    .m_axi_cos_out_V_AWBURST(grp_process_frame_fu_52_m_axi_cos_out_V_AWBURST),\n    .m_axi_cos_out_V_AWLOCK(grp_process_frame_fu_52_m_axi_cos_out_V_AWLOCK),\n    .m_axi_cos_out_V_AWCACHE(grp_process_frame_fu_52_m_axi_cos_out_V_AWCACHE),\n    .m_axi_cos_out_V_AWPROT(grp_process_frame_fu_52_m_axi_cos_out_V_AWPROT),\n    .m_axi_cos_out_V_AWQOS(grp_process_frame_fu_52_m_axi_cos_out_V_AWQOS),\n    .m_axi_cos_out_V_AWREGION(grp_process_frame_fu_52_m_axi_cos_out_V_AWREGION),\n    .m_axi_cos_out_V_AWUSER(grp_process_frame_fu_52_m_axi_cos_out_V_AWUSER),\n    .m_axi_cos_out_V_WVALID(grp_process_frame_fu_52_m_axi_cos_out_V_WVALID),\n    .m_axi_cos_out_V_WREADY(DDS_OUTPUT_WREADY),\n    .m_axi_cos_out_V_WDATA(grp_process_frame_fu_52_m_axi_cos_out_V_WDATA),\n    .m_axi_cos_out_V_WSTRB(grp_process_frame_fu_52_m_axi_cos_out_V_WSTRB),\n    .m_axi_cos_out_V_WLAST(grp_process_frame_fu_52_m_axi_cos_out_V_WLAST),\n    .m_axi_cos_out_V_WID(grp_process_frame_fu_52_m_axi_cos_out_V_WID),\n    .m_axi_cos_out_V_WUSER(grp_process_frame_fu_52_m_axi_cos_out_V_WUSER),\n    .m_axi_cos_out_V_ARVALID(grp_process_frame_fu_52_m_axi_cos_out_V_ARVALID),\n    .m_axi_cos_out_V_ARREADY(1'b0),\n    .m_axi_cos_out_V_ARADDR(grp_process_frame_fu_52_m_axi_cos_out_V_ARADDR),\n    .m_axi_cos_out_V_ARID(grp_process_frame_fu_52_m_axi_cos_out_V_ARID),\n    .m_axi_cos_out_V_ARLEN(grp_process_frame_fu_52_m_axi_cos_out_V_ARLEN),\n    .m_axi_cos_out_V_ARSIZE(grp_process_frame_fu_52_m_axi_cos_out_V_ARSIZE),\n    .m_axi_cos_out_V_ARBURST(grp_process_frame_fu_52_m_axi_cos_out_V_ARBURST),\n    .m_axi_cos_out_V_ARLOCK(grp_process_frame_fu_52_m_axi_cos_out_V_ARLOCK),\n    .m_axi_cos_out_V_ARCACHE(grp_process_frame_fu_52_m_axi_cos_out_V_ARCACHE),\n    .m_axi_cos_out_V_ARPROT(grp_process_frame_fu_52_m_axi_cos_out_V_ARPROT),\n    .m_axi_cos_out_V_ARQOS(grp_process_frame_fu_52_m_axi_cos_out_V_ARQOS),\n    .m_axi_cos_out_V_ARREGION(grp_process_frame_fu_52_m_axi_cos_out_V_ARREGION),\n    .m_axi_cos_out_V_ARUSER(grp_process_frame_fu_52_m_axi_cos_out_V_ARUSER),\n    .m_axi_cos_out_V_RVALID(1'b0),\n    .m_axi_cos_out_V_RREADY(grp_process_frame_fu_52_m_axi_cos_out_V_RREADY),\n    .m_axi_cos_out_V_RDATA(ap_const_lv16_0),\n    .m_axi_cos_out_V_RLAST(1'b0),\n    .m_axi_cos_out_V_RID(1'b0),\n    .m_axi_cos_out_V_RUSER(1'b0),\n    .m_axi_cos_out_V_RRESP(ap_const_lv2_0),\n    .m_axi_cos_out_V_BVALID(DDS_OUTPUT_BVALID),\n    .m_axi_cos_out_V_BREADY(grp_process_frame_fu_52_m_axi_cos_out_V_BREADY),\n    .m_axi_cos_out_V_BRESP(DDS_OUTPUT_BRESP),\n    .m_axi_cos_out_V_BID(DDS_OUTPUT_BID),\n    .m_axi_cos_out_V_BUSER(DDS_OUTPUT_BUSER),\n    .m_axi_sin_out_V_AWVALID(grp_process_frame_fu_52_m_axi_sin_out_V_AWVALID),\n    .m_axi_sin_out_V_AWREADY(DDS_OUTPUT1_AWREADY),\n    .m_axi_sin_out_V_AWADDR(grp_process_frame_fu_52_m_axi_sin_out_V_AWADDR),\n    .m_axi_sin_out_V_AWID(grp_process_frame_fu_52_m_axi_sin_out_V_AWID),\n    .m_axi_sin_out_V_AWLEN(grp_process_frame_fu_52_m_axi_sin_out_V_AWLEN),\n    .m_axi_sin_out_V_AWSIZE(grp_process_frame_fu_52_m_axi_sin_out_V_AWSIZE),\n    .m_axi_sin_out_V_AWBURST(grp_process_frame_fu_52_m_axi_sin_out_V_AWBURST),\n    .m_axi_sin_out_V_AWLOCK(grp_process_frame_fu_52_m_axi_sin_out_V_AWLOCK),\n    .m_axi_sin_out_V_AWCACHE(grp_process_frame_fu_52_m_axi_sin_out_V_AWCACHE),\n    .m_axi_sin_out_V_AWPROT(grp_process_frame_fu_52_m_axi_sin_out_V_AWPROT),\n    .m_axi_sin_out_V_AWQOS(grp_process_frame_fu_52_m_axi_sin_out_V_AWQOS),\n    .m_axi_sin_out_V_AWREGION(grp_process_frame_fu_52_m_axi_sin_out_V_AWREGION),\n    .m_axi_sin_out_V_AWUSER(grp_process_frame_fu_52_m_axi_sin_out_V_AWUSER),\n    .m_axi_sin_out_V_WVALID(grp_process_frame_fu_52_m_axi_sin_out_V_WVALID),\n    .m_axi_sin_out_V_WREADY(DDS_OUTPUT1_WREADY),\n    .m_axi_sin_out_V_WDATA(grp_process_frame_fu_52_m_axi_sin_out_V_WDATA),\n    .m_axi_sin_out_V_WSTRB(grp_process_frame_fu_52_m_axi_sin_out_V_WSTRB),\n    .m_axi_sin_out_V_WLAST(grp_process_frame_fu_52_m_axi_sin_out_V_WLAST),\n    .m_axi_sin_out_V_WID(grp_process_frame_fu_52_m_axi_sin_out_V_WID),\n    .m_axi_sin_out_V_WUSER(grp_process_frame_fu_52_m_axi_sin_out_V_WUSER),\n    .m_axi_sin_out_V_ARVALID(grp_process_frame_fu_52_m_axi_sin_out_V_ARVALID),\n    .m_axi_sin_out_V_ARREADY(1'b0),\n    .m_axi_sin_out_V_ARADDR(grp_process_frame_fu_52_m_axi_sin_out_V_ARADDR),\n    .m_axi_sin_out_V_ARID(grp_process_frame_fu_52_m_axi_sin_out_V_ARID),\n    .m_axi_sin_out_V_ARLEN(grp_process_frame_fu_52_m_axi_sin_out_V_ARLEN),\n    .m_axi_sin_out_V_ARSIZE(grp_process_frame_fu_52_m_axi_sin_out_V_ARSIZE),\n    .m_axi_sin_out_V_ARBURST(grp_process_frame_fu_52_m_axi_sin_out_V_ARBURST),\n    .m_axi_sin_out_V_ARLOCK(grp_process_frame_fu_52_m_axi_sin_out_V_ARLOCK),\n    .m_axi_sin_out_V_ARCACHE(grp_process_frame_fu_52_m_axi_sin_out_V_ARCACHE),\n    .m_axi_sin_out_V_ARPROT(grp_process_frame_fu_52_m_axi_sin_out_V_ARPROT),\n    .m_axi_sin_out_V_ARQOS(grp_process_frame_fu_52_m_axi_sin_out_V_ARQOS),\n    .m_axi_sin_out_V_ARREGION(grp_process_frame_fu_52_m_axi_sin_out_V_ARREGION),\n    .m_axi_sin_out_V_ARUSER(grp_process_frame_fu_52_m_axi_sin_out_V_ARUSER),\n    .m_axi_sin_out_V_RVALID(1'b0),\n    .m_axi_sin_out_V_RREADY(grp_process_frame_fu_52_m_axi_sin_out_V_RREADY),\n    .m_axi_sin_out_V_RDATA(ap_const_lv16_0),\n    .m_axi_sin_out_V_RLAST(1'b0),\n    .m_axi_sin_out_V_RID(1'b0),\n    .m_axi_sin_out_V_RUSER(1'b0),\n    .m_axi_sin_out_V_RRESP(ap_const_lv2_0),\n    .m_axi_sin_out_V_BVALID(DDS_OUTPUT1_BVALID),\n    .m_axi_sin_out_V_BREADY(grp_process_frame_fu_52_m_axi_sin_out_V_BREADY),\n    .m_axi_sin_out_V_BRESP(DDS_OUTPUT1_BRESP),\n    .m_axi_sin_out_V_BID(DDS_OUTPUT1_BID),\n    .m_axi_sin_out_V_BUSER(DDS_OUTPUT1_BUSER)\n);\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst_n_inv == 1'b1) begin\n        ap_CS_fsm <= ap_ST_fsm_state1;\n    end else begin\n        ap_CS_fsm <= ap_NS_fsm;\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst_n_inv == 1'b1) begin\n        ap_reg_grp_process_frame_fu_52_ap_start <= 1'b0;\n    end else begin\n        if ((1'b1 == ap_CS_fsm_state2)) begin\n            ap_reg_grp_process_frame_fu_52_ap_start <= 1'b1;\n        end else if ((1'b1 == grp_process_frame_fu_52_ap_ready)) begin\n            ap_reg_grp_process_frame_fu_52_ap_start <= 1'b0;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (((ap_CS_fsm_state1 == 1'b1) & ~(ap_start == 1'b0))) begin\n        incr_V_read_reg_68 <= incr_V;\n        nofSample_read_reg_73 <= nofSample;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state3))) begin\n        DDS_OUTPUT1_AWVALID = grp_process_frame_fu_52_m_axi_sin_out_V_AWVALID;\n    end else begin\n        DDS_OUTPUT1_AWVALID = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state3))) begin\n        DDS_OUTPUT1_BREADY = grp_process_frame_fu_52_m_axi_sin_out_V_BREADY;\n    end else begin\n        DDS_OUTPUT1_BREADY = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state3))) begin\n        DDS_OUTPUT1_WVALID = grp_process_frame_fu_52_m_axi_sin_out_V_WVALID;\n    end else begin\n        DDS_OUTPUT1_WVALID = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state3))) begin\n        DDS_OUTPUT_AWVALID = grp_process_frame_fu_52_m_axi_cos_out_V_AWVALID;\n    end else begin\n        DDS_OUTPUT_AWVALID = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state3))) begin\n        DDS_OUTPUT_BREADY = grp_process_frame_fu_52_m_axi_cos_out_V_BREADY;\n    end else begin\n        DDS_OUTPUT_BREADY = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state3))) begin\n        DDS_OUTPUT_WVALID = grp_process_frame_fu_52_m_axi_cos_out_V_WVALID;\n    end else begin\n        DDS_OUTPUT_WVALID = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b1 == ap_CS_fsm_state3) & ~(1'b0 == grp_process_frame_fu_52_ap_done))) begin\n        ap_done = 1'b1;\n    end else begin\n        ap_done = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b0 == ap_start) & (ap_CS_fsm_state1 == 1'b1))) begin\n        ap_idle = 1'b1;\n    end else begin\n        ap_idle = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b1 == ap_CS_fsm_state3) & ~(1'b0 == grp_process_frame_fu_52_ap_done))) begin\n        ap_ready = 1'b1;\n    end else begin\n        ap_ready = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    case (ap_CS_fsm)\n        ap_ST_fsm_state1 : begin\n            if (~(ap_start == 1'b0)) begin\n                ap_NS_fsm = ap_ST_fsm_state2;\n            end else begin\n                ap_NS_fsm = ap_ST_fsm_state1;\n            end\n        end\n        ap_ST_fsm_state2 : begin\n            ap_NS_fsm = ap_ST_fsm_state3;\n        end\n        ap_ST_fsm_state3 : begin\n            if (~(1'b0 == grp_process_frame_fu_52_ap_done)) begin\n                ap_NS_fsm = ap_ST_fsm_state1;\n            end else begin\n                ap_NS_fsm = ap_ST_fsm_state3;\n            end\n        end\n        default : begin\n            ap_NS_fsm = 'bx;\n        end\n    endcase\nend\n\nassign ap_CS_fsm_state1 = ap_CS_fsm[ap_const_lv32_0];\n\nassign ap_CS_fsm_state2 = ap_CS_fsm[ap_const_lv32_1];\n\nassign ap_CS_fsm_state3 = ap_CS_fsm[ap_const_lv32_2];\n\nalways @ (*) begin\n    ap_rst_n_inv = ~ap_rst_n;\nend\n\nassign grp_process_frame_fu_52_ap_start = ap_reg_grp_process_frame_fu_52_ap_start;\n\nendmodule //dds\n", "num_lines": 907}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// ==============================================================\n// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC\n// Version: 2016.3\n// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.\n// \n// ==============================================================\n\n`timescale 1ns/1ps\n\nmodule dds_DDS_OUTPUT1_m_axi\n#(parameter\n    NUM_READ_OUTSTANDING    = 2,\n    NUM_WRITE_OUTSTANDING   = 2,\n    MAX_READ_BURST_LENGTH   = 16,\n    MAX_WRITE_BURST_LENGTH  = 16,\n    C_M_AXI_ID_WIDTH        = 1,\n    C_M_AXI_ADDR_WIDTH      = 32,\n    C_TARGET_ADDR           = 32'h00000000,\n    C_M_AXI_DATA_WIDTH      = 32,\n    C_M_AXI_AWUSER_WIDTH    = 1,\n    C_M_AXI_ARUSER_WIDTH    = 1,\n    C_M_AXI_WUSER_WIDTH     = 1,\n    C_M_AXI_RUSER_WIDTH     = 1,\n    C_M_AXI_BUSER_WIDTH     = 1,\n    C_USER_VALUE      = 1'b0,\n    C_PROT_VALUE      = 3'b000,\n    C_CACHE_VALUE     = 4'b0011,\n    USER_DW           = 16,\n    USER_AW           = 32,\n    USER_MAXREQS      = 16\n)(\n    // system signal\n    input  wire                         ACLK,\n    input  wire                         ARESET,\n    input  wire                         ACLK_EN,\n    // write address channel\n    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,\n    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,\n    output wire [7:0]                   AWLEN,\n    output wire [2:0]                   AWSIZE,\n    output wire [1:0]                   AWBURST,\n    output wire [1:0]                   AWLOCK,\n    output wire [3:0]                   AWCACHE,\n    output wire [2:0]                   AWPROT,\n    output wire [3:0]                   AWQOS,\n    output wire [3:0]                   AWREGION,\n    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,\n    output wire                         AWVALID,\n    input  wire                         AWREADY,\n    // write data channel\n    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,\n    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,\n    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,\n    output wire                         WLAST,\n    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,\n    output wire                         WVALID,\n    input  wire                         WREADY,\n    // write response channel\n    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,\n    input  wire [1:0]                   BRESP,\n    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,\n    input  wire                         BVALID,\n    output wire                         BREADY,\n    // read address channel\n    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,\n    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,\n    output wire [7:0]                   ARLEN,\n    output wire [2:0]                   ARSIZE,\n    output wire [1:0]                   ARBURST,\n    output wire [1:0]                   ARLOCK,\n    output wire [3:0]                   ARCACHE,\n    output wire [2:0]                   ARPROT,\n    output wire [3:0]                   ARQOS,\n    output wire [3:0]                   ARREGION,\n    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,\n    output wire                         ARVALID,\n    input  wire                         ARREADY,\n    // read data channel\n    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,\n    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,\n    input  wire [1:0]                   RRESP,\n    input  wire                         RLAST,\n    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,\n    input  wire                         RVALID,\n    output wire                         RREADY,\n\n    // internal bus ports\n    // write address\n    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,\n    input  wire [USER_AW-1:0]           I_AWADDR,\n    input  wire [31:0]                  I_AWLEN,\n    input  wire [2:0]                   I_AWSIZE,\n    input  wire [1:0]                   I_AWBURST,\n    input  wire [1:0]                   I_AWLOCK,\n    input  wire [3:0]                   I_AWCACHE,\n    input  wire [2:0]                   I_AWPROT,\n    input  wire [3:0]                   I_AWQOS,\n    input  wire [3:0]                   I_AWREGION,\n    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,\n    input  wire                         I_AWVALID,\n    output wire                         I_AWREADY,\n    // write data\n    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,\n    input  wire [USER_DW-1:0]           I_WDATA,\n    input  wire                         I_WLAST,\n    input  wire [USER_DW/8-1:0]         I_WSTRB,\n    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,\n    input  wire                         I_WVALID,\n    output wire                         I_WREADY,\n    // write response\n    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,\n    output wire [1:0]                   I_BRESP,\n    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,\n    output wire                         I_BVALID,\n    input  wire                         I_BREADY,\n    // read address\n    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,\n    input  wire [USER_AW-1:0]           I_ARADDR,\n    input  wire [31:0]                  I_ARLEN,\n    input  wire [2:0]                   I_ARSIZE,\n    input  wire [1:0]                   I_ARBURST,\n    input  wire [1:0]                   I_ARLOCK,\n    input  wire [3:0]                   I_ARCACHE,\n    input  wire [2:0]                   I_ARPROT,\n    input  wire [3:0]                   I_ARQOS,\n    input  wire [3:0]                   I_ARREGION,\n    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,\n    input  wire                         I_ARVALID,\n    output wire                         I_ARREADY,\n    // read data\n    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,\n    output wire [USER_DW-1:0]           I_RDATA,\n    output wire [1:0]                   I_RRESP,\n    output wire                         I_RLAST,\n    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,\n    output wire                         I_RVALID,\n    input  wire                         I_RREADY\n);\n//------------------------Parameter----------------------\n\n//------------------------Local signal-------------------\n\n// Write Address channel throttling unit\nwire  [7:0]         AWLEN_Dummy;\nwire                AWVALID_Dummy;\nwire                AWREADY_Dummy;\nwire                WVALID_Dummy;\n\nassign AWLEN     = AWLEN_Dummy;\nassign WVALID    = WVALID_Dummy;\ndds_DDS_OUTPUT1_m_axi_throttl #(\n    .USED_FIX(0)\n) wreq_throttl (\n    .clk(ACLK),\n    .reset(ARESET),\n    .ce(ACLK_EN),\n    .in_len(AWLEN_Dummy),\n    .in_req_valid(AWVALID_Dummy),\n    .out_req_valid(AWVALID),\n    .in_req_ready(AWREADY),\n    .out_req_ready(AWREADY_Dummy),\n    .in_data_valid(WVALID_Dummy),\n    .in_data_ready(WREADY)\n);\n// END of write Address channel throttling unit\n\nassign I_BID = 1'b0;\nassign I_BUSER = C_USER_VALUE;\nassign I_RID = 1'b0;\nassign I_RLAST = 1'b0;\nassign I_RUSER = C_USER_VALUE;\n//------------------------Instantiation------------------\n\n// dds_DDS_OUTPUT1_m_axi_write\ndds_DDS_OUTPUT1_m_axi_write #(\n    .NUM_WRITE_OUTSTANDING    ( NUM_WRITE_OUTSTANDING ),\n    .MAX_WRITE_BURST_LENGTH   ( MAX_WRITE_BURST_LENGTH ),\n    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),\n    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),\n    .C_TARGET_ADDR     ( C_TARGET_ADDR ),\n    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),\n    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),\n    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),\n    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),\n    .C_USER_VALUE      ( C_USER_VALUE ),\n    .C_PROT_VALUE      ( C_PROT_VALUE ),\n    .C_CACHE_VALUE     ( C_CACHE_VALUE ),\n    .USER_DW           ( USER_DW ),\n    .USER_AW           ( USER_AW ),\n    .USER_MAXREQS      ( USER_MAXREQS )\n) bus_write (\n    .ACLK              ( ACLK ),\n    .ARESET            ( ARESET ),\n    .ACLK_EN           ( ACLK_EN ),\n    .AWID              ( AWID ),\n    .AWADDR            ( AWADDR ),\n    .AWLEN             ( AWLEN_Dummy ),\n    .AWSIZE            ( AWSIZE ),\n    .AWBURST           ( AWBURST ),\n    .AWLOCK            ( AWLOCK ),\n    .AWCACHE           ( AWCACHE ),\n    .AWPROT            ( AWPROT ),\n    .AWQOS             ( AWQOS ),\n    .AWREGION          ( AWREGION ),\n    .AWUSER            ( AWUSER ),\n    .AWVALID           ( AWVALID_Dummy ),\n    .AWREADY           ( AWREADY_Dummy ),\n    .WID               ( WID ),\n    .WDATA             ( WDATA ),\n    .WSTRB             ( WSTRB ),\n    .WLAST             ( WLAST ),\n    .WUSER             ( WUSER ),\n    .WVALID            ( WVALID_Dummy ),\n    .WREADY            ( WREADY ),\n    .BID               ( BID ),\n    .BRESP             ( BRESP ),\n    .BUSER             ( BUSER ),\n    .BVALID            ( BVALID ),\n    .BREADY            ( BREADY ),\n    .wreq_valid        ( I_AWVALID ),\n    .wreq_ack          ( I_AWREADY ),\n    .wreq_addr         ( I_AWADDR ),\n    .wreq_length       ( I_AWLEN ),\n    .wreq_cache        ( I_AWCACHE ),\n    .wreq_prot         ( I_AWPROT ),\n    .wreq_qos          ( I_AWQOS ),\n    .wreq_user         ( I_AWUSER ),\n    .wdata_valid       ( I_WVALID ),\n    .wdata_ack         ( I_WREADY ),\n    .wdata_strb        ( I_WSTRB ),\n    .wdata_user        ( I_WUSER ),\n    .wdata_data        ( I_WDATA ),\n    .wrsp_valid        ( I_BVALID ),\n    .wrsp_ack          ( I_BREADY ),\n    .wrsp              ( I_BRESP )\n);\n\n// dds_DDS_OUTPUT1_m_axi_read\ndds_DDS_OUTPUT1_m_axi_read #(\n    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),\n    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),\n    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),\n    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),\n    .C_TARGET_ADDR     ( C_TARGET_ADDR ),\n    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),\n    .C_M_AXI_ARUSER_WIDTH    ( C_M_AXI_ARUSER_WIDTH ),\n    .C_M_AXI_RUSER_WIDTH     ( C_M_AXI_RUSER_WIDTH ),\n    .C_USER_VALUE      ( C_USER_VALUE ),\n    .C_PROT_VALUE      ( C_PROT_VALUE ),\n    .C_CACHE_VALUE     ( C_CACHE_VALUE ),\n    .USER_DW           ( USER_DW ),\n    .USER_AW           ( USER_AW ),\n    .USER_MAXREQS      ( USER_MAXREQS )\n) bus_read (\n    .ACLK              ( ACLK ),\n    .ARESET            ( ARESET ),\n    .ACLK_EN           ( ACLK_EN ),\n    .ARID              ( ARID ),\n    .ARADDR            ( ARADDR ),\n    .ARLEN             ( ARLEN ),\n    .ARSIZE            ( ARSIZE ),\n    .ARBURST           ( ARBURST ),\n    .ARLOCK            ( ARLOCK ),\n    .ARCACHE           ( ARCACHE ),\n    .ARPROT            ( ARPROT ),\n    .ARQOS             ( ARQOS ),\n    .ARREGION          ( ARREGION ),\n    .ARUSER            ( ARUSER ),\n    .ARVALID           ( ARVALID ),\n    .ARREADY           ( ARREADY ),\n    .RID               ( RID ),\n    .RDATA             ( RDATA ),\n    .RRESP             ( RRESP ),\n    .RLAST             ( RLAST ),\n    .RUSER             ( RUSER ),\n    .RVALID            ( RVALID ),\n    .RREADY            ( RREADY ),\n    .rreq_valid        ( I_ARVALID ),\n    .rreq_ack          ( I_ARREADY ),\n    .rreq_addr         ( I_ARADDR ),\n    .rreq_length       ( I_ARLEN ),\n    .rreq_cache        ( I_ARCACHE ),\n    .rreq_prot         ( I_ARPROT ),\n    .rreq_qos          ( I_ARQOS ),\n    .rreq_user         ( I_ARUSER ),\n    .rdata_valid       ( I_RVALID ),\n    .rdata_ack         ( I_RREADY ),\n    .rdata_data        ( I_RDATA ),\n    .rrsp              ( I_RRESP )\n);\nendmodule\n\nmodule dds_DDS_OUTPUT1_m_axi_reg_slice\n#(parameter\n    N = 8   // data width\n) (\n    // system signals\n    input  wire         sclk,\n    input  wire         reset,\n    // slave side\n    input  wire [N-1:0] s_data,\n    input  wire         s_valid,\n    output wire         s_ready,\n    // master side\n    output wire [N-1:0] m_data,\n    output wire         m_valid,\n    input  wire         m_ready\n);\n//------------------------Parameter----------------------\n// state\nlocalparam [1:0]\n    ZERO = 2'b10,\n    ONE  = 2'b11,\n    TWO  = 2'b01;\n//------------------------Local signal-------------------\nreg  [N-1:0] data_p1;\nreg  [N-1:0] data_p2;\nwire         load_p1;\nwire         load_p2;\nwire         load_p1_from_p2;\nreg          s_ready_t;\nreg  [1:0]   state;\nreg  [1:0]   next;\n//------------------------Body---------------------------\nassign s_ready = s_ready_t;\nassign m_data  = data_p1;\nassign m_valid = state[0];\n\nassign load_p1 = (state == ZERO && s_valid) ||\n                 (state == ONE && s_valid && m_ready) ||\n                 (state == TWO && m_ready);\nassign load_p2 = s_valid & s_ready;\nassign load_p1_from_p2 = (state == TWO);\n\n// data_p1\nalways @(posedge sclk) begin\n    if (load_p1) begin\n        if (load_p1_from_p2)\n            data_p1 <= data_p2;\n        else\n            data_p1 <= s_data;\n    end\nend\n\n// data_p2\nalways @(posedge sclk) begin\n    if (load_p2) data_p2 <= s_data;\nend\n\n// s_ready_t\nalways @(posedge sclk) begin\n    if (reset)\n        s_ready_t <= 1'b0;\n    else if (state == ZERO)\n        s_ready_t <= 1'b1;\n    else if (state == ONE && next == TWO)\n        s_ready_t <= 1'b0;\n    else if (state == TWO && next == ONE)\n        s_ready_t <= 1'b1;\nend\n\n// state\nalways @(posedge sclk) begin\n    if (reset)\n        state <= ZERO;\n    else\n        state <= next;\nend\n\n// next\nalways @(*) begin\n    case (state)\n        ZERO:\n            if (s_valid & s_ready)\n                next = ONE;\n            else\n                next = ZERO;\n        ONE:\n            if (~s_valid & m_ready)\n                next = ZERO;\n            else if (s_valid & ~m_ready)\n                next = TWO;\n            else\n                next = ONE;\n        TWO:\n            if (m_ready)\n                next = ONE;\n            else\n                next = TWO;\n        default:\n            next = ZERO;\n    endcase\nend\n\nendmodule\n\nmodule dds_DDS_OUTPUT1_m_axi_fifo\n#(parameter\n    DATA_BITS  = 8,\n    DEPTH      = 16,\n    DEPTH_BITS = 4\n)(\n    input  wire                 sclk,\n    input  wire                 reset,\n    input  wire                 sclk_en,\n    output reg                  empty_n,\n    output reg                  full_n,\n    input  wire                 rdreq,\n    input  wire                 wrreq,\n    output reg  [DATA_BITS-1:0] q,\n    input  wire [DATA_BITS-1:0] data\n);\n//------------------------Parameter----------------------\n\n//------------------------Local signal-------------------\nwire                  push;\nwire                  pop;\nwire                  full_cond;\nreg                   data_vld;\nreg  [DEPTH_BITS-1:0] pout;\nreg  [DATA_BITS-1:0]  mem[0:DEPTH-1];\n//------------------------Body---------------------------\nassign push = full_n & wrreq;\nassign pop  = data_vld & (~(empty_n & ~rdreq));\nif (DEPTH >= 2) begin\nassign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;\nend else begin\nassign full_cond = push && ~pop;\nend\n\n// q\nalways @(posedge sclk)\nbegin\n    if (reset)\n        q <= 0;\n    else if (sclk_en) begin\n        if (~(empty_n & ~rdreq))\n            q <= mem[pout];\n    end\nend\n\n// empty_n\nalways @(posedge sclk)\nbegin\n    if (reset)\n        empty_n <= 1'b0;\n    else if (sclk_en) begin\n        if (~(empty_n & ~rdreq))\n            empty_n <= data_vld;\n    end\nend\n\n// data_vld\nalways @(posedge sclk)\nbegin\n    if (reset)\n        data_vld <= 1'b0;\n    else if (sclk_en) begin\n        if (push)\n            data_vld <= 1'b1;\n        else if (~push && pop && pout == 1'b0)\n            data_vld <= 1'b0;\n    end\nend\n\n// full_n\nalways @(posedge sclk)\nbegin\n    if (reset)\n        full_n <= 1'b1;\n    else if (sclk_en) begin\n        if (pop)\n            full_n <= 1'b1;\n        else if (full_cond)\n            full_n <= 1'b0;\n    end\nend\n\n// pout\nalways @(posedge sclk)\nbegin\n    if (reset)\n        pout <= 1'b0;\n    else if (sclk_en) begin\n        if (push & ~pop & data_vld)\n            pout <= pout + 1'b1;\n        else if (~push && pop && pout != 1'b0)\n            pout <= pout - 1'b1;\n    end\nend\n\ninteger i;\nalways @(posedge sclk)\nbegin\n    if (sclk_en) begin\n        if (push) begin\n            for (i = 0; i < DEPTH - 1; i = i + 1) begin\n                mem[i+1] <= mem[i];\n            end\n            mem[0] <= data;\n        end\n    end\nend\nendmodule\n\nmodule dds_DDS_OUTPUT1_m_axi_buffer\n#(parameter\n    MEM_STYLE  = \"block\",\n    DATA_WIDTH = 32,\n    ADDR_WIDTH = 5,\n    DEPTH      = 32\n) (\n    // system signal\n    input  wire                  clk,\n    input  wire                  reset,\n    input  wire                  sclk_en,\n\n    // write\n    output wire                  if_full_n,\n    input  wire                  if_write_ce,\n    input  wire                  if_write,\n    input  wire [DATA_WIDTH-1:0] if_din,\n\n    // read\n    output wire                  if_empty_n,\n    input  wire                  if_read_ce,\n    input  wire                  if_read,\n    output wire [DATA_WIDTH-1:0] if_dout\n);\n//------------------------Parameter----------------------\n\n//------------------------Local signal-------------------\n(* ram_style = MEM_STYLE *)\nreg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];\nreg  [DATA_WIDTH-1:0] q_buf = 1'b0;\nreg  [ADDR_WIDTH-1:0] waddr = 1'b0;\nreg  [ADDR_WIDTH-1:0] raddr = 1'b0;\nwire [ADDR_WIDTH-1:0] wnext;\nwire [ADDR_WIDTH-1:0] rnext;\nwire                  push;\nwire                  pop;\nreg  [ADDR_WIDTH-1:0] usedw = 1'b0;\nreg                   full_n = 1'b1;\nreg                   empty_n = 1'b0;\nreg  [DATA_WIDTH-1:0] q_tmp = 1'b0;\nreg                   show_ahead = 1'b0;\nreg  [DATA_WIDTH-1:0] dout_buf = 1'b0;\nreg                   dout_valid = 1'b0;\n\n\n//------------------------Instantiation------------------\n\n//------------------------Task and function--------------\n\n//------------------------Body---------------------------\nassign if_full_n  = full_n;\nassign if_empty_n = dout_valid;\nassign if_dout    = dout_buf;\nassign push       = full_n & if_write_ce & if_write;\nassign pop        = empty_n & if_read_ce & (~dout_valid | if_read);\nassign wnext      = !push                ? waddr :\n                    (waddr == DEPTH - 1) ? 1'b0  :\n                    waddr + 1'b1;\nassign rnext      = !pop                 ? raddr :\n                    (raddr == DEPTH - 1) ? 1'b0  :\n                    raddr + 1'b1;\n\n// waddr\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        waddr <= 1'b0;\n    else if (sclk_en)\n        waddr <= wnext;\nend\n\n// raddr\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        raddr <= 1'b0;\n    else if (sclk_en)\n        raddr <= rnext;\nend\n\n// usedw\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        usedw <= 1'b0;\n    else if (sclk_en)\n        if (push & ~pop)\n            usedw <= usedw + 1'b1;\n        else if (~push & pop)\n            usedw <= usedw - 1'b1;\nend\n\n// full_n\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        full_n <= 1'b1;\n    else if (sclk_en)\n        if (push & ~pop)\n            full_n <= (usedw != DEPTH - 1);\n        else if (~push & pop)\n            full_n <= 1'b1;\nend\n\n// empty_n\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        empty_n <= 1'b0;\n    else if (sclk_en)\n        if (push & ~pop)\n            empty_n <= 1'b1;\n        else if (~push & pop)\n            empty_n <= (usedw != 1'b1);\nend\n\n// mem\nalways @(posedge clk) begin\n    if (push)\n        mem[waddr] <= if_din;\nend\n\n// q_buf\nalways @(posedge clk) begin\n    q_buf <= mem[rnext];\nend\n\n// q_tmp\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        q_tmp <= 1'b0;\n    else if (sclk_en)\n        if (push)\n            q_tmp <= if_din;\nend\n\n// show_ahead\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        show_ahead <= 1'b0;\n    else if (sclk_en)\n        if (push && usedw == pop)\n            show_ahead <= 1'b1;\n        else\n            show_ahead <= 1'b0;\nend\n\n// dout_buf\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        dout_buf <= 1'b0;\n    else if (sclk_en)\n        if (pop)\n            dout_buf <= show_ahead? q_tmp : q_buf;\nend\n\n// dout_valid\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        dout_valid <= 1'b0;\n    else if (sclk_en)\n        if (pop)\n            dout_valid <= 1'b1;\n        else if (if_read_ce & if_read)\n            dout_valid <= 1'b0;\nend\n\nendmodule\n`timescale 1ns/1ps\n\nmodule dds_DDS_OUTPUT1_m_axi_decoder\n#(parameter\n    DIN_WIDTH       = 3\n)(\n    input  wire [DIN_WIDTH-1:0]         din,\n    output reg  [2**DIN_WIDTH-1:0]      dout\n);\n    integer i;\n    always @(din) begin\n        dout = {2**DIN_WIDTH{1'b0}};\n        for (i=0; i < din; i = i + 1)\n            dout[i] = 1'b1;\n    end\nendmodule\n\n\nmodule dds_DDS_OUTPUT1_m_axi_throttl\n#(parameter\n    USED_FIX       = 0,\n    FIX_VALUE      = 4\n)(\n    input               clk,\n    input               reset,\n    input               ce,\n    input   [7:0]       in_len,\n    input               in_req_valid,\n    input               in_req_ready,\n    input               in_data_valid,\n    input               in_data_ready,\n    output              out_req_valid,\n    output              out_req_ready\n);\n\nlocalparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;\n\nwire                req_en;\nwire                handshake;\nwire  [7:0]         load_init;\nreg   [7:0]         throttl_cnt;\n\nif (USED_FIX) begin\n    assign load_init = FIX_VALUE-1;\n    assign handshake = 1'b1;\nend else begin\n    assign load_init = in_len;\n    assign handshake = in_data_valid & in_data_ready;\nend\n\nassign out_req_valid = in_req_valid & req_en;\nassign out_req_ready = in_req_ready & req_en;\nassign req_en = (throttl_cnt == 0);\n\nalways @(posedge clk)\nbegin\n    if (reset)\n        throttl_cnt <= 0;\n    else if (ce) begin\n        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)\n            throttl_cnt <= load_init; //load\n        else if (throttl_cnt > 0 && handshake)\n            throttl_cnt <= throttl_cnt - 1'b1;\n    end\nend\n\nendmodule\n\n`timescale 1ns/1ps\n\nmodule dds_DDS_OUTPUT1_m_axi_read\n#(parameter\n    NUM_READ_OUTSTANDING      = 2,\n    MAX_READ_BURST_LENGTH     = 16,\n    C_M_AXI_ID_WIDTH          = 1,\n    C_M_AXI_ADDR_WIDTH        = 32,\n    C_TARGET_ADDR             = 32'h00000000,\n    C_M_AXI_DATA_WIDTH        = 32,\n    C_M_AXI_ARUSER_WIDTH      = 1,\n    C_M_AXI_RUSER_WIDTH       = 1,\n    C_USER_VALUE              = 1'b0,\n    C_PROT_VALUE              = 3'b000,\n    C_CACHE_VALUE             = 4'b0011,\n    USER_DW                   = 16,\n    USER_AW                   = 32,\n    USER_MAXREQS              = 16\n)(\n    // system signal\n    input  wire                         ACLK,\n    input  wire                         ARESET,\n    input  wire                         ACLK_EN,\n    // read address channel\n    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,\n    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,\n    output wire [7:0]                   ARLEN,\n    output wire [2:0]                   ARSIZE,\n    output wire [1:0]                   ARBURST,\n    output wire [1:0]                   ARLOCK,\n    output wire [3:0]                   ARCACHE,\n    output wire [2:0]                   ARPROT,\n    output wire [3:0]                   ARQOS,\n    output wire [3:0]                   ARREGION,\n    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,\n    output wire                         ARVALID,\n    input  wire                         ARREADY,\n    // read data channel\n    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,\n    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,\n    input  wire [1:0]                   RRESP,\n    input  wire                         RLAST,\n    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,\n    input  wire                         RVALID,\n    output wire                         RREADY,\n    // read\n    input  wire                         rreq_valid,\n    output wire                         rreq_ack,\n    input  wire [USER_AW-1:0]           rreq_addr,\n    input  wire [31:0]                  rreq_length,\n    input  wire [3:0]                   rreq_cache,\n    input  wire [2:0]                   rreq_prot,\n    input  wire [3:0]                   rreq_qos,\n    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,\n    output wire [USER_DW-1:0]           rdata_data,\n    output wire [1:0]                   rrsp,\n    output wire                         rdata_valid,\n    input  wire                         rdata_ack\n);\n\n//------------------------Parameter----------------------\nlocalparam\n    USER_DATA_WIDTH = calc_data_width(USER_DW),\n    USER_DATA_BYTES = USER_DATA_WIDTH / 8,\n    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),\n    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,\n    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,\n    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),\n    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),\n    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),\n    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};\n\n//------------------------Task and function--------------\nfunction integer calc_data_width;\n    input integer x;\n    integer y;\nbegin\n    y = 8;\n    while (y < x) y = y * 2;\n    calc_data_width = y;\nend\nendfunction\n\nfunction integer log2;\n    input integer x;\n    integer n, m;\nbegin\n    n = 0;\n    m = 1;\n    while (m < x) begin\n        n = n + 1;\n        m = m * 2;\n    end\n    log2 = n;\nend\nendfunction\n\n//------------------------Local signal-------------------\n    // AR channel\n    wire [USER_AW + 31:0]                   rreq_data;\n    wire [USER_AW + 31:0]                   fifo_rreq_data;\n    wire [USER_AW - 1:0]                    tmp_addr;\n    wire [31:0]                             tmp_len;\n    reg  [31:0]                             align_len;\n    wire [7:0]                              arlen_tmp;\n    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;\n    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;\n    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;\n    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;\n    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;\n    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;\n    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;\n    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;\n    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;\n    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;\n    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;\n    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;\n    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;\n    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;\n    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;\n    wire [1:0]                              ar2r_ardata;\n    wire                                    fifo_rctl_r;\n    wire                                    zero_len_event;\n    wire                                    negative_len_event;\n    reg                                     invalid_len_event;\n    wire                                    fifo_rreq_valid;\n    reg                                     fifo_rreq_valid_buf;\n    wire                                    fifo_rreq_read;\n    wire                                    fifo_burst_w;\n    wire                                    fifo_resp_w;\n    reg                                     ARVALID_Dummy;\n    wire                                    ready_for_sect;\n    wire                                    next_rreq;\n    wire                                    ready_for_rreq;\n    reg                                     rreq_handling;\n    wire                                    first_sect;\n    wire                                    last_sect;\n    wire                                    next_sect;\n    // R channel\n    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;\n    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;\n    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;\n    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;\n    wire    [USER_DW + 1:0]                 rdata_data_pack;\n    reg     [7:0]                           len_cnt;\n    wire    [1:0]                           ar2r_rdata;\n    wire    [1:0]                           tmp_resp;\n    reg     [1:0]                           resp_buf;\n    wire                                    tmp_last;\n    wire                                    need_rlast;\n    wire                                    fifo_rctl_ready;\n    wire                                    beat_valid;\n    wire                                    next_beat;\n    wire                                    burst_valid;\n    wire                                    fifo_burst_ready;\n    wire                                    next_burst;\n    wire                                    rdata_ack_t;\n    reg                                     rdata_valid_t;\n\n//------------------------AR channel begin---------------\n//------------------------Instantiation------------------\n    dds_DDS_OUTPUT1_m_axi_fifo #(\n        .DATA_BITS(USER_AW + 32),\n        .DEPTH(USER_MAXREQS),\n        .DEPTH_BITS(log2(USER_MAXREQS))\n    ) fifo_rreq (\n        .sclk(ACLK),\n        .reset(ARESET),\n        .sclk_en(ACLK_EN),\n        .empty_n(fifo_rreq_valid),\n        .full_n(rreq_ack),\n        .rdreq(fifo_rreq_read),\n        .wrreq(rreq_valid),\n        .q(fifo_rreq_data),\n        .data(rreq_data));\n\n//------------------------Body---------------------------\n    assign rreq_data   = {rreq_length, rreq_addr};\n    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];\n    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];\n    assign end_addr    = start_addr + align_len;\n\n    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;\n    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            align_len   <= 0;\n        else if (ACLK_EN) begin\n            if(fifo_rreq_valid && ready_for_rreq)\n                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            start_addr <= 0;\n        else if (ACLK_EN) begin\n            if(fifo_rreq_valid && ready_for_rreq)\n                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            fifo_rreq_valid_buf <= 1'b0;\n        else if (ACLK_EN) begin\n            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)\n                fifo_rreq_valid_buf <= fifo_rreq_valid;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            invalid_len_event <= 1'b0;\n        else if (ACLK_EN) begin\n            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)\n                invalid_len_event <= zero_len_event || negative_len_event;\n        end\n    end\n\n    assign next_rreq      = !invalid_len_event && (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;\n    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));\n    assign fifo_rreq_read = invalid_len_event || next_rreq;\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            rreq_handling <= 1'b0;\n        else if (ACLK_EN) begin\n            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)\n                rreq_handling <= 1'b1;\n            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)\n                rreq_handling <= 1'b0;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            start_addr_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_rreq)\n                start_addr_buf <= start_addr;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            end_addr_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_rreq)\n                end_addr_buf <= end_addr;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            beat_len_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_rreq)\n                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            sect_cnt <= 0;\n        else if (ACLK_EN) begin\n            if (next_rreq)\n                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];\n            else if (next_sect)\n                sect_cnt <= sect_cnt + 1;\n        end\n    end\n\n    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);\n    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);\n    assign next_sect  = rreq_handling && ready_for_sect;\n\n    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            sect_addr_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_sect)\n                sect_addr_buf <= sect_addr;\n        end\n    end\n\n    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];\n    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :\n                         ( first_sect && ~last_sect)? start_to_4k:\n                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :\n                                                      BOUNDARY_BEATS;\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            sect_len_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_sect)\n                sect_len_buf <= sect_len;\n        end\n    end\n\n    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            sect_end_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_sect)\n                sect_end_buf <= sect_end;\n        end\n    end\n\n    assign ARID    = 0;\n    assign ARSIZE  = BUS_ADDR_ALIGN;\n    assign ARBURST = 2'b01;\n    assign ARLOCK  = 2'b00;\n    assign ARCACHE = C_CACHE_VALUE;\n    assign ARPROT  = C_PROT_VALUE;\n    assign ARUSER  = C_USER_VALUE;\n    assign ARQOS   = rreq_qos;\n\n    generate\n    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst\n        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};\n        assign ARLEN   = sect_len_buf;\n        assign ARVALID = ARVALID_Dummy;\n\n        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                ARVALID_Dummy <= 1'b0;\n            else if (ACLK_EN) begin\n                if (next_sect)\n                    ARVALID_Dummy <= 1'b1;\n                else if (~next_sect && ARREADY)\n                    ARVALID_Dummy <= 1'b0;\n            end\n        end\n\n        assign fifo_rctl_r  = next_sect;\n        assign ar2r_ardata  = {last_sect, 1'b0};\n\n        assign fifo_burst_w = next_sect;\n        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];\n        assign arlen_tmp    = sect_len;\n        assign burst_end    = sect_end;\n    end\n    else begin : could_multi_bursts\n        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;\n        reg  [7:0]                                      arlen_buf;\n        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;\n        reg                                             sect_handling;\n        wire                                            last_loop;\n        wire                                            next_loop;\n        wire                                            ready_for_loop;\n\n        assign ARADDR  = araddr_buf;\n        assign ARLEN   = arlen_buf;\n        assign ARVALID = ARVALID_Dummy;\n\n        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);\n        assign next_loop      = sect_handling && ready_for_loop;\n        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;\n        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                sect_handling <= 1'b0;\n            else if (ACLK_EN) begin\n                if (rreq_handling && ~sect_handling)\n                    sect_handling <= 1'b1;\n                else if (~rreq_handling && last_loop && next_loop)\n                    sect_handling <= 1'b0;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                loop_cnt <= 0;\n            else if (ACLK_EN) begin\n                if (next_sect)\n                    loop_cnt <= 0;\n                else if (next_loop)\n                    loop_cnt <= loop_cnt + 1;\n            end\n        end\n\n        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                araddr_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_loop)\n                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};\n            end\n        end\n\n        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                arlen_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_loop)\n                    arlen_buf <= arlen_tmp;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                ARVALID_Dummy <= 1'b0;\n            else if (ACLK_EN) begin\n                if (next_loop)\n                    ARVALID_Dummy <= 1'b1;\n                else if (~next_loop && ARREADY)\n                    ARVALID_Dummy <= 1'b0;\n            end\n        end\n\n        assign fifo_rctl_r = next_loop;\n        assign ar2r_ardata = {last_loop, 1'b0};\n\n        assign fifo_burst_w = next_loop;\n        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};\n    end\n    endgenerate\n//------------------------AR channel end-----------------\n\n//------------------------R channel begin----------------\n//------------------------Instantiation------------------\n    dds_DDS_OUTPUT1_m_axi_buffer #(\n        .DATA_WIDTH(BUS_DATA_WIDTH + 3),\n        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),\n        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))\n    ) buff_rdata (\n        .clk(ACLK),\n        .reset(ARESET),\n        .sclk_en(ACLK_EN),\n        .if_full_n(RREADY),\n        .if_write_ce(1'b1),\n        .if_write(RVALID),\n        .if_din(fifo_rresp_rdata),\n        .if_empty_n(beat_valid),\n        .if_read_ce(1'b1),\n        .if_read(next_beat),\n        .if_dout(data_pack));\n\n    dds_DDS_OUTPUT1_m_axi_reg_slice #(\n        .N(USER_DW + 2)\n    ) rs_rdata (\n        .sclk(ACLK),\n        .reset(ARESET),\n        .s_data(rs_rrsp_rdata),\n        .s_valid(rdata_valid_t),\n        .s_ready(rdata_ack_t),\n        .m_data(rdata_data_pack),\n        .m_valid(rdata_valid),\n        .m_ready(rdata_ack));\n\n    dds_DDS_OUTPUT1_m_axi_fifo #(\n        .DATA_BITS(2),\n        .DEPTH(NUM_READ_OUTSTANDING-1),\n        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))\n    ) fifo_rctl (\n        .sclk(ACLK),\n        .reset(ARESET),\n        .sclk_en(ACLK_EN),\n        .empty_n(need_rlast),\n        .full_n(fifo_rctl_ready),\n        .rdreq(tmp_last),\n        .wrreq(fifo_rctl_r),\n        .q(ar2r_rdata),\n        .data(ar2r_ardata));\n\n    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};\n    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];\n    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];\n    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;\n\n    generate\n    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen\n        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;\n        wire                                ready_for_data;\n\n        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};\n        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];\n        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];\n\n        assign fifo_burst_ready = 1'b1;\n        assign next_beat        = beat_valid && ready_for_data;\n        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                data_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_beat)\n                    data_buf <= tmp_data;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                resp_buf <= 2'b00;\n            else if (ACLK_EN) begin\n                if (next_beat)\n                    resp_buf <= tmp_resp;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                rdata_valid_t <= 1'b0;\n            else if (ACLK_EN) begin\n                if (next_beat)\n                    rdata_valid_t <= 1'b1;\n                else if (ready_for_data)\n                    rdata_valid_t <= 1'b0;\n            end\n        end\n    end\n    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen\n        localparam\n        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,\n            SPLIT_ALIGN     = log2(TOTAL_SPLIT);\n\n        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;\n        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;\n        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;\n        wire [SPLIT_ALIGN - 1:0]        split_cnt;\n        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;\n        wire [SPLIT_ALIGN - 1:0]        head_split;\n        wire [SPLIT_ALIGN - 1:0]        tail_split;\n        wire [7:0]                      arlen_tmp_t;\n        wire [7:0]                      burst_len;\n        wire                            first_beat;\n        wire                            last_beat;\n        wire                            first_split;\n        wire                            next_split;\n        wire                            last_split;\n        wire                            ready_for_data;\n\n        dds_DDS_OUTPUT1_m_axi_fifo #(\n            .DATA_BITS(2*SPLIT_ALIGN + 8),\n            .DEPTH(USER_MAXREQS),\n            .DEPTH_BITS(log2(USER_MAXREQS))\n        ) fifo_burst (\n            .sclk(ACLK),\n            .reset(ARESET),\n            .sclk_en(ACLK_EN),\n            .empty_n(burst_valid),\n            .full_n(fifo_burst_ready),\n            .rdreq(next_burst),\n            .wrreq(fifo_burst_w),\n            .q(burst_pack),\n            .data(tmp_burst_info));\n\n        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};\n        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];\n        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];\n\n        assign arlen_tmp_t    = arlen_tmp;\n        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};\n        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];\n        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];\n        assign burst_len      = burst_pack[7:0];\n\n        assign next_beat        = last_split;\n        assign next_burst       = last_beat && last_split;\n        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);\n\n        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;\n        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;\n\n        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);\n        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);\n        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);\n\n        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                split_cnt_buf <= 0;\n            else if (ACLK_EN) begin\n                if (last_split)\n                    split_cnt_buf <= 0;\n                else if (first_split || next_split)\n                    split_cnt_buf <= split_cnt + 1;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                len_cnt <= 0;\n            else if (ACLK_EN) begin\n                if (last_beat && last_split)\n                    len_cnt <= 0;\n                else if (last_split)\n                    len_cnt <= len_cnt + 1;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                data_buf <= 0;\n            else if (ACLK_EN) begin\n                if (first_split && first_beat)\n                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);\n                else if (first_split)\n                    data_buf <= tmp_data;\n                else if (next_split)\n                    data_buf <= data_buf >> USER_DATA_WIDTH;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                resp_buf <= 2'b00;\n            else if (ACLK_EN) begin\n                if (first_split)\n                    resp_buf <= tmp_resp;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                rdata_valid_t <= 0;\n            else if (ACLK_EN) begin\n                if (first_split)\n                    rdata_valid_t <= 1;\n                else if (~(first_split || next_split) && ready_for_data)\n                    rdata_valid_t <= 0;\n            end\n        end\n\n    end\n    else begin: bus_narrow_gen\n        localparam\n            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,\n            PAD_ALIGN       = log2(TOTAL_PADS);\n\n        reg  [USER_DATA_WIDTH - 1:0]        data_buf;\n        wire [TOTAL_PADS - 1:0]             pad_oh;\n        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;\n        wire                                ready_for_data;\n        wire                                next_pad;\n        reg                                 first_pad;\n        wire                                last_pad;\n        wire                                next_data;\n\n        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};\n        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];\n        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];\n\n        assign fifo_burst_ready = 1'b1;\n        assign next_beat        = next_pad;\n        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);\n\n        assign next_pad  = beat_valid && ready_for_data;\n        assign last_pad  = pad_oh[TOTAL_PADS - 1];\n        assign next_data = last_pad && ready_for_data;\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                first_pad <= 1;\n            else if (ACLK_EN) begin\n                if (next_pad && ~last_pad)\n                    first_pad <= 0;\n                else if (next_pad && last_pad)\n                    first_pad <= 1;\n            end\n        end\n\n        assign pad_oh = (beat_valid == 0)?  0 :\n                        (first_pad)?        1 :\n                                            pad_oh_reg;\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                pad_oh_reg <= 0;\n            else if (ACLK_EN) begin\n                if (next_pad)\n                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};\n            end\n        end\n\n        genvar  i;\n        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen\n            always @(posedge ACLK)\n            begin\n                if (ARESET)\n                    data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= 0;\n                else if (ACLK_EN) begin\n                    if (pad_oh[i-1] == 1'b1 && ready_for_data)\n                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;\n                end\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                resp_buf <= 2'b00;\n            else if (ACLK_EN) begin\n                if (next_beat && (resp_buf[0] ==1'b0))\n                    resp_buf <= tmp_resp;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                rdata_valid_t <= 0;\n            else if (ACLK_EN) begin\n                if (next_data)\n                    rdata_valid_t <= 1;\n                else if (ready_for_data)\n                    rdata_valid_t <= 0;\n            end\n        end\n    end\n    endgenerate\n\n//------------------------Body---------------------------\n//------------------------R channel end------------------\nendmodule\n\nmodule dds_DDS_OUTPUT1_m_axi_write\n#(parameter\n    NUM_WRITE_OUTSTANDING     = 2,\n    MAX_WRITE_BURST_LENGTH    = 16,\n    C_M_AXI_ID_WIDTH          = 1,\n    C_M_AXI_ADDR_WIDTH        = 32,\n    C_TARGET_ADDR             = 32'h00000000,\n    C_M_AXI_DATA_WIDTH        = 32,\n    C_M_AXI_AWUSER_WIDTH      = 1,\n    C_M_AXI_WUSER_WIDTH       = 1,\n    C_M_AXI_BUSER_WIDTH       = 1,\n    C_USER_VALUE              = 1'b0,\n    C_PROT_VALUE              = 3'b000,\n    C_CACHE_VALUE             = 4'b0011,\n    USER_DW                   = 16,\n    USER_AW                   = 32,\n    USER_MAXREQS              = 16\n)(\n    // system signal\n    input  wire                         ACLK,\n    input  wire                         ARESET,\n    input  wire                         ACLK_EN,\n    // write address channel\n    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,\n    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,\n    output wire [7:0]                   AWLEN,\n    output wire [2:0]                   AWSIZE,\n    output wire [1:0]                   AWBURST,\n    output wire [1:0]                   AWLOCK,\n    output wire [3:0]                   AWCACHE,\n    output wire [2:0]                   AWPROT,\n    output wire [3:0]                   AWQOS,\n    output wire [3:0]                   AWREGION,\n    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,\n    output wire                         AWVALID,\n    input  wire                         AWREADY,\n    // write data channel\n    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,\n    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,\n    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,\n    output wire                         WLAST,\n    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,\n    output wire                         WVALID,\n    input  wire                         WREADY,\n    // write response channel\n    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,\n    input  wire [1:0]                   BRESP,\n    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,\n    input  wire                         BVALID,\n    output wire                         BREADY,\n    // write request\n    input  wire                         wreq_valid,\n    output wire                         wreq_ack,\n    input  wire [USER_AW-1:0]           wreq_addr,\n    input  wire [31:0]                  wreq_length,\n    input  wire [3:0]                   wreq_cache,\n    input  wire [2:0]                   wreq_prot,\n    input  wire [3:0]                   wreq_qos,\n    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,\n    input  wire                         wdata_valid,\n    output wire                         wdata_ack,\n    input  wire [USER_DW/8-1:0]         wdata_strb,\n    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,\n    input  wire [USER_DW-1:0]           wdata_data,\n    output wire                         wrsp_valid,\n    input  wire                         wrsp_ack,\n    output wire [1:0]                   wrsp\n);\n\n//------------------------Parameter----------------------\nlocalparam\n    USER_DATA_WIDTH = calc_data_width(USER_DW),\n    USER_DATA_BYTES = USER_DATA_WIDTH / 8,\n    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),\n    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,\n    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,\n    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),\n    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),\n    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),\n    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};\n\n//------------------------Task and function--------------\nfunction integer calc_data_width;\n    input integer x;\n    integer y;\nbegin\n    y = 8;\n    while (y < x) y = y * 2;\n    calc_data_width = y;\nend\nendfunction\n\nfunction integer log2;\n    input integer x;\n    integer n, m;\nbegin\n    n = 0;\n    m = 1;\n    while (m < x) begin\n        n = n + 1;\n        m = m * 2;\n    end\n    log2 = n;\nend\nendfunction\n\n//------------------------Local signal-------------------\n    // AW channel\n    wire [USER_AW + 31:0]                   wreq_data;\n    wire [USER_AW + 31:0]                   fifo_wreq_data;\n    wire [USER_AW - 1:0]                    tmp_addr;\n    wire [31:0]                             tmp_len;\n    reg  [31:0]                             align_len;\n    wire [7:0]                              awlen_tmp;\n    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;\n    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;\n    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;\n    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;\n    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;\n    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;\n    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;\n    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;\n    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;\n    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;\n    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;\n    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;\n    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;\n    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;\n    wire [1:0]                              aw2b_awdata;\n    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;\n    wire                                    zero_len_event;\n    wire                                    negative_len_event;\n    reg                                     invalid_len_event;\n    reg                                     invalid_len_event_reg1;\n    reg                                     invalid_len_event_reg2;\n    wire                                    fifo_wreq_valid;\n    reg                                     fifo_wreq_valid_buf;\n    wire                                    fifo_wreq_read;\n    wire                                    fifo_burst_w;\n    wire                                    fifo_resp_w;\n    reg                                     AWVALID_Dummy;\n    reg                                     last_sect_buf;\n    wire                                    ready_for_sect;\n    wire                                    next_wreq;\n    wire                                    ready_for_wreq;\n    reg                                     wreq_handling;\n    wire                                    first_sect;\n    wire                                    last_sect;\n    wire                                    next_sect;\n    // W channel\n    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;\n    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;\n    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;\n    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;\n    reg     [7:0]                           len_cnt;\n    wire    [7:0]                           burst_len;\n    wire                                    beat_valid;\n    wire                                    next_data;\n    wire                                    burst_valid;\n    wire                                    fifo_burst_ready;\n    wire                                    next_burst;\n    reg                                     WVALID_Dummy;\n    reg                                     WLAST_Dummy;\n    //B channel\n    wire    [1:0]                           aw2b_bdata;\n    reg     [1:0]                           bresp_tmp;\n    reg                                     next_resp;\n    wire                                    last_resp;\n    wire                                    invalid_event;\n    wire                                    fifo_resp_ready;\n    wire                                    need_wrsp;\n    wire                                    resp_match;\n    wire                                    resp_ready;\n\n//------------------------AW channel begin---------------\n//------------------------Instantiation------------------\n    dds_DDS_OUTPUT1_m_axi_fifo #(\n        .DATA_BITS(USER_AW + 32),\n        .DEPTH(USER_MAXREQS),\n        .DEPTH_BITS(log2(USER_MAXREQS))\n    ) fifo_wreq (\n        .sclk(ACLK),\n        .reset(ARESET),\n        .sclk_en(ACLK_EN),\n        .empty_n(fifo_wreq_valid),\n        .full_n(wreq_ack),\n        .rdreq(fifo_wreq_read),\n        .wrreq(wreq_valid),\n        .q(fifo_wreq_data),\n        .data(wreq_data));\n\n//------------------------Body---------------------------\n    assign wreq_data   = {wreq_length, wreq_addr};\n    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];\n    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];\n\n    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;\n    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;\n\n    assign end_addr    = start_addr + align_len;\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            align_len   <= 0;\n        else if (ACLK_EN) begin\n            if(fifo_wreq_valid && ready_for_wreq) begin\n                if (zero_len_event || negative_len_event)\n                    align_len   <= 32'b0;\n                else\n                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;\n            end\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            start_addr <= 0;\n        else if (ACLK_EN) begin\n            if(fifo_wreq_valid && ready_for_wreq)\n                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            fifo_wreq_valid_buf <= 1'b0;\n        else if (ACLK_EN) begin\n            if(next_wreq)\n                fifo_wreq_valid_buf <= fifo_wreq_valid;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            invalid_len_event <= 1'b0;\n        else if (ACLK_EN) begin\n            if(next_wreq)\n                invalid_len_event <= zero_len_event || negative_len_event;\n        end\n    end\n\n    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;\n    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));\n    assign fifo_wreq_read = next_wreq;\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            wreq_handling <= 1'b0;\n        else if (ACLK_EN) begin\n            if (fifo_wreq_valid_buf && ~wreq_handling)\n                wreq_handling <= 1'b1;\n            else if (~fifo_wreq_valid_buf && last_sect && next_sect)\n                wreq_handling <= 1'b0;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            start_addr_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_wreq)\n                start_addr_buf <= start_addr;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            end_addr_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_wreq)\n                end_addr_buf <= end_addr;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            beat_len_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_wreq)\n                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            sect_cnt <= 0;\n        else if (ACLK_EN) begin\n            if (next_wreq)\n                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];\n            else if (next_sect)\n                sect_cnt <= sect_cnt + 1;\n        end\n    end\n\n    // event registers\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            invalid_len_event_reg1 <= 0;\n        else if (ACLK_EN) begin\n            invalid_len_event_reg1 <= invalid_len_event;\n        end\n    end\n    // end event registers\n\n    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);\n    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);\n    assign next_sect  = wreq_handling && ready_for_sect;\n\n    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            sect_addr_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_sect)\n                sect_addr_buf <= sect_addr;\n        end\n    end\n\n    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];\n    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :\n                         ( first_sect && ~last_sect)? start_to_4k:\n                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :\n                                                      BOUNDARY_BEATS;\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            sect_len_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_sect)\n                sect_len_buf <= sect_len;\n        end\n    end\n\n    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            sect_end_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_sect)\n                sect_end_buf <= sect_end;\n        end\n    end\n\n    // event registers\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            invalid_len_event_reg2 <= 0;\n        else if (ACLK_EN) begin\n            invalid_len_event_reg2 <= invalid_len_event_reg1;\n        end\n    end \n    // end event registers\n\n    assign AWID    = 0;\n    assign AWSIZE  = BUS_ADDR_ALIGN;\n    assign AWBURST = 2'b01;\n    assign AWLOCK  = 2'b00;\n    assign AWCACHE = C_CACHE_VALUE;\n    assign AWPROT  = C_PROT_VALUE;\n    assign AWUSER  = C_USER_VALUE;\n    assign AWQOS   = wreq_qos;\n\n    generate\n    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst\n        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};\n        assign AWLEN   = sect_len_buf;\n        assign AWVALID = AWVALID_Dummy;\n\n        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                AWVALID_Dummy <= 1'b0;\n            else if (ACLK_EN) begin\n                if (invalid_len_event)\n                    AWVALID_Dummy <= 1'b0;\n                else if (next_sect)\n                    AWVALID_Dummy <= 1'b1;\n                else if (~next_sect && AWREADY)\n                    AWVALID_Dummy <= 1'b0;\n            end\n        end\n\n        assign fifo_resp_w = next_sect;\n        assign aw2b_awdata = {last_sect, invalid_len_event};\n\n        assign fifo_burst_w = next_sect;\n        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];\n        assign awlen_tmp    = sect_len;\n        assign burst_end    = sect_end;\n    end\n    else begin : could_multi_bursts\n        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;\n        reg  [7:0]                                          awlen_buf;\n        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;\n        reg                                                 sect_handling;\n        wire                                                last_loop;\n        wire                                                next_loop;\n        wire                                                ready_for_loop;\n\n        assign AWADDR  = awaddr_buf;\n        assign AWLEN   = awlen_buf;\n        assign AWVALID = AWVALID_Dummy;\n\n        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);\n        assign next_loop      = sect_handling && ready_for_loop;\n        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;\n        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                sect_handling <= 1'b0;\n            else if (ACLK_EN) begin\n                if (wreq_handling && ~sect_handling)\n                    sect_handling <= 1'b1;\n                else if (~wreq_handling && last_loop && next_loop)\n                    sect_handling <= 1'b0;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                loop_cnt <= 0;\n            else if (ACLK_EN) begin\n                if (next_sect)\n                    loop_cnt <= 0;\n                else if (next_loop)\n                    loop_cnt <= loop_cnt + 1;\n            end\n        end\n\n        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                awaddr_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_loop)\n                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};\n            end\n        end\n\n        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                awlen_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_loop)\n                    awlen_buf <= awlen_tmp;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                AWVALID_Dummy <= 1'b0;\n            else if (ACLK_EN) begin\n                if (invalid_len_event_reg2)\n                    AWVALID_Dummy <= 1'b0;\n                else if (next_loop)\n                    AWVALID_Dummy <= 1'b1;\n                else if (~next_loop && AWREADY)\n                    AWVALID_Dummy <= 1'b0;\n            end\n        end\n\n        assign fifo_resp_w = next_loop;\n        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                last_sect_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_sect && last_sect)\n                    last_sect_buf <= 1;\n                else if (next_sect)\n                    last_sect_buf <= 0;\n            end\n        end\n\n        assign fifo_burst_w = next_loop;\n        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};\n    end\n    endgenerate\n//------------------------AW channel end-----------------\n\n//------------------------W channel begin----------------\n//------------------------Instantiation------------------\n    dds_DDS_OUTPUT1_m_axi_buffer #(\n        .DATA_WIDTH(USER_DW + USER_DW/8),\n        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),\n        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))\n    ) buff_wdata (\n        .clk(ACLK),\n        .reset(ARESET),\n        .sclk_en(ACLK_EN),\n        .if_full_n(wdata_ack),\n        .if_write_ce(1'b1),\n        .if_write(wdata_valid),\n        .if_din(fifo_wdata_wstrb),\n        .if_empty_n(data_valid),\n        .if_read_ce(1'b1),\n        .if_read(next_data),\n        .if_dout(data_pack)\n    );\n\n//------------------------Body---------------------------\n    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};\n    assign tmp_data         = data_pack[USER_DW - 1:0];\n    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];\n\n    generate\n    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen\n        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;\n        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;\n        wire [7:0]                          tmp_burst_info;\n        wire                                ready_for_data;\n\n        dds_DDS_OUTPUT1_m_axi_fifo #(\n            .DATA_BITS(8),\n            .DEPTH(USER_MAXREQS),\n            .DEPTH_BITS(log2(USER_MAXREQS))\n        ) fifo_burst (\n            .sclk(ACLK),\n            .reset(ARESET),\n            .sclk_en(ACLK_EN),\n            .empty_n(burst_valid),\n            .full_n(fifo_burst_ready),\n            .rdreq(next_burst),\n            .wrreq(fifo_burst_w),\n            .q(burst_len),\n            .data(tmp_burst_info));\n\n        assign WDATA   = data_buf;\n        assign WSTRB   = strb_buf;\n        assign WLAST   = WLAST_Dummy;\n        assign WVALID  = WVALID_Dummy;\n\n        assign tmp_burst_info = awlen_tmp;\n\n        assign next_data        = burst_valid && data_valid && ready_for_data;\n        assign next_burst       = (len_cnt == burst_len) && next_data;\n        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                data_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_data)\n                    data_buf <= tmp_data;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                strb_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_data)\n                    strb_buf <= tmp_strb;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                WVALID_Dummy <= 1'b0;\n            else if (ACLK_EN) begin\n                if (next_data)\n                    WVALID_Dummy <= 1'b1;\n                else if (ready_for_data)\n                    WVALID_Dummy <= 1'b0;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                WLAST_Dummy <= 0;\n            else if (ACLK_EN) begin\n                if (next_burst)\n                    WLAST_Dummy <= 1;\n                else if (ready_for_data)\n                    WLAST_Dummy <= 0;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                len_cnt <= 0;\n            else if (ACLK_EN) begin\n                if (next_burst)\n                    len_cnt <= 0;\n                else if (next_data)\n                    len_cnt <= len_cnt + 1;\n            end\n        end\n\n    end\n    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen\n        localparam\n            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,\n            SPLIT_ALIGN     = log2(TOTAL_SPLIT);\n\n        reg  [USER_DATA_WIDTH - 1:0]                data_buf;\n        reg  [USER_DATA_BYTES - 1:0]                strb_buf;\n        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;\n        wire [7:0]                                  tmp_burst_info;\n        wire                                        first_split;\n        wire                                        next_split;\n        wire                                        last_split;\n        wire                                        ready_for_data;\n\n        dds_DDS_OUTPUT1_m_axi_fifo #(\n            .DATA_BITS(8),\n            .DEPTH(USER_MAXREQS),\n            .DEPTH_BITS(log2(USER_MAXREQS))\n        ) fifo_burst (\n            .sclk(ACLK),\n            .reset(ARESET),\n            .sclk_en(ACLK_EN),\n            .empty_n(burst_valid),\n            .full_n(fifo_burst_ready),\n            .rdreq(next_burst),\n            .wrreq(fifo_burst_w),\n            .q(burst_len),\n            .data(tmp_burst_info));\n\n        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];\n        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];\n        assign WLAST   = WLAST_Dummy;\n        assign WVALID  = WVALID_Dummy;\n\n        assign tmp_burst_info = awlen_tmp;\n\n        assign next_data        = first_split;\n        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;\n        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);\n\n        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;\n        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;\n        assign next_split  = (split_cnt != 0) && ready_for_data;\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                split_cnt <= 0;\n            else if (ACLK_EN) begin\n                if (last_split)\n                    split_cnt <= 0;\n                else if (first_split || next_split)\n                    split_cnt <= split_cnt + 1;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                len_cnt <= 0;\n            else if (ACLK_EN) begin\n                if (next_burst)\n                    len_cnt <= 0;\n                else if (next_data || next_split)\n                    len_cnt <= len_cnt + 1;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                data_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_data)\n                    data_buf <= tmp_data;\n                else if (next_split)\n                    data_buf <= data_buf >> BUS_DATA_WIDTH;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                strb_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_data)\n                    strb_buf <= tmp_strb;\n                else if (next_split)\n                    strb_buf <= strb_buf >> BUS_DATA_BYTES;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                WVALID_Dummy <= 0;\n            else if (ACLK_EN) begin\n                if (next_data)\n                    WVALID_Dummy <= 1;\n                else if (~(first_split || next_split) && ready_for_data)\n                    WVALID_Dummy <= 0;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                WLAST_Dummy <= 0;\n            else if (ACLK_EN) begin\n                if (next_burst && last_split)\n                    WLAST_Dummy <= 1;\n                else if (ready_for_data)\n                    WLAST_Dummy <= 0;\n            end\n        end\n\n    end\n    else begin: bus_wide_gen\n        localparam\n            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,\n            PAD_ALIGN       = log2(TOTAL_PADS);\n\n        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;\n        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;\n        wire [2*PAD_ALIGN + 7:0]                    burst_pack;\n        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;\n        wire [PAD_ALIGN - 1:0]                      head_pads;\n        wire [PAD_ALIGN - 1:0]                      tail_pads;\n        wire [TOTAL_PADS - 1:0]                     add_head;\n        wire [TOTAL_PADS - 1:0]                     add_tail;\n        wire [TOTAL_PADS - 1:0]                     pad_oh;\n        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;\n        wire [TOTAL_PADS - 1:0]                     head_pad_sel;\n        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;\n        wire [7:0]                                  awlen_tmp_t;\n        wire                                        ready_for_data;\n        wire                                        next_pad;\n        reg                                         first_pad;\n        wire                                        last_pad;\n        wire                                        first_beat;\n        wire                                        last_beat;\n        wire                                        next_beat;\n\n        dds_DDS_OUTPUT1_m_axi_fifo #(\n            .DATA_BITS(8 + 2*PAD_ALIGN),\n            .DEPTH(USER_MAXREQS),\n            .DEPTH_BITS(log2(USER_MAXREQS))\n        ) fifo_burst (\n            .sclk(ACLK),\n            .reset(ARESET),\n            .sclk_en(ACLK_EN),\n            .empty_n(burst_valid),\n            .full_n(fifo_burst_ready),\n            .rdreq(next_burst),\n            .wrreq(fifo_burst_w),\n            .q(burst_pack),\n            .data(tmp_burst_info));\n\n        assign WDATA   = data_buf;\n        assign WSTRB   = strb_buf;\n        assign WLAST   = WLAST_Dummy;\n        assign WVALID  = WVALID_Dummy;\n\n        assign awlen_tmp_t = awlen_tmp;\n        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};\n\n        dds_DDS_OUTPUT1_m_axi_decoder #(\n            .DIN_WIDTH(PAD_ALIGN)\n        ) head_pad_decoder (\n            .din(head_pads),\n            .dout(head_pad_sel));\n\n        dds_DDS_OUTPUT1_m_axi_decoder #(\n            .DIN_WIDTH(PAD_ALIGN)\n        ) tail_pad_decoder (\n            .din(tail_pads),\n            .dout(tail_pad_sel));\n\n        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];\n        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];\n        assign burst_len = burst_pack[7:0];\n\n        assign next_data        = next_pad;\n        assign next_burst       = last_beat && next_beat;\n        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);\n\n        assign first_beat = (len_cnt == 0) && burst_valid;\n        assign last_beat  = (len_cnt == burst_len) && burst_valid;\n        assign next_beat  = burst_valid && last_pad && ready_for_data;\n\n        assign next_pad  = burst_valid && data_valid && ready_for_data;\n        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                first_pad <= 1;\n            else if (ACLK_EN) begin\n                if (next_pad && ~last_pad)\n                    first_pad <= 0;\n                else if (next_pad && last_pad)\n                    first_pad <= 1;\n            end\n        end\n\n        assign pad_oh = (data_valid == 0)?          0 :\n                        (first_pad && first_beat)?  1 << head_pads :\n                        (first_pad)?                1 :\n                                                    pad_oh_reg;\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                pad_oh_reg <= 0;\n            else if (ACLK_EN) begin\n                if (next_pad)\n                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};\n            end\n        end\n\n        genvar  i;\n        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen\n            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;\n            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;\n\n            always @(posedge ACLK)\n            begin\n                if (ARESET)\n                    data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;\n                else if (ACLK_EN) begin\n                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)\n                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;\n                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)\n                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;\n                end\n            end\n\n            always @(posedge ACLK)\n            begin\n                if (ARESET)\n                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;\n                else if (ACLK_EN) begin\n                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)\n                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;\n                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)\n                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;\n                end\n            end\n\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                WVALID_Dummy <= 0;\n            else if (ACLK_EN) begin\n                if (next_beat)\n                    WVALID_Dummy <= 1;\n                else if (ready_for_data)\n                    WVALID_Dummy <= 0;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                WLAST_Dummy <= 0;\n            else if (ACLK_EN) begin\n                if (next_burst)\n                    WLAST_Dummy <= 1;\n                else if (ready_for_data)\n                    WLAST_Dummy <= 0;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                len_cnt <= 0;\n            else if (ACLK_EN) begin\n                if (next_burst)\n                    len_cnt <= 0;\n                else if (next_beat)\n                    len_cnt <= len_cnt + 1;\n            end\n        end\n\n    end\n    endgenerate\n\n//------------------------W channel end------------------\n\n//------------------------B channel begin----------------\n//------------------------Instantiation------------------\n    dds_DDS_OUTPUT1_m_axi_fifo #(\n        .DATA_BITS(2),\n        .DEPTH(NUM_WRITE_OUTSTANDING-1),\n        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))\n    ) fifo_resp (\n        .sclk(ACLK),\n        .reset(ARESET),\n        .sclk_en(ACLK_EN),\n        .empty_n(need_wrsp),\n        .full_n(fifo_resp_ready),\n        .rdreq(next_resp),\n        .wrreq(fifo_resp_w),\n        .q(aw2b_bdata),\n        .data(aw2b_awdata));\n\n    dds_DDS_OUTPUT1_m_axi_fifo #(\n        .DATA_BITS(2),\n        .DEPTH(USER_MAXREQS),\n        .DEPTH_BITS(log2(USER_MAXREQS))\n    ) fifo_resp_to_user (\n        .sclk(ACLK),\n        .reset(ARESET),\n        .sclk_en(ACLK_EN),\n        .empty_n(wrsp_valid),\n        .full_n(resp_ready),\n        .rdreq(wrsp_ack),\n        .wrreq(resp_match),\n        .q(wrsp),\n        .data(bresp_tmp));\n\n//------------------------Body---------------------------\n    assign BREADY = resp_ready;\n    assign last_resp = aw2b_bdata[1];\n    assign invalid_event = aw2b_bdata[0];\n    assign resp_match = ((next_resp && last_resp) || invalid_event) && need_wrsp;\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            next_resp <= 1'b0;\n        else if (ACLK_EN) begin\n            next_resp <= BVALID && resp_ready;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            bresp_tmp <= 2'b00;\n        else if (ACLK_EN) begin\n            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0\n                bresp_tmp <= 2'b00;\n            else if (resp_match && next_resp)       // last resp but has resp for next cycle\n                bresp_tmp <= BRESP;\n            else if (BVALID && resp_ready && ~bresp_tmp[1])\n                bresp_tmp <= BRESP;\n        end\n    end\n\n//------------------------B channel end------------------\nendmodule\n", "num_lines": 2464}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// ==============================================================\n// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC\n// Version: 2016.3\n// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.\n// \n// ==============================================================\n\n`timescale 1ns/1ps\n\nmodule dds_DDS_OUTPUT_m_axi\n#(parameter\n    NUM_READ_OUTSTANDING    = 2,\n    NUM_WRITE_OUTSTANDING   = 2,\n    MAX_READ_BURST_LENGTH   = 16,\n    MAX_WRITE_BURST_LENGTH  = 16,\n    C_M_AXI_ID_WIDTH        = 1,\n    C_M_AXI_ADDR_WIDTH      = 32,\n    C_TARGET_ADDR           = 32'h00000000,\n    C_M_AXI_DATA_WIDTH      = 32,\n    C_M_AXI_AWUSER_WIDTH    = 1,\n    C_M_AXI_ARUSER_WIDTH    = 1,\n    C_M_AXI_WUSER_WIDTH     = 1,\n    C_M_AXI_RUSER_WIDTH     = 1,\n    C_M_AXI_BUSER_WIDTH     = 1,\n    C_USER_VALUE      = 1'b0,\n    C_PROT_VALUE      = 3'b000,\n    C_CACHE_VALUE     = 4'b0011,\n    USER_DW           = 16,\n    USER_AW           = 32,\n    USER_MAXREQS      = 16\n)(\n    // system signal\n    input  wire                         ACLK,\n    input  wire                         ARESET,\n    input  wire                         ACLK_EN,\n    // write address channel\n    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,\n    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,\n    output wire [7:0]                   AWLEN,\n    output wire [2:0]                   AWSIZE,\n    output wire [1:0]                   AWBURST,\n    output wire [1:0]                   AWLOCK,\n    output wire [3:0]                   AWCACHE,\n    output wire [2:0]                   AWPROT,\n    output wire [3:0]                   AWQOS,\n    output wire [3:0]                   AWREGION,\n    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,\n    output wire                         AWVALID,\n    input  wire                         AWREADY,\n    // write data channel\n    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,\n    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,\n    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,\n    output wire                         WLAST,\n    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,\n    output wire                         WVALID,\n    input  wire                         WREADY,\n    // write response channel\n    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,\n    input  wire [1:0]                   BRESP,\n    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,\n    input  wire                         BVALID,\n    output wire                         BREADY,\n    // read address channel\n    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,\n    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,\n    output wire [7:0]                   ARLEN,\n    output wire [2:0]                   ARSIZE,\n    output wire [1:0]                   ARBURST,\n    output wire [1:0]                   ARLOCK,\n    output wire [3:0]                   ARCACHE,\n    output wire [2:0]                   ARPROT,\n    output wire [3:0]                   ARQOS,\n    output wire [3:0]                   ARREGION,\n    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,\n    output wire                         ARVALID,\n    input  wire                         ARREADY,\n    // read data channel\n    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,\n    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,\n    input  wire [1:0]                   RRESP,\n    input  wire                         RLAST,\n    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,\n    input  wire                         RVALID,\n    output wire                         RREADY,\n\n    // internal bus ports\n    // write address\n    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,\n    input  wire [USER_AW-1:0]           I_AWADDR,\n    input  wire [31:0]                  I_AWLEN,\n    input  wire [2:0]                   I_AWSIZE,\n    input  wire [1:0]                   I_AWBURST,\n    input  wire [1:0]                   I_AWLOCK,\n    input  wire [3:0]                   I_AWCACHE,\n    input  wire [2:0]                   I_AWPROT,\n    input  wire [3:0]                   I_AWQOS,\n    input  wire [3:0]                   I_AWREGION,\n    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,\n    input  wire                         I_AWVALID,\n    output wire                         I_AWREADY,\n    // write data\n    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,\n    input  wire [USER_DW-1:0]           I_WDATA,\n    input  wire                         I_WLAST,\n    input  wire [USER_DW/8-1:0]         I_WSTRB,\n    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,\n    input  wire                         I_WVALID,\n    output wire                         I_WREADY,\n    // write response\n    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,\n    output wire [1:0]                   I_BRESP,\n    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,\n    output wire                         I_BVALID,\n    input  wire                         I_BREADY,\n    // read address\n    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,\n    input  wire [USER_AW-1:0]           I_ARADDR,\n    input  wire [31:0]                  I_ARLEN,\n    input  wire [2:0]                   I_ARSIZE,\n    input  wire [1:0]                   I_ARBURST,\n    input  wire [1:0]                   I_ARLOCK,\n    input  wire [3:0]                   I_ARCACHE,\n    input  wire [2:0]                   I_ARPROT,\n    input  wire [3:0]                   I_ARQOS,\n    input  wire [3:0]                   I_ARREGION,\n    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,\n    input  wire                         I_ARVALID,\n    output wire                         I_ARREADY,\n    // read data\n    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,\n    output wire [USER_DW-1:0]           I_RDATA,\n    output wire [1:0]                   I_RRESP,\n    output wire                         I_RLAST,\n    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,\n    output wire                         I_RVALID,\n    input  wire                         I_RREADY\n);\n//------------------------Parameter----------------------\n\n//------------------------Local signal-------------------\n\n// Write Address channel throttling unit\nwire  [7:0]         AWLEN_Dummy;\nwire                AWVALID_Dummy;\nwire                AWREADY_Dummy;\nwire                WVALID_Dummy;\n\nassign AWLEN     = AWLEN_Dummy;\nassign WVALID    = WVALID_Dummy;\ndds_DDS_OUTPUT_m_axi_throttl #(\n    .USED_FIX(0)\n) wreq_throttl (\n    .clk(ACLK),\n    .reset(ARESET),\n    .ce(ACLK_EN),\n    .in_len(AWLEN_Dummy),\n    .in_req_valid(AWVALID_Dummy),\n    .out_req_valid(AWVALID),\n    .in_req_ready(AWREADY),\n    .out_req_ready(AWREADY_Dummy),\n    .in_data_valid(WVALID_Dummy),\n    .in_data_ready(WREADY)\n);\n// END of write Address channel throttling unit\n\nassign I_BID = 1'b0;\nassign I_BUSER = C_USER_VALUE;\nassign I_RID = 1'b0;\nassign I_RLAST = 1'b0;\nassign I_RUSER = C_USER_VALUE;\n//------------------------Instantiation------------------\n\n// dds_DDS_OUTPUT_m_axi_write\ndds_DDS_OUTPUT_m_axi_write #(\n    .NUM_WRITE_OUTSTANDING    ( NUM_WRITE_OUTSTANDING ),\n    .MAX_WRITE_BURST_LENGTH   ( MAX_WRITE_BURST_LENGTH ),\n    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),\n    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),\n    .C_TARGET_ADDR     ( C_TARGET_ADDR ),\n    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),\n    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),\n    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),\n    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),\n    .C_USER_VALUE      ( C_USER_VALUE ),\n    .C_PROT_VALUE      ( C_PROT_VALUE ),\n    .C_CACHE_VALUE     ( C_CACHE_VALUE ),\n    .USER_DW           ( USER_DW ),\n    .USER_AW           ( USER_AW ),\n    .USER_MAXREQS      ( USER_MAXREQS )\n) bus_write (\n    .ACLK              ( ACLK ),\n    .ARESET            ( ARESET ),\n    .ACLK_EN           ( ACLK_EN ),\n    .AWID              ( AWID ),\n    .AWADDR            ( AWADDR ),\n    .AWLEN             ( AWLEN_Dummy ),\n    .AWSIZE            ( AWSIZE ),\n    .AWBURST           ( AWBURST ),\n    .AWLOCK            ( AWLOCK ),\n    .AWCACHE           ( AWCACHE ),\n    .AWPROT            ( AWPROT ),\n    .AWQOS             ( AWQOS ),\n    .AWREGION          ( AWREGION ),\n    .AWUSER            ( AWUSER ),\n    .AWVALID           ( AWVALID_Dummy ),\n    .AWREADY           ( AWREADY_Dummy ),\n    .WID               ( WID ),\n    .WDATA             ( WDATA ),\n    .WSTRB             ( WSTRB ),\n    .WLAST             ( WLAST ),\n    .WUSER             ( WUSER ),\n    .WVALID            ( WVALID_Dummy ),\n    .WREADY            ( WREADY ),\n    .BID               ( BID ),\n    .BRESP             ( BRESP ),\n    .BUSER             ( BUSER ),\n    .BVALID            ( BVALID ),\n    .BREADY            ( BREADY ),\n    .wreq_valid        ( I_AWVALID ),\n    .wreq_ack          ( I_AWREADY ),\n    .wreq_addr         ( I_AWADDR ),\n    .wreq_length       ( I_AWLEN ),\n    .wreq_cache        ( I_AWCACHE ),\n    .wreq_prot         ( I_AWPROT ),\n    .wreq_qos          ( I_AWQOS ),\n    .wreq_user         ( I_AWUSER ),\n    .wdata_valid       ( I_WVALID ),\n    .wdata_ack         ( I_WREADY ),\n    .wdata_strb        ( I_WSTRB ),\n    .wdata_user        ( I_WUSER ),\n    .wdata_data        ( I_WDATA ),\n    .wrsp_valid        ( I_BVALID ),\n    .wrsp_ack          ( I_BREADY ),\n    .wrsp              ( I_BRESP )\n);\n\n// dds_DDS_OUTPUT_m_axi_read\ndds_DDS_OUTPUT_m_axi_read #(\n    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),\n    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),\n    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),\n    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),\n    .C_TARGET_ADDR     ( C_TARGET_ADDR ),\n    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),\n    .C_M_AXI_ARUSER_WIDTH    ( C_M_AXI_ARUSER_WIDTH ),\n    .C_M_AXI_RUSER_WIDTH     ( C_M_AXI_RUSER_WIDTH ),\n    .C_USER_VALUE      ( C_USER_VALUE ),\n    .C_PROT_VALUE      ( C_PROT_VALUE ),\n    .C_CACHE_VALUE     ( C_CACHE_VALUE ),\n    .USER_DW           ( USER_DW ),\n    .USER_AW           ( USER_AW ),\n    .USER_MAXREQS      ( USER_MAXREQS )\n) bus_read (\n    .ACLK              ( ACLK ),\n    .ARESET            ( ARESET ),\n    .ACLK_EN           ( ACLK_EN ),\n    .ARID              ( ARID ),\n    .ARADDR            ( ARADDR ),\n    .ARLEN             ( ARLEN ),\n    .ARSIZE            ( ARSIZE ),\n    .ARBURST           ( ARBURST ),\n    .ARLOCK            ( ARLOCK ),\n    .ARCACHE           ( ARCACHE ),\n    .ARPROT            ( ARPROT ),\n    .ARQOS             ( ARQOS ),\n    .ARREGION          ( ARREGION ),\n    .ARUSER            ( ARUSER ),\n    .ARVALID           ( ARVALID ),\n    .ARREADY           ( ARREADY ),\n    .RID               ( RID ),\n    .RDATA             ( RDATA ),\n    .RRESP             ( RRESP ),\n    .RLAST             ( RLAST ),\n    .RUSER             ( RUSER ),\n    .RVALID            ( RVALID ),\n    .RREADY            ( RREADY ),\n    .rreq_valid        ( I_ARVALID ),\n    .rreq_ack          ( I_ARREADY ),\n    .rreq_addr         ( I_ARADDR ),\n    .rreq_length       ( I_ARLEN ),\n    .rreq_cache        ( I_ARCACHE ),\n    .rreq_prot         ( I_ARPROT ),\n    .rreq_qos          ( I_ARQOS ),\n    .rreq_user         ( I_ARUSER ),\n    .rdata_valid       ( I_RVALID ),\n    .rdata_ack         ( I_RREADY ),\n    .rdata_data        ( I_RDATA ),\n    .rrsp              ( I_RRESP )\n);\nendmodule\n\nmodule dds_DDS_OUTPUT_m_axi_reg_slice\n#(parameter\n    N = 8   // data width\n) (\n    // system signals\n    input  wire         sclk,\n    input  wire         reset,\n    // slave side\n    input  wire [N-1:0] s_data,\n    input  wire         s_valid,\n    output wire         s_ready,\n    // master side\n    output wire [N-1:0] m_data,\n    output wire         m_valid,\n    input  wire         m_ready\n);\n//------------------------Parameter----------------------\n// state\nlocalparam [1:0]\n    ZERO = 2'b10,\n    ONE  = 2'b11,\n    TWO  = 2'b01;\n//------------------------Local signal-------------------\nreg  [N-1:0] data_p1;\nreg  [N-1:0] data_p2;\nwire         load_p1;\nwire         load_p2;\nwire         load_p1_from_p2;\nreg          s_ready_t;\nreg  [1:0]   state;\nreg  [1:0]   next;\n//------------------------Body---------------------------\nassign s_ready = s_ready_t;\nassign m_data  = data_p1;\nassign m_valid = state[0];\n\nassign load_p1 = (state == ZERO && s_valid) ||\n                 (state == ONE && s_valid && m_ready) ||\n                 (state == TWO && m_ready);\nassign load_p2 = s_valid & s_ready;\nassign load_p1_from_p2 = (state == TWO);\n\n// data_p1\nalways @(posedge sclk) begin\n    if (load_p1) begin\n        if (load_p1_from_p2)\n            data_p1 <= data_p2;\n        else\n            data_p1 <= s_data;\n    end\nend\n\n// data_p2\nalways @(posedge sclk) begin\n    if (load_p2) data_p2 <= s_data;\nend\n\n// s_ready_t\nalways @(posedge sclk) begin\n    if (reset)\n        s_ready_t <= 1'b0;\n    else if (state == ZERO)\n        s_ready_t <= 1'b1;\n    else if (state == ONE && next == TWO)\n        s_ready_t <= 1'b0;\n    else if (state == TWO && next == ONE)\n        s_ready_t <= 1'b1;\nend\n\n// state\nalways @(posedge sclk) begin\n    if (reset)\n        state <= ZERO;\n    else\n        state <= next;\nend\n\n// next\nalways @(*) begin\n    case (state)\n        ZERO:\n            if (s_valid & s_ready)\n                next = ONE;\n            else\n                next = ZERO;\n        ONE:\n            if (~s_valid & m_ready)\n                next = ZERO;\n            else if (s_valid & ~m_ready)\n                next = TWO;\n            else\n                next = ONE;\n        TWO:\n            if (m_ready)\n                next = ONE;\n            else\n                next = TWO;\n        default:\n            next = ZERO;\n    endcase\nend\n\nendmodule\n\nmodule dds_DDS_OUTPUT_m_axi_fifo\n#(parameter\n    DATA_BITS  = 8,\n    DEPTH      = 16,\n    DEPTH_BITS = 4\n)(\n    input  wire                 sclk,\n    input  wire                 reset,\n    input  wire                 sclk_en,\n    output reg                  empty_n,\n    output reg                  full_n,\n    input  wire                 rdreq,\n    input  wire                 wrreq,\n    output reg  [DATA_BITS-1:0] q,\n    input  wire [DATA_BITS-1:0] data\n);\n//------------------------Parameter----------------------\n\n//------------------------Local signal-------------------\nwire                  push;\nwire                  pop;\nwire                  full_cond;\nreg                   data_vld;\nreg  [DEPTH_BITS-1:0] pout;\nreg  [DATA_BITS-1:0]  mem[0:DEPTH-1];\n//------------------------Body---------------------------\nassign push = full_n & wrreq;\nassign pop  = data_vld & (~(empty_n & ~rdreq));\nif (DEPTH >= 2) begin\nassign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;\nend else begin\nassign full_cond = push && ~pop;\nend\n\n// q\nalways @(posedge sclk)\nbegin\n    if (reset)\n        q <= 0;\n    else if (sclk_en) begin\n        if (~(empty_n & ~rdreq))\n            q <= mem[pout];\n    end\nend\n\n// empty_n\nalways @(posedge sclk)\nbegin\n    if (reset)\n        empty_n <= 1'b0;\n    else if (sclk_en) begin\n        if (~(empty_n & ~rdreq))\n            empty_n <= data_vld;\n    end\nend\n\n// data_vld\nalways @(posedge sclk)\nbegin\n    if (reset)\n        data_vld <= 1'b0;\n    else if (sclk_en) begin\n        if (push)\n            data_vld <= 1'b1;\n        else if (~push && pop && pout == 1'b0)\n            data_vld <= 1'b0;\n    end\nend\n\n// full_n\nalways @(posedge sclk)\nbegin\n    if (reset)\n        full_n <= 1'b1;\n    else if (sclk_en) begin\n        if (pop)\n            full_n <= 1'b1;\n        else if (full_cond)\n            full_n <= 1'b0;\n    end\nend\n\n// pout\nalways @(posedge sclk)\nbegin\n    if (reset)\n        pout <= 1'b0;\n    else if (sclk_en) begin\n        if (push & ~pop & data_vld)\n            pout <= pout + 1'b1;\n        else if (~push && pop && pout != 1'b0)\n            pout <= pout - 1'b1;\n    end\nend\n\ninteger i;\nalways @(posedge sclk)\nbegin\n    if (sclk_en) begin\n        if (push) begin\n            for (i = 0; i < DEPTH - 1; i = i + 1) begin\n                mem[i+1] <= mem[i];\n            end\n            mem[0] <= data;\n        end\n    end\nend\nendmodule\n\nmodule dds_DDS_OUTPUT_m_axi_buffer\n#(parameter\n    MEM_STYLE  = \"block\",\n    DATA_WIDTH = 32,\n    ADDR_WIDTH = 5,\n    DEPTH      = 32\n) (\n    // system signal\n    input  wire                  clk,\n    input  wire                  reset,\n    input  wire                  sclk_en,\n\n    // write\n    output wire                  if_full_n,\n    input  wire                  if_write_ce,\n    input  wire                  if_write,\n    input  wire [DATA_WIDTH-1:0] if_din,\n\n    // read\n    output wire                  if_empty_n,\n    input  wire                  if_read_ce,\n    input  wire                  if_read,\n    output wire [DATA_WIDTH-1:0] if_dout\n);\n//------------------------Parameter----------------------\n\n//------------------------Local signal-------------------\n(* ram_style = MEM_STYLE *)\nreg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];\nreg  [DATA_WIDTH-1:0] q_buf = 1'b0;\nreg  [ADDR_WIDTH-1:0] waddr = 1'b0;\nreg  [ADDR_WIDTH-1:0] raddr = 1'b0;\nwire [ADDR_WIDTH-1:0] wnext;\nwire [ADDR_WIDTH-1:0] rnext;\nwire                  push;\nwire                  pop;\nreg  [ADDR_WIDTH-1:0] usedw = 1'b0;\nreg                   full_n = 1'b1;\nreg                   empty_n = 1'b0;\nreg  [DATA_WIDTH-1:0] q_tmp = 1'b0;\nreg                   show_ahead = 1'b0;\nreg  [DATA_WIDTH-1:0] dout_buf = 1'b0;\nreg                   dout_valid = 1'b0;\n\n\n//------------------------Instantiation------------------\n\n//------------------------Task and function--------------\n\n//------------------------Body---------------------------\nassign if_full_n  = full_n;\nassign if_empty_n = dout_valid;\nassign if_dout    = dout_buf;\nassign push       = full_n & if_write_ce & if_write;\nassign pop        = empty_n & if_read_ce & (~dout_valid | if_read);\nassign wnext      = !push                ? waddr :\n                    (waddr == DEPTH - 1) ? 1'b0  :\n                    waddr + 1'b1;\nassign rnext      = !pop                 ? raddr :\n                    (raddr == DEPTH - 1) ? 1'b0  :\n                    raddr + 1'b1;\n\n// waddr\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        waddr <= 1'b0;\n    else if (sclk_en)\n        waddr <= wnext;\nend\n\n// raddr\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        raddr <= 1'b0;\n    else if (sclk_en)\n        raddr <= rnext;\nend\n\n// usedw\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        usedw <= 1'b0;\n    else if (sclk_en)\n        if (push & ~pop)\n            usedw <= usedw + 1'b1;\n        else if (~push & pop)\n            usedw <= usedw - 1'b1;\nend\n\n// full_n\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        full_n <= 1'b1;\n    else if (sclk_en)\n        if (push & ~pop)\n            full_n <= (usedw != DEPTH - 1);\n        else if (~push & pop)\n            full_n <= 1'b1;\nend\n\n// empty_n\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        empty_n <= 1'b0;\n    else if (sclk_en)\n        if (push & ~pop)\n            empty_n <= 1'b1;\n        else if (~push & pop)\n            empty_n <= (usedw != 1'b1);\nend\n\n// mem\nalways @(posedge clk) begin\n    if (push)\n        mem[waddr] <= if_din;\nend\n\n// q_buf\nalways @(posedge clk) begin\n    q_buf <= mem[rnext];\nend\n\n// q_tmp\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        q_tmp <= 1'b0;\n    else if (sclk_en)\n        if (push)\n            q_tmp <= if_din;\nend\n\n// show_ahead\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        show_ahead <= 1'b0;\n    else if (sclk_en)\n        if (push && usedw == pop)\n            show_ahead <= 1'b1;\n        else\n            show_ahead <= 1'b0;\nend\n\n// dout_buf\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        dout_buf <= 1'b0;\n    else if (sclk_en)\n        if (pop)\n            dout_buf <= show_ahead? q_tmp : q_buf;\nend\n\n// dout_valid\nalways @(posedge clk) begin\n    if (reset == 1'b1)\n        dout_valid <= 1'b0;\n    else if (sclk_en)\n        if (pop)\n            dout_valid <= 1'b1;\n        else if (if_read_ce & if_read)\n            dout_valid <= 1'b0;\nend\n\nendmodule\n`timescale 1ns/1ps\n\nmodule dds_DDS_OUTPUT_m_axi_decoder\n#(parameter\n    DIN_WIDTH       = 3\n)(\n    input  wire [DIN_WIDTH-1:0]         din,\n    output reg  [2**DIN_WIDTH-1:0]      dout\n);\n    integer i;\n    always @(din) begin\n        dout = {2**DIN_WIDTH{1'b0}};\n        for (i=0; i < din; i = i + 1)\n            dout[i] = 1'b1;\n    end\nendmodule\n\n\nmodule dds_DDS_OUTPUT_m_axi_throttl\n#(parameter\n    USED_FIX       = 0,\n    FIX_VALUE      = 4\n)(\n    input               clk,\n    input               reset,\n    input               ce,\n    input   [7:0]       in_len,\n    input               in_req_valid,\n    input               in_req_ready,\n    input               in_data_valid,\n    input               in_data_ready,\n    output              out_req_valid,\n    output              out_req_ready\n);\n\nlocalparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;\n\nwire                req_en;\nwire                handshake;\nwire  [7:0]         load_init;\nreg   [7:0]         throttl_cnt;\n\nif (USED_FIX) begin\n    assign load_init = FIX_VALUE-1;\n    assign handshake = 1'b1;\nend else begin\n    assign load_init = in_len;\n    assign handshake = in_data_valid & in_data_ready;\nend\n\nassign out_req_valid = in_req_valid & req_en;\nassign out_req_ready = in_req_ready & req_en;\nassign req_en = (throttl_cnt == 0);\n\nalways @(posedge clk)\nbegin\n    if (reset)\n        throttl_cnt <= 0;\n    else if (ce) begin\n        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)\n            throttl_cnt <= load_init; //load\n        else if (throttl_cnt > 0 && handshake)\n            throttl_cnt <= throttl_cnt - 1'b1;\n    end\nend\n\nendmodule\n\n`timescale 1ns/1ps\n\nmodule dds_DDS_OUTPUT_m_axi_read\n#(parameter\n    NUM_READ_OUTSTANDING      = 2,\n    MAX_READ_BURST_LENGTH     = 16,\n    C_M_AXI_ID_WIDTH          = 1,\n    C_M_AXI_ADDR_WIDTH        = 32,\n    C_TARGET_ADDR             = 32'h00000000,\n    C_M_AXI_DATA_WIDTH        = 32,\n    C_M_AXI_ARUSER_WIDTH      = 1,\n    C_M_AXI_RUSER_WIDTH       = 1,\n    C_USER_VALUE              = 1'b0,\n    C_PROT_VALUE              = 3'b000,\n    C_CACHE_VALUE             = 4'b0011,\n    USER_DW                   = 16,\n    USER_AW                   = 32,\n    USER_MAXREQS              = 16\n)(\n    // system signal\n    input  wire                         ACLK,\n    input  wire                         ARESET,\n    input  wire                         ACLK_EN,\n    // read address channel\n    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,\n    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,\n    output wire [7:0]                   ARLEN,\n    output wire [2:0]                   ARSIZE,\n    output wire [1:0]                   ARBURST,\n    output wire [1:0]                   ARLOCK,\n    output wire [3:0]                   ARCACHE,\n    output wire [2:0]                   ARPROT,\n    output wire [3:0]                   ARQOS,\n    output wire [3:0]                   ARREGION,\n    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,\n    output wire                         ARVALID,\n    input  wire                         ARREADY,\n    // read data channel\n    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,\n    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,\n    input  wire [1:0]                   RRESP,\n    input  wire                         RLAST,\n    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,\n    input  wire                         RVALID,\n    output wire                         RREADY,\n    // read\n    input  wire                         rreq_valid,\n    output wire                         rreq_ack,\n    input  wire [USER_AW-1:0]           rreq_addr,\n    input  wire [31:0]                  rreq_length,\n    input  wire [3:0]                   rreq_cache,\n    input  wire [2:0]                   rreq_prot,\n    input  wire [3:0]                   rreq_qos,\n    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,\n    output wire [USER_DW-1:0]           rdata_data,\n    output wire [1:0]                   rrsp,\n    output wire                         rdata_valid,\n    input  wire                         rdata_ack\n);\n\n//------------------------Parameter----------------------\nlocalparam\n    USER_DATA_WIDTH = calc_data_width(USER_DW),\n    USER_DATA_BYTES = USER_DATA_WIDTH / 8,\n    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),\n    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,\n    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,\n    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),\n    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),\n    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),\n    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};\n\n//------------------------Task and function--------------\nfunction integer calc_data_width;\n    input integer x;\n    integer y;\nbegin\n    y = 8;\n    while (y < x) y = y * 2;\n    calc_data_width = y;\nend\nendfunction\n\nfunction integer log2;\n    input integer x;\n    integer n, m;\nbegin\n    n = 0;\n    m = 1;\n    while (m < x) begin\n        n = n + 1;\n        m = m * 2;\n    end\n    log2 = n;\nend\nendfunction\n\n//------------------------Local signal-------------------\n    // AR channel\n    wire [USER_AW + 31:0]                   rreq_data;\n    wire [USER_AW + 31:0]                   fifo_rreq_data;\n    wire [USER_AW - 1:0]                    tmp_addr;\n    wire [31:0]                             tmp_len;\n    reg  [31:0]                             align_len;\n    wire [7:0]                              arlen_tmp;\n    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;\n    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;\n    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;\n    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;\n    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;\n    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;\n    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;\n    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;\n    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;\n    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;\n    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;\n    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;\n    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;\n    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;\n    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;\n    wire [1:0]                              ar2r_ardata;\n    wire                                    fifo_rctl_r;\n    wire                                    zero_len_event;\n    wire                                    negative_len_event;\n    reg                                     invalid_len_event;\n    wire                                    fifo_rreq_valid;\n    reg                                     fifo_rreq_valid_buf;\n    wire                                    fifo_rreq_read;\n    wire                                    fifo_burst_w;\n    wire                                    fifo_resp_w;\n    reg                                     ARVALID_Dummy;\n    wire                                    ready_for_sect;\n    wire                                    next_rreq;\n    wire                                    ready_for_rreq;\n    reg                                     rreq_handling;\n    wire                                    first_sect;\n    wire                                    last_sect;\n    wire                                    next_sect;\n    // R channel\n    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;\n    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;\n    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;\n    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;\n    wire    [USER_DW + 1:0]                 rdata_data_pack;\n    reg     [7:0]                           len_cnt;\n    wire    [1:0]                           ar2r_rdata;\n    wire    [1:0]                           tmp_resp;\n    reg     [1:0]                           resp_buf;\n    wire                                    tmp_last;\n    wire                                    need_rlast;\n    wire                                    fifo_rctl_ready;\n    wire                                    beat_valid;\n    wire                                    next_beat;\n    wire                                    burst_valid;\n    wire                                    fifo_burst_ready;\n    wire                                    next_burst;\n    wire                                    rdata_ack_t;\n    reg                                     rdata_valid_t;\n\n//------------------------AR channel begin---------------\n//------------------------Instantiation------------------\n    dds_DDS_OUTPUT_m_axi_fifo #(\n        .DATA_BITS(USER_AW + 32),\n        .DEPTH(USER_MAXREQS),\n        .DEPTH_BITS(log2(USER_MAXREQS))\n    ) fifo_rreq (\n        .sclk(ACLK),\n        .reset(ARESET),\n        .sclk_en(ACLK_EN),\n        .empty_n(fifo_rreq_valid),\n        .full_n(rreq_ack),\n        .rdreq(fifo_rreq_read),\n        .wrreq(rreq_valid),\n        .q(fifo_rreq_data),\n        .data(rreq_data));\n\n//------------------------Body---------------------------\n    assign rreq_data   = {rreq_length, rreq_addr};\n    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];\n    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];\n    assign end_addr    = start_addr + align_len;\n\n    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;\n    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            align_len   <= 0;\n        else if (ACLK_EN) begin\n            if(fifo_rreq_valid && ready_for_rreq)\n                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            start_addr <= 0;\n        else if (ACLK_EN) begin\n            if(fifo_rreq_valid && ready_for_rreq)\n                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            fifo_rreq_valid_buf <= 1'b0;\n        else if (ACLK_EN) begin\n            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)\n                fifo_rreq_valid_buf <= fifo_rreq_valid;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            invalid_len_event <= 1'b0;\n        else if (ACLK_EN) begin\n            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)\n                invalid_len_event <= zero_len_event || negative_len_event;\n        end\n    end\n\n    assign next_rreq      = !invalid_len_event && (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;\n    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));\n    assign fifo_rreq_read = invalid_len_event || next_rreq;\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            rreq_handling <= 1'b0;\n        else if (ACLK_EN) begin\n            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)\n                rreq_handling <= 1'b1;\n            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)\n                rreq_handling <= 1'b0;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            start_addr_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_rreq)\n                start_addr_buf <= start_addr;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            end_addr_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_rreq)\n                end_addr_buf <= end_addr;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            beat_len_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_rreq)\n                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            sect_cnt <= 0;\n        else if (ACLK_EN) begin\n            if (next_rreq)\n                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];\n            else if (next_sect)\n                sect_cnt <= sect_cnt + 1;\n        end\n    end\n\n    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);\n    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);\n    assign next_sect  = rreq_handling && ready_for_sect;\n\n    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            sect_addr_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_sect)\n                sect_addr_buf <= sect_addr;\n        end\n    end\n\n    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];\n    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :\n                         ( first_sect && ~last_sect)? start_to_4k:\n                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :\n                                                      BOUNDARY_BEATS;\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            sect_len_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_sect)\n                sect_len_buf <= sect_len;\n        end\n    end\n\n    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            sect_end_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_sect)\n                sect_end_buf <= sect_end;\n        end\n    end\n\n    assign ARID    = 0;\n    assign ARSIZE  = BUS_ADDR_ALIGN;\n    assign ARBURST = 2'b01;\n    assign ARLOCK  = 2'b00;\n    assign ARCACHE = C_CACHE_VALUE;\n    assign ARPROT  = C_PROT_VALUE;\n    assign ARUSER  = C_USER_VALUE;\n    assign ARQOS   = rreq_qos;\n\n    generate\n    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst\n        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};\n        assign ARLEN   = sect_len_buf;\n        assign ARVALID = ARVALID_Dummy;\n\n        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                ARVALID_Dummy <= 1'b0;\n            else if (ACLK_EN) begin\n                if (next_sect)\n                    ARVALID_Dummy <= 1'b1;\n                else if (~next_sect && ARREADY)\n                    ARVALID_Dummy <= 1'b0;\n            end\n        end\n\n        assign fifo_rctl_r  = next_sect;\n        assign ar2r_ardata  = {last_sect, 1'b0};\n\n        assign fifo_burst_w = next_sect;\n        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];\n        assign arlen_tmp    = sect_len;\n        assign burst_end    = sect_end;\n    end\n    else begin : could_multi_bursts\n        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;\n        reg  [7:0]                                      arlen_buf;\n        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;\n        reg                                             sect_handling;\n        wire                                            last_loop;\n        wire                                            next_loop;\n        wire                                            ready_for_loop;\n\n        assign ARADDR  = araddr_buf;\n        assign ARLEN   = arlen_buf;\n        assign ARVALID = ARVALID_Dummy;\n\n        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);\n        assign next_loop      = sect_handling && ready_for_loop;\n        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;\n        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                sect_handling <= 1'b0;\n            else if (ACLK_EN) begin\n                if (rreq_handling && ~sect_handling)\n                    sect_handling <= 1'b1;\n                else if (~rreq_handling && last_loop && next_loop)\n                    sect_handling <= 1'b0;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                loop_cnt <= 0;\n            else if (ACLK_EN) begin\n                if (next_sect)\n                    loop_cnt <= 0;\n                else if (next_loop)\n                    loop_cnt <= loop_cnt + 1;\n            end\n        end\n\n        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                araddr_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_loop)\n                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};\n            end\n        end\n\n        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                arlen_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_loop)\n                    arlen_buf <= arlen_tmp;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                ARVALID_Dummy <= 1'b0;\n            else if (ACLK_EN) begin\n                if (next_loop)\n                    ARVALID_Dummy <= 1'b1;\n                else if (~next_loop && ARREADY)\n                    ARVALID_Dummy <= 1'b0;\n            end\n        end\n\n        assign fifo_rctl_r = next_loop;\n        assign ar2r_ardata = {last_loop, 1'b0};\n\n        assign fifo_burst_w = next_loop;\n        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};\n    end\n    endgenerate\n//------------------------AR channel end-----------------\n\n//------------------------R channel begin----------------\n//------------------------Instantiation------------------\n    dds_DDS_OUTPUT_m_axi_buffer #(\n        .DATA_WIDTH(BUS_DATA_WIDTH + 3),\n        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),\n        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))\n    ) buff_rdata (\n        .clk(ACLK),\n        .reset(ARESET),\n        .sclk_en(ACLK_EN),\n        .if_full_n(RREADY),\n        .if_write_ce(1'b1),\n        .if_write(RVALID),\n        .if_din(fifo_rresp_rdata),\n        .if_empty_n(beat_valid),\n        .if_read_ce(1'b1),\n        .if_read(next_beat),\n        .if_dout(data_pack));\n\n    dds_DDS_OUTPUT_m_axi_reg_slice #(\n        .N(USER_DW + 2)\n    ) rs_rdata (\n        .sclk(ACLK),\n        .reset(ARESET),\n        .s_data(rs_rrsp_rdata),\n        .s_valid(rdata_valid_t),\n        .s_ready(rdata_ack_t),\n        .m_data(rdata_data_pack),\n        .m_valid(rdata_valid),\n        .m_ready(rdata_ack));\n\n    dds_DDS_OUTPUT_m_axi_fifo #(\n        .DATA_BITS(2),\n        .DEPTH(NUM_READ_OUTSTANDING-1),\n        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))\n    ) fifo_rctl (\n        .sclk(ACLK),\n        .reset(ARESET),\n        .sclk_en(ACLK_EN),\n        .empty_n(need_rlast),\n        .full_n(fifo_rctl_ready),\n        .rdreq(tmp_last),\n        .wrreq(fifo_rctl_r),\n        .q(ar2r_rdata),\n        .data(ar2r_ardata));\n\n    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};\n    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];\n    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];\n    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;\n\n    generate\n    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen\n        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;\n        wire                                ready_for_data;\n\n        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};\n        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];\n        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];\n\n        assign fifo_burst_ready = 1'b1;\n        assign next_beat        = beat_valid && ready_for_data;\n        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                data_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_beat)\n                    data_buf <= tmp_data;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                resp_buf <= 2'b00;\n            else if (ACLK_EN) begin\n                if (next_beat)\n                    resp_buf <= tmp_resp;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                rdata_valid_t <= 1'b0;\n            else if (ACLK_EN) begin\n                if (next_beat)\n                    rdata_valid_t <= 1'b1;\n                else if (ready_for_data)\n                    rdata_valid_t <= 1'b0;\n            end\n        end\n    end\n    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen\n        localparam\n        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,\n            SPLIT_ALIGN     = log2(TOTAL_SPLIT);\n\n        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;\n        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;\n        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;\n        wire [SPLIT_ALIGN - 1:0]        split_cnt;\n        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;\n        wire [SPLIT_ALIGN - 1:0]        head_split;\n        wire [SPLIT_ALIGN - 1:0]        tail_split;\n        wire [7:0]                      arlen_tmp_t;\n        wire [7:0]                      burst_len;\n        wire                            first_beat;\n        wire                            last_beat;\n        wire                            first_split;\n        wire                            next_split;\n        wire                            last_split;\n        wire                            ready_for_data;\n\n        dds_DDS_OUTPUT_m_axi_fifo #(\n            .DATA_BITS(2*SPLIT_ALIGN + 8),\n            .DEPTH(USER_MAXREQS),\n            .DEPTH_BITS(log2(USER_MAXREQS))\n        ) fifo_burst (\n            .sclk(ACLK),\n            .reset(ARESET),\n            .sclk_en(ACLK_EN),\n            .empty_n(burst_valid),\n            .full_n(fifo_burst_ready),\n            .rdreq(next_burst),\n            .wrreq(fifo_burst_w),\n            .q(burst_pack),\n            .data(tmp_burst_info));\n\n        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};\n        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];\n        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];\n\n        assign arlen_tmp_t    = arlen_tmp;\n        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};\n        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];\n        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];\n        assign burst_len      = burst_pack[7:0];\n\n        assign next_beat        = last_split;\n        assign next_burst       = last_beat && last_split;\n        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);\n\n        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;\n        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;\n\n        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);\n        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);\n        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);\n\n        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                split_cnt_buf <= 0;\n            else if (ACLK_EN) begin\n                if (last_split)\n                    split_cnt_buf <= 0;\n                else if (first_split || next_split)\n                    split_cnt_buf <= split_cnt + 1;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                len_cnt <= 0;\n            else if (ACLK_EN) begin\n                if (last_beat && last_split)\n                    len_cnt <= 0;\n                else if (last_split)\n                    len_cnt <= len_cnt + 1;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                data_buf <= 0;\n            else if (ACLK_EN) begin\n                if (first_split && first_beat)\n                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);\n                else if (first_split)\n                    data_buf <= tmp_data;\n                else if (next_split)\n                    data_buf <= data_buf >> USER_DATA_WIDTH;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                resp_buf <= 2'b00;\n            else if (ACLK_EN) begin\n                if (first_split)\n                    resp_buf <= tmp_resp;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                rdata_valid_t <= 0;\n            else if (ACLK_EN) begin\n                if (first_split)\n                    rdata_valid_t <= 1;\n                else if (~(first_split || next_split) && ready_for_data)\n                    rdata_valid_t <= 0;\n            end\n        end\n\n    end\n    else begin: bus_narrow_gen\n        localparam\n            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,\n            PAD_ALIGN       = log2(TOTAL_PADS);\n\n        reg  [USER_DATA_WIDTH - 1:0]        data_buf;\n        wire [TOTAL_PADS - 1:0]             pad_oh;\n        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;\n        wire                                ready_for_data;\n        wire                                next_pad;\n        reg                                 first_pad;\n        wire                                last_pad;\n        wire                                next_data;\n\n        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};\n        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];\n        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];\n\n        assign fifo_burst_ready = 1'b1;\n        assign next_beat        = next_pad;\n        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);\n\n        assign next_pad  = beat_valid && ready_for_data;\n        assign last_pad  = pad_oh[TOTAL_PADS - 1];\n        assign next_data = last_pad && ready_for_data;\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                first_pad <= 1;\n            else if (ACLK_EN) begin\n                if (next_pad && ~last_pad)\n                    first_pad <= 0;\n                else if (next_pad && last_pad)\n                    first_pad <= 1;\n            end\n        end\n\n        assign pad_oh = (beat_valid == 0)?  0 :\n                        (first_pad)?        1 :\n                                            pad_oh_reg;\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                pad_oh_reg <= 0;\n            else if (ACLK_EN) begin\n                if (next_pad)\n                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};\n            end\n        end\n\n        genvar  i;\n        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen\n            always @(posedge ACLK)\n            begin\n                if (ARESET)\n                    data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= 0;\n                else if (ACLK_EN) begin\n                    if (pad_oh[i-1] == 1'b1 && ready_for_data)\n                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;\n                end\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                resp_buf <= 2'b00;\n            else if (ACLK_EN) begin\n                if (next_beat && (resp_buf[0] ==1'b0))\n                    resp_buf <= tmp_resp;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                rdata_valid_t <= 0;\n            else if (ACLK_EN) begin\n                if (next_data)\n                    rdata_valid_t <= 1;\n                else if (ready_for_data)\n                    rdata_valid_t <= 0;\n            end\n        end\n    end\n    endgenerate\n\n//------------------------Body---------------------------\n//------------------------R channel end------------------\nendmodule\n\nmodule dds_DDS_OUTPUT_m_axi_write\n#(parameter\n    NUM_WRITE_OUTSTANDING     = 2,\n    MAX_WRITE_BURST_LENGTH    = 16,\n    C_M_AXI_ID_WIDTH          = 1,\n    C_M_AXI_ADDR_WIDTH        = 32,\n    C_TARGET_ADDR             = 32'h00000000,\n    C_M_AXI_DATA_WIDTH        = 32,\n    C_M_AXI_AWUSER_WIDTH      = 1,\n    C_M_AXI_WUSER_WIDTH       = 1,\n    C_M_AXI_BUSER_WIDTH       = 1,\n    C_USER_VALUE              = 1'b0,\n    C_PROT_VALUE              = 3'b000,\n    C_CACHE_VALUE             = 4'b0011,\n    USER_DW                   = 16,\n    USER_AW                   = 32,\n    USER_MAXREQS              = 16\n)(\n    // system signal\n    input  wire                         ACLK,\n    input  wire                         ARESET,\n    input  wire                         ACLK_EN,\n    // write address channel\n    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,\n    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,\n    output wire [7:0]                   AWLEN,\n    output wire [2:0]                   AWSIZE,\n    output wire [1:0]                   AWBURST,\n    output wire [1:0]                   AWLOCK,\n    output wire [3:0]                   AWCACHE,\n    output wire [2:0]                   AWPROT,\n    output wire [3:0]                   AWQOS,\n    output wire [3:0]                   AWREGION,\n    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,\n    output wire                         AWVALID,\n    input  wire                         AWREADY,\n    // write data channel\n    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,\n    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,\n    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,\n    output wire                         WLAST,\n    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,\n    output wire                         WVALID,\n    input  wire                         WREADY,\n    // write response channel\n    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,\n    input  wire [1:0]                   BRESP,\n    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,\n    input  wire                         BVALID,\n    output wire                         BREADY,\n    // write request\n    input  wire                         wreq_valid,\n    output wire                         wreq_ack,\n    input  wire [USER_AW-1:0]           wreq_addr,\n    input  wire [31:0]                  wreq_length,\n    input  wire [3:0]                   wreq_cache,\n    input  wire [2:0]                   wreq_prot,\n    input  wire [3:0]                   wreq_qos,\n    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,\n    input  wire                         wdata_valid,\n    output wire                         wdata_ack,\n    input  wire [USER_DW/8-1:0]         wdata_strb,\n    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,\n    input  wire [USER_DW-1:0]           wdata_data,\n    output wire                         wrsp_valid,\n    input  wire                         wrsp_ack,\n    output wire [1:0]                   wrsp\n);\n\n//------------------------Parameter----------------------\nlocalparam\n    USER_DATA_WIDTH = calc_data_width(USER_DW),\n    USER_DATA_BYTES = USER_DATA_WIDTH / 8,\n    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),\n    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,\n    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,\n    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),\n    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),\n    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),\n    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};\n\n//------------------------Task and function--------------\nfunction integer calc_data_width;\n    input integer x;\n    integer y;\nbegin\n    y = 8;\n    while (y < x) y = y * 2;\n    calc_data_width = y;\nend\nendfunction\n\nfunction integer log2;\n    input integer x;\n    integer n, m;\nbegin\n    n = 0;\n    m = 1;\n    while (m < x) begin\n        n = n + 1;\n        m = m * 2;\n    end\n    log2 = n;\nend\nendfunction\n\n//------------------------Local signal-------------------\n    // AW channel\n    wire [USER_AW + 31:0]                   wreq_data;\n    wire [USER_AW + 31:0]                   fifo_wreq_data;\n    wire [USER_AW - 1:0]                    tmp_addr;\n    wire [31:0]                             tmp_len;\n    reg  [31:0]                             align_len;\n    wire [7:0]                              awlen_tmp;\n    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;\n    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;\n    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;\n    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;\n    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;\n    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;\n    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;\n    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;\n    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;\n    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;\n    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;\n    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;\n    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;\n    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;\n    wire [1:0]                              aw2b_awdata;\n    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;\n    wire                                    zero_len_event;\n    wire                                    negative_len_event;\n    reg                                     invalid_len_event;\n    reg                                     invalid_len_event_reg1;\n    reg                                     invalid_len_event_reg2;\n    wire                                    fifo_wreq_valid;\n    reg                                     fifo_wreq_valid_buf;\n    wire                                    fifo_wreq_read;\n    wire                                    fifo_burst_w;\n    wire                                    fifo_resp_w;\n    reg                                     AWVALID_Dummy;\n    reg                                     last_sect_buf;\n    wire                                    ready_for_sect;\n    wire                                    next_wreq;\n    wire                                    ready_for_wreq;\n    reg                                     wreq_handling;\n    wire                                    first_sect;\n    wire                                    last_sect;\n    wire                                    next_sect;\n    // W channel\n    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;\n    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;\n    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;\n    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;\n    reg     [7:0]                           len_cnt;\n    wire    [7:0]                           burst_len;\n    wire                                    beat_valid;\n    wire                                    next_data;\n    wire                                    burst_valid;\n    wire                                    fifo_burst_ready;\n    wire                                    next_burst;\n    reg                                     WVALID_Dummy;\n    reg                                     WLAST_Dummy;\n    //B channel\n    wire    [1:0]                           aw2b_bdata;\n    reg     [1:0]                           bresp_tmp;\n    reg                                     next_resp;\n    wire                                    last_resp;\n    wire                                    invalid_event;\n    wire                                    fifo_resp_ready;\n    wire                                    need_wrsp;\n    wire                                    resp_match;\n    wire                                    resp_ready;\n\n//------------------------AW channel begin---------------\n//------------------------Instantiation------------------\n    dds_DDS_OUTPUT_m_axi_fifo #(\n        .DATA_BITS(USER_AW + 32),\n        .DEPTH(USER_MAXREQS),\n        .DEPTH_BITS(log2(USER_MAXREQS))\n    ) fifo_wreq (\n        .sclk(ACLK),\n        .reset(ARESET),\n        .sclk_en(ACLK_EN),\n        .empty_n(fifo_wreq_valid),\n        .full_n(wreq_ack),\n        .rdreq(fifo_wreq_read),\n        .wrreq(wreq_valid),\n        .q(fifo_wreq_data),\n        .data(wreq_data));\n\n//------------------------Body---------------------------\n    assign wreq_data   = {wreq_length, wreq_addr};\n    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];\n    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];\n\n    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;\n    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;\n\n    assign end_addr    = start_addr + align_len;\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            align_len   <= 0;\n        else if (ACLK_EN) begin\n            if(fifo_wreq_valid && ready_for_wreq) begin\n                if (zero_len_event || negative_len_event)\n                    align_len   <= 32'b0;\n                else\n                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;\n            end\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            start_addr <= 0;\n        else if (ACLK_EN) begin\n            if(fifo_wreq_valid && ready_for_wreq)\n                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            fifo_wreq_valid_buf <= 1'b0;\n        else if (ACLK_EN) begin\n            if(next_wreq)\n                fifo_wreq_valid_buf <= fifo_wreq_valid;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            invalid_len_event <= 1'b0;\n        else if (ACLK_EN) begin\n            if(next_wreq)\n                invalid_len_event <= zero_len_event || negative_len_event;\n        end\n    end\n\n    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;\n    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));\n    assign fifo_wreq_read = next_wreq;\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            wreq_handling <= 1'b0;\n        else if (ACLK_EN) begin\n            if (fifo_wreq_valid_buf && ~wreq_handling)\n                wreq_handling <= 1'b1;\n            else if (~fifo_wreq_valid_buf && last_sect && next_sect)\n                wreq_handling <= 1'b0;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            start_addr_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_wreq)\n                start_addr_buf <= start_addr;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            end_addr_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_wreq)\n                end_addr_buf <= end_addr;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            beat_len_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_wreq)\n                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            sect_cnt <= 0;\n        else if (ACLK_EN) begin\n            if (next_wreq)\n                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];\n            else if (next_sect)\n                sect_cnt <= sect_cnt + 1;\n        end\n    end\n\n    // event registers\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            invalid_len_event_reg1 <= 0;\n        else if (ACLK_EN) begin\n            invalid_len_event_reg1 <= invalid_len_event;\n        end\n    end\n    // end event registers\n\n    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);\n    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);\n    assign next_sect  = wreq_handling && ready_for_sect;\n\n    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            sect_addr_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_sect)\n                sect_addr_buf <= sect_addr;\n        end\n    end\n\n    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];\n    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :\n                         ( first_sect && ~last_sect)? start_to_4k:\n                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :\n                                                      BOUNDARY_BEATS;\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            sect_len_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_sect)\n                sect_len_buf <= sect_len;\n        end\n    end\n\n    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            sect_end_buf <= 0;\n        else if (ACLK_EN) begin\n            if (next_sect)\n                sect_end_buf <= sect_end;\n        end\n    end\n\n    // event registers\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            invalid_len_event_reg2 <= 0;\n        else if (ACLK_EN) begin\n            invalid_len_event_reg2 <= invalid_len_event_reg1;\n        end\n    end \n    // end event registers\n\n    assign AWID    = 0;\n    assign AWSIZE  = BUS_ADDR_ALIGN;\n    assign AWBURST = 2'b01;\n    assign AWLOCK  = 2'b00;\n    assign AWCACHE = C_CACHE_VALUE;\n    assign AWPROT  = C_PROT_VALUE;\n    assign AWUSER  = C_USER_VALUE;\n    assign AWQOS   = wreq_qos;\n\n    generate\n    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst\n        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};\n        assign AWLEN   = sect_len_buf;\n        assign AWVALID = AWVALID_Dummy;\n\n        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                AWVALID_Dummy <= 1'b0;\n            else if (ACLK_EN) begin\n                if (invalid_len_event)\n                    AWVALID_Dummy <= 1'b0;\n                else if (next_sect)\n                    AWVALID_Dummy <= 1'b1;\n                else if (~next_sect && AWREADY)\n                    AWVALID_Dummy <= 1'b0;\n            end\n        end\n\n        assign fifo_resp_w = next_sect;\n        assign aw2b_awdata = {last_sect, invalid_len_event};\n\n        assign fifo_burst_w = next_sect;\n        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];\n        assign awlen_tmp    = sect_len;\n        assign burst_end    = sect_end;\n    end\n    else begin : could_multi_bursts\n        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;\n        reg  [7:0]                                          awlen_buf;\n        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;\n        reg                                                 sect_handling;\n        wire                                                last_loop;\n        wire                                                next_loop;\n        wire                                                ready_for_loop;\n\n        assign AWADDR  = awaddr_buf;\n        assign AWLEN   = awlen_buf;\n        assign AWVALID = AWVALID_Dummy;\n\n        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);\n        assign next_loop      = sect_handling && ready_for_loop;\n        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;\n        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                sect_handling <= 1'b0;\n            else if (ACLK_EN) begin\n                if (wreq_handling && ~sect_handling)\n                    sect_handling <= 1'b1;\n                else if (~wreq_handling && last_loop && next_loop)\n                    sect_handling <= 1'b0;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                loop_cnt <= 0;\n            else if (ACLK_EN) begin\n                if (next_sect)\n                    loop_cnt <= 0;\n                else if (next_loop)\n                    loop_cnt <= loop_cnt + 1;\n            end\n        end\n\n        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                awaddr_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_loop)\n                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};\n            end\n        end\n\n        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                awlen_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_loop)\n                    awlen_buf <= awlen_tmp;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                AWVALID_Dummy <= 1'b0;\n            else if (ACLK_EN) begin\n                if (invalid_len_event_reg2)\n                    AWVALID_Dummy <= 1'b0;\n                else if (next_loop)\n                    AWVALID_Dummy <= 1'b1;\n                else if (~next_loop && AWREADY)\n                    AWVALID_Dummy <= 1'b0;\n            end\n        end\n\n        assign fifo_resp_w = next_loop;\n        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                last_sect_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_sect && last_sect)\n                    last_sect_buf <= 1;\n                else if (next_sect)\n                    last_sect_buf <= 0;\n            end\n        end\n\n        assign fifo_burst_w = next_loop;\n        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};\n    end\n    endgenerate\n//------------------------AW channel end-----------------\n\n//------------------------W channel begin----------------\n//------------------------Instantiation------------------\n    dds_DDS_OUTPUT_m_axi_buffer #(\n        .DATA_WIDTH(USER_DW + USER_DW/8),\n        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),\n        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))\n    ) buff_wdata (\n        .clk(ACLK),\n        .reset(ARESET),\n        .sclk_en(ACLK_EN),\n        .if_full_n(wdata_ack),\n        .if_write_ce(1'b1),\n        .if_write(wdata_valid),\n        .if_din(fifo_wdata_wstrb),\n        .if_empty_n(data_valid),\n        .if_read_ce(1'b1),\n        .if_read(next_data),\n        .if_dout(data_pack)\n    );\n\n//------------------------Body---------------------------\n    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};\n    assign tmp_data         = data_pack[USER_DW - 1:0];\n    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];\n\n    generate\n    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen\n        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;\n        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;\n        wire [7:0]                          tmp_burst_info;\n        wire                                ready_for_data;\n\n        dds_DDS_OUTPUT_m_axi_fifo #(\n            .DATA_BITS(8),\n            .DEPTH(USER_MAXREQS),\n            .DEPTH_BITS(log2(USER_MAXREQS))\n        ) fifo_burst (\n            .sclk(ACLK),\n            .reset(ARESET),\n            .sclk_en(ACLK_EN),\n            .empty_n(burst_valid),\n            .full_n(fifo_burst_ready),\n            .rdreq(next_burst),\n            .wrreq(fifo_burst_w),\n            .q(burst_len),\n            .data(tmp_burst_info));\n\n        assign WDATA   = data_buf;\n        assign WSTRB   = strb_buf;\n        assign WLAST   = WLAST_Dummy;\n        assign WVALID  = WVALID_Dummy;\n\n        assign tmp_burst_info = awlen_tmp;\n\n        assign next_data        = burst_valid && data_valid && ready_for_data;\n        assign next_burst       = (len_cnt == burst_len) && next_data;\n        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                data_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_data)\n                    data_buf <= tmp_data;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                strb_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_data)\n                    strb_buf <= tmp_strb;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                WVALID_Dummy <= 1'b0;\n            else if (ACLK_EN) begin\n                if (next_data)\n                    WVALID_Dummy <= 1'b1;\n                else if (ready_for_data)\n                    WVALID_Dummy <= 1'b0;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                WLAST_Dummy <= 0;\n            else if (ACLK_EN) begin\n                if (next_burst)\n                    WLAST_Dummy <= 1;\n                else if (ready_for_data)\n                    WLAST_Dummy <= 0;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                len_cnt <= 0;\n            else if (ACLK_EN) begin\n                if (next_burst)\n                    len_cnt <= 0;\n                else if (next_data)\n                    len_cnt <= len_cnt + 1;\n            end\n        end\n\n    end\n    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen\n        localparam\n            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,\n            SPLIT_ALIGN     = log2(TOTAL_SPLIT);\n\n        reg  [USER_DATA_WIDTH - 1:0]                data_buf;\n        reg  [USER_DATA_BYTES - 1:0]                strb_buf;\n        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;\n        wire [7:0]                                  tmp_burst_info;\n        wire                                        first_split;\n        wire                                        next_split;\n        wire                                        last_split;\n        wire                                        ready_for_data;\n\n        dds_DDS_OUTPUT_m_axi_fifo #(\n            .DATA_BITS(8),\n            .DEPTH(USER_MAXREQS),\n            .DEPTH_BITS(log2(USER_MAXREQS))\n        ) fifo_burst (\n            .sclk(ACLK),\n            .reset(ARESET),\n            .sclk_en(ACLK_EN),\n            .empty_n(burst_valid),\n            .full_n(fifo_burst_ready),\n            .rdreq(next_burst),\n            .wrreq(fifo_burst_w),\n            .q(burst_len),\n            .data(tmp_burst_info));\n\n        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];\n        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];\n        assign WLAST   = WLAST_Dummy;\n        assign WVALID  = WVALID_Dummy;\n\n        assign tmp_burst_info = awlen_tmp;\n\n        assign next_data        = first_split;\n        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;\n        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);\n\n        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;\n        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;\n        assign next_split  = (split_cnt != 0) && ready_for_data;\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                split_cnt <= 0;\n            else if (ACLK_EN) begin\n                if (last_split)\n                    split_cnt <= 0;\n                else if (first_split || next_split)\n                    split_cnt <= split_cnt + 1;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                len_cnt <= 0;\n            else if (ACLK_EN) begin\n                if (next_burst)\n                    len_cnt <= 0;\n                else if (next_data || next_split)\n                    len_cnt <= len_cnt + 1;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                data_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_data)\n                    data_buf <= tmp_data;\n                else if (next_split)\n                    data_buf <= data_buf >> BUS_DATA_WIDTH;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                strb_buf <= 0;\n            else if (ACLK_EN) begin\n                if (next_data)\n                    strb_buf <= tmp_strb;\n                else if (next_split)\n                    strb_buf <= strb_buf >> BUS_DATA_BYTES;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                WVALID_Dummy <= 0;\n            else if (ACLK_EN) begin\n                if (next_data)\n                    WVALID_Dummy <= 1;\n                else if (~(first_split || next_split) && ready_for_data)\n                    WVALID_Dummy <= 0;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                WLAST_Dummy <= 0;\n            else if (ACLK_EN) begin\n                if (next_burst && last_split)\n                    WLAST_Dummy <= 1;\n                else if (ready_for_data)\n                    WLAST_Dummy <= 0;\n            end\n        end\n\n    end\n    else begin: bus_wide_gen\n        localparam\n            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,\n            PAD_ALIGN       = log2(TOTAL_PADS);\n\n        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;\n        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;\n        wire [2*PAD_ALIGN + 7:0]                    burst_pack;\n        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;\n        wire [PAD_ALIGN - 1:0]                      head_pads;\n        wire [PAD_ALIGN - 1:0]                      tail_pads;\n        wire [TOTAL_PADS - 1:0]                     add_head;\n        wire [TOTAL_PADS - 1:0]                     add_tail;\n        wire [TOTAL_PADS - 1:0]                     pad_oh;\n        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;\n        wire [TOTAL_PADS - 1:0]                     head_pad_sel;\n        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;\n        wire [7:0]                                  awlen_tmp_t;\n        wire                                        ready_for_data;\n        wire                                        next_pad;\n        reg                                         first_pad;\n        wire                                        last_pad;\n        wire                                        first_beat;\n        wire                                        last_beat;\n        wire                                        next_beat;\n\n        dds_DDS_OUTPUT_m_axi_fifo #(\n            .DATA_BITS(8 + 2*PAD_ALIGN),\n            .DEPTH(USER_MAXREQS),\n            .DEPTH_BITS(log2(USER_MAXREQS))\n        ) fifo_burst (\n            .sclk(ACLK),\n            .reset(ARESET),\n            .sclk_en(ACLK_EN),\n            .empty_n(burst_valid),\n            .full_n(fifo_burst_ready),\n            .rdreq(next_burst),\n            .wrreq(fifo_burst_w),\n            .q(burst_pack),\n            .data(tmp_burst_info));\n\n        assign WDATA   = data_buf;\n        assign WSTRB   = strb_buf;\n        assign WLAST   = WLAST_Dummy;\n        assign WVALID  = WVALID_Dummy;\n\n        assign awlen_tmp_t = awlen_tmp;\n        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};\n\n        dds_DDS_OUTPUT_m_axi_decoder #(\n            .DIN_WIDTH(PAD_ALIGN)\n        ) head_pad_decoder (\n            .din(head_pads),\n            .dout(head_pad_sel));\n\n        dds_DDS_OUTPUT_m_axi_decoder #(\n            .DIN_WIDTH(PAD_ALIGN)\n        ) tail_pad_decoder (\n            .din(tail_pads),\n            .dout(tail_pad_sel));\n\n        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];\n        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];\n        assign burst_len = burst_pack[7:0];\n\n        assign next_data        = next_pad;\n        assign next_burst       = last_beat && next_beat;\n        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);\n\n        assign first_beat = (len_cnt == 0) && burst_valid;\n        assign last_beat  = (len_cnt == burst_len) && burst_valid;\n        assign next_beat  = burst_valid && last_pad && ready_for_data;\n\n        assign next_pad  = burst_valid && data_valid && ready_for_data;\n        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                first_pad <= 1;\n            else if (ACLK_EN) begin\n                if (next_pad && ~last_pad)\n                    first_pad <= 0;\n                else if (next_pad && last_pad)\n                    first_pad <= 1;\n            end\n        end\n\n        assign pad_oh = (data_valid == 0)?          0 :\n                        (first_pad && first_beat)?  1 << head_pads :\n                        (first_pad)?                1 :\n                                                    pad_oh_reg;\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                pad_oh_reg <= 0;\n            else if (ACLK_EN) begin\n                if (next_pad)\n                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};\n            end\n        end\n\n        genvar  i;\n        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen\n            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;\n            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;\n\n            always @(posedge ACLK)\n            begin\n                if (ARESET)\n                    data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;\n                else if (ACLK_EN) begin\n                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)\n                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;\n                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)\n                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;\n                end\n            end\n\n            always @(posedge ACLK)\n            begin\n                if (ARESET)\n                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;\n                else if (ACLK_EN) begin\n                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)\n                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;\n                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)\n                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;\n                end\n            end\n\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                WVALID_Dummy <= 0;\n            else if (ACLK_EN) begin\n                if (next_beat)\n                    WVALID_Dummy <= 1;\n                else if (ready_for_data)\n                    WVALID_Dummy <= 0;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                WLAST_Dummy <= 0;\n            else if (ACLK_EN) begin\n                if (next_burst)\n                    WLAST_Dummy <= 1;\n                else if (ready_for_data)\n                    WLAST_Dummy <= 0;\n            end\n        end\n\n        always @(posedge ACLK)\n        begin\n            if (ARESET)\n                len_cnt <= 0;\n            else if (ACLK_EN) begin\n                if (next_burst)\n                    len_cnt <= 0;\n                else if (next_beat)\n                    len_cnt <= len_cnt + 1;\n            end\n        end\n\n    end\n    endgenerate\n\n//------------------------W channel end------------------\n\n//------------------------B channel begin----------------\n//------------------------Instantiation------------------\n    dds_DDS_OUTPUT_m_axi_fifo #(\n        .DATA_BITS(2),\n        .DEPTH(NUM_WRITE_OUTSTANDING-1),\n        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))\n    ) fifo_resp (\n        .sclk(ACLK),\n        .reset(ARESET),\n        .sclk_en(ACLK_EN),\n        .empty_n(need_wrsp),\n        .full_n(fifo_resp_ready),\n        .rdreq(next_resp),\n        .wrreq(fifo_resp_w),\n        .q(aw2b_bdata),\n        .data(aw2b_awdata));\n\n    dds_DDS_OUTPUT_m_axi_fifo #(\n        .DATA_BITS(2),\n        .DEPTH(USER_MAXREQS),\n        .DEPTH_BITS(log2(USER_MAXREQS))\n    ) fifo_resp_to_user (\n        .sclk(ACLK),\n        .reset(ARESET),\n        .sclk_en(ACLK_EN),\n        .empty_n(wrsp_valid),\n        .full_n(resp_ready),\n        .rdreq(wrsp_ack),\n        .wrreq(resp_match),\n        .q(wrsp),\n        .data(bresp_tmp));\n\n//------------------------Body---------------------------\n    assign BREADY = resp_ready;\n    assign last_resp = aw2b_bdata[1];\n    assign invalid_event = aw2b_bdata[0];\n    assign resp_match = ((next_resp && last_resp) || invalid_event) && need_wrsp;\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            next_resp <= 1'b0;\n        else if (ACLK_EN) begin\n            next_resp <= BVALID && resp_ready;\n        end\n    end\n\n    always @(posedge ACLK)\n    begin\n        if (ARESET)\n            bresp_tmp <= 2'b00;\n        else if (ACLK_EN) begin\n            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0\n                bresp_tmp <= 2'b00;\n            else if (resp_match && next_resp)       // last resp but has resp for next cycle\n                bresp_tmp <= BRESP;\n            else if (BVALID && resp_ready && ~bresp_tmp[1])\n                bresp_tmp <= BRESP;\n        end\n    end\n\n//------------------------B channel end------------------\nendmodule\n", "num_lines": 2464}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// ==============================================================\n// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC\n// Version: 2016.3\n// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.\n// \n// ==============================================================\n\n`timescale 1 ns / 1 ps\n\nmodule dds_mac_muladd_16eOg_DSP48_1(\n    input clk,\n    input rst,\n    input ce,\n    input  [16 - 1:0] in0,\n    input  [18 - 1:0] in1,\n    input  [43 - 1:0] in2,\n    output [44 - 1:0]  dout);\n\nwire signed [27 - 1:0]     a;\nwire signed [18 - 1:0]     b;\nwire signed [48 - 1:0]     c;\nwire signed [45 - 1:0]     m;\nwire signed [48 - 1:0]     p;\nreg  signed [45 - 1:0]     m_reg;\nreg  signed [27 - 1:0]     a_reg;\nreg  signed [18 - 1:0]     b_reg;\nreg  signed [48 - 1:0]     p_reg;\n\nassign a  = $unsigned(in0);\nassign b  = $signed(in1);\nassign c  = $signed(in2);\n\nassign m  = a_reg * b_reg;\nassign p  = m_reg + c;\n\nalways @(posedge clk) begin\n    if (rst) begin\n        m_reg  <= 0;\n        a_reg  <= 0;\n        b_reg  <= 0;\n        p_reg  <= 0;\n    end else if (ce) begin\n        m_reg  <= m;\n        a_reg  <= a;\n        b_reg  <= b;\n        p_reg  <= p;\n    end\nend\n\nassign dout = p_reg;\n\nendmodule\n\n`timescale 1 ns / 1 ps\nmodule dds_mac_muladd_16eOg(\n    clk,\n    reset,\n    ce,\n    din0,\n    din1,\n    din2,\n    dout);\n\nparameter ID = 32'd1;\nparameter NUM_STAGE = 32'd1;\nparameter din0_WIDTH = 32'd1;\nparameter din1_WIDTH = 32'd1;\nparameter din2_WIDTH = 32'd1;\nparameter dout_WIDTH = 32'd1;\ninput clk;\ninput reset;\ninput ce;\ninput[din0_WIDTH - 1:0] din0;\ninput[din1_WIDTH - 1:0] din1;\ninput[din2_WIDTH - 1:0] din2;\noutput[dout_WIDTH - 1:0] dout;\n\n\n\ndds_mac_muladd_16eOg_DSP48_1 dds_mac_muladd_16eOg_DSP48_1_U(\n    .clk( clk ),\n    .rst( reset ),\n    .ce( ce ),\n    .in0( din0 ),\n    .in1( din1 ),\n    .in2( din2 ),\n    .dout( dout ));\n\nendmodule\n\n", "num_lines": 91}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// ==============================================================\n// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC\n// Version: 2016.3\n// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.\n// \n// ==============================================================\n\n`timescale 1 ns / 1 ps\n\nmodule dds_mac_mulsub_18dEe_DSP48_0(\n    input clk,\n    input rst,\n    input ce,\n    input  [18 - 1:0] in0,\n    input  [16 - 1:0] in1,\n    input  [43 - 1:0] in2,\n    output [44 - 1:0]  dout);\n\nwire signed [27 - 1:0]     a;\nwire signed [18 - 1:0]     b;\nwire signed [48 - 1:0]     c;\nwire signed [45 - 1:0]     m;\nwire signed [48 - 1:0]     p;\nreg  signed [45 - 1:0]     m_reg;\nreg  signed [27 - 1:0]     a_reg;\nreg  signed [18 - 1:0]     b_reg;\nreg  signed [48 - 1:0]     p_reg;\n\nassign a  = $signed(in0);\nassign b  = $unsigned(in1);\nassign c  = $signed(in2);\n\nassign m  = a_reg * b_reg;\nassign p  = c - m_reg;\n\nalways @(posedge clk) begin\n    if (rst) begin\n        m_reg  <= 0;\n        a_reg  <= 0;\n        b_reg  <= 0;\n        p_reg  <= 0;\n    end else if (ce) begin\n        m_reg  <= m;\n        a_reg  <= a;\n        b_reg  <= b;\n        p_reg  <= p;\n    end\nend\n\nassign dout = p_reg;\n\nendmodule\n\n`timescale 1 ns / 1 ps\nmodule dds_mac_mulsub_18dEe(\n    clk,\n    reset,\n    ce,\n    din0,\n    din1,\n    din2,\n    dout);\n\nparameter ID = 32'd1;\nparameter NUM_STAGE = 32'd1;\nparameter din0_WIDTH = 32'd1;\nparameter din1_WIDTH = 32'd1;\nparameter din2_WIDTH = 32'd1;\nparameter dout_WIDTH = 32'd1;\ninput clk;\ninput reset;\ninput ce;\ninput[din0_WIDTH - 1:0] din0;\ninput[din1_WIDTH - 1:0] din1;\ninput[din2_WIDTH - 1:0] din2;\noutput[dout_WIDTH - 1:0] dout;\n\n\n\ndds_mac_mulsub_18dEe_DSP48_0 dds_mac_mulsub_18dEe_DSP48_0_U(\n    .clk( clk ),\n    .rst( reset ),\n    .ce( ce ),\n    .in0( din0 ),\n    .in1( din1 ),\n    .in2( din2 ),\n    .dout( dout ));\n\nendmodule\n\n", "num_lines": 91}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// ==============================================================\n// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC\n// Version: 2016.3\n// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.\n// \n// ==============================================================\n\n`timescale 1ns/1ps\nmodule dds_PROG_BUS_s_axi\n#(parameter\n    C_S_AXI_ADDR_WIDTH = 5,\n    C_S_AXI_DATA_WIDTH = 32\n)(\n    // axi4 lite slave signals\n    input  wire                          ACLK,\n    input  wire                          ARESET,\n    input  wire                          ACLK_EN,\n    input  wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,\n    input  wire                          AWVALID,\n    output wire                          AWREADY,\n    input  wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,\n    input  wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,\n    input  wire                          WVALID,\n    output wire                          WREADY,\n    output wire [1:0]                    BRESP,\n    output wire                          BVALID,\n    input  wire                          BREADY,\n    input  wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,\n    input  wire                          ARVALID,\n    output wire                          ARREADY,\n    output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,\n    output wire [1:0]                    RRESP,\n    output wire                          RVALID,\n    input  wire                          RREADY,\n    output wire                          interrupt,\n    // user signals\n    output wire                          ap_start,\n    input  wire                          ap_done,\n    input  wire                          ap_ready,\n    input  wire                          ap_idle,\n    output wire [31:0]                   nofSample,\n    output wire [31:0]                   incr_V\n);\n//------------------------Address Info-------------------\n// 0x00 : Control signals\n//        bit 0  - ap_start (Read/Write/COH)\n//        bit 1  - ap_done (Read/COR)\n//        bit 2  - ap_idle (Read)\n//        bit 3  - ap_ready (Read)\n//        bit 7  - auto_restart (Read/Write)\n//        others - reserved\n// 0x04 : Global Interrupt Enable Register\n//        bit 0  - Global Interrupt Enable (Read/Write)\n//        others - reserved\n// 0x08 : IP Interrupt Enable Register (Read/Write)\n//        bit 0  - Channel 0 (ap_done)\n//        bit 1  - Channel 1 (ap_ready)\n//        others - reserved\n// 0x0c : IP Interrupt Status Register (Read/TOW)\n//        bit 0  - Channel 0 (ap_done)\n//        bit 1  - Channel 1 (ap_ready)\n//        others - reserved\n// 0x10 : Data signal of nofSample\n//        bit 31~0 - nofSample[31:0] (Read/Write)\n// 0x14 : reserved\n// 0x18 : Data signal of incr_V\n//        bit 31~0 - incr_V[31:0] (Read/Write)\n// 0x1c : reserved\n// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)\n\n//------------------------Parameter----------------------\nlocalparam\n    ADDR_AP_CTRL          = 5'h00,\n    ADDR_GIE              = 5'h04,\n    ADDR_IER              = 5'h08,\n    ADDR_ISR              = 5'h0c,\n    ADDR_NOFSAMPLE_DATA_0 = 5'h10,\n    ADDR_NOFSAMPLE_CTRL   = 5'h14,\n    ADDR_INCR_V_DATA_0    = 5'h18,\n    ADDR_INCR_V_CTRL      = 5'h1c,\n    WRIDLE                = 2'd0,\n    WRDATA                = 2'd1,\n    WRRESP                = 2'd2,\n    RDIDLE                = 2'd0,\n    RDDATA                = 2'd1,\n    ADDR_BITS         = 5;\n\n//------------------------Local signal-------------------\n    reg  [1:0]                    wstate;\n    reg  [1:0]                    wnext;\n    reg  [ADDR_BITS-1:0]          waddr;\n    wire [31:0]                   wmask;\n    wire                          aw_hs;\n    wire                          w_hs;\n    reg  [1:0]                    rstate;\n    reg  [1:0]                    rnext;\n    reg  [31:0]                   rdata;\n    wire                          ar_hs;\n    wire [ADDR_BITS-1:0]          raddr;\n    // internal registers\n    wire                          int_ap_idle;\n    wire                          int_ap_ready;\n    reg                           int_ap_done;\n    reg                           int_ap_start;\n    reg                           int_auto_restart;\n    reg                           int_gie;\n    reg  [1:0]                    int_ier;\n    reg  [1:0]                    int_isr;\n    reg  [31:0]                   int_nofSample;\n    reg  [31:0]                   int_incr_V;\n\n//------------------------Instantiation------------------\n\n//------------------------AXI write fsm------------------\nassign AWREADY = (~ARESET) & (wstate == WRIDLE);\nassign WREADY  = (wstate == WRDATA);\nassign BRESP   = 2'b00;  // OKAY\nassign BVALID  = (wstate == WRRESP);\nassign wmask   = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };\nassign aw_hs   = AWVALID & AWREADY;\nassign w_hs    = WVALID & WREADY;\n\n// wstate\nalways @(posedge ACLK) begin\n    if (ARESET)\n        wstate <= WRIDLE;\n    else if (ACLK_EN)\n        wstate <= wnext;\nend\n\n// wnext\nalways @(*) begin\n    case (wstate)\n        WRIDLE:\n            if (AWVALID)\n                wnext = WRDATA;\n            else\n                wnext = WRIDLE;\n        WRDATA:\n            if (WVALID)\n                wnext = WRRESP;\n            else\n                wnext = WRDATA;\n        WRRESP:\n            if (BREADY)\n                wnext = WRIDLE;\n            else\n                wnext = WRRESP;\n        default:\n            wnext = WRIDLE;\n    endcase\nend\n\n// waddr\nalways @(posedge ACLK) begin\n    if (ACLK_EN) begin\n        if (aw_hs)\n            waddr <= AWADDR[ADDR_BITS-1:0];\n    end\nend\n\n//------------------------AXI read fsm-------------------\nassign ARREADY = (~ARESET) && (rstate == RDIDLE);\nassign RDATA   = rdata;\nassign RRESP   = 2'b00;  // OKAY\nassign RVALID  = (rstate == RDDATA);\nassign ar_hs   = ARVALID & ARREADY;\nassign raddr   = ARADDR[ADDR_BITS-1:0];\n\n// rstate\nalways @(posedge ACLK) begin\n    if (ARESET)\n        rstate <= RDIDLE;\n    else if (ACLK_EN)\n        rstate <= rnext;\nend\n\n// rnext\nalways @(*) begin\n    case (rstate)\n        RDIDLE:\n            if (ARVALID)\n                rnext = RDDATA;\n            else\n                rnext = RDIDLE;\n        RDDATA:\n            if (RREADY & RVALID)\n                rnext = RDIDLE;\n            else\n                rnext = RDDATA;\n        default:\n            rnext = RDIDLE;\n    endcase\nend\n\n// rdata\nalways @(posedge ACLK) begin\n    if (ACLK_EN) begin\n        if (ar_hs) begin\n            rdata <= 1'b0;\n            case (raddr)\n                ADDR_AP_CTRL: begin\n                    rdata[0] <= int_ap_start;\n                    rdata[1] <= int_ap_done;\n                    rdata[2] <= int_ap_idle;\n                    rdata[3] <= int_ap_ready;\n                    rdata[7] <= int_auto_restart;\n                end\n                ADDR_GIE: begin\n                    rdata <= int_gie;\n                end\n                ADDR_IER: begin\n                    rdata <= int_ier;\n                end\n                ADDR_ISR: begin\n                    rdata <= int_isr;\n                end\n                ADDR_NOFSAMPLE_DATA_0: begin\n                    rdata <= int_nofSample[31:0];\n                end\n                ADDR_INCR_V_DATA_0: begin\n                    rdata <= int_incr_V[31:0];\n                end\n            endcase\n        end\n    end\nend\n\n\n//------------------------Register logic-----------------\nassign interrupt    = int_gie & (|int_isr);\nassign ap_start     = int_ap_start;\nassign int_ap_idle  = ap_idle;\nassign int_ap_ready = ap_ready;\nassign nofSample    = int_nofSample;\nassign incr_V       = int_incr_V;\n// int_ap_start\nalways @(posedge ACLK) begin\n    if (ARESET)\n        int_ap_start <= 1'b0;\n    else if (ACLK_EN) begin\n        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])\n            int_ap_start <= 1'b1;\n        else if (int_ap_ready)\n            int_ap_start <= int_auto_restart; // clear on handshake/auto restart\n    end\nend\n\n// int_ap_done\nalways @(posedge ACLK) begin\n    if (ARESET)\n        int_ap_done <= 1'b0;\n    else if (ACLK_EN) begin\n        if (ap_done)\n            int_ap_done <= 1'b1;\n        else if (ar_hs && raddr == ADDR_AP_CTRL)\n            int_ap_done <= 1'b0; // clear on read\n    end\nend\n\n// int_auto_restart\nalways @(posedge ACLK) begin\n    if (ARESET)\n        int_auto_restart <= 1'b0;\n    else if (ACLK_EN) begin\n        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])\n            int_auto_restart <=  WDATA[7];\n    end\nend\n\n// int_gie\nalways @(posedge ACLK) begin\n    if (ARESET)\n        int_gie <= 1'b0;\n    else if (ACLK_EN) begin\n        if (w_hs && waddr == ADDR_GIE && WSTRB[0])\n            int_gie <= WDATA[0];\n    end\nend\n\n// int_ier\nalways @(posedge ACLK) begin\n    if (ARESET)\n        int_ier <= 1'b0;\n    else if (ACLK_EN) begin\n        if (w_hs && waddr == ADDR_IER && WSTRB[0])\n            int_ier <= WDATA[1:0];\n    end\nend\n\n// int_isr[0]\nalways @(posedge ACLK) begin\n    if (ARESET)\n        int_isr[0] <= 1'b0;\n    else if (ACLK_EN) begin\n        if (int_ier[0] & ap_done)\n            int_isr[0] <= 1'b1;\n        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])\n            int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write\n    end\nend\n\n// int_isr[1]\nalways @(posedge ACLK) begin\n    if (ARESET)\n        int_isr[1] <= 1'b0;\n    else if (ACLK_EN) begin\n        if (int_ier[1] & ap_ready)\n            int_isr[1] <= 1'b1;\n        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])\n            int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write\n    end\nend\n\n// int_nofSample[31:0]\nalways @(posedge ACLK) begin\n    if (ARESET)\n        int_nofSample[31:0] <= 0;\n    else if (ACLK_EN) begin\n        if (w_hs && waddr == ADDR_NOFSAMPLE_DATA_0)\n            int_nofSample[31:0] <= (WDATA[31:0] & wmask) | (int_nofSample[31:0] & ~wmask);\n    end\nend\n\n// int_incr_V[31:0]\nalways @(posedge ACLK) begin\n    if (ARESET)\n        int_incr_V[31:0] <= 0;\n    else if (ACLK_EN) begin\n        if (w_hs && waddr == ADDR_INCR_V_DATA_0)\n            int_incr_V[31:0] <= (WDATA[31:0] & wmask) | (int_incr_V[31:0] & ~wmask);\n    end\nend\n\n\n//------------------------Memory logic-------------------\n\nendmodule\n", "num_lines": 339}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// ==============================================================\n// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC\n// Version: 2016.3\n// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.\n// \n// ===========================================================\n\n`timescale 1 ns / 1 ps \n\nmodule process_frame (\n        ap_clk,\n        ap_rst,\n        ap_start,\n        ap_done,\n        ap_idle,\n        ap_ready,\n        nofSample,\n        incr_V,\n        m_axi_cos_out_V_AWVALID,\n        m_axi_cos_out_V_AWREADY,\n        m_axi_cos_out_V_AWADDR,\n        m_axi_cos_out_V_AWID,\n        m_axi_cos_out_V_AWLEN,\n        m_axi_cos_out_V_AWSIZE,\n        m_axi_cos_out_V_AWBURST,\n        m_axi_cos_out_V_AWLOCK,\n        m_axi_cos_out_V_AWCACHE,\n        m_axi_cos_out_V_AWPROT,\n        m_axi_cos_out_V_AWQOS,\n        m_axi_cos_out_V_AWREGION,\n        m_axi_cos_out_V_AWUSER,\n        m_axi_cos_out_V_WVALID,\n        m_axi_cos_out_V_WREADY,\n        m_axi_cos_out_V_WDATA,\n        m_axi_cos_out_V_WSTRB,\n        m_axi_cos_out_V_WLAST,\n        m_axi_cos_out_V_WID,\n        m_axi_cos_out_V_WUSER,\n        m_axi_cos_out_V_ARVALID,\n        m_axi_cos_out_V_ARREADY,\n        m_axi_cos_out_V_ARADDR,\n        m_axi_cos_out_V_ARID,\n        m_axi_cos_out_V_ARLEN,\n        m_axi_cos_out_V_ARSIZE,\n        m_axi_cos_out_V_ARBURST,\n        m_axi_cos_out_V_ARLOCK,\n        m_axi_cos_out_V_ARCACHE,\n        m_axi_cos_out_V_ARPROT,\n        m_axi_cos_out_V_ARQOS,\n        m_axi_cos_out_V_ARREGION,\n        m_axi_cos_out_V_ARUSER,\n        m_axi_cos_out_V_RVALID,\n        m_axi_cos_out_V_RREADY,\n        m_axi_cos_out_V_RDATA,\n        m_axi_cos_out_V_RLAST,\n        m_axi_cos_out_V_RID,\n        m_axi_cos_out_V_RUSER,\n        m_axi_cos_out_V_RRESP,\n        m_axi_cos_out_V_BVALID,\n        m_axi_cos_out_V_BREADY,\n        m_axi_cos_out_V_BRESP,\n        m_axi_cos_out_V_BID,\n        m_axi_cos_out_V_BUSER,\n        m_axi_sin_out_V_AWVALID,\n        m_axi_sin_out_V_AWREADY,\n        m_axi_sin_out_V_AWADDR,\n        m_axi_sin_out_V_AWID,\n        m_axi_sin_out_V_AWLEN,\n        m_axi_sin_out_V_AWSIZE,\n        m_axi_sin_out_V_AWBURST,\n        m_axi_sin_out_V_AWLOCK,\n        m_axi_sin_out_V_AWCACHE,\n        m_axi_sin_out_V_AWPROT,\n        m_axi_sin_out_V_AWQOS,\n        m_axi_sin_out_V_AWREGION,\n        m_axi_sin_out_V_AWUSER,\n        m_axi_sin_out_V_WVALID,\n        m_axi_sin_out_V_WREADY,\n        m_axi_sin_out_V_WDATA,\n        m_axi_sin_out_V_WSTRB,\n        m_axi_sin_out_V_WLAST,\n        m_axi_sin_out_V_WID,\n        m_axi_sin_out_V_WUSER,\n        m_axi_sin_out_V_ARVALID,\n        m_axi_sin_out_V_ARREADY,\n        m_axi_sin_out_V_ARADDR,\n        m_axi_sin_out_V_ARID,\n        m_axi_sin_out_V_ARLEN,\n        m_axi_sin_out_V_ARSIZE,\n        m_axi_sin_out_V_ARBURST,\n        m_axi_sin_out_V_ARLOCK,\n        m_axi_sin_out_V_ARCACHE,\n        m_axi_sin_out_V_ARPROT,\n        m_axi_sin_out_V_ARQOS,\n        m_axi_sin_out_V_ARREGION,\n        m_axi_sin_out_V_ARUSER,\n        m_axi_sin_out_V_RVALID,\n        m_axi_sin_out_V_RREADY,\n        m_axi_sin_out_V_RDATA,\n        m_axi_sin_out_V_RLAST,\n        m_axi_sin_out_V_RID,\n        m_axi_sin_out_V_RUSER,\n        m_axi_sin_out_V_RRESP,\n        m_axi_sin_out_V_BVALID,\n        m_axi_sin_out_V_BREADY,\n        m_axi_sin_out_V_BRESP,\n        m_axi_sin_out_V_BID,\n        m_axi_sin_out_V_BUSER\n);\n\nparameter    ap_ST_fsm_state1 = 3'b1;\nparameter    ap_ST_fsm_pp0_stage0 = 3'b10;\nparameter    ap_ST_fsm_state27 = 3'b100;\nparameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;\nparameter    ap_const_lv3_0 = 3'b000;\nparameter    ap_const_lv2_0 = 2'b00;\nparameter    ap_const_lv4_0 = 4'b0000;\nparameter    ap_const_lv32_1 = 32'b1;\nparameter    ap_const_lv31_0 = 31'b0000000000000000000000000000000;\nparameter    ap_const_lv2_3 = 2'b11;\nparameter    ap_const_lv31_1 = 31'b1;\nparameter    ap_const_lv32_2 = 32'b10;\n\ninput   ap_clk;\ninput   ap_rst;\ninput   ap_start;\noutput   ap_done;\noutput   ap_idle;\noutput   ap_ready;\ninput  [31:0] nofSample;\ninput  [31:0] incr_V;\noutput   m_axi_cos_out_V_AWVALID;\ninput   m_axi_cos_out_V_AWREADY;\noutput  [31:0] m_axi_cos_out_V_AWADDR;\noutput  [0:0] m_axi_cos_out_V_AWID;\noutput  [31:0] m_axi_cos_out_V_AWLEN;\noutput  [2:0] m_axi_cos_out_V_AWSIZE;\noutput  [1:0] m_axi_cos_out_V_AWBURST;\noutput  [1:0] m_axi_cos_out_V_AWLOCK;\noutput  [3:0] m_axi_cos_out_V_AWCACHE;\noutput  [2:0] m_axi_cos_out_V_AWPROT;\noutput  [3:0] m_axi_cos_out_V_AWQOS;\noutput  [3:0] m_axi_cos_out_V_AWREGION;\noutput  [0:0] m_axi_cos_out_V_AWUSER;\noutput   m_axi_cos_out_V_WVALID;\ninput   m_axi_cos_out_V_WREADY;\noutput  [15:0] m_axi_cos_out_V_WDATA;\noutput  [1:0] m_axi_cos_out_V_WSTRB;\noutput   m_axi_cos_out_V_WLAST;\noutput  [0:0] m_axi_cos_out_V_WID;\noutput  [0:0] m_axi_cos_out_V_WUSER;\noutput   m_axi_cos_out_V_ARVALID;\ninput   m_axi_cos_out_V_ARREADY;\noutput  [31:0] m_axi_cos_out_V_ARADDR;\noutput  [0:0] m_axi_cos_out_V_ARID;\noutput  [31:0] m_axi_cos_out_V_ARLEN;\noutput  [2:0] m_axi_cos_out_V_ARSIZE;\noutput  [1:0] m_axi_cos_out_V_ARBURST;\noutput  [1:0] m_axi_cos_out_V_ARLOCK;\noutput  [3:0] m_axi_cos_out_V_ARCACHE;\noutput  [2:0] m_axi_cos_out_V_ARPROT;\noutput  [3:0] m_axi_cos_out_V_ARQOS;\noutput  [3:0] m_axi_cos_out_V_ARREGION;\noutput  [0:0] m_axi_cos_out_V_ARUSER;\ninput   m_axi_cos_out_V_RVALID;\noutput   m_axi_cos_out_V_RREADY;\ninput  [15:0] m_axi_cos_out_V_RDATA;\ninput   m_axi_cos_out_V_RLAST;\ninput  [0:0] m_axi_cos_out_V_RID;\ninput  [0:0] m_axi_cos_out_V_RUSER;\ninput  [1:0] m_axi_cos_out_V_RRESP;\ninput   m_axi_cos_out_V_BVALID;\noutput   m_axi_cos_out_V_BREADY;\ninput  [1:0] m_axi_cos_out_V_BRESP;\ninput  [0:0] m_axi_cos_out_V_BID;\ninput  [0:0] m_axi_cos_out_V_BUSER;\noutput   m_axi_sin_out_V_AWVALID;\ninput   m_axi_sin_out_V_AWREADY;\noutput  [31:0] m_axi_sin_out_V_AWADDR;\noutput  [0:0] m_axi_sin_out_V_AWID;\noutput  [31:0] m_axi_sin_out_V_AWLEN;\noutput  [2:0] m_axi_sin_out_V_AWSIZE;\noutput  [1:0] m_axi_sin_out_V_AWBURST;\noutput  [1:0] m_axi_sin_out_V_AWLOCK;\noutput  [3:0] m_axi_sin_out_V_AWCACHE;\noutput  [2:0] m_axi_sin_out_V_AWPROT;\noutput  [3:0] m_axi_sin_out_V_AWQOS;\noutput  [3:0] m_axi_sin_out_V_AWREGION;\noutput  [0:0] m_axi_sin_out_V_AWUSER;\noutput   m_axi_sin_out_V_WVALID;\ninput   m_axi_sin_out_V_WREADY;\noutput  [15:0] m_axi_sin_out_V_WDATA;\noutput  [1:0] m_axi_sin_out_V_WSTRB;\noutput   m_axi_sin_out_V_WLAST;\noutput  [0:0] m_axi_sin_out_V_WID;\noutput  [0:0] m_axi_sin_out_V_WUSER;\noutput   m_axi_sin_out_V_ARVALID;\ninput   m_axi_sin_out_V_ARREADY;\noutput  [31:0] m_axi_sin_out_V_ARADDR;\noutput  [0:0] m_axi_sin_out_V_ARID;\noutput  [31:0] m_axi_sin_out_V_ARLEN;\noutput  [2:0] m_axi_sin_out_V_ARSIZE;\noutput  [1:0] m_axi_sin_out_V_ARBURST;\noutput  [1:0] m_axi_sin_out_V_ARLOCK;\noutput  [3:0] m_axi_sin_out_V_ARCACHE;\noutput  [2:0] m_axi_sin_out_V_ARPROT;\noutput  [3:0] m_axi_sin_out_V_ARQOS;\noutput  [3:0] m_axi_sin_out_V_ARREGION;\noutput  [0:0] m_axi_sin_out_V_ARUSER;\ninput   m_axi_sin_out_V_RVALID;\noutput   m_axi_sin_out_V_RREADY;\ninput  [15:0] m_axi_sin_out_V_RDATA;\ninput   m_axi_sin_out_V_RLAST;\ninput  [0:0] m_axi_sin_out_V_RID;\ninput  [0:0] m_axi_sin_out_V_RUSER;\ninput  [1:0] m_axi_sin_out_V_RRESP;\ninput   m_axi_sin_out_V_BVALID;\noutput   m_axi_sin_out_V_BREADY;\ninput  [1:0] m_axi_sin_out_V_BRESP;\ninput  [0:0] m_axi_sin_out_V_BID;\ninput  [0:0] m_axi_sin_out_V_BUSER;\n\nreg ap_done;\nreg ap_idle;\nreg ap_ready;\nreg m_axi_cos_out_V_AWVALID;\nreg m_axi_cos_out_V_WVALID;\nreg m_axi_cos_out_V_BREADY;\nreg m_axi_sin_out_V_AWVALID;\nreg m_axi_sin_out_V_WVALID;\nreg m_axi_sin_out_V_BREADY;\n\n(* fsm_encoding = \"none\" *) reg   [2:0] ap_CS_fsm;\nwire   [0:0] ap_CS_fsm_state1;\nreg    cos_out_V_blk_n_AW;\nreg    ap_enable_reg_pp0_iter18;\nreg    cos_out_V_blk_n_W;\nreg    ap_enable_reg_pp0_iter19;\nreg    cos_out_V_blk_n_B;\nreg    ap_enable_reg_pp0_iter24;\nreg    sin_out_V_blk_n_AW;\nreg    sin_out_V_blk_n_W;\nreg    sin_out_V_blk_n_B;\nreg   [30:0] i_cast6_reg_98;\nwire   [0:0] tmp4_fu_120_p2;\nwire   [31:0] i_cast6_cast_fu_126_p1;\nreg   [31:0] i_cast6_cast_reg_179;\nwire   [0:0] ap_CS_fsm_pp0_stage0;\nreg    ap_sig_ioackin_m_axi_cos_out_V_AWREADY;\nreg    ap_sig_ioackin_m_axi_sin_out_V_AWREADY;\nreg    ap_sig_ioackin_m_axi_cos_out_V_WREADY;\nreg    ap_sig_ioackin_m_axi_sin_out_V_WREADY;\nreg   [31:0] ap_pipeline_reg_pp0_iter1_i_cast6_cast_reg_179;\nreg   [31:0] ap_pipeline_reg_pp0_iter2_i_cast6_cast_reg_179;\nreg   [31:0] ap_pipeline_reg_pp0_iter3_i_cast6_cast_reg_179;\nreg   [31:0] ap_pipeline_reg_pp0_iter4_i_cast6_cast_reg_179;\nreg   [31:0] ap_pipeline_reg_pp0_iter5_i_cast6_cast_reg_179;\nreg   [31:0] ap_pipeline_reg_pp0_iter6_i_cast6_cast_reg_179;\nreg   [31:0] ap_pipeline_reg_pp0_iter7_i_cast6_cast_reg_179;\nreg   [31:0] ap_pipeline_reg_pp0_iter8_i_cast6_cast_reg_179;\nreg   [31:0] ap_pipeline_reg_pp0_iter9_i_cast6_cast_reg_179;\nreg   [31:0] ap_pipeline_reg_pp0_iter10_i_cast6_cast_reg_179;\nreg   [31:0] ap_pipeline_reg_pp0_iter11_i_cast6_cast_reg_179;\nreg   [31:0] ap_pipeline_reg_pp0_iter12_i_cast6_cast_reg_179;\nreg   [31:0] ap_pipeline_reg_pp0_iter13_i_cast6_cast_reg_179;\nreg   [31:0] ap_pipeline_reg_pp0_iter14_i_cast6_cast_reg_179;\nreg   [31:0] ap_pipeline_reg_pp0_iter15_i_cast6_cast_reg_179;\nreg   [31:0] ap_pipeline_reg_pp0_iter16_i_cast6_cast_reg_179;\nreg   [31:0] ap_pipeline_reg_pp0_iter17_i_cast6_cast_reg_179;\nwire   [30:0] i_fu_130_p2;\nreg   [30:0] i_reg_185;\nreg    ap_enable_reg_pp0_iter0;\nwire   [0:0] tmp_fu_140_p2;\nreg   [0:0] tmp_reg_190;\nreg   [15:0] dds_cos_V_reg_194;\nreg   [15:0] dds_sin_V_reg_199;\nreg    ap_enable_reg_pp0_iter1;\nreg    ap_enable_reg_pp0_iter2;\nreg    ap_enable_reg_pp0_iter3;\nreg    ap_enable_reg_pp0_iter4;\nreg    ap_enable_reg_pp0_iter5;\nreg    ap_enable_reg_pp0_iter6;\nreg    ap_enable_reg_pp0_iter7;\nreg    ap_enable_reg_pp0_iter8;\nreg    ap_enable_reg_pp0_iter9;\nreg    ap_enable_reg_pp0_iter10;\nreg    ap_enable_reg_pp0_iter11;\nreg    ap_enable_reg_pp0_iter12;\nreg    ap_enable_reg_pp0_iter13;\nreg    ap_enable_reg_pp0_iter14;\nreg    ap_enable_reg_pp0_iter15;\nreg    ap_enable_reg_pp0_iter16;\nreg    ap_enable_reg_pp0_iter17;\nreg    ap_enable_reg_pp0_iter20;\nreg    ap_enable_reg_pp0_iter21;\nreg    ap_enable_reg_pp0_iter22;\nreg    ap_enable_reg_pp0_iter23;\nwire    grp_process_r_fu_109_ap_start;\nwire    grp_process_r_fu_109_ap_done;\nwire    grp_process_r_fu_109_ap_idle;\nwire    grp_process_r_fu_109_ap_ready;\nreg    grp_process_r_fu_109_ap_ce;\nwire   [15:0] grp_process_r_fu_109_ap_return_0;\nwire   [15:0] grp_process_r_fu_109_ap_return_1;\nreg   [30:0] i_cast6_phi_fu_102_p4;\nreg    ap_reg_grp_process_r_fu_109_ap_start;\nreg    ap_reg_ioackin_m_axi_cos_out_V_AWREADY;\nreg    ap_reg_ioackin_m_axi_cos_out_V_WREADY;\nreg    ap_reg_ioackin_m_axi_sin_out_V_AWREADY;\nreg    ap_reg_ioackin_m_axi_sin_out_V_WREADY;\nwire   [31:0] i_cast_fu_136_p1;\nwire   [0:0] ap_CS_fsm_state27;\nreg   [2:0] ap_NS_fsm;\nreg    ap_condition_425;\nreg    ap_condition_182;\nreg    ap_condition_431;\nreg    ap_condition_434;\nreg    ap_condition_437;\n\n// power-on initialization\ninitial begin\n#0 ap_CS_fsm = 3'b1;\n#0 ap_enable_reg_pp0_iter18 = 1'b0;\n#0 ap_enable_reg_pp0_iter19 = 1'b0;\n#0 ap_enable_reg_pp0_iter24 = 1'b0;\n#0 ap_enable_reg_pp0_iter0 = 1'b0;\n#0 ap_enable_reg_pp0_iter1 = 1'b0;\n#0 ap_enable_reg_pp0_iter2 = 1'b0;\n#0 ap_enable_reg_pp0_iter3 = 1'b0;\n#0 ap_enable_reg_pp0_iter4 = 1'b0;\n#0 ap_enable_reg_pp0_iter5 = 1'b0;\n#0 ap_enable_reg_pp0_iter6 = 1'b0;\n#0 ap_enable_reg_pp0_iter7 = 1'b0;\n#0 ap_enable_reg_pp0_iter8 = 1'b0;\n#0 ap_enable_reg_pp0_iter9 = 1'b0;\n#0 ap_enable_reg_pp0_iter10 = 1'b0;\n#0 ap_enable_reg_pp0_iter11 = 1'b0;\n#0 ap_enable_reg_pp0_iter12 = 1'b0;\n#0 ap_enable_reg_pp0_iter13 = 1'b0;\n#0 ap_enable_reg_pp0_iter14 = 1'b0;\n#0 ap_enable_reg_pp0_iter15 = 1'b0;\n#0 ap_enable_reg_pp0_iter16 = 1'b0;\n#0 ap_enable_reg_pp0_iter17 = 1'b0;\n#0 ap_enable_reg_pp0_iter20 = 1'b0;\n#0 ap_enable_reg_pp0_iter21 = 1'b0;\n#0 ap_enable_reg_pp0_iter22 = 1'b0;\n#0 ap_enable_reg_pp0_iter23 = 1'b0;\n#0 ap_reg_grp_process_r_fu_109_ap_start = 1'b0;\n#0 ap_reg_ioackin_m_axi_cos_out_V_AWREADY = 1'b0;\n#0 ap_reg_ioackin_m_axi_cos_out_V_WREADY = 1'b0;\n#0 ap_reg_ioackin_m_axi_sin_out_V_AWREADY = 1'b0;\n#0 ap_reg_ioackin_m_axi_sin_out_V_WREADY = 1'b0;\nend\n\nprocess_r grp_process_r_fu_109(\n    .ap_clk(ap_clk),\n    .ap_rst(ap_rst),\n    .ap_start(grp_process_r_fu_109_ap_start),\n    .ap_done(grp_process_r_fu_109_ap_done),\n    .ap_idle(grp_process_r_fu_109_ap_idle),\n    .ap_ready(grp_process_r_fu_109_ap_ready),\n    .ap_ce(grp_process_r_fu_109_ap_ce),\n    .incr_V(incr_V),\n    .ap_return_0(grp_process_r_fu_109_ap_return_0),\n    .ap_return_1(grp_process_r_fu_109_ap_return_1)\n);\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_CS_fsm <= ap_ST_fsm_state1;\n    end else begin\n        ap_CS_fsm <= ap_NS_fsm;\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter0 <= 1'b0;\n    end else begin\n        if (((1'b1 == ap_CS_fsm_pp0_stage0) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))) & (1'b0 == tmp_fu_140_p2))) begin\n            ap_enable_reg_pp0_iter0 <= 1'b0;\n        end else if (((ap_CS_fsm_state1 == 1'b1) & ~(ap_start == 1'b0) & ~(1'b0 == tmp4_fu_120_p2))) begin\n            ap_enable_reg_pp0_iter0 <= 1'b1;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter1 <= 1'b0;\n    end else begin\n        if (((1'b1 == ap_CS_fsm_pp0_stage0) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))))) begin\n            ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;\n        end else if (((ap_CS_fsm_state1 == 1'b1) & ~(ap_start == 1'b0) & ~(1'b0 == tmp4_fu_120_p2))) begin\n            ap_enable_reg_pp0_iter1 <= 1'b0;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter10 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter11 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter12 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter13 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter14 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter15 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter16 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter17 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter18 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter19 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter2 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter20 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter21 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter22 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter23 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter23 <= ap_enable_reg_pp0_iter22;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter24 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter24 <= ap_enable_reg_pp0_iter23;\n        end else if (((ap_CS_fsm_state1 == 1'b1) & ~(ap_start == 1'b0) & ~(1'b0 == tmp4_fu_120_p2))) begin\n            ap_enable_reg_pp0_iter24 <= 1'b0;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter3 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter4 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter5 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter6 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter7 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter8 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter9 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n            ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_reg_grp_process_r_fu_109_ap_start <= 1'b0;\n    end else begin\n        if (((1'b1 == ap_CS_fsm_pp0_stage0) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))) & (1'b1 == ap_enable_reg_pp0_iter0))) begin\n            ap_reg_grp_process_r_fu_109_ap_start <= 1'b1;\n        end else if ((1'b1 == grp_process_r_fu_109_ap_ready)) begin\n            ap_reg_grp_process_r_fu_109_ap_start <= 1'b0;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_reg_ioackin_m_axi_cos_out_V_AWREADY <= 1'b0;\n    end else begin\n        if ((1'b1 == ap_enable_reg_pp0_iter18)) begin\n            if ((ap_condition_182 == 1'b1)) begin\n                ap_reg_ioackin_m_axi_cos_out_V_AWREADY <= 1'b0;\n            end else if ((ap_condition_425 == 1'b1)) begin\n                ap_reg_ioackin_m_axi_cos_out_V_AWREADY <= 1'b1;\n            end\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_reg_ioackin_m_axi_cos_out_V_WREADY <= 1'b0;\n    end else begin\n        if ((1'b1 == ap_enable_reg_pp0_iter19)) begin\n            if ((ap_condition_182 == 1'b1)) begin\n                ap_reg_ioackin_m_axi_cos_out_V_WREADY <= 1'b0;\n            end else if ((ap_condition_431 == 1'b1)) begin\n                ap_reg_ioackin_m_axi_cos_out_V_WREADY <= 1'b1;\n            end\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_reg_ioackin_m_axi_sin_out_V_AWREADY <= 1'b0;\n    end else begin\n        if ((1'b1 == ap_enable_reg_pp0_iter18)) begin\n            if ((ap_condition_182 == 1'b1)) begin\n                ap_reg_ioackin_m_axi_sin_out_V_AWREADY <= 1'b0;\n            end else if ((ap_condition_434 == 1'b1)) begin\n                ap_reg_ioackin_m_axi_sin_out_V_AWREADY <= 1'b1;\n            end\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_reg_ioackin_m_axi_sin_out_V_WREADY <= 1'b0;\n    end else begin\n        if ((1'b1 == ap_enable_reg_pp0_iter19)) begin\n            if ((ap_condition_182 == 1'b1)) begin\n                ap_reg_ioackin_m_axi_sin_out_V_WREADY <= 1'b0;\n            end else if ((ap_condition_437 == 1'b1)) begin\n                ap_reg_ioackin_m_axi_sin_out_V_WREADY <= 1'b1;\n            end\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (((ap_CS_fsm_state1 == 1'b1) & ~(ap_start == 1'b0) & ~(1'b0 == tmp4_fu_120_p2))) begin\n        i_cast6_reg_98 <= ap_const_lv31_0;\n    end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))) & (1'b1 == ap_enable_reg_pp0_iter1) & ~(1'b0 == tmp_reg_190))) begin\n        i_cast6_reg_98 <= i_reg_185;\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin\n        ap_pipeline_reg_pp0_iter10_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter9_i_cast6_cast_reg_179[30 : 0];\n        ap_pipeline_reg_pp0_iter11_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter10_i_cast6_cast_reg_179[30 : 0];\n        ap_pipeline_reg_pp0_iter12_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter11_i_cast6_cast_reg_179[30 : 0];\n        ap_pipeline_reg_pp0_iter13_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter12_i_cast6_cast_reg_179[30 : 0];\n        ap_pipeline_reg_pp0_iter14_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter13_i_cast6_cast_reg_179[30 : 0];\n        ap_pipeline_reg_pp0_iter15_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter14_i_cast6_cast_reg_179[30 : 0];\n        ap_pipeline_reg_pp0_iter16_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter15_i_cast6_cast_reg_179[30 : 0];\n        ap_pipeline_reg_pp0_iter17_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter16_i_cast6_cast_reg_179[30 : 0];\n        ap_pipeline_reg_pp0_iter2_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter1_i_cast6_cast_reg_179[30 : 0];\n        ap_pipeline_reg_pp0_iter3_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter2_i_cast6_cast_reg_179[30 : 0];\n        ap_pipeline_reg_pp0_iter4_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter3_i_cast6_cast_reg_179[30 : 0];\n        ap_pipeline_reg_pp0_iter5_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter4_i_cast6_cast_reg_179[30 : 0];\n        ap_pipeline_reg_pp0_iter6_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter5_i_cast6_cast_reg_179[30 : 0];\n        ap_pipeline_reg_pp0_iter7_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter6_i_cast6_cast_reg_179[30 : 0];\n        ap_pipeline_reg_pp0_iter8_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter7_i_cast6_cast_reg_179[30 : 0];\n        ap_pipeline_reg_pp0_iter9_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter8_i_cast6_cast_reg_179[30 : 0];\n        dds_cos_V_reg_194 <= grp_process_r_fu_109_ap_return_0;\n        dds_sin_V_reg_199 <= grp_process_r_fu_109_ap_return_1;\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (((1'b1 == ap_CS_fsm_pp0_stage0) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))))) begin\n        ap_pipeline_reg_pp0_iter1_i_cast6_cast_reg_179[30 : 0] <= i_cast6_cast_reg_179[30 : 0];\n        i_cast6_cast_reg_179[30 : 0] <= i_cast6_cast_fu_126_p1[30 : 0];\n        tmp_reg_190 <= tmp_fu_140_p2;\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (((1'b1 == ap_CS_fsm_pp0_stage0) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))) & (1'b1 == ap_enable_reg_pp0_iter0))) begin\n        i_reg_185 <= i_fu_130_p2;\n    end\nend\n\nalways @ (*) begin\n    if ((((1'b0 == ap_start) & (ap_CS_fsm_state1 == 1'b1)) | (1'b1 == ap_CS_fsm_state27))) begin\n        ap_done = 1'b1;\n    end else begin\n        ap_done = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b0 == ap_start) & (ap_CS_fsm_state1 == 1'b1))) begin\n        ap_idle = 1'b1;\n    end else begin\n        ap_idle = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if ((1'b1 == ap_CS_fsm_state27)) begin\n        ap_ready = 1'b1;\n    end else begin\n        ap_ready = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if ((1'b0 == ap_reg_ioackin_m_axi_cos_out_V_AWREADY)) begin\n        ap_sig_ioackin_m_axi_cos_out_V_AWREADY = m_axi_cos_out_V_AWREADY;\n    end else begin\n        ap_sig_ioackin_m_axi_cos_out_V_AWREADY = 1'b1;\n    end\nend\n\nalways @ (*) begin\n    if ((1'b0 == ap_reg_ioackin_m_axi_cos_out_V_WREADY)) begin\n        ap_sig_ioackin_m_axi_cos_out_V_WREADY = m_axi_cos_out_V_WREADY;\n    end else begin\n        ap_sig_ioackin_m_axi_cos_out_V_WREADY = 1'b1;\n    end\nend\n\nalways @ (*) begin\n    if ((1'b0 == ap_reg_ioackin_m_axi_sin_out_V_AWREADY)) begin\n        ap_sig_ioackin_m_axi_sin_out_V_AWREADY = m_axi_sin_out_V_AWREADY;\n    end else begin\n        ap_sig_ioackin_m_axi_sin_out_V_AWREADY = 1'b1;\n    end\nend\n\nalways @ (*) begin\n    if ((1'b0 == ap_reg_ioackin_m_axi_sin_out_V_WREADY)) begin\n        ap_sig_ioackin_m_axi_sin_out_V_WREADY = m_axi_sin_out_V_WREADY;\n    end else begin\n        ap_sig_ioackin_m_axi_sin_out_V_WREADY = 1'b1;\n    end\nend\n\nalways @ (*) begin\n    if ((1'b1 == ap_enable_reg_pp0_iter18)) begin\n        cos_out_V_blk_n_AW = m_axi_cos_out_V_AWREADY;\n    end else begin\n        cos_out_V_blk_n_AW = 1'b1;\n    end\nend\n\nalways @ (*) begin\n    if ((1'b1 == ap_enable_reg_pp0_iter24)) begin\n        cos_out_V_blk_n_B = m_axi_cos_out_V_BVALID;\n    end else begin\n        cos_out_V_blk_n_B = 1'b1;\n    end\nend\n\nalways @ (*) begin\n    if ((1'b1 == ap_enable_reg_pp0_iter19)) begin\n        cos_out_V_blk_n_W = m_axi_cos_out_V_WREADY;\n    end else begin\n        cos_out_V_blk_n_W = 1'b1;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b1 == ap_CS_fsm_pp0_stage0) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))))) begin\n        grp_process_r_fu_109_ap_ce = 1'b1;\n    end else begin\n        grp_process_r_fu_109_ap_ce = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & ~(1'b0 == tmp_reg_190))) begin\n        i_cast6_phi_fu_102_p4 = i_reg_185;\n    end else begin\n        i_cast6_phi_fu_102_p4 = i_cast6_reg_98;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b1 == ap_enable_reg_pp0_iter18) & ~((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))) & (1'b0 == ap_reg_ioackin_m_axi_cos_out_V_AWREADY))) begin\n        m_axi_cos_out_V_AWVALID = 1'b1;\n    end else begin\n        m_axi_cos_out_V_AWVALID = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b1 == ap_enable_reg_pp0_iter24) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))))) begin\n        m_axi_cos_out_V_BREADY = 1'b1;\n    end else begin\n        m_axi_cos_out_V_BREADY = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b1 == ap_enable_reg_pp0_iter19) & ~((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))) & (1'b0 == ap_reg_ioackin_m_axi_cos_out_V_WREADY))) begin\n        m_axi_cos_out_V_WVALID = 1'b1;\n    end else begin\n        m_axi_cos_out_V_WVALID = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b1 == ap_enable_reg_pp0_iter18) & ~((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))) & (1'b0 == ap_reg_ioackin_m_axi_sin_out_V_AWREADY))) begin\n        m_axi_sin_out_V_AWVALID = 1'b1;\n    end else begin\n        m_axi_sin_out_V_AWVALID = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b1 == ap_enable_reg_pp0_iter24) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))))) begin\n        m_axi_sin_out_V_BREADY = 1'b1;\n    end else begin\n        m_axi_sin_out_V_BREADY = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b1 == ap_enable_reg_pp0_iter19) & ~((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))) & (1'b0 == ap_reg_ioackin_m_axi_sin_out_V_WREADY))) begin\n        m_axi_sin_out_V_WVALID = 1'b1;\n    end else begin\n        m_axi_sin_out_V_WVALID = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if ((1'b1 == ap_enable_reg_pp0_iter18)) begin\n        sin_out_V_blk_n_AW = m_axi_sin_out_V_AWREADY;\n    end else begin\n        sin_out_V_blk_n_AW = 1'b1;\n    end\nend\n\nalways @ (*) begin\n    if ((1'b1 == ap_enable_reg_pp0_iter24)) begin\n        sin_out_V_blk_n_B = m_axi_sin_out_V_BVALID;\n    end else begin\n        sin_out_V_blk_n_B = 1'b1;\n    end\nend\n\nalways @ (*) begin\n    if ((1'b1 == ap_enable_reg_pp0_iter19)) begin\n        sin_out_V_blk_n_W = m_axi_sin_out_V_WREADY;\n    end else begin\n        sin_out_V_blk_n_W = 1'b1;\n    end\nend\n\nalways @ (*) begin\n    case (ap_CS_fsm)\n        ap_ST_fsm_state1 : begin\n            if ((~(ap_start == 1'b0) & ~(1'b0 == tmp4_fu_120_p2))) begin\n                ap_NS_fsm = ap_ST_fsm_pp0_stage0;\n            end else if ((~(ap_start == 1'b0) & (1'b0 == tmp4_fu_120_p2))) begin\n                ap_NS_fsm = ap_ST_fsm_state27;\n            end else begin\n                ap_NS_fsm = ap_ST_fsm_state1;\n            end\n        end\n        ap_ST_fsm_pp0_stage0 : begin\n            if (~((1'b1 == ap_enable_reg_pp0_iter24) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))) & ~(1'b1 == ap_enable_reg_pp0_iter23))) begin\n                ap_NS_fsm = ap_ST_fsm_pp0_stage0;\n            end else if (((1'b1 == ap_enable_reg_pp0_iter24) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))) & ~(1'b1 == ap_enable_reg_pp0_iter23))) begin\n                ap_NS_fsm = ap_ST_fsm_state27;\n            end else begin\n                ap_NS_fsm = ap_ST_fsm_pp0_stage0;\n            end\n        end\n        ap_ST_fsm_state27 : begin\n            ap_NS_fsm = ap_ST_fsm_state1;\n        end\n        default : begin\n            ap_NS_fsm = 'bx;\n        end\n    endcase\nend\n\nassign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[ap_const_lv32_1];\n\nassign ap_CS_fsm_state1 = ap_CS_fsm[ap_const_lv32_0];\n\nassign ap_CS_fsm_state27 = ap_CS_fsm[ap_const_lv32_2];\n\nalways @ (*) begin\n    ap_condition_182 = ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))));\nend\n\nalways @ (*) begin\n    ap_condition_425 = ((1'b1 == m_axi_cos_out_V_AWREADY) & ~((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))));\nend\n\nalways @ (*) begin\n    ap_condition_431 = (~((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))) & (1'b1 == m_axi_cos_out_V_WREADY));\nend\n\nalways @ (*) begin\n    ap_condition_434 = (~((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))) & (1'b1 == m_axi_sin_out_V_AWREADY));\nend\n\nalways @ (*) begin\n    ap_condition_437 = (~((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))) & (1'b1 == m_axi_sin_out_V_WREADY));\nend\n\nassign grp_process_r_fu_109_ap_start = ap_reg_grp_process_r_fu_109_ap_start;\n\nassign i_cast6_cast_fu_126_p1 = i_cast6_phi_fu_102_p4;\n\nassign i_cast_fu_136_p1 = i_fu_130_p2;\n\nassign i_fu_130_p2 = (i_cast6_phi_fu_102_p4 + ap_const_lv31_1);\n\nassign m_axi_cos_out_V_ARADDR = ap_const_lv32_0;\n\nassign m_axi_cos_out_V_ARBURST = ap_const_lv2_0;\n\nassign m_axi_cos_out_V_ARCACHE = ap_const_lv4_0;\n\nassign m_axi_cos_out_V_ARID = 1'b0;\n\nassign m_axi_cos_out_V_ARLEN = ap_const_lv32_0;\n\nassign m_axi_cos_out_V_ARLOCK = ap_const_lv2_0;\n\nassign m_axi_cos_out_V_ARPROT = ap_const_lv3_0;\n\nassign m_axi_cos_out_V_ARQOS = ap_const_lv4_0;\n\nassign m_axi_cos_out_V_ARREGION = ap_const_lv4_0;\n\nassign m_axi_cos_out_V_ARSIZE = ap_const_lv3_0;\n\nassign m_axi_cos_out_V_ARUSER = 1'b0;\n\nassign m_axi_cos_out_V_ARVALID = 1'b0;\n\nassign m_axi_cos_out_V_AWADDR = ap_pipeline_reg_pp0_iter17_i_cast6_cast_reg_179;\n\nassign m_axi_cos_out_V_AWBURST = ap_const_lv2_0;\n\nassign m_axi_cos_out_V_AWCACHE = ap_const_lv4_0;\n\nassign m_axi_cos_out_V_AWID = 1'b0;\n\nassign m_axi_cos_out_V_AWLEN = ap_const_lv32_1;\n\nassign m_axi_cos_out_V_AWLOCK = ap_const_lv2_0;\n\nassign m_axi_cos_out_V_AWPROT = ap_const_lv3_0;\n\nassign m_axi_cos_out_V_AWQOS = ap_const_lv4_0;\n\nassign m_axi_cos_out_V_AWREGION = ap_const_lv4_0;\n\nassign m_axi_cos_out_V_AWSIZE = ap_const_lv3_0;\n\nassign m_axi_cos_out_V_AWUSER = 1'b0;\n\nassign m_axi_cos_out_V_RREADY = 1'b0;\n\nassign m_axi_cos_out_V_WDATA = dds_cos_V_reg_194;\n\nassign m_axi_cos_out_V_WID = 1'b0;\n\nassign m_axi_cos_out_V_WLAST = 1'b0;\n\nassign m_axi_cos_out_V_WSTRB = ap_const_lv2_3;\n\nassign m_axi_cos_out_V_WUSER = 1'b0;\n\nassign m_axi_sin_out_V_ARADDR = ap_const_lv32_0;\n\nassign m_axi_sin_out_V_ARBURST = ap_const_lv2_0;\n\nassign m_axi_sin_out_V_ARCACHE = ap_const_lv4_0;\n\nassign m_axi_sin_out_V_ARID = 1'b0;\n\nassign m_axi_sin_out_V_ARLEN = ap_const_lv32_0;\n\nassign m_axi_sin_out_V_ARLOCK = ap_const_lv2_0;\n\nassign m_axi_sin_out_V_ARPROT = ap_const_lv3_0;\n\nassign m_axi_sin_out_V_ARQOS = ap_const_lv4_0;\n\nassign m_axi_sin_out_V_ARREGION = ap_const_lv4_0;\n\nassign m_axi_sin_out_V_ARSIZE = ap_const_lv3_0;\n\nassign m_axi_sin_out_V_ARUSER = 1'b0;\n\nassign m_axi_sin_out_V_ARVALID = 1'b0;\n\nassign m_axi_sin_out_V_AWADDR = ap_pipeline_reg_pp0_iter17_i_cast6_cast_reg_179;\n\nassign m_axi_sin_out_V_AWBURST = ap_const_lv2_0;\n\nassign m_axi_sin_out_V_AWCACHE = ap_const_lv4_0;\n\nassign m_axi_sin_out_V_AWID = 1'b0;\n\nassign m_axi_sin_out_V_AWLEN = ap_const_lv32_1;\n\nassign m_axi_sin_out_V_AWLOCK = ap_const_lv2_0;\n\nassign m_axi_sin_out_V_AWPROT = ap_const_lv3_0;\n\nassign m_axi_sin_out_V_AWQOS = ap_const_lv4_0;\n\nassign m_axi_sin_out_V_AWREGION = ap_const_lv4_0;\n\nassign m_axi_sin_out_V_AWSIZE = ap_const_lv3_0;\n\nassign m_axi_sin_out_V_AWUSER = 1'b0;\n\nassign m_axi_sin_out_V_RREADY = 1'b0;\n\nassign m_axi_sin_out_V_WDATA = dds_sin_V_reg_199;\n\nassign m_axi_sin_out_V_WID = 1'b0;\n\nassign m_axi_sin_out_V_WLAST = 1'b0;\n\nassign m_axi_sin_out_V_WSTRB = ap_const_lv2_3;\n\nassign m_axi_sin_out_V_WUSER = 1'b0;\n\nassign tmp4_fu_120_p2 = (($signed(nofSample) > $signed(32'b00000000000000000000000000000000)) ? 1'b1 : 1'b0);\n\nassign tmp_fu_140_p2 = (($signed(i_cast_fu_136_p1) < $signed(nofSample)) ? 1'b1 : 1'b0);\n\nalways @ (posedge ap_clk) begin\n    i_cast6_cast_reg_179[31] <= 1'b0;\n    ap_pipeline_reg_pp0_iter1_i_cast6_cast_reg_179[31] <= 1'b0;\n    ap_pipeline_reg_pp0_iter2_i_cast6_cast_reg_179[31] <= 1'b0;\n    ap_pipeline_reg_pp0_iter3_i_cast6_cast_reg_179[31] <= 1'b0;\n    ap_pipeline_reg_pp0_iter4_i_cast6_cast_reg_179[31] <= 1'b0;\n    ap_pipeline_reg_pp0_iter5_i_cast6_cast_reg_179[31] <= 1'b0;\n    ap_pipeline_reg_pp0_iter6_i_cast6_cast_reg_179[31] <= 1'b0;\n    ap_pipeline_reg_pp0_iter7_i_cast6_cast_reg_179[31] <= 1'b0;\n    ap_pipeline_reg_pp0_iter8_i_cast6_cast_reg_179[31] <= 1'b0;\n    ap_pipeline_reg_pp0_iter9_i_cast6_cast_reg_179[31] <= 1'b0;\n    ap_pipeline_reg_pp0_iter10_i_cast6_cast_reg_179[31] <= 1'b0;\n    ap_pipeline_reg_pp0_iter11_i_cast6_cast_reg_179[31] <= 1'b0;\n    ap_pipeline_reg_pp0_iter12_i_cast6_cast_reg_179[31] <= 1'b0;\n    ap_pipeline_reg_pp0_iter13_i_cast6_cast_reg_179[31] <= 1'b0;\n    ap_pipeline_reg_pp0_iter14_i_cast6_cast_reg_179[31] <= 1'b0;\n    ap_pipeline_reg_pp0_iter15_i_cast6_cast_reg_179[31] <= 1'b0;\n    ap_pipeline_reg_pp0_iter16_i_cast6_cast_reg_179[31] <= 1'b0;\n    ap_pipeline_reg_pp0_iter17_i_cast6_cast_reg_179[31] <= 1'b0;\nend\n\nendmodule //process_frame\n", "num_lines": 1118}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// ==============================================================\n// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC\n// Version: 2016.3\n// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.\n// \n// ===========================================================\n\n`timescale 1 ns / 1 ps \n\nmodule process_r (\n        ap_clk,\n        ap_rst,\n        ap_start,\n        ap_done,\n        ap_idle,\n        ap_ready,\n        ap_ce,\n        incr_V,\n        ap_return_0,\n        ap_return_1\n);\n\nparameter    ap_ST_fsm_pp0_stage0 = 1'b1;\nparameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;\nparameter    ap_const_lv32_1E = 32'b11110;\nparameter    ap_const_lv32_1F = 32'b11111;\nparameter    ap_const_lv32_14 = 32'b10100;\nparameter    ap_const_lv32_1D = 32'b11101;\nparameter    ap_const_lv32_B = 32'b1011;\nparameter    ap_const_lv32_13 = 32'b10011;\nparameter    ap_const_lv10_0 = 10'b0000000000;\nparameter    ap_const_lv18_0 = 18'b000000000000000000;\nparameter    ap_const_lv32_11 = 32'b10001;\nparameter    ap_const_lv2_0 = 2'b00;\nparameter    ap_const_lv2_1 = 2'b1;\nparameter    ap_const_lv2_3 = 2'b11;\nparameter    ap_const_lv17_0 = 17'b00000000000000000;\nparameter    ap_const_lv18_1FFFF = 18'b11111111111111111;\nparameter    ap_const_lv18_20001 = 18'b100000000000000001;\nparameter    ap_const_lv25_0 = 25'b0000000000000000000000000;\nparameter    ap_const_lv32_2B = 32'b101011;\nparameter    ap_const_lv32_2A = 32'b101010;\nparameter    ap_const_lv26_0 = 26'b00000000000000000000000000;\nparameter    ap_const_lv32_1B = 32'b11011;\nparameter    ap_const_lv32_1A = 32'b11010;\nparameter    ap_const_lv32_F = 32'b1111;\nparameter    ap_const_lv15_0 = 15'b000000000000000;\nparameter    ap_const_lv16_7FFF = 16'b111111111111111;\nparameter    ap_const_lv16_8001 = 16'b1000000000000001;\n\ninput   ap_clk;\ninput   ap_rst;\ninput   ap_start;\noutput   ap_done;\noutput   ap_idle;\noutput   ap_ready;\ninput   ap_ce;\ninput  [31:0] incr_V;\noutput  [15:0] ap_return_0;\noutput  [15:0] ap_return_1;\n\nreg ap_done;\nreg ap_idle;\nreg ap_ready;\n\n(* fsm_encoding = \"none\" *) reg   [0:0] ap_CS_fsm;\nwire   [0:0] ap_CS_fsm_pp0_stage0;\nwire    ap_enable_reg_pp0_iter0;\nreg    ap_enable_reg_pp0_iter1;\nreg    ap_enable_reg_pp0_iter2;\nreg    ap_enable_reg_pp0_iter3;\nreg    ap_enable_reg_pp0_iter4;\nreg    ap_enable_reg_pp0_iter5;\nreg    ap_enable_reg_pp0_iter6;\nreg    ap_enable_reg_pp0_iter7;\nreg    ap_enable_reg_pp0_iter8;\nreg    ap_enable_reg_pp0_iter9;\nreg    ap_enable_reg_pp0_iter10;\nreg    ap_enable_reg_pp0_iter11;\nreg    ap_enable_reg_pp0_iter12;\nreg    ap_enable_reg_pp0_iter13;\nreg    ap_enable_reg_pp0_iter14;\nreg    ap_enable_reg_pp0_iter15;\nreg    ap_enable_reg_pp0_iter16;\nreg    ap_enable_reg_pp0_iter17;\nreg   [31:0] dds_0_acc_V;\nwire   [9:0] dds_0_cos_lut_V_address0;\nreg    dds_0_cos_lut_V_ce0;\nwire   [16:0] dds_0_cos_lut_V_q0;\nwire   [9:0] dds_0_cos_lut_V_address1;\nreg    dds_0_cos_lut_V_ce1;\nwire   [16:0] dds_0_cos_lut_V_q1;\nwire   [8:0] dds_0_fine_lut_V_address0;\nreg    dds_0_fine_lut_V_ce0;\nwire   [15:0] dds_0_fine_lut_V_q0;\nreg   [1:0] msb_V_reg_952;\nreg   [1:0] ap_pipeline_reg_pp0_iter1_msb_V_reg_952;\nreg   [1:0] ap_pipeline_reg_pp0_iter2_msb_V_reg_952;\nreg   [1:0] ap_pipeline_reg_pp0_iter3_msb_V_reg_952;\nreg   [1:0] ap_pipeline_reg_pp0_iter4_msb_V_reg_952;\nreg   [9:0] lsb_V_reg_959;\nreg   [9:0] ap_pipeline_reg_pp0_iter1_lsb_V_reg_959;\nreg   [8:0] p_Result_8_reg_966;\nreg   [8:0] ap_pipeline_reg_pp0_iter1_p_Result_8_reg_966;\nreg   [8:0] ap_pipeline_reg_pp0_iter2_p_Result_8_reg_966;\nreg   [8:0] ap_pipeline_reg_pp0_iter3_p_Result_8_reg_966;\nreg   [8:0] ap_pipeline_reg_pp0_iter4_p_Result_8_reg_966;\nreg   [8:0] ap_pipeline_reg_pp0_iter5_p_Result_8_reg_966;\nreg   [8:0] ap_pipeline_reg_pp0_iter6_p_Result_8_reg_966;\nwire   [9:0] sin_adr_V_fu_169_p2;\nreg   [9:0] sin_adr_V_reg_971;\nwire   [0:0] tmp_2_fu_178_p2;\nreg   [0:0] tmp_2_reg_981;\nreg   [0:0] ap_pipeline_reg_pp0_iter3_tmp_2_reg_981;\nreg   [0:0] ap_pipeline_reg_pp0_iter4_tmp_2_reg_981;\nreg   [0:0] ap_pipeline_reg_pp0_iter5_tmp_2_reg_981;\nreg   [16:0] p_Val2_6_reg_996;\nreg   [16:0] p_Val2_4_reg_1001;\nreg   [16:0] ap_pipeline_reg_pp0_iter4_p_Val2_4_reg_1001;\nreg   [16:0] ap_pipeline_reg_pp0_iter5_p_Val2_4_reg_1001;\nwire   [17:0] dds_0_cos_lut_V_load_fu_187_p1;\nreg   [17:0] dds_0_cos_lut_V_load_reg_1007;\nreg   [17:0] ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_reg_1007;\nreg   [17:0] ap_pipeline_reg_pp0_iter6_dds_0_cos_lut_V_load_reg_1007;\nwire   [17:0] dds_0_cos_lut_V_load_2_fu_190_p1;\nreg   [17:0] dds_0_cos_lut_V_load_2_reg_1014;\nreg   [17:0] ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_2_reg_1014;\nwire   [17:0] p_Val2_5_fu_193_p2;\nreg   [17:0] p_Val2_5_reg_1019;\nreg   [17:0] ap_pipeline_reg_pp0_iter5_p_Val2_5_reg_1019;\nreg   [0:0] isneg_reg_1025;\nwire   [17:0] p_Val2_7_fu_207_p2;\nreg   [17:0] p_Val2_7_reg_1030;\nreg   [17:0] ap_pipeline_reg_pp0_iter5_p_Val2_7_reg_1030;\nreg   [17:0] ap_pipeline_reg_pp0_iter6_p_Val2_7_reg_1030;\nreg   [0:0] isneg_1_reg_1036;\nwire   [16:0] tmp_27_fu_221_p1;\nreg   [16:0] tmp_27_reg_1041;\nwire   [16:0] tmp_28_fu_225_p1;\nreg   [16:0] tmp_28_reg_1046;\nwire   [0:0] tmp_s_fu_229_p2;\nreg   [0:0] tmp_s_reg_1051;\nwire   [0:0] tmp_3_fu_234_p2;\nreg   [0:0] tmp_3_reg_1058;\nwire   [0:0] tmp_6_fu_239_p2;\nreg   [0:0] tmp_6_reg_1063;\nwire   [0:0] underflow_fu_249_p2;\nreg   [0:0] underflow_reg_1069;\nwire   [0:0] underflow_1_fu_259_p2;\nreg   [0:0] underflow_1_reg_1076;\nreg   [0:0] ap_pipeline_reg_pp0_iter6_underflow_1_reg_1076;\nwire   [0:0] sel_tmp1_fu_264_p2;\nreg   [0:0] sel_tmp1_reg_1084;\nwire   [0:0] sel_tmp18_demorgan_fu_269_p2;\nreg   [0:0] sel_tmp18_demorgan_reg_1090;\nwire   [17:0] p_Val2_74_mux_fu_280_p3;\nreg   [17:0] p_Val2_74_mux_reg_1096;\nwire   [16:0] p_Val2_0_i_i_fu_286_p3;\nreg   [16:0] p_Val2_0_i_i_reg_1101;\nwire   [17:0] p_Val2_1_fu_303_p3;\nreg   [17:0] p_Val2_1_reg_1106;\nreg   [17:0] ap_pipeline_reg_pp0_iter7_p_Val2_1_reg_1106;\nwire   [17:0] p_Val2_0_i_i1_fu_321_p3;\nreg   [17:0] p_Val2_0_i_i1_reg_1114;\nwire   [0:0] sel_tmp9_fu_329_p2;\nreg   [0:0] sel_tmp9_reg_1119;\nwire   [0:0] sel_tmp5_fu_338_p2;\nreg   [0:0] sel_tmp5_reg_1124;\nwire   [0:0] sel_tmp7_fu_343_p2;\nreg   [0:0] sel_tmp7_reg_1129;\nwire   [0:0] sel_tmp12_fu_357_p2;\nreg   [0:0] sel_tmp12_reg_1134;\nwire   [0:0] sel_tmp14_fu_362_p2;\nreg   [0:0] sel_tmp14_reg_1140;\nreg   [0:0] ap_pipeline_reg_pp0_iter7_sel_tmp14_reg_1140;\nwire   [0:0] sel_tmp17_fu_378_p2;\nreg   [0:0] sel_tmp17_reg_1146;\nreg   [0:0] ap_pipeline_reg_pp0_iter7_sel_tmp17_reg_1146;\nwire   [0:0] sel_tmp20_fu_394_p2;\nreg   [0:0] sel_tmp20_reg_1152;\nreg   [0:0] ap_pipeline_reg_pp0_iter7_sel_tmp20_reg_1152;\nwire   [17:0] sel_tmp23_fu_414_p3;\nreg   [17:0] sel_tmp23_reg_1158;\nwire   [17:0] p_Val2_0_i_i_cast_fu_422_p1;\nreg   [17:0] p_Val2_0_i_i_cast_reg_1163;\nwire   [17:0] sel_tmp13_fu_448_p3;\nreg   [17:0] sel_tmp13_reg_1168;\nwire   [17:0] p_Val2_1_8_fu_474_p3;\nreg   [17:0] p_Val2_1_8_reg_1173;\nreg  signed [17:0] ap_pipeline_reg_pp0_iter8_p_Val2_1_8_reg_1173;\nreg   [17:0] ap_pipeline_reg_pp0_iter9_p_Val2_1_8_reg_1173;\nreg   [17:0] ap_pipeline_reg_pp0_iter10_p_Val2_1_8_reg_1173;\nwire   [17:0] p_Val2_8_fu_495_p3;\nreg  signed [17:0] p_Val2_8_reg_1184;\nreg   [17:0] ap_pipeline_reg_pp0_iter9_p_Val2_8_reg_1184;\nreg   [17:0] ap_pipeline_reg_pp0_iter10_p_Val2_8_reg_1184;\nreg   [15:0] fine_word_V_reg_1190;\nwire   [33:0] OP2_V_cast_fu_504_p1;\nwire  signed [43:0] grp_fu_930_p3;\nreg  signed [43:0] p_Val2_9_reg_1221;\nreg  signed [43:0] ap_pipeline_reg_pp0_iter13_p_Val2_9_reg_1221;\nreg   [0:0] signbit_reg_1228;\nreg   [0:0] ap_pipeline_reg_pp0_iter13_signbit_reg_1228;\nreg   [0:0] ap_pipeline_reg_pp0_iter14_signbit_reg_1228;\nreg   [0:0] ap_pipeline_reg_pp0_iter15_signbit_reg_1228;\nwire   [25:0] tmp_31_fu_539_p1;\nreg   [25:0] tmp_31_reg_1236;\nreg   [0:0] tmp_32_reg_1241;\nreg   [0:0] ap_pipeline_reg_pp0_iter13_tmp_32_reg_1241;\nreg   [0:0] ap_pipeline_reg_pp0_iter14_tmp_32_reg_1241;\nreg   [0:0] ap_pipeline_reg_pp0_iter15_tmp_32_reg_1241;\nwire  signed [43:0] grp_fu_941_p3;\nreg  signed [43:0] p_Val2_13_reg_1247;\nreg  signed [43:0] ap_pipeline_reg_pp0_iter13_p_Val2_13_reg_1247;\nreg   [0:0] signbit_1_reg_1254;\nreg   [0:0] ap_pipeline_reg_pp0_iter13_signbit_1_reg_1254;\nreg   [0:0] ap_pipeline_reg_pp0_iter14_signbit_1_reg_1254;\nreg   [0:0] ap_pipeline_reg_pp0_iter15_signbit_1_reg_1254;\nwire   [25:0] tmp_38_fu_556_p1;\nreg   [25:0] tmp_38_reg_1262;\nreg   [0:0] tmp_39_reg_1267;\nreg   [0:0] ap_pipeline_reg_pp0_iter13_tmp_39_reg_1267;\nreg   [0:0] ap_pipeline_reg_pp0_iter14_tmp_39_reg_1267;\nreg   [0:0] ap_pipeline_reg_pp0_iter15_tmp_39_reg_1267;\nwire   [0:0] r_fu_566_p2;\nreg   [0:0] r_reg_1273;\nwire   [0:0] r_1_fu_571_p2;\nreg   [0:0] r_1_reg_1278;\nwire   [15:0] p_Val2_11_fu_614_p2;\nreg   [15:0] p_Val2_11_reg_1283;\nreg   [15:0] ap_pipeline_reg_pp0_iter15_p_Val2_11_reg_1283;\nreg   [15:0] ap_pipeline_reg_pp0_iter16_p_Val2_11_reg_1283;\nreg   [0:0] newsignbit_reg_1289;\nreg   [0:0] ap_pipeline_reg_pp0_iter15_newsignbit_reg_1289;\nwire   [14:0] tmp_35_fu_628_p1;\nreg   [14:0] tmp_35_reg_1297;\nwire   [15:0] p_Val2_15_fu_670_p2;\nreg   [15:0] p_Val2_15_reg_1302;\nreg   [15:0] ap_pipeline_reg_pp0_iter15_p_Val2_15_reg_1302;\nreg   [15:0] ap_pipeline_reg_pp0_iter16_p_Val2_15_reg_1302;\nreg   [0:0] newsignbit_1_reg_1308;\nreg   [0:0] ap_pipeline_reg_pp0_iter15_newsignbit_1_reg_1308;\nwire   [14:0] tmp_42_fu_684_p1;\nreg   [14:0] tmp_42_reg_1316;\nwire   [0:0] overflow_fu_720_p2;\nreg   [0:0] overflow_reg_1321;\nreg   [0:0] ap_pipeline_reg_pp0_iter16_overflow_reg_1321;\nwire   [0:0] tmp_16_fu_742_p2;\nreg   [0:0] tmp_16_reg_1327;\nwire   [0:0] overflow_1_fu_780_p2;\nreg   [0:0] overflow_1_reg_1332;\nreg   [0:0] ap_pipeline_reg_pp0_iter16_overflow_1_reg_1332;\nwire   [0:0] tmp_24_fu_802_p2;\nreg   [0:0] tmp_24_reg_1338;\nwire   [0:0] underflow_2_fu_823_p2;\nreg   [0:0] underflow_2_reg_1343;\nwire   [0:0] underflow_3_fu_843_p2;\nreg   [0:0] underflow_3_reg_1350;\nwire   [31:0] tmp_1_fu_174_p1;\nwire   [31:0] tmp_4_fu_183_p1;\nwire   [31:0] tmp_8_fu_480_p1;\nwire   [31:0] p_Val2_3_fu_127_p2;\nwire   [0:0] tmp_5_fu_244_p2;\nwire   [0:0] tmp_7_fu_254_p2;\nwire   [17:0] p_Val2_s_7_fu_297_p3;\nwire   [0:0] underflow_12_not_fu_275_p2;\nwire   [0:0] sel_tmp2_fu_316_p2;\nwire   [17:0] sel_tmp_fu_309_p3;\nwire   [0:0] sel_tmp4_fu_333_p2;\nwire   [0:0] sel_tmp10_fu_347_p2;\nwire   [0:0] sel_tmp11_fu_352_p2;\nwire   [0:0] underflow_14_not_fu_292_p2;\nwire   [0:0] sel_tmp33_demorgan_fu_368_p2;\nwire   [0:0] sel_tmp16_fu_372_p2;\nwire   [0:0] sel_tmp42_demorgan_fu_383_p2;\nwire   [0:0] sel_tmp19_fu_388_p2;\nwire   [17:0] sel_tmp21_fu_400_p3;\nwire   [17:0] sel_tmp22_fu_407_p3;\nwire   [17:0] sel_tmp3_fu_431_p3;\nwire   [17:0] sel_tmp6_fu_436_p3;\nwire   [17:0] sel_tmp8_fu_442_p3;\nwire   [17:0] p_Val2_77_mux_fu_425_p3;\nwire   [17:0] sel_tmp24_fu_455_p3;\nwire   [17:0] sel_tmp25_fu_460_p3;\nwire   [17:0] sel_tmp26_fu_467_p3;\nwire   [17:0] sel_tmp15_fu_484_p3;\nwire   [17:0] sel_tmp18_fu_489_p3;\nwire  signed [42:0] tmp_9_fu_510_p3;\nwire  signed [42:0] tmp_17_fu_521_p3;\nwire   [0:0] tmp_33_fu_592_p3;\nwire   [0:0] r_i_i_fu_599_p2;\nwire   [0:0] qbit_fu_585_p3;\nwire   [0:0] qb_assign_1_fu_604_p2;\nwire   [15:0] tmp_11_fu_610_p1;\nwire   [15:0] p_Val2_10_fu_576_p4;\nwire   [0:0] tmp_40_fu_648_p3;\nwire   [0:0] r_i_i1_fu_655_p2;\nwire   [0:0] qbit_1_fu_641_p3;\nwire   [0:0] qb_assign_3_fu_660_p2;\nwire   [15:0] tmp_19_fu_666_p1;\nwire   [15:0] p_Val2_14_fu_632_p4;\nwire   [0:0] tmp_12_fu_688_p2;\nwire   [0:0] carry_fu_693_p2;\nwire   [0:0] tmp_13_fu_698_p2;\nwire   [0:0] p_not_i_fu_710_p2;\nwire   [0:0] brmerge_i4_fu_715_p2;\nwire   [0:0] deleted_ones_fu_703_p3;\nwire   [0:0] brmerge40_demorgan_i_fu_726_p2;\nwire   [0:0] tmp_15_fu_737_p2;\nwire   [0:0] brmerge40_i_fu_731_p2;\nwire   [0:0] tmp_20_fu_748_p2;\nwire   [0:0] carry_1_fu_753_p2;\nwire   [0:0] tmp_21_fu_758_p2;\nwire   [0:0] p_not_i1_fu_770_p2;\nwire   [0:0] brmerge_i5_fu_775_p2;\nwire   [0:0] deleted_ones_1_fu_763_p3;\nwire   [0:0] brmerge40_demorgan_i_1_fu_786_p2;\nwire   [0:0] tmp_23_fu_797_p2;\nwire   [0:0] brmerge40_i1_fu_791_p2;\nwire   [0:0] p_Result_2_not_fu_808_p2;\nwire   [0:0] tmp_14_fu_813_p2;\nwire   [0:0] tmp_fu_818_p2;\nwire   [0:0] p_Result_11_not_fu_828_p2;\nwire   [0:0] tmp_22_fu_833_p2;\nwire   [0:0] tmp9_fu_838_p2;\nwire   [0:0] underflow_16_not_fu_852_p2;\nwire   [0:0] brmerge_i_i4_fu_848_p2;\nwire   [0:0] brmerge6_fu_857_p2;\nwire   [15:0] p_Val2_87_mux_fu_862_p3;\nwire   [15:0] p_Val2_4_9_fu_869_p3;\nwire   [0:0] underflow_17_not_fu_887_p2;\nwire   [0:0] brmerge_i_i5_fu_883_p2;\nwire   [0:0] brmerge7_fu_892_p2;\nwire   [15:0] p_Val2_91_mux_fu_897_p3;\nwire   [15:0] p_Val2_5_10_fu_904_p3;\nwire   [15:0] cos_dds_V_fu_875_p3;\nwire   [15:0] sin_dds_V_fu_910_p3;\nwire   [15:0] grp_fu_930_p1;\nwire   [15:0] grp_fu_941_p0;\nreg    grp_fu_930_ce;\nreg    grp_fu_941_ce;\nreg   [0:0] ap_NS_fsm;\nreg    ap_pipeline_idle_pp0;\n\n// power-on initialization\ninitial begin\n#0 ap_CS_fsm = 1'b1;\n#0 ap_enable_reg_pp0_iter1 = 1'b0;\n#0 ap_enable_reg_pp0_iter2 = 1'b0;\n#0 ap_enable_reg_pp0_iter3 = 1'b0;\n#0 ap_enable_reg_pp0_iter4 = 1'b0;\n#0 ap_enable_reg_pp0_iter5 = 1'b0;\n#0 ap_enable_reg_pp0_iter6 = 1'b0;\n#0 ap_enable_reg_pp0_iter7 = 1'b0;\n#0 ap_enable_reg_pp0_iter8 = 1'b0;\n#0 ap_enable_reg_pp0_iter9 = 1'b0;\n#0 ap_enable_reg_pp0_iter10 = 1'b0;\n#0 ap_enable_reg_pp0_iter11 = 1'b0;\n#0 ap_enable_reg_pp0_iter12 = 1'b0;\n#0 ap_enable_reg_pp0_iter13 = 1'b0;\n#0 ap_enable_reg_pp0_iter14 = 1'b0;\n#0 ap_enable_reg_pp0_iter15 = 1'b0;\n#0 ap_enable_reg_pp0_iter16 = 1'b0;\n#0 ap_enable_reg_pp0_iter17 = 1'b0;\n#0 dds_0_acc_V = 32'b00000000000000000000000000000000;\nend\n\nprocess_r_dds_0_cbkb #(\n    .DataWidth( 17 ),\n    .AddressRange( 1024 ),\n    .AddressWidth( 10 ))\ndds_0_cos_lut_V_U(\n    .clk(ap_clk),\n    .reset(ap_rst),\n    .address0(dds_0_cos_lut_V_address0),\n    .ce0(dds_0_cos_lut_V_ce0),\n    .q0(dds_0_cos_lut_V_q0),\n    .address1(dds_0_cos_lut_V_address1),\n    .ce1(dds_0_cos_lut_V_ce1),\n    .q1(dds_0_cos_lut_V_q1)\n);\n\nprocess_r_dds_0_fcud #(\n    .DataWidth( 16 ),\n    .AddressRange( 512 ),\n    .AddressWidth( 9 ))\ndds_0_fine_lut_V_U(\n    .clk(ap_clk),\n    .reset(ap_rst),\n    .address0(dds_0_fine_lut_V_address0),\n    .ce0(dds_0_fine_lut_V_ce0),\n    .q0(dds_0_fine_lut_V_q0)\n);\n\ndds_mac_mulsub_18dEe #(\n    .ID( 1 ),\n    .NUM_STAGE( 4 ),\n    .din0_WIDTH( 18 ),\n    .din1_WIDTH( 16 ),\n    .din2_WIDTH( 43 ),\n    .dout_WIDTH( 44 ))\ndds_mac_mulsub_18dEe_U0(\n    .clk(ap_clk),\n    .reset(ap_rst),\n    .din0(ap_pipeline_reg_pp0_iter8_p_Val2_1_8_reg_1173),\n    .din1(grp_fu_930_p1),\n    .din2(tmp_9_fu_510_p3),\n    .ce(grp_fu_930_ce),\n    .dout(grp_fu_930_p3)\n);\n\ndds_mac_muladd_16eOg #(\n    .ID( 1 ),\n    .NUM_STAGE( 4 ),\n    .din0_WIDTH( 16 ),\n    .din1_WIDTH( 18 ),\n    .din2_WIDTH( 43 ),\n    .dout_WIDTH( 44 ))\ndds_mac_muladd_16eOg_U1(\n    .clk(ap_clk),\n    .reset(ap_rst),\n    .din0(grp_fu_941_p0),\n    .din1(p_Val2_8_reg_1184),\n    .din2(tmp_17_fu_521_p3),\n    .ce(grp_fu_941_ce),\n    .dout(grp_fu_941_p3)\n);\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_CS_fsm <= ap_ST_fsm_pp0_stage0;\n    end else begin\n        ap_CS_fsm <= ap_NS_fsm;\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter1 <= 1'b0;\n    end else begin\n        if (((ap_CS_fsm_pp0_stage0 == 1'b1) & ~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce)))) begin\n            ap_enable_reg_pp0_iter1 <= ap_start;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter10 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin\n            ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter11 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin\n            ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter12 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin\n            ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter13 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin\n            ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter14 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin\n            ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter15 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin\n            ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter16 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin\n            ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter17 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin\n            ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter2 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin\n            ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter3 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin\n            ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter4 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin\n            ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter5 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin\n            ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter6 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin\n            ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter7 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin\n            ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter8 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin\n            ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_enable_reg_pp0_iter9 <= 1'b0;\n    end else begin\n        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin\n            ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if ((~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce))) begin\n        ap_pipeline_reg_pp0_iter10_p_Val2_1_8_reg_1173 <= ap_pipeline_reg_pp0_iter9_p_Val2_1_8_reg_1173;\n        ap_pipeline_reg_pp0_iter10_p_Val2_8_reg_1184 <= ap_pipeline_reg_pp0_iter9_p_Val2_8_reg_1184;\n        ap_pipeline_reg_pp0_iter13_p_Val2_13_reg_1247 <= p_Val2_13_reg_1247;\n        ap_pipeline_reg_pp0_iter13_p_Val2_9_reg_1221 <= p_Val2_9_reg_1221;\n        ap_pipeline_reg_pp0_iter13_signbit_1_reg_1254 <= signbit_1_reg_1254;\n        ap_pipeline_reg_pp0_iter13_signbit_reg_1228 <= signbit_reg_1228;\n        ap_pipeline_reg_pp0_iter13_tmp_32_reg_1241 <= tmp_32_reg_1241;\n        ap_pipeline_reg_pp0_iter13_tmp_39_reg_1267 <= tmp_39_reg_1267;\n        ap_pipeline_reg_pp0_iter14_signbit_1_reg_1254 <= ap_pipeline_reg_pp0_iter13_signbit_1_reg_1254;\n        ap_pipeline_reg_pp0_iter14_signbit_reg_1228 <= ap_pipeline_reg_pp0_iter13_signbit_reg_1228;\n        ap_pipeline_reg_pp0_iter14_tmp_32_reg_1241 <= ap_pipeline_reg_pp0_iter13_tmp_32_reg_1241;\n        ap_pipeline_reg_pp0_iter14_tmp_39_reg_1267 <= ap_pipeline_reg_pp0_iter13_tmp_39_reg_1267;\n        ap_pipeline_reg_pp0_iter15_newsignbit_1_reg_1308 <= newsignbit_1_reg_1308;\n        ap_pipeline_reg_pp0_iter15_newsignbit_reg_1289 <= newsignbit_reg_1289;\n        ap_pipeline_reg_pp0_iter15_p_Val2_11_reg_1283 <= p_Val2_11_reg_1283;\n        ap_pipeline_reg_pp0_iter15_p_Val2_15_reg_1302 <= p_Val2_15_reg_1302;\n        ap_pipeline_reg_pp0_iter15_signbit_1_reg_1254 <= ap_pipeline_reg_pp0_iter14_signbit_1_reg_1254;\n        ap_pipeline_reg_pp0_iter15_signbit_reg_1228 <= ap_pipeline_reg_pp0_iter14_signbit_reg_1228;\n        ap_pipeline_reg_pp0_iter15_tmp_32_reg_1241 <= ap_pipeline_reg_pp0_iter14_tmp_32_reg_1241;\n        ap_pipeline_reg_pp0_iter15_tmp_39_reg_1267 <= ap_pipeline_reg_pp0_iter14_tmp_39_reg_1267;\n        ap_pipeline_reg_pp0_iter16_overflow_1_reg_1332 <= overflow_1_reg_1332;\n        ap_pipeline_reg_pp0_iter16_overflow_reg_1321 <= overflow_reg_1321;\n        ap_pipeline_reg_pp0_iter16_p_Val2_11_reg_1283 <= ap_pipeline_reg_pp0_iter15_p_Val2_11_reg_1283;\n        ap_pipeline_reg_pp0_iter16_p_Val2_15_reg_1302 <= ap_pipeline_reg_pp0_iter15_p_Val2_15_reg_1302;\n        ap_pipeline_reg_pp0_iter2_msb_V_reg_952 <= ap_pipeline_reg_pp0_iter1_msb_V_reg_952;\n        ap_pipeline_reg_pp0_iter2_p_Result_8_reg_966 <= ap_pipeline_reg_pp0_iter1_p_Result_8_reg_966;\n        ap_pipeline_reg_pp0_iter3_msb_V_reg_952 <= ap_pipeline_reg_pp0_iter2_msb_V_reg_952;\n        ap_pipeline_reg_pp0_iter3_p_Result_8_reg_966 <= ap_pipeline_reg_pp0_iter2_p_Result_8_reg_966;\n        ap_pipeline_reg_pp0_iter3_tmp_2_reg_981 <= tmp_2_reg_981;\n        ap_pipeline_reg_pp0_iter4_msb_V_reg_952 <= ap_pipeline_reg_pp0_iter3_msb_V_reg_952;\n        ap_pipeline_reg_pp0_iter4_p_Result_8_reg_966 <= ap_pipeline_reg_pp0_iter3_p_Result_8_reg_966;\n        ap_pipeline_reg_pp0_iter4_p_Val2_4_reg_1001 <= p_Val2_4_reg_1001;\n        ap_pipeline_reg_pp0_iter4_tmp_2_reg_981 <= ap_pipeline_reg_pp0_iter3_tmp_2_reg_981;\n        ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_2_reg_1014[16 : 0] <= dds_0_cos_lut_V_load_2_reg_1014[16 : 0];\n        ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_reg_1007[16 : 0] <= dds_0_cos_lut_V_load_reg_1007[16 : 0];\n        ap_pipeline_reg_pp0_iter5_p_Result_8_reg_966 <= ap_pipeline_reg_pp0_iter4_p_Result_8_reg_966;\n        ap_pipeline_reg_pp0_iter5_p_Val2_4_reg_1001 <= ap_pipeline_reg_pp0_iter4_p_Val2_4_reg_1001;\n        ap_pipeline_reg_pp0_iter5_p_Val2_5_reg_1019 <= p_Val2_5_reg_1019;\n        ap_pipeline_reg_pp0_iter5_p_Val2_7_reg_1030 <= p_Val2_7_reg_1030;\n        ap_pipeline_reg_pp0_iter5_tmp_2_reg_981 <= ap_pipeline_reg_pp0_iter4_tmp_2_reg_981;\n        ap_pipeline_reg_pp0_iter6_dds_0_cos_lut_V_load_reg_1007[16 : 0] <= ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_reg_1007[16 : 0];\n        ap_pipeline_reg_pp0_iter6_p_Result_8_reg_966 <= ap_pipeline_reg_pp0_iter5_p_Result_8_reg_966;\n        ap_pipeline_reg_pp0_iter6_p_Val2_7_reg_1030 <= ap_pipeline_reg_pp0_iter5_p_Val2_7_reg_1030;\n        ap_pipeline_reg_pp0_iter6_underflow_1_reg_1076 <= underflow_1_reg_1076;\n        ap_pipeline_reg_pp0_iter7_p_Val2_1_reg_1106 <= p_Val2_1_reg_1106;\n        ap_pipeline_reg_pp0_iter7_sel_tmp14_reg_1140 <= sel_tmp14_reg_1140;\n        ap_pipeline_reg_pp0_iter7_sel_tmp17_reg_1146 <= sel_tmp17_reg_1146;\n        ap_pipeline_reg_pp0_iter7_sel_tmp20_reg_1152 <= sel_tmp20_reg_1152;\n        ap_pipeline_reg_pp0_iter8_p_Val2_1_8_reg_1173 <= p_Val2_1_8_reg_1173;\n        ap_pipeline_reg_pp0_iter9_p_Val2_1_8_reg_1173 <= ap_pipeline_reg_pp0_iter8_p_Val2_1_8_reg_1173;\n        ap_pipeline_reg_pp0_iter9_p_Val2_8_reg_1184 <= p_Val2_8_reg_1184;\n        dds_0_cos_lut_V_load_2_reg_1014[16 : 0] <= dds_0_cos_lut_V_load_2_fu_190_p1[16 : 0];\n        dds_0_cos_lut_V_load_reg_1007[16 : 0] <= dds_0_cos_lut_V_load_fu_187_p1[16 : 0];\n        fine_word_V_reg_1190 <= dds_0_fine_lut_V_q0;\n        isneg_1_reg_1036 <= p_Val2_7_fu_207_p2[ap_const_lv32_11];\n        isneg_reg_1025 <= p_Val2_5_fu_193_p2[ap_const_lv32_11];\n        newsignbit_1_reg_1308 <= p_Val2_15_fu_670_p2[ap_const_lv32_F];\n        newsignbit_reg_1289 <= p_Val2_11_fu_614_p2[ap_const_lv32_F];\n        overflow_1_reg_1332 <= overflow_1_fu_780_p2;\n        overflow_reg_1321 <= overflow_fu_720_p2;\n        p_Val2_0_i_i1_reg_1114 <= p_Val2_0_i_i1_fu_321_p3;\n        p_Val2_0_i_i_reg_1101 <= p_Val2_0_i_i_fu_286_p3;\n        p_Val2_11_reg_1283 <= p_Val2_11_fu_614_p2;\n        p_Val2_15_reg_1302 <= p_Val2_15_fu_670_p2;\n        p_Val2_1_8_reg_1173 <= p_Val2_1_8_fu_474_p3;\n        p_Val2_1_reg_1106 <= p_Val2_1_fu_303_p3;\n        p_Val2_5_reg_1019 <= p_Val2_5_fu_193_p2;\n        p_Val2_74_mux_reg_1096 <= p_Val2_74_mux_fu_280_p3;\n        p_Val2_7_reg_1030 <= p_Val2_7_fu_207_p2;\n        p_Val2_8_reg_1184 <= p_Val2_8_fu_495_p3;\n        r_1_reg_1278 <= r_1_fu_571_p2;\n        r_reg_1273 <= r_fu_566_p2;\n        sel_tmp12_reg_1134 <= sel_tmp12_fu_357_p2;\n        sel_tmp14_reg_1140 <= sel_tmp14_fu_362_p2;\n        sel_tmp17_reg_1146 <= sel_tmp17_fu_378_p2;\n        sel_tmp18_demorgan_reg_1090 <= sel_tmp18_demorgan_fu_269_p2;\n        sel_tmp1_reg_1084 <= sel_tmp1_fu_264_p2;\n        sel_tmp20_reg_1152 <= sel_tmp20_fu_394_p2;\n        sel_tmp23_reg_1158 <= sel_tmp23_fu_414_p3;\n        sel_tmp5_reg_1124 <= sel_tmp5_fu_338_p2;\n        sel_tmp7_reg_1129 <= sel_tmp7_fu_343_p2;\n        sel_tmp9_reg_1119 <= sel_tmp9_fu_329_p2;\n        signbit_1_reg_1254 <= grp_fu_941_p3[ap_const_lv32_2B];\n        signbit_reg_1228 <= grp_fu_930_p3[ap_const_lv32_2B];\n        tmp_16_reg_1327 <= tmp_16_fu_742_p2;\n        tmp_24_reg_1338 <= tmp_24_fu_802_p2;\n        tmp_27_reg_1041 <= tmp_27_fu_221_p1;\n        tmp_28_reg_1046 <= tmp_28_fu_225_p1;\n        tmp_2_reg_981 <= tmp_2_fu_178_p2;\n        tmp_31_reg_1236 <= tmp_31_fu_539_p1;\n        tmp_32_reg_1241 <= grp_fu_930_p3[ap_const_lv32_2A];\n        tmp_35_reg_1297 <= tmp_35_fu_628_p1;\n        tmp_38_reg_1262 <= tmp_38_fu_556_p1;\n        tmp_39_reg_1267 <= grp_fu_941_p3[ap_const_lv32_2A];\n        tmp_3_reg_1058 <= tmp_3_fu_234_p2;\n        tmp_42_reg_1316 <= tmp_42_fu_684_p1;\n        tmp_6_reg_1063 <= tmp_6_fu_239_p2;\n        tmp_s_reg_1051 <= tmp_s_fu_229_p2;\n        underflow_1_reg_1076 <= underflow_1_fu_259_p2;\n        underflow_2_reg_1343 <= underflow_2_fu_823_p2;\n        underflow_3_reg_1350 <= underflow_3_fu_843_p2;\n        underflow_reg_1069 <= underflow_fu_249_p2;\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (((ap_CS_fsm_pp0_stage0 == 1'b1) & ~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce))) begin\n        ap_pipeline_reg_pp0_iter1_lsb_V_reg_959 <= lsb_V_reg_959;\n        ap_pipeline_reg_pp0_iter1_msb_V_reg_952 <= msb_V_reg_952;\n        ap_pipeline_reg_pp0_iter1_p_Result_8_reg_966 <= p_Result_8_reg_966;\n        lsb_V_reg_959 <= {{p_Val2_3_fu_127_p2[ap_const_lv32_1D : ap_const_lv32_14]}};\n        msb_V_reg_952 <= {{p_Val2_3_fu_127_p2[ap_const_lv32_1F : ap_const_lv32_1E]}};\n        p_Result_8_reg_966 <= {{p_Val2_3_fu_127_p2[ap_const_lv32_13 : ap_const_lv32_B]}};\n        sin_adr_V_reg_971 <= sin_adr_V_fu_169_p2;\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (((ap_CS_fsm_pp0_stage0 == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter0) & ~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce))) begin\n        dds_0_acc_V <= p_Val2_3_fu_127_p2;\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if ((~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce) & (sel_tmp17_reg_1146 == 1'b0) & (sel_tmp20_reg_1152 == 1'b0))) begin\n        p_Val2_0_i_i_cast_reg_1163[16 : 0] <= p_Val2_0_i_i_cast_fu_422_p1[16 : 0];\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if ((~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce) & (1'b1 == ap_enable_reg_pp0_iter12))) begin\n        p_Val2_13_reg_1247 <= grp_fu_941_p3;\n        p_Val2_9_reg_1221 <= grp_fu_930_p3;\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if ((~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce) & (1'b1 == ap_enable_reg_pp0_iter3))) begin\n        p_Val2_4_reg_1001 <= dds_0_cos_lut_V_q1;\n        p_Val2_6_reg_996 <= dds_0_cos_lut_V_q0;\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if ((~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce) & (sel_tmp17_reg_1146 == 1'b0) & (sel_tmp20_reg_1152 == 1'b0) & (sel_tmp14_reg_1140 == 1'b0))) begin\n        sel_tmp13_reg_1168 <= sel_tmp13_fu_448_p3;\n    end\nend\n\nalways @ (*) begin\n    if ((((1'b0 == ap_start) & (ap_CS_fsm_pp0_stage0 == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter0)) | (~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce) & (1'b1 == ap_enable_reg_pp0_iter17)))) begin\n        ap_done = 1'b1;\n    end else begin\n        ap_done = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b0 == ap_start) & (ap_CS_fsm_pp0_stage0 == 1'b1) & (1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1) & (1'b0 == ap_enable_reg_pp0_iter2) & (1'b0 == ap_enable_reg_pp0_iter3) & (1'b0 == ap_enable_reg_pp0_iter4) & (1'b0 == ap_enable_reg_pp0_iter5) & (1'b0 == ap_enable_reg_pp0_iter6) & (1'b0 == ap_enable_reg_pp0_iter7) & (1'b0 == ap_enable_reg_pp0_iter8) & (1'b0 == ap_enable_reg_pp0_iter9) & (1'b0 == ap_enable_reg_pp0_iter10) & (1'b0 == ap_enable_reg_pp0_iter11) & (1'b0 == ap_enable_reg_pp0_iter12) & (1'b0 == ap_enable_reg_pp0_iter13) & (1'b0 == ap_enable_reg_pp0_iter14) & (1'b0 == ap_enable_reg_pp0_iter15) & (1'b0 == ap_enable_reg_pp0_iter16) & (1'b0 == ap_enable_reg_pp0_iter17))) begin\n        ap_idle = 1'b1;\n    end else begin\n        ap_idle = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((1'b0 == ap_start) & (1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1) & (1'b0 == ap_enable_reg_pp0_iter2) & (1'b0 == ap_enable_reg_pp0_iter3) & (1'b0 == ap_enable_reg_pp0_iter4) & (1'b0 == ap_enable_reg_pp0_iter5) & (1'b0 == ap_enable_reg_pp0_iter6) & (1'b0 == ap_enable_reg_pp0_iter7) & (1'b0 == ap_enable_reg_pp0_iter8) & (1'b0 == ap_enable_reg_pp0_iter9) & (1'b0 == ap_enable_reg_pp0_iter10) & (1'b0 == ap_enable_reg_pp0_iter11) & (1'b0 == ap_enable_reg_pp0_iter12) & (1'b0 == ap_enable_reg_pp0_iter13) & (1'b0 == ap_enable_reg_pp0_iter14) & (1'b0 == ap_enable_reg_pp0_iter15) & (1'b0 == ap_enable_reg_pp0_iter16))) begin\n        ap_pipeline_idle_pp0 = 1'b1;\n    end else begin\n        ap_pipeline_idle_pp0 = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((ap_CS_fsm_pp0_stage0 == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter0) & ~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce))) begin\n        ap_ready = 1'b1;\n    end else begin\n        ap_ready = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if ((~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce) & (1'b1 == ap_enable_reg_pp0_iter2))) begin\n        dds_0_cos_lut_V_ce0 = 1'b1;\n    end else begin\n        dds_0_cos_lut_V_ce0 = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if ((~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce) & (1'b1 == ap_enable_reg_pp0_iter2))) begin\n        dds_0_cos_lut_V_ce1 = 1'b1;\n    end else begin\n        dds_0_cos_lut_V_ce1 = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if ((~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce) & (1'b1 == ap_enable_reg_pp0_iter7))) begin\n        dds_0_fine_lut_V_ce0 = 1'b1;\n    end else begin\n        dds_0_fine_lut_V_ce0 = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((ap_CS_fsm_pp0_stage0 == 1'b1) & ~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce))) begin\n        grp_fu_930_ce = 1'b1;\n    end else begin\n        grp_fu_930_ce = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((ap_CS_fsm_pp0_stage0 == 1'b1) & ~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce))) begin\n        grp_fu_941_ce = 1'b1;\n    end else begin\n        grp_fu_941_ce = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    case (ap_CS_fsm)\n        ap_ST_fsm_pp0_stage0 : begin\n            ap_NS_fsm = ap_ST_fsm_pp0_stage0;\n        end\n        default : begin\n            ap_NS_fsm = 'bx;\n        end\n    endcase\nend\n\nassign OP2_V_cast_fu_504_p1 = fine_word_V_reg_1190;\n\nassign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[ap_const_lv32_0];\n\nassign ap_enable_reg_pp0_iter0 = ap_start;\n\nassign ap_return_0 = cos_dds_V_fu_875_p3;\n\nassign ap_return_1 = sin_dds_V_fu_910_p3;\n\nassign brmerge40_demorgan_i_1_fu_786_p2 = (newsignbit_1_reg_1308 & deleted_ones_1_fu_763_p3);\n\nassign brmerge40_demorgan_i_fu_726_p2 = (newsignbit_reg_1289 & deleted_ones_fu_703_p3);\n\nassign brmerge40_i1_fu_791_p2 = (brmerge40_demorgan_i_1_fu_786_p2 ^ 1'b1);\n\nassign brmerge40_i_fu_731_p2 = (brmerge40_demorgan_i_fu_726_p2 ^ 1'b1);\n\nassign brmerge6_fu_857_p2 = (ap_pipeline_reg_pp0_iter16_overflow_reg_1321 | underflow_16_not_fu_852_p2);\n\nassign brmerge7_fu_892_p2 = (ap_pipeline_reg_pp0_iter16_overflow_1_reg_1332 | underflow_17_not_fu_887_p2);\n\nassign brmerge_i4_fu_715_p2 = (newsignbit_reg_1289 | p_not_i_fu_710_p2);\n\nassign brmerge_i5_fu_775_p2 = (newsignbit_1_reg_1308 | p_not_i1_fu_770_p2);\n\nassign brmerge_i_i4_fu_848_p2 = (underflow_2_reg_1343 | ap_pipeline_reg_pp0_iter16_overflow_reg_1321);\n\nassign brmerge_i_i5_fu_883_p2 = (underflow_3_reg_1350 | ap_pipeline_reg_pp0_iter16_overflow_1_reg_1332);\n\nassign carry_1_fu_753_p2 = (ap_pipeline_reg_pp0_iter14_tmp_39_reg_1267 & tmp_20_fu_748_p2);\n\nassign carry_fu_693_p2 = (ap_pipeline_reg_pp0_iter14_tmp_32_reg_1241 & tmp_12_fu_688_p2);\n\nassign cos_dds_V_fu_875_p3 = ((brmerge6_fu_857_p2[0:0] === 1'b1) ? p_Val2_87_mux_fu_862_p3 : p_Val2_4_9_fu_869_p3);\n\nassign dds_0_cos_lut_V_address0 = tmp_1_fu_174_p1;\n\nassign dds_0_cos_lut_V_address1 = tmp_4_fu_183_p1;\n\nassign dds_0_cos_lut_V_load_2_fu_190_p1 = p_Val2_4_reg_1001;\n\nassign dds_0_cos_lut_V_load_fu_187_p1 = p_Val2_6_reg_996;\n\nassign dds_0_fine_lut_V_address0 = tmp_8_fu_480_p1;\n\nassign deleted_ones_1_fu_763_p3 = ((carry_1_fu_753_p2[0:0] === 1'b1) ? tmp_21_fu_758_p2 : ap_pipeline_reg_pp0_iter14_signbit_1_reg_1254);\n\nassign deleted_ones_fu_703_p3 = ((carry_fu_693_p2[0:0] === 1'b1) ? tmp_13_fu_698_p2 : ap_pipeline_reg_pp0_iter14_signbit_reg_1228);\n\nassign grp_fu_930_p1 = OP2_V_cast_fu_504_p1;\n\nassign grp_fu_941_p0 = OP2_V_cast_fu_504_p1;\n\nassign overflow_1_fu_780_p2 = (brmerge_i5_fu_775_p2 & tmp_21_fu_758_p2);\n\nassign overflow_fu_720_p2 = (brmerge_i4_fu_715_p2 & tmp_13_fu_698_p2);\n\nassign p_Result_11_not_fu_828_p2 = (ap_pipeline_reg_pp0_iter15_tmp_39_reg_1267 ^ 1'b1);\n\nassign p_Result_2_not_fu_808_p2 = (ap_pipeline_reg_pp0_iter15_tmp_32_reg_1241 ^ 1'b1);\n\nassign p_Val2_0_i_i1_fu_321_p3 = ((sel_tmp2_fu_316_p2[0:0] === 1'b1) ? p_Val2_74_mux_fu_280_p3 : sel_tmp_fu_309_p3);\n\nassign p_Val2_0_i_i_cast_fu_422_p1 = p_Val2_0_i_i_reg_1101;\n\nassign p_Val2_0_i_i_fu_286_p3 = ((ap_pipeline_reg_pp0_iter5_tmp_2_reg_981[0:0] === 1'b1) ? ap_const_lv17_0 : ap_pipeline_reg_pp0_iter5_p_Val2_4_reg_1001);\n\nassign p_Val2_10_fu_576_p4 = {{ap_pipeline_reg_pp0_iter13_p_Val2_9_reg_1221[ap_const_lv32_2A : ap_const_lv32_1B]}};\n\nassign p_Val2_11_fu_614_p2 = (tmp_11_fu_610_p1 + p_Val2_10_fu_576_p4);\n\nassign p_Val2_14_fu_632_p4 = {{ap_pipeline_reg_pp0_iter13_p_Val2_13_reg_1247[ap_const_lv32_2A : ap_const_lv32_1B]}};\n\nassign p_Val2_15_fu_670_p2 = (tmp_19_fu_666_p1 + p_Val2_14_fu_632_p4);\n\nassign p_Val2_1_8_fu_474_p3 = ((sel_tmp20_reg_1152[0:0] === 1'b1) ? p_Val2_74_mux_reg_1096 : sel_tmp26_fu_467_p3);\n\nassign p_Val2_1_fu_303_p3 = ((underflow_1_reg_1076[0:0] === 1'b1) ? ap_const_lv18_20001 : ap_pipeline_reg_pp0_iter5_p_Val2_7_reg_1030);\n\nassign p_Val2_3_fu_127_p2 = (incr_V + dds_0_acc_V);\n\nassign p_Val2_4_9_fu_869_p3 = ((underflow_2_reg_1343[0:0] === 1'b1) ? ap_const_lv16_8001 : ap_pipeline_reg_pp0_iter16_p_Val2_11_reg_1283);\n\nassign p_Val2_5_10_fu_904_p3 = ((underflow_3_reg_1350[0:0] === 1'b1) ? ap_const_lv16_8001 : ap_pipeline_reg_pp0_iter16_p_Val2_15_reg_1302);\n\nassign p_Val2_5_fu_193_p2 = (ap_const_lv18_0 - dds_0_cos_lut_V_load_2_fu_190_p1);\n\nassign p_Val2_74_mux_fu_280_p3 = ((underflow_reg_1069[0:0] === 1'b1) ? ap_const_lv18_1FFFF : ap_pipeline_reg_pp0_iter5_p_Val2_5_reg_1019);\n\nassign p_Val2_77_mux_fu_425_p3 = ((ap_pipeline_reg_pp0_iter6_underflow_1_reg_1076[0:0] === 1'b1) ? ap_const_lv18_1FFFF : ap_pipeline_reg_pp0_iter6_p_Val2_7_reg_1030);\n\nassign p_Val2_7_fu_207_p2 = (ap_const_lv18_0 - dds_0_cos_lut_V_load_fu_187_p1);\n\nassign p_Val2_87_mux_fu_862_p3 = ((brmerge_i_i4_fu_848_p2[0:0] === 1'b1) ? ap_const_lv16_7FFF : ap_pipeline_reg_pp0_iter16_p_Val2_11_reg_1283);\n\nassign p_Val2_8_fu_495_p3 = ((ap_pipeline_reg_pp0_iter7_sel_tmp20_reg_1152[0:0] === 1'b1) ? ap_pipeline_reg_pp0_iter7_p_Val2_1_reg_1106 : sel_tmp18_fu_489_p3);\n\nassign p_Val2_91_mux_fu_897_p3 = ((brmerge_i_i5_fu_883_p2[0:0] === 1'b1) ? ap_const_lv16_7FFF : ap_pipeline_reg_pp0_iter16_p_Val2_15_reg_1302);\n\nassign p_Val2_s_7_fu_297_p3 = ((underflow_reg_1069[0:0] === 1'b1) ? ap_const_lv18_20001 : ap_pipeline_reg_pp0_iter5_p_Val2_5_reg_1019);\n\nassign p_not_i1_fu_770_p2 = (ap_pipeline_reg_pp0_iter14_signbit_1_reg_1254 ^ carry_1_fu_753_p2);\n\nassign p_not_i_fu_710_p2 = (ap_pipeline_reg_pp0_iter14_signbit_reg_1228 ^ carry_fu_693_p2);\n\nassign qb_assign_1_fu_604_p2 = (r_i_i_fu_599_p2 & qbit_fu_585_p3);\n\nassign qb_assign_3_fu_660_p2 = (r_i_i1_fu_655_p2 & qbit_1_fu_641_p3);\n\nassign qbit_1_fu_641_p3 = ap_pipeline_reg_pp0_iter13_p_Val2_13_reg_1247[ap_const_lv32_1A];\n\nassign qbit_fu_585_p3 = ap_pipeline_reg_pp0_iter13_p_Val2_9_reg_1221[ap_const_lv32_1A];\n\nassign r_1_fu_571_p2 = ((tmp_38_reg_1262 != ap_const_lv26_0) ? 1'b1 : 1'b0);\n\nassign r_fu_566_p2 = ((tmp_31_reg_1236 != ap_const_lv26_0) ? 1'b1 : 1'b0);\n\nassign r_i_i1_fu_655_p2 = (tmp_40_fu_648_p3 | r_1_reg_1278);\n\nassign r_i_i_fu_599_p2 = (tmp_33_fu_592_p3 | r_reg_1273);\n\nassign sel_tmp10_fu_347_p2 = (sel_tmp18_demorgan_reg_1090 ^ 1'b1);\n\nassign sel_tmp11_fu_352_p2 = (tmp_6_reg_1063 & sel_tmp10_fu_347_p2);\n\nassign sel_tmp12_fu_357_p2 = (sel_tmp11_fu_352_p2 & underflow_1_reg_1076);\n\nassign sel_tmp13_fu_448_p3 = ((sel_tmp12_reg_1134[0:0] === 1'b1) ? p_Val2_0_i_i_cast_fu_422_p1 : sel_tmp8_fu_442_p3);\n\nassign sel_tmp14_fu_362_p2 = (sel_tmp11_fu_352_p2 & underflow_14_not_fu_292_p2);\n\nassign sel_tmp15_fu_484_p3 = ((ap_pipeline_reg_pp0_iter7_sel_tmp14_reg_1140[0:0] === 1'b1) ? p_Val2_0_i_i_cast_reg_1163 : sel_tmp13_reg_1168);\n\nassign sel_tmp16_fu_372_p2 = (sel_tmp33_demorgan_fu_368_p2 ^ 1'b1);\n\nassign sel_tmp17_fu_378_p2 = (ap_pipeline_reg_pp0_iter5_tmp_2_reg_981 & sel_tmp16_fu_372_p2);\n\nassign sel_tmp18_demorgan_fu_269_p2 = (tmp_s_fu_229_p2 | tmp_3_fu_234_p2);\n\nassign sel_tmp18_fu_489_p3 = ((ap_pipeline_reg_pp0_iter7_sel_tmp17_reg_1146[0:0] === 1'b1) ? ap_pipeline_reg_pp0_iter7_p_Val2_1_reg_1106 : sel_tmp15_fu_484_p3);\n\nassign sel_tmp19_fu_388_p2 = (sel_tmp42_demorgan_fu_383_p2 ^ 1'b1);\n\nassign sel_tmp1_fu_264_p2 = (ap_pipeline_reg_pp0_iter4_tmp_2_reg_981 ^ 1'b1);\n\nassign sel_tmp20_fu_394_p2 = (underflow_12_not_fu_275_p2 & sel_tmp19_fu_388_p2);\n\nassign sel_tmp21_fu_400_p3 = ((sel_tmp9_fu_329_p2[0:0] === 1'b1) ? ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_2_reg_1014 : p_Val2_s_7_fu_297_p3);\n\nassign sel_tmp22_fu_407_p3 = ((sel_tmp5_fu_338_p2[0:0] === 1'b1) ? ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_reg_1007 : sel_tmp21_fu_400_p3);\n\nassign sel_tmp23_fu_414_p3 = ((sel_tmp7_fu_343_p2[0:0] === 1'b1) ? ap_const_lv18_0 : sel_tmp22_fu_407_p3);\n\nassign sel_tmp24_fu_455_p3 = ((sel_tmp12_reg_1134[0:0] === 1'b1) ? p_Val2_1_reg_1106 : sel_tmp23_reg_1158);\n\nassign sel_tmp25_fu_460_p3 = ((sel_tmp14_reg_1140[0:0] === 1'b1) ? p_Val2_77_mux_fu_425_p3 : sel_tmp24_fu_455_p3);\n\nassign sel_tmp26_fu_467_p3 = ((sel_tmp17_reg_1146[0:0] === 1'b1) ? ap_const_lv18_0 : sel_tmp25_fu_460_p3);\n\nassign sel_tmp2_fu_316_p2 = (underflow_12_not_fu_275_p2 & sel_tmp1_reg_1084);\n\nassign sel_tmp33_demorgan_fu_368_p2 = (sel_tmp18_demorgan_reg_1090 | tmp_6_reg_1063);\n\nassign sel_tmp3_fu_431_p3 = ((sel_tmp9_reg_1119[0:0] === 1'b1) ? ap_pipeline_reg_pp0_iter6_dds_0_cos_lut_V_load_reg_1007 : p_Val2_1_reg_1106);\n\nassign sel_tmp42_demorgan_fu_383_p2 = (sel_tmp33_demorgan_fu_368_p2 | ap_pipeline_reg_pp0_iter5_tmp_2_reg_981);\n\nassign sel_tmp4_fu_333_p2 = (tmp_s_reg_1051 ^ 1'b1);\n\nassign sel_tmp5_fu_338_p2 = (tmp_3_reg_1058 & sel_tmp4_fu_333_p2);\n\nassign sel_tmp6_fu_436_p3 = ((sel_tmp5_reg_1124[0:0] === 1'b1) ? p_Val2_0_i_i1_reg_1114 : sel_tmp3_fu_431_p3);\n\nassign sel_tmp7_fu_343_p2 = (tmp_s_reg_1051 & ap_pipeline_reg_pp0_iter5_tmp_2_reg_981);\n\nassign sel_tmp8_fu_442_p3 = ((sel_tmp7_reg_1129[0:0] === 1'b1) ? ap_pipeline_reg_pp0_iter6_dds_0_cos_lut_V_load_reg_1007 : sel_tmp6_fu_436_p3);\n\nassign sel_tmp9_fu_329_p2 = (tmp_s_reg_1051 & sel_tmp1_reg_1084);\n\nassign sel_tmp_fu_309_p3 = ((ap_pipeline_reg_pp0_iter5_tmp_2_reg_981[0:0] === 1'b1) ? ap_const_lv18_0 : p_Val2_s_7_fu_297_p3);\n\nassign sin_adr_V_fu_169_p2 = (ap_const_lv10_0 - lsb_V_reg_959);\n\nassign sin_dds_V_fu_910_p3 = ((brmerge7_fu_892_p2[0:0] === 1'b1) ? p_Val2_91_mux_fu_897_p3 : p_Val2_5_10_fu_904_p3);\n\nassign tmp9_fu_838_p2 = (tmp_22_fu_833_p2 & tmp_24_reg_1338);\n\nassign tmp_11_fu_610_p1 = qb_assign_1_fu_604_p2;\n\nassign tmp_12_fu_688_p2 = (newsignbit_reg_1289 ^ 1'b1);\n\nassign tmp_13_fu_698_p2 = (ap_pipeline_reg_pp0_iter14_signbit_reg_1228 ^ 1'b1);\n\nassign tmp_14_fu_813_p2 = (ap_pipeline_reg_pp0_iter15_newsignbit_reg_1289 | p_Result_2_not_fu_808_p2);\n\nassign tmp_15_fu_737_p2 = ((tmp_35_reg_1297 == ap_const_lv15_0) ? 1'b1 : 1'b0);\n\nassign tmp_16_fu_742_p2 = (tmp_15_fu_737_p2 | brmerge40_i_fu_731_p2);\n\nassign tmp_17_fu_521_p3 = {{ap_pipeline_reg_pp0_iter10_p_Val2_1_8_reg_1173}, {ap_const_lv25_0}};\n\nassign tmp_19_fu_666_p1 = qb_assign_3_fu_660_p2;\n\nassign tmp_1_fu_174_p1 = ap_pipeline_reg_pp0_iter1_lsb_V_reg_959;\n\nassign tmp_20_fu_748_p2 = (newsignbit_1_reg_1308 ^ 1'b1);\n\nassign tmp_21_fu_758_p2 = (ap_pipeline_reg_pp0_iter14_signbit_1_reg_1254 ^ 1'b1);\n\nassign tmp_22_fu_833_p2 = (ap_pipeline_reg_pp0_iter15_newsignbit_1_reg_1308 | p_Result_11_not_fu_828_p2);\n\nassign tmp_23_fu_797_p2 = ((tmp_42_reg_1316 == ap_const_lv15_0) ? 1'b1 : 1'b0);\n\nassign tmp_24_fu_802_p2 = (tmp_23_fu_797_p2 | brmerge40_i1_fu_791_p2);\n\nassign tmp_27_fu_221_p1 = p_Val2_5_fu_193_p2[16:0];\n\nassign tmp_28_fu_225_p1 = p_Val2_7_fu_207_p2[16:0];\n\nassign tmp_2_fu_178_p2 = ((ap_pipeline_reg_pp0_iter1_lsb_V_reg_959 == ap_const_lv10_0) ? 1'b1 : 1'b0);\n\nassign tmp_31_fu_539_p1 = grp_fu_930_p3[25:0];\n\nassign tmp_33_fu_592_p3 = ap_pipeline_reg_pp0_iter13_p_Val2_9_reg_1221[ap_const_lv32_1B];\n\nassign tmp_35_fu_628_p1 = p_Val2_11_fu_614_p2[14:0];\n\nassign tmp_38_fu_556_p1 = grp_fu_941_p3[25:0];\n\nassign tmp_3_fu_234_p2 = ((ap_pipeline_reg_pp0_iter4_msb_V_reg_952 == ap_const_lv2_1) ? 1'b1 : 1'b0);\n\nassign tmp_40_fu_648_p3 = ap_pipeline_reg_pp0_iter13_p_Val2_13_reg_1247[ap_const_lv32_1B];\n\nassign tmp_42_fu_684_p1 = p_Val2_15_fu_670_p2[14:0];\n\nassign tmp_4_fu_183_p1 = sin_adr_V_reg_971;\n\nassign tmp_5_fu_244_p2 = ((tmp_27_reg_1041 == ap_const_lv17_0) ? 1'b1 : 1'b0);\n\nassign tmp_6_fu_239_p2 = ((ap_pipeline_reg_pp0_iter4_msb_V_reg_952 == ap_const_lv2_3) ? 1'b1 : 1'b0);\n\nassign tmp_7_fu_254_p2 = ((tmp_28_reg_1046 == ap_const_lv17_0) ? 1'b1 : 1'b0);\n\nassign tmp_8_fu_480_p1 = ap_pipeline_reg_pp0_iter6_p_Result_8_reg_966;\n\nassign tmp_9_fu_510_p3 = {{ap_pipeline_reg_pp0_iter10_p_Val2_8_reg_1184}, {ap_const_lv25_0}};\n\nassign tmp_fu_818_p2 = (tmp_14_fu_813_p2 & tmp_16_reg_1327);\n\nassign tmp_s_fu_229_p2 = ((ap_pipeline_reg_pp0_iter4_msb_V_reg_952 == ap_const_lv2_0) ? 1'b1 : 1'b0);\n\nassign underflow_12_not_fu_275_p2 = (underflow_reg_1069 ^ 1'b1);\n\nassign underflow_14_not_fu_292_p2 = (underflow_1_reg_1076 ^ 1'b1);\n\nassign underflow_16_not_fu_852_p2 = (underflow_2_reg_1343 ^ 1'b1);\n\nassign underflow_17_not_fu_887_p2 = (underflow_3_reg_1350 ^ 1'b1);\n\nassign underflow_1_fu_259_p2 = (isneg_1_reg_1036 & tmp_7_fu_254_p2);\n\nassign underflow_2_fu_823_p2 = (tmp_fu_818_p2 & ap_pipeline_reg_pp0_iter15_signbit_reg_1228);\n\nassign underflow_3_fu_843_p2 = (tmp9_fu_838_p2 & ap_pipeline_reg_pp0_iter15_signbit_1_reg_1254);\n\nassign underflow_fu_249_p2 = (isneg_reg_1025 & tmp_5_fu_244_p2);\n\nalways @ (posedge ap_clk) begin\n    dds_0_cos_lut_V_load_reg_1007[17] <= 1'b0;\n    ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_reg_1007[17] <= 1'b0;\n    ap_pipeline_reg_pp0_iter6_dds_0_cos_lut_V_load_reg_1007[17] <= 1'b0;\n    dds_0_cos_lut_V_load_2_reg_1014[17] <= 1'b0;\n    ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_2_reg_1014[17] <= 1'b0;\n    p_Val2_0_i_i_cast_reg_1163[17] <= 1'b0;\nend\n\nendmodule //process_r\n", "num_lines": 1119}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// ==============================================================\n// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC\n// Version: 2016.3\n// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.\n// \n// ==============================================================\n\n`timescale 1 ns / 1 ps\nmodule process_r_dds_0_cbkb_rom (\naddr0, ce0, q0, addr1, ce1, q1, clk);\n\nparameter DWIDTH = 17;\nparameter AWIDTH = 10;\nparameter MEM_SIZE = 1024;\n\ninput[AWIDTH-1:0] addr0;\ninput ce0;\noutput reg[DWIDTH-1:0] q0;\ninput[AWIDTH-1:0] addr1;\ninput ce1;\noutput reg[DWIDTH-1:0] q1;\ninput clk;\n\nreg [DWIDTH-1:0] ram[0:MEM_SIZE-1];\n\ninitial begin\n    $readmemh(\"./process_r_dds_0_cbkb_rom.dat\", ram);\nend\n\n\n\nalways @(posedge clk)  \nbegin \n    if (ce0) \n    begin\n        q0 <= ram[addr0];\n    end\nend\n\n\n\nalways @(posedge clk)  \nbegin \n    if (ce1) \n    begin\n        q1 <= ram[addr1];\n    end\nend\n\n\n\nendmodule\n\n\n`timescale 1 ns / 1 ps\nmodule process_r_dds_0_cbkb(\n    reset,\n    clk,\n    address0,\n    ce0,\n    q0,\n    address1,\n    ce1,\n    q1);\n\nparameter DataWidth = 32'd17;\nparameter AddressRange = 32'd1024;\nparameter AddressWidth = 32'd10;\ninput reset;\ninput clk;\ninput[AddressWidth - 1:0] address0;\ninput ce0;\noutput[DataWidth - 1:0] q0;\ninput[AddressWidth - 1:0] address1;\ninput ce1;\noutput[DataWidth - 1:0] q1;\n\n\n\nprocess_r_dds_0_cbkb_rom process_r_dds_0_cbkb_rom_U(\n    .clk( clk ),\n    .addr0( address0 ),\n    .ce0( ce0 ),\n    .q0( q0 ),\n    .addr1( address1 ),\n    .ce1( ce1 ),\n    .q1( q1 ));\n\nendmodule\n\n", "num_lines": 91}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// ==============================================================\n// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC\n// Version: 2016.3\n// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.\n// \n// ==============================================================\n\n`timescale 1 ns / 1 ps\nmodule process_r_dds_0_fcud_rom (\naddr0, ce0, q0, clk);\n\nparameter DWIDTH = 16;\nparameter AWIDTH = 9;\nparameter MEM_SIZE = 512;\n\ninput[AWIDTH-1:0] addr0;\ninput ce0;\noutput reg[DWIDTH-1:0] q0;\ninput clk;\n\nreg [DWIDTH-1:0] ram[0:MEM_SIZE-1];\n\ninitial begin\n    $readmemh(\"./process_r_dds_0_fcud_rom.dat\", ram);\nend\n\n\n\nalways @(posedge clk)  \nbegin \n    if (ce0) \n    begin\n        q0 <= ram[addr0];\n    end\nend\n\n\n\nendmodule\n\n\n`timescale 1 ns / 1 ps\nmodule process_r_dds_0_fcud(\n    reset,\n    clk,\n    address0,\n    ce0,\n    q0);\n\nparameter DataWidth = 32'd16;\nparameter AddressRange = 32'd512;\nparameter AddressWidth = 32'd9;\ninput reset;\ninput clk;\ninput[AddressWidth - 1:0] address0;\ninput ce0;\noutput[DataWidth - 1:0] q0;\n\n\n\nprocess_r_dds_0_fcud_rom process_r_dds_0_fcud_rom_U(\n    .clk( clk ),\n    .addr0( address0 ),\n    .ce0( ce0 ),\n    .q0( q0 ));\n\nendmodule\n\n", "num_lines": 69}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "// Amazon FPGA Hardware Development Kit\n//\n// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.\n//\n// Licensed under the Amazon Software License (the \"License\"). You may not use\n// this file except in compliance with the License. A copy of the License is\n// located at\n//\n//    http://aws.amazon.com/asl/\n//\n// or in the \"license\" file accompanying this file. This file is distributed on\n// an \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or\n// implied. See the License for the specific language governing permissions and\n// limitations under the License.\n\nmodule hello_world \n\n\n\t(\n\t\tinput wire  s_axi_aclk,\n\t\tinput wire  s_axi_aresetn,\n\t\tinput wire [31 : 0] s_axi_awaddr,\n\t\tinput wire [2 : 0] s_axi_awprot,\n\n\t\tinput wire  s_axi_awvalid,\n\n\t\toutput wire  s_axi_awready,\n\t\tinput wire [31 : 0] s_axi_wdata,\n    \n\t\tinput wire [3 : 0] s_axi_wstrb,\n\n\t\tinput wire  s_axi_wvalid,\n\n\t\toutput wire  s_axi_wready,\n\n\t\toutput wire [1 : 0] s_axi_bresp,\n\n\t\toutput reg  s_axi_bvalid,\n\n\t\tinput wire  s_axi_bready,\n\t\tinput wire [31 : 0] s_axi_araddr,\n\n\t\tinput wire [2 : 0] s_axi_arprot,\n\n\t\tinput wire  s_axi_arvalid,\n\n\t\toutput wire  s_axi_arready,\n\t\toutput reg [31 : 0] s_axi_rdata,\n\t\toutput reg [1 : 0] s_axi_rresp,\n\n\t\toutput reg  s_axi_rvalid,\n\t\tinput wire  s_axi_rready,\n\t\tinput wire [15:0] vdip,\n\t\toutput reg [15:0] vled\n\t);\n\n\n\n// CL Register Addresses\n`define HELLO_WORLD_REG_ADDR    32'h0000_0500\n`define VLED_REG_ADDR           32'h0000_0504\n`define UNIMPLEMENTED_REG_VALUE 32'hdeaddead\n\n\n//-------------------------------------------------\n// Wires\n//-------------------------------------------------\n  reg        arvalid_q;\n  reg [31:0] araddr_q;\n  wire [31:0] hello_world_q_byte_swapped;\n  reg [15:0] vled_q;\n  wire [15:0] pre_cl_sh_status_vled;\n  reg [15:0] sh_cl_status_vdip_q;\n  reg [15:0] sh_cl_status_vdip_q2;\n  reg [31:0] hello_world_q;\n\n\n\n\n//--------------------------------------------------------------\n// PCIe OCL AXI-L Slave Accesses (accesses from PCIe AppPF BAR0)\n//--------------------------------------------------------------\n// Only supports single-beat accesses.\n\n   wire        awvalid;\n   wire [31:0] awaddr;\n   wire        wvalid;\n   wire [31:0] wdata;\n   wire [3:0]  wstrb;\n   wire        bready;\n   wire        arvalid;\n   wire [31:0] araddr;\n   wire        rready;\n\n\n\n   // Inputs\n   assign awvalid         = s_axi_awvalid;\n   assign awaddr[31:0]    = s_axi_awaddr;\n   assign wvalid          = s_axi_wvalid;\n   assign wdata[31:0]     = s_axi_wdata;\n   assign wstrb[3:0]      = s_axi_wstrb;\n   assign bready          = s_axi_bready;\n   assign arvalid         = s_axi_arvalid;\n   assign araddr[31:0]    = s_axi_araddr;\n   assign rready          = s_axi_rready;\n\n\n\n// Write Request\nreg        wr_active;\nreg [31:0] wr_addr;\n\nalways @(posedge s_axi_aclk)\n  if (!s_axi_aresetn) begin\n     wr_active <= 0;\n     wr_addr   <= 0;\n  end\n  else begin\n     wr_active <=  wr_active && s_axi_bvalid  && bready ? 1'b0     :\n                  ~wr_active && awvalid           ? 1'b1     :\n                                                    wr_active;\n     wr_addr <= awvalid && ~wr_active ? awaddr : wr_addr     ;\n  end\n\nassign s_axi_awready = ~wr_active;\nassign s_axi_wready  =  wr_active && wvalid;\n\n// Write Response\nalways @(posedge s_axi_aclk)\n  if (!s_axi_aresetn) \n    s_axi_bvalid <= 0;\n  else\n    s_axi_bvalid <=  s_axi_bvalid &&  bready           ? 1'b0  : \n                         ~s_axi_bvalid && s_axi_wready ? 1'b1  :\n                                             s_axi_bvalid;\nassign s_axi_bresp = 0;\n\n// Read Request\nalways @(posedge s_axi_aclk)\n   if (!s_axi_aresetn) begin\n      arvalid_q <= 0;\n      araddr_q  <= 0;\n   end\n   else begin\n      arvalid_q <= arvalid;\n      araddr_q  <= arvalid ? araddr : araddr_q;\n   end\n\nassign s_axi_arready = !arvalid_q && !s_axi_rvalid;\n\n// Read Response\nalways @(posedge s_axi_aclk)\n   if (!s_axi_aresetn)\n   begin\n      s_axi_rvalid <= 0;\n      s_axi_rdata  <= 0;\n      s_axi_rresp  <= 0;\n   end\n   else if (s_axi_rvalid && rready)\n   begin\n      s_axi_rvalid <= 0;\n      s_axi_rdata  <= 0;\n      s_axi_rresp  <= 0;\n   end\n   else if (arvalid_q) \n   begin\n      s_axi_rvalid <= 1;\n      s_axi_rdata  <= (araddr_q == `HELLO_WORLD_REG_ADDR) ? hello_world_q_byte_swapped[31:0]:\n                (araddr_q == `VLED_REG_ADDR       ) ? {16'b0,vled_q[15:0]            }:\n                                                      `UNIMPLEMENTED_REG_VALUE        ;\n      s_axi_rresp  <= 0;\n   end\n\n//-------------------------------------------------\n// Hello World Register\n//-------------------------------------------------\n// When read it, returns the byte-flipped value.\n\nalways @(posedge s_axi_aclk)\n   if (!s_axi_aresetn) begin                    // Reset\n      hello_world_q[31:0] <= 32'h0000_0000;\n   end\n   else if (s_axi_wready & (wr_addr == `HELLO_WORLD_REG_ADDR)) begin  \n      hello_world_q[31:0] <= wdata[31:0];\n   end\n   else begin                                // Hold Value\n      hello_world_q[31:0] <= hello_world_q[31:0];\n   end\n\nassign hello_world_q_byte_swapped[31:0] = {hello_world_q[7:0],   hello_world_q[15:8],\n                                           hello_world_q[23:16], hello_world_q[31:24]};\n\n//-------------------------------------------------\n// Virtual LED Register\n//-------------------------------------------------\n// Flop/synchronize interface signals\nalways @(posedge s_axi_aclk)\n   if (!s_axi_aresetn) begin                    // Reset\n      sh_cl_status_vdip_q[15:0]  <= 16'h0000;\n      sh_cl_status_vdip_q2[15:0] <= 16'h0000;\n      vled[15:0]    <= 16'h0000;\n   end\n   else begin\n      sh_cl_status_vdip_q[15:0]  <= vdip[15:0];\n      sh_cl_status_vdip_q2[15:0] <= sh_cl_status_vdip_q[15:0];\n      vled[15:0]    <= pre_cl_sh_status_vled[15:0];\n   end\n\n// The register contains 16 read-only bits corresponding to 16 LED's.\n// For this example, the virtual LED register shadows the hello_world\n// register.\n// The same LED values can be read from the CL to Shell interface\n// by using the linux FPGA tool: $ fpga-get-virtual-led -S 0\n\nalways @(posedge s_axi_aclk)\n   if (!s_axi_aresetn) begin                    // Reset\n      vled_q[15:0] <= 16'h0000;\n   end\n   else begin\n      vled_q[15:0] <= hello_world_q[15:0];\n   end\n\n// The Virtual LED outputs will be masked with the Virtual DIP switches.\nassign pre_cl_sh_status_vled[15:0] = vled_q[15:0] & sh_cl_status_vdip_q2[15:0];\n\n\n\n\n\n\nendmodule\n\n\n\n\n\n", "num_lines": 238}
{"repo_name": "aws-fpga", "repo_creator": "aws", "programming_language": "V", "code": "//*****************************************************************************\n// (c) Copyright 2011-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n\n//Generated by MBAC v3.04\n//8-12-2010, 14h 8m 23s\n//--------------------------------------------\n\n//RESET_POLARITY_SYMBOL, set to ! (or blank) for active low (high)\n`define AKRPS ! // ###MBAC###\n\n`timescale 1 ps / 1 ps // ###MBAC###\n\n//Assertion circuit for vunit: inline\n//vunit is bound to module: Axi4LitePC\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_protocol_checker_v1_1_12_axi4litepc_asr_inline (Axi4LitePC_asr_inline_out, reset, BVALID, BRESP, ACLK, RVALID, RRESP);\n  parameter DATA_WIDTH = 64;\n  output [3:1] Axi4LitePC_asr_inline_out;\n  input reset, BVALID, ACLK, RVALID;\n  input [1:0] BRESP;\n  input [1:0] RRESP;\n\n  reg ASR_1, ASR_2, ASR_3;\n\n  assign Axi4LitePC_asr_inline_out={ASR_3, ASR_2, ASR_1};\n\n  //---------------\n  //ASR_1 : assert property ( @(posedge ACLK) ( BVALID |-> BRESP != 2'b1 ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_1<=0; else\n    ASR_1 <= ((BVALID && !((BRESP != 2'b1))));\n\n  //---------------\n  //ASR_2 : assert property ( @(posedge ACLK) ( RVALID |-> RRESP != 2'b1 ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_2<=0; else\n    ASR_2 <= ((RVALID && !((RRESP != 2'b1))));\n\n  //---------------\n  //ASR_3 : assert property ( @(posedge ACLK) ( ( DATA_WIDTH == 32 || DATA_WIDTH == 64 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_3<=0; else\n    ASR_3 <= (!(((DATA_WIDTH == 32) || (DATA_WIDTH == 64))));\n\nendmodule //Axi4LitePC_asr_inline\n/*Instantiation code:\nAxi4LitePC_asr_inline #(DATA_WIDTH) i_Axi4LitePC_asr_inline (Axi4LitePC_asr_inline_out, reset, BVALID, BRESP, ACLK, RVALID, RRESP);\n*/\n//End of circuit(s) for vunit: inline\n\n\n//*****************************************************************************\n// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n\n//RESET_POLARITY_SYMBOL, set to ! (or blank) for active low (high)\n`define AKRPS ! // ###MBAC###\n\n`timescale 1 ps / 1 ps // ###MBAC###\n\n//Assertion circuit for vunit: inline\n//vunit is bound to module: Axi4PC\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_protocol_checker_v1_1_12_axi4pc_asr_inline (Axi4PC_asr_inline_out, reset, AWVALID, AWBURST, AwAddrIncr, AWADDR, ACLK, AlignMaskW, AWLEN, AWLOCK, AWCACHE, AwSizeInBits, ARESETn, AWREADY, AWID, AWPROT, AWSIZE, AWQOS, AWREGION, i_RecommendOn, i_RecMaxWaitOn, WriteDataNumError, BStrbError, WVALID, WREADY, WDATA, WLAST, WSTRB, BrespErrorLast, BrespExokError, BVALID, BrespErrorLead, BREADY, BID, BRESP, ARVALID, ARBURST, ArAddrIncr, ARADDR, AlignMaskR, ARLEN, ARLOCK, ARCACHE, ArSizeInBits, ARREADY, ARID, ARPROT, ARSIZE, ARQOS, ARREGION, RVALID, RREADY, ArCountPending, ArLenPending, RLAST, RidMatch, RRESP, ArExclPending, RDATA, RID, CSYSREQ, CSYSACK, ExclMask, ExclReadAddr, ExclAwMatch, ExclAddr, ExclSize, ExclLen, ExclBurst, ExclCache, ExclProt, ExclRegion, ArLenInBytes, ExclReadData, AWUSER, WUSER, BUSER, ARUSER, RUSER); // ###MBAC###\n  parameter DATA_WIDTH = 64;\n  parameter ID_WIDTH = 4;\n  parameter AWUSER_WIDTH = 32;\n  parameter WUSER_WIDTH = 32;\n  parameter BUSER_WIDTH = 32;\n  parameter ARUSER_WIDTH = 32;\n  parameter RUSER_WIDTH = 32;\n  parameter MAXRBURSTS = 16;\n  parameter MAXWBURSTS = 16;\n  parameter ADDR_WIDTH = 32;\n  parameter EXMON_WIDTH = 4;\n  parameter DATA_MAX = DATA_WIDTH - 1; // ###MBAC###\n  parameter ADDR_MAX = ADDR_WIDTH - 1;\n  parameter STRB_WIDTH = DATA_WIDTH / 8;\n  parameter STRB_MAX = STRB_WIDTH - 1;\n  parameter ID_MAX = ID_WIDTH ? ID_WIDTH - 1 : 0;\n  parameter EXMON_MAX = EXMON_WIDTH - 1;\n  parameter EXMON_HI = {EXMON_WIDTH{1'b1}};\n  parameter AWUSER_MAX = AWUSER_WIDTH ? AWUSER_WIDTH - 1 : 0; // ###MBAC###\n  parameter WUSER_MAX = WUSER_WIDTH ? WUSER_WIDTH - 1 : 0;\n  parameter BUSER_MAX = BUSER_WIDTH ? BUSER_WIDTH - 1 : 0;\n  parameter ARUSER_MAX = ARUSER_WIDTH ? ARUSER_WIDTH - 1 : 0;\n  parameter RUSER_MAX = RUSER_WIDTH ? RUSER_WIDTH - 1 : 0;\n  parameter MAX_AW_WAITS = 16;\n  parameter MAX_AR_WAITS = 16;\n  parameter MAX_W_WAITS  = 16;\n  parameter MAX_R_WAITS  = 16;\n  parameter MAX_B_WAITS  = 16;\n  output [87:1] Axi4PC_asr_inline_out;\n  input reset, AWVALID, ACLK, AWLOCK, ARESETn, AWREADY, i_RecommendOn, i_RecMaxWaitOn, WriteDataNumError, BStrbError, WVALID, WREADY, WLAST, BrespErrorLast, BrespExokError, BVALID, BrespErrorLead, BREADY, ARVALID, ARLOCK, ARREADY, RVALID, RREADY, RLAST, ArExclPending, CSYSREQ, CSYSACK, ExclAwMatch; // ###MBAC###\n  input [1:0] AWBURST;\n  input [ADDR_MAX:0] AwAddrIncr;\n  input [ADDR_MAX:0] AWADDR;\n  input [6:0] AlignMaskW;\n  input [7:0] AWLEN;\n  input [3:0] AWCACHE;\n  input [10:0] AwSizeInBits;\n  input [ID_MAX:0] AWID;\n  input [2:0] AWPROT;\n  input [2:0] AWSIZE;\n  input [3:0] AWQOS;\n  input [3:0] AWREGION;\n  input [DATA_MAX:0] WDATA; // ###MBAC###\n  input [STRB_MAX:0] WSTRB;\n  input [ID_MAX:0] BID; // ###MBAC###\n  input [1:0] BRESP;\n  input [1:0] ARBURST;\n  input [ADDR_MAX:0] ArAddrIncr;\n  input [ADDR_MAX:0] ARADDR;\n  input [6:0] AlignMaskR;\n  input [7:0] ARLEN;\n  input [3:0] ARCACHE;\n  input [10:0] ArSizeInBits;\n  input [ID_MAX:0] ARID;\n  input [2:0] ARPROT;\n  input [2:0] ARSIZE;\n  input [3:0] ARQOS;\n  input [3:0] ARREGION;\n  input [8:0] ArCountPending;\n  input [8:0] ArLenPending;\n  input [31:0] RidMatch;\n  input [1:0] RRESP;\n  input [DATA_MAX:0] RDATA; // ###MBAC###\n  input [ID_MAX:0] RID;\n  input [14:0] ExclMask;\n// ###MBAC###  input [EXMON_MAX:0] ExclAwId;\n// ###MBAC###  input [ADDR_MAX:0] ExclAddr [EXMON_HI:0];\n// ###MBAC###  input [2:0] ExclSize [EXMON_HI:0];\n// ###MBAC###  input [7:0] ExclLen [EXMON_HI:0];\n// ###MBAC###  input [1:0] ExclBurst [EXMON_HI:0];\n// ###MBAC###  input [3:0] ExclCache [EXMON_HI:0];\n// ###MBAC###  input [2:0] ExclProt [EXMON_HI:0];\n// ###MBAC###  input [3:0] ExclRegion [EXMON_HI:0];\n  input [ADDR_MAX:0] ExclAddr;\n  input [2:0] ExclSize;\n  input [7:0] ExclLen;\n  input [1:0] ExclBurst;\n  input [3:0] ExclCache;\n  input [2:0] ExclProt;\n  input [3:0] ExclRegion;\n  input ExclReadAddr;\n  input ExclReadData;\n// ###MBAC###\n  input [15:0] ArLenInBytes;\n  input [AWUSER_MAX:0] AWUSER; // ###MBAC###\n  input [WUSER_MAX:0] WUSER;\n  input [BUSER_MAX:0] BUSER;\n  input [ARUSER_MAX:0] ARUSER;\n  input [RUSER_MAX:0] RUSER;\n// ###MBAC###  input [31:0] RIndex;\n// ###MBAC###  input [31:0] WIndex;\n\n  function integer f_clogb2 (input integer size);\n    integer s;\n    begin\n      s = size;\n      s = s - 1;\n      for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n            s = s >> 1;\n    end\n  endfunction // clogb2\n\n  wire [2:0] s1s;\n  reg [2:0] s1sq;\n  reg [ADDR_MAX:0] s2;\n  wire [2:0] s4s;\n  reg [2:0] s4sq;\n  reg [1:0] s5;\n  wire [2:0] s7s;\n  reg [2:0] s7sq;\n  reg [3:0] s8;\n  wire [2:0] s10s;\n  reg [2:0] s10sq;\n  reg [ID_MAX:0] s11;\n  wire [2:0] s13s;\n  reg [2:0] s13sq;\n  reg [7:0] s14;\n  wire [2:0] s16s;\n  reg [2:0] s16sq;\n  wire [2:0] s19s;\n  reg [2:0] s19sq;\n  reg [2:0] s20;\n  wire [2:0] s22s;\n  reg [2:0] s22sq;\n  reg [2:0] s23;\n  wire [2:0] s25s;\n  reg [2:0] s25sq;\n  reg [3:0] s26;\n  wire [2:0] s28s;\n  reg [2:0] s28sq;\n  reg [3:0] s29;\n  wire [2:0] s31s;\n  reg [2:0] s31sq;\n  wire [2:0] s32s;\n  reg [2:0] s32sq;\n  wire [2:0] s34s;\n  reg [2:0] s34sq;\n  reg [DATA_MAX:0] s35;\n  wire [2:0] s37s;\n  reg [2:0] s37sq;\n  wire [2:0] s40s;\n  reg [2:0] s40sq;\n  reg [STRB_MAX:0] s41;\n  wire [2:0] s43s;\n  reg [2:0] s43sq;\n  wire [2:0] s44s;\n  reg [2:0] s44sq;\n  wire [2:0] s46s;\n  reg [2:0] s46sq;\n  reg [ID_MAX:0] s47;\n  wire [2:0] s49s;\n  reg [2:0] s49sq;\n  reg [1:0] s50;\n  wire [2:0] s52s;\n  reg [2:0] s52sq;\n  wire [2:0] s53s;\n  reg [2:0] s53sq;\n  wire [2:0] s55s;\n  reg [2:0] s55sq;\n  reg [ADDR_MAX:0] s56;\n  wire [2:0] s58s;\n  reg [2:0] s58sq;\n  reg [1:0] s59;\n  wire [2:0] s61s;\n  reg [2:0] s61sq;\n  reg [3:0] s62;\n  wire [2:0] s64s;\n  reg [2:0] s64sq;\n  reg [ID_MAX:0] s65;\n  wire [2:0] s67s;\n  reg [2:0] s67sq;\n  reg [7:0] s68;\n  wire [2:0] s70s;\n  reg [2:0] s70sq;\n  wire [2:0] s73s;\n  reg [2:0] s73sq;\n  reg [2:0] s74;\n  wire [2:0] s76s;\n  reg [2:0] s76sq;\n  reg [2:0] s77;\n  wire [2:0] s79s;\n  reg [2:0] s79sq;\n  reg [3:0] s80;\n  wire [2:0] s82s;\n  reg [2:0] s82sq;\n  reg [3:0] s83;\n  wire [2:0] s85s;\n  reg [2:0] s85sq;\n  wire [2:0] s86s;\n  reg [2:0] s86sq;\n  wire [2:0] s88s;\n  reg [2:0] s88sq;\n  reg [DATA_MAX:0] s89;\n  wire [2:0] s91s;\n  reg [2:0] s91sq;\n  reg [ID_MAX:0] s92;\n  wire [2:0] s94s;\n  reg [2:0] s94sq;\n  wire [2:0] s97s;\n  reg [2:0] s97sq;\n  reg [1:0] s98;\n  wire [2:0] s100s;\n  reg [2:0] s100sq;\n  wire [2:0] s101s;\n  reg [2:0] s101sq;\n  reg [31:0] s103;\n  wire [2:0] s105s;\n  reg [2:0] s105sq;\n  reg [WUSER_MAX:0] s106;\n  wire [2:0] s108s;\n  reg [2:0] s108sq;\n  reg [BUSER_MAX:0] s109;\n  wire [2:0] s111s;\n  reg [2:0] s111sq;\n  reg [ARUSER_MAX:0] s112;\n  wire [2:0] s114s;\n  reg [2:0] s114sq;\n  reg [RUSER_MAX:0] s115;\n  wire [2:0] s117s;\n  reg [2:0] s117sq;\n  reg [AWUSER_MAX:0] s118;\n  reg [WUSER_MAX:0] s120;\n  reg [BUSER_MAX:0] s122;\n  reg [ARUSER_MAX:0] s124;\n  reg [RUSER_MAX:0] s126;\n  reg [ID_MAX:0] s128;\n  reg [ID_MAX:0] s130;\n  reg [ID_MAX:0] s132;\n  reg [ID_MAX:0] s134;\n  wire s3, s6, s9, s12, s15, s18, s21, s24, s27, s30, s36, s39, s42, s48, s51, s57, s60, s63, s66, s69, s72, s75, s78, s81, s84, s90, s93, s96, s99, s104, s107, s110, s113, s116, s119, s121, s123, s125, s127, s129, s131, s133, s135;\n  reg ASR_1, ASR_2, ASR_3, ASR_4, ASR_5, ASR_6, ASR_7, ASR_8, ASR_9, ASR_10, ASR_11, ASR_12, ASR_13, ASR_14, s17, ASR_15, ASR_16, ASR_17, ASR_18, ASR_19, ASR_20, ASR_21, ASR_22, ASR_23, ASR_24, ASR_25, s38, ASR_26, ASR_27, ASR_28, ASR_29, ASR_30, ASR_31, ASR_32, ASR_33, ASR_34, ASR_35, ASR_36, ASR_37, ASR_38, ASR_39, ASR_40, ASR_41, ASR_42, ASR_43, ASR_44, ASR_45, ASR_46, ASR_47, ASR_48, ASR_49, ASR_50, ASR_51, s71, ASR_52, ASR_53, ASR_54, ASR_55, ASR_56, ASR_57, ASR_58, ASR_59, ASR_60, ASR_61, ASR_62, ASR_63, ASR_64, s95, ASR_65, ASR_66, ASR_67, ASR_68, ASR_69, ASR_70, ASR_71, ASR_72, ASR_73, ASR_74, ASR_75, ASR_76, ASR_77, ASR_78, ASR_79, ASR_80, ASR_81, ASR_82, ASR_83, ASR_84, ASR_85, ASR_86, ASR_87;\n\n  assign Axi4PC_asr_inline_out={ASR_87, ASR_86, ASR_85, ASR_84, ASR_83, ASR_82, ASR_81, ASR_80, ASR_79, ASR_78, ASR_77, ASR_76, ASR_75, ASR_74, ASR_73, ASR_72, ASR_71, ASR_70, ASR_69, ASR_68, ASR_67, ASR_66, ASR_65, ASR_64, ASR_63, ASR_62, ASR_61, ASR_60, ASR_59, ASR_58, ASR_57, ASR_56, ASR_55, ASR_54, ASR_53, ASR_52, ASR_51, ASR_50, ASR_49, ASR_48, ASR_47, ASR_46, ASR_45, ASR_44, ASR_43, ASR_42, ASR_41, ASR_40, ASR_39, ASR_38, ASR_37, ASR_36, ASR_35, ASR_34, ASR_33, ASR_32, ASR_31, ASR_30, ASR_29, ASR_28, ASR_27, ASR_26, ASR_25, ASR_24, ASR_23, ASR_22, ASR_21, ASR_20, ASR_19, ASR_18, ASR_17, ASR_16, ASR_15, ASR_14, ASR_13, ASR_12, ASR_11, ASR_10, ASR_9, ASR_8, ASR_7, ASR_6, ASR_5, ASR_4, ASR_3, ASR_2, ASR_1};\n\nlocalparam L_AW_WAIT_WIDTH = f_clogb2(MAX_AW_WAITS+1);\nlocalparam L_AR_WAIT_WIDTH = f_clogb2(MAX_AW_WAITS+1);\nlocalparam L_W_WAIT_WIDTH  = f_clogb2(MAX_W_WAITS+1);\nlocalparam L_R_WAIT_WIDTH  = f_clogb2(MAX_R_WAITS+1);\nlocalparam L_B_WAIT_WIDTH  = f_clogb2(MAX_B_WAITS+1);\n\n\n  //---------------\n  //ASR_1 : assert property ( @(posedge ACLK) ( AWVALID & ( AWBURST == 2'b1 ) |-> ( AwAddrIncr[ADDR_MAX:12] == AWADDR[ADDR_MAX:12] ) ) );\n  //---------------\n  reg [ADDR_MAX-12:0] AwAddrIncr_q1;\n  reg [ADDR_MAX-12:0] AWADDR_q1;\n  reg                 asr_1_ctrl;\n  always @(posedge ACLK) begin\n    AwAddrIncr_q1 <= AwAddrIncr[ADDR_MAX:12];\n    AWADDR_q1     <= AWADDR[ADDR_MAX:12];\n    asr_1_ctrl   <= (AWVALID & ( (AWBURST == 2'b1) ));\n  end\n\n  always @(posedge ACLK) if (`AKRPS reset) ASR_1<=0; else\n    ASR_1 <= asr_1_ctrl && !(AwAddrIncr_q1 == AWADDR_q1);\n\n  //---------------\n  //ASR_2 : assert property ( @(posedge ACLK) ( AWVALID & ( AWBURST == 2'b10 ) |-> ( ( AWADDR[6:0] & AlignMaskW ) == AWADDR[6:0] ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_2<=0; else\n    ASR_2 <= (((AWVALID & ( (AWBURST == 2'b10) )) && !((( (AWADDR[6:0] & AlignMaskW) ) == AWADDR[6:0]))));\n\n  //---------------\n  //ASR_3 : assert property ( @(posedge ACLK) ( AWVALID |-> ( AWBURST != 2'b11 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_3<=0; else\n    ASR_3 <= ((AWVALID && !((AWBURST != 2'b11))));\n\n  //---------------\n  //ASR_4 : assert property ( @(posedge ACLK) ( AWVALID & AWLEN > 8'b1111 |-> ( AWLOCK != 1'b1 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_4<=0; else\n    ASR_4 <= (((AWVALID & (AWLEN > 8'b1111)) && !((AWLOCK != 1'b1))));\n\n  //---------------\n  //ASR_5 : assert property ( @(posedge ACLK) ( AWVALID & ~ AWCACHE[1] |-> ( AWCACHE[3:2] == 2'b0 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_5<=0; else\n    ASR_5 <= (((AWVALID & (~ AWCACHE[1])) && !((AWCACHE[3:2] == 2'b0))));\n\n  //---------------\n  //ASR_6 : assert property ( @(posedge ACLK) ( AWVALID & AWLEN > 8'b1111 |-> ( AWBURST != 2'b0 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_6<=0; else\n    ASR_6 <= (((AWVALID & (AWLEN > 8'b1111)) && !((AWBURST != 2'b0))));\n\n  //---------------\n  //ASR_7 : assert property ( @(posedge ACLK) ( AWVALID & ( AWBURST == 2'b10 ) |-> ( AWLEN == 8'b1 || AWLEN == 8'b11 || AWLEN == 8'b111 || AWLEN == 8'b1111 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_7<=0; else\n    ASR_7 <= (((AWVALID & ( (AWBURST == 2'b10) )) && !(((((AWLEN == 8'b1) || (AWLEN == 8'b11)) || (AWLEN == 8'b111)) || (AWLEN == 8'b1111)))));\n\n  //---------------\n  //ASR_8 : assert property ( @(posedge ACLK) ( AWVALID |-> ( AwSizeInBits <= DATA_WIDTH ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_8<=0; else\n    ASR_8 <= ((AWVALID && !((AwSizeInBits <= DATA_WIDTH))));\n\n  //---------------\n  //ASR_9 : assert property ( @(posedge ACLK) ( ! ( ARESETn ) ##1 ARESETn |-> ! AWVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s1sq<=3'h4; else\n    s1sq<=s1s;\n  assign s1s={1'b1,\n    !(ARESETn),\n    (s1sq[1] && (ARESETn && AWVALID))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_9<=0; else\n    ASR_9 <= (s1s[0]);\n\n  //---------------\n  //ASR_10 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWADDR) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s2<=AWADDR;\n//  assign s3 = s2 == AWADDR;\n//  always @(posedge ACLK) if (`AKRPS reset) s4sq<=3'h4; else\n//    s4sq<=s4s;\n//  assign s4s={1'b1,\n//    ((ARESETn & AWVALID) & (! AWREADY)),\n//    (s4sq[1] && (ARESETn && !(s3)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_10<=0; else\n//    ASR_10 <= (s4s[0]);\nlocalparam integer L_NUM_AWADDR_BYTES       = ((ADDR_WIDTH + 7) / 8);\nlocalparam integer L_NUM_AWADDR_BYTE_LANES  = ((L_NUM_AWADDR_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_AWADDR_EQ_LANES    = (L_NUM_AWADDR_BYTE_LANES / 8);\nlocalparam integer L_NUM_AWADDR_AND1_LANES  = (L_NUM_AWADDR_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_AWADDR_AND2_LANES  = (L_NUM_AWADDR_AND1_LANES + 7) / 8;\n\nreg   [ADDR_WIDTH - 1:0]  AWADDR_q;\nreg   [4:0]               s_AWADDR_sq;\nwire  [4:0]               s_AWADDR_s;\nwire                      s_AWADDR_sqaa;\n\nreg [(8*L_NUM_AWADDR_EQ_LANES)-1:0]    AWADDR_eq;\nreg [(8*L_NUM_AWADDR_AND1_LANES)-1:0]  AWADDR_stage_1_eq;\nreg [(8*L_NUM_AWADDR_AND2_LANES)-1:0]  AWADDR_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_AWADDR_sq<=5'h00; \n    ASR_10 <=0;\n  end else begin\n    s_AWADDR_sq<=s_AWADDR_s;\n    ASR_10 <= (s_AWADDR_s[0]);\n  end\nend\n\nassign s_AWADDR_s={\n  (((ARESETn & AWVALID) & (! AWREADY))),\n  (s_AWADDR_sq[4] && ARESETn),\n  (s_AWADDR_sq[3]),\n  (s_AWADDR_sq[2]),\n  (s_AWADDR_sq[1] & !(s_AWADDR_sqaa))\n  };\n\nassign s_AWADDR_sqaa = &AWADDR_stage_2_eq;\n\nwire  [(L_NUM_AWADDR_BYTES*8)-1:0]      AWADDR_expand;\nwire  [(L_NUM_AWADDR_BYTES*8)-1:0]      AWADDRsqa_expand;\ngenvar AWADDR_bit;\ngenerate\n  ///////////////////////////////////////////////////////////////////////////////////////////\n  //Expand the AWADDR up to the nearest byte\n  for (AWADDR_bit = 0; AWADDR_bit < (L_NUM_AWADDR_BYTES * 8); AWADDR_bit = AWADDR_bit + 1) begin : AWADDR_BIT_LOOP\n    if (AWADDR_bit < ADDR_WIDTH) begin : VAL\n      assign AWADDR_expand[AWADDR_bit] = AWADDR[AWADDR_bit];\n      assign AWADDRsqa_expand[AWADDR_bit] = AWADDR_q[AWADDR_bit];\n    end else begin\n      assign AWADDR_expand[AWADDR_bit] = 1'b0;\n      assign AWADDRsqa_expand[AWADDR_bit] = 1'b0;\n    end\n  end\nendgenerate\n\ninteger AWADDR_bc;\ninteger AWADDR_stage_1;\ninteger AWADDR_stage_2;\n\nalways @(posedge ACLK) begin\n  AWADDR_q<=AWADDR;\n\n  for (AWADDR_bc = 0; AWADDR_bc < L_NUM_AWADDR_EQ_LANES*8; AWADDR_bc = AWADDR_bc + 1) begin : AWADDR_BC_LOOP\n    if (AWADDR_bc < L_NUM_AWADDR_BYTES) begin\n      AWADDR_eq[AWADDR_bc] <= AWADDR_expand[AWADDR_bc*8 +:8] == AWADDRsqa_expand[AWADDR_bc*8 +: 8];\n    end else begin\n      AWADDR_eq[AWADDR_bc] <= 1'b1;\n    end\n  end\n\n  for (AWADDR_stage_1 = 0; AWADDR_stage_1 < L_NUM_AWADDR_AND1_LANES * 8;AWADDR_stage_1 = AWADDR_stage_1 + 1) begin : AWADDR_S1\n    if (AWADDR_stage_1 < L_NUM_AWADDR_EQ_LANES) begin\n      AWADDR_stage_1_eq[AWADDR_stage_1] <= &AWADDR_eq[AWADDR_stage_1*8 +:8];\n    end else begin\n      AWADDR_stage_1_eq[AWADDR_stage_1] <= 1'b1;\n    end\n  end\n\n  for (AWADDR_stage_2 = 0; AWADDR_stage_2 < L_NUM_AWADDR_AND2_LANES * 8;AWADDR_stage_2 = AWADDR_stage_2 + 1) begin : AWADDR_S2\n    if (AWADDR_stage_2 < L_NUM_AWADDR_AND1_LANES) begin\n      AWADDR_stage_2_eq[AWADDR_stage_2] <= &AWADDR_stage_1_eq[AWADDR_stage_2*8 +:8];\n    end else begin\n      AWADDR_stage_2_eq[AWADDR_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n  //---------------\n  //ASR_11 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWBURST) ) );\n  //---------------\n  always @(posedge ACLK)\n    s5<=AWBURST;\n  assign s6 = s5 == AWBURST;\n  always @(posedge ACLK) if (`AKRPS reset) s7sq<=3'h4; else\n    s7sq<=s7s;\n  assign s7s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s7sq[1] && (ARESETn && !(s6)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_11<=0; else\n    ASR_11 <= (s7s[0]);\n\n  //---------------\n  //ASR_12 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWCACHE) ) );\n  //---------------\n  always @(posedge ACLK)\n    s8<=AWCACHE;\n  assign s9 = s8 == AWCACHE;\n  always @(posedge ACLK) if (`AKRPS reset) s10sq<=3'h4; else\n    s10sq<=s10s;\n  assign s10s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s10sq[1] && (ARESETn && !(s9)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_12<=0; else\n    ASR_12 <= (s10s[0]);\n\n  //---------------\n  //ASR_13 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWID) ) );\n  //---------------\n  always @(posedge ACLK)\n    s11<=AWID;\n  assign s12 = s11 == AWID;\n  always @(posedge ACLK) if (`AKRPS reset) s13sq<=3'h4; else\n    s13sq<=s13s;\n  assign s13s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s13sq[1] && (ARESETn && !(s12)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_13<=0; else\n    ASR_13 <= (s13s[0]);\n\n  //---------------\n  //ASR_14 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWLEN) ) );\n  //---------------\n  always @(posedge ACLK)\n    s14<=AWLEN;\n  assign s15 = s14 == AWLEN;\n  always @(posedge ACLK) if (`AKRPS reset) s16sq<=3'h4; else\n    s16sq<=s16s;\n  assign s16s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s16sq[1] && (ARESETn && !(s15)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_14<=0; else\n    ASR_14 <= (s16s[0]);\n\n  //---------------\n  //ASR_15 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWLOCK) ) );\n  //---------------\n  always @(posedge ACLK)\n    s17<=AWLOCK;\n  assign s18 = s17 == AWLOCK;\n  always @(posedge ACLK) if (`AKRPS reset) s19sq<=3'h4; else\n    s19sq<=s19s;\n  assign s19s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s19sq[1] && (ARESETn && !(s18)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_15<=0; else\n    ASR_15 <= (s19s[0]);\n\n  //---------------\n  //ASR_16 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWPROT) ) );\n  //---------------\n  always @(posedge ACLK)\n    s20<=AWPROT;\n  assign s21 = s20 == AWPROT;\n  always @(posedge ACLK) if (`AKRPS reset) s22sq<=3'h4; else\n    s22sq<=s22s;\n  assign s22s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s22sq[1] && (ARESETn && !(s21)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_16<=0; else\n    ASR_16 <= (s22s[0]);\n\n  //---------------\n  //ASR_17 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWSIZE) ) );\n  //---------------\n  always @(posedge ACLK)\n    s23<=AWSIZE;\n  assign s24 = s23 == AWSIZE;\n  always @(posedge ACLK) if (`AKRPS reset) s25sq<=3'h4; else\n    s25sq<=s25s;\n  assign s25s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s25sq[1] && (ARESETn && !(s24)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_17<=0; else\n    ASR_17 <= (s25s[0]);\n\n  //---------------\n  //ASR_18 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWQOS) ) );\n  //---------------\n  always @(posedge ACLK)\n    s26<=AWQOS;\n  assign s27 = s26 == AWQOS;\n  always @(posedge ACLK) if (`AKRPS reset) s28sq<=3'h4; else\n    s28sq<=s28s;\n  assign s28s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s28sq[1] && (ARESETn && !(s27)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_18<=0; else\n    ASR_18 <= (s28s[0]);\n\n  //---------------\n  //ASR_19 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWREGION) ) );\n  //---------------\n  always @(posedge ACLK)\n    s29<=AWREGION;\n  assign s30 = s29 == AWREGION;\n  always @(posedge ACLK) if (`AKRPS reset) s31sq<=3'h4; else\n    s31sq<=s31s;\n  assign s31s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s31sq[1] && (ARESETn && !(s30)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_19<=0; else\n    ASR_19 <= (s31s[0]);\n\n  //---------------\n  //ASR_20 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> AWVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s32sq<=3'h4; else\n    s32sq<=s32s;\n  assign s32s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s32sq[1] && (ARESETn && !(AWVALID)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_20<=0; else\n    ASR_20 <= (s32s[0]);\n\n  //---------------\n  //ASR_21 : assert property ( @(posedge ACLK) ( ARESETn & i_RecommendOn & i_RecMaxWaitOn & ( AWVALID & ! AWREADY ) |-> ##[1:16] ( ! AWVALID | AWREADY ) ) );\n  //---------------\n\n  reg [L_AW_WAIT_WIDTH-1:0]  aw_cnt;\n  wire asr_21_set;\n\n  generate\n    if (MAX_AW_WAITS > 0) begin : gen_aw_wait\n      always @(posedge ACLK) begin\n        if (`AKRPS reset) begin\n          aw_cnt <= {L_AW_WAIT_WIDTH{1'b0}};\n        end else begin\n          //Valid, not ready, clken\n          if (((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) & ( AWVALID & ! AWREADY )) begin\n            aw_cnt <= aw_cnt + 1;\n          end else begin\n            aw_cnt <= {L_AW_WAIT_WIDTH{1'b0}};\n          end\n        end\n      end\n\n      assign asr_21_set = (aw_cnt == MAX_AW_WAITS) & (AWVALID & ! AWREADY);\n    end else begin : gen_no_aw_wait\n      assign asr_21_set = 1'b0;\n    end\n  endgenerate\n\n  always @(posedge ACLK) if (`AKRPS reset) ASR_21<=0; else\n    ASR_21 <= asr_21_set;\n\n  //---------------\n  //ASR_22 : assert property ( @(posedge ACLK) ( ARESETn |-> ~ WriteDataNumError ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_22<=0; else\n    ASR_22 <= ((ARESETn && WriteDataNumError));\n\n  //---------------\n  //ASR_23 : assert property ( @(posedge ACLK) ( ARESETn |-> ~ BStrbError ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_23<=0; else\n    ASR_23 <= ((ARESETn && BStrbError));\n\n  //---------------\n  //ASR_24 : assert property ( @(posedge ACLK) ( ! ( ARESETn ) ##1 ARESETn |-> ! WVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s34sq<=3'h4; else\n    s34sq<=s34s;\n  assign s34s={1'b1,\n    !(ARESETn),\n    (s34sq[1] && (ARESETn && WVALID))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_24<=0; else\n    ASR_24 <= (s34s[0]);\n\n  //---------------\n  //ASR_25 : assert property ( @(posedge ACLK) ( ARESETn & WVALID & ! WREADY ##1 ARESETn |-> $stable(WDATA) ) );\n//  //---------------\n//  always @(posedge ACLK)\n//    s35<=WDATA;\n//  assign s36 = s35 == WDATA;\n//  always @(posedge ACLK) if (`AKRPS reset) s37sq<=3'h4; else\n//    s37sq<=s37s;\n//  assign s37s={1'b1,\n//    ((ARESETn & WVALID) & (! WREADY)),\n//    (s37sq[1] && (ARESETn && !(s36)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_25<=0; else\n//    ASR_25 <= (s37s[0]);\n\nlocalparam integer L_NUM_WDATA_BYTES       = ((DATA_WIDTH + 7) / 8);\nlocalparam integer L_NUM_WDATA_BYTE_LANES  = ((L_NUM_WDATA_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_WDATA_EQ_LANES    = (L_NUM_WDATA_BYTE_LANES / 8);\nlocalparam integer L_NUM_WDATA_AND1_LANES  = (L_NUM_WDATA_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_WDATA_AND2_LANES  = (L_NUM_WDATA_AND1_LANES + 7) / 8;\n\nreg   [DATA_WIDTH - 1:0]  WDATA_q;\nreg   [4:0]               s_WDATA_sq;\nwire  [4:0]               s_WDATA_s;\nwire                      s_WDATA_sqaa;\n\nreg [(8*L_NUM_WDATA_EQ_LANES)-1:0]    WDATA_eq;\nreg [(8*L_NUM_WDATA_AND1_LANES)-1:0]  WDATA_stage_1_eq;\nreg [(8*L_NUM_WDATA_AND2_LANES)-1:0]  WDATA_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_WDATA_sq<=5'h00; \n    ASR_25 <=0;\n  end else begin\n    s_WDATA_sq<=s_WDATA_s;\n    ASR_25 <= (s_WDATA_s[0]);\n  end\nend\n\nassign s_WDATA_s={\n  (((ARESETn & WVALID) & (! WREADY))),\n  (s_WDATA_sq[4] && ARESETn),\n  (s_WDATA_sq[3]),\n  (s_WDATA_sq[2]),\n  (s_WDATA_sq[1] & !(s_WDATA_sqaa))\n  };\n\nassign s_WDATA_sqaa = &WDATA_stage_2_eq;\n\ninteger WDATA_bc;\ninteger WDATA_stage_1;\ninteger WDATA_stage_2;\n\nalways @(posedge ACLK) begin\n  WDATA_q<=WDATA;\n\n  for (WDATA_bc = 0; WDATA_bc < L_NUM_WDATA_EQ_LANES*8; WDATA_bc = WDATA_bc + 1) begin : WDATA_BC_LOOP\n    if (WDATA_bc < L_NUM_WDATA_BYTES) begin\n      WDATA_eq[WDATA_bc] <= WDATA_q[WDATA_bc*8 +:8] == WDATA[WDATA_bc*8 +: 8];\n    end else begin\n      WDATA_eq[WDATA_bc] <= 1'b1;\n    end\n  end\n\n  for (WDATA_stage_1 = 0; WDATA_stage_1 < L_NUM_WDATA_AND1_LANES * 8;WDATA_stage_1 = WDATA_stage_1 + 1) begin : WDATA_S1\n    if (WDATA_stage_1 < L_NUM_WDATA_EQ_LANES) begin\n      WDATA_stage_1_eq[WDATA_stage_1] <= &WDATA_eq[WDATA_stage_1*8 +:8];\n    end else begin\n      WDATA_stage_1_eq[WDATA_stage_1] <= 1'b1;\n    end\n  end\n\n  for (WDATA_stage_2 = 0; WDATA_stage_2 < L_NUM_WDATA_AND2_LANES * 8;WDATA_stage_2 = WDATA_stage_2 + 1) begin : WDATA_S2\n    if (WDATA_stage_2 < L_NUM_WDATA_AND1_LANES) begin\n      WDATA_stage_2_eq[WDATA_stage_2] <= &WDATA_stage_1_eq[WDATA_stage_2*8 +:8];\n    end else begin\n      WDATA_stage_2_eq[WDATA_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n\n  //---------------\n  //ASR_26 : assert property ( @(posedge ACLK) ( ARESETn & WVALID & ! WREADY ##1 ARESETn |-> $stable(WLAST) ) );\n  //---------------\n  always @(posedge ACLK)\n    s38<=WLAST;\n  assign s39 = s38 == WLAST;\n  always @(posedge ACLK) if (`AKRPS reset) s40sq<=3'h4; else\n    s40sq<=s40s;\n  assign s40s={1'b1,\n    ((ARESETn & WVALID) & (! WREADY)),\n    (s40sq[1] && (ARESETn && !(s39)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_26<=0; else\n    ASR_26 <= (s40s[0]);\n\n  //---------------\n  //ASR_27 : assert property ( @(posedge ACLK) ( ARESETn & WVALID & ! WREADY ##1 ARESETn |-> $stable(WSTRB) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s41<=WSTRB;\n//  assign s42 = s41 == WSTRB;\n//  always @(posedge ACLK) if (`AKRPS reset) s43sq<=3'h4; else\n//    s43sq<=s43s;\n//  assign s43s={1'b1,\n//    ((ARESETn & WVALID) & (! WREADY)),\n//    (s43sq[1] && (ARESETn && !(s42)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_27<=0; else\n//    ASR_27 <= (s43s[0]);\nlocalparam integer L_NUM_WSTRB_BYTES       = (((DATA_WIDTH/8) + 7) / 8);\nlocalparam integer L_NUM_WSTRB_BYTE_LANES  = ((L_NUM_WSTRB_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_WSTRB_EQ_LANES    = (L_NUM_WSTRB_BYTE_LANES / 8);\nlocalparam integer L_NUM_WSTRB_AND1_LANES  = (L_NUM_WSTRB_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_WSTRB_AND2_LANES  = (L_NUM_WSTRB_AND1_LANES + 7) / 8;\n\nreg   [(DATA_WIDTH/8) - 1:0] WSTRB_q;\nreg   [4:0]               s_WSTRB_sq;\nwire  [4:0]               s_WSTRB_s;\nwire                      s_WSTRB_sqaa;\n\nreg [(8*L_NUM_WSTRB_EQ_LANES)-1:0]    WSTRB_eq;\nreg [(8*L_NUM_WSTRB_AND1_LANES)-1:0]  WSTRB_stage_1_eq;\nreg [(8*L_NUM_WSTRB_AND2_LANES)-1:0]  WSTRB_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_WSTRB_sq<=5'h00; \n    ASR_27 <=0;\n  end else begin\n    s_WSTRB_sq<=s_WSTRB_s;\n    ASR_27 <= (s_WSTRB_s[0]);\n  end\nend\n\nassign s_WSTRB_s={\n  (((ARESETn & WVALID) & (! WREADY))),\n  (s_WSTRB_sq[4] && ARESETn),\n  (s_WSTRB_sq[3]),\n  (s_WSTRB_sq[2]),\n  (s_WSTRB_sq[1] & !(s_WSTRB_sqaa))\n  };\n\nassign s_WSTRB_sqaa = &WSTRB_stage_2_eq;\n\nwire  [(L_NUM_WSTRB_BYTES*8)-1:0]      WSTRB_expand;\nwire  [(L_NUM_WSTRB_BYTES*8)-1:0]      WSTRBsqa_expand;\ngenvar WSTRB_bit;\ngenerate\n  ///////////////////////////////////////////////////////////////////////////////////////////\n  //Expand the WSTRB up to the nearest byte\n  for (WSTRB_bit = 0; WSTRB_bit < (L_NUM_WSTRB_BYTES * 8); WSTRB_bit = WSTRB_bit + 1) begin : WSTRB_BIT_LOOP\n    if (WSTRB_bit < (DATA_WIDTH/8)) begin : VAL\n      assign WSTRB_expand[WSTRB_bit] = WSTRB[WSTRB_bit];\n      assign WSTRBsqa_expand[WSTRB_bit] = WSTRB_q[WSTRB_bit];\n    end else begin\n      assign WSTRB_expand[WSTRB_bit] = 1'b0;\n      assign WSTRBsqa_expand[WSTRB_bit] = 1'b0;\n    end\n  end\nendgenerate\n\ninteger WSTRB_bc;\ninteger WSTRB_stage_1;\ninteger WSTRB_stage_2;\n\nalways @(posedge ACLK) begin\n  WSTRB_q<=WSTRB;\n\n  for (WSTRB_bc = 0; WSTRB_bc < L_NUM_WSTRB_EQ_LANES*8; WSTRB_bc = WSTRB_bc + 1) begin : WSTRB_BC_LOOP\n    if (WSTRB_bc < L_NUM_WSTRB_BYTES) begin\n      WSTRB_eq[WSTRB_bc] <= WSTRB_expand[WSTRB_bc*8 +:8] == WSTRBsqa_expand[WSTRB_bc*8 +: 8];\n    end else begin\n      WSTRB_eq[WSTRB_bc] <= 1'b1;\n    end\n  end\n\n  for (WSTRB_stage_1 = 0; WSTRB_stage_1 < L_NUM_WSTRB_AND1_LANES * 8;WSTRB_stage_1 = WSTRB_stage_1 + 1) begin : WSTRB_S1\n    if (WSTRB_stage_1 < L_NUM_WSTRB_EQ_LANES) begin\n      WSTRB_stage_1_eq[WSTRB_stage_1] <= &WSTRB_eq[WSTRB_stage_1*8 +:8];\n    end else begin\n      WSTRB_stage_1_eq[WSTRB_stage_1] <= 1'b1;\n    end\n  end\n\n  for (WSTRB_stage_2 = 0; WSTRB_stage_2 < L_NUM_WSTRB_AND2_LANES * 8;WSTRB_stage_2 = WSTRB_stage_2 + 1) begin : WSTRB_S2\n    if (WSTRB_stage_2 < L_NUM_WSTRB_AND1_LANES) begin\n      WSTRB_stage_2_eq[WSTRB_stage_2] <= &WSTRB_stage_1_eq[WSTRB_stage_2*8 +:8];\n    end else begin\n      WSTRB_stage_2_eq[WSTRB_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n  //---------------\n  //ASR_28 : assert property ( @(posedge ACLK) ( ARESETn & WVALID & ! WREADY ##1 ARESETn |-> WVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s44sq<=3'h4; else\n    s44sq<=s44s;\n  assign s44s={1'b1,\n    ((ARESETn & WVALID) & (! WREADY)),\n    (s44sq[1] && (ARESETn && !(WVALID)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_28<=0; else\n    ASR_28 <= (s44s[0]);\n\n  //---------------\n  //ASR_29 : assert property ( @(posedge ACLK) ( ARESETn & i_RecommendOn & i_RecMaxWaitOn & ( WVALID & ! WREADY ) |-> ##[1:16] ( ! WVALID | WREADY ) ) );\n  //---------------\n  reg [L_W_WAIT_WIDTH-1:0]  w_cnt;\n  wire asr_29_set;\n\n  generate\n    if (MAX_W_WAITS > 0) begin : gen_w_wait\n      always @(posedge ACLK) begin\n        if (`AKRPS reset) begin\n          w_cnt <= {L_W_WAIT_WIDTH{1'b0}};\n        end else begin\n          //Valid, not ready, clken\n          if (((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) & ( WVALID & ! WREADY )) begin\n            w_cnt <= w_cnt + 1;\n          end else begin\n            w_cnt <= {L_W_WAIT_WIDTH{1'b0}};\n          end\n        end\n      end\n\n      assign asr_29_set = (w_cnt == MAX_W_WAITS) & ( WVALID & ! WREADY );\n    end else begin : gen_no_w_wait\n      assign asr_29_set = 1'b0;\n    end\n  endgenerate\n\n  always @(posedge ACLK) if (`AKRPS reset) ASR_29<=0; else\n    ASR_29 <= asr_29_set;\n\n  //---------------\n  //ASR_30 : assert property ( @(posedge ACLK) ( ARESETn |-> ~ BrespErrorLast ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_30<=0; else\n    ASR_30 <= ((ARESETn && BrespErrorLast));\n\n  //---------------\n  //ASR_31 : assert property ( @(posedge ACLK) ( ARESETn |-> ~ BrespExokError ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_31<=0; else\n    ASR_31 <= ((ARESETn && BrespExokError));\n\n  //---------------\n  //ASR_32 : assert property ( @(posedge ACLK) ( ! ( ARESETn ) ##1 ARESETn |-> ! BVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s46sq<=3'h4; else\n    s46sq<=s46s;\n  assign s46s={1'b1,\n    !(ARESETn),\n    (s46sq[1] && (ARESETn && BVALID))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_32<=0; else\n    ASR_32 <= (s46s[0]);\n\n  //---------------\n  //ASR_33 : assert property ( @(posedge ACLK) ( ARESETn |-> ~ BrespErrorLead ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_33<=0; else\n    ASR_33 <= ((ARESETn && BrespErrorLead));\n\n  //---------------\n  //ASR_34 : assert property ( @(posedge ACLK) ( ARESETn & BVALID & ! BREADY ##1 ARESETn |-> $stable(BID) ) );\n  //---------------\n  always @(posedge ACLK)\n    s47<=BID;\n  assign s48 = s47 == BID;\n  always @(posedge ACLK) if (`AKRPS reset) s49sq<=3'h4; else\n    s49sq<=s49s;\n  assign s49s={1'b1,\n    ((ARESETn & BVALID) & (! BREADY)),\n    (s49sq[1] && (ARESETn && !(s48)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_34<=0; else\n    ASR_34 <= (s49s[0]);\n\n  //---------------\n  //ASR_35 : assert property ( @(posedge ACLK) ( ARESETn & BVALID & ! BREADY ##1 ARESETn |-> $stable(BRESP) ) );\n  //---------------\n  always @(posedge ACLK)\n    s50<=BRESP;\n  assign s51 = s50 == BRESP;\n  always @(posedge ACLK) if (`AKRPS reset) s52sq<=3'h4; else\n    s52sq<=s52s;\n  assign s52s={1'b1,\n    ((ARESETn & BVALID) & (! BREADY)),\n    (s52sq[1] && (ARESETn && !(s51)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_35<=0; else\n    ASR_35 <= (s52s[0]);\n\n  //---------------\n  //ASR_36 : assert property ( @(posedge ACLK) ( ARESETn & BVALID & ! BREADY ##1 ARESETn |-> BVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s53sq<=3'h4; else\n    s53sq<=s53s;\n  assign s53s={1'b1,\n    ((ARESETn & BVALID) & (! BREADY)),\n    (s53sq[1] && (ARESETn && !(BVALID)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_36<=0; else\n    ASR_36 <= (s53s[0]);\n\n  //---------------\n  //ASR_37 : assert property ( @(posedge ACLK) ( ARESETn & i_RecommendOn & i_RecMaxWaitOn & ( BVALID & ! BREADY ) |-> ##[1:16] ( ! BVALID | BREADY ) ) );\n  //---------------\n  reg [L_B_WAIT_WIDTH-1:0]  b_cnt;\n  wire asr_37_set;\n\n  generate\n    if (MAX_B_WAITS > 0) begin : gen_b_wait\n      always @(posedge ACLK) begin\n        if (`AKRPS reset) begin\n          b_cnt <= {L_B_WAIT_WIDTH{1'b0}};\n        end else begin\n          //Valid, not ready, clken\n          if (((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) & ( BVALID & ! BREADY )) begin\n            b_cnt <= b_cnt + 1;\n          end else begin\n            b_cnt <= {L_B_WAIT_WIDTH{1'b0}};\n          end\n        end\n      end\n\n      assign asr_37_set = (b_cnt == MAX_B_WAITS) & ( BVALID & ! BREADY );\n\n    end else begin : gen_no_b_wait\n      assign asr_37_set = 1'b0;\n    end\n  endgenerate\n\n  always @(posedge ACLK) if (`AKRPS reset) ASR_37<=0; else\n    ASR_37 <= asr_37_set;\n\n  //---------------\n  //ASR_38 : assert property ( @(posedge ACLK) ( ARVALID & ( ARBURST == 2'b1 ) |-> ( ArAddrIncr[ADDR_MAX:12] == ARADDR[ADDR_MAX:12] ) ) );\n  //---------------\n  reg [ADDR_MAX-12:0] ArAddrIncr_q1;\n  reg [ADDR_MAX-12:0] ARADDR_q1;\n  reg                 asr_38_ctrl;\n  \n  always @(posedge ACLK) begin\n    ArAddrIncr_q1 <= ArAddrIncr[ADDR_MAX:12];\n    ARADDR_q1     <= ARADDR[ADDR_MAX:12];\n    asr_38_ctrl   <= (ARVALID & ( (ARBURST == 2'b1) ));\n  end\n  \n  always @(posedge ACLK) if (`AKRPS reset) ASR_38<=0; else\n    ASR_38 <= asr_38_ctrl && !(ArAddrIncr_q1 == ARADDR_q1);\n\n  //---------------\n  //ASR_39 : assert property ( @(posedge ACLK) ( ARVALID & ( ARBURST == 2'b10 ) |-> ( ( ARADDR[6:0] & AlignMaskR ) == ARADDR[6:0] ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_39<=0; else\n    ASR_39 <= (((ARVALID & ( (ARBURST == 2'b10) )) && !((( (ARADDR[6:0] & AlignMaskR) ) == ARADDR[6:0]))));\n\n  //---------------\n  //ASR_40 : assert property ( @(posedge ACLK) ( ARVALID |-> ( ARBURST != 2'b11 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_40<=0; else\n    ASR_40 <= ((ARVALID && !((ARBURST != 2'b11))));\n\n  //---------------\n  //ASR_41 : assert property ( @(posedge ACLK) ( ARVALID & ARLEN > 8'b1111 |-> ( ARLOCK != 1'b1 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_41<=0; else\n    ASR_41 <= (((ARVALID & (ARLEN > 8'b1111)) && !((ARLOCK != 1'b1))));\n\n  //---------------\n  //ASR_42 : assert property ( @(posedge ACLK) ( ARVALID & ~ ARCACHE[1] |-> ( ARCACHE[3:2] == 2'b0 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_42<=0; else\n    ASR_42 <= (((ARVALID & (~ ARCACHE[1])) && !((ARCACHE[3:2] == 2'b0))));\n\n  //---------------\n  //ASR_43 : assert property ( @(posedge ACLK) ( ARVALID & ARLEN > 8'b1111 |-> ( ARBURST != 2'b0 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_43<=0; else\n    ASR_43 <= (((ARVALID & (ARLEN > 8'b1111)) && !((ARBURST != 2'b0))));\n\n  //---------------\n  //ASR_44 : assert property ( @(posedge ACLK) ( ARVALID & ( ARBURST == 2'b10 ) |-> ( ARLEN == 8'b1 || ARLEN == 8'b11 || ARLEN == 8'b111 || ARLEN == 8'b1111 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_44<=0; else\n    ASR_44 <= (((ARVALID & ( (ARBURST == 2'b10) )) && !(((((ARLEN == 8'b1) || (ARLEN == 8'b11)) || (ARLEN == 8'b111)) || (ARLEN == 8'b1111)))));\n\n  //---------------\n  //ASR_45 : assert property ( @(posedge ACLK) ( ARVALID |-> ( ArSizeInBits <= DATA_WIDTH ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_45<=0; else\n    ASR_45 <= ((ARVALID && !((ArSizeInBits <= DATA_WIDTH))));\n\n  //---------------\n  //ASR_46 : assert property ( @(posedge ACLK) ( ! ( ARESETn ) ##1 ARESETn |-> ! ARVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s55sq<=3'h4; else\n    s55sq<=s55s;\n  assign s55s={1'b1,\n    !(ARESETn),\n    (s55sq[1] && (ARESETn && ARVALID))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_46<=0; else\n    ASR_46 <= (s55s[0]);\n\n  //---------------\n  //ASR_47 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARADDR) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s56<=ARADDR;\n//  assign s57 = s56 == ARADDR;\n//  always @(posedge ACLK) if (`AKRPS reset) s58sq<=3'h4; else\n//    s58sq<=s58s;\n//  assign s58s={1'b1,\n//    ((ARESETn & ARVALID) & (! ARREADY)),\n//    (s58sq[1] && (ARESETn && !(s57)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_47<=0; else\n//    ASR_47 <= (s58s[0]);\nlocalparam integer L_NUM_ARADDR_BYTES       = ((ADDR_WIDTH + 7) / 8);\nlocalparam integer L_NUM_ARADDR_BYTE_LANES  = ((L_NUM_ARADDR_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_ARADDR_EQ_LANES    = (L_NUM_ARADDR_BYTE_LANES / 8);\nlocalparam integer L_NUM_ARADDR_AND1_LANES  = (L_NUM_ARADDR_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_ARADDR_AND2_LANES  = (L_NUM_ARADDR_AND1_LANES + 7) / 8;\n\nreg   [ADDR_WIDTH - 1:0] ARADDR_q;\nreg   [4:0]               s_ARADDR_sq;\nwire  [4:0]               s_ARADDR_s;\nwire                      s_ARADDR_sqaa;\n\nreg [(8*L_NUM_ARADDR_EQ_LANES)-1:0]    ARADDR_eq;\nreg [(8*L_NUM_ARADDR_AND1_LANES)-1:0]  ARADDR_stage_1_eq;\nreg [(8*L_NUM_ARADDR_AND2_LANES)-1:0]  ARADDR_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_ARADDR_sq<=5'h00; \n    ASR_47 <=0;\n  end else begin\n    s_ARADDR_sq<=s_ARADDR_s;\n    ASR_47 <= (s_ARADDR_s[0]);\n  end\nend\n\nassign s_ARADDR_s={\n  (((ARESETn & ARVALID) & (! ARREADY))),\n  (s_ARADDR_sq[4] && ARESETn),\n  (s_ARADDR_sq[3]),\n  (s_ARADDR_sq[2]),\n  (s_ARADDR_sq[1] & !(s_ARADDR_sqaa))\n  };\n\nassign s_ARADDR_sqaa = &ARADDR_stage_2_eq;\n\nwire  [(L_NUM_ARADDR_BYTES*8)-1:0]      ARADDR_expand;\nwire  [(L_NUM_ARADDR_BYTES*8)-1:0]      ARADDRsqa_expand;\ngenvar ARADDR_bit;\ngenerate\n  ///////////////////////////////////////////////////////////////////////////////////////////\n  //Expand the ARADDR up to the nearest byte\n  for (ARADDR_bit = 0; ARADDR_bit < (L_NUM_ARADDR_BYTES * 8); ARADDR_bit = ARADDR_bit + 1) begin : ARADDR_BIT_LOOP\n    if (ARADDR_bit < ADDR_WIDTH) begin : VAL\n      assign ARADDR_expand[ARADDR_bit] = ARADDR[ARADDR_bit];\n      assign ARADDRsqa_expand[ARADDR_bit] = ARADDR_q[ARADDR_bit];\n    end else begin\n      assign ARADDR_expand[ARADDR_bit] = 1'b0;\n      assign ARADDRsqa_expand[ARADDR_bit] = 1'b0;\n    end\n  end\nendgenerate\n\ninteger ARADDR_bc;\ninteger ARADDR_stage_1;\ninteger ARADDR_stage_2;\n\nalways @(posedge ACLK) begin\n  ARADDR_q<=ARADDR;\n\n  for (ARADDR_bc = 0; ARADDR_bc < L_NUM_ARADDR_EQ_LANES*8; ARADDR_bc = ARADDR_bc + 1) begin : ARADDR_BC_LOOP\n    if (ARADDR_bc < L_NUM_ARADDR_BYTES) begin\n      ARADDR_eq[ARADDR_bc] <= ARADDR_expand[ARADDR_bc*8 +:8] == ARADDRsqa_expand[ARADDR_bc*8 +: 8];\n    end else begin\n      ARADDR_eq[ARADDR_bc] <= 1'b1;\n    end\n  end\n\n  for (ARADDR_stage_1 = 0; ARADDR_stage_1 < L_NUM_ARADDR_AND1_LANES * 8;ARADDR_stage_1 = ARADDR_stage_1 + 1) begin : ARADDR_S1\n    if (ARADDR_stage_1 < L_NUM_ARADDR_EQ_LANES) begin\n      ARADDR_stage_1_eq[ARADDR_stage_1] <= &ARADDR_eq[ARADDR_stage_1*8 +:8];\n    end else begin\n      ARADDR_stage_1_eq[ARADDR_stage_1] <= 1'b1;\n    end\n  end\n\n  for (ARADDR_stage_2 = 0; ARADDR_stage_2 < L_NUM_ARADDR_AND2_LANES * 8;ARADDR_stage_2 = ARADDR_stage_2 + 1) begin : ARADDR_S2\n    if (ARADDR_stage_2 < L_NUM_ARADDR_AND1_LANES) begin\n      ARADDR_stage_2_eq[ARADDR_stage_2] <= &ARADDR_stage_1_eq[ARADDR_stage_2*8 +:8];\n    end else begin\n      ARADDR_stage_2_eq[ARADDR_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n  //---------------\n  //ASR_48 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARBURST) ) );\n  //---------------\n  always @(posedge ACLK)\n    s59<=ARBURST;\n  assign s60 = s59 == ARBURST;\n  always @(posedge ACLK) if (`AKRPS reset) s61sq<=3'h4; else\n    s61sq<=s61s;\n  assign s61s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s61sq[1] && (ARESETn && !(s60)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_48<=0; else\n    ASR_48 <= (s61s[0]);\n\n  //---------------\n  //ASR_49 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARCACHE) ) );\n  //---------------\n  always @(posedge ACLK)\n    s62<=ARCACHE;\n  assign s63 = s62 == ARCACHE;\n  always @(posedge ACLK) if (`AKRPS reset) s64sq<=3'h4; else\n    s64sq<=s64s;\n  assign s64s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s64sq[1] && (ARESETn && !(s63)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_49<=0; else\n    ASR_49 <= (s64s[0]);\n\n  //---------------\n  //ASR_50 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARID) ) );\n  //---------------\n  always @(posedge ACLK)\n    s65<=ARID;\n  assign s66 = s65 == ARID;\n  always @(posedge ACLK) if (`AKRPS reset) s67sq<=3'h4; else\n    s67sq<=s67s;\n  assign s67s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s67sq[1] && (ARESETn && !(s66)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_50<=0; else\n    ASR_50 <= (s67s[0]);\n\n  //---------------\n  //ASR_51 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARLEN) ) );\n  //---------------\n  always @(posedge ACLK)\n    s68<=ARLEN;\n  assign s69 = s68 == ARLEN;\n  always @(posedge ACLK) if (`AKRPS reset) s70sq<=3'h4; else\n    s70sq<=s70s;\n  assign s70s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s70sq[1] && (ARESETn && !(s69)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_51<=0; else\n    ASR_51 <= (s70s[0]);\n\n  //---------------\n  //ASR_52 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARLOCK) ) );\n  //---------------\n  always @(posedge ACLK)\n    s71<=ARLOCK;\n  assign s72 = s71 == ARLOCK;\n  always @(posedge ACLK) if (`AKRPS reset) s73sq<=3'h4; else\n    s73sq<=s73s;\n  assign s73s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s73sq[1] && (ARESETn && !(s72)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_52<=0; else\n    ASR_52 <= (s73s[0]);\n\n  //---------------\n  //ASR_53 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARPROT) ) );\n  //---------------\n  always @(posedge ACLK)\n    s74<=ARPROT;\n  assign s75 = s74 == ARPROT;\n  always @(posedge ACLK) if (`AKRPS reset) s76sq<=3'h4; else\n    s76sq<=s76s;\n  assign s76s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s76sq[1] && (ARESETn && !(s75)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_53<=0; else\n    ASR_53 <= (s76s[0]);\n\n  //---------------\n  //ASR_54 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARSIZE) ) );\n  //---------------\n  always @(posedge ACLK)\n    s77<=ARSIZE;\n  assign s78 = s77 == ARSIZE;\n  always @(posedge ACLK) if (`AKRPS reset) s79sq<=3'h4; else\n    s79sq<=s79s;\n  assign s79s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s79sq[1] && (ARESETn && !(s78)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_54<=0; else\n    ASR_54 <= (s79s[0]);\n\n  //---------------\n  //ASR_55 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARQOS) ) );\n  //---------------\n  always @(posedge ACLK)\n    s80<=ARQOS;\n  assign s81 = s80 == ARQOS;\n  always @(posedge ACLK) if (`AKRPS reset) s82sq<=3'h4; else\n    s82sq<=s82s;\n  assign s82s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s82sq[1] && (ARESETn && !(s81)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_55<=0; else\n    ASR_55 <= (s82s[0]);\n\n  //---------------\n  //ASR_56 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARREGION) ) );\n  //---------------\n  always @(posedge ACLK)\n    s83<=ARREGION;\n  assign s84 = s83 == ARREGION;\n  always @(posedge ACLK) if (`AKRPS reset) s85sq<=3'h4; else\n    s85sq<=s85s;\n  assign s85s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s85sq[1] && (ARESETn && !(s84)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_56<=0; else\n    ASR_56 <= (s85s[0]);\n\n  //---------------\n  //ASR_57 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> ARVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s86sq<=3'h4; else\n    s86sq<=s86s;\n  assign s86s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s86sq[1] && (ARESETn && !(ARVALID)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_57<=0; else\n    ASR_57 <= (s86s[0]);\n\n  //---------------\n  //ASR_58 : assert property ( @(posedge ACLK) ( ARESETn & i_RecommendOn & i_RecMaxWaitOn & ( ARVALID & ! ARREADY ) |-> ##[1:16] ( ! ARVALID | ARREADY ) ) );\n  //---------------\n  reg [L_AR_WAIT_WIDTH-1:0]  ar_cnt;\n  wire asr_58_set;\n\n  generate\n    if (MAX_AR_WAITS > 0) begin : gen_ar_wait\n      always @(posedge ACLK) begin\n        if (`AKRPS reset) begin\n          ar_cnt <= {L_AR_WAIT_WIDTH{1'b0}};\n        end else begin\n          //Valid, not ready, clken\n          if (((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) & ( ARVALID & ! ARREADY )) begin\n            ar_cnt <= ar_cnt + 1;\n          end else begin\n            ar_cnt <= {L_AR_WAIT_WIDTH{1'b0}};\n          end\n        end\n      end\n\n      assign asr_58_set = (ar_cnt == MAX_AR_WAITS) & ( ARVALID & ! ARREADY );\n\n    end else begin : gen_no_ar_wait\n      assign asr_58_set = 1'b0;\n    end\n  endgenerate\n\n  always @(posedge ACLK) if (`AKRPS reset) ASR_58<=0; else\n    ASR_58 <= asr_58_set;\n\n  //---------------\n  //ASR_59 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & RREADY |-> ( ( ( ArCountPending == ArLenPending ) & RLAST ) | ( ( ArCountPending != ArLenPending ) & ~ RLAST ) ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_59<=0; else\n    ASR_59 <= ((((ARESETn & RVALID) & RREADY) && !((( (( (ArCountPending == ArLenPending) ) & RLAST) ) | ( (( (ArCountPending != ArLenPending) ) & (~ RLAST)) )))));\n\n  //---------------\n  //ASR_60 : assert property ( @(posedge ACLK) ( ARESETn & RVALID |-> ( RidMatch > 0 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_60<=0; else\n    ASR_60 <= (((ARESETn & RVALID) && !((RidMatch > 0))));\n\n  //---------------\n  //ASR_61 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & RREADY & ( RRESP == 2'b1 ) |-> ( ArExclPending ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_61<=0; else\n    ASR_61 <= (((((ARESETn & RVALID) & RREADY) & ( (RRESP == 2'b1) )) && !(ArExclPending)));\n\n  //---------------\n  //ASR_62 : assert property ( @(posedge ACLK) ( ! ( ARESETn ) ##1 ARESETn |-> ! RVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s88sq<=3'h4; else\n    s88sq<=s88s;\n  assign s88s={1'b1,\n    !(ARESETn),\n    (s88sq[1] && (ARESETn && RVALID))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_62<=0; else\n    ASR_62 <= (s88s[0]);\n\n  //---------------\n  //ASR_63 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> $stable(RDATA) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s89<=RDATA;\n//  assign s90 = s89 == RDATA;\n//  always @(posedge ACLK) if (`AKRPS reset) s91sq<=3'h4; else\n//    s91sq<=s91s;\n//  assign s91s={1'b1,\n//    ((ARESETn & RVALID) & (! RREADY)),\n//    (s91sq[1] && (ARESETn && !(s90)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_63<=0; else\n//    ASR_63 <= (s91s[0]);\nlocalparam integer L_NUM_RDATA_BYTES       = ((DATA_WIDTH + 7) / 8);\nlocalparam integer L_NUM_RDATA_BYTE_LANES  = ((L_NUM_RDATA_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_RDATA_EQ_LANES    = (L_NUM_RDATA_BYTE_LANES / 8);\nlocalparam integer L_NUM_RDATA_AND1_LANES  = (L_NUM_RDATA_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_RDATA_AND2_LANES  = (L_NUM_RDATA_AND1_LANES + 7) / 8;\n\nreg   [DATA_WIDTH - 1:0]  RDATA_q;\nreg   [4:0]               s_RDATA_sq;\nwire  [4:0]               s_RDATA_s;\nwire                      s_RDATA_sqaa;\n\nreg [(8*L_NUM_RDATA_EQ_LANES)-1:0]    RDATA_eq;\nreg [(8*L_NUM_RDATA_AND1_LANES)-1:0]  RDATA_stage_1_eq;\nreg [(8*L_NUM_RDATA_AND2_LANES)-1:0]  RDATA_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_RDATA_sq<=5'h00; \n    ASR_63 <=0;\n  end else begin\n    s_RDATA_sq<=s_RDATA_s;\n    ASR_63 <= (s_RDATA_s[0]);\n  end\nend\n\nassign s_RDATA_s={\n  (((ARESETn & RVALID) & (! RREADY))),\n  (s_RDATA_sq[4] && ARESETn),\n  (s_RDATA_sq[3]),\n  (s_RDATA_sq[2]),\n  (s_RDATA_sq[1] & !(s_RDATA_sqaa))\n  };\n\nassign s_RDATA_sqaa = &RDATA_stage_2_eq;\n\ninteger RDATA_bc;\ninteger RDATA_stage_1;\ninteger RDATA_stage_2;\n\nalways @(posedge ACLK) begin\n  RDATA_q<=RDATA;\n\n  for (RDATA_bc = 0; RDATA_bc < L_NUM_RDATA_EQ_LANES*8; RDATA_bc = RDATA_bc + 1) begin : RDATA_BC_LOOP\n    if (RDATA_bc < L_NUM_RDATA_BYTES) begin\n      RDATA_eq[RDATA_bc] <= RDATA_q[RDATA_bc*8 +:8] == RDATA[RDATA_bc*8 +: 8];\n    end else begin\n      RDATA_eq[RDATA_bc] <= 1'b1;\n    end\n  end\n\n  for (RDATA_stage_1 = 0; RDATA_stage_1 < L_NUM_RDATA_AND1_LANES * 8;RDATA_stage_1 = RDATA_stage_1 + 1) begin : RDATA_S1\n    if (RDATA_stage_1 < L_NUM_RDATA_EQ_LANES) begin\n      RDATA_stage_1_eq[RDATA_stage_1] <= &RDATA_eq[RDATA_stage_1*8 +:8];\n    end else begin\n      RDATA_stage_1_eq[RDATA_stage_1] <= 1'b1;\n    end\n  end\n\n  for (RDATA_stage_2 = 0; RDATA_stage_2 < L_NUM_RDATA_AND2_LANES * 8;RDATA_stage_2 = RDATA_stage_2 + 1) begin : RDATA_S2\n    if (RDATA_stage_2 < L_NUM_RDATA_AND1_LANES) begin\n      RDATA_stage_2_eq[RDATA_stage_2] <= &RDATA_stage_1_eq[RDATA_stage_2*8 +:8];\n    end else begin\n      RDATA_stage_2_eq[RDATA_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n  //---------------\n  //ASR_64 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> $stable(RID) ) );\n  //---------------\n  always @(posedge ACLK)\n    s92<=RID;\n  assign s93 = s92 == RID;\n  always @(posedge ACLK) if (`AKRPS reset) s94sq<=3'h4; else\n    s94sq<=s94s;\n  assign s94s={1'b1,\n    ((ARESETn & RVALID) & (! RREADY)),\n    (s94sq[1] && (ARESETn && !(s93)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_64<=0; else\n    ASR_64 <= (s94s[0]);\n\n  //---------------\n  //ASR_65 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> $stable(RLAST) ) );\n  //---------------\n  always @(posedge ACLK)\n    s95<=RLAST;\n  assign s96 = s95 == RLAST;\n  always @(posedge ACLK) if (`AKRPS reset) s97sq<=3'h4; else\n    s97sq<=s97s;\n  assign s97s={1'b1,\n    ((ARESETn & RVALID) & (! RREADY)),\n    (s97sq[1] && (ARESETn && !(s96)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_65<=0; else\n    ASR_65 <= (s97s[0]);\n\n  //---------------\n  //ASR_66 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> $stable(RRESP) ) );\n  //---------------\n  always @(posedge ACLK)\n    s98<=RRESP;\n  assign s99 = s98 == RRESP;\n  always @(posedge ACLK) if (`AKRPS reset) s100sq<=3'h4; else\n    s100sq<=s100s;\n  assign s100s={1'b1,\n    ((ARESETn & RVALID) & (! RREADY)),\n    (s100sq[1] && (ARESETn && !(s99)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_66<=0; else\n    ASR_66 <= (s100s[0]);\n\n  //---------------\n  //ASR_67 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> RVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s101sq<=3'h4; else\n    s101sq<=s101s;\n  assign s101s={1'b1,\n    ((ARESETn & RVALID) & (! RREADY)),\n    (s101sq[1] && (ARESETn && !(RVALID)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_67<=0; else\n    ASR_67 <= (s101s[0]);\n\n  //---------------\n  //ASR_68 : assert property ( @(posedge ACLK) ( ARESETn & i_RecommendOn & i_RecMaxWaitOn & ( RVALID & ! RREADY ) |-> ##[1:16] ( ! RVALID | RREADY ) ) );\n  //---------------\n  reg [L_R_WAIT_WIDTH-1:0]  r_cnt;\n  wire asr_68_set;\n\n  generate\n    if (MAX_R_WAITS > 0) begin : gen_r_wait\n      always @(posedge ACLK) begin\n        if (`AKRPS reset) begin\n          r_cnt <= {L_R_WAIT_WIDTH{1'b0}};\n        end else begin\n          //Valid, not ready, clken\n          if (((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) & ( RVALID & ! RREADY )) begin\n            r_cnt <= r_cnt + 1;\n          end else begin\n            r_cnt <= {L_R_WAIT_WIDTH{1'b0}};\n          end\n        end\n      end\n\n      assign asr_68_set = (r_cnt == MAX_R_WAITS) & ( RVALID & ! RREADY );\n    end else begin : gen_no_r_wait\n      assign asr_68_set = 1'b0;\n    end\n  endgenerate\n\n  always @(posedge ACLK) if (`AKRPS reset) ASR_68<=0; else\n    ASR_68 <= asr_68_set;\n\n  //---------------\n  //ASR_69 : assert property ( @(posedge ACLK) ( ( ARVALID & ( ARLOCK == 1'b1 ) & ( ARLEN == 8'b0 || ARLEN == 8'b1 || ARLEN == 8'b11 || ARLEN == 8'b111 || ARLEN == 8'b1111 ) ) |-> ( ( ARADDR[10:0] & ExclMask ) == ARADDR[10:0] ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_69<=0; else\n    ASR_69 <= ((((ARVALID & ( (ARLOCK == 1'b1) )) & ( (((((ARLEN == 8'b0) || (ARLEN == 8'b1)) || (ARLEN == 8'b11)) || (ARLEN == 8'b111)) || (ARLEN == 8'b1111)) )) && !((( (ARADDR[10:0] & ExclMask) ) == ARADDR[10:0]))));\n\n  //---------------\n  //ASR_70 : assert property ( @(posedge ACLK) ( ARVALID & ( ARLOCK == 1'b1 ) |-> ( ( ARLEN == 8'b0 ) || ( ARLEN == 8'b1 ) || ( ARLEN == 8'b11 ) || ( ARLEN == 8'b111 ) || ( ARLEN == 8'b1111 ) ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_70<=0; else\n    ASR_70 <= (((ARVALID & ( (ARLOCK == 1'b1) )) && !(((((( (ARLEN == 8'b0) ) || ( (ARLEN == 8'b1) )) || ( (ARLEN == 8'b11) )) || ( (ARLEN == 8'b111) )) || ( (ARLEN == 8'b1111) )))));\n\n  //---------------\n  //ASR_71 : assert property ( @(posedge ACLK) ( i_RecommendOn & AWVALID & AWREADY & ( AWLOCK == 1'b1 ) & ExclReadAddr[ExclAwId] & ExclAwMatch |-> ( ( ExclAddr[ExclAwId] == AWADDR ) & ( ExclSize[ExclAwId] == AWSIZE ) & ( ExclLen[ExclAwId] == AWLEN ) & ( ExclBurst[ExclAwId] == AWBURST ) & ( ExclCache[ExclAwId] == AWCACHE ) & ( ExclProt[ExclAwId] == AWPROT ) & ( ExclRegion[ExclAwId] == AWREGION ) ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_71<=0; else\n    ASR_71 <= (((((((i_RecommendOn & AWVALID) & AWREADY) & ( (AWLOCK == 1'b1) )) & ExclReadAddr) & ExclAwMatch) && !(((((((( (ExclAddr == AWADDR) ) & ( (ExclSize == AWSIZE) )) & ( (ExclLen == AWLEN) )) & ( (ExclBurst == AWBURST) )) & ( (ExclCache == AWCACHE) )) & ( (ExclProt == AWPROT) )) & ( (ExclRegion == AWREGION) ))))); // ###MBAC###\n\n  //---------------\n  //ASR_72 : assert property ( @(posedge ACLK) ( ( ARVALID & ( ARLOCK == 1'b1 ) & ( ARLEN == 8'b1 || ARLEN == 8'b11 || ARLEN == 8'b111 || ARLEN == 8'b1111 ) ) |-> ( ArLenInBytes <= 128 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_72<=0; else\n    ASR_72 <= ((((ARVALID & ( (ARLOCK == 1'b1) )) & ( ((((ARLEN == 8'b1) || (ARLEN == 8'b11)) || (ARLEN == 8'b111)) || (ARLEN == 8'b1111)) )) && !((ArLenInBytes <= 128))));\n\n  //---------------\n  //ASR_73 : assert property ( @(posedge ACLK) ( i_RecommendOn & AWVALID & AWREADY & ( AWLOCK == 1'b1 ) |-> ( ExclAwMatch && ExclReadAddr[ExclAwId] && ExclReadData[ExclAwId] ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_73<=0; else\n    ASR_73 <= (((((i_RecommendOn & AWVALID) & AWREADY) & ( (AWLOCK == 1'b1) )) && !(((ExclAwMatch && ExclReadAddr) && ExclReadData)))); // ###MBAC###\n\n  //---------------\n  //ASR_74 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWUSER) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s103<=AWUSER;\n//  assign s104 = s103 == AWUSER;\n//  always @(posedge ACLK) if (`AKRPS reset) s105sq<=3'h4; else\n//    s105sq<=s105s;\n//  assign s105s={1'b1,\n//    ((ARESETn & AWVALID) & (! AWREADY)),\n//    (s105sq[1] && (ARESETn && !(s104)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_74<=0; else\n//    ASR_74 <= (s105s[0]);\nlocalparam integer L_NUM_AWUSER_BYTES       = ((AWUSER_WIDTH + 7) / 8);\nlocalparam integer L_NUM_AWUSER_BYTE_LANES  = ((L_NUM_AWUSER_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_AWUSER_EQ_LANES    = (L_NUM_AWUSER_BYTE_LANES / 8);\nlocalparam integer L_NUM_AWUSER_AND1_LANES  = (L_NUM_AWUSER_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_AWUSER_AND2_LANES  = (L_NUM_AWUSER_AND1_LANES + 7) / 8;\n\nreg   [AWUSER_WIDTH - 1:0] AWUSER_q;\nreg   [4:0]               s_AWUSER_sq;\nwire  [4:0]               s_AWUSER_s;\nwire                      s_AWUSER_sqaa;\n\nreg [(8*L_NUM_AWUSER_EQ_LANES)-1:0]    AWUSER_eq;\nreg [(8*L_NUM_AWUSER_AND1_LANES)-1:0]  AWUSER_stage_1_eq;\nreg [(8*L_NUM_AWUSER_AND2_LANES)-1:0]  AWUSER_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_AWUSER_sq<=5'h00; \n    ASR_74 <=0;\n  end else begin\n    s_AWUSER_sq<=s_AWUSER_s;\n    ASR_74 <= (s_AWUSER_s[0]);\n  end\nend\n\nassign s_AWUSER_s={\n  (((ARESETn & AWVALID) & (! AWREADY))),\n  (s_AWUSER_sq[4] && ARESETn),\n  (s_AWUSER_sq[3]),\n  (s_AWUSER_sq[2]),\n  (s_AWUSER_sq[1] & !(s_AWUSER_sqaa))\n  };\n\nassign s_AWUSER_sqaa = &AWUSER_stage_2_eq;\n\nwire  [(L_NUM_AWUSER_BYTES*8)-1:0]      AWUSER_expand;\nwire  [(L_NUM_AWUSER_BYTES*8)-1:0]      AWUSERsqa_expand;\ngenvar AWUSER_bit;\ngenerate\n  ///////////////////////////////////////////////////////////////////////////////////////////\n  //Expand the AWUSER up to the nearest byte\n  for (AWUSER_bit = 0; AWUSER_bit < (L_NUM_AWUSER_BYTES * 8); AWUSER_bit = AWUSER_bit + 1) begin : AWUSER_BIT_LOOP\n    if (AWUSER_bit < AWUSER_WIDTH) begin : VAL\n      assign AWUSER_expand[AWUSER_bit] = AWUSER[AWUSER_bit];\n      assign AWUSERsqa_expand[AWUSER_bit] = AWUSER_q[AWUSER_bit];\n    end else begin\n      assign AWUSER_expand[AWUSER_bit] = 1'b0;\n      assign AWUSERsqa_expand[AWUSER_bit] = 1'b0;\n    end\n  end\nendgenerate\n\ninteger AWUSER_bc;\ninteger AWUSER_stage_1;\ninteger AWUSER_stage_2;\n\nalways @(posedge ACLK) begin\n  AWUSER_q<=AWUSER;\n\n  for (AWUSER_bc = 0; AWUSER_bc < L_NUM_AWUSER_EQ_LANES*8; AWUSER_bc = AWUSER_bc + 1) begin : AWUSER_BC_LOOP\n    if (AWUSER_bc < L_NUM_AWUSER_BYTES) begin\n      AWUSER_eq[AWUSER_bc] <= AWUSER_expand[AWUSER_bc*8 +:8] == AWUSERsqa_expand[AWUSER_bc*8 +: 8];\n    end else begin\n      AWUSER_eq[AWUSER_bc] <= 1'b1;\n    end\n  end\n\n  for (AWUSER_stage_1 = 0; AWUSER_stage_1 < L_NUM_AWUSER_AND1_LANES * 8;AWUSER_stage_1 = AWUSER_stage_1 + 1) begin : AWUSER_S1\n    if (AWUSER_stage_1 < L_NUM_AWUSER_EQ_LANES) begin\n      AWUSER_stage_1_eq[AWUSER_stage_1] <= &AWUSER_eq[AWUSER_stage_1*8 +:8];\n    end else begin\n      AWUSER_stage_1_eq[AWUSER_stage_1] <= 1'b1;\n    end\n  end\n\n  for (AWUSER_stage_2 = 0; AWUSER_stage_2 < L_NUM_AWUSER_AND2_LANES * 8;AWUSER_stage_2 = AWUSER_stage_2 + 1) begin : AWUSER_S2\n    if (AWUSER_stage_2 < L_NUM_AWUSER_AND1_LANES) begin\n      AWUSER_stage_2_eq[AWUSER_stage_2] <= &AWUSER_stage_1_eq[AWUSER_stage_2*8 +:8];\n    end else begin\n      AWUSER_stage_2_eq[AWUSER_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n\n  //---------------\n  //ASR_75 : assert property ( @(posedge ACLK) ( ARESETn & WVALID & ! WREADY ##1 ARESETn |-> $stable(WUSER) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s106<=WUSER;\n//  assign s107 = s106 == WUSER;\n//  always @(posedge ACLK) if (`AKRPS reset) s108sq<=3'h4; else\n//    s108sq<=s108s;\n//  assign s108s={1'b1,\n//    ((ARESETn & WVALID) & (! WREADY)),\n//    (s108sq[1] && (ARESETn && !(s107)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_75<=0; else\n//    ASR_75 <= (s108s[0]);\nlocalparam integer L_NUM_WUSER_BYTES       = ((WUSER_WIDTH + 7) / 8);\nlocalparam integer L_NUM_WUSER_BYTE_LANES  = ((L_NUM_WUSER_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_WUSER_EQ_LANES    = (L_NUM_WUSER_BYTE_LANES / 8);\nlocalparam integer L_NUM_WUSER_AND1_LANES  = (L_NUM_WUSER_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_WUSER_AND2_LANES  = (L_NUM_WUSER_AND1_LANES + 7) / 8;\n\nreg   [WUSER_WIDTH - 1:0] WUSER_q;\nreg   [4:0]               s_WUSER_sq;\nwire  [4:0]               s_WUSER_s;\nwire                      s_WUSER_sqaa;\n\nreg [(8*L_NUM_WUSER_EQ_LANES)-1:0]    WUSER_eq;\nreg [(8*L_NUM_WUSER_AND1_LANES)-1:0]  WUSER_stage_1_eq;\nreg [(8*L_NUM_WUSER_AND2_LANES)-1:0]  WUSER_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_WUSER_sq<=5'h00; \n    ASR_75 <=0;\n  end else begin\n    s_WUSER_sq<=s_WUSER_s;\n    ASR_75 <= (s_WUSER_s[0]);\n  end\nend\n\nassign s_WUSER_s={\n  (((ARESETn & WVALID) & (! WREADY))),\n  (s_WUSER_sq[4] && ARESETn),\n  (s_WUSER_sq[3]),\n  (s_WUSER_sq[2]),\n  (s_WUSER_sq[1] & !(s_WUSER_sqaa))\n  };\n\nassign s_WUSER_sqaa = &WUSER_stage_2_eq;\n\nwire  [(L_NUM_WUSER_BYTES*8)-1:0]      WUSER_expand;\nwire  [(L_NUM_WUSER_BYTES*8)-1:0]      WUSERsqa_expand;\ngenvar WUSER_bit;\ngenerate\n  ///////////////////////////////////////////////////////////////////////////////////////////\n  //Expand the WUSER up to the nearest byte\n  for (WUSER_bit = 0; WUSER_bit < (L_NUM_WUSER_BYTES * 8); WUSER_bit = WUSER_bit + 1) begin : WUSER_BIT_LOOP\n    if (WUSER_bit < WUSER_WIDTH) begin : VAL\n      assign WUSER_expand[WUSER_bit] = WUSER[WUSER_bit];\n      assign WUSERsqa_expand[WUSER_bit] = WUSER_q[WUSER_bit];\n    end else begin\n      assign WUSER_expand[WUSER_bit] = 1'b0;\n      assign WUSERsqa_expand[WUSER_bit] = 1'b0;\n    end\n  end\nendgenerate\n\ninteger WUSER_bc;\ninteger WUSER_stage_1;\ninteger WUSER_stage_2;\n\nalways @(posedge ACLK) begin\n  WUSER_q<=WUSER;\n\n  for (WUSER_bc = 0; WUSER_bc < L_NUM_WUSER_EQ_LANES*8; WUSER_bc = WUSER_bc + 1) begin : WUSER_BC_LOOP\n    if (WUSER_bc < L_NUM_WUSER_BYTES) begin\n      WUSER_eq[WUSER_bc] <= WUSER_expand[WUSER_bc*8 +:8] == WUSERsqa_expand[WUSER_bc*8 +: 8];\n    end else begin\n      WUSER_eq[WUSER_bc] <= 1'b1;\n    end\n  end\n\n  for (WUSER_stage_1 = 0; WUSER_stage_1 < L_NUM_WUSER_AND1_LANES * 8;WUSER_stage_1 = WUSER_stage_1 + 1) begin : WUSER_S1\n    if (WUSER_stage_1 < L_NUM_WUSER_EQ_LANES) begin\n      WUSER_stage_1_eq[WUSER_stage_1] <= &WUSER_eq[WUSER_stage_1*8 +:8];\n    end else begin\n      WUSER_stage_1_eq[WUSER_stage_1] <= 1'b1;\n    end\n  end\n\n  for (WUSER_stage_2 = 0; WUSER_stage_2 < L_NUM_WUSER_AND2_LANES * 8;WUSER_stage_2 = WUSER_stage_2 + 1) begin : WUSER_S2\n    if (WUSER_stage_2 < L_NUM_WUSER_AND1_LANES) begin\n      WUSER_stage_2_eq[WUSER_stage_2] <= &WUSER_stage_1_eq[WUSER_stage_2*8 +:8];\n    end else begin\n      WUSER_stage_2_eq[WUSER_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n\n  //---------------\n  //ASR_76 : assert property ( @(posedge ACLK) ( ARESETn & BVALID & ! BREADY ##1 ARESETn |-> $stable(BUSER) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s109<=BUSER;\n//  assign s110 = s109 == BUSER;\n//  always @(posedge ACLK) if (`AKRPS reset) s111sq<=3'h4; else\n//    s111sq<=s111s;\n//  assign s111s={1'b1,\n//    ((ARESETn & BVALID) & (! BREADY)),\n//    (s111sq[1] && (ARESETn && !(s110)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_76<=0; else\n//    ASR_76 <= (s111s[0]);\nlocalparam integer L_NUM_BUSER_BYTES       = ((BUSER_WIDTH + 7) / 8);\nlocalparam integer L_NUM_BUSER_BYTE_LANES  = ((L_NUM_BUSER_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_BUSER_EQ_LANES    = (L_NUM_BUSER_BYTE_LANES / 8);\nlocalparam integer L_NUM_BUSER_AND1_LANES  = (L_NUM_BUSER_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_BUSER_AND2_LANES  = (L_NUM_BUSER_AND1_LANES + 7) / 8;\n\nreg   [BUSER_WIDTH - 1:0] BUSER_q;\nreg   [4:0]               s_BUSER_sq;\nwire  [4:0]               s_BUSER_s;\nwire                      s_BUSER_sqaa;\n\nreg [(8*L_NUM_BUSER_EQ_LANES)-1:0]    BUSER_eq;\nreg [(8*L_NUM_BUSER_AND1_LANES)-1:0]  BUSER_stage_1_eq;\nreg [(8*L_NUM_BUSER_AND2_LANES)-1:0]  BUSER_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_BUSER_sq<=5'h00; \n    ASR_76 <=0;\n  end else begin\n    s_BUSER_sq<=s_BUSER_s;\n    ASR_76 <= (s_BUSER_s[0]);\n  end\nend\n\nassign s_BUSER_s={\n  (((ARESETn & BVALID) & (! BREADY))),\n  (s_BUSER_sq[4] && ARESETn),\n  (s_BUSER_sq[3]),\n  (s_BUSER_sq[2]),\n  (s_BUSER_sq[1] & !(s_BUSER_sqaa))\n  };\n\nassign s_BUSER_sqaa = &BUSER_stage_2_eq;\n\nwire  [(L_NUM_BUSER_BYTES*8)-1:0]      BUSER_expand;\nwire  [(L_NUM_BUSER_BYTES*8)-1:0]      BUSERsqa_expand;\ngenvar BUSER_bit;\ngenerate\n  ///////////////////////////////////////////////////////////////////////////////////////////\n  //Expand the BUSER up to the nearest byte\n  for (BUSER_bit = 0; BUSER_bit < (L_NUM_BUSER_BYTES * 8); BUSER_bit = BUSER_bit + 1) begin : BUSER_BIT_LOOP\n    if (BUSER_bit < BUSER_WIDTH) begin : VAL\n      assign BUSER_expand[BUSER_bit] = BUSER[BUSER_bit];\n      assign BUSERsqa_expand[BUSER_bit] = BUSER_q[BUSER_bit];\n    end else begin\n      assign BUSER_expand[BUSER_bit] = 1'b0;\n      assign BUSERsqa_expand[BUSER_bit] = 1'b0;\n    end\n  end\nendgenerate\n\ninteger BUSER_bc;\ninteger BUSER_stage_1;\ninteger BUSER_stage_2;\n\nalways @(posedge ACLK) begin\n  BUSER_q<=BUSER;\n\n  for (BUSER_bc = 0; BUSER_bc < L_NUM_BUSER_EQ_LANES*8; BUSER_bc = BUSER_bc + 1) begin : BUSER_BC_LOOP\n    if (BUSER_bc < L_NUM_BUSER_BYTES) begin\n      BUSER_eq[BUSER_bc] <= BUSER_expand[BUSER_bc*8 +:8] == BUSERsqa_expand[BUSER_bc*8 +: 8];\n    end else begin\n      BUSER_eq[BUSER_bc] <= 1'b1;\n    end\n  end\n\n  for (BUSER_stage_1 = 0; BUSER_stage_1 < L_NUM_BUSER_AND1_LANES * 8;BUSER_stage_1 = BUSER_stage_1 + 1) begin : BUSER_S1\n    if (BUSER_stage_1 < L_NUM_BUSER_EQ_LANES) begin\n      BUSER_stage_1_eq[BUSER_stage_1] <= &BUSER_eq[BUSER_stage_1*8 +:8];\n    end else begin\n      BUSER_stage_1_eq[BUSER_stage_1] <= 1'b1;\n    end\n  end\n\n  for (BUSER_stage_2 = 0; BUSER_stage_2 < L_NUM_BUSER_AND2_LANES * 8;BUSER_stage_2 = BUSER_stage_2 + 1) begin : BUSER_S2\n    if (BUSER_stage_2 < L_NUM_BUSER_AND1_LANES) begin\n      BUSER_stage_2_eq[BUSER_stage_2] <= &BUSER_stage_1_eq[BUSER_stage_2*8 +:8];\n    end else begin\n      BUSER_stage_2_eq[BUSER_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n  //---------------\n  //ASR_77 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARUSER) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s112<=ARUSER;\n//  assign s113 = s112 == ARUSER;\n//  always @(posedge ACLK) if (`AKRPS reset) s114sq<=3'h4; else\n//    s114sq<=s114s;\n//  assign s114s={1'b1,\n//    ((ARESETn & ARVALID) & (! ARREADY)),\n//    (s114sq[1] && (ARESETn && !(s113)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_77<=0; else\n//    ASR_77 <= (s114s[0]);\nlocalparam integer L_NUM_ARUSER_BYTES       = ((ARUSER_WIDTH + 7) / 8);\nlocalparam integer L_NUM_ARUSER_BYTE_LANES  = ((L_NUM_ARUSER_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_ARUSER_EQ_LANES    = (L_NUM_ARUSER_BYTE_LANES / 8);\nlocalparam integer L_NUM_ARUSER_AND1_LANES  = (L_NUM_ARUSER_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_ARUSER_AND2_LANES  = (L_NUM_ARUSER_AND1_LANES + 7) / 8;\n\nreg   [ARUSER_WIDTH - 1:0] ARUSER_q;\nreg   [4:0]               s_ARUSER_sq;\nwire  [4:0]               s_ARUSER_s;\nwire                      s_ARUSER_sqaa;\n\nreg [(8*L_NUM_ARUSER_EQ_LANES)-1:0]    ARUSER_eq;\nreg [(8*L_NUM_ARUSER_AND1_LANES)-1:0]  ARUSER_stage_1_eq;\nreg [(8*L_NUM_ARUSER_AND2_LANES)-1:0]  ARUSER_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_ARUSER_sq<=5'h00; \n    ASR_77 <=0;\n  end else begin\n    s_ARUSER_sq<=s_ARUSER_s;\n    ASR_77 <= (s_ARUSER_s[0]);\n  end\nend\n\nassign s_ARUSER_s={\n  (((ARESETn & ARVALID) & (! ARREADY))),\n  (s_ARUSER_sq[4] && ARESETn),\n  (s_ARUSER_sq[3]),\n  (s_ARUSER_sq[2]),\n  (s_ARUSER_sq[1] & !(s_ARUSER_sqaa))\n  };\n\nassign s_ARUSER_sqaa = &ARUSER_stage_2_eq;\n\nwire  [(L_NUM_ARUSER_BYTES*8)-1:0]      ARUSER_expand;\nwire  [(L_NUM_ARUSER_BYTES*8)-1:0]      ARUSERsqa_expand;\ngenvar ARUSER_bit;\ngenerate\n  ///////////////////////////////////////////////////////////////////////////////////////////\n  //Expand the ARUSER up to the nearest byte\n  for (ARUSER_bit = 0; ARUSER_bit < (L_NUM_ARUSER_BYTES * 8); ARUSER_bit = ARUSER_bit + 1) begin : ARUSER_BIT_LOOP\n    if (ARUSER_bit < ARUSER_WIDTH) begin : VAL\n      assign ARUSER_expand[ARUSER_bit] = ARUSER[ARUSER_bit];\n      assign ARUSERsqa_expand[ARUSER_bit] = ARUSER_q[ARUSER_bit];\n    end else begin\n      assign ARUSER_expand[ARUSER_bit] = 1'b0;\n      assign ARUSERsqa_expand[ARUSER_bit] = 1'b0;\n    end\n  end\nendgenerate\n\ninteger ARUSER_bc;\ninteger ARUSER_stage_1;\ninteger ARUSER_stage_2;\n\nalways @(posedge ACLK) begin\n  ARUSER_q<=ARUSER;\n\n  for (ARUSER_bc = 0; ARUSER_bc < L_NUM_ARUSER_EQ_LANES*8; ARUSER_bc = ARUSER_bc + 1) begin : ARUSER_BC_LOOP\n    if (ARUSER_bc < L_NUM_ARUSER_BYTES) begin\n      ARUSER_eq[ARUSER_bc] <= ARUSER_expand[ARUSER_bc*8 +:8] == ARUSERsqa_expand[ARUSER_bc*8 +: 8];\n    end else begin\n      ARUSER_eq[ARUSER_bc] <= 1'b1;\n    end\n  end\n\n  for (ARUSER_stage_1 = 0; ARUSER_stage_1 < L_NUM_ARUSER_AND1_LANES * 8;ARUSER_stage_1 = ARUSER_stage_1 + 1) begin : ARUSER_S1\n    if (ARUSER_stage_1 < L_NUM_ARUSER_EQ_LANES) begin\n      ARUSER_stage_1_eq[ARUSER_stage_1] <= &ARUSER_eq[ARUSER_stage_1*8 +:8];\n    end else begin\n      ARUSER_stage_1_eq[ARUSER_stage_1] <= 1'b1;\n    end\n  end\n\n  for (ARUSER_stage_2 = 0; ARUSER_stage_2 < L_NUM_ARUSER_AND2_LANES * 8;ARUSER_stage_2 = ARUSER_stage_2 + 1) begin : ARUSER_S2\n    if (ARUSER_stage_2 < L_NUM_ARUSER_AND1_LANES) begin\n      ARUSER_stage_2_eq[ARUSER_stage_2] <= &ARUSER_stage_1_eq[ARUSER_stage_2*8 +:8];\n    end else begin\n      ARUSER_stage_2_eq[ARUSER_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n  //---------------\n  //ASR_78 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> $stable(RUSER) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s115<=RUSER;\n//  assign s116 = s115 == RUSER;\n//  always @(posedge ACLK) if (`AKRPS reset) s117sq<=3'h4; else\n//    s117sq<=s117s;\n//  assign s117s={1'b1,\n//    ((ARESETn & RVALID) & (! RREADY)),\n//    (s117sq[1] && (ARESETn && !(s116)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_78<=0; else\n//    ASR_78 <= (s117s[0]);\nlocalparam integer L_NUM_RUSER_BYTES       = ((RUSER_WIDTH + 7) / 8);\nlocalparam integer L_NUM_RUSER_BYTE_LANES  = ((L_NUM_RUSER_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_RUSER_EQ_LANES    = (L_NUM_RUSER_BYTE_LANES / 8);\nlocalparam integer L_NUM_RUSER_AND1_LANES  = (L_NUM_RUSER_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_RUSER_AND2_LANES  = (L_NUM_RUSER_AND1_LANES + 7) / 8;\n\nreg   [RUSER_WIDTH - 1:0] RUSER_q;\nreg   [4:0]               s_RUSER_sq;\nwire  [4:0]               s_RUSER_s;\nwire                      s_RUSER_sqaa;\n\nreg [(8*L_NUM_RUSER_EQ_LANES)-1:0]    RUSER_eq;\nreg [(8*L_NUM_RUSER_AND1_LANES)-1:0]  RUSER_stage_1_eq;\nreg [(8*L_NUM_RUSER_AND2_LANES)-1:0]  RUSER_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_RUSER_sq<=5'h00; \n    ASR_78 <=0;\n  end else begin\n    s_RUSER_sq<=s_RUSER_s;\n    ASR_78 <= (s_RUSER_s[0]);\n  end\nend\n\nassign s_RUSER_s={\n  (((ARESETn & RVALID) & (! RREADY))),\n  (s_RUSER_sq[4] && ARESETn),\n  (s_RUSER_sq[3]),\n  (s_RUSER_sq[2]),\n  (s_RUSER_sq[1] & !(s_RUSER_sqaa))\n  };\n\nassign s_RUSER_sqaa = &RUSER_stage_2_eq;\n\nwire  [(L_NUM_RUSER_BYTES*8)-1:0]      RUSER_expand;\nwire  [(L_NUM_RUSER_BYTES*8)-1:0]      RUSERsqa_expand;\ngenvar RUSER_bit;\ngenerate\n  ///////////////////////////////////////////////////////////////////////////////////////////\n  //Expand the RUSER up to the nearest byte\n  for (RUSER_bit = 0; RUSER_bit < (L_NUM_RUSER_BYTES * 8); RUSER_bit = RUSER_bit + 1) begin : RUSER_BIT_LOOP\n    if (RUSER_bit < RUSER_WIDTH) begin : VAL\n      assign RUSER_expand[RUSER_bit] = RUSER[RUSER_bit];\n      assign RUSERsqa_expand[RUSER_bit] = RUSER_q[RUSER_bit];\n    end else begin\n      assign RUSER_expand[RUSER_bit] = 1'b0;\n      assign RUSERsqa_expand[RUSER_bit] = 1'b0;\n    end\n  end\nendgenerate\n\ninteger RUSER_bc;\ninteger RUSER_stage_1;\ninteger RUSER_stage_2;\n\nalways @(posedge ACLK) begin\n  RUSER_q<=RUSER;\n\n  for (RUSER_bc = 0; RUSER_bc < L_NUM_RUSER_EQ_LANES*8; RUSER_bc = RUSER_bc + 1) begin : RUSER_BC_LOOP\n    if (RUSER_bc < L_NUM_RUSER_BYTES) begin\n      RUSER_eq[RUSER_bc] <= RUSER_expand[RUSER_bc*8 +:8] == RUSERsqa_expand[RUSER_bc*8 +: 8];\n    end else begin\n      RUSER_eq[RUSER_bc] <= 1'b1;\n    end\n  end\n\n  for (RUSER_stage_1 = 0; RUSER_stage_1 < L_NUM_RUSER_AND1_LANES * 8;RUSER_stage_1 = RUSER_stage_1 + 1) begin : RUSER_S1\n    if (RUSER_stage_1 < L_NUM_RUSER_EQ_LANES) begin\n      RUSER_stage_1_eq[RUSER_stage_1] <= &RUSER_eq[RUSER_stage_1*8 +:8];\n    end else begin\n      RUSER_stage_1_eq[RUSER_stage_1] <= 1'b1;\n    end\n  end\n\n  for (RUSER_stage_2 = 0; RUSER_stage_2 < L_NUM_RUSER_AND2_LANES * 8;RUSER_stage_2 = RUSER_stage_2 + 1) begin : RUSER_S2\n    if (RUSER_stage_2 < L_NUM_RUSER_AND1_LANES) begin\n      RUSER_stage_2_eq[RUSER_stage_2] <= &RUSER_stage_1_eq[RUSER_stage_2*8 +:8];\n    end else begin\n      RUSER_stage_2_eq[RUSER_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n  //---------------\n  //ASR_79 : assert property ( @(posedge ACLK) ( ARESETn & ( AWUSER_WIDTH == 0 ) |-> $stable(AWUSER) ) );\n  //---------------\n  always @(posedge ACLK)\n    s118<=AWUSER;\n  assign s119 = s118 == AWUSER;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_79<=0; else\n    ASR_79 <= (((ARESETn & ( (AWUSER_WIDTH == 0) )) && !(s119)));\n\n  //---------------\n  //ASR_80 : assert property ( @(posedge ACLK) ( ARESETn & ( WUSER_WIDTH == 0 ) |-> $stable(WUSER) ) );\n  //---------------\n  always @(posedge ACLK)\n    s120<=WUSER;\n  assign s121 = s120 == WUSER;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_80<=0; else\n    ASR_80 <= (((ARESETn & ( (WUSER_WIDTH == 0) )) && !(s121)));\n\n  //---------------\n  //ASR_81 : assert property ( @(posedge ACLK) ( ARESETn & ( BUSER_WIDTH == 0 ) |-> $stable(BUSER) ) );\n  //---------------\n  always @(posedge ACLK)\n    s122<=BUSER;\n  assign s123 = s122 == BUSER;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_81<=0; else\n    ASR_81 <= (((ARESETn & ( (BUSER_WIDTH == 0) )) && !(s123)));\n\n  //---------------\n  //ASR_82 : assert property ( @(posedge ACLK) ( ARESETn & ( ARUSER_WIDTH == 0 ) |-> $stable(ARUSER) ) );\n  //---------------\n  always @(posedge ACLK)\n    s124<=ARUSER;\n  assign s125 = s124 == ARUSER;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_82<=0; else\n    ASR_82 <= (((ARESETn & ( (ARUSER_WIDTH == 0) )) && !(s125)));\n\n  //---------------\n  //ASR_83 : assert property ( @(posedge ACLK) ( ARESETn & ( RUSER_WIDTH == 0 ) |-> $stable(RUSER) ) );\n  //---------------\n  always @(posedge ACLK)\n    s126<=RUSER;\n  assign s127 = s126 == RUSER;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_83<=0; else\n    ASR_83 <= (((ARESETn & ( (RUSER_WIDTH == 0) )) && !(s127)));\n\n  //---------------\n  //ASR_84 : assert property ( @(posedge ACLK) ( ARESETn & ( ID_WIDTH == 0 ) |-> $stable(AWID) ) );\n  //---------------\n  always @(posedge ACLK)\n    s128<=AWID;\n  assign s129 = s128 == AWID;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_84<=0; else\n    ASR_84 <= (((ARESETn & ( (ID_WIDTH == 0) )) && !(s129)));\n\n  //---------------\n  //ASR_85 : assert property ( @(posedge ACLK) ( ARESETn & ( ID_WIDTH == 0 ) |-> $stable(BID) ) );\n  //---------------\n  always @(posedge ACLK)\n    s130<=BID;\n  assign s131 = s130 == BID;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_85<=0; else\n    ASR_85 <= (((ARESETn & ( (ID_WIDTH == 0) )) && !(s131)));\n\n  //---------------\n  //ASR_86 : assert property ( @(posedge ACLK) ( ARESETn & ( ID_WIDTH == 0 ) |-> $stable(ARID) ) );\n  //---------------\n  always @(posedge ACLK)\n    s132<=ARID;\n  assign s133 = s132 == ARID;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_86<=0; else\n    ASR_86 <= (((ARESETn & ( (ID_WIDTH == 0) )) && !(s133)));\n\n  //---------------\n  //ASR_87 : assert property ( @(posedge ACLK) ( ARESETn & ( ID_WIDTH == 0 ) |-> $stable(RID) ) );\n  //---------------\n  always @(posedge ACLK)\n    s134<=RID;\n  assign s135 = s134 == RID;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_87<=0; else\n    ASR_87 <= (((ARESETn & ( (ID_WIDTH == 0) )) && !(s135)));\n\nendmodule //Axi4PC_asr_inline\n\n\n// (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//*****************************************************************************\n// Notes            : The assertion ASR_23 is not implemented for WDATA before\n//                    AWADDR, since that would require storing all WSTRB in a\n//                    burst.\n//\n//                    The following assertions use FIFOs to store AW and W\n//                    signals, and can be disabled to improve frequency and\n//                    reduce area: ASR_22, ASR_23, ASR_30, ASR_31, ASR_33.\n//\n//                    The following assertions use FIFOs to store AW and W\n//                    signals, and can be disabled to improve frequency and\n//                    reduce area: ASR_59, ASR_60, ASR_61, ASR_63, ASR_73.\n//                    In particular, ASR_59 is timing critical.\n//*****************************************************************************\n\n`timescale 1ps/1ps\n`default_nettype none\n\n`define AXI4PC_TYPES\n// ALEN Encoding\n`define AXI4PC_ALEN_1            8'b00000000\n`define AXI4PC_ALEN_2            8'b00000001\n`define AXI4PC_ALEN_3            8'b00000010\n`define AXI4PC_ALEN_4            8'b00000011\n`define AXI4PC_ALEN_5            8'b00000100\n`define AXI4PC_ALEN_6            8'b00000101\n`define AXI4PC_ALEN_7            8'b00000110\n`define AXI4PC_ALEN_8            8'b00000111\n`define AXI4PC_ALEN_9            8'b00001000\n`define AXI4PC_ALEN_10           8'b00001001\n`define AXI4PC_ALEN_11           8'b00001010\n`define AXI4PC_ALEN_12           8'b00001011\n`define AXI4PC_ALEN_13           8'b00001100\n`define AXI4PC_ALEN_14           8'b00001101\n`define AXI4PC_ALEN_15           8'b00001110\n`define AXI4PC_ALEN_16           8'b00001111\n\n// ASIZE Encoding\n`define AXI4PC_ASIZE_8           3'b000\n`define AXI4PC_ASIZE_16          3'b001\n`define AXI4PC_ASIZE_32          3'b010\n`define AXI4PC_ASIZE_64          3'b011\n`define AXI4PC_ASIZE_128         3'b100\n`define AXI4PC_ASIZE_256         3'b101\n`define AXI4PC_ASIZE_512         3'b110\n`define AXI4PC_ASIZE_1024        3'b111\n\n// ABURST Encoding\n`define AXI4PC_ABURST_FIXED      2'b00\n`define AXI4PC_ABURST_INCR       2'b01 \n`define AXI4PC_ABURST_WRAP       2'b10 \n\n// ALOCK Encoding\n`define AXI4PC_ALOCK_EXCL        1'b1\n\n// RRESP / BRESP Encoding\n`define AXI4PC_RESP_OKAY         2'b00\n`define AXI4PC_RESP_EXOKAY       2'b01\n`define AXI4PC_RESP_SLVERR       2'b10\n`define AXI4PC_RESP_DECERR       2'b11\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_protocol_checker_v1_1_12_core #(\n  parameter integer C_ERROR_COUNT = 97,\n  parameter integer C_AXI_ID_WIDTH = 1,\n  parameter integer C_AXI_DATA_WIDTH = 32,\n  parameter integer C_AXI_ADDR_WIDTH = 32,\n  parameter integer C_AXI_AWUSER_WIDTH = 1,\n  parameter integer C_AXI_WUSER_WIDTH  = 1,\n  parameter integer C_AXI_BUSER_WIDTH  = 1,\n  parameter integer C_AXI_ARUSER_WIDTH = 1,\n  parameter integer C_AXI_RUSER_WIDTH  = 1,\n  parameter integer C_AXI_PROTOCOL = 0,\n  parameter integer MAXRBURSTS = 16,\n  parameter integer MAXWBURSTS = 16,\n  parameter integer EXMON_WIDTH = 4,\n  parameter integer RecommendOn = 1,\n  parameter integer RecommendWaitOn = 1,\n  parameter integer MAX_AW_WAITS = 16,\n  parameter integer MAX_AR_WAITS = 16,\n  parameter integer MAX_W_WAITS = 16,\n  parameter integer MAX_R_WAITS = 16,\n  parameter integer MAX_B_WAITS = 16,\n  parameter integer C_PC_SUPPORTS_NARROW_BURST     = 1,\n  parameter integer C_PC_HAS_SYSTEM_RESET = 0,\n  parameter integer C_PC_MAX_BURST_LENGTH          = 256\n) (\n   output wire [C_ERROR_COUNT-1:0]     pc_status,\n   input wire                          resetn,\n\n   input wire                          ACLK,\n   input wire                          ARST_N,\n   input wire [C_AXI_ID_WIDTH-1:0]     AWID,\n   input wire [C_AXI_ADDR_WIDTH-1:0]   AWADDR,\n   input wire [7:0]                    AWLEN,\n   input wire [2:0]                    AWSIZE,\n   input wire [1:0]                    AWBURST,\n   input wire [0:0]                    AWLOCK,\n   input wire [3:0]                    AWCACHE,\n   input wire [2:0]                    AWPROT,\n   input wire [3:0]                    AWQOS,\n   input wire [3:0]                    AWREGION,\n   input wire [C_AXI_AWUSER_WIDTH-1:0] AWUSER,\n   input wire                          AWVALID,\n   input wire                          AWREADY,\n\n   input wire                          WLAST,\n   input wire [C_AXI_DATA_WIDTH-1:0]   WDATA,\n   input wire [C_AXI_DATA_WIDTH/8-1:0] WSTRB,\n   input wire [C_AXI_WUSER_WIDTH-1:0]  WUSER,\n   input wire                          WVALID,\n   input wire                          WREADY,\n   input wire [C_AXI_ID_WIDTH-1:0]     BID,\n   input wire [1:0]                    BRESP,\n   input wire [C_AXI_BUSER_WIDTH-1:0]  BUSER,\n   input wire                          BVALID,\n   input wire                          BREADY,\n   input wire [C_AXI_ID_WIDTH-1:0]     ARID,\n   input wire [C_AXI_ADDR_WIDTH-1:0]   ARADDR,\n   input wire [7:0]                    ARLEN,\n   input wire [2:0]                    ARSIZE,\n   input wire [1:0]                    ARBURST,\n   input wire [0:0]                    ARLOCK,\n   input wire [3:0]                    ARCACHE,\n   input wire [2:0]                    ARPROT,\n   input wire [3:0]                    ARQOS,\n   input wire [3:0]                    ARREGION,\n   input wire [C_AXI_ARUSER_WIDTH-1:0] ARUSER,\n   input wire                          ARVALID,\n   input wire                          ARREADY,\n   input wire [C_AXI_ID_WIDTH-1:0]     RID,\n   input wire                          RLAST,\n   input wire [C_AXI_DATA_WIDTH-1:0]   RDATA,\n   input wire [1:0]                    RRESP,\n   input wire [C_AXI_RUSER_WIDTH-1:0]  RUSER,\n   input wire                          RVALID,\n   input wire                          RREADY\n  );\n\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Log2.\n  function integer log2;\n    input integer value;\n    integer a;\n    begin\n      a = value;\n      \n      for (log2=0; a>1; log2=log2+1) begin\n        a = a >> 1;\n      end\n    end\n  endfunction\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n\n  localparam WEXCL           = 0;\n  localparam WALENLO         = WEXCL + 1;\n  localparam WALENHI         = WALENLO + 7;\n\n  localparam WADDRLO         = 0;\n  localparam WADDRHI         = 6;\n  localparam WASIZELO        = WADDRHI + 1;\n  localparam WASIZEHI        = WASIZELO + 2;\n\n  localparam STRB_WIDTH      = C_AXI_DATA_WIDTH/8;\n  localparam LOG2_STRB_WIDTH = log2(STRB_WIDTH);\n\n  localparam ID_MAX          = C_AXI_ID_WIDTH? C_AXI_ID_WIDTH-1:0;\n  localparam integer P_NUM_THREADS = ((2**C_AXI_ID_WIDTH) < MAXRBURSTS) ? 2**C_AXI_ID_WIDTH : MAXRBURSTS;\n  localparam integer P_ACCEPTANCE_LOG = f_ceil_log2(MAXRBURSTS);\n  localparam ID_SIZE         = (2**C_AXI_ID_WIDTH) - 1;\n\n  localparam ADDRLO          = 0;\n  localparam ADDRHI          = 6;\n  localparam EXCL            = ADDRHI + 1;\n  localparam ALENLO          = EXCL + 1;\n  localparam ALENHI          = ALENLO + 7;\n  localparam ASIZELO         = ALENHI + 1;\n  localparam ASIZEHI         = ASIZELO + 2;\n  localparam BURSTLO         = ASIZEHI + 1;\n  localparam BURSTHI         = BURSTLO + 1;\n  localparam LP_ADDR_WIDTH   = (C_AXI_ADDR_WIDTH > 12) ? C_AXI_ADDR_WIDTH : 13;\n  localparam LP_EXMON_WIDTH  = (EXMON_WIDTH == 0) ? 1 : EXMON_WIDTH;\n\n  wire internal_AWLOCK;\n  wire internal_ARLOCK;\n  \n  assign internal_AWLOCK = (EXMON_WIDTH == 0) ? 1'b0 : AWLOCK;\n  assign internal_ARLOCK = (EXMON_WIDTH == 0) ? 1'b0 : ARLOCK;\n\n\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n\n  wire [87:1]                 Axi4PC_asr_inline_out;\n  wire [3:1]                  Axi4LitePC_asr_inline_out;\n  reg  [11:1]                 xilinx_inline_out;\n  wire [5:1]                  Axi4PC_aux;\n\n  reg  [6:0]                  AlignMaskR;\n  reg  [6:0]                  AlignMaskW;\n  reg  [14:0]                 ExclMask;\n  reg  [LP_ADDR_WIDTH-1:0]    ArAddrIncr;\n  reg  [LP_ADDR_WIDTH-1:0]    AwAddrIncr;\n  reg  [15:0]                 ArLenInBytes;\n  reg  [10:0]                 ArSizeInBits;\n  reg  [10:0]                 AwSizeInBits;\n  wire                        ArExclPending;\n  wire                        WriteDataNumError;\n  reg                         BStrbError;\n  wire [8:0]                  ArCountPending;\n  wire [8:0]                  ArLenPending;\n  reg                         RidMatch_index;\n  wire [31:0]                 RidMatch;\n  wire                        i_RecommendOn;\n  wire                        i_RecMaxWaitOn;\n  reg  [LP_EXMON_WIDTH-1:0]   ExclAwId;\n  wire                        ExclIdOverflow;\n  wire [LP_ADDR_WIDTH-1:0]    ExclAddr_indexed;\n  wire [2:0]                  ExclSize_indexed;\n  wire [7:0]                  ExclLen_indexed;\n  wire [1:0]                  ExclBurst_indexed;\n  wire [3:0]                  ExclCache_indexed;\n  wire [2:0]                  ExclProt_indexed;\n  wire [3:0]                  ExclRegion_indexed;\n  wire                        ExclReadAddr_indexed;\n  wire                        ExclReadData_indexed;\n\n  genvar                      i;                    // FIFO generation variable\n\n  // Write FIFO signals\n  reg  [8:0]                  WCountIn;\n  wire                        WDataOut[0:ID_SIZE];\n  reg                         WDataNumError1;\n  reg                         BrespErrorLead;\n\n  // Read FIFO signals\n  reg  [BURSTHI:0]            RBurstCam_index;\n  wire [BURSTHI:0]            RBurstCam;\n//  reg  [BURSTHI:0]            RBurstCam1;\n  reg  [8:0]                  RCountCam_index;\n  wire [8:0]                  RCountCam;\n  reg  [8:0]                  RCountCam1;\n\n  reg  [8:0]                  RCount[0:P_NUM_THREADS-1];\n  reg  [0:P_NUM_THREADS-1]    RCountIncr;\n  reg  [BURSTHI:0]            Burst;\n  wire [BURSTHI:0]            RDataOut[0:P_NUM_THREADS-1];\n  wire [P_NUM_THREADS-1:0]    REmpty;\n  wire [P_NUM_THREADS-1:0]    RFull;\n//  reg  [11:0]                 Bcount1;\n//  reg  [11:0]                 Bcount;\n//  reg  [16:0]                 Bshift1;\n//  reg  [15:0]                 Bshift;\n\n  wire [LP_ADDR_WIDTH-1:0] awaddr = {LP_ADDR_WIDTH{1'b0}} | AWADDR[C_AXI_ADDR_WIDTH-1:0];\n  wire [LP_ADDR_WIDTH-1:0] araddr = {LP_ADDR_WIDTH{1'b0}} | ARADDR[C_AXI_ADDR_WIDTH-1:0];\n\n  wire [C_AXI_ID_WIDTH-1:0]       AWIDOut;\n  wire [7:0]                      AWLENOut;\n  wire [6:0]                      AWStrbAddrOut;\n  wire [2:0]                      AWStrbsizeOut;\n  wire                            AWEmpty;\n  wire                            AWFull;\n  wire [8:0]                      WCheckCountOut;\n  wire [C_AXI_DATA_WIDTH/8-1:0]   WCheckstrbOut;\n  wire                            WCheckEmpty;\n  wire                            WCheckFull;\n  reg  [C_AXI_DATA_WIDTH/8-1:0]   WSTRBq;\n  wire [C_AXI_DATA_WIDTH/8-1:0]   WstrbIn;\n  reg                             first_strb;\n  wire                            wcheckPop;\n  reg  [log2(MAXWBURSTS):0]       AWXferCount[0:ID_SIZE];\n  reg                             AWXferCountOverflow;\n  wire                            AWPush;\n  wire                            WLastPush;\n\n  wire  reset_i;\n  wire  resetn_out;\n  wire  checker_main_resetn;\n  (* shreg_extract=\"no\", iob=\"false\", equivalent_register_removal = \"no\" *) reg [2:0] reset_resync;\n\n  assign reset_i = ~resetn;\n  assign resetn_out = (C_PC_HAS_SYSTEM_RESET == 1) ? reset_resync[2] : ARST_N;\n  \n  always @(posedge ACLK or posedge reset_i) begin\n    if (reset_i) begin\n      reset_resync <= 3'b000;\n    end else begin\n      reset_resync <= {reset_resync[1:0], 1'b1};\n    end\n  end\n\n  assign checker_main_resetn = resetn_out & ARST_N;\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Rewritten auxillary code to meet timing derived from Axi4PC.sv\n  /////////////////////////////////////////////////////////////////////////////\n\n  //---------------------------------------------------------------------------\n  // RDataMask\n  //---------------------------------------------------------------------------\n//  always @(posedge ACLK)\n//  begin : p_ByteCountShiftSeq\n//    if (!checker_main_resetn) begin\n//      Bcount1    <= 12'b0;\n//      Bcount     <= 12'b0;\n//      Bshift1    <= 17'b0;\n//      RBurstCam1 <= {BURSTHI+1{1'b0}};\n//      RCountCam1 <= 9'b0;\n//      Bshift     <= 16'b0;\n//    end else begin\n//      Bcount1    <= ByteCount(RBurstCam, RCountCam);\n//      Bcount     <= Bcount1;\n//      Bshift1    <= ByteShift1(RBurstCam, RCountCam);\n//      RBurstCam1 <= RBurstCam;\n//      RCountCam1 <= RCountCam;\n//      Bshift     <= ByteShift2(RBurstCam1, RCountCam1, Bshift1);\n//    end\n//  end\n\n  //---------------------------------------------------------------------------\n  // Read CAMs: One FIFO per ID instead of true CAMs to improve timing\n  //---------------------------------------------------------------------------\n\n\n  /////////////////////////////////////////////////////////////////////////////\n  //\nreg  [(P_ACCEPTANCE_LOG+1)-1:0] accept_cnt;\nwire [P_NUM_THREADS-1:0] thread_valid;\nwire [P_NUM_THREADS-1:0] aid_match;\nwire [P_NUM_THREADS-1:0] rid_match;\nwire [P_NUM_THREADS-1:0] cmd_push;\nwire [P_NUM_THREADS-1:0] cmd_pop;\nwire [P_NUM_THREADS:0]   accum_push;\nreg  [P_NUM_THREADS*C_AXI_ID_WIDTH-1:0] active_id;\nreg  [P_NUM_THREADS*8-1:0] active_cnt;\nwire any_aid_match;\nwire any_rid_match;\nwire accept_limit;\nwire any_push;\nwire any_pop;\n  \nassign any_push = ARREADY & ARVALID;\nassign any_pop = RVALID && RREADY && RLAST;\nassign accept_limit = (accept_cnt == MAXRBURSTS) & ~any_pop;  // Allow next push if a transaction is currently being completed\n\nassign any_aid_match = |aid_match;\nassign any_rid_match = |rid_match;\nassign accum_push[0] = 1'b0;\n    \nalways @(posedge ACLK) begin\n  if (!checker_main_resetn) begin\n    accept_cnt <= 0; \n  end else begin\n    if (any_push & ~any_pop) begin\n      accept_cnt <= accept_cnt + 1;\n  end else if (any_pop & ~any_push & (accept_cnt != 0)) begin\n      accept_cnt <= accept_cnt - 1;\n    end\n  end \nend\n\nalways @(araddr or internal_ARLOCK or ARBURST or ARLEN or ARSIZE) begin\n  Burst[ADDRHI:ADDRLO]     = araddr[ADDRHI:ADDRLO];\n  Burst[EXCL]              = (internal_ARLOCK == `AXI4PC_ALOCK_EXCL);\n  Burst[BURSTHI:BURSTLO]   = ARBURST;\n  Burst[ALENHI:ALENLO]     = ARLEN;\n  Burst[ASIZEHI:ASIZELO]   = ARSIZE;\nend\n\ninitial begin : REG_DEFAULTS\n  active_cnt = {MAXRBURSTS*8{1'b0}};\nend\n\n\ngenvar gen_thread;\ngenerate\n  for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop\n\n    assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: P_ACCEPTANCE_LOG+1] != 0);\n\n    /////////////////////////////////////////////////////////////////////////////////\n    // The currect thread is active for the requested transaction if\n    // this thread slot is not vacant, and\n    // the requested ID matches the active ID for this thread.\n    assign aid_match[gen_thread] =  thread_valid[gen_thread] && (ARID[C_AXI_ID_WIDTH-1:0] == active_id[gen_thread*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]);\n\n    /////////////////////////////////////////////////////////////////////////////////\n    // cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot.\n    assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread];\n    assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread]));\n    \n    /////////////////////////////////////////////////////////////////////////////////\n    // cmd_pop points to the position of the active thread that matches the current RID.\n    assign rid_match[gen_thread] = thread_valid[gen_thread] & ((RID[C_AXI_ID_WIDTH-1:0]) == active_id[gen_thread*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]);\n    assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread];\n  \n    always @(posedge ACLK) begin\n      if (!checker_main_resetn) begin\n        active_id[gen_thread*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] <= {C_AXI_ID_WIDTH{1'b0}};\n        active_cnt[gen_thread*8+:8] <= 0; \n      end else begin\n        if (cmd_push[gen_thread]) begin\n          active_id[gen_thread*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] <= ARID[C_AXI_ID_WIDTH-1:0];\n          if (~cmd_pop[gen_thread]) begin\n            active_cnt[gen_thread*8+:P_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:P_ACCEPTANCE_LOG+1] + 1;\n          end\n        end else if (cmd_pop[gen_thread]) begin\n          active_cnt[gen_thread*8+:P_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:P_ACCEPTANCE_LOG+1] - 1;\n        end\n      end \n    end\n\n    axi_protocol_checker_v1_1_12_syn_fifo #(\n      .C_DATA_WIDTH (BURSTHI+1),\n      .C_ADDR_WIDTH (P_ACCEPTANCE_LOG)\n    ) RDCAM (\n      .clk      (ACLK),\n      .rst      (!checker_main_resetn),\n      .data_in  (Burst),\n      .rd       (cmd_pop[gen_thread]),\n      .wr       (cmd_push[gen_thread]),\n      .data_out (RDataOut[gen_thread]),\n      .empty    (REmpty[gen_thread]),\n      .full     (RFull[gen_thread])\n    );\n  \n    // One Counter per ID\n    always @(posedge ACLK) begin : p_RCountSeq\n      if (!checker_main_resetn | cmd_pop[gen_thread] | (cmd_push[gen_thread] & REmpty[gen_thread])) begin\n        RCount[gen_thread] <= 9'h000;\n      end else if (rid_match[gen_thread] & (RVALID & RREADY & !RLAST)) begin\n        RCount[gen_thread] <= RCount[gen_thread] + 9'h001;\n      end\n    end\n  end\n  \n  \nendgenerate\n\ninteger gen_match;\n\nalways@( * ) begin : MUX_OUT\n  RBurstCam_index = {BURSTHI+1{1'b0}};\n  RCountCam_index = {9{1'b0}};\n  RidMatch_index  = 1'b0;\n  for (gen_match = 0; gen_match < P_NUM_THREADS; gen_match = gen_match + 1) begin : GEN_MATCH\n    if (rid_match[gen_match] == 1'b1) begin : RID_MATCH\n      RBurstCam_index = RDataOut[gen_match];\n      RCountCam_index = RCount[gen_match];\n      RidMatch_index = 1'b1;\n    end\n  end\nend\n\n  assign RBurstCam     = RBurstCam_index;\n  assign RCountCam     = RCountCam_index;\n\n  assign RidMatch      = !RidMatch_index ? 32'h00000000 : 32'h00000001;\n\n  //---------------------------------------------------------------------------\n  // Write CAMs: One FIFO per ID instead of true CAMs to improve timing.\n  // Write bursts are not stored in single structure for checking when complete.\n  // This prevents checking of write strobes for write data before address.\n  //---------------------------------------------------------------------------\n  always @(posedge ACLK) begin : p_WCountInSeq\n    if (!checker_main_resetn | (WVALID & WREADY & WLAST)) begin\n      WCountIn <= 9'h000;\n    end else if (WVALID & WREADY & !WLAST) begin\n      WCountIn <= WCountIn + 9'h001;\n    end\n  end\n\n  //---------------------------------------------------------------------------\n  // Auxillary logic assertions\n  //---------------------------------------------------------------------------\n  assign Axi4PC_aux[1] = |(RFull  & cmd_push) & ARST_N; // Rd CAM overflow\n  assign Axi4PC_aux[2] = |(REmpty & cmd_pop) & ARST_N; // Rd CAM underflow\n\n\n  assign Axi4PC_aux[3] = ((AWFull & AWPush) | AWXferCountOverflow) & ARST_N; // Wr CAM overflow\n  assign Axi4PC_aux[4] = (WCheckFull & WLastPush)  & ARST_N; // Wr CAM underflow\n  assign Axi4PC_aux[5] = (C_AXI_PROTOCOL != 2) & ExclIdOverflow & ARST_N;  // Excl overflow\n\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Code from Axi4PC.sv (modifications indicated with ###)\n  /////////////////////////////////////////////////////////////////////////////\n\n  localparam DATA_MAX    = C_AXI_DATA_WIDTH-1;\n  localparam EXMON_HI    = {LP_EXMON_WIDTH{1'b1}};\n  localparam AWUSER_MAX  = C_AXI_AWUSER_WIDTH ? C_AXI_AWUSER_WIDTH-1:0;\n  localparam WUSER_MAX   = C_AXI_WUSER_WIDTH ? C_AXI_WUSER_WIDTH-1:0;\n  localparam BUSER_MAX   = C_AXI_BUSER_WIDTH ? C_AXI_BUSER_WIDTH-1:0;\n  localparam ARUSER_MAX  = C_AXI_ARUSER_WIDTH ? C_AXI_ARUSER_WIDTH-1:0;\n  localparam RUSER_MAX   = C_AXI_RUSER_WIDTH ? C_AXI_RUSER_WIDTH-1:0;\n  localparam STRB_MAX    = C_AXI_DATA_WIDTH/8-1;\n  localparam STRB_1      = {{STRB_MAX{1'b0}}, 1'b1};\n\n  wire    [LP_EXMON_WIDTH-1:0] ExclIdWrPtr;\n  reg               [ID_MAX:0] ExclId[EXMON_HI:0];\n  reg                          ExclIdDelta;\n  reg             [EXMON_HI:0] ExclIdValid;\n  wire                         ExclIdFull;\n  reg     [LP_EXMON_WIDTH-1:0] ExclIdFreePtr;\n  reg                          ExclAwMatch;\n  reg     [LP_EXMON_WIDTH-1:0] ExclArId;\n  reg                          ExclArMatch;\n  reg     [LP_EXMON_WIDTH-1:0] ExclRId;\n  reg                          ExclRMatch;\n  reg                          ExclReadAddr[EXMON_HI:0];\n  reg                          ExclReadData[EXMON_HI:0];\n  reg      [LP_ADDR_WIDTH-1:0] ExclAddr[EXMON_HI:0];\n  reg                    [2:0] ExclSize[EXMON_HI:0];\n  reg                    [7:0] ExclLen[EXMON_HI:0];\n  reg                    [1:0] ExclBurst[EXMON_HI:0];\n  reg                    [3:0] ExclCache[EXMON_HI:0];\n  reg                    [2:0] ExclProt[EXMON_HI:0];\n  reg                    [3:0] ExclQos[EXMON_HI:0];\n  reg                    [3:0] ExclRegion[EXMON_HI:0];\n  reg [C_AXI_AWUSER_WIDTH-1:0] ExclUser[EXMON_HI:0];\n\n\n//------------------------------------------------------------------------------\n// INDEX:   2) Combinatorial Logic\n//------------------------------------------------------------------------------\n\n  //----------------------------------------------------------------------------\n  // INDEX:      a) Masks\n  //----------------------------------------------------------------------------\n\n  // INDEX:           - AlignMaskR\n  // =====\n  // Calculate wrap mask for read address\n  always @(ARSIZE or ARVALID)\n  begin\n    if (ARVALID)\n      case (ARSIZE)\n        `AXI4PC_ASIZE_1024:  AlignMaskR = 7'b0000000;\n        `AXI4PC_ASIZE_512:   AlignMaskR = 7'b1000000;\n        `AXI4PC_ASIZE_256:   AlignMaskR = 7'b1100000;\n        `AXI4PC_ASIZE_128:   AlignMaskR = 7'b1110000;\n        `AXI4PC_ASIZE_64:    AlignMaskR = 7'b1111000;\n        `AXI4PC_ASIZE_32:    AlignMaskR = 7'b1111100;\n        `AXI4PC_ASIZE_16:    AlignMaskR = 7'b1111110;\n        `AXI4PC_ASIZE_8:     AlignMaskR = 7'b1111111;\n        default:             AlignMaskR = 7'b1111111;\n      endcase\n    else\n      AlignMaskR = 7'b1111111;\n  end\n\n\n  // INDEX:           - AlignMaskW\n  // =====\n  // Calculate wrap mask for write address\n  always @(AWSIZE or AWVALID)\n  begin\n    if (AWVALID)\n      case (AWSIZE)\n        `AXI4PC_ASIZE_1024:  AlignMaskW = 7'b0000000;\n        `AXI4PC_ASIZE_512:   AlignMaskW = 7'b1000000;\n        `AXI4PC_ASIZE_256:   AlignMaskW = 7'b1100000;\n        `AXI4PC_ASIZE_128:   AlignMaskW = 7'b1110000;\n        `AXI4PC_ASIZE_64:    AlignMaskW = 7'b1111000;\n        `AXI4PC_ASIZE_32:    AlignMaskW = 7'b1111100;\n        `AXI4PC_ASIZE_16:    AlignMaskW = 7'b1111110;\n        `AXI4PC_ASIZE_8:     AlignMaskW = 7'b1111111;\n        default:             AlignMaskW = 7'b1111111;\n      endcase // case(AWSIZE)\n    else\n      AlignMaskW = 7'b1111111;\n  end\n\n\n  // INDEX:           - ExclMask\n  // =====\n  always @(ARLEN or ARSIZE)\n  begin : p_ExclMaskComb\n    ExclMask = ~((({7'b000_0000, ARLEN} + 15'b000_0000_0000_0001) << ARSIZE) - 15'b000_0000_0000_0001);\n  end // block: p_ExclMaskComb\n\n\n  //----------------------------------------------------------------------------\n  // INDEX:      b) Increments\n  //----------------------------------------------------------------------------\n\n  // INDEX:           - ArAddrIncr\n  // =====\n  always @(ARSIZE or ARLEN or araddr)\n  begin : p_RAddrIncrComb\n    ArAddrIncr = araddr + (ARLEN << ARSIZE);  // The final address of the burst\n  end\n\n\n  // INDEX:           - AwAddrIncr\n  // =====\n  always @(AWSIZE or AWLEN or awaddr)\n  begin : p_WAddrIncrComb\n    AwAddrIncr = awaddr + (AWLEN << AWSIZE);  // The final address of the burst\n  end\n\n\n  //----------------------------------------------------------------------------\n  // INDEX:      c) Conversions\n  //----------------------------------------------------------------------------\n\n  // INDEX:           - ArLenInBytes\n  // =====\n  always @(ARSIZE or ARLEN)\n  begin : p_ArLenInBytes\n    // bytes = (ARLEN+1) data transfers x ARSIZE bytes\n    ArLenInBytes = (({8'h00, ARLEN} + 16'h001) << ARSIZE); \n  end\n\n\n  // INDEX:           - ArSizeInBits\n  // =====\n  always @(ARSIZE)\n  begin : p_ArSizeInBits\n    ArSizeInBits = (11'b000_0000_1000 << ARSIZE); // bits = 8 x ARSIZE bytes\n  end\n\n\n  // INDEX:           - AwSizeInBits\n  // =====\n  always @(AWSIZE)\n  begin : p_AwSizeInBits\n    AwSizeInBits = (11'b000_0000_1000 << AWSIZE); // bits = 8 x AWSIZE bytes\n  end\n\n\n  //----------------------------------------------------------------------------\n  // INDEX:      d) Other\n  //----------------------------------------------------------------------------\n\n  // INDEX:           - ArExclPending\n  // =====\n  // Avoid putting on assertion directly as index is an integer\n  assign ArExclPending = RBurstCam[EXCL]; // ### Rewritten\n\n  // INDEX:           - ArLenPending\n  // =====\n  // Avoid putting on assertion directly as index is an integer\n  assign ArLenPending = {1'b0, RBurstCam[ALENHI:ALENLO]}; // ### Rewritten\n\n  // INDEX:           - ArCountPending\n  // =====\n  // Avoid putting on assertion directly as index is an integer\n  assign ArCountPending = RCountCam; // ### Rewritten\n\n\n//------------------------------------------------------------------------------\n// INDEX:   3) EXCL Accesses\n//------------------------------------------------------------------------------\n\n  // INDEX:        - Exclusive Access ID Lookup\n  // =====\n  // Map transaction IDs to the available exclusive access storage loactions\n\n  // Lookup table for IDs used by the exclusive access monitor\n  // Each location in the table has a valid flag to indicate if the ID is in use\n  // The location of an ID flagged as valid is used as a virtual ID in the\n  // exclusive access monitor checks\n  always @(posedge ACLK)\n  begin : p_ExclIdSeq\n    integer i;  // loop counter\n    if (!checker_main_resetn)\n    begin\n      ExclIdValid <= {EXMON_HI+1{1'b0}};\n      ExclIdDelta <= 1'b0;\n      for (i = 0; i <= EXMON_HI; i = i + 1)\n      begin\n        ExclId[i] <= {ID_MAX+1{1'b0}};\n      end\n    end else if (EXMON_WIDTH > 0) // clk edge\n    begin\n      // exclusive read address transfer\n      if (ARVALID && ARREADY && (internal_ARLOCK == `AXI4PC_ALOCK_EXCL) &&\n          !ExclIdFull)\n      begin\n        ExclId[ExclIdWrPtr] <= ARID;\n        ExclIdValid[ExclIdWrPtr] <= 1'b1;\n        ExclIdDelta <= ~ExclIdDelta;\n      end\n      // exclusive write\n      if (AWVALID && AWREADY && (internal_AWLOCK == `AXI4PC_ALOCK_EXCL) &&\n          ExclAwMatch)\n      begin\n        ExclIdValid[ExclAwId] <= 1'b0;\n        ExclIdDelta <= ~ExclIdDelta;\n      end\n    end // else: !if(!checker_main_resetn)\n  end // block: p_ExclIdSeq\n\n  // Lookup table is full when all valid bits are set\n  assign ExclIdFull = &ExclIdValid;\n\n  // Lookup table overflows when it is full and another exclusive read happens\n  // with an ID that does not match any already being monitored\n  assign ExclIdOverflow = ExclIdFull &&\n                          ARVALID && ARREADY && (internal_ARLOCK == `AXI4PC_ALOCK_EXCL) &&\n                          !ExclArMatch;\n\n  // New IDs are written to the highest location\n  // that does not have the valid flag set \n  always @(ExclIdValid)\n  begin : p_ExclIdFreePtrComb\n    integer i;  // loop counter\n    ExclIdFreePtr = 0;\n    for (i = 0; i <= EXMON_HI; i = i + 1)\n    begin\n      if (ExclIdValid[i] == 1'b0)\n      begin\n        ExclIdFreePtr = i;\n      end\n    end\n  end // p_ExclIdFreePtrComb\n\n  // If the ID is already being monitored then reuse the location\n  // New IDs are written to the highest location\n  // that does not have the valid flag set \n  assign ExclIdWrPtr = ExclArMatch ? ExclArId : ExclIdFreePtr;\n\n  // Write address ID comparator\n//  always @(AWVALID or AWID or ExclIdValid or ExclIdDelta or ExclId)\n  always @( * )\n  begin : p_ExclAwMatchComb\n    integer i;  // loop counter\n    ExclAwMatch = 1'b0;\n    ExclAwId = {LP_EXMON_WIDTH{1'b0}};\n    if (AWVALID)\n    begin\n      for (i = 0; i <= EXMON_HI; i = i + 1)\n      begin\n        if (ExclIdValid[i] && (AWID == ExclId[i]))\n        begin\n          ExclAwMatch = 1'b1;\n          ExclAwId = i;\n        end\n      end\n    end\n  end // p_ExclAwMatchComb\n\n  // Read address ID comparator\n//  always @(ARVALID or ARID or ExclIdValid or ExclIdDelta or ExclId)\n  always @( * )\n  begin : p_ExclArMatchComb\n    integer i;  // loop counter\n    ExclArMatch = 1'b0;\n    ExclArId = {LP_EXMON_WIDTH{1'b0}};\n    if (ARVALID)\n    begin\n      for (i = 0; i <= EXMON_HI; i = i + 1)\n      begin\n        if (ExclIdValid[i] && (ARID == ExclId[i]))\n        begin\n          ExclArMatch = 1'b1;\n          ExclArId = i;\n        end\n      end\n    end\n  end // p_ExclArMatchComb\n\n  // Read data ID comparator\n  always @( * )\n  begin : p_ExclRMatchComb\n    integer i;  // loop counter\n    ExclRMatch = 1'b0;\n    ExclRId = {LP_EXMON_WIDTH{1'b0}};\n    if (RVALID)\n    begin\n      for (i = 0; i <= EXMON_HI; i = i + 1)\n      begin\n        if (ExclIdValid[i] && (RID == ExclId[i]))\n        begin\n          ExclRMatch = 1'b1;\n          ExclRId = i;\n        end\n      end\n    end\n  end // p_ExclRMatchComb\n\n  // INDEX:        - Exclusive Access Storage\n  // =====\n  // Store exclusive control info on each read for checking against write\n\n  always @(posedge ACLK)\n  begin : p_ExclCtrlSeq\n    integer i;  // loop counter\n\n    if (!checker_main_resetn)\n      for (i = 0; i <= EXMON_HI; i = i + 1)\n      begin\n        ExclReadAddr[i] <= 1'b0;\n        ExclReadData[i] <= 1'b0;\n        ExclAddr[i]     <= {LP_ADDR_WIDTH{1'b0}};\n        ExclSize[i]     <= 3'b000;\n        ExclLen[i]      <= {8{1'b0}};\n        ExclBurst[i]    <= 2'b00;\n        ExclCache[i]    <= {4{1'b0}};\n        ExclProt[i]     <= {3{1'b0}};\n        ExclQos[i]      <= {4{1'b0}};\n        ExclRegion[i]   <= {4{1'b0}};\n        ExclUser[i]     <= {ARUSER_MAX+1{1'b0}};\n      end\n    else if (EXMON_WIDTH > 0) // clk edge\n    begin\n      // exclusive read address transfer\n      if (ARVALID && ARREADY && (internal_ARLOCK == `AXI4PC_ALOCK_EXCL) &&\n          !ExclIdFull)\n      begin\n        ExclReadAddr[ExclIdWrPtr] <= 1'b1; // set exclusive read addr flag for ARID\n        ExclReadData[ExclIdWrPtr] <= 1'b0; // reset exclusive read data flag for ARID\n        ExclAddr[ExclIdWrPtr]     <= araddr;\n        ExclSize[ExclIdWrPtr]     <= ARSIZE;\n        ExclLen[ExclIdWrPtr]      <= ARLEN;\n        ExclBurst[ExclIdWrPtr]    <= ARBURST;\n        ExclCache[ExclIdWrPtr]    <= ARCACHE;\n        ExclProt[ExclIdWrPtr]     <= ARPROT;\n        ExclQos[ExclIdWrPtr]      <= ARQOS;\n        ExclRegion[ExclIdWrPtr]   <= ARREGION;\n        ExclUser[ExclIdWrPtr]     <= ARUSER;\n      end\n      // exclusive write\n      if (AWVALID && AWREADY && (internal_AWLOCK == `AXI4PC_ALOCK_EXCL) &&\n          ExclAwMatch)\n      begin\n        ExclReadAddr[ExclAwId] <= 1'b0; // reset exclusive address flag for AWID\n        ExclReadData[ExclAwId] <= 1'b0; // reset exclusive read data flag for AWID\n      end\n      // completion of exclusive read data transaction\n      if ((RVALID && RREADY && RLAST && ExclReadAddr[ExclRId] &&\n           ExclRMatch) &&\n           // check the read CAM that this is part of an exclusive transfer\n           RBurstCam[EXCL] // ### Rewritten\n         )\n        ExclReadData[ExclRId]  <= 1'b1; // set exclusive read data flag for RID\n    end // else: !if(!checker_main_resetn)\n  end // block: p_ExclCtrlSeq\n\n//------------------------------------------------------------------------------\n// INDEX:   4) Content addressable memories (CAMs)\n//------------------------------------------------------------------------------\n\n  assign WriteDataNumError = WDataNumError1;\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiation\n  /////////////////////////////////////////////////////////////////////////////\n\n  assign i_RecommendOn  = (RecommendOn == 0)     ? 1'b0 : 1'b1;\n  assign i_RecMaxWaitOn = (RecommendWaitOn == 0) ? 1'b0 : 1'b1;\n\n  assign ExclAddr_indexed     = ExclAddr[ExclAwId];\n  assign ExclSize_indexed     = ExclSize[ExclAwId];\n  assign ExclLen_indexed      = ExclLen[ExclAwId];\n  assign ExclBurst_indexed    = ExclBurst[ExclAwId];\n  assign ExclCache_indexed    = ExclCache[ExclAwId];\n  assign ExclProt_indexed     = ExclProt[ExclAwId];\n  assign ExclRegion_indexed   = ExclRegion[ExclAwId];\n  assign ExclReadAddr_indexed = ExclReadAddr[ExclAwId];\n  assign ExclReadData_indexed = ExclReadData[ExclAwId];\n\n  axi_protocol_checker_v1_1_12_axi4pc_asr_inline #\n  (\n     .DATA_WIDTH   (C_AXI_DATA_WIDTH),\n     .ID_WIDTH     (C_AXI_ID_WIDTH),\n     .AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),\n     .WUSER_WIDTH  (C_AXI_WUSER_WIDTH),\n     .BUSER_WIDTH  (C_AXI_BUSER_WIDTH),\n     .ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),\n     .RUSER_WIDTH  (C_AXI_RUSER_WIDTH),\n     .MAXRBURSTS   (MAXRBURSTS),\n     .MAXWBURSTS   (MAXWBURSTS),\n     .ADDR_WIDTH   (LP_ADDR_WIDTH),\n     .DATA_MAX     (DATA_MAX),\n     .ADDR_MAX     (LP_ADDR_WIDTH - 1),\n     .STRB_WIDTH   (STRB_WIDTH),\n     .STRB_MAX     (STRB_MAX),\n     .ID_MAX       (ID_MAX),\n     .AWUSER_MAX   (AWUSER_MAX),\n     .WUSER_MAX    (WUSER_MAX),\n     .BUSER_MAX    (BUSER_MAX),\n     .ARUSER_MAX   (ARUSER_MAX),\n     .RUSER_MAX    (RUSER_MAX),\n     .MAX_AW_WAITS (MAX_AW_WAITS),\n     .MAX_AR_WAITS (MAX_AR_WAITS),\n     .MAX_W_WAITS  (MAX_W_WAITS),\n     .MAX_R_WAITS  (MAX_R_WAITS),\n     .MAX_B_WAITS  (MAX_B_WAITS)\n   )\n  i_Axi4PC_asr_inline\n  (\n     .Axi4PC_asr_inline_out (Axi4PC_asr_inline_out),\n     .reset                 (resetn_out),\n     .AWVALID               (AWVALID),\n     .AWBURST               (AWBURST),\n     .AwAddrIncr            (AwAddrIncr),\n     .AWADDR                (awaddr),\n     .ACLK                  (ACLK),\n     .AlignMaskW            (AlignMaskW),\n     .AWLEN                 (AWLEN),\n     .AWLOCK                (internal_AWLOCK),\n     .AWCACHE               (AWCACHE),\n     .AwSizeInBits          (AwSizeInBits),\n     .ARESETn               (ARST_N),\n     .AWREADY               (AWREADY),\n     .AWID                  (AWID),\n     .AWPROT                (AWPROT),\n     .AWSIZE                (AWSIZE),\n     .AWQOS                 (AWQOS),\n     .AWREGION              (AWREGION),\n     .i_RecommendOn         (i_RecommendOn),\n     .i_RecMaxWaitOn        (i_RecMaxWaitOn),\n     .WriteDataNumError     (WriteDataNumError),\n     .BStrbError            (BStrbError),\n     .WVALID                (WVALID),\n     .WREADY                (WREADY),\n     .WDATA                 (WDATA),\n     .WLAST                 (WLAST),\n     .WSTRB                 (WSTRB),\n     .BrespErrorLast        (1'b0),\n     .BrespExokError        (1'b0),\n     .BVALID                (BVALID),\n     .BrespErrorLead        (BrespErrorLead),\n     .BREADY                (BREADY),\n     .BID                   (BID),\n     .BRESP                 (BRESP),\n     .ARVALID               (ARVALID),\n     .ARBURST               (ARBURST),\n     .ArAddrIncr            (ArAddrIncr),\n     .ARADDR                (araddr),\n     .AlignMaskR            (AlignMaskR),\n     .ARLEN                 (ARLEN),\n     .ARLOCK                (internal_ARLOCK),\n     .ARCACHE               (ARCACHE),\n     .ArSizeInBits          (ArSizeInBits),\n     .ARREADY               (ARREADY),\n     .ARID                  (ARID),\n     .ARPROT                (ARPROT),\n     .ARSIZE                (ARSIZE),\n     .ARQOS                 (ARQOS),\n     .ARREGION              (ARREGION),\n     .RVALID                (RVALID),\n     .RREADY                (RREADY),\n     .ArCountPending        (ArCountPending),\n     .ArLenPending          (ArLenPending),\n     .RLAST                 (RLAST),\n     .RidMatch              (RidMatch),\n     .RRESP                 (RRESP),\n     .ArExclPending         (ArExclPending),\n     .RDATA                 (RDATA),\n     .RID                   (RID),\n     .CSYSREQ               (1'b0),\n     .CSYSACK               (1'b0),\n     .ExclMask              (ExclMask),\n     .ExclReadAddr          (ExclReadAddr_indexed),\n     .ExclAwMatch           (ExclAwMatch),\n     .ExclAddr              (ExclAddr_indexed),\n     .ExclSize              (ExclSize_indexed),\n     .ExclLen               (ExclLen_indexed),\n     .ExclBurst             (ExclBurst_indexed),\n     .ExclCache             (ExclCache_indexed),\n     .ExclProt              (ExclProt_indexed),\n     .ExclRegion            (ExclRegion_indexed),\n     .ArLenInBytes          (ArLenInBytes),\n     .ExclReadData          (ExclReadData_indexed),\n     .AWUSER                (AWUSER),\n     .WUSER                 (WUSER),\n     .BUSER                 (BUSER),\n     .ARUSER                (ARUSER),\n     .RUSER                 (RUSER)\n   );\n\n\n  generate\n    if (C_AXI_PROTOCOL == 2) begin : LITE\n      axi_protocol_checker_v1_1_12_axi4litepc_asr_inline #\n      (\n         .DATA_WIDTH (C_AXI_DATA_WIDTH)\n       )\n      i_Axi4LitePC_asr_inline\n      (\n         .Axi4LitePC_asr_inline_out (Axi4LitePC_asr_inline_out),\n         .reset                     (resetn_out),\n         .BVALID                    (BVALID),\n         .BRESP                     (BRESP),\n         .ACLK                      (ACLK),\n         .RVALID                    (RVALID),\n         .RRESP                     (RRESP)\n       );\n    end else begin : NO_LITE\n      assign Axi4LitePC_asr_inline_out = 3'b000;\n    end\n  endgenerate\n  \n\n  /////////////////////////////////////////////////////////////////////////////\n  // Error output masking and latching\n  /////////////////////////////////////////////////////////////////////////////\n\n  reg  [C_ERROR_COUNT-1:0] pc_status_i;\n  wire [C_ERROR_COUNT-1:0] pc_status_masked;\n\n  assign pc_status_masked = {xilinx_inline_out, Axi4LitePC_asr_inline_out, Axi4PC_aux, Axi4PC_asr_inline_out[78:1]};\n\n  always @(posedge ACLK)\n  begin : p_errorSeq\n    if (!checker_main_resetn) begin\n      pc_status_i <= {C_ERROR_COUNT {1'b0}};\n    end else begin\n      pc_status_i <= pc_status_masked | pc_status_i;\n    end\n  end\n\n  assign pc_status = pc_status_i;\n\n  assign AWPush = AWREADY & AWVALID;\n  assign WLastPush = WVALID & WREADY & WLAST;\n\n  /////////////////////////////////////////////////////////////////////////////\n  //AW-W checks\n  axi_protocol_checker_v1_1_12_syn_fifo # (\n    .C_DATA_WIDTH (WASIZEHI+1+8+C_AXI_ID_WIDTH),\n    .C_ADDR_WIDTH (log2(MAXWBURSTS))\n   ) AWCMD (\n    .clk      (ACLK),\n    .rst      (!checker_main_resetn),\n    .data_in  ({AWID,AWLEN,AWSIZE,awaddr[WADDRHI:WADDRLO]}),\n    .rd       (wcheckPop),\n    .wr       (AWPush),\n    .data_out ({AWIDOut, AWLENOut,AWStrbsizeOut, AWStrbAddrOut}),\n    .empty    (AWEmpty),\n    .full     (AWFull)\n  );\n  \n  axi_protocol_checker_v1_1_12_syn_fifo # (\n    .C_DATA_WIDTH (9+STRB_MAX+1),\n    .C_ADDR_WIDTH (log2(MAXWBURSTS))\n   ) WCHECK (\n    .clk      (ACLK),\n    .rst      (!checker_main_resetn),\n    .data_in  ({WCountIn,WstrbIn}),\n    .rd       (wcheckPop),\n    .wr       (WLastPush),\n    .data_out ({WCheckCountOut, WCheckstrbOut}),\n    .empty    (WCheckEmpty),\n    .full     (WCheckFull)\n  );\n\n  assign WstrbIn = (first_strb) ? WSTRB : WSTRBq;\n  assign wcheckPop = (!WCheckEmpty & !AWEmpty);\n\n  always @(posedge ACLK) begin : p_wstrb\n    if (!checker_main_resetn | (WVALID & WREADY & WLAST)) begin\n      WSTRBq <= {C_AXI_DATA_WIDTH/8{1'b0}};\n      first_strb <= 1'b1;\n    end else if (WVALID & WREADY & first_strb) begin\n      first_strb <= 1'b0;\n      WSTRBq <= WSTRB;\n    end\n  end\n\ninteger id_cnt;\n\nlocalparam L_CHECK_PIPE_WIDTH = 7;\n\nreg   [STRB_MAX:0] StrbMask_q1;  \nreg   [STRB_MAX:0] StrbMask_q2;  \nreg   [STRB_MAX:0] StrbMask_q3_n;  \n\nreg          [6:0] StrbAddr_q1;\nreg          [6:0] StrbAddr_q2;\nreg          [2:0] StrbSize_q1;\nreg          [2:0] StrbSize_q2;\nreg   [STRB_MAX:0] Strb_q1;\nreg   [STRB_MAX:0] Strb_q2;\nreg   [STRB_MAX:0] Strb_q3;\nreg          [L_CHECK_PIPE_WIDTH-1:0] wchechPop_shift;\nreg                CheckStrbAssert;\nreg          [6:0] mask_shift_stage_1;\nreg          [6:0] mask_shift_stage_2;\nreg          [6:0] mask_shift_stage_2_q1;\n\nalways @(posedge ACLK) begin\n  StrbAddr_q1 <= AWStrbAddrOut;\n  StrbAddr_q2 <= StrbAddr_q1;\n  StrbSize_q1 <= AWStrbsizeOut;\n  StrbSize_q2 <= StrbSize_q1;\n  Strb_q1 <= WCheckstrbOut;\n  Strb_q2 <= Strb_q1;\n  Strb_q3 <= Strb_q2;\n\n  mask_shift_stage_1 <= (AWStrbAddrOut & ((STRB_1 << AWStrbsizeOut) -  STRB_1));\n  mask_shift_stage_2 <= (AWStrbAddrOut & ((STRB_MAX << AWStrbsizeOut) & STRB_MAX));\n  mask_shift_stage_2_q1 <= mask_shift_stage_2;\n  // The basic strobe for an aligned address\n  StrbMask_q1 <= (STRB_1 << (STRB_1 << AWStrbsizeOut)) - STRB_1;\n  // Zero the unaligned byte lanes\n  // Note: the number of unaligned byte lanes is given by:\n  // (StrbAddr & ((1 << StrbSize) - 1)), i.e. the unaligned part of the\n  // address with respect to the transfer size\n  //\n  // Note! {{STRB_MAX{1'b0}}, 1'b1} gives 1 in the correct vector length\n  StrbMask_q2 <= StrbMask_q1 &                    // Mask off unaligned byte lanes\n    (StrbMask_q1 << mask_shift_stage_1);          // shift the strb mask left by the number of unaligned byte lanes\n\n  StrbMask_q3_n <= ~(StrbMask_q2 << mask_shift_stage_2_q1);\n\nend\n\nlocalparam integer L_NUM_CHKSTRB_NIBS       = (((C_AXI_DATA_WIDTH/8) + 3) / 4);\nlocalparam integer L_NUM_CHKSTRB_NIB_LANES  = ((L_NUM_CHKSTRB_NIBS + 3) / 4) * 4;\nlocalparam integer L_NUM_CHKSTRB_EQ_LANES    = (L_NUM_CHKSTRB_NIB_LANES / 4);\nlocalparam integer L_NUM_CHKSTRB_AND1_LANES  = (L_NUM_CHKSTRB_EQ_LANES + 3) / 4;\nlocalparam integer L_NUM_CHKSTRB_AND2_LANES  = (L_NUM_CHKSTRB_AND1_LANES + 3) / 4;\n\nreg [(4*L_NUM_CHKSTRB_EQ_LANES)-1:0]    CHKSTRB_eq;\nreg [(4*L_NUM_CHKSTRB_AND1_LANES)-1:0]  CHKSTRB_stage_1_eq;\nreg [(4*L_NUM_CHKSTRB_AND2_LANES)-1:0]  CHKSTRB_stage_2_eq;\n\n//assign s_CHKSTRB_sqaa = &CHKSTRB_stage_2_eq;\n\ninteger CHKSTRB_bc;\ninteger CHKSTRB_stage_1;\ninteger CHKSTRB_stage_2;\n\nalways @(posedge ACLK) begin\n  for (CHKSTRB_bc = 0; CHKSTRB_bc < L_NUM_CHKSTRB_EQ_LANES*4; CHKSTRB_bc = CHKSTRB_bc + 1) begin : CHKSTRB_BC_LOOP\n    if (CHKSTRB_bc < ((C_AXI_DATA_WIDTH/8)/4)) begin\n      CHKSTRB_eq[CHKSTRB_bc] <= |(Strb_q3[CHKSTRB_bc*4 +:4] & StrbMask_q3_n[CHKSTRB_bc*4 +: 4]);\n    end else begin\n      CHKSTRB_eq[CHKSTRB_bc] <= 1'b0;\n    end\n  end\n\n  for (CHKSTRB_stage_1 = 0; CHKSTRB_stage_1 < L_NUM_CHKSTRB_AND1_LANES * 4;CHKSTRB_stage_1 = CHKSTRB_stage_1 + 1) begin : CHKSTRB_S1\n    if (CHKSTRB_stage_1 < L_NUM_CHKSTRB_EQ_LANES) begin\n      CHKSTRB_stage_1_eq[CHKSTRB_stage_1] <= |CHKSTRB_eq[CHKSTRB_stage_1*4 +:4];\n    end else begin\n      CHKSTRB_stage_1_eq[CHKSTRB_stage_1] <= 1'b0;\n    end\n  end\n\n  for (CHKSTRB_stage_2 = 0; CHKSTRB_stage_2 < L_NUM_CHKSTRB_AND2_LANES * 4;CHKSTRB_stage_2 = CHKSTRB_stage_2 + 1) begin : CHKSTRB_S2\n    if (CHKSTRB_stage_2 < L_NUM_CHKSTRB_AND1_LANES) begin\n      CHKSTRB_stage_2_eq[CHKSTRB_stage_2] <= |CHKSTRB_stage_1_eq[CHKSTRB_stage_2*4 +:4];\n    end else begin\n      CHKSTRB_stage_2_eq[CHKSTRB_stage_2] <= 1'b0;\n    end\n  end\n\nend\n\n\nalways @(posedge ACLK) begin : bstrb_check\n  if (!checker_main_resetn) begin\n    BStrbError <= 1'b0;\n    wchechPop_shift <= {L_CHECK_PIPE_WIDTH{1'b0}};\n    CheckStrbAssert <= 1'b0;\n  end else begin\n    wchechPop_shift <= {wchechPop_shift[(L_CHECK_PIPE_WIDTH-2):0], wcheckPop};\n    BStrbError <= wchechPop_shift[(L_CHECK_PIPE_WIDTH-1)] & CheckStrbAssert;\n    CheckStrbAssert <= |CHKSTRB_stage_2_eq;\n  end\nend\n\n  always @(posedge ACLK) begin : p_check\n    if (!checker_main_resetn) begin\n      WDataNumError1 <= 1'b0;\n      for (id_cnt = 0; id_cnt <= ID_SIZE; id_cnt = id_cnt + 1) begin\n        AWXferCount[id_cnt] <= {log2(MAXWBURSTS) + 1{1'b0}};\n      end\n      BrespErrorLead <= 1'b0;\n      AWXferCountOverflow <= 1'b0;\n    end else begin\n      WDataNumError1 <= 1'b0;\n      BrespErrorLead <= 1'b0;\n      AWXferCountOverflow <= 1'b0;\n      if (wcheckPop) begin\n        WDataNumError1 <= (WCheckCountOut != {1'b0,AWLENOut});\n      end\n      ////////////////////////////////////////////////////////////////\n      //Count the number of AWID's and BID's\n      if (!(wcheckPop & (BVALID & BREADY) & (BID == AWIDOut))) begin\n        ////////////////////////////////////////////////////////////////\n        //  Increment on AWID - AW+WLast's Complete\n        // Trigger error when \n        if (wcheckPop == 1'b1) begin\n          if (AWXferCount[AWIDOut] == {1'b1,{log2(MAXWBURSTS){1'b0}}}) begin\n            AWXferCountOverflow <= 1'b1;\n          end\n          AWXferCount[AWIDOut] <= AWXferCount[AWIDOut] + 1;\n        end\n        ////////////////////////////////////////////////////////////////\n        //  Decrement on BID  - B Complete\n        if (BVALID & BREADY) begin\n          if (AWXferCount[BID] == 0) begin\n            //Trigger Error of B->{AW or W}\n            BrespErrorLead <= 1'b1;\n          end else begin\n            AWXferCount[BID] <= AWXferCount[BID] - 1;\n          end\n        end\n      end\n    end\n  end\n\n//////////////////////////////////////////////////////////////////////////////////////////////////\n//Xilinx Checks\nwire [2:0]  awready_s;\nwire [2:0]  wready_s;\nwire [2:0]  bready_s;\nwire [2:0]  arready_s;\nwire [2:0]  rready_s;\n\nreg  [2:0]  awready_sq;\nreg  [2:0]  wready_sq;\nreg  [2:0]  bready_sq;\nreg  [2:0]  arready_sq;\nreg  [2:0]  rready_sq;\n\nalways @(posedge ACLK) begin : xil_check\n  if (!resetn_out) begin\n    xilinx_inline_out <= 11'h000;\n    awready_sq <= 3'h4;\n    wready_sq <= 3'h4;\n    bready_sq <= 3'h4;\n    arready_sq <= 3'h4;\n    rready_sq <= 3'h4;\n  end else begin\n    xilinx_inline_out[1] <= (C_PC_SUPPORTS_NARROW_BURST == 0) && (AWVALID && (AWLEN > 0) && (AwSizeInBits < C_AXI_DATA_WIDTH));\n    xilinx_inline_out[2] <= (C_PC_SUPPORTS_NARROW_BURST == 0) && (ARVALID && (ARLEN > 0) && (ArSizeInBits < C_AXI_DATA_WIDTH));\n    xilinx_inline_out[3] <= (C_PC_SUPPORTS_NARROW_BURST == 0) && (AWVALID && (AWLEN > 0) && !(AWCACHE[1]));\n    xilinx_inline_out[4] <= (C_PC_SUPPORTS_NARROW_BURST == 0) && (ARVALID && (ARLEN > 0) && !(ARCACHE[1]));\n    xilinx_inline_out[5] <= (AWVALID && !(AWLEN <= (C_PC_MAX_BURST_LENGTH - 1)));\n    xilinx_inline_out[6] <= (ARVALID && !(ARLEN <= (C_PC_MAX_BURST_LENGTH - 1)));\n\n    //////////////////////////////////////////////////////////////////////////////////////////////////\n    //Xilinx xREADY checks : xREADY is LOW for the first cycle after ARESETn goes HIGH.\n    awready_sq  <= awready_s;\n    wready_sq   <= wready_s;\n    bready_sq   <= bready_s;\n    arready_sq  <= arready_s;\n    rready_sq   <= rready_s;\n\n    xilinx_inline_out[7] <= (awready_s[0]);\n    xilinx_inline_out[8] <= ( wready_s[0]);\n    xilinx_inline_out[9] <= ( bready_s[0]);\n    xilinx_inline_out[10] <= (arready_s[0]);\n    xilinx_inline_out[11] <= ( rready_s[0]);\n  end\nend\n\nassign awready_s  = {1'b1, !(ARST_N), (awready_sq[1] && (ARST_N && AWREADY))};\nassign wready_s   = {1'b1, !(ARST_N), ( wready_sq[1] && (ARST_N &&  WREADY))};\nassign bready_s   = {1'b1, !(ARST_N), ( bready_sq[1] && (ARST_N &&  BREADY))};\nassign arready_s  = {1'b1, !(ARST_N), (arready_sq[1] && (ARST_N && ARREADY))};\nassign rready_s   = {1'b1, !(ARST_N), ( rready_sq[1] && (ARST_N &&  RREADY))};\n\nendmodule\n`default_nettype wire\n\n\n//*****************************************************************************\n// (c) Copyright 2011-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// Design Name      : axi_protocol_checker_v1_1_12_syn_fifo\n// Function         : synchronous FIFO\n// Reference        : None\n// Revision History : Initial version\n//*****************************************************************************\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_protocol_checker_v1_1_12_syn_fifo #\n  (\n   parameter C_DATA_WIDTH = 8,\n   parameter C_ADDR_WIDTH = 4\n   )\n  (\n   input  wire                    clk,\n   input  wire                    rst,\n\n   input  wire [C_DATA_WIDTH-1:0] data_in,\n   input  wire                    rd,\n   input  wire                    wr,\n   output wire [C_DATA_WIDTH-1:0] data_out,\n   output wire                    empty,\n   output wire                    full\n  );\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n\n  localparam RAM_SIZE = (1 << C_ADDR_WIDTH);\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n\n  reg [C_ADDR_WIDTH-1:0] wr_ptr;\n  reg [C_ADDR_WIDTH-1:0] rd_ptr;\n  reg [C_ADDR_WIDTH:0]   cnt;\n\n  (* ram_style=\"distributed\" *)\n  reg [C_DATA_WIDTH-1:0] data_ram[RAM_SIZE-1:0];\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Code\n  /////////////////////////////////////////////////////////////////////////////\n\n  assign full  = (cnt == RAM_SIZE);\n  assign empty = (cnt == 0);\n\n  always @(posedge clk)\n  begin : COUNTER\n    if (rst) begin\n      cnt <= 0;\n    end else if (rd && !wr && (cnt != 0)) begin\n      cnt <= cnt - 1; // Just read: decrement\n    end else if (wr && !rd && (cnt != RAM_SIZE)) begin\n      cnt <= cnt + 1; // Just write: increment\n    end\n  end\n\n  always @(posedge clk)\n  begin : WRITE_PTR\n    if (rst) begin\n      wr_ptr <= 0;\n    end else if (wr) begin\n      wr_ptr <= wr_ptr + 1;\n    end\n  end\n\n  always @(posedge clk)\n  begin : READ_PTR\n    if (rst) begin\n      rd_ptr <= 0;\n    end else if (rd) begin\n      rd_ptr <= rd_ptr + 1;\n    end\n  end\n\n  // Distributed RAM\n  always @(posedge clk)\n  begin\n    if (wr)\n      data_ram[wr_ptr] <= data_in;\n  end\n\n  assign data_out = data_ram[rd_ptr];\n\nendmodule\n\n`default_nettype wire\n\n\n// (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n\n\n`timescale 1ps/1ps\n`default_nettype none\n`ifndef AXI4PC_MESSAGES\n  `define AXI4PC_MESSAGES\n  `define ERRM_AWADDR_BOUNDARY      \"AXI_ERRM_AWADDR_BOUNDARY. A write burst cannot cross a 4kbyte boundary. Spec: section 4.1 on page 4-2.\"\n  `define ERRM_AWADDR_WRAP_ALIGN    \"AXI_ERRM_AWADDR_WRAP_ALIGN. A write transaction with burst type WRAP must have an aligned address. Spec: section 4.4.3 on page 4-6.\"\n  `define ERRM_AWBURST              \"AXI_ERRM_AWBURST. When AWVALID is high, a value of 2'b11 on AWBURST is not permitted. Spec: table 4-3 on page 4-5.\"\n  `define ERRM_AWCACHE              \"AXI_ERRM_AWCACHE. A reserved value on AWCACHE is not allowed. Spec: table 5-1 on page 5-3.\"\n  `define ERRM_ARCACHE              \"AXI_ERRM_ARCACHE. A reserved value on ARCACHE is not allowed. Spec: table 5-1 on page 5-3.\"\n  `define ERRM_AWLEN_WRAP           \"AXI_ERRM_AWLEN_WRAP. A write transaction with burst type WRAP must have length 2, 4, 8 or 16. Spec: section 4.4.3 on page 4-6.\"\n  `define ERRM_AWSIZE               \"AXI_ERRM_AWSIZE. The size of a write transfer must not exceed the width of the data port. Spec: section 4.3 on page 4-4.\"\n  `define ERRM_AWVALID_RESET        \"AXI_ERRM_AWVALID_RESET. AWVALID must be low for the first clock edge that ARESETn goes high. Spec: section 11.1.2 on page 11-2.\"\n  `define ERRM_AWADDR_STABLE        \"AXI_ERRM_AWADDR_STABLE. AWADDR must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWBURST_STABLE       \"AXI_ERRM_AWBURST_STABLE. AWBURST must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWCACHE_STABLE       \"AXI_ERRM_AWCACHE_STABLE. AWCACHE must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWID_STABLE          \"AXI_ERRM_AWID_STABLE. AWID must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWLEN_STABLE         \"AXI_ERRM_AWLEN_STABLE. AWLEN must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWLOCK_STABLE        \"AXI_ERRM_AWLOCK_STABLE. AWLOCK must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWPROT_STABLE        \"AXI_ERRM_AWPROT_STABLE. AWPROT must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWSIZE_STABLE        \"AXI_ERRM_AWSIZE_STABLE. AWSIZE must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWQOS_STABLE         \"AXI_ERRM_AWQOS_STABLE. AWQOS must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWREGION_STABLE      \"AXI_ERRM_AWREGION_STABLE. AWREGION must remain stable when ARVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWVALID_STABLE       \"AXI_ERRM_AWVALID_STABLE. Once AWVALID is asserted, it must remain asserted until AWREADY is high. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWADDR_X             \"AXI_ERRM_AWADDR_X. When AWVALID is high, a value of X on AWADDR is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWBURST_X            \"AXI_ERRM_AWBURST_X. When AWVALID is high, a value of X on AWBURST is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWCACHE_X            \"AXI_ERRM_AWCACHE_X. When AWVALID is high, a value of X on AWCACHE is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWID_X               \"AXI_ERRM_AWID_X. When AWVALID is high, a value of X on AWID is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWLEN_X              \"AXI_ERRM_AWLEN_X. When AWVALID is high, a value of X on AWLEN is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWLOCK_X             \"AXI_ERRM_AWLOCK_X. When AWVALID is high, a value of X on AWLOCK is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWPROT_X             \"AXI_ERRM_AWPROT_X. When AWVALID is high, a value of X on AWPROT is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWSIZE_X             \"AXI_ERRM_AWSIZE_X. When AWVALID is high, a value of X on AWSIZE is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWQOS_X              \"AXI_ERRM_AWQOS_X. When AWVALID is high, a value of X on AWQOS is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWREGION_X           \"AXI_ERRM_AWREGION_X. When AWVALID is high, a value of X on AWREGION is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWVALID_X            \"AXI_ERRM_AWVALID_X. When not in reset, a value of X on AWVALID is not permitted.\"\n  `define ERRS_AWREADY_X            \"AXI_ERRS_AWREADY_X. When not in reset, a value of X on AWREADY is not permitted.\"\n  `define ERRM_WDATA_NUM            \"AXI_ERRM_WDATA_NUM. The number of write data items must match AWLEN for the corresponding address. Spec: table 4-1 on page 4-3.\"\n  `define ERRM_WSTRB                \"AXI_ERRM_WSTRB. Write strobes must only be asserted for the correct byte lanes as determined from start address, transfer size and beat number. Spec: section 9.2 on page 9-3.\"\n  `define ERRM_WVALID_RESET         \"AXI_ERRM_WVALID_RESET. WVALID must be low for the first clock edge that ARESETn goes high. Spec: section 11.1.2 on page 11-2.\"\n  `define ERRM_WDATA_STABLE         \"AXI_ERRM_WDATA_STABLE. WDATA must remain stable when WVALID is asserted and WREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_WLAST_STABLE         \"AXI_ERRM_WLAST_STABLE. WLAST must remain stable when WVALID is asserted and WREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_WSTRB_STABLE         \"AXI_ERRM_WSTRB_STABLE. WSTRB must remain stable when WVALID is asserted and WREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_WVALID_STABLE        \"AXI_ERRM_WVALID_STABLE. Once WVALID is asserted, it must remain asserted until WREADY is high. Spec: section 3.1.2 on page 3-3.\"\n  `define ERRM_WDATA_X              \"AXI_ERRM_WDATA_X. When WVALID is high, a value of X on active byte lanes of WDATA is not permitted.\"\n  `define ERRM_WLAST_X              \"AXI_ERRM_WLAST_X. When WVALID is high, a value of X on WLAST is not permitted.\"\n  `define ERRM_WSTRB_X              \"AXI_ERRM_WSTRB_X. When WVALID is high, a value of X on WSTRB is not permitted.\"\n  `define ERRM_WVALID_X             \"AXI_ERRM_WVALID_X. When not in reset, a value of X on WVALID is not permitted.\"\n  `define ERRS_WREADY_X             \"AXI_ERRS_WREADY_X. When not in reset, a value of X on WREADY is not permitted.\"\n  `define ERRS_BRESP_WLAST          \"AXI_ERRS_BRESP_WLAST. A slave must only give a write response after the last write data item is transferred. Spec: section 3.3 on page 3-6, and figure 3-5 on page 3-8.\"\n  `define ERRS_BRESP_ALL_DONE_EOS   \"AXI_ERRS_BRESP_ALL_DONE_EOS. All write transaction addresses must have been matched with corresponding write response.\"\n  `define ERRS_BRESP_EXOKAY         \"AXI_ERRS_BRESP_EXOKAY. An EXOKAY write response can only be given to an exclusive write access. Spec: section 6.2.3 on page 6-4.\"\n  `define ERRS_BVALID_RESET         \"AXI_ERRS_BVALID_RESET. BVALID must be low for the first clock edge that ARESETn goes high. Spec: section 11.1.2 on page 11-2.\"\n  `define ERRS_BRESP_AW             \"AXI_ERRS_BRESP_AW. A slave must not give a write response before the write address. Spec: section 13.4.1 on page 13-6, and figure 13-1 on page 13-6.\"\n  `define ERRS_BID_STABLE           \"AXI_ERRS_BID_STABLE. BID must remain stable when BVALID is asserted and BREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRS_BRESP_STABLE         \"AXI_ERRS_BRESP_STABLE. BRESP must remain stable when BVALID is asserted and BREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRS_BVALID_STABLE        \"AXI_ERRS_BVALID_STABLE. Once BVALID is asserted, it must remain asserted until BREADY is high. Spec: section 3.1.3 on page 3-3.\"\n  `define ERRM_BREADY_X             \"AXI_ERRM_BREADY_X. When not in reset, a value of X on BREADY is not permitted.\"\n  `define ERRS_BID_X                \"AXI_ERRS_BID_X. When BVALID is high, a value of X on BID is not permitted.\"\n  `define ERRS_BRESP_X              \"AXI_ERRS_BRESP_X. When BVALID is high, a value of X on BRESP is not permitted.  Spec: section 3.1.3 on page 3-4.\"\n  `define ERRS_BVALID_X             \"AXI_ERRS_BVALID_X. When not in reset, a value of X on BVALID is not permitted.\"\n  `define ERRM_ARADDR_BOUNDARY      \"AXI_ERRM_ARADDR_BOUNDARY. A read burst cannot cross a 4kbyte boundary. Spec: section 4.1 on page 4-2.\"\n  `define ERRM_ARADDR_WRAP_ALIGN    \"AXI_ERRM_ARADDR_WRAP_ALIGN. A read transaction with burst type WRAP must have an aligned address. Spec: section 4.4.3 on page 4-6.\"\n  `define ERRM_ARBURST              \"AXI_ERRM_ARBURST. When ARVALID is high, a value of 2'b11 on ARBURST is not permitted. Spec: table 4-3 on page 4-5.\"\n  `define ERRM_ARLEN_FIXED          \"AXI_ERRM_ARLEN_FIXED. Transactions of burst type FIXED cannot have a length greater than 16 beats. Spec: section 13.1.2 on page 13-2.\"\n  `define ERRM_AWLEN_FIXED          \"AXI_ERRM_AWLEN_FIXED. Transactions of burst type FIXED cannot have a length greater than 16 beats. Spec: section 13.1.2 on page 13-2.\"\n  `define ERRM_AWLEN_LOCK           \"AXI_ERRM_AWLEN_LOCK. Exclusive access transactions cannot have a length greater than 16 beats. Spec: section 13.1.2 on page 13-2.\"\n  `define ERRM_ARLEN_LOCK           \"AXI_ERRM_ARLEN_LOCK. Exclusive access transactions cannot have a length greater than 16 beats. Spec: section 13.1.2 on page 13-2.\"\n  `define ERRM_ARLEN_WRAP           \"AXI_ERRM_ARLEN_WRAP. A read transaction with burst type WRAP must have length 2, 4, 8 or 16. Spec: section 4.4.3 on page 4-6.\"\n  `define ERRM_ARSIZE               \"AXI_ERRM_ARSIZE. The size of a read transfer must not exceed the width of the data port. Spec: section 4.3 on page 4-4.\"\n  `define ERRM_ARVALID_RESET        \"AXI_ERRM_ARVALID_RESET. ARVALID must be low for the first clock edge that ARESETn goes high. Spec: section 11.1.2 on page 11-2.\"\n  `define ERRM_ARADDR_STABLE        \"AXI_ERRM_ARADDR_STABLE. ARADDR must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARBURST_STABLE       \"AXI_ERRM_ARBURST_STABLE. ARBURST must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARCACHE_STABLE       \"AXI_ERRM_ARCACHE_STABLE. ARCACHE must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARID_STABLE          \"AXI_ERRM_ARID_STABLE. ARID must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARLEN_STABLE         \"AXI_ERRM_ARLEN_STABLE. ARLEN must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARLOCK_STABLE        \"AXI_ERRM_ARLOCK_STABLE. ARLOCK must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARPROT_STABLE        \"AXI_ERRM_ARPROT_STABLE. ARPROT must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARSIZE_STABLE        \"AXI_ERRM_ARSIZE_STABLE. ARSIZE must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARQOS_STABLE         \"AXI_ERRM_ARQOS_STABLE. ARQOS must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARREGION_STABLE      \"AXI_ERRM_ARREGION_STABLE. ARREGION must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARVALID_STABLE       \"AXI_ERRM_ARVALID_STABLE. Once ARVALID is asserted, it must remain asserted until ARREADY is high. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARADDR_X             \"AXI_ERRM_ARADDR_X. When ARVALID is high, a value of X on ARADDR is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARBURST_X            \"AXI_ERRM_ARBURST_X. When ARVALID is high, a value of X on ARBURST is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARCACHE_X            \"AXI_ERRM_ARCACHE_X. When ARVALID is high, a value of X on ARCACHE is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARID_X               \"AXI_ERRM_ARID_X. When ARVALID is high, a value of X on ARID is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARLEN_X              \"AXI_ERRM_ARLEN_X. When ARVALID is high, a value of X on ARLEN is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARLOCK_X             \"AXI_ERRM_ARLOCK_X. When ARVALID is high, a value of X on ARLOCK is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARPROT_X             \"AXI_ERRM_ARPROT_X. When ARVALID is high, a value of X on ARPROT is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARSIZE_X             \"AXI_ERRM_ARSIZE_X. When ARVALID is high, a value of X on ARSIZE is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARQOS_X              \"AXI_ERRM_ARQOS_X. When ARVALID is high, a value of X on ARQOS is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARREGION_X           \"AXI_ERRM_ARREGION_X. When ARVALID is high, a value of X on ARREGION is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARVALID_X            \"AXI_ERRM_ARVALID_X. When not in reset, a value of X on ARVALID is not permitted.\"\n  `define ERRS_ARREADY_X            \"AXI_ERRS_ARREADY_X. When not in reset, a value of X on ARREADY is not permitted.\"\n  `define ERRS_RDATA_NUM            \"AXI_ERRS_RDATA_NUM. The number of read data items must match the corresponding ARLEN. Spec: table 4-1 on page 4-3.\"\n  `define ERRS_RLAST_ALL_DONE_EOS   \"AXI_ERRS_RLAST_ALL_DONE_EOS. All outstanding read bursts must have completed.\"\n  `define ERRS_RID                  \"AXI_ERRS_RID. A slave can only give read data in response to an outstanding read transaction, and the RID, if any, must match an outstanding ARID. Spec: section 3.1.5 on page 3-4, and section 8.3 on page 8-4.\"\n  `define ERRS_RRESP_EXOKAY         \"AXI_ERRS_RRESP_EXOKAY. An EXOKAY read response can only be given to an exclusive read access. Spec: section 6.2.3 on page 6-4.\"\n  `define ERRS_RVALID_RESET         \"AXI_ERRS_RVALID_RESET. RVALID must be low for the first clock edge that ARESETn goes high. Spec: section 11.1.2 on page 11-2.\"\n  `define ERRS_RDATA_STABLE         \"AXI_ERRS_RDATA_STABLE. RDATA must remain stable when RVALID is asserted and RREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRS_RID_STABLE           \"AXI_ERRS_RID_STABLE. RID must remain stable when RVALID is asserted and RREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRS_RLAST_STABLE         \"AXI_ERRS_RLAST_STABLE. RLAST must remain stable when RVALID is asserted and RREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRS_RRESP_STABLE         \"AXI_ERRS_RRESP_STABLE. RRESP must remain stable when RVALID is asserted and RREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRS_RVALID_STABLE        \"AXI_ERRS_RVALID_STABLE. Once RVALID is asserted, it must remain asserted until RREADY is high. Spec: section 3.1.5 on page 3-4.\"\n  `define ERRS_RDATA_X              \"AXI_ERRS_RDATA_X. When RVALID is high, a value of X on RDATA valid byte lanes is not permitted.\"\n  `define ERRM_RREADY_X             \"AXI_ERRM_RREADY_X. When not in reset, a value of X on RREADY is not permitted.\"\n  `define ERRS_RID_X                \"AXI_ERRS_RID_X. When RVALID is high, a value of X on RID is not permitted.\"\n  `define ERRS_RLAST_X              \"AXI_ERRS_RLAST_X. When RVALID is high, a value of X on RLAST is not permitted.\"\n  `define ERRS_RRESP_X              \"AXI_ERRS_RRESP_X. When RVALID is high, a value of X on RRESP is not permitted.\"\n  `define ERRS_RVALID_X             \"AXI_ERRS_RVALID_X. When not in reset, a value of X on RVALID is not permitted.\"\n  `define ERRL_CSYSACK_FALL         \"AXI_ERRL_CSYSACK_FALL. When CSYSACK transitions from high to low, CSYSREQ must be low. Spec: figure 12-1 on page 12-3.\"\n  `define ERRL_CSYSACK_RISE         \"AXI_ERRL_CSYSACK_RISE. When CSYSACK transitions from low to high, CSYSREQ must be high. Spec: figure 12-1 on page 12-3.\"\n  `define ERRL_CSYSREQ_FALL         \"AXI_ERRL_CSYSREQ_FALL. When CSYSREQ transitions from high to low, CSYSACK must be high. Spec: figure 12-1 on page 12-3.\"\n  `define ERRL_CSYSREQ_RISE         \"AXI_ERRL_CSYSREQ_RISE. When CSYSREQ transitions from low to high, CSYSACK must be low. Spec: figure 12-1 on page 12-3.\"\n  `define ERRL_CACTIVE_X            \"AXI_ERRL_CACTIVE_X. When not in reset, a value of X on CACTIVE is not permitted.\"\n  `define ERRL_CSYSACK_X            \"AXI_ERRL_CSYSACK_X. When not in reset, a value of X on CSYSACK is not permitted.\"\n  `define ERRL_CSYSREQ_X            \"AXI_ERRL_CSYSREQ_X. When not in reset, a value of X on CSYSREQ is not permitted.\"\n  `define ERRM_EXCL_ALIGN           \"AXI_ERRM_EXCL_ALIGN. The address of an exclusive access must be aligned to the total number of bytes in the transaction. Spec: section 6.2.4 on page 6-4.\"\n  `define ERRM_EXCL_LEN             \"AXI_ERRM_EXCL_LEN. The number of bytes to be transferred in an exclusive access burst must be a power of 2. Spec: section 6.2.4 on page 6-4.\"\n  `define ERRM_EXCL_MAX             \"AXI_ERRM_EXCL_MAX. The maximum number of bytes that can be transferred in an exclusive burst is 128. Spec: section 6.2.4 on page 6-4.\"\n  `define ERRM_AWUSER_STABLE        \"AXI_ERRM_AWUSER_STABLE. AWUSER must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_WUSER_STABLE         \"AXI_ERRM_WUSER_STABLE. WUSER must remain stable when WVALID is asserted and WREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRS_BUSER_STABLE         \"AXI_ERRS_BUSER_STABLE. BUSER must remain stable when BVALID is asserted and BREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARUSER_STABLE        \"AXI_ERRM_ARUSER_STABLE. ARUSER must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRS_RUSER_STABLE         \"AXI_ERRS_RUSER_STABLE. RUSER must remain stable when RVALID is asserted and RREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWUSER_X             \"AXI_ERRM_AWUSER_X. When AWVALID is high, a value of X on AWUSER is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_WUSER_X              \"AXI_ERRM_WUSER_X. When WVALID is high, a value of X on WUSER is not permitted.\"\n  `define ERRS_BUSER_X              \"AXI_ERRS_BUSER_X. When BVALID is high, a value of X on BUSER is not permitted.\"\n  `define ERRM_ARUSER_X             \"AXI_ERRM_ARUSER_X. When ARVALID is high, a value of X on ARUSER is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRS_RUSER_X              \"AXI_ERRS_RUSER_X. When RVALID is high, a value of X on RUSER is not permitted.\"\n  `define ERRM_AWUSER_TIEOFF        \"AXI_ERRM_AWUSER_TIEOFF. AWUSER must be stable when AWUSER_WIDTH is set to 0\" \n  `define ERRM_WUSER_TIEOFF         \"AXI_ERRM_WUSER_TIEOFF. WUSER must be stable when WUSER_WIDTH is set to 0\" \n  `define ERRS_BUSER_TIEOFF         \"AXI_ERRS_BUSER_TIEOFF. BUSER must be stable when BUSER_WIDTH is set to 0\" \n  `define ERRM_ARUSER_TIEOFF        \"AXI_ERRM_ARUSER_TIEOFF. ARUSER must be stable when ARUSER_WIDTH is set to 0\" \n  `define ERRS_RUSER_TIEOFF         \"AXI_ERRS_RUSER_TIEOFF. RUSER must be stable when RUSER_WIDTH is set to 0\" \n  `define ERRM_AWID_TIEOFF          \"AXI_ERRM_AWID_TIEOFF. AWID must be stable when ID_WIDTH is set to 0\" \n  `define ERRS_BID_TIEOFF           \"AXI_ERRS_BID_TIEOFF. BID must be stable when ID_WIDTH is set to 0\" \n  `define ERRM_ARID_TIEOFF          \"AXI_ERRM_ARID_TIEOFF. ARID must be stable when ID_WIDTH is set to 0\" \n  `define ERRS_RID_TIEOFF           \"AXI_ERRS_RID_TIEOFF. RID must be stable when ID_WIDTH is set to 0\" \n  `define AUXM_DATA_WIDTH           \"AXI_AUXM_DATA_WIDTH. Parameter DATA_WIDTH must be 32, 64, 128, 256, 512 or 1024\"\n  `define AUXM_ADDR_WIDTH           \"AXI_AUXM_ADDR_WIDTH. Parameter ADDR_WIDTH must be between 32 and 64 bits inclusive\"\n  `define AUXM_EXMON_WIDTH          \"AXI_AUXM_EXMON_WIDTH. Parameter EXMON_WIDTH must be greater than or equal to 1\"\n  `define AUXM_MAXRBURSTS           \"AXI_AUXM_MAXRBURSTS. Parameter MAXRBURSTS must be greater than or equal to 1\"\n  `define AUXM_MAXWBURSTS           \"AXI_AUXM_MAXWBURSTS. Parameter MAXWBURSTS must be greater than or equal to 1\"\n  `define AUXM_RCAM_OVERFLOW        \"AXI_AUXM_RCAM_OVERFLOW. Read CAM overflow, increase Maximum outstanding READ Transactions per ID (MAX_RD_BURSTS) parameter.\"\n  `define AUXM_RCAM_UNDERFLOW       \"AXI_AUXM_RCAM_UNDERFLOW. Read CAM underflow.\"\n  `define AUXM_WCAM_OVERFLOW        \"AXI_AUXM_WCAM_OVERFLOW. Write CAM overflow, increase Maximum outstanding WRITE Transactions per ID (MAX_WR_BURSTS) parameter.\"\n  `define AUXM_WCAM_UNDERFLOW       \"AXI_AUXM_WCAM_UNDERFLOW. Write CAM underflow\"\n  `define AUXM_EXCL_OVERFLOW        \"AXI_AUXM_EXCL_OVERFLOW. Exclusive access monitor overflow, increase EXMON_WIDTH parameter.\"\n  `define RECM_EXCL_PAIR            \"AXI_RECM_EXCL_PAIR. An exclusive write should have an earlier outstanding completed exclusive read with the same ID. Spec: section 6.2.2 on page 6-3.\"\n  `define RECS_AWREADY_MAX_WAIT     \"AXI_RECS_AWREADY_MAX_WAIT. AWREADY should be asserted within MAXWAITS cycles of AWVALID being asserted.\"\n  `define RECS_WREADY_MAX_WAIT      \"AXI_RECS_WREADY_MAX_WAIT. WREADY should be asserted within MAXWAITS cycles of WVALID being asserted.\"\n  `define RECM_BREADY_MAX_WAIT      \"AXI_RECM_BREADY_MAX_WAIT. BREADY should be asserted within MAXWAITS cycles of BVALID being asserted.\"\n  `define RECS_ARREADY_MAX_WAIT     \"AXI_RECS_ARREADY_MAX_WAIT. ARREADY should be asserted within MAXWAITS cycles of ARVALID being asserted.\"\n  `define RECM_RREADY_MAX_WAIT      \"AXI_RECM_RREADY_MAX_WAIT. RREADY should be asserted within MAXWAITS cycles of RVALID being asserted.\"\n  `define RECM_EXCL_MATCH           \"AXI_RECM_EXCL_MATCH. The address, size and length of an exclusive write should be the same as the preceding exclusive read with the same ID. Spec: section 6.2.4 on page 6-4.\"\n  `define ERRS_AXI4LITE_BRESP_EXOKAY   \"AXI4LITE_ERRS_BRESP_EXOKAY. A slave must not give an EXOKAY response on an Axi4Lite interface. Spec: section 14.2.2 on page 14-3.\"\n  `define ERRS_AXI4LITE_RRESP_EXOKAY   \"AXI4LITE_ERRS_RRESP_EXOKAY. A slave must not give an EXOKAY response on an Axi4Lite interface. Spec: section 14.2.2 on page 14-3.\"\n  `define AUXM_AXI4LITE_DATA_WIDTH     \"AXI4LITE_AUXM_DATA_WIDTH. Parameter DATA_WIDTH must be either 32 or 64.\"\n  `define XILINX_AW_SUPPORTS_NARROW_BURST    \"XILINX_AW_SUPPORTS_NARROW_BURST. AW Narrow burst issued from MASTER. Connection has been declared to NOT support narrow bursts.\"\n  `define XILINX_AR_SUPPORTS_NARROW_BURST    \"XILINX_AR_SUPPORTS_NARROW_BURST. AR Narrow burst issued from MASTER. Connection has been declared to NOT support narrow bursts.\"\n  `define XILINX_AW_SUPPORTS_NARROW_CACHE    \"XILINX_AW_SUPPORTS_NARROW_CACHE. AW Non-modifiable burst issued from MASTER. Connection has been declared to NOT support narrow bursts.\"\n  `define XILINX_AR_SUPPORTS_NARROW_CACHE    \"XILINX_AR_SUPPORTS_NARROW_CACHE. AR Non-modifiable burst issued from MASTER. Connection has been declared to NOT support narrow bursts.\"\n  `define XILINX_AW_MAX_BURST                \"XILINX_AW_MAX_BURST. AW MASTER has issued a burst longer than the declared MAXIMUM.\"\n  `define XILINX_AR_MAX_BURST                \"XILINX_AR_MAX_BURST. AR MASTER has issued a burst longer than the declared MAXIMUM.\"\n  `define XILINX_AWREADY_RESET               \"XILINX_AWREADY_RESET. AWREADY must be low for the first clock edge that ARESETn goes high.\"\n  `define XILINX_WREADY_RESET                \"XILINX_WREADY_RESET. WREADY must be low for the first clock edge that ARESETn goes high.\"\n  `define XILINX_BREADY_RESET                \"XILINX_BREADY_RESET. BREADY must be low for the first clock edge that ARESETn goes high.\"\n  `define XILINX_ARREADY_RESET               \"XILINX_ARREADY_RESET. ARREADY must be low for the first clock edge that ARESETn goes high.\"\n  `define XILINX_RREADY_RESET                \"XILINX_RREADY_RESET. RREADY must be low for the first clock edge that ARESETn goes high.\"\n`endif\n\n`define REPORTER_MACRO(ERR_BIT, NET_NAME, MSG_TEXT, SEV_NUM) \\\n  always@(posedge NET_NAME) begin \\\n    if ((SEV_NUM != 0) && (NET_NAME === 1'b1)) begin \\\n      $display(\"%t : %m : BIT(%d) : %s : %s\", $time, ERR_BIT, (SEV_NUM == 0) ? \"INFO\" : (SEV_NUM == 1) ? \"WARNING\" : \"ERROR\" , MSG_TEXT); \\\n      if (SEV_NUM == 3) $stop;\\\n      if (SEV_NUM == 4) $finish;\\\n    end else if ((NET_NAME !== 1'b1) && (NET_NAME !== 1'b0)) begin \\\n      $display(\"%t : %m : BIT(%d) :   ERROR : Invalid state %b\", $time, ERR_BIT, NET_NAME); \\\n    end \\\n  end\n\n`define ASSIGN_MARKED_DEBUG(ERR_BIT, DISPLAY_NETNAME) \\\n  (* mark_debug = \"true\" *) reg DISPLAY_NETNAME;\\\n  always@(posedge aclk) DISPLAY_NETNAME <= pc_status[ERR_BIT];\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_protocol_checker_v1_1_12_reporter #(\n  parameter integer C_PC_MESSAGE_LEVEL             = 2,\n  parameter integer C_PC_STATUS_WIDTH              = 97\n) (\n  input  wire                             aclk,\n  input  wire [C_PC_STATUS_WIDTH-1:0]     pc_status\n);\n\n`ASSIGN_MARKED_DEBUG(00, PC_00_AXI_ERRM_AWADDR_BOUNDARY          )\n`ASSIGN_MARKED_DEBUG(01, PC_01_AXI_ERRM_AWADDR_WRAP_ALIGN        )\n`ASSIGN_MARKED_DEBUG(02, PC_02_AXI_ERRM_AWBURST                  )\n`ASSIGN_MARKED_DEBUG(03, PC_03_AXI_ERRM_AWLEN_LOCK               )\n`ASSIGN_MARKED_DEBUG(04, PC_04_AXI_ERRM_AWCACHE                  )\n`ASSIGN_MARKED_DEBUG(05, PC_05_AXI_ERRM_AWLEN_FIXED              )\n`ASSIGN_MARKED_DEBUG(06, PC_06_AXI_ERRM_AWLEN_WRAP               )\n`ASSIGN_MARKED_DEBUG(07, PC_07_AXI_ERRM_AWSIZE                   )\n`ASSIGN_MARKED_DEBUG(08, PC_08_AXI_ERRM_AWVALID_RESET            )\n`ASSIGN_MARKED_DEBUG(09, PC_09_AXI_ERRM_AWADDR_STABLE            )\n`ASSIGN_MARKED_DEBUG(10, PC_10_AXI_ERRM_AWBURST_STABLE           )\n`ASSIGN_MARKED_DEBUG(11, PC_11_AXI_ERRM_AWCACHE_STABLE           )\n`ASSIGN_MARKED_DEBUG(12, PC_12_AXI_ERRM_AWID_STABLE              )\n`ASSIGN_MARKED_DEBUG(13, PC_13_AXI_ERRM_AWLEN_STABLE             )\n`ASSIGN_MARKED_DEBUG(14, PC_14_AXI_ERRM_AWLOCK_STABLE            )\n`ASSIGN_MARKED_DEBUG(15, PC_15_AXI_ERRM_AWPROT_STABLE            )\n`ASSIGN_MARKED_DEBUG(16, PC_16_AXI_ERRM_AWSIZE_STABLE            )\n`ASSIGN_MARKED_DEBUG(17, PC_17_AXI_ERRM_AWQOS_STABLE             )\n`ASSIGN_MARKED_DEBUG(18, PC_18_AXI_ERRM_AWREGION_STABLE          )\n`ASSIGN_MARKED_DEBUG(19, PC_19_AXI_ERRM_AWVALID_STABLE           )\n`ASSIGN_MARKED_DEBUG(20, PC_20_AXI_RECS_AWREADY_MAX_WAIT         )\n`ASSIGN_MARKED_DEBUG(21, PC_21_AXI_ERRM_WDATA_NUM                )\n`ASSIGN_MARKED_DEBUG(22, PC_22_AXI_ERRM_WSTRB                    )\n`ASSIGN_MARKED_DEBUG(23, PC_23_AXI_ERRM_WVALID_RESET             )\n`ASSIGN_MARKED_DEBUG(24, PC_24_AXI_ERRM_WDATA_STABLE             )\n`ASSIGN_MARKED_DEBUG(25, PC_25_AXI_ERRM_WLAST_STABLE             )\n`ASSIGN_MARKED_DEBUG(26, PC_26_AXI_ERRM_WSTRB_STABLE             )\n`ASSIGN_MARKED_DEBUG(27, PC_27_AXI_ERRM_WVALID_STABLE            )\n`ASSIGN_MARKED_DEBUG(28, PC_28_AXI_RECS_WREADY_MAX_WAIT          )\n`ASSIGN_MARKED_DEBUG(29, PC_29_AXI_ERRS_BRESP_WLAST              )\n`ASSIGN_MARKED_DEBUG(30, PC_30_AXI_ERRS_BRESP_EXOKAY             )\n`ASSIGN_MARKED_DEBUG(31, PC_31_AXI_ERRS_BVALID_RESET             )\n`ASSIGN_MARKED_DEBUG(32, PC_32_AXI_ERRS_BRESP_AW                 )\n`ASSIGN_MARKED_DEBUG(33, PC_33_AXI_ERRS_BID_STABLE               )\n`ASSIGN_MARKED_DEBUG(34, PC_34_AXI_ERRS_BRESP_STABLE             )\n`ASSIGN_MARKED_DEBUG(35, PC_35_AXI_ERRS_BVALID_STABLE            )\n`ASSIGN_MARKED_DEBUG(36, PC_36_AXI_RECM_BREADY_MAX_WAIT          )\n`ASSIGN_MARKED_DEBUG(37, PC_37_AXI_ERRM_ARADDR_BOUNDARY          )\n`ASSIGN_MARKED_DEBUG(38, PC_38_AXI_ERRM_ARADDR_WRAP_ALIGN        )\n`ASSIGN_MARKED_DEBUG(39, PC_39_AXI_ERRM_ARBURST                  )\n`ASSIGN_MARKED_DEBUG(40, PC_40_AXI_ERRM_ARLEN_LOCK               )\n`ASSIGN_MARKED_DEBUG(41, PC_41_AXI_ERRM_ARCACHE                  )\n`ASSIGN_MARKED_DEBUG(42, PC_42_AXI_ERRM_ARLEN_FIXED              )\n`ASSIGN_MARKED_DEBUG(43, PC_43_AXI_ERRM_ARLEN_WRAP               )\n`ASSIGN_MARKED_DEBUG(44, PC_44_AXI_ERRM_ARSIZE                   )\n`ASSIGN_MARKED_DEBUG(45, PC_45_AXI_ERRM_ARVALID_RESET            )\n`ASSIGN_MARKED_DEBUG(46, PC_46_AXI_ERRM_ARADDR_STABLE            )\n`ASSIGN_MARKED_DEBUG(47, PC_47_AXI_ERRM_ARBURST_STABLE           )\n`ASSIGN_MARKED_DEBUG(48, PC_48_AXI_ERRM_ARCACHE_STABLE           )\n`ASSIGN_MARKED_DEBUG(49, PC_49_AXI_ERRM_ARID_STABLE              )\n`ASSIGN_MARKED_DEBUG(50, PC_50_AXI_ERRM_ARLEN_STABLE             )\n`ASSIGN_MARKED_DEBUG(51, PC_51_AXI_ERRM_ARLOCK_STABLE            )\n`ASSIGN_MARKED_DEBUG(52, PC_52_AXI_ERRM_ARPROT_STABLE            )\n`ASSIGN_MARKED_DEBUG(53, PC_53_AXI_ERRM_ARSIZE_STABLE            )\n`ASSIGN_MARKED_DEBUG(54, PC_54_AXI_ERRM_ARQOS_STABLE             )\n`ASSIGN_MARKED_DEBUG(55, PC_55_AXI_ERRM_ARREGION_STABLE          )\n`ASSIGN_MARKED_DEBUG(56, PC_56_AXI_ERRM_ARVALID_STABLE           )\n`ASSIGN_MARKED_DEBUG(57, PC_57_AXI_RECS_ARREADY_MAX_WAIT         )\n`ASSIGN_MARKED_DEBUG(58, PC_58_AXI_ERRS_RDATA_NUM                )\n`ASSIGN_MARKED_DEBUG(59, PC_59_AXI_ERRS_RID                      )\n`ASSIGN_MARKED_DEBUG(60, PC_60_AXI_ERRS_RRESP_EXOKAY             )\n`ASSIGN_MARKED_DEBUG(61, PC_61_AXI_ERRS_RVALID_RESET             )\n`ASSIGN_MARKED_DEBUG(62, PC_62_AXI_ERRS_RDATA_STABLE             )\n`ASSIGN_MARKED_DEBUG(63, PC_63_AXI_ERRS_RID_STABLE               )\n`ASSIGN_MARKED_DEBUG(64, PC_64_AXI_ERRS_RLAST_STABLE             )\n`ASSIGN_MARKED_DEBUG(65, PC_65_AXI_ERRS_RRESP_STABLE             )\n`ASSIGN_MARKED_DEBUG(66, PC_66_AXI_ERRS_RVALID_STABLE            )\n`ASSIGN_MARKED_DEBUG(67, PC_67_AXI_RECM_RREADY_MAX_WAIT          )\n`ASSIGN_MARKED_DEBUG(68, PC_68_AXI_ERRM_EXCL_ALIGN               )\n`ASSIGN_MARKED_DEBUG(69, PC_69_AXI_ERRM_EXCL_LEN                 )\n`ASSIGN_MARKED_DEBUG(70, PC_70_AXI_RECM_EXCL_MATCH               )\n`ASSIGN_MARKED_DEBUG(71, PC_71_AXI_ERRM_EXCL_MAX                 )\n`ASSIGN_MARKED_DEBUG(72, PC_72_AXI_RECM_EXCL_PAIR                )\n`ASSIGN_MARKED_DEBUG(73, PC_73_AXI_ERRM_AWUSER_STABLE            )\n`ASSIGN_MARKED_DEBUG(74, PC_74_AXI_ERRM_WUSER_STABLE             )\n`ASSIGN_MARKED_DEBUG(75, PC_75_AXI_ERRS_BUSER_STABLE             )\n`ASSIGN_MARKED_DEBUG(76, PC_76_AXI_ERRM_ARUSER_STABLE            )\n`ASSIGN_MARKED_DEBUG(77, PC_77_AXI_ERRS_RUSER_STABLE             )\n`ASSIGN_MARKED_DEBUG(78, PC_78_AXI_AUXM_RCAM_OVERFLOW            )\n`ASSIGN_MARKED_DEBUG(79, PC_79_AXI_AUXM_RCAM_UNDERFLOW           )\n`ASSIGN_MARKED_DEBUG(80, PC_80_AXI_AUXM_WCAM_OVERFLOW            )\n`ASSIGN_MARKED_DEBUG(81, PC_81_AXI_AUXM_WCAM_UNDERFLOW           )\n`ASSIGN_MARKED_DEBUG(82, PC_82_AXI_AUXM_EXCL_OVERFLOW            )\n`ASSIGN_MARKED_DEBUG(83, PC_83_AXI4LITE_ERRS_BRESP_EXOKAY        )\n`ASSIGN_MARKED_DEBUG(84, PC_84_AXI4LITE_ERRS_RRESP_EXOKAY        )\n`ASSIGN_MARKED_DEBUG(85, PC_85_AXI4LITE_AUXM_DATA_WIDTH          )\n`ASSIGN_MARKED_DEBUG(86, PC_86_XILINX_AW_SUPPORTS_NARROW_BURST   )\n`ASSIGN_MARKED_DEBUG(87, PC_87_XILINX_AR_SUPPORTS_NARROW_BURST   )\n`ASSIGN_MARKED_DEBUG(88, PC_88_XILINX_AW_SUPPORTS_NARROW_CACHE   )\n`ASSIGN_MARKED_DEBUG(89, PC_89_XILINX_AR_SUPPORTS_NARROW_CACHE   )\n`ASSIGN_MARKED_DEBUG(90, PC_90_XILINX_AW_MAX_BURST               )\n`ASSIGN_MARKED_DEBUG(91, PC_91_XILINX_AR_MAX_BURST               )\n`ASSIGN_MARKED_DEBUG(92, PC_92_XILINX_AWREADY_RESET              )\n`ASSIGN_MARKED_DEBUG(93, PC_93_XILINX_WREADY_RESET               )\n`ASSIGN_MARKED_DEBUG(94, PC_94_XILINX_BREADY_RESET               )\n`ASSIGN_MARKED_DEBUG(95, PC_95_XILINX_ARREADY_RESET              )\n`ASSIGN_MARKED_DEBUG(96, PC_96_XILINX_RREADY_RESET               )\n\n// synthesis translate_off\n`REPORTER_MACRO(00, PC_00_AXI_ERRM_AWADDR_BOUNDARY          , `ERRM_AWADDR_BOUNDARY          , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(01, PC_01_AXI_ERRM_AWADDR_WRAP_ALIGN        , `ERRM_AWADDR_WRAP_ALIGN        , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(02, PC_02_AXI_ERRM_AWBURST                  , `ERRM_AWBURST                  , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(03, PC_03_AXI_ERRM_AWLEN_LOCK               , `ERRM_AWLEN_LOCK               , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(04, PC_04_AXI_ERRM_AWCACHE                  , `ERRM_AWCACHE                  , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(05, PC_05_AXI_ERRM_AWLEN_FIXED              , `ERRM_AWLEN_FIXED              , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(06, PC_06_AXI_ERRM_AWLEN_WRAP               , `ERRM_AWLEN_WRAP               , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(07, PC_07_AXI_ERRM_AWSIZE                   , `ERRM_AWSIZE                   , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(08, PC_08_AXI_ERRM_AWVALID_RESET            , `ERRM_AWVALID_RESET            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(09, PC_09_AXI_ERRM_AWADDR_STABLE            , `ERRM_AWADDR_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(10, PC_10_AXI_ERRM_AWBURST_STABLE           , `ERRM_AWBURST_STABLE           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(11, PC_11_AXI_ERRM_AWCACHE_STABLE           , `ERRM_AWCACHE_STABLE           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(12, PC_12_AXI_ERRM_AWID_STABLE              , `ERRM_AWID_STABLE              , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(13, PC_13_AXI_ERRM_AWLEN_STABLE             , `ERRM_AWLEN_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(14, PC_14_AXI_ERRM_AWLOCK_STABLE            , `ERRM_AWLOCK_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(15, PC_15_AXI_ERRM_AWPROT_STABLE            , `ERRM_AWPROT_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(16, PC_16_AXI_ERRM_AWSIZE_STABLE            , `ERRM_AWSIZE_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(17, PC_17_AXI_ERRM_AWQOS_STABLE             , `ERRM_AWQOS_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(18, PC_18_AXI_ERRM_AWREGION_STABLE          , `ERRM_AWREGION_STABLE          , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(19, PC_19_AXI_ERRM_AWVALID_STABLE           , `ERRM_AWVALID_STABLE           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(20, PC_20_AXI_RECS_AWREADY_MAX_WAIT         , `RECS_AWREADY_MAX_WAIT         , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(21, PC_21_AXI_ERRM_WDATA_NUM                , `ERRM_WDATA_NUM                , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(22, PC_22_AXI_ERRM_WSTRB                    , `ERRM_WSTRB                    , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(23, PC_23_AXI_ERRM_WVALID_RESET             , `ERRM_WVALID_RESET             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(24, PC_24_AXI_ERRM_WDATA_STABLE             , `ERRM_WDATA_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(25, PC_25_AXI_ERRM_WLAST_STABLE             , `ERRM_WLAST_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(26, PC_26_AXI_ERRM_WSTRB_STABLE             , `ERRM_WSTRB_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(27, PC_27_AXI_ERRM_WVALID_STABLE            , `ERRM_WVALID_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(28, PC_28_AXI_RECS_WREADY_MAX_WAIT          , `RECS_WREADY_MAX_WAIT          , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(29, PC_29_AXI_ERRS_BRESP_WLAST              , `ERRS_BRESP_WLAST              , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(30, PC_30_AXI_ERRS_BRESP_EXOKAY             , `ERRS_BRESP_EXOKAY             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(31, PC_31_AXI_ERRS_BVALID_RESET             , `ERRS_BVALID_RESET             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(32, PC_32_AXI_ERRS_BRESP_AW                 , `ERRS_BRESP_AW                 , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(33, PC_33_AXI_ERRS_BID_STABLE               , `ERRS_BID_STABLE               , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(34, PC_34_AXI_ERRS_BRESP_STABLE             , `ERRS_BRESP_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(35, PC_35_AXI_ERRS_BVALID_STABLE            , `ERRS_BVALID_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(36, PC_36_AXI_RECM_BREADY_MAX_WAIT          , `RECM_BREADY_MAX_WAIT          , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(37, PC_37_AXI_ERRM_ARADDR_BOUNDARY          , `ERRM_ARADDR_BOUNDARY          , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(38, PC_38_AXI_ERRM_ARADDR_WRAP_ALIGN        , `ERRM_ARADDR_WRAP_ALIGN        , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(39, PC_39_AXI_ERRM_ARBURST                  , `ERRM_ARBURST                  , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(40, PC_40_AXI_ERRM_ARLEN_LOCK               , `ERRM_ARLEN_LOCK               , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(41, PC_41_AXI_ERRM_ARCACHE                  , `ERRM_ARCACHE                  , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(42, PC_42_AXI_ERRM_ARLEN_FIXED              , `ERRM_ARLEN_FIXED              , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(43, PC_43_AXI_ERRM_ARLEN_WRAP               , `ERRM_ARLEN_WRAP               , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(44, PC_44_AXI_ERRM_ARSIZE                   , `ERRM_ARSIZE                   , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(45, PC_45_AXI_ERRM_ARVALID_RESET            , `ERRM_ARVALID_RESET            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(46, PC_46_AXI_ERRM_ARADDR_STABLE            , `ERRM_ARADDR_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(47, PC_47_AXI_ERRM_ARBURST_STABLE           , `ERRM_ARBURST_STABLE           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(48, PC_48_AXI_ERRM_ARCACHE_STABLE           , `ERRM_ARCACHE_STABLE           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(49, PC_49_AXI_ERRM_ARID_STABLE              , `ERRM_ARID_STABLE              , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(50, PC_50_AXI_ERRM_ARLEN_STABLE             , `ERRM_ARLEN_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(51, PC_51_AXI_ERRM_ARLOCK_STABLE            , `ERRM_ARLOCK_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(52, PC_52_AXI_ERRM_ARPROT_STABLE            , `ERRM_ARPROT_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(53, PC_53_AXI_ERRM_ARSIZE_STABLE            , `ERRM_ARSIZE_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(54, PC_54_AXI_ERRM_ARQOS_STABLE             , `ERRM_ARQOS_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(55, PC_55_AXI_ERRM_ARREGION_STABLE          , `ERRM_ARREGION_STABLE          , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(56, PC_56_AXI_ERRM_ARVALID_STABLE           , `ERRM_ARVALID_STABLE           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(57, PC_57_AXI_RECS_ARREADY_MAX_WAIT         , `RECS_ARREADY_MAX_WAIT         , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(58, PC_58_AXI_ERRS_RDATA_NUM                , `ERRS_RDATA_NUM                , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(59, PC_59_AXI_ERRS_RID                      , `ERRS_RID                      , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(60, PC_60_AXI_ERRS_RRESP_EXOKAY             , `ERRS_RRESP_EXOKAY             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(61, PC_61_AXI_ERRS_RVALID_RESET             , `ERRS_RVALID_RESET             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(62, PC_62_AXI_ERRS_RDATA_STABLE             , `ERRS_RDATA_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(63, PC_63_AXI_ERRS_RID_STABLE               , `ERRS_RID_STABLE               , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(64, PC_64_AXI_ERRS_RLAST_STABLE             , `ERRS_RLAST_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(65, PC_65_AXI_ERRS_RRESP_STABLE             , `ERRS_RRESP_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(66, PC_66_AXI_ERRS_RVALID_STABLE            , `ERRS_RVALID_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(67, PC_67_AXI_RECM_RREADY_MAX_WAIT          , `RECM_RREADY_MAX_WAIT          , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(68, PC_68_AXI_ERRM_EXCL_ALIGN               , `ERRM_EXCL_ALIGN               , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(69, PC_69_AXI_ERRM_EXCL_LEN                 , `ERRM_EXCL_LEN                 , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(70, PC_70_AXI_RECM_EXCL_MATCH               , `RECM_EXCL_MATCH               , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(71, PC_71_AXI_ERRM_EXCL_MAX                 , `ERRM_EXCL_MAX                 , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(72, PC_72_AXI_RECM_EXCL_PAIR                , `RECM_EXCL_PAIR                , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(73, PC_73_AXI_ERRM_AWUSER_STABLE            , `ERRM_AWUSER_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(74, PC_74_AXI_ERRM_WUSER_STABLE             , `ERRM_WUSER_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(75, PC_75_AXI_ERRS_BUSER_STABLE             , `ERRS_BUSER_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(76, PC_76_AXI_ERRM_ARUSER_STABLE            , `ERRM_ARUSER_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(77, PC_77_AXI_ERRS_RUSER_STABLE             , `ERRS_RUSER_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(78, PC_78_AXI_AUXM_RCAM_OVERFLOW            , `AUXM_RCAM_OVERFLOW            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(79, PC_79_AXI_AUXM_RCAM_UNDERFLOW           , `AUXM_RCAM_UNDERFLOW           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(80, PC_80_AXI_AUXM_WCAM_OVERFLOW            , `AUXM_WCAM_OVERFLOW            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(81, PC_81_AXI_AUXM_WCAM_UNDERFLOW           , `AUXM_WCAM_UNDERFLOW           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(82, PC_82_AXI_AUXM_EXCL_OVERFLOW            , `AUXM_EXCL_OVERFLOW            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(83, PC_83_AXI4LITE_ERRS_BRESP_EXOKAY        , `ERRS_AXI4LITE_BRESP_EXOKAY    , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(84, PC_84_AXI4LITE_ERRS_RRESP_EXOKAY        , `ERRS_AXI4LITE_RRESP_EXOKAY    , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(85, PC_85_AXI4LITE_AUXM_DATA_WIDTH          , `AUXM_AXI4LITE_DATA_WIDTH      , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(86, PC_86_XILINX_AW_SUPPORTS_NARROW_BURST   , `XILINX_AW_SUPPORTS_NARROW_BURST, C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(87, PC_87_XILINX_AR_SUPPORTS_NARROW_BURST   , `XILINX_AR_SUPPORTS_NARROW_BURST, C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(88, PC_88_XILINX_AW_SUPPORTS_NARROW_CACHE   , `XILINX_AW_SUPPORTS_NARROW_CACHE, C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(89, PC_89_XILINX_AR_SUPPORTS_NARROW_CACHE   , `XILINX_AR_SUPPORTS_NARROW_CACHE, C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(90, PC_90_XILINX_AW_MAX_BURST               , `XILINX_AW_MAX_BURST            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(91, PC_91_XILINX_AR_MAX_BURST               , `XILINX_AR_MAX_BURST            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(92, PC_92_XILINX_AWREADY_RESET              , `XILINX_AWREADY_RESET           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(93, PC_93_XILINX_WREADY_RESET               , `XILINX_WREADY_RESET            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(94, PC_94_XILINX_BREADY_RESET               , `XILINX_BREADY_RESET            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(95, PC_95_XILINX_ARREADY_RESET              , `XILINX_ARREADY_RESET           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(96, PC_96_XILINX_RREADY_RESET               , `XILINX_RREADY_RESET            , C_PC_MESSAGE_LEVEL)\n\n// synthesis translate_on\n\nendmodule\n`ifdef AXI4PC_MESSAGES\n  `undef AXI4PC_MESSAGES\n  `undef ERRM_AWADDR_BOUNDARY      \n  `undef ERRM_AWADDR_WRAP_ALIGN    \n  `undef ERRM_AWBURST              \n  `undef ERRM_AWCACHE              \n  `undef ERRM_ARCACHE              \n  `undef ERRM_AWLEN_WRAP           \n  `undef ERRM_AWSIZE               \n  `undef ERRM_AWVALID_RESET        \n  `undef ERRM_AWADDR_STABLE        \n  `undef ERRM_AWBURST_STABLE       \n  `undef ERRM_AWCACHE_STABLE       \n  `undef ERRM_AWID_STABLE          \n  `undef ERRM_AWLEN_STABLE         \n  `undef ERRM_AWLOCK_STABLE        \n  `undef ERRM_AWPROT_STABLE        \n  `undef ERRM_AWSIZE_STABLE        \n  `undef ERRM_AWQOS_STABLE         \n  `undef ERRM_AWREGION_STABLE      \n  `undef ERRM_AWVALID_STABLE       \n  `undef ERRM_AWADDR_X             \n  `undef ERRM_AWBURST_X            \n  `undef ERRM_AWCACHE_X            \n  `undef ERRM_AWID_X               \n  `undef ERRM_AWLEN_X              \n  `undef ERRM_AWLOCK_X             \n  `undef ERRM_AWPROT_X             \n  `undef ERRM_AWSIZE_X             \n  `undef ERRM_AWQOS_X              \n  `undef ERRM_AWREGION_X           \n  `undef ERRM_AWVALID_X            \n  `undef ERRS_AWREADY_X            \n  `undef ERRM_WDATA_NUM            \n  `undef ERRM_WSTRB                \n  `undef ERRM_WVALID_RESET         \n  `undef ERRM_WDATA_STABLE         \n  `undef ERRM_WLAST_STABLE         \n  `undef ERRM_WSTRB_STABLE         \n  `undef ERRM_WVALID_STABLE        \n  `undef ERRM_WDATA_X              \n  `undef ERRM_WLAST_X              \n  `undef ERRM_WSTRB_X              \n  `undef ERRM_WVALID_X             \n  `undef ERRS_WREADY_X             \n  `undef ERRS_BRESP_WLAST          \n  `undef ERRS_BRESP_ALL_DONE_EOS   \n  `undef ERRS_BRESP_EXOKAY         \n  `undef ERRS_BVALID_RESET         \n  `undef ERRS_BRESP_AW             \n  `undef ERRS_BID_STABLE           \n  `undef ERRS_BRESP_STABLE         \n  `undef ERRS_BVALID_STABLE        \n  `undef ERRM_BREADY_X             \n  `undef ERRS_BID_X                \n  `undef ERRS_BRESP_X              \n  `undef ERRS_BVALID_X             \n  `undef ERRM_ARADDR_BOUNDARY      \n  `undef ERRM_ARADDR_WRAP_ALIGN    \n  `undef ERRM_ARBURST              \n  `undef ERRM_ARLEN_FIXED          \n  `undef ERRM_AWLEN_FIXED          \n  `undef ERRM_AWLEN_LOCK           \n  `undef ERRM_ARLEN_LOCK           \n  `undef ERRM_ARLEN_WRAP           \n  `undef ERRM_ARSIZE               \n  `undef ERRM_ARVALID_RESET        \n  `undef ERRM_ARADDR_STABLE        \n  `undef ERRM_ARBURST_STABLE       \n  `undef ERRM_ARCACHE_STABLE       \n  `undef ERRM_ARID_STABLE          \n  `undef ERRM_ARLEN_STABLE         \n  `undef ERRM_ARLOCK_STABLE        \n  `undef ERRM_ARPROT_STABLE        \n  `undef ERRM_ARSIZE_STABLE        \n  `undef ERRM_ARQOS_STABLE         \n  `undef ERRM_ARREGION_STABLE      \n  `undef ERRM_ARVALID_STABLE       \n  `undef ERRM_ARADDR_X             \n  `undef ERRM_ARBURST_X            \n  `undef ERRM_ARCACHE_X            \n  `undef ERRM_ARID_X               \n  `undef ERRM_ARLEN_X              \n  `undef ERRM_ARLOCK_X             \n  `undef ERRM_ARPROT_X             \n  `undef ERRM_ARSIZE_X             \n  `undef ERRM_ARQOS_X              \n  `undef ERRM_ARREGION_X           \n  `undef ERRM_ARVALID_X            \n  `undef ERRS_ARREADY_X            \n  `undef ERRS_RDATA_NUM            \n  `undef ERRS_RLAST_ALL_DONE_EOS   \n  `undef ERRS_RID                  \n  `undef ERRS_RRESP_EXOKAY         \n  `undef ERRS_RVALID_RESET         \n  `undef ERRS_RDATA_STABLE         \n  `undef ERRS_RID_STABLE           \n  `undef ERRS_RLAST_STABLE         \n  `undef ERRS_RRESP_STABLE         \n  `undef ERRS_RVALID_STABLE        \n  `undef ERRS_RDATA_X              \n  `undef ERRM_RREADY_X             \n  `undef ERRS_RID_X                \n  `undef ERRS_RLAST_X              \n  `undef ERRS_RRESP_X              \n  `undef ERRS_RVALID_X             \n  `undef ERRL_CSYSACK_FALL         \n  `undef ERRL_CSYSACK_RISE         \n  `undef ERRL_CSYSREQ_FALL         \n  `undef ERRL_CSYSREQ_RISE         \n  `undef ERRL_CACTIVE_X            \n  `undef ERRL_CSYSACK_X            \n  `undef ERRL_CSYSREQ_X            \n  `undef ERRM_EXCL_ALIGN           \n  `undef ERRM_EXCL_LEN             \n  `undef ERRM_EXCL_MAX             \n  `undef ERRM_AWUSER_STABLE        \n  `undef ERRM_WUSER_STABLE         \n  `undef ERRS_BUSER_STABLE         \n  `undef ERRM_ARUSER_STABLE        \n  `undef ERRS_RUSER_STABLE         \n  `undef ERRM_AWUSER_X             \n  `undef ERRM_WUSER_X              \n  `undef ERRS_BUSER_X              \n  `undef ERRM_ARUSER_X             \n  `undef ERRS_RUSER_X              \n  `undef ERRM_AWUSER_TIEOFF\n  `undef ERRM_WUSER_TIEOFF\n  `undef ERRS_BUSER_TIEOFF\n  `undef ERRM_ARUSER_TIEOFF\n  `undef ERRS_RUSER_TIEOFF\n  `undef ERRM_AWID_TIEOFF \n  `undef ERRS_BID_TIEOFF \n  `undef ERRM_ARID_TIEOFF \n  `undef ERRS_RID_TIEOFF \n  `undef AUXM_DATA_WIDTH           \n  `undef AUXM_ADDR_WIDTH           \n  `undef AUXM_EXMON_WIDTH          \n  `undef AUXM_MAXRBURSTS           \n  `undef AUXM_MAXWBURSTS           \n  `undef AUXM_RCAM_OVERFLOW        \n  `undef AUXM_RCAM_UNDERFLOW       \n  `undef AUXM_WCAM_OVERFLOW        \n  `undef AUXM_WCAM_UNDERFLOW       \n  `undef AUXM_EXCL_OVERFLOW        \n  `undef RECM_EXCL_PAIR            \n  `undef RECS_AWREADY_MAX_WAIT     \n  `undef RECS_WREADY_MAX_WAIT      \n  `undef RECM_BREADY_MAX_WAIT      \n  `undef RECS_ARREADY_MAX_WAIT     \n  `undef RECM_RREADY_MAX_WAIT      \n  `undef RECM_EXCL_MATCH           \n  `undef ERRS_AXI4LITE_BRESP_EXOKAY \n  `undef ERRS_AXI4LITE_RRESP_EXOKAY \n  `undef AUXM_AXI4LITE_DATA_WIDTH\n  `undef XILINX_AW_SUPPORTS_NARROW_BURST \n  `undef XILINX_AR_SUPPORTS_NARROW_BURST \n  `undef XILINX_AW_SUPPORTS_NARROW_CACHE \n  `undef XILINX_AR_SUPPORTS_NARROW_CACHE \n  `undef XILINX_AW_MAX_BURST\n  `undef XILINX_AR_MAX_BURST\n  `undef XILINX_AWREADY_RESET\n  `undef XILINX_WREADY_RESET \n  `undef XILINX_BREADY_RESET \n  `undef XILINX_ARREADY_RESET\n  `undef XILINX_RREADY_RESET \n`endif\n\n`default_nettype wire\n\n\n// (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n module axi_protocol_checker_v1_1_12_top #(\n  //Core Level Generics\n  parameter integer C_AXI_PROTOCOL                 = 0,\n  parameter integer C_AXI_ID_WIDTH                 = 1,\n  parameter integer C_AXI_DATA_WIDTH               = 32,\n  parameter integer C_AXI_ADDR_WIDTH               = 32,\n  parameter integer C_AXI_AWUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH             = 1,\n  parameter integer C_AXI_WUSER_WIDTH              = 1,\n  parameter integer C_AXI_RUSER_WIDTH              = 1,\n  parameter integer C_AXI_BUSER_WIDTH              = 1,\n  \n  parameter integer C_PC_MAXRBURSTS                = 8,\n  parameter integer C_PC_MAXWBURSTS                = 8,\n  parameter integer C_PC_EXMON_WIDTH               = 0,\n  parameter integer C_PC_AW_MAXWAITS               = 0,\n  parameter integer C_PC_AR_MAXWAITS               = 0,\n  parameter integer C_PC_W_MAXWAITS                = 0,\n  parameter integer C_PC_R_MAXWAITS                = 0,\n  parameter integer C_PC_B_MAXWAITS                = 0,\n  parameter integer C_PC_MESSAGE_LEVEL             = 2,\n  parameter integer C_PC_SUPPORTS_NARROW_BURST     = 1,\n  parameter integer C_PC_MAX_BURST_LENGTH          = 256,\n  parameter integer C_PC_HAS_SYSTEM_RESET          = 0,\n  parameter integer C_PC_STATUS_WIDTH              = 97\n) (\n  //Protocol Checker Specific Signals\n  output wire [C_PC_STATUS_WIDTH - 1:0]               pc_status,\n  output wire                                         pc_asserted,\n  \n  input wire                                          system_resetn,\n  //AXI CLK\n  input wire                                          aclk,\n  //AXI Reset\n  input wire                                          aresetn,\n  //AXI Write Address\n  input wire [C_AXI_ID_WIDTH-1:0]                     pc_axi_awid,\n  input wire [C_AXI_ADDR_WIDTH-1:0]                   pc_axi_awaddr,\n  input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]    pc_axi_awlen,\n  input wire [2:0]                                    pc_axi_awsize,\n  input wire [1:0]                                    pc_axi_awburst,\n  input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]    pc_axi_awlock,\n  input wire [3:0]                                    pc_axi_awcache,\n  input wire [2:0]                                    pc_axi_awprot,\n  input wire [3:0]                                    pc_axi_awqos,\n  input wire [3:0]                                    pc_axi_awregion,\n  input wire [C_AXI_AWUSER_WIDTH-1:0]                 pc_axi_awuser,\n  input wire                                          pc_axi_awvalid,\n  input wire                                          pc_axi_awready,\n  //AXI Write Data\n  input wire [C_AXI_ID_WIDTH-1:0]                     pc_axi_wid,\n  input wire                                          pc_axi_wlast,\n  input wire [C_AXI_DATA_WIDTH-1:0]                   pc_axi_wdata,\n  input wire [C_AXI_DATA_WIDTH/8-1:0]                 pc_axi_wstrb,\n  input wire [C_AXI_WUSER_WIDTH-1:0]                  pc_axi_wuser,\n  input wire                                          pc_axi_wvalid,\n  input wire                                          pc_axi_wready,\n  //AXI Write Response\n  input wire [C_AXI_ID_WIDTH-1:0]                     pc_axi_bid,\n  input wire [1:0]                                    pc_axi_bresp,\n  input wire [C_AXI_BUSER_WIDTH-1:0]                  pc_axi_buser,\n  input wire                                          pc_axi_bvalid,\n  input wire                                          pc_axi_bready,\n  //AXI Read Address\n  input wire [C_AXI_ID_WIDTH-1:0]                     pc_axi_arid,\n  input wire [C_AXI_ADDR_WIDTH-1:0]                   pc_axi_araddr,\n  input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]    pc_axi_arlen,\n  input wire [2:0]                                    pc_axi_arsize,\n  input wire [1:0]                                    pc_axi_arburst,\n  input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]    pc_axi_arlock,\n  input wire [3:0]                                    pc_axi_arcache,\n  input wire [2:0]                                    pc_axi_arprot,\n  input wire [3:0]                                    pc_axi_arqos,\n  input wire [3:0]                                    pc_axi_arregion,\n  input wire [C_AXI_ARUSER_WIDTH-1:0]                 pc_axi_aruser,\n  input wire                                          pc_axi_arvalid,\n  input wire                                          pc_axi_arready,\n  //AXI Read Data\n  input wire [C_AXI_ID_WIDTH-1:0]                     pc_axi_rid,\n  input wire                                          pc_axi_rlast,\n  input wire [C_AXI_DATA_WIDTH-1:0]                   pc_axi_rdata,\n  input wire [1:0]                                    pc_axi_rresp,\n  input wire [C_AXI_RUSER_WIDTH-1:0]                  pc_axi_ruser,\n  input wire                                          pc_axi_rvalid,\n  input wire                                          pc_axi_rready\n);\n\nlocalparam LP_AXI_SIZE = (C_AXI_DATA_WIDTH == 32) ? 3'b010 : 3'b011;\n\nreg                           resetn_q;\nreg  [C_AXI_ID_WIDTH-1:0]     awid_q;\nreg  [C_AXI_ADDR_WIDTH-1:0]   awaddr_q;\nreg  [7:0]                    awlen_q;\nreg  [2:0]                    awsize_q;\nreg  [1:0]                    awburst_q;\nreg  [0:0]                    awlock_q;\nreg  [3:0]                    awcache_q;\nreg  [2:0]                    awprot_q;\nreg  [3:0]                    awqos_q;\nreg  [3:0]                    awregion_q;\nreg  [C_AXI_AWUSER_WIDTH-1:0] awuser_q;\nreg                           awvalid_q;\nreg                           awready_q;\nreg                           wlast_q;\nreg  [C_AXI_DATA_WIDTH-1:0]   wdata_q;\nreg  [C_AXI_DATA_WIDTH/8-1:0] wstrb_q;\nreg  [C_AXI_WUSER_WIDTH-1:0]  wuser_q;\nreg                           wvalid_q;\nreg                           wready_q;\nreg  [C_AXI_ID_WIDTH-1:0]     bid_q;\nreg  [1:0]                    bresp_q;\nreg  [C_AXI_BUSER_WIDTH-1:0]  buser_q;\nreg                           bvalid_q;\nreg                           bready_q;\nreg  [C_AXI_ID_WIDTH-1:0]     arid_q;\nreg  [C_AXI_ADDR_WIDTH-1:0]   araddr_q;\nreg  [7:0]                    arlen_q;\nreg  [2:0]                    arsize_q;\nreg  [1:0]                    arburst_q;\nreg  [0:0]                    arlock_q;\nreg  [3:0]                    arcache_q;\nreg  [2:0]                    arprot_q;\nreg  [3:0]                    arqos_q;\nreg  [3:0]                    arregion_q;\nreg  [C_AXI_ARUSER_WIDTH-1:0] aruser_q;\nreg                           arvalid_q;\nreg                           arready_q;\nreg  [C_AXI_ID_WIDTH-1:0]     rid_q;\nreg                           rlast_q;\nreg  [C_AXI_DATA_WIDTH-1:0]   rdata_q;\nreg  [1:0]                    rresp_q;\nreg  [C_AXI_RUSER_WIDTH-1:0]  ruser_q;\nreg                           rvalid_q;\nreg                           rready_q;\nreg                           pc_asserted_i;\n\nalways @(posedge aclk) begin\n  resetn_q    <= aresetn;\n  awid_q      <= (C_AXI_PROTOCOL != 2) ? pc_axi_awid     : {C_AXI_ID_WIDTH{1'b0}};\n  awaddr_q    <= pc_axi_awaddr;\n  awlen_q     <= (C_AXI_PROTOCOL == 0) ? pc_axi_awlen : (C_AXI_PROTOCOL == 1) ? (pc_axi_awlen | 8'h00) : 8'h00;\n  awsize_q    <= (C_AXI_PROTOCOL != 2) ? pc_axi_awsize   : LP_AXI_SIZE;\n  awburst_q   <= (C_AXI_PROTOCOL != 2) ? pc_axi_awburst  : 2'b01;\n  awlock_q    <= (C_AXI_PROTOCOL != 2) ? pc_axi_awlock[0] : 1'b0;\n  awcache_q   <= (C_AXI_PROTOCOL != 2) ? pc_axi_awcache  : 4'h0;\n  awprot_q    <= pc_axi_awprot;\n  awqos_q     <= (C_AXI_PROTOCOL != 2) ? pc_axi_awqos    : 4'h0;\n  awregion_q  <= (C_AXI_PROTOCOL != 2) ? pc_axi_awregion : 4'h0;\n  awuser_q    <= (C_AXI_PROTOCOL != 2) ? pc_axi_awuser   : {C_AXI_AWUSER_WIDTH{1'b0}};\n  awvalid_q   <= pc_axi_awvalid;\n  awready_q   <= pc_axi_awready;\n  wlast_q     <= (C_AXI_PROTOCOL != 2) ? pc_axi_wlast    : 1'b1;\n  wdata_q     <= pc_axi_wdata;\n  wstrb_q     <= pc_axi_wstrb;\n  wuser_q     <= (C_AXI_PROTOCOL != 2) ? pc_axi_wuser    : {C_AXI_WUSER_WIDTH{1'b0}};\n  wvalid_q    <= pc_axi_wvalid;\n  wready_q    <= pc_axi_wready;\n  bid_q       <= (C_AXI_PROTOCOL != 2) ? pc_axi_bid      : {C_AXI_ID_WIDTH{1'b0}};\n  bresp_q     <= pc_axi_bresp;\n  buser_q     <= (C_AXI_PROTOCOL != 2) ? pc_axi_buser    : {C_AXI_BUSER_WIDTH{1'b0}};\n  bvalid_q    <= pc_axi_bvalid;\n  bready_q    <= pc_axi_bready;\n  arid_q      <= (C_AXI_PROTOCOL != 2) ? pc_axi_arid     : {C_AXI_ID_WIDTH{1'b0}};\n  araddr_q    <= pc_axi_araddr;\n  arlen_q     <= (C_AXI_PROTOCOL == 0) ? pc_axi_arlen : (C_AXI_PROTOCOL == 1) ? (pc_axi_arlen| 8'h00) : 8'h00;\n  arsize_q    <= (C_AXI_PROTOCOL != 2) ? pc_axi_arsize   : LP_AXI_SIZE;\n  arburst_q   <= (C_AXI_PROTOCOL != 2) ? pc_axi_arburst  : 2'b01;\n  arlock_q    <= (C_AXI_PROTOCOL != 2) ? pc_axi_arlock[0] : 1'b0;\n  arcache_q   <= (C_AXI_PROTOCOL != 2) ? pc_axi_arcache  : 4'h0;\n  arprot_q    <= pc_axi_arprot;\n  arqos_q     <= (C_AXI_PROTOCOL != 2) ? pc_axi_arqos    : 4'h0;\n  arregion_q  <= (C_AXI_PROTOCOL != 2) ? pc_axi_arregion : 4'h0;\n  aruser_q    <= (C_AXI_PROTOCOL != 2) ? pc_axi_aruser   : {C_AXI_ARUSER_WIDTH{1'b0}};\n  arvalid_q   <= pc_axi_arvalid;\n  arready_q   <= pc_axi_arready;\n  rid_q       <= (C_AXI_PROTOCOL != 2) ? pc_axi_rid      : {C_AXI_ID_WIDTH{1'b0}};\n  rlast_q     <= (C_AXI_PROTOCOL != 2) ? pc_axi_rlast    : 1'b1;\n  rdata_q     <= pc_axi_rdata;\n  rresp_q     <= pc_axi_rresp;\n  ruser_q     <= (C_AXI_PROTOCOL != 2) ? pc_axi_ruser    : {C_AXI_RUSER_WIDTH{1'b0}};\n  rvalid_q    <= pc_axi_rvalid;\n  rready_q    <= pc_axi_rready;\n  pc_asserted_i <= |pc_status;\nend\n\nassign pc_asserted = pc_asserted_i;\n\naxi_protocol_checker_v1_1_12_core #(\n  .C_AXI_PROTOCOL             (C_AXI_PROTOCOL),\n  .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n  .C_AXI_DATA_WIDTH           (C_AXI_DATA_WIDTH),\n  .C_AXI_ADDR_WIDTH           (C_AXI_ADDR_WIDTH),\n  .C_AXI_AWUSER_WIDTH         (C_AXI_AWUSER_WIDTH),\n  .C_AXI_WUSER_WIDTH          (C_AXI_WUSER_WIDTH),\n  .C_AXI_BUSER_WIDTH          (C_AXI_BUSER_WIDTH),\n  .C_AXI_ARUSER_WIDTH         (C_AXI_ARUSER_WIDTH),\n  .C_AXI_RUSER_WIDTH          (C_AXI_RUSER_WIDTH),\n  .C_PC_SUPPORTS_NARROW_BURST (C_PC_SUPPORTS_NARROW_BURST),\n  .C_PC_MAX_BURST_LENGTH      (C_PC_MAX_BURST_LENGTH),\n  .MAXRBURSTS                 (C_PC_MAXRBURSTS),\n  .MAXWBURSTS                 (C_PC_MAXWBURSTS),\n  .EXMON_WIDTH                (C_PC_EXMON_WIDTH),\n  .MAX_AW_WAITS               (C_PC_AW_MAXWAITS),\n  .MAX_AR_WAITS               (C_PC_AR_MAXWAITS),\n  .MAX_W_WAITS                (C_PC_W_MAXWAITS),\n  .MAX_R_WAITS                (C_PC_R_MAXWAITS),\n  .MAX_B_WAITS                (C_PC_B_MAXWAITS),\n  .C_PC_HAS_SYSTEM_RESET      (C_PC_HAS_SYSTEM_RESET),\n  .C_ERROR_COUNT              (C_PC_STATUS_WIDTH)\n  ) CORE (\n    .pc_status        (pc_status),\n    .resetn           (system_resetn),\n    \n    .ACLK      (aclk),\n    .ARST_N    ( resetn_q   ),\n    .AWID      ( awid_q     ),\n    .AWADDR    ( awaddr_q   ),\n    .AWLEN     ( awlen_q    ),\n    .AWSIZE    ( awsize_q   ),\n    .AWBURST   ( awburst_q  ),\n    .AWLOCK    ( awlock_q   ),\n    .AWCACHE   ( awcache_q  ),\n    .AWPROT    ( awprot_q   ),\n    .AWQOS     ( awqos_q    ),\n    .AWREGION  ( awregion_q ),\n    .AWUSER    ( awuser_q   ),\n    .AWVALID   ( awvalid_q  ),\n    .AWREADY   ( awready_q  ),\n    .WLAST     ( wlast_q    ),\n    .WDATA     ( wdata_q    ),\n    .WSTRB     ( wstrb_q    ),\n    .WUSER     ( wuser_q    ),\n    .WVALID    ( wvalid_q   ),\n    .WREADY    ( wready_q   ),\n    .BID       ( bid_q      ),\n    .BRESP     ( bresp_q    ),\n    .BUSER     ( buser_q    ),\n    .BVALID    ( bvalid_q   ),\n    .BREADY    ( bready_q   ),\n    .ARID      ( arid_q     ),\n    .ARADDR    ( araddr_q   ),\n    .ARLEN     ( arlen_q    ),\n    .ARSIZE    ( arsize_q   ),\n    .ARBURST   ( arburst_q  ),\n    .ARLOCK    ( arlock_q   ),\n    .ARCACHE   ( arcache_q  ),\n    .ARPROT    ( arprot_q   ),\n    .ARQOS     ( arqos_q    ),\n    .ARREGION  ( arregion_q ),\n    .ARUSER    ( aruser_q   ),\n    .ARVALID   ( arvalid_q  ),\n    .ARREADY   ( arready_q  ),\n    .RID       ( rid_q      ),\n    .RLAST     ( rlast_q    ),\n    .RDATA     ( rdata_q    ),\n    .RRESP     ( rresp_q    ),\n    .RUSER     ( ruser_q    ),\n    .RVALID    ( rvalid_q   ),\n    .RREADY    ( rready_q   )\n);\n\naxi_protocol_checker_v1_1_12_reporter #(\n  .C_PC_MESSAGE_LEVEL         (C_PC_MESSAGE_LEVEL),\n  .C_PC_STATUS_WIDTH          (C_PC_STATUS_WIDTH)\n) REP (\n  .aclk         (aclk),\n  .pc_status    (pc_status)\n);\n\nendmodule // axi_protocol_checker_v1_1_12_top\n\n`default_nettype wire\n\n\n", "num_lines": 4624}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020\n//Date        : Wed Dec 15 00:42:23 2021\n//Host        : a-21awsprq4sria running 64-bit Amazon Linux release 2 (Karoo)\n//Command     : generate_target cl_axi_interconnect_wrapper.bd\n//Design      : cl_axi_interconnect_wrapper\n//Purpose     : IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule cl_axi_interconnect_wrapper\n   (ACLK,\n    ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  input ACLK;\n  input ARESETN;\n  output [63:0]M00_AXI_araddr;\n  output [1:0]M00_AXI_arburst;\n  output [3:0]M00_AXI_arcache;\n  output [6:0]M00_AXI_arid;\n  output [7:0]M00_AXI_arlen;\n  output [0:0]M00_AXI_arlock;\n  output [2:0]M00_AXI_arprot;\n  output [3:0]M00_AXI_arqos;\n  input M00_AXI_arready;\n  output [3:0]M00_AXI_arregion;\n  output [2:0]M00_AXI_arsize;\n  output M00_AXI_arvalid;\n  output [63:0]M00_AXI_awaddr;\n  output [1:0]M00_AXI_awburst;\n  output [3:0]M00_AXI_awcache;\n  output [6:0]M00_AXI_awid;\n  output [7:0]M00_AXI_awlen;\n  output [0:0]M00_AXI_awlock;\n  output [2:0]M00_AXI_awprot;\n  output [3:0]M00_AXI_awqos;\n  input M00_AXI_awready;\n  output [3:0]M00_AXI_awregion;\n  output [2:0]M00_AXI_awsize;\n  output M00_AXI_awvalid;\n  input [6:0]M00_AXI_bid;\n  output M00_AXI_bready;\n  input [1:0]M00_AXI_bresp;\n  input M00_AXI_bvalid;\n  input [511:0]M00_AXI_rdata;\n  input [6:0]M00_AXI_rid;\n  input M00_AXI_rlast;\n  output M00_AXI_rready;\n  input [1:0]M00_AXI_rresp;\n  input M00_AXI_rvalid;\n  output [511:0]M00_AXI_wdata;\n  output M00_AXI_wlast;\n  input M00_AXI_wready;\n  output [63:0]M00_AXI_wstrb;\n  output M00_AXI_wvalid;\n  output [63:0]M01_AXI_araddr;\n  output [1:0]M01_AXI_arburst;\n  output [3:0]M01_AXI_arcache;\n  output [6:0]M01_AXI_arid;\n  output [7:0]M01_AXI_arlen;\n  output [0:0]M01_AXI_arlock;\n  output [2:0]M01_AXI_arprot;\n  output [3:0]M01_AXI_arqos;\n  input M01_AXI_arready;\n  output [3:0]M01_AXI_arregion;\n  output [2:0]M01_AXI_arsize;\n  output M01_AXI_arvalid;\n  output [63:0]M01_AXI_awaddr;\n  output [1:0]M01_AXI_awburst;\n  output [3:0]M01_AXI_awcache;\n  output [6:0]M01_AXI_awid;\n  output [7:0]M01_AXI_awlen;\n  output [0:0]M01_AXI_awlock;\n  output [2:0]M01_AXI_awprot;\n  output [3:0]M01_AXI_awqos;\n  input M01_AXI_awready;\n  output [3:0]M01_AXI_awregion;\n  output [2:0]M01_AXI_awsize;\n  output M01_AXI_awvalid;\n  input [6:0]M01_AXI_bid;\n  output M01_AXI_bready;\n  input [1:0]M01_AXI_bresp;\n  input M01_AXI_bvalid;\n  input [511:0]M01_AXI_rdata;\n  input [6:0]M01_AXI_rid;\n  input M01_AXI_rlast;\n  output M01_AXI_rready;\n  input [1:0]M01_AXI_rresp;\n  input M01_AXI_rvalid;\n  output [511:0]M01_AXI_wdata;\n  output M01_AXI_wlast;\n  input M01_AXI_wready;\n  output [63:0]M01_AXI_wstrb;\n  output M01_AXI_wvalid;\n  output [63:0]M02_AXI_araddr;\n  output [1:0]M02_AXI_arburst;\n  output [3:0]M02_AXI_arcache;\n  output [6:0]M02_AXI_arid;\n  output [7:0]M02_AXI_arlen;\n  output [0:0]M02_AXI_arlock;\n  output [2:0]M02_AXI_arprot;\n  output [3:0]M02_AXI_arqos;\n  input M02_AXI_arready;\n  output [3:0]M02_AXI_arregion;\n  output [2:0]M02_AXI_arsize;\n  output M02_AXI_arvalid;\n  output [63:0]M02_AXI_awaddr;\n  output [1:0]M02_AXI_awburst;\n  output [3:0]M02_AXI_awcache;\n  output [6:0]M02_AXI_awid;\n  output [7:0]M02_AXI_awlen;\n  output [0:0]M02_AXI_awlock;\n  output [2:0]M02_AXI_awprot;\n  output [3:0]M02_AXI_awqos;\n  input M02_AXI_awready;\n  output [3:0]M02_AXI_awregion;\n  output [2:0]M02_AXI_awsize;\n  output M02_AXI_awvalid;\n  input [6:0]M02_AXI_bid;\n  output M02_AXI_bready;\n  input [1:0]M02_AXI_bresp;\n  input M02_AXI_bvalid;\n  input [511:0]M02_AXI_rdata;\n  input [6:0]M02_AXI_rid;\n  input M02_AXI_rlast;\n  output M02_AXI_rready;\n  input [1:0]M02_AXI_rresp;\n  input M02_AXI_rvalid;\n  output [511:0]M02_AXI_wdata;\n  output M02_AXI_wlast;\n  input M02_AXI_wready;\n  output [63:0]M02_AXI_wstrb;\n  output M02_AXI_wvalid;\n  output [63:0]M03_AXI_araddr;\n  output [1:0]M03_AXI_arburst;\n  output [3:0]M03_AXI_arcache;\n  output [6:0]M03_AXI_arid;\n  output [7:0]M03_AXI_arlen;\n  output [0:0]M03_AXI_arlock;\n  output [2:0]M03_AXI_arprot;\n  output [3:0]M03_AXI_arqos;\n  input M03_AXI_arready;\n  output [3:0]M03_AXI_arregion;\n  output [2:0]M03_AXI_arsize;\n  output M03_AXI_arvalid;\n  output [63:0]M03_AXI_awaddr;\n  output [1:0]M03_AXI_awburst;\n  output [3:0]M03_AXI_awcache;\n  output [6:0]M03_AXI_awid;\n  output [7:0]M03_AXI_awlen;\n  output [0:0]M03_AXI_awlock;\n  output [2:0]M03_AXI_awprot;\n  output [3:0]M03_AXI_awqos;\n  input M03_AXI_awready;\n  output [3:0]M03_AXI_awregion;\n  output [2:0]M03_AXI_awsize;\n  output M03_AXI_awvalid;\n  input [6:0]M03_AXI_bid;\n  output M03_AXI_bready;\n  input [1:0]M03_AXI_bresp;\n  input M03_AXI_bvalid;\n  input [511:0]M03_AXI_rdata;\n  input [6:0]M03_AXI_rid;\n  input M03_AXI_rlast;\n  output M03_AXI_rready;\n  input [1:0]M03_AXI_rresp;\n  input M03_AXI_rvalid;\n  output [511:0]M03_AXI_wdata;\n  output M03_AXI_wlast;\n  input M03_AXI_wready;\n  output [63:0]M03_AXI_wstrb;\n  output M03_AXI_wvalid;\n  input [63:0]S00_AXI_araddr;\n  input [1:0]S00_AXI_arburst;\n  input [3:0]S00_AXI_arcache;\n  input [5:0]S00_AXI_arid;\n  input [7:0]S00_AXI_arlen;\n  input [0:0]S00_AXI_arlock;\n  input [2:0]S00_AXI_arprot;\n  input [3:0]S00_AXI_arqos;\n  output S00_AXI_arready;\n  input [3:0]S00_AXI_arregion;\n  input [2:0]S00_AXI_arsize;\n  input S00_AXI_arvalid;\n  input [63:0]S00_AXI_awaddr;\n  input [1:0]S00_AXI_awburst;\n  input [3:0]S00_AXI_awcache;\n  input [5:0]S00_AXI_awid;\n  input [7:0]S00_AXI_awlen;\n  input [0:0]S00_AXI_awlock;\n  input [2:0]S00_AXI_awprot;\n  input [3:0]S00_AXI_awqos;\n  output S00_AXI_awready;\n  input [3:0]S00_AXI_awregion;\n  input [2:0]S00_AXI_awsize;\n  input S00_AXI_awvalid;\n  output [5:0]S00_AXI_bid;\n  input S00_AXI_bready;\n  output [1:0]S00_AXI_bresp;\n  output S00_AXI_bvalid;\n  output [511:0]S00_AXI_rdata;\n  output [5:0]S00_AXI_rid;\n  output S00_AXI_rlast;\n  input S00_AXI_rready;\n  output [1:0]S00_AXI_rresp;\n  output S00_AXI_rvalid;\n  input [511:0]S00_AXI_wdata;\n  input S00_AXI_wlast;\n  output S00_AXI_wready;\n  input [63:0]S00_AXI_wstrb;\n  input S00_AXI_wvalid;\n  input [63:0]S01_AXI_araddr;\n  input [1:0]S01_AXI_arburst;\n  input [3:0]S01_AXI_arcache;\n  input [5:0]S01_AXI_arid;\n  input [7:0]S01_AXI_arlen;\n  input [0:0]S01_AXI_arlock;\n  input [2:0]S01_AXI_arprot;\n  input [3:0]S01_AXI_arqos;\n  output S01_AXI_arready;\n  input [3:0]S01_AXI_arregion;\n  input [2:0]S01_AXI_arsize;\n  input S01_AXI_arvalid;\n  input [63:0]S01_AXI_awaddr;\n  input [1:0]S01_AXI_awburst;\n  input [3:0]S01_AXI_awcache;\n  input [5:0]S01_AXI_awid;\n  input [7:0]S01_AXI_awlen;\n  input [0:0]S01_AXI_awlock;\n  input [2:0]S01_AXI_awprot;\n  input [3:0]S01_AXI_awqos;\n  output S01_AXI_awready;\n  input [3:0]S01_AXI_awregion;\n  input [2:0]S01_AXI_awsize;\n  input S01_AXI_awvalid;\n  output [5:0]S01_AXI_bid;\n  input S01_AXI_bready;\n  output [1:0]S01_AXI_bresp;\n  output S01_AXI_bvalid;\n  output [511:0]S01_AXI_rdata;\n  output [5:0]S01_AXI_rid;\n  output S01_AXI_rlast;\n  input S01_AXI_rready;\n  output [1:0]S01_AXI_rresp;\n  output S01_AXI_rvalid;\n  input [511:0]S01_AXI_wdata;\n  input S01_AXI_wlast;\n  output S01_AXI_wready;\n  input [63:0]S01_AXI_wstrb;\n  input S01_AXI_wvalid;\n\n  wire ACLK;\n  wire ARESETN;\n  wire [63:0]M00_AXI_araddr;\n  wire [1:0]M00_AXI_arburst;\n  wire [3:0]M00_AXI_arcache;\n  wire [6:0]M00_AXI_arid;\n  wire [7:0]M00_AXI_arlen;\n  wire [0:0]M00_AXI_arlock;\n  wire [2:0]M00_AXI_arprot;\n  wire [3:0]M00_AXI_arqos;\n  wire M00_AXI_arready;\n  wire [3:0]M00_AXI_arregion;\n  wire [2:0]M00_AXI_arsize;\n  wire M00_AXI_arvalid;\n  wire [63:0]M00_AXI_awaddr;\n  wire [1:0]M00_AXI_awburst;\n  wire [3:0]M00_AXI_awcache;\n  wire [6:0]M00_AXI_awid;\n  wire [7:0]M00_AXI_awlen;\n  wire [0:0]M00_AXI_awlock;\n  wire [2:0]M00_AXI_awprot;\n  wire [3:0]M00_AXI_awqos;\n  wire M00_AXI_awready;\n  wire [3:0]M00_AXI_awregion;\n  wire [2:0]M00_AXI_awsize;\n  wire M00_AXI_awvalid;\n  wire [6:0]M00_AXI_bid;\n  wire M00_AXI_bready;\n  wire [1:0]M00_AXI_bresp;\n  wire M00_AXI_bvalid;\n  wire [511:0]M00_AXI_rdata;\n  wire [6:0]M00_AXI_rid;\n  wire M00_AXI_rlast;\n  wire M00_AXI_rready;\n  wire [1:0]M00_AXI_rresp;\n  wire M00_AXI_rvalid;\n  wire [511:0]M00_AXI_wdata;\n  wire M00_AXI_wlast;\n  wire M00_AXI_wready;\n  wire [63:0]M00_AXI_wstrb;\n  wire M00_AXI_wvalid;\n  wire [63:0]M01_AXI_araddr;\n  wire [1:0]M01_AXI_arburst;\n  wire [3:0]M01_AXI_arcache;\n  wire [6:0]M01_AXI_arid;\n  wire [7:0]M01_AXI_arlen;\n  wire [0:0]M01_AXI_arlock;\n  wire [2:0]M01_AXI_arprot;\n  wire [3:0]M01_AXI_arqos;\n  wire M01_AXI_arready;\n  wire [3:0]M01_AXI_arregion;\n  wire [2:0]M01_AXI_arsize;\n  wire M01_AXI_arvalid;\n  wire [63:0]M01_AXI_awaddr;\n  wire [1:0]M01_AXI_awburst;\n  wire [3:0]M01_AXI_awcache;\n  wire [6:0]M01_AXI_awid;\n  wire [7:0]M01_AXI_awlen;\n  wire [0:0]M01_AXI_awlock;\n  wire [2:0]M01_AXI_awprot;\n  wire [3:0]M01_AXI_awqos;\n  wire M01_AXI_awready;\n  wire [3:0]M01_AXI_awregion;\n  wire [2:0]M01_AXI_awsize;\n  wire M01_AXI_awvalid;\n  wire [6:0]M01_AXI_bid;\n  wire M01_AXI_bready;\n  wire [1:0]M01_AXI_bresp;\n  wire M01_AXI_bvalid;\n  wire [511:0]M01_AXI_rdata;\n  wire [6:0]M01_AXI_rid;\n  wire M01_AXI_rlast;\n  wire M01_AXI_rready;\n  wire [1:0]M01_AXI_rresp;\n  wire M01_AXI_rvalid;\n  wire [511:0]M01_AXI_wdata;\n  wire M01_AXI_wlast;\n  wire M01_AXI_wready;\n  wire [63:0]M01_AXI_wstrb;\n  wire M01_AXI_wvalid;\n  wire [63:0]M02_AXI_araddr;\n  wire [1:0]M02_AXI_arburst;\n  wire [3:0]M02_AXI_arcache;\n  wire [6:0]M02_AXI_arid;\n  wire [7:0]M02_AXI_arlen;\n  wire [0:0]M02_AXI_arlock;\n  wire [2:0]M02_AXI_arprot;\n  wire [3:0]M02_AXI_arqos;\n  wire M02_AXI_arready;\n  wire [3:0]M02_AXI_arregion;\n  wire [2:0]M02_AXI_arsize;\n  wire M02_AXI_arvalid;\n  wire [63:0]M02_AXI_awaddr;\n  wire [1:0]M02_AXI_awburst;\n  wire [3:0]M02_AXI_awcache;\n  wire [6:0]M02_AXI_awid;\n  wire [7:0]M02_AXI_awlen;\n  wire [0:0]M02_AXI_awlock;\n  wire [2:0]M02_AXI_awprot;\n  wire [3:0]M02_AXI_awqos;\n  wire M02_AXI_awready;\n  wire [3:0]M02_AXI_awregion;\n  wire [2:0]M02_AXI_awsize;\n  wire M02_AXI_awvalid;\n  wire [6:0]M02_AXI_bid;\n  wire M02_AXI_bready;\n  wire [1:0]M02_AXI_bresp;\n  wire M02_AXI_bvalid;\n  wire [511:0]M02_AXI_rdata;\n  wire [6:0]M02_AXI_rid;\n  wire M02_AXI_rlast;\n  wire M02_AXI_rready;\n  wire [1:0]M02_AXI_rresp;\n  wire M02_AXI_rvalid;\n  wire [511:0]M02_AXI_wdata;\n  wire M02_AXI_wlast;\n  wire M02_AXI_wready;\n  wire [63:0]M02_AXI_wstrb;\n  wire M02_AXI_wvalid;\n  wire [63:0]M03_AXI_araddr;\n  wire [1:0]M03_AXI_arburst;\n  wire [3:0]M03_AXI_arcache;\n  wire [6:0]M03_AXI_arid;\n  wire [7:0]M03_AXI_arlen;\n  wire [0:0]M03_AXI_arlock;\n  wire [2:0]M03_AXI_arprot;\n  wire [3:0]M03_AXI_arqos;\n  wire M03_AXI_arready;\n  wire [3:0]M03_AXI_arregion;\n  wire [2:0]M03_AXI_arsize;\n  wire M03_AXI_arvalid;\n  wire [63:0]M03_AXI_awaddr;\n  wire [1:0]M03_AXI_awburst;\n  wire [3:0]M03_AXI_awcache;\n  wire [6:0]M03_AXI_awid;\n  wire [7:0]M03_AXI_awlen;\n  wire [0:0]M03_AXI_awlock;\n  wire [2:0]M03_AXI_awprot;\n  wire [3:0]M03_AXI_awqos;\n  wire M03_AXI_awready;\n  wire [3:0]M03_AXI_awregion;\n  wire [2:0]M03_AXI_awsize;\n  wire M03_AXI_awvalid;\n  wire [6:0]M03_AXI_bid;\n  wire M03_AXI_bready;\n  wire [1:0]M03_AXI_bresp;\n  wire M03_AXI_bvalid;\n  wire [511:0]M03_AXI_rdata;\n  wire [6:0]M03_AXI_rid;\n  wire M03_AXI_rlast;\n  wire M03_AXI_rready;\n  wire [1:0]M03_AXI_rresp;\n  wire M03_AXI_rvalid;\n  wire [511:0]M03_AXI_wdata;\n  wire M03_AXI_wlast;\n  wire M03_AXI_wready;\n  wire [63:0]M03_AXI_wstrb;\n  wire M03_AXI_wvalid;\n  wire [63:0]S00_AXI_araddr;\n  wire [1:0]S00_AXI_arburst;\n  wire [3:0]S00_AXI_arcache;\n  wire [5:0]S00_AXI_arid;\n  wire [7:0]S00_AXI_arlen;\n  wire [0:0]S00_AXI_arlock;\n  wire [2:0]S00_AXI_arprot;\n  wire [3:0]S00_AXI_arqos;\n  wire S00_AXI_arready;\n  wire [3:0]S00_AXI_arregion;\n  wire [2:0]S00_AXI_arsize;\n  wire S00_AXI_arvalid;\n  wire [63:0]S00_AXI_awaddr;\n  wire [1:0]S00_AXI_awburst;\n  wire [3:0]S00_AXI_awcache;\n  wire [5:0]S00_AXI_awid;\n  wire [7:0]S00_AXI_awlen;\n  wire [0:0]S00_AXI_awlock;\n  wire [2:0]S00_AXI_awprot;\n  wire [3:0]S00_AXI_awqos;\n  wire S00_AXI_awready;\n  wire [3:0]S00_AXI_awregion;\n  wire [2:0]S00_AXI_awsize;\n  wire S00_AXI_awvalid;\n  wire [5:0]S00_AXI_bid;\n  wire S00_AXI_bready;\n  wire [1:0]S00_AXI_bresp;\n  wire S00_AXI_bvalid;\n  wire [511:0]S00_AXI_rdata;\n  wire [5:0]S00_AXI_rid;\n  wire S00_AXI_rlast;\n  wire S00_AXI_rready;\n  wire [1:0]S00_AXI_rresp;\n  wire S00_AXI_rvalid;\n  wire [511:0]S00_AXI_wdata;\n  wire S00_AXI_wlast;\n  wire S00_AXI_wready;\n  wire [63:0]S00_AXI_wstrb;\n  wire S00_AXI_wvalid;\n  wire [63:0]S01_AXI_araddr;\n  wire [1:0]S01_AXI_arburst;\n  wire [3:0]S01_AXI_arcache;\n  wire [5:0]S01_AXI_arid;\n  wire [7:0]S01_AXI_arlen;\n  wire [0:0]S01_AXI_arlock;\n  wire [2:0]S01_AXI_arprot;\n  wire [3:0]S01_AXI_arqos;\n  wire S01_AXI_arready;\n  wire [3:0]S01_AXI_arregion;\n  wire [2:0]S01_AXI_arsize;\n  wire S01_AXI_arvalid;\n  wire [63:0]S01_AXI_awaddr;\n  wire [1:0]S01_AXI_awburst;\n  wire [3:0]S01_AXI_awcache;\n  wire [5:0]S01_AXI_awid;\n  wire [7:0]S01_AXI_awlen;\n  wire [0:0]S01_AXI_awlock;\n  wire [2:0]S01_AXI_awprot;\n  wire [3:0]S01_AXI_awqos;\n  wire S01_AXI_awready;\n  wire [3:0]S01_AXI_awregion;\n  wire [2:0]S01_AXI_awsize;\n  wire S01_AXI_awvalid;\n  wire [5:0]S01_AXI_bid;\n  wire S01_AXI_bready;\n  wire [1:0]S01_AXI_bresp;\n  wire S01_AXI_bvalid;\n  wire [511:0]S01_AXI_rdata;\n  wire [5:0]S01_AXI_rid;\n  wire S01_AXI_rlast;\n  wire S01_AXI_rready;\n  wire [1:0]S01_AXI_rresp;\n  wire S01_AXI_rvalid;\n  wire [511:0]S01_AXI_wdata;\n  wire S01_AXI_wlast;\n  wire S01_AXI_wready;\n  wire [63:0]S01_AXI_wstrb;\n  wire S01_AXI_wvalid;\n\n  cl_axi_interconnect cl_axi_interconnect_i\n       (.ACLK(ACLK),\n        .ARESETN(ARESETN),\n        .M00_AXI_araddr(M00_AXI_araddr),\n        .M00_AXI_arburst(M00_AXI_arburst),\n        .M00_AXI_arcache(M00_AXI_arcache),\n        .M00_AXI_arid(M00_AXI_arid),\n        .M00_AXI_arlen(M00_AXI_arlen),\n        .M00_AXI_arlock(M00_AXI_arlock),\n        .M00_AXI_arprot(M00_AXI_arprot),\n        .M00_AXI_arqos(M00_AXI_arqos),\n        .M00_AXI_arready(M00_AXI_arready),\n        .M00_AXI_arregion(M00_AXI_arregion),\n        .M00_AXI_arsize(M00_AXI_arsize),\n        .M00_AXI_arvalid(M00_AXI_arvalid),\n        .M00_AXI_awaddr(M00_AXI_awaddr),\n        .M00_AXI_awburst(M00_AXI_awburst),\n        .M00_AXI_awcache(M00_AXI_awcache),\n        .M00_AXI_awid(M00_AXI_awid),\n        .M00_AXI_awlen(M00_AXI_awlen),\n        .M00_AXI_awlock(M00_AXI_awlock),\n        .M00_AXI_awprot(M00_AXI_awprot),\n        .M00_AXI_awqos(M00_AXI_awqos),\n        .M00_AXI_awready(M00_AXI_awready),\n        .M00_AXI_awregion(M00_AXI_awregion),\n        .M00_AXI_awsize(M00_AXI_awsize),\n        .M00_AXI_awvalid(M00_AXI_awvalid),\n        .M00_AXI_bid(M00_AXI_bid),\n        .M00_AXI_bready(M00_AXI_bready),\n        .M00_AXI_bresp(M00_AXI_bresp),\n        .M00_AXI_bvalid(M00_AXI_bvalid),\n        .M00_AXI_rdata(M00_AXI_rdata),\n        .M00_AXI_rid(M00_AXI_rid),\n        .M00_AXI_rlast(M00_AXI_rlast),\n        .M00_AXI_rready(M00_AXI_rready),\n        .M00_AXI_rresp(M00_AXI_rresp),\n        .M00_AXI_rvalid(M00_AXI_rvalid),\n        .M00_AXI_wdata(M00_AXI_wdata),\n        .M00_AXI_wlast(M00_AXI_wlast),\n        .M00_AXI_wready(M00_AXI_wready),\n        .M00_AXI_wstrb(M00_AXI_wstrb),\n        .M00_AXI_wvalid(M00_AXI_wvalid),\n        .M01_AXI_araddr(M01_AXI_araddr),\n        .M01_AXI_arburst(M01_AXI_arburst),\n        .M01_AXI_arcache(M01_AXI_arcache),\n        .M01_AXI_arid(M01_AXI_arid),\n        .M01_AXI_arlen(M01_AXI_arlen),\n        .M01_AXI_arlock(M01_AXI_arlock),\n        .M01_AXI_arprot(M01_AXI_arprot),\n        .M01_AXI_arqos(M01_AXI_arqos),\n        .M01_AXI_arready(M01_AXI_arready),\n        .M01_AXI_arregion(M01_AXI_arregion),\n        .M01_AXI_arsize(M01_AXI_arsize),\n        .M01_AXI_arvalid(M01_AXI_arvalid),\n        .M01_AXI_awaddr(M01_AXI_awaddr),\n        .M01_AXI_awburst(M01_AXI_awburst),\n        .M01_AXI_awcache(M01_AXI_awcache),\n        .M01_AXI_awid(M01_AXI_awid),\n        .M01_AXI_awlen(M01_AXI_awlen),\n        .M01_AXI_awlock(M01_AXI_awlock),\n        .M01_AXI_awprot(M01_AXI_awprot),\n        .M01_AXI_awqos(M01_AXI_awqos),\n        .M01_AXI_awready(M01_AXI_awready),\n        .M01_AXI_awregion(M01_AXI_awregion),\n        .M01_AXI_awsize(M01_AXI_awsize),\n        .M01_AXI_awvalid(M01_AXI_awvalid),\n        .M01_AXI_bid(M01_AXI_bid),\n        .M01_AXI_bready(M01_AXI_bready),\n        .M01_AXI_bresp(M01_AXI_bresp),\n        .M01_AXI_bvalid(M01_AXI_bvalid),\n        .M01_AXI_rdata(M01_AXI_rdata),\n        .M01_AXI_rid(M01_AXI_rid),\n        .M01_AXI_rlast(M01_AXI_rlast),\n        .M01_AXI_rready(M01_AXI_rready),\n        .M01_AXI_rresp(M01_AXI_rresp),\n        .M01_AXI_rvalid(M01_AXI_rvalid),\n        .M01_AXI_wdata(M01_AXI_wdata),\n        .M01_AXI_wlast(M01_AXI_wlast),\n        .M01_AXI_wready(M01_AXI_wready),\n        .M01_AXI_wstrb(M01_AXI_wstrb),\n        .M01_AXI_wvalid(M01_AXI_wvalid),\n        .M02_AXI_araddr(M02_AXI_araddr),\n        .M02_AXI_arburst(M02_AXI_arburst),\n        .M02_AXI_arcache(M02_AXI_arcache),\n        .M02_AXI_arid(M02_AXI_arid),\n        .M02_AXI_arlen(M02_AXI_arlen),\n        .M02_AXI_arlock(M02_AXI_arlock),\n        .M02_AXI_arprot(M02_AXI_arprot),\n        .M02_AXI_arqos(M02_AXI_arqos),\n        .M02_AXI_arready(M02_AXI_arready),\n        .M02_AXI_arregion(M02_AXI_arregion),\n        .M02_AXI_arsize(M02_AXI_arsize),\n        .M02_AXI_arvalid(M02_AXI_arvalid),\n        .M02_AXI_awaddr(M02_AXI_awaddr),\n        .M02_AXI_awburst(M02_AXI_awburst),\n        .M02_AXI_awcache(M02_AXI_awcache),\n        .M02_AXI_awid(M02_AXI_awid),\n        .M02_AXI_awlen(M02_AXI_awlen),\n        .M02_AXI_awlock(M02_AXI_awlock),\n        .M02_AXI_awprot(M02_AXI_awprot),\n        .M02_AXI_awqos(M02_AXI_awqos),\n        .M02_AXI_awready(M02_AXI_awready),\n        .M02_AXI_awregion(M02_AXI_awregion),\n        .M02_AXI_awsize(M02_AXI_awsize),\n        .M02_AXI_awvalid(M02_AXI_awvalid),\n        .M02_AXI_bid(M02_AXI_bid),\n        .M02_AXI_bready(M02_AXI_bready),\n        .M02_AXI_bresp(M02_AXI_bresp),\n        .M02_AXI_bvalid(M02_AXI_bvalid),\n        .M02_AXI_rdata(M02_AXI_rdata),\n        .M02_AXI_rid(M02_AXI_rid),\n        .M02_AXI_rlast(M02_AXI_rlast),\n        .M02_AXI_rready(M02_AXI_rready),\n        .M02_AXI_rresp(M02_AXI_rresp),\n        .M02_AXI_rvalid(M02_AXI_rvalid),\n        .M02_AXI_wdata(M02_AXI_wdata),\n        .M02_AXI_wlast(M02_AXI_wlast),\n        .M02_AXI_wready(M02_AXI_wready),\n        .M02_AXI_wstrb(M02_AXI_wstrb),\n        .M02_AXI_wvalid(M02_AXI_wvalid),\n        .M03_AXI_araddr(M03_AXI_araddr),\n        .M03_AXI_arburst(M03_AXI_arburst),\n        .M03_AXI_arcache(M03_AXI_arcache),\n        .M03_AXI_arid(M03_AXI_arid),\n        .M03_AXI_arlen(M03_AXI_arlen),\n        .M03_AXI_arlock(M03_AXI_arlock),\n        .M03_AXI_arprot(M03_AXI_arprot),\n        .M03_AXI_arqos(M03_AXI_arqos),\n        .M03_AXI_arready(M03_AXI_arready),\n        .M03_AXI_arregion(M03_AXI_arregion),\n        .M03_AXI_arsize(M03_AXI_arsize),\n        .M03_AXI_arvalid(M03_AXI_arvalid),\n        .M03_AXI_awaddr(M03_AXI_awaddr),\n        .M03_AXI_awburst(M03_AXI_awburst),\n        .M03_AXI_awcache(M03_AXI_awcache),\n        .M03_AXI_awid(M03_AXI_awid),\n        .M03_AXI_awlen(M03_AXI_awlen),\n        .M03_AXI_awlock(M03_AXI_awlock),\n        .M03_AXI_awprot(M03_AXI_awprot),\n        .M03_AXI_awqos(M03_AXI_awqos),\n        .M03_AXI_awready(M03_AXI_awready),\n        .M03_AXI_awregion(M03_AXI_awregion),\n        .M03_AXI_awsize(M03_AXI_awsize),\n        .M03_AXI_awvalid(M03_AXI_awvalid),\n        .M03_AXI_bid(M03_AXI_bid),\n        .M03_AXI_bready(M03_AXI_bready),\n        .M03_AXI_bresp(M03_AXI_bresp),\n        .M03_AXI_bvalid(M03_AXI_bvalid),\n        .M03_AXI_rdata(M03_AXI_rdata),\n        .M03_AXI_rid(M03_AXI_rid),\n        .M03_AXI_rlast(M03_AXI_rlast),\n        .M03_AXI_rready(M03_AXI_rready),\n        .M03_AXI_rresp(M03_AXI_rresp),\n        .M03_AXI_rvalid(M03_AXI_rvalid),\n        .M03_AXI_wdata(M03_AXI_wdata),\n        .M03_AXI_wlast(M03_AXI_wlast),\n        .M03_AXI_wready(M03_AXI_wready),\n        .M03_AXI_wstrb(M03_AXI_wstrb),\n        .M03_AXI_wvalid(M03_AXI_wvalid),\n        .S00_AXI_araddr(S00_AXI_araddr),\n        .S00_AXI_arburst(S00_AXI_arburst),\n        .S00_AXI_arcache(S00_AXI_arcache),\n        .S00_AXI_arid(S00_AXI_arid),\n        .S00_AXI_arlen(S00_AXI_arlen),\n        .S00_AXI_arlock(S00_AXI_arlock),\n        .S00_AXI_arprot(S00_AXI_arprot),\n        .S00_AXI_arqos(S00_AXI_arqos),\n        .S00_AXI_arready(S00_AXI_arready),\n        .S00_AXI_arregion(S00_AXI_arregion),\n        .S00_AXI_arsize(S00_AXI_arsize),\n        .S00_AXI_arvalid(S00_AXI_arvalid),\n        .S00_AXI_awaddr(S00_AXI_awaddr),\n        .S00_AXI_awburst(S00_AXI_awburst),\n        .S00_AXI_awcache(S00_AXI_awcache),\n        .S00_AXI_awid(S00_AXI_awid),\n        .S00_AXI_awlen(S00_AXI_awlen),\n        .S00_AXI_awlock(S00_AXI_awlock),\n        .S00_AXI_awprot(S00_AXI_awprot),\n        .S00_AXI_awqos(S00_AXI_awqos),\n        .S00_AXI_awready(S00_AXI_awready),\n        .S00_AXI_awregion(S00_AXI_awregion),\n        .S00_AXI_awsize(S00_AXI_awsize),\n        .S00_AXI_awvalid(S00_AXI_awvalid),\n        .S00_AXI_bid(S00_AXI_bid),\n        .S00_AXI_bready(S00_AXI_bready),\n        .S00_AXI_bresp(S00_AXI_bresp),\n        .S00_AXI_bvalid(S00_AXI_bvalid),\n        .S00_AXI_rdata(S00_AXI_rdata),\n        .S00_AXI_rid(S00_AXI_rid),\n        .S00_AXI_rlast(S00_AXI_rlast),\n        .S00_AXI_rready(S00_AXI_rready),\n        .S00_AXI_rresp(S00_AXI_rresp),\n        .S00_AXI_rvalid(S00_AXI_rvalid),\n        .S00_AXI_wdata(S00_AXI_wdata),\n        .S00_AXI_wlast(S00_AXI_wlast),\n        .S00_AXI_wready(S00_AXI_wready),\n        .S00_AXI_wstrb(S00_AXI_wstrb),\n        .S00_AXI_wvalid(S00_AXI_wvalid),\n        .S01_AXI_araddr(S01_AXI_araddr),\n        .S01_AXI_arburst(S01_AXI_arburst),\n        .S01_AXI_arcache(S01_AXI_arcache),\n        .S01_AXI_arid(S01_AXI_arid),\n        .S01_AXI_arlen(S01_AXI_arlen),\n        .S01_AXI_arlock(S01_AXI_arlock),\n        .S01_AXI_arprot(S01_AXI_arprot),\n        .S01_AXI_arqos(S01_AXI_arqos),\n        .S01_AXI_arready(S01_AXI_arready),\n        .S01_AXI_arregion(S01_AXI_arregion),\n        .S01_AXI_arsize(S01_AXI_arsize),\n        .S01_AXI_arvalid(S01_AXI_arvalid),\n        .S01_AXI_awaddr(S01_AXI_awaddr),\n        .S01_AXI_awburst(S01_AXI_awburst),\n        .S01_AXI_awcache(S01_AXI_awcache),\n        .S01_AXI_awid(S01_AXI_awid),\n        .S01_AXI_awlen(S01_AXI_awlen),\n        .S01_AXI_awlock(S01_AXI_awlock),\n        .S01_AXI_awprot(S01_AXI_awprot),\n        .S01_AXI_awqos(S01_AXI_awqos),\n        .S01_AXI_awready(S01_AXI_awready),\n        .S01_AXI_awregion(S01_AXI_awregion),\n        .S01_AXI_awsize(S01_AXI_awsize),\n        .S01_AXI_awvalid(S01_AXI_awvalid),\n        .S01_AXI_bid(S01_AXI_bid),\n        .S01_AXI_bready(S01_AXI_bready),\n        .S01_AXI_bresp(S01_AXI_bresp),\n        .S01_AXI_bvalid(S01_AXI_bvalid),\n        .S01_AXI_rdata(S01_AXI_rdata),\n        .S01_AXI_rid(S01_AXI_rid),\n        .S01_AXI_rlast(S01_AXI_rlast),\n        .S01_AXI_rready(S01_AXI_rready),\n        .S01_AXI_rresp(S01_AXI_rresp),\n        .S01_AXI_rvalid(S01_AXI_rvalid),\n        .S01_AXI_wdata(S01_AXI_wdata),\n        .S01_AXI_wlast(S01_AXI_wlast),\n        .S01_AXI_wready(S01_AXI_wready),\n        .S01_AXI_wstrb(S01_AXI_wstrb),\n        .S01_AXI_wvalid(S01_AXI_wvalid));\nendmodule\n", "num_lines": 961}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_m00_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_m00_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=7,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_\\\nREG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m01_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_m01_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_m01_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=7,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_\\\nREG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m01_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m02_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_m02_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_m02_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=7,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_\\\nREG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m02_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m03_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_m03_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_m03_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=7,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_\\\nREG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m03_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_s00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_s00_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_s00_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=6,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_\\\nREG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_s00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_s01_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_s01_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_s01_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=6,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_\\\nREG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_s01_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_crossbar:2.1\n// IP Revision: 23\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_xbar_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLKIF, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLKIF CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RSTIF RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [6:0] [13:7]\" *)\ninput wire [13 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]\" *)\ninput wire [15 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]\" *)\ninput wire [3 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [511:0] [1023:512]\" *)\ninput wire [1023 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [6:0] [13:7]\" *)\noutput wire [13 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]\" *)\noutput wire [3 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [6:0] [13:7]\" *)\ninput wire [13 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]\" *)\ninput wire [15 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]\" *)\ninput wire [3 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [6:0] [13:7]\" *)\noutput wire [13 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [511:0] [1023:512]\" *)\noutput wire [1023 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]\" *)\noutput wire [3 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_\\\nTHREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME S01_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0\\\n00, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI AWID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI AWID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI AWID [6:0] [27:21]\" *)\noutput wire [27 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI AWLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI AWLEN [7:0] [31:24]\" *)\noutput wire [31 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI AWBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI AWBURST [1:0] [7:6]\" *)\noutput wire [7 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWREGION [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWQOS [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [511:0] [1023:512], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [511:0] [1535:1024], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [511:0] [2047:1536]\" *)\noutput wire [2047 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WLAST [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI BID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI BID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI BID [6:0] [27:21]\" *)\ninput wire [27 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]\" *)\ninput wire [7 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI ARID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI ARID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI ARID [6:0] [27:21]\" *)\noutput wire [27 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI ARLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI ARLEN [7:0] [31:24]\" *)\noutput wire [31 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI ARBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI ARBURST [1:0] [7:6]\" *)\noutput wire [7 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARREGION [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARQOS [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI RID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI RID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI RID [6:0] [27:21]\" *)\ninput wire [27 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [511:0] [1023:512], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [511:0] [1535:1024], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [511:0] [2047:1536]\" *)\ninput wire [2047 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]\" *)\ninput wire [7 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RLAST [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE\\\n_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0\\\n.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ\\\n_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, \\\nHAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_rready;\n\n  axi_crossbar_v2_1_23_axi_crossbar #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_NUM_SLAVE_SLOTS(2),\n    .C_NUM_MASTER_SLOTS(4),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_PROTOCOL(0),\n    .C_NUM_ADDR_RANGES(1),\n    .C_M_AXI_BASE_ADDR(256'H0000000c00000000000000080000000000000004000000000000000000000000),\n    .C_M_AXI_ADDR_WIDTH(128'H00000022000000220000002200000022),\n    .C_S_AXI_BASE_ID(64'H0000004000000000),\n    .C_S_AXI_THREAD_ID_WIDTH(64'H0000000600000006),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_M_AXI_WRITE_CONNECTIVITY(128'H00000003000000030000000300000003),\n    .C_M_AXI_READ_CONNECTIVITY(128'H00000003000000030000000300000003),\n    .C_R_REGISTER(0),\n    .C_S_AXI_SINGLE_THREAD(64'H0000000000000000),\n    .C_S_AXI_WRITE_ACCEPTANCE(64'H0000002000000020),\n    .C_S_AXI_READ_ACCEPTANCE(64'H0000002000000020),\n    .C_M_AXI_WRITE_ISSUING(128'H00000010000000100000001000000010),\n    .C_M_AXI_READ_ISSUING(128'H00000010000000100000001000000010),\n    .C_S_AXI_ARB_PRIORITY(64'H0000000000000000),\n    .C_M_AXI_SECURE(128'H00000000000000000000000000000000),\n    .C_CONNECTIVITY_MODE(1)\n  ) inst (\n    .aclk(aclk),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(2'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(14'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(2'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(2'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(4'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(4'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 427}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_crossbar:2.1\n// IP Revision: 23\n\n(* X_CORE_INFO = \"axi_crossbar_v2_1_23_axi_crossbar,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_xbar_0,axi_crossbar_v2_1_23_axi_crossbar,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_xbar_0,axi_crossbar_v2_1_23_axi_crossbar,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=23,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_NUM_SLAVE_SLOTS=2,C_NUM_MASTER_SLOTS=4,C_AXI_ID_WIDTH=7,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_PROTOCOL=0,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x0000000c00000000000000080000000000000004000000000000000000000000,C_M_AXI_ADDR_WIDTH=0x00000022000\\\n000220000002200000022,C_S_AXI_BASE_ID=0x0000004000000000,C_S_AXI_THREAD_ID_WIDTH=0x0000000600000006,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000003000000030000000300000003,C_M_AXI_READ_CONNECTIVITY=0x00000003000000030000000300000003,C_R_REGISTER=0,C_S_AXI_SINGLE_THREAD=0x0000000000000000,C_S_AXI_WRITE_ACCEPTANCE=0x0000002000000020,C_S_AXI_READ_ACCEPTANCE=0x0000002000000020,C_\\\nM_AXI_WRITE_ISSUING=0x00000010000000100000001000000010,C_M_AXI_READ_ISSUING=0x00000010000000100000001000000010,C_S_AXI_ARB_PRIORITY=0x0000000000000000,C_M_AXI_SECURE=0x00000000000000000000000000000000,C_CONNECTIVITY_MODE=1}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_xbar_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLKIF, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLKIF CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RSTIF RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [6:0] [13:7]\" *)\ninput wire [13 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]\" *)\ninput wire [15 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]\" *)\ninput wire [3 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [511:0] [1023:512]\" *)\ninput wire [1023 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [6:0] [13:7]\" *)\noutput wire [13 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]\" *)\noutput wire [3 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [6:0] [13:7]\" *)\ninput wire [13 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]\" *)\ninput wire [15 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]\" *)\ninput wire [3 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [6:0] [13:7]\" *)\noutput wire [13 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [511:0] [1023:512]\" *)\noutput wire [1023 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]\" *)\noutput wire [3 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_\\\nTHREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME S01_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0\\\n00, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI AWID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI AWID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI AWID [6:0] [27:21]\" *)\noutput wire [27 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI AWLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI AWLEN [7:0] [31:24]\" *)\noutput wire [31 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI AWBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI AWBURST [1:0] [7:6]\" *)\noutput wire [7 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWREGION [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWQOS [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [511:0] [1023:512], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [511:0] [1535:1024], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [511:0] [2047:1536]\" *)\noutput wire [2047 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WLAST [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI BID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI BID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI BID [6:0] [27:21]\" *)\ninput wire [27 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]\" *)\ninput wire [7 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI ARID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI ARID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI ARID [6:0] [27:21]\" *)\noutput wire [27 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI ARLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI ARLEN [7:0] [31:24]\" *)\noutput wire [31 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI ARBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI ARBURST [1:0] [7:6]\" *)\noutput wire [7 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARREGION [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARQOS [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI RID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI RID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI RID [6:0] [27:21]\" *)\ninput wire [27 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [511:0] [1023:512], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [511:0] [1535:1024], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [511:0] [2047:1536]\" *)\ninput wire [2047 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]\" *)\ninput wire [7 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RLAST [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE\\\n_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0\\\n.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ\\\n_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, \\\nHAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_rready;\n\n  axi_crossbar_v2_1_23_axi_crossbar #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_NUM_SLAVE_SLOTS(2),\n    .C_NUM_MASTER_SLOTS(4),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_PROTOCOL(0),\n    .C_NUM_ADDR_RANGES(1),\n    .C_M_AXI_BASE_ADDR(256'H0000000c00000000000000080000000000000004000000000000000000000000),\n    .C_M_AXI_ADDR_WIDTH(128'H00000022000000220000002200000022),\n    .C_S_AXI_BASE_ID(64'H0000004000000000),\n    .C_S_AXI_THREAD_ID_WIDTH(64'H0000000600000006),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_M_AXI_WRITE_CONNECTIVITY(128'H00000003000000030000000300000003),\n    .C_M_AXI_READ_CONNECTIVITY(128'H00000003000000030000000300000003),\n    .C_R_REGISTER(0),\n    .C_S_AXI_SINGLE_THREAD(64'H0000000000000000),\n    .C_S_AXI_WRITE_ACCEPTANCE(64'H0000002000000020),\n    .C_S_AXI_READ_ACCEPTANCE(64'H0000002000000020),\n    .C_M_AXI_WRITE_ISSUING(128'H00000010000000100000001000000010),\n    .C_M_AXI_READ_ISSUING(128'H00000010000000100000001000000010),\n    .C_S_AXI_ARB_PRIORITY(64'H0000000000000000),\n    .C_M_AXI_SECURE(128'H00000000000000000000000000000000),\n    .C_CONNECTIVITY_MODE(1)\n  ) inst (\n    .aclk(aclk),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(2'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(14'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(2'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(2'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(4'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(4'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 430}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/*\n *******************************************************************************\n *\n * FIFO Generator - Verilog Behavioral Model\n *\n *******************************************************************************\n *\n * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.\n *\n * This file contains confidential and proprietary information\n * of Xilinx, Inc. and is protected under U.S. and\n * international copyright and other intellectual property\n * laws.\n *\n * DISCLAIMER\n * This disclaimer is not a license and does not grant any\n * rights to the materials distributed herewith. Except as\n * otherwise provided in a valid license issued to you by\n * Xilinx, and to the maximum extent permitted by applicable\n * law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n * (2) Xilinx shall not be liable (whether in contract or tort,\n * including negligence, or under any other theory of\n * liability) for any loss or damage of any kind or nature\n * related to, arising under or in connection with these\n * materials, including for any direct, or any indirect,\n * special, incidental, or consequential loss or damage\n * (including loss of data, profits, goodwill, or any type of\n * loss or damage suffered as a result of any action brought\n * by a third party) even if such damage or loss was\n * reasonably foreseeable or Xilinx had been advised of the\n * possibility of the same.\n *\n * CRITICAL APPLICATIONS\n * Xilinx products are not designed or intended to be fail-\n * safe, or for use in any application requiring fail-safe\n * performance, such as life-support or safety devices or\n * systems, Class III medical devices, nuclear facilities,\n * applications related to the deployment of airbags, or any\n * other applications that could lead to death, personal\n * injury, or severe property or environmental damage\n * (individually and collectively, \"Critical\n * Applications\"). Customer assumes the sole risk and\n * liability of any use of Xilinx products in Critical\n * Applications, subject only to applicable laws and\n * regulations governing limitations on product liability.\n *\n * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n * PART OF THIS FILE AT ALL TIMES.\n *\n *******************************************************************************\n *******************************************************************************\n *\n * Filename: fifo_generator_vlog_beh.v\n *\n * Author     : Xilinx\n *\n *******************************************************************************\n * Structure:\n * \n * fifo_generator_vlog_beh.v\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_as\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_ss\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_preload0\n * \n *******************************************************************************\n * Description:\n *\n * The Verilog behavioral model for the FIFO Generator.\n *\n *   The behavioral model has three parts:\n *      - The behavioral model for independent clocks FIFOs (_as)\n *      - The behavioral model for common clock FIFOs (_ss)\n *      - The \"preload logic\" block which implements First-word Fall-through\n * \n *******************************************************************************\n * Description:\n *  The verilog behavioral model for the FIFO generator core.\n *\n *******************************************************************************\n */\n\n`timescale 1ps/1ps\n`ifndef TCQ\n `define TCQ 100\n`endif\n\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_vlog_beh\n  #(\n    //-----------------------------------------------------------------------\n    // Generic Declarations\n    //-----------------------------------------------------------------------\n    parameter C_COMMON_CLOCK                 = 0,\n    parameter C_COUNT_TYPE                   = 0,\n    parameter C_DATA_COUNT_WIDTH             = 2,\n    parameter C_DEFAULT_VALUE                = \"\",\n    parameter C_DIN_WIDTH                    = 8,\n    parameter C_DOUT_RST_VAL                 = \"\",\n    parameter C_DOUT_WIDTH                   = 8,\n    parameter C_ENABLE_RLOCS                 = 0,\n    parameter C_FAMILY                       = \"\",\n    parameter C_FULL_FLAGS_RST_VAL           = 1,\n    parameter C_HAS_ALMOST_EMPTY             = 0,\n    parameter C_HAS_ALMOST_FULL              = 0,\n    parameter C_HAS_BACKUP                   = 0,\n    parameter C_HAS_DATA_COUNT               = 0,\n    parameter C_HAS_INT_CLK                  = 0,\n    parameter C_HAS_MEMINIT_FILE             = 0,\n    parameter C_HAS_OVERFLOW                 = 0,\n    parameter C_HAS_RD_DATA_COUNT            = 0,\n    parameter C_HAS_RD_RST                   = 0,\n    parameter C_HAS_RST                      = 1,\n    parameter C_HAS_SRST                     = 0,\n    parameter C_HAS_UNDERFLOW                = 0,\n    parameter C_HAS_VALID                    = 0,\n    parameter C_HAS_WR_ACK                   = 0,\n    parameter C_HAS_WR_DATA_COUNT            = 0,\n    parameter C_HAS_WR_RST                   = 0,\n    parameter C_IMPLEMENTATION_TYPE          = 0,\n    parameter C_INIT_WR_PNTR_VAL             = 0,\n    parameter C_MEMORY_TYPE                  = 1,\n    parameter C_MIF_FILE_NAME                = \"\",\n    parameter C_OPTIMIZATION_MODE            = 0,\n    parameter C_OVERFLOW_LOW                 = 0,\n    parameter C_EN_SAFETY_CKT                = 0,\n    parameter C_PRELOAD_LATENCY              = 1,\n    parameter C_PRELOAD_REGS                 = 0,\n    parameter C_PRIM_FIFO_TYPE               = \"4kx4\",\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter C_PROG_EMPTY_TYPE              = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter C_PROG_FULL_TYPE               = 0,\n    parameter C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter C_RD_DEPTH                     = 256,\n    parameter C_RD_FREQ                      = 1,\n    parameter C_RD_PNTR_WIDTH                = 8,\n    parameter C_UNDERFLOW_LOW                = 0,\n    parameter C_USE_DOUT_RST                 = 0,\n    parameter C_USE_ECC                      = 0,\n    parameter C_USE_EMBEDDED_REG             = 0,\n    parameter C_USE_PIPELINE_REG             = 0,\n    parameter C_POWER_SAVING_MODE            = 0,\n    parameter C_USE_FIFO16_FLAGS             = 0,\n    parameter C_USE_FWFT_DATA_COUNT          = 0,\n    parameter C_VALID_LOW                    = 0,\n    parameter C_WR_ACK_LOW                   = 0,\n    parameter C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter C_WR_DEPTH                     = 256,\n    parameter C_WR_FREQ                      = 1,\n    parameter C_WR_PNTR_WIDTH                = 8,\n    parameter C_WR_RESPONSE_LATENCY          = 1,\n    parameter C_MSGON_VAL                    = 1,\n    parameter C_ENABLE_RST_SYNC              = 1,\n    parameter C_ERROR_INJECTION_TYPE         = 0,\n    parameter C_SYNCHRONIZER_STAGE           = 2,\n\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE               = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3\n    parameter C_AXI_TYPE                     = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3\n    parameter C_HAS_AXI_WR_CHANNEL           = 0,\n    parameter C_HAS_AXI_RD_CHANNEL           = 0,\n    parameter C_HAS_SLAVE_CE                 = 0,\n    parameter C_HAS_MASTER_CE                = 0,\n    parameter C_ADD_NGC_CONSTRAINT           = 0,\n    parameter C_USE_COMMON_UNDERFLOW         = 0,\n    parameter C_USE_COMMON_OVERFLOW          = 0,\n    parameter C_USE_DEFAULT_SETTINGS         = 0,\n\n    // AXI Full/Lite\n    parameter C_AXI_ID_WIDTH                 = 0,\n    parameter C_AXI_ADDR_WIDTH               = 0,\n    parameter C_AXI_DATA_WIDTH               = 0,\n    parameter C_AXI_LEN_WIDTH                = 8,\n    parameter C_AXI_LOCK_WIDTH               = 2,\n    parameter C_HAS_AXI_ID                   = 0,\n    parameter C_HAS_AXI_AWUSER               = 0,\n    parameter C_HAS_AXI_WUSER                = 0,\n    parameter C_HAS_AXI_BUSER                = 0,\n    parameter C_HAS_AXI_ARUSER               = 0,\n    parameter C_HAS_AXI_RUSER                = 0,\n    parameter C_AXI_ARUSER_WIDTH             = 0,\n    parameter C_AXI_AWUSER_WIDTH             = 0,\n    parameter C_AXI_WUSER_WIDTH              = 0,\n    parameter C_AXI_BUSER_WIDTH              = 0,\n    parameter C_AXI_RUSER_WIDTH              = 0,\n\n    // AXI Streaming\n    parameter C_HAS_AXIS_TDATA               = 0,\n    parameter C_HAS_AXIS_TID                 = 0,\n    parameter C_HAS_AXIS_TDEST               = 0,\n    parameter C_HAS_AXIS_TUSER               = 0,\n    parameter C_HAS_AXIS_TREADY              = 0,\n    parameter C_HAS_AXIS_TLAST               = 0,\n    parameter C_HAS_AXIS_TSTRB               = 0,\n    parameter C_HAS_AXIS_TKEEP               = 0,\n    parameter C_AXIS_TDATA_WIDTH             = 1,\n    parameter C_AXIS_TID_WIDTH               = 1,\n    parameter C_AXIS_TDEST_WIDTH             = 1,\n    parameter C_AXIS_TUSER_WIDTH             = 1,\n    parameter C_AXIS_TSTRB_WIDTH             = 1,\n    parameter C_AXIS_TKEEP_WIDTH             = 1,\n\n    // AXI Channel Type\n    // WACH --> Write Address Channel\n    // WDCH --> Write Data Channel\n    // WRCH --> Write Response Channel\n    // RACH --> Read Address Channel\n    // RDCH --> Read Data Channel\n    // AXIS --> AXI Streaming\n    parameter C_WACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic\n    parameter C_WDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_WRCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_AXIS_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n\n    // AXI Implementation Type\n    // 1 = Common Clock Block RAM FIFO\n    // 2 = Common Clock Distributed RAM FIFO\n    // 11 = Independent Clock Block RAM FIFO\n    // 12 = Independent Clock Distributed RAM FIFO\n    parameter C_IMPLEMENTATION_TYPE_WACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WRCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_AXIS     = 0,\n\n    // AXI FIFO Type\n    // 0 = Data FIFO\n    // 1 = Packet FIFO\n    // 2 = Low Latency Sync FIFO\n    // 3 = Low Latency Async FIFO\n    parameter C_APPLICATION_TYPE_WACH        = 0,\n    parameter C_APPLICATION_TYPE_WDCH        = 0,\n    parameter C_APPLICATION_TYPE_WRCH        = 0,\n    parameter C_APPLICATION_TYPE_RACH        = 0,\n    parameter C_APPLICATION_TYPE_RDCH        = 0,\n    parameter C_APPLICATION_TYPE_AXIS        = 0,\n\n    // AXI Built-in FIFO Primitive Type\n    // 512x36, 1kx18, 2kx9, 4kx4, etc\n    parameter C_PRIM_FIFO_TYPE_WACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WRCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_AXIS          = \"512x36\",\n\n    // Enable ECC\n    // 0 = ECC disabled\n    // 1 = ECC enabled\n    parameter C_USE_ECC_WACH                 = 0,\n    parameter C_USE_ECC_WDCH                 = 0,\n    parameter C_USE_ECC_WRCH                 = 0,\n    parameter C_USE_ECC_RACH                 = 0,\n    parameter C_USE_ECC_RDCH                 = 0,\n    parameter C_USE_ECC_AXIS                 = 0,\n\n    // ECC Error Injection Type\n    // 0 = No Error Injection\n    // 1 = Single Bit Error Injection\n    // 2 = Double Bit Error Injection\n    // 3 = Single Bit and Double Bit Error Injection\n    parameter C_ERROR_INJECTION_TYPE_WACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WRCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_AXIS    = 0,\n\n    // Input Data Width\n    // Accumulation of all AXI input signal's width\n    parameter C_DIN_WIDTH_WACH               = 1,\n    parameter C_DIN_WIDTH_WDCH               = 1,\n    parameter C_DIN_WIDTH_WRCH               = 1,\n    parameter C_DIN_WIDTH_RACH               = 1,\n    parameter C_DIN_WIDTH_RDCH               = 1,\n    parameter C_DIN_WIDTH_AXIS               = 1,\n\n    parameter C_WR_DEPTH_WACH                = 16,\n    parameter C_WR_DEPTH_WDCH                = 16,\n    parameter C_WR_DEPTH_WRCH                = 16,\n    parameter C_WR_DEPTH_RACH                = 16,\n    parameter C_WR_DEPTH_RDCH                = 16,\n    parameter C_WR_DEPTH_AXIS                = 16,\n\n    parameter C_WR_PNTR_WIDTH_WACH           = 4,\n    parameter C_WR_PNTR_WIDTH_WDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_WRCH           = 4,\n    parameter C_WR_PNTR_WIDTH_RACH           = 4,\n    parameter C_WR_PNTR_WIDTH_RDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_AXIS           = 4,\n\n    parameter C_HAS_DATA_COUNTS_WACH         = 0,\n    parameter C_HAS_DATA_COUNTS_WDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_WRCH         = 0,\n    parameter C_HAS_DATA_COUNTS_RACH         = 0,\n    parameter C_HAS_DATA_COUNTS_RDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_AXIS         = 0,\n\n    parameter C_HAS_PROG_FLAGS_WACH          = 0,\n    parameter C_HAS_PROG_FLAGS_WDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_WRCH          = 0,\n    parameter C_HAS_PROG_FLAGS_RACH          = 0,\n    parameter C_HAS_PROG_FLAGS_RDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_AXIS          = 0,\n\n    parameter C_PROG_FULL_TYPE_WACH          = 0,\n    parameter C_PROG_FULL_TYPE_WDCH          = 0,\n    parameter C_PROG_FULL_TYPE_WRCH          = 0,\n    parameter C_PROG_FULL_TYPE_RACH          = 0,\n    parameter C_PROG_FULL_TYPE_RDCH          = 0,\n    parameter C_PROG_FULL_TYPE_AXIS          = 0,\n\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS      = 0,\n\n    parameter C_PROG_EMPTY_TYPE_WACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WRCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_AXIS         = 0,\n\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS     = 0,\n\n    parameter C_REG_SLICE_MODE_WACH          = 0,\n    parameter C_REG_SLICE_MODE_WDCH          = 0,\n    parameter C_REG_SLICE_MODE_WRCH          = 0,\n    parameter C_REG_SLICE_MODE_RACH          = 0,\n    parameter C_REG_SLICE_MODE_RDCH          = 0,\n    parameter C_REG_SLICE_MODE_AXIS          = 0\n\n    )\n\n   (\n    //------------------------------------------------------------------------------\n    // Input and Output Declarations\n    //------------------------------------------------------------------------------\n\n    // Conventional FIFO Interface Signals\n    input                               backup,\n    input                               backup_marker,\n    input                               clk,\n    input                               rst,\n    input                               srst,\n    input                               wr_clk,\n    input                               wr_rst,\n    input                               rd_clk,\n    input                               rd_rst,\n    input [C_DIN_WIDTH-1:0]             din,\n    input                               wr_en,\n    input                               rd_en,\n    // Optional inputs\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_assert,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_negate,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_assert,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_negate,\n    input                               int_clk,\n    input                               injectdbiterr,\n    input                               injectsbiterr,\n    input                               sleep,\n\n    output [C_DOUT_WIDTH-1:0]           dout,\n    output                              full,\n    output                              almost_full,\n    output                              wr_ack,\n    output                              overflow,\n    output                              empty,\n    output                              almost_empty,\n    output                              valid,\n    output                              underflow,\n    output [C_DATA_COUNT_WIDTH-1:0]     data_count,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]  rd_data_count,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count,\n    output                              prog_full,\n    output                              prog_empty,\n    output                              sbiterr,\n    output                              dbiterr,\n    output                              wr_rst_busy,\n    output                              rd_rst_busy,\n\n\n    // AXI Global Signal\n    input                               m_aclk,\n    input                               s_aclk,\n    input                               s_aresetn,\n    input                               s_aclk_en,\n    input                               m_aclk_en,\n    \n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_awid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_awaddr,\n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_awlen,\n    input [3-1:0]                       s_axi_awsize,\n    input [2-1:0]                       s_axi_awburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_awlock,\n    input [4-1:0]                       s_axi_awcache,\n    input [3-1:0]                       s_axi_awprot,\n    input [4-1:0]                       s_axi_awqos,\n    input [4-1:0]                       s_axi_awregion,\n    input [C_AXI_AWUSER_WIDTH-1:0]      s_axi_awuser,\n    input                               s_axi_awvalid,\n    output                              s_axi_awready,\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_wid,\n    input [C_AXI_DATA_WIDTH-1:0]        s_axi_wdata,\n    input [C_AXI_DATA_WIDTH/8-1:0]      s_axi_wstrb,\n    input                               s_axi_wlast,\n    input [C_AXI_WUSER_WIDTH-1:0]       s_axi_wuser,\n    input                               s_axi_wvalid,\n    output                              s_axi_wready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_bid,\n    output [2-1:0]                      s_axi_bresp,\n    output [C_AXI_BUSER_WIDTH-1:0]      s_axi_buser,\n    output                              s_axi_bvalid,\n    input                               s_axi_bready,\n    \n    // AXI Full/Lite Master Write Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_awid,\n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_awlen,\n    output [3-1:0]                      m_axi_awsize,\n    output [2-1:0]                      m_axi_awburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_awlock,\n    output [4-1:0]                      m_axi_awcache,\n    output [3-1:0]                      m_axi_awprot,\n    output [4-1:0]                      m_axi_awqos,\n    output [4-1:0]                      m_axi_awregion,\n    output [C_AXI_AWUSER_WIDTH-1:0]     m_axi_awuser,\n    output                              m_axi_awvalid,\n    input                               m_axi_awready,\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_wid,\n    output [C_AXI_DATA_WIDTH-1:0]       m_axi_wdata,\n    output [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb,\n    output                              m_axi_wlast,\n    output [C_AXI_WUSER_WIDTH-1:0]      m_axi_wuser,\n    output                              m_axi_wvalid,\n    input                               m_axi_wready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_bid,\n    input [2-1:0]                       m_axi_bresp,\n    input [C_AXI_BUSER_WIDTH-1:0]       m_axi_buser,\n    input                               m_axi_bvalid,\n    output                              m_axi_bready,\n    \n    \n    // AXI Full/Lite Slave Read Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_arid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_araddr, \n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_arlen,\n    input [3-1:0]                       s_axi_arsize,\n    input [2-1:0]                       s_axi_arburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_arlock,\n    input [4-1:0]                       s_axi_arcache,\n    input [3-1:0]                       s_axi_arprot,\n    input [4-1:0]                       s_axi_arqos,\n    input [4-1:0]                       s_axi_arregion,\n    input [C_AXI_ARUSER_WIDTH-1:0]      s_axi_aruser,\n    input                               s_axi_arvalid,\n    output                              s_axi_arready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_rid,       \n    output [C_AXI_DATA_WIDTH-1:0]       s_axi_rdata, \n    output [2-1:0]                      s_axi_rresp,\n    output                              s_axi_rlast,\n    output [C_AXI_RUSER_WIDTH-1:0]      s_axi_ruser,\n    output                              s_axi_rvalid,\n    input                               s_axi_rready,\n    \n    \n    \n    // AXI Full/Lite Master Read Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_arid,        \n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,  \n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_arlen,\n    output [3-1:0]                      m_axi_arsize,\n    output [2-1:0]                      m_axi_arburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_arlock,\n    output [4-1:0]                      m_axi_arcache,\n    output [3-1:0]                      m_axi_arprot,\n    output [4-1:0]                      m_axi_arqos,\n    output [4-1:0]                      m_axi_arregion,\n    output [C_AXI_ARUSER_WIDTH-1:0]     m_axi_aruser,\n    output                              m_axi_arvalid,\n    input                               m_axi_arready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_rid,        \n    input [C_AXI_DATA_WIDTH-1:0]        m_axi_rdata,  \n    input [2-1:0]                       m_axi_rresp,\n    input                               m_axi_rlast,\n    input [C_AXI_RUSER_WIDTH-1:0]       m_axi_ruser,\n    input                               m_axi_rvalid,\n    output                              m_axi_rready,\n    \n    \n    // AXI Streaming Slave Signals (Write side)\n    input                               s_axis_tvalid,\n    output                              s_axis_tready,\n    input [C_AXIS_TDATA_WIDTH-1:0]      s_axis_tdata,\n    input [C_AXIS_TSTRB_WIDTH-1:0]      s_axis_tstrb,\n    input [C_AXIS_TKEEP_WIDTH-1:0]      s_axis_tkeep,\n    input                               s_axis_tlast,\n    input [C_AXIS_TID_WIDTH-1:0]        s_axis_tid,\n    input [C_AXIS_TDEST_WIDTH-1:0]      s_axis_tdest,\n    input [C_AXIS_TUSER_WIDTH-1:0]      s_axis_tuser,\n    \n    // AXI Streaming Master Signals (Read side)\n    output                              m_axis_tvalid,\n    input                               m_axis_tready,\n    output [C_AXIS_TDATA_WIDTH-1:0]     m_axis_tdata,\n    output [C_AXIS_TSTRB_WIDTH-1:0]     m_axis_tstrb,\n    output [C_AXIS_TKEEP_WIDTH-1:0]     m_axis_tkeep,\n    output                              m_axis_tlast,\n    output [C_AXIS_TID_WIDTH-1:0]       m_axis_tid,\n    output [C_AXIS_TDEST_WIDTH-1:0]     m_axis_tdest,\n    output [C_AXIS_TUSER_WIDTH-1:0]     m_axis_tuser,\n    \n           \n    \n    \n    // AXI Full/Lite Write Address Channel signals\n    input                               axi_aw_injectsbiterr,\n    input                               axi_aw_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_rd_data_count,\n    output                              axi_aw_sbiterr,\n    output                              axi_aw_dbiterr,\n    output                              axi_aw_overflow,\n    output                              axi_aw_underflow,\n    output                              axi_aw_prog_full,\n    output                              axi_aw_prog_empty,\n    \n    \n    // AXI Full/Lite Write Data Channel signals\n    input                               axi_w_injectsbiterr,\n    input                               axi_w_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_rd_data_count,\n    output                              axi_w_sbiterr,\n    output                              axi_w_dbiterr,\n    output                              axi_w_overflow,\n    output                              axi_w_underflow,\n    output                              axi_w_prog_full,\n    output                              axi_w_prog_empty,\n    \n    \n    // AXI Full/Lite Write Response Channel signals\n    input                               axi_b_injectsbiterr,\n    input                               axi_b_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_rd_data_count,\n    output                              axi_b_sbiterr,\n    output                              axi_b_dbiterr,\n    output                              axi_b_overflow,\n    output                              axi_b_underflow,\n    output                              axi_b_prog_full,\n    output                              axi_b_prog_empty,\n    \n    \n    \n    // AXI Full/Lite Read Address Channel signals\n    input                               axi_ar_injectsbiterr,\n    input                               axi_ar_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_rd_data_count,\n    output                              axi_ar_sbiterr,\n    output                              axi_ar_dbiterr,\n    output                              axi_ar_overflow,\n    output                              axi_ar_underflow,\n    output                              axi_ar_prog_full,\n    output                              axi_ar_prog_empty,\n\n    \n    // AXI Full/Lite Read Data Channel Signals\n    input                               axi_r_injectsbiterr,\n    input                               axi_r_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_rd_data_count,\n    output                              axi_r_sbiterr,\n    output                              axi_r_dbiterr,\n    output                              axi_r_overflow,\n    output                              axi_r_underflow,\n    output                              axi_r_prog_full,\n    output                              axi_r_prog_empty,\n\n    \n    // AXI Streaming FIFO Related Signals\n    input                               axis_injectsbiterr,\n    input                               axis_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_wr_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_rd_data_count,\n    output                              axis_sbiterr,\n    output                              axis_dbiterr,\n    output                              axis_overflow,\n    output                              axis_underflow,\n    output                              axis_prog_full,\n    output                              axis_prog_empty\n\n    );\n\n    wire                              BACKUP;\n    wire                              BACKUP_MARKER;\n    wire                              CLK;\n    wire                              RST;\n    wire                              SRST;\n    wire                              WR_CLK;\n    wire                              WR_RST;\n    wire                              RD_CLK;\n    wire                              RD_RST;\n    wire [C_DIN_WIDTH-1:0]            DIN;\n    wire                              WR_EN;\n    wire                              RD_EN;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_ASSERT;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_NEGATE;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_ASSERT;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_NEGATE;\n    wire                              INT_CLK;\n    wire                              INJECTDBITERR;\n    wire                              INJECTSBITERR;\n    wire                              SLEEP;\n    wire [C_DOUT_WIDTH-1:0]           DOUT;\n    wire                              FULL;\n    wire                              ALMOST_FULL;\n    wire                              WR_ACK;\n    wire                              OVERFLOW;\n    wire                              EMPTY;\n    wire                              ALMOST_EMPTY;\n    wire                              VALID;\n    wire                              UNDERFLOW;\n    wire [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT;\n    wire [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT;\n    wire                              PROG_FULL;\n    wire                              PROG_EMPTY;\n    wire                              SBITERR;\n    wire                              DBITERR;\n    wire                              WR_RST_BUSY;\n    wire                              RD_RST_BUSY;\n    wire                              M_ACLK;\n    wire                              S_ACLK;\n    wire                              S_ARESETN;\n    wire                              S_ACLK_EN;\n    wire                              M_ACLK_EN;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_AWLEN;\n    wire [3-1:0]                      S_AXI_AWSIZE;\n    wire [2-1:0]                      S_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_AWLOCK;\n    wire [4-1:0]                      S_AXI_AWCACHE;\n    wire [3-1:0]                      S_AXI_AWPROT;\n    wire [4-1:0]                      S_AXI_AWQOS;\n    wire [4-1:0]                      S_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     S_AXI_AWUSER;\n    wire                              S_AXI_AWVALID;\n    wire                              S_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     S_AXI_WSTRB;\n    wire                              S_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      S_AXI_WUSER;\n    wire                              S_AXI_WVALID;\n    wire                              S_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_BID;\n    wire [2-1:0]                      S_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      S_AXI_BUSER;\n    wire                              S_AXI_BVALID;\n    wire                              S_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_AWLEN;\n    wire [3-1:0]                      M_AXI_AWSIZE;\n    wire [2-1:0]                      M_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_AWLOCK;\n    wire [4-1:0]                      M_AXI_AWCACHE;\n    wire [3-1:0]                      M_AXI_AWPROT;\n    wire [4-1:0]                      M_AXI_AWQOS;\n    wire [4-1:0]                      M_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     M_AXI_AWUSER;\n    wire                              M_AXI_AWVALID;\n    wire                              M_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     M_AXI_WSTRB;\n    wire                              M_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      M_AXI_WUSER;\n    wire                              M_AXI_WVALID;\n    wire                              M_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_BID;\n    wire [2-1:0]                      M_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      M_AXI_BUSER;\n    wire                              M_AXI_BVALID;\n    wire                              M_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_ARID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_ARADDR; \n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_ARLEN;\n    wire [3-1:0]                      S_AXI_ARSIZE;\n    wire [2-1:0]                      S_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_ARLOCK;\n    wire [4-1:0]                      S_AXI_ARCACHE;\n    wire [3-1:0]                      S_AXI_ARPROT;\n    wire [4-1:0]                      S_AXI_ARQOS;\n    wire [4-1:0]                      S_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     S_AXI_ARUSER;\n    wire                              S_AXI_ARVALID;\n    wire                              S_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_RID;       \n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_RDATA; \n    wire [2-1:0]                      S_AXI_RRESP;\n    wire                              S_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      S_AXI_RUSER;\n    wire                              S_AXI_RVALID;\n    wire                              S_AXI_RREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_ARID;        \n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_ARADDR;  \n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_ARLEN;\n    wire [3-1:0]                      M_AXI_ARSIZE;\n    wire [2-1:0]                      M_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_ARLOCK;\n    wire [4-1:0]                      M_AXI_ARCACHE;\n    wire [3-1:0]                      M_AXI_ARPROT;\n    wire [4-1:0]                      M_AXI_ARQOS;\n    wire [4-1:0]                      M_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     M_AXI_ARUSER;\n    wire                              M_AXI_ARVALID;\n    wire                              M_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_RID;        \n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_RDATA;  \n    wire [2-1:0]                      M_AXI_RRESP;\n    wire                              M_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      M_AXI_RUSER;\n    wire                              M_AXI_RVALID;\n    wire                              M_AXI_RREADY;\n    wire                              S_AXIS_TVALID;\n    wire                              S_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     S_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     S_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     S_AXIS_TKEEP;\n    wire                              S_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       S_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     S_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     S_AXIS_TUSER;\n    wire                              M_AXIS_TVALID;\n    wire                              M_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     M_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     M_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     M_AXIS_TKEEP;\n    wire                              M_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       M_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     M_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     M_AXIS_TUSER;\n    wire                              AXI_AW_INJECTSBITERR;\n    wire                              AXI_AW_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_RD_DATA_COUNT;\n    wire                              AXI_AW_SBITERR;\n    wire                              AXI_AW_DBITERR;\n    wire                              AXI_AW_OVERFLOW;\n    wire                              AXI_AW_UNDERFLOW;\n    wire                              AXI_AW_PROG_FULL;\n    wire                              AXI_AW_PROG_EMPTY;\n    wire                              AXI_W_INJECTSBITERR;\n    wire                              AXI_W_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_RD_DATA_COUNT;\n    wire                              AXI_W_SBITERR;\n    wire                              AXI_W_DBITERR;\n    wire                              AXI_W_OVERFLOW;\n    wire                              AXI_W_UNDERFLOW;\n    wire                              AXI_W_PROG_FULL;\n    wire                              AXI_W_PROG_EMPTY;\n    wire                              AXI_B_INJECTSBITERR;\n    wire                              AXI_B_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_RD_DATA_COUNT;\n    wire                              AXI_B_SBITERR;\n    wire                              AXI_B_DBITERR;\n    wire                              AXI_B_OVERFLOW;\n    wire                              AXI_B_UNDERFLOW;\n    wire                              AXI_B_PROG_FULL;\n    wire                              AXI_B_PROG_EMPTY;\n    wire                              AXI_AR_INJECTSBITERR;\n    wire                              AXI_AR_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_RD_DATA_COUNT;\n    wire                              AXI_AR_SBITERR;\n    wire                              AXI_AR_DBITERR;\n    wire                              AXI_AR_OVERFLOW;\n    wire                              AXI_AR_UNDERFLOW;\n    wire                              AXI_AR_PROG_FULL;\n    wire                              AXI_AR_PROG_EMPTY;\n    wire                              AXI_R_INJECTSBITERR;\n    wire                              AXI_R_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_RD_DATA_COUNT;\n    wire                              AXI_R_SBITERR;\n    wire                              AXI_R_DBITERR;\n    wire                              AXI_R_OVERFLOW;\n    wire                              AXI_R_UNDERFLOW;\n    wire                              AXI_R_PROG_FULL;\n    wire                              AXI_R_PROG_EMPTY;\n    wire                              AXIS_INJECTSBITERR;\n    wire                              AXIS_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_RD_DATA_COUNT;\n    wire                              AXIS_SBITERR;\n    wire                              AXIS_DBITERR;\n    wire                              AXIS_OVERFLOW;\n    wire                              AXIS_UNDERFLOW;\n    wire                              AXIS_PROG_FULL;\n    wire                              AXIS_PROG_EMPTY;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count_in;\n    wire                              wr_rst_int;\n    wire                              rd_rst_int;\n    wire                              wr_rst_busy_o;\n    wire                              wr_rst_busy_ntve;\n    wire                              wr_rst_busy_axis;\n    wire                              wr_rst_busy_wach;\n    wire                              wr_rst_busy_wdch;\n    wire                              wr_rst_busy_wrch;\n    wire                              wr_rst_busy_rach;\n    wire                              wr_rst_busy_rdch;\n\n\n\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n\n\n\n    // Conventional FIFO Interface Signals\n    assign BACKUP                 = backup;\n    assign BACKUP_MARKER          = backup_marker;\n    assign CLK                    = clk;\n    assign RST                    = rst;\n    assign SRST                   = srst;\n    assign WR_CLK                 = wr_clk;\n    assign WR_RST                 = wr_rst;\n    assign RD_CLK                 = rd_clk;\n    assign RD_RST                 = rd_rst;\n    assign WR_EN                  = wr_en;\n    assign RD_EN                  = rd_en;\n    assign INT_CLK                = int_clk;\n    assign INJECTDBITERR          = injectdbiterr;\n    assign INJECTSBITERR          = injectsbiterr;\n    assign SLEEP                  = sleep;\n    assign full                   = FULL;\n    assign almost_full            = ALMOST_FULL;\n    assign wr_ack                 = WR_ACK;\n    assign overflow               = OVERFLOW;\n    assign empty                  = EMPTY;\n    assign almost_empty           = ALMOST_EMPTY;\n    assign valid                  = VALID;\n    assign underflow              = UNDERFLOW;\n    assign prog_full              = PROG_FULL;\n    assign prog_empty             = PROG_EMPTY;\n    assign sbiterr                = SBITERR;\n    assign dbiterr                = DBITERR;\n//    assign wr_rst_busy            = WR_RST_BUSY | wr_rst_busy_o;\n    assign wr_rst_busy            = wr_rst_busy_o;\n    assign rd_rst_busy            = RD_RST_BUSY;\n    assign M_ACLK                 = m_aclk;\n    assign S_ACLK                 = s_aclk;\n    assign S_ARESETN              = s_aresetn;\n    assign S_ACLK_EN              = s_aclk_en;\n    assign M_ACLK_EN              = m_aclk_en;\n    assign S_AXI_AWVALID          = s_axi_awvalid;\n    assign s_axi_awready          = S_AXI_AWREADY;\n    assign S_AXI_WLAST            = s_axi_wlast;\n    assign S_AXI_WVALID           = s_axi_wvalid;\n    assign s_axi_wready           = S_AXI_WREADY;\n    assign s_axi_bvalid           = S_AXI_BVALID;\n    assign S_AXI_BREADY           = s_axi_bready;\n    assign m_axi_awvalid          = M_AXI_AWVALID;\n    assign M_AXI_AWREADY          = m_axi_awready;\n    assign m_axi_wlast            = M_AXI_WLAST;\n    assign m_axi_wvalid           = M_AXI_WVALID;\n    assign M_AXI_WREADY           = m_axi_wready;\n    assign M_AXI_BVALID           = m_axi_bvalid;\n    assign m_axi_bready           = M_AXI_BREADY;\n    assign S_AXI_ARVALID          = s_axi_arvalid;\n    assign s_axi_arready          = S_AXI_ARREADY;\n    assign s_axi_rlast            = S_AXI_RLAST;\n    assign s_axi_rvalid           = S_AXI_RVALID;\n    assign S_AXI_RREADY           = s_axi_rready;\n    assign m_axi_arvalid          = M_AXI_ARVALID;\n    assign M_AXI_ARREADY          = m_axi_arready;\n    assign M_AXI_RLAST            = m_axi_rlast;\n    assign M_AXI_RVALID           = m_axi_rvalid;\n    assign m_axi_rready           = M_AXI_RREADY;\n    assign S_AXIS_TVALID          = s_axis_tvalid;\n    assign s_axis_tready          = S_AXIS_TREADY;\n    assign S_AXIS_TLAST           = s_axis_tlast;\n    assign m_axis_tvalid          = M_AXIS_TVALID;\n    assign M_AXIS_TREADY          = m_axis_tready;\n    assign m_axis_tlast           = M_AXIS_TLAST;\n    assign AXI_AW_INJECTSBITERR   = axi_aw_injectsbiterr;\n    assign AXI_AW_INJECTDBITERR   = axi_aw_injectdbiterr;\n    assign axi_aw_sbiterr         = AXI_AW_SBITERR;\n    assign axi_aw_dbiterr         = AXI_AW_DBITERR;\n    assign axi_aw_overflow        = AXI_AW_OVERFLOW;\n    assign axi_aw_underflow       = AXI_AW_UNDERFLOW;\n    assign axi_aw_prog_full       = AXI_AW_PROG_FULL;\n    assign axi_aw_prog_empty      = AXI_AW_PROG_EMPTY;\n    assign AXI_W_INJECTSBITERR    = axi_w_injectsbiterr;\n    assign AXI_W_INJECTDBITERR    = axi_w_injectdbiterr;\n    assign axi_w_sbiterr          = AXI_W_SBITERR;\n    assign axi_w_dbiterr          = AXI_W_DBITERR;\n    assign axi_w_overflow         = AXI_W_OVERFLOW;\n    assign axi_w_underflow        = AXI_W_UNDERFLOW;\n    assign axi_w_prog_full        = AXI_W_PROG_FULL;\n    assign axi_w_prog_empty       = AXI_W_PROG_EMPTY;\n    assign AXI_B_INJECTSBITERR    = axi_b_injectsbiterr;\n    assign AXI_B_INJECTDBITERR    = axi_b_injectdbiterr;\n    assign axi_b_sbiterr          = AXI_B_SBITERR;\n    assign axi_b_dbiterr          = AXI_B_DBITERR;\n    assign axi_b_overflow         = AXI_B_OVERFLOW;\n    assign axi_b_underflow        = AXI_B_UNDERFLOW;\n    assign axi_b_prog_full        = AXI_B_PROG_FULL;\n    assign axi_b_prog_empty       = AXI_B_PROG_EMPTY;\n    assign AXI_AR_INJECTSBITERR   = axi_ar_injectsbiterr;\n    assign AXI_AR_INJECTDBITERR   = axi_ar_injectdbiterr;\n    assign axi_ar_sbiterr         = AXI_AR_SBITERR;\n    assign axi_ar_dbiterr         = AXI_AR_DBITERR;\n    assign axi_ar_overflow        = AXI_AR_OVERFLOW;\n    assign axi_ar_underflow       = AXI_AR_UNDERFLOW;\n    assign axi_ar_prog_full       = AXI_AR_PROG_FULL;\n    assign axi_ar_prog_empty      = AXI_AR_PROG_EMPTY;\n    assign AXI_R_INJECTSBITERR    = axi_r_injectsbiterr;\n    assign AXI_R_INJECTDBITERR    = axi_r_injectdbiterr;\n    assign axi_r_sbiterr          = AXI_R_SBITERR;\n    assign axi_r_dbiterr          = AXI_R_DBITERR;\n    assign axi_r_overflow         = AXI_R_OVERFLOW;\n    assign axi_r_underflow        = AXI_R_UNDERFLOW;\n    assign axi_r_prog_full        = AXI_R_PROG_FULL;\n    assign axi_r_prog_empty       = AXI_R_PROG_EMPTY;\n    assign AXIS_INJECTSBITERR     = axis_injectsbiterr;\n    assign AXIS_INJECTDBITERR     = axis_injectdbiterr;\n    assign axis_sbiterr           = AXIS_SBITERR;\n    assign axis_dbiterr           = AXIS_DBITERR;\n    assign axis_overflow          = AXIS_OVERFLOW;\n    assign axis_underflow         = AXIS_UNDERFLOW;\n    assign axis_prog_full         = AXIS_PROG_FULL;\n    assign axis_prog_empty        = AXIS_PROG_EMPTY;\n\n\n    assign DIN                       = din;\n    assign PROG_EMPTY_THRESH         = prog_empty_thresh;\n    assign PROG_EMPTY_THRESH_ASSERT  = prog_empty_thresh_assert;\n    assign PROG_EMPTY_THRESH_NEGATE  = prog_empty_thresh_negate;\n    assign PROG_FULL_THRESH          = prog_full_thresh;\n    assign PROG_FULL_THRESH_ASSERT   = prog_full_thresh_assert;\n    assign PROG_FULL_THRESH_NEGATE   = prog_full_thresh_negate;\n    assign dout                      = DOUT;\n    assign data_count                = DATA_COUNT;\n    assign rd_data_count             = RD_DATA_COUNT;\n    assign wr_data_count             = WR_DATA_COUNT;\n    assign S_AXI_AWID                = s_axi_awid;\n    assign S_AXI_AWADDR              = s_axi_awaddr;\n    assign S_AXI_AWLEN               = s_axi_awlen;\n    assign S_AXI_AWSIZE              = s_axi_awsize;\n    assign S_AXI_AWBURST             = s_axi_awburst;\n    assign S_AXI_AWLOCK              = s_axi_awlock;\n    assign S_AXI_AWCACHE             = s_axi_awcache;\n    assign S_AXI_AWPROT              = s_axi_awprot;\n    assign S_AXI_AWQOS               = s_axi_awqos;\n    assign S_AXI_AWREGION            = s_axi_awregion;\n    assign S_AXI_AWUSER              = s_axi_awuser;\n    assign S_AXI_WID                 = s_axi_wid;\n    assign S_AXI_WDATA               = s_axi_wdata;\n    assign S_AXI_WSTRB               = s_axi_wstrb;\n    assign S_AXI_WUSER               = s_axi_wuser;\n    assign s_axi_bid                 = S_AXI_BID;\n    assign s_axi_bresp               = S_AXI_BRESP;\n    assign s_axi_buser               = S_AXI_BUSER;\n    assign m_axi_awid                = M_AXI_AWID;\n    assign m_axi_awaddr              = M_AXI_AWADDR;\n    assign m_axi_awlen               = M_AXI_AWLEN;\n    assign m_axi_awsize              = M_AXI_AWSIZE;\n    assign m_axi_awburst             = M_AXI_AWBURST;\n    assign m_axi_awlock              = M_AXI_AWLOCK;\n    assign m_axi_awcache             = M_AXI_AWCACHE;\n    assign m_axi_awprot              = M_AXI_AWPROT;\n    assign m_axi_awqos               = M_AXI_AWQOS;\n    assign m_axi_awregion            = M_AXI_AWREGION;\n    assign m_axi_awuser              = M_AXI_AWUSER;\n    assign m_axi_wid                 = M_AXI_WID;\n    assign m_axi_wdata               = M_AXI_WDATA;\n    assign m_axi_wstrb               = M_AXI_WSTRB;\n    assign m_axi_wuser               = M_AXI_WUSER;\n    assign M_AXI_BID                 = m_axi_bid;\n    assign M_AXI_BRESP               = m_axi_bresp;\n    assign M_AXI_BUSER               = m_axi_buser;\n    assign S_AXI_ARID                = s_axi_arid;\n    assign S_AXI_ARADDR              = s_axi_araddr; \n    assign S_AXI_ARLEN               = s_axi_arlen;\n    assign S_AXI_ARSIZE              = s_axi_arsize;\n    assign S_AXI_ARBURST             = s_axi_arburst;\n    assign S_AXI_ARLOCK              = s_axi_arlock;\n    assign S_AXI_ARCACHE             = s_axi_arcache;\n    assign S_AXI_ARPROT              = s_axi_arprot;\n    assign S_AXI_ARQOS               = s_axi_arqos;\n    assign S_AXI_ARREGION            = s_axi_arregion;\n    assign S_AXI_ARUSER              = s_axi_aruser;\n    assign s_axi_rid                 = S_AXI_RID;\n    assign s_axi_rdata               = S_AXI_RDATA;\n    assign s_axi_rresp               = S_AXI_RRESP;\n    assign s_axi_ruser               = S_AXI_RUSER;\n    assign m_axi_arid                = M_AXI_ARID;        \n    assign m_axi_araddr              = M_AXI_ARADDR;  \n    assign m_axi_arlen               = M_AXI_ARLEN;\n    assign m_axi_arsize              = M_AXI_ARSIZE;\n    assign m_axi_arburst             = M_AXI_ARBURST;\n    assign m_axi_arlock              = M_AXI_ARLOCK;\n    assign m_axi_arcache             = M_AXI_ARCACHE;\n    assign m_axi_arprot              = M_AXI_ARPROT;\n    assign m_axi_arqos               = M_AXI_ARQOS;\n    assign m_axi_arregion            = M_AXI_ARREGION;\n    assign m_axi_aruser              = M_AXI_ARUSER;\n    assign M_AXI_RID                 = m_axi_rid;        \n    assign M_AXI_RDATA               = m_axi_rdata;  \n    assign M_AXI_RRESP               = m_axi_rresp;\n    assign M_AXI_RUSER               = m_axi_ruser;\n    assign S_AXIS_TDATA              = s_axis_tdata;\n    assign S_AXIS_TSTRB              = s_axis_tstrb;\n    assign S_AXIS_TKEEP              = s_axis_tkeep;\n    assign S_AXIS_TID                = s_axis_tid;\n    assign S_AXIS_TDEST              = s_axis_tdest;\n    assign S_AXIS_TUSER              = s_axis_tuser;\n    assign m_axis_tdata              = M_AXIS_TDATA;\n    assign m_axis_tstrb              = M_AXIS_TSTRB;\n    assign m_axis_tkeep              = M_AXIS_TKEEP;\n    assign m_axis_tid                = M_AXIS_TID;\n    assign m_axis_tdest              = M_AXIS_TDEST;\n    assign m_axis_tuser              = M_AXIS_TUSER;\n    assign AXI_AW_PROG_FULL_THRESH   = axi_aw_prog_full_thresh;\n    assign AXI_AW_PROG_EMPTY_THRESH  = axi_aw_prog_empty_thresh;\n    assign axi_aw_data_count         = AXI_AW_DATA_COUNT;\n    assign axi_aw_wr_data_count      = AXI_AW_WR_DATA_COUNT;\n    assign axi_aw_rd_data_count      = AXI_AW_RD_DATA_COUNT;\n    assign AXI_W_PROG_FULL_THRESH    = axi_w_prog_full_thresh;\n    assign AXI_W_PROG_EMPTY_THRESH   = axi_w_prog_empty_thresh;\n    assign axi_w_data_count          = AXI_W_DATA_COUNT;\n    assign axi_w_wr_data_count       = AXI_W_WR_DATA_COUNT;\n    assign axi_w_rd_data_count       = AXI_W_RD_DATA_COUNT;\n    assign AXI_B_PROG_FULL_THRESH    = axi_b_prog_full_thresh;\n    assign AXI_B_PROG_EMPTY_THRESH   = axi_b_prog_empty_thresh;\n    assign axi_b_data_count          = AXI_B_DATA_COUNT;\n    assign axi_b_wr_data_count       = AXI_B_WR_DATA_COUNT;\n    assign axi_b_rd_data_count       = AXI_B_RD_DATA_COUNT;\n    assign AXI_AR_PROG_FULL_THRESH   = axi_ar_prog_full_thresh;\n    assign AXI_AR_PROG_EMPTY_THRESH  = axi_ar_prog_empty_thresh;\n    assign axi_ar_data_count         = AXI_AR_DATA_COUNT;\n    assign axi_ar_wr_data_count      = AXI_AR_WR_DATA_COUNT;\n    assign axi_ar_rd_data_count      = AXI_AR_RD_DATA_COUNT;\n    assign AXI_R_PROG_FULL_THRESH    = axi_r_prog_full_thresh;\n    assign AXI_R_PROG_EMPTY_THRESH   = axi_r_prog_empty_thresh;\n    assign axi_r_data_count          = AXI_R_DATA_COUNT;\n    assign axi_r_wr_data_count       = AXI_R_WR_DATA_COUNT;\n    assign axi_r_rd_data_count       = AXI_R_RD_DATA_COUNT;\n    assign AXIS_PROG_FULL_THRESH     = axis_prog_full_thresh;\n    assign AXIS_PROG_EMPTY_THRESH    = axis_prog_empty_thresh;\n    assign axis_data_count           = AXIS_DATA_COUNT;\n    assign axis_wr_data_count        = AXIS_WR_DATA_COUNT;\n    assign axis_rd_data_count        = AXIS_RD_DATA_COUNT;\n\n\n  generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_COMMON_CLOCK \t\t(C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DATA_COUNT_WIDTH\t\t(C_DATA_COUNT_WIDTH),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH),\n        .C_DOUT_RST_VAL\t\t\t(C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),\n        .C_DOUT_WIDTH\t\t\t(C_DOUT_WIDTH),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n        .C_HAS_ALMOST_EMPTY\t\t(C_HAS_ALMOST_EMPTY),\n        .C_HAS_ALMOST_FULL\t\t(C_HAS_ALMOST_FULL),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_DATA_COUNT\t\t(C_HAS_DATA_COUNT),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_HAS_RD_DATA_COUNT\t\t(C_HAS_RD_DATA_COUNT),\n        .C_HAS_RD_RST\t\t\t(C_HAS_RD_RST),\n        .C_HAS_RST\t\t\t(C_HAS_RST),\n        .C_HAS_SRST\t\t\t(C_HAS_SRST),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_HAS_VALID\t\t\t(C_HAS_VALID),\n        .C_HAS_WR_ACK\t\t\t(C_HAS_WR_ACK),\n        .C_HAS_WR_DATA_COUNT\t\t(C_HAS_WR_DATA_COUNT),\n        .C_HAS_WR_RST\t\t\t(C_HAS_WR_RST),\n        .C_IMPLEMENTATION_TYPE\t\t(C_IMPLEMENTATION_TYPE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_MEMORY_TYPE\t\t\t(C_MEMORY_TYPE),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n        .C_PRELOAD_LATENCY\t\t(C_PRELOAD_LATENCY),\n        .C_PRELOAD_REGS\t\t\t(C_PRELOAD_REGS),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL),\n        .C_PROG_EMPTY_THRESH_NEGATE_VAL\t(C_PROG_EMPTY_THRESH_NEGATE_VAL),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL),\n        .C_PROG_FULL_THRESH_NEGATE_VAL\t(C_PROG_FULL_THRESH_NEGATE_VAL),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_RD_DATA_COUNT_WIDTH),\n        .C_RD_DEPTH\t\t\t(C_RD_DEPTH),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_RD_PNTR_WIDTH\t\t(C_RD_PNTR_WIDTH),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n        .C_USE_ECC                      (C_USE_ECC),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_EN_SAFETY_CKT\t\t(C_EN_SAFETY_CKT),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_USE_FWFT_DATA_COUNT\t\t(C_USE_FWFT_DATA_COUNT),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_DATA_COUNT_WIDTH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (C_ENABLE_RST_SYNC),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE),\n        .C_AXI_TYPE                     (C_AXI_TYPE),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE)\n      )\n    fifo_generator_v13_2_5_conv_dut\n      (\n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .CLK                      (CLK),\n        .RST                      (RST),\n        .SRST                     (SRST),\n        .WR_CLK                   (WR_CLK),\n        .WR_RST                   (WR_RST),\n        .RD_CLK                   (RD_CLK),\n        .RD_RST                   (RD_RST),\n        .DIN                      (DIN),\n        .WR_EN                    (WR_EN),\n        .RD_EN                    (RD_EN),\n        .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),\n        .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),\n        .PROG_FULL_THRESH         (PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),\n        .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),\n        .INT_CLK                  (INT_CLK),\n        .INJECTDBITERR            (INJECTDBITERR), \n        .INJECTSBITERR            (INJECTSBITERR),\n  \n        .DOUT                     (DOUT),\n        .FULL                     (FULL),\n        .ALMOST_FULL              (ALMOST_FULL),\n        .WR_ACK                   (WR_ACK),\n        .OVERFLOW                 (OVERFLOW),\n        .EMPTY                    (EMPTY),\n        .ALMOST_EMPTY             (ALMOST_EMPTY),\n        .VALID                    (VALID),\n        .UNDERFLOW                (UNDERFLOW),\n        .DATA_COUNT               (DATA_COUNT),\n        .RD_DATA_COUNT            (RD_DATA_COUNT),\n        .WR_DATA_COUNT            (wr_data_count_in),\n        .PROG_FULL                (PROG_FULL),\n        .PROG_EMPTY               (PROG_EMPTY),\n        .SBITERR                  (SBITERR),\n        .DBITERR                  (DBITERR),\n        .wr_rst_busy_o            (wr_rst_busy_o),\n        .wr_rst_busy              (wr_rst_busy_i),\n        .rd_rst_busy              (rd_rst_busy),\n        .wr_rst_i_out             (wr_rst_int),\n        .rd_rst_i_out             (rd_rst_int)\n       );\n  end endgenerate\n\n\n\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n  localparam C_AXI_SIZE_WIDTH   = 3;\n  localparam C_AXI_BURST_WIDTH  = 2;\n  localparam C_AXI_CACHE_WIDTH  = 4;\n  localparam C_AXI_PROT_WIDTH   = 3;\n  localparam C_AXI_QOS_WIDTH    = 4;\n  localparam C_AXI_REGION_WIDTH = 4;\n  localparam C_AXI_BRESP_WIDTH  = 2;\n  localparam C_AXI_RRESP_WIDTH  = 2;\n\n  localparam IS_AXI_STREAMING  = C_INTERFACE_TYPE == 1 ? 1 : 0;\n  localparam TDATA_OFFSET      = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;\n  localparam TSTRB_OFFSET      = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;\n  localparam TKEEP_OFFSET      = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;\n  localparam TID_OFFSET        = C_HAS_AXIS_TID   == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;\n  localparam TDEST_OFFSET      = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;\n  localparam TUSER_OFFSET      = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;\n  localparam LOG_DEPTH_AXIS    = find_log2(C_WR_DEPTH_AXIS); \n  localparam LOG_WR_DEPTH      = find_log2(C_WR_DEPTH); \n\n\n  function [LOG_DEPTH_AXIS-1:0] bin2gray;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      begin\n         bin2gray = x ^ (x>>1);\n      end\n   endfunction\n\n  function [LOG_DEPTH_AXIS-1:0] gray2bin;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      integer                i;\n      begin\n         gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];\n         for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin\n            gray2bin[i] =  gray2bin[i+1] ^ x[i];\n         end\n      end\n   endfunction\n\nwire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;\nwire  [LOG_WR_DEPTH-1 : 0]  w_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;\nreg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;\nwire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;\nwire [LOG_WR_DEPTH : 0] r_inv_pad;\nwire [LOG_WR_DEPTH-1 : 0] d_cnt;\nreg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;\nreg adj_w_cnt_rd_pad_0 = 0;\nreg r_inv_pad_0 = 0;\n\n\n   genvar l;\n\n   generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (LOG_WR_DEPTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_int), \n         .CLK      (RD_CLK), \n         .DIN      (w_q[l-1]), \n         .DOUT     (w_q[l])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter\n    assign wr_eop_ad = WR_EN & !(FULL);\n    assign rd_eop_ad = RD_EN & !(EMPTY);\n\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt    <= 1'b0;\n      else if (wr_eop_ad)\n        w_cnt    <= w_cnt + 1;\n    end\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt_gc    <= 1'b0;\n      else \n        w_cnt_gc    <= bin2gray(w_cnt);\n    end\n\n\n    assign  w_q[0]  = w_cnt_gc;\n    assign  w_cnt_gc_asreg_last       = w_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        w_cnt_rd    <= 1'b0;\n      else \n        w_cnt_rd    <= gray2bin(w_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        r_cnt    <= 1'b0;\n      else if (rd_eop_ad)\n        r_cnt    <= r_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;\n   assign r_inv_pad[LOG_WR_DEPTH : 1]        = ~r_cnt;\n   assign adj_w_cnt_rd_pad[0]                = adj_w_cnt_rd_pad_0;\n   assign r_inv_pad[0]                       = r_inv_pad_0;\n\n\n  always @ ( rd_eop_ad )\n    begin\n      if (!rd_eop_ad) begin\n        adj_w_cnt_rd_pad_0    <= 1'b1;\n        r_inv_pad_0           <= 1'b1;\n      end else begin \n        adj_w_cnt_rd_pad_0    <= 1'b0;\n        r_inv_pad_0           <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        d_cnt_pad    <= 1'b0;\n      else \n        d_cnt_pad    <= adj_w_cnt_rd_pad + r_inv_pad ;\n    end\n\n   assign  d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;\n   assign  WR_DATA_COUNT = d_cnt;\n\n  end endgenerate // fifo_ic_adapter\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter\n   assign  WR_DATA_COUNT = wr_data_count_in;\n\n  end endgenerate // fifo_icn_adapter\n\n\n\n  wire                          inverted_reset = ~S_ARESETN;\n  wire                          axi_rs_rst;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_din          ;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_dout         ;\n  wire                          axis_full         ;\n  wire                          axis_almost_full  ;\n  wire                          axis_empty        ;\n  wire                          axis_s_axis_tready;\n  wire                          axis_m_axis_tvalid;\n  wire                          axis_wr_en        ;\n  wire                          axis_rd_en        ;\n  wire                          axis_we           ;\n  wire                          axis_re           ;\n  wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;\n  reg                           axis_pkt_read = 1'b0;\n  wire                          axis_rd_rst;\n  wire                          axis_wr_rst;\n\n  generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||\n               C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst\n      reg                           rst_d1 = 0        ;\n      reg                           rst_d2 = 0        ;\n      reg [3:0]                    axi_rst = 4'h0     ;\n      always @ (posedge inverted_reset or posedge S_ACLK) begin\n        if (inverted_reset) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          axi_rst        <= 4'hf;\n        end else begin\n          rst_d1         <= #`TCQ 1'b0;\n          rst_d2         <= #`TCQ rst_d1;\n          axi_rst        <= #`TCQ {axi_rst[2:0],1'b0};\n        end\n      end\n\n      assign axi_rs_rst = axi_rst[3];//rst_d2;\n  end endgenerate // gaxi_rs_rst\n\n  generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming\n\n    // Write protection when almost full or prog_full is high\n    assign axis_we    = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : \n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign axis_re    = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :\n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? axis_we & S_ACLK_EN : axis_we;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE               (C_INTERFACE_TYPE),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 2  || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_AXIS),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_AXIS),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),\n        .C_USE_ECC                      (C_USE_ECC_AXIS),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_AXIS),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_axis_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (axis_wr_en),\n        .RD_EN                    (axis_rd_en),\n        .PROG_FULL_THRESH         (AXIS_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXIS_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .INJECTDBITERR            (AXIS_INJECTDBITERR), \n        .INJECTSBITERR            (AXIS_INJECTSBITERR),\n  \n        .DIN                      (axis_din),\n        .DOUT                     (axis_dout),\n        .FULL                     (axis_full),\n        .EMPTY                    (axis_empty),\n        .ALMOST_FULL              (axis_almost_full),\n        .PROG_FULL                (AXIS_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXIS_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (AXIS_OVERFLOW),\n        .VALID                    (),\n        .UNDERFLOW                (AXIS_UNDERFLOW),\n        .DATA_COUNT               (axis_dc),\n        .RD_DATA_COUNT            (AXIS_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXIS_WR_DATA_COUNT),\n        .SBITERR                  (AXIS_SBITERR),\n        .DBITERR                  (AXIS_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_axis),\n        .rd_rst_busy              (rd_rst_busy_axis),\n        .wr_rst_i_out             (axis_wr_rst),\n        .rd_rst_i_out             (axis_rd_rst),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign axis_s_axis_tready    = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;\n    assign axis_m_axis_tvalid    = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;\n    assign S_AXIS_TREADY         = axis_s_axis_tready;\n    assign M_AXIS_TVALID         = axis_m_axis_tvalid;\n\n  end endgenerate // axi_streaming\n\n  wire axis_wr_eop;\n  reg  axis_wr_eop_d1 = 1'b0;\n  wire axis_rd_eop;\n  integer  axis_pkt_cnt;\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)\n        axis_pkt_read    <= 1'b0;\n      else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_wr_eop_d1    <= 1'b0;\n      else\n        axis_wr_eop_d1   <= axis_wr_eop;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_cnt    <= 0;\n      else if (axis_wr_eop_d1 && ~axis_rd_eop)\n        axis_pkt_cnt    <= axis_pkt_cnt + 1;\n      else if (axis_rd_eop && ~axis_wr_eop_d1)\n        axis_pkt_cnt    <= axis_pkt_cnt - 1;\n    end\n  end endgenerate // gaxis_pkt_fifo_cc\n\n\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;\nwire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;\nwire axis_rd_has_rst;\nwire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;\nwire  [LOG_DEPTH_AXIS-1 : 0]  wpkt_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;\nwire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;\nwire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;\nwire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;\nwire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;\nreg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;\nreg adj_axis_wpkt_cnt_rd_pad_0 = 0;\nreg rpkt_inv_pad_0 = 0;\nwire axis_af_rd ;\n\ngenerate if (C_HAS_RST == 1) begin : rst_blk_has\n  assign axis_rd_has_rst = axis_rd_rst;\nend endgenerate //rst_blk_has\n\ngenerate if (C_HAS_RST == 0) begin :rst_blk_no\n  assign axis_rd_has_rst = 1'b0;\nend endgenerate //rst_blk_no\n\n   genvar i;\n\n   generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (LOG_DEPTH_AXIS)\n        )\n     rd_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (wpkt_q[i-1]), \n         .DOUT     (wpkt_q[i])\n        );\n \n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (1)\n        )\n     wr_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (axis_af_q[i-1]), \n         .DOUT     (axis_af_q[i])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (diff_pkt_cnt == 1))\n        axis_pkt_read    <= 1'b0;\n      else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt    <= 1'b0;\n      else if (axis_wr_eop)\n        axis_wpkt_cnt    <= axis_wpkt_cnt + 1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt_gc    <= 1'b0;\n      else \n        axis_wpkt_cnt_gc    <= bin2gray(axis_wpkt_cnt);\n    end\n\n\n    assign  wpkt_q[0]  = axis_wpkt_cnt_gc;\n    assign  axis_wpkt_cnt_gc_asreg_last       = wpkt_q[C_SYNCHRONIZER_STAGE];\n    assign  axis_af_q[0]                      = axis_almost_full;\n    //assign  axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];\n    assign  axis_af_rd                        = axis_af_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_wpkt_cnt_rd    <= 1'b0;\n      else \n        axis_wpkt_cnt_rd    <= gray2bin(axis_wpkt_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_rpkt_cnt    <= 1'b0;\n      else if (axis_rd_eop)\n        axis_rpkt_cnt    <= axis_rpkt_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;\n   assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1]             = ~axis_rpkt_cnt;\n   assign adj_axis_wpkt_cnt_rd_pad[0]                                = adj_axis_wpkt_cnt_rd_pad_0;\n   assign rpkt_inv_pad[0]                                            = rpkt_inv_pad_0;\n\n\n  always @ ( axis_rd_eop )\n    begin\n      if (!axis_rd_eop) begin\n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b1;\n        rpkt_inv_pad_0                <= 1'b1;\n      end else begin \n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b0;\n        rpkt_inv_pad_0                <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        diff_pkt_cnt_pad    <= 1'b0;\n      else \n        diff_pkt_cnt_pad    <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;\n    end\n\n   assign  diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;\n\n\n\n\n\n   end endgenerate // gaxis_pkt_fifo_ic\n\n\n\n\n  // Generate the accurate data count for axi stream packet fifo configuration\n  reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_dc_pkt_fifo <= 0;\n      else if (axis_wr_en && (~axis_rd_en))\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;\n      else if (~axis_wr_en && axis_rd_en)\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;\n    end\n    assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;\n  end endgenerate // gdc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt\n    assign AXIS_DATA_COUNT = 0;\n  end endgenerate // gndc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc\n    assign AXIS_DATA_COUNT = axis_dc;\n  end endgenerate // gdc\n\n  // Register Slice for Write Address Channel\n  generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_AXIS),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_AXIS)\n            )\n    axis_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (axis_din),\n          .S_VALID                   (axis_wr_en),\n          .S_READY                   (S_AXIS_TREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (axis_dout),\n          .M_VALID                   (M_AXIS_TVALID),\n          .M_READY                   (axis_rd_en)\n          );\n  end endgenerate // gaxis_reg_slice\n\n\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata\n    assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;\n    assign M_AXIS_TDATA   = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb\n    assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;\n    assign M_AXIS_TSTRB   = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep\n    assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;\n    assign M_AXIS_TKEEP   = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid\n    assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;\n    assign M_AXIS_TID     = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest\n    assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;\n    assign M_AXIS_TDEST   = axis_dout[TID_OFFSET-1:TDEST_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser\n    assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;\n    assign M_AXIS_TUSER   = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast\n    assign axis_din[0] = S_AXIS_TLAST;\n    assign M_AXIS_TLAST   = axis_dout[0];\n  end endgenerate\n\n  //###########################################################################\n  //  AXI FULL Write Channel (axi_write_channel)\n  //###########################################################################\n\n  localparam IS_AXI_FULL       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;\n  localparam IS_AXI_LITE       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;\n\n  localparam IS_AXI_FULL_WACH  = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WDCH  = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WRCH  = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RACH  = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RDCH  = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_AXI_LITE_WACH  = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WDCH  = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WRCH  = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RACH  = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RDCH  = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_WR_ADDR_CH     = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;\n  localparam IS_WR_DATA_CH     = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;\n  localparam IS_WR_RESP_CH     = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;\n  localparam IS_RD_ADDR_CH     = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;\n  localparam IS_RD_DATA_CH     = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;\n\n  localparam AWID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;\n  localparam AWADDR_OFFSET     = AWID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam AWLEN_OFFSET      = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;\n  localparam AWSIZE_OFFSET     = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;\n  localparam AWBURST_OFFSET    = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;\n  localparam AWLOCK_OFFSET     = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;\n  localparam AWCACHE_OFFSET    = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;\n  localparam AWPROT_OFFSET     = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam AWQOS_OFFSET      = AWPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam AWREGION_OFFSET   = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;\n  localparam AWUSER_OFFSET     = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;\n\n  localparam WID_OFFSET        = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;\n  localparam WDATA_OFFSET      = WID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam WSTRB_OFFSET      = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;\n  localparam WUSER_OFFSET      = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;\n\n  localparam BID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;\n  localparam BRESP_OFFSET      = BID_OFFSET - C_AXI_BRESP_WIDTH;\n  localparam BUSER_OFFSET      = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;\n\n\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_din          ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout         ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout_pkt     ;\n  wire                          wach_full         ;\n  wire                          wach_almost_full  ;\n  wire                          wach_prog_full    ;\n  wire                          wach_empty        ;\n  wire                          wach_almost_empty ;\n  wire                          wach_prog_empty   ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_din          ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_dout         ;\n  wire                          wdch_full         ;\n  wire                          wdch_almost_full  ;\n  wire                          wdch_prog_full    ;\n  wire                          wdch_empty        ;\n  wire                          wdch_almost_empty ;\n  wire                          wdch_prog_empty   ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_din          ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_dout         ;\n  wire                          wrch_full         ;\n  wire                          wrch_almost_full  ;\n  wire                          wrch_prog_full    ;\n  wire                          wrch_empty        ;\n  wire                          wrch_almost_empty ;\n  wire                          wrch_prog_empty   ;\n  wire                          axi_aw_underflow_i;\n  wire                          axi_w_underflow_i ;\n  wire                          axi_b_underflow_i ;\n  wire                          axi_aw_overflow_i ;\n  wire                          axi_w_overflow_i  ;\n  wire                          axi_b_overflow_i  ;\n  wire                          axi_wr_underflow_i;\n  wire                          axi_wr_overflow_i ;\n  wire                          wach_s_axi_awready;\n  wire                          wach_m_axi_awvalid;\n  wire                          wach_wr_en        ;\n  wire                          wach_rd_en        ;\n  wire                          wdch_s_axi_wready ;\n  wire                          wdch_m_axi_wvalid ;\n  wire                          wdch_wr_en        ;\n  wire                          wdch_rd_en        ;\n  wire                          wrch_s_axi_bvalid ;\n  wire                          wrch_m_axi_bready ;\n  wire                          wrch_wr_en        ;\n  wire                          wrch_rd_en        ;\n  wire                          txn_count_up      ;\n  wire                          txn_count_down    ;\n  wire                          awvalid_en        ;\n  wire                          awvalid_pkt       ;\n  wire                          awready_pkt       ;\n  integer                       wr_pkt_count      ;\n  wire                          wach_we           ;\n  wire                          wach_re           ;\n  wire                          wdch_we           ;\n  wire                          wdch_re           ;\n  wire                          wrch_we           ;\n  wire                          wrch_re           ;\n\n  generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel\n    // Write protection when almost full or prog_full is high\n    assign wach_we    = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wach_re    = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        wach_m_axi_awvalid & awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY && wach_m_axi_awvalid :\n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY : 1'b0;\n    assign wach_wr_en = (C_HAS_SLAVE_CE == 1)  ? wach_we & S_ACLK_EN : wach_we;\n    assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 2  || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),\n        .C_USE_ECC                      (C_USE_ECC_WACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wach_wr_en),\n        .RD_EN                    (wach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AW_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AW_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AW_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AW_INJECTSBITERR),\n  \n        .DIN                      (wach_din),\n        .DOUT                     (wach_dout_pkt),\n        .FULL                     (wach_full),\n        .EMPTY                    (wach_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_AW_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_AW_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_aw_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_aw_underflow_i),\n        .DATA_COUNT               (AXI_AW_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AW_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AW_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AW_SBITERR),\n        .DBITERR                  (AXI_AW_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wach),\n        .rd_rst_busy              (rd_rst_busy_wach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wach_s_axi_awready    = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;\n    assign wach_m_axi_awvalid   = ~wach_empty;\n    assign S_AXI_AWREADY        = wach_s_axi_awready;\n\n    assign AXI_AW_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;\n    assign AXI_AW_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_aw_overflow_i  : 0;\n\n  end endgenerate // axi_write_address_channel\n\n  // Register Slice for Write Address Channel\n  generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WACH)\n            )\n    wach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_din),\n          .S_VALID                   (S_AXI_AWVALID),\n          .S_READY                   (S_AXI_AWREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n  end endgenerate // gwach_reg_slice\n  \n  generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (1)\n            )\n    wach_pkt_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_dout_pkt),\n          .S_VALID                   (awvalid_pkt),\n          .S_READY                   (awready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n\n    assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;\n\n    assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; \n    assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset == 1) begin\n\twr_pkt_count <= 0;\n      end else begin\n\tif(txn_count_up == 1 && txn_count_down == 0) begin\n\t  wr_pkt_count <= wr_pkt_count + 1;\n\tend else if(txn_count_up == 0 && txn_count_down == 1) begin\n\t  wr_pkt_count <= wr_pkt_count - 1;\n\tend\n      end\n    end //Always end\n    assign awvalid_en = (wr_pkt_count > 0)?1:0;\n  end endgenerate\n  \n  generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr\n    assign awvalid_en    = 1;    \n    assign wach_dout     = wach_dout_pkt;\n    assign M_AXI_AWVALID = wach_m_axi_awvalid;\n  end\n  endgenerate\n\n\n\n  generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel\n    // Write protection when almost full or prog_full is high\n    assign wdch_we    = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wdch_re    = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;\n    assign wdch_wr_en = (C_HAS_SLAVE_CE == 1)  ? wdch_we & S_ACLK_EN : wdch_we;\n    assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;\n\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 2  || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),\n        .C_USE_ECC                      (C_USE_ECC_WDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wdch_wr_en),\n        .RD_EN                    (wdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_W_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_W_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_W_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_W_INJECTSBITERR),\n  \n        .DIN                      (wdch_din),\n        .DOUT                     (wdch_dout),\n        .FULL                     (wdch_full),\n        .EMPTY                    (wdch_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_W_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_W_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_w_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_w_underflow_i),\n        .DATA_COUNT               (AXI_W_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_W_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_W_WR_DATA_COUNT),\n        .SBITERR                  (AXI_W_SBITERR),\n        .DBITERR                  (AXI_W_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wdch),\n        .rd_rst_busy              (rd_rst_busy_wdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wdch_s_axi_wready     = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;\n    assign wdch_m_axi_wvalid = ~wdch_empty;\n    assign S_AXI_WREADY      = wdch_s_axi_wready;\n    assign M_AXI_WVALID      = wdch_m_axi_wvalid;\n\n    assign AXI_W_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i  : 0;\n    assign AXI_W_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_w_overflow_i   : 0;\n\n  end endgenerate // axi_write_data_channel\n\n  // Register Slice for Write Data Channel\n  generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WDCH)\n            )\n    wdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wdch_din),\n          .S_VALID                   (S_AXI_WVALID),\n          .S_READY                   (S_AXI_WREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wdch_dout),\n          .M_VALID                   (M_AXI_WVALID),\n          .M_READY                   (M_AXI_WREADY)\n          );\n  end endgenerate // gwdch_reg_slice\n\n  generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel\n    // Write protection when almost full or prog_full is high\n    assign wrch_we    = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wrch_re    = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;\n    assign wrch_wr_en = (C_HAS_MASTER_CE == 1)  ? wrch_we & M_ACLK_EN : wrch_we;\n    assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 2  || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WRCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WRCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),\n        .C_USE_ECC                      (C_USE_ECC_WRCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WRCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WRCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wrch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wrch_wr_en),\n        .RD_EN                    (wrch_rd_en),\n        .PROG_FULL_THRESH         (AXI_B_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_B_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .INJECTDBITERR            (AXI_B_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_B_INJECTSBITERR),\n  \n        .DIN                      (wrch_din),\n        .DOUT                     (wrch_dout),\n        .FULL                     (wrch_full),\n        .EMPTY                    (wrch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_B_PROG_FULL),\n        .PROG_EMPTY               (AXI_B_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_b_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_b_underflow_i),\n        .DATA_COUNT               (AXI_B_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_B_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_B_WR_DATA_COUNT),\n        .SBITERR                  (AXI_B_SBITERR),\n        .DBITERR                  (AXI_B_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wrch),\n        .rd_rst_busy              (rd_rst_busy_wrch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wrch_s_axi_bvalid = ~wrch_empty;\n    assign wrch_m_axi_bready     = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;\n    assign S_AXI_BVALID      = wrch_s_axi_bvalid;\n    assign M_AXI_BREADY      = wrch_m_axi_bready;\n\n    assign AXI_B_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i  : 0;\n    assign AXI_B_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_b_overflow_i   : 0;\n  end endgenerate // axi_write_resp_channel\n\n  // Register Slice for Write Response Channel\n  generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WRCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WRCH)\n            )\n    wrch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wrch_din),\n          .S_VALID                   (M_AXI_BVALID),\n          .S_READY                   (M_AXI_BREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wrch_dout),\n          .M_VALID                   (S_AXI_BVALID),\n          .M_READY                   (S_AXI_BREADY)\n          );\n  end endgenerate // gwrch_reg_slice\n\n\n    assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW  == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;\n    assign axi_wr_overflow_i  = C_USE_COMMON_OVERFLOW   == 1 ? (axi_aw_overflow_i  || axi_w_overflow_i  || axi_b_overflow_i)  : 0;\n\n  generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output\n    assign M_AXI_AWADDR    = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];    \n    assign M_AXI_AWLEN     = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];    \n    assign M_AXI_AWSIZE    = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];    \n    assign M_AXI_AWBURST   = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];    \n    assign M_AXI_AWLOCK    = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];    \n    assign M_AXI_AWCACHE   = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];    \n    assign M_AXI_AWQOS     = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];    \n    assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET]    = S_AXI_AWADDR;\n    assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET]   = S_AXI_AWLEN;\n    assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET]   = S_AXI_AWSIZE;\n    assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;\n    assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;\n    assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;\n    assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;\n    assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET]   = S_AXI_AWQOS;\n  end endgenerate // axi_wach_output\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion\n    assign M_AXI_AWREGION  = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];    \n  end endgenerate // axi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion\n    assign M_AXI_AWREGION  = 0;    \n  end endgenerate // naxi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser\n    assign M_AXI_AWUSER  = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];    \n  end endgenerate // axi_awuser\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser\n    assign M_AXI_AWUSER  = 0;    \n  end endgenerate // naxi_awuser\n\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid\n    assign M_AXI_AWID      = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];\n  end endgenerate //axi_awid\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid\n    assign M_AXI_AWID      = 0;\n  end endgenerate //naxi_awid\n\n  generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output\n    assign M_AXI_WDATA     = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n    assign M_AXI_WLAST     = wdch_dout[0];\n    assign wdch_din[WID_OFFSET-1:WDATA_OFFSET]   = S_AXI_WDATA;\n    assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;\n    assign wdch_din[0]   = S_AXI_WLAST;\n  end endgenerate // axi_wdch_output\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin\n    assign M_AXI_WID       = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];\n  end endgenerate\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin\n    assign M_AXI_WID       = 0;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin\n    assign M_AXI_WUSER     = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];    \n  end endgenerate\n  generate if (C_HAS_AXI_WUSER == 0) begin\n    assign M_AXI_WUSER       = 0;\n  end endgenerate\n\n  generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output\n    assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; \n    assign wrch_din[BID_OFFSET-1:BRESP_OFFSET]   = M_AXI_BRESP;\n  end endgenerate // axi_wrch_output\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser\n    assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];\n  end endgenerate // axi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser\n    assign S_AXI_BUSER = 0;\n  end endgenerate // naxi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid\n    assign S_AXI_BID   =  wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];\n  end endgenerate // axi_bid\n  \n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid\n    assign S_AXI_BID   =  0 ;\n  end endgenerate // naxi_bid  \n\n\n  generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1\n    assign wach_din        = {S_AXI_AWADDR, S_AXI_AWPROT};\n    assign M_AXI_AWADDR    = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];    \n  end endgenerate // axi_wach_output1\n\n  generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1\n    assign wdch_din        = {S_AXI_WDATA, S_AXI_WSTRB};\n    assign M_AXI_WDATA     = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n  end endgenerate // axi_wdch_output1\n\n  generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1\n    assign wrch_din        = M_AXI_BRESP;\n    assign S_AXI_BRESP     = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; \n  end endgenerate // axi_wrch_output1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1\n    assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET]     = S_AXI_AWUSER;\n  end endgenerate // gwach_din1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2\n    assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET]     = S_AXI_AWID;\n  end endgenerate // gwach_din2\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3\n    assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET]     = S_AXI_AWREGION;\n  end endgenerate // gwach_din3\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1\n    assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;\n  end endgenerate // gwdch_din1\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2\n    assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;\n  end endgenerate // gwdch_din2\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1\n    assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET]    = M_AXI_BUSER;\n  end endgenerate // gwrch_din1\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2\n    assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET]    = M_AXI_BID;\n  end endgenerate // gwrch_din2\n\n  //end of  axi_write_channel\n\n  //###########################################################################\n  //  AXI FULL Read Channel (axi_read_channel)\n  //###########################################################################\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_din            ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout           ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout_pkt       ;\n  wire                               rach_full           ;\n  wire                               rach_almost_full    ;\n  wire                               rach_prog_full      ;\n  wire                               rach_empty          ;\n  wire                               rach_almost_empty   ;\n  wire                               rach_prog_empty     ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_din            ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_dout           ;\n  wire                               rdch_full           ;\n  wire                               rdch_almost_full    ;\n  wire                               rdch_prog_full      ;\n  wire                               rdch_empty          ;\n  wire                               rdch_almost_empty   ;\n  wire                               rdch_prog_empty     ;\n  wire                               axi_ar_underflow_i  ;\n  wire                               axi_r_underflow_i   ;\n  wire                               axi_ar_overflow_i   ;\n  wire                               axi_r_overflow_i    ;\n  wire                               axi_rd_underflow_i  ;\n  wire                               axi_rd_overflow_i   ;\n  wire                               rach_s_axi_arready  ;\n  wire                               rach_m_axi_arvalid  ;\n  wire                               rach_wr_en          ;\n  wire                               rach_rd_en          ;\n  wire                               rdch_m_axi_rready   ;\n  wire                               rdch_s_axi_rvalid   ;\n  wire                               rdch_wr_en          ;\n  wire                               rdch_rd_en          ;\n  wire                               arvalid_pkt         ;\n  wire                               arready_pkt         ;\n  wire                               arvalid_en          ;\n  wire                               rdch_rd_ok          ;\n  wire                               accept_next_pkt     ;\n  integer                            rdch_free_space     ;\n  integer                            rdch_commited_space ;\n  wire                               rach_we             ;\n  wire                               rach_re             ;\n  wire                               rdch_we             ;\n  wire                               rdch_re             ;\n\n  localparam ARID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;\n  localparam ARADDR_OFFSET     = ARID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam ARLEN_OFFSET      = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;\n  localparam ARSIZE_OFFSET     = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;\n  localparam ARBURST_OFFSET    = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;\n  localparam ARLOCK_OFFSET     = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;\n  localparam ARCACHE_OFFSET    = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;\n  localparam ARPROT_OFFSET     = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam ARQOS_OFFSET      = ARPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam ARREGION_OFFSET   = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;\n  localparam ARUSER_OFFSET     = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;\n\n  localparam RID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;\n  localparam RDATA_OFFSET      = RID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam RRESP_OFFSET      = RDATA_OFFSET - C_AXI_RRESP_WIDTH;\n  localparam RUSER_OFFSET      = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;\n\n\n  generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rach_we    = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;\n\n    // Read protection when almost empty or prog_empty is high\n//    assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;\n    assign rach_re    = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        rach_m_axi_arvalid & arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY && rach_m_axi_arvalid :\n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY : 1'b0;\n    assign rach_wr_en = (C_HAS_SLAVE_CE == 1)  ? rach_we & S_ACLK_EN : rach_we;\n    assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;\n\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 2  || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),\n        .C_USE_ECC                      (C_USE_ECC_RACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_rach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rach_wr_en),\n        .RD_EN                    (rach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AR_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AR_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AR_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AR_INJECTSBITERR),\n  \n        .DIN                      (rach_din),\n        .DOUT                     (rach_dout_pkt),\n        .FULL                     (rach_full),\n        .EMPTY                    (rach_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_AR_PROG_FULL),\n        .PROG_EMPTY               (AXI_AR_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_ar_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_ar_underflow_i),\n        .DATA_COUNT               (AXI_AR_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AR_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AR_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AR_SBITERR),\n        .DBITERR                  (AXI_AR_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rach),\n        .rd_rst_busy              (rd_rst_busy_rach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rach_s_axi_arready    = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;\n    assign rach_m_axi_arvalid = ~rach_empty;\n    assign S_AXI_ARREADY      = rach_s_axi_arready;\n\n    assign AXI_AR_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;\n    assign AXI_AR_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_ar_overflow_i  : 0;\n\n  end endgenerate // axi_read_addr_channel\n\n  // Register Slice for Read Address Channel\n  generate if (C_RACH_TYPE == 1) begin : grach_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RACH)\n            )\n    rach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_din),\n          .S_VALID                   (S_AXI_ARVALID),\n          .S_READY                   (S_AXI_ARREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice\n\n  // Register Slice for Read Address Channel for MM Packet FIFO\n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (1)\n            )\n    reg_slice_mm_pkt_fifo_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_dout_pkt),\n          .S_VALID                   (arvalid_pkt),\n          .S_READY                   (arready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice_mm_pkt_fifo\n\n  \n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid\n    assign M_AXI_ARVALID      = rach_m_axi_arvalid;\n    assign rach_dout          = rach_dout_pkt;\n  end endgenerate // grach_m_axi_arvalid\n  \n  \n  generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd\n    assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;\n    assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;\n    assign accept_next_pkt  = rach_m_axi_arvalid && arready_pkt && arvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset) begin\n\trdch_commited_space <= 0;\n      end else begin\n\tif(rdch_rd_ok && !accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space-1;\n\tend else if(!rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);\n\tend else if(rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);\n\tend\n      end\n    end //Always end\n\n    always@(*) begin\n      rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));\n    end\n\n    assign arvalid_en = (rdch_free_space >= 0)?1:0;\n  end\n  endgenerate\n  \n  generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd\n    assign arvalid_en = 1;    \n  end\n  endgenerate\n\n  generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rdch_we    = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready  & M_AXI_RVALID : M_AXI_RVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign rdch_re    = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid  & S_AXI_RREADY : S_AXI_RREADY;\n    assign rdch_wr_en = (C_HAS_MASTER_CE == 1)  ? rdch_we & M_ACLK_EN : rdch_we;\n    assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 2  || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),\n        .C_USE_ECC                      (C_USE_ECC_RDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_RDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_rdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rdch_wr_en),\n        .RD_EN                    (rdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_R_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_R_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_R_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_R_INJECTSBITERR),\n  \n        .DIN                      (rdch_din),\n        .DOUT                     (rdch_dout),\n        .FULL                     (rdch_full),\n        .EMPTY                    (rdch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_R_PROG_FULL),\n        .PROG_EMPTY               (AXI_R_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_r_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_r_underflow_i),\n        .DATA_COUNT               (AXI_R_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_R_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_R_WR_DATA_COUNT),\n        .SBITERR                  (AXI_R_SBITERR),\n        .DBITERR                  (AXI_R_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rdch),\n        .rd_rst_busy              (rd_rst_busy_rdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rdch_s_axi_rvalid = ~rdch_empty;\n    assign rdch_m_axi_rready     = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;\n    assign S_AXI_RVALID      = rdch_s_axi_rvalid;\n    assign M_AXI_RREADY      = rdch_m_axi_rready;\n\n    assign AXI_R_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i  : 0;\n    assign AXI_R_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_r_overflow_i   : 0;\n\n  end endgenerate //axi_read_data_channel\n\n  // Register Slice for read Data Channel\n  generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RDCH)\n            )\n    rdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rdch_din),\n          .S_VALID                   (M_AXI_RVALID),\n          .S_READY                   (M_AXI_RREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rdch_dout),\n          .M_VALID                   (S_AXI_RVALID),\n          .M_READY                   (S_AXI_RREADY)\n          );\n  end endgenerate // grdch_reg_slice\n\n\n    assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;\n    assign axi_rd_overflow_i  = C_USE_COMMON_OVERFLOW  == 1 ? (axi_ar_overflow_i  || axi_r_overflow_i) : 0;\n\n\n  generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output\n    assign M_AXI_ARADDR    = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];    \n    assign M_AXI_ARLEN     = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];    \n    assign M_AXI_ARSIZE    = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];    \n    assign M_AXI_ARBURST   = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];    \n    assign M_AXI_ARLOCK    = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];    \n    assign M_AXI_ARCACHE   = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];    \n    assign M_AXI_ARPROT    = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];    \n    assign M_AXI_ARQOS     = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];    \n    assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET]    = S_AXI_ARADDR;\n    assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET]   = S_AXI_ARLEN;\n    assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET]   = S_AXI_ARSIZE;\n    assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;\n    assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;\n    assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;\n    assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;\n    assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET]   = S_AXI_ARQOS;\n  end endgenerate // axi_full_rach_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion\n    assign M_AXI_ARREGION  = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];    \n  end endgenerate // axi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion\n    assign M_AXI_ARREGION  = 0;    \n  end endgenerate // naxi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser\n    assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];    \n  end endgenerate // axi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser\n    assign M_AXI_ARUSER = 0;    \n  end endgenerate // naxi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid\n    assign M_AXI_ARID      = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];\n  end endgenerate // axi_arid\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid\n    assign M_AXI_ARID      = 0;\n  end endgenerate // naxi_arid\n\n  generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output\n    assign S_AXI_RDATA     = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];\n    assign S_AXI_RRESP     = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n    assign S_AXI_RLAST     = rdch_dout[0];\n    assign rdch_din[RID_OFFSET-1:RDATA_OFFSET]   = M_AXI_RDATA;\n    assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;\n    assign rdch_din[0] = M_AXI_RLAST;\n  end endgenerate // axi_full_rdch_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output\n    assign S_AXI_RUSER     = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];\n  end endgenerate // axi_full_ruser_output\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output\n    assign S_AXI_RUSER     =  0;\n  end endgenerate // axi_full_nruser_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid\n    assign S_AXI_RID       = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];\n  end endgenerate // axi_rid\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid\n    assign S_AXI_RID       = 0;\n  end endgenerate // naxi_rid\n\n  generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1\n    assign rach_din      = {S_AXI_ARADDR, S_AXI_ARPROT};\n    assign M_AXI_ARADDR  = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];\n    assign M_AXI_ARPROT  = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];\n  end endgenerate // axi_lite_rach_output\n\n  generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1\n    assign rdch_din      = {M_AXI_RDATA, M_AXI_RRESP};\n    assign S_AXI_RDATA   = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];\n    assign S_AXI_RRESP   = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n  end endgenerate // axi_lite_rdch_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1\n    assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET]     = S_AXI_ARUSER;\n  end endgenerate // grach_din1\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2\n    assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET]     = S_AXI_ARID;\n  end endgenerate // grach_din2\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin\n    assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1\n    assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET]     = M_AXI_RUSER;\n  end endgenerate // grdch_din1\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2\n    assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;\n  end endgenerate // grdch_din2\n\n  //end of axi_read_channel\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf\n    assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :\n                       (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :\n                       (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;\n  end endgenerate // gaxi_comm_uf\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of\n    assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :\n                      (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :\n                      (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;\n  end endgenerate // gaxi_comm_of\n  \n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  // Pass Through Logic or Wiring Logic\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  \n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Write Address Channel\n  generate if (C_WACH_TYPE == 2) begin : gwach_pass_through\n    assign M_AXI_AWID      = S_AXI_AWID;\n    assign M_AXI_AWADDR    = S_AXI_AWADDR;\n    assign M_AXI_AWLEN     = S_AXI_AWLEN;\n    assign M_AXI_AWSIZE    = S_AXI_AWSIZE;\n    assign M_AXI_AWBURST   = S_AXI_AWBURST;\n    assign M_AXI_AWLOCK    = S_AXI_AWLOCK;\n    assign M_AXI_AWCACHE   = S_AXI_AWCACHE;\n    assign M_AXI_AWPROT    = S_AXI_AWPROT;\n    assign M_AXI_AWQOS     = S_AXI_AWQOS;\n    assign M_AXI_AWREGION  = S_AXI_AWREGION;\n    assign M_AXI_AWUSER    = S_AXI_AWUSER;\n    assign S_AXI_AWREADY   = M_AXI_AWREADY;\n    assign M_AXI_AWVALID   = S_AXI_AWVALID;\n  end endgenerate // gwach_pass_through;\n\n  // Wiring logic for Write Data Channel\n  generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through\n    assign M_AXI_WID       = S_AXI_WID;\n    assign M_AXI_WDATA     = S_AXI_WDATA;\n    assign M_AXI_WSTRB     = S_AXI_WSTRB;\n    assign M_AXI_WLAST     = S_AXI_WLAST;\n    assign M_AXI_WUSER     = S_AXI_WUSER;\n    assign S_AXI_WREADY    = M_AXI_WREADY;\n    assign M_AXI_WVALID    = S_AXI_WVALID;\n  end endgenerate // gwdch_pass_through;\n\n  // Wiring logic for Write Response Channel\n  generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through\n    assign S_AXI_BID       = M_AXI_BID;\n    assign S_AXI_BRESP     = M_AXI_BRESP;\n    assign S_AXI_BUSER     = M_AXI_BUSER;\n    assign M_AXI_BREADY    = S_AXI_BREADY;\n    assign S_AXI_BVALID    = M_AXI_BVALID;\n  end endgenerate // gwrch_pass_through;\n\n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Read Address Channel\n  generate if (C_RACH_TYPE == 2) begin : grach_pass_through\n    assign M_AXI_ARID      = S_AXI_ARID;\n    assign M_AXI_ARADDR    = S_AXI_ARADDR;\n    assign M_AXI_ARLEN     = S_AXI_ARLEN;\n    assign M_AXI_ARSIZE    = S_AXI_ARSIZE;\n    assign M_AXI_ARBURST   = S_AXI_ARBURST;\n    assign M_AXI_ARLOCK    = S_AXI_ARLOCK;\n    assign M_AXI_ARCACHE   = S_AXI_ARCACHE;\n    assign M_AXI_ARPROT    = S_AXI_ARPROT;\n    assign M_AXI_ARQOS     = S_AXI_ARQOS;\n    assign M_AXI_ARREGION  = S_AXI_ARREGION;\n    assign M_AXI_ARUSER    = S_AXI_ARUSER;\n    assign S_AXI_ARREADY   = M_AXI_ARREADY;\n    assign M_AXI_ARVALID   = S_AXI_ARVALID;\n  end endgenerate // grach_pass_through;\n\n  // Wiring logic for Read Data Channel \n  generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through\n    assign S_AXI_RID      = M_AXI_RID;\n    assign S_AXI_RLAST    = M_AXI_RLAST;\n    assign S_AXI_RUSER    = M_AXI_RUSER;\n    assign S_AXI_RDATA    = M_AXI_RDATA;\n    assign S_AXI_RRESP    = M_AXI_RRESP;\n    assign S_AXI_RVALID   = M_AXI_RVALID;\n    assign M_AXI_RREADY   = S_AXI_RREADY;\n  end endgenerate // grdch_pass_through;\n\n  // Wiring logic for AXI Streaming\n  generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through\n    assign M_AXIS_TDATA   = S_AXIS_TDATA;\n    assign M_AXIS_TSTRB   = S_AXIS_TSTRB;\n    assign M_AXIS_TKEEP   = S_AXIS_TKEEP;\n    assign M_AXIS_TID     = S_AXIS_TID;\n    assign M_AXIS_TDEST   = S_AXIS_TDEST;\n    assign M_AXIS_TUSER   = S_AXIS_TUSER;\n    assign M_AXIS_TLAST   = S_AXIS_TLAST;\n    assign S_AXIS_TREADY  = M_AXIS_TREADY;\n    assign M_AXIS_TVALID  = S_AXIS_TVALID;\n  end endgenerate // gaxis_pass_through;\n\n\nendmodule //fifo_generator_v13_2_5\n\n\n\n/*******************************************************************************\n * Declaration of top-level module for Conventional FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_CONV_VER\n  #(\n    parameter  C_COMMON_CLOCK                 = 0,\n    parameter  C_INTERFACE_TYPE               = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_COUNT_TYPE                   = 0,\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DEFAULT_VALUE                = \"\",\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_ENABLE_RLOCS                 = 0,\n    parameter  C_FAMILY                       = \"virtex7\", //Not allowed in Verilog model\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_BACKUP                   = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_INT_CLK                  = 0,\n    parameter  C_HAS_MEMINIT_FILE             = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RD_RST                   = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_RST                   = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_INIT_WR_PNTR_VAL             = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_MIF_FILE_NAME                = \"\",\n    parameter  C_OPTIMIZATION_MODE            = 0,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PRIM_FIFO_TYPE               = \"\",\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_FREQ                      = 1,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_ECC                      = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_USE_FIFO16_FLAGS             = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_FREQ                      = 1,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_WR_RESPONSE_LATENCY          = 1,\n    parameter  C_MSGON_VAL                    = 1,\n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2,\n    parameter  C_AXI_TYPE                     = 0\n   )\n\n  (\n   input                               BACKUP,\n   input                               BACKUP_MARKER,\n   input                               CLK,\n   input                               RST,\n   input                               SRST,\n   input                               WR_CLK,\n   input                               WR_RST,\n   input                               RD_CLK,\n   input                               RD_RST,\n   input [C_DIN_WIDTH-1:0]             DIN,\n   input                               WR_EN,\n   input                               RD_EN,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_ASSERT,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_NEGATE,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_ASSERT,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_NEGATE,\n   input                               INT_CLK,\n   input                               INJECTDBITERR,\n   input                               INJECTSBITERR,\n  \n   output [C_DOUT_WIDTH-1:0]           DOUT,\n   output                              FULL,\n   output                              ALMOST_FULL,\n   output                              WR_ACK,\n   output                              OVERFLOW,\n   output                              EMPTY,\n   output                              ALMOST_EMPTY,\n   output                              VALID,\n   output                              UNDERFLOW,\n   output [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT,\n   output [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT,\n   output [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT,\n   output                              PROG_FULL,\n   output                              PROG_EMPTY,\n   output                              SBITERR,\n   output                              DBITERR,\n   output                              wr_rst_busy_o,\n   output                              wr_rst_busy,\n   output                              rd_rst_busy,\n   output                              wr_rst_i_out,\n   output                              rd_rst_i_out\n  );\n\n/*\n ******************************************************************************\n * Definition of Parameters\n ******************************************************************************\n *     C_COMMON_CLOCK                : Common Clock (1), Independent Clocks (0)\n *     C_COUNT_TYPE                  :    *not used\n *     C_DATA_COUNT_WIDTH            : Width of DATA_COUNT bus\n *     C_DEFAULT_VALUE               :    *not used\n *     C_DIN_WIDTH                   : Width of DIN bus\n *     C_DOUT_RST_VAL                : Reset value of DOUT\n *     C_DOUT_WIDTH                  : Width of DOUT bus\n *     C_ENABLE_RLOCS                :    *not used\n *     C_FAMILY                      : not used in bhv model\n *     C_FULL_FLAGS_RST_VAL          : Full flags rst val (0 or 1)\n *     C_HAS_ALMOST_EMPTY            : 1=Core has ALMOST_EMPTY flag\n *     C_HAS_ALMOST_FULL             : 1=Core has ALMOST_FULL flag\n *     C_HAS_BACKUP                  :    *not used\n *     C_HAS_DATA_COUNT              : 1=Core has DATA_COUNT bus\n *     C_HAS_INT_CLK                 : not used in bhv model\n *     C_HAS_MEMINIT_FILE            :    *not used\n *     C_HAS_OVERFLOW                : 1=Core has OVERFLOW flag\n *     C_HAS_RD_DATA_COUNT           : 1=Core has RD_DATA_COUNT bus\n *     C_HAS_RD_RST                  :    *not used\n *     C_HAS_RST                     : 1=Core has Async Rst\n *     C_HAS_SRST                    : 1=Core has Sync Rst\n *     C_HAS_UNDERFLOW               : 1=Core has UNDERFLOW flag\n *     C_HAS_VALID                   : 1=Core has VALID flag\n *     C_HAS_WR_ACK                  : 1=Core has WR_ACK flag\n *     C_HAS_WR_DATA_COUNT           : 1=Core has WR_DATA_COUNT bus\n *     C_HAS_WR_RST                  :    *not used\n *     C_IMPLEMENTATION_TYPE         : 0=Common-Clock Bram/Dram\n *                                     1=Common-Clock ShiftRam\n *                                     2=Indep. Clocks Bram/Dram\n *                                     3=Virtex-4 Built-in\n *                                     4=Virtex-5 Built-in\n *     C_INIT_WR_PNTR_VAL            :   *not used\n *     C_MEMORY_TYPE                 : 1=Block RAM\n *                                     2=Distributed RAM\n *                                     3=Shift RAM\n *                                     4=Built-in FIFO\n *     C_MIF_FILE_NAME               :   *not used\n *     C_OPTIMIZATION_MODE           :   *not used\n *     C_OVERFLOW_LOW                : 1=OVERFLOW active low\n *     C_PRELOAD_LATENCY             : Latency of read: 0, 1, 2\n *     C_PRELOAD_REGS                : 1=Use output registers\n *     C_PRIM_FIFO_TYPE              : not used in bhv model\n *     C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold\n *     C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold\n *     C_PROG_EMPTY_TYPE             : 0=No programmable empty\n *                                     1=Single prog empty thresh constant\n *                                     2=Multiple prog empty thresh constants\n *                                     3=Single prog empty thresh input\n *                                     4=Multiple prog empty thresh inputs\n *     C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold\n *     C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold\n *     C_PROG_FULL_TYPE              : 0=No prog full\n *                                     1=Single prog full thresh constant\n *                                     2=Multiple prog full thresh constants\n *                                     3=Single prog full thresh input\n *                                     4=Multiple prog full thresh inputs\n *     C_RD_DATA_COUNT_WIDTH         : Width of RD_DATA_COUNT bus\n *     C_RD_DEPTH                    : Depth of read interface (2^N)\n *     C_RD_FREQ                     : not used in bhv model\n *     C_RD_PNTR_WIDTH               : always log2(C_RD_DEPTH)\n *     C_UNDERFLOW_LOW               : 1=UNDERFLOW active low\n *     C_USE_DOUT_RST                : 1=Resets DOUT on RST\n *     C_USE_ECC                     : Used for error injection purpose\n *     C_USE_EMBEDDED_REG            : 1=Use BRAM embedded output register\n *     C_USE_FIFO16_FLAGS            : not used in bhv model\n *     C_USE_FWFT_DATA_COUNT         : 1=Use extra logic for FWFT data count\n *     C_VALID_LOW                   : 1=VALID active low\n *     C_WR_ACK_LOW                  : 1=WR_ACK active low\n *     C_WR_DATA_COUNT_WIDTH         : Width of WR_DATA_COUNT bus\n *     C_WR_DEPTH                    : Depth of write interface (2^N)\n *     C_WR_FREQ                     : not used in bhv model\n *     C_WR_PNTR_WIDTH               : always log2(C_WR_DEPTH)\n *     C_WR_RESPONSE_LATENCY         :    *not used\n *     C_MSGON_VAL                   :    *not used by bhv model\n *     C_ENABLE_RST_SYNC             : 0 = Use WR_RST & RD_RST\n *                                     1 = Use RST\n *     C_ERROR_INJECTION_TYPE        : 0 = No error injection\n *                                     1 = Single bit error injection only\n *                                     2 = Double bit error injection only\n *                                     3 = Single and double bit error injection\n ******************************************************************************\n * Definition of Ports\n ******************************************************************************\n *   BACKUP       : Not used\n *   BACKUP_MARKER: Not used\n *   CLK          : Clock\n *   DIN          : Input data bus\n *   PROG_EMPTY_THRESH       : Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag\n *   PROG_FULL_THRESH        : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag\n *   RD_CLK       : Read Domain Clock\n *   RD_EN        : Read enable\n *   RD_RST       : Read Reset\n *   RST          : Asynchronous Reset\n *   SRST         : Synchronous Reset\n *   WR_CLK       : Write Domain Clock\n *   WR_EN        : Write enable\n *   WR_RST       : Write Reset\n *   INT_CLK      : Internal Clock\n *   INJECTSBITERR: Inject Signle bit error\n *   INJECTDBITERR: Inject Double bit error\n *   ALMOST_EMPTY : One word remaining in FIFO\n *   ALMOST_FULL  : One empty space remaining in FIFO\n *   DATA_COUNT   : Number of data words in fifo( synchronous to CLK)\n *   DOUT         : Output data bus\n *   EMPTY        : Empty flag\n *   FULL         : Full flag\n *   OVERFLOW     : Last write rejected\n *   PROG_EMPTY   : Programmable Empty Flag\n *   PROG_FULL    : Programmable Full Flag\n *   RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)\n *   UNDERFLOW    : Last read rejected\n *   VALID        : Last read acknowledged, DOUT bus VALID\n *   WR_ACK       : Last write acknowledged\n *   WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)\n *   SBITERR      : Single Bit ECC Error Detected\n *   DBITERR      : Double Bit ECC Error Detected\n ******************************************************************************\n */\n\n  //----------------------------------------------------------------------------\n  //- Internal Signals for delayed input signals\n  //- All the input signals except Clock are delayed by 100 ps and then given to\n  //- the models.\n  //----------------------------------------------------------------------------\n \n  reg                         rst_delayed                       ;\n  reg                         empty_fb                       ;\n  reg                         srst_delayed                      ;\n  reg                         wr_rst_delayed                    ;\n  reg                         rd_rst_delayed                    ;\n  reg                         wr_en_delayed                     ;\n  reg                         rd_en_delayed                     ;\n  reg  [C_DIN_WIDTH-1:0]      din_delayed                       ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_delayed         ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_assert_delayed  ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_negate_delayed  ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_delayed          ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_assert_delayed   ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_negate_delayed   ;\n  reg                         injectdbiterr_delayed             ;\n  reg                         injectsbiterr_delayed             ;\n   wire                        empty_p0_out;\n\n  always @* rst_delayed                       <= #`TCQ RST                      ;\n  always @* empty_fb                       <= #`TCQ empty_p0_out                      ;\n  always @* srst_delayed                      <= #`TCQ SRST                     ; \n  always @* wr_rst_delayed                    <= #`TCQ WR_RST                   ; \n  always @* rd_rst_delayed                    <= #`TCQ RD_RST                   ; \n  always @* din_delayed                       <= #`TCQ DIN                      ; \n  always @* wr_en_delayed                     <= #`TCQ WR_EN                    ; \n  always @* rd_en_delayed                     <= #`TCQ RD_EN                    ; \n  always @* prog_empty_thresh_delayed         <= #`TCQ PROG_EMPTY_THRESH        ; \n  always @* prog_empty_thresh_assert_delayed  <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; \n  always @* prog_empty_thresh_negate_delayed  <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; \n  always @* prog_full_thresh_delayed          <= #`TCQ PROG_FULL_THRESH         ; \n  always @* prog_full_thresh_assert_delayed   <= #`TCQ PROG_FULL_THRESH_ASSERT  ; \n  always @* prog_full_thresh_negate_delayed   <= #`TCQ PROG_FULL_THRESH_NEGATE  ; \n  always @* injectdbiterr_delayed             <= #`TCQ INJECTDBITERR            ; \n  always @* injectsbiterr_delayed             <= #`TCQ INJECTSBITERR            ; \n\n  /*****************************************************************************\n   * Derived parameters\n   ****************************************************************************/\n  //There are 2 Verilog behavioral models\n  // 0 = Common-Clock FIFO/ShiftRam FIFO\n  // 1 = Independent Clocks FIFO\n  // 2 = Low Latency Synchronous FIFO\n  // 3 = Low Latency Asynchronous FIFO\n  localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :\n                              (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n\n  //Internal reset signals\n  reg                                rd_rst_asreg    = 1'b0;\n  reg                                rd_rst_asreg_d1 = 1'b0;\n  reg                                rd_rst_asreg_d2 = 1'b0;\n  reg                                rd_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_reg      = 1'b0;\n  reg                                rd_rst_comb     = 1'b1;\n  reg                                rd_rst_comb_d1  = 1'b0;\n  reg                                wr_rst_d0       = 1'b0;\n  reg                                wr_rst_d1       = 1'b0;\n  reg                                wr_rst_d2       = 1'b0;\n  reg                                rd_rst_d0       = 1'b0;\n  reg                                rd_rst_d1       = 1'b0;\n  reg                                rd_rst_d2       = 1'b0;\n  reg                                rd_rst_d3       = 1'b0;\n  reg                                wrrst_done      = 1'b0;\n  reg                                rdrst_done      = 1'b0;\n  reg                                wr_rst_asreg    = 1'b0;\n  reg                                wr_rst_asreg_d1 = 1'b0;\n  reg                                wr_rst_asreg_d2 = 1'b0;\n  reg                                wr_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_wr_d0    = 1'b0;\n  reg                                rd_rst_wr_d1    = 1'b0;\n  reg                                rd_rst_wr_d2    = 1'b0;\n  reg                                wr_rst_reg      = 1'b0;\n  reg                                rst_active_i    = 1'b1;\n  reg                                rst_delayed_d1  = 1'b1;\n  reg                                rst_delayed_d2  = 1'b1;\n  reg                                wr_rst_comb     = 1'b1;\n  reg                                wr_rst_comb_d1  = 1'b0;\n  wire                               wr_rst_i;\n  wire                               rd_rst_i;\n  wire                               rst_i;\n\n  //Internal reset signals\n  reg                                rst_asreg     = 1'b0;\n  reg                                srst_asreg    = 1'b0;\n  reg                                rst_asreg_d1  = 1'b0;\n  reg                                rst_asreg_d2  = 1'b0;\n  reg                                srst_asreg_d1 = 1'b0;\n  reg                                srst_asreg_d2 = 1'b0;\n  reg                                rst_reg       = 1'b0;\n  reg                                srst_reg      = 1'b0;\n  reg                                rst_comb      = 1'b1;\n  reg                                rst_comb_d1   = 1'b0;\n  wire                               srst_comb;\n  reg                                rst_full_gen_i = 0;\n  reg                                rst_full_ff_i = 0;\n  reg  [2:0]                         sckt_ff0_bsy_o_i = {3{1'b0}};\n                                     \n  wire                               RD_CLK_P0_IN;\n  wire                               RST_P0_IN;\n  wire                               RD_EN_FIFO_IN;\n  wire                               RD_EN_P0_IN;\n\n  wire                               ALMOST_EMPTY_FIFO_OUT;\n  wire                               ALMOST_FULL_FIFO_OUT;\n  wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT_FIFO_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DOUT_FIFO_OUT;\n  wire                               EMPTY_FIFO_OUT;\n  wire                               fifo_empty_fb;\n  wire                               FULL_FIFO_OUT;\n  wire                               OVERFLOW_FIFO_OUT;\n  wire                               PROG_EMPTY_FIFO_OUT;\n  wire                               PROG_FULL_FIFO_OUT;\n  wire                               VALID_FIFO_OUT;\n  wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT_FIFO_OUT;\n  wire                               UNDERFLOW_FIFO_OUT;\n  wire                               WR_ACK_FIFO_OUT;\n  wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT_FIFO_OUT;\n\n\n  //***************************************************************************\n  // Internal Signals\n  //   The core uses either the internal_ wires or the preload0_ wires depending\n  //     on whether the core uses Preload0 or not.\n  //   When using preload0, the internal signals connect the internal core to\n  //     the preload logic, and the external core's interfaces are tied to the\n  //     preload0 signals from the preload logic.\n  //***************************************************************************\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_OUT;\n  wire                               VALID_P0_OUT;\n  wire                               EMPTY_P0_OUT;\n  wire                               ALMOSTEMPTY_P0_OUT;\n  reg                                EMPTY_P0_OUT_Q;\n  reg                                ALMOSTEMPTY_P0_OUT_Q;\n  wire                               UNDERFLOW_P0_OUT;\n  wire                               RDEN_P0_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_IN;\n  wire                               EMPTY_P0_IN;\n  reg  [31:0]                        DATA_COUNT_FWFT;\n  reg                                SS_FWFT_WR  ;\n  reg                                SS_FWFT_RD ;\n\n  wire                               sbiterr_fifo_out;\n  wire                               dbiterr_fifo_out;\n  wire                               inject_sbit_err;\n  wire                               inject_dbit_err;\n  wire                               sckt_wr_rst_i;\n  wire                               sckt_rd_rst_i;\n  reg                                sckt_wr_rst_i_q = 1'b0;\n \n  wire                               w_fab_read_data_valid_i;\n  wire                               w_read_data_valid_i;\n  wire                               w_ram_valid_i;\n  // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.\n  assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectsbiterr_delayed : 0;\n  assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectdbiterr_delayed : 0;\n                           \n  assign wr_rst_i_out = wr_rst_i;\n  assign rd_rst_i_out = rd_rst_i;\n  assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];\n  generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o\n    wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;\n    always @ (posedge clk_i)\n      sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; \n  end endgenerate \n// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL\n// parameter (1=Independent Clocks, 0=Common Clock)\n\n  localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;\ngenerate\ncase (C_VERILOG_IMPL)\n0 : begin : block1_ss\n  //Common Clock Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_ss\n  #(\n    .C_FAMILY                            (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                  (C_DATA_COUNT_WIDTH),            \n    .C_DIN_WIDTH                         (C_DIN_WIDTH),                   \n    .C_DOUT_RST_VAL                      (C_DOUT_RST_VAL),                \n    .C_DOUT_WIDTH                        (C_DOUT_WIDTH),                  \n    .C_FULL_FLAGS_RST_VAL                (FULL_FLAGS_RST_VAL),            \n    .C_HAS_ALMOST_EMPTY                  (C_HAS_ALMOST_EMPTY),            \n    .C_HAS_ALMOST_FULL                   ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),             \n    .C_HAS_DATA_COUNT                    (C_HAS_DATA_COUNT),              \n    .C_HAS_OVERFLOW                      (C_HAS_OVERFLOW),                \n    .C_HAS_RD_DATA_COUNT                 (C_HAS_RD_DATA_COUNT),           \n    .C_HAS_RST                           (C_EN_SAFETY_CKT?0:C_HAS_RST),                     \n    .C_HAS_SRST                          (C_EN_SAFETY_CKT?1:C_HAS_SRST),                    \n    .C_HAS_UNDERFLOW                     (C_HAS_UNDERFLOW),               \n    .C_HAS_VALID                         (C_HAS_VALID),                   \n    .C_HAS_WR_ACK                        (C_HAS_WR_ACK),                  \n    .C_HAS_WR_DATA_COUNT                 (C_HAS_WR_DATA_COUNT),           \n    .C_IMPLEMENTATION_TYPE               (C_IMPLEMENTATION_TYPE),         \n    .C_MEMORY_TYPE                       (C_MEMORY_TYPE),                 \n    .C_OVERFLOW_LOW                      (C_OVERFLOW_LOW),                \n    .C_PRELOAD_LATENCY                   (C_PRELOAD_LATENCY),             \n    .C_PRELOAD_REGS                      (C_PRELOAD_REGS),                \n    .C_PROG_EMPTY_THRESH_ASSERT_VAL      (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL      (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                   (C_PROG_EMPTY_TYPE),             \n    .C_PROG_FULL_THRESH_ASSERT_VAL       (C_PROG_FULL_THRESH_ASSERT_VAL), \n    .C_PROG_FULL_THRESH_NEGATE_VAL       (C_PROG_FULL_THRESH_NEGATE_VAL), \n    .C_PROG_FULL_TYPE                    (C_PROG_FULL_TYPE),              \n    .C_RD_DATA_COUNT_WIDTH               (C_RD_DATA_COUNT_WIDTH),         \n    .C_RD_DEPTH                          (C_RD_DEPTH),                    \n    .C_RD_PNTR_WIDTH                     (C_RD_PNTR_WIDTH),               \n    .C_UNDERFLOW_LOW                     (C_UNDERFLOW_LOW),               \n    .C_USE_DOUT_RST                      (C_USE_DOUT_RST),                \n    .C_USE_EMBEDDED_REG                  (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                     (C_EN_SAFETY_CKT),            \n    .C_USE_FWFT_DATA_COUNT               (C_USE_FWFT_DATA_COUNT),         \n    .C_VALID_LOW                         (C_VALID_LOW),                   \n    .C_WR_ACK_LOW                        (C_WR_ACK_LOW),                  \n    .C_WR_DATA_COUNT_WIDTH               (C_WR_DATA_COUNT_WIDTH),         \n    .C_WR_DEPTH                          (C_WR_DEPTH),                    \n    .C_WR_PNTR_WIDTH                     (C_WR_PNTR_WIDTH),               \n    .C_USE_ECC                           (C_USE_ECC),                     \n    .C_ENABLE_RST_SYNC                   (C_ENABLE_RST_SYNC),             \n    .C_ERROR_INJECTION_TYPE              (C_ERROR_INJECTION_TYPE),\n    .C_FIFO_TYPE                         (C_FIFO_TYPE)                     \n  )\n  gen_ss\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .CLK                      (CLK),\n    .RST                      (C_EN_SAFETY_CKT?1'b0:rst_i),\n    .SRST                     (C_EN_SAFETY_CKT?sckt_wr_rst_i:srst_delayed),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .USER_EMPTY_FB            (empty_fb),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .DATA_COUNT               (DATA_COUNT_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .WR_RST_BUSY              (wr_rst_busy),\n    .RD_RST_BUSY              (rd_rst_busy),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n1 : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT), \n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .fab_read_data_valid_i    (w_fab_read_data_valid_i),\n    .read_data_valid_i        (w_read_data_valid_i),\n    .ram_valid_i              (w_ram_valid_i),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\n2 : begin : ll_afifo_inst\n  fifo_generator_v13_2_5_beh_ver_ll_afifo\n  #(\n    .C_DIN_WIDTH                    (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                 (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                   (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_RD_DATA_COUNT            (C_HAS_RD_DATA_COUNT),\n    .C_HAS_WR_DATA_COUNT            (C_HAS_WR_DATA_COUNT),\n    .C_RD_DEPTH                     (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                (C_RD_PNTR_WIDTH),\n    .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n    .C_WR_DATA_COUNT_WIDTH          (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                     (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                (C_WR_PNTR_WIDTH),\n    .C_FIFO_TYPE                    (C_FIFO_TYPE)\n   )\n  gen_ll_afifo\n  (\n    .DIN                        (din_delayed),\n    .RD_CLK                     (RD_CLK),\n    .RD_EN                      (rd_en_delayed),\n    .WR_RST                     (wr_rst_i),\n    .RD_RST                     (rd_rst_i),\n    .WR_CLK                     (WR_CLK),\n    .WR_EN                      (wr_en_delayed),\n    .DOUT                       (DOUT),\n    .EMPTY                      (EMPTY),\n    .FULL                       (FULL)\n  );\nend\ndefault : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT),\n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\nendcase\nendgenerate\n\n\n   //**************************************************************************\n   // Connect Internal Signals\n   //   (Signals labeled internal_*)\n   //  In the normal case, these signals tie directly to the FIFO's inputs and\n   //    outputs.\n   //  In the case of Preload Latency 0 or 1, there are intermediate\n   //    signals between the internal FIFO and the preload logic.\n   //**************************************************************************\n   \n   \n   //***********************************************\n   // If First-Word Fall-Through, instantiate\n   // the preload0 (FWFT) module\n   //***********************************************\n   wire                        rd_en_to_fwft_fifo;\n   wire                        sbiterr_fwft;\n   wire                        dbiterr_fwft;\n   wire [C_DOUT_WIDTH-1:0]     dout_fwft;\n   wire                        empty_fwft;\n   wire                        rd_en_fifo_in;\n   wire                        stage2_reg_en_i;\n   wire [1:0]                  valid_stages_i;\n   wire                        rst_fwft;\n   //wire                        empty_p0_out;\n   reg  [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n   localparam IS_PKT_FIFO      = (C_FIFO_TYPE == 1) ? 1 : 0;\n   localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;\n   assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2_fwft\n\n\n         fifo_generator_v13_2_5_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_EMBEDDED_REG  (C_USE_EMBEDDED_REG),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (C_FIFO_TYPE)\n             )\n             fgpl0\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (RST_P0_IN),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (RD_EN_P0_IN),\n                .FIFOEMPTY        (EMPTY_P0_IN),\n                .FIFODATA         (DATA_P0_IN),\n                .FIFOSBITERR      (sbiterr_fifo_out),\n                .FIFODBITERR      (dbiterr_fifo_out),\n                // Output\n                .USERDATA         (dout_fwft),\n                .USERVALID        (VALID_P0_OUT),\n                .USEREMPTY        (empty_fwft),\n                .USERALMOSTEMPTY  (ALMOSTEMPTY_P0_OUT),\n                .USERUNDERFLOW    (UNDERFLOW_P0_OUT),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_fifo_in),\n                .USERSBITERR      (sbiterr_fwft),\n                .USERDBITERR      (dbiterr_fwft),\n                .STAGE2_REG_EN    (stage2_reg_en_i),\n                .fab_read_data_valid_i_o    (w_fab_read_data_valid_i),\n                .read_data_valid_i_o        (w_read_data_valid_i),\n                .ram_valid_i_o              (w_ram_valid_i),\n                .VALID_STAGES                (valid_stages_i)\n                );\n\n         \n         //***********************************************\n         // Connect inputs to preload (FWFT) module\n         //***********************************************\n         //Connect the RD_CLK of the Preload (FWFT) module to CLK if we \n         // have a common-clock FIFO, or RD_CLK if we have an \n         // independent clock FIFO\n         assign RD_CLK_P0_IN       = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);\n         assign RST_P0_IN          = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;\n         assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n         assign EMPTY_P0_IN        = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;\n         assign DATA_P0_IN         = DOUT_FIFO_OUT;\n         \n         //***********************************************\n         // Connect outputs from preload (FWFT) module\n         //***********************************************\n         assign VALID              = VALID_P0_OUT ;\n         assign ALMOST_EMPTY       = ALMOSTEMPTY_P0_OUT;\n         assign UNDERFLOW          = UNDERFLOW_P0_OUT ;\n         \n         assign RD_EN_FIFO_IN      = rd_en_fifo_in;\n         \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:\n           (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : \n           DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];  \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               EMPTY_P0_OUT_Q       <= 1;\n               ALMOSTEMPTY_P0_OUT_Q <= 1;\n            end else begin\n               EMPTY_P0_OUT_Q       <= #`TCQ empty_p0_out;\n//               EMPTY_P0_OUT_Q       <= #`TCQ EMPTY_FIFO_OUT;\n               ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;\n            end\n         end //always\n         \n         \n         //***********************************************\n         // logic for common-clock data count when FWFT is selected\n         //***********************************************\n         initial begin\n            SS_FWFT_RD = 1'b0;\n            DATA_COUNT_FWFT = 0 ;\n            SS_FWFT_WR   = 1'b0 ;\n         end //initial\n         \n         \n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter. SS_FWFT_WR and SS_FWFT_RD\n         // are the up/down enables for the counter.\n         //***********************************************\n         always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin\n            if (C_VALID_LOW == 1) begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;\n            end else begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;\n            end\n            SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT))  ;\n         end \n\n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter for FWFT. This always block \n         // calculates the counter.\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               DATA_COUNT_FWFT      <= 0;\n            end else begin\n               //if (srst_delayed && (C_HAS_SRST == 1) ) begin\n               if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin\n                  DATA_COUNT_FWFT      <= #`TCQ 0;\n               end else begin\n                  case ( {SS_FWFT_WR, SS_FWFT_RD})\n                    2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                    2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;\n                    2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;\n                    2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                  endcase  \n               end //if SRST\n            end //IF RST\n         end //always\n\n      end endgenerate // : block2\n\n    // AXI Streaming Packet FIFO\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_plus1 = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_reg   = 0;\n    reg                         partial_packet     = 0;\n    reg                         stage1_eop_d1      = 0;\n    reg                         rd_en_fifo_in_d1   = 0;\n    reg                         eop_at_stage2      = 0;\n    reg                         ram_pkt_empty      = 0;\n    reg                         ram_pkt_empty_d1   = 0;\n\n    wire [C_DOUT_WIDTH-1:0]     dout_p0_out;\n    wire                        packet_empty_wr;\n    wire                        wr_rst_fwft_pkt_fifo;\n    wire                        dummy_wr_eop;\n    wire                        ram_wr_en_pkt_fifo;\n    wire                        wr_eop;\n    wire                        ram_rd_en_compare;\n    wire                        stage1_eop;\n    wire                        pkt_ready_to_read;\n    wire                        rd_en_2_stage2;\n\n    // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)\n    // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP\n    // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of\n    // write packet count\n    generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop\n       always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n          if (wr_rst_fwft_pkt_fifo)\n             partial_packet   <= 1'b0;\n          else begin\n             if (srst_delayed | wr_rst_busy | rd_rst_busy)\n                partial_packet <= #`TCQ 1'b0;\n             else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))\n                partial_packet <= #`TCQ 1'b1;\n             else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)\n                partial_packet <= #`TCQ 1'b0;\n          end\n        end\n    end endgenerate // gdummy_wr_eop\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin : gpkt_fifo_fwft\n      assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;\n      assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);\n      assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];\n  \n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft) begin\n          stage1_eop_d1    <= 1'b0;\n          rd_en_fifo_in_d1 <= 1'b0;\n        end else begin\n          if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            stage1_eop_d1    <= #`TCQ 1'b0;\n            rd_en_fifo_in_d1 <= #`TCQ 1'b0;\n          end else begin\n            stage1_eop_d1    <= #`TCQ stage1_eop;\n            rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;\n          end\n        end\n      end\n      assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;\n      assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);\n      assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);\n      assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;\n\n\n         fifo_generator_v13_2_5_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (2) // Enable low latency fwft logic\n             )\n         pkt_fifo_fwft\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (rst_fwft),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (rd_en_delayed),\n                .FIFOEMPTY        (pkt_ready_to_read),\n                .FIFODATA         (dout_fwft),\n                .FIFOSBITERR      (sbiterr_fwft),\n                .FIFODBITERR      (dbiterr_fwft),\n                // Output\n                .USERDATA         (dout_p0_out),\n                .USERVALID        (),\n                .USEREMPTY        (empty_p0_out),\n                .USERALMOSTEMPTY  (),\n                .USERUNDERFLOW    (),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_2_stage2),\n                .USERSBITERR      (SBITERR),\n                .USERDBITERR      (DBITERR),\n                .STAGE2_REG_EN    (),\n                .VALID_STAGES     ()\n                );\n\n      assign pkt_ready_to_read  = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));\n      assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft)\n          eop_at_stage2 <= 1'b0;\n        else if (stage2_reg_en_i)\n          eop_at_stage2 <= #`TCQ stage1_eop;\n      end\n\n      //---------------------------------------------------------------------------\n      // Write and Read Packet Count\n      //---------------------------------------------------------------------------\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count  <= 0;\n         else if (srst_delayed  | wr_rst_busy | rd_rst_busy)\n            wr_pkt_count  <= #`TCQ 0;\n         else if (wr_eop)\n            wr_pkt_count  <= #`TCQ wr_pkt_count + 1;\n      end\n    \n    end endgenerate //: gpkt_fifo_fwft\n\n    assign DOUT               = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;\n    assign EMPTY              = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            rd_pkt_count       <= 0;\n            rd_pkt_count_plus1 <= 1;\n         end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            rd_pkt_count       <= #`TCQ 0;\n            rd_pkt_count_plus1 <= #`TCQ 1;\n         end else if (stage2_reg_en_i && stage1_eop) begin\n            rd_pkt_count       <= #`TCQ rd_pkt_count + 1;\n            rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;\n         end\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (SRST | wr_rst_busy | rd_rst_busy) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n    end endgenerate //grss_pkt_cnt\n    \n    localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;\n    reg  [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_b2g = 0;\n    wire [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_rd;\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt\n      // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count_b2g  <= 0;\n         else\n            wr_pkt_count_b2g  <= #`TCQ wr_pkt_count;\n      end\n\n      // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            wr_pkt_count_q       <= 0;\n         else\n            wr_pkt_count_q       <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};\n      end\n\n      always @* begin\n        if (stage1_eop)\n           rd_pkt_count    <= rd_pkt_count_reg + 1;\n        else\n           rd_pkt_count    <= rd_pkt_count_reg;\n      end\n\n      assign wr_pkt_count_rd    = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            rd_pkt_count_reg       <= 0;\n         else if (rd_en_fifo_in)\n            rd_pkt_count_reg       <= #`TCQ rd_pkt_count;\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (rd_pkt_count != wr_pkt_count_rd) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n\n      // Synchronize the empty in write domain\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            pkt_empty_sync  <= 'b1;\n         else\n            pkt_empty_sync  <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};\n      end\n\n    end endgenerate //gras_pkt_cnt\n\n   generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO\n\n     //***********************************************\n     // If NOT First-Word Fall-Through, wire the outputs\n     // of the internal _ss or _as FIFO directly to the\n     // output, and do not instantiate the preload0\n     // module.\n     //***********************************************\n\n     assign RD_CLK_P0_IN       = 0;\n     assign RST_P0_IN          = 0;\n     assign RD_EN_P0_IN        = 0;\n\n     assign RD_EN_FIFO_IN      = rd_en_delayed;\n\n     assign DOUT               = DOUT_FIFO_OUT;\n     assign DATA_P0_IN         = 0;\n     assign VALID              = VALID_FIFO_OUT;\n     assign EMPTY              = EMPTY_FIFO_OUT;\n     assign ALMOST_EMPTY       = ALMOST_EMPTY_FIFO_OUT;\n     assign EMPTY_P0_IN        = 0;\n     assign UNDERFLOW          = UNDERFLOW_FIFO_OUT;\n     assign DATA_COUNT         = DATA_COUNT_FIFO_OUT;\n     assign SBITERR            = sbiterr_fifo_out;\n     assign DBITERR            = dbiterr_fifo_out;\n\n   end endgenerate // STD_FIFO\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO\n     assign empty_p0_out       = empty_fwft;\n     assign SBITERR            = sbiterr_fwft;\n     assign DBITERR            = dbiterr_fwft;\n     assign DOUT               = dout_fwft;\n     assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n\n   end endgenerate // NO_PKT_FIFO\n\n   //***********************************************\n   // Connect user flags to internal signals\n   //***********************************************\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3\n      if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);\n      end //block_ic\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3\n   endgenerate\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30\n       if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30\n   endgenerate\n\n\n    \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both\n       if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30_both\n   endgenerate\n\n generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both\n      if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));\n      end //block_ic_both\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3_both\n   endgenerate\n\n\n   //If we are not using extra logic for the FWFT data count,\n   //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the\n   //internal FIFO instance  \n   generate\n      if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n   //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal\n   //FIFO instance\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1) begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n      else begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n\n   //Connect other flags to the internal FIFO instance\n   assign       FULL        = FULL_FIFO_OUT;\n   assign       ALMOST_FULL = ALMOST_FULL_FIFO_OUT;\n   assign       WR_ACK      = WR_ACK_FIFO_OUT;\n   assign       OVERFLOW    = OVERFLOW_FIFO_OUT;\n   assign       PROG_FULL   = PROG_FULL_FIFO_OUT;\n   assign       PROG_EMPTY  = PROG_EMPTY_FIFO_OUT;\n\n\n  /**************************************************************************\n  * find_log2\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n   // if an asynchronous FIFO has been selected, display a message that the FIFO\n   //   will not be cycle-accurate in simulation\n   initial begin\n      if (C_IMPLEMENTATION_TYPE == 2) begin\n         $display(\"WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.\");\n      end else if (C_MEMORY_TYPE == 4) begin\n         $display(\"FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.\");\n         $finish;\n      end\n\n      if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin\n         $display(\"FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.\");\n         $finish;\n      end\n\n      if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin\n         $display(\"FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.\");\n         $finish;\n      end\n\n      if (C_USE_ECC == 1) begin\n         if (C_DIN_WIDTH != C_DOUT_WIDTH) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.\");\n            $finish;\n         end\n         if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.\");\n            $finish;\n         end\n      end\n\n   end //initial\n\n  /**************************************************************************\n  * Internal reset logic\n  **************************************************************************/\n  assign wr_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg|sckt_wr_rst_i : 0;\n  assign rd_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg|sckt_rd_rst_i : 0;\n  assign rst_i            = C_HAS_RST ? rst_reg|sckt_wr_rst_i : 0;\n\n  wire rst_2_sync;\n  wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;\n\n  localparam RST_SYNC_STAGES = C_EN_SAFETY_CKT == 0 ? C_COMMON_CLOCK ? C_SYNCHRONIZER_STAGE : C_SYNCHRONIZER_STAGE+2 : 5;\n  localparam RST_BUSY_LEN    = 4;\n  reg  wr_rst_busy_i = 0;\n  reg  rd_rst_busy_i = 0;\n  generate\n      if (C_ENABLE_RST_SYNC == 0 || (C_HAS_RST == 0 && C_HAS_SRST == 0)) begin : gnrst_sync\n        always @* begin\n          wr_rst_reg <= wr_rst_delayed;\n          rd_rst_reg <= rd_rst_delayed;\n          rst_reg    <= 1'b0;\n          srst_reg    <= 1'b0;\n        end\n        assign rst_2_sync = wr_rst_delayed;\n        assign wr_rst_busy = 1'b0;\n        assign wr_rst_busy_o = 1'b0;\n        assign rd_rst_busy = 1'b0;\n        assign sckt_wr_rst_i = 1'b0;\n        assign sckt_rd_rst_i = 1'b0;\n      end // gnrst_sync\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 0) begin : g7s_ic_rst_nsckt\n        reg [1:0]                 arst_sync_wr  = 2'b11;\n        reg [1:0]                 arst_sync_rd  = 2'b11;\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge WR_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge RD_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_rd    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_rd    <= #`TCQ {arst_sync_rd[0], rst_delayed};\n        end\n        always @(posedge WR_CLK) begin\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n\tend\n        always @(posedge WR_CLK or posedge arst_sync_wr[1]) begin\n\t  if (arst_sync_wr[1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n            rd_rst_wr_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            rd_rst_wr_ext  <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t    if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t      sckt_wr_rst_ic <= #`TCQ 1'b0;\n            else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t      wr_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n        always @(posedge RD_CLK) begin\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], sckt_wr_rst_ic};\n\tend\n        always @(posedge RD_CLK or posedge arst_sync_rd[1]) begin\n\t  if (arst_sync_rd[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n            wr_rst_rd_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            wr_rst_rd_ext  <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t    if (wr_rst_rd_ext[1]) begin\n\t      sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t      rd_rst_busy_i  <= #`TCQ 1'b0;\n\t    end\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic|arst_sync_wr[1];\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic|arst_sync_rd[1];\n      end // g7s_ic_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 1) begin : g7s_ic_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] arst_sync_rd  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        always @(posedge WR_CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n          rd_rst_wr_ext    <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_wr[RST_SYNC_STAGES-1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n          end else if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t    sckt_wr_rst_ic <= #`TCQ 1'b0;\n          else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t    wr_rst_busy_i  <= #`TCQ 1'b0;\n\tend\n        always @(posedge RD_CLK) begin\n\t  arst_sync_rd     <= #`TCQ {arst_sync_rd[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n          wr_rst_rd_ext    <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_rd[RST_SYNC_STAGES-1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n\t  end else if (wr_rst_rd_ext[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t    rd_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic;\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic;\n      end // g7s_ic_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 0) begin : g7s_cc_rst_nsckt\n        reg [1:0]              arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge CLK) begin\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0] | arst_sync_wr[1]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc | arst_sync_wr[1];\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 1) begin : g7s_cc_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n\n        always @(posedge CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc;\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst\n        assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;\n        assign rd_rst_busy = rst_reg;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = rst_reg;\n        always @* rst_full_ff_i  <= 1'b0;\n        always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;\n\n        always @(posedge CLK) begin\n          rst_delayed_d1 <= #`TCQ srst_delayed;\n          rst_delayed_d2 <= #`TCQ rst_delayed_d1;\n          if (rst_reg || rst_delayed_d2) begin\n            rst_active_i <= #`TCQ 1'b1;\n          end else begin\n            rst_active_i <= #`TCQ rst_reg;\n          end    \n        end   \n        always @(posedge CLK) begin\n          if (~rst_reg && srst_delayed) begin\n             rst_reg <= #`TCQ 1'b1;\n           end else if (rst_reg) begin\n             rst_reg <= #`TCQ 1'b0;\n           end else begin\n             rst_reg <= #`TCQ rst_reg;\n           end    \n        end   \n      end // g8s_cc_rst\n      else if (IS_8SERIES != 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_srst\n        assign wr_rst_busy = srst_delayed;\n        assign rd_rst_busy = srst_delayed;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = srst_delayed;\n        always @* rst_full_ff_i  <= 1'b0;\n      end // g7s_cc_srst\n  endgenerate \n\n  reg rst_d1 = 1'b0;\n  reg rst_d2 = 1'b0;\n  reg rst_d3 = 1'b0;\n  reg rst_d4 = 1'b0;\n  generate\n    if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1\n    // RST_FULL_GEN replaces the reset falling edge detection used to de-assert\n    // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.\n\n    // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &\n    // PROG_FULL\n\n      always @ (posedge rst_2_sync or posedge clk_2_sync) begin\n        if (rst_2_sync && C_EN_SAFETY_CKT == 0) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          rst_d3         <= 1'b1;\n          rst_d4         <= 1'b0;\n        end else begin\n          if (srst_delayed) begin\n            rst_d1         <= #`TCQ 1'b1;\n            rst_d2         <= #`TCQ 1'b1;\n            rst_d3         <= #`TCQ 1'b1;\n            rst_d4         <= #`TCQ 1'b0;\n          end else begin\n            rst_d1         <= #`TCQ wr_rst_busy;//1'b0;\n            rst_d2         <= #`TCQ rst_d1;\n            rst_d3         <= #`TCQ rst_d2 | sckt_wr_rst_i;\n            rst_d4         <= #`TCQ rst_d3;\n          end\n        end\n      end\n\n      always @* rst_full_ff_i  <= C_HAS_SRST ? 1'b0 : rst_d2 | sckt_wr_rst_i;\n      always @* rst_full_gen_i <= C_HAS_SRST ? rst_d4 : rst_d3;\n\n    end else if (C_EN_SAFETY_CKT == 1 && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full_sckt\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end\n  endgenerate // grstd1\n\nendmodule //fifo_generator_v13_2_5_CONV_VER\n\n\nmodule fifo_generator_v13_2_5_sync_stage\n  #(\n    parameter  C_WIDTH          = 10\n   )\n   (\n    input                     RST,\n    input                     CLK,\n    input       [C_WIDTH-1:0] DIN,\n    output reg  [C_WIDTH-1:0] DOUT = 0\n   );\n   always @ (posedge RST or posedge CLK) begin\n     if (RST)\n       DOUT <= 0;\n     else\n       DOUT <= #`TCQ DIN;\n   end\nendmodule // fifo_generator_v13_2_5_sync_stage\n\n/*******************************************************************************\n * Declaration of Independent-Clocks FIFO Module\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_as\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2 \n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input                                         SAFETY_CKT_WR_RST,\n   input                                         SAFETY_CKT_RD_RST,\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_ASSERT,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_NEGATE,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_ASSERT,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_NEGATE,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         RD_EN_USER,\n   input                                         RST,\n   input                                         RST_FULL_GEN,\n   input                                         RST_FULL_FF,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   input                                         INJECTDBITERR,\n   input                                         INJECTSBITERR,\n   input                                         USER_EMPTY_FB,\n   input                                         fab_read_data_valid_i,\n   input                                         read_data_valid_i,\n   input                                         ram_valid_i,\n   output reg                                    ALMOST_EMPTY = 1'b1,\n   output reg                                    ALMOST_FULL = C_FULL_FLAGS_RST_VAL,\n   output      [C_DOUT_WIDTH-1:0]                DOUT,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    EMPTY_FB = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL,\n   output                                        OVERFLOW,\n   output                                        PROG_EMPTY,\n   output                                        PROG_FULL,\n   output                                        VALID,\n   output      [C_RD_DATA_COUNT_WIDTH-1:0]       RD_DATA_COUNT,\n   output                                        UNDERFLOW,\n   output                                        WR_ACK,\n   output      [C_WR_DATA_COUNT_WIDTH-1:0]       WR_DATA_COUNT,\n   output                                        SBITERR,\n   output                                        DBITERR\n  );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   \n  \n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   \n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;\n   // Array that holds the error injection type (single/double bit error) on \n   // a specific write operation, which is returned on read to corrupt the\n   // output data.\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   //The amount of data stored in the FIFO at any time is given\n   // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK\n   // domain.\n   //num_wr_bits is calculated by considering the total words in the FIFO,\n   // and the state of the read pointer (which may not have yet crossed clock\n   // domains.)\n   //num_rd_bits is calculated by considering the total words in the FIFO,\n   // and the state of the write pointer (which may not have yet crossed clock\n   // domains.)\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   wire                        wr_rst_i = WR_RST;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n   wire                        rd_rst_i = RD_RST;\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n\n\n\n   // Delayed ram_rd_en is needed only for STD Embedded register option\n   generate\n     if (C_PRELOAD_LATENCY == 2) begin : grd_d\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n       end\n     end\n   endgenerate\n   \n    generate\n     if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n           fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n       end\n     end\n   endgenerate\n\n  \n\n   // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;\n     end else begin : rdl // Read depth lesser than or equal to write depth\n       assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n     end\n   endgenerate\n\n   // Generate Empty and Almost Empty\n  // ram_rd_en used to determine EMPTY should depend on the EMPTY.\n   assign ram_rd_en        = RD_EN & !EMPTY;\n   assign empty_int        = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));\n   assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));\n\n   // Register Empty and Almost Empty\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else begin\n         rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};\n\n         if (empty_int)\n           EMPTY           <= #`TCQ 1'b1;\n         else\n           EMPTY           <= #`TCQ 1'b0;\n\n         if (!EMPTY) begin\n           if (almost_empty_int)\n             ALMOST_EMPTY  <= #`TCQ 1'b1;\n           else\n             ALMOST_EMPTY  <= #`TCQ 1'b0;\n         end\n       end // rd_rst_i\n     end // always\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY_FB     <= 1'b1;\n       end else begin\n         if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else if (empty_int)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else\n           EMPTY_FB   <= #`TCQ 1'b0;\n       end // rd_rst_i\n     end // always\n\n   // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;\n     end else begin : wdl // Write depth lesser than or equal to read depth\n       assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n     end\n   endgenerate\n\n  // Generate FULL and ALMOST_FULL\n  // ram_wr_en used to determine FULL should depend on the FULL.\n  assign ram_wr_en       = WR_EN & !FULL;\n  assign full_int        = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));\n  assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));\n\n   // Register FULL and ALMOST_FULL Empty\n   always @ (posedge WR_CLK or posedge RST_FULL_FF)\n     begin\n       if (RST_FULL_FF & C_HAS_RST) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else begin\n         if (full_int) begin\n           FULL           <= #`TCQ 1'b1;\n         end else begin\n           FULL           <= #`TCQ 1'b0;\n         end\n\n         if (RST_FULL_GEN) begin\n           ALMOST_FULL    <= #`TCQ 1'b0;\n         end else if (!FULL) begin\n           if (almost_full_int)\n             ALMOST_FULL  <= #`TCQ 1'b1;\n           else\n             ALMOST_FULL  <= #`TCQ 1'b0;\n         end\n       end // wr_rst_i\n     end // always\n   always @ (posedge WR_CLK or posedge wr_rst_i)\n     begin\n       if (wr_rst_i) begin\n         wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};\n       end else begin\n         wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};\n       end // wr_rst_i\n     end // always\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i) begin\n           stage1_valid     <= 0;\n           stage2_valid     <= 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n   //Pointers passed into opposite clock domain\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_EMPTY.\n   wire [31:0] num_read_words_pe = \n     num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_FULL.\n   wire [31:0] num_write_words_pf =\n     num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n    \n    \n   /***************************************************************************\n    * Internal registers and wires\n    **************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire [C_DOUT_WIDTH-1:0] ideal_dout_out;      \n   wire valid_i;\n   wire valid_out1;\n   wire valid_out2;\n   wire valid_out;  \n   wire underflow_i;\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]               err_type                 = 0;\n   reg [1:0]               err_type_d1              = 0;\n   reg [1:0]               err_type_both              = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout               = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_d1            = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_both            = 0;\n   reg                     ideal_wr_ack             = 0;\n   reg                     ideal_valid              = 0;\n   reg                     ideal_overflow           = C_OVERFLOW_LOW;\n   reg                     ideal_underflow          = C_UNDERFLOW_LOW;\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   reg         valid_d1     = 0;\n   reg         valid_d2     = 0; \n   \n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n   \n\n  /****************************************************************************\n   * Function Declarations\n   ***************************************************************************/\n\n  /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n      if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n    end\n  endtask\n\n  /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n  /***********************************************************************\n  * hexstr_conv\n  *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n  ***********************************************************************/\n  function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_d2           = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n    end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the \n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n    wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;   \n   wire RD_CLK;\n   wire RD_EN;\n   wire RST;\n   wire WR_CLK;\n   wire WR_EN;\n    */\n\n   //***************************************************************************\n   // Dout may change behavior based on latency\n   //***************************************************************************\n   assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?\n                         ideal_dout_d1: ideal_dout;   \n   assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; \n\n   //***************************************************************************\n   // Assign SBITERR and DBITERR based on latency \n   //***************************************************************************\n   assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                    (C_PRELOAD_LATENCY == 2 &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?\n                    err_type_d1[0]: err_type[0]; \n   assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                    (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                    err_type_d1[1]: err_type[1]; \n  \n   //***************************************************************************\n   // Safety-ckt logic with embedded reg/fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n       //  if (C_HAS_VALID == 1) begin\n       //       assign valid_out = valid_d1;\n       //  end\n             \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)\n          begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else \n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n          end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                  @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n           end\n           else begin\n                   if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                   end\n             end \n           end  \n      end \n      endgenerate   \n\n//***************************************************************************\n   // Safety-ckt logic with embedded reg + fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else begin\n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n               fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n          end\n        end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   ideal_dout_both <= #`TCQ dout_reset_val;\n              end\n           end else begin\n             if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n              \n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n             end\n           end \n         end      \n      end \n      endgenerate    \n \n   //***************************************************************************\n   // Overflow may be active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_OVERFLOW==1) begin : blockOF1\n   assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n      end\n   endgenerate\n\n   assign PROG_EMPTY = ideal_prog_empty;\n   assign PROG_FULL  = ideal_prog_full;\n\n   //***************************************************************************\n   // Valid may change behavior based on latency or active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_VALID==1) begin : blockVL1\n   assign valid_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;\n   assign valid_out1 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?\n                       valid_d1: valid_i;  \n   assign valid_out2 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?\n                       valid_d2: valid_i; \n   assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;\n   assign VALID     = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Underflow may change behavior based on latency or active-low   \n   //***************************************************************************\n   generate\n      if (C_HAS_UNDERFLOW==1) begin : blockUF1\n   assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;\n   assign UNDERFLOW   = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n    end\n   endgenerate\n\n   //***************************************************************************\n   // Write acknowledge may be active low\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_ACK==1) begin : blockWK1\n   assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext\n\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_wr_pntr = 0;\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_rd_pntr = 0;\n      wire [C_PNTR_WIDTH-1:0]  diff_wr_rd_tmp;\n      wire [C_PNTR_WIDTH:0]    diff_wr_rd;\n      reg  [C_PNTR_WIDTH:0]    wr_data_count_i  = 0;\n        always @* begin\n          if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = 0;\n            adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n          end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin\n            adjusted_rd_pntr = rd_pntr_wr;\n            adjusted_wr_pntr = 0;\n            adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n          end else begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = rd_pntr_wr;\n          end\n        end // always @*\n\n        assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;\n        assign diff_wr_rd     = {1'b0,diff_wr_rd_tmp};\n\n        always @ (posedge wr_rst_i or posedge WR_CLK)\n        begin\n            if (wr_rst_i)\n              wr_data_count_i <= 0;\n            else\n              wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;\n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n\n        always @* begin\n          if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];\n          else\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n        end // always @*\n      end // wdc_fwft_ext\n   endgenerate\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   reg  [C_RD_PNTR_WIDTH:0]    rdc_fwft_ext_as  = 0;\n\n   generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n\n\n   always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= 0;\n            end else begin\n              if (!stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 0;\n              else if (!stage1_valid && stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 1;\n              else\n                rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;\n            end \n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n      end // rdc_fwft_ext\n end\n   endgenerate\n\n\n  generate if (C_USE_EMBEDDED_REG == 3) begin\n     if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n        wire [C_RD_PNTR_WIDTH:0]  diff_rd_wr_1;\n   //     assign diff_rd_wr_1 = diff_rd_wr +2'h2;\n\n       always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= #`TCQ 0;\n            end else begin\n          //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))\n          //    rdc_fwft_ext_as <= 1'b0;\n          //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) \n          //    rdc_fwft_ext_as <= 1'b1;\n          //else\n            rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;\n        end\n\n\n\nend\nend\nend\nendgenerate\n          \n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1) begin : grdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?\n          rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :\n          rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?\n          wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :\n          wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n\n  /**************************************************************************\n  * Assorted registers for delayed versions of signals\n  **************************************************************************/\n  //Capture delayed version of valid\n  generate\n      if (C_HAS_VALID==1) begin : blockVL2\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n      valid_d1 <= 1'b0;\n      valid_d2 <= 1'b0;\n    end else begin\n      valid_d1 <= #`TCQ valid_i;\n      valid_d2 <= #`TCQ valid_d1;\n    end \n//    if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin\n  //      valid_d2 <= #`TCQ valid_d1;\n      //  end \n  end \n      end\n endgenerate  \n   \n  //Capture delayed version of dout\n  /**************************************************************************\n    *embedded/fabric reg with no safety ckt\n    **************************************************************************/\n  generate \n       if (C_USE_EMBEDDED_REG < 3) begin\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n       if (C_USE_DOUT_RST == 1'b1) begin\n         @(posedge RD_CLK)\n           ideal_dout_d1   <= #`TCQ dout_reset_val;\n           ideal_dout   <= #`TCQ dout_reset_val;\n       end\n      // Reset err_type only if ECC is not selected\n      if (C_USE_ECC == 0)\n        err_type_d1     <= #`TCQ 0;\n     end else if (ram_rd_en_d1) begin\n      ideal_dout_d1   <= #`TCQ ideal_dout;\n      err_type_d1     <= #`TCQ err_type;\n           end    \n  end  \n   \nend  \nendgenerate \n/**************************************************************************\n    *embedded + fabric reg with no safety ckt\n    **************************************************************************/\n\ngenerate \n  if (C_USE_EMBEDDED_REG == 3) begin\n    always @(posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i == 1'b1) begin\n        if (C_USE_DOUT_RST == 1'b1) begin\n           @(posedge RD_CLK)\n             ideal_dout    <= #`TCQ dout_reset_val;\n             ideal_dout_d1   <= #`TCQ dout_reset_val;\n             ideal_dout_both   <= #`TCQ dout_reset_val;\n        end\n        // Reset err_type only if ECC is not selected\n        if (C_USE_ECC == 0) begin\n          err_type_d1     <= #`TCQ 0;\n          err_type_both   <= #`TCQ 0;\n        end\n      end else begin\n         if (ram_rd_en_d1) begin\n           ideal_dout_both   <= #`TCQ ideal_dout;\n           err_type_both     <= #`TCQ err_type;\n         end    \n         if (fab_rd_en_d1) begin\n           ideal_dout_d1   <= #`TCQ ideal_dout_both;\n           err_type_d1     <= #`TCQ err_type_both;\n         end\n      end\n    end  \n  end  \nendgenerate \n\n  \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate\n     if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n       always @(posedge WR_CLK) begin\n         ideal_overflow    <= #`TCQ WR_EN & FULL;\n       end\n     end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n       always @(posedge WR_CLK) begin\n         //ideal_overflow    <= #`TCQ WR_EN & (FULL | wr_rst_i);\n         ideal_overflow    <= #`TCQ WR_EN & (FULL );\n       end\n     end\n   endgenerate\n\n   generate\n     if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ EMPTY & RD_EN;\n       end\n     end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ (EMPTY) & RD_EN;\n         //ideal_underflow    <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;\n       end\n     end\n   endgenerate\n\n   /**************************************************************************\n   * Write/Read Pointer Synchronization\n   **************************************************************************/\n   localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;\n   wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   genvar gss;\n\n   generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (C_WR_PNTR_WIDTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_i), \n         .CLK      (RD_CLK), \n         .DIN      (wr_pntr_sync_stgs[gss-1]), \n         .DOUT     (wr_pntr_sync_stgs[gss])\n        );\n \n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (C_RD_PNTR_WIDTH)\n        )\n     wr_stg_inst\n        (\n         .RST      (wr_rst_i), \n         .CLK      (WR_CLK), \n         .DIN      (rd_pntr_sync_stgs[gss-1]), \n         .DOUT     (rd_pntr_sync_stgs[gss])\n        );\n   end endgenerate // Sync_stage_inst\n\n   assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;\n   assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;\n   always@* begin\n     wr_pntr_rd           <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n     rd_pntr_wr           <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n   end\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp\n     if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)\n       wr_pntr           <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)\n       wr_pntr           <= #`TCQ 0;\n   end\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (wr_rst_i == 1'b1) begin\n       num_wr_bits       <= 0;\n       next_num_wr_bits   = 0;\n       wr_ptr            <= C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= C_RD_DEPTH - 1;\n       ideal_wr_ack      <= 0;\n       ideal_wr_count    <= 0;\n       tmp_wr_listsize    = 0;\n       rd_ptr_wrclk_next <= 0;\n       wr_pntr_rd1       <= 0;\n\n     end else begin //wr_rst_i==0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       //If this is a write, handle the write by adding the value\n       // to the linked list, and updating all outputs appropriately\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD \n             >= C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full, but reporting full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //With DEPTH-1 words in the FIFO, it is almost_full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n\n           //If the FIFO is completely empty, but it is\n           // reporting FULL for some reason (like reset)\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=\n                C_FIFO_WR_DEPTH-2) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //FIFO is really not close to full, so change flag status.\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n           end //(tmp_wr_listsize == 0)\n\n         end else begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=\n              C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack       <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count     <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;\n\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //This write is CAUSING the FIFO to go full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is 2 from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == \n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits =  next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Still 2 from full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is not close to being full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <\n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //wr_rst_i==0\n   end // gen_fifo_w\n\n\n  /***************************************************************************\n   * Programmable FULL flags\n   ***************************************************************************/\n\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;\n\n   generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;\n   end else begin // STD\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;\n   end endgenerate\n\n   always @(posedge WR_CLK or posedge wr_rst_i) begin\n\n     if (wr_rst_i == 1'b1) begin\n       diff_pntr         <= 0;\n     end else begin\n       if (ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);\n       else if (!ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);\n    end\n  end\n\n\n   always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf\n\n     if (RST_FULL_FF & C_HAS_RST) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else begin\n\n       if (RST_FULL_GEN)\n         ideal_prog_full   <= #`TCQ 0;\n       //Single Programmable Full Constant Threshold\n       else if (C_PROG_FULL_TYPE == 1) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else\n             ideal_prog_full <= #`TCQ 0;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Constant Thresholds\n       end else if (C_PROG_FULL_TYPE == 2) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else if (diff_pntr < pf_thr_negate_val)\n             ideal_prog_full <= #`TCQ 0;\n           else\n             ideal_prog_full <= #`TCQ ideal_prog_full;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Single Programmable Full Threshold Input\n       end else if (C_PROG_FULL_TYPE == 3) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH)\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Threshold Inputs\n       end else if (C_PROG_FULL_TYPE == 4) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH_ASSERT)\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < PROG_FULL_THRESH_NEGATE)\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       end // C_PROG_FULL_TYPE\n\n     end //wr_rst_i==0\n   end //\n\n   \n   /**************************************************************************\n   * Read Domain Logic\n   **************************************************************************/\n\n\n   /*********************************************************\n    * Programmable EMPTY flags\n    *********************************************************/\n   //Determine the Assert and Negate thresholds for Programmable Empty\n\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd      = 0;\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe\n\n     if (rd_rst_i & C_HAS_RST) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else begin\n       if (ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;\n       else if (!ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr);\n       else\n         diff_pntr_rd       <=  #`TCQ diff_pntr_rd;\n  \n       if (C_PROG_EMPTY_TYPE == 1) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 2) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 3) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 4) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end  //C_PROG_EMPTY_TYPE\n     end\n   end // gen_pe\n\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;\n   end endgenerate // single_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;\n   end endgenerate // multiple_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;\n   end endgenerate // single_multiple_pe_thr_const\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp\n     if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n       rd_pntr            <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)\n       rd_pntr            <= #`TCQ 0;\n   end\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rd_rst_i & C_HAS_RST) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n     end else begin //rd_rst_i==0\n\n       rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 1\n       /*****************************************************************/\n       if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Reminder that FIFO is still empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end // if (tmp_rd_listsize <= 0)\n\n             //If the FIFO is one from empty, but it is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 1)\n\n             //If the FIFO is two from empty, and is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Fifo has two words, so is neither empty or almost empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 2)\n\n             //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid <= #`TCQ 1'b0;\n                 //Note that the FIFO is No Longer Empty or Almost Empty\n\n                 ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n               end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n             end // else: if(ideal_empty == 1'b1)\n\n           else //if (ideal_empty == 1'b0)\n             begin\n\n               //If the FIFO is completely full, and we are successfully reading from it\n               if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)\n\n               //If the FIFO is not close to being empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n               //If the FIFO is two from empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Fifo is not yet empty. It is going almost_empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n\n               //If the FIFO is one from empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Note that FIFO is GOING empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 1)\n\n\n               //If the FIFO is completely empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n                 begin\n                   //Do not change the contents of the FIFO\n\n                   //Do not acknowledge the read from empty FIFO\n                   ideal_valid        <= #`TCQ 1'b0;\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize <= 0)\n\n             end // if (ideal_empty == 1'b0)\n\n           end //(RD_EN == 1'b1)\n\n         else //if (RD_EN == 1'b0)\n           begin\n             //If user did not attempt a read, do not give an ack or err\n             ideal_valid          <= #`TCQ 1'b0;\n\n             ideal_rd_count       <= #`TCQ num_read_words_sized_i;\n\n           end // else: !if(RD_EN == 1'b1)\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 0\n       /*****************************************************************/\n       end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty, but it is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty, and is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Fifo has two words, so is neither empty or almost empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                         (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that the FIFO is No Longer Empty or Almost Empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n           end else begin\n\n             //If the FIFO is completely full, and we are successfully reading from it\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is not close to being empty\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                          (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Fifo is not yet empty. It is going almost_empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Note that FIFO is GOING empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is completely empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if (tmp_rd_listsize <= 0)\n\n           end // if (ideal_empty == 1'b0)\n\n         end else begin//(RD_EN == 1'b0)\n\n         \n           //If user did not attempt a read, do not give an ack or err\n           ideal_valid           <= #`TCQ 1'b0;\n           ideal_rd_count        <= #`TCQ num_read_words_sized_i;\n\n         end // else: !if(RD_EN == 1'b1)\n       end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //rd_rst_i==0\n   end //always gen_fifo_r_as\n\nendmodule // fifo_generator_v13_2_5_bhv_ver_as\n\n\n/*******************************************************************************\n * Declaration of Low Latency Asynchronous FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_beh_ver_ll_afifo\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_FIFO_TYPE                    = 0\n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   output reg  [C_DOUT_WIDTH-1:0]                DOUT = 0,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL\n  );\n\n  //-----------------------------------------------------------------------------\n  // Low Latency Asynchronous FIFO\n  //-----------------------------------------------------------------------------\n\n  // Memory which will be used to simulate a FIFO\n  reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n  integer i;\n  initial begin\n    for (i = 0; i < C_WR_DEPTH; i = i + 1)\n      memory[i] = 0;\n  end\n\n  reg  [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;\n  wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;\n  reg  [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;\n  reg                        ll_afifo_full    = 1'b0;\n  reg                        ll_afifo_empty   = 1'b1;\n  wire                       write_allow;\n  wire                       read_allow;\n\n  assign write_allow = WR_EN & ~ll_afifo_full;\n  assign read_allow  = RD_EN & ~ll_afifo_empty;\n\n  //-----------------------------------------------------------------------------\n  // Write Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      wr_pntr_ll_afifo   <= 0;\n    else if (write_allow)\n      wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Read Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      rd_pntr_ll_afifo_q   <= 0;\n    else\n      rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;\n  end\n  assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;\n  \n  //-----------------------------------------------------------------------------\n  // Fill the Memory\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK) begin\n    if (write_allow)\n      memory[wr_pntr_ll_afifo] <= #`TCQ DIN;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate DOUT\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK) begin\n      DOUT <= #`TCQ memory[rd_pntr_ll_afifo];\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate EMPTY\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      ll_afifo_empty   <= 1'b1;\n    else\n      ll_afifo_empty   <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | \n                           (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate FULL\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      ll_afifo_full   <= 1'b1;\n    else\n      ll_afifo_full   <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | \n                           (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));\n  end\n\n  always @* begin\n    FULL  <= ll_afifo_full;\n    EMPTY <= ll_afifo_empty;\n  end\n\nendmodule // fifo_generator_v13_2_5_beh_ver_ll_afifo\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_ss\n   \n  /**************************************************************************\n   * Declare user parameters and their defaults\n   *************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0 \n   )\n   \n  /**************************************************************************\n   * Declare Input and Output Ports\n   *************************************************************************/\n   (\n    //Inputs\n    input                                 SAFETY_CKT_WR_RST,\n    input                                 CLK,\n    input       [C_DIN_WIDTH-1:0]         DIN,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_ASSERT,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_NEGATE,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_ASSERT,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_NEGATE,\n    input                                 RD_EN,\n    input                                 RD_EN_USER,\n    input                                 USER_EMPTY_FB,\n    input                                 RST,\n    input                                 RST_FULL_GEN,\n    input                                 RST_FULL_FF,\n    input                                 SRST,\n    input                                 WR_EN,\n    input                                 INJECTDBITERR,\n    input                                 INJECTSBITERR,\n    input                                 WR_RST_BUSY,\n    input                                 RD_RST_BUSY,\n                                    \n    //Outputs                       \n    output                                ALMOST_EMPTY,\n    output                                ALMOST_FULL,\n    output reg   [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,\n    output       [C_DOUT_WIDTH-1:0]       DOUT,\n    output                                EMPTY,\n    output reg                            EMPTY_FB = 1'b1,\n    output                                FULL,\n    output                                OVERFLOW,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]    RD_DATA_COUNT,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]    WR_DATA_COUNT,\n    output                                PROG_EMPTY,\n    output                                PROG_FULL,\n    output                                VALID,\n    output                                UNDERFLOW,\n    output                                WR_ACK,\n    output                                SBITERR,\n    output                                DBITERR\n   );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;\n   wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n   localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; \n\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n   localparam  EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //localparam  EXTRA_WORDS_PE_PARAM  = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not \n   //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.\n   // Therefore, during SRST, all the FULL flags reset to 0.\n   localparam                      C_HAS_FAST_FIFO = 0;\n   localparam                      C_FIFO_WR_DEPTH = C_WR_DEPTH;\n   localparam                      C_FIFO_RD_DEPTH = C_RD_DEPTH;\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;\n   localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;\n   localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;\n   localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n  localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; \n  localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; \n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   \n   /**************************************************************************\n    * Internal Registers and wires\n    *************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire                           underflow_i;\n   wire                           valid_i;\n   wire                           valid_out;\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_reg = 1'b0;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n   wire                         srst_rrst_busy;\n\n\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]                      err_type           = 0;\n   reg [1:0]                      err_type_d1        = 0;\n   reg [1:0]                      err_type_both      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout         = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_d1      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_both      = 0;\n   wire [C_DOUT_WIDTH-1:0]        ideal_dout_out;\n   wire                           fwft_enabled;\n   reg                            ideal_wr_ack       = 0;\n   reg                            ideal_valid        = 0;\n   reg                            ideal_overflow     = C_OVERFLOW_LOW;\n   reg                            ideal_underflow    = C_UNDERFLOW_LOW;\n\n   reg                            full_i             = C_FULL_FLAGS_RST_VAL;\n   reg                            full_i_temp        = 0;\n   reg                            empty_i            = 1;\n   reg                            almost_full_i      = 0;\n   reg                            almost_empty_i     = 1;\n   reg                            prog_full_i        = 0;\n   reg                            prog_empty_i       = 1;\n   reg [C_WR_PNTR_WIDTH-1:0]      wr_pntr            = 0;\n   reg [C_RD_PNTR_WIDTH-1:0]      rd_pntr            = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg [C_RD_PNTR_WIDTH-1:0]      diff_count         = 0;\n\n   reg                            write_allow_q      = 0;\n   reg                            read_allow_q       = 0;\n   reg                            valid_d1           = 0;\n   reg                            valid_both           = 0;\n   reg                            valid_d2           = 0;\n   wire                           rst_i;\n   wire                           srst_i;\n\n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]         dout_reset_val = 0;\n\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n\n\n\n   /****************************************************************************\n    * Function Declarations\n    ***************************************************************************/\n\n   /****************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***************************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin\n        case (def_data[7:0])\n          8'b00000000 : begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default : begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1) begin\n          if ((index*4)+j < C_DOUT_WIDTH) begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   //reg         valid_d1     = 0;\n   \n   \n   //user specified value for reseting the size of the fifo\n   //reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n\n\n /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n     if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n\n     end\n  endtask\n\n\n   \n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_dout_both    = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_both         = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n\n   end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the\n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n   wire CLK;\n   wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;\n   wire RD_EN;\n   wire RST;\n   wire WR_EN;\n    */\n\n  // Assign ALMOST_EPMTY\n  generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae\n    assign ALMOST_EMPTY = almost_empty_i;\n  end else begin : gnae\n    assign ALMOST_EMPTY = 0;\n  end endgenerate // gae\n\n  // Assign ALMOST_FULL\n  generate if (C_HAS_ALMOST_FULL==1) begin : gaf\n    assign ALMOST_FULL  = almost_full_i;\n  end else begin : gnaf\n    assign ALMOST_FULL  = 0;\n  end endgenerate // gaf\n\n   // Dout may change behavior based on latency\n  localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?\n                         ideal_dout_d1: ideal_dout; \n  assign DOUT = ideal_dout_out;\n\n  // Assign SBITERR and DBITERR based on latency \n  assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[0]: err_type[0]; \n  assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[1]: err_type[1]; \n\n  assign EMPTY         = empty_i;\n  assign FULL          = full_i;\n  //saftey_ckt with one register\n\n  generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)\n          begin\n          if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n              valid_d1 <= #`TCQ 1'b0;\n          end\n          else begin\n               ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n               valid_d1 <= #`TCQ valid_i;\n          end\n          end\n          \n           always@(posedge rst_delayed_sft2 or posedge CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n              end\n           else if (srst_rrst_busy == 1'b1) begin\n                   if (C_USE_DOUT_RST == 1'b1) begin\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   end\n           end else if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                end\n           end   \n      end //if \n      endgenerate   \n\n//safety ckt with both registers\n\ngenerate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK) begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            valid_d1 <= #`TCQ 1'b0;\n          end else begin\n            ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n            fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n            valid_both <= #`TCQ valid_i;\n            valid_d1 <= #`TCQ valid_both;\n          end\n        end\n\n        always@(posedge rst_delayed_sft2 or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                  ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else if (srst_rrst_busy == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else begin \n            if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n            end\n          end\n        end\n      end //if \n      endgenerate    \n \n \n  //Overflow may be active-low\n  generate if (C_HAS_OVERFLOW==1) begin : gof\n    assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n  end else begin : gnof\n    assign OVERFLOW = 0;\n  end endgenerate // gof\n\n  assign PROG_EMPTY    = prog_empty_i;\n  assign PROG_FULL     = prog_full_i;\n\n   //Valid may change behavior based on latency or active-low\n  generate if (C_HAS_VALID==1) begin : gvalid\n    assign valid_i       = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;\n    assign valid_out     = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?\n                            valid_d1 : valid_i; \n    assign VALID         = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n  end else begin : gnvalid\n    assign VALID         = 0;\n  end endgenerate // gvalid\n\n  //Trim data count differently depending on set widths\n  generate if (C_HAS_DATA_COUNT == 1) begin : gdc\n    always @* begin\n      diff_count <= wr_pntr - rd_pntr;\n      if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin\n        DATA_COUNT[C_RD_PNTR_WIDTH-1:0]  <= diff_count;\n        DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; \n      end else begin\n        DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];\n      end\n    end\n//  end else begin : gndc\n//    always @* DATA_COUNT <= 0;\n  end endgenerate // gdc\n\n  //Underflow may change behavior based on latency or active-low\n  generate if (C_HAS_UNDERFLOW==1) begin : guf\n    assign underflow_i   = ideal_underflow;\n    assign UNDERFLOW     = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n  end else begin : gnuf\n    assign UNDERFLOW     = 0;\n  end endgenerate // guf\n \n\n  //Write acknowledge may be active low \n  generate if (C_HAS_WR_ACK==1) begin : gwr_ack\n    assign WR_ACK        = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n  end else begin : gnwr_ack\n    assign WR_ACK        = 0;\n  end endgenerate // gwr_ack\n\n\n  /*****************************************************************************\n   * Internal reset logic \n   ****************************************************************************/\n  assign srst_i        = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;\n  assign rst_i            = C_HAS_RST ? RST : 0;\n  assign srst_wrst_busy   = srst_i;\n  assign srst_rrst_busy   = srst_i;\n\n   /**************************************************************************\n    * Assorted registers for delayed versions of signals\n    **************************************************************************/\n   //Capture delayed version of valid\n   generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20\n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1 <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n           end else begin\n              valid_d1 <= #`TCQ valid_i;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n     end \n   endgenerate // blockVL20\n\n  generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin \n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1   <= 1'b0;\n           valid_both <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n              valid_both <= #`TCQ 1'b0;\n              \n           end else begin\n              valid_both <= #`TCQ valid_i;\n               valid_d1 <= #`TCQ valid_both;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n  end\n endgenerate // blockVL20\n\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge CLK or posedge rst_i) begin\n         if (rst_i) begin\n           stage1_valid     <= #`TCQ 0;\n           stage2_valid     <= #`TCQ 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n\n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc\n       assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc\n       assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n   \n   //reg ram_rd_en_d1 = 1'b0;\n   //Capture delayed version of dout\n   generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         ram_rd_en_d1 <= #`TCQ 1'b0;\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n        end\n      end else begin\n         ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n         if (srst_rrst_busy) begin\n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            // Reset err_type only if ECC is not selected\n            if (C_USE_ECC == 0) begin\n               err_type_d1   <= #`TCQ 0;\n               err_type_both <= #`TCQ 0;\n            end\n            // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n            if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n            end \n         if (C_USE_DOUT_RST == 1) begin\n           // @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         end else begin\n            if (ram_rd_en_d1 ) begin\n            ideal_dout_d1 <= #`TCQ ideal_dout;\n            err_type_d1   <= #`TCQ err_type;\n            end\n         end\n      end    \n   end   // always\nend\nendgenerate \n\n//no safety ckt with both registers\n generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n          ram_rd_en_d1 <= #`TCQ 1'b0;\n          fab_rd_en_d1 <= #`TCQ 1'b0;\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val; \n            \n      end\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val;\n       end\n      end else begin\n         if (srst_rrst_busy) begin \n           ram_rd_en_d1 <= #`TCQ 1'b0;\n           fab_rd_en_d1 <= #`TCQ 1'b0;\n           // Reset err_type only if ECC is not selected\n           if (C_USE_ECC == 0) begin\n              err_type_d1   <= #`TCQ 0;\n              err_type_both <= #`TCQ 0;\n           end\n           // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n           if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n              ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end \n           if (C_USE_DOUT_RST == 1) begin\n             ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end\n         end else begin\n           ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n           fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);\n           if (ram_rd_en_d1 ) begin\n             ideal_dout_both <= #`TCQ ideal_dout;\n             err_type_both   <= #`TCQ err_type;\n           end\n           if (fab_rd_en_d1 ) begin\n             ideal_dout_d1 <= #`TCQ ideal_dout_both;\n             err_type_d1   <= #`TCQ err_type_both;\n           end\n         end\n      end    \n   end   // always\nend\nendgenerate \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n     always @(posedge CLK) begin\n       ideal_overflow    <= #`TCQ WR_EN & full_i;\n     end\n   end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n     always @(posedge CLK) begin\n       //ideal_overflow    <= #`TCQ WR_EN & (rst_i | full_i);\n       ideal_overflow    <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);\n     end\n   end endgenerate // blockOF20\n \n   generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n     always @(posedge CLK) begin\n       ideal_underflow   <= #`TCQ empty_i & RD_EN;\n     end\n   end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n     always @(posedge CLK) begin\n       //ideal_underflow   <= #`TCQ (rst_i | empty_i) & RD_EN;\n       ideal_underflow   <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;\n     end\n   end endgenerate // blockUF20\n\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n\n  /*************************************************************************\n   * Write and Read Logic  \n   ************************************************************************/\n   wire              write_allow;\n   wire              read_allow;\n   wire              read_allow_dc;\n   wire              write_only;\n   wire              read_only;\n   //wire              write_only_q;\n   reg              write_only_q;\n   //wire              read_only_q;\n   reg              read_only_q;\n   reg              full_reg;\n   reg              rst_full_ff_reg1;\n   reg              rst_full_ff_reg2;\n   wire              ram_full_comb;\n   wire              carry;\n   \n   assign write_allow  = WR_EN & ~full_i;\n   assign read_allow   = RD_EN & ~empty_i;\n   assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;\n   //assign write_only   = write_allow & ~read_allow;\n   //assign write_only_q = write_allow_q;\n   //assign read_only    = read_allow    & ~write_allow;\n   //assign read_only_q  = read_allow_q ;\n   wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;\n   wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;\n   wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;\n\n   assign diff_pntr_pe_max = DIFF_MAX_RD;\n   assign diff_pntr_max = DIFF_MAX_WR;\n\n\n\n   generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym\n    assign write_only   = write_allow & ~read_allow;\n    assign read_only    = read_allow    & ~write_allow;\n    end endgenerate\n    generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd\n     assign read_only   = read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;\n     assign write_only    = write_allow    & ~(read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n    generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr\n     assign read_only   = read_allow & ~(write_allow  & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n     assign write_only    = write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;\n    end endgenerate\n\n\n   //-----------------------------------------------------------------------------\n   // Write and Read pointer generation\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       wr_pntr         <= 0;\n       rd_pntr         <= 0;\n     end else begin\n       if (srst_i) begin\n         wr_pntr       <= #`TCQ 0;\n         rd_pntr       <= #`TCQ 0;\n       end else begin\n         if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;\n         if (read_allow)  rd_pntr <= #`TCQ rd_pntr + 1;\n       end\n     end\n   end\n\n   generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout\n   always @(posedge CLK) begin\n     if (write_allow) begin\n       if (ENABLE_ERR_INJECTION == 1)\n         memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};\n       else\n         memory[wr_pntr] <= #`TCQ DIN;\n     end\n   end\n\n   reg  [C_DATA_WIDTH-1:0] dout_tmp_q;\n   reg [C_DATA_WIDTH-1:0] dout_tmp = 0;\n   reg  [C_DATA_WIDTH-1:0] dout_tmp1 = 0;\n   always @(posedge CLK) begin\n     dout_tmp_q <= #`TCQ ideal_dout;\n   end\n\n\n\n     always @* begin\n       if (read_allow)\n         ideal_dout <= memory[rd_pntr];\n       else\n         ideal_dout <= dout_tmp_q;\n     end\n   end endgenerate // gll_dm_dout\n\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   assign ram_rd_en        = RD_EN & !EMPTY;\n\n   //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   generate if (C_FIFO_TYPE != 2) begin : gnll_din\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i == 1'b1) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n\n     end else begin //rst_i==0\n     if (srst_wrst_busy) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n     end else begin//srst_i=0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n         end else begin\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error  \n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           //end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //srst_i==0\n     end //wr_rst_i==0\n   end // gen_fifo_w\n    end endgenerate\n\n   generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout\n     always @(posedge CLK) begin\n       if (rst_i || srst_rrst_busy) begin\n         if (C_USE_DOUT_RST == 1) begin\n           ideal_dout <= #`TCQ dout_reset_val;\n           ideal_dout_both <= #`TCQ dout_reset_val;\n         end\n       end\n     end\n    end endgenerate\n\n\n\n\n   generate if (C_FIFO_TYPE != 2) begin : gnll_dout\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_r\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n\n     end else begin //rd_rst_i==0\n     if (srst_rrst_busy) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets synchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= #`TCQ 0;\n         err_type_both    <= #`TCQ 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n      end //srst_i\n      else begin\n\n       //rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n         if (RD_EN == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end \n           else \n             begin\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n         end\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //s_rst_i==0\n     end //rd_rst_i==0\n   end //always\n  end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate diff_pntr for PROG_FULL generation\n   // Generate diff_pntr_pe for PROG_EMPTY generation\n   //-----------------------------------------------------------------------------\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         write_only_q   <= 1'b0;\n         read_only_q    <= 1'b0;\n         diff_pntr_reg1       <= 0;\n         diff_pntr_pe_reg1    <= 0;\n         diff_pntr_reg2       <= 0;\n         diff_pntr_pe_reg2    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_rrst_busy) begin\n           read_only_q  <= #`TCQ 1'b0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n           diff_pntr_pe_reg2  <= #`TCQ 0;\n          end\n          if (srst_wrst_busy) begin\n           write_only_q <= #`TCQ 1'b0;\n           diff_pntr_reg1     <= #`TCQ 0;\n           diff_pntr_reg2     <= #`TCQ 0;\n          end\n         end else begin\n           write_only_q <= #`TCQ write_only;\n           read_only_q  <= #`TCQ read_only;\n           diff_pntr_reg2  <= #`TCQ diff_pntr_reg1;\n           diff_pntr_pe_reg2  <= #`TCQ diff_pntr_pe_reg1;\n\n           // Add 1 to the difference pointer value when only write happens.\n           if (write_only)  \n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;\n           else\n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;\n\n           // Add 1 to the difference pointer value when write or both write & read or no write & read happen.\n           if (read_only)  \n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;\n           else\n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;\n         end\n       end\n     end\n   assign diff_pntr_pe = diff_pntr_pe_reg1;\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow\n\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym\n    assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};\n    assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         diff_pntr_pe_asym    <= 0;\n         diff_pntr_reg1       <= 0;\n         full_reg             <= 0;\n         rst_full_ff_reg1     <= 1;\n         rst_full_ff_reg2     <= 1;\n         diff_pntr_pe_reg1    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_wrst_busy)\n           diff_pntr_reg1     <= #`TCQ 0;\n          if (srst_rrst_busy)\n           full_reg             <=  #`TCQ 0;\n           rst_full_ff_reg1     <=  #`TCQ 1;\n           rst_full_ff_reg2     <=  #`TCQ 1;\n           diff_pntr_pe_asym    <=  #`TCQ 0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n         end else begin\n             diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;\n             full_reg          <= #`TCQ full_i;\n             rst_full_ff_reg1  <=  #`TCQ RST_FULL_FF;\n             rst_full_ff_reg2  <=  #`TCQ rst_full_ff_reg1;\n           if (~full_i) begin  \n             diff_pntr_reg1 <=  #`TCQ wr_pntr - adj_rd_pntr_wr;\n          end\n         end\n       end\n     end\n   assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));\n   assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow_asym\n\n\n   //-----------------------------------------------------------------------------\n   // Generate FULL flag\n   //-----------------------------------------------------------------------------\n   wire                 comp0;\n   wire                 comp1;\n   wire                 going_full;\n   wire                 leaving_full;\n \n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin :  gpad \t\n    assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;\n    assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin :  gtrim \n    assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n  end endgenerate\n\n   assign comp1         = (adj_rd_pntr_wr == (wr_pntr + 1'b1));\n   assign comp0         = (adj_rd_pntr_wr == wr_pntr);\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp\n     assign going_full    = (comp1 & write_allow & ~read_allow);\n     assign leaving_full  = (comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym\n      assign going_full = (comp1 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_full = (comp0 & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp \n      assign going_full = (comp1 & write_allow & ~read_allow);\n      assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n\n   assign ram_full_comb = going_full | (~leaving_full & full_i);\n\n   generate if (C_HAS_RST == 1) begin : grst_full\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF & C_HAS_RST)\n         full_i   <= C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_SRST == 1) begin : gsrst_full\n     always @(posedge CLK) begin\n       if (srst_wrst_busy)\n         full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_full\n     always @(posedge CLK) begin\n         full_i   <= #`TCQ ram_full_comb;\n     end\n   end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate EMPTY flag\n   //-----------------------------------------------------------------------------\n   wire                 ecomp0;\n   wire                 ecomp1;\n   wire                 going_empty;\n   wire                 leaving_empty;\n   wire                 ram_empty_comb;\n\n  \n generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin :  pad \t\n    assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n    assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin :  trim \n    assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n  end endgenerate\n\n   assign ecomp1         = (adj_wr_pntr_rd == (rd_pntr + 1'b1));\n   assign ecomp0         = (adj_wr_pntr_rd == rd_pntr);\n\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp\n     assign going_empty    = (ecomp1 & ~write_allow & read_allow);\n     assign leaving_empty  = (ecomp0 & write_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp\n      assign going_empty = (ecomp1 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_empty = (ecomp0 & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp \n      assign going_empty = (ecomp1 & ~write_allow & read_allow);\n      assign leaving_empty =(ecomp0 & write_allow);\n    end endgenerate\n\n\n\n    assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);\n\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       empty_i  <= 1'b1;\n     else if (srst_rrst_busy)\n       empty_i  <= #`TCQ 1'b1;\n     else\n       empty_i  <= #`TCQ ram_empty_comb;\n    end\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       EMPTY_FB     <= 1'b1;\n     end else begin\n       if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))\n         EMPTY_FB   <= #`TCQ 1'b1;\n       else\n         EMPTY_FB   <= #`TCQ ram_empty_comb;\n     end\n   end // always\n\n   //-----------------------------------------------------------------------------\n   // Generate Read and write data counts for asymmetic common clock\n   //-----------------------------------------------------------------------------\n\n    reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; \n    wire [C_GRTR_PNTR_WIDTH :0] ratio; \n    wire decr_by_one;\n    wire incr_by_ratio;\n    wire incr_by_one;\n    wire decr_by_ratio;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n\n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr \n      assign ratio         = C_DEPTH_RATIO_RD;\n      assign decr_by_one   = (IS_FWFT == 1)? read_allow_dc : read_allow;\n      assign incr_by_ratio = write_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (decr_by_one) begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc - 1;\n           else\n\t    count_dc <= #`TCQ count_dc - 1  + ratio ;\n\t end\n\t else begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc + ratio ;\n\tend\n       end\n       end\n\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n\n    end endgenerate\n\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd \n      assign ratio         = C_DEPTH_RATIO_WR;\n      assign incr_by_one   = write_allow;\n      assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (incr_by_one) begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc + 1;\n           else\n\t    count_dc <= #`TCQ count_dc + 1  - ratio ;\n\t end\n\t else begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc - ratio ;\n\tend\n       end\n       end\n\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n\n    end endgenerate\n\n\n\n\n\n\n   //-----------------------------------------------------------------------------\n   // Generate WR_ACK flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_wr_ack  <= 1'b0;\n     else if (srst_wrst_busy)\n       ideal_wr_ack  <= #`TCQ 1'b0;\n     else if (WR_EN & ~full_i)\n       ideal_wr_ack  <= #`TCQ 1'b1;\n     else\n       ideal_wr_ack  <= #`TCQ 1'b0;\n    end\n\n   //-----------------------------------------------------------------------------\n   // Generate VALID flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_valid  <= 1'b0;\n     else if (srst_rrst_busy)\n       ideal_valid  <= #`TCQ 1'b0;\n     else if (RD_EN & ~empty_i)\n       ideal_valid  <= #`TCQ 1'b1;\n     else\n       ideal_valid  <= #`TCQ 1'b0;\n    end\n\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_FULL flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss\n\n     wire                 fcomp2;\n     wire                 going_afull;\n     wire                 leaving_afull;\n     wire                 ram_afull_comb;\n\n\n   assign fcomp2         = (adj_rd_pntr_wr == (wr_pntr + 2'h2));\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp\n     assign going_afull    = (fcomp2 & write_allow & ~read_allow);\n     assign leaving_afull  = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym\n      assign going_afull = (fcomp2 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_afull = (comp1 & (~write_allow) & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp \n      assign going_afull = (fcomp2 & write_allow & ~read_allow);\n      assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n     assign ram_afull_comb  = going_afull | (~leaving_afull & almost_full_i);\n\n\n    generate if (C_HAS_RST == 1) begin : grst_afull\n      always @(posedge CLK or posedge RST_FULL_FF) begin\n        if (RST_FULL_FF & C_HAS_RST)\n          almost_full_i   <= C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_SRST == 1) begin : gsrst_afull\n      always @(posedge CLK) begin\n        if (srst_wrst_busy)\n          almost_full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_afull\n      always @(posedge CLK) begin\n          almost_full_i   <= #`TCQ ram_afull_comb;\n      end\n    end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_EMPTY flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss\n\n     wire                 ecomp2;\n     wire                 going_aempty;\n     wire                 leaving_aempty;\n     wire                 ram_aempty_comb;\n      \n     assign ecomp2          = (adj_wr_pntr_rd == (rd_pntr + 2'h2));\n   \n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp\n     assign going_aempty    = (ecomp2 & ~write_allow & read_allow);\n     assign leaving_aempty  = (ecomp1 & write_allow & ~read_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp\n      assign going_aempty = (ecomp2 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp \n      assign going_aempty = (ecomp2 & ~write_allow & read_allow);\n      assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);\n    end endgenerate\n\n\n     assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);\n\n     always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         almost_empty_i  <= 1'b1;\n       else if (srst_rrst_busy)\n         almost_empty_i  <= #`TCQ 1'b1;\n       else\n         almost_empty_i  <= #`TCQ ram_aempty_comb;\n      end\n  // end endgenerate // gae_ss\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL\n   //-----------------------------------------------------------------------------\n\n   localparam  C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT \n                                  C_PROG_FULL_THRESH_ASSERT_VAL; // STD\n   localparam  C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT\n                                  C_PROG_FULL_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;   \n   generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin \n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n          prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr>= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  ((diff_pntr) < C_PF_ASSERT_VAL )\n        prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate // single_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr >= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n       else if  (diff_pntr < C_PF_NEGATE_VAL)\n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate //multiple_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT\n                                               PROG_FULL_THRESH; // STD\n   generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input\n\n     always @(posedge CLK or posedge RST_FULL_FF) begin//0\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin //1\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin//2 \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin//3\n           if (diff_pntr > pf3_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if (diff_pntr == pf3_assert_val) begin//4\n             if (read_only_q)\n               prog_full_i <= #`TCQ 1'b0;\n             else\n               prog_full_i <= #`TCQ 1'b1;\n           end else//4\n             prog_full_i <= #`TCQ 1'b0;\n         end else//3\n           prog_full_i <= #`TCQ prog_full_i;\n       end //2\n       else begin//5\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin//6 \n        if (diff_pntr >= pf3_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  (diff_pntr < pf3_assert_val) begin//7\n         prog_full_i <= #`TCQ 1'b0;\n       end//7\n       end//6\n      else\n           prog_full_i <= #`TCQ prog_full_i;\n       end//5\n     end//1\n     end//0\n   end endgenerate //single_pf_input\n  \n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_ASSERT; // STD\n   wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_NEGATE; // STD\n\n   generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin\n           if (diff_pntr >= pf_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if ((diff_pntr == pf_negate_val && read_only_q) ||\n                  diff_pntr < pf_negate_val)\n             prog_full_i <= #`TCQ 1'b0;\n           else\n             prog_full_i <= #`TCQ prog_full_i;\n         end else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin \n        if (diff_pntr >= pf_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n       else if (diff_pntr < pf_negate_val) \n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n\n     end\n   end\n   end endgenerate //multiple_pf_inputs\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY\n   //-----------------------------------------------------------------------------\n   localparam  C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD\n   localparam  C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i) \n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy) \n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL)\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > C_PE_ASSERT_VAL)\n         prog_empty_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n     end\n     end\n   end endgenerate // single_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > C_PE_NEGATE_VAL) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n\n     end\n\n     end\n   end endgenerate //multiple_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH -2) : // FWFT\n                                                PROG_EMPTY_THRESH; // STD\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe < pe3_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (diff_pntr_pe == pe3_assert_val) begin\n             if (write_only_q)\n               prog_empty_i <= #`TCQ 1'b0;\n             else\n               prog_empty_i <= #`TCQ 1'b1;\n           end else\n             prog_empty_i <= #`TCQ 1'b0;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe3_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > pe3_assert_val)\n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n\n     end\n   end endgenerate // single_pe_input\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_ASSERT; // STD\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_NEGATE; // STD\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n      else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe <= pe4_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || \n                     (diff_pntr_pe > pe4_negate_val)) begin\n             prog_empty_i <= #`TCQ 1'b0;\n           end else\n             prog_empty_i <= #`TCQ prog_empty_i;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe4_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > pe4_negate_val) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n     end\n   end endgenerate // multiple_pe_inputs\n\nendmodule // fifo_generator_v13_2_5_bhv_ver_ss\n\n\n\n/**************************************************************************\n * First-Word Fall-Through module (preload 0)\n **************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_preload0\n  #(\n    parameter  C_DOUT_RST_VAL            = \"\",\n    parameter  C_DOUT_WIDTH              = 8,\n    parameter  C_HAS_RST                 = 0,\n    parameter  C_ENABLE_RST_SYNC         = 0,\n    parameter  C_HAS_SRST                = 0,\n    parameter  C_USE_EMBEDDED_REG        = 0,\n    parameter  C_EN_SAFETY_CKT           = 0, \n    parameter  C_USE_DOUT_RST            = 0,\n    parameter  C_USE_ECC                 = 0,\n    parameter  C_USERVALID_LOW           = 0,\n    parameter  C_USERUNDERFLOW_LOW       = 0,\n    parameter  C_MEMORY_TYPE             = 0,\n    parameter  C_FIFO_TYPE               = 0\n  )\n  (\n    //Inputs\n    input                          SAFETY_CKT_RD_RST,\n    input                          RD_CLK,\n    input                          RD_RST,\n    input                          SRST,\n    input                          WR_RST_BUSY,\n    input                          RD_RST_BUSY,\n    input                          RD_EN,\n    input                          FIFOEMPTY,\n    input       [C_DOUT_WIDTH-1:0] FIFODATA,\n    input                          FIFOSBITERR,\n    input                          FIFODBITERR,\n   \n    //Outputs\n    output reg  [C_DOUT_WIDTH-1:0] USERDATA,\n    output                         USERVALID,\n    output                         USERUNDERFLOW,\n    output                         USEREMPTY,\n    output                         USERALMOSTEMPTY,\n    output                         RAMVALID,\n    output                         FIFORDEN,\n    output reg                     USERSBITERR,\n    output reg                     USERDBITERR,\n    output reg                     STAGE2_REG_EN,\n    output                         fab_read_data_valid_i_o,\n    output                         read_data_valid_i_o,\n    output                         ram_valid_i_o,\n    output      [1:0]              VALID_STAGES \n  );\n //Internal signals\n wire                      preloadstage1;\n wire                      preloadstage2;\n reg                       ram_valid_i;\n reg                       fab_valid;\n reg                       read_data_valid_i;\n reg                       fab_read_data_valid_i;\n reg                       fab_read_data_valid_i_1;\n reg                       ram_valid_i_d;\n reg                       read_data_valid_i_d;\n reg                       fab_read_data_valid_i_d;\n wire                      ram_regout_en;\n reg                       ram_regout_en_d1;\n reg                       ram_regout_en_d2;\n wire                      fab_regout_en;\n wire                      ram_rd_en;\n reg                       empty_i        = 1'b1;\n reg                       empty_sckt     = 1'b1;\n reg                       sckt_rrst_q    = 1'b0;\n reg                       sckt_rrst_done = 1'b0;\n reg                       empty_q        = 1'b1;\n reg                       rd_en_q        = 1'b0;\n reg                       almost_empty_i = 1'b1;\n reg                       almost_empty_q = 1'b1;\n wire                      rd_rst_i;\n wire                      srst_i;\n reg  [C_DOUT_WIDTH-1:0]   userdata_both;\n wire                      uservalid_both;\n wire                      uservalid_one;\n reg                       user_sbiterr_both = 1'b0;\n reg                       user_dbiterr_both = 1'b0;\n  \nassign ram_valid_i_o = ram_valid_i;\nassign read_data_valid_i_o = read_data_valid_i;\nassign fab_read_data_valid_i_o = fab_read_data_valid_i; \n\n\n\n/*************************************************************************\n* FUNCTIONS\n*************************************************************************/\n\n   /*************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***********************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n   \n   //*************************************************************************\n   //  Set power-on states for regs\n   //*************************************************************************\n   initial begin\n      ram_valid_i       = 1'b0;\n      fab_valid         = 1'b0;\n      read_data_valid_i = 1'b0;\n      fab_read_data_valid_i = 1'b0;\n      fab_read_data_valid_i_1 = 1'b0;\n      USERDATA          = hexstr_conv(C_DOUT_RST_VAL);\n      userdata_both          = hexstr_conv(C_DOUT_RST_VAL);\n      USERSBITERR       = 1'b0;\n      USERDBITERR       = 1'b0;\n      user_sbiterr_both = 1'b0;\n      user_dbiterr_both = 1'b0;\n   end //initial\n\n   //***************************************************************************\n   //  connect up optional reset\n   //***************************************************************************\n   assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;\n   assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;\n\n   reg  sckt_rd_rst_fwft = 1'b0;\n   reg  fwft_rst_done_i  = 1'b0;\n   wire fwft_rst_done;\n   assign fwft_rst_done = 1'b1;//C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;\n   always @ (posedge RD_CLK) begin\n     sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;\n   end\n\n   always @ (posedge rd_rst_i or posedge RD_CLK) begin\n     if (rd_rst_i)\n       fwft_rst_done_i  <= 1'b0;\n     else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)\n       fwft_rst_done_i  <= #`TCQ 1'b1;\n   end\n\n   localparam INVALID             = 0;\n   localparam STAGE1_VALID        = 2;\n   localparam STAGE2_VALID        = 1;\n   localparam BOTH_STAGES_VALID   = 3;\n\n   reg  [1:0] curr_fwft_state = INVALID;\n   reg  [1:0] next_fwft_state = INVALID;\n\n\ngenerate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin\n         always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n \n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n     \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n    \n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = preloadstage2;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;\n   end\nendgenerate // gnll_fifo\n\n   reg curr_state         = 0;\n   reg next_state         = 0;\n   reg leaving_empty_fwft = 0;\n   reg going_empty_fwft   = 0;\n   reg empty_i_q          = 0;\n   reg ram_rd_en_fwft     = 0;\n   generate if (C_FIFO_TYPE == 2) begin : gll_fifo\n     always @* begin // FSM fo FWFT\n       case (curr_state)\n         1'b0: begin\n           if (~FIFOEMPTY)\n             next_state <= 1'b1;\n           else\n             next_state <= 1'b0;\n           end\n         1'b1: begin\n           if (FIFOEMPTY && RD_EN)\n             next_state <= 1'b0;\n           else\n             next_state <= 1'b1;\n           end\n         default: next_state <= 1'b0;\n       endcase\n     end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_i       <= 1'b1;\n           empty_i_q     <= 1'b1;\n           ram_valid_i   <= 1'b0;\n        end else if (srst_i) begin\n           empty_i       <= #`TCQ 1'b1;\n           empty_i_q     <= #`TCQ 1'b1;\n           ram_valid_i   <= #`TCQ 1'b0;\n        end else begin\n           empty_i       <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);\n           empty_i_q     <= #`TCQ FIFOEMPTY;\n           ram_valid_i   <= #`TCQ next_state;\n        end\n     end //always\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n           curr_state    <= 1'b0;\n        end else if (srst_i) begin\n           curr_state    <= #`TCQ 1'b0;\n        end else begin\n           curr_state    <= #`TCQ next_state;\n        end\n     end //always\n\n     wire                  fe_of_empty; \n     assign fe_of_empty   = empty_i_q & ~FIFOEMPTY;\n\n     always @* begin // Finding leaving empty\n       case (curr_state)\n         1'b0:    leaving_empty_fwft <= fe_of_empty;\n         1'b1:    leaving_empty_fwft <= 1'b1;\n         default: leaving_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Finding going empty\n       case (curr_state)\n         1'b1:    going_empty_fwft <= FIFOEMPTY & RD_EN;\n         default: going_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Generating FWFT rd_en\n       case (curr_state)\n         1'b0:    ram_rd_en_fwft <= ~FIFOEMPTY;\n         1'b1:    ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;\n         default: ram_rd_en_fwft <= 1'b0;\n       endcase\n     end\n\n     assign ram_regout_en = ram_rd_en_fwft;\n     //assign ram_regout_en_d1 = ram_rd_en_fwft;\n     //assign ram_regout_en_d2 = ram_rd_en_fwft;\n     assign ram_rd_en     = ram_rd_en_fwft;\n   end endgenerate // gll_fifo\n\n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false.\n   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n   generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           ram_valid_i     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              ram_valid_i     <= #`TCQ 1'b0;\n           end else begin\n              if (ram_rd_en == 1'b1) begin\n                 ram_valid_i   <= #`TCQ 1'b1;\n              end else begin\n                 if (ram_regout_en == 1'b1)\n                   ram_valid_i <= #`TCQ 1'b0;\n                 else\n                   ram_valid_i <= #`TCQ ram_valid_i;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_ram_valid\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n  \n generate if(C_USE_EMBEDDED_REG < 3) begin\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else\n        read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);\n   end //always\nend \nendgenerate\n\n   \n   \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n generate if ( C_USE_EMBEDDED_REG < 3) begin\n  always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin         // asynchronous reset (active high)\n             almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ FIFOEMPTY;\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n   \n   \n     \n  // BRAM resets synchronously\n generate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin\n   always @ ( posedge rd_rst_i)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n           @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n             USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end  else if (fwft_rst_done) begin\n            if (ram_regout_en) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end\n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n//safety ckt with one register\ngenerate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n            @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n        end\n     end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n          //@(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end \n       end\n        else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n            //  @(posedge RD_CLK)\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end else if (fwft_rst_done) begin\n            if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end          \n          end\n        end\n       end //always\n  end //if\nendgenerate\n\n\ngenerate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin\n         \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d1 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d1 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d1 <= #`TCQ ram_regout_en;\n                 end\n            end //always\n   //  assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));\n       assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d2 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d2 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;\n                 end\n            end //always\n\n    \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n     always @ (posedge RD_CLK) begin\n        ram_valid_i_d <= #`TCQ ram_valid_i;\n        read_data_valid_i_d <= #`TCQ read_data_valid_i;\n        fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;\n\n     end\n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n    \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;\n   end\n   endgenerate // gnll_fifo\n\n   \n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n     generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid\n\n     \n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           fab_valid     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              fab_valid    <= #`TCQ 1'b0;\n           end else begin\n              if (ram_regout_en == 1'b1) begin\n                 fab_valid  <= #`TCQ 1'b1;\n              end else begin\n                 if (fab_regout_en == 1'b1)\n                   fab_valid <= #`TCQ 1'b0;\n                 else\n                   fab_valid <= #`TCQ fab_valid;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_fab_valid\n\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n    generate if(C_USE_EMBEDDED_REG == 3) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else begin\n        if (ram_regout_en == 1'b1) begin\n          read_data_valid_i <= #`TCQ 1'b1;\n        end else begin\n         if (fab_regout_en == 1'b1)\n          read_data_valid_i <= #`TCQ 1'b0;\n        else\n          read_data_valid_i <= #`TCQ read_data_valid_i;\n        end \n      end \n   end //always\nend\nendgenerate\n\n//generate if(C_USE_EMBEDDED_REG == 3) begin\n//   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n//      if (rd_rst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//      else if (srst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//\n//      if (ram_regout_en == 1'b1) begin\n//        fab_read_data_valid_i <= #`TCQ 1'b0;\n//      end else begin\n//       if (fab_regout_en == 1'b1)\n//        fab_read_data_valid_i <= #`TCQ 1'b1;\n//      else\n//        fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;\n//      end \n//   end //always\n//end\n//endgenerate\n\n     generate if(C_USE_EMBEDDED_REG == 3 ) begin \n    always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid\n      if (rd_rst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else \n        fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);\n   end //always\nend\nendgenerate\n \nalways @ (posedge RD_CLK ) begin : proc_del1\n             begin\n                 fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;\n              end\n            end //always\n \n \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty_both\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n   reg FIFOEMPTY_1;\n   generate if (C_USE_EMBEDDED_REG == 3 ) begin\n    always @(posedge RD_CLK) begin\n            FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;\n           end\n    end\nendgenerate\n    generate if (C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n   begin\n      if (rd_rst_i) begin         // asynchronous reset (active high)\n           almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ (~ram_valid_i);\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_sckt <= #`TCQ 1'b1;\n           sckt_rrst_q <= #`TCQ 1'b0;\n           sckt_rrst_done <= #`TCQ 1'b0;\n        end else begin\n           sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;\n           if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin\n              sckt_rrst_done <= #`TCQ 1'b1;\n           end else if (sckt_rrst_done) begin\n              // rising clock edge\n              empty_sckt <= #`TCQ 1'b0;\n           end\n        end\n     end //always\n   \n   \n//   assign USEREMPTY       = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;\n   assign USEREMPTY       = empty_i;\n   assign USERALMOSTEMPTY = almost_empty_i;\n   assign FIFORDEN        = ram_rd_en;\n   assign RAMVALID        = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;\n   assign uservalid_both       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3)  ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);\n   assign uservalid_one       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3)  ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);\n   assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;\n   assign USERUNDERFLOW   = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;\n//no safety ckt with both reg\ngenerate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n            USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              userdata_both   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end else begin\n            if (fwft_rst_done) begin\n              if (ram_regout_en) begin\n                 userdata_both     <= #`TCQ FIFODATA; \n                 user_dbiterr_both <= #`TCQ FIFODBITERR;\n                 user_sbiterr_both <= #`TCQ FIFOSBITERR; \n              end\n              if (fab_regout_en) begin\n                 USERDATA     <= #`TCQ userdata_both;\n                 USERDBITERR  <= #`TCQ user_dbiterr_both;\n                 USERSBITERR  <= #`TCQ user_sbiterr_both; \n              end             \n            end             \n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n\n//safety_ckt with both registers\n generate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always @ (posedge RD_CLK) begin\n          if (rd_rst_i || srst_i) begin\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n              @(posedge RD_CLK)\n              USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n               userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end\n        end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n     if (rd_rst_i) begin //asynchronous reset (active high)\n       if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n         USERSBITERR       <= #`TCQ 0;\n         USERDBITERR       <= #`TCQ 0;\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end\n       // DRAM resets asynchronously\n       if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n         USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end \n     end else begin // rising clock edge\n       if (srst_i) begin\n         if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n           USERSBITERR       <= #`TCQ 0;\n           USERDBITERR       <= #`TCQ 0;\n           user_sbiterr_both <= #`TCQ 0;\n           user_dbiterr_both <= #`TCQ 0;\n         end\n         if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n           USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end\n       end else if (fwft_rst_done) begin\n         if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            userdata_both     <= #`TCQ FIFODATA;\n            user_dbiterr_both <= #`TCQ FIFODBITERR;\n            user_sbiterr_both <= #`TCQ FIFOSBITERR; \n         end\n         if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            USERDATA          <= #`TCQ userdata_both;\n            USERDBITERR       <= #`TCQ user_dbiterr_both;\n            USERSBITERR       <= #`TCQ user_sbiterr_both;\n         end\n       end\n     end\n   end //always\n  end //if\nendgenerate\n\nendmodule //fifo_generator_v13_2_5_bhv_ver_preload0\n\n\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Register one AXI channel on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   reg_slice\n//\n//--------------------------------------------------------------------------\n\nmodule fifo_generator_v13_2_5_axic_reg_slice #\n  (\n   parameter C_FAMILY     = \"virtex7\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   )\n  (\n   // System Signals\n   input  wire                      ACLK,\n   input  wire                      ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0]   S_PAYLOAD_DATA,\n   input  wire                      S_VALID,\n   output wire                      S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0]   M_PAYLOAD_DATA,\n   output wire                      M_VALID,\n   input  wire                      M_READY\n   );\n\n  localparam RST_SYNC_STAGES = 5;\n  localparam RST_BUSY_LEN    = 6;\n  reg [1:0] arst_sync_wr  = 2'b11;\n  reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n  wire sync_reset;\n  wire extnd_reset;\n\n\n  always @(posedge ARESET or posedge ACLK) begin\n    if (ARESET)\n      arst_sync_wr <= 2'b11;\n    else\n      arst_sync_wr <= #`TCQ {arst_sync_wr[0], 1'b0};\n  end\n\n  always @(posedge ACLK) begin\n    sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[1]};\n  end\n\n  assign sync_reset     = |sckt_wr_rst_cc[RST_BUSY_LEN-5:0] | arst_sync_wr[1]; \n  assign extnd_reset    = |sckt_wr_rst_cc | arst_sync_wr[1];\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000)\n    begin\n      reg [1:0] state;\n      localparam [1:0] \n        ZERO = 2'b10,\n        ONE  = 2'b11,\n        TWO  = 2'b01;\n      \n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg [C_DATA_WIDTH-1:0] storage_data2 = 0;\n      reg                    load_s1;\n      wire                   load_s2;\n      wire                   load_s1_from_s2;\n      reg                    s_ready_i; //local signal of output\n      wire                   m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with either slave side data or from storage2\n      always @(posedge ACLK) \n      begin\n        if (load_s1)\n          if (load_s1_from_s2)\n            storage_data1 <= storage_data2;\n          else\n            storage_data1 <= S_PAYLOAD_DATA;        \n      end\n\n      // Load storage2 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data1;\n\n      // Always load s2 on a valid transaction even if it's unnecessary\n      assign load_s2 = S_VALID & s_ready_i;\n\n      // Loading s1\n      always @ *\n      begin\n        if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction\n             // Load when ONE if we both have read and write at the same time\n             ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||\n             // Load when TWO and we have a transaction on Master side\n             ((state == TWO) && (M_READY == 1)))\n          load_s1 = 1'b1;\n        else\n          load_s1 = 1'b0;\n      end // always @ *\n\n      assign load_s1_from_s2 = (state == TWO);\n                       \n      // State Machine for handling output signals\n      always @(posedge ACLK) begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          state <= ZERO;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          case (state)\n            // No transaction stored locally\n            ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE\n\n            // One transaction stored locally\n            ONE: begin\n              if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO\n              if (~M_READY & S_VALID) begin\n                state <= TWO;  // Got another one so move to TWO\n                s_ready_i <= 1'b0;\n              end\n            end\n\n            // TWO transaction stored locally\n            TWO: if (M_READY) begin\n              state <= ONE; // Read out one so move to ONE\n              s_ready_i <= 1'b1;\n            end\n          endcase // case (state)\n        end\n      end // always @ (posedge ACLK)\n      \n      assign m_valid_i = state[0];\n\n    end // if (C_REG_CONFIG == 1)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000001)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg                    s_ready_i; //local signal of output\n      reg                    m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b0;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else if (m_valid_i & M_READY) begin\n          s_ready_i <= 1'b1;\n          m_valid_i <= 1'b0;\n        end else if (S_VALID & s_ready_i) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b1;\n        end\n        if (~m_valid_i) begin\n          storage_data1 <= S_PAYLOAD_DATA;        \n        end\n      end\n      assign M_PAYLOAD_DATA = storage_data1;\n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // reg_slice\n", "num_lines": 10520}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Generic single-channel AXI FIFO\n// Synchronous FIFO is implemented using either LUTs (SRL) or BRAM.\n// Transfers received on the AXI slave port are pushed onto the FIFO.\n// FIFO output, when available, is presented on the AXI master port and\n//   popped when the master port responds (M_READY).\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n// Structure:\n//   axic_fifo\n//     fifo_gen\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_21_axic_fifo #\n  (\n   parameter         C_FAMILY          = \"virtex6\",\n   parameter integer C_FIFO_DEPTH_LOG  = 5,      // FIFO depth = 2**C_FIFO_DEPTH_LOG\n                                                 // Range = [5:9] when TYPE=\"lut\",\n                                                 // Range = [5:12] when TYPE=\"bram\",\n   parameter integer C_FIFO_WIDTH      = 64,     // Width of payload [1:512]\n   parameter         C_FIFO_TYPE       = \"lut\"   // \"lut\" = LUT (SRL) based,\n                                                 // \"bram\" = BRAM based\n   )\n  (\n   // Global inputs\n   input  wire                        ACLK,    // Clock\n   input  wire                        ARESET,  // Reset\n   // Slave  Port\n   input  wire [C_FIFO_WIDTH-1:0]     S_MESG,  // Payload (may be any set of channel signals)\n   input  wire                        S_VALID, // FIFO push\n   output wire                        S_READY, // FIFO not full\n   // Master  Port\n   output wire [C_FIFO_WIDTH-1:0]     M_MESG,  // Payload\n   output wire                        M_VALID, // FIFO not empty\n   input  wire                        M_READY  // FIFO pop\n   );\n\n   axi_data_fifo_v2_1_21_fifo_gen #(\n     .C_FAMILY(C_FAMILY),\n     .C_COMMON_CLOCK(1),\n     .C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),\n     .C_FIFO_WIDTH(C_FIFO_WIDTH),\n     .C_FIFO_TYPE(C_FIFO_TYPE))\n   inst (\n     .clk(ACLK),\n     .rst(ARESET),\n     .wr_clk(1'b0),\n     .wr_en(S_VALID),\n     .wr_ready(S_READY),\n     .wr_data(S_MESG),\n     .rd_clk(1'b0),\n     .rd_en(M_READY),\n     .rd_valid(M_VALID),\n     .rd_data(M_MESG));\n\nendmodule\n\n\n// -- (c) Copyright 1995 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------\n\n// The synthesis directives \"translate_off/translate_on\" specified below are\n// supported by Xilinx, Mentor Graphics and Synplicity synthesis\n// tools. Ensure they are correct for your synthesis tool(s).\n\n// You must compile the fifo_generator wrapper file when simulating\n// the core. When compiling the wrapper file, be sure to\n// reference the XilinxCoreLib Verilog simulation library. For detailed\n// instructions, please refer to the \"CORE Generator Help\".\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_21_fifo_gen #(\nparameter C_FAMILY          = \"virtex7\",\nparameter integer C_COMMON_CLOCK    = 1,\nparameter integer C_SYNCHRONIZER_STAGE = 3,\nparameter integer C_FIFO_DEPTH_LOG  = 5,\nparameter integer C_FIFO_WIDTH      = 64,\nparameter C_FIFO_TYPE       = \"lut\"\n)(\n  clk,\n  rst,\n  wr_clk,\n  wr_en,\n  wr_ready,\n  wr_data,\n  rd_clk,\n  rd_en,\n  rd_valid,\n  rd_data);\n\ninput clk;\ninput wr_clk;\ninput rd_clk;\ninput rst;\ninput [C_FIFO_WIDTH-1 : 0] wr_data;\ninput wr_en;\ninput rd_en;\noutput [C_FIFO_WIDTH-1 : 0] rd_data;\noutput wr_ready;\noutput rd_valid;\n\nwire  full;\nwire  empty;\nwire  rd_valid = ~empty;\nwire  wr_ready = ~full;\n\nlocalparam C_MEMORY_TYPE =  (C_FIFO_TYPE == \"bram\")? 1 : 2;\n\nlocalparam C_IMPLEMENTATION_TYPE = (C_COMMON_CLOCK == 1)? 0 : 2;\n\n  fifo_generator_v13_2_5 #(\n    .C_COMMON_CLOCK(C_COMMON_CLOCK),\n    .C_DIN_WIDTH(C_FIFO_WIDTH),\n    .C_DOUT_WIDTH(C_FIFO_WIDTH),\n    .C_FAMILY(C_FAMILY),\n    .C_IMPLEMENTATION_TYPE(C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE(C_MEMORY_TYPE),\n    .C_RD_DEPTH(1<<C_FIFO_DEPTH_LOG),\n    .C_RD_PNTR_WIDTH(C_FIFO_DEPTH_LOG),\n    .C_WR_DEPTH(1<<C_FIFO_DEPTH_LOG),\n    .C_WR_PNTR_WIDTH(C_FIFO_DEPTH_LOG),\n    .C_ADD_NGC_CONSTRAINT(0),\n    .C_APPLICATION_TYPE_AXIS(0),\n    .C_APPLICATION_TYPE_RACH(0),\n    .C_APPLICATION_TYPE_RDCH(0),\n    .C_APPLICATION_TYPE_WACH(0),\n    .C_APPLICATION_TYPE_WDCH(0),\n    .C_APPLICATION_TYPE_WRCH(0),\n    .C_AXIS_TDATA_WIDTH(64),\n    .C_AXIS_TDEST_WIDTH(4),\n    .C_AXIS_TID_WIDTH(8),\n    .C_AXIS_TKEEP_WIDTH(4),\n    .C_AXIS_TSTRB_WIDTH(4),\n    .C_AXIS_TUSER_WIDTH(4),\n    .C_AXIS_TYPE(0),\n    .C_AXI_ADDR_WIDTH(32),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_AXI_DATA_WIDTH(64),\n    .C_AXI_ID_WIDTH(4),\n    .C_AXI_LEN_WIDTH(8),\n    .C_AXI_LOCK_WIDTH(2),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_TYPE(0),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_COUNT_TYPE(0),\n    .C_DATA_COUNT_WIDTH(6),\n    .C_DEFAULT_VALUE(\"BlankString\"),\n    .C_DIN_WIDTH_AXIS(1),\n    .C_DIN_WIDTH_RACH(32),\n    .C_DIN_WIDTH_RDCH(64),\n    .C_DIN_WIDTH_WACH(32),\n    .C_DIN_WIDTH_WDCH(64),\n    .C_DIN_WIDTH_WRCH(2),\n    .C_DOUT_RST_VAL(\"0\"),\n    .C_ENABLE_RLOCS(0),\n    .C_ENABLE_RST_SYNC(1),\n    .C_ERROR_INJECTION_TYPE(0),\n    .C_ERROR_INJECTION_TYPE_AXIS(0),\n    .C_ERROR_INJECTION_TYPE_RACH(0),\n    .C_ERROR_INJECTION_TYPE_RDCH(0),\n    .C_ERROR_INJECTION_TYPE_WACH(0),\n    .C_ERROR_INJECTION_TYPE_WDCH(0),\n    .C_ERROR_INJECTION_TYPE_WRCH(0),\n    .C_FULL_FLAGS_RST_VAL(0),\n    .C_HAS_ALMOST_EMPTY(0),\n    .C_HAS_ALMOST_FULL(0),\n    .C_HAS_AXIS_TDATA(0),\n    .C_HAS_AXIS_TDEST(0),\n    .C_HAS_AXIS_TID(0),\n    .C_HAS_AXIS_TKEEP(0),\n    .C_HAS_AXIS_TLAST(0),\n    .C_HAS_AXIS_TREADY(1),\n    .C_HAS_AXIS_TSTRB(0),\n    .C_HAS_AXIS_TUSER(0),\n    .C_HAS_AXI_ARUSER(0),\n    .C_HAS_AXI_AWUSER(0),\n    .C_HAS_AXI_BUSER(0),\n    .C_HAS_AXI_RD_CHANNEL(0),\n    .C_HAS_AXI_RUSER(0),\n    .C_HAS_AXI_WR_CHANNEL(0),\n    .C_HAS_AXI_WUSER(0),\n    .C_HAS_BACKUP(0),\n    .C_HAS_DATA_COUNT(0),\n    .C_HAS_DATA_COUNTS_AXIS(0),\n    .C_HAS_DATA_COUNTS_RACH(0),\n    .C_HAS_DATA_COUNTS_RDCH(0),\n    .C_HAS_DATA_COUNTS_WACH(0),\n    .C_HAS_DATA_COUNTS_WDCH(0),\n    .C_HAS_DATA_COUNTS_WRCH(0),\n    .C_HAS_INT_CLK(0),\n    .C_HAS_MASTER_CE(0),\n    .C_HAS_MEMINIT_FILE(0),\n    .C_HAS_OVERFLOW(0),\n    .C_HAS_PROG_FLAGS_AXIS(0),\n    .C_HAS_PROG_FLAGS_RACH(0),\n    .C_HAS_PROG_FLAGS_RDCH(0),\n    .C_HAS_PROG_FLAGS_WACH(0),\n    .C_HAS_PROG_FLAGS_WDCH(0),\n    .C_HAS_PROG_FLAGS_WRCH(0),\n    .C_HAS_RD_DATA_COUNT(0),\n    .C_HAS_RD_RST(0),\n    .C_HAS_RST(1),\n    .C_HAS_SLAVE_CE(0),\n    .C_HAS_SRST(0),\n    .C_HAS_UNDERFLOW(0),\n    .C_HAS_VALID(0),\n    .C_HAS_WR_ACK(0),\n    .C_HAS_WR_DATA_COUNT(0),\n    .C_HAS_WR_RST(0),\n    .C_IMPLEMENTATION_TYPE_AXIS(1),\n    .C_IMPLEMENTATION_TYPE_RACH(1),\n    .C_IMPLEMENTATION_TYPE_RDCH(1),\n    .C_IMPLEMENTATION_TYPE_WACH(1),\n    .C_IMPLEMENTATION_TYPE_WDCH(1),\n    .C_IMPLEMENTATION_TYPE_WRCH(1),\n    .C_INIT_WR_PNTR_VAL(0),\n    .C_INTERFACE_TYPE(0),\n    .C_MIF_FILE_NAME(\"BlankString\"),\n    .C_MSGON_VAL(1),\n    .C_OPTIMIZATION_MODE(0),\n    .C_OVERFLOW_LOW(0),\n    .C_PRELOAD_LATENCY(0),\n    .C_PRELOAD_REGS(1),\n    .C_PRIM_FIFO_TYPE(\"512x36\"),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),\n    .C_PROG_EMPTY_TYPE(0),\n    .C_PROG_EMPTY_TYPE_AXIS(0),\n    .C_PROG_EMPTY_TYPE_RACH(0),\n    .C_PROG_EMPTY_TYPE_RDCH(0),\n    .C_PROG_EMPTY_TYPE_WACH(0),\n    .C_PROG_EMPTY_TYPE_WDCH(0),\n    .C_PROG_EMPTY_TYPE_WRCH(0),\n    .C_PROG_FULL_THRESH_ASSERT_VAL(31),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),\n    .C_PROG_FULL_THRESH_NEGATE_VAL(30),\n    .C_PROG_FULL_TYPE(0),\n    .C_PROG_FULL_TYPE_AXIS(0),\n    .C_PROG_FULL_TYPE_RACH(0),\n    .C_PROG_FULL_TYPE_RDCH(0),\n    .C_PROG_FULL_TYPE_WACH(0),\n    .C_PROG_FULL_TYPE_WDCH(0),\n    .C_PROG_FULL_TYPE_WRCH(0),\n    .C_RACH_TYPE(0),\n    .C_RDCH_TYPE(0),\n    .C_RD_DATA_COUNT_WIDTH(6),\n    .C_RD_FREQ(1),\n    .C_REG_SLICE_MODE_AXIS(0),\n    .C_REG_SLICE_MODE_RACH(0),\n    .C_REG_SLICE_MODE_RDCH(0),\n    .C_REG_SLICE_MODE_WACH(0),\n    .C_REG_SLICE_MODE_WDCH(0),\n    .C_REG_SLICE_MODE_WRCH(0),\n    .C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),\n    .C_UNDERFLOW_LOW(0),\n    .C_USE_COMMON_OVERFLOW(0),\n    .C_USE_COMMON_UNDERFLOW(0),\n    .C_USE_DEFAULT_SETTINGS(0),\n    .C_USE_DOUT_RST(0),\n    .C_USE_ECC(0),\n    .C_USE_ECC_AXIS(0),\n    .C_USE_ECC_RACH(0),\n    .C_USE_ECC_RDCH(0),\n    .C_USE_ECC_WACH(0),\n    .C_USE_ECC_WDCH(0),\n    .C_USE_ECC_WRCH(0),\n    .C_USE_EMBEDDED_REG(0),\n    .C_USE_FIFO16_FLAGS(0),\n    .C_USE_FWFT_DATA_COUNT(1),\n    .C_VALID_LOW(0),\n    .C_WACH_TYPE(0),\n    .C_WDCH_TYPE(0),\n    .C_WRCH_TYPE(0),\n    .C_WR_ACK_LOW(0),\n    .C_WR_DATA_COUNT_WIDTH(6),\n    .C_WR_DEPTH_AXIS(1024),\n    .C_WR_DEPTH_RACH(16),\n    .C_WR_DEPTH_RDCH(1024),\n    .C_WR_DEPTH_WACH(16),\n    .C_WR_DEPTH_WDCH(1024),\n    .C_WR_DEPTH_WRCH(16),\n    .C_WR_FREQ(1),\n    .C_WR_PNTR_WIDTH_AXIS(10),\n    .C_WR_PNTR_WIDTH_RACH(4),\n    .C_WR_PNTR_WIDTH_RDCH(10),\n    .C_WR_PNTR_WIDTH_WACH(4),\n    .C_WR_PNTR_WIDTH_WDCH(10),\n    .C_WR_PNTR_WIDTH_WRCH(4),\n    .C_WR_RESPONSE_LATENCY(1)\n    )\n  fifo_gen_inst (\n    .clk(clk),\n    .din(wr_data),\n    .dout(rd_data),\n    .empty(empty),\n    .full(full),\n    .rd_clk(rd_clk),\n    .rd_en(rd_en),\n    .rst(rst),\n    .wr_clk(wr_clk),\n    .wr_en(wr_en),\n    .almost_empty(),\n    .almost_full(),\n    .axi_ar_data_count(),\n    .axi_ar_dbiterr(),\n    .axi_ar_injectdbiterr(1'b0),\n    .axi_ar_injectsbiterr(1'b0),\n    .axi_ar_overflow(),\n    .axi_ar_prog_empty(),\n    .axi_ar_prog_empty_thresh(4'b0),\n    .axi_ar_prog_full(),\n    .axi_ar_prog_full_thresh(4'b0),\n    .axi_ar_rd_data_count(),\n    .axi_ar_sbiterr(),\n    .axi_ar_underflow(),\n    .axi_ar_wr_data_count(),\n    .axi_aw_data_count(),\n    .axi_aw_dbiterr(),\n    .axi_aw_injectdbiterr(1'b0),\n    .axi_aw_injectsbiterr(1'b0),\n    .axi_aw_overflow(),\n    .axi_aw_prog_empty(),\n    .axi_aw_prog_empty_thresh(4'b0),\n    .axi_aw_prog_full(),\n    .axi_aw_prog_full_thresh(4'b0),\n    .axi_aw_rd_data_count(),\n    .axi_aw_sbiterr(),\n    .axi_aw_underflow(),\n    .axi_aw_wr_data_count(),\n    .axi_b_data_count(),\n    .axi_b_dbiterr(),\n    .axi_b_injectdbiterr(1'b0),\n    .axi_b_injectsbiterr(1'b0),\n    .axi_b_overflow(),\n    .axi_b_prog_empty(),\n    .axi_b_prog_empty_thresh(4'b0),\n    .axi_b_prog_full(),\n    .axi_b_prog_full_thresh(4'b0),\n    .axi_b_rd_data_count(),\n    .axi_b_sbiterr(),\n    .axi_b_underflow(),\n    .axi_b_wr_data_count(),\n    .axi_r_data_count(),\n    .axi_r_dbiterr(),\n    .axi_r_injectdbiterr(1'b0),\n    .axi_r_injectsbiterr(1'b0),\n    .axi_r_overflow(),\n    .axi_r_prog_empty(),\n    .axi_r_prog_empty_thresh(10'b0),\n    .axi_r_prog_full(),\n    .axi_r_prog_full_thresh(10'b0),\n    .axi_r_rd_data_count(),\n    .axi_r_sbiterr(),\n    .axi_r_underflow(),\n    .axi_r_wr_data_count(),\n    .axi_w_data_count(),\n    .axi_w_dbiterr(),\n    .axi_w_injectdbiterr(1'b0),\n    .axi_w_injectsbiterr(1'b0),\n    .axi_w_overflow(),\n    .axi_w_prog_empty(),\n    .axi_w_prog_empty_thresh(10'b0),\n    .axi_w_prog_full(),\n    .axi_w_prog_full_thresh(10'b0),\n    .axi_w_rd_data_count(),\n    .axi_w_sbiterr(),\n    .axi_w_underflow(),\n    .axi_w_wr_data_count(),\n    .axis_data_count(),\n    .axis_dbiterr(),\n    .axis_injectdbiterr(1'b0),\n    .axis_injectsbiterr(1'b0),\n    .axis_overflow(),\n    .axis_prog_empty(),\n    .axis_prog_empty_thresh(10'b0),\n    .axis_prog_full(),\n    .axis_prog_full_thresh(10'b0),\n    .axis_rd_data_count(),\n    .axis_sbiterr(),\n    .axis_underflow(),\n    .axis_wr_data_count(),\n    .backup(1'b0),\n    .backup_marker(1'b0),\n    .data_count(),\n    .dbiterr(),\n    .injectdbiterr(1'b0),\n    .injectsbiterr(1'b0),\n    .int_clk(1'b0),\n    .m_aclk(1'b0),\n    .m_aclk_en(1'b0),\n    .m_axi_araddr(),\n    .m_axi_arburst(),\n    .m_axi_arcache(),\n    .m_axi_arid(),\n    .m_axi_arlen(),\n    .m_axi_arlock(),\n    .m_axi_arprot(),\n    .m_axi_arqos(),\n    .m_axi_arready(1'b0),\n    .m_axi_arregion(),\n    .m_axi_arsize(),\n    .m_axi_aruser(),\n    .m_axi_arvalid(),\n    .m_axi_awaddr(),\n    .m_axi_awburst(),\n    .m_axi_awcache(),\n    .m_axi_awid(),\n    .m_axi_awlen(),\n    .m_axi_awlock(),\n    .m_axi_awprot(),\n    .m_axi_awqos(),\n    .m_axi_awready(1'b0),\n    .m_axi_awregion(),\n    .m_axi_awsize(),\n    .m_axi_awuser(),\n    .m_axi_awvalid(),\n    .m_axi_bid(4'b0),\n    .m_axi_bready(),\n    .m_axi_bresp(2'b0),\n    .m_axi_buser(1'b0),\n    .m_axi_bvalid(1'b0),\n    .m_axi_rdata(64'b0),\n    .m_axi_rid(4'b0),\n    .m_axi_rlast(1'b0),\n    .m_axi_rready(),\n    .m_axi_rresp(2'b0),\n    .m_axi_ruser(1'b0),\n    .m_axi_rvalid(1'b0),\n    .m_axi_wdata(),\n    .m_axi_wid(),\n    .m_axi_wlast(),\n    .m_axi_wready(1'b0),\n    .m_axi_wstrb(),\n    .m_axi_wuser(),\n    .m_axi_wvalid(),\n    .m_axis_tdata(),\n    .m_axis_tdest(),\n    .m_axis_tid(),\n    .m_axis_tkeep(),\n    .m_axis_tlast(),\n    .m_axis_tready(1'b0),\n    .m_axis_tstrb(),\n    .m_axis_tuser(),\n    .m_axis_tvalid(),\n    .overflow(),\n    .prog_empty(),\n    .prog_empty_thresh(5'b0),\n    .prog_empty_thresh_assert(5'b0),\n    .prog_empty_thresh_negate(5'b0),\n    .prog_full(),\n    .prog_full_thresh(5'b0),\n    .prog_full_thresh_assert(5'b0),\n    .prog_full_thresh_negate(5'b0),\n    .rd_data_count(),\n    .rd_rst(1'b0),\n    .s_aclk(1'b0),\n    .s_aclk_en(1'b0),\n    .s_aresetn(1'b0),\n    .s_axi_araddr(32'b0),\n    .s_axi_arburst(2'b0),\n    .s_axi_arcache(4'b0),\n    .s_axi_arid(4'b0),\n    .s_axi_arlen(8'b0),\n    .s_axi_arlock(2'b0),\n    .s_axi_arprot(3'b0),\n    .s_axi_arqos(4'b0),\n    .s_axi_arready(),\n    .s_axi_arregion(4'b0),\n    .s_axi_arsize(3'b0),\n    .s_axi_aruser(1'b0),\n    .s_axi_arvalid(1'b0),\n    .s_axi_awaddr(32'b0),\n    .s_axi_awburst(2'b0),\n    .s_axi_awcache(4'b0),\n    .s_axi_awid(4'b0),\n    .s_axi_awlen(8'b0),\n    .s_axi_awlock(2'b0),\n    .s_axi_awprot(3'b0),\n    .s_axi_awqos(4'b0),\n    .s_axi_awready(),\n    .s_axi_awregion(4'b0),\n    .s_axi_awsize(3'b0),\n    .s_axi_awuser(1'b0),\n    .s_axi_awvalid(1'b0),\n    .s_axi_bid(),\n    .s_axi_bready(1'b0),\n    .s_axi_bresp(),\n    .s_axi_buser(),\n    .s_axi_bvalid(),\n    .s_axi_rdata(),\n    .s_axi_rid(),\n    .s_axi_rlast(),\n    .s_axi_rready(1'b0),\n    .s_axi_rresp(),\n    .s_axi_ruser(),\n    .s_axi_rvalid(),\n    .s_axi_wdata(64'b0),\n    .s_axi_wid(4'b0),\n    .s_axi_wlast(1'b0),\n    .s_axi_wready(),\n    .s_axi_wstrb(8'b0),\n    .s_axi_wuser(1'b0),\n    .s_axi_wvalid(1'b0),\n    .s_axis_tdata(64'b0),\n    .s_axis_tdest(4'b0),\n    .s_axis_tid(8'b0),\n    .s_axis_tkeep(4'b0),\n    .s_axis_tlast(1'b0),\n    .s_axis_tready(),\n    .s_axis_tstrb(4'b0),\n    .s_axis_tuser(4'b0),\n    .s_axis_tvalid(1'b0),\n    .sbiterr(),\n    .srst(1'b0),\n    .underflow(),\n    .valid(),\n    .wr_ack(),\n    .wr_data_count(),\n    .wr_rst(1'b0),\n    .wr_rst_busy(),\n    .rd_rst_busy(),\n    .sleep(1'b0)\n  );\n\nendmodule\n\n\n\n// -- (c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n// Structure:\n//   axic_srl_fifo\n//     ndeep_srl\n//       nto1_mux\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_21_axic_srl_fifo #\n  (\n   parameter         C_FAMILY   = \"none\", // FPGA Family\n   parameter integer C_FIFO_WIDTH  = 1, // Width of S_MESG/M_MESG.\n   parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits\n                                             // the control logic can be used\n                                             // on before the control logic\n                                             // needs to be replicated.\n   parameter integer C_FIFO_DEPTH_LOG =  2,  // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.  \n                                             // The minimum size fifo generated is 4-deep.\n   parameter         C_USE_FULL =  1         // Prevent overwrite by throttling S_READY.                                              \n   )\n  (\n   input  wire                        ACLK,    // Clock\n   input  wire                        ARESET,  // Reset\n   input  wire [C_FIFO_WIDTH-1:0]     S_MESG,  // Input data\n   input  wire                        S_VALID, // Input data valid\n   output wire                        S_READY, // Input data ready\n   output wire [C_FIFO_WIDTH-1:0]     M_MESG,  // Output data\n   output wire                        M_VALID, // Output data valid\n   input  wire                        M_READY  // Output data ready\n   );\n  \n  localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;\n  localparam P_EMPTY       = {P_FIFO_DEPTH_LOG{1'b1}};\n  localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};\n  localparam P_ALMOSTFULL_TEMP  = {P_EMPTY, 1'b0};\n  localparam P_ALMOSTFULL  = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];\n  localparam P_NUM_REPS    = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?\n                             (C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :\n                             ((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;\n\n  (* syn_keep = \"1\" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0]  fifoaddr;\n  (* syn_keep = \"1\" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;\n\n  genvar i;\n  genvar j;\n\n  reg  M_VALID_i;\n  reg  S_READY_i;\n  wire push;     // FIFO push\n  wire pop;      // FIFO pop\n  reg  areset_d1; // Reset delay register\n  wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data\n\n  assign M_VALID = M_VALID_i;\n  assign S_READY = C_USE_FULL ? S_READY_i : 1'b1;\n  assign M_MESG = m_axi_mesg_i;\n  assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1'b1);\n  assign pop  = M_VALID_i & M_READY;\n  \n  always @(posedge ACLK) begin\n    areset_d1 <= ARESET;\n  end\n      \n  generate\n    //---------------------------------------------------------------------------\n    // Create count of number of elements in FIFOs\n    //---------------------------------------------------------------------------\n    for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep\n      assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] = \n         push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :\n                fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;\n      always @(posedge ACLK) begin\n        if (ARESET)\n          fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= \n                {P_FIFO_DEPTH_LOG{1'b1}};\n        else if (push ^ pop)\n          fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= \n                fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];\n      end\n    end\n\n    //---------------------------------------------------------------------------\n    // When FIFO is empty, reset master valid bit.  When not empty set valid bit.\n    // When FIFO is full,  reset slave  ready bit.  When not full  set ready bit.\n    //---------------------------------------------------------------------------\n    \n    always @(posedge ACLK) begin\n      if (ARESET) begin\n        M_VALID_i <= 1'b0;\n      end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == \n                               P_ALMOSTEMPTY) && pop && ~push) begin\n        M_VALID_i <= 1'b0;\n      end else if (push) begin\n        M_VALID_i <= 1'b1;\n      end\n    end\n      \n    always @(posedge ACLK) begin\n      if (ARESET) begin\n        S_READY_i <= 1'b0;\n      end else if (areset_d1) begin\n        S_READY_i <= 1'b1;\n      end else if (C_USE_FULL && \n        ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == \n         P_ALMOSTFULL) && push && ~pop)) begin\n        S_READY_i <= 1'b0;\n      end else if (C_USE_FULL && pop) begin\n        S_READY_i <= 1'b1;\n      end\n    end\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls\n      for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep\n        axi_data_fifo_v2_1_21_ndeep_srl #\n          (\n           .C_FAMILY  (C_FAMILY),\n           .C_A_WIDTH (P_FIFO_DEPTH_LOG)\n          )\n          srl_nx1\n          (\n           .CLK (ACLK),\n           .A   (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:\n                          P_FIFO_DEPTH_LOG*(i)]),\n           .CE  (push),\n           .D   (S_MESG[i*C_MAX_CTRL_FANOUT+j]),\n           .Q   (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j])\n          );\n      end\n    end      \n  endgenerate\n  \nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.\n//   Interface outputs are synchronized using ordinary flops for improved timing.\n//--------------------------------------------------------------------------\n// Structure:\n//   axic_reg_srl_fifo\n//     ndeep_srl\n//       nto1_mux\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_21_axic_reg_srl_fifo #\n  (\n   parameter         C_FAMILY   = \"none\", // FPGA Family\n   parameter integer C_FIFO_WIDTH  = 1, // Width of S_MESG/M_MESG.\n   parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits\n                                             // the control logic can be used\n                                             // on before the control logic\n                                             // needs to be replicated.\n   parameter integer C_FIFO_DEPTH_LOG =  2,  // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.  \n                                             // The minimum size fifo generated is 4-deep.\n   parameter         C_USE_FULL =  1         // Prevent overwrite by throttling S_READY.                                              \n   )\n  (\n   input  wire                        ACLK,    // Clock\n   input  wire                        ARESET,  // Reset\n   input  wire [C_FIFO_WIDTH-1:0]     S_MESG,  // Input data\n   input  wire                        S_VALID, // Input data valid\n   output wire                        S_READY, // Input data ready\n   output wire [C_FIFO_WIDTH-1:0]     M_MESG,  // Output data\n   output wire                        M_VALID, // Output data valid\n   input  wire                        M_READY  // Output data ready\n   );\n  \n  localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;\n  localparam P_EMPTY       = {P_FIFO_DEPTH_LOG{1'b1}};\n  localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};\n  localparam P_ALMOSTFULL_TEMP  = {P_EMPTY, 1'b0};\n  localparam P_ALMOSTFULL  = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];\n  localparam P_NUM_REPS    = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?\n                             (C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :\n                             ((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;\n\n  (* syn_keep = \"1\" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0]  fifoaddr;\n  (* syn_keep = \"1\" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;\n\n  genvar i;\n  genvar j;\n\n  \n  reg  m_valid_i = 1'b0;\n  reg  s_ready_i;\n  wire push;     // FIFO push\n  wire pop;      // FIFO pop\n  reg  areset_d1; // Reset delay register\n  reg  [C_FIFO_WIDTH-1:0] storage_data1;\n  wire [C_FIFO_WIDTH-1:0] storage_data2; // Intermediate SRL data\n  reg                    load_s1;\n  wire                   load_s1_from_s2;\n\n  reg [1:0] state;\n  localparam [1:0] \n    ZERO = 2'b10,\n    ONE  = 2'b11,\n    TWO  = 2'b01;\n      \n  assign M_VALID = m_valid_i;\n  assign S_READY = C_USE_FULL ? s_ready_i : 1'b1;\n  assign push = (S_VALID & (C_USE_FULL ? s_ready_i : 1'b1) & (state == TWO)) | (~M_READY & S_VALID & (state == ONE));\n  assign pop  = M_READY & (state == TWO);\n  assign M_MESG = storage_data1;\n  \n  always @(posedge ACLK) begin\n    areset_d1 <= ARESET;\n  end\n      \n  // Load storage1 with either slave side data or from storage2\n  always @(posedge ACLK) \n  begin\n    if (load_s1)\n      if (load_s1_from_s2)\n        storage_data1 <= storage_data2;\n      else\n        storage_data1 <= S_MESG;        \n  end\n\n  // Loading s1\n  always @ *\n  begin\n    if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction\n         // Load when ONE if we both have read and write at the same time\n         ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||\n         // Load when TWO and we have a transaction on Master side\n         ((state == TWO) && (M_READY == 1)))\n      load_s1 = 1'b1;\n    else\n      load_s1 = 1'b0;\n  end // always @ *\n\n  assign load_s1_from_s2 = (state == TWO);\n                   \n  // State Machine for handling output signals\n  always @(posedge ACLK) \n  begin\n    if (areset_d1) begin\n      state <= ZERO;\n      m_valid_i <= 1'b0;\n    end else begin\n      case (state)\n        // No transaction stored locally\n        ZERO: begin\n          if (S_VALID) begin\n            state <= ONE; // Got one so move to ONE\n            m_valid_i <= 1'b1;\n          end\n        end\n\n        // One transaction stored locally\n        ONE: begin\n          if (M_READY & ~S_VALID) begin\n            state <= ZERO; // Read out one so move to ZERO\n            m_valid_i <= 1'b0;\n          end else if (~M_READY & S_VALID) begin\n            state <= TWO;  // Got another one so move to TWO\n            m_valid_i <= 1'b1;\n          end\n        end\n\n        // TWO transaction stored locally\n        TWO: begin\n          if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == \n                 P_ALMOSTEMPTY) && pop && ~push) begin\n            state <= ONE; // Read out one so move to ONE\n            m_valid_i <= 1'b1;\n          end\n        end\n      endcase // case (state)\n    end\n  end // always @ (posedge ACLK)\n      \n  generate\n    //---------------------------------------------------------------------------\n    // Create count of number of elements in FIFOs\n    //---------------------------------------------------------------------------\n    for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep\n      assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] = \n         push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :\n                fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;\n      always @(posedge ACLK) begin\n        if (ARESET)\n          fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= \n                {P_FIFO_DEPTH_LOG{1'b1}};\n        else if (push ^ pop)\n          fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= \n                fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (ARESET) begin\n        s_ready_i <= 1'b0;\n      end else if (areset_d1) begin\n        s_ready_i <= 1'b1;\n      end else if (C_USE_FULL && \n        ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == \n         P_ALMOSTFULL) && push && ~pop)) begin\n        s_ready_i <= 1'b0;\n      end else if (C_USE_FULL && pop) begin\n        s_ready_i <= 1'b1;\n      end\n    end\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls\n      for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep\n        axi_data_fifo_v2_1_21_ndeep_srl #\n          (\n           .C_FAMILY  (C_FAMILY),\n           .C_A_WIDTH (P_FIFO_DEPTH_LOG)\n          )\n          srl_nx1\n          (\n           .CLK (ACLK),\n           .A   (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:\n                          P_FIFO_DEPTH_LOG*(i)]),\n           .CE  (push),\n           .D   (S_MESG[i*C_MAX_CTRL_FANOUT+j]),\n           .Q   (storage_data2[i*C_MAX_CTRL_FANOUT+j])\n          );\n      end\n    end      \n  endgenerate\n  \nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: This is a generic n-deep SRL instantiation\n// Verilog-standard:  Verilog 2001\n// $Revision: \n// $Date: \n//\n//-----------------------------------------------------------------------------\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_21_ndeep_srl #\n  (\n   parameter         C_FAMILY  = \"rtl\", // FPGA Family\n   parameter         C_A_WIDTH = 1          // Address Width (>= 1)\n   )\n  (\n   input  wire                 CLK, // Clock\n   input  wire [C_A_WIDTH-1:0] A,   // Address\n   input  wire                 CE,  // Clock Enable\n   input  wire                 D,   // Input Data\n   output wire                 Q    // Output Data\n   );\n\n  localparam integer P_SRLASIZE = 5;\n  localparam integer P_SRLDEPTH = 32;\n  localparam integer P_NUMSRLS  = (C_A_WIDTH>P_SRLASIZE) ? (2**(C_A_WIDTH-P_SRLASIZE)) : 1;\n  localparam integer P_SHIFT_DEPTH  = 2**C_A_WIDTH;\n  \n  wire [P_NUMSRLS:0]   d_i;\n  wire [P_NUMSRLS-1:0] q_i;\n  wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i;\n  \n  genvar i;\n  \n  // Instantiate SRLs in carry chain format\n  assign d_i[0] = D;\n  assign a_i = A;\n  \n  generate\n\t\t\t\t\t\n    if (C_FAMILY == \"rtl\") begin : gen_rtl_shifter\n      if (C_A_WIDTH <= P_SRLASIZE) begin : gen_inferred_srl\n        reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n        always @(posedge CLK)\n          if (CE)\n            shift_reg <= {shift_reg[P_SRLDEPTH-2:0], D};\n        assign Q = shift_reg[a_i];\n      end else begin : gen_logic_shifter  // Very wasteful\n        reg [P_SHIFT_DEPTH-1:0] shift_reg = {P_SHIFT_DEPTH{1'b0}};\n        always @(posedge CLK)\n          if (CE)\n            shift_reg <= {shift_reg[P_SHIFT_DEPTH-2:0], D};\n        assign Q = shift_reg[a_i];\n      end\n    end else begin : gen_primitive_shifter\n      for (i=0;i<P_NUMSRLS;i=i+1) begin : gen_srls\n        SRLC32E\n          srl_inst\n            (\n             .CLK (CLK),\n             .A   (a_i[P_SRLASIZE-1:0]),\n             .CE  (CE),\n             .D   (d_i[i]),\n             .Q   (q_i[i]),\n             .Q31 (d_i[i+1])\n             );\n      end\n      \n      if (C_A_WIDTH>P_SRLASIZE) begin : gen_srl_mux\n        generic_baseblocks_v2_1_0_nto1_mux #\n        (\n          .C_RATIO         (2**(C_A_WIDTH-P_SRLASIZE)),\n          .C_SEL_WIDTH     (C_A_WIDTH-P_SRLASIZE),\n          .C_DATAOUT_WIDTH (1),\n          .C_ONEHOT        (0)\n        )\n        srl_q_mux_inst\n        (\n          .SEL_ONEHOT ({2**(C_A_WIDTH-P_SRLASIZE){1'b0}}),\n          .SEL        (a_i[C_A_WIDTH-1:P_SRLASIZE]),\n          .IN         (q_i),\n          .OUT        (Q)\n        );\n      end else begin : gen_no_srl_mux\n        assign Q = q_i[0];\n      end\n    end\n  endgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// AXI data fifo module:    \n//   5-channel memory-mapped AXI4 interfaces.\n//   SRL or BRAM based FIFO on AXI W and/or R channels.\n//   FIFO to accommodate various data flow rates through the AXI interconnect\n//\n// Verilog-standard:  Verilog 2001\n//-----------------------------------------------------------------------------\n//\n// Structure:\n//   axi_data_fifo\n//     fifo_generator\n//\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_21_axi_data_fifo #\n  (\n   parameter         C_FAMILY                    = \"virtex7\",\n   parameter integer C_AXI_PROTOCOL              = 0,\n   parameter integer C_AXI_ID_WIDTH              = 4,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   parameter integer C_AXI_WRITE_FIFO_DEPTH      = 0,      // Range: (0, 32, 512)\n   parameter         C_AXI_WRITE_FIFO_TYPE       = \"lut\",  // \"lut\" = LUT (SRL) based,\n                                                           // \"bram\" = BRAM based\n   parameter integer C_AXI_WRITE_FIFO_DELAY      = 0,      // 0 = No, 1 = Yes\n                       // Indicates whether AWVALID and WVALID assertion is delayed until:\n                       //   a. the corresponding WLAST is stored in the FIFO, or\n                       //   b. no WLAST is stored and the FIFO is full.\n                       // 0 means AW channel is pass-through and \n                       //   WVALID is asserted whenever FIFO is not empty.\n   parameter integer C_AXI_READ_FIFO_DEPTH       = 0,      // Range: (0, 32, 512)\n   parameter         C_AXI_READ_FIFO_TYPE        = \"lut\",  // \"lut\" = LUT (SRL) based,\n                                                           // \"bram\" = BRAM based\n   parameter integer C_AXI_READ_FIFO_DELAY       = 0)      // 0 = No, 1 = Yes\n                       // Indicates whether ARVALID assertion is delayed until the \n                       //   the remaining vacancy of the FIFO is at least the burst length\n                       //   as indicated by ARLEN.\n                       // 0 means AR channel is pass-through.\n   // System Signals\n  (input wire aclk,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     s_axi_bid,\n   output wire [2-1:0]                  s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0]  s_axi_buser,\n   output wire                          s_axi_bvalid,\n   input  wire                          s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   s_axi_rdata,\n   output wire [2-1:0]                  s_axi_rresp,\n   output wire                          s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0]  s_axi_ruser,\n   output wire                          s_axi_rvalid,\n   input  wire                          s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     m_axi_bid,\n   input  wire [2-1:0]                  m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0]  m_axi_buser,\n   input  wire                          m_axi_bvalid,\n   output wire                          m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   m_axi_rdata,\n   input  wire [2-1:0]                  m_axi_rresp,\n   input  wire                          m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0]  m_axi_ruser,\n   input  wire                          m_axi_rvalid,\n   output wire                          m_axi_rready);\n  \n  localparam integer P_WIDTH_RACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_ARUSER_WIDTH;\n  localparam integer P_WIDTH_WACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_AWUSER_WIDTH;\n  localparam integer P_WIDTH_RDCH = 1 + 2 + C_AXI_DATA_WIDTH + C_AXI_ID_WIDTH + C_AXI_RUSER_WIDTH;\n  localparam integer P_WIDTH_WDCH = 1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+((C_AXI_PROTOCOL==1)?C_AXI_ID_WIDTH:0)+C_AXI_WUSER_WIDTH;\n  localparam integer P_WIDTH_WRCH = 2 + C_AXI_ID_WIDTH + C_AXI_BUSER_WIDTH;\n  \n  localparam         P_PRIM_FIFO_TYPE = \"512x72\" ;\n  localparam integer P_AXI4 = 0;\n  localparam integer P_AXI3 = 1;\n  localparam integer P_AXILITE = 2;\n  localparam integer P_WRITE_FIFO_DEPTH_LOG = (C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1;\n  localparam integer P_READ_FIFO_DEPTH_LOG = (C_AXI_READ_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1;\n  \n  // Ceiling of log2(x)\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  generate\n    if (((C_AXI_WRITE_FIFO_DEPTH == 0) && (C_AXI_READ_FIFO_DEPTH == 0)) || (C_AXI_PROTOCOL == P_AXILITE)) begin : gen_bypass\n      assign m_axi_awid     = s_axi_awid;\n      assign m_axi_awaddr   = s_axi_awaddr;\n      assign m_axi_awlen    = s_axi_awlen;\n      assign m_axi_awsize   = s_axi_awsize;\n      assign m_axi_awburst  = s_axi_awburst;\n      assign m_axi_awlock   = s_axi_awlock;\n      assign m_axi_awcache  = s_axi_awcache;\n      assign m_axi_awprot   = s_axi_awprot;\n      assign m_axi_awregion = s_axi_awregion;\n      assign m_axi_awqos    = s_axi_awqos;\n      assign m_axi_awuser   = s_axi_awuser;\n      assign m_axi_awvalid  = s_axi_awvalid;\n      assign s_axi_awready  = m_axi_awready;\n      \n      assign m_axi_wid      = s_axi_wid;\n      assign m_axi_wdata    = s_axi_wdata;\n      assign m_axi_wstrb    = s_axi_wstrb;\n      assign m_axi_wlast    = s_axi_wlast;\n      assign m_axi_wuser    = s_axi_wuser;\n      assign m_axi_wvalid   = s_axi_wvalid;\n      assign s_axi_wready   = m_axi_wready;\n    \n      assign s_axi_bid      = m_axi_bid;\n      assign s_axi_bresp    = m_axi_bresp;\n      assign s_axi_buser    = m_axi_buser;\n      assign s_axi_bvalid   = m_axi_bvalid;\n      assign m_axi_bready   = s_axi_bready;\n    \n      assign m_axi_arid     = s_axi_arid;\n      assign m_axi_araddr   = s_axi_araddr;\n      assign m_axi_arlen    = s_axi_arlen;\n      assign m_axi_arsize   = s_axi_arsize;\n      assign m_axi_arburst  = s_axi_arburst;\n      assign m_axi_arlock   = s_axi_arlock;\n      assign m_axi_arcache  = s_axi_arcache;\n      assign m_axi_arprot   = s_axi_arprot;\n      assign m_axi_arregion = s_axi_arregion;\n      assign m_axi_arqos    = s_axi_arqos;\n      assign m_axi_aruser   = s_axi_aruser;\n      assign m_axi_arvalid  = s_axi_arvalid;\n      assign s_axi_arready  = m_axi_arready;\n  \n      assign s_axi_rid      = m_axi_rid;\n      assign s_axi_rdata    = m_axi_rdata;\n      assign s_axi_rresp    = m_axi_rresp;\n      assign s_axi_rlast    = m_axi_rlast;\n      assign s_axi_ruser    = m_axi_ruser;\n      assign s_axi_rvalid   = m_axi_rvalid;\n      assign m_axi_rready   = s_axi_rready;\n      \n    end else begin : gen_fifo\n      \n      wire [4-1:0]                  s_axi_awregion_i;\n      wire [4-1:0]                  s_axi_arregion_i;\n      wire [4-1:0]                  m_axi_awregion_i;\n      wire [4-1:0]                  m_axi_arregion_i;\n      wire [C_AXI_ID_WIDTH-1:0]     s_axi_wid_i;\n      wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid_i;\n      \n      assign s_axi_awregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : s_axi_awregion;\n      assign s_axi_arregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : s_axi_arregion;\n      assign m_axi_awregion = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : m_axi_awregion_i;\n      assign m_axi_arregion = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : m_axi_arregion_i;\n      assign s_axi_wid_i = (C_AXI_PROTOCOL == P_AXI3) ? s_axi_wid : {C_AXI_ID_WIDTH{1'b0}};\n      assign m_axi_wid = (C_AXI_PROTOCOL == P_AXI3) ? m_axi_wid_i : {C_AXI_ID_WIDTH{1'b0}};\n\n\n      fifo_generator_v13_2_5 #(\n          .C_EN_SAFETY_CKT(0),\n          .C_SELECT_XPM(0),\n          .C_INTERFACE_TYPE(2),\n          .C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : 3),\n          .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n          .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n          .C_HAS_AXI_ID(1),\n          .C_AXI_LEN_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 8 : 4),\n          .C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 1 : 2),\n          .C_HAS_AXI_ARUSER(1),\n          .C_HAS_AXI_AWUSER(1),\n          .C_HAS_AXI_BUSER(1),\n          .C_HAS_AXI_RUSER(1),\n          .C_HAS_AXI_WUSER(1),\n          .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n          .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n          .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n          .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),\n          .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n          .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n          .C_DIN_WIDTH_RACH(P_WIDTH_RACH),\n          .C_DIN_WIDTH_RDCH(P_WIDTH_RDCH),\n          .C_DIN_WIDTH_WACH(P_WIDTH_WACH),\n          .C_DIN_WIDTH_WDCH(P_WIDTH_WDCH),\n          .C_DIN_WIDTH_WRCH(P_WIDTH_WDCH),\n          .C_RACH_TYPE(((C_AXI_READ_FIFO_DEPTH != 0) && C_AXI_READ_FIFO_DELAY) ? 0 : 2),\n          .C_WACH_TYPE(((C_AXI_WRITE_FIFO_DEPTH != 0) && C_AXI_WRITE_FIFO_DELAY) ? 0 : 2),\n          .C_WDCH_TYPE((C_AXI_WRITE_FIFO_DEPTH != 0) ? 0 : 2),\n          .C_RDCH_TYPE((C_AXI_READ_FIFO_DEPTH != 0) ? 0 : 2),\n          .C_WRCH_TYPE(2),\n          .C_COMMON_CLOCK(1),\n          .C_ADD_NGC_CONSTRAINT(0),\n          .C_APPLICATION_TYPE_AXIS(0),\n          .C_APPLICATION_TYPE_RACH(C_AXI_READ_FIFO_DELAY ? 1 : 0),\n          .C_APPLICATION_TYPE_RDCH(0),\n          .C_APPLICATION_TYPE_WACH(C_AXI_WRITE_FIFO_DELAY ? 1 : 0),\n          .C_APPLICATION_TYPE_WDCH(0),\n          .C_APPLICATION_TYPE_WRCH(0),\n          .C_AXIS_TDATA_WIDTH(64),\n          .C_AXIS_TDEST_WIDTH(4),\n          .C_AXIS_TID_WIDTH(8),\n          .C_AXIS_TKEEP_WIDTH(4),\n          .C_AXIS_TSTRB_WIDTH(4),\n          .C_AXIS_TUSER_WIDTH(4),\n          .C_AXIS_TYPE(0),\n          .C_COUNT_TYPE(0),\n          .C_DATA_COUNT_WIDTH(10),\n          .C_DEFAULT_VALUE(\"BlankString\"),\n          .C_DIN_WIDTH(18),\n          .C_DIN_WIDTH_AXIS(1),\n          .C_DOUT_RST_VAL(\"0\"),\n          .C_DOUT_WIDTH(18),\n          .C_ENABLE_RLOCS(0),\n          .C_ENABLE_RST_SYNC(1),\n          .C_ERROR_INJECTION_TYPE(0),\n          .C_ERROR_INJECTION_TYPE_AXIS(0),\n          .C_ERROR_INJECTION_TYPE_RACH(0),\n          .C_ERROR_INJECTION_TYPE_RDCH(0),\n          .C_ERROR_INJECTION_TYPE_WACH(0),\n          .C_ERROR_INJECTION_TYPE_WDCH(0),\n          .C_ERROR_INJECTION_TYPE_WRCH(0),\n          .C_FAMILY(C_FAMILY),\n          .C_FULL_FLAGS_RST_VAL(1),\n          .C_HAS_ALMOST_EMPTY(0),\n          .C_HAS_ALMOST_FULL(0),\n          .C_HAS_AXI_RD_CHANNEL(1),\n          .C_HAS_AXI_WR_CHANNEL(1),\n          .C_HAS_AXIS_TDATA(0),\n          .C_HAS_AXIS_TDEST(0),\n          .C_HAS_AXIS_TID(0),\n          .C_HAS_AXIS_TKEEP(0),\n          .C_HAS_AXIS_TLAST(0),\n          .C_HAS_AXIS_TREADY(1),\n          .C_HAS_AXIS_TSTRB(0),\n          .C_HAS_AXIS_TUSER(0),\n          .C_HAS_BACKUP(0),\n          .C_HAS_DATA_COUNT(0),\n          .C_HAS_DATA_COUNTS_AXIS(0),\n          .C_HAS_DATA_COUNTS_RACH(0),\n          .C_HAS_DATA_COUNTS_RDCH(0),\n          .C_HAS_DATA_COUNTS_WACH(0),\n          .C_HAS_DATA_COUNTS_WDCH(0),\n          .C_HAS_DATA_COUNTS_WRCH(0),\n          .C_HAS_INT_CLK(0),\n          .C_HAS_MASTER_CE(0),\n          .C_HAS_MEMINIT_FILE(0),\n          .C_HAS_OVERFLOW(0),\n          .C_HAS_PROG_FLAGS_AXIS(0),\n          .C_HAS_PROG_FLAGS_RACH(0),\n          .C_HAS_PROG_FLAGS_RDCH(0),\n          .C_HAS_PROG_FLAGS_WACH(0),\n          .C_HAS_PROG_FLAGS_WDCH(0),\n          .C_HAS_PROG_FLAGS_WRCH(0),\n          .C_HAS_RD_DATA_COUNT(0),\n          .C_HAS_RD_RST(0),\n          .C_HAS_RST(1),\n          .C_HAS_SLAVE_CE(0),\n          .C_HAS_SRST(0),\n          .C_HAS_UNDERFLOW(0),\n          .C_HAS_VALID(0),\n          .C_HAS_WR_ACK(0),\n          .C_HAS_WR_DATA_COUNT(0),\n          .C_HAS_WR_RST(0),\n          .C_IMPLEMENTATION_TYPE(0),\n          .C_IMPLEMENTATION_TYPE_AXIS(1),\n          .C_IMPLEMENTATION_TYPE_RACH(2),\n          .C_IMPLEMENTATION_TYPE_RDCH((C_AXI_READ_FIFO_TYPE == \"bram\") ? 1 : 2),\n          .C_IMPLEMENTATION_TYPE_WACH(2),\n          .C_IMPLEMENTATION_TYPE_WDCH((C_AXI_WRITE_FIFO_TYPE == \"bram\") ? 1 : 2),\n          .C_IMPLEMENTATION_TYPE_WRCH(2),\n          .C_INIT_WR_PNTR_VAL(0),\n          .C_MEMORY_TYPE(1),\n          .C_MIF_FILE_NAME(\"BlankString\"),\n          .C_MSGON_VAL(1),\n          .C_OPTIMIZATION_MODE(0),\n          .C_OVERFLOW_LOW(0),\n          .C_PRELOAD_LATENCY(1),\n          .C_PRELOAD_REGS(0),\n          .C_PRIM_FIFO_TYPE(P_PRIM_FIFO_TYPE),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(30),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(510),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(30),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(510),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(14),\n          .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),\n          .C_PROG_EMPTY_TYPE(0),\n          .C_PROG_EMPTY_TYPE_AXIS(5),\n          .C_PROG_EMPTY_TYPE_RACH(5),\n          .C_PROG_EMPTY_TYPE_RDCH(5),\n          .C_PROG_EMPTY_TYPE_WACH(5),\n          .C_PROG_EMPTY_TYPE_WDCH(5),\n          .C_PROG_EMPTY_TYPE_WRCH(5),\n          .C_PROG_FULL_THRESH_ASSERT_VAL(1022),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(31),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(511),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(31),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(511),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),\n          .C_PROG_FULL_THRESH_NEGATE_VAL(1021),\n          .C_PROG_FULL_TYPE(0),\n          .C_PROG_FULL_TYPE_AXIS(5),\n          .C_PROG_FULL_TYPE_RACH(5),\n          .C_PROG_FULL_TYPE_RDCH(5),\n          .C_PROG_FULL_TYPE_WACH(5),\n          .C_PROG_FULL_TYPE_WDCH(5),\n          .C_PROG_FULL_TYPE_WRCH(5),\n          .C_RD_DATA_COUNT_WIDTH(10),\n          .C_RD_DEPTH(1024),\n          .C_RD_FREQ(1),\n          .C_RD_PNTR_WIDTH(10),\n          .C_REG_SLICE_MODE_AXIS(0),\n          .C_REG_SLICE_MODE_RACH(0),\n          .C_REG_SLICE_MODE_RDCH(0),\n          .C_REG_SLICE_MODE_WACH(0),\n          .C_REG_SLICE_MODE_WDCH(0),\n          .C_REG_SLICE_MODE_WRCH(0),\n          .C_UNDERFLOW_LOW(0),\n          .C_USE_COMMON_OVERFLOW(0),\n          .C_USE_COMMON_UNDERFLOW(0),\n          .C_USE_DEFAULT_SETTINGS(0),\n          .C_USE_DOUT_RST(1),\n          .C_USE_ECC(0),\n          .C_USE_ECC_AXIS(0),\n          .C_USE_ECC_RACH(0),\n          .C_USE_ECC_RDCH(0),\n          .C_USE_ECC_WACH(0),\n          .C_USE_ECC_WDCH(0),\n          .C_USE_ECC_WRCH(0),\n          .C_USE_EMBEDDED_REG(0),\n          .C_USE_FIFO16_FLAGS(0),\n          .C_USE_FWFT_DATA_COUNT(0),\n          .C_VALID_LOW(0),\n          .C_WR_ACK_LOW(0),\n          .C_WR_DATA_COUNT_WIDTH(10),\n          .C_WR_DEPTH(1024),\n          .C_WR_DEPTH_AXIS(1024),\n          .C_WR_DEPTH_RACH(32),\n          .C_WR_DEPTH_RDCH(C_AXI_READ_FIFO_DEPTH),\n          .C_WR_DEPTH_WACH(32),\n          .C_WR_DEPTH_WDCH(C_AXI_WRITE_FIFO_DEPTH),\n          .C_WR_DEPTH_WRCH(16),\n          .C_WR_FREQ(1),\n          .C_WR_PNTR_WIDTH(10),\n          .C_WR_PNTR_WIDTH_AXIS(10),\n          .C_WR_PNTR_WIDTH_RACH(5),\n          .C_WR_PNTR_WIDTH_RDCH((C_AXI_READ_FIFO_DEPTH> 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1),\n          .C_WR_PNTR_WIDTH_WACH(5),\n          .C_WR_PNTR_WIDTH_WDCH((C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1),\n          .C_WR_PNTR_WIDTH_WRCH(4),\n          .C_WR_RESPONSE_LATENCY(1)\n        )\n        fifo_gen_inst (\n          .s_aclk(aclk),\n          .s_aresetn(aresetn),\n          .s_axi_awid(s_axi_awid),\n          .s_axi_awaddr(s_axi_awaddr),\n          .s_axi_awlen(s_axi_awlen),\n          .s_axi_awsize(s_axi_awsize),\n          .s_axi_awburst(s_axi_awburst),\n          .s_axi_awlock(s_axi_awlock),\n          .s_axi_awcache(s_axi_awcache),\n          .s_axi_awprot(s_axi_awprot),\n          .s_axi_awqos(s_axi_awqos),\n          .s_axi_awregion(s_axi_awregion_i),\n          .s_axi_awuser(s_axi_awuser),\n          .s_axi_awvalid(s_axi_awvalid),\n          .s_axi_awready(s_axi_awready),\n          .s_axi_wid(s_axi_wid_i),\n          .s_axi_wdata(s_axi_wdata),\n          .s_axi_wstrb(s_axi_wstrb),\n          .s_axi_wlast(s_axi_wlast),\n          .s_axi_wvalid(s_axi_wvalid),\n          .s_axi_wready(s_axi_wready),\n          .s_axi_bid(s_axi_bid),\n          .s_axi_bresp(s_axi_bresp),\n          .s_axi_bvalid(s_axi_bvalid),\n          .s_axi_bready(s_axi_bready),\n          .m_axi_awid(m_axi_awid),\n          .m_axi_awaddr(m_axi_awaddr),\n          .m_axi_awlen(m_axi_awlen),\n          .m_axi_awsize(m_axi_awsize),\n          .m_axi_awburst(m_axi_awburst),\n          .m_axi_awlock(m_axi_awlock),\n          .m_axi_awcache(m_axi_awcache),\n          .m_axi_awprot(m_axi_awprot),\n          .m_axi_awqos(m_axi_awqos),\n          .m_axi_awregion(m_axi_awregion_i),\n          .m_axi_awuser(m_axi_awuser),\n          .m_axi_awvalid(m_axi_awvalid),\n          .m_axi_awready(m_axi_awready),\n          .m_axi_wid(m_axi_wid_i),\n          .m_axi_wdata(m_axi_wdata),\n          .m_axi_wstrb(m_axi_wstrb),\n          .m_axi_wlast(m_axi_wlast),\n          .m_axi_wvalid(m_axi_wvalid),\n          .m_axi_wready(m_axi_wready),\n          .m_axi_bid(m_axi_bid),\n          .m_axi_bresp(m_axi_bresp),\n          .m_axi_bvalid(m_axi_bvalid),\n          .m_axi_bready(m_axi_bready),\n          .s_axi_arid(s_axi_arid),\n          .s_axi_araddr(s_axi_araddr),\n          .s_axi_arlen(s_axi_arlen),\n          .s_axi_arsize(s_axi_arsize),\n          .s_axi_arburst(s_axi_arburst),\n          .s_axi_arlock(s_axi_arlock),\n          .s_axi_arcache(s_axi_arcache),\n          .s_axi_arprot(s_axi_arprot),\n          .s_axi_arqos(s_axi_arqos),\n          .s_axi_arregion(s_axi_arregion_i),\n          .s_axi_arvalid(s_axi_arvalid),\n          .s_axi_arready(s_axi_arready),\n          .s_axi_rid(s_axi_rid),\n          .s_axi_rdata(s_axi_rdata),\n          .s_axi_rresp(s_axi_rresp),\n          .s_axi_rlast(s_axi_rlast),\n          .s_axi_rvalid(s_axi_rvalid),\n          .s_axi_rready(s_axi_rready),\n          .m_axi_arid(m_axi_arid),\n          .m_axi_araddr(m_axi_araddr),\n          .m_axi_arlen(m_axi_arlen),\n          .m_axi_arsize(m_axi_arsize),\n          .m_axi_arburst(m_axi_arburst),\n          .m_axi_arlock(m_axi_arlock),\n          .m_axi_arcache(m_axi_arcache),\n          .m_axi_arprot(m_axi_arprot),\n          .m_axi_arqos(m_axi_arqos),\n          .m_axi_arregion(m_axi_arregion_i),\n          .m_axi_arvalid(m_axi_arvalid),\n          .m_axi_arready(m_axi_arready),\n          .m_axi_rid(m_axi_rid),\n          .m_axi_rdata(m_axi_rdata),\n          .m_axi_rresp(m_axi_rresp),\n          .m_axi_rlast(m_axi_rlast),\n          .m_axi_rvalid(m_axi_rvalid),\n          .m_axi_rready(m_axi_rready),\n          .m_aclk(aclk),\n          .m_aclk_en(1'b1),\n          .s_aclk_en(1'b1),\n          .s_axi_wuser(s_axi_wuser),\n          .s_axi_buser(s_axi_buser),\n          .m_axi_wuser(m_axi_wuser),\n          .m_axi_buser(m_axi_buser),\n          .s_axi_aruser(s_axi_aruser),\n          .s_axi_ruser(s_axi_ruser),\n          .m_axi_aruser(m_axi_aruser),\n          .m_axi_ruser(m_axi_ruser),\n          .almost_empty(),\n          .almost_full(),\n          .axis_data_count(),\n          .axis_dbiterr(),\n          .axis_injectdbiterr(1'b0),\n          .axis_injectsbiterr(1'b0),\n          .axis_overflow(),\n          .axis_prog_empty(),\n          .axis_prog_empty_thresh(10'b0),\n          .axis_prog_full(),\n          .axis_prog_full_thresh(10'b0),\n          .axis_rd_data_count(),\n          .axis_sbiterr(),\n          .axis_underflow(),\n          .axis_wr_data_count(),\n          .axi_ar_data_count(),\n          .axi_ar_dbiterr(),\n          .axi_ar_injectdbiterr(1'b0),\n          .axi_ar_injectsbiterr(1'b0),\n          .axi_ar_overflow(),\n          .axi_ar_prog_empty(),\n          .axi_ar_prog_empty_thresh(5'b0),\n          .axi_ar_prog_full(),\n          .axi_ar_prog_full_thresh(5'b0),\n          .axi_ar_rd_data_count(),\n          .axi_ar_sbiterr(),\n          .axi_ar_underflow(),\n          .axi_ar_wr_data_count(),\n          .axi_aw_data_count(),\n          .axi_aw_dbiterr(),\n          .axi_aw_injectdbiterr(1'b0),\n          .axi_aw_injectsbiterr(1'b0),\n          .axi_aw_overflow(),\n          .axi_aw_prog_empty(),\n          .axi_aw_prog_empty_thresh(5'b0),\n          .axi_aw_prog_full(),\n          .axi_aw_prog_full_thresh(5'b0),\n          .axi_aw_rd_data_count(),\n          .axi_aw_sbiterr(),\n          .axi_aw_underflow(),\n          .axi_aw_wr_data_count(),\n          .axi_b_data_count(),\n          .axi_b_dbiterr(),\n          .axi_b_injectdbiterr(1'b0),\n          .axi_b_injectsbiterr(1'b0),\n          .axi_b_overflow(),\n          .axi_b_prog_empty(),\n          .axi_b_prog_empty_thresh(4'b0),\n          .axi_b_prog_full(),\n          .axi_b_prog_full_thresh(4'b0),\n          .axi_b_rd_data_count(),\n          .axi_b_sbiterr(),\n          .axi_b_underflow(),\n          .axi_b_wr_data_count(),\n          .axi_r_data_count(),\n          .axi_r_dbiterr(),\n          .axi_r_injectdbiterr(1'b0),\n          .axi_r_injectsbiterr(1'b0),\n          .axi_r_overflow(),\n          .axi_r_prog_empty(),\n          .axi_r_prog_empty_thresh({P_READ_FIFO_DEPTH_LOG{1'b0}}),\n          .axi_r_prog_full(),\n          .axi_r_prog_full_thresh({P_READ_FIFO_DEPTH_LOG{1'b0}}),\n          .axi_r_rd_data_count(),\n          .axi_r_sbiterr(),\n          .axi_r_underflow(),\n          .axi_r_wr_data_count(),\n          .axi_w_data_count(),\n          .axi_w_dbiterr(),\n          .axi_w_injectdbiterr(1'b0),\n          .axi_w_injectsbiterr(1'b0),\n          .axi_w_overflow(),\n          .axi_w_prog_empty(),\n          .axi_w_prog_empty_thresh({P_WRITE_FIFO_DEPTH_LOG{1'b0}}),\n          .axi_w_prog_full(),\n          .axi_w_prog_full_thresh({P_WRITE_FIFO_DEPTH_LOG{1'b0}}),\n          .axi_w_rd_data_count(),\n          .axi_w_sbiterr(),\n          .axi_w_underflow(),\n          .axi_w_wr_data_count(),\n          .backup(1'b0),\n          .backup_marker(1'b0),\n          .clk(1'b0),\n          .data_count(),\n          .dbiterr(),\n          .din(18'b0),\n          .dout(),\n          .empty(),\n          .full(),\n          .injectdbiterr(1'b0),\n          .injectsbiterr(1'b0),\n          .int_clk(1'b0),\n          .m_axis_tdata(),\n          .m_axis_tdest(),\n          .m_axis_tid(),\n          .m_axis_tkeep(),\n          .m_axis_tlast(),\n          .m_axis_tready(1'b0),\n          .m_axis_tstrb(),\n          .m_axis_tuser(),\n          .m_axis_tvalid(),\n          .overflow(),\n          .prog_empty(),\n          .prog_empty_thresh(10'b0),\n          .prog_empty_thresh_assert(10'b0),\n          .prog_empty_thresh_negate(10'b0),\n          .prog_full(),\n          .prog_full_thresh(10'b0),\n          .prog_full_thresh_assert(10'b0),\n          .prog_full_thresh_negate(10'b0),\n          .rd_clk(1'b0),\n          .rd_data_count(),\n          .rd_en(1'b0),\n          .rd_rst(1'b0),\n          .rst(1'b0),\n          .sbiterr(),\n          .srst(1'b0),\n          .s_axis_tdata(64'b0),\n          .s_axis_tdest(4'b0),\n          .s_axis_tid(8'b0),\n          .s_axis_tkeep(4'b0),\n          .s_axis_tlast(1'b0),\n          .s_axis_tready(),\n          .s_axis_tstrb(4'b0),\n          .s_axis_tuser(4'b0),\n          .s_axis_tvalid(1'b0),\n          .underflow(),\n          .valid(),\n          .wr_ack(),\n          .wr_clk(1'b0),\n          .wr_data_count(),\n          .wr_en(1'b0),\n          .wr_rst(1'b0),\n          .wr_rst_busy(),\n          .rd_rst_busy(),\n          .sleep(1'b0)\n        );\n    end\n  endgenerate\nendmodule\n\n\n\n", "num_lines": 1957}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_master #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_SUPPORTS_NARROW = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1,\n   parameter [C_AXI_ADDR_WIDTH-1:0] C_AXI_ADDR = 0,  // Base address\n   parameter integer C_NUM_ADDR = 1,  // Number of address iterations; range 1..2**16 (fixed increment = 32'h10000\n   parameter integer C_NUM_ID = 1,  // Number of ID iterations; range 1..2**C_ID_WIDTH (base = 0; fixed increment = 1)\n   parameter integer C_NUM_LEN = 1,  // Number of LEN iterations; range 1..9 (base = 0; value = 2**i - 1)\n   parameter integer C_NUM_TRANS = 1  // Number of transactions; range >=1 (read and write)\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_awvalid,\n  input  wire                            m_axi_awready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_awburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_awlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_awlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_awid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]    m_axi_awuser = 'b0,\n  /**************** Write Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_wid,\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]      m_axi_wdata,\n  (* dont_touch=\"true\" *) output reg [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb = {(C_AXI_DATA_WIDTH/8){1'b1}},\n  (* dont_touch=\"true\" *) output wire                             m_axi_wvalid,\n  input  wire                            m_axi_wready,\n  (* dont_touch=\"true\" *) output wire                             m_axi_wlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]     m_axi_wuser = 'b0,\n  /**************** Write Response Channel Signals ****************/\n  input  wire [2-1:0]                    m_axi_bresp,\n  input  wire                            m_axi_bvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_bready,\n  input  wire [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]     m_axi_buser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_bid,\n  /**************** Read Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_arvalid,\n  input  wire                            m_axi_arready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_arburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_arlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_arlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_arid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]    m_axi_aruser = 'b0,\n  /**************** Read Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]      m_axi_rdata,\n  input  wire [2-1:0]                    m_axi_rresp,\n  input  wire                            m_axi_rvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_rready,\n  input  wire                            m_axi_rlast,\n  input  wire [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]     m_axi_ruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_rid,\n  /**************** System Signals ****************/\n  input  wire                            aclk,\n  input  wire                            aresetn\n  );\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n  localparam integer  P_NUM_ID_LOG = f_ceil_log2(C_NUM_ID);\n  localparam integer  P_NUM_ADDR_LOG = f_ceil_log2(C_NUM_ADDR);\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL==0 ? 8 : C_AXI_PROTOCOL==1 ? 4 : 1);\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer               P_M_AXI_DATA_BYTES = (C_AXI_DATA_WIDTH / 8);\n  localparam integer               P_M_AXI_DONE_WIDTH = f_ceil_log2(C_NUM_TRANS<2?2:C_NUM_TRANS);\n  localparam integer               P_M_AXI_SIZE = f_ceil_log2(C_AXI_DATA_WIDTH)-3;\n\n  /**************** Internal Wires/Regs - Global ****************/\n   wire                            done;\n    wire                            dummy ;\n  reg                         done_i;\n  reg                         done_sel;\n  wire                         done_cycle;\n  reg                          done_d1 = 1'b0;\n  reg                   areset = 1'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] arcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] rcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [3:0]                    acc_r_i = 4'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] awcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] wcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] bcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [2:0]                    acc_b_i = 3'b0;\n\n  // Register Reset\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    \n    /**************** Internal Wires/Regs - Read Channels ****************/\n    wire                         read_xaction_done_i;\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_arid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_ADDR_WIDTH:0]      araddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  arprot_i = 3'b0;\n    reg [3-1:0]                  arsize_i = 3'b0;\n    reg [2-1:0]                  arburst_i = 2'b0;\n    reg [4-1:0]                  arcache_i = 4'b0;\n    reg [2-1:0]                  arlock_i = 2'b0;\n    reg [P_LEN_WIDTH-1:0]     arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [4-1:0]                  arqos_i = 4'b0;\n    reg [P_ID_WIDTH-1:0]        arid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [2-1:0]                  rresp_i = 2'b00;\n    reg [C_AXI_RUSER_WIDTH:0]   ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      rid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_arvalid_i = 1'b0;\n    reg                        m_axi_rready_i = 1'b0;\n    reg [P_NUM_ADDR_LOG:0]    araddr_cnt = 0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign read_xaction_done_i = m_axi_rvalid && m_axi_rready_i && ((C_AXI_PROTOCOL==2)?1'b1:m_axi_rlast);\n    assign m_axi_arvalid = m_axi_arvalid_i;\n    assign m_axi_rready = m_axi_rready_i;\n    assign m_axi_araddr = m_axi_araddr_i;\n    assign m_axi_arlen = m_axi_arlen_i;\n    always @(posedge aclk) begin\n      m_axi_arprot <= dummy ? arprot_i : 3'b000;\n      m_axi_arsize <= dummy ? arsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_arburst <= dummy ? arburst_i : 2'b01;\n      m_axi_arlock <= dummy ? arlock_i : 1'b0;\n      m_axi_arcache <= dummy ? arcache_i : 4'h3;\n      m_axi_arqos <= dummy  ? arqos_i : 4'h0;\n      m_axi_aruser <= dummy ? aruser_i : 0;\n    end\n  \n    //**********************************************\n    // Read Channel: ARVALID, ARADDR, ARLEN, RREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_arvalid_i <= 1'b0;\n        arcnt_i <= C_NUM_TRANS;\n        m_axi_arlen_i <= 0;\n        m_axi_araddr_i <= C_AXI_ADDR;\n        m_axi_arid_i <= 1;\n        araddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_arready & m_axi_arvalid_i) begin\n          arcnt_i <= arcnt_i - 1;\n          if (araddr_cnt == 1) begin\n            m_axi_araddr_i <= dummy ? araddr_i : C_AXI_ADDR;\n            araddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_araddr_i <= m_axi_araddr_i + 32'h10000;\n            araddr_cnt <= araddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_arlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_arlen_i <= dummy ? arlen_i : 0;\n          end else begin\n            m_axi_arlen_i <= (m_axi_arlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_arid_i == C_NUM_ID)) begin\n            m_axi_arid <= dummy ? arid_i : 0;\n            m_axi_arid_i <= 1;\n          end else begin\n            m_axi_arid <= m_axi_arid_i;\n            m_axi_arid_i <= m_axi_arid_i + 1;\n          end\n          if (arcnt_i == 1) begin\n            m_axi_arvalid_i <= 1'b0;\n          end\n        end else if (arcnt_i != 0) begin\n          m_axi_arvalid_i <= 1'b1;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      araddr_i <= {araddr_i, ~araddr_i[C_AXI_ADDR_WIDTH]};\n      arprot_i <= {arprot_i, ~arprot_i[3-1]};\n      arlen_i <= {arlen_i, ~arlen_i[P_LEN_WIDTH-1]};\n      arsize_i <= {arsize_i, ~arsize_i[3-1]};\n      arburst_i <= {arburst_i, ~arburst_i[2-1]};\n      arlock_i <= {arlock_i, ~arlock_i[2-1]};\n      arcache_i <= {arcache_i, ~arcache_i[4-1]};\n      arqos_i <= {arqos_i, ~arqos_i[4-1]};\n      aruser_i <= {aruser_i, ~aruser_i[C_AXI_ARUSER_WIDTH]};\n      arid_i <= {arid_i, ~arid_i[P_ID_WIDTH-1]};\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        m_axi_rready_i <= 1'b0;\n        rcnt_i <= C_NUM_TRANS;\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        rresp_i <= {2{1'b0}};\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n        rid_i <= {P_ID_WIDTH{1'b0}};\n        acc_r_i <= 4'b0;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_rvalid & m_axi_rready_i) begin\n          m_axi_rready_i <= 1'b0;\n          rdata_i <= m_axi_rdata;\n            acc_r_i[0] <= rdata_i[0];\n          rresp_i <= m_axi_rresp;\n            acc_r_i[1] <= rresp_i[0];\n          ruser_i <= m_axi_ruser;\n            acc_r_i[2] <= ruser_i[0];\n          rid_i <= m_axi_rid;\n            acc_r_i[3] <= rid_i[0];\n          if (m_axi_rlast) begin\n            rcnt_i <= rcnt_i - 1;\n          end\n        end else begin\n          rdata_i <= rdata_i>>1;\n          rresp_i <= rresp_i>>1;\n          ruser_i <= ruser_i>>1;\n          rid_i <= rid_i>>1;\n          acc_r_i <= acc_r_i>>1;\n          if (m_axi_rvalid) begin\n            m_axi_rready_i <= 1'b1;\n          end\n        end\n      end\n    end\n    \n    assign dummy = rdata_i[0];\n    \n    \n\n    /**************** Internal Wires/Regs - Write Channels ****************/\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_awid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [8-1:0]                  xfer_w_i = 8'h00;\n    wire                         write_burst_done_i;\n    reg [C_AXI_ADDR_WIDTH:0]      awaddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  awprot_i = 3'b0;\n    reg [P_LEN_WIDTH-1:0]     awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [3-1:0]                  awsize_i = 3'b0;\n    reg [2-1:0]                  awburst_i = 2'b0;\n    reg [4-1:0]                  awcache_i = 4'b0;\n    reg [2-1:0]                  awlock_i = 2'b0;\n    reg [4-1:0]                  awqos_i = 4'b0;\n    reg [P_ID_WIDTH:0]        awid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_AWUSER_WIDTH:0]    awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg [P_M_AXI_DATA_BYTES-1:0] wstrb_i = {P_M_AXI_DATA_BYTES{1'b1}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]        wid_i = {P_ID_WIDTH{1'b0}};\n    reg [2-1:0]                  bresp_i = 2'b00;\n    reg [C_AXI_BUSER_WIDTH:0]   buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      bid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_awvalid_i = 1'b0;\n    reg                        m_axi_wvalid_i = 1'b0;\n    reg                        m_axi_bready_i = 1'b0;\n    reg                        m_axi_wlast_i = 1'b0;\n    reg                        m_axi_wid_i = {P_ID_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]     wlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [P_NUM_ADDR_LOG:0]    awaddr_cnt = 0;\n  \n    /**************** Assign Write Channel Outputs ****************/\n    assign m_axi_wdata = {wdata_i, done};\n    assign write_burst_done_i = m_axi_wready && m_axi_wvalid_i && ((C_AXI_PROTOCOL==2) || m_axi_wlast_i);\n    assign m_axi_awvalid = m_axi_awvalid_i;\n    assign m_axi_wvalid = m_axi_wvalid_i;\n    assign m_axi_bready = m_axi_bready_i;\n    assign m_axi_wlast = m_axi_wlast_i;\n    assign m_axi_awaddr = m_axi_awaddr_i;\n    assign m_axi_awlen = m_axi_awlen_i;\n    assign m_axi_wid = m_axi_wid_i;\n    always @(posedge aclk) begin\n      m_axi_awprot <= dummy ? awprot_i : 3'b000;\n      m_axi_awsize <= dummy ? awsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_awburst <= dummy ? awburst_i : 2'b01;\n      m_axi_awlock <= dummy ? awlock_i : 1'b0;\n      m_axi_awcache <= dummy ? awcache_i : 4'h3;\n      m_axi_awqos <= dummy ? awqos_i : 4'h0;\n      m_axi_wstrb <= dummy ? wstrb_i : {P_M_AXI_DATA_BYTES{1'b1}};\n      m_axi_awuser <= dummy ?  awuser_i : 0;\n      m_axi_wuser <= dummy ?  wuser_i : 0;\n    end\n  \n    //**********************************************\n    // Write Channel: AWVALID, AWADDR, AWLEN, WVALID, WLAST, BREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_awvalid_i <= 1'b0;\n        m_axi_wvalid_i <= 1'b0;\n        awcnt_i <= C_NUM_TRANS;\n        wcnt_i <= C_NUM_TRANS;\n        xfer_w_i <= 8'h00;\n        m_axi_awlen_i <= 0;\n        m_axi_awaddr_i <= C_AXI_ADDR;\n        m_axi_awid_i <= 1;\n        m_axi_wid_i <= 0;\n        m_axi_wlast_i <= 1'b0;\n        wlen_i <= 0;\n        wid_i <= 0;\n        awaddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_awvalid_i <= 1'b0;\n          awcnt_i <= awcnt_i - 1;\n          if (awaddr_cnt == 1) begin\n            m_axi_awaddr_i <= dummy ? awaddr_i : C_AXI_ADDR;\n            awaddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_awaddr_i <= m_axi_awaddr_i + 32'h10000;\n            awaddr_cnt <= awaddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_awlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_awlen_i <= dummy ? awlen_i : 0;\n          end else begin\n            m_axi_awlen_i <= (m_axi_awlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_awid_i == C_NUM_ID)) begin\n            m_axi_awid <= dummy ? awid_i : 0;\n            m_axi_awid_i <= 1;\n          end else begin\n            m_axi_awid <= m_axi_awid_i;\n            m_axi_awid_i <= m_axi_awid_i + 1;\n          end\n        end else if (~m_axi_wvalid_i) begin\n          if (awcnt_i != 0) begin\n            m_axi_awvalid_i <= 1'b1;\n          end\n        end\n  \n        /**************** Write Data Channel ****************/\n\n        if (m_axi_wready && m_axi_wvalid_i) begin\n          xfer_w_i <= xfer_w_i - 1'b1;\n          if (m_axi_wlast_i) begin\n            m_axi_wvalid_i <= 1'b0;\n            wcnt_i <= wcnt_i - 1'b1;\n          end else begin\n            m_axi_wlast_i <=  (xfer_w_i == 1);\n          end\n        end else if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_wvalid_i <= 1'b1;\n          xfer_w_i <= m_axi_awlen_i;\n          m_axi_wlast_i <= (m_axi_awlen_i==0);\n          m_axi_wid_i <= m_axi_awid_i;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: WDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        wdata_i <= (m_axi_wvalid_i && m_axi_wready) ? {wdata_i[C_AXI_DATA_WIDTH-2 : 0], ~wdata_i[C_AXI_DATA_WIDTH-1]} : wdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      awaddr_i <= {awaddr_i, ~awaddr_i[C_AXI_ADDR_WIDTH]};\n      awprot_i <= {awprot_i[3-2:0], ~awprot_i[3-1]};\n      wstrb_i <= {wstrb_i, ~wstrb_i[C_AXI_DATA_WIDTH/8-1]};\n      awlen_i <= {awlen_i, ~awlen_i[P_LEN_WIDTH-1]};\n      awsize_i <= {awsize_i, ~awsize_i[3-1]};\n      awburst_i <= {awburst_i, ~awburst_i[2-1]};\n      awlock_i <= {awlock_i, ~awlock_i[2-1]};\n      awcache_i <= {awcache_i, ~awcache_i[4-1]};\n      awqos_i <= {awqos_i, ~awqos_i[4-1]};\n      awid_i <= {awid_i, ~awid_i[P_ID_WIDTH-1]};\n      awuser_i <= {awuser_i, ~awuser_i[C_AXI_AWUSER_WIDTH]};\n      wuser_i <= {wuser_i, ~wuser_i[C_AXI_WUSER_WIDTH]};\n    end\n  \n    //**********************************************\n    // Write Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_bready_i <= 1'b0;\n        bcnt_i <= C_NUM_TRANS;\n        bresp_i <= {2{1'b0}};\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n        bid_i <= {P_ID_WIDTH{1'b0}};\n        acc_b_i <= 3'b0;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_bvalid & m_axi_bready_i) begin\n          m_axi_bready_i <= 1'b0;\n          bresp_i <= m_axi_bresp;\n            acc_b_i[0] <= bresp_i[0];\n          buser_i <= m_axi_buser;\n            acc_b_i[1] <= buser_i[0];\n          bid_i <= m_axi_bid;\n            acc_b_i[2] <= bid_i[0];\n          bcnt_i <= bcnt_i - 1;\n        end else begin\n          bresp_i <= bresp_i>>1;\n          buser_i <= buser_i>>1;\n          bid_i <= bid_i>>1;\n          acc_b_i <= acc_b_i>>1;\n          if (m_axi_bvalid) begin\n            m_axi_bready_i <= 1'b1;\n          end\n        end\n      end\n    end\n\n\n  //**********************************************\n  // Assert Done\n  //**********************************************\n  always @(posedge aclk) begin\n    if (~aresetn) begin\n      done_d1 <= 1'b0;\n    end else begin\n      done_d1 <= done_i;\n    end\n  end\n\n  assign done = done_sel ? done_i : done_d1;\n  assign done_cycle = done_i & ~done_d1;\n  \n  always @ * begin\n    if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_readonly_done\n       done_i = rcnt_i==0;\n       done_sel = acc_r_i[0];\n    end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_writeonly_done\n       done_i = bcnt_i==0;\n       done_sel = acc_b_i[0];\n    end else begin : gen_readwrite_done\n       done_i = (rcnt_i==0) && (bcnt_i==0);\n       done_sel = acc_r_i[0] ^ acc_b_i[0];\n    end\n  end\n  \nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n  input  wire [3-1:0]                   s_axi_awprot,\n  input  wire                           s_axi_awvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_awready,\n  input  wire [3-1:0]                   s_axi_awsize,\n  input  wire [2-1:0]                   s_axi_awburst,\n  input  wire [4-1:0]                   s_axi_awcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_awlen,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_awlock,\n  input  wire [4-1:0]                   s_axi_awqos,\n  input  wire [4-1:0]                   s_axi_awregion,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_awid,\n  input  wire [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]   s_axi_awuser,\n  /**************** Write Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n  input  wire                           s_axi_wvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_wready,\n  input  wire                           s_axi_wlast,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_wid,\n  input  wire [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]    s_axi_wuser,\n  /**************** Write Response Channel Signals ****************/\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_bresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_bvalid,\n  input  wire                           s_axi_bready,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]    s_axi_buser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_bid = 'b0,\n  /**************** Read Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n  input  wire [3-1:0]                   s_axi_arprot,\n  input  wire                           s_axi_arvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_arready,\n  input  wire [3-1:0]                   s_axi_arsize,\n  input  wire [2-1:0]                   s_axi_arburst,\n  input  wire [4-1:0]                   s_axi_arcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_arlock,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_arlen,\n  input  wire [4-1:0]                   s_axi_arqos,\n  input  wire [4-1:0]                   s_axi_arregion,\n  input  wire [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]   s_axi_aruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_arid,\n  /**************** Read Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_rresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rvalid,\n  input  wire                           s_axi_rready,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]    s_axi_ruser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_rid = 'b0,\n  /**************** System Signals ****************/\n  input  wire                           aclk,\n  input  wire                           aresetn\n   );\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL == 1) ? 4 : 8;\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer P_S_AXI_DATA_BYTES = 32/8;\n  localparam integer P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n\n  /**************** Internal Wires/Regs - Global ****************/\n  reg                   areset = 1'b0;\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    /**************** Internal Wires/Regs - Read Channels ****************/\n    reg [8-1:0]                   xfer_r_cnt = 8'h00;\n    reg [16-1:0]                  arcnt_i = 16'h0000;\n    wire                          read_xaction_done_i;\n    reg [C_AXI_DATA_WIDTH-1:0]     rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]      arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg                           arvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     araddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   arprot_i = 3'b000;\n    reg [3-1:0]                   arsize_i = 3'b000;\n    reg [2-1:0]                   arburst_i = 2'b00;\n    reg [4-1:0]                   arcache_i = 4'b0000;\n    reg [1-1:0]     arlock_i = 1'b0;\n    reg [4-1:0]                   arqos_i = 4'b0000;\n    reg [4-1:0]                   arregion_i = 4'b0000;\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_RUSER_WIDTH:0]     ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_ar_i = 9'b0;\n    reg                           s_axi_rvalid_i = 1'b0;\n    reg                           s_axi_arready_i = 1'b0;\n    reg                           s_axi_rlast_i = 1'b0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign s_axi_rdata = rdata_i;\n    assign read_xaction_done_i = (s_axi_rready && s_axi_rvalid_i && s_axi_rlast_i);\n    assign s_axi_rvalid = s_axi_rvalid_i;\n    assign s_axi_arready = s_axi_arready_i;\n    assign s_axi_rlast = s_axi_rlast_i;\n    //**********************************************\n    // Read Channel: ARREADY, RVALID, RLAST, RID\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        xfer_r_cnt <= 8'h00;\n        arcnt_i <= 16'h0000;\n        arlen_i <= {P_LEN_WIDTH{1'b0}};\n        s_axi_rlast_i <= 1'b0;\n      end else begin\n        /**************** Read Address Channel ****************/\n        // arready\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_arready_i <= 1'b0;\n          arcnt_i <= arcnt_i + 1'b1;\n        end else if (~s_axi_rvalid_i) begin\n          s_axi_arready_i <= 1'b1;\n        end\n  \n        /**************** Read Data Channel ****************/\n        // rvalid\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_rvalid_i <= 1'b1;\n          s_axi_rid <= s_axi_arid;\n          s_axi_ruser <= ruser_i;\n        end else if(read_xaction_done_i) begin\n          s_axi_rvalid_i <= 1'b0;\n        end\n  \n        // rlast\n        if(s_axi_rready && s_axi_rvalid_i) begin\n          xfer_r_cnt <= xfer_r_cnt - 1;\n          if(xfer_r_cnt == 1) begin\n            s_axi_rlast_i <= 1'b1;\n          end\n        end else if(s_axi_arready_i && s_axi_arvalid) begin\n          xfer_r_cnt <= s_axi_arlen;\n          s_axi_rlast_i <= (s_axi_arlen==0);\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Read Channel: RDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        rdata_i <= (s_axi_rready && s_axi_rvalid_i) ? {rdata_i[C_AXI_DATA_WIDTH-2 : 0], ~rdata_i[C_AXI_DATA_WIDTH-1]} : rdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_rresp <= {2{1'b0}};\n      end else if (~s_axi_rvalid_i) begin\n        s_axi_rresp <= {acc_ar_i[0], 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n      end else begin\n        ruser_i <= (s_axi_arready_i && s_axi_arvalid) ? {ruser_i, ~ruser_i[C_AXI_RUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        araddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        arprot_i <= {3{1'b0}};\n        arsize_i <= {3{1'b0}};\n        arburst_i <= {2{1'b0}};\n        arcache_i <= {4{1'b0}};\n        arlock_i <= {1{1'b0}};\n        arqos_i <= {4{1'b0}};\n        arregion_i <= {4{1'b0}};\n        aruser_i <= {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n        acc_ar_i <= 9'b0;\n      end else if (s_axi_arvalid) begin\n        // Register Inputs\n        araddr_i <= s_axi_araddr;\n          acc_ar_i[0] <= araddr_i[0];\n        arprot_i <= s_axi_arprot;\n          acc_ar_i[1] <= arprot_i[0];\n        arsize_i <= s_axi_arsize;\n          acc_ar_i[2] <= arsize_i[0];\n        arburst_i <= s_axi_arburst;\n          acc_ar_i[3] <= arburst_i[0];\n        arcache_i <= s_axi_arcache;\n          acc_ar_i[4] <= arcache_i[0];\n        arlock_i <= s_axi_arlock;\n          acc_ar_i[5] <= arlock_i[0];\n        arqos_i <= s_axi_arqos;\n          acc_ar_i[6] <= arqos_i[0];\n        arregion_i <= s_axi_arregion;\n          acc_ar_i[7] <= arregion_i[0];\n        aruser_i <= s_axi_aruser;\n          acc_ar_i[8] <= aruser_i[0];\n      end else begin\n        araddr_i <= araddr_i>>1;\n        arprot_i <= arprot_i>>1;\n        arsize_i <= arsize_i>>1;\n        arburst_i <= arburst_i>>1;\n        arcache_i <= arcache_i>>1;\n        arlock_i <= arlock_i>>1;\n        arqos_i <= arqos_i>>1;\n        arregion_i <= arregion_i>>1;\n        aruser_i <= aruser_i>>1;\n        acc_ar_i <= acc_ar_i>>1;\n      end\n    end\n  \n  \n    /**************** Internal Wires/Regs - Write Channels ****************/\n    wire                          write_burst_done_i;\n    reg [16-1:0]                  awcnt_i = 16'h0000;\n    reg                           awvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     awaddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   awprot_i = 3'b000;\n    reg [3-1:0]                   awsize_i = 3'b000;\n    reg [2-1:0]                   awburst_i = 2'b00;\n    reg [4-1:0]                   awcache_i = 4'b0000;\n    reg [P_LEN_WIDTH-1:0]      awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [1-1:0]     awlock_i = 1'b0;\n    reg [4-1:0]                   awqos_i = 4'b0000;\n    reg [4-1:0]                   awregion_i = 4'b0000;\n    reg [C_AXI_AWUSER_WIDTH:0]     awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg                           wvalid_i = 1'b0;\n    reg [C_AXI_DATA_WIDTH-1:0]     wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH/8-1:0]   wstrb_i = {(C_AXI_DATA_WIDTH/8){1'b0}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_BUSER_WIDTH:0]     buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_aw_i = 9'b0;\n    reg [3:0]                     acc_w_i = 4'b0;\n    reg                           s_axi_bvalid_i = 1'b0;\n    reg                           s_axi_awready_i = 1'b0;\n    reg                           s_axi_wready_i = 1'b0;\n    /**************** Assign Write Channel Outputs ****************/\n    assign write_burst_done_i =s_axi_wready_i && s_axi_wvalid && ((C_AXI_PROTOCOL == 2) ? 1'b1 : s_axi_wlast);\n    assign s_axi_bvalid = s_axi_bvalid_i;\n    assign s_axi_awready = s_axi_awready_i;\n    assign s_axi_wready = s_axi_wready_i;\n  \n    //**********************************************\n    // Write Channel: AWREADY, WREADY, BVALID, BID\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awcnt_i <= 16'h0000;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        /**************** Write Address Channel ****************/\n        // awready\n        if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_awready_i <= 1'b0;\n          awcnt_i <= awcnt_i + 1'b1;\n          s_axi_bid <= s_axi_awid;\n          s_axi_buser <= buser_i;\n        end else if(~s_axi_wready_i & ~s_axi_bvalid_i) begin\n          s_axi_awready_i <= 1'b1;\n        end\n  \n        /**************** Write Data Channel ****************/\n        // wready\n        if(write_burst_done_i) begin\n          s_axi_wready_i <= 1'b0;\n        end else if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_wready_i <= 1'b1;\n        end\n  \n        /**************** Write Response Channel ****************/\n        // bvalid\n        if(write_burst_done_i) begin\n          s_axi_bvalid_i <= 1'b1;\n        end else if(s_axi_bready && s_axi_bvalid_i) begin\n          s_axi_bvalid_i <= 1'b0;\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Write Channel: BRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_bresp <= {2{1'b0}};\n      end else if (~s_axi_bvalid_i) begin\n        s_axi_bresp <= {(acc_aw_i[0] ^ acc_w_i[0]), 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: BUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (aresetn) begin\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n      end else begin\n        buser_i <= (s_axi_awready_i && s_axi_awvalid) ? {buser_i, ~buser_i[C_AXI_BUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Write Address Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awaddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        awprot_i <= {3{1'b0}};\n        awsize_i <= {3{1'b0}};\n        awburst_i <= {2{1'b0}};\n        awcache_i <= {4{1'b0}};\n        awlen_i <= {P_LEN_WIDTH{1'b0}};\n        awlock_i <= {1{1'b0}};\n        awqos_i <= {4{1'b0}};\n        awregion_i <= {4{1'b0}};\n        awuser_i <= {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n        acc_aw_i <= 9'b0;\n      end else if (s_axi_awvalid) begin\n        // Register Inputs\n        awaddr_i <= s_axi_awaddr;\n          acc_aw_i[0] <= awaddr_i[0];\n        awprot_i <= s_axi_awprot;\n          acc_aw_i[1] <= awprot_i[0];\n        awsize_i <= s_axi_awsize;\n          acc_aw_i[2] <= awsize_i[0];\n        awburst_i <= s_axi_awburst;\n          acc_aw_i[3] <= awburst_i[0];\n        awcache_i <= s_axi_awcache;\n          acc_aw_i[4] <= awcache_i[0];\n        awlock_i <= s_axi_awlock;\n          acc_aw_i[5] <= awlock_i[0];\n        awqos_i <= s_axi_awqos;\n          acc_aw_i[6] <= awqos_i[0];\n        awregion_i <= s_axi_awregion;\n          acc_aw_i[7] <= awregion_i[0];\n        awuser_i <= s_axi_awuser;\n          acc_aw_i[8] <= awuser_i[0];\n      end else begin\n        awaddr_i <= awaddr_i>>1;\n        awprot_i <= awprot_i>>1;\n        awsize_i <= awsize_i>>1;\n        awburst_i <= awburst_i>>1;\n        awcache_i <= awcache_i>>1;\n        awlock_i <= awlock_i>>1;\n        awqos_i <= awqos_i>>1;\n        awregion_i <= awregion_i>>1;\n        awuser_i <= awuser_i>>1;\n        acc_aw_i <= acc_aw_i>>1;\n      end\n    end\n  \n    //**********************************************\n    // Write Data Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        wstrb_i <= {(C_AXI_DATA_WIDTH/8){1'b0}};\n        wuser_i <= {(C_AXI_WUSER_WIDTH+1){1'b0}};\n        acc_w_i <= 4'b0;\n      end else if (s_axi_wvalid) begin\n        // Register Inputs\n        wdata_i <= s_axi_wdata;\n          acc_w_i[0] <= wdata_i[0];\n        wstrb_i <= s_axi_wstrb;\n          acc_w_i[1] <= wstrb_i[0];\n        wuser_i <= s_axi_wuser;\n          acc_w_i[2] <= wuser_i[0];\n      end else begin\n        wdata_i <= wdata_i>>1;\n        wstrb_i <= wstrb_i>>1;\n        wuser_i <= wuser_i>>1;\n        acc_w_i <= acc_w_i>>1;\n      end\n    end\n  \nendmodule\n\n\n\n//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_22_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \n(* autopipeline_module=\"yes\" *)\nmodule axi_register_slice_v2_1_22_auto_slr #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n    wire                    handshake_pipe;\n    wire                    ready_pipe;\n    wire [C_DATA_WIDTH-1:0] payload_pipe;\n    (* keep=\"true\" *)                                                                reg  s_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  s_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  s_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  s_areset_resp2 = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  m_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  m_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_areset_resp2 = 1'b0;\n    \n  // Global Reset pipelining\n  \n    always @(posedge ACLK) begin\n      s_aclear       <= ~ARESETN;\n      s_areset_fwd   <= ~ARESETN; \n      s_areset_resp  <= s_areset_fwd;  // Auto-pipeline\n      s_areset_resp2 <= s_areset_resp; // Auto-pipeline\n    end\n    \n    always @(posedge ACLK) begin\n      m_aclear       <= ~ARESETN;\n      m_areset_fwd   <= ~ARESETN; \n      m_areset_resp  <= m_areset_fwd;  // Auto-pipeline\n      m_areset_resp2 <= m_areset_resp; // Auto-pipeline\n    end\n    \n  // Source-side submodule\n    \n    axi_register_slice_v2_1_22_auto_src #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_src\n      (\n       .ACLK             (ACLK),    \n       .s_aclear         (s_aclear),\n       .s_areset_resp2   (s_areset_resp2),  \n       .S_VALID          (S_VALID),  \n       .S_READY          (S_READY), \n       .S_PAYLOAD_DATA   (S_PAYLOAD_DATA),\n       .ready_pipe        (ready_pipe), \n       .handshake_pipe    (handshake_pipe),\n       .payload_pipe      (payload_pipe)  \n      );\n    \n  // Destination-side submodule\n    \n    axi_register_slice_v2_1_22_auto_dest #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_dest\n      (\n       .ACLK           (ACLK),    \n       .m_aclear       (m_aclear),\n       .m_areset_resp2 (m_areset_resp2),  \n       .M_READY        (M_READY), \n       .M_VALID        (M_VALID),  \n       .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n       .handshake_pipe  (handshake_pipe),\n       .ready_pipe      (ready_pipe),  \n       .payload_pipe    (payload_pipe)  \n      );\n    \nendmodule  // auto_slr\n\nmodule axi_register_slice_v2_1_22_auto_src #\n  (\n   parameter integer C_DATA_WIDTH = 32\n  )\n  (\n   input  wire ACLK,\n   input  wire s_aclear,\n   input  wire s_areset_resp2,\n   input  wire S_VALID,\n   input  wire ready_pipe,\n   output wire S_READY,\n   output wire handshake_pipe,\n   output wire  [C_DATA_WIDTH-1:0] payload_pipe,\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA\n   );\n    \n   (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  [C_DATA_WIDTH-1:0] payload_pipe_r;\n    (* keep=\"true\" *) reg [2:0] s_aresetn_resp4 = 3'b000;\n    wire s_aresetn_resp3;\n    wire s_aresetn_d;\n    wire s_aresetn_q;\n    wire s_handshake_d;\n    wire s_ready_i;\n    \n    assign S_READY = s_ready_i & s_aresetn_q;\n    assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;\n    assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;\n    assign payload_pipe = payload_pipe_r;\n    \n    always @(posedge ACLK or posedge s_aclear) begin\n      if (s_aclear) begin\n        s_aresetn_resp4 <= 3'b000;\n      end else begin\n        s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      payload_pipe_r <= S_PAYLOAD_DATA;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) s_aresetn_resp3_inst (\n        .Q   (s_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~s_areset_resp2)\n     );\n    \n    // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (s_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_aresetn_d)\n     );\n    \n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (handshake_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_handshake_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (s_ready_i),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (ready_pipe)\n     );\n    \nendmodule  // auto_src\n\nmodule axi_register_slice_v2_1_22_auto_dest #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   input  wire ACLK,\n   input  wire m_aclear,\n   input  wire m_areset_resp2,\n   input  wire M_READY,\n   input  wire handshake_pipe,\n   output wire ready_pipe,\n   output wire M_VALID,\n   input  wire [C_DATA_WIDTH-1:0] payload_pipe,\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n   );\n    \n    (* keep=\"true\" *) reg [2:0] m_aresetn_resp4 = 3'b000;\n    wire m_aresetn_resp3;\n    wire m_aresetn_d;\n    wire m_aresetn_q;\n    wire m_valid_i;\n    wire pop;\n    wire m_ready_d;\n    wire m_handshake_q;\n    reg  [C_DATA_WIDTH-1:0] m_payload_q;\n    \n    assign M_VALID = m_valid_i;\n    assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;\n    assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;\n    assign pop     = M_READY & m_valid_i;\n    \n    always @(posedge ACLK or posedge m_aclear) begin\n      if (m_aclear) begin\n        m_aresetn_resp4 <= 3'b000;\n      end else begin\n        m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      m_payload_q <= payload_pipe;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) m_aresetn_resp3_inst (\n        .Q   (m_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~m_areset_resp2)\n     );\n    \n    // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (m_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_aresetn_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (m_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (handshake_pipe)\n     );\n    \n    (* autopipeline_group=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (ready_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_ready_d)\n     );\n    \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  (5)  \n      )\n      srl_fifo\n      (\n       .aclk    (ACLK),    \n       .areset  (~m_aresetn_q),\n       .aclear  (m_aclear),  \n       .s_mesg  (m_payload_q),  \n       .s_valid (m_handshake_q), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      );\n    \nendmodule  // auto_dest\n\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      reg s_valid_d;\n      reg s_ready_d = 1'b0;\n      reg s_ready_reg = 1'b0;\n      reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_22_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_RESP_MIDDLE2_LATENCY = C_PIPELINES_SLAVE + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_22_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      .ACLK           (ACLK),\n      .ARESETN         (ARESETN),\n      .S_PAYLOAD_DATA (S_PAYLOAD_DATA),\n      .S_VALID        (S_VALID),\n      .S_READY        (S_READY),\n      .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n      .M_VALID        (M_VALID),\n      .M_READY        (M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_reset;\n    wire src_ready;\n    wire dummy_reset;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  ( C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( dummy_reset   ) ,\n        .laguna_s_reset_in  ( src_reset   ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset   ) ,\n        .laguna_m_reset_in  ( src_reset  ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset2   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n      \n  end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] mid_payload;\n    wire mid_handshake;\n    wire mid_ready;\n    wire mid_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n    wire dummy_reset3;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( mid_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( mid_reset    ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset3   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset3   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out (  dummy_reset2  ) ,\n        .laguna_m_reset_in  ( mid_reset   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE2_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( mid_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2   ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset3   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset3    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n   \n  generate\n\n  (* keep=\"true\" *) reg s_reset_dd = 1'b0;\n  (* keep=\"true\" *) reg m_reset_dd = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n  \n  assign laguna_s_reset_out = laguna_s_reset_out_i;\n  assign laguna_m_reset_out = laguna_m_reset_out_i;\n  \n  always @(posedge ACLK) begin\n    laguna_s_reset_in_d <= laguna_s_reset_in;\n    laguna_m_reset_in_d <= laguna_m_reset_in;\n    s_reset_dd <= laguna_s_reset_in_d;\n    m_reset_dd <= laguna_m_reset_in_d;\n    laguna_s_reset_out_i <= C_PIPELINES==0 ? laguna_m_reset_in_d : m_reset_dd;\n    laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;\n  end\n  \n  wire ACLEAR;\n  assign ACLEAR = ~ARESETN;\n  \n  if (1) begin : common\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire laguna_s_handshake_q;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, laguna_m_ready_d}; \n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else if (p==C_PIPELINES+1) begin\n          laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n\n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = handshake_i[C_PIPELINES];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_m_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* keep=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_22_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_m_reset_out = laguna_m_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_m_reset_in_d <= laguna_m_reset_in;\n      aresetn_d <= C_CHANNEL==P_FORWARD ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? areset_dly[15]  : laguna_m_reset_in_d;\n      laguna_m_reset_out_i <= areset_d;  // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n  \n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* keep=\"true\" *)  reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      ready_d <= {ready_d, laguna_m_ready_d}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid_q;\n      assign payload_valid_d = (p==0) ? (S_VALID & s_ready_i) : handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==C_PIPELINES) begin\n          laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else if (p==0) begin\n          payload_data <= S_PAYLOAD_DATA;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n      \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_s_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* keep=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_s_reset_out = laguna_s_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_s_reset_in_d <= laguna_s_reset_in;\n      aresetn_d <= C_CHANNEL==P_RESPONSE ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? laguna_s_reset_in_d : areset_dly[15];\n      laguna_s_reset_out_i <= areset_d;  // For forward channels, reflect laguna_s_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n\n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    wire laguna_s_handshake_q;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      laguna_s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n        \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n        \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)  \n      )\n      srl_fifo_0\n      (\n       .aclk    (ACLK),    \n       .areset  (areset_d),  \n       .aclear  (ACLEAR),\n       .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n       .s_valid (push), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      ); \n  \n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  reg areset_d = 1'b0;\n  reg [3:0] areset_dly = 4'b0;\n  always @(posedge ACLK) begin\n    areset_dly <= {4{~ARESETN}} | (areset_dly<<1);\n    areset_d <= areset_dly[3];\n  end\n  \n  if (1) begin : common\n    reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID & s_ready_i;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* keep=\"true\" *)  reg payload_valid = 1'b0;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          payload_data <= S_PAYLOAD_DATA;\n          payload_valid <= S_VALID & s_ready_i & ~areset_d;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n          payload_valid <= handshake_i[((p>0)?(p-1):0)];\n        end\n      end\n    end\n    \n    if (C_PIPELINES==0) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),\n         .aclear  (1'b0),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire                        aclear,  // Async clear\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    wire [1:0] state;  // State vector register\n    reg  [1:0] next;           // Next state value\n    wire [1:0] next_qual;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    reg  m_valid_d;\n    wire m_valid_q;\n    \n    assign m_valid = m_valid_q;\n    assign next_qual = areset ? K_EMPTY : next;\n    assign m_mesg  = mesg_reg;\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_mvalid_inst (\n        .Q   (m_valid_q),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (m_valid_d)\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state0_inst (\n        .Q   (state[0]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[0])\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state1_inst (\n        .Q   (state[1]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[1])\n     );\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      m_valid_d = m_valid_q & ~areset;\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid & ~areset) begin\n            next = K_HAS1;\n            m_valid_d = 1'b0;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              m_valid_d = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n              m_valid_d = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          m_valid_d = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      (* keep_hierarchy = \"yes\" *) axi_register_slice_v2_1_22_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule  // axic_reg_srl_fifo\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   //   16 -> Auto-pipelining\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_RESERVE_MODE = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n  \n  if (C_RESERVE_MODE==1) begin : gen_reserve_si\n  \n    axi_register_slice_v2_1_22_test_slave #(\n      .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n      .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n      .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n      .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n      .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n      .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n      .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n      .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n      .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .s_axi_awaddr(s_axi_awaddr),\n      .s_axi_awprot(s_axi_awprot),\n      .s_axi_awvalid(s_axi_awvalid),\n      .s_axi_awready(s_axi_awready),\n      .s_axi_awsize(s_axi_awsize),\n      .s_axi_awburst(s_axi_awburst),\n      .s_axi_awcache(s_axi_awcache),\n      .s_axi_awlen(s_axi_awlen),\n      .s_axi_awlock(s_axi_awlock),\n      .s_axi_awqos(s_axi_awqos),\n      .s_axi_awregion(s_axi_awregion),\n      .s_axi_awid(s_axi_awid),\n      .s_axi_awuser(s_axi_awuser),\n      .s_axi_wdata(s_axi_wdata),\n      .s_axi_wstrb(s_axi_wstrb),\n      .s_axi_wvalid(s_axi_wvalid),\n      .s_axi_wready(s_axi_wready),\n      .s_axi_wlast(s_axi_wlast),\n      .s_axi_wid(s_axi_wid),\n      .s_axi_wuser(s_axi_wuser),\n      .s_axi_bresp(s_axi_bresp),\n      .s_axi_bvalid(s_axi_bvalid),\n      .s_axi_bready(s_axi_bready),\n      .s_axi_buser(s_axi_buser),\n      .s_axi_bid(s_axi_bid),\n      .s_axi_araddr(s_axi_araddr),\n      .s_axi_arprot(s_axi_arprot),\n      .s_axi_arvalid(s_axi_arvalid),\n      .s_axi_arready(s_axi_arready),\n      .s_axi_arsize(s_axi_arsize),\n      .s_axi_arburst(s_axi_arburst),\n      .s_axi_arcache(s_axi_arcache),\n      .s_axi_arlock(s_axi_arlock),\n      .s_axi_arlen(s_axi_arlen),\n      .s_axi_arqos(s_axi_arqos),\n      .s_axi_arregion(s_axi_arregion),\n      .s_axi_aruser(s_axi_aruser),\n      .s_axi_arid(s_axi_arid),\n      .s_axi_rdata(s_axi_rdata),\n      .s_axi_rresp(s_axi_rresp),\n      .s_axi_rvalid(s_axi_rvalid),\n      .s_axi_rready(s_axi_rready),\n      .s_axi_rlast(s_axi_rlast),\n      .s_axi_ruser(s_axi_ruser),\n      .s_axi_rid(s_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign m_axi_awid     = 0;\n     assign m_axi_awaddr   = 0;\n     assign m_axi_awlen    = 0;\n     assign m_axi_awsize   = 0;\n     assign m_axi_awburst  = 0;\n     assign m_axi_awlock   = 0;\n     assign m_axi_awcache  = 0;\n     assign m_axi_awprot   = 0;\n     assign m_axi_awregion = 0;\n     assign m_axi_awqos    = 0;\n     assign m_axi_awuser   = 0;\n     assign m_axi_awvalid  = 0;\n     assign m_axi_wid      = 0;\n     assign m_axi_wdata    = 0;\n     assign m_axi_wstrb    = 0;\n     assign m_axi_wlast    = 0;\n     assign m_axi_wuser    = 0;\n     assign m_axi_wvalid   = 0;\n     assign m_axi_bready   = 0;\n     assign m_axi_arid     = 0;\n     assign m_axi_araddr   = 0;\n     assign m_axi_arlen    = 0;\n     assign m_axi_arsize   = 0;\n     assign m_axi_arburst  = 0;\n     assign m_axi_arlock   = 0;\n     assign m_axi_arcache  = 0;\n     assign m_axi_arprot   = 0;\n     assign m_axi_arregion = 0;\n     assign m_axi_arqos    = 0;\n     assign m_axi_aruser   = 0;\n     assign m_axi_arvalid  = 0;\n     assign m_axi_rready   = 0;\n      \n  end else if (C_RESERVE_MODE==2) begin : gen_reserve_mi\n    \n    axi_register_slice_v2_1_22_test_master #(\n    .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n    .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .m_axi_awaddr(m_axi_awaddr),\n      .m_axi_awprot(m_axi_awprot),\n      .m_axi_awvalid(m_axi_awvalid),\n      .m_axi_awready(m_axi_awready),\n      .m_axi_awsize(m_axi_awsize),\n      .m_axi_awburst(m_axi_awburst),\n      .m_axi_awcache(m_axi_awcache),\n      .m_axi_awlen(m_axi_awlen),\n      .m_axi_awlock(m_axi_awlock),\n      .m_axi_awqos(m_axi_awqos),\n      .m_axi_awid(m_axi_awid),\n      .m_axi_awuser(m_axi_awuser),\n      .m_axi_wid(m_axi_wid),\n      .m_axi_wdata(m_axi_wdata),\n      .m_axi_wstrb(m_axi_wstrb),\n      .m_axi_wvalid(m_axi_wvalid),\n      .m_axi_wready(m_axi_wready),\n      .m_axi_wlast(m_axi_wlast),\n      .m_axi_wuser(m_axi_wuser),\n      .m_axi_bresp(m_axi_bresp),\n      .m_axi_bvalid(m_axi_bvalid),\n      .m_axi_bready(m_axi_bready),\n      .m_axi_buser(m_axi_buser),\n      .m_axi_bid(m_axi_bid),\n      .m_axi_araddr(m_axi_araddr),\n      .m_axi_arprot(m_axi_arprot),\n      .m_axi_arvalid(m_axi_arvalid),\n      .m_axi_arready(m_axi_arready),\n      .m_axi_arsize(m_axi_arsize),\n      .m_axi_arburst(m_axi_arburst),\n      .m_axi_arcache(m_axi_arcache),\n      .m_axi_arlen(m_axi_arlen),\n      .m_axi_arlock(m_axi_arlock),\n      .m_axi_arqos(m_axi_arqos),\n      .m_axi_arid(m_axi_arid),\n      .m_axi_aruser(m_axi_aruser),\n      .m_axi_rdata(m_axi_rdata),\n      .m_axi_rresp(m_axi_rresp),\n      .m_axi_rvalid(m_axi_rvalid),\n      .m_axi_rready(m_axi_rready),\n      .m_axi_rlast(m_axi_rlast),\n      .m_axi_ruser(m_axi_ruser),\n      .m_axi_rid(m_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign s_axi_awready = 0;\n     assign s_axi_wready  = 0;\n     assign s_axi_bid     = 0;\n     assign s_axi_bresp   = 0;\n     assign s_axi_buser   = 0;\n     assign s_axi_bvalid  = 0;\n     assign s_axi_arready = 0;\n     assign s_axi_rid     = 0;\n     assign s_axi_rdata   = 0;\n     assign s_axi_rresp   = 0;\n     assign s_axi_rlast   = 0;\n     assign s_axi_ruser   = 0;\n     assign s_axi_rvalid  = 0;\n\n  end else begin : gen_reg_slice  // Any normal reg-slice mode\n\n    axi_infrastructure_v1_1_0_axi2vector #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    axi2vector_0 ( \n      .s_axi_awid      ( s_axi_awid      ) ,\n      .s_axi_awaddr    ( s_axi_awaddr    ) ,\n      .s_axi_awlen     ( s_axi_awlen     ) ,\n      .s_axi_awsize    ( s_axi_awsize    ) ,\n      .s_axi_awburst   ( s_axi_awburst   ) ,\n      .s_axi_awlock    ( s_axi_awlock    ) ,\n      .s_axi_awcache   ( s_axi_awcache   ) ,\n      .s_axi_awprot    ( s_axi_awprot    ) ,\n      .s_axi_awqos     ( s_axi_awqos     ) ,\n      .s_axi_awuser    ( s_axi_awuser    ) ,\n      .s_axi_awregion  ( s_axi_awregion  ) ,\n      .s_axi_wid       ( s_axi_wid       ) ,\n      .s_axi_wdata     ( s_axi_wdata     ) ,\n      .s_axi_wstrb     ( s_axi_wstrb     ) ,\n      .s_axi_wlast     ( s_axi_wlast     ) ,\n      .s_axi_wuser     ( s_axi_wuser     ) ,\n      .s_axi_bid       ( s_axi_bid       ) ,\n      .s_axi_bresp     ( s_axi_bresp     ) ,\n      .s_axi_buser     ( s_axi_buser     ) ,\n      .s_axi_arid      ( s_axi_arid      ) ,\n      .s_axi_araddr    ( s_axi_araddr    ) ,\n      .s_axi_arlen     ( s_axi_arlen     ) ,\n      .s_axi_arsize    ( s_axi_arsize    ) ,\n      .s_axi_arburst   ( s_axi_arburst   ) ,\n      .s_axi_arlock    ( s_axi_arlock    ) ,\n      .s_axi_arcache   ( s_axi_arcache   ) ,\n      .s_axi_arprot    ( s_axi_arprot    ) ,\n      .s_axi_arqos     ( s_axi_arqos     ) ,\n      .s_axi_aruser    ( s_axi_aruser    ) ,\n      .s_axi_arregion  ( s_axi_arregion  ) ,\n      .s_axi_rid       ( s_axi_rid       ) ,\n      .s_axi_rdata     ( s_axi_rdata     ) ,\n      .s_axi_rresp     ( s_axi_rresp     ) ,\n      .s_axi_rlast     ( s_axi_rlast     ) ,\n      .s_axi_ruser     ( s_axi_ruser     ) ,\n      .s_awpayload ( s_awpayload ) ,\n      .s_wpayload  ( s_wpayload  ) ,\n      .s_bpayload  ( s_bpayload  ) ,\n      .s_arpayload ( s_arpayload ) ,\n      .s_rpayload  ( s_rpayload  ) \n    );\n    \n    axi_infrastructure_v1_1_0_vector2axi #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    vector2axi_0 ( \n      .m_awpayload    ( m_awpayload    ) ,\n      .m_wpayload     ( m_wpayload     ) ,\n      .m_bpayload     ( m_bpayload     ) ,\n      .m_arpayload    ( m_arpayload    ) ,\n      .m_rpayload     ( m_rpayload     ) ,\n      .m_axi_awid     ( m_axi_awid     ) ,\n      .m_axi_awaddr   ( m_axi_awaddr   ) ,\n      .m_axi_awlen    ( m_axi_awlen    ) ,\n      .m_axi_awsize   ( m_axi_awsize   ) ,\n      .m_axi_awburst  ( m_axi_awburst  ) ,\n      .m_axi_awlock   ( m_axi_awlock   ) ,\n      .m_axi_awcache  ( m_axi_awcache  ) ,\n      .m_axi_awprot   ( m_axi_awprot   ) ,\n      .m_axi_awqos    ( m_axi_awqos    ) ,\n      .m_axi_awuser   ( m_axi_awuser   ) ,\n      .m_axi_awregion ( m_axi_awregion ) ,\n      .m_axi_wid      ( m_axi_wid      ) ,\n      .m_axi_wdata    ( m_axi_wdata    ) ,\n      .m_axi_wstrb    ( m_axi_wstrb    ) ,\n      .m_axi_wlast    ( m_axi_wlast    ) ,\n      .m_axi_wuser    ( m_axi_wuser    ) ,\n      .m_axi_bid      ( m_axi_bid      ) ,\n      .m_axi_bresp    ( m_axi_bresp    ) ,\n      .m_axi_buser    ( m_axi_buser    ) ,\n      .m_axi_arid     ( m_axi_arid     ) ,\n      .m_axi_araddr   ( m_axi_araddr   ) ,\n      .m_axi_arlen    ( m_axi_arlen    ) ,\n      .m_axi_arsize   ( m_axi_arsize   ) ,\n      .m_axi_arburst  ( m_axi_arburst  ) ,\n      .m_axi_arlock   ( m_axi_arlock   ) ,\n      .m_axi_arcache  ( m_axi_arcache  ) ,\n      .m_axi_arprot   ( m_axi_arprot   ) ,\n      .m_axi_arqos    ( m_axi_arqos    ) ,\n      .m_axi_aruser   ( m_axi_aruser   ) ,\n      .m_axi_arregion ( m_axi_arregion ) ,\n      .m_axi_rid      ( m_axi_rid      ) ,\n      .m_axi_rdata    ( m_axi_rdata    ) ,\n      .m_axi_rresp    ( m_axi_rresp    ) ,\n      .m_axi_rlast    ( m_axi_rlast    ) ,\n      .m_axi_ruser    ( m_axi_ruser    ) \n    );\n    \n  end  // Reserve SI/MI branch\n\n  if ((C_REG_CONFIG_AW <= 9) && (C_RESERVE_MODE==0)) begin : aw\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 15) && (C_RESERVE_MODE==0)) begin : aw15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 16) && (C_RESERVE_MODE==0)) begin : aw16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) \n    )\n    aw_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if ((C_REG_CONFIG_W <= 9) && (C_RESERVE_MODE==0)) begin : w\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 15) && (C_RESERVE_MODE==0)) begin : w15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 16) && (C_RESERVE_MODE==0)) begin : w16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) \n    )\n    w_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if ((C_REG_CONFIG_B <= 9) && (C_RESERVE_MODE==0)) begin : b\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if ((C_REG_CONFIG_B == 15) && (C_RESERVE_MODE==0)) begin : b15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if ((C_REG_CONFIG_B == 16) && (C_RESERVE_MODE==0)) begin : b16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) \n    )\n    b_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if ((C_REG_CONFIG_AR <= 9) && (C_RESERVE_MODE==0)) begin : ar\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 15) && (C_RESERVE_MODE==0)) begin : ar15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 16) && (C_RESERVE_MODE==0)) begin : ar16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) \n    )\n    ar_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if ((C_REG_CONFIG_R <= 9) && (C_RESERVE_MODE==0)) begin : r\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 15) && (C_RESERVE_MODE==0)) begin : r15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 16) && (C_RESERVE_MODE==0)) begin : r16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) \n    )\n    r_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 4844}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized AND with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_carry_and #\n  (\n   parameter         C_FAMILY                         = \"virtex6\"\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   )\n  (\n   input  wire        CIN,\n   input  wire        S,\n   output wire        COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n\n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n      assign COUT = CIN & S;\n      \n    end else begin : USE_FPGA\n      MUXCY and_inst \n      (\n       .O (COUT), \n       .CI (CIN), \n       .DI (1'b0), \n       .S (S)\n      ); \n      \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized AND with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_carry_latch_and #\n  (\n   parameter          C_FAMILY                         = \"virtex6\"\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   )\n  (\n   input  wire        CIN,\n   input  wire        I,\n   output wire        O\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n\n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n      assign O = CIN & ~I;\n      \n    end else begin : USE_FPGA\n      wire I_n;\n      \n      assign I_n = ~I;\n    \n      AND2B1L and2b1l_inst \n        (\n         .O(O),\n         .DI(CIN),\n         .SRI(I_n)\n        );\n      \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized OR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_carry_latch_or #\n  (\n   parameter          C_FAMILY                         = \"virtex6\"\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   )\n  (\n   input  wire        CIN,\n   input  wire        I,\n   output wire        O\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n      assign O = CIN | I;\n      \n    end else begin : USE_FPGA\n      OR2L or2l_inst1\n        (\n         .O(O),\n         .DI(CIN),\n         .SRI(I)\n        );\n      \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized OR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_carry_or #\n  (\n   parameter         C_FAMILY                         = \"virtex6\"\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   )\n  (\n   input  wire        CIN,\n   input  wire        S,\n   output wire        COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n      assign COUT = CIN | S;\n      \n    end else begin : USE_FPGA\n      wire S_n;\n      \n      assign S_n = ~S;\n    \n      MUXCY and_inst \n      (\n       .O (COUT), \n       .CI (CIN), \n       .DI (1'b1), \n       .S (S_n)\n      ); \n      \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_carry #\n  (\n   parameter         C_FAMILY                         = \"virtex6\"\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   )\n  (\n   input  wire        CIN,\n   input  wire        S,\n   input  wire        DI,\n   output wire        COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n      assign COUT = (CIN & S) | (DI & ~S);\n      \n    end else begin : USE_FPGA\n    \n      MUXCY and_inst \n      (\n       .O (COUT), \n       .CI (CIN), \n       .DI (DI), \n       .S (S)\n      ); \n      \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized 16/32 word deep FIFO.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_command_fifo #\n  (\n   parameter         C_FAMILY                        = \"virtex6\",\n   parameter integer C_ENABLE_S_VALID_CARRY          = 0,\n   parameter integer C_ENABLE_REGISTERED_OUTPUT      = 0,\n   parameter integer C_FIFO_DEPTH_LOG                = 5,      // FIFO depth = 2**C_FIFO_DEPTH_LOG\n                                                               // Range = [4:5].\n   parameter integer C_FIFO_WIDTH                    = 64      // Width of payload [1:512]\n   )\n  (\n   // Global inputs\n   input  wire                        ACLK,    // Clock\n   input  wire                        ARESET,  // Reset\n   // Information\n   output wire                        EMPTY,   // FIFO empty (all stages)\n   // Slave  Port\n   input  wire [C_FIFO_WIDTH-1:0]     S_MESG,  // Payload (may be any set of channel signals)\n   input  wire                        S_VALID, // FIFO push\n   output wire                        S_READY, // FIFO not full\n   // Master  Port\n   output wire [C_FIFO_WIDTH-1:0]     M_MESG,  // Payload\n   output wire                        M_VALID, // FIFO not empty\n   input  wire                        M_READY  // FIFO pop\n   );\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for data vector.\n  genvar addr_cnt;\n  genvar bit_cnt;\n  integer index;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIFO_DEPTH_LOG-1:0] addr;\n  wire                        buffer_Full;\n  wire                        buffer_Empty;\n  \n  wire                        next_Data_Exists;\n  reg                         data_Exists_I = 1'b0;\n  \n  wire                        valid_Write;\n  wire                        new_write;\n  \n  wire [C_FIFO_DEPTH_LOG-1:0] hsum_A;\n  wire [C_FIFO_DEPTH_LOG-1:0] sum_A;\n  wire [C_FIFO_DEPTH_LOG-1:0] addr_cy;\n\n  wire                        buffer_full_early;\n  \n  wire [C_FIFO_WIDTH-1:0]     M_MESG_I;   // Payload\n  wire                        M_VALID_I;  // FIFO not empty\n  wire                        M_READY_I;  // FIFO pop\n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Create Flags \n  /////////////////////////////////////////////////////////////////////////////\n  \n  assign buffer_full_early  = ( (addr == {{C_FIFO_DEPTH_LOG-1{1'b1}}, 1'b0}) & valid_Write & ~M_READY_I ) |\n                              ( buffer_Full & ~M_READY_I );\n\n  assign S_READY            = ~buffer_Full;\n\n  assign buffer_Empty       = (addr == {C_FIFO_DEPTH_LOG{1'b0}});\n\n  assign next_Data_Exists   = (data_Exists_I & ~buffer_Empty) |\n                              (buffer_Empty & S_VALID) |\n                              (data_Exists_I & ~(M_READY_I & data_Exists_I));\n\n  always @ (posedge ACLK) begin\n    if (ARESET) begin\n      data_Exists_I <= 1'b0;\n    end else begin\n      data_Exists_I <= next_Data_Exists;\n    end\n  end\n\n  assign M_VALID_I = data_Exists_I;\n  \n  // Select RTL or FPGA optimized instatiations for critical parts.\n  generate\n    if ( C_FAMILY == \"rtl\" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE\n      reg                         buffer_Full_q = 1'b0;\n      \n      assign valid_Write = S_VALID & ~buffer_Full;\n      \n      assign new_write = (S_VALID | ~buffer_Empty);\n     \n      assign addr_cy[0] = valid_Write;\n      \n      always @ (posedge ACLK) begin\n        if (ARESET) begin\n          buffer_Full_q <= 1'b0;\n        end else if ( data_Exists_I ) begin\n          buffer_Full_q <= buffer_full_early;\n        end\n      end\n      assign buffer_Full = buffer_Full_q;\n      \n    end else begin : USE_FPGA_VALID_WRITE\n      wire s_valid_dummy1;\n      wire s_valid_dummy2;\n      wire sel_s_valid;\n      wire sel_new_write;\n      wire valid_Write_dummy1;\n      wire valid_Write_dummy2;\n      \n      assign sel_s_valid = ~buffer_Full;\n      \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) s_valid_dummy_inst1\n        (\n         .CIN(S_VALID),\n         .S(1'b1),\n         .COUT(s_valid_dummy1)\n         );\n      \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) s_valid_dummy_inst2\n        (\n         .CIN(s_valid_dummy1),\n         .S(1'b1),\n         .COUT(s_valid_dummy2)\n         );\n      \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) valid_write_inst\n        (\n         .CIN(s_valid_dummy2),\n         .S(sel_s_valid),\n         .COUT(valid_Write)\n         );\n      \n      assign sel_new_write = ~buffer_Empty;\n       \n      generic_baseblocks_v2_1_0_carry_latch_or #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) new_write_inst\n        (\n         .CIN(valid_Write),\n         .I(sel_new_write),\n         .O(new_write)\n         );\n         \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) valid_write_dummy_inst1\n        (\n         .CIN(valid_Write),\n         .S(1'b1),\n         .COUT(valid_Write_dummy1)\n         );\n      \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) valid_write_dummy_inst2\n        (\n         .CIN(valid_Write_dummy1),\n         .S(1'b1),\n         .COUT(valid_Write_dummy2)\n         );\n      \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) valid_write_dummy_inst3\n        (\n         .CIN(valid_Write_dummy2),\n         .S(1'b1),\n         .COUT(addr_cy[0])\n         );\n      \n      FDRE #(\n       .INIT(1'b0)              // Initial value of register (1'b0 or 1'b1)\n       ) FDRE_I1 (\n       .Q(buffer_Full),         // Data output\n       .C(ACLK),                // Clock input\n       .CE(data_Exists_I),      // Clock enable input\n       .R(ARESET),              // Synchronous reset input\n       .D(buffer_full_early)    // Data input\n       );\n       \n    end\n  endgenerate\n      \n    \n  /////////////////////////////////////////////////////////////////////////////\n  // Create address pointer\n  /////////////////////////////////////////////////////////////////////////////\n\n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_ADDR\n    \n      reg  [C_FIFO_DEPTH_LOG-1:0] addr_q = {C_FIFO_DEPTH_LOG{1'b0}};\n      \n      always @ (posedge ACLK) begin\n        if (ARESET) begin\n          addr_q <= {C_FIFO_DEPTH_LOG{1'b0}};\n        end else if ( data_Exists_I ) begin\n          if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin\n            addr_q <= addr_q + 1'b1;\n          end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin\n            addr_q <= addr_q - 1'b1;\n          end\n          else begin\n            addr_q <= addr_q;\n          end\n        end\n        else begin\n          addr_q <= addr_q;\n        end\n      end\n      \n      assign addr = addr_q;\n      \n    end else begin : USE_FPGA_ADDR\n      for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN\n        assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write;\n        \n        // Don't need the last muxcy, addr_cy(last) is not used anywhere\n        if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY\n          MUXCY MUXCY_inst (\n           .DI(addr[addr_cnt]),\n           .CI(addr_cy[addr_cnt]),\n           .S(hsum_A[addr_cnt]),\n           .O(addr_cy[addr_cnt+1])\n           );\n           \n        end\n        else begin : NO_MUXCY\n        end\n        \n        XORCY XORCY_inst (\n         .LI(hsum_A[addr_cnt]),\n         .CI(addr_cy[addr_cnt]),\n         .O(sum_A[addr_cnt])\n         );\n        \n        FDRE #(\n         .INIT(1'b0)             // Initial value of register (1'b0 or 1'b1)\n         ) FDRE_inst (\n         .Q(addr[addr_cnt]),     // Data output\n         .C(ACLK),               // Clock input\n         .CE(data_Exists_I),     // Clock enable input\n         .R(ARESET),             // Synchronous reset input\n         .D(sum_A[addr_cnt])     // Data input\n         );\n        \n      end // end for bit_cnt\n    end // C_FAMILY\n  endgenerate\n      \n      \n  /////////////////////////////////////////////////////////////////////////////\n  // Data storage\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_FIFO\n      reg  [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0];\n      \n      always @ (posedge ACLK) begin\n        if ( valid_Write ) begin\n          for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin\n            data_srl[index+1] <= data_srl[index];\n          end\n          data_srl[0]   <= S_MESG;\n        end\n      end\n      \n      assign M_MESG_I = data_srl[addr];\n      \n    end else begin : USE_FPGA_FIFO\n      for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN\n        \n        if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32\n            SRLC32E # (\n             .INIT(32'h00000000)    // Initial Value of Shift Register\n            ) SRLC32E_inst (\n             .Q(M_MESG_I[bit_cnt]), // SRL data output\n             .Q31(),                // SRL cascade output pin\n             .A(addr),              // 5-bit shift depth select input\n             .CE(valid_Write),      // Clock enable input\n             .CLK(ACLK),            // Clock input\n             .D(S_MESG[bit_cnt])    // SRL data input\n            );\n        end else begin : USE_16\n            SRLC16E # (\n             .INIT(32'h00000000)    // Initial Value of Shift Register\n            ) SRLC16E_inst (\n             .Q(M_MESG_I[bit_cnt]), // SRL data output\n             .Q15(),                // SRL cascade output pin\n             .A0(addr[0]),          // 4-bit shift depth select input 0\n             .A1(addr[1]),          // 4-bit shift depth select input 1\n             .A2(addr[2]),          // 4-bit shift depth select input 2\n             .A3(addr[3]),          // 4-bit shift depth select input 3\n             .CE(valid_Write),      // Clock enable input\n             .CLK(ACLK),            // Clock input\n             .D(S_MESG[bit_cnt])    // SRL data input\n            );\n        end // C_FIFO_DEPTH_LOG\n      \n      end // end for bit_cnt\n    end // C_FAMILY\n  endgenerate\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Pipeline stage\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT\n      \n      wire [C_FIFO_WIDTH-1:0]     M_MESG_FF;    // Payload\n      wire                        M_VALID_FF;   // FIFO not empty\n      \n      // Select RTL or FPGA optimized instatiations for critical parts.\n      if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_OUTPUT_PIPELINE\n      \n        reg  [C_FIFO_WIDTH-1:0]     M_MESG_Q;   // Payload\n        reg                         M_VALID_Q = 1'b0;  // FIFO not empty\n        \n        always @ (posedge ACLK) begin\n          if (ARESET) begin\n            M_MESG_Q    <= {C_FIFO_WIDTH{1'b0}};\n            M_VALID_Q   <= 1'b0;\n          end else begin\n            if ( M_READY_I ) begin\n              M_MESG_Q    <= M_MESG_I;\n              M_VALID_Q   <= M_VALID_I;\n            end\n          end\n        end\n      \n        assign M_MESG_FF     = M_MESG_Q;\n        assign M_VALID_FF    = M_VALID_Q;\n        \n      end else begin : USE_FPGA_OUTPUT_PIPELINE\n      \n        reg  [C_FIFO_WIDTH-1:0]     M_MESG_CMB;   // Payload\n        reg                         M_VALID_CMB;  // FIFO not empty\n        \n        always @ *\n        begin\n          if ( M_READY_I ) begin\n            M_MESG_CMB  <= M_MESG_I;\n            M_VALID_CMB <= M_VALID_I;\n          end else begin\n            M_MESG_CMB  <= M_MESG_FF;\n            M_VALID_CMB <= M_VALID_FF;\n          end\n        end\n        \n        for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN\n              \n          FDRE #(\n           .INIT(1'b0)                    // Initial value of register (1'b0 or 1'b1)\n           ) FDRE_inst (\n           .Q(M_MESG_FF[bit_cnt]),        // Data output\n           .C(ACLK),                      // Clock input\n           .CE(1'b1),                     // Clock enable input\n           .R(ARESET),                    // Synchronous reset input\n           .D(M_MESG_CMB[bit_cnt])        // Data input\n           );\n        end // end for bit_cnt\n            \n        FDRE #(\n         .INIT(1'b0)                    // Initial value of register (1'b0 or 1'b1)\n         ) FDRE_inst (\n         .Q(M_VALID_FF),                // Data output\n         .C(ACLK),                      // Clock input\n         .CE(1'b1),                     // Clock enable input\n         .R(ARESET),                    // Synchronous reset input\n         .D(M_VALID_CMB)                // Data input\n         );\n      \n      end\n      \n      assign EMPTY      = ~M_VALID_I & ~M_VALID_FF;\n      assign M_MESG     = M_MESG_FF;\n      assign M_VALID    = M_VALID_FF;\n      assign M_READY_I  = ( M_READY & M_VALID_FF ) | ~M_VALID_FF;\n      \n    end else begin : NO_FF_OUT\n      \n      assign EMPTY      = ~M_VALID_I;\n      assign M_MESG     = M_MESG_I;\n      assign M_VALID    = M_VALID_I;\n      assign M_READY_I  = M_READY;\n      \n    end\n  endgenerate\n\nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_mask_static #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter         C_VALUE                          = 4'b0,\n                       // Static value to compare against.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] M,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar lut_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 3;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] m_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign m_local        = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = C_VALUE;\n      assign m_local        = M;\n    end\n    \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == \n                              ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[lut_cnt+1]),\n       .CIN   (carry_local[lut_cnt]),\n       .S     (sel[lut_cnt])\n      ); \n      \n    end // end for lut_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_mask #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   input  wire [C_DATA_WIDTH-1:0] M,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar lut_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 2;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] m_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign m_local        = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n      assign m_local        = M;\n    end\n  \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == \n                              ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[lut_cnt+1]),\n       .CIN   (carry_local[lut_cnt]),\n       .S     (sel[lut_cnt])\n      ); \n      \n    end // end for lut_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_sel_mask_static #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter         C_VALUE                          = 4'b0,\n                       // Static value to compare against.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire                    S,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   input  wire [C_DATA_WIDTH-1:0] M,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar lut_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 1;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] m_local;\n  wire [C_FIX_DATA_WIDTH-1:0] v_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign m_local        = {M,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign v_local        = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n      assign m_local        = M;\n      assign v_local        = C_VALUE;\n    end\n    \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==\n                                ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |\n                            ( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==\n                                ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[lut_cnt+1]),\n       .CIN   (carry_local[lut_cnt]),\n       .S     (sel[lut_cnt])\n      ); \n      \n    end // end for lut_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_sel_mask #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire                    S,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   input  wire [C_DATA_WIDTH-1:0] M,\n   input  wire [C_DATA_WIDTH-1:0] V,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar lut_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 1;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] m_local;\n  wire [C_FIX_DATA_WIDTH-1:0] v_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign m_local        = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign v_local        = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n      assign m_local        = M;\n      assign v_local        = V;\n    end\n    \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==\n                                ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |\n                            ( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==\n                                ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[lut_cnt+1]),\n       .CIN   (carry_local[lut_cnt]),\n       .S     (sel[lut_cnt])\n      ); \n      \n    end // end for lut_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_sel_static #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter         C_VALUE                          = 4'b0,\n                       // Static value to compare against.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire                    S,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar bit_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 2;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] v_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign v_local        = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n      assign v_local        = C_VALUE;\n    end\n    \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                                v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |\n                            ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                                v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[bit_cnt+1]),\n       .CIN   (carry_local[bit_cnt]),\n       .S     (sel[bit_cnt])\n      ); \n      \n    end // end for bit_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_sel #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire                    S,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   input  wire [C_DATA_WIDTH-1:0] V,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar bit_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 1;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] v_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign v_local        = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n      assign v_local        = V;\n    end\n  \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                                v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |\n                            ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                                v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[bit_cnt+1]),\n       .CIN   (carry_local[bit_cnt]),\n       .S     (sel[bit_cnt])\n      ); \n      \n    end // end for bit_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_static #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter         C_VALUE                          = 4'b0,\n                       // Static value to compare against.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar bit_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 6;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = C_VALUE;\n    end\n    \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                              b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[bit_cnt+1]),\n       .CIN   (carry_local[bit_cnt]),\n       .S     (sel[bit_cnt])\n      ); \n      \n    end // end for bit_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar bit_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 3;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n    end\n  \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                              b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[bit_cnt+1]),\n       .CIN   (carry_local[bit_cnt]),\n       .S     (sel[bit_cnt])\n      ); \n      \n    end // end for bit_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized Mux using MUXF7/8.\n//  Any generic_baseblocks_v2_1_0_mux ratio.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   mux_enc\n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_mux_enc #\n  (\n   parameter         C_FAMILY                       = \"rtl\",\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_RATIO                        = 4,\n                       // Mux select ratio. Can be any binary value (>= 1)\n   parameter integer C_SEL_WIDTH                    = 2,\n                       // Log2-ceiling of C_RATIO (>= 1)\n   parameter integer C_DATA_WIDTH                   = 1\n                       // Data width for generic_baseblocks_v2_1_0_comparator (>= 1)\n   )\n  (\n   input  wire [C_SEL_WIDTH-1:0]                    S,\n   input  wire [C_RATIO*C_DATA_WIDTH-1:0]           A,\n   output wire [C_DATA_WIDTH-1:0]                   O,\n   input  wire                                      OE\n   );\n  \n  wire [C_DATA_WIDTH-1:0] o_i;\n  genvar bit_cnt;\n  \n  function [C_DATA_WIDTH-1:0] f_mux\n    (\n     input [C_SEL_WIDTH-1:0] s,\n     input [C_RATIO*C_DATA_WIDTH-1:0] a\n     );\n    integer i;\n    reg [C_RATIO*C_DATA_WIDTH-1:0] carry;\n    begin\n      carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];\n      for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc\n        carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] = \n          carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |\n          ({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);\n      end\n      f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)];\n    end\n  endfunction\n  \n  function [C_DATA_WIDTH-1:0] f_mux4\n    (\n     input [1:0] s,\n     input [4*C_DATA_WIDTH-1:0] a\n     );\n    integer i;\n    reg [4*C_DATA_WIDTH-1:0] carry;\n    begin\n      carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];\n      for (i=1;i<4;i=i+1) begin : gen_carrychain_enc\n        carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] = \n          carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |\n          ({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);\n      end\n      f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3];\n    end\n  endfunction\n  \n  assign O = o_i & {C_DATA_WIDTH{OE}};  // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic)\n  \n  generate\n    if ( C_RATIO < 2 ) begin : gen_bypass\n      assign o_i = A;\n    end else if ( C_FAMILY == \"rtl\" || C_RATIO < 5 ) begin : gen_rtl\n      assign o_i = f_mux(S, A);\n      \n    end else begin : gen_fpga\n      wire [C_DATA_WIDTH-1:0] l;\n      wire [C_DATA_WIDTH-1:0] h;\n      wire [C_DATA_WIDTH-1:0] ll;\n      wire [C_DATA_WIDTH-1:0] lh;\n      wire [C_DATA_WIDTH-1:0] hl;\n      wire [C_DATA_WIDTH-1:0] hh;\n      \n      case (C_RATIO)\n        1, 5, 9, 13: \n          assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        2, 6, 10, 14:\n          assign hh = S[0] ? \n            A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :\n            A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ;\n        3, 7, 11, 15:\n          assign hh = S[1] ? \n            A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :\n            (S[0] ? \n              A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] :\n              A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] );\n        4, 8, 12, 16:\n          assign hh = S[1] ? \n            (S[0] ? \n              A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :\n              A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) :\n            (S[0] ? \n              A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] :\n              A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] );\n        17:\n          assign hh = S[1] ? \n            (S[0] ? \n              A[15*C_DATA_WIDTH +: C_DATA_WIDTH] :\n              A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) :\n            (S[0] ? \n              A[13*C_DATA_WIDTH +: C_DATA_WIDTH] :\n              A[12*C_DATA_WIDTH +: C_DATA_WIDTH] );\n        default:\n          assign hh = 0; \n      endcase\n\n      case (C_RATIO)\n        5, 6, 7, 8: begin\n          assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);\n          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8\n            MUXF7 mux_s2_inst \n            (\n             .I0  (l[bit_cnt]),\n             .I1  (hh[bit_cnt]),\n             .S   (S[2]),\n             .O   (o_i[bit_cnt])\n            ); \n          end\n        end\n          \n        9, 10, 11, 12: begin\n          assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);\n          assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);\n          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12\n            MUXF7 muxf_s2_low_inst \n            (\n             .I0  (ll[bit_cnt]),\n             .I1  (lh[bit_cnt]),\n             .S   (S[2]),\n             .O   (l[bit_cnt])\n            ); \n            MUXF8 muxf_s3_inst \n            (\n             .I0  (l[bit_cnt]),\n             .I1  (hh[bit_cnt]),\n             .S   (S[3]),\n             .O   (o_i[bit_cnt])\n            ); \n          end\n        end\n          \n        13,14,15,16: begin\n          assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);\n          assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);\n          assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);\n          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16\n            MUXF7 muxf_s2_low_inst \n            (\n             .I0  (ll[bit_cnt]),\n             .I1  (lh[bit_cnt]),\n             .S   (S[2]),\n             .O   (l[bit_cnt])\n            ); \n            MUXF7 muxf_s2_hi_inst \n            (\n             .I0  (hl[bit_cnt]),\n             .I1  (hh[bit_cnt]),\n             .S   (S[2]),\n             .O   (h[bit_cnt])\n            );\n          \n            MUXF8 muxf_s3_inst \n            (\n             .I0  (l[bit_cnt]),\n             .I1  (h[bit_cnt]),\n             .S   (S[3]),\n             .O   (o_i[bit_cnt])\n            ); \n          end\n        end\n          \n        17: begin\n          assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);  // 5-input mux\n          assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);\n          assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);\n          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17\n            MUXF7 muxf_s2_low_inst \n            (\n             .I0  (ll[bit_cnt]),\n             .I1  (lh[bit_cnt]),\n             .S   (S[2]),\n             .O   (l[bit_cnt])\n            ); \n            MUXF7 muxf_s2_hi_inst \n            (\n             .I0  (hl[bit_cnt]),\n             .I1  (hh[bit_cnt]),\n             .S   (S[2]),\n             .O   (h[bit_cnt])\n            ); \n            MUXF8 muxf_s3_inst \n            (\n             .I0  (l[bit_cnt]),\n             .I1  (h[bit_cnt]),\n             .S   (S[3]),\n             .O   (o_i[bit_cnt])\n            ); \n          end\n        end\n          \n        default:  // If RATIO > 17, use RTL\n          assign o_i = f_mux(S, A);\n      endcase\n    end  // gen_fpga\n  endgenerate\nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized Mux from 2:1 upto 16:1.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_mux #\n  (\n   parameter         C_FAMILY                         = \"rtl\",\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_SEL_WIDTH                      = 4,\n                       // Data width for comparator.\n   parameter integer C_DATA_WIDTH                     = 2\n                       // Data width for comparator.\n   )\n  (\n   input  wire [C_SEL_WIDTH-1:0]                    S,\n   input  wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0]  A,\n   output wire [C_DATA_WIDTH-1:0]                   O\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar bit_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" || C_SEL_WIDTH < 3 ) begin : USE_RTL\n      assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH];\n      \n    end else begin : USE_FPGA\n      \n      wire [C_DATA_WIDTH-1:0] C;\n      wire [C_DATA_WIDTH-1:0] D;\n      \n      // Lower half recursively.\n      generic_baseblocks_v2_1_0_mux # \n      (\n       .C_FAMILY      (C_FAMILY),\n       .C_SEL_WIDTH   (C_SEL_WIDTH-1),\n       .C_DATA_WIDTH  (C_DATA_WIDTH)\n      ) mux_c_inst \n      (\n       .S   (S[C_SEL_WIDTH-2:0]),\n       .A   (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]),\n       .O   (C)\n      ); \n      \n      // Upper half recursively.\n      generic_baseblocks_v2_1_0_mux # \n      (\n       .C_FAMILY      (C_FAMILY),\n       .C_SEL_WIDTH   (C_SEL_WIDTH-1),\n       .C_DATA_WIDTH  (C_DATA_WIDTH)\n      ) mux_d_inst \n      (\n       .S   (S[C_SEL_WIDTH-2:0]),\n       .A   (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]),\n       .O   (D)\n      ); \n      \n      // Generate instantiated generic_baseblocks_v2_1_0_mux components as required.\n      for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM\n        if ( C_SEL_WIDTH == 4 ) begin : USE_F8\n        \n          MUXF8 muxf8_inst \n          (\n           .I0  (C[bit_cnt]),\n           .I1  (D[bit_cnt]),\n           .S   (S[C_SEL_WIDTH-1]),\n           .O   (O[bit_cnt])\n          ); \n          \n        end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7\n      \n          MUXF7 muxf7_inst \n          (\n           .I0  (C[bit_cnt]),\n           .I1  (D[bit_cnt]),\n           .S   (S[C_SEL_WIDTH-1]),\n           .O   (O[bit_cnt])\n          ); \n          \n        end // C_SEL_WIDTH\n      end // end for bit_cnt\n    \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: nto1_mux.v\n//\n// Description: N:1 MUX based on either binary-encoded or one-hot select input\n//   One-hot mode does not protect against multiple active SEL_ONEHOT inputs.\n//   Note: All port signals changed to all-upper-case (w.r.t. prior version).\n//\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_nto1_mux #\n  (\n   parameter integer C_RATIO         =  1,  // Range: >=1\n   parameter integer C_SEL_WIDTH     =  1,  // Range: >=1; recommended: ceil_log2(C_RATIO)\n   parameter integer C_DATAOUT_WIDTH =  1,  // Range: >=1\n   parameter integer C_ONEHOT        =  0   // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)\n   )\n  (\n   input  wire [C_RATIO-1:0]                 SEL_ONEHOT,  // One-hot generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=1)\n   input  wire [C_SEL_WIDTH-1:0]             SEL,         // Binary-encoded generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=0)\n   input  wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN,          // Data input array (num_selections x data_width)\n   output wire [C_DATAOUT_WIDTH-1:0]         OUT          // Data output vector\n   );\n\n  wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;\n  genvar i;\n  \n  generate\n    if (C_ONEHOT == 0) begin : gen_encoded\n      assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1'b1:1'b0}} & IN[C_DATAOUT_WIDTH-1:0];\n      for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc\n        assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] = \n               carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |\n               {C_DATAOUT_WIDTH{(SEL==i)?1'b1:1'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];\n      end\n    end else begin : gen_onehot\n      assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];\n      for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot\n        assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] = \n               carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |\n               {C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];\n      end\n    end\n  endgenerate\n  assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:\n                     C_DATAOUT_WIDTH*(C_RATIO-1)];\nendmodule\n\n`default_nettype wire\n\n\n", "num_lines": 2931}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: addr_arbiter_sasd.v\n//\n// Description: \n//   Hybrid priority + round-robin arbiter.\n//   Read & write requests combined (read preferred) at each slot\n//   Muxes AR and AW channel payload inputs based on arbitration results.\n//-----------------------------------------------------------------------------\n//\n// Structure:\n//    addr_arbiter_sasd\n//      mux_enc\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_addr_arbiter_sasd #\n  (\n   parameter         C_FAMILY                         = \"none\", \n   parameter integer C_NUM_S                = 1, \n   parameter integer C_NUM_S_LOG                = 1, \n   parameter integer C_AMESG_WIDTH                 = 1, \n   parameter         C_GRANT_ENC        = 0,\n   parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY             = {C_NUM_S{32'h00000000}}\n                       // Arbitration priority among each SI slot. \n                       // Higher values indicate higher priority.\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 'h0-'hF.\n   )\n  (\n   // Global Signals\n   input  wire                                      ACLK,\n   input  wire                                      ARESET,\n   // Slave Ports\n   input  wire [C_NUM_S*C_AMESG_WIDTH-1:0]  S_AWMESG,\n   input  wire [C_NUM_S*C_AMESG_WIDTH-1:0]  S_ARMESG,\n   input  wire [C_NUM_S-1:0]                S_AWVALID,\n   output wire [C_NUM_S-1:0]                S_AWREADY,\n   input  wire [C_NUM_S-1:0]                S_ARVALID,\n   output wire [C_NUM_S-1:0]                S_ARREADY,\n   // Master Ports\n   output wire [C_AMESG_WIDTH-1:0]          M_AMESG,\n   output wire [C_NUM_S_LOG-1:0]            M_GRANT_ENC,\n   output wire [C_NUM_S-1:0]                M_GRANT_HOT,\n   output wire                              M_GRANT_RNW,\n   output wire                              M_GRANT_ANY,\n   output wire                              M_AWVALID,\n   input  wire                              M_AWREADY,\n   output wire                              M_ARVALID,\n   input  wire                              M_ARREADY\n   );\n   \n  // Generates a mask for all input slots that are priority based\n  function [C_NUM_S-1:0] f_prio_mask\n    (\n      input integer null_arg\n    );\n    reg   [C_NUM_S-1:0]            mask;\n    integer                        i;    \n    begin\n      mask = 0;    \n      for (i=0; i < C_NUM_S; i=i+1) begin\n        mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0);\n      end \n      f_prio_mask = mask;\n    end   \n  endfunction\n  \n  // Convert 16-bit one-hot to 4-bit binary\n  function [3:0] f_hot2enc\n    (\n      input [15:0]  one_hot\n    );\n    begin\n      f_hot2enc[0] = |(one_hot & 16'b1010101010101010);\n      f_hot2enc[1] = |(one_hot & 16'b1100110011001100);\n      f_hot2enc[2] = |(one_hot & 16'b1111000011110000);\n      f_hot2enc[3] = |(one_hot & 16'b1111111100000000);\n    end\n  endfunction\n\n  localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0);\n\n  reg                     m_valid_i = 1'b0;\n  reg [C_NUM_S-1:0]       s_ready_i = 0;\n  reg [C_NUM_S-1:0]       s_awvalid_reg = 0;\n  reg [C_NUM_S-1:0]       s_arvalid_reg = 0;\n  wire [15:0]             s_avalid;\n  wire                    m_aready;\n  wire [C_NUM_S-1:0]      rnw;\n  reg                     grant_rnw;\n  reg [C_NUM_S_LOG-1:0]   m_grant_enc_i;\n  reg [C_NUM_S-1:0]       m_grant_hot_i; \n  reg [C_NUM_S-1:0]       last_rr_hot;\n  reg                     any_grant;\n  reg                     any_prio;\n  reg [C_NUM_S-1:0]       which_prio_hot;\n  reg [C_NUM_S_LOG-1:0]   which_prio_enc;          \n  reg [4:0]               current_highest;\n  reg [15:0]              next_prio_hot;\n  reg [C_NUM_S_LOG-1:0]   next_prio_enc;    \n  reg                     found_prio;\n  wire [C_NUM_S-1:0]      valid_rr;\n  reg [15:0]              next_rr_hot;\n  reg [C_NUM_S_LOG-1:0]   next_rr_enc;    \n  reg [C_NUM_S*C_NUM_S-1:0] carry_rr;\n  reg [C_NUM_S*C_NUM_S-1:0] mask_rr;\n  reg                     found_rr;\n  wire [C_NUM_S-1:0]      next_hot;\n  wire [C_NUM_S_LOG-1:0]  next_enc;    \n  integer                 i;\n  wire  [C_AMESG_WIDTH-1:0] amesg_mux;\n  reg   [C_AMESG_WIDTH-1:0] m_amesg_i;\n  wire [C_NUM_S*C_AMESG_WIDTH-1:0] s_amesg;\n  genvar                  gen_si;\n\n  always @(posedge ACLK) begin\n    if (ARESET) begin\n      s_awvalid_reg <= 0;\n      s_arvalid_reg <= 0;\n    end else if (|s_ready_i) begin\n      s_awvalid_reg <= 0;\n      s_arvalid_reg <= 0;\n    end else begin\n      s_arvalid_reg <= S_ARVALID & ~s_awvalid_reg;\n      s_awvalid_reg <= S_AWVALID & ~s_arvalid_reg & (~S_ARVALID | s_awvalid_reg);\n    end\n  end\n  \n  assign s_avalid = S_AWVALID | S_ARVALID;\n  assign M_AWVALID = m_valid_i & ~grant_rnw;\n  assign M_ARVALID = m_valid_i & grant_rnw;\n  assign S_AWREADY = s_ready_i & {C_NUM_S{~grant_rnw}};\n  assign S_ARREADY = s_ready_i & {C_NUM_S{grant_rnw}};\n  assign M_GRANT_ENC = C_GRANT_ENC ? m_grant_enc_i : 0;\n  assign M_GRANT_HOT = m_grant_hot_i;\n  assign M_GRANT_RNW = grant_rnw;\n  assign rnw = S_ARVALID & ~s_awvalid_reg;\n  assign M_AMESG = m_amesg_i;\n  assign m_aready = grant_rnw ? M_ARREADY : M_AWREADY;\n  \n  generate\n    for (gen_si=0; gen_si<C_NUM_S; gen_si=gen_si+1) begin : gen_mesg_mux\n      assign s_amesg[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] = rnw[gen_si] ? S_ARMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] : S_AWMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH];\n    end  // gen_mesg_mux\n         \n    if (C_NUM_S>1) begin : gen_arbiter\n    \n      /////////////////////////////////////////////////////////////////////////////\n      // Grant a new request when there is none still pending.\n      // If no qualified requests found, de-assert M_VALID.\n      /////////////////////////////////////////////////////////////////////////////\n      \n      assign M_GRANT_ANY = any_grant;\n      assign next_hot = found_prio ? next_prio_hot : next_rr_hot;\n      assign next_enc = found_prio ? next_prio_enc : next_rr_enc;\n      \n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          m_valid_i <= 0;\n          s_ready_i <= 0;\n          m_grant_hot_i <= 0;\n          m_grant_enc_i <= 0;\n          any_grant <= 1'b0;\n          last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};\n          grant_rnw <= 1'b0;\n        end else begin\n          s_ready_i <= 0;\n          if (m_valid_i) begin\n            // Stall 1 cycle after each master-side completion.\n            if (m_aready) begin  // Master-side completion\n              m_valid_i <= 1'b0;\n              m_grant_hot_i <= 0;\n              any_grant <= 1'b0;\n            end\n          end else if (any_grant) begin\n            m_valid_i <= 1'b1;\n            s_ready_i <= m_grant_hot_i;  // Assert S_AW/READY for 1 cycle to complete SI address transfer\n          end else begin\n            if (found_prio | found_rr) begin\n              m_grant_hot_i <= next_hot;\n              m_grant_enc_i <= next_enc;\n              any_grant <= 1'b1;\n              grant_rnw <= |(rnw & next_hot);\n              if (~found_prio) begin\n                last_rr_hot <= next_rr_hot;\n              end\n            end\n          end\n        end\n      end\n    \n      /////////////////////////////////////////////////////////////////////////////\n      // Fixed Priority arbiter\n      // Selects next request to grant from among inputs with PRIO > 0, if any.\n      /////////////////////////////////////////////////////////////////////////////\n      \n      always @ * begin : ALG_PRIO\n        integer ip;\n        any_prio = 1'b0;\n        which_prio_hot = 0;        \n        which_prio_enc = 0;    \n        current_highest = 0;    \n        for (ip=0; ip < C_NUM_S; ip=ip+1) begin\n          if (P_PRIO_MASK[ip] & ({1'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest)) begin\n            if (s_avalid[ip]) begin\n              current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4];\n              any_prio = 1'b1;\n              which_prio_hot = 1'b1 << ip;\n              which_prio_enc = ip;\n            end\n          end   \n        end\n        found_prio = any_prio;\n        next_prio_hot = which_prio_hot;\n        next_prio_enc = which_prio_enc;\n      end\n     \n      /////////////////////////////////////////////////////////////////////////////\n      // Round-robin arbiter\n      // Selects next request to grant from among inputs with PRIO = 0, if any.\n      /////////////////////////////////////////////////////////////////////////////\n      \n      assign valid_rr = ~P_PRIO_MASK & s_avalid;\n      \n      always @ * begin : ALG_RR\n        integer ir, jr, nr;\n        next_rr_hot = 0;\n        for (ir=0;ir<C_NUM_S;ir=ir+1) begin\n          nr = (ir>0) ? (ir-1) : (C_NUM_S-1);\n          carry_rr[ir*C_NUM_S] = last_rr_hot[nr];\n          mask_rr[ir*C_NUM_S] = ~valid_rr[nr];\n          for (jr=1;jr<C_NUM_S;jr=jr+1) begin\n            nr = (ir-jr > 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1);\n            carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]);\n            if (jr < C_NUM_S-1) begin\n              mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr];\n            end\n          end   \n          next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1];\n        end\n        next_rr_enc = f_hot2enc(next_rr_hot);\n        found_rr = |(next_rr_hot);\n      end\n  \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_S),\n         .C_SEL_WIDTH   (C_NUM_S_LOG),\n         .C_DATA_WIDTH  (C_AMESG_WIDTH)\n        ) si_amesg_mux_inst \n        (\n         .S   (next_enc),\n         .A   (s_amesg),\n         .O   (amesg_mux),\n         .OE  (1'b1)\n        ); \n        \n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          m_amesg_i <= 0;\n        end else if (~any_grant) begin\n          m_amesg_i <= amesg_mux;\n        end\n      end\n    \n    end else begin : gen_no_arbiter\n      \n      assign M_GRANT_ANY = m_grant_hot_i;\n\n      always @ (posedge ACLK) begin\n        if (ARESET) begin\n          m_valid_i <= 1'b0;\n          s_ready_i <= 1'b0;\n          m_grant_enc_i <= 0;\n          m_grant_hot_i <= 1'b0;\n          grant_rnw <= 1'b0;\n        end else begin\n          s_ready_i <= 1'b0;\n          if (m_valid_i) begin\n            if (m_aready) begin\n              m_valid_i <= 1'b0;\n              m_grant_hot_i <= 1'b0;\n            end\n          end else if (m_grant_hot_i) begin\n            m_valid_i <= 1'b1;\n            s_ready_i[0] <= 1'b1;  // Assert S_AW/READY for 1 cycle to complete SI address transfer\n          end else if (s_avalid[0]) begin\n            m_grant_hot_i <= 1'b1;\n            grant_rnw <= rnw[0];\n          end\n        end\n      end\n      \n      always @ (posedge ACLK) begin\n        if (ARESET) begin\n          m_amesg_i <= 0;\n        end else if (~m_grant_hot_i) begin\n          m_amesg_i <= s_amesg;\n        end\n      end\n    \n    end  // gen_arbiter\n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: addr_arbiter.v\n//\n// Description: \n//   Instantiates generic priority encoder.\n//   Each request is qualified if its target has not reached its issuing limit.\n//   Muxes mesg and target inputs based on arbitration results.\n//-----------------------------------------------------------------------------\n//\n// Structure:\n//    addr_arbiter\n//      mux_enc\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_addr_arbiter #\n  (\n   parameter         C_FAMILY                         = \"none\", \n   parameter integer C_NUM_S                = 1, \n   parameter integer C_NUM_S_LOG                = 1, \n   parameter integer C_NUM_M               = 1, \n   parameter integer C_MESG_WIDTH                 = 1, \n   parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY             = {C_NUM_S{32'h00000000}}\n                       // Arbitration priority among each SI slot. \n                       // Higher values indicate higher priority.\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 'h0-'hF.\n   )\n  (\n   // Global Signals\n   input  wire                                      ACLK,\n   input  wire                                      ARESET,\n   // Slave Ports\n   input  wire [C_NUM_S*C_MESG_WIDTH-1:0]  S_MESG,\n   input  wire [C_NUM_S*C_NUM_M-1:0]                S_TARGET_HOT,\n   input  wire [C_NUM_S-1:0]                S_VALID,\n   input  wire [C_NUM_S-1:0]                S_VALID_QUAL,\n   output wire [C_NUM_S-1:0]                S_READY,\n   // Master Ports\n   output wire [C_MESG_WIDTH-1:0]                    M_MESG,\n   output wire [C_NUM_M-1:0]                           M_TARGET_HOT,\n   output wire [C_NUM_S_LOG-1:0]                      M_GRANT_ENC,\n   output wire                                        M_VALID,\n   input  wire                                        M_READY,\n   // Sideband input\n   input  wire [C_NUM_M-1:0]                ISSUING_LIMIT\n   );\n   \n  // Generates a mask for all input slots that are priority based\n  function [C_NUM_S-1:0] f_prio_mask\n    (\n      input integer null_arg\n    );\n    reg   [C_NUM_S-1:0]            mask;\n    integer                        i;    \n    begin\n      mask = 0;    \n      for (i=0; i < C_NUM_S; i=i+1) begin\n        mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0);\n      end \n      f_prio_mask = mask;\n    end   \n  endfunction\n  \n  // Convert 16-bit one-hot to 4-bit binary\n  function [3:0] f_hot2enc\n    (\n      input [15:0]  one_hot\n    );\n    begin\n      f_hot2enc[0] = |(one_hot & 16'b1010101010101010);\n      f_hot2enc[1] = |(one_hot & 16'b1100110011001100);\n      f_hot2enc[2] = |(one_hot & 16'b1111000011110000);\n      f_hot2enc[3] = |(one_hot & 16'b1111111100000000);\n    end\n  endfunction\n\n  localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0);\n\n  reg                     m_valid_i = 1'b0;\n  reg [C_NUM_S-1:0]       s_ready_i = 0;\n  reg [C_NUM_S-1:0]       qual_reg;\n  reg [C_NUM_S-1:0]       grant_hot; \n  reg [C_NUM_S-1:0]       last_rr_hot;\n  reg                     any_grant;\n  reg                     any_prio;\n  reg                     found_prio;\n  reg [C_NUM_S-1:0]       which_prio_hot;\n  reg [C_NUM_S-1:0]       next_prio_hot;\n  reg [C_NUM_S_LOG-1:0]   which_prio_enc;          \n  reg [C_NUM_S_LOG-1:0]   next_prio_enc;    \n  reg [4:0]               current_highest;\n  wire [C_NUM_S-1:0]      valid_rr;\n  reg [15:0]              next_rr_hot;\n  reg [C_NUM_S_LOG-1:0]   next_rr_enc;    \n  reg [C_NUM_S*C_NUM_S-1:0] carry_rr;\n  reg [C_NUM_S*C_NUM_S-1:0] mask_rr;\n  reg                     found_rr;\n  wire [C_NUM_S-1:0]      next_hot;\n  wire [C_NUM_S_LOG-1:0]  next_enc;    \n  reg                     prio_stall;\n  integer                 i;\n  wire [C_NUM_S-1:0]      valid_qual_i;\n  reg  [C_NUM_S_LOG-1:0]  m_grant_enc_i;\n  reg  [C_NUM_M-1:0]      m_target_hot_i;\n  wire [C_NUM_M-1:0]      m_target_hot_mux;\n  reg  [C_MESG_WIDTH-1:0] m_mesg_i;\n  wire [C_MESG_WIDTH-1:0] m_mesg_mux;\n  genvar                  gen_si;\n\n  assign M_VALID = m_valid_i;\n  assign S_READY = s_ready_i;\n  assign M_GRANT_ENC = m_grant_enc_i;\n  assign M_MESG = m_mesg_i;\n  assign M_TARGET_HOT = m_target_hot_i;\n  \n  generate\n    if (C_NUM_S>1) begin : gen_arbiter\n      \n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          qual_reg <= 0;\n        end else begin \n          qual_reg <= valid_qual_i | ~S_VALID; // Don't disqualify when bus not VALID (valid_qual_i would be garbage)\n        end\n      end\n    \n      for (gen_si=0; gen_si<C_NUM_S; gen_si=gen_si+1) begin : gen_req_qual\n        assign valid_qual_i[gen_si] = S_VALID_QUAL[gen_si] & (|(S_TARGET_HOT[gen_si*C_NUM_M+:C_NUM_M] & ~ISSUING_LIMIT));\n      end\n    \n      /////////////////////////////////////////////////////////////////////////////\n      // Grant a new request when there is none still pending.\n      // If no qualified requests found, de-assert M_VALID.\n      /////////////////////////////////////////////////////////////////////////////\n      \n      assign next_hot = found_prio ? next_prio_hot : next_rr_hot;\n      assign next_enc = found_prio ? next_prio_enc : next_rr_enc;\n      \n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          m_valid_i <= 0;\n          s_ready_i <= 0;\n          grant_hot <= 0;\n          any_grant <= 1'b0;\n          m_grant_enc_i <= 0;\n          last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};\n          m_target_hot_i <= 0;\n        end else begin\n          s_ready_i <= 0;\n          if (m_valid_i) begin\n            // Stall 1 cycle after each master-side completion.\n            if (M_READY) begin  // Master-side completion\n              m_valid_i <= 1'b0;\n              grant_hot <= 0;\n              any_grant <= 1'b0;\n            end\n          end else if (any_grant) begin\n            m_valid_i <= 1'b1;\n            s_ready_i <= grant_hot;  // Assert S_AW/READY for 1 cycle to complete SI address transfer (regardless of M_AREADY)\n          end else begin\n            if ((found_prio | found_rr) & ~prio_stall) begin\n              // Waste 1 cycle and re-arbitrate if target of highest prio hit issuing limit in previous cycle (valid_qual_i).\n              if (|(next_hot & valid_qual_i)) begin  \n                grant_hot <= next_hot;\n                m_grant_enc_i <= next_enc;\n                any_grant <= 1'b1;\n                if (~found_prio) begin\n                  last_rr_hot <= next_rr_hot;\n                end\n                m_target_hot_i <= m_target_hot_mux;\n              end\n            end\n          end\n        end\n      end\n    \n      /////////////////////////////////////////////////////////////////////////////\n      // Fixed Priority arbiter\n      // Selects next request to grant from among inputs with PRIO > 0, if any.\n      /////////////////////////////////////////////////////////////////////////////\n          \n      always @ * begin : ALG_PRIO\n        integer ip;\n        any_prio = 1'b0;\n        prio_stall = 1'b0;\n        which_prio_hot = 0;        \n        which_prio_enc = 0;    \n        current_highest = 0;    \n        for (ip=0; ip < C_NUM_S; ip=ip+1) begin\n          // Disqualify slot if target hit issuing limit (pass to lower prio slot).\n          if (P_PRIO_MASK[ip] & S_VALID[ip] & qual_reg[ip]) begin\n            if ({1'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest) begin\n              current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4];\n              // Stall 1 cycle when highest prio is recovering from SI-side handshake.\n              // (Do not allow lower-prio slot to win arbitration.)\n              if (s_ready_i[ip]) begin\n                any_prio = 1'b0;\n                prio_stall = 1'b1;\n                which_prio_hot = 0;\n                which_prio_enc = 0;\n              end else begin\n                any_prio = 1'b1;\n                which_prio_hot = 1'b1 << ip;\n                which_prio_enc = ip;\n              end\n            end\n          end   \n        end\n        found_prio = any_prio;\n        next_prio_hot = which_prio_hot;\n        next_prio_enc = which_prio_enc;\n      end\n     \n      /////////////////////////////////////////////////////////////////////////////\n      // Round-robin arbiter\n      // Selects next request to grant from among inputs with PRIO = 0, if any.\n      /////////////////////////////////////////////////////////////////////////////\n      \n      // Disqualify slot if target hit issuing limit 2 or more cycles earlier (pass to next RR slot).\n      // Disqualify for 1 cycle a slot that is recovering from SI-side handshake (s_ready_i),\n      //   and allow arbitration to pass to any other RR requester.\n      assign valid_rr = ~P_PRIO_MASK & S_VALID & ~s_ready_i & qual_reg;\n      \n      always @ * begin : ALG_RR\n        integer ir, jr, nr;\n        next_rr_hot = 0;\n        for (ir=0;ir<C_NUM_S;ir=ir+1) begin\n          nr = (ir>0) ? (ir-1) : (C_NUM_S-1);\n          carry_rr[ir*C_NUM_S] = last_rr_hot[nr];\n          mask_rr[ir*C_NUM_S] = ~valid_rr[nr];\n          for (jr=1;jr<C_NUM_S;jr=jr+1) begin\n            nr = (ir-jr > 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1);\n            carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]);\n            if (jr < C_NUM_S-1) begin\n              mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr];\n            end\n          end   \n          next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1];\n        end\n        next_rr_enc = f_hot2enc(next_rr_hot);\n        found_rr = |(next_rr_hot);\n      end\n  \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_S),\n         .C_SEL_WIDTH   (C_NUM_S_LOG),\n         .C_DATA_WIDTH  (C_MESG_WIDTH)\n        ) mux_mesg \n        (\n         .S   (m_grant_enc_i),\n         .A   (S_MESG),\n         .O   (m_mesg_mux),\n         .OE  (1'b1)\n        ); \n        \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_S),\n         .C_SEL_WIDTH   (C_NUM_S_LOG),\n         .C_DATA_WIDTH  (C_NUM_M)\n        ) si_amesg_mux_inst \n        (\n         .S   (next_enc),\n         .A   (S_TARGET_HOT),\n         .O   (m_target_hot_mux),\n         .OE  (1'b1)\n        ); \n        \n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          m_mesg_i <= 0;\n        end else if (~m_valid_i) begin\n          m_mesg_i <= m_mesg_mux;\n        end\n      end\n    \n    end else begin : gen_no_arbiter\n      \n      assign valid_qual_i = S_VALID_QUAL & |(S_TARGET_HOT & ~ISSUING_LIMIT);\n      \n      always @ (posedge ACLK) begin\n        if (ARESET) begin\n          m_valid_i <= 1'b0;\n          s_ready_i <= 1'b0;\n          m_grant_enc_i <= 0;\n        end else begin\n          s_ready_i <= 1'b0;\n          if (m_valid_i) begin\n            if (M_READY) begin\n              m_valid_i <= 1'b0;\n            end\n          end else if (S_VALID[0] & valid_qual_i[0] & ~s_ready_i) begin\n            m_valid_i <= 1'b1;\n            s_ready_i <= 1'b1;\n            m_target_hot_i <= S_TARGET_HOT;\n          end\n        end\n      end\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          m_mesg_i <= 0;\n        end else if (~m_valid_i) begin\n          m_mesg_i <= S_MESG;\n        end\n      end\n      \n      \n    end  // gen_arbiter\n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: Addr Decoder\n// Each received address is compared to base and high address pairs for each \n//   of a set of decode targets. \n// The matching target's index (if any) is output combinatorially.\n// If the decode is successful (matches any target), the MATCH output is asserted.\n// For each target, a set of alternative address ranges may be specified.\n// The base and high address pairs are formatted as a pair of 2-dimensional arrays,\n//   alternative address ranges iterate within each target.\n// The alternative range which matches the address is also output as REGION.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   addr_decoder\n//      comparator_static\n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_addr_decoder #\n  (\n   parameter         C_FAMILY          = \"none\",\n   parameter integer C_NUM_TARGETS     = 2,  // Number of decode targets = [1:16]\n   parameter integer C_NUM_TARGETS_LOG = 1,  // Log2(C_NUM_TARGETS)\n   parameter integer C_NUM_RANGES      = 1, // Number of alternative ranges that\n                                             //    can match each target [1:16]\n   parameter integer C_ADDR_WIDTH      = 32, // Width of decoder operand and of\n                                             //   each base and high address [2:64]\n   parameter integer C_TARGET_ENC      = 0,  // Enable encoded target output\n   parameter integer C_TARGET_HOT      = 1,  // Enable 1-hot target output\n   parameter integer C_REGION_ENC      = 0,   // Enable REGION output\n   parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}}, \n   parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}}, \n   parameter [C_NUM_TARGETS:0]    C_TARGET_QUAL                 = {C_NUM_TARGETS{1'b1}},\n                       // Indicates whether each target has connectivity.\n                       // Format: C_NUM_TARGETS{Bit1}.\n   parameter integer   C_RESOLUTION                 = 0,\n                       // Number of low-order ADDR bits that can be ignored when decoding.\n   parameter integer   C_COMPARATOR_THRESHOLD       = 6\n                       // Number of decoded ADDR bits above which will implement comparator_static.\n   )\n  (\n   input  wire [C_ADDR_WIDTH-1:0]      ADDR,        // Decoder input operand\n   output wire [C_NUM_TARGETS-1:0]     TARGET_HOT,  // Target matching address (1-hot)\n   output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC,  // Target matching address (encoded)\n   output wire                         MATCH,       // Decode successful\n   output wire [3:0]                   REGION      // Range within target matching address (encoded)\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  genvar target_cnt;\n  genvar region_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Function to detect addrs is in the addressable range.\n  // Only compare 4KB page address (ignore low-order 12 bits)\n  function  decode_address;\n    input [C_ADDR_WIDTH-1:0] base, high, addr;\n    reg   [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask;\n    reg   [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page;\n    reg   [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page;\n    reg   [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page;\n  begin\n    addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];\n    base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];\n    high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];\n    if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin\n      decode_address = 1'b0;\n    end else begin\n      mask  = base_page ^ high_page;\n      if ( (base_page & ~mask) == (addr_page & ~mask) ) begin\n        decode_address = 1'b1;\n      end else begin\n        decode_address = 1'b0;\n      end\n    end\n  end\n  endfunction\n  \n  // Generates a binary coded from onehotone encoded\n  function [3:0] f_hot2enc\n    (\n      input [15:0]  one_hot\n    );\n    begin\n      f_hot2enc[0] = |(one_hot & 16'b1010101010101010);\n      f_hot2enc[1] = |(one_hot & 16'b1100110011001100);\n      f_hot2enc[2] = |(one_hot & 16'b1111000011110000);\n      f_hot2enc[3] = |(one_hot & 16'b1111111100000000);\n    end\n  endfunction\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  wire [C_NUM_TARGETS-1:0]              TARGET_HOT_I;     // Target matching address (1-hot).\n  wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT;      // For address hit (1-hot).\n  wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG;  // For address hit (1-hot).\n  wire [C_NUM_RANGES-1:0]               REGION_HOT;       // Reginon matching address (1-hot).\n  wire [3:0]                            TARGET_ENC_I;     // Internal version of encoded hit. \n  /////////////////////////////////////////////////////////////////////////////\n  // Generate detection per region per target.\n  generate\n    for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target\n      for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region\n        // Detect if this is an address hit (including used region decoding).\n        if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static\n          if (C_TARGET_QUAL[target_cnt] &&\n              ((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) ||\n               (C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range\n            generic_baseblocks_v2_1_0_comparator_static #\n            (\n            .C_FAMILY(\"rtl\"),\n            .C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]),\n            .C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION)\n            ) addr_decode_comparator\n            (\n            .CIN(1'b1),\n            .A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] &\n              ~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^\n                C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])),\n            .COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt])\n            );\n          end else begin : gen_null_range\n            assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0;\n          end\n        end else begin : gen_no_comparator_static\n          assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ? \n                                    decode_address(\n                                      C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],\n                                      C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],\n                                      ADDR)\n                                    : 1'b0;\n        end  // gen_comparator_static\n        assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt];\n      end  // gen_region\n      \n      // All regions are non-overlapping\n      // => Or all the region detections for this target to determine if it is a hit.\n      assign TARGET_HOT_I[target_cnt]  = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES];\n    end  // gen_target\n    \n    for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region_or\n      assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS];\n    end  // gen_region_or\n  endgenerate\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // All regions are non-overlapping\n  // => Or all the target hit detections if it is a match.\n  assign MATCH = | TARGET_HOT_I;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Assign conditional onehot target output signal.\n  generate\n    if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT\n      assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1;\n    end else begin : NO_TARGET_ONEHOT\n      assign TARGET_HOT = {C_NUM_TARGETS{1'b0}};\n    end\n  endgenerate\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Assign conditional encoded target output signal.\n  generate\n    if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED\n      assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I);\n      assign TARGET_ENC   = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0];\n    end else begin : NO_TARGET_ENCODED\n      assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}};\n    end\n  endgenerate\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Assign conditional encoded region output signal.\n  generate\n    if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED\n      assign REGION = f_hot2enc(REGION_HOT);\n    end else begin : NO_REGION_ENCODED\n      assign REGION = 4'b0;\n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Round-Robin Arbiter for R and B channel responses\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    arbiter_resp\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_arbiter_resp #\n  (\n   parameter         C_FAMILY       = \"none\",\n   parameter integer C_NUM_S        = 4,      // Number of requesting Slave ports = [2:16]\n   parameter integer C_NUM_S_LOG    = 2,      // Log2(C_NUM_S)\n   parameter integer C_GRANT_ENC    = 0,      // Enable encoded grant output\n   parameter integer C_GRANT_HOT    = 1       // Enable 1-hot grant output\n   )\n  (\n   // Global Inputs\n   input  wire                     ACLK,\n   input  wire                     ARESET,\n   // Slave  Ports\n   input  wire [C_NUM_S-1:0]       S_VALID,      // Request from each slave\n   output wire [C_NUM_S-1:0]       S_READY,      // Grant response to each slave\n   // Master Ports\n   output wire [C_NUM_S_LOG-1:0]   M_GRANT_ENC,  // Granted slave index (encoded)\n   output wire [C_NUM_S-1:0]       M_GRANT_HOT,  // Granted slave index (1-hot)\n   output wire                     M_VALID,      // Grant event\n   input  wire                     M_READY\n   );\n\n  // Generates a binary coded from onehotone encoded\n  function [4:0] f_hot2enc\n    (\n      input [16:0]  one_hot\n    );\n    begin\n      f_hot2enc[0] = |(one_hot & 17'b01010101010101010);\n      f_hot2enc[1] = |(one_hot & 17'b01100110011001100);\n      f_hot2enc[2] = |(one_hot & 17'b01111000011110000);\n      f_hot2enc[3] = |(one_hot & 17'b01111111100000000);\n      f_hot2enc[4] = |(one_hot & 17'b10000000000000000);\n    end\n  endfunction\n\n  (* use_clock_enable = \"yes\" *)\n  reg [C_NUM_S-1:0]      chosen = 0;\n  \n  wire [C_NUM_S-1:0]     grant_hot; \n  wire                   master_selected; \n  wire                   active_master;\n  wire                   need_arbitration;\n  wire                   m_valid_i;\n  wire [C_NUM_S-1:0]     s_ready_i;\n  wire                   access_done;\n  reg [C_NUM_S-1:0]      last_rr_hot;\n  wire [C_NUM_S-1:0]     valid_rr;\n  reg [C_NUM_S-1:0]      next_rr_hot;\n  reg [C_NUM_S*C_NUM_S-1:0] carry_rr;\n  reg [C_NUM_S*C_NUM_S-1:0] mask_rr;\n  integer                 i;\n  integer                 j;\n  integer                 n;\n  \n  /////////////////////////////////////////////////////////////////////////////\n  //   \n  // Implementation of the arbiter outputs independant of arbitration\n  //\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Mask the current requests with the chosen master\n  assign grant_hot        = chosen & S_VALID;\n\n  // See if we have a selected master\n  assign master_selected  = |grant_hot[0+:C_NUM_S];\n\n  // See if we have current requests\n  assign active_master    = |S_VALID;\n\n  // Access is completed\n  assign access_done = m_valid_i & M_READY;\n  \n  // Need to handle if we drive S_ready combinatorial and without an IDLE state\n\n  // Drive S_READY on the master who has been chosen when we get a M_READY\n  assign s_ready_i = {C_NUM_S{M_READY}} & grant_hot[0+:C_NUM_S];\n\n  // Drive M_VALID if we have a selected master\n  assign m_valid_i = master_selected;\n                \n  // If we have request and not a selected master, we need to arbitrate a new chosen \n  assign need_arbitration = (active_master & ~master_selected) | access_done;\n\n  // need internal signals of the output signals\n  assign M_VALID = m_valid_i;\n  assign S_READY = s_ready_i;\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Assign conditional onehot target output signal.\n  assign M_GRANT_HOT = (C_GRANT_HOT == 1) ? grant_hot[0+:C_NUM_S] : {C_NUM_S{1'b0}};\n  /////////////////////////////////////////////////////////////////////////////\n  // Assign conditional encoded target output signal.\n  assign M_GRANT_ENC = (C_GRANT_ENC == 1) ? f_hot2enc(grant_hot) : {C_NUM_S_LOG{1'b0}};\n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Select a new chosen when we need to arbitrate\n  // If we don't have a new chosen, keep the old one since it's a good chance\n  // that it will do another request\n  always @(posedge ACLK)\n    begin\n      if (ARESET) begin\n        chosen <= {C_NUM_S{1'b0}};\n        last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};\n      end else if (need_arbitration) begin\n        chosen <= next_rr_hot;   \n        if (|next_rr_hot) last_rr_hot <= next_rr_hot;\n      end\n    end\n\n  assign valid_rr =  S_VALID;\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Round-robin arbiter\n  // Selects next request to grant from among inputs with PRIO = 0, if any.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  always @ * begin\n    next_rr_hot = 0;\n    for (i=0;i<C_NUM_S;i=i+1) begin\n      n = (i>0) ? (i-1) : (C_NUM_S-1);\n      carry_rr[i*C_NUM_S] = last_rr_hot[n];\n      mask_rr[i*C_NUM_S] = ~valid_rr[n];\n      for (j=1;j<C_NUM_S;j=j+1) begin\n        n = (i-j > 0) ? (i-j-1) : (C_NUM_S+i-j-1);\n        carry_rr[i*C_NUM_S+j] = carry_rr[i*C_NUM_S+j-1] | (last_rr_hot[n] & mask_rr[i*C_NUM_S+j-1]);\n        if (j < C_NUM_S-1) begin\n          mask_rr[i*C_NUM_S+j] = mask_rr[i*C_NUM_S+j-1] & ~valid_rr[n];\n        end\n      end   \n      next_rr_hot[i] = valid_rr[i] & carry_rr[(i+1)*C_NUM_S-1];\n    end\n  end\n  \nendmodule\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: crossbar_sasd.v\n//\n// Description: \n//   This module is a M-master to N-slave AXI axi_crossbar_v2_1_23_crossbar switch.\n//   Single transaction issuing, single arbiter (both W&R), single data pathways.\n//   The interface of this module consists of a vectored slave and master interface\n//     in which all slots are sized and synchronized to the native width and clock \n//     of the interconnect, and are all AXI4 protocol.\n//   All width, clock and protocol conversions are done outside this block, as are\n//     any pipeline registers or data FIFOs.\n//   This module contains all arbitration, decoders and channel multiplexing logic.\n//     It also contains the diagnostic registers and control interface.\n//\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    crossbar_sasd\n//      addr_arbiter_sasd\n//        mux_enc\n//      addr_decoder\n//        comparator_static\n//      splitter\n//      mux_enc\n//      axic_register_slice\n//      decerr_slave\n//      \n//-----------------------------------------------------------------------------\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_crossbar_sasd #\n  (\n   parameter         C_FAMILY                       = \"none\", \n   parameter integer C_NUM_SLAVE_SLOTS              =   1, \n   parameter integer C_NUM_MASTER_SLOTS             =   1, \n   parameter integer C_NUM_ADDR_RANGES              = 1,\n   parameter integer C_AXI_ID_WIDTH                   = 1, \n   parameter integer C_AXI_ADDR_WIDTH                 = 32, \n   parameter integer C_AXI_DATA_WIDTH = 32, \n   parameter integer C_AXI_PROTOCOL                 = 0, \n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}}, \n   parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},\n   parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS      = 0,\n   parameter integer C_AXI_AWUSER_WIDTH               = 1,\n   parameter integer C_AXI_ARUSER_WIDTH               = 1,\n   parameter integer C_AXI_WUSER_WIDTH                = 1,\n   parameter integer C_AXI_RUSER_WIDTH                = 1,\n   parameter integer C_AXI_BUSER_WIDTH                = 1,\n   parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE           = {C_NUM_SLAVE_SLOTS{1'b1}}, \n   parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ            = {C_NUM_SLAVE_SLOTS{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE           = {C_NUM_MASTER_SLOTS{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ            = {C_NUM_MASTER_SLOTS{1'b1}}, \n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY             = {C_NUM_SLAVE_SLOTS{32'h00000000}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE                   = {C_NUM_MASTER_SLOTS{32'h00000000}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE            = {C_NUM_MASTER_SLOTS{32'h00000000}},\n   parameter integer C_R_REGISTER               = 0,\n   parameter integer C_RANGE_CHECK                    = 0,\n   parameter integer C_ADDR_DECODE                    = 0,\n   parameter integer C_DEBUG              = 1\n   )\n  (\n   // Global Signals\n   input  wire                                                    ACLK,\n   input  wire                                                    ARESETN,\n   // Slave Interface Write Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_AWID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           S_AXI_AWADDR,\n   input  wire [C_NUM_SLAVE_SLOTS*8-1:0]                          S_AXI_AWLEN,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_AWSIZE,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_AWBURST,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_AWLOCK,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWCACHE,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_AWPROT,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWREGION,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWQOS,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0]         S_AXI_AWUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_AWVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_AWREADY,\n   // Slave Interface Write Data Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_WID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]     S_AXI_WDATA,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0]   S_AXI_WSTRB,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WLAST,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0]          S_AXI_WUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WREADY,\n   // Slave Interface Write Response Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_BID,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_BRESP,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_BVALID,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_BREADY,\n   // Slave Interface Read Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_ARID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           S_AXI_ARADDR,\n   input  wire [C_NUM_SLAVE_SLOTS*8-1:0]                          S_AXI_ARLEN,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_ARSIZE,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_ARBURST,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_ARLOCK,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARCACHE,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_ARPROT,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARREGION,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARQOS,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0]         S_AXI_ARUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_ARVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_ARREADY,\n   // Slave Interface Read Data Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_RID,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]     S_AXI_RDATA,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_RRESP,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RLAST,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0]          S_AXI_RUSER,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RVALID,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RREADY,\n   // Master Interface Write Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_AWID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          M_AXI_AWADDR,\n   output wire [C_NUM_MASTER_SLOTS*8-1:0]                         M_AXI_AWLEN,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_AWSIZE,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_AWBURST,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_AWLOCK,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWCACHE,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_AWPROT,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWREGION,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWQOS,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0]        M_AXI_AWUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_AWVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_AWREADY,\n   // Master Interface Write Data Ports\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_WID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]    M_AXI_WDATA,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0]  M_AXI_WSTRB,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WLAST,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0]         M_AXI_WUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WREADY,\n   // Master Interface Write Response Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_BID,  // Unused\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_BRESP,\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0]         M_AXI_BUSER,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_BVALID,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_BREADY,\n   // Master Interface Read Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_ARID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          M_AXI_ARADDR,\n   output wire [C_NUM_MASTER_SLOTS*8-1:0]                         M_AXI_ARLEN,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_ARSIZE,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_ARBURST,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_ARLOCK,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARCACHE,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_ARPROT,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARREGION,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARQOS,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0]        M_AXI_ARUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_ARVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_ARREADY,\n   // Master Interface Read Data Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_RID,  // Unused\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]    M_AXI_RDATA,\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_RRESP,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RLAST,\n   input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0]         M_AXI_RUSER,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RVALID,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RREADY\n   );\n   \n  localparam integer  P_AXI4 = 0;\n  localparam integer  P_AXI3 = 1;\n  localparam integer  P_AXILITE = 2;\n  localparam integer P_NUM_MASTER_SLOTS_DE = C_RANGE_CHECK ? C_NUM_MASTER_SLOTS+1 : C_NUM_MASTER_SLOTS;\n  localparam integer P_NUM_MASTER_SLOTS_LOG = (C_NUM_MASTER_SLOTS>1) ? f_ceil_log2(C_NUM_MASTER_SLOTS) : 1;\n  localparam integer P_NUM_MASTER_SLOTS_DE_LOG = (P_NUM_MASTER_SLOTS_DE>1) ? f_ceil_log2(P_NUM_MASTER_SLOTS_DE) : 1;\n  localparam integer P_NUM_SLAVE_SLOTS_LOG = (C_NUM_SLAVE_SLOTS>1) ? f_ceil_log2(C_NUM_SLAVE_SLOTS) : 1;\n  localparam integer P_AXI_AUSER_WIDTH = (C_AXI_AWUSER_WIDTH > C_AXI_ARUSER_WIDTH) ? C_AXI_AWUSER_WIDTH : C_AXI_ARUSER_WIDTH;\n  localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1;\n  localparam integer P_AMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+2+4+4 + P_AXI_AUSER_WIDTH + 4;\n  localparam integer P_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH;\n  localparam integer P_RMESG_WIDTH = 1+2 + C_AXI_DATA_WIDTH + C_AXI_RUSER_WIDTH;\n  localparam integer P_WMESG_WIDTH = 1 + C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH;\n  localparam [31:0]   P_AXILITE_ERRMODE = 32'h00000001;\n  localparam integer P_NONSECURE_BIT = 1; \n  localparam [C_NUM_MASTER_SLOTS-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE);  // Mask of secure MI-slots\n  localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXILITE_MASK = f_m_axilite(0);  // Mask of axilite rule-check MI-slots\n  localparam [1:0]   P_FIXED = 2'b00;\n  localparam integer P_BYPASS = 0;\n  localparam integer P_LIGHTWT = 7;\n  localparam integer P_FULLY_REG = 1;\n  localparam integer P_R_REG_CONFIG = C_R_REGISTER == 8 ?  // \"Automatic\" reg-slice\n        (C_RANGE_CHECK ? ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHTWT : P_FULLY_REG) : P_BYPASS) :  // Bypass if no R-channel mux\n        C_R_REGISTER;\n  localparam P_DECERR = 2'b11;\n\n  //---------------------------------------------------------------------------\n  // Functions\n  //---------------------------------------------------------------------------\n  // Ceiling of log2(x)\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  // Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value\n  //   only for end-point SI-slots\n  function [C_AXI_ID_WIDTH-1:0] f_extend_ID\n    (\n     input [C_AXI_ID_WIDTH-1:0] s_id,\n     input integer slot\n     );\n    begin\n      f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH]));\n    end\n  endfunction\n\n  // Convert Bit32 vector of range [0,1] to Bit1 vector on MI\n  function [C_NUM_MASTER_SLOTS-1:0] f_bit32to1_mi\n    (input [C_NUM_MASTER_SLOTS*32-1:0] vec32);\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        f_bit32to1_mi[mi] = vec32[mi*32];\n      end\n    end\n  endfunction\n\n  // AxiLite error-checking mask (on MI)      \n  function [C_NUM_MASTER_SLOTS-1:0] f_m_axilite\n    (\n      input integer null_arg\n    );\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        f_m_axilite[mi] = (C_M_AXI_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);\n      end\n    end\n  endfunction\n\n  genvar gen_si_slot;\n  genvar gen_mi_slot;\n  wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0]                      si_awmesg          ;\n  wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0]                      si_armesg          ;\n  wire [P_AMESG_WIDTH-1:0]                                        aa_amesg         ;\n  wire [C_AXI_ID_WIDTH-1:0]                                       mi_aid            ;\n  wire [C_AXI_ADDR_WIDTH-1:0]                                     mi_aaddr          ;\n  wire [8-1:0]                                                    mi_alen           ;\n  wire [3-1:0]                                                    mi_asize          ;\n  wire [2-1:0]                                                    mi_alock          ;\n  wire [3-1:0]                                                    mi_aprot          ;\n  wire [2-1:0]                                                    mi_aburst        ;\n  wire [4-1:0]                                                    mi_acache        ;\n  wire [4-1:0]                                                    mi_aregion        ;\n  wire [4-1:0]                                                    mi_aqos        ;\n  wire [P_AXI_AUSER_WIDTH-1:0]                                    mi_auser        ;\n  wire [4-1:0]                                                    target_region        ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  aa_grant_hot     ;\n  wire [P_NUM_SLAVE_SLOTS_LOG-1:0]                                  aa_grant_enc     ;\n  wire                                                            aa_grant_rnw ;\n  wire                                                            aa_grant_any ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                                   target_mi_hot    ;\n  wire [P_NUM_MASTER_SLOTS_LOG-1:0]                                   target_mi_enc    ;\n  reg  [P_NUM_MASTER_SLOTS_DE-1:0]                               m_atarget_hot = 0    ;\n  reg  [P_NUM_MASTER_SLOTS_DE_LOG-1:0]                               m_atarget_enc = 0    ;\n  wire [P_NUM_MASTER_SLOTS_DE_LOG-1:0]                               m_atarget_enc_comb    ;\n  wire                                                            match;\n  wire                                                            any_error         ;\n  wire [7:0]                                                      m_aerror_i         ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_awvalid            ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_awready            ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_arvalid            ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_arready            ;\n  wire                                                            aa_awvalid         ;\n  wire                                                            aa_awready         ;\n  wire                                                            aa_arvalid         ;\n  wire                                                            aa_arready         ;\n  wire                                                            mi_awvalid_en;\n  wire                                                            mi_awready_mux;\n  wire                                                            mi_arvalid_en;\n  wire                                                            mi_arready_mux;\n  wire                                                            w_transfer_en;\n  wire                                                            w_complete_mux;\n  wire                                                            b_transfer_en;\n  wire                                                            b_complete_mux;\n  wire                                                            r_transfer_en;\n  wire                                                            r_complete_mux;\n  wire                                                            target_secure;\n  wire                                                            target_write;\n  wire                                                            target_read;\n  wire                                                            target_axilite;\n  \n  wire [P_BMESG_WIDTH-1:0]                                        si_bmesg           ;\n  wire [P_NUM_MASTER_SLOTS_DE*P_BMESG_WIDTH-1:0]                 mi_bmesg           ;\n  wire [P_NUM_MASTER_SLOTS_DE*2-1:0]                             mi_bresp           ;\n  wire [P_NUM_MASTER_SLOTS_DE*C_AXI_BUSER_WIDTH-1:0]             mi_buser           ;\n  wire [2-1:0]                                                    si_bresp           ;\n  wire [C_AXI_BUSER_WIDTH-1:0]                                    si_buser           ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_bvalid          ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_bready          ;\n  wire                                                            aa_bvalid          ;\n  wire                                                            aa_bready         ;\n  wire                                                            si_bready         ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                                    si_bvalid;\n  \n  wire [P_RMESG_WIDTH-1:0]                                        aa_rmesg           ;\n  wire [P_RMESG_WIDTH-1:0]                                        sr_rmesg           ;\n  wire [P_NUM_MASTER_SLOTS_DE*P_RMESG_WIDTH-1:0]                 mi_rmesg           ;\n  wire [P_NUM_MASTER_SLOTS_DE*2-1:0]                             mi_rresp           ;\n  wire [P_NUM_MASTER_SLOTS_DE*C_AXI_RUSER_WIDTH-1:0]             mi_ruser           ;\n  wire [P_NUM_MASTER_SLOTS_DE*C_AXI_DATA_WIDTH-1:0]          mi_rdata              ;\n  wire [P_NUM_MASTER_SLOTS_DE*1-1:0]                             mi_rlast              ;\n  wire [2-1:0]                                                    si_rresp           ;\n  wire [C_AXI_RUSER_WIDTH-1:0]                                    si_ruser           ;\n  wire [C_AXI_DATA_WIDTH-1:0]                                 si_rdata              ;\n  wire                                                            si_rlast              ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_rvalid          ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_rready          ;\n  wire                                                            aa_rvalid          ;\n  wire                                                            aa_rready         ;\n  wire                                                            sr_rvalid          ;\n  wire                                                            si_rready         ;\n  wire                                                            sr_rready         ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                                    si_rvalid;\n  \n  wire [C_NUM_SLAVE_SLOTS*P_WMESG_WIDTH-1:0]                      si_wmesg           ;\n  wire [P_WMESG_WIDTH-1:0]                                        mi_wmesg           ;\n  wire [C_AXI_ID_WIDTH-1:0]                                    mi_wid              ;\n  wire [C_AXI_DATA_WIDTH-1:0]                            mi_wdata              ;\n  wire [C_AXI_DATA_WIDTH/8-1:0]                          mi_wstrb              ;\n  wire [C_AXI_WUSER_WIDTH-1:0]                                    mi_wuser              ;\n  wire [1-1:0]                                                    mi_wlast              ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_wvalid          ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_wready          ;\n  wire                                                            aa_wvalid          ;\n  wire                                                            aa_wready         ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                                    si_wready;\n  \n  reg  [7:0]                                                      debug_r_beat_cnt_i;\n  reg  [7:0]                                                      debug_w_beat_cnt_i;\n  reg  [7:0]                                                      debug_aw_trans_seq_i;\n  reg  [7:0]                                                      debug_ar_trans_seq_i;\n\n  reg aresetn_d = 1'b0; // Reset delay register\n  always @(posedge ACLK) begin\n    if (~ARESETN) begin\n      aresetn_d <= 1'b0;\n    end else begin\n      aresetn_d <= ARESETN;\n    end\n  end\n  wire reset;\n  assign reset = ~aresetn_d;\n\n  generate\n    axi_crossbar_v2_1_23_addr_arbiter_sasd #\n      (\n       .C_FAMILY                (C_FAMILY),\n       .C_NUM_S                 (C_NUM_SLAVE_SLOTS),\n       .C_NUM_S_LOG             (P_NUM_SLAVE_SLOTS_LOG),\n       .C_AMESG_WIDTH            (P_AMESG_WIDTH),\n       .C_GRANT_ENC             (1),\n       .C_ARB_PRIORITY          (C_S_AXI_ARB_PRIORITY)\n       )\n      addr_arbiter_inst\n        (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         // Vector of SI-side AW command request inputs\n         .S_AWMESG                (si_awmesg),\n         .S_ARMESG                (si_armesg),\n         .S_AWVALID               (S_AXI_AWVALID),\n         .S_AWREADY               (S_AXI_AWREADY),\n         .S_ARVALID               (S_AXI_ARVALID),\n         .S_ARREADY               (S_AXI_ARREADY),\n         .M_GRANT_ENC           (aa_grant_enc),\n         .M_GRANT_HOT           (aa_grant_hot),  // SI-slot 1-hot mask of granted command\n         .M_GRANT_ANY             (aa_grant_any),\n         .M_GRANT_RNW             (aa_grant_rnw),\n         .M_AMESG                (aa_amesg),  // Either S_AWMESG or S_ARMESG, as indicated by M_AWVALID and M_ARVALID.\n         .M_AWVALID               (aa_awvalid),\n         .M_AWREADY               (aa_awready),\n         .M_ARVALID               (aa_arvalid),\n         .M_ARREADY               (aa_arready)\n         );\n\n    if (C_ADDR_DECODE) begin : gen_addr_decoder\n      axi_crossbar_v2_1_23_addr_decoder #\n        (\n          .C_FAMILY          (C_FAMILY),\n          .C_NUM_TARGETS     (C_NUM_MASTER_SLOTS),\n          .C_NUM_TARGETS_LOG (P_NUM_MASTER_SLOTS_LOG),\n          .C_NUM_RANGES      (C_NUM_ADDR_RANGES),\n          .C_ADDR_WIDTH      (C_AXI_ADDR_WIDTH),\n          .C_TARGET_ENC      (1),\n          .C_TARGET_HOT      (1),\n          .C_REGION_ENC      (1),\n          .C_BASE_ADDR      (C_M_AXI_BASE_ADDR),\n          .C_HIGH_ADDR      (C_M_AXI_HIGH_ADDR),\n          .C_TARGET_QUAL     ({C_NUM_MASTER_SLOTS{1'b1}}),\n          .C_RESOLUTION      (2)\n        ) \n        addr_decoder_inst \n        (\n          .ADDR             (mi_aaddr),        \n          .TARGET_HOT       (target_mi_hot),  \n          .TARGET_ENC       (target_mi_enc),  \n          .MATCH            (match),       \n          .REGION           (target_region)      \n        );\n    end else begin : gen_no_addr_decoder\n      assign target_mi_hot = 1;\n      assign match = 1'b1;\n      assign target_region = 4'b0000;\n    end  // gen_addr_decoder\n    \n    // AW-channel arbiter command transfer completes upon completion of both M-side AW-channel transfer and B channel completion.\n    axi_crossbar_v2_1_23_splitter #  \n      (\n        .C_NUM_M                (3)\n      )\n      splitter_aw\n      (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         .S_VALID              (aa_awvalid),\n         .S_READY              (aa_awready),\n         .M_VALID              ({mi_awvalid_en, w_transfer_en, b_transfer_en}),\n         .M_READY              ({mi_awready_mux, w_complete_mux, b_complete_mux})\n      );\n    \n    // AR-channel arbiter command transfer completes upon completion of both M-side AR-channel transfer and R channel completion.\n    axi_crossbar_v2_1_23_splitter #  \n      (\n        .C_NUM_M                (2)\n      )\n      splitter_ar\n      (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         .S_VALID              (aa_arvalid),\n         .S_READY              (aa_arready),\n         .M_VALID              ({mi_arvalid_en, r_transfer_en}),\n         .M_READY              ({mi_arready_mux, r_complete_mux})\n      );\n    \n    assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);\n    assign target_write = |(target_mi_hot & C_M_AXI_SUPPORTS_WRITE);\n    assign target_read = |(target_mi_hot & C_M_AXI_SUPPORTS_READ);\n    assign target_axilite = |(target_mi_hot & P_M_AXILITE_MASK);\n    \n    assign any_error = C_RANGE_CHECK && (m_aerror_i != 0);             // DECERR if error-detection enabled and any error condition.\n    assign m_aerror_i[0] = ~match;                                     // Invalid target address\n    assign m_aerror_i[1] = target_secure && mi_aprot[P_NONSECURE_BIT]; // TrustZone violation\n    assign m_aerror_i[2] = target_axilite && ((mi_alen != 0) || \n      (mi_asize[1:0] == 2'b11) || (mi_asize[2] == 1'b1));              // AxiLite access violation\n    assign m_aerror_i[3] = (~aa_grant_rnw && ~target_write) ||\n      (aa_grant_rnw && ~target_read);                                  // R/W direction unsupported by target\n    assign m_aerror_i[7:4] = 4'b0000;                                     // Reserved\n    assign m_atarget_enc_comb = any_error ? (P_NUM_MASTER_SLOTS_DE-1) : target_mi_enc;  // Select MI slot or decerr_slave\n      \n    always @(posedge ACLK) begin\n      if (reset) begin\n        m_atarget_hot <= 0;\n        m_atarget_enc <= 0;\n      end else begin\n        m_atarget_hot <= {P_NUM_MASTER_SLOTS_DE{aa_grant_any}} & (any_error ? {1'b1, {C_NUM_MASTER_SLOTS{1'b0}}} : {1'b0, target_mi_hot});  // Select MI slot or decerr_slave\n        m_atarget_enc <= m_atarget_enc_comb;\n      end\n    end\n    \n    // Receive AWREADY from targeted MI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (1)\n      ) mi_awready_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_awready),\n       .O   (mi_awready_mux),\n       .OE  (mi_awvalid_en)\n      ); \n      \n    // Receive ARREADY from targeted MI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (1)\n      ) mi_arready_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_arready),\n       .O   (mi_arready_mux),\n       .OE  (mi_arvalid_en)\n      ); \n      \n    assign mi_awvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_awvalid_en}};  // Assert AWVALID on targeted MI.\n    assign mi_arvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_arvalid_en}};  // Assert ARVALID on targeted MI.\n    assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS];  // Propagate to MI slots.\n    assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS];  // Propagate to MI slots.\n    assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY;  // Copy from MI slots.\n    assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY;  // Copy from MI slots.\n    \n    // Receive WREADY from targeted MI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (1)\n      ) mi_wready_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_wready),\n       .O   (aa_wready),\n       .OE  (w_transfer_en)\n      ); \n      \n    assign mi_wvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_wvalid}};  // Assert WVALID on targeted MI.\n    assign si_wready = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_wready}};  // Assert WREADY on granted SI.\n    assign S_AXI_WREADY = si_wready;\n    assign w_complete_mux = aa_wready & aa_wvalid & mi_wlast;  // W burst complete on on designated SI/MI.\n    \n    // Receive RREADY from granted SI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (C_NUM_SLAVE_SLOTS),\n       .C_SEL_WIDTH   (P_NUM_SLAVE_SLOTS_LOG),\n       .C_DATA_WIDTH  (1)\n      ) si_rready_mux_inst \n      (\n       .S   (aa_grant_enc),\n       .A   (S_AXI_RREADY),\n       .O   (si_rready),\n       .OE  (r_transfer_en)\n      ); \n      \n    assign sr_rready = si_rready & r_transfer_en;\n    assign mi_rready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_rready}};  // Assert RREADY on targeted MI.\n    assign si_rvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{sr_rvalid}};  // Assert RVALID on granted SI.\n    assign S_AXI_RVALID = si_rvalid;\n    assign r_complete_mux = sr_rready & sr_rvalid & si_rlast;  // R burst complete on on designated SI/MI.\n    \n    // Receive BREADY from granted SI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (C_NUM_SLAVE_SLOTS),\n       .C_SEL_WIDTH   (P_NUM_SLAVE_SLOTS_LOG),\n       .C_DATA_WIDTH  (1)\n      ) si_bready_mux_inst \n      (\n       .S   (aa_grant_enc),\n       .A   (S_AXI_BREADY),\n       .O   (si_bready),\n       .OE  (b_transfer_en)\n      ); \n      \n    assign aa_bready = si_bready & b_transfer_en;\n    assign mi_bready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_bready}};  // Assert BREADY on targeted MI.\n    assign si_bvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_bvalid}};  // Assert BVALID on granted SI.\n    assign S_AXI_BVALID = si_bvalid;\n    assign b_complete_mux = aa_bready & aa_bvalid;  // B transfer complete on on designated SI/MI.\n    \n    for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_si_amesg\n      assign si_armesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = {  // Concatenate from MSB to LSB\n        4'b0000,\n//        S_AXI_ARREGION[gen_si_slot*4+:4],\n        S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH +: C_AXI_ARUSER_WIDTH],\n        S_AXI_ARQOS[gen_si_slot*4+:4],\n        S_AXI_ARCACHE[gen_si_slot*4+:4],\n        S_AXI_ARBURST[gen_si_slot*2+:2],\n        S_AXI_ARPROT[gen_si_slot*3+:3],\n        S_AXI_ARLOCK[gen_si_slot*2+:2],\n        S_AXI_ARSIZE[gen_si_slot*3+:3],\n        S_AXI_ARLEN[gen_si_slot*8+:8],\n        S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH],\n        f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH +: C_AXI_ID_WIDTH], gen_si_slot)\n        };\n      assign si_awmesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = {  // Concatenate from MSB to LSB\n        4'b0000,\n//        S_AXI_AWREGION[gen_si_slot*4+:4],\n        S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH +: C_AXI_AWUSER_WIDTH],\n        S_AXI_AWQOS[gen_si_slot*4+:4],\n        S_AXI_AWCACHE[gen_si_slot*4+:4],\n        S_AXI_AWBURST[gen_si_slot*2+:2],\n        S_AXI_AWPROT[gen_si_slot*3+:3],\n        S_AXI_AWLOCK[gen_si_slot*2+:2],\n        S_AXI_AWSIZE[gen_si_slot*3+:3],\n        S_AXI_AWLEN[gen_si_slot*8+:8],\n        S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH],\n        f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)\n        };\n    end  // gen_si_amesg\n    \n    assign mi_aid        = aa_amesg[0 +: C_AXI_ID_WIDTH];\n    assign mi_aaddr      = aa_amesg[C_AXI_ID_WIDTH +: C_AXI_ADDR_WIDTH];\n    assign mi_alen       = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +: 8];\n    assign mi_asize      = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +: 3];\n    assign mi_alock      = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +: 2];\n    assign mi_aprot      = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +: 3];\n    assign mi_aburst     = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +: 2];\n    assign mi_acache     = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2 +: 4];\n    assign mi_aqos       = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4 +: 4];\n    assign mi_auser      = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4 +: P_AXI_AUSER_WIDTH];\n    assign mi_aregion    = (C_ADDR_DECODE != 0) ? target_region : aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4+P_AXI_AUSER_WIDTH +: 4];\n      \n    // Broadcast AW transfer payload to all MI-slots\n    assign M_AXI_AWID        = {C_NUM_MASTER_SLOTS{mi_aid}};\n    assign M_AXI_AWADDR      = {C_NUM_MASTER_SLOTS{mi_aaddr}};\n    assign M_AXI_AWLEN       = {C_NUM_MASTER_SLOTS{mi_alen }};\n    assign M_AXI_AWSIZE      = {C_NUM_MASTER_SLOTS{mi_asize}};\n    assign M_AXI_AWLOCK      = {C_NUM_MASTER_SLOTS{mi_alock}};\n    assign M_AXI_AWPROT      = {C_NUM_MASTER_SLOTS{mi_aprot}};\n    assign M_AXI_AWREGION    = {C_NUM_MASTER_SLOTS{mi_aregion}};\n    assign M_AXI_AWBURST     = {C_NUM_MASTER_SLOTS{mi_aburst}};\n    assign M_AXI_AWCACHE     = {C_NUM_MASTER_SLOTS{mi_acache}};\n    assign M_AXI_AWQOS       = {C_NUM_MASTER_SLOTS{mi_aqos  }};\n    assign M_AXI_AWUSER      = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_AWUSER_WIDTH] }};\n    \n    // Broadcast AR transfer payload to all MI-slots\n    assign M_AXI_ARID        = {C_NUM_MASTER_SLOTS{mi_aid}};\n    assign M_AXI_ARADDR      = {C_NUM_MASTER_SLOTS{mi_aaddr}};                        \n    assign M_AXI_ARLEN       = {C_NUM_MASTER_SLOTS{mi_alen }};                        \n    assign M_AXI_ARSIZE      = {C_NUM_MASTER_SLOTS{mi_asize}};                        \n    assign M_AXI_ARLOCK      = {C_NUM_MASTER_SLOTS{mi_alock}};                        \n    assign M_AXI_ARPROT      = {C_NUM_MASTER_SLOTS{mi_aprot}};                        \n    assign M_AXI_ARREGION    = {C_NUM_MASTER_SLOTS{mi_aregion}};                          \n    assign M_AXI_ARBURST     = {C_NUM_MASTER_SLOTS{mi_aburst}};                       \n    assign M_AXI_ARCACHE     = {C_NUM_MASTER_SLOTS{mi_acache}};                       \n    assign M_AXI_ARQOS       = {C_NUM_MASTER_SLOTS{mi_aqos  }};                       \n    assign M_AXI_ARUSER      = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_ARUSER_WIDTH] }};\n    \n    // W-channel MI handshakes\n    assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS];\n    assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY;\n    // Broadcast W transfer payload to all MI-slots\n    assign M_AXI_WLAST = {C_NUM_MASTER_SLOTS{mi_wlast}};\n    assign M_AXI_WUSER = {C_NUM_MASTER_SLOTS{mi_wuser}};\n    assign M_AXI_WDATA = {C_NUM_MASTER_SLOTS{mi_wdata}};\n    assign M_AXI_WSTRB = {C_NUM_MASTER_SLOTS{mi_wstrb}};\n    assign M_AXI_WID =   {C_NUM_MASTER_SLOTS{mi_wid}};\n    \n    // Broadcast R transfer payload to all SI-slots\n    assign S_AXI_RLAST = {C_NUM_SLAVE_SLOTS{si_rlast}};\n    assign S_AXI_RRESP = {C_NUM_SLAVE_SLOTS{si_rresp}};\n    assign S_AXI_RUSER = {C_NUM_SLAVE_SLOTS{si_ruser}};\n    assign S_AXI_RDATA = {C_NUM_SLAVE_SLOTS{si_rdata}};\n    assign S_AXI_RID =   {C_NUM_SLAVE_SLOTS{mi_aid}};\n    \n    // Broadcast B transfer payload to all SI-slots\n    assign S_AXI_BRESP = {C_NUM_SLAVE_SLOTS{si_bresp}};\n    assign S_AXI_BUSER = {C_NUM_SLAVE_SLOTS{si_buser}};\n    assign S_AXI_BID =   {C_NUM_SLAVE_SLOTS{mi_aid}};\n    \n    if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux\n      // SI WVALID mux.\n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_SLAVE_SLOTS),\n         .C_SEL_WIDTH   (P_NUM_SLAVE_SLOTS_LOG),\n         .C_DATA_WIDTH  (1)\n        ) si_w_valid_mux_inst \n        (\n         .S   (aa_grant_enc),\n         .A   (S_AXI_WVALID),\n         .O   (aa_wvalid),\n         .OE  (w_transfer_en)\n        ); \n      \n      // SI W-channel payload mux\n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_SLAVE_SLOTS),\n         .C_SEL_WIDTH   (P_NUM_SLAVE_SLOTS_LOG),\n         .C_DATA_WIDTH  (P_WMESG_WIDTH)\n        ) si_w_payload_mux_inst \n        (\n         .S   (aa_grant_enc),\n         .A   (si_wmesg),\n         .O   (mi_wmesg),\n         .OE  (1'b1)\n        ); \n        \n      for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_wmesg\n        assign si_wmesg[gen_si_slot*P_WMESG_WIDTH+:P_WMESG_WIDTH] = {  // Concatenate from MSB to LSB\n          ((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1'b0),\n          S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH],\n          S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8],\n          S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],\n          S_AXI_WLAST[gen_si_slot*1+:1]\n        };\n      end  // gen_wmesg\n      \n      assign mi_wlast = mi_wmesg[0];\n      assign mi_wdata = mi_wmesg[1 +: C_AXI_DATA_WIDTH];\n      assign mi_wstrb = mi_wmesg[1+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8];\n      assign mi_wuser = mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH];\n      assign mi_wid =   mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH];\n    end else begin : gen_no_wmux\n      assign aa_wvalid = w_transfer_en & S_AXI_WVALID;\n      assign mi_wlast  = S_AXI_WLAST;\n      assign mi_wdata  = S_AXI_WDATA;\n      assign mi_wstrb  = S_AXI_WSTRB;\n      assign mi_wuser  = S_AXI_WUSER;\n      assign mi_wid =    S_AXI_WID;\n    end  // gen_wmux\n    \n    // Receive RVALID from targeted MI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (1)\n      ) mi_rvalid_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_rvalid),\n       .O   (aa_rvalid),\n       .OE  (r_transfer_en)\n      ); \n      \n    // MI R-channel payload mux\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (P_RMESG_WIDTH)\n      ) mi_rmesg_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_rmesg),\n       .O   (aa_rmesg),\n       .OE  (1'b1)\n      ); \n      \n    axi_register_slice_v2_1_22_axic_register_slice #\n      (\n       .C_FAMILY (C_FAMILY),\n       .C_DATA_WIDTH (P_RMESG_WIDTH),\n       .C_REG_CONFIG (P_R_REG_CONFIG)\n       )\n      reg_slice_r\n      (\n       // System Signals\n       .ACLK(ACLK),\n       .ARESET(reset),\n\n       // Slave side\n       .S_PAYLOAD_DATA(aa_rmesg),\n       .S_VALID(aa_rvalid),\n       .S_READY(aa_rready),\n\n       // Master side\n       .M_PAYLOAD_DATA(sr_rmesg),\n       .M_VALID(sr_rvalid),\n       .M_READY(sr_rready)\n       );\n\n    assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID; \n    assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST; \n    assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP;\n    assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER;\n    assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA;\n    assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS];\n    \n    for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_rmesg\n      assign mi_rmesg[gen_mi_slot*P_RMESG_WIDTH+:P_RMESG_WIDTH] = {  // Concatenate from MSB to LSB\n        mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH],\n        mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],\n        mi_rresp[gen_mi_slot*2+:2],\n        mi_rlast[gen_mi_slot*1+:1]\n      };\n    end  // gen_rmesg\n    \n    assign si_rlast = sr_rmesg[0];\n    assign si_rresp = sr_rmesg[1 +: 2];\n    assign si_rdata = sr_rmesg[1+2 +: C_AXI_DATA_WIDTH];\n    assign si_ruser = sr_rmesg[1+2+C_AXI_DATA_WIDTH +: C_AXI_RUSER_WIDTH];\n      \n    // Receive BVALID from targeted MI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (1)\n      ) mi_bvalid_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_bvalid),\n       .O   (aa_bvalid),\n       .OE  (b_transfer_en)\n      ); \n      \n    // MI B-channel payload mux\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (P_BMESG_WIDTH)\n      ) mi_bmesg_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_bmesg),\n       .O   (si_bmesg),\n       .OE  (1'b1)\n      ); \n      \n    assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID; \n    assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP;\n    assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER;\n    assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS];\n    \n    for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_bmesg\n      assign mi_bmesg[gen_mi_slot*P_BMESG_WIDTH+:P_BMESG_WIDTH] = {  // Concatenate from MSB to LSB\n        mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH],\n        mi_bresp[gen_mi_slot*2+:2]\n      };\n    end  // gen_bmesg\n    \n    assign si_bresp = si_bmesg[0 +: 2];\n    assign si_buser = si_bmesg[2 +: C_AXI_BUSER_WIDTH];\n    \n    if (C_DEBUG) begin : gen_debug_trans_seq\n      // DEBUG WRITE TRANSACTION SEQUENCE COUNTER\n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_aw_trans_seq_i <= 1;\n        end else begin\n          if (aa_awvalid && aa_awready) begin\n            debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1;\n          end\n        end\n      end\n  \n      // DEBUG READ TRANSACTION SEQUENCE COUNTER\n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_ar_trans_seq_i <= 1;\n        end else begin\n          if (aa_arvalid && aa_arready) begin\n            debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1;\n          end\n        end\n      end\n      \n      // DEBUG WRITE BEAT COUNTER \n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_w_beat_cnt_i <= 0;\n        end else if (aa_wready & aa_wvalid) begin\n          if (mi_wlast) begin\n            debug_w_beat_cnt_i <= 0;\n          end else begin\n            debug_w_beat_cnt_i <= debug_w_beat_cnt_i + 1;\n          end\n        end\n      end  // Clocked process\n    \n      // DEBUG READ BEAT COUNTER \n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_r_beat_cnt_i <= 0;\n        end else if (sr_rready & sr_rvalid) begin\n          if (si_rlast) begin\n            debug_r_beat_cnt_i <= 0;\n          end else begin\n            debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;\n          end\n        end\n      end  // Clocked process\n    \n    end  // gen_debug_trans_seq\n\n    if (C_RANGE_CHECK) begin : gen_decerr\n      // Highest MI-slot (index C_NUM_MASTER_SLOTS) is the error handler\n      axi_crossbar_v2_1_23_decerr_slave #\n        (\n         .C_AXI_ID_WIDTH                 (1),\n         .C_AXI_DATA_WIDTH               (C_AXI_DATA_WIDTH),\n         .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),\n         .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),\n         .C_AXI_PROTOCOL                 (C_AXI_PROTOCOL),\n         .C_RESP                         (P_DECERR) \n        )\n        decerr_slave_inst\n          (\n           .S_AXI_ACLK (ACLK),\n           .S_AXI_ARESET (reset),\n           .S_AXI_AWID (1'b0),\n           .S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_WLAST (mi_wlast),\n           .S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_BID (),\n           .S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]),\n           .S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]),\n           .S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_ARID (1'b0),\n           .S_AXI_ARLEN (mi_alen),\n           .S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RID (),\n           .S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),\n           .S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]),\n           .S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]),\n           .S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS])\n         );\n    end  // gen_decerr\n\n  endgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: crossbar.v\n//\n// Description: \n//   This module is a M-master to N-slave AXI axi_crossbar_v2_1_23_crossbar switch.\n//   The interface of this module consists of a vectored slave and master interface\n//     in which all slots are sized and synchronized to the native width and clock \n//     of the interconnect.\n//   The SAMD axi_crossbar_v2_1_23_crossbar supports only AXI4 and AXI3 protocols.\n//   All width, clock and protocol conversions are done outside this block, as are\n//     any pipeline registers or data FIFOs.\n//   This module contains all arbitration, decoders and channel multiplexing logic.\n//     It also contains the diagnostic registers and control interface.\n//\n//-----------------------------------------------------------------------------\n//\n// Structure:\n//    crossbar\n//      si_transactor\n//        addr_decoder\n//          comparator_static\n//        mux_enc\n//        axic_srl_fifo\n//        arbiter_resp\n//      splitter\n//      wdata_router\n//        axic_reg_srl_fifo\n//      wdata_mux\n//        axic_reg_srl_fifo\n//        mux_enc\n//      addr_decoder\n//        comparator_static\n//      axic_srl_fifo\n//      axi_register_slice\n//      addr_arbiter\n//        mux_enc\n//      decerr_slave\n//      \n//-----------------------------------------------------------------------------\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_crossbar #\n  (\n   parameter         C_FAMILY                       = \"none\", \n   parameter integer C_NUM_SLAVE_SLOTS              =   1, \n   parameter integer C_NUM_MASTER_SLOTS             =   1, \n   parameter integer C_NUM_ADDR_RANGES              = 1,\n   parameter integer C_AXI_ID_WIDTH                   = 1, \n   parameter integer C_AXI_ADDR_WIDTH                 = 32, \n   parameter integer C_AXI_DATA_WIDTH = 32, \n   parameter integer C_AXI_PROTOCOL           = 0, \n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}}, \n   parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},\n   parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}}, \n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 1,\n   parameter integer C_AXI_ARUSER_WIDTH = 1,\n   parameter integer C_AXI_WUSER_WIDTH = 1,\n   parameter integer C_AXI_RUSER_WIDTH = 1,\n   parameter integer C_AXI_BUSER_WIDTH = 1,\n   parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE           = {C_NUM_SLAVE_SLOTS{1'b1}}, \n   parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ            = {C_NUM_SLAVE_SLOTS{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE           = {C_NUM_MASTER_SLOTS{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ            = {C_NUM_MASTER_SLOTS{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1'b1}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1'b1}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD                 = {C_NUM_SLAVE_SLOTS{32'h00000000}}, \n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE         = {C_NUM_SLAVE_SLOTS{32'h00000001}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE          = {C_NUM_SLAVE_SLOTS{32'h00000001}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING            = {C_NUM_MASTER_SLOTS{32'h00000001}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING            = {C_NUM_MASTER_SLOTS{32'h00000001}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY             = {C_NUM_SLAVE_SLOTS{32'h00000000}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE                   = {C_NUM_MASTER_SLOTS{32'h00000000}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE            = {C_NUM_MASTER_SLOTS{32'h00000000}},\n   parameter integer C_RANGE_CHECK                    = 0,\n   parameter integer C_ADDR_DECODE                    = 0,\n   parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_W_ISSUE_WIDTH  = {C_NUM_MASTER_SLOTS+1{32'h00000000}},\n   parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_R_ISSUE_WIDTH  = {C_NUM_MASTER_SLOTS+1{32'h00000000}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_W_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_R_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}},\n   parameter integer C_DEBUG              = 1\n   )\n  (\n   // Global Signals\n   input  wire                                                    ACLK,\n   input  wire                                                    ARESETN,\n   // Slave Interface Write Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_AWID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           S_AXI_AWADDR,\n   input  wire [C_NUM_SLAVE_SLOTS*8-1:0]                          S_AXI_AWLEN,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_AWSIZE,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_AWBURST,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_AWLOCK,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWCACHE,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_AWPROT,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWREGION,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWQOS,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0]         S_AXI_AWUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_AWVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_AWREADY,\n   // Slave Interface Write Data Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_WID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]     S_AXI_WDATA,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0]   S_AXI_WSTRB,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WLAST,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0]          S_AXI_WUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WREADY,\n   // Slave Interface Write Response Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_BID,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_BRESP,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_BVALID,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_BREADY,\n   // Slave Interface Read Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_ARID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           S_AXI_ARADDR,\n   input  wire [C_NUM_SLAVE_SLOTS*8-1:0]                          S_AXI_ARLEN,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_ARSIZE,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_ARBURST,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_ARLOCK,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARCACHE,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_ARPROT,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARREGION,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARQOS,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0]         S_AXI_ARUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_ARVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_ARREADY,\n   // Slave Interface Read Data Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_RID,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]     S_AXI_RDATA,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_RRESP,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RLAST,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0]          S_AXI_RUSER,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RVALID,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RREADY,\n   // Master Interface Write Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_AWID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          M_AXI_AWADDR,\n   output wire [C_NUM_MASTER_SLOTS*8-1:0]                         M_AXI_AWLEN,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_AWSIZE,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_AWBURST,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_AWLOCK,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWCACHE,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_AWPROT,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWREGION,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWQOS,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0]        M_AXI_AWUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_AWVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_AWREADY,\n   // Master Interface Write Data Ports\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_WID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]    M_AXI_WDATA,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0]  M_AXI_WSTRB,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WLAST,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0]         M_AXI_WUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WREADY,\n   // Master Interface Write Response Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_BID,\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_BRESP,\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0]         M_AXI_BUSER,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_BVALID,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_BREADY,\n   // Master Interface Read Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_ARID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          M_AXI_ARADDR,\n   output wire [C_NUM_MASTER_SLOTS*8-1:0]                         M_AXI_ARLEN,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_ARSIZE,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_ARBURST,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_ARLOCK,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARCACHE,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_ARPROT,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARREGION,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARQOS,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0]        M_AXI_ARUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_ARVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_ARREADY,\n   // Master Interface Read Data Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_RID,\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]    M_AXI_RDATA,\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_RRESP,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RLAST,\n   input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0]         M_AXI_RUSER,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RVALID,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RREADY\n   );\n   \n  localparam integer  P_AXI4 = 0;\n  localparam integer  P_AXI3 = 1;\n  localparam integer  P_AXILITE = 2;\n  localparam integer P_WRITE = 0;\n  localparam integer P_READ = 1;\n  localparam integer P_NUM_MASTER_SLOTS_LOG = f_ceil_log2(C_NUM_MASTER_SLOTS);\n  localparam integer P_NUM_SLAVE_SLOTS_LOG = f_ceil_log2((C_NUM_SLAVE_SLOTS>1) ? C_NUM_SLAVE_SLOTS : 2);\n  localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1;\n  localparam integer P_ST_AWMESG_WIDTH = 2+4+4 + C_AXI_AWUSER_WIDTH;\n  localparam integer P_AA_AWMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_AWMESG_WIDTH;\n  localparam integer P_ST_ARMESG_WIDTH = 2+4+4 + C_AXI_ARUSER_WIDTH;\n  localparam integer P_AA_ARMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_ARMESG_WIDTH;\n  localparam integer P_ST_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH;\n  localparam integer P_ST_RMESG_WIDTH = 2 + C_AXI_RUSER_WIDTH + C_AXI_DATA_WIDTH;\n  localparam integer P_WR_WMESG_WIDTH = C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH;\n  localparam [31:0] P_BYPASS  = 32'h00000000;\n  localparam [31:0] P_FWD_REV = 32'h00000001;\n  localparam [31:0] P_SIMPLE  = 32'h00000007;\n  localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_READ = {1'b1, C_M_AXI_SUPPORTS_READ[0+:C_NUM_MASTER_SLOTS]};\n  localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_WRITE = {1'b1, C_M_AXI_SUPPORTS_WRITE[0+:C_NUM_MASTER_SLOTS]};\n  localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_WRITE_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]};\n  localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_READ_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]};\n  localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_WRITE_CONNECTIVITY = f_si_write_connectivity(0);\n  localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_READ_CONNECTIVITY = f_si_read_connectivity(0);\n  localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_ISSUING = {32'h00000001, C_M_AXI_READ_ISSUING[0+:C_NUM_MASTER_SLOTS*32]};\n  localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_ISSUING = {32'h00000001, C_M_AXI_WRITE_ISSUING[0+:C_NUM_MASTER_SLOTS*32]};\n  localparam P_DECERR = 2'b11;\n\n  //---------------------------------------------------------------------------\n  // Functions\n  //---------------------------------------------------------------------------\n  // Ceiling of log2(x)\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  // Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value\n  //   only for end-point SI-slots\n  function [C_AXI_ID_WIDTH-1:0] f_extend_ID\n    (\n     input [C_AXI_ID_WIDTH-1:0] s_id,\n     input integer slot\n     );\n    begin\n      f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH]));\n    end\n  endfunction\n\n  // Write connectivity array transposed\n  function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_write_connectivity\n    (\n      input integer null_arg\n     );\n    integer si_slot;\n    integer mi_slot;\n    reg  [C_NUM_SLAVE_SLOTS*32-1:0]  result;\n    begin\n      result = {C_NUM_SLAVE_SLOTS*32{1'b1}};\n      for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin\n        for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin\n          result[si_slot*32+mi_slot] = C_M_AXI_WRITE_CONNECTIVITY[mi_slot*32+si_slot];\n        end\n      end\n    f_si_write_connectivity = result;\n    end\n  endfunction\n\n  // Read connectivity array transposed\n  function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_read_connectivity\n    (\n      input integer null_arg\n     );\n    integer si_slot;\n    integer mi_slot;\n    reg  [C_NUM_SLAVE_SLOTS*32-1:0]  result;\n    begin\n      result = {C_NUM_SLAVE_SLOTS*32{1'b1}};\n      for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin\n        for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin\n          result[si_slot*32+mi_slot] = C_M_AXI_READ_CONNECTIVITY[mi_slot*32+si_slot];\n        end\n      end\n    f_si_read_connectivity = result;\n    end\n  endfunction\n\n  genvar gen_si_slot;\n  genvar gen_mi_slot;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0]                  si_st_awmesg          ;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0]                  st_tmp_awmesg         ;\n  wire [C_NUM_SLAVE_SLOTS*P_AA_AWMESG_WIDTH-1:0]                  tmp_aa_awmesg         ;\n  wire [P_AA_AWMESG_WIDTH-1:0]                                    aa_mi_awmesg          ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]                     st_aa_awid            ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]                   st_aa_awaddr          ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                                  st_aa_awlen           ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                                  st_aa_awsize          ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                                  st_aa_awlock          ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                                  st_aa_awprot          ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                                  st_aa_awregion        ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                                  st_aa_awerror         ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_aa_awtarget_hot    ;\n  wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0]         st_aa_awtarget_enc    ;\n  wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0]                              aa_wm_awgrant_enc     ;\n  wire [(C_NUM_MASTER_SLOTS+1)-1:0]                               aa_mi_awtarget_hot    ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_aa_awvalid_qual    ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_ss_awvalid         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_ss_awready         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  ss_wr_awvalid         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  ss_wr_awready         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  ss_aa_awvalid         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  ss_aa_awready         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             sa_wm_awvalid         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             sa_wm_awready         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_awvalid            ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_awready            ;\n  wire                                                            aa_sa_awvalid         ;\n  wire                                                            aa_sa_awready         ;\n  wire                                                            aa_mi_arready         ;\n  wire                                                            mi_awvalid_en         ;\n  wire                                                            sa_wm_awvalid_en      ;\n  wire                                                            sa_wm_awready_mux     ;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0]                  si_st_armesg          ;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0]                  st_tmp_armesg         ;\n  wire [C_NUM_SLAVE_SLOTS*P_AA_ARMESG_WIDTH-1:0]                  tmp_aa_armesg         ;\n  wire [P_AA_ARMESG_WIDTH-1:0]                                    aa_mi_armesg          ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]                     st_aa_arid            ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]                   st_aa_araddr          ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                                  st_aa_arlen           ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                                  st_aa_arsize          ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                                  st_aa_arlock          ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                                  st_aa_arprot          ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                                  st_aa_arregion        ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                                  st_aa_arerror         ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_aa_artarget_hot    ;\n  wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0]         st_aa_artarget_enc    ;\n  wire [(C_NUM_MASTER_SLOTS+1)-1:0]                               aa_mi_artarget_hot    ;\n  wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0]                              aa_mi_argrant_enc     ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_aa_arvalid_qual    ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_aa_arvalid         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_aa_arready         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_arvalid            ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_arready            ;\n  wire                                                            aa_mi_arvalid         ;\n  wire                                                            mi_awready_mux        ;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_BMESG_WIDTH-1:0]                   st_si_bmesg           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*P_ST_BMESG_WIDTH-1:0]              st_mr_bmesg           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                st_mr_bid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*2-1:0]                             st_mr_bresp           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0]             st_mr_buser           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_bvalid          ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_bready          ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_tmp_bready         ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_tmp_bid_target     ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0]             tmp_mr_bid_target     ;\n  wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0]         debug_bid_target_i    ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             bid_match             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                mi_bid                ;\n  wire [(C_NUM_MASTER_SLOTS+1)*2-1:0]                             mi_bresp              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0]             mi_buser              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_bvalid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_bready             ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             bready_carry          ;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_RMESG_WIDTH-1:0]                   st_si_rmesg           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*P_ST_RMESG_WIDTH-1:0]              st_mr_rmesg           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                st_mr_rid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0]     st_mr_rdata           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0]             st_mr_ruser           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_rlast           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*2-1:0]                             st_mr_rresp           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_rvalid          ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_rready          ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_tmp_rready         ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_tmp_rid_target     ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0]             tmp_mr_rid_target     ;\n  wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0]         debug_rid_target_i    ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             rid_match             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                mi_rid                ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0]          mi_rdata              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0]             mi_ruser              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_rlast              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*2-1:0]                             mi_rresp              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_rvalid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_rready             ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             rready_carry          ;\n  wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0]                   si_wr_wmesg           ;\n  wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0]                   wr_wm_wmesg           ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  wr_wm_wlast           ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             wr_tmp_wvalid         ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             wr_tmp_wready         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0]             tmp_wm_wvalid         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0]             tmp_wm_wready         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*P_WR_WMESG_WIDTH-1:0]              wm_mr_wmesg              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0]          wm_mr_wdata              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0]        wm_mr_wstrb              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                wm_mr_wid              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0]             wm_mr_wuser              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             wm_mr_wlast              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             wm_mr_wvalid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             wm_mr_wready             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0]          mi_wdata              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0]        mi_wstrb              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0]             mi_wuser              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                mi_wid              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_wlast              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_wvalid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_wready             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             w_cmd_push            ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             w_cmd_pop             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             r_cmd_push            ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             r_cmd_pop             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_awmaxissuing      ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_armaxissuing      ;\n  reg  [(C_NUM_MASTER_SLOTS+1)*8-1:0]                             w_issuing_cnt        ;\n  reg  [(C_NUM_MASTER_SLOTS+1)*8-1:0]                             r_issuing_cnt        ;\n  reg  [8-1:0]                                                    debug_aw_trans_seq_i    ;\n  reg  [8-1:0]                                                    debug_ar_trans_seq_i    ;\n  wire [(C_NUM_MASTER_SLOTS+1)*8-1:0]                             debug_w_trans_seq_i     ;\n  reg  [(C_NUM_MASTER_SLOTS+1)*8-1:0]                             debug_w_beat_cnt_i      ;\n\n  reg aresetn_d = 1'b0; // Reset delay register\n  always @(posedge ACLK) begin\n    if (~ARESETN) begin\n      aresetn_d <= 1'b0;\n    end else begin\n      aresetn_d <= ARESETN;\n    end\n  end\n  wire reset;\n  assign reset = ~aresetn_d;\n\n  generate\n    for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_slave_slots\n      if (C_S_AXI_SUPPORTS_READ[gen_si_slot]) begin : gen_si_read\n        axi_crossbar_v2_1_23_si_transactor #  // \"ST\": SI Transactor (read channel)\n          (\n           .C_FAMILY                (C_FAMILY),\n           .C_SI                    (gen_si_slot),\n           .C_DIR                   (P_READ),\n           .C_NUM_ADDR_RANGES       (C_NUM_ADDR_RANGES),\n           .C_NUM_M                 (C_NUM_MASTER_SLOTS),\n           .C_NUM_M_LOG             (P_NUM_MASTER_SLOTS_LOG),\n           .C_ACCEPTANCE            (C_S_AXI_READ_ACCEPTANCE[gen_si_slot*32+:32]),\n           .C_ACCEPTANCE_LOG        (C_R_ACCEPT_WIDTH[gen_si_slot*32+:32]),\n           .C_ID_WIDTH              (C_AXI_ID_WIDTH),\n           .C_THREAD_ID_WIDTH       (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]),\n           .C_ADDR_WIDTH            (C_AXI_ADDR_WIDTH),\n           .C_AMESG_WIDTH           (P_ST_ARMESG_WIDTH),\n           .C_RMESG_WIDTH           (P_ST_RMESG_WIDTH),\n           .C_BASE_ID               (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),\n           .C_HIGH_ID               (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),\n           .C_SINGLE_THREAD         (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]),\n           .C_BASE_ADDR             (C_M_AXI_BASE_ADDR),\n           .C_HIGH_ADDR             (C_M_AXI_HIGH_ADDR),\n           .C_TARGET_QUAL           (P_S_AXI_READ_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]),\n           .C_M_AXI_SECURE          (C_M_AXI_SECURE),\n           .C_RANGE_CHECK           (C_RANGE_CHECK),\n           .C_ADDR_DECODE           (C_ADDR_DECODE),\n           .C_ERR_MODE              (C_M_AXI_ERR_MODE),\n           .C_DEBUG                 (C_DEBUG)\n           )\n          si_transactor_ar\n            (\n             .ACLK                  (ACLK),\n             .ARESET                (reset),\n             .S_AID                 (f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)),\n             .S_AADDR               (S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),\n             .S_ALEN                (S_AXI_ARLEN[gen_si_slot*8+:8]),\n             .S_ASIZE               (S_AXI_ARSIZE[gen_si_slot*3+:3]),\n             .S_ABURST              (S_AXI_ARBURST[gen_si_slot*2+:2]),\n             .S_ALOCK               (S_AXI_ARLOCK[gen_si_slot*2+:2]),\n             .S_APROT               (S_AXI_ARPROT[gen_si_slot*3+:3]),\n//             .S_AREGION             (S_AXI_ARREGION[gen_si_slot*4+:4]),\n             .S_AMESG               (si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]),\n             .S_AVALID              (S_AXI_ARVALID[gen_si_slot]),\n             .S_AREADY              (S_AXI_ARREADY[gen_si_slot]),\n             .M_AID                 (st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n             .M_AADDR               (st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),\n             .M_ALEN                (st_aa_arlen[gen_si_slot*8+:8]),\n             .M_ASIZE               (st_aa_arsize[gen_si_slot*3+:3]),\n             .M_ALOCK               (st_aa_arlock[gen_si_slot*2+:2]),\n             .M_APROT               (st_aa_arprot[gen_si_slot*3+:3]),\n             .M_AREGION             (st_aa_arregion[gen_si_slot*4+:4]),\n             .M_AMESG               (st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]),\n             .M_ATARGET_HOT         (st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .M_ATARGET_ENC         (st_aa_artarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),\n             .M_AERROR              (st_aa_arerror[gen_si_slot*8+:8]),\n             .M_AVALID_QUAL         (st_aa_arvalid_qual[gen_si_slot]),\n             .M_AVALID              (st_aa_arvalid[gen_si_slot]),\n             .M_AREADY              (st_aa_arready[gen_si_slot]),\n             .S_RID                 (S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n             .S_RMESG               (st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH]),\n             .S_RLAST               (S_AXI_RLAST[gen_si_slot]),\n             .S_RVALID              (S_AXI_RVALID[gen_si_slot]),\n             .S_RREADY              (S_AXI_RREADY[gen_si_slot]),\n             .M_RID                 (st_mr_rid),\n             .M_RLAST               (st_mr_rlast),\n             .M_RMESG               (st_mr_rmesg),\n             .M_RVALID              (st_mr_rvalid),\n             .M_RREADY              (st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .M_RTARGET             (st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .DEBUG_A_TRANS_SEQ     (C_DEBUG ? debug_ar_trans_seq_i : 8'h0)\n             );\n        \n        assign si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH] = {\n          S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH],\n          S_AXI_ARQOS[gen_si_slot*4+:4],\n          S_AXI_ARCACHE[gen_si_slot*4+:4],\n          S_AXI_ARBURST[gen_si_slot*2+:2]\n          };\n        assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = {\n          st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH],\n          st_aa_arregion[gen_si_slot*4+:4],\n          st_aa_arprot[gen_si_slot*3+:3],\n          st_aa_arlock[gen_si_slot*2+:2],\n          st_aa_arsize[gen_si_slot*3+:3],\n          st_aa_arlen[gen_si_slot*8+:8],\n          st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH],\n          st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]\n          };\n        assign S_AXI_RRESP[gen_si_slot*2+:2] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:2];\n        assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2 +: C_AXI_RUSER_WIDTH];\n        assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2+C_AXI_RUSER_WIDTH +: C_AXI_DATA_WIDTH];\n      end else begin : gen_no_si_read\n        assign S_AXI_ARREADY[gen_si_slot] = 1'b0;\n        assign st_aa_arvalid[gen_si_slot] = 1'b0;\n        assign st_aa_arvalid_qual[gen_si_slot] = 1'b1;\n        assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = 0;\n        assign S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;\n        assign S_AXI_RRESP[gen_si_slot*2+:2] = 0;\n        assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = 0;\n        //assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0;\n        assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = {C_AXI_DATA_WIDTH/32{32'hDEC0_DE1C}};\n        assign S_AXI_RVALID[gen_si_slot] = 1'b0;\n        assign S_AXI_RLAST[gen_si_slot] = 1'b0;\n        assign st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;\n        assign st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;\n      end  // gen_si_read\n        \n      if (C_S_AXI_SUPPORTS_WRITE[gen_si_slot]) begin : gen_si_write\n        axi_crossbar_v2_1_23_si_transactor #  // \"ST\": SI Transactor (write channel)\n          (\n           .C_FAMILY                (C_FAMILY),\n           .C_SI                    (gen_si_slot),\n           .C_DIR                   (P_WRITE),\n           .C_NUM_ADDR_RANGES       (C_NUM_ADDR_RANGES),\n           .C_NUM_M                 (C_NUM_MASTER_SLOTS),\n           .C_NUM_M_LOG             (P_NUM_MASTER_SLOTS_LOG),\n           .C_ACCEPTANCE            (C_S_AXI_WRITE_ACCEPTANCE[gen_si_slot*32+:32]),\n           .C_ACCEPTANCE_LOG        (C_W_ACCEPT_WIDTH[gen_si_slot*32+:32]),\n           .C_ID_WIDTH              (C_AXI_ID_WIDTH),\n           .C_THREAD_ID_WIDTH       (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]),\n           .C_ADDR_WIDTH            (C_AXI_ADDR_WIDTH),\n           .C_AMESG_WIDTH           (P_ST_AWMESG_WIDTH),\n           .C_RMESG_WIDTH           (P_ST_BMESG_WIDTH),\n           .C_BASE_ID               (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),\n           .C_HIGH_ID               (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),\n           .C_SINGLE_THREAD         (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]),\n           .C_BASE_ADDR             (C_M_AXI_BASE_ADDR),\n           .C_HIGH_ADDR             (C_M_AXI_HIGH_ADDR),\n           .C_TARGET_QUAL           (P_S_AXI_WRITE_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]),\n           .C_M_AXI_SECURE          (C_M_AXI_SECURE),\n           .C_RANGE_CHECK           (C_RANGE_CHECK),\n           .C_ADDR_DECODE           (C_ADDR_DECODE),\n           .C_ERR_MODE              (C_M_AXI_ERR_MODE),\n           .C_DEBUG                 (C_DEBUG)\n           )\n          si_transactor_aw\n            (\n             .ACLK                  (ACLK),\n             .ARESET                (reset),\n             .S_AID                 (f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)),\n             .S_AADDR               (S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),\n             .S_ALEN                (S_AXI_AWLEN[gen_si_slot*8+:8]),\n             .S_ASIZE               (S_AXI_AWSIZE[gen_si_slot*3+:3]),\n             .S_ABURST              (S_AXI_AWBURST[gen_si_slot*2+:2]),\n             .S_ALOCK               (S_AXI_AWLOCK[gen_si_slot*2+:2]),\n             .S_APROT               (S_AXI_AWPROT[gen_si_slot*3+:3]),\n//             .S_AREGION             (S_AXI_AWREGION[gen_si_slot*4+:4]),\n             .S_AMESG               (si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]),\n             .S_AVALID              (S_AXI_AWVALID[gen_si_slot]),\n             .S_AREADY              (S_AXI_AWREADY[gen_si_slot]),\n             .M_AID                 (st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n             .M_AADDR               (st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),\n             .M_ALEN                (st_aa_awlen[gen_si_slot*8+:8]),\n             .M_ASIZE               (st_aa_awsize[gen_si_slot*3+:3]),\n             .M_ALOCK               (st_aa_awlock[gen_si_slot*2+:2]),\n             .M_APROT               (st_aa_awprot[gen_si_slot*3+:3]),\n             .M_AREGION             (st_aa_awregion[gen_si_slot*4+:4]),\n             .M_AMESG               (st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]),\n             .M_ATARGET_HOT         (st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .M_ATARGET_ENC         (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),\n             .M_AERROR              (st_aa_awerror[gen_si_slot*8+:8]),\n             .M_AVALID_QUAL         (st_aa_awvalid_qual[gen_si_slot]),\n             .M_AVALID              (st_ss_awvalid[gen_si_slot]),\n             .M_AREADY              (st_ss_awready[gen_si_slot]),\n             .S_RID                 (S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n             .S_RMESG               (st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH]),\n             .S_RLAST               (),\n             .S_RVALID              (S_AXI_BVALID[gen_si_slot]),\n             .S_RREADY              (S_AXI_BREADY[gen_si_slot]),\n             .M_RID                 (st_mr_bid),\n             .M_RLAST               ({(C_NUM_MASTER_SLOTS+1){1'b1}}),\n             .M_RMESG               (st_mr_bmesg),\n             .M_RVALID              (st_mr_bvalid),\n             .M_RREADY              (st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .M_RTARGET             (st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .DEBUG_A_TRANS_SEQ     (C_DEBUG ? debug_aw_trans_seq_i : 8'h0)\n             );\n        \n        // Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.\n        assign si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH] = {\n          S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH],\n          S_AXI_AWQOS[gen_si_slot*4+:4],\n          S_AXI_AWCACHE[gen_si_slot*4+:4],\n          S_AXI_AWBURST[gen_si_slot*2+:2]\n          };\n        assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = {\n          st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH],\n          st_aa_awregion[gen_si_slot*4+:4],\n          st_aa_awprot[gen_si_slot*3+:3],\n          st_aa_awlock[gen_si_slot*2+:2],\n          st_aa_awsize[gen_si_slot*3+:3],\n          st_aa_awlen[gen_si_slot*8+:8],\n          st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH],\n          st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]\n          };\n        assign S_AXI_BRESP[gen_si_slot*2+:2] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:2];\n        assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+2 +: C_AXI_BUSER_WIDTH];\n                       \n        // AW SI-transactor transfer completes upon completion of both W-router address acceptance (command push) and AW arbitration\n        axi_crossbar_v2_1_23_splitter #  // \"SS\": Splitter from SI-Transactor (write channel)\n          (\n            .C_NUM_M                (2)\n          )\n          splitter_aw_si\n          (\n             .ACLK                  (ACLK),\n             .ARESET                (reset),\n             .S_VALID              (st_ss_awvalid[gen_si_slot]),\n             .S_READY              (st_ss_awready[gen_si_slot]),\n             .M_VALID              ({ss_wr_awvalid[gen_si_slot], ss_aa_awvalid[gen_si_slot]}),\n             .M_READY              ({ss_wr_awready[gen_si_slot], ss_aa_awready[gen_si_slot]})\n          );\n      \n        axi_crossbar_v2_1_23_wdata_router #  // \"WR\": Write data Router\n          (\n           .C_FAMILY                   (C_FAMILY),\n           .C_NUM_MASTER_SLOTS         (C_NUM_MASTER_SLOTS+1),\n           .C_SELECT_WIDTH             (P_NUM_MASTER_SLOTS_LOG+1),\n           .C_WMESG_WIDTH               (P_WR_WMESG_WIDTH),\n           .C_FIFO_DEPTH_LOG           (C_W_ACCEPT_WIDTH[gen_si_slot*32+:6])\n           )\n          wdata_router_w\n            (\n             .ACLK    (ACLK),\n             .ARESET  (reset),\n             // Write transfer input from the current SI-slot\n             .S_WMESG  (si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]),\n             .S_WLAST  (S_AXI_WLAST[gen_si_slot]),\n             .S_WVALID (S_AXI_WVALID[gen_si_slot]),\n             .S_WREADY (S_AXI_WREADY[gen_si_slot]),\n             // Vector of write transfer outputs to each MI-slot's W-mux\n             .M_WMESG  (wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH]),\n             .M_WLAST  (wr_wm_wlast[gen_si_slot]),\n             .M_WVALID (wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .M_WREADY (wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             // AW command push from local SI-slot\n             .S_ASELECT (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),  // Target MI-slot\n             .S_AVALID  (ss_wr_awvalid[gen_si_slot]),\n             .S_AREADY  (ss_wr_awready[gen_si_slot])\n             );\n             \n        assign si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH] = {\n          ((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1'b0),\n          S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH],\n          S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8],\n          S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]\n        };        \n      end else begin : gen_no_si_write\n        assign S_AXI_AWREADY[gen_si_slot] = 1'b0;\n        assign ss_aa_awvalid[gen_si_slot] = 1'b0;\n        assign st_aa_awvalid_qual[gen_si_slot] = 1'b1;\n        assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = 0;\n        assign S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;\n        assign S_AXI_BRESP[gen_si_slot*2+:2] = 0;\n        assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = 0;\n        assign S_AXI_BVALID[gen_si_slot] = 1'b0;\n        assign st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;\n        assign S_AXI_WREADY[gen_si_slot] = 1'b0;\n        assign wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH] = 0;\n        assign wr_wm_wlast[gen_si_slot] = 1'b0;\n        assign wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;\n        assign st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;\n      end  // gen_si_write\n    end  // gen_slave_slots\n    \n    for (gen_mi_slot=0; gen_mi_slot<C_NUM_MASTER_SLOTS+1; gen_mi_slot=gen_mi_slot+1) begin : gen_master_slots\n      if (P_M_AXI_SUPPORTS_READ[gen_mi_slot]) begin : gen_mi_read\n        if (C_NUM_SLAVE_SLOTS>1) begin : gen_rid_decoder\n          axi_crossbar_v2_1_23_addr_decoder #\n            (\n              .C_FAMILY          (C_FAMILY),\n              .C_NUM_TARGETS     (C_NUM_SLAVE_SLOTS),\n              .C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG),\n              .C_NUM_RANGES      (1),\n              .C_ADDR_WIDTH      (C_AXI_ID_WIDTH),\n              .C_TARGET_ENC      (C_DEBUG),\n              .C_TARGET_HOT      (1),\n              .C_REGION_ENC      (0),\n              .C_BASE_ADDR       (C_S_AXI_BASE_ID),\n              .C_HIGH_ADDR       (C_S_AXI_HIGH_ID),\n              .C_TARGET_QUAL     (P_M_AXI_READ_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]),\n              .C_RESOLUTION      (0)\n            ) \n            rid_decoder_inst \n            (\n              .ADDR             (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),        \n              .TARGET_HOT       (tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),  \n              .TARGET_ENC       (debug_rid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]),  \n              .MATCH            (rid_match[gen_mi_slot]),       \n              .REGION           ()      \n            );\n        end else begin : gen_no_rid_decoder\n          assign tmp_mr_rid_target[gen_mi_slot] = 1'b1;  // All response transfers route to solo SI-slot.\n          assign rid_match[gen_mi_slot] = 1'b1;\n        end\n        \n        assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = {\n          st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],\n          st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH], \n          st_mr_rresp[gen_mi_slot*2+:2]\n          }; \n      end else begin : gen_no_mi_read\n        assign tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;\n        assign rid_match[gen_mi_slot] = 1'b0;\n        assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = 0;\n      end  // gen_mi_read\n      \n      if (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot]) begin : gen_mi_write\n        if (C_NUM_SLAVE_SLOTS>1) begin : gen_bid_decoder\n          axi_crossbar_v2_1_23_addr_decoder #\n            (\n              .C_FAMILY          (C_FAMILY),\n              .C_NUM_TARGETS     (C_NUM_SLAVE_SLOTS),\n              .C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG),\n              .C_NUM_RANGES      (1),\n              .C_ADDR_WIDTH      (C_AXI_ID_WIDTH),\n              .C_TARGET_ENC      (C_DEBUG),\n              .C_TARGET_HOT      (1),\n              .C_REGION_ENC      (0),\n              .C_BASE_ADDR       (C_S_AXI_BASE_ID),\n              .C_HIGH_ADDR       (C_S_AXI_HIGH_ID),\n              .C_TARGET_QUAL     (P_M_AXI_WRITE_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]),\n              .C_RESOLUTION      (0)\n            ) \n            bid_decoder_inst \n            (\n              .ADDR             (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),        \n              .TARGET_HOT       (tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),  \n              .TARGET_ENC       (debug_bid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]),  \n              .MATCH            (bid_match[gen_mi_slot]),       \n              .REGION           ()      \n            );\n        end else begin : gen_no_bid_decoder\n          assign tmp_mr_bid_target[gen_mi_slot] = 1'b1;  // All response transfers route to solo SI-slot.\n          assign bid_match[gen_mi_slot] = 1'b1;\n        end\n      \n        axi_crossbar_v2_1_23_wdata_mux #  // \"WM\": Write data Mux, per MI-slot (incl error-handler)\n          (\n           .C_FAMILY                   (C_FAMILY),\n           .C_NUM_SLAVE_SLOTS         (C_NUM_SLAVE_SLOTS),\n           .C_SELECT_WIDTH     (P_NUM_SLAVE_SLOTS_LOG),\n           .C_WMESG_WIDTH               (P_WR_WMESG_WIDTH),\n           .C_FIFO_DEPTH_LOG           (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6])\n           )\n          wdata_mux_w\n            (\n             .ACLK    (ACLK),\n             .ARESET  (reset),\n             // Vector of write transfer inputs from each SI-slot's W-router\n             .S_WMESG  (wr_wm_wmesg),\n             .S_WLAST  (wr_wm_wlast),\n             .S_WVALID (tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),\n             .S_WREADY (tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),\n             // Write transfer output to the current MI-slot\n             .M_WMESG  (wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]),\n             .M_WLAST  (wm_mr_wlast[gen_mi_slot]),\n             .M_WVALID (wm_mr_wvalid[gen_mi_slot]),\n             .M_WREADY (wm_mr_wready[gen_mi_slot]),\n             // AW command push from AW arbiter output\n             .S_ASELECT (aa_wm_awgrant_enc),  // SI-slot selected by arbiter\n             .S_AVALID  (sa_wm_awvalid[gen_mi_slot]),\n             .S_AREADY  (sa_wm_awready[gen_mi_slot])\n             );\n             \n        if (C_DEBUG) begin : gen_debug_w\n          // DEBUG WRITE BEAT COUNTER\n          always @(posedge ACLK) begin\n            if (reset) begin\n              debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0;\n            end else begin\n              if (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot]) begin\n                if (mi_wlast[gen_mi_slot]) begin\n                  debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0;\n                end else begin\n                  debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= debug_w_beat_cnt_i[gen_mi_slot*8+:8] + 1;\n                end\n              end\n            end\n          end  // clocked process\n  \n          // DEBUG W-CHANNEL TRANSACTION SEQUENCE QUEUE\n          axi_data_fifo_v2_1_21_axic_srl_fifo #\n            (\n             .C_FAMILY          (C_FAMILY),\n             .C_FIFO_WIDTH      (8),\n             .C_FIFO_DEPTH_LOG  (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]),\n             .C_USE_FULL        (0)\n             )\n            debug_w_seq_fifo\n              (\n               .ACLK    (ACLK),\n               .ARESET  (reset),\n               .S_MESG  (debug_aw_trans_seq_i),\n               .S_VALID (sa_wm_awvalid[gen_mi_slot]),\n               .S_READY (),\n               .M_MESG  (debug_w_trans_seq_i[gen_mi_slot*8+:8]),\n               .M_VALID (),\n               .M_READY (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot] & mi_wlast[gen_mi_slot])\n              );\n        end  // gen_debug_w\n             \n        assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH +: C_AXI_DATA_WIDTH];\n        assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8];\n        assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH];\n        assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+(C_AXI_DATA_WIDTH/8)+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH];\n        assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = {\n          st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH],\n          st_mr_bresp[gen_mi_slot*2+:2]\n          }; \n      end else begin : gen_no_mi_write\n        assign tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;\n        assign bid_match[gen_mi_slot] = 1'b0;\n        assign wm_mr_wvalid[gen_mi_slot] = 0;\n        assign wm_mr_wlast[gen_mi_slot] = 0;\n        assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0;\n        assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = 0;\n        assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = 0;\n        assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;\n        assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = 0;\n        assign tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;\n        assign sa_wm_awready[gen_mi_slot] = 0;\n      end  // gen_mi_write\n      \n      for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_trans_si\n        // Transpose handshakes from W-router (SxM) to W-mux (MxS).\n        assign tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot] = wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot];\n        assign wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];\n        // Transpose response enables from ID decoders (MxS) to si_transactors (SxM).\n        assign st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];\n        assign st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];\n      end  // gen_trans_si\n      \n      assign bready_carry[gen_mi_slot] =  st_tmp_bready[gen_mi_slot];\n      assign rready_carry[gen_mi_slot] =  st_tmp_rready[gen_mi_slot];\n      for (gen_si_slot=1; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_resp_carry_si\n        assign bready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] =  // Generate M_BREADY if ...\n          bready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] |  // For any SI-slot (OR carry-chain across all SI-slots), ...\n          st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot];  // The write SI transactor indicates BREADY for that MI-slot.\n        assign rready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] =  // Generate M_RREADY if ...\n          rready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] |  // For any SI-slot (OR carry-chain across all SI-slots), ...\n          st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot];  // The write SI transactor indicates RREADY for that MI-slot.\n      end  // gen_resp_carry_si\n           \n      assign w_cmd_push[gen_mi_slot] = mi_awvalid[gen_mi_slot] && mi_awready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot];\n      assign r_cmd_push[gen_mi_slot] = mi_arvalid[gen_mi_slot] && mi_arready[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot];\n      assign w_cmd_pop[gen_mi_slot] = st_mr_bvalid[gen_mi_slot] && st_mr_bready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot];\n      assign r_cmd_pop[gen_mi_slot] = st_mr_rvalid[gen_mi_slot] && st_mr_rready[gen_mi_slot] && st_mr_rlast[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot];\n      // Disqualify arbitration of SI-slot if targeted MI-slot has reached its issuing limit.\n      assign mi_awmaxissuing[gen_mi_slot] = (w_issuing_cnt[gen_mi_slot*8 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] == \n          P_M_AXI_WRITE_ISSUING[gen_mi_slot*32 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~w_cmd_pop[gen_mi_slot];\n      assign mi_armaxissuing[gen_mi_slot] = (r_issuing_cnt[gen_mi_slot*8 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] == \n          P_M_AXI_READ_ISSUING[gen_mi_slot*32 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~r_cmd_pop[gen_mi_slot];\n      \n      always @(posedge ACLK) begin\n        if (reset) begin\n          w_issuing_cnt[gen_mi_slot*8+:8] <= 0;  // Some high-order bits remain constant 0\n          r_issuing_cnt[gen_mi_slot*8+:8] <= 0;  // Some high-order bits remain constant 0\n        end else begin\n          if (w_cmd_push[gen_mi_slot] && ~w_cmd_pop[gen_mi_slot]) begin\n            w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1;\n          end else if (w_cmd_pop[gen_mi_slot] && ~w_cmd_push[gen_mi_slot] && (|w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin\n            w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1;\n          end\n          if (r_cmd_push[gen_mi_slot] && ~r_cmd_pop[gen_mi_slot]) begin\n            r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1;\n          end else if (r_cmd_pop[gen_mi_slot] && ~r_cmd_push[gen_mi_slot] && (|r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin\n            r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1;\n          end\n        end\n      end  // Clocked process\n      \n      // Reg-slice must break combinatorial path from M_BID and M_RID inputs to M_BREADY and M_RREADY outputs.\n      //   (See m_rready_i and m_resp_en combinatorial assignments in si_transactor.)\n      //   Reg-slice incurs +1 latency, but no bubble-cycles.\n      axi_register_slice_v2_1_22_axi_register_slice #  // \"MR\": MI-side R/B-channel Reg-slice, per MI-slot (pass-through if only 1 SI-slot configured)\n        (\n          .C_FAMILY                         (C_FAMILY),\n          .C_AXI_PROTOCOL                   ((C_AXI_PROTOCOL == P_AXI3) ? P_AXI3 : P_AXI4),\n          .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),\n          .C_AXI_ADDR_WIDTH                 (1),\n          .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),\n          .C_AXI_SUPPORTS_USER_SIGNALS      (C_AXI_SUPPORTS_USER_SIGNALS),\n          .C_AXI_AWUSER_WIDTH               (1),\n          .C_AXI_ARUSER_WIDTH               (1),\n          .C_AXI_WUSER_WIDTH                (C_AXI_WUSER_WIDTH),\n          .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),\n          .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),\n          .C_REG_CONFIG_AW                  (P_BYPASS),\n          .C_REG_CONFIG_AR                  (P_BYPASS),\n          .C_REG_CONFIG_W                   (P_BYPASS),\n          .C_REG_CONFIG_R                   (P_M_AXI_SUPPORTS_READ[gen_mi_slot] ? P_FWD_REV : P_BYPASS),\n          .C_REG_CONFIG_B                   (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot] ? P_SIMPLE : P_BYPASS)\n        )\n        reg_slice_mi \n        (\n          .aresetn                          (ARESETN),\n          .aclk                             (ACLK),\n          .s_axi_awid                       ({C_AXI_ID_WIDTH{1'b0}}),\n          .s_axi_awaddr                     ({1{1'b0}}),\n          .s_axi_awlen                      ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1'b0}}),\n          .s_axi_awsize                     ({3{1'b0}}),\n          .s_axi_awburst                    ({2{1'b0}}),\n          .s_axi_awlock                     ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1'b0}}),\n          .s_axi_awcache                    ({4{1'b0}}),\n          .s_axi_awprot                     ({3{1'b0}}),\n          .s_axi_awregion                   ({4{1'b0}}),\n          .s_axi_awqos                      ({4{1'b0}}),\n          .s_axi_awuser                     ({1{1'b0}}),\n          .s_axi_awvalid                    ({1{1'b0}}),\n          .s_axi_awready                    (),\n          .s_axi_wid                        (wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n          .s_axi_wdata                      (wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),\n          .s_axi_wstrb                      (wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]),\n          .s_axi_wlast                      (wm_mr_wlast[gen_mi_slot]),\n          .s_axi_wuser                      (wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]),\n          .s_axi_wvalid                     (wm_mr_wvalid[gen_mi_slot]),\n          .s_axi_wready                     (wm_mr_wready[gen_mi_slot]),\n          .s_axi_bid                        (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]         ),\n          .s_axi_bresp                      (st_mr_bresp[gen_mi_slot*2+:2]                                 ),\n          .s_axi_buser                      (st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] ),\n          .s_axi_bvalid                     (st_mr_bvalid[gen_mi_slot*1+:1]                                ),\n          .s_axi_bready                     (st_mr_bready[gen_mi_slot*1+:1]                                ),\n          .s_axi_arid                       ({C_AXI_ID_WIDTH{1'b0}}),\n          .s_axi_araddr                     ({1{1'b0}}),\n          .s_axi_arlen                      ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1'b0}}),\n          .s_axi_arsize                     ({3{1'b0}}),\n          .s_axi_arburst                    ({2{1'b0}}),\n          .s_axi_arlock                     ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1'b0}}),\n          .s_axi_arcache                    ({4{1'b0}}),\n          .s_axi_arprot                     ({3{1'b0}}),\n          .s_axi_arregion                   ({4{1'b0}}),\n          .s_axi_arqos                      ({4{1'b0}}),\n          .s_axi_aruser                     ({1{1'b0}}),\n          .s_axi_arvalid                    ({1{1'b0}}),\n          .s_axi_arready                    (),\n          .s_axi_rid                        (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                          ),\n          .s_axi_rdata                      (st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]  ),\n          .s_axi_rresp                      (st_mr_rresp[gen_mi_slot*2+:2]                                                  ),\n          .s_axi_rlast                      (st_mr_rlast[gen_mi_slot*1+:1]                                                  ),\n          .s_axi_ruser                      (st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                  ),\n          .s_axi_rvalid                     (st_mr_rvalid[gen_mi_slot*1+:1]                                                 ),\n          .s_axi_rready                     (st_mr_rready[gen_mi_slot*1+:1]                                                 ),\n          .m_axi_awid                       (),\n          .m_axi_awaddr                     (),\n          .m_axi_awlen                      (),\n          .m_axi_awsize                     (),\n          .m_axi_awburst                    (),\n          .m_axi_awlock                     (),\n          .m_axi_awcache                    (),\n          .m_axi_awprot                     (),\n          .m_axi_awregion                   (),\n          .m_axi_awqos                      (),\n          .m_axi_awuser                     (),\n          .m_axi_awvalid                    (),\n          .m_axi_awready                    ({1{1'b0}}),\n          .m_axi_wid                        (mi_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n          .m_axi_wdata                      (mi_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),\n          .m_axi_wstrb                      (mi_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]),\n          .m_axi_wlast                      (mi_wlast[gen_mi_slot]),\n          .m_axi_wuser                      (mi_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]),\n          .m_axi_wvalid                     (mi_wvalid[gen_mi_slot]),\n          .m_axi_wready                     (mi_wready[gen_mi_slot]),\n          .m_axi_bid                        (mi_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                          ),\n          .m_axi_bresp                      (mi_bresp[gen_mi_slot*2+:2]                                                  ),\n          .m_axi_buser                      (mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                  ),\n          .m_axi_bvalid                     (mi_bvalid[gen_mi_slot*1+:1]                                                 ),\n          .m_axi_bready                     (mi_bready[gen_mi_slot*1+:1]                                                 ),\n          .m_axi_arid                       (),\n          .m_axi_araddr                     (),\n          .m_axi_arlen                      (),\n          .m_axi_arsize                     (),\n          .m_axi_arburst                    (),\n          .m_axi_arlock                     (),\n          .m_axi_arcache                    (),\n          .m_axi_arprot                     (),\n          .m_axi_arregion                   (),\n          .m_axi_arqos                      (),\n          .m_axi_aruser                     (),\n          .m_axi_arvalid                    (),\n          .m_axi_arready                    ({1{1'b0}}),\n          .m_axi_rid                        (mi_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                          ),\n          .m_axi_rdata                      (mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]  ),\n          .m_axi_rresp                      (mi_rresp[gen_mi_slot*2+:2]                                                  ),\n          .m_axi_rlast                      (mi_rlast[gen_mi_slot*1+:1]                                                  ),\n          .m_axi_ruser                      (mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                  ),\n          .m_axi_rvalid                     (mi_rvalid[gen_mi_slot*1+:1]                                                 ),\n          .m_axi_rready                     (mi_rready[gen_mi_slot*1+:1]                                                 )\n        );\n    end  // gen_master_slots (Next gen_mi_slot)\n  \n    // Highest row of *ready_carry contains accumulated OR across all SI-slots, for each MI-slot.\n    assign st_mr_bready = bready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1]; \n    assign st_mr_rready = rready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1]; \n    // Assign MI-side B, R and W channel ports (exclude error handler signals).\n    assign mi_bid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_BID;\n    assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID; \n    assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP;\n    assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER;\n    assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS];\n    assign mi_rid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_RID;\n    assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST; \n    assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID; \n    assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP;\n    assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER;\n    assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA;\n    assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS];\n    assign M_AXI_WLAST = mi_wlast[0+:C_NUM_MASTER_SLOTS];\n    assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS];\n    assign M_AXI_WUSER = mi_wuser[0+:C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH];\n    assign M_AXI_WID = (C_AXI_PROTOCOL == P_AXI3) ? mi_wid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] : 0;\n    assign M_AXI_WDATA = mi_wdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH];\n    assign M_AXI_WSTRB = mi_wstrb[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8];\n    assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY;\n\n    axi_crossbar_v2_1_23_addr_arbiter #  // \"AA\": Addr Arbiter (AW channel)\n      (\n       .C_FAMILY                (C_FAMILY),\n       .C_NUM_M                 (C_NUM_MASTER_SLOTS+1),\n       .C_NUM_S                 (C_NUM_SLAVE_SLOTS),\n       .C_NUM_S_LOG             (P_NUM_SLAVE_SLOTS_LOG),\n       .C_MESG_WIDTH            (P_AA_AWMESG_WIDTH),\n       .C_ARB_PRIORITY          (C_S_AXI_ARB_PRIORITY)\n       )\n      addr_arbiter_aw\n        (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         // Vector of SI-side AW command request inputs\n         .S_MESG                (tmp_aa_awmesg),\n         .S_TARGET_HOT          (st_aa_awtarget_hot),\n         .S_VALID               (ss_aa_awvalid),\n         .S_VALID_QUAL          (st_aa_awvalid_qual),\n         .S_READY               (ss_aa_awready),\n         // Granted AW command output\n         .M_MESG                (aa_mi_awmesg),\n         .M_TARGET_HOT          (aa_mi_awtarget_hot),  // MI-slot targeted by granted command\n         .M_GRANT_ENC           (aa_wm_awgrant_enc),  // SI-slot index of granted command\n         .M_VALID               (aa_sa_awvalid),\n         .M_READY               (aa_sa_awready),\n         .ISSUING_LIMIT        (mi_awmaxissuing)\n        );\n         \n    // Broadcast AW transfer payload to all MI-slots\n    assign M_AXI_AWID        = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[0+:C_AXI_ID_WIDTH]}};\n    assign M_AXI_AWADDR      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}};\n    assign M_AXI_AWLEN       = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}};\n    assign M_AXI_AWSIZE      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}};\n    assign M_AXI_AWLOCK      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}};\n    assign M_AXI_AWPROT      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}};\n    assign M_AXI_AWREGION    = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}};\n    assign M_AXI_AWBURST     = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}};\n    assign M_AXI_AWCACHE     = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}};\n    assign M_AXI_AWQOS       = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}};\n    assign M_AXI_AWUSER      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_AWUSER_WIDTH]}};\n         \n    axi_crossbar_v2_1_23_addr_arbiter #  // \"AA\": Addr Arbiter (AR channel)\n      (\n       .C_FAMILY                (C_FAMILY),\n       .C_NUM_M                 (C_NUM_MASTER_SLOTS+1),\n       .C_NUM_S                 (C_NUM_SLAVE_SLOTS),\n       .C_NUM_S_LOG             (P_NUM_SLAVE_SLOTS_LOG),\n       .C_MESG_WIDTH            (P_AA_ARMESG_WIDTH),\n       .C_ARB_PRIORITY          (C_S_AXI_ARB_PRIORITY)\n       )\n      addr_arbiter_ar\n        (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         // Vector of SI-side AR command request inputs\n         .S_MESG                (tmp_aa_armesg),\n         .S_TARGET_HOT          (st_aa_artarget_hot),\n         .S_VALID_QUAL          (st_aa_arvalid_qual),\n         .S_VALID               (st_aa_arvalid),\n         .S_READY               (st_aa_arready),\n         // Granted AR command output\n         .M_MESG                (aa_mi_armesg),\n         .M_TARGET_HOT          (aa_mi_artarget_hot),  // MI-slot targeted by granted command\n         .M_GRANT_ENC           (aa_mi_argrant_enc),\n         .M_VALID               (aa_mi_arvalid),  // SI-slot index of granted command\n         .M_READY               (aa_mi_arready),\n         .ISSUING_LIMIT        (mi_armaxissuing)\n        );\n    \n    if (C_DEBUG) begin : gen_debug_trans_seq\n      // DEBUG WRITE TRANSACTION SEQUENCE COUNTER\n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_aw_trans_seq_i <= 1;\n        end else begin\n          if (aa_sa_awvalid && aa_sa_awready) begin\n            debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1;\n          end\n        end\n      end\n  \n      // DEBUG READ TRANSACTION SEQUENCE COUNTER\n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_ar_trans_seq_i <= 1;\n        end else begin\n          if (aa_mi_arvalid && aa_mi_arready) begin\n            debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1;\n          end\n        end\n      end\n    end  // gen_debug_trans_seq\n\n    // Broadcast AR transfer payload to all MI-slots\n    assign M_AXI_ARID        = {C_NUM_MASTER_SLOTS{aa_mi_armesg[0+:C_AXI_ID_WIDTH]}};\n    assign M_AXI_ARADDR      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}};\n    assign M_AXI_ARLEN       = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}};\n    assign M_AXI_ARSIZE      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}};\n    assign M_AXI_ARLOCK      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}};\n    assign M_AXI_ARPROT      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}};\n    assign M_AXI_ARREGION    = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}};\n    assign M_AXI_ARBURST     = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}};\n    assign M_AXI_ARCACHE     = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}};\n    assign M_AXI_ARQOS       = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}};\n    assign M_AXI_ARUSER      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_ARUSER_WIDTH]}};\n         \n    // AW arbiter command transfer completes upon completion of both M-side AW-channel transfer and W-mux address acceptance (command push).\n    axi_crossbar_v2_1_23_splitter #  // \"SA\": Splitter for Write Addr Arbiter\n      (\n        .C_NUM_M                (2)\n      )\n      splitter_aw_mi\n      (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         .S_VALID              (aa_sa_awvalid),\n         .S_READY              (aa_sa_awready),\n         .M_VALID              ({mi_awvalid_en, sa_wm_awvalid_en}),\n         .M_READY              ({mi_awready_mux, sa_wm_awready_mux})\n      );\n      \n    assign mi_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{mi_awvalid_en}};\n    assign mi_awready_mux = |(aa_mi_awtarget_hot & mi_awready);\n    assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS];  // Slot C_NUM_MASTER_SLOTS+1 is the error handler\n    assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY;\n    assign sa_wm_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{sa_wm_awvalid_en}};\n    assign sa_wm_awready_mux = |(aa_mi_awtarget_hot & sa_wm_awready);\n    \n    assign mi_arvalid = aa_mi_artarget_hot & {C_NUM_MASTER_SLOTS+1{aa_mi_arvalid}};\n    assign aa_mi_arready = |(aa_mi_artarget_hot & mi_arready);\n    assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS];  // Slot C_NUM_MASTER_SLOTS+1 is the error handler\n    assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY;\n    \n    // MI-slot # C_NUM_MASTER_SLOTS is the error handler\n    if (C_RANGE_CHECK) begin : gen_decerr_slave\n      axi_crossbar_v2_1_23_decerr_slave #\n        (\n         .C_AXI_ID_WIDTH                 (C_AXI_ID_WIDTH),\n         .C_AXI_DATA_WIDTH               (C_AXI_DATA_WIDTH),\n         .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),\n         .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),\n         .C_AXI_PROTOCOL                 (C_AXI_PROTOCOL),\n         .C_RESP                         (P_DECERR) \n        )\n        decerr_slave_inst\n          (\n           .S_AXI_ACLK (ACLK),\n           .S_AXI_ARESET (reset),\n           .S_AXI_AWID (aa_mi_awmesg[0+:C_AXI_ID_WIDTH]),\n           .S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_WLAST (mi_wlast[C_NUM_MASTER_SLOTS]),\n           .S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_BID (mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n           .S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]),\n           .S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]),\n           .S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_ARID (aa_mi_armesg[0+:C_AXI_ID_WIDTH]),\n           .S_AXI_ARLEN (aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]),\n           .S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RID (mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n           .S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),\n           .S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]),\n           .S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]),\n           .S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS])\n         );\n    end else begin : gen_no_decerr_slave\n      assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;\n      assign mi_wready[C_NUM_MASTER_SLOTS] = 1'b0;\n      assign mi_arready[C_NUM_MASTER_SLOTS] = 1'b0;\n      assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;\n      assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;\n      assign mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                    = 0;\n      assign mi_bresp[C_NUM_MASTER_SLOTS*2+:2]                                            = 0;\n      assign mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]            = 0;\n      assign mi_bvalid[C_NUM_MASTER_SLOTS]                                                = 1'b0;\n      assign mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                    = 0;\n      assign mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0; \n      assign mi_rresp[C_NUM_MASTER_SLOTS*2+:2]                                            = 0; \n      assign mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]            = 0; \n      assign mi_rlast[C_NUM_MASTER_SLOTS]                                                  = 1'b0;\n      assign mi_rvalid[C_NUM_MASTER_SLOTS]                                                 = 1'b0;\n    end  // gen_decerr_slave\n  endgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: decerr_slave.v\n//\n// Description: \n//   Phantom slave interface used to complete W, R and B channel transfers when an\n//   erroneous transaction is trapped in the crossbar.\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    decerr_slave\n//    \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_decerr_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH           = 1,\n   parameter integer C_AXI_DATA_WIDTH         = 32,\n   parameter integer C_AXI_BUSER_WIDTH        = 1,\n   parameter integer C_AXI_RUSER_WIDTH        = 1,\n   parameter integer C_AXI_PROTOCOL           = 0,\n   parameter integer C_RESP                   = 2'b11   \n   )\n  (\n   input wire S_AXI_ACLK,\n   input wire S_AXI_ARESET,\n   input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,\n   input wire S_AXI_AWVALID,\n   output wire S_AXI_AWREADY,\n   input wire S_AXI_WLAST,\n   input wire S_AXI_WVALID,\n   output wire S_AXI_WREADY,\n   output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,\n   output wire [1:0] S_AXI_BRESP,\n   output wire [C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,\n   output wire S_AXI_BVALID,\n   input wire S_AXI_BREADY,\n   input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,\n   input wire [7:0] S_AXI_ARLEN,\n   input wire S_AXI_ARVALID,\n   output wire S_AXI_ARREADY,\n   output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,\n   output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,\n   output wire [1:0] S_AXI_RRESP,\n   output wire [C_AXI_RUSER_WIDTH-1:0]          S_AXI_RUSER,\n   output wire S_AXI_RLAST,\n   output wire S_AXI_RVALID,\n   input wire S_AXI_RREADY\n   );\n   \n  reg s_axi_awready_i = 1'b0;\n  reg s_axi_wready_i = 1'b0;\n  reg s_axi_bvalid_i = 1'b0;\n  reg s_axi_arready_i = 1'b0;\n  reg s_axi_rvalid_i = 1'b0;\n  \n  localparam P_WRITE_IDLE = 2'b00;\n  localparam P_WRITE_DATA = 2'b01;\n  localparam P_WRITE_RESP = 2'b10;\n  localparam P_READ_IDLE = 1'b0;\n  localparam P_READ_DATA = 1'b1;\n  localparam integer  P_AXI4 = 0;\n  localparam integer  P_AXI3 = 1;\n  localparam integer  P_AXILITE = 2;\n   \n  assign S_AXI_BRESP = C_RESP;\n  assign S_AXI_RRESP = C_RESP;\n  //assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};\n  assign S_AXI_RDATA = {C_AXI_DATA_WIDTH/32{32'hDEC0_DE1C}};\n  assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};\n  assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};\n  assign S_AXI_AWREADY = s_axi_awready_i;\n  assign S_AXI_WREADY = s_axi_wready_i;\n  assign S_AXI_BVALID = s_axi_bvalid_i;\n  assign S_AXI_ARREADY = s_axi_arready_i;\n  assign S_AXI_RVALID = s_axi_rvalid_i;\n  \n  generate\n  if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite\n    \n    assign S_AXI_RLAST = 1'b1;\n    assign S_AXI_BID = 0;\n    assign S_AXI_RID = 0;\n    \n    always @(posedge S_AXI_ACLK) begin\n      if (S_AXI_ARESET) begin\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        if (s_axi_bvalid_i) begin\n          if (S_AXI_BREADY) begin\n            s_axi_bvalid_i <= 1'b0;\n          end\n        end else if (S_AXI_AWVALID & S_AXI_WVALID) begin\n          if (s_axi_awready_i) begin\n            s_axi_awready_i <= 1'b0;\n            s_axi_wready_i <= 1'b0;\n            s_axi_bvalid_i <= 1'b1;\n          end else begin\n            s_axi_awready_i <= 1'b1;\n            s_axi_wready_i <= 1'b1;\n          end\n        end\n      end\n    end\n           \n    always @(posedge S_AXI_ACLK) begin\n      if (S_AXI_ARESET) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n      end else begin\n        if (s_axi_rvalid_i) begin\n          if (S_AXI_RREADY) begin\n            s_axi_rvalid_i <= 1'b0;\n          end\n        end else if (S_AXI_ARVALID & s_axi_arready_i) begin\n          s_axi_arready_i <= 1'b0;\n          s_axi_rvalid_i <= 1'b1;\n        end else begin\n          s_axi_arready_i <= 1'b1;\n        end\n      end\n    end\n        \n  end else begin : gen_axi\n  \n    reg s_axi_rlast_i;\n    reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;\n    reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;\n    reg [7:0] read_cnt;\n    reg [1:0] write_cs;\n    reg [0:0] read_cs;\n  \n    assign S_AXI_RLAST = s_axi_rlast_i;\n    assign S_AXI_BID = s_axi_bid_i;\n    assign S_AXI_RID = s_axi_rid_i;\n  \n    always @(posedge S_AXI_ACLK) begin\n      if (S_AXI_ARESET) begin\n        write_cs <= P_WRITE_IDLE;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n        s_axi_bid_i <= 0;\n      end else begin\n        case (write_cs) \n          P_WRITE_IDLE: \n            begin\n              if (S_AXI_AWVALID & s_axi_awready_i) begin\n                s_axi_awready_i <= 1'b0;\n                s_axi_bid_i <= S_AXI_AWID;\n                s_axi_wready_i <= 1'b1;\n                write_cs <= P_WRITE_DATA;\n              end else begin\n                s_axi_awready_i <= 1'b1;\n              end\n            end\n          P_WRITE_DATA:\n            begin\n              if (S_AXI_WVALID & S_AXI_WLAST) begin\n                s_axi_wready_i <= 1'b0;\n                s_axi_bvalid_i <= 1'b1;\n                write_cs <= P_WRITE_RESP;\n              end\n            end\n          P_WRITE_RESP:\n            begin\n              if (S_AXI_BREADY) begin\n                s_axi_bvalid_i <= 1'b0;\n                s_axi_awready_i <= 1'b1;\n                write_cs <= P_WRITE_IDLE;\n              end\n            end\n        endcase\n      end\n    end\n  \n    always @(posedge S_AXI_ACLK) begin\n      if (S_AXI_ARESET) begin\n        read_cs <= P_READ_IDLE;\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        s_axi_rlast_i <= 1'b0;\n        s_axi_rid_i <= 0;\n        read_cnt <= 0;\n      end else begin\n        case (read_cs) \n          P_READ_IDLE: \n            begin\n              if (S_AXI_ARVALID & s_axi_arready_i) begin\n                s_axi_arready_i <= 1'b0;\n                s_axi_rid_i <= S_AXI_ARID;\n                read_cnt <= S_AXI_ARLEN;\n                s_axi_rvalid_i <= 1'b1;\n                if (S_AXI_ARLEN == 0) begin\n                  s_axi_rlast_i <= 1'b1;\n                end else begin\n                  s_axi_rlast_i <= 1'b0;\n                end\n                read_cs <= P_READ_DATA;\n              end else begin\n                s_axi_arready_i <= 1'b1;\n              end\n            end\n          P_READ_DATA:\n            begin\n              if (S_AXI_RREADY) begin\n                if (read_cnt == 0) begin\n                  s_axi_rvalid_i <= 1'b0;\n                  s_axi_rlast_i <= 1'b0;\n                  s_axi_arready_i <= 1'b1;\n                  read_cs <= P_READ_IDLE;\n                end else begin\n                  if (read_cnt == 1) begin\n                    s_axi_rlast_i <= 1'b1;\n                  end\n                  read_cnt <= read_cnt - 1;\n                end\n              end\n            end\n        endcase\n      end\n    end\n  \n  end  \n  endgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: si_transactor.v\n//\n// Description: \n//   This module manages multi-threaded transactions for one SI-slot.\n//   The module interface consists of a 1-slave to 1-master address channel, plus a\n//     (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel.\n//   The module maintains transaction thread control registers that count the\n//     number of outstanding transations for each thread and the target MI-slot.\n//   On the address channel, the module decodes addresses to select among MI-slots \n//     accessible to the SI-slot where it is instantiated.\n//     It then qualifies whether each received transaction\n//     should be propagated as a request to the address channel arbiter.\n//     Transactions are blocked while there is any outstanding transaction to a \n//     different slave (MI-slot) for the requested ID thread (for deadlock avoidance).\n//   On the response channel, the module mulitplexes transfers from each of the \n//     MI-slots whenever a transfer targets the ID of an active thread,\n//     arbitrating between MI-slots if multiple threads respond concurrently.\n//\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    si_transactor\n//      addr_decoder\n//        comparator_static\n//      mux_enc\n//      axic_srl_fifo\n//      arbiter_resp\n//      \n//-----------------------------------------------------------------------------\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_si_transactor #\n  (\n   parameter         C_FAMILY                       = \"none\", \n   parameter integer C_SI             =   0, // SI-slot number of current instance.\n   parameter integer C_DIR             =   0, // Direction: 0 = Write; 1 = Read.\n   parameter integer C_NUM_ADDR_RANGES = 1,\n   parameter integer C_NUM_M             =   2, \n   parameter integer C_NUM_M_LOG             =   1, \n   parameter integer C_ACCEPTANCE             =   1,  // Acceptance limit of this SI-slot.\n   parameter integer C_ACCEPTANCE_LOG             =   0,  // Width of acceptance counter for this SI-slot.\n   parameter integer C_ID_WIDTH                   = 1, \n   parameter integer C_THREAD_ID_WIDTH                  = 0,\n   parameter integer C_ADDR_WIDTH                 = 32, \n   parameter integer C_AMESG_WIDTH = 1,  // Used for AW or AR channel payload, depending on instantiation.\n   parameter integer C_RMESG_WIDTH = 1,  // Used for B or R channel payload, depending on instantiation.\n   parameter [C_ID_WIDTH-1:0]  C_BASE_ID                  = {C_ID_WIDTH{1'b0}},\n   parameter [C_ID_WIDTH-1:0]  C_HIGH_ID                  = {C_ID_WIDTH{1'b0}},\n   parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b1}}, \n   parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b0}}, \n   parameter integer C_SINGLE_THREAD             =   0,\n   parameter [C_NUM_M-1:0]    C_TARGET_QUAL                 = {C_NUM_M{1'b1}},\n   parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE                   = {C_NUM_M{32'h00000000}},\n   parameter integer C_RANGE_CHECK                    = 0,\n   parameter integer C_ADDR_DECODE           =0,\n   parameter [C_NUM_M*32-1:0] C_ERR_MODE            = {C_NUM_M{32'h00000000}},\n   parameter integer C_DEBUG                = 1\n   )\n  (\n   // Global Signals\n   input  wire                                                    ACLK,\n   input  wire                                                    ARESET,\n   // Slave Address Channel Interface Ports\n   input  wire [C_ID_WIDTH-1:0]           S_AID,\n   input  wire [C_ADDR_WIDTH-1:0]          S_AADDR,\n   input  wire [8-1:0]                    S_ALEN,\n   input  wire [3-1:0]                    S_ASIZE,\n   input  wire [2-1:0]                    S_ABURST,\n   input  wire [2-1:0]                    S_ALOCK,\n   input  wire [3-1:0]                    S_APROT,\n//   input  wire [4-1:0]                    S_AREGION,\n   input  wire [C_AMESG_WIDTH-1:0]         S_AMESG,\n   input  wire                             S_AVALID,\n   output wire                             S_AREADY,\n   // Master Address Channel Interface Ports\n   output wire [C_ID_WIDTH-1:0]          M_AID,\n   output wire [C_ADDR_WIDTH-1:0]          M_AADDR,\n   output  wire [8-1:0]                    M_ALEN,\n   output  wire [3-1:0]                    M_ASIZE,\n   output  wire [2-1:0]                    M_ALOCK,\n   output  wire [3-1:0]                    M_APROT,\n   output wire [4-1:0]                         M_AREGION,\n   output wire [C_AMESG_WIDTH-1:0]                         M_AMESG,\n   output wire [(C_NUM_M+1)-1:0]                         M_ATARGET_HOT,\n   output wire [(C_NUM_M_LOG+1)-1:0]                         M_ATARGET_ENC,\n   output wire [7:0]                         M_AERROR,\n   output wire                            M_AVALID_QUAL,\n   output wire                            M_AVALID,\n   input  wire                            M_AREADY,\n   // Slave Response Channel Interface Ports\n   output  wire [C_ID_WIDTH-1:0]           S_RID,\n   output  wire [C_RMESG_WIDTH-1:0]         S_RMESG,\n   output  wire                             S_RLAST,\n   output  wire                             S_RVALID,\n   input wire                             S_RREADY,\n   // Master Response Channel Interface Ports\n   input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0]          M_RID,\n   input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0]             M_RMESG,\n   input wire [(C_NUM_M+1)-1:0]                           M_RLAST,\n   input wire [(C_NUM_M+1)-1:0]                           M_RVALID,\n   output  wire [(C_NUM_M+1)-1:0]                           M_RREADY,\n   input wire [(C_NUM_M+1)-1:0]           M_RTARGET,  // Does response ID from each MI-slot target this SI slot?\n   input wire [8-1:0]                        DEBUG_A_TRANS_SEQ\n   );\n\n  localparam integer P_WRITE = 0;\n  localparam integer P_READ = 1;\n  localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1;\n  localparam [31:0]   P_AXILITE_ERRMODE = 32'h00000001;\n  localparam integer P_NONSECURE_BIT = 1; \n  localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1;\n  localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0);  // Mask of AxiLite MI-slots\n  localparam [1:0]   P_FIXED = 2'b00;\n  localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1);\n  localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1; \n  localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH;\n  localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE;\n  localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE);  // Mask of secure MI-slots\n  \n  // Ceiling of log2(x)\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  // AxiLite protocol flag vector      \n  function [C_NUM_M-1:0] f_m_axilite\n    (\n      input integer null_arg\n    );\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_M; mi=mi+1) begin\n        f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);\n      end\n    end\n  endfunction\n\n  // Convert Bit32 vector of range [0,1] to Bit1 vector on MI\n  function [C_NUM_M-1:0] f_bit32to1_mi\n    (input [C_NUM_M*32-1:0] vec32);\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_M; mi=mi+1) begin\n        f_bit32to1_mi[mi] = vec32[mi*32];\n      end\n    end\n  endfunction\n  \n  wire [C_NUM_M-1:0] target_mi_hot;\n  wire [P_NUM_M_LOG_M1-1:0] target_mi_enc;\n  wire [(C_NUM_M+1)-1:0] m_atarget_hot_i;\n  wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i;\n  wire match;\n  wire [3:0] target_region;\n  wire [3:0] m_aregion_i;\n  wire m_avalid_i;\n  wire s_aready_i;\n  wire any_error;\n  wire s_rvalid_i;\n  wire [C_ID_WIDTH-1:0] s_rid_i;\n  wire s_rlast_i;\n  wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg;\n  wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg;\n  wire [(C_NUM_M+1)-1:0] m_rvalid_qual;\n  wire [(C_NUM_M+1)-1:0] m_rready_arb;\n  wire [(C_NUM_M+1)-1:0] m_rready_i;\n  wire target_secure;\n  wire target_axilite;\n  wire m_avalid_qual_i;\n  wire [7:0] m_aerror_i;\n  \n  genvar gen_mi;\n  genvar gen_thread;\n    \n  generate\n    if (C_ADDR_DECODE) begin : gen_addr_decoder\n      axi_crossbar_v2_1_23_addr_decoder #\n        (\n          .C_FAMILY          (C_FAMILY),\n          .C_NUM_TARGETS     (C_NUM_M),\n          .C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1),\n          .C_NUM_RANGES      (C_NUM_ADDR_RANGES),\n          .C_ADDR_WIDTH      (C_ADDR_WIDTH),\n          .C_TARGET_ENC      (1),\n          .C_TARGET_HOT      (1),\n          .C_REGION_ENC      (1),\n          .C_BASE_ADDR      (C_BASE_ADDR),\n          .C_HIGH_ADDR      (C_HIGH_ADDR),\n          .C_TARGET_QUAL     (C_TARGET_QUAL),\n          .C_RESOLUTION      (2)\n        ) \n        addr_decoder_inst \n        (\n          .ADDR             (S_AADDR),        \n          .TARGET_HOT       (target_mi_hot),  \n          .TARGET_ENC       (target_mi_enc),  \n          .MATCH            (match),       \n          .REGION           (target_region)      \n        );\n    end else begin : gen_no_addr_decoder\n      assign target_mi_hot = 1;\n      assign target_mi_enc = 0;\n      assign match = 1'b1;\n      assign target_region = 4'b0000;\n    end\n  endgenerate\n  \n  assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);\n  assign target_axilite = |(target_mi_hot & P_M_AXILITE);\n\n  assign any_error = C_RANGE_CHECK && (m_aerror_i != 0);            // DECERR if error-detection enabled and any error condition.\n  assign m_aerror_i[0] = ~match;                                    // Invalid target address\n  assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation\n  assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) || \n    (S_ASIZE[1:0] == 2'b11) || (S_ASIZE[2] == 1'b1));               // AxiLite access violation\n  assign m_aerror_i[7:3] = 5'b00000;                                    // Reserved\n  assign M_ATARGET_HOT = m_atarget_hot_i;\n  assign m_atarget_hot_i = (any_error ? {1'b1, {C_NUM_M{1'b0}}} : {1'b0, target_mi_hot});\n  assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc);\n    \n  assign M_AVALID = m_avalid_i;\n  assign m_avalid_i = S_AVALID;\n  assign M_AVALID_QUAL = m_avalid_qual_i; \n  assign S_AREADY = s_aready_i;\n  assign s_aready_i = M_AREADY;\n  assign M_AERROR = m_aerror_i;\n  assign M_ATARGET_ENC = m_atarget_enc_i;\n  assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4'b0000;\n//  assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION;\n  assign M_AREGION = m_aregion_i;\n  assign M_AID = S_AID;\n  assign M_AADDR = S_AADDR;\n  assign M_ALEN = S_ALEN;\n  assign M_ASIZE = S_ASIZE;\n  assign M_ALOCK = S_ALOCK;\n  assign M_APROT = S_APROT;\n  assign M_AMESG = S_AMESG;\n  \n  assign S_RVALID = s_rvalid_i;\n  assign M_RREADY = m_rready_i;\n  assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH];\n  assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH];\n  assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1];\n  assign S_RID = s_rid_i;\n  assign S_RLAST = s_rlast_i;\n  assign m_rvalid_qual = M_RVALID & M_RTARGET;\n  assign m_rready_i = m_rready_arb & M_RTARGET;\n\n  generate\n    for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi\n      // Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.\n      assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = {\n               M_RLAST[gen_mi],\n               M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH],\n               M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH]\n               };\n    end  // gen_rmesg_mi\n\n    if (C_ACCEPTANCE == 1) begin : gen_single_issue\n      wire  cmd_push;\n      wire  cmd_pop;\n      reg  [(C_NUM_M+1)-1:0] active_target_hot = 0;\n      reg  [P_NUM_M_DE_LOG-1:0] active_target_enc = 0;\n      reg  accept_cnt = 1'b0;\n      reg  [8-1:0] debug_r_beat_cnt_i;\n      wire [8-1:0] debug_r_trans_seq_i;\n\n      assign cmd_push = M_AREADY;\n      assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i;  // Pop command queue if end of read burst\n      assign m_avalid_qual_i = ~accept_cnt | cmd_pop;  // Ready for arbitration if no outstanding transaction or transaction being completed\n\n      always @(posedge ACLK) begin \n        if (ARESET) begin\n          accept_cnt <= 1'b0;\n          active_target_enc <= 0;\n          active_target_hot <= 0;\n        end else begin\n          if (cmd_push) begin\n            active_target_enc <= m_atarget_enc_i;\n            active_target_hot <= m_atarget_hot_i;\n            accept_cnt <= 1'b1;\n          end else if (cmd_pop) begin\n            accept_cnt <= 1'b0;\n          end\n        end \n      end  // Clocked process\n        \n      assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};\n      assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);\n                 \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (C_FAMILY),\n         .C_RATIO       (C_NUM_M+1),\n         .C_SEL_WIDTH   (P_NUM_M_DE_LOG),\n         .C_DATA_WIDTH  (P_RMUX_MESG_WIDTH)\n        ) mux_resp_single_issue\n        (\n         .S   (active_target_enc),\n         .A   (mi_rmux_mesg),\n         .O   (si_rmux_mesg),\n         .OE  (1'b1)\n        ); \n        \n      if (C_DEBUG) begin : gen_debug_r_single_issue\n        // DEBUG READ BEAT COUNTER (only meaningful for R-channel)\n        always @(posedge ACLK) begin\n          if (ARESET) begin\n            debug_r_beat_cnt_i <= 0;\n          end else if (C_DIR == P_READ) begin\n            if (s_rvalid_i && S_RREADY) begin\n              if (s_rlast_i) begin\n                debug_r_beat_cnt_i <= 0;\n              end else begin\n                debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;\n              end\n            end\n          end else begin\n            debug_r_beat_cnt_i <= 0;            \n          end\n        end  // Clocked process\n        \n        // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO\n        axi_data_fifo_v2_1_21_axic_srl_fifo #\n          (\n           .C_FAMILY          (C_FAMILY),\n           .C_FIFO_WIDTH      (8),\n           .C_FIFO_DEPTH_LOG  (C_ACCEPTANCE_LOG+1),\n           .C_USE_FULL        (0)\n           )\n          debug_r_seq_fifo_single_issue\n            (\n             .ACLK    (ACLK),\n             .ARESET  (ARESET),\n             .S_MESG  (DEBUG_A_TRANS_SEQ),\n             .S_VALID (cmd_push),\n             .S_READY (),\n             .M_MESG  (debug_r_trans_seq_i),\n             .M_VALID (),\n             .M_READY (cmd_pop)\n            );\n            \n      end  // gen_debug_r\n      \n    end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread\n      wire  s_avalid_en;\n      wire  cmd_push;\n      wire  cmd_pop;\n      reg  [C_ID_WIDTH-1:0] active_id;\n      reg  [(C_NUM_M+1)-1:0] active_target_hot = 0;\n      reg  [P_NUM_M_DE_LOG-1:0] active_target_enc = 0;\n      reg  [4-1:0] active_region;\n      reg  [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt = 0;\n      reg  [8-1:0] debug_r_beat_cnt_i;\n      wire [8-1:0] debug_r_trans_seq_i;\n      wire accept_limit ;\n\n      // Implement single-region-per-ID cyclic dependency avoidance method.\n      assign s_avalid_en =  // This transaction is qualified to request arbitration if ...\n        (accept_cnt == 0) ||  // Either there are no outstanding transactions, or ...\n        (((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) &&  // the current transaction ID matches the previous, and ...\n        (active_target_enc == m_atarget_enc_i) &&  // all outstanding transactions are to the same target MI ...\n        (active_region == m_aregion_i));  // and to the same REGION.\n      \n      assign cmd_push = M_AREADY;\n      assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i;  // Pop command queue if end of read burst\n      assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop;  // Allow next push if a transaction is currently being completed\n      assign m_avalid_qual_i = s_avalid_en & ~accept_limit; \n      \n      always @(posedge ACLK) begin \n        if (ARESET) begin\n          accept_cnt <= 0;\n          active_id <= 0;\n          active_target_enc <= 0;\n          active_target_hot <= 0;\n          active_region <= 0;\n        end else begin\n          if (cmd_push) begin\n            active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];\n            active_target_enc <= m_atarget_enc_i;\n            active_target_hot <= m_atarget_hot_i;\n            active_region <= m_aregion_i;\n            if (~cmd_pop) begin\n              accept_cnt <= accept_cnt + 1;\n            end\n          end else begin\n            if (cmd_pop & (accept_cnt != 0)) begin\n              accept_cnt <= accept_cnt - 1;\n            end\n          end\n        end \n      end  // Clocked process\n        \n      assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};\n      assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);\n                 \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (C_FAMILY),\n         .C_RATIO       (C_NUM_M+1),\n         .C_SEL_WIDTH   (P_NUM_M_DE_LOG),\n         .C_DATA_WIDTH  (P_RMUX_MESG_WIDTH)\n        ) mux_resp_single_thread\n        (\n         .S   (active_target_enc),\n         .A   (mi_rmux_mesg),\n         .O   (si_rmux_mesg),\n         .OE  (1'b1)\n        ); \n        \n      if (C_DEBUG) begin : gen_debug_r_single_thread\n        // DEBUG READ BEAT COUNTER (only meaningful for R-channel)\n        always @(posedge ACLK) begin\n          if (ARESET) begin\n            debug_r_beat_cnt_i <= 0;\n          end else if (C_DIR == P_READ) begin\n            if (s_rvalid_i && S_RREADY) begin\n              if (s_rlast_i) begin\n                debug_r_beat_cnt_i <= 0;\n              end else begin\n                debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;\n              end\n            end\n          end else begin\n            debug_r_beat_cnt_i <= 0;            \n          end\n        end  // Clocked process\n        \n        // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO\n        axi_data_fifo_v2_1_21_axic_srl_fifo #\n          (\n           .C_FAMILY          (C_FAMILY),\n           .C_FIFO_WIDTH      (8),\n           .C_FIFO_DEPTH_LOG  (C_ACCEPTANCE_LOG+1),\n           .C_USE_FULL        (0)\n           )\n          debug_r_seq_fifo_single_thread\n            (\n             .ACLK    (ACLK),\n             .ARESET  (ARESET),\n             .S_MESG  (DEBUG_A_TRANS_SEQ),\n             .S_VALID (cmd_push),\n             .S_READY (),\n             .M_MESG  (debug_r_trans_seq_i),\n             .M_VALID (),\n             .M_READY (cmd_pop)\n            );\n            \n      end  // gen_debug_r\n      \n    end else begin : gen_multi_thread\n      wire [(P_NUM_M_DE_LOG)-1:0] resp_select;\n      reg  [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt = 0;\n      wire [P_NUM_THREADS-1:0] s_avalid_en;\n      wire [P_NUM_THREADS-1:0] thread_valid;\n      wire [P_NUM_THREADS-1:0] aid_match;\n      wire [P_NUM_THREADS-1:0] rid_match;\n      wire [P_NUM_THREADS-1:0] cmd_push;\n      wire [P_NUM_THREADS-1:0] cmd_pop;\n      wire [P_NUM_THREADS:0]   accum_push;\n      reg  [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id;\n      reg  [P_NUM_THREADS*8-1:0] active_target;\n      reg  [P_NUM_THREADS*8-1:0] active_region;\n      reg  [P_NUM_THREADS*8-1:0] active_cnt = 0;\n      reg  [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i;\n      wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i;\n      wire any_aid_match;\n      wire any_rid_match;\n      wire accept_limit;\n      wire any_push;\n      wire any_pop;\n        \n      axi_crossbar_v2_1_23_arbiter_resp #  // Multi-thread response arbiter\n        (\n         .C_FAMILY                (C_FAMILY),\n         .C_NUM_S                 (C_NUM_M+1),\n         .C_NUM_S_LOG             (P_NUM_M_DE_LOG),\n         .C_GRANT_ENC            (1),\n         .C_GRANT_HOT            (0)\n         )\n        arbiter_resp_inst\n          (\n           .ACLK                  (ACLK),\n           .ARESET                (ARESET),\n           .S_VALID               (m_rvalid_qual),\n           .S_READY               (m_rready_arb),\n           .M_GRANT_HOT           (),\n           .M_GRANT_ENC           (resp_select),\n           .M_VALID               (s_rvalid_i),\n           .M_READY               (S_RREADY)\n           );\n                 \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (C_FAMILY),\n         .C_RATIO       (C_NUM_M+1),\n         .C_SEL_WIDTH   (P_NUM_M_DE_LOG),\n         .C_DATA_WIDTH  (P_RMUX_MESG_WIDTH)\n        ) mux_resp_multi_thread\n        (\n         .S   (resp_select),\n         .A   (mi_rmux_mesg),\n         .O   (si_rmux_mesg),\n         .OE  (1'b1)\n        ); \n        \n      assign any_push = M_AREADY;\n      assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i;\n      assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop;  // Allow next push if a transaction is currently being completed\n        assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit;  // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads.\n        assign any_aid_match = |aid_match;\n        assign any_rid_match = |rid_match;\n        assign accum_push[0] = 1'b0;\n        \n        always @(posedge ACLK) begin\n          if (ARESET) begin\n            accept_cnt <= 0; \n          end else begin\n            if (any_push & ~any_pop) begin\n              accept_cnt <= accept_cnt + 1;\n          end else if (any_pop & ~any_push & (accept_cnt != 0)) begin\n              accept_cnt <= accept_cnt - 1;\n            end\n          end \n        end  // Clocked process\n          \n        for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop\n          assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0);\n          assign aid_match[gen_thread] =  // The currect thread is active for the requested transaction if\n            thread_valid[gen_thread] &&  // this thread slot is not vacant, and\n          ((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]);  // the requested ID matches the active ID for this thread.\n          assign s_avalid_en[gen_thread] =  // The current request is qualified against this thread slot if\n            (~aid_match[gen_thread]) ||  // This thread slot is not active for the requested ID, or\n            ((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) &&  // this outstanding transaction was to the same target and\n            (m_aregion_i == active_region[gen_thread*8+:4]));  // to the same region.\n          \n          // cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot.\n          assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread];\n          assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread]));\n          \n          // cmd_pop points to the position of the active thread that matches the current RID.\n        assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]);\n          assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread];\n        \n          always @(posedge ACLK) begin\n            if (ARESET) begin\n              active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0;\n              active_target[gen_thread*8+:8] <= 0;\n              active_region[gen_thread*8+:8] <= 0;\n              active_cnt[gen_thread*8+:8] <= 0; \n            end else begin\n              if (cmd_push[gen_thread]) begin\n              active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];\n                active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i;\n                active_region[gen_thread*8+:4] <= m_aregion_i;\n                if (~cmd_pop[gen_thread]) begin\n                  active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1;\n                end\n              end else if (cmd_pop[gen_thread]) begin\n                  active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1;\n              end\n            end \n          end  // Clocked process\n            \n        if (C_DEBUG) begin : gen_debug_r_multi_thread\n            // DEBUG READ BEAT COUNTER (only meaningful for R-channel)\n            always @(posedge ACLK) begin\n              if (ARESET) begin\n                debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;\n              end else if (C_DIR == P_READ) begin\n                if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin\n                  if (s_rlast_i) begin\n                    debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;\n                  end else begin\n                    debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1;\n                  end\n                end\n              end else begin\n                debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;            \n              end\n            end  // Clocked process\n            \n            // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO\n            axi_data_fifo_v2_1_21_axic_srl_fifo #\n              (\n               .C_FAMILY          (C_FAMILY),\n               .C_FIFO_WIDTH      (8),\n               .C_FIFO_DEPTH_LOG  (C_ACCEPTANCE_LOG+1),\n               .C_USE_FULL        (0)\n               )\n            debug_r_seq_fifo_multi_thread\n                (\n                 .ACLK    (ACLK),\n                 .ARESET  (ARESET),\n                 .S_MESG  (DEBUG_A_TRANS_SEQ),\n                 .S_VALID (cmd_push[gen_thread]),\n                 .S_READY (),\n                 .M_MESG  (debug_r_trans_seq_i[gen_thread*8+:8]),\n                 .M_VALID (),\n                 .M_READY (cmd_pop[gen_thread])\n                );\n        end  // gen_debug_r_multi_thread\n      end  // Next gen_thread_loop\n            \n    end  // thread control\n        \n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: AXI Splitter\n// Each transfer received on the AXI handshake slave port is replicated onto \n//   each of the master ports, and is completed back to the slave (S_READY) \n//   once all master ports have completed.\n//   \n// M_VALID is asserted combinatorially from S_VALID assertion.\n// Each M_VALID is masked off beginning the cycle after each M_READY is\n//   received (if S_READY remains low) until the cycle after both S_VALID\n//   and S_READY are asserted.\n// S_READY is asserted combinatorially when the last (or all) of the M_READY\n//   inputs have been received.\n// If all M_READYs are asserted when S_VALID is asserted, back-to-back\n//   handshakes can occur without bubble cycles.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   splitter\n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_splitter #\n  (\n   parameter integer C_NUM_M = 2  // Number of master ports = [2:16]\n   )\n  (\n   // Global Signals\n   input  wire                             ACLK,\n   input  wire                             ARESET,\n   // Slave  Port\n   input  wire                             S_VALID,\n   output wire                             S_READY,\n   // Master Ports\n   output wire [C_NUM_M-1:0]               M_VALID,\n   input  wire [C_NUM_M-1:0]               M_READY\n   );\n\n   reg  [C_NUM_M-1:0] m_ready_d = 0;\n   wire               s_ready_i;\n   wire [C_NUM_M-1:0] m_valid_i;\n\n   always @(posedge ACLK) begin\n      if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1'b0}};\n      else                    m_ready_d <= m_ready_d | (m_valid_i & M_READY);\n   end\n\n   assign s_ready_i = &(m_ready_d | M_READY);\n   assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d;\n   assign M_VALID = m_valid_i;\n   assign S_READY = s_ready_i;\n\nendmodule\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: wdata_mux.v\n//\n// Description: \n//   Contains MI-side write command queue.\n//   SI-slot index selected by AW arbiter is pushed onto queue when S_AVALID transfer is received.\n//   Queue is popped when WLAST data beat is transferred.\n//   W-channel input from SI-slot selected by queue output is transferred to MI-side output .\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    wdata_mux\n//      axic_reg_srl_fifo\n//      mux_enc\n//      \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_wdata_mux #\n  (\n   parameter         C_FAMILY       = \"none\", // FPGA Family.\n   parameter integer C_WMESG_WIDTH            =  1, // Width of W-channel payload.\n   parameter integer C_NUM_SLAVE_SLOTS     =  1, // Number of S_* ports.\n   parameter integer C_SELECT_WIDTH      =  1, // Width of ASELECT.\n   parameter integer C_FIFO_DEPTH_LOG     =  0 // Queue depth = 2**C_FIFO_DEPTH_LOG.\n   )\n  (\n   // System Signals\n   input  wire                                        ACLK,\n   input  wire                                        ARESET,\n   // Slave Data Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_WMESG_WIDTH-1:0]     S_WMESG,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                S_WLAST,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                S_WVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                S_WREADY,\n   // Master Data Ports\n   output wire [C_WMESG_WIDTH-1:0]                       M_WMESG,\n   output wire                                        M_WLAST,\n   output wire                                        M_WVALID,\n   input  wire                                        M_WREADY,\n   // Write Command Ports\n   input  wire [C_SELECT_WIDTH-1:0]                 S_ASELECT,  // SI-slot index from AW arbiter\n   input  wire                                        S_AVALID,\n   output wire                                        S_AREADY\n   );\n\n  localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5;  // Max depth = 32\n  \n  // Decode select input to 1-hot\n  function [C_NUM_SLAVE_SLOTS-1:0] f_decoder (\n      input [C_SELECT_WIDTH-1:0] sel\n    );\n    integer i;\n    begin\n      for (i=0; i<C_NUM_SLAVE_SLOTS; i=i+1) begin\n        f_decoder[i] = (sel == i);\n      end\n    end\n  endfunction\n\n  wire                                          m_valid_i;\n  wire                                          m_last_i;\n  wire [C_NUM_SLAVE_SLOTS-1:0]             m_select_hot;\n  wire [C_SELECT_WIDTH-1:0]                 m_select_enc;\n  wire                                          m_avalid;\n  wire                                          m_aready;\n  \n  generate\n    if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux\n      // SI-side write command queue\n      axi_data_fifo_v2_1_21_axic_reg_srl_fifo #\n        (\n         .C_FAMILY          (C_FAMILY),\n         .C_FIFO_WIDTH      (C_SELECT_WIDTH),\n         .C_FIFO_DEPTH_LOG  (P_FIFO_DEPTH_LOG),\n         .C_USE_FULL        (0)\n         )\n        wmux_aw_fifo\n          (\n           .ACLK    (ACLK),\n           .ARESET  (ARESET),\n           .S_MESG  (S_ASELECT),\n           .S_VALID (S_AVALID),\n           .S_READY (S_AREADY),\n           .M_MESG  (m_select_enc),\n           .M_VALID (m_avalid),\n           .M_READY (m_aready)\n           );\n    \n      assign m_select_hot = f_decoder(m_select_enc);\n      \n      // Instantiate MUX\n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_SLAVE_SLOTS),\n         .C_SEL_WIDTH   (C_SELECT_WIDTH),\n         .C_DATA_WIDTH  (C_WMESG_WIDTH)\n        ) mux_w \n        (\n         .S   (m_select_enc),\n         .A   (S_WMESG),\n         .O   (M_WMESG),\n         .OE  (1'b1)\n        ); \n        \n      assign m_last_i  = |(S_WLAST & m_select_hot);\n      assign m_valid_i = |(S_WVALID & m_select_hot);\n      \n      assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY;\n      assign M_WLAST = m_last_i;\n      assign M_WVALID = m_valid_i & m_avalid;\n      assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}};\n    end else begin : gen_no_wmux\n      assign S_AREADY = 1'b1;\n      assign M_WVALID = S_WVALID;\n      assign S_WREADY = M_WREADY;\n      assign M_WLAST = S_WLAST;\n      assign M_WMESG = S_WMESG;\n    end\n  endgenerate\n  \nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: wdata_router.v\n//\n// Description: \n//   Contains SI-side write command queue.\n//   Target MI-slot index is pushed onto queue when S_AVALID transfer is received.\n//   Queue is popped when WLAST data beat is transferred.\n//   W-channel input is transferred to MI-slot output selected by queue output.\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    wdata_router\n//      axic_reg_srl_fifo\n//      \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_wdata_router #\n  (\n   parameter         C_FAMILY       = \"none\", // FPGA Family.\n   parameter integer C_WMESG_WIDTH          = 1, // Width of all data signals\n   parameter integer C_NUM_MASTER_SLOTS     = 1, // Number of M_* ports.\n   parameter integer C_SELECT_WIDTH     =  1, // Width of S_ASELECT.\n   parameter integer C_FIFO_DEPTH_LOG     =  0 // Queue depth = 2**C_FIFO_DEPTH_LOG.\n   )\n  (\n   // System Signals\n   input  wire                                        ACLK,\n   input  wire                                        ARESET,\n   // Slave Data Ports\n   input  wire [C_WMESG_WIDTH-1:0]                    S_WMESG,\n   input  wire                                        S_WLAST,\n   input  wire                                        S_WVALID,\n   output wire                                        S_WREADY,\n   // Master Data Ports\n   output wire [C_WMESG_WIDTH-1:0]                    M_WMESG,  // Broadcast to all MI-slots\n   output wire                                        M_WLAST,  // Broadcast to all MI-slots\n   output wire [C_NUM_MASTER_SLOTS-1:0]               M_WVALID,  // Per MI-slot\n   input  wire [C_NUM_MASTER_SLOTS-1:0]               M_WREADY,  // Per MI-slot\n   // Address Arbiter Ports\n   input  wire [C_SELECT_WIDTH-1:0]                   S_ASELECT,  // Target MI-slot index from SI-side AW command\n   input  wire                                        S_AVALID,\n   output wire                                        S_AREADY\n   );\n\n  localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5;  // Max depth = 32\n\n  // Decode select input to 1-hot\n  function [C_NUM_MASTER_SLOTS-1:0] f_decoder (\n      input [C_SELECT_WIDTH-1:0] sel\n    );\n    integer i;\n    begin\n      for (i=0; i<C_NUM_MASTER_SLOTS; i=i+1) begin\n        f_decoder[i] = (sel == i);\n      end\n    end\n  endfunction\n\n  //---------------------------------------------------------------------------\n  // Internal signal declarations\n  //---------------------------------------------------------------------------\n  wire [C_NUM_MASTER_SLOTS-1:0]             m_select_hot;\n  wire [C_SELECT_WIDTH-1:0]                 m_select_enc;\n  wire                                          m_avalid;\n  wire                                          m_aready;\n  \n  //---------------------------------------------------------------------------\n  // Router\n  //---------------------------------------------------------------------------\n\n  // SI-side write command queue\n  axi_data_fifo_v2_1_21_axic_reg_srl_fifo #\n    (\n     .C_FAMILY          (C_FAMILY),\n     .C_FIFO_WIDTH      (C_SELECT_WIDTH),\n     .C_FIFO_DEPTH_LOG  (P_FIFO_DEPTH_LOG),\n     .C_USE_FULL        (1)\n     )\n    wrouter_aw_fifo\n      (\n       .ACLK    (ACLK),\n       .ARESET  (ARESET),\n       .S_MESG  (S_ASELECT),\n       .S_VALID (S_AVALID),\n       .S_READY (S_AREADY),\n       .M_MESG  (m_select_enc),\n       .M_VALID (m_avalid),\n       .M_READY (m_aready)\n       );\n\n  assign m_select_hot = f_decoder(m_select_enc);\n  \n  // W-channel payload and LAST are broadcast to all MI-slot's W-mux\n  assign M_WMESG   = S_WMESG;\n  assign M_WLAST =   S_WLAST;\n  \n  // Assert m_aready when last beat acknowledged by slave\n  assign m_aready = m_avalid & S_WVALID & S_WLAST & (|(M_WREADY & m_select_hot));\n\n  // M_WVALID is generated per MI-slot (including error handler at slot C_NUM_MASTER_SLOTS).\n  // The slot selected by the head of the queue (m_select_enc) is enabled.\n  assign M_WVALID = {C_NUM_MASTER_SLOTS{S_WVALID & m_avalid}} & m_select_hot;\n\n  // S_WREADY is muxed from the MI slot selected by the head of the queue (m_select_enc).\n  assign S_WREADY = m_avalid & (|(M_WREADY & m_select_hot));\n  \nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2011-2014 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: axi_crossbar.v\n//-----------------------------------------------------------------------------\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_axi_crossbar # (\n   parameter         C_FAMILY                         = \"rtl\", \n                       // FPGA Base Family. Current version: virtex6 or spartan6.\n   parameter integer C_NUM_SLAVE_SLOTS                = 1, \n                       // Number of Slave Interface (SI) slots for connecting \n                       // to master IP. Range: 1-16.\n   parameter integer C_NUM_MASTER_SLOTS               = 2, \n                       // Number of Master Interface (MI) slots for connecting \n                       // to slave IP. Range: 1-16.                       \n   parameter integer C_AXI_ID_WIDTH                   = 1, \n                       // Width of ID signals propagated by the Interconnect.\n                       // Width of ID signals produced on all MI slots.\n                       // Range: 1-32.\n   parameter integer C_AXI_ADDR_WIDTH                 = 32, \n                       // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and \n                       // m_axi_araddr for all SI/MI slots.\n                       // Range: 1-64.\n   parameter integer C_AXI_DATA_WIDTH        = 32, \n                       // Data width of the internal interconnect write and read \n                       // data paths.\n                       // Range: 32, 64, 128, 256, 512, 1024.\n   parameter integer C_AXI_PROTOCOL                 = 0, \n                       // 0 = \"AXI4\",\n                       // 1 = \"AXI3\", \n                       // 2 = \"AXI4LITE\"\n                       //   Propagate WID only when C_AXI_PROTOCOL = 1.\n   parameter integer C_NUM_ADDR_RANGES = 1,\n                       // Number of BASE/HIGH_ADDR pairs per MI slot.\n                       // Range: 1-16.\n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = 128'h00000000001000000000000000000000,\n                       // Base address of each range of each MI slot. \n                       // For unused ranges, set C_M_AXI_BASE_ADDR[mm*aa*64 +: C_AXI_ADDR_WIDTH] = {C_AXI_ADDR_WIDTH{1'b1}}. \n                       //   (Bit positions above C_AXI_ADDR_WIDTH are ignored.)\n                       // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit64}}.\n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*32-1:0] C_M_AXI_ADDR_WIDTH = 64'H0000000c0000000c, \n                       // Number of low-order address bits that are used to select locations within each address range of each MI slot.\n                       // The High address of each range is derived as BASE_ADDR + 2**C_M_AXI_ADDR_WIDTH -1.\n                       // For used address ranges, C_M_AXI_ADDR_WIDTH must be > 0.\n                       // For unused ranges, set C_M_AXI_ADDR_WIDTH to 32'h00000000.\n                       // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit32}}.\n                       // Range: 0 - C_AXI_ADDR_WIDTH.\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_BASE_ID = 32'h00000000,\n                       // Base ID of each SI slot. \n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 0 to 2**C_AXI_ID_WIDTH-1.\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = 32'h00000000,\n                       // Number of low-order ID bits a connected master may vary to select a transaction thread.\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 0 - C_AXI_ID_WIDTH.\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS      = 0,\n                       // 1 = Propagate all USER signals, 0 = Dont propagate.\n   parameter integer C_AXI_AWUSER_WIDTH               = 1,\n                       // Width of AWUSER signals for all SI slots and MI slots. \n                       // Range: 1-1024.\n   parameter integer C_AXI_ARUSER_WIDTH               = 1,\n                       // Width of ARUSER signals for all SI slots and MI slots. \n                       // Range: 1-1024.\n   parameter integer C_AXI_WUSER_WIDTH                = 1,\n                       // Width of WUSER signals for all SI slots and MI slots. \n                       // Range: 1-1024.\n   parameter integer C_AXI_RUSER_WIDTH                = 1,\n                       // Width of RUSER signals for all SI slots and MI slots. \n                       // Range: 1-1024.\n   parameter integer C_AXI_BUSER_WIDTH                = 1,\n                       // Width of BUSER signals for all SI slots and MI slots. \n                       // Range: 1-1024.\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,\n                       // Multi-pathway write connectivity from each SI slot (N) to each \n                       // MI slot (M):\n                       // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)\n                       // Format: C_NUM_MASTER_SLOTS{Bit32}; \n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,\n                       // Multi-pathway read connectivity from each SI slot (N) to each \n                       // MI slot (M):\n                       // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)\n                       // Format: C_NUM_MASTER_SLOTS{Bit32}; \n   parameter integer C_R_REGISTER               = 0,\n                       // Insert register slice on R channel in the crossbar. (Valid only for SASD)\n                       // Range: Reg-slice type (0-8).\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD                 = 32'h00000000, \n                       // 0 = Implement separate command queues per ID thread.\n                       // 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD)\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32}; \n                       // Range: 0, 1\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE         = 32'H00000002,\n                       // Maximum number of active write transactions that each SI \n                       // slot can accept. (Valid only for SAMD)\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32}; \n                       // Range: 1-32.\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE          = 32'H00000002,\n                       // Maximum number of active read transactions that each SI \n                       // slot can accept. (Valid only for SAMD)\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 1-32.\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING            = 64'H0000000400000004,\n                       // Maximum number of data-active write transactions that \n                       // each MI slot can generate at any one time. (Valid only for SAMD)\n                       // Format: C_NUM_MASTER_SLOTS{Bit32};\n                       // Range: 1-32.\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING            = 64'H0000000400000004,\n                       // Maximum number of active read transactions that \n                       // each MI slot can generate at any one time. (Valid only for SAMD)\n                       // Format: C_NUM_MASTER_SLOTS{Bit32};\n                       // Range: 1-32.\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY             = 32'h00000000,\n                       // Arbitration priority among each SI slot. \n                       // Higher values indicate higher priority.\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 0-15.\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE                   = 32'h00000000,\n                       // Indicates whether each MI slot connects to a secure slave \n                       // (allows only TrustZone secure access).\n                       // Format: C_NUM_MASTER_SLOTS{Bit32}.\n                       // Range: 0, 1\n   parameter integer C_CONNECTIVITY_MODE = 1\n                       // 0 = Shared-Address Shared-Data (SASD).\n                       // 1 = Shared-Address Multi-Data (SAMD).\n                       // Default 1 (on) for simulation; default 0 (off) for implementation.\n)\n(\n   // Global Signals\n   input  wire                                                    aclk,\n   input  wire                                                    aresetn,\n   // Slave Interface Write Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_awid,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           s_axi_awaddr,\n   input  wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          s_axi_awsize,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          s_axi_awburst,\n   input  wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_awcache,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          s_axi_awprot,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_awregion,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_awqos,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0]         s_axi_awuser,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_awvalid,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_awready,\n   // Slave Interface Write Data Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_wid,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]           s_axi_wdata,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0]         s_axi_wstrb,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_wlast,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0]          s_axi_wuser,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_wvalid,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_wready,\n   // Slave Interface Write Response Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_bid,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          s_axi_bresp,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0]          s_axi_buser,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_bvalid,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_bready,\n   // Slave Interface Read Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_arid,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           s_axi_araddr,\n   input  wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          s_axi_arsize,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          s_axi_arburst,\n   input  wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_arcache,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          s_axi_arprot,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_arregion,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_arqos,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0]         s_axi_aruser,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_arvalid,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_arready,\n   // Slave Interface Read Data Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_rid,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]           s_axi_rdata,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          s_axi_rresp,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_rlast,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0]          s_axi_ruser,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_rvalid,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_rready,\n   // Master Interface Write Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_awid,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          m_axi_awaddr,\n   output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         m_axi_awsize,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         m_axi_awburst,\n   output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_awcache,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         m_axi_awprot,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_awregion,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_awqos,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0]        m_axi_awuser,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_awvalid,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_awready,\n   // Master Interface Write Data Ports\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_wid,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]          m_axi_wdata,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0]        m_axi_wstrb,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_wlast,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0]         m_axi_wuser,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_wvalid,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_wready,\n   // Master Interface Write Response Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_bid,\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         m_axi_bresp,\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0]         m_axi_buser,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_bvalid,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_bready,\n   // Master Interface Read Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_arid,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          m_axi_araddr,\n   output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         m_axi_arsize,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         m_axi_arburst,\n   output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_arcache,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         m_axi_arprot,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_arregion,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_arqos,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0]        m_axi_aruser,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_arvalid,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_arready,\n   // Master Interface Read Data Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_rid,\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]          m_axi_rdata,\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         m_axi_rresp,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_rlast,\n   input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0]          m_axi_ruser,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_rvalid,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_rready\n);\n\n  localparam [64:0] P_ONES = {65{1'b1}};\n  localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_BASE_ID = f_base_id(0);\n  localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_HIGH_ID = f_high_id(0);\n  localparam integer  P_AXI4 = 0;\n  localparam integer  P_AXI3 = 1;\n  localparam integer  P_AXILITE = 2;\n  localparam [2:0]   P_AXILITE_SIZE = 3'b010;\n  localparam [1:0]   P_INCR = 2'b01;\n  localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_WRITE = f_m_supports_write(0);\n  localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_READ = f_m_supports_read(0);\n  localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_WRITE = f_s_supports_write(0);\n  localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_READ = f_s_supports_read(0);\n  localparam integer C_DEBUG              = 1;\n  localparam integer P_RANGE_CHECK                    = 1;\n                       // 1 (non-zero) = Detect and issue DECERR on the following conditions:\n                       //   a. address range mismatch (no valid MI slot)\n                       //   b. Burst or >32-bit transfer to AxiLite slave\n                       //   c. TrustZone access violation\n                       //   d. R/W direction unsupported by target\n                       // 0 = Pass all transactions (no DECERR):\n                       //   a. Omit DECERR detection and response logic\n                       //   b. Omit address decoder and propagate s_axi_a*REGION to m_axi_a*REGION\n                       //      when C_NUM_MASTER_SLOTS=1 and C_NUM_ADDR_RANGES=1.\n                       //   c. Unpredictable target MI-slot if address mismatch and >1 MI-slot\n                       //   d. Transaction corruption if any burst or >32-bit transfer to AxiLite slave\n                       // Illegal combination: P_RANGE_CHECK = 0 && C_M_AXI_SECURE != 0.\n  localparam integer P_ADDR_DECODE = ((P_RANGE_CHECK == 1) || (C_NUM_MASTER_SLOTS > 1) || (C_NUM_ADDR_RANGES > 1)) ? 1 : 0;  // Always 1\n  localparam [C_NUM_MASTER_SLOTS*32-1:0] P_M_AXI_ERR_MODE            = {C_NUM_MASTER_SLOTS{32'h00000000}};\n                       // Transaction error detection (per MI-slot)\n                       // 0 = None; 1 = AXI4Lite burst violation\n                       // Format: C_NUM_MASTER_SLOTS{Bit32};\n  localparam integer P_LEN = (C_AXI_PROTOCOL == P_AXI3) ? 4 : 8;\n  localparam integer P_LOCK = (C_AXI_PROTOCOL == P_AXI3) ? 2 : 1;\n  localparam P_FAMILY = ((C_FAMILY == \"virtex7\") || (C_FAMILY == \"kintex7\") || (C_FAMILY == \"artix7\") || (C_FAMILY == \"zynq\")) ? C_FAMILY : \"rtl\";\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  // Widths of all write issuance counters implemented in axi_crossbar_v2_1_23_crossbar (before counter carry-out bit)\n  function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_write_issue_width_vec\n    (input null_arg);\n    integer mi;\n    reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;\n    begin\n      result = 0;\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_WRITE_ISSUING[mi*32+:32]);\n      end\n      result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;\n      f_write_issue_width_vec = result;\n    end\n  endfunction\n\n  // Widths of all read issuance counters implemented in axi_crossbar_v2_1_23_crossbar (before counter carry-out bit)\n  function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_read_issue_width_vec\n    (input null_arg);\n    integer mi;\n    reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;\n    begin\n      result = 0;\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_READ_ISSUING[mi*32+:32]);\n      end\n      result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;\n      f_read_issue_width_vec = result;\n    end\n  endfunction\n\n  // Widths of all write acceptance counters implemented in axi_crossbar_v2_1_23_crossbar (before counter carry-out bit)\n  function [C_NUM_SLAVE_SLOTS*32-1:0] f_write_accept_width_vec\n    (input null_arg);\n    integer si;\n    reg [C_NUM_SLAVE_SLOTS*32-1:0] result;\n    begin\n      result = 0;\n      for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin\n        result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_WRITE_ACCEPTANCE[si*32+:32]);\n      end\n      f_write_accept_width_vec = result;\n    end\n  endfunction\n\n  // Widths of all read acceptance counters implemented in axi_crossbar_v2_1_23_crossbar (before counter carry-out bit)\n  function [C_NUM_SLAVE_SLOTS*32-1:0] f_read_accept_width_vec\n    (input null_arg);\n    integer si;\n    reg [C_NUM_SLAVE_SLOTS*32-1:0] result;\n    begin\n      result = 0;\n      for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin\n        result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_READ_ACCEPTANCE[si*32+:32]);\n      end\n      f_read_accept_width_vec = result;\n    end\n  endfunction\n\n  // Convert C_S_AXI_BASE_ID vector from Bit32 to Bit64 format\n  function [C_NUM_SLAVE_SLOTS*64-1:0] f_base_id\n    (input null_arg);\n    integer si;\n    reg [C_NUM_SLAVE_SLOTS*64-1:0] result;\n    begin\n      result = 0;\n      for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin\n        result[si*64+:C_AXI_ID_WIDTH] = C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH];\n      end\n      f_base_id = result;\n    end\n  endfunction\n\n  // Construct P_S_HIGH_ID vector\n  function [C_NUM_SLAVE_SLOTS*64-1:0] f_high_id\n    (input null_arg);\n    integer si;\n    reg [C_NUM_SLAVE_SLOTS*64-1:0] result;\n    begin\n      result = 0;\n      for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin\n        result[si*64+:C_AXI_ID_WIDTH] = (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :\n          ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :\n          (C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));\n      end\n      f_high_id = result;\n    end\n  endfunction\n\n  // Construct P_M_HIGH_ADDR vector\n  function [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] f_high_addr\n    (input null_arg);\n    integer ar;\n    reg [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] result;\n    begin\n      result = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}};\n      for (ar=0; ar<C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES; ar=ar+1) begin\n        result[ar*64+:C_AXI_ADDR_WIDTH] = (C_M_AXI_ADDR_WIDTH[ar*32+:32] == 0) ? 64'h00000000_00000000 : \n          ({1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:31]} >= C_AXI_ADDR_WIDTH) ? {C_AXI_ADDR_WIDTH{1'b1}} :\n          (C_M_AXI_BASE_ADDR[ar*64+:C_AXI_ADDR_WIDTH] | ~(P_ONES << {1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:7]}));\n      end\n      f_high_addr = result;\n    end\n  endfunction\n\n  // Generate a mask of valid ID bits for a given SI slot.\n  function [C_AXI_ID_WIDTH-1:0] f_thread_id_mask\n    (input integer si);\n    begin\n      f_thread_id_mask = \n        (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? {C_AXI_ID_WIDTH{1'b0}} : \n        ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :\n        ({C_AXI_ID_WIDTH{1'b0}} | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));\n      end\n  endfunction\n\n  // Isolate thread bits of input S_ID and add to BASE_ID to form MI-side ID value\n  //   only for end-point SI-slots\n  function [C_AXI_ID_WIDTH-1:0] f_extend_ID (\n    input [C_AXI_ID_WIDTH-1:0] s_id,\n    input integer si\n    );\n    begin\n      f_extend_ID = \n        (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] : \n        ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? s_id :\n        (C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | (s_id &  ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]})));\n    end\n  endfunction\n\n  // Bit vector of SI slots with at least one write connection.\n  function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_write\n    (input null_arg);\n    integer mi;\n    reg [C_NUM_SLAVE_SLOTS-1:0] result;\n    begin\n      result = {C_NUM_SLAVE_SLOTS{1'b0}};\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        result = result | C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];\n      end\n      f_s_supports_write = result;\n    end\n  endfunction\n\n  // Bit vector of SI slots with at least one read connection.\n  function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_read\n    (input null_arg);\n    integer mi;\n    reg [C_NUM_SLAVE_SLOTS-1:0] result;\n    begin\n      result = {C_NUM_SLAVE_SLOTS{1'b0}};\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        result = result | C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];\n      end\n      f_s_supports_read = result;\n    end\n  endfunction\n\n  // Bit vector of MI slots with at least one write connection.\n  function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_write\n    (input null_arg);\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        f_m_supports_write[mi] = (|C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);\n      end\n    end\n  endfunction\n\n  // Bit vector of MI slots with at least one read connection.\n  function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_read\n    (input null_arg);\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        f_m_supports_read[mi] = (|C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);\n      end\n    end\n  endfunction\n\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_awid            ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]        si_cb_awaddr          ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                       si_cb_awlen           ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                       si_cb_awsize          ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_awburst         ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_awlock          ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_awcache         ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                       si_cb_awprot          ;\n//  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_awregion        ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_awqos           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0]      si_cb_awuser          ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_awvalid         ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_awready         ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_wid            ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]        si_cb_wdata           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0]      si_cb_wstrb           ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_wlast           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0]       si_cb_wuser           ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_wvalid          ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_wready          ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_bid             ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_bresp           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0]       si_cb_buser           ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_bvalid          ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_bready          ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_arid            ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]        si_cb_araddr          ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                       si_cb_arlen           ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                       si_cb_arsize          ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_arburst         ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_arlock          ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_arcache         ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                       si_cb_arprot          ;\n//  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_arregion        ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_arqos           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0]      si_cb_aruser          ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_arvalid         ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_arready         ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_rid             ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]        si_cb_rdata           ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_rresp           ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_rlast           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0]       si_cb_ruser           ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_rvalid          ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_rready          ;\n\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_awid            ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]       cb_mi_awaddr          ;\n  wire [C_NUM_MASTER_SLOTS*8-1:0]                      cb_mi_awlen           ;\n  wire [C_NUM_MASTER_SLOTS*3-1:0]                      cb_mi_awsize          ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_awburst         ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_awlock          ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_awcache         ;\n  wire [C_NUM_MASTER_SLOTS*3-1:0]                      cb_mi_awprot          ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_awregion        ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_awqos           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0]     cb_mi_awuser          ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_awvalid         ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_awready         ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_wid             ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]       cb_mi_wdata           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0]     cb_mi_wstrb           ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_wlast           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0]      cb_mi_wuser           ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_wvalid          ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_wready          ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_bid             ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_bresp           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0]      cb_mi_buser           ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_bvalid          ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_bready          ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_arid            ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]       cb_mi_araddr          ;\n  wire [C_NUM_MASTER_SLOTS*8-1:0]                      cb_mi_arlen           ;\n  wire [C_NUM_MASTER_SLOTS*3-1:0]                      cb_mi_arsize          ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_arburst         ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_arlock          ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_arcache         ;\n  wire [C_NUM_MASTER_SLOTS*3-1:0]                      cb_mi_arprot          ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_arregion        ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_arqos           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0]     cb_mi_aruser          ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_arvalid         ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_arready         ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_rid             ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]       cb_mi_rdata           ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_rresp           ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_rlast           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0]      cb_mi_ruser           ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_rvalid          ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_rready          ;\n  \n  genvar slot;\n\ngenerate\n    for (slot=0;slot<C_NUM_SLAVE_SLOTS;slot=slot+1) begin : gen_si_tieoff\n      assign si_cb_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? (s_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))              : 0 ;\n      assign si_cb_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       : 0 ;\n      assign si_cb_awlen[slot*8+:8]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awlen[slot*P_LEN+:P_LEN] : 0 ;\n      assign si_cb_awsize[slot*3+:3]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awsize[slot*3+:3]                                                     : P_AXILITE_SIZE ;\n      assign si_cb_awburst[slot*2+:2]                                                    = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awburst[slot*2+:2]                                                    : P_INCR ;\n      assign si_cb_awlock[slot*2+:2]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? {1'b0, s_axi_awlock[slot*P_LOCK+:1]}                                             : 0 ;\n      assign si_cb_awcache[slot*4+:4]                                                    = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awcache[slot*4+:4]                                                    : 0 ;\n      assign si_cb_awprot[slot*3+:3]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_awprot[slot*3+:3]                                                     : 0 ;\n      assign si_cb_awqos[slot*4+:4]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awqos[slot*4+:4]                                                      : 0 ;\n//      assign si_cb_awregion[slot*4+:4]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4)                                ) ? s_axi_awregion[slot*4+:4]                                                      : 0 ;\n      assign si_cb_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH]                   = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH]                   : 0 ;\n      assign si_cb_awvalid[slot*1+:1]                                                    = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_awvalid[slot*1+:1]                                                    : 0 ;\n      assign si_cb_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI3)                                   ) ? (s_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))   : 0 ;\n      assign si_cb_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]                        = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]     : 0 ;\n      assign si_cb_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]                    = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;\n      assign si_cb_wlast[slot*1+:1]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_wlast[slot*1+:1]                                                      : 1'b1 ;\n      assign si_cb_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]                      : 0 ;\n      assign si_cb_wvalid[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_wvalid[slot*1+:1]                                                     : 0 ;\n      assign si_cb_bready[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_bready[slot*1+:1]                                                     : 0 ;\n      assign si_cb_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? (s_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))              : 0 ;\n      assign si_cb_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? s_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       : 0 ;\n      assign si_cb_arlen[slot*8+:8]                                                      = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_arlen[slot*P_LEN+:P_LEN] : 0 ;\n      assign si_cb_arsize[slot*3+:3]                                                     = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_arsize[slot*3+:3]                                                     : P_AXILITE_SIZE ;\n      assign si_cb_arburst[slot*2+:2]                                                    = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_arburst[slot*2+:2]                                                    : P_INCR ;\n      assign si_cb_arlock[slot*2+:2]                                                     = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? {1'b0, s_axi_arlock[slot*P_LOCK+:1]}                                             : 0 ;\n      assign si_cb_arcache[slot*4+:4]                                                    = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                  ) ? s_axi_arcache[slot*4+:4]                                                    : 0 ;\n      assign si_cb_arprot[slot*3+:3]                                                     = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? s_axi_arprot[slot*3+:3]                                                     : 0 ;\n      assign si_cb_arqos[slot*4+:4]                                                      = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_arqos[slot*4+:4]                                                      : 0 ;\n//      assign si_cb_arregion[slot*4+:4]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4)                                ) ? s_axi_arregion[slot*4+:4]                                                      : 0 ;\n      assign si_cb_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH]                   = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH]                   : 0 ;\n      assign si_cb_arvalid[slot*1+:1]                                                    = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? s_axi_arvalid[slot*1+:1]                                                    : 0 ;\n      assign si_cb_rready[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? s_axi_rready[slot*1+:1]                                                     : 0 ;                                       \n\n      assign s_axi_awready[slot*1+:1]                                                    = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? si_cb_awready[slot*1+:1]                                                    : 0 ;\n      assign s_axi_wready[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? si_cb_wready[slot*1+:1]                                                     : 0 ;\n      assign s_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? (si_cb_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))               : 0 ;\n      assign s_axi_bresp[slot*2+:2]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? si_cb_bresp[slot*2+:2]                                                      : 0 ;\n      assign s_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                      : 0 ;\n      assign s_axi_bvalid[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? si_cb_bvalid[slot*1+:1]                                                     : 0 ;\n      assign s_axi_arready[slot*1+:1]                                                    = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? si_cb_arready[slot*1+:1]                                                    : 0 ;\n      assign s_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? (si_cb_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))               : 0 ;\n      assign s_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]                        = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? si_cb_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]     : 0 ;\n      assign s_axi_rresp[slot*2+:2]                                                      = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? si_cb_rresp[slot*2+:2]                                                      : 0 ;\n      assign s_axi_rlast[slot*1+:1]                                                      = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? si_cb_rlast[slot*1+:1]                                                      : 0 ;\n      assign s_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                      = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                      : 0 ;\n      assign s_axi_rvalid[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? si_cb_rvalid[slot*1+:1]                                                     : 0 ;\n    end  // gen_si_tieoff\n\n    for (slot=0;slot<C_NUM_MASTER_SLOTS;slot=slot+1) begin : gen_mi_tieoff\n      assign m_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             : 0 ;\n      assign m_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       : 0 ;\n      assign m_axi_awlen[slot*P_LEN+:P_LEN]                                              = (~P_M_AXI_SUPPORTS_WRITE[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4                             ) ? cb_mi_awlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_awlen[slot*8+:4] : 0 ;\n      assign m_axi_awsize[slot*3+:3]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awsize[slot*3+:3]                                                     : 0 ;\n      assign m_axi_awburst[slot*2+:2]                                                    = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awburst[slot*2+:2]                                                    : 0 ;\n      assign m_axi_awlock[slot*P_LOCK+:P_LOCK]                                           = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awlock[slot*2+:1]                                                     : 0 ;\n      assign m_axi_awcache[slot*4+:4]                                                    = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awcache[slot*4+:4]                                                    : 0 ;\n      assign m_axi_awprot[slot*3+:3]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_awprot[slot*3+:3]                                                     : 0 ;\n      assign m_axi_awregion[slot*4+:4]                                                   = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL==P_AXI4)                                 ) ? cb_mi_awregion[slot*4+:4]                                                   : 0 ;\n      assign m_axi_awqos[slot*4+:4]                                                      = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awqos[slot*4+:4]                                                      : 0 ;\n      assign m_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH]                   = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH]                   : 0 ;\n      assign m_axi_awvalid[slot*1+:1]                                                    = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_awvalid[slot*1+:1]                                                    : 0 ;\n      assign m_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              : 0 ;\n      assign m_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]                        = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]     : 0 ;\n      assign m_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]                    = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;\n      assign m_axi_wlast[slot*1+:1]                                                      = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_wlast[slot*1+:1]                                                      : 0 ;\n      assign m_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]                      = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]                      : 0 ;\n      assign m_axi_wvalid[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_wvalid[slot*1+:1]                                                     : 0 ;\n      assign m_axi_bready[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_bready[slot*1+:1]                                                     : 0 ;\n      assign m_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                            : 0 ;\n      assign m_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? cb_mi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       : 0 ;\n      assign m_axi_arlen[slot*P_LEN+:P_LEN]                                              = (~P_M_AXI_SUPPORTS_READ[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4                             ) ? cb_mi_arlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_arlen[slot*8+:4] : 0 ;\n      assign m_axi_arsize[slot*3+:3]                                                     = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arsize[slot*3+:3]                                                     : 0 ;\n      assign m_axi_arburst[slot*2+:2]                                                    = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arburst[slot*2+:2]                                                    : 0 ;\n      assign m_axi_arlock[slot*P_LOCK+:P_LOCK]                                           = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arlock[slot*2+:1]                                                     : 0 ;\n      assign m_axi_arcache[slot*4+:4]                                                    = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arcache[slot*4+:4]                                                    : 0 ;\n      assign m_axi_arprot[slot*3+:3]                                                     = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? cb_mi_arprot[slot*3+:3]                                                     : 0 ;\n      assign m_axi_arregion[slot*4+:4]                                                   = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL==P_AXI4)                                 ) ? cb_mi_arregion[slot*4+:4]                                                   : 0 ;\n      assign m_axi_arqos[slot*4+:4]                                                      = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arqos[slot*4+:4]                                                      : 0 ;\n      assign m_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH]                   = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH]                   : 0 ;\n      assign m_axi_arvalid[slot*1+:1]                                                    = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? cb_mi_arvalid[slot*1+:1]                                                    : 0 ;\n      assign m_axi_rready[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? cb_mi_rready[slot*1+:1]                                                     : 0 ;\n\n      assign cb_mi_awready[slot*1+:1]                                                    = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? m_axi_awready[slot*1+:1]                                                    : 0 ;\n      assign cb_mi_wready[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? m_axi_wready[slot*1+:1]                                                     : 0 ;\n      assign cb_mi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? m_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              : 0 ;\n      assign cb_mi_bresp[slot*2+:2]                                                      = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? m_axi_bresp[slot*2+:2]                                                      : 0 ;\n      assign cb_mi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                      = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                      : 0 ;\n      assign cb_mi_bvalid[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? m_axi_bvalid[slot*1+:1]                                                     : 0 ;\n      assign cb_mi_arready[slot*1+:1]                                                    = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? m_axi_arready[slot*1+:1]                                                    : 0 ;\n      assign cb_mi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? m_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              : 0 ;\n      assign cb_mi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]                        = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? m_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]     : 0 ;\n      assign cb_mi_rresp[slot*2+:2]                                                      = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? m_axi_rresp[slot*2+:2]                                                      : 0 ;\n      assign cb_mi_rlast[slot*1+:1]                                                      = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? m_axi_rlast[slot*1+:1]                                                      : 1'b1 ;\n      assign cb_mi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                      = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                      : 0 ;\n      assign cb_mi_rvalid[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? m_axi_rvalid[slot*1+:1]                                                     : 0 ;\n    end  // gen_mi_tieoff\n\n    if ((C_CONNECTIVITY_MODE==0) || (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_sasd\n      axi_crossbar_v2_1_23_crossbar_sasd #\n      (\n        .C_FAMILY                         (P_FAMILY),\n        .C_NUM_SLAVE_SLOTS                (C_NUM_SLAVE_SLOTS),\n        .C_NUM_MASTER_SLOTS               (C_NUM_MASTER_SLOTS),\n        .C_NUM_ADDR_RANGES                (C_NUM_ADDR_RANGES),\n        .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),\n        .C_AXI_ADDR_WIDTH                 (C_AXI_ADDR_WIDTH),\n        .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),\n        .C_AXI_PROTOCOL                   (C_AXI_PROTOCOL),\n        .C_M_AXI_BASE_ADDR                (C_M_AXI_BASE_ADDR),\n        .C_M_AXI_HIGH_ADDR                (f_high_addr(0)),\n        .C_S_AXI_BASE_ID                  (P_S_AXI_BASE_ID),\n        .C_S_AXI_HIGH_ID                  (P_S_AXI_HIGH_ID),\n        .C_AXI_SUPPORTS_USER_SIGNALS      (C_AXI_SUPPORTS_USER_SIGNALS),\n        .C_AXI_AWUSER_WIDTH               (C_AXI_AWUSER_WIDTH),\n        .C_AXI_ARUSER_WIDTH               (C_AXI_ARUSER_WIDTH),\n        .C_AXI_WUSER_WIDTH                (C_AXI_WUSER_WIDTH),\n        .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),\n        .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),\n        .C_S_AXI_SUPPORTS_WRITE           (P_S_AXI_SUPPORTS_WRITE),\n        .C_S_AXI_SUPPORTS_READ            (P_S_AXI_SUPPORTS_READ),\n        .C_M_AXI_SUPPORTS_WRITE           (P_M_AXI_SUPPORTS_WRITE),\n        .C_M_AXI_SUPPORTS_READ            (P_M_AXI_SUPPORTS_READ),\n        .C_S_AXI_ARB_PRIORITY             (C_S_AXI_ARB_PRIORITY),\n        .C_M_AXI_SECURE                   (C_M_AXI_SECURE),\n        .C_R_REGISTER                     (C_R_REGISTER),\n        .C_RANGE_CHECK                    (P_RANGE_CHECK),\n        .C_ADDR_DECODE                    (P_ADDR_DECODE),\n        .C_M_AXI_ERR_MODE                 (P_M_AXI_ERR_MODE),\n        .C_DEBUG                          (C_DEBUG)\n      )\n        crossbar_sasd_0\n      (\n          .ACLK                             (aclk),\n          .ARESETN                          (aresetn),\n          .S_AXI_AWID                       (si_cb_awid           ),\n          .S_AXI_AWADDR                     (si_cb_awaddr         ),\n          .S_AXI_AWLEN                      (si_cb_awlen          ),\n          .S_AXI_AWSIZE                     (si_cb_awsize         ),\n          .S_AXI_AWBURST                    (si_cb_awburst        ),\n          .S_AXI_AWLOCK                     (si_cb_awlock         ),\n          .S_AXI_AWCACHE                    (si_cb_awcache        ),\n          .S_AXI_AWPROT                     (si_cb_awprot         ),\n//          .S_AXI_AWREGION                   (si_cb_awregion       ),\n          .S_AXI_AWQOS                      (si_cb_awqos          ),\n          .S_AXI_AWUSER                     (si_cb_awuser         ),\n          .S_AXI_AWVALID                    (si_cb_awvalid        ),\n          .S_AXI_AWREADY                    (si_cb_awready        ),\n          .S_AXI_WID                        (si_cb_wid             ),\n          .S_AXI_WDATA                      (si_cb_wdata          ),\n          .S_AXI_WSTRB                      (si_cb_wstrb          ),\n          .S_AXI_WLAST                      (si_cb_wlast          ),\n          .S_AXI_WUSER                      (si_cb_wuser          ),\n          .S_AXI_WVALID                     (si_cb_wvalid         ),\n          .S_AXI_WREADY                     (si_cb_wready         ),\n          .S_AXI_BID                        (si_cb_bid            ),\n          .S_AXI_BRESP                      (si_cb_bresp          ),\n          .S_AXI_BUSER                      (si_cb_buser          ),\n          .S_AXI_BVALID                     (si_cb_bvalid         ),\n          .S_AXI_BREADY                     (si_cb_bready         ),\n          .S_AXI_ARID                       (si_cb_arid           ),\n          .S_AXI_ARADDR                     (si_cb_araddr         ),\n          .S_AXI_ARLEN                      (si_cb_arlen          ),\n          .S_AXI_ARSIZE                     (si_cb_arsize         ),\n          .S_AXI_ARBURST                    (si_cb_arburst        ),\n          .S_AXI_ARLOCK                     (si_cb_arlock         ),\n          .S_AXI_ARCACHE                    (si_cb_arcache        ),\n          .S_AXI_ARPROT                     (si_cb_arprot         ),\n//          .S_AXI_ARREGION                   (si_cb_arregion       ),\n          .S_AXI_ARQOS                      (si_cb_arqos          ),\n          .S_AXI_ARUSER                     (si_cb_aruser         ),\n          .S_AXI_ARVALID                    (si_cb_arvalid        ),\n          .S_AXI_ARREADY                    (si_cb_arready        ),\n          .S_AXI_RID                        (si_cb_rid            ),\n          .S_AXI_RDATA                      (si_cb_rdata          ),\n          .S_AXI_RRESP                      (si_cb_rresp          ),\n          .S_AXI_RLAST                      (si_cb_rlast          ),\n          .S_AXI_RUSER                      (si_cb_ruser          ),\n          .S_AXI_RVALID                     (si_cb_rvalid         ),\n          .S_AXI_RREADY                     (si_cb_rready         ),\n          .M_AXI_AWID                       (cb_mi_awid           ),\n          .M_AXI_AWADDR                     (cb_mi_awaddr         ),\n          .M_AXI_AWLEN                      (cb_mi_awlen          ),\n          .M_AXI_AWSIZE                     (cb_mi_awsize         ),\n          .M_AXI_AWBURST                    (cb_mi_awburst        ),\n          .M_AXI_AWLOCK                     (cb_mi_awlock         ),\n          .M_AXI_AWCACHE                    (cb_mi_awcache        ),\n          .M_AXI_AWPROT                     (cb_mi_awprot         ),\n          .M_AXI_AWREGION                   (cb_mi_awregion       ),\n          .M_AXI_AWQOS                      (cb_mi_awqos          ),\n          .M_AXI_AWUSER                     (cb_mi_awuser         ),\n          .M_AXI_AWVALID                    (cb_mi_awvalid        ),\n          .M_AXI_AWREADY                    (cb_mi_awready        ),\n          .M_AXI_WID                        (cb_mi_wid             ),\n          .M_AXI_WDATA                      (cb_mi_wdata          ),\n          .M_AXI_WSTRB                      (cb_mi_wstrb          ),\n          .M_AXI_WLAST                      (cb_mi_wlast          ),\n          .M_AXI_WUSER                      (cb_mi_wuser          ),\n          .M_AXI_WVALID                     (cb_mi_wvalid         ),\n          .M_AXI_WREADY                     (cb_mi_wready         ),\n          .M_AXI_BID                        (cb_mi_bid            ),\n          .M_AXI_BRESP                      (cb_mi_bresp          ),\n          .M_AXI_BUSER                      (cb_mi_buser          ),\n          .M_AXI_BVALID                     (cb_mi_bvalid         ),\n          .M_AXI_BREADY                     (cb_mi_bready         ),\n          .M_AXI_ARID                       (cb_mi_arid           ),\n          .M_AXI_ARADDR                     (cb_mi_araddr         ),\n          .M_AXI_ARLEN                      (cb_mi_arlen          ),\n          .M_AXI_ARSIZE                     (cb_mi_arsize         ),\n          .M_AXI_ARBURST                    (cb_mi_arburst        ),\n          .M_AXI_ARLOCK                     (cb_mi_arlock         ),\n          .M_AXI_ARCACHE                    (cb_mi_arcache        ),\n          .M_AXI_ARPROT                     (cb_mi_arprot         ),\n          .M_AXI_ARREGION                   (cb_mi_arregion       ),\n          .M_AXI_ARQOS                      (cb_mi_arqos          ),\n          .M_AXI_ARUSER                     (cb_mi_aruser         ),\n          .M_AXI_ARVALID                    (cb_mi_arvalid        ),\n          .M_AXI_ARREADY                    (cb_mi_arready        ),\n          .M_AXI_RID                        (cb_mi_rid            ),\n          .M_AXI_RDATA                      (cb_mi_rdata          ),\n          .M_AXI_RRESP                      (cb_mi_rresp          ),\n          .M_AXI_RLAST                      (cb_mi_rlast          ),\n          .M_AXI_RUSER                      (cb_mi_ruser          ),\n          .M_AXI_RVALID                     (cb_mi_rvalid         ),\n          .M_AXI_RREADY                     (cb_mi_rready         )\n      );\n    end else begin : gen_samd\n      axi_crossbar_v2_1_23_crossbar #\n      (\n        .C_FAMILY                         (P_FAMILY),\n        .C_NUM_SLAVE_SLOTS                (C_NUM_SLAVE_SLOTS),\n        .C_NUM_MASTER_SLOTS               (C_NUM_MASTER_SLOTS),\n        .C_NUM_ADDR_RANGES                (C_NUM_ADDR_RANGES),\n        .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),\n        .C_S_AXI_THREAD_ID_WIDTH          (C_S_AXI_THREAD_ID_WIDTH),\n        .C_AXI_ADDR_WIDTH                 (C_AXI_ADDR_WIDTH),\n        .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),\n        .C_AXI_PROTOCOL                   (C_AXI_PROTOCOL),\n        .C_M_AXI_BASE_ADDR                (C_M_AXI_BASE_ADDR),\n        .C_M_AXI_HIGH_ADDR                (f_high_addr(0)),\n        .C_S_AXI_BASE_ID                  (P_S_AXI_BASE_ID),\n        .C_S_AXI_HIGH_ID                  (P_S_AXI_HIGH_ID),\n        .C_AXI_SUPPORTS_USER_SIGNALS      (C_AXI_SUPPORTS_USER_SIGNALS),\n        .C_AXI_AWUSER_WIDTH               (C_AXI_AWUSER_WIDTH),\n        .C_AXI_ARUSER_WIDTH               (C_AXI_ARUSER_WIDTH),\n        .C_AXI_WUSER_WIDTH                (C_AXI_WUSER_WIDTH),\n        .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),\n        .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),\n        .C_S_AXI_SUPPORTS_WRITE           (P_S_AXI_SUPPORTS_WRITE),\n        .C_S_AXI_SUPPORTS_READ            (P_S_AXI_SUPPORTS_READ),\n        .C_M_AXI_SUPPORTS_WRITE           (P_M_AXI_SUPPORTS_WRITE),\n        .C_M_AXI_SUPPORTS_READ            (P_M_AXI_SUPPORTS_READ),\n        .C_M_AXI_WRITE_CONNECTIVITY       (C_M_AXI_WRITE_CONNECTIVITY),\n        .C_M_AXI_READ_CONNECTIVITY        (C_M_AXI_READ_CONNECTIVITY),\n        .C_S_AXI_SINGLE_THREAD            (C_S_AXI_SINGLE_THREAD),\n        .C_S_AXI_WRITE_ACCEPTANCE         (C_S_AXI_WRITE_ACCEPTANCE),\n        .C_S_AXI_READ_ACCEPTANCE          (C_S_AXI_READ_ACCEPTANCE),\n        .C_M_AXI_WRITE_ISSUING            (C_M_AXI_WRITE_ISSUING),\n        .C_M_AXI_READ_ISSUING             (C_M_AXI_READ_ISSUING),\n        .C_S_AXI_ARB_PRIORITY             (C_S_AXI_ARB_PRIORITY),\n        .C_M_AXI_SECURE                   (C_M_AXI_SECURE),\n        .C_RANGE_CHECK                    (P_RANGE_CHECK),\n        .C_ADDR_DECODE                    (P_ADDR_DECODE),\n        .C_W_ISSUE_WIDTH                  (f_write_issue_width_vec(0) ),\n        .C_R_ISSUE_WIDTH                  (f_read_issue_width_vec(0) ),\n        .C_W_ACCEPT_WIDTH                 (f_write_accept_width_vec(0)),\n        .C_R_ACCEPT_WIDTH                 (f_read_accept_width_vec(0)),\n        .C_M_AXI_ERR_MODE                 (P_M_AXI_ERR_MODE),\n        .C_DEBUG                          (C_DEBUG)\n      )\n        crossbar_samd \n      (\n          .ACLK                             (aclk),\n          .ARESETN                          (aresetn),\n          .S_AXI_AWID                       (si_cb_awid             ),\n          .S_AXI_AWADDR                     (si_cb_awaddr           ),\n          .S_AXI_AWLEN                      (si_cb_awlen            ),\n          .S_AXI_AWSIZE                     (si_cb_awsize           ),\n          .S_AXI_AWBURST                    (si_cb_awburst          ),\n          .S_AXI_AWLOCK                     (si_cb_awlock           ),\n          .S_AXI_AWCACHE                    (si_cb_awcache          ),\n          .S_AXI_AWPROT                     (si_cb_awprot           ),\n//          .S_AXI_AWREGION                   (si_cb_awregion       ),\n          .S_AXI_AWQOS                      (si_cb_awqos            ),\n          .S_AXI_AWUSER                     (si_cb_awuser           ),\n          .S_AXI_AWVALID                    (si_cb_awvalid          ),\n          .S_AXI_AWREADY                    (si_cb_awready          ),\n          .S_AXI_WID                        (si_cb_wid             ),\n          .S_AXI_WDATA                      (si_cb_wdata            ),\n          .S_AXI_WSTRB                      (si_cb_wstrb            ),\n          .S_AXI_WLAST                      (si_cb_wlast            ),\n          .S_AXI_WUSER                      (si_cb_wuser            ),\n          .S_AXI_WVALID                     (si_cb_wvalid           ),\n          .S_AXI_WREADY                     (si_cb_wready           ),\n          .S_AXI_BID                        (si_cb_bid              ),\n          .S_AXI_BRESP                      (si_cb_bresp            ),\n          .S_AXI_BUSER                      (si_cb_buser            ),\n          .S_AXI_BVALID                     (si_cb_bvalid           ),\n          .S_AXI_BREADY                     (si_cb_bready           ),\n          .S_AXI_ARID                       (si_cb_arid             ),\n          .S_AXI_ARADDR                     (si_cb_araddr           ),\n          .S_AXI_ARLEN                      (si_cb_arlen            ),\n          .S_AXI_ARSIZE                     (si_cb_arsize           ),\n          .S_AXI_ARBURST                    (si_cb_arburst          ),\n          .S_AXI_ARLOCK                     (si_cb_arlock           ),\n          .S_AXI_ARCACHE                    (si_cb_arcache          ),\n          .S_AXI_ARPROT                     (si_cb_arprot           ),\n//          .S_AXI_ARREGION                   (si_cb_arregion       ),\n          .S_AXI_ARQOS                      (si_cb_arqos            ),\n          .S_AXI_ARUSER                     (si_cb_aruser           ),\n          .S_AXI_ARVALID                    (si_cb_arvalid          ),\n          .S_AXI_ARREADY                    (si_cb_arready          ),\n          .S_AXI_RID                        (si_cb_rid              ),\n          .S_AXI_RDATA                      (si_cb_rdata            ),\n          .S_AXI_RRESP                      (si_cb_rresp            ),\n          .S_AXI_RLAST                      (si_cb_rlast            ),\n          .S_AXI_RUSER                      (si_cb_ruser            ),\n          .S_AXI_RVALID                     (si_cb_rvalid           ),\n          .S_AXI_RREADY                     (si_cb_rready           ),\n          .M_AXI_AWID                       (cb_mi_awid             ),\n          .M_AXI_AWADDR                     (cb_mi_awaddr           ),\n          .M_AXI_AWLEN                      (cb_mi_awlen            ),\n          .M_AXI_AWSIZE                     (cb_mi_awsize           ),\n          .M_AXI_AWBURST                    (cb_mi_awburst          ),\n          .M_AXI_AWLOCK                     (cb_mi_awlock           ),\n          .M_AXI_AWCACHE                    (cb_mi_awcache          ),\n          .M_AXI_AWPROT                     (cb_mi_awprot           ),\n          .M_AXI_AWREGION                   (cb_mi_awregion         ),\n          .M_AXI_AWQOS                      (cb_mi_awqos            ),\n          .M_AXI_AWUSER                     (cb_mi_awuser           ),\n          .M_AXI_AWVALID                    (cb_mi_awvalid          ),\n          .M_AXI_AWREADY                    (cb_mi_awready          ),\n          .M_AXI_WID                        (cb_mi_wid             ),\n          .M_AXI_WDATA                      (cb_mi_wdata            ),\n          .M_AXI_WSTRB                      (cb_mi_wstrb            ),\n          .M_AXI_WLAST                      (cb_mi_wlast            ),\n          .M_AXI_WUSER                      (cb_mi_wuser            ),\n          .M_AXI_WVALID                     (cb_mi_wvalid           ),\n          .M_AXI_WREADY                     (cb_mi_wready           ),\n          .M_AXI_BID                        (cb_mi_bid              ),\n          .M_AXI_BRESP                      (cb_mi_bresp            ),\n          .M_AXI_BUSER                      (cb_mi_buser            ),\n          .M_AXI_BVALID                     (cb_mi_bvalid           ),\n          .M_AXI_BREADY                     (cb_mi_bready           ),\n          .M_AXI_ARID                       (cb_mi_arid             ),\n          .M_AXI_ARADDR                     (cb_mi_araddr           ),\n          .M_AXI_ARLEN                      (cb_mi_arlen            ),\n          .M_AXI_ARSIZE                     (cb_mi_arsize           ),\n          .M_AXI_ARBURST                    (cb_mi_arburst          ),\n          .M_AXI_ARLOCK                     (cb_mi_arlock           ),\n          .M_AXI_ARCACHE                    (cb_mi_arcache          ),\n          .M_AXI_ARPROT                     (cb_mi_arprot           ),\n          .M_AXI_ARREGION                   (cb_mi_arregion         ),\n          .M_AXI_ARQOS                      (cb_mi_arqos            ),\n          .M_AXI_ARUSER                     (cb_mi_aruser           ),\n          .M_AXI_ARVALID                    (cb_mi_arvalid          ),\n          .M_AXI_ARREADY                    (cb_mi_arready          ),\n          .M_AXI_RID                        (cb_mi_rid              ),\n          .M_AXI_RDATA                      (cb_mi_rdata            ),\n          .M_AXI_RRESP                      (cb_mi_rresp            ),\n          .M_AXI_RLAST                      (cb_mi_rlast            ),\n          .M_AXI_RUSER                      (cb_mi_ruser            ),\n          .M_AXI_RVALID                     (cb_mi_rvalid           ),\n          .M_AXI_RREADY                     (cb_mi_rready           )\n      );\n    end  // gen_samd\n//  end  // gen_crossbar\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n", "num_lines": 5805}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020\n//Date        : Wed Dec 15 00:42:21 2021\n//Host        : a-21awsprq4sria running 64-bit Amazon Linux release 2 (Karoo)\n//Command     : generate_target cl_axi_interconnect.bd\n//Design      : cl_axi_interconnect\n//Purpose     : IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=cl_axi_interconnect,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=14,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}\" *) (* HW_HANDOFF = \"cl_axi_interconnect.hwdef\" *) \nmodule cl_axi_interconnect\n   (ACLK,\n    ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.ACLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF S00_AXI:M00_AXI:M01_AXI:M02_AXI:M03_AXI:S01_AXI, ASSOCIATED_RESET ARESETN, CLK_DOMAIN cl_axi_interconnect_ACLK, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input ACLK;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.ARESETN RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW\" *) input ARESETN;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M00_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M00_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARBURST\" *) output [1:0]M00_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE\" *) output [3:0]M00_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARID\" *) output [6:0]M00_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLEN\" *) output [7:0]M00_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK\" *) output [0:0]M00_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARPROT\" *) output [2:0]M00_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARQOS\" *) output [3:0]M00_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREADY\" *) input M00_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREGION\" *) output [3:0]M00_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE\" *) output [2:0]M00_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARVALID\" *) output M00_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWADDR\" *) output [63:0]M00_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWBURST\" *) output [1:0]M00_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE\" *) output [3:0]M00_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWID\" *) output [6:0]M00_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLEN\" *) output [7:0]M00_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK\" *) output [0:0]M00_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWPROT\" *) output [2:0]M00_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWQOS\" *) output [3:0]M00_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREADY\" *) input M00_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREGION\" *) output [3:0]M00_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE\" *) output [2:0]M00_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWVALID\" *) output M00_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BID\" *) input [6:0]M00_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BREADY\" *) output M00_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BRESP\" *) input [1:0]M00_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BVALID\" *) input M00_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RDATA\" *) input [511:0]M00_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RID\" *) input [6:0]M00_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RLAST\" *) input M00_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RREADY\" *) output M00_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RRESP\" *) input [1:0]M00_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RVALID\" *) input M00_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WDATA\" *) output [511:0]M00_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WLAST\" *) output M00_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WREADY\" *) input M00_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WSTRB\" *) output [63:0]M00_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WVALID\" *) output M00_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M01_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M01_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARBURST\" *) output [1:0]M01_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE\" *) output [3:0]M01_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARID\" *) output [6:0]M01_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARLEN\" *) output [7:0]M01_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK\" *) output [0:0]M01_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARPROT\" *) output [2:0]M01_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARQOS\" *) output [3:0]M01_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARREADY\" *) input M01_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARREGION\" *) output [3:0]M01_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE\" *) output [2:0]M01_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARVALID\" *) output M01_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWADDR\" *) output [63:0]M01_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWBURST\" *) output [1:0]M01_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE\" *) output [3:0]M01_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWID\" *) output [6:0]M01_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWLEN\" *) output [7:0]M01_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK\" *) output [0:0]M01_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWPROT\" *) output [2:0]M01_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWQOS\" *) output [3:0]M01_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWREADY\" *) input M01_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWREGION\" *) output [3:0]M01_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE\" *) output [2:0]M01_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWVALID\" *) output M01_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BID\" *) input [6:0]M01_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BREADY\" *) output M01_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BRESP\" *) input [1:0]M01_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BVALID\" *) input M01_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RDATA\" *) input [511:0]M01_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RID\" *) input [6:0]M01_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RLAST\" *) input M01_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RREADY\" *) output M01_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RRESP\" *) input [1:0]M01_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RVALID\" *) input M01_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WDATA\" *) output [511:0]M01_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WLAST\" *) output M01_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WREADY\" *) input M01_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WSTRB\" *) output [63:0]M01_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WVALID\" *) output M01_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M02_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M02_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARBURST\" *) output [1:0]M02_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE\" *) output [3:0]M02_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARID\" *) output [6:0]M02_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARLEN\" *) output [7:0]M02_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK\" *) output [0:0]M02_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARPROT\" *) output [2:0]M02_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARQOS\" *) output [3:0]M02_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARREADY\" *) input M02_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARREGION\" *) output [3:0]M02_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE\" *) output [2:0]M02_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARVALID\" *) output M02_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWADDR\" *) output [63:0]M02_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWBURST\" *) output [1:0]M02_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE\" *) output [3:0]M02_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWID\" *) output [6:0]M02_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWLEN\" *) output [7:0]M02_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK\" *) output [0:0]M02_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWPROT\" *) output [2:0]M02_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWQOS\" *) output [3:0]M02_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWREADY\" *) input M02_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWREGION\" *) output [3:0]M02_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE\" *) output [2:0]M02_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWVALID\" *) output M02_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BID\" *) input [6:0]M02_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BREADY\" *) output M02_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BRESP\" *) input [1:0]M02_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BVALID\" *) input M02_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RDATA\" *) input [511:0]M02_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RID\" *) input [6:0]M02_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RLAST\" *) input M02_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RREADY\" *) output M02_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RRESP\" *) input [1:0]M02_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RVALID\" *) input M02_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WDATA\" *) output [511:0]M02_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WLAST\" *) output M02_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WREADY\" *) input M02_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WSTRB\" *) output [63:0]M02_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WVALID\" *) output M02_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M03_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M03_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARBURST\" *) output [1:0]M03_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE\" *) output [3:0]M03_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARID\" *) output [6:0]M03_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARLEN\" *) output [7:0]M03_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK\" *) output [0:0]M03_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARPROT\" *) output [2:0]M03_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARQOS\" *) output [3:0]M03_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARREADY\" *) input M03_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARREGION\" *) output [3:0]M03_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE\" *) output [2:0]M03_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARVALID\" *) output M03_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWADDR\" *) output [63:0]M03_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWBURST\" *) output [1:0]M03_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE\" *) output [3:0]M03_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWID\" *) output [6:0]M03_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWLEN\" *) output [7:0]M03_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK\" *) output [0:0]M03_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWPROT\" *) output [2:0]M03_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWQOS\" *) output [3:0]M03_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWREADY\" *) input M03_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWREGION\" *) output [3:0]M03_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE\" *) output [2:0]M03_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWVALID\" *) output M03_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BID\" *) input [6:0]M03_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BREADY\" *) output M03_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BRESP\" *) input [1:0]M03_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BVALID\" *) input M03_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RDATA\" *) input [511:0]M03_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RID\" *) input [6:0]M03_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RLAST\" *) input M03_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RREADY\" *) output M03_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RRESP\" *) input [1:0]M03_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RVALID\" *) input M03_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WDATA\" *) output [511:0]M03_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WLAST\" *) output M03_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WREADY\" *) input M03_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WSTRB\" *) output [63:0]M03_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WVALID\" *) output M03_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S00_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 6, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 32, NUM_READ_THREADS 16, NUM_WRITE_OUTSTANDING 32, NUM_WRITE_THREADS 16, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) input [63:0]S00_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARBURST\" *) input [1:0]S00_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE\" *) input [3:0]S00_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARID\" *) input [5:0]S00_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLEN\" *) input [7:0]S00_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK\" *) input [0:0]S00_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARPROT\" *) input [2:0]S00_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARQOS\" *) input [3:0]S00_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREADY\" *) output S00_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREGION\" *) input [3:0]S00_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE\" *) input [2:0]S00_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARVALID\" *) input S00_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWADDR\" *) input [63:0]S00_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWBURST\" *) input [1:0]S00_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE\" *) input [3:0]S00_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWID\" *) input [5:0]S00_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLEN\" *) input [7:0]S00_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK\" *) input [0:0]S00_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWPROT\" *) input [2:0]S00_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWQOS\" *) input [3:0]S00_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREADY\" *) output S00_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREGION\" *) input [3:0]S00_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE\" *) input [2:0]S00_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWVALID\" *) input S00_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BID\" *) output [5:0]S00_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BREADY\" *) input S00_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BRESP\" *) output [1:0]S00_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BVALID\" *) output S00_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RDATA\" *) output [511:0]S00_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RID\" *) output [5:0]S00_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RLAST\" *) output S00_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RREADY\" *) input S00_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RRESP\" *) output [1:0]S00_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RVALID\" *) output S00_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WDATA\" *) input [511:0]S00_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WLAST\" *) input S00_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WREADY\" *) output S00_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WSTRB\" *) input [63:0]S00_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WVALID\" *) input S00_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S01_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 6, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 32, NUM_READ_THREADS 16, NUM_WRITE_OUTSTANDING 32, NUM_WRITE_THREADS 16, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) input [63:0]S01_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARBURST\" *) input [1:0]S01_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE\" *) input [3:0]S01_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARID\" *) input [5:0]S01_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARLEN\" *) input [7:0]S01_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK\" *) input [0:0]S01_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARPROT\" *) input [2:0]S01_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARQOS\" *) input [3:0]S01_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARREADY\" *) output S01_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARREGION\" *) input [3:0]S01_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE\" *) input [2:0]S01_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARVALID\" *) input S01_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWADDR\" *) input [63:0]S01_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWBURST\" *) input [1:0]S01_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE\" *) input [3:0]S01_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWID\" *) input [5:0]S01_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWLEN\" *) input [7:0]S01_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK\" *) input [0:0]S01_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWPROT\" *) input [2:0]S01_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWQOS\" *) input [3:0]S01_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWREADY\" *) output S01_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWREGION\" *) input [3:0]S01_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE\" *) input [2:0]S01_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWVALID\" *) input S01_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BID\" *) output [5:0]S01_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BREADY\" *) input S01_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BRESP\" *) output [1:0]S01_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BVALID\" *) output S01_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RDATA\" *) output [511:0]S01_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RID\" *) output [5:0]S01_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RLAST\" *) output S01_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RREADY\" *) input S01_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RRESP\" *) output [1:0]S01_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RVALID\" *) output S01_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WDATA\" *) input [511:0]S01_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WLAST\" *) input S01_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WREADY\" *) output S01_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WSTRB\" *) input [63:0]S01_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WVALID\" *) input S01_AXI_wvalid;\n\n  wire ACLK_1;\n  wire ARESETN_1;\n  wire [63:0]S00_AXI_1_ARADDR;\n  wire [1:0]S00_AXI_1_ARBURST;\n  wire [3:0]S00_AXI_1_ARCACHE;\n  wire [5:0]S00_AXI_1_ARID;\n  wire [7:0]S00_AXI_1_ARLEN;\n  wire [0:0]S00_AXI_1_ARLOCK;\n  wire [2:0]S00_AXI_1_ARPROT;\n  wire [3:0]S00_AXI_1_ARQOS;\n  wire S00_AXI_1_ARREADY;\n  wire [3:0]S00_AXI_1_ARREGION;\n  wire [2:0]S00_AXI_1_ARSIZE;\n  wire S00_AXI_1_ARVALID;\n  wire [63:0]S00_AXI_1_AWADDR;\n  wire [1:0]S00_AXI_1_AWBURST;\n  wire [3:0]S00_AXI_1_AWCACHE;\n  wire [5:0]S00_AXI_1_AWID;\n  wire [7:0]S00_AXI_1_AWLEN;\n  wire [0:0]S00_AXI_1_AWLOCK;\n  wire [2:0]S00_AXI_1_AWPROT;\n  wire [3:0]S00_AXI_1_AWQOS;\n  wire S00_AXI_1_AWREADY;\n  wire [3:0]S00_AXI_1_AWREGION;\n  wire [2:0]S00_AXI_1_AWSIZE;\n  wire S00_AXI_1_AWVALID;\n  wire [5:0]S00_AXI_1_BID;\n  wire S00_AXI_1_BREADY;\n  wire [1:0]S00_AXI_1_BRESP;\n  wire S00_AXI_1_BVALID;\n  wire [511:0]S00_AXI_1_RDATA;\n  wire [5:0]S00_AXI_1_RID;\n  wire S00_AXI_1_RLAST;\n  wire S00_AXI_1_RREADY;\n  wire [1:0]S00_AXI_1_RRESP;\n  wire S00_AXI_1_RVALID;\n  wire [511:0]S00_AXI_1_WDATA;\n  wire S00_AXI_1_WLAST;\n  wire S00_AXI_1_WREADY;\n  wire [63:0]S00_AXI_1_WSTRB;\n  wire S00_AXI_1_WVALID;\n  wire [63:0]S01_AXI_1_ARADDR;\n  wire [1:0]S01_AXI_1_ARBURST;\n  wire [3:0]S01_AXI_1_ARCACHE;\n  wire [5:0]S01_AXI_1_ARID;\n  wire [7:0]S01_AXI_1_ARLEN;\n  wire [0:0]S01_AXI_1_ARLOCK;\n  wire [2:0]S01_AXI_1_ARPROT;\n  wire [3:0]S01_AXI_1_ARQOS;\n  wire S01_AXI_1_ARREADY;\n  wire [3:0]S01_AXI_1_ARREGION;\n  wire [2:0]S01_AXI_1_ARSIZE;\n  wire S01_AXI_1_ARVALID;\n  wire [63:0]S01_AXI_1_AWADDR;\n  wire [1:0]S01_AXI_1_AWBURST;\n  wire [3:0]S01_AXI_1_AWCACHE;\n  wire [5:0]S01_AXI_1_AWID;\n  wire [7:0]S01_AXI_1_AWLEN;\n  wire [0:0]S01_AXI_1_AWLOCK;\n  wire [2:0]S01_AXI_1_AWPROT;\n  wire [3:0]S01_AXI_1_AWQOS;\n  wire S01_AXI_1_AWREADY;\n  wire [3:0]S01_AXI_1_AWREGION;\n  wire [2:0]S01_AXI_1_AWSIZE;\n  wire S01_AXI_1_AWVALID;\n  wire [5:0]S01_AXI_1_BID;\n  wire S01_AXI_1_BREADY;\n  wire [1:0]S01_AXI_1_BRESP;\n  wire S01_AXI_1_BVALID;\n  wire [511:0]S01_AXI_1_RDATA;\n  wire [5:0]S01_AXI_1_RID;\n  wire S01_AXI_1_RLAST;\n  wire S01_AXI_1_RREADY;\n  wire [1:0]S01_AXI_1_RRESP;\n  wire S01_AXI_1_RVALID;\n  wire [511:0]S01_AXI_1_WDATA;\n  wire S01_AXI_1_WLAST;\n  wire S01_AXI_1_WREADY;\n  wire [63:0]S01_AXI_1_WSTRB;\n  wire S01_AXI_1_WVALID;\n  wire [63:0]axi_interconnect_0_M00_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M00_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M00_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M00_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M00_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M00_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARQOS;\n  wire axi_interconnect_0_M00_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M00_AXI_ARSIZE;\n  wire axi_interconnect_0_M00_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M00_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M00_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M00_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M00_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M00_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M00_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWQOS;\n  wire axi_interconnect_0_M00_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M00_AXI_AWSIZE;\n  wire axi_interconnect_0_M00_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M00_AXI_BID;\n  wire axi_interconnect_0_M00_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M00_AXI_BRESP;\n  wire axi_interconnect_0_M00_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M00_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M00_AXI_RID;\n  wire axi_interconnect_0_M00_AXI_RLAST;\n  wire axi_interconnect_0_M00_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M00_AXI_RRESP;\n  wire axi_interconnect_0_M00_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M00_AXI_WDATA;\n  wire axi_interconnect_0_M00_AXI_WLAST;\n  wire axi_interconnect_0_M00_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M00_AXI_WSTRB;\n  wire axi_interconnect_0_M00_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M01_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M01_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M01_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M01_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M01_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M01_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARQOS;\n  wire axi_interconnect_0_M01_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M01_AXI_ARSIZE;\n  wire axi_interconnect_0_M01_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M01_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M01_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M01_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M01_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M01_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M01_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWQOS;\n  wire axi_interconnect_0_M01_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M01_AXI_AWSIZE;\n  wire axi_interconnect_0_M01_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M01_AXI_BID;\n  wire axi_interconnect_0_M01_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M01_AXI_BRESP;\n  wire axi_interconnect_0_M01_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M01_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M01_AXI_RID;\n  wire axi_interconnect_0_M01_AXI_RLAST;\n  wire axi_interconnect_0_M01_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M01_AXI_RRESP;\n  wire axi_interconnect_0_M01_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M01_AXI_WDATA;\n  wire axi_interconnect_0_M01_AXI_WLAST;\n  wire axi_interconnect_0_M01_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M01_AXI_WSTRB;\n  wire axi_interconnect_0_M01_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M02_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M02_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M02_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M02_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M02_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M02_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARQOS;\n  wire axi_interconnect_0_M02_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M02_AXI_ARSIZE;\n  wire axi_interconnect_0_M02_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M02_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M02_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M02_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M02_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M02_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M02_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWQOS;\n  wire axi_interconnect_0_M02_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M02_AXI_AWSIZE;\n  wire axi_interconnect_0_M02_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M02_AXI_BID;\n  wire axi_interconnect_0_M02_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M02_AXI_BRESP;\n  wire axi_interconnect_0_M02_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M02_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M02_AXI_RID;\n  wire axi_interconnect_0_M02_AXI_RLAST;\n  wire axi_interconnect_0_M02_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M02_AXI_RRESP;\n  wire axi_interconnect_0_M02_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M02_AXI_WDATA;\n  wire axi_interconnect_0_M02_AXI_WLAST;\n  wire axi_interconnect_0_M02_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M02_AXI_WSTRB;\n  wire axi_interconnect_0_M02_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M03_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M03_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M03_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M03_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M03_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M03_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARQOS;\n  wire axi_interconnect_0_M03_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M03_AXI_ARSIZE;\n  wire axi_interconnect_0_M03_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M03_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M03_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M03_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M03_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M03_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M03_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWQOS;\n  wire axi_interconnect_0_M03_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M03_AXI_AWSIZE;\n  wire axi_interconnect_0_M03_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M03_AXI_BID;\n  wire axi_interconnect_0_M03_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M03_AXI_BRESP;\n  wire axi_interconnect_0_M03_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M03_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M03_AXI_RID;\n  wire axi_interconnect_0_M03_AXI_RLAST;\n  wire axi_interconnect_0_M03_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M03_AXI_RRESP;\n  wire axi_interconnect_0_M03_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M03_AXI_WDATA;\n  wire axi_interconnect_0_M03_AXI_WLAST;\n  wire axi_interconnect_0_M03_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M03_AXI_WSTRB;\n  wire axi_interconnect_0_M03_AXI_WVALID;\n\n  assign ACLK_1 = ACLK;\n  assign ARESETN_1 = ARESETN;\n  assign M00_AXI_araddr[63:0] = axi_interconnect_0_M00_AXI_ARADDR;\n  assign M00_AXI_arburst[1:0] = axi_interconnect_0_M00_AXI_ARBURST;\n  assign M00_AXI_arcache[3:0] = axi_interconnect_0_M00_AXI_ARCACHE;\n  assign M00_AXI_arid[6:0] = axi_interconnect_0_M00_AXI_ARID;\n  assign M00_AXI_arlen[7:0] = axi_interconnect_0_M00_AXI_ARLEN;\n  assign M00_AXI_arlock[0] = axi_interconnect_0_M00_AXI_ARLOCK;\n  assign M00_AXI_arprot[2:0] = axi_interconnect_0_M00_AXI_ARPROT;\n  assign M00_AXI_arqos[3:0] = axi_interconnect_0_M00_AXI_ARQOS;\n  assign M00_AXI_arregion[3:0] = axi_interconnect_0_M00_AXI_ARREGION;\n  assign M00_AXI_arsize[2:0] = axi_interconnect_0_M00_AXI_ARSIZE;\n  assign M00_AXI_arvalid = axi_interconnect_0_M00_AXI_ARVALID;\n  assign M00_AXI_awaddr[63:0] = axi_interconnect_0_M00_AXI_AWADDR;\n  assign M00_AXI_awburst[1:0] = axi_interconnect_0_M00_AXI_AWBURST;\n  assign M00_AXI_awcache[3:0] = axi_interconnect_0_M00_AXI_AWCACHE;\n  assign M00_AXI_awid[6:0] = axi_interconnect_0_M00_AXI_AWID;\n  assign M00_AXI_awlen[7:0] = axi_interconnect_0_M00_AXI_AWLEN;\n  assign M00_AXI_awlock[0] = axi_interconnect_0_M00_AXI_AWLOCK;\n  assign M00_AXI_awprot[2:0] = axi_interconnect_0_M00_AXI_AWPROT;\n  assign M00_AXI_awqos[3:0] = axi_interconnect_0_M00_AXI_AWQOS;\n  assign M00_AXI_awregion[3:0] = axi_interconnect_0_M00_AXI_AWREGION;\n  assign M00_AXI_awsize[2:0] = axi_interconnect_0_M00_AXI_AWSIZE;\n  assign M00_AXI_awvalid = axi_interconnect_0_M00_AXI_AWVALID;\n  assign M00_AXI_bready = axi_interconnect_0_M00_AXI_BREADY;\n  assign M00_AXI_rready = axi_interconnect_0_M00_AXI_RREADY;\n  assign M00_AXI_wdata[511:0] = axi_interconnect_0_M00_AXI_WDATA;\n  assign M00_AXI_wlast = axi_interconnect_0_M00_AXI_WLAST;\n  assign M00_AXI_wstrb[63:0] = axi_interconnect_0_M00_AXI_WSTRB;\n  assign M00_AXI_wvalid = axi_interconnect_0_M00_AXI_WVALID;\n  assign M01_AXI_araddr[63:0] = axi_interconnect_0_M01_AXI_ARADDR;\n  assign M01_AXI_arburst[1:0] = axi_interconnect_0_M01_AXI_ARBURST;\n  assign M01_AXI_arcache[3:0] = axi_interconnect_0_M01_AXI_ARCACHE;\n  assign M01_AXI_arid[6:0] = axi_interconnect_0_M01_AXI_ARID;\n  assign M01_AXI_arlen[7:0] = axi_interconnect_0_M01_AXI_ARLEN;\n  assign M01_AXI_arlock[0] = axi_interconnect_0_M01_AXI_ARLOCK;\n  assign M01_AXI_arprot[2:0] = axi_interconnect_0_M01_AXI_ARPROT;\n  assign M01_AXI_arqos[3:0] = axi_interconnect_0_M01_AXI_ARQOS;\n  assign M01_AXI_arregion[3:0] = axi_interconnect_0_M01_AXI_ARREGION;\n  assign M01_AXI_arsize[2:0] = axi_interconnect_0_M01_AXI_ARSIZE;\n  assign M01_AXI_arvalid = axi_interconnect_0_M01_AXI_ARVALID;\n  assign M01_AXI_awaddr[63:0] = axi_interconnect_0_M01_AXI_AWADDR;\n  assign M01_AXI_awburst[1:0] = axi_interconnect_0_M01_AXI_AWBURST;\n  assign M01_AXI_awcache[3:0] = axi_interconnect_0_M01_AXI_AWCACHE;\n  assign M01_AXI_awid[6:0] = axi_interconnect_0_M01_AXI_AWID;\n  assign M01_AXI_awlen[7:0] = axi_interconnect_0_M01_AXI_AWLEN;\n  assign M01_AXI_awlock[0] = axi_interconnect_0_M01_AXI_AWLOCK;\n  assign M01_AXI_awprot[2:0] = axi_interconnect_0_M01_AXI_AWPROT;\n  assign M01_AXI_awqos[3:0] = axi_interconnect_0_M01_AXI_AWQOS;\n  assign M01_AXI_awregion[3:0] = axi_interconnect_0_M01_AXI_AWREGION;\n  assign M01_AXI_awsize[2:0] = axi_interconnect_0_M01_AXI_AWSIZE;\n  assign M01_AXI_awvalid = axi_interconnect_0_M01_AXI_AWVALID;\n  assign M01_AXI_bready = axi_interconnect_0_M01_AXI_BREADY;\n  assign M01_AXI_rready = axi_interconnect_0_M01_AXI_RREADY;\n  assign M01_AXI_wdata[511:0] = axi_interconnect_0_M01_AXI_WDATA;\n  assign M01_AXI_wlast = axi_interconnect_0_M01_AXI_WLAST;\n  assign M01_AXI_wstrb[63:0] = axi_interconnect_0_M01_AXI_WSTRB;\n  assign M01_AXI_wvalid = axi_interconnect_0_M01_AXI_WVALID;\n  assign M02_AXI_araddr[63:0] = axi_interconnect_0_M02_AXI_ARADDR;\n  assign M02_AXI_arburst[1:0] = axi_interconnect_0_M02_AXI_ARBURST;\n  assign M02_AXI_arcache[3:0] = axi_interconnect_0_M02_AXI_ARCACHE;\n  assign M02_AXI_arid[6:0] = axi_interconnect_0_M02_AXI_ARID;\n  assign M02_AXI_arlen[7:0] = axi_interconnect_0_M02_AXI_ARLEN;\n  assign M02_AXI_arlock[0] = axi_interconnect_0_M02_AXI_ARLOCK;\n  assign M02_AXI_arprot[2:0] = axi_interconnect_0_M02_AXI_ARPROT;\n  assign M02_AXI_arqos[3:0] = axi_interconnect_0_M02_AXI_ARQOS;\n  assign M02_AXI_arregion[3:0] = axi_interconnect_0_M02_AXI_ARREGION;\n  assign M02_AXI_arsize[2:0] = axi_interconnect_0_M02_AXI_ARSIZE;\n  assign M02_AXI_arvalid = axi_interconnect_0_M02_AXI_ARVALID;\n  assign M02_AXI_awaddr[63:0] = axi_interconnect_0_M02_AXI_AWADDR;\n  assign M02_AXI_awburst[1:0] = axi_interconnect_0_M02_AXI_AWBURST;\n  assign M02_AXI_awcache[3:0] = axi_interconnect_0_M02_AXI_AWCACHE;\n  assign M02_AXI_awid[6:0] = axi_interconnect_0_M02_AXI_AWID;\n  assign M02_AXI_awlen[7:0] = axi_interconnect_0_M02_AXI_AWLEN;\n  assign M02_AXI_awlock[0] = axi_interconnect_0_M02_AXI_AWLOCK;\n  assign M02_AXI_awprot[2:0] = axi_interconnect_0_M02_AXI_AWPROT;\n  assign M02_AXI_awqos[3:0] = axi_interconnect_0_M02_AXI_AWQOS;\n  assign M02_AXI_awregion[3:0] = axi_interconnect_0_M02_AXI_AWREGION;\n  assign M02_AXI_awsize[2:0] = axi_interconnect_0_M02_AXI_AWSIZE;\n  assign M02_AXI_awvalid = axi_interconnect_0_M02_AXI_AWVALID;\n  assign M02_AXI_bready = axi_interconnect_0_M02_AXI_BREADY;\n  assign M02_AXI_rready = axi_interconnect_0_M02_AXI_RREADY;\n  assign M02_AXI_wdata[511:0] = axi_interconnect_0_M02_AXI_WDATA;\n  assign M02_AXI_wlast = axi_interconnect_0_M02_AXI_WLAST;\n  assign M02_AXI_wstrb[63:0] = axi_interconnect_0_M02_AXI_WSTRB;\n  assign M02_AXI_wvalid = axi_interconnect_0_M02_AXI_WVALID;\n  assign M03_AXI_araddr[63:0] = axi_interconnect_0_M03_AXI_ARADDR;\n  assign M03_AXI_arburst[1:0] = axi_interconnect_0_M03_AXI_ARBURST;\n  assign M03_AXI_arcache[3:0] = axi_interconnect_0_M03_AXI_ARCACHE;\n  assign M03_AXI_arid[6:0] = axi_interconnect_0_M03_AXI_ARID;\n  assign M03_AXI_arlen[7:0] = axi_interconnect_0_M03_AXI_ARLEN;\n  assign M03_AXI_arlock[0] = axi_interconnect_0_M03_AXI_ARLOCK;\n  assign M03_AXI_arprot[2:0] = axi_interconnect_0_M03_AXI_ARPROT;\n  assign M03_AXI_arqos[3:0] = axi_interconnect_0_M03_AXI_ARQOS;\n  assign M03_AXI_arregion[3:0] = axi_interconnect_0_M03_AXI_ARREGION;\n  assign M03_AXI_arsize[2:0] = axi_interconnect_0_M03_AXI_ARSIZE;\n  assign M03_AXI_arvalid = axi_interconnect_0_M03_AXI_ARVALID;\n  assign M03_AXI_awaddr[63:0] = axi_interconnect_0_M03_AXI_AWADDR;\n  assign M03_AXI_awburst[1:0] = axi_interconnect_0_M03_AXI_AWBURST;\n  assign M03_AXI_awcache[3:0] = axi_interconnect_0_M03_AXI_AWCACHE;\n  assign M03_AXI_awid[6:0] = axi_interconnect_0_M03_AXI_AWID;\n  assign M03_AXI_awlen[7:0] = axi_interconnect_0_M03_AXI_AWLEN;\n  assign M03_AXI_awlock[0] = axi_interconnect_0_M03_AXI_AWLOCK;\n  assign M03_AXI_awprot[2:0] = axi_interconnect_0_M03_AXI_AWPROT;\n  assign M03_AXI_awqos[3:0] = axi_interconnect_0_M03_AXI_AWQOS;\n  assign M03_AXI_awregion[3:0] = axi_interconnect_0_M03_AXI_AWREGION;\n  assign M03_AXI_awsize[2:0] = axi_interconnect_0_M03_AXI_AWSIZE;\n  assign M03_AXI_awvalid = axi_interconnect_0_M03_AXI_AWVALID;\n  assign M03_AXI_bready = axi_interconnect_0_M03_AXI_BREADY;\n  assign M03_AXI_rready = axi_interconnect_0_M03_AXI_RREADY;\n  assign M03_AXI_wdata[511:0] = axi_interconnect_0_M03_AXI_WDATA;\n  assign M03_AXI_wlast = axi_interconnect_0_M03_AXI_WLAST;\n  assign M03_AXI_wstrb[63:0] = axi_interconnect_0_M03_AXI_WSTRB;\n  assign M03_AXI_wvalid = axi_interconnect_0_M03_AXI_WVALID;\n  assign S00_AXI_1_ARADDR = S00_AXI_araddr[63:0];\n  assign S00_AXI_1_ARBURST = S00_AXI_arburst[1:0];\n  assign S00_AXI_1_ARCACHE = S00_AXI_arcache[3:0];\n  assign S00_AXI_1_ARID = S00_AXI_arid[5:0];\n  assign S00_AXI_1_ARLEN = S00_AXI_arlen[7:0];\n  assign S00_AXI_1_ARLOCK = S00_AXI_arlock[0];\n  assign S00_AXI_1_ARPROT = S00_AXI_arprot[2:0];\n  assign S00_AXI_1_ARQOS = S00_AXI_arqos[3:0];\n  assign S00_AXI_1_ARREGION = S00_AXI_arregion[3:0];\n  assign S00_AXI_1_ARSIZE = S00_AXI_arsize[2:0];\n  assign S00_AXI_1_ARVALID = S00_AXI_arvalid;\n  assign S00_AXI_1_AWADDR = S00_AXI_awaddr[63:0];\n  assign S00_AXI_1_AWBURST = S00_AXI_awburst[1:0];\n  assign S00_AXI_1_AWCACHE = S00_AXI_awcache[3:0];\n  assign S00_AXI_1_AWID = S00_AXI_awid[5:0];\n  assign S00_AXI_1_AWLEN = S00_AXI_awlen[7:0];\n  assign S00_AXI_1_AWLOCK = S00_AXI_awlock[0];\n  assign S00_AXI_1_AWPROT = S00_AXI_awprot[2:0];\n  assign S00_AXI_1_AWQOS = S00_AXI_awqos[3:0];\n  assign S00_AXI_1_AWREGION = S00_AXI_awregion[3:0];\n  assign S00_AXI_1_AWSIZE = S00_AXI_awsize[2:0];\n  assign S00_AXI_1_AWVALID = S00_AXI_awvalid;\n  assign S00_AXI_1_BREADY = S00_AXI_bready;\n  assign S00_AXI_1_RREADY = S00_AXI_rready;\n  assign S00_AXI_1_WDATA = S00_AXI_wdata[511:0];\n  assign S00_AXI_1_WLAST = S00_AXI_wlast;\n  assign S00_AXI_1_WSTRB = S00_AXI_wstrb[63:0];\n  assign S00_AXI_1_WVALID = S00_AXI_wvalid;\n  assign S00_AXI_arready = S00_AXI_1_ARREADY;\n  assign S00_AXI_awready = S00_AXI_1_AWREADY;\n  assign S00_AXI_bid[5:0] = S00_AXI_1_BID;\n  assign S00_AXI_bresp[1:0] = S00_AXI_1_BRESP;\n  assign S00_AXI_bvalid = S00_AXI_1_BVALID;\n  assign S00_AXI_rdata[511:0] = S00_AXI_1_RDATA;\n  assign S00_AXI_rid[5:0] = S00_AXI_1_RID;\n  assign S00_AXI_rlast = S00_AXI_1_RLAST;\n  assign S00_AXI_rresp[1:0] = S00_AXI_1_RRESP;\n  assign S00_AXI_rvalid = S00_AXI_1_RVALID;\n  assign S00_AXI_wready = S00_AXI_1_WREADY;\n  assign S01_AXI_1_ARADDR = S01_AXI_araddr[63:0];\n  assign S01_AXI_1_ARBURST = S01_AXI_arburst[1:0];\n  assign S01_AXI_1_ARCACHE = S01_AXI_arcache[3:0];\n  assign S01_AXI_1_ARID = S01_AXI_arid[5:0];\n  assign S01_AXI_1_ARLEN = S01_AXI_arlen[7:0];\n  assign S01_AXI_1_ARLOCK = S01_AXI_arlock[0];\n  assign S01_AXI_1_ARPROT = S01_AXI_arprot[2:0];\n  assign S01_AXI_1_ARQOS = S01_AXI_arqos[3:0];\n  assign S01_AXI_1_ARREGION = S01_AXI_arregion[3:0];\n  assign S01_AXI_1_ARSIZE = S01_AXI_arsize[2:0];\n  assign S01_AXI_1_ARVALID = S01_AXI_arvalid;\n  assign S01_AXI_1_AWADDR = S01_AXI_awaddr[63:0];\n  assign S01_AXI_1_AWBURST = S01_AXI_awburst[1:0];\n  assign S01_AXI_1_AWCACHE = S01_AXI_awcache[3:0];\n  assign S01_AXI_1_AWID = S01_AXI_awid[5:0];\n  assign S01_AXI_1_AWLEN = S01_AXI_awlen[7:0];\n  assign S01_AXI_1_AWLOCK = S01_AXI_awlock[0];\n  assign S01_AXI_1_AWPROT = S01_AXI_awprot[2:0];\n  assign S01_AXI_1_AWQOS = S01_AXI_awqos[3:0];\n  assign S01_AXI_1_AWREGION = S01_AXI_awregion[3:0];\n  assign S01_AXI_1_AWSIZE = S01_AXI_awsize[2:0];\n  assign S01_AXI_1_AWVALID = S01_AXI_awvalid;\n  assign S01_AXI_1_BREADY = S01_AXI_bready;\n  assign S01_AXI_1_RREADY = S01_AXI_rready;\n  assign S01_AXI_1_WDATA = S01_AXI_wdata[511:0];\n  assign S01_AXI_1_WLAST = S01_AXI_wlast;\n  assign S01_AXI_1_WSTRB = S01_AXI_wstrb[63:0];\n  assign S01_AXI_1_WVALID = S01_AXI_wvalid;\n  assign S01_AXI_arready = S01_AXI_1_ARREADY;\n  assign S01_AXI_awready = S01_AXI_1_AWREADY;\n  assign S01_AXI_bid[5:0] = S01_AXI_1_BID;\n  assign S01_AXI_bresp[1:0] = S01_AXI_1_BRESP;\n  assign S01_AXI_bvalid = S01_AXI_1_BVALID;\n  assign S01_AXI_rdata[511:0] = S01_AXI_1_RDATA;\n  assign S01_AXI_rid[5:0] = S01_AXI_1_RID;\n  assign S01_AXI_rlast = S01_AXI_1_RLAST;\n  assign S01_AXI_rresp[1:0] = S01_AXI_1_RRESP;\n  assign S01_AXI_rvalid = S01_AXI_1_RVALID;\n  assign S01_AXI_wready = S01_AXI_1_WREADY;\n  assign axi_interconnect_0_M00_AXI_ARREADY = M00_AXI_arready;\n  assign axi_interconnect_0_M00_AXI_AWREADY = M00_AXI_awready;\n  assign axi_interconnect_0_M00_AXI_BID = M00_AXI_bid[6:0];\n  assign axi_interconnect_0_M00_AXI_BRESP = M00_AXI_bresp[1:0];\n  assign axi_interconnect_0_M00_AXI_BVALID = M00_AXI_bvalid;\n  assign axi_interconnect_0_M00_AXI_RDATA = M00_AXI_rdata[511:0];\n  assign axi_interconnect_0_M00_AXI_RID = M00_AXI_rid[6:0];\n  assign axi_interconnect_0_M00_AXI_RLAST = M00_AXI_rlast;\n  assign axi_interconnect_0_M00_AXI_RRESP = M00_AXI_rresp[1:0];\n  assign axi_interconnect_0_M00_AXI_RVALID = M00_AXI_rvalid;\n  assign axi_interconnect_0_M00_AXI_WREADY = M00_AXI_wready;\n  assign axi_interconnect_0_M01_AXI_ARREADY = M01_AXI_arready;\n  assign axi_interconnect_0_M01_AXI_AWREADY = M01_AXI_awready;\n  assign axi_interconnect_0_M01_AXI_BID = M01_AXI_bid[6:0];\n  assign axi_interconnect_0_M01_AXI_BRESP = M01_AXI_bresp[1:0];\n  assign axi_interconnect_0_M01_AXI_BVALID = M01_AXI_bvalid;\n  assign axi_interconnect_0_M01_AXI_RDATA = M01_AXI_rdata[511:0];\n  assign axi_interconnect_0_M01_AXI_RID = M01_AXI_rid[6:0];\n  assign axi_interconnect_0_M01_AXI_RLAST = M01_AXI_rlast;\n  assign axi_interconnect_0_M01_AXI_RRESP = M01_AXI_rresp[1:0];\n  assign axi_interconnect_0_M01_AXI_RVALID = M01_AXI_rvalid;\n  assign axi_interconnect_0_M01_AXI_WREADY = M01_AXI_wready;\n  assign axi_interconnect_0_M02_AXI_ARREADY = M02_AXI_arready;\n  assign axi_interconnect_0_M02_AXI_AWREADY = M02_AXI_awready;\n  assign axi_interconnect_0_M02_AXI_BID = M02_AXI_bid[6:0];\n  assign axi_interconnect_0_M02_AXI_BRESP = M02_AXI_bresp[1:0];\n  assign axi_interconnect_0_M02_AXI_BVALID = M02_AXI_bvalid;\n  assign axi_interconnect_0_M02_AXI_RDATA = M02_AXI_rdata[511:0];\n  assign axi_interconnect_0_M02_AXI_RID = M02_AXI_rid[6:0];\n  assign axi_interconnect_0_M02_AXI_RLAST = M02_AXI_rlast;\n  assign axi_interconnect_0_M02_AXI_RRESP = M02_AXI_rresp[1:0];\n  assign axi_interconnect_0_M02_AXI_RVALID = M02_AXI_rvalid;\n  assign axi_interconnect_0_M02_AXI_WREADY = M02_AXI_wready;\n  assign axi_interconnect_0_M03_AXI_ARREADY = M03_AXI_arready;\n  assign axi_interconnect_0_M03_AXI_AWREADY = M03_AXI_awready;\n  assign axi_interconnect_0_M03_AXI_BID = M03_AXI_bid[6:0];\n  assign axi_interconnect_0_M03_AXI_BRESP = M03_AXI_bresp[1:0];\n  assign axi_interconnect_0_M03_AXI_BVALID = M03_AXI_bvalid;\n  assign axi_interconnect_0_M03_AXI_RDATA = M03_AXI_rdata[511:0];\n  assign axi_interconnect_0_M03_AXI_RID = M03_AXI_rid[6:0];\n  assign axi_interconnect_0_M03_AXI_RLAST = M03_AXI_rlast;\n  assign axi_interconnect_0_M03_AXI_RRESP = M03_AXI_rresp[1:0];\n  assign axi_interconnect_0_M03_AXI_RVALID = M03_AXI_rvalid;\n  assign axi_interconnect_0_M03_AXI_WREADY = M03_AXI_wready;\n  cl_axi_interconnect_axi_interconnect_0_0 axi_interconnect_0\n       (.ACLK(ACLK_1),\n        .ARESETN(ARESETN_1),\n        .M00_ACLK(ACLK_1),\n        .M00_ARESETN(ARESETN_1),\n        .M00_AXI_araddr(axi_interconnect_0_M00_AXI_ARADDR),\n        .M00_AXI_arburst(axi_interconnect_0_M00_AXI_ARBURST),\n        .M00_AXI_arcache(axi_interconnect_0_M00_AXI_ARCACHE),\n        .M00_AXI_arid(axi_interconnect_0_M00_AXI_ARID),\n        .M00_AXI_arlen(axi_interconnect_0_M00_AXI_ARLEN),\n        .M00_AXI_arlock(axi_interconnect_0_M00_AXI_ARLOCK),\n        .M00_AXI_arprot(axi_interconnect_0_M00_AXI_ARPROT),\n        .M00_AXI_arqos(axi_interconnect_0_M00_AXI_ARQOS),\n        .M00_AXI_arready(axi_interconnect_0_M00_AXI_ARREADY),\n        .M00_AXI_arregion(axi_interconnect_0_M00_AXI_ARREGION),\n        .M00_AXI_arsize(axi_interconnect_0_M00_AXI_ARSIZE),\n        .M00_AXI_arvalid(axi_interconnect_0_M00_AXI_ARVALID),\n        .M00_AXI_awaddr(axi_interconnect_0_M00_AXI_AWADDR),\n        .M00_AXI_awburst(axi_interconnect_0_M00_AXI_AWBURST),\n        .M00_AXI_awcache(axi_interconnect_0_M00_AXI_AWCACHE),\n        .M00_AXI_awid(axi_interconnect_0_M00_AXI_AWID),\n        .M00_AXI_awlen(axi_interconnect_0_M00_AXI_AWLEN),\n        .M00_AXI_awlock(axi_interconnect_0_M00_AXI_AWLOCK),\n        .M00_AXI_awprot(axi_interconnect_0_M00_AXI_AWPROT),\n        .M00_AXI_awqos(axi_interconnect_0_M00_AXI_AWQOS),\n        .M00_AXI_awready(axi_interconnect_0_M00_AXI_AWREADY),\n        .M00_AXI_awregion(axi_interconnect_0_M00_AXI_AWREGION),\n        .M00_AXI_awsize(axi_interconnect_0_M00_AXI_AWSIZE),\n        .M00_AXI_awvalid(axi_interconnect_0_M00_AXI_AWVALID),\n        .M00_AXI_bid(axi_interconnect_0_M00_AXI_BID),\n        .M00_AXI_bready(axi_interconnect_0_M00_AXI_BREADY),\n        .M00_AXI_bresp(axi_interconnect_0_M00_AXI_BRESP),\n        .M00_AXI_bvalid(axi_interconnect_0_M00_AXI_BVALID),\n        .M00_AXI_rdata(axi_interconnect_0_M00_AXI_RDATA),\n        .M00_AXI_rid(axi_interconnect_0_M00_AXI_RID),\n        .M00_AXI_rlast(axi_interconnect_0_M00_AXI_RLAST),\n        .M00_AXI_rready(axi_interconnect_0_M00_AXI_RREADY),\n        .M00_AXI_rresp(axi_interconnect_0_M00_AXI_RRESP),\n        .M00_AXI_rvalid(axi_interconnect_0_M00_AXI_RVALID),\n        .M00_AXI_wdata(axi_interconnect_0_M00_AXI_WDATA),\n        .M00_AXI_wlast(axi_interconnect_0_M00_AXI_WLAST),\n        .M00_AXI_wready(axi_interconnect_0_M00_AXI_WREADY),\n        .M00_AXI_wstrb(axi_interconnect_0_M00_AXI_WSTRB),\n        .M00_AXI_wvalid(axi_interconnect_0_M00_AXI_WVALID),\n        .M01_ACLK(ACLK_1),\n        .M01_ARESETN(ARESETN_1),\n        .M01_AXI_araddr(axi_interconnect_0_M01_AXI_ARADDR),\n        .M01_AXI_arburst(axi_interconnect_0_M01_AXI_ARBURST),\n        .M01_AXI_arcache(axi_interconnect_0_M01_AXI_ARCACHE),\n        .M01_AXI_arid(axi_interconnect_0_M01_AXI_ARID),\n        .M01_AXI_arlen(axi_interconnect_0_M01_AXI_ARLEN),\n        .M01_AXI_arlock(axi_interconnect_0_M01_AXI_ARLOCK),\n        .M01_AXI_arprot(axi_interconnect_0_M01_AXI_ARPROT),\n        .M01_AXI_arqos(axi_interconnect_0_M01_AXI_ARQOS),\n        .M01_AXI_arready(axi_interconnect_0_M01_AXI_ARREADY),\n        .M01_AXI_arregion(axi_interconnect_0_M01_AXI_ARREGION),\n        .M01_AXI_arsize(axi_interconnect_0_M01_AXI_ARSIZE),\n        .M01_AXI_arvalid(axi_interconnect_0_M01_AXI_ARVALID),\n        .M01_AXI_awaddr(axi_interconnect_0_M01_AXI_AWADDR),\n        .M01_AXI_awburst(axi_interconnect_0_M01_AXI_AWBURST),\n        .M01_AXI_awcache(axi_interconnect_0_M01_AXI_AWCACHE),\n        .M01_AXI_awid(axi_interconnect_0_M01_AXI_AWID),\n        .M01_AXI_awlen(axi_interconnect_0_M01_AXI_AWLEN),\n        .M01_AXI_awlock(axi_interconnect_0_M01_AXI_AWLOCK),\n        .M01_AXI_awprot(axi_interconnect_0_M01_AXI_AWPROT),\n        .M01_AXI_awqos(axi_interconnect_0_M01_AXI_AWQOS),\n        .M01_AXI_awready(axi_interconnect_0_M01_AXI_AWREADY),\n        .M01_AXI_awregion(axi_interconnect_0_M01_AXI_AWREGION),\n        .M01_AXI_awsize(axi_interconnect_0_M01_AXI_AWSIZE),\n        .M01_AXI_awvalid(axi_interconnect_0_M01_AXI_AWVALID),\n        .M01_AXI_bid(axi_interconnect_0_M01_AXI_BID),\n        .M01_AXI_bready(axi_interconnect_0_M01_AXI_BREADY),\n        .M01_AXI_bresp(axi_interconnect_0_M01_AXI_BRESP),\n        .M01_AXI_bvalid(axi_interconnect_0_M01_AXI_BVALID),\n        .M01_AXI_rdata(axi_interconnect_0_M01_AXI_RDATA),\n        .M01_AXI_rid(axi_interconnect_0_M01_AXI_RID),\n        .M01_AXI_rlast(axi_interconnect_0_M01_AXI_RLAST),\n        .M01_AXI_rready(axi_interconnect_0_M01_AXI_RREADY),\n        .M01_AXI_rresp(axi_interconnect_0_M01_AXI_RRESP),\n        .M01_AXI_rvalid(axi_interconnect_0_M01_AXI_RVALID),\n        .M01_AXI_wdata(axi_interconnect_0_M01_AXI_WDATA),\n        .M01_AXI_wlast(axi_interconnect_0_M01_AXI_WLAST),\n        .M01_AXI_wready(axi_interconnect_0_M01_AXI_WREADY),\n        .M01_AXI_wstrb(axi_interconnect_0_M01_AXI_WSTRB),\n        .M01_AXI_wvalid(axi_interconnect_0_M01_AXI_WVALID),\n        .M02_ACLK(ACLK_1),\n        .M02_ARESETN(ARESETN_1),\n        .M02_AXI_araddr(axi_interconnect_0_M02_AXI_ARADDR),\n        .M02_AXI_arburst(axi_interconnect_0_M02_AXI_ARBURST),\n        .M02_AXI_arcache(axi_interconnect_0_M02_AXI_ARCACHE),\n        .M02_AXI_arid(axi_interconnect_0_M02_AXI_ARID),\n        .M02_AXI_arlen(axi_interconnect_0_M02_AXI_ARLEN),\n        .M02_AXI_arlock(axi_interconnect_0_M02_AXI_ARLOCK),\n        .M02_AXI_arprot(axi_interconnect_0_M02_AXI_ARPROT),\n        .M02_AXI_arqos(axi_interconnect_0_M02_AXI_ARQOS),\n        .M02_AXI_arready(axi_interconnect_0_M02_AXI_ARREADY),\n        .M02_AXI_arregion(axi_interconnect_0_M02_AXI_ARREGION),\n        .M02_AXI_arsize(axi_interconnect_0_M02_AXI_ARSIZE),\n        .M02_AXI_arvalid(axi_interconnect_0_M02_AXI_ARVALID),\n        .M02_AXI_awaddr(axi_interconnect_0_M02_AXI_AWADDR),\n        .M02_AXI_awburst(axi_interconnect_0_M02_AXI_AWBURST),\n        .M02_AXI_awcache(axi_interconnect_0_M02_AXI_AWCACHE),\n        .M02_AXI_awid(axi_interconnect_0_M02_AXI_AWID),\n        .M02_AXI_awlen(axi_interconnect_0_M02_AXI_AWLEN),\n        .M02_AXI_awlock(axi_interconnect_0_M02_AXI_AWLOCK),\n        .M02_AXI_awprot(axi_interconnect_0_M02_AXI_AWPROT),\n        .M02_AXI_awqos(axi_interconnect_0_M02_AXI_AWQOS),\n        .M02_AXI_awready(axi_interconnect_0_M02_AXI_AWREADY),\n        .M02_AXI_awregion(axi_interconnect_0_M02_AXI_AWREGION),\n        .M02_AXI_awsize(axi_interconnect_0_M02_AXI_AWSIZE),\n        .M02_AXI_awvalid(axi_interconnect_0_M02_AXI_AWVALID),\n        .M02_AXI_bid(axi_interconnect_0_M02_AXI_BID),\n        .M02_AXI_bready(axi_interconnect_0_M02_AXI_BREADY),\n        .M02_AXI_bresp(axi_interconnect_0_M02_AXI_BRESP),\n        .M02_AXI_bvalid(axi_interconnect_0_M02_AXI_BVALID),\n        .M02_AXI_rdata(axi_interconnect_0_M02_AXI_RDATA),\n        .M02_AXI_rid(axi_interconnect_0_M02_AXI_RID),\n        .M02_AXI_rlast(axi_interconnect_0_M02_AXI_RLAST),\n        .M02_AXI_rready(axi_interconnect_0_M02_AXI_RREADY),\n        .M02_AXI_rresp(axi_interconnect_0_M02_AXI_RRESP),\n        .M02_AXI_rvalid(axi_interconnect_0_M02_AXI_RVALID),\n        .M02_AXI_wdata(axi_interconnect_0_M02_AXI_WDATA),\n        .M02_AXI_wlast(axi_interconnect_0_M02_AXI_WLAST),\n        .M02_AXI_wready(axi_interconnect_0_M02_AXI_WREADY),\n        .M02_AXI_wstrb(axi_interconnect_0_M02_AXI_WSTRB),\n        .M02_AXI_wvalid(axi_interconnect_0_M02_AXI_WVALID),\n        .M03_ACLK(ACLK_1),\n        .M03_ARESETN(ARESETN_1),\n        .M03_AXI_araddr(axi_interconnect_0_M03_AXI_ARADDR),\n        .M03_AXI_arburst(axi_interconnect_0_M03_AXI_ARBURST),\n        .M03_AXI_arcache(axi_interconnect_0_M03_AXI_ARCACHE),\n        .M03_AXI_arid(axi_interconnect_0_M03_AXI_ARID),\n        .M03_AXI_arlen(axi_interconnect_0_M03_AXI_ARLEN),\n        .M03_AXI_arlock(axi_interconnect_0_M03_AXI_ARLOCK),\n        .M03_AXI_arprot(axi_interconnect_0_M03_AXI_ARPROT),\n        .M03_AXI_arqos(axi_interconnect_0_M03_AXI_ARQOS),\n        .M03_AXI_arready(axi_interconnect_0_M03_AXI_ARREADY),\n        .M03_AXI_arregion(axi_interconnect_0_M03_AXI_ARREGION),\n        .M03_AXI_arsize(axi_interconnect_0_M03_AXI_ARSIZE),\n        .M03_AXI_arvalid(axi_interconnect_0_M03_AXI_ARVALID),\n        .M03_AXI_awaddr(axi_interconnect_0_M03_AXI_AWADDR),\n        .M03_AXI_awburst(axi_interconnect_0_M03_AXI_AWBURST),\n        .M03_AXI_awcache(axi_interconnect_0_M03_AXI_AWCACHE),\n        .M03_AXI_awid(axi_interconnect_0_M03_AXI_AWID),\n        .M03_AXI_awlen(axi_interconnect_0_M03_AXI_AWLEN),\n        .M03_AXI_awlock(axi_interconnect_0_M03_AXI_AWLOCK),\n        .M03_AXI_awprot(axi_interconnect_0_M03_AXI_AWPROT),\n        .M03_AXI_awqos(axi_interconnect_0_M03_AXI_AWQOS),\n        .M03_AXI_awready(axi_interconnect_0_M03_AXI_AWREADY),\n        .M03_AXI_awregion(axi_interconnect_0_M03_AXI_AWREGION),\n        .M03_AXI_awsize(axi_interconnect_0_M03_AXI_AWSIZE),\n        .M03_AXI_awvalid(axi_interconnect_0_M03_AXI_AWVALID),\n        .M03_AXI_bid(axi_interconnect_0_M03_AXI_BID),\n        .M03_AXI_bready(axi_interconnect_0_M03_AXI_BREADY),\n        .M03_AXI_bresp(axi_interconnect_0_M03_AXI_BRESP),\n        .M03_AXI_bvalid(axi_interconnect_0_M03_AXI_BVALID),\n        .M03_AXI_rdata(axi_interconnect_0_M03_AXI_RDATA),\n        .M03_AXI_rid(axi_interconnect_0_M03_AXI_RID),\n        .M03_AXI_rlast(axi_interconnect_0_M03_AXI_RLAST),\n        .M03_AXI_rready(axi_interconnect_0_M03_AXI_RREADY),\n        .M03_AXI_rresp(axi_interconnect_0_M03_AXI_RRESP),\n        .M03_AXI_rvalid(axi_interconnect_0_M03_AXI_RVALID),\n        .M03_AXI_wdata(axi_interconnect_0_M03_AXI_WDATA),\n        .M03_AXI_wlast(axi_interconnect_0_M03_AXI_WLAST),\n        .M03_AXI_wready(axi_interconnect_0_M03_AXI_WREADY),\n        .M03_AXI_wstrb(axi_interconnect_0_M03_AXI_WSTRB),\n        .M03_AXI_wvalid(axi_interconnect_0_M03_AXI_WVALID),\n        .S00_ACLK(ACLK_1),\n        .S00_ARESETN(ARESETN_1),\n        .S00_AXI_araddr(S00_AXI_1_ARADDR),\n        .S00_AXI_arburst(S00_AXI_1_ARBURST),\n        .S00_AXI_arcache(S00_AXI_1_ARCACHE),\n        .S00_AXI_arid(S00_AXI_1_ARID),\n        .S00_AXI_arlen(S00_AXI_1_ARLEN),\n        .S00_AXI_arlock(S00_AXI_1_ARLOCK),\n        .S00_AXI_arprot(S00_AXI_1_ARPROT),\n        .S00_AXI_arqos(S00_AXI_1_ARQOS),\n        .S00_AXI_arready(S00_AXI_1_ARREADY),\n        .S00_AXI_arregion(S00_AXI_1_ARREGION),\n        .S00_AXI_arsize(S00_AXI_1_ARSIZE),\n        .S00_AXI_arvalid(S00_AXI_1_ARVALID),\n        .S00_AXI_awaddr(S00_AXI_1_AWADDR),\n        .S00_AXI_awburst(S00_AXI_1_AWBURST),\n        .S00_AXI_awcache(S00_AXI_1_AWCACHE),\n        .S00_AXI_awid(S00_AXI_1_AWID),\n        .S00_AXI_awlen(S00_AXI_1_AWLEN),\n        .S00_AXI_awlock(S00_AXI_1_AWLOCK),\n        .S00_AXI_awprot(S00_AXI_1_AWPROT),\n        .S00_AXI_awqos(S00_AXI_1_AWQOS),\n        .S00_AXI_awready(S00_AXI_1_AWREADY),\n        .S00_AXI_awregion(S00_AXI_1_AWREGION),\n        .S00_AXI_awsize(S00_AXI_1_AWSIZE),\n        .S00_AXI_awvalid(S00_AXI_1_AWVALID),\n        .S00_AXI_bid(S00_AXI_1_BID),\n        .S00_AXI_bready(S00_AXI_1_BREADY),\n        .S00_AXI_bresp(S00_AXI_1_BRESP),\n        .S00_AXI_bvalid(S00_AXI_1_BVALID),\n        .S00_AXI_rdata(S00_AXI_1_RDATA),\n        .S00_AXI_rid(S00_AXI_1_RID),\n        .S00_AXI_rlast(S00_AXI_1_RLAST),\n        .S00_AXI_rready(S00_AXI_1_RREADY),\n        .S00_AXI_rresp(S00_AXI_1_RRESP),\n        .S00_AXI_rvalid(S00_AXI_1_RVALID),\n        .S00_AXI_wdata(S00_AXI_1_WDATA),\n        .S00_AXI_wlast(S00_AXI_1_WLAST),\n        .S00_AXI_wready(S00_AXI_1_WREADY),\n        .S00_AXI_wstrb(S00_AXI_1_WSTRB),\n        .S00_AXI_wvalid(S00_AXI_1_WVALID),\n        .S01_ACLK(ACLK_1),\n        .S01_ARESETN(ARESETN_1),\n        .S01_AXI_araddr(S01_AXI_1_ARADDR),\n        .S01_AXI_arburst(S01_AXI_1_ARBURST),\n        .S01_AXI_arcache(S01_AXI_1_ARCACHE),\n        .S01_AXI_arid(S01_AXI_1_ARID),\n        .S01_AXI_arlen(S01_AXI_1_ARLEN),\n        .S01_AXI_arlock(S01_AXI_1_ARLOCK),\n        .S01_AXI_arprot(S01_AXI_1_ARPROT),\n        .S01_AXI_arqos(S01_AXI_1_ARQOS),\n        .S01_AXI_arready(S01_AXI_1_ARREADY),\n        .S01_AXI_arregion(S01_AXI_1_ARREGION),\n        .S01_AXI_arsize(S01_AXI_1_ARSIZE),\n        .S01_AXI_arvalid(S01_AXI_1_ARVALID),\n        .S01_AXI_awaddr(S01_AXI_1_AWADDR),\n        .S01_AXI_awburst(S01_AXI_1_AWBURST),\n        .S01_AXI_awcache(S01_AXI_1_AWCACHE),\n        .S01_AXI_awid(S01_AXI_1_AWID),\n        .S01_AXI_awlen(S01_AXI_1_AWLEN),\n        .S01_AXI_awlock(S01_AXI_1_AWLOCK),\n        .S01_AXI_awprot(S01_AXI_1_AWPROT),\n        .S01_AXI_awqos(S01_AXI_1_AWQOS),\n        .S01_AXI_awready(S01_AXI_1_AWREADY),\n        .S01_AXI_awregion(S01_AXI_1_AWREGION),\n        .S01_AXI_awsize(S01_AXI_1_AWSIZE),\n        .S01_AXI_awvalid(S01_AXI_1_AWVALID),\n        .S01_AXI_bid(S01_AXI_1_BID),\n        .S01_AXI_bready(S01_AXI_1_BREADY),\n        .S01_AXI_bresp(S01_AXI_1_BRESP),\n        .S01_AXI_bvalid(S01_AXI_1_BVALID),\n        .S01_AXI_rdata(S01_AXI_1_RDATA),\n        .S01_AXI_rid(S01_AXI_1_RID),\n        .S01_AXI_rlast(S01_AXI_1_RLAST),\n        .S01_AXI_rready(S01_AXI_1_RREADY),\n        .S01_AXI_rresp(S01_AXI_1_RRESP),\n        .S01_AXI_rvalid(S01_AXI_1_RVALID),\n        .S01_AXI_wdata(S01_AXI_1_WDATA),\n        .S01_AXI_wlast(S01_AXI_1_WLAST),\n        .S01_AXI_wready(S01_AXI_1_WREADY),\n        .S01_AXI_wstrb(S01_AXI_1_WSTRB),\n        .S01_AXI_wvalid(S01_AXI_1_WVALID));\nendmodule\n\nmodule cl_axi_interconnect_axi_interconnect_0_0\n   (ACLK,\n    ARESETN,\n    M00_ACLK,\n    M00_ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_ACLK,\n    M01_ARESETN,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_ACLK,\n    M02_ARESETN,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_ACLK,\n    M03_ARESETN,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_ACLK,\n    S00_ARESETN,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_ACLK,\n    S01_ARESETN,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  input ACLK;\n  input ARESETN;\n  input M00_ACLK;\n  input M00_ARESETN;\n  output [63:0]M00_AXI_araddr;\n  output [1:0]M00_AXI_arburst;\n  output [3:0]M00_AXI_arcache;\n  output [6:0]M00_AXI_arid;\n  output [7:0]M00_AXI_arlen;\n  output [0:0]M00_AXI_arlock;\n  output [2:0]M00_AXI_arprot;\n  output [3:0]M00_AXI_arqos;\n  input M00_AXI_arready;\n  output [3:0]M00_AXI_arregion;\n  output [2:0]M00_AXI_arsize;\n  output M00_AXI_arvalid;\n  output [63:0]M00_AXI_awaddr;\n  output [1:0]M00_AXI_awburst;\n  output [3:0]M00_AXI_awcache;\n  output [6:0]M00_AXI_awid;\n  output [7:0]M00_AXI_awlen;\n  output [0:0]M00_AXI_awlock;\n  output [2:0]M00_AXI_awprot;\n  output [3:0]M00_AXI_awqos;\n  input M00_AXI_awready;\n  output [3:0]M00_AXI_awregion;\n  output [2:0]M00_AXI_awsize;\n  output M00_AXI_awvalid;\n  input [6:0]M00_AXI_bid;\n  output M00_AXI_bready;\n  input [1:0]M00_AXI_bresp;\n  input M00_AXI_bvalid;\n  input [511:0]M00_AXI_rdata;\n  input [6:0]M00_AXI_rid;\n  input M00_AXI_rlast;\n  output M00_AXI_rready;\n  input [1:0]M00_AXI_rresp;\n  input M00_AXI_rvalid;\n  output [511:0]M00_AXI_wdata;\n  output M00_AXI_wlast;\n  input M00_AXI_wready;\n  output [63:0]M00_AXI_wstrb;\n  output M00_AXI_wvalid;\n  input M01_ACLK;\n  input M01_ARESETN;\n  output [63:0]M01_AXI_araddr;\n  output [1:0]M01_AXI_arburst;\n  output [3:0]M01_AXI_arcache;\n  output [6:0]M01_AXI_arid;\n  output [7:0]M01_AXI_arlen;\n  output [0:0]M01_AXI_arlock;\n  output [2:0]M01_AXI_arprot;\n  output [3:0]M01_AXI_arqos;\n  input M01_AXI_arready;\n  output [3:0]M01_AXI_arregion;\n  output [2:0]M01_AXI_arsize;\n  output M01_AXI_arvalid;\n  output [63:0]M01_AXI_awaddr;\n  output [1:0]M01_AXI_awburst;\n  output [3:0]M01_AXI_awcache;\n  output [6:0]M01_AXI_awid;\n  output [7:0]M01_AXI_awlen;\n  output [0:0]M01_AXI_awlock;\n  output [2:0]M01_AXI_awprot;\n  output [3:0]M01_AXI_awqos;\n  input M01_AXI_awready;\n  output [3:0]M01_AXI_awregion;\n  output [2:0]M01_AXI_awsize;\n  output M01_AXI_awvalid;\n  input [6:0]M01_AXI_bid;\n  output M01_AXI_bready;\n  input [1:0]M01_AXI_bresp;\n  input M01_AXI_bvalid;\n  input [511:0]M01_AXI_rdata;\n  input [6:0]M01_AXI_rid;\n  input M01_AXI_rlast;\n  output M01_AXI_rready;\n  input [1:0]M01_AXI_rresp;\n  input M01_AXI_rvalid;\n  output [511:0]M01_AXI_wdata;\n  output M01_AXI_wlast;\n  input M01_AXI_wready;\n  output [63:0]M01_AXI_wstrb;\n  output M01_AXI_wvalid;\n  input M02_ACLK;\n  input M02_ARESETN;\n  output [63:0]M02_AXI_araddr;\n  output [1:0]M02_AXI_arburst;\n  output [3:0]M02_AXI_arcache;\n  output [6:0]M02_AXI_arid;\n  output [7:0]M02_AXI_arlen;\n  output [0:0]M02_AXI_arlock;\n  output [2:0]M02_AXI_arprot;\n  output [3:0]M02_AXI_arqos;\n  input M02_AXI_arready;\n  output [3:0]M02_AXI_arregion;\n  output [2:0]M02_AXI_arsize;\n  output M02_AXI_arvalid;\n  output [63:0]M02_AXI_awaddr;\n  output [1:0]M02_AXI_awburst;\n  output [3:0]M02_AXI_awcache;\n  output [6:0]M02_AXI_awid;\n  output [7:0]M02_AXI_awlen;\n  output [0:0]M02_AXI_awlock;\n  output [2:0]M02_AXI_awprot;\n  output [3:0]M02_AXI_awqos;\n  input M02_AXI_awready;\n  output [3:0]M02_AXI_awregion;\n  output [2:0]M02_AXI_awsize;\n  output M02_AXI_awvalid;\n  input [6:0]M02_AXI_bid;\n  output M02_AXI_bready;\n  input [1:0]M02_AXI_bresp;\n  input M02_AXI_bvalid;\n  input [511:0]M02_AXI_rdata;\n  input [6:0]M02_AXI_rid;\n  input M02_AXI_rlast;\n  output M02_AXI_rready;\n  input [1:0]M02_AXI_rresp;\n  input M02_AXI_rvalid;\n  output [511:0]M02_AXI_wdata;\n  output M02_AXI_wlast;\n  input M02_AXI_wready;\n  output [63:0]M02_AXI_wstrb;\n  output M02_AXI_wvalid;\n  input M03_ACLK;\n  input M03_ARESETN;\n  output [63:0]M03_AXI_araddr;\n  output [1:0]M03_AXI_arburst;\n  output [3:0]M03_AXI_arcache;\n  output [6:0]M03_AXI_arid;\n  output [7:0]M03_AXI_arlen;\n  output [0:0]M03_AXI_arlock;\n  output [2:0]M03_AXI_arprot;\n  output [3:0]M03_AXI_arqos;\n  input M03_AXI_arready;\n  output [3:0]M03_AXI_arregion;\n  output [2:0]M03_AXI_arsize;\n  output M03_AXI_arvalid;\n  output [63:0]M03_AXI_awaddr;\n  output [1:0]M03_AXI_awburst;\n  output [3:0]M03_AXI_awcache;\n  output [6:0]M03_AXI_awid;\n  output [7:0]M03_AXI_awlen;\n  output [0:0]M03_AXI_awlock;\n  output [2:0]M03_AXI_awprot;\n  output [3:0]M03_AXI_awqos;\n  input M03_AXI_awready;\n  output [3:0]M03_AXI_awregion;\n  output [2:0]M03_AXI_awsize;\n  output M03_AXI_awvalid;\n  input [6:0]M03_AXI_bid;\n  output M03_AXI_bready;\n  input [1:0]M03_AXI_bresp;\n  input M03_AXI_bvalid;\n  input [511:0]M03_AXI_rdata;\n  input [6:0]M03_AXI_rid;\n  input M03_AXI_rlast;\n  output M03_AXI_rready;\n  input [1:0]M03_AXI_rresp;\n  input M03_AXI_rvalid;\n  output [511:0]M03_AXI_wdata;\n  output M03_AXI_wlast;\n  input M03_AXI_wready;\n  output [63:0]M03_AXI_wstrb;\n  output M03_AXI_wvalid;\n  input S00_ACLK;\n  input S00_ARESETN;\n  input [63:0]S00_AXI_araddr;\n  input [1:0]S00_AXI_arburst;\n  input [3:0]S00_AXI_arcache;\n  input [5:0]S00_AXI_arid;\n  input [7:0]S00_AXI_arlen;\n  input [0:0]S00_AXI_arlock;\n  input [2:0]S00_AXI_arprot;\n  input [3:0]S00_AXI_arqos;\n  output S00_AXI_arready;\n  input [3:0]S00_AXI_arregion;\n  input [2:0]S00_AXI_arsize;\n  input S00_AXI_arvalid;\n  input [63:0]S00_AXI_awaddr;\n  input [1:0]S00_AXI_awburst;\n  input [3:0]S00_AXI_awcache;\n  input [5:0]S00_AXI_awid;\n  input [7:0]S00_AXI_awlen;\n  input [0:0]S00_AXI_awlock;\n  input [2:0]S00_AXI_awprot;\n  input [3:0]S00_AXI_awqos;\n  output S00_AXI_awready;\n  input [3:0]S00_AXI_awregion;\n  input [2:0]S00_AXI_awsize;\n  input S00_AXI_awvalid;\n  output [5:0]S00_AXI_bid;\n  input S00_AXI_bready;\n  output [1:0]S00_AXI_bresp;\n  output S00_AXI_bvalid;\n  output [511:0]S00_AXI_rdata;\n  output [5:0]S00_AXI_rid;\n  output S00_AXI_rlast;\n  input S00_AXI_rready;\n  output [1:0]S00_AXI_rresp;\n  output S00_AXI_rvalid;\n  input [511:0]S00_AXI_wdata;\n  input S00_AXI_wlast;\n  output S00_AXI_wready;\n  input [63:0]S00_AXI_wstrb;\n  input S00_AXI_wvalid;\n  input S01_ACLK;\n  input S01_ARESETN;\n  input [63:0]S01_AXI_araddr;\n  input [1:0]S01_AXI_arburst;\n  input [3:0]S01_AXI_arcache;\n  input [5:0]S01_AXI_arid;\n  input [7:0]S01_AXI_arlen;\n  input [0:0]S01_AXI_arlock;\n  input [2:0]S01_AXI_arprot;\n  input [3:0]S01_AXI_arqos;\n  output S01_AXI_arready;\n  input [3:0]S01_AXI_arregion;\n  input [2:0]S01_AXI_arsize;\n  input S01_AXI_arvalid;\n  input [63:0]S01_AXI_awaddr;\n  input [1:0]S01_AXI_awburst;\n  input [3:0]S01_AXI_awcache;\n  input [5:0]S01_AXI_awid;\n  input [7:0]S01_AXI_awlen;\n  input [0:0]S01_AXI_awlock;\n  input [2:0]S01_AXI_awprot;\n  input [3:0]S01_AXI_awqos;\n  output S01_AXI_awready;\n  input [3:0]S01_AXI_awregion;\n  input [2:0]S01_AXI_awsize;\n  input S01_AXI_awvalid;\n  output [5:0]S01_AXI_bid;\n  input S01_AXI_bready;\n  output [1:0]S01_AXI_bresp;\n  output S01_AXI_bvalid;\n  output [511:0]S01_AXI_rdata;\n  output [5:0]S01_AXI_rid;\n  output S01_AXI_rlast;\n  input S01_AXI_rready;\n  output [1:0]S01_AXI_rresp;\n  output S01_AXI_rvalid;\n  input [511:0]S01_AXI_wdata;\n  input S01_AXI_wlast;\n  output S01_AXI_wready;\n  input [63:0]S01_AXI_wstrb;\n  input S01_AXI_wvalid;\n\n  wire axi_interconnect_0_ACLK_net;\n  wire axi_interconnect_0_ARESETN_net;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_ARADDR;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_ARBURST;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARCACHE;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_ARID;\n  wire [7:0]axi_interconnect_0_to_s00_couplers_ARLEN;\n  wire [0:0]axi_interconnect_0_to_s00_couplers_ARLOCK;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_ARPROT;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARQOS;\n  wire axi_interconnect_0_to_s00_couplers_ARREADY;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARREGION;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_ARSIZE;\n  wire axi_interconnect_0_to_s00_couplers_ARVALID;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_AWADDR;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_AWBURST;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWCACHE;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_AWID;\n  wire [7:0]axi_interconnect_0_to_s00_couplers_AWLEN;\n  wire [0:0]axi_interconnect_0_to_s00_couplers_AWLOCK;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_AWPROT;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWQOS;\n  wire axi_interconnect_0_to_s00_couplers_AWREADY;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWREGION;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_AWSIZE;\n  wire axi_interconnect_0_to_s00_couplers_AWVALID;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_BID;\n  wire axi_interconnect_0_to_s00_couplers_BREADY;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_BRESP;\n  wire axi_interconnect_0_to_s00_couplers_BVALID;\n  wire [511:0]axi_interconnect_0_to_s00_couplers_RDATA;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_RID;\n  wire axi_interconnect_0_to_s00_couplers_RLAST;\n  wire axi_interconnect_0_to_s00_couplers_RREADY;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_RRESP;\n  wire axi_interconnect_0_to_s00_couplers_RVALID;\n  wire [511:0]axi_interconnect_0_to_s00_couplers_WDATA;\n  wire axi_interconnect_0_to_s00_couplers_WLAST;\n  wire axi_interconnect_0_to_s00_couplers_WREADY;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_WSTRB;\n  wire axi_interconnect_0_to_s00_couplers_WVALID;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_ARADDR;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_ARBURST;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARCACHE;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_ARID;\n  wire [7:0]axi_interconnect_0_to_s01_couplers_ARLEN;\n  wire [0:0]axi_interconnect_0_to_s01_couplers_ARLOCK;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_ARPROT;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARQOS;\n  wire axi_interconnect_0_to_s01_couplers_ARREADY;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARREGION;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_ARSIZE;\n  wire axi_interconnect_0_to_s01_couplers_ARVALID;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_AWADDR;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_AWBURST;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWCACHE;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_AWID;\n  wire [7:0]axi_interconnect_0_to_s01_couplers_AWLEN;\n  wire [0:0]axi_interconnect_0_to_s01_couplers_AWLOCK;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_AWPROT;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWQOS;\n  wire axi_interconnect_0_to_s01_couplers_AWREADY;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWREGION;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_AWSIZE;\n  wire axi_interconnect_0_to_s01_couplers_AWVALID;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_BID;\n  wire axi_interconnect_0_to_s01_couplers_BREADY;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_BRESP;\n  wire axi_interconnect_0_to_s01_couplers_BVALID;\n  wire [511:0]axi_interconnect_0_to_s01_couplers_RDATA;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_RID;\n  wire axi_interconnect_0_to_s01_couplers_RLAST;\n  wire axi_interconnect_0_to_s01_couplers_RREADY;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_RRESP;\n  wire axi_interconnect_0_to_s01_couplers_RVALID;\n  wire [511:0]axi_interconnect_0_to_s01_couplers_WDATA;\n  wire axi_interconnect_0_to_s01_couplers_WLAST;\n  wire axi_interconnect_0_to_s01_couplers_WREADY;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_WSTRB;\n  wire axi_interconnect_0_to_s01_couplers_WVALID;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m00_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m00_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARQOS;\n  wire m00_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m00_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m00_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m00_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWQOS;\n  wire m00_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m00_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_BID;\n  wire m00_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_BRESP;\n  wire m00_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m00_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_RID;\n  wire m00_couplers_to_axi_interconnect_0_RLAST;\n  wire m00_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_RRESP;\n  wire m00_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m00_couplers_to_axi_interconnect_0_WDATA;\n  wire m00_couplers_to_axi_interconnect_0_WLAST;\n  wire m00_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_WSTRB;\n  wire m00_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m01_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m01_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARQOS;\n  wire m01_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m01_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m01_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m01_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWQOS;\n  wire m01_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m01_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_BID;\n  wire m01_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_BRESP;\n  wire m01_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m01_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_RID;\n  wire m01_couplers_to_axi_interconnect_0_RLAST;\n  wire m01_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_RRESP;\n  wire m01_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m01_couplers_to_axi_interconnect_0_WDATA;\n  wire m01_couplers_to_axi_interconnect_0_WLAST;\n  wire m01_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_WSTRB;\n  wire m01_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m02_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m02_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARQOS;\n  wire m02_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m02_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m02_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m02_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWQOS;\n  wire m02_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m02_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_BID;\n  wire m02_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_BRESP;\n  wire m02_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m02_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_RID;\n  wire m02_couplers_to_axi_interconnect_0_RLAST;\n  wire m02_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_RRESP;\n  wire m02_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m02_couplers_to_axi_interconnect_0_WDATA;\n  wire m02_couplers_to_axi_interconnect_0_WLAST;\n  wire m02_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_WSTRB;\n  wire m02_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m03_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m03_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARQOS;\n  wire m03_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m03_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m03_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m03_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWQOS;\n  wire m03_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m03_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_BID;\n  wire m03_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_BRESP;\n  wire m03_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m03_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_RID;\n  wire m03_couplers_to_axi_interconnect_0_RLAST;\n  wire m03_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_RRESP;\n  wire m03_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m03_couplers_to_axi_interconnect_0_WDATA;\n  wire m03_couplers_to_axi_interconnect_0_WLAST;\n  wire m03_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_WSTRB;\n  wire m03_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]s00_couplers_to_xbar_ARADDR;\n  wire [1:0]s00_couplers_to_xbar_ARBURST;\n  wire [3:0]s00_couplers_to_xbar_ARCACHE;\n  wire [5:0]s00_couplers_to_xbar_ARID;\n  wire [7:0]s00_couplers_to_xbar_ARLEN;\n  wire [0:0]s00_couplers_to_xbar_ARLOCK;\n  wire [2:0]s00_couplers_to_xbar_ARPROT;\n  wire [3:0]s00_couplers_to_xbar_ARQOS;\n  wire [0:0]s00_couplers_to_xbar_ARREADY;\n  wire [2:0]s00_couplers_to_xbar_ARSIZE;\n  wire s00_couplers_to_xbar_ARVALID;\n  wire [63:0]s00_couplers_to_xbar_AWADDR;\n  wire [1:0]s00_couplers_to_xbar_AWBURST;\n  wire [3:0]s00_couplers_to_xbar_AWCACHE;\n  wire [5:0]s00_couplers_to_xbar_AWID;\n  wire [7:0]s00_couplers_to_xbar_AWLEN;\n  wire [0:0]s00_couplers_to_xbar_AWLOCK;\n  wire [2:0]s00_couplers_to_xbar_AWPROT;\n  wire [3:0]s00_couplers_to_xbar_AWQOS;\n  wire [0:0]s00_couplers_to_xbar_AWREADY;\n  wire [2:0]s00_couplers_to_xbar_AWSIZE;\n  wire s00_couplers_to_xbar_AWVALID;\n  wire [6:0]s00_couplers_to_xbar_BID;\n  wire s00_couplers_to_xbar_BREADY;\n  wire [1:0]s00_couplers_to_xbar_BRESP;\n  wire [0:0]s00_couplers_to_xbar_BVALID;\n  wire [511:0]s00_couplers_to_xbar_RDATA;\n  wire [6:0]s00_couplers_to_xbar_RID;\n  wire [0:0]s00_couplers_to_xbar_RLAST;\n  wire s00_couplers_to_xbar_RREADY;\n  wire [1:0]s00_couplers_to_xbar_RRESP;\n  wire [0:0]s00_couplers_to_xbar_RVALID;\n  wire [511:0]s00_couplers_to_xbar_WDATA;\n  wire s00_couplers_to_xbar_WLAST;\n  wire [0:0]s00_couplers_to_xbar_WREADY;\n  wire [63:0]s00_couplers_to_xbar_WSTRB;\n  wire s00_couplers_to_xbar_WVALID;\n  wire [63:0]s01_couplers_to_xbar_ARADDR;\n  wire [1:0]s01_couplers_to_xbar_ARBURST;\n  wire [3:0]s01_couplers_to_xbar_ARCACHE;\n  wire [5:0]s01_couplers_to_xbar_ARID;\n  wire [7:0]s01_couplers_to_xbar_ARLEN;\n  wire [0:0]s01_couplers_to_xbar_ARLOCK;\n  wire [2:0]s01_couplers_to_xbar_ARPROT;\n  wire [3:0]s01_couplers_to_xbar_ARQOS;\n  wire [1:1]s01_couplers_to_xbar_ARREADY;\n  wire [2:0]s01_couplers_to_xbar_ARSIZE;\n  wire s01_couplers_to_xbar_ARVALID;\n  wire [63:0]s01_couplers_to_xbar_AWADDR;\n  wire [1:0]s01_couplers_to_xbar_AWBURST;\n  wire [3:0]s01_couplers_to_xbar_AWCACHE;\n  wire [5:0]s01_couplers_to_xbar_AWID;\n  wire [7:0]s01_couplers_to_xbar_AWLEN;\n  wire [0:0]s01_couplers_to_xbar_AWLOCK;\n  wire [2:0]s01_couplers_to_xbar_AWPROT;\n  wire [3:0]s01_couplers_to_xbar_AWQOS;\n  wire [1:1]s01_couplers_to_xbar_AWREADY;\n  wire [2:0]s01_couplers_to_xbar_AWSIZE;\n  wire s01_couplers_to_xbar_AWVALID;\n  wire [13:7]s01_couplers_to_xbar_BID;\n  wire s01_couplers_to_xbar_BREADY;\n  wire [3:2]s01_couplers_to_xbar_BRESP;\n  wire [1:1]s01_couplers_to_xbar_BVALID;\n  wire [1023:512]s01_couplers_to_xbar_RDATA;\n  wire [13:7]s01_couplers_to_xbar_RID;\n  wire [1:1]s01_couplers_to_xbar_RLAST;\n  wire s01_couplers_to_xbar_RREADY;\n  wire [3:2]s01_couplers_to_xbar_RRESP;\n  wire [1:1]s01_couplers_to_xbar_RVALID;\n  wire [511:0]s01_couplers_to_xbar_WDATA;\n  wire s01_couplers_to_xbar_WLAST;\n  wire [1:1]s01_couplers_to_xbar_WREADY;\n  wire [63:0]s01_couplers_to_xbar_WSTRB;\n  wire s01_couplers_to_xbar_WVALID;\n  wire [63:0]xbar_to_m00_couplers_ARADDR;\n  wire [1:0]xbar_to_m00_couplers_ARBURST;\n  wire [3:0]xbar_to_m00_couplers_ARCACHE;\n  wire [6:0]xbar_to_m00_couplers_ARID;\n  wire [7:0]xbar_to_m00_couplers_ARLEN;\n  wire [0:0]xbar_to_m00_couplers_ARLOCK;\n  wire [2:0]xbar_to_m00_couplers_ARPROT;\n  wire [3:0]xbar_to_m00_couplers_ARQOS;\n  wire xbar_to_m00_couplers_ARREADY;\n  wire [3:0]xbar_to_m00_couplers_ARREGION;\n  wire [2:0]xbar_to_m00_couplers_ARSIZE;\n  wire [0:0]xbar_to_m00_couplers_ARVALID;\n  wire [63:0]xbar_to_m00_couplers_AWADDR;\n  wire [1:0]xbar_to_m00_couplers_AWBURST;\n  wire [3:0]xbar_to_m00_couplers_AWCACHE;\n  wire [6:0]xbar_to_m00_couplers_AWID;\n  wire [7:0]xbar_to_m00_couplers_AWLEN;\n  wire [0:0]xbar_to_m00_couplers_AWLOCK;\n  wire [2:0]xbar_to_m00_couplers_AWPROT;\n  wire [3:0]xbar_to_m00_couplers_AWQOS;\n  wire xbar_to_m00_couplers_AWREADY;\n  wire [3:0]xbar_to_m00_couplers_AWREGION;\n  wire [2:0]xbar_to_m00_couplers_AWSIZE;\n  wire [0:0]xbar_to_m00_couplers_AWVALID;\n  wire [6:0]xbar_to_m00_couplers_BID;\n  wire [0:0]xbar_to_m00_couplers_BREADY;\n  wire [1:0]xbar_to_m00_couplers_BRESP;\n  wire xbar_to_m00_couplers_BVALID;\n  wire [511:0]xbar_to_m00_couplers_RDATA;\n  wire [6:0]xbar_to_m00_couplers_RID;\n  wire xbar_to_m00_couplers_RLAST;\n  wire [0:0]xbar_to_m00_couplers_RREADY;\n  wire [1:0]xbar_to_m00_couplers_RRESP;\n  wire xbar_to_m00_couplers_RVALID;\n  wire [511:0]xbar_to_m00_couplers_WDATA;\n  wire [0:0]xbar_to_m00_couplers_WLAST;\n  wire xbar_to_m00_couplers_WREADY;\n  wire [63:0]xbar_to_m00_couplers_WSTRB;\n  wire [0:0]xbar_to_m00_couplers_WVALID;\n  wire [127:64]xbar_to_m01_couplers_ARADDR;\n  wire [3:2]xbar_to_m01_couplers_ARBURST;\n  wire [7:4]xbar_to_m01_couplers_ARCACHE;\n  wire [13:7]xbar_to_m01_couplers_ARID;\n  wire [15:8]xbar_to_m01_couplers_ARLEN;\n  wire [1:1]xbar_to_m01_couplers_ARLOCK;\n  wire [5:3]xbar_to_m01_couplers_ARPROT;\n  wire [7:4]xbar_to_m01_couplers_ARQOS;\n  wire xbar_to_m01_couplers_ARREADY;\n  wire [7:4]xbar_to_m01_couplers_ARREGION;\n  wire [5:3]xbar_to_m01_couplers_ARSIZE;\n  wire [1:1]xbar_to_m01_couplers_ARVALID;\n  wire [127:64]xbar_to_m01_couplers_AWADDR;\n  wire [3:2]xbar_to_m01_couplers_AWBURST;\n  wire [7:4]xbar_to_m01_couplers_AWCACHE;\n  wire [13:7]xbar_to_m01_couplers_AWID;\n  wire [15:8]xbar_to_m01_couplers_AWLEN;\n  wire [1:1]xbar_to_m01_couplers_AWLOCK;\n  wire [5:3]xbar_to_m01_couplers_AWPROT;\n  wire [7:4]xbar_to_m01_couplers_AWQOS;\n  wire xbar_to_m01_couplers_AWREADY;\n  wire [7:4]xbar_to_m01_couplers_AWREGION;\n  wire [5:3]xbar_to_m01_couplers_AWSIZE;\n  wire [1:1]xbar_to_m01_couplers_AWVALID;\n  wire [6:0]xbar_to_m01_couplers_BID;\n  wire [1:1]xbar_to_m01_couplers_BREADY;\n  wire [1:0]xbar_to_m01_couplers_BRESP;\n  wire xbar_to_m01_couplers_BVALID;\n  wire [511:0]xbar_to_m01_couplers_RDATA;\n  wire [6:0]xbar_to_m01_couplers_RID;\n  wire xbar_to_m01_couplers_RLAST;\n  wire [1:1]xbar_to_m01_couplers_RREADY;\n  wire [1:0]xbar_to_m01_couplers_RRESP;\n  wire xbar_to_m01_couplers_RVALID;\n  wire [1023:512]xbar_to_m01_couplers_WDATA;\n  wire [1:1]xbar_to_m01_couplers_WLAST;\n  wire xbar_to_m01_couplers_WREADY;\n  wire [127:64]xbar_to_m01_couplers_WSTRB;\n  wire [1:1]xbar_to_m01_couplers_WVALID;\n  wire [191:128]xbar_to_m02_couplers_ARADDR;\n  wire [5:4]xbar_to_m02_couplers_ARBURST;\n  wire [11:8]xbar_to_m02_couplers_ARCACHE;\n  wire [20:14]xbar_to_m02_couplers_ARID;\n  wire [23:16]xbar_to_m02_couplers_ARLEN;\n  wire [2:2]xbar_to_m02_couplers_ARLOCK;\n  wire [8:6]xbar_to_m02_couplers_ARPROT;\n  wire [11:8]xbar_to_m02_couplers_ARQOS;\n  wire xbar_to_m02_couplers_ARREADY;\n  wire [11:8]xbar_to_m02_couplers_ARREGION;\n  wire [8:6]xbar_to_m02_couplers_ARSIZE;\n  wire [2:2]xbar_to_m02_couplers_ARVALID;\n  wire [191:128]xbar_to_m02_couplers_AWADDR;\n  wire [5:4]xbar_to_m02_couplers_AWBURST;\n  wire [11:8]xbar_to_m02_couplers_AWCACHE;\n  wire [20:14]xbar_to_m02_couplers_AWID;\n  wire [23:16]xbar_to_m02_couplers_AWLEN;\n  wire [2:2]xbar_to_m02_couplers_AWLOCK;\n  wire [8:6]xbar_to_m02_couplers_AWPROT;\n  wire [11:8]xbar_to_m02_couplers_AWQOS;\n  wire xbar_to_m02_couplers_AWREADY;\n  wire [11:8]xbar_to_m02_couplers_AWREGION;\n  wire [8:6]xbar_to_m02_couplers_AWSIZE;\n  wire [2:2]xbar_to_m02_couplers_AWVALID;\n  wire [6:0]xbar_to_m02_couplers_BID;\n  wire [2:2]xbar_to_m02_couplers_BREADY;\n  wire [1:0]xbar_to_m02_couplers_BRESP;\n  wire xbar_to_m02_couplers_BVALID;\n  wire [511:0]xbar_to_m02_couplers_RDATA;\n  wire [6:0]xbar_to_m02_couplers_RID;\n  wire xbar_to_m02_couplers_RLAST;\n  wire [2:2]xbar_to_m02_couplers_RREADY;\n  wire [1:0]xbar_to_m02_couplers_RRESP;\n  wire xbar_to_m02_couplers_RVALID;\n  wire [1535:1024]xbar_to_m02_couplers_WDATA;\n  wire [2:2]xbar_to_m02_couplers_WLAST;\n  wire xbar_to_m02_couplers_WREADY;\n  wire [191:128]xbar_to_m02_couplers_WSTRB;\n  wire [2:2]xbar_to_m02_couplers_WVALID;\n  wire [255:192]xbar_to_m03_couplers_ARADDR;\n  wire [7:6]xbar_to_m03_couplers_ARBURST;\n  wire [15:12]xbar_to_m03_couplers_ARCACHE;\n  wire [27:21]xbar_to_m03_couplers_ARID;\n  wire [31:24]xbar_to_m03_couplers_ARLEN;\n  wire [3:3]xbar_to_m03_couplers_ARLOCK;\n  wire [11:9]xbar_to_m03_couplers_ARPROT;\n  wire [15:12]xbar_to_m03_couplers_ARQOS;\n  wire xbar_to_m03_couplers_ARREADY;\n  wire [15:12]xbar_to_m03_couplers_ARREGION;\n  wire [11:9]xbar_to_m03_couplers_ARSIZE;\n  wire [3:3]xbar_to_m03_couplers_ARVALID;\n  wire [255:192]xbar_to_m03_couplers_AWADDR;\n  wire [7:6]xbar_to_m03_couplers_AWBURST;\n  wire [15:12]xbar_to_m03_couplers_AWCACHE;\n  wire [27:21]xbar_to_m03_couplers_AWID;\n  wire [31:24]xbar_to_m03_couplers_AWLEN;\n  wire [3:3]xbar_to_m03_couplers_AWLOCK;\n  wire [11:9]xbar_to_m03_couplers_AWPROT;\n  wire [15:12]xbar_to_m03_couplers_AWQOS;\n  wire xbar_to_m03_couplers_AWREADY;\n  wire [15:12]xbar_to_m03_couplers_AWREGION;\n  wire [11:9]xbar_to_m03_couplers_AWSIZE;\n  wire [3:3]xbar_to_m03_couplers_AWVALID;\n  wire [6:0]xbar_to_m03_couplers_BID;\n  wire [3:3]xbar_to_m03_couplers_BREADY;\n  wire [1:0]xbar_to_m03_couplers_BRESP;\n  wire xbar_to_m03_couplers_BVALID;\n  wire [511:0]xbar_to_m03_couplers_RDATA;\n  wire [6:0]xbar_to_m03_couplers_RID;\n  wire xbar_to_m03_couplers_RLAST;\n  wire [3:3]xbar_to_m03_couplers_RREADY;\n  wire [1:0]xbar_to_m03_couplers_RRESP;\n  wire xbar_to_m03_couplers_RVALID;\n  wire [2047:1536]xbar_to_m03_couplers_WDATA;\n  wire [3:3]xbar_to_m03_couplers_WLAST;\n  wire xbar_to_m03_couplers_WREADY;\n  wire [255:192]xbar_to_m03_couplers_WSTRB;\n  wire [3:3]xbar_to_m03_couplers_WVALID;\n\n  assign M00_AXI_araddr[63:0] = m00_couplers_to_axi_interconnect_0_ARADDR;\n  assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_interconnect_0_ARBURST;\n  assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M00_AXI_arid[6:0] = m00_couplers_to_axi_interconnect_0_ARID;\n  assign M00_AXI_arlen[7:0] = m00_couplers_to_axi_interconnect_0_ARLEN;\n  assign M00_AXI_arlock[0] = m00_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_interconnect_0_ARPROT;\n  assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_interconnect_0_ARQOS;\n  assign M00_AXI_arregion[3:0] = m00_couplers_to_axi_interconnect_0_ARREGION;\n  assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M00_AXI_arvalid = m00_couplers_to_axi_interconnect_0_ARVALID;\n  assign M00_AXI_awaddr[63:0] = m00_couplers_to_axi_interconnect_0_AWADDR;\n  assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_interconnect_0_AWBURST;\n  assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M00_AXI_awid[6:0] = m00_couplers_to_axi_interconnect_0_AWID;\n  assign M00_AXI_awlen[7:0] = m00_couplers_to_axi_interconnect_0_AWLEN;\n  assign M00_AXI_awlock[0] = m00_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_interconnect_0_AWPROT;\n  assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_interconnect_0_AWQOS;\n  assign M00_AXI_awregion[3:0] = m00_couplers_to_axi_interconnect_0_AWREGION;\n  assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M00_AXI_awvalid = m00_couplers_to_axi_interconnect_0_AWVALID;\n  assign M00_AXI_bready = m00_couplers_to_axi_interconnect_0_BREADY;\n  assign M00_AXI_rready = m00_couplers_to_axi_interconnect_0_RREADY;\n  assign M00_AXI_wdata[511:0] = m00_couplers_to_axi_interconnect_0_WDATA;\n  assign M00_AXI_wlast = m00_couplers_to_axi_interconnect_0_WLAST;\n  assign M00_AXI_wstrb[63:0] = m00_couplers_to_axi_interconnect_0_WSTRB;\n  assign M00_AXI_wvalid = m00_couplers_to_axi_interconnect_0_WVALID;\n  assign M01_AXI_araddr[63:0] = m01_couplers_to_axi_interconnect_0_ARADDR;\n  assign M01_AXI_arburst[1:0] = m01_couplers_to_axi_interconnect_0_ARBURST;\n  assign M01_AXI_arcache[3:0] = m01_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M01_AXI_arid[6:0] = m01_couplers_to_axi_interconnect_0_ARID;\n  assign M01_AXI_arlen[7:0] = m01_couplers_to_axi_interconnect_0_ARLEN;\n  assign M01_AXI_arlock[0] = m01_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M01_AXI_arprot[2:0] = m01_couplers_to_axi_interconnect_0_ARPROT;\n  assign M01_AXI_arqos[3:0] = m01_couplers_to_axi_interconnect_0_ARQOS;\n  assign M01_AXI_arregion[3:0] = m01_couplers_to_axi_interconnect_0_ARREGION;\n  assign M01_AXI_arsize[2:0] = m01_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M01_AXI_arvalid = m01_couplers_to_axi_interconnect_0_ARVALID;\n  assign M01_AXI_awaddr[63:0] = m01_couplers_to_axi_interconnect_0_AWADDR;\n  assign M01_AXI_awburst[1:0] = m01_couplers_to_axi_interconnect_0_AWBURST;\n  assign M01_AXI_awcache[3:0] = m01_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M01_AXI_awid[6:0] = m01_couplers_to_axi_interconnect_0_AWID;\n  assign M01_AXI_awlen[7:0] = m01_couplers_to_axi_interconnect_0_AWLEN;\n  assign M01_AXI_awlock[0] = m01_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M01_AXI_awprot[2:0] = m01_couplers_to_axi_interconnect_0_AWPROT;\n  assign M01_AXI_awqos[3:0] = m01_couplers_to_axi_interconnect_0_AWQOS;\n  assign M01_AXI_awregion[3:0] = m01_couplers_to_axi_interconnect_0_AWREGION;\n  assign M01_AXI_awsize[2:0] = m01_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M01_AXI_awvalid = m01_couplers_to_axi_interconnect_0_AWVALID;\n  assign M01_AXI_bready = m01_couplers_to_axi_interconnect_0_BREADY;\n  assign M01_AXI_rready = m01_couplers_to_axi_interconnect_0_RREADY;\n  assign M01_AXI_wdata[511:0] = m01_couplers_to_axi_interconnect_0_WDATA;\n  assign M01_AXI_wlast = m01_couplers_to_axi_interconnect_0_WLAST;\n  assign M01_AXI_wstrb[63:0] = m01_couplers_to_axi_interconnect_0_WSTRB;\n  assign M01_AXI_wvalid = m01_couplers_to_axi_interconnect_0_WVALID;\n  assign M02_AXI_araddr[63:0] = m02_couplers_to_axi_interconnect_0_ARADDR;\n  assign M02_AXI_arburst[1:0] = m02_couplers_to_axi_interconnect_0_ARBURST;\n  assign M02_AXI_arcache[3:0] = m02_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M02_AXI_arid[6:0] = m02_couplers_to_axi_interconnect_0_ARID;\n  assign M02_AXI_arlen[7:0] = m02_couplers_to_axi_interconnect_0_ARLEN;\n  assign M02_AXI_arlock[0] = m02_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M02_AXI_arprot[2:0] = m02_couplers_to_axi_interconnect_0_ARPROT;\n  assign M02_AXI_arqos[3:0] = m02_couplers_to_axi_interconnect_0_ARQOS;\n  assign M02_AXI_arregion[3:0] = m02_couplers_to_axi_interconnect_0_ARREGION;\n  assign M02_AXI_arsize[2:0] = m02_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M02_AXI_arvalid = m02_couplers_to_axi_interconnect_0_ARVALID;\n  assign M02_AXI_awaddr[63:0] = m02_couplers_to_axi_interconnect_0_AWADDR;\n  assign M02_AXI_awburst[1:0] = m02_couplers_to_axi_interconnect_0_AWBURST;\n  assign M02_AXI_awcache[3:0] = m02_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M02_AXI_awid[6:0] = m02_couplers_to_axi_interconnect_0_AWID;\n  assign M02_AXI_awlen[7:0] = m02_couplers_to_axi_interconnect_0_AWLEN;\n  assign M02_AXI_awlock[0] = m02_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M02_AXI_awprot[2:0] = m02_couplers_to_axi_interconnect_0_AWPROT;\n  assign M02_AXI_awqos[3:0] = m02_couplers_to_axi_interconnect_0_AWQOS;\n  assign M02_AXI_awregion[3:0] = m02_couplers_to_axi_interconnect_0_AWREGION;\n  assign M02_AXI_awsize[2:0] = m02_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M02_AXI_awvalid = m02_couplers_to_axi_interconnect_0_AWVALID;\n  assign M02_AXI_bready = m02_couplers_to_axi_interconnect_0_BREADY;\n  assign M02_AXI_rready = m02_couplers_to_axi_interconnect_0_RREADY;\n  assign M02_AXI_wdata[511:0] = m02_couplers_to_axi_interconnect_0_WDATA;\n  assign M02_AXI_wlast = m02_couplers_to_axi_interconnect_0_WLAST;\n  assign M02_AXI_wstrb[63:0] = m02_couplers_to_axi_interconnect_0_WSTRB;\n  assign M02_AXI_wvalid = m02_couplers_to_axi_interconnect_0_WVALID;\n  assign M03_AXI_araddr[63:0] = m03_couplers_to_axi_interconnect_0_ARADDR;\n  assign M03_AXI_arburst[1:0] = m03_couplers_to_axi_interconnect_0_ARBURST;\n  assign M03_AXI_arcache[3:0] = m03_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M03_AXI_arid[6:0] = m03_couplers_to_axi_interconnect_0_ARID;\n  assign M03_AXI_arlen[7:0] = m03_couplers_to_axi_interconnect_0_ARLEN;\n  assign M03_AXI_arlock[0] = m03_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M03_AXI_arprot[2:0] = m03_couplers_to_axi_interconnect_0_ARPROT;\n  assign M03_AXI_arqos[3:0] = m03_couplers_to_axi_interconnect_0_ARQOS;\n  assign M03_AXI_arregion[3:0] = m03_couplers_to_axi_interconnect_0_ARREGION;\n  assign M03_AXI_arsize[2:0] = m03_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M03_AXI_arvalid = m03_couplers_to_axi_interconnect_0_ARVALID;\n  assign M03_AXI_awaddr[63:0] = m03_couplers_to_axi_interconnect_0_AWADDR;\n  assign M03_AXI_awburst[1:0] = m03_couplers_to_axi_interconnect_0_AWBURST;\n  assign M03_AXI_awcache[3:0] = m03_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M03_AXI_awid[6:0] = m03_couplers_to_axi_interconnect_0_AWID;\n  assign M03_AXI_awlen[7:0] = m03_couplers_to_axi_interconnect_0_AWLEN;\n  assign M03_AXI_awlock[0] = m03_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M03_AXI_awprot[2:0] = m03_couplers_to_axi_interconnect_0_AWPROT;\n  assign M03_AXI_awqos[3:0] = m03_couplers_to_axi_interconnect_0_AWQOS;\n  assign M03_AXI_awregion[3:0] = m03_couplers_to_axi_interconnect_0_AWREGION;\n  assign M03_AXI_awsize[2:0] = m03_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M03_AXI_awvalid = m03_couplers_to_axi_interconnect_0_AWVALID;\n  assign M03_AXI_bready = m03_couplers_to_axi_interconnect_0_BREADY;\n  assign M03_AXI_rready = m03_couplers_to_axi_interconnect_0_RREADY;\n  assign M03_AXI_wdata[511:0] = m03_couplers_to_axi_interconnect_0_WDATA;\n  assign M03_AXI_wlast = m03_couplers_to_axi_interconnect_0_WLAST;\n  assign M03_AXI_wstrb[63:0] = m03_couplers_to_axi_interconnect_0_WSTRB;\n  assign M03_AXI_wvalid = m03_couplers_to_axi_interconnect_0_WVALID;\n  assign S00_AXI_arready = axi_interconnect_0_to_s00_couplers_ARREADY;\n  assign S00_AXI_awready = axi_interconnect_0_to_s00_couplers_AWREADY;\n  assign S00_AXI_bid[5:0] = axi_interconnect_0_to_s00_couplers_BID;\n  assign S00_AXI_bresp[1:0] = axi_interconnect_0_to_s00_couplers_BRESP;\n  assign S00_AXI_bvalid = axi_interconnect_0_to_s00_couplers_BVALID;\n  assign S00_AXI_rdata[511:0] = axi_interconnect_0_to_s00_couplers_RDATA;\n  assign S00_AXI_rid[5:0] = axi_interconnect_0_to_s00_couplers_RID;\n  assign S00_AXI_rlast = axi_interconnect_0_to_s00_couplers_RLAST;\n  assign S00_AXI_rresp[1:0] = axi_interconnect_0_to_s00_couplers_RRESP;\n  assign S00_AXI_rvalid = axi_interconnect_0_to_s00_couplers_RVALID;\n  assign S00_AXI_wready = axi_interconnect_0_to_s00_couplers_WREADY;\n  assign S01_AXI_arready = axi_interconnect_0_to_s01_couplers_ARREADY;\n  assign S01_AXI_awready = axi_interconnect_0_to_s01_couplers_AWREADY;\n  assign S01_AXI_bid[5:0] = axi_interconnect_0_to_s01_couplers_BID;\n  assign S01_AXI_bresp[1:0] = axi_interconnect_0_to_s01_couplers_BRESP;\n  assign S01_AXI_bvalid = axi_interconnect_0_to_s01_couplers_BVALID;\n  assign S01_AXI_rdata[511:0] = axi_interconnect_0_to_s01_couplers_RDATA;\n  assign S01_AXI_rid[5:0] = axi_interconnect_0_to_s01_couplers_RID;\n  assign S01_AXI_rlast = axi_interconnect_0_to_s01_couplers_RLAST;\n  assign S01_AXI_rresp[1:0] = axi_interconnect_0_to_s01_couplers_RRESP;\n  assign S01_AXI_rvalid = axi_interconnect_0_to_s01_couplers_RVALID;\n  assign S01_AXI_wready = axi_interconnect_0_to_s01_couplers_WREADY;\n  assign axi_interconnect_0_ACLK_net = ACLK;\n  assign axi_interconnect_0_ARESETN_net = ARESETN;\n  assign axi_interconnect_0_to_s00_couplers_ARADDR = S00_AXI_araddr[63:0];\n  assign axi_interconnect_0_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];\n  assign axi_interconnect_0_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARID = S00_AXI_arid[5:0];\n  assign axi_interconnect_0_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0];\n  assign axi_interconnect_0_to_s00_couplers_ARLOCK = S00_AXI_arlock[0];\n  assign axi_interconnect_0_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];\n  assign axi_interconnect_0_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARREGION = S00_AXI_arregion[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];\n  assign axi_interconnect_0_to_s00_couplers_ARVALID = S00_AXI_arvalid;\n  assign axi_interconnect_0_to_s00_couplers_AWADDR = S00_AXI_awaddr[63:0];\n  assign axi_interconnect_0_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];\n  assign axi_interconnect_0_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWID = S00_AXI_awid[5:0];\n  assign axi_interconnect_0_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0];\n  assign axi_interconnect_0_to_s00_couplers_AWLOCK = S00_AXI_awlock[0];\n  assign axi_interconnect_0_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];\n  assign axi_interconnect_0_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWREGION = S00_AXI_awregion[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];\n  assign axi_interconnect_0_to_s00_couplers_AWVALID = S00_AXI_awvalid;\n  assign axi_interconnect_0_to_s00_couplers_BREADY = S00_AXI_bready;\n  assign axi_interconnect_0_to_s00_couplers_RREADY = S00_AXI_rready;\n  assign axi_interconnect_0_to_s00_couplers_WDATA = S00_AXI_wdata[511:0];\n  assign axi_interconnect_0_to_s00_couplers_WLAST = S00_AXI_wlast;\n  assign axi_interconnect_0_to_s00_couplers_WSTRB = S00_AXI_wstrb[63:0];\n  assign axi_interconnect_0_to_s00_couplers_WVALID = S00_AXI_wvalid;\n  assign axi_interconnect_0_to_s01_couplers_ARADDR = S01_AXI_araddr[63:0];\n  assign axi_interconnect_0_to_s01_couplers_ARBURST = S01_AXI_arburst[1:0];\n  assign axi_interconnect_0_to_s01_couplers_ARCACHE = S01_AXI_arcache[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARID = S01_AXI_arid[5:0];\n  assign axi_interconnect_0_to_s01_couplers_ARLEN = S01_AXI_arlen[7:0];\n  assign axi_interconnect_0_to_s01_couplers_ARLOCK = S01_AXI_arlock[0];\n  assign axi_interconnect_0_to_s01_couplers_ARPROT = S01_AXI_arprot[2:0];\n  assign axi_interconnect_0_to_s01_couplers_ARQOS = S01_AXI_arqos[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARREGION = S01_AXI_arregion[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARSIZE = S01_AXI_arsize[2:0];\n  assign axi_interconnect_0_to_s01_couplers_ARVALID = S01_AXI_arvalid;\n  assign axi_interconnect_0_to_s01_couplers_AWADDR = S01_AXI_awaddr[63:0];\n  assign axi_interconnect_0_to_s01_couplers_AWBURST = S01_AXI_awburst[1:0];\n  assign axi_interconnect_0_to_s01_couplers_AWCACHE = S01_AXI_awcache[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWID = S01_AXI_awid[5:0];\n  assign axi_interconnect_0_to_s01_couplers_AWLEN = S01_AXI_awlen[7:0];\n  assign axi_interconnect_0_to_s01_couplers_AWLOCK = S01_AXI_awlock[0];\n  assign axi_interconnect_0_to_s01_couplers_AWPROT = S01_AXI_awprot[2:0];\n  assign axi_interconnect_0_to_s01_couplers_AWQOS = S01_AXI_awqos[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWREGION = S01_AXI_awregion[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWSIZE = S01_AXI_awsize[2:0];\n  assign axi_interconnect_0_to_s01_couplers_AWVALID = S01_AXI_awvalid;\n  assign axi_interconnect_0_to_s01_couplers_BREADY = S01_AXI_bready;\n  assign axi_interconnect_0_to_s01_couplers_RREADY = S01_AXI_rready;\n  assign axi_interconnect_0_to_s01_couplers_WDATA = S01_AXI_wdata[511:0];\n  assign axi_interconnect_0_to_s01_couplers_WLAST = S01_AXI_wlast;\n  assign axi_interconnect_0_to_s01_couplers_WSTRB = S01_AXI_wstrb[63:0];\n  assign axi_interconnect_0_to_s01_couplers_WVALID = S01_AXI_wvalid;\n  assign m00_couplers_to_axi_interconnect_0_ARREADY = M00_AXI_arready;\n  assign m00_couplers_to_axi_interconnect_0_AWREADY = M00_AXI_awready;\n  assign m00_couplers_to_axi_interconnect_0_BID = M00_AXI_bid[6:0];\n  assign m00_couplers_to_axi_interconnect_0_BRESP = M00_AXI_bresp[1:0];\n  assign m00_couplers_to_axi_interconnect_0_BVALID = M00_AXI_bvalid;\n  assign m00_couplers_to_axi_interconnect_0_RDATA = M00_AXI_rdata[511:0];\n  assign m00_couplers_to_axi_interconnect_0_RID = M00_AXI_rid[6:0];\n  assign m00_couplers_to_axi_interconnect_0_RLAST = M00_AXI_rlast;\n  assign m00_couplers_to_axi_interconnect_0_RRESP = M00_AXI_rresp[1:0];\n  assign m00_couplers_to_axi_interconnect_0_RVALID = M00_AXI_rvalid;\n  assign m00_couplers_to_axi_interconnect_0_WREADY = M00_AXI_wready;\n  assign m01_couplers_to_axi_interconnect_0_ARREADY = M01_AXI_arready;\n  assign m01_couplers_to_axi_interconnect_0_AWREADY = M01_AXI_awready;\n  assign m01_couplers_to_axi_interconnect_0_BID = M01_AXI_bid[6:0];\n  assign m01_couplers_to_axi_interconnect_0_BRESP = M01_AXI_bresp[1:0];\n  assign m01_couplers_to_axi_interconnect_0_BVALID = M01_AXI_bvalid;\n  assign m01_couplers_to_axi_interconnect_0_RDATA = M01_AXI_rdata[511:0];\n  assign m01_couplers_to_axi_interconnect_0_RID = M01_AXI_rid[6:0];\n  assign m01_couplers_to_axi_interconnect_0_RLAST = M01_AXI_rlast;\n  assign m01_couplers_to_axi_interconnect_0_RRESP = M01_AXI_rresp[1:0];\n  assign m01_couplers_to_axi_interconnect_0_RVALID = M01_AXI_rvalid;\n  assign m01_couplers_to_axi_interconnect_0_WREADY = M01_AXI_wready;\n  assign m02_couplers_to_axi_interconnect_0_ARREADY = M02_AXI_arready;\n  assign m02_couplers_to_axi_interconnect_0_AWREADY = M02_AXI_awready;\n  assign m02_couplers_to_axi_interconnect_0_BID = M02_AXI_bid[6:0];\n  assign m02_couplers_to_axi_interconnect_0_BRESP = M02_AXI_bresp[1:0];\n  assign m02_couplers_to_axi_interconnect_0_BVALID = M02_AXI_bvalid;\n  assign m02_couplers_to_axi_interconnect_0_RDATA = M02_AXI_rdata[511:0];\n  assign m02_couplers_to_axi_interconnect_0_RID = M02_AXI_rid[6:0];\n  assign m02_couplers_to_axi_interconnect_0_RLAST = M02_AXI_rlast;\n  assign m02_couplers_to_axi_interconnect_0_RRESP = M02_AXI_rresp[1:0];\n  assign m02_couplers_to_axi_interconnect_0_RVALID = M02_AXI_rvalid;\n  assign m02_couplers_to_axi_interconnect_0_WREADY = M02_AXI_wready;\n  assign m03_couplers_to_axi_interconnect_0_ARREADY = M03_AXI_arready;\n  assign m03_couplers_to_axi_interconnect_0_AWREADY = M03_AXI_awready;\n  assign m03_couplers_to_axi_interconnect_0_BID = M03_AXI_bid[6:0];\n  assign m03_couplers_to_axi_interconnect_0_BRESP = M03_AXI_bresp[1:0];\n  assign m03_couplers_to_axi_interconnect_0_BVALID = M03_AXI_bvalid;\n  assign m03_couplers_to_axi_interconnect_0_RDATA = M03_AXI_rdata[511:0];\n  assign m03_couplers_to_axi_interconnect_0_RID = M03_AXI_rid[6:0];\n  assign m03_couplers_to_axi_interconnect_0_RLAST = M03_AXI_rlast;\n  assign m03_couplers_to_axi_interconnect_0_RRESP = M03_AXI_rresp[1:0];\n  assign m03_couplers_to_axi_interconnect_0_RVALID = M03_AXI_rvalid;\n  assign m03_couplers_to_axi_interconnect_0_WREADY = M03_AXI_wready;\n  m00_couplers_imp_1QBJ6U2 m00_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m00_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m00_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m00_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m00_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m00_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m00_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m00_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m00_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m00_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m00_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m00_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m00_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m00_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m00_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m00_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m00_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m00_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m00_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m00_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m00_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m00_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m00_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m00_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m00_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m00_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m00_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m00_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m00_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m00_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m00_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m00_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m00_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m00_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m00_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m00_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m00_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m00_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m00_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m00_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m00_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m00_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m00_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m00_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m00_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m00_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m00_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m00_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m00_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m00_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m00_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m00_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m00_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m00_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m00_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m00_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m00_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m00_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m00_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m00_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m00_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m00_couplers_BID),\n        .S_AXI_bready(xbar_to_m00_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m00_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m00_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m00_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m00_couplers_RID),\n        .S_AXI_rlast(xbar_to_m00_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m00_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m00_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m00_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m00_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m00_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m00_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m00_couplers_WVALID));\n  m01_couplers_imp_10IMR9A m01_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m01_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m01_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m01_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m01_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m01_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m01_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m01_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m01_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m01_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m01_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m01_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m01_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m01_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m01_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m01_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m01_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m01_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m01_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m01_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m01_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m01_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m01_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m01_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m01_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m01_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m01_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m01_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m01_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m01_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m01_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m01_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m01_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m01_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m01_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m01_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m01_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m01_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m01_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m01_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m01_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m01_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m01_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m01_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m01_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m01_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m01_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m01_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m01_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m01_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m01_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m01_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m01_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m01_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m01_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m01_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m01_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m01_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m01_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m01_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m01_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m01_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m01_couplers_BID),\n        .S_AXI_bready(xbar_to_m01_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m01_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m01_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m01_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m01_couplers_RID),\n        .S_AXI_rlast(xbar_to_m01_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m01_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m01_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m01_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m01_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m01_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m01_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m01_couplers_WVALID));\n  m02_couplers_imp_APDUS2 m02_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m02_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m02_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m02_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m02_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m02_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m02_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m02_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m02_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m02_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m02_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m02_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m02_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m02_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m02_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m02_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m02_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m02_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m02_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m02_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m02_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m02_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m02_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m02_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m02_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m02_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m02_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m02_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m02_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m02_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m02_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m02_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m02_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m02_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m02_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m02_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m02_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m02_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m02_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m02_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m02_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m02_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m02_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m02_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m02_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m02_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m02_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m02_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m02_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m02_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m02_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m02_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m02_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m02_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m02_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m02_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m02_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m02_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m02_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m02_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m02_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m02_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m02_couplers_BID),\n        .S_AXI_bready(xbar_to_m02_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m02_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m02_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m02_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m02_couplers_RID),\n        .S_AXI_rlast(xbar_to_m02_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m02_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m02_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m02_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m02_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m02_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m02_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m02_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m02_couplers_WVALID));\n  m03_couplers_imp_JAYOMU m03_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m03_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m03_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m03_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m03_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m03_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m03_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m03_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m03_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m03_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m03_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m03_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m03_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m03_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m03_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m03_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m03_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m03_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m03_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m03_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m03_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m03_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m03_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m03_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m03_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m03_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m03_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m03_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m03_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m03_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m03_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m03_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m03_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m03_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m03_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m03_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m03_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m03_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m03_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m03_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m03_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m03_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m03_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m03_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m03_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m03_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m03_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m03_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m03_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m03_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m03_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m03_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m03_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m03_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m03_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m03_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m03_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m03_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m03_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m03_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m03_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m03_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m03_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m03_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m03_couplers_BID),\n        .S_AXI_bready(xbar_to_m03_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m03_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m03_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m03_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m03_couplers_RID),\n        .S_AXI_rlast(xbar_to_m03_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m03_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m03_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m03_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m03_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m03_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m03_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m03_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m03_couplers_WVALID));\n  s00_couplers_imp_QICM5G s00_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(s00_couplers_to_xbar_ARADDR),\n        .M_AXI_arburst(s00_couplers_to_xbar_ARBURST),\n        .M_AXI_arcache(s00_couplers_to_xbar_ARCACHE),\n        .M_AXI_arid(s00_couplers_to_xbar_ARID),\n        .M_AXI_arlen(s00_couplers_to_xbar_ARLEN),\n        .M_AXI_arlock(s00_couplers_to_xbar_ARLOCK),\n        .M_AXI_arprot(s00_couplers_to_xbar_ARPROT),\n        .M_AXI_arqos(s00_couplers_to_xbar_ARQOS),\n        .M_AXI_arready(s00_couplers_to_xbar_ARREADY),\n        .M_AXI_arsize(s00_couplers_to_xbar_ARSIZE),\n        .M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),\n        .M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),\n        .M_AXI_awburst(s00_couplers_to_xbar_AWBURST),\n        .M_AXI_awcache(s00_couplers_to_xbar_AWCACHE),\n        .M_AXI_awid(s00_couplers_to_xbar_AWID),\n        .M_AXI_awlen(s00_couplers_to_xbar_AWLEN),\n        .M_AXI_awlock(s00_couplers_to_xbar_AWLOCK),\n        .M_AXI_awprot(s00_couplers_to_xbar_AWPROT),\n        .M_AXI_awqos(s00_couplers_to_xbar_AWQOS),\n        .M_AXI_awready(s00_couplers_to_xbar_AWREADY),\n        .M_AXI_awsize(s00_couplers_to_xbar_AWSIZE),\n        .M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),\n        .M_AXI_bid(s00_couplers_to_xbar_BID),\n        .M_AXI_bready(s00_couplers_to_xbar_BREADY),\n        .M_AXI_bresp(s00_couplers_to_xbar_BRESP),\n        .M_AXI_bvalid(s00_couplers_to_xbar_BVALID),\n        .M_AXI_rdata(s00_couplers_to_xbar_RDATA),\n        .M_AXI_rid(s00_couplers_to_xbar_RID),\n        .M_AXI_rlast(s00_couplers_to_xbar_RLAST),\n        .M_AXI_rready(s00_couplers_to_xbar_RREADY),\n        .M_AXI_rresp(s00_couplers_to_xbar_RRESP),\n        .M_AXI_rvalid(s00_couplers_to_xbar_RVALID),\n        .M_AXI_wdata(s00_couplers_to_xbar_WDATA),\n        .M_AXI_wlast(s00_couplers_to_xbar_WLAST),\n        .M_AXI_wready(s00_couplers_to_xbar_WREADY),\n        .M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),\n        .M_AXI_wvalid(s00_couplers_to_xbar_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(axi_interconnect_0_to_s00_couplers_ARADDR),\n        .S_AXI_arburst(axi_interconnect_0_to_s00_couplers_ARBURST),\n        .S_AXI_arcache(axi_interconnect_0_to_s00_couplers_ARCACHE),\n        .S_AXI_arid(axi_interconnect_0_to_s00_couplers_ARID),\n        .S_AXI_arlen(axi_interconnect_0_to_s00_couplers_ARLEN),\n        .S_AXI_arlock(axi_interconnect_0_to_s00_couplers_ARLOCK),\n        .S_AXI_arprot(axi_interconnect_0_to_s00_couplers_ARPROT),\n        .S_AXI_arqos(axi_interconnect_0_to_s00_couplers_ARQOS),\n        .S_AXI_arready(axi_interconnect_0_to_s00_couplers_ARREADY),\n        .S_AXI_arregion(axi_interconnect_0_to_s00_couplers_ARREGION),\n        .S_AXI_arsize(axi_interconnect_0_to_s00_couplers_ARSIZE),\n        .S_AXI_arvalid(axi_interconnect_0_to_s00_couplers_ARVALID),\n        .S_AXI_awaddr(axi_interconnect_0_to_s00_couplers_AWADDR),\n        .S_AXI_awburst(axi_interconnect_0_to_s00_couplers_AWBURST),\n        .S_AXI_awcache(axi_interconnect_0_to_s00_couplers_AWCACHE),\n        .S_AXI_awid(axi_interconnect_0_to_s00_couplers_AWID),\n        .S_AXI_awlen(axi_interconnect_0_to_s00_couplers_AWLEN),\n        .S_AXI_awlock(axi_interconnect_0_to_s00_couplers_AWLOCK),\n        .S_AXI_awprot(axi_interconnect_0_to_s00_couplers_AWPROT),\n        .S_AXI_awqos(axi_interconnect_0_to_s00_couplers_AWQOS),\n        .S_AXI_awready(axi_interconnect_0_to_s00_couplers_AWREADY),\n        .S_AXI_awregion(axi_interconnect_0_to_s00_couplers_AWREGION),\n        .S_AXI_awsize(axi_interconnect_0_to_s00_couplers_AWSIZE),\n        .S_AXI_awvalid(axi_interconnect_0_to_s00_couplers_AWVALID),\n        .S_AXI_bid(axi_interconnect_0_to_s00_couplers_BID),\n        .S_AXI_bready(axi_interconnect_0_to_s00_couplers_BREADY),\n        .S_AXI_bresp(axi_interconnect_0_to_s00_couplers_BRESP),\n        .S_AXI_bvalid(axi_interconnect_0_to_s00_couplers_BVALID),\n        .S_AXI_rdata(axi_interconnect_0_to_s00_couplers_RDATA),\n        .S_AXI_rid(axi_interconnect_0_to_s00_couplers_RID),\n        .S_AXI_rlast(axi_interconnect_0_to_s00_couplers_RLAST),\n        .S_AXI_rready(axi_interconnect_0_to_s00_couplers_RREADY),\n        .S_AXI_rresp(axi_interconnect_0_to_s00_couplers_RRESP),\n        .S_AXI_rvalid(axi_interconnect_0_to_s00_couplers_RVALID),\n        .S_AXI_wdata(axi_interconnect_0_to_s00_couplers_WDATA),\n        .S_AXI_wlast(axi_interconnect_0_to_s00_couplers_WLAST),\n        .S_AXI_wready(axi_interconnect_0_to_s00_couplers_WREADY),\n        .S_AXI_wstrb(axi_interconnect_0_to_s00_couplers_WSTRB),\n        .S_AXI_wvalid(axi_interconnect_0_to_s00_couplers_WVALID));\n  s01_couplers_imp_GSTXQ8 s01_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(s01_couplers_to_xbar_ARADDR),\n        .M_AXI_arburst(s01_couplers_to_xbar_ARBURST),\n        .M_AXI_arcache(s01_couplers_to_xbar_ARCACHE),\n        .M_AXI_arid(s01_couplers_to_xbar_ARID),\n        .M_AXI_arlen(s01_couplers_to_xbar_ARLEN),\n        .M_AXI_arlock(s01_couplers_to_xbar_ARLOCK),\n        .M_AXI_arprot(s01_couplers_to_xbar_ARPROT),\n        .M_AXI_arqos(s01_couplers_to_xbar_ARQOS),\n        .M_AXI_arready(s01_couplers_to_xbar_ARREADY),\n        .M_AXI_arsize(s01_couplers_to_xbar_ARSIZE),\n        .M_AXI_arvalid(s01_couplers_to_xbar_ARVALID),\n        .M_AXI_awaddr(s01_couplers_to_xbar_AWADDR),\n        .M_AXI_awburst(s01_couplers_to_xbar_AWBURST),\n        .M_AXI_awcache(s01_couplers_to_xbar_AWCACHE),\n        .M_AXI_awid(s01_couplers_to_xbar_AWID),\n        .M_AXI_awlen(s01_couplers_to_xbar_AWLEN),\n        .M_AXI_awlock(s01_couplers_to_xbar_AWLOCK),\n        .M_AXI_awprot(s01_couplers_to_xbar_AWPROT),\n        .M_AXI_awqos(s01_couplers_to_xbar_AWQOS),\n        .M_AXI_awready(s01_couplers_to_xbar_AWREADY),\n        .M_AXI_awsize(s01_couplers_to_xbar_AWSIZE),\n        .M_AXI_awvalid(s01_couplers_to_xbar_AWVALID),\n        .M_AXI_bid(s01_couplers_to_xbar_BID),\n        .M_AXI_bready(s01_couplers_to_xbar_BREADY),\n        .M_AXI_bresp(s01_couplers_to_xbar_BRESP),\n        .M_AXI_bvalid(s01_couplers_to_xbar_BVALID),\n        .M_AXI_rdata(s01_couplers_to_xbar_RDATA),\n        .M_AXI_rid(s01_couplers_to_xbar_RID),\n        .M_AXI_rlast(s01_couplers_to_xbar_RLAST),\n        .M_AXI_rready(s01_couplers_to_xbar_RREADY),\n        .M_AXI_rresp(s01_couplers_to_xbar_RRESP),\n        .M_AXI_rvalid(s01_couplers_to_xbar_RVALID),\n        .M_AXI_wdata(s01_couplers_to_xbar_WDATA),\n        .M_AXI_wlast(s01_couplers_to_xbar_WLAST),\n        .M_AXI_wready(s01_couplers_to_xbar_WREADY),\n        .M_AXI_wstrb(s01_couplers_to_xbar_WSTRB),\n        .M_AXI_wvalid(s01_couplers_to_xbar_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(axi_interconnect_0_to_s01_couplers_ARADDR),\n        .S_AXI_arburst(axi_interconnect_0_to_s01_couplers_ARBURST),\n        .S_AXI_arcache(axi_interconnect_0_to_s01_couplers_ARCACHE),\n        .S_AXI_arid(axi_interconnect_0_to_s01_couplers_ARID),\n        .S_AXI_arlen(axi_interconnect_0_to_s01_couplers_ARLEN),\n        .S_AXI_arlock(axi_interconnect_0_to_s01_couplers_ARLOCK),\n        .S_AXI_arprot(axi_interconnect_0_to_s01_couplers_ARPROT),\n        .S_AXI_arqos(axi_interconnect_0_to_s01_couplers_ARQOS),\n        .S_AXI_arready(axi_interconnect_0_to_s01_couplers_ARREADY),\n        .S_AXI_arregion(axi_interconnect_0_to_s01_couplers_ARREGION),\n        .S_AXI_arsize(axi_interconnect_0_to_s01_couplers_ARSIZE),\n        .S_AXI_arvalid(axi_interconnect_0_to_s01_couplers_ARVALID),\n        .S_AXI_awaddr(axi_interconnect_0_to_s01_couplers_AWADDR),\n        .S_AXI_awburst(axi_interconnect_0_to_s01_couplers_AWBURST),\n        .S_AXI_awcache(axi_interconnect_0_to_s01_couplers_AWCACHE),\n        .S_AXI_awid(axi_interconnect_0_to_s01_couplers_AWID),\n        .S_AXI_awlen(axi_interconnect_0_to_s01_couplers_AWLEN),\n        .S_AXI_awlock(axi_interconnect_0_to_s01_couplers_AWLOCK),\n        .S_AXI_awprot(axi_interconnect_0_to_s01_couplers_AWPROT),\n        .S_AXI_awqos(axi_interconnect_0_to_s01_couplers_AWQOS),\n        .S_AXI_awready(axi_interconnect_0_to_s01_couplers_AWREADY),\n        .S_AXI_awregion(axi_interconnect_0_to_s01_couplers_AWREGION),\n        .S_AXI_awsize(axi_interconnect_0_to_s01_couplers_AWSIZE),\n        .S_AXI_awvalid(axi_interconnect_0_to_s01_couplers_AWVALID),\n        .S_AXI_bid(axi_interconnect_0_to_s01_couplers_BID),\n        .S_AXI_bready(axi_interconnect_0_to_s01_couplers_BREADY),\n        .S_AXI_bresp(axi_interconnect_0_to_s01_couplers_BRESP),\n        .S_AXI_bvalid(axi_interconnect_0_to_s01_couplers_BVALID),\n        .S_AXI_rdata(axi_interconnect_0_to_s01_couplers_RDATA),\n        .S_AXI_rid(axi_interconnect_0_to_s01_couplers_RID),\n        .S_AXI_rlast(axi_interconnect_0_to_s01_couplers_RLAST),\n        .S_AXI_rready(axi_interconnect_0_to_s01_couplers_RREADY),\n        .S_AXI_rresp(axi_interconnect_0_to_s01_couplers_RRESP),\n        .S_AXI_rvalid(axi_interconnect_0_to_s01_couplers_RVALID),\n        .S_AXI_wdata(axi_interconnect_0_to_s01_couplers_WDATA),\n        .S_AXI_wlast(axi_interconnect_0_to_s01_couplers_WLAST),\n        .S_AXI_wready(axi_interconnect_0_to_s01_couplers_WREADY),\n        .S_AXI_wstrb(axi_interconnect_0_to_s01_couplers_WSTRB),\n        .S_AXI_wvalid(axi_interconnect_0_to_s01_couplers_WVALID));\n  cl_axi_interconnect_xbar_0 xbar\n       (.aclk(axi_interconnect_0_ACLK_net),\n        .aresetn(axi_interconnect_0_ARESETN_net),\n        .m_axi_araddr({xbar_to_m03_couplers_ARADDR,xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),\n        .m_axi_arburst({xbar_to_m03_couplers_ARBURST,xbar_to_m02_couplers_ARBURST,xbar_to_m01_couplers_ARBURST,xbar_to_m00_couplers_ARBURST}),\n        .m_axi_arcache({xbar_to_m03_couplers_ARCACHE,xbar_to_m02_couplers_ARCACHE,xbar_to_m01_couplers_ARCACHE,xbar_to_m00_couplers_ARCACHE}),\n        .m_axi_arid({xbar_to_m03_couplers_ARID,xbar_to_m02_couplers_ARID,xbar_to_m01_couplers_ARID,xbar_to_m00_couplers_ARID}),\n        .m_axi_arlen({xbar_to_m03_couplers_ARLEN,xbar_to_m02_couplers_ARLEN,xbar_to_m01_couplers_ARLEN,xbar_to_m00_couplers_ARLEN}),\n        .m_axi_arlock({xbar_to_m03_couplers_ARLOCK,xbar_to_m02_couplers_ARLOCK,xbar_to_m01_couplers_ARLOCK,xbar_to_m00_couplers_ARLOCK}),\n        .m_axi_arprot({xbar_to_m03_couplers_ARPROT,xbar_to_m02_couplers_ARPROT,xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}),\n        .m_axi_arqos({xbar_to_m03_couplers_ARQOS,xbar_to_m02_couplers_ARQOS,xbar_to_m01_couplers_ARQOS,xbar_to_m00_couplers_ARQOS}),\n        .m_axi_arready({xbar_to_m03_couplers_ARREADY,xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),\n        .m_axi_arregion({xbar_to_m03_couplers_ARREGION,xbar_to_m02_couplers_ARREGION,xbar_to_m01_couplers_ARREGION,xbar_to_m00_couplers_ARREGION}),\n        .m_axi_arsize({xbar_to_m03_couplers_ARSIZE,xbar_to_m02_couplers_ARSIZE,xbar_to_m01_couplers_ARSIZE,xbar_to_m00_couplers_ARSIZE}),\n        .m_axi_arvalid({xbar_to_m03_couplers_ARVALID,xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),\n        .m_axi_awaddr({xbar_to_m03_couplers_AWADDR,xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),\n        .m_axi_awburst({xbar_to_m03_couplers_AWBURST,xbar_to_m02_couplers_AWBURST,xbar_to_m01_couplers_AWBURST,xbar_to_m00_couplers_AWBURST}),\n        .m_axi_awcache({xbar_to_m03_couplers_AWCACHE,xbar_to_m02_couplers_AWCACHE,xbar_to_m01_couplers_AWCACHE,xbar_to_m00_couplers_AWCACHE}),\n        .m_axi_awid({xbar_to_m03_couplers_AWID,xbar_to_m02_couplers_AWID,xbar_to_m01_couplers_AWID,xbar_to_m00_couplers_AWID}),\n        .m_axi_awlen({xbar_to_m03_couplers_AWLEN,xbar_to_m02_couplers_AWLEN,xbar_to_m01_couplers_AWLEN,xbar_to_m00_couplers_AWLEN}),\n        .m_axi_awlock({xbar_to_m03_couplers_AWLOCK,xbar_to_m02_couplers_AWLOCK,xbar_to_m01_couplers_AWLOCK,xbar_to_m00_couplers_AWLOCK}),\n        .m_axi_awprot({xbar_to_m03_couplers_AWPROT,xbar_to_m02_couplers_AWPROT,xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}),\n        .m_axi_awqos({xbar_to_m03_couplers_AWQOS,xbar_to_m02_couplers_AWQOS,xbar_to_m01_couplers_AWQOS,xbar_to_m00_couplers_AWQOS}),\n        .m_axi_awready({xbar_to_m03_couplers_AWREADY,xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),\n        .m_axi_awregion({xbar_to_m03_couplers_AWREGION,xbar_to_m02_couplers_AWREGION,xbar_to_m01_couplers_AWREGION,xbar_to_m00_couplers_AWREGION}),\n        .m_axi_awsize({xbar_to_m03_couplers_AWSIZE,xbar_to_m02_couplers_AWSIZE,xbar_to_m01_couplers_AWSIZE,xbar_to_m00_couplers_AWSIZE}),\n        .m_axi_awvalid({xbar_to_m03_couplers_AWVALID,xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),\n        .m_axi_bid({xbar_to_m03_couplers_BID,xbar_to_m02_couplers_BID,xbar_to_m01_couplers_BID,xbar_to_m00_couplers_BID}),\n        .m_axi_bready({xbar_to_m03_couplers_BREADY,xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),\n        .m_axi_bresp({xbar_to_m03_couplers_BRESP,xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),\n        .m_axi_bvalid({xbar_to_m03_couplers_BVALID,xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),\n        .m_axi_rdata({xbar_to_m03_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),\n        .m_axi_rid({xbar_to_m03_couplers_RID,xbar_to_m02_couplers_RID,xbar_to_m01_couplers_RID,xbar_to_m00_couplers_RID}),\n        .m_axi_rlast({xbar_to_m03_couplers_RLAST,xbar_to_m02_couplers_RLAST,xbar_to_m01_couplers_RLAST,xbar_to_m00_couplers_RLAST}),\n        .m_axi_rready({xbar_to_m03_couplers_RREADY,xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),\n        .m_axi_rresp({xbar_to_m03_couplers_RRESP,xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),\n        .m_axi_rvalid({xbar_to_m03_couplers_RVALID,xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),\n        .m_axi_wdata({xbar_to_m03_couplers_WDATA,xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),\n        .m_axi_wlast({xbar_to_m03_couplers_WLAST,xbar_to_m02_couplers_WLAST,xbar_to_m01_couplers_WLAST,xbar_to_m00_couplers_WLAST}),\n        .m_axi_wready({xbar_to_m03_couplers_WREADY,xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),\n        .m_axi_wstrb({xbar_to_m03_couplers_WSTRB,xbar_to_m02_couplers_WSTRB,xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),\n        .m_axi_wvalid({xbar_to_m03_couplers_WVALID,xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),\n        .s_axi_araddr({s01_couplers_to_xbar_ARADDR,s00_couplers_to_xbar_ARADDR}),\n        .s_axi_arburst({s01_couplers_to_xbar_ARBURST,s00_couplers_to_xbar_ARBURST}),\n        .s_axi_arcache({s01_couplers_to_xbar_ARCACHE,s00_couplers_to_xbar_ARCACHE}),\n        .s_axi_arid({1'b0,s01_couplers_to_xbar_ARID,1'b0,s00_couplers_to_xbar_ARID}),\n        .s_axi_arlen({s01_couplers_to_xbar_ARLEN,s00_couplers_to_xbar_ARLEN}),\n        .s_axi_arlock({s01_couplers_to_xbar_ARLOCK,s00_couplers_to_xbar_ARLOCK}),\n        .s_axi_arprot({s01_couplers_to_xbar_ARPROT,s00_couplers_to_xbar_ARPROT}),\n        .s_axi_arqos({s01_couplers_to_xbar_ARQOS,s00_couplers_to_xbar_ARQOS}),\n        .s_axi_arready({s01_couplers_to_xbar_ARREADY,s00_couplers_to_xbar_ARREADY}),\n        .s_axi_arsize({s01_couplers_to_xbar_ARSIZE,s00_couplers_to_xbar_ARSIZE}),\n        .s_axi_arvalid({s01_couplers_to_xbar_ARVALID,s00_couplers_to_xbar_ARVALID}),\n        .s_axi_awaddr({s01_couplers_to_xbar_AWADDR,s00_couplers_to_xbar_AWADDR}),\n        .s_axi_awburst({s01_couplers_to_xbar_AWBURST,s00_couplers_to_xbar_AWBURST}),\n        .s_axi_awcache({s01_couplers_to_xbar_AWCACHE,s00_couplers_to_xbar_AWCACHE}),\n        .s_axi_awid({1'b0,s01_couplers_to_xbar_AWID,1'b0,s00_couplers_to_xbar_AWID}),\n        .s_axi_awlen({s01_couplers_to_xbar_AWLEN,s00_couplers_to_xbar_AWLEN}),\n        .s_axi_awlock({s01_couplers_to_xbar_AWLOCK,s00_couplers_to_xbar_AWLOCK}),\n        .s_axi_awprot({s01_couplers_to_xbar_AWPROT,s00_couplers_to_xbar_AWPROT}),\n        .s_axi_awqos({s01_couplers_to_xbar_AWQOS,s00_couplers_to_xbar_AWQOS}),\n        .s_axi_awready({s01_couplers_to_xbar_AWREADY,s00_couplers_to_xbar_AWREADY}),\n        .s_axi_awsize({s01_couplers_to_xbar_AWSIZE,s00_couplers_to_xbar_AWSIZE}),\n        .s_axi_awvalid({s01_couplers_to_xbar_AWVALID,s00_couplers_to_xbar_AWVALID}),\n        .s_axi_bid({s01_couplers_to_xbar_BID,s00_couplers_to_xbar_BID}),\n        .s_axi_bready({s01_couplers_to_xbar_BREADY,s00_couplers_to_xbar_BREADY}),\n        .s_axi_bresp({s01_couplers_to_xbar_BRESP,s00_couplers_to_xbar_BRESP}),\n        .s_axi_bvalid({s01_couplers_to_xbar_BVALID,s00_couplers_to_xbar_BVALID}),\n        .s_axi_rdata({s01_couplers_to_xbar_RDATA,s00_couplers_to_xbar_RDATA}),\n        .s_axi_rid({s01_couplers_to_xbar_RID,s00_couplers_to_xbar_RID}),\n        .s_axi_rlast({s01_couplers_to_xbar_RLAST,s00_couplers_to_xbar_RLAST}),\n        .s_axi_rready({s01_couplers_to_xbar_RREADY,s00_couplers_to_xbar_RREADY}),\n        .s_axi_rresp({s01_couplers_to_xbar_RRESP,s00_couplers_to_xbar_RRESP}),\n        .s_axi_rvalid({s01_couplers_to_xbar_RVALID,s00_couplers_to_xbar_RVALID}),\n        .s_axi_wdata({s01_couplers_to_xbar_WDATA,s00_couplers_to_xbar_WDATA}),\n        .s_axi_wlast({s01_couplers_to_xbar_WLAST,s00_couplers_to_xbar_WLAST}),\n        .s_axi_wready({s01_couplers_to_xbar_WREADY,s00_couplers_to_xbar_WREADY}),\n        .s_axi_wstrb({s01_couplers_to_xbar_WSTRB,s00_couplers_to_xbar_WSTRB}),\n        .s_axi_wvalid({s01_couplers_to_xbar_WVALID,s00_couplers_to_xbar_WVALID}));\nendmodule\n\nmodule m00_couplers_imp_1QBJ6U2\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m00_couplers_to_m00_regslice_ARADDR;\n  wire [1:0]m00_couplers_to_m00_regslice_ARBURST;\n  wire [3:0]m00_couplers_to_m00_regslice_ARCACHE;\n  wire [6:0]m00_couplers_to_m00_regslice_ARID;\n  wire [7:0]m00_couplers_to_m00_regslice_ARLEN;\n  wire [0:0]m00_couplers_to_m00_regslice_ARLOCK;\n  wire [2:0]m00_couplers_to_m00_regslice_ARPROT;\n  wire [3:0]m00_couplers_to_m00_regslice_ARQOS;\n  wire m00_couplers_to_m00_regslice_ARREADY;\n  wire [3:0]m00_couplers_to_m00_regslice_ARREGION;\n  wire [2:0]m00_couplers_to_m00_regslice_ARSIZE;\n  wire m00_couplers_to_m00_regslice_ARVALID;\n  wire [63:0]m00_couplers_to_m00_regslice_AWADDR;\n  wire [1:0]m00_couplers_to_m00_regslice_AWBURST;\n  wire [3:0]m00_couplers_to_m00_regslice_AWCACHE;\n  wire [6:0]m00_couplers_to_m00_regslice_AWID;\n  wire [7:0]m00_couplers_to_m00_regslice_AWLEN;\n  wire [0:0]m00_couplers_to_m00_regslice_AWLOCK;\n  wire [2:0]m00_couplers_to_m00_regslice_AWPROT;\n  wire [3:0]m00_couplers_to_m00_regslice_AWQOS;\n  wire m00_couplers_to_m00_regslice_AWREADY;\n  wire [3:0]m00_couplers_to_m00_regslice_AWREGION;\n  wire [2:0]m00_couplers_to_m00_regslice_AWSIZE;\n  wire m00_couplers_to_m00_regslice_AWVALID;\n  wire [6:0]m00_couplers_to_m00_regslice_BID;\n  wire m00_couplers_to_m00_regslice_BREADY;\n  wire [1:0]m00_couplers_to_m00_regslice_BRESP;\n  wire m00_couplers_to_m00_regslice_BVALID;\n  wire [511:0]m00_couplers_to_m00_regslice_RDATA;\n  wire [6:0]m00_couplers_to_m00_regslice_RID;\n  wire m00_couplers_to_m00_regslice_RLAST;\n  wire m00_couplers_to_m00_regslice_RREADY;\n  wire [1:0]m00_couplers_to_m00_regslice_RRESP;\n  wire m00_couplers_to_m00_regslice_RVALID;\n  wire [511:0]m00_couplers_to_m00_regslice_WDATA;\n  wire m00_couplers_to_m00_regslice_WLAST;\n  wire m00_couplers_to_m00_regslice_WREADY;\n  wire [63:0]m00_couplers_to_m00_regslice_WSTRB;\n  wire m00_couplers_to_m00_regslice_WVALID;\n  wire [63:0]m00_regslice_to_m00_couplers_ARADDR;\n  wire [1:0]m00_regslice_to_m00_couplers_ARBURST;\n  wire [3:0]m00_regslice_to_m00_couplers_ARCACHE;\n  wire [6:0]m00_regslice_to_m00_couplers_ARID;\n  wire [7:0]m00_regslice_to_m00_couplers_ARLEN;\n  wire [0:0]m00_regslice_to_m00_couplers_ARLOCK;\n  wire [2:0]m00_regslice_to_m00_couplers_ARPROT;\n  wire [3:0]m00_regslice_to_m00_couplers_ARQOS;\n  wire m00_regslice_to_m00_couplers_ARREADY;\n  wire [3:0]m00_regslice_to_m00_couplers_ARREGION;\n  wire [2:0]m00_regslice_to_m00_couplers_ARSIZE;\n  wire m00_regslice_to_m00_couplers_ARVALID;\n  wire [63:0]m00_regslice_to_m00_couplers_AWADDR;\n  wire [1:0]m00_regslice_to_m00_couplers_AWBURST;\n  wire [3:0]m00_regslice_to_m00_couplers_AWCACHE;\n  wire [6:0]m00_regslice_to_m00_couplers_AWID;\n  wire [7:0]m00_regslice_to_m00_couplers_AWLEN;\n  wire [0:0]m00_regslice_to_m00_couplers_AWLOCK;\n  wire [2:0]m00_regslice_to_m00_couplers_AWPROT;\n  wire [3:0]m00_regslice_to_m00_couplers_AWQOS;\n  wire m00_regslice_to_m00_couplers_AWREADY;\n  wire [3:0]m00_regslice_to_m00_couplers_AWREGION;\n  wire [2:0]m00_regslice_to_m00_couplers_AWSIZE;\n  wire m00_regslice_to_m00_couplers_AWVALID;\n  wire [6:0]m00_regslice_to_m00_couplers_BID;\n  wire m00_regslice_to_m00_couplers_BREADY;\n  wire [1:0]m00_regslice_to_m00_couplers_BRESP;\n  wire m00_regslice_to_m00_couplers_BVALID;\n  wire [511:0]m00_regslice_to_m00_couplers_RDATA;\n  wire [6:0]m00_regslice_to_m00_couplers_RID;\n  wire m00_regslice_to_m00_couplers_RLAST;\n  wire m00_regslice_to_m00_couplers_RREADY;\n  wire [1:0]m00_regslice_to_m00_couplers_RRESP;\n  wire m00_regslice_to_m00_couplers_RVALID;\n  wire [511:0]m00_regslice_to_m00_couplers_WDATA;\n  wire m00_regslice_to_m00_couplers_WLAST;\n  wire m00_regslice_to_m00_couplers_WREADY;\n  wire [63:0]m00_regslice_to_m00_couplers_WSTRB;\n  wire m00_regslice_to_m00_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m00_regslice_to_m00_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m00_regslice_to_m00_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m00_regslice_to_m00_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m00_regslice_to_m00_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m00_regslice_to_m00_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m00_regslice_to_m00_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m00_regslice_to_m00_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m00_regslice_to_m00_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m00_regslice_to_m00_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m00_regslice_to_m00_couplers_ARSIZE;\n  assign M_AXI_arvalid = m00_regslice_to_m00_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m00_regslice_to_m00_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m00_regslice_to_m00_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m00_regslice_to_m00_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m00_regslice_to_m00_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m00_regslice_to_m00_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m00_regslice_to_m00_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m00_regslice_to_m00_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m00_regslice_to_m00_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m00_regslice_to_m00_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m00_regslice_to_m00_couplers_AWSIZE;\n  assign M_AXI_awvalid = m00_regslice_to_m00_couplers_AWVALID;\n  assign M_AXI_bready = m00_regslice_to_m00_couplers_BREADY;\n  assign M_AXI_rready = m00_regslice_to_m00_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m00_regslice_to_m00_couplers_WDATA;\n  assign M_AXI_wlast = m00_regslice_to_m00_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m00_regslice_to_m00_couplers_WSTRB;\n  assign M_AXI_wvalid = m00_regslice_to_m00_couplers_WVALID;\n  assign S_AXI_arready = m00_couplers_to_m00_regslice_ARREADY;\n  assign S_AXI_awready = m00_couplers_to_m00_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m00_couplers_to_m00_regslice_BID;\n  assign S_AXI_bresp[1:0] = m00_couplers_to_m00_regslice_BRESP;\n  assign S_AXI_bvalid = m00_couplers_to_m00_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m00_couplers_to_m00_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m00_couplers_to_m00_regslice_RID;\n  assign S_AXI_rlast = m00_couplers_to_m00_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m00_couplers_to_m00_regslice_RRESP;\n  assign S_AXI_rvalid = m00_couplers_to_m00_regslice_RVALID;\n  assign S_AXI_wready = m00_couplers_to_m00_regslice_WREADY;\n  assign m00_couplers_to_m00_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m00_couplers_to_m00_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m00_couplers_to_m00_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m00_couplers_to_m00_regslice_ARID = S_AXI_arid[6:0];\n  assign m00_couplers_to_m00_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m00_couplers_to_m00_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m00_couplers_to_m00_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m00_couplers_to_m00_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m00_couplers_to_m00_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m00_couplers_to_m00_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m00_couplers_to_m00_regslice_ARVALID = S_AXI_arvalid;\n  assign m00_couplers_to_m00_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m00_couplers_to_m00_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m00_couplers_to_m00_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m00_couplers_to_m00_regslice_AWID = S_AXI_awid[6:0];\n  assign m00_couplers_to_m00_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m00_couplers_to_m00_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m00_couplers_to_m00_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m00_couplers_to_m00_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m00_couplers_to_m00_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m00_couplers_to_m00_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m00_couplers_to_m00_regslice_AWVALID = S_AXI_awvalid;\n  assign m00_couplers_to_m00_regslice_BREADY = S_AXI_bready;\n  assign m00_couplers_to_m00_regslice_RREADY = S_AXI_rready;\n  assign m00_couplers_to_m00_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m00_couplers_to_m00_regslice_WLAST = S_AXI_wlast;\n  assign m00_couplers_to_m00_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m00_couplers_to_m00_regslice_WVALID = S_AXI_wvalid;\n  assign m00_regslice_to_m00_couplers_ARREADY = M_AXI_arready;\n  assign m00_regslice_to_m00_couplers_AWREADY = M_AXI_awready;\n  assign m00_regslice_to_m00_couplers_BID = M_AXI_bid[6:0];\n  assign m00_regslice_to_m00_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m00_regslice_to_m00_couplers_BVALID = M_AXI_bvalid;\n  assign m00_regslice_to_m00_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m00_regslice_to_m00_couplers_RID = M_AXI_rid[6:0];\n  assign m00_regslice_to_m00_couplers_RLAST = M_AXI_rlast;\n  assign m00_regslice_to_m00_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m00_regslice_to_m00_couplers_RVALID = M_AXI_rvalid;\n  assign m00_regslice_to_m00_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m00_regslice_0 m00_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m00_regslice_to_m00_couplers_ARADDR),\n        .m_axi_arburst(m00_regslice_to_m00_couplers_ARBURST),\n        .m_axi_arcache(m00_regslice_to_m00_couplers_ARCACHE),\n        .m_axi_arid(m00_regslice_to_m00_couplers_ARID),\n        .m_axi_arlen(m00_regslice_to_m00_couplers_ARLEN),\n        .m_axi_arlock(m00_regslice_to_m00_couplers_ARLOCK),\n        .m_axi_arprot(m00_regslice_to_m00_couplers_ARPROT),\n        .m_axi_arqos(m00_regslice_to_m00_couplers_ARQOS),\n        .m_axi_arready(m00_regslice_to_m00_couplers_ARREADY),\n        .m_axi_arregion(m00_regslice_to_m00_couplers_ARREGION),\n        .m_axi_arsize(m00_regslice_to_m00_couplers_ARSIZE),\n        .m_axi_arvalid(m00_regslice_to_m00_couplers_ARVALID),\n        .m_axi_awaddr(m00_regslice_to_m00_couplers_AWADDR),\n        .m_axi_awburst(m00_regslice_to_m00_couplers_AWBURST),\n        .m_axi_awcache(m00_regslice_to_m00_couplers_AWCACHE),\n        .m_axi_awid(m00_regslice_to_m00_couplers_AWID),\n        .m_axi_awlen(m00_regslice_to_m00_couplers_AWLEN),\n        .m_axi_awlock(m00_regslice_to_m00_couplers_AWLOCK),\n        .m_axi_awprot(m00_regslice_to_m00_couplers_AWPROT),\n        .m_axi_awqos(m00_regslice_to_m00_couplers_AWQOS),\n        .m_axi_awready(m00_regslice_to_m00_couplers_AWREADY),\n        .m_axi_awregion(m00_regslice_to_m00_couplers_AWREGION),\n        .m_axi_awsize(m00_regslice_to_m00_couplers_AWSIZE),\n        .m_axi_awvalid(m00_regslice_to_m00_couplers_AWVALID),\n        .m_axi_bid(m00_regslice_to_m00_couplers_BID),\n        .m_axi_bready(m00_regslice_to_m00_couplers_BREADY),\n        .m_axi_bresp(m00_regslice_to_m00_couplers_BRESP),\n        .m_axi_bvalid(m00_regslice_to_m00_couplers_BVALID),\n        .m_axi_rdata(m00_regslice_to_m00_couplers_RDATA),\n        .m_axi_rid(m00_regslice_to_m00_couplers_RID),\n        .m_axi_rlast(m00_regslice_to_m00_couplers_RLAST),\n        .m_axi_rready(m00_regslice_to_m00_couplers_RREADY),\n        .m_axi_rresp(m00_regslice_to_m00_couplers_RRESP),\n        .m_axi_rvalid(m00_regslice_to_m00_couplers_RVALID),\n        .m_axi_wdata(m00_regslice_to_m00_couplers_WDATA),\n        .m_axi_wlast(m00_regslice_to_m00_couplers_WLAST),\n        .m_axi_wready(m00_regslice_to_m00_couplers_WREADY),\n        .m_axi_wstrb(m00_regslice_to_m00_couplers_WSTRB),\n        .m_axi_wvalid(m00_regslice_to_m00_couplers_WVALID),\n        .s_axi_araddr(m00_couplers_to_m00_regslice_ARADDR),\n        .s_axi_arburst(m00_couplers_to_m00_regslice_ARBURST),\n        .s_axi_arcache(m00_couplers_to_m00_regslice_ARCACHE),\n        .s_axi_arid(m00_couplers_to_m00_regslice_ARID),\n        .s_axi_arlen(m00_couplers_to_m00_regslice_ARLEN),\n        .s_axi_arlock(m00_couplers_to_m00_regslice_ARLOCK),\n        .s_axi_arprot(m00_couplers_to_m00_regslice_ARPROT),\n        .s_axi_arqos(m00_couplers_to_m00_regslice_ARQOS),\n        .s_axi_arready(m00_couplers_to_m00_regslice_ARREADY),\n        .s_axi_arregion(m00_couplers_to_m00_regslice_ARREGION),\n        .s_axi_arsize(m00_couplers_to_m00_regslice_ARSIZE),\n        .s_axi_arvalid(m00_couplers_to_m00_regslice_ARVALID),\n        .s_axi_awaddr(m00_couplers_to_m00_regslice_AWADDR),\n        .s_axi_awburst(m00_couplers_to_m00_regslice_AWBURST),\n        .s_axi_awcache(m00_couplers_to_m00_regslice_AWCACHE),\n        .s_axi_awid(m00_couplers_to_m00_regslice_AWID),\n        .s_axi_awlen(m00_couplers_to_m00_regslice_AWLEN),\n        .s_axi_awlock(m00_couplers_to_m00_regslice_AWLOCK),\n        .s_axi_awprot(m00_couplers_to_m00_regslice_AWPROT),\n        .s_axi_awqos(m00_couplers_to_m00_regslice_AWQOS),\n        .s_axi_awready(m00_couplers_to_m00_regslice_AWREADY),\n        .s_axi_awregion(m00_couplers_to_m00_regslice_AWREGION),\n        .s_axi_awsize(m00_couplers_to_m00_regslice_AWSIZE),\n        .s_axi_awvalid(m00_couplers_to_m00_regslice_AWVALID),\n        .s_axi_bid(m00_couplers_to_m00_regslice_BID),\n        .s_axi_bready(m00_couplers_to_m00_regslice_BREADY),\n        .s_axi_bresp(m00_couplers_to_m00_regslice_BRESP),\n        .s_axi_bvalid(m00_couplers_to_m00_regslice_BVALID),\n        .s_axi_rdata(m00_couplers_to_m00_regslice_RDATA),\n        .s_axi_rid(m00_couplers_to_m00_regslice_RID),\n        .s_axi_rlast(m00_couplers_to_m00_regslice_RLAST),\n        .s_axi_rready(m00_couplers_to_m00_regslice_RREADY),\n        .s_axi_rresp(m00_couplers_to_m00_regslice_RRESP),\n        .s_axi_rvalid(m00_couplers_to_m00_regslice_RVALID),\n        .s_axi_wdata(m00_couplers_to_m00_regslice_WDATA),\n        .s_axi_wlast(m00_couplers_to_m00_regslice_WLAST),\n        .s_axi_wready(m00_couplers_to_m00_regslice_WREADY),\n        .s_axi_wstrb(m00_couplers_to_m00_regslice_WSTRB),\n        .s_axi_wvalid(m00_couplers_to_m00_regslice_WVALID));\nendmodule\n\nmodule m01_couplers_imp_10IMR9A\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m01_couplers_to_m01_regslice_ARADDR;\n  wire [1:0]m01_couplers_to_m01_regslice_ARBURST;\n  wire [3:0]m01_couplers_to_m01_regslice_ARCACHE;\n  wire [6:0]m01_couplers_to_m01_regslice_ARID;\n  wire [7:0]m01_couplers_to_m01_regslice_ARLEN;\n  wire [0:0]m01_couplers_to_m01_regslice_ARLOCK;\n  wire [2:0]m01_couplers_to_m01_regslice_ARPROT;\n  wire [3:0]m01_couplers_to_m01_regslice_ARQOS;\n  wire m01_couplers_to_m01_regslice_ARREADY;\n  wire [3:0]m01_couplers_to_m01_regslice_ARREGION;\n  wire [2:0]m01_couplers_to_m01_regslice_ARSIZE;\n  wire m01_couplers_to_m01_regslice_ARVALID;\n  wire [63:0]m01_couplers_to_m01_regslice_AWADDR;\n  wire [1:0]m01_couplers_to_m01_regslice_AWBURST;\n  wire [3:0]m01_couplers_to_m01_regslice_AWCACHE;\n  wire [6:0]m01_couplers_to_m01_regslice_AWID;\n  wire [7:0]m01_couplers_to_m01_regslice_AWLEN;\n  wire [0:0]m01_couplers_to_m01_regslice_AWLOCK;\n  wire [2:0]m01_couplers_to_m01_regslice_AWPROT;\n  wire [3:0]m01_couplers_to_m01_regslice_AWQOS;\n  wire m01_couplers_to_m01_regslice_AWREADY;\n  wire [3:0]m01_couplers_to_m01_regslice_AWREGION;\n  wire [2:0]m01_couplers_to_m01_regslice_AWSIZE;\n  wire m01_couplers_to_m01_regslice_AWVALID;\n  wire [6:0]m01_couplers_to_m01_regslice_BID;\n  wire m01_couplers_to_m01_regslice_BREADY;\n  wire [1:0]m01_couplers_to_m01_regslice_BRESP;\n  wire m01_couplers_to_m01_regslice_BVALID;\n  wire [511:0]m01_couplers_to_m01_regslice_RDATA;\n  wire [6:0]m01_couplers_to_m01_regslice_RID;\n  wire m01_couplers_to_m01_regslice_RLAST;\n  wire m01_couplers_to_m01_regslice_RREADY;\n  wire [1:0]m01_couplers_to_m01_regslice_RRESP;\n  wire m01_couplers_to_m01_regslice_RVALID;\n  wire [511:0]m01_couplers_to_m01_regslice_WDATA;\n  wire m01_couplers_to_m01_regslice_WLAST;\n  wire m01_couplers_to_m01_regslice_WREADY;\n  wire [63:0]m01_couplers_to_m01_regslice_WSTRB;\n  wire m01_couplers_to_m01_regslice_WVALID;\n  wire [63:0]m01_regslice_to_m01_couplers_ARADDR;\n  wire [1:0]m01_regslice_to_m01_couplers_ARBURST;\n  wire [3:0]m01_regslice_to_m01_couplers_ARCACHE;\n  wire [6:0]m01_regslice_to_m01_couplers_ARID;\n  wire [7:0]m01_regslice_to_m01_couplers_ARLEN;\n  wire [0:0]m01_regslice_to_m01_couplers_ARLOCK;\n  wire [2:0]m01_regslice_to_m01_couplers_ARPROT;\n  wire [3:0]m01_regslice_to_m01_couplers_ARQOS;\n  wire m01_regslice_to_m01_couplers_ARREADY;\n  wire [3:0]m01_regslice_to_m01_couplers_ARREGION;\n  wire [2:0]m01_regslice_to_m01_couplers_ARSIZE;\n  wire m01_regslice_to_m01_couplers_ARVALID;\n  wire [63:0]m01_regslice_to_m01_couplers_AWADDR;\n  wire [1:0]m01_regslice_to_m01_couplers_AWBURST;\n  wire [3:0]m01_regslice_to_m01_couplers_AWCACHE;\n  wire [6:0]m01_regslice_to_m01_couplers_AWID;\n  wire [7:0]m01_regslice_to_m01_couplers_AWLEN;\n  wire [0:0]m01_regslice_to_m01_couplers_AWLOCK;\n  wire [2:0]m01_regslice_to_m01_couplers_AWPROT;\n  wire [3:0]m01_regslice_to_m01_couplers_AWQOS;\n  wire m01_regslice_to_m01_couplers_AWREADY;\n  wire [3:0]m01_regslice_to_m01_couplers_AWREGION;\n  wire [2:0]m01_regslice_to_m01_couplers_AWSIZE;\n  wire m01_regslice_to_m01_couplers_AWVALID;\n  wire [6:0]m01_regslice_to_m01_couplers_BID;\n  wire m01_regslice_to_m01_couplers_BREADY;\n  wire [1:0]m01_regslice_to_m01_couplers_BRESP;\n  wire m01_regslice_to_m01_couplers_BVALID;\n  wire [511:0]m01_regslice_to_m01_couplers_RDATA;\n  wire [6:0]m01_regslice_to_m01_couplers_RID;\n  wire m01_regslice_to_m01_couplers_RLAST;\n  wire m01_regslice_to_m01_couplers_RREADY;\n  wire [1:0]m01_regslice_to_m01_couplers_RRESP;\n  wire m01_regslice_to_m01_couplers_RVALID;\n  wire [511:0]m01_regslice_to_m01_couplers_WDATA;\n  wire m01_regslice_to_m01_couplers_WLAST;\n  wire m01_regslice_to_m01_couplers_WREADY;\n  wire [63:0]m01_regslice_to_m01_couplers_WSTRB;\n  wire m01_regslice_to_m01_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m01_regslice_to_m01_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m01_regslice_to_m01_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m01_regslice_to_m01_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m01_regslice_to_m01_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m01_regslice_to_m01_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m01_regslice_to_m01_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m01_regslice_to_m01_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m01_regslice_to_m01_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m01_regslice_to_m01_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m01_regslice_to_m01_couplers_ARSIZE;\n  assign M_AXI_arvalid = m01_regslice_to_m01_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m01_regslice_to_m01_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m01_regslice_to_m01_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m01_regslice_to_m01_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m01_regslice_to_m01_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m01_regslice_to_m01_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m01_regslice_to_m01_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m01_regslice_to_m01_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m01_regslice_to_m01_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m01_regslice_to_m01_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m01_regslice_to_m01_couplers_AWSIZE;\n  assign M_AXI_awvalid = m01_regslice_to_m01_couplers_AWVALID;\n  assign M_AXI_bready = m01_regslice_to_m01_couplers_BREADY;\n  assign M_AXI_rready = m01_regslice_to_m01_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m01_regslice_to_m01_couplers_WDATA;\n  assign M_AXI_wlast = m01_regslice_to_m01_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m01_regslice_to_m01_couplers_WSTRB;\n  assign M_AXI_wvalid = m01_regslice_to_m01_couplers_WVALID;\n  assign S_AXI_arready = m01_couplers_to_m01_regslice_ARREADY;\n  assign S_AXI_awready = m01_couplers_to_m01_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m01_couplers_to_m01_regslice_BID;\n  assign S_AXI_bresp[1:0] = m01_couplers_to_m01_regslice_BRESP;\n  assign S_AXI_bvalid = m01_couplers_to_m01_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m01_couplers_to_m01_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m01_couplers_to_m01_regslice_RID;\n  assign S_AXI_rlast = m01_couplers_to_m01_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m01_couplers_to_m01_regslice_RRESP;\n  assign S_AXI_rvalid = m01_couplers_to_m01_regslice_RVALID;\n  assign S_AXI_wready = m01_couplers_to_m01_regslice_WREADY;\n  assign m01_couplers_to_m01_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m01_couplers_to_m01_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m01_couplers_to_m01_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m01_couplers_to_m01_regslice_ARID = S_AXI_arid[6:0];\n  assign m01_couplers_to_m01_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m01_couplers_to_m01_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m01_couplers_to_m01_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m01_couplers_to_m01_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m01_couplers_to_m01_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m01_couplers_to_m01_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m01_couplers_to_m01_regslice_ARVALID = S_AXI_arvalid;\n  assign m01_couplers_to_m01_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m01_couplers_to_m01_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m01_couplers_to_m01_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m01_couplers_to_m01_regslice_AWID = S_AXI_awid[6:0];\n  assign m01_couplers_to_m01_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m01_couplers_to_m01_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m01_couplers_to_m01_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m01_couplers_to_m01_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m01_couplers_to_m01_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m01_couplers_to_m01_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m01_couplers_to_m01_regslice_AWVALID = S_AXI_awvalid;\n  assign m01_couplers_to_m01_regslice_BREADY = S_AXI_bready;\n  assign m01_couplers_to_m01_regslice_RREADY = S_AXI_rready;\n  assign m01_couplers_to_m01_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m01_couplers_to_m01_regslice_WLAST = S_AXI_wlast;\n  assign m01_couplers_to_m01_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m01_couplers_to_m01_regslice_WVALID = S_AXI_wvalid;\n  assign m01_regslice_to_m01_couplers_ARREADY = M_AXI_arready;\n  assign m01_regslice_to_m01_couplers_AWREADY = M_AXI_awready;\n  assign m01_regslice_to_m01_couplers_BID = M_AXI_bid[6:0];\n  assign m01_regslice_to_m01_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m01_regslice_to_m01_couplers_BVALID = M_AXI_bvalid;\n  assign m01_regslice_to_m01_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m01_regslice_to_m01_couplers_RID = M_AXI_rid[6:0];\n  assign m01_regslice_to_m01_couplers_RLAST = M_AXI_rlast;\n  assign m01_regslice_to_m01_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m01_regslice_to_m01_couplers_RVALID = M_AXI_rvalid;\n  assign m01_regslice_to_m01_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m01_regslice_0 m01_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m01_regslice_to_m01_couplers_ARADDR),\n        .m_axi_arburst(m01_regslice_to_m01_couplers_ARBURST),\n        .m_axi_arcache(m01_regslice_to_m01_couplers_ARCACHE),\n        .m_axi_arid(m01_regslice_to_m01_couplers_ARID),\n        .m_axi_arlen(m01_regslice_to_m01_couplers_ARLEN),\n        .m_axi_arlock(m01_regslice_to_m01_couplers_ARLOCK),\n        .m_axi_arprot(m01_regslice_to_m01_couplers_ARPROT),\n        .m_axi_arqos(m01_regslice_to_m01_couplers_ARQOS),\n        .m_axi_arready(m01_regslice_to_m01_couplers_ARREADY),\n        .m_axi_arregion(m01_regslice_to_m01_couplers_ARREGION),\n        .m_axi_arsize(m01_regslice_to_m01_couplers_ARSIZE),\n        .m_axi_arvalid(m01_regslice_to_m01_couplers_ARVALID),\n        .m_axi_awaddr(m01_regslice_to_m01_couplers_AWADDR),\n        .m_axi_awburst(m01_regslice_to_m01_couplers_AWBURST),\n        .m_axi_awcache(m01_regslice_to_m01_couplers_AWCACHE),\n        .m_axi_awid(m01_regslice_to_m01_couplers_AWID),\n        .m_axi_awlen(m01_regslice_to_m01_couplers_AWLEN),\n        .m_axi_awlock(m01_regslice_to_m01_couplers_AWLOCK),\n        .m_axi_awprot(m01_regslice_to_m01_couplers_AWPROT),\n        .m_axi_awqos(m01_regslice_to_m01_couplers_AWQOS),\n        .m_axi_awready(m01_regslice_to_m01_couplers_AWREADY),\n        .m_axi_awregion(m01_regslice_to_m01_couplers_AWREGION),\n        .m_axi_awsize(m01_regslice_to_m01_couplers_AWSIZE),\n        .m_axi_awvalid(m01_regslice_to_m01_couplers_AWVALID),\n        .m_axi_bid(m01_regslice_to_m01_couplers_BID),\n        .m_axi_bready(m01_regslice_to_m01_couplers_BREADY),\n        .m_axi_bresp(m01_regslice_to_m01_couplers_BRESP),\n        .m_axi_bvalid(m01_regslice_to_m01_couplers_BVALID),\n        .m_axi_rdata(m01_regslice_to_m01_couplers_RDATA),\n        .m_axi_rid(m01_regslice_to_m01_couplers_RID),\n        .m_axi_rlast(m01_regslice_to_m01_couplers_RLAST),\n        .m_axi_rready(m01_regslice_to_m01_couplers_RREADY),\n        .m_axi_rresp(m01_regslice_to_m01_couplers_RRESP),\n        .m_axi_rvalid(m01_regslice_to_m01_couplers_RVALID),\n        .m_axi_wdata(m01_regslice_to_m01_couplers_WDATA),\n        .m_axi_wlast(m01_regslice_to_m01_couplers_WLAST),\n        .m_axi_wready(m01_regslice_to_m01_couplers_WREADY),\n        .m_axi_wstrb(m01_regslice_to_m01_couplers_WSTRB),\n        .m_axi_wvalid(m01_regslice_to_m01_couplers_WVALID),\n        .s_axi_araddr(m01_couplers_to_m01_regslice_ARADDR),\n        .s_axi_arburst(m01_couplers_to_m01_regslice_ARBURST),\n        .s_axi_arcache(m01_couplers_to_m01_regslice_ARCACHE),\n        .s_axi_arid(m01_couplers_to_m01_regslice_ARID),\n        .s_axi_arlen(m01_couplers_to_m01_regslice_ARLEN),\n        .s_axi_arlock(m01_couplers_to_m01_regslice_ARLOCK),\n        .s_axi_arprot(m01_couplers_to_m01_regslice_ARPROT),\n        .s_axi_arqos(m01_couplers_to_m01_regslice_ARQOS),\n        .s_axi_arready(m01_couplers_to_m01_regslice_ARREADY),\n        .s_axi_arregion(m01_couplers_to_m01_regslice_ARREGION),\n        .s_axi_arsize(m01_couplers_to_m01_regslice_ARSIZE),\n        .s_axi_arvalid(m01_couplers_to_m01_regslice_ARVALID),\n        .s_axi_awaddr(m01_couplers_to_m01_regslice_AWADDR),\n        .s_axi_awburst(m01_couplers_to_m01_regslice_AWBURST),\n        .s_axi_awcache(m01_couplers_to_m01_regslice_AWCACHE),\n        .s_axi_awid(m01_couplers_to_m01_regslice_AWID),\n        .s_axi_awlen(m01_couplers_to_m01_regslice_AWLEN),\n        .s_axi_awlock(m01_couplers_to_m01_regslice_AWLOCK),\n        .s_axi_awprot(m01_couplers_to_m01_regslice_AWPROT),\n        .s_axi_awqos(m01_couplers_to_m01_regslice_AWQOS),\n        .s_axi_awready(m01_couplers_to_m01_regslice_AWREADY),\n        .s_axi_awregion(m01_couplers_to_m01_regslice_AWREGION),\n        .s_axi_awsize(m01_couplers_to_m01_regslice_AWSIZE),\n        .s_axi_awvalid(m01_couplers_to_m01_regslice_AWVALID),\n        .s_axi_bid(m01_couplers_to_m01_regslice_BID),\n        .s_axi_bready(m01_couplers_to_m01_regslice_BREADY),\n        .s_axi_bresp(m01_couplers_to_m01_regslice_BRESP),\n        .s_axi_bvalid(m01_couplers_to_m01_regslice_BVALID),\n        .s_axi_rdata(m01_couplers_to_m01_regslice_RDATA),\n        .s_axi_rid(m01_couplers_to_m01_regslice_RID),\n        .s_axi_rlast(m01_couplers_to_m01_regslice_RLAST),\n        .s_axi_rready(m01_couplers_to_m01_regslice_RREADY),\n        .s_axi_rresp(m01_couplers_to_m01_regslice_RRESP),\n        .s_axi_rvalid(m01_couplers_to_m01_regslice_RVALID),\n        .s_axi_wdata(m01_couplers_to_m01_regslice_WDATA),\n        .s_axi_wlast(m01_couplers_to_m01_regslice_WLAST),\n        .s_axi_wready(m01_couplers_to_m01_regslice_WREADY),\n        .s_axi_wstrb(m01_couplers_to_m01_regslice_WSTRB),\n        .s_axi_wvalid(m01_couplers_to_m01_regslice_WVALID));\nendmodule\n\nmodule m02_couplers_imp_APDUS2\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m02_couplers_to_m02_regslice_ARADDR;\n  wire [1:0]m02_couplers_to_m02_regslice_ARBURST;\n  wire [3:0]m02_couplers_to_m02_regslice_ARCACHE;\n  wire [6:0]m02_couplers_to_m02_regslice_ARID;\n  wire [7:0]m02_couplers_to_m02_regslice_ARLEN;\n  wire [0:0]m02_couplers_to_m02_regslice_ARLOCK;\n  wire [2:0]m02_couplers_to_m02_regslice_ARPROT;\n  wire [3:0]m02_couplers_to_m02_regslice_ARQOS;\n  wire m02_couplers_to_m02_regslice_ARREADY;\n  wire [3:0]m02_couplers_to_m02_regslice_ARREGION;\n  wire [2:0]m02_couplers_to_m02_regslice_ARSIZE;\n  wire m02_couplers_to_m02_regslice_ARVALID;\n  wire [63:0]m02_couplers_to_m02_regslice_AWADDR;\n  wire [1:0]m02_couplers_to_m02_regslice_AWBURST;\n  wire [3:0]m02_couplers_to_m02_regslice_AWCACHE;\n  wire [6:0]m02_couplers_to_m02_regslice_AWID;\n  wire [7:0]m02_couplers_to_m02_regslice_AWLEN;\n  wire [0:0]m02_couplers_to_m02_regslice_AWLOCK;\n  wire [2:0]m02_couplers_to_m02_regslice_AWPROT;\n  wire [3:0]m02_couplers_to_m02_regslice_AWQOS;\n  wire m02_couplers_to_m02_regslice_AWREADY;\n  wire [3:0]m02_couplers_to_m02_regslice_AWREGION;\n  wire [2:0]m02_couplers_to_m02_regslice_AWSIZE;\n  wire m02_couplers_to_m02_regslice_AWVALID;\n  wire [6:0]m02_couplers_to_m02_regslice_BID;\n  wire m02_couplers_to_m02_regslice_BREADY;\n  wire [1:0]m02_couplers_to_m02_regslice_BRESP;\n  wire m02_couplers_to_m02_regslice_BVALID;\n  wire [511:0]m02_couplers_to_m02_regslice_RDATA;\n  wire [6:0]m02_couplers_to_m02_regslice_RID;\n  wire m02_couplers_to_m02_regslice_RLAST;\n  wire m02_couplers_to_m02_regslice_RREADY;\n  wire [1:0]m02_couplers_to_m02_regslice_RRESP;\n  wire m02_couplers_to_m02_regslice_RVALID;\n  wire [511:0]m02_couplers_to_m02_regslice_WDATA;\n  wire m02_couplers_to_m02_regslice_WLAST;\n  wire m02_couplers_to_m02_regslice_WREADY;\n  wire [63:0]m02_couplers_to_m02_regslice_WSTRB;\n  wire m02_couplers_to_m02_regslice_WVALID;\n  wire [63:0]m02_regslice_to_m02_couplers_ARADDR;\n  wire [1:0]m02_regslice_to_m02_couplers_ARBURST;\n  wire [3:0]m02_regslice_to_m02_couplers_ARCACHE;\n  wire [6:0]m02_regslice_to_m02_couplers_ARID;\n  wire [7:0]m02_regslice_to_m02_couplers_ARLEN;\n  wire [0:0]m02_regslice_to_m02_couplers_ARLOCK;\n  wire [2:0]m02_regslice_to_m02_couplers_ARPROT;\n  wire [3:0]m02_regslice_to_m02_couplers_ARQOS;\n  wire m02_regslice_to_m02_couplers_ARREADY;\n  wire [3:0]m02_regslice_to_m02_couplers_ARREGION;\n  wire [2:0]m02_regslice_to_m02_couplers_ARSIZE;\n  wire m02_regslice_to_m02_couplers_ARVALID;\n  wire [63:0]m02_regslice_to_m02_couplers_AWADDR;\n  wire [1:0]m02_regslice_to_m02_couplers_AWBURST;\n  wire [3:0]m02_regslice_to_m02_couplers_AWCACHE;\n  wire [6:0]m02_regslice_to_m02_couplers_AWID;\n  wire [7:0]m02_regslice_to_m02_couplers_AWLEN;\n  wire [0:0]m02_regslice_to_m02_couplers_AWLOCK;\n  wire [2:0]m02_regslice_to_m02_couplers_AWPROT;\n  wire [3:0]m02_regslice_to_m02_couplers_AWQOS;\n  wire m02_regslice_to_m02_couplers_AWREADY;\n  wire [3:0]m02_regslice_to_m02_couplers_AWREGION;\n  wire [2:0]m02_regslice_to_m02_couplers_AWSIZE;\n  wire m02_regslice_to_m02_couplers_AWVALID;\n  wire [6:0]m02_regslice_to_m02_couplers_BID;\n  wire m02_regslice_to_m02_couplers_BREADY;\n  wire [1:0]m02_regslice_to_m02_couplers_BRESP;\n  wire m02_regslice_to_m02_couplers_BVALID;\n  wire [511:0]m02_regslice_to_m02_couplers_RDATA;\n  wire [6:0]m02_regslice_to_m02_couplers_RID;\n  wire m02_regslice_to_m02_couplers_RLAST;\n  wire m02_regslice_to_m02_couplers_RREADY;\n  wire [1:0]m02_regslice_to_m02_couplers_RRESP;\n  wire m02_regslice_to_m02_couplers_RVALID;\n  wire [511:0]m02_regslice_to_m02_couplers_WDATA;\n  wire m02_regslice_to_m02_couplers_WLAST;\n  wire m02_regslice_to_m02_couplers_WREADY;\n  wire [63:0]m02_regslice_to_m02_couplers_WSTRB;\n  wire m02_regslice_to_m02_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m02_regslice_to_m02_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m02_regslice_to_m02_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m02_regslice_to_m02_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m02_regslice_to_m02_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m02_regslice_to_m02_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m02_regslice_to_m02_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m02_regslice_to_m02_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m02_regslice_to_m02_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m02_regslice_to_m02_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m02_regslice_to_m02_couplers_ARSIZE;\n  assign M_AXI_arvalid = m02_regslice_to_m02_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m02_regslice_to_m02_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m02_regslice_to_m02_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m02_regslice_to_m02_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m02_regslice_to_m02_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m02_regslice_to_m02_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m02_regslice_to_m02_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m02_regslice_to_m02_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m02_regslice_to_m02_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m02_regslice_to_m02_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m02_regslice_to_m02_couplers_AWSIZE;\n  assign M_AXI_awvalid = m02_regslice_to_m02_couplers_AWVALID;\n  assign M_AXI_bready = m02_regslice_to_m02_couplers_BREADY;\n  assign M_AXI_rready = m02_regslice_to_m02_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m02_regslice_to_m02_couplers_WDATA;\n  assign M_AXI_wlast = m02_regslice_to_m02_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m02_regslice_to_m02_couplers_WSTRB;\n  assign M_AXI_wvalid = m02_regslice_to_m02_couplers_WVALID;\n  assign S_AXI_arready = m02_couplers_to_m02_regslice_ARREADY;\n  assign S_AXI_awready = m02_couplers_to_m02_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m02_couplers_to_m02_regslice_BID;\n  assign S_AXI_bresp[1:0] = m02_couplers_to_m02_regslice_BRESP;\n  assign S_AXI_bvalid = m02_couplers_to_m02_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m02_couplers_to_m02_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m02_couplers_to_m02_regslice_RID;\n  assign S_AXI_rlast = m02_couplers_to_m02_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m02_couplers_to_m02_regslice_RRESP;\n  assign S_AXI_rvalid = m02_couplers_to_m02_regslice_RVALID;\n  assign S_AXI_wready = m02_couplers_to_m02_regslice_WREADY;\n  assign m02_couplers_to_m02_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m02_couplers_to_m02_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m02_couplers_to_m02_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m02_couplers_to_m02_regslice_ARID = S_AXI_arid[6:0];\n  assign m02_couplers_to_m02_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m02_couplers_to_m02_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m02_couplers_to_m02_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m02_couplers_to_m02_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m02_couplers_to_m02_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m02_couplers_to_m02_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m02_couplers_to_m02_regslice_ARVALID = S_AXI_arvalid;\n  assign m02_couplers_to_m02_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m02_couplers_to_m02_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m02_couplers_to_m02_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m02_couplers_to_m02_regslice_AWID = S_AXI_awid[6:0];\n  assign m02_couplers_to_m02_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m02_couplers_to_m02_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m02_couplers_to_m02_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m02_couplers_to_m02_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m02_couplers_to_m02_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m02_couplers_to_m02_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m02_couplers_to_m02_regslice_AWVALID = S_AXI_awvalid;\n  assign m02_couplers_to_m02_regslice_BREADY = S_AXI_bready;\n  assign m02_couplers_to_m02_regslice_RREADY = S_AXI_rready;\n  assign m02_couplers_to_m02_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m02_couplers_to_m02_regslice_WLAST = S_AXI_wlast;\n  assign m02_couplers_to_m02_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m02_couplers_to_m02_regslice_WVALID = S_AXI_wvalid;\n  assign m02_regslice_to_m02_couplers_ARREADY = M_AXI_arready;\n  assign m02_regslice_to_m02_couplers_AWREADY = M_AXI_awready;\n  assign m02_regslice_to_m02_couplers_BID = M_AXI_bid[6:0];\n  assign m02_regslice_to_m02_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m02_regslice_to_m02_couplers_BVALID = M_AXI_bvalid;\n  assign m02_regslice_to_m02_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m02_regslice_to_m02_couplers_RID = M_AXI_rid[6:0];\n  assign m02_regslice_to_m02_couplers_RLAST = M_AXI_rlast;\n  assign m02_regslice_to_m02_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m02_regslice_to_m02_couplers_RVALID = M_AXI_rvalid;\n  assign m02_regslice_to_m02_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m02_regslice_0 m02_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m02_regslice_to_m02_couplers_ARADDR),\n        .m_axi_arburst(m02_regslice_to_m02_couplers_ARBURST),\n        .m_axi_arcache(m02_regslice_to_m02_couplers_ARCACHE),\n        .m_axi_arid(m02_regslice_to_m02_couplers_ARID),\n        .m_axi_arlen(m02_regslice_to_m02_couplers_ARLEN),\n        .m_axi_arlock(m02_regslice_to_m02_couplers_ARLOCK),\n        .m_axi_arprot(m02_regslice_to_m02_couplers_ARPROT),\n        .m_axi_arqos(m02_regslice_to_m02_couplers_ARQOS),\n        .m_axi_arready(m02_regslice_to_m02_couplers_ARREADY),\n        .m_axi_arregion(m02_regslice_to_m02_couplers_ARREGION),\n        .m_axi_arsize(m02_regslice_to_m02_couplers_ARSIZE),\n        .m_axi_arvalid(m02_regslice_to_m02_couplers_ARVALID),\n        .m_axi_awaddr(m02_regslice_to_m02_couplers_AWADDR),\n        .m_axi_awburst(m02_regslice_to_m02_couplers_AWBURST),\n        .m_axi_awcache(m02_regslice_to_m02_couplers_AWCACHE),\n        .m_axi_awid(m02_regslice_to_m02_couplers_AWID),\n        .m_axi_awlen(m02_regslice_to_m02_couplers_AWLEN),\n        .m_axi_awlock(m02_regslice_to_m02_couplers_AWLOCK),\n        .m_axi_awprot(m02_regslice_to_m02_couplers_AWPROT),\n        .m_axi_awqos(m02_regslice_to_m02_couplers_AWQOS),\n        .m_axi_awready(m02_regslice_to_m02_couplers_AWREADY),\n        .m_axi_awregion(m02_regslice_to_m02_couplers_AWREGION),\n        .m_axi_awsize(m02_regslice_to_m02_couplers_AWSIZE),\n        .m_axi_awvalid(m02_regslice_to_m02_couplers_AWVALID),\n        .m_axi_bid(m02_regslice_to_m02_couplers_BID),\n        .m_axi_bready(m02_regslice_to_m02_couplers_BREADY),\n        .m_axi_bresp(m02_regslice_to_m02_couplers_BRESP),\n        .m_axi_bvalid(m02_regslice_to_m02_couplers_BVALID),\n        .m_axi_rdata(m02_regslice_to_m02_couplers_RDATA),\n        .m_axi_rid(m02_regslice_to_m02_couplers_RID),\n        .m_axi_rlast(m02_regslice_to_m02_couplers_RLAST),\n        .m_axi_rready(m02_regslice_to_m02_couplers_RREADY),\n        .m_axi_rresp(m02_regslice_to_m02_couplers_RRESP),\n        .m_axi_rvalid(m02_regslice_to_m02_couplers_RVALID),\n        .m_axi_wdata(m02_regslice_to_m02_couplers_WDATA),\n        .m_axi_wlast(m02_regslice_to_m02_couplers_WLAST),\n        .m_axi_wready(m02_regslice_to_m02_couplers_WREADY),\n        .m_axi_wstrb(m02_regslice_to_m02_couplers_WSTRB),\n        .m_axi_wvalid(m02_regslice_to_m02_couplers_WVALID),\n        .s_axi_araddr(m02_couplers_to_m02_regslice_ARADDR),\n        .s_axi_arburst(m02_couplers_to_m02_regslice_ARBURST),\n        .s_axi_arcache(m02_couplers_to_m02_regslice_ARCACHE),\n        .s_axi_arid(m02_couplers_to_m02_regslice_ARID),\n        .s_axi_arlen(m02_couplers_to_m02_regslice_ARLEN),\n        .s_axi_arlock(m02_couplers_to_m02_regslice_ARLOCK),\n        .s_axi_arprot(m02_couplers_to_m02_regslice_ARPROT),\n        .s_axi_arqos(m02_couplers_to_m02_regslice_ARQOS),\n        .s_axi_arready(m02_couplers_to_m02_regslice_ARREADY),\n        .s_axi_arregion(m02_couplers_to_m02_regslice_ARREGION),\n        .s_axi_arsize(m02_couplers_to_m02_regslice_ARSIZE),\n        .s_axi_arvalid(m02_couplers_to_m02_regslice_ARVALID),\n        .s_axi_awaddr(m02_couplers_to_m02_regslice_AWADDR),\n        .s_axi_awburst(m02_couplers_to_m02_regslice_AWBURST),\n        .s_axi_awcache(m02_couplers_to_m02_regslice_AWCACHE),\n        .s_axi_awid(m02_couplers_to_m02_regslice_AWID),\n        .s_axi_awlen(m02_couplers_to_m02_regslice_AWLEN),\n        .s_axi_awlock(m02_couplers_to_m02_regslice_AWLOCK),\n        .s_axi_awprot(m02_couplers_to_m02_regslice_AWPROT),\n        .s_axi_awqos(m02_couplers_to_m02_regslice_AWQOS),\n        .s_axi_awready(m02_couplers_to_m02_regslice_AWREADY),\n        .s_axi_awregion(m02_couplers_to_m02_regslice_AWREGION),\n        .s_axi_awsize(m02_couplers_to_m02_regslice_AWSIZE),\n        .s_axi_awvalid(m02_couplers_to_m02_regslice_AWVALID),\n        .s_axi_bid(m02_couplers_to_m02_regslice_BID),\n        .s_axi_bready(m02_couplers_to_m02_regslice_BREADY),\n        .s_axi_bresp(m02_couplers_to_m02_regslice_BRESP),\n        .s_axi_bvalid(m02_couplers_to_m02_regslice_BVALID),\n        .s_axi_rdata(m02_couplers_to_m02_regslice_RDATA),\n        .s_axi_rid(m02_couplers_to_m02_regslice_RID),\n        .s_axi_rlast(m02_couplers_to_m02_regslice_RLAST),\n        .s_axi_rready(m02_couplers_to_m02_regslice_RREADY),\n        .s_axi_rresp(m02_couplers_to_m02_regslice_RRESP),\n        .s_axi_rvalid(m02_couplers_to_m02_regslice_RVALID),\n        .s_axi_wdata(m02_couplers_to_m02_regslice_WDATA),\n        .s_axi_wlast(m02_couplers_to_m02_regslice_WLAST),\n        .s_axi_wready(m02_couplers_to_m02_regslice_WREADY),\n        .s_axi_wstrb(m02_couplers_to_m02_regslice_WSTRB),\n        .s_axi_wvalid(m02_couplers_to_m02_regslice_WVALID));\nendmodule\n\nmodule m03_couplers_imp_JAYOMU\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m03_couplers_to_m03_regslice_ARADDR;\n  wire [1:0]m03_couplers_to_m03_regslice_ARBURST;\n  wire [3:0]m03_couplers_to_m03_regslice_ARCACHE;\n  wire [6:0]m03_couplers_to_m03_regslice_ARID;\n  wire [7:0]m03_couplers_to_m03_regslice_ARLEN;\n  wire [0:0]m03_couplers_to_m03_regslice_ARLOCK;\n  wire [2:0]m03_couplers_to_m03_regslice_ARPROT;\n  wire [3:0]m03_couplers_to_m03_regslice_ARQOS;\n  wire m03_couplers_to_m03_regslice_ARREADY;\n  wire [3:0]m03_couplers_to_m03_regslice_ARREGION;\n  wire [2:0]m03_couplers_to_m03_regslice_ARSIZE;\n  wire m03_couplers_to_m03_regslice_ARVALID;\n  wire [63:0]m03_couplers_to_m03_regslice_AWADDR;\n  wire [1:0]m03_couplers_to_m03_regslice_AWBURST;\n  wire [3:0]m03_couplers_to_m03_regslice_AWCACHE;\n  wire [6:0]m03_couplers_to_m03_regslice_AWID;\n  wire [7:0]m03_couplers_to_m03_regslice_AWLEN;\n  wire [0:0]m03_couplers_to_m03_regslice_AWLOCK;\n  wire [2:0]m03_couplers_to_m03_regslice_AWPROT;\n  wire [3:0]m03_couplers_to_m03_regslice_AWQOS;\n  wire m03_couplers_to_m03_regslice_AWREADY;\n  wire [3:0]m03_couplers_to_m03_regslice_AWREGION;\n  wire [2:0]m03_couplers_to_m03_regslice_AWSIZE;\n  wire m03_couplers_to_m03_regslice_AWVALID;\n  wire [6:0]m03_couplers_to_m03_regslice_BID;\n  wire m03_couplers_to_m03_regslice_BREADY;\n  wire [1:0]m03_couplers_to_m03_regslice_BRESP;\n  wire m03_couplers_to_m03_regslice_BVALID;\n  wire [511:0]m03_couplers_to_m03_regslice_RDATA;\n  wire [6:0]m03_couplers_to_m03_regslice_RID;\n  wire m03_couplers_to_m03_regslice_RLAST;\n  wire m03_couplers_to_m03_regslice_RREADY;\n  wire [1:0]m03_couplers_to_m03_regslice_RRESP;\n  wire m03_couplers_to_m03_regslice_RVALID;\n  wire [511:0]m03_couplers_to_m03_regslice_WDATA;\n  wire m03_couplers_to_m03_regslice_WLAST;\n  wire m03_couplers_to_m03_regslice_WREADY;\n  wire [63:0]m03_couplers_to_m03_regslice_WSTRB;\n  wire m03_couplers_to_m03_regslice_WVALID;\n  wire [63:0]m03_regslice_to_m03_couplers_ARADDR;\n  wire [1:0]m03_regslice_to_m03_couplers_ARBURST;\n  wire [3:0]m03_regslice_to_m03_couplers_ARCACHE;\n  wire [6:0]m03_regslice_to_m03_couplers_ARID;\n  wire [7:0]m03_regslice_to_m03_couplers_ARLEN;\n  wire [0:0]m03_regslice_to_m03_couplers_ARLOCK;\n  wire [2:0]m03_regslice_to_m03_couplers_ARPROT;\n  wire [3:0]m03_regslice_to_m03_couplers_ARQOS;\n  wire m03_regslice_to_m03_couplers_ARREADY;\n  wire [3:0]m03_regslice_to_m03_couplers_ARREGION;\n  wire [2:0]m03_regslice_to_m03_couplers_ARSIZE;\n  wire m03_regslice_to_m03_couplers_ARVALID;\n  wire [63:0]m03_regslice_to_m03_couplers_AWADDR;\n  wire [1:0]m03_regslice_to_m03_couplers_AWBURST;\n  wire [3:0]m03_regslice_to_m03_couplers_AWCACHE;\n  wire [6:0]m03_regslice_to_m03_couplers_AWID;\n  wire [7:0]m03_regslice_to_m03_couplers_AWLEN;\n  wire [0:0]m03_regslice_to_m03_couplers_AWLOCK;\n  wire [2:0]m03_regslice_to_m03_couplers_AWPROT;\n  wire [3:0]m03_regslice_to_m03_couplers_AWQOS;\n  wire m03_regslice_to_m03_couplers_AWREADY;\n  wire [3:0]m03_regslice_to_m03_couplers_AWREGION;\n  wire [2:0]m03_regslice_to_m03_couplers_AWSIZE;\n  wire m03_regslice_to_m03_couplers_AWVALID;\n  wire [6:0]m03_regslice_to_m03_couplers_BID;\n  wire m03_regslice_to_m03_couplers_BREADY;\n  wire [1:0]m03_regslice_to_m03_couplers_BRESP;\n  wire m03_regslice_to_m03_couplers_BVALID;\n  wire [511:0]m03_regslice_to_m03_couplers_RDATA;\n  wire [6:0]m03_regslice_to_m03_couplers_RID;\n  wire m03_regslice_to_m03_couplers_RLAST;\n  wire m03_regslice_to_m03_couplers_RREADY;\n  wire [1:0]m03_regslice_to_m03_couplers_RRESP;\n  wire m03_regslice_to_m03_couplers_RVALID;\n  wire [511:0]m03_regslice_to_m03_couplers_WDATA;\n  wire m03_regslice_to_m03_couplers_WLAST;\n  wire m03_regslice_to_m03_couplers_WREADY;\n  wire [63:0]m03_regslice_to_m03_couplers_WSTRB;\n  wire m03_regslice_to_m03_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m03_regslice_to_m03_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m03_regslice_to_m03_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m03_regslice_to_m03_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m03_regslice_to_m03_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m03_regslice_to_m03_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m03_regslice_to_m03_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m03_regslice_to_m03_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m03_regslice_to_m03_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m03_regslice_to_m03_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m03_regslice_to_m03_couplers_ARSIZE;\n  assign M_AXI_arvalid = m03_regslice_to_m03_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m03_regslice_to_m03_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m03_regslice_to_m03_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m03_regslice_to_m03_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m03_regslice_to_m03_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m03_regslice_to_m03_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m03_regslice_to_m03_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m03_regslice_to_m03_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m03_regslice_to_m03_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m03_regslice_to_m03_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m03_regslice_to_m03_couplers_AWSIZE;\n  assign M_AXI_awvalid = m03_regslice_to_m03_couplers_AWVALID;\n  assign M_AXI_bready = m03_regslice_to_m03_couplers_BREADY;\n  assign M_AXI_rready = m03_regslice_to_m03_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m03_regslice_to_m03_couplers_WDATA;\n  assign M_AXI_wlast = m03_regslice_to_m03_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m03_regslice_to_m03_couplers_WSTRB;\n  assign M_AXI_wvalid = m03_regslice_to_m03_couplers_WVALID;\n  assign S_AXI_arready = m03_couplers_to_m03_regslice_ARREADY;\n  assign S_AXI_awready = m03_couplers_to_m03_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m03_couplers_to_m03_regslice_BID;\n  assign S_AXI_bresp[1:0] = m03_couplers_to_m03_regslice_BRESP;\n  assign S_AXI_bvalid = m03_couplers_to_m03_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m03_couplers_to_m03_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m03_couplers_to_m03_regslice_RID;\n  assign S_AXI_rlast = m03_couplers_to_m03_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m03_couplers_to_m03_regslice_RRESP;\n  assign S_AXI_rvalid = m03_couplers_to_m03_regslice_RVALID;\n  assign S_AXI_wready = m03_couplers_to_m03_regslice_WREADY;\n  assign m03_couplers_to_m03_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m03_couplers_to_m03_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m03_couplers_to_m03_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m03_couplers_to_m03_regslice_ARID = S_AXI_arid[6:0];\n  assign m03_couplers_to_m03_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m03_couplers_to_m03_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m03_couplers_to_m03_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m03_couplers_to_m03_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m03_couplers_to_m03_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m03_couplers_to_m03_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m03_couplers_to_m03_regslice_ARVALID = S_AXI_arvalid;\n  assign m03_couplers_to_m03_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m03_couplers_to_m03_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m03_couplers_to_m03_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m03_couplers_to_m03_regslice_AWID = S_AXI_awid[6:0];\n  assign m03_couplers_to_m03_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m03_couplers_to_m03_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m03_couplers_to_m03_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m03_couplers_to_m03_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m03_couplers_to_m03_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m03_couplers_to_m03_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m03_couplers_to_m03_regslice_AWVALID = S_AXI_awvalid;\n  assign m03_couplers_to_m03_regslice_BREADY = S_AXI_bready;\n  assign m03_couplers_to_m03_regslice_RREADY = S_AXI_rready;\n  assign m03_couplers_to_m03_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m03_couplers_to_m03_regslice_WLAST = S_AXI_wlast;\n  assign m03_couplers_to_m03_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m03_couplers_to_m03_regslice_WVALID = S_AXI_wvalid;\n  assign m03_regslice_to_m03_couplers_ARREADY = M_AXI_arready;\n  assign m03_regslice_to_m03_couplers_AWREADY = M_AXI_awready;\n  assign m03_regslice_to_m03_couplers_BID = M_AXI_bid[6:0];\n  assign m03_regslice_to_m03_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m03_regslice_to_m03_couplers_BVALID = M_AXI_bvalid;\n  assign m03_regslice_to_m03_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m03_regslice_to_m03_couplers_RID = M_AXI_rid[6:0];\n  assign m03_regslice_to_m03_couplers_RLAST = M_AXI_rlast;\n  assign m03_regslice_to_m03_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m03_regslice_to_m03_couplers_RVALID = M_AXI_rvalid;\n  assign m03_regslice_to_m03_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m03_regslice_0 m03_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m03_regslice_to_m03_couplers_ARADDR),\n        .m_axi_arburst(m03_regslice_to_m03_couplers_ARBURST),\n        .m_axi_arcache(m03_regslice_to_m03_couplers_ARCACHE),\n        .m_axi_arid(m03_regslice_to_m03_couplers_ARID),\n        .m_axi_arlen(m03_regslice_to_m03_couplers_ARLEN),\n        .m_axi_arlock(m03_regslice_to_m03_couplers_ARLOCK),\n        .m_axi_arprot(m03_regslice_to_m03_couplers_ARPROT),\n        .m_axi_arqos(m03_regslice_to_m03_couplers_ARQOS),\n        .m_axi_arready(m03_regslice_to_m03_couplers_ARREADY),\n        .m_axi_arregion(m03_regslice_to_m03_couplers_ARREGION),\n        .m_axi_arsize(m03_regslice_to_m03_couplers_ARSIZE),\n        .m_axi_arvalid(m03_regslice_to_m03_couplers_ARVALID),\n        .m_axi_awaddr(m03_regslice_to_m03_couplers_AWADDR),\n        .m_axi_awburst(m03_regslice_to_m03_couplers_AWBURST),\n        .m_axi_awcache(m03_regslice_to_m03_couplers_AWCACHE),\n        .m_axi_awid(m03_regslice_to_m03_couplers_AWID),\n        .m_axi_awlen(m03_regslice_to_m03_couplers_AWLEN),\n        .m_axi_awlock(m03_regslice_to_m03_couplers_AWLOCK),\n        .m_axi_awprot(m03_regslice_to_m03_couplers_AWPROT),\n        .m_axi_awqos(m03_regslice_to_m03_couplers_AWQOS),\n        .m_axi_awready(m03_regslice_to_m03_couplers_AWREADY),\n        .m_axi_awregion(m03_regslice_to_m03_couplers_AWREGION),\n        .m_axi_awsize(m03_regslice_to_m03_couplers_AWSIZE),\n        .m_axi_awvalid(m03_regslice_to_m03_couplers_AWVALID),\n        .m_axi_bid(m03_regslice_to_m03_couplers_BID),\n        .m_axi_bready(m03_regslice_to_m03_couplers_BREADY),\n        .m_axi_bresp(m03_regslice_to_m03_couplers_BRESP),\n        .m_axi_bvalid(m03_regslice_to_m03_couplers_BVALID),\n        .m_axi_rdata(m03_regslice_to_m03_couplers_RDATA),\n        .m_axi_rid(m03_regslice_to_m03_couplers_RID),\n        .m_axi_rlast(m03_regslice_to_m03_couplers_RLAST),\n        .m_axi_rready(m03_regslice_to_m03_couplers_RREADY),\n        .m_axi_rresp(m03_regslice_to_m03_couplers_RRESP),\n        .m_axi_rvalid(m03_regslice_to_m03_couplers_RVALID),\n        .m_axi_wdata(m03_regslice_to_m03_couplers_WDATA),\n        .m_axi_wlast(m03_regslice_to_m03_couplers_WLAST),\n        .m_axi_wready(m03_regslice_to_m03_couplers_WREADY),\n        .m_axi_wstrb(m03_regslice_to_m03_couplers_WSTRB),\n        .m_axi_wvalid(m03_regslice_to_m03_couplers_WVALID),\n        .s_axi_araddr(m03_couplers_to_m03_regslice_ARADDR),\n        .s_axi_arburst(m03_couplers_to_m03_regslice_ARBURST),\n        .s_axi_arcache(m03_couplers_to_m03_regslice_ARCACHE),\n        .s_axi_arid(m03_couplers_to_m03_regslice_ARID),\n        .s_axi_arlen(m03_couplers_to_m03_regslice_ARLEN),\n        .s_axi_arlock(m03_couplers_to_m03_regslice_ARLOCK),\n        .s_axi_arprot(m03_couplers_to_m03_regslice_ARPROT),\n        .s_axi_arqos(m03_couplers_to_m03_regslice_ARQOS),\n        .s_axi_arready(m03_couplers_to_m03_regslice_ARREADY),\n        .s_axi_arregion(m03_couplers_to_m03_regslice_ARREGION),\n        .s_axi_arsize(m03_couplers_to_m03_regslice_ARSIZE),\n        .s_axi_arvalid(m03_couplers_to_m03_regslice_ARVALID),\n        .s_axi_awaddr(m03_couplers_to_m03_regslice_AWADDR),\n        .s_axi_awburst(m03_couplers_to_m03_regslice_AWBURST),\n        .s_axi_awcache(m03_couplers_to_m03_regslice_AWCACHE),\n        .s_axi_awid(m03_couplers_to_m03_regslice_AWID),\n        .s_axi_awlen(m03_couplers_to_m03_regslice_AWLEN),\n        .s_axi_awlock(m03_couplers_to_m03_regslice_AWLOCK),\n        .s_axi_awprot(m03_couplers_to_m03_regslice_AWPROT),\n        .s_axi_awqos(m03_couplers_to_m03_regslice_AWQOS),\n        .s_axi_awready(m03_couplers_to_m03_regslice_AWREADY),\n        .s_axi_awregion(m03_couplers_to_m03_regslice_AWREGION),\n        .s_axi_awsize(m03_couplers_to_m03_regslice_AWSIZE),\n        .s_axi_awvalid(m03_couplers_to_m03_regslice_AWVALID),\n        .s_axi_bid(m03_couplers_to_m03_regslice_BID),\n        .s_axi_bready(m03_couplers_to_m03_regslice_BREADY),\n        .s_axi_bresp(m03_couplers_to_m03_regslice_BRESP),\n        .s_axi_bvalid(m03_couplers_to_m03_regslice_BVALID),\n        .s_axi_rdata(m03_couplers_to_m03_regslice_RDATA),\n        .s_axi_rid(m03_couplers_to_m03_regslice_RID),\n        .s_axi_rlast(m03_couplers_to_m03_regslice_RLAST),\n        .s_axi_rready(m03_couplers_to_m03_regslice_RREADY),\n        .s_axi_rresp(m03_couplers_to_m03_regslice_RRESP),\n        .s_axi_rvalid(m03_couplers_to_m03_regslice_RVALID),\n        .s_axi_wdata(m03_couplers_to_m03_regslice_WDATA),\n        .s_axi_wlast(m03_couplers_to_m03_regslice_WLAST),\n        .s_axi_wready(m03_couplers_to_m03_regslice_WREADY),\n        .s_axi_wstrb(m03_couplers_to_m03_regslice_WSTRB),\n        .s_axi_wvalid(m03_couplers_to_m03_regslice_WVALID));\nendmodule\n\nmodule s00_couplers_imp_QICM5G\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [5:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [5:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [5:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [5:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [5:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [5:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire S_ACLK_1;\n  wire S_ARESETN_1;\n  wire [63:0]s00_couplers_to_s00_regslice_ARADDR;\n  wire [1:0]s00_couplers_to_s00_regslice_ARBURST;\n  wire [3:0]s00_couplers_to_s00_regslice_ARCACHE;\n  wire [5:0]s00_couplers_to_s00_regslice_ARID;\n  wire [7:0]s00_couplers_to_s00_regslice_ARLEN;\n  wire [0:0]s00_couplers_to_s00_regslice_ARLOCK;\n  wire [2:0]s00_couplers_to_s00_regslice_ARPROT;\n  wire [3:0]s00_couplers_to_s00_regslice_ARQOS;\n  wire s00_couplers_to_s00_regslice_ARREADY;\n  wire [3:0]s00_couplers_to_s00_regslice_ARREGION;\n  wire [2:0]s00_couplers_to_s00_regslice_ARSIZE;\n  wire s00_couplers_to_s00_regslice_ARVALID;\n  wire [63:0]s00_couplers_to_s00_regslice_AWADDR;\n  wire [1:0]s00_couplers_to_s00_regslice_AWBURST;\n  wire [3:0]s00_couplers_to_s00_regslice_AWCACHE;\n  wire [5:0]s00_couplers_to_s00_regslice_AWID;\n  wire [7:0]s00_couplers_to_s00_regslice_AWLEN;\n  wire [0:0]s00_couplers_to_s00_regslice_AWLOCK;\n  wire [2:0]s00_couplers_to_s00_regslice_AWPROT;\n  wire [3:0]s00_couplers_to_s00_regslice_AWQOS;\n  wire s00_couplers_to_s00_regslice_AWREADY;\n  wire [3:0]s00_couplers_to_s00_regslice_AWREGION;\n  wire [2:0]s00_couplers_to_s00_regslice_AWSIZE;\n  wire s00_couplers_to_s00_regslice_AWVALID;\n  wire [5:0]s00_couplers_to_s00_regslice_BID;\n  wire s00_couplers_to_s00_regslice_BREADY;\n  wire [1:0]s00_couplers_to_s00_regslice_BRESP;\n  wire s00_couplers_to_s00_regslice_BVALID;\n  wire [511:0]s00_couplers_to_s00_regslice_RDATA;\n  wire [5:0]s00_couplers_to_s00_regslice_RID;\n  wire s00_couplers_to_s00_regslice_RLAST;\n  wire s00_couplers_to_s00_regslice_RREADY;\n  wire [1:0]s00_couplers_to_s00_regslice_RRESP;\n  wire s00_couplers_to_s00_regslice_RVALID;\n  wire [511:0]s00_couplers_to_s00_regslice_WDATA;\n  wire s00_couplers_to_s00_regslice_WLAST;\n  wire s00_couplers_to_s00_regslice_WREADY;\n  wire [63:0]s00_couplers_to_s00_regslice_WSTRB;\n  wire s00_couplers_to_s00_regslice_WVALID;\n  wire [63:0]s00_regslice_to_s00_couplers_ARADDR;\n  wire [1:0]s00_regslice_to_s00_couplers_ARBURST;\n  wire [3:0]s00_regslice_to_s00_couplers_ARCACHE;\n  wire [5:0]s00_regslice_to_s00_couplers_ARID;\n  wire [7:0]s00_regslice_to_s00_couplers_ARLEN;\n  wire [0:0]s00_regslice_to_s00_couplers_ARLOCK;\n  wire [2:0]s00_regslice_to_s00_couplers_ARPROT;\n  wire [3:0]s00_regslice_to_s00_couplers_ARQOS;\n  wire s00_regslice_to_s00_couplers_ARREADY;\n  wire [2:0]s00_regslice_to_s00_couplers_ARSIZE;\n  wire s00_regslice_to_s00_couplers_ARVALID;\n  wire [63:0]s00_regslice_to_s00_couplers_AWADDR;\n  wire [1:0]s00_regslice_to_s00_couplers_AWBURST;\n  wire [3:0]s00_regslice_to_s00_couplers_AWCACHE;\n  wire [5:0]s00_regslice_to_s00_couplers_AWID;\n  wire [7:0]s00_regslice_to_s00_couplers_AWLEN;\n  wire [0:0]s00_regslice_to_s00_couplers_AWLOCK;\n  wire [2:0]s00_regslice_to_s00_couplers_AWPROT;\n  wire [3:0]s00_regslice_to_s00_couplers_AWQOS;\n  wire s00_regslice_to_s00_couplers_AWREADY;\n  wire [2:0]s00_regslice_to_s00_couplers_AWSIZE;\n  wire s00_regslice_to_s00_couplers_AWVALID;\n  wire [6:0]s00_regslice_to_s00_couplers_BID;\n  wire s00_regslice_to_s00_couplers_BREADY;\n  wire [1:0]s00_regslice_to_s00_couplers_BRESP;\n  wire s00_regslice_to_s00_couplers_BVALID;\n  wire [511:0]s00_regslice_to_s00_couplers_RDATA;\n  wire [6:0]s00_regslice_to_s00_couplers_RID;\n  wire s00_regslice_to_s00_couplers_RLAST;\n  wire s00_regslice_to_s00_couplers_RREADY;\n  wire [1:0]s00_regslice_to_s00_couplers_RRESP;\n  wire s00_regslice_to_s00_couplers_RVALID;\n  wire [511:0]s00_regslice_to_s00_couplers_WDATA;\n  wire s00_regslice_to_s00_couplers_WLAST;\n  wire s00_regslice_to_s00_couplers_WREADY;\n  wire [63:0]s00_regslice_to_s00_couplers_WSTRB;\n  wire s00_regslice_to_s00_couplers_WVALID;\n\n  assign M_AXI_araddr[63:0] = s00_regslice_to_s00_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = s00_regslice_to_s00_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = s00_regslice_to_s00_couplers_ARCACHE;\n  assign M_AXI_arid[5:0] = s00_regslice_to_s00_couplers_ARID;\n  assign M_AXI_arlen[7:0] = s00_regslice_to_s00_couplers_ARLEN;\n  assign M_AXI_arlock[0] = s00_regslice_to_s00_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = s00_regslice_to_s00_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = s00_regslice_to_s00_couplers_ARQOS;\n  assign M_AXI_arsize[2:0] = s00_regslice_to_s00_couplers_ARSIZE;\n  assign M_AXI_arvalid = s00_regslice_to_s00_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = s00_regslice_to_s00_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = s00_regslice_to_s00_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = s00_regslice_to_s00_couplers_AWCACHE;\n  assign M_AXI_awid[5:0] = s00_regslice_to_s00_couplers_AWID;\n  assign M_AXI_awlen[7:0] = s00_regslice_to_s00_couplers_AWLEN;\n  assign M_AXI_awlock[0] = s00_regslice_to_s00_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = s00_regslice_to_s00_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = s00_regslice_to_s00_couplers_AWQOS;\n  assign M_AXI_awsize[2:0] = s00_regslice_to_s00_couplers_AWSIZE;\n  assign M_AXI_awvalid = s00_regslice_to_s00_couplers_AWVALID;\n  assign M_AXI_bready = s00_regslice_to_s00_couplers_BREADY;\n  assign M_AXI_rready = s00_regslice_to_s00_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = s00_regslice_to_s00_couplers_WDATA;\n  assign M_AXI_wlast = s00_regslice_to_s00_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = s00_regslice_to_s00_couplers_WSTRB;\n  assign M_AXI_wvalid = s00_regslice_to_s00_couplers_WVALID;\n  assign S_ACLK_1 = S_ACLK;\n  assign S_ARESETN_1 = S_ARESETN;\n  assign S_AXI_arready = s00_couplers_to_s00_regslice_ARREADY;\n  assign S_AXI_awready = s00_couplers_to_s00_regslice_AWREADY;\n  assign S_AXI_bid[5:0] = s00_couplers_to_s00_regslice_BID;\n  assign S_AXI_bresp[1:0] = s00_couplers_to_s00_regslice_BRESP;\n  assign S_AXI_bvalid = s00_couplers_to_s00_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = s00_couplers_to_s00_regslice_RDATA;\n  assign S_AXI_rid[5:0] = s00_couplers_to_s00_regslice_RID;\n  assign S_AXI_rlast = s00_couplers_to_s00_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = s00_couplers_to_s00_regslice_RRESP;\n  assign S_AXI_rvalid = s00_couplers_to_s00_regslice_RVALID;\n  assign S_AXI_wready = s00_couplers_to_s00_regslice_WREADY;\n  assign s00_couplers_to_s00_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign s00_couplers_to_s00_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign s00_couplers_to_s00_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign s00_couplers_to_s00_regslice_ARID = S_AXI_arid[5:0];\n  assign s00_couplers_to_s00_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign s00_couplers_to_s00_regslice_ARLOCK = S_AXI_arlock[0];\n  assign s00_couplers_to_s00_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign s00_couplers_to_s00_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign s00_couplers_to_s00_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign s00_couplers_to_s00_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign s00_couplers_to_s00_regslice_ARVALID = S_AXI_arvalid;\n  assign s00_couplers_to_s00_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign s00_couplers_to_s00_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign s00_couplers_to_s00_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign s00_couplers_to_s00_regslice_AWID = S_AXI_awid[5:0];\n  assign s00_couplers_to_s00_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign s00_couplers_to_s00_regslice_AWLOCK = S_AXI_awlock[0];\n  assign s00_couplers_to_s00_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign s00_couplers_to_s00_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign s00_couplers_to_s00_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign s00_couplers_to_s00_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign s00_couplers_to_s00_regslice_AWVALID = S_AXI_awvalid;\n  assign s00_couplers_to_s00_regslice_BREADY = S_AXI_bready;\n  assign s00_couplers_to_s00_regslice_RREADY = S_AXI_rready;\n  assign s00_couplers_to_s00_regslice_WDATA = S_AXI_wdata[511:0];\n  assign s00_couplers_to_s00_regslice_WLAST = S_AXI_wlast;\n  assign s00_couplers_to_s00_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign s00_couplers_to_s00_regslice_WVALID = S_AXI_wvalid;\n  assign s00_regslice_to_s00_couplers_ARREADY = M_AXI_arready;\n  assign s00_regslice_to_s00_couplers_AWREADY = M_AXI_awready;\n  assign s00_regslice_to_s00_couplers_BID = M_AXI_bid[6:0];\n  assign s00_regslice_to_s00_couplers_BRESP = M_AXI_bresp[1:0];\n  assign s00_regslice_to_s00_couplers_BVALID = M_AXI_bvalid;\n  assign s00_regslice_to_s00_couplers_RDATA = M_AXI_rdata[511:0];\n  assign s00_regslice_to_s00_couplers_RID = M_AXI_rid[6:0];\n  assign s00_regslice_to_s00_couplers_RLAST = M_AXI_rlast;\n  assign s00_regslice_to_s00_couplers_RRESP = M_AXI_rresp[1:0];\n  assign s00_regslice_to_s00_couplers_RVALID = M_AXI_rvalid;\n  assign s00_regslice_to_s00_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_s00_regslice_0 s00_regslice\n       (.aclk(S_ACLK_1),\n        .aresetn(S_ARESETN_1),\n        .m_axi_araddr(s00_regslice_to_s00_couplers_ARADDR),\n        .m_axi_arburst(s00_regslice_to_s00_couplers_ARBURST),\n        .m_axi_arcache(s00_regslice_to_s00_couplers_ARCACHE),\n        .m_axi_arid(s00_regslice_to_s00_couplers_ARID),\n        .m_axi_arlen(s00_regslice_to_s00_couplers_ARLEN),\n        .m_axi_arlock(s00_regslice_to_s00_couplers_ARLOCK),\n        .m_axi_arprot(s00_regslice_to_s00_couplers_ARPROT),\n        .m_axi_arqos(s00_regslice_to_s00_couplers_ARQOS),\n        .m_axi_arready(s00_regslice_to_s00_couplers_ARREADY),\n        .m_axi_arsize(s00_regslice_to_s00_couplers_ARSIZE),\n        .m_axi_arvalid(s00_regslice_to_s00_couplers_ARVALID),\n        .m_axi_awaddr(s00_regslice_to_s00_couplers_AWADDR),\n        .m_axi_awburst(s00_regslice_to_s00_couplers_AWBURST),\n        .m_axi_awcache(s00_regslice_to_s00_couplers_AWCACHE),\n        .m_axi_awid(s00_regslice_to_s00_couplers_AWID),\n        .m_axi_awlen(s00_regslice_to_s00_couplers_AWLEN),\n        .m_axi_awlock(s00_regslice_to_s00_couplers_AWLOCK),\n        .m_axi_awprot(s00_regslice_to_s00_couplers_AWPROT),\n        .m_axi_awqos(s00_regslice_to_s00_couplers_AWQOS),\n        .m_axi_awready(s00_regslice_to_s00_couplers_AWREADY),\n        .m_axi_awsize(s00_regslice_to_s00_couplers_AWSIZE),\n        .m_axi_awvalid(s00_regslice_to_s00_couplers_AWVALID),\n        .m_axi_bid(s00_regslice_to_s00_couplers_BID[5:0]),\n        .m_axi_bready(s00_regslice_to_s00_couplers_BREADY),\n        .m_axi_bresp(s00_regslice_to_s00_couplers_BRESP),\n        .m_axi_bvalid(s00_regslice_to_s00_couplers_BVALID),\n        .m_axi_rdata(s00_regslice_to_s00_couplers_RDATA),\n        .m_axi_rid(s00_regslice_to_s00_couplers_RID[5:0]),\n        .m_axi_rlast(s00_regslice_to_s00_couplers_RLAST),\n        .m_axi_rready(s00_regslice_to_s00_couplers_RREADY),\n        .m_axi_rresp(s00_regslice_to_s00_couplers_RRESP),\n        .m_axi_rvalid(s00_regslice_to_s00_couplers_RVALID),\n        .m_axi_wdata(s00_regslice_to_s00_couplers_WDATA),\n        .m_axi_wlast(s00_regslice_to_s00_couplers_WLAST),\n        .m_axi_wready(s00_regslice_to_s00_couplers_WREADY),\n        .m_axi_wstrb(s00_regslice_to_s00_couplers_WSTRB),\n        .m_axi_wvalid(s00_regslice_to_s00_couplers_WVALID),\n        .s_axi_araddr(s00_couplers_to_s00_regslice_ARADDR),\n        .s_axi_arburst(s00_couplers_to_s00_regslice_ARBURST),\n        .s_axi_arcache(s00_couplers_to_s00_regslice_ARCACHE),\n        .s_axi_arid(s00_couplers_to_s00_regslice_ARID),\n        .s_axi_arlen(s00_couplers_to_s00_regslice_ARLEN),\n        .s_axi_arlock(s00_couplers_to_s00_regslice_ARLOCK),\n        .s_axi_arprot(s00_couplers_to_s00_regslice_ARPROT),\n        .s_axi_arqos(s00_couplers_to_s00_regslice_ARQOS),\n        .s_axi_arready(s00_couplers_to_s00_regslice_ARREADY),\n        .s_axi_arregion(s00_couplers_to_s00_regslice_ARREGION),\n        .s_axi_arsize(s00_couplers_to_s00_regslice_ARSIZE),\n        .s_axi_arvalid(s00_couplers_to_s00_regslice_ARVALID),\n        .s_axi_awaddr(s00_couplers_to_s00_regslice_AWADDR),\n        .s_axi_awburst(s00_couplers_to_s00_regslice_AWBURST),\n        .s_axi_awcache(s00_couplers_to_s00_regslice_AWCACHE),\n        .s_axi_awid(s00_couplers_to_s00_regslice_AWID),\n        .s_axi_awlen(s00_couplers_to_s00_regslice_AWLEN),\n        .s_axi_awlock(s00_couplers_to_s00_regslice_AWLOCK),\n        .s_axi_awprot(s00_couplers_to_s00_regslice_AWPROT),\n        .s_axi_awqos(s00_couplers_to_s00_regslice_AWQOS),\n        .s_axi_awready(s00_couplers_to_s00_regslice_AWREADY),\n        .s_axi_awregion(s00_couplers_to_s00_regslice_AWREGION),\n        .s_axi_awsize(s00_couplers_to_s00_regslice_AWSIZE),\n        .s_axi_awvalid(s00_couplers_to_s00_regslice_AWVALID),\n        .s_axi_bid(s00_couplers_to_s00_regslice_BID),\n        .s_axi_bready(s00_couplers_to_s00_regslice_BREADY),\n        .s_axi_bresp(s00_couplers_to_s00_regslice_BRESP),\n        .s_axi_bvalid(s00_couplers_to_s00_regslice_BVALID),\n        .s_axi_rdata(s00_couplers_to_s00_regslice_RDATA),\n        .s_axi_rid(s00_couplers_to_s00_regslice_RID),\n        .s_axi_rlast(s00_couplers_to_s00_regslice_RLAST),\n        .s_axi_rready(s00_couplers_to_s00_regslice_RREADY),\n        .s_axi_rresp(s00_couplers_to_s00_regslice_RRESP),\n        .s_axi_rvalid(s00_couplers_to_s00_regslice_RVALID),\n        .s_axi_wdata(s00_couplers_to_s00_regslice_WDATA),\n        .s_axi_wlast(s00_couplers_to_s00_regslice_WLAST),\n        .s_axi_wready(s00_couplers_to_s00_regslice_WREADY),\n        .s_axi_wstrb(s00_couplers_to_s00_regslice_WSTRB),\n        .s_axi_wvalid(s00_couplers_to_s00_regslice_WVALID));\nendmodule\n\nmodule s01_couplers_imp_GSTXQ8\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [5:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [5:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [5:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [5:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [5:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [5:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire S_ACLK_1;\n  wire S_ARESETN_1;\n  wire [63:0]s01_couplers_to_s01_regslice_ARADDR;\n  wire [1:0]s01_couplers_to_s01_regslice_ARBURST;\n  wire [3:0]s01_couplers_to_s01_regslice_ARCACHE;\n  wire [5:0]s01_couplers_to_s01_regslice_ARID;\n  wire [7:0]s01_couplers_to_s01_regslice_ARLEN;\n  wire [0:0]s01_couplers_to_s01_regslice_ARLOCK;\n  wire [2:0]s01_couplers_to_s01_regslice_ARPROT;\n  wire [3:0]s01_couplers_to_s01_regslice_ARQOS;\n  wire s01_couplers_to_s01_regslice_ARREADY;\n  wire [3:0]s01_couplers_to_s01_regslice_ARREGION;\n  wire [2:0]s01_couplers_to_s01_regslice_ARSIZE;\n  wire s01_couplers_to_s01_regslice_ARVALID;\n  wire [63:0]s01_couplers_to_s01_regslice_AWADDR;\n  wire [1:0]s01_couplers_to_s01_regslice_AWBURST;\n  wire [3:0]s01_couplers_to_s01_regslice_AWCACHE;\n  wire [5:0]s01_couplers_to_s01_regslice_AWID;\n  wire [7:0]s01_couplers_to_s01_regslice_AWLEN;\n  wire [0:0]s01_couplers_to_s01_regslice_AWLOCK;\n  wire [2:0]s01_couplers_to_s01_regslice_AWPROT;\n  wire [3:0]s01_couplers_to_s01_regslice_AWQOS;\n  wire s01_couplers_to_s01_regslice_AWREADY;\n  wire [3:0]s01_couplers_to_s01_regslice_AWREGION;\n  wire [2:0]s01_couplers_to_s01_regslice_AWSIZE;\n  wire s01_couplers_to_s01_regslice_AWVALID;\n  wire [5:0]s01_couplers_to_s01_regslice_BID;\n  wire s01_couplers_to_s01_regslice_BREADY;\n  wire [1:0]s01_couplers_to_s01_regslice_BRESP;\n  wire s01_couplers_to_s01_regslice_BVALID;\n  wire [511:0]s01_couplers_to_s01_regslice_RDATA;\n  wire [5:0]s01_couplers_to_s01_regslice_RID;\n  wire s01_couplers_to_s01_regslice_RLAST;\n  wire s01_couplers_to_s01_regslice_RREADY;\n  wire [1:0]s01_couplers_to_s01_regslice_RRESP;\n  wire s01_couplers_to_s01_regslice_RVALID;\n  wire [511:0]s01_couplers_to_s01_regslice_WDATA;\n  wire s01_couplers_to_s01_regslice_WLAST;\n  wire s01_couplers_to_s01_regslice_WREADY;\n  wire [63:0]s01_couplers_to_s01_regslice_WSTRB;\n  wire s01_couplers_to_s01_regslice_WVALID;\n  wire [63:0]s01_regslice_to_s01_couplers_ARADDR;\n  wire [1:0]s01_regslice_to_s01_couplers_ARBURST;\n  wire [3:0]s01_regslice_to_s01_couplers_ARCACHE;\n  wire [5:0]s01_regslice_to_s01_couplers_ARID;\n  wire [7:0]s01_regslice_to_s01_couplers_ARLEN;\n  wire [0:0]s01_regslice_to_s01_couplers_ARLOCK;\n  wire [2:0]s01_regslice_to_s01_couplers_ARPROT;\n  wire [3:0]s01_regslice_to_s01_couplers_ARQOS;\n  wire s01_regslice_to_s01_couplers_ARREADY;\n  wire [2:0]s01_regslice_to_s01_couplers_ARSIZE;\n  wire s01_regslice_to_s01_couplers_ARVALID;\n  wire [63:0]s01_regslice_to_s01_couplers_AWADDR;\n  wire [1:0]s01_regslice_to_s01_couplers_AWBURST;\n  wire [3:0]s01_regslice_to_s01_couplers_AWCACHE;\n  wire [5:0]s01_regslice_to_s01_couplers_AWID;\n  wire [7:0]s01_regslice_to_s01_couplers_AWLEN;\n  wire [0:0]s01_regslice_to_s01_couplers_AWLOCK;\n  wire [2:0]s01_regslice_to_s01_couplers_AWPROT;\n  wire [3:0]s01_regslice_to_s01_couplers_AWQOS;\n  wire s01_regslice_to_s01_couplers_AWREADY;\n  wire [2:0]s01_regslice_to_s01_couplers_AWSIZE;\n  wire s01_regslice_to_s01_couplers_AWVALID;\n  wire [6:0]s01_regslice_to_s01_couplers_BID;\n  wire s01_regslice_to_s01_couplers_BREADY;\n  wire [1:0]s01_regslice_to_s01_couplers_BRESP;\n  wire s01_regslice_to_s01_couplers_BVALID;\n  wire [511:0]s01_regslice_to_s01_couplers_RDATA;\n  wire [6:0]s01_regslice_to_s01_couplers_RID;\n  wire s01_regslice_to_s01_couplers_RLAST;\n  wire s01_regslice_to_s01_couplers_RREADY;\n  wire [1:0]s01_regslice_to_s01_couplers_RRESP;\n  wire s01_regslice_to_s01_couplers_RVALID;\n  wire [511:0]s01_regslice_to_s01_couplers_WDATA;\n  wire s01_regslice_to_s01_couplers_WLAST;\n  wire s01_regslice_to_s01_couplers_WREADY;\n  wire [63:0]s01_regslice_to_s01_couplers_WSTRB;\n  wire s01_regslice_to_s01_couplers_WVALID;\n\n  assign M_AXI_araddr[63:0] = s01_regslice_to_s01_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = s01_regslice_to_s01_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = s01_regslice_to_s01_couplers_ARCACHE;\n  assign M_AXI_arid[5:0] = s01_regslice_to_s01_couplers_ARID;\n  assign M_AXI_arlen[7:0] = s01_regslice_to_s01_couplers_ARLEN;\n  assign M_AXI_arlock[0] = s01_regslice_to_s01_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = s01_regslice_to_s01_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = s01_regslice_to_s01_couplers_ARQOS;\n  assign M_AXI_arsize[2:0] = s01_regslice_to_s01_couplers_ARSIZE;\n  assign M_AXI_arvalid = s01_regslice_to_s01_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = s01_regslice_to_s01_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = s01_regslice_to_s01_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = s01_regslice_to_s01_couplers_AWCACHE;\n  assign M_AXI_awid[5:0] = s01_regslice_to_s01_couplers_AWID;\n  assign M_AXI_awlen[7:0] = s01_regslice_to_s01_couplers_AWLEN;\n  assign M_AXI_awlock[0] = s01_regslice_to_s01_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = s01_regslice_to_s01_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = s01_regslice_to_s01_couplers_AWQOS;\n  assign M_AXI_awsize[2:0] = s01_regslice_to_s01_couplers_AWSIZE;\n  assign M_AXI_awvalid = s01_regslice_to_s01_couplers_AWVALID;\n  assign M_AXI_bready = s01_regslice_to_s01_couplers_BREADY;\n  assign M_AXI_rready = s01_regslice_to_s01_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = s01_regslice_to_s01_couplers_WDATA;\n  assign M_AXI_wlast = s01_regslice_to_s01_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = s01_regslice_to_s01_couplers_WSTRB;\n  assign M_AXI_wvalid = s01_regslice_to_s01_couplers_WVALID;\n  assign S_ACLK_1 = S_ACLK;\n  assign S_ARESETN_1 = S_ARESETN;\n  assign S_AXI_arready = s01_couplers_to_s01_regslice_ARREADY;\n  assign S_AXI_awready = s01_couplers_to_s01_regslice_AWREADY;\n  assign S_AXI_bid[5:0] = s01_couplers_to_s01_regslice_BID;\n  assign S_AXI_bresp[1:0] = s01_couplers_to_s01_regslice_BRESP;\n  assign S_AXI_bvalid = s01_couplers_to_s01_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = s01_couplers_to_s01_regslice_RDATA;\n  assign S_AXI_rid[5:0] = s01_couplers_to_s01_regslice_RID;\n  assign S_AXI_rlast = s01_couplers_to_s01_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = s01_couplers_to_s01_regslice_RRESP;\n  assign S_AXI_rvalid = s01_couplers_to_s01_regslice_RVALID;\n  assign S_AXI_wready = s01_couplers_to_s01_regslice_WREADY;\n  assign s01_couplers_to_s01_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign s01_couplers_to_s01_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign s01_couplers_to_s01_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign s01_couplers_to_s01_regslice_ARID = S_AXI_arid[5:0];\n  assign s01_couplers_to_s01_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign s01_couplers_to_s01_regslice_ARLOCK = S_AXI_arlock[0];\n  assign s01_couplers_to_s01_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign s01_couplers_to_s01_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign s01_couplers_to_s01_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign s01_couplers_to_s01_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign s01_couplers_to_s01_regslice_ARVALID = S_AXI_arvalid;\n  assign s01_couplers_to_s01_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign s01_couplers_to_s01_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign s01_couplers_to_s01_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign s01_couplers_to_s01_regslice_AWID = S_AXI_awid[5:0];\n  assign s01_couplers_to_s01_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign s01_couplers_to_s01_regslice_AWLOCK = S_AXI_awlock[0];\n  assign s01_couplers_to_s01_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign s01_couplers_to_s01_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign s01_couplers_to_s01_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign s01_couplers_to_s01_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign s01_couplers_to_s01_regslice_AWVALID = S_AXI_awvalid;\n  assign s01_couplers_to_s01_regslice_BREADY = S_AXI_bready;\n  assign s01_couplers_to_s01_regslice_RREADY = S_AXI_rready;\n  assign s01_couplers_to_s01_regslice_WDATA = S_AXI_wdata[511:0];\n  assign s01_couplers_to_s01_regslice_WLAST = S_AXI_wlast;\n  assign s01_couplers_to_s01_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign s01_couplers_to_s01_regslice_WVALID = S_AXI_wvalid;\n  assign s01_regslice_to_s01_couplers_ARREADY = M_AXI_arready;\n  assign s01_regslice_to_s01_couplers_AWREADY = M_AXI_awready;\n  assign s01_regslice_to_s01_couplers_BID = M_AXI_bid[6:0];\n  assign s01_regslice_to_s01_couplers_BRESP = M_AXI_bresp[1:0];\n  assign s01_regslice_to_s01_couplers_BVALID = M_AXI_bvalid;\n  assign s01_regslice_to_s01_couplers_RDATA = M_AXI_rdata[511:0];\n  assign s01_regslice_to_s01_couplers_RID = M_AXI_rid[6:0];\n  assign s01_regslice_to_s01_couplers_RLAST = M_AXI_rlast;\n  assign s01_regslice_to_s01_couplers_RRESP = M_AXI_rresp[1:0];\n  assign s01_regslice_to_s01_couplers_RVALID = M_AXI_rvalid;\n  assign s01_regslice_to_s01_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_s01_regslice_0 s01_regslice\n       (.aclk(S_ACLK_1),\n        .aresetn(S_ARESETN_1),\n        .m_axi_araddr(s01_regslice_to_s01_couplers_ARADDR),\n        .m_axi_arburst(s01_regslice_to_s01_couplers_ARBURST),\n        .m_axi_arcache(s01_regslice_to_s01_couplers_ARCACHE),\n        .m_axi_arid(s01_regslice_to_s01_couplers_ARID),\n        .m_axi_arlen(s01_regslice_to_s01_couplers_ARLEN),\n        .m_axi_arlock(s01_regslice_to_s01_couplers_ARLOCK),\n        .m_axi_arprot(s01_regslice_to_s01_couplers_ARPROT),\n        .m_axi_arqos(s01_regslice_to_s01_couplers_ARQOS),\n        .m_axi_arready(s01_regslice_to_s01_couplers_ARREADY),\n        .m_axi_arsize(s01_regslice_to_s01_couplers_ARSIZE),\n        .m_axi_arvalid(s01_regslice_to_s01_couplers_ARVALID),\n        .m_axi_awaddr(s01_regslice_to_s01_couplers_AWADDR),\n        .m_axi_awburst(s01_regslice_to_s01_couplers_AWBURST),\n        .m_axi_awcache(s01_regslice_to_s01_couplers_AWCACHE),\n        .m_axi_awid(s01_regslice_to_s01_couplers_AWID),\n        .m_axi_awlen(s01_regslice_to_s01_couplers_AWLEN),\n        .m_axi_awlock(s01_regslice_to_s01_couplers_AWLOCK),\n        .m_axi_awprot(s01_regslice_to_s01_couplers_AWPROT),\n        .m_axi_awqos(s01_regslice_to_s01_couplers_AWQOS),\n        .m_axi_awready(s01_regslice_to_s01_couplers_AWREADY),\n        .m_axi_awsize(s01_regslice_to_s01_couplers_AWSIZE),\n        .m_axi_awvalid(s01_regslice_to_s01_couplers_AWVALID),\n        .m_axi_bid(s01_regslice_to_s01_couplers_BID[5:0]),\n        .m_axi_bready(s01_regslice_to_s01_couplers_BREADY),\n        .m_axi_bresp(s01_regslice_to_s01_couplers_BRESP),\n        .m_axi_bvalid(s01_regslice_to_s01_couplers_BVALID),\n        .m_axi_rdata(s01_regslice_to_s01_couplers_RDATA),\n        .m_axi_rid(s01_regslice_to_s01_couplers_RID[5:0]),\n        .m_axi_rlast(s01_regslice_to_s01_couplers_RLAST),\n        .m_axi_rready(s01_regslice_to_s01_couplers_RREADY),\n        .m_axi_rresp(s01_regslice_to_s01_couplers_RRESP),\n        .m_axi_rvalid(s01_regslice_to_s01_couplers_RVALID),\n        .m_axi_wdata(s01_regslice_to_s01_couplers_WDATA),\n        .m_axi_wlast(s01_regslice_to_s01_couplers_WLAST),\n        .m_axi_wready(s01_regslice_to_s01_couplers_WREADY),\n        .m_axi_wstrb(s01_regslice_to_s01_couplers_WSTRB),\n        .m_axi_wvalid(s01_regslice_to_s01_couplers_WVALID),\n        .s_axi_araddr(s01_couplers_to_s01_regslice_ARADDR),\n        .s_axi_arburst(s01_couplers_to_s01_regslice_ARBURST),\n        .s_axi_arcache(s01_couplers_to_s01_regslice_ARCACHE),\n        .s_axi_arid(s01_couplers_to_s01_regslice_ARID),\n        .s_axi_arlen(s01_couplers_to_s01_regslice_ARLEN),\n        .s_axi_arlock(s01_couplers_to_s01_regslice_ARLOCK),\n        .s_axi_arprot(s01_couplers_to_s01_regslice_ARPROT),\n        .s_axi_arqos(s01_couplers_to_s01_regslice_ARQOS),\n        .s_axi_arready(s01_couplers_to_s01_regslice_ARREADY),\n        .s_axi_arregion(s01_couplers_to_s01_regslice_ARREGION),\n        .s_axi_arsize(s01_couplers_to_s01_regslice_ARSIZE),\n        .s_axi_arvalid(s01_couplers_to_s01_regslice_ARVALID),\n        .s_axi_awaddr(s01_couplers_to_s01_regslice_AWADDR),\n        .s_axi_awburst(s01_couplers_to_s01_regslice_AWBURST),\n        .s_axi_awcache(s01_couplers_to_s01_regslice_AWCACHE),\n        .s_axi_awid(s01_couplers_to_s01_regslice_AWID),\n        .s_axi_awlen(s01_couplers_to_s01_regslice_AWLEN),\n        .s_axi_awlock(s01_couplers_to_s01_regslice_AWLOCK),\n        .s_axi_awprot(s01_couplers_to_s01_regslice_AWPROT),\n        .s_axi_awqos(s01_couplers_to_s01_regslice_AWQOS),\n        .s_axi_awready(s01_couplers_to_s01_regslice_AWREADY),\n        .s_axi_awregion(s01_couplers_to_s01_regslice_AWREGION),\n        .s_axi_awsize(s01_couplers_to_s01_regslice_AWSIZE),\n        .s_axi_awvalid(s01_couplers_to_s01_regslice_AWVALID),\n        .s_axi_bid(s01_couplers_to_s01_regslice_BID),\n        .s_axi_bready(s01_couplers_to_s01_regslice_BREADY),\n        .s_axi_bresp(s01_couplers_to_s01_regslice_BRESP),\n        .s_axi_bvalid(s01_couplers_to_s01_regslice_BVALID),\n        .s_axi_rdata(s01_couplers_to_s01_regslice_RDATA),\n        .s_axi_rid(s01_couplers_to_s01_regslice_RID),\n        .s_axi_rlast(s01_couplers_to_s01_regslice_RLAST),\n        .s_axi_rready(s01_couplers_to_s01_regslice_RREADY),\n        .s_axi_rresp(s01_couplers_to_s01_regslice_RRESP),\n        .s_axi_rvalid(s01_couplers_to_s01_regslice_RVALID),\n        .s_axi_wdata(s01_couplers_to_s01_regslice_WDATA),\n        .s_axi_wlast(s01_couplers_to_s01_regslice_WLAST),\n        .s_axi_wready(s01_couplers_to_s01_regslice_WREADY),\n        .s_axi_wstrb(s01_couplers_to_s01_regslice_WSTRB),\n        .s_axi_wvalid(s01_couplers_to_s01_regslice_WVALID));\nendmodule\n", "num_lines": 5426}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020\n//Date        : Wed Dec 15 00:42:18 2021\n//Host        : a-21awsprq4sria running 64-bit Amazon Linux release 2 (Karoo)\n//Command     : generate_target cl_axi_interconnect.bd\n//Design      : cl_axi_interconnect\n//Purpose     : IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=cl_axi_interconnect,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=14,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}\" *) (* HW_HANDOFF = \"cl_axi_interconnect.hwdef\" *) \nmodule cl_axi_interconnect\n   (ACLK,\n    ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.ACLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF S00_AXI:M00_AXI:M01_AXI:M02_AXI:M03_AXI:S01_AXI, ASSOCIATED_RESET ARESETN, CLK_DOMAIN cl_axi_interconnect_ACLK, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input ACLK;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.ARESETN RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW\" *) input ARESETN;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M00_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M00_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARBURST\" *) output [1:0]M00_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE\" *) output [3:0]M00_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARID\" *) output [6:0]M00_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLEN\" *) output [7:0]M00_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK\" *) output [0:0]M00_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARPROT\" *) output [2:0]M00_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARQOS\" *) output [3:0]M00_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREADY\" *) input M00_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREGION\" *) output [3:0]M00_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE\" *) output [2:0]M00_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARVALID\" *) output M00_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWADDR\" *) output [63:0]M00_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWBURST\" *) output [1:0]M00_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE\" *) output [3:0]M00_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWID\" *) output [6:0]M00_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLEN\" *) output [7:0]M00_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK\" *) output [0:0]M00_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWPROT\" *) output [2:0]M00_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWQOS\" *) output [3:0]M00_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREADY\" *) input M00_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREGION\" *) output [3:0]M00_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE\" *) output [2:0]M00_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWVALID\" *) output M00_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BID\" *) input [6:0]M00_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BREADY\" *) output M00_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BRESP\" *) input [1:0]M00_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BVALID\" *) input M00_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RDATA\" *) input [511:0]M00_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RID\" *) input [6:0]M00_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RLAST\" *) input M00_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RREADY\" *) output M00_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RRESP\" *) input [1:0]M00_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RVALID\" *) input M00_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WDATA\" *) output [511:0]M00_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WLAST\" *) output M00_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WREADY\" *) input M00_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WSTRB\" *) output [63:0]M00_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WVALID\" *) output M00_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M01_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M01_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARBURST\" *) output [1:0]M01_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE\" *) output [3:0]M01_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARID\" *) output [6:0]M01_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARLEN\" *) output [7:0]M01_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK\" *) output [0:0]M01_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARPROT\" *) output [2:0]M01_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARQOS\" *) output [3:0]M01_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARREADY\" *) input M01_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARREGION\" *) output [3:0]M01_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE\" *) output [2:0]M01_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARVALID\" *) output M01_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWADDR\" *) output [63:0]M01_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWBURST\" *) output [1:0]M01_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE\" *) output [3:0]M01_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWID\" *) output [6:0]M01_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWLEN\" *) output [7:0]M01_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK\" *) output [0:0]M01_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWPROT\" *) output [2:0]M01_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWQOS\" *) output [3:0]M01_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWREADY\" *) input M01_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWREGION\" *) output [3:0]M01_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE\" *) output [2:0]M01_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWVALID\" *) output M01_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BID\" *) input [6:0]M01_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BREADY\" *) output M01_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BRESP\" *) input [1:0]M01_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BVALID\" *) input M01_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RDATA\" *) input [511:0]M01_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RID\" *) input [6:0]M01_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RLAST\" *) input M01_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RREADY\" *) output M01_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RRESP\" *) input [1:0]M01_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RVALID\" *) input M01_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WDATA\" *) output [511:0]M01_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WLAST\" *) output M01_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WREADY\" *) input M01_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WSTRB\" *) output [63:0]M01_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WVALID\" *) output M01_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M02_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M02_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARBURST\" *) output [1:0]M02_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE\" *) output [3:0]M02_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARID\" *) output [6:0]M02_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARLEN\" *) output [7:0]M02_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK\" *) output [0:0]M02_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARPROT\" *) output [2:0]M02_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARQOS\" *) output [3:0]M02_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARREADY\" *) input M02_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARREGION\" *) output [3:0]M02_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE\" *) output [2:0]M02_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARVALID\" *) output M02_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWADDR\" *) output [63:0]M02_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWBURST\" *) output [1:0]M02_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE\" *) output [3:0]M02_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWID\" *) output [6:0]M02_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWLEN\" *) output [7:0]M02_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK\" *) output [0:0]M02_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWPROT\" *) output [2:0]M02_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWQOS\" *) output [3:0]M02_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWREADY\" *) input M02_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWREGION\" *) output [3:0]M02_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE\" *) output [2:0]M02_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWVALID\" *) output M02_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BID\" *) input [6:0]M02_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BREADY\" *) output M02_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BRESP\" *) input [1:0]M02_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BVALID\" *) input M02_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RDATA\" *) input [511:0]M02_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RID\" *) input [6:0]M02_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RLAST\" *) input M02_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RREADY\" *) output M02_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RRESP\" *) input [1:0]M02_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RVALID\" *) input M02_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WDATA\" *) output [511:0]M02_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WLAST\" *) output M02_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WREADY\" *) input M02_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WSTRB\" *) output [63:0]M02_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WVALID\" *) output M02_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M03_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M03_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARBURST\" *) output [1:0]M03_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE\" *) output [3:0]M03_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARID\" *) output [6:0]M03_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARLEN\" *) output [7:0]M03_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK\" *) output [0:0]M03_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARPROT\" *) output [2:0]M03_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARQOS\" *) output [3:0]M03_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARREADY\" *) input M03_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARREGION\" *) output [3:0]M03_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE\" *) output [2:0]M03_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARVALID\" *) output M03_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWADDR\" *) output [63:0]M03_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWBURST\" *) output [1:0]M03_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE\" *) output [3:0]M03_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWID\" *) output [6:0]M03_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWLEN\" *) output [7:0]M03_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK\" *) output [0:0]M03_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWPROT\" *) output [2:0]M03_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWQOS\" *) output [3:0]M03_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWREADY\" *) input M03_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWREGION\" *) output [3:0]M03_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE\" *) output [2:0]M03_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWVALID\" *) output M03_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BID\" *) input [6:0]M03_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BREADY\" *) output M03_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BRESP\" *) input [1:0]M03_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BVALID\" *) input M03_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RDATA\" *) input [511:0]M03_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RID\" *) input [6:0]M03_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RLAST\" *) input M03_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RREADY\" *) output M03_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RRESP\" *) input [1:0]M03_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RVALID\" *) input M03_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WDATA\" *) output [511:0]M03_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WLAST\" *) output M03_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WREADY\" *) input M03_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WSTRB\" *) output [63:0]M03_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WVALID\" *) output M03_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S00_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 6, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 32, NUM_READ_THREADS 16, NUM_WRITE_OUTSTANDING 32, NUM_WRITE_THREADS 16, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) input [63:0]S00_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARBURST\" *) input [1:0]S00_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE\" *) input [3:0]S00_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARID\" *) input [5:0]S00_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLEN\" *) input [7:0]S00_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK\" *) input [0:0]S00_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARPROT\" *) input [2:0]S00_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARQOS\" *) input [3:0]S00_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREADY\" *) output S00_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREGION\" *) input [3:0]S00_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE\" *) input [2:0]S00_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARVALID\" *) input S00_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWADDR\" *) input [63:0]S00_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWBURST\" *) input [1:0]S00_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE\" *) input [3:0]S00_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWID\" *) input [5:0]S00_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLEN\" *) input [7:0]S00_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK\" *) input [0:0]S00_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWPROT\" *) input [2:0]S00_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWQOS\" *) input [3:0]S00_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREADY\" *) output S00_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREGION\" *) input [3:0]S00_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE\" *) input [2:0]S00_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWVALID\" *) input S00_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BID\" *) output [5:0]S00_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BREADY\" *) input S00_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BRESP\" *) output [1:0]S00_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BVALID\" *) output S00_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RDATA\" *) output [511:0]S00_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RID\" *) output [5:0]S00_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RLAST\" *) output S00_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RREADY\" *) input S00_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RRESP\" *) output [1:0]S00_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RVALID\" *) output S00_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WDATA\" *) input [511:0]S00_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WLAST\" *) input S00_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WREADY\" *) output S00_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WSTRB\" *) input [63:0]S00_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WVALID\" *) input S00_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S01_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 6, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 32, NUM_READ_THREADS 16, NUM_WRITE_OUTSTANDING 32, NUM_WRITE_THREADS 16, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) input [63:0]S01_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARBURST\" *) input [1:0]S01_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE\" *) input [3:0]S01_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARID\" *) input [5:0]S01_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARLEN\" *) input [7:0]S01_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK\" *) input [0:0]S01_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARPROT\" *) input [2:0]S01_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARQOS\" *) input [3:0]S01_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARREADY\" *) output S01_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARREGION\" *) input [3:0]S01_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE\" *) input [2:0]S01_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARVALID\" *) input S01_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWADDR\" *) input [63:0]S01_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWBURST\" *) input [1:0]S01_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE\" *) input [3:0]S01_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWID\" *) input [5:0]S01_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWLEN\" *) input [7:0]S01_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK\" *) input [0:0]S01_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWPROT\" *) input [2:0]S01_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWQOS\" *) input [3:0]S01_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWREADY\" *) output S01_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWREGION\" *) input [3:0]S01_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE\" *) input [2:0]S01_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWVALID\" *) input S01_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BID\" *) output [5:0]S01_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BREADY\" *) input S01_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BRESP\" *) output [1:0]S01_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BVALID\" *) output S01_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RDATA\" *) output [511:0]S01_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RID\" *) output [5:0]S01_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RLAST\" *) output S01_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RREADY\" *) input S01_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RRESP\" *) output [1:0]S01_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RVALID\" *) output S01_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WDATA\" *) input [511:0]S01_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WLAST\" *) input S01_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WREADY\" *) output S01_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WSTRB\" *) input [63:0]S01_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WVALID\" *) input S01_AXI_wvalid;\n\n  wire ACLK_1;\n  wire ARESETN_1;\n  wire [63:0]S00_AXI_1_ARADDR;\n  wire [1:0]S00_AXI_1_ARBURST;\n  wire [3:0]S00_AXI_1_ARCACHE;\n  wire [5:0]S00_AXI_1_ARID;\n  wire [7:0]S00_AXI_1_ARLEN;\n  wire [0:0]S00_AXI_1_ARLOCK;\n  wire [2:0]S00_AXI_1_ARPROT;\n  wire [3:0]S00_AXI_1_ARQOS;\n  wire S00_AXI_1_ARREADY;\n  wire [3:0]S00_AXI_1_ARREGION;\n  wire [2:0]S00_AXI_1_ARSIZE;\n  wire S00_AXI_1_ARVALID;\n  wire [63:0]S00_AXI_1_AWADDR;\n  wire [1:0]S00_AXI_1_AWBURST;\n  wire [3:0]S00_AXI_1_AWCACHE;\n  wire [5:0]S00_AXI_1_AWID;\n  wire [7:0]S00_AXI_1_AWLEN;\n  wire [0:0]S00_AXI_1_AWLOCK;\n  wire [2:0]S00_AXI_1_AWPROT;\n  wire [3:0]S00_AXI_1_AWQOS;\n  wire S00_AXI_1_AWREADY;\n  wire [3:0]S00_AXI_1_AWREGION;\n  wire [2:0]S00_AXI_1_AWSIZE;\n  wire S00_AXI_1_AWVALID;\n  wire [5:0]S00_AXI_1_BID;\n  wire S00_AXI_1_BREADY;\n  wire [1:0]S00_AXI_1_BRESP;\n  wire S00_AXI_1_BVALID;\n  wire [511:0]S00_AXI_1_RDATA;\n  wire [5:0]S00_AXI_1_RID;\n  wire S00_AXI_1_RLAST;\n  wire S00_AXI_1_RREADY;\n  wire [1:0]S00_AXI_1_RRESP;\n  wire S00_AXI_1_RVALID;\n  wire [511:0]S00_AXI_1_WDATA;\n  wire S00_AXI_1_WLAST;\n  wire S00_AXI_1_WREADY;\n  wire [63:0]S00_AXI_1_WSTRB;\n  wire S00_AXI_1_WVALID;\n  wire [63:0]S01_AXI_1_ARADDR;\n  wire [1:0]S01_AXI_1_ARBURST;\n  wire [3:0]S01_AXI_1_ARCACHE;\n  wire [5:0]S01_AXI_1_ARID;\n  wire [7:0]S01_AXI_1_ARLEN;\n  wire [0:0]S01_AXI_1_ARLOCK;\n  wire [2:0]S01_AXI_1_ARPROT;\n  wire [3:0]S01_AXI_1_ARQOS;\n  wire S01_AXI_1_ARREADY;\n  wire [3:0]S01_AXI_1_ARREGION;\n  wire [2:0]S01_AXI_1_ARSIZE;\n  wire S01_AXI_1_ARVALID;\n  wire [63:0]S01_AXI_1_AWADDR;\n  wire [1:0]S01_AXI_1_AWBURST;\n  wire [3:0]S01_AXI_1_AWCACHE;\n  wire [5:0]S01_AXI_1_AWID;\n  wire [7:0]S01_AXI_1_AWLEN;\n  wire [0:0]S01_AXI_1_AWLOCK;\n  wire [2:0]S01_AXI_1_AWPROT;\n  wire [3:0]S01_AXI_1_AWQOS;\n  wire S01_AXI_1_AWREADY;\n  wire [3:0]S01_AXI_1_AWREGION;\n  wire [2:0]S01_AXI_1_AWSIZE;\n  wire S01_AXI_1_AWVALID;\n  wire [5:0]S01_AXI_1_BID;\n  wire S01_AXI_1_BREADY;\n  wire [1:0]S01_AXI_1_BRESP;\n  wire S01_AXI_1_BVALID;\n  wire [511:0]S01_AXI_1_RDATA;\n  wire [5:0]S01_AXI_1_RID;\n  wire S01_AXI_1_RLAST;\n  wire S01_AXI_1_RREADY;\n  wire [1:0]S01_AXI_1_RRESP;\n  wire S01_AXI_1_RVALID;\n  wire [511:0]S01_AXI_1_WDATA;\n  wire S01_AXI_1_WLAST;\n  wire S01_AXI_1_WREADY;\n  wire [63:0]S01_AXI_1_WSTRB;\n  wire S01_AXI_1_WVALID;\n  wire [63:0]axi_interconnect_0_M00_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M00_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M00_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M00_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M00_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M00_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARQOS;\n  wire axi_interconnect_0_M00_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M00_AXI_ARSIZE;\n  wire axi_interconnect_0_M00_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M00_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M00_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M00_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M00_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M00_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M00_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWQOS;\n  wire axi_interconnect_0_M00_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M00_AXI_AWSIZE;\n  wire axi_interconnect_0_M00_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M00_AXI_BID;\n  wire axi_interconnect_0_M00_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M00_AXI_BRESP;\n  wire axi_interconnect_0_M00_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M00_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M00_AXI_RID;\n  wire axi_interconnect_0_M00_AXI_RLAST;\n  wire axi_interconnect_0_M00_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M00_AXI_RRESP;\n  wire axi_interconnect_0_M00_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M00_AXI_WDATA;\n  wire axi_interconnect_0_M00_AXI_WLAST;\n  wire axi_interconnect_0_M00_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M00_AXI_WSTRB;\n  wire axi_interconnect_0_M00_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M01_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M01_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M01_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M01_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M01_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M01_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARQOS;\n  wire axi_interconnect_0_M01_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M01_AXI_ARSIZE;\n  wire axi_interconnect_0_M01_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M01_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M01_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M01_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M01_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M01_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M01_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWQOS;\n  wire axi_interconnect_0_M01_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M01_AXI_AWSIZE;\n  wire axi_interconnect_0_M01_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M01_AXI_BID;\n  wire axi_interconnect_0_M01_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M01_AXI_BRESP;\n  wire axi_interconnect_0_M01_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M01_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M01_AXI_RID;\n  wire axi_interconnect_0_M01_AXI_RLAST;\n  wire axi_interconnect_0_M01_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M01_AXI_RRESP;\n  wire axi_interconnect_0_M01_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M01_AXI_WDATA;\n  wire axi_interconnect_0_M01_AXI_WLAST;\n  wire axi_interconnect_0_M01_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M01_AXI_WSTRB;\n  wire axi_interconnect_0_M01_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M02_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M02_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M02_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M02_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M02_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M02_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARQOS;\n  wire axi_interconnect_0_M02_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M02_AXI_ARSIZE;\n  wire axi_interconnect_0_M02_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M02_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M02_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M02_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M02_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M02_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M02_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWQOS;\n  wire axi_interconnect_0_M02_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M02_AXI_AWSIZE;\n  wire axi_interconnect_0_M02_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M02_AXI_BID;\n  wire axi_interconnect_0_M02_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M02_AXI_BRESP;\n  wire axi_interconnect_0_M02_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M02_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M02_AXI_RID;\n  wire axi_interconnect_0_M02_AXI_RLAST;\n  wire axi_interconnect_0_M02_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M02_AXI_RRESP;\n  wire axi_interconnect_0_M02_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M02_AXI_WDATA;\n  wire axi_interconnect_0_M02_AXI_WLAST;\n  wire axi_interconnect_0_M02_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M02_AXI_WSTRB;\n  wire axi_interconnect_0_M02_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M03_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M03_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M03_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M03_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M03_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M03_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARQOS;\n  wire axi_interconnect_0_M03_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M03_AXI_ARSIZE;\n  wire axi_interconnect_0_M03_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M03_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M03_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M03_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M03_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M03_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M03_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWQOS;\n  wire axi_interconnect_0_M03_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M03_AXI_AWSIZE;\n  wire axi_interconnect_0_M03_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M03_AXI_BID;\n  wire axi_interconnect_0_M03_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M03_AXI_BRESP;\n  wire axi_interconnect_0_M03_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M03_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M03_AXI_RID;\n  wire axi_interconnect_0_M03_AXI_RLAST;\n  wire axi_interconnect_0_M03_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M03_AXI_RRESP;\n  wire axi_interconnect_0_M03_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M03_AXI_WDATA;\n  wire axi_interconnect_0_M03_AXI_WLAST;\n  wire axi_interconnect_0_M03_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M03_AXI_WSTRB;\n  wire axi_interconnect_0_M03_AXI_WVALID;\n\n  assign ACLK_1 = ACLK;\n  assign ARESETN_1 = ARESETN;\n  assign M00_AXI_araddr[63:0] = axi_interconnect_0_M00_AXI_ARADDR;\n  assign M00_AXI_arburst[1:0] = axi_interconnect_0_M00_AXI_ARBURST;\n  assign M00_AXI_arcache[3:0] = axi_interconnect_0_M00_AXI_ARCACHE;\n  assign M00_AXI_arid[6:0] = axi_interconnect_0_M00_AXI_ARID;\n  assign M00_AXI_arlen[7:0] = axi_interconnect_0_M00_AXI_ARLEN;\n  assign M00_AXI_arlock[0] = axi_interconnect_0_M00_AXI_ARLOCK;\n  assign M00_AXI_arprot[2:0] = axi_interconnect_0_M00_AXI_ARPROT;\n  assign M00_AXI_arqos[3:0] = axi_interconnect_0_M00_AXI_ARQOS;\n  assign M00_AXI_arregion[3:0] = axi_interconnect_0_M00_AXI_ARREGION;\n  assign M00_AXI_arsize[2:0] = axi_interconnect_0_M00_AXI_ARSIZE;\n  assign M00_AXI_arvalid = axi_interconnect_0_M00_AXI_ARVALID;\n  assign M00_AXI_awaddr[63:0] = axi_interconnect_0_M00_AXI_AWADDR;\n  assign M00_AXI_awburst[1:0] = axi_interconnect_0_M00_AXI_AWBURST;\n  assign M00_AXI_awcache[3:0] = axi_interconnect_0_M00_AXI_AWCACHE;\n  assign M00_AXI_awid[6:0] = axi_interconnect_0_M00_AXI_AWID;\n  assign M00_AXI_awlen[7:0] = axi_interconnect_0_M00_AXI_AWLEN;\n  assign M00_AXI_awlock[0] = axi_interconnect_0_M00_AXI_AWLOCK;\n  assign M00_AXI_awprot[2:0] = axi_interconnect_0_M00_AXI_AWPROT;\n  assign M00_AXI_awqos[3:0] = axi_interconnect_0_M00_AXI_AWQOS;\n  assign M00_AXI_awregion[3:0] = axi_interconnect_0_M00_AXI_AWREGION;\n  assign M00_AXI_awsize[2:0] = axi_interconnect_0_M00_AXI_AWSIZE;\n  assign M00_AXI_awvalid = axi_interconnect_0_M00_AXI_AWVALID;\n  assign M00_AXI_bready = axi_interconnect_0_M00_AXI_BREADY;\n  assign M00_AXI_rready = axi_interconnect_0_M00_AXI_RREADY;\n  assign M00_AXI_wdata[511:0] = axi_interconnect_0_M00_AXI_WDATA;\n  assign M00_AXI_wlast = axi_interconnect_0_M00_AXI_WLAST;\n  assign M00_AXI_wstrb[63:0] = axi_interconnect_0_M00_AXI_WSTRB;\n  assign M00_AXI_wvalid = axi_interconnect_0_M00_AXI_WVALID;\n  assign M01_AXI_araddr[63:0] = axi_interconnect_0_M01_AXI_ARADDR;\n  assign M01_AXI_arburst[1:0] = axi_interconnect_0_M01_AXI_ARBURST;\n  assign M01_AXI_arcache[3:0] = axi_interconnect_0_M01_AXI_ARCACHE;\n  assign M01_AXI_arid[6:0] = axi_interconnect_0_M01_AXI_ARID;\n  assign M01_AXI_arlen[7:0] = axi_interconnect_0_M01_AXI_ARLEN;\n  assign M01_AXI_arlock[0] = axi_interconnect_0_M01_AXI_ARLOCK;\n  assign M01_AXI_arprot[2:0] = axi_interconnect_0_M01_AXI_ARPROT;\n  assign M01_AXI_arqos[3:0] = axi_interconnect_0_M01_AXI_ARQOS;\n  assign M01_AXI_arregion[3:0] = axi_interconnect_0_M01_AXI_ARREGION;\n  assign M01_AXI_arsize[2:0] = axi_interconnect_0_M01_AXI_ARSIZE;\n  assign M01_AXI_arvalid = axi_interconnect_0_M01_AXI_ARVALID;\n  assign M01_AXI_awaddr[63:0] = axi_interconnect_0_M01_AXI_AWADDR;\n  assign M01_AXI_awburst[1:0] = axi_interconnect_0_M01_AXI_AWBURST;\n  assign M01_AXI_awcache[3:0] = axi_interconnect_0_M01_AXI_AWCACHE;\n  assign M01_AXI_awid[6:0] = axi_interconnect_0_M01_AXI_AWID;\n  assign M01_AXI_awlen[7:0] = axi_interconnect_0_M01_AXI_AWLEN;\n  assign M01_AXI_awlock[0] = axi_interconnect_0_M01_AXI_AWLOCK;\n  assign M01_AXI_awprot[2:0] = axi_interconnect_0_M01_AXI_AWPROT;\n  assign M01_AXI_awqos[3:0] = axi_interconnect_0_M01_AXI_AWQOS;\n  assign M01_AXI_awregion[3:0] = axi_interconnect_0_M01_AXI_AWREGION;\n  assign M01_AXI_awsize[2:0] = axi_interconnect_0_M01_AXI_AWSIZE;\n  assign M01_AXI_awvalid = axi_interconnect_0_M01_AXI_AWVALID;\n  assign M01_AXI_bready = axi_interconnect_0_M01_AXI_BREADY;\n  assign M01_AXI_rready = axi_interconnect_0_M01_AXI_RREADY;\n  assign M01_AXI_wdata[511:0] = axi_interconnect_0_M01_AXI_WDATA;\n  assign M01_AXI_wlast = axi_interconnect_0_M01_AXI_WLAST;\n  assign M01_AXI_wstrb[63:0] = axi_interconnect_0_M01_AXI_WSTRB;\n  assign M01_AXI_wvalid = axi_interconnect_0_M01_AXI_WVALID;\n  assign M02_AXI_araddr[63:0] = axi_interconnect_0_M02_AXI_ARADDR;\n  assign M02_AXI_arburst[1:0] = axi_interconnect_0_M02_AXI_ARBURST;\n  assign M02_AXI_arcache[3:0] = axi_interconnect_0_M02_AXI_ARCACHE;\n  assign M02_AXI_arid[6:0] = axi_interconnect_0_M02_AXI_ARID;\n  assign M02_AXI_arlen[7:0] = axi_interconnect_0_M02_AXI_ARLEN;\n  assign M02_AXI_arlock[0] = axi_interconnect_0_M02_AXI_ARLOCK;\n  assign M02_AXI_arprot[2:0] = axi_interconnect_0_M02_AXI_ARPROT;\n  assign M02_AXI_arqos[3:0] = axi_interconnect_0_M02_AXI_ARQOS;\n  assign M02_AXI_arregion[3:0] = axi_interconnect_0_M02_AXI_ARREGION;\n  assign M02_AXI_arsize[2:0] = axi_interconnect_0_M02_AXI_ARSIZE;\n  assign M02_AXI_arvalid = axi_interconnect_0_M02_AXI_ARVALID;\n  assign M02_AXI_awaddr[63:0] = axi_interconnect_0_M02_AXI_AWADDR;\n  assign M02_AXI_awburst[1:0] = axi_interconnect_0_M02_AXI_AWBURST;\n  assign M02_AXI_awcache[3:0] = axi_interconnect_0_M02_AXI_AWCACHE;\n  assign M02_AXI_awid[6:0] = axi_interconnect_0_M02_AXI_AWID;\n  assign M02_AXI_awlen[7:0] = axi_interconnect_0_M02_AXI_AWLEN;\n  assign M02_AXI_awlock[0] = axi_interconnect_0_M02_AXI_AWLOCK;\n  assign M02_AXI_awprot[2:0] = axi_interconnect_0_M02_AXI_AWPROT;\n  assign M02_AXI_awqos[3:0] = axi_interconnect_0_M02_AXI_AWQOS;\n  assign M02_AXI_awregion[3:0] = axi_interconnect_0_M02_AXI_AWREGION;\n  assign M02_AXI_awsize[2:0] = axi_interconnect_0_M02_AXI_AWSIZE;\n  assign M02_AXI_awvalid = axi_interconnect_0_M02_AXI_AWVALID;\n  assign M02_AXI_bready = axi_interconnect_0_M02_AXI_BREADY;\n  assign M02_AXI_rready = axi_interconnect_0_M02_AXI_RREADY;\n  assign M02_AXI_wdata[511:0] = axi_interconnect_0_M02_AXI_WDATA;\n  assign M02_AXI_wlast = axi_interconnect_0_M02_AXI_WLAST;\n  assign M02_AXI_wstrb[63:0] = axi_interconnect_0_M02_AXI_WSTRB;\n  assign M02_AXI_wvalid = axi_interconnect_0_M02_AXI_WVALID;\n  assign M03_AXI_araddr[63:0] = axi_interconnect_0_M03_AXI_ARADDR;\n  assign M03_AXI_arburst[1:0] = axi_interconnect_0_M03_AXI_ARBURST;\n  assign M03_AXI_arcache[3:0] = axi_interconnect_0_M03_AXI_ARCACHE;\n  assign M03_AXI_arid[6:0] = axi_interconnect_0_M03_AXI_ARID;\n  assign M03_AXI_arlen[7:0] = axi_interconnect_0_M03_AXI_ARLEN;\n  assign M03_AXI_arlock[0] = axi_interconnect_0_M03_AXI_ARLOCK;\n  assign M03_AXI_arprot[2:0] = axi_interconnect_0_M03_AXI_ARPROT;\n  assign M03_AXI_arqos[3:0] = axi_interconnect_0_M03_AXI_ARQOS;\n  assign M03_AXI_arregion[3:0] = axi_interconnect_0_M03_AXI_ARREGION;\n  assign M03_AXI_arsize[2:0] = axi_interconnect_0_M03_AXI_ARSIZE;\n  assign M03_AXI_arvalid = axi_interconnect_0_M03_AXI_ARVALID;\n  assign M03_AXI_awaddr[63:0] = axi_interconnect_0_M03_AXI_AWADDR;\n  assign M03_AXI_awburst[1:0] = axi_interconnect_0_M03_AXI_AWBURST;\n  assign M03_AXI_awcache[3:0] = axi_interconnect_0_M03_AXI_AWCACHE;\n  assign M03_AXI_awid[6:0] = axi_interconnect_0_M03_AXI_AWID;\n  assign M03_AXI_awlen[7:0] = axi_interconnect_0_M03_AXI_AWLEN;\n  assign M03_AXI_awlock[0] = axi_interconnect_0_M03_AXI_AWLOCK;\n  assign M03_AXI_awprot[2:0] = axi_interconnect_0_M03_AXI_AWPROT;\n  assign M03_AXI_awqos[3:0] = axi_interconnect_0_M03_AXI_AWQOS;\n  assign M03_AXI_awregion[3:0] = axi_interconnect_0_M03_AXI_AWREGION;\n  assign M03_AXI_awsize[2:0] = axi_interconnect_0_M03_AXI_AWSIZE;\n  assign M03_AXI_awvalid = axi_interconnect_0_M03_AXI_AWVALID;\n  assign M03_AXI_bready = axi_interconnect_0_M03_AXI_BREADY;\n  assign M03_AXI_rready = axi_interconnect_0_M03_AXI_RREADY;\n  assign M03_AXI_wdata[511:0] = axi_interconnect_0_M03_AXI_WDATA;\n  assign M03_AXI_wlast = axi_interconnect_0_M03_AXI_WLAST;\n  assign M03_AXI_wstrb[63:0] = axi_interconnect_0_M03_AXI_WSTRB;\n  assign M03_AXI_wvalid = axi_interconnect_0_M03_AXI_WVALID;\n  assign S00_AXI_1_ARADDR = S00_AXI_araddr[63:0];\n  assign S00_AXI_1_ARBURST = S00_AXI_arburst[1:0];\n  assign S00_AXI_1_ARCACHE = S00_AXI_arcache[3:0];\n  assign S00_AXI_1_ARID = S00_AXI_arid[5:0];\n  assign S00_AXI_1_ARLEN = S00_AXI_arlen[7:0];\n  assign S00_AXI_1_ARLOCK = S00_AXI_arlock[0];\n  assign S00_AXI_1_ARPROT = S00_AXI_arprot[2:0];\n  assign S00_AXI_1_ARQOS = S00_AXI_arqos[3:0];\n  assign S00_AXI_1_ARREGION = S00_AXI_arregion[3:0];\n  assign S00_AXI_1_ARSIZE = S00_AXI_arsize[2:0];\n  assign S00_AXI_1_ARVALID = S00_AXI_arvalid;\n  assign S00_AXI_1_AWADDR = S00_AXI_awaddr[63:0];\n  assign S00_AXI_1_AWBURST = S00_AXI_awburst[1:0];\n  assign S00_AXI_1_AWCACHE = S00_AXI_awcache[3:0];\n  assign S00_AXI_1_AWID = S00_AXI_awid[5:0];\n  assign S00_AXI_1_AWLEN = S00_AXI_awlen[7:0];\n  assign S00_AXI_1_AWLOCK = S00_AXI_awlock[0];\n  assign S00_AXI_1_AWPROT = S00_AXI_awprot[2:0];\n  assign S00_AXI_1_AWQOS = S00_AXI_awqos[3:0];\n  assign S00_AXI_1_AWREGION = S00_AXI_awregion[3:0];\n  assign S00_AXI_1_AWSIZE = S00_AXI_awsize[2:0];\n  assign S00_AXI_1_AWVALID = S00_AXI_awvalid;\n  assign S00_AXI_1_BREADY = S00_AXI_bready;\n  assign S00_AXI_1_RREADY = S00_AXI_rready;\n  assign S00_AXI_1_WDATA = S00_AXI_wdata[511:0];\n  assign S00_AXI_1_WLAST = S00_AXI_wlast;\n  assign S00_AXI_1_WSTRB = S00_AXI_wstrb[63:0];\n  assign S00_AXI_1_WVALID = S00_AXI_wvalid;\n  assign S00_AXI_arready = S00_AXI_1_ARREADY;\n  assign S00_AXI_awready = S00_AXI_1_AWREADY;\n  assign S00_AXI_bid[5:0] = S00_AXI_1_BID;\n  assign S00_AXI_bresp[1:0] = S00_AXI_1_BRESP;\n  assign S00_AXI_bvalid = S00_AXI_1_BVALID;\n  assign S00_AXI_rdata[511:0] = S00_AXI_1_RDATA;\n  assign S00_AXI_rid[5:0] = S00_AXI_1_RID;\n  assign S00_AXI_rlast = S00_AXI_1_RLAST;\n  assign S00_AXI_rresp[1:0] = S00_AXI_1_RRESP;\n  assign S00_AXI_rvalid = S00_AXI_1_RVALID;\n  assign S00_AXI_wready = S00_AXI_1_WREADY;\n  assign S01_AXI_1_ARADDR = S01_AXI_araddr[63:0];\n  assign S01_AXI_1_ARBURST = S01_AXI_arburst[1:0];\n  assign S01_AXI_1_ARCACHE = S01_AXI_arcache[3:0];\n  assign S01_AXI_1_ARID = S01_AXI_arid[5:0];\n  assign S01_AXI_1_ARLEN = S01_AXI_arlen[7:0];\n  assign S01_AXI_1_ARLOCK = S01_AXI_arlock[0];\n  assign S01_AXI_1_ARPROT = S01_AXI_arprot[2:0];\n  assign S01_AXI_1_ARQOS = S01_AXI_arqos[3:0];\n  assign S01_AXI_1_ARREGION = S01_AXI_arregion[3:0];\n  assign S01_AXI_1_ARSIZE = S01_AXI_arsize[2:0];\n  assign S01_AXI_1_ARVALID = S01_AXI_arvalid;\n  assign S01_AXI_1_AWADDR = S01_AXI_awaddr[63:0];\n  assign S01_AXI_1_AWBURST = S01_AXI_awburst[1:0];\n  assign S01_AXI_1_AWCACHE = S01_AXI_awcache[3:0];\n  assign S01_AXI_1_AWID = S01_AXI_awid[5:0];\n  assign S01_AXI_1_AWLEN = S01_AXI_awlen[7:0];\n  assign S01_AXI_1_AWLOCK = S01_AXI_awlock[0];\n  assign S01_AXI_1_AWPROT = S01_AXI_awprot[2:0];\n  assign S01_AXI_1_AWQOS = S01_AXI_awqos[3:0];\n  assign S01_AXI_1_AWREGION = S01_AXI_awregion[3:0];\n  assign S01_AXI_1_AWSIZE = S01_AXI_awsize[2:0];\n  assign S01_AXI_1_AWVALID = S01_AXI_awvalid;\n  assign S01_AXI_1_BREADY = S01_AXI_bready;\n  assign S01_AXI_1_RREADY = S01_AXI_rready;\n  assign S01_AXI_1_WDATA = S01_AXI_wdata[511:0];\n  assign S01_AXI_1_WLAST = S01_AXI_wlast;\n  assign S01_AXI_1_WSTRB = S01_AXI_wstrb[63:0];\n  assign S01_AXI_1_WVALID = S01_AXI_wvalid;\n  assign S01_AXI_arready = S01_AXI_1_ARREADY;\n  assign S01_AXI_awready = S01_AXI_1_AWREADY;\n  assign S01_AXI_bid[5:0] = S01_AXI_1_BID;\n  assign S01_AXI_bresp[1:0] = S01_AXI_1_BRESP;\n  assign S01_AXI_bvalid = S01_AXI_1_BVALID;\n  assign S01_AXI_rdata[511:0] = S01_AXI_1_RDATA;\n  assign S01_AXI_rid[5:0] = S01_AXI_1_RID;\n  assign S01_AXI_rlast = S01_AXI_1_RLAST;\n  assign S01_AXI_rresp[1:0] = S01_AXI_1_RRESP;\n  assign S01_AXI_rvalid = S01_AXI_1_RVALID;\n  assign S01_AXI_wready = S01_AXI_1_WREADY;\n  assign axi_interconnect_0_M00_AXI_ARREADY = M00_AXI_arready;\n  assign axi_interconnect_0_M00_AXI_AWREADY = M00_AXI_awready;\n  assign axi_interconnect_0_M00_AXI_BID = M00_AXI_bid[6:0];\n  assign axi_interconnect_0_M00_AXI_BRESP = M00_AXI_bresp[1:0];\n  assign axi_interconnect_0_M00_AXI_BVALID = M00_AXI_bvalid;\n  assign axi_interconnect_0_M00_AXI_RDATA = M00_AXI_rdata[511:0];\n  assign axi_interconnect_0_M00_AXI_RID = M00_AXI_rid[6:0];\n  assign axi_interconnect_0_M00_AXI_RLAST = M00_AXI_rlast;\n  assign axi_interconnect_0_M00_AXI_RRESP = M00_AXI_rresp[1:0];\n  assign axi_interconnect_0_M00_AXI_RVALID = M00_AXI_rvalid;\n  assign axi_interconnect_0_M00_AXI_WREADY = M00_AXI_wready;\n  assign axi_interconnect_0_M01_AXI_ARREADY = M01_AXI_arready;\n  assign axi_interconnect_0_M01_AXI_AWREADY = M01_AXI_awready;\n  assign axi_interconnect_0_M01_AXI_BID = M01_AXI_bid[6:0];\n  assign axi_interconnect_0_M01_AXI_BRESP = M01_AXI_bresp[1:0];\n  assign axi_interconnect_0_M01_AXI_BVALID = M01_AXI_bvalid;\n  assign axi_interconnect_0_M01_AXI_RDATA = M01_AXI_rdata[511:0];\n  assign axi_interconnect_0_M01_AXI_RID = M01_AXI_rid[6:0];\n  assign axi_interconnect_0_M01_AXI_RLAST = M01_AXI_rlast;\n  assign axi_interconnect_0_M01_AXI_RRESP = M01_AXI_rresp[1:0];\n  assign axi_interconnect_0_M01_AXI_RVALID = M01_AXI_rvalid;\n  assign axi_interconnect_0_M01_AXI_WREADY = M01_AXI_wready;\n  assign axi_interconnect_0_M02_AXI_ARREADY = M02_AXI_arready;\n  assign axi_interconnect_0_M02_AXI_AWREADY = M02_AXI_awready;\n  assign axi_interconnect_0_M02_AXI_BID = M02_AXI_bid[6:0];\n  assign axi_interconnect_0_M02_AXI_BRESP = M02_AXI_bresp[1:0];\n  assign axi_interconnect_0_M02_AXI_BVALID = M02_AXI_bvalid;\n  assign axi_interconnect_0_M02_AXI_RDATA = M02_AXI_rdata[511:0];\n  assign axi_interconnect_0_M02_AXI_RID = M02_AXI_rid[6:0];\n  assign axi_interconnect_0_M02_AXI_RLAST = M02_AXI_rlast;\n  assign axi_interconnect_0_M02_AXI_RRESP = M02_AXI_rresp[1:0];\n  assign axi_interconnect_0_M02_AXI_RVALID = M02_AXI_rvalid;\n  assign axi_interconnect_0_M02_AXI_WREADY = M02_AXI_wready;\n  assign axi_interconnect_0_M03_AXI_ARREADY = M03_AXI_arready;\n  assign axi_interconnect_0_M03_AXI_AWREADY = M03_AXI_awready;\n  assign axi_interconnect_0_M03_AXI_BID = M03_AXI_bid[6:0];\n  assign axi_interconnect_0_M03_AXI_BRESP = M03_AXI_bresp[1:0];\n  assign axi_interconnect_0_M03_AXI_BVALID = M03_AXI_bvalid;\n  assign axi_interconnect_0_M03_AXI_RDATA = M03_AXI_rdata[511:0];\n  assign axi_interconnect_0_M03_AXI_RID = M03_AXI_rid[6:0];\n  assign axi_interconnect_0_M03_AXI_RLAST = M03_AXI_rlast;\n  assign axi_interconnect_0_M03_AXI_RRESP = M03_AXI_rresp[1:0];\n  assign axi_interconnect_0_M03_AXI_RVALID = M03_AXI_rvalid;\n  assign axi_interconnect_0_M03_AXI_WREADY = M03_AXI_wready;\n  cl_axi_interconnect_axi_interconnect_0_0 axi_interconnect_0\n       (.ACLK(ACLK_1),\n        .ARESETN(ARESETN_1),\n        .M00_ACLK(ACLK_1),\n        .M00_ARESETN(ARESETN_1),\n        .M00_AXI_araddr(axi_interconnect_0_M00_AXI_ARADDR),\n        .M00_AXI_arburst(axi_interconnect_0_M00_AXI_ARBURST),\n        .M00_AXI_arcache(axi_interconnect_0_M00_AXI_ARCACHE),\n        .M00_AXI_arid(axi_interconnect_0_M00_AXI_ARID),\n        .M00_AXI_arlen(axi_interconnect_0_M00_AXI_ARLEN),\n        .M00_AXI_arlock(axi_interconnect_0_M00_AXI_ARLOCK),\n        .M00_AXI_arprot(axi_interconnect_0_M00_AXI_ARPROT),\n        .M00_AXI_arqos(axi_interconnect_0_M00_AXI_ARQOS),\n        .M00_AXI_arready(axi_interconnect_0_M00_AXI_ARREADY),\n        .M00_AXI_arregion(axi_interconnect_0_M00_AXI_ARREGION),\n        .M00_AXI_arsize(axi_interconnect_0_M00_AXI_ARSIZE),\n        .M00_AXI_arvalid(axi_interconnect_0_M00_AXI_ARVALID),\n        .M00_AXI_awaddr(axi_interconnect_0_M00_AXI_AWADDR),\n        .M00_AXI_awburst(axi_interconnect_0_M00_AXI_AWBURST),\n        .M00_AXI_awcache(axi_interconnect_0_M00_AXI_AWCACHE),\n        .M00_AXI_awid(axi_interconnect_0_M00_AXI_AWID),\n        .M00_AXI_awlen(axi_interconnect_0_M00_AXI_AWLEN),\n        .M00_AXI_awlock(axi_interconnect_0_M00_AXI_AWLOCK),\n        .M00_AXI_awprot(axi_interconnect_0_M00_AXI_AWPROT),\n        .M00_AXI_awqos(axi_interconnect_0_M00_AXI_AWQOS),\n        .M00_AXI_awready(axi_interconnect_0_M00_AXI_AWREADY),\n        .M00_AXI_awregion(axi_interconnect_0_M00_AXI_AWREGION),\n        .M00_AXI_awsize(axi_interconnect_0_M00_AXI_AWSIZE),\n        .M00_AXI_awvalid(axi_interconnect_0_M00_AXI_AWVALID),\n        .M00_AXI_bid(axi_interconnect_0_M00_AXI_BID),\n        .M00_AXI_bready(axi_interconnect_0_M00_AXI_BREADY),\n        .M00_AXI_bresp(axi_interconnect_0_M00_AXI_BRESP),\n        .M00_AXI_bvalid(axi_interconnect_0_M00_AXI_BVALID),\n        .M00_AXI_rdata(axi_interconnect_0_M00_AXI_RDATA),\n        .M00_AXI_rid(axi_interconnect_0_M00_AXI_RID),\n        .M00_AXI_rlast(axi_interconnect_0_M00_AXI_RLAST),\n        .M00_AXI_rready(axi_interconnect_0_M00_AXI_RREADY),\n        .M00_AXI_rresp(axi_interconnect_0_M00_AXI_RRESP),\n        .M00_AXI_rvalid(axi_interconnect_0_M00_AXI_RVALID),\n        .M00_AXI_wdata(axi_interconnect_0_M00_AXI_WDATA),\n        .M00_AXI_wlast(axi_interconnect_0_M00_AXI_WLAST),\n        .M00_AXI_wready(axi_interconnect_0_M00_AXI_WREADY),\n        .M00_AXI_wstrb(axi_interconnect_0_M00_AXI_WSTRB),\n        .M00_AXI_wvalid(axi_interconnect_0_M00_AXI_WVALID),\n        .M01_ACLK(ACLK_1),\n        .M01_ARESETN(ARESETN_1),\n        .M01_AXI_araddr(axi_interconnect_0_M01_AXI_ARADDR),\n        .M01_AXI_arburst(axi_interconnect_0_M01_AXI_ARBURST),\n        .M01_AXI_arcache(axi_interconnect_0_M01_AXI_ARCACHE),\n        .M01_AXI_arid(axi_interconnect_0_M01_AXI_ARID),\n        .M01_AXI_arlen(axi_interconnect_0_M01_AXI_ARLEN),\n        .M01_AXI_arlock(axi_interconnect_0_M01_AXI_ARLOCK),\n        .M01_AXI_arprot(axi_interconnect_0_M01_AXI_ARPROT),\n        .M01_AXI_arqos(axi_interconnect_0_M01_AXI_ARQOS),\n        .M01_AXI_arready(axi_interconnect_0_M01_AXI_ARREADY),\n        .M01_AXI_arregion(axi_interconnect_0_M01_AXI_ARREGION),\n        .M01_AXI_arsize(axi_interconnect_0_M01_AXI_ARSIZE),\n        .M01_AXI_arvalid(axi_interconnect_0_M01_AXI_ARVALID),\n        .M01_AXI_awaddr(axi_interconnect_0_M01_AXI_AWADDR),\n        .M01_AXI_awburst(axi_interconnect_0_M01_AXI_AWBURST),\n        .M01_AXI_awcache(axi_interconnect_0_M01_AXI_AWCACHE),\n        .M01_AXI_awid(axi_interconnect_0_M01_AXI_AWID),\n        .M01_AXI_awlen(axi_interconnect_0_M01_AXI_AWLEN),\n        .M01_AXI_awlock(axi_interconnect_0_M01_AXI_AWLOCK),\n        .M01_AXI_awprot(axi_interconnect_0_M01_AXI_AWPROT),\n        .M01_AXI_awqos(axi_interconnect_0_M01_AXI_AWQOS),\n        .M01_AXI_awready(axi_interconnect_0_M01_AXI_AWREADY),\n        .M01_AXI_awregion(axi_interconnect_0_M01_AXI_AWREGION),\n        .M01_AXI_awsize(axi_interconnect_0_M01_AXI_AWSIZE),\n        .M01_AXI_awvalid(axi_interconnect_0_M01_AXI_AWVALID),\n        .M01_AXI_bid(axi_interconnect_0_M01_AXI_BID),\n        .M01_AXI_bready(axi_interconnect_0_M01_AXI_BREADY),\n        .M01_AXI_bresp(axi_interconnect_0_M01_AXI_BRESP),\n        .M01_AXI_bvalid(axi_interconnect_0_M01_AXI_BVALID),\n        .M01_AXI_rdata(axi_interconnect_0_M01_AXI_RDATA),\n        .M01_AXI_rid(axi_interconnect_0_M01_AXI_RID),\n        .M01_AXI_rlast(axi_interconnect_0_M01_AXI_RLAST),\n        .M01_AXI_rready(axi_interconnect_0_M01_AXI_RREADY),\n        .M01_AXI_rresp(axi_interconnect_0_M01_AXI_RRESP),\n        .M01_AXI_rvalid(axi_interconnect_0_M01_AXI_RVALID),\n        .M01_AXI_wdata(axi_interconnect_0_M01_AXI_WDATA),\n        .M01_AXI_wlast(axi_interconnect_0_M01_AXI_WLAST),\n        .M01_AXI_wready(axi_interconnect_0_M01_AXI_WREADY),\n        .M01_AXI_wstrb(axi_interconnect_0_M01_AXI_WSTRB),\n        .M01_AXI_wvalid(axi_interconnect_0_M01_AXI_WVALID),\n        .M02_ACLK(ACLK_1),\n        .M02_ARESETN(ARESETN_1),\n        .M02_AXI_araddr(axi_interconnect_0_M02_AXI_ARADDR),\n        .M02_AXI_arburst(axi_interconnect_0_M02_AXI_ARBURST),\n        .M02_AXI_arcache(axi_interconnect_0_M02_AXI_ARCACHE),\n        .M02_AXI_arid(axi_interconnect_0_M02_AXI_ARID),\n        .M02_AXI_arlen(axi_interconnect_0_M02_AXI_ARLEN),\n        .M02_AXI_arlock(axi_interconnect_0_M02_AXI_ARLOCK),\n        .M02_AXI_arprot(axi_interconnect_0_M02_AXI_ARPROT),\n        .M02_AXI_arqos(axi_interconnect_0_M02_AXI_ARQOS),\n        .M02_AXI_arready(axi_interconnect_0_M02_AXI_ARREADY),\n        .M02_AXI_arregion(axi_interconnect_0_M02_AXI_ARREGION),\n        .M02_AXI_arsize(axi_interconnect_0_M02_AXI_ARSIZE),\n        .M02_AXI_arvalid(axi_interconnect_0_M02_AXI_ARVALID),\n        .M02_AXI_awaddr(axi_interconnect_0_M02_AXI_AWADDR),\n        .M02_AXI_awburst(axi_interconnect_0_M02_AXI_AWBURST),\n        .M02_AXI_awcache(axi_interconnect_0_M02_AXI_AWCACHE),\n        .M02_AXI_awid(axi_interconnect_0_M02_AXI_AWID),\n        .M02_AXI_awlen(axi_interconnect_0_M02_AXI_AWLEN),\n        .M02_AXI_awlock(axi_interconnect_0_M02_AXI_AWLOCK),\n        .M02_AXI_awprot(axi_interconnect_0_M02_AXI_AWPROT),\n        .M02_AXI_awqos(axi_interconnect_0_M02_AXI_AWQOS),\n        .M02_AXI_awready(axi_interconnect_0_M02_AXI_AWREADY),\n        .M02_AXI_awregion(axi_interconnect_0_M02_AXI_AWREGION),\n        .M02_AXI_awsize(axi_interconnect_0_M02_AXI_AWSIZE),\n        .M02_AXI_awvalid(axi_interconnect_0_M02_AXI_AWVALID),\n        .M02_AXI_bid(axi_interconnect_0_M02_AXI_BID),\n        .M02_AXI_bready(axi_interconnect_0_M02_AXI_BREADY),\n        .M02_AXI_bresp(axi_interconnect_0_M02_AXI_BRESP),\n        .M02_AXI_bvalid(axi_interconnect_0_M02_AXI_BVALID),\n        .M02_AXI_rdata(axi_interconnect_0_M02_AXI_RDATA),\n        .M02_AXI_rid(axi_interconnect_0_M02_AXI_RID),\n        .M02_AXI_rlast(axi_interconnect_0_M02_AXI_RLAST),\n        .M02_AXI_rready(axi_interconnect_0_M02_AXI_RREADY),\n        .M02_AXI_rresp(axi_interconnect_0_M02_AXI_RRESP),\n        .M02_AXI_rvalid(axi_interconnect_0_M02_AXI_RVALID),\n        .M02_AXI_wdata(axi_interconnect_0_M02_AXI_WDATA),\n        .M02_AXI_wlast(axi_interconnect_0_M02_AXI_WLAST),\n        .M02_AXI_wready(axi_interconnect_0_M02_AXI_WREADY),\n        .M02_AXI_wstrb(axi_interconnect_0_M02_AXI_WSTRB),\n        .M02_AXI_wvalid(axi_interconnect_0_M02_AXI_WVALID),\n        .M03_ACLK(ACLK_1),\n        .M03_ARESETN(ARESETN_1),\n        .M03_AXI_araddr(axi_interconnect_0_M03_AXI_ARADDR),\n        .M03_AXI_arburst(axi_interconnect_0_M03_AXI_ARBURST),\n        .M03_AXI_arcache(axi_interconnect_0_M03_AXI_ARCACHE),\n        .M03_AXI_arid(axi_interconnect_0_M03_AXI_ARID),\n        .M03_AXI_arlen(axi_interconnect_0_M03_AXI_ARLEN),\n        .M03_AXI_arlock(axi_interconnect_0_M03_AXI_ARLOCK),\n        .M03_AXI_arprot(axi_interconnect_0_M03_AXI_ARPROT),\n        .M03_AXI_arqos(axi_interconnect_0_M03_AXI_ARQOS),\n        .M03_AXI_arready(axi_interconnect_0_M03_AXI_ARREADY),\n        .M03_AXI_arregion(axi_interconnect_0_M03_AXI_ARREGION),\n        .M03_AXI_arsize(axi_interconnect_0_M03_AXI_ARSIZE),\n        .M03_AXI_arvalid(axi_interconnect_0_M03_AXI_ARVALID),\n        .M03_AXI_awaddr(axi_interconnect_0_M03_AXI_AWADDR),\n        .M03_AXI_awburst(axi_interconnect_0_M03_AXI_AWBURST),\n        .M03_AXI_awcache(axi_interconnect_0_M03_AXI_AWCACHE),\n        .M03_AXI_awid(axi_interconnect_0_M03_AXI_AWID),\n        .M03_AXI_awlen(axi_interconnect_0_M03_AXI_AWLEN),\n        .M03_AXI_awlock(axi_interconnect_0_M03_AXI_AWLOCK),\n        .M03_AXI_awprot(axi_interconnect_0_M03_AXI_AWPROT),\n        .M03_AXI_awqos(axi_interconnect_0_M03_AXI_AWQOS),\n        .M03_AXI_awready(axi_interconnect_0_M03_AXI_AWREADY),\n        .M03_AXI_awregion(axi_interconnect_0_M03_AXI_AWREGION),\n        .M03_AXI_awsize(axi_interconnect_0_M03_AXI_AWSIZE),\n        .M03_AXI_awvalid(axi_interconnect_0_M03_AXI_AWVALID),\n        .M03_AXI_bid(axi_interconnect_0_M03_AXI_BID),\n        .M03_AXI_bready(axi_interconnect_0_M03_AXI_BREADY),\n        .M03_AXI_bresp(axi_interconnect_0_M03_AXI_BRESP),\n        .M03_AXI_bvalid(axi_interconnect_0_M03_AXI_BVALID),\n        .M03_AXI_rdata(axi_interconnect_0_M03_AXI_RDATA),\n        .M03_AXI_rid(axi_interconnect_0_M03_AXI_RID),\n        .M03_AXI_rlast(axi_interconnect_0_M03_AXI_RLAST),\n        .M03_AXI_rready(axi_interconnect_0_M03_AXI_RREADY),\n        .M03_AXI_rresp(axi_interconnect_0_M03_AXI_RRESP),\n        .M03_AXI_rvalid(axi_interconnect_0_M03_AXI_RVALID),\n        .M03_AXI_wdata(axi_interconnect_0_M03_AXI_WDATA),\n        .M03_AXI_wlast(axi_interconnect_0_M03_AXI_WLAST),\n        .M03_AXI_wready(axi_interconnect_0_M03_AXI_WREADY),\n        .M03_AXI_wstrb(axi_interconnect_0_M03_AXI_WSTRB),\n        .M03_AXI_wvalid(axi_interconnect_0_M03_AXI_WVALID),\n        .S00_ACLK(ACLK_1),\n        .S00_ARESETN(ARESETN_1),\n        .S00_AXI_araddr(S00_AXI_1_ARADDR),\n        .S00_AXI_arburst(S00_AXI_1_ARBURST),\n        .S00_AXI_arcache(S00_AXI_1_ARCACHE),\n        .S00_AXI_arid(S00_AXI_1_ARID),\n        .S00_AXI_arlen(S00_AXI_1_ARLEN),\n        .S00_AXI_arlock(S00_AXI_1_ARLOCK),\n        .S00_AXI_arprot(S00_AXI_1_ARPROT),\n        .S00_AXI_arqos(S00_AXI_1_ARQOS),\n        .S00_AXI_arready(S00_AXI_1_ARREADY),\n        .S00_AXI_arregion(S00_AXI_1_ARREGION),\n        .S00_AXI_arsize(S00_AXI_1_ARSIZE),\n        .S00_AXI_arvalid(S00_AXI_1_ARVALID),\n        .S00_AXI_awaddr(S00_AXI_1_AWADDR),\n        .S00_AXI_awburst(S00_AXI_1_AWBURST),\n        .S00_AXI_awcache(S00_AXI_1_AWCACHE),\n        .S00_AXI_awid(S00_AXI_1_AWID),\n        .S00_AXI_awlen(S00_AXI_1_AWLEN),\n        .S00_AXI_awlock(S00_AXI_1_AWLOCK),\n        .S00_AXI_awprot(S00_AXI_1_AWPROT),\n        .S00_AXI_awqos(S00_AXI_1_AWQOS),\n        .S00_AXI_awready(S00_AXI_1_AWREADY),\n        .S00_AXI_awregion(S00_AXI_1_AWREGION),\n        .S00_AXI_awsize(S00_AXI_1_AWSIZE),\n        .S00_AXI_awvalid(S00_AXI_1_AWVALID),\n        .S00_AXI_bid(S00_AXI_1_BID),\n        .S00_AXI_bready(S00_AXI_1_BREADY),\n        .S00_AXI_bresp(S00_AXI_1_BRESP),\n        .S00_AXI_bvalid(S00_AXI_1_BVALID),\n        .S00_AXI_rdata(S00_AXI_1_RDATA),\n        .S00_AXI_rid(S00_AXI_1_RID),\n        .S00_AXI_rlast(S00_AXI_1_RLAST),\n        .S00_AXI_rready(S00_AXI_1_RREADY),\n        .S00_AXI_rresp(S00_AXI_1_RRESP),\n        .S00_AXI_rvalid(S00_AXI_1_RVALID),\n        .S00_AXI_wdata(S00_AXI_1_WDATA),\n        .S00_AXI_wlast(S00_AXI_1_WLAST),\n        .S00_AXI_wready(S00_AXI_1_WREADY),\n        .S00_AXI_wstrb(S00_AXI_1_WSTRB),\n        .S00_AXI_wvalid(S00_AXI_1_WVALID),\n        .S01_ACLK(ACLK_1),\n        .S01_ARESETN(ARESETN_1),\n        .S01_AXI_araddr(S01_AXI_1_ARADDR),\n        .S01_AXI_arburst(S01_AXI_1_ARBURST),\n        .S01_AXI_arcache(S01_AXI_1_ARCACHE),\n        .S01_AXI_arid(S01_AXI_1_ARID),\n        .S01_AXI_arlen(S01_AXI_1_ARLEN),\n        .S01_AXI_arlock(S01_AXI_1_ARLOCK),\n        .S01_AXI_arprot(S01_AXI_1_ARPROT),\n        .S01_AXI_arqos(S01_AXI_1_ARQOS),\n        .S01_AXI_arready(S01_AXI_1_ARREADY),\n        .S01_AXI_arregion(S01_AXI_1_ARREGION),\n        .S01_AXI_arsize(S01_AXI_1_ARSIZE),\n        .S01_AXI_arvalid(S01_AXI_1_ARVALID),\n        .S01_AXI_awaddr(S01_AXI_1_AWADDR),\n        .S01_AXI_awburst(S01_AXI_1_AWBURST),\n        .S01_AXI_awcache(S01_AXI_1_AWCACHE),\n        .S01_AXI_awid(S01_AXI_1_AWID),\n        .S01_AXI_awlen(S01_AXI_1_AWLEN),\n        .S01_AXI_awlock(S01_AXI_1_AWLOCK),\n        .S01_AXI_awprot(S01_AXI_1_AWPROT),\n        .S01_AXI_awqos(S01_AXI_1_AWQOS),\n        .S01_AXI_awready(S01_AXI_1_AWREADY),\n        .S01_AXI_awregion(S01_AXI_1_AWREGION),\n        .S01_AXI_awsize(S01_AXI_1_AWSIZE),\n        .S01_AXI_awvalid(S01_AXI_1_AWVALID),\n        .S01_AXI_bid(S01_AXI_1_BID),\n        .S01_AXI_bready(S01_AXI_1_BREADY),\n        .S01_AXI_bresp(S01_AXI_1_BRESP),\n        .S01_AXI_bvalid(S01_AXI_1_BVALID),\n        .S01_AXI_rdata(S01_AXI_1_RDATA),\n        .S01_AXI_rid(S01_AXI_1_RID),\n        .S01_AXI_rlast(S01_AXI_1_RLAST),\n        .S01_AXI_rready(S01_AXI_1_RREADY),\n        .S01_AXI_rresp(S01_AXI_1_RRESP),\n        .S01_AXI_rvalid(S01_AXI_1_RVALID),\n        .S01_AXI_wdata(S01_AXI_1_WDATA),\n        .S01_AXI_wlast(S01_AXI_1_WLAST),\n        .S01_AXI_wready(S01_AXI_1_WREADY),\n        .S01_AXI_wstrb(S01_AXI_1_WSTRB),\n        .S01_AXI_wvalid(S01_AXI_1_WVALID));\nendmodule\n\nmodule cl_axi_interconnect_axi_interconnect_0_0\n   (ACLK,\n    ARESETN,\n    M00_ACLK,\n    M00_ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_ACLK,\n    M01_ARESETN,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_ACLK,\n    M02_ARESETN,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_ACLK,\n    M03_ARESETN,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_ACLK,\n    S00_ARESETN,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_ACLK,\n    S01_ARESETN,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  input ACLK;\n  input ARESETN;\n  input M00_ACLK;\n  input M00_ARESETN;\n  output [63:0]M00_AXI_araddr;\n  output [1:0]M00_AXI_arburst;\n  output [3:0]M00_AXI_arcache;\n  output [6:0]M00_AXI_arid;\n  output [7:0]M00_AXI_arlen;\n  output [0:0]M00_AXI_arlock;\n  output [2:0]M00_AXI_arprot;\n  output [3:0]M00_AXI_arqos;\n  input M00_AXI_arready;\n  output [3:0]M00_AXI_arregion;\n  output [2:0]M00_AXI_arsize;\n  output M00_AXI_arvalid;\n  output [63:0]M00_AXI_awaddr;\n  output [1:0]M00_AXI_awburst;\n  output [3:0]M00_AXI_awcache;\n  output [6:0]M00_AXI_awid;\n  output [7:0]M00_AXI_awlen;\n  output [0:0]M00_AXI_awlock;\n  output [2:0]M00_AXI_awprot;\n  output [3:0]M00_AXI_awqos;\n  input M00_AXI_awready;\n  output [3:0]M00_AXI_awregion;\n  output [2:0]M00_AXI_awsize;\n  output M00_AXI_awvalid;\n  input [6:0]M00_AXI_bid;\n  output M00_AXI_bready;\n  input [1:0]M00_AXI_bresp;\n  input M00_AXI_bvalid;\n  input [511:0]M00_AXI_rdata;\n  input [6:0]M00_AXI_rid;\n  input M00_AXI_rlast;\n  output M00_AXI_rready;\n  input [1:0]M00_AXI_rresp;\n  input M00_AXI_rvalid;\n  output [511:0]M00_AXI_wdata;\n  output M00_AXI_wlast;\n  input M00_AXI_wready;\n  output [63:0]M00_AXI_wstrb;\n  output M00_AXI_wvalid;\n  input M01_ACLK;\n  input M01_ARESETN;\n  output [63:0]M01_AXI_araddr;\n  output [1:0]M01_AXI_arburst;\n  output [3:0]M01_AXI_arcache;\n  output [6:0]M01_AXI_arid;\n  output [7:0]M01_AXI_arlen;\n  output [0:0]M01_AXI_arlock;\n  output [2:0]M01_AXI_arprot;\n  output [3:0]M01_AXI_arqos;\n  input M01_AXI_arready;\n  output [3:0]M01_AXI_arregion;\n  output [2:0]M01_AXI_arsize;\n  output M01_AXI_arvalid;\n  output [63:0]M01_AXI_awaddr;\n  output [1:0]M01_AXI_awburst;\n  output [3:0]M01_AXI_awcache;\n  output [6:0]M01_AXI_awid;\n  output [7:0]M01_AXI_awlen;\n  output [0:0]M01_AXI_awlock;\n  output [2:0]M01_AXI_awprot;\n  output [3:0]M01_AXI_awqos;\n  input M01_AXI_awready;\n  output [3:0]M01_AXI_awregion;\n  output [2:0]M01_AXI_awsize;\n  output M01_AXI_awvalid;\n  input [6:0]M01_AXI_bid;\n  output M01_AXI_bready;\n  input [1:0]M01_AXI_bresp;\n  input M01_AXI_bvalid;\n  input [511:0]M01_AXI_rdata;\n  input [6:0]M01_AXI_rid;\n  input M01_AXI_rlast;\n  output M01_AXI_rready;\n  input [1:0]M01_AXI_rresp;\n  input M01_AXI_rvalid;\n  output [511:0]M01_AXI_wdata;\n  output M01_AXI_wlast;\n  input M01_AXI_wready;\n  output [63:0]M01_AXI_wstrb;\n  output M01_AXI_wvalid;\n  input M02_ACLK;\n  input M02_ARESETN;\n  output [63:0]M02_AXI_araddr;\n  output [1:0]M02_AXI_arburst;\n  output [3:0]M02_AXI_arcache;\n  output [6:0]M02_AXI_arid;\n  output [7:0]M02_AXI_arlen;\n  output [0:0]M02_AXI_arlock;\n  output [2:0]M02_AXI_arprot;\n  output [3:0]M02_AXI_arqos;\n  input M02_AXI_arready;\n  output [3:0]M02_AXI_arregion;\n  output [2:0]M02_AXI_arsize;\n  output M02_AXI_arvalid;\n  output [63:0]M02_AXI_awaddr;\n  output [1:0]M02_AXI_awburst;\n  output [3:0]M02_AXI_awcache;\n  output [6:0]M02_AXI_awid;\n  output [7:0]M02_AXI_awlen;\n  output [0:0]M02_AXI_awlock;\n  output [2:0]M02_AXI_awprot;\n  output [3:0]M02_AXI_awqos;\n  input M02_AXI_awready;\n  output [3:0]M02_AXI_awregion;\n  output [2:0]M02_AXI_awsize;\n  output M02_AXI_awvalid;\n  input [6:0]M02_AXI_bid;\n  output M02_AXI_bready;\n  input [1:0]M02_AXI_bresp;\n  input M02_AXI_bvalid;\n  input [511:0]M02_AXI_rdata;\n  input [6:0]M02_AXI_rid;\n  input M02_AXI_rlast;\n  output M02_AXI_rready;\n  input [1:0]M02_AXI_rresp;\n  input M02_AXI_rvalid;\n  output [511:0]M02_AXI_wdata;\n  output M02_AXI_wlast;\n  input M02_AXI_wready;\n  output [63:0]M02_AXI_wstrb;\n  output M02_AXI_wvalid;\n  input M03_ACLK;\n  input M03_ARESETN;\n  output [63:0]M03_AXI_araddr;\n  output [1:0]M03_AXI_arburst;\n  output [3:0]M03_AXI_arcache;\n  output [6:0]M03_AXI_arid;\n  output [7:0]M03_AXI_arlen;\n  output [0:0]M03_AXI_arlock;\n  output [2:0]M03_AXI_arprot;\n  output [3:0]M03_AXI_arqos;\n  input M03_AXI_arready;\n  output [3:0]M03_AXI_arregion;\n  output [2:0]M03_AXI_arsize;\n  output M03_AXI_arvalid;\n  output [63:0]M03_AXI_awaddr;\n  output [1:0]M03_AXI_awburst;\n  output [3:0]M03_AXI_awcache;\n  output [6:0]M03_AXI_awid;\n  output [7:0]M03_AXI_awlen;\n  output [0:0]M03_AXI_awlock;\n  output [2:0]M03_AXI_awprot;\n  output [3:0]M03_AXI_awqos;\n  input M03_AXI_awready;\n  output [3:0]M03_AXI_awregion;\n  output [2:0]M03_AXI_awsize;\n  output M03_AXI_awvalid;\n  input [6:0]M03_AXI_bid;\n  output M03_AXI_bready;\n  input [1:0]M03_AXI_bresp;\n  input M03_AXI_bvalid;\n  input [511:0]M03_AXI_rdata;\n  input [6:0]M03_AXI_rid;\n  input M03_AXI_rlast;\n  output M03_AXI_rready;\n  input [1:0]M03_AXI_rresp;\n  input M03_AXI_rvalid;\n  output [511:0]M03_AXI_wdata;\n  output M03_AXI_wlast;\n  input M03_AXI_wready;\n  output [63:0]M03_AXI_wstrb;\n  output M03_AXI_wvalid;\n  input S00_ACLK;\n  input S00_ARESETN;\n  input [63:0]S00_AXI_araddr;\n  input [1:0]S00_AXI_arburst;\n  input [3:0]S00_AXI_arcache;\n  input [5:0]S00_AXI_arid;\n  input [7:0]S00_AXI_arlen;\n  input [0:0]S00_AXI_arlock;\n  input [2:0]S00_AXI_arprot;\n  input [3:0]S00_AXI_arqos;\n  output S00_AXI_arready;\n  input [3:0]S00_AXI_arregion;\n  input [2:0]S00_AXI_arsize;\n  input S00_AXI_arvalid;\n  input [63:0]S00_AXI_awaddr;\n  input [1:0]S00_AXI_awburst;\n  input [3:0]S00_AXI_awcache;\n  input [5:0]S00_AXI_awid;\n  input [7:0]S00_AXI_awlen;\n  input [0:0]S00_AXI_awlock;\n  input [2:0]S00_AXI_awprot;\n  input [3:0]S00_AXI_awqos;\n  output S00_AXI_awready;\n  input [3:0]S00_AXI_awregion;\n  input [2:0]S00_AXI_awsize;\n  input S00_AXI_awvalid;\n  output [5:0]S00_AXI_bid;\n  input S00_AXI_bready;\n  output [1:0]S00_AXI_bresp;\n  output S00_AXI_bvalid;\n  output [511:0]S00_AXI_rdata;\n  output [5:0]S00_AXI_rid;\n  output S00_AXI_rlast;\n  input S00_AXI_rready;\n  output [1:0]S00_AXI_rresp;\n  output S00_AXI_rvalid;\n  input [511:0]S00_AXI_wdata;\n  input S00_AXI_wlast;\n  output S00_AXI_wready;\n  input [63:0]S00_AXI_wstrb;\n  input S00_AXI_wvalid;\n  input S01_ACLK;\n  input S01_ARESETN;\n  input [63:0]S01_AXI_araddr;\n  input [1:0]S01_AXI_arburst;\n  input [3:0]S01_AXI_arcache;\n  input [5:0]S01_AXI_arid;\n  input [7:0]S01_AXI_arlen;\n  input [0:0]S01_AXI_arlock;\n  input [2:0]S01_AXI_arprot;\n  input [3:0]S01_AXI_arqos;\n  output S01_AXI_arready;\n  input [3:0]S01_AXI_arregion;\n  input [2:0]S01_AXI_arsize;\n  input S01_AXI_arvalid;\n  input [63:0]S01_AXI_awaddr;\n  input [1:0]S01_AXI_awburst;\n  input [3:0]S01_AXI_awcache;\n  input [5:0]S01_AXI_awid;\n  input [7:0]S01_AXI_awlen;\n  input [0:0]S01_AXI_awlock;\n  input [2:0]S01_AXI_awprot;\n  input [3:0]S01_AXI_awqos;\n  output S01_AXI_awready;\n  input [3:0]S01_AXI_awregion;\n  input [2:0]S01_AXI_awsize;\n  input S01_AXI_awvalid;\n  output [5:0]S01_AXI_bid;\n  input S01_AXI_bready;\n  output [1:0]S01_AXI_bresp;\n  output S01_AXI_bvalid;\n  output [511:0]S01_AXI_rdata;\n  output [5:0]S01_AXI_rid;\n  output S01_AXI_rlast;\n  input S01_AXI_rready;\n  output [1:0]S01_AXI_rresp;\n  output S01_AXI_rvalid;\n  input [511:0]S01_AXI_wdata;\n  input S01_AXI_wlast;\n  output S01_AXI_wready;\n  input [63:0]S01_AXI_wstrb;\n  input S01_AXI_wvalid;\n\n  wire axi_interconnect_0_ACLK_net;\n  wire axi_interconnect_0_ARESETN_net;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_ARADDR;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_ARBURST;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARCACHE;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_ARID;\n  wire [7:0]axi_interconnect_0_to_s00_couplers_ARLEN;\n  wire [0:0]axi_interconnect_0_to_s00_couplers_ARLOCK;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_ARPROT;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARQOS;\n  wire axi_interconnect_0_to_s00_couplers_ARREADY;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARREGION;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_ARSIZE;\n  wire axi_interconnect_0_to_s00_couplers_ARVALID;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_AWADDR;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_AWBURST;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWCACHE;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_AWID;\n  wire [7:0]axi_interconnect_0_to_s00_couplers_AWLEN;\n  wire [0:0]axi_interconnect_0_to_s00_couplers_AWLOCK;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_AWPROT;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWQOS;\n  wire axi_interconnect_0_to_s00_couplers_AWREADY;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWREGION;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_AWSIZE;\n  wire axi_interconnect_0_to_s00_couplers_AWVALID;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_BID;\n  wire axi_interconnect_0_to_s00_couplers_BREADY;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_BRESP;\n  wire axi_interconnect_0_to_s00_couplers_BVALID;\n  wire [511:0]axi_interconnect_0_to_s00_couplers_RDATA;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_RID;\n  wire axi_interconnect_0_to_s00_couplers_RLAST;\n  wire axi_interconnect_0_to_s00_couplers_RREADY;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_RRESP;\n  wire axi_interconnect_0_to_s00_couplers_RVALID;\n  wire [511:0]axi_interconnect_0_to_s00_couplers_WDATA;\n  wire axi_interconnect_0_to_s00_couplers_WLAST;\n  wire axi_interconnect_0_to_s00_couplers_WREADY;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_WSTRB;\n  wire axi_interconnect_0_to_s00_couplers_WVALID;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_ARADDR;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_ARBURST;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARCACHE;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_ARID;\n  wire [7:0]axi_interconnect_0_to_s01_couplers_ARLEN;\n  wire [0:0]axi_interconnect_0_to_s01_couplers_ARLOCK;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_ARPROT;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARQOS;\n  wire axi_interconnect_0_to_s01_couplers_ARREADY;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARREGION;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_ARSIZE;\n  wire axi_interconnect_0_to_s01_couplers_ARVALID;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_AWADDR;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_AWBURST;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWCACHE;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_AWID;\n  wire [7:0]axi_interconnect_0_to_s01_couplers_AWLEN;\n  wire [0:0]axi_interconnect_0_to_s01_couplers_AWLOCK;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_AWPROT;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWQOS;\n  wire axi_interconnect_0_to_s01_couplers_AWREADY;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWREGION;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_AWSIZE;\n  wire axi_interconnect_0_to_s01_couplers_AWVALID;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_BID;\n  wire axi_interconnect_0_to_s01_couplers_BREADY;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_BRESP;\n  wire axi_interconnect_0_to_s01_couplers_BVALID;\n  wire [511:0]axi_interconnect_0_to_s01_couplers_RDATA;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_RID;\n  wire axi_interconnect_0_to_s01_couplers_RLAST;\n  wire axi_interconnect_0_to_s01_couplers_RREADY;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_RRESP;\n  wire axi_interconnect_0_to_s01_couplers_RVALID;\n  wire [511:0]axi_interconnect_0_to_s01_couplers_WDATA;\n  wire axi_interconnect_0_to_s01_couplers_WLAST;\n  wire axi_interconnect_0_to_s01_couplers_WREADY;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_WSTRB;\n  wire axi_interconnect_0_to_s01_couplers_WVALID;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m00_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m00_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARQOS;\n  wire m00_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m00_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m00_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m00_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWQOS;\n  wire m00_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m00_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_BID;\n  wire m00_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_BRESP;\n  wire m00_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m00_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_RID;\n  wire m00_couplers_to_axi_interconnect_0_RLAST;\n  wire m00_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_RRESP;\n  wire m00_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m00_couplers_to_axi_interconnect_0_WDATA;\n  wire m00_couplers_to_axi_interconnect_0_WLAST;\n  wire m00_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_WSTRB;\n  wire m00_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m01_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m01_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARQOS;\n  wire m01_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m01_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m01_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m01_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWQOS;\n  wire m01_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m01_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_BID;\n  wire m01_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_BRESP;\n  wire m01_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m01_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_RID;\n  wire m01_couplers_to_axi_interconnect_0_RLAST;\n  wire m01_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_RRESP;\n  wire m01_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m01_couplers_to_axi_interconnect_0_WDATA;\n  wire m01_couplers_to_axi_interconnect_0_WLAST;\n  wire m01_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_WSTRB;\n  wire m01_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m02_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m02_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARQOS;\n  wire m02_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m02_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m02_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m02_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWQOS;\n  wire m02_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m02_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_BID;\n  wire m02_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_BRESP;\n  wire m02_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m02_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_RID;\n  wire m02_couplers_to_axi_interconnect_0_RLAST;\n  wire m02_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_RRESP;\n  wire m02_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m02_couplers_to_axi_interconnect_0_WDATA;\n  wire m02_couplers_to_axi_interconnect_0_WLAST;\n  wire m02_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_WSTRB;\n  wire m02_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m03_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m03_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARQOS;\n  wire m03_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m03_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m03_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m03_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWQOS;\n  wire m03_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m03_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_BID;\n  wire m03_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_BRESP;\n  wire m03_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m03_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_RID;\n  wire m03_couplers_to_axi_interconnect_0_RLAST;\n  wire m03_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_RRESP;\n  wire m03_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m03_couplers_to_axi_interconnect_0_WDATA;\n  wire m03_couplers_to_axi_interconnect_0_WLAST;\n  wire m03_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_WSTRB;\n  wire m03_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]s00_couplers_to_xbar_ARADDR;\n  wire [1:0]s00_couplers_to_xbar_ARBURST;\n  wire [3:0]s00_couplers_to_xbar_ARCACHE;\n  wire [5:0]s00_couplers_to_xbar_ARID;\n  wire [7:0]s00_couplers_to_xbar_ARLEN;\n  wire [0:0]s00_couplers_to_xbar_ARLOCK;\n  wire [2:0]s00_couplers_to_xbar_ARPROT;\n  wire [3:0]s00_couplers_to_xbar_ARQOS;\n  wire [0:0]s00_couplers_to_xbar_ARREADY;\n  wire [2:0]s00_couplers_to_xbar_ARSIZE;\n  wire s00_couplers_to_xbar_ARVALID;\n  wire [63:0]s00_couplers_to_xbar_AWADDR;\n  wire [1:0]s00_couplers_to_xbar_AWBURST;\n  wire [3:0]s00_couplers_to_xbar_AWCACHE;\n  wire [5:0]s00_couplers_to_xbar_AWID;\n  wire [7:0]s00_couplers_to_xbar_AWLEN;\n  wire [0:0]s00_couplers_to_xbar_AWLOCK;\n  wire [2:0]s00_couplers_to_xbar_AWPROT;\n  wire [3:0]s00_couplers_to_xbar_AWQOS;\n  wire [0:0]s00_couplers_to_xbar_AWREADY;\n  wire [2:0]s00_couplers_to_xbar_AWSIZE;\n  wire s00_couplers_to_xbar_AWVALID;\n  wire [6:0]s00_couplers_to_xbar_BID;\n  wire s00_couplers_to_xbar_BREADY;\n  wire [1:0]s00_couplers_to_xbar_BRESP;\n  wire [0:0]s00_couplers_to_xbar_BVALID;\n  wire [511:0]s00_couplers_to_xbar_RDATA;\n  wire [6:0]s00_couplers_to_xbar_RID;\n  wire [0:0]s00_couplers_to_xbar_RLAST;\n  wire s00_couplers_to_xbar_RREADY;\n  wire [1:0]s00_couplers_to_xbar_RRESP;\n  wire [0:0]s00_couplers_to_xbar_RVALID;\n  wire [511:0]s00_couplers_to_xbar_WDATA;\n  wire s00_couplers_to_xbar_WLAST;\n  wire [0:0]s00_couplers_to_xbar_WREADY;\n  wire [63:0]s00_couplers_to_xbar_WSTRB;\n  wire s00_couplers_to_xbar_WVALID;\n  wire [63:0]s01_couplers_to_xbar_ARADDR;\n  wire [1:0]s01_couplers_to_xbar_ARBURST;\n  wire [3:0]s01_couplers_to_xbar_ARCACHE;\n  wire [5:0]s01_couplers_to_xbar_ARID;\n  wire [7:0]s01_couplers_to_xbar_ARLEN;\n  wire [0:0]s01_couplers_to_xbar_ARLOCK;\n  wire [2:0]s01_couplers_to_xbar_ARPROT;\n  wire [3:0]s01_couplers_to_xbar_ARQOS;\n  wire [1:1]s01_couplers_to_xbar_ARREADY;\n  wire [2:0]s01_couplers_to_xbar_ARSIZE;\n  wire s01_couplers_to_xbar_ARVALID;\n  wire [63:0]s01_couplers_to_xbar_AWADDR;\n  wire [1:0]s01_couplers_to_xbar_AWBURST;\n  wire [3:0]s01_couplers_to_xbar_AWCACHE;\n  wire [5:0]s01_couplers_to_xbar_AWID;\n  wire [7:0]s01_couplers_to_xbar_AWLEN;\n  wire [0:0]s01_couplers_to_xbar_AWLOCK;\n  wire [2:0]s01_couplers_to_xbar_AWPROT;\n  wire [3:0]s01_couplers_to_xbar_AWQOS;\n  wire [1:1]s01_couplers_to_xbar_AWREADY;\n  wire [2:0]s01_couplers_to_xbar_AWSIZE;\n  wire s01_couplers_to_xbar_AWVALID;\n  wire [13:7]s01_couplers_to_xbar_BID;\n  wire s01_couplers_to_xbar_BREADY;\n  wire [3:2]s01_couplers_to_xbar_BRESP;\n  wire [1:1]s01_couplers_to_xbar_BVALID;\n  wire [1023:512]s01_couplers_to_xbar_RDATA;\n  wire [13:7]s01_couplers_to_xbar_RID;\n  wire [1:1]s01_couplers_to_xbar_RLAST;\n  wire s01_couplers_to_xbar_RREADY;\n  wire [3:2]s01_couplers_to_xbar_RRESP;\n  wire [1:1]s01_couplers_to_xbar_RVALID;\n  wire [511:0]s01_couplers_to_xbar_WDATA;\n  wire s01_couplers_to_xbar_WLAST;\n  wire [1:1]s01_couplers_to_xbar_WREADY;\n  wire [63:0]s01_couplers_to_xbar_WSTRB;\n  wire s01_couplers_to_xbar_WVALID;\n  wire [63:0]xbar_to_m00_couplers_ARADDR;\n  wire [1:0]xbar_to_m00_couplers_ARBURST;\n  wire [3:0]xbar_to_m00_couplers_ARCACHE;\n  wire [6:0]xbar_to_m00_couplers_ARID;\n  wire [7:0]xbar_to_m00_couplers_ARLEN;\n  wire [0:0]xbar_to_m00_couplers_ARLOCK;\n  wire [2:0]xbar_to_m00_couplers_ARPROT;\n  wire [3:0]xbar_to_m00_couplers_ARQOS;\n  wire xbar_to_m00_couplers_ARREADY;\n  wire [3:0]xbar_to_m00_couplers_ARREGION;\n  wire [2:0]xbar_to_m00_couplers_ARSIZE;\n  wire [0:0]xbar_to_m00_couplers_ARVALID;\n  wire [63:0]xbar_to_m00_couplers_AWADDR;\n  wire [1:0]xbar_to_m00_couplers_AWBURST;\n  wire [3:0]xbar_to_m00_couplers_AWCACHE;\n  wire [6:0]xbar_to_m00_couplers_AWID;\n  wire [7:0]xbar_to_m00_couplers_AWLEN;\n  wire [0:0]xbar_to_m00_couplers_AWLOCK;\n  wire [2:0]xbar_to_m00_couplers_AWPROT;\n  wire [3:0]xbar_to_m00_couplers_AWQOS;\n  wire xbar_to_m00_couplers_AWREADY;\n  wire [3:0]xbar_to_m00_couplers_AWREGION;\n  wire [2:0]xbar_to_m00_couplers_AWSIZE;\n  wire [0:0]xbar_to_m00_couplers_AWVALID;\n  wire [6:0]xbar_to_m00_couplers_BID;\n  wire [0:0]xbar_to_m00_couplers_BREADY;\n  wire [1:0]xbar_to_m00_couplers_BRESP;\n  wire xbar_to_m00_couplers_BVALID;\n  wire [511:0]xbar_to_m00_couplers_RDATA;\n  wire [6:0]xbar_to_m00_couplers_RID;\n  wire xbar_to_m00_couplers_RLAST;\n  wire [0:0]xbar_to_m00_couplers_RREADY;\n  wire [1:0]xbar_to_m00_couplers_RRESP;\n  wire xbar_to_m00_couplers_RVALID;\n  wire [511:0]xbar_to_m00_couplers_WDATA;\n  wire [0:0]xbar_to_m00_couplers_WLAST;\n  wire xbar_to_m00_couplers_WREADY;\n  wire [63:0]xbar_to_m00_couplers_WSTRB;\n  wire [0:0]xbar_to_m00_couplers_WVALID;\n  wire [127:64]xbar_to_m01_couplers_ARADDR;\n  wire [3:2]xbar_to_m01_couplers_ARBURST;\n  wire [7:4]xbar_to_m01_couplers_ARCACHE;\n  wire [13:7]xbar_to_m01_couplers_ARID;\n  wire [15:8]xbar_to_m01_couplers_ARLEN;\n  wire [1:1]xbar_to_m01_couplers_ARLOCK;\n  wire [5:3]xbar_to_m01_couplers_ARPROT;\n  wire [7:4]xbar_to_m01_couplers_ARQOS;\n  wire xbar_to_m01_couplers_ARREADY;\n  wire [7:4]xbar_to_m01_couplers_ARREGION;\n  wire [5:3]xbar_to_m01_couplers_ARSIZE;\n  wire [1:1]xbar_to_m01_couplers_ARVALID;\n  wire [127:64]xbar_to_m01_couplers_AWADDR;\n  wire [3:2]xbar_to_m01_couplers_AWBURST;\n  wire [7:4]xbar_to_m01_couplers_AWCACHE;\n  wire [13:7]xbar_to_m01_couplers_AWID;\n  wire [15:8]xbar_to_m01_couplers_AWLEN;\n  wire [1:1]xbar_to_m01_couplers_AWLOCK;\n  wire [5:3]xbar_to_m01_couplers_AWPROT;\n  wire [7:4]xbar_to_m01_couplers_AWQOS;\n  wire xbar_to_m01_couplers_AWREADY;\n  wire [7:4]xbar_to_m01_couplers_AWREGION;\n  wire [5:3]xbar_to_m01_couplers_AWSIZE;\n  wire [1:1]xbar_to_m01_couplers_AWVALID;\n  wire [6:0]xbar_to_m01_couplers_BID;\n  wire [1:1]xbar_to_m01_couplers_BREADY;\n  wire [1:0]xbar_to_m01_couplers_BRESP;\n  wire xbar_to_m01_couplers_BVALID;\n  wire [511:0]xbar_to_m01_couplers_RDATA;\n  wire [6:0]xbar_to_m01_couplers_RID;\n  wire xbar_to_m01_couplers_RLAST;\n  wire [1:1]xbar_to_m01_couplers_RREADY;\n  wire [1:0]xbar_to_m01_couplers_RRESP;\n  wire xbar_to_m01_couplers_RVALID;\n  wire [1023:512]xbar_to_m01_couplers_WDATA;\n  wire [1:1]xbar_to_m01_couplers_WLAST;\n  wire xbar_to_m01_couplers_WREADY;\n  wire [127:64]xbar_to_m01_couplers_WSTRB;\n  wire [1:1]xbar_to_m01_couplers_WVALID;\n  wire [191:128]xbar_to_m02_couplers_ARADDR;\n  wire [5:4]xbar_to_m02_couplers_ARBURST;\n  wire [11:8]xbar_to_m02_couplers_ARCACHE;\n  wire [20:14]xbar_to_m02_couplers_ARID;\n  wire [23:16]xbar_to_m02_couplers_ARLEN;\n  wire [2:2]xbar_to_m02_couplers_ARLOCK;\n  wire [8:6]xbar_to_m02_couplers_ARPROT;\n  wire [11:8]xbar_to_m02_couplers_ARQOS;\n  wire xbar_to_m02_couplers_ARREADY;\n  wire [11:8]xbar_to_m02_couplers_ARREGION;\n  wire [8:6]xbar_to_m02_couplers_ARSIZE;\n  wire [2:2]xbar_to_m02_couplers_ARVALID;\n  wire [191:128]xbar_to_m02_couplers_AWADDR;\n  wire [5:4]xbar_to_m02_couplers_AWBURST;\n  wire [11:8]xbar_to_m02_couplers_AWCACHE;\n  wire [20:14]xbar_to_m02_couplers_AWID;\n  wire [23:16]xbar_to_m02_couplers_AWLEN;\n  wire [2:2]xbar_to_m02_couplers_AWLOCK;\n  wire [8:6]xbar_to_m02_couplers_AWPROT;\n  wire [11:8]xbar_to_m02_couplers_AWQOS;\n  wire xbar_to_m02_couplers_AWREADY;\n  wire [11:8]xbar_to_m02_couplers_AWREGION;\n  wire [8:6]xbar_to_m02_couplers_AWSIZE;\n  wire [2:2]xbar_to_m02_couplers_AWVALID;\n  wire [6:0]xbar_to_m02_couplers_BID;\n  wire [2:2]xbar_to_m02_couplers_BREADY;\n  wire [1:0]xbar_to_m02_couplers_BRESP;\n  wire xbar_to_m02_couplers_BVALID;\n  wire [511:0]xbar_to_m02_couplers_RDATA;\n  wire [6:0]xbar_to_m02_couplers_RID;\n  wire xbar_to_m02_couplers_RLAST;\n  wire [2:2]xbar_to_m02_couplers_RREADY;\n  wire [1:0]xbar_to_m02_couplers_RRESP;\n  wire xbar_to_m02_couplers_RVALID;\n  wire [1535:1024]xbar_to_m02_couplers_WDATA;\n  wire [2:2]xbar_to_m02_couplers_WLAST;\n  wire xbar_to_m02_couplers_WREADY;\n  wire [191:128]xbar_to_m02_couplers_WSTRB;\n  wire [2:2]xbar_to_m02_couplers_WVALID;\n  wire [255:192]xbar_to_m03_couplers_ARADDR;\n  wire [7:6]xbar_to_m03_couplers_ARBURST;\n  wire [15:12]xbar_to_m03_couplers_ARCACHE;\n  wire [27:21]xbar_to_m03_couplers_ARID;\n  wire [31:24]xbar_to_m03_couplers_ARLEN;\n  wire [3:3]xbar_to_m03_couplers_ARLOCK;\n  wire [11:9]xbar_to_m03_couplers_ARPROT;\n  wire [15:12]xbar_to_m03_couplers_ARQOS;\n  wire xbar_to_m03_couplers_ARREADY;\n  wire [15:12]xbar_to_m03_couplers_ARREGION;\n  wire [11:9]xbar_to_m03_couplers_ARSIZE;\n  wire [3:3]xbar_to_m03_couplers_ARVALID;\n  wire [255:192]xbar_to_m03_couplers_AWADDR;\n  wire [7:6]xbar_to_m03_couplers_AWBURST;\n  wire [15:12]xbar_to_m03_couplers_AWCACHE;\n  wire [27:21]xbar_to_m03_couplers_AWID;\n  wire [31:24]xbar_to_m03_couplers_AWLEN;\n  wire [3:3]xbar_to_m03_couplers_AWLOCK;\n  wire [11:9]xbar_to_m03_couplers_AWPROT;\n  wire [15:12]xbar_to_m03_couplers_AWQOS;\n  wire xbar_to_m03_couplers_AWREADY;\n  wire [15:12]xbar_to_m03_couplers_AWREGION;\n  wire [11:9]xbar_to_m03_couplers_AWSIZE;\n  wire [3:3]xbar_to_m03_couplers_AWVALID;\n  wire [6:0]xbar_to_m03_couplers_BID;\n  wire [3:3]xbar_to_m03_couplers_BREADY;\n  wire [1:0]xbar_to_m03_couplers_BRESP;\n  wire xbar_to_m03_couplers_BVALID;\n  wire [511:0]xbar_to_m03_couplers_RDATA;\n  wire [6:0]xbar_to_m03_couplers_RID;\n  wire xbar_to_m03_couplers_RLAST;\n  wire [3:3]xbar_to_m03_couplers_RREADY;\n  wire [1:0]xbar_to_m03_couplers_RRESP;\n  wire xbar_to_m03_couplers_RVALID;\n  wire [2047:1536]xbar_to_m03_couplers_WDATA;\n  wire [3:3]xbar_to_m03_couplers_WLAST;\n  wire xbar_to_m03_couplers_WREADY;\n  wire [255:192]xbar_to_m03_couplers_WSTRB;\n  wire [3:3]xbar_to_m03_couplers_WVALID;\n\n  assign M00_AXI_araddr[63:0] = m00_couplers_to_axi_interconnect_0_ARADDR;\n  assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_interconnect_0_ARBURST;\n  assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M00_AXI_arid[6:0] = m00_couplers_to_axi_interconnect_0_ARID;\n  assign M00_AXI_arlen[7:0] = m00_couplers_to_axi_interconnect_0_ARLEN;\n  assign M00_AXI_arlock[0] = m00_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_interconnect_0_ARPROT;\n  assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_interconnect_0_ARQOS;\n  assign M00_AXI_arregion[3:0] = m00_couplers_to_axi_interconnect_0_ARREGION;\n  assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M00_AXI_arvalid = m00_couplers_to_axi_interconnect_0_ARVALID;\n  assign M00_AXI_awaddr[63:0] = m00_couplers_to_axi_interconnect_0_AWADDR;\n  assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_interconnect_0_AWBURST;\n  assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M00_AXI_awid[6:0] = m00_couplers_to_axi_interconnect_0_AWID;\n  assign M00_AXI_awlen[7:0] = m00_couplers_to_axi_interconnect_0_AWLEN;\n  assign M00_AXI_awlock[0] = m00_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_interconnect_0_AWPROT;\n  assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_interconnect_0_AWQOS;\n  assign M00_AXI_awregion[3:0] = m00_couplers_to_axi_interconnect_0_AWREGION;\n  assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M00_AXI_awvalid = m00_couplers_to_axi_interconnect_0_AWVALID;\n  assign M00_AXI_bready = m00_couplers_to_axi_interconnect_0_BREADY;\n  assign M00_AXI_rready = m00_couplers_to_axi_interconnect_0_RREADY;\n  assign M00_AXI_wdata[511:0] = m00_couplers_to_axi_interconnect_0_WDATA;\n  assign M00_AXI_wlast = m00_couplers_to_axi_interconnect_0_WLAST;\n  assign M00_AXI_wstrb[63:0] = m00_couplers_to_axi_interconnect_0_WSTRB;\n  assign M00_AXI_wvalid = m00_couplers_to_axi_interconnect_0_WVALID;\n  assign M01_AXI_araddr[63:0] = m01_couplers_to_axi_interconnect_0_ARADDR;\n  assign M01_AXI_arburst[1:0] = m01_couplers_to_axi_interconnect_0_ARBURST;\n  assign M01_AXI_arcache[3:0] = m01_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M01_AXI_arid[6:0] = m01_couplers_to_axi_interconnect_0_ARID;\n  assign M01_AXI_arlen[7:0] = m01_couplers_to_axi_interconnect_0_ARLEN;\n  assign M01_AXI_arlock[0] = m01_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M01_AXI_arprot[2:0] = m01_couplers_to_axi_interconnect_0_ARPROT;\n  assign M01_AXI_arqos[3:0] = m01_couplers_to_axi_interconnect_0_ARQOS;\n  assign M01_AXI_arregion[3:0] = m01_couplers_to_axi_interconnect_0_ARREGION;\n  assign M01_AXI_arsize[2:0] = m01_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M01_AXI_arvalid = m01_couplers_to_axi_interconnect_0_ARVALID;\n  assign M01_AXI_awaddr[63:0] = m01_couplers_to_axi_interconnect_0_AWADDR;\n  assign M01_AXI_awburst[1:0] = m01_couplers_to_axi_interconnect_0_AWBURST;\n  assign M01_AXI_awcache[3:0] = m01_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M01_AXI_awid[6:0] = m01_couplers_to_axi_interconnect_0_AWID;\n  assign M01_AXI_awlen[7:0] = m01_couplers_to_axi_interconnect_0_AWLEN;\n  assign M01_AXI_awlock[0] = m01_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M01_AXI_awprot[2:0] = m01_couplers_to_axi_interconnect_0_AWPROT;\n  assign M01_AXI_awqos[3:0] = m01_couplers_to_axi_interconnect_0_AWQOS;\n  assign M01_AXI_awregion[3:0] = m01_couplers_to_axi_interconnect_0_AWREGION;\n  assign M01_AXI_awsize[2:0] = m01_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M01_AXI_awvalid = m01_couplers_to_axi_interconnect_0_AWVALID;\n  assign M01_AXI_bready = m01_couplers_to_axi_interconnect_0_BREADY;\n  assign M01_AXI_rready = m01_couplers_to_axi_interconnect_0_RREADY;\n  assign M01_AXI_wdata[511:0] = m01_couplers_to_axi_interconnect_0_WDATA;\n  assign M01_AXI_wlast = m01_couplers_to_axi_interconnect_0_WLAST;\n  assign M01_AXI_wstrb[63:0] = m01_couplers_to_axi_interconnect_0_WSTRB;\n  assign M01_AXI_wvalid = m01_couplers_to_axi_interconnect_0_WVALID;\n  assign M02_AXI_araddr[63:0] = m02_couplers_to_axi_interconnect_0_ARADDR;\n  assign M02_AXI_arburst[1:0] = m02_couplers_to_axi_interconnect_0_ARBURST;\n  assign M02_AXI_arcache[3:0] = m02_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M02_AXI_arid[6:0] = m02_couplers_to_axi_interconnect_0_ARID;\n  assign M02_AXI_arlen[7:0] = m02_couplers_to_axi_interconnect_0_ARLEN;\n  assign M02_AXI_arlock[0] = m02_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M02_AXI_arprot[2:0] = m02_couplers_to_axi_interconnect_0_ARPROT;\n  assign M02_AXI_arqos[3:0] = m02_couplers_to_axi_interconnect_0_ARQOS;\n  assign M02_AXI_arregion[3:0] = m02_couplers_to_axi_interconnect_0_ARREGION;\n  assign M02_AXI_arsize[2:0] = m02_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M02_AXI_arvalid = m02_couplers_to_axi_interconnect_0_ARVALID;\n  assign M02_AXI_awaddr[63:0] = m02_couplers_to_axi_interconnect_0_AWADDR;\n  assign M02_AXI_awburst[1:0] = m02_couplers_to_axi_interconnect_0_AWBURST;\n  assign M02_AXI_awcache[3:0] = m02_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M02_AXI_awid[6:0] = m02_couplers_to_axi_interconnect_0_AWID;\n  assign M02_AXI_awlen[7:0] = m02_couplers_to_axi_interconnect_0_AWLEN;\n  assign M02_AXI_awlock[0] = m02_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M02_AXI_awprot[2:0] = m02_couplers_to_axi_interconnect_0_AWPROT;\n  assign M02_AXI_awqos[3:0] = m02_couplers_to_axi_interconnect_0_AWQOS;\n  assign M02_AXI_awregion[3:0] = m02_couplers_to_axi_interconnect_0_AWREGION;\n  assign M02_AXI_awsize[2:0] = m02_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M02_AXI_awvalid = m02_couplers_to_axi_interconnect_0_AWVALID;\n  assign M02_AXI_bready = m02_couplers_to_axi_interconnect_0_BREADY;\n  assign M02_AXI_rready = m02_couplers_to_axi_interconnect_0_RREADY;\n  assign M02_AXI_wdata[511:0] = m02_couplers_to_axi_interconnect_0_WDATA;\n  assign M02_AXI_wlast = m02_couplers_to_axi_interconnect_0_WLAST;\n  assign M02_AXI_wstrb[63:0] = m02_couplers_to_axi_interconnect_0_WSTRB;\n  assign M02_AXI_wvalid = m02_couplers_to_axi_interconnect_0_WVALID;\n  assign M03_AXI_araddr[63:0] = m03_couplers_to_axi_interconnect_0_ARADDR;\n  assign M03_AXI_arburst[1:0] = m03_couplers_to_axi_interconnect_0_ARBURST;\n  assign M03_AXI_arcache[3:0] = m03_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M03_AXI_arid[6:0] = m03_couplers_to_axi_interconnect_0_ARID;\n  assign M03_AXI_arlen[7:0] = m03_couplers_to_axi_interconnect_0_ARLEN;\n  assign M03_AXI_arlock[0] = m03_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M03_AXI_arprot[2:0] = m03_couplers_to_axi_interconnect_0_ARPROT;\n  assign M03_AXI_arqos[3:0] = m03_couplers_to_axi_interconnect_0_ARQOS;\n  assign M03_AXI_arregion[3:0] = m03_couplers_to_axi_interconnect_0_ARREGION;\n  assign M03_AXI_arsize[2:0] = m03_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M03_AXI_arvalid = m03_couplers_to_axi_interconnect_0_ARVALID;\n  assign M03_AXI_awaddr[63:0] = m03_couplers_to_axi_interconnect_0_AWADDR;\n  assign M03_AXI_awburst[1:0] = m03_couplers_to_axi_interconnect_0_AWBURST;\n  assign M03_AXI_awcache[3:0] = m03_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M03_AXI_awid[6:0] = m03_couplers_to_axi_interconnect_0_AWID;\n  assign M03_AXI_awlen[7:0] = m03_couplers_to_axi_interconnect_0_AWLEN;\n  assign M03_AXI_awlock[0] = m03_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M03_AXI_awprot[2:0] = m03_couplers_to_axi_interconnect_0_AWPROT;\n  assign M03_AXI_awqos[3:0] = m03_couplers_to_axi_interconnect_0_AWQOS;\n  assign M03_AXI_awregion[3:0] = m03_couplers_to_axi_interconnect_0_AWREGION;\n  assign M03_AXI_awsize[2:0] = m03_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M03_AXI_awvalid = m03_couplers_to_axi_interconnect_0_AWVALID;\n  assign M03_AXI_bready = m03_couplers_to_axi_interconnect_0_BREADY;\n  assign M03_AXI_rready = m03_couplers_to_axi_interconnect_0_RREADY;\n  assign M03_AXI_wdata[511:0] = m03_couplers_to_axi_interconnect_0_WDATA;\n  assign M03_AXI_wlast = m03_couplers_to_axi_interconnect_0_WLAST;\n  assign M03_AXI_wstrb[63:0] = m03_couplers_to_axi_interconnect_0_WSTRB;\n  assign M03_AXI_wvalid = m03_couplers_to_axi_interconnect_0_WVALID;\n  assign S00_AXI_arready = axi_interconnect_0_to_s00_couplers_ARREADY;\n  assign S00_AXI_awready = axi_interconnect_0_to_s00_couplers_AWREADY;\n  assign S00_AXI_bid[5:0] = axi_interconnect_0_to_s00_couplers_BID;\n  assign S00_AXI_bresp[1:0] = axi_interconnect_0_to_s00_couplers_BRESP;\n  assign S00_AXI_bvalid = axi_interconnect_0_to_s00_couplers_BVALID;\n  assign S00_AXI_rdata[511:0] = axi_interconnect_0_to_s00_couplers_RDATA;\n  assign S00_AXI_rid[5:0] = axi_interconnect_0_to_s00_couplers_RID;\n  assign S00_AXI_rlast = axi_interconnect_0_to_s00_couplers_RLAST;\n  assign S00_AXI_rresp[1:0] = axi_interconnect_0_to_s00_couplers_RRESP;\n  assign S00_AXI_rvalid = axi_interconnect_0_to_s00_couplers_RVALID;\n  assign S00_AXI_wready = axi_interconnect_0_to_s00_couplers_WREADY;\n  assign S01_AXI_arready = axi_interconnect_0_to_s01_couplers_ARREADY;\n  assign S01_AXI_awready = axi_interconnect_0_to_s01_couplers_AWREADY;\n  assign S01_AXI_bid[5:0] = axi_interconnect_0_to_s01_couplers_BID;\n  assign S01_AXI_bresp[1:0] = axi_interconnect_0_to_s01_couplers_BRESP;\n  assign S01_AXI_bvalid = axi_interconnect_0_to_s01_couplers_BVALID;\n  assign S01_AXI_rdata[511:0] = axi_interconnect_0_to_s01_couplers_RDATA;\n  assign S01_AXI_rid[5:0] = axi_interconnect_0_to_s01_couplers_RID;\n  assign S01_AXI_rlast = axi_interconnect_0_to_s01_couplers_RLAST;\n  assign S01_AXI_rresp[1:0] = axi_interconnect_0_to_s01_couplers_RRESP;\n  assign S01_AXI_rvalid = axi_interconnect_0_to_s01_couplers_RVALID;\n  assign S01_AXI_wready = axi_interconnect_0_to_s01_couplers_WREADY;\n  assign axi_interconnect_0_ACLK_net = ACLK;\n  assign axi_interconnect_0_ARESETN_net = ARESETN;\n  assign axi_interconnect_0_to_s00_couplers_ARADDR = S00_AXI_araddr[63:0];\n  assign axi_interconnect_0_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];\n  assign axi_interconnect_0_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARID = S00_AXI_arid[5:0];\n  assign axi_interconnect_0_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0];\n  assign axi_interconnect_0_to_s00_couplers_ARLOCK = S00_AXI_arlock[0];\n  assign axi_interconnect_0_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];\n  assign axi_interconnect_0_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARREGION = S00_AXI_arregion[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];\n  assign axi_interconnect_0_to_s00_couplers_ARVALID = S00_AXI_arvalid;\n  assign axi_interconnect_0_to_s00_couplers_AWADDR = S00_AXI_awaddr[63:0];\n  assign axi_interconnect_0_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];\n  assign axi_interconnect_0_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWID = S00_AXI_awid[5:0];\n  assign axi_interconnect_0_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0];\n  assign axi_interconnect_0_to_s00_couplers_AWLOCK = S00_AXI_awlock[0];\n  assign axi_interconnect_0_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];\n  assign axi_interconnect_0_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWREGION = S00_AXI_awregion[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];\n  assign axi_interconnect_0_to_s00_couplers_AWVALID = S00_AXI_awvalid;\n  assign axi_interconnect_0_to_s00_couplers_BREADY = S00_AXI_bready;\n  assign axi_interconnect_0_to_s00_couplers_RREADY = S00_AXI_rready;\n  assign axi_interconnect_0_to_s00_couplers_WDATA = S00_AXI_wdata[511:0];\n  assign axi_interconnect_0_to_s00_couplers_WLAST = S00_AXI_wlast;\n  assign axi_interconnect_0_to_s00_couplers_WSTRB = S00_AXI_wstrb[63:0];\n  assign axi_interconnect_0_to_s00_couplers_WVALID = S00_AXI_wvalid;\n  assign axi_interconnect_0_to_s01_couplers_ARADDR = S01_AXI_araddr[63:0];\n  assign axi_interconnect_0_to_s01_couplers_ARBURST = S01_AXI_arburst[1:0];\n  assign axi_interconnect_0_to_s01_couplers_ARCACHE = S01_AXI_arcache[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARID = S01_AXI_arid[5:0];\n  assign axi_interconnect_0_to_s01_couplers_ARLEN = S01_AXI_arlen[7:0];\n  assign axi_interconnect_0_to_s01_couplers_ARLOCK = S01_AXI_arlock[0];\n  assign axi_interconnect_0_to_s01_couplers_ARPROT = S01_AXI_arprot[2:0];\n  assign axi_interconnect_0_to_s01_couplers_ARQOS = S01_AXI_arqos[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARREGION = S01_AXI_arregion[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARSIZE = S01_AXI_arsize[2:0];\n  assign axi_interconnect_0_to_s01_couplers_ARVALID = S01_AXI_arvalid;\n  assign axi_interconnect_0_to_s01_couplers_AWADDR = S01_AXI_awaddr[63:0];\n  assign axi_interconnect_0_to_s01_couplers_AWBURST = S01_AXI_awburst[1:0];\n  assign axi_interconnect_0_to_s01_couplers_AWCACHE = S01_AXI_awcache[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWID = S01_AXI_awid[5:0];\n  assign axi_interconnect_0_to_s01_couplers_AWLEN = S01_AXI_awlen[7:0];\n  assign axi_interconnect_0_to_s01_couplers_AWLOCK = S01_AXI_awlock[0];\n  assign axi_interconnect_0_to_s01_couplers_AWPROT = S01_AXI_awprot[2:0];\n  assign axi_interconnect_0_to_s01_couplers_AWQOS = S01_AXI_awqos[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWREGION = S01_AXI_awregion[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWSIZE = S01_AXI_awsize[2:0];\n  assign axi_interconnect_0_to_s01_couplers_AWVALID = S01_AXI_awvalid;\n  assign axi_interconnect_0_to_s01_couplers_BREADY = S01_AXI_bready;\n  assign axi_interconnect_0_to_s01_couplers_RREADY = S01_AXI_rready;\n  assign axi_interconnect_0_to_s01_couplers_WDATA = S01_AXI_wdata[511:0];\n  assign axi_interconnect_0_to_s01_couplers_WLAST = S01_AXI_wlast;\n  assign axi_interconnect_0_to_s01_couplers_WSTRB = S01_AXI_wstrb[63:0];\n  assign axi_interconnect_0_to_s01_couplers_WVALID = S01_AXI_wvalid;\n  assign m00_couplers_to_axi_interconnect_0_ARREADY = M00_AXI_arready;\n  assign m00_couplers_to_axi_interconnect_0_AWREADY = M00_AXI_awready;\n  assign m00_couplers_to_axi_interconnect_0_BID = M00_AXI_bid[6:0];\n  assign m00_couplers_to_axi_interconnect_0_BRESP = M00_AXI_bresp[1:0];\n  assign m00_couplers_to_axi_interconnect_0_BVALID = M00_AXI_bvalid;\n  assign m00_couplers_to_axi_interconnect_0_RDATA = M00_AXI_rdata[511:0];\n  assign m00_couplers_to_axi_interconnect_0_RID = M00_AXI_rid[6:0];\n  assign m00_couplers_to_axi_interconnect_0_RLAST = M00_AXI_rlast;\n  assign m00_couplers_to_axi_interconnect_0_RRESP = M00_AXI_rresp[1:0];\n  assign m00_couplers_to_axi_interconnect_0_RVALID = M00_AXI_rvalid;\n  assign m00_couplers_to_axi_interconnect_0_WREADY = M00_AXI_wready;\n  assign m01_couplers_to_axi_interconnect_0_ARREADY = M01_AXI_arready;\n  assign m01_couplers_to_axi_interconnect_0_AWREADY = M01_AXI_awready;\n  assign m01_couplers_to_axi_interconnect_0_BID = M01_AXI_bid[6:0];\n  assign m01_couplers_to_axi_interconnect_0_BRESP = M01_AXI_bresp[1:0];\n  assign m01_couplers_to_axi_interconnect_0_BVALID = M01_AXI_bvalid;\n  assign m01_couplers_to_axi_interconnect_0_RDATA = M01_AXI_rdata[511:0];\n  assign m01_couplers_to_axi_interconnect_0_RID = M01_AXI_rid[6:0];\n  assign m01_couplers_to_axi_interconnect_0_RLAST = M01_AXI_rlast;\n  assign m01_couplers_to_axi_interconnect_0_RRESP = M01_AXI_rresp[1:0];\n  assign m01_couplers_to_axi_interconnect_0_RVALID = M01_AXI_rvalid;\n  assign m01_couplers_to_axi_interconnect_0_WREADY = M01_AXI_wready;\n  assign m02_couplers_to_axi_interconnect_0_ARREADY = M02_AXI_arready;\n  assign m02_couplers_to_axi_interconnect_0_AWREADY = M02_AXI_awready;\n  assign m02_couplers_to_axi_interconnect_0_BID = M02_AXI_bid[6:0];\n  assign m02_couplers_to_axi_interconnect_0_BRESP = M02_AXI_bresp[1:0];\n  assign m02_couplers_to_axi_interconnect_0_BVALID = M02_AXI_bvalid;\n  assign m02_couplers_to_axi_interconnect_0_RDATA = M02_AXI_rdata[511:0];\n  assign m02_couplers_to_axi_interconnect_0_RID = M02_AXI_rid[6:0];\n  assign m02_couplers_to_axi_interconnect_0_RLAST = M02_AXI_rlast;\n  assign m02_couplers_to_axi_interconnect_0_RRESP = M02_AXI_rresp[1:0];\n  assign m02_couplers_to_axi_interconnect_0_RVALID = M02_AXI_rvalid;\n  assign m02_couplers_to_axi_interconnect_0_WREADY = M02_AXI_wready;\n  assign m03_couplers_to_axi_interconnect_0_ARREADY = M03_AXI_arready;\n  assign m03_couplers_to_axi_interconnect_0_AWREADY = M03_AXI_awready;\n  assign m03_couplers_to_axi_interconnect_0_BID = M03_AXI_bid[6:0];\n  assign m03_couplers_to_axi_interconnect_0_BRESP = M03_AXI_bresp[1:0];\n  assign m03_couplers_to_axi_interconnect_0_BVALID = M03_AXI_bvalid;\n  assign m03_couplers_to_axi_interconnect_0_RDATA = M03_AXI_rdata[511:0];\n  assign m03_couplers_to_axi_interconnect_0_RID = M03_AXI_rid[6:0];\n  assign m03_couplers_to_axi_interconnect_0_RLAST = M03_AXI_rlast;\n  assign m03_couplers_to_axi_interconnect_0_RRESP = M03_AXI_rresp[1:0];\n  assign m03_couplers_to_axi_interconnect_0_RVALID = M03_AXI_rvalid;\n  assign m03_couplers_to_axi_interconnect_0_WREADY = M03_AXI_wready;\n  m00_couplers_imp_1QBJ6U2 m00_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m00_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m00_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m00_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m00_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m00_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m00_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m00_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m00_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m00_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m00_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m00_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m00_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m00_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m00_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m00_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m00_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m00_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m00_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m00_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m00_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m00_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m00_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m00_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m00_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m00_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m00_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m00_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m00_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m00_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m00_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m00_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m00_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m00_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m00_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m00_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m00_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m00_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m00_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m00_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m00_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m00_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m00_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m00_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m00_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m00_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m00_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m00_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m00_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m00_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m00_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m00_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m00_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m00_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m00_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m00_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m00_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m00_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m00_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m00_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m00_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m00_couplers_BID),\n        .S_AXI_bready(xbar_to_m00_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m00_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m00_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m00_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m00_couplers_RID),\n        .S_AXI_rlast(xbar_to_m00_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m00_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m00_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m00_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m00_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m00_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m00_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m00_couplers_WVALID));\n  m01_couplers_imp_10IMR9A m01_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m01_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m01_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m01_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m01_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m01_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m01_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m01_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m01_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m01_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m01_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m01_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m01_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m01_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m01_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m01_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m01_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m01_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m01_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m01_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m01_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m01_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m01_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m01_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m01_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m01_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m01_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m01_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m01_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m01_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m01_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m01_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m01_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m01_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m01_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m01_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m01_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m01_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m01_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m01_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m01_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m01_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m01_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m01_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m01_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m01_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m01_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m01_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m01_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m01_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m01_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m01_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m01_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m01_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m01_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m01_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m01_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m01_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m01_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m01_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m01_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m01_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m01_couplers_BID),\n        .S_AXI_bready(xbar_to_m01_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m01_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m01_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m01_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m01_couplers_RID),\n        .S_AXI_rlast(xbar_to_m01_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m01_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m01_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m01_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m01_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m01_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m01_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m01_couplers_WVALID));\n  m02_couplers_imp_APDUS2 m02_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m02_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m02_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m02_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m02_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m02_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m02_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m02_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m02_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m02_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m02_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m02_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m02_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m02_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m02_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m02_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m02_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m02_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m02_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m02_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m02_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m02_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m02_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m02_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m02_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m02_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m02_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m02_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m02_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m02_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m02_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m02_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m02_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m02_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m02_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m02_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m02_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m02_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m02_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m02_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m02_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m02_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m02_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m02_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m02_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m02_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m02_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m02_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m02_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m02_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m02_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m02_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m02_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m02_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m02_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m02_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m02_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m02_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m02_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m02_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m02_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m02_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m02_couplers_BID),\n        .S_AXI_bready(xbar_to_m02_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m02_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m02_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m02_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m02_couplers_RID),\n        .S_AXI_rlast(xbar_to_m02_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m02_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m02_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m02_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m02_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m02_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m02_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m02_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m02_couplers_WVALID));\n  m03_couplers_imp_JAYOMU m03_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m03_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m03_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m03_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m03_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m03_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m03_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m03_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m03_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m03_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m03_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m03_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m03_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m03_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m03_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m03_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m03_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m03_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m03_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m03_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m03_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m03_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m03_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m03_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m03_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m03_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m03_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m03_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m03_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m03_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m03_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m03_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m03_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m03_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m03_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m03_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m03_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m03_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m03_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m03_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m03_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m03_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m03_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m03_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m03_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m03_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m03_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m03_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m03_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m03_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m03_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m03_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m03_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m03_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m03_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m03_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m03_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m03_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m03_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m03_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m03_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m03_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m03_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m03_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m03_couplers_BID),\n        .S_AXI_bready(xbar_to_m03_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m03_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m03_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m03_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m03_couplers_RID),\n        .S_AXI_rlast(xbar_to_m03_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m03_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m03_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m03_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m03_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m03_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m03_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m03_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m03_couplers_WVALID));\n  s00_couplers_imp_QICM5G s00_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(s00_couplers_to_xbar_ARADDR),\n        .M_AXI_arburst(s00_couplers_to_xbar_ARBURST),\n        .M_AXI_arcache(s00_couplers_to_xbar_ARCACHE),\n        .M_AXI_arid(s00_couplers_to_xbar_ARID),\n        .M_AXI_arlen(s00_couplers_to_xbar_ARLEN),\n        .M_AXI_arlock(s00_couplers_to_xbar_ARLOCK),\n        .M_AXI_arprot(s00_couplers_to_xbar_ARPROT),\n        .M_AXI_arqos(s00_couplers_to_xbar_ARQOS),\n        .M_AXI_arready(s00_couplers_to_xbar_ARREADY),\n        .M_AXI_arsize(s00_couplers_to_xbar_ARSIZE),\n        .M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),\n        .M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),\n        .M_AXI_awburst(s00_couplers_to_xbar_AWBURST),\n        .M_AXI_awcache(s00_couplers_to_xbar_AWCACHE),\n        .M_AXI_awid(s00_couplers_to_xbar_AWID),\n        .M_AXI_awlen(s00_couplers_to_xbar_AWLEN),\n        .M_AXI_awlock(s00_couplers_to_xbar_AWLOCK),\n        .M_AXI_awprot(s00_couplers_to_xbar_AWPROT),\n        .M_AXI_awqos(s00_couplers_to_xbar_AWQOS),\n        .M_AXI_awready(s00_couplers_to_xbar_AWREADY),\n        .M_AXI_awsize(s00_couplers_to_xbar_AWSIZE),\n        .M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),\n        .M_AXI_bid(s00_couplers_to_xbar_BID),\n        .M_AXI_bready(s00_couplers_to_xbar_BREADY),\n        .M_AXI_bresp(s00_couplers_to_xbar_BRESP),\n        .M_AXI_bvalid(s00_couplers_to_xbar_BVALID),\n        .M_AXI_rdata(s00_couplers_to_xbar_RDATA),\n        .M_AXI_rid(s00_couplers_to_xbar_RID),\n        .M_AXI_rlast(s00_couplers_to_xbar_RLAST),\n        .M_AXI_rready(s00_couplers_to_xbar_RREADY),\n        .M_AXI_rresp(s00_couplers_to_xbar_RRESP),\n        .M_AXI_rvalid(s00_couplers_to_xbar_RVALID),\n        .M_AXI_wdata(s00_couplers_to_xbar_WDATA),\n        .M_AXI_wlast(s00_couplers_to_xbar_WLAST),\n        .M_AXI_wready(s00_couplers_to_xbar_WREADY),\n        .M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),\n        .M_AXI_wvalid(s00_couplers_to_xbar_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(axi_interconnect_0_to_s00_couplers_ARADDR),\n        .S_AXI_arburst(axi_interconnect_0_to_s00_couplers_ARBURST),\n        .S_AXI_arcache(axi_interconnect_0_to_s00_couplers_ARCACHE),\n        .S_AXI_arid(axi_interconnect_0_to_s00_couplers_ARID),\n        .S_AXI_arlen(axi_interconnect_0_to_s00_couplers_ARLEN),\n        .S_AXI_arlock(axi_interconnect_0_to_s00_couplers_ARLOCK),\n        .S_AXI_arprot(axi_interconnect_0_to_s00_couplers_ARPROT),\n        .S_AXI_arqos(axi_interconnect_0_to_s00_couplers_ARQOS),\n        .S_AXI_arready(axi_interconnect_0_to_s00_couplers_ARREADY),\n        .S_AXI_arregion(axi_interconnect_0_to_s00_couplers_ARREGION),\n        .S_AXI_arsize(axi_interconnect_0_to_s00_couplers_ARSIZE),\n        .S_AXI_arvalid(axi_interconnect_0_to_s00_couplers_ARVALID),\n        .S_AXI_awaddr(axi_interconnect_0_to_s00_couplers_AWADDR),\n        .S_AXI_awburst(axi_interconnect_0_to_s00_couplers_AWBURST),\n        .S_AXI_awcache(axi_interconnect_0_to_s00_couplers_AWCACHE),\n        .S_AXI_awid(axi_interconnect_0_to_s00_couplers_AWID),\n        .S_AXI_awlen(axi_interconnect_0_to_s00_couplers_AWLEN),\n        .S_AXI_awlock(axi_interconnect_0_to_s00_couplers_AWLOCK),\n        .S_AXI_awprot(axi_interconnect_0_to_s00_couplers_AWPROT),\n        .S_AXI_awqos(axi_interconnect_0_to_s00_couplers_AWQOS),\n        .S_AXI_awready(axi_interconnect_0_to_s00_couplers_AWREADY),\n        .S_AXI_awregion(axi_interconnect_0_to_s00_couplers_AWREGION),\n        .S_AXI_awsize(axi_interconnect_0_to_s00_couplers_AWSIZE),\n        .S_AXI_awvalid(axi_interconnect_0_to_s00_couplers_AWVALID),\n        .S_AXI_bid(axi_interconnect_0_to_s00_couplers_BID),\n        .S_AXI_bready(axi_interconnect_0_to_s00_couplers_BREADY),\n        .S_AXI_bresp(axi_interconnect_0_to_s00_couplers_BRESP),\n        .S_AXI_bvalid(axi_interconnect_0_to_s00_couplers_BVALID),\n        .S_AXI_rdata(axi_interconnect_0_to_s00_couplers_RDATA),\n        .S_AXI_rid(axi_interconnect_0_to_s00_couplers_RID),\n        .S_AXI_rlast(axi_interconnect_0_to_s00_couplers_RLAST),\n        .S_AXI_rready(axi_interconnect_0_to_s00_couplers_RREADY),\n        .S_AXI_rresp(axi_interconnect_0_to_s00_couplers_RRESP),\n        .S_AXI_rvalid(axi_interconnect_0_to_s00_couplers_RVALID),\n        .S_AXI_wdata(axi_interconnect_0_to_s00_couplers_WDATA),\n        .S_AXI_wlast(axi_interconnect_0_to_s00_couplers_WLAST),\n        .S_AXI_wready(axi_interconnect_0_to_s00_couplers_WREADY),\n        .S_AXI_wstrb(axi_interconnect_0_to_s00_couplers_WSTRB),\n        .S_AXI_wvalid(axi_interconnect_0_to_s00_couplers_WVALID));\n  s01_couplers_imp_GSTXQ8 s01_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(s01_couplers_to_xbar_ARADDR),\n        .M_AXI_arburst(s01_couplers_to_xbar_ARBURST),\n        .M_AXI_arcache(s01_couplers_to_xbar_ARCACHE),\n        .M_AXI_arid(s01_couplers_to_xbar_ARID),\n        .M_AXI_arlen(s01_couplers_to_xbar_ARLEN),\n        .M_AXI_arlock(s01_couplers_to_xbar_ARLOCK),\n        .M_AXI_arprot(s01_couplers_to_xbar_ARPROT),\n        .M_AXI_arqos(s01_couplers_to_xbar_ARQOS),\n        .M_AXI_arready(s01_couplers_to_xbar_ARREADY),\n        .M_AXI_arsize(s01_couplers_to_xbar_ARSIZE),\n        .M_AXI_arvalid(s01_couplers_to_xbar_ARVALID),\n        .M_AXI_awaddr(s01_couplers_to_xbar_AWADDR),\n        .M_AXI_awburst(s01_couplers_to_xbar_AWBURST),\n        .M_AXI_awcache(s01_couplers_to_xbar_AWCACHE),\n        .M_AXI_awid(s01_couplers_to_xbar_AWID),\n        .M_AXI_awlen(s01_couplers_to_xbar_AWLEN),\n        .M_AXI_awlock(s01_couplers_to_xbar_AWLOCK),\n        .M_AXI_awprot(s01_couplers_to_xbar_AWPROT),\n        .M_AXI_awqos(s01_couplers_to_xbar_AWQOS),\n        .M_AXI_awready(s01_couplers_to_xbar_AWREADY),\n        .M_AXI_awsize(s01_couplers_to_xbar_AWSIZE),\n        .M_AXI_awvalid(s01_couplers_to_xbar_AWVALID),\n        .M_AXI_bid(s01_couplers_to_xbar_BID),\n        .M_AXI_bready(s01_couplers_to_xbar_BREADY),\n        .M_AXI_bresp(s01_couplers_to_xbar_BRESP),\n        .M_AXI_bvalid(s01_couplers_to_xbar_BVALID),\n        .M_AXI_rdata(s01_couplers_to_xbar_RDATA),\n        .M_AXI_rid(s01_couplers_to_xbar_RID),\n        .M_AXI_rlast(s01_couplers_to_xbar_RLAST),\n        .M_AXI_rready(s01_couplers_to_xbar_RREADY),\n        .M_AXI_rresp(s01_couplers_to_xbar_RRESP),\n        .M_AXI_rvalid(s01_couplers_to_xbar_RVALID),\n        .M_AXI_wdata(s01_couplers_to_xbar_WDATA),\n        .M_AXI_wlast(s01_couplers_to_xbar_WLAST),\n        .M_AXI_wready(s01_couplers_to_xbar_WREADY),\n        .M_AXI_wstrb(s01_couplers_to_xbar_WSTRB),\n        .M_AXI_wvalid(s01_couplers_to_xbar_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(axi_interconnect_0_to_s01_couplers_ARADDR),\n        .S_AXI_arburst(axi_interconnect_0_to_s01_couplers_ARBURST),\n        .S_AXI_arcache(axi_interconnect_0_to_s01_couplers_ARCACHE),\n        .S_AXI_arid(axi_interconnect_0_to_s01_couplers_ARID),\n        .S_AXI_arlen(axi_interconnect_0_to_s01_couplers_ARLEN),\n        .S_AXI_arlock(axi_interconnect_0_to_s01_couplers_ARLOCK),\n        .S_AXI_arprot(axi_interconnect_0_to_s01_couplers_ARPROT),\n        .S_AXI_arqos(axi_interconnect_0_to_s01_couplers_ARQOS),\n        .S_AXI_arready(axi_interconnect_0_to_s01_couplers_ARREADY),\n        .S_AXI_arregion(axi_interconnect_0_to_s01_couplers_ARREGION),\n        .S_AXI_arsize(axi_interconnect_0_to_s01_couplers_ARSIZE),\n        .S_AXI_arvalid(axi_interconnect_0_to_s01_couplers_ARVALID),\n        .S_AXI_awaddr(axi_interconnect_0_to_s01_couplers_AWADDR),\n        .S_AXI_awburst(axi_interconnect_0_to_s01_couplers_AWBURST),\n        .S_AXI_awcache(axi_interconnect_0_to_s01_couplers_AWCACHE),\n        .S_AXI_awid(axi_interconnect_0_to_s01_couplers_AWID),\n        .S_AXI_awlen(axi_interconnect_0_to_s01_couplers_AWLEN),\n        .S_AXI_awlock(axi_interconnect_0_to_s01_couplers_AWLOCK),\n        .S_AXI_awprot(axi_interconnect_0_to_s01_couplers_AWPROT),\n        .S_AXI_awqos(axi_interconnect_0_to_s01_couplers_AWQOS),\n        .S_AXI_awready(axi_interconnect_0_to_s01_couplers_AWREADY),\n        .S_AXI_awregion(axi_interconnect_0_to_s01_couplers_AWREGION),\n        .S_AXI_awsize(axi_interconnect_0_to_s01_couplers_AWSIZE),\n        .S_AXI_awvalid(axi_interconnect_0_to_s01_couplers_AWVALID),\n        .S_AXI_bid(axi_interconnect_0_to_s01_couplers_BID),\n        .S_AXI_bready(axi_interconnect_0_to_s01_couplers_BREADY),\n        .S_AXI_bresp(axi_interconnect_0_to_s01_couplers_BRESP),\n        .S_AXI_bvalid(axi_interconnect_0_to_s01_couplers_BVALID),\n        .S_AXI_rdata(axi_interconnect_0_to_s01_couplers_RDATA),\n        .S_AXI_rid(axi_interconnect_0_to_s01_couplers_RID),\n        .S_AXI_rlast(axi_interconnect_0_to_s01_couplers_RLAST),\n        .S_AXI_rready(axi_interconnect_0_to_s01_couplers_RREADY),\n        .S_AXI_rresp(axi_interconnect_0_to_s01_couplers_RRESP),\n        .S_AXI_rvalid(axi_interconnect_0_to_s01_couplers_RVALID),\n        .S_AXI_wdata(axi_interconnect_0_to_s01_couplers_WDATA),\n        .S_AXI_wlast(axi_interconnect_0_to_s01_couplers_WLAST),\n        .S_AXI_wready(axi_interconnect_0_to_s01_couplers_WREADY),\n        .S_AXI_wstrb(axi_interconnect_0_to_s01_couplers_WSTRB),\n        .S_AXI_wvalid(axi_interconnect_0_to_s01_couplers_WVALID));\n  cl_axi_interconnect_xbar_0 xbar\n       (.aclk(axi_interconnect_0_ACLK_net),\n        .aresetn(axi_interconnect_0_ARESETN_net),\n        .m_axi_araddr({xbar_to_m03_couplers_ARADDR,xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),\n        .m_axi_arburst({xbar_to_m03_couplers_ARBURST,xbar_to_m02_couplers_ARBURST,xbar_to_m01_couplers_ARBURST,xbar_to_m00_couplers_ARBURST}),\n        .m_axi_arcache({xbar_to_m03_couplers_ARCACHE,xbar_to_m02_couplers_ARCACHE,xbar_to_m01_couplers_ARCACHE,xbar_to_m00_couplers_ARCACHE}),\n        .m_axi_arid({xbar_to_m03_couplers_ARID,xbar_to_m02_couplers_ARID,xbar_to_m01_couplers_ARID,xbar_to_m00_couplers_ARID}),\n        .m_axi_arlen({xbar_to_m03_couplers_ARLEN,xbar_to_m02_couplers_ARLEN,xbar_to_m01_couplers_ARLEN,xbar_to_m00_couplers_ARLEN}),\n        .m_axi_arlock({xbar_to_m03_couplers_ARLOCK,xbar_to_m02_couplers_ARLOCK,xbar_to_m01_couplers_ARLOCK,xbar_to_m00_couplers_ARLOCK}),\n        .m_axi_arprot({xbar_to_m03_couplers_ARPROT,xbar_to_m02_couplers_ARPROT,xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}),\n        .m_axi_arqos({xbar_to_m03_couplers_ARQOS,xbar_to_m02_couplers_ARQOS,xbar_to_m01_couplers_ARQOS,xbar_to_m00_couplers_ARQOS}),\n        .m_axi_arready({xbar_to_m03_couplers_ARREADY,xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),\n        .m_axi_arregion({xbar_to_m03_couplers_ARREGION,xbar_to_m02_couplers_ARREGION,xbar_to_m01_couplers_ARREGION,xbar_to_m00_couplers_ARREGION}),\n        .m_axi_arsize({xbar_to_m03_couplers_ARSIZE,xbar_to_m02_couplers_ARSIZE,xbar_to_m01_couplers_ARSIZE,xbar_to_m00_couplers_ARSIZE}),\n        .m_axi_arvalid({xbar_to_m03_couplers_ARVALID,xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),\n        .m_axi_awaddr({xbar_to_m03_couplers_AWADDR,xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),\n        .m_axi_awburst({xbar_to_m03_couplers_AWBURST,xbar_to_m02_couplers_AWBURST,xbar_to_m01_couplers_AWBURST,xbar_to_m00_couplers_AWBURST}),\n        .m_axi_awcache({xbar_to_m03_couplers_AWCACHE,xbar_to_m02_couplers_AWCACHE,xbar_to_m01_couplers_AWCACHE,xbar_to_m00_couplers_AWCACHE}),\n        .m_axi_awid({xbar_to_m03_couplers_AWID,xbar_to_m02_couplers_AWID,xbar_to_m01_couplers_AWID,xbar_to_m00_couplers_AWID}),\n        .m_axi_awlen({xbar_to_m03_couplers_AWLEN,xbar_to_m02_couplers_AWLEN,xbar_to_m01_couplers_AWLEN,xbar_to_m00_couplers_AWLEN}),\n        .m_axi_awlock({xbar_to_m03_couplers_AWLOCK,xbar_to_m02_couplers_AWLOCK,xbar_to_m01_couplers_AWLOCK,xbar_to_m00_couplers_AWLOCK}),\n        .m_axi_awprot({xbar_to_m03_couplers_AWPROT,xbar_to_m02_couplers_AWPROT,xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}),\n        .m_axi_awqos({xbar_to_m03_couplers_AWQOS,xbar_to_m02_couplers_AWQOS,xbar_to_m01_couplers_AWQOS,xbar_to_m00_couplers_AWQOS}),\n        .m_axi_awready({xbar_to_m03_couplers_AWREADY,xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),\n        .m_axi_awregion({xbar_to_m03_couplers_AWREGION,xbar_to_m02_couplers_AWREGION,xbar_to_m01_couplers_AWREGION,xbar_to_m00_couplers_AWREGION}),\n        .m_axi_awsize({xbar_to_m03_couplers_AWSIZE,xbar_to_m02_couplers_AWSIZE,xbar_to_m01_couplers_AWSIZE,xbar_to_m00_couplers_AWSIZE}),\n        .m_axi_awvalid({xbar_to_m03_couplers_AWVALID,xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),\n        .m_axi_bid({xbar_to_m03_couplers_BID,xbar_to_m02_couplers_BID,xbar_to_m01_couplers_BID,xbar_to_m00_couplers_BID}),\n        .m_axi_bready({xbar_to_m03_couplers_BREADY,xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),\n        .m_axi_bresp({xbar_to_m03_couplers_BRESP,xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),\n        .m_axi_bvalid({xbar_to_m03_couplers_BVALID,xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),\n        .m_axi_rdata({xbar_to_m03_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),\n        .m_axi_rid({xbar_to_m03_couplers_RID,xbar_to_m02_couplers_RID,xbar_to_m01_couplers_RID,xbar_to_m00_couplers_RID}),\n        .m_axi_rlast({xbar_to_m03_couplers_RLAST,xbar_to_m02_couplers_RLAST,xbar_to_m01_couplers_RLAST,xbar_to_m00_couplers_RLAST}),\n        .m_axi_rready({xbar_to_m03_couplers_RREADY,xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),\n        .m_axi_rresp({xbar_to_m03_couplers_RRESP,xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),\n        .m_axi_rvalid({xbar_to_m03_couplers_RVALID,xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),\n        .m_axi_wdata({xbar_to_m03_couplers_WDATA,xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),\n        .m_axi_wlast({xbar_to_m03_couplers_WLAST,xbar_to_m02_couplers_WLAST,xbar_to_m01_couplers_WLAST,xbar_to_m00_couplers_WLAST}),\n        .m_axi_wready({xbar_to_m03_couplers_WREADY,xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),\n        .m_axi_wstrb({xbar_to_m03_couplers_WSTRB,xbar_to_m02_couplers_WSTRB,xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),\n        .m_axi_wvalid({xbar_to_m03_couplers_WVALID,xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),\n        .s_axi_araddr({s01_couplers_to_xbar_ARADDR,s00_couplers_to_xbar_ARADDR}),\n        .s_axi_arburst({s01_couplers_to_xbar_ARBURST,s00_couplers_to_xbar_ARBURST}),\n        .s_axi_arcache({s01_couplers_to_xbar_ARCACHE,s00_couplers_to_xbar_ARCACHE}),\n        .s_axi_arid({1'b0,s01_couplers_to_xbar_ARID,1'b0,s00_couplers_to_xbar_ARID}),\n        .s_axi_arlen({s01_couplers_to_xbar_ARLEN,s00_couplers_to_xbar_ARLEN}),\n        .s_axi_arlock({s01_couplers_to_xbar_ARLOCK,s00_couplers_to_xbar_ARLOCK}),\n        .s_axi_arprot({s01_couplers_to_xbar_ARPROT,s00_couplers_to_xbar_ARPROT}),\n        .s_axi_arqos({s01_couplers_to_xbar_ARQOS,s00_couplers_to_xbar_ARQOS}),\n        .s_axi_arready({s01_couplers_to_xbar_ARREADY,s00_couplers_to_xbar_ARREADY}),\n        .s_axi_arsize({s01_couplers_to_xbar_ARSIZE,s00_couplers_to_xbar_ARSIZE}),\n        .s_axi_arvalid({s01_couplers_to_xbar_ARVALID,s00_couplers_to_xbar_ARVALID}),\n        .s_axi_awaddr({s01_couplers_to_xbar_AWADDR,s00_couplers_to_xbar_AWADDR}),\n        .s_axi_awburst({s01_couplers_to_xbar_AWBURST,s00_couplers_to_xbar_AWBURST}),\n        .s_axi_awcache({s01_couplers_to_xbar_AWCACHE,s00_couplers_to_xbar_AWCACHE}),\n        .s_axi_awid({1'b0,s01_couplers_to_xbar_AWID,1'b0,s00_couplers_to_xbar_AWID}),\n        .s_axi_awlen({s01_couplers_to_xbar_AWLEN,s00_couplers_to_xbar_AWLEN}),\n        .s_axi_awlock({s01_couplers_to_xbar_AWLOCK,s00_couplers_to_xbar_AWLOCK}),\n        .s_axi_awprot({s01_couplers_to_xbar_AWPROT,s00_couplers_to_xbar_AWPROT}),\n        .s_axi_awqos({s01_couplers_to_xbar_AWQOS,s00_couplers_to_xbar_AWQOS}),\n        .s_axi_awready({s01_couplers_to_xbar_AWREADY,s00_couplers_to_xbar_AWREADY}),\n        .s_axi_awsize({s01_couplers_to_xbar_AWSIZE,s00_couplers_to_xbar_AWSIZE}),\n        .s_axi_awvalid({s01_couplers_to_xbar_AWVALID,s00_couplers_to_xbar_AWVALID}),\n        .s_axi_bid({s01_couplers_to_xbar_BID,s00_couplers_to_xbar_BID}),\n        .s_axi_bready({s01_couplers_to_xbar_BREADY,s00_couplers_to_xbar_BREADY}),\n        .s_axi_bresp({s01_couplers_to_xbar_BRESP,s00_couplers_to_xbar_BRESP}),\n        .s_axi_bvalid({s01_couplers_to_xbar_BVALID,s00_couplers_to_xbar_BVALID}),\n        .s_axi_rdata({s01_couplers_to_xbar_RDATA,s00_couplers_to_xbar_RDATA}),\n        .s_axi_rid({s01_couplers_to_xbar_RID,s00_couplers_to_xbar_RID}),\n        .s_axi_rlast({s01_couplers_to_xbar_RLAST,s00_couplers_to_xbar_RLAST}),\n        .s_axi_rready({s01_couplers_to_xbar_RREADY,s00_couplers_to_xbar_RREADY}),\n        .s_axi_rresp({s01_couplers_to_xbar_RRESP,s00_couplers_to_xbar_RRESP}),\n        .s_axi_rvalid({s01_couplers_to_xbar_RVALID,s00_couplers_to_xbar_RVALID}),\n        .s_axi_wdata({s01_couplers_to_xbar_WDATA,s00_couplers_to_xbar_WDATA}),\n        .s_axi_wlast({s01_couplers_to_xbar_WLAST,s00_couplers_to_xbar_WLAST}),\n        .s_axi_wready({s01_couplers_to_xbar_WREADY,s00_couplers_to_xbar_WREADY}),\n        .s_axi_wstrb({s01_couplers_to_xbar_WSTRB,s00_couplers_to_xbar_WSTRB}),\n        .s_axi_wvalid({s01_couplers_to_xbar_WVALID,s00_couplers_to_xbar_WVALID}));\nendmodule\n\nmodule m00_couplers_imp_1QBJ6U2\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m00_couplers_to_m00_regslice_ARADDR;\n  wire [1:0]m00_couplers_to_m00_regslice_ARBURST;\n  wire [3:0]m00_couplers_to_m00_regslice_ARCACHE;\n  wire [6:0]m00_couplers_to_m00_regslice_ARID;\n  wire [7:0]m00_couplers_to_m00_regslice_ARLEN;\n  wire [0:0]m00_couplers_to_m00_regslice_ARLOCK;\n  wire [2:0]m00_couplers_to_m00_regslice_ARPROT;\n  wire [3:0]m00_couplers_to_m00_regslice_ARQOS;\n  wire m00_couplers_to_m00_regslice_ARREADY;\n  wire [3:0]m00_couplers_to_m00_regslice_ARREGION;\n  wire [2:0]m00_couplers_to_m00_regslice_ARSIZE;\n  wire m00_couplers_to_m00_regslice_ARVALID;\n  wire [63:0]m00_couplers_to_m00_regslice_AWADDR;\n  wire [1:0]m00_couplers_to_m00_regslice_AWBURST;\n  wire [3:0]m00_couplers_to_m00_regslice_AWCACHE;\n  wire [6:0]m00_couplers_to_m00_regslice_AWID;\n  wire [7:0]m00_couplers_to_m00_regslice_AWLEN;\n  wire [0:0]m00_couplers_to_m00_regslice_AWLOCK;\n  wire [2:0]m00_couplers_to_m00_regslice_AWPROT;\n  wire [3:0]m00_couplers_to_m00_regslice_AWQOS;\n  wire m00_couplers_to_m00_regslice_AWREADY;\n  wire [3:0]m00_couplers_to_m00_regslice_AWREGION;\n  wire [2:0]m00_couplers_to_m00_regslice_AWSIZE;\n  wire m00_couplers_to_m00_regslice_AWVALID;\n  wire [6:0]m00_couplers_to_m00_regslice_BID;\n  wire m00_couplers_to_m00_regslice_BREADY;\n  wire [1:0]m00_couplers_to_m00_regslice_BRESP;\n  wire m00_couplers_to_m00_regslice_BVALID;\n  wire [511:0]m00_couplers_to_m00_regslice_RDATA;\n  wire [6:0]m00_couplers_to_m00_regslice_RID;\n  wire m00_couplers_to_m00_regslice_RLAST;\n  wire m00_couplers_to_m00_regslice_RREADY;\n  wire [1:0]m00_couplers_to_m00_regslice_RRESP;\n  wire m00_couplers_to_m00_regslice_RVALID;\n  wire [511:0]m00_couplers_to_m00_regslice_WDATA;\n  wire m00_couplers_to_m00_regslice_WLAST;\n  wire m00_couplers_to_m00_regslice_WREADY;\n  wire [63:0]m00_couplers_to_m00_regslice_WSTRB;\n  wire m00_couplers_to_m00_regslice_WVALID;\n  wire [63:0]m00_regslice_to_m00_couplers_ARADDR;\n  wire [1:0]m00_regslice_to_m00_couplers_ARBURST;\n  wire [3:0]m00_regslice_to_m00_couplers_ARCACHE;\n  wire [6:0]m00_regslice_to_m00_couplers_ARID;\n  wire [7:0]m00_regslice_to_m00_couplers_ARLEN;\n  wire [0:0]m00_regslice_to_m00_couplers_ARLOCK;\n  wire [2:0]m00_regslice_to_m00_couplers_ARPROT;\n  wire [3:0]m00_regslice_to_m00_couplers_ARQOS;\n  wire m00_regslice_to_m00_couplers_ARREADY;\n  wire [3:0]m00_regslice_to_m00_couplers_ARREGION;\n  wire [2:0]m00_regslice_to_m00_couplers_ARSIZE;\n  wire m00_regslice_to_m00_couplers_ARVALID;\n  wire [63:0]m00_regslice_to_m00_couplers_AWADDR;\n  wire [1:0]m00_regslice_to_m00_couplers_AWBURST;\n  wire [3:0]m00_regslice_to_m00_couplers_AWCACHE;\n  wire [6:0]m00_regslice_to_m00_couplers_AWID;\n  wire [7:0]m00_regslice_to_m00_couplers_AWLEN;\n  wire [0:0]m00_regslice_to_m00_couplers_AWLOCK;\n  wire [2:0]m00_regslice_to_m00_couplers_AWPROT;\n  wire [3:0]m00_regslice_to_m00_couplers_AWQOS;\n  wire m00_regslice_to_m00_couplers_AWREADY;\n  wire [3:0]m00_regslice_to_m00_couplers_AWREGION;\n  wire [2:0]m00_regslice_to_m00_couplers_AWSIZE;\n  wire m00_regslice_to_m00_couplers_AWVALID;\n  wire [6:0]m00_regslice_to_m00_couplers_BID;\n  wire m00_regslice_to_m00_couplers_BREADY;\n  wire [1:0]m00_regslice_to_m00_couplers_BRESP;\n  wire m00_regslice_to_m00_couplers_BVALID;\n  wire [511:0]m00_regslice_to_m00_couplers_RDATA;\n  wire [6:0]m00_regslice_to_m00_couplers_RID;\n  wire m00_regslice_to_m00_couplers_RLAST;\n  wire m00_regslice_to_m00_couplers_RREADY;\n  wire [1:0]m00_regslice_to_m00_couplers_RRESP;\n  wire m00_regslice_to_m00_couplers_RVALID;\n  wire [511:0]m00_regslice_to_m00_couplers_WDATA;\n  wire m00_regslice_to_m00_couplers_WLAST;\n  wire m00_regslice_to_m00_couplers_WREADY;\n  wire [63:0]m00_regslice_to_m00_couplers_WSTRB;\n  wire m00_regslice_to_m00_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m00_regslice_to_m00_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m00_regslice_to_m00_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m00_regslice_to_m00_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m00_regslice_to_m00_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m00_regslice_to_m00_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m00_regslice_to_m00_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m00_regslice_to_m00_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m00_regslice_to_m00_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m00_regslice_to_m00_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m00_regslice_to_m00_couplers_ARSIZE;\n  assign M_AXI_arvalid = m00_regslice_to_m00_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m00_regslice_to_m00_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m00_regslice_to_m00_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m00_regslice_to_m00_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m00_regslice_to_m00_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m00_regslice_to_m00_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m00_regslice_to_m00_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m00_regslice_to_m00_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m00_regslice_to_m00_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m00_regslice_to_m00_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m00_regslice_to_m00_couplers_AWSIZE;\n  assign M_AXI_awvalid = m00_regslice_to_m00_couplers_AWVALID;\n  assign M_AXI_bready = m00_regslice_to_m00_couplers_BREADY;\n  assign M_AXI_rready = m00_regslice_to_m00_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m00_regslice_to_m00_couplers_WDATA;\n  assign M_AXI_wlast = m00_regslice_to_m00_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m00_regslice_to_m00_couplers_WSTRB;\n  assign M_AXI_wvalid = m00_regslice_to_m00_couplers_WVALID;\n  assign S_AXI_arready = m00_couplers_to_m00_regslice_ARREADY;\n  assign S_AXI_awready = m00_couplers_to_m00_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m00_couplers_to_m00_regslice_BID;\n  assign S_AXI_bresp[1:0] = m00_couplers_to_m00_regslice_BRESP;\n  assign S_AXI_bvalid = m00_couplers_to_m00_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m00_couplers_to_m00_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m00_couplers_to_m00_regslice_RID;\n  assign S_AXI_rlast = m00_couplers_to_m00_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m00_couplers_to_m00_regslice_RRESP;\n  assign S_AXI_rvalid = m00_couplers_to_m00_regslice_RVALID;\n  assign S_AXI_wready = m00_couplers_to_m00_regslice_WREADY;\n  assign m00_couplers_to_m00_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m00_couplers_to_m00_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m00_couplers_to_m00_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m00_couplers_to_m00_regslice_ARID = S_AXI_arid[6:0];\n  assign m00_couplers_to_m00_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m00_couplers_to_m00_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m00_couplers_to_m00_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m00_couplers_to_m00_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m00_couplers_to_m00_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m00_couplers_to_m00_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m00_couplers_to_m00_regslice_ARVALID = S_AXI_arvalid;\n  assign m00_couplers_to_m00_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m00_couplers_to_m00_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m00_couplers_to_m00_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m00_couplers_to_m00_regslice_AWID = S_AXI_awid[6:0];\n  assign m00_couplers_to_m00_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m00_couplers_to_m00_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m00_couplers_to_m00_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m00_couplers_to_m00_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m00_couplers_to_m00_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m00_couplers_to_m00_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m00_couplers_to_m00_regslice_AWVALID = S_AXI_awvalid;\n  assign m00_couplers_to_m00_regslice_BREADY = S_AXI_bready;\n  assign m00_couplers_to_m00_regslice_RREADY = S_AXI_rready;\n  assign m00_couplers_to_m00_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m00_couplers_to_m00_regslice_WLAST = S_AXI_wlast;\n  assign m00_couplers_to_m00_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m00_couplers_to_m00_regslice_WVALID = S_AXI_wvalid;\n  assign m00_regslice_to_m00_couplers_ARREADY = M_AXI_arready;\n  assign m00_regslice_to_m00_couplers_AWREADY = M_AXI_awready;\n  assign m00_regslice_to_m00_couplers_BID = M_AXI_bid[6:0];\n  assign m00_regslice_to_m00_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m00_regslice_to_m00_couplers_BVALID = M_AXI_bvalid;\n  assign m00_regslice_to_m00_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m00_regslice_to_m00_couplers_RID = M_AXI_rid[6:0];\n  assign m00_regslice_to_m00_couplers_RLAST = M_AXI_rlast;\n  assign m00_regslice_to_m00_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m00_regslice_to_m00_couplers_RVALID = M_AXI_rvalid;\n  assign m00_regslice_to_m00_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m00_regslice_0 m00_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m00_regslice_to_m00_couplers_ARADDR),\n        .m_axi_arburst(m00_regslice_to_m00_couplers_ARBURST),\n        .m_axi_arcache(m00_regslice_to_m00_couplers_ARCACHE),\n        .m_axi_arid(m00_regslice_to_m00_couplers_ARID),\n        .m_axi_arlen(m00_regslice_to_m00_couplers_ARLEN),\n        .m_axi_arlock(m00_regslice_to_m00_couplers_ARLOCK),\n        .m_axi_arprot(m00_regslice_to_m00_couplers_ARPROT),\n        .m_axi_arqos(m00_regslice_to_m00_couplers_ARQOS),\n        .m_axi_arready(m00_regslice_to_m00_couplers_ARREADY),\n        .m_axi_arregion(m00_regslice_to_m00_couplers_ARREGION),\n        .m_axi_arsize(m00_regslice_to_m00_couplers_ARSIZE),\n        .m_axi_arvalid(m00_regslice_to_m00_couplers_ARVALID),\n        .m_axi_awaddr(m00_regslice_to_m00_couplers_AWADDR),\n        .m_axi_awburst(m00_regslice_to_m00_couplers_AWBURST),\n        .m_axi_awcache(m00_regslice_to_m00_couplers_AWCACHE),\n        .m_axi_awid(m00_regslice_to_m00_couplers_AWID),\n        .m_axi_awlen(m00_regslice_to_m00_couplers_AWLEN),\n        .m_axi_awlock(m00_regslice_to_m00_couplers_AWLOCK),\n        .m_axi_awprot(m00_regslice_to_m00_couplers_AWPROT),\n        .m_axi_awqos(m00_regslice_to_m00_couplers_AWQOS),\n        .m_axi_awready(m00_regslice_to_m00_couplers_AWREADY),\n        .m_axi_awregion(m00_regslice_to_m00_couplers_AWREGION),\n        .m_axi_awsize(m00_regslice_to_m00_couplers_AWSIZE),\n        .m_axi_awvalid(m00_regslice_to_m00_couplers_AWVALID),\n        .m_axi_bid(m00_regslice_to_m00_couplers_BID),\n        .m_axi_bready(m00_regslice_to_m00_couplers_BREADY),\n        .m_axi_bresp(m00_regslice_to_m00_couplers_BRESP),\n        .m_axi_bvalid(m00_regslice_to_m00_couplers_BVALID),\n        .m_axi_rdata(m00_regslice_to_m00_couplers_RDATA),\n        .m_axi_rid(m00_regslice_to_m00_couplers_RID),\n        .m_axi_rlast(m00_regslice_to_m00_couplers_RLAST),\n        .m_axi_rready(m00_regslice_to_m00_couplers_RREADY),\n        .m_axi_rresp(m00_regslice_to_m00_couplers_RRESP),\n        .m_axi_rvalid(m00_regslice_to_m00_couplers_RVALID),\n        .m_axi_wdata(m00_regslice_to_m00_couplers_WDATA),\n        .m_axi_wlast(m00_regslice_to_m00_couplers_WLAST),\n        .m_axi_wready(m00_regslice_to_m00_couplers_WREADY),\n        .m_axi_wstrb(m00_regslice_to_m00_couplers_WSTRB),\n        .m_axi_wvalid(m00_regslice_to_m00_couplers_WVALID),\n        .s_axi_araddr(m00_couplers_to_m00_regslice_ARADDR),\n        .s_axi_arburst(m00_couplers_to_m00_regslice_ARBURST),\n        .s_axi_arcache(m00_couplers_to_m00_regslice_ARCACHE),\n        .s_axi_arid(m00_couplers_to_m00_regslice_ARID),\n        .s_axi_arlen(m00_couplers_to_m00_regslice_ARLEN),\n        .s_axi_arlock(m00_couplers_to_m00_regslice_ARLOCK),\n        .s_axi_arprot(m00_couplers_to_m00_regslice_ARPROT),\n        .s_axi_arqos(m00_couplers_to_m00_regslice_ARQOS),\n        .s_axi_arready(m00_couplers_to_m00_regslice_ARREADY),\n        .s_axi_arregion(m00_couplers_to_m00_regslice_ARREGION),\n        .s_axi_arsize(m00_couplers_to_m00_regslice_ARSIZE),\n        .s_axi_arvalid(m00_couplers_to_m00_regslice_ARVALID),\n        .s_axi_awaddr(m00_couplers_to_m00_regslice_AWADDR),\n        .s_axi_awburst(m00_couplers_to_m00_regslice_AWBURST),\n        .s_axi_awcache(m00_couplers_to_m00_regslice_AWCACHE),\n        .s_axi_awid(m00_couplers_to_m00_regslice_AWID),\n        .s_axi_awlen(m00_couplers_to_m00_regslice_AWLEN),\n        .s_axi_awlock(m00_couplers_to_m00_regslice_AWLOCK),\n        .s_axi_awprot(m00_couplers_to_m00_regslice_AWPROT),\n        .s_axi_awqos(m00_couplers_to_m00_regslice_AWQOS),\n        .s_axi_awready(m00_couplers_to_m00_regslice_AWREADY),\n        .s_axi_awregion(m00_couplers_to_m00_regslice_AWREGION),\n        .s_axi_awsize(m00_couplers_to_m00_regslice_AWSIZE),\n        .s_axi_awvalid(m00_couplers_to_m00_regslice_AWVALID),\n        .s_axi_bid(m00_couplers_to_m00_regslice_BID),\n        .s_axi_bready(m00_couplers_to_m00_regslice_BREADY),\n        .s_axi_bresp(m00_couplers_to_m00_regslice_BRESP),\n        .s_axi_bvalid(m00_couplers_to_m00_regslice_BVALID),\n        .s_axi_rdata(m00_couplers_to_m00_regslice_RDATA),\n        .s_axi_rid(m00_couplers_to_m00_regslice_RID),\n        .s_axi_rlast(m00_couplers_to_m00_regslice_RLAST),\n        .s_axi_rready(m00_couplers_to_m00_regslice_RREADY),\n        .s_axi_rresp(m00_couplers_to_m00_regslice_RRESP),\n        .s_axi_rvalid(m00_couplers_to_m00_regslice_RVALID),\n        .s_axi_wdata(m00_couplers_to_m00_regslice_WDATA),\n        .s_axi_wlast(m00_couplers_to_m00_regslice_WLAST),\n        .s_axi_wready(m00_couplers_to_m00_regslice_WREADY),\n        .s_axi_wstrb(m00_couplers_to_m00_regslice_WSTRB),\n        .s_axi_wvalid(m00_couplers_to_m00_regslice_WVALID));\nendmodule\n\nmodule m01_couplers_imp_10IMR9A\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m01_couplers_to_m01_regslice_ARADDR;\n  wire [1:0]m01_couplers_to_m01_regslice_ARBURST;\n  wire [3:0]m01_couplers_to_m01_regslice_ARCACHE;\n  wire [6:0]m01_couplers_to_m01_regslice_ARID;\n  wire [7:0]m01_couplers_to_m01_regslice_ARLEN;\n  wire [0:0]m01_couplers_to_m01_regslice_ARLOCK;\n  wire [2:0]m01_couplers_to_m01_regslice_ARPROT;\n  wire [3:0]m01_couplers_to_m01_regslice_ARQOS;\n  wire m01_couplers_to_m01_regslice_ARREADY;\n  wire [3:0]m01_couplers_to_m01_regslice_ARREGION;\n  wire [2:0]m01_couplers_to_m01_regslice_ARSIZE;\n  wire m01_couplers_to_m01_regslice_ARVALID;\n  wire [63:0]m01_couplers_to_m01_regslice_AWADDR;\n  wire [1:0]m01_couplers_to_m01_regslice_AWBURST;\n  wire [3:0]m01_couplers_to_m01_regslice_AWCACHE;\n  wire [6:0]m01_couplers_to_m01_regslice_AWID;\n  wire [7:0]m01_couplers_to_m01_regslice_AWLEN;\n  wire [0:0]m01_couplers_to_m01_regslice_AWLOCK;\n  wire [2:0]m01_couplers_to_m01_regslice_AWPROT;\n  wire [3:0]m01_couplers_to_m01_regslice_AWQOS;\n  wire m01_couplers_to_m01_regslice_AWREADY;\n  wire [3:0]m01_couplers_to_m01_regslice_AWREGION;\n  wire [2:0]m01_couplers_to_m01_regslice_AWSIZE;\n  wire m01_couplers_to_m01_regslice_AWVALID;\n  wire [6:0]m01_couplers_to_m01_regslice_BID;\n  wire m01_couplers_to_m01_regslice_BREADY;\n  wire [1:0]m01_couplers_to_m01_regslice_BRESP;\n  wire m01_couplers_to_m01_regslice_BVALID;\n  wire [511:0]m01_couplers_to_m01_regslice_RDATA;\n  wire [6:0]m01_couplers_to_m01_regslice_RID;\n  wire m01_couplers_to_m01_regslice_RLAST;\n  wire m01_couplers_to_m01_regslice_RREADY;\n  wire [1:0]m01_couplers_to_m01_regslice_RRESP;\n  wire m01_couplers_to_m01_regslice_RVALID;\n  wire [511:0]m01_couplers_to_m01_regslice_WDATA;\n  wire m01_couplers_to_m01_regslice_WLAST;\n  wire m01_couplers_to_m01_regslice_WREADY;\n  wire [63:0]m01_couplers_to_m01_regslice_WSTRB;\n  wire m01_couplers_to_m01_regslice_WVALID;\n  wire [63:0]m01_regslice_to_m01_couplers_ARADDR;\n  wire [1:0]m01_regslice_to_m01_couplers_ARBURST;\n  wire [3:0]m01_regslice_to_m01_couplers_ARCACHE;\n  wire [6:0]m01_regslice_to_m01_couplers_ARID;\n  wire [7:0]m01_regslice_to_m01_couplers_ARLEN;\n  wire [0:0]m01_regslice_to_m01_couplers_ARLOCK;\n  wire [2:0]m01_regslice_to_m01_couplers_ARPROT;\n  wire [3:0]m01_regslice_to_m01_couplers_ARQOS;\n  wire m01_regslice_to_m01_couplers_ARREADY;\n  wire [3:0]m01_regslice_to_m01_couplers_ARREGION;\n  wire [2:0]m01_regslice_to_m01_couplers_ARSIZE;\n  wire m01_regslice_to_m01_couplers_ARVALID;\n  wire [63:0]m01_regslice_to_m01_couplers_AWADDR;\n  wire [1:0]m01_regslice_to_m01_couplers_AWBURST;\n  wire [3:0]m01_regslice_to_m01_couplers_AWCACHE;\n  wire [6:0]m01_regslice_to_m01_couplers_AWID;\n  wire [7:0]m01_regslice_to_m01_couplers_AWLEN;\n  wire [0:0]m01_regslice_to_m01_couplers_AWLOCK;\n  wire [2:0]m01_regslice_to_m01_couplers_AWPROT;\n  wire [3:0]m01_regslice_to_m01_couplers_AWQOS;\n  wire m01_regslice_to_m01_couplers_AWREADY;\n  wire [3:0]m01_regslice_to_m01_couplers_AWREGION;\n  wire [2:0]m01_regslice_to_m01_couplers_AWSIZE;\n  wire m01_regslice_to_m01_couplers_AWVALID;\n  wire [6:0]m01_regslice_to_m01_couplers_BID;\n  wire m01_regslice_to_m01_couplers_BREADY;\n  wire [1:0]m01_regslice_to_m01_couplers_BRESP;\n  wire m01_regslice_to_m01_couplers_BVALID;\n  wire [511:0]m01_regslice_to_m01_couplers_RDATA;\n  wire [6:0]m01_regslice_to_m01_couplers_RID;\n  wire m01_regslice_to_m01_couplers_RLAST;\n  wire m01_regslice_to_m01_couplers_RREADY;\n  wire [1:0]m01_regslice_to_m01_couplers_RRESP;\n  wire m01_regslice_to_m01_couplers_RVALID;\n  wire [511:0]m01_regslice_to_m01_couplers_WDATA;\n  wire m01_regslice_to_m01_couplers_WLAST;\n  wire m01_regslice_to_m01_couplers_WREADY;\n  wire [63:0]m01_regslice_to_m01_couplers_WSTRB;\n  wire m01_regslice_to_m01_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m01_regslice_to_m01_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m01_regslice_to_m01_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m01_regslice_to_m01_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m01_regslice_to_m01_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m01_regslice_to_m01_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m01_regslice_to_m01_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m01_regslice_to_m01_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m01_regslice_to_m01_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m01_regslice_to_m01_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m01_regslice_to_m01_couplers_ARSIZE;\n  assign M_AXI_arvalid = m01_regslice_to_m01_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m01_regslice_to_m01_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m01_regslice_to_m01_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m01_regslice_to_m01_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m01_regslice_to_m01_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m01_regslice_to_m01_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m01_regslice_to_m01_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m01_regslice_to_m01_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m01_regslice_to_m01_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m01_regslice_to_m01_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m01_regslice_to_m01_couplers_AWSIZE;\n  assign M_AXI_awvalid = m01_regslice_to_m01_couplers_AWVALID;\n  assign M_AXI_bready = m01_regslice_to_m01_couplers_BREADY;\n  assign M_AXI_rready = m01_regslice_to_m01_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m01_regslice_to_m01_couplers_WDATA;\n  assign M_AXI_wlast = m01_regslice_to_m01_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m01_regslice_to_m01_couplers_WSTRB;\n  assign M_AXI_wvalid = m01_regslice_to_m01_couplers_WVALID;\n  assign S_AXI_arready = m01_couplers_to_m01_regslice_ARREADY;\n  assign S_AXI_awready = m01_couplers_to_m01_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m01_couplers_to_m01_regslice_BID;\n  assign S_AXI_bresp[1:0] = m01_couplers_to_m01_regslice_BRESP;\n  assign S_AXI_bvalid = m01_couplers_to_m01_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m01_couplers_to_m01_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m01_couplers_to_m01_regslice_RID;\n  assign S_AXI_rlast = m01_couplers_to_m01_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m01_couplers_to_m01_regslice_RRESP;\n  assign S_AXI_rvalid = m01_couplers_to_m01_regslice_RVALID;\n  assign S_AXI_wready = m01_couplers_to_m01_regslice_WREADY;\n  assign m01_couplers_to_m01_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m01_couplers_to_m01_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m01_couplers_to_m01_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m01_couplers_to_m01_regslice_ARID = S_AXI_arid[6:0];\n  assign m01_couplers_to_m01_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m01_couplers_to_m01_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m01_couplers_to_m01_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m01_couplers_to_m01_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m01_couplers_to_m01_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m01_couplers_to_m01_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m01_couplers_to_m01_regslice_ARVALID = S_AXI_arvalid;\n  assign m01_couplers_to_m01_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m01_couplers_to_m01_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m01_couplers_to_m01_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m01_couplers_to_m01_regslice_AWID = S_AXI_awid[6:0];\n  assign m01_couplers_to_m01_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m01_couplers_to_m01_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m01_couplers_to_m01_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m01_couplers_to_m01_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m01_couplers_to_m01_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m01_couplers_to_m01_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m01_couplers_to_m01_regslice_AWVALID = S_AXI_awvalid;\n  assign m01_couplers_to_m01_regslice_BREADY = S_AXI_bready;\n  assign m01_couplers_to_m01_regslice_RREADY = S_AXI_rready;\n  assign m01_couplers_to_m01_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m01_couplers_to_m01_regslice_WLAST = S_AXI_wlast;\n  assign m01_couplers_to_m01_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m01_couplers_to_m01_regslice_WVALID = S_AXI_wvalid;\n  assign m01_regslice_to_m01_couplers_ARREADY = M_AXI_arready;\n  assign m01_regslice_to_m01_couplers_AWREADY = M_AXI_awready;\n  assign m01_regslice_to_m01_couplers_BID = M_AXI_bid[6:0];\n  assign m01_regslice_to_m01_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m01_regslice_to_m01_couplers_BVALID = M_AXI_bvalid;\n  assign m01_regslice_to_m01_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m01_regslice_to_m01_couplers_RID = M_AXI_rid[6:0];\n  assign m01_regslice_to_m01_couplers_RLAST = M_AXI_rlast;\n  assign m01_regslice_to_m01_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m01_regslice_to_m01_couplers_RVALID = M_AXI_rvalid;\n  assign m01_regslice_to_m01_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m01_regslice_0 m01_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m01_regslice_to_m01_couplers_ARADDR),\n        .m_axi_arburst(m01_regslice_to_m01_couplers_ARBURST),\n        .m_axi_arcache(m01_regslice_to_m01_couplers_ARCACHE),\n        .m_axi_arid(m01_regslice_to_m01_couplers_ARID),\n        .m_axi_arlen(m01_regslice_to_m01_couplers_ARLEN),\n        .m_axi_arlock(m01_regslice_to_m01_couplers_ARLOCK),\n        .m_axi_arprot(m01_regslice_to_m01_couplers_ARPROT),\n        .m_axi_arqos(m01_regslice_to_m01_couplers_ARQOS),\n        .m_axi_arready(m01_regslice_to_m01_couplers_ARREADY),\n        .m_axi_arregion(m01_regslice_to_m01_couplers_ARREGION),\n        .m_axi_arsize(m01_regslice_to_m01_couplers_ARSIZE),\n        .m_axi_arvalid(m01_regslice_to_m01_couplers_ARVALID),\n        .m_axi_awaddr(m01_regslice_to_m01_couplers_AWADDR),\n        .m_axi_awburst(m01_regslice_to_m01_couplers_AWBURST),\n        .m_axi_awcache(m01_regslice_to_m01_couplers_AWCACHE),\n        .m_axi_awid(m01_regslice_to_m01_couplers_AWID),\n        .m_axi_awlen(m01_regslice_to_m01_couplers_AWLEN),\n        .m_axi_awlock(m01_regslice_to_m01_couplers_AWLOCK),\n        .m_axi_awprot(m01_regslice_to_m01_couplers_AWPROT),\n        .m_axi_awqos(m01_regslice_to_m01_couplers_AWQOS),\n        .m_axi_awready(m01_regslice_to_m01_couplers_AWREADY),\n        .m_axi_awregion(m01_regslice_to_m01_couplers_AWREGION),\n        .m_axi_awsize(m01_regslice_to_m01_couplers_AWSIZE),\n        .m_axi_awvalid(m01_regslice_to_m01_couplers_AWVALID),\n        .m_axi_bid(m01_regslice_to_m01_couplers_BID),\n        .m_axi_bready(m01_regslice_to_m01_couplers_BREADY),\n        .m_axi_bresp(m01_regslice_to_m01_couplers_BRESP),\n        .m_axi_bvalid(m01_regslice_to_m01_couplers_BVALID),\n        .m_axi_rdata(m01_regslice_to_m01_couplers_RDATA),\n        .m_axi_rid(m01_regslice_to_m01_couplers_RID),\n        .m_axi_rlast(m01_regslice_to_m01_couplers_RLAST),\n        .m_axi_rready(m01_regslice_to_m01_couplers_RREADY),\n        .m_axi_rresp(m01_regslice_to_m01_couplers_RRESP),\n        .m_axi_rvalid(m01_regslice_to_m01_couplers_RVALID),\n        .m_axi_wdata(m01_regslice_to_m01_couplers_WDATA),\n        .m_axi_wlast(m01_regslice_to_m01_couplers_WLAST),\n        .m_axi_wready(m01_regslice_to_m01_couplers_WREADY),\n        .m_axi_wstrb(m01_regslice_to_m01_couplers_WSTRB),\n        .m_axi_wvalid(m01_regslice_to_m01_couplers_WVALID),\n        .s_axi_araddr(m01_couplers_to_m01_regslice_ARADDR),\n        .s_axi_arburst(m01_couplers_to_m01_regslice_ARBURST),\n        .s_axi_arcache(m01_couplers_to_m01_regslice_ARCACHE),\n        .s_axi_arid(m01_couplers_to_m01_regslice_ARID),\n        .s_axi_arlen(m01_couplers_to_m01_regslice_ARLEN),\n        .s_axi_arlock(m01_couplers_to_m01_regslice_ARLOCK),\n        .s_axi_arprot(m01_couplers_to_m01_regslice_ARPROT),\n        .s_axi_arqos(m01_couplers_to_m01_regslice_ARQOS),\n        .s_axi_arready(m01_couplers_to_m01_regslice_ARREADY),\n        .s_axi_arregion(m01_couplers_to_m01_regslice_ARREGION),\n        .s_axi_arsize(m01_couplers_to_m01_regslice_ARSIZE),\n        .s_axi_arvalid(m01_couplers_to_m01_regslice_ARVALID),\n        .s_axi_awaddr(m01_couplers_to_m01_regslice_AWADDR),\n        .s_axi_awburst(m01_couplers_to_m01_regslice_AWBURST),\n        .s_axi_awcache(m01_couplers_to_m01_regslice_AWCACHE),\n        .s_axi_awid(m01_couplers_to_m01_regslice_AWID),\n        .s_axi_awlen(m01_couplers_to_m01_regslice_AWLEN),\n        .s_axi_awlock(m01_couplers_to_m01_regslice_AWLOCK),\n        .s_axi_awprot(m01_couplers_to_m01_regslice_AWPROT),\n        .s_axi_awqos(m01_couplers_to_m01_regslice_AWQOS),\n        .s_axi_awready(m01_couplers_to_m01_regslice_AWREADY),\n        .s_axi_awregion(m01_couplers_to_m01_regslice_AWREGION),\n        .s_axi_awsize(m01_couplers_to_m01_regslice_AWSIZE),\n        .s_axi_awvalid(m01_couplers_to_m01_regslice_AWVALID),\n        .s_axi_bid(m01_couplers_to_m01_regslice_BID),\n        .s_axi_bready(m01_couplers_to_m01_regslice_BREADY),\n        .s_axi_bresp(m01_couplers_to_m01_regslice_BRESP),\n        .s_axi_bvalid(m01_couplers_to_m01_regslice_BVALID),\n        .s_axi_rdata(m01_couplers_to_m01_regslice_RDATA),\n        .s_axi_rid(m01_couplers_to_m01_regslice_RID),\n        .s_axi_rlast(m01_couplers_to_m01_regslice_RLAST),\n        .s_axi_rready(m01_couplers_to_m01_regslice_RREADY),\n        .s_axi_rresp(m01_couplers_to_m01_regslice_RRESP),\n        .s_axi_rvalid(m01_couplers_to_m01_regslice_RVALID),\n        .s_axi_wdata(m01_couplers_to_m01_regslice_WDATA),\n        .s_axi_wlast(m01_couplers_to_m01_regslice_WLAST),\n        .s_axi_wready(m01_couplers_to_m01_regslice_WREADY),\n        .s_axi_wstrb(m01_couplers_to_m01_regslice_WSTRB),\n        .s_axi_wvalid(m01_couplers_to_m01_regslice_WVALID));\nendmodule\n\nmodule m02_couplers_imp_APDUS2\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m02_couplers_to_m02_regslice_ARADDR;\n  wire [1:0]m02_couplers_to_m02_regslice_ARBURST;\n  wire [3:0]m02_couplers_to_m02_regslice_ARCACHE;\n  wire [6:0]m02_couplers_to_m02_regslice_ARID;\n  wire [7:0]m02_couplers_to_m02_regslice_ARLEN;\n  wire [0:0]m02_couplers_to_m02_regslice_ARLOCK;\n  wire [2:0]m02_couplers_to_m02_regslice_ARPROT;\n  wire [3:0]m02_couplers_to_m02_regslice_ARQOS;\n  wire m02_couplers_to_m02_regslice_ARREADY;\n  wire [3:0]m02_couplers_to_m02_regslice_ARREGION;\n  wire [2:0]m02_couplers_to_m02_regslice_ARSIZE;\n  wire m02_couplers_to_m02_regslice_ARVALID;\n  wire [63:0]m02_couplers_to_m02_regslice_AWADDR;\n  wire [1:0]m02_couplers_to_m02_regslice_AWBURST;\n  wire [3:0]m02_couplers_to_m02_regslice_AWCACHE;\n  wire [6:0]m02_couplers_to_m02_regslice_AWID;\n  wire [7:0]m02_couplers_to_m02_regslice_AWLEN;\n  wire [0:0]m02_couplers_to_m02_regslice_AWLOCK;\n  wire [2:0]m02_couplers_to_m02_regslice_AWPROT;\n  wire [3:0]m02_couplers_to_m02_regslice_AWQOS;\n  wire m02_couplers_to_m02_regslice_AWREADY;\n  wire [3:0]m02_couplers_to_m02_regslice_AWREGION;\n  wire [2:0]m02_couplers_to_m02_regslice_AWSIZE;\n  wire m02_couplers_to_m02_regslice_AWVALID;\n  wire [6:0]m02_couplers_to_m02_regslice_BID;\n  wire m02_couplers_to_m02_regslice_BREADY;\n  wire [1:0]m02_couplers_to_m02_regslice_BRESP;\n  wire m02_couplers_to_m02_regslice_BVALID;\n  wire [511:0]m02_couplers_to_m02_regslice_RDATA;\n  wire [6:0]m02_couplers_to_m02_regslice_RID;\n  wire m02_couplers_to_m02_regslice_RLAST;\n  wire m02_couplers_to_m02_regslice_RREADY;\n  wire [1:0]m02_couplers_to_m02_regslice_RRESP;\n  wire m02_couplers_to_m02_regslice_RVALID;\n  wire [511:0]m02_couplers_to_m02_regslice_WDATA;\n  wire m02_couplers_to_m02_regslice_WLAST;\n  wire m02_couplers_to_m02_regslice_WREADY;\n  wire [63:0]m02_couplers_to_m02_regslice_WSTRB;\n  wire m02_couplers_to_m02_regslice_WVALID;\n  wire [63:0]m02_regslice_to_m02_couplers_ARADDR;\n  wire [1:0]m02_regslice_to_m02_couplers_ARBURST;\n  wire [3:0]m02_regslice_to_m02_couplers_ARCACHE;\n  wire [6:0]m02_regslice_to_m02_couplers_ARID;\n  wire [7:0]m02_regslice_to_m02_couplers_ARLEN;\n  wire [0:0]m02_regslice_to_m02_couplers_ARLOCK;\n  wire [2:0]m02_regslice_to_m02_couplers_ARPROT;\n  wire [3:0]m02_regslice_to_m02_couplers_ARQOS;\n  wire m02_regslice_to_m02_couplers_ARREADY;\n  wire [3:0]m02_regslice_to_m02_couplers_ARREGION;\n  wire [2:0]m02_regslice_to_m02_couplers_ARSIZE;\n  wire m02_regslice_to_m02_couplers_ARVALID;\n  wire [63:0]m02_regslice_to_m02_couplers_AWADDR;\n  wire [1:0]m02_regslice_to_m02_couplers_AWBURST;\n  wire [3:0]m02_regslice_to_m02_couplers_AWCACHE;\n  wire [6:0]m02_regslice_to_m02_couplers_AWID;\n  wire [7:0]m02_regslice_to_m02_couplers_AWLEN;\n  wire [0:0]m02_regslice_to_m02_couplers_AWLOCK;\n  wire [2:0]m02_regslice_to_m02_couplers_AWPROT;\n  wire [3:0]m02_regslice_to_m02_couplers_AWQOS;\n  wire m02_regslice_to_m02_couplers_AWREADY;\n  wire [3:0]m02_regslice_to_m02_couplers_AWREGION;\n  wire [2:0]m02_regslice_to_m02_couplers_AWSIZE;\n  wire m02_regslice_to_m02_couplers_AWVALID;\n  wire [6:0]m02_regslice_to_m02_couplers_BID;\n  wire m02_regslice_to_m02_couplers_BREADY;\n  wire [1:0]m02_regslice_to_m02_couplers_BRESP;\n  wire m02_regslice_to_m02_couplers_BVALID;\n  wire [511:0]m02_regslice_to_m02_couplers_RDATA;\n  wire [6:0]m02_regslice_to_m02_couplers_RID;\n  wire m02_regslice_to_m02_couplers_RLAST;\n  wire m02_regslice_to_m02_couplers_RREADY;\n  wire [1:0]m02_regslice_to_m02_couplers_RRESP;\n  wire m02_regslice_to_m02_couplers_RVALID;\n  wire [511:0]m02_regslice_to_m02_couplers_WDATA;\n  wire m02_regslice_to_m02_couplers_WLAST;\n  wire m02_regslice_to_m02_couplers_WREADY;\n  wire [63:0]m02_regslice_to_m02_couplers_WSTRB;\n  wire m02_regslice_to_m02_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m02_regslice_to_m02_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m02_regslice_to_m02_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m02_regslice_to_m02_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m02_regslice_to_m02_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m02_regslice_to_m02_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m02_regslice_to_m02_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m02_regslice_to_m02_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m02_regslice_to_m02_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m02_regslice_to_m02_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m02_regslice_to_m02_couplers_ARSIZE;\n  assign M_AXI_arvalid = m02_regslice_to_m02_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m02_regslice_to_m02_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m02_regslice_to_m02_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m02_regslice_to_m02_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m02_regslice_to_m02_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m02_regslice_to_m02_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m02_regslice_to_m02_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m02_regslice_to_m02_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m02_regslice_to_m02_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m02_regslice_to_m02_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m02_regslice_to_m02_couplers_AWSIZE;\n  assign M_AXI_awvalid = m02_regslice_to_m02_couplers_AWVALID;\n  assign M_AXI_bready = m02_regslice_to_m02_couplers_BREADY;\n  assign M_AXI_rready = m02_regslice_to_m02_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m02_regslice_to_m02_couplers_WDATA;\n  assign M_AXI_wlast = m02_regslice_to_m02_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m02_regslice_to_m02_couplers_WSTRB;\n  assign M_AXI_wvalid = m02_regslice_to_m02_couplers_WVALID;\n  assign S_AXI_arready = m02_couplers_to_m02_regslice_ARREADY;\n  assign S_AXI_awready = m02_couplers_to_m02_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m02_couplers_to_m02_regslice_BID;\n  assign S_AXI_bresp[1:0] = m02_couplers_to_m02_regslice_BRESP;\n  assign S_AXI_bvalid = m02_couplers_to_m02_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m02_couplers_to_m02_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m02_couplers_to_m02_regslice_RID;\n  assign S_AXI_rlast = m02_couplers_to_m02_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m02_couplers_to_m02_regslice_RRESP;\n  assign S_AXI_rvalid = m02_couplers_to_m02_regslice_RVALID;\n  assign S_AXI_wready = m02_couplers_to_m02_regslice_WREADY;\n  assign m02_couplers_to_m02_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m02_couplers_to_m02_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m02_couplers_to_m02_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m02_couplers_to_m02_regslice_ARID = S_AXI_arid[6:0];\n  assign m02_couplers_to_m02_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m02_couplers_to_m02_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m02_couplers_to_m02_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m02_couplers_to_m02_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m02_couplers_to_m02_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m02_couplers_to_m02_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m02_couplers_to_m02_regslice_ARVALID = S_AXI_arvalid;\n  assign m02_couplers_to_m02_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m02_couplers_to_m02_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m02_couplers_to_m02_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m02_couplers_to_m02_regslice_AWID = S_AXI_awid[6:0];\n  assign m02_couplers_to_m02_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m02_couplers_to_m02_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m02_couplers_to_m02_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m02_couplers_to_m02_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m02_couplers_to_m02_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m02_couplers_to_m02_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m02_couplers_to_m02_regslice_AWVALID = S_AXI_awvalid;\n  assign m02_couplers_to_m02_regslice_BREADY = S_AXI_bready;\n  assign m02_couplers_to_m02_regslice_RREADY = S_AXI_rready;\n  assign m02_couplers_to_m02_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m02_couplers_to_m02_regslice_WLAST = S_AXI_wlast;\n  assign m02_couplers_to_m02_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m02_couplers_to_m02_regslice_WVALID = S_AXI_wvalid;\n  assign m02_regslice_to_m02_couplers_ARREADY = M_AXI_arready;\n  assign m02_regslice_to_m02_couplers_AWREADY = M_AXI_awready;\n  assign m02_regslice_to_m02_couplers_BID = M_AXI_bid[6:0];\n  assign m02_regslice_to_m02_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m02_regslice_to_m02_couplers_BVALID = M_AXI_bvalid;\n  assign m02_regslice_to_m02_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m02_regslice_to_m02_couplers_RID = M_AXI_rid[6:0];\n  assign m02_regslice_to_m02_couplers_RLAST = M_AXI_rlast;\n  assign m02_regslice_to_m02_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m02_regslice_to_m02_couplers_RVALID = M_AXI_rvalid;\n  assign m02_regslice_to_m02_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m02_regslice_0 m02_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m02_regslice_to_m02_couplers_ARADDR),\n        .m_axi_arburst(m02_regslice_to_m02_couplers_ARBURST),\n        .m_axi_arcache(m02_regslice_to_m02_couplers_ARCACHE),\n        .m_axi_arid(m02_regslice_to_m02_couplers_ARID),\n        .m_axi_arlen(m02_regslice_to_m02_couplers_ARLEN),\n        .m_axi_arlock(m02_regslice_to_m02_couplers_ARLOCK),\n        .m_axi_arprot(m02_regslice_to_m02_couplers_ARPROT),\n        .m_axi_arqos(m02_regslice_to_m02_couplers_ARQOS),\n        .m_axi_arready(m02_regslice_to_m02_couplers_ARREADY),\n        .m_axi_arregion(m02_regslice_to_m02_couplers_ARREGION),\n        .m_axi_arsize(m02_regslice_to_m02_couplers_ARSIZE),\n        .m_axi_arvalid(m02_regslice_to_m02_couplers_ARVALID),\n        .m_axi_awaddr(m02_regslice_to_m02_couplers_AWADDR),\n        .m_axi_awburst(m02_regslice_to_m02_couplers_AWBURST),\n        .m_axi_awcache(m02_regslice_to_m02_couplers_AWCACHE),\n        .m_axi_awid(m02_regslice_to_m02_couplers_AWID),\n        .m_axi_awlen(m02_regslice_to_m02_couplers_AWLEN),\n        .m_axi_awlock(m02_regslice_to_m02_couplers_AWLOCK),\n        .m_axi_awprot(m02_regslice_to_m02_couplers_AWPROT),\n        .m_axi_awqos(m02_regslice_to_m02_couplers_AWQOS),\n        .m_axi_awready(m02_regslice_to_m02_couplers_AWREADY),\n        .m_axi_awregion(m02_regslice_to_m02_couplers_AWREGION),\n        .m_axi_awsize(m02_regslice_to_m02_couplers_AWSIZE),\n        .m_axi_awvalid(m02_regslice_to_m02_couplers_AWVALID),\n        .m_axi_bid(m02_regslice_to_m02_couplers_BID),\n        .m_axi_bready(m02_regslice_to_m02_couplers_BREADY),\n        .m_axi_bresp(m02_regslice_to_m02_couplers_BRESP),\n        .m_axi_bvalid(m02_regslice_to_m02_couplers_BVALID),\n        .m_axi_rdata(m02_regslice_to_m02_couplers_RDATA),\n        .m_axi_rid(m02_regslice_to_m02_couplers_RID),\n        .m_axi_rlast(m02_regslice_to_m02_couplers_RLAST),\n        .m_axi_rready(m02_regslice_to_m02_couplers_RREADY),\n        .m_axi_rresp(m02_regslice_to_m02_couplers_RRESP),\n        .m_axi_rvalid(m02_regslice_to_m02_couplers_RVALID),\n        .m_axi_wdata(m02_regslice_to_m02_couplers_WDATA),\n        .m_axi_wlast(m02_regslice_to_m02_couplers_WLAST),\n        .m_axi_wready(m02_regslice_to_m02_couplers_WREADY),\n        .m_axi_wstrb(m02_regslice_to_m02_couplers_WSTRB),\n        .m_axi_wvalid(m02_regslice_to_m02_couplers_WVALID),\n        .s_axi_araddr(m02_couplers_to_m02_regslice_ARADDR),\n        .s_axi_arburst(m02_couplers_to_m02_regslice_ARBURST),\n        .s_axi_arcache(m02_couplers_to_m02_regslice_ARCACHE),\n        .s_axi_arid(m02_couplers_to_m02_regslice_ARID),\n        .s_axi_arlen(m02_couplers_to_m02_regslice_ARLEN),\n        .s_axi_arlock(m02_couplers_to_m02_regslice_ARLOCK),\n        .s_axi_arprot(m02_couplers_to_m02_regslice_ARPROT),\n        .s_axi_arqos(m02_couplers_to_m02_regslice_ARQOS),\n        .s_axi_arready(m02_couplers_to_m02_regslice_ARREADY),\n        .s_axi_arregion(m02_couplers_to_m02_regslice_ARREGION),\n        .s_axi_arsize(m02_couplers_to_m02_regslice_ARSIZE),\n        .s_axi_arvalid(m02_couplers_to_m02_regslice_ARVALID),\n        .s_axi_awaddr(m02_couplers_to_m02_regslice_AWADDR),\n        .s_axi_awburst(m02_couplers_to_m02_regslice_AWBURST),\n        .s_axi_awcache(m02_couplers_to_m02_regslice_AWCACHE),\n        .s_axi_awid(m02_couplers_to_m02_regslice_AWID),\n        .s_axi_awlen(m02_couplers_to_m02_regslice_AWLEN),\n        .s_axi_awlock(m02_couplers_to_m02_regslice_AWLOCK),\n        .s_axi_awprot(m02_couplers_to_m02_regslice_AWPROT),\n        .s_axi_awqos(m02_couplers_to_m02_regslice_AWQOS),\n        .s_axi_awready(m02_couplers_to_m02_regslice_AWREADY),\n        .s_axi_awregion(m02_couplers_to_m02_regslice_AWREGION),\n        .s_axi_awsize(m02_couplers_to_m02_regslice_AWSIZE),\n        .s_axi_awvalid(m02_couplers_to_m02_regslice_AWVALID),\n        .s_axi_bid(m02_couplers_to_m02_regslice_BID),\n        .s_axi_bready(m02_couplers_to_m02_regslice_BREADY),\n        .s_axi_bresp(m02_couplers_to_m02_regslice_BRESP),\n        .s_axi_bvalid(m02_couplers_to_m02_regslice_BVALID),\n        .s_axi_rdata(m02_couplers_to_m02_regslice_RDATA),\n        .s_axi_rid(m02_couplers_to_m02_regslice_RID),\n        .s_axi_rlast(m02_couplers_to_m02_regslice_RLAST),\n        .s_axi_rready(m02_couplers_to_m02_regslice_RREADY),\n        .s_axi_rresp(m02_couplers_to_m02_regslice_RRESP),\n        .s_axi_rvalid(m02_couplers_to_m02_regslice_RVALID),\n        .s_axi_wdata(m02_couplers_to_m02_regslice_WDATA),\n        .s_axi_wlast(m02_couplers_to_m02_regslice_WLAST),\n        .s_axi_wready(m02_couplers_to_m02_regslice_WREADY),\n        .s_axi_wstrb(m02_couplers_to_m02_regslice_WSTRB),\n        .s_axi_wvalid(m02_couplers_to_m02_regslice_WVALID));\nendmodule\n\nmodule m03_couplers_imp_JAYOMU\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m03_couplers_to_m03_regslice_ARADDR;\n  wire [1:0]m03_couplers_to_m03_regslice_ARBURST;\n  wire [3:0]m03_couplers_to_m03_regslice_ARCACHE;\n  wire [6:0]m03_couplers_to_m03_regslice_ARID;\n  wire [7:0]m03_couplers_to_m03_regslice_ARLEN;\n  wire [0:0]m03_couplers_to_m03_regslice_ARLOCK;\n  wire [2:0]m03_couplers_to_m03_regslice_ARPROT;\n  wire [3:0]m03_couplers_to_m03_regslice_ARQOS;\n  wire m03_couplers_to_m03_regslice_ARREADY;\n  wire [3:0]m03_couplers_to_m03_regslice_ARREGION;\n  wire [2:0]m03_couplers_to_m03_regslice_ARSIZE;\n  wire m03_couplers_to_m03_regslice_ARVALID;\n  wire [63:0]m03_couplers_to_m03_regslice_AWADDR;\n  wire [1:0]m03_couplers_to_m03_regslice_AWBURST;\n  wire [3:0]m03_couplers_to_m03_regslice_AWCACHE;\n  wire [6:0]m03_couplers_to_m03_regslice_AWID;\n  wire [7:0]m03_couplers_to_m03_regslice_AWLEN;\n  wire [0:0]m03_couplers_to_m03_regslice_AWLOCK;\n  wire [2:0]m03_couplers_to_m03_regslice_AWPROT;\n  wire [3:0]m03_couplers_to_m03_regslice_AWQOS;\n  wire m03_couplers_to_m03_regslice_AWREADY;\n  wire [3:0]m03_couplers_to_m03_regslice_AWREGION;\n  wire [2:0]m03_couplers_to_m03_regslice_AWSIZE;\n  wire m03_couplers_to_m03_regslice_AWVALID;\n  wire [6:0]m03_couplers_to_m03_regslice_BID;\n  wire m03_couplers_to_m03_regslice_BREADY;\n  wire [1:0]m03_couplers_to_m03_regslice_BRESP;\n  wire m03_couplers_to_m03_regslice_BVALID;\n  wire [511:0]m03_couplers_to_m03_regslice_RDATA;\n  wire [6:0]m03_couplers_to_m03_regslice_RID;\n  wire m03_couplers_to_m03_regslice_RLAST;\n  wire m03_couplers_to_m03_regslice_RREADY;\n  wire [1:0]m03_couplers_to_m03_regslice_RRESP;\n  wire m03_couplers_to_m03_regslice_RVALID;\n  wire [511:0]m03_couplers_to_m03_regslice_WDATA;\n  wire m03_couplers_to_m03_regslice_WLAST;\n  wire m03_couplers_to_m03_regslice_WREADY;\n  wire [63:0]m03_couplers_to_m03_regslice_WSTRB;\n  wire m03_couplers_to_m03_regslice_WVALID;\n  wire [63:0]m03_regslice_to_m03_couplers_ARADDR;\n  wire [1:0]m03_regslice_to_m03_couplers_ARBURST;\n  wire [3:0]m03_regslice_to_m03_couplers_ARCACHE;\n  wire [6:0]m03_regslice_to_m03_couplers_ARID;\n  wire [7:0]m03_regslice_to_m03_couplers_ARLEN;\n  wire [0:0]m03_regslice_to_m03_couplers_ARLOCK;\n  wire [2:0]m03_regslice_to_m03_couplers_ARPROT;\n  wire [3:0]m03_regslice_to_m03_couplers_ARQOS;\n  wire m03_regslice_to_m03_couplers_ARREADY;\n  wire [3:0]m03_regslice_to_m03_couplers_ARREGION;\n  wire [2:0]m03_regslice_to_m03_couplers_ARSIZE;\n  wire m03_regslice_to_m03_couplers_ARVALID;\n  wire [63:0]m03_regslice_to_m03_couplers_AWADDR;\n  wire [1:0]m03_regslice_to_m03_couplers_AWBURST;\n  wire [3:0]m03_regslice_to_m03_couplers_AWCACHE;\n  wire [6:0]m03_regslice_to_m03_couplers_AWID;\n  wire [7:0]m03_regslice_to_m03_couplers_AWLEN;\n  wire [0:0]m03_regslice_to_m03_couplers_AWLOCK;\n  wire [2:0]m03_regslice_to_m03_couplers_AWPROT;\n  wire [3:0]m03_regslice_to_m03_couplers_AWQOS;\n  wire m03_regslice_to_m03_couplers_AWREADY;\n  wire [3:0]m03_regslice_to_m03_couplers_AWREGION;\n  wire [2:0]m03_regslice_to_m03_couplers_AWSIZE;\n  wire m03_regslice_to_m03_couplers_AWVALID;\n  wire [6:0]m03_regslice_to_m03_couplers_BID;\n  wire m03_regslice_to_m03_couplers_BREADY;\n  wire [1:0]m03_regslice_to_m03_couplers_BRESP;\n  wire m03_regslice_to_m03_couplers_BVALID;\n  wire [511:0]m03_regslice_to_m03_couplers_RDATA;\n  wire [6:0]m03_regslice_to_m03_couplers_RID;\n  wire m03_regslice_to_m03_couplers_RLAST;\n  wire m03_regslice_to_m03_couplers_RREADY;\n  wire [1:0]m03_regslice_to_m03_couplers_RRESP;\n  wire m03_regslice_to_m03_couplers_RVALID;\n  wire [511:0]m03_regslice_to_m03_couplers_WDATA;\n  wire m03_regslice_to_m03_couplers_WLAST;\n  wire m03_regslice_to_m03_couplers_WREADY;\n  wire [63:0]m03_regslice_to_m03_couplers_WSTRB;\n  wire m03_regslice_to_m03_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m03_regslice_to_m03_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m03_regslice_to_m03_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m03_regslice_to_m03_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m03_regslice_to_m03_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m03_regslice_to_m03_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m03_regslice_to_m03_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m03_regslice_to_m03_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m03_regslice_to_m03_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m03_regslice_to_m03_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m03_regslice_to_m03_couplers_ARSIZE;\n  assign M_AXI_arvalid = m03_regslice_to_m03_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m03_regslice_to_m03_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m03_regslice_to_m03_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m03_regslice_to_m03_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m03_regslice_to_m03_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m03_regslice_to_m03_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m03_regslice_to_m03_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m03_regslice_to_m03_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m03_regslice_to_m03_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m03_regslice_to_m03_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m03_regslice_to_m03_couplers_AWSIZE;\n  assign M_AXI_awvalid = m03_regslice_to_m03_couplers_AWVALID;\n  assign M_AXI_bready = m03_regslice_to_m03_couplers_BREADY;\n  assign M_AXI_rready = m03_regslice_to_m03_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m03_regslice_to_m03_couplers_WDATA;\n  assign M_AXI_wlast = m03_regslice_to_m03_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m03_regslice_to_m03_couplers_WSTRB;\n  assign M_AXI_wvalid = m03_regslice_to_m03_couplers_WVALID;\n  assign S_AXI_arready = m03_couplers_to_m03_regslice_ARREADY;\n  assign S_AXI_awready = m03_couplers_to_m03_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m03_couplers_to_m03_regslice_BID;\n  assign S_AXI_bresp[1:0] = m03_couplers_to_m03_regslice_BRESP;\n  assign S_AXI_bvalid = m03_couplers_to_m03_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m03_couplers_to_m03_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m03_couplers_to_m03_regslice_RID;\n  assign S_AXI_rlast = m03_couplers_to_m03_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m03_couplers_to_m03_regslice_RRESP;\n  assign S_AXI_rvalid = m03_couplers_to_m03_regslice_RVALID;\n  assign S_AXI_wready = m03_couplers_to_m03_regslice_WREADY;\n  assign m03_couplers_to_m03_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m03_couplers_to_m03_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m03_couplers_to_m03_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m03_couplers_to_m03_regslice_ARID = S_AXI_arid[6:0];\n  assign m03_couplers_to_m03_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m03_couplers_to_m03_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m03_couplers_to_m03_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m03_couplers_to_m03_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m03_couplers_to_m03_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m03_couplers_to_m03_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m03_couplers_to_m03_regslice_ARVALID = S_AXI_arvalid;\n  assign m03_couplers_to_m03_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m03_couplers_to_m03_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m03_couplers_to_m03_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m03_couplers_to_m03_regslice_AWID = S_AXI_awid[6:0];\n  assign m03_couplers_to_m03_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m03_couplers_to_m03_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m03_couplers_to_m03_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m03_couplers_to_m03_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m03_couplers_to_m03_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m03_couplers_to_m03_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m03_couplers_to_m03_regslice_AWVALID = S_AXI_awvalid;\n  assign m03_couplers_to_m03_regslice_BREADY = S_AXI_bready;\n  assign m03_couplers_to_m03_regslice_RREADY = S_AXI_rready;\n  assign m03_couplers_to_m03_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m03_couplers_to_m03_regslice_WLAST = S_AXI_wlast;\n  assign m03_couplers_to_m03_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m03_couplers_to_m03_regslice_WVALID = S_AXI_wvalid;\n  assign m03_regslice_to_m03_couplers_ARREADY = M_AXI_arready;\n  assign m03_regslice_to_m03_couplers_AWREADY = M_AXI_awready;\n  assign m03_regslice_to_m03_couplers_BID = M_AXI_bid[6:0];\n  assign m03_regslice_to_m03_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m03_regslice_to_m03_couplers_BVALID = M_AXI_bvalid;\n  assign m03_regslice_to_m03_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m03_regslice_to_m03_couplers_RID = M_AXI_rid[6:0];\n  assign m03_regslice_to_m03_couplers_RLAST = M_AXI_rlast;\n  assign m03_regslice_to_m03_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m03_regslice_to_m03_couplers_RVALID = M_AXI_rvalid;\n  assign m03_regslice_to_m03_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m03_regslice_0 m03_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m03_regslice_to_m03_couplers_ARADDR),\n        .m_axi_arburst(m03_regslice_to_m03_couplers_ARBURST),\n        .m_axi_arcache(m03_regslice_to_m03_couplers_ARCACHE),\n        .m_axi_arid(m03_regslice_to_m03_couplers_ARID),\n        .m_axi_arlen(m03_regslice_to_m03_couplers_ARLEN),\n        .m_axi_arlock(m03_regslice_to_m03_couplers_ARLOCK),\n        .m_axi_arprot(m03_regslice_to_m03_couplers_ARPROT),\n        .m_axi_arqos(m03_regslice_to_m03_couplers_ARQOS),\n        .m_axi_arready(m03_regslice_to_m03_couplers_ARREADY),\n        .m_axi_arregion(m03_regslice_to_m03_couplers_ARREGION),\n        .m_axi_arsize(m03_regslice_to_m03_couplers_ARSIZE),\n        .m_axi_arvalid(m03_regslice_to_m03_couplers_ARVALID),\n        .m_axi_awaddr(m03_regslice_to_m03_couplers_AWADDR),\n        .m_axi_awburst(m03_regslice_to_m03_couplers_AWBURST),\n        .m_axi_awcache(m03_regslice_to_m03_couplers_AWCACHE),\n        .m_axi_awid(m03_regslice_to_m03_couplers_AWID),\n        .m_axi_awlen(m03_regslice_to_m03_couplers_AWLEN),\n        .m_axi_awlock(m03_regslice_to_m03_couplers_AWLOCK),\n        .m_axi_awprot(m03_regslice_to_m03_couplers_AWPROT),\n        .m_axi_awqos(m03_regslice_to_m03_couplers_AWQOS),\n        .m_axi_awready(m03_regslice_to_m03_couplers_AWREADY),\n        .m_axi_awregion(m03_regslice_to_m03_couplers_AWREGION),\n        .m_axi_awsize(m03_regslice_to_m03_couplers_AWSIZE),\n        .m_axi_awvalid(m03_regslice_to_m03_couplers_AWVALID),\n        .m_axi_bid(m03_regslice_to_m03_couplers_BID),\n        .m_axi_bready(m03_regslice_to_m03_couplers_BREADY),\n        .m_axi_bresp(m03_regslice_to_m03_couplers_BRESP),\n        .m_axi_bvalid(m03_regslice_to_m03_couplers_BVALID),\n        .m_axi_rdata(m03_regslice_to_m03_couplers_RDATA),\n        .m_axi_rid(m03_regslice_to_m03_couplers_RID),\n        .m_axi_rlast(m03_regslice_to_m03_couplers_RLAST),\n        .m_axi_rready(m03_regslice_to_m03_couplers_RREADY),\n        .m_axi_rresp(m03_regslice_to_m03_couplers_RRESP),\n        .m_axi_rvalid(m03_regslice_to_m03_couplers_RVALID),\n        .m_axi_wdata(m03_regslice_to_m03_couplers_WDATA),\n        .m_axi_wlast(m03_regslice_to_m03_couplers_WLAST),\n        .m_axi_wready(m03_regslice_to_m03_couplers_WREADY),\n        .m_axi_wstrb(m03_regslice_to_m03_couplers_WSTRB),\n        .m_axi_wvalid(m03_regslice_to_m03_couplers_WVALID),\n        .s_axi_araddr(m03_couplers_to_m03_regslice_ARADDR),\n        .s_axi_arburst(m03_couplers_to_m03_regslice_ARBURST),\n        .s_axi_arcache(m03_couplers_to_m03_regslice_ARCACHE),\n        .s_axi_arid(m03_couplers_to_m03_regslice_ARID),\n        .s_axi_arlen(m03_couplers_to_m03_regslice_ARLEN),\n        .s_axi_arlock(m03_couplers_to_m03_regslice_ARLOCK),\n        .s_axi_arprot(m03_couplers_to_m03_regslice_ARPROT),\n        .s_axi_arqos(m03_couplers_to_m03_regslice_ARQOS),\n        .s_axi_arready(m03_couplers_to_m03_regslice_ARREADY),\n        .s_axi_arregion(m03_couplers_to_m03_regslice_ARREGION),\n        .s_axi_arsize(m03_couplers_to_m03_regslice_ARSIZE),\n        .s_axi_arvalid(m03_couplers_to_m03_regslice_ARVALID),\n        .s_axi_awaddr(m03_couplers_to_m03_regslice_AWADDR),\n        .s_axi_awburst(m03_couplers_to_m03_regslice_AWBURST),\n        .s_axi_awcache(m03_couplers_to_m03_regslice_AWCACHE),\n        .s_axi_awid(m03_couplers_to_m03_regslice_AWID),\n        .s_axi_awlen(m03_couplers_to_m03_regslice_AWLEN),\n        .s_axi_awlock(m03_couplers_to_m03_regslice_AWLOCK),\n        .s_axi_awprot(m03_couplers_to_m03_regslice_AWPROT),\n        .s_axi_awqos(m03_couplers_to_m03_regslice_AWQOS),\n        .s_axi_awready(m03_couplers_to_m03_regslice_AWREADY),\n        .s_axi_awregion(m03_couplers_to_m03_regslice_AWREGION),\n        .s_axi_awsize(m03_couplers_to_m03_regslice_AWSIZE),\n        .s_axi_awvalid(m03_couplers_to_m03_regslice_AWVALID),\n        .s_axi_bid(m03_couplers_to_m03_regslice_BID),\n        .s_axi_bready(m03_couplers_to_m03_regslice_BREADY),\n        .s_axi_bresp(m03_couplers_to_m03_regslice_BRESP),\n        .s_axi_bvalid(m03_couplers_to_m03_regslice_BVALID),\n        .s_axi_rdata(m03_couplers_to_m03_regslice_RDATA),\n        .s_axi_rid(m03_couplers_to_m03_regslice_RID),\n        .s_axi_rlast(m03_couplers_to_m03_regslice_RLAST),\n        .s_axi_rready(m03_couplers_to_m03_regslice_RREADY),\n        .s_axi_rresp(m03_couplers_to_m03_regslice_RRESP),\n        .s_axi_rvalid(m03_couplers_to_m03_regslice_RVALID),\n        .s_axi_wdata(m03_couplers_to_m03_regslice_WDATA),\n        .s_axi_wlast(m03_couplers_to_m03_regslice_WLAST),\n        .s_axi_wready(m03_couplers_to_m03_regslice_WREADY),\n        .s_axi_wstrb(m03_couplers_to_m03_regslice_WSTRB),\n        .s_axi_wvalid(m03_couplers_to_m03_regslice_WVALID));\nendmodule\n\nmodule s00_couplers_imp_QICM5G\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [5:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [5:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [5:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [5:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [5:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [5:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire S_ACLK_1;\n  wire S_ARESETN_1;\n  wire [63:0]s00_couplers_to_s00_regslice_ARADDR;\n  wire [1:0]s00_couplers_to_s00_regslice_ARBURST;\n  wire [3:0]s00_couplers_to_s00_regslice_ARCACHE;\n  wire [5:0]s00_couplers_to_s00_regslice_ARID;\n  wire [7:0]s00_couplers_to_s00_regslice_ARLEN;\n  wire [0:0]s00_couplers_to_s00_regslice_ARLOCK;\n  wire [2:0]s00_couplers_to_s00_regslice_ARPROT;\n  wire [3:0]s00_couplers_to_s00_regslice_ARQOS;\n  wire s00_couplers_to_s00_regslice_ARREADY;\n  wire [3:0]s00_couplers_to_s00_regslice_ARREGION;\n  wire [2:0]s00_couplers_to_s00_regslice_ARSIZE;\n  wire s00_couplers_to_s00_regslice_ARVALID;\n  wire [63:0]s00_couplers_to_s00_regslice_AWADDR;\n  wire [1:0]s00_couplers_to_s00_regslice_AWBURST;\n  wire [3:0]s00_couplers_to_s00_regslice_AWCACHE;\n  wire [5:0]s00_couplers_to_s00_regslice_AWID;\n  wire [7:0]s00_couplers_to_s00_regslice_AWLEN;\n  wire [0:0]s00_couplers_to_s00_regslice_AWLOCK;\n  wire [2:0]s00_couplers_to_s00_regslice_AWPROT;\n  wire [3:0]s00_couplers_to_s00_regslice_AWQOS;\n  wire s00_couplers_to_s00_regslice_AWREADY;\n  wire [3:0]s00_couplers_to_s00_regslice_AWREGION;\n  wire [2:0]s00_couplers_to_s00_regslice_AWSIZE;\n  wire s00_couplers_to_s00_regslice_AWVALID;\n  wire [5:0]s00_couplers_to_s00_regslice_BID;\n  wire s00_couplers_to_s00_regslice_BREADY;\n  wire [1:0]s00_couplers_to_s00_regslice_BRESP;\n  wire s00_couplers_to_s00_regslice_BVALID;\n  wire [511:0]s00_couplers_to_s00_regslice_RDATA;\n  wire [5:0]s00_couplers_to_s00_regslice_RID;\n  wire s00_couplers_to_s00_regslice_RLAST;\n  wire s00_couplers_to_s00_regslice_RREADY;\n  wire [1:0]s00_couplers_to_s00_regslice_RRESP;\n  wire s00_couplers_to_s00_regslice_RVALID;\n  wire [511:0]s00_couplers_to_s00_regslice_WDATA;\n  wire s00_couplers_to_s00_regslice_WLAST;\n  wire s00_couplers_to_s00_regslice_WREADY;\n  wire [63:0]s00_couplers_to_s00_regslice_WSTRB;\n  wire s00_couplers_to_s00_regslice_WVALID;\n  wire [63:0]s00_regslice_to_s00_couplers_ARADDR;\n  wire [1:0]s00_regslice_to_s00_couplers_ARBURST;\n  wire [3:0]s00_regslice_to_s00_couplers_ARCACHE;\n  wire [5:0]s00_regslice_to_s00_couplers_ARID;\n  wire [7:0]s00_regslice_to_s00_couplers_ARLEN;\n  wire [0:0]s00_regslice_to_s00_couplers_ARLOCK;\n  wire [2:0]s00_regslice_to_s00_couplers_ARPROT;\n  wire [3:0]s00_regslice_to_s00_couplers_ARQOS;\n  wire s00_regslice_to_s00_couplers_ARREADY;\n  wire [2:0]s00_regslice_to_s00_couplers_ARSIZE;\n  wire s00_regslice_to_s00_couplers_ARVALID;\n  wire [63:0]s00_regslice_to_s00_couplers_AWADDR;\n  wire [1:0]s00_regslice_to_s00_couplers_AWBURST;\n  wire [3:0]s00_regslice_to_s00_couplers_AWCACHE;\n  wire [5:0]s00_regslice_to_s00_couplers_AWID;\n  wire [7:0]s00_regslice_to_s00_couplers_AWLEN;\n  wire [0:0]s00_regslice_to_s00_couplers_AWLOCK;\n  wire [2:0]s00_regslice_to_s00_couplers_AWPROT;\n  wire [3:0]s00_regslice_to_s00_couplers_AWQOS;\n  wire s00_regslice_to_s00_couplers_AWREADY;\n  wire [2:0]s00_regslice_to_s00_couplers_AWSIZE;\n  wire s00_regslice_to_s00_couplers_AWVALID;\n  wire [6:0]s00_regslice_to_s00_couplers_BID;\n  wire s00_regslice_to_s00_couplers_BREADY;\n  wire [1:0]s00_regslice_to_s00_couplers_BRESP;\n  wire s00_regslice_to_s00_couplers_BVALID;\n  wire [511:0]s00_regslice_to_s00_couplers_RDATA;\n  wire [6:0]s00_regslice_to_s00_couplers_RID;\n  wire s00_regslice_to_s00_couplers_RLAST;\n  wire s00_regslice_to_s00_couplers_RREADY;\n  wire [1:0]s00_regslice_to_s00_couplers_RRESP;\n  wire s00_regslice_to_s00_couplers_RVALID;\n  wire [511:0]s00_regslice_to_s00_couplers_WDATA;\n  wire s00_regslice_to_s00_couplers_WLAST;\n  wire s00_regslice_to_s00_couplers_WREADY;\n  wire [63:0]s00_regslice_to_s00_couplers_WSTRB;\n  wire s00_regslice_to_s00_couplers_WVALID;\n\n  assign M_AXI_araddr[63:0] = s00_regslice_to_s00_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = s00_regslice_to_s00_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = s00_regslice_to_s00_couplers_ARCACHE;\n  assign M_AXI_arid[5:0] = s00_regslice_to_s00_couplers_ARID;\n  assign M_AXI_arlen[7:0] = s00_regslice_to_s00_couplers_ARLEN;\n  assign M_AXI_arlock[0] = s00_regslice_to_s00_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = s00_regslice_to_s00_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = s00_regslice_to_s00_couplers_ARQOS;\n  assign M_AXI_arsize[2:0] = s00_regslice_to_s00_couplers_ARSIZE;\n  assign M_AXI_arvalid = s00_regslice_to_s00_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = s00_regslice_to_s00_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = s00_regslice_to_s00_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = s00_regslice_to_s00_couplers_AWCACHE;\n  assign M_AXI_awid[5:0] = s00_regslice_to_s00_couplers_AWID;\n  assign M_AXI_awlen[7:0] = s00_regslice_to_s00_couplers_AWLEN;\n  assign M_AXI_awlock[0] = s00_regslice_to_s00_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = s00_regslice_to_s00_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = s00_regslice_to_s00_couplers_AWQOS;\n  assign M_AXI_awsize[2:0] = s00_regslice_to_s00_couplers_AWSIZE;\n  assign M_AXI_awvalid = s00_regslice_to_s00_couplers_AWVALID;\n  assign M_AXI_bready = s00_regslice_to_s00_couplers_BREADY;\n  assign M_AXI_rready = s00_regslice_to_s00_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = s00_regslice_to_s00_couplers_WDATA;\n  assign M_AXI_wlast = s00_regslice_to_s00_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = s00_regslice_to_s00_couplers_WSTRB;\n  assign M_AXI_wvalid = s00_regslice_to_s00_couplers_WVALID;\n  assign S_ACLK_1 = S_ACLK;\n  assign S_ARESETN_1 = S_ARESETN;\n  assign S_AXI_arready = s00_couplers_to_s00_regslice_ARREADY;\n  assign S_AXI_awready = s00_couplers_to_s00_regslice_AWREADY;\n  assign S_AXI_bid[5:0] = s00_couplers_to_s00_regslice_BID;\n  assign S_AXI_bresp[1:0] = s00_couplers_to_s00_regslice_BRESP;\n  assign S_AXI_bvalid = s00_couplers_to_s00_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = s00_couplers_to_s00_regslice_RDATA;\n  assign S_AXI_rid[5:0] = s00_couplers_to_s00_regslice_RID;\n  assign S_AXI_rlast = s00_couplers_to_s00_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = s00_couplers_to_s00_regslice_RRESP;\n  assign S_AXI_rvalid = s00_couplers_to_s00_regslice_RVALID;\n  assign S_AXI_wready = s00_couplers_to_s00_regslice_WREADY;\n  assign s00_couplers_to_s00_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign s00_couplers_to_s00_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign s00_couplers_to_s00_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign s00_couplers_to_s00_regslice_ARID = S_AXI_arid[5:0];\n  assign s00_couplers_to_s00_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign s00_couplers_to_s00_regslice_ARLOCK = S_AXI_arlock[0];\n  assign s00_couplers_to_s00_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign s00_couplers_to_s00_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign s00_couplers_to_s00_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign s00_couplers_to_s00_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign s00_couplers_to_s00_regslice_ARVALID = S_AXI_arvalid;\n  assign s00_couplers_to_s00_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign s00_couplers_to_s00_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign s00_couplers_to_s00_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign s00_couplers_to_s00_regslice_AWID = S_AXI_awid[5:0];\n  assign s00_couplers_to_s00_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign s00_couplers_to_s00_regslice_AWLOCK = S_AXI_awlock[0];\n  assign s00_couplers_to_s00_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign s00_couplers_to_s00_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign s00_couplers_to_s00_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign s00_couplers_to_s00_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign s00_couplers_to_s00_regslice_AWVALID = S_AXI_awvalid;\n  assign s00_couplers_to_s00_regslice_BREADY = S_AXI_bready;\n  assign s00_couplers_to_s00_regslice_RREADY = S_AXI_rready;\n  assign s00_couplers_to_s00_regslice_WDATA = S_AXI_wdata[511:0];\n  assign s00_couplers_to_s00_regslice_WLAST = S_AXI_wlast;\n  assign s00_couplers_to_s00_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign s00_couplers_to_s00_regslice_WVALID = S_AXI_wvalid;\n  assign s00_regslice_to_s00_couplers_ARREADY = M_AXI_arready;\n  assign s00_regslice_to_s00_couplers_AWREADY = M_AXI_awready;\n  assign s00_regslice_to_s00_couplers_BID = M_AXI_bid[6:0];\n  assign s00_regslice_to_s00_couplers_BRESP = M_AXI_bresp[1:0];\n  assign s00_regslice_to_s00_couplers_BVALID = M_AXI_bvalid;\n  assign s00_regslice_to_s00_couplers_RDATA = M_AXI_rdata[511:0];\n  assign s00_regslice_to_s00_couplers_RID = M_AXI_rid[6:0];\n  assign s00_regslice_to_s00_couplers_RLAST = M_AXI_rlast;\n  assign s00_regslice_to_s00_couplers_RRESP = M_AXI_rresp[1:0];\n  assign s00_regslice_to_s00_couplers_RVALID = M_AXI_rvalid;\n  assign s00_regslice_to_s00_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_s00_regslice_0 s00_regslice\n       (.aclk(S_ACLK_1),\n        .aresetn(S_ARESETN_1),\n        .m_axi_araddr(s00_regslice_to_s00_couplers_ARADDR),\n        .m_axi_arburst(s00_regslice_to_s00_couplers_ARBURST),\n        .m_axi_arcache(s00_regslice_to_s00_couplers_ARCACHE),\n        .m_axi_arid(s00_regslice_to_s00_couplers_ARID),\n        .m_axi_arlen(s00_regslice_to_s00_couplers_ARLEN),\n        .m_axi_arlock(s00_regslice_to_s00_couplers_ARLOCK),\n        .m_axi_arprot(s00_regslice_to_s00_couplers_ARPROT),\n        .m_axi_arqos(s00_regslice_to_s00_couplers_ARQOS),\n        .m_axi_arready(s00_regslice_to_s00_couplers_ARREADY),\n        .m_axi_arsize(s00_regslice_to_s00_couplers_ARSIZE),\n        .m_axi_arvalid(s00_regslice_to_s00_couplers_ARVALID),\n        .m_axi_awaddr(s00_regslice_to_s00_couplers_AWADDR),\n        .m_axi_awburst(s00_regslice_to_s00_couplers_AWBURST),\n        .m_axi_awcache(s00_regslice_to_s00_couplers_AWCACHE),\n        .m_axi_awid(s00_regslice_to_s00_couplers_AWID),\n        .m_axi_awlen(s00_regslice_to_s00_couplers_AWLEN),\n        .m_axi_awlock(s00_regslice_to_s00_couplers_AWLOCK),\n        .m_axi_awprot(s00_regslice_to_s00_couplers_AWPROT),\n        .m_axi_awqos(s00_regslice_to_s00_couplers_AWQOS),\n        .m_axi_awready(s00_regslice_to_s00_couplers_AWREADY),\n        .m_axi_awsize(s00_regslice_to_s00_couplers_AWSIZE),\n        .m_axi_awvalid(s00_regslice_to_s00_couplers_AWVALID),\n        .m_axi_bid(s00_regslice_to_s00_couplers_BID[5:0]),\n        .m_axi_bready(s00_regslice_to_s00_couplers_BREADY),\n        .m_axi_bresp(s00_regslice_to_s00_couplers_BRESP),\n        .m_axi_bvalid(s00_regslice_to_s00_couplers_BVALID),\n        .m_axi_rdata(s00_regslice_to_s00_couplers_RDATA),\n        .m_axi_rid(s00_regslice_to_s00_couplers_RID[5:0]),\n        .m_axi_rlast(s00_regslice_to_s00_couplers_RLAST),\n        .m_axi_rready(s00_regslice_to_s00_couplers_RREADY),\n        .m_axi_rresp(s00_regslice_to_s00_couplers_RRESP),\n        .m_axi_rvalid(s00_regslice_to_s00_couplers_RVALID),\n        .m_axi_wdata(s00_regslice_to_s00_couplers_WDATA),\n        .m_axi_wlast(s00_regslice_to_s00_couplers_WLAST),\n        .m_axi_wready(s00_regslice_to_s00_couplers_WREADY),\n        .m_axi_wstrb(s00_regslice_to_s00_couplers_WSTRB),\n        .m_axi_wvalid(s00_regslice_to_s00_couplers_WVALID),\n        .s_axi_araddr(s00_couplers_to_s00_regslice_ARADDR),\n        .s_axi_arburst(s00_couplers_to_s00_regslice_ARBURST),\n        .s_axi_arcache(s00_couplers_to_s00_regslice_ARCACHE),\n        .s_axi_arid(s00_couplers_to_s00_regslice_ARID),\n        .s_axi_arlen(s00_couplers_to_s00_regslice_ARLEN),\n        .s_axi_arlock(s00_couplers_to_s00_regslice_ARLOCK),\n        .s_axi_arprot(s00_couplers_to_s00_regslice_ARPROT),\n        .s_axi_arqos(s00_couplers_to_s00_regslice_ARQOS),\n        .s_axi_arready(s00_couplers_to_s00_regslice_ARREADY),\n        .s_axi_arregion(s00_couplers_to_s00_regslice_ARREGION),\n        .s_axi_arsize(s00_couplers_to_s00_regslice_ARSIZE),\n        .s_axi_arvalid(s00_couplers_to_s00_regslice_ARVALID),\n        .s_axi_awaddr(s00_couplers_to_s00_regslice_AWADDR),\n        .s_axi_awburst(s00_couplers_to_s00_regslice_AWBURST),\n        .s_axi_awcache(s00_couplers_to_s00_regslice_AWCACHE),\n        .s_axi_awid(s00_couplers_to_s00_regslice_AWID),\n        .s_axi_awlen(s00_couplers_to_s00_regslice_AWLEN),\n        .s_axi_awlock(s00_couplers_to_s00_regslice_AWLOCK),\n        .s_axi_awprot(s00_couplers_to_s00_regslice_AWPROT),\n        .s_axi_awqos(s00_couplers_to_s00_regslice_AWQOS),\n        .s_axi_awready(s00_couplers_to_s00_regslice_AWREADY),\n        .s_axi_awregion(s00_couplers_to_s00_regslice_AWREGION),\n        .s_axi_awsize(s00_couplers_to_s00_regslice_AWSIZE),\n        .s_axi_awvalid(s00_couplers_to_s00_regslice_AWVALID),\n        .s_axi_bid(s00_couplers_to_s00_regslice_BID),\n        .s_axi_bready(s00_couplers_to_s00_regslice_BREADY),\n        .s_axi_bresp(s00_couplers_to_s00_regslice_BRESP),\n        .s_axi_bvalid(s00_couplers_to_s00_regslice_BVALID),\n        .s_axi_rdata(s00_couplers_to_s00_regslice_RDATA),\n        .s_axi_rid(s00_couplers_to_s00_regslice_RID),\n        .s_axi_rlast(s00_couplers_to_s00_regslice_RLAST),\n        .s_axi_rready(s00_couplers_to_s00_regslice_RREADY),\n        .s_axi_rresp(s00_couplers_to_s00_regslice_RRESP),\n        .s_axi_rvalid(s00_couplers_to_s00_regslice_RVALID),\n        .s_axi_wdata(s00_couplers_to_s00_regslice_WDATA),\n        .s_axi_wlast(s00_couplers_to_s00_regslice_WLAST),\n        .s_axi_wready(s00_couplers_to_s00_regslice_WREADY),\n        .s_axi_wstrb(s00_couplers_to_s00_regslice_WSTRB),\n        .s_axi_wvalid(s00_couplers_to_s00_regslice_WVALID));\nendmodule\n\nmodule s01_couplers_imp_GSTXQ8\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [5:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [5:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [5:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [5:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [5:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [5:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire S_ACLK_1;\n  wire S_ARESETN_1;\n  wire [63:0]s01_couplers_to_s01_regslice_ARADDR;\n  wire [1:0]s01_couplers_to_s01_regslice_ARBURST;\n  wire [3:0]s01_couplers_to_s01_regslice_ARCACHE;\n  wire [5:0]s01_couplers_to_s01_regslice_ARID;\n  wire [7:0]s01_couplers_to_s01_regslice_ARLEN;\n  wire [0:0]s01_couplers_to_s01_regslice_ARLOCK;\n  wire [2:0]s01_couplers_to_s01_regslice_ARPROT;\n  wire [3:0]s01_couplers_to_s01_regslice_ARQOS;\n  wire s01_couplers_to_s01_regslice_ARREADY;\n  wire [3:0]s01_couplers_to_s01_regslice_ARREGION;\n  wire [2:0]s01_couplers_to_s01_regslice_ARSIZE;\n  wire s01_couplers_to_s01_regslice_ARVALID;\n  wire [63:0]s01_couplers_to_s01_regslice_AWADDR;\n  wire [1:0]s01_couplers_to_s01_regslice_AWBURST;\n  wire [3:0]s01_couplers_to_s01_regslice_AWCACHE;\n  wire [5:0]s01_couplers_to_s01_regslice_AWID;\n  wire [7:0]s01_couplers_to_s01_regslice_AWLEN;\n  wire [0:0]s01_couplers_to_s01_regslice_AWLOCK;\n  wire [2:0]s01_couplers_to_s01_regslice_AWPROT;\n  wire [3:0]s01_couplers_to_s01_regslice_AWQOS;\n  wire s01_couplers_to_s01_regslice_AWREADY;\n  wire [3:0]s01_couplers_to_s01_regslice_AWREGION;\n  wire [2:0]s01_couplers_to_s01_regslice_AWSIZE;\n  wire s01_couplers_to_s01_regslice_AWVALID;\n  wire [5:0]s01_couplers_to_s01_regslice_BID;\n  wire s01_couplers_to_s01_regslice_BREADY;\n  wire [1:0]s01_couplers_to_s01_regslice_BRESP;\n  wire s01_couplers_to_s01_regslice_BVALID;\n  wire [511:0]s01_couplers_to_s01_regslice_RDATA;\n  wire [5:0]s01_couplers_to_s01_regslice_RID;\n  wire s01_couplers_to_s01_regslice_RLAST;\n  wire s01_couplers_to_s01_regslice_RREADY;\n  wire [1:0]s01_couplers_to_s01_regslice_RRESP;\n  wire s01_couplers_to_s01_regslice_RVALID;\n  wire [511:0]s01_couplers_to_s01_regslice_WDATA;\n  wire s01_couplers_to_s01_regslice_WLAST;\n  wire s01_couplers_to_s01_regslice_WREADY;\n  wire [63:0]s01_couplers_to_s01_regslice_WSTRB;\n  wire s01_couplers_to_s01_regslice_WVALID;\n  wire [63:0]s01_regslice_to_s01_couplers_ARADDR;\n  wire [1:0]s01_regslice_to_s01_couplers_ARBURST;\n  wire [3:0]s01_regslice_to_s01_couplers_ARCACHE;\n  wire [5:0]s01_regslice_to_s01_couplers_ARID;\n  wire [7:0]s01_regslice_to_s01_couplers_ARLEN;\n  wire [0:0]s01_regslice_to_s01_couplers_ARLOCK;\n  wire [2:0]s01_regslice_to_s01_couplers_ARPROT;\n  wire [3:0]s01_regslice_to_s01_couplers_ARQOS;\n  wire s01_regslice_to_s01_couplers_ARREADY;\n  wire [2:0]s01_regslice_to_s01_couplers_ARSIZE;\n  wire s01_regslice_to_s01_couplers_ARVALID;\n  wire [63:0]s01_regslice_to_s01_couplers_AWADDR;\n  wire [1:0]s01_regslice_to_s01_couplers_AWBURST;\n  wire [3:0]s01_regslice_to_s01_couplers_AWCACHE;\n  wire [5:0]s01_regslice_to_s01_couplers_AWID;\n  wire [7:0]s01_regslice_to_s01_couplers_AWLEN;\n  wire [0:0]s01_regslice_to_s01_couplers_AWLOCK;\n  wire [2:0]s01_regslice_to_s01_couplers_AWPROT;\n  wire [3:0]s01_regslice_to_s01_couplers_AWQOS;\n  wire s01_regslice_to_s01_couplers_AWREADY;\n  wire [2:0]s01_regslice_to_s01_couplers_AWSIZE;\n  wire s01_regslice_to_s01_couplers_AWVALID;\n  wire [6:0]s01_regslice_to_s01_couplers_BID;\n  wire s01_regslice_to_s01_couplers_BREADY;\n  wire [1:0]s01_regslice_to_s01_couplers_BRESP;\n  wire s01_regslice_to_s01_couplers_BVALID;\n  wire [511:0]s01_regslice_to_s01_couplers_RDATA;\n  wire [6:0]s01_regslice_to_s01_couplers_RID;\n  wire s01_regslice_to_s01_couplers_RLAST;\n  wire s01_regslice_to_s01_couplers_RREADY;\n  wire [1:0]s01_regslice_to_s01_couplers_RRESP;\n  wire s01_regslice_to_s01_couplers_RVALID;\n  wire [511:0]s01_regslice_to_s01_couplers_WDATA;\n  wire s01_regslice_to_s01_couplers_WLAST;\n  wire s01_regslice_to_s01_couplers_WREADY;\n  wire [63:0]s01_regslice_to_s01_couplers_WSTRB;\n  wire s01_regslice_to_s01_couplers_WVALID;\n\n  assign M_AXI_araddr[63:0] = s01_regslice_to_s01_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = s01_regslice_to_s01_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = s01_regslice_to_s01_couplers_ARCACHE;\n  assign M_AXI_arid[5:0] = s01_regslice_to_s01_couplers_ARID;\n  assign M_AXI_arlen[7:0] = s01_regslice_to_s01_couplers_ARLEN;\n  assign M_AXI_arlock[0] = s01_regslice_to_s01_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = s01_regslice_to_s01_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = s01_regslice_to_s01_couplers_ARQOS;\n  assign M_AXI_arsize[2:0] = s01_regslice_to_s01_couplers_ARSIZE;\n  assign M_AXI_arvalid = s01_regslice_to_s01_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = s01_regslice_to_s01_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = s01_regslice_to_s01_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = s01_regslice_to_s01_couplers_AWCACHE;\n  assign M_AXI_awid[5:0] = s01_regslice_to_s01_couplers_AWID;\n  assign M_AXI_awlen[7:0] = s01_regslice_to_s01_couplers_AWLEN;\n  assign M_AXI_awlock[0] = s01_regslice_to_s01_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = s01_regslice_to_s01_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = s01_regslice_to_s01_couplers_AWQOS;\n  assign M_AXI_awsize[2:0] = s01_regslice_to_s01_couplers_AWSIZE;\n  assign M_AXI_awvalid = s01_regslice_to_s01_couplers_AWVALID;\n  assign M_AXI_bready = s01_regslice_to_s01_couplers_BREADY;\n  assign M_AXI_rready = s01_regslice_to_s01_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = s01_regslice_to_s01_couplers_WDATA;\n  assign M_AXI_wlast = s01_regslice_to_s01_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = s01_regslice_to_s01_couplers_WSTRB;\n  assign M_AXI_wvalid = s01_regslice_to_s01_couplers_WVALID;\n  assign S_ACLK_1 = S_ACLK;\n  assign S_ARESETN_1 = S_ARESETN;\n  assign S_AXI_arready = s01_couplers_to_s01_regslice_ARREADY;\n  assign S_AXI_awready = s01_couplers_to_s01_regslice_AWREADY;\n  assign S_AXI_bid[5:0] = s01_couplers_to_s01_regslice_BID;\n  assign S_AXI_bresp[1:0] = s01_couplers_to_s01_regslice_BRESP;\n  assign S_AXI_bvalid = s01_couplers_to_s01_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = s01_couplers_to_s01_regslice_RDATA;\n  assign S_AXI_rid[5:0] = s01_couplers_to_s01_regslice_RID;\n  assign S_AXI_rlast = s01_couplers_to_s01_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = s01_couplers_to_s01_regslice_RRESP;\n  assign S_AXI_rvalid = s01_couplers_to_s01_regslice_RVALID;\n  assign S_AXI_wready = s01_couplers_to_s01_regslice_WREADY;\n  assign s01_couplers_to_s01_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign s01_couplers_to_s01_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign s01_couplers_to_s01_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign s01_couplers_to_s01_regslice_ARID = S_AXI_arid[5:0];\n  assign s01_couplers_to_s01_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign s01_couplers_to_s01_regslice_ARLOCK = S_AXI_arlock[0];\n  assign s01_couplers_to_s01_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign s01_couplers_to_s01_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign s01_couplers_to_s01_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign s01_couplers_to_s01_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign s01_couplers_to_s01_regslice_ARVALID = S_AXI_arvalid;\n  assign s01_couplers_to_s01_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign s01_couplers_to_s01_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign s01_couplers_to_s01_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign s01_couplers_to_s01_regslice_AWID = S_AXI_awid[5:0];\n  assign s01_couplers_to_s01_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign s01_couplers_to_s01_regslice_AWLOCK = S_AXI_awlock[0];\n  assign s01_couplers_to_s01_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign s01_couplers_to_s01_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign s01_couplers_to_s01_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign s01_couplers_to_s01_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign s01_couplers_to_s01_regslice_AWVALID = S_AXI_awvalid;\n  assign s01_couplers_to_s01_regslice_BREADY = S_AXI_bready;\n  assign s01_couplers_to_s01_regslice_RREADY = S_AXI_rready;\n  assign s01_couplers_to_s01_regslice_WDATA = S_AXI_wdata[511:0];\n  assign s01_couplers_to_s01_regslice_WLAST = S_AXI_wlast;\n  assign s01_couplers_to_s01_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign s01_couplers_to_s01_regslice_WVALID = S_AXI_wvalid;\n  assign s01_regslice_to_s01_couplers_ARREADY = M_AXI_arready;\n  assign s01_regslice_to_s01_couplers_AWREADY = M_AXI_awready;\n  assign s01_regslice_to_s01_couplers_BID = M_AXI_bid[6:0];\n  assign s01_regslice_to_s01_couplers_BRESP = M_AXI_bresp[1:0];\n  assign s01_regslice_to_s01_couplers_BVALID = M_AXI_bvalid;\n  assign s01_regslice_to_s01_couplers_RDATA = M_AXI_rdata[511:0];\n  assign s01_regslice_to_s01_couplers_RID = M_AXI_rid[6:0];\n  assign s01_regslice_to_s01_couplers_RLAST = M_AXI_rlast;\n  assign s01_regslice_to_s01_couplers_RRESP = M_AXI_rresp[1:0];\n  assign s01_regslice_to_s01_couplers_RVALID = M_AXI_rvalid;\n  assign s01_regslice_to_s01_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_s01_regslice_0 s01_regslice\n       (.aclk(S_ACLK_1),\n        .aresetn(S_ARESETN_1),\n        .m_axi_araddr(s01_regslice_to_s01_couplers_ARADDR),\n        .m_axi_arburst(s01_regslice_to_s01_couplers_ARBURST),\n        .m_axi_arcache(s01_regslice_to_s01_couplers_ARCACHE),\n        .m_axi_arid(s01_regslice_to_s01_couplers_ARID),\n        .m_axi_arlen(s01_regslice_to_s01_couplers_ARLEN),\n        .m_axi_arlock(s01_regslice_to_s01_couplers_ARLOCK),\n        .m_axi_arprot(s01_regslice_to_s01_couplers_ARPROT),\n        .m_axi_arqos(s01_regslice_to_s01_couplers_ARQOS),\n        .m_axi_arready(s01_regslice_to_s01_couplers_ARREADY),\n        .m_axi_arsize(s01_regslice_to_s01_couplers_ARSIZE),\n        .m_axi_arvalid(s01_regslice_to_s01_couplers_ARVALID),\n        .m_axi_awaddr(s01_regslice_to_s01_couplers_AWADDR),\n        .m_axi_awburst(s01_regslice_to_s01_couplers_AWBURST),\n        .m_axi_awcache(s01_regslice_to_s01_couplers_AWCACHE),\n        .m_axi_awid(s01_regslice_to_s01_couplers_AWID),\n        .m_axi_awlen(s01_regslice_to_s01_couplers_AWLEN),\n        .m_axi_awlock(s01_regslice_to_s01_couplers_AWLOCK),\n        .m_axi_awprot(s01_regslice_to_s01_couplers_AWPROT),\n        .m_axi_awqos(s01_regslice_to_s01_couplers_AWQOS),\n        .m_axi_awready(s01_regslice_to_s01_couplers_AWREADY),\n        .m_axi_awsize(s01_regslice_to_s01_couplers_AWSIZE),\n        .m_axi_awvalid(s01_regslice_to_s01_couplers_AWVALID),\n        .m_axi_bid(s01_regslice_to_s01_couplers_BID[5:0]),\n        .m_axi_bready(s01_regslice_to_s01_couplers_BREADY),\n        .m_axi_bresp(s01_regslice_to_s01_couplers_BRESP),\n        .m_axi_bvalid(s01_regslice_to_s01_couplers_BVALID),\n        .m_axi_rdata(s01_regslice_to_s01_couplers_RDATA),\n        .m_axi_rid(s01_regslice_to_s01_couplers_RID[5:0]),\n        .m_axi_rlast(s01_regslice_to_s01_couplers_RLAST),\n        .m_axi_rready(s01_regslice_to_s01_couplers_RREADY),\n        .m_axi_rresp(s01_regslice_to_s01_couplers_RRESP),\n        .m_axi_rvalid(s01_regslice_to_s01_couplers_RVALID),\n        .m_axi_wdata(s01_regslice_to_s01_couplers_WDATA),\n        .m_axi_wlast(s01_regslice_to_s01_couplers_WLAST),\n        .m_axi_wready(s01_regslice_to_s01_couplers_WREADY),\n        .m_axi_wstrb(s01_regslice_to_s01_couplers_WSTRB),\n        .m_axi_wvalid(s01_regslice_to_s01_couplers_WVALID),\n        .s_axi_araddr(s01_couplers_to_s01_regslice_ARADDR),\n        .s_axi_arburst(s01_couplers_to_s01_regslice_ARBURST),\n        .s_axi_arcache(s01_couplers_to_s01_regslice_ARCACHE),\n        .s_axi_arid(s01_couplers_to_s01_regslice_ARID),\n        .s_axi_arlen(s01_couplers_to_s01_regslice_ARLEN),\n        .s_axi_arlock(s01_couplers_to_s01_regslice_ARLOCK),\n        .s_axi_arprot(s01_couplers_to_s01_regslice_ARPROT),\n        .s_axi_arqos(s01_couplers_to_s01_regslice_ARQOS),\n        .s_axi_arready(s01_couplers_to_s01_regslice_ARREADY),\n        .s_axi_arregion(s01_couplers_to_s01_regslice_ARREGION),\n        .s_axi_arsize(s01_couplers_to_s01_regslice_ARSIZE),\n        .s_axi_arvalid(s01_couplers_to_s01_regslice_ARVALID),\n        .s_axi_awaddr(s01_couplers_to_s01_regslice_AWADDR),\n        .s_axi_awburst(s01_couplers_to_s01_regslice_AWBURST),\n        .s_axi_awcache(s01_couplers_to_s01_regslice_AWCACHE),\n        .s_axi_awid(s01_couplers_to_s01_regslice_AWID),\n        .s_axi_awlen(s01_couplers_to_s01_regslice_AWLEN),\n        .s_axi_awlock(s01_couplers_to_s01_regslice_AWLOCK),\n        .s_axi_awprot(s01_couplers_to_s01_regslice_AWPROT),\n        .s_axi_awqos(s01_couplers_to_s01_regslice_AWQOS),\n        .s_axi_awready(s01_couplers_to_s01_regslice_AWREADY),\n        .s_axi_awregion(s01_couplers_to_s01_regslice_AWREGION),\n        .s_axi_awsize(s01_couplers_to_s01_regslice_AWSIZE),\n        .s_axi_awvalid(s01_couplers_to_s01_regslice_AWVALID),\n        .s_axi_bid(s01_couplers_to_s01_regslice_BID),\n        .s_axi_bready(s01_couplers_to_s01_regslice_BREADY),\n        .s_axi_bresp(s01_couplers_to_s01_regslice_BRESP),\n        .s_axi_bvalid(s01_couplers_to_s01_regslice_BVALID),\n        .s_axi_rdata(s01_couplers_to_s01_regslice_RDATA),\n        .s_axi_rid(s01_couplers_to_s01_regslice_RID),\n        .s_axi_rlast(s01_couplers_to_s01_regslice_RLAST),\n        .s_axi_rready(s01_couplers_to_s01_regslice_RREADY),\n        .s_axi_rresp(s01_couplers_to_s01_regslice_RRESP),\n        .s_axi_rvalid(s01_couplers_to_s01_regslice_RVALID),\n        .s_axi_wdata(s01_couplers_to_s01_regslice_WDATA),\n        .s_axi_wlast(s01_couplers_to_s01_regslice_WLAST),\n        .s_axi_wready(s01_couplers_to_s01_regslice_WREADY),\n        .s_axi_wstrb(s01_couplers_to_s01_regslice_WSTRB),\n        .s_axi_wvalid(s01_couplers_to_s01_regslice_WVALID));\nendmodule\n", "num_lines": 5426}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sync_clock_converter\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axic_sync_clock_converter # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_FAMILY     = \"virtex6\",\n  parameter integer C_PAYLOAD_WIDTH = 32,\n  parameter integer C_S_ACLK_RATIO = 1,\n  parameter integer C_M_ACLK_RATIO = 1 ,\n  parameter integer C_MODE = 0  // 0 = light-weight (1-deep); 1 = fully-pipelined (2-deep)\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input wire                    SAMPLE_CYCLE_EARLY,\n  input wire                    SAMPLE_CYCLE,\n  // Slave side\n  input  wire                        S_ACLK,\n  input  wire                        S_ARESETN,\n  input  wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD,\n  input  wire                        S_VALID,\n  output wire                        S_READY,\n\n  // Master side\n  input  wire                        M_ACLK,\n  input  wire                        M_ARESETN,\n  output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD,\n  output wire                        M_VALID,\n  input  wire                        M_READY\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam [1:0] ZERO = 2'b10;\nlocalparam [1:0] ONE  = 2'b11;\nlocalparam [1:0] TWO  = 2'b01;\nlocalparam [1:0] INIT = 2'b00;\nlocalparam integer P_LIGHT_WT = 0;\nlocalparam integer P_FULLY_REG = 1;\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\ngenerate\n  if (C_S_ACLK_RATIO == C_M_ACLK_RATIO) begin : gen_passthru\n    assign M_PAYLOAD = S_PAYLOAD;\n    assign M_VALID   = S_VALID;\n    assign S_READY   = M_READY;      \n  end else begin : gen_sync_clock_converter\n    wire s_sample_cycle;\n    wire s_sample_cycle_early;\n    wire m_sample_cycle;\n    wire m_sample_cycle_early;\n\n    wire slow_aclk;\n    wire slow_areset;\n    wire s_areset_r;\n    wire m_areset_r;\n   \n    reg  s_tready_r = 1'b0; \n    wire s_tready_ns; \n    reg  m_tvalid_r = 1'b0; \n    wire m_tvalid_ns; \n    reg  [C_PAYLOAD_WIDTH-1:0] m_tpayload_r;\n    reg  [C_PAYLOAD_WIDTH-1:0] m_tstorage_r;\n    wire [C_PAYLOAD_WIDTH-1:0] m_tpayload_ns; \n    wire [C_PAYLOAD_WIDTH-1:0] m_tstorage_ns; \n    reg  m_tready_hold = 1'b0;\n    wire m_tready_sample;\n    wire load_tpayload;\n    wire load_tstorage;\n    wire load_tpayload_from_tstorage;\n    reg [1:0] state = INIT;\n    reg [1:0] next_state;\n    \n    reg s_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge S_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        s_aresetn_r <= 1'b0;\n      end else begin\n        s_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign s_areset_r = ~s_aresetn_r;\n\n    reg m_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge M_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        m_aresetn_r <= 1'b0;\n      end else begin\n        m_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign m_areset_r = ~m_aresetn_r;\n\n    if (C_S_ACLK_RATIO > C_M_ACLK_RATIO) begin : gen_slowclk_mi\n      assign slow_aclk = M_ACLK;\n    end else begin : gen_slowclk_si\n      assign slow_aclk = S_ACLK;\n    end\n  \n    assign slow_areset = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? m_areset_r : s_areset_r;\n    assign s_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE_EARLY : 1'b1;\n    assign s_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE : 1'b1;\n    assign m_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE_EARLY;\n    assign m_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE;\n\n    // Output flop for S_READY, value is encoded into state machine.\n    assign s_tready_ns = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? state[1] & (state != INIT) : next_state[1];\n\n    always @(posedge S_ACLK) begin \n      if (s_areset_r) begin\n        s_tready_r <= 1'b0;\n      end\n      else begin\n        s_tready_r <= s_sample_cycle_early ? s_tready_ns : 1'b0;\n      end\n    end\n\n    assign S_READY = s_tready_r;\n\n    // Output flop for M_VALID\n    assign m_tvalid_ns = next_state[0];\n\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tvalid_r <= 1'b0;\n      end\n      else begin\n        m_tvalid_r <= m_sample_cycle ? m_tvalid_ns : m_tvalid_r & ~M_READY;\n      end\n    end\n\n    assign M_VALID = m_tvalid_r;\n\n    // Hold register for M_READY when M_ACLK is fast.\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tready_hold <= 1'b0;\n      end\n      else begin\n        m_tready_hold <= m_sample_cycle ? 1'b0 : m_tready_sample;\n      end\n    end\n\n    assign m_tready_sample = (M_READY ) | m_tready_hold;\n    // Output/storage flops for PAYLOAD\n    assign m_tpayload_ns = ~load_tpayload ? m_tpayload_r :\n                           load_tpayload_from_tstorage ? m_tstorage_r : \n                           S_PAYLOAD;\n\n    assign m_tstorage_ns = C_MODE ? (load_tstorage ? S_PAYLOAD : m_tstorage_r) : 0;\n\n    always @(posedge slow_aclk) begin \n      m_tpayload_r <= m_tpayload_ns;\n      m_tstorage_r <= C_MODE ? m_tstorage_ns : 0;\n    end\n\n    assign M_PAYLOAD = m_tpayload_r;\n\n    // load logic\n    assign load_tstorage = C_MODE && (state != TWO);\n    assign load_tpayload = m_tready_sample || (state == ZERO);\n    assign load_tpayload_from_tstorage = C_MODE && (state == TWO) && m_tready_sample;\n    \n    // State machine\n    always @(posedge slow_aclk) begin \n      state <= next_state;\n    end\n\n    always @* begin \n      if (slow_areset) begin \n        next_state = INIT;\n      end else begin\n        case (state)\n          INIT: begin\n            next_state = ZERO;\n          end\n          // No transaction stored locally\n          ZERO: begin\n            if (S_VALID) begin\n              next_state = C_MODE ? ONE : TWO; // Push from empty\n            end\n            else begin\n              next_state = ZERO;\n            end\n          end\n\n          // One transaction stored locally\n          ONE: begin\n            if (C_MODE == 0) begin\n              next_state = TWO;  // State ONE is inaccessible when C_MODE=0\n            end \n            else if (m_tready_sample & ~S_VALID) begin \n              next_state = ZERO; // Read out one so move to ZERO\n            end\n            else if (~m_tready_sample & S_VALID) begin\n              next_state = TWO;  // Got another one so move to TWO\n            end\n            else begin\n              next_state = ONE;\n            end\n          end\n\n          // Storage registers full\n          TWO: begin \n            if (m_tready_sample) begin\n              next_state = C_MODE ? ONE : ZERO; // Pop from full\n            end\n            else begin\n              next_state = TWO;\n            end\n          end\n        endcase // case (state)\n      end\n    end\n  end // gen_sync_clock_converter\n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sample_cycle_ratio\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axic_sample_cycle_ratio # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_RATIO = 2 // Must be > 0\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    SLOW_ACLK,\n  input  wire                    FAST_ACLK,\n\n  output wire                    SAMPLE_CYCLE_EARLY,\n  output wire                    SAMPLE_CYCLE\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam P_DELAY = C_RATIO > 2 ? C_RATIO-1 : C_RATIO-1; \n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_aclk_div2 = 1'b0;\nreg                posedge_finder_first = 1'b0;\nreg                posedge_finder_second = 1'b0;\nwire               first_edge;\nwire               second_edge;\nwire               any_edge;\nreg  [P_DELAY-1:0] sample_cycle_d = {P_DELAY{1'b0}};\n(* shreg_extract = \"no\" *) reg                sample_cycle_r = 1'b0;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\ngenerate\n  if (C_RATIO == 1) begin : gen_always_sample\n    assign SAMPLE_CYCLE_EARLY = 1'b1;\n    assign SAMPLE_CYCLE = 1'b1;\n  end\n  else begin : gen_sample_cycle\n    genvar i;\n    always @(posedge SLOW_ACLK) begin \n      slow_aclk_div2 <= ~slow_aclk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_aclk_div2 onto faster clock\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_first <= slow_aclk_div2;\n    end\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_second <= ~slow_aclk_div2;\n    end\n\n    assign first_edge = slow_aclk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;\n    assign any_edge = first_edge | second_edge;\n   \n    // delay the posedge alignment by C_RATIO - 1 to set the sample cycle as\n    // the clock one cycle before the posedge.\n    for (i = P_DELAY-1; i > 0; i = i - 1) begin : gen_delay\n      always @(posedge FAST_ACLK) begin\n        if (i == P_DELAY-1) begin\n          sample_cycle_d[i-1] <= any_edge;\n        end else begin\n          sample_cycle_d[i-1] <= sample_cycle_d[i];\n        end\n      end\n    end\n\n    always @(posedge FAST_ACLK) begin \n      sample_cycle_r <= (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    end\n    assign SAMPLE_CYCLE_EARLY = (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    assign SAMPLE_CYCLE = sample_cycle_r;\n  end\nendgenerate\n\nendmodule // axisc_sample_cycle_ratio\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2010 - 2016 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and\n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Clock converter module\n//   Asynchronous clock converter when asynchronous M:N conversion\n//   Bypass when synchronous and ratio between S and M clock is 1:1\n//   Synchronous clock converter (S:M or M:S must be integer ratio)\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_clock_conv\n//     fifo_generator\n//     axic_sync_clock_converter\n//       axic_sample_cycle_ratio\n//\n// PROTECTED NAMES:\n//   Instance names \"asyncfifo_*\" are pattern-matched in core-level UCF.\n//   Signal names \"*_resync\" are pattern-matched in core-level UCF.\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_lite_async #(\n  parameter integer C_DEST_SYNC_FF = 3,\n  parameter integer C_SRC_SYNC_FF  = 3,\n  parameter integer C_WIDTH        = 1\n) (\n  input wire                s_aclk,\n  input wire                m_aclk,\n  input wire                s_aresetn,\n  input wire                m_aresetn,\n  input wire                s_valid,\n  output wire                s_ready,\n  input wire [C_WIDTH-1:0]  s_payld,\n  output wire                m_valid,\n  input wire                m_ready,\n  output wire [C_WIDTH-1:0] m_payld\n);\n\nreg [C_SRC_SYNC_FF:0] s_areset_dly = {C_SRC_SYNC_FF+1{1'b0}};\nreg [C_DEST_SYNC_FF:0] m_areset_dly = {C_DEST_SYNC_FF+1{1'b0}};\nreg                s_ready_i = 1'b0;\nreg                m_valid_i = 1'b0;\nreg   src_send = 1'b0;\nreg   dest_ack = 1'b0;\nwire  src_rcv;\nwire  dest_req;\n\nassign s_ready = s_ready_i;\nassign m_valid = m_valid_i;\n\nlocalparam SRC_IDLE           = 2'b00;\nlocalparam SRC_DRV_SEND       = 2'b01;\nlocalparam SRC_WAIT_RCV_DONE  = 2'b10;\nreg [1:0] src_state = SRC_IDLE;\n\nalways @(posedge s_aclk) begin\n  s_areset_dly <= {C_SRC_SYNC_FF+1{~s_aresetn}} | (s_areset_dly<<1);\n  if (s_areset_dly[C_SRC_SYNC_FF]) begin\n    s_ready_i <= 1'b0;\n    src_send <= 1'b0;\n    src_state <= SRC_IDLE;\n  end else begin\n    case (src_state)\n      SRC_IDLE: begin\n        if (s_valid) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end\n      end\n      SRC_DRV_SEND: begin\n        if (src_rcv) begin\n          s_ready_i <= 1'b1;\n          src_send <= 1'b0;\n          src_state <= SRC_WAIT_RCV_DONE;\n        end\n      end\n      SRC_WAIT_RCV_DONE: begin\n        s_ready_i <= 1'b0;\n        if (s_valid & !src_rcv) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end else if (!src_rcv) begin\n          src_state <= SRC_IDLE;\n        end\n      end\n      default: begin\n        s_ready_i <= 1'b0;\n        src_send <= 1'b0;\n        src_state <= SRC_IDLE;\n      end\n    endcase\n  end\nend\n\nlocalparam DEST_IDLE           = 2'b00;\nlocalparam DEST_DRV_VALID      = 2'b01;\nlocalparam DEST_DRV_ACK        = 2'b10;\nreg [1:0] dest_state = DEST_IDLE;\n\nalways @(posedge m_aclk) begin\n  m_areset_dly <= {C_DEST_SYNC_FF+1{~m_aresetn}} | (m_areset_dly<<1);\n  if (m_areset_dly[C_DEST_SYNC_FF]) begin\n    m_valid_i <= 1'b0;\n    dest_ack <= 1'b0;\n    dest_state <= DEST_IDLE;\n  end else begin\n    case (dest_state)\n      DEST_IDLE: begin\n        if (dest_req) begin\n          dest_state <= DEST_DRV_VALID;\n          m_valid_i <= 1'b1;\n        end else begin\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b0;\n        end\n      end\n      DEST_DRV_VALID: begin\n        if (m_ready & m_valid_i) begin\n          dest_state <= DEST_DRV_ACK;\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b1;\n        end\n      end\n      DEST_DRV_ACK: begin\n        if (!dest_req) begin\n          dest_state <= DEST_IDLE;\n          dest_ack <= 1'b0;\n        end\n      end\n      default: begin\n        m_valid_i <= 1'b0;\n        dest_ack <= 1'b0;\n        dest_state <= DEST_IDLE;\n      end\n    endcase\n  end\nend\n\nxpm_cdc_handshake #(\n  .DEST_SYNC_FF   (C_DEST_SYNC_FF),\n  .SRC_SYNC_FF    (C_SRC_SYNC_FF),\n  .WIDTH          (C_WIDTH)\n) handshake (\n  .src_clk  (s_aclk),\n  .src_in   (s_payld),\n  .src_send (src_send),\n  .src_rcv  (src_rcv),\n  .dest_clk (m_aclk),\n  .dest_out (m_payld),\n  .dest_req (dest_req),\n  .dest_ack (dest_ack)\n);\n\nendmodule\n\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axi_clock_converter #\n  (parameter         C_FAMILY = \"virtex7\",\n   parameter integer C_AXI_ID_WIDTH = 5,                    // Width of all ID signals on SI and MI side.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ADDR_WIDTH = 32,                 // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and\n                                                            // m_axi_araddr.\n                                                            // Range: 32.\n   parameter integer C_AXI_DATA_WIDTH = 32,       // Width of WDATA and RDATA (either side).\n                                                            // Format: Bit32;\n                                                            // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.\n   parameter integer C_S_AXI_ACLK_RATIO = 1,     // Clock frequency ratio of SI w.r.t. MI.\n   parameter integer C_M_AXI_ACLK_RATIO = 1,     // (Slowest of all clock inputs should have ratio=1.)\n                                                            // S:M or M:S must be integer ratio.\n                                                            // Format: Bit32; Range: >='h00000001.\n   parameter integer C_AXI_IS_ACLK_ASYNC = 1,            // Indicates whether S and M clocks are asynchronous.\n                                                            // FUTURE FEATURE\n                                                            // Format: Bit1. Range = 1'b0.\n   parameter integer C_AXI_PROTOCOL = 0,         // Protocol of this SI/MI slot.\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS  = 1,      // 1 = Propagate all USER signals, 0 = Do not propagate.\n   parameter integer C_AXI_AWUSER_WIDTH = 1,                // Width of AWUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ARUSER_WIDTH = 1,                // Width of ARUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_WUSER_WIDTH = 1,                 // Width of WUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_RUSER_WIDTH = 1,                 // Width of RUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_BUSER_WIDTH = 1,                 // Width of BUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,              // Implement AXI write channels\n   parameter integer C_AXI_SUPPORTS_READ = 1,               // Implement AXI read channels\n   parameter integer C_SYNCHRONIZER_STAGE = 3\n  )\n\n  (\n   // Slave Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n   input  wire [4-1:0]                    s_axi_awcache,\n   input  wire [3-1:0]                    s_axi_awprot,\n   input  wire [4-1:0]                    s_axi_awregion,\n   input  wire [4-1:0]                    s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0]   s_axi_awuser,\n   input  wire                            s_axi_awvalid,\n   output wire                            s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n   input  wire                            s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]    s_axi_wuser,\n   input  wire                            s_axi_wvalid,\n   output wire                            s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_bid,\n   output wire [2-1:0]                    s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0]    s_axi_buser,\n   output wire                            s_axi_bvalid,\n   input  wire                            s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n   input  wire [3-1:0]                    s_axi_arsize,\n   input  wire [2-1:0]                    s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n   input  wire [4-1:0]                    s_axi_arcache,\n   input  wire [3-1:0]                    s_axi_arprot,\n   input  wire [4-1:0]                    s_axi_arregion,\n   input  wire [4-1:0]                    s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0]   s_axi_aruser,\n   input  wire                            s_axi_arvalid,\n   output wire                            s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n   output wire [2-1:0]                    s_axi_rresp,\n   output wire                            s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0]    s_axi_ruser,\n   output wire                            s_axi_rvalid,\n   input  wire                            s_axi_rready,\n\n   // Master Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aresetn,\n\n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n   output wire [3-1:0]                    m_axi_awsize,\n   output wire [2-1:0]                    m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n   output wire [4-1:0]                    m_axi_awcache,\n   output wire [3-1:0]                    m_axi_awprot,\n   output wire [4-1:0]                    m_axi_awregion,\n   output wire [4-1:0]                    m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0]   m_axi_awuser,\n   output wire                            m_axi_awvalid,\n   input  wire                            m_axi_awready,\n\n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0]   m_axi_wstrb,\n   output wire                            m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]    m_axi_wuser,\n   output wire                            m_axi_wvalid,\n   input  wire                            m_axi_wready,\n\n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_bid,\n   input  wire [2-1:0]                    m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0]    m_axi_buser,\n   input  wire                            m_axi_bvalid,\n   output wire                            m_axi_bready,\n\n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n   output wire [3-1:0]                    m_axi_arsize,\n   output wire [2-1:0]                    m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n   output wire [4-1:0]                    m_axi_arcache,\n   output wire [3-1:0]                    m_axi_arprot,\n   output wire [4-1:0]                    m_axi_arregion,\n   output wire [4-1:0]                    m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0]   m_axi_aruser,\n   output wire                            m_axi_arvalid,\n   input  wire                            m_axi_arready,\n\n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     m_axi_rdata,\n   input  wire [2-1:0]                    m_axi_rresp,\n   input  wire                            m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0]    m_axi_ruser,\n   input  wire                            m_axi_rvalid,\n   output wire                            m_axi_rready);\n\n  localparam integer P_AXI4 = 0;\n  localparam integer P_AXI3 = 1;\n  localparam integer P_AXILITE = 2;\n  localparam integer P_LIGHT_WT = 0;\n  localparam integer P_FULLY_REG = 1;\n  localparam integer P_LUTRAM_ASYNC = 12;\n\n  // Sample cycle ratio\n  localparam  P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);\n  localparam integer P_ROUNDING_OFFSET = P_SI_LT_MI ? (C_S_AXI_ACLK_RATIO/2) : (C_M_AXI_ACLK_RATIO/2);\n  localparam integer P_ACLK_RATIO = P_SI_LT_MI ?\n    ((C_M_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_S_AXI_ACLK_RATIO) :\n    ((C_S_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_M_AXI_ACLK_RATIO);\n\n  // Write Address Port bit positions\n  localparam integer C_AWUSER_RIGHT   = 0;\n  localparam integer C_AWUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_AWUSER_WIDTH : 0;\n  localparam integer C_AWQOS_RIGHT    = C_AWUSER_RIGHT + C_AWUSER_WIDTH;\n  localparam integer C_AWQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWREGION_RIGHT = C_AWQOS_RIGHT + C_AWQOS_WIDTH;\n  localparam integer C_AWREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_AWPROT_RIGHT   = C_AWREGION_RIGHT + C_AWREGION_WIDTH;\n  localparam integer C_AWPROT_WIDTH     = 3;\n  localparam integer C_AWCACHE_RIGHT  = C_AWPROT_RIGHT + C_AWPROT_WIDTH;\n  localparam integer C_AWCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWLOCK_RIGHT   = C_AWCACHE_RIGHT + C_AWCACHE_WIDTH;\n  localparam integer C_AWLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_AWBURST_RIGHT  = C_AWLOCK_RIGHT + C_AWLOCK_WIDTH;\n  localparam integer C_AWBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_AWSIZE_RIGHT   = C_AWBURST_RIGHT + C_AWBURST_WIDTH;\n  localparam integer C_AWSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_AWLEN_RIGHT    = C_AWSIZE_RIGHT + C_AWSIZE_WIDTH;\n  localparam integer C_AWLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_AWADDR_RIGHT   = C_AWLEN_RIGHT + C_AWLEN_WIDTH;\n  localparam integer C_AWADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_AWID_RIGHT     = C_AWADDR_RIGHT + C_AWADDR_WIDTH;\n  localparam integer C_AWID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AW_WIDTH        = C_AWID_RIGHT + C_AWID_WIDTH;\n  localparam integer C_FIFO_AW_WIDTH   = C_AWUSER_WIDTH+C_AWQOS_WIDTH+C_AWQOS_WIDTH+3+C_AWCACHE_WIDTH+C_AWLOCK_WIDTH+C_AWBURST_WIDTH+C_AWSIZE_WIDTH+C_AWLEN_WIDTH+C_AXI_ADDR_WIDTH+C_AWID_WIDTH;\n\n  // Write Data Port bit positions\n  localparam integer C_WUSER_RIGHT   = 0;\n  localparam integer C_WUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_WUSER_WIDTH : 0;\n  localparam integer C_WLAST_RIGHT   = C_WUSER_RIGHT + C_WUSER_WIDTH;\n  localparam integer C_WLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_WSTRB_RIGHT   = C_WLAST_RIGHT + C_WLAST_WIDTH;\n  localparam integer C_WSTRB_WIDTH     = C_AXI_DATA_WIDTH/8;\n  localparam integer C_WDATA_RIGHT   = C_WSTRB_RIGHT + C_WSTRB_WIDTH;\n  localparam integer C_WDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_WID_RIGHT     = C_WDATA_RIGHT + C_WDATA_WIDTH;\n  localparam integer C_WID_WIDTH       = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_W_WIDTH        = C_WID_RIGHT + C_WID_WIDTH;\n  localparam integer C_FIFO_W_WIDTH   = C_WUSER_WIDTH + C_WLAST_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_DATA_WIDTH + C_WID_WIDTH;\n\n  // Write Response Port bit positions\n  localparam integer C_BUSER_RIGHT   = 0;\n  localparam integer C_BUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_BUSER_WIDTH : 0;\n  localparam integer C_BRESP_RIGHT   = C_BUSER_RIGHT + C_BUSER_WIDTH;\n  localparam integer C_BRESP_WIDTH     = 2;\n  localparam integer C_BID_RIGHT     = C_BRESP_RIGHT + C_BRESP_WIDTH;\n  localparam integer C_BID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_B_WIDTH        = C_BID_RIGHT + C_BID_WIDTH;\n  localparam integer C_FIFO_B_WIDTH    = C_BUSER_WIDTH + 2 + C_BID_WIDTH;\n\n  // Read Address Port bit positions\n  localparam integer C_ARUSER_RIGHT   = 0;\n  localparam integer C_ARUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_ARUSER_WIDTH : 0;\n  localparam integer C_ARQOS_RIGHT    = C_ARUSER_RIGHT + C_ARUSER_WIDTH;\n  localparam integer C_ARQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARREGION_RIGHT = C_ARQOS_RIGHT + C_ARQOS_WIDTH;\n  localparam integer C_ARREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_ARPROT_RIGHT   = C_ARREGION_RIGHT + C_ARREGION_WIDTH;\n  localparam integer C_ARPROT_WIDTH     = 3;\n  localparam integer C_ARCACHE_RIGHT  = C_ARPROT_RIGHT + C_ARPROT_WIDTH;\n  localparam integer C_ARCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARLOCK_RIGHT   = C_ARCACHE_RIGHT + C_ARCACHE_WIDTH;\n  localparam integer C_ARLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_ARBURST_RIGHT  = C_ARLOCK_RIGHT + C_ARLOCK_WIDTH;\n  localparam integer C_ARBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_ARSIZE_RIGHT   = C_ARBURST_RIGHT + C_ARBURST_WIDTH;\n  localparam integer C_ARSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_ARLEN_RIGHT    = C_ARSIZE_RIGHT + C_ARSIZE_WIDTH;\n  localparam integer C_ARLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_ARADDR_RIGHT   = C_ARLEN_RIGHT + C_ARLEN_WIDTH;\n  localparam integer C_ARADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_ARID_RIGHT     = C_ARADDR_RIGHT + C_ARADDR_WIDTH;\n  localparam integer C_ARID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AR_WIDTH        = C_ARID_RIGHT + C_ARID_WIDTH;\n  localparam integer C_FIFO_AR_WIDTH   = C_ARUSER_WIDTH+C_ARQOS_WIDTH+C_ARQOS_WIDTH+3+C_ARCACHE_WIDTH+C_ARLOCK_WIDTH+C_ARBURST_WIDTH+C_ARSIZE_WIDTH+C_ARLEN_WIDTH+C_AXI_ADDR_WIDTH+C_ARID_WIDTH;\n\n  // Read Data Ports bit positions\n  localparam integer C_RUSER_RIGHT   = 0;\n  localparam integer C_RUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_RUSER_WIDTH : 0;\n  localparam integer C_RLAST_RIGHT   = C_RUSER_RIGHT + C_RUSER_WIDTH;\n  localparam integer C_RLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_RRESP_RIGHT   = C_RLAST_RIGHT + C_RLAST_WIDTH;\n  localparam integer C_RRESP_WIDTH     = 2;\n  localparam integer C_RDATA_RIGHT   = C_RRESP_RIGHT + C_RRESP_WIDTH;\n  localparam integer C_RDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_RID_RIGHT     = C_RDATA_RIGHT + C_RDATA_WIDTH;\n  localparam integer C_RID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_R_WIDTH        = C_RID_RIGHT + C_RID_WIDTH;\n  localparam integer C_FIFO_R_WIDTH   = C_RUSER_WIDTH + C_RLAST_WIDTH + 2 + C_AXI_DATA_WIDTH + C_RID_WIDTH;\n\n  generate\n    if ((C_AXI_IS_ACLK_ASYNC == 0) && (P_ACLK_RATIO == 1)) begin : gen_bypass\n      \n      // Write address port\n      assign m_axi_awid     = s_axi_awid;\n      assign m_axi_awaddr   = s_axi_awaddr;\n      assign m_axi_awlen    = s_axi_awlen;\n      assign m_axi_awsize   = s_axi_awsize;\n      assign m_axi_awburst  = s_axi_awburst;\n      assign m_axi_awlock   = s_axi_awlock;\n      assign m_axi_awcache  = s_axi_awcache;\n      assign m_axi_awprot   = s_axi_awprot;\n      assign m_axi_awregion = s_axi_awregion;\n      assign m_axi_awqos    = s_axi_awqos;\n      assign m_axi_awuser   = s_axi_awuser;\n      assign m_axi_awvalid  = s_axi_awvalid;\n      assign s_axi_awready  = m_axi_awready;\n\n      // Write Data Port\n      assign m_axi_wid      = s_axi_wid;\n      assign m_axi_wdata    = s_axi_wdata;\n      assign m_axi_wstrb    = s_axi_wstrb;\n      assign m_axi_wlast    = s_axi_wlast;\n      assign m_axi_wuser    = s_axi_wuser;\n      assign m_axi_wvalid   = s_axi_wvalid;\n      assign s_axi_wready   = m_axi_wready;\n\n      // Write Response Port\n      assign s_axi_bid      = m_axi_bid;\n      assign s_axi_bresp    = m_axi_bresp;\n      assign s_axi_buser    = m_axi_buser;\n      assign s_axi_bvalid   = m_axi_bvalid;\n      assign m_axi_bready   = s_axi_bready;\n\n      // Read Address Port\n      assign m_axi_arid     = s_axi_arid;\n      assign m_axi_araddr   = s_axi_araddr;\n      assign m_axi_arlen    = s_axi_arlen;\n      assign m_axi_arsize   = s_axi_arsize;\n      assign m_axi_arburst  = s_axi_arburst;\n      assign m_axi_arlock   = s_axi_arlock;\n      assign m_axi_arcache  = s_axi_arcache;\n      assign m_axi_arprot   = s_axi_arprot;\n      assign m_axi_arregion = s_axi_arregion;\n      assign m_axi_arqos    = s_axi_arqos;\n      assign m_axi_aruser   = s_axi_aruser;\n      assign m_axi_arvalid  = s_axi_arvalid;\n      assign s_axi_arready  = m_axi_arready;\n\n      // Read Data Port\n      assign s_axi_rid      = m_axi_rid;\n      assign s_axi_rdata    = m_axi_rdata;\n      assign s_axi_rresp    = m_axi_rresp;\n      assign s_axi_rlast    = m_axi_rlast;\n      assign s_axi_ruser    = m_axi_ruser;\n      assign s_axi_rvalid   = m_axi_rvalid;\n      assign m_axi_rready   = s_axi_rready;\n      \n    end else begin : gen_clock_conv\n      \n      wire fast_aclk;\n      wire slow_aclk;\n      wire sample_cycle;\n      wire sample_cycle_early;\n    \n      // Write Address Port FIFO data read and write\n      wire [C_AW_WIDTH-1:0] s_aw_mesg ;\n      wire [C_AW_WIDTH-1:0] m_aw_mesg ;\n    \n      // Write Data Port FIFO data read and write\n      wire [C_W_WIDTH-1:0] s_w_mesg;\n      wire [C_W_WIDTH-1:0] m_w_mesg;\n    \n      // Write Response Port FIFO data read and write\n      wire [C_B_WIDTH-1:0] s_b_mesg;\n      wire [C_B_WIDTH-1:0] m_b_mesg;\n    \n      // Read Address Port FIFO data read and write\n      wire [C_AR_WIDTH-1:0] s_ar_mesg;\n      wire [C_AR_WIDTH-1:0] m_ar_mesg;\n    \n      // Read Data Ports FIFO data read and write\n      wire [C_R_WIDTH-1:0] s_r_mesg;\n      wire [C_R_WIDTH-1:0] m_r_mesg;\n    \n      wire async_conv_reset_n;\n      assign async_conv_reset_n = ~(~s_axi_aresetn | ~m_axi_aresetn);\n      \n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_awlen           ;\n      wire [3-1:0]                       si_cc_awsize          ;\n      wire [2-1:0]                       si_cc_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_awlock          ;\n      wire [4-1:0]                       si_cc_awcache         ;\n      wire [3-1:0]                       si_cc_awprot          ;\n      wire [4-1:0]                       si_cc_awregion        ;\n      wire [4-1:0]                       si_cc_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]      si_cc_awuser          ;\n      wire                               si_cc_awvalid         ;\n      wire                               si_cc_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_wid            ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]      si_cc_wstrb           ;\n      wire                               si_cc_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]       si_cc_wuser           ;\n      wire                               si_cc_wvalid          ;\n      wire                               si_cc_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_bid             ;\n      wire [2-1:0]                       si_cc_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]       si_cc_buser           ;\n      wire                               si_cc_bvalid          ;\n      wire                               si_cc_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_arlen           ;\n      wire [3-1:0]                       si_cc_arsize          ;\n      wire [2-1:0]                       si_cc_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_arlock          ;\n      wire [4-1:0]                       si_cc_arcache         ;\n      wire [3-1:0]                       si_cc_arprot          ;\n      wire [4-1:0]                       si_cc_arregion        ;\n      wire [4-1:0]                       si_cc_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]      si_cc_aruser          ;\n      wire                               si_cc_arvalid         ;\n      wire                               si_cc_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_rdata           ;\n      wire [2-1:0]                       si_cc_rresp           ;\n      wire                               si_cc_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]       si_cc_ruser           ;\n      wire                               si_cc_rvalid          ;\n      wire                               si_cc_rready          ;\n      \n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_awlen           ;\n      wire [3-1:0]                      cc_mi_awsize          ;\n      wire [2-1:0]                      cc_mi_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_awlock          ;\n      wire [4-1:0]                      cc_mi_awcache         ;\n      wire [3-1:0]                      cc_mi_awprot          ;\n      wire [4-1:0]                      cc_mi_awregion        ;\n      wire [4-1:0]                      cc_mi_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]     cc_mi_awuser          ;\n      wire                              cc_mi_awvalid         ;\n      wire                              cc_mi_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_wid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]     cc_mi_wstrb           ;\n      wire                              cc_mi_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]      cc_mi_wuser           ;\n      wire                              cc_mi_wvalid          ;\n      wire                              cc_mi_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_bid             ;\n      wire [2-1:0]                      cc_mi_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]      cc_mi_buser           ;\n      wire                              cc_mi_bvalid          ;\n      wire                              cc_mi_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_arlen           ;\n      wire [3-1:0]                      cc_mi_arsize          ;\n      wire [2-1:0]                      cc_mi_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_arlock          ;\n      wire [4-1:0]                      cc_mi_arcache         ;\n      wire [3-1:0]                      cc_mi_arprot          ;\n      wire [4-1:0]                      cc_mi_arregion        ;\n      wire [4-1:0]                      cc_mi_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]     cc_mi_aruser          ;\n      wire                              cc_mi_arvalid         ;\n      wire                              cc_mi_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_rdata           ;\n      wire [2-1:0]                      cc_mi_rresp           ;\n      wire                              cc_mi_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]      cc_mi_ruser           ;\n      wire                              cc_mi_rvalid          ;\n      wire                              cc_mi_rready          ;\n      \n    // Tie-offs\n      assign si_cc_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awid : 0 ;\n      assign si_cc_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awaddr : 0 ;\n      assign si_cc_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_awlen : {4'b0000, s_axi_awlen[3:0]}) : 0 ;\n      assign si_cc_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize : 0 ;\n      assign si_cc_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst : 0 ;\n      assign si_cc_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_awlock : {1'b0, s_axi_awlock[0]}) : 0 ;\n      assign si_cc_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache : 0 ;\n      assign si_cc_awprot    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awprot : 0 ;\n      assign si_cc_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos : 0 ;\n      assign si_cc_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion : 0 ;\n      assign si_cc_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser : 0 ;\n      assign si_cc_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awvalid : 0 ;\n      assign si_cc_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? s_axi_wid : 0 ;\n      assign si_cc_wdata     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wdata : 0 ;\n      assign si_cc_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wstrb : 0 ;\n      assign si_cc_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast : 1'b0 ;\n      assign si_cc_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser : 0 ;\n      assign si_cc_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wvalid : 0 ;\n      assign si_cc_bready    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_bready : 0 ;\n      assign si_cc_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arid : 0 ;\n      assign si_cc_araddr    = (C_AXI_SUPPORTS_READ ) ? s_axi_araddr : 0 ;\n      assign si_cc_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_arlen : {4'b0000, s_axi_arlen[3:0]}) : 0 ;\n      assign si_cc_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize : 0 ;\n      assign si_cc_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst : 0 ;\n      assign si_cc_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_arlock : {1'b0, s_axi_arlock[0]}) : 0 ;\n      assign si_cc_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache : 0 ;\n      assign si_cc_arprot    = (C_AXI_SUPPORTS_READ ) ? s_axi_arprot : 0 ;\n      assign si_cc_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos : 0 ;\n      assign si_cc_arregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion : 0 ;\n      assign si_cc_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser : 0 ;\n      assign si_cc_arvalid   = (C_AXI_SUPPORTS_READ ) ? s_axi_arvalid : 0 ;\n      assign si_cc_rready    = (C_AXI_SUPPORTS_READ ) ? s_axi_rready : 0 ;                                       \n                                                                                               \n      assign s_axi_awready   = (C_AXI_SUPPORTS_WRITE ) ? si_cc_awready : 0 ;\n      assign s_axi_wready    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_wready : 0 ;\n      assign s_axi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_bid : 0 ;\n      assign s_axi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bresp : 0 ;\n      assign s_axi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_buser : 0 ;\n      assign s_axi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bvalid : 0 ;\n      assign s_axi_arready   = (C_AXI_SUPPORTS_READ ) ? si_cc_arready : 0 ;\n      assign s_axi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rid : 0 ;\n      assign s_axi_rdata     = (C_AXI_SUPPORTS_READ ) ? si_cc_rdata : 0 ;\n      assign s_axi_rresp     = (C_AXI_SUPPORTS_READ ) ? si_cc_rresp : 0 ;\n      assign s_axi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rlast : 0 ;\n      assign s_axi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_ruser : 0 ;\n      assign s_axi_rvalid    = (C_AXI_SUPPORTS_READ ) ? si_cc_rvalid : 0 ;\n\n      assign m_axi_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awid : 0 ;\n      assign m_axi_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awaddr : 0 ;\n      assign m_axi_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_awlen : cc_mi_awlen[3:0]) : 0 ;\n      assign m_axi_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awsize : 0 ;\n      assign m_axi_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awburst : 0 ;\n      assign m_axi_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_awlock : cc_mi_awlock[0]) : 0 ;\n      assign m_axi_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awcache : 0 ;\n      assign m_axi_awprot    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awprot : 0 ;\n      assign m_axi_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_awregion : 0 ;\n      assign m_axi_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awqos : 0 ;\n      assign m_axi_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_awuser : 0 ;\n      assign m_axi_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awvalid : 0 ;\n      assign m_axi_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? cc_mi_wid : 0 ;\n      assign m_axi_wdata     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wdata : 0 ;\n      assign m_axi_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wstrb : 0 ;\n      assign m_axi_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_wlast : 0 ;\n      assign m_axi_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_wuser : 0 ;\n      assign m_axi_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wvalid : 0 ;\n      assign m_axi_bready    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_bready : 0 ;\n      assign m_axi_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arid : 0 ;\n      assign m_axi_araddr    = (C_AXI_SUPPORTS_READ ) ? cc_mi_araddr : 0 ;\n      assign m_axi_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_arlen : cc_mi_arlen[3:0]) : 0 ;\n      assign m_axi_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arsize : 0 ;\n      assign m_axi_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arburst : 0 ;\n      assign m_axi_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_arlock : cc_mi_arlock[0]) : 0 ;\n      assign m_axi_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arcache : 0 ;\n      assign m_axi_arprot    = (C_AXI_SUPPORTS_READ ) ? cc_mi_arprot : 0 ;\n      assign m_axi_arregion  = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_arregion : 0 ;\n      assign m_axi_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arqos : 0 ;\n      assign m_axi_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_aruser : 0 ;\n      assign m_axi_arvalid   = (C_AXI_SUPPORTS_READ ) ? cc_mi_arvalid : 0 ;\n      assign m_axi_rready    = (C_AXI_SUPPORTS_READ ) ? cc_mi_rready : 0 ;\n                                                                                                                                                                                                                                                                                        \n      assign cc_mi_awready   = (C_AXI_SUPPORTS_WRITE ) ? m_axi_awready : 0 ;\n      assign cc_mi_wready    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_wready : 0 ;\n      assign cc_mi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid : 0 ;\n      assign cc_mi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bresp : 0 ;\n      assign cc_mi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser : 0 ;\n      assign cc_mi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bvalid : 0 ;\n      assign cc_mi_arready   = (C_AXI_SUPPORTS_READ ) ? m_axi_arready : 0 ;\n      assign cc_mi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid : 0 ;\n      assign cc_mi_rdata     = (C_AXI_SUPPORTS_READ ) ? m_axi_rdata : 0 ;\n      assign cc_mi_rresp     = (C_AXI_SUPPORTS_READ ) ? m_axi_rresp : 0 ;\n      assign cc_mi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast : 1'b0 ;\n      assign cc_mi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser : 0 ;\n      assign cc_mi_rvalid    = (C_AXI_SUPPORTS_READ ) ? m_axi_rvalid : 0 ;\n      \n      if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL!=P_AXILITE)) begin : gen_async_conv\n        \n        fifo_generator_v13_2_5 #(\n          .C_EN_SAFETY_CKT(0),\n          .C_SELECT_XPM(0),\n          .C_INTERFACE_TYPE(2),\n          .C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ? 3 : 2),\n          .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n          .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n          .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n          .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n          .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n          .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),\n          .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n          .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n          .C_HAS_AXI_ID((C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0),\n          .C_AXI_LEN_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 8 : 4),\n          .C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 1 : 2),\n          .C_HAS_AXI_ARUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_AWUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_BUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_RUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_WUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_DIN_WIDTH_RACH(C_FIFO_AR_WIDTH),\n          .C_DIN_WIDTH_RDCH(C_FIFO_R_WIDTH),\n          .C_DIN_WIDTH_WACH(C_FIFO_AW_WIDTH),\n          .C_DIN_WIDTH_WDCH(C_FIFO_W_WIDTH),\n          .C_DIN_WIDTH_WRCH(C_FIFO_B_WIDTH),\n          .C_HAS_AXI_RD_CHANNEL(C_AXI_SUPPORTS_READ),\n          .C_HAS_AXI_WR_CHANNEL(C_AXI_SUPPORTS_WRITE),\n          .C_RACH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_RDCH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_WACH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WDCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WRCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),\n          .C_COMMON_CLOCK(0),\n          .C_COUNT_TYPE(0),\n          .C_DATA_COUNT_WIDTH(10),\n          .C_DEFAULT_VALUE(\"BlankString\"),\n          .C_DIN_WIDTH(18),\n          .C_DOUT_RST_VAL(\"0\"),\n          .C_DOUT_WIDTH(18),\n          .C_ENABLE_RLOCS(0),\n          .C_FAMILY(C_FAMILY),\n          .C_FULL_FLAGS_RST_VAL(1),\n          .C_HAS_ALMOST_EMPTY(0),\n          .C_HAS_ALMOST_FULL(0),\n          .C_HAS_BACKUP(0),\n          .C_HAS_DATA_COUNT(0),\n          .C_HAS_INT_CLK(0),\n          .C_HAS_MEMINIT_FILE(0),\n          .C_HAS_OVERFLOW(0),\n          .C_HAS_RD_DATA_COUNT(0),\n          .C_HAS_RD_RST(0),\n          .C_HAS_RST(1),\n          .C_HAS_SRST(0),\n          .C_HAS_UNDERFLOW(0),\n          .C_HAS_VALID(0),\n          .C_HAS_WR_ACK(0),\n          .C_HAS_WR_DATA_COUNT(0),\n          .C_HAS_WR_RST(0),\n          .C_IMPLEMENTATION_TYPE(0),\n          .C_INIT_WR_PNTR_VAL(0),\n          .C_MEMORY_TYPE(1),\n          .C_MIF_FILE_NAME(\"BlankString\"),\n          .C_OPTIMIZATION_MODE(0),\n          .C_OVERFLOW_LOW(0),\n          .C_PRELOAD_LATENCY(1),\n          .C_PRELOAD_REGS(0),\n          .C_PRIM_FIFO_TYPE(\"4kx4\"),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),\n          .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),\n          .C_PROG_EMPTY_TYPE(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL(1022),\n          .C_PROG_FULL_THRESH_NEGATE_VAL(1021),\n          .C_PROG_FULL_TYPE(0),\n          .C_RD_DATA_COUNT_WIDTH(10),\n          .C_RD_DEPTH(1024),\n          .C_RD_FREQ(1),\n          .C_RD_PNTR_WIDTH(10),\n          .C_UNDERFLOW_LOW(0),\n          .C_USE_DOUT_RST(1),\n          .C_USE_ECC(0),\n          .C_USE_EMBEDDED_REG(0),\n          .C_USE_FIFO16_FLAGS(0),\n          .C_USE_FWFT_DATA_COUNT(0),\n          .C_VALID_LOW(0),\n          .C_WR_ACK_LOW(0),\n          .C_WR_DATA_COUNT_WIDTH(10),\n          .C_WR_DEPTH(1024),\n          .C_WR_FREQ(1),\n          .C_WR_PNTR_WIDTH(10),\n          .C_WR_RESPONSE_LATENCY(1),\n          .C_MSGON_VAL(1),\n          .C_ENABLE_RST_SYNC(1),\n          .C_ERROR_INJECTION_TYPE(0),\n          .C_HAS_SLAVE_CE(0),\n          .C_HAS_MASTER_CE(0),\n          .C_ADD_NGC_CONSTRAINT(0),\n          .C_USE_COMMON_OVERFLOW(0),\n          .C_USE_COMMON_UNDERFLOW(0),\n          .C_USE_DEFAULT_SETTINGS(0),\n          .C_HAS_AXIS_TDATA(1),\n          .C_HAS_AXIS_TID(0),\n          .C_HAS_AXIS_TDEST(0),\n          .C_HAS_AXIS_TUSER(1),\n          .C_HAS_AXIS_TREADY(1),\n          .C_HAS_AXIS_TLAST(0),\n          .C_HAS_AXIS_TSTRB(0),\n          .C_HAS_AXIS_TKEEP(0),\n          .C_AXIS_TDATA_WIDTH(8),\n          .C_AXIS_TID_WIDTH(1),\n          .C_AXIS_TDEST_WIDTH(1),\n          .C_AXIS_TUSER_WIDTH(4),\n          .C_AXIS_TSTRB_WIDTH(1),\n          .C_AXIS_TKEEP_WIDTH(1),\n          .C_AXIS_TYPE(0),\n          .C_IMPLEMENTATION_TYPE_WACH(12),\n          .C_IMPLEMENTATION_TYPE_WDCH(12),\n          .C_IMPLEMENTATION_TYPE_WRCH(12),\n          .C_IMPLEMENTATION_TYPE_RACH(12),\n          .C_IMPLEMENTATION_TYPE_RDCH(12),\n          .C_IMPLEMENTATION_TYPE_AXIS(11),\n          .C_APPLICATION_TYPE_WACH(0),\n          .C_APPLICATION_TYPE_WDCH(0),\n          .C_APPLICATION_TYPE_WRCH(0),\n          .C_APPLICATION_TYPE_RACH(0),\n          .C_APPLICATION_TYPE_RDCH(0),\n          .C_APPLICATION_TYPE_AXIS(0),\n          .C_USE_ECC_WACH(0),\n          .C_USE_ECC_WDCH(0),\n          .C_USE_ECC_WRCH(0),\n          .C_USE_ECC_RACH(0),\n          .C_USE_ECC_RDCH(0),\n          .C_USE_ECC_AXIS(0),\n          .C_ERROR_INJECTION_TYPE_WACH(0),\n          .C_ERROR_INJECTION_TYPE_WDCH(0),\n          .C_ERROR_INJECTION_TYPE_WRCH(0),\n          .C_ERROR_INJECTION_TYPE_RACH(0),\n          .C_ERROR_INJECTION_TYPE_RDCH(0),\n          .C_ERROR_INJECTION_TYPE_AXIS(0),\n          .C_DIN_WIDTH_AXIS(1),\n          .C_WR_DEPTH_WACH(16),\n          .C_WR_DEPTH_WDCH(16),\n          .C_WR_DEPTH_WRCH(16),\n          .C_WR_DEPTH_RACH(16),\n          .C_WR_DEPTH_RDCH(16),\n          .C_WR_DEPTH_AXIS(1024),\n          .C_WR_PNTR_WIDTH_WACH(4),\n          .C_WR_PNTR_WIDTH_WDCH(4),\n          .C_WR_PNTR_WIDTH_WRCH(4),\n          .C_WR_PNTR_WIDTH_RACH(4),\n          .C_WR_PNTR_WIDTH_RDCH(4),\n          .C_WR_PNTR_WIDTH_AXIS(10),\n          .C_HAS_DATA_COUNTS_WACH(0),\n          .C_HAS_DATA_COUNTS_WDCH(0),\n          .C_HAS_DATA_COUNTS_WRCH(0),\n          .C_HAS_DATA_COUNTS_RACH(0),\n          .C_HAS_DATA_COUNTS_RDCH(0),\n          .C_HAS_DATA_COUNTS_AXIS(0),\n          .C_HAS_PROG_FLAGS_WACH(0),\n          .C_HAS_PROG_FLAGS_WDCH(0),\n          .C_HAS_PROG_FLAGS_WRCH(0),\n          .C_HAS_PROG_FLAGS_RACH(0),\n          .C_HAS_PROG_FLAGS_RDCH(0),\n          .C_HAS_PROG_FLAGS_AXIS(0),\n          .C_PROG_FULL_TYPE_WACH(0),\n          .C_PROG_FULL_TYPE_WDCH(0),\n          .C_PROG_FULL_TYPE_WRCH(0),\n          .C_PROG_FULL_TYPE_RACH(0),\n          .C_PROG_FULL_TYPE_RDCH(0),\n          .C_PROG_FULL_TYPE_AXIS(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),\n          .C_PROG_EMPTY_TYPE_WACH(0),\n          .C_PROG_EMPTY_TYPE_WDCH(0),\n          .C_PROG_EMPTY_TYPE_WRCH(0),\n          .C_PROG_EMPTY_TYPE_RACH(0),\n          .C_PROG_EMPTY_TYPE_RDCH(0),\n          .C_PROG_EMPTY_TYPE_AXIS(0),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1021),\n          .C_REG_SLICE_MODE_WACH(0),\n          .C_REG_SLICE_MODE_WDCH(0),\n          .C_REG_SLICE_MODE_WRCH(0),\n          .C_REG_SLICE_MODE_RACH(0),\n          .C_REG_SLICE_MODE_RDCH(0),\n          .C_REG_SLICE_MODE_AXIS(0)\n          )\n          asyncfifo_axi (\n            .s_aclk(s_axi_aclk),\n            .m_aclk(m_axi_aclk),\n            .s_aresetn(async_conv_reset_n),\n            .s_axi_awid           (si_cc_awid),\n            .s_axi_awaddr         (si_cc_awaddr),\n            .s_axi_awlen          (si_cc_awlen),\n            .s_axi_awsize         (si_cc_awsize),\n            .s_axi_awburst        (si_cc_awburst),\n            .s_axi_awlock         (si_cc_awlock),\n            .s_axi_awcache        (si_cc_awcache),\n            .s_axi_awprot         (si_cc_awprot),\n            .s_axi_awqos          (si_cc_awqos),\n            .s_axi_awregion       (si_cc_awregion),\n            .s_axi_awuser         (si_cc_awuser),\n            .s_axi_awvalid        (si_cc_awvalid),\n            .s_axi_awready        (si_cc_awready),\n            .s_axi_wid            (si_cc_wid),\n            .s_axi_wdata          (si_cc_wdata),\n            .s_axi_wstrb          (si_cc_wstrb),\n            .s_axi_wlast          (si_cc_wlast),\n            .s_axi_wuser          (si_cc_wuser),\n            .s_axi_wvalid         (si_cc_wvalid),\n            .s_axi_wready         (si_cc_wready),\n            .s_axi_bid            (si_cc_bid),\n            .s_axi_bresp          (si_cc_bresp),\n            .s_axi_buser          (si_cc_buser),\n            .s_axi_bvalid         (si_cc_bvalid),\n            .s_axi_bready         (si_cc_bready),\n            .m_axi_awid           (cc_mi_awid),\n            .m_axi_awaddr         (cc_mi_awaddr),\n            .m_axi_awlen          (cc_mi_awlen),\n            .m_axi_awsize         (cc_mi_awsize),\n            .m_axi_awburst        (cc_mi_awburst),\n            .m_axi_awlock         (cc_mi_awlock),\n            .m_axi_awcache        (cc_mi_awcache),\n            .m_axi_awprot         (cc_mi_awprot),\n            .m_axi_awqos          (cc_mi_awqos),\n            .m_axi_awregion       (cc_mi_awregion),\n            .m_axi_awuser         (cc_mi_awuser),\n            .m_axi_awvalid        (cc_mi_awvalid),\n            .m_axi_awready        (cc_mi_awready),\n            .m_axi_wid            (cc_mi_wid),\n            .m_axi_wdata          (cc_mi_wdata),\n            .m_axi_wstrb          (cc_mi_wstrb),\n            .m_axi_wlast          (cc_mi_wlast),\n            .m_axi_wuser          (cc_mi_wuser),\n            .m_axi_wvalid         (cc_mi_wvalid),\n            .m_axi_wready         (cc_mi_wready),\n            .m_axi_bid            (cc_mi_bid),\n            .m_axi_bresp          (cc_mi_bresp),\n            .m_axi_buser          (cc_mi_buser),\n            .m_axi_bvalid         (cc_mi_bvalid),\n            .m_axi_bready         (cc_mi_bready),\n            .s_axi_arid           (si_cc_arid),\n            .s_axi_araddr         (si_cc_araddr),\n            .s_axi_arlen          (si_cc_arlen),\n            .s_axi_arsize         (si_cc_arsize),\n            .s_axi_arburst        (si_cc_arburst),\n            .s_axi_arlock         (si_cc_arlock),\n            .s_axi_arcache        (si_cc_arcache),\n            .s_axi_arprot         (si_cc_arprot),\n            .s_axi_arqos          (si_cc_arqos),\n            .s_axi_arregion       (si_cc_arregion),\n            .s_axi_aruser         (si_cc_aruser),\n            .s_axi_arvalid        (si_cc_arvalid),\n            .s_axi_arready        (si_cc_arready),\n            .s_axi_rid            (si_cc_rid),\n            .s_axi_rdata          (si_cc_rdata),\n            .s_axi_rresp          (si_cc_rresp),\n            .s_axi_rlast          (si_cc_rlast),\n            .s_axi_ruser          (si_cc_ruser),\n            .s_axi_rvalid         (si_cc_rvalid),\n            .s_axi_rready         (si_cc_rready),\n            .m_axi_arid           (cc_mi_arid),\n            .m_axi_araddr         (cc_mi_araddr),\n            .m_axi_arlen          (cc_mi_arlen),\n            .m_axi_arsize         (cc_mi_arsize),\n            .m_axi_arburst        (cc_mi_arburst),\n            .m_axi_arlock         (cc_mi_arlock),\n            .m_axi_arcache        (cc_mi_arcache),\n            .m_axi_arprot         (cc_mi_arprot),\n            .m_axi_arqos          (cc_mi_arqos),\n            .m_axi_arregion       (cc_mi_arregion),\n            .m_axi_aruser         (cc_mi_aruser),\n            .m_axi_arvalid        (cc_mi_arvalid),\n            .m_axi_arready        (cc_mi_arready),\n            .m_axi_rid            (cc_mi_rid),\n            .m_axi_rdata          (cc_mi_rdata),\n            .m_axi_rresp          (cc_mi_rresp),\n            .m_axi_rlast          (cc_mi_rlast),\n            .m_axi_ruser          (cc_mi_ruser),\n            .m_axi_rvalid         (cc_mi_rvalid),\n            .m_axi_rready         (cc_mi_rready),\n            .m_aclk_en(1'b1),\n            .s_aclk_en(1'b1),\n            .almost_empty(),\n            .almost_full(),\n            .axis_data_count(),\n            .axis_dbiterr(),\n            .axis_injectdbiterr(1'b0),\n            .axis_injectsbiterr(1'b0),\n            .axis_overflow(),\n            .axis_prog_empty(),\n            .axis_prog_empty_thresh(10'b0),\n            .axis_prog_full(),\n            .axis_prog_full_thresh(10'b0),\n            .axis_rd_data_count(),\n            .axis_sbiterr(),\n            .axis_underflow(),\n            .axis_wr_data_count(),\n            .axi_ar_data_count(),\n            .axi_ar_dbiterr(),\n            .axi_ar_injectdbiterr(1'b0),\n            .axi_ar_injectsbiterr(1'b0),\n            .axi_ar_overflow(),\n            .axi_ar_prog_empty(),\n            .axi_ar_prog_empty_thresh(4'b0),\n            .axi_ar_prog_full(),\n            .axi_ar_prog_full_thresh(4'b0),\n            .axi_ar_rd_data_count(),\n            .axi_ar_sbiterr(),\n            .axi_ar_underflow(),\n            .axi_ar_wr_data_count(),\n            .axi_aw_data_count(),\n            .axi_aw_dbiterr(),\n            .axi_aw_injectdbiterr(1'b0),\n            .axi_aw_injectsbiterr(1'b0),\n            .axi_aw_overflow(),\n            .axi_aw_prog_empty(),\n            .axi_aw_prog_empty_thresh(4'b0),\n            .axi_aw_prog_full(),\n            .axi_aw_prog_full_thresh(4'b0),\n            .axi_aw_rd_data_count(),\n            .axi_aw_sbiterr(),\n            .axi_aw_underflow(),\n            .axi_aw_wr_data_count(),\n            .axi_b_data_count(),\n            .axi_b_dbiterr(),\n            .axi_b_injectdbiterr(1'b0),\n            .axi_b_injectsbiterr(1'b0),\n            .axi_b_overflow(),\n            .axi_b_prog_empty(),\n            .axi_b_prog_empty_thresh(4'b0),\n            .axi_b_prog_full(),\n            .axi_b_prog_full_thresh(4'b0),\n            .axi_b_rd_data_count(),\n            .axi_b_sbiterr(),\n            .axi_b_underflow(),\n            .axi_b_wr_data_count(),\n            .axi_r_data_count(),\n            .axi_r_dbiterr(),\n            .axi_r_injectdbiterr(1'b0),\n            .axi_r_injectsbiterr(1'b0),\n            .axi_r_overflow(),\n            .axi_r_prog_empty(),\n            .axi_r_prog_empty_thresh(4'b0),\n            .axi_r_prog_full(),\n            .axi_r_prog_full_thresh(4'b0),\n            .axi_r_rd_data_count(),\n            .axi_r_sbiterr(),\n            .axi_r_underflow(),\n            .axi_r_wr_data_count(),\n            .axi_w_data_count(),\n            .axi_w_dbiterr(),\n            .axi_w_injectdbiterr(1'b0),\n            .axi_w_injectsbiterr(1'b0),\n            .axi_w_overflow(),\n            .axi_w_prog_empty(),\n            .axi_w_prog_empty_thresh(4'b0),\n            .axi_w_prog_full(),\n            .axi_w_prog_full_thresh(4'b0),\n            .axi_w_rd_data_count(),\n            .axi_w_sbiterr(),\n            .axi_w_underflow(),\n            .axi_w_wr_data_count(),\n            .backup(1'b0),\n            .backup_marker(1'b0),\n            .clk(1'b0),\n            .data_count(),\n            .dbiterr(),\n            .din(18'b0),\n            .dout(),\n            .empty(),\n            .full(),\n            .injectdbiterr(1'b0),\n            .injectsbiterr(1'b0),\n            .int_clk(1'b0),\n            .m_axis_tdata(),\n            .m_axis_tdest(),\n            .m_axis_tid(),\n            .m_axis_tkeep(),\n            .m_axis_tlast(),\n            .m_axis_tready(1'b0),\n            .m_axis_tstrb(),\n            .m_axis_tuser(),\n            .m_axis_tvalid(),\n            .overflow(),\n            .prog_empty(),\n            .prog_empty_thresh(10'b0),\n            .prog_empty_thresh_assert(10'b0),\n            .prog_empty_thresh_negate(10'b0),\n            .prog_full(),\n            .prog_full_thresh(10'b0),\n            .prog_full_thresh_assert(10'b0),\n            .prog_full_thresh_negate(10'b0),\n            .rd_clk(1'b0),\n            .rd_data_count(),\n            .rd_en(1'b0),\n            .rd_rst(1'b0),\n            .rst(1'b0),\n            .sbiterr(),\n            .srst(1'b0),\n            .s_axis_tdata(8'b0),\n            .s_axis_tdest(1'b0),\n            .s_axis_tid(1'b0),\n            .s_axis_tkeep(1'b0),\n            .s_axis_tlast(1'b0),\n            .s_axis_tready(),\n            .s_axis_tstrb(1'b0),\n            .s_axis_tuser(4'b0),\n            .s_axis_tvalid(1'b0),\n            .underflow(),\n            .valid(),\n            .wr_ack(),\n            .wr_clk(1'b0),\n            .wr_data_count(),\n            .wr_en(1'b0),\n            .wr_rst(1'b0),\n            .wr_rst_busy(),\n            .rd_rst_busy(),\n            .sleep(1'b0)\n        );\n      end else if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_async_lite_conv\n        localparam C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n        `include \"axi_infrastructure_v1_1_0.vh\"\n\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n        axi_infrastructure_v1_1_0_axi2vector #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        axi2vec ( \n          .s_axi_awid      ( si_cc_awid      ) ,\n          .s_axi_awaddr    ( si_cc_awaddr    ) ,\n          .s_axi_awlen     ( s_axi_awlen     ) ,\n          .s_axi_awsize    ( si_cc_awsize    ) ,\n          .s_axi_awburst   ( si_cc_awburst   ) ,\n          .s_axi_awlock    ( s_axi_awlock    ) ,\n          .s_axi_awcache   ( si_cc_awcache   ) ,\n          .s_axi_awprot    ( si_cc_awprot    ) ,\n          .s_axi_awqos     ( si_cc_awqos     ) ,\n          .s_axi_awuser    ( si_cc_awuser    ) ,\n          .s_axi_awregion  ( si_cc_awregion  ) ,\n          .s_axi_wid       ( si_cc_wid       ) ,\n          .s_axi_wdata     ( si_cc_wdata     ) ,\n          .s_axi_wstrb     ( si_cc_wstrb     ) ,\n          .s_axi_wlast     ( si_cc_wlast     ) ,\n          .s_axi_wuser     ( si_cc_wuser     ) ,\n          .s_axi_bid       ( si_cc_bid       ) ,\n          .s_axi_bresp     ( si_cc_bresp     ) ,\n          .s_axi_buser     ( si_cc_buser     ) ,\n          .s_axi_arid      ( si_cc_arid      ) ,\n          .s_axi_araddr    ( si_cc_araddr    ) ,\n          .s_axi_arlen     ( s_axi_arlen     ) ,\n          .s_axi_arsize    ( si_cc_arsize    ) ,\n          .s_axi_arburst   ( si_cc_arburst   ) ,\n          .s_axi_arlock    ( s_axi_arlock    ) ,\n          .s_axi_arcache   ( si_cc_arcache   ) ,\n          .s_axi_arprot    ( si_cc_arprot    ) ,\n          .s_axi_arqos     ( si_cc_arqos     ) ,\n          .s_axi_aruser    ( si_cc_aruser    ) ,\n          .s_axi_arregion  ( si_cc_arregion  ) ,\n          .s_axi_rid       ( si_cc_rid       ) ,\n          .s_axi_rdata     ( si_cc_rdata     ) ,\n          .s_axi_rresp     ( si_cc_rresp     ) ,\n          .s_axi_rlast     ( si_cc_rlast     ) ,\n          .s_axi_ruser     ( si_cc_ruser     ) ,\n          .s_awpayload     ( s_awpayload ) ,\n          .s_wpayload      ( s_wpayload  ) ,\n          .s_bpayload      ( s_bpayload  ) ,\n          .s_arpayload     ( s_arpayload ) ,\n          .s_rpayload      ( s_rpayload  ) \n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_AWPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_aw (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_awvalid),\n          .s_ready  (si_cc_awready),\n          .s_payld  (s_awpayload),\n          .m_valid  (cc_mi_awvalid),\n          .m_ready  (cc_mi_awready),\n          .m_payld  (m_awpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_ARPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_ar (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_arvalid),\n          .s_ready  (si_cc_arready),\n          .s_payld  (s_arpayload),\n          .m_valid  (cc_mi_arvalid),\n          .m_ready  (cc_mi_arready),\n          .m_payld  (m_arpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_WPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_w (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_wvalid),\n          .s_ready  (si_cc_wready),\n          .s_payld  (s_wpayload),\n          .m_valid  (cc_mi_wvalid),\n          .m_ready  (cc_mi_wready),\n          .m_payld  (m_wpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_BPAYLOAD_WIDTH)\n        ) clock_conv_lite_resp_b (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_bvalid),\n          .s_ready  (cc_mi_bready),\n          .s_payld  (m_bpayload),\n          .m_valid  (si_cc_bvalid),\n          .m_ready  (si_cc_bready),\n          .m_payld  (s_bpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_RPAYLOAD_WIDTH)\n        ) clock_conv_lite_resp_r (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_rvalid),\n          .s_ready  (cc_mi_rready),\n          .s_payld  (m_rpayload),\n          .m_valid  (si_cc_rvalid),\n          .m_ready  (si_cc_rready),\n          .m_payld  (s_rpayload)\n        );\n\n        axi_infrastructure_v1_1_0_vector2axi #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        vec2axi ( \n          .m_awpayload    ( m_awpayload    ) ,\n          .m_wpayload     ( m_wpayload     ) ,\n          .m_bpayload     ( m_bpayload     ) ,\n          .m_arpayload    ( m_arpayload    ) ,\n          .m_rpayload     ( m_rpayload     ) ,\n          .m_axi_awid     ( cc_mi_awid     ) ,\n          .m_axi_awaddr   ( cc_mi_awaddr   ) ,\n          .m_axi_awlen    ( cc_mi_awlen    ) ,\n          .m_axi_awsize   ( cc_mi_awsize   ) ,\n          .m_axi_awburst  ( cc_mi_awburst  ) ,\n          .m_axi_awlock   ( cc_mi_awlock   ) ,\n          .m_axi_awcache  ( cc_mi_awcache  ) ,\n          .m_axi_awprot   ( cc_mi_awprot   ) ,\n          .m_axi_awqos    ( cc_mi_awqos    ) ,\n          .m_axi_awuser   ( cc_mi_awuser   ) ,\n          .m_axi_awregion ( cc_mi_awregion ) ,\n          .m_axi_wid      ( cc_mi_wid      ) ,\n          .m_axi_wdata    ( cc_mi_wdata    ) ,\n          .m_axi_wstrb    ( cc_mi_wstrb    ) ,\n          .m_axi_wlast    ( cc_mi_wlast    ) ,\n          .m_axi_wuser    ( cc_mi_wuser    ) ,\n          .m_axi_bid      ( cc_mi_bid      ) ,\n          .m_axi_bresp    ( cc_mi_bresp    ) ,\n          .m_axi_buser    ( cc_mi_buser    ) ,\n          .m_axi_arid     ( cc_mi_arid     ) ,\n          .m_axi_araddr   ( cc_mi_araddr   ) ,\n          .m_axi_arlen    ( cc_mi_arlen    ) ,\n          .m_axi_arsize   ( cc_mi_arsize   ) ,\n          .m_axi_arburst  ( cc_mi_arburst  ) ,\n          .m_axi_arlock   ( cc_mi_arlock   ) ,\n          .m_axi_arcache  ( cc_mi_arcache  ) ,\n          .m_axi_arprot   ( cc_mi_arprot   ) ,\n          .m_axi_arqos    ( cc_mi_arqos    ) ,\n          .m_axi_aruser   ( cc_mi_aruser   ) ,\n          .m_axi_arregion ( cc_mi_arregion ) ,\n          .m_axi_rid      ( cc_mi_rid      ) ,\n          .m_axi_rdata    ( cc_mi_rdata    ) ,\n          .m_axi_rresp    ( cc_mi_rresp    ) ,\n          .m_axi_rlast    ( cc_mi_rlast    ) ,\n          .m_axi_ruser    ( cc_mi_ruser    ) \n        );\n\n      end else begin : gen_sync_conv\n        \n        assign {fast_aclk, slow_aclk} = P_SI_LT_MI ? {m_axi_aclk, s_axi_aclk} : {s_axi_aclk, m_axi_aclk};\n    \n        // Sample cycle used to determine when to assert a signal on a fast clock\n        // to be flopped onto a slow clock.\n        axi_clock_converter_v2_1_21_axic_sample_cycle_ratio #(\n          .C_RATIO ( P_ACLK_RATIO )\n        )\n        axic_sample_cycle_inst (\n          .SLOW_ACLK          ( slow_aclk               ) ,\n          .FAST_ACLK          ( fast_aclk               ) ,\n          .SAMPLE_CYCLE_EARLY ( sample_cycle_early ) ,\n          .SAMPLE_CYCLE       ( sample_cycle       )\n        );\n    \n      ////////////////////////////////////////////////////////////////////////////////\n      // AXI write channels\n      ////////////////////////////////////////////////////////////////////////////////\n        if (C_AXI_SUPPORTS_WRITE) begin : gen_conv_write_ch\n    \n          // Write Address Port\n          assign s_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH]     = si_cc_awaddr   ;\n          assign s_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH]     = si_cc_awprot   ;\n          assign cc_mi_awaddr   = m_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH];\n          assign cc_mi_awprot   = m_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_aw_axi4\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen    ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock[0] ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH] = si_cc_awregion ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awregion = m_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_aw_axi3\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen[3:0] ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock   ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_aw_user\n            assign s_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH]  = si_cc_awuser;\n            assign cc_mi_awuser = m_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AW_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          aw_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_aw_mesg ) ,\n            .S_VALID   ( si_cc_awvalid   ) ,\n            .S_READY   ( si_cc_awready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_aw_mesg ) ,\n            .M_VALID   ( cc_mi_awvalid   ) ,\n            .M_READY   ( cc_mi_awready   )\n          );\n    \n          // Write Data Port\n          assign s_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH] = si_cc_wdata; \n          assign s_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH] = si_cc_wstrb; \n          assign cc_mi_wdata    = m_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH];\n          assign cc_mi_wstrb    = m_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_w_axi4\n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_w_axi3\n            assign s_w_mesg[C_WID_RIGHT+:C_WID_WIDTH]     = si_cc_wid; \n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wid      = m_w_mesg[C_WID_RIGHT+:C_WID_WIDTH];\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_w_user\n            assign s_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH]  = si_cc_wuser;\n            assign cc_mi_wuser = m_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH  ( C_W_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE           ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          w_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_w_mesg ) ,\n            .S_VALID   ( si_cc_wvalid   ) ,\n            .S_READY   ( si_cc_wready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_w_mesg ) ,\n            .M_VALID   ( cc_mi_wvalid   ) ,\n            .M_READY   ( cc_mi_wready   )\n          );\n    \n          // Write Response Port\n          assign m_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH] = cc_mi_bresp;\n          assign si_cc_bresp    = s_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_b_axi\n            assign m_b_mesg[C_BID_RIGHT+:C_BID_WIDTH]     = cc_mi_bid;\n            assign si_cc_bid      = s_b_mesg[C_BID_RIGHT+:C_BID_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_b_user\n            assign m_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH] = cc_mi_buser;\n            assign si_cc_buser  = s_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_B_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          b_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_b_mesg ) ,\n            .S_VALID   ( cc_mi_bvalid   ) ,\n            .S_READY   ( cc_mi_bready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_b_mesg ) ,\n            .M_VALID   ( si_cc_bvalid   ) ,\n            .M_READY   ( si_cc_bready   )\n          );\n    \n        end else begin : gen_tieoff_write_ch\n    \n          // Write address port\n          assign cc_mi_awid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_awaddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_awlen    = {8{1'b0}};\n          assign cc_mi_awsize   = {3{1'b0}};\n          assign cc_mi_awburst  = {2{1'b0}};\n          assign cc_mi_awlock   = {2{1'b0}};\n          assign cc_mi_awcache  = {4{1'b0}};\n          assign cc_mi_awprot   = {3{1'b0}};\n          assign cc_mi_awregion = {4{1'b0}};\n          assign cc_mi_awqos    = {4{1'b0}};\n          assign cc_mi_awuser   = {C_AXI_AWUSER_WIDTH{1'b0}};\n          assign cc_mi_awvalid  = 1'b0;\n          assign si_cc_awready  = 1'b0;\n    \n          // Write data port\n          assign cc_mi_wid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_wdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign cc_mi_wstrb    = {C_AXI_DATA_WIDTH/8{1'b0}};\n          assign cc_mi_wlast    = 1'b0;\n          assign cc_mi_wuser    = {C_AXI_WUSER_WIDTH{1'b0}};\n          assign cc_mi_wvalid   = 1'b0;\n          assign si_cc_wready   = 1'b0;\n    \n          // Write response port\n          assign si_cc_bid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_bresp    = {2{1'b0}};\n          assign si_cc_buser    = {C_AXI_BUSER_WIDTH{1'b0}};\n          assign si_cc_bvalid   = 1'b0;\n          assign cc_mi_bready   = 1'b0;\n        end\n    \n        ////////////////////////////////////////////////////////////////////////////////\n        // AXI read channels\n        ////////////////////////////////////////////////////////////////////////////////\n    \n        if (C_AXI_SUPPORTS_READ) begin : gen_conv_read_ch\n    \n          // Read Address Port\n          assign s_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH]     = si_cc_araddr   ;\n          assign s_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH]     = si_cc_arprot   ;\n          assign cc_mi_araddr   = m_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH];\n          assign cc_mi_arprot   = m_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_ar_axi4\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen    ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock[0] ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH] = si_cc_arregion ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arregion = m_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_ar_axi3\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen[3:0] ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock   ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_ar_user\n            assign s_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH]  = si_cc_aruser;\n            assign cc_mi_aruser = m_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AR_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          ar_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_ar_mesg ) ,\n            .S_VALID   ( si_cc_arvalid   ) ,\n            .S_READY   ( si_cc_arready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN  ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_ar_mesg ) ,\n            .M_VALID   ( cc_mi_arvalid   ) ,\n            .M_READY   ( cc_mi_arready   )\n          );\n    \n          // Read Data Port\n          assign m_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH] = cc_mi_rdata; \n          assign m_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH] = cc_mi_rresp; \n          assign si_cc_rdata    = s_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH];\n          assign si_cc_rresp    = s_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_r_axi\n            assign m_r_mesg[C_RID_RIGHT+:C_RID_WIDTH]     = cc_mi_rid;   \n            assign m_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH] = cc_mi_rlast;\n            assign si_cc_rid      = s_r_mesg[C_RID_RIGHT+:C_RID_WIDTH];\n            assign si_cc_rlast    = s_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_r_user\n            assign m_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH] = cc_mi_ruser;\n            assign si_cc_ruser  = s_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_R_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          r_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_r_mesg ) ,\n            .S_VALID   ( cc_mi_rvalid   ) ,\n            .S_READY   ( cc_mi_rready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_r_mesg ) ,\n            .M_VALID   ( si_cc_rvalid   ) ,\n            .M_READY   ( si_cc_rready   )\n          );\n    \n        end else begin : gen_tieoff_read_ch\n    \n          // Read Address Port\n          assign cc_mi_arid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_araddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_arlen    = {8{1'b0}};\n          assign cc_mi_arsize   = {3{1'b0}};\n          assign cc_mi_arburst  = {2{1'b0}};\n          assign cc_mi_arlock   = {2{1'b0}};\n          assign cc_mi_arcache  = {4{1'b0}};\n          assign cc_mi_arprot   = {3{1'b0}};\n          assign cc_mi_arregion = {4{1'b0}};\n          assign cc_mi_arqos    = {4{1'b0}};\n          assign cc_mi_aruser   = {C_AXI_ARUSER_WIDTH{1'b0}};\n          assign cc_mi_arvalid  = 1'b0;\n          assign si_cc_arready  = 1'b0;\n    \n          // Read data port\n          assign si_cc_rid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_rdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign si_cc_rresp    = {2{1'b0}};\n          assign si_cc_rlast    = 1'b0;\n          assign si_cc_ruser    = {C_AXI_RUSER_WIDTH{1'b0}};\n          assign si_cc_rvalid   = 1'b0;\n          assign cc_mi_rready   = 1'b0;\n        end\n      end\n    end\n\n  endgenerate\n\nendmodule\n\n\n\n", "num_lines": 2178}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1\n// IP Revision: 21\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_clock_converter_0 (\n  s_axi_aclk,\n  s_axi_aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awuser,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_aruser,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_aclk,\n  m_axi_aresetn,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awuser,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_aruser,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_CLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 SI_CLK CLK\" *)\ninput wire s_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 SI_RST RST\" *)\ninput wire s_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWUSER\" *)\ninput wire [18 : 0] s_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARUSER\" *)\ninput wire [18 : 0] s_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 19, ARUSER_WIDTH 19, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUS\\\nER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_CLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 MI_CLK CLK\" *)\ninput wire m_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 MI_RST RST\" *)\ninput wire m_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWUSER\" *)\noutput wire [18 : 0] m_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARUSER\" *)\noutput wire [18 : 0] m_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 19, ARUSER_WIDTH 19, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUS\\\nER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_clock_converter_v2_1_21_axi_clock_converter #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_S_AXI_ACLK_RATIO(1),\n    .C_M_AXI_ACLK_RATIO(2),\n    .C_AXI_IS_ACLK_ASYNC(1),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_SUPPORTS_USER_SIGNALS(1),\n    .C_AXI_AWUSER_WIDTH(19),\n    .C_AXI_ARUSER_WIDTH(19),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_AXI_SUPPORTS_WRITE(1),\n    .C_AXI_SUPPORTS_READ(1),\n    .C_SYNCHRONIZER_STAGE(2)\n  ) inst (\n    .s_axi_aclk(s_axi_aclk),\n    .s_axi_aresetn(s_axi_aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(s_axi_awuser),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(s_axi_aruser),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_aclk(m_axi_aclk),\n    .m_axi_aresetn(m_axi_aresetn),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(m_axi_awuser),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(m_axi_aruser),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 441}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/*\n *******************************************************************************\n *\n * FIFO Generator - Verilog Behavioral Model\n *\n *******************************************************************************\n *\n * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.\n *\n * This file contains confidential and proprietary information\n * of Xilinx, Inc. and is protected under U.S. and\n * international copyright and other intellectual property\n * laws.\n *\n * DISCLAIMER\n * This disclaimer is not a license and does not grant any\n * rights to the materials distributed herewith. Except as\n * otherwise provided in a valid license issued to you by\n * Xilinx, and to the maximum extent permitted by applicable\n * law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n * (2) Xilinx shall not be liable (whether in contract or tort,\n * including negligence, or under any other theory of\n * liability) for any loss or damage of any kind or nature\n * related to, arising under or in connection with these\n * materials, including for any direct, or any indirect,\n * special, incidental, or consequential loss or damage\n * (including loss of data, profits, goodwill, or any type of\n * loss or damage suffered as a result of any action brought\n * by a third party) even if such damage or loss was\n * reasonably foreseeable or Xilinx had been advised of the\n * possibility of the same.\n *\n * CRITICAL APPLICATIONS\n * Xilinx products are not designed or intended to be fail-\n * safe, or for use in any application requiring fail-safe\n * performance, such as life-support or safety devices or\n * systems, Class III medical devices, nuclear facilities,\n * applications related to the deployment of airbags, or any\n * other applications that could lead to death, personal\n * injury, or severe property or environmental damage\n * (individually and collectively, \"Critical\n * Applications\"). Customer assumes the sole risk and\n * liability of any use of Xilinx products in Critical\n * Applications, subject only to applicable laws and\n * regulations governing limitations on product liability.\n *\n * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n * PART OF THIS FILE AT ALL TIMES.\n *\n *******************************************************************************\n *******************************************************************************\n *\n * Filename: fifo_generator_vlog_beh.v\n *\n * Author     : Xilinx\n *\n *******************************************************************************\n * Structure:\n * \n * fifo_generator_vlog_beh.v\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_as\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_ss\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_preload0\n * \n *******************************************************************************\n * Description:\n *\n * The Verilog behavioral model for the FIFO Generator.\n *\n *   The behavioral model has three parts:\n *      - The behavioral model for independent clocks FIFOs (_as)\n *      - The behavioral model for common clock FIFOs (_ss)\n *      - The \"preload logic\" block which implements First-word Fall-through\n * \n *******************************************************************************\n * Description:\n *  The verilog behavioral model for the FIFO generator core.\n *\n *******************************************************************************\n */\n\n`timescale 1ps/1ps\n`ifndef TCQ\n `define TCQ 100\n`endif\n\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_vlog_beh\n  #(\n    //-----------------------------------------------------------------------\n    // Generic Declarations\n    //-----------------------------------------------------------------------\n    parameter C_COMMON_CLOCK                 = 0,\n    parameter C_COUNT_TYPE                   = 0,\n    parameter C_DATA_COUNT_WIDTH             = 2,\n    parameter C_DEFAULT_VALUE                = \"\",\n    parameter C_DIN_WIDTH                    = 8,\n    parameter C_DOUT_RST_VAL                 = \"\",\n    parameter C_DOUT_WIDTH                   = 8,\n    parameter C_ENABLE_RLOCS                 = 0,\n    parameter C_FAMILY                       = \"\",\n    parameter C_FULL_FLAGS_RST_VAL           = 1,\n    parameter C_HAS_ALMOST_EMPTY             = 0,\n    parameter C_HAS_ALMOST_FULL              = 0,\n    parameter C_HAS_BACKUP                   = 0,\n    parameter C_HAS_DATA_COUNT               = 0,\n    parameter C_HAS_INT_CLK                  = 0,\n    parameter C_HAS_MEMINIT_FILE             = 0,\n    parameter C_HAS_OVERFLOW                 = 0,\n    parameter C_HAS_RD_DATA_COUNT            = 0,\n    parameter C_HAS_RD_RST                   = 0,\n    parameter C_HAS_RST                      = 1,\n    parameter C_HAS_SRST                     = 0,\n    parameter C_HAS_UNDERFLOW                = 0,\n    parameter C_HAS_VALID                    = 0,\n    parameter C_HAS_WR_ACK                   = 0,\n    parameter C_HAS_WR_DATA_COUNT            = 0,\n    parameter C_HAS_WR_RST                   = 0,\n    parameter C_IMPLEMENTATION_TYPE          = 0,\n    parameter C_INIT_WR_PNTR_VAL             = 0,\n    parameter C_MEMORY_TYPE                  = 1,\n    parameter C_MIF_FILE_NAME                = \"\",\n    parameter C_OPTIMIZATION_MODE            = 0,\n    parameter C_OVERFLOW_LOW                 = 0,\n    parameter C_EN_SAFETY_CKT                = 0,\n    parameter C_PRELOAD_LATENCY              = 1,\n    parameter C_PRELOAD_REGS                 = 0,\n    parameter C_PRIM_FIFO_TYPE               = \"4kx4\",\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter C_PROG_EMPTY_TYPE              = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter C_PROG_FULL_TYPE               = 0,\n    parameter C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter C_RD_DEPTH                     = 256,\n    parameter C_RD_FREQ                      = 1,\n    parameter C_RD_PNTR_WIDTH                = 8,\n    parameter C_UNDERFLOW_LOW                = 0,\n    parameter C_USE_DOUT_RST                 = 0,\n    parameter C_USE_ECC                      = 0,\n    parameter C_USE_EMBEDDED_REG             = 0,\n    parameter C_USE_PIPELINE_REG             = 0,\n    parameter C_POWER_SAVING_MODE            = 0,\n    parameter C_USE_FIFO16_FLAGS             = 0,\n    parameter C_USE_FWFT_DATA_COUNT          = 0,\n    parameter C_VALID_LOW                    = 0,\n    parameter C_WR_ACK_LOW                   = 0,\n    parameter C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter C_WR_DEPTH                     = 256,\n    parameter C_WR_FREQ                      = 1,\n    parameter C_WR_PNTR_WIDTH                = 8,\n    parameter C_WR_RESPONSE_LATENCY          = 1,\n    parameter C_MSGON_VAL                    = 1,\n    parameter C_ENABLE_RST_SYNC              = 1,\n    parameter C_ERROR_INJECTION_TYPE         = 0,\n    parameter C_SYNCHRONIZER_STAGE           = 2,\n\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE               = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3\n    parameter C_AXI_TYPE                     = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3\n    parameter C_HAS_AXI_WR_CHANNEL           = 0,\n    parameter C_HAS_AXI_RD_CHANNEL           = 0,\n    parameter C_HAS_SLAVE_CE                 = 0,\n    parameter C_HAS_MASTER_CE                = 0,\n    parameter C_ADD_NGC_CONSTRAINT           = 0,\n    parameter C_USE_COMMON_UNDERFLOW         = 0,\n    parameter C_USE_COMMON_OVERFLOW          = 0,\n    parameter C_USE_DEFAULT_SETTINGS         = 0,\n\n    // AXI Full/Lite\n    parameter C_AXI_ID_WIDTH                 = 0,\n    parameter C_AXI_ADDR_WIDTH               = 0,\n    parameter C_AXI_DATA_WIDTH               = 0,\n    parameter C_AXI_LEN_WIDTH                = 8,\n    parameter C_AXI_LOCK_WIDTH               = 2,\n    parameter C_HAS_AXI_ID                   = 0,\n    parameter C_HAS_AXI_AWUSER               = 0,\n    parameter C_HAS_AXI_WUSER                = 0,\n    parameter C_HAS_AXI_BUSER                = 0,\n    parameter C_HAS_AXI_ARUSER               = 0,\n    parameter C_HAS_AXI_RUSER                = 0,\n    parameter C_AXI_ARUSER_WIDTH             = 0,\n    parameter C_AXI_AWUSER_WIDTH             = 0,\n    parameter C_AXI_WUSER_WIDTH              = 0,\n    parameter C_AXI_BUSER_WIDTH              = 0,\n    parameter C_AXI_RUSER_WIDTH              = 0,\n\n    // AXI Streaming\n    parameter C_HAS_AXIS_TDATA               = 0,\n    parameter C_HAS_AXIS_TID                 = 0,\n    parameter C_HAS_AXIS_TDEST               = 0,\n    parameter C_HAS_AXIS_TUSER               = 0,\n    parameter C_HAS_AXIS_TREADY              = 0,\n    parameter C_HAS_AXIS_TLAST               = 0,\n    parameter C_HAS_AXIS_TSTRB               = 0,\n    parameter C_HAS_AXIS_TKEEP               = 0,\n    parameter C_AXIS_TDATA_WIDTH             = 1,\n    parameter C_AXIS_TID_WIDTH               = 1,\n    parameter C_AXIS_TDEST_WIDTH             = 1,\n    parameter C_AXIS_TUSER_WIDTH             = 1,\n    parameter C_AXIS_TSTRB_WIDTH             = 1,\n    parameter C_AXIS_TKEEP_WIDTH             = 1,\n\n    // AXI Channel Type\n    // WACH --> Write Address Channel\n    // WDCH --> Write Data Channel\n    // WRCH --> Write Response Channel\n    // RACH --> Read Address Channel\n    // RDCH --> Read Data Channel\n    // AXIS --> AXI Streaming\n    parameter C_WACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic\n    parameter C_WDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_WRCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_AXIS_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n\n    // AXI Implementation Type\n    // 1 = Common Clock Block RAM FIFO\n    // 2 = Common Clock Distributed RAM FIFO\n    // 11 = Independent Clock Block RAM FIFO\n    // 12 = Independent Clock Distributed RAM FIFO\n    parameter C_IMPLEMENTATION_TYPE_WACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WRCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_AXIS     = 0,\n\n    // AXI FIFO Type\n    // 0 = Data FIFO\n    // 1 = Packet FIFO\n    // 2 = Low Latency Sync FIFO\n    // 3 = Low Latency Async FIFO\n    parameter C_APPLICATION_TYPE_WACH        = 0,\n    parameter C_APPLICATION_TYPE_WDCH        = 0,\n    parameter C_APPLICATION_TYPE_WRCH        = 0,\n    parameter C_APPLICATION_TYPE_RACH        = 0,\n    parameter C_APPLICATION_TYPE_RDCH        = 0,\n    parameter C_APPLICATION_TYPE_AXIS        = 0,\n\n    // AXI Built-in FIFO Primitive Type\n    // 512x36, 1kx18, 2kx9, 4kx4, etc\n    parameter C_PRIM_FIFO_TYPE_WACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WRCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_AXIS          = \"512x36\",\n\n    // Enable ECC\n    // 0 = ECC disabled\n    // 1 = ECC enabled\n    parameter C_USE_ECC_WACH                 = 0,\n    parameter C_USE_ECC_WDCH                 = 0,\n    parameter C_USE_ECC_WRCH                 = 0,\n    parameter C_USE_ECC_RACH                 = 0,\n    parameter C_USE_ECC_RDCH                 = 0,\n    parameter C_USE_ECC_AXIS                 = 0,\n\n    // ECC Error Injection Type\n    // 0 = No Error Injection\n    // 1 = Single Bit Error Injection\n    // 2 = Double Bit Error Injection\n    // 3 = Single Bit and Double Bit Error Injection\n    parameter C_ERROR_INJECTION_TYPE_WACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WRCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_AXIS    = 0,\n\n    // Input Data Width\n    // Accumulation of all AXI input signal's width\n    parameter C_DIN_WIDTH_WACH               = 1,\n    parameter C_DIN_WIDTH_WDCH               = 1,\n    parameter C_DIN_WIDTH_WRCH               = 1,\n    parameter C_DIN_WIDTH_RACH               = 1,\n    parameter C_DIN_WIDTH_RDCH               = 1,\n    parameter C_DIN_WIDTH_AXIS               = 1,\n\n    parameter C_WR_DEPTH_WACH                = 16,\n    parameter C_WR_DEPTH_WDCH                = 16,\n    parameter C_WR_DEPTH_WRCH                = 16,\n    parameter C_WR_DEPTH_RACH                = 16,\n    parameter C_WR_DEPTH_RDCH                = 16,\n    parameter C_WR_DEPTH_AXIS                = 16,\n\n    parameter C_WR_PNTR_WIDTH_WACH           = 4,\n    parameter C_WR_PNTR_WIDTH_WDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_WRCH           = 4,\n    parameter C_WR_PNTR_WIDTH_RACH           = 4,\n    parameter C_WR_PNTR_WIDTH_RDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_AXIS           = 4,\n\n    parameter C_HAS_DATA_COUNTS_WACH         = 0,\n    parameter C_HAS_DATA_COUNTS_WDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_WRCH         = 0,\n    parameter C_HAS_DATA_COUNTS_RACH         = 0,\n    parameter C_HAS_DATA_COUNTS_RDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_AXIS         = 0,\n\n    parameter C_HAS_PROG_FLAGS_WACH          = 0,\n    parameter C_HAS_PROG_FLAGS_WDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_WRCH          = 0,\n    parameter C_HAS_PROG_FLAGS_RACH          = 0,\n    parameter C_HAS_PROG_FLAGS_RDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_AXIS          = 0,\n\n    parameter C_PROG_FULL_TYPE_WACH          = 0,\n    parameter C_PROG_FULL_TYPE_WDCH          = 0,\n    parameter C_PROG_FULL_TYPE_WRCH          = 0,\n    parameter C_PROG_FULL_TYPE_RACH          = 0,\n    parameter C_PROG_FULL_TYPE_RDCH          = 0,\n    parameter C_PROG_FULL_TYPE_AXIS          = 0,\n\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS      = 0,\n\n    parameter C_PROG_EMPTY_TYPE_WACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WRCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_AXIS         = 0,\n\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS     = 0,\n\n    parameter C_REG_SLICE_MODE_WACH          = 0,\n    parameter C_REG_SLICE_MODE_WDCH          = 0,\n    parameter C_REG_SLICE_MODE_WRCH          = 0,\n    parameter C_REG_SLICE_MODE_RACH          = 0,\n    parameter C_REG_SLICE_MODE_RDCH          = 0,\n    parameter C_REG_SLICE_MODE_AXIS          = 0\n\n    )\n\n   (\n    //------------------------------------------------------------------------------\n    // Input and Output Declarations\n    //------------------------------------------------------------------------------\n\n    // Conventional FIFO Interface Signals\n    input                               backup,\n    input                               backup_marker,\n    input                               clk,\n    input                               rst,\n    input                               srst,\n    input                               wr_clk,\n    input                               wr_rst,\n    input                               rd_clk,\n    input                               rd_rst,\n    input [C_DIN_WIDTH-1:0]             din,\n    input                               wr_en,\n    input                               rd_en,\n    // Optional inputs\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_assert,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_negate,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_assert,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_negate,\n    input                               int_clk,\n    input                               injectdbiterr,\n    input                               injectsbiterr,\n    input                               sleep,\n\n    output [C_DOUT_WIDTH-1:0]           dout,\n    output                              full,\n    output                              almost_full,\n    output                              wr_ack,\n    output                              overflow,\n    output                              empty,\n    output                              almost_empty,\n    output                              valid,\n    output                              underflow,\n    output [C_DATA_COUNT_WIDTH-1:0]     data_count,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]  rd_data_count,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count,\n    output                              prog_full,\n    output                              prog_empty,\n    output                              sbiterr,\n    output                              dbiterr,\n    output                              wr_rst_busy,\n    output                              rd_rst_busy,\n\n\n    // AXI Global Signal\n    input                               m_aclk,\n    input                               s_aclk,\n    input                               s_aresetn,\n    input                               s_aclk_en,\n    input                               m_aclk_en,\n    \n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_awid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_awaddr,\n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_awlen,\n    input [3-1:0]                       s_axi_awsize,\n    input [2-1:0]                       s_axi_awburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_awlock,\n    input [4-1:0]                       s_axi_awcache,\n    input [3-1:0]                       s_axi_awprot,\n    input [4-1:0]                       s_axi_awqos,\n    input [4-1:0]                       s_axi_awregion,\n    input [C_AXI_AWUSER_WIDTH-1:0]      s_axi_awuser,\n    input                               s_axi_awvalid,\n    output                              s_axi_awready,\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_wid,\n    input [C_AXI_DATA_WIDTH-1:0]        s_axi_wdata,\n    input [C_AXI_DATA_WIDTH/8-1:0]      s_axi_wstrb,\n    input                               s_axi_wlast,\n    input [C_AXI_WUSER_WIDTH-1:0]       s_axi_wuser,\n    input                               s_axi_wvalid,\n    output                              s_axi_wready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_bid,\n    output [2-1:0]                      s_axi_bresp,\n    output [C_AXI_BUSER_WIDTH-1:0]      s_axi_buser,\n    output                              s_axi_bvalid,\n    input                               s_axi_bready,\n    \n    // AXI Full/Lite Master Write Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_awid,\n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_awlen,\n    output [3-1:0]                      m_axi_awsize,\n    output [2-1:0]                      m_axi_awburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_awlock,\n    output [4-1:0]                      m_axi_awcache,\n    output [3-1:0]                      m_axi_awprot,\n    output [4-1:0]                      m_axi_awqos,\n    output [4-1:0]                      m_axi_awregion,\n    output [C_AXI_AWUSER_WIDTH-1:0]     m_axi_awuser,\n    output                              m_axi_awvalid,\n    input                               m_axi_awready,\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_wid,\n    output [C_AXI_DATA_WIDTH-1:0]       m_axi_wdata,\n    output [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb,\n    output                              m_axi_wlast,\n    output [C_AXI_WUSER_WIDTH-1:0]      m_axi_wuser,\n    output                              m_axi_wvalid,\n    input                               m_axi_wready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_bid,\n    input [2-1:0]                       m_axi_bresp,\n    input [C_AXI_BUSER_WIDTH-1:0]       m_axi_buser,\n    input                               m_axi_bvalid,\n    output                              m_axi_bready,\n    \n    \n    // AXI Full/Lite Slave Read Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_arid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_araddr, \n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_arlen,\n    input [3-1:0]                       s_axi_arsize,\n    input [2-1:0]                       s_axi_arburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_arlock,\n    input [4-1:0]                       s_axi_arcache,\n    input [3-1:0]                       s_axi_arprot,\n    input [4-1:0]                       s_axi_arqos,\n    input [4-1:0]                       s_axi_arregion,\n    input [C_AXI_ARUSER_WIDTH-1:0]      s_axi_aruser,\n    input                               s_axi_arvalid,\n    output                              s_axi_arready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_rid,       \n    output [C_AXI_DATA_WIDTH-1:0]       s_axi_rdata, \n    output [2-1:0]                      s_axi_rresp,\n    output                              s_axi_rlast,\n    output [C_AXI_RUSER_WIDTH-1:0]      s_axi_ruser,\n    output                              s_axi_rvalid,\n    input                               s_axi_rready,\n    \n    \n    \n    // AXI Full/Lite Master Read Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_arid,        \n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,  \n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_arlen,\n    output [3-1:0]                      m_axi_arsize,\n    output [2-1:0]                      m_axi_arburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_arlock,\n    output [4-1:0]                      m_axi_arcache,\n    output [3-1:0]                      m_axi_arprot,\n    output [4-1:0]                      m_axi_arqos,\n    output [4-1:0]                      m_axi_arregion,\n    output [C_AXI_ARUSER_WIDTH-1:0]     m_axi_aruser,\n    output                              m_axi_arvalid,\n    input                               m_axi_arready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_rid,        \n    input [C_AXI_DATA_WIDTH-1:0]        m_axi_rdata,  \n    input [2-1:0]                       m_axi_rresp,\n    input                               m_axi_rlast,\n    input [C_AXI_RUSER_WIDTH-1:0]       m_axi_ruser,\n    input                               m_axi_rvalid,\n    output                              m_axi_rready,\n    \n    \n    // AXI Streaming Slave Signals (Write side)\n    input                               s_axis_tvalid,\n    output                              s_axis_tready,\n    input [C_AXIS_TDATA_WIDTH-1:0]      s_axis_tdata,\n    input [C_AXIS_TSTRB_WIDTH-1:0]      s_axis_tstrb,\n    input [C_AXIS_TKEEP_WIDTH-1:0]      s_axis_tkeep,\n    input                               s_axis_tlast,\n    input [C_AXIS_TID_WIDTH-1:0]        s_axis_tid,\n    input [C_AXIS_TDEST_WIDTH-1:0]      s_axis_tdest,\n    input [C_AXIS_TUSER_WIDTH-1:0]      s_axis_tuser,\n    \n    // AXI Streaming Master Signals (Read side)\n    output                              m_axis_tvalid,\n    input                               m_axis_tready,\n    output [C_AXIS_TDATA_WIDTH-1:0]     m_axis_tdata,\n    output [C_AXIS_TSTRB_WIDTH-1:0]     m_axis_tstrb,\n    output [C_AXIS_TKEEP_WIDTH-1:0]     m_axis_tkeep,\n    output                              m_axis_tlast,\n    output [C_AXIS_TID_WIDTH-1:0]       m_axis_tid,\n    output [C_AXIS_TDEST_WIDTH-1:0]     m_axis_tdest,\n    output [C_AXIS_TUSER_WIDTH-1:0]     m_axis_tuser,\n    \n           \n    \n    \n    // AXI Full/Lite Write Address Channel signals\n    input                               axi_aw_injectsbiterr,\n    input                               axi_aw_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_rd_data_count,\n    output                              axi_aw_sbiterr,\n    output                              axi_aw_dbiterr,\n    output                              axi_aw_overflow,\n    output                              axi_aw_underflow,\n    output                              axi_aw_prog_full,\n    output                              axi_aw_prog_empty,\n    \n    \n    // AXI Full/Lite Write Data Channel signals\n    input                               axi_w_injectsbiterr,\n    input                               axi_w_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_rd_data_count,\n    output                              axi_w_sbiterr,\n    output                              axi_w_dbiterr,\n    output                              axi_w_overflow,\n    output                              axi_w_underflow,\n    output                              axi_w_prog_full,\n    output                              axi_w_prog_empty,\n    \n    \n    // AXI Full/Lite Write Response Channel signals\n    input                               axi_b_injectsbiterr,\n    input                               axi_b_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_rd_data_count,\n    output                              axi_b_sbiterr,\n    output                              axi_b_dbiterr,\n    output                              axi_b_overflow,\n    output                              axi_b_underflow,\n    output                              axi_b_prog_full,\n    output                              axi_b_prog_empty,\n    \n    \n    \n    // AXI Full/Lite Read Address Channel signals\n    input                               axi_ar_injectsbiterr,\n    input                               axi_ar_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_rd_data_count,\n    output                              axi_ar_sbiterr,\n    output                              axi_ar_dbiterr,\n    output                              axi_ar_overflow,\n    output                              axi_ar_underflow,\n    output                              axi_ar_prog_full,\n    output                              axi_ar_prog_empty,\n\n    \n    // AXI Full/Lite Read Data Channel Signals\n    input                               axi_r_injectsbiterr,\n    input                               axi_r_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_rd_data_count,\n    output                              axi_r_sbiterr,\n    output                              axi_r_dbiterr,\n    output                              axi_r_overflow,\n    output                              axi_r_underflow,\n    output                              axi_r_prog_full,\n    output                              axi_r_prog_empty,\n\n    \n    // AXI Streaming FIFO Related Signals\n    input                               axis_injectsbiterr,\n    input                               axis_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_wr_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_rd_data_count,\n    output                              axis_sbiterr,\n    output                              axis_dbiterr,\n    output                              axis_overflow,\n    output                              axis_underflow,\n    output                              axis_prog_full,\n    output                              axis_prog_empty\n\n    );\n\n    wire                              BACKUP;\n    wire                              BACKUP_MARKER;\n    wire                              CLK;\n    wire                              RST;\n    wire                              SRST;\n    wire                              WR_CLK;\n    wire                              WR_RST;\n    wire                              RD_CLK;\n    wire                              RD_RST;\n    wire [C_DIN_WIDTH-1:0]            DIN;\n    wire                              WR_EN;\n    wire                              RD_EN;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_ASSERT;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_NEGATE;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_ASSERT;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_NEGATE;\n    wire                              INT_CLK;\n    wire                              INJECTDBITERR;\n    wire                              INJECTSBITERR;\n    wire                              SLEEP;\n    wire [C_DOUT_WIDTH-1:0]           DOUT;\n    wire                              FULL;\n    wire                              ALMOST_FULL;\n    wire                              WR_ACK;\n    wire                              OVERFLOW;\n    wire                              EMPTY;\n    wire                              ALMOST_EMPTY;\n    wire                              VALID;\n    wire                              UNDERFLOW;\n    wire [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT;\n    wire [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT;\n    wire                              PROG_FULL;\n    wire                              PROG_EMPTY;\n    wire                              SBITERR;\n    wire                              DBITERR;\n    wire                              WR_RST_BUSY;\n    wire                              RD_RST_BUSY;\n    wire                              M_ACLK;\n    wire                              S_ACLK;\n    wire                              S_ARESETN;\n    wire                              S_ACLK_EN;\n    wire                              M_ACLK_EN;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_AWLEN;\n    wire [3-1:0]                      S_AXI_AWSIZE;\n    wire [2-1:0]                      S_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_AWLOCK;\n    wire [4-1:0]                      S_AXI_AWCACHE;\n    wire [3-1:0]                      S_AXI_AWPROT;\n    wire [4-1:0]                      S_AXI_AWQOS;\n    wire [4-1:0]                      S_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     S_AXI_AWUSER;\n    wire                              S_AXI_AWVALID;\n    wire                              S_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     S_AXI_WSTRB;\n    wire                              S_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      S_AXI_WUSER;\n    wire                              S_AXI_WVALID;\n    wire                              S_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_BID;\n    wire [2-1:0]                      S_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      S_AXI_BUSER;\n    wire                              S_AXI_BVALID;\n    wire                              S_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_AWLEN;\n    wire [3-1:0]                      M_AXI_AWSIZE;\n    wire [2-1:0]                      M_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_AWLOCK;\n    wire [4-1:0]                      M_AXI_AWCACHE;\n    wire [3-1:0]                      M_AXI_AWPROT;\n    wire [4-1:0]                      M_AXI_AWQOS;\n    wire [4-1:0]                      M_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     M_AXI_AWUSER;\n    wire                              M_AXI_AWVALID;\n    wire                              M_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     M_AXI_WSTRB;\n    wire                              M_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      M_AXI_WUSER;\n    wire                              M_AXI_WVALID;\n    wire                              M_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_BID;\n    wire [2-1:0]                      M_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      M_AXI_BUSER;\n    wire                              M_AXI_BVALID;\n    wire                              M_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_ARID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_ARADDR; \n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_ARLEN;\n    wire [3-1:0]                      S_AXI_ARSIZE;\n    wire [2-1:0]                      S_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_ARLOCK;\n    wire [4-1:0]                      S_AXI_ARCACHE;\n    wire [3-1:0]                      S_AXI_ARPROT;\n    wire [4-1:0]                      S_AXI_ARQOS;\n    wire [4-1:0]                      S_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     S_AXI_ARUSER;\n    wire                              S_AXI_ARVALID;\n    wire                              S_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_RID;       \n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_RDATA; \n    wire [2-1:0]                      S_AXI_RRESP;\n    wire                              S_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      S_AXI_RUSER;\n    wire                              S_AXI_RVALID;\n    wire                              S_AXI_RREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_ARID;        \n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_ARADDR;  \n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_ARLEN;\n    wire [3-1:0]                      M_AXI_ARSIZE;\n    wire [2-1:0]                      M_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_ARLOCK;\n    wire [4-1:0]                      M_AXI_ARCACHE;\n    wire [3-1:0]                      M_AXI_ARPROT;\n    wire [4-1:0]                      M_AXI_ARQOS;\n    wire [4-1:0]                      M_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     M_AXI_ARUSER;\n    wire                              M_AXI_ARVALID;\n    wire                              M_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_RID;        \n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_RDATA;  \n    wire [2-1:0]                      M_AXI_RRESP;\n    wire                              M_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      M_AXI_RUSER;\n    wire                              M_AXI_RVALID;\n    wire                              M_AXI_RREADY;\n    wire                              S_AXIS_TVALID;\n    wire                              S_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     S_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     S_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     S_AXIS_TKEEP;\n    wire                              S_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       S_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     S_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     S_AXIS_TUSER;\n    wire                              M_AXIS_TVALID;\n    wire                              M_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     M_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     M_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     M_AXIS_TKEEP;\n    wire                              M_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       M_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     M_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     M_AXIS_TUSER;\n    wire                              AXI_AW_INJECTSBITERR;\n    wire                              AXI_AW_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_RD_DATA_COUNT;\n    wire                              AXI_AW_SBITERR;\n    wire                              AXI_AW_DBITERR;\n    wire                              AXI_AW_OVERFLOW;\n    wire                              AXI_AW_UNDERFLOW;\n    wire                              AXI_AW_PROG_FULL;\n    wire                              AXI_AW_PROG_EMPTY;\n    wire                              AXI_W_INJECTSBITERR;\n    wire                              AXI_W_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_RD_DATA_COUNT;\n    wire                              AXI_W_SBITERR;\n    wire                              AXI_W_DBITERR;\n    wire                              AXI_W_OVERFLOW;\n    wire                              AXI_W_UNDERFLOW;\n    wire                              AXI_W_PROG_FULL;\n    wire                              AXI_W_PROG_EMPTY;\n    wire                              AXI_B_INJECTSBITERR;\n    wire                              AXI_B_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_RD_DATA_COUNT;\n    wire                              AXI_B_SBITERR;\n    wire                              AXI_B_DBITERR;\n    wire                              AXI_B_OVERFLOW;\n    wire                              AXI_B_UNDERFLOW;\n    wire                              AXI_B_PROG_FULL;\n    wire                              AXI_B_PROG_EMPTY;\n    wire                              AXI_AR_INJECTSBITERR;\n    wire                              AXI_AR_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_RD_DATA_COUNT;\n    wire                              AXI_AR_SBITERR;\n    wire                              AXI_AR_DBITERR;\n    wire                              AXI_AR_OVERFLOW;\n    wire                              AXI_AR_UNDERFLOW;\n    wire                              AXI_AR_PROG_FULL;\n    wire                              AXI_AR_PROG_EMPTY;\n    wire                              AXI_R_INJECTSBITERR;\n    wire                              AXI_R_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_RD_DATA_COUNT;\n    wire                              AXI_R_SBITERR;\n    wire                              AXI_R_DBITERR;\n    wire                              AXI_R_OVERFLOW;\n    wire                              AXI_R_UNDERFLOW;\n    wire                              AXI_R_PROG_FULL;\n    wire                              AXI_R_PROG_EMPTY;\n    wire                              AXIS_INJECTSBITERR;\n    wire                              AXIS_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_RD_DATA_COUNT;\n    wire                              AXIS_SBITERR;\n    wire                              AXIS_DBITERR;\n    wire                              AXIS_OVERFLOW;\n    wire                              AXIS_UNDERFLOW;\n    wire                              AXIS_PROG_FULL;\n    wire                              AXIS_PROG_EMPTY;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count_in;\n    wire                              wr_rst_int;\n    wire                              rd_rst_int;\n    wire                              wr_rst_busy_o;\n    wire                              wr_rst_busy_ntve;\n    wire                              wr_rst_busy_axis;\n    wire                              wr_rst_busy_wach;\n    wire                              wr_rst_busy_wdch;\n    wire                              wr_rst_busy_wrch;\n    wire                              wr_rst_busy_rach;\n    wire                              wr_rst_busy_rdch;\n\n\n\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n\n\n\n    // Conventional FIFO Interface Signals\n    assign BACKUP                 = backup;\n    assign BACKUP_MARKER          = backup_marker;\n    assign CLK                    = clk;\n    assign RST                    = rst;\n    assign SRST                   = srst;\n    assign WR_CLK                 = wr_clk;\n    assign WR_RST                 = wr_rst;\n    assign RD_CLK                 = rd_clk;\n    assign RD_RST                 = rd_rst;\n    assign WR_EN                  = wr_en;\n    assign RD_EN                  = rd_en;\n    assign INT_CLK                = int_clk;\n    assign INJECTDBITERR          = injectdbiterr;\n    assign INJECTSBITERR          = injectsbiterr;\n    assign SLEEP                  = sleep;\n    assign full                   = FULL;\n    assign almost_full            = ALMOST_FULL;\n    assign wr_ack                 = WR_ACK;\n    assign overflow               = OVERFLOW;\n    assign empty                  = EMPTY;\n    assign almost_empty           = ALMOST_EMPTY;\n    assign valid                  = VALID;\n    assign underflow              = UNDERFLOW;\n    assign prog_full              = PROG_FULL;\n    assign prog_empty             = PROG_EMPTY;\n    assign sbiterr                = SBITERR;\n    assign dbiterr                = DBITERR;\n//    assign wr_rst_busy            = WR_RST_BUSY | wr_rst_busy_o;\n    assign wr_rst_busy            = wr_rst_busy_o;\n    assign rd_rst_busy            = RD_RST_BUSY;\n    assign M_ACLK                 = m_aclk;\n    assign S_ACLK                 = s_aclk;\n    assign S_ARESETN              = s_aresetn;\n    assign S_ACLK_EN              = s_aclk_en;\n    assign M_ACLK_EN              = m_aclk_en;\n    assign S_AXI_AWVALID          = s_axi_awvalid;\n    assign s_axi_awready          = S_AXI_AWREADY;\n    assign S_AXI_WLAST            = s_axi_wlast;\n    assign S_AXI_WVALID           = s_axi_wvalid;\n    assign s_axi_wready           = S_AXI_WREADY;\n    assign s_axi_bvalid           = S_AXI_BVALID;\n    assign S_AXI_BREADY           = s_axi_bready;\n    assign m_axi_awvalid          = M_AXI_AWVALID;\n    assign M_AXI_AWREADY          = m_axi_awready;\n    assign m_axi_wlast            = M_AXI_WLAST;\n    assign m_axi_wvalid           = M_AXI_WVALID;\n    assign M_AXI_WREADY           = m_axi_wready;\n    assign M_AXI_BVALID           = m_axi_bvalid;\n    assign m_axi_bready           = M_AXI_BREADY;\n    assign S_AXI_ARVALID          = s_axi_arvalid;\n    assign s_axi_arready          = S_AXI_ARREADY;\n    assign s_axi_rlast            = S_AXI_RLAST;\n    assign s_axi_rvalid           = S_AXI_RVALID;\n    assign S_AXI_RREADY           = s_axi_rready;\n    assign m_axi_arvalid          = M_AXI_ARVALID;\n    assign M_AXI_ARREADY          = m_axi_arready;\n    assign M_AXI_RLAST            = m_axi_rlast;\n    assign M_AXI_RVALID           = m_axi_rvalid;\n    assign m_axi_rready           = M_AXI_RREADY;\n    assign S_AXIS_TVALID          = s_axis_tvalid;\n    assign s_axis_tready          = S_AXIS_TREADY;\n    assign S_AXIS_TLAST           = s_axis_tlast;\n    assign m_axis_tvalid          = M_AXIS_TVALID;\n    assign M_AXIS_TREADY          = m_axis_tready;\n    assign m_axis_tlast           = M_AXIS_TLAST;\n    assign AXI_AW_INJECTSBITERR   = axi_aw_injectsbiterr;\n    assign AXI_AW_INJECTDBITERR   = axi_aw_injectdbiterr;\n    assign axi_aw_sbiterr         = AXI_AW_SBITERR;\n    assign axi_aw_dbiterr         = AXI_AW_DBITERR;\n    assign axi_aw_overflow        = AXI_AW_OVERFLOW;\n    assign axi_aw_underflow       = AXI_AW_UNDERFLOW;\n    assign axi_aw_prog_full       = AXI_AW_PROG_FULL;\n    assign axi_aw_prog_empty      = AXI_AW_PROG_EMPTY;\n    assign AXI_W_INJECTSBITERR    = axi_w_injectsbiterr;\n    assign AXI_W_INJECTDBITERR    = axi_w_injectdbiterr;\n    assign axi_w_sbiterr          = AXI_W_SBITERR;\n    assign axi_w_dbiterr          = AXI_W_DBITERR;\n    assign axi_w_overflow         = AXI_W_OVERFLOW;\n    assign axi_w_underflow        = AXI_W_UNDERFLOW;\n    assign axi_w_prog_full        = AXI_W_PROG_FULL;\n    assign axi_w_prog_empty       = AXI_W_PROG_EMPTY;\n    assign AXI_B_INJECTSBITERR    = axi_b_injectsbiterr;\n    assign AXI_B_INJECTDBITERR    = axi_b_injectdbiterr;\n    assign axi_b_sbiterr          = AXI_B_SBITERR;\n    assign axi_b_dbiterr          = AXI_B_DBITERR;\n    assign axi_b_overflow         = AXI_B_OVERFLOW;\n    assign axi_b_underflow        = AXI_B_UNDERFLOW;\n    assign axi_b_prog_full        = AXI_B_PROG_FULL;\n    assign axi_b_prog_empty       = AXI_B_PROG_EMPTY;\n    assign AXI_AR_INJECTSBITERR   = axi_ar_injectsbiterr;\n    assign AXI_AR_INJECTDBITERR   = axi_ar_injectdbiterr;\n    assign axi_ar_sbiterr         = AXI_AR_SBITERR;\n    assign axi_ar_dbiterr         = AXI_AR_DBITERR;\n    assign axi_ar_overflow        = AXI_AR_OVERFLOW;\n    assign axi_ar_underflow       = AXI_AR_UNDERFLOW;\n    assign axi_ar_prog_full       = AXI_AR_PROG_FULL;\n    assign axi_ar_prog_empty      = AXI_AR_PROG_EMPTY;\n    assign AXI_R_INJECTSBITERR    = axi_r_injectsbiterr;\n    assign AXI_R_INJECTDBITERR    = axi_r_injectdbiterr;\n    assign axi_r_sbiterr          = AXI_R_SBITERR;\n    assign axi_r_dbiterr          = AXI_R_DBITERR;\n    assign axi_r_overflow         = AXI_R_OVERFLOW;\n    assign axi_r_underflow        = AXI_R_UNDERFLOW;\n    assign axi_r_prog_full        = AXI_R_PROG_FULL;\n    assign axi_r_prog_empty       = AXI_R_PROG_EMPTY;\n    assign AXIS_INJECTSBITERR     = axis_injectsbiterr;\n    assign AXIS_INJECTDBITERR     = axis_injectdbiterr;\n    assign axis_sbiterr           = AXIS_SBITERR;\n    assign axis_dbiterr           = AXIS_DBITERR;\n    assign axis_overflow          = AXIS_OVERFLOW;\n    assign axis_underflow         = AXIS_UNDERFLOW;\n    assign axis_prog_full         = AXIS_PROG_FULL;\n    assign axis_prog_empty        = AXIS_PROG_EMPTY;\n\n\n    assign DIN                       = din;\n    assign PROG_EMPTY_THRESH         = prog_empty_thresh;\n    assign PROG_EMPTY_THRESH_ASSERT  = prog_empty_thresh_assert;\n    assign PROG_EMPTY_THRESH_NEGATE  = prog_empty_thresh_negate;\n    assign PROG_FULL_THRESH          = prog_full_thresh;\n    assign PROG_FULL_THRESH_ASSERT   = prog_full_thresh_assert;\n    assign PROG_FULL_THRESH_NEGATE   = prog_full_thresh_negate;\n    assign dout                      = DOUT;\n    assign data_count                = DATA_COUNT;\n    assign rd_data_count             = RD_DATA_COUNT;\n    assign wr_data_count             = WR_DATA_COUNT;\n    assign S_AXI_AWID                = s_axi_awid;\n    assign S_AXI_AWADDR              = s_axi_awaddr;\n    assign S_AXI_AWLEN               = s_axi_awlen;\n    assign S_AXI_AWSIZE              = s_axi_awsize;\n    assign S_AXI_AWBURST             = s_axi_awburst;\n    assign S_AXI_AWLOCK              = s_axi_awlock;\n    assign S_AXI_AWCACHE             = s_axi_awcache;\n    assign S_AXI_AWPROT              = s_axi_awprot;\n    assign S_AXI_AWQOS               = s_axi_awqos;\n    assign S_AXI_AWREGION            = s_axi_awregion;\n    assign S_AXI_AWUSER              = s_axi_awuser;\n    assign S_AXI_WID                 = s_axi_wid;\n    assign S_AXI_WDATA               = s_axi_wdata;\n    assign S_AXI_WSTRB               = s_axi_wstrb;\n    assign S_AXI_WUSER               = s_axi_wuser;\n    assign s_axi_bid                 = S_AXI_BID;\n    assign s_axi_bresp               = S_AXI_BRESP;\n    assign s_axi_buser               = S_AXI_BUSER;\n    assign m_axi_awid                = M_AXI_AWID;\n    assign m_axi_awaddr              = M_AXI_AWADDR;\n    assign m_axi_awlen               = M_AXI_AWLEN;\n    assign m_axi_awsize              = M_AXI_AWSIZE;\n    assign m_axi_awburst             = M_AXI_AWBURST;\n    assign m_axi_awlock              = M_AXI_AWLOCK;\n    assign m_axi_awcache             = M_AXI_AWCACHE;\n    assign m_axi_awprot              = M_AXI_AWPROT;\n    assign m_axi_awqos               = M_AXI_AWQOS;\n    assign m_axi_awregion            = M_AXI_AWREGION;\n    assign m_axi_awuser              = M_AXI_AWUSER;\n    assign m_axi_wid                 = M_AXI_WID;\n    assign m_axi_wdata               = M_AXI_WDATA;\n    assign m_axi_wstrb               = M_AXI_WSTRB;\n    assign m_axi_wuser               = M_AXI_WUSER;\n    assign M_AXI_BID                 = m_axi_bid;\n    assign M_AXI_BRESP               = m_axi_bresp;\n    assign M_AXI_BUSER               = m_axi_buser;\n    assign S_AXI_ARID                = s_axi_arid;\n    assign S_AXI_ARADDR              = s_axi_araddr; \n    assign S_AXI_ARLEN               = s_axi_arlen;\n    assign S_AXI_ARSIZE              = s_axi_arsize;\n    assign S_AXI_ARBURST             = s_axi_arburst;\n    assign S_AXI_ARLOCK              = s_axi_arlock;\n    assign S_AXI_ARCACHE             = s_axi_arcache;\n    assign S_AXI_ARPROT              = s_axi_arprot;\n    assign S_AXI_ARQOS               = s_axi_arqos;\n    assign S_AXI_ARREGION            = s_axi_arregion;\n    assign S_AXI_ARUSER              = s_axi_aruser;\n    assign s_axi_rid                 = S_AXI_RID;\n    assign s_axi_rdata               = S_AXI_RDATA;\n    assign s_axi_rresp               = S_AXI_RRESP;\n    assign s_axi_ruser               = S_AXI_RUSER;\n    assign m_axi_arid                = M_AXI_ARID;        \n    assign m_axi_araddr              = M_AXI_ARADDR;  \n    assign m_axi_arlen               = M_AXI_ARLEN;\n    assign m_axi_arsize              = M_AXI_ARSIZE;\n    assign m_axi_arburst             = M_AXI_ARBURST;\n    assign m_axi_arlock              = M_AXI_ARLOCK;\n    assign m_axi_arcache             = M_AXI_ARCACHE;\n    assign m_axi_arprot              = M_AXI_ARPROT;\n    assign m_axi_arqos               = M_AXI_ARQOS;\n    assign m_axi_arregion            = M_AXI_ARREGION;\n    assign m_axi_aruser              = M_AXI_ARUSER;\n    assign M_AXI_RID                 = m_axi_rid;        \n    assign M_AXI_RDATA               = m_axi_rdata;  \n    assign M_AXI_RRESP               = m_axi_rresp;\n    assign M_AXI_RUSER               = m_axi_ruser;\n    assign S_AXIS_TDATA              = s_axis_tdata;\n    assign S_AXIS_TSTRB              = s_axis_tstrb;\n    assign S_AXIS_TKEEP              = s_axis_tkeep;\n    assign S_AXIS_TID                = s_axis_tid;\n    assign S_AXIS_TDEST              = s_axis_tdest;\n    assign S_AXIS_TUSER              = s_axis_tuser;\n    assign m_axis_tdata              = M_AXIS_TDATA;\n    assign m_axis_tstrb              = M_AXIS_TSTRB;\n    assign m_axis_tkeep              = M_AXIS_TKEEP;\n    assign m_axis_tid                = M_AXIS_TID;\n    assign m_axis_tdest              = M_AXIS_TDEST;\n    assign m_axis_tuser              = M_AXIS_TUSER;\n    assign AXI_AW_PROG_FULL_THRESH   = axi_aw_prog_full_thresh;\n    assign AXI_AW_PROG_EMPTY_THRESH  = axi_aw_prog_empty_thresh;\n    assign axi_aw_data_count         = AXI_AW_DATA_COUNT;\n    assign axi_aw_wr_data_count      = AXI_AW_WR_DATA_COUNT;\n    assign axi_aw_rd_data_count      = AXI_AW_RD_DATA_COUNT;\n    assign AXI_W_PROG_FULL_THRESH    = axi_w_prog_full_thresh;\n    assign AXI_W_PROG_EMPTY_THRESH   = axi_w_prog_empty_thresh;\n    assign axi_w_data_count          = AXI_W_DATA_COUNT;\n    assign axi_w_wr_data_count       = AXI_W_WR_DATA_COUNT;\n    assign axi_w_rd_data_count       = AXI_W_RD_DATA_COUNT;\n    assign AXI_B_PROG_FULL_THRESH    = axi_b_prog_full_thresh;\n    assign AXI_B_PROG_EMPTY_THRESH   = axi_b_prog_empty_thresh;\n    assign axi_b_data_count          = AXI_B_DATA_COUNT;\n    assign axi_b_wr_data_count       = AXI_B_WR_DATA_COUNT;\n    assign axi_b_rd_data_count       = AXI_B_RD_DATA_COUNT;\n    assign AXI_AR_PROG_FULL_THRESH   = axi_ar_prog_full_thresh;\n    assign AXI_AR_PROG_EMPTY_THRESH  = axi_ar_prog_empty_thresh;\n    assign axi_ar_data_count         = AXI_AR_DATA_COUNT;\n    assign axi_ar_wr_data_count      = AXI_AR_WR_DATA_COUNT;\n    assign axi_ar_rd_data_count      = AXI_AR_RD_DATA_COUNT;\n    assign AXI_R_PROG_FULL_THRESH    = axi_r_prog_full_thresh;\n    assign AXI_R_PROG_EMPTY_THRESH   = axi_r_prog_empty_thresh;\n    assign axi_r_data_count          = AXI_R_DATA_COUNT;\n    assign axi_r_wr_data_count       = AXI_R_WR_DATA_COUNT;\n    assign axi_r_rd_data_count       = AXI_R_RD_DATA_COUNT;\n    assign AXIS_PROG_FULL_THRESH     = axis_prog_full_thresh;\n    assign AXIS_PROG_EMPTY_THRESH    = axis_prog_empty_thresh;\n    assign axis_data_count           = AXIS_DATA_COUNT;\n    assign axis_wr_data_count        = AXIS_WR_DATA_COUNT;\n    assign axis_rd_data_count        = AXIS_RD_DATA_COUNT;\n\n\n  generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_COMMON_CLOCK \t\t(C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DATA_COUNT_WIDTH\t\t(C_DATA_COUNT_WIDTH),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH),\n        .C_DOUT_RST_VAL\t\t\t(C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),\n        .C_DOUT_WIDTH\t\t\t(C_DOUT_WIDTH),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n        .C_HAS_ALMOST_EMPTY\t\t(C_HAS_ALMOST_EMPTY),\n        .C_HAS_ALMOST_FULL\t\t(C_HAS_ALMOST_FULL),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_DATA_COUNT\t\t(C_HAS_DATA_COUNT),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_HAS_RD_DATA_COUNT\t\t(C_HAS_RD_DATA_COUNT),\n        .C_HAS_RD_RST\t\t\t(C_HAS_RD_RST),\n        .C_HAS_RST\t\t\t(C_HAS_RST),\n        .C_HAS_SRST\t\t\t(C_HAS_SRST),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_HAS_VALID\t\t\t(C_HAS_VALID),\n        .C_HAS_WR_ACK\t\t\t(C_HAS_WR_ACK),\n        .C_HAS_WR_DATA_COUNT\t\t(C_HAS_WR_DATA_COUNT),\n        .C_HAS_WR_RST\t\t\t(C_HAS_WR_RST),\n        .C_IMPLEMENTATION_TYPE\t\t(C_IMPLEMENTATION_TYPE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_MEMORY_TYPE\t\t\t(C_MEMORY_TYPE),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n        .C_PRELOAD_LATENCY\t\t(C_PRELOAD_LATENCY),\n        .C_PRELOAD_REGS\t\t\t(C_PRELOAD_REGS),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL),\n        .C_PROG_EMPTY_THRESH_NEGATE_VAL\t(C_PROG_EMPTY_THRESH_NEGATE_VAL),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL),\n        .C_PROG_FULL_THRESH_NEGATE_VAL\t(C_PROG_FULL_THRESH_NEGATE_VAL),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_RD_DATA_COUNT_WIDTH),\n        .C_RD_DEPTH\t\t\t(C_RD_DEPTH),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_RD_PNTR_WIDTH\t\t(C_RD_PNTR_WIDTH),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n        .C_USE_ECC                      (C_USE_ECC),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_EN_SAFETY_CKT\t\t(C_EN_SAFETY_CKT),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_USE_FWFT_DATA_COUNT\t\t(C_USE_FWFT_DATA_COUNT),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_DATA_COUNT_WIDTH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (C_ENABLE_RST_SYNC),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE),\n        .C_AXI_TYPE                     (C_AXI_TYPE),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE)\n      )\n    fifo_generator_v13_2_5_conv_dut\n      (\n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .CLK                      (CLK),\n        .RST                      (RST),\n        .SRST                     (SRST),\n        .WR_CLK                   (WR_CLK),\n        .WR_RST                   (WR_RST),\n        .RD_CLK                   (RD_CLK),\n        .RD_RST                   (RD_RST),\n        .DIN                      (DIN),\n        .WR_EN                    (WR_EN),\n        .RD_EN                    (RD_EN),\n        .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),\n        .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),\n        .PROG_FULL_THRESH         (PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),\n        .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),\n        .INT_CLK                  (INT_CLK),\n        .INJECTDBITERR            (INJECTDBITERR), \n        .INJECTSBITERR            (INJECTSBITERR),\n  \n        .DOUT                     (DOUT),\n        .FULL                     (FULL),\n        .ALMOST_FULL              (ALMOST_FULL),\n        .WR_ACK                   (WR_ACK),\n        .OVERFLOW                 (OVERFLOW),\n        .EMPTY                    (EMPTY),\n        .ALMOST_EMPTY             (ALMOST_EMPTY),\n        .VALID                    (VALID),\n        .UNDERFLOW                (UNDERFLOW),\n        .DATA_COUNT               (DATA_COUNT),\n        .RD_DATA_COUNT            (RD_DATA_COUNT),\n        .WR_DATA_COUNT            (wr_data_count_in),\n        .PROG_FULL                (PROG_FULL),\n        .PROG_EMPTY               (PROG_EMPTY),\n        .SBITERR                  (SBITERR),\n        .DBITERR                  (DBITERR),\n        .wr_rst_busy_o            (wr_rst_busy_o),\n        .wr_rst_busy              (wr_rst_busy_i),\n        .rd_rst_busy              (rd_rst_busy),\n        .wr_rst_i_out             (wr_rst_int),\n        .rd_rst_i_out             (rd_rst_int)\n       );\n  end endgenerate\n\n\n\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n  localparam C_AXI_SIZE_WIDTH   = 3;\n  localparam C_AXI_BURST_WIDTH  = 2;\n  localparam C_AXI_CACHE_WIDTH  = 4;\n  localparam C_AXI_PROT_WIDTH   = 3;\n  localparam C_AXI_QOS_WIDTH    = 4;\n  localparam C_AXI_REGION_WIDTH = 4;\n  localparam C_AXI_BRESP_WIDTH  = 2;\n  localparam C_AXI_RRESP_WIDTH  = 2;\n\n  localparam IS_AXI_STREAMING  = C_INTERFACE_TYPE == 1 ? 1 : 0;\n  localparam TDATA_OFFSET      = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;\n  localparam TSTRB_OFFSET      = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;\n  localparam TKEEP_OFFSET      = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;\n  localparam TID_OFFSET        = C_HAS_AXIS_TID   == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;\n  localparam TDEST_OFFSET      = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;\n  localparam TUSER_OFFSET      = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;\n  localparam LOG_DEPTH_AXIS    = find_log2(C_WR_DEPTH_AXIS); \n  localparam LOG_WR_DEPTH      = find_log2(C_WR_DEPTH); \n\n\n  function [LOG_DEPTH_AXIS-1:0] bin2gray;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      begin\n         bin2gray = x ^ (x>>1);\n      end\n   endfunction\n\n  function [LOG_DEPTH_AXIS-1:0] gray2bin;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      integer                i;\n      begin\n         gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];\n         for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin\n            gray2bin[i] =  gray2bin[i+1] ^ x[i];\n         end\n      end\n   endfunction\n\nwire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;\nwire  [LOG_WR_DEPTH-1 : 0]  w_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;\nreg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;\nwire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;\nwire [LOG_WR_DEPTH : 0] r_inv_pad;\nwire [LOG_WR_DEPTH-1 : 0] d_cnt;\nreg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;\nreg adj_w_cnt_rd_pad_0 = 0;\nreg r_inv_pad_0 = 0;\n\n\n   genvar l;\n\n   generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (LOG_WR_DEPTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_int), \n         .CLK      (RD_CLK), \n         .DIN      (w_q[l-1]), \n         .DOUT     (w_q[l])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter\n    assign wr_eop_ad = WR_EN & !(FULL);\n    assign rd_eop_ad = RD_EN & !(EMPTY);\n\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt    <= 1'b0;\n      else if (wr_eop_ad)\n        w_cnt    <= w_cnt + 1;\n    end\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt_gc    <= 1'b0;\n      else \n        w_cnt_gc    <= bin2gray(w_cnt);\n    end\n\n\n    assign  w_q[0]  = w_cnt_gc;\n    assign  w_cnt_gc_asreg_last       = w_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        w_cnt_rd    <= 1'b0;\n      else \n        w_cnt_rd    <= gray2bin(w_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        r_cnt    <= 1'b0;\n      else if (rd_eop_ad)\n        r_cnt    <= r_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;\n   assign r_inv_pad[LOG_WR_DEPTH : 1]        = ~r_cnt;\n   assign adj_w_cnt_rd_pad[0]                = adj_w_cnt_rd_pad_0;\n   assign r_inv_pad[0]                       = r_inv_pad_0;\n\n\n  always @ ( rd_eop_ad )\n    begin\n      if (!rd_eop_ad) begin\n        adj_w_cnt_rd_pad_0    <= 1'b1;\n        r_inv_pad_0           <= 1'b1;\n      end else begin \n        adj_w_cnt_rd_pad_0    <= 1'b0;\n        r_inv_pad_0           <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        d_cnt_pad    <= 1'b0;\n      else \n        d_cnt_pad    <= adj_w_cnt_rd_pad + r_inv_pad ;\n    end\n\n   assign  d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;\n   assign  WR_DATA_COUNT = d_cnt;\n\n  end endgenerate // fifo_ic_adapter\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter\n   assign  WR_DATA_COUNT = wr_data_count_in;\n\n  end endgenerate // fifo_icn_adapter\n\n\n\n  wire                          inverted_reset = ~S_ARESETN;\n  wire                          axi_rs_rst;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_din          ;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_dout         ;\n  wire                          axis_full         ;\n  wire                          axis_almost_full  ;\n  wire                          axis_empty        ;\n  wire                          axis_s_axis_tready;\n  wire                          axis_m_axis_tvalid;\n  wire                          axis_wr_en        ;\n  wire                          axis_rd_en        ;\n  wire                          axis_we           ;\n  wire                          axis_re           ;\n  wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;\n  reg                           axis_pkt_read = 1'b0;\n  wire                          axis_rd_rst;\n  wire                          axis_wr_rst;\n\n  generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||\n               C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst\n      reg                           rst_d1 = 0        ;\n      reg                           rst_d2 = 0        ;\n      reg [3:0]                    axi_rst = 4'h0     ;\n      always @ (posedge inverted_reset or posedge S_ACLK) begin\n        if (inverted_reset) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          axi_rst        <= 4'hf;\n        end else begin\n          rst_d1         <= #`TCQ 1'b0;\n          rst_d2         <= #`TCQ rst_d1;\n          axi_rst        <= #`TCQ {axi_rst[2:0],1'b0};\n        end\n      end\n\n      assign axi_rs_rst = axi_rst[3];//rst_d2;\n  end endgenerate // gaxi_rs_rst\n\n  generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming\n\n    // Write protection when almost full or prog_full is high\n    assign axis_we    = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : \n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign axis_re    = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :\n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? axis_we & S_ACLK_EN : axis_we;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE               (C_INTERFACE_TYPE),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 2  || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_AXIS),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_AXIS),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),\n        .C_USE_ECC                      (C_USE_ECC_AXIS),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_AXIS),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_axis_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (axis_wr_en),\n        .RD_EN                    (axis_rd_en),\n        .PROG_FULL_THRESH         (AXIS_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXIS_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .INJECTDBITERR            (AXIS_INJECTDBITERR), \n        .INJECTSBITERR            (AXIS_INJECTSBITERR),\n  \n        .DIN                      (axis_din),\n        .DOUT                     (axis_dout),\n        .FULL                     (axis_full),\n        .EMPTY                    (axis_empty),\n        .ALMOST_FULL              (axis_almost_full),\n        .PROG_FULL                (AXIS_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXIS_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (AXIS_OVERFLOW),\n        .VALID                    (),\n        .UNDERFLOW                (AXIS_UNDERFLOW),\n        .DATA_COUNT               (axis_dc),\n        .RD_DATA_COUNT            (AXIS_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXIS_WR_DATA_COUNT),\n        .SBITERR                  (AXIS_SBITERR),\n        .DBITERR                  (AXIS_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_axis),\n        .rd_rst_busy              (rd_rst_busy_axis),\n        .wr_rst_i_out             (axis_wr_rst),\n        .rd_rst_i_out             (axis_rd_rst),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign axis_s_axis_tready    = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;\n    assign axis_m_axis_tvalid    = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;\n    assign S_AXIS_TREADY         = axis_s_axis_tready;\n    assign M_AXIS_TVALID         = axis_m_axis_tvalid;\n\n  end endgenerate // axi_streaming\n\n  wire axis_wr_eop;\n  reg  axis_wr_eop_d1 = 1'b0;\n  wire axis_rd_eop;\n  integer  axis_pkt_cnt;\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)\n        axis_pkt_read    <= 1'b0;\n      else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_wr_eop_d1    <= 1'b0;\n      else\n        axis_wr_eop_d1   <= axis_wr_eop;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_cnt    <= 0;\n      else if (axis_wr_eop_d1 && ~axis_rd_eop)\n        axis_pkt_cnt    <= axis_pkt_cnt + 1;\n      else if (axis_rd_eop && ~axis_wr_eop_d1)\n        axis_pkt_cnt    <= axis_pkt_cnt - 1;\n    end\n  end endgenerate // gaxis_pkt_fifo_cc\n\n\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;\nwire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;\nwire axis_rd_has_rst;\nwire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;\nwire  [LOG_DEPTH_AXIS-1 : 0]  wpkt_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;\nwire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;\nwire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;\nwire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;\nwire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;\nreg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;\nreg adj_axis_wpkt_cnt_rd_pad_0 = 0;\nreg rpkt_inv_pad_0 = 0;\nwire axis_af_rd ;\n\ngenerate if (C_HAS_RST == 1) begin : rst_blk_has\n  assign axis_rd_has_rst = axis_rd_rst;\nend endgenerate //rst_blk_has\n\ngenerate if (C_HAS_RST == 0) begin :rst_blk_no\n  assign axis_rd_has_rst = 1'b0;\nend endgenerate //rst_blk_no\n\n   genvar i;\n\n   generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (LOG_DEPTH_AXIS)\n        )\n     rd_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (wpkt_q[i-1]), \n         .DOUT     (wpkt_q[i])\n        );\n \n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (1)\n        )\n     wr_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (axis_af_q[i-1]), \n         .DOUT     (axis_af_q[i])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (diff_pkt_cnt == 1))\n        axis_pkt_read    <= 1'b0;\n      else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt    <= 1'b0;\n      else if (axis_wr_eop)\n        axis_wpkt_cnt    <= axis_wpkt_cnt + 1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt_gc    <= 1'b0;\n      else \n        axis_wpkt_cnt_gc    <= bin2gray(axis_wpkt_cnt);\n    end\n\n\n    assign  wpkt_q[0]  = axis_wpkt_cnt_gc;\n    assign  axis_wpkt_cnt_gc_asreg_last       = wpkt_q[C_SYNCHRONIZER_STAGE];\n    assign  axis_af_q[0]                      = axis_almost_full;\n    //assign  axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];\n    assign  axis_af_rd                        = axis_af_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_wpkt_cnt_rd    <= 1'b0;\n      else \n        axis_wpkt_cnt_rd    <= gray2bin(axis_wpkt_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_rpkt_cnt    <= 1'b0;\n      else if (axis_rd_eop)\n        axis_rpkt_cnt    <= axis_rpkt_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;\n   assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1]             = ~axis_rpkt_cnt;\n   assign adj_axis_wpkt_cnt_rd_pad[0]                                = adj_axis_wpkt_cnt_rd_pad_0;\n   assign rpkt_inv_pad[0]                                            = rpkt_inv_pad_0;\n\n\n  always @ ( axis_rd_eop )\n    begin\n      if (!axis_rd_eop) begin\n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b1;\n        rpkt_inv_pad_0                <= 1'b1;\n      end else begin \n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b0;\n        rpkt_inv_pad_0                <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        diff_pkt_cnt_pad    <= 1'b0;\n      else \n        diff_pkt_cnt_pad    <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;\n    end\n\n   assign  diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;\n\n\n\n\n\n   end endgenerate // gaxis_pkt_fifo_ic\n\n\n\n\n  // Generate the accurate data count for axi stream packet fifo configuration\n  reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_dc_pkt_fifo <= 0;\n      else if (axis_wr_en && (~axis_rd_en))\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;\n      else if (~axis_wr_en && axis_rd_en)\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;\n    end\n    assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;\n  end endgenerate // gdc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt\n    assign AXIS_DATA_COUNT = 0;\n  end endgenerate // gndc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc\n    assign AXIS_DATA_COUNT = axis_dc;\n  end endgenerate // gdc\n\n  // Register Slice for Write Address Channel\n  generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_AXIS),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_AXIS)\n            )\n    axis_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (axis_din),\n          .S_VALID                   (axis_wr_en),\n          .S_READY                   (S_AXIS_TREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (axis_dout),\n          .M_VALID                   (M_AXIS_TVALID),\n          .M_READY                   (axis_rd_en)\n          );\n  end endgenerate // gaxis_reg_slice\n\n\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata\n    assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;\n    assign M_AXIS_TDATA   = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb\n    assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;\n    assign M_AXIS_TSTRB   = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep\n    assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;\n    assign M_AXIS_TKEEP   = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid\n    assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;\n    assign M_AXIS_TID     = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest\n    assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;\n    assign M_AXIS_TDEST   = axis_dout[TID_OFFSET-1:TDEST_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser\n    assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;\n    assign M_AXIS_TUSER   = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast\n    assign axis_din[0] = S_AXIS_TLAST;\n    assign M_AXIS_TLAST   = axis_dout[0];\n  end endgenerate\n\n  //###########################################################################\n  //  AXI FULL Write Channel (axi_write_channel)\n  //###########################################################################\n\n  localparam IS_AXI_FULL       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;\n  localparam IS_AXI_LITE       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;\n\n  localparam IS_AXI_FULL_WACH  = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WDCH  = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WRCH  = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RACH  = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RDCH  = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_AXI_LITE_WACH  = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WDCH  = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WRCH  = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RACH  = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RDCH  = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_WR_ADDR_CH     = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;\n  localparam IS_WR_DATA_CH     = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;\n  localparam IS_WR_RESP_CH     = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;\n  localparam IS_RD_ADDR_CH     = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;\n  localparam IS_RD_DATA_CH     = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;\n\n  localparam AWID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;\n  localparam AWADDR_OFFSET     = AWID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam AWLEN_OFFSET      = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;\n  localparam AWSIZE_OFFSET     = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;\n  localparam AWBURST_OFFSET    = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;\n  localparam AWLOCK_OFFSET     = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;\n  localparam AWCACHE_OFFSET    = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;\n  localparam AWPROT_OFFSET     = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam AWQOS_OFFSET      = AWPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam AWREGION_OFFSET   = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;\n  localparam AWUSER_OFFSET     = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;\n\n  localparam WID_OFFSET        = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;\n  localparam WDATA_OFFSET      = WID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam WSTRB_OFFSET      = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;\n  localparam WUSER_OFFSET      = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;\n\n  localparam BID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;\n  localparam BRESP_OFFSET      = BID_OFFSET - C_AXI_BRESP_WIDTH;\n  localparam BUSER_OFFSET      = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;\n\n\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_din          ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout         ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout_pkt     ;\n  wire                          wach_full         ;\n  wire                          wach_almost_full  ;\n  wire                          wach_prog_full    ;\n  wire                          wach_empty        ;\n  wire                          wach_almost_empty ;\n  wire                          wach_prog_empty   ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_din          ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_dout         ;\n  wire                          wdch_full         ;\n  wire                          wdch_almost_full  ;\n  wire                          wdch_prog_full    ;\n  wire                          wdch_empty        ;\n  wire                          wdch_almost_empty ;\n  wire                          wdch_prog_empty   ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_din          ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_dout         ;\n  wire                          wrch_full         ;\n  wire                          wrch_almost_full  ;\n  wire                          wrch_prog_full    ;\n  wire                          wrch_empty        ;\n  wire                          wrch_almost_empty ;\n  wire                          wrch_prog_empty   ;\n  wire                          axi_aw_underflow_i;\n  wire                          axi_w_underflow_i ;\n  wire                          axi_b_underflow_i ;\n  wire                          axi_aw_overflow_i ;\n  wire                          axi_w_overflow_i  ;\n  wire                          axi_b_overflow_i  ;\n  wire                          axi_wr_underflow_i;\n  wire                          axi_wr_overflow_i ;\n  wire                          wach_s_axi_awready;\n  wire                          wach_m_axi_awvalid;\n  wire                          wach_wr_en        ;\n  wire                          wach_rd_en        ;\n  wire                          wdch_s_axi_wready ;\n  wire                          wdch_m_axi_wvalid ;\n  wire                          wdch_wr_en        ;\n  wire                          wdch_rd_en        ;\n  wire                          wrch_s_axi_bvalid ;\n  wire                          wrch_m_axi_bready ;\n  wire                          wrch_wr_en        ;\n  wire                          wrch_rd_en        ;\n  wire                          txn_count_up      ;\n  wire                          txn_count_down    ;\n  wire                          awvalid_en        ;\n  wire                          awvalid_pkt       ;\n  wire                          awready_pkt       ;\n  integer                       wr_pkt_count      ;\n  wire                          wach_we           ;\n  wire                          wach_re           ;\n  wire                          wdch_we           ;\n  wire                          wdch_re           ;\n  wire                          wrch_we           ;\n  wire                          wrch_re           ;\n\n  generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel\n    // Write protection when almost full or prog_full is high\n    assign wach_we    = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wach_re    = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        wach_m_axi_awvalid & awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY && wach_m_axi_awvalid :\n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY : 1'b0;\n    assign wach_wr_en = (C_HAS_SLAVE_CE == 1)  ? wach_we & S_ACLK_EN : wach_we;\n    assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 2  || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),\n        .C_USE_ECC                      (C_USE_ECC_WACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wach_wr_en),\n        .RD_EN                    (wach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AW_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AW_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AW_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AW_INJECTSBITERR),\n  \n        .DIN                      (wach_din),\n        .DOUT                     (wach_dout_pkt),\n        .FULL                     (wach_full),\n        .EMPTY                    (wach_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_AW_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_AW_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_aw_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_aw_underflow_i),\n        .DATA_COUNT               (AXI_AW_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AW_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AW_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AW_SBITERR),\n        .DBITERR                  (AXI_AW_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wach),\n        .rd_rst_busy              (rd_rst_busy_wach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wach_s_axi_awready    = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;\n    assign wach_m_axi_awvalid   = ~wach_empty;\n    assign S_AXI_AWREADY        = wach_s_axi_awready;\n\n    assign AXI_AW_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;\n    assign AXI_AW_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_aw_overflow_i  : 0;\n\n  end endgenerate // axi_write_address_channel\n\n  // Register Slice for Write Address Channel\n  generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WACH)\n            )\n    wach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_din),\n          .S_VALID                   (S_AXI_AWVALID),\n          .S_READY                   (S_AXI_AWREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n  end endgenerate // gwach_reg_slice\n  \n  generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (1)\n            )\n    wach_pkt_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_dout_pkt),\n          .S_VALID                   (awvalid_pkt),\n          .S_READY                   (awready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n\n    assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;\n\n    assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; \n    assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset == 1) begin\n\twr_pkt_count <= 0;\n      end else begin\n\tif(txn_count_up == 1 && txn_count_down == 0) begin\n\t  wr_pkt_count <= wr_pkt_count + 1;\n\tend else if(txn_count_up == 0 && txn_count_down == 1) begin\n\t  wr_pkt_count <= wr_pkt_count - 1;\n\tend\n      end\n    end //Always end\n    assign awvalid_en = (wr_pkt_count > 0)?1:0;\n  end endgenerate\n  \n  generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr\n    assign awvalid_en    = 1;    \n    assign wach_dout     = wach_dout_pkt;\n    assign M_AXI_AWVALID = wach_m_axi_awvalid;\n  end\n  endgenerate\n\n\n\n  generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel\n    // Write protection when almost full or prog_full is high\n    assign wdch_we    = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wdch_re    = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;\n    assign wdch_wr_en = (C_HAS_SLAVE_CE == 1)  ? wdch_we & S_ACLK_EN : wdch_we;\n    assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;\n\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 2  || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),\n        .C_USE_ECC                      (C_USE_ECC_WDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wdch_wr_en),\n        .RD_EN                    (wdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_W_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_W_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_W_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_W_INJECTSBITERR),\n  \n        .DIN                      (wdch_din),\n        .DOUT                     (wdch_dout),\n        .FULL                     (wdch_full),\n        .EMPTY                    (wdch_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_W_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_W_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_w_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_w_underflow_i),\n        .DATA_COUNT               (AXI_W_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_W_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_W_WR_DATA_COUNT),\n        .SBITERR                  (AXI_W_SBITERR),\n        .DBITERR                  (AXI_W_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wdch),\n        .rd_rst_busy              (rd_rst_busy_wdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wdch_s_axi_wready     = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;\n    assign wdch_m_axi_wvalid = ~wdch_empty;\n    assign S_AXI_WREADY      = wdch_s_axi_wready;\n    assign M_AXI_WVALID      = wdch_m_axi_wvalid;\n\n    assign AXI_W_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i  : 0;\n    assign AXI_W_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_w_overflow_i   : 0;\n\n  end endgenerate // axi_write_data_channel\n\n  // Register Slice for Write Data Channel\n  generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WDCH)\n            )\n    wdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wdch_din),\n          .S_VALID                   (S_AXI_WVALID),\n          .S_READY                   (S_AXI_WREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wdch_dout),\n          .M_VALID                   (M_AXI_WVALID),\n          .M_READY                   (M_AXI_WREADY)\n          );\n  end endgenerate // gwdch_reg_slice\n\n  generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel\n    // Write protection when almost full or prog_full is high\n    assign wrch_we    = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wrch_re    = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;\n    assign wrch_wr_en = (C_HAS_MASTER_CE == 1)  ? wrch_we & M_ACLK_EN : wrch_we;\n    assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 2  || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WRCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WRCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),\n        .C_USE_ECC                      (C_USE_ECC_WRCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WRCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WRCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wrch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wrch_wr_en),\n        .RD_EN                    (wrch_rd_en),\n        .PROG_FULL_THRESH         (AXI_B_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_B_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .INJECTDBITERR            (AXI_B_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_B_INJECTSBITERR),\n  \n        .DIN                      (wrch_din),\n        .DOUT                     (wrch_dout),\n        .FULL                     (wrch_full),\n        .EMPTY                    (wrch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_B_PROG_FULL),\n        .PROG_EMPTY               (AXI_B_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_b_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_b_underflow_i),\n        .DATA_COUNT               (AXI_B_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_B_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_B_WR_DATA_COUNT),\n        .SBITERR                  (AXI_B_SBITERR),\n        .DBITERR                  (AXI_B_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wrch),\n        .rd_rst_busy              (rd_rst_busy_wrch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wrch_s_axi_bvalid = ~wrch_empty;\n    assign wrch_m_axi_bready     = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;\n    assign S_AXI_BVALID      = wrch_s_axi_bvalid;\n    assign M_AXI_BREADY      = wrch_m_axi_bready;\n\n    assign AXI_B_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i  : 0;\n    assign AXI_B_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_b_overflow_i   : 0;\n  end endgenerate // axi_write_resp_channel\n\n  // Register Slice for Write Response Channel\n  generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WRCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WRCH)\n            )\n    wrch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wrch_din),\n          .S_VALID                   (M_AXI_BVALID),\n          .S_READY                   (M_AXI_BREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wrch_dout),\n          .M_VALID                   (S_AXI_BVALID),\n          .M_READY                   (S_AXI_BREADY)\n          );\n  end endgenerate // gwrch_reg_slice\n\n\n    assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW  == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;\n    assign axi_wr_overflow_i  = C_USE_COMMON_OVERFLOW   == 1 ? (axi_aw_overflow_i  || axi_w_overflow_i  || axi_b_overflow_i)  : 0;\n\n  generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output\n    assign M_AXI_AWADDR    = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];    \n    assign M_AXI_AWLEN     = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];    \n    assign M_AXI_AWSIZE    = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];    \n    assign M_AXI_AWBURST   = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];    \n    assign M_AXI_AWLOCK    = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];    \n    assign M_AXI_AWCACHE   = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];    \n    assign M_AXI_AWQOS     = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];    \n    assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET]    = S_AXI_AWADDR;\n    assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET]   = S_AXI_AWLEN;\n    assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET]   = S_AXI_AWSIZE;\n    assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;\n    assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;\n    assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;\n    assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;\n    assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET]   = S_AXI_AWQOS;\n  end endgenerate // axi_wach_output\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion\n    assign M_AXI_AWREGION  = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];    \n  end endgenerate // axi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion\n    assign M_AXI_AWREGION  = 0;    \n  end endgenerate // naxi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser\n    assign M_AXI_AWUSER  = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];    \n  end endgenerate // axi_awuser\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser\n    assign M_AXI_AWUSER  = 0;    \n  end endgenerate // naxi_awuser\n\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid\n    assign M_AXI_AWID      = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];\n  end endgenerate //axi_awid\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid\n    assign M_AXI_AWID      = 0;\n  end endgenerate //naxi_awid\n\n  generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output\n    assign M_AXI_WDATA     = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n    assign M_AXI_WLAST     = wdch_dout[0];\n    assign wdch_din[WID_OFFSET-1:WDATA_OFFSET]   = S_AXI_WDATA;\n    assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;\n    assign wdch_din[0]   = S_AXI_WLAST;\n  end endgenerate // axi_wdch_output\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin\n    assign M_AXI_WID       = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];\n  end endgenerate\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin\n    assign M_AXI_WID       = 0;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin\n    assign M_AXI_WUSER     = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];    \n  end endgenerate\n  generate if (C_HAS_AXI_WUSER == 0) begin\n    assign M_AXI_WUSER       = 0;\n  end endgenerate\n\n  generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output\n    assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; \n    assign wrch_din[BID_OFFSET-1:BRESP_OFFSET]   = M_AXI_BRESP;\n  end endgenerate // axi_wrch_output\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser\n    assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];\n  end endgenerate // axi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser\n    assign S_AXI_BUSER = 0;\n  end endgenerate // naxi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid\n    assign S_AXI_BID   =  wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];\n  end endgenerate // axi_bid\n  \n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid\n    assign S_AXI_BID   =  0 ;\n  end endgenerate // naxi_bid  \n\n\n  generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1\n    assign wach_din        = {S_AXI_AWADDR, S_AXI_AWPROT};\n    assign M_AXI_AWADDR    = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];    \n  end endgenerate // axi_wach_output1\n\n  generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1\n    assign wdch_din        = {S_AXI_WDATA, S_AXI_WSTRB};\n    assign M_AXI_WDATA     = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n  end endgenerate // axi_wdch_output1\n\n  generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1\n    assign wrch_din        = M_AXI_BRESP;\n    assign S_AXI_BRESP     = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; \n  end endgenerate // axi_wrch_output1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1\n    assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET]     = S_AXI_AWUSER;\n  end endgenerate // gwach_din1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2\n    assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET]     = S_AXI_AWID;\n  end endgenerate // gwach_din2\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3\n    assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET]     = S_AXI_AWREGION;\n  end endgenerate // gwach_din3\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1\n    assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;\n  end endgenerate // gwdch_din1\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2\n    assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;\n  end endgenerate // gwdch_din2\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1\n    assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET]    = M_AXI_BUSER;\n  end endgenerate // gwrch_din1\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2\n    assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET]    = M_AXI_BID;\n  end endgenerate // gwrch_din2\n\n  //end of  axi_write_channel\n\n  //###########################################################################\n  //  AXI FULL Read Channel (axi_read_channel)\n  //###########################################################################\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_din            ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout           ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout_pkt       ;\n  wire                               rach_full           ;\n  wire                               rach_almost_full    ;\n  wire                               rach_prog_full      ;\n  wire                               rach_empty          ;\n  wire                               rach_almost_empty   ;\n  wire                               rach_prog_empty     ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_din            ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_dout           ;\n  wire                               rdch_full           ;\n  wire                               rdch_almost_full    ;\n  wire                               rdch_prog_full      ;\n  wire                               rdch_empty          ;\n  wire                               rdch_almost_empty   ;\n  wire                               rdch_prog_empty     ;\n  wire                               axi_ar_underflow_i  ;\n  wire                               axi_r_underflow_i   ;\n  wire                               axi_ar_overflow_i   ;\n  wire                               axi_r_overflow_i    ;\n  wire                               axi_rd_underflow_i  ;\n  wire                               axi_rd_overflow_i   ;\n  wire                               rach_s_axi_arready  ;\n  wire                               rach_m_axi_arvalid  ;\n  wire                               rach_wr_en          ;\n  wire                               rach_rd_en          ;\n  wire                               rdch_m_axi_rready   ;\n  wire                               rdch_s_axi_rvalid   ;\n  wire                               rdch_wr_en          ;\n  wire                               rdch_rd_en          ;\n  wire                               arvalid_pkt         ;\n  wire                               arready_pkt         ;\n  wire                               arvalid_en          ;\n  wire                               rdch_rd_ok          ;\n  wire                               accept_next_pkt     ;\n  integer                            rdch_free_space     ;\n  integer                            rdch_commited_space ;\n  wire                               rach_we             ;\n  wire                               rach_re             ;\n  wire                               rdch_we             ;\n  wire                               rdch_re             ;\n\n  localparam ARID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;\n  localparam ARADDR_OFFSET     = ARID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam ARLEN_OFFSET      = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;\n  localparam ARSIZE_OFFSET     = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;\n  localparam ARBURST_OFFSET    = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;\n  localparam ARLOCK_OFFSET     = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;\n  localparam ARCACHE_OFFSET    = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;\n  localparam ARPROT_OFFSET     = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam ARQOS_OFFSET      = ARPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam ARREGION_OFFSET   = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;\n  localparam ARUSER_OFFSET     = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;\n\n  localparam RID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;\n  localparam RDATA_OFFSET      = RID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam RRESP_OFFSET      = RDATA_OFFSET - C_AXI_RRESP_WIDTH;\n  localparam RUSER_OFFSET      = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;\n\n\n  generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rach_we    = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;\n\n    // Read protection when almost empty or prog_empty is high\n//    assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;\n    assign rach_re    = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        rach_m_axi_arvalid & arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY && rach_m_axi_arvalid :\n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY : 1'b0;\n    assign rach_wr_en = (C_HAS_SLAVE_CE == 1)  ? rach_we & S_ACLK_EN : rach_we;\n    assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;\n\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 2  || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),\n        .C_USE_ECC                      (C_USE_ECC_RACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_rach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rach_wr_en),\n        .RD_EN                    (rach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AR_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AR_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AR_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AR_INJECTSBITERR),\n  \n        .DIN                      (rach_din),\n        .DOUT                     (rach_dout_pkt),\n        .FULL                     (rach_full),\n        .EMPTY                    (rach_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_AR_PROG_FULL),\n        .PROG_EMPTY               (AXI_AR_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_ar_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_ar_underflow_i),\n        .DATA_COUNT               (AXI_AR_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AR_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AR_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AR_SBITERR),\n        .DBITERR                  (AXI_AR_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rach),\n        .rd_rst_busy              (rd_rst_busy_rach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rach_s_axi_arready    = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;\n    assign rach_m_axi_arvalid = ~rach_empty;\n    assign S_AXI_ARREADY      = rach_s_axi_arready;\n\n    assign AXI_AR_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;\n    assign AXI_AR_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_ar_overflow_i  : 0;\n\n  end endgenerate // axi_read_addr_channel\n\n  // Register Slice for Read Address Channel\n  generate if (C_RACH_TYPE == 1) begin : grach_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RACH)\n            )\n    rach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_din),\n          .S_VALID                   (S_AXI_ARVALID),\n          .S_READY                   (S_AXI_ARREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice\n\n  // Register Slice for Read Address Channel for MM Packet FIFO\n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (1)\n            )\n    reg_slice_mm_pkt_fifo_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_dout_pkt),\n          .S_VALID                   (arvalid_pkt),\n          .S_READY                   (arready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice_mm_pkt_fifo\n\n  \n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid\n    assign M_AXI_ARVALID      = rach_m_axi_arvalid;\n    assign rach_dout          = rach_dout_pkt;\n  end endgenerate // grach_m_axi_arvalid\n  \n  \n  generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd\n    assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;\n    assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;\n    assign accept_next_pkt  = rach_m_axi_arvalid && arready_pkt && arvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset) begin\n\trdch_commited_space <= 0;\n      end else begin\n\tif(rdch_rd_ok && !accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space-1;\n\tend else if(!rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);\n\tend else if(rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);\n\tend\n      end\n    end //Always end\n\n    always@(*) begin\n      rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));\n    end\n\n    assign arvalid_en = (rdch_free_space >= 0)?1:0;\n  end\n  endgenerate\n  \n  generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd\n    assign arvalid_en = 1;    \n  end\n  endgenerate\n\n  generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rdch_we    = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready  & M_AXI_RVALID : M_AXI_RVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign rdch_re    = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid  & S_AXI_RREADY : S_AXI_RREADY;\n    assign rdch_wr_en = (C_HAS_MASTER_CE == 1)  ? rdch_we & M_ACLK_EN : rdch_we;\n    assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 2  || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),\n        .C_USE_ECC                      (C_USE_ECC_RDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_RDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_rdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rdch_wr_en),\n        .RD_EN                    (rdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_R_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_R_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_R_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_R_INJECTSBITERR),\n  \n        .DIN                      (rdch_din),\n        .DOUT                     (rdch_dout),\n        .FULL                     (rdch_full),\n        .EMPTY                    (rdch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_R_PROG_FULL),\n        .PROG_EMPTY               (AXI_R_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_r_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_r_underflow_i),\n        .DATA_COUNT               (AXI_R_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_R_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_R_WR_DATA_COUNT),\n        .SBITERR                  (AXI_R_SBITERR),\n        .DBITERR                  (AXI_R_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rdch),\n        .rd_rst_busy              (rd_rst_busy_rdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rdch_s_axi_rvalid = ~rdch_empty;\n    assign rdch_m_axi_rready     = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;\n    assign S_AXI_RVALID      = rdch_s_axi_rvalid;\n    assign M_AXI_RREADY      = rdch_m_axi_rready;\n\n    assign AXI_R_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i  : 0;\n    assign AXI_R_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_r_overflow_i   : 0;\n\n  end endgenerate //axi_read_data_channel\n\n  // Register Slice for read Data Channel\n  generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RDCH)\n            )\n    rdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rdch_din),\n          .S_VALID                   (M_AXI_RVALID),\n          .S_READY                   (M_AXI_RREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rdch_dout),\n          .M_VALID                   (S_AXI_RVALID),\n          .M_READY                   (S_AXI_RREADY)\n          );\n  end endgenerate // grdch_reg_slice\n\n\n    assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;\n    assign axi_rd_overflow_i  = C_USE_COMMON_OVERFLOW  == 1 ? (axi_ar_overflow_i  || axi_r_overflow_i) : 0;\n\n\n  generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output\n    assign M_AXI_ARADDR    = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];    \n    assign M_AXI_ARLEN     = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];    \n    assign M_AXI_ARSIZE    = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];    \n    assign M_AXI_ARBURST   = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];    \n    assign M_AXI_ARLOCK    = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];    \n    assign M_AXI_ARCACHE   = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];    \n    assign M_AXI_ARPROT    = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];    \n    assign M_AXI_ARQOS     = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];    \n    assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET]    = S_AXI_ARADDR;\n    assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET]   = S_AXI_ARLEN;\n    assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET]   = S_AXI_ARSIZE;\n    assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;\n    assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;\n    assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;\n    assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;\n    assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET]   = S_AXI_ARQOS;\n  end endgenerate // axi_full_rach_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion\n    assign M_AXI_ARREGION  = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];    \n  end endgenerate // axi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion\n    assign M_AXI_ARREGION  = 0;    \n  end endgenerate // naxi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser\n    assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];    \n  end endgenerate // axi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser\n    assign M_AXI_ARUSER = 0;    \n  end endgenerate // naxi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid\n    assign M_AXI_ARID      = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];\n  end endgenerate // axi_arid\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid\n    assign M_AXI_ARID      = 0;\n  end endgenerate // naxi_arid\n\n  generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output\n    assign S_AXI_RDATA     = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];\n    assign S_AXI_RRESP     = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n    assign S_AXI_RLAST     = rdch_dout[0];\n    assign rdch_din[RID_OFFSET-1:RDATA_OFFSET]   = M_AXI_RDATA;\n    assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;\n    assign rdch_din[0] = M_AXI_RLAST;\n  end endgenerate // axi_full_rdch_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output\n    assign S_AXI_RUSER     = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];\n  end endgenerate // axi_full_ruser_output\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output\n    assign S_AXI_RUSER     =  0;\n  end endgenerate // axi_full_nruser_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid\n    assign S_AXI_RID       = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];\n  end endgenerate // axi_rid\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid\n    assign S_AXI_RID       = 0;\n  end endgenerate // naxi_rid\n\n  generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1\n    assign rach_din      = {S_AXI_ARADDR, S_AXI_ARPROT};\n    assign M_AXI_ARADDR  = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];\n    assign M_AXI_ARPROT  = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];\n  end endgenerate // axi_lite_rach_output\n\n  generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1\n    assign rdch_din      = {M_AXI_RDATA, M_AXI_RRESP};\n    assign S_AXI_RDATA   = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];\n    assign S_AXI_RRESP   = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n  end endgenerate // axi_lite_rdch_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1\n    assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET]     = S_AXI_ARUSER;\n  end endgenerate // grach_din1\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2\n    assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET]     = S_AXI_ARID;\n  end endgenerate // grach_din2\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin\n    assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1\n    assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET]     = M_AXI_RUSER;\n  end endgenerate // grdch_din1\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2\n    assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;\n  end endgenerate // grdch_din2\n\n  //end of axi_read_channel\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf\n    assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :\n                       (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :\n                       (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;\n  end endgenerate // gaxi_comm_uf\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of\n    assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :\n                      (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :\n                      (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;\n  end endgenerate // gaxi_comm_of\n  \n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  // Pass Through Logic or Wiring Logic\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  \n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Write Address Channel\n  generate if (C_WACH_TYPE == 2) begin : gwach_pass_through\n    assign M_AXI_AWID      = S_AXI_AWID;\n    assign M_AXI_AWADDR    = S_AXI_AWADDR;\n    assign M_AXI_AWLEN     = S_AXI_AWLEN;\n    assign M_AXI_AWSIZE    = S_AXI_AWSIZE;\n    assign M_AXI_AWBURST   = S_AXI_AWBURST;\n    assign M_AXI_AWLOCK    = S_AXI_AWLOCK;\n    assign M_AXI_AWCACHE   = S_AXI_AWCACHE;\n    assign M_AXI_AWPROT    = S_AXI_AWPROT;\n    assign M_AXI_AWQOS     = S_AXI_AWQOS;\n    assign M_AXI_AWREGION  = S_AXI_AWREGION;\n    assign M_AXI_AWUSER    = S_AXI_AWUSER;\n    assign S_AXI_AWREADY   = M_AXI_AWREADY;\n    assign M_AXI_AWVALID   = S_AXI_AWVALID;\n  end endgenerate // gwach_pass_through;\n\n  // Wiring logic for Write Data Channel\n  generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through\n    assign M_AXI_WID       = S_AXI_WID;\n    assign M_AXI_WDATA     = S_AXI_WDATA;\n    assign M_AXI_WSTRB     = S_AXI_WSTRB;\n    assign M_AXI_WLAST     = S_AXI_WLAST;\n    assign M_AXI_WUSER     = S_AXI_WUSER;\n    assign S_AXI_WREADY    = M_AXI_WREADY;\n    assign M_AXI_WVALID    = S_AXI_WVALID;\n  end endgenerate // gwdch_pass_through;\n\n  // Wiring logic for Write Response Channel\n  generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through\n    assign S_AXI_BID       = M_AXI_BID;\n    assign S_AXI_BRESP     = M_AXI_BRESP;\n    assign S_AXI_BUSER     = M_AXI_BUSER;\n    assign M_AXI_BREADY    = S_AXI_BREADY;\n    assign S_AXI_BVALID    = M_AXI_BVALID;\n  end endgenerate // gwrch_pass_through;\n\n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Read Address Channel\n  generate if (C_RACH_TYPE == 2) begin : grach_pass_through\n    assign M_AXI_ARID      = S_AXI_ARID;\n    assign M_AXI_ARADDR    = S_AXI_ARADDR;\n    assign M_AXI_ARLEN     = S_AXI_ARLEN;\n    assign M_AXI_ARSIZE    = S_AXI_ARSIZE;\n    assign M_AXI_ARBURST   = S_AXI_ARBURST;\n    assign M_AXI_ARLOCK    = S_AXI_ARLOCK;\n    assign M_AXI_ARCACHE   = S_AXI_ARCACHE;\n    assign M_AXI_ARPROT    = S_AXI_ARPROT;\n    assign M_AXI_ARQOS     = S_AXI_ARQOS;\n    assign M_AXI_ARREGION  = S_AXI_ARREGION;\n    assign M_AXI_ARUSER    = S_AXI_ARUSER;\n    assign S_AXI_ARREADY   = M_AXI_ARREADY;\n    assign M_AXI_ARVALID   = S_AXI_ARVALID;\n  end endgenerate // grach_pass_through;\n\n  // Wiring logic for Read Data Channel \n  generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through\n    assign S_AXI_RID      = M_AXI_RID;\n    assign S_AXI_RLAST    = M_AXI_RLAST;\n    assign S_AXI_RUSER    = M_AXI_RUSER;\n    assign S_AXI_RDATA    = M_AXI_RDATA;\n    assign S_AXI_RRESP    = M_AXI_RRESP;\n    assign S_AXI_RVALID   = M_AXI_RVALID;\n    assign M_AXI_RREADY   = S_AXI_RREADY;\n  end endgenerate // grdch_pass_through;\n\n  // Wiring logic for AXI Streaming\n  generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through\n    assign M_AXIS_TDATA   = S_AXIS_TDATA;\n    assign M_AXIS_TSTRB   = S_AXIS_TSTRB;\n    assign M_AXIS_TKEEP   = S_AXIS_TKEEP;\n    assign M_AXIS_TID     = S_AXIS_TID;\n    assign M_AXIS_TDEST   = S_AXIS_TDEST;\n    assign M_AXIS_TUSER   = S_AXIS_TUSER;\n    assign M_AXIS_TLAST   = S_AXIS_TLAST;\n    assign S_AXIS_TREADY  = M_AXIS_TREADY;\n    assign M_AXIS_TVALID  = S_AXIS_TVALID;\n  end endgenerate // gaxis_pass_through;\n\n\nendmodule //fifo_generator_v13_2_5\n\n\n\n/*******************************************************************************\n * Declaration of top-level module for Conventional FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_CONV_VER\n  #(\n    parameter  C_COMMON_CLOCK                 = 0,\n    parameter  C_INTERFACE_TYPE               = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_COUNT_TYPE                   = 0,\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DEFAULT_VALUE                = \"\",\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_ENABLE_RLOCS                 = 0,\n    parameter  C_FAMILY                       = \"virtex7\", //Not allowed in Verilog model\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_BACKUP                   = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_INT_CLK                  = 0,\n    parameter  C_HAS_MEMINIT_FILE             = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RD_RST                   = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_RST                   = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_INIT_WR_PNTR_VAL             = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_MIF_FILE_NAME                = \"\",\n    parameter  C_OPTIMIZATION_MODE            = 0,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PRIM_FIFO_TYPE               = \"\",\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_FREQ                      = 1,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_ECC                      = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_USE_FIFO16_FLAGS             = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_FREQ                      = 1,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_WR_RESPONSE_LATENCY          = 1,\n    parameter  C_MSGON_VAL                    = 1,\n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2,\n    parameter  C_AXI_TYPE                     = 0\n   )\n\n  (\n   input                               BACKUP,\n   input                               BACKUP_MARKER,\n   input                               CLK,\n   input                               RST,\n   input                               SRST,\n   input                               WR_CLK,\n   input                               WR_RST,\n   input                               RD_CLK,\n   input                               RD_RST,\n   input [C_DIN_WIDTH-1:0]             DIN,\n   input                               WR_EN,\n   input                               RD_EN,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_ASSERT,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_NEGATE,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_ASSERT,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_NEGATE,\n   input                               INT_CLK,\n   input                               INJECTDBITERR,\n   input                               INJECTSBITERR,\n  \n   output [C_DOUT_WIDTH-1:0]           DOUT,\n   output                              FULL,\n   output                              ALMOST_FULL,\n   output                              WR_ACK,\n   output                              OVERFLOW,\n   output                              EMPTY,\n   output                              ALMOST_EMPTY,\n   output                              VALID,\n   output                              UNDERFLOW,\n   output [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT,\n   output [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT,\n   output [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT,\n   output                              PROG_FULL,\n   output                              PROG_EMPTY,\n   output                              SBITERR,\n   output                              DBITERR,\n   output                              wr_rst_busy_o,\n   output                              wr_rst_busy,\n   output                              rd_rst_busy,\n   output                              wr_rst_i_out,\n   output                              rd_rst_i_out\n  );\n\n/*\n ******************************************************************************\n * Definition of Parameters\n ******************************************************************************\n *     C_COMMON_CLOCK                : Common Clock (1), Independent Clocks (0)\n *     C_COUNT_TYPE                  :    *not used\n *     C_DATA_COUNT_WIDTH            : Width of DATA_COUNT bus\n *     C_DEFAULT_VALUE               :    *not used\n *     C_DIN_WIDTH                   : Width of DIN bus\n *     C_DOUT_RST_VAL                : Reset value of DOUT\n *     C_DOUT_WIDTH                  : Width of DOUT bus\n *     C_ENABLE_RLOCS                :    *not used\n *     C_FAMILY                      : not used in bhv model\n *     C_FULL_FLAGS_RST_VAL          : Full flags rst val (0 or 1)\n *     C_HAS_ALMOST_EMPTY            : 1=Core has ALMOST_EMPTY flag\n *     C_HAS_ALMOST_FULL             : 1=Core has ALMOST_FULL flag\n *     C_HAS_BACKUP                  :    *not used\n *     C_HAS_DATA_COUNT              : 1=Core has DATA_COUNT bus\n *     C_HAS_INT_CLK                 : not used in bhv model\n *     C_HAS_MEMINIT_FILE            :    *not used\n *     C_HAS_OVERFLOW                : 1=Core has OVERFLOW flag\n *     C_HAS_RD_DATA_COUNT           : 1=Core has RD_DATA_COUNT bus\n *     C_HAS_RD_RST                  :    *not used\n *     C_HAS_RST                     : 1=Core has Async Rst\n *     C_HAS_SRST                    : 1=Core has Sync Rst\n *     C_HAS_UNDERFLOW               : 1=Core has UNDERFLOW flag\n *     C_HAS_VALID                   : 1=Core has VALID flag\n *     C_HAS_WR_ACK                  : 1=Core has WR_ACK flag\n *     C_HAS_WR_DATA_COUNT           : 1=Core has WR_DATA_COUNT bus\n *     C_HAS_WR_RST                  :    *not used\n *     C_IMPLEMENTATION_TYPE         : 0=Common-Clock Bram/Dram\n *                                     1=Common-Clock ShiftRam\n *                                     2=Indep. Clocks Bram/Dram\n *                                     3=Virtex-4 Built-in\n *                                     4=Virtex-5 Built-in\n *     C_INIT_WR_PNTR_VAL            :   *not used\n *     C_MEMORY_TYPE                 : 1=Block RAM\n *                                     2=Distributed RAM\n *                                     3=Shift RAM\n *                                     4=Built-in FIFO\n *     C_MIF_FILE_NAME               :   *not used\n *     C_OPTIMIZATION_MODE           :   *not used\n *     C_OVERFLOW_LOW                : 1=OVERFLOW active low\n *     C_PRELOAD_LATENCY             : Latency of read: 0, 1, 2\n *     C_PRELOAD_REGS                : 1=Use output registers\n *     C_PRIM_FIFO_TYPE              : not used in bhv model\n *     C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold\n *     C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold\n *     C_PROG_EMPTY_TYPE             : 0=No programmable empty\n *                                     1=Single prog empty thresh constant\n *                                     2=Multiple prog empty thresh constants\n *                                     3=Single prog empty thresh input\n *                                     4=Multiple prog empty thresh inputs\n *     C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold\n *     C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold\n *     C_PROG_FULL_TYPE              : 0=No prog full\n *                                     1=Single prog full thresh constant\n *                                     2=Multiple prog full thresh constants\n *                                     3=Single prog full thresh input\n *                                     4=Multiple prog full thresh inputs\n *     C_RD_DATA_COUNT_WIDTH         : Width of RD_DATA_COUNT bus\n *     C_RD_DEPTH                    : Depth of read interface (2^N)\n *     C_RD_FREQ                     : not used in bhv model\n *     C_RD_PNTR_WIDTH               : always log2(C_RD_DEPTH)\n *     C_UNDERFLOW_LOW               : 1=UNDERFLOW active low\n *     C_USE_DOUT_RST                : 1=Resets DOUT on RST\n *     C_USE_ECC                     : Used for error injection purpose\n *     C_USE_EMBEDDED_REG            : 1=Use BRAM embedded output register\n *     C_USE_FIFO16_FLAGS            : not used in bhv model\n *     C_USE_FWFT_DATA_COUNT         : 1=Use extra logic for FWFT data count\n *     C_VALID_LOW                   : 1=VALID active low\n *     C_WR_ACK_LOW                  : 1=WR_ACK active low\n *     C_WR_DATA_COUNT_WIDTH         : Width of WR_DATA_COUNT bus\n *     C_WR_DEPTH                    : Depth of write interface (2^N)\n *     C_WR_FREQ                     : not used in bhv model\n *     C_WR_PNTR_WIDTH               : always log2(C_WR_DEPTH)\n *     C_WR_RESPONSE_LATENCY         :    *not used\n *     C_MSGON_VAL                   :    *not used by bhv model\n *     C_ENABLE_RST_SYNC             : 0 = Use WR_RST & RD_RST\n *                                     1 = Use RST\n *     C_ERROR_INJECTION_TYPE        : 0 = No error injection\n *                                     1 = Single bit error injection only\n *                                     2 = Double bit error injection only\n *                                     3 = Single and double bit error injection\n ******************************************************************************\n * Definition of Ports\n ******************************************************************************\n *   BACKUP       : Not used\n *   BACKUP_MARKER: Not used\n *   CLK          : Clock\n *   DIN          : Input data bus\n *   PROG_EMPTY_THRESH       : Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag\n *   PROG_FULL_THRESH        : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag\n *   RD_CLK       : Read Domain Clock\n *   RD_EN        : Read enable\n *   RD_RST       : Read Reset\n *   RST          : Asynchronous Reset\n *   SRST         : Synchronous Reset\n *   WR_CLK       : Write Domain Clock\n *   WR_EN        : Write enable\n *   WR_RST       : Write Reset\n *   INT_CLK      : Internal Clock\n *   INJECTSBITERR: Inject Signle bit error\n *   INJECTDBITERR: Inject Double bit error\n *   ALMOST_EMPTY : One word remaining in FIFO\n *   ALMOST_FULL  : One empty space remaining in FIFO\n *   DATA_COUNT   : Number of data words in fifo( synchronous to CLK)\n *   DOUT         : Output data bus\n *   EMPTY        : Empty flag\n *   FULL         : Full flag\n *   OVERFLOW     : Last write rejected\n *   PROG_EMPTY   : Programmable Empty Flag\n *   PROG_FULL    : Programmable Full Flag\n *   RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)\n *   UNDERFLOW    : Last read rejected\n *   VALID        : Last read acknowledged, DOUT bus VALID\n *   WR_ACK       : Last write acknowledged\n *   WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)\n *   SBITERR      : Single Bit ECC Error Detected\n *   DBITERR      : Double Bit ECC Error Detected\n ******************************************************************************\n */\n\n  //----------------------------------------------------------------------------\n  //- Internal Signals for delayed input signals\n  //- All the input signals except Clock are delayed by 100 ps and then given to\n  //- the models.\n  //----------------------------------------------------------------------------\n \n  reg                         rst_delayed                       ;\n  reg                         empty_fb                       ;\n  reg                         srst_delayed                      ;\n  reg                         wr_rst_delayed                    ;\n  reg                         rd_rst_delayed                    ;\n  reg                         wr_en_delayed                     ;\n  reg                         rd_en_delayed                     ;\n  reg  [C_DIN_WIDTH-1:0]      din_delayed                       ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_delayed         ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_assert_delayed  ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_negate_delayed  ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_delayed          ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_assert_delayed   ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_negate_delayed   ;\n  reg                         injectdbiterr_delayed             ;\n  reg                         injectsbiterr_delayed             ;\n   wire                        empty_p0_out;\n\n  always @* rst_delayed                       <= #`TCQ RST                      ;\n  always @* empty_fb                       <= #`TCQ empty_p0_out                      ;\n  always @* srst_delayed                      <= #`TCQ SRST                     ; \n  always @* wr_rst_delayed                    <= #`TCQ WR_RST                   ; \n  always @* rd_rst_delayed                    <= #`TCQ RD_RST                   ; \n  always @* din_delayed                       <= #`TCQ DIN                      ; \n  always @* wr_en_delayed                     <= #`TCQ WR_EN                    ; \n  always @* rd_en_delayed                     <= #`TCQ RD_EN                    ; \n  always @* prog_empty_thresh_delayed         <= #`TCQ PROG_EMPTY_THRESH        ; \n  always @* prog_empty_thresh_assert_delayed  <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; \n  always @* prog_empty_thresh_negate_delayed  <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; \n  always @* prog_full_thresh_delayed          <= #`TCQ PROG_FULL_THRESH         ; \n  always @* prog_full_thresh_assert_delayed   <= #`TCQ PROG_FULL_THRESH_ASSERT  ; \n  always @* prog_full_thresh_negate_delayed   <= #`TCQ PROG_FULL_THRESH_NEGATE  ; \n  always @* injectdbiterr_delayed             <= #`TCQ INJECTDBITERR            ; \n  always @* injectsbiterr_delayed             <= #`TCQ INJECTSBITERR            ; \n\n  /*****************************************************************************\n   * Derived parameters\n   ****************************************************************************/\n  //There are 2 Verilog behavioral models\n  // 0 = Common-Clock FIFO/ShiftRam FIFO\n  // 1 = Independent Clocks FIFO\n  // 2 = Low Latency Synchronous FIFO\n  // 3 = Low Latency Asynchronous FIFO\n  localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :\n                              (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n\n  //Internal reset signals\n  reg                                rd_rst_asreg    = 1'b0;\n  reg                                rd_rst_asreg_d1 = 1'b0;\n  reg                                rd_rst_asreg_d2 = 1'b0;\n  reg                                rd_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_reg      = 1'b0;\n  reg                                rd_rst_comb     = 1'b1;\n  reg                                rd_rst_comb_d1  = 1'b0;\n  reg                                wr_rst_d0       = 1'b0;\n  reg                                wr_rst_d1       = 1'b0;\n  reg                                wr_rst_d2       = 1'b0;\n  reg                                rd_rst_d0       = 1'b0;\n  reg                                rd_rst_d1       = 1'b0;\n  reg                                rd_rst_d2       = 1'b0;\n  reg                                rd_rst_d3       = 1'b0;\n  reg                                wrrst_done      = 1'b0;\n  reg                                rdrst_done      = 1'b0;\n  reg                                wr_rst_asreg    = 1'b0;\n  reg                                wr_rst_asreg_d1 = 1'b0;\n  reg                                wr_rst_asreg_d2 = 1'b0;\n  reg                                wr_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_wr_d0    = 1'b0;\n  reg                                rd_rst_wr_d1    = 1'b0;\n  reg                                rd_rst_wr_d2    = 1'b0;\n  reg                                wr_rst_reg      = 1'b0;\n  reg                                rst_active_i    = 1'b1;\n  reg                                rst_delayed_d1  = 1'b1;\n  reg                                rst_delayed_d2  = 1'b1;\n  reg                                wr_rst_comb     = 1'b1;\n  reg                                wr_rst_comb_d1  = 1'b0;\n  wire                               wr_rst_i;\n  wire                               rd_rst_i;\n  wire                               rst_i;\n\n  //Internal reset signals\n  reg                                rst_asreg     = 1'b0;\n  reg                                srst_asreg    = 1'b0;\n  reg                                rst_asreg_d1  = 1'b0;\n  reg                                rst_asreg_d2  = 1'b0;\n  reg                                srst_asreg_d1 = 1'b0;\n  reg                                srst_asreg_d2 = 1'b0;\n  reg                                rst_reg       = 1'b0;\n  reg                                srst_reg      = 1'b0;\n  reg                                rst_comb      = 1'b1;\n  reg                                rst_comb_d1   = 1'b0;\n  wire                               srst_comb;\n  reg                                rst_full_gen_i = 0;\n  reg                                rst_full_ff_i = 0;\n  reg  [2:0]                         sckt_ff0_bsy_o_i = {3{1'b0}};\n                                     \n  wire                               RD_CLK_P0_IN;\n  wire                               RST_P0_IN;\n  wire                               RD_EN_FIFO_IN;\n  wire                               RD_EN_P0_IN;\n\n  wire                               ALMOST_EMPTY_FIFO_OUT;\n  wire                               ALMOST_FULL_FIFO_OUT;\n  wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT_FIFO_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DOUT_FIFO_OUT;\n  wire                               EMPTY_FIFO_OUT;\n  wire                               fifo_empty_fb;\n  wire                               FULL_FIFO_OUT;\n  wire                               OVERFLOW_FIFO_OUT;\n  wire                               PROG_EMPTY_FIFO_OUT;\n  wire                               PROG_FULL_FIFO_OUT;\n  wire                               VALID_FIFO_OUT;\n  wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT_FIFO_OUT;\n  wire                               UNDERFLOW_FIFO_OUT;\n  wire                               WR_ACK_FIFO_OUT;\n  wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT_FIFO_OUT;\n\n\n  //***************************************************************************\n  // Internal Signals\n  //   The core uses either the internal_ wires or the preload0_ wires depending\n  //     on whether the core uses Preload0 or not.\n  //   When using preload0, the internal signals connect the internal core to\n  //     the preload logic, and the external core's interfaces are tied to the\n  //     preload0 signals from the preload logic.\n  //***************************************************************************\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_OUT;\n  wire                               VALID_P0_OUT;\n  wire                               EMPTY_P0_OUT;\n  wire                               ALMOSTEMPTY_P0_OUT;\n  reg                                EMPTY_P0_OUT_Q;\n  reg                                ALMOSTEMPTY_P0_OUT_Q;\n  wire                               UNDERFLOW_P0_OUT;\n  wire                               RDEN_P0_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_IN;\n  wire                               EMPTY_P0_IN;\n  reg  [31:0]                        DATA_COUNT_FWFT;\n  reg                                SS_FWFT_WR  ;\n  reg                                SS_FWFT_RD ;\n\n  wire                               sbiterr_fifo_out;\n  wire                               dbiterr_fifo_out;\n  wire                               inject_sbit_err;\n  wire                               inject_dbit_err;\n  wire                               sckt_wr_rst_i;\n  wire                               sckt_rd_rst_i;\n  reg                                sckt_wr_rst_i_q = 1'b0;\n \n  wire                               w_fab_read_data_valid_i;\n  wire                               w_read_data_valid_i;\n  wire                               w_ram_valid_i;\n  // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.\n  assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectsbiterr_delayed : 0;\n  assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectdbiterr_delayed : 0;\n                           \n  assign wr_rst_i_out = wr_rst_i;\n  assign rd_rst_i_out = rd_rst_i;\n  assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];\n  generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o\n    wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;\n    always @ (posedge clk_i)\n      sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; \n  end endgenerate \n// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL\n// parameter (1=Independent Clocks, 0=Common Clock)\n\n  localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;\ngenerate\ncase (C_VERILOG_IMPL)\n0 : begin : block1_ss\n  //Common Clock Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_ss\n  #(\n    .C_FAMILY                            (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                  (C_DATA_COUNT_WIDTH),            \n    .C_DIN_WIDTH                         (C_DIN_WIDTH),                   \n    .C_DOUT_RST_VAL                      (C_DOUT_RST_VAL),                \n    .C_DOUT_WIDTH                        (C_DOUT_WIDTH),                  \n    .C_FULL_FLAGS_RST_VAL                (FULL_FLAGS_RST_VAL),            \n    .C_HAS_ALMOST_EMPTY                  (C_HAS_ALMOST_EMPTY),            \n    .C_HAS_ALMOST_FULL                   ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),             \n    .C_HAS_DATA_COUNT                    (C_HAS_DATA_COUNT),              \n    .C_HAS_OVERFLOW                      (C_HAS_OVERFLOW),                \n    .C_HAS_RD_DATA_COUNT                 (C_HAS_RD_DATA_COUNT),           \n    .C_HAS_RST                           (C_EN_SAFETY_CKT?0:C_HAS_RST),                     \n    .C_HAS_SRST                          (C_EN_SAFETY_CKT?1:C_HAS_SRST),                    \n    .C_HAS_UNDERFLOW                     (C_HAS_UNDERFLOW),               \n    .C_HAS_VALID                         (C_HAS_VALID),                   \n    .C_HAS_WR_ACK                        (C_HAS_WR_ACK),                  \n    .C_HAS_WR_DATA_COUNT                 (C_HAS_WR_DATA_COUNT),           \n    .C_IMPLEMENTATION_TYPE               (C_IMPLEMENTATION_TYPE),         \n    .C_MEMORY_TYPE                       (C_MEMORY_TYPE),                 \n    .C_OVERFLOW_LOW                      (C_OVERFLOW_LOW),                \n    .C_PRELOAD_LATENCY                   (C_PRELOAD_LATENCY),             \n    .C_PRELOAD_REGS                      (C_PRELOAD_REGS),                \n    .C_PROG_EMPTY_THRESH_ASSERT_VAL      (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL      (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                   (C_PROG_EMPTY_TYPE),             \n    .C_PROG_FULL_THRESH_ASSERT_VAL       (C_PROG_FULL_THRESH_ASSERT_VAL), \n    .C_PROG_FULL_THRESH_NEGATE_VAL       (C_PROG_FULL_THRESH_NEGATE_VAL), \n    .C_PROG_FULL_TYPE                    (C_PROG_FULL_TYPE),              \n    .C_RD_DATA_COUNT_WIDTH               (C_RD_DATA_COUNT_WIDTH),         \n    .C_RD_DEPTH                          (C_RD_DEPTH),                    \n    .C_RD_PNTR_WIDTH                     (C_RD_PNTR_WIDTH),               \n    .C_UNDERFLOW_LOW                     (C_UNDERFLOW_LOW),               \n    .C_USE_DOUT_RST                      (C_USE_DOUT_RST),                \n    .C_USE_EMBEDDED_REG                  (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                     (C_EN_SAFETY_CKT),            \n    .C_USE_FWFT_DATA_COUNT               (C_USE_FWFT_DATA_COUNT),         \n    .C_VALID_LOW                         (C_VALID_LOW),                   \n    .C_WR_ACK_LOW                        (C_WR_ACK_LOW),                  \n    .C_WR_DATA_COUNT_WIDTH               (C_WR_DATA_COUNT_WIDTH),         \n    .C_WR_DEPTH                          (C_WR_DEPTH),                    \n    .C_WR_PNTR_WIDTH                     (C_WR_PNTR_WIDTH),               \n    .C_USE_ECC                           (C_USE_ECC),                     \n    .C_ENABLE_RST_SYNC                   (C_ENABLE_RST_SYNC),             \n    .C_ERROR_INJECTION_TYPE              (C_ERROR_INJECTION_TYPE),\n    .C_FIFO_TYPE                         (C_FIFO_TYPE)                     \n  )\n  gen_ss\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .CLK                      (CLK),\n    .RST                      (C_EN_SAFETY_CKT?1'b0:rst_i),\n    .SRST                     (C_EN_SAFETY_CKT?sckt_wr_rst_i:srst_delayed),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .USER_EMPTY_FB            (empty_fb),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .DATA_COUNT               (DATA_COUNT_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .WR_RST_BUSY              (wr_rst_busy),\n    .RD_RST_BUSY              (rd_rst_busy),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n1 : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT), \n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .fab_read_data_valid_i    (w_fab_read_data_valid_i),\n    .read_data_valid_i        (w_read_data_valid_i),\n    .ram_valid_i              (w_ram_valid_i),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\n2 : begin : ll_afifo_inst\n  fifo_generator_v13_2_5_beh_ver_ll_afifo\n  #(\n    .C_DIN_WIDTH                    (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                 (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                   (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_RD_DATA_COUNT            (C_HAS_RD_DATA_COUNT),\n    .C_HAS_WR_DATA_COUNT            (C_HAS_WR_DATA_COUNT),\n    .C_RD_DEPTH                     (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                (C_RD_PNTR_WIDTH),\n    .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n    .C_WR_DATA_COUNT_WIDTH          (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                     (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                (C_WR_PNTR_WIDTH),\n    .C_FIFO_TYPE                    (C_FIFO_TYPE)\n   )\n  gen_ll_afifo\n  (\n    .DIN                        (din_delayed),\n    .RD_CLK                     (RD_CLK),\n    .RD_EN                      (rd_en_delayed),\n    .WR_RST                     (wr_rst_i),\n    .RD_RST                     (rd_rst_i),\n    .WR_CLK                     (WR_CLK),\n    .WR_EN                      (wr_en_delayed),\n    .DOUT                       (DOUT),\n    .EMPTY                      (EMPTY),\n    .FULL                       (FULL)\n  );\nend\ndefault : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT),\n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\nendcase\nendgenerate\n\n\n   //**************************************************************************\n   // Connect Internal Signals\n   //   (Signals labeled internal_*)\n   //  In the normal case, these signals tie directly to the FIFO's inputs and\n   //    outputs.\n   //  In the case of Preload Latency 0 or 1, there are intermediate\n   //    signals between the internal FIFO and the preload logic.\n   //**************************************************************************\n   \n   \n   //***********************************************\n   // If First-Word Fall-Through, instantiate\n   // the preload0 (FWFT) module\n   //***********************************************\n   wire                        rd_en_to_fwft_fifo;\n   wire                        sbiterr_fwft;\n   wire                        dbiterr_fwft;\n   wire [C_DOUT_WIDTH-1:0]     dout_fwft;\n   wire                        empty_fwft;\n   wire                        rd_en_fifo_in;\n   wire                        stage2_reg_en_i;\n   wire [1:0]                  valid_stages_i;\n   wire                        rst_fwft;\n   //wire                        empty_p0_out;\n   reg  [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n   localparam IS_PKT_FIFO      = (C_FIFO_TYPE == 1) ? 1 : 0;\n   localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;\n   assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2_fwft\n\n\n         fifo_generator_v13_2_5_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_EMBEDDED_REG  (C_USE_EMBEDDED_REG),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (C_FIFO_TYPE)\n             )\n             fgpl0\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (RST_P0_IN),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (RD_EN_P0_IN),\n                .FIFOEMPTY        (EMPTY_P0_IN),\n                .FIFODATA         (DATA_P0_IN),\n                .FIFOSBITERR      (sbiterr_fifo_out),\n                .FIFODBITERR      (dbiterr_fifo_out),\n                // Output\n                .USERDATA         (dout_fwft),\n                .USERVALID        (VALID_P0_OUT),\n                .USEREMPTY        (empty_fwft),\n                .USERALMOSTEMPTY  (ALMOSTEMPTY_P0_OUT),\n                .USERUNDERFLOW    (UNDERFLOW_P0_OUT),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_fifo_in),\n                .USERSBITERR      (sbiterr_fwft),\n                .USERDBITERR      (dbiterr_fwft),\n                .STAGE2_REG_EN    (stage2_reg_en_i),\n                .fab_read_data_valid_i_o    (w_fab_read_data_valid_i),\n                .read_data_valid_i_o        (w_read_data_valid_i),\n                .ram_valid_i_o              (w_ram_valid_i),\n                .VALID_STAGES                (valid_stages_i)\n                );\n\n         \n         //***********************************************\n         // Connect inputs to preload (FWFT) module\n         //***********************************************\n         //Connect the RD_CLK of the Preload (FWFT) module to CLK if we \n         // have a common-clock FIFO, or RD_CLK if we have an \n         // independent clock FIFO\n         assign RD_CLK_P0_IN       = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);\n         assign RST_P0_IN          = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;\n         assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n         assign EMPTY_P0_IN        = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;\n         assign DATA_P0_IN         = DOUT_FIFO_OUT;\n         \n         //***********************************************\n         // Connect outputs from preload (FWFT) module\n         //***********************************************\n         assign VALID              = VALID_P0_OUT ;\n         assign ALMOST_EMPTY       = ALMOSTEMPTY_P0_OUT;\n         assign UNDERFLOW          = UNDERFLOW_P0_OUT ;\n         \n         assign RD_EN_FIFO_IN      = rd_en_fifo_in;\n         \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:\n           (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : \n           DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];  \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               EMPTY_P0_OUT_Q       <= 1;\n               ALMOSTEMPTY_P0_OUT_Q <= 1;\n            end else begin\n               EMPTY_P0_OUT_Q       <= #`TCQ empty_p0_out;\n//               EMPTY_P0_OUT_Q       <= #`TCQ EMPTY_FIFO_OUT;\n               ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;\n            end\n         end //always\n         \n         \n         //***********************************************\n         // logic for common-clock data count when FWFT is selected\n         //***********************************************\n         initial begin\n            SS_FWFT_RD = 1'b0;\n            DATA_COUNT_FWFT = 0 ;\n            SS_FWFT_WR   = 1'b0 ;\n         end //initial\n         \n         \n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter. SS_FWFT_WR and SS_FWFT_RD\n         // are the up/down enables for the counter.\n         //***********************************************\n         always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin\n            if (C_VALID_LOW == 1) begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;\n            end else begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;\n            end\n            SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT))  ;\n         end \n\n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter for FWFT. This always block \n         // calculates the counter.\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               DATA_COUNT_FWFT      <= 0;\n            end else begin\n               //if (srst_delayed && (C_HAS_SRST == 1) ) begin\n               if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin\n                  DATA_COUNT_FWFT      <= #`TCQ 0;\n               end else begin\n                  case ( {SS_FWFT_WR, SS_FWFT_RD})\n                    2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                    2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;\n                    2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;\n                    2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                  endcase  \n               end //if SRST\n            end //IF RST\n         end //always\n\n      end endgenerate // : block2\n\n    // AXI Streaming Packet FIFO\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_plus1 = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_reg   = 0;\n    reg                         partial_packet     = 0;\n    reg                         stage1_eop_d1      = 0;\n    reg                         rd_en_fifo_in_d1   = 0;\n    reg                         eop_at_stage2      = 0;\n    reg                         ram_pkt_empty      = 0;\n    reg                         ram_pkt_empty_d1   = 0;\n\n    wire [C_DOUT_WIDTH-1:0]     dout_p0_out;\n    wire                        packet_empty_wr;\n    wire                        wr_rst_fwft_pkt_fifo;\n    wire                        dummy_wr_eop;\n    wire                        ram_wr_en_pkt_fifo;\n    wire                        wr_eop;\n    wire                        ram_rd_en_compare;\n    wire                        stage1_eop;\n    wire                        pkt_ready_to_read;\n    wire                        rd_en_2_stage2;\n\n    // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)\n    // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP\n    // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of\n    // write packet count\n    generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop\n       always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n          if (wr_rst_fwft_pkt_fifo)\n             partial_packet   <= 1'b0;\n          else begin\n             if (srst_delayed | wr_rst_busy | rd_rst_busy)\n                partial_packet <= #`TCQ 1'b0;\n             else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))\n                partial_packet <= #`TCQ 1'b1;\n             else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)\n                partial_packet <= #`TCQ 1'b0;\n          end\n        end\n    end endgenerate // gdummy_wr_eop\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin : gpkt_fifo_fwft\n      assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;\n      assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);\n      assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];\n  \n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft) begin\n          stage1_eop_d1    <= 1'b0;\n          rd_en_fifo_in_d1 <= 1'b0;\n        end else begin\n          if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            stage1_eop_d1    <= #`TCQ 1'b0;\n            rd_en_fifo_in_d1 <= #`TCQ 1'b0;\n          end else begin\n            stage1_eop_d1    <= #`TCQ stage1_eop;\n            rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;\n          end\n        end\n      end\n      assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;\n      assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);\n      assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);\n      assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;\n\n\n         fifo_generator_v13_2_5_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (2) // Enable low latency fwft logic\n             )\n         pkt_fifo_fwft\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (rst_fwft),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (rd_en_delayed),\n                .FIFOEMPTY        (pkt_ready_to_read),\n                .FIFODATA         (dout_fwft),\n                .FIFOSBITERR      (sbiterr_fwft),\n                .FIFODBITERR      (dbiterr_fwft),\n                // Output\n                .USERDATA         (dout_p0_out),\n                .USERVALID        (),\n                .USEREMPTY        (empty_p0_out),\n                .USERALMOSTEMPTY  (),\n                .USERUNDERFLOW    (),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_2_stage2),\n                .USERSBITERR      (SBITERR),\n                .USERDBITERR      (DBITERR),\n                .STAGE2_REG_EN    (),\n                .VALID_STAGES     ()\n                );\n\n      assign pkt_ready_to_read  = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));\n      assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft)\n          eop_at_stage2 <= 1'b0;\n        else if (stage2_reg_en_i)\n          eop_at_stage2 <= #`TCQ stage1_eop;\n      end\n\n      //---------------------------------------------------------------------------\n      // Write and Read Packet Count\n      //---------------------------------------------------------------------------\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count  <= 0;\n         else if (srst_delayed  | wr_rst_busy | rd_rst_busy)\n            wr_pkt_count  <= #`TCQ 0;\n         else if (wr_eop)\n            wr_pkt_count  <= #`TCQ wr_pkt_count + 1;\n      end\n    \n    end endgenerate //: gpkt_fifo_fwft\n\n    assign DOUT               = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;\n    assign EMPTY              = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            rd_pkt_count       <= 0;\n            rd_pkt_count_plus1 <= 1;\n         end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            rd_pkt_count       <= #`TCQ 0;\n            rd_pkt_count_plus1 <= #`TCQ 1;\n         end else if (stage2_reg_en_i && stage1_eop) begin\n            rd_pkt_count       <= #`TCQ rd_pkt_count + 1;\n            rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;\n         end\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (SRST | wr_rst_busy | rd_rst_busy) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n    end endgenerate //grss_pkt_cnt\n    \n    localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;\n    reg  [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_b2g = 0;\n    wire [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_rd;\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt\n      // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count_b2g  <= 0;\n         else\n            wr_pkt_count_b2g  <= #`TCQ wr_pkt_count;\n      end\n\n      // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            wr_pkt_count_q       <= 0;\n         else\n            wr_pkt_count_q       <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};\n      end\n\n      always @* begin\n        if (stage1_eop)\n           rd_pkt_count    <= rd_pkt_count_reg + 1;\n        else\n           rd_pkt_count    <= rd_pkt_count_reg;\n      end\n\n      assign wr_pkt_count_rd    = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            rd_pkt_count_reg       <= 0;\n         else if (rd_en_fifo_in)\n            rd_pkt_count_reg       <= #`TCQ rd_pkt_count;\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (rd_pkt_count != wr_pkt_count_rd) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n\n      // Synchronize the empty in write domain\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            pkt_empty_sync  <= 'b1;\n         else\n            pkt_empty_sync  <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};\n      end\n\n    end endgenerate //gras_pkt_cnt\n\n   generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO\n\n     //***********************************************\n     // If NOT First-Word Fall-Through, wire the outputs\n     // of the internal _ss or _as FIFO directly to the\n     // output, and do not instantiate the preload0\n     // module.\n     //***********************************************\n\n     assign RD_CLK_P0_IN       = 0;\n     assign RST_P0_IN          = 0;\n     assign RD_EN_P0_IN        = 0;\n\n     assign RD_EN_FIFO_IN      = rd_en_delayed;\n\n     assign DOUT               = DOUT_FIFO_OUT;\n     assign DATA_P0_IN         = 0;\n     assign VALID              = VALID_FIFO_OUT;\n     assign EMPTY              = EMPTY_FIFO_OUT;\n     assign ALMOST_EMPTY       = ALMOST_EMPTY_FIFO_OUT;\n     assign EMPTY_P0_IN        = 0;\n     assign UNDERFLOW          = UNDERFLOW_FIFO_OUT;\n     assign DATA_COUNT         = DATA_COUNT_FIFO_OUT;\n     assign SBITERR            = sbiterr_fifo_out;\n     assign DBITERR            = dbiterr_fifo_out;\n\n   end endgenerate // STD_FIFO\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO\n     assign empty_p0_out       = empty_fwft;\n     assign SBITERR            = sbiterr_fwft;\n     assign DBITERR            = dbiterr_fwft;\n     assign DOUT               = dout_fwft;\n     assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n\n   end endgenerate // NO_PKT_FIFO\n\n   //***********************************************\n   // Connect user flags to internal signals\n   //***********************************************\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3\n      if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);\n      end //block_ic\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3\n   endgenerate\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30\n       if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30\n   endgenerate\n\n\n    \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both\n       if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30_both\n   endgenerate\n\n generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both\n      if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));\n      end //block_ic_both\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3_both\n   endgenerate\n\n\n   //If we are not using extra logic for the FWFT data count,\n   //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the\n   //internal FIFO instance  \n   generate\n      if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n   //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal\n   //FIFO instance\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1) begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n      else begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n\n   //Connect other flags to the internal FIFO instance\n   assign       FULL        = FULL_FIFO_OUT;\n   assign       ALMOST_FULL = ALMOST_FULL_FIFO_OUT;\n   assign       WR_ACK      = WR_ACK_FIFO_OUT;\n   assign       OVERFLOW    = OVERFLOW_FIFO_OUT;\n   assign       PROG_FULL   = PROG_FULL_FIFO_OUT;\n   assign       PROG_EMPTY  = PROG_EMPTY_FIFO_OUT;\n\n\n  /**************************************************************************\n  * find_log2\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n   // if an asynchronous FIFO has been selected, display a message that the FIFO\n   //   will not be cycle-accurate in simulation\n   initial begin\n      if (C_IMPLEMENTATION_TYPE == 2) begin\n         $display(\"WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.\");\n      end else if (C_MEMORY_TYPE == 4) begin\n         $display(\"FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.\");\n         $finish;\n      end\n\n      if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin\n         $display(\"FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.\");\n         $finish;\n      end\n\n      if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin\n         $display(\"FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.\");\n         $finish;\n      end\n\n      if (C_USE_ECC == 1) begin\n         if (C_DIN_WIDTH != C_DOUT_WIDTH) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.\");\n            $finish;\n         end\n         if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.\");\n            $finish;\n         end\n      end\n\n   end //initial\n\n  /**************************************************************************\n  * Internal reset logic\n  **************************************************************************/\n  assign wr_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg|sckt_wr_rst_i : 0;\n  assign rd_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg|sckt_rd_rst_i : 0;\n  assign rst_i            = C_HAS_RST ? rst_reg|sckt_wr_rst_i : 0;\n\n  wire rst_2_sync;\n  wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;\n\n  localparam RST_SYNC_STAGES = C_EN_SAFETY_CKT == 0 ? C_COMMON_CLOCK ? C_SYNCHRONIZER_STAGE : C_SYNCHRONIZER_STAGE+2 : 5;\n  localparam RST_BUSY_LEN    = 4;\n  reg  wr_rst_busy_i = 0;\n  reg  rd_rst_busy_i = 0;\n  generate\n      if (C_ENABLE_RST_SYNC == 0 || (C_HAS_RST == 0 && C_HAS_SRST == 0)) begin : gnrst_sync\n        always @* begin\n          wr_rst_reg <= wr_rst_delayed;\n          rd_rst_reg <= rd_rst_delayed;\n          rst_reg    <= 1'b0;\n          srst_reg    <= 1'b0;\n        end\n        assign rst_2_sync = wr_rst_delayed;\n        assign wr_rst_busy = 1'b0;\n        assign wr_rst_busy_o = 1'b0;\n        assign rd_rst_busy = 1'b0;\n        assign sckt_wr_rst_i = 1'b0;\n        assign sckt_rd_rst_i = 1'b0;\n      end // gnrst_sync\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 0) begin : g7s_ic_rst_nsckt\n        reg [1:0]                 arst_sync_wr  = 2'b11;\n        reg [1:0]                 arst_sync_rd  = 2'b11;\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge WR_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge RD_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_rd    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_rd    <= #`TCQ {arst_sync_rd[0], rst_delayed};\n        end\n        always @(posedge WR_CLK) begin\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n\tend\n        always @(posedge WR_CLK or posedge arst_sync_wr[1]) begin\n\t  if (arst_sync_wr[1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n            rd_rst_wr_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            rd_rst_wr_ext  <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t    if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t      sckt_wr_rst_ic <= #`TCQ 1'b0;\n            else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t      wr_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n        always @(posedge RD_CLK) begin\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], sckt_wr_rst_ic};\n\tend\n        always @(posedge RD_CLK or posedge arst_sync_rd[1]) begin\n\t  if (arst_sync_rd[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n            wr_rst_rd_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            wr_rst_rd_ext  <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t    if (wr_rst_rd_ext[1]) begin\n\t      sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t      rd_rst_busy_i  <= #`TCQ 1'b0;\n\t    end\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic|arst_sync_wr[1];\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic|arst_sync_rd[1];\n      end // g7s_ic_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 1) begin : g7s_ic_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] arst_sync_rd  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        always @(posedge WR_CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n          rd_rst_wr_ext    <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_wr[RST_SYNC_STAGES-1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n          end else if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t    sckt_wr_rst_ic <= #`TCQ 1'b0;\n          else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t    wr_rst_busy_i  <= #`TCQ 1'b0;\n\tend\n        always @(posedge RD_CLK) begin\n\t  arst_sync_rd     <= #`TCQ {arst_sync_rd[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n          wr_rst_rd_ext    <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_rd[RST_SYNC_STAGES-1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n\t  end else if (wr_rst_rd_ext[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t    rd_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic;\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic;\n      end // g7s_ic_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 0) begin : g7s_cc_rst_nsckt\n        reg [1:0]              arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge CLK) begin\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0] | arst_sync_wr[1]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc | arst_sync_wr[1];\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 1) begin : g7s_cc_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n\n        always @(posedge CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc;\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst\n        assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;\n        assign rd_rst_busy = rst_reg;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = rst_reg;\n        always @* rst_full_ff_i  <= 1'b0;\n        always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;\n\n        always @(posedge CLK) begin\n          rst_delayed_d1 <= #`TCQ srst_delayed;\n          rst_delayed_d2 <= #`TCQ rst_delayed_d1;\n          if (rst_reg || rst_delayed_d2) begin\n            rst_active_i <= #`TCQ 1'b1;\n          end else begin\n            rst_active_i <= #`TCQ rst_reg;\n          end    \n        end   \n        always @(posedge CLK) begin\n          if (~rst_reg && srst_delayed) begin\n             rst_reg <= #`TCQ 1'b1;\n           end else if (rst_reg) begin\n             rst_reg <= #`TCQ 1'b0;\n           end else begin\n             rst_reg <= #`TCQ rst_reg;\n           end    \n        end   \n      end // g8s_cc_rst\n      else if (IS_8SERIES != 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_srst\n        assign wr_rst_busy = srst_delayed;\n        assign rd_rst_busy = srst_delayed;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = srst_delayed;\n        always @* rst_full_ff_i  <= 1'b0;\n      end // g7s_cc_srst\n  endgenerate \n\n  reg rst_d1 = 1'b0;\n  reg rst_d2 = 1'b0;\n  reg rst_d3 = 1'b0;\n  reg rst_d4 = 1'b0;\n  generate\n    if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1\n    // RST_FULL_GEN replaces the reset falling edge detection used to de-assert\n    // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.\n\n    // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &\n    // PROG_FULL\n\n      always @ (posedge rst_2_sync or posedge clk_2_sync) begin\n        if (rst_2_sync && C_EN_SAFETY_CKT == 0) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          rst_d3         <= 1'b1;\n          rst_d4         <= 1'b0;\n        end else begin\n          if (srst_delayed) begin\n            rst_d1         <= #`TCQ 1'b1;\n            rst_d2         <= #`TCQ 1'b1;\n            rst_d3         <= #`TCQ 1'b1;\n            rst_d4         <= #`TCQ 1'b0;\n          end else begin\n            rst_d1         <= #`TCQ wr_rst_busy;//1'b0;\n            rst_d2         <= #`TCQ rst_d1;\n            rst_d3         <= #`TCQ rst_d2 | sckt_wr_rst_i;\n            rst_d4         <= #`TCQ rst_d3;\n          end\n        end\n      end\n\n      always @* rst_full_ff_i  <= C_HAS_SRST ? 1'b0 : rst_d2 | sckt_wr_rst_i;\n      always @* rst_full_gen_i <= C_HAS_SRST ? rst_d4 : rst_d3;\n\n    end else if (C_EN_SAFETY_CKT == 1 && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full_sckt\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end\n  endgenerate // grstd1\n\nendmodule //fifo_generator_v13_2_5_CONV_VER\n\n\nmodule fifo_generator_v13_2_5_sync_stage\n  #(\n    parameter  C_WIDTH          = 10\n   )\n   (\n    input                     RST,\n    input                     CLK,\n    input       [C_WIDTH-1:0] DIN,\n    output reg  [C_WIDTH-1:0] DOUT = 0\n   );\n   always @ (posedge RST or posedge CLK) begin\n     if (RST)\n       DOUT <= 0;\n     else\n       DOUT <= #`TCQ DIN;\n   end\nendmodule // fifo_generator_v13_2_5_sync_stage\n\n/*******************************************************************************\n * Declaration of Independent-Clocks FIFO Module\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_as\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2 \n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input                                         SAFETY_CKT_WR_RST,\n   input                                         SAFETY_CKT_RD_RST,\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_ASSERT,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_NEGATE,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_ASSERT,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_NEGATE,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         RD_EN_USER,\n   input                                         RST,\n   input                                         RST_FULL_GEN,\n   input                                         RST_FULL_FF,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   input                                         INJECTDBITERR,\n   input                                         INJECTSBITERR,\n   input                                         USER_EMPTY_FB,\n   input                                         fab_read_data_valid_i,\n   input                                         read_data_valid_i,\n   input                                         ram_valid_i,\n   output reg                                    ALMOST_EMPTY = 1'b1,\n   output reg                                    ALMOST_FULL = C_FULL_FLAGS_RST_VAL,\n   output      [C_DOUT_WIDTH-1:0]                DOUT,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    EMPTY_FB = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL,\n   output                                        OVERFLOW,\n   output                                        PROG_EMPTY,\n   output                                        PROG_FULL,\n   output                                        VALID,\n   output      [C_RD_DATA_COUNT_WIDTH-1:0]       RD_DATA_COUNT,\n   output                                        UNDERFLOW,\n   output                                        WR_ACK,\n   output      [C_WR_DATA_COUNT_WIDTH-1:0]       WR_DATA_COUNT,\n   output                                        SBITERR,\n   output                                        DBITERR\n  );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   \n  \n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   \n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;\n   // Array that holds the error injection type (single/double bit error) on \n   // a specific write operation, which is returned on read to corrupt the\n   // output data.\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   //The amount of data stored in the FIFO at any time is given\n   // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK\n   // domain.\n   //num_wr_bits is calculated by considering the total words in the FIFO,\n   // and the state of the read pointer (which may not have yet crossed clock\n   // domains.)\n   //num_rd_bits is calculated by considering the total words in the FIFO,\n   // and the state of the write pointer (which may not have yet crossed clock\n   // domains.)\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   wire                        wr_rst_i = WR_RST;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n   wire                        rd_rst_i = RD_RST;\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n\n\n\n   // Delayed ram_rd_en is needed only for STD Embedded register option\n   generate\n     if (C_PRELOAD_LATENCY == 2) begin : grd_d\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n       end\n     end\n   endgenerate\n   \n    generate\n     if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n           fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n       end\n     end\n   endgenerate\n\n  \n\n   // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;\n     end else begin : rdl // Read depth lesser than or equal to write depth\n       assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n     end\n   endgenerate\n\n   // Generate Empty and Almost Empty\n  // ram_rd_en used to determine EMPTY should depend on the EMPTY.\n   assign ram_rd_en        = RD_EN & !EMPTY;\n   assign empty_int        = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));\n   assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));\n\n   // Register Empty and Almost Empty\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else begin\n         rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};\n\n         if (empty_int)\n           EMPTY           <= #`TCQ 1'b1;\n         else\n           EMPTY           <= #`TCQ 1'b0;\n\n         if (!EMPTY) begin\n           if (almost_empty_int)\n             ALMOST_EMPTY  <= #`TCQ 1'b1;\n           else\n             ALMOST_EMPTY  <= #`TCQ 1'b0;\n         end\n       end // rd_rst_i\n     end // always\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY_FB     <= 1'b1;\n       end else begin\n         if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else if (empty_int)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else\n           EMPTY_FB   <= #`TCQ 1'b0;\n       end // rd_rst_i\n     end // always\n\n   // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;\n     end else begin : wdl // Write depth lesser than or equal to read depth\n       assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n     end\n   endgenerate\n\n  // Generate FULL and ALMOST_FULL\n  // ram_wr_en used to determine FULL should depend on the FULL.\n  assign ram_wr_en       = WR_EN & !FULL;\n  assign full_int        = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));\n  assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));\n\n   // Register FULL and ALMOST_FULL Empty\n   always @ (posedge WR_CLK or posedge RST_FULL_FF)\n     begin\n       if (RST_FULL_FF & C_HAS_RST) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else begin\n         if (full_int) begin\n           FULL           <= #`TCQ 1'b1;\n         end else begin\n           FULL           <= #`TCQ 1'b0;\n         end\n\n         if (RST_FULL_GEN) begin\n           ALMOST_FULL    <= #`TCQ 1'b0;\n         end else if (!FULL) begin\n           if (almost_full_int)\n             ALMOST_FULL  <= #`TCQ 1'b1;\n           else\n             ALMOST_FULL  <= #`TCQ 1'b0;\n         end\n       end // wr_rst_i\n     end // always\n   always @ (posedge WR_CLK or posedge wr_rst_i)\n     begin\n       if (wr_rst_i) begin\n         wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};\n       end else begin\n         wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};\n       end // wr_rst_i\n     end // always\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i) begin\n           stage1_valid     <= 0;\n           stage2_valid     <= 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n   //Pointers passed into opposite clock domain\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_EMPTY.\n   wire [31:0] num_read_words_pe = \n     num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_FULL.\n   wire [31:0] num_write_words_pf =\n     num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n    \n    \n   /***************************************************************************\n    * Internal registers and wires\n    **************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire [C_DOUT_WIDTH-1:0] ideal_dout_out;      \n   wire valid_i;\n   wire valid_out1;\n   wire valid_out2;\n   wire valid_out;  \n   wire underflow_i;\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]               err_type                 = 0;\n   reg [1:0]               err_type_d1              = 0;\n   reg [1:0]               err_type_both              = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout               = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_d1            = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_both            = 0;\n   reg                     ideal_wr_ack             = 0;\n   reg                     ideal_valid              = 0;\n   reg                     ideal_overflow           = C_OVERFLOW_LOW;\n   reg                     ideal_underflow          = C_UNDERFLOW_LOW;\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   reg         valid_d1     = 0;\n   reg         valid_d2     = 0; \n   \n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n   \n\n  /****************************************************************************\n   * Function Declarations\n   ***************************************************************************/\n\n  /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n      if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n    end\n  endtask\n\n  /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n  /***********************************************************************\n  * hexstr_conv\n  *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n  ***********************************************************************/\n  function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_d2           = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n    end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the \n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n    wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;   \n   wire RD_CLK;\n   wire RD_EN;\n   wire RST;\n   wire WR_CLK;\n   wire WR_EN;\n    */\n\n   //***************************************************************************\n   // Dout may change behavior based on latency\n   //***************************************************************************\n   assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?\n                         ideal_dout_d1: ideal_dout;   \n   assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; \n\n   //***************************************************************************\n   // Assign SBITERR and DBITERR based on latency \n   //***************************************************************************\n   assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                    (C_PRELOAD_LATENCY == 2 &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?\n                    err_type_d1[0]: err_type[0]; \n   assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                    (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                    err_type_d1[1]: err_type[1]; \n  \n   //***************************************************************************\n   // Safety-ckt logic with embedded reg/fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n       //  if (C_HAS_VALID == 1) begin\n       //       assign valid_out = valid_d1;\n       //  end\n             \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)\n          begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else \n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n          end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                  @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n           end\n           else begin\n                   if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                   end\n             end \n           end  \n      end \n      endgenerate   \n\n//***************************************************************************\n   // Safety-ckt logic with embedded reg + fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else begin\n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n               fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n          end\n        end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   ideal_dout_both <= #`TCQ dout_reset_val;\n              end\n           end else begin\n             if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n              \n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n             end\n           end \n         end      \n      end \n      endgenerate    \n \n   //***************************************************************************\n   // Overflow may be active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_OVERFLOW==1) begin : blockOF1\n   assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n      end\n   endgenerate\n\n   assign PROG_EMPTY = ideal_prog_empty;\n   assign PROG_FULL  = ideal_prog_full;\n\n   //***************************************************************************\n   // Valid may change behavior based on latency or active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_VALID==1) begin : blockVL1\n   assign valid_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;\n   assign valid_out1 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?\n                       valid_d1: valid_i;  \n   assign valid_out2 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?\n                       valid_d2: valid_i; \n   assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;\n   assign VALID     = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Underflow may change behavior based on latency or active-low   \n   //***************************************************************************\n   generate\n      if (C_HAS_UNDERFLOW==1) begin : blockUF1\n   assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;\n   assign UNDERFLOW   = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n    end\n   endgenerate\n\n   //***************************************************************************\n   // Write acknowledge may be active low\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_ACK==1) begin : blockWK1\n   assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext\n\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_wr_pntr = 0;\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_rd_pntr = 0;\n      wire [C_PNTR_WIDTH-1:0]  diff_wr_rd_tmp;\n      wire [C_PNTR_WIDTH:0]    diff_wr_rd;\n      reg  [C_PNTR_WIDTH:0]    wr_data_count_i  = 0;\n        always @* begin\n          if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = 0;\n            adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n          end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin\n            adjusted_rd_pntr = rd_pntr_wr;\n            adjusted_wr_pntr = 0;\n            adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n          end else begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = rd_pntr_wr;\n          end\n        end // always @*\n\n        assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;\n        assign diff_wr_rd     = {1'b0,diff_wr_rd_tmp};\n\n        always @ (posedge wr_rst_i or posedge WR_CLK)\n        begin\n            if (wr_rst_i)\n              wr_data_count_i <= 0;\n            else\n              wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;\n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n\n        always @* begin\n          if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];\n          else\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n        end // always @*\n      end // wdc_fwft_ext\n   endgenerate\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   reg  [C_RD_PNTR_WIDTH:0]    rdc_fwft_ext_as  = 0;\n\n   generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n\n\n   always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= 0;\n            end else begin\n              if (!stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 0;\n              else if (!stage1_valid && stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 1;\n              else\n                rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;\n            end \n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n      end // rdc_fwft_ext\n end\n   endgenerate\n\n\n  generate if (C_USE_EMBEDDED_REG == 3) begin\n     if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n        wire [C_RD_PNTR_WIDTH:0]  diff_rd_wr_1;\n   //     assign diff_rd_wr_1 = diff_rd_wr +2'h2;\n\n       always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= #`TCQ 0;\n            end else begin\n          //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))\n          //    rdc_fwft_ext_as <= 1'b0;\n          //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) \n          //    rdc_fwft_ext_as <= 1'b1;\n          //else\n            rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;\n        end\n\n\n\nend\nend\nend\nendgenerate\n          \n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1) begin : grdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?\n          rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :\n          rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?\n          wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :\n          wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n\n  /**************************************************************************\n  * Assorted registers for delayed versions of signals\n  **************************************************************************/\n  //Capture delayed version of valid\n  generate\n      if (C_HAS_VALID==1) begin : blockVL2\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n      valid_d1 <= 1'b0;\n      valid_d2 <= 1'b0;\n    end else begin\n      valid_d1 <= #`TCQ valid_i;\n      valid_d2 <= #`TCQ valid_d1;\n    end \n//    if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin\n  //      valid_d2 <= #`TCQ valid_d1;\n      //  end \n  end \n      end\n endgenerate  \n   \n  //Capture delayed version of dout\n  /**************************************************************************\n    *embedded/fabric reg with no safety ckt\n    **************************************************************************/\n  generate \n       if (C_USE_EMBEDDED_REG < 3) begin\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n       if (C_USE_DOUT_RST == 1'b1) begin\n         @(posedge RD_CLK)\n           ideal_dout_d1   <= #`TCQ dout_reset_val;\n           ideal_dout   <= #`TCQ dout_reset_val;\n       end\n      // Reset err_type only if ECC is not selected\n      if (C_USE_ECC == 0)\n        err_type_d1     <= #`TCQ 0;\n     end else if (ram_rd_en_d1) begin\n      ideal_dout_d1   <= #`TCQ ideal_dout;\n      err_type_d1     <= #`TCQ err_type;\n           end    \n  end  \n   \nend  \nendgenerate \n/**************************************************************************\n    *embedded + fabric reg with no safety ckt\n    **************************************************************************/\n\ngenerate \n  if (C_USE_EMBEDDED_REG == 3) begin\n    always @(posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i == 1'b1) begin\n        if (C_USE_DOUT_RST == 1'b1) begin\n           @(posedge RD_CLK)\n             ideal_dout    <= #`TCQ dout_reset_val;\n             ideal_dout_d1   <= #`TCQ dout_reset_val;\n             ideal_dout_both   <= #`TCQ dout_reset_val;\n        end\n        // Reset err_type only if ECC is not selected\n        if (C_USE_ECC == 0) begin\n          err_type_d1     <= #`TCQ 0;\n          err_type_both   <= #`TCQ 0;\n        end\n      end else begin\n         if (ram_rd_en_d1) begin\n           ideal_dout_both   <= #`TCQ ideal_dout;\n           err_type_both     <= #`TCQ err_type;\n         end    \n         if (fab_rd_en_d1) begin\n           ideal_dout_d1   <= #`TCQ ideal_dout_both;\n           err_type_d1     <= #`TCQ err_type_both;\n         end\n      end\n    end  \n  end  \nendgenerate \n\n  \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate\n     if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n       always @(posedge WR_CLK) begin\n         ideal_overflow    <= #`TCQ WR_EN & FULL;\n       end\n     end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n       always @(posedge WR_CLK) begin\n         //ideal_overflow    <= #`TCQ WR_EN & (FULL | wr_rst_i);\n         ideal_overflow    <= #`TCQ WR_EN & (FULL );\n       end\n     end\n   endgenerate\n\n   generate\n     if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ EMPTY & RD_EN;\n       end\n     end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ (EMPTY) & RD_EN;\n         //ideal_underflow    <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;\n       end\n     end\n   endgenerate\n\n   /**************************************************************************\n   * Write/Read Pointer Synchronization\n   **************************************************************************/\n   localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;\n   wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   genvar gss;\n\n   generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (C_WR_PNTR_WIDTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_i), \n         .CLK      (RD_CLK), \n         .DIN      (wr_pntr_sync_stgs[gss-1]), \n         .DOUT     (wr_pntr_sync_stgs[gss])\n        );\n \n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (C_RD_PNTR_WIDTH)\n        )\n     wr_stg_inst\n        (\n         .RST      (wr_rst_i), \n         .CLK      (WR_CLK), \n         .DIN      (rd_pntr_sync_stgs[gss-1]), \n         .DOUT     (rd_pntr_sync_stgs[gss])\n        );\n   end endgenerate // Sync_stage_inst\n\n   assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;\n   assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;\n   always@* begin\n     wr_pntr_rd           <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n     rd_pntr_wr           <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n   end\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp\n     if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)\n       wr_pntr           <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)\n       wr_pntr           <= #`TCQ 0;\n   end\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (wr_rst_i == 1'b1) begin\n       num_wr_bits       <= 0;\n       next_num_wr_bits   = 0;\n       wr_ptr            <= C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= C_RD_DEPTH - 1;\n       ideal_wr_ack      <= 0;\n       ideal_wr_count    <= 0;\n       tmp_wr_listsize    = 0;\n       rd_ptr_wrclk_next <= 0;\n       wr_pntr_rd1       <= 0;\n\n     end else begin //wr_rst_i==0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       //If this is a write, handle the write by adding the value\n       // to the linked list, and updating all outputs appropriately\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD \n             >= C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full, but reporting full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //With DEPTH-1 words in the FIFO, it is almost_full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n\n           //If the FIFO is completely empty, but it is\n           // reporting FULL for some reason (like reset)\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=\n                C_FIFO_WR_DEPTH-2) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //FIFO is really not close to full, so change flag status.\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n           end //(tmp_wr_listsize == 0)\n\n         end else begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=\n              C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack       <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count     <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;\n\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //This write is CAUSING the FIFO to go full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is 2 from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == \n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits =  next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Still 2 from full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is not close to being full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <\n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //wr_rst_i==0\n   end // gen_fifo_w\n\n\n  /***************************************************************************\n   * Programmable FULL flags\n   ***************************************************************************/\n\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;\n\n   generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;\n   end else begin // STD\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;\n   end endgenerate\n\n   always @(posedge WR_CLK or posedge wr_rst_i) begin\n\n     if (wr_rst_i == 1'b1) begin\n       diff_pntr         <= 0;\n     end else begin\n       if (ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);\n       else if (!ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);\n    end\n  end\n\n\n   always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf\n\n     if (RST_FULL_FF & C_HAS_RST) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else begin\n\n       if (RST_FULL_GEN)\n         ideal_prog_full   <= #`TCQ 0;\n       //Single Programmable Full Constant Threshold\n       else if (C_PROG_FULL_TYPE == 1) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else\n             ideal_prog_full <= #`TCQ 0;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Constant Thresholds\n       end else if (C_PROG_FULL_TYPE == 2) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else if (diff_pntr < pf_thr_negate_val)\n             ideal_prog_full <= #`TCQ 0;\n           else\n             ideal_prog_full <= #`TCQ ideal_prog_full;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Single Programmable Full Threshold Input\n       end else if (C_PROG_FULL_TYPE == 3) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH)\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Threshold Inputs\n       end else if (C_PROG_FULL_TYPE == 4) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH_ASSERT)\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < PROG_FULL_THRESH_NEGATE)\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       end // C_PROG_FULL_TYPE\n\n     end //wr_rst_i==0\n   end //\n\n   \n   /**************************************************************************\n   * Read Domain Logic\n   **************************************************************************/\n\n\n   /*********************************************************\n    * Programmable EMPTY flags\n    *********************************************************/\n   //Determine the Assert and Negate thresholds for Programmable Empty\n\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd      = 0;\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe\n\n     if (rd_rst_i & C_HAS_RST) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else begin\n       if (ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;\n       else if (!ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr);\n       else\n         diff_pntr_rd       <=  #`TCQ diff_pntr_rd;\n  \n       if (C_PROG_EMPTY_TYPE == 1) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 2) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 3) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 4) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end  //C_PROG_EMPTY_TYPE\n     end\n   end // gen_pe\n\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;\n   end endgenerate // single_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;\n   end endgenerate // multiple_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;\n   end endgenerate // single_multiple_pe_thr_const\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp\n     if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n       rd_pntr            <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)\n       rd_pntr            <= #`TCQ 0;\n   end\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rd_rst_i & C_HAS_RST) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n     end else begin //rd_rst_i==0\n\n       rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 1\n       /*****************************************************************/\n       if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Reminder that FIFO is still empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end // if (tmp_rd_listsize <= 0)\n\n             //If the FIFO is one from empty, but it is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 1)\n\n             //If the FIFO is two from empty, and is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Fifo has two words, so is neither empty or almost empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 2)\n\n             //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid <= #`TCQ 1'b0;\n                 //Note that the FIFO is No Longer Empty or Almost Empty\n\n                 ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n               end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n             end // else: if(ideal_empty == 1'b1)\n\n           else //if (ideal_empty == 1'b0)\n             begin\n\n               //If the FIFO is completely full, and we are successfully reading from it\n               if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)\n\n               //If the FIFO is not close to being empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n               //If the FIFO is two from empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Fifo is not yet empty. It is going almost_empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n\n               //If the FIFO is one from empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Note that FIFO is GOING empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 1)\n\n\n               //If the FIFO is completely empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n                 begin\n                   //Do not change the contents of the FIFO\n\n                   //Do not acknowledge the read from empty FIFO\n                   ideal_valid        <= #`TCQ 1'b0;\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize <= 0)\n\n             end // if (ideal_empty == 1'b0)\n\n           end //(RD_EN == 1'b1)\n\n         else //if (RD_EN == 1'b0)\n           begin\n             //If user did not attempt a read, do not give an ack or err\n             ideal_valid          <= #`TCQ 1'b0;\n\n             ideal_rd_count       <= #`TCQ num_read_words_sized_i;\n\n           end // else: !if(RD_EN == 1'b1)\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 0\n       /*****************************************************************/\n       end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty, but it is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty, and is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Fifo has two words, so is neither empty or almost empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                         (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that the FIFO is No Longer Empty or Almost Empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n           end else begin\n\n             //If the FIFO is completely full, and we are successfully reading from it\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is not close to being empty\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                          (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Fifo is not yet empty. It is going almost_empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Note that FIFO is GOING empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is completely empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if (tmp_rd_listsize <= 0)\n\n           end // if (ideal_empty == 1'b0)\n\n         end else begin//(RD_EN == 1'b0)\n\n         \n           //If user did not attempt a read, do not give an ack or err\n           ideal_valid           <= #`TCQ 1'b0;\n           ideal_rd_count        <= #`TCQ num_read_words_sized_i;\n\n         end // else: !if(RD_EN == 1'b1)\n       end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //rd_rst_i==0\n   end //always gen_fifo_r_as\n\nendmodule // fifo_generator_v13_2_5_bhv_ver_as\n\n\n/*******************************************************************************\n * Declaration of Low Latency Asynchronous FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_beh_ver_ll_afifo\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_FIFO_TYPE                    = 0\n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   output reg  [C_DOUT_WIDTH-1:0]                DOUT = 0,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL\n  );\n\n  //-----------------------------------------------------------------------------\n  // Low Latency Asynchronous FIFO\n  //-----------------------------------------------------------------------------\n\n  // Memory which will be used to simulate a FIFO\n  reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n  integer i;\n  initial begin\n    for (i = 0; i < C_WR_DEPTH; i = i + 1)\n      memory[i] = 0;\n  end\n\n  reg  [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;\n  wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;\n  reg  [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;\n  reg                        ll_afifo_full    = 1'b0;\n  reg                        ll_afifo_empty   = 1'b1;\n  wire                       write_allow;\n  wire                       read_allow;\n\n  assign write_allow = WR_EN & ~ll_afifo_full;\n  assign read_allow  = RD_EN & ~ll_afifo_empty;\n\n  //-----------------------------------------------------------------------------\n  // Write Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      wr_pntr_ll_afifo   <= 0;\n    else if (write_allow)\n      wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Read Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      rd_pntr_ll_afifo_q   <= 0;\n    else\n      rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;\n  end\n  assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;\n  \n  //-----------------------------------------------------------------------------\n  // Fill the Memory\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK) begin\n    if (write_allow)\n      memory[wr_pntr_ll_afifo] <= #`TCQ DIN;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate DOUT\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK) begin\n      DOUT <= #`TCQ memory[rd_pntr_ll_afifo];\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate EMPTY\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      ll_afifo_empty   <= 1'b1;\n    else\n      ll_afifo_empty   <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | \n                           (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate FULL\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      ll_afifo_full   <= 1'b1;\n    else\n      ll_afifo_full   <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | \n                           (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));\n  end\n\n  always @* begin\n    FULL  <= ll_afifo_full;\n    EMPTY <= ll_afifo_empty;\n  end\n\nendmodule // fifo_generator_v13_2_5_beh_ver_ll_afifo\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_ss\n   \n  /**************************************************************************\n   * Declare user parameters and their defaults\n   *************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0 \n   )\n   \n  /**************************************************************************\n   * Declare Input and Output Ports\n   *************************************************************************/\n   (\n    //Inputs\n    input                                 SAFETY_CKT_WR_RST,\n    input                                 CLK,\n    input       [C_DIN_WIDTH-1:0]         DIN,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_ASSERT,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_NEGATE,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_ASSERT,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_NEGATE,\n    input                                 RD_EN,\n    input                                 RD_EN_USER,\n    input                                 USER_EMPTY_FB,\n    input                                 RST,\n    input                                 RST_FULL_GEN,\n    input                                 RST_FULL_FF,\n    input                                 SRST,\n    input                                 WR_EN,\n    input                                 INJECTDBITERR,\n    input                                 INJECTSBITERR,\n    input                                 WR_RST_BUSY,\n    input                                 RD_RST_BUSY,\n                                    \n    //Outputs                       \n    output                                ALMOST_EMPTY,\n    output                                ALMOST_FULL,\n    output reg   [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,\n    output       [C_DOUT_WIDTH-1:0]       DOUT,\n    output                                EMPTY,\n    output reg                            EMPTY_FB = 1'b1,\n    output                                FULL,\n    output                                OVERFLOW,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]    RD_DATA_COUNT,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]    WR_DATA_COUNT,\n    output                                PROG_EMPTY,\n    output                                PROG_FULL,\n    output                                VALID,\n    output                                UNDERFLOW,\n    output                                WR_ACK,\n    output                                SBITERR,\n    output                                DBITERR\n   );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;\n   wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n   localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; \n\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n   localparam  EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //localparam  EXTRA_WORDS_PE_PARAM  = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not \n   //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.\n   // Therefore, during SRST, all the FULL flags reset to 0.\n   localparam                      C_HAS_FAST_FIFO = 0;\n   localparam                      C_FIFO_WR_DEPTH = C_WR_DEPTH;\n   localparam                      C_FIFO_RD_DEPTH = C_RD_DEPTH;\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;\n   localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;\n   localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;\n   localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n  localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; \n  localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; \n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   \n   /**************************************************************************\n    * Internal Registers and wires\n    *************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire                           underflow_i;\n   wire                           valid_i;\n   wire                           valid_out;\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_reg = 1'b0;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n   wire                         srst_rrst_busy;\n\n\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]                      err_type           = 0;\n   reg [1:0]                      err_type_d1        = 0;\n   reg [1:0]                      err_type_both      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout         = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_d1      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_both      = 0;\n   wire [C_DOUT_WIDTH-1:0]        ideal_dout_out;\n   wire                           fwft_enabled;\n   reg                            ideal_wr_ack       = 0;\n   reg                            ideal_valid        = 0;\n   reg                            ideal_overflow     = C_OVERFLOW_LOW;\n   reg                            ideal_underflow    = C_UNDERFLOW_LOW;\n\n   reg                            full_i             = C_FULL_FLAGS_RST_VAL;\n   reg                            full_i_temp        = 0;\n   reg                            empty_i            = 1;\n   reg                            almost_full_i      = 0;\n   reg                            almost_empty_i     = 1;\n   reg                            prog_full_i        = 0;\n   reg                            prog_empty_i       = 1;\n   reg [C_WR_PNTR_WIDTH-1:0]      wr_pntr            = 0;\n   reg [C_RD_PNTR_WIDTH-1:0]      rd_pntr            = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg [C_RD_PNTR_WIDTH-1:0]      diff_count         = 0;\n\n   reg                            write_allow_q      = 0;\n   reg                            read_allow_q       = 0;\n   reg                            valid_d1           = 0;\n   reg                            valid_both           = 0;\n   reg                            valid_d2           = 0;\n   wire                           rst_i;\n   wire                           srst_i;\n\n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]         dout_reset_val = 0;\n\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n\n\n\n   /****************************************************************************\n    * Function Declarations\n    ***************************************************************************/\n\n   /****************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***************************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin\n        case (def_data[7:0])\n          8'b00000000 : begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default : begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1) begin\n          if ((index*4)+j < C_DOUT_WIDTH) begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   //reg         valid_d1     = 0;\n   \n   \n   //user specified value for reseting the size of the fifo\n   //reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n\n\n /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n     if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n\n     end\n  endtask\n\n\n   \n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_dout_both    = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_both         = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n\n   end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the\n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n   wire CLK;\n   wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;\n   wire RD_EN;\n   wire RST;\n   wire WR_EN;\n    */\n\n  // Assign ALMOST_EPMTY\n  generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae\n    assign ALMOST_EMPTY = almost_empty_i;\n  end else begin : gnae\n    assign ALMOST_EMPTY = 0;\n  end endgenerate // gae\n\n  // Assign ALMOST_FULL\n  generate if (C_HAS_ALMOST_FULL==1) begin : gaf\n    assign ALMOST_FULL  = almost_full_i;\n  end else begin : gnaf\n    assign ALMOST_FULL  = 0;\n  end endgenerate // gaf\n\n   // Dout may change behavior based on latency\n  localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?\n                         ideal_dout_d1: ideal_dout; \n  assign DOUT = ideal_dout_out;\n\n  // Assign SBITERR and DBITERR based on latency \n  assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[0]: err_type[0]; \n  assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[1]: err_type[1]; \n\n  assign EMPTY         = empty_i;\n  assign FULL          = full_i;\n  //saftey_ckt with one register\n\n  generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)\n          begin\n          if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n              valid_d1 <= #`TCQ 1'b0;\n          end\n          else begin\n               ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n               valid_d1 <= #`TCQ valid_i;\n          end\n          end\n          \n           always@(posedge rst_delayed_sft2 or posedge CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n              end\n           else if (srst_rrst_busy == 1'b1) begin\n                   if (C_USE_DOUT_RST == 1'b1) begin\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   end\n           end else if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                end\n           end   \n      end //if \n      endgenerate   \n\n//safety ckt with both registers\n\ngenerate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK) begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            valid_d1 <= #`TCQ 1'b0;\n          end else begin\n            ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n            fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n            valid_both <= #`TCQ valid_i;\n            valid_d1 <= #`TCQ valid_both;\n          end\n        end\n\n        always@(posedge rst_delayed_sft2 or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                  ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else if (srst_rrst_busy == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else begin \n            if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n            end\n          end\n        end\n      end //if \n      endgenerate    \n \n \n  //Overflow may be active-low\n  generate if (C_HAS_OVERFLOW==1) begin : gof\n    assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n  end else begin : gnof\n    assign OVERFLOW = 0;\n  end endgenerate // gof\n\n  assign PROG_EMPTY    = prog_empty_i;\n  assign PROG_FULL     = prog_full_i;\n\n   //Valid may change behavior based on latency or active-low\n  generate if (C_HAS_VALID==1) begin : gvalid\n    assign valid_i       = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;\n    assign valid_out     = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?\n                            valid_d1 : valid_i; \n    assign VALID         = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n  end else begin : gnvalid\n    assign VALID         = 0;\n  end endgenerate // gvalid\n\n  //Trim data count differently depending on set widths\n  generate if (C_HAS_DATA_COUNT == 1) begin : gdc\n    always @* begin\n      diff_count <= wr_pntr - rd_pntr;\n      if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin\n        DATA_COUNT[C_RD_PNTR_WIDTH-1:0]  <= diff_count;\n        DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; \n      end else begin\n        DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];\n      end\n    end\n//  end else begin : gndc\n//    always @* DATA_COUNT <= 0;\n  end endgenerate // gdc\n\n  //Underflow may change behavior based on latency or active-low\n  generate if (C_HAS_UNDERFLOW==1) begin : guf\n    assign underflow_i   = ideal_underflow;\n    assign UNDERFLOW     = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n  end else begin : gnuf\n    assign UNDERFLOW     = 0;\n  end endgenerate // guf\n \n\n  //Write acknowledge may be active low \n  generate if (C_HAS_WR_ACK==1) begin : gwr_ack\n    assign WR_ACK        = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n  end else begin : gnwr_ack\n    assign WR_ACK        = 0;\n  end endgenerate // gwr_ack\n\n\n  /*****************************************************************************\n   * Internal reset logic \n   ****************************************************************************/\n  assign srst_i        = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;\n  assign rst_i            = C_HAS_RST ? RST : 0;\n  assign srst_wrst_busy   = srst_i;\n  assign srst_rrst_busy   = srst_i;\n\n   /**************************************************************************\n    * Assorted registers for delayed versions of signals\n    **************************************************************************/\n   //Capture delayed version of valid\n   generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20\n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1 <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n           end else begin\n              valid_d1 <= #`TCQ valid_i;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n     end \n   endgenerate // blockVL20\n\n  generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin \n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1   <= 1'b0;\n           valid_both <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n              valid_both <= #`TCQ 1'b0;\n              \n           end else begin\n              valid_both <= #`TCQ valid_i;\n               valid_d1 <= #`TCQ valid_both;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n  end\n endgenerate // blockVL20\n\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge CLK or posedge rst_i) begin\n         if (rst_i) begin\n           stage1_valid     <= #`TCQ 0;\n           stage2_valid     <= #`TCQ 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n\n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc\n       assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc\n       assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n   \n   //reg ram_rd_en_d1 = 1'b0;\n   //Capture delayed version of dout\n   generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         ram_rd_en_d1 <= #`TCQ 1'b0;\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n        end\n      end else begin\n         ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n         if (srst_rrst_busy) begin\n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            // Reset err_type only if ECC is not selected\n            if (C_USE_ECC == 0) begin\n               err_type_d1   <= #`TCQ 0;\n               err_type_both <= #`TCQ 0;\n            end\n            // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n            if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n            end \n         if (C_USE_DOUT_RST == 1) begin\n           // @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         end else begin\n            if (ram_rd_en_d1 ) begin\n            ideal_dout_d1 <= #`TCQ ideal_dout;\n            err_type_d1   <= #`TCQ err_type;\n            end\n         end\n      end    \n   end   // always\nend\nendgenerate \n\n//no safety ckt with both registers\n generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n          ram_rd_en_d1 <= #`TCQ 1'b0;\n          fab_rd_en_d1 <= #`TCQ 1'b0;\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val; \n            \n      end\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val;\n       end\n      end else begin\n         if (srst_rrst_busy) begin \n           ram_rd_en_d1 <= #`TCQ 1'b0;\n           fab_rd_en_d1 <= #`TCQ 1'b0;\n           // Reset err_type only if ECC is not selected\n           if (C_USE_ECC == 0) begin\n              err_type_d1   <= #`TCQ 0;\n              err_type_both <= #`TCQ 0;\n           end\n           // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n           if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n              ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end \n           if (C_USE_DOUT_RST == 1) begin\n             ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end\n         end else begin\n           ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n           fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);\n           if (ram_rd_en_d1 ) begin\n             ideal_dout_both <= #`TCQ ideal_dout;\n             err_type_both   <= #`TCQ err_type;\n           end\n           if (fab_rd_en_d1 ) begin\n             ideal_dout_d1 <= #`TCQ ideal_dout_both;\n             err_type_d1   <= #`TCQ err_type_both;\n           end\n         end\n      end    \n   end   // always\nend\nendgenerate \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n     always @(posedge CLK) begin\n       ideal_overflow    <= #`TCQ WR_EN & full_i;\n     end\n   end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n     always @(posedge CLK) begin\n       //ideal_overflow    <= #`TCQ WR_EN & (rst_i | full_i);\n       ideal_overflow    <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);\n     end\n   end endgenerate // blockOF20\n \n   generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n     always @(posedge CLK) begin\n       ideal_underflow   <= #`TCQ empty_i & RD_EN;\n     end\n   end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n     always @(posedge CLK) begin\n       //ideal_underflow   <= #`TCQ (rst_i | empty_i) & RD_EN;\n       ideal_underflow   <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;\n     end\n   end endgenerate // blockUF20\n\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n\n  /*************************************************************************\n   * Write and Read Logic  \n   ************************************************************************/\n   wire              write_allow;\n   wire              read_allow;\n   wire              read_allow_dc;\n   wire              write_only;\n   wire              read_only;\n   //wire              write_only_q;\n   reg              write_only_q;\n   //wire              read_only_q;\n   reg              read_only_q;\n   reg              full_reg;\n   reg              rst_full_ff_reg1;\n   reg              rst_full_ff_reg2;\n   wire              ram_full_comb;\n   wire              carry;\n   \n   assign write_allow  = WR_EN & ~full_i;\n   assign read_allow   = RD_EN & ~empty_i;\n   assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;\n   //assign write_only   = write_allow & ~read_allow;\n   //assign write_only_q = write_allow_q;\n   //assign read_only    = read_allow    & ~write_allow;\n   //assign read_only_q  = read_allow_q ;\n   wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;\n   wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;\n   wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;\n\n   assign diff_pntr_pe_max = DIFF_MAX_RD;\n   assign diff_pntr_max = DIFF_MAX_WR;\n\n\n\n   generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym\n    assign write_only   = write_allow & ~read_allow;\n    assign read_only    = read_allow    & ~write_allow;\n    end endgenerate\n    generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd\n     assign read_only   = read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;\n     assign write_only    = write_allow    & ~(read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n    generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr\n     assign read_only   = read_allow & ~(write_allow  & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n     assign write_only    = write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;\n    end endgenerate\n\n\n   //-----------------------------------------------------------------------------\n   // Write and Read pointer generation\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       wr_pntr         <= 0;\n       rd_pntr         <= 0;\n     end else begin\n       if (srst_i) begin\n         wr_pntr       <= #`TCQ 0;\n         rd_pntr       <= #`TCQ 0;\n       end else begin\n         if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;\n         if (read_allow)  rd_pntr <= #`TCQ rd_pntr + 1;\n       end\n     end\n   end\n\n   generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout\n   always @(posedge CLK) begin\n     if (write_allow) begin\n       if (ENABLE_ERR_INJECTION == 1)\n         memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};\n       else\n         memory[wr_pntr] <= #`TCQ DIN;\n     end\n   end\n\n   reg  [C_DATA_WIDTH-1:0] dout_tmp_q;\n   reg [C_DATA_WIDTH-1:0] dout_tmp = 0;\n   reg  [C_DATA_WIDTH-1:0] dout_tmp1 = 0;\n   always @(posedge CLK) begin\n     dout_tmp_q <= #`TCQ ideal_dout;\n   end\n\n\n\n     always @* begin\n       if (read_allow)\n         ideal_dout <= memory[rd_pntr];\n       else\n         ideal_dout <= dout_tmp_q;\n     end\n   end endgenerate // gll_dm_dout\n\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   assign ram_rd_en        = RD_EN & !EMPTY;\n\n   //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   generate if (C_FIFO_TYPE != 2) begin : gnll_din\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i == 1'b1) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n\n     end else begin //rst_i==0\n     if (srst_wrst_busy) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n     end else begin//srst_i=0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n         end else begin\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error  \n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           //end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //srst_i==0\n     end //wr_rst_i==0\n   end // gen_fifo_w\n    end endgenerate\n\n   generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout\n     always @(posedge CLK) begin\n       if (rst_i || srst_rrst_busy) begin\n         if (C_USE_DOUT_RST == 1) begin\n           ideal_dout <= #`TCQ dout_reset_val;\n           ideal_dout_both <= #`TCQ dout_reset_val;\n         end\n       end\n     end\n    end endgenerate\n\n\n\n\n   generate if (C_FIFO_TYPE != 2) begin : gnll_dout\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_r\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n\n     end else begin //rd_rst_i==0\n     if (srst_rrst_busy) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets synchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= #`TCQ 0;\n         err_type_both    <= #`TCQ 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n      end //srst_i\n      else begin\n\n       //rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n         if (RD_EN == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end \n           else \n             begin\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n         end\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //s_rst_i==0\n     end //rd_rst_i==0\n   end //always\n  end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate diff_pntr for PROG_FULL generation\n   // Generate diff_pntr_pe for PROG_EMPTY generation\n   //-----------------------------------------------------------------------------\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         write_only_q   <= 1'b0;\n         read_only_q    <= 1'b0;\n         diff_pntr_reg1       <= 0;\n         diff_pntr_pe_reg1    <= 0;\n         diff_pntr_reg2       <= 0;\n         diff_pntr_pe_reg2    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_rrst_busy) begin\n           read_only_q  <= #`TCQ 1'b0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n           diff_pntr_pe_reg2  <= #`TCQ 0;\n          end\n          if (srst_wrst_busy) begin\n           write_only_q <= #`TCQ 1'b0;\n           diff_pntr_reg1     <= #`TCQ 0;\n           diff_pntr_reg2     <= #`TCQ 0;\n          end\n         end else begin\n           write_only_q <= #`TCQ write_only;\n           read_only_q  <= #`TCQ read_only;\n           diff_pntr_reg2  <= #`TCQ diff_pntr_reg1;\n           diff_pntr_pe_reg2  <= #`TCQ diff_pntr_pe_reg1;\n\n           // Add 1 to the difference pointer value when only write happens.\n           if (write_only)  \n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;\n           else\n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;\n\n           // Add 1 to the difference pointer value when write or both write & read or no write & read happen.\n           if (read_only)  \n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;\n           else\n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;\n         end\n       end\n     end\n   assign diff_pntr_pe = diff_pntr_pe_reg1;\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow\n\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym\n    assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};\n    assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         diff_pntr_pe_asym    <= 0;\n         diff_pntr_reg1       <= 0;\n         full_reg             <= 0;\n         rst_full_ff_reg1     <= 1;\n         rst_full_ff_reg2     <= 1;\n         diff_pntr_pe_reg1    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_wrst_busy)\n           diff_pntr_reg1     <= #`TCQ 0;\n          if (srst_rrst_busy)\n           full_reg             <=  #`TCQ 0;\n           rst_full_ff_reg1     <=  #`TCQ 1;\n           rst_full_ff_reg2     <=  #`TCQ 1;\n           diff_pntr_pe_asym    <=  #`TCQ 0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n         end else begin\n             diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;\n             full_reg          <= #`TCQ full_i;\n             rst_full_ff_reg1  <=  #`TCQ RST_FULL_FF;\n             rst_full_ff_reg2  <=  #`TCQ rst_full_ff_reg1;\n           if (~full_i) begin  \n             diff_pntr_reg1 <=  #`TCQ wr_pntr - adj_rd_pntr_wr;\n          end\n         end\n       end\n     end\n   assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));\n   assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow_asym\n\n\n   //-----------------------------------------------------------------------------\n   // Generate FULL flag\n   //-----------------------------------------------------------------------------\n   wire                 comp0;\n   wire                 comp1;\n   wire                 going_full;\n   wire                 leaving_full;\n \n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin :  gpad \t\n    assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;\n    assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin :  gtrim \n    assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n  end endgenerate\n\n   assign comp1         = (adj_rd_pntr_wr == (wr_pntr + 1'b1));\n   assign comp0         = (adj_rd_pntr_wr == wr_pntr);\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp\n     assign going_full    = (comp1 & write_allow & ~read_allow);\n     assign leaving_full  = (comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym\n      assign going_full = (comp1 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_full = (comp0 & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp \n      assign going_full = (comp1 & write_allow & ~read_allow);\n      assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n\n   assign ram_full_comb = going_full | (~leaving_full & full_i);\n\n   generate if (C_HAS_RST == 1) begin : grst_full\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF & C_HAS_RST)\n         full_i   <= C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_SRST == 1) begin : gsrst_full\n     always @(posedge CLK) begin\n       if (srst_wrst_busy)\n         full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_full\n     always @(posedge CLK) begin\n         full_i   <= #`TCQ ram_full_comb;\n     end\n   end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate EMPTY flag\n   //-----------------------------------------------------------------------------\n   wire                 ecomp0;\n   wire                 ecomp1;\n   wire                 going_empty;\n   wire                 leaving_empty;\n   wire                 ram_empty_comb;\n\n  \n generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin :  pad \t\n    assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n    assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin :  trim \n    assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n  end endgenerate\n\n   assign ecomp1         = (adj_wr_pntr_rd == (rd_pntr + 1'b1));\n   assign ecomp0         = (adj_wr_pntr_rd == rd_pntr);\n\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp\n     assign going_empty    = (ecomp1 & ~write_allow & read_allow);\n     assign leaving_empty  = (ecomp0 & write_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp\n      assign going_empty = (ecomp1 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_empty = (ecomp0 & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp \n      assign going_empty = (ecomp1 & ~write_allow & read_allow);\n      assign leaving_empty =(ecomp0 & write_allow);\n    end endgenerate\n\n\n\n    assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);\n\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       empty_i  <= 1'b1;\n     else if (srst_rrst_busy)\n       empty_i  <= #`TCQ 1'b1;\n     else\n       empty_i  <= #`TCQ ram_empty_comb;\n    end\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       EMPTY_FB     <= 1'b1;\n     end else begin\n       if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))\n         EMPTY_FB   <= #`TCQ 1'b1;\n       else\n         EMPTY_FB   <= #`TCQ ram_empty_comb;\n     end\n   end // always\n\n   //-----------------------------------------------------------------------------\n   // Generate Read and write data counts for asymmetic common clock\n   //-----------------------------------------------------------------------------\n\n    reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; \n    wire [C_GRTR_PNTR_WIDTH :0] ratio; \n    wire decr_by_one;\n    wire incr_by_ratio;\n    wire incr_by_one;\n    wire decr_by_ratio;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n\n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr \n      assign ratio         = C_DEPTH_RATIO_RD;\n      assign decr_by_one   = (IS_FWFT == 1)? read_allow_dc : read_allow;\n      assign incr_by_ratio = write_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (decr_by_one) begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc - 1;\n           else\n\t    count_dc <= #`TCQ count_dc - 1  + ratio ;\n\t end\n\t else begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc + ratio ;\n\tend\n       end\n       end\n\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n\n    end endgenerate\n\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd \n      assign ratio         = C_DEPTH_RATIO_WR;\n      assign incr_by_one   = write_allow;\n      assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (incr_by_one) begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc + 1;\n           else\n\t    count_dc <= #`TCQ count_dc + 1  - ratio ;\n\t end\n\t else begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc - ratio ;\n\tend\n       end\n       end\n\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n\n    end endgenerate\n\n\n\n\n\n\n   //-----------------------------------------------------------------------------\n   // Generate WR_ACK flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_wr_ack  <= 1'b0;\n     else if (srst_wrst_busy)\n       ideal_wr_ack  <= #`TCQ 1'b0;\n     else if (WR_EN & ~full_i)\n       ideal_wr_ack  <= #`TCQ 1'b1;\n     else\n       ideal_wr_ack  <= #`TCQ 1'b0;\n    end\n\n   //-----------------------------------------------------------------------------\n   // Generate VALID flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_valid  <= 1'b0;\n     else if (srst_rrst_busy)\n       ideal_valid  <= #`TCQ 1'b0;\n     else if (RD_EN & ~empty_i)\n       ideal_valid  <= #`TCQ 1'b1;\n     else\n       ideal_valid  <= #`TCQ 1'b0;\n    end\n\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_FULL flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss\n\n     wire                 fcomp2;\n     wire                 going_afull;\n     wire                 leaving_afull;\n     wire                 ram_afull_comb;\n\n\n   assign fcomp2         = (adj_rd_pntr_wr == (wr_pntr + 2'h2));\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp\n     assign going_afull    = (fcomp2 & write_allow & ~read_allow);\n     assign leaving_afull  = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym\n      assign going_afull = (fcomp2 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_afull = (comp1 & (~write_allow) & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp \n      assign going_afull = (fcomp2 & write_allow & ~read_allow);\n      assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n     assign ram_afull_comb  = going_afull | (~leaving_afull & almost_full_i);\n\n\n    generate if (C_HAS_RST == 1) begin : grst_afull\n      always @(posedge CLK or posedge RST_FULL_FF) begin\n        if (RST_FULL_FF & C_HAS_RST)\n          almost_full_i   <= C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_SRST == 1) begin : gsrst_afull\n      always @(posedge CLK) begin\n        if (srst_wrst_busy)\n          almost_full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_afull\n      always @(posedge CLK) begin\n          almost_full_i   <= #`TCQ ram_afull_comb;\n      end\n    end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_EMPTY flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss\n\n     wire                 ecomp2;\n     wire                 going_aempty;\n     wire                 leaving_aempty;\n     wire                 ram_aempty_comb;\n      \n     assign ecomp2          = (adj_wr_pntr_rd == (rd_pntr + 2'h2));\n   \n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp\n     assign going_aempty    = (ecomp2 & ~write_allow & read_allow);\n     assign leaving_aempty  = (ecomp1 & write_allow & ~read_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp\n      assign going_aempty = (ecomp2 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp \n      assign going_aempty = (ecomp2 & ~write_allow & read_allow);\n      assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);\n    end endgenerate\n\n\n     assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);\n\n     always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         almost_empty_i  <= 1'b1;\n       else if (srst_rrst_busy)\n         almost_empty_i  <= #`TCQ 1'b1;\n       else\n         almost_empty_i  <= #`TCQ ram_aempty_comb;\n      end\n  // end endgenerate // gae_ss\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL\n   //-----------------------------------------------------------------------------\n\n   localparam  C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT \n                                  C_PROG_FULL_THRESH_ASSERT_VAL; // STD\n   localparam  C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT\n                                  C_PROG_FULL_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;   \n   generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin \n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n          prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr>= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  ((diff_pntr) < C_PF_ASSERT_VAL )\n        prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate // single_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr >= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n       else if  (diff_pntr < C_PF_NEGATE_VAL)\n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate //multiple_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT\n                                               PROG_FULL_THRESH; // STD\n   generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input\n\n     always @(posedge CLK or posedge RST_FULL_FF) begin//0\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin //1\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin//2 \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin//3\n           if (diff_pntr > pf3_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if (diff_pntr == pf3_assert_val) begin//4\n             if (read_only_q)\n               prog_full_i <= #`TCQ 1'b0;\n             else\n               prog_full_i <= #`TCQ 1'b1;\n           end else//4\n             prog_full_i <= #`TCQ 1'b0;\n         end else//3\n           prog_full_i <= #`TCQ prog_full_i;\n       end //2\n       else begin//5\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin//6 \n        if (diff_pntr >= pf3_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  (diff_pntr < pf3_assert_val) begin//7\n         prog_full_i <= #`TCQ 1'b0;\n       end//7\n       end//6\n      else\n           prog_full_i <= #`TCQ prog_full_i;\n       end//5\n     end//1\n     end//0\n   end endgenerate //single_pf_input\n  \n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_ASSERT; // STD\n   wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_NEGATE; // STD\n\n   generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin\n           if (diff_pntr >= pf_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if ((diff_pntr == pf_negate_val && read_only_q) ||\n                  diff_pntr < pf_negate_val)\n             prog_full_i <= #`TCQ 1'b0;\n           else\n             prog_full_i <= #`TCQ prog_full_i;\n         end else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin \n        if (diff_pntr >= pf_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n       else if (diff_pntr < pf_negate_val) \n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n\n     end\n   end\n   end endgenerate //multiple_pf_inputs\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY\n   //-----------------------------------------------------------------------------\n   localparam  C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD\n   localparam  C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i) \n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy) \n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL)\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > C_PE_ASSERT_VAL)\n         prog_empty_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n     end\n     end\n   end endgenerate // single_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > C_PE_NEGATE_VAL) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n\n     end\n\n     end\n   end endgenerate //multiple_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH -2) : // FWFT\n                                                PROG_EMPTY_THRESH; // STD\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe < pe3_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (diff_pntr_pe == pe3_assert_val) begin\n             if (write_only_q)\n               prog_empty_i <= #`TCQ 1'b0;\n             else\n               prog_empty_i <= #`TCQ 1'b1;\n           end else\n             prog_empty_i <= #`TCQ 1'b0;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe3_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > pe3_assert_val)\n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n\n     end\n   end endgenerate // single_pe_input\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_ASSERT; // STD\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_NEGATE; // STD\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n      else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe <= pe4_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || \n                     (diff_pntr_pe > pe4_negate_val)) begin\n             prog_empty_i <= #`TCQ 1'b0;\n           end else\n             prog_empty_i <= #`TCQ prog_empty_i;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe4_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > pe4_negate_val) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n     end\n   end endgenerate // multiple_pe_inputs\n\nendmodule // fifo_generator_v13_2_5_bhv_ver_ss\n\n\n\n/**************************************************************************\n * First-Word Fall-Through module (preload 0)\n **************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_preload0\n  #(\n    parameter  C_DOUT_RST_VAL            = \"\",\n    parameter  C_DOUT_WIDTH              = 8,\n    parameter  C_HAS_RST                 = 0,\n    parameter  C_ENABLE_RST_SYNC         = 0,\n    parameter  C_HAS_SRST                = 0,\n    parameter  C_USE_EMBEDDED_REG        = 0,\n    parameter  C_EN_SAFETY_CKT           = 0, \n    parameter  C_USE_DOUT_RST            = 0,\n    parameter  C_USE_ECC                 = 0,\n    parameter  C_USERVALID_LOW           = 0,\n    parameter  C_USERUNDERFLOW_LOW       = 0,\n    parameter  C_MEMORY_TYPE             = 0,\n    parameter  C_FIFO_TYPE               = 0\n  )\n  (\n    //Inputs\n    input                          SAFETY_CKT_RD_RST,\n    input                          RD_CLK,\n    input                          RD_RST,\n    input                          SRST,\n    input                          WR_RST_BUSY,\n    input                          RD_RST_BUSY,\n    input                          RD_EN,\n    input                          FIFOEMPTY,\n    input       [C_DOUT_WIDTH-1:0] FIFODATA,\n    input                          FIFOSBITERR,\n    input                          FIFODBITERR,\n   \n    //Outputs\n    output reg  [C_DOUT_WIDTH-1:0] USERDATA,\n    output                         USERVALID,\n    output                         USERUNDERFLOW,\n    output                         USEREMPTY,\n    output                         USERALMOSTEMPTY,\n    output                         RAMVALID,\n    output                         FIFORDEN,\n    output reg                     USERSBITERR,\n    output reg                     USERDBITERR,\n    output reg                     STAGE2_REG_EN,\n    output                         fab_read_data_valid_i_o,\n    output                         read_data_valid_i_o,\n    output                         ram_valid_i_o,\n    output      [1:0]              VALID_STAGES \n  );\n //Internal signals\n wire                      preloadstage1;\n wire                      preloadstage2;\n reg                       ram_valid_i;\n reg                       fab_valid;\n reg                       read_data_valid_i;\n reg                       fab_read_data_valid_i;\n reg                       fab_read_data_valid_i_1;\n reg                       ram_valid_i_d;\n reg                       read_data_valid_i_d;\n reg                       fab_read_data_valid_i_d;\n wire                      ram_regout_en;\n reg                       ram_regout_en_d1;\n reg                       ram_regout_en_d2;\n wire                      fab_regout_en;\n wire                      ram_rd_en;\n reg                       empty_i        = 1'b1;\n reg                       empty_sckt     = 1'b1;\n reg                       sckt_rrst_q    = 1'b0;\n reg                       sckt_rrst_done = 1'b0;\n reg                       empty_q        = 1'b1;\n reg                       rd_en_q        = 1'b0;\n reg                       almost_empty_i = 1'b1;\n reg                       almost_empty_q = 1'b1;\n wire                      rd_rst_i;\n wire                      srst_i;\n reg  [C_DOUT_WIDTH-1:0]   userdata_both;\n wire                      uservalid_both;\n wire                      uservalid_one;\n reg                       user_sbiterr_both = 1'b0;\n reg                       user_dbiterr_both = 1'b0;\n  \nassign ram_valid_i_o = ram_valid_i;\nassign read_data_valid_i_o = read_data_valid_i;\nassign fab_read_data_valid_i_o = fab_read_data_valid_i; \n\n\n\n/*************************************************************************\n* FUNCTIONS\n*************************************************************************/\n\n   /*************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***********************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n   \n   //*************************************************************************\n   //  Set power-on states for regs\n   //*************************************************************************\n   initial begin\n      ram_valid_i       = 1'b0;\n      fab_valid         = 1'b0;\n      read_data_valid_i = 1'b0;\n      fab_read_data_valid_i = 1'b0;\n      fab_read_data_valid_i_1 = 1'b0;\n      USERDATA          = hexstr_conv(C_DOUT_RST_VAL);\n      userdata_both          = hexstr_conv(C_DOUT_RST_VAL);\n      USERSBITERR       = 1'b0;\n      USERDBITERR       = 1'b0;\n      user_sbiterr_both = 1'b0;\n      user_dbiterr_both = 1'b0;\n   end //initial\n\n   //***************************************************************************\n   //  connect up optional reset\n   //***************************************************************************\n   assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;\n   assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;\n\n   reg  sckt_rd_rst_fwft = 1'b0;\n   reg  fwft_rst_done_i  = 1'b0;\n   wire fwft_rst_done;\n   assign fwft_rst_done = 1'b1;//C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;\n   always @ (posedge RD_CLK) begin\n     sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;\n   end\n\n   always @ (posedge rd_rst_i or posedge RD_CLK) begin\n     if (rd_rst_i)\n       fwft_rst_done_i  <= 1'b0;\n     else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)\n       fwft_rst_done_i  <= #`TCQ 1'b1;\n   end\n\n   localparam INVALID             = 0;\n   localparam STAGE1_VALID        = 2;\n   localparam STAGE2_VALID        = 1;\n   localparam BOTH_STAGES_VALID   = 3;\n\n   reg  [1:0] curr_fwft_state = INVALID;\n   reg  [1:0] next_fwft_state = INVALID;\n\n\ngenerate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin\n         always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n \n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n     \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n    \n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = preloadstage2;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;\n   end\nendgenerate // gnll_fifo\n\n   reg curr_state         = 0;\n   reg next_state         = 0;\n   reg leaving_empty_fwft = 0;\n   reg going_empty_fwft   = 0;\n   reg empty_i_q          = 0;\n   reg ram_rd_en_fwft     = 0;\n   generate if (C_FIFO_TYPE == 2) begin : gll_fifo\n     always @* begin // FSM fo FWFT\n       case (curr_state)\n         1'b0: begin\n           if (~FIFOEMPTY)\n             next_state <= 1'b1;\n           else\n             next_state <= 1'b0;\n           end\n         1'b1: begin\n           if (FIFOEMPTY && RD_EN)\n             next_state <= 1'b0;\n           else\n             next_state <= 1'b1;\n           end\n         default: next_state <= 1'b0;\n       endcase\n     end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_i       <= 1'b1;\n           empty_i_q     <= 1'b1;\n           ram_valid_i   <= 1'b0;\n        end else if (srst_i) begin\n           empty_i       <= #`TCQ 1'b1;\n           empty_i_q     <= #`TCQ 1'b1;\n           ram_valid_i   <= #`TCQ 1'b0;\n        end else begin\n           empty_i       <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);\n           empty_i_q     <= #`TCQ FIFOEMPTY;\n           ram_valid_i   <= #`TCQ next_state;\n        end\n     end //always\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n           curr_state    <= 1'b0;\n        end else if (srst_i) begin\n           curr_state    <= #`TCQ 1'b0;\n        end else begin\n           curr_state    <= #`TCQ next_state;\n        end\n     end //always\n\n     wire                  fe_of_empty; \n     assign fe_of_empty   = empty_i_q & ~FIFOEMPTY;\n\n     always @* begin // Finding leaving empty\n       case (curr_state)\n         1'b0:    leaving_empty_fwft <= fe_of_empty;\n         1'b1:    leaving_empty_fwft <= 1'b1;\n         default: leaving_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Finding going empty\n       case (curr_state)\n         1'b1:    going_empty_fwft <= FIFOEMPTY & RD_EN;\n         default: going_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Generating FWFT rd_en\n       case (curr_state)\n         1'b0:    ram_rd_en_fwft <= ~FIFOEMPTY;\n         1'b1:    ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;\n         default: ram_rd_en_fwft <= 1'b0;\n       endcase\n     end\n\n     assign ram_regout_en = ram_rd_en_fwft;\n     //assign ram_regout_en_d1 = ram_rd_en_fwft;\n     //assign ram_regout_en_d2 = ram_rd_en_fwft;\n     assign ram_rd_en     = ram_rd_en_fwft;\n   end endgenerate // gll_fifo\n\n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false.\n   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n   generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           ram_valid_i     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              ram_valid_i     <= #`TCQ 1'b0;\n           end else begin\n              if (ram_rd_en == 1'b1) begin\n                 ram_valid_i   <= #`TCQ 1'b1;\n              end else begin\n                 if (ram_regout_en == 1'b1)\n                   ram_valid_i <= #`TCQ 1'b0;\n                 else\n                   ram_valid_i <= #`TCQ ram_valid_i;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_ram_valid\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n  \n generate if(C_USE_EMBEDDED_REG < 3) begin\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else\n        read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);\n   end //always\nend \nendgenerate\n\n   \n   \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n generate if ( C_USE_EMBEDDED_REG < 3) begin\n  always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin         // asynchronous reset (active high)\n             almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ FIFOEMPTY;\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n   \n   \n     \n  // BRAM resets synchronously\n generate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin\n   always @ ( posedge rd_rst_i)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n           @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n             USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end  else if (fwft_rst_done) begin\n            if (ram_regout_en) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end\n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n//safety ckt with one register\ngenerate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n            @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n        end\n     end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n          //@(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end \n       end\n        else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n            //  @(posedge RD_CLK)\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end else if (fwft_rst_done) begin\n            if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end          \n          end\n        end\n       end //always\n  end //if\nendgenerate\n\n\ngenerate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin\n         \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d1 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d1 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d1 <= #`TCQ ram_regout_en;\n                 end\n            end //always\n   //  assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));\n       assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d2 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d2 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;\n                 end\n            end //always\n\n    \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n     always @ (posedge RD_CLK) begin\n        ram_valid_i_d <= #`TCQ ram_valid_i;\n        read_data_valid_i_d <= #`TCQ read_data_valid_i;\n        fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;\n\n     end\n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n    \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;\n   end\n   endgenerate // gnll_fifo\n\n   \n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n     generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid\n\n     \n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           fab_valid     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              fab_valid    <= #`TCQ 1'b0;\n           end else begin\n              if (ram_regout_en == 1'b1) begin\n                 fab_valid  <= #`TCQ 1'b1;\n              end else begin\n                 if (fab_regout_en == 1'b1)\n                   fab_valid <= #`TCQ 1'b0;\n                 else\n                   fab_valid <= #`TCQ fab_valid;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_fab_valid\n\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n    generate if(C_USE_EMBEDDED_REG == 3) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else begin\n        if (ram_regout_en == 1'b1) begin\n          read_data_valid_i <= #`TCQ 1'b1;\n        end else begin\n         if (fab_regout_en == 1'b1)\n          read_data_valid_i <= #`TCQ 1'b0;\n        else\n          read_data_valid_i <= #`TCQ read_data_valid_i;\n        end \n      end \n   end //always\nend\nendgenerate\n\n//generate if(C_USE_EMBEDDED_REG == 3) begin\n//   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n//      if (rd_rst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//      else if (srst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//\n//      if (ram_regout_en == 1'b1) begin\n//        fab_read_data_valid_i <= #`TCQ 1'b0;\n//      end else begin\n//       if (fab_regout_en == 1'b1)\n//        fab_read_data_valid_i <= #`TCQ 1'b1;\n//      else\n//        fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;\n//      end \n//   end //always\n//end\n//endgenerate\n\n     generate if(C_USE_EMBEDDED_REG == 3 ) begin \n    always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid\n      if (rd_rst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else \n        fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);\n   end //always\nend\nendgenerate\n \nalways @ (posedge RD_CLK ) begin : proc_del1\n             begin\n                 fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;\n              end\n            end //always\n \n \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty_both\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n   reg FIFOEMPTY_1;\n   generate if (C_USE_EMBEDDED_REG == 3 ) begin\n    always @(posedge RD_CLK) begin\n            FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;\n           end\n    end\nendgenerate\n    generate if (C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n   begin\n      if (rd_rst_i) begin         // asynchronous reset (active high)\n           almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ (~ram_valid_i);\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_sckt <= #`TCQ 1'b1;\n           sckt_rrst_q <= #`TCQ 1'b0;\n           sckt_rrst_done <= #`TCQ 1'b0;\n        end else begin\n           sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;\n           if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin\n              sckt_rrst_done <= #`TCQ 1'b1;\n           end else if (sckt_rrst_done) begin\n              // rising clock edge\n              empty_sckt <= #`TCQ 1'b0;\n           end\n        end\n     end //always\n   \n   \n//   assign USEREMPTY       = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;\n   assign USEREMPTY       = empty_i;\n   assign USERALMOSTEMPTY = almost_empty_i;\n   assign FIFORDEN        = ram_rd_en;\n   assign RAMVALID        = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;\n   assign uservalid_both       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3)  ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);\n   assign uservalid_one       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3)  ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);\n   assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;\n   assign USERUNDERFLOW   = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;\n//no safety ckt with both reg\ngenerate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n            USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              userdata_both   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end else begin\n            if (fwft_rst_done) begin\n              if (ram_regout_en) begin\n                 userdata_both     <= #`TCQ FIFODATA; \n                 user_dbiterr_both <= #`TCQ FIFODBITERR;\n                 user_sbiterr_both <= #`TCQ FIFOSBITERR; \n              end\n              if (fab_regout_en) begin\n                 USERDATA     <= #`TCQ userdata_both;\n                 USERDBITERR  <= #`TCQ user_dbiterr_both;\n                 USERSBITERR  <= #`TCQ user_sbiterr_both; \n              end             \n            end             \n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n\n//safety_ckt with both registers\n generate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always @ (posedge RD_CLK) begin\n          if (rd_rst_i || srst_i) begin\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n              @(posedge RD_CLK)\n              USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n               userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end\n        end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n     if (rd_rst_i) begin //asynchronous reset (active high)\n       if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n         USERSBITERR       <= #`TCQ 0;\n         USERDBITERR       <= #`TCQ 0;\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end\n       // DRAM resets asynchronously\n       if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n         USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end \n     end else begin // rising clock edge\n       if (srst_i) begin\n         if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n           USERSBITERR       <= #`TCQ 0;\n           USERDBITERR       <= #`TCQ 0;\n           user_sbiterr_both <= #`TCQ 0;\n           user_dbiterr_both <= #`TCQ 0;\n         end\n         if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n           USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end\n       end else if (fwft_rst_done) begin\n         if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            userdata_both     <= #`TCQ FIFODATA;\n            user_dbiterr_both <= #`TCQ FIFODBITERR;\n            user_sbiterr_both <= #`TCQ FIFOSBITERR; \n         end\n         if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            USERDATA          <= #`TCQ userdata_both;\n            USERDBITERR       <= #`TCQ user_dbiterr_both;\n            USERSBITERR       <= #`TCQ user_sbiterr_both;\n         end\n       end\n     end\n   end //always\n  end //if\nendgenerate\n\nendmodule //fifo_generator_v13_2_5_bhv_ver_preload0\n\n\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Register one AXI channel on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   reg_slice\n//\n//--------------------------------------------------------------------------\n\nmodule fifo_generator_v13_2_5_axic_reg_slice #\n  (\n   parameter C_FAMILY     = \"virtex7\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   )\n  (\n   // System Signals\n   input  wire                      ACLK,\n   input  wire                      ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0]   S_PAYLOAD_DATA,\n   input  wire                      S_VALID,\n   output wire                      S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0]   M_PAYLOAD_DATA,\n   output wire                      M_VALID,\n   input  wire                      M_READY\n   );\n\n  localparam RST_SYNC_STAGES = 5;\n  localparam RST_BUSY_LEN    = 6;\n  reg [1:0] arst_sync_wr  = 2'b11;\n  reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n  wire sync_reset;\n  wire extnd_reset;\n\n\n  always @(posedge ARESET or posedge ACLK) begin\n    if (ARESET)\n      arst_sync_wr <= 2'b11;\n    else\n      arst_sync_wr <= #`TCQ {arst_sync_wr[0], 1'b0};\n  end\n\n  always @(posedge ACLK) begin\n    sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[1]};\n  end\n\n  assign sync_reset     = |sckt_wr_rst_cc[RST_BUSY_LEN-5:0] | arst_sync_wr[1]; \n  assign extnd_reset    = |sckt_wr_rst_cc | arst_sync_wr[1];\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000)\n    begin\n      reg [1:0] state;\n      localparam [1:0] \n        ZERO = 2'b10,\n        ONE  = 2'b11,\n        TWO  = 2'b01;\n      \n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg [C_DATA_WIDTH-1:0] storage_data2 = 0;\n      reg                    load_s1;\n      wire                   load_s2;\n      wire                   load_s1_from_s2;\n      reg                    s_ready_i; //local signal of output\n      wire                   m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with either slave side data or from storage2\n      always @(posedge ACLK) \n      begin\n        if (load_s1)\n          if (load_s1_from_s2)\n            storage_data1 <= storage_data2;\n          else\n            storage_data1 <= S_PAYLOAD_DATA;        \n      end\n\n      // Load storage2 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data1;\n\n      // Always load s2 on a valid transaction even if it's unnecessary\n      assign load_s2 = S_VALID & s_ready_i;\n\n      // Loading s1\n      always @ *\n      begin\n        if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction\n             // Load when ONE if we both have read and write at the same time\n             ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||\n             // Load when TWO and we have a transaction on Master side\n             ((state == TWO) && (M_READY == 1)))\n          load_s1 = 1'b1;\n        else\n          load_s1 = 1'b0;\n      end // always @ *\n\n      assign load_s1_from_s2 = (state == TWO);\n                       \n      // State Machine for handling output signals\n      always @(posedge ACLK) begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          state <= ZERO;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          case (state)\n            // No transaction stored locally\n            ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE\n\n            // One transaction stored locally\n            ONE: begin\n              if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO\n              if (~M_READY & S_VALID) begin\n                state <= TWO;  // Got another one so move to TWO\n                s_ready_i <= 1'b0;\n              end\n            end\n\n            // TWO transaction stored locally\n            TWO: if (M_READY) begin\n              state <= ONE; // Read out one so move to ONE\n              s_ready_i <= 1'b1;\n            end\n          endcase // case (state)\n        end\n      end // always @ (posedge ACLK)\n      \n      assign m_valid_i = state[0];\n\n    end // if (C_REG_CONFIG == 1)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000001)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg                    s_ready_i; //local signal of output\n      reg                    m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b0;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else if (m_valid_i & M_READY) begin\n          s_ready_i <= 1'b1;\n          m_valid_i <= 1'b0;\n        end else if (S_VALID & s_ready_i) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b1;\n        end\n        if (~m_valid_i) begin\n          storage_data1 <= S_PAYLOAD_DATA;        \n        end\n      end\n      assign M_PAYLOAD_DATA = storage_data1;\n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // reg_slice\n", "num_lines": 10520}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1\n// IP Revision: 21\n\n(* X_CORE_INFO = \"axi_clock_converter_v2_1_21_axi_clock_converter,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"axi_clock_converter_0,axi_clock_converter_v2_1_21_axi_clock_converter,{}\" *)\n(* CORE_GENERATION_INFO = \"axi_clock_converter_0,axi_clock_converter_v2_1_21_axi_clock_converter,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_clock_converter,x_ipVersion=2.1,x_ipCoreRevision=21,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_ID_WIDTH=16,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=1,C_AXI_PROTOCOL=0,C_AXI_SUPPORTS_USER_SIGNALS=1,C_AXI_AWUSER_WIDTH=19,C_AXI_ARUSER_WIDTH=19,C_AXI_WUSER_WIDTH=1,C_A\\\nXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_SYNCHRONIZER_STAGE=2}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_clock_converter_0 (\n  s_axi_aclk,\n  s_axi_aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awuser,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_aruser,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_aclk,\n  m_axi_aresetn,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awuser,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_aruser,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_CLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 SI_CLK CLK\" *)\ninput wire s_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 SI_RST RST\" *)\ninput wire s_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWUSER\" *)\ninput wire [18 : 0] s_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARUSER\" *)\ninput wire [18 : 0] s_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 19, ARUSER_WIDTH 19, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUS\\\nER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_CLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 MI_CLK CLK\" *)\ninput wire m_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 MI_RST RST\" *)\ninput wire m_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWUSER\" *)\noutput wire [18 : 0] m_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARUSER\" *)\noutput wire [18 : 0] m_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 19, ARUSER_WIDTH 19, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUS\\\nER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_clock_converter_v2_1_21_axi_clock_converter #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_S_AXI_ACLK_RATIO(1),\n    .C_M_AXI_ACLK_RATIO(2),\n    .C_AXI_IS_ACLK_ASYNC(1),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_SUPPORTS_USER_SIGNALS(1),\n    .C_AXI_AWUSER_WIDTH(19),\n    .C_AXI_ARUSER_WIDTH(19),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_AXI_SUPPORTS_WRITE(1),\n    .C_AXI_SUPPORTS_READ(1),\n    .C_SYNCHRONIZER_STAGE(2)\n  ) inst (\n    .s_axi_aclk(s_axi_aclk),\n    .s_axi_aresetn(s_axi_aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(s_axi_awuser),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(s_axi_aruser),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_aclk(m_axi_aclk),\n    .m_axi_aresetn(m_axi_aresetn),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(m_axi_awuser),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(m_axi_aruser),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 443}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sync_clock_converter\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axic_sync_clock_converter # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_FAMILY     = \"virtex6\",\n  parameter integer C_PAYLOAD_WIDTH = 32,\n  parameter integer C_S_ACLK_RATIO = 1,\n  parameter integer C_M_ACLK_RATIO = 1 ,\n  parameter integer C_MODE = 0  // 0 = light-weight (1-deep); 1 = fully-pipelined (2-deep)\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input wire                    SAMPLE_CYCLE_EARLY,\n  input wire                    SAMPLE_CYCLE,\n  // Slave side\n  input  wire                        S_ACLK,\n  input  wire                        S_ARESETN,\n  input  wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD,\n  input  wire                        S_VALID,\n  output wire                        S_READY,\n\n  // Master side\n  input  wire                        M_ACLK,\n  input  wire                        M_ARESETN,\n  output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD,\n  output wire                        M_VALID,\n  input  wire                        M_READY\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam [1:0] ZERO = 2'b10;\nlocalparam [1:0] ONE  = 2'b11;\nlocalparam [1:0] TWO  = 2'b01;\nlocalparam [1:0] INIT = 2'b00;\nlocalparam integer P_LIGHT_WT = 0;\nlocalparam integer P_FULLY_REG = 1;\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\ngenerate\n  if (C_S_ACLK_RATIO == C_M_ACLK_RATIO) begin : gen_passthru\n    assign M_PAYLOAD = S_PAYLOAD;\n    assign M_VALID   = S_VALID;\n    assign S_READY   = M_READY;      \n  end else begin : gen_sync_clock_converter\n    wire s_sample_cycle;\n    wire s_sample_cycle_early;\n    wire m_sample_cycle;\n    wire m_sample_cycle_early;\n\n    wire slow_aclk;\n    wire slow_areset;\n    wire s_areset_r;\n    wire m_areset_r;\n   \n    reg  s_tready_r = 1'b0; \n    wire s_tready_ns; \n    reg  m_tvalid_r = 1'b0; \n    wire m_tvalid_ns; \n    reg  [C_PAYLOAD_WIDTH-1:0] m_tpayload_r;\n    reg  [C_PAYLOAD_WIDTH-1:0] m_tstorage_r;\n    wire [C_PAYLOAD_WIDTH-1:0] m_tpayload_ns; \n    wire [C_PAYLOAD_WIDTH-1:0] m_tstorage_ns; \n    reg  m_tready_hold = 1'b0;\n    wire m_tready_sample;\n    wire load_tpayload;\n    wire load_tstorage;\n    wire load_tpayload_from_tstorage;\n    reg [1:0] state = INIT;\n    reg [1:0] next_state;\n    \n    reg s_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge S_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        s_aresetn_r <= 1'b0;\n      end else begin\n        s_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign s_areset_r = ~s_aresetn_r;\n\n    reg m_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge M_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        m_aresetn_r <= 1'b0;\n      end else begin\n        m_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign m_areset_r = ~m_aresetn_r;\n\n    if (C_S_ACLK_RATIO > C_M_ACLK_RATIO) begin : gen_slowclk_mi\n      assign slow_aclk = M_ACLK;\n    end else begin : gen_slowclk_si\n      assign slow_aclk = S_ACLK;\n    end\n  \n    assign slow_areset = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? m_areset_r : s_areset_r;\n    assign s_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE_EARLY : 1'b1;\n    assign s_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE : 1'b1;\n    assign m_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE_EARLY;\n    assign m_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE;\n\n    // Output flop for S_READY, value is encoded into state machine.\n    assign s_tready_ns = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? state[1] & (state != INIT) : next_state[1];\n\n    always @(posedge S_ACLK) begin \n      if (s_areset_r) begin\n        s_tready_r <= 1'b0;\n      end\n      else begin\n        s_tready_r <= s_sample_cycle_early ? s_tready_ns : 1'b0;\n      end\n    end\n\n    assign S_READY = s_tready_r;\n\n    // Output flop for M_VALID\n    assign m_tvalid_ns = next_state[0];\n\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tvalid_r <= 1'b0;\n      end\n      else begin\n        m_tvalid_r <= m_sample_cycle ? m_tvalid_ns : m_tvalid_r & ~M_READY;\n      end\n    end\n\n    assign M_VALID = m_tvalid_r;\n\n    // Hold register for M_READY when M_ACLK is fast.\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tready_hold <= 1'b0;\n      end\n      else begin\n        m_tready_hold <= m_sample_cycle ? 1'b0 : m_tready_sample;\n      end\n    end\n\n    assign m_tready_sample = (M_READY ) | m_tready_hold;\n    // Output/storage flops for PAYLOAD\n    assign m_tpayload_ns = ~load_tpayload ? m_tpayload_r :\n                           load_tpayload_from_tstorage ? m_tstorage_r : \n                           S_PAYLOAD;\n\n    assign m_tstorage_ns = C_MODE ? (load_tstorage ? S_PAYLOAD : m_tstorage_r) : 0;\n\n    always @(posedge slow_aclk) begin \n      m_tpayload_r <= m_tpayload_ns;\n      m_tstorage_r <= C_MODE ? m_tstorage_ns : 0;\n    end\n\n    assign M_PAYLOAD = m_tpayload_r;\n\n    // load logic\n    assign load_tstorage = C_MODE && (state != TWO);\n    assign load_tpayload = m_tready_sample || (state == ZERO);\n    assign load_tpayload_from_tstorage = C_MODE && (state == TWO) && m_tready_sample;\n    \n    // State machine\n    always @(posedge slow_aclk) begin \n      state <= next_state;\n    end\n\n    always @* begin \n      if (slow_areset) begin \n        next_state = INIT;\n      end else begin\n        case (state)\n          INIT: begin\n            next_state = ZERO;\n          end\n          // No transaction stored locally\n          ZERO: begin\n            if (S_VALID) begin\n              next_state = C_MODE ? ONE : TWO; // Push from empty\n            end\n            else begin\n              next_state = ZERO;\n            end\n          end\n\n          // One transaction stored locally\n          ONE: begin\n            if (C_MODE == 0) begin\n              next_state = TWO;  // State ONE is inaccessible when C_MODE=0\n            end \n            else if (m_tready_sample & ~S_VALID) begin \n              next_state = ZERO; // Read out one so move to ZERO\n            end\n            else if (~m_tready_sample & S_VALID) begin\n              next_state = TWO;  // Got another one so move to TWO\n            end\n            else begin\n              next_state = ONE;\n            end\n          end\n\n          // Storage registers full\n          TWO: begin \n            if (m_tready_sample) begin\n              next_state = C_MODE ? ONE : ZERO; // Pop from full\n            end\n            else begin\n              next_state = TWO;\n            end\n          end\n        endcase // case (state)\n      end\n    end\n  end // gen_sync_clock_converter\n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sample_cycle_ratio\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axic_sample_cycle_ratio # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_RATIO = 2 // Must be > 0\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    SLOW_ACLK,\n  input  wire                    FAST_ACLK,\n\n  output wire                    SAMPLE_CYCLE_EARLY,\n  output wire                    SAMPLE_CYCLE\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam P_DELAY = C_RATIO > 2 ? C_RATIO-1 : C_RATIO-1; \n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_aclk_div2 = 1'b0;\nreg                posedge_finder_first = 1'b0;\nreg                posedge_finder_second = 1'b0;\nwire               first_edge;\nwire               second_edge;\nwire               any_edge;\nreg  [P_DELAY-1:0] sample_cycle_d = {P_DELAY{1'b0}};\n(* shreg_extract = \"no\" *) reg                sample_cycle_r = 1'b0;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\ngenerate\n  if (C_RATIO == 1) begin : gen_always_sample\n    assign SAMPLE_CYCLE_EARLY = 1'b1;\n    assign SAMPLE_CYCLE = 1'b1;\n  end\n  else begin : gen_sample_cycle\n    genvar i;\n    always @(posedge SLOW_ACLK) begin \n      slow_aclk_div2 <= ~slow_aclk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_aclk_div2 onto faster clock\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_first <= slow_aclk_div2;\n    end\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_second <= ~slow_aclk_div2;\n    end\n\n    assign first_edge = slow_aclk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;\n    assign any_edge = first_edge | second_edge;\n   \n    // delay the posedge alignment by C_RATIO - 1 to set the sample cycle as\n    // the clock one cycle before the posedge.\n    for (i = P_DELAY-1; i > 0; i = i - 1) begin : gen_delay\n      always @(posedge FAST_ACLK) begin\n        if (i == P_DELAY-1) begin\n          sample_cycle_d[i-1] <= any_edge;\n        end else begin\n          sample_cycle_d[i-1] <= sample_cycle_d[i];\n        end\n      end\n    end\n\n    always @(posedge FAST_ACLK) begin \n      sample_cycle_r <= (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    end\n    assign SAMPLE_CYCLE_EARLY = (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    assign SAMPLE_CYCLE = sample_cycle_r;\n  end\nendgenerate\n\nendmodule // axisc_sample_cycle_ratio\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2010 - 2016 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and\n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Clock converter module\n//   Asynchronous clock converter when asynchronous M:N conversion\n//   Bypass when synchronous and ratio between S and M clock is 1:1\n//   Synchronous clock converter (S:M or M:S must be integer ratio)\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_clock_conv\n//     fifo_generator\n//     axic_sync_clock_converter\n//       axic_sample_cycle_ratio\n//\n// PROTECTED NAMES:\n//   Instance names \"asyncfifo_*\" are pattern-matched in core-level UCF.\n//   Signal names \"*_resync\" are pattern-matched in core-level UCF.\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_lite_async #(\n  parameter integer C_DEST_SYNC_FF = 3,\n  parameter integer C_SRC_SYNC_FF  = 3,\n  parameter integer C_WIDTH        = 1\n) (\n  input wire                s_aclk,\n  input wire                m_aclk,\n  input wire                s_aresetn,\n  input wire                m_aresetn,\n  input wire                s_valid,\n  output wire                s_ready,\n  input wire [C_WIDTH-1:0]  s_payld,\n  output wire                m_valid,\n  input wire                m_ready,\n  output wire [C_WIDTH-1:0] m_payld\n);\n\nreg [C_SRC_SYNC_FF:0] s_areset_dly = {C_SRC_SYNC_FF+1{1'b0}};\nreg [C_DEST_SYNC_FF:0] m_areset_dly = {C_DEST_SYNC_FF+1{1'b0}};\nreg                s_ready_i = 1'b0;\nreg                m_valid_i = 1'b0;\nreg   src_send = 1'b0;\nreg   dest_ack = 1'b0;\nwire  src_rcv;\nwire  dest_req;\n\nassign s_ready = s_ready_i;\nassign m_valid = m_valid_i;\n\nlocalparam SRC_IDLE           = 2'b00;\nlocalparam SRC_DRV_SEND       = 2'b01;\nlocalparam SRC_WAIT_RCV_DONE  = 2'b10;\nreg [1:0] src_state = SRC_IDLE;\n\nalways @(posedge s_aclk) begin\n  s_areset_dly <= {C_SRC_SYNC_FF+1{~s_aresetn}} | (s_areset_dly<<1);\n  if (s_areset_dly[C_SRC_SYNC_FF]) begin\n    s_ready_i <= 1'b0;\n    src_send <= 1'b0;\n    src_state <= SRC_IDLE;\n  end else begin\n    case (src_state)\n      SRC_IDLE: begin\n        if (s_valid) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end\n      end\n      SRC_DRV_SEND: begin\n        if (src_rcv) begin\n          s_ready_i <= 1'b1;\n          src_send <= 1'b0;\n          src_state <= SRC_WAIT_RCV_DONE;\n        end\n      end\n      SRC_WAIT_RCV_DONE: begin\n        s_ready_i <= 1'b0;\n        if (s_valid & !src_rcv) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end else if (!src_rcv) begin\n          src_state <= SRC_IDLE;\n        end\n      end\n      default: begin\n        s_ready_i <= 1'b0;\n        src_send <= 1'b0;\n        src_state <= SRC_IDLE;\n      end\n    endcase\n  end\nend\n\nlocalparam DEST_IDLE           = 2'b00;\nlocalparam DEST_DRV_VALID      = 2'b01;\nlocalparam DEST_DRV_ACK        = 2'b10;\nreg [1:0] dest_state = DEST_IDLE;\n\nalways @(posedge m_aclk) begin\n  m_areset_dly <= {C_DEST_SYNC_FF+1{~m_aresetn}} | (m_areset_dly<<1);\n  if (m_areset_dly[C_DEST_SYNC_FF]) begin\n    m_valid_i <= 1'b0;\n    dest_ack <= 1'b0;\n    dest_state <= DEST_IDLE;\n  end else begin\n    case (dest_state)\n      DEST_IDLE: begin\n        if (dest_req) begin\n          dest_state <= DEST_DRV_VALID;\n          m_valid_i <= 1'b1;\n        end else begin\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b0;\n        end\n      end\n      DEST_DRV_VALID: begin\n        if (m_ready & m_valid_i) begin\n          dest_state <= DEST_DRV_ACK;\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b1;\n        end\n      end\n      DEST_DRV_ACK: begin\n        if (!dest_req) begin\n          dest_state <= DEST_IDLE;\n          dest_ack <= 1'b0;\n        end\n      end\n      default: begin\n        m_valid_i <= 1'b0;\n        dest_ack <= 1'b0;\n        dest_state <= DEST_IDLE;\n      end\n    endcase\n  end\nend\n\nxpm_cdc_handshake #(\n  .DEST_SYNC_FF   (C_DEST_SYNC_FF),\n  .SRC_SYNC_FF    (C_SRC_SYNC_FF),\n  .WIDTH          (C_WIDTH)\n) handshake (\n  .src_clk  (s_aclk),\n  .src_in   (s_payld),\n  .src_send (src_send),\n  .src_rcv  (src_rcv),\n  .dest_clk (m_aclk),\n  .dest_out (m_payld),\n  .dest_req (dest_req),\n  .dest_ack (dest_ack)\n);\n\nendmodule\n\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axi_clock_converter #\n  (parameter         C_FAMILY = \"virtex7\",\n   parameter integer C_AXI_ID_WIDTH = 5,                    // Width of all ID signals on SI and MI side.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ADDR_WIDTH = 32,                 // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and\n                                                            // m_axi_araddr.\n                                                            // Range: 32.\n   parameter integer C_AXI_DATA_WIDTH = 32,       // Width of WDATA and RDATA (either side).\n                                                            // Format: Bit32;\n                                                            // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.\n   parameter integer C_S_AXI_ACLK_RATIO = 1,     // Clock frequency ratio of SI w.r.t. MI.\n   parameter integer C_M_AXI_ACLK_RATIO = 1,     // (Slowest of all clock inputs should have ratio=1.)\n                                                            // S:M or M:S must be integer ratio.\n                                                            // Format: Bit32; Range: >='h00000001.\n   parameter integer C_AXI_IS_ACLK_ASYNC = 1,            // Indicates whether S and M clocks are asynchronous.\n                                                            // FUTURE FEATURE\n                                                            // Format: Bit1. Range = 1'b0.\n   parameter integer C_AXI_PROTOCOL = 0,         // Protocol of this SI/MI slot.\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS  = 1,      // 1 = Propagate all USER signals, 0 = Do not propagate.\n   parameter integer C_AXI_AWUSER_WIDTH = 1,                // Width of AWUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ARUSER_WIDTH = 1,                // Width of ARUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_WUSER_WIDTH = 1,                 // Width of WUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_RUSER_WIDTH = 1,                 // Width of RUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_BUSER_WIDTH = 1,                 // Width of BUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,              // Implement AXI write channels\n   parameter integer C_AXI_SUPPORTS_READ = 1,               // Implement AXI read channels\n   parameter integer C_SYNCHRONIZER_STAGE = 3\n  )\n\n  (\n   // Slave Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n   input  wire [4-1:0]                    s_axi_awcache,\n   input  wire [3-1:0]                    s_axi_awprot,\n   input  wire [4-1:0]                    s_axi_awregion,\n   input  wire [4-1:0]                    s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0]   s_axi_awuser,\n   input  wire                            s_axi_awvalid,\n   output wire                            s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n   input  wire                            s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]    s_axi_wuser,\n   input  wire                            s_axi_wvalid,\n   output wire                            s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_bid,\n   output wire [2-1:0]                    s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0]    s_axi_buser,\n   output wire                            s_axi_bvalid,\n   input  wire                            s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n   input  wire [3-1:0]                    s_axi_arsize,\n   input  wire [2-1:0]                    s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n   input  wire [4-1:0]                    s_axi_arcache,\n   input  wire [3-1:0]                    s_axi_arprot,\n   input  wire [4-1:0]                    s_axi_arregion,\n   input  wire [4-1:0]                    s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0]   s_axi_aruser,\n   input  wire                            s_axi_arvalid,\n   output wire                            s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n   output wire [2-1:0]                    s_axi_rresp,\n   output wire                            s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0]    s_axi_ruser,\n   output wire                            s_axi_rvalid,\n   input  wire                            s_axi_rready,\n\n   // Master Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aresetn,\n\n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n   output wire [3-1:0]                    m_axi_awsize,\n   output wire [2-1:0]                    m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n   output wire [4-1:0]                    m_axi_awcache,\n   output wire [3-1:0]                    m_axi_awprot,\n   output wire [4-1:0]                    m_axi_awregion,\n   output wire [4-1:0]                    m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0]   m_axi_awuser,\n   output wire                            m_axi_awvalid,\n   input  wire                            m_axi_awready,\n\n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0]   m_axi_wstrb,\n   output wire                            m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]    m_axi_wuser,\n   output wire                            m_axi_wvalid,\n   input  wire                            m_axi_wready,\n\n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_bid,\n   input  wire [2-1:0]                    m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0]    m_axi_buser,\n   input  wire                            m_axi_bvalid,\n   output wire                            m_axi_bready,\n\n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n   output wire [3-1:0]                    m_axi_arsize,\n   output wire [2-1:0]                    m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n   output wire [4-1:0]                    m_axi_arcache,\n   output wire [3-1:0]                    m_axi_arprot,\n   output wire [4-1:0]                    m_axi_arregion,\n   output wire [4-1:0]                    m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0]   m_axi_aruser,\n   output wire                            m_axi_arvalid,\n   input  wire                            m_axi_arready,\n\n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     m_axi_rdata,\n   input  wire [2-1:0]                    m_axi_rresp,\n   input  wire                            m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0]    m_axi_ruser,\n   input  wire                            m_axi_rvalid,\n   output wire                            m_axi_rready);\n\n  localparam integer P_AXI4 = 0;\n  localparam integer P_AXI3 = 1;\n  localparam integer P_AXILITE = 2;\n  localparam integer P_LIGHT_WT = 0;\n  localparam integer P_FULLY_REG = 1;\n  localparam integer P_LUTRAM_ASYNC = 12;\n\n  // Sample cycle ratio\n  localparam  P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);\n  localparam integer P_ROUNDING_OFFSET = P_SI_LT_MI ? (C_S_AXI_ACLK_RATIO/2) : (C_M_AXI_ACLK_RATIO/2);\n  localparam integer P_ACLK_RATIO = P_SI_LT_MI ?\n    ((C_M_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_S_AXI_ACLK_RATIO) :\n    ((C_S_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_M_AXI_ACLK_RATIO);\n\n  // Write Address Port bit positions\n  localparam integer C_AWUSER_RIGHT   = 0;\n  localparam integer C_AWUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_AWUSER_WIDTH : 0;\n  localparam integer C_AWQOS_RIGHT    = C_AWUSER_RIGHT + C_AWUSER_WIDTH;\n  localparam integer C_AWQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWREGION_RIGHT = C_AWQOS_RIGHT + C_AWQOS_WIDTH;\n  localparam integer C_AWREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_AWPROT_RIGHT   = C_AWREGION_RIGHT + C_AWREGION_WIDTH;\n  localparam integer C_AWPROT_WIDTH     = 3;\n  localparam integer C_AWCACHE_RIGHT  = C_AWPROT_RIGHT + C_AWPROT_WIDTH;\n  localparam integer C_AWCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWLOCK_RIGHT   = C_AWCACHE_RIGHT + C_AWCACHE_WIDTH;\n  localparam integer C_AWLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_AWBURST_RIGHT  = C_AWLOCK_RIGHT + C_AWLOCK_WIDTH;\n  localparam integer C_AWBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_AWSIZE_RIGHT   = C_AWBURST_RIGHT + C_AWBURST_WIDTH;\n  localparam integer C_AWSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_AWLEN_RIGHT    = C_AWSIZE_RIGHT + C_AWSIZE_WIDTH;\n  localparam integer C_AWLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_AWADDR_RIGHT   = C_AWLEN_RIGHT + C_AWLEN_WIDTH;\n  localparam integer C_AWADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_AWID_RIGHT     = C_AWADDR_RIGHT + C_AWADDR_WIDTH;\n  localparam integer C_AWID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AW_WIDTH        = C_AWID_RIGHT + C_AWID_WIDTH;\n  localparam integer C_FIFO_AW_WIDTH   = C_AWUSER_WIDTH+C_AWQOS_WIDTH+C_AWQOS_WIDTH+3+C_AWCACHE_WIDTH+C_AWLOCK_WIDTH+C_AWBURST_WIDTH+C_AWSIZE_WIDTH+C_AWLEN_WIDTH+C_AXI_ADDR_WIDTH+C_AWID_WIDTH;\n\n  // Write Data Port bit positions\n  localparam integer C_WUSER_RIGHT   = 0;\n  localparam integer C_WUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_WUSER_WIDTH : 0;\n  localparam integer C_WLAST_RIGHT   = C_WUSER_RIGHT + C_WUSER_WIDTH;\n  localparam integer C_WLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_WSTRB_RIGHT   = C_WLAST_RIGHT + C_WLAST_WIDTH;\n  localparam integer C_WSTRB_WIDTH     = C_AXI_DATA_WIDTH/8;\n  localparam integer C_WDATA_RIGHT   = C_WSTRB_RIGHT + C_WSTRB_WIDTH;\n  localparam integer C_WDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_WID_RIGHT     = C_WDATA_RIGHT + C_WDATA_WIDTH;\n  localparam integer C_WID_WIDTH       = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_W_WIDTH        = C_WID_RIGHT + C_WID_WIDTH;\n  localparam integer C_FIFO_W_WIDTH   = C_WUSER_WIDTH + C_WLAST_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_DATA_WIDTH + C_WID_WIDTH;\n\n  // Write Response Port bit positions\n  localparam integer C_BUSER_RIGHT   = 0;\n  localparam integer C_BUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_BUSER_WIDTH : 0;\n  localparam integer C_BRESP_RIGHT   = C_BUSER_RIGHT + C_BUSER_WIDTH;\n  localparam integer C_BRESP_WIDTH     = 2;\n  localparam integer C_BID_RIGHT     = C_BRESP_RIGHT + C_BRESP_WIDTH;\n  localparam integer C_BID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_B_WIDTH        = C_BID_RIGHT + C_BID_WIDTH;\n  localparam integer C_FIFO_B_WIDTH    = C_BUSER_WIDTH + 2 + C_BID_WIDTH;\n\n  // Read Address Port bit positions\n  localparam integer C_ARUSER_RIGHT   = 0;\n  localparam integer C_ARUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_ARUSER_WIDTH : 0;\n  localparam integer C_ARQOS_RIGHT    = C_ARUSER_RIGHT + C_ARUSER_WIDTH;\n  localparam integer C_ARQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARREGION_RIGHT = C_ARQOS_RIGHT + C_ARQOS_WIDTH;\n  localparam integer C_ARREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_ARPROT_RIGHT   = C_ARREGION_RIGHT + C_ARREGION_WIDTH;\n  localparam integer C_ARPROT_WIDTH     = 3;\n  localparam integer C_ARCACHE_RIGHT  = C_ARPROT_RIGHT + C_ARPROT_WIDTH;\n  localparam integer C_ARCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARLOCK_RIGHT   = C_ARCACHE_RIGHT + C_ARCACHE_WIDTH;\n  localparam integer C_ARLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_ARBURST_RIGHT  = C_ARLOCK_RIGHT + C_ARLOCK_WIDTH;\n  localparam integer C_ARBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_ARSIZE_RIGHT   = C_ARBURST_RIGHT + C_ARBURST_WIDTH;\n  localparam integer C_ARSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_ARLEN_RIGHT    = C_ARSIZE_RIGHT + C_ARSIZE_WIDTH;\n  localparam integer C_ARLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_ARADDR_RIGHT   = C_ARLEN_RIGHT + C_ARLEN_WIDTH;\n  localparam integer C_ARADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_ARID_RIGHT     = C_ARADDR_RIGHT + C_ARADDR_WIDTH;\n  localparam integer C_ARID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AR_WIDTH        = C_ARID_RIGHT + C_ARID_WIDTH;\n  localparam integer C_FIFO_AR_WIDTH   = C_ARUSER_WIDTH+C_ARQOS_WIDTH+C_ARQOS_WIDTH+3+C_ARCACHE_WIDTH+C_ARLOCK_WIDTH+C_ARBURST_WIDTH+C_ARSIZE_WIDTH+C_ARLEN_WIDTH+C_AXI_ADDR_WIDTH+C_ARID_WIDTH;\n\n  // Read Data Ports bit positions\n  localparam integer C_RUSER_RIGHT   = 0;\n  localparam integer C_RUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_RUSER_WIDTH : 0;\n  localparam integer C_RLAST_RIGHT   = C_RUSER_RIGHT + C_RUSER_WIDTH;\n  localparam integer C_RLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_RRESP_RIGHT   = C_RLAST_RIGHT + C_RLAST_WIDTH;\n  localparam integer C_RRESP_WIDTH     = 2;\n  localparam integer C_RDATA_RIGHT   = C_RRESP_RIGHT + C_RRESP_WIDTH;\n  localparam integer C_RDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_RID_RIGHT     = C_RDATA_RIGHT + C_RDATA_WIDTH;\n  localparam integer C_RID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_R_WIDTH        = C_RID_RIGHT + C_RID_WIDTH;\n  localparam integer C_FIFO_R_WIDTH   = C_RUSER_WIDTH + C_RLAST_WIDTH + 2 + C_AXI_DATA_WIDTH + C_RID_WIDTH;\n\n  generate\n    if ((C_AXI_IS_ACLK_ASYNC == 0) && (P_ACLK_RATIO == 1)) begin : gen_bypass\n      \n      // Write address port\n      assign m_axi_awid     = s_axi_awid;\n      assign m_axi_awaddr   = s_axi_awaddr;\n      assign m_axi_awlen    = s_axi_awlen;\n      assign m_axi_awsize   = s_axi_awsize;\n      assign m_axi_awburst  = s_axi_awburst;\n      assign m_axi_awlock   = s_axi_awlock;\n      assign m_axi_awcache  = s_axi_awcache;\n      assign m_axi_awprot   = s_axi_awprot;\n      assign m_axi_awregion = s_axi_awregion;\n      assign m_axi_awqos    = s_axi_awqos;\n      assign m_axi_awuser   = s_axi_awuser;\n      assign m_axi_awvalid  = s_axi_awvalid;\n      assign s_axi_awready  = m_axi_awready;\n\n      // Write Data Port\n      assign m_axi_wid      = s_axi_wid;\n      assign m_axi_wdata    = s_axi_wdata;\n      assign m_axi_wstrb    = s_axi_wstrb;\n      assign m_axi_wlast    = s_axi_wlast;\n      assign m_axi_wuser    = s_axi_wuser;\n      assign m_axi_wvalid   = s_axi_wvalid;\n      assign s_axi_wready   = m_axi_wready;\n\n      // Write Response Port\n      assign s_axi_bid      = m_axi_bid;\n      assign s_axi_bresp    = m_axi_bresp;\n      assign s_axi_buser    = m_axi_buser;\n      assign s_axi_bvalid   = m_axi_bvalid;\n      assign m_axi_bready   = s_axi_bready;\n\n      // Read Address Port\n      assign m_axi_arid     = s_axi_arid;\n      assign m_axi_araddr   = s_axi_araddr;\n      assign m_axi_arlen    = s_axi_arlen;\n      assign m_axi_arsize   = s_axi_arsize;\n      assign m_axi_arburst  = s_axi_arburst;\n      assign m_axi_arlock   = s_axi_arlock;\n      assign m_axi_arcache  = s_axi_arcache;\n      assign m_axi_arprot   = s_axi_arprot;\n      assign m_axi_arregion = s_axi_arregion;\n      assign m_axi_arqos    = s_axi_arqos;\n      assign m_axi_aruser   = s_axi_aruser;\n      assign m_axi_arvalid  = s_axi_arvalid;\n      assign s_axi_arready  = m_axi_arready;\n\n      // Read Data Port\n      assign s_axi_rid      = m_axi_rid;\n      assign s_axi_rdata    = m_axi_rdata;\n      assign s_axi_rresp    = m_axi_rresp;\n      assign s_axi_rlast    = m_axi_rlast;\n      assign s_axi_ruser    = m_axi_ruser;\n      assign s_axi_rvalid   = m_axi_rvalid;\n      assign m_axi_rready   = s_axi_rready;\n      \n    end else begin : gen_clock_conv\n      \n      wire fast_aclk;\n      wire slow_aclk;\n      wire sample_cycle;\n      wire sample_cycle_early;\n    \n      // Write Address Port FIFO data read and write\n      wire [C_AW_WIDTH-1:0] s_aw_mesg ;\n      wire [C_AW_WIDTH-1:0] m_aw_mesg ;\n    \n      // Write Data Port FIFO data read and write\n      wire [C_W_WIDTH-1:0] s_w_mesg;\n      wire [C_W_WIDTH-1:0] m_w_mesg;\n    \n      // Write Response Port FIFO data read and write\n      wire [C_B_WIDTH-1:0] s_b_mesg;\n      wire [C_B_WIDTH-1:0] m_b_mesg;\n    \n      // Read Address Port FIFO data read and write\n      wire [C_AR_WIDTH-1:0] s_ar_mesg;\n      wire [C_AR_WIDTH-1:0] m_ar_mesg;\n    \n      // Read Data Ports FIFO data read and write\n      wire [C_R_WIDTH-1:0] s_r_mesg;\n      wire [C_R_WIDTH-1:0] m_r_mesg;\n    \n      wire async_conv_reset_n;\n      assign async_conv_reset_n = ~(~s_axi_aresetn | ~m_axi_aresetn);\n      \n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_awlen           ;\n      wire [3-1:0]                       si_cc_awsize          ;\n      wire [2-1:0]                       si_cc_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_awlock          ;\n      wire [4-1:0]                       si_cc_awcache         ;\n      wire [3-1:0]                       si_cc_awprot          ;\n      wire [4-1:0]                       si_cc_awregion        ;\n      wire [4-1:0]                       si_cc_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]      si_cc_awuser          ;\n      wire                               si_cc_awvalid         ;\n      wire                               si_cc_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_wid            ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]      si_cc_wstrb           ;\n      wire                               si_cc_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]       si_cc_wuser           ;\n      wire                               si_cc_wvalid          ;\n      wire                               si_cc_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_bid             ;\n      wire [2-1:0]                       si_cc_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]       si_cc_buser           ;\n      wire                               si_cc_bvalid          ;\n      wire                               si_cc_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_arlen           ;\n      wire [3-1:0]                       si_cc_arsize          ;\n      wire [2-1:0]                       si_cc_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_arlock          ;\n      wire [4-1:0]                       si_cc_arcache         ;\n      wire [3-1:0]                       si_cc_arprot          ;\n      wire [4-1:0]                       si_cc_arregion        ;\n      wire [4-1:0]                       si_cc_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]      si_cc_aruser          ;\n      wire                               si_cc_arvalid         ;\n      wire                               si_cc_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_rdata           ;\n      wire [2-1:0]                       si_cc_rresp           ;\n      wire                               si_cc_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]       si_cc_ruser           ;\n      wire                               si_cc_rvalid          ;\n      wire                               si_cc_rready          ;\n      \n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_awlen           ;\n      wire [3-1:0]                      cc_mi_awsize          ;\n      wire [2-1:0]                      cc_mi_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_awlock          ;\n      wire [4-1:0]                      cc_mi_awcache         ;\n      wire [3-1:0]                      cc_mi_awprot          ;\n      wire [4-1:0]                      cc_mi_awregion        ;\n      wire [4-1:0]                      cc_mi_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]     cc_mi_awuser          ;\n      wire                              cc_mi_awvalid         ;\n      wire                              cc_mi_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_wid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]     cc_mi_wstrb           ;\n      wire                              cc_mi_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]      cc_mi_wuser           ;\n      wire                              cc_mi_wvalid          ;\n      wire                              cc_mi_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_bid             ;\n      wire [2-1:0]                      cc_mi_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]      cc_mi_buser           ;\n      wire                              cc_mi_bvalid          ;\n      wire                              cc_mi_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_arlen           ;\n      wire [3-1:0]                      cc_mi_arsize          ;\n      wire [2-1:0]                      cc_mi_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_arlock          ;\n      wire [4-1:0]                      cc_mi_arcache         ;\n      wire [3-1:0]                      cc_mi_arprot          ;\n      wire [4-1:0]                      cc_mi_arregion        ;\n      wire [4-1:0]                      cc_mi_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]     cc_mi_aruser          ;\n      wire                              cc_mi_arvalid         ;\n      wire                              cc_mi_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_rdata           ;\n      wire [2-1:0]                      cc_mi_rresp           ;\n      wire                              cc_mi_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]      cc_mi_ruser           ;\n      wire                              cc_mi_rvalid          ;\n      wire                              cc_mi_rready          ;\n      \n    // Tie-offs\n      assign si_cc_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awid : 0 ;\n      assign si_cc_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awaddr : 0 ;\n      assign si_cc_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_awlen : {4'b0000, s_axi_awlen[3:0]}) : 0 ;\n      assign si_cc_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize : 0 ;\n      assign si_cc_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst : 0 ;\n      assign si_cc_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_awlock : {1'b0, s_axi_awlock[0]}) : 0 ;\n      assign si_cc_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache : 0 ;\n      assign si_cc_awprot    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awprot : 0 ;\n      assign si_cc_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos : 0 ;\n      assign si_cc_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion : 0 ;\n      assign si_cc_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser : 0 ;\n      assign si_cc_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awvalid : 0 ;\n      assign si_cc_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? s_axi_wid : 0 ;\n      assign si_cc_wdata     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wdata : 0 ;\n      assign si_cc_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wstrb : 0 ;\n      assign si_cc_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast : 1'b0 ;\n      assign si_cc_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser : 0 ;\n      assign si_cc_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wvalid : 0 ;\n      assign si_cc_bready    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_bready : 0 ;\n      assign si_cc_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arid : 0 ;\n      assign si_cc_araddr    = (C_AXI_SUPPORTS_READ ) ? s_axi_araddr : 0 ;\n      assign si_cc_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_arlen : {4'b0000, s_axi_arlen[3:0]}) : 0 ;\n      assign si_cc_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize : 0 ;\n      assign si_cc_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst : 0 ;\n      assign si_cc_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_arlock : {1'b0, s_axi_arlock[0]}) : 0 ;\n      assign si_cc_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache : 0 ;\n      assign si_cc_arprot    = (C_AXI_SUPPORTS_READ ) ? s_axi_arprot : 0 ;\n      assign si_cc_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos : 0 ;\n      assign si_cc_arregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion : 0 ;\n      assign si_cc_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser : 0 ;\n      assign si_cc_arvalid   = (C_AXI_SUPPORTS_READ ) ? s_axi_arvalid : 0 ;\n      assign si_cc_rready    = (C_AXI_SUPPORTS_READ ) ? s_axi_rready : 0 ;                                       \n                                                                                               \n      assign s_axi_awready   = (C_AXI_SUPPORTS_WRITE ) ? si_cc_awready : 0 ;\n      assign s_axi_wready    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_wready : 0 ;\n      assign s_axi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_bid : 0 ;\n      assign s_axi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bresp : 0 ;\n      assign s_axi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_buser : 0 ;\n      assign s_axi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bvalid : 0 ;\n      assign s_axi_arready   = (C_AXI_SUPPORTS_READ ) ? si_cc_arready : 0 ;\n      assign s_axi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rid : 0 ;\n      assign s_axi_rdata     = (C_AXI_SUPPORTS_READ ) ? si_cc_rdata : 0 ;\n      assign s_axi_rresp     = (C_AXI_SUPPORTS_READ ) ? si_cc_rresp : 0 ;\n      assign s_axi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rlast : 0 ;\n      assign s_axi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_ruser : 0 ;\n      assign s_axi_rvalid    = (C_AXI_SUPPORTS_READ ) ? si_cc_rvalid : 0 ;\n\n      assign m_axi_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awid : 0 ;\n      assign m_axi_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awaddr : 0 ;\n      assign m_axi_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_awlen : cc_mi_awlen[3:0]) : 0 ;\n      assign m_axi_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awsize : 0 ;\n      assign m_axi_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awburst : 0 ;\n      assign m_axi_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_awlock : cc_mi_awlock[0]) : 0 ;\n      assign m_axi_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awcache : 0 ;\n      assign m_axi_awprot    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awprot : 0 ;\n      assign m_axi_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_awregion : 0 ;\n      assign m_axi_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awqos : 0 ;\n      assign m_axi_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_awuser : 0 ;\n      assign m_axi_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awvalid : 0 ;\n      assign m_axi_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? cc_mi_wid : 0 ;\n      assign m_axi_wdata     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wdata : 0 ;\n      assign m_axi_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wstrb : 0 ;\n      assign m_axi_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_wlast : 0 ;\n      assign m_axi_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_wuser : 0 ;\n      assign m_axi_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wvalid : 0 ;\n      assign m_axi_bready    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_bready : 0 ;\n      assign m_axi_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arid : 0 ;\n      assign m_axi_araddr    = (C_AXI_SUPPORTS_READ ) ? cc_mi_araddr : 0 ;\n      assign m_axi_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_arlen : cc_mi_arlen[3:0]) : 0 ;\n      assign m_axi_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arsize : 0 ;\n      assign m_axi_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arburst : 0 ;\n      assign m_axi_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_arlock : cc_mi_arlock[0]) : 0 ;\n      assign m_axi_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arcache : 0 ;\n      assign m_axi_arprot    = (C_AXI_SUPPORTS_READ ) ? cc_mi_arprot : 0 ;\n      assign m_axi_arregion  = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_arregion : 0 ;\n      assign m_axi_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arqos : 0 ;\n      assign m_axi_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_aruser : 0 ;\n      assign m_axi_arvalid   = (C_AXI_SUPPORTS_READ ) ? cc_mi_arvalid : 0 ;\n      assign m_axi_rready    = (C_AXI_SUPPORTS_READ ) ? cc_mi_rready : 0 ;\n                                                                                                                                                                                                                                                                                        \n      assign cc_mi_awready   = (C_AXI_SUPPORTS_WRITE ) ? m_axi_awready : 0 ;\n      assign cc_mi_wready    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_wready : 0 ;\n      assign cc_mi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid : 0 ;\n      assign cc_mi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bresp : 0 ;\n      assign cc_mi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser : 0 ;\n      assign cc_mi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bvalid : 0 ;\n      assign cc_mi_arready   = (C_AXI_SUPPORTS_READ ) ? m_axi_arready : 0 ;\n      assign cc_mi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid : 0 ;\n      assign cc_mi_rdata     = (C_AXI_SUPPORTS_READ ) ? m_axi_rdata : 0 ;\n      assign cc_mi_rresp     = (C_AXI_SUPPORTS_READ ) ? m_axi_rresp : 0 ;\n      assign cc_mi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast : 1'b0 ;\n      assign cc_mi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser : 0 ;\n      assign cc_mi_rvalid    = (C_AXI_SUPPORTS_READ ) ? m_axi_rvalid : 0 ;\n      \n      if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL!=P_AXILITE)) begin : gen_async_conv\n        \n        fifo_generator_v13_2_5 #(\n          .C_EN_SAFETY_CKT(0),\n          .C_SELECT_XPM(0),\n          .C_INTERFACE_TYPE(2),\n          .C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ? 3 : 2),\n          .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n          .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n          .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n          .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n          .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n          .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),\n          .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n          .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n          .C_HAS_AXI_ID((C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0),\n          .C_AXI_LEN_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 8 : 4),\n          .C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 1 : 2),\n          .C_HAS_AXI_ARUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_AWUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_BUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_RUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_WUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_DIN_WIDTH_RACH(C_FIFO_AR_WIDTH),\n          .C_DIN_WIDTH_RDCH(C_FIFO_R_WIDTH),\n          .C_DIN_WIDTH_WACH(C_FIFO_AW_WIDTH),\n          .C_DIN_WIDTH_WDCH(C_FIFO_W_WIDTH),\n          .C_DIN_WIDTH_WRCH(C_FIFO_B_WIDTH),\n          .C_HAS_AXI_RD_CHANNEL(C_AXI_SUPPORTS_READ),\n          .C_HAS_AXI_WR_CHANNEL(C_AXI_SUPPORTS_WRITE),\n          .C_RACH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_RDCH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_WACH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WDCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WRCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),\n          .C_COMMON_CLOCK(0),\n          .C_COUNT_TYPE(0),\n          .C_DATA_COUNT_WIDTH(10),\n          .C_DEFAULT_VALUE(\"BlankString\"),\n          .C_DIN_WIDTH(18),\n          .C_DOUT_RST_VAL(\"0\"),\n          .C_DOUT_WIDTH(18),\n          .C_ENABLE_RLOCS(0),\n          .C_FAMILY(C_FAMILY),\n          .C_FULL_FLAGS_RST_VAL(1),\n          .C_HAS_ALMOST_EMPTY(0),\n          .C_HAS_ALMOST_FULL(0),\n          .C_HAS_BACKUP(0),\n          .C_HAS_DATA_COUNT(0),\n          .C_HAS_INT_CLK(0),\n          .C_HAS_MEMINIT_FILE(0),\n          .C_HAS_OVERFLOW(0),\n          .C_HAS_RD_DATA_COUNT(0),\n          .C_HAS_RD_RST(0),\n          .C_HAS_RST(1),\n          .C_HAS_SRST(0),\n          .C_HAS_UNDERFLOW(0),\n          .C_HAS_VALID(0),\n          .C_HAS_WR_ACK(0),\n          .C_HAS_WR_DATA_COUNT(0),\n          .C_HAS_WR_RST(0),\n          .C_IMPLEMENTATION_TYPE(0),\n          .C_INIT_WR_PNTR_VAL(0),\n          .C_MEMORY_TYPE(1),\n          .C_MIF_FILE_NAME(\"BlankString\"),\n          .C_OPTIMIZATION_MODE(0),\n          .C_OVERFLOW_LOW(0),\n          .C_PRELOAD_LATENCY(1),\n          .C_PRELOAD_REGS(0),\n          .C_PRIM_FIFO_TYPE(\"4kx4\"),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),\n          .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),\n          .C_PROG_EMPTY_TYPE(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL(1022),\n          .C_PROG_FULL_THRESH_NEGATE_VAL(1021),\n          .C_PROG_FULL_TYPE(0),\n          .C_RD_DATA_COUNT_WIDTH(10),\n          .C_RD_DEPTH(1024),\n          .C_RD_FREQ(1),\n          .C_RD_PNTR_WIDTH(10),\n          .C_UNDERFLOW_LOW(0),\n          .C_USE_DOUT_RST(1),\n          .C_USE_ECC(0),\n          .C_USE_EMBEDDED_REG(0),\n          .C_USE_FIFO16_FLAGS(0),\n          .C_USE_FWFT_DATA_COUNT(0),\n          .C_VALID_LOW(0),\n          .C_WR_ACK_LOW(0),\n          .C_WR_DATA_COUNT_WIDTH(10),\n          .C_WR_DEPTH(1024),\n          .C_WR_FREQ(1),\n          .C_WR_PNTR_WIDTH(10),\n          .C_WR_RESPONSE_LATENCY(1),\n          .C_MSGON_VAL(1),\n          .C_ENABLE_RST_SYNC(1),\n          .C_ERROR_INJECTION_TYPE(0),\n          .C_HAS_SLAVE_CE(0),\n          .C_HAS_MASTER_CE(0),\n          .C_ADD_NGC_CONSTRAINT(0),\n          .C_USE_COMMON_OVERFLOW(0),\n          .C_USE_COMMON_UNDERFLOW(0),\n          .C_USE_DEFAULT_SETTINGS(0),\n          .C_HAS_AXIS_TDATA(1),\n          .C_HAS_AXIS_TID(0),\n          .C_HAS_AXIS_TDEST(0),\n          .C_HAS_AXIS_TUSER(1),\n          .C_HAS_AXIS_TREADY(1),\n          .C_HAS_AXIS_TLAST(0),\n          .C_HAS_AXIS_TSTRB(0),\n          .C_HAS_AXIS_TKEEP(0),\n          .C_AXIS_TDATA_WIDTH(8),\n          .C_AXIS_TID_WIDTH(1),\n          .C_AXIS_TDEST_WIDTH(1),\n          .C_AXIS_TUSER_WIDTH(4),\n          .C_AXIS_TSTRB_WIDTH(1),\n          .C_AXIS_TKEEP_WIDTH(1),\n          .C_AXIS_TYPE(0),\n          .C_IMPLEMENTATION_TYPE_WACH(12),\n          .C_IMPLEMENTATION_TYPE_WDCH(12),\n          .C_IMPLEMENTATION_TYPE_WRCH(12),\n          .C_IMPLEMENTATION_TYPE_RACH(12),\n          .C_IMPLEMENTATION_TYPE_RDCH(12),\n          .C_IMPLEMENTATION_TYPE_AXIS(11),\n          .C_APPLICATION_TYPE_WACH(0),\n          .C_APPLICATION_TYPE_WDCH(0),\n          .C_APPLICATION_TYPE_WRCH(0),\n          .C_APPLICATION_TYPE_RACH(0),\n          .C_APPLICATION_TYPE_RDCH(0),\n          .C_APPLICATION_TYPE_AXIS(0),\n          .C_USE_ECC_WACH(0),\n          .C_USE_ECC_WDCH(0),\n          .C_USE_ECC_WRCH(0),\n          .C_USE_ECC_RACH(0),\n          .C_USE_ECC_RDCH(0),\n          .C_USE_ECC_AXIS(0),\n          .C_ERROR_INJECTION_TYPE_WACH(0),\n          .C_ERROR_INJECTION_TYPE_WDCH(0),\n          .C_ERROR_INJECTION_TYPE_WRCH(0),\n          .C_ERROR_INJECTION_TYPE_RACH(0),\n          .C_ERROR_INJECTION_TYPE_RDCH(0),\n          .C_ERROR_INJECTION_TYPE_AXIS(0),\n          .C_DIN_WIDTH_AXIS(1),\n          .C_WR_DEPTH_WACH(16),\n          .C_WR_DEPTH_WDCH(16),\n          .C_WR_DEPTH_WRCH(16),\n          .C_WR_DEPTH_RACH(16),\n          .C_WR_DEPTH_RDCH(16),\n          .C_WR_DEPTH_AXIS(1024),\n          .C_WR_PNTR_WIDTH_WACH(4),\n          .C_WR_PNTR_WIDTH_WDCH(4),\n          .C_WR_PNTR_WIDTH_WRCH(4),\n          .C_WR_PNTR_WIDTH_RACH(4),\n          .C_WR_PNTR_WIDTH_RDCH(4),\n          .C_WR_PNTR_WIDTH_AXIS(10),\n          .C_HAS_DATA_COUNTS_WACH(0),\n          .C_HAS_DATA_COUNTS_WDCH(0),\n          .C_HAS_DATA_COUNTS_WRCH(0),\n          .C_HAS_DATA_COUNTS_RACH(0),\n          .C_HAS_DATA_COUNTS_RDCH(0),\n          .C_HAS_DATA_COUNTS_AXIS(0),\n          .C_HAS_PROG_FLAGS_WACH(0),\n          .C_HAS_PROG_FLAGS_WDCH(0),\n          .C_HAS_PROG_FLAGS_WRCH(0),\n          .C_HAS_PROG_FLAGS_RACH(0),\n          .C_HAS_PROG_FLAGS_RDCH(0),\n          .C_HAS_PROG_FLAGS_AXIS(0),\n          .C_PROG_FULL_TYPE_WACH(0),\n          .C_PROG_FULL_TYPE_WDCH(0),\n          .C_PROG_FULL_TYPE_WRCH(0),\n          .C_PROG_FULL_TYPE_RACH(0),\n          .C_PROG_FULL_TYPE_RDCH(0),\n          .C_PROG_FULL_TYPE_AXIS(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),\n          .C_PROG_EMPTY_TYPE_WACH(0),\n          .C_PROG_EMPTY_TYPE_WDCH(0),\n          .C_PROG_EMPTY_TYPE_WRCH(0),\n          .C_PROG_EMPTY_TYPE_RACH(0),\n          .C_PROG_EMPTY_TYPE_RDCH(0),\n          .C_PROG_EMPTY_TYPE_AXIS(0),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1021),\n          .C_REG_SLICE_MODE_WACH(0),\n          .C_REG_SLICE_MODE_WDCH(0),\n          .C_REG_SLICE_MODE_WRCH(0),\n          .C_REG_SLICE_MODE_RACH(0),\n          .C_REG_SLICE_MODE_RDCH(0),\n          .C_REG_SLICE_MODE_AXIS(0)\n          )\n          asyncfifo_axi (\n            .s_aclk(s_axi_aclk),\n            .m_aclk(m_axi_aclk),\n            .s_aresetn(async_conv_reset_n),\n            .s_axi_awid           (si_cc_awid),\n            .s_axi_awaddr         (si_cc_awaddr),\n            .s_axi_awlen          (si_cc_awlen),\n            .s_axi_awsize         (si_cc_awsize),\n            .s_axi_awburst        (si_cc_awburst),\n            .s_axi_awlock         (si_cc_awlock),\n            .s_axi_awcache        (si_cc_awcache),\n            .s_axi_awprot         (si_cc_awprot),\n            .s_axi_awqos          (si_cc_awqos),\n            .s_axi_awregion       (si_cc_awregion),\n            .s_axi_awuser         (si_cc_awuser),\n            .s_axi_awvalid        (si_cc_awvalid),\n            .s_axi_awready        (si_cc_awready),\n            .s_axi_wid            (si_cc_wid),\n            .s_axi_wdata          (si_cc_wdata),\n            .s_axi_wstrb          (si_cc_wstrb),\n            .s_axi_wlast          (si_cc_wlast),\n            .s_axi_wuser          (si_cc_wuser),\n            .s_axi_wvalid         (si_cc_wvalid),\n            .s_axi_wready         (si_cc_wready),\n            .s_axi_bid            (si_cc_bid),\n            .s_axi_bresp          (si_cc_bresp),\n            .s_axi_buser          (si_cc_buser),\n            .s_axi_bvalid         (si_cc_bvalid),\n            .s_axi_bready         (si_cc_bready),\n            .m_axi_awid           (cc_mi_awid),\n            .m_axi_awaddr         (cc_mi_awaddr),\n            .m_axi_awlen          (cc_mi_awlen),\n            .m_axi_awsize         (cc_mi_awsize),\n            .m_axi_awburst        (cc_mi_awburst),\n            .m_axi_awlock         (cc_mi_awlock),\n            .m_axi_awcache        (cc_mi_awcache),\n            .m_axi_awprot         (cc_mi_awprot),\n            .m_axi_awqos          (cc_mi_awqos),\n            .m_axi_awregion       (cc_mi_awregion),\n            .m_axi_awuser         (cc_mi_awuser),\n            .m_axi_awvalid        (cc_mi_awvalid),\n            .m_axi_awready        (cc_mi_awready),\n            .m_axi_wid            (cc_mi_wid),\n            .m_axi_wdata          (cc_mi_wdata),\n            .m_axi_wstrb          (cc_mi_wstrb),\n            .m_axi_wlast          (cc_mi_wlast),\n            .m_axi_wuser          (cc_mi_wuser),\n            .m_axi_wvalid         (cc_mi_wvalid),\n            .m_axi_wready         (cc_mi_wready),\n            .m_axi_bid            (cc_mi_bid),\n            .m_axi_bresp          (cc_mi_bresp),\n            .m_axi_buser          (cc_mi_buser),\n            .m_axi_bvalid         (cc_mi_bvalid),\n            .m_axi_bready         (cc_mi_bready),\n            .s_axi_arid           (si_cc_arid),\n            .s_axi_araddr         (si_cc_araddr),\n            .s_axi_arlen          (si_cc_arlen),\n            .s_axi_arsize         (si_cc_arsize),\n            .s_axi_arburst        (si_cc_arburst),\n            .s_axi_arlock         (si_cc_arlock),\n            .s_axi_arcache        (si_cc_arcache),\n            .s_axi_arprot         (si_cc_arprot),\n            .s_axi_arqos          (si_cc_arqos),\n            .s_axi_arregion       (si_cc_arregion),\n            .s_axi_aruser         (si_cc_aruser),\n            .s_axi_arvalid        (si_cc_arvalid),\n            .s_axi_arready        (si_cc_arready),\n            .s_axi_rid            (si_cc_rid),\n            .s_axi_rdata          (si_cc_rdata),\n            .s_axi_rresp          (si_cc_rresp),\n            .s_axi_rlast          (si_cc_rlast),\n            .s_axi_ruser          (si_cc_ruser),\n            .s_axi_rvalid         (si_cc_rvalid),\n            .s_axi_rready         (si_cc_rready),\n            .m_axi_arid           (cc_mi_arid),\n            .m_axi_araddr         (cc_mi_araddr),\n            .m_axi_arlen          (cc_mi_arlen),\n            .m_axi_arsize         (cc_mi_arsize),\n            .m_axi_arburst        (cc_mi_arburst),\n            .m_axi_arlock         (cc_mi_arlock),\n            .m_axi_arcache        (cc_mi_arcache),\n            .m_axi_arprot         (cc_mi_arprot),\n            .m_axi_arqos          (cc_mi_arqos),\n            .m_axi_arregion       (cc_mi_arregion),\n            .m_axi_aruser         (cc_mi_aruser),\n            .m_axi_arvalid        (cc_mi_arvalid),\n            .m_axi_arready        (cc_mi_arready),\n            .m_axi_rid            (cc_mi_rid),\n            .m_axi_rdata          (cc_mi_rdata),\n            .m_axi_rresp          (cc_mi_rresp),\n            .m_axi_rlast          (cc_mi_rlast),\n            .m_axi_ruser          (cc_mi_ruser),\n            .m_axi_rvalid         (cc_mi_rvalid),\n            .m_axi_rready         (cc_mi_rready),\n            .m_aclk_en(1'b1),\n            .s_aclk_en(1'b1),\n            .almost_empty(),\n            .almost_full(),\n            .axis_data_count(),\n            .axis_dbiterr(),\n            .axis_injectdbiterr(1'b0),\n            .axis_injectsbiterr(1'b0),\n            .axis_overflow(),\n            .axis_prog_empty(),\n            .axis_prog_empty_thresh(10'b0),\n            .axis_prog_full(),\n            .axis_prog_full_thresh(10'b0),\n            .axis_rd_data_count(),\n            .axis_sbiterr(),\n            .axis_underflow(),\n            .axis_wr_data_count(),\n            .axi_ar_data_count(),\n            .axi_ar_dbiterr(),\n            .axi_ar_injectdbiterr(1'b0),\n            .axi_ar_injectsbiterr(1'b0),\n            .axi_ar_overflow(),\n            .axi_ar_prog_empty(),\n            .axi_ar_prog_empty_thresh(4'b0),\n            .axi_ar_prog_full(),\n            .axi_ar_prog_full_thresh(4'b0),\n            .axi_ar_rd_data_count(),\n            .axi_ar_sbiterr(),\n            .axi_ar_underflow(),\n            .axi_ar_wr_data_count(),\n            .axi_aw_data_count(),\n            .axi_aw_dbiterr(),\n            .axi_aw_injectdbiterr(1'b0),\n            .axi_aw_injectsbiterr(1'b0),\n            .axi_aw_overflow(),\n            .axi_aw_prog_empty(),\n            .axi_aw_prog_empty_thresh(4'b0),\n            .axi_aw_prog_full(),\n            .axi_aw_prog_full_thresh(4'b0),\n            .axi_aw_rd_data_count(),\n            .axi_aw_sbiterr(),\n            .axi_aw_underflow(),\n            .axi_aw_wr_data_count(),\n            .axi_b_data_count(),\n            .axi_b_dbiterr(),\n            .axi_b_injectdbiterr(1'b0),\n            .axi_b_injectsbiterr(1'b0),\n            .axi_b_overflow(),\n            .axi_b_prog_empty(),\n            .axi_b_prog_empty_thresh(4'b0),\n            .axi_b_prog_full(),\n            .axi_b_prog_full_thresh(4'b0),\n            .axi_b_rd_data_count(),\n            .axi_b_sbiterr(),\n            .axi_b_underflow(),\n            .axi_b_wr_data_count(),\n            .axi_r_data_count(),\n            .axi_r_dbiterr(),\n            .axi_r_injectdbiterr(1'b0),\n            .axi_r_injectsbiterr(1'b0),\n            .axi_r_overflow(),\n            .axi_r_prog_empty(),\n            .axi_r_prog_empty_thresh(4'b0),\n            .axi_r_prog_full(),\n            .axi_r_prog_full_thresh(4'b0),\n            .axi_r_rd_data_count(),\n            .axi_r_sbiterr(),\n            .axi_r_underflow(),\n            .axi_r_wr_data_count(),\n            .axi_w_data_count(),\n            .axi_w_dbiterr(),\n            .axi_w_injectdbiterr(1'b0),\n            .axi_w_injectsbiterr(1'b0),\n            .axi_w_overflow(),\n            .axi_w_prog_empty(),\n            .axi_w_prog_empty_thresh(4'b0),\n            .axi_w_prog_full(),\n            .axi_w_prog_full_thresh(4'b0),\n            .axi_w_rd_data_count(),\n            .axi_w_sbiterr(),\n            .axi_w_underflow(),\n            .axi_w_wr_data_count(),\n            .backup(1'b0),\n            .backup_marker(1'b0),\n            .clk(1'b0),\n            .data_count(),\n            .dbiterr(),\n            .din(18'b0),\n            .dout(),\n            .empty(),\n            .full(),\n            .injectdbiterr(1'b0),\n            .injectsbiterr(1'b0),\n            .int_clk(1'b0),\n            .m_axis_tdata(),\n            .m_axis_tdest(),\n            .m_axis_tid(),\n            .m_axis_tkeep(),\n            .m_axis_tlast(),\n            .m_axis_tready(1'b0),\n            .m_axis_tstrb(),\n            .m_axis_tuser(),\n            .m_axis_tvalid(),\n            .overflow(),\n            .prog_empty(),\n            .prog_empty_thresh(10'b0),\n            .prog_empty_thresh_assert(10'b0),\n            .prog_empty_thresh_negate(10'b0),\n            .prog_full(),\n            .prog_full_thresh(10'b0),\n            .prog_full_thresh_assert(10'b0),\n            .prog_full_thresh_negate(10'b0),\n            .rd_clk(1'b0),\n            .rd_data_count(),\n            .rd_en(1'b0),\n            .rd_rst(1'b0),\n            .rst(1'b0),\n            .sbiterr(),\n            .srst(1'b0),\n            .s_axis_tdata(8'b0),\n            .s_axis_tdest(1'b0),\n            .s_axis_tid(1'b0),\n            .s_axis_tkeep(1'b0),\n            .s_axis_tlast(1'b0),\n            .s_axis_tready(),\n            .s_axis_tstrb(1'b0),\n            .s_axis_tuser(4'b0),\n            .s_axis_tvalid(1'b0),\n            .underflow(),\n            .valid(),\n            .wr_ack(),\n            .wr_clk(1'b0),\n            .wr_data_count(),\n            .wr_en(1'b0),\n            .wr_rst(1'b0),\n            .wr_rst_busy(),\n            .rd_rst_busy(),\n            .sleep(1'b0)\n        );\n      end else if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_async_lite_conv\n        localparam C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n        `include \"axi_infrastructure_v1_1_0.vh\"\n\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n        axi_infrastructure_v1_1_0_axi2vector #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        axi2vec ( \n          .s_axi_awid      ( si_cc_awid      ) ,\n          .s_axi_awaddr    ( si_cc_awaddr    ) ,\n          .s_axi_awlen     ( s_axi_awlen     ) ,\n          .s_axi_awsize    ( si_cc_awsize    ) ,\n          .s_axi_awburst   ( si_cc_awburst   ) ,\n          .s_axi_awlock    ( s_axi_awlock    ) ,\n          .s_axi_awcache   ( si_cc_awcache   ) ,\n          .s_axi_awprot    ( si_cc_awprot    ) ,\n          .s_axi_awqos     ( si_cc_awqos     ) ,\n          .s_axi_awuser    ( si_cc_awuser    ) ,\n          .s_axi_awregion  ( si_cc_awregion  ) ,\n          .s_axi_wid       ( si_cc_wid       ) ,\n          .s_axi_wdata     ( si_cc_wdata     ) ,\n          .s_axi_wstrb     ( si_cc_wstrb     ) ,\n          .s_axi_wlast     ( si_cc_wlast     ) ,\n          .s_axi_wuser     ( si_cc_wuser     ) ,\n          .s_axi_bid       ( si_cc_bid       ) ,\n          .s_axi_bresp     ( si_cc_bresp     ) ,\n          .s_axi_buser     ( si_cc_buser     ) ,\n          .s_axi_arid      ( si_cc_arid      ) ,\n          .s_axi_araddr    ( si_cc_araddr    ) ,\n          .s_axi_arlen     ( s_axi_arlen     ) ,\n          .s_axi_arsize    ( si_cc_arsize    ) ,\n          .s_axi_arburst   ( si_cc_arburst   ) ,\n          .s_axi_arlock    ( s_axi_arlock    ) ,\n          .s_axi_arcache   ( si_cc_arcache   ) ,\n          .s_axi_arprot    ( si_cc_arprot    ) ,\n          .s_axi_arqos     ( si_cc_arqos     ) ,\n          .s_axi_aruser    ( si_cc_aruser    ) ,\n          .s_axi_arregion  ( si_cc_arregion  ) ,\n          .s_axi_rid       ( si_cc_rid       ) ,\n          .s_axi_rdata     ( si_cc_rdata     ) ,\n          .s_axi_rresp     ( si_cc_rresp     ) ,\n          .s_axi_rlast     ( si_cc_rlast     ) ,\n          .s_axi_ruser     ( si_cc_ruser     ) ,\n          .s_awpayload     ( s_awpayload ) ,\n          .s_wpayload      ( s_wpayload  ) ,\n          .s_bpayload      ( s_bpayload  ) ,\n          .s_arpayload     ( s_arpayload ) ,\n          .s_rpayload      ( s_rpayload  ) \n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_AWPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_aw (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_awvalid),\n          .s_ready  (si_cc_awready),\n          .s_payld  (s_awpayload),\n          .m_valid  (cc_mi_awvalid),\n          .m_ready  (cc_mi_awready),\n          .m_payld  (m_awpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_ARPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_ar (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_arvalid),\n          .s_ready  (si_cc_arready),\n          .s_payld  (s_arpayload),\n          .m_valid  (cc_mi_arvalid),\n          .m_ready  (cc_mi_arready),\n          .m_payld  (m_arpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_WPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_w (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_wvalid),\n          .s_ready  (si_cc_wready),\n          .s_payld  (s_wpayload),\n          .m_valid  (cc_mi_wvalid),\n          .m_ready  (cc_mi_wready),\n          .m_payld  (m_wpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_BPAYLOAD_WIDTH)\n        ) clock_conv_lite_resp_b (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_bvalid),\n          .s_ready  (cc_mi_bready),\n          .s_payld  (m_bpayload),\n          .m_valid  (si_cc_bvalid),\n          .m_ready  (si_cc_bready),\n          .m_payld  (s_bpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_RPAYLOAD_WIDTH)\n        ) clock_conv_lite_resp_r (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_rvalid),\n          .s_ready  (cc_mi_rready),\n          .s_payld  (m_rpayload),\n          .m_valid  (si_cc_rvalid),\n          .m_ready  (si_cc_rready),\n          .m_payld  (s_rpayload)\n        );\n\n        axi_infrastructure_v1_1_0_vector2axi #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        vec2axi ( \n          .m_awpayload    ( m_awpayload    ) ,\n          .m_wpayload     ( m_wpayload     ) ,\n          .m_bpayload     ( m_bpayload     ) ,\n          .m_arpayload    ( m_arpayload    ) ,\n          .m_rpayload     ( m_rpayload     ) ,\n          .m_axi_awid     ( cc_mi_awid     ) ,\n          .m_axi_awaddr   ( cc_mi_awaddr   ) ,\n          .m_axi_awlen    ( cc_mi_awlen    ) ,\n          .m_axi_awsize   ( cc_mi_awsize   ) ,\n          .m_axi_awburst  ( cc_mi_awburst  ) ,\n          .m_axi_awlock   ( cc_mi_awlock   ) ,\n          .m_axi_awcache  ( cc_mi_awcache  ) ,\n          .m_axi_awprot   ( cc_mi_awprot   ) ,\n          .m_axi_awqos    ( cc_mi_awqos    ) ,\n          .m_axi_awuser   ( cc_mi_awuser   ) ,\n          .m_axi_awregion ( cc_mi_awregion ) ,\n          .m_axi_wid      ( cc_mi_wid      ) ,\n          .m_axi_wdata    ( cc_mi_wdata    ) ,\n          .m_axi_wstrb    ( cc_mi_wstrb    ) ,\n          .m_axi_wlast    ( cc_mi_wlast    ) ,\n          .m_axi_wuser    ( cc_mi_wuser    ) ,\n          .m_axi_bid      ( cc_mi_bid      ) ,\n          .m_axi_bresp    ( cc_mi_bresp    ) ,\n          .m_axi_buser    ( cc_mi_buser    ) ,\n          .m_axi_arid     ( cc_mi_arid     ) ,\n          .m_axi_araddr   ( cc_mi_araddr   ) ,\n          .m_axi_arlen    ( cc_mi_arlen    ) ,\n          .m_axi_arsize   ( cc_mi_arsize   ) ,\n          .m_axi_arburst  ( cc_mi_arburst  ) ,\n          .m_axi_arlock   ( cc_mi_arlock   ) ,\n          .m_axi_arcache  ( cc_mi_arcache  ) ,\n          .m_axi_arprot   ( cc_mi_arprot   ) ,\n          .m_axi_arqos    ( cc_mi_arqos    ) ,\n          .m_axi_aruser   ( cc_mi_aruser   ) ,\n          .m_axi_arregion ( cc_mi_arregion ) ,\n          .m_axi_rid      ( cc_mi_rid      ) ,\n          .m_axi_rdata    ( cc_mi_rdata    ) ,\n          .m_axi_rresp    ( cc_mi_rresp    ) ,\n          .m_axi_rlast    ( cc_mi_rlast    ) ,\n          .m_axi_ruser    ( cc_mi_ruser    ) \n        );\n\n      end else begin : gen_sync_conv\n        \n        assign {fast_aclk, slow_aclk} = P_SI_LT_MI ? {m_axi_aclk, s_axi_aclk} : {s_axi_aclk, m_axi_aclk};\n    \n        // Sample cycle used to determine when to assert a signal on a fast clock\n        // to be flopped onto a slow clock.\n        axi_clock_converter_v2_1_21_axic_sample_cycle_ratio #(\n          .C_RATIO ( P_ACLK_RATIO )\n        )\n        axic_sample_cycle_inst (\n          .SLOW_ACLK          ( slow_aclk               ) ,\n          .FAST_ACLK          ( fast_aclk               ) ,\n          .SAMPLE_CYCLE_EARLY ( sample_cycle_early ) ,\n          .SAMPLE_CYCLE       ( sample_cycle       )\n        );\n    \n      ////////////////////////////////////////////////////////////////////////////////\n      // AXI write channels\n      ////////////////////////////////////////////////////////////////////////////////\n        if (C_AXI_SUPPORTS_WRITE) begin : gen_conv_write_ch\n    \n          // Write Address Port\n          assign s_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH]     = si_cc_awaddr   ;\n          assign s_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH]     = si_cc_awprot   ;\n          assign cc_mi_awaddr   = m_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH];\n          assign cc_mi_awprot   = m_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_aw_axi4\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen    ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock[0] ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH] = si_cc_awregion ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awregion = m_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_aw_axi3\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen[3:0] ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock   ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_aw_user\n            assign s_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH]  = si_cc_awuser;\n            assign cc_mi_awuser = m_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AW_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          aw_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_aw_mesg ) ,\n            .S_VALID   ( si_cc_awvalid   ) ,\n            .S_READY   ( si_cc_awready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_aw_mesg ) ,\n            .M_VALID   ( cc_mi_awvalid   ) ,\n            .M_READY   ( cc_mi_awready   )\n          );\n    \n          // Write Data Port\n          assign s_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH] = si_cc_wdata; \n          assign s_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH] = si_cc_wstrb; \n          assign cc_mi_wdata    = m_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH];\n          assign cc_mi_wstrb    = m_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_w_axi4\n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_w_axi3\n            assign s_w_mesg[C_WID_RIGHT+:C_WID_WIDTH]     = si_cc_wid; \n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wid      = m_w_mesg[C_WID_RIGHT+:C_WID_WIDTH];\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_w_user\n            assign s_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH]  = si_cc_wuser;\n            assign cc_mi_wuser = m_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH  ( C_W_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE           ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          w_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_w_mesg ) ,\n            .S_VALID   ( si_cc_wvalid   ) ,\n            .S_READY   ( si_cc_wready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_w_mesg ) ,\n            .M_VALID   ( cc_mi_wvalid   ) ,\n            .M_READY   ( cc_mi_wready   )\n          );\n    \n          // Write Response Port\n          assign m_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH] = cc_mi_bresp;\n          assign si_cc_bresp    = s_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_b_axi\n            assign m_b_mesg[C_BID_RIGHT+:C_BID_WIDTH]     = cc_mi_bid;\n            assign si_cc_bid      = s_b_mesg[C_BID_RIGHT+:C_BID_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_b_user\n            assign m_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH] = cc_mi_buser;\n            assign si_cc_buser  = s_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_B_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          b_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_b_mesg ) ,\n            .S_VALID   ( cc_mi_bvalid   ) ,\n            .S_READY   ( cc_mi_bready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_b_mesg ) ,\n            .M_VALID   ( si_cc_bvalid   ) ,\n            .M_READY   ( si_cc_bready   )\n          );\n    \n        end else begin : gen_tieoff_write_ch\n    \n          // Write address port\n          assign cc_mi_awid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_awaddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_awlen    = {8{1'b0}};\n          assign cc_mi_awsize   = {3{1'b0}};\n          assign cc_mi_awburst  = {2{1'b0}};\n          assign cc_mi_awlock   = {2{1'b0}};\n          assign cc_mi_awcache  = {4{1'b0}};\n          assign cc_mi_awprot   = {3{1'b0}};\n          assign cc_mi_awregion = {4{1'b0}};\n          assign cc_mi_awqos    = {4{1'b0}};\n          assign cc_mi_awuser   = {C_AXI_AWUSER_WIDTH{1'b0}};\n          assign cc_mi_awvalid  = 1'b0;\n          assign si_cc_awready  = 1'b0;\n    \n          // Write data port\n          assign cc_mi_wid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_wdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign cc_mi_wstrb    = {C_AXI_DATA_WIDTH/8{1'b0}};\n          assign cc_mi_wlast    = 1'b0;\n          assign cc_mi_wuser    = {C_AXI_WUSER_WIDTH{1'b0}};\n          assign cc_mi_wvalid   = 1'b0;\n          assign si_cc_wready   = 1'b0;\n    \n          // Write response port\n          assign si_cc_bid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_bresp    = {2{1'b0}};\n          assign si_cc_buser    = {C_AXI_BUSER_WIDTH{1'b0}};\n          assign si_cc_bvalid   = 1'b0;\n          assign cc_mi_bready   = 1'b0;\n        end\n    \n        ////////////////////////////////////////////////////////////////////////////////\n        // AXI read channels\n        ////////////////////////////////////////////////////////////////////////////////\n    \n        if (C_AXI_SUPPORTS_READ) begin : gen_conv_read_ch\n    \n          // Read Address Port\n          assign s_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH]     = si_cc_araddr   ;\n          assign s_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH]     = si_cc_arprot   ;\n          assign cc_mi_araddr   = m_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH];\n          assign cc_mi_arprot   = m_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_ar_axi4\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen    ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock[0] ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH] = si_cc_arregion ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arregion = m_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_ar_axi3\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen[3:0] ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock   ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_ar_user\n            assign s_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH]  = si_cc_aruser;\n            assign cc_mi_aruser = m_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AR_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          ar_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_ar_mesg ) ,\n            .S_VALID   ( si_cc_arvalid   ) ,\n            .S_READY   ( si_cc_arready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN  ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_ar_mesg ) ,\n            .M_VALID   ( cc_mi_arvalid   ) ,\n            .M_READY   ( cc_mi_arready   )\n          );\n    \n          // Read Data Port\n          assign m_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH] = cc_mi_rdata; \n          assign m_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH] = cc_mi_rresp; \n          assign si_cc_rdata    = s_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH];\n          assign si_cc_rresp    = s_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_r_axi\n            assign m_r_mesg[C_RID_RIGHT+:C_RID_WIDTH]     = cc_mi_rid;   \n            assign m_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH] = cc_mi_rlast;\n            assign si_cc_rid      = s_r_mesg[C_RID_RIGHT+:C_RID_WIDTH];\n            assign si_cc_rlast    = s_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_r_user\n            assign m_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH] = cc_mi_ruser;\n            assign si_cc_ruser  = s_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_R_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          r_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_r_mesg ) ,\n            .S_VALID   ( cc_mi_rvalid   ) ,\n            .S_READY   ( cc_mi_rready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_r_mesg ) ,\n            .M_VALID   ( si_cc_rvalid   ) ,\n            .M_READY   ( si_cc_rready   )\n          );\n    \n        end else begin : gen_tieoff_read_ch\n    \n          // Read Address Port\n          assign cc_mi_arid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_araddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_arlen    = {8{1'b0}};\n          assign cc_mi_arsize   = {3{1'b0}};\n          assign cc_mi_arburst  = {2{1'b0}};\n          assign cc_mi_arlock   = {2{1'b0}};\n          assign cc_mi_arcache  = {4{1'b0}};\n          assign cc_mi_arprot   = {3{1'b0}};\n          assign cc_mi_arregion = {4{1'b0}};\n          assign cc_mi_arqos    = {4{1'b0}};\n          assign cc_mi_aruser   = {C_AXI_ARUSER_WIDTH{1'b0}};\n          assign cc_mi_arvalid  = 1'b0;\n          assign si_cc_arready  = 1'b0;\n    \n          // Read data port\n          assign si_cc_rid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_rdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign si_cc_rresp    = {2{1'b0}};\n          assign si_cc_rlast    = 1'b0;\n          assign si_cc_ruser    = {C_AXI_RUSER_WIDTH{1'b0}};\n          assign si_cc_rvalid   = 1'b0;\n          assign cc_mi_rready   = 1'b0;\n        end\n      end\n    end\n\n  endgenerate\n\nendmodule\n\n\n\n", "num_lines": 2178}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1\n// IP Revision: 21\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_clock_converter_512 (\n  s_axi_aclk,\n  s_axi_aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awuser,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_aruser,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_aclk,\n  m_axi_aresetn,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awuser,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_aruser,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_CLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 SI_CLK CLK\" *)\ninput wire s_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 SI_RST RST\" *)\ninput wire s_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWUSER\" *)\ninput wire [7 : 0] s_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARUSER\" *)\ninput wire [7 : 0] s_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 8, ARUSER_WIDTH 8, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_CLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 MI_CLK CLK\" *)\ninput wire m_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 MI_RST RST\" *)\ninput wire m_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWUSER\" *)\noutput wire [7 : 0] m_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARUSER\" *)\noutput wire [7 : 0] m_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 8, ARUSER_WIDTH 8, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_clock_converter_v2_1_21_axi_clock_converter #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_S_AXI_ACLK_RATIO(1),\n    .C_M_AXI_ACLK_RATIO(2),\n    .C_AXI_IS_ACLK_ASYNC(1),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_SUPPORTS_USER_SIGNALS(1),\n    .C_AXI_AWUSER_WIDTH(8),\n    .C_AXI_ARUSER_WIDTH(8),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_AXI_SUPPORTS_WRITE(1),\n    .C_AXI_SUPPORTS_READ(1),\n    .C_SYNCHRONIZER_STAGE(2)\n  ) inst (\n    .s_axi_aclk(s_axi_aclk),\n    .s_axi_aresetn(s_axi_aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(s_axi_awuser),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(s_axi_aruser),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_aclk(m_axi_aclk),\n    .m_axi_aresetn(m_axi_aresetn),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(m_axi_awuser),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(m_axi_aruser),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 441}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/*\n *******************************************************************************\n *\n * FIFO Generator - Verilog Behavioral Model\n *\n *******************************************************************************\n *\n * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.\n *\n * This file contains confidential and proprietary information\n * of Xilinx, Inc. and is protected under U.S. and\n * international copyright and other intellectual property\n * laws.\n *\n * DISCLAIMER\n * This disclaimer is not a license and does not grant any\n * rights to the materials distributed herewith. Except as\n * otherwise provided in a valid license issued to you by\n * Xilinx, and to the maximum extent permitted by applicable\n * law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n * (2) Xilinx shall not be liable (whether in contract or tort,\n * including negligence, or under any other theory of\n * liability) for any loss or damage of any kind or nature\n * related to, arising under or in connection with these\n * materials, including for any direct, or any indirect,\n * special, incidental, or consequential loss or damage\n * (including loss of data, profits, goodwill, or any type of\n * loss or damage suffered as a result of any action brought\n * by a third party) even if such damage or loss was\n * reasonably foreseeable or Xilinx had been advised of the\n * possibility of the same.\n *\n * CRITICAL APPLICATIONS\n * Xilinx products are not designed or intended to be fail-\n * safe, or for use in any application requiring fail-safe\n * performance, such as life-support or safety devices or\n * systems, Class III medical devices, nuclear facilities,\n * applications related to the deployment of airbags, or any\n * other applications that could lead to death, personal\n * injury, or severe property or environmental damage\n * (individually and collectively, \"Critical\n * Applications\"). Customer assumes the sole risk and\n * liability of any use of Xilinx products in Critical\n * Applications, subject only to applicable laws and\n * regulations governing limitations on product liability.\n *\n * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n * PART OF THIS FILE AT ALL TIMES.\n *\n *******************************************************************************\n *******************************************************************************\n *\n * Filename: fifo_generator_vlog_beh.v\n *\n * Author     : Xilinx\n *\n *******************************************************************************\n * Structure:\n * \n * fifo_generator_vlog_beh.v\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_as\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_ss\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_preload0\n * \n *******************************************************************************\n * Description:\n *\n * The Verilog behavioral model for the FIFO Generator.\n *\n *   The behavioral model has three parts:\n *      - The behavioral model for independent clocks FIFOs (_as)\n *      - The behavioral model for common clock FIFOs (_ss)\n *      - The \"preload logic\" block which implements First-word Fall-through\n * \n *******************************************************************************\n * Description:\n *  The verilog behavioral model for the FIFO generator core.\n *\n *******************************************************************************\n */\n\n`timescale 1ps/1ps\n`ifndef TCQ\n `define TCQ 100\n`endif\n\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_vlog_beh\n  #(\n    //-----------------------------------------------------------------------\n    // Generic Declarations\n    //-----------------------------------------------------------------------\n    parameter C_COMMON_CLOCK                 = 0,\n    parameter C_COUNT_TYPE                   = 0,\n    parameter C_DATA_COUNT_WIDTH             = 2,\n    parameter C_DEFAULT_VALUE                = \"\",\n    parameter C_DIN_WIDTH                    = 8,\n    parameter C_DOUT_RST_VAL                 = \"\",\n    parameter C_DOUT_WIDTH                   = 8,\n    parameter C_ENABLE_RLOCS                 = 0,\n    parameter C_FAMILY                       = \"\",\n    parameter C_FULL_FLAGS_RST_VAL           = 1,\n    parameter C_HAS_ALMOST_EMPTY             = 0,\n    parameter C_HAS_ALMOST_FULL              = 0,\n    parameter C_HAS_BACKUP                   = 0,\n    parameter C_HAS_DATA_COUNT               = 0,\n    parameter C_HAS_INT_CLK                  = 0,\n    parameter C_HAS_MEMINIT_FILE             = 0,\n    parameter C_HAS_OVERFLOW                 = 0,\n    parameter C_HAS_RD_DATA_COUNT            = 0,\n    parameter C_HAS_RD_RST                   = 0,\n    parameter C_HAS_RST                      = 1,\n    parameter C_HAS_SRST                     = 0,\n    parameter C_HAS_UNDERFLOW                = 0,\n    parameter C_HAS_VALID                    = 0,\n    parameter C_HAS_WR_ACK                   = 0,\n    parameter C_HAS_WR_DATA_COUNT            = 0,\n    parameter C_HAS_WR_RST                   = 0,\n    parameter C_IMPLEMENTATION_TYPE          = 0,\n    parameter C_INIT_WR_PNTR_VAL             = 0,\n    parameter C_MEMORY_TYPE                  = 1,\n    parameter C_MIF_FILE_NAME                = \"\",\n    parameter C_OPTIMIZATION_MODE            = 0,\n    parameter C_OVERFLOW_LOW                 = 0,\n    parameter C_EN_SAFETY_CKT                = 0,\n    parameter C_PRELOAD_LATENCY              = 1,\n    parameter C_PRELOAD_REGS                 = 0,\n    parameter C_PRIM_FIFO_TYPE               = \"4kx4\",\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter C_PROG_EMPTY_TYPE              = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter C_PROG_FULL_TYPE               = 0,\n    parameter C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter C_RD_DEPTH                     = 256,\n    parameter C_RD_FREQ                      = 1,\n    parameter C_RD_PNTR_WIDTH                = 8,\n    parameter C_UNDERFLOW_LOW                = 0,\n    parameter C_USE_DOUT_RST                 = 0,\n    parameter C_USE_ECC                      = 0,\n    parameter C_USE_EMBEDDED_REG             = 0,\n    parameter C_USE_PIPELINE_REG             = 0,\n    parameter C_POWER_SAVING_MODE            = 0,\n    parameter C_USE_FIFO16_FLAGS             = 0,\n    parameter C_USE_FWFT_DATA_COUNT          = 0,\n    parameter C_VALID_LOW                    = 0,\n    parameter C_WR_ACK_LOW                   = 0,\n    parameter C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter C_WR_DEPTH                     = 256,\n    parameter C_WR_FREQ                      = 1,\n    parameter C_WR_PNTR_WIDTH                = 8,\n    parameter C_WR_RESPONSE_LATENCY          = 1,\n    parameter C_MSGON_VAL                    = 1,\n    parameter C_ENABLE_RST_SYNC              = 1,\n    parameter C_ERROR_INJECTION_TYPE         = 0,\n    parameter C_SYNCHRONIZER_STAGE           = 2,\n\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE               = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3\n    parameter C_AXI_TYPE                     = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3\n    parameter C_HAS_AXI_WR_CHANNEL           = 0,\n    parameter C_HAS_AXI_RD_CHANNEL           = 0,\n    parameter C_HAS_SLAVE_CE                 = 0,\n    parameter C_HAS_MASTER_CE                = 0,\n    parameter C_ADD_NGC_CONSTRAINT           = 0,\n    parameter C_USE_COMMON_UNDERFLOW         = 0,\n    parameter C_USE_COMMON_OVERFLOW          = 0,\n    parameter C_USE_DEFAULT_SETTINGS         = 0,\n\n    // AXI Full/Lite\n    parameter C_AXI_ID_WIDTH                 = 0,\n    parameter C_AXI_ADDR_WIDTH               = 0,\n    parameter C_AXI_DATA_WIDTH               = 0,\n    parameter C_AXI_LEN_WIDTH                = 8,\n    parameter C_AXI_LOCK_WIDTH               = 2,\n    parameter C_HAS_AXI_ID                   = 0,\n    parameter C_HAS_AXI_AWUSER               = 0,\n    parameter C_HAS_AXI_WUSER                = 0,\n    parameter C_HAS_AXI_BUSER                = 0,\n    parameter C_HAS_AXI_ARUSER               = 0,\n    parameter C_HAS_AXI_RUSER                = 0,\n    parameter C_AXI_ARUSER_WIDTH             = 0,\n    parameter C_AXI_AWUSER_WIDTH             = 0,\n    parameter C_AXI_WUSER_WIDTH              = 0,\n    parameter C_AXI_BUSER_WIDTH              = 0,\n    parameter C_AXI_RUSER_WIDTH              = 0,\n\n    // AXI Streaming\n    parameter C_HAS_AXIS_TDATA               = 0,\n    parameter C_HAS_AXIS_TID                 = 0,\n    parameter C_HAS_AXIS_TDEST               = 0,\n    parameter C_HAS_AXIS_TUSER               = 0,\n    parameter C_HAS_AXIS_TREADY              = 0,\n    parameter C_HAS_AXIS_TLAST               = 0,\n    parameter C_HAS_AXIS_TSTRB               = 0,\n    parameter C_HAS_AXIS_TKEEP               = 0,\n    parameter C_AXIS_TDATA_WIDTH             = 1,\n    parameter C_AXIS_TID_WIDTH               = 1,\n    parameter C_AXIS_TDEST_WIDTH             = 1,\n    parameter C_AXIS_TUSER_WIDTH             = 1,\n    parameter C_AXIS_TSTRB_WIDTH             = 1,\n    parameter C_AXIS_TKEEP_WIDTH             = 1,\n\n    // AXI Channel Type\n    // WACH --> Write Address Channel\n    // WDCH --> Write Data Channel\n    // WRCH --> Write Response Channel\n    // RACH --> Read Address Channel\n    // RDCH --> Read Data Channel\n    // AXIS --> AXI Streaming\n    parameter C_WACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic\n    parameter C_WDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_WRCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_AXIS_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n\n    // AXI Implementation Type\n    // 1 = Common Clock Block RAM FIFO\n    // 2 = Common Clock Distributed RAM FIFO\n    // 11 = Independent Clock Block RAM FIFO\n    // 12 = Independent Clock Distributed RAM FIFO\n    parameter C_IMPLEMENTATION_TYPE_WACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WRCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_AXIS     = 0,\n\n    // AXI FIFO Type\n    // 0 = Data FIFO\n    // 1 = Packet FIFO\n    // 2 = Low Latency Sync FIFO\n    // 3 = Low Latency Async FIFO\n    parameter C_APPLICATION_TYPE_WACH        = 0,\n    parameter C_APPLICATION_TYPE_WDCH        = 0,\n    parameter C_APPLICATION_TYPE_WRCH        = 0,\n    parameter C_APPLICATION_TYPE_RACH        = 0,\n    parameter C_APPLICATION_TYPE_RDCH        = 0,\n    parameter C_APPLICATION_TYPE_AXIS        = 0,\n\n    // AXI Built-in FIFO Primitive Type\n    // 512x36, 1kx18, 2kx9, 4kx4, etc\n    parameter C_PRIM_FIFO_TYPE_WACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WRCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_AXIS          = \"512x36\",\n\n    // Enable ECC\n    // 0 = ECC disabled\n    // 1 = ECC enabled\n    parameter C_USE_ECC_WACH                 = 0,\n    parameter C_USE_ECC_WDCH                 = 0,\n    parameter C_USE_ECC_WRCH                 = 0,\n    parameter C_USE_ECC_RACH                 = 0,\n    parameter C_USE_ECC_RDCH                 = 0,\n    parameter C_USE_ECC_AXIS                 = 0,\n\n    // ECC Error Injection Type\n    // 0 = No Error Injection\n    // 1 = Single Bit Error Injection\n    // 2 = Double Bit Error Injection\n    // 3 = Single Bit and Double Bit Error Injection\n    parameter C_ERROR_INJECTION_TYPE_WACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WRCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_AXIS    = 0,\n\n    // Input Data Width\n    // Accumulation of all AXI input signal's width\n    parameter C_DIN_WIDTH_WACH               = 1,\n    parameter C_DIN_WIDTH_WDCH               = 1,\n    parameter C_DIN_WIDTH_WRCH               = 1,\n    parameter C_DIN_WIDTH_RACH               = 1,\n    parameter C_DIN_WIDTH_RDCH               = 1,\n    parameter C_DIN_WIDTH_AXIS               = 1,\n\n    parameter C_WR_DEPTH_WACH                = 16,\n    parameter C_WR_DEPTH_WDCH                = 16,\n    parameter C_WR_DEPTH_WRCH                = 16,\n    parameter C_WR_DEPTH_RACH                = 16,\n    parameter C_WR_DEPTH_RDCH                = 16,\n    parameter C_WR_DEPTH_AXIS                = 16,\n\n    parameter C_WR_PNTR_WIDTH_WACH           = 4,\n    parameter C_WR_PNTR_WIDTH_WDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_WRCH           = 4,\n    parameter C_WR_PNTR_WIDTH_RACH           = 4,\n    parameter C_WR_PNTR_WIDTH_RDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_AXIS           = 4,\n\n    parameter C_HAS_DATA_COUNTS_WACH         = 0,\n    parameter C_HAS_DATA_COUNTS_WDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_WRCH         = 0,\n    parameter C_HAS_DATA_COUNTS_RACH         = 0,\n    parameter C_HAS_DATA_COUNTS_RDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_AXIS         = 0,\n\n    parameter C_HAS_PROG_FLAGS_WACH          = 0,\n    parameter C_HAS_PROG_FLAGS_WDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_WRCH          = 0,\n    parameter C_HAS_PROG_FLAGS_RACH          = 0,\n    parameter C_HAS_PROG_FLAGS_RDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_AXIS          = 0,\n\n    parameter C_PROG_FULL_TYPE_WACH          = 0,\n    parameter C_PROG_FULL_TYPE_WDCH          = 0,\n    parameter C_PROG_FULL_TYPE_WRCH          = 0,\n    parameter C_PROG_FULL_TYPE_RACH          = 0,\n    parameter C_PROG_FULL_TYPE_RDCH          = 0,\n    parameter C_PROG_FULL_TYPE_AXIS          = 0,\n\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS      = 0,\n\n    parameter C_PROG_EMPTY_TYPE_WACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WRCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_AXIS         = 0,\n\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS     = 0,\n\n    parameter C_REG_SLICE_MODE_WACH          = 0,\n    parameter C_REG_SLICE_MODE_WDCH          = 0,\n    parameter C_REG_SLICE_MODE_WRCH          = 0,\n    parameter C_REG_SLICE_MODE_RACH          = 0,\n    parameter C_REG_SLICE_MODE_RDCH          = 0,\n    parameter C_REG_SLICE_MODE_AXIS          = 0\n\n    )\n\n   (\n    //------------------------------------------------------------------------------\n    // Input and Output Declarations\n    //------------------------------------------------------------------------------\n\n    // Conventional FIFO Interface Signals\n    input                               backup,\n    input                               backup_marker,\n    input                               clk,\n    input                               rst,\n    input                               srst,\n    input                               wr_clk,\n    input                               wr_rst,\n    input                               rd_clk,\n    input                               rd_rst,\n    input [C_DIN_WIDTH-1:0]             din,\n    input                               wr_en,\n    input                               rd_en,\n    // Optional inputs\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_assert,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_negate,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_assert,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_negate,\n    input                               int_clk,\n    input                               injectdbiterr,\n    input                               injectsbiterr,\n    input                               sleep,\n\n    output [C_DOUT_WIDTH-1:0]           dout,\n    output                              full,\n    output                              almost_full,\n    output                              wr_ack,\n    output                              overflow,\n    output                              empty,\n    output                              almost_empty,\n    output                              valid,\n    output                              underflow,\n    output [C_DATA_COUNT_WIDTH-1:0]     data_count,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]  rd_data_count,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count,\n    output                              prog_full,\n    output                              prog_empty,\n    output                              sbiterr,\n    output                              dbiterr,\n    output                              wr_rst_busy,\n    output                              rd_rst_busy,\n\n\n    // AXI Global Signal\n    input                               m_aclk,\n    input                               s_aclk,\n    input                               s_aresetn,\n    input                               s_aclk_en,\n    input                               m_aclk_en,\n    \n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_awid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_awaddr,\n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_awlen,\n    input [3-1:0]                       s_axi_awsize,\n    input [2-1:0]                       s_axi_awburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_awlock,\n    input [4-1:0]                       s_axi_awcache,\n    input [3-1:0]                       s_axi_awprot,\n    input [4-1:0]                       s_axi_awqos,\n    input [4-1:0]                       s_axi_awregion,\n    input [C_AXI_AWUSER_WIDTH-1:0]      s_axi_awuser,\n    input                               s_axi_awvalid,\n    output                              s_axi_awready,\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_wid,\n    input [C_AXI_DATA_WIDTH-1:0]        s_axi_wdata,\n    input [C_AXI_DATA_WIDTH/8-1:0]      s_axi_wstrb,\n    input                               s_axi_wlast,\n    input [C_AXI_WUSER_WIDTH-1:0]       s_axi_wuser,\n    input                               s_axi_wvalid,\n    output                              s_axi_wready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_bid,\n    output [2-1:0]                      s_axi_bresp,\n    output [C_AXI_BUSER_WIDTH-1:0]      s_axi_buser,\n    output                              s_axi_bvalid,\n    input                               s_axi_bready,\n    \n    // AXI Full/Lite Master Write Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_awid,\n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_awlen,\n    output [3-1:0]                      m_axi_awsize,\n    output [2-1:0]                      m_axi_awburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_awlock,\n    output [4-1:0]                      m_axi_awcache,\n    output [3-1:0]                      m_axi_awprot,\n    output [4-1:0]                      m_axi_awqos,\n    output [4-1:0]                      m_axi_awregion,\n    output [C_AXI_AWUSER_WIDTH-1:0]     m_axi_awuser,\n    output                              m_axi_awvalid,\n    input                               m_axi_awready,\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_wid,\n    output [C_AXI_DATA_WIDTH-1:0]       m_axi_wdata,\n    output [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb,\n    output                              m_axi_wlast,\n    output [C_AXI_WUSER_WIDTH-1:0]      m_axi_wuser,\n    output                              m_axi_wvalid,\n    input                               m_axi_wready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_bid,\n    input [2-1:0]                       m_axi_bresp,\n    input [C_AXI_BUSER_WIDTH-1:0]       m_axi_buser,\n    input                               m_axi_bvalid,\n    output                              m_axi_bready,\n    \n    \n    // AXI Full/Lite Slave Read Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_arid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_araddr, \n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_arlen,\n    input [3-1:0]                       s_axi_arsize,\n    input [2-1:0]                       s_axi_arburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_arlock,\n    input [4-1:0]                       s_axi_arcache,\n    input [3-1:0]                       s_axi_arprot,\n    input [4-1:0]                       s_axi_arqos,\n    input [4-1:0]                       s_axi_arregion,\n    input [C_AXI_ARUSER_WIDTH-1:0]      s_axi_aruser,\n    input                               s_axi_arvalid,\n    output                              s_axi_arready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_rid,       \n    output [C_AXI_DATA_WIDTH-1:0]       s_axi_rdata, \n    output [2-1:0]                      s_axi_rresp,\n    output                              s_axi_rlast,\n    output [C_AXI_RUSER_WIDTH-1:0]      s_axi_ruser,\n    output                              s_axi_rvalid,\n    input                               s_axi_rready,\n    \n    \n    \n    // AXI Full/Lite Master Read Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_arid,        \n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,  \n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_arlen,\n    output [3-1:0]                      m_axi_arsize,\n    output [2-1:0]                      m_axi_arburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_arlock,\n    output [4-1:0]                      m_axi_arcache,\n    output [3-1:0]                      m_axi_arprot,\n    output [4-1:0]                      m_axi_arqos,\n    output [4-1:0]                      m_axi_arregion,\n    output [C_AXI_ARUSER_WIDTH-1:0]     m_axi_aruser,\n    output                              m_axi_arvalid,\n    input                               m_axi_arready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_rid,        \n    input [C_AXI_DATA_WIDTH-1:0]        m_axi_rdata,  \n    input [2-1:0]                       m_axi_rresp,\n    input                               m_axi_rlast,\n    input [C_AXI_RUSER_WIDTH-1:0]       m_axi_ruser,\n    input                               m_axi_rvalid,\n    output                              m_axi_rready,\n    \n    \n    // AXI Streaming Slave Signals (Write side)\n    input                               s_axis_tvalid,\n    output                              s_axis_tready,\n    input [C_AXIS_TDATA_WIDTH-1:0]      s_axis_tdata,\n    input [C_AXIS_TSTRB_WIDTH-1:0]      s_axis_tstrb,\n    input [C_AXIS_TKEEP_WIDTH-1:0]      s_axis_tkeep,\n    input                               s_axis_tlast,\n    input [C_AXIS_TID_WIDTH-1:0]        s_axis_tid,\n    input [C_AXIS_TDEST_WIDTH-1:0]      s_axis_tdest,\n    input [C_AXIS_TUSER_WIDTH-1:0]      s_axis_tuser,\n    \n    // AXI Streaming Master Signals (Read side)\n    output                              m_axis_tvalid,\n    input                               m_axis_tready,\n    output [C_AXIS_TDATA_WIDTH-1:0]     m_axis_tdata,\n    output [C_AXIS_TSTRB_WIDTH-1:0]     m_axis_tstrb,\n    output [C_AXIS_TKEEP_WIDTH-1:0]     m_axis_tkeep,\n    output                              m_axis_tlast,\n    output [C_AXIS_TID_WIDTH-1:0]       m_axis_tid,\n    output [C_AXIS_TDEST_WIDTH-1:0]     m_axis_tdest,\n    output [C_AXIS_TUSER_WIDTH-1:0]     m_axis_tuser,\n    \n           \n    \n    \n    // AXI Full/Lite Write Address Channel signals\n    input                               axi_aw_injectsbiterr,\n    input                               axi_aw_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_rd_data_count,\n    output                              axi_aw_sbiterr,\n    output                              axi_aw_dbiterr,\n    output                              axi_aw_overflow,\n    output                              axi_aw_underflow,\n    output                              axi_aw_prog_full,\n    output                              axi_aw_prog_empty,\n    \n    \n    // AXI Full/Lite Write Data Channel signals\n    input                               axi_w_injectsbiterr,\n    input                               axi_w_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_rd_data_count,\n    output                              axi_w_sbiterr,\n    output                              axi_w_dbiterr,\n    output                              axi_w_overflow,\n    output                              axi_w_underflow,\n    output                              axi_w_prog_full,\n    output                              axi_w_prog_empty,\n    \n    \n    // AXI Full/Lite Write Response Channel signals\n    input                               axi_b_injectsbiterr,\n    input                               axi_b_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_rd_data_count,\n    output                              axi_b_sbiterr,\n    output                              axi_b_dbiterr,\n    output                              axi_b_overflow,\n    output                              axi_b_underflow,\n    output                              axi_b_prog_full,\n    output                              axi_b_prog_empty,\n    \n    \n    \n    // AXI Full/Lite Read Address Channel signals\n    input                               axi_ar_injectsbiterr,\n    input                               axi_ar_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_rd_data_count,\n    output                              axi_ar_sbiterr,\n    output                              axi_ar_dbiterr,\n    output                              axi_ar_overflow,\n    output                              axi_ar_underflow,\n    output                              axi_ar_prog_full,\n    output                              axi_ar_prog_empty,\n\n    \n    // AXI Full/Lite Read Data Channel Signals\n    input                               axi_r_injectsbiterr,\n    input                               axi_r_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_rd_data_count,\n    output                              axi_r_sbiterr,\n    output                              axi_r_dbiterr,\n    output                              axi_r_overflow,\n    output                              axi_r_underflow,\n    output                              axi_r_prog_full,\n    output                              axi_r_prog_empty,\n\n    \n    // AXI Streaming FIFO Related Signals\n    input                               axis_injectsbiterr,\n    input                               axis_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_wr_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_rd_data_count,\n    output                              axis_sbiterr,\n    output                              axis_dbiterr,\n    output                              axis_overflow,\n    output                              axis_underflow,\n    output                              axis_prog_full,\n    output                              axis_prog_empty\n\n    );\n\n    wire                              BACKUP;\n    wire                              BACKUP_MARKER;\n    wire                              CLK;\n    wire                              RST;\n    wire                              SRST;\n    wire                              WR_CLK;\n    wire                              WR_RST;\n    wire                              RD_CLK;\n    wire                              RD_RST;\n    wire [C_DIN_WIDTH-1:0]            DIN;\n    wire                              WR_EN;\n    wire                              RD_EN;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_ASSERT;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_NEGATE;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_ASSERT;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_NEGATE;\n    wire                              INT_CLK;\n    wire                              INJECTDBITERR;\n    wire                              INJECTSBITERR;\n    wire                              SLEEP;\n    wire [C_DOUT_WIDTH-1:0]           DOUT;\n    wire                              FULL;\n    wire                              ALMOST_FULL;\n    wire                              WR_ACK;\n    wire                              OVERFLOW;\n    wire                              EMPTY;\n    wire                              ALMOST_EMPTY;\n    wire                              VALID;\n    wire                              UNDERFLOW;\n    wire [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT;\n    wire [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT;\n    wire                              PROG_FULL;\n    wire                              PROG_EMPTY;\n    wire                              SBITERR;\n    wire                              DBITERR;\n    wire                              WR_RST_BUSY;\n    wire                              RD_RST_BUSY;\n    wire                              M_ACLK;\n    wire                              S_ACLK;\n    wire                              S_ARESETN;\n    wire                              S_ACLK_EN;\n    wire                              M_ACLK_EN;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_AWLEN;\n    wire [3-1:0]                      S_AXI_AWSIZE;\n    wire [2-1:0]                      S_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_AWLOCK;\n    wire [4-1:0]                      S_AXI_AWCACHE;\n    wire [3-1:0]                      S_AXI_AWPROT;\n    wire [4-1:0]                      S_AXI_AWQOS;\n    wire [4-1:0]                      S_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     S_AXI_AWUSER;\n    wire                              S_AXI_AWVALID;\n    wire                              S_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     S_AXI_WSTRB;\n    wire                              S_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      S_AXI_WUSER;\n    wire                              S_AXI_WVALID;\n    wire                              S_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_BID;\n    wire [2-1:0]                      S_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      S_AXI_BUSER;\n    wire                              S_AXI_BVALID;\n    wire                              S_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_AWLEN;\n    wire [3-1:0]                      M_AXI_AWSIZE;\n    wire [2-1:0]                      M_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_AWLOCK;\n    wire [4-1:0]                      M_AXI_AWCACHE;\n    wire [3-1:0]                      M_AXI_AWPROT;\n    wire [4-1:0]                      M_AXI_AWQOS;\n    wire [4-1:0]                      M_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     M_AXI_AWUSER;\n    wire                              M_AXI_AWVALID;\n    wire                              M_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     M_AXI_WSTRB;\n    wire                              M_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      M_AXI_WUSER;\n    wire                              M_AXI_WVALID;\n    wire                              M_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_BID;\n    wire [2-1:0]                      M_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      M_AXI_BUSER;\n    wire                              M_AXI_BVALID;\n    wire                              M_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_ARID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_ARADDR; \n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_ARLEN;\n    wire [3-1:0]                      S_AXI_ARSIZE;\n    wire [2-1:0]                      S_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_ARLOCK;\n    wire [4-1:0]                      S_AXI_ARCACHE;\n    wire [3-1:0]                      S_AXI_ARPROT;\n    wire [4-1:0]                      S_AXI_ARQOS;\n    wire [4-1:0]                      S_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     S_AXI_ARUSER;\n    wire                              S_AXI_ARVALID;\n    wire                              S_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_RID;       \n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_RDATA; \n    wire [2-1:0]                      S_AXI_RRESP;\n    wire                              S_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      S_AXI_RUSER;\n    wire                              S_AXI_RVALID;\n    wire                              S_AXI_RREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_ARID;        \n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_ARADDR;  \n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_ARLEN;\n    wire [3-1:0]                      M_AXI_ARSIZE;\n    wire [2-1:0]                      M_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_ARLOCK;\n    wire [4-1:0]                      M_AXI_ARCACHE;\n    wire [3-1:0]                      M_AXI_ARPROT;\n    wire [4-1:0]                      M_AXI_ARQOS;\n    wire [4-1:0]                      M_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     M_AXI_ARUSER;\n    wire                              M_AXI_ARVALID;\n    wire                              M_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_RID;        \n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_RDATA;  \n    wire [2-1:0]                      M_AXI_RRESP;\n    wire                              M_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      M_AXI_RUSER;\n    wire                              M_AXI_RVALID;\n    wire                              M_AXI_RREADY;\n    wire                              S_AXIS_TVALID;\n    wire                              S_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     S_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     S_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     S_AXIS_TKEEP;\n    wire                              S_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       S_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     S_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     S_AXIS_TUSER;\n    wire                              M_AXIS_TVALID;\n    wire                              M_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     M_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     M_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     M_AXIS_TKEEP;\n    wire                              M_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       M_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     M_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     M_AXIS_TUSER;\n    wire                              AXI_AW_INJECTSBITERR;\n    wire                              AXI_AW_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_RD_DATA_COUNT;\n    wire                              AXI_AW_SBITERR;\n    wire                              AXI_AW_DBITERR;\n    wire                              AXI_AW_OVERFLOW;\n    wire                              AXI_AW_UNDERFLOW;\n    wire                              AXI_AW_PROG_FULL;\n    wire                              AXI_AW_PROG_EMPTY;\n    wire                              AXI_W_INJECTSBITERR;\n    wire                              AXI_W_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_RD_DATA_COUNT;\n    wire                              AXI_W_SBITERR;\n    wire                              AXI_W_DBITERR;\n    wire                              AXI_W_OVERFLOW;\n    wire                              AXI_W_UNDERFLOW;\n    wire                              AXI_W_PROG_FULL;\n    wire                              AXI_W_PROG_EMPTY;\n    wire                              AXI_B_INJECTSBITERR;\n    wire                              AXI_B_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_RD_DATA_COUNT;\n    wire                              AXI_B_SBITERR;\n    wire                              AXI_B_DBITERR;\n    wire                              AXI_B_OVERFLOW;\n    wire                              AXI_B_UNDERFLOW;\n    wire                              AXI_B_PROG_FULL;\n    wire                              AXI_B_PROG_EMPTY;\n    wire                              AXI_AR_INJECTSBITERR;\n    wire                              AXI_AR_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_RD_DATA_COUNT;\n    wire                              AXI_AR_SBITERR;\n    wire                              AXI_AR_DBITERR;\n    wire                              AXI_AR_OVERFLOW;\n    wire                              AXI_AR_UNDERFLOW;\n    wire                              AXI_AR_PROG_FULL;\n    wire                              AXI_AR_PROG_EMPTY;\n    wire                              AXI_R_INJECTSBITERR;\n    wire                              AXI_R_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_RD_DATA_COUNT;\n    wire                              AXI_R_SBITERR;\n    wire                              AXI_R_DBITERR;\n    wire                              AXI_R_OVERFLOW;\n    wire                              AXI_R_UNDERFLOW;\n    wire                              AXI_R_PROG_FULL;\n    wire                              AXI_R_PROG_EMPTY;\n    wire                              AXIS_INJECTSBITERR;\n    wire                              AXIS_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_RD_DATA_COUNT;\n    wire                              AXIS_SBITERR;\n    wire                              AXIS_DBITERR;\n    wire                              AXIS_OVERFLOW;\n    wire                              AXIS_UNDERFLOW;\n    wire                              AXIS_PROG_FULL;\n    wire                              AXIS_PROG_EMPTY;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count_in;\n    wire                              wr_rst_int;\n    wire                              rd_rst_int;\n    wire                              wr_rst_busy_o;\n    wire                              wr_rst_busy_ntve;\n    wire                              wr_rst_busy_axis;\n    wire                              wr_rst_busy_wach;\n    wire                              wr_rst_busy_wdch;\n    wire                              wr_rst_busy_wrch;\n    wire                              wr_rst_busy_rach;\n    wire                              wr_rst_busy_rdch;\n\n\n\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n\n\n\n    // Conventional FIFO Interface Signals\n    assign BACKUP                 = backup;\n    assign BACKUP_MARKER          = backup_marker;\n    assign CLK                    = clk;\n    assign RST                    = rst;\n    assign SRST                   = srst;\n    assign WR_CLK                 = wr_clk;\n    assign WR_RST                 = wr_rst;\n    assign RD_CLK                 = rd_clk;\n    assign RD_RST                 = rd_rst;\n    assign WR_EN                  = wr_en;\n    assign RD_EN                  = rd_en;\n    assign INT_CLK                = int_clk;\n    assign INJECTDBITERR          = injectdbiterr;\n    assign INJECTSBITERR          = injectsbiterr;\n    assign SLEEP                  = sleep;\n    assign full                   = FULL;\n    assign almost_full            = ALMOST_FULL;\n    assign wr_ack                 = WR_ACK;\n    assign overflow               = OVERFLOW;\n    assign empty                  = EMPTY;\n    assign almost_empty           = ALMOST_EMPTY;\n    assign valid                  = VALID;\n    assign underflow              = UNDERFLOW;\n    assign prog_full              = PROG_FULL;\n    assign prog_empty             = PROG_EMPTY;\n    assign sbiterr                = SBITERR;\n    assign dbiterr                = DBITERR;\n//    assign wr_rst_busy            = WR_RST_BUSY | wr_rst_busy_o;\n    assign wr_rst_busy            = wr_rst_busy_o;\n    assign rd_rst_busy            = RD_RST_BUSY;\n    assign M_ACLK                 = m_aclk;\n    assign S_ACLK                 = s_aclk;\n    assign S_ARESETN              = s_aresetn;\n    assign S_ACLK_EN              = s_aclk_en;\n    assign M_ACLK_EN              = m_aclk_en;\n    assign S_AXI_AWVALID          = s_axi_awvalid;\n    assign s_axi_awready          = S_AXI_AWREADY;\n    assign S_AXI_WLAST            = s_axi_wlast;\n    assign S_AXI_WVALID           = s_axi_wvalid;\n    assign s_axi_wready           = S_AXI_WREADY;\n    assign s_axi_bvalid           = S_AXI_BVALID;\n    assign S_AXI_BREADY           = s_axi_bready;\n    assign m_axi_awvalid          = M_AXI_AWVALID;\n    assign M_AXI_AWREADY          = m_axi_awready;\n    assign m_axi_wlast            = M_AXI_WLAST;\n    assign m_axi_wvalid           = M_AXI_WVALID;\n    assign M_AXI_WREADY           = m_axi_wready;\n    assign M_AXI_BVALID           = m_axi_bvalid;\n    assign m_axi_bready           = M_AXI_BREADY;\n    assign S_AXI_ARVALID          = s_axi_arvalid;\n    assign s_axi_arready          = S_AXI_ARREADY;\n    assign s_axi_rlast            = S_AXI_RLAST;\n    assign s_axi_rvalid           = S_AXI_RVALID;\n    assign S_AXI_RREADY           = s_axi_rready;\n    assign m_axi_arvalid          = M_AXI_ARVALID;\n    assign M_AXI_ARREADY          = m_axi_arready;\n    assign M_AXI_RLAST            = m_axi_rlast;\n    assign M_AXI_RVALID           = m_axi_rvalid;\n    assign m_axi_rready           = M_AXI_RREADY;\n    assign S_AXIS_TVALID          = s_axis_tvalid;\n    assign s_axis_tready          = S_AXIS_TREADY;\n    assign S_AXIS_TLAST           = s_axis_tlast;\n    assign m_axis_tvalid          = M_AXIS_TVALID;\n    assign M_AXIS_TREADY          = m_axis_tready;\n    assign m_axis_tlast           = M_AXIS_TLAST;\n    assign AXI_AW_INJECTSBITERR   = axi_aw_injectsbiterr;\n    assign AXI_AW_INJECTDBITERR   = axi_aw_injectdbiterr;\n    assign axi_aw_sbiterr         = AXI_AW_SBITERR;\n    assign axi_aw_dbiterr         = AXI_AW_DBITERR;\n    assign axi_aw_overflow        = AXI_AW_OVERFLOW;\n    assign axi_aw_underflow       = AXI_AW_UNDERFLOW;\n    assign axi_aw_prog_full       = AXI_AW_PROG_FULL;\n    assign axi_aw_prog_empty      = AXI_AW_PROG_EMPTY;\n    assign AXI_W_INJECTSBITERR    = axi_w_injectsbiterr;\n    assign AXI_W_INJECTDBITERR    = axi_w_injectdbiterr;\n    assign axi_w_sbiterr          = AXI_W_SBITERR;\n    assign axi_w_dbiterr          = AXI_W_DBITERR;\n    assign axi_w_overflow         = AXI_W_OVERFLOW;\n    assign axi_w_underflow        = AXI_W_UNDERFLOW;\n    assign axi_w_prog_full        = AXI_W_PROG_FULL;\n    assign axi_w_prog_empty       = AXI_W_PROG_EMPTY;\n    assign AXI_B_INJECTSBITERR    = axi_b_injectsbiterr;\n    assign AXI_B_INJECTDBITERR    = axi_b_injectdbiterr;\n    assign axi_b_sbiterr          = AXI_B_SBITERR;\n    assign axi_b_dbiterr          = AXI_B_DBITERR;\n    assign axi_b_overflow         = AXI_B_OVERFLOW;\n    assign axi_b_underflow        = AXI_B_UNDERFLOW;\n    assign axi_b_prog_full        = AXI_B_PROG_FULL;\n    assign axi_b_prog_empty       = AXI_B_PROG_EMPTY;\n    assign AXI_AR_INJECTSBITERR   = axi_ar_injectsbiterr;\n    assign AXI_AR_INJECTDBITERR   = axi_ar_injectdbiterr;\n    assign axi_ar_sbiterr         = AXI_AR_SBITERR;\n    assign axi_ar_dbiterr         = AXI_AR_DBITERR;\n    assign axi_ar_overflow        = AXI_AR_OVERFLOW;\n    assign axi_ar_underflow       = AXI_AR_UNDERFLOW;\n    assign axi_ar_prog_full       = AXI_AR_PROG_FULL;\n    assign axi_ar_prog_empty      = AXI_AR_PROG_EMPTY;\n    assign AXI_R_INJECTSBITERR    = axi_r_injectsbiterr;\n    assign AXI_R_INJECTDBITERR    = axi_r_injectdbiterr;\n    assign axi_r_sbiterr          = AXI_R_SBITERR;\n    assign axi_r_dbiterr          = AXI_R_DBITERR;\n    assign axi_r_overflow         = AXI_R_OVERFLOW;\n    assign axi_r_underflow        = AXI_R_UNDERFLOW;\n    assign axi_r_prog_full        = AXI_R_PROG_FULL;\n    assign axi_r_prog_empty       = AXI_R_PROG_EMPTY;\n    assign AXIS_INJECTSBITERR     = axis_injectsbiterr;\n    assign AXIS_INJECTDBITERR     = axis_injectdbiterr;\n    assign axis_sbiterr           = AXIS_SBITERR;\n    assign axis_dbiterr           = AXIS_DBITERR;\n    assign axis_overflow          = AXIS_OVERFLOW;\n    assign axis_underflow         = AXIS_UNDERFLOW;\n    assign axis_prog_full         = AXIS_PROG_FULL;\n    assign axis_prog_empty        = AXIS_PROG_EMPTY;\n\n\n    assign DIN                       = din;\n    assign PROG_EMPTY_THRESH         = prog_empty_thresh;\n    assign PROG_EMPTY_THRESH_ASSERT  = prog_empty_thresh_assert;\n    assign PROG_EMPTY_THRESH_NEGATE  = prog_empty_thresh_negate;\n    assign PROG_FULL_THRESH          = prog_full_thresh;\n    assign PROG_FULL_THRESH_ASSERT   = prog_full_thresh_assert;\n    assign PROG_FULL_THRESH_NEGATE   = prog_full_thresh_negate;\n    assign dout                      = DOUT;\n    assign data_count                = DATA_COUNT;\n    assign rd_data_count             = RD_DATA_COUNT;\n    assign wr_data_count             = WR_DATA_COUNT;\n    assign S_AXI_AWID                = s_axi_awid;\n    assign S_AXI_AWADDR              = s_axi_awaddr;\n    assign S_AXI_AWLEN               = s_axi_awlen;\n    assign S_AXI_AWSIZE              = s_axi_awsize;\n    assign S_AXI_AWBURST             = s_axi_awburst;\n    assign S_AXI_AWLOCK              = s_axi_awlock;\n    assign S_AXI_AWCACHE             = s_axi_awcache;\n    assign S_AXI_AWPROT              = s_axi_awprot;\n    assign S_AXI_AWQOS               = s_axi_awqos;\n    assign S_AXI_AWREGION            = s_axi_awregion;\n    assign S_AXI_AWUSER              = s_axi_awuser;\n    assign S_AXI_WID                 = s_axi_wid;\n    assign S_AXI_WDATA               = s_axi_wdata;\n    assign S_AXI_WSTRB               = s_axi_wstrb;\n    assign S_AXI_WUSER               = s_axi_wuser;\n    assign s_axi_bid                 = S_AXI_BID;\n    assign s_axi_bresp               = S_AXI_BRESP;\n    assign s_axi_buser               = S_AXI_BUSER;\n    assign m_axi_awid                = M_AXI_AWID;\n    assign m_axi_awaddr              = M_AXI_AWADDR;\n    assign m_axi_awlen               = M_AXI_AWLEN;\n    assign m_axi_awsize              = M_AXI_AWSIZE;\n    assign m_axi_awburst             = M_AXI_AWBURST;\n    assign m_axi_awlock              = M_AXI_AWLOCK;\n    assign m_axi_awcache             = M_AXI_AWCACHE;\n    assign m_axi_awprot              = M_AXI_AWPROT;\n    assign m_axi_awqos               = M_AXI_AWQOS;\n    assign m_axi_awregion            = M_AXI_AWREGION;\n    assign m_axi_awuser              = M_AXI_AWUSER;\n    assign m_axi_wid                 = M_AXI_WID;\n    assign m_axi_wdata               = M_AXI_WDATA;\n    assign m_axi_wstrb               = M_AXI_WSTRB;\n    assign m_axi_wuser               = M_AXI_WUSER;\n    assign M_AXI_BID                 = m_axi_bid;\n    assign M_AXI_BRESP               = m_axi_bresp;\n    assign M_AXI_BUSER               = m_axi_buser;\n    assign S_AXI_ARID                = s_axi_arid;\n    assign S_AXI_ARADDR              = s_axi_araddr; \n    assign S_AXI_ARLEN               = s_axi_arlen;\n    assign S_AXI_ARSIZE              = s_axi_arsize;\n    assign S_AXI_ARBURST             = s_axi_arburst;\n    assign S_AXI_ARLOCK              = s_axi_arlock;\n    assign S_AXI_ARCACHE             = s_axi_arcache;\n    assign S_AXI_ARPROT              = s_axi_arprot;\n    assign S_AXI_ARQOS               = s_axi_arqos;\n    assign S_AXI_ARREGION            = s_axi_arregion;\n    assign S_AXI_ARUSER              = s_axi_aruser;\n    assign s_axi_rid                 = S_AXI_RID;\n    assign s_axi_rdata               = S_AXI_RDATA;\n    assign s_axi_rresp               = S_AXI_RRESP;\n    assign s_axi_ruser               = S_AXI_RUSER;\n    assign m_axi_arid                = M_AXI_ARID;        \n    assign m_axi_araddr              = M_AXI_ARADDR;  \n    assign m_axi_arlen               = M_AXI_ARLEN;\n    assign m_axi_arsize              = M_AXI_ARSIZE;\n    assign m_axi_arburst             = M_AXI_ARBURST;\n    assign m_axi_arlock              = M_AXI_ARLOCK;\n    assign m_axi_arcache             = M_AXI_ARCACHE;\n    assign m_axi_arprot              = M_AXI_ARPROT;\n    assign m_axi_arqos               = M_AXI_ARQOS;\n    assign m_axi_arregion            = M_AXI_ARREGION;\n    assign m_axi_aruser              = M_AXI_ARUSER;\n    assign M_AXI_RID                 = m_axi_rid;        \n    assign M_AXI_RDATA               = m_axi_rdata;  \n    assign M_AXI_RRESP               = m_axi_rresp;\n    assign M_AXI_RUSER               = m_axi_ruser;\n    assign S_AXIS_TDATA              = s_axis_tdata;\n    assign S_AXIS_TSTRB              = s_axis_tstrb;\n    assign S_AXIS_TKEEP              = s_axis_tkeep;\n    assign S_AXIS_TID                = s_axis_tid;\n    assign S_AXIS_TDEST              = s_axis_tdest;\n    assign S_AXIS_TUSER              = s_axis_tuser;\n    assign m_axis_tdata              = M_AXIS_TDATA;\n    assign m_axis_tstrb              = M_AXIS_TSTRB;\n    assign m_axis_tkeep              = M_AXIS_TKEEP;\n    assign m_axis_tid                = M_AXIS_TID;\n    assign m_axis_tdest              = M_AXIS_TDEST;\n    assign m_axis_tuser              = M_AXIS_TUSER;\n    assign AXI_AW_PROG_FULL_THRESH   = axi_aw_prog_full_thresh;\n    assign AXI_AW_PROG_EMPTY_THRESH  = axi_aw_prog_empty_thresh;\n    assign axi_aw_data_count         = AXI_AW_DATA_COUNT;\n    assign axi_aw_wr_data_count      = AXI_AW_WR_DATA_COUNT;\n    assign axi_aw_rd_data_count      = AXI_AW_RD_DATA_COUNT;\n    assign AXI_W_PROG_FULL_THRESH    = axi_w_prog_full_thresh;\n    assign AXI_W_PROG_EMPTY_THRESH   = axi_w_prog_empty_thresh;\n    assign axi_w_data_count          = AXI_W_DATA_COUNT;\n    assign axi_w_wr_data_count       = AXI_W_WR_DATA_COUNT;\n    assign axi_w_rd_data_count       = AXI_W_RD_DATA_COUNT;\n    assign AXI_B_PROG_FULL_THRESH    = axi_b_prog_full_thresh;\n    assign AXI_B_PROG_EMPTY_THRESH   = axi_b_prog_empty_thresh;\n    assign axi_b_data_count          = AXI_B_DATA_COUNT;\n    assign axi_b_wr_data_count       = AXI_B_WR_DATA_COUNT;\n    assign axi_b_rd_data_count       = AXI_B_RD_DATA_COUNT;\n    assign AXI_AR_PROG_FULL_THRESH   = axi_ar_prog_full_thresh;\n    assign AXI_AR_PROG_EMPTY_THRESH  = axi_ar_prog_empty_thresh;\n    assign axi_ar_data_count         = AXI_AR_DATA_COUNT;\n    assign axi_ar_wr_data_count      = AXI_AR_WR_DATA_COUNT;\n    assign axi_ar_rd_data_count      = AXI_AR_RD_DATA_COUNT;\n    assign AXI_R_PROG_FULL_THRESH    = axi_r_prog_full_thresh;\n    assign AXI_R_PROG_EMPTY_THRESH   = axi_r_prog_empty_thresh;\n    assign axi_r_data_count          = AXI_R_DATA_COUNT;\n    assign axi_r_wr_data_count       = AXI_R_WR_DATA_COUNT;\n    assign axi_r_rd_data_count       = AXI_R_RD_DATA_COUNT;\n    assign AXIS_PROG_FULL_THRESH     = axis_prog_full_thresh;\n    assign AXIS_PROG_EMPTY_THRESH    = axis_prog_empty_thresh;\n    assign axis_data_count           = AXIS_DATA_COUNT;\n    assign axis_wr_data_count        = AXIS_WR_DATA_COUNT;\n    assign axis_rd_data_count        = AXIS_RD_DATA_COUNT;\n\n\n  generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_COMMON_CLOCK \t\t(C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DATA_COUNT_WIDTH\t\t(C_DATA_COUNT_WIDTH),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH),\n        .C_DOUT_RST_VAL\t\t\t(C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),\n        .C_DOUT_WIDTH\t\t\t(C_DOUT_WIDTH),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n        .C_HAS_ALMOST_EMPTY\t\t(C_HAS_ALMOST_EMPTY),\n        .C_HAS_ALMOST_FULL\t\t(C_HAS_ALMOST_FULL),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_DATA_COUNT\t\t(C_HAS_DATA_COUNT),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_HAS_RD_DATA_COUNT\t\t(C_HAS_RD_DATA_COUNT),\n        .C_HAS_RD_RST\t\t\t(C_HAS_RD_RST),\n        .C_HAS_RST\t\t\t(C_HAS_RST),\n        .C_HAS_SRST\t\t\t(C_HAS_SRST),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_HAS_VALID\t\t\t(C_HAS_VALID),\n        .C_HAS_WR_ACK\t\t\t(C_HAS_WR_ACK),\n        .C_HAS_WR_DATA_COUNT\t\t(C_HAS_WR_DATA_COUNT),\n        .C_HAS_WR_RST\t\t\t(C_HAS_WR_RST),\n        .C_IMPLEMENTATION_TYPE\t\t(C_IMPLEMENTATION_TYPE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_MEMORY_TYPE\t\t\t(C_MEMORY_TYPE),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n        .C_PRELOAD_LATENCY\t\t(C_PRELOAD_LATENCY),\n        .C_PRELOAD_REGS\t\t\t(C_PRELOAD_REGS),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL),\n        .C_PROG_EMPTY_THRESH_NEGATE_VAL\t(C_PROG_EMPTY_THRESH_NEGATE_VAL),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL),\n        .C_PROG_FULL_THRESH_NEGATE_VAL\t(C_PROG_FULL_THRESH_NEGATE_VAL),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_RD_DATA_COUNT_WIDTH),\n        .C_RD_DEPTH\t\t\t(C_RD_DEPTH),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_RD_PNTR_WIDTH\t\t(C_RD_PNTR_WIDTH),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n        .C_USE_ECC                      (C_USE_ECC),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_EN_SAFETY_CKT\t\t(C_EN_SAFETY_CKT),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_USE_FWFT_DATA_COUNT\t\t(C_USE_FWFT_DATA_COUNT),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_DATA_COUNT_WIDTH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (C_ENABLE_RST_SYNC),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE),\n        .C_AXI_TYPE                     (C_AXI_TYPE),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE)\n      )\n    fifo_generator_v13_2_5_conv_dut\n      (\n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .CLK                      (CLK),\n        .RST                      (RST),\n        .SRST                     (SRST),\n        .WR_CLK                   (WR_CLK),\n        .WR_RST                   (WR_RST),\n        .RD_CLK                   (RD_CLK),\n        .RD_RST                   (RD_RST),\n        .DIN                      (DIN),\n        .WR_EN                    (WR_EN),\n        .RD_EN                    (RD_EN),\n        .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),\n        .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),\n        .PROG_FULL_THRESH         (PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),\n        .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),\n        .INT_CLK                  (INT_CLK),\n        .INJECTDBITERR            (INJECTDBITERR), \n        .INJECTSBITERR            (INJECTSBITERR),\n  \n        .DOUT                     (DOUT),\n        .FULL                     (FULL),\n        .ALMOST_FULL              (ALMOST_FULL),\n        .WR_ACK                   (WR_ACK),\n        .OVERFLOW                 (OVERFLOW),\n        .EMPTY                    (EMPTY),\n        .ALMOST_EMPTY             (ALMOST_EMPTY),\n        .VALID                    (VALID),\n        .UNDERFLOW                (UNDERFLOW),\n        .DATA_COUNT               (DATA_COUNT),\n        .RD_DATA_COUNT            (RD_DATA_COUNT),\n        .WR_DATA_COUNT            (wr_data_count_in),\n        .PROG_FULL                (PROG_FULL),\n        .PROG_EMPTY               (PROG_EMPTY),\n        .SBITERR                  (SBITERR),\n        .DBITERR                  (DBITERR),\n        .wr_rst_busy_o            (wr_rst_busy_o),\n        .wr_rst_busy              (wr_rst_busy_i),\n        .rd_rst_busy              (rd_rst_busy),\n        .wr_rst_i_out             (wr_rst_int),\n        .rd_rst_i_out             (rd_rst_int)\n       );\n  end endgenerate\n\n\n\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n  localparam C_AXI_SIZE_WIDTH   = 3;\n  localparam C_AXI_BURST_WIDTH  = 2;\n  localparam C_AXI_CACHE_WIDTH  = 4;\n  localparam C_AXI_PROT_WIDTH   = 3;\n  localparam C_AXI_QOS_WIDTH    = 4;\n  localparam C_AXI_REGION_WIDTH = 4;\n  localparam C_AXI_BRESP_WIDTH  = 2;\n  localparam C_AXI_RRESP_WIDTH  = 2;\n\n  localparam IS_AXI_STREAMING  = C_INTERFACE_TYPE == 1 ? 1 : 0;\n  localparam TDATA_OFFSET      = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;\n  localparam TSTRB_OFFSET      = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;\n  localparam TKEEP_OFFSET      = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;\n  localparam TID_OFFSET        = C_HAS_AXIS_TID   == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;\n  localparam TDEST_OFFSET      = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;\n  localparam TUSER_OFFSET      = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;\n  localparam LOG_DEPTH_AXIS    = find_log2(C_WR_DEPTH_AXIS); \n  localparam LOG_WR_DEPTH      = find_log2(C_WR_DEPTH); \n\n\n  function [LOG_DEPTH_AXIS-1:0] bin2gray;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      begin\n         bin2gray = x ^ (x>>1);\n      end\n   endfunction\n\n  function [LOG_DEPTH_AXIS-1:0] gray2bin;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      integer                i;\n      begin\n         gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];\n         for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin\n            gray2bin[i] =  gray2bin[i+1] ^ x[i];\n         end\n      end\n   endfunction\n\nwire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;\nwire  [LOG_WR_DEPTH-1 : 0]  w_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;\nreg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;\nwire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;\nwire [LOG_WR_DEPTH : 0] r_inv_pad;\nwire [LOG_WR_DEPTH-1 : 0] d_cnt;\nreg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;\nreg adj_w_cnt_rd_pad_0 = 0;\nreg r_inv_pad_0 = 0;\n\n\n   genvar l;\n\n   generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (LOG_WR_DEPTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_int), \n         .CLK      (RD_CLK), \n         .DIN      (w_q[l-1]), \n         .DOUT     (w_q[l])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter\n    assign wr_eop_ad = WR_EN & !(FULL);\n    assign rd_eop_ad = RD_EN & !(EMPTY);\n\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt    <= 1'b0;\n      else if (wr_eop_ad)\n        w_cnt    <= w_cnt + 1;\n    end\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt_gc    <= 1'b0;\n      else \n        w_cnt_gc    <= bin2gray(w_cnt);\n    end\n\n\n    assign  w_q[0]  = w_cnt_gc;\n    assign  w_cnt_gc_asreg_last       = w_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        w_cnt_rd    <= 1'b0;\n      else \n        w_cnt_rd    <= gray2bin(w_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        r_cnt    <= 1'b0;\n      else if (rd_eop_ad)\n        r_cnt    <= r_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;\n   assign r_inv_pad[LOG_WR_DEPTH : 1]        = ~r_cnt;\n   assign adj_w_cnt_rd_pad[0]                = adj_w_cnt_rd_pad_0;\n   assign r_inv_pad[0]                       = r_inv_pad_0;\n\n\n  always @ ( rd_eop_ad )\n    begin\n      if (!rd_eop_ad) begin\n        adj_w_cnt_rd_pad_0    <= 1'b1;\n        r_inv_pad_0           <= 1'b1;\n      end else begin \n        adj_w_cnt_rd_pad_0    <= 1'b0;\n        r_inv_pad_0           <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        d_cnt_pad    <= 1'b0;\n      else \n        d_cnt_pad    <= adj_w_cnt_rd_pad + r_inv_pad ;\n    end\n\n   assign  d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;\n   assign  WR_DATA_COUNT = d_cnt;\n\n  end endgenerate // fifo_ic_adapter\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter\n   assign  WR_DATA_COUNT = wr_data_count_in;\n\n  end endgenerate // fifo_icn_adapter\n\n\n\n  wire                          inverted_reset = ~S_ARESETN;\n  wire                          axi_rs_rst;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_din          ;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_dout         ;\n  wire                          axis_full         ;\n  wire                          axis_almost_full  ;\n  wire                          axis_empty        ;\n  wire                          axis_s_axis_tready;\n  wire                          axis_m_axis_tvalid;\n  wire                          axis_wr_en        ;\n  wire                          axis_rd_en        ;\n  wire                          axis_we           ;\n  wire                          axis_re           ;\n  wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;\n  reg                           axis_pkt_read = 1'b0;\n  wire                          axis_rd_rst;\n  wire                          axis_wr_rst;\n\n  generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||\n               C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst\n      reg                           rst_d1 = 0        ;\n      reg                           rst_d2 = 0        ;\n      reg [3:0]                    axi_rst = 4'h0     ;\n      always @ (posedge inverted_reset or posedge S_ACLK) begin\n        if (inverted_reset) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          axi_rst        <= 4'hf;\n        end else begin\n          rst_d1         <= #`TCQ 1'b0;\n          rst_d2         <= #`TCQ rst_d1;\n          axi_rst        <= #`TCQ {axi_rst[2:0],1'b0};\n        end\n      end\n\n      assign axi_rs_rst = axi_rst[3];//rst_d2;\n  end endgenerate // gaxi_rs_rst\n\n  generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming\n\n    // Write protection when almost full or prog_full is high\n    assign axis_we    = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : \n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign axis_re    = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :\n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? axis_we & S_ACLK_EN : axis_we;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE               (C_INTERFACE_TYPE),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 2  || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_AXIS),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_AXIS),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),\n        .C_USE_ECC                      (C_USE_ECC_AXIS),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_AXIS),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_axis_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (axis_wr_en),\n        .RD_EN                    (axis_rd_en),\n        .PROG_FULL_THRESH         (AXIS_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXIS_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .INJECTDBITERR            (AXIS_INJECTDBITERR), \n        .INJECTSBITERR            (AXIS_INJECTSBITERR),\n  \n        .DIN                      (axis_din),\n        .DOUT                     (axis_dout),\n        .FULL                     (axis_full),\n        .EMPTY                    (axis_empty),\n        .ALMOST_FULL              (axis_almost_full),\n        .PROG_FULL                (AXIS_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXIS_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (AXIS_OVERFLOW),\n        .VALID                    (),\n        .UNDERFLOW                (AXIS_UNDERFLOW),\n        .DATA_COUNT               (axis_dc),\n        .RD_DATA_COUNT            (AXIS_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXIS_WR_DATA_COUNT),\n        .SBITERR                  (AXIS_SBITERR),\n        .DBITERR                  (AXIS_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_axis),\n        .rd_rst_busy              (rd_rst_busy_axis),\n        .wr_rst_i_out             (axis_wr_rst),\n        .rd_rst_i_out             (axis_rd_rst),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign axis_s_axis_tready    = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;\n    assign axis_m_axis_tvalid    = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;\n    assign S_AXIS_TREADY         = axis_s_axis_tready;\n    assign M_AXIS_TVALID         = axis_m_axis_tvalid;\n\n  end endgenerate // axi_streaming\n\n  wire axis_wr_eop;\n  reg  axis_wr_eop_d1 = 1'b0;\n  wire axis_rd_eop;\n  integer  axis_pkt_cnt;\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)\n        axis_pkt_read    <= 1'b0;\n      else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_wr_eop_d1    <= 1'b0;\n      else\n        axis_wr_eop_d1   <= axis_wr_eop;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_cnt    <= 0;\n      else if (axis_wr_eop_d1 && ~axis_rd_eop)\n        axis_pkt_cnt    <= axis_pkt_cnt + 1;\n      else if (axis_rd_eop && ~axis_wr_eop_d1)\n        axis_pkt_cnt    <= axis_pkt_cnt - 1;\n    end\n  end endgenerate // gaxis_pkt_fifo_cc\n\n\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;\nwire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;\nwire axis_rd_has_rst;\nwire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;\nwire  [LOG_DEPTH_AXIS-1 : 0]  wpkt_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;\nwire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;\nwire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;\nwire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;\nwire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;\nreg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;\nreg adj_axis_wpkt_cnt_rd_pad_0 = 0;\nreg rpkt_inv_pad_0 = 0;\nwire axis_af_rd ;\n\ngenerate if (C_HAS_RST == 1) begin : rst_blk_has\n  assign axis_rd_has_rst = axis_rd_rst;\nend endgenerate //rst_blk_has\n\ngenerate if (C_HAS_RST == 0) begin :rst_blk_no\n  assign axis_rd_has_rst = 1'b0;\nend endgenerate //rst_blk_no\n\n   genvar i;\n\n   generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (LOG_DEPTH_AXIS)\n        )\n     rd_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (wpkt_q[i-1]), \n         .DOUT     (wpkt_q[i])\n        );\n \n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (1)\n        )\n     wr_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (axis_af_q[i-1]), \n         .DOUT     (axis_af_q[i])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (diff_pkt_cnt == 1))\n        axis_pkt_read    <= 1'b0;\n      else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt    <= 1'b0;\n      else if (axis_wr_eop)\n        axis_wpkt_cnt    <= axis_wpkt_cnt + 1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt_gc    <= 1'b0;\n      else \n        axis_wpkt_cnt_gc    <= bin2gray(axis_wpkt_cnt);\n    end\n\n\n    assign  wpkt_q[0]  = axis_wpkt_cnt_gc;\n    assign  axis_wpkt_cnt_gc_asreg_last       = wpkt_q[C_SYNCHRONIZER_STAGE];\n    assign  axis_af_q[0]                      = axis_almost_full;\n    //assign  axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];\n    assign  axis_af_rd                        = axis_af_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_wpkt_cnt_rd    <= 1'b0;\n      else \n        axis_wpkt_cnt_rd    <= gray2bin(axis_wpkt_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_rpkt_cnt    <= 1'b0;\n      else if (axis_rd_eop)\n        axis_rpkt_cnt    <= axis_rpkt_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;\n   assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1]             = ~axis_rpkt_cnt;\n   assign adj_axis_wpkt_cnt_rd_pad[0]                                = adj_axis_wpkt_cnt_rd_pad_0;\n   assign rpkt_inv_pad[0]                                            = rpkt_inv_pad_0;\n\n\n  always @ ( axis_rd_eop )\n    begin\n      if (!axis_rd_eop) begin\n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b1;\n        rpkt_inv_pad_0                <= 1'b1;\n      end else begin \n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b0;\n        rpkt_inv_pad_0                <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        diff_pkt_cnt_pad    <= 1'b0;\n      else \n        diff_pkt_cnt_pad    <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;\n    end\n\n   assign  diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;\n\n\n\n\n\n   end endgenerate // gaxis_pkt_fifo_ic\n\n\n\n\n  // Generate the accurate data count for axi stream packet fifo configuration\n  reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_dc_pkt_fifo <= 0;\n      else if (axis_wr_en && (~axis_rd_en))\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;\n      else if (~axis_wr_en && axis_rd_en)\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;\n    end\n    assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;\n  end endgenerate // gdc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt\n    assign AXIS_DATA_COUNT = 0;\n  end endgenerate // gndc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc\n    assign AXIS_DATA_COUNT = axis_dc;\n  end endgenerate // gdc\n\n  // Register Slice for Write Address Channel\n  generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_AXIS),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_AXIS)\n            )\n    axis_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (axis_din),\n          .S_VALID                   (axis_wr_en),\n          .S_READY                   (S_AXIS_TREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (axis_dout),\n          .M_VALID                   (M_AXIS_TVALID),\n          .M_READY                   (axis_rd_en)\n          );\n  end endgenerate // gaxis_reg_slice\n\n\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata\n    assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;\n    assign M_AXIS_TDATA   = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb\n    assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;\n    assign M_AXIS_TSTRB   = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep\n    assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;\n    assign M_AXIS_TKEEP   = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid\n    assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;\n    assign M_AXIS_TID     = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest\n    assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;\n    assign M_AXIS_TDEST   = axis_dout[TID_OFFSET-1:TDEST_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser\n    assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;\n    assign M_AXIS_TUSER   = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast\n    assign axis_din[0] = S_AXIS_TLAST;\n    assign M_AXIS_TLAST   = axis_dout[0];\n  end endgenerate\n\n  //###########################################################################\n  //  AXI FULL Write Channel (axi_write_channel)\n  //###########################################################################\n\n  localparam IS_AXI_FULL       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;\n  localparam IS_AXI_LITE       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;\n\n  localparam IS_AXI_FULL_WACH  = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WDCH  = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WRCH  = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RACH  = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RDCH  = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_AXI_LITE_WACH  = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WDCH  = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WRCH  = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RACH  = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RDCH  = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_WR_ADDR_CH     = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;\n  localparam IS_WR_DATA_CH     = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;\n  localparam IS_WR_RESP_CH     = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;\n  localparam IS_RD_ADDR_CH     = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;\n  localparam IS_RD_DATA_CH     = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;\n\n  localparam AWID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;\n  localparam AWADDR_OFFSET     = AWID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam AWLEN_OFFSET      = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;\n  localparam AWSIZE_OFFSET     = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;\n  localparam AWBURST_OFFSET    = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;\n  localparam AWLOCK_OFFSET     = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;\n  localparam AWCACHE_OFFSET    = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;\n  localparam AWPROT_OFFSET     = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam AWQOS_OFFSET      = AWPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam AWREGION_OFFSET   = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;\n  localparam AWUSER_OFFSET     = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;\n\n  localparam WID_OFFSET        = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;\n  localparam WDATA_OFFSET      = WID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam WSTRB_OFFSET      = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;\n  localparam WUSER_OFFSET      = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;\n\n  localparam BID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;\n  localparam BRESP_OFFSET      = BID_OFFSET - C_AXI_BRESP_WIDTH;\n  localparam BUSER_OFFSET      = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;\n\n\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_din          ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout         ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout_pkt     ;\n  wire                          wach_full         ;\n  wire                          wach_almost_full  ;\n  wire                          wach_prog_full    ;\n  wire                          wach_empty        ;\n  wire                          wach_almost_empty ;\n  wire                          wach_prog_empty   ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_din          ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_dout         ;\n  wire                          wdch_full         ;\n  wire                          wdch_almost_full  ;\n  wire                          wdch_prog_full    ;\n  wire                          wdch_empty        ;\n  wire                          wdch_almost_empty ;\n  wire                          wdch_prog_empty   ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_din          ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_dout         ;\n  wire                          wrch_full         ;\n  wire                          wrch_almost_full  ;\n  wire                          wrch_prog_full    ;\n  wire                          wrch_empty        ;\n  wire                          wrch_almost_empty ;\n  wire                          wrch_prog_empty   ;\n  wire                          axi_aw_underflow_i;\n  wire                          axi_w_underflow_i ;\n  wire                          axi_b_underflow_i ;\n  wire                          axi_aw_overflow_i ;\n  wire                          axi_w_overflow_i  ;\n  wire                          axi_b_overflow_i  ;\n  wire                          axi_wr_underflow_i;\n  wire                          axi_wr_overflow_i ;\n  wire                          wach_s_axi_awready;\n  wire                          wach_m_axi_awvalid;\n  wire                          wach_wr_en        ;\n  wire                          wach_rd_en        ;\n  wire                          wdch_s_axi_wready ;\n  wire                          wdch_m_axi_wvalid ;\n  wire                          wdch_wr_en        ;\n  wire                          wdch_rd_en        ;\n  wire                          wrch_s_axi_bvalid ;\n  wire                          wrch_m_axi_bready ;\n  wire                          wrch_wr_en        ;\n  wire                          wrch_rd_en        ;\n  wire                          txn_count_up      ;\n  wire                          txn_count_down    ;\n  wire                          awvalid_en        ;\n  wire                          awvalid_pkt       ;\n  wire                          awready_pkt       ;\n  integer                       wr_pkt_count      ;\n  wire                          wach_we           ;\n  wire                          wach_re           ;\n  wire                          wdch_we           ;\n  wire                          wdch_re           ;\n  wire                          wrch_we           ;\n  wire                          wrch_re           ;\n\n  generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel\n    // Write protection when almost full or prog_full is high\n    assign wach_we    = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wach_re    = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        wach_m_axi_awvalid & awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY && wach_m_axi_awvalid :\n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY : 1'b0;\n    assign wach_wr_en = (C_HAS_SLAVE_CE == 1)  ? wach_we & S_ACLK_EN : wach_we;\n    assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 2  || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),\n        .C_USE_ECC                      (C_USE_ECC_WACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wach_wr_en),\n        .RD_EN                    (wach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AW_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AW_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AW_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AW_INJECTSBITERR),\n  \n        .DIN                      (wach_din),\n        .DOUT                     (wach_dout_pkt),\n        .FULL                     (wach_full),\n        .EMPTY                    (wach_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_AW_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_AW_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_aw_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_aw_underflow_i),\n        .DATA_COUNT               (AXI_AW_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AW_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AW_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AW_SBITERR),\n        .DBITERR                  (AXI_AW_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wach),\n        .rd_rst_busy              (rd_rst_busy_wach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wach_s_axi_awready    = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;\n    assign wach_m_axi_awvalid   = ~wach_empty;\n    assign S_AXI_AWREADY        = wach_s_axi_awready;\n\n    assign AXI_AW_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;\n    assign AXI_AW_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_aw_overflow_i  : 0;\n\n  end endgenerate // axi_write_address_channel\n\n  // Register Slice for Write Address Channel\n  generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WACH)\n            )\n    wach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_din),\n          .S_VALID                   (S_AXI_AWVALID),\n          .S_READY                   (S_AXI_AWREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n  end endgenerate // gwach_reg_slice\n  \n  generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (1)\n            )\n    wach_pkt_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_dout_pkt),\n          .S_VALID                   (awvalid_pkt),\n          .S_READY                   (awready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n\n    assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;\n\n    assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; \n    assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset == 1) begin\n\twr_pkt_count <= 0;\n      end else begin\n\tif(txn_count_up == 1 && txn_count_down == 0) begin\n\t  wr_pkt_count <= wr_pkt_count + 1;\n\tend else if(txn_count_up == 0 && txn_count_down == 1) begin\n\t  wr_pkt_count <= wr_pkt_count - 1;\n\tend\n      end\n    end //Always end\n    assign awvalid_en = (wr_pkt_count > 0)?1:0;\n  end endgenerate\n  \n  generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr\n    assign awvalid_en    = 1;    \n    assign wach_dout     = wach_dout_pkt;\n    assign M_AXI_AWVALID = wach_m_axi_awvalid;\n  end\n  endgenerate\n\n\n\n  generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel\n    // Write protection when almost full or prog_full is high\n    assign wdch_we    = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wdch_re    = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;\n    assign wdch_wr_en = (C_HAS_SLAVE_CE == 1)  ? wdch_we & S_ACLK_EN : wdch_we;\n    assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;\n\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 2  || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),\n        .C_USE_ECC                      (C_USE_ECC_WDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wdch_wr_en),\n        .RD_EN                    (wdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_W_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_W_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_W_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_W_INJECTSBITERR),\n  \n        .DIN                      (wdch_din),\n        .DOUT                     (wdch_dout),\n        .FULL                     (wdch_full),\n        .EMPTY                    (wdch_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_W_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_W_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_w_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_w_underflow_i),\n        .DATA_COUNT               (AXI_W_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_W_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_W_WR_DATA_COUNT),\n        .SBITERR                  (AXI_W_SBITERR),\n        .DBITERR                  (AXI_W_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wdch),\n        .rd_rst_busy              (rd_rst_busy_wdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wdch_s_axi_wready     = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;\n    assign wdch_m_axi_wvalid = ~wdch_empty;\n    assign S_AXI_WREADY      = wdch_s_axi_wready;\n    assign M_AXI_WVALID      = wdch_m_axi_wvalid;\n\n    assign AXI_W_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i  : 0;\n    assign AXI_W_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_w_overflow_i   : 0;\n\n  end endgenerate // axi_write_data_channel\n\n  // Register Slice for Write Data Channel\n  generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WDCH)\n            )\n    wdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wdch_din),\n          .S_VALID                   (S_AXI_WVALID),\n          .S_READY                   (S_AXI_WREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wdch_dout),\n          .M_VALID                   (M_AXI_WVALID),\n          .M_READY                   (M_AXI_WREADY)\n          );\n  end endgenerate // gwdch_reg_slice\n\n  generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel\n    // Write protection when almost full or prog_full is high\n    assign wrch_we    = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wrch_re    = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;\n    assign wrch_wr_en = (C_HAS_MASTER_CE == 1)  ? wrch_we & M_ACLK_EN : wrch_we;\n    assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 2  || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WRCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WRCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),\n        .C_USE_ECC                      (C_USE_ECC_WRCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WRCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WRCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wrch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wrch_wr_en),\n        .RD_EN                    (wrch_rd_en),\n        .PROG_FULL_THRESH         (AXI_B_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_B_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .INJECTDBITERR            (AXI_B_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_B_INJECTSBITERR),\n  \n        .DIN                      (wrch_din),\n        .DOUT                     (wrch_dout),\n        .FULL                     (wrch_full),\n        .EMPTY                    (wrch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_B_PROG_FULL),\n        .PROG_EMPTY               (AXI_B_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_b_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_b_underflow_i),\n        .DATA_COUNT               (AXI_B_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_B_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_B_WR_DATA_COUNT),\n        .SBITERR                  (AXI_B_SBITERR),\n        .DBITERR                  (AXI_B_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wrch),\n        .rd_rst_busy              (rd_rst_busy_wrch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wrch_s_axi_bvalid = ~wrch_empty;\n    assign wrch_m_axi_bready     = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;\n    assign S_AXI_BVALID      = wrch_s_axi_bvalid;\n    assign M_AXI_BREADY      = wrch_m_axi_bready;\n\n    assign AXI_B_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i  : 0;\n    assign AXI_B_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_b_overflow_i   : 0;\n  end endgenerate // axi_write_resp_channel\n\n  // Register Slice for Write Response Channel\n  generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WRCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WRCH)\n            )\n    wrch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wrch_din),\n          .S_VALID                   (M_AXI_BVALID),\n          .S_READY                   (M_AXI_BREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wrch_dout),\n          .M_VALID                   (S_AXI_BVALID),\n          .M_READY                   (S_AXI_BREADY)\n          );\n  end endgenerate // gwrch_reg_slice\n\n\n    assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW  == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;\n    assign axi_wr_overflow_i  = C_USE_COMMON_OVERFLOW   == 1 ? (axi_aw_overflow_i  || axi_w_overflow_i  || axi_b_overflow_i)  : 0;\n\n  generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output\n    assign M_AXI_AWADDR    = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];    \n    assign M_AXI_AWLEN     = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];    \n    assign M_AXI_AWSIZE    = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];    \n    assign M_AXI_AWBURST   = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];    \n    assign M_AXI_AWLOCK    = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];    \n    assign M_AXI_AWCACHE   = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];    \n    assign M_AXI_AWQOS     = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];    \n    assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET]    = S_AXI_AWADDR;\n    assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET]   = S_AXI_AWLEN;\n    assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET]   = S_AXI_AWSIZE;\n    assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;\n    assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;\n    assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;\n    assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;\n    assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET]   = S_AXI_AWQOS;\n  end endgenerate // axi_wach_output\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion\n    assign M_AXI_AWREGION  = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];    \n  end endgenerate // axi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion\n    assign M_AXI_AWREGION  = 0;    \n  end endgenerate // naxi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser\n    assign M_AXI_AWUSER  = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];    \n  end endgenerate // axi_awuser\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser\n    assign M_AXI_AWUSER  = 0;    \n  end endgenerate // naxi_awuser\n\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid\n    assign M_AXI_AWID      = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];\n  end endgenerate //axi_awid\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid\n    assign M_AXI_AWID      = 0;\n  end endgenerate //naxi_awid\n\n  generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output\n    assign M_AXI_WDATA     = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n    assign M_AXI_WLAST     = wdch_dout[0];\n    assign wdch_din[WID_OFFSET-1:WDATA_OFFSET]   = S_AXI_WDATA;\n    assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;\n    assign wdch_din[0]   = S_AXI_WLAST;\n  end endgenerate // axi_wdch_output\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin\n    assign M_AXI_WID       = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];\n  end endgenerate\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin\n    assign M_AXI_WID       = 0;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin\n    assign M_AXI_WUSER     = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];    \n  end endgenerate\n  generate if (C_HAS_AXI_WUSER == 0) begin\n    assign M_AXI_WUSER       = 0;\n  end endgenerate\n\n  generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output\n    assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; \n    assign wrch_din[BID_OFFSET-1:BRESP_OFFSET]   = M_AXI_BRESP;\n  end endgenerate // axi_wrch_output\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser\n    assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];\n  end endgenerate // axi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser\n    assign S_AXI_BUSER = 0;\n  end endgenerate // naxi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid\n    assign S_AXI_BID   =  wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];\n  end endgenerate // axi_bid\n  \n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid\n    assign S_AXI_BID   =  0 ;\n  end endgenerate // naxi_bid  \n\n\n  generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1\n    assign wach_din        = {S_AXI_AWADDR, S_AXI_AWPROT};\n    assign M_AXI_AWADDR    = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];    \n  end endgenerate // axi_wach_output1\n\n  generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1\n    assign wdch_din        = {S_AXI_WDATA, S_AXI_WSTRB};\n    assign M_AXI_WDATA     = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n  end endgenerate // axi_wdch_output1\n\n  generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1\n    assign wrch_din        = M_AXI_BRESP;\n    assign S_AXI_BRESP     = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; \n  end endgenerate // axi_wrch_output1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1\n    assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET]     = S_AXI_AWUSER;\n  end endgenerate // gwach_din1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2\n    assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET]     = S_AXI_AWID;\n  end endgenerate // gwach_din2\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3\n    assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET]     = S_AXI_AWREGION;\n  end endgenerate // gwach_din3\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1\n    assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;\n  end endgenerate // gwdch_din1\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2\n    assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;\n  end endgenerate // gwdch_din2\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1\n    assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET]    = M_AXI_BUSER;\n  end endgenerate // gwrch_din1\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2\n    assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET]    = M_AXI_BID;\n  end endgenerate // gwrch_din2\n\n  //end of  axi_write_channel\n\n  //###########################################################################\n  //  AXI FULL Read Channel (axi_read_channel)\n  //###########################################################################\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_din            ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout           ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout_pkt       ;\n  wire                               rach_full           ;\n  wire                               rach_almost_full    ;\n  wire                               rach_prog_full      ;\n  wire                               rach_empty          ;\n  wire                               rach_almost_empty   ;\n  wire                               rach_prog_empty     ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_din            ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_dout           ;\n  wire                               rdch_full           ;\n  wire                               rdch_almost_full    ;\n  wire                               rdch_prog_full      ;\n  wire                               rdch_empty          ;\n  wire                               rdch_almost_empty   ;\n  wire                               rdch_prog_empty     ;\n  wire                               axi_ar_underflow_i  ;\n  wire                               axi_r_underflow_i   ;\n  wire                               axi_ar_overflow_i   ;\n  wire                               axi_r_overflow_i    ;\n  wire                               axi_rd_underflow_i  ;\n  wire                               axi_rd_overflow_i   ;\n  wire                               rach_s_axi_arready  ;\n  wire                               rach_m_axi_arvalid  ;\n  wire                               rach_wr_en          ;\n  wire                               rach_rd_en          ;\n  wire                               rdch_m_axi_rready   ;\n  wire                               rdch_s_axi_rvalid   ;\n  wire                               rdch_wr_en          ;\n  wire                               rdch_rd_en          ;\n  wire                               arvalid_pkt         ;\n  wire                               arready_pkt         ;\n  wire                               arvalid_en          ;\n  wire                               rdch_rd_ok          ;\n  wire                               accept_next_pkt     ;\n  integer                            rdch_free_space     ;\n  integer                            rdch_commited_space ;\n  wire                               rach_we             ;\n  wire                               rach_re             ;\n  wire                               rdch_we             ;\n  wire                               rdch_re             ;\n\n  localparam ARID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;\n  localparam ARADDR_OFFSET     = ARID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam ARLEN_OFFSET      = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;\n  localparam ARSIZE_OFFSET     = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;\n  localparam ARBURST_OFFSET    = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;\n  localparam ARLOCK_OFFSET     = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;\n  localparam ARCACHE_OFFSET    = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;\n  localparam ARPROT_OFFSET     = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam ARQOS_OFFSET      = ARPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam ARREGION_OFFSET   = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;\n  localparam ARUSER_OFFSET     = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;\n\n  localparam RID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;\n  localparam RDATA_OFFSET      = RID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam RRESP_OFFSET      = RDATA_OFFSET - C_AXI_RRESP_WIDTH;\n  localparam RUSER_OFFSET      = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;\n\n\n  generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rach_we    = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;\n\n    // Read protection when almost empty or prog_empty is high\n//    assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;\n    assign rach_re    = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        rach_m_axi_arvalid & arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY && rach_m_axi_arvalid :\n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY : 1'b0;\n    assign rach_wr_en = (C_HAS_SLAVE_CE == 1)  ? rach_we & S_ACLK_EN : rach_we;\n    assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;\n\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 2  || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),\n        .C_USE_ECC                      (C_USE_ECC_RACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_rach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rach_wr_en),\n        .RD_EN                    (rach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AR_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AR_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AR_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AR_INJECTSBITERR),\n  \n        .DIN                      (rach_din),\n        .DOUT                     (rach_dout_pkt),\n        .FULL                     (rach_full),\n        .EMPTY                    (rach_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_AR_PROG_FULL),\n        .PROG_EMPTY               (AXI_AR_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_ar_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_ar_underflow_i),\n        .DATA_COUNT               (AXI_AR_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AR_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AR_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AR_SBITERR),\n        .DBITERR                  (AXI_AR_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rach),\n        .rd_rst_busy              (rd_rst_busy_rach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rach_s_axi_arready    = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;\n    assign rach_m_axi_arvalid = ~rach_empty;\n    assign S_AXI_ARREADY      = rach_s_axi_arready;\n\n    assign AXI_AR_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;\n    assign AXI_AR_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_ar_overflow_i  : 0;\n\n  end endgenerate // axi_read_addr_channel\n\n  // Register Slice for Read Address Channel\n  generate if (C_RACH_TYPE == 1) begin : grach_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RACH)\n            )\n    rach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_din),\n          .S_VALID                   (S_AXI_ARVALID),\n          .S_READY                   (S_AXI_ARREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice\n\n  // Register Slice for Read Address Channel for MM Packet FIFO\n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (1)\n            )\n    reg_slice_mm_pkt_fifo_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_dout_pkt),\n          .S_VALID                   (arvalid_pkt),\n          .S_READY                   (arready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice_mm_pkt_fifo\n\n  \n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid\n    assign M_AXI_ARVALID      = rach_m_axi_arvalid;\n    assign rach_dout          = rach_dout_pkt;\n  end endgenerate // grach_m_axi_arvalid\n  \n  \n  generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd\n    assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;\n    assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;\n    assign accept_next_pkt  = rach_m_axi_arvalid && arready_pkt && arvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset) begin\n\trdch_commited_space <= 0;\n      end else begin\n\tif(rdch_rd_ok && !accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space-1;\n\tend else if(!rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);\n\tend else if(rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);\n\tend\n      end\n    end //Always end\n\n    always@(*) begin\n      rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));\n    end\n\n    assign arvalid_en = (rdch_free_space >= 0)?1:0;\n  end\n  endgenerate\n  \n  generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd\n    assign arvalid_en = 1;    \n  end\n  endgenerate\n\n  generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rdch_we    = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready  & M_AXI_RVALID : M_AXI_RVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign rdch_re    = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid  & S_AXI_RREADY : S_AXI_RREADY;\n    assign rdch_wr_en = (C_HAS_MASTER_CE == 1)  ? rdch_we & M_ACLK_EN : rdch_we;\n    assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 2  || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),\n        .C_USE_ECC                      (C_USE_ECC_RDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_RDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_rdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rdch_wr_en),\n        .RD_EN                    (rdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_R_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_R_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_R_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_R_INJECTSBITERR),\n  \n        .DIN                      (rdch_din),\n        .DOUT                     (rdch_dout),\n        .FULL                     (rdch_full),\n        .EMPTY                    (rdch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_R_PROG_FULL),\n        .PROG_EMPTY               (AXI_R_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_r_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_r_underflow_i),\n        .DATA_COUNT               (AXI_R_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_R_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_R_WR_DATA_COUNT),\n        .SBITERR                  (AXI_R_SBITERR),\n        .DBITERR                  (AXI_R_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rdch),\n        .rd_rst_busy              (rd_rst_busy_rdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rdch_s_axi_rvalid = ~rdch_empty;\n    assign rdch_m_axi_rready     = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;\n    assign S_AXI_RVALID      = rdch_s_axi_rvalid;\n    assign M_AXI_RREADY      = rdch_m_axi_rready;\n\n    assign AXI_R_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i  : 0;\n    assign AXI_R_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_r_overflow_i   : 0;\n\n  end endgenerate //axi_read_data_channel\n\n  // Register Slice for read Data Channel\n  generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RDCH)\n            )\n    rdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rdch_din),\n          .S_VALID                   (M_AXI_RVALID),\n          .S_READY                   (M_AXI_RREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rdch_dout),\n          .M_VALID                   (S_AXI_RVALID),\n          .M_READY                   (S_AXI_RREADY)\n          );\n  end endgenerate // grdch_reg_slice\n\n\n    assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;\n    assign axi_rd_overflow_i  = C_USE_COMMON_OVERFLOW  == 1 ? (axi_ar_overflow_i  || axi_r_overflow_i) : 0;\n\n\n  generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output\n    assign M_AXI_ARADDR    = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];    \n    assign M_AXI_ARLEN     = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];    \n    assign M_AXI_ARSIZE    = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];    \n    assign M_AXI_ARBURST   = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];    \n    assign M_AXI_ARLOCK    = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];    \n    assign M_AXI_ARCACHE   = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];    \n    assign M_AXI_ARPROT    = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];    \n    assign M_AXI_ARQOS     = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];    \n    assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET]    = S_AXI_ARADDR;\n    assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET]   = S_AXI_ARLEN;\n    assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET]   = S_AXI_ARSIZE;\n    assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;\n    assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;\n    assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;\n    assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;\n    assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET]   = S_AXI_ARQOS;\n  end endgenerate // axi_full_rach_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion\n    assign M_AXI_ARREGION  = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];    \n  end endgenerate // axi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion\n    assign M_AXI_ARREGION  = 0;    \n  end endgenerate // naxi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser\n    assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];    \n  end endgenerate // axi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser\n    assign M_AXI_ARUSER = 0;    \n  end endgenerate // naxi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid\n    assign M_AXI_ARID      = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];\n  end endgenerate // axi_arid\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid\n    assign M_AXI_ARID      = 0;\n  end endgenerate // naxi_arid\n\n  generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output\n    assign S_AXI_RDATA     = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];\n    assign S_AXI_RRESP     = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n    assign S_AXI_RLAST     = rdch_dout[0];\n    assign rdch_din[RID_OFFSET-1:RDATA_OFFSET]   = M_AXI_RDATA;\n    assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;\n    assign rdch_din[0] = M_AXI_RLAST;\n  end endgenerate // axi_full_rdch_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output\n    assign S_AXI_RUSER     = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];\n  end endgenerate // axi_full_ruser_output\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output\n    assign S_AXI_RUSER     =  0;\n  end endgenerate // axi_full_nruser_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid\n    assign S_AXI_RID       = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];\n  end endgenerate // axi_rid\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid\n    assign S_AXI_RID       = 0;\n  end endgenerate // naxi_rid\n\n  generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1\n    assign rach_din      = {S_AXI_ARADDR, S_AXI_ARPROT};\n    assign M_AXI_ARADDR  = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];\n    assign M_AXI_ARPROT  = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];\n  end endgenerate // axi_lite_rach_output\n\n  generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1\n    assign rdch_din      = {M_AXI_RDATA, M_AXI_RRESP};\n    assign S_AXI_RDATA   = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];\n    assign S_AXI_RRESP   = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n  end endgenerate // axi_lite_rdch_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1\n    assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET]     = S_AXI_ARUSER;\n  end endgenerate // grach_din1\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2\n    assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET]     = S_AXI_ARID;\n  end endgenerate // grach_din2\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin\n    assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1\n    assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET]     = M_AXI_RUSER;\n  end endgenerate // grdch_din1\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2\n    assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;\n  end endgenerate // grdch_din2\n\n  //end of axi_read_channel\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf\n    assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :\n                       (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :\n                       (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;\n  end endgenerate // gaxi_comm_uf\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of\n    assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :\n                      (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :\n                      (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;\n  end endgenerate // gaxi_comm_of\n  \n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  // Pass Through Logic or Wiring Logic\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  \n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Write Address Channel\n  generate if (C_WACH_TYPE == 2) begin : gwach_pass_through\n    assign M_AXI_AWID      = S_AXI_AWID;\n    assign M_AXI_AWADDR    = S_AXI_AWADDR;\n    assign M_AXI_AWLEN     = S_AXI_AWLEN;\n    assign M_AXI_AWSIZE    = S_AXI_AWSIZE;\n    assign M_AXI_AWBURST   = S_AXI_AWBURST;\n    assign M_AXI_AWLOCK    = S_AXI_AWLOCK;\n    assign M_AXI_AWCACHE   = S_AXI_AWCACHE;\n    assign M_AXI_AWPROT    = S_AXI_AWPROT;\n    assign M_AXI_AWQOS     = S_AXI_AWQOS;\n    assign M_AXI_AWREGION  = S_AXI_AWREGION;\n    assign M_AXI_AWUSER    = S_AXI_AWUSER;\n    assign S_AXI_AWREADY   = M_AXI_AWREADY;\n    assign M_AXI_AWVALID   = S_AXI_AWVALID;\n  end endgenerate // gwach_pass_through;\n\n  // Wiring logic for Write Data Channel\n  generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through\n    assign M_AXI_WID       = S_AXI_WID;\n    assign M_AXI_WDATA     = S_AXI_WDATA;\n    assign M_AXI_WSTRB     = S_AXI_WSTRB;\n    assign M_AXI_WLAST     = S_AXI_WLAST;\n    assign M_AXI_WUSER     = S_AXI_WUSER;\n    assign S_AXI_WREADY    = M_AXI_WREADY;\n    assign M_AXI_WVALID    = S_AXI_WVALID;\n  end endgenerate // gwdch_pass_through;\n\n  // Wiring logic for Write Response Channel\n  generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through\n    assign S_AXI_BID       = M_AXI_BID;\n    assign S_AXI_BRESP     = M_AXI_BRESP;\n    assign S_AXI_BUSER     = M_AXI_BUSER;\n    assign M_AXI_BREADY    = S_AXI_BREADY;\n    assign S_AXI_BVALID    = M_AXI_BVALID;\n  end endgenerate // gwrch_pass_through;\n\n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Read Address Channel\n  generate if (C_RACH_TYPE == 2) begin : grach_pass_through\n    assign M_AXI_ARID      = S_AXI_ARID;\n    assign M_AXI_ARADDR    = S_AXI_ARADDR;\n    assign M_AXI_ARLEN     = S_AXI_ARLEN;\n    assign M_AXI_ARSIZE    = S_AXI_ARSIZE;\n    assign M_AXI_ARBURST   = S_AXI_ARBURST;\n    assign M_AXI_ARLOCK    = S_AXI_ARLOCK;\n    assign M_AXI_ARCACHE   = S_AXI_ARCACHE;\n    assign M_AXI_ARPROT    = S_AXI_ARPROT;\n    assign M_AXI_ARQOS     = S_AXI_ARQOS;\n    assign M_AXI_ARREGION  = S_AXI_ARREGION;\n    assign M_AXI_ARUSER    = S_AXI_ARUSER;\n    assign S_AXI_ARREADY   = M_AXI_ARREADY;\n    assign M_AXI_ARVALID   = S_AXI_ARVALID;\n  end endgenerate // grach_pass_through;\n\n  // Wiring logic for Read Data Channel \n  generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through\n    assign S_AXI_RID      = M_AXI_RID;\n    assign S_AXI_RLAST    = M_AXI_RLAST;\n    assign S_AXI_RUSER    = M_AXI_RUSER;\n    assign S_AXI_RDATA    = M_AXI_RDATA;\n    assign S_AXI_RRESP    = M_AXI_RRESP;\n    assign S_AXI_RVALID   = M_AXI_RVALID;\n    assign M_AXI_RREADY   = S_AXI_RREADY;\n  end endgenerate // grdch_pass_through;\n\n  // Wiring logic for AXI Streaming\n  generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through\n    assign M_AXIS_TDATA   = S_AXIS_TDATA;\n    assign M_AXIS_TSTRB   = S_AXIS_TSTRB;\n    assign M_AXIS_TKEEP   = S_AXIS_TKEEP;\n    assign M_AXIS_TID     = S_AXIS_TID;\n    assign M_AXIS_TDEST   = S_AXIS_TDEST;\n    assign M_AXIS_TUSER   = S_AXIS_TUSER;\n    assign M_AXIS_TLAST   = S_AXIS_TLAST;\n    assign S_AXIS_TREADY  = M_AXIS_TREADY;\n    assign M_AXIS_TVALID  = S_AXIS_TVALID;\n  end endgenerate // gaxis_pass_through;\n\n\nendmodule //fifo_generator_v13_2_5\n\n\n\n/*******************************************************************************\n * Declaration of top-level module for Conventional FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_CONV_VER\n  #(\n    parameter  C_COMMON_CLOCK                 = 0,\n    parameter  C_INTERFACE_TYPE               = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_COUNT_TYPE                   = 0,\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DEFAULT_VALUE                = \"\",\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_ENABLE_RLOCS                 = 0,\n    parameter  C_FAMILY                       = \"virtex7\", //Not allowed in Verilog model\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_BACKUP                   = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_INT_CLK                  = 0,\n    parameter  C_HAS_MEMINIT_FILE             = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RD_RST                   = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_RST                   = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_INIT_WR_PNTR_VAL             = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_MIF_FILE_NAME                = \"\",\n    parameter  C_OPTIMIZATION_MODE            = 0,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PRIM_FIFO_TYPE               = \"\",\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_FREQ                      = 1,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_ECC                      = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_USE_FIFO16_FLAGS             = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_FREQ                      = 1,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_WR_RESPONSE_LATENCY          = 1,\n    parameter  C_MSGON_VAL                    = 1,\n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2,\n    parameter  C_AXI_TYPE                     = 0\n   )\n\n  (\n   input                               BACKUP,\n   input                               BACKUP_MARKER,\n   input                               CLK,\n   input                               RST,\n   input                               SRST,\n   input                               WR_CLK,\n   input                               WR_RST,\n   input                               RD_CLK,\n   input                               RD_RST,\n   input [C_DIN_WIDTH-1:0]             DIN,\n   input                               WR_EN,\n   input                               RD_EN,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_ASSERT,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_NEGATE,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_ASSERT,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_NEGATE,\n   input                               INT_CLK,\n   input                               INJECTDBITERR,\n   input                               INJECTSBITERR,\n  \n   output [C_DOUT_WIDTH-1:0]           DOUT,\n   output                              FULL,\n   output                              ALMOST_FULL,\n   output                              WR_ACK,\n   output                              OVERFLOW,\n   output                              EMPTY,\n   output                              ALMOST_EMPTY,\n   output                              VALID,\n   output                              UNDERFLOW,\n   output [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT,\n   output [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT,\n   output [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT,\n   output                              PROG_FULL,\n   output                              PROG_EMPTY,\n   output                              SBITERR,\n   output                              DBITERR,\n   output                              wr_rst_busy_o,\n   output                              wr_rst_busy,\n   output                              rd_rst_busy,\n   output                              wr_rst_i_out,\n   output                              rd_rst_i_out\n  );\n\n/*\n ******************************************************************************\n * Definition of Parameters\n ******************************************************************************\n *     C_COMMON_CLOCK                : Common Clock (1), Independent Clocks (0)\n *     C_COUNT_TYPE                  :    *not used\n *     C_DATA_COUNT_WIDTH            : Width of DATA_COUNT bus\n *     C_DEFAULT_VALUE               :    *not used\n *     C_DIN_WIDTH                   : Width of DIN bus\n *     C_DOUT_RST_VAL                : Reset value of DOUT\n *     C_DOUT_WIDTH                  : Width of DOUT bus\n *     C_ENABLE_RLOCS                :    *not used\n *     C_FAMILY                      : not used in bhv model\n *     C_FULL_FLAGS_RST_VAL          : Full flags rst val (0 or 1)\n *     C_HAS_ALMOST_EMPTY            : 1=Core has ALMOST_EMPTY flag\n *     C_HAS_ALMOST_FULL             : 1=Core has ALMOST_FULL flag\n *     C_HAS_BACKUP                  :    *not used\n *     C_HAS_DATA_COUNT              : 1=Core has DATA_COUNT bus\n *     C_HAS_INT_CLK                 : not used in bhv model\n *     C_HAS_MEMINIT_FILE            :    *not used\n *     C_HAS_OVERFLOW                : 1=Core has OVERFLOW flag\n *     C_HAS_RD_DATA_COUNT           : 1=Core has RD_DATA_COUNT bus\n *     C_HAS_RD_RST                  :    *not used\n *     C_HAS_RST                     : 1=Core has Async Rst\n *     C_HAS_SRST                    : 1=Core has Sync Rst\n *     C_HAS_UNDERFLOW               : 1=Core has UNDERFLOW flag\n *     C_HAS_VALID                   : 1=Core has VALID flag\n *     C_HAS_WR_ACK                  : 1=Core has WR_ACK flag\n *     C_HAS_WR_DATA_COUNT           : 1=Core has WR_DATA_COUNT bus\n *     C_HAS_WR_RST                  :    *not used\n *     C_IMPLEMENTATION_TYPE         : 0=Common-Clock Bram/Dram\n *                                     1=Common-Clock ShiftRam\n *                                     2=Indep. Clocks Bram/Dram\n *                                     3=Virtex-4 Built-in\n *                                     4=Virtex-5 Built-in\n *     C_INIT_WR_PNTR_VAL            :   *not used\n *     C_MEMORY_TYPE                 : 1=Block RAM\n *                                     2=Distributed RAM\n *                                     3=Shift RAM\n *                                     4=Built-in FIFO\n *     C_MIF_FILE_NAME               :   *not used\n *     C_OPTIMIZATION_MODE           :   *not used\n *     C_OVERFLOW_LOW                : 1=OVERFLOW active low\n *     C_PRELOAD_LATENCY             : Latency of read: 0, 1, 2\n *     C_PRELOAD_REGS                : 1=Use output registers\n *     C_PRIM_FIFO_TYPE              : not used in bhv model\n *     C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold\n *     C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold\n *     C_PROG_EMPTY_TYPE             : 0=No programmable empty\n *                                     1=Single prog empty thresh constant\n *                                     2=Multiple prog empty thresh constants\n *                                     3=Single prog empty thresh input\n *                                     4=Multiple prog empty thresh inputs\n *     C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold\n *     C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold\n *     C_PROG_FULL_TYPE              : 0=No prog full\n *                                     1=Single prog full thresh constant\n *                                     2=Multiple prog full thresh constants\n *                                     3=Single prog full thresh input\n *                                     4=Multiple prog full thresh inputs\n *     C_RD_DATA_COUNT_WIDTH         : Width of RD_DATA_COUNT bus\n *     C_RD_DEPTH                    : Depth of read interface (2^N)\n *     C_RD_FREQ                     : not used in bhv model\n *     C_RD_PNTR_WIDTH               : always log2(C_RD_DEPTH)\n *     C_UNDERFLOW_LOW               : 1=UNDERFLOW active low\n *     C_USE_DOUT_RST                : 1=Resets DOUT on RST\n *     C_USE_ECC                     : Used for error injection purpose\n *     C_USE_EMBEDDED_REG            : 1=Use BRAM embedded output register\n *     C_USE_FIFO16_FLAGS            : not used in bhv model\n *     C_USE_FWFT_DATA_COUNT         : 1=Use extra logic for FWFT data count\n *     C_VALID_LOW                   : 1=VALID active low\n *     C_WR_ACK_LOW                  : 1=WR_ACK active low\n *     C_WR_DATA_COUNT_WIDTH         : Width of WR_DATA_COUNT bus\n *     C_WR_DEPTH                    : Depth of write interface (2^N)\n *     C_WR_FREQ                     : not used in bhv model\n *     C_WR_PNTR_WIDTH               : always log2(C_WR_DEPTH)\n *     C_WR_RESPONSE_LATENCY         :    *not used\n *     C_MSGON_VAL                   :    *not used by bhv model\n *     C_ENABLE_RST_SYNC             : 0 = Use WR_RST & RD_RST\n *                                     1 = Use RST\n *     C_ERROR_INJECTION_TYPE        : 0 = No error injection\n *                                     1 = Single bit error injection only\n *                                     2 = Double bit error injection only\n *                                     3 = Single and double bit error injection\n ******************************************************************************\n * Definition of Ports\n ******************************************************************************\n *   BACKUP       : Not used\n *   BACKUP_MARKER: Not used\n *   CLK          : Clock\n *   DIN          : Input data bus\n *   PROG_EMPTY_THRESH       : Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag\n *   PROG_FULL_THRESH        : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag\n *   RD_CLK       : Read Domain Clock\n *   RD_EN        : Read enable\n *   RD_RST       : Read Reset\n *   RST          : Asynchronous Reset\n *   SRST         : Synchronous Reset\n *   WR_CLK       : Write Domain Clock\n *   WR_EN        : Write enable\n *   WR_RST       : Write Reset\n *   INT_CLK      : Internal Clock\n *   INJECTSBITERR: Inject Signle bit error\n *   INJECTDBITERR: Inject Double bit error\n *   ALMOST_EMPTY : One word remaining in FIFO\n *   ALMOST_FULL  : One empty space remaining in FIFO\n *   DATA_COUNT   : Number of data words in fifo( synchronous to CLK)\n *   DOUT         : Output data bus\n *   EMPTY        : Empty flag\n *   FULL         : Full flag\n *   OVERFLOW     : Last write rejected\n *   PROG_EMPTY   : Programmable Empty Flag\n *   PROG_FULL    : Programmable Full Flag\n *   RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)\n *   UNDERFLOW    : Last read rejected\n *   VALID        : Last read acknowledged, DOUT bus VALID\n *   WR_ACK       : Last write acknowledged\n *   WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)\n *   SBITERR      : Single Bit ECC Error Detected\n *   DBITERR      : Double Bit ECC Error Detected\n ******************************************************************************\n */\n\n  //----------------------------------------------------------------------------\n  //- Internal Signals for delayed input signals\n  //- All the input signals except Clock are delayed by 100 ps and then given to\n  //- the models.\n  //----------------------------------------------------------------------------\n \n  reg                         rst_delayed                       ;\n  reg                         empty_fb                       ;\n  reg                         srst_delayed                      ;\n  reg                         wr_rst_delayed                    ;\n  reg                         rd_rst_delayed                    ;\n  reg                         wr_en_delayed                     ;\n  reg                         rd_en_delayed                     ;\n  reg  [C_DIN_WIDTH-1:0]      din_delayed                       ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_delayed         ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_assert_delayed  ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_negate_delayed  ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_delayed          ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_assert_delayed   ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_negate_delayed   ;\n  reg                         injectdbiterr_delayed             ;\n  reg                         injectsbiterr_delayed             ;\n   wire                        empty_p0_out;\n\n  always @* rst_delayed                       <= #`TCQ RST                      ;\n  always @* empty_fb                       <= #`TCQ empty_p0_out                      ;\n  always @* srst_delayed                      <= #`TCQ SRST                     ; \n  always @* wr_rst_delayed                    <= #`TCQ WR_RST                   ; \n  always @* rd_rst_delayed                    <= #`TCQ RD_RST                   ; \n  always @* din_delayed                       <= #`TCQ DIN                      ; \n  always @* wr_en_delayed                     <= #`TCQ WR_EN                    ; \n  always @* rd_en_delayed                     <= #`TCQ RD_EN                    ; \n  always @* prog_empty_thresh_delayed         <= #`TCQ PROG_EMPTY_THRESH        ; \n  always @* prog_empty_thresh_assert_delayed  <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; \n  always @* prog_empty_thresh_negate_delayed  <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; \n  always @* prog_full_thresh_delayed          <= #`TCQ PROG_FULL_THRESH         ; \n  always @* prog_full_thresh_assert_delayed   <= #`TCQ PROG_FULL_THRESH_ASSERT  ; \n  always @* prog_full_thresh_negate_delayed   <= #`TCQ PROG_FULL_THRESH_NEGATE  ; \n  always @* injectdbiterr_delayed             <= #`TCQ INJECTDBITERR            ; \n  always @* injectsbiterr_delayed             <= #`TCQ INJECTSBITERR            ; \n\n  /*****************************************************************************\n   * Derived parameters\n   ****************************************************************************/\n  //There are 2 Verilog behavioral models\n  // 0 = Common-Clock FIFO/ShiftRam FIFO\n  // 1 = Independent Clocks FIFO\n  // 2 = Low Latency Synchronous FIFO\n  // 3 = Low Latency Asynchronous FIFO\n  localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :\n                              (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n\n  //Internal reset signals\n  reg                                rd_rst_asreg    = 1'b0;\n  reg                                rd_rst_asreg_d1 = 1'b0;\n  reg                                rd_rst_asreg_d2 = 1'b0;\n  reg                                rd_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_reg      = 1'b0;\n  reg                                rd_rst_comb     = 1'b1;\n  reg                                rd_rst_comb_d1  = 1'b0;\n  reg                                wr_rst_d0       = 1'b0;\n  reg                                wr_rst_d1       = 1'b0;\n  reg                                wr_rst_d2       = 1'b0;\n  reg                                rd_rst_d0       = 1'b0;\n  reg                                rd_rst_d1       = 1'b0;\n  reg                                rd_rst_d2       = 1'b0;\n  reg                                rd_rst_d3       = 1'b0;\n  reg                                wrrst_done      = 1'b0;\n  reg                                rdrst_done      = 1'b0;\n  reg                                wr_rst_asreg    = 1'b0;\n  reg                                wr_rst_asreg_d1 = 1'b0;\n  reg                                wr_rst_asreg_d2 = 1'b0;\n  reg                                wr_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_wr_d0    = 1'b0;\n  reg                                rd_rst_wr_d1    = 1'b0;\n  reg                                rd_rst_wr_d2    = 1'b0;\n  reg                                wr_rst_reg      = 1'b0;\n  reg                                rst_active_i    = 1'b1;\n  reg                                rst_delayed_d1  = 1'b1;\n  reg                                rst_delayed_d2  = 1'b1;\n  reg                                wr_rst_comb     = 1'b1;\n  reg                                wr_rst_comb_d1  = 1'b0;\n  wire                               wr_rst_i;\n  wire                               rd_rst_i;\n  wire                               rst_i;\n\n  //Internal reset signals\n  reg                                rst_asreg     = 1'b0;\n  reg                                srst_asreg    = 1'b0;\n  reg                                rst_asreg_d1  = 1'b0;\n  reg                                rst_asreg_d2  = 1'b0;\n  reg                                srst_asreg_d1 = 1'b0;\n  reg                                srst_asreg_d2 = 1'b0;\n  reg                                rst_reg       = 1'b0;\n  reg                                srst_reg      = 1'b0;\n  reg                                rst_comb      = 1'b1;\n  reg                                rst_comb_d1   = 1'b0;\n  wire                               srst_comb;\n  reg                                rst_full_gen_i = 0;\n  reg                                rst_full_ff_i = 0;\n  reg  [2:0]                         sckt_ff0_bsy_o_i = {3{1'b0}};\n                                     \n  wire                               RD_CLK_P0_IN;\n  wire                               RST_P0_IN;\n  wire                               RD_EN_FIFO_IN;\n  wire                               RD_EN_P0_IN;\n\n  wire                               ALMOST_EMPTY_FIFO_OUT;\n  wire                               ALMOST_FULL_FIFO_OUT;\n  wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT_FIFO_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DOUT_FIFO_OUT;\n  wire                               EMPTY_FIFO_OUT;\n  wire                               fifo_empty_fb;\n  wire                               FULL_FIFO_OUT;\n  wire                               OVERFLOW_FIFO_OUT;\n  wire                               PROG_EMPTY_FIFO_OUT;\n  wire                               PROG_FULL_FIFO_OUT;\n  wire                               VALID_FIFO_OUT;\n  wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT_FIFO_OUT;\n  wire                               UNDERFLOW_FIFO_OUT;\n  wire                               WR_ACK_FIFO_OUT;\n  wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT_FIFO_OUT;\n\n\n  //***************************************************************************\n  // Internal Signals\n  //   The core uses either the internal_ wires or the preload0_ wires depending\n  //     on whether the core uses Preload0 or not.\n  //   When using preload0, the internal signals connect the internal core to\n  //     the preload logic, and the external core's interfaces are tied to the\n  //     preload0 signals from the preload logic.\n  //***************************************************************************\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_OUT;\n  wire                               VALID_P0_OUT;\n  wire                               EMPTY_P0_OUT;\n  wire                               ALMOSTEMPTY_P0_OUT;\n  reg                                EMPTY_P0_OUT_Q;\n  reg                                ALMOSTEMPTY_P0_OUT_Q;\n  wire                               UNDERFLOW_P0_OUT;\n  wire                               RDEN_P0_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_IN;\n  wire                               EMPTY_P0_IN;\n  reg  [31:0]                        DATA_COUNT_FWFT;\n  reg                                SS_FWFT_WR  ;\n  reg                                SS_FWFT_RD ;\n\n  wire                               sbiterr_fifo_out;\n  wire                               dbiterr_fifo_out;\n  wire                               inject_sbit_err;\n  wire                               inject_dbit_err;\n  wire                               sckt_wr_rst_i;\n  wire                               sckt_rd_rst_i;\n  reg                                sckt_wr_rst_i_q = 1'b0;\n \n  wire                               w_fab_read_data_valid_i;\n  wire                               w_read_data_valid_i;\n  wire                               w_ram_valid_i;\n  // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.\n  assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectsbiterr_delayed : 0;\n  assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectdbiterr_delayed : 0;\n                           \n  assign wr_rst_i_out = wr_rst_i;\n  assign rd_rst_i_out = rd_rst_i;\n  assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];\n  generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o\n    wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;\n    always @ (posedge clk_i)\n      sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; \n  end endgenerate \n// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL\n// parameter (1=Independent Clocks, 0=Common Clock)\n\n  localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;\ngenerate\ncase (C_VERILOG_IMPL)\n0 : begin : block1_ss\n  //Common Clock Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_ss\n  #(\n    .C_FAMILY                            (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                  (C_DATA_COUNT_WIDTH),            \n    .C_DIN_WIDTH                         (C_DIN_WIDTH),                   \n    .C_DOUT_RST_VAL                      (C_DOUT_RST_VAL),                \n    .C_DOUT_WIDTH                        (C_DOUT_WIDTH),                  \n    .C_FULL_FLAGS_RST_VAL                (FULL_FLAGS_RST_VAL),            \n    .C_HAS_ALMOST_EMPTY                  (C_HAS_ALMOST_EMPTY),            \n    .C_HAS_ALMOST_FULL                   ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),             \n    .C_HAS_DATA_COUNT                    (C_HAS_DATA_COUNT),              \n    .C_HAS_OVERFLOW                      (C_HAS_OVERFLOW),                \n    .C_HAS_RD_DATA_COUNT                 (C_HAS_RD_DATA_COUNT),           \n    .C_HAS_RST                           (C_EN_SAFETY_CKT?0:C_HAS_RST),                     \n    .C_HAS_SRST                          (C_EN_SAFETY_CKT?1:C_HAS_SRST),                    \n    .C_HAS_UNDERFLOW                     (C_HAS_UNDERFLOW),               \n    .C_HAS_VALID                         (C_HAS_VALID),                   \n    .C_HAS_WR_ACK                        (C_HAS_WR_ACK),                  \n    .C_HAS_WR_DATA_COUNT                 (C_HAS_WR_DATA_COUNT),           \n    .C_IMPLEMENTATION_TYPE               (C_IMPLEMENTATION_TYPE),         \n    .C_MEMORY_TYPE                       (C_MEMORY_TYPE),                 \n    .C_OVERFLOW_LOW                      (C_OVERFLOW_LOW),                \n    .C_PRELOAD_LATENCY                   (C_PRELOAD_LATENCY),             \n    .C_PRELOAD_REGS                      (C_PRELOAD_REGS),                \n    .C_PROG_EMPTY_THRESH_ASSERT_VAL      (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL      (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                   (C_PROG_EMPTY_TYPE),             \n    .C_PROG_FULL_THRESH_ASSERT_VAL       (C_PROG_FULL_THRESH_ASSERT_VAL), \n    .C_PROG_FULL_THRESH_NEGATE_VAL       (C_PROG_FULL_THRESH_NEGATE_VAL), \n    .C_PROG_FULL_TYPE                    (C_PROG_FULL_TYPE),              \n    .C_RD_DATA_COUNT_WIDTH               (C_RD_DATA_COUNT_WIDTH),         \n    .C_RD_DEPTH                          (C_RD_DEPTH),                    \n    .C_RD_PNTR_WIDTH                     (C_RD_PNTR_WIDTH),               \n    .C_UNDERFLOW_LOW                     (C_UNDERFLOW_LOW),               \n    .C_USE_DOUT_RST                      (C_USE_DOUT_RST),                \n    .C_USE_EMBEDDED_REG                  (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                     (C_EN_SAFETY_CKT),            \n    .C_USE_FWFT_DATA_COUNT               (C_USE_FWFT_DATA_COUNT),         \n    .C_VALID_LOW                         (C_VALID_LOW),                   \n    .C_WR_ACK_LOW                        (C_WR_ACK_LOW),                  \n    .C_WR_DATA_COUNT_WIDTH               (C_WR_DATA_COUNT_WIDTH),         \n    .C_WR_DEPTH                          (C_WR_DEPTH),                    \n    .C_WR_PNTR_WIDTH                     (C_WR_PNTR_WIDTH),               \n    .C_USE_ECC                           (C_USE_ECC),                     \n    .C_ENABLE_RST_SYNC                   (C_ENABLE_RST_SYNC),             \n    .C_ERROR_INJECTION_TYPE              (C_ERROR_INJECTION_TYPE),\n    .C_FIFO_TYPE                         (C_FIFO_TYPE)                     \n  )\n  gen_ss\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .CLK                      (CLK),\n    .RST                      (C_EN_SAFETY_CKT?1'b0:rst_i),\n    .SRST                     (C_EN_SAFETY_CKT?sckt_wr_rst_i:srst_delayed),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .USER_EMPTY_FB            (empty_fb),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .DATA_COUNT               (DATA_COUNT_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .WR_RST_BUSY              (wr_rst_busy),\n    .RD_RST_BUSY              (rd_rst_busy),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n1 : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT), \n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .fab_read_data_valid_i    (w_fab_read_data_valid_i),\n    .read_data_valid_i        (w_read_data_valid_i),\n    .ram_valid_i              (w_ram_valid_i),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\n2 : begin : ll_afifo_inst\n  fifo_generator_v13_2_5_beh_ver_ll_afifo\n  #(\n    .C_DIN_WIDTH                    (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                 (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                   (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_RD_DATA_COUNT            (C_HAS_RD_DATA_COUNT),\n    .C_HAS_WR_DATA_COUNT            (C_HAS_WR_DATA_COUNT),\n    .C_RD_DEPTH                     (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                (C_RD_PNTR_WIDTH),\n    .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n    .C_WR_DATA_COUNT_WIDTH          (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                     (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                (C_WR_PNTR_WIDTH),\n    .C_FIFO_TYPE                    (C_FIFO_TYPE)\n   )\n  gen_ll_afifo\n  (\n    .DIN                        (din_delayed),\n    .RD_CLK                     (RD_CLK),\n    .RD_EN                      (rd_en_delayed),\n    .WR_RST                     (wr_rst_i),\n    .RD_RST                     (rd_rst_i),\n    .WR_CLK                     (WR_CLK),\n    .WR_EN                      (wr_en_delayed),\n    .DOUT                       (DOUT),\n    .EMPTY                      (EMPTY),\n    .FULL                       (FULL)\n  );\nend\ndefault : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT),\n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\nendcase\nendgenerate\n\n\n   //**************************************************************************\n   // Connect Internal Signals\n   //   (Signals labeled internal_*)\n   //  In the normal case, these signals tie directly to the FIFO's inputs and\n   //    outputs.\n   //  In the case of Preload Latency 0 or 1, there are intermediate\n   //    signals between the internal FIFO and the preload logic.\n   //**************************************************************************\n   \n   \n   //***********************************************\n   // If First-Word Fall-Through, instantiate\n   // the preload0 (FWFT) module\n   //***********************************************\n   wire                        rd_en_to_fwft_fifo;\n   wire                        sbiterr_fwft;\n   wire                        dbiterr_fwft;\n   wire [C_DOUT_WIDTH-1:0]     dout_fwft;\n   wire                        empty_fwft;\n   wire                        rd_en_fifo_in;\n   wire                        stage2_reg_en_i;\n   wire [1:0]                  valid_stages_i;\n   wire                        rst_fwft;\n   //wire                        empty_p0_out;\n   reg  [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n   localparam IS_PKT_FIFO      = (C_FIFO_TYPE == 1) ? 1 : 0;\n   localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;\n   assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2_fwft\n\n\n         fifo_generator_v13_2_5_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_EMBEDDED_REG  (C_USE_EMBEDDED_REG),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (C_FIFO_TYPE)\n             )\n             fgpl0\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (RST_P0_IN),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (RD_EN_P0_IN),\n                .FIFOEMPTY        (EMPTY_P0_IN),\n                .FIFODATA         (DATA_P0_IN),\n                .FIFOSBITERR      (sbiterr_fifo_out),\n                .FIFODBITERR      (dbiterr_fifo_out),\n                // Output\n                .USERDATA         (dout_fwft),\n                .USERVALID        (VALID_P0_OUT),\n                .USEREMPTY        (empty_fwft),\n                .USERALMOSTEMPTY  (ALMOSTEMPTY_P0_OUT),\n                .USERUNDERFLOW    (UNDERFLOW_P0_OUT),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_fifo_in),\n                .USERSBITERR      (sbiterr_fwft),\n                .USERDBITERR      (dbiterr_fwft),\n                .STAGE2_REG_EN    (stage2_reg_en_i),\n                .fab_read_data_valid_i_o    (w_fab_read_data_valid_i),\n                .read_data_valid_i_o        (w_read_data_valid_i),\n                .ram_valid_i_o              (w_ram_valid_i),\n                .VALID_STAGES                (valid_stages_i)\n                );\n\n         \n         //***********************************************\n         // Connect inputs to preload (FWFT) module\n         //***********************************************\n         //Connect the RD_CLK of the Preload (FWFT) module to CLK if we \n         // have a common-clock FIFO, or RD_CLK if we have an \n         // independent clock FIFO\n         assign RD_CLK_P0_IN       = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);\n         assign RST_P0_IN          = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;\n         assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n         assign EMPTY_P0_IN        = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;\n         assign DATA_P0_IN         = DOUT_FIFO_OUT;\n         \n         //***********************************************\n         // Connect outputs from preload (FWFT) module\n         //***********************************************\n         assign VALID              = VALID_P0_OUT ;\n         assign ALMOST_EMPTY       = ALMOSTEMPTY_P0_OUT;\n         assign UNDERFLOW          = UNDERFLOW_P0_OUT ;\n         \n         assign RD_EN_FIFO_IN      = rd_en_fifo_in;\n         \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:\n           (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : \n           DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];  \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               EMPTY_P0_OUT_Q       <= 1;\n               ALMOSTEMPTY_P0_OUT_Q <= 1;\n            end else begin\n               EMPTY_P0_OUT_Q       <= #`TCQ empty_p0_out;\n//               EMPTY_P0_OUT_Q       <= #`TCQ EMPTY_FIFO_OUT;\n               ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;\n            end\n         end //always\n         \n         \n         //***********************************************\n         // logic for common-clock data count when FWFT is selected\n         //***********************************************\n         initial begin\n            SS_FWFT_RD = 1'b0;\n            DATA_COUNT_FWFT = 0 ;\n            SS_FWFT_WR   = 1'b0 ;\n         end //initial\n         \n         \n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter. SS_FWFT_WR and SS_FWFT_RD\n         // are the up/down enables for the counter.\n         //***********************************************\n         always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin\n            if (C_VALID_LOW == 1) begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;\n            end else begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;\n            end\n            SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT))  ;\n         end \n\n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter for FWFT. This always block \n         // calculates the counter.\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               DATA_COUNT_FWFT      <= 0;\n            end else begin\n               //if (srst_delayed && (C_HAS_SRST == 1) ) begin\n               if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin\n                  DATA_COUNT_FWFT      <= #`TCQ 0;\n               end else begin\n                  case ( {SS_FWFT_WR, SS_FWFT_RD})\n                    2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                    2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;\n                    2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;\n                    2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                  endcase  \n               end //if SRST\n            end //IF RST\n         end //always\n\n      end endgenerate // : block2\n\n    // AXI Streaming Packet FIFO\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_plus1 = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_reg   = 0;\n    reg                         partial_packet     = 0;\n    reg                         stage1_eop_d1      = 0;\n    reg                         rd_en_fifo_in_d1   = 0;\n    reg                         eop_at_stage2      = 0;\n    reg                         ram_pkt_empty      = 0;\n    reg                         ram_pkt_empty_d1   = 0;\n\n    wire [C_DOUT_WIDTH-1:0]     dout_p0_out;\n    wire                        packet_empty_wr;\n    wire                        wr_rst_fwft_pkt_fifo;\n    wire                        dummy_wr_eop;\n    wire                        ram_wr_en_pkt_fifo;\n    wire                        wr_eop;\n    wire                        ram_rd_en_compare;\n    wire                        stage1_eop;\n    wire                        pkt_ready_to_read;\n    wire                        rd_en_2_stage2;\n\n    // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)\n    // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP\n    // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of\n    // write packet count\n    generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop\n       always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n          if (wr_rst_fwft_pkt_fifo)\n             partial_packet   <= 1'b0;\n          else begin\n             if (srst_delayed | wr_rst_busy | rd_rst_busy)\n                partial_packet <= #`TCQ 1'b0;\n             else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))\n                partial_packet <= #`TCQ 1'b1;\n             else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)\n                partial_packet <= #`TCQ 1'b0;\n          end\n        end\n    end endgenerate // gdummy_wr_eop\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin : gpkt_fifo_fwft\n      assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;\n      assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);\n      assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];\n  \n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft) begin\n          stage1_eop_d1    <= 1'b0;\n          rd_en_fifo_in_d1 <= 1'b0;\n        end else begin\n          if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            stage1_eop_d1    <= #`TCQ 1'b0;\n            rd_en_fifo_in_d1 <= #`TCQ 1'b0;\n          end else begin\n            stage1_eop_d1    <= #`TCQ stage1_eop;\n            rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;\n          end\n        end\n      end\n      assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;\n      assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);\n      assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);\n      assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;\n\n\n         fifo_generator_v13_2_5_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (2) // Enable low latency fwft logic\n             )\n         pkt_fifo_fwft\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (rst_fwft),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (rd_en_delayed),\n                .FIFOEMPTY        (pkt_ready_to_read),\n                .FIFODATA         (dout_fwft),\n                .FIFOSBITERR      (sbiterr_fwft),\n                .FIFODBITERR      (dbiterr_fwft),\n                // Output\n                .USERDATA         (dout_p0_out),\n                .USERVALID        (),\n                .USEREMPTY        (empty_p0_out),\n                .USERALMOSTEMPTY  (),\n                .USERUNDERFLOW    (),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_2_stage2),\n                .USERSBITERR      (SBITERR),\n                .USERDBITERR      (DBITERR),\n                .STAGE2_REG_EN    (),\n                .VALID_STAGES     ()\n                );\n\n      assign pkt_ready_to_read  = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));\n      assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft)\n          eop_at_stage2 <= 1'b0;\n        else if (stage2_reg_en_i)\n          eop_at_stage2 <= #`TCQ stage1_eop;\n      end\n\n      //---------------------------------------------------------------------------\n      // Write and Read Packet Count\n      //---------------------------------------------------------------------------\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count  <= 0;\n         else if (srst_delayed  | wr_rst_busy | rd_rst_busy)\n            wr_pkt_count  <= #`TCQ 0;\n         else if (wr_eop)\n            wr_pkt_count  <= #`TCQ wr_pkt_count + 1;\n      end\n    \n    end endgenerate //: gpkt_fifo_fwft\n\n    assign DOUT               = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;\n    assign EMPTY              = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            rd_pkt_count       <= 0;\n            rd_pkt_count_plus1 <= 1;\n         end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            rd_pkt_count       <= #`TCQ 0;\n            rd_pkt_count_plus1 <= #`TCQ 1;\n         end else if (stage2_reg_en_i && stage1_eop) begin\n            rd_pkt_count       <= #`TCQ rd_pkt_count + 1;\n            rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;\n         end\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (SRST | wr_rst_busy | rd_rst_busy) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n    end endgenerate //grss_pkt_cnt\n    \n    localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;\n    reg  [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_b2g = 0;\n    wire [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_rd;\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt\n      // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count_b2g  <= 0;\n         else\n            wr_pkt_count_b2g  <= #`TCQ wr_pkt_count;\n      end\n\n      // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            wr_pkt_count_q       <= 0;\n         else\n            wr_pkt_count_q       <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};\n      end\n\n      always @* begin\n        if (stage1_eop)\n           rd_pkt_count    <= rd_pkt_count_reg + 1;\n        else\n           rd_pkt_count    <= rd_pkt_count_reg;\n      end\n\n      assign wr_pkt_count_rd    = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            rd_pkt_count_reg       <= 0;\n         else if (rd_en_fifo_in)\n            rd_pkt_count_reg       <= #`TCQ rd_pkt_count;\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (rd_pkt_count != wr_pkt_count_rd) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n\n      // Synchronize the empty in write domain\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            pkt_empty_sync  <= 'b1;\n         else\n            pkt_empty_sync  <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};\n      end\n\n    end endgenerate //gras_pkt_cnt\n\n   generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO\n\n     //***********************************************\n     // If NOT First-Word Fall-Through, wire the outputs\n     // of the internal _ss or _as FIFO directly to the\n     // output, and do not instantiate the preload0\n     // module.\n     //***********************************************\n\n     assign RD_CLK_P0_IN       = 0;\n     assign RST_P0_IN          = 0;\n     assign RD_EN_P0_IN        = 0;\n\n     assign RD_EN_FIFO_IN      = rd_en_delayed;\n\n     assign DOUT               = DOUT_FIFO_OUT;\n     assign DATA_P0_IN         = 0;\n     assign VALID              = VALID_FIFO_OUT;\n     assign EMPTY              = EMPTY_FIFO_OUT;\n     assign ALMOST_EMPTY       = ALMOST_EMPTY_FIFO_OUT;\n     assign EMPTY_P0_IN        = 0;\n     assign UNDERFLOW          = UNDERFLOW_FIFO_OUT;\n     assign DATA_COUNT         = DATA_COUNT_FIFO_OUT;\n     assign SBITERR            = sbiterr_fifo_out;\n     assign DBITERR            = dbiterr_fifo_out;\n\n   end endgenerate // STD_FIFO\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO\n     assign empty_p0_out       = empty_fwft;\n     assign SBITERR            = sbiterr_fwft;\n     assign DBITERR            = dbiterr_fwft;\n     assign DOUT               = dout_fwft;\n     assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n\n   end endgenerate // NO_PKT_FIFO\n\n   //***********************************************\n   // Connect user flags to internal signals\n   //***********************************************\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3\n      if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);\n      end //block_ic\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3\n   endgenerate\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30\n       if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30\n   endgenerate\n\n\n    \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both\n       if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30_both\n   endgenerate\n\n generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both\n      if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));\n      end //block_ic_both\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3_both\n   endgenerate\n\n\n   //If we are not using extra logic for the FWFT data count,\n   //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the\n   //internal FIFO instance  \n   generate\n      if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n   //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal\n   //FIFO instance\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1) begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n      else begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n\n   //Connect other flags to the internal FIFO instance\n   assign       FULL        = FULL_FIFO_OUT;\n   assign       ALMOST_FULL = ALMOST_FULL_FIFO_OUT;\n   assign       WR_ACK      = WR_ACK_FIFO_OUT;\n   assign       OVERFLOW    = OVERFLOW_FIFO_OUT;\n   assign       PROG_FULL   = PROG_FULL_FIFO_OUT;\n   assign       PROG_EMPTY  = PROG_EMPTY_FIFO_OUT;\n\n\n  /**************************************************************************\n  * find_log2\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n   // if an asynchronous FIFO has been selected, display a message that the FIFO\n   //   will not be cycle-accurate in simulation\n   initial begin\n      if (C_IMPLEMENTATION_TYPE == 2) begin\n         $display(\"WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.\");\n      end else if (C_MEMORY_TYPE == 4) begin\n         $display(\"FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.\");\n         $finish;\n      end\n\n      if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin\n         $display(\"FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.\");\n         $finish;\n      end\n\n      if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin\n         $display(\"FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.\");\n         $finish;\n      end\n\n      if (C_USE_ECC == 1) begin\n         if (C_DIN_WIDTH != C_DOUT_WIDTH) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.\");\n            $finish;\n         end\n         if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.\");\n            $finish;\n         end\n      end\n\n   end //initial\n\n  /**************************************************************************\n  * Internal reset logic\n  **************************************************************************/\n  assign wr_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg|sckt_wr_rst_i : 0;\n  assign rd_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg|sckt_rd_rst_i : 0;\n  assign rst_i            = C_HAS_RST ? rst_reg|sckt_wr_rst_i : 0;\n\n  wire rst_2_sync;\n  wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;\n\n  localparam RST_SYNC_STAGES = C_EN_SAFETY_CKT == 0 ? C_COMMON_CLOCK ? C_SYNCHRONIZER_STAGE : C_SYNCHRONIZER_STAGE+2 : 5;\n  localparam RST_BUSY_LEN    = 4;\n  reg  wr_rst_busy_i = 0;\n  reg  rd_rst_busy_i = 0;\n  generate\n      if (C_ENABLE_RST_SYNC == 0 || (C_HAS_RST == 0 && C_HAS_SRST == 0)) begin : gnrst_sync\n        always @* begin\n          wr_rst_reg <= wr_rst_delayed;\n          rd_rst_reg <= rd_rst_delayed;\n          rst_reg    <= 1'b0;\n          srst_reg    <= 1'b0;\n        end\n        assign rst_2_sync = wr_rst_delayed;\n        assign wr_rst_busy = 1'b0;\n        assign wr_rst_busy_o = 1'b0;\n        assign rd_rst_busy = 1'b0;\n        assign sckt_wr_rst_i = 1'b0;\n        assign sckt_rd_rst_i = 1'b0;\n      end // gnrst_sync\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 0) begin : g7s_ic_rst_nsckt\n        reg [1:0]                 arst_sync_wr  = 2'b11;\n        reg [1:0]                 arst_sync_rd  = 2'b11;\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge WR_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge RD_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_rd    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_rd    <= #`TCQ {arst_sync_rd[0], rst_delayed};\n        end\n        always @(posedge WR_CLK) begin\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n\tend\n        always @(posedge WR_CLK or posedge arst_sync_wr[1]) begin\n\t  if (arst_sync_wr[1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n            rd_rst_wr_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            rd_rst_wr_ext  <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t    if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t      sckt_wr_rst_ic <= #`TCQ 1'b0;\n            else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t      wr_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n        always @(posedge RD_CLK) begin\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], sckt_wr_rst_ic};\n\tend\n        always @(posedge RD_CLK or posedge arst_sync_rd[1]) begin\n\t  if (arst_sync_rd[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n            wr_rst_rd_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            wr_rst_rd_ext  <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t    if (wr_rst_rd_ext[1]) begin\n\t      sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t      rd_rst_busy_i  <= #`TCQ 1'b0;\n\t    end\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic|arst_sync_wr[1];\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic|arst_sync_rd[1];\n      end // g7s_ic_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 1) begin : g7s_ic_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] arst_sync_rd  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        always @(posedge WR_CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n          rd_rst_wr_ext    <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_wr[RST_SYNC_STAGES-1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n          end else if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t    sckt_wr_rst_ic <= #`TCQ 1'b0;\n          else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t    wr_rst_busy_i  <= #`TCQ 1'b0;\n\tend\n        always @(posedge RD_CLK) begin\n\t  arst_sync_rd     <= #`TCQ {arst_sync_rd[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n          wr_rst_rd_ext    <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_rd[RST_SYNC_STAGES-1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n\t  end else if (wr_rst_rd_ext[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t    rd_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic;\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic;\n      end // g7s_ic_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 0) begin : g7s_cc_rst_nsckt\n        reg [1:0]              arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge CLK) begin\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0] | arst_sync_wr[1]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc | arst_sync_wr[1];\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 1) begin : g7s_cc_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n\n        always @(posedge CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc;\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst\n        assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;\n        assign rd_rst_busy = rst_reg;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = rst_reg;\n        always @* rst_full_ff_i  <= 1'b0;\n        always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;\n\n        always @(posedge CLK) begin\n          rst_delayed_d1 <= #`TCQ srst_delayed;\n          rst_delayed_d2 <= #`TCQ rst_delayed_d1;\n          if (rst_reg || rst_delayed_d2) begin\n            rst_active_i <= #`TCQ 1'b1;\n          end else begin\n            rst_active_i <= #`TCQ rst_reg;\n          end    \n        end   \n        always @(posedge CLK) begin\n          if (~rst_reg && srst_delayed) begin\n             rst_reg <= #`TCQ 1'b1;\n           end else if (rst_reg) begin\n             rst_reg <= #`TCQ 1'b0;\n           end else begin\n             rst_reg <= #`TCQ rst_reg;\n           end    \n        end   \n      end // g8s_cc_rst\n      else if (IS_8SERIES != 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_srst\n        assign wr_rst_busy = srst_delayed;\n        assign rd_rst_busy = srst_delayed;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = srst_delayed;\n        always @* rst_full_ff_i  <= 1'b0;\n      end // g7s_cc_srst\n  endgenerate \n\n  reg rst_d1 = 1'b0;\n  reg rst_d2 = 1'b0;\n  reg rst_d3 = 1'b0;\n  reg rst_d4 = 1'b0;\n  generate\n    if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1\n    // RST_FULL_GEN replaces the reset falling edge detection used to de-assert\n    // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.\n\n    // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &\n    // PROG_FULL\n\n      always @ (posedge rst_2_sync or posedge clk_2_sync) begin\n        if (rst_2_sync && C_EN_SAFETY_CKT == 0) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          rst_d3         <= 1'b1;\n          rst_d4         <= 1'b0;\n        end else begin\n          if (srst_delayed) begin\n            rst_d1         <= #`TCQ 1'b1;\n            rst_d2         <= #`TCQ 1'b1;\n            rst_d3         <= #`TCQ 1'b1;\n            rst_d4         <= #`TCQ 1'b0;\n          end else begin\n            rst_d1         <= #`TCQ wr_rst_busy;//1'b0;\n            rst_d2         <= #`TCQ rst_d1;\n            rst_d3         <= #`TCQ rst_d2 | sckt_wr_rst_i;\n            rst_d4         <= #`TCQ rst_d3;\n          end\n        end\n      end\n\n      always @* rst_full_ff_i  <= C_HAS_SRST ? 1'b0 : rst_d2 | sckt_wr_rst_i;\n      always @* rst_full_gen_i <= C_HAS_SRST ? rst_d4 : rst_d3;\n\n    end else if (C_EN_SAFETY_CKT == 1 && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full_sckt\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end\n  endgenerate // grstd1\n\nendmodule //fifo_generator_v13_2_5_CONV_VER\n\n\nmodule fifo_generator_v13_2_5_sync_stage\n  #(\n    parameter  C_WIDTH          = 10\n   )\n   (\n    input                     RST,\n    input                     CLK,\n    input       [C_WIDTH-1:0] DIN,\n    output reg  [C_WIDTH-1:0] DOUT = 0\n   );\n   always @ (posedge RST or posedge CLK) begin\n     if (RST)\n       DOUT <= 0;\n     else\n       DOUT <= #`TCQ DIN;\n   end\nendmodule // fifo_generator_v13_2_5_sync_stage\n\n/*******************************************************************************\n * Declaration of Independent-Clocks FIFO Module\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_as\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2 \n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input                                         SAFETY_CKT_WR_RST,\n   input                                         SAFETY_CKT_RD_RST,\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_ASSERT,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_NEGATE,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_ASSERT,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_NEGATE,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         RD_EN_USER,\n   input                                         RST,\n   input                                         RST_FULL_GEN,\n   input                                         RST_FULL_FF,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   input                                         INJECTDBITERR,\n   input                                         INJECTSBITERR,\n   input                                         USER_EMPTY_FB,\n   input                                         fab_read_data_valid_i,\n   input                                         read_data_valid_i,\n   input                                         ram_valid_i,\n   output reg                                    ALMOST_EMPTY = 1'b1,\n   output reg                                    ALMOST_FULL = C_FULL_FLAGS_RST_VAL,\n   output      [C_DOUT_WIDTH-1:0]                DOUT,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    EMPTY_FB = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL,\n   output                                        OVERFLOW,\n   output                                        PROG_EMPTY,\n   output                                        PROG_FULL,\n   output                                        VALID,\n   output      [C_RD_DATA_COUNT_WIDTH-1:0]       RD_DATA_COUNT,\n   output                                        UNDERFLOW,\n   output                                        WR_ACK,\n   output      [C_WR_DATA_COUNT_WIDTH-1:0]       WR_DATA_COUNT,\n   output                                        SBITERR,\n   output                                        DBITERR\n  );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   \n  \n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   \n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;\n   // Array that holds the error injection type (single/double bit error) on \n   // a specific write operation, which is returned on read to corrupt the\n   // output data.\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   //The amount of data stored in the FIFO at any time is given\n   // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK\n   // domain.\n   //num_wr_bits is calculated by considering the total words in the FIFO,\n   // and the state of the read pointer (which may not have yet crossed clock\n   // domains.)\n   //num_rd_bits is calculated by considering the total words in the FIFO,\n   // and the state of the write pointer (which may not have yet crossed clock\n   // domains.)\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   wire                        wr_rst_i = WR_RST;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n   wire                        rd_rst_i = RD_RST;\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n\n\n\n   // Delayed ram_rd_en is needed only for STD Embedded register option\n   generate\n     if (C_PRELOAD_LATENCY == 2) begin : grd_d\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n       end\n     end\n   endgenerate\n   \n    generate\n     if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n           fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n       end\n     end\n   endgenerate\n\n  \n\n   // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;\n     end else begin : rdl // Read depth lesser than or equal to write depth\n       assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n     end\n   endgenerate\n\n   // Generate Empty and Almost Empty\n  // ram_rd_en used to determine EMPTY should depend on the EMPTY.\n   assign ram_rd_en        = RD_EN & !EMPTY;\n   assign empty_int        = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));\n   assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));\n\n   // Register Empty and Almost Empty\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else begin\n         rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};\n\n         if (empty_int)\n           EMPTY           <= #`TCQ 1'b1;\n         else\n           EMPTY           <= #`TCQ 1'b0;\n\n         if (!EMPTY) begin\n           if (almost_empty_int)\n             ALMOST_EMPTY  <= #`TCQ 1'b1;\n           else\n             ALMOST_EMPTY  <= #`TCQ 1'b0;\n         end\n       end // rd_rst_i\n     end // always\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY_FB     <= 1'b1;\n       end else begin\n         if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else if (empty_int)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else\n           EMPTY_FB   <= #`TCQ 1'b0;\n       end // rd_rst_i\n     end // always\n\n   // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;\n     end else begin : wdl // Write depth lesser than or equal to read depth\n       assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n     end\n   endgenerate\n\n  // Generate FULL and ALMOST_FULL\n  // ram_wr_en used to determine FULL should depend on the FULL.\n  assign ram_wr_en       = WR_EN & !FULL;\n  assign full_int        = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));\n  assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));\n\n   // Register FULL and ALMOST_FULL Empty\n   always @ (posedge WR_CLK or posedge RST_FULL_FF)\n     begin\n       if (RST_FULL_FF & C_HAS_RST) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else begin\n         if (full_int) begin\n           FULL           <= #`TCQ 1'b1;\n         end else begin\n           FULL           <= #`TCQ 1'b0;\n         end\n\n         if (RST_FULL_GEN) begin\n           ALMOST_FULL    <= #`TCQ 1'b0;\n         end else if (!FULL) begin\n           if (almost_full_int)\n             ALMOST_FULL  <= #`TCQ 1'b1;\n           else\n             ALMOST_FULL  <= #`TCQ 1'b0;\n         end\n       end // wr_rst_i\n     end // always\n   always @ (posedge WR_CLK or posedge wr_rst_i)\n     begin\n       if (wr_rst_i) begin\n         wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};\n       end else begin\n         wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};\n       end // wr_rst_i\n     end // always\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i) begin\n           stage1_valid     <= 0;\n           stage2_valid     <= 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n   //Pointers passed into opposite clock domain\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_EMPTY.\n   wire [31:0] num_read_words_pe = \n     num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_FULL.\n   wire [31:0] num_write_words_pf =\n     num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n    \n    \n   /***************************************************************************\n    * Internal registers and wires\n    **************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire [C_DOUT_WIDTH-1:0] ideal_dout_out;      \n   wire valid_i;\n   wire valid_out1;\n   wire valid_out2;\n   wire valid_out;  \n   wire underflow_i;\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]               err_type                 = 0;\n   reg [1:0]               err_type_d1              = 0;\n   reg [1:0]               err_type_both              = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout               = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_d1            = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_both            = 0;\n   reg                     ideal_wr_ack             = 0;\n   reg                     ideal_valid              = 0;\n   reg                     ideal_overflow           = C_OVERFLOW_LOW;\n   reg                     ideal_underflow          = C_UNDERFLOW_LOW;\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   reg         valid_d1     = 0;\n   reg         valid_d2     = 0; \n   \n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n   \n\n  /****************************************************************************\n   * Function Declarations\n   ***************************************************************************/\n\n  /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n      if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n    end\n  endtask\n\n  /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n  /***********************************************************************\n  * hexstr_conv\n  *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n  ***********************************************************************/\n  function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_d2           = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n    end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the \n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n    wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;   \n   wire RD_CLK;\n   wire RD_EN;\n   wire RST;\n   wire WR_CLK;\n   wire WR_EN;\n    */\n\n   //***************************************************************************\n   // Dout may change behavior based on latency\n   //***************************************************************************\n   assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?\n                         ideal_dout_d1: ideal_dout;   \n   assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; \n\n   //***************************************************************************\n   // Assign SBITERR and DBITERR based on latency \n   //***************************************************************************\n   assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                    (C_PRELOAD_LATENCY == 2 &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?\n                    err_type_d1[0]: err_type[0]; \n   assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                    (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                    err_type_d1[1]: err_type[1]; \n  \n   //***************************************************************************\n   // Safety-ckt logic with embedded reg/fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n       //  if (C_HAS_VALID == 1) begin\n       //       assign valid_out = valid_d1;\n       //  end\n             \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)\n          begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else \n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n          end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                  @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n           end\n           else begin\n                   if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                   end\n             end \n           end  \n      end \n      endgenerate   \n\n//***************************************************************************\n   // Safety-ckt logic with embedded reg + fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else begin\n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n               fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n          end\n        end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   ideal_dout_both <= #`TCQ dout_reset_val;\n              end\n           end else begin\n             if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n              \n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n             end\n           end \n         end      \n      end \n      endgenerate    \n \n   //***************************************************************************\n   // Overflow may be active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_OVERFLOW==1) begin : blockOF1\n   assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n      end\n   endgenerate\n\n   assign PROG_EMPTY = ideal_prog_empty;\n   assign PROG_FULL  = ideal_prog_full;\n\n   //***************************************************************************\n   // Valid may change behavior based on latency or active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_VALID==1) begin : blockVL1\n   assign valid_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;\n   assign valid_out1 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?\n                       valid_d1: valid_i;  \n   assign valid_out2 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?\n                       valid_d2: valid_i; \n   assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;\n   assign VALID     = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Underflow may change behavior based on latency or active-low   \n   //***************************************************************************\n   generate\n      if (C_HAS_UNDERFLOW==1) begin : blockUF1\n   assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;\n   assign UNDERFLOW   = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n    end\n   endgenerate\n\n   //***************************************************************************\n   // Write acknowledge may be active low\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_ACK==1) begin : blockWK1\n   assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext\n\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_wr_pntr = 0;\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_rd_pntr = 0;\n      wire [C_PNTR_WIDTH-1:0]  diff_wr_rd_tmp;\n      wire [C_PNTR_WIDTH:0]    diff_wr_rd;\n      reg  [C_PNTR_WIDTH:0]    wr_data_count_i  = 0;\n        always @* begin\n          if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = 0;\n            adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n          end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin\n            adjusted_rd_pntr = rd_pntr_wr;\n            adjusted_wr_pntr = 0;\n            adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n          end else begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = rd_pntr_wr;\n          end\n        end // always @*\n\n        assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;\n        assign diff_wr_rd     = {1'b0,diff_wr_rd_tmp};\n\n        always @ (posedge wr_rst_i or posedge WR_CLK)\n        begin\n            if (wr_rst_i)\n              wr_data_count_i <= 0;\n            else\n              wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;\n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n\n        always @* begin\n          if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];\n          else\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n        end // always @*\n      end // wdc_fwft_ext\n   endgenerate\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   reg  [C_RD_PNTR_WIDTH:0]    rdc_fwft_ext_as  = 0;\n\n   generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n\n\n   always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= 0;\n            end else begin\n              if (!stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 0;\n              else if (!stage1_valid && stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 1;\n              else\n                rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;\n            end \n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n      end // rdc_fwft_ext\n end\n   endgenerate\n\n\n  generate if (C_USE_EMBEDDED_REG == 3) begin\n     if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n        wire [C_RD_PNTR_WIDTH:0]  diff_rd_wr_1;\n   //     assign diff_rd_wr_1 = diff_rd_wr +2'h2;\n\n       always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= #`TCQ 0;\n            end else begin\n          //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))\n          //    rdc_fwft_ext_as <= 1'b0;\n          //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) \n          //    rdc_fwft_ext_as <= 1'b1;\n          //else\n            rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;\n        end\n\n\n\nend\nend\nend\nendgenerate\n          \n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1) begin : grdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?\n          rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :\n          rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?\n          wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :\n          wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n\n  /**************************************************************************\n  * Assorted registers for delayed versions of signals\n  **************************************************************************/\n  //Capture delayed version of valid\n  generate\n      if (C_HAS_VALID==1) begin : blockVL2\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n      valid_d1 <= 1'b0;\n      valid_d2 <= 1'b0;\n    end else begin\n      valid_d1 <= #`TCQ valid_i;\n      valid_d2 <= #`TCQ valid_d1;\n    end \n//    if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin\n  //      valid_d2 <= #`TCQ valid_d1;\n      //  end \n  end \n      end\n endgenerate  \n   \n  //Capture delayed version of dout\n  /**************************************************************************\n    *embedded/fabric reg with no safety ckt\n    **************************************************************************/\n  generate \n       if (C_USE_EMBEDDED_REG < 3) begin\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n       if (C_USE_DOUT_RST == 1'b1) begin\n         @(posedge RD_CLK)\n           ideal_dout_d1   <= #`TCQ dout_reset_val;\n           ideal_dout   <= #`TCQ dout_reset_val;\n       end\n      // Reset err_type only if ECC is not selected\n      if (C_USE_ECC == 0)\n        err_type_d1     <= #`TCQ 0;\n     end else if (ram_rd_en_d1) begin\n      ideal_dout_d1   <= #`TCQ ideal_dout;\n      err_type_d1     <= #`TCQ err_type;\n           end    \n  end  \n   \nend  \nendgenerate \n/**************************************************************************\n    *embedded + fabric reg with no safety ckt\n    **************************************************************************/\n\ngenerate \n  if (C_USE_EMBEDDED_REG == 3) begin\n    always @(posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i == 1'b1) begin\n        if (C_USE_DOUT_RST == 1'b1) begin\n           @(posedge RD_CLK)\n             ideal_dout    <= #`TCQ dout_reset_val;\n             ideal_dout_d1   <= #`TCQ dout_reset_val;\n             ideal_dout_both   <= #`TCQ dout_reset_val;\n        end\n        // Reset err_type only if ECC is not selected\n        if (C_USE_ECC == 0) begin\n          err_type_d1     <= #`TCQ 0;\n          err_type_both   <= #`TCQ 0;\n        end\n      end else begin\n         if (ram_rd_en_d1) begin\n           ideal_dout_both   <= #`TCQ ideal_dout;\n           err_type_both     <= #`TCQ err_type;\n         end    \n         if (fab_rd_en_d1) begin\n           ideal_dout_d1   <= #`TCQ ideal_dout_both;\n           err_type_d1     <= #`TCQ err_type_both;\n         end\n      end\n    end  \n  end  \nendgenerate \n\n  \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate\n     if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n       always @(posedge WR_CLK) begin\n         ideal_overflow    <= #`TCQ WR_EN & FULL;\n       end\n     end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n       always @(posedge WR_CLK) begin\n         //ideal_overflow    <= #`TCQ WR_EN & (FULL | wr_rst_i);\n         ideal_overflow    <= #`TCQ WR_EN & (FULL );\n       end\n     end\n   endgenerate\n\n   generate\n     if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ EMPTY & RD_EN;\n       end\n     end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ (EMPTY) & RD_EN;\n         //ideal_underflow    <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;\n       end\n     end\n   endgenerate\n\n   /**************************************************************************\n   * Write/Read Pointer Synchronization\n   **************************************************************************/\n   localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;\n   wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   genvar gss;\n\n   generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (C_WR_PNTR_WIDTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_i), \n         .CLK      (RD_CLK), \n         .DIN      (wr_pntr_sync_stgs[gss-1]), \n         .DOUT     (wr_pntr_sync_stgs[gss])\n        );\n \n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (C_RD_PNTR_WIDTH)\n        )\n     wr_stg_inst\n        (\n         .RST      (wr_rst_i), \n         .CLK      (WR_CLK), \n         .DIN      (rd_pntr_sync_stgs[gss-1]), \n         .DOUT     (rd_pntr_sync_stgs[gss])\n        );\n   end endgenerate // Sync_stage_inst\n\n   assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;\n   assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;\n   always@* begin\n     wr_pntr_rd           <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n     rd_pntr_wr           <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n   end\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp\n     if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)\n       wr_pntr           <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)\n       wr_pntr           <= #`TCQ 0;\n   end\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (wr_rst_i == 1'b1) begin\n       num_wr_bits       <= 0;\n       next_num_wr_bits   = 0;\n       wr_ptr            <= C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= C_RD_DEPTH - 1;\n       ideal_wr_ack      <= 0;\n       ideal_wr_count    <= 0;\n       tmp_wr_listsize    = 0;\n       rd_ptr_wrclk_next <= 0;\n       wr_pntr_rd1       <= 0;\n\n     end else begin //wr_rst_i==0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       //If this is a write, handle the write by adding the value\n       // to the linked list, and updating all outputs appropriately\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD \n             >= C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full, but reporting full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //With DEPTH-1 words in the FIFO, it is almost_full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n\n           //If the FIFO is completely empty, but it is\n           // reporting FULL for some reason (like reset)\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=\n                C_FIFO_WR_DEPTH-2) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //FIFO is really not close to full, so change flag status.\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n           end //(tmp_wr_listsize == 0)\n\n         end else begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=\n              C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack       <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count     <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;\n\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //This write is CAUSING the FIFO to go full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is 2 from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == \n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits =  next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Still 2 from full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is not close to being full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <\n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //wr_rst_i==0\n   end // gen_fifo_w\n\n\n  /***************************************************************************\n   * Programmable FULL flags\n   ***************************************************************************/\n\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;\n\n   generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;\n   end else begin // STD\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;\n   end endgenerate\n\n   always @(posedge WR_CLK or posedge wr_rst_i) begin\n\n     if (wr_rst_i == 1'b1) begin\n       diff_pntr         <= 0;\n     end else begin\n       if (ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);\n       else if (!ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);\n    end\n  end\n\n\n   always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf\n\n     if (RST_FULL_FF & C_HAS_RST) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else begin\n\n       if (RST_FULL_GEN)\n         ideal_prog_full   <= #`TCQ 0;\n       //Single Programmable Full Constant Threshold\n       else if (C_PROG_FULL_TYPE == 1) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else\n             ideal_prog_full <= #`TCQ 0;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Constant Thresholds\n       end else if (C_PROG_FULL_TYPE == 2) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else if (diff_pntr < pf_thr_negate_val)\n             ideal_prog_full <= #`TCQ 0;\n           else\n             ideal_prog_full <= #`TCQ ideal_prog_full;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Single Programmable Full Threshold Input\n       end else if (C_PROG_FULL_TYPE == 3) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH)\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Threshold Inputs\n       end else if (C_PROG_FULL_TYPE == 4) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH_ASSERT)\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < PROG_FULL_THRESH_NEGATE)\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       end // C_PROG_FULL_TYPE\n\n     end //wr_rst_i==0\n   end //\n\n   \n   /**************************************************************************\n   * Read Domain Logic\n   **************************************************************************/\n\n\n   /*********************************************************\n    * Programmable EMPTY flags\n    *********************************************************/\n   //Determine the Assert and Negate thresholds for Programmable Empty\n\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd      = 0;\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe\n\n     if (rd_rst_i & C_HAS_RST) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else begin\n       if (ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;\n       else if (!ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr);\n       else\n         diff_pntr_rd       <=  #`TCQ diff_pntr_rd;\n  \n       if (C_PROG_EMPTY_TYPE == 1) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 2) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 3) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 4) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end  //C_PROG_EMPTY_TYPE\n     end\n   end // gen_pe\n\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;\n   end endgenerate // single_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;\n   end endgenerate // multiple_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;\n   end endgenerate // single_multiple_pe_thr_const\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp\n     if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n       rd_pntr            <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)\n       rd_pntr            <= #`TCQ 0;\n   end\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rd_rst_i & C_HAS_RST) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n     end else begin //rd_rst_i==0\n\n       rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 1\n       /*****************************************************************/\n       if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Reminder that FIFO is still empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end // if (tmp_rd_listsize <= 0)\n\n             //If the FIFO is one from empty, but it is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 1)\n\n             //If the FIFO is two from empty, and is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Fifo has two words, so is neither empty or almost empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 2)\n\n             //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid <= #`TCQ 1'b0;\n                 //Note that the FIFO is No Longer Empty or Almost Empty\n\n                 ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n               end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n             end // else: if(ideal_empty == 1'b1)\n\n           else //if (ideal_empty == 1'b0)\n             begin\n\n               //If the FIFO is completely full, and we are successfully reading from it\n               if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)\n\n               //If the FIFO is not close to being empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n               //If the FIFO is two from empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Fifo is not yet empty. It is going almost_empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n\n               //If the FIFO is one from empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Note that FIFO is GOING empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 1)\n\n\n               //If the FIFO is completely empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n                 begin\n                   //Do not change the contents of the FIFO\n\n                   //Do not acknowledge the read from empty FIFO\n                   ideal_valid        <= #`TCQ 1'b0;\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize <= 0)\n\n             end // if (ideal_empty == 1'b0)\n\n           end //(RD_EN == 1'b1)\n\n         else //if (RD_EN == 1'b0)\n           begin\n             //If user did not attempt a read, do not give an ack or err\n             ideal_valid          <= #`TCQ 1'b0;\n\n             ideal_rd_count       <= #`TCQ num_read_words_sized_i;\n\n           end // else: !if(RD_EN == 1'b1)\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 0\n       /*****************************************************************/\n       end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty, but it is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty, and is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Fifo has two words, so is neither empty or almost empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                         (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that the FIFO is No Longer Empty or Almost Empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n           end else begin\n\n             //If the FIFO is completely full, and we are successfully reading from it\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is not close to being empty\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                          (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Fifo is not yet empty. It is going almost_empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Note that FIFO is GOING empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is completely empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if (tmp_rd_listsize <= 0)\n\n           end // if (ideal_empty == 1'b0)\n\n         end else begin//(RD_EN == 1'b0)\n\n         \n           //If user did not attempt a read, do not give an ack or err\n           ideal_valid           <= #`TCQ 1'b0;\n           ideal_rd_count        <= #`TCQ num_read_words_sized_i;\n\n         end // else: !if(RD_EN == 1'b1)\n       end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //rd_rst_i==0\n   end //always gen_fifo_r_as\n\nendmodule // fifo_generator_v13_2_5_bhv_ver_as\n\n\n/*******************************************************************************\n * Declaration of Low Latency Asynchronous FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_beh_ver_ll_afifo\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_FIFO_TYPE                    = 0\n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   output reg  [C_DOUT_WIDTH-1:0]                DOUT = 0,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL\n  );\n\n  //-----------------------------------------------------------------------------\n  // Low Latency Asynchronous FIFO\n  //-----------------------------------------------------------------------------\n\n  // Memory which will be used to simulate a FIFO\n  reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n  integer i;\n  initial begin\n    for (i = 0; i < C_WR_DEPTH; i = i + 1)\n      memory[i] = 0;\n  end\n\n  reg  [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;\n  wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;\n  reg  [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;\n  reg                        ll_afifo_full    = 1'b0;\n  reg                        ll_afifo_empty   = 1'b1;\n  wire                       write_allow;\n  wire                       read_allow;\n\n  assign write_allow = WR_EN & ~ll_afifo_full;\n  assign read_allow  = RD_EN & ~ll_afifo_empty;\n\n  //-----------------------------------------------------------------------------\n  // Write Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      wr_pntr_ll_afifo   <= 0;\n    else if (write_allow)\n      wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Read Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      rd_pntr_ll_afifo_q   <= 0;\n    else\n      rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;\n  end\n  assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;\n  \n  //-----------------------------------------------------------------------------\n  // Fill the Memory\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK) begin\n    if (write_allow)\n      memory[wr_pntr_ll_afifo] <= #`TCQ DIN;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate DOUT\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK) begin\n      DOUT <= #`TCQ memory[rd_pntr_ll_afifo];\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate EMPTY\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      ll_afifo_empty   <= 1'b1;\n    else\n      ll_afifo_empty   <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | \n                           (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate FULL\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      ll_afifo_full   <= 1'b1;\n    else\n      ll_afifo_full   <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | \n                           (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));\n  end\n\n  always @* begin\n    FULL  <= ll_afifo_full;\n    EMPTY <= ll_afifo_empty;\n  end\n\nendmodule // fifo_generator_v13_2_5_beh_ver_ll_afifo\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_ss\n   \n  /**************************************************************************\n   * Declare user parameters and their defaults\n   *************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0 \n   )\n   \n  /**************************************************************************\n   * Declare Input and Output Ports\n   *************************************************************************/\n   (\n    //Inputs\n    input                                 SAFETY_CKT_WR_RST,\n    input                                 CLK,\n    input       [C_DIN_WIDTH-1:0]         DIN,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_ASSERT,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_NEGATE,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_ASSERT,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_NEGATE,\n    input                                 RD_EN,\n    input                                 RD_EN_USER,\n    input                                 USER_EMPTY_FB,\n    input                                 RST,\n    input                                 RST_FULL_GEN,\n    input                                 RST_FULL_FF,\n    input                                 SRST,\n    input                                 WR_EN,\n    input                                 INJECTDBITERR,\n    input                                 INJECTSBITERR,\n    input                                 WR_RST_BUSY,\n    input                                 RD_RST_BUSY,\n                                    \n    //Outputs                       \n    output                                ALMOST_EMPTY,\n    output                                ALMOST_FULL,\n    output reg   [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,\n    output       [C_DOUT_WIDTH-1:0]       DOUT,\n    output                                EMPTY,\n    output reg                            EMPTY_FB = 1'b1,\n    output                                FULL,\n    output                                OVERFLOW,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]    RD_DATA_COUNT,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]    WR_DATA_COUNT,\n    output                                PROG_EMPTY,\n    output                                PROG_FULL,\n    output                                VALID,\n    output                                UNDERFLOW,\n    output                                WR_ACK,\n    output                                SBITERR,\n    output                                DBITERR\n   );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;\n   wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n   localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; \n\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n   localparam  EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //localparam  EXTRA_WORDS_PE_PARAM  = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not \n   //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.\n   // Therefore, during SRST, all the FULL flags reset to 0.\n   localparam                      C_HAS_FAST_FIFO = 0;\n   localparam                      C_FIFO_WR_DEPTH = C_WR_DEPTH;\n   localparam                      C_FIFO_RD_DEPTH = C_RD_DEPTH;\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;\n   localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;\n   localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;\n   localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n  localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; \n  localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; \n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   \n   /**************************************************************************\n    * Internal Registers and wires\n    *************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire                           underflow_i;\n   wire                           valid_i;\n   wire                           valid_out;\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_reg = 1'b0;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n   wire                         srst_rrst_busy;\n\n\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]                      err_type           = 0;\n   reg [1:0]                      err_type_d1        = 0;\n   reg [1:0]                      err_type_both      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout         = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_d1      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_both      = 0;\n   wire [C_DOUT_WIDTH-1:0]        ideal_dout_out;\n   wire                           fwft_enabled;\n   reg                            ideal_wr_ack       = 0;\n   reg                            ideal_valid        = 0;\n   reg                            ideal_overflow     = C_OVERFLOW_LOW;\n   reg                            ideal_underflow    = C_UNDERFLOW_LOW;\n\n   reg                            full_i             = C_FULL_FLAGS_RST_VAL;\n   reg                            full_i_temp        = 0;\n   reg                            empty_i            = 1;\n   reg                            almost_full_i      = 0;\n   reg                            almost_empty_i     = 1;\n   reg                            prog_full_i        = 0;\n   reg                            prog_empty_i       = 1;\n   reg [C_WR_PNTR_WIDTH-1:0]      wr_pntr            = 0;\n   reg [C_RD_PNTR_WIDTH-1:0]      rd_pntr            = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg [C_RD_PNTR_WIDTH-1:0]      diff_count         = 0;\n\n   reg                            write_allow_q      = 0;\n   reg                            read_allow_q       = 0;\n   reg                            valid_d1           = 0;\n   reg                            valid_both           = 0;\n   reg                            valid_d2           = 0;\n   wire                           rst_i;\n   wire                           srst_i;\n\n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]         dout_reset_val = 0;\n\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n\n\n\n   /****************************************************************************\n    * Function Declarations\n    ***************************************************************************/\n\n   /****************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***************************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin\n        case (def_data[7:0])\n          8'b00000000 : begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default : begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1) begin\n          if ((index*4)+j < C_DOUT_WIDTH) begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   //reg         valid_d1     = 0;\n   \n   \n   //user specified value for reseting the size of the fifo\n   //reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n\n\n /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n     if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n\n     end\n  endtask\n\n\n   \n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_dout_both    = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_both         = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n\n   end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the\n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n   wire CLK;\n   wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;\n   wire RD_EN;\n   wire RST;\n   wire WR_EN;\n    */\n\n  // Assign ALMOST_EPMTY\n  generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae\n    assign ALMOST_EMPTY = almost_empty_i;\n  end else begin : gnae\n    assign ALMOST_EMPTY = 0;\n  end endgenerate // gae\n\n  // Assign ALMOST_FULL\n  generate if (C_HAS_ALMOST_FULL==1) begin : gaf\n    assign ALMOST_FULL  = almost_full_i;\n  end else begin : gnaf\n    assign ALMOST_FULL  = 0;\n  end endgenerate // gaf\n\n   // Dout may change behavior based on latency\n  localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?\n                         ideal_dout_d1: ideal_dout; \n  assign DOUT = ideal_dout_out;\n\n  // Assign SBITERR and DBITERR based on latency \n  assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[0]: err_type[0]; \n  assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[1]: err_type[1]; \n\n  assign EMPTY         = empty_i;\n  assign FULL          = full_i;\n  //saftey_ckt with one register\n\n  generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)\n          begin\n          if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n              valid_d1 <= #`TCQ 1'b0;\n          end\n          else begin\n               ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n               valid_d1 <= #`TCQ valid_i;\n          end\n          end\n          \n           always@(posedge rst_delayed_sft2 or posedge CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n              end\n           else if (srst_rrst_busy == 1'b1) begin\n                   if (C_USE_DOUT_RST == 1'b1) begin\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   end\n           end else if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                end\n           end   \n      end //if \n      endgenerate   \n\n//safety ckt with both registers\n\ngenerate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK) begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            valid_d1 <= #`TCQ 1'b0;\n          end else begin\n            ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n            fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n            valid_both <= #`TCQ valid_i;\n            valid_d1 <= #`TCQ valid_both;\n          end\n        end\n\n        always@(posedge rst_delayed_sft2 or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                  ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else if (srst_rrst_busy == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else begin \n            if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n            end\n          end\n        end\n      end //if \n      endgenerate    \n \n \n  //Overflow may be active-low\n  generate if (C_HAS_OVERFLOW==1) begin : gof\n    assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n  end else begin : gnof\n    assign OVERFLOW = 0;\n  end endgenerate // gof\n\n  assign PROG_EMPTY    = prog_empty_i;\n  assign PROG_FULL     = prog_full_i;\n\n   //Valid may change behavior based on latency or active-low\n  generate if (C_HAS_VALID==1) begin : gvalid\n    assign valid_i       = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;\n    assign valid_out     = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?\n                            valid_d1 : valid_i; \n    assign VALID         = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n  end else begin : gnvalid\n    assign VALID         = 0;\n  end endgenerate // gvalid\n\n  //Trim data count differently depending on set widths\n  generate if (C_HAS_DATA_COUNT == 1) begin : gdc\n    always @* begin\n      diff_count <= wr_pntr - rd_pntr;\n      if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin\n        DATA_COUNT[C_RD_PNTR_WIDTH-1:0]  <= diff_count;\n        DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; \n      end else begin\n        DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];\n      end\n    end\n//  end else begin : gndc\n//    always @* DATA_COUNT <= 0;\n  end endgenerate // gdc\n\n  //Underflow may change behavior based on latency or active-low\n  generate if (C_HAS_UNDERFLOW==1) begin : guf\n    assign underflow_i   = ideal_underflow;\n    assign UNDERFLOW     = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n  end else begin : gnuf\n    assign UNDERFLOW     = 0;\n  end endgenerate // guf\n \n\n  //Write acknowledge may be active low \n  generate if (C_HAS_WR_ACK==1) begin : gwr_ack\n    assign WR_ACK        = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n  end else begin : gnwr_ack\n    assign WR_ACK        = 0;\n  end endgenerate // gwr_ack\n\n\n  /*****************************************************************************\n   * Internal reset logic \n   ****************************************************************************/\n  assign srst_i        = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;\n  assign rst_i            = C_HAS_RST ? RST : 0;\n  assign srst_wrst_busy   = srst_i;\n  assign srst_rrst_busy   = srst_i;\n\n   /**************************************************************************\n    * Assorted registers for delayed versions of signals\n    **************************************************************************/\n   //Capture delayed version of valid\n   generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20\n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1 <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n           end else begin\n              valid_d1 <= #`TCQ valid_i;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n     end \n   endgenerate // blockVL20\n\n  generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin \n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1   <= 1'b0;\n           valid_both <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n              valid_both <= #`TCQ 1'b0;\n              \n           end else begin\n              valid_both <= #`TCQ valid_i;\n               valid_d1 <= #`TCQ valid_both;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n  end\n endgenerate // blockVL20\n\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge CLK or posedge rst_i) begin\n         if (rst_i) begin\n           stage1_valid     <= #`TCQ 0;\n           stage2_valid     <= #`TCQ 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n\n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc\n       assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc\n       assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n   \n   //reg ram_rd_en_d1 = 1'b0;\n   //Capture delayed version of dout\n   generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         ram_rd_en_d1 <= #`TCQ 1'b0;\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n        end\n      end else begin\n         ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n         if (srst_rrst_busy) begin\n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            // Reset err_type only if ECC is not selected\n            if (C_USE_ECC == 0) begin\n               err_type_d1   <= #`TCQ 0;\n               err_type_both <= #`TCQ 0;\n            end\n            // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n            if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n            end \n         if (C_USE_DOUT_RST == 1) begin\n           // @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         end else begin\n            if (ram_rd_en_d1 ) begin\n            ideal_dout_d1 <= #`TCQ ideal_dout;\n            err_type_d1   <= #`TCQ err_type;\n            end\n         end\n      end    \n   end   // always\nend\nendgenerate \n\n//no safety ckt with both registers\n generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n          ram_rd_en_d1 <= #`TCQ 1'b0;\n          fab_rd_en_d1 <= #`TCQ 1'b0;\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val; \n            \n      end\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val;\n       end\n      end else begin\n         if (srst_rrst_busy) begin \n           ram_rd_en_d1 <= #`TCQ 1'b0;\n           fab_rd_en_d1 <= #`TCQ 1'b0;\n           // Reset err_type only if ECC is not selected\n           if (C_USE_ECC == 0) begin\n              err_type_d1   <= #`TCQ 0;\n              err_type_both <= #`TCQ 0;\n           end\n           // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n           if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n              ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end \n           if (C_USE_DOUT_RST == 1) begin\n             ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end\n         end else begin\n           ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n           fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);\n           if (ram_rd_en_d1 ) begin\n             ideal_dout_both <= #`TCQ ideal_dout;\n             err_type_both   <= #`TCQ err_type;\n           end\n           if (fab_rd_en_d1 ) begin\n             ideal_dout_d1 <= #`TCQ ideal_dout_both;\n             err_type_d1   <= #`TCQ err_type_both;\n           end\n         end\n      end    \n   end   // always\nend\nendgenerate \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n     always @(posedge CLK) begin\n       ideal_overflow    <= #`TCQ WR_EN & full_i;\n     end\n   end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n     always @(posedge CLK) begin\n       //ideal_overflow    <= #`TCQ WR_EN & (rst_i | full_i);\n       ideal_overflow    <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);\n     end\n   end endgenerate // blockOF20\n \n   generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n     always @(posedge CLK) begin\n       ideal_underflow   <= #`TCQ empty_i & RD_EN;\n     end\n   end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n     always @(posedge CLK) begin\n       //ideal_underflow   <= #`TCQ (rst_i | empty_i) & RD_EN;\n       ideal_underflow   <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;\n     end\n   end endgenerate // blockUF20\n\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n\n  /*************************************************************************\n   * Write and Read Logic  \n   ************************************************************************/\n   wire              write_allow;\n   wire              read_allow;\n   wire              read_allow_dc;\n   wire              write_only;\n   wire              read_only;\n   //wire              write_only_q;\n   reg              write_only_q;\n   //wire              read_only_q;\n   reg              read_only_q;\n   reg              full_reg;\n   reg              rst_full_ff_reg1;\n   reg              rst_full_ff_reg2;\n   wire              ram_full_comb;\n   wire              carry;\n   \n   assign write_allow  = WR_EN & ~full_i;\n   assign read_allow   = RD_EN & ~empty_i;\n   assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;\n   //assign write_only   = write_allow & ~read_allow;\n   //assign write_only_q = write_allow_q;\n   //assign read_only    = read_allow    & ~write_allow;\n   //assign read_only_q  = read_allow_q ;\n   wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;\n   wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;\n   wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;\n\n   assign diff_pntr_pe_max = DIFF_MAX_RD;\n   assign diff_pntr_max = DIFF_MAX_WR;\n\n\n\n   generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym\n    assign write_only   = write_allow & ~read_allow;\n    assign read_only    = read_allow    & ~write_allow;\n    end endgenerate\n    generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd\n     assign read_only   = read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;\n     assign write_only    = write_allow    & ~(read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n    generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr\n     assign read_only   = read_allow & ~(write_allow  & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n     assign write_only    = write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;\n    end endgenerate\n\n\n   //-----------------------------------------------------------------------------\n   // Write and Read pointer generation\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       wr_pntr         <= 0;\n       rd_pntr         <= 0;\n     end else begin\n       if (srst_i) begin\n         wr_pntr       <= #`TCQ 0;\n         rd_pntr       <= #`TCQ 0;\n       end else begin\n         if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;\n         if (read_allow)  rd_pntr <= #`TCQ rd_pntr + 1;\n       end\n     end\n   end\n\n   generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout\n   always @(posedge CLK) begin\n     if (write_allow) begin\n       if (ENABLE_ERR_INJECTION == 1)\n         memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};\n       else\n         memory[wr_pntr] <= #`TCQ DIN;\n     end\n   end\n\n   reg  [C_DATA_WIDTH-1:0] dout_tmp_q;\n   reg [C_DATA_WIDTH-1:0] dout_tmp = 0;\n   reg  [C_DATA_WIDTH-1:0] dout_tmp1 = 0;\n   always @(posedge CLK) begin\n     dout_tmp_q <= #`TCQ ideal_dout;\n   end\n\n\n\n     always @* begin\n       if (read_allow)\n         ideal_dout <= memory[rd_pntr];\n       else\n         ideal_dout <= dout_tmp_q;\n     end\n   end endgenerate // gll_dm_dout\n\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   assign ram_rd_en        = RD_EN & !EMPTY;\n\n   //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   generate if (C_FIFO_TYPE != 2) begin : gnll_din\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i == 1'b1) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n\n     end else begin //rst_i==0\n     if (srst_wrst_busy) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n     end else begin//srst_i=0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n         end else begin\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error  \n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           //end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //srst_i==0\n     end //wr_rst_i==0\n   end // gen_fifo_w\n    end endgenerate\n\n   generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout\n     always @(posedge CLK) begin\n       if (rst_i || srst_rrst_busy) begin\n         if (C_USE_DOUT_RST == 1) begin\n           ideal_dout <= #`TCQ dout_reset_val;\n           ideal_dout_both <= #`TCQ dout_reset_val;\n         end\n       end\n     end\n    end endgenerate\n\n\n\n\n   generate if (C_FIFO_TYPE != 2) begin : gnll_dout\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_r\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n\n     end else begin //rd_rst_i==0\n     if (srst_rrst_busy) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets synchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= #`TCQ 0;\n         err_type_both    <= #`TCQ 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n      end //srst_i\n      else begin\n\n       //rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n         if (RD_EN == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end \n           else \n             begin\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n         end\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //s_rst_i==0\n     end //rd_rst_i==0\n   end //always\n  end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate diff_pntr for PROG_FULL generation\n   // Generate diff_pntr_pe for PROG_EMPTY generation\n   //-----------------------------------------------------------------------------\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         write_only_q   <= 1'b0;\n         read_only_q    <= 1'b0;\n         diff_pntr_reg1       <= 0;\n         diff_pntr_pe_reg1    <= 0;\n         diff_pntr_reg2       <= 0;\n         diff_pntr_pe_reg2    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_rrst_busy) begin\n           read_only_q  <= #`TCQ 1'b0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n           diff_pntr_pe_reg2  <= #`TCQ 0;\n          end\n          if (srst_wrst_busy) begin\n           write_only_q <= #`TCQ 1'b0;\n           diff_pntr_reg1     <= #`TCQ 0;\n           diff_pntr_reg2     <= #`TCQ 0;\n          end\n         end else begin\n           write_only_q <= #`TCQ write_only;\n           read_only_q  <= #`TCQ read_only;\n           diff_pntr_reg2  <= #`TCQ diff_pntr_reg1;\n           diff_pntr_pe_reg2  <= #`TCQ diff_pntr_pe_reg1;\n\n           // Add 1 to the difference pointer value when only write happens.\n           if (write_only)  \n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;\n           else\n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;\n\n           // Add 1 to the difference pointer value when write or both write & read or no write & read happen.\n           if (read_only)  \n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;\n           else\n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;\n         end\n       end\n     end\n   assign diff_pntr_pe = diff_pntr_pe_reg1;\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow\n\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym\n    assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};\n    assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         diff_pntr_pe_asym    <= 0;\n         diff_pntr_reg1       <= 0;\n         full_reg             <= 0;\n         rst_full_ff_reg1     <= 1;\n         rst_full_ff_reg2     <= 1;\n         diff_pntr_pe_reg1    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_wrst_busy)\n           diff_pntr_reg1     <= #`TCQ 0;\n          if (srst_rrst_busy)\n           full_reg             <=  #`TCQ 0;\n           rst_full_ff_reg1     <=  #`TCQ 1;\n           rst_full_ff_reg2     <=  #`TCQ 1;\n           diff_pntr_pe_asym    <=  #`TCQ 0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n         end else begin\n             diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;\n             full_reg          <= #`TCQ full_i;\n             rst_full_ff_reg1  <=  #`TCQ RST_FULL_FF;\n             rst_full_ff_reg2  <=  #`TCQ rst_full_ff_reg1;\n           if (~full_i) begin  \n             diff_pntr_reg1 <=  #`TCQ wr_pntr - adj_rd_pntr_wr;\n          end\n         end\n       end\n     end\n   assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));\n   assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow_asym\n\n\n   //-----------------------------------------------------------------------------\n   // Generate FULL flag\n   //-----------------------------------------------------------------------------\n   wire                 comp0;\n   wire                 comp1;\n   wire                 going_full;\n   wire                 leaving_full;\n \n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin :  gpad \t\n    assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;\n    assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin :  gtrim \n    assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n  end endgenerate\n\n   assign comp1         = (adj_rd_pntr_wr == (wr_pntr + 1'b1));\n   assign comp0         = (adj_rd_pntr_wr == wr_pntr);\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp\n     assign going_full    = (comp1 & write_allow & ~read_allow);\n     assign leaving_full  = (comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym\n      assign going_full = (comp1 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_full = (comp0 & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp \n      assign going_full = (comp1 & write_allow & ~read_allow);\n      assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n\n   assign ram_full_comb = going_full | (~leaving_full & full_i);\n\n   generate if (C_HAS_RST == 1) begin : grst_full\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF & C_HAS_RST)\n         full_i   <= C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_SRST == 1) begin : gsrst_full\n     always @(posedge CLK) begin\n       if (srst_wrst_busy)\n         full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_full\n     always @(posedge CLK) begin\n         full_i   <= #`TCQ ram_full_comb;\n     end\n   end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate EMPTY flag\n   //-----------------------------------------------------------------------------\n   wire                 ecomp0;\n   wire                 ecomp1;\n   wire                 going_empty;\n   wire                 leaving_empty;\n   wire                 ram_empty_comb;\n\n  \n generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin :  pad \t\n    assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n    assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin :  trim \n    assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n  end endgenerate\n\n   assign ecomp1         = (adj_wr_pntr_rd == (rd_pntr + 1'b1));\n   assign ecomp0         = (adj_wr_pntr_rd == rd_pntr);\n\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp\n     assign going_empty    = (ecomp1 & ~write_allow & read_allow);\n     assign leaving_empty  = (ecomp0 & write_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp\n      assign going_empty = (ecomp1 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_empty = (ecomp0 & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp \n      assign going_empty = (ecomp1 & ~write_allow & read_allow);\n      assign leaving_empty =(ecomp0 & write_allow);\n    end endgenerate\n\n\n\n    assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);\n\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       empty_i  <= 1'b1;\n     else if (srst_rrst_busy)\n       empty_i  <= #`TCQ 1'b1;\n     else\n       empty_i  <= #`TCQ ram_empty_comb;\n    end\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       EMPTY_FB     <= 1'b1;\n     end else begin\n       if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))\n         EMPTY_FB   <= #`TCQ 1'b1;\n       else\n         EMPTY_FB   <= #`TCQ ram_empty_comb;\n     end\n   end // always\n\n   //-----------------------------------------------------------------------------\n   // Generate Read and write data counts for asymmetic common clock\n   //-----------------------------------------------------------------------------\n\n    reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; \n    wire [C_GRTR_PNTR_WIDTH :0] ratio; \n    wire decr_by_one;\n    wire incr_by_ratio;\n    wire incr_by_one;\n    wire decr_by_ratio;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n\n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr \n      assign ratio         = C_DEPTH_RATIO_RD;\n      assign decr_by_one   = (IS_FWFT == 1)? read_allow_dc : read_allow;\n      assign incr_by_ratio = write_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (decr_by_one) begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc - 1;\n           else\n\t    count_dc <= #`TCQ count_dc - 1  + ratio ;\n\t end\n\t else begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc + ratio ;\n\tend\n       end\n       end\n\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n\n    end endgenerate\n\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd \n      assign ratio         = C_DEPTH_RATIO_WR;\n      assign incr_by_one   = write_allow;\n      assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (incr_by_one) begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc + 1;\n           else\n\t    count_dc <= #`TCQ count_dc + 1  - ratio ;\n\t end\n\t else begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc - ratio ;\n\tend\n       end\n       end\n\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n\n    end endgenerate\n\n\n\n\n\n\n   //-----------------------------------------------------------------------------\n   // Generate WR_ACK flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_wr_ack  <= 1'b0;\n     else if (srst_wrst_busy)\n       ideal_wr_ack  <= #`TCQ 1'b0;\n     else if (WR_EN & ~full_i)\n       ideal_wr_ack  <= #`TCQ 1'b1;\n     else\n       ideal_wr_ack  <= #`TCQ 1'b0;\n    end\n\n   //-----------------------------------------------------------------------------\n   // Generate VALID flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_valid  <= 1'b0;\n     else if (srst_rrst_busy)\n       ideal_valid  <= #`TCQ 1'b0;\n     else if (RD_EN & ~empty_i)\n       ideal_valid  <= #`TCQ 1'b1;\n     else\n       ideal_valid  <= #`TCQ 1'b0;\n    end\n\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_FULL flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss\n\n     wire                 fcomp2;\n     wire                 going_afull;\n     wire                 leaving_afull;\n     wire                 ram_afull_comb;\n\n\n   assign fcomp2         = (adj_rd_pntr_wr == (wr_pntr + 2'h2));\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp\n     assign going_afull    = (fcomp2 & write_allow & ~read_allow);\n     assign leaving_afull  = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym\n      assign going_afull = (fcomp2 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_afull = (comp1 & (~write_allow) & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp \n      assign going_afull = (fcomp2 & write_allow & ~read_allow);\n      assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n     assign ram_afull_comb  = going_afull | (~leaving_afull & almost_full_i);\n\n\n    generate if (C_HAS_RST == 1) begin : grst_afull\n      always @(posedge CLK or posedge RST_FULL_FF) begin\n        if (RST_FULL_FF & C_HAS_RST)\n          almost_full_i   <= C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_SRST == 1) begin : gsrst_afull\n      always @(posedge CLK) begin\n        if (srst_wrst_busy)\n          almost_full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_afull\n      always @(posedge CLK) begin\n          almost_full_i   <= #`TCQ ram_afull_comb;\n      end\n    end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_EMPTY flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss\n\n     wire                 ecomp2;\n     wire                 going_aempty;\n     wire                 leaving_aempty;\n     wire                 ram_aempty_comb;\n      \n     assign ecomp2          = (adj_wr_pntr_rd == (rd_pntr + 2'h2));\n   \n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp\n     assign going_aempty    = (ecomp2 & ~write_allow & read_allow);\n     assign leaving_aempty  = (ecomp1 & write_allow & ~read_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp\n      assign going_aempty = (ecomp2 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp \n      assign going_aempty = (ecomp2 & ~write_allow & read_allow);\n      assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);\n    end endgenerate\n\n\n     assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);\n\n     always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         almost_empty_i  <= 1'b1;\n       else if (srst_rrst_busy)\n         almost_empty_i  <= #`TCQ 1'b1;\n       else\n         almost_empty_i  <= #`TCQ ram_aempty_comb;\n      end\n  // end endgenerate // gae_ss\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL\n   //-----------------------------------------------------------------------------\n\n   localparam  C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT \n                                  C_PROG_FULL_THRESH_ASSERT_VAL; // STD\n   localparam  C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT\n                                  C_PROG_FULL_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;   \n   generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin \n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n          prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr>= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  ((diff_pntr) < C_PF_ASSERT_VAL )\n        prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate // single_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr >= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n       else if  (diff_pntr < C_PF_NEGATE_VAL)\n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate //multiple_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT\n                                               PROG_FULL_THRESH; // STD\n   generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input\n\n     always @(posedge CLK or posedge RST_FULL_FF) begin//0\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin //1\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin//2 \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin//3\n           if (diff_pntr > pf3_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if (diff_pntr == pf3_assert_val) begin//4\n             if (read_only_q)\n               prog_full_i <= #`TCQ 1'b0;\n             else\n               prog_full_i <= #`TCQ 1'b1;\n           end else//4\n             prog_full_i <= #`TCQ 1'b0;\n         end else//3\n           prog_full_i <= #`TCQ prog_full_i;\n       end //2\n       else begin//5\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin//6 \n        if (diff_pntr >= pf3_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  (diff_pntr < pf3_assert_val) begin//7\n         prog_full_i <= #`TCQ 1'b0;\n       end//7\n       end//6\n      else\n           prog_full_i <= #`TCQ prog_full_i;\n       end//5\n     end//1\n     end//0\n   end endgenerate //single_pf_input\n  \n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_ASSERT; // STD\n   wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_NEGATE; // STD\n\n   generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin\n           if (diff_pntr >= pf_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if ((diff_pntr == pf_negate_val && read_only_q) ||\n                  diff_pntr < pf_negate_val)\n             prog_full_i <= #`TCQ 1'b0;\n           else\n             prog_full_i <= #`TCQ prog_full_i;\n         end else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin \n        if (diff_pntr >= pf_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n       else if (diff_pntr < pf_negate_val) \n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n\n     end\n   end\n   end endgenerate //multiple_pf_inputs\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY\n   //-----------------------------------------------------------------------------\n   localparam  C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD\n   localparam  C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i) \n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy) \n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL)\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > C_PE_ASSERT_VAL)\n         prog_empty_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n     end\n     end\n   end endgenerate // single_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > C_PE_NEGATE_VAL) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n\n     end\n\n     end\n   end endgenerate //multiple_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH -2) : // FWFT\n                                                PROG_EMPTY_THRESH; // STD\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe < pe3_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (diff_pntr_pe == pe3_assert_val) begin\n             if (write_only_q)\n               prog_empty_i <= #`TCQ 1'b0;\n             else\n               prog_empty_i <= #`TCQ 1'b1;\n           end else\n             prog_empty_i <= #`TCQ 1'b0;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe3_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > pe3_assert_val)\n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n\n     end\n   end endgenerate // single_pe_input\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_ASSERT; // STD\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_NEGATE; // STD\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n      else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe <= pe4_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || \n                     (diff_pntr_pe > pe4_negate_val)) begin\n             prog_empty_i <= #`TCQ 1'b0;\n           end else\n             prog_empty_i <= #`TCQ prog_empty_i;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe4_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > pe4_negate_val) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n     end\n   end endgenerate // multiple_pe_inputs\n\nendmodule // fifo_generator_v13_2_5_bhv_ver_ss\n\n\n\n/**************************************************************************\n * First-Word Fall-Through module (preload 0)\n **************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_preload0\n  #(\n    parameter  C_DOUT_RST_VAL            = \"\",\n    parameter  C_DOUT_WIDTH              = 8,\n    parameter  C_HAS_RST                 = 0,\n    parameter  C_ENABLE_RST_SYNC         = 0,\n    parameter  C_HAS_SRST                = 0,\n    parameter  C_USE_EMBEDDED_REG        = 0,\n    parameter  C_EN_SAFETY_CKT           = 0, \n    parameter  C_USE_DOUT_RST            = 0,\n    parameter  C_USE_ECC                 = 0,\n    parameter  C_USERVALID_LOW           = 0,\n    parameter  C_USERUNDERFLOW_LOW       = 0,\n    parameter  C_MEMORY_TYPE             = 0,\n    parameter  C_FIFO_TYPE               = 0\n  )\n  (\n    //Inputs\n    input                          SAFETY_CKT_RD_RST,\n    input                          RD_CLK,\n    input                          RD_RST,\n    input                          SRST,\n    input                          WR_RST_BUSY,\n    input                          RD_RST_BUSY,\n    input                          RD_EN,\n    input                          FIFOEMPTY,\n    input       [C_DOUT_WIDTH-1:0] FIFODATA,\n    input                          FIFOSBITERR,\n    input                          FIFODBITERR,\n   \n    //Outputs\n    output reg  [C_DOUT_WIDTH-1:0] USERDATA,\n    output                         USERVALID,\n    output                         USERUNDERFLOW,\n    output                         USEREMPTY,\n    output                         USERALMOSTEMPTY,\n    output                         RAMVALID,\n    output                         FIFORDEN,\n    output reg                     USERSBITERR,\n    output reg                     USERDBITERR,\n    output reg                     STAGE2_REG_EN,\n    output                         fab_read_data_valid_i_o,\n    output                         read_data_valid_i_o,\n    output                         ram_valid_i_o,\n    output      [1:0]              VALID_STAGES \n  );\n //Internal signals\n wire                      preloadstage1;\n wire                      preloadstage2;\n reg                       ram_valid_i;\n reg                       fab_valid;\n reg                       read_data_valid_i;\n reg                       fab_read_data_valid_i;\n reg                       fab_read_data_valid_i_1;\n reg                       ram_valid_i_d;\n reg                       read_data_valid_i_d;\n reg                       fab_read_data_valid_i_d;\n wire                      ram_regout_en;\n reg                       ram_regout_en_d1;\n reg                       ram_regout_en_d2;\n wire                      fab_regout_en;\n wire                      ram_rd_en;\n reg                       empty_i        = 1'b1;\n reg                       empty_sckt     = 1'b1;\n reg                       sckt_rrst_q    = 1'b0;\n reg                       sckt_rrst_done = 1'b0;\n reg                       empty_q        = 1'b1;\n reg                       rd_en_q        = 1'b0;\n reg                       almost_empty_i = 1'b1;\n reg                       almost_empty_q = 1'b1;\n wire                      rd_rst_i;\n wire                      srst_i;\n reg  [C_DOUT_WIDTH-1:0]   userdata_both;\n wire                      uservalid_both;\n wire                      uservalid_one;\n reg                       user_sbiterr_both = 1'b0;\n reg                       user_dbiterr_both = 1'b0;\n  \nassign ram_valid_i_o = ram_valid_i;\nassign read_data_valid_i_o = read_data_valid_i;\nassign fab_read_data_valid_i_o = fab_read_data_valid_i; \n\n\n\n/*************************************************************************\n* FUNCTIONS\n*************************************************************************/\n\n   /*************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***********************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n   \n   //*************************************************************************\n   //  Set power-on states for regs\n   //*************************************************************************\n   initial begin\n      ram_valid_i       = 1'b0;\n      fab_valid         = 1'b0;\n      read_data_valid_i = 1'b0;\n      fab_read_data_valid_i = 1'b0;\n      fab_read_data_valid_i_1 = 1'b0;\n      USERDATA          = hexstr_conv(C_DOUT_RST_VAL);\n      userdata_both          = hexstr_conv(C_DOUT_RST_VAL);\n      USERSBITERR       = 1'b0;\n      USERDBITERR       = 1'b0;\n      user_sbiterr_both = 1'b0;\n      user_dbiterr_both = 1'b0;\n   end //initial\n\n   //***************************************************************************\n   //  connect up optional reset\n   //***************************************************************************\n   assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;\n   assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;\n\n   reg  sckt_rd_rst_fwft = 1'b0;\n   reg  fwft_rst_done_i  = 1'b0;\n   wire fwft_rst_done;\n   assign fwft_rst_done = 1'b1;//C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;\n   always @ (posedge RD_CLK) begin\n     sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;\n   end\n\n   always @ (posedge rd_rst_i or posedge RD_CLK) begin\n     if (rd_rst_i)\n       fwft_rst_done_i  <= 1'b0;\n     else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)\n       fwft_rst_done_i  <= #`TCQ 1'b1;\n   end\n\n   localparam INVALID             = 0;\n   localparam STAGE1_VALID        = 2;\n   localparam STAGE2_VALID        = 1;\n   localparam BOTH_STAGES_VALID   = 3;\n\n   reg  [1:0] curr_fwft_state = INVALID;\n   reg  [1:0] next_fwft_state = INVALID;\n\n\ngenerate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin\n         always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n \n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n     \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n    \n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = preloadstage2;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;\n   end\nendgenerate // gnll_fifo\n\n   reg curr_state         = 0;\n   reg next_state         = 0;\n   reg leaving_empty_fwft = 0;\n   reg going_empty_fwft   = 0;\n   reg empty_i_q          = 0;\n   reg ram_rd_en_fwft     = 0;\n   generate if (C_FIFO_TYPE == 2) begin : gll_fifo\n     always @* begin // FSM fo FWFT\n       case (curr_state)\n         1'b0: begin\n           if (~FIFOEMPTY)\n             next_state <= 1'b1;\n           else\n             next_state <= 1'b0;\n           end\n         1'b1: begin\n           if (FIFOEMPTY && RD_EN)\n             next_state <= 1'b0;\n           else\n             next_state <= 1'b1;\n           end\n         default: next_state <= 1'b0;\n       endcase\n     end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_i       <= 1'b1;\n           empty_i_q     <= 1'b1;\n           ram_valid_i   <= 1'b0;\n        end else if (srst_i) begin\n           empty_i       <= #`TCQ 1'b1;\n           empty_i_q     <= #`TCQ 1'b1;\n           ram_valid_i   <= #`TCQ 1'b0;\n        end else begin\n           empty_i       <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);\n           empty_i_q     <= #`TCQ FIFOEMPTY;\n           ram_valid_i   <= #`TCQ next_state;\n        end\n     end //always\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n           curr_state    <= 1'b0;\n        end else if (srst_i) begin\n           curr_state    <= #`TCQ 1'b0;\n        end else begin\n           curr_state    <= #`TCQ next_state;\n        end\n     end //always\n\n     wire                  fe_of_empty; \n     assign fe_of_empty   = empty_i_q & ~FIFOEMPTY;\n\n     always @* begin // Finding leaving empty\n       case (curr_state)\n         1'b0:    leaving_empty_fwft <= fe_of_empty;\n         1'b1:    leaving_empty_fwft <= 1'b1;\n         default: leaving_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Finding going empty\n       case (curr_state)\n         1'b1:    going_empty_fwft <= FIFOEMPTY & RD_EN;\n         default: going_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Generating FWFT rd_en\n       case (curr_state)\n         1'b0:    ram_rd_en_fwft <= ~FIFOEMPTY;\n         1'b1:    ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;\n         default: ram_rd_en_fwft <= 1'b0;\n       endcase\n     end\n\n     assign ram_regout_en = ram_rd_en_fwft;\n     //assign ram_regout_en_d1 = ram_rd_en_fwft;\n     //assign ram_regout_en_d2 = ram_rd_en_fwft;\n     assign ram_rd_en     = ram_rd_en_fwft;\n   end endgenerate // gll_fifo\n\n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false.\n   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n   generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           ram_valid_i     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              ram_valid_i     <= #`TCQ 1'b0;\n           end else begin\n              if (ram_rd_en == 1'b1) begin\n                 ram_valid_i   <= #`TCQ 1'b1;\n              end else begin\n                 if (ram_regout_en == 1'b1)\n                   ram_valid_i <= #`TCQ 1'b0;\n                 else\n                   ram_valid_i <= #`TCQ ram_valid_i;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_ram_valid\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n  \n generate if(C_USE_EMBEDDED_REG < 3) begin\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else\n        read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);\n   end //always\nend \nendgenerate\n\n   \n   \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n generate if ( C_USE_EMBEDDED_REG < 3) begin\n  always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin         // asynchronous reset (active high)\n             almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ FIFOEMPTY;\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n   \n   \n     \n  // BRAM resets synchronously\n generate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin\n   always @ ( posedge rd_rst_i)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n           @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n             USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end  else if (fwft_rst_done) begin\n            if (ram_regout_en) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end\n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n//safety ckt with one register\ngenerate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n            @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n        end\n     end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n          //@(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end \n       end\n        else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n            //  @(posedge RD_CLK)\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end else if (fwft_rst_done) begin\n            if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end          \n          end\n        end\n       end //always\n  end //if\nendgenerate\n\n\ngenerate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin\n         \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d1 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d1 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d1 <= #`TCQ ram_regout_en;\n                 end\n            end //always\n   //  assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));\n       assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d2 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d2 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;\n                 end\n            end //always\n\n    \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n     always @ (posedge RD_CLK) begin\n        ram_valid_i_d <= #`TCQ ram_valid_i;\n        read_data_valid_i_d <= #`TCQ read_data_valid_i;\n        fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;\n\n     end\n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n    \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;\n   end\n   endgenerate // gnll_fifo\n\n   \n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n     generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid\n\n     \n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           fab_valid     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              fab_valid    <= #`TCQ 1'b0;\n           end else begin\n              if (ram_regout_en == 1'b1) begin\n                 fab_valid  <= #`TCQ 1'b1;\n              end else begin\n                 if (fab_regout_en == 1'b1)\n                   fab_valid <= #`TCQ 1'b0;\n                 else\n                   fab_valid <= #`TCQ fab_valid;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_fab_valid\n\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n    generate if(C_USE_EMBEDDED_REG == 3) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else begin\n        if (ram_regout_en == 1'b1) begin\n          read_data_valid_i <= #`TCQ 1'b1;\n        end else begin\n         if (fab_regout_en == 1'b1)\n          read_data_valid_i <= #`TCQ 1'b0;\n        else\n          read_data_valid_i <= #`TCQ read_data_valid_i;\n        end \n      end \n   end //always\nend\nendgenerate\n\n//generate if(C_USE_EMBEDDED_REG == 3) begin\n//   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n//      if (rd_rst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//      else if (srst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//\n//      if (ram_regout_en == 1'b1) begin\n//        fab_read_data_valid_i <= #`TCQ 1'b0;\n//      end else begin\n//       if (fab_regout_en == 1'b1)\n//        fab_read_data_valid_i <= #`TCQ 1'b1;\n//      else\n//        fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;\n//      end \n//   end //always\n//end\n//endgenerate\n\n     generate if(C_USE_EMBEDDED_REG == 3 ) begin \n    always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid\n      if (rd_rst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else \n        fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);\n   end //always\nend\nendgenerate\n \nalways @ (posedge RD_CLK ) begin : proc_del1\n             begin\n                 fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;\n              end\n            end //always\n \n \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty_both\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n   reg FIFOEMPTY_1;\n   generate if (C_USE_EMBEDDED_REG == 3 ) begin\n    always @(posedge RD_CLK) begin\n            FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;\n           end\n    end\nendgenerate\n    generate if (C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n   begin\n      if (rd_rst_i) begin         // asynchronous reset (active high)\n           almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ (~ram_valid_i);\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_sckt <= #`TCQ 1'b1;\n           sckt_rrst_q <= #`TCQ 1'b0;\n           sckt_rrst_done <= #`TCQ 1'b0;\n        end else begin\n           sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;\n           if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin\n              sckt_rrst_done <= #`TCQ 1'b1;\n           end else if (sckt_rrst_done) begin\n              // rising clock edge\n              empty_sckt <= #`TCQ 1'b0;\n           end\n        end\n     end //always\n   \n   \n//   assign USEREMPTY       = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;\n   assign USEREMPTY       = empty_i;\n   assign USERALMOSTEMPTY = almost_empty_i;\n   assign FIFORDEN        = ram_rd_en;\n   assign RAMVALID        = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;\n   assign uservalid_both       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3)  ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);\n   assign uservalid_one       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3)  ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);\n   assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;\n   assign USERUNDERFLOW   = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;\n//no safety ckt with both reg\ngenerate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n            USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              userdata_both   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end else begin\n            if (fwft_rst_done) begin\n              if (ram_regout_en) begin\n                 userdata_both     <= #`TCQ FIFODATA; \n                 user_dbiterr_both <= #`TCQ FIFODBITERR;\n                 user_sbiterr_both <= #`TCQ FIFOSBITERR; \n              end\n              if (fab_regout_en) begin\n                 USERDATA     <= #`TCQ userdata_both;\n                 USERDBITERR  <= #`TCQ user_dbiterr_both;\n                 USERSBITERR  <= #`TCQ user_sbiterr_both; \n              end             \n            end             \n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n\n//safety_ckt with both registers\n generate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always @ (posedge RD_CLK) begin\n          if (rd_rst_i || srst_i) begin\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n              @(posedge RD_CLK)\n              USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n               userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end\n        end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n     if (rd_rst_i) begin //asynchronous reset (active high)\n       if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n         USERSBITERR       <= #`TCQ 0;\n         USERDBITERR       <= #`TCQ 0;\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end\n       // DRAM resets asynchronously\n       if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n         USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end \n     end else begin // rising clock edge\n       if (srst_i) begin\n         if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n           USERSBITERR       <= #`TCQ 0;\n           USERDBITERR       <= #`TCQ 0;\n           user_sbiterr_both <= #`TCQ 0;\n           user_dbiterr_both <= #`TCQ 0;\n         end\n         if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n           USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end\n       end else if (fwft_rst_done) begin\n         if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            userdata_both     <= #`TCQ FIFODATA;\n            user_dbiterr_both <= #`TCQ FIFODBITERR;\n            user_sbiterr_both <= #`TCQ FIFOSBITERR; \n         end\n         if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            USERDATA          <= #`TCQ userdata_both;\n            USERDBITERR       <= #`TCQ user_dbiterr_both;\n            USERSBITERR       <= #`TCQ user_sbiterr_both;\n         end\n       end\n     end\n   end //always\n  end //if\nendgenerate\n\nendmodule //fifo_generator_v13_2_5_bhv_ver_preload0\n\n\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Register one AXI channel on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   reg_slice\n//\n//--------------------------------------------------------------------------\n\nmodule fifo_generator_v13_2_5_axic_reg_slice #\n  (\n   parameter C_FAMILY     = \"virtex7\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   )\n  (\n   // System Signals\n   input  wire                      ACLK,\n   input  wire                      ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0]   S_PAYLOAD_DATA,\n   input  wire                      S_VALID,\n   output wire                      S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0]   M_PAYLOAD_DATA,\n   output wire                      M_VALID,\n   input  wire                      M_READY\n   );\n\n  localparam RST_SYNC_STAGES = 5;\n  localparam RST_BUSY_LEN    = 6;\n  reg [1:0] arst_sync_wr  = 2'b11;\n  reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n  wire sync_reset;\n  wire extnd_reset;\n\n\n  always @(posedge ARESET or posedge ACLK) begin\n    if (ARESET)\n      arst_sync_wr <= 2'b11;\n    else\n      arst_sync_wr <= #`TCQ {arst_sync_wr[0], 1'b0};\n  end\n\n  always @(posedge ACLK) begin\n    sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[1]};\n  end\n\n  assign sync_reset     = |sckt_wr_rst_cc[RST_BUSY_LEN-5:0] | arst_sync_wr[1]; \n  assign extnd_reset    = |sckt_wr_rst_cc | arst_sync_wr[1];\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000)\n    begin\n      reg [1:0] state;\n      localparam [1:0] \n        ZERO = 2'b10,\n        ONE  = 2'b11,\n        TWO  = 2'b01;\n      \n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg [C_DATA_WIDTH-1:0] storage_data2 = 0;\n      reg                    load_s1;\n      wire                   load_s2;\n      wire                   load_s1_from_s2;\n      reg                    s_ready_i; //local signal of output\n      wire                   m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with either slave side data or from storage2\n      always @(posedge ACLK) \n      begin\n        if (load_s1)\n          if (load_s1_from_s2)\n            storage_data1 <= storage_data2;\n          else\n            storage_data1 <= S_PAYLOAD_DATA;        \n      end\n\n      // Load storage2 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data1;\n\n      // Always load s2 on a valid transaction even if it's unnecessary\n      assign load_s2 = S_VALID & s_ready_i;\n\n      // Loading s1\n      always @ *\n      begin\n        if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction\n             // Load when ONE if we both have read and write at the same time\n             ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||\n             // Load when TWO and we have a transaction on Master side\n             ((state == TWO) && (M_READY == 1)))\n          load_s1 = 1'b1;\n        else\n          load_s1 = 1'b0;\n      end // always @ *\n\n      assign load_s1_from_s2 = (state == TWO);\n                       \n      // State Machine for handling output signals\n      always @(posedge ACLK) begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          state <= ZERO;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          case (state)\n            // No transaction stored locally\n            ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE\n\n            // One transaction stored locally\n            ONE: begin\n              if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO\n              if (~M_READY & S_VALID) begin\n                state <= TWO;  // Got another one so move to TWO\n                s_ready_i <= 1'b0;\n              end\n            end\n\n            // TWO transaction stored locally\n            TWO: if (M_READY) begin\n              state <= ONE; // Read out one so move to ONE\n              s_ready_i <= 1'b1;\n            end\n          endcase // case (state)\n        end\n      end // always @ (posedge ACLK)\n      \n      assign m_valid_i = state[0];\n\n    end // if (C_REG_CONFIG == 1)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000001)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg                    s_ready_i; //local signal of output\n      reg                    m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b0;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else if (m_valid_i & M_READY) begin\n          s_ready_i <= 1'b1;\n          m_valid_i <= 1'b0;\n        end else if (S_VALID & s_ready_i) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b1;\n        end\n        if (~m_valid_i) begin\n          storage_data1 <= S_PAYLOAD_DATA;        \n        end\n      end\n      assign M_PAYLOAD_DATA = storage_data1;\n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // reg_slice\n", "num_lines": 10520}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1\n// IP Revision: 21\n\n(* X_CORE_INFO = \"axi_clock_converter_v2_1_21_axi_clock_converter,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"axi_clock_converter_512,axi_clock_converter_v2_1_21_axi_clock_converter,{}\" *)\n(* CORE_GENERATION_INFO = \"axi_clock_converter_512,axi_clock_converter_v2_1_21_axi_clock_converter,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_clock_converter,x_ipVersion=2.1,x_ipCoreRevision=21,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_ID_WIDTH=16,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=1,C_AXI_PROTOCOL=0,C_AXI_SUPPORTS_USER_SIGNALS=1,C_AXI_AWUSER_WIDTH=8,C_AXI_ARUSER_WIDTH=8,C_AXI_WUSER_WIDTH=1,C_A\\\nXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_SYNCHRONIZER_STAGE=2}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_clock_converter_512 (\n  s_axi_aclk,\n  s_axi_aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awuser,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_aruser,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_aclk,\n  m_axi_aresetn,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awuser,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_aruser,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_CLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 SI_CLK CLK\" *)\ninput wire s_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 SI_RST RST\" *)\ninput wire s_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWUSER\" *)\ninput wire [7 : 0] s_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARUSER\" *)\ninput wire [7 : 0] s_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 8, ARUSER_WIDTH 8, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_CLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 MI_CLK CLK\" *)\ninput wire m_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 MI_RST RST\" *)\ninput wire m_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWUSER\" *)\noutput wire [7 : 0] m_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARUSER\" *)\noutput wire [7 : 0] m_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 8, ARUSER_WIDTH 8, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_clock_converter_v2_1_21_axi_clock_converter #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_S_AXI_ACLK_RATIO(1),\n    .C_M_AXI_ACLK_RATIO(2),\n    .C_AXI_IS_ACLK_ASYNC(1),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_SUPPORTS_USER_SIGNALS(1),\n    .C_AXI_AWUSER_WIDTH(8),\n    .C_AXI_ARUSER_WIDTH(8),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_AXI_SUPPORTS_WRITE(1),\n    .C_AXI_SUPPORTS_READ(1),\n    .C_SYNCHRONIZER_STAGE(2)\n  ) inst (\n    .s_axi_aclk(s_axi_aclk),\n    .s_axi_aresetn(s_axi_aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(s_axi_awuser),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(s_axi_aruser),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_aclk(m_axi_aclk),\n    .m_axi_aresetn(m_axi_aresetn),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(m_axi_awuser),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(m_axi_aruser),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 443}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_master #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_SUPPORTS_NARROW = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1,\n   parameter [C_AXI_ADDR_WIDTH-1:0] C_AXI_ADDR = 0,  // Base address\n   parameter integer C_NUM_ADDR = 1,  // Number of address iterations; range 1..2**16 (fixed increment = 32'h10000\n   parameter integer C_NUM_ID = 1,  // Number of ID iterations; range 1..2**C_ID_WIDTH (base = 0; fixed increment = 1)\n   parameter integer C_NUM_LEN = 1,  // Number of LEN iterations; range 1..9 (base = 0; value = 2**i - 1)\n   parameter integer C_NUM_TRANS = 1  // Number of transactions; range >=1 (read and write)\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_awvalid,\n  input  wire                            m_axi_awready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_awburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_awlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_awlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_awid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]    m_axi_awuser = 'b0,\n  /**************** Write Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_wid,\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]      m_axi_wdata,\n  (* dont_touch=\"true\" *) output reg [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb = {(C_AXI_DATA_WIDTH/8){1'b1}},\n  (* dont_touch=\"true\" *) output wire                             m_axi_wvalid,\n  input  wire                            m_axi_wready,\n  (* dont_touch=\"true\" *) output wire                             m_axi_wlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]     m_axi_wuser = 'b0,\n  /**************** Write Response Channel Signals ****************/\n  input  wire [2-1:0]                    m_axi_bresp,\n  input  wire                            m_axi_bvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_bready,\n  input  wire [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]     m_axi_buser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_bid,\n  /**************** Read Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_arvalid,\n  input  wire                            m_axi_arready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_arburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_arlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_arlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_arid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]    m_axi_aruser = 'b0,\n  /**************** Read Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]      m_axi_rdata,\n  input  wire [2-1:0]                    m_axi_rresp,\n  input  wire                            m_axi_rvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_rready,\n  input  wire                            m_axi_rlast,\n  input  wire [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]     m_axi_ruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_rid,\n  /**************** System Signals ****************/\n  input  wire                            aclk,\n  input  wire                            aresetn\n  );\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n  localparam integer  P_NUM_ID_LOG = f_ceil_log2(C_NUM_ID);\n  localparam integer  P_NUM_ADDR_LOG = f_ceil_log2(C_NUM_ADDR);\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL==0 ? 8 : C_AXI_PROTOCOL==1 ? 4 : 1);\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer               P_M_AXI_DATA_BYTES = (C_AXI_DATA_WIDTH / 8);\n  localparam integer               P_M_AXI_DONE_WIDTH = f_ceil_log2(C_NUM_TRANS<2?2:C_NUM_TRANS);\n  localparam integer               P_M_AXI_SIZE = f_ceil_log2(C_AXI_DATA_WIDTH)-3;\n\n  /**************** Internal Wires/Regs - Global ****************/\n   wire                            done;\n    wire                            dummy ;\n  reg                         done_i;\n  reg                         done_sel;\n  wire                         done_cycle;\n  reg                          done_d1 = 1'b0;\n  reg                   areset = 1'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] arcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] rcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [3:0]                    acc_r_i = 4'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] awcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] wcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] bcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [2:0]                    acc_b_i = 3'b0;\n\n  // Register Reset\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    \n    /**************** Internal Wires/Regs - Read Channels ****************/\n    wire                         read_xaction_done_i;\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_arid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_ADDR_WIDTH:0]      araddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  arprot_i = 3'b0;\n    reg [3-1:0]                  arsize_i = 3'b0;\n    reg [2-1:0]                  arburst_i = 2'b0;\n    reg [4-1:0]                  arcache_i = 4'b0;\n    reg [2-1:0]                  arlock_i = 2'b0;\n    reg [P_LEN_WIDTH-1:0]     arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [4-1:0]                  arqos_i = 4'b0;\n    reg [P_ID_WIDTH-1:0]        arid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [2-1:0]                  rresp_i = 2'b00;\n    reg [C_AXI_RUSER_WIDTH:0]   ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      rid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_arvalid_i = 1'b0;\n    reg                        m_axi_rready_i = 1'b0;\n    reg [P_NUM_ADDR_LOG:0]    araddr_cnt = 0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign read_xaction_done_i = m_axi_rvalid && m_axi_rready_i && ((C_AXI_PROTOCOL==2)?1'b1:m_axi_rlast);\n    assign m_axi_arvalid = m_axi_arvalid_i;\n    assign m_axi_rready = m_axi_rready_i;\n    assign m_axi_araddr = m_axi_araddr_i;\n    assign m_axi_arlen = m_axi_arlen_i;\n    always @(posedge aclk) begin\n      m_axi_arprot <= dummy ? arprot_i : 3'b000;\n      m_axi_arsize <= dummy ? arsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_arburst <= dummy ? arburst_i : 2'b01;\n      m_axi_arlock <= dummy ? arlock_i : 1'b0;\n      m_axi_arcache <= dummy ? arcache_i : 4'h3;\n      m_axi_arqos <= dummy  ? arqos_i : 4'h0;\n      m_axi_aruser <= dummy ? aruser_i : 0;\n    end\n  \n    //**********************************************\n    // Read Channel: ARVALID, ARADDR, ARLEN, RREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_arvalid_i <= 1'b0;\n        arcnt_i <= C_NUM_TRANS;\n        m_axi_arlen_i <= 0;\n        m_axi_araddr_i <= C_AXI_ADDR;\n        m_axi_arid_i <= 1;\n        araddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_arready & m_axi_arvalid_i) begin\n          arcnt_i <= arcnt_i - 1;\n          if (araddr_cnt == 1) begin\n            m_axi_araddr_i <= dummy ? araddr_i : C_AXI_ADDR;\n            araddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_araddr_i <= m_axi_araddr_i + 32'h10000;\n            araddr_cnt <= araddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_arlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_arlen_i <= dummy ? arlen_i : 0;\n          end else begin\n            m_axi_arlen_i <= (m_axi_arlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_arid_i == C_NUM_ID)) begin\n            m_axi_arid <= dummy ? arid_i : 0;\n            m_axi_arid_i <= 1;\n          end else begin\n            m_axi_arid <= m_axi_arid_i;\n            m_axi_arid_i <= m_axi_arid_i + 1;\n          end\n          if (arcnt_i == 1) begin\n            m_axi_arvalid_i <= 1'b0;\n          end\n        end else if (arcnt_i != 0) begin\n          m_axi_arvalid_i <= 1'b1;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      araddr_i <= {araddr_i, ~araddr_i[C_AXI_ADDR_WIDTH]};\n      arprot_i <= {arprot_i, ~arprot_i[3-1]};\n      arlen_i <= {arlen_i, ~arlen_i[P_LEN_WIDTH-1]};\n      arsize_i <= {arsize_i, ~arsize_i[3-1]};\n      arburst_i <= {arburst_i, ~arburst_i[2-1]};\n      arlock_i <= {arlock_i, ~arlock_i[2-1]};\n      arcache_i <= {arcache_i, ~arcache_i[4-1]};\n      arqos_i <= {arqos_i, ~arqos_i[4-1]};\n      aruser_i <= {aruser_i, ~aruser_i[C_AXI_ARUSER_WIDTH]};\n      arid_i <= {arid_i, ~arid_i[P_ID_WIDTH-1]};\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        m_axi_rready_i <= 1'b0;\n        rcnt_i <= C_NUM_TRANS;\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        rresp_i <= {2{1'b0}};\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n        rid_i <= {P_ID_WIDTH{1'b0}};\n        acc_r_i <= 4'b0;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_rvalid & m_axi_rready_i) begin\n          m_axi_rready_i <= 1'b0;\n          rdata_i <= m_axi_rdata;\n            acc_r_i[0] <= rdata_i[0];\n          rresp_i <= m_axi_rresp;\n            acc_r_i[1] <= rresp_i[0];\n          ruser_i <= m_axi_ruser;\n            acc_r_i[2] <= ruser_i[0];\n          rid_i <= m_axi_rid;\n            acc_r_i[3] <= rid_i[0];\n          if (m_axi_rlast) begin\n            rcnt_i <= rcnt_i - 1;\n          end\n        end else begin\n          rdata_i <= rdata_i>>1;\n          rresp_i <= rresp_i>>1;\n          ruser_i <= ruser_i>>1;\n          rid_i <= rid_i>>1;\n          acc_r_i <= acc_r_i>>1;\n          if (m_axi_rvalid) begin\n            m_axi_rready_i <= 1'b1;\n          end\n        end\n      end\n    end\n    \n    assign dummy = rdata_i[0];\n    \n    \n\n    /**************** Internal Wires/Regs - Write Channels ****************/\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_awid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [8-1:0]                  xfer_w_i = 8'h00;\n    wire                         write_burst_done_i;\n    reg [C_AXI_ADDR_WIDTH:0]      awaddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  awprot_i = 3'b0;\n    reg [P_LEN_WIDTH-1:0]     awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [3-1:0]                  awsize_i = 3'b0;\n    reg [2-1:0]                  awburst_i = 2'b0;\n    reg [4-1:0]                  awcache_i = 4'b0;\n    reg [2-1:0]                  awlock_i = 2'b0;\n    reg [4-1:0]                  awqos_i = 4'b0;\n    reg [P_ID_WIDTH:0]        awid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_AWUSER_WIDTH:0]    awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg [P_M_AXI_DATA_BYTES-1:0] wstrb_i = {P_M_AXI_DATA_BYTES{1'b1}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]        wid_i = {P_ID_WIDTH{1'b0}};\n    reg [2-1:0]                  bresp_i = 2'b00;\n    reg [C_AXI_BUSER_WIDTH:0]   buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      bid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_awvalid_i = 1'b0;\n    reg                        m_axi_wvalid_i = 1'b0;\n    reg                        m_axi_bready_i = 1'b0;\n    reg                        m_axi_wlast_i = 1'b0;\n    reg                        m_axi_wid_i = {P_ID_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]     wlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [P_NUM_ADDR_LOG:0]    awaddr_cnt = 0;\n  \n    /**************** Assign Write Channel Outputs ****************/\n    assign m_axi_wdata = {wdata_i, done};\n    assign write_burst_done_i = m_axi_wready && m_axi_wvalid_i && ((C_AXI_PROTOCOL==2) || m_axi_wlast_i);\n    assign m_axi_awvalid = m_axi_awvalid_i;\n    assign m_axi_wvalid = m_axi_wvalid_i;\n    assign m_axi_bready = m_axi_bready_i;\n    assign m_axi_wlast = m_axi_wlast_i;\n    assign m_axi_awaddr = m_axi_awaddr_i;\n    assign m_axi_awlen = m_axi_awlen_i;\n    assign m_axi_wid = m_axi_wid_i;\n    always @(posedge aclk) begin\n      m_axi_awprot <= dummy ? awprot_i : 3'b000;\n      m_axi_awsize <= dummy ? awsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_awburst <= dummy ? awburst_i : 2'b01;\n      m_axi_awlock <= dummy ? awlock_i : 1'b0;\n      m_axi_awcache <= dummy ? awcache_i : 4'h3;\n      m_axi_awqos <= dummy ? awqos_i : 4'h0;\n      m_axi_wstrb <= dummy ? wstrb_i : {P_M_AXI_DATA_BYTES{1'b1}};\n      m_axi_awuser <= dummy ?  awuser_i : 0;\n      m_axi_wuser <= dummy ?  wuser_i : 0;\n    end\n  \n    //**********************************************\n    // Write Channel: AWVALID, AWADDR, AWLEN, WVALID, WLAST, BREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_awvalid_i <= 1'b0;\n        m_axi_wvalid_i <= 1'b0;\n        awcnt_i <= C_NUM_TRANS;\n        wcnt_i <= C_NUM_TRANS;\n        xfer_w_i <= 8'h00;\n        m_axi_awlen_i <= 0;\n        m_axi_awaddr_i <= C_AXI_ADDR;\n        m_axi_awid_i <= 1;\n        m_axi_wid_i <= 0;\n        m_axi_wlast_i <= 1'b0;\n        wlen_i <= 0;\n        wid_i <= 0;\n        awaddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_awvalid_i <= 1'b0;\n          awcnt_i <= awcnt_i - 1;\n          if (awaddr_cnt == 1) begin\n            m_axi_awaddr_i <= dummy ? awaddr_i : C_AXI_ADDR;\n            awaddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_awaddr_i <= m_axi_awaddr_i + 32'h10000;\n            awaddr_cnt <= awaddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_awlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_awlen_i <= dummy ? awlen_i : 0;\n          end else begin\n            m_axi_awlen_i <= (m_axi_awlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_awid_i == C_NUM_ID)) begin\n            m_axi_awid <= dummy ? awid_i : 0;\n            m_axi_awid_i <= 1;\n          end else begin\n            m_axi_awid <= m_axi_awid_i;\n            m_axi_awid_i <= m_axi_awid_i + 1;\n          end\n        end else if (~m_axi_wvalid_i) begin\n          if (awcnt_i != 0) begin\n            m_axi_awvalid_i <= 1'b1;\n          end\n        end\n  \n        /**************** Write Data Channel ****************/\n\n        if (m_axi_wready && m_axi_wvalid_i) begin\n          xfer_w_i <= xfer_w_i - 1'b1;\n          if (m_axi_wlast_i) begin\n            m_axi_wvalid_i <= 1'b0;\n            wcnt_i <= wcnt_i - 1'b1;\n          end else begin\n            m_axi_wlast_i <=  (xfer_w_i == 1);\n          end\n        end else if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_wvalid_i <= 1'b1;\n          xfer_w_i <= m_axi_awlen_i;\n          m_axi_wlast_i <= (m_axi_awlen_i==0);\n          m_axi_wid_i <= m_axi_awid_i;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: WDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        wdata_i <= (m_axi_wvalid_i && m_axi_wready) ? {wdata_i[C_AXI_DATA_WIDTH-2 : 0], ~wdata_i[C_AXI_DATA_WIDTH-1]} : wdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      awaddr_i <= {awaddr_i, ~awaddr_i[C_AXI_ADDR_WIDTH]};\n      awprot_i <= {awprot_i[3-2:0], ~awprot_i[3-1]};\n      wstrb_i <= {wstrb_i, ~wstrb_i[C_AXI_DATA_WIDTH/8-1]};\n      awlen_i <= {awlen_i, ~awlen_i[P_LEN_WIDTH-1]};\n      awsize_i <= {awsize_i, ~awsize_i[3-1]};\n      awburst_i <= {awburst_i, ~awburst_i[2-1]};\n      awlock_i <= {awlock_i, ~awlock_i[2-1]};\n      awcache_i <= {awcache_i, ~awcache_i[4-1]};\n      awqos_i <= {awqos_i, ~awqos_i[4-1]};\n      awid_i <= {awid_i, ~awid_i[P_ID_WIDTH-1]};\n      awuser_i <= {awuser_i, ~awuser_i[C_AXI_AWUSER_WIDTH]};\n      wuser_i <= {wuser_i, ~wuser_i[C_AXI_WUSER_WIDTH]};\n    end\n  \n    //**********************************************\n    // Write Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_bready_i <= 1'b0;\n        bcnt_i <= C_NUM_TRANS;\n        bresp_i <= {2{1'b0}};\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n        bid_i <= {P_ID_WIDTH{1'b0}};\n        acc_b_i <= 3'b0;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_bvalid & m_axi_bready_i) begin\n          m_axi_bready_i <= 1'b0;\n          bresp_i <= m_axi_bresp;\n            acc_b_i[0] <= bresp_i[0];\n          buser_i <= m_axi_buser;\n            acc_b_i[1] <= buser_i[0];\n          bid_i <= m_axi_bid;\n            acc_b_i[2] <= bid_i[0];\n          bcnt_i <= bcnt_i - 1;\n        end else begin\n          bresp_i <= bresp_i>>1;\n          buser_i <= buser_i>>1;\n          bid_i <= bid_i>>1;\n          acc_b_i <= acc_b_i>>1;\n          if (m_axi_bvalid) begin\n            m_axi_bready_i <= 1'b1;\n          end\n        end\n      end\n    end\n\n\n  //**********************************************\n  // Assert Done\n  //**********************************************\n  always @(posedge aclk) begin\n    if (~aresetn) begin\n      done_d1 <= 1'b0;\n    end else begin\n      done_d1 <= done_i;\n    end\n  end\n\n  assign done = done_sel ? done_i : done_d1;\n  assign done_cycle = done_i & ~done_d1;\n  \n  always @ * begin\n    if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_readonly_done\n       done_i = rcnt_i==0;\n       done_sel = acc_r_i[0];\n    end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_writeonly_done\n       done_i = bcnt_i==0;\n       done_sel = acc_b_i[0];\n    end else begin : gen_readwrite_done\n       done_i = (rcnt_i==0) && (bcnt_i==0);\n       done_sel = acc_r_i[0] ^ acc_b_i[0];\n    end\n  end\n  \nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n  input  wire [3-1:0]                   s_axi_awprot,\n  input  wire                           s_axi_awvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_awready,\n  input  wire [3-1:0]                   s_axi_awsize,\n  input  wire [2-1:0]                   s_axi_awburst,\n  input  wire [4-1:0]                   s_axi_awcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_awlen,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_awlock,\n  input  wire [4-1:0]                   s_axi_awqos,\n  input  wire [4-1:0]                   s_axi_awregion,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_awid,\n  input  wire [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]   s_axi_awuser,\n  /**************** Write Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n  input  wire                           s_axi_wvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_wready,\n  input  wire                           s_axi_wlast,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_wid,\n  input  wire [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]    s_axi_wuser,\n  /**************** Write Response Channel Signals ****************/\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_bresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_bvalid,\n  input  wire                           s_axi_bready,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]    s_axi_buser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_bid = 'b0,\n  /**************** Read Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n  input  wire [3-1:0]                   s_axi_arprot,\n  input  wire                           s_axi_arvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_arready,\n  input  wire [3-1:0]                   s_axi_arsize,\n  input  wire [2-1:0]                   s_axi_arburst,\n  input  wire [4-1:0]                   s_axi_arcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_arlock,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_arlen,\n  input  wire [4-1:0]                   s_axi_arqos,\n  input  wire [4-1:0]                   s_axi_arregion,\n  input  wire [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]   s_axi_aruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_arid,\n  /**************** Read Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_rresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rvalid,\n  input  wire                           s_axi_rready,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]    s_axi_ruser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_rid = 'b0,\n  /**************** System Signals ****************/\n  input  wire                           aclk,\n  input  wire                           aresetn\n   );\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL == 1) ? 4 : 8;\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer P_S_AXI_DATA_BYTES = 32/8;\n  localparam integer P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n\n  /**************** Internal Wires/Regs - Global ****************/\n  reg                   areset = 1'b0;\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    /**************** Internal Wires/Regs - Read Channels ****************/\n    reg [8-1:0]                   xfer_r_cnt = 8'h00;\n    reg [16-1:0]                  arcnt_i = 16'h0000;\n    wire                          read_xaction_done_i;\n    reg [C_AXI_DATA_WIDTH-1:0]     rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]      arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg                           arvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     araddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   arprot_i = 3'b000;\n    reg [3-1:0]                   arsize_i = 3'b000;\n    reg [2-1:0]                   arburst_i = 2'b00;\n    reg [4-1:0]                   arcache_i = 4'b0000;\n    reg [1-1:0]     arlock_i = 1'b0;\n    reg [4-1:0]                   arqos_i = 4'b0000;\n    reg [4-1:0]                   arregion_i = 4'b0000;\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_RUSER_WIDTH:0]     ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_ar_i = 9'b0;\n    reg                           s_axi_rvalid_i = 1'b0;\n    reg                           s_axi_arready_i = 1'b0;\n    reg                           s_axi_rlast_i = 1'b0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign s_axi_rdata = rdata_i;\n    assign read_xaction_done_i = (s_axi_rready && s_axi_rvalid_i && s_axi_rlast_i);\n    assign s_axi_rvalid = s_axi_rvalid_i;\n    assign s_axi_arready = s_axi_arready_i;\n    assign s_axi_rlast = s_axi_rlast_i;\n    //**********************************************\n    // Read Channel: ARREADY, RVALID, RLAST, RID\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        xfer_r_cnt <= 8'h00;\n        arcnt_i <= 16'h0000;\n        arlen_i <= {P_LEN_WIDTH{1'b0}};\n        s_axi_rlast_i <= 1'b0;\n      end else begin\n        /**************** Read Address Channel ****************/\n        // arready\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_arready_i <= 1'b0;\n          arcnt_i <= arcnt_i + 1'b1;\n        end else if (~s_axi_rvalid_i) begin\n          s_axi_arready_i <= 1'b1;\n        end\n  \n        /**************** Read Data Channel ****************/\n        // rvalid\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_rvalid_i <= 1'b1;\n          s_axi_rid <= s_axi_arid;\n          s_axi_ruser <= ruser_i;\n        end else if(read_xaction_done_i) begin\n          s_axi_rvalid_i <= 1'b0;\n        end\n  \n        // rlast\n        if(s_axi_rready && s_axi_rvalid_i) begin\n          xfer_r_cnt <= xfer_r_cnt - 1;\n          if(xfer_r_cnt == 1) begin\n            s_axi_rlast_i <= 1'b1;\n          end\n        end else if(s_axi_arready_i && s_axi_arvalid) begin\n          xfer_r_cnt <= s_axi_arlen;\n          s_axi_rlast_i <= (s_axi_arlen==0);\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Read Channel: RDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        rdata_i <= (s_axi_rready && s_axi_rvalid_i) ? {rdata_i[C_AXI_DATA_WIDTH-2 : 0], ~rdata_i[C_AXI_DATA_WIDTH-1]} : rdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_rresp <= {2{1'b0}};\n      end else if (~s_axi_rvalid_i) begin\n        s_axi_rresp <= {acc_ar_i[0], 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n      end else begin\n        ruser_i <= (s_axi_arready_i && s_axi_arvalid) ? {ruser_i, ~ruser_i[C_AXI_RUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        araddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        arprot_i <= {3{1'b0}};\n        arsize_i <= {3{1'b0}};\n        arburst_i <= {2{1'b0}};\n        arcache_i <= {4{1'b0}};\n        arlock_i <= {1{1'b0}};\n        arqos_i <= {4{1'b0}};\n        arregion_i <= {4{1'b0}};\n        aruser_i <= {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n        acc_ar_i <= 9'b0;\n      end else if (s_axi_arvalid) begin\n        // Register Inputs\n        araddr_i <= s_axi_araddr;\n          acc_ar_i[0] <= araddr_i[0];\n        arprot_i <= s_axi_arprot;\n          acc_ar_i[1] <= arprot_i[0];\n        arsize_i <= s_axi_arsize;\n          acc_ar_i[2] <= arsize_i[0];\n        arburst_i <= s_axi_arburst;\n          acc_ar_i[3] <= arburst_i[0];\n        arcache_i <= s_axi_arcache;\n          acc_ar_i[4] <= arcache_i[0];\n        arlock_i <= s_axi_arlock;\n          acc_ar_i[5] <= arlock_i[0];\n        arqos_i <= s_axi_arqos;\n          acc_ar_i[6] <= arqos_i[0];\n        arregion_i <= s_axi_arregion;\n          acc_ar_i[7] <= arregion_i[0];\n        aruser_i <= s_axi_aruser;\n          acc_ar_i[8] <= aruser_i[0];\n      end else begin\n        araddr_i <= araddr_i>>1;\n        arprot_i <= arprot_i>>1;\n        arsize_i <= arsize_i>>1;\n        arburst_i <= arburst_i>>1;\n        arcache_i <= arcache_i>>1;\n        arlock_i <= arlock_i>>1;\n        arqos_i <= arqos_i>>1;\n        arregion_i <= arregion_i>>1;\n        aruser_i <= aruser_i>>1;\n        acc_ar_i <= acc_ar_i>>1;\n      end\n    end\n  \n  \n    /**************** Internal Wires/Regs - Write Channels ****************/\n    wire                          write_burst_done_i;\n    reg [16-1:0]                  awcnt_i = 16'h0000;\n    reg                           awvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     awaddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   awprot_i = 3'b000;\n    reg [3-1:0]                   awsize_i = 3'b000;\n    reg [2-1:0]                   awburst_i = 2'b00;\n    reg [4-1:0]                   awcache_i = 4'b0000;\n    reg [P_LEN_WIDTH-1:0]      awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [1-1:0]     awlock_i = 1'b0;\n    reg [4-1:0]                   awqos_i = 4'b0000;\n    reg [4-1:0]                   awregion_i = 4'b0000;\n    reg [C_AXI_AWUSER_WIDTH:0]     awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg                           wvalid_i = 1'b0;\n    reg [C_AXI_DATA_WIDTH-1:0]     wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH/8-1:0]   wstrb_i = {(C_AXI_DATA_WIDTH/8){1'b0}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_BUSER_WIDTH:0]     buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_aw_i = 9'b0;\n    reg [3:0]                     acc_w_i = 4'b0;\n    reg                           s_axi_bvalid_i = 1'b0;\n    reg                           s_axi_awready_i = 1'b0;\n    reg                           s_axi_wready_i = 1'b0;\n    /**************** Assign Write Channel Outputs ****************/\n    assign write_burst_done_i =s_axi_wready_i && s_axi_wvalid && ((C_AXI_PROTOCOL == 2) ? 1'b1 : s_axi_wlast);\n    assign s_axi_bvalid = s_axi_bvalid_i;\n    assign s_axi_awready = s_axi_awready_i;\n    assign s_axi_wready = s_axi_wready_i;\n  \n    //**********************************************\n    // Write Channel: AWREADY, WREADY, BVALID, BID\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awcnt_i <= 16'h0000;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        /**************** Write Address Channel ****************/\n        // awready\n        if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_awready_i <= 1'b0;\n          awcnt_i <= awcnt_i + 1'b1;\n          s_axi_bid <= s_axi_awid;\n          s_axi_buser <= buser_i;\n        end else if(~s_axi_wready_i & ~s_axi_bvalid_i) begin\n          s_axi_awready_i <= 1'b1;\n        end\n  \n        /**************** Write Data Channel ****************/\n        // wready\n        if(write_burst_done_i) begin\n          s_axi_wready_i <= 1'b0;\n        end else if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_wready_i <= 1'b1;\n        end\n  \n        /**************** Write Response Channel ****************/\n        // bvalid\n        if(write_burst_done_i) begin\n          s_axi_bvalid_i <= 1'b1;\n        end else if(s_axi_bready && s_axi_bvalid_i) begin\n          s_axi_bvalid_i <= 1'b0;\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Write Channel: BRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_bresp <= {2{1'b0}};\n      end else if (~s_axi_bvalid_i) begin\n        s_axi_bresp <= {(acc_aw_i[0] ^ acc_w_i[0]), 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: BUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (aresetn) begin\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n      end else begin\n        buser_i <= (s_axi_awready_i && s_axi_awvalid) ? {buser_i, ~buser_i[C_AXI_BUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Write Address Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awaddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        awprot_i <= {3{1'b0}};\n        awsize_i <= {3{1'b0}};\n        awburst_i <= {2{1'b0}};\n        awcache_i <= {4{1'b0}};\n        awlen_i <= {P_LEN_WIDTH{1'b0}};\n        awlock_i <= {1{1'b0}};\n        awqos_i <= {4{1'b0}};\n        awregion_i <= {4{1'b0}};\n        awuser_i <= {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n        acc_aw_i <= 9'b0;\n      end else if (s_axi_awvalid) begin\n        // Register Inputs\n        awaddr_i <= s_axi_awaddr;\n          acc_aw_i[0] <= awaddr_i[0];\n        awprot_i <= s_axi_awprot;\n          acc_aw_i[1] <= awprot_i[0];\n        awsize_i <= s_axi_awsize;\n          acc_aw_i[2] <= awsize_i[0];\n        awburst_i <= s_axi_awburst;\n          acc_aw_i[3] <= awburst_i[0];\n        awcache_i <= s_axi_awcache;\n          acc_aw_i[4] <= awcache_i[0];\n        awlock_i <= s_axi_awlock;\n          acc_aw_i[5] <= awlock_i[0];\n        awqos_i <= s_axi_awqos;\n          acc_aw_i[6] <= awqos_i[0];\n        awregion_i <= s_axi_awregion;\n          acc_aw_i[7] <= awregion_i[0];\n        awuser_i <= s_axi_awuser;\n          acc_aw_i[8] <= awuser_i[0];\n      end else begin\n        awaddr_i <= awaddr_i>>1;\n        awprot_i <= awprot_i>>1;\n        awsize_i <= awsize_i>>1;\n        awburst_i <= awburst_i>>1;\n        awcache_i <= awcache_i>>1;\n        awlock_i <= awlock_i>>1;\n        awqos_i <= awqos_i>>1;\n        awregion_i <= awregion_i>>1;\n        awuser_i <= awuser_i>>1;\n        acc_aw_i <= acc_aw_i>>1;\n      end\n    end\n  \n    //**********************************************\n    // Write Data Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        wstrb_i <= {(C_AXI_DATA_WIDTH/8){1'b0}};\n        wuser_i <= {(C_AXI_WUSER_WIDTH+1){1'b0}};\n        acc_w_i <= 4'b0;\n      end else if (s_axi_wvalid) begin\n        // Register Inputs\n        wdata_i <= s_axi_wdata;\n          acc_w_i[0] <= wdata_i[0];\n        wstrb_i <= s_axi_wstrb;\n          acc_w_i[1] <= wstrb_i[0];\n        wuser_i <= s_axi_wuser;\n          acc_w_i[2] <= wuser_i[0];\n      end else begin\n        wdata_i <= wdata_i>>1;\n        wstrb_i <= wstrb_i>>1;\n        wuser_i <= wuser_i>>1;\n        acc_w_i <= acc_w_i>>1;\n      end\n    end\n  \nendmodule\n\n\n\n//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_22_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \n(* autopipeline_module=\"yes\" *)\nmodule axi_register_slice_v2_1_22_auto_slr #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n    wire                    handshake_pipe;\n    wire                    ready_pipe;\n    wire [C_DATA_WIDTH-1:0] payload_pipe;\n    (* keep=\"true\" *)                                                                reg  s_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  s_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  s_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  s_areset_resp2 = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  m_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  m_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_areset_resp2 = 1'b0;\n    \n  // Global Reset pipelining\n  \n    always @(posedge ACLK) begin\n      s_aclear       <= ~ARESETN;\n      s_areset_fwd   <= ~ARESETN; \n      s_areset_resp  <= s_areset_fwd;  // Auto-pipeline\n      s_areset_resp2 <= s_areset_resp; // Auto-pipeline\n    end\n    \n    always @(posedge ACLK) begin\n      m_aclear       <= ~ARESETN;\n      m_areset_fwd   <= ~ARESETN; \n      m_areset_resp  <= m_areset_fwd;  // Auto-pipeline\n      m_areset_resp2 <= m_areset_resp; // Auto-pipeline\n    end\n    \n  // Source-side submodule\n    \n    axi_register_slice_v2_1_22_auto_src #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_src\n      (\n       .ACLK             (ACLK),    \n       .s_aclear         (s_aclear),\n       .s_areset_resp2   (s_areset_resp2),  \n       .S_VALID          (S_VALID),  \n       .S_READY          (S_READY), \n       .S_PAYLOAD_DATA   (S_PAYLOAD_DATA),\n       .ready_pipe        (ready_pipe), \n       .handshake_pipe    (handshake_pipe),\n       .payload_pipe      (payload_pipe)  \n      );\n    \n  // Destination-side submodule\n    \n    axi_register_slice_v2_1_22_auto_dest #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_dest\n      (\n       .ACLK           (ACLK),    \n       .m_aclear       (m_aclear),\n       .m_areset_resp2 (m_areset_resp2),  \n       .M_READY        (M_READY), \n       .M_VALID        (M_VALID),  \n       .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n       .handshake_pipe  (handshake_pipe),\n       .ready_pipe      (ready_pipe),  \n       .payload_pipe    (payload_pipe)  \n      );\n    \nendmodule  // auto_slr\n\nmodule axi_register_slice_v2_1_22_auto_src #\n  (\n   parameter integer C_DATA_WIDTH = 32\n  )\n  (\n   input  wire ACLK,\n   input  wire s_aclear,\n   input  wire s_areset_resp2,\n   input  wire S_VALID,\n   input  wire ready_pipe,\n   output wire S_READY,\n   output wire handshake_pipe,\n   output wire  [C_DATA_WIDTH-1:0] payload_pipe,\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA\n   );\n    \n   (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  [C_DATA_WIDTH-1:0] payload_pipe_r;\n    (* keep=\"true\" *) reg [2:0] s_aresetn_resp4 = 3'b000;\n    wire s_aresetn_resp3;\n    wire s_aresetn_d;\n    wire s_aresetn_q;\n    wire s_handshake_d;\n    wire s_ready_i;\n    \n    assign S_READY = s_ready_i & s_aresetn_q;\n    assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;\n    assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;\n    assign payload_pipe = payload_pipe_r;\n    \n    always @(posedge ACLK or posedge s_aclear) begin\n      if (s_aclear) begin\n        s_aresetn_resp4 <= 3'b000;\n      end else begin\n        s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      payload_pipe_r <= S_PAYLOAD_DATA;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) s_aresetn_resp3_inst (\n        .Q   (s_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~s_areset_resp2)\n     );\n    \n    // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (s_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_aresetn_d)\n     );\n    \n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (handshake_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_handshake_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (s_ready_i),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (ready_pipe)\n     );\n    \nendmodule  // auto_src\n\nmodule axi_register_slice_v2_1_22_auto_dest #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   input  wire ACLK,\n   input  wire m_aclear,\n   input  wire m_areset_resp2,\n   input  wire M_READY,\n   input  wire handshake_pipe,\n   output wire ready_pipe,\n   output wire M_VALID,\n   input  wire [C_DATA_WIDTH-1:0] payload_pipe,\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n   );\n    \n    (* keep=\"true\" *) reg [2:0] m_aresetn_resp4 = 3'b000;\n    wire m_aresetn_resp3;\n    wire m_aresetn_d;\n    wire m_aresetn_q;\n    wire m_valid_i;\n    wire pop;\n    wire m_ready_d;\n    wire m_handshake_q;\n    reg  [C_DATA_WIDTH-1:0] m_payload_q;\n    \n    assign M_VALID = m_valid_i;\n    assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;\n    assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;\n    assign pop     = M_READY & m_valid_i;\n    \n    always @(posedge ACLK or posedge m_aclear) begin\n      if (m_aclear) begin\n        m_aresetn_resp4 <= 3'b000;\n      end else begin\n        m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      m_payload_q <= payload_pipe;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) m_aresetn_resp3_inst (\n        .Q   (m_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~m_areset_resp2)\n     );\n    \n    // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (m_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_aresetn_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (m_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (handshake_pipe)\n     );\n    \n    (* autopipeline_group=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (ready_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_ready_d)\n     );\n    \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  (5)  \n      )\n      srl_fifo\n      (\n       .aclk    (ACLK),    \n       .areset  (~m_aresetn_q),\n       .aclear  (m_aclear),  \n       .s_mesg  (m_payload_q),  \n       .s_valid (m_handshake_q), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      );\n    \nendmodule  // auto_dest\n\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      reg s_valid_d;\n      reg s_ready_d = 1'b0;\n      reg s_ready_reg = 1'b0;\n      reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_22_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_RESP_MIDDLE2_LATENCY = C_PIPELINES_SLAVE + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_22_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      .ACLK           (ACLK),\n      .ARESETN         (ARESETN),\n      .S_PAYLOAD_DATA (S_PAYLOAD_DATA),\n      .S_VALID        (S_VALID),\n      .S_READY        (S_READY),\n      .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n      .M_VALID        (M_VALID),\n      .M_READY        (M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_reset;\n    wire src_ready;\n    wire dummy_reset;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  ( C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( dummy_reset   ) ,\n        .laguna_s_reset_in  ( src_reset   ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset   ) ,\n        .laguna_m_reset_in  ( src_reset  ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset2   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n      \n  end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] mid_payload;\n    wire mid_handshake;\n    wire mid_ready;\n    wire mid_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n    wire dummy_reset3;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( mid_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( mid_reset    ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset3   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset3   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out (  dummy_reset2  ) ,\n        .laguna_m_reset_in  ( mid_reset   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE2_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( mid_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2   ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset3   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset3    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n   \n  generate\n\n  (* keep=\"true\" *) reg s_reset_dd = 1'b0;\n  (* keep=\"true\" *) reg m_reset_dd = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n  \n  assign laguna_s_reset_out = laguna_s_reset_out_i;\n  assign laguna_m_reset_out = laguna_m_reset_out_i;\n  \n  always @(posedge ACLK) begin\n    laguna_s_reset_in_d <= laguna_s_reset_in;\n    laguna_m_reset_in_d <= laguna_m_reset_in;\n    s_reset_dd <= laguna_s_reset_in_d;\n    m_reset_dd <= laguna_m_reset_in_d;\n    laguna_s_reset_out_i <= C_PIPELINES==0 ? laguna_m_reset_in_d : m_reset_dd;\n    laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;\n  end\n  \n  wire ACLEAR;\n  assign ACLEAR = ~ARESETN;\n  \n  if (1) begin : common\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire laguna_s_handshake_q;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, laguna_m_ready_d}; \n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else if (p==C_PIPELINES+1) begin\n          laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n\n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = handshake_i[C_PIPELINES];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_m_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* keep=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_22_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_m_reset_out = laguna_m_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_m_reset_in_d <= laguna_m_reset_in;\n      aresetn_d <= C_CHANNEL==P_FORWARD ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? areset_dly[15]  : laguna_m_reset_in_d;\n      laguna_m_reset_out_i <= areset_d;  // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n  \n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* keep=\"true\" *)  reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      ready_d <= {ready_d, laguna_m_ready_d}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid_q;\n      assign payload_valid_d = (p==0) ? (S_VALID & s_ready_i) : handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==C_PIPELINES) begin\n          laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else if (p==0) begin\n          payload_data <= S_PAYLOAD_DATA;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n      \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_s_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* keep=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_s_reset_out = laguna_s_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_s_reset_in_d <= laguna_s_reset_in;\n      aresetn_d <= C_CHANNEL==P_RESPONSE ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? laguna_s_reset_in_d : areset_dly[15];\n      laguna_s_reset_out_i <= areset_d;  // For forward channels, reflect laguna_s_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n\n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    wire laguna_s_handshake_q;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      laguna_s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n        \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n        \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)  \n      )\n      srl_fifo_0\n      (\n       .aclk    (ACLK),    \n       .areset  (areset_d),  \n       .aclear  (ACLEAR),\n       .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n       .s_valid (push), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      ); \n  \n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  reg areset_d = 1'b0;\n  reg [3:0] areset_dly = 4'b0;\n  always @(posedge ACLK) begin\n    areset_dly <= {4{~ARESETN}} | (areset_dly<<1);\n    areset_d <= areset_dly[3];\n  end\n  \n  if (1) begin : common\n    reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID & s_ready_i;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* keep=\"true\" *)  reg payload_valid = 1'b0;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          payload_data <= S_PAYLOAD_DATA;\n          payload_valid <= S_VALID & s_ready_i & ~areset_d;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n          payload_valid <= handshake_i[((p>0)?(p-1):0)];\n        end\n      end\n    end\n    \n    if (C_PIPELINES==0) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),\n         .aclear  (1'b0),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire                        aclear,  // Async clear\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    wire [1:0] state;  // State vector register\n    reg  [1:0] next;           // Next state value\n    wire [1:0] next_qual;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    reg  m_valid_d;\n    wire m_valid_q;\n    \n    assign m_valid = m_valid_q;\n    assign next_qual = areset ? K_EMPTY : next;\n    assign m_mesg  = mesg_reg;\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_mvalid_inst (\n        .Q   (m_valid_q),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (m_valid_d)\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state0_inst (\n        .Q   (state[0]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[0])\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state1_inst (\n        .Q   (state[1]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[1])\n     );\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      m_valid_d = m_valid_q & ~areset;\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid & ~areset) begin\n            next = K_HAS1;\n            m_valid_d = 1'b0;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              m_valid_d = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n              m_valid_d = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          m_valid_d = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      (* keep_hierarchy = \"yes\" *) axi_register_slice_v2_1_22_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule  // axic_reg_srl_fifo\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   //   16 -> Auto-pipelining\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_RESERVE_MODE = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n  \n  if (C_RESERVE_MODE==1) begin : gen_reserve_si\n  \n    axi_register_slice_v2_1_22_test_slave #(\n      .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n      .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n      .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n      .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n      .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n      .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n      .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n      .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n      .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .s_axi_awaddr(s_axi_awaddr),\n      .s_axi_awprot(s_axi_awprot),\n      .s_axi_awvalid(s_axi_awvalid),\n      .s_axi_awready(s_axi_awready),\n      .s_axi_awsize(s_axi_awsize),\n      .s_axi_awburst(s_axi_awburst),\n      .s_axi_awcache(s_axi_awcache),\n      .s_axi_awlen(s_axi_awlen),\n      .s_axi_awlock(s_axi_awlock),\n      .s_axi_awqos(s_axi_awqos),\n      .s_axi_awregion(s_axi_awregion),\n      .s_axi_awid(s_axi_awid),\n      .s_axi_awuser(s_axi_awuser),\n      .s_axi_wdata(s_axi_wdata),\n      .s_axi_wstrb(s_axi_wstrb),\n      .s_axi_wvalid(s_axi_wvalid),\n      .s_axi_wready(s_axi_wready),\n      .s_axi_wlast(s_axi_wlast),\n      .s_axi_wid(s_axi_wid),\n      .s_axi_wuser(s_axi_wuser),\n      .s_axi_bresp(s_axi_bresp),\n      .s_axi_bvalid(s_axi_bvalid),\n      .s_axi_bready(s_axi_bready),\n      .s_axi_buser(s_axi_buser),\n      .s_axi_bid(s_axi_bid),\n      .s_axi_araddr(s_axi_araddr),\n      .s_axi_arprot(s_axi_arprot),\n      .s_axi_arvalid(s_axi_arvalid),\n      .s_axi_arready(s_axi_arready),\n      .s_axi_arsize(s_axi_arsize),\n      .s_axi_arburst(s_axi_arburst),\n      .s_axi_arcache(s_axi_arcache),\n      .s_axi_arlock(s_axi_arlock),\n      .s_axi_arlen(s_axi_arlen),\n      .s_axi_arqos(s_axi_arqos),\n      .s_axi_arregion(s_axi_arregion),\n      .s_axi_aruser(s_axi_aruser),\n      .s_axi_arid(s_axi_arid),\n      .s_axi_rdata(s_axi_rdata),\n      .s_axi_rresp(s_axi_rresp),\n      .s_axi_rvalid(s_axi_rvalid),\n      .s_axi_rready(s_axi_rready),\n      .s_axi_rlast(s_axi_rlast),\n      .s_axi_ruser(s_axi_ruser),\n      .s_axi_rid(s_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign m_axi_awid     = 0;\n     assign m_axi_awaddr   = 0;\n     assign m_axi_awlen    = 0;\n     assign m_axi_awsize   = 0;\n     assign m_axi_awburst  = 0;\n     assign m_axi_awlock   = 0;\n     assign m_axi_awcache  = 0;\n     assign m_axi_awprot   = 0;\n     assign m_axi_awregion = 0;\n     assign m_axi_awqos    = 0;\n     assign m_axi_awuser   = 0;\n     assign m_axi_awvalid  = 0;\n     assign m_axi_wid      = 0;\n     assign m_axi_wdata    = 0;\n     assign m_axi_wstrb    = 0;\n     assign m_axi_wlast    = 0;\n     assign m_axi_wuser    = 0;\n     assign m_axi_wvalid   = 0;\n     assign m_axi_bready   = 0;\n     assign m_axi_arid     = 0;\n     assign m_axi_araddr   = 0;\n     assign m_axi_arlen    = 0;\n     assign m_axi_arsize   = 0;\n     assign m_axi_arburst  = 0;\n     assign m_axi_arlock   = 0;\n     assign m_axi_arcache  = 0;\n     assign m_axi_arprot   = 0;\n     assign m_axi_arregion = 0;\n     assign m_axi_arqos    = 0;\n     assign m_axi_aruser   = 0;\n     assign m_axi_arvalid  = 0;\n     assign m_axi_rready   = 0;\n      \n  end else if (C_RESERVE_MODE==2) begin : gen_reserve_mi\n    \n    axi_register_slice_v2_1_22_test_master #(\n    .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n    .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .m_axi_awaddr(m_axi_awaddr),\n      .m_axi_awprot(m_axi_awprot),\n      .m_axi_awvalid(m_axi_awvalid),\n      .m_axi_awready(m_axi_awready),\n      .m_axi_awsize(m_axi_awsize),\n      .m_axi_awburst(m_axi_awburst),\n      .m_axi_awcache(m_axi_awcache),\n      .m_axi_awlen(m_axi_awlen),\n      .m_axi_awlock(m_axi_awlock),\n      .m_axi_awqos(m_axi_awqos),\n      .m_axi_awid(m_axi_awid),\n      .m_axi_awuser(m_axi_awuser),\n      .m_axi_wid(m_axi_wid),\n      .m_axi_wdata(m_axi_wdata),\n      .m_axi_wstrb(m_axi_wstrb),\n      .m_axi_wvalid(m_axi_wvalid),\n      .m_axi_wready(m_axi_wready),\n      .m_axi_wlast(m_axi_wlast),\n      .m_axi_wuser(m_axi_wuser),\n      .m_axi_bresp(m_axi_bresp),\n      .m_axi_bvalid(m_axi_bvalid),\n      .m_axi_bready(m_axi_bready),\n      .m_axi_buser(m_axi_buser),\n      .m_axi_bid(m_axi_bid),\n      .m_axi_araddr(m_axi_araddr),\n      .m_axi_arprot(m_axi_arprot),\n      .m_axi_arvalid(m_axi_arvalid),\n      .m_axi_arready(m_axi_arready),\n      .m_axi_arsize(m_axi_arsize),\n      .m_axi_arburst(m_axi_arburst),\n      .m_axi_arcache(m_axi_arcache),\n      .m_axi_arlen(m_axi_arlen),\n      .m_axi_arlock(m_axi_arlock),\n      .m_axi_arqos(m_axi_arqos),\n      .m_axi_arid(m_axi_arid),\n      .m_axi_aruser(m_axi_aruser),\n      .m_axi_rdata(m_axi_rdata),\n      .m_axi_rresp(m_axi_rresp),\n      .m_axi_rvalid(m_axi_rvalid),\n      .m_axi_rready(m_axi_rready),\n      .m_axi_rlast(m_axi_rlast),\n      .m_axi_ruser(m_axi_ruser),\n      .m_axi_rid(m_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign s_axi_awready = 0;\n     assign s_axi_wready  = 0;\n     assign s_axi_bid     = 0;\n     assign s_axi_bresp   = 0;\n     assign s_axi_buser   = 0;\n     assign s_axi_bvalid  = 0;\n     assign s_axi_arready = 0;\n     assign s_axi_rid     = 0;\n     assign s_axi_rdata   = 0;\n     assign s_axi_rresp   = 0;\n     assign s_axi_rlast   = 0;\n     assign s_axi_ruser   = 0;\n     assign s_axi_rvalid  = 0;\n\n  end else begin : gen_reg_slice  // Any normal reg-slice mode\n\n    axi_infrastructure_v1_1_0_axi2vector #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    axi2vector_0 ( \n      .s_axi_awid      ( s_axi_awid      ) ,\n      .s_axi_awaddr    ( s_axi_awaddr    ) ,\n      .s_axi_awlen     ( s_axi_awlen     ) ,\n      .s_axi_awsize    ( s_axi_awsize    ) ,\n      .s_axi_awburst   ( s_axi_awburst   ) ,\n      .s_axi_awlock    ( s_axi_awlock    ) ,\n      .s_axi_awcache   ( s_axi_awcache   ) ,\n      .s_axi_awprot    ( s_axi_awprot    ) ,\n      .s_axi_awqos     ( s_axi_awqos     ) ,\n      .s_axi_awuser    ( s_axi_awuser    ) ,\n      .s_axi_awregion  ( s_axi_awregion  ) ,\n      .s_axi_wid       ( s_axi_wid       ) ,\n      .s_axi_wdata     ( s_axi_wdata     ) ,\n      .s_axi_wstrb     ( s_axi_wstrb     ) ,\n      .s_axi_wlast     ( s_axi_wlast     ) ,\n      .s_axi_wuser     ( s_axi_wuser     ) ,\n      .s_axi_bid       ( s_axi_bid       ) ,\n      .s_axi_bresp     ( s_axi_bresp     ) ,\n      .s_axi_buser     ( s_axi_buser     ) ,\n      .s_axi_arid      ( s_axi_arid      ) ,\n      .s_axi_araddr    ( s_axi_araddr    ) ,\n      .s_axi_arlen     ( s_axi_arlen     ) ,\n      .s_axi_arsize    ( s_axi_arsize    ) ,\n      .s_axi_arburst   ( s_axi_arburst   ) ,\n      .s_axi_arlock    ( s_axi_arlock    ) ,\n      .s_axi_arcache   ( s_axi_arcache   ) ,\n      .s_axi_arprot    ( s_axi_arprot    ) ,\n      .s_axi_arqos     ( s_axi_arqos     ) ,\n      .s_axi_aruser    ( s_axi_aruser    ) ,\n      .s_axi_arregion  ( s_axi_arregion  ) ,\n      .s_axi_rid       ( s_axi_rid       ) ,\n      .s_axi_rdata     ( s_axi_rdata     ) ,\n      .s_axi_rresp     ( s_axi_rresp     ) ,\n      .s_axi_rlast     ( s_axi_rlast     ) ,\n      .s_axi_ruser     ( s_axi_ruser     ) ,\n      .s_awpayload ( s_awpayload ) ,\n      .s_wpayload  ( s_wpayload  ) ,\n      .s_bpayload  ( s_bpayload  ) ,\n      .s_arpayload ( s_arpayload ) ,\n      .s_rpayload  ( s_rpayload  ) \n    );\n    \n    axi_infrastructure_v1_1_0_vector2axi #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    vector2axi_0 ( \n      .m_awpayload    ( m_awpayload    ) ,\n      .m_wpayload     ( m_wpayload     ) ,\n      .m_bpayload     ( m_bpayload     ) ,\n      .m_arpayload    ( m_arpayload    ) ,\n      .m_rpayload     ( m_rpayload     ) ,\n      .m_axi_awid     ( m_axi_awid     ) ,\n      .m_axi_awaddr   ( m_axi_awaddr   ) ,\n      .m_axi_awlen    ( m_axi_awlen    ) ,\n      .m_axi_awsize   ( m_axi_awsize   ) ,\n      .m_axi_awburst  ( m_axi_awburst  ) ,\n      .m_axi_awlock   ( m_axi_awlock   ) ,\n      .m_axi_awcache  ( m_axi_awcache  ) ,\n      .m_axi_awprot   ( m_axi_awprot   ) ,\n      .m_axi_awqos    ( m_axi_awqos    ) ,\n      .m_axi_awuser   ( m_axi_awuser   ) ,\n      .m_axi_awregion ( m_axi_awregion ) ,\n      .m_axi_wid      ( m_axi_wid      ) ,\n      .m_axi_wdata    ( m_axi_wdata    ) ,\n      .m_axi_wstrb    ( m_axi_wstrb    ) ,\n      .m_axi_wlast    ( m_axi_wlast    ) ,\n      .m_axi_wuser    ( m_axi_wuser    ) ,\n      .m_axi_bid      ( m_axi_bid      ) ,\n      .m_axi_bresp    ( m_axi_bresp    ) ,\n      .m_axi_buser    ( m_axi_buser    ) ,\n      .m_axi_arid     ( m_axi_arid     ) ,\n      .m_axi_araddr   ( m_axi_araddr   ) ,\n      .m_axi_arlen    ( m_axi_arlen    ) ,\n      .m_axi_arsize   ( m_axi_arsize   ) ,\n      .m_axi_arburst  ( m_axi_arburst  ) ,\n      .m_axi_arlock   ( m_axi_arlock   ) ,\n      .m_axi_arcache  ( m_axi_arcache  ) ,\n      .m_axi_arprot   ( m_axi_arprot   ) ,\n      .m_axi_arqos    ( m_axi_arqos    ) ,\n      .m_axi_aruser   ( m_axi_aruser   ) ,\n      .m_axi_arregion ( m_axi_arregion ) ,\n      .m_axi_rid      ( m_axi_rid      ) ,\n      .m_axi_rdata    ( m_axi_rdata    ) ,\n      .m_axi_rresp    ( m_axi_rresp    ) ,\n      .m_axi_rlast    ( m_axi_rlast    ) ,\n      .m_axi_ruser    ( m_axi_ruser    ) \n    );\n    \n  end  // Reserve SI/MI branch\n\n  if ((C_REG_CONFIG_AW <= 9) && (C_RESERVE_MODE==0)) begin : aw\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 15) && (C_RESERVE_MODE==0)) begin : aw15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 16) && (C_RESERVE_MODE==0)) begin : aw16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) \n    )\n    aw_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if ((C_REG_CONFIG_W <= 9) && (C_RESERVE_MODE==0)) begin : w\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 15) && (C_RESERVE_MODE==0)) begin : w15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 16) && (C_RESERVE_MODE==0)) begin : w16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) \n    )\n    w_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if ((C_REG_CONFIG_B <= 9) && (C_RESERVE_MODE==0)) begin : b\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if ((C_REG_CONFIG_B == 15) && (C_RESERVE_MODE==0)) begin : b15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if ((C_REG_CONFIG_B == 16) && (C_RESERVE_MODE==0)) begin : b16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) \n    )\n    b_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if ((C_REG_CONFIG_AR <= 9) && (C_RESERVE_MODE==0)) begin : ar\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 15) && (C_RESERVE_MODE==0)) begin : ar15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 16) && (C_RESERVE_MODE==0)) begin : ar16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) \n    )\n    ar_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if ((C_REG_CONFIG_R <= 9) && (C_RESERVE_MODE==0)) begin : r\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 15) && (C_RESERVE_MODE==0)) begin : r15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 16) && (C_RESERVE_MODE==0)) begin : r16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) \n    )\n    r_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 4844}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(1),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(1),\n    .C_REG_CONFIG_AR(1),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"axi_register_slice,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"axi_register_slice,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=16,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=1,C_REG_CONFIG_W=1,\\\nC_REG_CONFIG_B=1,C_REG_CONFIG_AR=1,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(1),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(1),\n    .C_REG_CONFIG_AR(1),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_master #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_SUPPORTS_NARROW = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1,\n   parameter [C_AXI_ADDR_WIDTH-1:0] C_AXI_ADDR = 0,  // Base address\n   parameter integer C_NUM_ADDR = 1,  // Number of address iterations; range 1..2**16 (fixed increment = 32'h10000\n   parameter integer C_NUM_ID = 1,  // Number of ID iterations; range 1..2**C_ID_WIDTH (base = 0; fixed increment = 1)\n   parameter integer C_NUM_LEN = 1,  // Number of LEN iterations; range 1..9 (base = 0; value = 2**i - 1)\n   parameter integer C_NUM_TRANS = 1  // Number of transactions; range >=1 (read and write)\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_awvalid,\n  input  wire                            m_axi_awready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_awburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_awlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_awlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_awid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]    m_axi_awuser = 'b0,\n  /**************** Write Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_wid,\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]      m_axi_wdata,\n  (* dont_touch=\"true\" *) output reg [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb = {(C_AXI_DATA_WIDTH/8){1'b1}},\n  (* dont_touch=\"true\" *) output wire                             m_axi_wvalid,\n  input  wire                            m_axi_wready,\n  (* dont_touch=\"true\" *) output wire                             m_axi_wlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]     m_axi_wuser = 'b0,\n  /**************** Write Response Channel Signals ****************/\n  input  wire [2-1:0]                    m_axi_bresp,\n  input  wire                            m_axi_bvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_bready,\n  input  wire [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]     m_axi_buser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_bid,\n  /**************** Read Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_arvalid,\n  input  wire                            m_axi_arready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_arburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_arlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_arlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_arid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]    m_axi_aruser = 'b0,\n  /**************** Read Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]      m_axi_rdata,\n  input  wire [2-1:0]                    m_axi_rresp,\n  input  wire                            m_axi_rvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_rready,\n  input  wire                            m_axi_rlast,\n  input  wire [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]     m_axi_ruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_rid,\n  /**************** System Signals ****************/\n  input  wire                            aclk,\n  input  wire                            aresetn\n  );\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n  localparam integer  P_NUM_ID_LOG = f_ceil_log2(C_NUM_ID);\n  localparam integer  P_NUM_ADDR_LOG = f_ceil_log2(C_NUM_ADDR);\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL==0 ? 8 : C_AXI_PROTOCOL==1 ? 4 : 1);\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer               P_M_AXI_DATA_BYTES = (C_AXI_DATA_WIDTH / 8);\n  localparam integer               P_M_AXI_DONE_WIDTH = f_ceil_log2(C_NUM_TRANS<2?2:C_NUM_TRANS);\n  localparam integer               P_M_AXI_SIZE = f_ceil_log2(C_AXI_DATA_WIDTH)-3;\n\n  /**************** Internal Wires/Regs - Global ****************/\n   wire                            done;\n    wire                            dummy ;\n  reg                         done_i;\n  reg                         done_sel;\n  wire                         done_cycle;\n  reg                          done_d1 = 1'b0;\n  reg                   areset = 1'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] arcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] rcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [3:0]                    acc_r_i = 4'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] awcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] wcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] bcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [2:0]                    acc_b_i = 3'b0;\n\n  // Register Reset\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    \n    /**************** Internal Wires/Regs - Read Channels ****************/\n    wire                         read_xaction_done_i;\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_arid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_ADDR_WIDTH:0]      araddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  arprot_i = 3'b0;\n    reg [3-1:0]                  arsize_i = 3'b0;\n    reg [2-1:0]                  arburst_i = 2'b0;\n    reg [4-1:0]                  arcache_i = 4'b0;\n    reg [2-1:0]                  arlock_i = 2'b0;\n    reg [P_LEN_WIDTH-1:0]     arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [4-1:0]                  arqos_i = 4'b0;\n    reg [P_ID_WIDTH-1:0]        arid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [2-1:0]                  rresp_i = 2'b00;\n    reg [C_AXI_RUSER_WIDTH:0]   ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      rid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_arvalid_i = 1'b0;\n    reg                        m_axi_rready_i = 1'b0;\n    reg [P_NUM_ADDR_LOG:0]    araddr_cnt = 0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign read_xaction_done_i = m_axi_rvalid && m_axi_rready_i && ((C_AXI_PROTOCOL==2)?1'b1:m_axi_rlast);\n    assign m_axi_arvalid = m_axi_arvalid_i;\n    assign m_axi_rready = m_axi_rready_i;\n    assign m_axi_araddr = m_axi_araddr_i;\n    assign m_axi_arlen = m_axi_arlen_i;\n    always @(posedge aclk) begin\n      m_axi_arprot <= dummy ? arprot_i : 3'b000;\n      m_axi_arsize <= dummy ? arsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_arburst <= dummy ? arburst_i : 2'b01;\n      m_axi_arlock <= dummy ? arlock_i : 1'b0;\n      m_axi_arcache <= dummy ? arcache_i : 4'h3;\n      m_axi_arqos <= dummy  ? arqos_i : 4'h0;\n      m_axi_aruser <= dummy ? aruser_i : 0;\n    end\n  \n    //**********************************************\n    // Read Channel: ARVALID, ARADDR, ARLEN, RREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_arvalid_i <= 1'b0;\n        arcnt_i <= C_NUM_TRANS;\n        m_axi_arlen_i <= 0;\n        m_axi_araddr_i <= C_AXI_ADDR;\n        m_axi_arid_i <= 1;\n        araddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_arready & m_axi_arvalid_i) begin\n          arcnt_i <= arcnt_i - 1;\n          if (araddr_cnt == 1) begin\n            m_axi_araddr_i <= dummy ? araddr_i : C_AXI_ADDR;\n            araddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_araddr_i <= m_axi_araddr_i + 32'h10000;\n            araddr_cnt <= araddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_arlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_arlen_i <= dummy ? arlen_i : 0;\n          end else begin\n            m_axi_arlen_i <= (m_axi_arlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_arid_i == C_NUM_ID)) begin\n            m_axi_arid <= dummy ? arid_i : 0;\n            m_axi_arid_i <= 1;\n          end else begin\n            m_axi_arid <= m_axi_arid_i;\n            m_axi_arid_i <= m_axi_arid_i + 1;\n          end\n          if (arcnt_i == 1) begin\n            m_axi_arvalid_i <= 1'b0;\n          end\n        end else if (arcnt_i != 0) begin\n          m_axi_arvalid_i <= 1'b1;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      araddr_i <= {araddr_i, ~araddr_i[C_AXI_ADDR_WIDTH]};\n      arprot_i <= {arprot_i, ~arprot_i[3-1]};\n      arlen_i <= {arlen_i, ~arlen_i[P_LEN_WIDTH-1]};\n      arsize_i <= {arsize_i, ~arsize_i[3-1]};\n      arburst_i <= {arburst_i, ~arburst_i[2-1]};\n      arlock_i <= {arlock_i, ~arlock_i[2-1]};\n      arcache_i <= {arcache_i, ~arcache_i[4-1]};\n      arqos_i <= {arqos_i, ~arqos_i[4-1]};\n      aruser_i <= {aruser_i, ~aruser_i[C_AXI_ARUSER_WIDTH]};\n      arid_i <= {arid_i, ~arid_i[P_ID_WIDTH-1]};\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        m_axi_rready_i <= 1'b0;\n        rcnt_i <= C_NUM_TRANS;\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        rresp_i <= {2{1'b0}};\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n        rid_i <= {P_ID_WIDTH{1'b0}};\n        acc_r_i <= 4'b0;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_rvalid & m_axi_rready_i) begin\n          m_axi_rready_i <= 1'b0;\n          rdata_i <= m_axi_rdata;\n            acc_r_i[0] <= rdata_i[0];\n          rresp_i <= m_axi_rresp;\n            acc_r_i[1] <= rresp_i[0];\n          ruser_i <= m_axi_ruser;\n            acc_r_i[2] <= ruser_i[0];\n          rid_i <= m_axi_rid;\n            acc_r_i[3] <= rid_i[0];\n          if (m_axi_rlast) begin\n            rcnt_i <= rcnt_i - 1;\n          end\n        end else begin\n          rdata_i <= rdata_i>>1;\n          rresp_i <= rresp_i>>1;\n          ruser_i <= ruser_i>>1;\n          rid_i <= rid_i>>1;\n          acc_r_i <= acc_r_i>>1;\n          if (m_axi_rvalid) begin\n            m_axi_rready_i <= 1'b1;\n          end\n        end\n      end\n    end\n    \n    assign dummy = rdata_i[0];\n    \n    \n\n    /**************** Internal Wires/Regs - Write Channels ****************/\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_awid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [8-1:0]                  xfer_w_i = 8'h00;\n    wire                         write_burst_done_i;\n    reg [C_AXI_ADDR_WIDTH:0]      awaddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  awprot_i = 3'b0;\n    reg [P_LEN_WIDTH-1:0]     awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [3-1:0]                  awsize_i = 3'b0;\n    reg [2-1:0]                  awburst_i = 2'b0;\n    reg [4-1:0]                  awcache_i = 4'b0;\n    reg [2-1:0]                  awlock_i = 2'b0;\n    reg [4-1:0]                  awqos_i = 4'b0;\n    reg [P_ID_WIDTH:0]        awid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_AWUSER_WIDTH:0]    awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg [P_M_AXI_DATA_BYTES-1:0] wstrb_i = {P_M_AXI_DATA_BYTES{1'b1}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]        wid_i = {P_ID_WIDTH{1'b0}};\n    reg [2-1:0]                  bresp_i = 2'b00;\n    reg [C_AXI_BUSER_WIDTH:0]   buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      bid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_awvalid_i = 1'b0;\n    reg                        m_axi_wvalid_i = 1'b0;\n    reg                        m_axi_bready_i = 1'b0;\n    reg                        m_axi_wlast_i = 1'b0;\n    reg                        m_axi_wid_i = {P_ID_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]     wlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [P_NUM_ADDR_LOG:0]    awaddr_cnt = 0;\n  \n    /**************** Assign Write Channel Outputs ****************/\n    assign m_axi_wdata = {wdata_i, done};\n    assign write_burst_done_i = m_axi_wready && m_axi_wvalid_i && ((C_AXI_PROTOCOL==2) || m_axi_wlast_i);\n    assign m_axi_awvalid = m_axi_awvalid_i;\n    assign m_axi_wvalid = m_axi_wvalid_i;\n    assign m_axi_bready = m_axi_bready_i;\n    assign m_axi_wlast = m_axi_wlast_i;\n    assign m_axi_awaddr = m_axi_awaddr_i;\n    assign m_axi_awlen = m_axi_awlen_i;\n    assign m_axi_wid = m_axi_wid_i;\n    always @(posedge aclk) begin\n      m_axi_awprot <= dummy ? awprot_i : 3'b000;\n      m_axi_awsize <= dummy ? awsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_awburst <= dummy ? awburst_i : 2'b01;\n      m_axi_awlock <= dummy ? awlock_i : 1'b0;\n      m_axi_awcache <= dummy ? awcache_i : 4'h3;\n      m_axi_awqos <= dummy ? awqos_i : 4'h0;\n      m_axi_wstrb <= dummy ? wstrb_i : {P_M_AXI_DATA_BYTES{1'b1}};\n      m_axi_awuser <= dummy ?  awuser_i : 0;\n      m_axi_wuser <= dummy ?  wuser_i : 0;\n    end\n  \n    //**********************************************\n    // Write Channel: AWVALID, AWADDR, AWLEN, WVALID, WLAST, BREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_awvalid_i <= 1'b0;\n        m_axi_wvalid_i <= 1'b0;\n        awcnt_i <= C_NUM_TRANS;\n        wcnt_i <= C_NUM_TRANS;\n        xfer_w_i <= 8'h00;\n        m_axi_awlen_i <= 0;\n        m_axi_awaddr_i <= C_AXI_ADDR;\n        m_axi_awid_i <= 1;\n        m_axi_wid_i <= 0;\n        m_axi_wlast_i <= 1'b0;\n        wlen_i <= 0;\n        wid_i <= 0;\n        awaddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_awvalid_i <= 1'b0;\n          awcnt_i <= awcnt_i - 1;\n          if (awaddr_cnt == 1) begin\n            m_axi_awaddr_i <= dummy ? awaddr_i : C_AXI_ADDR;\n            awaddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_awaddr_i <= m_axi_awaddr_i + 32'h10000;\n            awaddr_cnt <= awaddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_awlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_awlen_i <= dummy ? awlen_i : 0;\n          end else begin\n            m_axi_awlen_i <= (m_axi_awlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_awid_i == C_NUM_ID)) begin\n            m_axi_awid <= dummy ? awid_i : 0;\n            m_axi_awid_i <= 1;\n          end else begin\n            m_axi_awid <= m_axi_awid_i;\n            m_axi_awid_i <= m_axi_awid_i + 1;\n          end\n        end else if (~m_axi_wvalid_i) begin\n          if (awcnt_i != 0) begin\n            m_axi_awvalid_i <= 1'b1;\n          end\n        end\n  \n        /**************** Write Data Channel ****************/\n\n        if (m_axi_wready && m_axi_wvalid_i) begin\n          xfer_w_i <= xfer_w_i - 1'b1;\n          if (m_axi_wlast_i) begin\n            m_axi_wvalid_i <= 1'b0;\n            wcnt_i <= wcnt_i - 1'b1;\n          end else begin\n            m_axi_wlast_i <=  (xfer_w_i == 1);\n          end\n        end else if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_wvalid_i <= 1'b1;\n          xfer_w_i <= m_axi_awlen_i;\n          m_axi_wlast_i <= (m_axi_awlen_i==0);\n          m_axi_wid_i <= m_axi_awid_i;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: WDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        wdata_i <= (m_axi_wvalid_i && m_axi_wready) ? {wdata_i[C_AXI_DATA_WIDTH-2 : 0], ~wdata_i[C_AXI_DATA_WIDTH-1]} : wdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      awaddr_i <= {awaddr_i, ~awaddr_i[C_AXI_ADDR_WIDTH]};\n      awprot_i <= {awprot_i[3-2:0], ~awprot_i[3-1]};\n      wstrb_i <= {wstrb_i, ~wstrb_i[C_AXI_DATA_WIDTH/8-1]};\n      awlen_i <= {awlen_i, ~awlen_i[P_LEN_WIDTH-1]};\n      awsize_i <= {awsize_i, ~awsize_i[3-1]};\n      awburst_i <= {awburst_i, ~awburst_i[2-1]};\n      awlock_i <= {awlock_i, ~awlock_i[2-1]};\n      awcache_i <= {awcache_i, ~awcache_i[4-1]};\n      awqos_i <= {awqos_i, ~awqos_i[4-1]};\n      awid_i <= {awid_i, ~awid_i[P_ID_WIDTH-1]};\n      awuser_i <= {awuser_i, ~awuser_i[C_AXI_AWUSER_WIDTH]};\n      wuser_i <= {wuser_i, ~wuser_i[C_AXI_WUSER_WIDTH]};\n    end\n  \n    //**********************************************\n    // Write Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_bready_i <= 1'b0;\n        bcnt_i <= C_NUM_TRANS;\n        bresp_i <= {2{1'b0}};\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n        bid_i <= {P_ID_WIDTH{1'b0}};\n        acc_b_i <= 3'b0;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_bvalid & m_axi_bready_i) begin\n          m_axi_bready_i <= 1'b0;\n          bresp_i <= m_axi_bresp;\n            acc_b_i[0] <= bresp_i[0];\n          buser_i <= m_axi_buser;\n            acc_b_i[1] <= buser_i[0];\n          bid_i <= m_axi_bid;\n            acc_b_i[2] <= bid_i[0];\n          bcnt_i <= bcnt_i - 1;\n        end else begin\n          bresp_i <= bresp_i>>1;\n          buser_i <= buser_i>>1;\n          bid_i <= bid_i>>1;\n          acc_b_i <= acc_b_i>>1;\n          if (m_axi_bvalid) begin\n            m_axi_bready_i <= 1'b1;\n          end\n        end\n      end\n    end\n\n\n  //**********************************************\n  // Assert Done\n  //**********************************************\n  always @(posedge aclk) begin\n    if (~aresetn) begin\n      done_d1 <= 1'b0;\n    end else begin\n      done_d1 <= done_i;\n    end\n  end\n\n  assign done = done_sel ? done_i : done_d1;\n  assign done_cycle = done_i & ~done_d1;\n  \n  always @ * begin\n    if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_readonly_done\n       done_i = rcnt_i==0;\n       done_sel = acc_r_i[0];\n    end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_writeonly_done\n       done_i = bcnt_i==0;\n       done_sel = acc_b_i[0];\n    end else begin : gen_readwrite_done\n       done_i = (rcnt_i==0) && (bcnt_i==0);\n       done_sel = acc_r_i[0] ^ acc_b_i[0];\n    end\n  end\n  \nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n  input  wire [3-1:0]                   s_axi_awprot,\n  input  wire                           s_axi_awvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_awready,\n  input  wire [3-1:0]                   s_axi_awsize,\n  input  wire [2-1:0]                   s_axi_awburst,\n  input  wire [4-1:0]                   s_axi_awcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_awlen,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_awlock,\n  input  wire [4-1:0]                   s_axi_awqos,\n  input  wire [4-1:0]                   s_axi_awregion,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_awid,\n  input  wire [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]   s_axi_awuser,\n  /**************** Write Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n  input  wire                           s_axi_wvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_wready,\n  input  wire                           s_axi_wlast,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_wid,\n  input  wire [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]    s_axi_wuser,\n  /**************** Write Response Channel Signals ****************/\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_bresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_bvalid,\n  input  wire                           s_axi_bready,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]    s_axi_buser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_bid = 'b0,\n  /**************** Read Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n  input  wire [3-1:0]                   s_axi_arprot,\n  input  wire                           s_axi_arvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_arready,\n  input  wire [3-1:0]                   s_axi_arsize,\n  input  wire [2-1:0]                   s_axi_arburst,\n  input  wire [4-1:0]                   s_axi_arcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_arlock,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_arlen,\n  input  wire [4-1:0]                   s_axi_arqos,\n  input  wire [4-1:0]                   s_axi_arregion,\n  input  wire [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]   s_axi_aruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_arid,\n  /**************** Read Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_rresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rvalid,\n  input  wire                           s_axi_rready,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]    s_axi_ruser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_rid = 'b0,\n  /**************** System Signals ****************/\n  input  wire                           aclk,\n  input  wire                           aresetn\n   );\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL == 1) ? 4 : 8;\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer P_S_AXI_DATA_BYTES = 32/8;\n  localparam integer P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n\n  /**************** Internal Wires/Regs - Global ****************/\n  reg                   areset = 1'b0;\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    /**************** Internal Wires/Regs - Read Channels ****************/\n    reg [8-1:0]                   xfer_r_cnt = 8'h00;\n    reg [16-1:0]                  arcnt_i = 16'h0000;\n    wire                          read_xaction_done_i;\n    reg [C_AXI_DATA_WIDTH-1:0]     rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]      arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg                           arvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     araddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   arprot_i = 3'b000;\n    reg [3-1:0]                   arsize_i = 3'b000;\n    reg [2-1:0]                   arburst_i = 2'b00;\n    reg [4-1:0]                   arcache_i = 4'b0000;\n    reg [1-1:0]     arlock_i = 1'b0;\n    reg [4-1:0]                   arqos_i = 4'b0000;\n    reg [4-1:0]                   arregion_i = 4'b0000;\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_RUSER_WIDTH:0]     ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_ar_i = 9'b0;\n    reg                           s_axi_rvalid_i = 1'b0;\n    reg                           s_axi_arready_i = 1'b0;\n    reg                           s_axi_rlast_i = 1'b0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign s_axi_rdata = rdata_i;\n    assign read_xaction_done_i = (s_axi_rready && s_axi_rvalid_i && s_axi_rlast_i);\n    assign s_axi_rvalid = s_axi_rvalid_i;\n    assign s_axi_arready = s_axi_arready_i;\n    assign s_axi_rlast = s_axi_rlast_i;\n    //**********************************************\n    // Read Channel: ARREADY, RVALID, RLAST, RID\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        xfer_r_cnt <= 8'h00;\n        arcnt_i <= 16'h0000;\n        arlen_i <= {P_LEN_WIDTH{1'b0}};\n        s_axi_rlast_i <= 1'b0;\n      end else begin\n        /**************** Read Address Channel ****************/\n        // arready\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_arready_i <= 1'b0;\n          arcnt_i <= arcnt_i + 1'b1;\n        end else if (~s_axi_rvalid_i) begin\n          s_axi_arready_i <= 1'b1;\n        end\n  \n        /**************** Read Data Channel ****************/\n        // rvalid\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_rvalid_i <= 1'b1;\n          s_axi_rid <= s_axi_arid;\n          s_axi_ruser <= ruser_i;\n        end else if(read_xaction_done_i) begin\n          s_axi_rvalid_i <= 1'b0;\n        end\n  \n        // rlast\n        if(s_axi_rready && s_axi_rvalid_i) begin\n          xfer_r_cnt <= xfer_r_cnt - 1;\n          if(xfer_r_cnt == 1) begin\n            s_axi_rlast_i <= 1'b1;\n          end\n        end else if(s_axi_arready_i && s_axi_arvalid) begin\n          xfer_r_cnt <= s_axi_arlen;\n          s_axi_rlast_i <= (s_axi_arlen==0);\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Read Channel: RDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        rdata_i <= (s_axi_rready && s_axi_rvalid_i) ? {rdata_i[C_AXI_DATA_WIDTH-2 : 0], ~rdata_i[C_AXI_DATA_WIDTH-1]} : rdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_rresp <= {2{1'b0}};\n      end else if (~s_axi_rvalid_i) begin\n        s_axi_rresp <= {acc_ar_i[0], 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n      end else begin\n        ruser_i <= (s_axi_arready_i && s_axi_arvalid) ? {ruser_i, ~ruser_i[C_AXI_RUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        araddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        arprot_i <= {3{1'b0}};\n        arsize_i <= {3{1'b0}};\n        arburst_i <= {2{1'b0}};\n        arcache_i <= {4{1'b0}};\n        arlock_i <= {1{1'b0}};\n        arqos_i <= {4{1'b0}};\n        arregion_i <= {4{1'b0}};\n        aruser_i <= {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n        acc_ar_i <= 9'b0;\n      end else if (s_axi_arvalid) begin\n        // Register Inputs\n        araddr_i <= s_axi_araddr;\n          acc_ar_i[0] <= araddr_i[0];\n        arprot_i <= s_axi_arprot;\n          acc_ar_i[1] <= arprot_i[0];\n        arsize_i <= s_axi_arsize;\n          acc_ar_i[2] <= arsize_i[0];\n        arburst_i <= s_axi_arburst;\n          acc_ar_i[3] <= arburst_i[0];\n        arcache_i <= s_axi_arcache;\n          acc_ar_i[4] <= arcache_i[0];\n        arlock_i <= s_axi_arlock;\n          acc_ar_i[5] <= arlock_i[0];\n        arqos_i <= s_axi_arqos;\n          acc_ar_i[6] <= arqos_i[0];\n        arregion_i <= s_axi_arregion;\n          acc_ar_i[7] <= arregion_i[0];\n        aruser_i <= s_axi_aruser;\n          acc_ar_i[8] <= aruser_i[0];\n      end else begin\n        araddr_i <= araddr_i>>1;\n        arprot_i <= arprot_i>>1;\n        arsize_i <= arsize_i>>1;\n        arburst_i <= arburst_i>>1;\n        arcache_i <= arcache_i>>1;\n        arlock_i <= arlock_i>>1;\n        arqos_i <= arqos_i>>1;\n        arregion_i <= arregion_i>>1;\n        aruser_i <= aruser_i>>1;\n        acc_ar_i <= acc_ar_i>>1;\n      end\n    end\n  \n  \n    /**************** Internal Wires/Regs - Write Channels ****************/\n    wire                          write_burst_done_i;\n    reg [16-1:0]                  awcnt_i = 16'h0000;\n    reg                           awvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     awaddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   awprot_i = 3'b000;\n    reg [3-1:0]                   awsize_i = 3'b000;\n    reg [2-1:0]                   awburst_i = 2'b00;\n    reg [4-1:0]                   awcache_i = 4'b0000;\n    reg [P_LEN_WIDTH-1:0]      awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [1-1:0]     awlock_i = 1'b0;\n    reg [4-1:0]                   awqos_i = 4'b0000;\n    reg [4-1:0]                   awregion_i = 4'b0000;\n    reg [C_AXI_AWUSER_WIDTH:0]     awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg                           wvalid_i = 1'b0;\n    reg [C_AXI_DATA_WIDTH-1:0]     wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH/8-1:0]   wstrb_i = {(C_AXI_DATA_WIDTH/8){1'b0}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_BUSER_WIDTH:0]     buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_aw_i = 9'b0;\n    reg [3:0]                     acc_w_i = 4'b0;\n    reg                           s_axi_bvalid_i = 1'b0;\n    reg                           s_axi_awready_i = 1'b0;\n    reg                           s_axi_wready_i = 1'b0;\n    /**************** Assign Write Channel Outputs ****************/\n    assign write_burst_done_i =s_axi_wready_i && s_axi_wvalid && ((C_AXI_PROTOCOL == 2) ? 1'b1 : s_axi_wlast);\n    assign s_axi_bvalid = s_axi_bvalid_i;\n    assign s_axi_awready = s_axi_awready_i;\n    assign s_axi_wready = s_axi_wready_i;\n  \n    //**********************************************\n    // Write Channel: AWREADY, WREADY, BVALID, BID\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awcnt_i <= 16'h0000;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        /**************** Write Address Channel ****************/\n        // awready\n        if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_awready_i <= 1'b0;\n          awcnt_i <= awcnt_i + 1'b1;\n          s_axi_bid <= s_axi_awid;\n          s_axi_buser <= buser_i;\n        end else if(~s_axi_wready_i & ~s_axi_bvalid_i) begin\n          s_axi_awready_i <= 1'b1;\n        end\n  \n        /**************** Write Data Channel ****************/\n        // wready\n        if(write_burst_done_i) begin\n          s_axi_wready_i <= 1'b0;\n        end else if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_wready_i <= 1'b1;\n        end\n  \n        /**************** Write Response Channel ****************/\n        // bvalid\n        if(write_burst_done_i) begin\n          s_axi_bvalid_i <= 1'b1;\n        end else if(s_axi_bready && s_axi_bvalid_i) begin\n          s_axi_bvalid_i <= 1'b0;\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Write Channel: BRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_bresp <= {2{1'b0}};\n      end else if (~s_axi_bvalid_i) begin\n        s_axi_bresp <= {(acc_aw_i[0] ^ acc_w_i[0]), 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: BUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (aresetn) begin\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n      end else begin\n        buser_i <= (s_axi_awready_i && s_axi_awvalid) ? {buser_i, ~buser_i[C_AXI_BUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Write Address Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awaddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        awprot_i <= {3{1'b0}};\n        awsize_i <= {3{1'b0}};\n        awburst_i <= {2{1'b0}};\n        awcache_i <= {4{1'b0}};\n        awlen_i <= {P_LEN_WIDTH{1'b0}};\n        awlock_i <= {1{1'b0}};\n        awqos_i <= {4{1'b0}};\n        awregion_i <= {4{1'b0}};\n        awuser_i <= {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n        acc_aw_i <= 9'b0;\n      end else if (s_axi_awvalid) begin\n        // Register Inputs\n        awaddr_i <= s_axi_awaddr;\n          acc_aw_i[0] <= awaddr_i[0];\n        awprot_i <= s_axi_awprot;\n          acc_aw_i[1] <= awprot_i[0];\n        awsize_i <= s_axi_awsize;\n          acc_aw_i[2] <= awsize_i[0];\n        awburst_i <= s_axi_awburst;\n          acc_aw_i[3] <= awburst_i[0];\n        awcache_i <= s_axi_awcache;\n          acc_aw_i[4] <= awcache_i[0];\n        awlock_i <= s_axi_awlock;\n          acc_aw_i[5] <= awlock_i[0];\n        awqos_i <= s_axi_awqos;\n          acc_aw_i[6] <= awqos_i[0];\n        awregion_i <= s_axi_awregion;\n          acc_aw_i[7] <= awregion_i[0];\n        awuser_i <= s_axi_awuser;\n          acc_aw_i[8] <= awuser_i[0];\n      end else begin\n        awaddr_i <= awaddr_i>>1;\n        awprot_i <= awprot_i>>1;\n        awsize_i <= awsize_i>>1;\n        awburst_i <= awburst_i>>1;\n        awcache_i <= awcache_i>>1;\n        awlock_i <= awlock_i>>1;\n        awqos_i <= awqos_i>>1;\n        awregion_i <= awregion_i>>1;\n        awuser_i <= awuser_i>>1;\n        acc_aw_i <= acc_aw_i>>1;\n      end\n    end\n  \n    //**********************************************\n    // Write Data Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        wstrb_i <= {(C_AXI_DATA_WIDTH/8){1'b0}};\n        wuser_i <= {(C_AXI_WUSER_WIDTH+1){1'b0}};\n        acc_w_i <= 4'b0;\n      end else if (s_axi_wvalid) begin\n        // Register Inputs\n        wdata_i <= s_axi_wdata;\n          acc_w_i[0] <= wdata_i[0];\n        wstrb_i <= s_axi_wstrb;\n          acc_w_i[1] <= wstrb_i[0];\n        wuser_i <= s_axi_wuser;\n          acc_w_i[2] <= wuser_i[0];\n      end else begin\n        wdata_i <= wdata_i>>1;\n        wstrb_i <= wstrb_i>>1;\n        wuser_i <= wuser_i>>1;\n        acc_w_i <= acc_w_i>>1;\n      end\n    end\n  \nendmodule\n\n\n\n//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_22_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \n(* autopipeline_module=\"yes\" *)\nmodule axi_register_slice_v2_1_22_auto_slr #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n    wire                    handshake_pipe;\n    wire                    ready_pipe;\n    wire [C_DATA_WIDTH-1:0] payload_pipe;\n    (* keep=\"true\" *)                                                                reg  s_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  s_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  s_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  s_areset_resp2 = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  m_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  m_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_areset_resp2 = 1'b0;\n    \n  // Global Reset pipelining\n  \n    always @(posedge ACLK) begin\n      s_aclear       <= ~ARESETN;\n      s_areset_fwd   <= ~ARESETN; \n      s_areset_resp  <= s_areset_fwd;  // Auto-pipeline\n      s_areset_resp2 <= s_areset_resp; // Auto-pipeline\n    end\n    \n    always @(posedge ACLK) begin\n      m_aclear       <= ~ARESETN;\n      m_areset_fwd   <= ~ARESETN; \n      m_areset_resp  <= m_areset_fwd;  // Auto-pipeline\n      m_areset_resp2 <= m_areset_resp; // Auto-pipeline\n    end\n    \n  // Source-side submodule\n    \n    axi_register_slice_v2_1_22_auto_src #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_src\n      (\n       .ACLK             (ACLK),    \n       .s_aclear         (s_aclear),\n       .s_areset_resp2   (s_areset_resp2),  \n       .S_VALID          (S_VALID),  \n       .S_READY          (S_READY), \n       .S_PAYLOAD_DATA   (S_PAYLOAD_DATA),\n       .ready_pipe        (ready_pipe), \n       .handshake_pipe    (handshake_pipe),\n       .payload_pipe      (payload_pipe)  \n      );\n    \n  // Destination-side submodule\n    \n    axi_register_slice_v2_1_22_auto_dest #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_dest\n      (\n       .ACLK           (ACLK),    \n       .m_aclear       (m_aclear),\n       .m_areset_resp2 (m_areset_resp2),  \n       .M_READY        (M_READY), \n       .M_VALID        (M_VALID),  \n       .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n       .handshake_pipe  (handshake_pipe),\n       .ready_pipe      (ready_pipe),  \n       .payload_pipe    (payload_pipe)  \n      );\n    \nendmodule  // auto_slr\n\nmodule axi_register_slice_v2_1_22_auto_src #\n  (\n   parameter integer C_DATA_WIDTH = 32\n  )\n  (\n   input  wire ACLK,\n   input  wire s_aclear,\n   input  wire s_areset_resp2,\n   input  wire S_VALID,\n   input  wire ready_pipe,\n   output wire S_READY,\n   output wire handshake_pipe,\n   output wire  [C_DATA_WIDTH-1:0] payload_pipe,\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA\n   );\n    \n   (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  [C_DATA_WIDTH-1:0] payload_pipe_r;\n    (* keep=\"true\" *) reg [2:0] s_aresetn_resp4 = 3'b000;\n    wire s_aresetn_resp3;\n    wire s_aresetn_d;\n    wire s_aresetn_q;\n    wire s_handshake_d;\n    wire s_ready_i;\n    \n    assign S_READY = s_ready_i & s_aresetn_q;\n    assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;\n    assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;\n    assign payload_pipe = payload_pipe_r;\n    \n    always @(posedge ACLK or posedge s_aclear) begin\n      if (s_aclear) begin\n        s_aresetn_resp4 <= 3'b000;\n      end else begin\n        s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      payload_pipe_r <= S_PAYLOAD_DATA;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) s_aresetn_resp3_inst (\n        .Q   (s_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~s_areset_resp2)\n     );\n    \n    // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (s_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_aresetn_d)\n     );\n    \n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (handshake_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_handshake_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (s_ready_i),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (ready_pipe)\n     );\n    \nendmodule  // auto_src\n\nmodule axi_register_slice_v2_1_22_auto_dest #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   input  wire ACLK,\n   input  wire m_aclear,\n   input  wire m_areset_resp2,\n   input  wire M_READY,\n   input  wire handshake_pipe,\n   output wire ready_pipe,\n   output wire M_VALID,\n   input  wire [C_DATA_WIDTH-1:0] payload_pipe,\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n   );\n    \n    (* keep=\"true\" *) reg [2:0] m_aresetn_resp4 = 3'b000;\n    wire m_aresetn_resp3;\n    wire m_aresetn_d;\n    wire m_aresetn_q;\n    wire m_valid_i;\n    wire pop;\n    wire m_ready_d;\n    wire m_handshake_q;\n    reg  [C_DATA_WIDTH-1:0] m_payload_q;\n    \n    assign M_VALID = m_valid_i;\n    assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;\n    assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;\n    assign pop     = M_READY & m_valid_i;\n    \n    always @(posedge ACLK or posedge m_aclear) begin\n      if (m_aclear) begin\n        m_aresetn_resp4 <= 3'b000;\n      end else begin\n        m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      m_payload_q <= payload_pipe;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) m_aresetn_resp3_inst (\n        .Q   (m_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~m_areset_resp2)\n     );\n    \n    // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (m_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_aresetn_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (m_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (handshake_pipe)\n     );\n    \n    (* autopipeline_group=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (ready_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_ready_d)\n     );\n    \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  (5)  \n      )\n      srl_fifo\n      (\n       .aclk    (ACLK),    \n       .areset  (~m_aresetn_q),\n       .aclear  (m_aclear),  \n       .s_mesg  (m_payload_q),  \n       .s_valid (m_handshake_q), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      );\n    \nendmodule  // auto_dest\n\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      reg s_valid_d;\n      reg s_ready_d = 1'b0;\n      reg s_ready_reg = 1'b0;\n      reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_22_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_RESP_MIDDLE2_LATENCY = C_PIPELINES_SLAVE + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_22_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      .ACLK           (ACLK),\n      .ARESETN         (ARESETN),\n      .S_PAYLOAD_DATA (S_PAYLOAD_DATA),\n      .S_VALID        (S_VALID),\n      .S_READY        (S_READY),\n      .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n      .M_VALID        (M_VALID),\n      .M_READY        (M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_reset;\n    wire src_ready;\n    wire dummy_reset;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  ( C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( dummy_reset   ) ,\n        .laguna_s_reset_in  ( src_reset   ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset   ) ,\n        .laguna_m_reset_in  ( src_reset  ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset2   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n      \n  end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] mid_payload;\n    wire mid_handshake;\n    wire mid_ready;\n    wire mid_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n    wire dummy_reset3;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( mid_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( mid_reset    ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset3   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset3   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out (  dummy_reset2  ) ,\n        .laguna_m_reset_in  ( mid_reset   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE2_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( mid_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2   ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset3   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset3    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n   \n  generate\n\n  (* keep=\"true\" *) reg s_reset_dd = 1'b0;\n  (* keep=\"true\" *) reg m_reset_dd = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n  \n  assign laguna_s_reset_out = laguna_s_reset_out_i;\n  assign laguna_m_reset_out = laguna_m_reset_out_i;\n  \n  always @(posedge ACLK) begin\n    laguna_s_reset_in_d <= laguna_s_reset_in;\n    laguna_m_reset_in_d <= laguna_m_reset_in;\n    s_reset_dd <= laguna_s_reset_in_d;\n    m_reset_dd <= laguna_m_reset_in_d;\n    laguna_s_reset_out_i <= C_PIPELINES==0 ? laguna_m_reset_in_d : m_reset_dd;\n    laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;\n  end\n  \n  wire ACLEAR;\n  assign ACLEAR = ~ARESETN;\n  \n  if (1) begin : common\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire laguna_s_handshake_q;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, laguna_m_ready_d}; \n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else if (p==C_PIPELINES+1) begin\n          laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n\n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = handshake_i[C_PIPELINES];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_m_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* keep=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_22_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_m_reset_out = laguna_m_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_m_reset_in_d <= laguna_m_reset_in;\n      aresetn_d <= C_CHANNEL==P_FORWARD ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? areset_dly[15]  : laguna_m_reset_in_d;\n      laguna_m_reset_out_i <= areset_d;  // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n  \n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* keep=\"true\" *)  reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      ready_d <= {ready_d, laguna_m_ready_d}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid_q;\n      assign payload_valid_d = (p==0) ? (S_VALID & s_ready_i) : handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==C_PIPELINES) begin\n          laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else if (p==0) begin\n          payload_data <= S_PAYLOAD_DATA;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n      \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_s_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* keep=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_s_reset_out = laguna_s_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_s_reset_in_d <= laguna_s_reset_in;\n      aresetn_d <= C_CHANNEL==P_RESPONSE ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? laguna_s_reset_in_d : areset_dly[15];\n      laguna_s_reset_out_i <= areset_d;  // For forward channels, reflect laguna_s_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n\n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    wire laguna_s_handshake_q;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      laguna_s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n        \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n        \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)  \n      )\n      srl_fifo_0\n      (\n       .aclk    (ACLK),    \n       .areset  (areset_d),  \n       .aclear  (ACLEAR),\n       .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n       .s_valid (push), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      ); \n  \n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  reg areset_d = 1'b0;\n  reg [3:0] areset_dly = 4'b0;\n  always @(posedge ACLK) begin\n    areset_dly <= {4{~ARESETN}} | (areset_dly<<1);\n    areset_d <= areset_dly[3];\n  end\n  \n  if (1) begin : common\n    reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID & s_ready_i;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* keep=\"true\" *)  reg payload_valid = 1'b0;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          payload_data <= S_PAYLOAD_DATA;\n          payload_valid <= S_VALID & s_ready_i & ~areset_d;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n          payload_valid <= handshake_i[((p>0)?(p-1):0)];\n        end\n      end\n    end\n    \n    if (C_PIPELINES==0) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),\n         .aclear  (1'b0),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire                        aclear,  // Async clear\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    wire [1:0] state;  // State vector register\n    reg  [1:0] next;           // Next state value\n    wire [1:0] next_qual;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    reg  m_valid_d;\n    wire m_valid_q;\n    \n    assign m_valid = m_valid_q;\n    assign next_qual = areset ? K_EMPTY : next;\n    assign m_mesg  = mesg_reg;\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_mvalid_inst (\n        .Q   (m_valid_q),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (m_valid_d)\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state0_inst (\n        .Q   (state[0]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[0])\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state1_inst (\n        .Q   (state[1]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[1])\n     );\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      m_valid_d = m_valid_q & ~areset;\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid & ~areset) begin\n            next = K_HAS1;\n            m_valid_d = 1'b0;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              m_valid_d = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n              m_valid_d = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          m_valid_d = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      (* keep_hierarchy = \"yes\" *) axi_register_slice_v2_1_22_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule  // axic_reg_srl_fifo\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   //   16 -> Auto-pipelining\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_RESERVE_MODE = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n  \n  if (C_RESERVE_MODE==1) begin : gen_reserve_si\n  \n    axi_register_slice_v2_1_22_test_slave #(\n      .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n      .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n      .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n      .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n      .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n      .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n      .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n      .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n      .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .s_axi_awaddr(s_axi_awaddr),\n      .s_axi_awprot(s_axi_awprot),\n      .s_axi_awvalid(s_axi_awvalid),\n      .s_axi_awready(s_axi_awready),\n      .s_axi_awsize(s_axi_awsize),\n      .s_axi_awburst(s_axi_awburst),\n      .s_axi_awcache(s_axi_awcache),\n      .s_axi_awlen(s_axi_awlen),\n      .s_axi_awlock(s_axi_awlock),\n      .s_axi_awqos(s_axi_awqos),\n      .s_axi_awregion(s_axi_awregion),\n      .s_axi_awid(s_axi_awid),\n      .s_axi_awuser(s_axi_awuser),\n      .s_axi_wdata(s_axi_wdata),\n      .s_axi_wstrb(s_axi_wstrb),\n      .s_axi_wvalid(s_axi_wvalid),\n      .s_axi_wready(s_axi_wready),\n      .s_axi_wlast(s_axi_wlast),\n      .s_axi_wid(s_axi_wid),\n      .s_axi_wuser(s_axi_wuser),\n      .s_axi_bresp(s_axi_bresp),\n      .s_axi_bvalid(s_axi_bvalid),\n      .s_axi_bready(s_axi_bready),\n      .s_axi_buser(s_axi_buser),\n      .s_axi_bid(s_axi_bid),\n      .s_axi_araddr(s_axi_araddr),\n      .s_axi_arprot(s_axi_arprot),\n      .s_axi_arvalid(s_axi_arvalid),\n      .s_axi_arready(s_axi_arready),\n      .s_axi_arsize(s_axi_arsize),\n      .s_axi_arburst(s_axi_arburst),\n      .s_axi_arcache(s_axi_arcache),\n      .s_axi_arlock(s_axi_arlock),\n      .s_axi_arlen(s_axi_arlen),\n      .s_axi_arqos(s_axi_arqos),\n      .s_axi_arregion(s_axi_arregion),\n      .s_axi_aruser(s_axi_aruser),\n      .s_axi_arid(s_axi_arid),\n      .s_axi_rdata(s_axi_rdata),\n      .s_axi_rresp(s_axi_rresp),\n      .s_axi_rvalid(s_axi_rvalid),\n      .s_axi_rready(s_axi_rready),\n      .s_axi_rlast(s_axi_rlast),\n      .s_axi_ruser(s_axi_ruser),\n      .s_axi_rid(s_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign m_axi_awid     = 0;\n     assign m_axi_awaddr   = 0;\n     assign m_axi_awlen    = 0;\n     assign m_axi_awsize   = 0;\n     assign m_axi_awburst  = 0;\n     assign m_axi_awlock   = 0;\n     assign m_axi_awcache  = 0;\n     assign m_axi_awprot   = 0;\n     assign m_axi_awregion = 0;\n     assign m_axi_awqos    = 0;\n     assign m_axi_awuser   = 0;\n     assign m_axi_awvalid  = 0;\n     assign m_axi_wid      = 0;\n     assign m_axi_wdata    = 0;\n     assign m_axi_wstrb    = 0;\n     assign m_axi_wlast    = 0;\n     assign m_axi_wuser    = 0;\n     assign m_axi_wvalid   = 0;\n     assign m_axi_bready   = 0;\n     assign m_axi_arid     = 0;\n     assign m_axi_araddr   = 0;\n     assign m_axi_arlen    = 0;\n     assign m_axi_arsize   = 0;\n     assign m_axi_arburst  = 0;\n     assign m_axi_arlock   = 0;\n     assign m_axi_arcache  = 0;\n     assign m_axi_arprot   = 0;\n     assign m_axi_arregion = 0;\n     assign m_axi_arqos    = 0;\n     assign m_axi_aruser   = 0;\n     assign m_axi_arvalid  = 0;\n     assign m_axi_rready   = 0;\n      \n  end else if (C_RESERVE_MODE==2) begin : gen_reserve_mi\n    \n    axi_register_slice_v2_1_22_test_master #(\n    .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n    .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .m_axi_awaddr(m_axi_awaddr),\n      .m_axi_awprot(m_axi_awprot),\n      .m_axi_awvalid(m_axi_awvalid),\n      .m_axi_awready(m_axi_awready),\n      .m_axi_awsize(m_axi_awsize),\n      .m_axi_awburst(m_axi_awburst),\n      .m_axi_awcache(m_axi_awcache),\n      .m_axi_awlen(m_axi_awlen),\n      .m_axi_awlock(m_axi_awlock),\n      .m_axi_awqos(m_axi_awqos),\n      .m_axi_awid(m_axi_awid),\n      .m_axi_awuser(m_axi_awuser),\n      .m_axi_wid(m_axi_wid),\n      .m_axi_wdata(m_axi_wdata),\n      .m_axi_wstrb(m_axi_wstrb),\n      .m_axi_wvalid(m_axi_wvalid),\n      .m_axi_wready(m_axi_wready),\n      .m_axi_wlast(m_axi_wlast),\n      .m_axi_wuser(m_axi_wuser),\n      .m_axi_bresp(m_axi_bresp),\n      .m_axi_bvalid(m_axi_bvalid),\n      .m_axi_bready(m_axi_bready),\n      .m_axi_buser(m_axi_buser),\n      .m_axi_bid(m_axi_bid),\n      .m_axi_araddr(m_axi_araddr),\n      .m_axi_arprot(m_axi_arprot),\n      .m_axi_arvalid(m_axi_arvalid),\n      .m_axi_arready(m_axi_arready),\n      .m_axi_arsize(m_axi_arsize),\n      .m_axi_arburst(m_axi_arburst),\n      .m_axi_arcache(m_axi_arcache),\n      .m_axi_arlen(m_axi_arlen),\n      .m_axi_arlock(m_axi_arlock),\n      .m_axi_arqos(m_axi_arqos),\n      .m_axi_arid(m_axi_arid),\n      .m_axi_aruser(m_axi_aruser),\n      .m_axi_rdata(m_axi_rdata),\n      .m_axi_rresp(m_axi_rresp),\n      .m_axi_rvalid(m_axi_rvalid),\n      .m_axi_rready(m_axi_rready),\n      .m_axi_rlast(m_axi_rlast),\n      .m_axi_ruser(m_axi_ruser),\n      .m_axi_rid(m_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign s_axi_awready = 0;\n     assign s_axi_wready  = 0;\n     assign s_axi_bid     = 0;\n     assign s_axi_bresp   = 0;\n     assign s_axi_buser   = 0;\n     assign s_axi_bvalid  = 0;\n     assign s_axi_arready = 0;\n     assign s_axi_rid     = 0;\n     assign s_axi_rdata   = 0;\n     assign s_axi_rresp   = 0;\n     assign s_axi_rlast   = 0;\n     assign s_axi_ruser   = 0;\n     assign s_axi_rvalid  = 0;\n\n  end else begin : gen_reg_slice  // Any normal reg-slice mode\n\n    axi_infrastructure_v1_1_0_axi2vector #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    axi2vector_0 ( \n      .s_axi_awid      ( s_axi_awid      ) ,\n      .s_axi_awaddr    ( s_axi_awaddr    ) ,\n      .s_axi_awlen     ( s_axi_awlen     ) ,\n      .s_axi_awsize    ( s_axi_awsize    ) ,\n      .s_axi_awburst   ( s_axi_awburst   ) ,\n      .s_axi_awlock    ( s_axi_awlock    ) ,\n      .s_axi_awcache   ( s_axi_awcache   ) ,\n      .s_axi_awprot    ( s_axi_awprot    ) ,\n      .s_axi_awqos     ( s_axi_awqos     ) ,\n      .s_axi_awuser    ( s_axi_awuser    ) ,\n      .s_axi_awregion  ( s_axi_awregion  ) ,\n      .s_axi_wid       ( s_axi_wid       ) ,\n      .s_axi_wdata     ( s_axi_wdata     ) ,\n      .s_axi_wstrb     ( s_axi_wstrb     ) ,\n      .s_axi_wlast     ( s_axi_wlast     ) ,\n      .s_axi_wuser     ( s_axi_wuser     ) ,\n      .s_axi_bid       ( s_axi_bid       ) ,\n      .s_axi_bresp     ( s_axi_bresp     ) ,\n      .s_axi_buser     ( s_axi_buser     ) ,\n      .s_axi_arid      ( s_axi_arid      ) ,\n      .s_axi_araddr    ( s_axi_araddr    ) ,\n      .s_axi_arlen     ( s_axi_arlen     ) ,\n      .s_axi_arsize    ( s_axi_arsize    ) ,\n      .s_axi_arburst   ( s_axi_arburst   ) ,\n      .s_axi_arlock    ( s_axi_arlock    ) ,\n      .s_axi_arcache   ( s_axi_arcache   ) ,\n      .s_axi_arprot    ( s_axi_arprot    ) ,\n      .s_axi_arqos     ( s_axi_arqos     ) ,\n      .s_axi_aruser    ( s_axi_aruser    ) ,\n      .s_axi_arregion  ( s_axi_arregion  ) ,\n      .s_axi_rid       ( s_axi_rid       ) ,\n      .s_axi_rdata     ( s_axi_rdata     ) ,\n      .s_axi_rresp     ( s_axi_rresp     ) ,\n      .s_axi_rlast     ( s_axi_rlast     ) ,\n      .s_axi_ruser     ( s_axi_ruser     ) ,\n      .s_awpayload ( s_awpayload ) ,\n      .s_wpayload  ( s_wpayload  ) ,\n      .s_bpayload  ( s_bpayload  ) ,\n      .s_arpayload ( s_arpayload ) ,\n      .s_rpayload  ( s_rpayload  ) \n    );\n    \n    axi_infrastructure_v1_1_0_vector2axi #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    vector2axi_0 ( \n      .m_awpayload    ( m_awpayload    ) ,\n      .m_wpayload     ( m_wpayload     ) ,\n      .m_bpayload     ( m_bpayload     ) ,\n      .m_arpayload    ( m_arpayload    ) ,\n      .m_rpayload     ( m_rpayload     ) ,\n      .m_axi_awid     ( m_axi_awid     ) ,\n      .m_axi_awaddr   ( m_axi_awaddr   ) ,\n      .m_axi_awlen    ( m_axi_awlen    ) ,\n      .m_axi_awsize   ( m_axi_awsize   ) ,\n      .m_axi_awburst  ( m_axi_awburst  ) ,\n      .m_axi_awlock   ( m_axi_awlock   ) ,\n      .m_axi_awcache  ( m_axi_awcache  ) ,\n      .m_axi_awprot   ( m_axi_awprot   ) ,\n      .m_axi_awqos    ( m_axi_awqos    ) ,\n      .m_axi_awuser   ( m_axi_awuser   ) ,\n      .m_axi_awregion ( m_axi_awregion ) ,\n      .m_axi_wid      ( m_axi_wid      ) ,\n      .m_axi_wdata    ( m_axi_wdata    ) ,\n      .m_axi_wstrb    ( m_axi_wstrb    ) ,\n      .m_axi_wlast    ( m_axi_wlast    ) ,\n      .m_axi_wuser    ( m_axi_wuser    ) ,\n      .m_axi_bid      ( m_axi_bid      ) ,\n      .m_axi_bresp    ( m_axi_bresp    ) ,\n      .m_axi_buser    ( m_axi_buser    ) ,\n      .m_axi_arid     ( m_axi_arid     ) ,\n      .m_axi_araddr   ( m_axi_araddr   ) ,\n      .m_axi_arlen    ( m_axi_arlen    ) ,\n      .m_axi_arsize   ( m_axi_arsize   ) ,\n      .m_axi_arburst  ( m_axi_arburst  ) ,\n      .m_axi_arlock   ( m_axi_arlock   ) ,\n      .m_axi_arcache  ( m_axi_arcache  ) ,\n      .m_axi_arprot   ( m_axi_arprot   ) ,\n      .m_axi_arqos    ( m_axi_arqos    ) ,\n      .m_axi_aruser   ( m_axi_aruser   ) ,\n      .m_axi_arregion ( m_axi_arregion ) ,\n      .m_axi_rid      ( m_axi_rid      ) ,\n      .m_axi_rdata    ( m_axi_rdata    ) ,\n      .m_axi_rresp    ( m_axi_rresp    ) ,\n      .m_axi_rlast    ( m_axi_rlast    ) ,\n      .m_axi_ruser    ( m_axi_ruser    ) \n    );\n    \n  end  // Reserve SI/MI branch\n\n  if ((C_REG_CONFIG_AW <= 9) && (C_RESERVE_MODE==0)) begin : aw\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 15) && (C_RESERVE_MODE==0)) begin : aw15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 16) && (C_RESERVE_MODE==0)) begin : aw16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) \n    )\n    aw_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if ((C_REG_CONFIG_W <= 9) && (C_RESERVE_MODE==0)) begin : w\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 15) && (C_RESERVE_MODE==0)) begin : w15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 16) && (C_RESERVE_MODE==0)) begin : w16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) \n    )\n    w_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if ((C_REG_CONFIG_B <= 9) && (C_RESERVE_MODE==0)) begin : b\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if ((C_REG_CONFIG_B == 15) && (C_RESERVE_MODE==0)) begin : b15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if ((C_REG_CONFIG_B == 16) && (C_RESERVE_MODE==0)) begin : b16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) \n    )\n    b_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if ((C_REG_CONFIG_AR <= 9) && (C_RESERVE_MODE==0)) begin : ar\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 15) && (C_RESERVE_MODE==0)) begin : ar15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 16) && (C_RESERVE_MODE==0)) begin : ar16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) \n    )\n    ar_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if ((C_REG_CONFIG_R <= 9) && (C_RESERVE_MODE==0)) begin : r\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 15) && (C_RESERVE_MODE==0)) begin : r15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 16) && (C_RESERVE_MODE==0)) begin : r16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) \n    )\n    r_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 4844}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_register_slice_light (\n  aclk,\n  aresetn,\n  s_axi_awaddr,\n  s_axi_awprot,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_araddr,\n  s_axi_arprot,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awaddr,\n  m_axi_awprot,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_araddr,\n  m_axi_arprot,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [31 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [31 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [3 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [31 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [31 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [31 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [31 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [3 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [31 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [31 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(2),\n    .C_AXI_ID_WIDTH(1),\n    .C_AXI_ADDR_WIDTH(32),\n    .C_AXI_DATA_WIDTH(32),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(7),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(7),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(1'B0),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'H00000002),\n    .s_axi_awburst(2'B1),\n    .s_axi_awlock(1'B0),\n    .s_axi_awcache(4'B0),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(4'B0),\n    .s_axi_awqos(4'B0),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(1'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(1'B0),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(1'B0),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'H00000002),\n    .s_axi_arburst(2'B1),\n    .s_axi_arlock(1'B0),\n    .s_axi_arcache(4'B0),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(4'B0),\n    .s_axi_arqos(4'B0),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(),\n    .m_axi_awsize(),\n    .m_axi_awburst(),\n    .m_axi_awlock(),\n    .m_axi_awcache(),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(),\n    .m_axi_awqos(),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(1'B0),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(),\n    .m_axi_arsize(),\n    .m_axi_arburst(),\n    .m_axi_arlock(),\n    .m_axi_arcache(),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(),\n    .m_axi_arqos(),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(1'B0),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(1'B0),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 316}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"axi_register_slice_light,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"axi_register_slice_light,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=2,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_REG_CONFIG_\\\nW=7,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=7,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_register_slice_light (\n  aclk,\n  aresetn,\n  s_axi_awaddr,\n  s_axi_awprot,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_araddr,\n  s_axi_arprot,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awaddr,\n  m_axi_awprot,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_araddr,\n  m_axi_arprot,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [31 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [31 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [3 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [31 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [31 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [31 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [31 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [3 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [31 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [31 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(2),\n    .C_AXI_ID_WIDTH(1),\n    .C_AXI_ADDR_WIDTH(32),\n    .C_AXI_DATA_WIDTH(32),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(7),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(7),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(1'B0),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'H00000002),\n    .s_axi_awburst(2'B1),\n    .s_axi_awlock(1'B0),\n    .s_axi_awcache(4'B0),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(4'B0),\n    .s_axi_awqos(4'B0),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(1'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(1'B0),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(1'B0),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'H00000002),\n    .s_axi_arburst(2'B1),\n    .s_axi_arlock(1'B0),\n    .s_axi_arcache(4'B0),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(4'B0),\n    .s_axi_arqos(4'B0),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(),\n    .m_axi_awsize(),\n    .m_axi_awburst(),\n    .m_axi_awlock(),\n    .m_axi_awcache(),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(),\n    .m_axi_awqos(),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(1'B0),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(),\n    .m_axi_arsize(),\n    .m_axi_arburst(),\n    .m_axi_arlock(),\n    .m_axi_arcache(),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(),\n    .m_axi_arqos(),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(1'B0),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(1'B0),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 318}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_\\\nBITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_\\\nBITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_m00_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_m00_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=6,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_\\\nREG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_\\\nBITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_\\\nBITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_a493_wrapper.bd\n//Design : bd_a493_wrapper\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule bd_a493_wrapper\n   (S_BSCAN_bscanid_en,\n    S_BSCAN_capture,\n    S_BSCAN_drck,\n    S_BSCAN_reset,\n    S_BSCAN_runtest,\n    S_BSCAN_sel,\n    S_BSCAN_shift,\n    S_BSCAN_tck,\n    S_BSCAN_tdi,\n    S_BSCAN_tdo,\n    S_BSCAN_tms,\n    S_BSCAN_update,\n    clk);\n  input S_BSCAN_bscanid_en;\n  input S_BSCAN_capture;\n  input S_BSCAN_drck;\n  input S_BSCAN_reset;\n  input S_BSCAN_runtest;\n  input S_BSCAN_sel;\n  input S_BSCAN_shift;\n  input S_BSCAN_tck;\n  input S_BSCAN_tdi;\n  output S_BSCAN_tdo;\n  input S_BSCAN_tms;\n  input S_BSCAN_update;\n  input clk;\n\n  wire S_BSCAN_bscanid_en;\n  wire S_BSCAN_capture;\n  wire S_BSCAN_drck;\n  wire S_BSCAN_reset;\n  wire S_BSCAN_runtest;\n  wire S_BSCAN_sel;\n  wire S_BSCAN_shift;\n  wire S_BSCAN_tck;\n  wire S_BSCAN_tdi;\n  wire S_BSCAN_tdo;\n  wire S_BSCAN_tms;\n  wire S_BSCAN_update;\n  wire clk;\n\n  bd_a493 bd_a493_i\n       (.S_BSCAN_bscanid_en(S_BSCAN_bscanid_en),\n        .S_BSCAN_capture(S_BSCAN_capture),\n        .S_BSCAN_drck(S_BSCAN_drck),\n        .S_BSCAN_reset(S_BSCAN_reset),\n        .S_BSCAN_runtest(S_BSCAN_runtest),\n        .S_BSCAN_sel(S_BSCAN_sel),\n        .S_BSCAN_shift(S_BSCAN_shift),\n        .S_BSCAN_tck(S_BSCAN_tck),\n        .S_BSCAN_tdi(S_BSCAN_tdi),\n        .S_BSCAN_tdo(S_BSCAN_tdo),\n        .S_BSCAN_tms(S_BSCAN_tms),\n        .S_BSCAN_update(S_BSCAN_update),\n        .clk(clk));\nendmodule\n", "num_lines": 66}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nXvoWuyjysN5V55U4xsjyWg2bXI++8I1KAZgJ0eiQkY3L8ns1PfNti9fujmr8wvFQA6ycwh4K6mSp\nINQjc8TyLQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nbD05I2IKef08FLVG4C2ftkJOY+/UsvagxY6ta+A0N1USwLQivKTmRt7LJlQ+5UJqrfPvhHMyYrLN\nrjoJbClg85XfNTYCnalRVvg3mmCcjtJkCLf6S5E9Q6UF92b6bwgtMTsr0BndJhdItlJtr0dYZtoP\nAEskMBthh6RdNMkZ3CA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nvLo4Yp/zX6HvZ92VMA2Xr4EIhMWPNGq2EvSBkjiZd5sCSFAX+37MKx4gdbrsGvhUMl1njqvSaoP7\nKrAa29/cm3QWjPgpaCsR/MhnaG5+7aUvxA5iCqVHXdriMlgx9kzxkB9SD+mOC8XR5LtYA0bPhbZ9\njQzWpWxdaOGYFF25DU0O9M7LMc7SLfKunYH/cQ91D37m0LjgZh1/uZv8chFzvCBbkHqUU0qi17/k\nZTWIIzqb1oycbuhZZrWLl95xQ/aaTxZ30sONWd/axZtO3Cd57huCbCxLuOH51qq6erD9AVszmxL8\noEoM+KW88P1S3LJ/EcIQN4LU0/nyN/f7xEmy2w==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nj99ihkoCqIO9DhRZEJdEqlRF2P+IwS2wuYmoh3hWFCDXbmGTwTqc+3EMjxY8Z4uDixuazjlTMiEH\nCk4MdTkVZ55pPhFb4druHTap3Twn20B3SWvOy2nf84OpTkdBnbK4qagABgZXs9/mAtQxbF++/F6Y\n+OOE3yUNTWvHiVGvpTJavfADkB2CL5wEIlBSnYRwtLp71JokDsMvjq2l3o3hxAjvtdg9ej7NKx4I\nkAZfrpZH7Ebv2hfXrTVI2kDTAl5Etr+4oSqxIhABJut2WaeWJrsSbL+dz9s2ZmYDMb1BCQdRexck\nbMMvUaS+P7sSGuR9BTVynHOY5GdQelHO1aazQw==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nHuzbd0U90PuPKn40554Cnki98HuQSq7dg6ZyXufEWFHsji6rteNupAY3HQsuLpXjFVxsNlS4bcHj\nAAOnDcL0hCCVbSkU011mqhhlkFmWqeBBECGfP+T7/+l9KBu+9ynszhlhaVhmZMffsEuohDl5x084\nFnzFCdxrFyvqrOyWDac=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\neoQKmSsNWNEOJcUApe0UhUNGRDkxOLedPbjyDILgUJWMG+WVCpL9MC2MXZeZ6/oVwAYRlZTZsF1h\nUsVo6BO7IAuHuJAHeIQgEs2oIMj/I2qZxm9wUsOzWoK5/Jz4SS4sTE3TgOJXaX1GNAJlbUrCBtnM\nqIiavU164vZjX5BFoPGuHp4kICN8A4Wr9y2w2Lh0/IdiHjr/Ruk5PpVNyl7tW9EaSFY1AL4aoQpd\nRFDdUFRk4tMBtmFxi/B+pLVFE0hAUZnlVCsSaf4B0lN/m4CME7lgy7oXElp7ov4fMnD9VI8HLGMX\nWBSQjD8F6BB0Wblgm9lJNc0h0VqxxD4DbRleKA==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nyrn0K+G4SU1wuMdE7DJlKWErX/N5nCqD3+dP+4ONmo8yuM983VHfjLhCoeQMbM26e49U4PPdXcDR\ny0rRemqJACoi5H5NvzXohhKZI9q+WKME4TkhFzfKvIwyta1m/uNSe/A0+52Dzbg5uAxYihw0IdZR\nZMywfa3deZ8IUMz3kWSlMs1P4wESz2pKpdYGs0FpvovucuNn4OhZKH7RGX8z8Zy4E9juZRgnSQnX\nmvRtisgVB9uL2J0vl9XjW/1990VYZi0nrZJ8gQL38HLTz62vDuMuYjiFbbnDCujJNKOCHh/xJTdt\n73nsz+dY3We4tQdnxuESibzLQLGF1l8+d9FPDA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nJPIGH1v6BG8bvo+3pHrWlum+XEDtFDlKP+4Toq88+g/eeinS/p8A0zMVVYj4wfjGDhx3kGvJ9XAx\ngxYpezvlgnz+IEGWQzepCMSp4iHz9TEdGkc5LTQj50VJj4+HGz2Qhrw96Hw0c+5RDrv238ILy3p7\nuzIPIzxKEl8D7gK6b8ZPrzx95KMPuGZyju4JUHBWdjDx0hhhIl+L3Ju/bVyWaWd7w1xI0mreJtAN\noOdcObOESJpTuj0KqFtfA3UY7v9n9Lj/I/vMaPX7LnSIZuS+tHyiD8D+t+Kf6XiIl3sYDL9erP7t\nSpHvPfG9bOfGRxM7dmsvKj+XqHeXg23wyS1Nfg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nrxmK0sxFw5opGoAsi+RHBRwE0wYNls8LL+oURMgLNuoRDOPNH7up4F86jASnrdlvXLShGHMZnaJ6\ny1orZ0uAZ6xxM2PeKAxvxBI02HOu0aXd/SMNxr16dADlCYK6R1DVdq3DC+T8bQTLWyyHr9r4m4En\nW5DcJ2hEs5b31PUg/DoCNTpHm2swT7sLG9qRkSfTddaSyGTADcvRXYjnHKHin6TQlOCZufWMm54P\nPJeCQmj1MjyycQGpsvFNX7VMxW49ashO7EGmRdy7lMGRoHDqLWBxcIlwAS4L28iuln/NdC/QV538\nQei7EbcqeUmfs07XP8FKxdA3hi3Aq2Upg9DkOw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64736)\n`pragma protect data_block\npJdOORWQloxSGvgvy0l4tBp1HqnYdonsYgNOe99SLH3qi9BP+2tNlaoelqmLJLSHNsBn3TJxXlZa\nnIZxc0/l2jA1h9Jz15QEEgUR0MqZaESeIPQdEbADnul6xUXY0J6g//n8Vnzph99nb1v9j4yp0I8W\nmF2Bvdz/qHJcUcV5zedPk5PkPVS8cmwYFQWer3rOMl6Or1E/YoHi9T9wfbgxxTs6yzqYqVGUBlz5\nAlhSoRF+xXB1Z4h2Ny4v4u05pGtbpnnDj+JhauZ7AfT+uRL3JZ7hNdSiI3coyNU077RtI/1VAmYO\npJoj/3tO2z4y9phvRShE/Otch4qxfx53IywqoRQmUF57yV4NjbkGPW8j7U6iQ8Ls1911ZAOgZIga\nmynl1jCs8ajbsNdraT0wfsPf1kWJOCuUGyItYv2eEwfh7iEYRrpT0V6YT5gENAgDuriQCZuFtnJE\ndhvImjwTXy3d76buWun43bM5pyUNSUzm90uucXHtbfsv8HZTM/chDluZJ4cMeW8D9Pwjtvo6lXLx\nYJM6v2cUpOTIMOcKDxrRTFomRQ1DwRsa4wQGal4q2dhrokLR6YNhu1ED6+AbEAN+FWui25yRPN2c\nRifAbYj3+oa+z6kUON22gegvkiRIe3iVn5MeyImok+P+5dmykiOW6L7J+GDFd4UZtYwJkwUH4ijt\ny9tlvkg7bhgKKY/VRht7EZFg6U4GjUBwLTEWIsD/6R8LgyENKTNO1FVyOJge9+hJYOxJpk93nMac\n0dR2cl0TLESIEfZQ8wSlqKcnzibNa/Mwa+gyj8uNmBtlGMv9GLnh914fnVrJPaJYjkLNLesy5uKF\nWOOHFhlsuqMHkybog57X/W2y+bzzdtaWoQ8/DU/QWGyTt3Vhlmu4YBKvv/DBB51RUj7naprx+CNR\nK7/l3uoheqcD/zy4ipVqZ/mSOTxjqNwJ88tpKUTD7UHuLf8rEeiu80iR1raYJGMHzUS7FcK/APPf\nbBCJIKpjoq1C63MJYurbOeqWcRL3DDPi/z3C66E9WG/nFKs7vMkhbVhClFUAjy+DwMCS7VjbvUvn\nCbr4m+kTXY7ipbBxU7YIDWHssBAAjeM1Rdxx9VvDqABN+rFZAA7C08PNPUeOiVYCFO3gmbAqYK8f\nEPeBaPUk6eskVX2sXw5/qrh1a5mqGk/sYCFZItuYZ6SMz1BFuaZz+ac8Feq8+d7gH2f1DuK4EG20\nOgLh0liUdRk5TCUZsSZTlhRd1FA4SqglWHYk+GIL1WEcVBskAEiY2YIK1TGXzUQaG00TT5TRBNmv\nsPnVI8z6bWwqXomyqcYSelXrfl2izqtjadlA+3+0O2A1XhL9tmMhT3v0nQIlobxn4nFE376czv08\n2+xLHI/chXlg2WvKMK3NCBbWGw7tnHSdJc47JRdiCkb0tIr9wocUbWPbM7W5G3Ku+bQZQXPM0lNy\nstFAjwukEDL4vbC72EJbEwf+6kzkzLjBrc0JDEzvjqnYQYiwloQ0qi9k/yE3bXcnEHvgw8ig5Y/S\nt9SttzL9mNMXwbouRg1seAZ89RrLrTNZiBk2TlhzdIfvWsbvdBYdIhaMqKRGJFpWxZgPm+JbW+09\nfF1z2nf/18EW+WziUuICezISE4+2HDfqFOEltKV6AdesQWDrloYiby+MezSSORPfWkx+nVGv8JEs\nI01podsuoWFRpVmbt/Dua5qZk9EOHGFBRgvYNnlH47YVREn5j8l2T/0bBlGUrv4r0tmSTvb5Rk62\nTtYvXt/3/jJe7TX05O4Uz8CDBe02LhhwyNkyyNYPm6hcqislaGMW5IrlUBR19xoKivY5xsi9WHEp\nOscK7GlXBFf+1ZdqPUIFBzo8CoanS+vY6N5dX/zhH9ka7wSGlru7qjqAyYG3VOzYi+lIUT1D0l0A\nhIuLJhQlgGIPioPMX5r9G+nJX9J1xhmQmslUobJCrtsIfoshA1m3sO8FVq/uKShEPK85uU48DmE1\nBM73G3APR/Pn3q4udJagFjB+ngJWARXqQX1U/fZdrs1d4U8E/KLlkVQywLtM4ImADW15ZRE2zwbt\n93vD21KzRF0gTEp32+Y94DZJmilvEITUz6i6Uf3GIhk/8VlW2sgoZBxyIXdlfZU0hAeWoF6z0y8i\nsz3YJBSL59bOXPeovsUY+1K4JWkThiLh9WlHMd3YfANHBPnf+imIQZm0bk8SniIn386MI5OOzHz4\nE4NRinoFBZ2QveSs8W7mDkgRcm6PoFPVY3QRUGVKM/cdavafi55CMHzsrvtIU+GTn9VIn3xNt55T\nvun82PwGiZ2FiwhlNlG8Wy4O+LFNA76IijNkkamPOoINY3NpvBlYJ4sMSw1dZ/S+Qd509gN+YqK/\njuugLi10dq5ezC717GDkCW4fL6XMF1BLctfTjFHbDnQePKJIiB57aUuvbzah60QCKQnwYsO2mNs3\nlX8Tl9YL68F88dwoxH0JclrQ/K+4uYuofKZNpcUqyesWLZ7Ajkjo1V/LWCNdqLb7jaE2Z0v+PGsJ\nbQ2zY2rbw1xVbkOFkWnJb00IZlS5AfKLW2JwtTjSc9R5cytj7Kj8rVyPRdWixjwHVXwb9oIhCtsZ\nr9zdlcsnNvnrEk8HWDJmg9t+Ss3qdeobuZBvC1qVhW9OeCSeLWFmmlBTM7zlf4bIM7BPobwINrOH\na+x81+t4Xk/8bAWK5b1pfO/q6usi0t9Z1NTJb3ix47MRkhAbStRfFBfBwzDQr/YBXixPzFiRd7RK\nKHM5pI4NGo4x/1eUa3I9iGFb0JwOlvTvmyLF4CY35sdztuKueaGq0YUi4X3SbBVUihPbcPvhcn3q\nULcb1JlytkOdtyHtyrm7/EOiSLmMn3uCPXQDioYj1f6NsIRA8BV+t4V5VK8a2hNJ+Ci6U9tBmG7R\n2AfVDNWXakk0eYIUYcZuIPVd4sH7Be8PANt6YH+bxeZtBfUel13RoATsMc/l+Vz7BvaZ9ZhPoxu0\nMpG5BKJTAuGZ3OqNXDuuvsvuBv8s5hC8JKvLoL76k+rFk8PlyNwEnYoc7nFhCrqDHeOr/8E3maxP\nPv/AiEhEzjU5PQBF457AHnjeQ3eTwpDPSnYJ6nuR0WhnaxbVcRDXmfQc5Pm+RgJOQXySVRlfAtO/\nJmM8oWf9Wd57qYf2P95KvohDPW6vlFW5UOuYJRNedw/Vofmtj6gUXmSUtZzX9x+pGUbZK1L7qaRH\n4Bl+RKLFFF3ULv72pe+uhZoyumhCUE9nTUfh/0bbyfQ0/7E4OjNceJy3IuQXZAelpm4/lyIClM6a\nbcA7XaiUNtUxRgOk+Gm4bXDK/lbpfHAo3ZLrOeIIrJSFdGgfIjMAMcPO2agXDXysM9w0LXX4XzKa\nAk5Ctu+YxqwaE3xbxVfqa3Xiwxzu9RezCh2I21Ysg1ckJugmX+s7525qUeaUizKlxcu5ef5xX40W\nh5pW3QA7UPCugDISw+aX406IO2drov2E5eUNDLRRG/nY7aG606JFGCFgUNVLl22BloATVP6ZeMDr\nmifoHBORyaJvgAndCrygYyJGcy9labne+Cqn0A1qtn323sFNB43FEMX42WIgtgc4oPab1AYsEQum\ns46nWTCUaZAyRO+53Dzben+MOJEy1iKP7o1PMZDKjaQ4Atrpot1Ix9OivbbWL8nNOjFG3rRgc8Tf\nLOVtiwqq/r+IiSB/HQOV/ZHmkDTL9dtw3UFvBE6wRo6XaWDbKDi/T7PaYAC3GGNaQZw3CTXVFb6P\nSvTMYdICAhD7YCZDr6aVLiD1Mgc225aXecHZoluSWOck9HO5ezjlCFCPDSTSj5OnC9v9zUcFbNOa\nri/TT7JdgqdBMKQjvpVrljLeuPPWvSxLMEar6iv8iFwj9w4fIGsSX5D1h0fx53Dosj7c99OjPOKJ\n43ciuUlKmUrl8zGTv1bTsvgQBspvbQjDlKlZcFGKkJ5y+h+FKT7sLG0T7X0OsNyJhlkV8Oh1B7s0\nnzc4JG92kvRVvDmVljLF5q7kSbo4pOg+r9MMh209JANj1imzsRTwNlFhL4KQmOy32YKv975WzfpE\n5gOHTY5gj/9beHVy72SphX1PvZ/GvMrFHu0Q1SdMOxiDJO/8Vv+UogST5Z+pm6YS50RKp917SJLr\npQGNrqMBt2q0TjdKoF10330Oq2OQnGbPQBcF5wAOKor3lUhuKlgi4yfTsE7g0RlphaWiUi0kfQnJ\nxJaR/v3zWkal8YKuqBUOk2zAI58JgLOCGfkeP4lLDigas6lR86dIFm2ehEwWiuUxA0rMWk7MxUFq\nIvlNP2JTSuRX5d7mSS5TdZoich5Z28tzuAxtmfX/HVgsAiDJsXeq2lNJnPI4t7OJcjw+/LTBFn4u\nGkaeVQKsrDg0XjypHHAcx3Htai3F8S3SrSZThLhmNA0UuPAVwrWM/YxdRJdPCFxRV9DIfFLc78ED\nrxRf+2hm2iIX0v9lJubvukxj3RKg3bWedHf9X7fBwzCzmT3xpSVT/orUQHTM7BJi1uX619EAPHfH\nEslFnO9xBhBE/NfxEOIr6puKJWQy0vcdu3KHp/98gdYKgnVg5mCXI4uGSJL+j3Mo34LyWj6jofG1\nRpvUjZOY2WsTY2U7akBl0Uyiv66vuAVFTYtHxbLeKihdYSSxteod2tWquqRvLeBirXL2qi69vijg\n+WXGPNEs1ioW+W6cjl9Kt1V92qIp1LbqTEC9jDdj5VHq36eM3zGGY1FX+VH47w4FoxWcrGaGXkXO\nhGXHGyLwe6ssZ273qYR1N0RhvtgHnAdUHIPdsqqRbjeld0f7uZDVEUjGCA5HvEPmaA4qaz1HEmEX\nMSbcEbGOwM4/lsTSso35cqWlqf9VepPPahniUNw1bY7j79iM/o0F8kJkfL5NumCR5VM7RsWuHT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C99kqfj/UVOTB5eheZdHy7EcqBeNR/+6GsibmPncbobTk24qcaqVJt3wgZyWp0s45X+9wMv8\naq7nxbvk+JD5cuPi785YB4Is1gg85t6bvpA9Qfzb3O9Wk32ecemuYY7hfv+wXPcCciMC61K8t1VJ\nDxofEz9Nxh0L6M2gdZhrIeECMYqp9YunMryNLeqc7YQLvKIjonC1l4sbrYWZ+Vr/tRAksYUVxldM\nWs7rdbIReyHwkW9Q3eVk5tGNZYwsTJZ3LLHqX4k4QW4fN5SrXF7tpu0Nh6B20X5kbA57dL9bI0Mg\ngdCKLlB0s2kqOmSFFGQ2qiGM4gLCtJKTcJvH0QXyq3PoTYgnvqWXAi7962ulHUUvjiqAbTLGRYQR\ngd6pRfridQ9QkVVZ3q8/Wwg9RSEsbZuIJ9bsY3KxRk+Bv/QJmfbw9otM2ufRS79SLoJDUzayREpA\nzPDRjhDoGxRqrI6rV3uPDIkmG/IgiRjrOM3CMltuf+l5zCRv72lm/BooJKYufHaSMAUyCUXJp/Uc\nFu0s9YVH+QVUDZtdn/t+XoUZ1zviEEgoAEoY2VYry4fCJ8DYaSDlP46tShiJjQrOJdERGgL/xQBx\nO6uzJrNrt7Cf6kh0YFyp6QRAfTkuf7kwETESQMUFV2MR8wr0hZHmd/UBOQiPTPb8DscsuSAYh8Zc\nrknuK0zKex9YiHkZeDo7D/PSeuh+WG2d2zJdkM3Td3eMS6WVDFMFl2b5W8/jYjNABrnjK1XwThFh\nYLnSLJi/Op7SthgN17FwYwSwj+AcsR63hVzcnfiVu3ZUXHEZJEyz2HWtWt0RLaZ7MNZccAta93yH\ngOMoJdpfeYUKCCFDGcTyJlFegiSY/R9BWXq/NR5ouF0kpaoEUa+kWjoHoOiSEaQs4XEhSuNjRynD\nrVhVZzcmzBTJAU/E9/o/Hq/uvAStcm39QbP3OeAuNYGNe3sCFCFik9NxiyTW3OEmJSjBcrOnO+Qw\nx7FcS9UJ/wQfURM4P12Z7osL0N6s5Am8NipjMtQyeAtwOcmnJoNC+0+NUiyPWlCuXP/3Z4arSgFa\nZR7xsOv//tsF4wlUna5iH3TC56YNk8nUsFEw6Ge6ZSuhEVsfIeY4wG2IxxjFm7GLEm+Qi2fnWvFp\nirwOxF+K+U92WcMWV9jGmnuJKdDgr9f0rTsSnyJoE6abD5qCwAUSiMOFTLyqf0omOu5SrdwPvxDF\ndftrQ5R+oqkHgkZje/QojcIA5MmPjkCLRdKv8Qe8et8c4lmY6vRi/j86jriaKSwx4Y+Mw85SnPR2\n2j1hg4L1bm3Y95mODLr49QGkDVB7kvY4Qy33Bsp2CTuOWo05KgZSEEXL/7U+fWGzRHjASwfcbgCg\niVFHnASo+4H+F8SItbh9vW9aZB7dvzb/sp41V3sOiSQ/lvFv36hNky3d5TPRgeWxk7ahEnAeBvcU\nN36JNzslIJ0QcFbUJcrGjbreKWGwtRudHbvZZiy3VBuJefbL+K/nA5GKYex5vaF8VvW2JtNaz6nG\nO2mf0K1OaIC26ble9NY9pYrqytCcdTpOisFBK/sWMwJTDavyPDcaK3b2r0z6l8yWe/+kZORkwM1n\n+vS+mBxXx0tf6GtBwKVn9Wq5PBEpboQb7z+jnDgqEVQGEQk44+zDxF6mTiYHaVCLhGP1x2L8Qxtw\nPkf1ixuZGNM5w3J6JjwoYA1WqjGzNXQ/2I4IFQ7+zOL2BVVm8a+5aGNvBOtcu4B12kHIJpqjtEJq\n3tU1eussVADMAsGVV8uDeYtJPvulbF/idSwsgG8crk6BAOKJo99VQxAzmHr6hzse35prsun1dsY+\ntbANM8RyL4weuRCRdH+gaMfEFjRTXyRtKzs19VCSRxpLGUewvAFPajZ9ighUQ2DOA7Kr/rcMTxxd\nrh6hpvfsAFBAQjLiKMsH8ZMXPqNGDBjA8s7TGxd1KmM66Kj1RfzFBtlBuz9LglC/dRn/arEJkYKW\ngOxCUP9SwP1tqpMfyCFKkHci/RYZqmjbNlLH12cl5zMhmsQpiIcZXYfQL8enrVutyHkc8Oplycxn\njTecEx2W4yyRww+b9SpNrQwNcQAZHfUmu5afg1rtbUHZmBW//Afpurxew4MlsTVbE/q+GW4sYS08\n5hT4/ITaA2T979WNydM1h2SItDPecKYro2NCBuNGPCj2smuGGwIqTTedt7kY0lTXqc1QprlIXDOv\n7A/WEW6Ks/DyDbzo5ebBQ9k/Or/ERzVfh5qWgkq8yG0qonueIlbVexyJM/7sKO/BjOR3x/FKDD5A\nPOch29mk1tOqyzjUVo2fdU4B2P5yIWUu4LyA1+iW0TzGEcAlb+9A3LJHWtdxf5XRYSDst39xRNq/\njlN38Ihbn61REmPKmA+LoB8LUMaREXZsyBT2mkJjbCqOmNANgzEAOIj9ceuS25Y2KtrSdejGBdIE\nvCBEfvsJHNzt4EujHKaeJh7o4NDjqLcdEp7ed4Ep3cSOHMCOA874EICbE2zaW5mDE8TG62+kJMaF\nV28mlwI5fMFxipXSTKgVDY4Vj5EWSGuC9St7IfruwsQ039cqwvbAOIuBDwEDSJc6lCmXs/qZhmZt\nnFv7j6yW+vhyh9F/M49mYXMIrZDI2IQn1meVK5DQbu4ISFnSDGJl+UGx+F0w292X7x/NZlrDFxjU\n8F8hH3SoFUjtp3cdqR6J0qgyyvNuJIK0pC2nq9IzjvH1k+PjKgFH3e23kG7suulbVb/rfU+4p0A0\nUw/8qfFdt9ZBcVINnpEPSUJScU20uwWwAzXtPblYceO4Nbetd/Rru6gMmzl4QBV6dHDFv9Llj35m\nrcJlg8L6gZdUkbc5dWUef9LywyJ3ifFwzOukFPVGj0p1G9hRSiNUqdgpYFlexuLPL30vERjJltwu\nf4LrTIZ2VSuuoDz3yvK7YYnre2MTp1IvJIRPF0FnWr5WUuDhARBzNlManehpegpS4ik+5bBOARnk\n2ikf25Ea+euX4IRwUJwiPzAGTUbPzL3cODFaJ4mHcPv972AeFd1T3djc/nkOpMRfzLbUHz1h++GZ\nfguK3eWFxgEnwvmTBOSV/2pqlydJB+j2kzDoBOhHJ7yMYPINzLTm+GvY8+PE6TGpMumpLB79DVsR\nwtH293Qaqs60uwABd29zk+xMrOUEivDU8FIBU3QFpa33/+/A4nI1MVfVSHknip/yEcpuNY2qPJsT\nYuN68cBSWDFeSQJE5yXwjpRVFkSAHd8nML/bKhBZiplgzijzI6AXJOmkqclzuE3gbvl06XzNvh5g\niwbchkuC2q85hHpT3w63G6WwlR9OlnKpzSBsWJI5MiFvl09L3irrYtbw529xtermE/blvOxQYxuJ\nA3+cCbwrhbuASE/lxx/+CQSXsAGEFsG+rJZf02gTem+flBUQWxgYw7USLAXlR/yGYO6KKUiU5mYp\nMcLp5SF0ptsnO4GjOAmsRzhq+nFaThfDeXAXowTEeuWN+d56AInospMZc/eW0bFPTbgOjid6z1Vd\n+9+s7tiYNg6b6j0iAwEiBa8LX50Gz1E8B8Xk0bA4iCfVG+pXzxngp/ZgDAxA6x4B4xS8JSzvBqG9\n3fF/tpaS1x0ZYZNKrC0vl9eX2oeN5I3CbgEuLOUU1xIlzEYHqt8Ta5ZEnYRUtbhiunpXdVyqirCN\n2dgXkldd9U31gMhMY7qFkzBGBtdUApeaRyAGLxKnyg+nwnmirKX9Y3rBKSd6L+R5qhO6n0UbbSzD\n+4en4Cmiy/ti0HItxFAe4vWNWKSwEzlKaZ2HLEPHIUlwN4xiAAyIeXLQP3SyqcvdMzkhMFVdQYhH\nM2F1yAOo3G/JqR2EjrPkiLCy80ya2Cey9fh2IrTFABUwl8LswS7gb3noQTWyDJTWhVsMOvXawU6k\n9W4Jitv0d/+g4QNb1K05p1NtcnLpsIbcTsGei35vIairYz2Wpukkc+QIjcnbRoRYwr386Jd+y7da\n3/zxTz0ylTc2RMTh2TEZRm4kwoCvMb5bRjiCs5p4VDLdB5NKcfMPq/J+LOvbN9BdKd2e8etvM1x9\nZ83qLpzhi7vatfxsU6M1tYzeP0N1fDEQPFerPkzA/sJJfcYa5H+94+uMTRANw63xIlLDhmnCm9fB\nvFsT1znWi0KNE5YxMVAP5Nj3aNk30viM/aEGcXN1+348mdh8cJXP6Se0n9M2ShPtIh6uOzHcNN4F\nXvgZxyI06BOFPCh6pPn8pM/4wkj6M+5Q3d37NGdAT8T8ei4zfuLUhoasw2cJjrdrZ3LNelT1XVzr\ngtfkU+onSthCPR4WS6Xrw7Ok/kkEQoYmkdI7UB9unluvVVQ764ldp5OlFSL6uGJlq53fikq1mMPd\nHtYt08ogxQnb+cC85LdLrpUdkov30YC0DE++eB3VOpsBoGUdgSzOw4L/wn+VuAsCWq5ABwRe4fqT\no7SyMEpq1RX0wDx7yvM1IrLxDdnN/w9pE9XQ1ww/ANlsQf3806Yc1bxBlnH0iwF7F5dr6ExWX02C\nm4GMD+POG+syw7glXgXQ0OUc8vp22qMR4sD57/Oul0voKncx2id8UccXB9vsMZIBhX8NK9iQyJK7\nYG53Y6spKPwBaJ+D6oCzIRdMrl47suvOHOFMlq9EgcKZSM8cW1EeM34Q9wneG+hmi1jxmgRg05WA\nNvs9ns0cBAUoExbeKaTDf+UdQg8kQpTj787x73pVcySGZAe6vE/iMHRuSiZo8GQ7v7UaVF9ntzDG\nTtrPWvFHyuV/SDdzax+LPSONzmqYuZtNNGc7rSFNjipVg81YgVclfSx1PGAIfydo7Z24e3Gz6NIU\nMwj2TtlQKBbeM3mx05abZdGgKr2KZg/G7mtpHcWqPBAwGoOynrpV4ZdlOI7jP3SkujjjiUQJ8FdQ\n9dU1KADRL9hr5MOS92p0+2CDZXdgK1l4EzeYC6fuN9IyAXHsqWhfswpOubjlkJfdxHP/GX3hjyHO\nUvlaWBcZDw7BAWM+AX28BwSssw+yc8sPIxzjHKVjNVz51Vpi6eQgVAZfgVeW/CVd4po9zDauDBPe\nLW3Ffrt6P9FU45qwQ7MWE7oZ3zsTc0evg2krhbb9dLqiCoz6VuCkphBd+BhX2nSPTl+BrGC3EtT8\naS6sDKIiJlBJL+8+GJ5RSEQoTGfqIs6ND98n26dELJI8S0uXSltTPxBhra5yloAd2F4/mmmPjyWr\nTQxaz9QC3JZaY5ciYNddoc6aIflLXGP2kZlT/V1zu+CW+BExE9WpMnVToGI8RRt4jv0a874Y0An6\nHhiPkeDYN6VUowNBrQ5rQnTkFaMpJk4oWUQE3v6avp7Y5alYEE4wCED+ItD2AgaKwC/nFgLMfAnZ\nktUhijy2X1yEewInb5S1xc28GWJeUEjeegaSJijHmFVUCwrnggKTZlbyJ2a2ezSse3QS7DNzMLsw\ns3lvV7VDvQazHXN8RAgvOB0B/CgfYjwZQnyysjBMCOEXr9ltmJw3ogG/vxGHBu667EeL5qOCFKZS\nK2yY/1setEN3lBeyWFiOt84crc97yyhIN9WLadvrh/f0YfzTa8/jZpqi6C6YM8s4vbQgQayL34x2\n47QkQV/JCgk47e027m4LJl2YsaOwIdm0CLnMgOgEGQPFdyZktwDaQcho9eG3wdeeDVrkyzQormhu\n9aXm2HxMwA7LFBoLoLMTe/h9G0EmWJjSZJbpYBym7mGdw7mGASxg/8DfPNQ061R+2X3xcnmG+cIO\nvl0+UTTis+WrgnTXMMvcqbanhkRzuTaNKehiSLRg6bGYM0soIp56mfxn+lCOLxRvrFVCb4SESUTQ\nh41pLzHt1noaHrzs6Gg5F6h/f/xdaHC5qixpm+GAiRp0dMj0xX0roGySULb0Pg5Ik9k6Txub6XiO\nZgO5zmj4Zg5w8I0AnXTXRWRQrHzuRzUxeqeeMsb/JspTSY5oZj06H3vlmxUcBhypLvXrMLcXh/Ls\nc3bNxQvpWzLBqqdhy2tGJ8fAWkun0YPhNwlUU8lBB4Gk06kgUQm222XRVdAheeWAjR8NbiAop06S\n8Wy+XiAj+daeCKkiouMukARqbllP0jcynVe076LG+ZgkcNqoPU37HDyH9n2pGf6ZkAQuwFeIbkSF\nPg4iQ36vkP+KaDnRItQq5Ii+DKzEOXGkFXjeyB2kGs1noDV9eD6DHXsQa0azeB+0c9fKSA7nV4Mx\n1BtiwRMnJT7JPQOciedKCuaoP0Aq+hvnG6MBlo+nAOOlQfvZ8qQxlg0laf4f6XLVWOpAeGt6y0pr\nAw0YlMDiAyvjsrh3t8P4eyWaZSoFPRIJLol9+5QCyrLlm2aVeoMUtwJ1/53pTKnTEHcZIZfi1n7e\npjP+HdzVIccamu4mef1McNibQT4nUfu60LdH+ZQICzwZKDu6slLfWc1KaTXs71UCJzmFmBNREiS2\nXy7c04shnL9MVkGQUM4rVvlqeU7hjpj2FNlt0nq2A7NHDHkEArM25UeIzO+An0jC3tn+qfMDBZmx\npl24RVKkzC2NhWcwhhc3TGrk1gzXt5aE3zkSTGv9pEL/s8V0XrlWQBLq2XFeBXgLpSAzseg2st1r\n71IH25LcYi65u03YZ8TaQSNK5ZQxrVBVO+JVdqF5H+UcYmJxyBsmvTOso+y/z+nGXXnu6Wxeb2K3\nPMCSNT7G7TIbSFmkl2cSMzEeMwmt7AyMdckkJzv6cvcC0j0fLIcJ+ygBucF6mrNY7OMFKMatX0PI\n4UdpryZPtTB7sdMGLH8FqHkw0PoHM+53+V3rRDIo+ImSU7g97SHk4uMmW9/lU3+h4QEVhf1SsCoH\nD9SCjVbJmWSx+5ck3SWahLdUTGE0c66fdQ50VOj3xxA9nvsgL6x8+drW1LZr6SHG4Ma07PvqbId/\ncOHrnVi5FevEja28niNJV/635eMPcCA8uWcnSyTm1J3Fe+CyROmWWUPs1QOJLqlM/Ai2tsSCIaui\nrBVtakmXqv0aMhA33NdtZu3vrog0aJfleoLXQUuDYIGcGc8kfavMyQBG72eZnrVz6/tupr3lLY4Q\nxVGFP4Jxgxq1oFD+d8nf2DrnUh9AyNvtyyOCKi7z+ReLuwDg4jFzd3U9eZQ7WTDxuOYKmerT5+UO\nG4qs6dNLomx30eVvW25a2Z2qtWBywQq/MaVipSr2RmdVavfkdvSb4lRU8c/OXc2j2EjLF9uwD9ij\nR+SremaAbHZZKoNbBX79rPCGwHPTuu2e/3veCG7t4yv5s3WUvVkFPocYD2rO92YBt3DE5NjJ8kgM\nBCj48v+cPe2x069u+Nco6d7scSnHpPHHPSM+6Py5/LgYVagzcTfjK8PlJARVcAMsLJiBvfzpO+zb\na4Rs26CnEdvlCgaKBV1YLeJ2dXWhGAXTQg7SIPEe+qxZanakqfbbb2xT8QLylB2wpP6fAVc2MhM7\n8GAoec89XNo9PAPakTkcl0WxeigJFRkS527gXqWbZigV+8fVkzfLL8ARih7A5Y8faOuGrHTI1D3/\nzLMHy7/g+ESSQUAfGIeRgrKCYK7EMouPFRuxC5uxAYpm5W/pKsdIPrBHWTqvC0PZClvqzFXBi97p\n9keo4Q8i5+/jCqoMSKdh43uf/t7GW8Dcg5wWxhGnjWC7PMUgwEzMeruqNa0zB76K0zeUaOmh69WT\nQE+NgpCq0rrPFoR4W/hxQ5lqPWMYVQs08oixXrdi4qxOlpMbrxoLJ9dbreMCg21g+h8idnl0Tl1L\ntZ5uVIyA0sfNcXr37h71rInz9wjZ2D+cn1MJf9A+S9uhwm3BGTz/4NlrrXLFirxI7VfKkYEQ5kS9\nUmJtizU6dQ6Ehg6JDdHxuh5l52FvU7VuMVMozDJdJMvbkeQHAh3I0RSRxjaUk9t20AqO38NUWado\ngkUnSoEZCLnKpWk0YPx/LgMwFeFUGPMwCcZ+o4LM/G/XVGe5eO/pecve0eHmEnfeVBoIeGUVNgM+\np5FXp1hflAYwWYzb3FqUrZM6TMi1jBAtwoA8RkCsrYN61H3rOO2e29xzDffAshtKB1dXBUfI0Zxp\nVN8o0s2S0sIOL0Z6Y2+38Wn6hSTm9pUH+2vQjPt5mmWo7cg22+s7MbGkZISOJNCM1mCrD3s08ZAJ\nwSe0IXxQ9GoXKl71fWfyxDOEN80E97kYHfLwT/anINNK4DYOqinZPKwL6lPcmfztT/jkkYeC47vc\n2LKundEqdpIO8cT/NlrAVtDH6t3Fm9VABN/HIsAxIiNvOpHUSrLSF1keYvjZzNPJ5FRQgPns+eTv\nGP8JvC15MCNYsPYO03i0V8tim0p2g1ZGaidN0DRZ+8QURKlhGPX747Npc+Sns6GK2hOpqQs5xmC/\nkg05svfxeKyBc+mnkDT3BuW6tl06gkPpjvfgTxknS3UtGnjHnLRzXmIjQMl2IQ0m0gzzccVzi/72\niZtemsxeuumi+UP3MrCWaN+wN9xfBDV49pifJbqDeSGoznX/Zcb2XT9kvtBFWMmlBG27ZlbXviyw\nPnR21Qdpe9Ga3f0oQjJGGlKrEtk8kpZXg8bTyYQAlP0cxQpKZU2EjD5JPPrHfj1jG8shz+Fu/9Ho\nMoczpTM2n3rQNUp7R8v0cHO6ikm9/A1cUv3WjysTiu7SuCs4gBkotSNY2Xk68SXZWzYgFxmK8HXy\ntx9sdKEH13yEbULEXA+4COwl/PywoPj/Nl+Ew4Pwcm3TnoqS0GSPt7HJPOo2hoOxxqB08tPM+X0t\nB9E3nmeN6WGtdPk5mkipZRl6B32i/Zgg+ya/eRdCQdf9fg9Wyl1aioGzWlZgA8sH0At8Y7gl7NYv\nGsBJKYY9eIu3oVdG89uBhlUj0AOPcTOGIyt2OwESMxURJPXjak9Yh0eSBLOasPf3rxt91kWGROIx\njBiT8eMt0OnS2yu5HO2Eg40cmIqsC2vwtJoj9wOdu3zeceXfhMsdMoEsk85U9XUNedzDXBDY+d/K\ni529zO4iKsBwTRgnL3+Qq6lgmFdlFvr4PT7x/PusFTxAe30moNx7vtlthoDXjY69raOtJEVg3oac\nlEa+QrsLiy6szONetja8Xwm35OWq22kBLLd/fhaSvhSgxFNpHlINTa+dJ4OHbZshSM479f3oy6Gw\n36CHvvAUHpTmQiWWOqNmmUHHHnMRxvyySNkV7J8hlPk547mUpXPDCAheNrbQCq7Zg9QcaiQWd9qJ\ngnrFkLP+BjGxkvJwrV+1jUS4ymZ8io4U0EOc64Tuk3B2OXy4e8bHbNs90VoNbogNJ2JBBrluJx1L\nQ4+/oI2p1bd9BrWyi9lb2v+KL4o85RzAFnSU5vGSjrIx3lm/ZH/QN8/90o4qJsXwnwzwywuIEieB\nDYWlvqUtcnk46xKGSj9rr/PSTZBd7gFkW0W3nLbd5MKKjVDxtdiKjSV30e6iwgDQZ5rKvLaEPVul\npiJd8wgHGnnZRT6oMODzea5SMDG1Mx/Uu8SQZWcFTOb11D7MmcZD74Dh6kGsUS+qfY/P6LK5ZyoN\nHNMkZtEiQINbI3DG2LexnjcnXgKqZm2ZXGavRz/1f3A+4d4Rw6KoWfXIZOVUdNn/l4FxU3xw44SI\noKl1tT8NUagrB/gafvUWFBenLnxPxW0TaqMp+/lnAdDvwHLTwf2p56K21HxTlxXAb2QmgQlZB6bU\nDuYRjWtw96PcNIcEhaffTdNRFC37g/+Rw8qIWX4+euwL7s7q0kxKR4/TG/OfLrnBR/5+jgJGxj+u\ndtyDwjwrtChjTru6KPXODLvAm97PhZ8NRtb2Yzn5a9LjbWYSBpxjf4eyfAdYjEw9yPbjJpi9AJAW\nmwhWv/9b5rkxkeCEr4yQ7tXZTLx9l9hQktow08Zlh6pE4/8M86ah/0BFrTA8TwV1MQM9W2oncjGH\n+9q2b04TNO3wbncrECEi4DtBvtfYup7Ewyn3GlaO5eYLTg2/jiNmLP8fy893XZvRFmwsQRwnyXCo\n2nYZv3H6iAokmm54kiA8wDeKeZH5bMVRb8coUhzn+OdVrFqyf8myg0lyTJzy+bzzY4Pah1/xh3/L\nbI1bdfdg2OoVS3n1aXMOJQSoBQzk8F4lkSgV14x0kEgcg+6I2cD6IG6bQHCLflY17NMmKnX7MQeQ\n9ARoZL9Ftb6h6jt+Yj9TqigvDbbli6iYyt/3iLvMaE7nKbkI+BcyGR8FeD5rz5Sukk8W6WTDkgsD\nYzu0DTmAkRvyAwCKiwy6bzCh4dzKWJOK4GMV+psXZepr0io43Re5pRIkbdTsNzCzimW21WR9ePZ8\noWGZGUVoCCHkoM+VhFyZgrFBCuEGtlTrL1OhJnn8G/vmj6GzP7ppzjqtQOJdd1NT3mIJtM2MU2jK\nSJ1bL9b1YgSVmGnENvIHBs2oDoiFeYB/AdsDKbam8Ofe08wTbM09FVlDEjl4Kvym/+mlqBqdjB8W\nBTlVuLz1Npwe2Rqin9pAfmf2mro+7Q+P1t2MkMMBq7+mNXk6t7f1EZ9CP//mfVK5vfUlm1bJwc7h\n7zjymmmA2J7MYyTiTZCFm7zKpr2m0yARdirGbh5+XEerjM0JG1JFcunC/BfW4EJW+aPNSQhpCcmS\ntpvSqc1TiSkWDACL+Kld4mtOaUOVAjJ4IPoOKrJtnDz5EYLStpqmXsohKLCt+sy9YZ7t7NEdk0SI\n+i8nrAQsijEAoguMLC2r4fcfepagdfAzf18AS3Z8t8vItfUFlgvlByAWPD0pAxEeL6gRPo34mHvp\nqtb02SaAbEWUaCCZNhoIT+MAPCCwxxu6OEN9VW7YQw/hmrD4e4GyB19xhrNtuyh4zHoN+FX72opr\nxOkXzzghtXGGsQ2q3/6cNaNiE7P1xigeetIkjYaEOogeiEI0BuF1fbJDaLfReX9e6jXiLvhJ5AQe\ngiPAl3g0FjDUcmDqjRteAhE/PNHfoJUSgu55pPfO0NY2t2Z2Ye8DF9v/uGaVuFA1bhi9O6ZJfE0V\ndCrNoO9JVtPWadZbKqRoRYR64EhOYf8QMWXpQea8J6pNasP5XG62E3mNJmZhsEhO8da14ofQAFnr\nuw1npXWWvVGW2OGong7N2Kwh7SRpeKL+2tVeUM5oyRkkegprU8oY6yDTmkgW4gzR3iUD9r2yEQQR\nEUrnBqjowX6/a2UbkSvengDsfeYrIn57XZhpweU0dH5uBYP5FkquBKbngRzDWRIhRjpZOeNBuquj\nX6fJiQEmJedr3pyKIPHyXEepzbIAgL5Wuhzk/LNljrsUkTz1/vK9wk75QbxTXjCCi0MlhBUnf0Rn\nT9gWptFSKOOspcWHZzz1bR3qAF6yX2iGIpC7CBqaPPjOSnOIr1Qhts3FByUz2W7IrG7VFIApG2Qr\nZEpY3450S8oEjLqImCdG2XYabHF3KyViSlBMveVAn1qZGku+UFjoqKXKLREhng3hLqooi6ugvH3F\nhLD0lteBKSVsoGT5MDZ10f0FHDYuDu8pt7Yx+avdWuF0XQUqscn1y0GeYS5kr86t+F4ToSMW3ovR\nH9BqBMW/e94nritukUh+pUU2ENfgPglvuqcA55FabulEONPo2iV/4CdTcW3iZD/sNsGF1UHqf12a\nGB0N+vCYNuUpx9LspYpJWTeHOQslPRs7vWN8S54MBEJuS2EKLe8/vgESL+G2BnW7yrnXdPGpYRi7\nantqD/KGvHSTv4C2mNcnINFPsx4e4JPlmwJwsIHL8ez4LDfzGkbQo3znuwcl1FgqMpr/rZfAbjGd\nJnMlIYAo47jNmAfLXWB+SdpPEJgdYuuRi2GQKLWkI8JUR+/CMdKDssgcEyaJyvWOzURvv1hQUUs8\nPkMdKt81i7zFYQjiItlszd2C8zczwlH0eWE2I/wYLwBYMkRn868QftUBc7WCXFXvjBndT65IzaLk\ntS+XJHy1Fk4Cnnkwhr5UiOJVKXMm45H5EKxjwXZ8si08tIgWT/TPY7OcTvYc4EdO5sqbIrOIlxcJ\nA9IOjMcJqGbEoWMAtk2ASak4RNiXlg1zb+mt4fLZDqvemjQOEytIdpDjsKXex4b1kwug4wZmGlki\n8NSMfJNHvGf+G1NZ/qm5S3ZV2kDMvsq1CbBFSw/PxZ+mi7bChotalY0y4uMUAOBSP9kunqJAUrMn\nS2uohKVUiU917LWN5sndUR/DPUfV8pwKaCkdxF5wwUhxZriym4suG9nSYCjgTo7RtHPM8zJ6jadr\nTOy4MQeh/41kZsJ/XYpc5ElRTokVajxpABDhLz+d8fs3DQLWhTQ7dAQFzaxKEHPQYD5+qYLkSURA\n9WeBKvZqJTRRibHc4nbOfxRMxaQc+EAAjELMdOKS89L0XejFvCUujsz2fzQBJkpDyfKoXWLRko92\npzHpWTlhRDA9s5b8PX/AR77wA5ArUGNjqLmVzA1pp9zbxZdgpjqCLi9BNmyv/dg2HOuQs4tgw0Wa\nhIkwx7jfZ3N+FEnXqMihEhWujWBIpFVWJJg9UJ8Cj597k6j613fhjn+fQC3KCwnC2yGWi5ohm/8M\nSpdCBPF0n3F7iEKeRYOe9LRZGXKsa7cPF1dK3NOLqS9L8s/I5RGmzzYpuJX9J3AdnFkFX+eNJqg0\nKMrTPSxtaHUEe+by0YZm0zlcR9t+oiatQXde6yVVzmFWgcmsoz/fDx/AOOCTGxthX7cLvkDnRut2\nzdGY+x0SPOUVq9Up20+HVCHHJVdvlDHnRcwiopLP9EVVJJ3+8+zXcRwdR/W0qU3e3tjHMQeLcQKh\nJEXrK+Byiw8OmW0QMfzy1sWD0q0/sbMxlvt4eq0rHv2LvmpDayo5mQXKasNBMKdsSCFzmjkeVXkL\nx6lrIBNQrnRK3F9WHeo1St/Vlx7gKX61STdUZx3s6I2o9Fu5kQ/n87oY5kGnfIYy/Sqe7poccG8s\nnwtvT0W1l8YAgjLp+y4ttwVZN1u2Tib7vNpCGWTeUR4N4HZlfTWLkfxHA9E6qHgLyLhFdQxD5MjF\nzFCW5kFcsPysIWupF6wd+bHTvxMd9+e6km+LqJvwX9TJm0/Tuhv5smOEetrL85LZL4hoOD3gkOD9\nux8mkIV156Zn5qAXgRhGCBzTAoc3gdEEAZuM9CMnvGFt7nYQqUWozJbVNIu84YUuW9UaohW0MdBq\n9OmTNAp1jaYXjqH+ZcW4yCPJEkJKLw97SJqnlj0ts5ypvSx0AsRbwVqIUkBHIRTEuqdwXy7ffZPz\nSuwzY87QGmpoKvLB/NF/8a/XOC/8ekWrTlyNU7kOVZdUUan4xgg+rmtb5dxRQOg2+Cg5yB2KYpFZ\nGLIJEaN5ePx6OuNsKyGAnoL8VB4CVbYL2YhLksaWv9aVH0MSEQBH+d+Hhh/hyb08on14QDQ3IPn5\nPOfH37BX1Kt4ZT9FhH9AqYK9+IYyvlY1QZqMYqku6WF19aB5M1k1mnxoD9qP2OCDsvW0PulTcPwe\nbZWzXBB+yCTURvqwPmCCGg7Botgo7UemIA/YDo6uZQhRsrlLBqrNEpQRRJvwcCZadPmql+bxVLoB\nHRd0slNjme8ocHNUYblDKhFKIO4zGW4vkVS2xu86jFCJP+AUtWtEoBbRuFb6se1EPWSEZccg/tdG\n3S+yZwJXmSQIKiocBNNsoQl0ZuYObaHJFh/ghdUlIm9QpTkoUQwAdD6P2fVXHsUxXitYILj9Eao4\nnl7koAUxv+egJe38T+XzWu3qJvZlze2xvOmAAXEjVQQfE0DmYJfZVFKcDVdg5jYqF8G8FxSmQcxC\ntIn4gkrqg6EV87gisbn7qspi0sacZ6Q/1gQAURtDxooDDK5gsV0NEhI7EyoinLXjZJ9SY84+Bzcw\n+VD19FvREqBGtziYVyJ2+YAO9kUgWbuDuEy3aFnNOeTv9ze33bOAoAhBDtbJ4BJZt+eGcbWYWlP0\npMcWI4mKtcX18daNTCZR+LgCAw6J/bR3KiArm9ML52M7oEzMMSX7skvxyTaIj1zojGgXeZXvki/H\ntGHQauTSObrzhFf+YE5t50078XpPzdQQVhn63OgOKp+6Rie0Q2OZJJP1G9PXiAViKajwJ0U6IoUK\nVG0LJhSYwAOF+ditODWEnyYQJx6u4HFg1/OYPbRRf5SL0HEyB2SOhxzRc+QylENCwbGWxkJ/MjpF\nucxP9yehbXSUmmAXr6u8e0PlT+0MEcL5+hML6XanaR4sMnepTVUB5OQKCOhz5bVdYkfJf/AZhI5u\n1tj4AjxaqRwn5RhHqqcjspa9oAXyD6fTTd6VkJtf79obE2Vn0/CkZx5Gc/vEV6Y/UUsQa0+HNWxC\n0KxJ/LqbD+0Xo9hk30nIOWumBfNHVFNABhSH0FO6hXe1h7DRvhESnhSo7kGWpv0N7/A4SIRMybQt\nC3MeWIdBm09lya/sOlRRHwnjh6BgZeBEtPqYX++mSFDadrZ5912qAYsGsdIFlk7+p6xospuH+IyQ\n1PP4r9wg6I1iF+wSIukIJgfswFgAGBtqgDHhfMaea99tCTbBODCxTlvVOkbfZwEcdfqDQJioj+nY\nkY//DSMVhLeq/3yvLCdiembO06ynPh1byTgwmALsU/RT7uf5DrZBontbQhHqEaFGqtf8irH9r7Cg\nJC23F1/SWnAd16dLnUjiqbXwbIoLMHbD3pnqvbyyqy7FNroWPX4qTHJMm5LbSMWNMGR/l4ucWMxV\nky/QnNMEU4wvxoK1RI+mCtU7cdIjq7I9Jx8vXkCdnLnAXFb9QNHosk8LwZfmibS/xe8bBW7lTtzc\ndbpZwB90QL9ATHHTbwX997qQwU6f8Q6ZjTVx8VzS23VGBt3KmFvGycKB6dmPyzvkFWiQW+Cs8bpN\nvwr1sTQF8HierHVZSIDcGGnQ2RcE9sHY9ywA2gug29YJOrasaChUvfzGHMkvgAeWBLoNN45Ptoq1\nHNYIOiNBDDt8b2NxtHOlftvoV+KQTNTItY8HuSuvucGLRFZ/ijxZMp7Gka8hw0omBjJ3K/Canqk0\np/nI+kfZ/ww8PnWSkJCV3iTei8yb9akSyGPtimN3DRXg+nm9F1vhe6ZjwvfxYdXsR9RM2YFddDJj\nPJ/7sbG2ySqr5AI3utiP/mJsP9zsIUtciEXpzIiY17AGEzEf9WZc01mBXJheccBxjLpk2hOmp7DW\n/bolFGQo1u0HwOCjvUQEN/VnOXBf9dUC8dHNpljvbvcpY97VkVLl1hhLXJ1B6CZ5pcmV49ukA2yP\nHUvkv0kKuJDG2kjj4LUJ5YXaAGBdch2MCw/ET+X9R1Lbz7Tm0oYfP/vj2oQjxfHEux6lD/Urc2oI\n1tAqwKd6r/F2M/RmthYfXTEpVDUbiw91v8Sh4I0wwtXOQr1qrn4qwtP90lOT+tlF2M8TKR+rerOz\n/5Xgv0CCYjY7xCg4tuF//w6fpvgs0Xp8n+/+RRHW9SZuYLcjNkECku4X/bNTWgMoAfJIJLIPFZEg\nKFFHSa7PwlQqsQtO7f3M30QtV+S6oPKAnAqXuAd8gNhhlzMJ4O71NOrGSrsYdqyKFMu1pulAegSk\nQZ+uiKAj5kh/P0Ce6xKJQVPByIdBLuUdKWrNSvLdkjayB5YrzBXr2uR8Z3qtXmVTRrfhblbKcmVx\nbSlQCkpVPIWCxkOIc1vH7QfvkHgkz0Vh1O4Br6JIiEDbSD3WhYk8pT3YrbNfBhL9XWekVTilmC+E\ncoRGgWwOOnLGcaI7bxVfNZzqrCajMQSnYQUipkO9bAkBHiMkdegZfmnOCpQgUhIRZAmdKCA5IYZs\nhcQolXWCTRNRgfH7AkKeeObiP8KDY1vJ1LZx2YPiRrfGHoQeAVKnpo5Q+XF4nsb5FDWlbSF9WK4x\n3r2tGTKoamdzjbn2uks7TO7uFcTC1hsh2iFiECPnECYbt25QcuA6GhkCaQDMVCRlC72dzdy8cM0X\nNLgdEMCfAuh/pfO5Soab4eZFkdYi0lUKw2JYfFUm0MsvAYUhYEY0Hv6jh5aRNCEz+5cuDw7ufd7P\nmvD82HTyuLstpgQVz9MqL2IrFX7zOwsr4Iki/sE9jhAIqK6UNb2lrwHuhRS6OETJDguQycwqveDU\ni5P15/S9l0xzS0bAffASHIiHDS/nna1mXJMzNA92v5SHt6iND+4NgaspRFj5McYl13C+pzciz3D4\nX0zSkKlDQTpJZAjzqyduOgXcU5sROz6raPi+V12shPmKE5aTU+nt5baf0/qBBo47q2UjQMY75tMF\nRVal05IPRf/HOpHBowN7F02gfVE7H44F4ERDK/Hq1xEtrOFK7H2U3ec851+lya2zTCJR/Xcf3VBe\nlxb4RN1NWaePQkEcv/YWnNpQx+wtJntRzhd2+4ZsxawcWl10ffFyNr4ZHupqLvX7v4I/hqx48thY\niV2fchI4tKi54R4OpsCf7NZMQeEvUspEGjrcQxpHVgtMx1vXC3/lApBlX1jOD1aTwr7ThB9FbEPp\nc37PFCi99PpLZuExy4twaIUSOK+4IOfnhrNzP4+bb4TObcMe1gbmAED5+fDlwoMUWWRMMzWsyN/A\n1xIrOrM7zcDWgLZLcIOfS0spfbW4l41PKSCbIcNrB3jFSBrcwm0pQbneAUYkURTiw0Js/NskmPQ1\nqg+UnXhDdicyH0Wfn4tVGjaPXG+qMWBP4Fx3Z4tA7m0jIrR68Ao8aX+cbhBeS0kMS/j246amm0/s\nCXDiO60Fcdr+vOQpO10O+LjBwZ5qsiJnpnjeaJqXT+Et9/jkV5Fjp1xJ3EnlachHDM//79eNvK8/\n/JKOSm4wMLqBigZLP0jzbtnwgaUT77pjjr7T1mI5GQzeY3nuBOxgyscRlg6qA+96hZ+yXXtVArTR\nnf8MO1ycpLPgEkAEsRETTvNnDrfQAd3EFl4I5oisHtpNwuZC9DBflnl5hDZaZW8INJHxcaYffeOA\nI4SZqRyHEDisnaRsUSDIwcwj+tUhOyJyOMFqPYPu3W8unFFJc5VDswkGf2v1azZ9sqH/+QC2r1+q\nvmU/p4fmXXsNumWv6mJCHSInANf3xj65XGYYVUADHApABy4FLykn1IX80gOG/DkB8tArpTRIvOnL\nymsyFKe7bYMu0tUnlo2TPt/h8MeCWZiDdodmrMWa35AxrWLyT0U3n0ZtHC6/Vdt/e3T6oziJ/eVg\nlSZVzkrl/F5IvDwa6bvb6U0s/exSaMcTOHYms2e8B986/g+KZ9CjNQx8CSaf/8NGvuVEXtnONlx3\nLAWQZyLkf9AlRhWJk8otSYNkhQ30sHgRnkTwxaL/hxEClk6MEI+Z5UJt9ycXKODHuULHepLOcPZ6\n14Qufb3ZpVjOTbYmikm1m0IX3bCoKrUhj9oXXboV9woaTYxH8fx08ABGoDz1wA4F8VMn3QUY+F4A\nsb8WtvEmh+XEuRlB1edUNrN8WEkKjj3TwLKejJhrheVTvDZR3LGzRN5p/Fiz3f35bZUALgirF+Xu\npJhpoFYB7CAMH8og/F+Jlma38Ms96J/JN2SLV6bxpjWe5s/aAFb/m5T2WMr6f/Fi+hR3bYw2ANUU\nuDrYb3BZizZl8oAm3Y8N/HtMXtiLLPo1FuXhV/I/dqimr5RkGNYv2vmFyIRzlTWvf1OoQdCpp/8e\njsVRC2nOL5aja1Gbrsb6xLI7v7zOy3OXXnL3A+5G/aRzJIi6OYRIU9iBmF4cPrBOeljwsiThjyIo\nKFFxbCwY3TLsY5DzxbRnwXg5/kBxZOaES7X3X+zHI5eyla9CnQbfH3EUEvY3EV/37+8QTasY1tOI\ny905e4+8SABe51gkubKLjrhy29UKH7O2fYpuytamltn64Cdq4NhqTcnJzHCqZsFlQR2d3NCt85uw\nAMhm34FtpsIt7/67XzcvPhzNtotKCiLKN/Cgm6WqDNXxXQdqWBpk2t0ruAhp3IlUhukD3Wg+LyXf\n/ZO143HqZM09ejrB30WW0BvJbccuf5qb0GgBxnj7M/eDXJJPxea5jNDgIz5AJ0m2xwLDSCHWb2Wv\n2gTrQlIYnhFqNF51eS9oTQcHL1NUd8J5WhoKC/tnFnYhqZPSXTiC1F8H3rMUITUwIwR4Eq5f/SMy\n9vvjUuHFbAre0sYO884yH76/735dC/HbyF81vbM7uEaXpOBXKXUyFJwP5E5GfEcWXmllf5c8aS/0\nX1aavdNjFTbB38PKSNPR7vE4GYr8QZDsjsYzycp5vB/F1X1R55r1oHlKyB4lyggTZMjolN7L0+/K\nh0SaDpL1hBSp0datucCgpkHAK1ECDvvnZz/EYs4aUJdU/3zroy9RYIfB24/4jNs5h5aCBTMkmeiR\nAMIDLVnyEReJ7oVzZ6u1b6EZKmUGyoE/NAWcRmSPjTUJgrzF4ERtajmDO5hzZdyTOkti/h4tFdJl\nsaYMNAKg0w+186Fz7c25LLBkit7BG/wjrAPz2cW6JI3S4ru5pGGi85VQsoeLOW80nnosEnFDip+V\nJ7aDxGq9BSwM50DlrWdIxbvLObiVnLR8Ar9HAyYTzspjd0FPpeLqQVnWy9kn6nIT5CqukkpCwcLo\nSlct2bLxTcQhrwQucx5/LHBYpKkrp7rrzkHZ6P+cTUcLHJNyJPZkZK3heV/f0OcEsM4EKLZpD0g1\nJv8wATCKBeecm7/VqyQllTUUWvP69Owt0G4XzttdIBz8DTPtaI6ts0hlmbOkcDTTvBf5mZ3rNmnw\nlg1mysjyO/US6Fuiq9t9+3Xofstc4bHEm4YBjGCH1IHTDzvQccKfnM/cqleRvo7H5eXiFsZtPp1G\n6GOcsXHa95RzZj79MoKZNjnpEY+t8YauJ+ETl9KG2HPb5yLpP6Q6cV2HTp5GNHhvtcCoWQBAiqHO\nbxr7/HrkWj51SqQJe0KV/R6u46GvpDHfkVkDlouZTZy9uiFGVIo58fKeM3Te6Crcktg/2o5vSjkO\na7Z8yu/uzD4/L9K5yC9W0SCtqS8uulGQZpEHMWNlzCWY+pOvRSTSp73IL0EUO6DI/7fF2UjEWTyP\nl7qk/O9HvnOrrWAV5MLHT2Axk1W7H5akhnhcPAA7Lx/Q/Q5iLoPNHVWxjlvlwLlwWq9OaQICR4jq\nGDNMi14HM8VyANmSUU50AAoSn5ABDzSXJ9eUaJT/oU+O6OyAckpg07u/yYW4BkTMw8xIioyNOSqn\nvyJ7cBAB7X6KOj/KjRLLt2J94Qj6UBECe8x1PJ+/oKc1U5SNGmaDsiJPYE42OuvkHxD9CXzez4zx\nMiigISEAWNHfQrcy73vctjtz9y0ieOjN163Or2pLp5RE+4EnBTO68tZ7DiFsYAvgyApEJfTwTzS/\nH+NfjaRftQPoB23DSbd4otwB9wqCTcgyKeHfwrA2tWNoBnRRDh43MiB/X3InWXASYwMqfd2bTAXB\nO2ZNmuvDjFCqHdc6XOPqtha0OlB3JmvtCjQqmRjfwBDEg9nRrUo5OrhjinJ1ZZwsA6X9Oc2M1jUP\nlgQgjlV0P/hsZqt/GDjLt30k3e6DvQg5Ye+Kvn8MkqXne8Omnj4K3lzvEKXPYgWrAr6+t3IuGKRO\nr/774W4XqSnQXDXYSsPlm5VAGXmAqncVo5ekdQw9di1hmya76/G8VcN4QK0J/Q5c7xhsRvZUhBbD\naoZnX74rF3GIzaxID8PujDrYDMP2QkRZijphPCywc/l0jsldhR2NB4RW/kYPN3uUqK75cVesEaL5\n5v/AR9/c4p8tdoJRCWfRRBN5m9RRDQl3XFMUCUPifDExugkQfos7EIKRGrXely/Hf1bqQd84KBHw\nQgmROHDt2QlItAPE/wtivVzftCklyirO4+OmfkftzxGbX1/QGxAlJyR0gmm6RvKa1YoKUrKgK5S7\nXscl6MYwHWn1FJriTwerIP4mWdDdbOdCyCWKVqrv72q1sgu9Oofps4WpH4Id8HnAUAeoyYdHVdyf\nJnSE8viWhzvF+yf1tjrLZZySiZWT+ad44uIZkAqC4GRPwpOiYMPcB2Wa+1jl9Sjtp6expmx+u/5h\nAqCBE5nVYwwbNJ5/97wkl/T0DZm9KVtrlWoLxqYBUhTAfQ/Vdd5kx3Es/xK0tvL1c62UXivN7/I9\nVqga2Z9NvKTT8owc+ZOI0CANprFE4IK8JbXKrTc2NMiULmEnCU8OGYBYIMnkxGLerH12+A3ChuLx\nHIhcg1avfqvOounj2H362C2fJYDtmMVv5i0y8x0+v2FBjrTzdrisolTypKmUZ2MHXga5ZGY7mXqn\ndgkFBZOS64qYD1nIn48V5Vlsi7LF5aLMCOZWlXOw8WmIF6glbehcEFsPSnmyeQWeFK9duIjIEiYC\n2S0COsdbabYyYPGGFpz+iI9h675DoLj4BC552U1qA3tp95Z5GrD+9NcJQeNA3QjGp8mHde/skpX4\nYkex6WxEDA5ppcdy4YJO/pIrDUz4Y+KJm2AHQ8G/1UYNLy3QQm2xvEdP165sZy/GgTk/MxGtmTrE\nUumAVGVSTzDM3pMWOXMbHsDiCoY+LxKBmOofdTajcbPQor9UnJOOh3bk79plZvZkj/kjgc1ipavu\njT6UFxbm9ghBi9L6eUME4BbN+EiorSLlyWruDKS6fq83mX+4iaCshfP6nQnuTU1728nJ1U7J8h9l\nq+nruftauizB/m2VnGlEUGvC5d/olcqk6pWiMeuemTJM5+/BeAZ82XblX62hnpwo2kJhh0byu56B\npAUGKnLdamBw437+UlRRmPWEp2UG5OrqjLR0JMf02lGeO+AXXllC0ji5T+qUuITeYpHEadr7rg4V\n4vCNuTSmTymv06ja7bmoQR69HQxh8GWBKzTOLLC0knyElBbtUMaLTK8ocsuJxklx/fiJ6dcTfyay\n17QKT9aSN/+h/kzJsmdd/rSI6eJuQzg5lq1pM9nNggWdnDkZteF0Zg9YFqHbGfJMRqZuHxiWWHYf\nhs6BYwa1Si9yITAbky6OYkMYRRXLKB11R+pmRoUoiwr0xLh07t5UF7xEWYTqv+9KueNxtSOeV/+f\nEdo7uzq0Dii7Z8WTX2z7Aga6oO50BUYS7Zu9EQqXr8lj66On35fDlpEVb6h0feMPSn8Z7CCYxZxv\nrrgpc+B2PXhRlSumar1I9au3GrGSzbXaP9tYa1pWTWneUxksfdk/VkDLBuWlUN3jc5hvC0URlDsn\nV9FN14sxPOVWYbJt04oVou/R5XA4BNMUei+KMqaZ9LsMWy3qKESHAs0vomXA0Q1xxXac/zDN7LsB\nRTS+2gszGrNQQd961iFcXZUTQQaittUszpL3Z1wklSTLGQ3Do9eYkpQ4MXTmKjEcUcTkDd/8NA7M\nahK/cQ2y1mYEyJRkYFICvafpDj2h3+Vrzbg9cJ/+E1y9pNY2lS19jiEtaCisx04TRLUodD8TP7UQ\n4/ijc61VHaWa3tTgXuk6D9hD0oCiJOSUItz8iavDq1u7eDRCMKfEuHf2v8Ddhmkd04t2N/NQRTRb\nIoNNHHHBrQ/dszA1gWrgEV1xZ0dKWps4R/gk47Ow72agtIRoPMhVUyWaBgxaaEF9NAB/0Knc79/h\npDrIRM3UDEfbvOJJfBhGpmEXa5waa5PjxFrms+lsyTs58QeBBGPyfXH1r00fkBCCrhrlsM1QQTrU\n048xf/oyN0tUcjE/B1ZIBe410V5kNJfAtxAh2VPfvVbgbecLqGm3bRUljE8ozf1n6ARxD6GASLmc\n3GOh/dMJqp5oJn2sOFwv+B+AYOeGsnY8Qc0sa1DnEwTVUhDCZ2M775dMR3zZGEM/kk1pALwGQ6Im\nCnigap8WJ3+AQ+x5TZJsjWnnsZFbKiAITDP4+5gG9BpBQwVL7bSQYfWAYV+HsZNkpN9DYVKoz2u/\nbNnXohT5+gKpBQYKTg+h6XWaT/lwjspKXQkftnXwIgZC2EoA3j1BVjXTu6ePnVHr0azUwa7rhzUe\nSNoCfmOWeqnZSvRbVB+fRNZRI4hAVPpgptKPpCgL7DekF+8a8+X+Rca6jH9KFM6Vat3qvo4j81hW\nxg4glHb86eHWcUlzAW4wQR/D6gOuwjzvEi1jMpNNzZda2vtnd6b2QWQHKGtf2V3gPQNE7qp0z6tn\n8zMGcmW/WdC4n3Sc9GSGmsVAzNkoJmkCpBSMUwSbM1Tu1dX8eqXtI53zosOPO/buxyAkhN9sXDC/\nt5lVZdFQB3QqqT4xDjY+CwXxguwKeogUHQlcmu2PyndG1/ZlougRvZrmb/Lkw6bwLFHnuYLBZbov\nvAFBpbSKNKvQkZfTSwYiDNvc8BMFjMmjcFamwmizpssKFLlKIIbAUGDo7/9giFPRr+jOsQsmEYM4\nvL/nKadZokw3N0FCPbZNG7oP3I1wFyii7Klje6QNyIu/MqYQmb/XY51Tt3uPm7Xfc3/tNrmlri9s\nqzbMC9eeiwC2HkXHim2p0c4EKVWinPJkmzzHhHD5XqOMojAJPhX+ZblrNiwdx7yZ9FDd+udt11t5\nKBAtGk+DkDqFAWmcK77O05i4wt2nbfCYpoKyN224bqN/dwJBUcvQDeGU7zCkK9cY/M1RyGyOrSBv\nuZdwpqjj52VMyhC4eSw0VKnH/dkjXE6ob2Bu4okt1VlwfosxgTLiKv30Nxqa6xsSgUBdLW76YgRM\nSSxCp+DlI4KsYaCpTLqAkTsNbWs/XXcz+KkpZwGT3Ak7gUk9gWYDThPEGhAMifMZoNiuB/frOteo\nErLJDy9+/CBi+mwbqwhlM1mSLtEL+QjKXQtFXnAoKwlV0A0S3Y1F3eZVIt6N7EGpp+GqKm6pbvJi\n19Uv96Xgojy6KuRIp/r7ylJhgsaZmktjQVHgyTwbhlwc443FUjShzjYUNu1v/lv/ma3v07n/Nu1v\n5Ygxneefjd/BazNEjUTdLMV+xI/8Z5v2ZgRVVM/EjyzoDUtDR+/Fc3MUuqiQt7vYIQ3vJshwAQ7H\nq6dkx314RtY4hRvZUCGU+rnX/qCmenpVXFV2xn6Cc/5OF4EXbr6RN/qhCuiD81yAQd/NbjNEOtMW\nVmqXqTPsOOPY+FHam5EW4IxjWPRsAIX3P6My6Rer1kJd1F5zhDJbArwUbEm54c9GQkVXxhTWYIqF\nvH+Qp0Yy9tyMUnRlASj5jMvgwe3cUuHPxlyPUuZK+rK5ayJVxweBf8s8NsE58TFti+6DGNH+GMoj\niJrcHMl7JIRez9U7WoBdNSTa6Wu4FsIQskSZAPRnqG1YIhSSsLnEaonRZ5jHn6PxFIsGHWLkRRTM\nPYYKNKVMipW3WnaHIgiN57KTb5pXBGnXQxTZWgNJ4Oc1Hb/CLPxx+jpJFEHcrEa1chVQZd0SORaJ\nC0zRLJ3K6naY4bpkuEtRGvqnEiC69i7rkR5IYJVZn4T0L/IaF+HxfL2jZBzUqPiEpBIkGRIoRoal\nnAnVsez+Tf1g3sKGGb8Jc7Bvv9mbKP5r+ciY4SkeEHFCjRtXAHTU2sIxj+cVDrOGcwgj04QZg1CG\nf9j+AucjM1EmfmYfM6GMwlJ+jju7bvRNsowv0BBNlF7J8l98+ikv4vmUYM4WSkRV/jc+XOLWD2y5\nyNpM1OjVk1/KAG/In+VQAh+vgz1+4/xoyotLH/qRGT+bFxn9tomW0+Yzn/gahFC7LGrb3bI0eQTp\nQSejapmUj3nSlxVQ7dpQNZ0NrLwA+G/GycUyauRzRBxKtZMNHDmjfuBZX7Tcy7YiatzCZ6M2eST9\n05E4HperTb/cfGMm16ME0VdyxSZXAmb+OckEFGyGvWLoIVi1AdQUkJAh5rbT1QIkSS95m6iNjS13\ntFc+QIFe0S9X0DKXeRy730ZfGzxDHl3mt004W60VSMKldSaBLcHxxkrXUno6fZskEcRQEFd8weJj\neZkjtL6rtwkKjYV6x+cAqIRIH2CIcwgvi1MM+SbuB7Ej2OHbWGsH+ae6kDWlG5RxNhyL9DD4xcf0\nDdxElbdQ8rphwwoJvoNEe02bsY8iwtjuSyD6Y6clNaL27fwyCzjLujIWDUy4CHvK7Vl7a2PLD+dw\ny3uIbO9kn1IMMIKHSlomNpPap52CEIksHGtfk+4XSYfSkQKKp/kNqVVR1RPQGFToDqSveiV0bWAu\nSEee8c2awA4VDSIte3mzaYqUYDEfpBfjlJ1kfUOttH4qAi0IgL4BL+9FkiKjuwGeHVs7r+v2X30a\ngWOPSwAX10NabuD1IZjK3kIAgJJXnmco2ziHkW63XC2rKj3imToI3yyPwL11wtrAgJETZGrJTxO+\nMfLO+/2U61Knhu2slj+hYdaJqoIn0DCviHnI7DIQ2fAgjjaBl5/Er7USC8yzu0STnipb7cjZiTZP\naakr4i4vGo4b9Bd1itUaJzJtsdWrkVcFA2gSmBCHTYdro1jelehFneB/aDR7mxtnjz4PoHdES47A\nOuvVgKpCzNoMR43wGwKzG0B32o2W4cyo5fewsH6eHMn+T4EedcuHmgurYiN62uO0nz+M7aIaaBjS\nbPAJW3sIHIEEdl1P1Qtj5bpN+FoHJO1S7NGnxpS9OU7QMPd0thdPovlaO1Whwj23a2G2ry9SoW1z\nY5olooVHpgXYzMH7/aKVZy7EIaC6Pq6ILrl+N6Ql3+UuOAhOVuIGmgA3U234T48fYm736NjR5Gul\nrSbC9/WbAzLVLiCWKyxHmQqbSEsaOrjhz+ddTL3rcvzVLwFzhjTqRWQsPbtItebs41tdPf8MvInt\nkHYDIMP1RHhTu/5dAS9h/X3tQYAQgRhCHOAE/4uMtfdvIjgAe8fs2gC8QK99+EappIfJfUkvZKML\nn7JtFbyd4wN7CU5dpNIk8/RsvM3z2u7jtDa1yIZZIHNQfTaJ8WmsrUrjGpbjbT5lPZoMiQt/jblL\nk5uJo5y4kpVNE9Mg+OlMSMqekZyUeFSHuGOBn2smMqko+UVNaCFxXInWjz4TYpqXp288S605F7cL\nLmqsI1yHvV6yXa/8DztLhmbusW0vtxUKU3I2h/KupFTrxLHKOWOrxyix7kJ4L/g8/PutXuU1kAoI\nAu9OkaBF9G4qAHp30Eb2fxolsyRqSg7tDREIfyA6rPwj7+gY9z+2g65bC2+O5XyzC979ETBl5EmI\nPjuXiDRlRRDNtKsOLoz98L/9GAnV0AudrPU+sgVjxwcNfKaRqib2icBzWMIIsL3QLhhQxLI6bZwp\neya26npYMw+VI6+huptBzOaBV//Yonn62HLD3MBmDEsZRbSRiedUiuv7FO2kTlQi66FK9h02Uf30\nzrbGSKr4sRI666hzuzBE11QBkJqOosb4dDlHX01MQSKIc2w5pKvfi1MECCATgZMZ7ilhizyPHPhM\nqYR6erClv/4mrKlfdy/eRyaWBenWkK0J9aQB62+fNvXWRJ3F5SQA4xtCLxOlSKoqQVV+311DUvax\nEm5l0r5y8XMpy8Ig9W/TOidKG2ruNkmtRHwn7fomGNnG+YRWvlHPYkKcrMXXVZYEHhVwrwv0FRdw\nqqilhFaMowQStCU6A/Mch+SK8shJHK11OJnt4E6n7GSS0VWWIoddIm5+RK6+DVbhGIGMWvq2c+/r\nUMAozYzqqMD/iC/ZUuMEFaGnsRaf7fDLta1A7VFGGX1JrfJ84/D89+TUzIoiJt2a+mlOv47F/nIt\nDAgtzOSYGKb1NhXlkc5js+oaoygWm3Nl2B3F52XQd7P+eJfDpWK2TjB4F1BX9GMnOlI5S3kWAp+y\n8m67tK5JQgHqpN0CZ6yLbololzSu4PX3gW8kafdkgnx/s11MMaGgmdlGj2EpOY3RmzfYb0zUcv6x\nrDj6PCQU7tjBx85GxXzUZpzyoW0vswvtkLufpFueFe13Lj/xkjdwrV9ztjg3RmEWpqEDhb/ewj9w\nMDgzH1m5Waee3zV6RsdM8OywzwGB7r3QEi4+TJUT7n93NRH2bl++VBegv12aakTzLHKbSb6HyWdE\nUctb0DJhxi6aBKuzwBDJ8IXilBnK5vb0oGMpyvR0+SIG/WehKC+lUhfpwyKzZ/x+BMz/AakXAFHB\ngprixyoHCJS+IyJRNTufZoRpXGD/NdpZEyuZEAOBoY4iuamF/oaWgXBZgaa0NGa7axmq8VyYXhhS\nXRaEXo0XFlyt34x/Hs3t5P2AwUqFOhBalvgxSFuIdt8s1SfXHA48jwEBSY2mRa/LrKm9DL7CVsfd\nW7AcoaS+xAkMd1ZA7zGD1+xV5kFBSJ+oUm+BHq35pBGjxdwPM4IYx5qL8t5y6LkBzYVXQeXrYz3n\nAPikEn834V2RN3BXwNBi++a9RQG/9kyZFKAgjy/EIEDqsZ2Fz1a5AD+kRnZMq4Gy8FqfvtzaDX51\n/24gW4s+KdESku5GMoJiIdxYoPSC5yYdU6maW2zfvhU7j/VxHIVkEAuL1jggslz7UvWmLvDQSvyg\nAOiGhRngYu4hcVry1NbfF4Y9YOxx5VSFvbZcdVav2L76PYXQvfZa6b5zAj8nMtYby/auDzpCGggX\nIFig1IHnalQgAmlg++abElpqAE9+F7wlpvxSuMr9qjsXMJFa1NLhTAuYn6KSATMLJtmc5ZgFjtV/\nqZI83QMNaqgB/sFXO/zdaW6lc3DKYv0khan0DLyxC9ZYoU56KxHnwcsy316h2kq+KlFI9JUD4R5K\nk+NKgW87SF7e2IsYnl9F4WoeUQ9uu1TrYwvbBQikWhMo5zGJ+jDNnZE0hXYvD7zLnrpjNxk8u1jB\nVI3+wFkgF3y9dft9r//mAputCiFpTIwLsQE06NCVgTlG73PCHAGOQBkEBW1i6c/u8at890aDr9FL\nJulPXrkRHnyQlGS6bml0RA8vNJpoVwFRl2QRt2qUo3qTbXDEV9aj3xXdfeEseUR6MQCshhixhNj0\nKU4YYyNjpsnXLYyHerXk3ioDeukDGLEyA51ZK07Szu2UDcIFqZ+ab2ZHiovr68NcLfw6YE1qkg9c\nYLT5Dk89XCyGIdn3pgnES+Sd0tcg+T5Pp7nx1EigHx3ZihMi8Oxe/D6guDWy5TSL1G0ZaC8BvFYa\nh1C5Pfr43DjEoojJFMUyz4w/w5lCEUBEh6E8gXjAMVjzFAsA7vDjdWz08GsKz+CFWPXVVrVAaIRy\n19k1gGQ1MRtI7CUf1wWh7f416K2hwjHgzz6cmETCt7TexIThgarGxn+VSXO5pr5O1/Fs179fijJE\nLmwfZInZ5GW/PJnyfU80Z3xD7Jf8tA9KEhVmkiNE+SX7QVCho8sBVQhT5B26NKZrKHXkuFWKcBsM\nBhB6mZkvndJIuBm6ALke5fJITcrvcci6rA987B6eGw2NVJK11fP8ugBJBkmiSCxH3U6uXThxgqMz\nPujL2p61OUB/0gPUXs/sr7qt6X9/kYDGwejPI9ievkME+XteHvCyDtPlq/mjoWYawo1wDIP2NnLV\n+0QatxMMZBMlG6naoEf4pifcaMe3CAyIAlbYCkFgKoMf0qVgdHd05KcNusDkLqz+bNqx0PyHucx6\ntQNR+G/WKS4eXcAdwTudTPLXuqY4T5dXr3EU/fhG2oKFgHJRrAIllJQn5it+B1ljBrm8BMXVZC50\nkm/y/Dv2k1RZg83xH6UoGk0OEw29nx+XrBNqjLBViBHSdzLAg7XUs4irDXyfhxGycqBdvG0a98Nk\nxNU46vJazVxZWSL6U6mAe6Sv3Sr9jGmNIgA/VdbNk/SIP/AhthEjNhk/19pheo85ryTp4KL24Vhw\nrSotkbHebmTArYBspDLozvV51DeBkxnLdq1AwEdI+kiwzBbiud1p9rJEfRCLlqRYOI2rNY48L9Lz\nVwjSLp1+SKY7ERb2h+5bygkAImLrivJNuv0yj8p03GAPfu6DwfwlYjr/ZSn5C713pe6Imf5odEyk\n2g27gNss5gKol+0fnIRlZrAdBphbK+HDGns5LVFnXt6nhEEzzrhmhY5q8YS8OBSR09NzveOjphSo\nMFsa7DV6Mx6FidSa3xeL8Kiq98kSg/JzKmT917YSdmFImgN839ZxMPonkiRYfizHC0bcdFfVJC9P\ney50x1ZvNhADKvxaQoVppfhgjgY4RAL3yo8CNeL+8diNOvxxv7VXL6VmkVHb0OPSK9T7jM0UNC7g\nx2kdywCP5JyEAE1ZYgyfhp0cZseW8D3oJ03+f6aWUefyoDW+U7lhbahfjP9EC67VrkOC0aA2r1qb\n0EGdy+Wgbo8LwZqlv+i0kT6JJVzJAs9m9mIkVRdSau7A6EtZ++Gui0K56HTnHxdBZpKPLfaMY/Vq\ncO5ShwiXPBEzE8G5dKmjHC+z12W1EDxgsCLar9+YOAjxKhgHkBGfg69+NmO0ydwiFZtkb9kQn2n2\ncakas/WtmPRcBrFKxTJv7hrqsa0tATeeQxEfLYe4qtlUzpbtLY2FdoNRQlSxUGJ4pGgiCSx+x5ri\n5dbUwJzYin9/1AkNrajyQ1igqFH63Oe5iA05U0OBHL1TZbqVJu91v+1hHGccThB7kV/xn+sWCL0Q\nmMULWQqEWLR9aFsTO9vP+2fvOf6Zwuefn0MzofCFTwq/kYuMgyppHBeqD0San0S3+DlRWFbvQxtd\n/2tSB+nGWbiKevmP/K3gE8oRdXigzg7xbPH+gh2lCC0wJmKwTgQwHIC31x50ZJkg8cci6fVAAw/C\nVHXrDrjZSiroK8utPInMK9UgiLiJZaxnv6VMTQfV26pYRuUPBEPpZ4PLypuOIcDs1tS4X6nUNDU2\nfNyzzsyS7Fs6nTKsfTb13JGw+dOOt4lMUIBEU84U5RQKL+jrymEyKK/sSA4kuQYjQXLCHUIIG8G5\nHUgZ9GKsNo3ugw6mpQdnfJ5cW5I10H8JLWrMiCExw/s1EXPyeM59eTd7T9tDoN1rAZKPHG/JN8dV\nh0oYFXVBv9sIAGpOy1+yMXyrapdwkmnq9M75xOw+4tdRAWNlhGUgeer4qaGwM1AiZOh9ICdC5zLx\nBQ6+b4pwzgxHxvbCVYSY3J/6A1H2OWZ/DJsHbkCJzKyyIJI6c9Sj+iL7IWOEz3kPoTdwojbxnFjE\nFHyzNYqDISswQg6KXYsPWTEGpB/obQREvd+ABflTfjzhr3Tjftzcg8LURNmOgUQANWT1DWQSbC19\nmfeCmEA3Y+mKQXkzlCARoH1uXMPPUpVC1ipWTPqeH7TcwHjaNCNhXgDS/uk2Z5GBD8YiHzSvAuVf\nKZvULyg1j21LI/bSkfQ7+lk8ROtqWPv7/JtmfKo4EJbyI7aQPWjlTqdH9mV0ELtfD7EbTPEhwZZQ\nHGWfHrL778ObaVgVlJ+4cur5V5ysxaYVfZvWa3RzOCv0QqOo2lYVW6b1BV6cZPLYruo7o4VgOq4K\nzMz6Tv5RTu1X/Q0sXm1kmGF9b7w0Pc5x3QBxIGCO+NzcC9HZekrjxRIqqqG9SREDtovJy40tvW9B\nVLyL0e4LS6wq+BG21T5Tm3wStOhCHnyJAneG91iZNFnrTY57YkATwIja/JJiSnDtzisBcdOXsnE+\njF+WIPe/OXaP7EXFwWnvQcMy3CEeH0v9WQ8R0k7m5/5LJUSKZegVF2vImSnXZte3+N1jLmIspK2X\nLSW00mKB9e7X0tmoffFcNa5K91v5qCKZP+jH9FlXfo6FyNfnHZeBtYWE1rFrWkkNoyffdTydMxU3\nHsE7+QvtoAiGifQOxWPvyL6jtcKpDsPkZKwWMaDS6t6CrUW2+7FIzIySi4GPD+UtldMfOgfX/xY4\nRwOLpHM0qz77Vk7F8r5igDm3YdRUclJRj/9p3PhuaGURCCOfvYY/1YtGyn4pRScUV0eI5mWn2HkY\nPB1KwhTPUTGwVWu7Y3fD26njzSehEGb15soneI8/j2u57nBdio7e76zBGd1Ae28DCxlw6eheUL+t\nVfbb+l1BrerQeAHVxnm+duuLE+rNrPfp+17NGTOlB2Qf1rcFqQWYCmgEI+VzyOhWARntifEQ91cL\neG3JS8IW02lPLDfwgGnw1jdsBDrP490+YoZQxAo1kmK8lSjgUXuTchXZtHz6I8/mHaTDsZ3ZJQA3\nNXIjfP4KlMMnUOG5LiaeDZ03uItPx33c7XIlhC8wCHIeOQHEnRoS7Ah4f7M3FP3oommN4YQxreJR\n/uAHpkr0sCdoRVU3J+7N2vwSP685CNjrqyl78reB2aX7Ty3g0hVKTHlyPzRgA62N3Gfb9vMrk+W0\nY78yHpQHiYOQTwAsjZvyYBwT9f/ldXZVwC1YIvI20GQ7kL8uvhV/+zbXVzv6kyjHg6HZIY+D/+rY\n9JnqgDOXkANYZNab/6uv2j1ojjDqBOeZShxkJkbTwoWc1yT8OmnQVIXLmeGTpGuabFKI9Zi6Q/06\n+HPwkG5LawIar0MHYUs4lb8X9uKIVauJZHO3fCfDJpfE7p0weI+DMayYvriGCPSu2+0cO66waMD8\nkoQKpOmFxHOrio+PflCURVPrWAdtiOVWfTKpPdCUgyjcX/0SNGNc+GsKLpPgnseR5baF4rxbWWCj\nkZQJhVLuPemR09jsCHluA70+mz9AXQAg/pa7bfPbMldU69lewVO7xbwqdUDy4hdTZYJCwX9TNp1P\nNpCzdGsgoswj/88Cy3icvq+rPBdxfqogbUZXI0ZcBQuBSscM9RPagLxJRYfOWbvPYakgaarvMURQ\nUKkmvS7oHX3jyOH166f1V6kX7iU1FtSODnMP0RTIiVB1jMY8PPv20LD5653dtu8nhpW/yxdeaulB\n6HrUOModOutJHPogWpEpYquKf+DCjyztBIiWtsXp0rIdpdackzsWc3l3gZdiLtsV1BhLCsj0FJw2\nU26qRLCKKxk0axjYCW1xbCcNn2Ui03uJuYtzjrQJU/ng+M40qPAoIOoonXkN2va+Z/XjAlJvXRLl\npvwhi82zybVUV7GX+GBE0mShC/h7yvkzFiRrRDA/RwRQur+2okCdE6dK8hr1zzFE10JBP0d9TUS0\npK2XqZN2VJ/BQSHEd38SApjeg4BZNbFB4+Qm5v2hy9XGHVWFBr86STemwiPK/HTKyvHbsTG8gt94\n4Y361rCNBFPqISw38qIcz8ooUjFi622Y/CWCjDz21lLX3iFDIFf/ZxxqVSlJM1NoqsTHOTYaVwF7\nhlfj1vG0b3l+cGCZNArEGD9fxGx3Z8OwL7Bzs63ULFNDz9lM2zFr4UU6eL3vuRH3yJfuI3H4I77P\nffLuBWlPBg9kdeOw+bZrrzSRIRmKmYS6kOz3Uyn/i0ejd+TPM5dR+qHmiFt7OZjjSaf6pYIDxuFA\nDZ6PvZDVBcTDMavNkIcSkwsm+B0NwELE2BV7pbI7jpTpkuTQpZAIcuURtrHRXOohYiktQX0f2DId\nGDX2juPGYqAkqHn2O6TuzV+PKfUMTryW3TwkT2rIqBqzrGBtN1hU0JVrCaZAM1J928FQGECowe4C\nYw3phOU/wxWfcpsDd+JjsNmQP1GrNaLeCvX9iiM91ya+u8I0UPBSSpBhbDExnHRQ8x8L+Nxrv2P0\njVZpcPraT1DfqxmICYoVm6AY7rdTgJrjclMbYmafOsUk5wRRTQVAYPBpGcA93u8qLRqEvvDHhnS2\n9RKzGmNUV0hKqNIF4f426z0tJi0IkRW0znccZmt2d8TXKzYkCOfKAliSBqpZS7bodKplqMqc4voE\njaPXEf1vKkbUQOV5HqmvUiJPI5Y7jQrosCCg5VL2/oqN5DodmIqCCTd3vdAm/tt/b0IuI5mRfpP6\nV2Y/cRCrmE+MumRavYpcem+l50tCbeSbglB4grrAtBooNSiWou5vd+6WISoDxewgOeJQGew6HhaX\nO3eGe6KfJ6TaL3fiJuZF3hZ9XXqyDuGrb8nQoAt6dqqzzDpGo1JaPScwI3EIpud4EhFE1Qti5v5a\nV3Vl1+6/UJSBa8V/BrByhZyt7xmrFz+1Bgy6E+Z8DAH3rQXV6mKOieQAoUPkW2mh9tx9xnFpbSsZ\nTPYhbec2cj4bGLI5crXAxEScCC7qH6wD4Zgnd+qNl2NdDJqKJO+4hUlTbuc5wXXvarGBBhgjMHLs\nXGdXVwHOm+Cc8rKXJvr7+5PUUtnwD8gWKxJXPimyS72D9CW6d7dkhkbP7lFlaWAatkkLR5ARwFbx\nMZAF9W53PRE329iWi8zBjf2WDZBSN2Q0TcA10dOE5nbnbfeT01IkqmqARAkQh+nTwL9T3bR2A8Pf\ngmwCqBj1+5rRlYslJ8CZOrLDQgDuLDJ0EbX+JSDcQd6jEyne6hgAaoZs41ByP/8g/PE2alqR1kRZ\nTYhiSUk5FbaPSLijYoL5o1w7Zy0qqdH/p9GBtm4JO9CVzc6hI09H8Uk2lQbJPzvt9YSlv3v92sQz\n2TKxXXtBQ+mUlziFQ/8BYitiRqoE2cdR+mE5f1X1YvM49qIirMbEuumBGiHJqvkqNUZBHU0ZgVKg\nvobG6mF+vwwH28e3no4tQ7zOa/fDVprzZjLGnvdPUjym+XCgbrKyypqUWKJ4/T/4PjaanyzPvvXt\nRlcGp/nhqI4n2u93okHPDK6jV/5phIyTYsLiXu3CKgu+8IRYdXYOiIo/e1Y5WDTKYgQhmBVshF3g\np1hGuj0SPHrrAaGaEG0egjAyMEWxwFicIsMjvHDzms9wj7SGPo6CFt4YMfar870S3Mr4rqPPTLEl\nKaX83QSEnw2lHk1wIWIFRH/7JbyQRSmJQSWe1dyCNY3CJc9ckpBwv+ZE3JjOz/eE9hu5cxojJXoW\nlr5td8y7IAWzChiI0YLBwLJRGcSEKYwgbLcICqV6JillP9J4X92YlMW6BHoBsMhB1DOl6TyZgMNQ\nVlZGWfNoYelupoRkIT8M7MzXISDSzqoDIKM5mr9eoSAo8ib6YK3ODFN1Ipi0Hm+qUVh97Qb3LCXy\nJ6TLZ7yBPe3PyN9tI0DKKMQaEf7MIeR/pJVXBGsWw1J8lMeUKMZGj/PNQ8jCoeKR8IQWRQA+u08l\nvi2HhJO/OOKzrT7wWfTqQ8JQJWoego0wyxREKsmJVph5puuURbW1rqMZ59X/1NWVNk/LbJ1gpEhD\nRDB7m4Z37EdY60O5sOgWAgfgocCGN+qw4b+xKacYxMN4HjXO+wJq18wCTE6+j/Riq53L1N8BhQ8Y\nGzmRansnzeytnsaTfsvP369sjt22XF5RMpCRvIpwnBzhVtSbsoEOecovV9J60ihS9Fe3klm6gBY7\nO27ky2+Nqy6V5sFI8PXp8SBwkwq5pNi/BqYrHGV+KbX8d32v1RUYbRrV4F6ptibJnNz0aU+HQQBw\ns4RzTcJUIJhlCEM+J8xX7HwyaUGYXM4Vblpw6Pdu9uJT0tjyon29wMG41c5BLhYFL9bVxSB0rylA\no9dhCoNanyu2VfmWH0K1eh+YJaNXtEb0ysEmWhCOAN/BB005lvi/w2S97ehdtGEWfujIFXRsvCgY\n+RCIDAxVVZqHL8q746Y3NWuLClwgx1vHx1NcQUcDBNsRytgo9Gb0DigkKNt+dAAIGmfD2l8RTA00\ni2rxwGF3erRv9z6mzledqzEO17RKC31VFamUnhcuZiDRaRRCBnE8GuE5BHaK8rw79pL1YSIawfMd\nLK7hHkbaDI3kT4s0uTl+t99PyWMS/B/0yfBkHsKDGfriLreKrAncpEeUpJVFKdFGrPl1HIHS5ZEX\ns1gVTXjNJJrMestKVYaEs4nViCstGD9zSan6JhEmfaifIkJ7GLKw+NimA9uOzyKvxUxfRCCFUSvF\nMprZGCfJ4ltS0NYsdjAs1KQSH/5sn/PQ6OIeDHlZ/n3Of315bRk57pzLC1/aVqAi8XLsSRefF/uG\ng/x4R0AMUW0mo2mdnHH/TY/0iT8LYCmwQO5G/dkxHjhJRFJDZ3qUZid99q56MwmCVIj6WDNBu+KO\nQN6QM5N82dHzc1QI4OMalKCyGwtF1fJoK6eNGi3dVQTES3YoHYpJwy9mkxPa0rvrWLS6/4KyUv+I\nEDZZY6lbAg/ozYCu+01v8P5fYavZmOXKq7EICFKOmUroiCAKQb7RAGvnYqGcYPcJRAsDYdAoIFDU\nroKp2Ovcei4dqjC/IMmPpx2utomxn1moEPZkeviZ/h4Jw8M+YkT9VrkRWpAoADxDnDqVJm9CyRZ3\nZYi06cQ7Xi+nISoqnuU0wG4niseJcLPhRyK/eN25gKr33zC0KA1F90dGy8K2XjjGkAy166Fm+3nU\nL2M0OoqaJrHkmiE5GOorVEOvOcgQPi5mcLYVduX9edasttXX1GWuqS6e+TdcltrvITA2mCaGW9W3\nuLXjKkSpq982wMXZ6Lezt5GVq0xxPV/hocBpYZGNk1GnQrKh6TZ2oDCwL3BfXTqGPrO2BfEl6Gt4\n/y3kZDSf1MYEfz0iQOKOy+lWAlsnuPolMTRzT1cOGY/Xo5ZfvbKryDcTb6bhVTvO6/ytROqjAUmQ\nTHPlyl8CeG7hdq6DGm/TlWk+DtDGTXDeiF5IwFeBRsJPlaQ//IAkaAdtGnFztK5xLzNvyFs87v/9\njkbEu4pvPLRGn8alKJB8ZZ/E12VD5owB7dVz3WdKnfFS+ewUVFFKFM/LqRQIoLDfau36JyDEBIoK\nCc9QhI4knWpjgd3rc0Ror6hYufUfdIhZvbYz3935zgckWWECuvAIgdz5z2ckO8J2UHAmrLdWFxtz\n7NFYheF0uQVqIWu7hRMmfPVEgJNVslEfrtSENg19NvNy3vkke892kD/uoMfkVuyjAkS8PzGBrXJ7\nSQqI6VjMifzTsYMS/WQ+kXXwPhjx09QEncMmZSp0thPdg5CZk8eEvrZGprWuaWpDs9S3lN+NV/qh\nEaMcIGIuEMxbxMgD5WtZb20rxjLc674wYAzoVZKd1k0L9/5C0iSgJUwYBe49dyDOKYUMctmkESxi\nVd7eT/IqusXB5Q/PLFKKSpIjnafKrHv8yGyfnTaBC+kzTlVpb2G++mJNfwSbkDuqAvAoKjPAVHv+\nqzQVAKQ0+UOmw3T+29c4atCHzi2+uB2N0pr3kiOHQ8yooLRMdkn24q9cxynSkIZo1/dARHNNdxa3\nCJv1zraDIX2a9McxBdYXYYPeFRe//3X0Icj+fafoR1L6ZnzJ8pkqjZSGr7s9acLQGxabvRMGFAlH\nVSEB3Y7eWvxapneBKniIGGujM8MXaz15lv9RmTiEqxfRsxRhgthrhqNWOlGWfz21p8uZT/iV0h9Y\nfzfelebsnPN2uqnYGEKFTYTm43VLTKdViucgm0FyCsC5i7j0MIw20+J+3xPhA7x4++Bg0WIc2oa6\nyZWBWrw09oorWa4VXS9O4jd/qCs1lXQO9qyI4RaWmg1w/2nMaDgx3InEckVMCboMIeiaxntF0Oan\nPBiBdb1PPzTtsMmzVNpv4Fjv/cOEPRIRFPibNg3qhLCCRI7H9mgzfUzv90GEsJjMVTCAhWsuuHo9\nwGzpvadtd3ZPmPsOFa01NwPTRw0Ka+zQf07NZ5o1vtUsD8QeGQdLQQ/Q5OKw2HbA/bmpERHgtPaO\nU2pjfnadcng5L589GtL1Yn1o8CLSPo3GBOJXJ+EEsGHxmSytk2TceD72Fzn1at8SRZcjtsb4Puy5\nD6IOS7UeaGPeKQA6l11RgJHgfZbUgaJmK6tPYXZqXja2NBHNAlJGUGSUdtTyFwrSw1v9Kvbta3nm\n9dSQggcFLN0jfOh4Wx4PkZqrNAn4aYXAl1hVDrYSJYeIi/g9UWvt4lKEKzII7sSP+/Smvc+DQI7c\nKrUPoBrCwwSIULOWIvTrmc/9H9lyRuvvalVYoO1UJ4h1QZ8l8Awyua3XBfn+LhsE5y8En3VMKVBK\nHDDhGXOo1ly3kQ8NfiYxpwcHcNdNtrv6maO8YQ5GRGqef7AdwOaB88p4d8Lo4SDu62Dzf2fkdySN\nvx+zps0lGn2ew4IFCknQaUtUaHVrSDUG/NZZQabVDl4WAdblcpbCOW8uTiNoFIKFX8dP4RYXgq+N\n0wODhInglAFqObFfIC84RBfDlEA6t/45rPMvS12+uDunWBSZHyVY1Uwvwu/pnI48lV9m61OsJCLO\nOIgrpGewilIwhStXkjxdI/PB+Vez075WfTee96epvw8Gy7kPD7RFvqrDDIrSGm93FKnRHplTj8O5\n5uu+yfmzGBWYcqCbo4mJK6V0M/SJnB1HCGbgLiRxGy/WnHWjaYx9bBqMbBHImuGlpEzPmfDKvgV7\nAlHvpdpzcBlf2iAEr4jhpXqh/KwnRQ4vJL1P84YbChWf4s+IKE0AZ6f0vl7phKgUVq+P+ULvZdoT\nqnWO0Ig8FCSr/a6sZumTd2V59t1HdZTvc9V7LHv7XW1ar8fwPredD5AYEDMepb6AgFxec1FiOc3D\nykbfBhIXJE6n+Yn+BkBfyPaHQtr6CygbQYqPxrWvwqNaGqiR4M1+SnXc1ZPUCuO3jpsqErNCpGur\n86gev9iN95nwRZl1czxWVa9z2Vups+DUDYNl6OGsA3VaU6eY+zfjdw22WdfBTQW1yLZbKdfPdglM\nk0W3fK6xVQmWd7Q0MFJx12rohylS2M3jRt6ymRYDuj9G2x7e5COQAH4HvGSj1xQao0Oqt1esrJ4a\nYIqOffOvsSJq932yvAK//wpl7jU/meranK6kL+SFodAzXhE5O9i3yUroUaSX5y59xIfZoFg4NHP0\nM7zEBF6QB2GW8onP2jBMjRx1c2YyjCZC9I2gxLVNFMuAynr8b5R66ZPqvrh/8y6Mqr83orbrcV1X\njrDazLR6yHEOtNQ4bi8mN7w1RxzLuL2h058RZGlSsTBsO8xP6HAr5Kp2wBfbvI57lK6CxqUspCj8\neO92O5CNgGOfYdotXRnXfVffA4XKFtgvw2Me/hq6OXRjQJn4ru2BJA8kDP43xdNfLhkeKIZM3AoG\nTcMCW6giOWLiADsnkr2ofGgeUFbW+ngIOyctXvMwRFMD+1K5RpwKmd9uVYsHK5u+PLBnvBGoyoS7\n8/m4+m5zQh1ucW8F1QfRwl/sKSrRq0ciF10lQ6zYZB4lLAem6FOmUFaoyuBVPiQdDA1ZsbW/Oy9h\nCVMHPZwPrJ3UnrPvs6YOfXs2Jlfc4nyTMV9gez2SwA0MbPHMnpIcvsBYMqVf1NbZumEG5UI4mVji\nsP+Lo3Q+cV56vHImYilS916X7mZ0gHna6WTTGV9UyJ+Du3k0Tl5TlYLHL/ob4uKWbj822Gt7tv23\nAJnMLGCkgZQbYYRLwv5C7jFKxzPsaYrdBbnhN8Hzj8uWglOv5NmXOcg2pNyIv6Xp7o3P4/taZy/s\nbavizNn1qFu+wczAKyYeOCD1GOD150qXMwDfJGIaD722D5IfvLbBJkBz14/nzS42fO+i/NSflxqQ\nIh8W1dHgXZR1+1xGFhfpNgJ73eVqPltXA5/xNtE6EWKAK2h01+j9T0mPP+TCq80DejbANcjNu+ug\nQ7qp1/IN1oZBnRQf0DNejhOdZ3Ik88Xhwy2Bn0jLmvR81NTNbmVEoZf6/LBhkmC++d5tWUODaE3V\nMmjV73rV8eAB0kRkj3yGu5GLwWEtbau6TqRGb0BcVzUlzqvF5MPetFqKTBQY6sJENoTXq1XQjWm6\n9wH63KFczwcmFRWNgBpkvjQZUGWcCIlioS4fuoQg+RfiCszpQm6etlOglZq6tbo35s7iHLifH2fJ\nXgBvGhw1Mzh5WLkhF0SZtXs1flSvmLCyJM6MwWBe9Vg1rncHvsaqt33+9kknBEsl8yJuvLzpWHIq\nIOyjgBz9NEl5RNUhBXzOzvIRK9F3Z+fejM0uOy+z5JQfMyUHKAEhEtGivvnuKn5Iv1yGYQbKcWzf\nrLxAQP1WA+5zJeTLRbU+kco9GYRaVaIvruvNy1wYXHcRnwEui9exP//Ej02tNULykhUHv7P7iTnf\nYCwad9m+QexSnt0Sf+x7TTYZGucEUC7Y4EDC2m9MsTtXFuhHgin2e9eHMTm7cMiFUf3O8h8Qszop\nwzWvIQZOkkv91HzJT8h4L2b0+s0LMTK978OOGCGHEcqUPGyAWN7nOu16o2UjvQGFPn79rD1sub3W\nU+zCmNvAttFgu659SJhYDXnvhUoNWhfY6acclg3KD38v/SOAfl/eq+85NRYWvJtweiJRYYtk0vVs\nu6EitsHfSy055na+HIelCMTPbv3+3OwB8KNeJGveU0qxSv4okxF8YWWxztNlTRVWwx6fC7LrHTJS\nXhjvKRWBJrdBkAn903FdNO406+gwfbMP6VAaTCMo2gsunicIpS8xTA9jcMdcnCyP4GXLvQi4UckD\nQNgqbWYvw5fxTLOWyf1Qu4u6Ul1cRBRNRqZ3sZG1iD58EIMSS69VEvYM1w5CWdFFkYZesNsF2ZAC\n4RTSQLixyOWbPHcCckgl3/E4FZCkIi1A0xsbsyirad4r4OdBa4ELnPi0ASWPuCJZp8QxIx9ohBTU\ncXKA+rgTrCgCLzavqrmNtp3Gr4WW1sfls95t68GeO6SScz+13sR+D3gkP998Q+3+9ENk5i7fJ9/i\nQcLd8GqnDZaJ/h36F7+cUQZg67jcA5APE29UEhwTU72sbZWGcGykxoFo6Wu8gG9xLNC2pPVSdS6a\nF55fpU0b9k7eoRIM9wJyDoF5jVRrL+wNULRlvZpfiLOpSwjUKnZ6ljjKtTt6qfsye31ZSpQbTEDi\nei67gpANY9oE+l8zI+oIf8eBQod4TXK0aotrRsx0T048+WvCuIiR+iczHejTE8Pdi8+enWorNp6u\nCcR1yfG23NU1xEPqbMjQdnMIw2T7xx8WBpnaS+nBJ1gNENmT+JS56BNxD6xy5OvTLAQXjtm+KiG5\ncnsBBCY/Am/rByb+pNGepykPoma6lXmXc5FMpKsySFKxXx7y5zorfRE9gSbCmTG5Ltvw4142R91i\n812qH7JQQPaumVCKm33BGCVGuitsJfOfv/98p8oQPsV6SftmQusOjQSyn5Qm+dlpy2+VymZDEnTc\neJlGz99qQGTvq8/CnYHNoTodEyCv3uGGGoA0TqUo53dr7ssSRbAFgdsyRHMDxepGAcjkw7T6laTd\nqtTg6VF8hWTkI7MN6+pMfl4m1JUI3jCTvL3r/vgV6Kz3ppGiAoXiSzxy4keXJ6PAPwFmbGMVtZay\nWyEhiliGvUyzaYlZPptWWhQOtNFU7fxXPiYE32GVZIx+SiWJLnWydxbRC/WlhwgNYcGsyqSZMFit\nsNGCmXGtYx50tvzGxQwzehYg0nZ2T3/PJDCx29bJ47EO9lmaIUUPuHUmene0vI1Pu3WArggyDcZm\nv2T2/rnn/OkCTuK9/cnfLCkG9PZvw+b6Q8iqL81fUCaMHPspDM/w/iL0pGUM68CLdUwOhsuz9jrD\nADfcq+EHTkeSm1tRfg+5QtFa4PgsUd1tA9j3+oO8OS4wuERtXT8tItcS8PjZuyin4U0+G5ec8xRq\nNXig33Ho45rUFp/dzkeNN1A0r9jrBnzIxzHAQZgfdTuGWuttmgbHPe/8AhXQ1iFepoTAzqrCqBln\ndNdMPtSzeK2ZoMaHjCWqZs+s8/+1seQjregjKaPbNxtmkplWus0EExT+udkoO7IXvlQq7BgPYo4r\nRpjeAfQC8Li0QA1OIq++poHELmQg9Sv753ldrgUe7HlrntwA8pnVfa3P2xWCC5ti+tEdtMl2Z3R5\nahgZisYsB8c1LNpju99Cd5thHlHl4q8bD77qMmBldsN89OKNqPHdYrbQUxFuR0cSUly501EUip2r\nJwNftGERUEMKhO82u2cZQzDhz17Ttkor/7NeO+Z+DrmO2e4BlNdtNXxiWIprq5n7njgKw0+Y31Z9\no5bBl4zCMvNHlQ/IuBUEEIcDEP1SH8hlHzzCrOoA3/6P17v4Px9APMiiv33ExsXH8T1i0iteJS07\nzLASBPvauUC9xNjitpan8V2eHxBVPDkLlNHX8+hobBnp5vRMSQcBO0JFm33M2lSRBE9ZNcgYf+g3\nkB2CVDaFyDLLvhVdXW034NGCc2deKjNDfZrSkVEFJH0aDJoEYzxeEnMh9d5rIKx3VYmcYHgw6JGg\nJBhUkNHmCjfh0vCo+hjMCPwH95m3vUFe1wKhOoXsIWyk1QJ+QTR9t+hZTowkYlQprcv5t2gWHJYG\nys6npKLa+KanvsrGVrXB32uysIZliELY0rvCu1lnLfOVG5o6VxHS66qJPHimhiy6XX4IgXd6zZiW\nYO7BOZluVxA1fF+ajFTsjY32A70kD/tRSPQpYwH9EMaoF76kkDLhsIobb2kYNomgtk7M503onnCd\nu64Y7Grs+FvIkcG6rJ/SZUqfoPbCZmvMJtxhS3d9eDphfgzSyg0uEcbc30Scvx3MW/Ka45FcPqWU\nTTJuaFa5sYSLgrtp0/xa2z1ZrvplfUMOfs1Ir4WbJ9S9rWOTG+MOlyxRJVANozxhNnL+p0UxBvIK\nFUnFSYxOeTffvL/9AiuwYKEGlG8TP4W0kgfeL3hMAL5gpcXggAW/2zDLba/syJhMD6Tp62ZpzZTH\nz/IPQv4NIEnBLbQy6BH4d0wGaSLfPyXvaUjY7YQ+ntuC31nihw1bQwaZ+MUWyZRcmiX5r9u7+XdL\nI1L1yZBLfdvFM+nIfXra/bYYxC99jIKFf7pNPlxoLNMW5ArXRg/FY+4oEjkoCU5VQUgZUNAuJNxU\nkjCdWYT/MrC1tV8BTjT8vgZqsUVG+9Q9BiJFhhAhyxYKch4SAtURNyGrLtp0SSnIYJ3B/ZVjzn7I\nxuxZZ2v2AflGdJfcDL+Rr6aLQdbjGj/+0zoSVfLZv4JbXBQwhr85A0tkeg6cGcxR9Vza/zc7+M6g\nJ5ccWZqPWubJGmJvKwm8cnMa+pcVTxa27WsCDyvS0Y68jalHosyqevLvcB3xDPTsn2uHlV+VpQcj\nV0VFxSXFpQmg8i91a+zS4L7xHHbrjcRUly+muThjtgw6ig/wF5IxtSpj5x7igdPnhA36Go4s6ycI\nIiK57NlcBNfiebdpAbi/w5sM+taV1uXqviHauEuFjtQA33Ok8ch86BdmtrhnfMrEJ8rHapBXrVht\nIdcFv0tQUfg2nx+8xWmAW0dbKjOV9EeqQp0I4g9LeZD5GoAP9n3P9uxbxza4GAUXxvg8YQn638cD\npJ08vWFIXQz+R7QyyTo9sX+L/8OhlUe57VaGzoGGHeg2RfhPUXKQ5g4vkHkUQq05nbCCuLIsc/NF\nA9VSgYsetAZd8ab3oI/3nSeVQn9BqI6eeK76MN9q/uGinlJrJwDKg2lAwE4Sx1NtxZUDL5Qng1z2\n+lwVJzNItzXwfBtFu0TCpNDRouYbIY10OgzqrgN8p1Iw4yC4fdfmvvoeJBaWzueEUdTT0lR9CbXg\nnCIcYnStmgLfad7bKNKuZF0N2BdtTyt02DP4LzxwMUX9zaxXo2s/7FBfFcU3FJuvYBvJNxclo8rd\nK99uOpDhoAF68Cp8f3U1xGQs9hcQFsIiZxeJK3ILBP5gp+CyPPneqHwgN07Z3h+9wvOFgwV7PuNs\nihcq9INZE5hivSIUv1J4uqxZxw2YOvj+4XtgILMDsLBUh2/CeiJHDnRXHHXa8xyHN/VEZlvP995w\nphboRlruPD5mR/ocPYK7UdxRiSWJM3aJzUcLRi955umxUm0bw6N0pSJ7JahT+I2XC34PwpktoFJK\ncnszLXBWbxz29fPMUkVIgrJLImaca+mZQRabAzDdtkZVBJfpiL95/WLyAlyEFqHx6pOn9YdqK/x8\nls+aAzMGETkfnoOlM6je/dTzj3l6Qegyttg6hacm7+dwNcr5RLP10+lmLI47KpEZMRH0JtDps/ey\nRtCY/uN6O1UaJdOhdtyZCpou6ZZrao39nAAK3hsYPS++aZgjVAM+j0HZPfDxzqTE4Wp2AHE0vEVb\nsbWOC5JkhFUEsNgxf3CZZek4tylhZBFe2qAPmca7Nr8cX+/fGwJa4zsstW1RSHzzXp+ga7T04RRj\nqKwX8lhMp83DKrFARIncMkCPhC9OchoFv6Gq/qOjB5ENUspxDy4S/IOsNdRpKsjsoA/E6+aiSeQp\n3DWa071ADqC3V/jEDFQxKj++OP+/pINq6Y1craLIugETiEcpuMZtIfeNmTtUQ9bQlnnIHSMgiiLk\nEYO/fwfSTz7trn+YBvKL5vAPEgd8EXnJTQmYglGi3iPtfYZCecyOfq3JykNYoLGzlc8l+lgHht6D\njBryf+zujUdATobQ6vmyUQSCtmPgv044olqWdpLhzoc9ASuMzv1Tf60b+vX3nQLZbSJuYh7SHxUc\nGxaQJbaAUNbtxB873Z2xQaexfwD0XIgmIrV4nTsGA8CKeZGD44WmVGfF2zAEj0Suw90pvxZ6ak52\npnNXRoiYA1GbUbaAPifn9es5nNMox1WMhiiFqkfTt6QT/LPDaI6pctEEKbhZABvzuC+AFV6ApkFQ\n9sEbC67oJqc2L/F5+EIi5bC2E4TuVw5PGllkgLBAmBS9ZJXLt8W/7AZzh2zXOiztarPYrGxcQWQi\n1NqD9kbqMfjq4GgxdfOh6GXp+/8hzguNrB0XOLT57jqu3ukdyPI/38f/tdSR8rVLm9ctklpFxIp1\natcGe6ZzLhkmrAWaEgXu+rkvalDeJJzYMCdssUggP9sbyIBqNm+bu0hs27axwtzO0aLTdEmRy7BX\n02mW+0eM4axPDPBXp7Km1zDETT9OuwhMcrmk9IDiDrbaUj5u9Is6RN5ZNoT9chv4XZJKvLR2ut3e\nQGCvbdUAVHxPLCOslYfGfXiNFdwL9ygx5Xv94ULNBynBX65Yc0v5uokgRUlQFr4KxsdMcxhnJrjd\n5mKOOdcKDyXcYKKk1YrFmxp2Mqa1iRK0gm7BoGrH6dy8ZY4obArr8X7BYzzkf4oUx8I+5e2BLyig\nSCmP33zMkZFpk/Auh1rgfxz/PbMciaPSHZvrsiCsT3mIopE+JgltnrrCcjK7GAdB5hrTS3w3SR1y\nGBavVYxjiEqnr8WlVGP5HbH08fIsOBlMX7LO5sciII0cGlRpn364mCbdp91BslmVrQoxcPaj+TC9\nO0MZi9C8aOZsUVk7GGBEye2EQ6zuEpA0PE6X2sUd4HqfaTrtQg1EivraNouAMLztKnLgN7pU/ETf\nK4iMYGGJzip/SjpXL4XIr62c0IMMYJzIXHBaTyrZ4idSxkM6S6Q/VUPOjO00HKdaRqOIH4Fl7siD\nQGdPpuIRj0b31W/7wIswcFZmCuzoZQGgj7b7P4nLZ1ugw4MHnHQ0p0zWM+A+R01iDJDTBdfEPSsz\ntVdGAoTuJ+O5nYpHMc+IAOA29tvUF0hLHKvwz719ElO2436olcY+xVc88CWad1ptcp6aodqcFyUM\nOlHeSnAgLnQRB4lEfJKprHEnN1TrjL67oHO/cABupwcFGBhTJebJn1u/nizRAVf+CKSUryUX1plf\nq1Wg9A52pO4nv4UPs5j2/i4PgDiSZY8dZu2YgE043PYJ5dEjNrmyvjaWkjFwtziqqKJ/zAwzxSfY\nFx5VOVen0XsXcoLpFHKH06Nbml4lnpDAxCdCAQlBhJagIUqVZUEIMzzBgaOUj7Y0E/Sx/MU06AAm\nb+hjKhJ4ht+9FDe3q31ngEpHms3C2CB73sGjLP85VrkgocaNNOGwWb85+dtp6SbR1oOXKGSgDIuW\nWa9nFDdb80zA/9MYuiTLZB0pGf2ysznBH4gVaJ86M27pJbE/oidnAlTQUPvFB38TOYQNTSnCNbmC\nBY/7Vz2hDC+A4DHGgWSJ/wWGblIidbsZpgHg1Xo8ekbgWacICP4eJRnFY0h99QUPrb9rr7nSKoVD\n4fgt/CUrqX9nvnFnEEI8eiWD+oHVrQKGRK6TnOP/839TpPTKpwfa5Qlp8j3ABCliKMAkPP6HOX+K\ndwjGgNzWtsIMFH+5fIx94smDLYyUxaUiQLsy44s+y54eVCf5XtKV7oMkEfvPoBAXlmhHKys2EraD\nKquLZQqsoRYc87pUW7KZ+/FGw76fQKeccRJfucdYfj2hHBcIaBuJUIPKrC592N7/WwEBhSd8nLa1\nLZKRMwzDGxXGYlmDMwf56Zf6OgqrCqSI/SnvV5mzligO5Au0AT5y8UGRR9x2hTLAohR3HhVudEXO\nowk0UJg8YDcoxxu0VpwoNbMLIcaEY1pemBsAdLqJhGMTRnneNxKrTtSgUwFN30HpP1fHg8FLhkHd\nFEhXXm6zT2mMHNhNgq8nbsHlIZj6lPdOCqJht4xkSQhmq+b4kwFjsVIOsR+y6Mo+C1vtZM89MyCi\n6SWt8fabXIQhJg+XGRqdh6vVWl5/YYso5T332zDvVQTlJAIu30bYPbZTre/xqhs/eG5/01Gy6nQd\nsONvdiK5TjgFj1gAUliaaUHi3VsgkrNExifz+rXAoecbj8lpEh36t3rEyvXjjGsAl6nV1UgQiCOU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mjmT3stzC/Xv3U+2KUtVN3IyoZysXfApjzYPxRGoY14wxVxml3cjWkid8wTZt/\nqKiZ8+DNGhOWsKqtYFfzvK3ApRuFrMQI4nmfP0ioaEsTGAw0TGjMc/edUC/KrxwpP9WbWlpcR1Mn\nyRmHmO1G980fLf1P/q5GKog5mVjHFI3YGEOry1qcHAJR2dzO40KJ0/5N3/Pxa7i6wNIJh/mHzFZ+\n31kRMiX98q/i5AnwSm6CIHRH2WptfuJJu8bOdHyEc2X/ZykVW5x17fso5tTlUjx5p+HR96FFUaBH\nlCZQUHaHREVDgLoo37xNLUuVkMHZqp9r/Bd63iatA1vtI53HEnJpU6AsMLIsCdkY+Lf82Feavy1/\nXEAxqjo7H1QoA9YuFHqbS5WP7hI7NfNQMDjoqprgcz9/UB7xC5WYr8rq2d5mgeAbnstt5tE7sQm6\nQgLlHockY4CJK8Xvmv4d4SblYXDAds1reKTgyhuI4ZtI4IEsIdiA6/FCJ2Vtw+GFFB0zIWutZ9Qg\nvRS3DxbGOPG7mDhBr7DndSkrx0aocMGbybimWSBSg54OO8poGqinGYfYKzIcnpmV8De9rNUYTd70\nICpozYFwIfHD6uW/tcf8vX5K9TD61i5pXIBimaenR5BI2PMYIhZxYqmWN5m2C4lpq7eUVSFU6cJU\nDopA56H0YzS1Yghkaz6ccapw4+IWSfmbW+U+xxGGT3wNd/C0LkyFKJzdCEZLxeZWC2Om6YAKNHn+\niFQ0gxa5wWQPwuJ8ZhYyqSk/q1Ta/GqqRzNbWLlZC4xztgz3JY1yx0g4gGXDKlO705YMD2H1sVzh\ny8FE+koC6h6l4i41cL/DFsmJm5Jqj52bd3iigktOLK6QtleXtA6WLojTYOnJOguFYPtthxaSvmGm\nqQTuLmCdlOWgPxQizNJRMRBTiuN87BktKycizvXRwigxNRv5V2btiXkJPtyPyqkLA4WN6rCMZBko\niXN3m7e9ovTge7aNZ42IWrAY75oe3jrfzduFMjJB7BHwVaV1dNpZqNe+ZP4gzGhO6yKU6gUhhLjo\nhuML+408orbEV4f3IS8O1PfQ+c9afO72/Ivqt12Iq1YNG3EKdwt+NulV+j6oevJWc1U/vV8MrQa0\nbeVkn5LMWMAilgmbX61R6wISQo0NfBGdFL7yL76BwJ5wauMZ3beZYu5smvlVxpEwVhQ8fFxH5Xpo\noihRZCSnp0L/BG8e+f6/sZJ3g939OWCjOd7v+b1g7lOXhRH12gLTb/5yvbYNu6R73tarKDzA+EDC\nV6Cjc0uuB1aWJB/N+OrNOcVXKhZcotiTMF4vDqfRNuqt4Lr8gjOQdRbrQEveoS5Z3dGPAUi07lqg\nqVZaKQNTSVTGNdFooKDV6jxrbpDI7VfHYQeRlcfaGQ1FG1NFjzlHBtwZAFGM65hXUyuLRvTsfmyJ\nKoaS6UFC1MuuQS/l45/VFm1tfQmlNWunhV0kpPrB8jg4HzKBk9f2BfqoHchtOGcUKTenprkzbPfn\nw4lemz9G4I8Lj5ly28uFVHheaCmKS4+8HGNam+xtZvyfd5dpBY8AcoNMtHr6i4UmfWaURIdijXdH\n4Bmll6uW4Pbk+DGTBh4mPSh2on/JXHVKOI+tXmcYauiEje985N91S+0Na3tbw+coqe0WLnAcRjrm\nq0HRhBFaPvHkoNwuQKN20uBjwavtz72na95RG+VD89klPSBmoG9U09U91P6sJ18GtlDxXCP0UAvS\nYwS5AWhwvu1ZBenlPuvRWL5SCxKd60mnVbKgePL10ztCgNJWKHL/tYG5erl6R7VpWRMeuAsivG4L\nvlZh1VMUk7WcEFtlQ8ewoghZgp/iUiIGdB8UYFsMC2n0jF2KlbD0qxkuacheyV42MhjTNrWOGJpP\nb8cLqovTnWaUaEQR4ox7qhg+i7lW7pFMSIP9k6dZSVrywanuiKxyZEM8txnRmifM5BWdVlFe7o4Q\n6LDdZw4TPzfPC/79pncGr4kcfXBeItIkCz2Kb37YPXMbPvCbBJ3buirX4xlN4U9Fzi5U0OI8rI/m\nxEaubhXYIo1C1wVEbMmhjjAYqm9mdtqwtK34nKt6UA8yzfBAKUcRS9C7ComgLKAnsqqYmQ6+d9du\nQEqBOA+dGyP5ei6S8XQuTmoeHBEzJtkaDcSReujBlwUYKT5jEDk0nET2T3W05RN8O+I1iuCL2zEk\nCBa9XojaCW7WnyD9fHIfIlVP3k5fyrMDshYPSJRoF+L3za8tcsFxoTB29Q6BjKAxZ/R2U7piuOIo\n3MRAXcIwBS55HqoJGM2SsAP+FtMEdbi9rvWNynjnYLT3VWrn9y4dpa1PzuBknAAIADZ1iJy8w45l\nKMoZndthreWqtx5WJ/NDeCbjKlRUXo+VcTOw5wfPGjtROIJrk+a0pBEvk9IgkLPXS67zcTg3SmX6\nqQGKLp8Q4wEM9wWWnL2h6O0wifvd8KNCNPziDdUS1b31LePR/mZo4s8QhVTskrjHFAb4QUbPl7a6\nHLudISZ7yV3Gmp6lxCIVCJYIiPkLiVfwQRSQViwIUWt6BCc960d/MqoOz0fwpsTkdjYr+EqA4FGJ\nwxJLPlTgl2lMVKdWumgkU6nREoX2fmCnx53Jl2LcDzdxTiKv4g72G/QzytkzP/3csANiNniXJKyb\nyPEYM+lewTjlwyBrvA1Hseq0rwEyuZIohPauQrtMD/CqgPghUCPc1zEUWqtbD7Cs6Wa9Q6i9cZe6\noygam6u4DqOHve4zENyA4vn6BeFcxUULrbhaf00LyIK8JhVfO3PgfxROzcPGkUTDn9lNMcgSYFw1\nF5h0O+k4KTZAuh5WmzhA07pUadrHIEWS84zpb597LkMmlP/Ir2b5DSd3a9WrRzXtffoW6wj+dqC7\npakKeVaDaFLsKew4NQn/5Gv2SSsl4XFUnLgN38g3e2L47gMZVmWlB+Y2pxNwsAyXV5zrfZ66+6NO\n/atnQFy39BdJa/QlM1kXvILZzqUOXKGZVYZLaTWJEug9PUV3sxznlaY+cyInU/Zyp4GnlbQ0XVJM\njjTgTXNLU2xwchHYZ2fBegrJgvIFGdryBZ0iiPdHvP0oKTrobiiLLzbV6OGhFV17NAM1UtiiGvmX\nCecPeJZhMWSNd1sR0zXBMsmK0TzQz9wCoe+6xVsyVVjA7V2FOPwHS/UUbVQY48xEuz3BqvoRTDza\n/Upe/JHbXSk9IhwLJhuQT51Ra6cPMWmXfgxXBAUVwMzzMx5nf38uLxEbI8HuxHJNoAr5GGRdDbDM\nvIaZdGD58IBnjKY6oHp0HRYu4WKaLDRblLUdGdvRRYTa8gDWhSNjXPohCsckVTdJP+6e2e4QOj4j\nERJFaK63X5h0QsmZOgpBr0rJwPTHnVY6GB3YKBw354eubQ9K7LofK66j6q3zT4Guf8RJUbdEAwPX\nO76Nk2K/YZetp9kO7l+c5cAIr8TwXPfl9w6+CZ8CwysJcd4GCwCkfBAE6qXqEVKayXnkzL+/gi9q\nYhodZUcg9N6TE/MQblA4jb3J2ttB1IdT6RQqaipYfiglppdRbRW1Qij7hpryOT2LWAgda1QDnOCw\nN/aRmOHe3cYkOP7spl87Ts3hk7E2Ax/UCeVxagIHpfy+FrsHZ4qiX+k649T/cfEl5rBbvmxA/xiL\nCwG9iyKqxglcf46ESxutKiDbBbgTxm51oe53JUdUJ80WTQ9/VQIlCKHVZPeWam1by0CZhhQ+FHPz\niRM7iAkCLl0ad6jbmsTBDB4Yo3j9GzlRn4OwfvkX+1X6Br/jpb7Ods5R9sYdCU8iirwHrrDeyl4P\n5Oa3TjRfEeRc/j9P7DyMx3ksTLodItG9x/vZWgOy4iFOa215lI7+X25rZS1Ummp/5i+Xpg/2bqL1\nYc6h7fbQjdpHUXjn4QUz0LYvmc+BNdDxx7TgSkeXOeHhdOTNPZBaDLDk2cy+lw8H7HLME+RVBt1k\nsXgcUBHjvvnpcteXo3EY/4mNbR/ZqLeXimXlWhSbjhCGYDzmqa5rgtz3n/CYymQhxCskPAQGw+sz\nezc1Bd1Gs8eiRp5AYUfgRpr4jbtwjt6z++6Vu8p97biVpBs1ExN2/VFrFqgpOJw9uA6QDmVZnx8t\ntsVnG09ksxL5q7LXryPT74zfhepy7+7aTH5YUpDpb2waeTIFvBdg8gmxXZB2ZJNSvEFEPglZ4KhP\ns5Wo15NcuLVfQySWiiEeFOZVqadoOuNZDghUEifrUf+33tFg6SeVx+zBDJbH89YDSGPONwYA8KZ1\nllfpAVGLBseobFKvocGgdqQf5YsUQQL2aNanPQqWDHJHr30u4IJBVKuluk8tjx90eD5z0fjoCqq3\nJds3DQnYjrQ7BU2xCixiaN26VICrnw47sIinfFcVXPidugt7ZC/KdJ/aQIVQbkrgDLjDxprUS7W1\nFffseESv5PsMOXQPCsFvlKPUCAAM4JKznpl/d5fx73jhcyMXizSXCoL3+8p/2BFB2u1ZYbisTH6V\nHLzAnIYsfS7eDvpwedtN7UZnmo/srjqJdMDTnCXrvGjHEr7252l6Ipuygr6C+WLPMQU9rrfvIwyN\n7t6vCh04Uqaszzc5CY9Aglhmwt/2Y5fx9JkGZumJynrdGXP33p2621iPJ4AevXZ3fdpNsCsmXnzc\n03cELWhMybwOw1YYoFbfYaz0s7PGleQIeLnk/884jAZTBzjHWSoLCwehSZqGTEAap+F/qiwHr9if\nuKfdQfIf1sOFlHlFnmEytGa24c0rloKQYqZPkuEVY7dS+SDs3W/Bcfs8x0goY2jaXFj4ZMP5UuTc\nyYDHI66HFcvlFknDksj2QlDgRfqZvhK4nKn/ov1YLKpHRhjo71lyHjJm2VbSQ+0OKQv8nqczLIpC\n2mynrP+VJILPijymLq5vCPGo6QllgLdqvuNKBIsJJrlMhIMyMmnRNJvVS+sTiwwsxinybxQicOf4\n34R6e7oY72ItEWWzrwJMtmMMcQrNBoRVgZsDnDu3B/iLN9B445+Ia/2xI8tg4h4bWVtfUrPF/GHF\nCCMcBaai/7iqersKU25P9YqCrW5gzK4yd6hHRVmP/GReTSC8etOcS/dQ+iH7YAw6g+VqwGCE9NNq\nrDHzSFNHzcuTFPuPTnjdDyBuk8tgZ2P8L+upWmAB8WRT08N0FYWxRVHTgdWwIb++kpR4oah3SMVh\ncMdDNeDMRXWOPYx+eoBFG4TdDky/+Rpt3Y3t+kXs5rBtuM3mN6lO/N62N0YIWBy9PPROt6ABLhjn\nkTSPxHFYPlq+2tW7Yq6PpB3gOJgIpw6Jd2FVY/nnHFVGLeti1SuPxoqA/zB+RqAZ1ugF1/HuD/no\nlOzP6btVSLptufMfKGXQlqJurAbPNswzU1SgOzKKgJWsBc8A1dZhUmmODZr7QJWHHjXRe7yJioTB\nSe+1t1P79UExlkY2Av53wBpm/Qf4fP4wQc1SW3DW0IMbQtjt9uv9/X9fGV6/G4GCcNq3idyucymc\n5DsqZ30iU7nUPo5TDk2xTfYTo5J6KDFbWg68PBTUjc9YU+xUqFwxcpfCVXhHxosuzfUSnP6d8DrK\n3sQNP4khBnas9LtuKIEewVH1iv2IiKUdT79XbsL/vFcNBq0+Sqvvg8Mk/IozOebCZTqLA+pRh8j1\nPO0dg1EYBx38k9kKMWWaaucDeaXpyGKEurCt+rNNj6O3iZ4CRZX9o1/noytgel7upuLBzZqGwGps\n73AtMGLpnD77WEcHmk7vCb/9ZIQ/1JqILIS7tWQrpz13TnS0vYnHyN54RndRSVrH3tV5/OmRT8Vr\n86wb6pLSlRI3+LytODQtXr5Pjm9zRxy6ohZ3KULiJ++p02B77O1XtFtNs3jRNxHwmT1DpOf+e3YF\n7zwucJ1nuZyIc7dAzGodikj09oxWDfGZLpGvUv8slbHALDP09Q1sZYzbZb1WMxARlYmMMbOMv6bp\nqXEGb6OxN9Z+GzBYi3Txjse2FDv2HMAimBoCXDRXlk+yVpwUiCn5LTOOrLgekPXApsjOz7wN1iAF\nuPCOno030qg47WpIfuuAkwTBNanyjM9t9kGvHBUbYvNGJkbeRm8WiEhVGVnfSDbFg1e8sBlL0Lu3\naMpK5PBpegs+vk8K2IkOGYvR5Aow1ZeA5q1rcMpEdIMR3mvYVfmtKdsviHZ0E9byAXZKlxdLV500\nemm5GQ0btI6qUDeat0/afCtAal+KQNfrpHPt/BKEshvW65onuKtkGdVhgINJh2YjRt6jDRwNZQy0\nt2/zk33lRdcQQQ8LBhOyDN4ulcQycDTY8OirqCVBDoNZ+9yHallJ2KKSJ36/U8NF0hahr7y5qtSM\nA/CkX1Sq/WW9AUQghL6/flbo6xyPz6Bk2CrrAkVR1m8WMsMYMTJzDzfobDkq/uOLuUcYSHS8GNM6\nIdJqSHQHu56KgPK0O/DnWxNXJkyeBTmFrEEAeToW3FoLlXfLwtvWmC06ciSqRnbm4gQimtKLA186\n3MaT356eSiGNv5qN+OQ8jv9hOKg17JmP9W2QWQxotOSiN3CpHK96mnBgBkpBqeksHSwkZ0Ym0Qlr\nWv4lGLAVFUI/rN/rGeRGjup/z4iwy542LcR9kEYZOCDY7F+46FcaQVcgrEM3BbZM1pZ7vMLZbBAB\nNIp2+fxvCHdPb2MYCkQJEi/lNoxzKSXQtUF/XliVdGDd/gJwms8Xkb0HYbyyJaWmfe/7DA0SWmmI\n5fHk2ePB/BvngIkwjKN6KMMHlozyCxLMBeUviR479mhHY3qV5gjKRE18cK3t6WtqD1l/r8fKmf2w\nmzxkLYc44rJqGUZqz2o47L0QXKUl4KpIGJ/PgoMPvA1kf0RdRqeBduHyjVFsKxHnVpN5TcWOPpEw\nsnzFSf8uh2B3xmR8tN3FtBy76kvQdN+6jOgMRDMtqYF7sGVg9vWPkeNNYzWk3rNC82l1Zzzx1ztQ\nJPblX9T7Eopb8dQclIpQtlVlyIvKm//abXhCgGVhBiQO4HX0Mien3FDZ990Z+ACbN0ccUL4Q1a8i\nxBtv+PWgZCeEA7utiTzOAPee3+34gAm6naicmXjXFCr2YvuZ5nD8J4hTINSaASRF8YaSrvYywwTy\n0iiBeMiahZnjX6Ra2SrDx7v34srF6/hoMCA8DyH1mFmdEUrCRgE4t6Hi1YVAINEphDeCGVVAVZ2N\nPykajTZihGf35IIRqjlR4U376Y0tBRNDAGp0Q6kPtvejvKlrZKN4G7r1lJAyP09bE7KDPRmbs/fs\nNyVC8RFydYUivRE6veitQTKDOMDm6JNj7qAaWp77cujnVGbn64Bd4xm7WZeKIKIm4aYSnUwJl5hL\nD+LcQnpAu6AAfc5YHgN5y5HYw1yEUhRnMl/L5Bjz/LberH5kV5CAMGc35Dn5CCsgW62MH0Klur3t\nqvDQ3OvhGmDL4Y2xOoW4kBC/Rjs4GjGtRYrXT4e2tlpknnpaKlAKV1YKawJ0W5ajt598+Y5C55Xi\nFrK/U1x+yGGVlKNimaW2agOl9VuEcCh6glCflnLynYngd4XXKA2JKIVNlRW01Xgdtfi10B5ipXZS\nZVEoJ/hncNBjVQcHqAeGhnptqMCqfg7CcyShKr61kfcsAc5VLbEphtId0rpP5V0qOrtNJAKxoEaN\n0ppVGEAI9TOF73jTYNy5e79+kav+WYHx6AgbaL192QJxAqG6252UlyKD+TN3wBZoObX12Adr3vX0\nj8zGgO0he4Dx9Cc1zYRKQf+J+yMSyWdmVEp+MKCbgyK6LEYoIp17fcKhZNmAg+ZS36UfkshviFTK\n+POKT3AT1fvcHL8OYw/QdRPMaLWPsOWPzcq4yVgeUMUgiaSnDUCDUB2yCO1vrkhPMwKhlhn0LwuZ\nwfM3h+czZAHuZRighzjAJUXwkEsN1Pgt9F4Ga9v4FpSBRve37ucHHuEn5jrX7b93oBywaPyG4za/\nsKerqFfobeFqou+l5uZHAWu9PB7G/36xCuN+gmjhdwI/5TjKnJGVa/Y4mrJHsK6xloq5ez4C0iUi\nDmzKDqJoGdws5uiPusdI5CZWqgii+tJ8UWOIJHe9wGCyFsM8DcbrnffJ/viThaJpSCiPR0zFv6En\nui3LW356UdHeYjk/6ZLmILb75WrZlIL0kBuk74qo9+iFxkDdId6A9FExjyh5C0dP0BDu7B53lknF\nihlFcZBGxzYFi0FbzdfCEM2K3tcVp8899GthOJgGu1N/qgTjg7ZC/hyW+NBVWOcsA/YI7H3p0zgC\nXErEvovgf4PesV8V5YrcnbNOLDkF2F+Hf+2W32/JFOuPVvcNZ0gw633lx0jeGk6zfpU4S+UqC6Z5\nlv2D7EYFebe8OBLKCmRA2kE6MXcrMBmFn7B6+0q/HxIcCLbSLBhEYooIbwK4lBvBHwt3ZNID9S46\nrlt9jHIYAJJLaDmqvniX1DClRh9zTvsHpSGG3mOKpwD1pbAsE/8AMN715F7VM9sLDloqgirm14c6\n6KaiDL34h1u3UPQcAYa/iUBBFD/omsncOZqodQoWJn1t78iJvCBlDiE/KRD+shi7MBiWR2qJzUV6\nvszTfqHmcpXqEKqJvAXBiNAYngR+GmMYIbTgB1YEwXQCZD0LToUOiwp5anTrAhDmS/ZUfyPA3O6e\nTeDJzu+g6CkNKGT6qnI9zSYRkn59rzdWimTbmd31+E9sE3oldZ7yukJKGm9HcrjmEn5iIHN2ksfy\n/bkuKAzgYebyoHDYTZZ4VZqRJkKaocRo0fbIi3zd65Gp3s5K7YmVN1cvTb30eNMvckNTr5tRJMXB\nQ1bruBwB0ntnrr5x/IGxj/XRZ7/oSwIkJdyNApk2te/birUbUR6UnGc4y4ttNTCDEuqggW3Cbfx9\n9tQdOjLwh43tPYA8H/M++ZwOf3HhfJjQQKysv0lOWY4S7ARJ3OrEoqKqyXAWdXniajcpDVbynsa8\nNsjwPf5WL5HPa+3iczXjARgydFiLFoxXOvEHjL7tJu91ngVLoHuKCc1sVCOdlfYThGi23uWH7vJ0\nYOLKmVWobVhcf5VpB8+yu1Am0dOHkBdHCr3rrgZdInlMue8oop0PLaPmJVMowyGjsverdCv6z6UE\nOqIUWtaPVpiBpHHD9Yw6XYxDCAiGibe+Gl6m/28e8Ym+QSzsogPaSQBf0SelV7KrqzHbId7aPJEq\ngRCDJzmPbD1Avv3QgG3iKsbrPI2KxWvxVP0dALSOEGlaW1luiCFhyVQZMjhvB2qkJbqeiTDhS7h7\n3EUa4i+fV/sjeR56deRJoqqk3M2q5B2q8M8jiW3dXI4Bxnmf1g7J8vrQ+iXPrLgC2JkSbeRZ/eFF\nCnM7HWHG7fLPw+dEcoxCvhyjiLG4nrEVGBWGXhUmx7lCGjGBUwRSXgUKYTNM+tVB/GGQSLqO1BXa\nqonr6lyJ9aQG7gc66GT96wZBQGclYbR4btuwY1dBNSMp+euELOd1xEiLYTm8oFfu+4GyZNtxGaNH\nQPGRCGjL34JDEnum18YLX1sqaLAaI4Vd3oohNrCZpQUGEPboSGGh1OhTL0TcjUaI1kzx5pnFFlQW\num+7966tMQzGB0widT/dnC203OehdRUxF3mVKO3vyZQS/QQL0LhvmTW6F2yZftZZwGor4BAllquC\n557VhXbkeLpl/vbtt0chG5IT/u9C7bdHihJPK9UT4R88nM21DYUK11SdT+pomG5JH2mJc3Io3YzG\nZcfbv8KIZsybNllnnP/EBy1sp1maLL9qN6kF8hDFHfB/Jr2elZJJ01JYHPOQCHNy+UA2Gl5QwPr8\nc9SHuUtr8rz+WAOCvege7emLx4Jt5ytymFbSfrvoRM+ZUxFmqe62SfHTEzg7ml6FYKGwZFzHxAVP\nqClbYQVma1hfPRcOQ2EPNB+IDQvSMtnMgfNCRvCXzR+Q+46QsNEdqQLttQrMkLWYUWQ/PxH/abKm\naMyBEKhbB0uA37pA7d7nNWme6VWCZ7Phlw4sTGZ9usfSAF2iks+dhfHFUczhnkRr5kLs2nN//1Hm\nujL9S2Xh+YR8mZbK/X/DNNxk5vMeM2BEVm1PZoxk2SRTp2R/vYNolwEbwelAj06fIHNm5MpYsL1E\n7ncTpnND/46Rp+9dC46VWjFitJhw6xYQBnAnAUgK5XKJoMd1ULWbXo9Obn6RduRPzN0a789FLdcx\n4OyYK3f61tQF3inIYC1r1HHOGDrI2xRZVZNZNDzADjAcygRu1Sw4WL8VBi/vYsKqVoNERt38KOEl\n9NyG3q3+6TPPg72wauvsj9vXnxr/ERZ9FdkR/nhOatd9PJBBtPaEAMYvPNJ01ByAr1H9v7EusrNo\ndtHZtpRoWhrKsTvw8ChWSzj4E7jptyFhnLEslaw4KGbKc0rKYK/kNZB6DrrEl2aCV7QHsdkX9Bj1\nPKcOWqa37YQlp97WsyhXrowmbd3CistDmVeRnzDx4swr7Q6boEig1BCH+1d5aIEO9ffvu2QbMvti\nAbcrVFpP6sBalPmiLjS15uhWV8KEGw781zQ4mqnoVw3oCKOuwjvvK/9OhNoout6ggrrMMfHFLop/\n7TagcwxVB59eehfgXDHC5RxEwiKlLkX4TdQk3bJgWiNKjaUI0iF5sXdRTcu76owM9bPDeFQ0zvcK\ndUkPtD7AXtk/vFhKjwLRLeB3UTz+YhoVaUH1daPHUMlMEH+eJQESKAxgCeuJAj8GZnyT7+cw0TT7\ncjpaqS0H1C0WUL6EFh9/Re8yGO0a8+1Wp5GoD3ceJ9EingExgibnx1rZ3dLJ8Hmf4F6c97FHtUGj\nWWra/KN5WoCJrdl6TSdm2vPt/3JFImXL3VxVhD1lHg5jk87q0UvPEFJbe56oPyUDYIHorFMXCtkB\nSp0+FG2szkowh6Po7B7p6lTueX4hCfE63q/RjQu0vNkacOGXYHvO/nT/7D6KtFG9OpRZwtuB5emu\nCGXEsehh9FDIFrOpVZN7q6ME4mkpcEBoVM5qdWoVt/3gUeGi7NoO+67+Xub8tmwmHzbP8nOXg3X9\nfNoTD1RXYZyvLZE4fAJJsmUmaxheX5QZ7wY+viDhcuVgAlnxxX0LLauJsgSdLdbbADd1bV5VS5Lr\n7B78FfM0LvFrQA5ay6ZN+k3078VR8KQ77wOOtuiXuls/asxNNLGEZe3j1Oqa8f4PJaCMlo6GC4Fw\nG3ADbVBwDp6yZwFL+jqVJcecF0yGso2WSscQ2vtmwXqV/rt1ntgPMcrqJSBUCsg3n8UAqSqyrJMP\nFl3aW/zxO8e34gRl8Gb+Av7qEDyqQnJbSeqv+bQRtgG85qT9oO8xyqlwpsHqHY98338C2Doe0qWE\nihq/+PAb/4nr9c5kJKMC6aqGRJYAD0fox21bybPmT4ZB2ZffeOrw36ME+hNkiBhNVDEW0j4LFPfC\nYTBRPHdDBONBGboUy+sX0hhLEFqDxD/pZ5nuulAJ1Gnpq5tYOdAVxsaLS4xVsiN6zvxKorSgpp8N\n6MetCHR0J1sVQSDbgLtEnrJ7/7F0wLUSS9jjxyJk3JHSRXyJQkLPrGjNvsgaaZ2+lUq84JavE4TW\n9WVMjvOBSoHbjCPnbFZC8a49DiHvK1W7MjjzSoFWxEqbJf55ZKbmbZgJvRBEMomcR2nX6WZLbKWd\noRt3xjhQXyyiLw7QmCKsylEF4+dhqgHIebhz0y70vdoOeqc0rMJsm2eLHLngRgytaRry7GtPEs5k\nEPzKLb4IzUud4aHQuqMS48KrQWjqCoEMqJC+/cyg0GMCPX8DoZ9NTjThi3KQ0Zm7ccl0zBlw3HJO\n4qeihfn5PUbsuXiimxdpDSOITExdNX2hgIYo6AHvcXqMa/5Srf1HuJLKLN77iqK19L2yGGkfG4cT\nPp+WIn1zd33WLqzGEEGFwucN4QrfZT0Mk0WseahDZbW80vLs1NuEfK2AfMYWc+gVKQjjNjUOEeA9\nEL0nVCajyreQL1X77MQ/Z3f7MKXlMZIKZ9st9Pqja1Wqt63i3HjrSEDh1cr7EQru3+zBo7gAIJNr\n9GzPVfhPzNmlRJyLd29w63i3/hPgjFiRB2yI01ijIow79xNLQev0WpGBJKnLZIkIGQdHfPjySCPp\nLNOOluCTX9RiV7C2yt65IAYwEE3Rmu0QeEMTSJr8M6cwP8mkQHG7TC26sVsjzhaVJ31m5gOTplWS\neyBIdXbYZgIWt1obgM5qbXkjN05FCv5jjW3R13d0x6cAu0lu1EIU8Otrn3d7K7abyyOqc6fFOCWC\nFarr8sTVDJSYHojX+adnx0hjaUrcMBbGBTKORHKWrTFaDAPouT+Wyu7oCi+Hh5VqU+mZe/qB7Kxj\nlgqWgjbbdcxQ8ViVvicBe5q/Ovu9OX/S/BryWWNVpNVVPrNNP7Ud6AruH/fVFpmbyTL55m/dllDf\nEsoSG4IV4Iq8y+AEYbXrUUN6PUiM0B/GGx4FWgf8LDcPntO8P7KQcTV6F6MLG/Me/gsMqJg9cTka\nGebbtdVE3YGk4XTN1vGthwkfPh1Bj6hbaXmcvd1KVqWndHf7ySukioyKHVdLKfaleKZQjgYrFC3+\nk9M5UF8iyFNdxOHcn2vCBKWVc1I2pd6ZMR0eYCpW3Bl+UUc551rT4YjvRrmtgQDJa6pyO3YU8u8d\n4WmETh5BlAaqkEDHrICLy8G5Yep8lSuyYflQRyJlV2xhgVqOUJTgtQij9t35ogixJNN+XdeAvnZN\nYp/xoGGboGv2dQbh1AB6/hISTyoeoxiUiY8Nc+wJ43jxi7Zof2SnRGiGZO+DEU5xvGRXl2Ws30bG\nF6+Am3Fvx6BC8+k+3uh9EM9dWQfSBMnHdb3idchTHaECxrWgQ6YbLbIwFuEO5ZH79Vq0tBc5et4I\nGX9TavQlby9lMDPpsiWQoFMzvCBc3iZ+lZJau9LWocl+f/9BM5rtOdI0HmACQiXtU54IhGtfHCn8\navgoEX6YeYOtrL13mkeqZNMTwp9lDG2/ChB8jfBoeD2759DTTH3o0cL9Sf5OTcuPA3V6/lQNTJTO\nF17UEFBwpnizy/n8XdzKpjU+gDcJsRcp/WGYombRXjSxfOEcYeRGaNBkgmqcV6xbHB9voCeSyNZQ\n3NYbjLsDuHnQ5i0saD+Yo1ryDiGFJoetyr6nXA1l8onA/40QGdAL14rfQV6HmaKHRVYCsF5tQoxH\nG29OdGuI0EVOUfIt+T29zFbaLde+rv8aqiogYctNjvILupJVMCrUy3eB1cYL1r4cE8vDpaIrVw3S\nlXsgoXh2LK7PC3REaCHJDLS9oq0Nxu43MiAuaSZ6DZp0U5rHH4DcUGKGK4LxiKC1fKZB2YXk8CXg\n4JmMulWsBZyVc1Hs2STEooc5NEZRynFPyNx6sPwUKpBlwvxgPIz8ashYeArr7pgtazIlQCV8RsbB\no3WNCfSTrHDscYbNhNGSN15ujTXyZIxf0xmw1NxhW4VE0LbVbU4Q9muynFksh/f+O3sz79eTs2Wk\ncj94qweFDzzDSKfo+fYFxr35zCg/FefHqD9FPNrkArUiafPmFRWLGkm6SWycHTHW2dmOUxqBLDnS\nKOU4i53LrnwJtNlnnNbR9vCnTV3HZkrvTaGD1GJiRzC/es+XDUFHEb7YDM8JUKlRbU33uV+CnXcq\nE5Afnqcfch6xTfp4W24eBeAxeKZEXYdjLxisOYvQ03BbLnt/ao+HyqjiaVos86B9Z8guiTv7Y7vm\nU0QBEPyFWR0ehm2yrjUy2ZOjpN+dN8ptlOpi+8jkgisg6gYT2U8e1S2pPCrAtZwj51rEayRg6gp+\nfZ1+HBHDLTW++YMQshPGSEXZMzn40VO97CNjgrh8ovSvROZzPoujNet0XF4Xl+0pRfUzN08GGTzc\nCDNZWKvs7QQNI0+Jzy3TOqD5OoFWQbRf3ETptGJEjsxTG4xPlNBT393qN4TMLuz9Lu1DCUKN/auR\nkZ2FO6X5bGfE7IJXmo05JK9M+NQ17wS6A/rJrHFTFQG3i3U1xyCqWFjTpJJamaXa8Ap24WYvz6dc\n098Zr90dPEFqCDwe6hxyVvY5RfffPzDqQb5DMiiFBA0+l1lXQ6msvQO0/PjN67FDr+p4RuZxhV6p\nTCZm4lrQ47Q5/Asnv2QX7XT23yACOPXvT5VII5iJx66cZDW8PqcokaLa+pAtVqbgZDPxZD1C4NXw\nAoObbkqulKoJobs7EjZSIpKQqr5GCZ3QjgDDwPruhevdnzONX5uBvI19+JYqusyuR333F376uyvK\nn6F+d/zNdvSAV3gIz9JaPPEhjbKgsUOFhdyDoaXdydwVHrAB1SkIhNzpfNl62QU0h9m1rX0tPNdt\nUnlnjJPMTjVt7hS8vJhfgtk+39dFB37FS3rVDWUD/97MlcR8z6MEGzbLsGSRtQgzQXSzXL4ruX2E\n7F8oaVsrywznJGiEc+2zzA1QekJQuy5dxS2hvHftZoajaCqWhhrACvQAE5HTIr8etonzlt70MhBX\nR4L2Kdszs+cuKe7YCn41vp6yn+jkXCpOzLOekgT30vVB2cScqwhXUnoA4eD5oeMK/VvSG8OomIto\nmaCJiv0wLgJ7kJsprJEeL16mqTkMwmvay2FtiWlIWbKIs9hgg5RqP5ftklAYWiA/4wg9CMMoH2hp\nuZ1nni2cWWGynf2ne0XC1qDqennT2JyNAQtk9Jw0eXHvjVLarN4YgyFvFTr0C5rV9472azo3UE8A\ndbhgNUf94/74joOWhz9K0BX6hu6u9am3nZfHjzT8iT3pq3MtSlLDx/+vqR09j1sBXhBoyiyASoio\nhAQyBIlf137OHYUONIvyzXe1M6PgVDfdvFr6g7VVEpVZDeSgkN1SXdnbZwYBVLOYe3JTzPfiCNmw\nPL+c0DJ8OwN91pieUcftyhX8/4nraUP0jfbmoqYneAn2aizdgj+uYZDayM1DDIqG7HkWgfoTyOux\nFto6L/LvFuzFDe+ipcLHg/txvv/oK16fIF31ETqIDIKRU1LBbQAbPUwEZxC+TEnpkcr6oVT0hwHN\nJuTLW8ZHgsVNC5YQaLbTIU0uVZ2AYfXpD5jXx2DHxpFmqpwAA10PEvjjBwEXurS92XYW6Vlh3vag\nh8071PI4Y8h0dlx5dPI/VyJA5MsaecCPh9Wc3Mu9ju7CmJzmdnouyGW49lVc7T+BFgn8vY84W4Jy\n0EOJqxtbldn/b0RL9qNfkmndlxOOYUGpkoTDXOeKNtd7HyleHoQUnqsrJltt7n1TUWyBkUSvmr2e\nhIco9V0pfGLnQmBrcS8ESf7JoDfid3dd9xhfTYd7x95o4BpLRW9VbAnUv/qzO2Ql4PsXD4elhlqQ\nIX/zvEAslyulqRlaIojF5lfyR5gs5T3XDgy9J3wvtzGMB2e/OdhArVKDlyiGKVBCwObJBltJLdrm\nqQtoqvfdCn+V9EPh8P1tILiKhp/pxpNcMLi4F54Ss1mMT6eOjdsUUk2NgxCMXJ9DCe3Vzm8uyZL7\ngcN4jfAg3E1rqk3m/i6KHng7yyFwHWIWhDG1pdVdgHnmaVWwnYivlzpB/S7eNw4unSB3dd2BlnzG\nRb5PE2fCqQmV6WZPnzyEbQbON8IXydg2GwqhVl7d+KhVvB9u2DtRSUwccaSTmzQitYkii0ktito/\nOZn5ZAWREOagH6xk2jSJtB+raBOlZD/StDmobLXWmpcaSlaEkDEyTAMr+crVbeg3vAGSoSOK9IbG\nhEMMVUnbYc1PtZV+vY21I6ppYt5T/zHwORuaK4UahSEs+tc11E84gYKfibx4zaxbrR6PIWoRhFpx\nfygJGI82fQqpK8rIAfb84Z6eXjnfx8vNe3ePHTI9pkZghZ1vx44M7VPJerWd7U5zd1C45avIo7bJ\n7u6tesU5+cplrvIG+231DuhICa8DH9UF72c/JWk3FiHDqhpde5ScS3IcWx1hhrKBvi5FXoH10veQ\nlHicTS5ZPF03XuljrC096UTByid0LNhm3MEYNMhJHDAg//PphATDzK9kPRVEqWJNnUXtQxCtfaGv\nDDm9ZwguZj9gqtu4FYLLYUIYBSERRP0P3uA20WOHJw+chMy+nL/5NJ5IbO3bDpRrULtw20tfYeXd\nMEZRrVydMWKNjYU3WDHTREgJjguTG/o0uckR8jUjDqND8/aBClo3a38CpFmPcWL6ws4xn7mPX0eQ\ndm04/XpCC8K8rCxBby0gOx53dNfuWePoTZANSnjGGiUI5BxmFdAWSo6va4tcRBNNZMPM97o0kVhv\nEPnfc3/sGE1x3k8/zSHbDc8HaQOXTo9W3rmPsM1cLrN9t27Iox3uo8H8MKqn1YcA0ilt5LAjrSV+\ntUKxL0hO5/r4sVSAigD8X48thLABHsoJPxsvEF8LqbeF6ar28+m3HKCwEkXmuDsb2D9EH9UPETzk\noU7Zlu+cBilAsNow3MhIVGRoQMJ90wjs5tMHHN0coijGoZTA0lcU/s6NGNC2TOBj1w5bSDX8FKiM\nS07TxyW3rw6YTaoFIbD66Rq/NSP/31Z3DELdKtPR9xDQKSDKf8jWDeUMJczhi6nWPBQbN7UQtmrO\nLkeWuAHdvStParHRMDHlyl76hJKPEZy48fg9N9UdnO+Pd1Ald+lem+PCsHHf+OqbXStJyJ7sNQPS\njKJNQgifRKxMJxi0ijJ0y77hsBxInqwKBywtcfVKlXs5gwB5+HzKqctr1bzPf+oUVROtD4s7C8n8\nPRAVBiiazwsrGoCKpXRTQdmcPIWk5o/ljibexkeIJdZGOflQLAG79TkQP4VR589A9TEHqrbDA8Ow\niEvue5OjEfXk8v35rM5k036b2nWDRQjwgH6Ww3B4Lm4ynLAYQGTB96U9XWkAnWLiLp5m8zvFZdDi\nE+meA0JkE6eMo9xpSCwtthR9qC/ZN+oxyhOIxOtsuOB79uBllrVRyxq5F8q9Jv+a7IKcvLMc3+Sk\nZmbgOAgVLYMQnsj7C+GgRoA181qNGBLLADnDESGgJ/3VlMRVMiOvVQ+AWmMuns4aRjO7TJj0T4gj\nOtQxN5mRSOWygf4wDNFbjjzdk9Wrb+YtBxxP67a1DBY73E4f8rq4GAGOc+uA+vYPxN2cpzQMxn67\ntST3yTFSN0HU+TLzADeDsR9fli+VCAO40pjEmfvnmz8uX4ieAh1/bmsrpCB4hddDi4K7Pm6hCPVZ\nlNMu2yUJ2Gv7pSfim/c6uDmTOvuyKRHsEtHBss9V0SHiF7zsCw9jC1Gw1Z3hAWIEE9MWxlQFYCc/\nOJl2e+2sT7p7D6B+NL5udUm7nX8gB74q1PUFWPsGYpD2pu3lCBVsQcSipoVTozPzXTMu9GhiBbtD\nKMVzVgZKLQb85zYLEfk9esGkaaAa/IMlXBYyZ3KgxHNEQVVYLd/28z6Bgq4z92uZ+nUjAQQNhNbd\nihUSeLisI8jS+p0o5SqzysX2BhJTA73Dl1qC80tYYxi+Dgt6Ix5T5JgkBeZt5XKSBj+tWhDWKCDx\n6uUFw/ci6OktwfqL5KZVOMkEwPLWW0W3S4EwFRv/nqulclXjxaiEmI1qy2g3i4xu4ozAzfvuY4PX\n4TNsbHRGXKHnbUq3OX7WWl0FoO0CnTw7uzXYj3goIj+2ppauZVSQt3oGFMco07p5c7AG791rM2wx\n+pZL5s5qBaL9pScdRgmtmuslKlqootc7gQJ5OxR6mvoMhOnphhgyojQnOr+SJEtDMMD5rHlXoSgW\nUJGwt8q/XT7s+tAVwEfFZwcio0IPbQNDOOsdHChnWoWh82tTu2wWSgR7Kg3fahsm6lpYDnkid7j5\nkTGihYKRKRkvpg2Ws63TmPYjpdul3WC+b4ZOhk6v3C1IdjpjOJ5UG4l9tMkYVfoW7y024BquSO5/\nMPPdTM2nWYdjbgO42K4Zxv4zLj2NSkWZm3pkgJP8LOnt+bV9C5AceuFe2YEcYfHP2NnzCbPkW3DX\n7OB2UfViC3Mm7S4KKuGfnRC4dEAlRwcrCwYneuiP6uS0A1MNUvCnPn8WEs3qpVOweX2aJkYS5ur/\nR1bloUhVQUshGkVfjwbVCpNKA1Z9uzEmBMAoQ7XvphL37Gw4A6IF6IP0hE2sLueqpM8yW6YP/n2m\nThOWH112SQ7B6Cl1xkrSYRy2fRhCPLiOb/AIOrOXBfO7Htq4hRh8mLjn9tsBdxQiCauhjPtftHqA\nbnkLa4np5WOkVect6L/DVTK0V5YtCK3SVmMRX5+n/iH5KjTBdbJDG5zE1+cZIZUf1jHOQT1zGeYb\nPcdKviHtuX/dxA/zR96YYgE+6kvpWexwOMkvDnMeZrFWV3YA2Q4yzl1IMz7mxXAYg+xr1XhyQAHh\nbvAoPX1ZX/f/hT0d5tm7H0+hzJGpOMNmOb9uWoxbURr1oTe7Aub9LGHM7MeHGjRy0eeNA4l9a3ZY\nWaNVI8NHq1/gTMRD2P454oSx+FPyBOny6Sx3+WAXKWV4raTpFUBs/OkARVapcvZtqOP0JQyWm7PT\nCLXQurpYYnK+M5sJwh9q8N5Ymi5B7RVWKXSw3bTt5UpCMFF8w3wqLBnB20ai9FBNCmCWLZmqK1BW\nOT5Z9SWGsFad4wD/ykn7EphW/XOoLWY4gWTRReb8kUiyK4uYq3GdyedGWQMQubbwsw4Yf9XLQOCA\nveyvPmR0nXWIDyie/P517DyAPPR3QSsQaXWL6OwedlZe9/pJZvpyVuCkMvohDO0OiZBnKhw8c6g7\nQDxVJpr+PzuscPWWNvWsRleF9CtP6o3lVCPYofb5eni3/gew6UuMOOPdq96vjfol+ipMOitig/EK\n5KSSJc4ignVV1rpPdS8jKt1uRzdiIG04lIgKV/iTrGxulwFTYWn0YXZ70j00M7akJBpgtHYtEwg7\ntuFwF87SDt98jOPD/WHKwoeleWTKwDzN8dUG6rIIjciM7ttKAupuKB8zcngy2+VEd8SJsoOuiVXv\nI1jEkJzWfyF9h+BgpXXoFGfSUjm4PqBwqBTsya3TbfnxMusFwVAmhcgkODyoaBE2aPevUBLTPEyg\noXiZdFn96TTFBTSKxfbvfoWmBfJLQG+IUMH6XUArLaDvPsOewnpCrh+xOPs2VUJvRJlbOoQA8hhc\nBYFw9C/vaE8JPImPCF8Mcml3atuzrH8J+M55leKZ+Ahyde17lDJYmLaTtLVQgqkyaZyHgYJabqrL\nfvxMvqW5F5ysEsk4uLDBFDd26mKkWfaYPU1SQDCVe5TX6ZCrMoOF7QT3xo/dGRKOrgxhF80rEBSA\npbHEX09kRVpK/s7dJePfIDBOH4wslJSyr+cpQWARs1LDsRdJqfBnbx5MEQ4E2qk0F1V6P0Uu3APK\nPs8KsBhcdUXgUqbGbsEQmLHNmMsW9PItMgYMqBKVjCWjmnu7XFM+2WPGuA22GFgbq/HHjTvb4+a/\nhNHFvP4EGDou4Pq063a7EtIFFh0VzxeE8It65f8GizD4Z/YaE5NBdVql7NOdDECr3l5vqCI3HnNC\nrd00HANISl5oyA2MuYTQR+GQaXrKUzZ0cDbvQZ7P2epot1a+MCmRzUKtgRQlP3GEAOvl/z6jyNGl\n0i9gClFCTubmketbUNA8oLzc5tOCpMdeyfZX7wq1Mj84m63g4WECc1S400lGBZhiUvaRIgsEnvQo\n0/oWeneHemIMitJgnp4Mf5PvMfKmyud8ED+o05VrGt2n1P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{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:xsdbm:3.0\n// IP Revision: 0\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_a493_xsdbm_0 (\n  update,\n  capture,\n  reset,\n  runtest,\n  tck,\n  tms,\n  tdi,\n  sel,\n  shift,\n  drck,\n  tdo,\n  bscanid_en,\n  clk\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan UPDATE\" *)\ninput wire update;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan CAPTURE\" *)\ninput wire capture;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RESET\" *)\ninput wire reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RUNTEST\" *)\ninput wire runtest;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TCK\" *)\ninput wire tck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TMS\" *)\ninput wire tms;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDI\" *)\ninput wire tdi;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SEL\" *)\ninput wire sel;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SHIFT\" *)\ninput wire shift;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan DRCK\" *)\ninput wire drck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDO\" *)\noutput wire tdo;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan BSCANID_EN\" *)\ninput wire bscanid_en;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME signal_clock, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_a493_clk, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 signal_clock CLK\" *)\ninput wire clk;\n\n  xsdbm_v3_0_0_xsdbm #(\n    .C_FIFO_STYLE(\"SUBCORE\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_MAJOR_VERSION(14),\n    .C_MINOR_VERSION(1),\n    .C_BUILD_REVISION(0),\n    .C_CORE_MAJOR_VER(1),\n    .C_CORE_MINOR_VER(0),\n    .C_CORE_MINOR_ALPHA_VER(97),\n    .C_XSDB_NUM_SLAVES(0),\n    .C_XSDB_PERIOD_INT(10),\n    .C_XSDB_PERIOD_FRC(0),\n    .C_USE_BUFR(0),\n    .C_DCLK_HAS_RESET(0),\n    .C_EN_INT_SIM(1),\n    .C_CORE_TYPE(1),\n    .C_USER_SCAN_CHAIN(1),\n    .C_CLKFBOUT_MULT_F(4.000),\n    .C_DIVCLK_DIVIDE(1),\n    .C_CLKOUT0_DIVIDE_F(12.000),\n    .C_CLK_INPUT_FREQ_HZ(300000000),\n    .C_ENABLE_CLK_DIVIDER(0),\n    .C_USE_EXT_BSCAN(1),\n    .C_USE_STARTUP_CLK(0),\n    .C_EN_BSCANID_VEC(0),\n    .C_TWO_PRIM_MODE(0),\n    .C_USER_SCAN_CHAIN1(1),\n    .C_BSCANID(76546592),\n    .C_BSCAN_MODE(0),\n    .C_BSCAN_MODE_WITH_CORE(0),\n    .C_NUM_BSCAN_MASTER_PORTS(0)\n  ) inst (\n    .sl_iport0_o(),\n    .sl_iport1_o(),\n    .sl_iport2_o(),\n    .sl_iport3_o(),\n    .sl_iport4_o(),\n    .sl_iport5_o(),\n    .sl_iport6_o(),\n    .sl_iport7_o(),\n    .sl_iport8_o(),\n    .sl_iport9_o(),\n    .sl_iport10_o(),\n    .sl_iport11_o(),\n    .sl_iport12_o(),\n    .sl_iport13_o(),\n    .sl_iport14_o(),\n    .sl_iport15_o(),\n    .sl_iport16_o(),\n    .sl_iport17_o(),\n    .sl_iport18_o(),\n    .sl_iport19_o(),\n    .sl_iport20_o(),\n    .sl_iport21_o(),\n    .sl_iport22_o(),\n    .sl_iport23_o(),\n    .sl_iport24_o(),\n    .sl_iport25_o(),\n    .sl_iport26_o(),\n    .sl_iport27_o(),\n    .sl_iport28_o(),\n    .sl_iport29_o(),\n    .sl_iport30_o(),\n    .sl_iport31_o(),\n    .sl_iport32_o(),\n    .sl_iport33_o(),\n    .sl_iport34_o(),\n    .sl_iport35_o(),\n    .sl_iport36_o(),\n    .sl_iport37_o(),\n    .sl_iport38_o(),\n    .sl_iport39_o(),\n    .sl_iport40_o(),\n    .sl_iport41_o(),\n    .sl_iport42_o(),\n    .sl_iport43_o(),\n    .sl_iport44_o(),\n    .sl_iport45_o(),\n    .sl_iport46_o(),\n    .sl_iport47_o(),\n    .sl_iport48_o(),\n    .sl_iport49_o(),\n    .sl_iport50_o(),\n    .sl_iport51_o(),\n    .sl_iport52_o(),\n    .sl_iport53_o(),\n    .sl_iport54_o(),\n    .sl_iport55_o(),\n    .sl_iport56_o(),\n    .sl_iport57_o(),\n    .sl_iport58_o(),\n    .sl_iport59_o(),\n    .sl_iport60_o(),\n    .sl_iport61_o(),\n    .sl_iport62_o(),\n    .sl_iport63_o(),\n    .sl_iport64_o(),\n    .sl_iport65_o(),\n    .sl_iport66_o(),\n    .sl_iport67_o(),\n    .sl_iport68_o(),\n    .sl_iport69_o(),\n    .sl_iport70_o(),\n    .sl_iport71_o(),\n    .sl_iport72_o(),\n    .sl_iport73_o(),\n    .sl_iport74_o(),\n    .sl_iport75_o(),\n    .sl_iport76_o(),\n    .sl_iport77_o(),\n    .sl_iport78_o(),\n    .sl_iport79_o(),\n    .sl_iport80_o(),\n    .sl_iport81_o(),\n    .sl_iport82_o(),\n    .sl_iport83_o(),\n    .sl_iport84_o(),\n    .sl_iport85_o(),\n    .sl_iport86_o(),\n    .sl_iport87_o(),\n    .sl_iport88_o(),\n    .sl_iport89_o(),\n    .sl_iport90_o(),\n    .sl_iport91_o(),\n    .sl_iport92_o(),\n    .sl_iport93_o(),\n    .sl_iport94_o(),\n    .sl_iport95_o(),\n    .sl_iport96_o(),\n    .sl_iport97_o(),\n    .sl_iport98_o(),\n    .sl_iport99_o(),\n    .sl_iport100_o(),\n    .sl_iport101_o(),\n    .sl_iport102_o(),\n    .sl_iport103_o(),\n    .sl_iport104_o(),\n    .sl_iport105_o(),\n    .sl_iport106_o(),\n    .sl_iport107_o(),\n    .sl_iport108_o(),\n    .sl_iport109_o(),\n    .sl_iport110_o(),\n    .sl_iport111_o(),\n    .sl_iport112_o(),\n    .sl_iport113_o(),\n    .sl_iport114_o(),\n    .sl_iport115_o(),\n    .sl_iport116_o(),\n    .sl_iport117_o(),\n    .sl_iport118_o(),\n    .sl_iport119_o(),\n    .sl_iport120_o(),\n    .sl_iport121_o(),\n    .sl_iport122_o(),\n    .sl_iport123_o(),\n    .sl_iport124_o(),\n    .sl_iport125_o(),\n    .sl_iport126_o(),\n    .sl_iport127_o(),\n    .sl_iport128_o(),\n    .sl_iport129_o(),\n    .sl_iport130_o(),\n    .sl_iport131_o(),\n    .sl_iport132_o(),\n    .sl_iport133_o(),\n    .sl_iport134_o(),\n    .sl_iport135_o(),\n    .sl_iport136_o(),\n    .sl_iport137_o(),\n    .sl_iport138_o(),\n    .sl_iport139_o(),\n    .sl_iport140_o(),\n    .sl_iport141_o(),\n    .sl_iport142_o(),\n    .sl_iport143_o(),\n    .sl_iport144_o(),\n    .sl_iport145_o(),\n    .sl_iport146_o(),\n    .sl_iport147_o(),\n    .sl_iport148_o(),\n    .sl_iport149_o(),\n    .sl_iport150_o(),\n    .sl_iport151_o(),\n    .sl_iport152_o(),\n    .sl_iport153_o(),\n    .sl_iport154_o(),\n    .sl_iport155_o(),\n    .sl_iport156_o(),\n    .sl_iport157_o(),\n    .sl_iport158_o(),\n    .sl_iport159_o(),\n    .sl_iport160_o(),\n    .sl_iport161_o(),\n    .sl_iport162_o(),\n    .sl_iport163_o(),\n    .sl_iport164_o(),\n    .sl_iport165_o(),\n    .sl_iport166_o(),\n    .sl_iport167_o(),\n    .sl_iport168_o(),\n    .sl_iport169_o(),\n    .sl_iport170_o(),\n    .sl_iport171_o(),\n    .sl_iport172_o(),\n    .sl_iport173_o(),\n    .sl_iport174_o(),\n    .sl_iport175_o(),\n    .sl_iport176_o(),\n    .sl_iport177_o(),\n    .sl_iport178_o(),\n    .sl_iport179_o(),\n    .sl_iport180_o(),\n    .sl_iport181_o(),\n    .sl_iport182_o(),\n    .sl_iport183_o(),\n    .sl_iport184_o(),\n    .sl_iport185_o(),\n    .sl_iport186_o(),\n    .sl_iport187_o(),\n    .sl_iport188_o(),\n    .sl_iport189_o(),\n    .sl_iport190_o(),\n    .sl_iport191_o(),\n    .sl_iport192_o(),\n    .sl_iport193_o(),\n    .sl_iport194_o(),\n    .sl_iport195_o(),\n    .sl_iport196_o(),\n    .sl_iport197_o(),\n    .sl_iport198_o(),\n    .sl_iport199_o(),\n    .sl_iport200_o(),\n    .sl_iport201_o(),\n    .sl_iport202_o(),\n    .sl_iport203_o(),\n    .sl_iport204_o(),\n    .sl_iport205_o(),\n    .sl_iport206_o(),\n    .sl_iport207_o(),\n    .sl_iport208_o(),\n    .sl_iport209_o(),\n    .sl_iport210_o(),\n    .sl_iport211_o(),\n    .sl_iport212_o(),\n    .sl_iport213_o(),\n    .sl_iport214_o(),\n    .sl_iport215_o(),\n    .sl_iport216_o(),\n    .sl_iport217_o(),\n    .sl_iport218_o(),\n    .sl_iport219_o(),\n    .sl_iport220_o(),\n    .sl_iport221_o(),\n    .sl_iport222_o(),\n    .sl_iport223_o(),\n    .sl_iport224_o(),\n    .sl_iport225_o(),\n    .sl_iport226_o(),\n    .sl_iport227_o(),\n    .sl_iport228_o(),\n    .sl_iport229_o(),\n    .sl_iport230_o(),\n    .sl_iport231_o(),\n    .sl_iport232_o(),\n    .sl_iport233_o(),\n    .sl_iport234_o(),\n    .sl_iport235_o(),\n    .sl_iport236_o(),\n    .sl_iport237_o(),\n    .sl_iport238_o(),\n    .sl_iport239_o(),\n    .sl_iport240_o(),\n    .sl_iport241_o(),\n    .sl_iport242_o(),\n    .sl_iport243_o(),\n    .sl_iport244_o(),\n    .sl_iport245_o(),\n    .sl_iport246_o(),\n    .sl_iport247_o(),\n    .sl_iport248_o(),\n    .sl_iport249_o(),\n    .sl_iport250_o(),\n    .sl_iport251_o(),\n    .sl_iport252_o(),\n    .sl_iport253_o(),\n    .sl_iport254_o(),\n    .sl_iport255_o(),\n    .sl_oport0_i(1'B0),\n    .sl_oport1_i(1'B0),\n    .sl_oport2_i(1'B0),\n    .sl_oport3_i(1'B0),\n    .sl_oport4_i(1'B0),\n    .sl_oport5_i(1'B0),\n    .sl_oport6_i(1'B0),\n    .sl_oport7_i(1'B0),\n    .sl_oport8_i(1'B0),\n    .sl_oport9_i(1'B0),\n    .sl_oport10_i(1'B0),\n    .sl_oport11_i(1'B0),\n    .sl_oport12_i(1'B0),\n    .sl_oport13_i(1'B0),\n    .sl_oport14_i(1'B0),\n    .sl_oport15_i(1'B0),\n    .sl_oport16_i(1'B0),\n    .sl_oport17_i(1'B0),\n    .sl_oport18_i(1'B0),\n    .sl_oport19_i(1'B0),\n    .sl_oport20_i(1'B0),\n    .sl_oport21_i(1'B0),\n    .sl_oport22_i(1'B0),\n    .sl_oport23_i(1'B0),\n    .sl_oport24_i(1'B0),\n    .sl_oport25_i(1'B0),\n    .sl_oport26_i(1'B0),\n    .sl_oport27_i(1'B0),\n    .sl_oport28_i(1'B0),\n    .sl_oport29_i(1'B0),\n    .sl_oport30_i(1'B0),\n    .sl_oport31_i(1'B0),\n    .sl_oport32_i(1'B0),\n    .sl_oport33_i(1'B0),\n    .sl_oport34_i(1'B0),\n    .sl_oport35_i(1'B0),\n    .sl_oport36_i(1'B0),\n    .sl_oport37_i(1'B0),\n    .sl_oport38_i(1'B0),\n    .sl_oport39_i(1'B0),\n    .sl_oport40_i(1'B0),\n    .sl_oport41_i(1'B0),\n    .sl_oport42_i(1'B0),\n    .sl_oport43_i(1'B0),\n    .sl_oport44_i(1'B0),\n    .sl_oport45_i(1'B0),\n    .sl_oport46_i(1'B0),\n    .sl_oport47_i(1'B0),\n    .sl_oport48_i(1'B0),\n    .sl_oport49_i(1'B0),\n    .sl_oport50_i(1'B0),\n    .sl_oport51_i(1'B0),\n    .sl_oport52_i(1'B0),\n    .sl_oport53_i(1'B0),\n    .sl_oport54_i(1'B0),\n    .sl_oport55_i(1'B0),\n    .sl_oport56_i(1'B0),\n    .sl_oport57_i(1'B0),\n    .sl_oport58_i(1'B0),\n    .sl_oport59_i(1'B0),\n    .sl_oport60_i(1'B0),\n    .sl_oport61_i(1'B0),\n    .sl_oport62_i(1'B0),\n    .sl_oport63_i(1'B0),\n    .sl_oport64_i(1'B0),\n    .sl_oport65_i(1'B0),\n    .sl_oport66_i(1'B0),\n    .sl_oport67_i(1'B0),\n    .sl_oport68_i(1'B0),\n    .sl_oport69_i(1'B0),\n    .sl_oport70_i(1'B0),\n    .sl_oport71_i(1'B0),\n    .sl_oport72_i(1'B0),\n    .sl_oport73_i(1'B0),\n    .sl_oport74_i(1'B0),\n    .sl_oport75_i(1'B0),\n    .sl_oport76_i(1'B0),\n    .sl_oport77_i(1'B0),\n    .sl_oport78_i(1'B0),\n    .sl_oport79_i(1'B0),\n    .sl_oport80_i(1'B0),\n    .sl_oport81_i(1'B0),\n    .sl_oport82_i(1'B0),\n    .sl_oport83_i(1'B0),\n    .sl_oport84_i(1'B0),\n    .sl_oport85_i(1'B0),\n    .sl_oport86_i(1'B0),\n    .sl_oport87_i(1'B0),\n    .sl_oport88_i(1'B0),\n    .sl_oport89_i(1'B0),\n    .sl_oport90_i(1'B0),\n    .sl_oport91_i(1'B0),\n    .sl_oport92_i(1'B0),\n    .sl_oport93_i(1'B0),\n    .sl_oport94_i(1'B0),\n    .sl_oport95_i(1'B0),\n    .sl_oport96_i(1'B0),\n    .sl_oport97_i(1'B0),\n    .sl_oport98_i(1'B0),\n    .sl_oport99_i(1'B0),\n    .sl_oport100_i(1'B0),\n    .sl_oport101_i(1'B0),\n    .sl_oport102_i(1'B0),\n    .sl_oport103_i(1'B0),\n    .sl_oport104_i(1'B0),\n    .sl_oport105_i(1'B0),\n    .sl_oport106_i(1'B0),\n    .sl_oport107_i(1'B0),\n    .sl_oport108_i(1'B0),\n    .sl_oport109_i(1'B0),\n    .sl_oport110_i(1'B0),\n    .sl_oport111_i(1'B0),\n    .sl_oport112_i(1'B0),\n    .sl_oport113_i(1'B0),\n    .sl_oport114_i(1'B0),\n    .sl_oport115_i(1'B0),\n    .sl_oport116_i(1'B0),\n    .sl_oport117_i(1'B0),\n    .sl_oport118_i(1'B0),\n    .sl_oport119_i(1'B0),\n    .sl_oport120_i(1'B0),\n    .sl_oport121_i(1'B0),\n    .sl_oport122_i(1'B0),\n    .sl_oport123_i(1'B0),\n    .sl_oport124_i(1'B0),\n    .sl_oport125_i(1'B0),\n    .sl_oport126_i(1'B0),\n    .sl_oport127_i(1'B0),\n    .sl_oport128_i(1'B0),\n    .sl_oport129_i(1'B0),\n    .sl_oport130_i(1'B0),\n    .sl_oport131_i(1'B0),\n    .sl_oport132_i(1'B0),\n    .sl_oport133_i(1'B0),\n    .sl_oport134_i(1'B0),\n    .sl_oport135_i(1'B0),\n    .sl_oport136_i(1'B0),\n    .sl_oport137_i(1'B0),\n    .sl_oport138_i(1'B0),\n    .sl_oport139_i(1'B0),\n    .sl_oport140_i(1'B0),\n    .sl_oport141_i(1'B0),\n    .sl_oport142_i(1'B0),\n    .sl_oport143_i(1'B0),\n    .sl_oport144_i(1'B0),\n    .sl_oport145_i(1'B0),\n    .sl_oport146_i(1'B0),\n    .sl_oport147_i(1'B0),\n    .sl_oport148_i(1'B0),\n    .sl_oport149_i(1'B0),\n    .sl_oport150_i(1'B0),\n    .sl_oport151_i(1'B0),\n    .sl_oport152_i(1'B0),\n    .sl_oport153_i(1'B0),\n    .sl_oport154_i(1'B0),\n    .sl_oport155_i(1'B0),\n    .sl_oport156_i(1'B0),\n    .sl_oport157_i(1'B0),\n    .sl_oport158_i(1'B0),\n    .sl_oport159_i(1'B0),\n    .sl_oport160_i(1'B0),\n    .sl_oport161_i(1'B0),\n    .sl_oport162_i(1'B0),\n    .sl_oport163_i(1'B0),\n    .sl_oport164_i(1'B0),\n    .sl_oport165_i(1'B0),\n    .sl_oport166_i(1'B0),\n    .sl_oport167_i(1'B0),\n    .sl_oport168_i(1'B0),\n    .sl_oport169_i(1'B0),\n    .sl_oport170_i(1'B0),\n    .sl_oport171_i(1'B0),\n    .sl_oport172_i(1'B0),\n    .sl_oport173_i(1'B0),\n    .sl_oport174_i(1'B0),\n    .sl_oport175_i(1'B0),\n    .sl_oport176_i(1'B0),\n    .sl_oport177_i(1'B0),\n    .sl_oport178_i(1'B0),\n    .sl_oport179_i(1'B0),\n    .sl_oport180_i(1'B0),\n    .sl_oport181_i(1'B0),\n    .sl_oport182_i(1'B0),\n    .sl_oport183_i(1'B0),\n    .sl_oport184_i(1'B0),\n    .sl_oport185_i(1'B0),\n    .sl_oport186_i(1'B0),\n    .sl_oport187_i(1'B0),\n    .sl_oport188_i(1'B0),\n    .sl_oport189_i(1'B0),\n    .sl_oport190_i(1'B0),\n    .sl_oport191_i(1'B0),\n    .sl_oport192_i(1'B0),\n    .sl_oport193_i(1'B0),\n    .sl_oport194_i(1'B0),\n    .sl_oport195_i(1'B0),\n    .sl_oport196_i(1'B0),\n    .sl_oport197_i(1'B0),\n    .sl_oport198_i(1'B0),\n    .sl_oport199_i(1'B0),\n    .sl_oport200_i(1'B0),\n    .sl_oport201_i(1'B0),\n    .sl_oport202_i(1'B0),\n    .sl_oport203_i(1'B0),\n    .sl_oport204_i(1'B0),\n    .sl_oport205_i(1'B0),\n    .sl_oport206_i(1'B0),\n    .sl_oport207_i(1'B0),\n    .sl_oport208_i(1'B0),\n    .sl_oport209_i(1'B0),\n    .sl_oport210_i(1'B0),\n    .sl_oport211_i(1'B0),\n    .sl_oport212_i(1'B0),\n    .sl_oport213_i(1'B0),\n    .sl_oport214_i(1'B0),\n    .sl_oport215_i(1'B0),\n    .sl_oport216_i(1'B0),\n    .sl_oport217_i(1'B0),\n    .sl_oport218_i(1'B0),\n    .sl_oport219_i(1'B0),\n    .sl_oport220_i(1'B0),\n    .sl_oport221_i(1'B0),\n    .sl_oport222_i(1'B0),\n    .sl_oport223_i(1'B0),\n    .sl_oport224_i(1'B0),\n    .sl_oport225_i(1'B0),\n    .sl_oport226_i(1'B0),\n    .sl_oport227_i(1'B0),\n    .sl_oport228_i(1'B0),\n    .sl_oport229_i(1'B0),\n    .sl_oport230_i(1'B0),\n    .sl_oport231_i(1'B0),\n    .sl_oport232_i(1'B0),\n    .sl_oport233_i(1'B0),\n    .sl_oport234_i(1'B0),\n    .sl_oport235_i(1'B0),\n    .sl_oport236_i(1'B0),\n    .sl_oport237_i(1'B0),\n    .sl_oport238_i(1'B0),\n    .sl_oport239_i(1'B0),\n    .sl_oport240_i(1'B0),\n    .sl_oport241_i(1'B0),\n    .sl_oport242_i(1'B0),\n    .sl_oport243_i(1'B0),\n    .sl_oport244_i(1'B0),\n    .sl_oport245_i(1'B0),\n    .sl_oport246_i(1'B0),\n    .sl_oport247_i(1'B0),\n    .sl_oport248_i(1'B0),\n    .sl_oport249_i(1'B0),\n    .sl_oport250_i(1'B0),\n    .sl_oport251_i(1'B0),\n    .sl_oport252_i(1'B0),\n    .sl_oport253_i(1'B0),\n    .sl_oport254_i(1'B0),\n    .sl_oport255_i(1'B0),\n    .update_0(),\n    .capture_0(),\n    .reset_0(),\n    .runtest_0(),\n    .tms_0(),\n    .tck_0(),\n    .tdi_0(),\n    .sel_0(),\n    .shift_0(),\n    .drck_0(),\n    .tdo_0(1'B0),\n    .update_1(),\n    .capture_1(),\n    .reset_1(),\n    .runtest_1(),\n    .tms_1(),\n    .tck_1(),\n    .tdi_1(),\n    .sel_1(),\n    .shift_1(),\n    .drck_1(),\n    .tdo_1(1'B0),\n    .update_2(),\n    .capture_2(),\n    .reset_2(),\n    .runtest_2(),\n    .tms_2(),\n    .tck_2(),\n    .tdi_2(),\n    .sel_2(),\n    .shift_2(),\n    .drck_2(),\n    .tdo_2(1'B0),\n    .update_3(),\n    .capture_3(),\n    .reset_3(),\n    .runtest_3(),\n    .tms_3(),\n    .tck_3(),\n    .tdi_3(),\n    .sel_3(),\n    .shift_3(),\n    .drck_3(),\n    .tdo_3(1'B0),\n    .update_4(),\n    .capture_4(),\n    .reset_4(),\n    .runtest_4(),\n    .tms_4(),\n    .tck_4(),\n    .tdi_4(),\n    .sel_4(),\n    .shift_4(),\n    .drck_4(),\n    .tdo_4(1'B0),\n    .update_5(),\n    .capture_5(),\n    .reset_5(),\n    .runtest_5(),\n    .tms_5(),\n    .tck_5(),\n    .tdi_5(),\n    .sel_5(),\n    .shift_5(),\n    .drck_5(),\n    .tdo_5(1'B0),\n    .update_6(),\n    .capture_6(),\n    .reset_6(),\n    .runtest_6(),\n    .tms_6(),\n    .tck_6(),\n    .tdi_6(),\n    .sel_6(),\n    .shift_6(),\n    .drck_6(),\n    .tdo_6(1'B0),\n    .update_7(),\n    .capture_7(),\n    .reset_7(),\n    .runtest_7(),\n    .tms_7(),\n    .tck_7(),\n    .tdi_7(),\n    .sel_7(),\n    .shift_7(),\n    .drck_7(),\n    .tdo_7(1'B0),\n    .update_8(),\n    .capture_8(),\n    .reset_8(),\n    .runtest_8(),\n    .tms_8(),\n    .tck_8(),\n    .tdi_8(),\n    .sel_8(),\n    .shift_8(),\n    .drck_8(),\n    .tdo_8(1'B0),\n    .update_9(),\n    .capture_9(),\n    .reset_9(),\n    .runtest_9(),\n    .tms_9(),\n    .tck_9(),\n    .tdi_9(),\n    .sel_9(),\n    .shift_9(),\n    .drck_9(),\n    .tdo_9(1'B0),\n    .update_10(),\n    .capture_10(),\n    .reset_10(),\n    .runtest_10(),\n    .tms_10(),\n    .tck_10(),\n    .tdi_10(),\n    .sel_10(),\n    .shift_10(),\n    .drck_10(),\n    .tdo_10(1'B0),\n    .update_11(),\n    .capture_11(),\n    .reset_11(),\n    .runtest_11(),\n    .tms_11(),\n    .tck_11(),\n    .tdi_11(),\n    .sel_11(),\n    .shift_11(),\n    .drck_11(),\n    .tdo_11(1'B0),\n    .update_12(),\n    .capture_12(),\n    .reset_12(),\n    .runtest_12(),\n    .tms_12(),\n    .tck_12(),\n    .tdi_12(),\n    .sel_12(),\n    .shift_12(),\n    .drck_12(),\n    .tdo_12(1'B0),\n    .update_13(),\n    .capture_13(),\n    .reset_13(),\n    .runtest_13(),\n    .tms_13(),\n    .tck_13(),\n    .tdi_13(),\n    .sel_13(),\n    .shift_13(),\n    .drck_13(),\n    .tdo_13(1'B0),\n    .update_14(),\n    .capture_14(),\n    .reset_14(),\n    .runtest_14(),\n    .tms_14(),\n    .tck_14(),\n    .tdi_14(),\n    .sel_14(),\n    .shift_14(),\n    .drck_14(),\n    .tdo_14(1'B0),\n    .update_15(),\n    .capture_15(),\n    .reset_15(),\n    .runtest_15(),\n    .tms_15(),\n    .tck_15(),\n    .tdi_15(),\n    .sel_15(),\n    .shift_15(),\n    .drck_15(),\n    .tdo_15(1'B0),\n    .bscanid_en_0(),\n    .bscanid_en_1(),\n    .bscanid_en_2(),\n    .bscanid_en_3(),\n    .bscanid_en_4(),\n    .bscanid_en_5(),\n    .bscanid_en_6(),\n    .bscanid_en_7(),\n    .bscanid_en_8(),\n    .bscanid_en_9(),\n    .bscanid_en_10(),\n    .bscanid_en_11(),\n    .bscanid_en_12(),\n    .bscanid_en_13(),\n    .bscanid_en_14(),\n    .bscanid_en_15(),\n    .bscanid_0(32'B0),\n    .bscanid_1(32'B0),\n    .bscanid_2(32'B0),\n    .bscanid_3(32'B0),\n    .bscanid_4(32'B0),\n    .bscanid_5(32'B0),\n    .bscanid_6(32'B0),\n    .bscanid_7(32'B0),\n    .bscanid_8(32'B0),\n    .bscanid_9(32'B0),\n    .bscanid_10(32'B0),\n    .bscanid_11(32'B0),\n    .bscanid_12(32'B0),\n    .bscanid_13(32'B0),\n    .bscanid_14(32'B0),\n    .bscanid_15(32'B0),\n    .update(update),\n    .capture(capture),\n    .reset(reset),\n    .runtest(runtest),\n    .tck(tck),\n    .tms(tms),\n    .tdi(tdi),\n    .sel(sel),\n    .shift(shift),\n    .drck(drck),\n    .tdo(tdo),\n    .bscanid_en(bscanid_en),\n    .bscanid(),\n    .clk(clk)\n  );\nendmodule\n", "num_lines": 868}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:xsdbm:3.0\n// IP Revision: 0\n\n(* X_CORE_INFO = \"xsdbm_v3_0_0_xsdbm,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"bd_a493_xsdbm_0,xsdbm_v3_0_0_xsdbm,{}\" *)\n(* CORE_GENERATION_INFO = \"bd_a493_xsdbm_0,xsdbm_v3_0_0_xsdbm,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xsdbm,x_ipVersion=3.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FIFO_STYLE=SUBCORE,C_XDEVICEFAMILY=virtexuplus,C_MAJOR_VERSION=14,C_MINOR_VERSION=1,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=1,C_CORE_MINOR_VER=0,C_CORE_MINOR_ALPHA_VER=97,C_XSDB_NUM_SLAVES=0,C_XSDB_PERIOD_INT=10,C_XSDB_PERIOD_FRC=0,C_USE_BUFR=0,C_DCLK_HAS_RESET=0,C_EN_INT_SIM=1,C_CORE_TYPE=1,C_USER_SCAN_CHAIN\\\n=1,C_CLKFBOUT_MULT_F=4.000,C_DIVCLK_DIVIDE=1,C_CLKOUT0_DIVIDE_F=12.000,C_CLK_INPUT_FREQ_HZ=300000000,C_ENABLE_CLK_DIVIDER=0,C_USE_EXT_BSCAN=1,C_USE_STARTUP_CLK=0,C_EN_BSCANID_VEC=0,C_TWO_PRIM_MODE=0,C_USER_SCAN_CHAIN1=1,C_BSCANID=76546592,C_BSCAN_MODE=0,C_BSCAN_MODE_WITH_CORE=0,C_NUM_BSCAN_MASTER_PORTS=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_a493_xsdbm_0 (\n  update,\n  capture,\n  reset,\n  runtest,\n  tck,\n  tms,\n  tdi,\n  sel,\n  shift,\n  drck,\n  tdo,\n  bscanid_en,\n  clk\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan UPDATE\" *)\ninput wire update;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan CAPTURE\" *)\ninput wire capture;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RESET\" *)\ninput wire reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RUNTEST\" *)\ninput wire runtest;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TCK\" *)\ninput wire tck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TMS\" *)\ninput wire tms;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDI\" *)\ninput wire tdi;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SEL\" *)\ninput wire sel;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SHIFT\" *)\ninput wire shift;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan DRCK\" *)\ninput wire drck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDO\" *)\noutput wire tdo;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan BSCANID_EN\" *)\ninput wire bscanid_en;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME signal_clock, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_a493_clk, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 signal_clock CLK\" *)\ninput wire clk;\n\n  xsdbm_v3_0_0_xsdbm #(\n    .C_FIFO_STYLE(\"SUBCORE\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_MAJOR_VERSION(14),\n    .C_MINOR_VERSION(1),\n    .C_BUILD_REVISION(0),\n    .C_CORE_MAJOR_VER(1),\n    .C_CORE_MINOR_VER(0),\n    .C_CORE_MINOR_ALPHA_VER(97),\n    .C_XSDB_NUM_SLAVES(0),\n    .C_XSDB_PERIOD_INT(10),\n    .C_XSDB_PERIOD_FRC(0),\n    .C_USE_BUFR(0),\n    .C_DCLK_HAS_RESET(0),\n    .C_EN_INT_SIM(1),\n    .C_CORE_TYPE(1),\n    .C_USER_SCAN_CHAIN(1),\n    .C_CLKFBOUT_MULT_F(4.000),\n    .C_DIVCLK_DIVIDE(1),\n    .C_CLKOUT0_DIVIDE_F(12.000),\n    .C_CLK_INPUT_FREQ_HZ(300000000),\n    .C_ENABLE_CLK_DIVIDER(0),\n    .C_USE_EXT_BSCAN(1),\n    .C_USE_STARTUP_CLK(0),\n    .C_EN_BSCANID_VEC(0),\n    .C_TWO_PRIM_MODE(0),\n    .C_USER_SCAN_CHAIN1(1),\n    .C_BSCANID(76546592),\n    .C_BSCAN_MODE(0),\n    .C_BSCAN_MODE_WITH_CORE(0),\n    .C_NUM_BSCAN_MASTER_PORTS(0)\n  ) inst (\n    .sl_iport0_o(),\n    .sl_iport1_o(),\n    .sl_iport2_o(),\n    .sl_iport3_o(),\n    .sl_iport4_o(),\n    .sl_iport5_o(),\n    .sl_iport6_o(),\n    .sl_iport7_o(),\n    .sl_iport8_o(),\n    .sl_iport9_o(),\n    .sl_iport10_o(),\n    .sl_iport11_o(),\n    .sl_iport12_o(),\n    .sl_iport13_o(),\n    .sl_iport14_o(),\n    .sl_iport15_o(),\n    .sl_iport16_o(),\n    .sl_iport17_o(),\n    .sl_iport18_o(),\n    .sl_iport19_o(),\n    .sl_iport20_o(),\n    .sl_iport21_o(),\n    .sl_iport22_o(),\n    .sl_iport23_o(),\n    .sl_iport24_o(),\n    .sl_iport25_o(),\n    .sl_iport26_o(),\n    .sl_iport27_o(),\n    .sl_iport28_o(),\n    .sl_iport29_o(),\n    .sl_iport30_o(),\n    .sl_iport31_o(),\n    .sl_iport32_o(),\n    .sl_iport33_o(),\n    .sl_iport34_o(),\n    .sl_iport35_o(),\n    .sl_iport36_o(),\n    .sl_iport37_o(),\n    .sl_iport38_o(),\n    .sl_iport39_o(),\n    .sl_iport40_o(),\n    .sl_iport41_o(),\n    .sl_iport42_o(),\n    .sl_iport43_o(),\n    .sl_iport44_o(),\n    .sl_iport45_o(),\n    .sl_iport46_o(),\n    .sl_iport47_o(),\n    .sl_iport48_o(),\n    .sl_iport49_o(),\n    .sl_iport50_o(),\n    .sl_iport51_o(),\n    .sl_iport52_o(),\n    .sl_iport53_o(),\n    .sl_iport54_o(),\n    .sl_iport55_o(),\n    .sl_iport56_o(),\n    .sl_iport57_o(),\n    .sl_iport58_o(),\n    .sl_iport59_o(),\n    .sl_iport60_o(),\n    .sl_iport61_o(),\n    .sl_iport62_o(),\n    .sl_iport63_o(),\n    .sl_iport64_o(),\n    .sl_iport65_o(),\n    .sl_iport66_o(),\n    .sl_iport67_o(),\n    .sl_iport68_o(),\n    .sl_iport69_o(),\n    .sl_iport70_o(),\n    .sl_iport71_o(),\n    .sl_iport72_o(),\n    .sl_iport73_o(),\n    .sl_iport74_o(),\n    .sl_iport75_o(),\n    .sl_iport76_o(),\n    .sl_iport77_o(),\n    .sl_iport78_o(),\n    .sl_iport79_o(),\n    .sl_iport80_o(),\n    .sl_iport81_o(),\n    .sl_iport82_o(),\n    .sl_iport83_o(),\n    .sl_iport84_o(),\n    .sl_iport85_o(),\n    .sl_iport86_o(),\n    .sl_iport87_o(),\n    .sl_iport88_o(),\n    .sl_iport89_o(),\n    .sl_iport90_o(),\n    .sl_iport91_o(),\n    .sl_iport92_o(),\n    .sl_iport93_o(),\n    .sl_iport94_o(),\n    .sl_iport95_o(),\n    .sl_iport96_o(),\n    .sl_iport97_o(),\n    .sl_iport98_o(),\n    .sl_iport99_o(),\n    .sl_iport100_o(),\n    .sl_iport101_o(),\n    .sl_iport102_o(),\n    .sl_iport103_o(),\n    .sl_iport104_o(),\n    .sl_iport105_o(),\n    .sl_iport106_o(),\n    .sl_iport107_o(),\n    .sl_iport108_o(),\n    .sl_iport109_o(),\n    .sl_iport110_o(),\n    .sl_iport111_o(),\n    .sl_iport112_o(),\n    .sl_iport113_o(),\n    .sl_iport114_o(),\n    .sl_iport115_o(),\n    .sl_iport116_o(),\n    .sl_iport117_o(),\n    .sl_iport118_o(),\n    .sl_iport119_o(),\n    .sl_iport120_o(),\n    .sl_iport121_o(),\n    .sl_iport122_o(),\n    .sl_iport123_o(),\n    .sl_iport124_o(),\n    .sl_iport125_o(),\n    .sl_iport126_o(),\n    .sl_iport127_o(),\n    .sl_iport128_o(),\n    .sl_iport129_o(),\n    .sl_iport130_o(),\n    .sl_iport131_o(),\n    .sl_iport132_o(),\n    .sl_iport133_o(),\n    .sl_iport134_o(),\n    .sl_iport135_o(),\n    .sl_iport136_o(),\n    .sl_iport137_o(),\n    .sl_iport138_o(),\n    .sl_iport139_o(),\n    .sl_iport140_o(),\n    .sl_iport141_o(),\n    .sl_iport142_o(),\n    .sl_iport143_o(),\n    .sl_iport144_o(),\n    .sl_iport145_o(),\n    .sl_iport146_o(),\n    .sl_iport147_o(),\n    .sl_iport148_o(),\n    .sl_iport149_o(),\n    .sl_iport150_o(),\n    .sl_iport151_o(),\n    .sl_iport152_o(),\n    .sl_iport153_o(),\n    .sl_iport154_o(),\n    .sl_iport155_o(),\n    .sl_iport156_o(),\n    .sl_iport157_o(),\n    .sl_iport158_o(),\n    .sl_iport159_o(),\n    .sl_iport160_o(),\n    .sl_iport161_o(),\n    .sl_iport162_o(),\n    .sl_iport163_o(),\n    .sl_iport164_o(),\n    .sl_iport165_o(),\n    .sl_iport166_o(),\n    .sl_iport167_o(),\n    .sl_iport168_o(),\n    .sl_iport169_o(),\n    .sl_iport170_o(),\n    .sl_iport171_o(),\n    .sl_iport172_o(),\n    .sl_iport173_o(),\n    .sl_iport174_o(),\n    .sl_iport175_o(),\n    .sl_iport176_o(),\n    .sl_iport177_o(),\n    .sl_iport178_o(),\n    .sl_iport179_o(),\n    .sl_iport180_o(),\n    .sl_iport181_o(),\n    .sl_iport182_o(),\n    .sl_iport183_o(),\n    .sl_iport184_o(),\n    .sl_iport185_o(),\n    .sl_iport186_o(),\n    .sl_iport187_o(),\n    .sl_iport188_o(),\n    .sl_iport189_o(),\n    .sl_iport190_o(),\n    .sl_iport191_o(),\n    .sl_iport192_o(),\n    .sl_iport193_o(),\n    .sl_iport194_o(),\n    .sl_iport195_o(),\n    .sl_iport196_o(),\n    .sl_iport197_o(),\n    .sl_iport198_o(),\n    .sl_iport199_o(),\n    .sl_iport200_o(),\n    .sl_iport201_o(),\n    .sl_iport202_o(),\n    .sl_iport203_o(),\n    .sl_iport204_o(),\n    .sl_iport205_o(),\n    .sl_iport206_o(),\n    .sl_iport207_o(),\n    .sl_iport208_o(),\n    .sl_iport209_o(),\n    .sl_iport210_o(),\n    .sl_iport211_o(),\n    .sl_iport212_o(),\n    .sl_iport213_o(),\n    .sl_iport214_o(),\n    .sl_iport215_o(),\n    .sl_iport216_o(),\n    .sl_iport217_o(),\n    .sl_iport218_o(),\n    .sl_iport219_o(),\n    .sl_iport220_o(),\n    .sl_iport221_o(),\n    .sl_iport222_o(),\n    .sl_iport223_o(),\n    .sl_iport224_o(),\n    .sl_iport225_o(),\n    .sl_iport226_o(),\n    .sl_iport227_o(),\n    .sl_iport228_o(),\n    .sl_iport229_o(),\n    .sl_iport230_o(),\n    .sl_iport231_o(),\n    .sl_iport232_o(),\n    .sl_iport233_o(),\n    .sl_iport234_o(),\n    .sl_iport235_o(),\n    .sl_iport236_o(),\n    .sl_iport237_o(),\n    .sl_iport238_o(),\n    .sl_iport239_o(),\n    .sl_iport240_o(),\n    .sl_iport241_o(),\n    .sl_iport242_o(),\n    .sl_iport243_o(),\n    .sl_iport244_o(),\n    .sl_iport245_o(),\n    .sl_iport246_o(),\n    .sl_iport247_o(),\n    .sl_iport248_o(),\n    .sl_iport249_o(),\n    .sl_iport250_o(),\n    .sl_iport251_o(),\n    .sl_iport252_o(),\n    .sl_iport253_o(),\n    .sl_iport254_o(),\n    .sl_iport255_o(),\n    .sl_oport0_i(1'B0),\n    .sl_oport1_i(1'B0),\n    .sl_oport2_i(1'B0),\n    .sl_oport3_i(1'B0),\n    .sl_oport4_i(1'B0),\n    .sl_oport5_i(1'B0),\n    .sl_oport6_i(1'B0),\n    .sl_oport7_i(1'B0),\n    .sl_oport8_i(1'B0),\n    .sl_oport9_i(1'B0),\n    .sl_oport10_i(1'B0),\n    .sl_oport11_i(1'B0),\n    .sl_oport12_i(1'B0),\n    .sl_oport13_i(1'B0),\n    .sl_oport14_i(1'B0),\n    .sl_oport15_i(1'B0),\n    .sl_oport16_i(1'B0),\n    .sl_oport17_i(1'B0),\n    .sl_oport18_i(1'B0),\n    .sl_oport19_i(1'B0),\n    .sl_oport20_i(1'B0),\n    .sl_oport21_i(1'B0),\n    .sl_oport22_i(1'B0),\n    .sl_oport23_i(1'B0),\n    .sl_oport24_i(1'B0),\n    .sl_oport25_i(1'B0),\n    .sl_oport26_i(1'B0),\n    .sl_oport27_i(1'B0),\n    .sl_oport28_i(1'B0),\n    .sl_oport29_i(1'B0),\n    .sl_oport30_i(1'B0),\n    .sl_oport31_i(1'B0),\n    .sl_oport32_i(1'B0),\n    .sl_oport33_i(1'B0),\n    .sl_oport34_i(1'B0),\n    .sl_oport35_i(1'B0),\n    .sl_oport36_i(1'B0),\n    .sl_oport37_i(1'B0),\n    .sl_oport38_i(1'B0),\n    .sl_oport39_i(1'B0),\n    .sl_oport40_i(1'B0),\n    .sl_oport41_i(1'B0),\n    .sl_oport42_i(1'B0),\n    .sl_oport43_i(1'B0),\n    .sl_oport44_i(1'B0),\n    .sl_oport45_i(1'B0),\n    .sl_oport46_i(1'B0),\n    .sl_oport47_i(1'B0),\n    .sl_oport48_i(1'B0),\n    .sl_oport49_i(1'B0),\n    .sl_oport50_i(1'B0),\n    .sl_oport51_i(1'B0),\n    .sl_oport52_i(1'B0),\n    .sl_oport53_i(1'B0),\n    .sl_oport54_i(1'B0),\n    .sl_oport55_i(1'B0),\n    .sl_oport56_i(1'B0),\n    .sl_oport57_i(1'B0),\n    .sl_oport58_i(1'B0),\n    .sl_oport59_i(1'B0),\n    .sl_oport60_i(1'B0),\n    .sl_oport61_i(1'B0),\n    .sl_oport62_i(1'B0),\n    .sl_oport63_i(1'B0),\n    .sl_oport64_i(1'B0),\n    .sl_oport65_i(1'B0),\n    .sl_oport66_i(1'B0),\n    .sl_oport67_i(1'B0),\n    .sl_oport68_i(1'B0),\n    .sl_oport69_i(1'B0),\n    .sl_oport70_i(1'B0),\n    .sl_oport71_i(1'B0),\n    .sl_oport72_i(1'B0),\n    .sl_oport73_i(1'B0),\n    .sl_oport74_i(1'B0),\n    .sl_oport75_i(1'B0),\n    .sl_oport76_i(1'B0),\n    .sl_oport77_i(1'B0),\n    .sl_oport78_i(1'B0),\n    .sl_oport79_i(1'B0),\n    .sl_oport80_i(1'B0),\n    .sl_oport81_i(1'B0),\n    .sl_oport82_i(1'B0),\n    .sl_oport83_i(1'B0),\n    .sl_oport84_i(1'B0),\n    .sl_oport85_i(1'B0),\n    .sl_oport86_i(1'B0),\n    .sl_oport87_i(1'B0),\n    .sl_oport88_i(1'B0),\n    .sl_oport89_i(1'B0),\n    .sl_oport90_i(1'B0),\n    .sl_oport91_i(1'B0),\n    .sl_oport92_i(1'B0),\n    .sl_oport93_i(1'B0),\n    .sl_oport94_i(1'B0),\n    .sl_oport95_i(1'B0),\n    .sl_oport96_i(1'B0),\n    .sl_oport97_i(1'B0),\n    .sl_oport98_i(1'B0),\n    .sl_oport99_i(1'B0),\n    .sl_oport100_i(1'B0),\n    .sl_oport101_i(1'B0),\n    .sl_oport102_i(1'B0),\n    .sl_oport103_i(1'B0),\n    .sl_oport104_i(1'B0),\n    .sl_oport105_i(1'B0),\n    .sl_oport106_i(1'B0),\n    .sl_oport107_i(1'B0),\n    .sl_oport108_i(1'B0),\n    .sl_oport109_i(1'B0),\n    .sl_oport110_i(1'B0),\n    .sl_oport111_i(1'B0),\n    .sl_oport112_i(1'B0),\n    .sl_oport113_i(1'B0),\n    .sl_oport114_i(1'B0),\n    .sl_oport115_i(1'B0),\n    .sl_oport116_i(1'B0),\n    .sl_oport117_i(1'B0),\n    .sl_oport118_i(1'B0),\n    .sl_oport119_i(1'B0),\n    .sl_oport120_i(1'B0),\n    .sl_oport121_i(1'B0),\n    .sl_oport122_i(1'B0),\n    .sl_oport123_i(1'B0),\n    .sl_oport124_i(1'B0),\n    .sl_oport125_i(1'B0),\n    .sl_oport126_i(1'B0),\n    .sl_oport127_i(1'B0),\n    .sl_oport128_i(1'B0),\n    .sl_oport129_i(1'B0),\n    .sl_oport130_i(1'B0),\n    .sl_oport131_i(1'B0),\n    .sl_oport132_i(1'B0),\n    .sl_oport133_i(1'B0),\n    .sl_oport134_i(1'B0),\n    .sl_oport135_i(1'B0),\n    .sl_oport136_i(1'B0),\n    .sl_oport137_i(1'B0),\n    .sl_oport138_i(1'B0),\n    .sl_oport139_i(1'B0),\n    .sl_oport140_i(1'B0),\n    .sl_oport141_i(1'B0),\n    .sl_oport142_i(1'B0),\n    .sl_oport143_i(1'B0),\n    .sl_oport144_i(1'B0),\n    .sl_oport145_i(1'B0),\n    .sl_oport146_i(1'B0),\n    .sl_oport147_i(1'B0),\n    .sl_oport148_i(1'B0),\n    .sl_oport149_i(1'B0),\n    .sl_oport150_i(1'B0),\n    .sl_oport151_i(1'B0),\n    .sl_oport152_i(1'B0),\n    .sl_oport153_i(1'B0),\n    .sl_oport154_i(1'B0),\n    .sl_oport155_i(1'B0),\n    .sl_oport156_i(1'B0),\n    .sl_oport157_i(1'B0),\n    .sl_oport158_i(1'B0),\n    .sl_oport159_i(1'B0),\n    .sl_oport160_i(1'B0),\n    .sl_oport161_i(1'B0),\n    .sl_oport162_i(1'B0),\n    .sl_oport163_i(1'B0),\n    .sl_oport164_i(1'B0),\n    .sl_oport165_i(1'B0),\n    .sl_oport166_i(1'B0),\n    .sl_oport167_i(1'B0),\n    .sl_oport168_i(1'B0),\n    .sl_oport169_i(1'B0),\n    .sl_oport170_i(1'B0),\n    .sl_oport171_i(1'B0),\n    .sl_oport172_i(1'B0),\n    .sl_oport173_i(1'B0),\n    .sl_oport174_i(1'B0),\n    .sl_oport175_i(1'B0),\n    .sl_oport176_i(1'B0),\n    .sl_oport177_i(1'B0),\n    .sl_oport178_i(1'B0),\n    .sl_oport179_i(1'B0),\n    .sl_oport180_i(1'B0),\n    .sl_oport181_i(1'B0),\n    .sl_oport182_i(1'B0),\n    .sl_oport183_i(1'B0),\n    .sl_oport184_i(1'B0),\n    .sl_oport185_i(1'B0),\n    .sl_oport186_i(1'B0),\n    .sl_oport187_i(1'B0),\n    .sl_oport188_i(1'B0),\n    .sl_oport189_i(1'B0),\n    .sl_oport190_i(1'B0),\n    .sl_oport191_i(1'B0),\n    .sl_oport192_i(1'B0),\n    .sl_oport193_i(1'B0),\n    .sl_oport194_i(1'B0),\n    .sl_oport195_i(1'B0),\n    .sl_oport196_i(1'B0),\n    .sl_oport197_i(1'B0),\n    .sl_oport198_i(1'B0),\n    .sl_oport199_i(1'B0),\n    .sl_oport200_i(1'B0),\n    .sl_oport201_i(1'B0),\n    .sl_oport202_i(1'B0),\n    .sl_oport203_i(1'B0),\n    .sl_oport204_i(1'B0),\n    .sl_oport205_i(1'B0),\n    .sl_oport206_i(1'B0),\n    .sl_oport207_i(1'B0),\n    .sl_oport208_i(1'B0),\n    .sl_oport209_i(1'B0),\n    .sl_oport210_i(1'B0),\n    .sl_oport211_i(1'B0),\n    .sl_oport212_i(1'B0),\n    .sl_oport213_i(1'B0),\n    .sl_oport214_i(1'B0),\n    .sl_oport215_i(1'B0),\n    .sl_oport216_i(1'B0),\n    .sl_oport217_i(1'B0),\n    .sl_oport218_i(1'B0),\n    .sl_oport219_i(1'B0),\n    .sl_oport220_i(1'B0),\n    .sl_oport221_i(1'B0),\n    .sl_oport222_i(1'B0),\n    .sl_oport223_i(1'B0),\n    .sl_oport224_i(1'B0),\n    .sl_oport225_i(1'B0),\n    .sl_oport226_i(1'B0),\n    .sl_oport227_i(1'B0),\n    .sl_oport228_i(1'B0),\n    .sl_oport229_i(1'B0),\n    .sl_oport230_i(1'B0),\n    .sl_oport231_i(1'B0),\n    .sl_oport232_i(1'B0),\n    .sl_oport233_i(1'B0),\n    .sl_oport234_i(1'B0),\n    .sl_oport235_i(1'B0),\n    .sl_oport236_i(1'B0),\n    .sl_oport237_i(1'B0),\n    .sl_oport238_i(1'B0),\n    .sl_oport239_i(1'B0),\n    .sl_oport240_i(1'B0),\n    .sl_oport241_i(1'B0),\n    .sl_oport242_i(1'B0),\n    .sl_oport243_i(1'B0),\n    .sl_oport244_i(1'B0),\n    .sl_oport245_i(1'B0),\n    .sl_oport246_i(1'B0),\n    .sl_oport247_i(1'B0),\n    .sl_oport248_i(1'B0),\n    .sl_oport249_i(1'B0),\n    .sl_oport250_i(1'B0),\n    .sl_oport251_i(1'B0),\n    .sl_oport252_i(1'B0),\n    .sl_oport253_i(1'B0),\n    .sl_oport254_i(1'B0),\n    .sl_oport255_i(1'B0),\n    .update_0(),\n    .capture_0(),\n    .reset_0(),\n    .runtest_0(),\n    .tms_0(),\n    .tck_0(),\n    .tdi_0(),\n    .sel_0(),\n    .shift_0(),\n    .drck_0(),\n    .tdo_0(1'B0),\n    .update_1(),\n    .capture_1(),\n    .reset_1(),\n    .runtest_1(),\n    .tms_1(),\n    .tck_1(),\n    .tdi_1(),\n    .sel_1(),\n    .shift_1(),\n    .drck_1(),\n    .tdo_1(1'B0),\n    .update_2(),\n    .capture_2(),\n    .reset_2(),\n    .runtest_2(),\n    .tms_2(),\n    .tck_2(),\n    .tdi_2(),\n    .sel_2(),\n    .shift_2(),\n    .drck_2(),\n    .tdo_2(1'B0),\n    .update_3(),\n    .capture_3(),\n    .reset_3(),\n    .runtest_3(),\n    .tms_3(),\n    .tck_3(),\n    .tdi_3(),\n    .sel_3(),\n    .shift_3(),\n    .drck_3(),\n    .tdo_3(1'B0),\n    .update_4(),\n    .capture_4(),\n    .reset_4(),\n    .runtest_4(),\n    .tms_4(),\n    .tck_4(),\n    .tdi_4(),\n    .sel_4(),\n    .shift_4(),\n    .drck_4(),\n    .tdo_4(1'B0),\n    .update_5(),\n    .capture_5(),\n    .reset_5(),\n    .runtest_5(),\n    .tms_5(),\n    .tck_5(),\n    .tdi_5(),\n    .sel_5(),\n    .shift_5(),\n    .drck_5(),\n    .tdo_5(1'B0),\n    .update_6(),\n    .capture_6(),\n    .reset_6(),\n    .runtest_6(),\n    .tms_6(),\n    .tck_6(),\n    .tdi_6(),\n    .sel_6(),\n    .shift_6(),\n    .drck_6(),\n    .tdo_6(1'B0),\n    .update_7(),\n    .capture_7(),\n    .reset_7(),\n    .runtest_7(),\n    .tms_7(),\n    .tck_7(),\n    .tdi_7(),\n    .sel_7(),\n    .shift_7(),\n    .drck_7(),\n    .tdo_7(1'B0),\n    .update_8(),\n    .capture_8(),\n    .reset_8(),\n    .runtest_8(),\n    .tms_8(),\n    .tck_8(),\n    .tdi_8(),\n    .sel_8(),\n    .shift_8(),\n    .drck_8(),\n    .tdo_8(1'B0),\n    .update_9(),\n    .capture_9(),\n    .reset_9(),\n    .runtest_9(),\n    .tms_9(),\n    .tck_9(),\n    .tdi_9(),\n    .sel_9(),\n    .shift_9(),\n    .drck_9(),\n    .tdo_9(1'B0),\n    .update_10(),\n    .capture_10(),\n    .reset_10(),\n    .runtest_10(),\n    .tms_10(),\n    .tck_10(),\n    .tdi_10(),\n    .sel_10(),\n    .shift_10(),\n    .drck_10(),\n    .tdo_10(1'B0),\n    .update_11(),\n    .capture_11(),\n    .reset_11(),\n    .runtest_11(),\n    .tms_11(),\n    .tck_11(),\n    .tdi_11(),\n    .sel_11(),\n    .shift_11(),\n    .drck_11(),\n    .tdo_11(1'B0),\n    .update_12(),\n    .capture_12(),\n    .reset_12(),\n    .runtest_12(),\n    .tms_12(),\n    .tck_12(),\n    .tdi_12(),\n    .sel_12(),\n    .shift_12(),\n    .drck_12(),\n    .tdo_12(1'B0),\n    .update_13(),\n    .capture_13(),\n    .reset_13(),\n    .runtest_13(),\n    .tms_13(),\n    .tck_13(),\n    .tdi_13(),\n    .sel_13(),\n    .shift_13(),\n    .drck_13(),\n    .tdo_13(1'B0),\n    .update_14(),\n    .capture_14(),\n    .reset_14(),\n    .runtest_14(),\n    .tms_14(),\n    .tck_14(),\n    .tdi_14(),\n    .sel_14(),\n    .shift_14(),\n    .drck_14(),\n    .tdo_14(1'B0),\n    .update_15(),\n    .capture_15(),\n    .reset_15(),\n    .runtest_15(),\n    .tms_15(),\n    .tck_15(),\n    .tdi_15(),\n    .sel_15(),\n    .shift_15(),\n    .drck_15(),\n    .tdo_15(1'B0),\n    .bscanid_en_0(),\n    .bscanid_en_1(),\n    .bscanid_en_2(),\n    .bscanid_en_3(),\n    .bscanid_en_4(),\n    .bscanid_en_5(),\n    .bscanid_en_6(),\n    .bscanid_en_7(),\n    .bscanid_en_8(),\n    .bscanid_en_9(),\n    .bscanid_en_10(),\n    .bscanid_en_11(),\n    .bscanid_en_12(),\n    .bscanid_en_13(),\n    .bscanid_en_14(),\n    .bscanid_en_15(),\n    .bscanid_0(32'B0),\n    .bscanid_1(32'B0),\n    .bscanid_2(32'B0),\n    .bscanid_3(32'B0),\n    .bscanid_4(32'B0),\n    .bscanid_5(32'B0),\n    .bscanid_6(32'B0),\n    .bscanid_7(32'B0),\n    .bscanid_8(32'B0),\n    .bscanid_9(32'B0),\n    .bscanid_10(32'B0),\n    .bscanid_11(32'B0),\n    .bscanid_12(32'B0),\n    .bscanid_13(32'B0),\n    .bscanid_14(32'B0),\n    .bscanid_15(32'B0),\n    .update(update),\n    .capture(capture),\n    .reset(reset),\n    .runtest(runtest),\n    .tck(tck),\n    .tms(tms),\n    .tdi(tdi),\n    .sel(sel),\n    .shift(shift),\n    .drck(drck),\n    .tdo(tdo),\n    .bscanid_en(bscanid_en),\n    .bscanid(),\n    .clk(clk)\n  );\nendmodule\n", "num_lines": 870}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\ngeSCzw9gYjFCv0Dn0YxOXxhH+GZFMePCQPK3AjT+zbjt1urPphGbRmSIP212qcXhU3u6qBayOOuP\nzGTUOznyYQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nOnCSRn8bnLy+eSxgkIEXKk5zY3JDppSX+6N3lQVX9PeSypgnQ/2z4GTpmoL+rdMoco6U9R4G1u4m\nE0xhKuM4ba9nEk7cLfAxOQqKqsWQrZaIEmzIr1ET+cp4jOMvYA/MsN4jh93kbuKcSDuJ8zN13DFX\nRemIkmekhFjPkyUS5qM=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nMSBAO7tnsBVh2XpVImbQvPkv1Ik+6Bw1D0e9n6H/Bw1mXnRXzm0RzPaEYAIFuluPbWglTrw4pQSr\nJI/DSdCg6087Xmb+Q5zKawFvuZahx4HgmrKxTL15lZwamiIpmu3LGyxaEH/VbYGM9Ky0jp5PyDKU\nJeskyx64XVUPlRklhMjIKCtYITsgROzqjs+d1jIc494zqnDADEz0msJP38WdzHgwLDQ0NamfpodX\nBUqMR71hgPx1Rvdt7HagUbkfyaG3/12LxFvpAblT7W0W6RKBFEFgFrxWRFaDw+jzj4jgl9g+sjY0\ncveJYAA4UpZJwPSDIWehjmS+mOinzlnl8UP7jw==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUtIiSU3lZ1iUKAuaJuT083jLC5QokBuxbJC/zVsWXf8ozOCIDAvtpSufF02lDCCaNNheB40dXQFS\nI8VBcTtdWzNr2vj/HmW17e10D6T6mqn/8t0HnWx9c3modRuXup0Too1mNTU5gTH+v3utogTO5ztm\nHbJZ/+5ov0tPkaeJufJl5L/RZAfLmRnRYybtx5bbc7XiGyWaVk6KunsaWtX5zJtVnMeUOkg0N8oL\nRBeyFp3tFqTN7ecNUp7zom6BjZ3fR6euRy36u1XviJsqBjcxzASI1k+bn2lDs3oEdXuMHoRvcuWL\nmmMddzjwWr43L7YoB/WBz/Tw7t6iYI5B6imPUA==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nAMZ17uwJyVzW4KyzjD/YjCrX2GlLIDwW9HSuEat97pn8ZQ7QpDPhFLNx09klp1fHQ8yb1KlxCqpm\nIjAljp4A5oQHWcBw/s+Xhtpin6GMDGjsmd5KmAD2J5DQmzqPazc0M8vNO+pGpCJogvWarX5XrP6U\n56l9vH5mfyPmbT/09Kw=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\noAGTk8IFmmwAT5eT+h5xMK7MsqYCJnsMll3rq17njNu6wbVX2TAoOlVC5DzNg9T5ce7gVnuLuFG/\nFgNSnTJx8TlbP73KxlDubmAVofR56G/yHzaJfJ0fwNhrfXm5AFgmFaKFPTKNkrG/qjdNuwUeA8p4\niHoj1zvPx50myVHXSpHLQ8n92DLWgMUX/57aPLbMHmYu/gsD0kHOuQ8Fr2Mi2DxufAvq1gzT0kc+\nlxSntoseL+X1HLSvmKpEkR/sjaz6P9omIzqKlmOhvLeTZVEZcUtukVN1HTrlol+4/pTFDztcz0tZ\nXqYZKVNB/igvn1iP/Fej8fpkaeJOrk1YgJZ6xw==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nHM0OWTHTT9qkiqicwldwQlaXCXhAavOkOLtzdsXybVEqcdGTuInS8Xvu2i7fjfGdnZjc+o4ZayFd\nadCXUGMQZ+7u79Rm71DMtV7WL4PMhXZmItLJgXQmNzajU211AuWse/CyD7Am9ZDJuQcIK0fcqZQI\nXVJU6sMESVWiSWdCuqkcQLSuSoBY7TVLmCDoTF9n7MlYfcxCkkK6d+2Xs/gjaWO59GZ3TbWhAQLc\n9hHL9YUJUTzZ8yPC8tX+DLS/YrniD3lBpquxXGcl1FxHKFTSpMG/6pTH+7Y5u1s29iqS/KYCCOfR\nPqg3ikxxR4ywBL+umX+Ijv+Hqgol6tBnCkWh/g==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nDQuK/YuairmUNmnTZFN/Tbbjjk202ciTMNZWiES7z/c8BYrmlnBses/x7XzAVxFxOTns+S6gcbxv\nlho3MoYQI3b1wxR93ymMpbFY2AAKqfTaYrt9nuBi+J66NUkNb4mO5Ysrmk/FyxUuVMw2JeKhCxVf\n1Lkw2weXEA2RSHrWxd8764IFSbBqKoKUTMuqLxHovRaQHDy/mOdyefGG7/6ywGbKjVTlE8lXVH8E\n8QodSYZ7p8uod81sVFzJL26a9Tqu+u2tOgD/WqMuxrio7zRkYYC5P+/FtxLC4GaIZ6LivaJuTLOF\nbkAMneaa5dlfamLnRyzDXUCJu/DFpJtH5s1eLQ==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nDL1JbuaDxIhP8ir0jAdx6nea42/rMQ2VXG8PZEGqMkgF/yLmK8+UcPNvmkEnUbVxq6WNxCUUYBOO\neroUXvKd3hB7aza+lE1PkczDRQpe4dZWQ8yHCUSbqj/KnUKU7sMHOSk5MiYcbBazdC+B/zdSxJsr\nsUmnOLgp/SqygmZW7/oDYMIYyOExEOrIPD4CH/xXZGlvuNs4OjdmaSus7kQp/iaUxQz03NGaMv3/\nEuIfORb3j+mQPwXwEBQhecy81p8ky3bmOS0LK+CPuz0LF3VVvrDnnXUSBCWa2WW6t7burmoHvgPV\noB2jrvwkS6dNjRJ7CoyGvV0N6d60kiD0LjZg6Q==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 2400)\n`pragma protect data_block\nNayj+Ml813fDniWORR2jtIBWLUnTKLU73quUTC0r5jwck/h8GoDq9XKw8BqI5v1J3nTgkNVm5atb\ncAw/VaO3NkhfBheJQbSR69Nrz/dOO5tggQHH5bhiVgkyJ10J0IJijCkqHTEM7eqAUpRB+C+swn77\n0UbAbjpA6iLxZtySLCkfu1IDmIuJVGQQu5gx5HhJOOS9sbBqYLpKFtMkq0ekmdT8uVsJas5Dn/rL\nFK6cI0u3hF6jx7C6EuRP9bts5JinWmopHabvdIuMWogq/jEOmvK/YWa2F6a22JfPI9md2SGv001Z\nNF3S+OFUqWLkWcQuQiK1EeStnUgfx0DKmP44Rh49vAuwvoCnEGtGPoJcuqCj8kkx2HperJBoPMXF\nbwOXyBsVw8smubJpJUklj/jkYQU7Mhn0+1DDK4kkK06W5VS0PwpcHI/NCpCrtst2FFbkesNH2SsO\n5KIGW+Cfb4QrEDe5XavyjtAdc7Kf/olEw1ZvNmIwyZXSdJcT54GFCi4KQPPRS9kiaadQLPQS/WUP\nwP3P3JdX9YvFC5Sp1yq2sPWuL1eMLRyNl339wIhus+/wM5aQSDi/pHmJmMEl1YLUa+mN6EenORTG\n5MU9xnSDDk5SD4ObbT9KWXjRTWogMOCapY1Tv1MWBzOTNzXGtVtAJBw4cxOHMG+OFF0yGvhE/AiV\nUJBEeJzP8L2Bj71c8RCxIViFz07rXhaFlBxMGxkdgTscOVxJtGiXqO970qc+E+YhnpZrgzpPog3A\nHIxK9BG2bcC2sSeQO+WCrtfMMdvVUNZHntYQpZozeGZF5OTZeeqs2I0PvZblmP7/srlzJ/JzetZ0\nCpTygxJF6W9HlXHv9qS2in1MDX5LvPjFtN0zKGyxUv4X8CFSqcYRW0lPxKh8dQ8KfIf1/+JRuMUW\nCO3I17UAoMQyc5PLA35Nis/x1CGOS2Zq5QgnlIBPpFv5JGoS0wKJ/bIyq0i0w+v4KWN5TrLYWJ84\nsMf45/+/nnmUoNq90k8SrWlnr9pxaqXZeklZOtEGejWc0oYa3+O2lYV0522Cm+XAuCiLIx1oRyxa\n+u6HnsKXvR9DGb1osgt9gANalMh//k8N88W7tvMLcXwdkFi3uvBg/oZZeRm+o8p5swkqfDh2gQuZ\nGJ1QE8KWN8hTZ9fEsScunk4GbuTk3dg05a1sMGm1gkRzTfiEVCzyn5Hi3pFpbikjAO7g/FLU6yiZ\npKzI2Crm4XPWRCfhwxycS8r2s63JspfJUZBW7tfCcbmQHYqHgxL3ZiEIV4N4tCF6rLQe8eu8xVI4\n/ReaCvAsFB9k7r6h7vh2b/kor3j4v+vAAZs3NBd5vlKFfHc3a2phzTdGn9/IodWpqPp66h+D0hMB\n8NQHJ3785F0Znfee4XxCQdXvwh03Pq+vWOHfhxdV+GL/oYI5/3eX0cZlwNXNhgrBE/jjCvh+/qf+\nEuYKKMASHjIYzBihs/pCIBjKCya9eF6CKxRfp3KTjZ2nu0k/P00aR1alNLtPJR6SD3wEBMa7yNgY\nByaV1EQovQeu24Klh9zavCXFUHc3h3j8MqHxZrNfI/eUyIDoEuURBHymJZ13GIYA+mWIFdrXIC84\nSlX5spcjNcB+mHif2EzCB6nJP3AE9aq8cpOJcQjhkcPZHkg2t9l5F5EupuAFUvvfcTXN/y6F3qIr\nThqLyFGwSiGzZX0AwRaNpyXuZKQsNz1WTzj1BjvDSTF1//OlAgzx0F1UZOuh9Hzv4+IBl0yGCHiR\noGXeQvMTSxI1D0BcFoc61ga1nbv3+QY2aYafMEJ+LKq2sz3mGk0Vpzo+swUVCYeveAb11ugkLVq9\nRa5FHeyN5v+RwxysgCDPo+jBUyzguryY6OBJBtBUXJV3Vrg8TEC1JNfIuiaQGmXiWvUj7VD3fgFP\nA/Pax3F+Unn9dJaEhfgG23dLGZyo/H32CTtiWZfkWBJV8/W3g040xdKdNl+Y7sBtjuGt0IdS8lWJ\nbomc8CybMXpVp9SQkhVlf4135WYYZuozj6Kt0dv581TbcnOPMEkTrRnU/XCQOVj9mHD8kDE8BGPs\nu1WPZBZQ1Tfgb5SDwQQf3XYTIQNAnDzjLrEPaxy7I36CFdPTpJXR+DrTmbYH416q/LusHMxfzhkE\nw+OkHqm6czWhunOkfPBoECoA9j609E2s6JDyqqdyNGGw3KsGIu3zyudgD+AeIlbr5wvld3VhQu+k\nGbD1GKPT9sOuQylU6aG0R75sAjP0/RSbLUhGUdAL1NeNa2Q5utBg4b7xY2znf8k43uQuH9gDftQK\nMoCj+4M/kY5vFOehA+mgPmocoo8+ta7JVcwiLjJPyYN/N7RIRvu0bpPfTeQM+6DijB5NSetCHZeW\nKLrP7l1+niGT/aEUEZej5w42fhW5sZHSiMRrLyLeDxPtaeUE82Q8OzcJqmXqsrFMkgyVYOS6vWRE\np8+5qxoxSzeQ36exOktW+E2/pJPFVJYv608U/e/KsJ18RpOpuwdPQeazasQl0zwh9u34LrhV6Hgs\nG8DKy0o62/rCo+JVEb1RdF37hXvTDGFF//rlcyBQgVtwCOJFFL5geugUbu5A/8AzBEN9Pzw0vxPV\nfUaRNNckCcVybD5F7BZ3ielbt42QOneOK6+07rP2GQq6wu4Kocbpi5WXkAwDwn9iEsJT6Vh3Xz9A\nGjEIelxMlGde1Ett9oxHhKcMYEnPyv4evAmG7EErwlTCQd+vp8tPPTmVvXbIJEpz4ViA5GiW8eTI\nk/BkHd7IGq64iYXdddJ63IxopIFrccFbADHVy2LXr73bfFWYkRzvShUlQXRs2nK8iLqkmlEeNa8u\nxaG3JQj0CYQCzTlqrKFs7AK8b8BwqaXmZ3FB9Xfj65H3mkW01gIq4i7sdVBBe4FgjsQAPdA+QPyP\nFymbOZEQQPblH3qHCFfiQ9DDi/zDZi26sar4BjLeoS6GuI2juEmSKZLMcHezPShGjMq7TDo25lD6\nlTlVWv5FmEIE4aI6UTNu4lJ3xl7a4lWJea95qzcitsplCEQA3mhp4zu9euRzSrneC01njKmDnrPH\nmqzSlSiWOcwitRn6BFaIcXktL6gU0l0wbOKHkv4u6Wd4kbpRfHuZGrrcUU9JHlIQn9e7Rhx3a8Le\nWewZ4FHJqc4gDvS+d8JPbCOb0K5VOINAjyn78G8320oCOfCyv3IKlkmyNHvqFcKzpNFcaza/1v/w\nwP46e8ZI\n`pragma protect end_protected\n", "num_lines": 126}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:lut_buffer:2.0\n// IP Revision: 0\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_a493_lut_buffer_0 (\n  tdi_i,\n  tms_i,\n  tck_i,\n  drck_i,\n  sel_i,\n  shift_i,\n  update_i,\n  capture_i,\n  runtest_i,\n  reset_i,\n  bscanid_en_i,\n  tdo_o,\n  tdi_o,\n  tms_o,\n  tck_o,\n  drck_o,\n  sel_o,\n  shift_o,\n  update_o,\n  capture_o,\n  runtest_o,\n  reset_o,\n  bscanid_en_o,\n  tdo_i\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDI\" *)\ninput wire tdi_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TMS\" *)\ninput wire tms_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TCK\" *)\ninput wire tck_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan DRCK\" *)\ninput wire drck_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SEL\" *)\ninput wire sel_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SHIFT\" *)\ninput wire shift_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan UPDATE\" *)\ninput wire update_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan CAPTURE\" *)\ninput wire capture_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RUNTEST\" *)\ninput wire runtest_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RESET\" *)\ninput wire reset_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan BSCANID_EN\" *)\ninput wire bscanid_en_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDO\" *)\noutput wire tdo_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TDI\" *)\noutput wire tdi_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TMS\" *)\noutput wire tms_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TCK\" *)\noutput wire tck_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan DRCK\" *)\noutput wire drck_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan SEL\" *)\noutput wire sel_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan SHIFT\" *)\noutput wire shift_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan UPDATE\" *)\noutput wire update_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan CAPTURE\" *)\noutput wire capture_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan RUNTEST\" *)\noutput wire runtest_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan RESET\" *)\noutput wire reset_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan BSCANID_EN\" *)\noutput wire bscanid_en_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TDO\" *)\ninput wire tdo_i;\n\n  lut_buffer_v2_0_0_lut_buffer #(\n    .C_EN_BSCANID_VEC(0)\n  ) inst (\n    .tdi_i(tdi_i),\n    .tms_i(tms_i),\n    .tck_i(tck_i),\n    .drck_i(drck_i),\n    .sel_i(sel_i),\n    .shift_i(shift_i),\n    .update_i(update_i),\n    .capture_i(capture_i),\n    .runtest_i(runtest_i),\n    .reset_i(reset_i),\n    .bscanid_en_i(bscanid_en_i),\n    .tdo_o(tdo_o),\n    .bscanid_o(),\n    .tdi_o(tdi_o),\n    .tms_o(tms_o),\n    .tck_o(tck_o),\n    .drck_o(drck_o),\n    .sel_o(sel_o),\n    .shift_o(shift_o),\n    .update_o(update_o),\n    .capture_o(capture_o),\n    .runtest_o(runtest_o),\n    .reset_o(reset_o),\n    .bscanid_en_o(bscanid_en_o),\n    .tdo_i(tdo_i),\n    .bscanid_i(32'B0)\n  );\nendmodule\n", "num_lines": 163}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:lut_buffer:2.0\n// IP Revision: 0\n\n(* X_CORE_INFO = \"lut_buffer_v2_0_0_lut_buffer,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"bd_a493_lut_buffer_0,lut_buffer_v2_0_0_lut_buffer,{}\" *)\n(* CORE_GENERATION_INFO = \"bd_a493_lut_buffer_0,lut_buffer_v2_0_0_lut_buffer,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lut_buffer,x_ipVersion=2.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_BSCANID_VEC=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_a493_lut_buffer_0 (\n  tdi_i,\n  tms_i,\n  tck_i,\n  drck_i,\n  sel_i,\n  shift_i,\n  update_i,\n  capture_i,\n  runtest_i,\n  reset_i,\n  bscanid_en_i,\n  tdo_o,\n  tdi_o,\n  tms_o,\n  tck_o,\n  drck_o,\n  sel_o,\n  shift_o,\n  update_o,\n  capture_o,\n  runtest_o,\n  reset_o,\n  bscanid_en_o,\n  tdo_i\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDI\" *)\ninput wire tdi_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TMS\" *)\ninput wire tms_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TCK\" *)\ninput wire tck_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan DRCK\" *)\ninput wire drck_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SEL\" *)\ninput wire sel_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SHIFT\" *)\ninput wire shift_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan UPDATE\" *)\ninput wire update_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan CAPTURE\" *)\ninput wire capture_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RUNTEST\" *)\ninput wire runtest_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RESET\" *)\ninput wire reset_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan BSCANID_EN\" *)\ninput wire bscanid_en_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDO\" *)\noutput wire tdo_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TDI\" *)\noutput wire tdi_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TMS\" *)\noutput wire tms_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TCK\" *)\noutput wire tck_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan DRCK\" *)\noutput wire drck_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan SEL\" *)\noutput wire sel_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan SHIFT\" *)\noutput wire shift_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan UPDATE\" *)\noutput wire update_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan CAPTURE\" *)\noutput wire capture_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan RUNTEST\" *)\noutput wire runtest_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan RESET\" *)\noutput wire reset_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan BSCANID_EN\" *)\noutput wire bscanid_en_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TDO\" *)\ninput wire tdo_i;\n\n  lut_buffer_v2_0_0_lut_buffer #(\n    .C_EN_BSCANID_VEC(0)\n  ) inst (\n    .tdi_i(tdi_i),\n    .tms_i(tms_i),\n    .tck_i(tck_i),\n    .drck_i(drck_i),\n    .sel_i(sel_i),\n    .shift_i(shift_i),\n    .update_i(update_i),\n    .capture_i(capture_i),\n    .runtest_i(runtest_i),\n    .reset_i(reset_i),\n    .bscanid_en_i(bscanid_en_i),\n    .tdo_o(tdo_o),\n    .bscanid_o(),\n    .tdi_o(tdi_o),\n    .tms_o(tms_o),\n    .tck_o(tck_o),\n    .drck_o(drck_o),\n    .sel_o(sel_o),\n    .shift_o(shift_o),\n    .update_o(update_o),\n    .capture_o(capture_o),\n    .runtest_o(runtest_o),\n    .reset_o(reset_o),\n    .bscanid_en_o(bscanid_en_o),\n    .tdo_i(tdo_i),\n    .bscanid_i(32'B0)\n  );\nendmodule\n", "num_lines": 164}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_a493.bd\n//Design : bd_a493\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_a493,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_a493,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}\" *) (* HW_HANDOFF = \"cl_debug_bridge.hwdef\" *) \nmodule bd_a493\n   (S_BSCAN_bscanid_en,\n    S_BSCAN_capture,\n    S_BSCAN_drck,\n    S_BSCAN_reset,\n    S_BSCAN_runtest,\n    S_BSCAN_sel,\n    S_BSCAN_shift,\n    S_BSCAN_tck,\n    S_BSCAN_tdi,\n    S_BSCAN_tdo,\n    S_BSCAN_tms,\n    S_BSCAN_update,\n    clk);\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN BSCANID_EN\" *) input S_BSCAN_bscanid_en;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN CAPTURE\" *) input S_BSCAN_capture;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN DRCK\" *) input S_BSCAN_drck;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RESET\" *) input S_BSCAN_reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RUNTEST\" *) input S_BSCAN_runtest;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SEL\" *) input S_BSCAN_sel;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SHIFT\" *) input S_BSCAN_shift;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TCK\" *) input S_BSCAN_tck;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDI\" *) input S_BSCAN_tdi;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDO\" *) output S_BSCAN_tdo;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TMS\" *) input S_BSCAN_tms;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN UPDATE\" *) input S_BSCAN_update;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, CLK_DOMAIN bd_a493_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input clk;\n\n  wire S_BSCAN_1_BSCANID_EN;\n  wire S_BSCAN_1_CAPTURE;\n  wire S_BSCAN_1_DRCK;\n  wire S_BSCAN_1_RESET;\n  wire S_BSCAN_1_RUNTEST;\n  wire S_BSCAN_1_SEL;\n  wire S_BSCAN_1_SHIFT;\n  wire S_BSCAN_1_TCK;\n  wire S_BSCAN_1_TDI;\n  wire S_BSCAN_1_TDO;\n  wire S_BSCAN_1_TMS;\n  wire S_BSCAN_1_UPDATE;\n  wire clk_1;\n  wire lut_buffer_m_bscan_BSCANID_EN;\n  wire lut_buffer_m_bscan_CAPTURE;\n  wire lut_buffer_m_bscan_DRCK;\n  wire lut_buffer_m_bscan_RESET;\n  wire lut_buffer_m_bscan_RUNTEST;\n  wire lut_buffer_m_bscan_SEL;\n  wire lut_buffer_m_bscan_SHIFT;\n  wire lut_buffer_m_bscan_TCK;\n  wire lut_buffer_m_bscan_TDI;\n  wire lut_buffer_m_bscan_TDO;\n  wire lut_buffer_m_bscan_TMS;\n  wire lut_buffer_m_bscan_UPDATE;\n\n  assign S_BSCAN_1_BSCANID_EN = S_BSCAN_bscanid_en;\n  assign S_BSCAN_1_CAPTURE = S_BSCAN_capture;\n  assign S_BSCAN_1_DRCK = S_BSCAN_drck;\n  assign S_BSCAN_1_RESET = S_BSCAN_reset;\n  assign S_BSCAN_1_RUNTEST = S_BSCAN_runtest;\n  assign S_BSCAN_1_SEL = S_BSCAN_sel;\n  assign S_BSCAN_1_SHIFT = S_BSCAN_shift;\n  assign S_BSCAN_1_TCK = S_BSCAN_tck;\n  assign S_BSCAN_1_TDI = S_BSCAN_tdi;\n  assign S_BSCAN_1_TMS = S_BSCAN_tms;\n  assign S_BSCAN_1_UPDATE = S_BSCAN_update;\n  assign S_BSCAN_tdo = S_BSCAN_1_TDO;\n  assign clk_1 = clk;\n  bd_a493_lut_buffer_0 lut_buffer\n       (.bscanid_en_i(S_BSCAN_1_BSCANID_EN),\n        .bscanid_en_o(lut_buffer_m_bscan_BSCANID_EN),\n        .capture_i(S_BSCAN_1_CAPTURE),\n        .capture_o(lut_buffer_m_bscan_CAPTURE),\n        .drck_i(S_BSCAN_1_DRCK),\n        .drck_o(lut_buffer_m_bscan_DRCK),\n        .reset_i(S_BSCAN_1_RESET),\n        .reset_o(lut_buffer_m_bscan_RESET),\n        .runtest_i(S_BSCAN_1_RUNTEST),\n        .runtest_o(lut_buffer_m_bscan_RUNTEST),\n        .sel_i(S_BSCAN_1_SEL),\n        .sel_o(lut_buffer_m_bscan_SEL),\n        .shift_i(S_BSCAN_1_SHIFT),\n        .shift_o(lut_buffer_m_bscan_SHIFT),\n        .tck_i(S_BSCAN_1_TCK),\n        .tck_o(lut_buffer_m_bscan_TCK),\n        .tdi_i(S_BSCAN_1_TDI),\n        .tdi_o(lut_buffer_m_bscan_TDI),\n        .tdo_i(lut_buffer_m_bscan_TDO),\n        .tdo_o(S_BSCAN_1_TDO),\n        .tms_i(S_BSCAN_1_TMS),\n        .tms_o(lut_buffer_m_bscan_TMS),\n        .update_i(S_BSCAN_1_UPDATE),\n        .update_o(lut_buffer_m_bscan_UPDATE));\n  bd_a493_xsdbm_0 xsdbm\n       (.bscanid_en(lut_buffer_m_bscan_BSCANID_EN),\n        .capture(lut_buffer_m_bscan_CAPTURE),\n        .clk(clk_1),\n        .drck(lut_buffer_m_bscan_DRCK),\n        .reset(lut_buffer_m_bscan_RESET),\n        .runtest(lut_buffer_m_bscan_RUNTEST),\n        .sel(lut_buffer_m_bscan_SEL),\n        .shift(lut_buffer_m_bscan_SHIFT),\n        .tck(lut_buffer_m_bscan_TCK),\n        .tdi(lut_buffer_m_bscan_TDI),\n        .tdo(lut_buffer_m_bscan_TDO),\n        .tms(lut_buffer_m_bscan_TMS),\n        .update(lut_buffer_m_bscan_UPDATE));\nendmodule\n", "num_lines": 117}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_a493.bd\n//Design : bd_a493\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_a493,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_a493,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}\" *) (* HW_HANDOFF = \"cl_debug_bridge.hwdef\" *) \nmodule bd_a493\n   (S_BSCAN_bscanid_en,\n    S_BSCAN_capture,\n    S_BSCAN_drck,\n    S_BSCAN_reset,\n    S_BSCAN_runtest,\n    S_BSCAN_sel,\n    S_BSCAN_shift,\n    S_BSCAN_tck,\n    S_BSCAN_tdi,\n    S_BSCAN_tdo,\n    S_BSCAN_tms,\n    S_BSCAN_update,\n    clk);\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN BSCANID_EN\" *) input S_BSCAN_bscanid_en;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN CAPTURE\" *) input S_BSCAN_capture;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN DRCK\" *) input S_BSCAN_drck;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RESET\" *) input S_BSCAN_reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RUNTEST\" *) input S_BSCAN_runtest;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SEL\" *) input S_BSCAN_sel;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SHIFT\" *) input S_BSCAN_shift;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TCK\" *) input S_BSCAN_tck;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDI\" *) input S_BSCAN_tdi;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDO\" *) output S_BSCAN_tdo;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TMS\" *) input S_BSCAN_tms;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN UPDATE\" *) input S_BSCAN_update;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, CLK_DOMAIN bd_a493_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input clk;\n\n  wire S_BSCAN_1_BSCANID_EN;\n  wire S_BSCAN_1_CAPTURE;\n  wire S_BSCAN_1_DRCK;\n  wire S_BSCAN_1_RESET;\n  wire S_BSCAN_1_RUNTEST;\n  wire S_BSCAN_1_SEL;\n  wire S_BSCAN_1_SHIFT;\n  wire S_BSCAN_1_TCK;\n  wire S_BSCAN_1_TDI;\n  wire S_BSCAN_1_TDO;\n  wire S_BSCAN_1_TMS;\n  wire S_BSCAN_1_UPDATE;\n  wire clk_1;\n  wire lut_buffer_m_bscan_BSCANID_EN;\n  wire lut_buffer_m_bscan_CAPTURE;\n  wire lut_buffer_m_bscan_DRCK;\n  wire lut_buffer_m_bscan_RESET;\n  wire lut_buffer_m_bscan_RUNTEST;\n  wire lut_buffer_m_bscan_SEL;\n  wire lut_buffer_m_bscan_SHIFT;\n  wire lut_buffer_m_bscan_TCK;\n  wire lut_buffer_m_bscan_TDI;\n  wire lut_buffer_m_bscan_TDO;\n  wire lut_buffer_m_bscan_TMS;\n  wire lut_buffer_m_bscan_UPDATE;\n\n  assign S_BSCAN_1_BSCANID_EN = S_BSCAN_bscanid_en;\n  assign S_BSCAN_1_CAPTURE = S_BSCAN_capture;\n  assign S_BSCAN_1_DRCK = S_BSCAN_drck;\n  assign S_BSCAN_1_RESET = S_BSCAN_reset;\n  assign S_BSCAN_1_RUNTEST = S_BSCAN_runtest;\n  assign S_BSCAN_1_SEL = S_BSCAN_sel;\n  assign S_BSCAN_1_SHIFT = S_BSCAN_shift;\n  assign S_BSCAN_1_TCK = S_BSCAN_tck;\n  assign S_BSCAN_1_TDI = S_BSCAN_tdi;\n  assign S_BSCAN_1_TMS = S_BSCAN_tms;\n  assign S_BSCAN_1_UPDATE = S_BSCAN_update;\n  assign S_BSCAN_tdo = S_BSCAN_1_TDO;\n  assign clk_1 = clk;\n  bd_a493_lut_buffer_0 lut_buffer\n       (.bscanid_en_i(S_BSCAN_1_BSCANID_EN),\n        .bscanid_en_o(lut_buffer_m_bscan_BSCANID_EN),\n        .capture_i(S_BSCAN_1_CAPTURE),\n        .capture_o(lut_buffer_m_bscan_CAPTURE),\n        .drck_i(S_BSCAN_1_DRCK),\n        .drck_o(lut_buffer_m_bscan_DRCK),\n        .reset_i(S_BSCAN_1_RESET),\n        .reset_o(lut_buffer_m_bscan_RESET),\n        .runtest_i(S_BSCAN_1_RUNTEST),\n        .runtest_o(lut_buffer_m_bscan_RUNTEST),\n        .sel_i(S_BSCAN_1_SEL),\n        .sel_o(lut_buffer_m_bscan_SEL),\n        .shift_i(S_BSCAN_1_SHIFT),\n        .shift_o(lut_buffer_m_bscan_SHIFT),\n        .tck_i(S_BSCAN_1_TCK),\n        .tck_o(lut_buffer_m_bscan_TCK),\n        .tdi_i(S_BSCAN_1_TDI),\n        .tdi_o(lut_buffer_m_bscan_TDI),\n        .tdo_i(lut_buffer_m_bscan_TDO),\n        .tdo_o(S_BSCAN_1_TDO),\n        .tms_i(S_BSCAN_1_TMS),\n        .tms_o(lut_buffer_m_bscan_TMS),\n        .update_i(S_BSCAN_1_UPDATE),\n        .update_o(lut_buffer_m_bscan_UPDATE));\n  bd_a493_xsdbm_0 xsdbm\n       (.bscanid_en(lut_buffer_m_bscan_BSCANID_EN),\n        .capture(lut_buffer_m_bscan_CAPTURE),\n        .clk(clk_1),\n        .drck(lut_buffer_m_bscan_DRCK),\n        .reset(lut_buffer_m_bscan_RESET),\n        .runtest(lut_buffer_m_bscan_RUNTEST),\n        .sel(lut_buffer_m_bscan_SEL),\n        .shift(lut_buffer_m_bscan_SHIFT),\n        .tck(lut_buffer_m_bscan_TCK),\n        .tdi(lut_buffer_m_bscan_TDI),\n        .tdo(lut_buffer_m_bscan_TDO),\n        .tms(lut_buffer_m_bscan_TMS),\n        .update(lut_buffer_m_bscan_UPDATE));\nendmodule\n", "num_lines": 117}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:debug_bridge:3.0\n// IP Revision: 6\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_debug_bridge (\n  clk,\n  S_BSCAN_bscanid_en,\n  S_BSCAN_capture,\n  S_BSCAN_drck,\n  S_BSCAN_reset,\n  S_BSCAN_runtest,\n  S_BSCAN_sel,\n  S_BSCAN_shift,\n  S_BSCAN_tck,\n  S_BSCAN_tdi,\n  S_BSCAN_tdo,\n  S_BSCAN_tms,\n  S_BSCAN_update\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_a493_clk, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.clk CLK\" *)\ninput wire clk;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN BSCANID_EN\" *)\ninput wire S_BSCAN_bscanid_en;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN CAPTURE\" *)\ninput wire S_BSCAN_capture;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN DRCK\" *)\ninput wire S_BSCAN_drck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RESET\" *)\ninput wire S_BSCAN_reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RUNTEST\" *)\ninput wire S_BSCAN_runtest;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SEL\" *)\ninput wire S_BSCAN_sel;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SHIFT\" *)\ninput wire S_BSCAN_shift;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TCK\" *)\ninput wire S_BSCAN_tck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDI\" *)\ninput wire S_BSCAN_tdi;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDO\" *)\noutput wire S_BSCAN_tdo;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TMS\" *)\ninput wire S_BSCAN_tms;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN UPDATE\" *)\ninput wire S_BSCAN_update;\n\n  bd_a493 inst (\n    .clk(clk),\n    .S_BSCAN_bscanid_en(S_BSCAN_bscanid_en),\n    .S_BSCAN_capture(S_BSCAN_capture),\n    .S_BSCAN_drck(S_BSCAN_drck),\n    .S_BSCAN_reset(S_BSCAN_reset),\n    .S_BSCAN_runtest(S_BSCAN_runtest),\n    .S_BSCAN_sel(S_BSCAN_sel),\n    .S_BSCAN_shift(S_BSCAN_shift),\n    .S_BSCAN_tck(S_BSCAN_tck),\n    .S_BSCAN_tdi(S_BSCAN_tdi),\n    .S_BSCAN_tdo(S_BSCAN_tdo),\n    .S_BSCAN_tms(S_BSCAN_tms),\n    .S_BSCAN_update(S_BSCAN_update)\n  );\nendmodule\n", "num_lines": 116}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:debug_bridge:3.0\n// IP Revision: 6\n\n(* X_CORE_INFO = \"bd_a493,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_debug_bridge,bd_a493,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_debug_bridge,bd_a493,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=debug_bridge,x_ipVersion=3.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_DEBUG_MODE=1,C_NUM_BS_MASTER=0,C_BSCAN_MUX=1,C_EN_BSCANID_VEC=false,C_USE_EXT_BSCAN=true,C_USE_STARTUP_CLK=false,C_ENABLE_CLK_DIVIDER=false,C_TWO_PRIM_MODE=false,C_USER_SCAN_CHAIN=1,C_CORE_TYPE=1,C_EN_INT_SIM=1,C_DCLK_HAS_RESET=0,C_USE_BUFR=0,C_XSDB_NUM_SLAVES=0,C_CORE_MINOR_ALPHA_VER=97,C_CORE_MINOR_VER=0,C_\\\nCORE_MAJOR_VER=1,C_BUILD_REVISION=0,C_MINOR_VERSION=1,C_MAJOR_VERSION=14,C_FIFO_STYLE=SUBCORE,C_DESIGN_TYPE=0,C_MASTER_INTF_TYPE=1,C_EN_PASSTHROUGH=0,C_XVC_HW_ID=0x0001,C_XVC_SW_ID=0x0001,C_PCIE_EXT_CFG_BASE_ADDR=0x400,C_PCIE_EXT_CFG_VSEC_REV_ID=0x0,C_PCIE_EXT_CFG_VSEC_LENGTH=0x020,C_PCIE_EXT_CFG_NEXT_PTR=0x000,C_PCIE_EXT_CFG_VSEC_ID=0x0008,Component_Name=cl_debug_bridge,C_CLK_INPUT_FREQ_HZ=300000000,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ADDR_WIDTH=5,C_TCK_CLOCK_RATIO=8,C_USE_SOFTBSCAN=1,C_DEVICE_FAMILY\\\n=0,C_IR_WIDTH=0,C_CHIP_ID=0,C_IR_ID_INSTR=0,C_IR_USER1_INSTR=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_debug_bridge (\n  clk,\n  S_BSCAN_bscanid_en,\n  S_BSCAN_capture,\n  S_BSCAN_drck,\n  S_BSCAN_reset,\n  S_BSCAN_runtest,\n  S_BSCAN_sel,\n  S_BSCAN_shift,\n  S_BSCAN_tck,\n  S_BSCAN_tdi,\n  S_BSCAN_tdo,\n  S_BSCAN_tms,\n  S_BSCAN_update\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_a493_clk, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.clk CLK\" *)\ninput wire clk;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN BSCANID_EN\" *)\ninput wire S_BSCAN_bscanid_en;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN CAPTURE\" *)\ninput wire S_BSCAN_capture;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN DRCK\" *)\ninput wire S_BSCAN_drck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RESET\" *)\ninput wire S_BSCAN_reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RUNTEST\" *)\ninput wire S_BSCAN_runtest;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SEL\" *)\ninput wire S_BSCAN_sel;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SHIFT\" *)\ninput wire S_BSCAN_shift;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TCK\" *)\ninput wire S_BSCAN_tck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDI\" *)\ninput wire S_BSCAN_tdi;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDO\" *)\noutput wire S_BSCAN_tdo;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TMS\" *)\ninput wire S_BSCAN_tms;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN UPDATE\" *)\ninput wire S_BSCAN_update;\n\n  bd_a493 inst (\n    .clk(clk),\n    .S_BSCAN_bscanid_en(S_BSCAN_bscanid_en),\n    .S_BSCAN_capture(S_BSCAN_capture),\n    .S_BSCAN_drck(S_BSCAN_drck),\n    .S_BSCAN_reset(S_BSCAN_reset),\n    .S_BSCAN_runtest(S_BSCAN_runtest),\n    .S_BSCAN_sel(S_BSCAN_sel),\n    .S_BSCAN_shift(S_BSCAN_shift),\n    .S_BSCAN_tck(S_BSCAN_tck),\n    .S_BSCAN_tdi(S_BSCAN_tdi),\n    .S_BSCAN_tdo(S_BSCAN_tdo),\n    .S_BSCAN_tms(S_BSCAN_tms),\n    .S_BSCAN_update(S_BSCAN_update)\n  );\nendmodule\n", "num_lines": 119}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_bf3f_wrapper.bd\n//Design : bd_bf3f_wrapper\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule bd_bf3f_wrapper\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  input Clk;\n  output IO_addr_strobe;\n  output [31:0]IO_address;\n  output [3:0]IO_byte_enable;\n  input [31:0]IO_read_data;\n  output IO_read_strobe;\n  input IO_ready;\n  output [31:0]IO_write_data;\n  output IO_write_strobe;\n  input Reset;\n  output TRACE_data_access;\n  output [0:31]TRACE_data_address;\n  output [0:3]TRACE_data_byte_enable;\n  output TRACE_data_read;\n  output TRACE_data_write;\n  output [0:31]TRACE_data_write_value;\n  output TRACE_dcache_hit;\n  output TRACE_dcache_rdy;\n  output TRACE_dcache_read;\n  output TRACE_dcache_req;\n  output TRACE_delay_slot;\n  output TRACE_ex_piperun;\n  output [0:4]TRACE_exception_kind;\n  output TRACE_exception_taken;\n  output TRACE_icache_hit;\n  output TRACE_icache_rdy;\n  output TRACE_icache_req;\n  output [0:31]TRACE_instruction;\n  output TRACE_jump_hit;\n  output TRACE_jump_taken;\n  output TRACE_mb_halted;\n  output TRACE_mem_piperun;\n  output [0:14]TRACE_msr_reg;\n  output [0:31]TRACE_new_reg_value;\n  output TRACE_of_piperun;\n  output [0:31]TRACE_pc;\n  output [0:7]TRACE_pid_reg;\n  output [0:4]TRACE_reg_addr;\n  output TRACE_reg_write;\n  output TRACE_valid_instr;\n\n  wire Clk;\n  wire IO_addr_strobe;\n  wire [31:0]IO_address;\n  wire [3:0]IO_byte_enable;\n  wire [31:0]IO_read_data;\n  wire IO_read_strobe;\n  wire IO_ready;\n  wire [31:0]IO_write_data;\n  wire IO_write_strobe;\n  wire Reset;\n  wire TRACE_data_access;\n  wire [0:31]TRACE_data_address;\n  wire [0:3]TRACE_data_byte_enable;\n  wire TRACE_data_read;\n  wire TRACE_data_write;\n  wire [0:31]TRACE_data_write_value;\n  wire TRACE_dcache_hit;\n  wire TRACE_dcache_rdy;\n  wire TRACE_dcache_read;\n  wire TRACE_dcache_req;\n  wire TRACE_delay_slot;\n  wire TRACE_ex_piperun;\n  wire [0:4]TRACE_exception_kind;\n  wire TRACE_exception_taken;\n  wire TRACE_icache_hit;\n  wire TRACE_icache_rdy;\n  wire TRACE_icache_req;\n  wire [0:31]TRACE_instruction;\n  wire TRACE_jump_hit;\n  wire TRACE_jump_taken;\n  wire TRACE_mb_halted;\n  wire TRACE_mem_piperun;\n  wire [0:14]TRACE_msr_reg;\n  wire [0:31]TRACE_new_reg_value;\n  wire TRACE_of_piperun;\n  wire [0:31]TRACE_pc;\n  wire [0:7]TRACE_pid_reg;\n  wire [0:4]TRACE_reg_addr;\n  wire TRACE_reg_write;\n  wire TRACE_valid_instr;\n\n  bd_bf3f bd_bf3f_i\n       (.Clk(Clk),\n        .IO_addr_strobe(IO_addr_strobe),\n        .IO_address(IO_address),\n        .IO_byte_enable(IO_byte_enable),\n        .IO_read_data(IO_read_data),\n        .IO_read_strobe(IO_read_strobe),\n        .IO_ready(IO_ready),\n        .IO_write_data(IO_write_data),\n        .IO_write_strobe(IO_write_strobe),\n        .Reset(Reset),\n        .TRACE_data_access(TRACE_data_access),\n        .TRACE_data_address(TRACE_data_address),\n        .TRACE_data_byte_enable(TRACE_data_byte_enable),\n        .TRACE_data_read(TRACE_data_read),\n        .TRACE_data_write(TRACE_data_write),\n        .TRACE_data_write_value(TRACE_data_write_value),\n        .TRACE_dcache_hit(TRACE_dcache_hit),\n        .TRACE_dcache_rdy(TRACE_dcache_rdy),\n        .TRACE_dcache_read(TRACE_dcache_read),\n        .TRACE_dcache_req(TRACE_dcache_req),\n        .TRACE_delay_slot(TRACE_delay_slot),\n        .TRACE_ex_piperun(TRACE_ex_piperun),\n        .TRACE_exception_kind(TRACE_exception_kind),\n        .TRACE_exception_taken(TRACE_exception_taken),\n        .TRACE_icache_hit(TRACE_icache_hit),\n        .TRACE_icache_rdy(TRACE_icache_rdy),\n        .TRACE_icache_req(TRACE_icache_req),\n        .TRACE_instruction(TRACE_instruction),\n        .TRACE_jump_hit(TRACE_jump_hit),\n        .TRACE_jump_taken(TRACE_jump_taken),\n        .TRACE_mb_halted(TRACE_mb_halted),\n        .TRACE_mem_piperun(TRACE_mem_piperun),\n        .TRACE_msr_reg(TRACE_msr_reg),\n        .TRACE_new_reg_value(TRACE_new_reg_value),\n        .TRACE_of_piperun(TRACE_of_piperun),\n        .TRACE_pc(TRACE_pc),\n        .TRACE_pid_reg(TRACE_pid_reg),\n        .TRACE_reg_addr(TRACE_reg_addr),\n        .TRACE_reg_write(TRACE_reg_write),\n        .TRACE_valid_instr(TRACE_valid_instr));\nendmodule\n", "num_lines": 174}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_bf3f_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_bf3f_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(16384),\n    .C_READ_DEPTH_A(16384),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(16384),\n    .C_READ_DEPTH_B(16384),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"16\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     19.660986 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_bf3f_second_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_bf3f_second_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(8192),\n    .C_READ_DEPTH_A(8192),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(8192),\n    .C_READ_DEPTH_B(8192),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"8\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     17.246228 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_bf3f.bd\n//Design : bd_bf3f\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_bf3f,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_bf3f,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_microblaze_mcs.hwdef\" *) \nmodule bd_bf3f\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_bf3f_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_bf3f_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_bf3f lmb_bram_I bd_bf3f second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_bf3f_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_bf3f_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_bf3f_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_bf3f_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_bf3f_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_bf3f dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_bf3f_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_bf3f_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_bf3f_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_bf3f_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_bf3f_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_bf3f.bd\n//Design : bd_bf3f\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_bf3f,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_bf3f,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_microblaze_mcs.hwdef\" *) \nmodule bd_bf3f\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_bf3f_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_bf3f_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_bf3f lmb_bram_I bd_bf3f second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_bf3f_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_bf3f_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_bf3f_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_bf3f_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_bf3f_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_bf3f dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_bf3f_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_bf3f_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_bf3f_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_bf3f_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_bf3f_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_bf3f_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_bf3f inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 225}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n(* X_CORE_INFO = \"bd_bf3f,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"ddr4_core_microblaze_mcs,bd_bf3f,{}\" *)\n(* CORE_GENERATION_INFO = \"ddr4_core_microblaze_mcs,bd_bf3f,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze_mcs,x_ipVersion=3.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,JTAG_CHAIN=2,MICROBLAZE_INSTANCE=microblaze_0,AVOID_PRIMITIVES=0,PATH=mcs_0,FREQ=100.0,OPTIMIZATION=1,DEBUG_ENABLED=0,USE_BSCAN=0,BSCANID=76547328,TRACE=1,ECC=0,MEMSIZE=98304,MEMTYPE=0,USE_IO_BUS=1,USE_UART_RX=0,USE_UART_TX=0,UART_BAUDRATE=9600,UART_PROG_BAUDRATE=0,UART_DATA_BITS=8,UART_USE_PARITY=0\\\n,UART_ODD_PARITY=0,UART_RX_INTERRUPT=0,UART_TX_INTERRUPT=0,UART_ERROR_INTERRUPT=0,USE_FIT1=0,FIT1_No_CLOCKS=6216,FIT1_INTERRUPT=0,USE_FIT2=0,FIT2_No_CLOCKS=6216,FIT2_INTERRUPT=0,USE_FIT3=0,FIT3_No_CLOCKS=6216,FIT3_INTERRUPT=0,USE_FIT4=0,FIT4_No_CLOCKS=6216,FIT4_INTERRUPT=0,USE_PIT1=0,PIT1_SIZE=32,PIT1_READABLE=1,PIT1_PRESCALER=0,PIT1_INTERRUPT=0,USE_PIT2=0,PIT2_SIZE=32,PIT2_READABLE=1,PIT2_PRESCALER=0,PIT2_INTERRUPT=0,USE_PIT3=0,PIT3_SIZE=32,PIT3_READABLE=1,PIT3_PRESCALER=0,PIT3_INTERRUPT=0,USE_\\\nPIT4=0,PIT4_SIZE=32,PIT4_READABLE=1,PIT4_PRESCALER=0,PIT4_INTERRUPT=0,USE_GPO1=0,GPO1_SIZE=32,GPO1_INIT=0x00000000,USE_GPO2=0,GPO2_SIZE=32,GPO2_INIT=0x00000000,USE_GPO3=0,GPO3_SIZE=32,GPO3_INIT=0x00000000,USE_GPO4=0,GPO4_SIZE=32,GPO4_INIT=0x00000000,USE_GPI1=0,GPI1_SIZE=32,GPI1_INTERRUPT=0,USE_GPI2=0,GPI2_SIZE=32,GPI2_INTERRUPT=0,USE_GPI3=0,GPI3_SIZE=32,GPI3_INTERRUPT=0,USE_GPI4=0,GPI4_SIZE=32,GPI4_INTERRUPT=0,INTC_USE_EXT_INTR=0,INTC_INTR_SIZE=1,INTC_LEVEL_EDGE=0x0000,INTC_POSITIVE=0xFFFF,INTC_\\\nASYNC_INTR=0xFFFF,INTC_NUM_SYNC_FF=2,Component_Name=ddr4_core_microblaze_mcs,USE_BOARD_FLOW=false,CLK_BOARD_INTERFACE=Custom,RESET_BOARD_INTERFACE=Custom,GPIO1_BOARD_INTERFACE=Custom,GPIO2_BOARD_INTERFACE=Custom,GPIO3_BOARD_INTERFACE=Custom,GPIO4_BOARD_INTERFACE=Custom,UART_BOARD_INTERFACE=Custom}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_bf3f_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_bf3f inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 229}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_8120_wrapper.bd\n//Design : bd_8120_wrapper\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule bd_8120_wrapper\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  input Clk;\n  output IO_addr_strobe;\n  output [31:0]IO_address;\n  output [3:0]IO_byte_enable;\n  input [31:0]IO_read_data;\n  output IO_read_strobe;\n  input IO_ready;\n  output [31:0]IO_write_data;\n  output IO_write_strobe;\n  input Reset;\n  output TRACE_data_access;\n  output [0:31]TRACE_data_address;\n  output [0:3]TRACE_data_byte_enable;\n  output TRACE_data_read;\n  output TRACE_data_write;\n  output [0:31]TRACE_data_write_value;\n  output TRACE_dcache_hit;\n  output TRACE_dcache_rdy;\n  output TRACE_dcache_read;\n  output TRACE_dcache_req;\n  output TRACE_delay_slot;\n  output TRACE_ex_piperun;\n  output [0:4]TRACE_exception_kind;\n  output TRACE_exception_taken;\n  output TRACE_icache_hit;\n  output TRACE_icache_rdy;\n  output TRACE_icache_req;\n  output [0:31]TRACE_instruction;\n  output TRACE_jump_hit;\n  output TRACE_jump_taken;\n  output TRACE_mb_halted;\n  output TRACE_mem_piperun;\n  output [0:14]TRACE_msr_reg;\n  output [0:31]TRACE_new_reg_value;\n  output TRACE_of_piperun;\n  output [0:31]TRACE_pc;\n  output [0:7]TRACE_pid_reg;\n  output [0:4]TRACE_reg_addr;\n  output TRACE_reg_write;\n  output TRACE_valid_instr;\n\n  wire Clk;\n  wire IO_addr_strobe;\n  wire [31:0]IO_address;\n  wire [3:0]IO_byte_enable;\n  wire [31:0]IO_read_data;\n  wire IO_read_strobe;\n  wire IO_ready;\n  wire [31:0]IO_write_data;\n  wire IO_write_strobe;\n  wire Reset;\n  wire TRACE_data_access;\n  wire [0:31]TRACE_data_address;\n  wire [0:3]TRACE_data_byte_enable;\n  wire TRACE_data_read;\n  wire TRACE_data_write;\n  wire [0:31]TRACE_data_write_value;\n  wire TRACE_dcache_hit;\n  wire TRACE_dcache_rdy;\n  wire TRACE_dcache_read;\n  wire TRACE_dcache_req;\n  wire TRACE_delay_slot;\n  wire TRACE_ex_piperun;\n  wire [0:4]TRACE_exception_kind;\n  wire TRACE_exception_taken;\n  wire TRACE_icache_hit;\n  wire TRACE_icache_rdy;\n  wire TRACE_icache_req;\n  wire [0:31]TRACE_instruction;\n  wire TRACE_jump_hit;\n  wire TRACE_jump_taken;\n  wire TRACE_mb_halted;\n  wire TRACE_mem_piperun;\n  wire [0:14]TRACE_msr_reg;\n  wire [0:31]TRACE_new_reg_value;\n  wire TRACE_of_piperun;\n  wire [0:31]TRACE_pc;\n  wire [0:7]TRACE_pid_reg;\n  wire [0:4]TRACE_reg_addr;\n  wire TRACE_reg_write;\n  wire TRACE_valid_instr;\n\n  bd_8120 bd_8120_i\n       (.Clk(Clk),\n        .IO_addr_strobe(IO_addr_strobe),\n        .IO_address(IO_address),\n        .IO_byte_enable(IO_byte_enable),\n        .IO_read_data(IO_read_data),\n        .IO_read_strobe(IO_read_strobe),\n        .IO_ready(IO_ready),\n        .IO_write_data(IO_write_data),\n        .IO_write_strobe(IO_write_strobe),\n        .Reset(Reset),\n        .TRACE_data_access(TRACE_data_access),\n        .TRACE_data_address(TRACE_data_address),\n        .TRACE_data_byte_enable(TRACE_data_byte_enable),\n        .TRACE_data_read(TRACE_data_read),\n        .TRACE_data_write(TRACE_data_write),\n        .TRACE_data_write_value(TRACE_data_write_value),\n        .TRACE_dcache_hit(TRACE_dcache_hit),\n        .TRACE_dcache_rdy(TRACE_dcache_rdy),\n        .TRACE_dcache_read(TRACE_dcache_read),\n        .TRACE_dcache_req(TRACE_dcache_req),\n        .TRACE_delay_slot(TRACE_delay_slot),\n        .TRACE_ex_piperun(TRACE_ex_piperun),\n        .TRACE_exception_kind(TRACE_exception_kind),\n        .TRACE_exception_taken(TRACE_exception_taken),\n        .TRACE_icache_hit(TRACE_icache_hit),\n        .TRACE_icache_rdy(TRACE_icache_rdy),\n        .TRACE_icache_req(TRACE_icache_req),\n        .TRACE_instruction(TRACE_instruction),\n        .TRACE_jump_hit(TRACE_jump_hit),\n        .TRACE_jump_taken(TRACE_jump_taken),\n        .TRACE_mb_halted(TRACE_mb_halted),\n        .TRACE_mem_piperun(TRACE_mem_piperun),\n        .TRACE_msr_reg(TRACE_msr_reg),\n        .TRACE_new_reg_value(TRACE_new_reg_value),\n        .TRACE_of_piperun(TRACE_of_piperun),\n        .TRACE_pc(TRACE_pc),\n        .TRACE_pid_reg(TRACE_pid_reg),\n        .TRACE_reg_addr(TRACE_reg_addr),\n        .TRACE_reg_write(TRACE_reg_write),\n        .TRACE_valid_instr(TRACE_valid_instr));\nendmodule\n", "num_lines": 174}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_8120_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_8120_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(16384),\n    .C_READ_DEPTH_A(16384),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(16384),\n    .C_READ_DEPTH_B(16384),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"16\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     19.660986 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_8120_second_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_8120_second_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(8192),\n    .C_READ_DEPTH_A(8192),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(8192),\n    .C_READ_DEPTH_B(8192),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"8\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     17.246228 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_8120.bd\n//Design : bd_8120\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_8120,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_8120,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_a_microblaze_mcs.hwdef\" *) \nmodule bd_8120\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_8120_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_8120_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_8120 lmb_bram_I bd_8120 second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_8120_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_8120_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_8120_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_8120_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_8120_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_8120 dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_8120_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_8120_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_8120_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_8120_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_8120_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_8120.bd\n//Design : bd_8120\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_8120,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_8120,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_a_microblaze_mcs.hwdef\" *) \nmodule bd_8120\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_8120_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_8120_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_8120 lmb_bram_I bd_8120 second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_8120_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_8120_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_8120_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_8120_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_8120_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_8120 dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_8120_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_8120_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_8120_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_8120_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_8120_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_a_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_8120_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_8120 inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 225}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n(* X_CORE_INFO = \"bd_8120,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"ddr4_core_a_microblaze_mcs,bd_8120,{}\" *)\n(* CORE_GENERATION_INFO = \"ddr4_core_a_microblaze_mcs,bd_8120,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze_mcs,x_ipVersion=3.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,JTAG_CHAIN=2,MICROBLAZE_INSTANCE=microblaze_0,AVOID_PRIMITIVES=0,PATH=mcs_0,FREQ=100.0,OPTIMIZATION=1,DEBUG_ENABLED=0,USE_BSCAN=0,BSCANID=76547328,TRACE=1,ECC=0,MEMSIZE=98304,MEMTYPE=0,USE_IO_BUS=1,USE_UART_RX=0,USE_UART_TX=0,UART_BAUDRATE=9600,UART_PROG_BAUDRATE=0,UART_DATA_BITS=8,UART_USE_PARITY\\\n=0,UART_ODD_PARITY=0,UART_RX_INTERRUPT=0,UART_TX_INTERRUPT=0,UART_ERROR_INTERRUPT=0,USE_FIT1=0,FIT1_No_CLOCKS=6216,FIT1_INTERRUPT=0,USE_FIT2=0,FIT2_No_CLOCKS=6216,FIT2_INTERRUPT=0,USE_FIT3=0,FIT3_No_CLOCKS=6216,FIT3_INTERRUPT=0,USE_FIT4=0,FIT4_No_CLOCKS=6216,FIT4_INTERRUPT=0,USE_PIT1=0,PIT1_SIZE=32,PIT1_READABLE=1,PIT1_PRESCALER=0,PIT1_INTERRUPT=0,USE_PIT2=0,PIT2_SIZE=32,PIT2_READABLE=1,PIT2_PRESCALER=0,PIT2_INTERRUPT=0,USE_PIT3=0,PIT3_SIZE=32,PIT3_READABLE=1,PIT3_PRESCALER=0,PIT3_INTERRUPT=0,US\\\nE_PIT4=0,PIT4_SIZE=32,PIT4_READABLE=1,PIT4_PRESCALER=0,PIT4_INTERRUPT=0,USE_GPO1=0,GPO1_SIZE=32,GPO1_INIT=0x00000000,USE_GPO2=0,GPO2_SIZE=32,GPO2_INIT=0x00000000,USE_GPO3=0,GPO3_SIZE=32,GPO3_INIT=0x00000000,USE_GPO4=0,GPO4_SIZE=32,GPO4_INIT=0x00000000,USE_GPI1=0,GPI1_SIZE=32,GPI1_INTERRUPT=0,USE_GPI2=0,GPI2_SIZE=32,GPI2_INTERRUPT=0,USE_GPI3=0,GPI3_SIZE=32,GPI3_INTERRUPT=0,USE_GPI4=0,GPI4_SIZE=32,GPI4_INTERRUPT=0,INTC_USE_EXT_INTR=0,INTC_INTR_SIZE=1,INTC_LEVEL_EDGE=0x0000,INTC_POSITIVE=0xFFFF,INT\\\nC_ASYNC_INTR=0xFFFF,INTC_NUM_SYNC_FF=2,Component_Name=ddr4_core_a_microblaze_mcs,USE_BOARD_FLOW=false,CLK_BOARD_INTERFACE=Custom,RESET_BOARD_INTERFACE=Custom,GPIO1_BOARD_INTERFACE=Custom,GPIO2_BOARD_INTERFACE=Custom,GPIO3_BOARD_INTERFACE=Custom,GPIO4_BOARD_INTERFACE=Custom,UART_BOARD_INTERFACE=Custom}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_a_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_8120_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_8120 inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 229}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_b066_wrapper.bd\n//Design : bd_b066_wrapper\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule bd_b066_wrapper\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  input Clk;\n  output IO_addr_strobe;\n  output [31:0]IO_address;\n  output [3:0]IO_byte_enable;\n  input [31:0]IO_read_data;\n  output IO_read_strobe;\n  input IO_ready;\n  output [31:0]IO_write_data;\n  output IO_write_strobe;\n  input Reset;\n  output TRACE_data_access;\n  output [0:31]TRACE_data_address;\n  output [0:3]TRACE_data_byte_enable;\n  output TRACE_data_read;\n  output TRACE_data_write;\n  output [0:31]TRACE_data_write_value;\n  output TRACE_dcache_hit;\n  output TRACE_dcache_rdy;\n  output TRACE_dcache_read;\n  output TRACE_dcache_req;\n  output TRACE_delay_slot;\n  output TRACE_ex_piperun;\n  output [0:4]TRACE_exception_kind;\n  output TRACE_exception_taken;\n  output TRACE_icache_hit;\n  output TRACE_icache_rdy;\n  output TRACE_icache_req;\n  output [0:31]TRACE_instruction;\n  output TRACE_jump_hit;\n  output TRACE_jump_taken;\n  output TRACE_mb_halted;\n  output TRACE_mem_piperun;\n  output [0:14]TRACE_msr_reg;\n  output [0:31]TRACE_new_reg_value;\n  output TRACE_of_piperun;\n  output [0:31]TRACE_pc;\n  output [0:7]TRACE_pid_reg;\n  output [0:4]TRACE_reg_addr;\n  output TRACE_reg_write;\n  output TRACE_valid_instr;\n\n  wire Clk;\n  wire IO_addr_strobe;\n  wire [31:0]IO_address;\n  wire [3:0]IO_byte_enable;\n  wire [31:0]IO_read_data;\n  wire IO_read_strobe;\n  wire IO_ready;\n  wire [31:0]IO_write_data;\n  wire IO_write_strobe;\n  wire Reset;\n  wire TRACE_data_access;\n  wire [0:31]TRACE_data_address;\n  wire [0:3]TRACE_data_byte_enable;\n  wire TRACE_data_read;\n  wire TRACE_data_write;\n  wire [0:31]TRACE_data_write_value;\n  wire TRACE_dcache_hit;\n  wire TRACE_dcache_rdy;\n  wire TRACE_dcache_read;\n  wire TRACE_dcache_req;\n  wire TRACE_delay_slot;\n  wire TRACE_ex_piperun;\n  wire [0:4]TRACE_exception_kind;\n  wire TRACE_exception_taken;\n  wire TRACE_icache_hit;\n  wire TRACE_icache_rdy;\n  wire TRACE_icache_req;\n  wire [0:31]TRACE_instruction;\n  wire TRACE_jump_hit;\n  wire TRACE_jump_taken;\n  wire TRACE_mb_halted;\n  wire TRACE_mem_piperun;\n  wire [0:14]TRACE_msr_reg;\n  wire [0:31]TRACE_new_reg_value;\n  wire TRACE_of_piperun;\n  wire [0:31]TRACE_pc;\n  wire [0:7]TRACE_pid_reg;\n  wire [0:4]TRACE_reg_addr;\n  wire TRACE_reg_write;\n  wire TRACE_valid_instr;\n\n  bd_b066 bd_b066_i\n       (.Clk(Clk),\n        .IO_addr_strobe(IO_addr_strobe),\n        .IO_address(IO_address),\n        .IO_byte_enable(IO_byte_enable),\n        .IO_read_data(IO_read_data),\n        .IO_read_strobe(IO_read_strobe),\n        .IO_ready(IO_ready),\n        .IO_write_data(IO_write_data),\n        .IO_write_strobe(IO_write_strobe),\n        .Reset(Reset),\n        .TRACE_data_access(TRACE_data_access),\n        .TRACE_data_address(TRACE_data_address),\n        .TRACE_data_byte_enable(TRACE_data_byte_enable),\n        .TRACE_data_read(TRACE_data_read),\n        .TRACE_data_write(TRACE_data_write),\n        .TRACE_data_write_value(TRACE_data_write_value),\n        .TRACE_dcache_hit(TRACE_dcache_hit),\n        .TRACE_dcache_rdy(TRACE_dcache_rdy),\n        .TRACE_dcache_read(TRACE_dcache_read),\n        .TRACE_dcache_req(TRACE_dcache_req),\n        .TRACE_delay_slot(TRACE_delay_slot),\n        .TRACE_ex_piperun(TRACE_ex_piperun),\n        .TRACE_exception_kind(TRACE_exception_kind),\n        .TRACE_exception_taken(TRACE_exception_taken),\n        .TRACE_icache_hit(TRACE_icache_hit),\n        .TRACE_icache_rdy(TRACE_icache_rdy),\n        .TRACE_icache_req(TRACE_icache_req),\n        .TRACE_instruction(TRACE_instruction),\n        .TRACE_jump_hit(TRACE_jump_hit),\n        .TRACE_jump_taken(TRACE_jump_taken),\n        .TRACE_mb_halted(TRACE_mb_halted),\n        .TRACE_mem_piperun(TRACE_mem_piperun),\n        .TRACE_msr_reg(TRACE_msr_reg),\n        .TRACE_new_reg_value(TRACE_new_reg_value),\n        .TRACE_of_piperun(TRACE_of_piperun),\n        .TRACE_pc(TRACE_pc),\n        .TRACE_pid_reg(TRACE_pid_reg),\n        .TRACE_reg_addr(TRACE_reg_addr),\n        .TRACE_reg_write(TRACE_reg_write),\n        .TRACE_valid_instr(TRACE_valid_instr));\nendmodule\n", "num_lines": 174}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_b066_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_b066_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(16384),\n    .C_READ_DEPTH_A(16384),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(16384),\n    .C_READ_DEPTH_B(16384),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"16\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     19.660986 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_b066_second_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_b066_second_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(8192),\n    .C_READ_DEPTH_A(8192),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(8192),\n    .C_READ_DEPTH_B(8192),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"8\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     17.246228 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_b066.bd\n//Design : bd_b066\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_b066,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_b066,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_b_microblaze_mcs.hwdef\" *) \nmodule bd_b066\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_b066_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_b066_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_b066 lmb_bram_I bd_b066 second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_b066_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_b066_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_b066_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_b066_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_b066_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_b066 dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_b066_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_b066_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_b066_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_b066_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_b066_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_b066.bd\n//Design : bd_b066\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_b066,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_b066,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_b_microblaze_mcs.hwdef\" *) \nmodule bd_b066\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_b066_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_b066_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_b066 lmb_bram_I bd_b066 second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_b066_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_b066_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_b066_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_b066_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_b066_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_b066 dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_b066_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_b066_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_b066_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_b066_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_b066_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_b_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_b066_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_b066 inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 225}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n(* X_CORE_INFO = \"bd_b066,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"ddr4_core_b_microblaze_mcs,bd_b066,{}\" *)\n(* CORE_GENERATION_INFO = \"ddr4_core_b_microblaze_mcs,bd_b066,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze_mcs,x_ipVersion=3.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,JTAG_CHAIN=2,MICROBLAZE_INSTANCE=microblaze_0,AVOID_PRIMITIVES=0,PATH=mcs_0,FREQ=100.0,OPTIMIZATION=1,DEBUG_ENABLED=0,USE_BSCAN=0,BSCANID=76547328,TRACE=1,ECC=0,MEMSIZE=98304,MEMTYPE=0,USE_IO_BUS=1,USE_UART_RX=0,USE_UART_TX=0,UART_BAUDRATE=9600,UART_PROG_BAUDRATE=0,UART_DATA_BITS=8,UART_USE_PARITY\\\n=0,UART_ODD_PARITY=0,UART_RX_INTERRUPT=0,UART_TX_INTERRUPT=0,UART_ERROR_INTERRUPT=0,USE_FIT1=0,FIT1_No_CLOCKS=6216,FIT1_INTERRUPT=0,USE_FIT2=0,FIT2_No_CLOCKS=6216,FIT2_INTERRUPT=0,USE_FIT3=0,FIT3_No_CLOCKS=6216,FIT3_INTERRUPT=0,USE_FIT4=0,FIT4_No_CLOCKS=6216,FIT4_INTERRUPT=0,USE_PIT1=0,PIT1_SIZE=32,PIT1_READABLE=1,PIT1_PRESCALER=0,PIT1_INTERRUPT=0,USE_PIT2=0,PIT2_SIZE=32,PIT2_READABLE=1,PIT2_PRESCALER=0,PIT2_INTERRUPT=0,USE_PIT3=0,PIT3_SIZE=32,PIT3_READABLE=1,PIT3_PRESCALER=0,PIT3_INTERRUPT=0,US\\\nE_PIT4=0,PIT4_SIZE=32,PIT4_READABLE=1,PIT4_PRESCALER=0,PIT4_INTERRUPT=0,USE_GPO1=0,GPO1_SIZE=32,GPO1_INIT=0x00000000,USE_GPO2=0,GPO2_SIZE=32,GPO2_INIT=0x00000000,USE_GPO3=0,GPO3_SIZE=32,GPO3_INIT=0x00000000,USE_GPO4=0,GPO4_SIZE=32,GPO4_INIT=0x00000000,USE_GPI1=0,GPI1_SIZE=32,GPI1_INTERRUPT=0,USE_GPI2=0,GPI2_SIZE=32,GPI2_INTERRUPT=0,USE_GPI3=0,GPI3_SIZE=32,GPI3_INTERRUPT=0,USE_GPI4=0,GPI4_SIZE=32,GPI4_INTERRUPT=0,INTC_USE_EXT_INTR=0,INTC_INTR_SIZE=1,INTC_LEVEL_EDGE=0x0000,INTC_POSITIVE=0xFFFF,INT\\\nC_ASYNC_INTR=0xFFFF,INTC_NUM_SYNC_FF=2,Component_Name=ddr4_core_b_microblaze_mcs,USE_BOARD_FLOW=false,CLK_BOARD_INTERFACE=Custom,RESET_BOARD_INTERFACE=Custom,GPIO1_BOARD_INTERFACE=Custom,GPIO2_BOARD_INTERFACE=Custom,GPIO3_BOARD_INTERFACE=Custom,GPIO4_BOARD_INTERFACE=Custom,UART_BOARD_INTERFACE=Custom}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_b_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_b066_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_b066 inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 229}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_a0a4_wrapper.bd\n//Design : bd_a0a4_wrapper\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule bd_a0a4_wrapper\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  input Clk;\n  output IO_addr_strobe;\n  output [31:0]IO_address;\n  output [3:0]IO_byte_enable;\n  input [31:0]IO_read_data;\n  output IO_read_strobe;\n  input IO_ready;\n  output [31:0]IO_write_data;\n  output IO_write_strobe;\n  input Reset;\n  output TRACE_data_access;\n  output [0:31]TRACE_data_address;\n  output [0:3]TRACE_data_byte_enable;\n  output TRACE_data_read;\n  output TRACE_data_write;\n  output [0:31]TRACE_data_write_value;\n  output TRACE_dcache_hit;\n  output TRACE_dcache_rdy;\n  output TRACE_dcache_read;\n  output TRACE_dcache_req;\n  output TRACE_delay_slot;\n  output TRACE_ex_piperun;\n  output [0:4]TRACE_exception_kind;\n  output TRACE_exception_taken;\n  output TRACE_icache_hit;\n  output TRACE_icache_rdy;\n  output TRACE_icache_req;\n  output [0:31]TRACE_instruction;\n  output TRACE_jump_hit;\n  output TRACE_jump_taken;\n  output TRACE_mb_halted;\n  output TRACE_mem_piperun;\n  output [0:14]TRACE_msr_reg;\n  output [0:31]TRACE_new_reg_value;\n  output TRACE_of_piperun;\n  output [0:31]TRACE_pc;\n  output [0:7]TRACE_pid_reg;\n  output [0:4]TRACE_reg_addr;\n  output TRACE_reg_write;\n  output TRACE_valid_instr;\n\n  wire Clk;\n  wire IO_addr_strobe;\n  wire [31:0]IO_address;\n  wire [3:0]IO_byte_enable;\n  wire [31:0]IO_read_data;\n  wire IO_read_strobe;\n  wire IO_ready;\n  wire [31:0]IO_write_data;\n  wire IO_write_strobe;\n  wire Reset;\n  wire TRACE_data_access;\n  wire [0:31]TRACE_data_address;\n  wire [0:3]TRACE_data_byte_enable;\n  wire TRACE_data_read;\n  wire TRACE_data_write;\n  wire [0:31]TRACE_data_write_value;\n  wire TRACE_dcache_hit;\n  wire TRACE_dcache_rdy;\n  wire TRACE_dcache_read;\n  wire TRACE_dcache_req;\n  wire TRACE_delay_slot;\n  wire TRACE_ex_piperun;\n  wire [0:4]TRACE_exception_kind;\n  wire TRACE_exception_taken;\n  wire TRACE_icache_hit;\n  wire TRACE_icache_rdy;\n  wire TRACE_icache_req;\n  wire [0:31]TRACE_instruction;\n  wire TRACE_jump_hit;\n  wire TRACE_jump_taken;\n  wire TRACE_mb_halted;\n  wire TRACE_mem_piperun;\n  wire [0:14]TRACE_msr_reg;\n  wire [0:31]TRACE_new_reg_value;\n  wire TRACE_of_piperun;\n  wire [0:31]TRACE_pc;\n  wire [0:7]TRACE_pid_reg;\n  wire [0:4]TRACE_reg_addr;\n  wire TRACE_reg_write;\n  wire TRACE_valid_instr;\n\n  bd_a0a4 bd_a0a4_i\n       (.Clk(Clk),\n        .IO_addr_strobe(IO_addr_strobe),\n        .IO_address(IO_address),\n        .IO_byte_enable(IO_byte_enable),\n        .IO_read_data(IO_read_data),\n        .IO_read_strobe(IO_read_strobe),\n        .IO_ready(IO_ready),\n        .IO_write_data(IO_write_data),\n        .IO_write_strobe(IO_write_strobe),\n        .Reset(Reset),\n        .TRACE_data_access(TRACE_data_access),\n        .TRACE_data_address(TRACE_data_address),\n        .TRACE_data_byte_enable(TRACE_data_byte_enable),\n        .TRACE_data_read(TRACE_data_read),\n        .TRACE_data_write(TRACE_data_write),\n        .TRACE_data_write_value(TRACE_data_write_value),\n        .TRACE_dcache_hit(TRACE_dcache_hit),\n        .TRACE_dcache_rdy(TRACE_dcache_rdy),\n        .TRACE_dcache_read(TRACE_dcache_read),\n        .TRACE_dcache_req(TRACE_dcache_req),\n        .TRACE_delay_slot(TRACE_delay_slot),\n        .TRACE_ex_piperun(TRACE_ex_piperun),\n        .TRACE_exception_kind(TRACE_exception_kind),\n        .TRACE_exception_taken(TRACE_exception_taken),\n        .TRACE_icache_hit(TRACE_icache_hit),\n        .TRACE_icache_rdy(TRACE_icache_rdy),\n        .TRACE_icache_req(TRACE_icache_req),\n        .TRACE_instruction(TRACE_instruction),\n        .TRACE_jump_hit(TRACE_jump_hit),\n        .TRACE_jump_taken(TRACE_jump_taken),\n        .TRACE_mb_halted(TRACE_mb_halted),\n        .TRACE_mem_piperun(TRACE_mem_piperun),\n        .TRACE_msr_reg(TRACE_msr_reg),\n        .TRACE_new_reg_value(TRACE_new_reg_value),\n        .TRACE_of_piperun(TRACE_of_piperun),\n        .TRACE_pc(TRACE_pc),\n        .TRACE_pid_reg(TRACE_pid_reg),\n        .TRACE_reg_addr(TRACE_reg_addr),\n        .TRACE_reg_write(TRACE_reg_write),\n        .TRACE_valid_instr(TRACE_valid_instr));\nendmodule\n", "num_lines": 174}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_a0a4_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_a0a4_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(16384),\n    .C_READ_DEPTH_A(16384),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(16384),\n    .C_READ_DEPTH_B(16384),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"16\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     19.660986 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_a0a4_second_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_a0a4_second_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(8192),\n    .C_READ_DEPTH_A(8192),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(8192),\n    .C_READ_DEPTH_B(8192),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"8\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     17.246228 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_a0a4.bd\n//Design : bd_a0a4\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_a0a4,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_a0a4,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_c_microblaze_mcs.hwdef\" *) \nmodule bd_a0a4\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_a0a4_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_a0a4_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_a0a4 lmb_bram_I bd_a0a4 second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_a0a4_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_a0a4_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_a0a4_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_a0a4_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_a0a4_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_a0a4 dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_a0a4_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_a0a4_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_a0a4_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_a0a4_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_a0a4_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_a0a4.bd\n//Design : bd_a0a4\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_a0a4,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_a0a4,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_c_microblaze_mcs.hwdef\" *) \nmodule bd_a0a4\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_a0a4_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_a0a4_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_a0a4 lmb_bram_I bd_a0a4 second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_a0a4_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_a0a4_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_a0a4_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_a0a4_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_a0a4_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_a0a4 dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_a0a4_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_a0a4_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_a0a4_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_a0a4_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_a0a4_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_c_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_a0a4_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_a0a4 inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 225}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n(* X_CORE_INFO = \"bd_a0a4,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"ddr4_core_c_microblaze_mcs,bd_a0a4,{}\" *)\n(* CORE_GENERATION_INFO = \"ddr4_core_c_microblaze_mcs,bd_a0a4,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze_mcs,x_ipVersion=3.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,JTAG_CHAIN=2,MICROBLAZE_INSTANCE=microblaze_0,AVOID_PRIMITIVES=0,PATH=mcs_0,FREQ=100.0,OPTIMIZATION=1,DEBUG_ENABLED=0,USE_BSCAN=0,BSCANID=76547328,TRACE=1,ECC=0,MEMSIZE=98304,MEMTYPE=0,USE_IO_BUS=1,USE_UART_RX=0,USE_UART_TX=0,UART_BAUDRATE=9600,UART_PROG_BAUDRATE=0,UART_DATA_BITS=8,UART_USE_PARITY\\\n=0,UART_ODD_PARITY=0,UART_RX_INTERRUPT=0,UART_TX_INTERRUPT=0,UART_ERROR_INTERRUPT=0,USE_FIT1=0,FIT1_No_CLOCKS=6216,FIT1_INTERRUPT=0,USE_FIT2=0,FIT2_No_CLOCKS=6216,FIT2_INTERRUPT=0,USE_FIT3=0,FIT3_No_CLOCKS=6216,FIT3_INTERRUPT=0,USE_FIT4=0,FIT4_No_CLOCKS=6216,FIT4_INTERRUPT=0,USE_PIT1=0,PIT1_SIZE=32,PIT1_READABLE=1,PIT1_PRESCALER=0,PIT1_INTERRUPT=0,USE_PIT2=0,PIT2_SIZE=32,PIT2_READABLE=1,PIT2_PRESCALER=0,PIT2_INTERRUPT=0,USE_PIT3=0,PIT3_SIZE=32,PIT3_READABLE=1,PIT3_PRESCALER=0,PIT3_INTERRUPT=0,US\\\nE_PIT4=0,PIT4_SIZE=32,PIT4_READABLE=1,PIT4_PRESCALER=0,PIT4_INTERRUPT=0,USE_GPO1=0,GPO1_SIZE=32,GPO1_INIT=0x00000000,USE_GPO2=0,GPO2_SIZE=32,GPO2_INIT=0x00000000,USE_GPO3=0,GPO3_SIZE=32,GPO3_INIT=0x00000000,USE_GPO4=0,GPO4_SIZE=32,GPO4_INIT=0x00000000,USE_GPI1=0,GPI1_SIZE=32,GPI1_INTERRUPT=0,USE_GPI2=0,GPI2_SIZE=32,GPI2_INTERRUPT=0,USE_GPI3=0,GPI3_SIZE=32,GPI3_INTERRUPT=0,USE_GPI4=0,GPI4_SIZE=32,GPI4_INTERRUPT=0,INTC_USE_EXT_INTR=0,INTC_INTR_SIZE=1,INTC_LEVEL_EDGE=0x0000,INTC_POSITIVE=0xFFFF,INT\\\nC_ASYNC_INTR=0xFFFF,INTC_NUM_SYNC_FF=2,Component_Name=ddr4_core_c_microblaze_mcs,USE_BOARD_FLOW=false,CLK_BOARD_INTERFACE=Custom,RESET_BOARD_INTERFACE=Custom,GPIO1_BOARD_INTERFACE=Custom,GPIO2_BOARD_INTERFACE=Custom,GPIO3_BOARD_INTERFACE=Custom,GPIO4_BOARD_INTERFACE=Custom,UART_BOARD_INTERFACE=Custom}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_c_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_a0a4_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_a0a4 inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 229}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_d2ea_wrapper.bd\n//Design : bd_d2ea_wrapper\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule bd_d2ea_wrapper\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  input Clk;\n  output IO_addr_strobe;\n  output [31:0]IO_address;\n  output [3:0]IO_byte_enable;\n  input [31:0]IO_read_data;\n  output IO_read_strobe;\n  input IO_ready;\n  output [31:0]IO_write_data;\n  output IO_write_strobe;\n  input Reset;\n  output TRACE_data_access;\n  output [0:31]TRACE_data_address;\n  output [0:3]TRACE_data_byte_enable;\n  output TRACE_data_read;\n  output TRACE_data_write;\n  output [0:31]TRACE_data_write_value;\n  output TRACE_dcache_hit;\n  output TRACE_dcache_rdy;\n  output TRACE_dcache_read;\n  output TRACE_dcache_req;\n  output TRACE_delay_slot;\n  output TRACE_ex_piperun;\n  output [0:4]TRACE_exception_kind;\n  output TRACE_exception_taken;\n  output TRACE_icache_hit;\n  output TRACE_icache_rdy;\n  output TRACE_icache_req;\n  output [0:31]TRACE_instruction;\n  output TRACE_jump_hit;\n  output TRACE_jump_taken;\n  output TRACE_mb_halted;\n  output TRACE_mem_piperun;\n  output [0:14]TRACE_msr_reg;\n  output [0:31]TRACE_new_reg_value;\n  output TRACE_of_piperun;\n  output [0:31]TRACE_pc;\n  output [0:7]TRACE_pid_reg;\n  output [0:4]TRACE_reg_addr;\n  output TRACE_reg_write;\n  output TRACE_valid_instr;\n\n  wire Clk;\n  wire IO_addr_strobe;\n  wire [31:0]IO_address;\n  wire [3:0]IO_byte_enable;\n  wire [31:0]IO_read_data;\n  wire IO_read_strobe;\n  wire IO_ready;\n  wire [31:0]IO_write_data;\n  wire IO_write_strobe;\n  wire Reset;\n  wire TRACE_data_access;\n  wire [0:31]TRACE_data_address;\n  wire [0:3]TRACE_data_byte_enable;\n  wire TRACE_data_read;\n  wire TRACE_data_write;\n  wire [0:31]TRACE_data_write_value;\n  wire TRACE_dcache_hit;\n  wire TRACE_dcache_rdy;\n  wire TRACE_dcache_read;\n  wire TRACE_dcache_req;\n  wire TRACE_delay_slot;\n  wire TRACE_ex_piperun;\n  wire [0:4]TRACE_exception_kind;\n  wire TRACE_exception_taken;\n  wire TRACE_icache_hit;\n  wire TRACE_icache_rdy;\n  wire TRACE_icache_req;\n  wire [0:31]TRACE_instruction;\n  wire TRACE_jump_hit;\n  wire TRACE_jump_taken;\n  wire TRACE_mb_halted;\n  wire TRACE_mem_piperun;\n  wire [0:14]TRACE_msr_reg;\n  wire [0:31]TRACE_new_reg_value;\n  wire TRACE_of_piperun;\n  wire [0:31]TRACE_pc;\n  wire [0:7]TRACE_pid_reg;\n  wire [0:4]TRACE_reg_addr;\n  wire TRACE_reg_write;\n  wire TRACE_valid_instr;\n\n  bd_d2ea bd_d2ea_i\n       (.Clk(Clk),\n        .IO_addr_strobe(IO_addr_strobe),\n        .IO_address(IO_address),\n        .IO_byte_enable(IO_byte_enable),\n        .IO_read_data(IO_read_data),\n        .IO_read_strobe(IO_read_strobe),\n        .IO_ready(IO_ready),\n        .IO_write_data(IO_write_data),\n        .IO_write_strobe(IO_write_strobe),\n        .Reset(Reset),\n        .TRACE_data_access(TRACE_data_access),\n        .TRACE_data_address(TRACE_data_address),\n        .TRACE_data_byte_enable(TRACE_data_byte_enable),\n        .TRACE_data_read(TRACE_data_read),\n        .TRACE_data_write(TRACE_data_write),\n        .TRACE_data_write_value(TRACE_data_write_value),\n        .TRACE_dcache_hit(TRACE_dcache_hit),\n        .TRACE_dcache_rdy(TRACE_dcache_rdy),\n        .TRACE_dcache_read(TRACE_dcache_read),\n        .TRACE_dcache_req(TRACE_dcache_req),\n        .TRACE_delay_slot(TRACE_delay_slot),\n        .TRACE_ex_piperun(TRACE_ex_piperun),\n        .TRACE_exception_kind(TRACE_exception_kind),\n        .TRACE_exception_taken(TRACE_exception_taken),\n        .TRACE_icache_hit(TRACE_icache_hit),\n        .TRACE_icache_rdy(TRACE_icache_rdy),\n        .TRACE_icache_req(TRACE_icache_req),\n        .TRACE_instruction(TRACE_instruction),\n        .TRACE_jump_hit(TRACE_jump_hit),\n        .TRACE_jump_taken(TRACE_jump_taken),\n        .TRACE_mb_halted(TRACE_mb_halted),\n        .TRACE_mem_piperun(TRACE_mem_piperun),\n        .TRACE_msr_reg(TRACE_msr_reg),\n        .TRACE_new_reg_value(TRACE_new_reg_value),\n        .TRACE_of_piperun(TRACE_of_piperun),\n        .TRACE_pc(TRACE_pc),\n        .TRACE_pid_reg(TRACE_pid_reg),\n        .TRACE_reg_addr(TRACE_reg_addr),\n        .TRACE_reg_write(TRACE_reg_write),\n        .TRACE_valid_instr(TRACE_valid_instr));\nendmodule\n", "num_lines": 174}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_d2ea_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_d2ea_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(16384),\n    .C_READ_DEPTH_A(16384),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(16384),\n    .C_READ_DEPTH_B(16384),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"16\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     19.660986 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_d2ea_second_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_d2ea_second_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(8192),\n    .C_READ_DEPTH_A(8192),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(8192),\n    .C_READ_DEPTH_B(8192),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"8\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     17.246228 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_d2ea.bd\n//Design : bd_d2ea\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_d2ea,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_d2ea,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_d_microblaze_mcs.hwdef\" *) \nmodule bd_d2ea\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_d2ea_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_d2ea_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_d2ea lmb_bram_I bd_d2ea second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_d2ea_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_d2ea_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_d2ea_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_d2ea_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_d2ea_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_d2ea dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_d2ea_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_d2ea_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_d2ea_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_d2ea_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_d2ea_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_d2ea.bd\n//Design : bd_d2ea\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_d2ea,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_d2ea,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_d_microblaze_mcs.hwdef\" *) \nmodule bd_d2ea\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_d2ea_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_d2ea_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_d2ea lmb_bram_I bd_d2ea second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_d2ea_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_d2ea_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_d2ea_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_d2ea_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_d2ea_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_d2ea dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_d2ea_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_d2ea_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_d2ea_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_d2ea_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_d2ea_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_d_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_d2ea_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_d2ea inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 225}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n(* X_CORE_INFO = \"bd_d2ea,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"ddr4_core_d_microblaze_mcs,bd_d2ea,{}\" *)\n(* CORE_GENERATION_INFO = \"ddr4_core_d_microblaze_mcs,bd_d2ea,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze_mcs,x_ipVersion=3.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,JTAG_CHAIN=2,MICROBLAZE_INSTANCE=microblaze_0,AVOID_PRIMITIVES=0,PATH=mcs_0,FREQ=100.0,OPTIMIZATION=1,DEBUG_ENABLED=0,USE_BSCAN=0,BSCANID=76547328,TRACE=1,ECC=0,MEMSIZE=98304,MEMTYPE=0,USE_IO_BUS=1,USE_UART_RX=0,USE_UART_TX=0,UART_BAUDRATE=9600,UART_PROG_BAUDRATE=0,UART_DATA_BITS=8,UART_USE_PARITY\\\n=0,UART_ODD_PARITY=0,UART_RX_INTERRUPT=0,UART_TX_INTERRUPT=0,UART_ERROR_INTERRUPT=0,USE_FIT1=0,FIT1_No_CLOCKS=6216,FIT1_INTERRUPT=0,USE_FIT2=0,FIT2_No_CLOCKS=6216,FIT2_INTERRUPT=0,USE_FIT3=0,FIT3_No_CLOCKS=6216,FIT3_INTERRUPT=0,USE_FIT4=0,FIT4_No_CLOCKS=6216,FIT4_INTERRUPT=0,USE_PIT1=0,PIT1_SIZE=32,PIT1_READABLE=1,PIT1_PRESCALER=0,PIT1_INTERRUPT=0,USE_PIT2=0,PIT2_SIZE=32,PIT2_READABLE=1,PIT2_PRESCALER=0,PIT2_INTERRUPT=0,USE_PIT3=0,PIT3_SIZE=32,PIT3_READABLE=1,PIT3_PRESCALER=0,PIT3_INTERRUPT=0,US\\\nE_PIT4=0,PIT4_SIZE=32,PIT4_READABLE=1,PIT4_PRESCALER=0,PIT4_INTERRUPT=0,USE_GPO1=0,GPO1_SIZE=32,GPO1_INIT=0x00000000,USE_GPO2=0,GPO2_SIZE=32,GPO2_INIT=0x00000000,USE_GPO3=0,GPO3_SIZE=32,GPO3_INIT=0x00000000,USE_GPO4=0,GPO4_SIZE=32,GPO4_INIT=0x00000000,USE_GPI1=0,GPI1_SIZE=32,GPI1_INTERRUPT=0,USE_GPI2=0,GPI2_SIZE=32,GPI2_INTERRUPT=0,USE_GPI3=0,GPI3_SIZE=32,GPI3_INTERRUPT=0,USE_GPI4=0,GPI4_SIZE=32,GPI4_INTERRUPT=0,INTC_USE_EXT_INTR=0,INTC_INTR_SIZE=1,INTC_LEVEL_EDGE=0x0000,INTC_POSITIVE=0xFFFF,INT\\\nC_ASYNC_INTR=0xFFFF,INTC_NUM_SYNC_FF=2,Component_Name=ddr4_core_d_microblaze_mcs,USE_BOARD_FLOW=false,CLK_BOARD_INTERFACE=Custom,RESET_BOARD_INTERFACE=Custom,GPIO1_BOARD_INTERFACE=Custom,GPIO2_BOARD_INTERFACE=Custom,GPIO3_BOARD_INTERFACE=Custom,GPIO4_BOARD_INTERFACE=Custom,UART_BOARD_INTERFACE=Custom}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_d_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_d2ea_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_d2ea inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 229}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_master #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_SUPPORTS_NARROW = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1,\n   parameter [C_AXI_ADDR_WIDTH-1:0] C_AXI_ADDR = 0,  // Base address\n   parameter integer C_NUM_ADDR = 1,  // Number of address iterations; range 1..2**16 (fixed increment = 32'h10000\n   parameter integer C_NUM_ID = 1,  // Number of ID iterations; range 1..2**C_ID_WIDTH (base = 0; fixed increment = 1)\n   parameter integer C_NUM_LEN = 1,  // Number of LEN iterations; range 1..9 (base = 0; value = 2**i - 1)\n   parameter integer C_NUM_TRANS = 1  // Number of transactions; range >=1 (read and write)\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_awvalid,\n  input  wire                            m_axi_awready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_awburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_awlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_awlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_awid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]    m_axi_awuser = 'b0,\n  /**************** Write Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_wid,\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]      m_axi_wdata,\n  (* dont_touch=\"true\" *) output reg [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb = {(C_AXI_DATA_WIDTH/8){1'b1}},\n  (* dont_touch=\"true\" *) output wire                             m_axi_wvalid,\n  input  wire                            m_axi_wready,\n  (* dont_touch=\"true\" *) output wire                             m_axi_wlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]     m_axi_wuser = 'b0,\n  /**************** Write Response Channel Signals ****************/\n  input  wire [2-1:0]                    m_axi_bresp,\n  input  wire                            m_axi_bvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_bready,\n  input  wire [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]     m_axi_buser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_bid,\n  /**************** Read Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_arvalid,\n  input  wire                            m_axi_arready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_arburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_arlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_arlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_arid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]    m_axi_aruser = 'b0,\n  /**************** Read Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]      m_axi_rdata,\n  input  wire [2-1:0]                    m_axi_rresp,\n  input  wire                            m_axi_rvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_rready,\n  input  wire                            m_axi_rlast,\n  input  wire [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]     m_axi_ruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_rid,\n  /**************** System Signals ****************/\n  input  wire                            aclk,\n  input  wire                            aresetn\n  );\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n  localparam integer  P_NUM_ID_LOG = f_ceil_log2(C_NUM_ID);\n  localparam integer  P_NUM_ADDR_LOG = f_ceil_log2(C_NUM_ADDR);\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL==0 ? 8 : C_AXI_PROTOCOL==1 ? 4 : 1);\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer               P_M_AXI_DATA_BYTES = (C_AXI_DATA_WIDTH / 8);\n  localparam integer               P_M_AXI_DONE_WIDTH = f_ceil_log2(C_NUM_TRANS<2?2:C_NUM_TRANS);\n  localparam integer               P_M_AXI_SIZE = f_ceil_log2(C_AXI_DATA_WIDTH)-3;\n\n  /**************** Internal Wires/Regs - Global ****************/\n   wire                            done;\n    wire                            dummy ;\n  reg                         done_i;\n  reg                         done_sel;\n  wire                         done_cycle;\n  reg                          done_d1 = 1'b0;\n  reg                   areset = 1'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] arcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] rcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [3:0]                    acc_r_i = 4'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] awcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] wcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] bcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [2:0]                    acc_b_i = 3'b0;\n\n  // Register Reset\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    \n    /**************** Internal Wires/Regs - Read Channels ****************/\n    wire                         read_xaction_done_i;\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_arid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_ADDR_WIDTH:0]      araddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  arprot_i = 3'b0;\n    reg [3-1:0]                  arsize_i = 3'b0;\n    reg [2-1:0]                  arburst_i = 2'b0;\n    reg [4-1:0]                  arcache_i = 4'b0;\n    reg [2-1:0]                  arlock_i = 2'b0;\n    reg [P_LEN_WIDTH-1:0]     arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [4-1:0]                  arqos_i = 4'b0;\n    reg [P_ID_WIDTH-1:0]        arid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [2-1:0]                  rresp_i = 2'b00;\n    reg [C_AXI_RUSER_WIDTH:0]   ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      rid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_arvalid_i = 1'b0;\n    reg                        m_axi_rready_i = 1'b0;\n    reg [P_NUM_ADDR_LOG:0]    araddr_cnt = 0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign read_xaction_done_i = m_axi_rvalid && m_axi_rready_i && ((C_AXI_PROTOCOL==2)?1'b1:m_axi_rlast);\n    assign m_axi_arvalid = m_axi_arvalid_i;\n    assign m_axi_rready = m_axi_rready_i;\n    assign m_axi_araddr = m_axi_araddr_i;\n    assign m_axi_arlen = m_axi_arlen_i;\n    always @(posedge aclk) begin\n      m_axi_arprot <= dummy ? arprot_i : 3'b000;\n      m_axi_arsize <= dummy ? arsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_arburst <= dummy ? arburst_i : 2'b01;\n      m_axi_arlock <= dummy ? arlock_i : 1'b0;\n      m_axi_arcache <= dummy ? arcache_i : 4'h3;\n      m_axi_arqos <= dummy  ? arqos_i : 4'h0;\n      m_axi_aruser <= dummy ? aruser_i : 0;\n    end\n  \n    //**********************************************\n    // Read Channel: ARVALID, ARADDR, ARLEN, RREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_arvalid_i <= 1'b0;\n        arcnt_i <= C_NUM_TRANS;\n        m_axi_arlen_i <= 0;\n        m_axi_araddr_i <= C_AXI_ADDR;\n        m_axi_arid_i <= 1;\n        araddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_arready & m_axi_arvalid_i) begin\n          arcnt_i <= arcnt_i - 1;\n          if (araddr_cnt == 1) begin\n            m_axi_araddr_i <= dummy ? araddr_i : C_AXI_ADDR;\n            araddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_araddr_i <= m_axi_araddr_i + 32'h10000;\n            araddr_cnt <= araddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_arlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_arlen_i <= dummy ? arlen_i : 0;\n          end else begin\n            m_axi_arlen_i <= (m_axi_arlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_arid_i == C_NUM_ID)) begin\n            m_axi_arid <= dummy ? arid_i : 0;\n            m_axi_arid_i <= 1;\n          end else begin\n            m_axi_arid <= m_axi_arid_i;\n            m_axi_arid_i <= m_axi_arid_i + 1;\n          end\n          if (arcnt_i == 1) begin\n            m_axi_arvalid_i <= 1'b0;\n          end\n        end else if (arcnt_i != 0) begin\n          m_axi_arvalid_i <= 1'b1;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      araddr_i <= {araddr_i, ~araddr_i[C_AXI_ADDR_WIDTH]};\n      arprot_i <= {arprot_i, ~arprot_i[3-1]};\n      arlen_i <= {arlen_i, ~arlen_i[P_LEN_WIDTH-1]};\n      arsize_i <= {arsize_i, ~arsize_i[3-1]};\n      arburst_i <= {arburst_i, ~arburst_i[2-1]};\n      arlock_i <= {arlock_i, ~arlock_i[2-1]};\n      arcache_i <= {arcache_i, ~arcache_i[4-1]};\n      arqos_i <= {arqos_i, ~arqos_i[4-1]};\n      aruser_i <= {aruser_i, ~aruser_i[C_AXI_ARUSER_WIDTH]};\n      arid_i <= {arid_i, ~arid_i[P_ID_WIDTH-1]};\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        m_axi_rready_i <= 1'b0;\n        rcnt_i <= C_NUM_TRANS;\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        rresp_i <= {2{1'b0}};\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n        rid_i <= {P_ID_WIDTH{1'b0}};\n        acc_r_i <= 4'b0;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_rvalid & m_axi_rready_i) begin\n          m_axi_rready_i <= 1'b0;\n          rdata_i <= m_axi_rdata;\n            acc_r_i[0] <= rdata_i[0];\n          rresp_i <= m_axi_rresp;\n            acc_r_i[1] <= rresp_i[0];\n          ruser_i <= m_axi_ruser;\n            acc_r_i[2] <= ruser_i[0];\n          rid_i <= m_axi_rid;\n            acc_r_i[3] <= rid_i[0];\n          if (m_axi_rlast) begin\n            rcnt_i <= rcnt_i - 1;\n          end\n        end else begin\n          rdata_i <= rdata_i>>1;\n          rresp_i <= rresp_i>>1;\n          ruser_i <= ruser_i>>1;\n          rid_i <= rid_i>>1;\n          acc_r_i <= acc_r_i>>1;\n          if (m_axi_rvalid) begin\n            m_axi_rready_i <= 1'b1;\n          end\n        end\n      end\n    end\n    \n    assign dummy = rdata_i[0];\n    \n    \n\n    /**************** Internal Wires/Regs - Write Channels ****************/\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_awid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [8-1:0]                  xfer_w_i = 8'h00;\n    wire                         write_burst_done_i;\n    reg [C_AXI_ADDR_WIDTH:0]      awaddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  awprot_i = 3'b0;\n    reg [P_LEN_WIDTH-1:0]     awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [3-1:0]                  awsize_i = 3'b0;\n    reg [2-1:0]                  awburst_i = 2'b0;\n    reg [4-1:0]                  awcache_i = 4'b0;\n    reg [2-1:0]                  awlock_i = 2'b0;\n    reg [4-1:0]                  awqos_i = 4'b0;\n    reg [P_ID_WIDTH:0]        awid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_AWUSER_WIDTH:0]    awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg [P_M_AXI_DATA_BYTES-1:0] wstrb_i = {P_M_AXI_DATA_BYTES{1'b1}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]        wid_i = {P_ID_WIDTH{1'b0}};\n    reg [2-1:0]                  bresp_i = 2'b00;\n    reg [C_AXI_BUSER_WIDTH:0]   buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      bid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_awvalid_i = 1'b0;\n    reg                        m_axi_wvalid_i = 1'b0;\n    reg                        m_axi_bready_i = 1'b0;\n    reg                        m_axi_wlast_i = 1'b0;\n    reg                        m_axi_wid_i = {P_ID_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]     wlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [P_NUM_ADDR_LOG:0]    awaddr_cnt = 0;\n  \n    /**************** Assign Write Channel Outputs ****************/\n    assign m_axi_wdata = {wdata_i, done};\n    assign write_burst_done_i = m_axi_wready && m_axi_wvalid_i && ((C_AXI_PROTOCOL==2) || m_axi_wlast_i);\n    assign m_axi_awvalid = m_axi_awvalid_i;\n    assign m_axi_wvalid = m_axi_wvalid_i;\n    assign m_axi_bready = m_axi_bready_i;\n    assign m_axi_wlast = m_axi_wlast_i;\n    assign m_axi_awaddr = m_axi_awaddr_i;\n    assign m_axi_awlen = m_axi_awlen_i;\n    assign m_axi_wid = m_axi_wid_i;\n    always @(posedge aclk) begin\n      m_axi_awprot <= dummy ? awprot_i : 3'b000;\n      m_axi_awsize <= dummy ? awsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_awburst <= dummy ? awburst_i : 2'b01;\n      m_axi_awlock <= dummy ? awlock_i : 1'b0;\n      m_axi_awcache <= dummy ? awcache_i : 4'h3;\n      m_axi_awqos <= dummy ? awqos_i : 4'h0;\n      m_axi_wstrb <= dummy ? wstrb_i : {P_M_AXI_DATA_BYTES{1'b1}};\n      m_axi_awuser <= dummy ?  awuser_i : 0;\n      m_axi_wuser <= dummy ?  wuser_i : 0;\n    end\n  \n    //**********************************************\n    // Write Channel: AWVALID, AWADDR, AWLEN, WVALID, WLAST, BREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_awvalid_i <= 1'b0;\n        m_axi_wvalid_i <= 1'b0;\n        awcnt_i <= C_NUM_TRANS;\n        wcnt_i <= C_NUM_TRANS;\n        xfer_w_i <= 8'h00;\n        m_axi_awlen_i <= 0;\n        m_axi_awaddr_i <= C_AXI_ADDR;\n        m_axi_awid_i <= 1;\n        m_axi_wid_i <= 0;\n        m_axi_wlast_i <= 1'b0;\n        wlen_i <= 0;\n        wid_i <= 0;\n        awaddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_awvalid_i <= 1'b0;\n          awcnt_i <= awcnt_i - 1;\n          if (awaddr_cnt == 1) begin\n            m_axi_awaddr_i <= dummy ? awaddr_i : C_AXI_ADDR;\n            awaddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_awaddr_i <= m_axi_awaddr_i + 32'h10000;\n            awaddr_cnt <= awaddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_awlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_awlen_i <= dummy ? awlen_i : 0;\n          end else begin\n            m_axi_awlen_i <= (m_axi_awlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_awid_i == C_NUM_ID)) begin\n            m_axi_awid <= dummy ? awid_i : 0;\n            m_axi_awid_i <= 1;\n          end else begin\n            m_axi_awid <= m_axi_awid_i;\n            m_axi_awid_i <= m_axi_awid_i + 1;\n          end\n        end else if (~m_axi_wvalid_i) begin\n          if (awcnt_i != 0) begin\n            m_axi_awvalid_i <= 1'b1;\n          end\n        end\n  \n        /**************** Write Data Channel ****************/\n\n        if (m_axi_wready && m_axi_wvalid_i) begin\n          xfer_w_i <= xfer_w_i - 1'b1;\n          if (m_axi_wlast_i) begin\n            m_axi_wvalid_i <= 1'b0;\n            wcnt_i <= wcnt_i - 1'b1;\n          end else begin\n            m_axi_wlast_i <=  (xfer_w_i == 1);\n          end\n        end else if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_wvalid_i <= 1'b1;\n          xfer_w_i <= m_axi_awlen_i;\n          m_axi_wlast_i <= (m_axi_awlen_i==0);\n          m_axi_wid_i <= m_axi_awid_i;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: WDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        wdata_i <= (m_axi_wvalid_i && m_axi_wready) ? {wdata_i[C_AXI_DATA_WIDTH-2 : 0], ~wdata_i[C_AXI_DATA_WIDTH-1]} : wdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      awaddr_i <= {awaddr_i, ~awaddr_i[C_AXI_ADDR_WIDTH]};\n      awprot_i <= {awprot_i[3-2:0], ~awprot_i[3-1]};\n      wstrb_i <= {wstrb_i, ~wstrb_i[C_AXI_DATA_WIDTH/8-1]};\n      awlen_i <= {awlen_i, ~awlen_i[P_LEN_WIDTH-1]};\n      awsize_i <= {awsize_i, ~awsize_i[3-1]};\n      awburst_i <= {awburst_i, ~awburst_i[2-1]};\n      awlock_i <= {awlock_i, ~awlock_i[2-1]};\n      awcache_i <= {awcache_i, ~awcache_i[4-1]};\n      awqos_i <= {awqos_i, ~awqos_i[4-1]};\n      awid_i <= {awid_i, ~awid_i[P_ID_WIDTH-1]};\n      awuser_i <= {awuser_i, ~awuser_i[C_AXI_AWUSER_WIDTH]};\n      wuser_i <= {wuser_i, ~wuser_i[C_AXI_WUSER_WIDTH]};\n    end\n  \n    //**********************************************\n    // Write Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_bready_i <= 1'b0;\n        bcnt_i <= C_NUM_TRANS;\n        bresp_i <= {2{1'b0}};\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n        bid_i <= {P_ID_WIDTH{1'b0}};\n        acc_b_i <= 3'b0;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_bvalid & m_axi_bready_i) begin\n          m_axi_bready_i <= 1'b0;\n          bresp_i <= m_axi_bresp;\n            acc_b_i[0] <= bresp_i[0];\n          buser_i <= m_axi_buser;\n            acc_b_i[1] <= buser_i[0];\n          bid_i <= m_axi_bid;\n            acc_b_i[2] <= bid_i[0];\n          bcnt_i <= bcnt_i - 1;\n        end else begin\n          bresp_i <= bresp_i>>1;\n          buser_i <= buser_i>>1;\n          bid_i <= bid_i>>1;\n          acc_b_i <= acc_b_i>>1;\n          if (m_axi_bvalid) begin\n            m_axi_bready_i <= 1'b1;\n          end\n        end\n      end\n    end\n\n\n  //**********************************************\n  // Assert Done\n  //**********************************************\n  always @(posedge aclk) begin\n    if (~aresetn) begin\n      done_d1 <= 1'b0;\n    end else begin\n      done_d1 <= done_i;\n    end\n  end\n\n  assign done = done_sel ? done_i : done_d1;\n  assign done_cycle = done_i & ~done_d1;\n  \n  always @ * begin\n    if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_readonly_done\n       done_i = rcnt_i==0;\n       done_sel = acc_r_i[0];\n    end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_writeonly_done\n       done_i = bcnt_i==0;\n       done_sel = acc_b_i[0];\n    end else begin : gen_readwrite_done\n       done_i = (rcnt_i==0) && (bcnt_i==0);\n       done_sel = acc_r_i[0] ^ acc_b_i[0];\n    end\n  end\n  \nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n  input  wire [3-1:0]                   s_axi_awprot,\n  input  wire                           s_axi_awvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_awready,\n  input  wire [3-1:0]                   s_axi_awsize,\n  input  wire [2-1:0]                   s_axi_awburst,\n  input  wire [4-1:0]                   s_axi_awcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_awlen,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_awlock,\n  input  wire [4-1:0]                   s_axi_awqos,\n  input  wire [4-1:0]                   s_axi_awregion,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_awid,\n  input  wire [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]   s_axi_awuser,\n  /**************** Write Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n  input  wire                           s_axi_wvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_wready,\n  input  wire                           s_axi_wlast,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_wid,\n  input  wire [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]    s_axi_wuser,\n  /**************** Write Response Channel Signals ****************/\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_bresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_bvalid,\n  input  wire                           s_axi_bready,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]    s_axi_buser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_bid = 'b0,\n  /**************** Read Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n  input  wire [3-1:0]                   s_axi_arprot,\n  input  wire                           s_axi_arvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_arready,\n  input  wire [3-1:0]                   s_axi_arsize,\n  input  wire [2-1:0]                   s_axi_arburst,\n  input  wire [4-1:0]                   s_axi_arcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_arlock,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_arlen,\n  input  wire [4-1:0]                   s_axi_arqos,\n  input  wire [4-1:0]                   s_axi_arregion,\n  input  wire [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]   s_axi_aruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_arid,\n  /**************** Read Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_rresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rvalid,\n  input  wire                           s_axi_rready,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]    s_axi_ruser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_rid = 'b0,\n  /**************** System Signals ****************/\n  input  wire                           aclk,\n  input  wire                           aresetn\n   );\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL == 1) ? 4 : 8;\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer P_S_AXI_DATA_BYTES = 32/8;\n  localparam integer P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n\n  /**************** Internal Wires/Regs - Global ****************/\n  reg                   areset = 1'b0;\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    /**************** Internal Wires/Regs - Read Channels ****************/\n    reg [8-1:0]                   xfer_r_cnt = 8'h00;\n    reg [16-1:0]                  arcnt_i = 16'h0000;\n    wire                          read_xaction_done_i;\n    reg [C_AXI_DATA_WIDTH-1:0]     rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]      arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg                           arvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     araddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   arprot_i = 3'b000;\n    reg [3-1:0]                   arsize_i = 3'b000;\n    reg [2-1:0]                   arburst_i = 2'b00;\n    reg [4-1:0]                   arcache_i = 4'b0000;\n    reg [1-1:0]     arlock_i = 1'b0;\n    reg [4-1:0]                   arqos_i = 4'b0000;\n    reg [4-1:0]                   arregion_i = 4'b0000;\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_RUSER_WIDTH:0]     ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_ar_i = 9'b0;\n    reg                           s_axi_rvalid_i = 1'b0;\n    reg                           s_axi_arready_i = 1'b0;\n    reg                           s_axi_rlast_i = 1'b0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign s_axi_rdata = rdata_i;\n    assign read_xaction_done_i = (s_axi_rready && s_axi_rvalid_i && s_axi_rlast_i);\n    assign s_axi_rvalid = s_axi_rvalid_i;\n    assign s_axi_arready = s_axi_arready_i;\n    assign s_axi_rlast = s_axi_rlast_i;\n    //**********************************************\n    // Read Channel: ARREADY, RVALID, RLAST, RID\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        xfer_r_cnt <= 8'h00;\n        arcnt_i <= 16'h0000;\n        arlen_i <= {P_LEN_WIDTH{1'b0}};\n        s_axi_rlast_i <= 1'b0;\n      end else begin\n        /**************** Read Address Channel ****************/\n        // arready\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_arready_i <= 1'b0;\n          arcnt_i <= arcnt_i + 1'b1;\n        end else if (~s_axi_rvalid_i) begin\n          s_axi_arready_i <= 1'b1;\n        end\n  \n        /**************** Read Data Channel ****************/\n        // rvalid\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_rvalid_i <= 1'b1;\n          s_axi_rid <= s_axi_arid;\n          s_axi_ruser <= ruser_i;\n        end else if(read_xaction_done_i) begin\n          s_axi_rvalid_i <= 1'b0;\n        end\n  \n        // rlast\n        if(s_axi_rready && s_axi_rvalid_i) begin\n          xfer_r_cnt <= xfer_r_cnt - 1;\n          if(xfer_r_cnt == 1) begin\n            s_axi_rlast_i <= 1'b1;\n          end\n        end else if(s_axi_arready_i && s_axi_arvalid) begin\n          xfer_r_cnt <= s_axi_arlen;\n          s_axi_rlast_i <= (s_axi_arlen==0);\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Read Channel: RDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        rdata_i <= (s_axi_rready && s_axi_rvalid_i) ? {rdata_i[C_AXI_DATA_WIDTH-2 : 0], ~rdata_i[C_AXI_DATA_WIDTH-1]} : rdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_rresp <= {2{1'b0}};\n      end else if (~s_axi_rvalid_i) begin\n        s_axi_rresp <= {acc_ar_i[0], 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n      end else begin\n        ruser_i <= (s_axi_arready_i && s_axi_arvalid) ? {ruser_i, ~ruser_i[C_AXI_RUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        araddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        arprot_i <= {3{1'b0}};\n        arsize_i <= {3{1'b0}};\n        arburst_i <= {2{1'b0}};\n        arcache_i <= {4{1'b0}};\n        arlock_i <= {1{1'b0}};\n        arqos_i <= {4{1'b0}};\n        arregion_i <= {4{1'b0}};\n        aruser_i <= {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n        acc_ar_i <= 9'b0;\n      end else if (s_axi_arvalid) begin\n        // Register Inputs\n        araddr_i <= s_axi_araddr;\n          acc_ar_i[0] <= araddr_i[0];\n        arprot_i <= s_axi_arprot;\n          acc_ar_i[1] <= arprot_i[0];\n        arsize_i <= s_axi_arsize;\n          acc_ar_i[2] <= arsize_i[0];\n        arburst_i <= s_axi_arburst;\n          acc_ar_i[3] <= arburst_i[0];\n        arcache_i <= s_axi_arcache;\n          acc_ar_i[4] <= arcache_i[0];\n        arlock_i <= s_axi_arlock;\n          acc_ar_i[5] <= arlock_i[0];\n        arqos_i <= s_axi_arqos;\n          acc_ar_i[6] <= arqos_i[0];\n        arregion_i <= s_axi_arregion;\n          acc_ar_i[7] <= arregion_i[0];\n        aruser_i <= s_axi_aruser;\n          acc_ar_i[8] <= aruser_i[0];\n      end else begin\n        araddr_i <= araddr_i>>1;\n        arprot_i <= arprot_i>>1;\n        arsize_i <= arsize_i>>1;\n        arburst_i <= arburst_i>>1;\n        arcache_i <= arcache_i>>1;\n        arlock_i <= arlock_i>>1;\n        arqos_i <= arqos_i>>1;\n        arregion_i <= arregion_i>>1;\n        aruser_i <= aruser_i>>1;\n        acc_ar_i <= acc_ar_i>>1;\n      end\n    end\n  \n  \n    /**************** Internal Wires/Regs - Write Channels ****************/\n    wire                          write_burst_done_i;\n    reg [16-1:0]                  awcnt_i = 16'h0000;\n    reg                           awvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     awaddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   awprot_i = 3'b000;\n    reg [3-1:0]                   awsize_i = 3'b000;\n    reg [2-1:0]                   awburst_i = 2'b00;\n    reg [4-1:0]                   awcache_i = 4'b0000;\n    reg [P_LEN_WIDTH-1:0]      awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [1-1:0]     awlock_i = 1'b0;\n    reg [4-1:0]                   awqos_i = 4'b0000;\n    reg [4-1:0]                   awregion_i = 4'b0000;\n    reg [C_AXI_AWUSER_WIDTH:0]     awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg                           wvalid_i = 1'b0;\n    reg [C_AXI_DATA_WIDTH-1:0]     wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH/8-1:0]   wstrb_i = {(C_AXI_DATA_WIDTH/8){1'b0}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_BUSER_WIDTH:0]     buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_aw_i = 9'b0;\n    reg [3:0]                     acc_w_i = 4'b0;\n    reg                           s_axi_bvalid_i = 1'b0;\n    reg                           s_axi_awready_i = 1'b0;\n    reg                           s_axi_wready_i = 1'b0;\n    /**************** Assign Write Channel Outputs ****************/\n    assign write_burst_done_i =s_axi_wready_i && s_axi_wvalid && ((C_AXI_PROTOCOL == 2) ? 1'b1 : s_axi_wlast);\n    assign s_axi_bvalid = s_axi_bvalid_i;\n    assign s_axi_awready = s_axi_awready_i;\n    assign s_axi_wready = s_axi_wready_i;\n  \n    //**********************************************\n    // Write Channel: AWREADY, WREADY, BVALID, BID\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awcnt_i <= 16'h0000;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        /**************** Write Address Channel ****************/\n        // awready\n        if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_awready_i <= 1'b0;\n          awcnt_i <= awcnt_i + 1'b1;\n          s_axi_bid <= s_axi_awid;\n          s_axi_buser <= buser_i;\n        end else if(~s_axi_wready_i & ~s_axi_bvalid_i) begin\n          s_axi_awready_i <= 1'b1;\n        end\n  \n        /**************** Write Data Channel ****************/\n        // wready\n        if(write_burst_done_i) begin\n          s_axi_wready_i <= 1'b0;\n        end else if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_wready_i <= 1'b1;\n        end\n  \n        /**************** Write Response Channel ****************/\n        // bvalid\n        if(write_burst_done_i) begin\n          s_axi_bvalid_i <= 1'b1;\n        end else if(s_axi_bready && s_axi_bvalid_i) begin\n          s_axi_bvalid_i <= 1'b0;\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Write Channel: BRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_bresp <= {2{1'b0}};\n      end else if (~s_axi_bvalid_i) begin\n        s_axi_bresp <= {(acc_aw_i[0] ^ acc_w_i[0]), 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: BUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (aresetn) begin\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n      end else begin\n        buser_i <= (s_axi_awready_i && s_axi_awvalid) ? {buser_i, ~buser_i[C_AXI_BUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Write Address Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awaddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        awprot_i <= {3{1'b0}};\n        awsize_i <= {3{1'b0}};\n        awburst_i <= {2{1'b0}};\n        awcache_i <= {4{1'b0}};\n        awlen_i <= {P_LEN_WIDTH{1'b0}};\n        awlock_i <= {1{1'b0}};\n        awqos_i <= {4{1'b0}};\n        awregion_i <= {4{1'b0}};\n        awuser_i <= {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n        acc_aw_i <= 9'b0;\n      end else if (s_axi_awvalid) begin\n        // Register Inputs\n        awaddr_i <= s_axi_awaddr;\n          acc_aw_i[0] <= awaddr_i[0];\n        awprot_i <= s_axi_awprot;\n          acc_aw_i[1] <= awprot_i[0];\n        awsize_i <= s_axi_awsize;\n          acc_aw_i[2] <= awsize_i[0];\n        awburst_i <= s_axi_awburst;\n          acc_aw_i[3] <= awburst_i[0];\n        awcache_i <= s_axi_awcache;\n          acc_aw_i[4] <= awcache_i[0];\n        awlock_i <= s_axi_awlock;\n          acc_aw_i[5] <= awlock_i[0];\n        awqos_i <= s_axi_awqos;\n          acc_aw_i[6] <= awqos_i[0];\n        awregion_i <= s_axi_awregion;\n          acc_aw_i[7] <= awregion_i[0];\n        awuser_i <= s_axi_awuser;\n          acc_aw_i[8] <= awuser_i[0];\n      end else begin\n        awaddr_i <= awaddr_i>>1;\n        awprot_i <= awprot_i>>1;\n        awsize_i <= awsize_i>>1;\n        awburst_i <= awburst_i>>1;\n        awcache_i <= awcache_i>>1;\n        awlock_i <= awlock_i>>1;\n        awqos_i <= awqos_i>>1;\n        awregion_i <= awregion_i>>1;\n        awuser_i <= awuser_i>>1;\n        acc_aw_i <= acc_aw_i>>1;\n      end\n    end\n  \n    //**********************************************\n    // Write Data Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        wstrb_i <= {(C_AXI_DATA_WIDTH/8){1'b0}};\n        wuser_i <= {(C_AXI_WUSER_WIDTH+1){1'b0}};\n        acc_w_i <= 4'b0;\n      end else if (s_axi_wvalid) begin\n        // Register Inputs\n        wdata_i <= s_axi_wdata;\n          acc_w_i[0] <= wdata_i[0];\n        wstrb_i <= s_axi_wstrb;\n          acc_w_i[1] <= wstrb_i[0];\n        wuser_i <= s_axi_wuser;\n          acc_w_i[2] <= wuser_i[0];\n      end else begin\n        wdata_i <= wdata_i>>1;\n        wstrb_i <= wstrb_i>>1;\n        wuser_i <= wuser_i>>1;\n        acc_w_i <= acc_w_i>>1;\n      end\n    end\n  \nendmodule\n\n\n\n//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_22_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \n(* autopipeline_module=\"yes\" *)\nmodule axi_register_slice_v2_1_22_auto_slr #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n    wire                    handshake_pipe;\n    wire                    ready_pipe;\n    wire [C_DATA_WIDTH-1:0] payload_pipe;\n    (* keep=\"true\" *)                                                                reg  s_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  s_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  s_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  s_areset_resp2 = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  m_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  m_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_areset_resp2 = 1'b0;\n    \n  // Global Reset pipelining\n  \n    always @(posedge ACLK) begin\n      s_aclear       <= ~ARESETN;\n      s_areset_fwd   <= ~ARESETN; \n      s_areset_resp  <= s_areset_fwd;  // Auto-pipeline\n      s_areset_resp2 <= s_areset_resp; // Auto-pipeline\n    end\n    \n    always @(posedge ACLK) begin\n      m_aclear       <= ~ARESETN;\n      m_areset_fwd   <= ~ARESETN; \n      m_areset_resp  <= m_areset_fwd;  // Auto-pipeline\n      m_areset_resp2 <= m_areset_resp; // Auto-pipeline\n    end\n    \n  // Source-side submodule\n    \n    axi_register_slice_v2_1_22_auto_src #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_src\n      (\n       .ACLK             (ACLK),    \n       .s_aclear         (s_aclear),\n       .s_areset_resp2   (s_areset_resp2),  \n       .S_VALID          (S_VALID),  \n       .S_READY          (S_READY), \n       .S_PAYLOAD_DATA   (S_PAYLOAD_DATA),\n       .ready_pipe        (ready_pipe), \n       .handshake_pipe    (handshake_pipe),\n       .payload_pipe      (payload_pipe)  \n      );\n    \n  // Destination-side submodule\n    \n    axi_register_slice_v2_1_22_auto_dest #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_dest\n      (\n       .ACLK           (ACLK),    \n       .m_aclear       (m_aclear),\n       .m_areset_resp2 (m_areset_resp2),  \n       .M_READY        (M_READY), \n       .M_VALID        (M_VALID),  \n       .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n       .handshake_pipe  (handshake_pipe),\n       .ready_pipe      (ready_pipe),  \n       .payload_pipe    (payload_pipe)  \n      );\n    \nendmodule  // auto_slr\n\nmodule axi_register_slice_v2_1_22_auto_src #\n  (\n   parameter integer C_DATA_WIDTH = 32\n  )\n  (\n   input  wire ACLK,\n   input  wire s_aclear,\n   input  wire s_areset_resp2,\n   input  wire S_VALID,\n   input  wire ready_pipe,\n   output wire S_READY,\n   output wire handshake_pipe,\n   output wire  [C_DATA_WIDTH-1:0] payload_pipe,\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA\n   );\n    \n   (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  [C_DATA_WIDTH-1:0] payload_pipe_r;\n    (* keep=\"true\" *) reg [2:0] s_aresetn_resp4 = 3'b000;\n    wire s_aresetn_resp3;\n    wire s_aresetn_d;\n    wire s_aresetn_q;\n    wire s_handshake_d;\n    wire s_ready_i;\n    \n    assign S_READY = s_ready_i & s_aresetn_q;\n    assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;\n    assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;\n    assign payload_pipe = payload_pipe_r;\n    \n    always @(posedge ACLK or posedge s_aclear) begin\n      if (s_aclear) begin\n        s_aresetn_resp4 <= 3'b000;\n      end else begin\n        s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      payload_pipe_r <= S_PAYLOAD_DATA;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) s_aresetn_resp3_inst (\n        .Q   (s_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~s_areset_resp2)\n     );\n    \n    // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (s_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_aresetn_d)\n     );\n    \n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (handshake_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_handshake_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (s_ready_i),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (ready_pipe)\n     );\n    \nendmodule  // auto_src\n\nmodule axi_register_slice_v2_1_22_auto_dest #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   input  wire ACLK,\n   input  wire m_aclear,\n   input  wire m_areset_resp2,\n   input  wire M_READY,\n   input  wire handshake_pipe,\n   output wire ready_pipe,\n   output wire M_VALID,\n   input  wire [C_DATA_WIDTH-1:0] payload_pipe,\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n   );\n    \n    (* keep=\"true\" *) reg [2:0] m_aresetn_resp4 = 3'b000;\n    wire m_aresetn_resp3;\n    wire m_aresetn_d;\n    wire m_aresetn_q;\n    wire m_valid_i;\n    wire pop;\n    wire m_ready_d;\n    wire m_handshake_q;\n    reg  [C_DATA_WIDTH-1:0] m_payload_q;\n    \n    assign M_VALID = m_valid_i;\n    assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;\n    assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;\n    assign pop     = M_READY & m_valid_i;\n    \n    always @(posedge ACLK or posedge m_aclear) begin\n      if (m_aclear) begin\n        m_aresetn_resp4 <= 3'b000;\n      end else begin\n        m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      m_payload_q <= payload_pipe;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) m_aresetn_resp3_inst (\n        .Q   (m_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~m_areset_resp2)\n     );\n    \n    // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (m_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_aresetn_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (m_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (handshake_pipe)\n     );\n    \n    (* autopipeline_group=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (ready_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_ready_d)\n     );\n    \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  (5)  \n      )\n      srl_fifo\n      (\n       .aclk    (ACLK),    \n       .areset  (~m_aresetn_q),\n       .aclear  (m_aclear),  \n       .s_mesg  (m_payload_q),  \n       .s_valid (m_handshake_q), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      );\n    \nendmodule  // auto_dest\n\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      reg s_valid_d;\n      reg s_ready_d = 1'b0;\n      reg s_ready_reg = 1'b0;\n      reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_22_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_RESP_MIDDLE2_LATENCY = C_PIPELINES_SLAVE + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_22_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      .ACLK           (ACLK),\n      .ARESETN         (ARESETN),\n      .S_PAYLOAD_DATA (S_PAYLOAD_DATA),\n      .S_VALID        (S_VALID),\n      .S_READY        (S_READY),\n      .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n      .M_VALID        (M_VALID),\n      .M_READY        (M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_reset;\n    wire src_ready;\n    wire dummy_reset;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  ( C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( dummy_reset   ) ,\n        .laguna_s_reset_in  ( src_reset   ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset   ) ,\n        .laguna_m_reset_in  ( src_reset  ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset2   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n      \n  end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] mid_payload;\n    wire mid_handshake;\n    wire mid_ready;\n    wire mid_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n    wire dummy_reset3;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( mid_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( mid_reset    ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset3   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset3   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out (  dummy_reset2  ) ,\n        .laguna_m_reset_in  ( mid_reset   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE2_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( mid_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2   ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset3   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset3    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n   \n  generate\n\n  (* keep=\"true\" *) reg s_reset_dd = 1'b0;\n  (* keep=\"true\" *) reg m_reset_dd = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n  \n  assign laguna_s_reset_out = laguna_s_reset_out_i;\n  assign laguna_m_reset_out = laguna_m_reset_out_i;\n  \n  always @(posedge ACLK) begin\n    laguna_s_reset_in_d <= laguna_s_reset_in;\n    laguna_m_reset_in_d <= laguna_m_reset_in;\n    s_reset_dd <= laguna_s_reset_in_d;\n    m_reset_dd <= laguna_m_reset_in_d;\n    laguna_s_reset_out_i <= C_PIPELINES==0 ? laguna_m_reset_in_d : m_reset_dd;\n    laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;\n  end\n  \n  wire ACLEAR;\n  assign ACLEAR = ~ARESETN;\n  \n  if (1) begin : common\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire laguna_s_handshake_q;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, laguna_m_ready_d}; \n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else if (p==C_PIPELINES+1) begin\n          laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n\n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = handshake_i[C_PIPELINES];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_m_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* keep=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_22_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_m_reset_out = laguna_m_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_m_reset_in_d <= laguna_m_reset_in;\n      aresetn_d <= C_CHANNEL==P_FORWARD ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? areset_dly[15]  : laguna_m_reset_in_d;\n      laguna_m_reset_out_i <= areset_d;  // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n  \n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* keep=\"true\" *)  reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      ready_d <= {ready_d, laguna_m_ready_d}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid_q;\n      assign payload_valid_d = (p==0) ? (S_VALID & s_ready_i) : handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==C_PIPELINES) begin\n          laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else if (p==0) begin\n          payload_data <= S_PAYLOAD_DATA;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n      \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_s_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* keep=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_s_reset_out = laguna_s_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_s_reset_in_d <= laguna_s_reset_in;\n      aresetn_d <= C_CHANNEL==P_RESPONSE ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? laguna_s_reset_in_d : areset_dly[15];\n      laguna_s_reset_out_i <= areset_d;  // For forward channels, reflect laguna_s_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n\n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    wire laguna_s_handshake_q;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      laguna_s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n        \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n        \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)  \n      )\n      srl_fifo_0\n      (\n       .aclk    (ACLK),    \n       .areset  (areset_d),  \n       .aclear  (ACLEAR),\n       .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n       .s_valid (push), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      ); \n  \n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  reg areset_d = 1'b0;\n  reg [3:0] areset_dly = 4'b0;\n  always @(posedge ACLK) begin\n    areset_dly <= {4{~ARESETN}} | (areset_dly<<1);\n    areset_d <= areset_dly[3];\n  end\n  \n  if (1) begin : common\n    reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID & s_ready_i;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* keep=\"true\" *)  reg payload_valid = 1'b0;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          payload_data <= S_PAYLOAD_DATA;\n          payload_valid <= S_VALID & s_ready_i & ~areset_d;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n          payload_valid <= handshake_i[((p>0)?(p-1):0)];\n        end\n      end\n    end\n    \n    if (C_PIPELINES==0) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),\n         .aclear  (1'b0),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire                        aclear,  // Async clear\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    wire [1:0] state;  // State vector register\n    reg  [1:0] next;           // Next state value\n    wire [1:0] next_qual;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    reg  m_valid_d;\n    wire m_valid_q;\n    \n    assign m_valid = m_valid_q;\n    assign next_qual = areset ? K_EMPTY : next;\n    assign m_mesg  = mesg_reg;\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_mvalid_inst (\n        .Q   (m_valid_q),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (m_valid_d)\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state0_inst (\n        .Q   (state[0]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[0])\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state1_inst (\n        .Q   (state[1]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[1])\n     );\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      m_valid_d = m_valid_q & ~areset;\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid & ~areset) begin\n            next = K_HAS1;\n            m_valid_d = 1'b0;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              m_valid_d = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n              m_valid_d = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          m_valid_d = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      (* keep_hierarchy = \"yes\" *) axi_register_slice_v2_1_22_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule  // axic_reg_srl_fifo\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   //   16 -> Auto-pipelining\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_RESERVE_MODE = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n  \n  if (C_RESERVE_MODE==1) begin : gen_reserve_si\n  \n    axi_register_slice_v2_1_22_test_slave #(\n      .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n      .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n      .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n      .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n      .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n      .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n      .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n      .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n      .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .s_axi_awaddr(s_axi_awaddr),\n      .s_axi_awprot(s_axi_awprot),\n      .s_axi_awvalid(s_axi_awvalid),\n      .s_axi_awready(s_axi_awready),\n      .s_axi_awsize(s_axi_awsize),\n      .s_axi_awburst(s_axi_awburst),\n      .s_axi_awcache(s_axi_awcache),\n      .s_axi_awlen(s_axi_awlen),\n      .s_axi_awlock(s_axi_awlock),\n      .s_axi_awqos(s_axi_awqos),\n      .s_axi_awregion(s_axi_awregion),\n      .s_axi_awid(s_axi_awid),\n      .s_axi_awuser(s_axi_awuser),\n      .s_axi_wdata(s_axi_wdata),\n      .s_axi_wstrb(s_axi_wstrb),\n      .s_axi_wvalid(s_axi_wvalid),\n      .s_axi_wready(s_axi_wready),\n      .s_axi_wlast(s_axi_wlast),\n      .s_axi_wid(s_axi_wid),\n      .s_axi_wuser(s_axi_wuser),\n      .s_axi_bresp(s_axi_bresp),\n      .s_axi_bvalid(s_axi_bvalid),\n      .s_axi_bready(s_axi_bready),\n      .s_axi_buser(s_axi_buser),\n      .s_axi_bid(s_axi_bid),\n      .s_axi_araddr(s_axi_araddr),\n      .s_axi_arprot(s_axi_arprot),\n      .s_axi_arvalid(s_axi_arvalid),\n      .s_axi_arready(s_axi_arready),\n      .s_axi_arsize(s_axi_arsize),\n      .s_axi_arburst(s_axi_arburst),\n      .s_axi_arcache(s_axi_arcache),\n      .s_axi_arlock(s_axi_arlock),\n      .s_axi_arlen(s_axi_arlen),\n      .s_axi_arqos(s_axi_arqos),\n      .s_axi_arregion(s_axi_arregion),\n      .s_axi_aruser(s_axi_aruser),\n      .s_axi_arid(s_axi_arid),\n      .s_axi_rdata(s_axi_rdata),\n      .s_axi_rresp(s_axi_rresp),\n      .s_axi_rvalid(s_axi_rvalid),\n      .s_axi_rready(s_axi_rready),\n      .s_axi_rlast(s_axi_rlast),\n      .s_axi_ruser(s_axi_ruser),\n      .s_axi_rid(s_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign m_axi_awid     = 0;\n     assign m_axi_awaddr   = 0;\n     assign m_axi_awlen    = 0;\n     assign m_axi_awsize   = 0;\n     assign m_axi_awburst  = 0;\n     assign m_axi_awlock   = 0;\n     assign m_axi_awcache  = 0;\n     assign m_axi_awprot   = 0;\n     assign m_axi_awregion = 0;\n     assign m_axi_awqos    = 0;\n     assign m_axi_awuser   = 0;\n     assign m_axi_awvalid  = 0;\n     assign m_axi_wid      = 0;\n     assign m_axi_wdata    = 0;\n     assign m_axi_wstrb    = 0;\n     assign m_axi_wlast    = 0;\n     assign m_axi_wuser    = 0;\n     assign m_axi_wvalid   = 0;\n     assign m_axi_bready   = 0;\n     assign m_axi_arid     = 0;\n     assign m_axi_araddr   = 0;\n     assign m_axi_arlen    = 0;\n     assign m_axi_arsize   = 0;\n     assign m_axi_arburst  = 0;\n     assign m_axi_arlock   = 0;\n     assign m_axi_arcache  = 0;\n     assign m_axi_arprot   = 0;\n     assign m_axi_arregion = 0;\n     assign m_axi_arqos    = 0;\n     assign m_axi_aruser   = 0;\n     assign m_axi_arvalid  = 0;\n     assign m_axi_rready   = 0;\n      \n  end else if (C_RESERVE_MODE==2) begin : gen_reserve_mi\n    \n    axi_register_slice_v2_1_22_test_master #(\n    .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n    .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .m_axi_awaddr(m_axi_awaddr),\n      .m_axi_awprot(m_axi_awprot),\n      .m_axi_awvalid(m_axi_awvalid),\n      .m_axi_awready(m_axi_awready),\n      .m_axi_awsize(m_axi_awsize),\n      .m_axi_awburst(m_axi_awburst),\n      .m_axi_awcache(m_axi_awcache),\n      .m_axi_awlen(m_axi_awlen),\n      .m_axi_awlock(m_axi_awlock),\n      .m_axi_awqos(m_axi_awqos),\n      .m_axi_awid(m_axi_awid),\n      .m_axi_awuser(m_axi_awuser),\n      .m_axi_wid(m_axi_wid),\n      .m_axi_wdata(m_axi_wdata),\n      .m_axi_wstrb(m_axi_wstrb),\n      .m_axi_wvalid(m_axi_wvalid),\n      .m_axi_wready(m_axi_wready),\n      .m_axi_wlast(m_axi_wlast),\n      .m_axi_wuser(m_axi_wuser),\n      .m_axi_bresp(m_axi_bresp),\n      .m_axi_bvalid(m_axi_bvalid),\n      .m_axi_bready(m_axi_bready),\n      .m_axi_buser(m_axi_buser),\n      .m_axi_bid(m_axi_bid),\n      .m_axi_araddr(m_axi_araddr),\n      .m_axi_arprot(m_axi_arprot),\n      .m_axi_arvalid(m_axi_arvalid),\n      .m_axi_arready(m_axi_arready),\n      .m_axi_arsize(m_axi_arsize),\n      .m_axi_arburst(m_axi_arburst),\n      .m_axi_arcache(m_axi_arcache),\n      .m_axi_arlen(m_axi_arlen),\n      .m_axi_arlock(m_axi_arlock),\n      .m_axi_arqos(m_axi_arqos),\n      .m_axi_arid(m_axi_arid),\n      .m_axi_aruser(m_axi_aruser),\n      .m_axi_rdata(m_axi_rdata),\n      .m_axi_rresp(m_axi_rresp),\n      .m_axi_rvalid(m_axi_rvalid),\n      .m_axi_rready(m_axi_rready),\n      .m_axi_rlast(m_axi_rlast),\n      .m_axi_ruser(m_axi_ruser),\n      .m_axi_rid(m_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign s_axi_awready = 0;\n     assign s_axi_wready  = 0;\n     assign s_axi_bid     = 0;\n     assign s_axi_bresp   = 0;\n     assign s_axi_buser   = 0;\n     assign s_axi_bvalid  = 0;\n     assign s_axi_arready = 0;\n     assign s_axi_rid     = 0;\n     assign s_axi_rdata   = 0;\n     assign s_axi_rresp   = 0;\n     assign s_axi_rlast   = 0;\n     assign s_axi_ruser   = 0;\n     assign s_axi_rvalid  = 0;\n\n  end else begin : gen_reg_slice  // Any normal reg-slice mode\n\n    axi_infrastructure_v1_1_0_axi2vector #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    axi2vector_0 ( \n      .s_axi_awid      ( s_axi_awid      ) ,\n      .s_axi_awaddr    ( s_axi_awaddr    ) ,\n      .s_axi_awlen     ( s_axi_awlen     ) ,\n      .s_axi_awsize    ( s_axi_awsize    ) ,\n      .s_axi_awburst   ( s_axi_awburst   ) ,\n      .s_axi_awlock    ( s_axi_awlock    ) ,\n      .s_axi_awcache   ( s_axi_awcache   ) ,\n      .s_axi_awprot    ( s_axi_awprot    ) ,\n      .s_axi_awqos     ( s_axi_awqos     ) ,\n      .s_axi_awuser    ( s_axi_awuser    ) ,\n      .s_axi_awregion  ( s_axi_awregion  ) ,\n      .s_axi_wid       ( s_axi_wid       ) ,\n      .s_axi_wdata     ( s_axi_wdata     ) ,\n      .s_axi_wstrb     ( s_axi_wstrb     ) ,\n      .s_axi_wlast     ( s_axi_wlast     ) ,\n      .s_axi_wuser     ( s_axi_wuser     ) ,\n      .s_axi_bid       ( s_axi_bid       ) ,\n      .s_axi_bresp     ( s_axi_bresp     ) ,\n      .s_axi_buser     ( s_axi_buser     ) ,\n      .s_axi_arid      ( s_axi_arid      ) ,\n      .s_axi_araddr    ( s_axi_araddr    ) ,\n      .s_axi_arlen     ( s_axi_arlen     ) ,\n      .s_axi_arsize    ( s_axi_arsize    ) ,\n      .s_axi_arburst   ( s_axi_arburst   ) ,\n      .s_axi_arlock    ( s_axi_arlock    ) ,\n      .s_axi_arcache   ( s_axi_arcache   ) ,\n      .s_axi_arprot    ( s_axi_arprot    ) ,\n      .s_axi_arqos     ( s_axi_arqos     ) ,\n      .s_axi_aruser    ( s_axi_aruser    ) ,\n      .s_axi_arregion  ( s_axi_arregion  ) ,\n      .s_axi_rid       ( s_axi_rid       ) ,\n      .s_axi_rdata     ( s_axi_rdata     ) ,\n      .s_axi_rresp     ( s_axi_rresp     ) ,\n      .s_axi_rlast     ( s_axi_rlast     ) ,\n      .s_axi_ruser     ( s_axi_ruser     ) ,\n      .s_awpayload ( s_awpayload ) ,\n      .s_wpayload  ( s_wpayload  ) ,\n      .s_bpayload  ( s_bpayload  ) ,\n      .s_arpayload ( s_arpayload ) ,\n      .s_rpayload  ( s_rpayload  ) \n    );\n    \n    axi_infrastructure_v1_1_0_vector2axi #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    vector2axi_0 ( \n      .m_awpayload    ( m_awpayload    ) ,\n      .m_wpayload     ( m_wpayload     ) ,\n      .m_bpayload     ( m_bpayload     ) ,\n      .m_arpayload    ( m_arpayload    ) ,\n      .m_rpayload     ( m_rpayload     ) ,\n      .m_axi_awid     ( m_axi_awid     ) ,\n      .m_axi_awaddr   ( m_axi_awaddr   ) ,\n      .m_axi_awlen    ( m_axi_awlen    ) ,\n      .m_axi_awsize   ( m_axi_awsize   ) ,\n      .m_axi_awburst  ( m_axi_awburst  ) ,\n      .m_axi_awlock   ( m_axi_awlock   ) ,\n      .m_axi_awcache  ( m_axi_awcache  ) ,\n      .m_axi_awprot   ( m_axi_awprot   ) ,\n      .m_axi_awqos    ( m_axi_awqos    ) ,\n      .m_axi_awuser   ( m_axi_awuser   ) ,\n      .m_axi_awregion ( m_axi_awregion ) ,\n      .m_axi_wid      ( m_axi_wid      ) ,\n      .m_axi_wdata    ( m_axi_wdata    ) ,\n      .m_axi_wstrb    ( m_axi_wstrb    ) ,\n      .m_axi_wlast    ( m_axi_wlast    ) ,\n      .m_axi_wuser    ( m_axi_wuser    ) ,\n      .m_axi_bid      ( m_axi_bid      ) ,\n      .m_axi_bresp    ( m_axi_bresp    ) ,\n      .m_axi_buser    ( m_axi_buser    ) ,\n      .m_axi_arid     ( m_axi_arid     ) ,\n      .m_axi_araddr   ( m_axi_araddr   ) ,\n      .m_axi_arlen    ( m_axi_arlen    ) ,\n      .m_axi_arsize   ( m_axi_arsize   ) ,\n      .m_axi_arburst  ( m_axi_arburst  ) ,\n      .m_axi_arlock   ( m_axi_arlock   ) ,\n      .m_axi_arcache  ( m_axi_arcache  ) ,\n      .m_axi_arprot   ( m_axi_arprot   ) ,\n      .m_axi_arqos    ( m_axi_arqos    ) ,\n      .m_axi_aruser   ( m_axi_aruser   ) ,\n      .m_axi_arregion ( m_axi_arregion ) ,\n      .m_axi_rid      ( m_axi_rid      ) ,\n      .m_axi_rdata    ( m_axi_rdata    ) ,\n      .m_axi_rresp    ( m_axi_rresp    ) ,\n      .m_axi_rlast    ( m_axi_rlast    ) ,\n      .m_axi_ruser    ( m_axi_ruser    ) \n    );\n    \n  end  // Reserve SI/MI branch\n\n  if ((C_REG_CONFIG_AW <= 9) && (C_RESERVE_MODE==0)) begin : aw\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 15) && (C_RESERVE_MODE==0)) begin : aw15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 16) && (C_RESERVE_MODE==0)) begin : aw16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) \n    )\n    aw_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if ((C_REG_CONFIG_W <= 9) && (C_RESERVE_MODE==0)) begin : w\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 15) && (C_RESERVE_MODE==0)) begin : w15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 16) && (C_RESERVE_MODE==0)) begin : w16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) \n    )\n    w_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if ((C_REG_CONFIG_B <= 9) && (C_RESERVE_MODE==0)) begin : b\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if ((C_REG_CONFIG_B == 15) && (C_RESERVE_MODE==0)) begin : b15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if ((C_REG_CONFIG_B == 16) && (C_RESERVE_MODE==0)) begin : b16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) \n    )\n    b_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if ((C_REG_CONFIG_AR <= 9) && (C_RESERVE_MODE==0)) begin : ar\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 15) && (C_RESERVE_MODE==0)) begin : ar15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 16) && (C_RESERVE_MODE==0)) begin : ar16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) \n    )\n    ar_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if ((C_REG_CONFIG_R <= 9) && (C_RESERVE_MODE==0)) begin : r\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 15) && (C_RESERVE_MODE==0)) begin : r15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 16) && (C_RESERVE_MODE==0)) begin : r16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) \n    )\n    r_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 4844}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule dest_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(9),\n    .C_REG_CONFIG_W(9),\n    .C_REG_CONFIG_B(1),\n    .C_REG_CONFIG_AR(9),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"dest_register_slice,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"dest_register_slice,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=16,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=9,C_REG_CONFIG_W=9\\\n,C_REG_CONFIG_B=1,C_REG_CONFIG_AR=9,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule dest_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(9),\n    .C_REG_CONFIG_W(9),\n    .C_REG_CONFIG_B(1),\n    .C_REG_CONFIG_AR(9),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nXvoWuyjysN5V55U4xsjyWg2bXI++8I1KAZgJ0eiQkY3L8ns1PfNti9fujmr8wvFQA6ycwh4K6mSp\nINQjc8TyLQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nbD05I2IKef08FLVG4C2ftkJOY+/UsvagxY6ta+A0N1USwLQivKTmRt7LJlQ+5UJqrfPvhHMyYrLN\nrjoJbClg85XfNTYCnalRVvg3mmCcjtJkCLf6S5E9Q6UF92b6bwgtMTsr0BndJhdItlJtr0dYZtoP\nAEskMBthh6RdNMkZ3CA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nvLo4Yp/zX6HvZ92VMA2Xr4EIhMWPNGq2EvSBkjiZd5sCSFAX+37MKx4gdbrsGvhUMl1njqvSaoP7\nKrAa29/cm3QWjPgpaCsR/MhnaG5+7aUvxA5iCqVHXdriMlgx9kzxkB9SD+mOC8XR5LtYA0bPhbZ9\njQzWpWxdaOGYFF25DU0O9M7LMc7SLfKunYH/cQ91D37m0LjgZh1/uZv8chFzvCBbkHqUU0qi17/k\nZTWIIzqb1oycbuhZZrWLl95xQ/aaTxZ30sONWd/axZtO3Cd57huCbCxLuOH51qq6erD9AVszmxL8\noEoM+KW88P1S3LJ/EcIQN4LU0/nyN/f7xEmy2w==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nj99ihkoCqIO9DhRZEJdEqlRF2P+IwS2wuYmoh3hWFCDXbmGTwTqc+3EMjxY8Z4uDixuazjlTMiEH\nCk4MdTkVZ55pPhFb4druHTap3Twn20B3SWvOy2nf84OpTkdBnbK4qagABgZXs9/mAtQxbF++/F6Y\n+OOE3yUNTWvHiVGvpTJavfADkB2CL5wEIlBSnYRwtLp71JokDsMvjq2l3o3hxAjvtdg9ej7NKx4I\nkAZfrpZH7Ebv2hfXrTVI2kDTAl5Etr+4oSqxIhABJut2WaeWJrsSbL+dz9s2ZmYDMb1BCQdRexck\nbMMvUaS+P7sSGuR9BTVynHOY5GdQelHO1aazQw==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nHuzbd0U90PuPKn40554Cnki98HuQSq7dg6ZyXufEWFHsji6rteNupAY3HQsuLpXjFVxsNlS4bcHj\nAAOnDcL0hCCVbSkU011mqhhlkFmWqeBBECGfP+T7/+l9KBu+9ynszhlhaVhmZMffsEuohDl5x084\nFnzFCdxrFyvqrOyWDac=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\neoQKmSsNWNEOJcUApe0UhUNGRDkxOLedPbjyDILgUJWMG+WVCpL9MC2MXZeZ6/oVwAYRlZTZsF1h\nUsVo6BO7IAuHuJAHeIQgEs2oIMj/I2qZxm9wUsOzWoK5/Jz4SS4sTE3TgOJXaX1GNAJlbUrCBtnM\nqIiavU164vZjX5BFoPGuHp4kICN8A4Wr9y2w2Lh0/IdiHjr/Ruk5PpVNyl7tW9EaSFY1AL4aoQpd\nRFDdUFRk4tMBtmFxi/B+pLVFE0hAUZnlVCsSaf4B0lN/m4CME7lgy7oXElp7ov4fMnD9VI8HLGMX\nWBSQjD8F6BB0Wblgm9lJNc0h0VqxxD4DbRleKA==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nyrn0K+G4SU1wuMdE7DJlKWErX/N5nCqD3+dP+4ONmo8yuM983VHfjLhCoeQMbM26e49U4PPdXcDR\ny0rRemqJACoi5H5NvzXohhKZI9q+WKME4TkhFzfKvIwyta1m/uNSe/A0+52Dzbg5uAxYihw0IdZR\nZMywfa3deZ8IUMz3kWSlMs1P4wESz2pKpdYGs0FpvovucuNn4OhZKH7RGX8z8Zy4E9juZRgnSQnX\nmvRtisgVB9uL2J0vl9XjW/1990VYZi0nrZJ8gQL38HLTz62vDuMuYjiFbbnDCujJNKOCHh/xJTdt\n73nsz+dY3We4tQdnxuESibzLQLGF1l8+d9FPDA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nJPIGH1v6BG8bvo+3pHrWlum+XEDtFDlKP+4Toq88+g/eeinS/p8A0zMVVYj4wfjGDhx3kGvJ9XAx\ngxYpezvlgnz+IEGWQzepCMSp4iHz9TEdGkc5LTQj50VJj4+HGz2Qhrw96Hw0c+5RDrv238ILy3p7\nuzIPIzxKEl8D7gK6b8ZPrzx95KMPuGZyju4JUHBWdjDx0hhhIl+L3Ju/bVyWaWd7w1xI0mreJtAN\noOdcObOESJpTuj0KqFtfA3UY7v9n9Lj/I/vMaPX7LnSIZuS+tHyiD8D+t+Kf6XiIl3sYDL9erP7t\nSpHvPfG9bOfGRxM7dmsvKj+XqHeXg23wyS1Nfg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nrxmK0sxFw5opGoAsi+RHBRwE0wYNls8LL+oURMgLNuoRDOPNH7up4F86jASnrdlvXLShGHMZnaJ6\ny1orZ0uAZ6xxM2PeKAxvxBI02HOu0aXd/SMNxr16dADlCYK6R1DVdq3DC+T8bQTLWyyHr9r4m4En\nW5DcJ2hEs5b31PUg/DoCNTpHm2swT7sLG9qRkSfTddaSyGTADcvRXYjnHKHin6TQlOCZufWMm54P\nPJeCQmj1MjyycQGpsvFNX7VMxW49ashO7EGmRdy7lMGRoHDqLWBxcIlwAS4L28iuln/NdC/QV538\nQei7EbcqeUmfs07XP8FKxdA3hi3Aq2Upg9DkOw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64736)\n`pragma protect data_block\npJdOORWQloxSGvgvy0l4tBp1HqnYdonsYgNOe99SLH3qi9BP+2tNlaoelqmLJLSHNsBn3TJxXlZa\nnIZxc0/l2jA1h9Jz15QEEgUR0MqZaESeIPQdEbADnul6xUXY0J6g//n8Vnzph99nb1v9j4yp0I8W\nmF2Bvdz/qHJcUcV5zedPk5PkPVS8cmwYFQWer3rOMl6Or1E/YoHi9T9wfbgxxTs6yzqYqVGUBlz5\nAlhSoRF+xXB1Z4h2Ny4v4u05pGtbpnnDj+JhauZ7AfT+uRL3JZ7hNdSiI3coyNU077RtI/1VAmYO\npJoj/3tO2z4y9phvRShE/Otch4qxfx53IywqoRQmUF57yV4NjbkGPW8j7U6iQ8Ls1911ZAOgZIga\nmynl1jCs8ajbsNdraT0wfsPf1kWJOCuUGyItYv2eEwfh7iEYRrpT0V6YT5gENAgDuriQCZuFtnJE\ndhvImjwTXy3d76buWun43bM5pyUNSUzm90uucXHtbfsv8HZTM/chDluZJ4cMeW8D9Pwjtvo6lXLx\nYJM6v2cUpOTIMOcKDxrRTFomRQ1DwRsa4wQGal4q2dhrokLR6YNhu1ED6+AbEAN+FWui25yRPN2c\nRifAbYj3+oa+z6kUON22gegvkiRIe3iVn5MeyImok+P+5dmykiOW6L7J+GDFd4UZtYwJkwUH4ijt\ny9tlvkg7bhgKKY/VRht7EZFg6U4GjUBwLTEWIsD/6R8LgyENKTNO1FVyOJge9+hJYOxJpk93nMac\n0dR2cl0TLESIEfZQ8wSlqKcnzibNa/Mwa+gyj8uNmBtlGMv9GLnh914fnVrJPaJYjkLNLesy5uKF\nWOOHFhlsuqMHkybog57X/W2y+bzzdtaWoQ8/DU/QWGyTt3Vhlmu4YBKvv/DBB51RUj7naprx+CNR\nK7/l3uoheqcD/zy4ipVqZ/mSOTxjqNwJ88tpKUTD7UHuLf8rEeiu80iR1raYJGMHzUS7FcK/APPf\nbBCJIKpjoq1C63MJYurbOeqWcRL3DDPi/z3C66E9WG/nFKs7vMkhbVhClFUAjy+DwMCS7VjbvUvn\nCbr4m+kTXY7ipbBxU7YIDWHssBAAjeM1Rdxx9VvDqABN+rFZAA7C08PNPUeOiVYCFO3gmbAqYK8f\nEPeBaPUk6eskVX2sXw5/qrh1a5mqGk/sYCFZItuYZ6SMz1BFuaZz+ac8Feq8+d7gH2f1DuK4EG20\nOgLh0liUdRk5TCUZsSZTlhRd1FA4SqglWHYk+GIL1WEcVBskAEiY2YIK1TGXzUQaG00TT5TRBNmv\nsPnVI8z6bWwqXomyqcYSelXrfl2izqtjadlA+3+0O2A1XhL9tmMhT3v0nQIlobxn4nFE376czv08\n2+xLHI/chXlg2WvKMK3NCBbWGw7tnHSdJc47JRdiCkb0tIr9wocUbWPbM7W5G3Ku+bQZQXPM0lNy\nstFAjwukEDL4vbC72EJbEwf+6kzkzLjBrc0JDEzvjqnYQYiwloQ0qi9k/yE3bXcnEHvgw8ig5Y/S\nt9SttzL9mNMXwbouRg1seAZ89RrLrTNZiBk2TlhzdIfvWsbvdBYdIhaMqKRGJFpWxZgPm+JbW+09\nfF1z2nf/18EW+WziUuICezISE4+2HDfqFOEltKV6AdesQWDrloYiby+MezSSORPfWkx+nVGv8JEs\nI01podsuoWFRpVmbt/Dua5qZk9EOHGFBRgvYNnlH47YVREn5j8l2T/0bBlGUrv4r0tmSTvb5Rk62\nTtYvXt/3/jJe7TX05O4Uz8CDBe02LhhwyNkyyNYPm6hcqislaGMW5IrlUBR19xoKivY5xsi9WHEp\nOscK7GlXBFf+1ZdqPUIFBzo8CoanS+vY6N5dX/zhH9ka7wSGlru7qjqAyYG3VOzYi+lIUT1D0l0A\nhIuLJhQlgGIPioPMX5r9G+nJX9J1xhmQmslUobJCrtsIfoshA1m3sO8FVq/uKShEPK85uU48DmE1\nBM73G3APR/Pn3q4udJagFjB+ngJWARXqQX1U/fZdrs1d4U8E/KLlkVQywLtM4ImADW15ZRE2zwbt\n93vD21KzRF0gTEp32+Y94DZJmilvEITUz6i6Uf3GIhk/8VlW2sgoZBxyIXdlfZU0hAeWoF6z0y8i\nsz3YJBSL59bOXPeovsUY+1K4JWkThiLh9WlHMd3YfANHBPnf+imIQZm0bk8SniIn386MI5OOzHz4\nE4NRinoFBZ2QveSs8W7mDkgRcm6PoFPVY3QRUGVKM/cdavafi55CMHzsrvtIU+GTn9VIn3xNt55T\nvun82PwGiZ2FiwhlNlG8Wy4O+LFNA76IijNkkamPOoINY3NpvBlYJ4sMSw1dZ/S+Qd509gN+YqK/\njuugLi10dq5ezC717GDkCW4fL6XMF1BLctfTjFHbDnQePKJIiB57aUuvbzah60QCKQnwYsO2mNs3\nlX8Tl9YL68F88dwoxH0JclrQ/K+4uYuofKZNpcUqyesWLZ7Ajkjo1V/LWCNdqLb7jaE2Z0v+PGsJ\nbQ2zY2rbw1xVbkOFkWnJb00IZlS5AfKLW2JwtTjSc9R5cytj7Kj8rVyPRdWixjwHVXwb9oIhCtsZ\nr9zdlcsnNvnrEk8HWDJmg9t+Ss3qdeobuZBvC1qVhW9OeCSeLWFmmlBTM7zlf4bIM7BPobwINrOH\na+x81+t4Xk/8bAWK5b1pfO/q6usi0t9Z1NTJb3ix47MRkhAbStRfFBfBwzDQr/YBXixPzFiRd7RK\nKHM5pI4NGo4x/1eUa3I9iGFb0JwOlvTvmyLF4CY35sdztuKueaGq0YUi4X3SbBVUihPbcPvhcn3q\nULcb1JlytkOdtyHtyrm7/EOiSLmMn3uCPXQDioYj1f6NsIRA8BV+t4V5VK8a2hNJ+Ci6U9tBmG7R\n2AfVDNWXakk0eYIUYcZuIPVd4sH7Be8PANt6YH+bxeZtBfUel13RoATsMc/l+Vz7BvaZ9ZhPoxu0\nMpG5BKJTAuGZ3OqNXDuuvsvuBv8s5hC8JKvLoL76k+rFk8PlyNwEnYoc7nFhCrqDHeOr/8E3maxP\nPv/AiEhEzjU5PQBF457AHnjeQ3eTwpDPSnYJ6nuR0WhnaxbVcRDXmfQc5Pm+RgJOQXySVRlfAtO/\nJmM8oWf9Wd57qYf2P95KvohDPW6vlFW5UOuYJRNedw/Vofmtj6gUXmSUtZzX9x+pGUbZK1L7qaRH\n4Bl+RKLFFF3ULv72pe+uhZoyumhCUE9nTUfh/0bbyfQ0/7E4OjNceJy3IuQXZAelpm4/lyIClM6a\nbcA7XaiUNtUxRgOk+Gm4bXDK/lbpfHAo3ZLrOeIIrJSFdGgfIjMAMcPO2agXDXysM9w0LXX4XzKa\nAk5Ctu+YxqwaE3xbxVfqa3Xiwxzu9RezCh2I21Ysg1ckJugmX+s7525qUeaUizKlxcu5ef5xX40W\nh5pW3QA7UPCugDISw+aX406IO2drov2E5eUNDLRRG/nY7aG606JFGCFgUNVLl22BloATVP6ZeMDr\nmifoHBORyaJvgAndCrygYyJGcy9labne+Cqn0A1qtn323sFNB43FEMX42WIgtgc4oPab1AYsEQum\ns46nWTCUaZAyRO+53Dzben+MOJEy1iKP7o1PMZDKjaQ4Atrpot1Ix9OivbbWL8nNOjFG3rRgc8Tf\nLOVtiwqq/r+IiSB/HQOV/ZHmkDTL9dtw3UFvBE6wRo6XaWDbKDi/T7PaYAC3GGNaQZw3CTXVFb6P\nSvTMYdICAhD7YCZDr6aVLiD1Mgc225aXecHZoluSWOck9HO5ezjlCFCPDSTSj5OnC9v9zUcFbNOa\nri/TT7JdgqdBMKQjvpVrljLeuPPWvSxLMEar6iv8iFwj9w4fIGsSX5D1h0fx53Dosj7c99OjPOKJ\n43ciuUlKmUrl8zGTv1bTsvgQBspvbQjDlKlZcFGKkJ5y+h+FKT7sLG0T7X0OsNyJhlkV8Oh1B7s0\nnzc4JG92kvRVvDmVljLF5q7kSbo4pOg+r9MMh209JANj1imzsRTwNlFhL4KQmOy32YKv975WzfpE\n5gOHTY5gj/9beHVy72SphX1PvZ/GvMrFHu0Q1SdMOxiDJO/8Vv+UogST5Z+pm6YS50RKp917SJLr\npQGNrqMBt2q0TjdKoF10330Oq2OQnGbPQBcF5wAOKor3lUhuKlgi4yfTsE7g0RlphaWiUi0kfQnJ\nxJaR/v3zWkal8YKuqBUOk2zAI58JgLOCGfkeP4lLDigas6lR86dIFm2ehEwWiuUxA0rMWk7MxUFq\nIvlNP2JTSuRX5d7mSS5TdZoich5Z28tzuAxtmfX/HVgsAiDJsXeq2lNJnPI4t7OJcjw+/LTBFn4u\nGkaeVQKsrDg0XjypHHAcx3Htai3F8S3SrSZThLhmNA0UuPAVwrWM/YxdRJdPCFxRV9DIfFLc78ED\nrxRf+2hm2iIX0v9lJubvukxj3RKg3bWedHf9X7fBwzCzmT3xpSVT/orUQHTM7BJi1uX619EAPHfH\nEslFnO9xBhBE/NfxEOIr6puKJWQy0vcdu3KHp/98gdYKgnVg5mCXI4uGSJL+j3Mo34LyWj6jofG1\nRpvUjZOY2WsTY2U7akBl0Uyiv66vuAVFTYtHxbLeKihdYSSxteod2tWquqRvLeBirXL2qi69vijg\n+WXGPNEs1ioW+W6cjl9Kt1V92qIp1LbqTEC9jDdj5VHq36eM3zGGY1FX+VH47w4FoxWcrGaGXkXO\nhGXHGyLwe6ssZ273qYR1N0RhvtgHnAdUHIPdsqqRbjeld0f7uZDVEUjGCA5HvEPmaA4qaz1HEmEX\nMSbcEbGOwM4/lsTSso35cqWlqf9VepPPahniUNw1bY7j79iM/o0F8kJkfL5NumCR5VM7RsWuHT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C99kqfj/UVOTB5eheZdHy7EcqBeNR/+6GsibmPncbobTk24qcaqVJt3wgZyWp0s45X+9wMv8\naq7nxbvk+JD5cuPi785YB4Is1gg85t6bvpA9Qfzb3O9Wk32ecemuYY7hfv+wXPcCciMC61K8t1VJ\nDxofEz9Nxh0L6M2gdZhrIeECMYqp9YunMryNLeqc7YQLvKIjonC1l4sbrYWZ+Vr/tRAksYUVxldM\nWs7rdbIReyHwkW9Q3eVk5tGNZYwsTJZ3LLHqX4k4QW4fN5SrXF7tpu0Nh6B20X5kbA57dL9bI0Mg\ngdCKLlB0s2kqOmSFFGQ2qiGM4gLCtJKTcJvH0QXyq3PoTYgnvqWXAi7962ulHUUvjiqAbTLGRYQR\ngd6pRfridQ9QkVVZ3q8/Wwg9RSEsbZuIJ9bsY3KxRk+Bv/QJmfbw9otM2ufRS79SLoJDUzayREpA\nzPDRjhDoGxRqrI6rV3uPDIkmG/IgiRjrOM3CMltuf+l5zCRv72lm/BooJKYufHaSMAUyCUXJp/Uc\nFu0s9YVH+QVUDZtdn/t+XoUZ1zviEEgoAEoY2VYry4fCJ8DYaSDlP46tShiJjQrOJdERGgL/xQBx\nO6uzJrNrt7Cf6kh0YFyp6QRAfTkuf7kwETESQMUFV2MR8wr0hZHmd/UBOQiPTPb8DscsuSAYh8Zc\nrknuK0zKex9YiHkZeDo7D/PSeuh+WG2d2zJdkM3Td3eMS6WVDFMFl2b5W8/jYjNABrnjK1XwThFh\nYLnSLJi/Op7SthgN17FwYwSwj+AcsR63hVzcnfiVu3ZUXHEZJEyz2HWtWt0RLaZ7MNZccAta93yH\ngOMoJdpfeYUKCCFDGcTyJlFegiSY/R9BWXq/NR5ouF0kpaoEUa+kWjoHoOiSEaQs4XEhSuNjRynD\nrVhVZzcmzBTJAU/E9/o/Hq/uvAStcm39QbP3OeAuNYGNe3sCFCFik9NxiyTW3OEmJSjBcrOnO+Qw\nx7FcS9UJ/wQfURM4P12Z7osL0N6s5Am8NipjMtQyeAtwOcmnJoNC+0+NUiyPWlCuXP/3Z4arSgFa\nZR7xsOv//tsF4wlUna5iH3TC56YNk8nUsFEw6Ge6ZSuhEVsfIeY4wG2IxxjFm7GLEm+Qi2fnWvFp\nirwOxF+K+U92WcMWV9jGmnuJKdDgr9f0rTsSnyJoE6abD5qCwAUSiMOFTLyqf0omOu5SrdwPvxDF\ndftrQ5R+oqkHgkZje/QojcIA5MmPjkCLRdKv8Qe8et8c4lmY6vRi/j86jriaKSwx4Y+Mw85SnPR2\n2j1hg4L1bm3Y95mODLr49QGkDVB7kvY4Qy33Bsp2CTuOWo05KgZSEEXL/7U+fWGzRHjASwfcbgCg\niVFHnASo+4H+F8SItbh9vW9aZB7dvzb/sp41V3sOiSQ/lvFv36hNky3d5TPRgeWxk7ahEnAeBvcU\nN36JNzslIJ0QcFbUJcrGjbreKWGwtRudHbvZZiy3VBuJefbL+K/nA5GKYex5vaF8VvW2JtNaz6nG\nO2mf0K1OaIC26ble9NY9pYrqytCcdTpOisFBK/sWMwJTDavyPDcaK3b2r0z6l8yWe/+kZORkwM1n\n+vS+mBxXx0tf6GtBwKVn9Wq5PBEpboQb7z+jnDgqEVQGEQk44+zDxF6mTiYHaVCLhGP1x2L8Qxtw\nPkf1ixuZGNM5w3J6JjwoYA1WqjGzNXQ/2I4IFQ7+zOL2BVVm8a+5aGNvBOtcu4B12kHIJpqjtEJq\n3tU1eussVADMAsGVV8uDeYtJPvulbF/idSwsgG8crk6BAOKJo99VQxAzmHr6hzse35prsun1dsY+\ntbANM8RyL4weuRCRdH+gaMfEFjRTXyRtKzs19VCSRxpLGUewvAFPajZ9ighUQ2DOA7Kr/rcMTxxd\nrh6hpvfsAFBAQjLiKMsH8ZMXPqNGDBjA8s7TGxd1KmM66Kj1RfzFBtlBuz9LglC/dRn/arEJkYKW\ngOxCUP9SwP1tqpMfyCFKkHci/RYZqmjbNlLH12cl5zMhmsQpiIcZXYfQL8enrVutyHkc8Oplycxn\njTecEx2W4yyRww+b9SpNrQwNcQAZHfUmu5afg1rtbUHZmBW//Afpurxew4MlsTVbE/q+GW4sYS08\n5hT4/ITaA2T979WNydM1h2SItDPecKYro2NCBuNGPCj2smuGGwIqTTedt7kY0lTXqc1QprlIXDOv\n7A/WEW6Ks/DyDbzo5ebBQ9k/Or/ERzVfh5qWgkq8yG0qonueIlbVexyJM/7sKO/BjOR3x/FKDD5A\nPOch29mk1tOqyzjUVo2fdU4B2P5yIWUu4LyA1+iW0TzGEcAlb+9A3LJHWtdxf5XRYSDst39xRNq/\njlN38Ihbn61REmPKmA+LoB8LUMaREXZsyBT2mkJjbCqOmNANgzEAOIj9ceuS25Y2KtrSdejGBdIE\nvCBEfvsJHNzt4EujHKaeJh7o4NDjqLcdEp7ed4Ep3cSOHMCOA874EICbE2zaW5mDE8TG62+kJMaF\nV28mlwI5fMFxipXSTKgVDY4Vj5EWSGuC9St7IfruwsQ039cqwvbAOIuBDwEDSJc6lCmXs/qZhmZt\nnFv7j6yW+vhyh9F/M49mYXMIrZDI2IQn1meVK5DQbu4ISFnSDGJl+UGx+F0w292X7x/NZlrDFxjU\n8F8hH3SoFUjtp3cdqR6J0qgyyvNuJIK0pC2nq9IzjvH1k+PjKgFH3e23kG7suulbVb/rfU+4p0A0\nUw/8qfFdt9ZBcVINnpEPSUJScU20uwWwAzXtPblYceO4Nbetd/Rru6gMmzl4QBV6dHDFv9Llj35m\nrcJlg8L6gZdUkbc5dWUef9LywyJ3ifFwzOukFPVGj0p1G9hRSiNUqdgpYFlexuLPL30vERjJltwu\nf4LrTIZ2VSuuoDz3yvK7YYnre2MTp1IvJIRPF0FnWr5WUuDhARBzNlManehpegpS4ik+5bBOARnk\n2ikf25Ea+euX4IRwUJwiPzAGTUbPzL3cODFaJ4mHcPv972AeFd1T3djc/nkOpMRfzLbUHz1h++GZ\nfguK3eWFxgEnwvmTBOSV/2pqlydJB+j2kzDoBOhHJ7yMYPINzLTm+GvY8+PE6TGpMumpLB79DVsR\nwtH293Qaqs60uwABd29zk+xMrOUEivDU8FIBU3QFpa33/+/A4nI1MVfVSHknip/yEcpuNY2qPJsT\nYuN68cBSWDFeSQJE5yXwjpRVFkSAHd8nML/bKhBZiplgzijzI6AXJOmkqclzuE3gbvl06XzNvh5g\niwbchkuC2q85hHpT3w63G6WwlR9OlnKpzSBsWJI5MiFvl09L3irrYtbw529xtermE/blvOxQYxuJ\nA3+cCbwrhbuASE/lxx/+CQSXsAGEFsG+rJZf02gTem+flBUQWxgYw7USLAXlR/yGYO6KKUiU5mYp\nMcLp5SF0ptsnO4GjOAmsRzhq+nFaThfDeXAXowTEeuWN+d56AInospMZc/eW0bFPTbgOjid6z1Vd\n+9+s7tiYNg6b6j0iAwEiBa8LX50Gz1E8B8Xk0bA4iCfVG+pXzxngp/ZgDAxA6x4B4xS8JSzvBqG9\n3fF/tpaS1x0ZYZNKrC0vl9eX2oeN5I3CbgEuLOUU1xIlzEYHqt8Ta5ZEnYRUtbhiunpXdVyqirCN\n2dgXkldd9U31gMhMY7qFkzBGBtdUApeaRyAGLxKnyg+nwnmirKX9Y3rBKSd6L+R5qhO6n0UbbSzD\n+4en4Cmiy/ti0HItxFAe4vWNWKSwEzlKaZ2HLEPHIUlwN4xiAAyIeXLQP3SyqcvdMzkhMFVdQYhH\nM2F1yAOo3G/JqR2EjrPkiLCy80ya2Cey9fh2IrTFABUwl8LswS7gb3noQTWyDJTWhVsMOvXawU6k\n9W4Jitv0d/+g4QNb1K05p1NtcnLpsIbcTsGei35vIairYz2Wpukkc+QIjcnbRoRYwr386Jd+y7da\n3/zxTz0ylTc2RMTh2TEZRm4kwoCvMb5bRjiCs5p4VDLdB5NKcfMPq/J+LOvbN9BdKd2e8etvM1x9\nZ83qLpzhi7vatfxsU6M1tYzeP0N1fDEQPFerPkzA/sJJfcYa5H+94+uMTRANw63xIlLDhmnCm9fB\nvFsT1znWi0KNE5YxMVAP5Nj3aNk30viM/aEGcXN1+348mdh8cJXP6Se0n9M2ShPtIh6uOzHcNN4F\nXvgZxyI06BOFPCh6pPn8pM/4wkj6M+5Q3d37NGdAT8T8ei4zfuLUhoasw2cJjrdrZ3LNelT1XVzr\ngtfkU+onSthCPR4WS6Xrw7Ok/kkEQoYmkdI7UB9unluvVVQ764ldp5OlFSL6uGJlq53fikq1mMPd\nHtYt08ogxQnb+cC85LdLrpUdkov30YC0DE++eB3VOpsBoGUdgSzOw4L/wn+VuAsCWq5ABwRe4fqT\no7SyMEpq1RX0wDx7yvM1IrLxDdnN/w9pE9XQ1ww/ANlsQf3806Yc1bxBlnH0iwF7F5dr6ExWX02C\nm4GMD+POG+syw7glXgXQ0OUc8vp22qMR4sD57/Oul0voKncx2id8UccXB9vsMZIBhX8NK9iQyJK7\nYG53Y6spKPwBaJ+D6oCzIRdMrl47suvOHOFMlq9EgcKZSM8cW1EeM34Q9wneG+hmi1jxmgRg05WA\nNvs9ns0cBAUoExbeKaTDf+UdQg8kQpTj787x73pVcySGZAe6vE/iMHRuSiZo8GQ7v7UaVF9ntzDG\nTtrPWvFHyuV/SDdzax+LPSONzmqYuZtNNGc7rSFNjipVg81YgVclfSx1PGAIfydo7Z24e3Gz6NIU\nMwj2TtlQKBbeM3mx05abZdGgKr2KZg/G7mtpHcWqPBAwGoOynrpV4ZdlOI7jP3SkujjjiUQJ8FdQ\n9dU1KADRL9hr5MOS92p0+2CDZXdgK1l4EzeYC6fuN9IyAXHsqWhfswpOubjlkJfdxHP/GX3hjyHO\nUvlaWBcZDw7BAWM+AX28BwSssw+yc8sPIxzjHKVjNVz51Vpi6eQgVAZfgVeW/CVd4po9zDauDBPe\nLW3Ffrt6P9FU45qwQ7MWE7oZ3zsTc0evg2krhbb9dLqiCoz6VuCkphBd+BhX2nSPTl+BrGC3EtT8\naS6sDKIiJlBJL+8+GJ5RSEQoTGfqIs6ND98n26dELJI8S0uXSltTPxBhra5yloAd2F4/mmmPjyWr\nTQxaz9QC3JZaY5ciYNddoc6aIflLXGP2kZlT/V1zu+CW+BExE9WpMnVToGI8RRt4jv0a874Y0An6\nHhiPkeDYN6VUowNBrQ5rQnTkFaMpJk4oWUQE3v6avp7Y5alYEE4wCED+ItD2AgaKwC/nFgLMfAnZ\nktUhijy2X1yEewInb5S1xc28GWJeUEjeegaSJijHmFVUCwrnggKTZlbyJ2a2ezSse3QS7DNzMLsw\ns3lvV7VDvQazHXN8RAgvOB0B/CgfYjwZQnyysjBMCOEXr9ltmJw3ogG/vxGHBu667EeL5qOCFKZS\nK2yY/1setEN3lBeyWFiOt84crc97yyhIN9WLadvrh/f0YfzTa8/jZpqi6C6YM8s4vbQgQayL34x2\n47QkQV/JCgk47e027m4LJl2YsaOwIdm0CLnMgOgEGQPFdyZktwDaQcho9eG3wdeeDVrkyzQormhu\n9aXm2HxMwA7LFBoLoLMTe/h9G0EmWJjSZJbpYBym7mGdw7mGASxg/8DfPNQ061R+2X3xcnmG+cIO\nvl0+UTTis+WrgnTXMMvcqbanhkRzuTaNKehiSLRg6bGYM0soIp56mfxn+lCOLxRvrFVCb4SESUTQ\nh41pLzHt1noaHrzs6Gg5F6h/f/xdaHC5qixpm+GAiRp0dMj0xX0roGySULb0Pg5Ik9k6Txub6XiO\nZgO5zmj4Zg5w8I0AnXTXRWRQrHzuRzUxeqeeMsb/JspTSY5oZj06H3vlmxUcBhypLvXrMLcXh/Ls\nc3bNxQvpWzLBqqdhy2tGJ8fAWkun0YPhNwlUU8lBB4Gk06kgUQm222XRVdAheeWAjR8NbiAop06S\n8Wy+XiAj+daeCKkiouMukARqbllP0jcynVe076LG+ZgkcNqoPU37HDyH9n2pGf6ZkAQuwFeIbkSF\nPg4iQ36vkP+KaDnRItQq5Ii+DKzEOXGkFXjeyB2kGs1noDV9eD6DHXsQa0azeB+0c9fKSA7nV4Mx\n1BtiwRMnJT7JPQOciedKCuaoP0Aq+hvnG6MBlo+nAOOlQfvZ8qQxlg0laf4f6XLVWOpAeGt6y0pr\nAw0YlMDiAyvjsrh3t8P4eyWaZSoFPRIJLol9+5QCyrLlm2aVeoMUtwJ1/53pTKnTEHcZIZfi1n7e\npjP+HdzVIccamu4mef1McNibQT4nUfu60LdH+ZQICzwZKDu6slLfWc1KaTXs71UCJzmFmBNREiS2\nXy7c04shnL9MVkGQUM4rVvlqeU7hjpj2FNlt0nq2A7NHDHkEArM25UeIzO+An0jC3tn+qfMDBZmx\npl24RVKkzC2NhWcwhhc3TGrk1gzXt5aE3zkSTGv9pEL/s8V0XrlWQBLq2XFeBXgLpSAzseg2st1r\n71IH25LcYi65u03YZ8TaQSNK5ZQxrVBVO+JVdqF5H+UcYmJxyBsmvTOso+y/z+nGXXnu6Wxeb2K3\nPMCSNT7G7TIbSFmkl2cSMzEeMwmt7AyMdckkJzv6cvcC0j0fLIcJ+ygBucF6mrNY7OMFKMatX0PI\n4UdpryZPtTB7sdMGLH8FqHkw0PoHM+53+V3rRDIo+ImSU7g97SHk4uMmW9/lU3+h4QEVhf1SsCoH\nD9SCjVbJmWSx+5ck3SWahLdUTGE0c66fdQ50VOj3xxA9nvsgL6x8+drW1LZr6SHG4Ma07PvqbId/\ncOHrnVi5FevEja28niNJV/635eMPcCA8uWcnSyTm1J3Fe+CyROmWWUPs1QOJLqlM/Ai2tsSCIaui\nrBVtakmXqv0aMhA33NdtZu3vrog0aJfleoLXQUuDYIGcGc8kfavMyQBG72eZnrVz6/tupr3lLY4Q\nxVGFP4Jxgxq1oFD+d8nf2DrnUh9AyNvtyyOCKi7z+ReLuwDg4jFzd3U9eZQ7WTDxuOYKmerT5+UO\nG4qs6dNLomx30eVvW25a2Z2qtWBywQq/MaVipSr2RmdVavfkdvSb4lRU8c/OXc2j2EjLF9uwD9ij\nR+SremaAbHZZKoNbBX79rPCGwHPTuu2e/3veCG7t4yv5s3WUvVkFPocYD2rO92YBt3DE5NjJ8kgM\nBCj48v+cPe2x069u+Nco6d7scSnHpPHHPSM+6Py5/LgYVagzcTfjK8PlJARVcAMsLJiBvfzpO+zb\na4Rs26CnEdvlCgaKBV1YLeJ2dXWhGAXTQg7SIPEe+qxZanakqfbbb2xT8QLylB2wpP6fAVc2MhM7\n8GAoec89XNo9PAPakTkcl0WxeigJFRkS527gXqWbZigV+8fVkzfLL8ARih7A5Y8faOuGrHTI1D3/\nzLMHy7/g+ESSQUAfGIeRgrKCYK7EMouPFRuxC5uxAYpm5W/pKsdIPrBHWTqvC0PZClvqzFXBi97p\n9keo4Q8i5+/jCqoMSKdh43uf/t7GW8Dcg5wWxhGnjWC7PMUgwEzMeruqNa0zB76K0zeUaOmh69WT\nQE+NgpCq0rrPFoR4W/hxQ5lqPWMYVQs08oixXrdi4qxOlpMbrxoLJ9dbreMCg21g+h8idnl0Tl1L\ntZ5uVIyA0sfNcXr37h71rInz9wjZ2D+cn1MJf9A+S9uhwm3BGTz/4NlrrXLFirxI7VfKkYEQ5kS9\nUmJtizU6dQ6Ehg6JDdHxuh5l52FvU7VuMVMozDJdJMvbkeQHAh3I0RSRxjaUk9t20AqO38NUWado\ngkUnSoEZCLnKpWk0YPx/LgMwFeFUGPMwCcZ+o4LM/G/XVGe5eO/pecve0eHmEnfeVBoIeGUVNgM+\np5FXp1hflAYwWYzb3FqUrZM6TMi1jBAtwoA8RkCsrYN61H3rOO2e29xzDffAshtKB1dXBUfI0Zxp\nVN8o0s2S0sIOL0Z6Y2+38Wn6hSTm9pUH+2vQjPt5mmWo7cg22+s7MbGkZISOJNCM1mCrD3s08ZAJ\nwSe0IXxQ9GoXKl71fWfyxDOEN80E97kYHfLwT/anINNK4DYOqinZPKwL6lPcmfztT/jkkYeC47vc\n2LKundEqdpIO8cT/NlrAVtDH6t3Fm9VABN/HIsAxIiNvOpHUSrLSF1keYvjZzNPJ5FRQgPns+eTv\nGP8JvC15MCNYsPYO03i0V8tim0p2g1ZGaidN0DRZ+8QURKlhGPX747Npc+Sns6GK2hOpqQs5xmC/\nkg05svfxeKyBc+mnkDT3BuW6tl06gkPpjvfgTxknS3UtGnjHnLRzXmIjQMl2IQ0m0gzzccVzi/72\niZtemsxeuumi+UP3MrCWaN+wN9xfBDV49pifJbqDeSGoznX/Zcb2XT9kvtBFWMmlBG27ZlbXviyw\nPnR21Qdpe9Ga3f0oQjJGGlKrEtk8kpZXg8bTyYQAlP0cxQpKZU2EjD5JPPrHfj1jG8shz+Fu/9Ho\nMoczpTM2n3rQNUp7R8v0cHO6ikm9/A1cUv3WjysTiu7SuCs4gBkotSNY2Xk68SXZWzYgFxmK8HXy\ntx9sdKEH13yEbULEXA+4COwl/PywoPj/Nl+Ew4Pwcm3TnoqS0GSPt7HJPOo2hoOxxqB08tPM+X0t\nB9E3nmeN6WGtdPk5mkipZRl6B32i/Zgg+ya/eRdCQdf9fg9Wyl1aioGzWlZgA8sH0At8Y7gl7NYv\nGsBJKYY9eIu3oVdG89uBhlUj0AOPcTOGIyt2OwESMxURJPXjak9Yh0eSBLOasPf3rxt91kWGROIx\njBiT8eMt0OnS2yu5HO2Eg40cmIqsC2vwtJoj9wOdu3zeceXfhMsdMoEsk85U9XUNedzDXBDY+d/K\ni529zO4iKsBwTRgnL3+Qq6lgmFdlFvr4PT7x/PusFTxAe30moNx7vtlthoDXjY69raOtJEVg3oac\nlEa+QrsLiy6szONetja8Xwm35OWq22kBLLd/fhaSvhSgxFNpHlINTa+dJ4OHbZshSM479f3oy6Gw\n36CHvvAUHpTmQiWWOqNmmUHHHnMRxvyySNkV7J8hlPk547mUpXPDCAheNrbQCq7Zg9QcaiQWd9qJ\ngnrFkLP+BjGxkvJwrV+1jUS4ymZ8io4U0EOc64Tuk3B2OXy4e8bHbNs90VoNbogNJ2JBBrluJx1L\nQ4+/oI2p1bd9BrWyi9lb2v+KL4o85RzAFnSU5vGSjrIx3lm/ZH/QN8/90o4qJsXwnwzwywuIEieB\nDYWlvqUtcnk46xKGSj9rr/PSTZBd7gFkW0W3nLbd5MKKjVDxtdiKjSV30e6iwgDQZ5rKvLaEPVul\npiJd8wgHGnnZRT6oMODzea5SMDG1Mx/Uu8SQZWcFTOb11D7MmcZD74Dh6kGsUS+qfY/P6LK5ZyoN\nHNMkZtEiQINbI3DG2LexnjcnXgKqZm2ZXGavRz/1f3A+4d4Rw6KoWfXIZOVUdNn/l4FxU3xw44SI\noKl1tT8NUagrB/gafvUWFBenLnxPxW0TaqMp+/lnAdDvwHLTwf2p56K21HxTlxXAb2QmgQlZB6bU\nDuYRjWtw96PcNIcEhaffTdNRFC37g/+Rw8qIWX4+euwL7s7q0kxKR4/TG/OfLrnBR/5+jgJGxj+u\ndtyDwjwrtChjTru6KPXODLvAm97PhZ8NRtb2Yzn5a9LjbWYSBpxjf4eyfAdYjEw9yPbjJpi9AJAW\nmwhWv/9b5rkxkeCEr4yQ7tXZTLx9l9hQktow08Zlh6pE4/8M86ah/0BFrTA8TwV1MQM9W2oncjGH\n+9q2b04TNO3wbncrECEi4DtBvtfYup7Ewyn3GlaO5eYLTg2/jiNmLP8fy893XZvRFmwsQRwnyXCo\n2nYZv3H6iAokmm54kiA8wDeKeZH5bMVRb8coUhzn+OdVrFqyf8myg0lyTJzy+bzzY4Pah1/xh3/L\nbI1bdfdg2OoVS3n1aXMOJQSoBQzk8F4lkSgV14x0kEgcg+6I2cD6IG6bQHCLflY17NMmKnX7MQeQ\n9ARoZL9Ftb6h6jt+Yj9TqigvDbbli6iYyt/3iLvMaE7nKbkI+BcyGR8FeD5rz5Sukk8W6WTDkgsD\nYzu0DTmAkRvyAwCKiwy6bzCh4dzKWJOK4GMV+psXZepr0io43Re5pRIkbdTsNzCzimW21WR9ePZ8\noWGZGUVoCCHkoM+VhFyZgrFBCuEGtlTrL1OhJnn8G/vmj6GzP7ppzjqtQOJdd1NT3mIJtM2MU2jK\nSJ1bL9b1YgSVmGnENvIHBs2oDoiFeYB/AdsDKbam8Ofe08wTbM09FVlDEjl4Kvym/+mlqBqdjB8W\nBTlVuLz1Npwe2Rqin9pAfmf2mro+7Q+P1t2MkMMBq7+mNXk6t7f1EZ9CP//mfVK5vfUlm1bJwc7h\n7zjymmmA2J7MYyTiTZCFm7zKpr2m0yARdirGbh5+XEerjM0JG1JFcunC/BfW4EJW+aPNSQhpCcmS\ntpvSqc1TiSkWDACL+Kld4mtOaUOVAjJ4IPoOKrJtnDz5EYLStpqmXsohKLCt+sy9YZ7t7NEdk0SI\n+i8nrAQsijEAoguMLC2r4fcfepagdfAzf18AS3Z8t8vItfUFlgvlByAWPD0pAxEeL6gRPo34mHvp\nqtb02SaAbEWUaCCZNhoIT+MAPCCwxxu6OEN9VW7YQw/hmrD4e4GyB19xhrNtuyh4zHoN+FX72opr\nxOkXzzghtXGGsQ2q3/6cNaNiE7P1xigeetIkjYaEOogeiEI0BuF1fbJDaLfReX9e6jXiLvhJ5AQe\ngiPAl3g0FjDUcmDqjRteAhE/PNHfoJUSgu55pPfO0NY2t2Z2Ye8DF9v/uGaVuFA1bhi9O6ZJfE0V\ndCrNoO9JVtPWadZbKqRoRYR64EhOYf8QMWXpQea8J6pNasP5XG62E3mNJmZhsEhO8da14ofQAFnr\nuw1npXWWvVGW2OGong7N2Kwh7SRpeKL+2tVeUM5oyRkkegprU8oY6yDTmkgW4gzR3iUD9r2yEQQR\nEUrnBqjowX6/a2UbkSvengDsfeYrIn57XZhpweU0dH5uBYP5FkquBKbngRzDWRIhRjpZOeNBuquj\nX6fJiQEmJedr3pyKIPHyXEepzbIAgL5Wuhzk/LNljrsUkTz1/vK9wk75QbxTXjCCi0MlhBUnf0Rn\nT9gWptFSKOOspcWHZzz1bR3qAF6yX2iGIpC7CBqaPPjOSnOIr1Qhts3FByUz2W7IrG7VFIApG2Qr\nZEpY3450S8oEjLqImCdG2XYabHF3KyViSlBMveVAn1qZGku+UFjoqKXKLREhng3hLqooi6ugvH3F\nhLD0lteBKSVsoGT5MDZ10f0FHDYuDu8pt7Yx+avdWuF0XQUqscn1y0GeYS5kr86t+F4ToSMW3ovR\nH9BqBMW/e94nritukUh+pUU2ENfgPglvuqcA55FabulEONPo2iV/4CdTcW3iZD/sNsGF1UHqf12a\nGB0N+vCYNuUpx9LspYpJWTeHOQslPRs7vWN8S54MBEJuS2EKLe8/vgESL+G2BnW7yrnXdPGpYRi7\nantqD/KGvHSTv4C2mNcnINFPsx4e4JPlmwJwsIHL8ez4LDfzGkbQo3znuwcl1FgqMpr/rZfAbjGd\nJnMlIYAo47jNmAfLXWB+SdpPEJgdYuuRi2GQKLWkI8JUR+/CMdKDssgcEyaJyvWOzURvv1hQUUs8\nPkMdKt81i7zFYQjiItlszd2C8zczwlH0eWE2I/wYLwBYMkRn868QftUBc7WCXFXvjBndT65IzaLk\ntS+XJHy1Fk4Cnnkwhr5UiOJVKXMm45H5EKxjwXZ8si08tIgWT/TPY7OcTvYc4EdO5sqbIrOIlxcJ\nA9IOjMcJqGbEoWMAtk2ASak4RNiXlg1zb+mt4fLZDqvemjQOEytIdpDjsKXex4b1kwug4wZmGlki\n8NSMfJNHvGf+G1NZ/qm5S3ZV2kDMvsq1CbBFSw/PxZ+mi7bChotalY0y4uMUAOBSP9kunqJAUrMn\nS2uohKVUiU917LWN5sndUR/DPUfV8pwKaCkdxF5wwUhxZriym4suG9nSYCjgTo7RtHPM8zJ6jadr\nTOy4MQeh/41kZsJ/XYpc5ElRTokVajxpABDhLz+d8fs3DQLWhTQ7dAQFzaxKEHPQYD5+qYLkSURA\n9WeBKvZqJTRRibHc4nbOfxRMxaQc+EAAjELMdOKS89L0XejFvCUujsz2fzQBJkpDyfKoXWLRko92\npzHpWTlhRDA9s5b8PX/AR77wA5ArUGNjqLmVzA1pp9zbxZdgpjqCLi9BNmyv/dg2HOuQs4tgw0Wa\nhIkwx7jfZ3N+FEnXqMihEhWujWBIpFVWJJg9UJ8Cj597k6j613fhjn+fQC3KCwnC2yGWi5ohm/8M\nSpdCBPF0n3F7iEKeRYOe9LRZGXKsa7cPF1dK3NOLqS9L8s/I5RGmzzYpuJX9J3AdnFkFX+eNJqg0\nKMrTPSxtaHUEe+by0YZm0zlcR9t+oiatQXde6yVVzmFWgcmsoz/fDx/AOOCTGxthX7cLvkDnRut2\nzdGY+x0SPOUVq9Up20+HVCHHJVdvlDHnRcwiopLP9EVVJJ3+8+zXcRwdR/W0qU3e3tjHMQeLcQKh\nJEXrK+Byiw8OmW0QMfzy1sWD0q0/sbMxlvt4eq0rHv2LvmpDayo5mQXKasNBMKdsSCFzmjkeVXkL\nx6lrIBNQrnRK3F9WHeo1St/Vlx7gKX61STdUZx3s6I2o9Fu5kQ/n87oY5kGnfIYy/Sqe7poccG8s\nnwtvT0W1l8YAgjLp+y4ttwVZN1u2Tib7vNpCGWTeUR4N4HZlfTWLkfxHA9E6qHgLyLhFdQxD5MjF\nzFCW5kFcsPysIWupF6wd+bHTvxMd9+e6km+LqJvwX9TJm0/Tuhv5smOEetrL85LZL4hoOD3gkOD9\nux8mkIV156Zn5qAXgRhGCBzTAoc3gdEEAZuM9CMnvGFt7nYQqUWozJbVNIu84YUuW9UaohW0MdBq\n9OmTNAp1jaYXjqH+ZcW4yCPJEkJKLw97SJqnlj0ts5ypvSx0AsRbwVqIUkBHIRTEuqdwXy7ffZPz\nSuwzY87QGmpoKvLB/NF/8a/XOC/8ekWrTlyNU7kOVZdUUan4xgg+rmtb5dxRQOg2+Cg5yB2KYpFZ\nGLIJEaN5ePx6OuNsKyGAnoL8VB4CVbYL2YhLksaWv9aVH0MSEQBH+d+Hhh/hyb08on14QDQ3IPn5\nPOfH37BX1Kt4ZT9FhH9AqYK9+IYyvlY1QZqMYqku6WF19aB5M1k1mnxoD9qP2OCDsvW0PulTcPwe\nbZWzXBB+yCTURvqwPmCCGg7Botgo7UemIA/YDo6uZQhRsrlLBqrNEpQRRJvwcCZadPmql+bxVLoB\nHRd0slNjme8ocHNUYblDKhFKIO4zGW4vkVS2xu86jFCJP+AUtWtEoBbRuFb6se1EPWSEZccg/tdG\n3S+yZwJXmSQIKiocBNNsoQl0ZuYObaHJFh/ghdUlIm9QpTkoUQwAdD6P2fVXHsUxXitYILj9Eao4\nnl7koAUxv+egJe38T+XzWu3qJvZlze2xvOmAAXEjVQQfE0DmYJfZVFKcDVdg5jYqF8G8FxSmQcxC\ntIn4gkrqg6EV87gisbn7qspi0sacZ6Q/1gQAURtDxooDDK5gsV0NEhI7EyoinLXjZJ9SY84+Bzcw\n+VD19FvREqBGtziYVyJ2+YAO9kUgWbuDuEy3aFnNOeTv9ze33bOAoAhBDtbJ4BJZt+eGcbWYWlP0\npMcWI4mKtcX18daNTCZR+LgCAw6J/bR3KiArm9ML52M7oEzMMSX7skvxyTaIj1zojGgXeZXvki/H\ntGHQauTSObrzhFf+YE5t50078XpPzdQQVhn63OgOKp+6Rie0Q2OZJJP1G9PXiAViKajwJ0U6IoUK\nVG0LJhSYwAOF+ditODWEnyYQJx6u4HFg1/OYPbRRf5SL0HEyB2SOhxzRc+QylENCwbGWxkJ/MjpF\nucxP9yehbXSUmmAXr6u8e0PlT+0MEcL5+hML6XanaR4sMnepTVUB5OQKCOhz5bVdYkfJf/AZhI5u\n1tj4AjxaqRwn5RhHqqcjspa9oAXyD6fTTd6VkJtf79obE2Vn0/CkZx5Gc/vEV6Y/UUsQa0+HNWxC\n0KxJ/LqbD+0Xo9hk30nIOWumBfNHVFNABhSH0FO6hXe1h7DRvhESnhSo7kGWpv0N7/A4SIRMybQt\nC3MeWIdBm09lya/sOlRRHwnjh6BgZeBEtPqYX++mSFDadrZ5912qAYsGsdIFlk7+p6xospuH+IyQ\n1PP4r9wg6I1iF+wSIukIJgfswFgAGBtqgDHhfMaea99tCTbBODCxTlvVOkbfZwEcdfqDQJioj+nY\nkY//DSMVhLeq/3yvLCdiembO06ynPh1byTgwmALsU/RT7uf5DrZBontbQhHqEaFGqtf8irH9r7Cg\nJC23F1/SWnAd16dLnUjiqbXwbIoLMHbD3pnqvbyyqy7FNroWPX4qTHJMm5LbSMWNMGR/l4ucWMxV\nky/QnNMEU4wvxoK1RI+mCtU7cdIjq7I9Jx8vXkCdnLnAXFb9QNHosk8LwZfmibS/xe8bBW7lTtzc\ndbpZwB90QL9ATHHTbwX997qQwU6f8Q6ZjTVx8VzS23VGBt3KmFvGycKB6dmPyzvkFWiQW+Cs8bpN\nvwr1sTQF8HierHVZSIDcGGnQ2RcE9sHY9ywA2gug29YJOrasaChUvfzGHMkvgAeWBLoNN45Ptoq1\nHNYIOiNBDDt8b2NxtHOlftvoV+KQTNTItY8HuSuvucGLRFZ/ijxZMp7Gka8hw0omBjJ3K/Canqk0\np/nI+kfZ/ww8PnWSkJCV3iTei8yb9akSyGPtimN3DRXg+nm9F1vhe6ZjwvfxYdXsR9RM2YFddDJj\nPJ/7sbG2ySqr5AI3utiP/mJsP9zsIUtciEXpzIiY17AGEzEf9WZc01mBXJheccBxjLpk2hOmp7DW\n/bolFGQo1u0HwOCjvUQEN/VnOXBf9dUC8dHNpljvbvcpY97VkVLl1hhLXJ1B6CZ5pcmV49ukA2yP\nHUvkv0kKuJDG2kjj4LUJ5YXaAGBdch2MCw/ET+X9R1Lbz7Tm0oYfP/vj2oQjxfHEux6lD/Urc2oI\n1tAqwKd6r/F2M/RmthYfXTEpVDUbiw91v8Sh4I0wwtXOQr1qrn4qwtP90lOT+tlF2M8TKR+rerOz\n/5Xgv0CCYjY7xCg4tuF//w6fpvgs0Xp8n+/+RRHW9SZuYLcjNkECku4X/bNTWgMoAfJIJLIPFZEg\nKFFHSa7PwlQqsQtO7f3M30QtV+S6oPKAnAqXuAd8gNhhlzMJ4O71NOrGSrsYdqyKFMu1pulAegSk\nQZ+uiKAj5kh/P0Ce6xKJQVPByIdBLuUdKWrNSvLdkjayB5YrzBXr2uR8Z3qtXmVTRrfhblbKcmVx\nbSlQCkpVPIWCxkOIc1vH7QfvkHgkz0Vh1O4Br6JIiEDbSD3WhYk8pT3YrbNfBhL9XWekVTilmC+E\ncoRGgWwOOnLGcaI7bxVfNZzqrCajMQSnYQUipkO9bAkBHiMkdegZfmnOCpQgUhIRZAmdKCA5IYZs\nhcQolXWCTRNRgfH7AkKeeObiP8KDY1vJ1LZx2YPiRrfGHoQeAVKnpo5Q+XF4nsb5FDWlbSF9WK4x\n3r2tGTKoamdzjbn2uks7TO7uFcTC1hsh2iFiECPnECYbt25QcuA6GhkCaQDMVCRlC72dzdy8cM0X\nNLgdEMCfAuh/pfO5Soab4eZFkdYi0lUKw2JYfFUm0MsvAYUhYEY0Hv6jh5aRNCEz+5cuDw7ufd7P\nmvD82HTyuLstpgQVz9MqL2IrFX7zOwsr4Iki/sE9jhAIqK6UNb2lrwHuhRS6OETJDguQycwqveDU\ni5P15/S9l0xzS0bAffASHIiHDS/nna1mXJMzNA92v5SHt6iND+4NgaspRFj5McYl13C+pzciz3D4\nX0zSkKlDQTpJZAjzqyduOgXcU5sROz6raPi+V12shPmKE5aTU+nt5baf0/qBBo47q2UjQMY75tMF\nRVal05IPRf/HOpHBowN7F02gfVE7H44F4ERDK/Hq1xEtrOFK7H2U3ec851+lya2zTCJR/Xcf3VBe\nlxb4RN1NWaePQkEcv/YWnNpQx+wtJntRzhd2+4ZsxawcWl10ffFyNr4ZHupqLvX7v4I/hqx48thY\niV2fchI4tKi54R4OpsCf7NZMQeEvUspEGjrcQxpHVgtMx1vXC3/lApBlX1jOD1aTwr7ThB9FbEPp\nc37PFCi99PpLZuExy4twaIUSOK+4IOfnhrNzP4+bb4TObcMe1gbmAED5+fDlwoMUWWRMMzWsyN/A\n1xIrOrM7zcDWgLZLcIOfS0spfbW4l41PKSCbIcNrB3jFSBrcwm0pQbneAUYkURTiw0Js/NskmPQ1\nqg+UnXhDdicyH0Wfn4tVGjaPXG+qMWBP4Fx3Z4tA7m0jIrR68Ao8aX+cbhBeS0kMS/j246amm0/s\nCXDiO60Fcdr+vOQpO10O+LjBwZ5qsiJnpnjeaJqXT+Et9/jkV5Fjp1xJ3EnlachHDM//79eNvK8/\n/JKOSm4wMLqBigZLP0jzbtnwgaUT77pjjr7T1mI5GQzeY3nuBOxgyscRlg6qA+96hZ+yXXtVArTR\nnf8MO1ycpLPgEkAEsRETTvNnDrfQAd3EFl4I5oisHtpNwuZC9DBflnl5hDZaZW8INJHxcaYffeOA\nI4SZqRyHEDisnaRsUSDIwcwj+tUhOyJyOMFqPYPu3W8unFFJc5VDswkGf2v1azZ9sqH/+QC2r1+q\nvmU/p4fmXXsNumWv6mJCHSInANf3xj65XGYYVUADHApABy4FLykn1IX80gOG/DkB8tArpTRIvOnL\nymsyFKe7bYMu0tUnlo2TPt/h8MeCWZiDdodmrMWa35AxrWLyT0U3n0ZtHC6/Vdt/e3T6oziJ/eVg\nlSZVzkrl/F5IvDwa6bvb6U0s/exSaMcTOHYms2e8B986/g+KZ9CjNQx8CSaf/8NGvuVEXtnONlx3\nLAWQZyLkf9AlRhWJk8otSYNkhQ30sHgRnkTwxaL/hxEClk6MEI+Z5UJt9ycXKODHuULHepLOcPZ6\n14Qufb3ZpVjOTbYmikm1m0IX3bCoKrUhj9oXXboV9woaTYxH8fx08ABGoDz1wA4F8VMn3QUY+F4A\nsb8WtvEmh+XEuRlB1edUNrN8WEkKjj3TwLKejJhrheVTvDZR3LGzRN5p/Fiz3f35bZUALgirF+Xu\npJhpoFYB7CAMH8og/F+Jlma38Ms96J/JN2SLV6bxpjWe5s/aAFb/m5T2WMr6f/Fi+hR3bYw2ANUU\nuDrYb3BZizZl8oAm3Y8N/HtMXtiLLPo1FuXhV/I/dqimr5RkGNYv2vmFyIRzlTWvf1OoQdCpp/8e\njsVRC2nOL5aja1Gbrsb6xLI7v7zOy3OXXnL3A+5G/aRzJIi6OYRIU9iBmF4cPrBOeljwsiThjyIo\nKFFxbCwY3TLsY5DzxbRnwXg5/kBxZOaES7X3X+zHI5eyla9CnQbfH3EUEvY3EV/37+8QTasY1tOI\ny905e4+8SABe51gkubKLjrhy29UKH7O2fYpuytamltn64Cdq4NhqTcnJzHCqZsFlQR2d3NCt85uw\nAMhm34FtpsIt7/67XzcvPhzNtotKCiLKN/Cgm6WqDNXxXQdqWBpk2t0ruAhp3IlUhukD3Wg+LyXf\n/ZO143HqZM09ejrB30WW0BvJbccuf5qb0GgBxnj7M/eDXJJPxea5jNDgIz5AJ0m2xwLDSCHWb2Wv\n2gTrQlIYnhFqNF51eS9oTQcHL1NUd8J5WhoKC/tnFnYhqZPSXTiC1F8H3rMUITUwIwR4Eq5f/SMy\n9vvjUuHFbAre0sYO884yH76/735dC/HbyF81vbM7uEaXpOBXKXUyFJwP5E5GfEcWXmllf5c8aS/0\nX1aavdNjFTbB38PKSNPR7vE4GYr8QZDsjsYzycp5vB/F1X1R55r1oHlKyB4lyggTZMjolN7L0+/K\nh0SaDpL1hBSp0datucCgpkHAK1ECDvvnZz/EYs4aUJdU/3zroy9RYIfB24/4jNs5h5aCBTMkmeiR\nAMIDLVnyEReJ7oVzZ6u1b6EZKmUGyoE/NAWcRmSPjTUJgrzF4ERtajmDO5hzZdyTOkti/h4tFdJl\nsaYMNAKg0w+186Fz7c25LLBkit7BG/wjrAPz2cW6JI3S4ru5pGGi85VQsoeLOW80nnosEnFDip+V\nJ7aDxGq9BSwM50DlrWdIxbvLObiVnLR8Ar9HAyYTzspjd0FPpeLqQVnWy9kn6nIT5CqukkpCwcLo\nSlct2bLxTcQhrwQucx5/LHBYpKkrp7rrzkHZ6P+cTUcLHJNyJPZkZK3heV/f0OcEsM4EKLZpD0g1\nJv8wATCKBeecm7/VqyQllTUUWvP69Owt0G4XzttdIBz8DTPtaI6ts0hlmbOkcDTTvBf5mZ3rNmnw\nlg1mysjyO/US6Fuiq9t9+3Xofstc4bHEm4YBjGCH1IHTDzvQccKfnM/cqleRvo7H5eXiFsZtPp1G\n6GOcsXHa95RzZj79MoKZNjnpEY+t8YauJ+ETl9KG2HPb5yLpP6Q6cV2HTp5GNHhvtcCoWQBAiqHO\nbxr7/HrkWj51SqQJe0KV/R6u46GvpDHfkVkDlouZTZy9uiFGVIo58fKeM3Te6Crcktg/2o5vSjkO\na7Z8yu/uzD4/L9K5yC9W0SCtqS8uulGQZpEHMWNlzCWY+pOvRSTSp73IL0EUO6DI/7fF2UjEWTyP\nl7qk/O9HvnOrrWAV5MLHT2Axk1W7H5akhnhcPAA7Lx/Q/Q5iLoPNHVWxjlvlwLlwWq9OaQICR4jq\nGDNMi14HM8VyANmSUU50AAoSn5ABDzSXJ9eUaJT/oU+O6OyAckpg07u/yYW4BkTMw8xIioyNOSqn\nvyJ7cBAB7X6KOj/KjRLLt2J94Qj6UBECe8x1PJ+/oKc1U5SNGmaDsiJPYE42OuvkHxD9CXzez4zx\nMiigISEAWNHfQrcy73vctjtz9y0ieOjN163Or2pLp5RE+4EnBTO68tZ7DiFsYAvgyApEJfTwTzS/\nH+NfjaRftQPoB23DSbd4otwB9wqCTcgyKeHfwrA2tWNoBnRRDh43MiB/X3InWXASYwMqfd2bTAXB\nO2ZNmuvDjFCqHdc6XOPqtha0OlB3JmvtCjQqmRjfwBDEg9nRrUo5OrhjinJ1ZZwsA6X9Oc2M1jUP\nlgQgjlV0P/hsZqt/GDjLt30k3e6DvQg5Ye+Kvn8MkqXne8Omnj4K3lzvEKXPYgWrAr6+t3IuGKRO\nr/774W4XqSnQXDXYSsPlm5VAGXmAqncVo5ekdQw9di1hmya76/G8VcN4QK0J/Q5c7xhsRvZUhBbD\naoZnX74rF3GIzaxID8PujDrYDMP2QkRZijphPCywc/l0jsldhR2NB4RW/kYPN3uUqK75cVesEaL5\n5v/AR9/c4p8tdoJRCWfRRBN5m9RRDQl3XFMUCUPifDExugkQfos7EIKRGrXely/Hf1bqQd84KBHw\nQgmROHDt2QlItAPE/wtivVzftCklyirO4+OmfkftzxGbX1/QGxAlJyR0gmm6RvKa1YoKUrKgK5S7\nXscl6MYwHWn1FJriTwerIP4mWdDdbOdCyCWKVqrv72q1sgu9Oofps4WpH4Id8HnAUAeoyYdHVdyf\nJnSE8viWhzvF+yf1tjrLZZySiZWT+ad44uIZkAqC4GRPwpOiYMPcB2Wa+1jl9Sjtp6expmx+u/5h\nAqCBE5nVYwwbNJ5/97wkl/T0DZm9KVtrlWoLxqYBUhTAfQ/Vdd5kx3Es/xK0tvL1c62UXivN7/I9\nVqga2Z9NvKTT8owc+ZOI0CANprFE4IK8JbXKrTc2NMiULmEnCU8OGYBYIMnkxGLerH12+A3ChuLx\nHIhcg1avfqvOounj2H362C2fJYDtmMVv5i0y8x0+v2FBjrTzdrisolTypKmUZ2MHXga5ZGY7mXqn\ndgkFBZOS64qYD1nIn48V5Vlsi7LF5aLMCOZWlXOw8WmIF6glbehcEFsPSnmyeQWeFK9duIjIEiYC\n2S0COsdbabYyYPGGFpz+iI9h675DoLj4BC552U1qA3tp95Z5GrD+9NcJQeNA3QjGp8mHde/skpX4\nYkex6WxEDA5ppcdy4YJO/pIrDUz4Y+KJm2AHQ8G/1UYNLy3QQm2xvEdP165sZy/GgTk/MxGtmTrE\nUumAVGVSTzDM3pMWOXMbHsDiCoY+LxKBmOofdTajcbPQor9UnJOOh3bk79plZvZkj/kjgc1ipavu\njT6UFxbm9ghBi9L6eUME4BbN+EiorSLlyWruDKS6fq83mX+4iaCshfP6nQnuTU1728nJ1U7J8h9l\nq+nruftauizB/m2VnGlEUGvC5d/olcqk6pWiMeuemTJM5+/BeAZ82XblX62hnpwo2kJhh0byu56B\npAUGKnLdamBw437+UlRRmPWEp2UG5OrqjLR0JMf02lGeO+AXXllC0ji5T+qUuITeYpHEadr7rg4V\n4vCNuTSmTymv06ja7bmoQR69HQxh8GWBKzTOLLC0knyElBbtUMaLTK8ocsuJxklx/fiJ6dcTfyay\n17QKT9aSN/+h/kzJsmdd/rSI6eJuQzg5lq1pM9nNggWdnDkZteF0Zg9YFqHbGfJMRqZuHxiWWHYf\nhs6BYwa1Si9yITAbky6OYkMYRRXLKB11R+pmRoUoiwr0xLh07t5UF7xEWYTqv+9KueNxtSOeV/+f\nEdo7uzq0Dii7Z8WTX2z7Aga6oO50BUYS7Zu9EQqXr8lj66On35fDlpEVb6h0feMPSn8Z7CCYxZxv\nrrgpc+B2PXhRlSumar1I9au3GrGSzbXaP9tYa1pWTWneUxksfdk/VkDLBuWlUN3jc5hvC0URlDsn\nV9FN14sxPOVWYbJt04oVou/R5XA4BNMUei+KMqaZ9LsMWy3qKESHAs0vomXA0Q1xxXac/zDN7LsB\nRTS+2gszGrNQQd961iFcXZUTQQaittUszpL3Z1wklSTLGQ3Do9eYkpQ4MXTmKjEcUcTkDd/8NA7M\nahK/cQ2y1mYEyJRkYFICvafpDj2h3+Vrzbg9cJ/+E1y9pNY2lS19jiEtaCisx04TRLUodD8TP7UQ\n4/ijc61VHaWa3tTgXuk6D9hD0oCiJOSUItz8iavDq1u7eDRCMKfEuHf2v8Ddhmkd04t2N/NQRTRb\nIoNNHHHBrQ/dszA1gWrgEV1xZ0dKWps4R/gk47Ow72agtIRoPMhVUyWaBgxaaEF9NAB/0Knc79/h\npDrIRM3UDEfbvOJJfBhGpmEXa5waa5PjxFrms+lsyTs58QeBBGPyfXH1r00fkBCCrhrlsM1QQTrU\n048xf/oyN0tUcjE/B1ZIBe410V5kNJfAtxAh2VPfvVbgbecLqGm3bRUljE8ozf1n6ARxD6GASLmc\n3GOh/dMJqp5oJn2sOFwv+B+AYOeGsnY8Qc0sa1DnEwTVUhDCZ2M775dMR3zZGEM/kk1pALwGQ6Im\nCnigap8WJ3+AQ+x5TZJsjWnnsZFbKiAITDP4+5gG9BpBQwVL7bSQYfWAYV+HsZNkpN9DYVKoz2u/\nbNnXohT5+gKpBQYKTg+h6XWaT/lwjspKXQkftnXwIgZC2EoA3j1BVjXTu6ePnVHr0azUwa7rhzUe\nSNoCfmOWeqnZSvRbVB+fRNZRI4hAVPpgptKPpCgL7DekF+8a8+X+Rca6jH9KFM6Vat3qvo4j81hW\nxg4glHb86eHWcUlzAW4wQR/D6gOuwjzvEi1jMpNNzZda2vtnd6b2QWQHKGtf2V3gPQNE7qp0z6tn\n8zMGcmW/WdC4n3Sc9GSGmsVAzNkoJmkCpBSMUwSbM1Tu1dX8eqXtI53zosOPO/buxyAkhN9sXDC/\nt5lVZdFQB3QqqT4xDjY+CwXxguwKeogUHQlcmu2PyndG1/ZlougRvZrmb/Lkw6bwLFHnuYLBZbov\nvAFBpbSKNKvQkZfTSwYiDNvc8BMFjMmjcFamwmizpssKFLlKIIbAUGDo7/9giFPRr+jOsQsmEYM4\nvL/nKadZokw3N0FCPbZNG7oP3I1wFyii7Klje6QNyIu/MqYQmb/XY51Tt3uPm7Xfc3/tNrmlri9s\nqzbMC9eeiwC2HkXHim2p0c4EKVWinPJkmzzHhHD5XqOMojAJPhX+ZblrNiwdx7yZ9FDd+udt11t5\nKBAtGk+DkDqFAWmcK77O05i4wt2nbfCYpoKyN224bqN/dwJBUcvQDeGU7zCkK9cY/M1RyGyOrSBv\nuZdwpqjj52VMyhC4eSw0VKnH/dkjXE6ob2Bu4okt1VlwfosxgTLiKv30Nxqa6xsSgUBdLW76YgRM\nSSxCp+DlI4KsYaCpTLqAkTsNbWs/XXcz+KkpZwGT3Ak7gUk9gWYDThPEGhAMifMZoNiuB/frOteo\nErLJDy9+/CBi+mwbqwhlM1mSLtEL+QjKXQtFXnAoKwlV0A0S3Y1F3eZVIt6N7EGpp+GqKm6pbvJi\n19Uv96Xgojy6KuRIp/r7ylJhgsaZmktjQVHgyTwbhlwc443FUjShzjYUNu1v/lv/ma3v07n/Nu1v\n5Ygxneefjd/BazNEjUTdLMV+xI/8Z5v2ZgRVVM/EjyzoDUtDR+/Fc3MUuqiQt7vYIQ3vJshwAQ7H\nq6dkx314RtY4hRvZUCGU+rnX/qCmenpVXFV2xn6Cc/5OF4EXbr6RN/qhCuiD81yAQd/NbjNEOtMW\nVmqXqTPsOOPY+FHam5EW4IxjWPRsAIX3P6My6Rer1kJd1F5zhDJbArwUbEm54c9GQkVXxhTWYIqF\nvH+Qp0Yy9tyMUnRlASj5jMvgwe3cUuHPxlyPUuZK+rK5ayJVxweBf8s8NsE58TFti+6DGNH+GMoj\niJrcHMl7JIRez9U7WoBdNSTa6Wu4FsIQskSZAPRnqG1YIhSSsLnEaonRZ5jHn6PxFIsGHWLkRRTM\nPYYKNKVMipW3WnaHIgiN57KTb5pXBGnXQxTZWgNJ4Oc1Hb/CLPxx+jpJFEHcrEa1chVQZd0SORaJ\nC0zRLJ3K6naY4bpkuEtRGvqnEiC69i7rkR5IYJVZn4T0L/IaF+HxfL2jZBzUqPiEpBIkGRIoRoal\nnAnVsez+Tf1g3sKGGb8Jc7Bvv9mbKP5r+ciY4SkeEHFCjRtXAHTU2sIxj+cVDrOGcwgj04QZg1CG\nf9j+AucjM1EmfmYfM6GMwlJ+jju7bvRNsowv0BBNlF7J8l98+ikv4vmUYM4WSkRV/jc+XOLWD2y5\nyNpM1OjVk1/KAG/In+VQAh+vgz1+4/xoyotLH/qRGT+bFxn9tomW0+Yzn/gahFC7LGrb3bI0eQTp\nQSejapmUj3nSlxVQ7dpQNZ0NrLwA+G/GycUyauRzRBxKtZMNHDmjfuBZX7Tcy7YiatzCZ6M2eST9\n05E4HperTb/cfGMm16ME0VdyxSZXAmb+OckEFGyGvWLoIVi1AdQUkJAh5rbT1QIkSS95m6iNjS13\ntFc+QIFe0S9X0DKXeRy730ZfGzxDHl3mt004W60VSMKldSaBLcHxxkrXUno6fZskEcRQEFd8weJj\neZkjtL6rtwkKjYV6x+cAqIRIH2CIcwgvi1MM+SbuB7Ej2OHbWGsH+ae6kDWlG5RxNhyL9DD4xcf0\nDdxElbdQ8rphwwoJvoNEe02bsY8iwtjuSyD6Y6clNaL27fwyCzjLujIWDUy4CHvK7Vl7a2PLD+dw\ny3uIbO9kn1IMMIKHSlomNpPap52CEIksHGtfk+4XSYfSkQKKp/kNqVVR1RPQGFToDqSveiV0bWAu\nSEee8c2awA4VDSIte3mzaYqUYDEfpBfjlJ1kfUOttH4qAi0IgL4BL+9FkiKjuwGeHVs7r+v2X30a\ngWOPSwAX10NabuD1IZjK3kIAgJJXnmco2ziHkW63XC2rKj3imToI3yyPwL11wtrAgJETZGrJTxO+\nMfLO+/2U61Knhu2slj+hYdaJqoIn0DCviHnI7DIQ2fAgjjaBl5/Er7USC8yzu0STnipb7cjZiTZP\naakr4i4vGo4b9Bd1itUaJzJtsdWrkVcFA2gSmBCHTYdro1jelehFneB/aDR7mxtnjz4PoHdES47A\nOuvVgKpCzNoMR43wGwKzG0B32o2W4cyo5fewsH6eHMn+T4EedcuHmgurYiN62uO0nz+M7aIaaBjS\nbPAJW3sIHIEEdl1P1Qtj5bpN+FoHJO1S7NGnxpS9OU7QMPd0thdPovlaO1Whwj23a2G2ry9SoW1z\nY5olooVHpgXYzMH7/aKVZy7EIaC6Pq6ILrl+N6Ql3+UuOAhOVuIGmgA3U234T48fYm736NjR5Gul\nrSbC9/WbAzLVLiCWKyxHmQqbSEsaOrjhz+ddTL3rcvzVLwFzhjTqRWQsPbtItebs41tdPf8MvInt\nkHYDIMP1RHhTu/5dAS9h/X3tQYAQgRhCHOAE/4uMtfdvIjgAe8fs2gC8QK99+EappIfJfUkvZKML\nn7JtFbyd4wN7CU5dpNIk8/RsvM3z2u7jtDa1yIZZIHNQfTaJ8WmsrUrjGpbjbT5lPZoMiQt/jblL\nk5uJo5y4kpVNE9Mg+OlMSMqekZyUeFSHuGOBn2smMqko+UVNaCFxXInWjz4TYpqXp288S605F7cL\nLmqsI1yHvV6yXa/8DztLhmbusW0vtxUKU3I2h/KupFTrxLHKOWOrxyix7kJ4L/g8/PutXuU1kAoI\nAu9OkaBF9G4qAHp30Eb2fxolsyRqSg7tDREIfyA6rPwj7+gY9z+2g65bC2+O5XyzC979ETBl5EmI\nPjuXiDRlRRDNtKsOLoz98L/9GAnV0AudrPU+sgVjxwcNfKaRqib2icBzWMIIsL3QLhhQxLI6bZwp\neya26npYMw+VI6+huptBzOaBV//Yonn62HLD3MBmDEsZRbSRiedUiuv7FO2kTlQi66FK9h02Uf30\nzrbGSKr4sRI666hzuzBE11QBkJqOosb4dDlHX01MQSKIc2w5pKvfi1MECCATgZMZ7ilhizyPHPhM\nqYR6erClv/4mrKlfdy/eRyaWBenWkK0J9aQB62+fNvXWRJ3F5SQA4xtCLxOlSKoqQVV+311DUvax\nEm5l0r5y8XMpy8Ig9W/TOidKG2ruNkmtRHwn7fomGNnG+YRWvlHPYkKcrMXXVZYEHhVwrwv0FRdw\nqqilhFaMowQStCU6A/Mch+SK8shJHK11OJnt4E6n7GSS0VWWIoddIm5+RK6+DVbhGIGMWvq2c+/r\nUMAozYzqqMD/iC/ZUuMEFaGnsRaf7fDLta1A7VFGGX1JrfJ84/D89+TUzIoiJt2a+mlOv47F/nIt\nDAgtzOSYGKb1NhXlkc5js+oaoygWm3Nl2B3F52XQd7P+eJfDpWK2TjB4F1BX9GMnOlI5S3kWAp+y\n8m67tK5JQgHqpN0CZ6yLbololzSu4PX3gW8kafdkgnx/s11MMaGgmdlGj2EpOY3RmzfYb0zUcv6x\nrDj6PCQU7tjBx85GxXzUZpzyoW0vswvtkLufpFueFe13Lj/xkjdwrV9ztjg3RmEWpqEDhb/ewj9w\nMDgzH1m5Waee3zV6RsdM8OywzwGB7r3QEi4+TJUT7n93NRH2bl++VBegv12aakTzLHKbSb6HyWdE\nUctb0DJhxi6aBKuzwBDJ8IXilBnK5vb0oGMpyvR0+SIG/WehKC+lUhfpwyKzZ/x+BMz/AakXAFHB\ngprixyoHCJS+IyJRNTufZoRpXGD/NdpZEyuZEAOBoY4iuamF/oaWgXBZgaa0NGa7axmq8VyYXhhS\nXRaEXo0XFlyt34x/Hs3t5P2AwUqFOhBalvgxSFuIdt8s1SfXHA48jwEBSY2mRa/LrKm9DL7CVsfd\nW7AcoaS+xAkMd1ZA7zGD1+xV5kFBSJ+oUm+BHq35pBGjxdwPM4IYx5qL8t5y6LkBzYVXQeXrYz3n\nAPikEn834V2RN3BXwNBi++a9RQG/9kyZFKAgjy/EIEDqsZ2Fz1a5AD+kRnZMq4Gy8FqfvtzaDX51\n/24gW4s+KdESku5GMoJiIdxYoPSC5yYdU6maW2zfvhU7j/VxHIVkEAuL1jggslz7UvWmLvDQSvyg\nAOiGhRngYu4hcVry1NbfF4Y9YOxx5VSFvbZcdVav2L76PYXQvfZa6b5zAj8nMtYby/auDzpCGggX\nIFig1IHnalQgAmlg++abElpqAE9+F7wlpvxSuMr9qjsXMJFa1NLhTAuYn6KSATMLJtmc5ZgFjtV/\nqZI83QMNaqgB/sFXO/zdaW6lc3DKYv0khan0DLyxC9ZYoU56KxHnwcsy316h2kq+KlFI9JUD4R5K\nk+NKgW87SF7e2IsYnl9F4WoeUQ9uu1TrYwvbBQikWhMo5zGJ+jDNnZE0hXYvD7zLnrpjNxk8u1jB\nVI3+wFkgF3y9dft9r//mAputCiFpTIwLsQE06NCVgTlG73PCHAGOQBkEBW1i6c/u8at890aDr9FL\nJulPXrkRHnyQlGS6bml0RA8vNJpoVwFRl2QRt2qUo3qTbXDEV9aj3xXdfeEseUR6MQCshhixhNj0\nKU4YYyNjpsnXLYyHerXk3ioDeukDGLEyA51ZK07Szu2UDcIFqZ+ab2ZHiovr68NcLfw6YE1qkg9c\nYLT5Dk89XCyGIdn3pgnES+Sd0tcg+T5Pp7nx1EigHx3ZihMi8Oxe/D6guDWy5TSL1G0ZaC8BvFYa\nh1C5Pfr43DjEoojJFMUyz4w/w5lCEUBEh6E8gXjAMVjzFAsA7vDjdWz08GsKz+CFWPXVVrVAaIRy\n19k1gGQ1MRtI7CUf1wWh7f416K2hwjHgzz6cmETCt7TexIThgarGxn+VSXO5pr5O1/Fs179fijJE\nLmwfZInZ5GW/PJnyfU80Z3xD7Jf8tA9KEhVmkiNE+SX7QVCho8sBVQhT5B26NKZrKHXkuFWKcBsM\nBhB6mZkvndJIuBm6ALke5fJITcrvcci6rA987B6eGw2NVJK11fP8ugBJBkmiSCxH3U6uXThxgqMz\nPujL2p61OUB/0gPUXs/sr7qt6X9/kYDGwejPI9ievkME+XteHvCyDtPlq/mjoWYawo1wDIP2NnLV\n+0QatxMMZBMlG6naoEf4pifcaMe3CAyIAlbYCkFgKoMf0qVgdHd05KcNusDkLqz+bNqx0PyHucx6\ntQNR+G/WKS4eXcAdwTudTPLXuqY4T5dXr3EU/fhG2oKFgHJRrAIllJQn5it+B1ljBrm8BMXVZC50\nkm/y/Dv2k1RZg83xH6UoGk0OEw29nx+XrBNqjLBViBHSdzLAg7XUs4irDXyfhxGycqBdvG0a98Nk\nxNU46vJazVxZWSL6U6mAe6Sv3Sr9jGmNIgA/VdbNk/SIP/AhthEjNhk/19pheo85ryTp4KL24Vhw\nrSotkbHebmTArYBspDLozvV51DeBkxnLdq1AwEdI+kiwzBbiud1p9rJEfRCLlqRYOI2rNY48L9Lz\nVwjSLp1+SKY7ERb2h+5bygkAImLrivJNuv0yj8p03GAPfu6DwfwlYjr/ZSn5C713pe6Imf5odEyk\n2g27gNss5gKol+0fnIRlZrAdBphbK+HDGns5LVFnXt6nhEEzzrhmhY5q8YS8OBSR09NzveOjphSo\nMFsa7DV6Mx6FidSa3xeL8Kiq98kSg/JzKmT917YSdmFImgN839ZxMPonkiRYfizHC0bcdFfVJC9P\ney50x1ZvNhADKvxaQoVppfhgjgY4RAL3yo8CNeL+8diNOvxxv7VXL6VmkVHb0OPSK9T7jM0UNC7g\nx2kdywCP5JyEAE1ZYgyfhp0cZseW8D3oJ03+f6aWUefyoDW+U7lhbahfjP9EC67VrkOC0aA2r1qb\n0EGdy+Wgbo8LwZqlv+i0kT6JJVzJAs9m9mIkVRdSau7A6EtZ++Gui0K56HTnHxdBZpKPLfaMY/Vq\ncO5ShwiXPBEzE8G5dKmjHC+z12W1EDxgsCLar9+YOAjxKhgHkBGfg69+NmO0ydwiFZtkb9kQn2n2\ncakas/WtmPRcBrFKxTJv7hrqsa0tATeeQxEfLYe4qtlUzpbtLY2FdoNRQlSxUGJ4pGgiCSx+x5ri\n5dbUwJzYin9/1AkNrajyQ1igqFH63Oe5iA05U0OBHL1TZbqVJu91v+1hHGccThB7kV/xn+sWCL0Q\nmMULWQqEWLR9aFsTO9vP+2fvOf6Zwuefn0MzofCFTwq/kYuMgyppHBeqD0San0S3+DlRWFbvQxtd\n/2tSB+nGWbiKevmP/K3gE8oRdXigzg7xbPH+gh2lCC0wJmKwTgQwHIC31x50ZJkg8cci6fVAAw/C\nVHXrDrjZSiroK8utPInMK9UgiLiJZaxnv6VMTQfV26pYRuUPBEPpZ4PLypuOIcDs1tS4X6nUNDU2\nfNyzzsyS7Fs6nTKsfTb13JGw+dOOt4lMUIBEU84U5RQKL+jrymEyKK/sSA4kuQYjQXLCHUIIG8G5\nHUgZ9GKsNo3ugw6mpQdnfJ5cW5I10H8JLWrMiCExw/s1EXPyeM59eTd7T9tDoN1rAZKPHG/JN8dV\nh0oYFXVBv9sIAGpOy1+yMXyrapdwkmnq9M75xOw+4tdRAWNlhGUgeer4qaGwM1AiZOh9ICdC5zLx\nBQ6+b4pwzgxHxvbCVYSY3J/6A1H2OWZ/DJsHbkCJzKyyIJI6c9Sj+iL7IWOEz3kPoTdwojbxnFjE\nFHyzNYqDISswQg6KXYsPWTEGpB/obQREvd+ABflTfjzhr3Tjftzcg8LURNmOgUQANWT1DWQSbC19\nmfeCmEA3Y+mKQXkzlCARoH1uXMPPUpVC1ipWTPqeH7TcwHjaNCNhXgDS/uk2Z5GBD8YiHzSvAuVf\nKZvULyg1j21LI/bSkfQ7+lk8ROtqWPv7/JtmfKo4EJbyI7aQPWjlTqdH9mV0ELtfD7EbTPEhwZZQ\nHGWfHrL778ObaVgVlJ+4cur5V5ysxaYVfZvWa3RzOCv0QqOo2lYVW6b1BV6cZPLYruo7o4VgOq4K\nzMz6Tv5RTu1X/Q0sXm1kmGF9b7w0Pc5x3QBxIGCO+NzcC9HZekrjxRIqqqG9SREDtovJy40tvW9B\nVLyL0e4LS6wq+BG21T5Tm3wStOhCHnyJAneG91iZNFnrTY57YkATwIja/JJiSnDtzisBcdOXsnE+\njF+WIPe/OXaP7EXFwWnvQcMy3CEeH0v9WQ8R0k7m5/5LJUSKZegVF2vImSnXZte3+N1jLmIspK2X\nLSW00mKB9e7X0tmoffFcNa5K91v5qCKZP+jH9FlXfo6FyNfnHZeBtYWE1rFrWkkNoyffdTydMxU3\nHsE7+QvtoAiGifQOxWPvyL6jtcKpDsPkZKwWMaDS6t6CrUW2+7FIzIySi4GPD+UtldMfOgfX/xY4\nRwOLpHM0qz77Vk7F8r5igDm3YdRUclJRj/9p3PhuaGURCCOfvYY/1YtGyn4pRScUV0eI5mWn2HkY\nPB1KwhTPUTGwVWu7Y3fD26njzSehEGb15soneI8/j2u57nBdio7e76zBGd1Ae28DCxlw6eheUL+t\nVfbb+l1BrerQeAHVxnm+duuLE+rNrPfp+17NGTOlB2Qf1rcFqQWYCmgEI+VzyOhWARntifEQ91cL\neG3JS8IW02lPLDfwgGnw1jdsBDrP490+YoZQxAo1kmK8lSjgUXuTchXZtHz6I8/mHaTDsZ3ZJQA3\nNXIjfP4KlMMnUOG5LiaeDZ03uItPx33c7XIlhC8wCHIeOQHEnRoS7Ah4f7M3FP3oommN4YQxreJR\n/uAHpkr0sCdoRVU3J+7N2vwSP685CNjrqyl78reB2aX7Ty3g0hVKTHlyPzRgA62N3Gfb9vMrk+W0\nY78yHpQHiYOQTwAsjZvyYBwT9f/ldXZVwC1YIvI20GQ7kL8uvhV/+zbXVzv6kyjHg6HZIY+D/+rY\n9JnqgDOXkANYZNab/6uv2j1ojjDqBOeZShxkJkbTwoWc1yT8OmnQVIXLmeGTpGuabFKI9Zi6Q/06\n+HPwkG5LawIar0MHYUs4lb8X9uKIVauJZHO3fCfDJpfE7p0weI+DMayYvriGCPSu2+0cO66waMD8\nkoQKpOmFxHOrio+PflCURVPrWAdtiOVWfTKpPdCUgyjcX/0SNGNc+GsKLpPgnseR5baF4rxbWWCj\nkZQJhVLuPemR09jsCHluA70+mz9AXQAg/pa7bfPbMldU69lewVO7xbwqdUDy4hdTZYJCwX9TNp1P\nNpCzdGsgoswj/88Cy3icvq+rPBdxfqogbUZXI0ZcBQuBSscM9RPagLxJRYfOWbvPYakgaarvMURQ\nUKkmvS7oHX3jyOH166f1V6kX7iU1FtSODnMP0RTIiVB1jMY8PPv20LD5653dtu8nhpW/yxdeaulB\n6HrUOModOutJHPogWpEpYquKf+DCjyztBIiWtsXp0rIdpdackzsWc3l3gZdiLtsV1BhLCsj0FJw2\nU26qRLCKKxk0axjYCW1xbCcNn2Ui03uJuYtzjrQJU/ng+M40qPAoIOoonXkN2va+Z/XjAlJvXRLl\npvwhi82zybVUV7GX+GBE0mShC/h7yvkzFiRrRDA/RwRQur+2okCdE6dK8hr1zzFE10JBP0d9TUS0\npK2XqZN2VJ/BQSHEd38SApjeg4BZNbFB4+Qm5v2hy9XGHVWFBr86STemwiPK/HTKyvHbsTG8gt94\n4Y361rCNBFPqISw38qIcz8ooUjFi622Y/CWCjDz21lLX3iFDIFf/ZxxqVSlJM1NoqsTHOTYaVwF7\nhlfj1vG0b3l+cGCZNArEGD9fxGx3Z8OwL7Bzs63ULFNDz9lM2zFr4UU6eL3vuRH3yJfuI3H4I77P\nffLuBWlPBg9kdeOw+bZrrzSRIRmKmYS6kOz3Uyn/i0ejd+TPM5dR+qHmiFt7OZjjSaf6pYIDxuFA\nDZ6PvZDVBcTDMavNkIcSkwsm+B0NwELE2BV7pbI7jpTpkuTQpZAIcuURtrHRXOohYiktQX0f2DId\nGDX2juPGYqAkqHn2O6TuzV+PKfUMTryW3TwkT2rIqBqzrGBtN1hU0JVrCaZAM1J928FQGECowe4C\nYw3phOU/wxWfcpsDd+JjsNmQP1GrNaLeCvX9iiM91ya+u8I0UPBSSpBhbDExnHRQ8x8L+Nxrv2P0\njVZpcPraT1DfqxmICYoVm6AY7rdTgJrjclMbYmafOsUk5wRRTQVAYPBpGcA93u8qLRqEvvDHhnS2\n9RKzGmNUV0hKqNIF4f426z0tJi0IkRW0znccZmt2d8TXKzYkCOfKAliSBqpZS7bodKplqMqc4voE\njaPXEf1vKkbUQOV5HqmvUiJPI5Y7jQrosCCg5VL2/oqN5DodmIqCCTd3vdAm/tt/b0IuI5mRfpP6\nV2Y/cRCrmE+MumRavYpcem+l50tCbeSbglB4grrAtBooNSiWou5vd+6WISoDxewgOeJQGew6HhaX\nO3eGe6KfJ6TaL3fiJuZF3hZ9XXqyDuGrb8nQoAt6dqqzzDpGo1JaPScwI3EIpud4EhFE1Qti5v5a\nV3Vl1+6/UJSBa8V/BrByhZyt7xmrFz+1Bgy6E+Z8DAH3rQXV6mKOieQAoUPkW2mh9tx9xnFpbSsZ\nTPYhbec2cj4bGLI5crXAxEScCC7qH6wD4Zgnd+qNl2NdDJqKJO+4hUlTbuc5wXXvarGBBhgjMHLs\nXGdXVwHOm+Cc8rKXJvr7+5PUUtnwD8gWKxJXPimyS72D9CW6d7dkhkbP7lFlaWAatkkLR5ARwFbx\nMZAF9W53PRE329iWi8zBjf2WDZBSN2Q0TcA10dOE5nbnbfeT01IkqmqARAkQh+nTwL9T3bR2A8Pf\ngmwCqBj1+5rRlYslJ8CZOrLDQgDuLDJ0EbX+JSDcQd6jEyne6hgAaoZs41ByP/8g/PE2alqR1kRZ\nTYhiSUk5FbaPSLijYoL5o1w7Zy0qqdH/p9GBtm4JO9CVzc6hI09H8Uk2lQbJPzvt9YSlv3v92sQz\n2TKxXXtBQ+mUlziFQ/8BYitiRqoE2cdR+mE5f1X1YvM49qIirMbEuumBGiHJqvkqNUZBHU0ZgVKg\nvobG6mF+vwwH28e3no4tQ7zOa/fDVprzZjLGnvdPUjym+XCgbrKyypqUWKJ4/T/4PjaanyzPvvXt\nRlcGp/nhqI4n2u93okHPDK6jV/5phIyTYsLiXu3CKgu+8IRYdXYOiIo/e1Y5WDTKYgQhmBVshF3g\np1hGuj0SPHrrAaGaEG0egjAyMEWxwFicIsMjvHDzms9wj7SGPo6CFt4YMfar870S3Mr4rqPPTLEl\nKaX83QSEnw2lHk1wIWIFRH/7JbyQRSmJQSWe1dyCNY3CJc9ckpBwv+ZE3JjOz/eE9hu5cxojJXoW\nlr5td8y7IAWzChiI0YLBwLJRGcSEKYwgbLcICqV6JillP9J4X92YlMW6BHoBsMhB1DOl6TyZgMNQ\nVlZGWfNoYelupoRkIT8M7MzXISDSzqoDIKM5mr9eoSAo8ib6YK3ODFN1Ipi0Hm+qUVh97Qb3LCXy\nJ6TLZ7yBPe3PyN9tI0DKKMQaEf7MIeR/pJVXBGsWw1J8lMeUKMZGj/PNQ8jCoeKR8IQWRQA+u08l\nvi2HhJO/OOKzrT7wWfTqQ8JQJWoego0wyxREKsmJVph5puuURbW1rqMZ59X/1NWVNk/LbJ1gpEhD\nRDB7m4Z37EdY60O5sOgWAgfgocCGN+qw4b+xKacYxMN4HjXO+wJq18wCTE6+j/Riq53L1N8BhQ8Y\nGzmRansnzeytnsaTfsvP369sjt22XF5RMpCRvIpwnBzhVtSbsoEOecovV9J60ihS9Fe3klm6gBY7\nO27ky2+Nqy6V5sFI8PXp8SBwkwq5pNi/BqYrHGV+KbX8d32v1RUYbRrV4F6ptibJnNz0aU+HQQBw\ns4RzTcJUIJhlCEM+J8xX7HwyaUGYXM4Vblpw6Pdu9uJT0tjyon29wMG41c5BLhYFL9bVxSB0rylA\no9dhCoNanyu2VfmWH0K1eh+YJaNXtEb0ysEmWhCOAN/BB005lvi/w2S97ehdtGEWfujIFXRsvCgY\n+RCIDAxVVZqHL8q746Y3NWuLClwgx1vHx1NcQUcDBNsRytgo9Gb0DigkKNt+dAAIGmfD2l8RTA00\ni2rxwGF3erRv9z6mzledqzEO17RKC31VFamUnhcuZiDRaRRCBnE8GuE5BHaK8rw79pL1YSIawfMd\nLK7hHkbaDI3kT4s0uTl+t99PyWMS/B/0yfBkHsKDGfriLreKrAncpEeUpJVFKdFGrPl1HIHS5ZEX\ns1gVTXjNJJrMestKVYaEs4nViCstGD9zSan6JhEmfaifIkJ7GLKw+NimA9uOzyKvxUxfRCCFUSvF\nMprZGCfJ4ltS0NYsdjAs1KQSH/5sn/PQ6OIeDHlZ/n3Of315bRk57pzLC1/aVqAi8XLsSRefF/uG\ng/x4R0AMUW0mo2mdnHH/TY/0iT8LYCmwQO5G/dkxHjhJRFJDZ3qUZid99q56MwmCVIj6WDNBu+KO\nQN6QM5N82dHzc1QI4OMalKCyGwtF1fJoK6eNGi3dVQTES3YoHYpJwy9mkxPa0rvrWLS6/4KyUv+I\nEDZZY6lbAg/ozYCu+01v8P5fYavZmOXKq7EICFKOmUroiCAKQb7RAGvnYqGcYPcJRAsDYdAoIFDU\nroKp2Ovcei4dqjC/IMmPpx2utomxn1moEPZkeviZ/h4Jw8M+YkT9VrkRWpAoADxDnDqVJm9CyRZ3\nZYi06cQ7Xi+nISoqnuU0wG4niseJcLPhRyK/eN25gKr33zC0KA1F90dGy8K2XjjGkAy166Fm+3nU\nL2M0OoqaJrHkmiE5GOorVEOvOcgQPi5mcLYVduX9edasttXX1GWuqS6e+TdcltrvITA2mCaGW9W3\nuLXjKkSpq982wMXZ6Lezt5GVq0xxPV/hocBpYZGNk1GnQrKh6TZ2oDCwL3BfXTqGPrO2BfEl6Gt4\n/y3kZDSf1MYEfz0iQOKOy+lWAlsnuPolMTRzT1cOGY/Xo5ZfvbKryDcTb6bhVTvO6/ytROqjAUmQ\nTHPlyl8CeG7hdq6DGm/TlWk+DtDGTXDeiF5IwFeBRsJPlaQ//IAkaAdtGnFztK5xLzNvyFs87v/9\njkbEu4pvPLRGn8alKJB8ZZ/E12VD5owB7dVz3WdKnfFS+ewUVFFKFM/LqRQIoLDfau36JyDEBIoK\nCc9QhI4knWpjgd3rc0Ror6hYufUfdIhZvbYz3935zgckWWECuvAIgdz5z2ckO8J2UHAmrLdWFxtz\n7NFYheF0uQVqIWu7hRMmfPVEgJNVslEfrtSENg19NvNy3vkke892kD/uoMfkVuyjAkS8PzGBrXJ7\nSQqI6VjMifzTsYMS/WQ+kXXwPhjx09QEncMmZSp0thPdg5CZk8eEvrZGprWuaWpDs9S3lN+NV/qh\nEaMcIGIuEMxbxMgD5WtZb20rxjLc674wYAzoVZKd1k0L9/5C0iSgJUwYBe49dyDOKYUMctmkESxi\nVd7eT/IqusXB5Q/PLFKKSpIjnafKrHv8yGyfnTaBC+kzTlVpb2G++mJNfwSbkDuqAvAoKjPAVHv+\nqzQVAKQ0+UOmw3T+29c4atCHzi2+uB2N0pr3kiOHQ8yooLRMdkn24q9cxynSkIZo1/dARHNNdxa3\nCJv1zraDIX2a9McxBdYXYYPeFRe//3X0Icj+fafoR1L6ZnzJ8pkqjZSGr7s9acLQGxabvRMGFAlH\nVSEB3Y7eWvxapneBKniIGGujM8MXaz15lv9RmTiEqxfRsxRhgthrhqNWOlGWfz21p8uZT/iV0h9Y\nfzfelebsnPN2uqnYGEKFTYTm43VLTKdViucgm0FyCsC5i7j0MIw20+J+3xPhA7x4++Bg0WIc2oa6\nyZWBWrw09oorWa4VXS9O4jd/qCs1lXQO9qyI4RaWmg1w/2nMaDgx3InEckVMCboMIeiaxntF0Oan\nPBiBdb1PPzTtsMmzVNpv4Fjv/cOEPRIRFPibNg3qhLCCRI7H9mgzfUzv90GEsJjMVTCAhWsuuHo9\nwGzpvadtd3ZPmPsOFa01NwPTRw0Ka+zQf07NZ5o1vtUsD8QeGQdLQQ/Q5OKw2HbA/bmpERHgtPaO\nU2pjfnadcng5L589GtL1Yn1o8CLSPo3GBOJXJ+EEsGHxmSytk2TceD72Fzn1at8SRZcjtsb4Puy5\nD6IOS7UeaGPeKQA6l11RgJHgfZbUgaJmK6tPYXZqXja2NBHNAlJGUGSUdtTyFwrSw1v9Kvbta3nm\n9dSQggcFLN0jfOh4Wx4PkZqrNAn4aYXAl1hVDrYSJYeIi/g9UWvt4lKEKzII7sSP+/Smvc+DQI7c\nKrUPoBrCwwSIULOWIvTrmc/9H9lyRuvvalVYoO1UJ4h1QZ8l8Awyua3XBfn+LhsE5y8En3VMKVBK\nHDDhGXOo1ly3kQ8NfiYxpwcHcNdNtrv6maO8YQ5GRGqef7AdwOaB88p4d8Lo4SDu62Dzf2fkdySN\nvx+zps0lGn2ew4IFCknQaUtUaHVrSDUG/NZZQabVDl4WAdblcpbCOW8uTiNoFIKFX8dP4RYXgq+N\n0wODhInglAFqObFfIC84RBfDlEA6t/45rPMvS12+uDunWBSZHyVY1Uwvwu/pnI48lV9m61OsJCLO\nOIgrpGewilIwhStXkjxdI/PB+Vez075WfTee96epvw8Gy7kPD7RFvqrDDIrSGm93FKnRHplTj8O5\n5uu+yfmzGBWYcqCbo4mJK6V0M/SJnB1HCGbgLiRxGy/WnHWjaYx9bBqMbBHImuGlpEzPmfDKvgV7\nAlHvpdpzcBlf2iAEr4jhpXqh/KwnRQ4vJL1P84YbChWf4s+IKE0AZ6f0vl7phKgUVq+P+ULvZdoT\nqnWO0Ig8FCSr/a6sZumTd2V59t1HdZTvc9V7LHv7XW1ar8fwPredD5AYEDMepb6AgFxec1FiOc3D\nykbfBhIXJE6n+Yn+BkBfyPaHQtr6CygbQYqPxrWvwqNaGqiR4M1+SnXc1ZPUCuO3jpsqErNCpGur\n86gev9iN95nwRZl1czxWVa9z2Vups+DUDYNl6OGsA3VaU6eY+zfjdw22WdfBTQW1yLZbKdfPdglM\nk0W3fK6xVQmWd7Q0MFJx12rohylS2M3jRt6ymRYDuj9G2x7e5COQAH4HvGSj1xQao0Oqt1esrJ4a\nYIqOffOvsSJq932yvAK//wpl7jU/meranK6kL+SFodAzXhE5O9i3yUroUaSX5y59xIfZoFg4NHP0\nM7zEBF6QB2GW8onP2jBMjRx1c2YyjCZC9I2gxLVNFMuAynr8b5R66ZPqvrh/8y6Mqr83orbrcV1X\njrDazLR6yHEOtNQ4bi8mN7w1RxzLuL2h058RZGlSsTBsO8xP6HAr5Kp2wBfbvI57lK6CxqUspCj8\neO92O5CNgGOfYdotXRnXfVffA4XKFtgvw2Me/hq6OXRjQJn4ru2BJA8kDP43xdNfLhkeKIZM3AoG\nTcMCW6giOWLiADsnkr2ofGgeUFbW+ngIOyctXvMwRFMD+1K5RpwKmd9uVYsHK5u+PLBnvBGoyoS7\n8/m4+m5zQh1ucW8F1QfRwl/sKSrRq0ciF10lQ6zYZB4lLAem6FOmUFaoyuBVPiQdDA1ZsbW/Oy9h\nCVMHPZwPrJ3UnrPvs6YOfXs2Jlfc4nyTMV9gez2SwA0MbPHMnpIcvsBYMqVf1NbZumEG5UI4mVji\nsP+Lo3Q+cV56vHImYilS916X7mZ0gHna6WTTGV9UyJ+Du3k0Tl5TlYLHL/ob4uKWbj822Gt7tv23\nAJnMLGCkgZQbYYRLwv5C7jFKxzPsaYrdBbnhN8Hzj8uWglOv5NmXOcg2pNyIv6Xp7o3P4/taZy/s\nbavizNn1qFu+wczAKyYeOCD1GOD150qXMwDfJGIaD722D5IfvLbBJkBz14/nzS42fO+i/NSflxqQ\nIh8W1dHgXZR1+1xGFhfpNgJ73eVqPltXA5/xNtE6EWKAK2h01+j9T0mPP+TCq80DejbANcjNu+ug\nQ7qp1/IN1oZBnRQf0DNejhOdZ3Ik88Xhwy2Bn0jLmvR81NTNbmVEoZf6/LBhkmC++d5tWUODaE3V\nMmjV73rV8eAB0kRkj3yGu5GLwWEtbau6TqRGb0BcVzUlzqvF5MPetFqKTBQY6sJENoTXq1XQjWm6\n9wH63KFczwcmFRWNgBpkvjQZUGWcCIlioS4fuoQg+RfiCszpQm6etlOglZq6tbo35s7iHLifH2fJ\nXgBvGhw1Mzh5WLkhF0SZtXs1flSvmLCyJM6MwWBe9Vg1rncHvsaqt33+9kknBEsl8yJuvLzpWHIq\nIOyjgBz9NEl5RNUhBXzOzvIRK9F3Z+fejM0uOy+z5JQfMyUHKAEhEtGivvnuKn5Iv1yGYQbKcWzf\nrLxAQP1WA+5zJeTLRbU+kco9GYRaVaIvruvNy1wYXHcRnwEui9exP//Ej02tNULykhUHv7P7iTnf\nYCwad9m+QexSnt0Sf+x7TTYZGucEUC7Y4EDC2m9MsTtXFuhHgin2e9eHMTm7cMiFUf3O8h8Qszop\nwzWvIQZOkkv91HzJT8h4L2b0+s0LMTK978OOGCGHEcqUPGyAWN7nOu16o2UjvQGFPn79rD1sub3W\nU+zCmNvAttFgu659SJhYDXnvhUoNWhfY6acclg3KD38v/SOAfl/eq+85NRYWvJtweiJRYYtk0vVs\nu6EitsHfSy055na+HIelCMTPbv3+3OwB8KNeJGveU0qxSv4okxF8YWWxztNlTRVWwx6fC7LrHTJS\nXhjvKRWBJrdBkAn903FdNO406+gwfbMP6VAaTCMo2gsunicIpS8xTA9jcMdcnCyP4GXLvQi4UckD\nQNgqbWYvw5fxTLOWyf1Qu4u6Ul1cRBRNRqZ3sZG1iD58EIMSS69VEvYM1w5CWdFFkYZesNsF2ZAC\n4RTSQLixyOWbPHcCckgl3/E4FZCkIi1A0xsbsyirad4r4OdBa4ELnPi0ASWPuCJZp8QxIx9ohBTU\ncXKA+rgTrCgCLzavqrmNtp3Gr4WW1sfls95t68GeO6SScz+13sR+D3gkP998Q+3+9ENk5i7fJ9/i\nQcLd8GqnDZaJ/h36F7+cUQZg67jcA5APE29UEhwTU72sbZWGcGykxoFo6Wu8gG9xLNC2pPVSdS6a\nF55fpU0b9k7eoRIM9wJyDoF5jVRrL+wNULRlvZpfiLOpSwjUKnZ6ljjKtTt6qfsye31ZSpQbTEDi\nei67gpANY9oE+l8zI+oIf8eBQod4TXK0aotrRsx0T048+WvCuIiR+iczHejTE8Pdi8+enWorNp6u\nCcR1yfG23NU1xEPqbMjQdnMIw2T7xx8WBpnaS+nBJ1gNENmT+JS56BNxD6xy5OvTLAQXjtm+KiG5\ncnsBBCY/Am/rByb+pNGepykPoma6lXmXc5FMpKsySFKxXx7y5zorfRE9gSbCmTG5Ltvw4142R91i\n812qH7JQQPaumVCKm33BGCVGuitsJfOfv/98p8oQPsV6SftmQusOjQSyn5Qm+dlpy2+VymZDEnTc\neJlGz99qQGTvq8/CnYHNoTodEyCv3uGGGoA0TqUo53dr7ssSRbAFgdsyRHMDxepGAcjkw7T6laTd\nqtTg6VF8hWTkI7MN6+pMfl4m1JUI3jCTvL3r/vgV6Kz3ppGiAoXiSzxy4keXJ6PAPwFmbGMVtZay\nWyEhiliGvUyzaYlZPptWWhQOtNFU7fxXPiYE32GVZIx+SiWJLnWydxbRC/WlhwgNYcGsyqSZMFit\nsNGCmXGtYx50tvzGxQwzehYg0nZ2T3/PJDCx29bJ47EO9lmaIUUPuHUmene0vI1Pu3WArggyDcZm\nv2T2/rnn/OkCTuK9/cnfLCkG9PZvw+b6Q8iqL81fUCaMHPspDM/w/iL0pGUM68CLdUwOhsuz9jrD\nADfcq+EHTkeSm1tRfg+5QtFa4PgsUd1tA9j3+oO8OS4wuERtXT8tItcS8PjZuyin4U0+G5ec8xRq\nNXig33Ho45rUFp/dzkeNN1A0r9jrBnzIxzHAQZgfdTuGWuttmgbHPe/8AhXQ1iFepoTAzqrCqBln\ndNdMPtSzeK2ZoMaHjCWqZs+s8/+1seQjregjKaPbNxtmkplWus0EExT+udkoO7IXvlQq7BgPYo4r\nRpjeAfQC8Li0QA1OIq++poHELmQg9Sv753ldrgUe7HlrntwA8pnVfa3P2xWCC5ti+tEdtMl2Z3R5\nahgZisYsB8c1LNpju99Cd5thHlHl4q8bD77qMmBldsN89OKNqPHdYrbQUxFuR0cSUly501EUip2r\nJwNftGERUEMKhO82u2cZQzDhz17Ttkor/7NeO+Z+DrmO2e4BlNdtNXxiWIprq5n7njgKw0+Y31Z9\no5bBl4zCMvNHlQ/IuBUEEIcDEP1SH8hlHzzCrOoA3/6P17v4Px9APMiiv33ExsXH8T1i0iteJS07\nzLASBPvauUC9xNjitpan8V2eHxBVPDkLlNHX8+hobBnp5vRMSQcBO0JFm33M2lSRBE9ZNcgYf+g3\nkB2CVDaFyDLLvhVdXW034NGCc2deKjNDfZrSkVEFJH0aDJoEYzxeEnMh9d5rIKx3VYmcYHgw6JGg\nJBhUkNHmCjfh0vCo+hjMCPwH95m3vUFe1wKhOoXsIWyk1QJ+QTR9t+hZTowkYlQprcv5t2gWHJYG\nys6npKLa+KanvsrGVrXB32uysIZliELY0rvCu1lnLfOVG5o6VxHS66qJPHimhiy6XX4IgXd6zZiW\nYO7BOZluVxA1fF+ajFTsjY32A70kD/tRSPQpYwH9EMaoF76kkDLhsIobb2kYNomgtk7M503onnCd\nu64Y7Grs+FvIkcG6rJ/SZUqfoPbCZmvMJtxhS3d9eDphfgzSyg0uEcbc30Scvx3MW/Ka45FcPqWU\nTTJuaFa5sYSLgrtp0/xa2z1ZrvplfUMOfs1Ir4WbJ9S9rWOTG+MOlyxRJVANozxhNnL+p0UxBvIK\nFUnFSYxOeTffvL/9AiuwYKEGlG8TP4W0kgfeL3hMAL5gpcXggAW/2zDLba/syJhMD6Tp62ZpzZTH\nz/IPQv4NIEnBLbQy6BH4d0wGaSLfPyXvaUjY7YQ+ntuC31nihw1bQwaZ+MUWyZRcmiX5r9u7+XdL\nI1L1yZBLfdvFM+nIfXra/bYYxC99jIKFf7pNPlxoLNMW5ArXRg/FY+4oEjkoCU5VQUgZUNAuJNxU\nkjCdWYT/MrC1tV8BTjT8vgZqsUVG+9Q9BiJFhhAhyxYKch4SAtURNyGrLtp0SSnIYJ3B/ZVjzn7I\nxuxZZ2v2AflGdJfcDL+Rr6aLQdbjGj/+0zoSVfLZv4JbXBQwhr85A0tkeg6cGcxR9Vza/zc7+M6g\nJ5ccWZqPWubJGmJvKwm8cnMa+pcVTxa27WsCDyvS0Y68jalHosyqevLvcB3xDPTsn2uHlV+VpQcj\nV0VFxSXFpQmg8i91a+zS4L7xHHbrjcRUly+muThjtgw6ig/wF5IxtSpj5x7igdPnhA36Go4s6ycI\nIiK57NlcBNfiebdpAbi/w5sM+taV1uXqviHauEuFjtQA33Ok8ch86BdmtrhnfMrEJ8rHapBXrVht\nIdcFv0tQUfg2nx+8xWmAW0dbKjOV9EeqQp0I4g9LeZD5GoAP9n3P9uxbxza4GAUXxvg8YQn638cD\npJ08vWFIXQz+R7QyyTo9sX+L/8OhlUe57VaGzoGGHeg2RfhPUXKQ5g4vkHkUQq05nbCCuLIsc/NF\nA9VSgYsetAZd8ab3oI/3nSeVQn9BqI6eeK76MN9q/uGinlJrJwDKg2lAwE4Sx1NtxZUDL5Qng1z2\n+lwVJzNItzXwfBtFu0TCpNDRouYbIY10OgzqrgN8p1Iw4yC4fdfmvvoeJBaWzueEUdTT0lR9CbXg\nnCIcYnStmgLfad7bKNKuZF0N2BdtTyt02DP4LzxwMUX9zaxXo2s/7FBfFcU3FJuvYBvJNxclo8rd\nK99uOpDhoAF68Cp8f3U1xGQs9hcQFsIiZxeJK3ILBP5gp+CyPPneqHwgN07Z3h+9wvOFgwV7PuNs\nihcq9INZE5hivSIUv1J4uqxZxw2YOvj+4XtgILMDsLBUh2/CeiJHDnRXHHXa8xyHN/VEZlvP995w\nphboRlruPD5mR/ocPYK7UdxRiSWJM3aJzUcLRi955umxUm0bw6N0pSJ7JahT+I2XC34PwpktoFJK\ncnszLXBWbxz29fPMUkVIgrJLImaca+mZQRabAzDdtkZVBJfpiL95/WLyAlyEFqHx6pOn9YdqK/x8\nls+aAzMGETkfnoOlM6je/dTzj3l6Qegyttg6hacm7+dwNcr5RLP10+lmLI47KpEZMRH0JtDps/ey\nRtCY/uN6O1UaJdOhdtyZCpou6ZZrao39nAAK3hsYPS++aZgjVAM+j0HZPfDxzqTE4Wp2AHE0vEVb\nsbWOC5JkhFUEsNgxf3CZZek4tylhZBFe2qAPmca7Nr8cX+/fGwJa4zsstW1RSHzzXp+ga7T04RRj\nqKwX8lhMp83DKrFARIncMkCPhC9OchoFv6Gq/qOjB5ENUspxDy4S/IOsNdRpKsjsoA/E6+aiSeQp\n3DWa071ADqC3V/jEDFQxKj++OP+/pINq6Y1craLIugETiEcpuMZtIfeNmTtUQ9bQlnnIHSMgiiLk\nEYO/fwfSTz7trn+YBvKL5vAPEgd8EXnJTQmYglGi3iPtfYZCecyOfq3JykNYoLGzlc8l+lgHht6D\njBryf+zujUdATobQ6vmyUQSCtmPgv044olqWdpLhzoc9ASuMzv1Tf60b+vX3nQLZbSJuYh7SHxUc\nGxaQJbaAUNbtxB873Z2xQaexfwD0XIgmIrV4nTsGA8CKeZGD44WmVGfF2zAEj0Suw90pvxZ6ak52\npnNXRoiYA1GbUbaAPifn9es5nNMox1WMhiiFqkfTt6QT/LPDaI6pctEEKbhZABvzuC+AFV6ApkFQ\n9sEbC67oJqc2L/F5+EIi5bC2E4TuVw5PGllkgLBAmBS9ZJXLt8W/7AZzh2zXOiztarPYrGxcQWQi\n1NqD9kbqMfjq4GgxdfOh6GXp+/8hzguNrB0XOLT57jqu3ukdyPI/38f/tdSR8rVLm9ctklpFxIp1\natcGe6ZzLhkmrAWaEgXu+rkvalDeJJzYMCdssUggP9sbyIBqNm+bu0hs27axwtzO0aLTdEmRy7BX\n02mW+0eM4axPDPBXp7Km1zDETT9OuwhMcrmk9IDiDrbaUj5u9Is6RN5ZNoT9chv4XZJKvLR2ut3e\nQGCvbdUAVHxPLCOslYfGfXiNFdwL9ygx5Xv94ULNBynBX65Yc0v5uokgRUlQFr4KxsdMcxhnJrjd\n5mKOOdcKDyXcYKKk1YrFmxp2Mqa1iRK0gm7BoGrH6dy8ZY4obArr8X7BYzzkf4oUx8I+5e2BLyig\nSCmP33zMkZFpk/Auh1rgfxz/PbMciaPSHZvrsiCsT3mIopE+JgltnrrCcjK7GAdB5hrTS3w3SR1y\nGBavVYxjiEqnr8WlVGP5HbH08fIsOBlMX7LO5sciII0cGlRpn364mCbdp91BslmVrQoxcPaj+TC9\nO0MZi9C8aOZsUVk7GGBEye2EQ6zuEpA0PE6X2sUd4HqfaTrtQg1EivraNouAMLztKnLgN7pU/ETf\nK4iMYGGJzip/SjpXL4XIr62c0IMMYJzIXHBaTyrZ4idSxkM6S6Q/VUPOjO00HKdaRqOIH4Fl7siD\nQGdPpuIRj0b31W/7wIswcFZmCuzoZQGgj7b7P4nLZ1ugw4MHnHQ0p0zWM+A+R01iDJDTBdfEPSsz\ntVdGAoTuJ+O5nYpHMc+IAOA29tvUF0hLHKvwz719ElO2436olcY+xVc88CWad1ptcp6aodqcFyUM\nOlHeSnAgLnQRB4lEfJKprHEnN1TrjL67oHO/cABupwcFGBhTJebJn1u/nizRAVf+CKSUryUX1plf\nq1Wg9A52pO4nv4UPs5j2/i4PgDiSZY8dZu2YgE043PYJ5dEjNrmyvjaWkjFwtziqqKJ/zAwzxSfY\nFx5VOVen0XsXcoLpFHKH06Nbml4lnpDAxCdCAQlBhJagIUqVZUEIMzzBgaOUj7Y0E/Sx/MU06AAm\nb+hjKhJ4ht+9FDe3q31ngEpHms3C2CB73sGjLP85VrkgocaNNOGwWb85+dtp6SbR1oOXKGSgDIuW\nWa9nFDdb80zA/9MYuiTLZB0pGf2ysznBH4gVaJ86M27pJbE/oidnAlTQUPvFB38TOYQNTSnCNbmC\nBY/7Vz2hDC+A4DHGgWSJ/wWGblIidbsZpgHg1Xo8ekbgWacICP4eJRnFY0h99QUPrb9rr7nSKoVD\n4fgt/CUrqX9nvnFnEEI8eiWD+oHVrQKGRK6TnOP/839TpPTKpwfa5Qlp8j3ABCliKMAkPP6HOX+K\ndwjGgNzWtsIMFH+5fIx94smDLYyUxaUiQLsy44s+y54eVCf5XtKV7oMkEfvPoBAXlmhHKys2EraD\nKquLZQqsoRYc87pUW7KZ+/FGw76fQKeccRJfucdYfj2hHBcIaBuJUIPKrC592N7/WwEBhSd8nLa1\nLZKRMwzDGxXGYlmDMwf56Zf6OgqrCqSI/SnvV5mzligO5Au0AT5y8UGRR9x2hTLAohR3HhVudEXO\nowk0UJg8YDcoxxu0VpwoNbMLIcaEY1pemBsAdLqJhGMTRnneNxKrTtSgUwFN30HpP1fHg8FLhkHd\nFEhXXm6zT2mMHNhNgq8nbsHlIZj6lPdOCqJht4xkSQhmq+b4kwFjsVIOsR+y6Mo+C1vtZM89MyCi\n6SWt8fabXIQhJg+XGRqdh6vVWl5/YYso5T332zDvVQTlJAIu30bYPbZTre/xqhs/eG5/01Gy6nQd\nsONvdiK5TjgFj1gAUliaaUHi3VsgkrNExifz+rXAoecbj8lpEh36t3rEyvXjjGsAl6nV1UgQiCOU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mjmT3stzC/Xv3U+2KUtVN3IyoZysXfApjzYPxRGoY14wxVxml3cjWkid8wTZt/\nqKiZ8+DNGhOWsKqtYFfzvK3ApRuFrMQI4nmfP0ioaEsTGAw0TGjMc/edUC/KrxwpP9WbWlpcR1Mn\nyRmHmO1G980fLf1P/q5GKog5mVjHFI3YGEOry1qcHAJR2dzO40KJ0/5N3/Pxa7i6wNIJh/mHzFZ+\n31kRMiX98q/i5AnwSm6CIHRH2WptfuJJu8bOdHyEc2X/ZykVW5x17fso5tTlUjx5p+HR96FFUaBH\nlCZQUHaHREVDgLoo37xNLUuVkMHZqp9r/Bd63iatA1vtI53HEnJpU6AsMLIsCdkY+Lf82Feavy1/\nXEAxqjo7H1QoA9YuFHqbS5WP7hI7NfNQMDjoqprgcz9/UB7xC5WYr8rq2d5mgeAbnstt5tE7sQm6\nQgLlHockY4CJK8Xvmv4d4SblYXDAds1reKTgyhuI4ZtI4IEsIdiA6/FCJ2Vtw+GFFB0zIWutZ9Qg\nvRS3DxbGOPG7mDhBr7DndSkrx0aocMGbybimWSBSg54OO8poGqinGYfYKzIcnpmV8De9rNUYTd70\nICpozYFwIfHD6uW/tcf8vX5K9TD61i5pXIBimaenR5BI2PMYIhZxYqmWN5m2C4lpq7eUVSFU6cJU\nDopA56H0YzS1Yghkaz6ccapw4+IWSfmbW+U+xxGGT3wNd/C0LkyFKJzdCEZLxeZWC2Om6YAKNHn+\niFQ0gxa5wWQPwuJ8ZhYyqSk/q1Ta/GqqRzNbWLlZC4xztgz3JY1yx0g4gGXDKlO705YMD2H1sVzh\ny8FE+koC6h6l4i41cL/DFsmJm5Jqj52bd3iigktOLK6QtleXtA6WLojTYOnJOguFYPtthxaSvmGm\nqQTuLmCdlOWgPxQizNJRMRBTiuN87BktKycizvXRwigxNRv5V2btiXkJPtyPyqkLA4WN6rCMZBko\niXN3m7e9ovTge7aNZ42IWrAY75oe3jrfzduFMjJB7BHwVaV1dNpZqNe+ZP4gzGhO6yKU6gUhhLjo\nhuML+408orbEV4f3IS8O1PfQ+c9afO72/Ivqt12Iq1YNG3EKdwt+NulV+j6oevJWc1U/vV8MrQa0\nbeVkn5LMWMAilgmbX61R6wISQo0NfBGdFL7yL76BwJ5wauMZ3beZYu5smvlVxpEwVhQ8fFxH5Xpo\noihRZCSnp0L/BG8e+f6/sZJ3g939OWCjOd7v+b1g7lOXhRH12gLTb/5yvbYNu6R73tarKDzA+EDC\nV6Cjc0uuB1aWJB/N+OrNOcVXKhZcotiTMF4vDqfRNuqt4Lr8gjOQdRbrQEveoS5Z3dGPAUi07lqg\nqVZaKQNTSVTGNdFooKDV6jxrbpDI7VfHYQeRlcfaGQ1FG1NFjzlHBtwZAFGM65hXUyuLRvTsfmyJ\nKoaS6UFC1MuuQS/l45/VFm1tfQmlNWunhV0kpPrB8jg4HzKBk9f2BfqoHchtOGcUKTenprkzbPfn\nw4lemz9G4I8Lj5ly28uFVHheaCmKS4+8HGNam+xtZvyfd5dpBY8AcoNMtHr6i4UmfWaURIdijXdH\n4Bmll6uW4Pbk+DGTBh4mPSh2on/JXHVKOI+tXmcYauiEje985N91S+0Na3tbw+coqe0WLnAcRjrm\nq0HRhBFaPvHkoNwuQKN20uBjwavtz72na95RG+VD89klPSBmoG9U09U91P6sJ18GtlDxXCP0UAvS\nYwS5AWhwvu1ZBenlPuvRWL5SCxKd60mnVbKgePL10ztCgNJWKHL/tYG5erl6R7VpWRMeuAsivG4L\nvlZh1VMUk7WcEFtlQ8ewoghZgp/iUiIGdB8UYFsMC2n0jF2KlbD0qxkuacheyV42MhjTNrWOGJpP\nb8cLqovTnWaUaEQR4ox7qhg+i7lW7pFMSIP9k6dZSVrywanuiKxyZEM8txnRmifM5BWdVlFe7o4Q\n6LDdZw4TPzfPC/79pncGr4kcfXBeItIkCz2Kb37YPXMbPvCbBJ3buirX4xlN4U9Fzi5U0OI8rI/m\nxEaubhXYIo1C1wVEbMmhjjAYqm9mdtqwtK34nKt6UA8yzfBAKUcRS9C7ComgLKAnsqqYmQ6+d9du\nQEqBOA+dGyP5ei6S8XQuTmoeHBEzJtkaDcSReujBlwUYKT5jEDk0nET2T3W05RN8O+I1iuCL2zEk\nCBa9XojaCW7WnyD9fHIfIlVP3k5fyrMDshYPSJRoF+L3za8tcsFxoTB29Q6BjKAxZ/R2U7piuOIo\n3MRAXcIwBS55HqoJGM2SsAP+FtMEdbi9rvWNynjnYLT3VWrn9y4dpa1PzuBknAAIADZ1iJy8w45l\nKMoZndthreWqtx5WJ/NDeCbjKlRUXo+VcTOw5wfPGjtROIJrk+a0pBEvk9IgkLPXS67zcTg3SmX6\nqQGKLp8Q4wEM9wWWnL2h6O0wifvd8KNCNPziDdUS1b31LePR/mZo4s8QhVTskrjHFAb4QUbPl7a6\nHLudISZ7yV3Gmp6lxCIVCJYIiPkLiVfwQRSQViwIUWt6BCc960d/MqoOz0fwpsTkdjYr+EqA4FGJ\nwxJLPlTgl2lMVKdWumgkU6nREoX2fmCnx53Jl2LcDzdxTiKv4g72G/QzytkzP/3csANiNniXJKyb\nyPEYM+lewTjlwyBrvA1Hseq0rwEyuZIohPauQrtMD/CqgPghUCPc1zEUWqtbD7Cs6Wa9Q6i9cZe6\noygam6u4DqOHve4zENyA4vn6BeFcxUULrbhaf00LyIK8JhVfO3PgfxROzcPGkUTDn9lNMcgSYFw1\nF5h0O+k4KTZAuh5WmzhA07pUadrHIEWS84zpb597LkMmlP/Ir2b5DSd3a9WrRzXtffoW6wj+dqC7\npakKeVaDaFLsKew4NQn/5Gv2SSsl4XFUnLgN38g3e2L47gMZVmWlB+Y2pxNwsAyXV5zrfZ66+6NO\n/atnQFy39BdJa/QlM1kXvILZzqUOXKGZVYZLaTWJEug9PUV3sxznlaY+cyInU/Zyp4GnlbQ0XVJM\njjTgTXNLU2xwchHYZ2fBegrJgvIFGdryBZ0iiPdHvP0oKTrobiiLLzbV6OGhFV17NAM1UtiiGvmX\nCecPeJZhMWSNd1sR0zXBMsmK0TzQz9wCoe+6xVsyVVjA7V2FOPwHS/UUbVQY48xEuz3BqvoRTDza\n/Upe/JHbXSk9IhwLJhuQT51Ra6cPMWmXfgxXBAUVwMzzMx5nf38uLxEbI8HuxHJNoAr5GGRdDbDM\nvIaZdGD58IBnjKY6oHp0HRYu4WKaLDRblLUdGdvRRYTa8gDWhSNjXPohCsckVTdJP+6e2e4QOj4j\nERJFaK63X5h0QsmZOgpBr0rJwPTHnVY6GB3YKBw354eubQ9K7LofK66j6q3zT4Guf8RJUbdEAwPX\nO76Nk2K/YZetp9kO7l+c5cAIr8TwXPfl9w6+CZ8CwysJcd4GCwCkfBAE6qXqEVKayXnkzL+/gi9q\nYhodZUcg9N6TE/MQblA4jb3J2ttB1IdT6RQqaipYfiglppdRbRW1Qij7hpryOT2LWAgda1QDnOCw\nN/aRmOHe3cYkOP7spl87Ts3hk7E2Ax/UCeVxagIHpfy+FrsHZ4qiX+k649T/cfEl5rBbvmxA/xiL\nCwG9iyKqxglcf46ESxutKiDbBbgTxm51oe53JUdUJ80WTQ9/VQIlCKHVZPeWam1by0CZhhQ+FHPz\niRM7iAkCLl0ad6jbmsTBDB4Yo3j9GzlRn4OwfvkX+1X6Br/jpb7Ods5R9sYdCU8iirwHrrDeyl4P\n5Oa3TjRfEeRc/j9P7DyMx3ksTLodItG9x/vZWgOy4iFOa215lI7+X25rZS1Ummp/5i+Xpg/2bqL1\nYc6h7fbQjdpHUXjn4QUz0LYvmc+BNdDxx7TgSkeXOeHhdOTNPZBaDLDk2cy+lw8H7HLME+RVBt1k\nsXgcUBHjvvnpcteXo3EY/4mNbR/ZqLeXimXlWhSbjhCGYDzmqa5rgtz3n/CYymQhxCskPAQGw+sz\nezc1Bd1Gs8eiRp5AYUfgRpr4jbtwjt6z++6Vu8p97biVpBs1ExN2/VFrFqgpOJw9uA6QDmVZnx8t\ntsVnG09ksxL5q7LXryPT74zfhepy7+7aTH5YUpDpb2waeTIFvBdg8gmxXZB2ZJNSvEFEPglZ4KhP\ns5Wo15NcuLVfQySWiiEeFOZVqadoOuNZDghUEifrUf+33tFg6SeVx+zBDJbH89YDSGPONwYA8KZ1\nllfpAVGLBseobFKvocGgdqQf5YsUQQL2aNanPQqWDHJHr30u4IJBVKuluk8tjx90eD5z0fjoCqq3\nJds3DQnYjrQ7BU2xCixiaN26VICrnw47sIinfFcVXPidugt7ZC/KdJ/aQIVQbkrgDLjDxprUS7W1\nFffseESv5PsMOXQPCsFvlKPUCAAM4JKznpl/d5fx73jhcyMXizSXCoL3+8p/2BFB2u1ZYbisTH6V\nHLzAnIYsfS7eDvpwedtN7UZnmo/srjqJdMDTnCXrvGjHEr7252l6Ipuygr6C+WLPMQU9rrfvIwyN\n7t6vCh04Uqaszzc5CY9Aglhmwt/2Y5fx9JkGZumJynrdGXP33p2621iPJ4AevXZ3fdpNsCsmXnzc\n03cELWhMybwOw1YYoFbfYaz0s7PGleQIeLnk/884jAZTBzjHWSoLCwehSZqGTEAap+F/qiwHr9if\nuKfdQfIf1sOFlHlFnmEytGa24c0rloKQYqZPkuEVY7dS+SDs3W/Bcfs8x0goY2jaXFj4ZMP5UuTc\nyYDHI66HFcvlFknDksj2QlDgRfqZvhK4nKn/ov1YLKpHRhjo71lyHjJm2VbSQ+0OKQv8nqczLIpC\n2mynrP+VJILPijymLq5vCPGo6QllgLdqvuNKBIsJJrlMhIMyMmnRNJvVS+sTiwwsxinybxQicOf4\n34R6e7oY72ItEWWzrwJMtmMMcQrNBoRVgZsDnDu3B/iLN9B445+Ia/2xI8tg4h4bWVtfUrPF/GHF\nCCMcBaai/7iqersKU25P9YqCrW5gzK4yd6hHRVmP/GReTSC8etOcS/dQ+iH7YAw6g+VqwGCE9NNq\nrDHzSFNHzcuTFPuPTnjdDyBuk8tgZ2P8L+upWmAB8WRT08N0FYWxRVHTgdWwIb++kpR4oah3SMVh\ncMdDNeDMRXWOPYx+eoBFG4TdDky/+Rpt3Y3t+kXs5rBtuM3mN6lO/N62N0YIWBy9PPROt6ABLhjn\nkTSPxHFYPlq+2tW7Yq6PpB3gOJgIpw6Jd2FVY/nnHFVGLeti1SuPxoqA/zB+RqAZ1ugF1/HuD/no\nlOzP6btVSLptufMfKGXQlqJurAbPNswzU1SgOzKKgJWsBc8A1dZhUmmODZr7QJWHHjXRe7yJioTB\nSe+1t1P79UExlkY2Av53wBpm/Qf4fP4wQc1SW3DW0IMbQtjt9uv9/X9fGV6/G4GCcNq3idyucymc\n5DsqZ30iU7nUPo5TDk2xTfYTo5J6KDFbWg68PBTUjc9YU+xUqFwxcpfCVXhHxosuzfUSnP6d8DrK\n3sQNP4khBnas9LtuKIEewVH1iv2IiKUdT79XbsL/vFcNBq0+Sqvvg8Mk/IozOebCZTqLA+pRh8j1\nPO0dg1EYBx38k9kKMWWaaucDeaXpyGKEurCt+rNNj6O3iZ4CRZX9o1/noytgel7upuLBzZqGwGps\n73AtMGLpnD77WEcHmk7vCb/9ZIQ/1JqILIS7tWQrpz13TnS0vYnHyN54RndRSVrH3tV5/OmRT8Vr\n86wb6pLSlRI3+LytODQtXr5Pjm9zRxy6ohZ3KULiJ++p02B77O1XtFtNs3jRNxHwmT1DpOf+e3YF\n7zwucJ1nuZyIc7dAzGodikj09oxWDfGZLpGvUv8slbHALDP09Q1sZYzbZb1WMxARlYmMMbOMv6bp\nqXEGb6OxN9Z+GzBYi3Txjse2FDv2HMAimBoCXDRXlk+yVpwUiCn5LTOOrLgekPXApsjOz7wN1iAF\nuPCOno030qg47WpIfuuAkwTBNanyjM9t9kGvHBUbYvNGJkbeRm8WiEhVGVnfSDbFg1e8sBlL0Lu3\naMpK5PBpegs+vk8K2IkOGYvR5Aow1ZeA5q1rcMpEdIMR3mvYVfmtKdsviHZ0E9byAXZKlxdLV500\nemm5GQ0btI6qUDeat0/afCtAal+KQNfrpHPt/BKEshvW65onuKtkGdVhgINJh2YjRt6jDRwNZQy0\nt2/zk33lRdcQQQ8LBhOyDN4ulcQycDTY8OirqCVBDoNZ+9yHallJ2KKSJ36/U8NF0hahr7y5qtSM\nA/CkX1Sq/WW9AUQghL6/flbo6xyPz6Bk2CrrAkVR1m8WMsMYMTJzDzfobDkq/uOLuUcYSHS8GNM6\nIdJqSHQHu56KgPK0O/DnWxNXJkyeBTmFrEEAeToW3FoLlXfLwtvWmC06ciSqRnbm4gQimtKLA186\n3MaT356eSiGNv5qN+OQ8jv9hOKg17JmP9W2QWQxotOSiN3CpHK96mnBgBkpBqeksHSwkZ0Ym0Qlr\nWv4lGLAVFUI/rN/rGeRGjup/z4iwy542LcR9kEYZOCDY7F+46FcaQVcgrEM3BbZM1pZ7vMLZbBAB\nNIp2+fxvCHdPb2MYCkQJEi/lNoxzKSXQtUF/XliVdGDd/gJwms8Xkb0HYbyyJaWmfe/7DA0SWmmI\n5fHk2ePB/BvngIkwjKN6KMMHlozyCxLMBeUviR479mhHY3qV5gjKRE18cK3t6WtqD1l/r8fKmf2w\nmzxkLYc44rJqGUZqz2o47L0QXKUl4KpIGJ/PgoMPvA1kf0RdRqeBduHyjVFsKxHnVpN5TcWOPpEw\nsnzFSf8uh2B3xmR8tN3FtBy76kvQdN+6jOgMRDMtqYF7sGVg9vWPkeNNYzWk3rNC82l1Zzzx1ztQ\nJPblX9T7Eopb8dQclIpQtlVlyIvKm//abXhCgGVhBiQO4HX0Mien3FDZ990Z+ACbN0ccUL4Q1a8i\nxBtv+PWgZCeEA7utiTzOAPee3+34gAm6naicmXjXFCr2YvuZ5nD8J4hTINSaASRF8YaSrvYywwTy\n0iiBeMiahZnjX6Ra2SrDx7v34srF6/hoMCA8DyH1mFmdEUrCRgE4t6Hi1YVAINEphDeCGVVAVZ2N\nPykajTZihGf35IIRqjlR4U376Y0tBRNDAGp0Q6kPtvejvKlrZKN4G7r1lJAyP09bE7KDPRmbs/fs\nNyVC8RFydYUivRE6veitQTKDOMDm6JNj7qAaWp77cujnVGbn64Bd4xm7WZeKIKIm4aYSnUwJl5hL\nD+LcQnpAu6AAfc5YHgN5y5HYw1yEUhRnMl/L5Bjz/LberH5kV5CAMGc35Dn5CCsgW62MH0Klur3t\nqvDQ3OvhGmDL4Y2xOoW4kBC/Rjs4GjGtRYrXT4e2tlpknnpaKlAKV1YKawJ0W5ajt598+Y5C55Xi\nFrK/U1x+yGGVlKNimaW2agOl9VuEcCh6glCflnLynYngd4XXKA2JKIVNlRW01Xgdtfi10B5ipXZS\nZVEoJ/hncNBjVQcHqAeGhnptqMCqfg7CcyShKr61kfcsAc5VLbEphtId0rpP5V0qOrtNJAKxoEaN\n0ppVGEAI9TOF73jTYNy5e79+kav+WYHx6AgbaL192QJxAqG6252UlyKD+TN3wBZoObX12Adr3vX0\nj8zGgO0he4Dx9Cc1zYRKQf+J+yMSyWdmVEp+MKCbgyK6LEYoIp17fcKhZNmAg+ZS36UfkshviFTK\n+POKT3AT1fvcHL8OYw/QdRPMaLWPsOWPzcq4yVgeUMUgiaSnDUCDUB2yCO1vrkhPMwKhlhn0LwuZ\nwfM3h+czZAHuZRighzjAJUXwkEsN1Pgt9F4Ga9v4FpSBRve37ucHHuEn5jrX7b93oBywaPyG4za/\nsKerqFfobeFqou+l5uZHAWu9PB7G/36xCuN+gmjhdwI/5TjKnJGVa/Y4mrJHsK6xloq5ez4C0iUi\nDmzKDqJoGdws5uiPusdI5CZWqgii+tJ8UWOIJHe9wGCyFsM8DcbrnffJ/viThaJpSCiPR0zFv6En\nui3LW356UdHeYjk/6ZLmILb75WrZlIL0kBuk74qo9+iFxkDdId6A9FExjyh5C0dP0BDu7B53lknF\nihlFcZBGxzYFi0FbzdfCEM2K3tcVp8899GthOJgGu1N/qgTjg7ZC/hyW+NBVWOcsA/YI7H3p0zgC\nXErEvovgf4PesV8V5YrcnbNOLDkF2F+Hf+2W32/JFOuPVvcNZ0gw633lx0jeGk6zfpU4S+UqC6Z5\nlv2D7EYFebe8OBLKCmRA2kE6MXcrMBmFn7B6+0q/HxIcCLbSLBhEYooIbwK4lBvBHwt3ZNID9S46\nrlt9jHIYAJJLaDmqvniX1DClRh9zTvsHpSGG3mOKpwD1pbAsE/8AMN715F7VM9sLDloqgirm14c6\n6KaiDL34h1u3UPQcAYa/iUBBFD/omsncOZqodQoWJn1t78iJvCBlDiE/KRD+shi7MBiWR2qJzUV6\nvszTfqHmcpXqEKqJvAXBiNAYngR+GmMYIbTgB1YEwXQCZD0LToUOiwp5anTrAhDmS/ZUfyPA3O6e\nTeDJzu+g6CkNKGT6qnI9zSYRkn59rzdWimTbmd31+E9sE3oldZ7yukJKGm9HcrjmEn5iIHN2ksfy\n/bkuKAzgYebyoHDYTZZ4VZqRJkKaocRo0fbIi3zd65Gp3s5K7YmVN1cvTb30eNMvckNTr5tRJMXB\nQ1bruBwB0ntnrr5x/IGxj/XRZ7/oSwIkJdyNApk2te/birUbUR6UnGc4y4ttNTCDEuqggW3Cbfx9\n9tQdOjLwh43tPYA8H/M++ZwOf3HhfJjQQKysv0lOWY4S7ARJ3OrEoqKqyXAWdXniajcpDVbynsa8\nNsjwPf5WL5HPa+3iczXjARgydFiLFoxXOvEHjL7tJu91ngVLoHuKCc1sVCOdlfYThGi23uWH7vJ0\nYOLKmVWobVhcf5VpB8+yu1Am0dOHkBdHCr3rrgZdInlMue8oop0PLaPmJVMowyGjsverdCv6z6UE\nOqIUWtaPVpiBpHHD9Yw6XYxDCAiGibe+Gl6m/28e8Ym+QSzsogPaSQBf0SelV7KrqzHbId7aPJEq\ngRCDJzmPbD1Avv3QgG3iKsbrPI2KxWvxVP0dALSOEGlaW1luiCFhyVQZMjhvB2qkJbqeiTDhS7h7\n3EUa4i+fV/sjeR56deRJoqqk3M2q5B2q8M8jiW3dXI4Bxnmf1g7J8vrQ+iXPrLgC2JkSbeRZ/eFF\nCnM7HWHG7fLPw+dEcoxCvhyjiLG4nrEVGBWGXhUmx7lCGjGBUwRSXgUKYTNM+tVB/GGQSLqO1BXa\nqonr6lyJ9aQG7gc66GT96wZBQGclYbR4btuwY1dBNSMp+euELOd1xEiLYTm8oFfu+4GyZNtxGaNH\nQPGRCGjL34JDEnum18YLX1sqaLAaI4Vd3oohNrCZpQUGEPboSGGh1OhTL0TcjUaI1kzx5pnFFlQW\num+7966tMQzGB0widT/dnC203OehdRUxF3mVKO3vyZQS/QQL0LhvmTW6F2yZftZZwGor4BAllquC\n557VhXbkeLpl/vbtt0chG5IT/u9C7bdHihJPK9UT4R88nM21DYUK11SdT+pomG5JH2mJc3Io3YzG\nZcfbv8KIZsybNllnnP/EBy1sp1maLL9qN6kF8hDFHfB/Jr2elZJJ01JYHPOQCHNy+UA2Gl5QwPr8\nc9SHuUtr8rz+WAOCvege7emLx4Jt5ytymFbSfrvoRM+ZUxFmqe62SfHTEzg7ml6FYKGwZFzHxAVP\nqClbYQVma1hfPRcOQ2EPNB+IDQvSMtnMgfNCRvCXzR+Q+46QsNEdqQLttQrMkLWYUWQ/PxH/abKm\naMyBEKhbB0uA37pA7d7nNWme6VWCZ7Phlw4sTGZ9usfSAF2iks+dhfHFUczhnkRr5kLs2nN//1Hm\nujL9S2Xh+YR8mZbK/X/DNNxk5vMeM2BEVm1PZoxk2SRTp2R/vYNolwEbwelAj06fIHNm5MpYsL1E\n7ncTpnND/46Rp+9dC46VWjFitJhw6xYQBnAnAUgK5XKJoMd1ULWbXo9Obn6RduRPzN0a789FLdcx\n4OyYK3f61tQF3inIYC1r1HHOGDrI2xRZVZNZNDzADjAcygRu1Sw4WL8VBi/vYsKqVoNERt38KOEl\n9NyG3q3+6TPPg72wauvsj9vXnxr/ERZ9FdkR/nhOatd9PJBBtPaEAMYvPNJ01ByAr1H9v7EusrNo\ndtHZtpRoWhrKsTvw8ChWSzj4E7jptyFhnLEslaw4KGbKc0rKYK/kNZB6DrrEl2aCV7QHsdkX9Bj1\nPKcOWqa37YQlp97WsyhXrowmbd3CistDmVeRnzDx4swr7Q6boEig1BCH+1d5aIEO9ffvu2QbMvti\nAbcrVFpP6sBalPmiLjS15uhWV8KEGw781zQ4mqnoVw3oCKOuwjvvK/9OhNoout6ggrrMMfHFLop/\n7TagcwxVB59eehfgXDHC5RxEwiKlLkX4TdQk3bJgWiNKjaUI0iF5sXdRTcu76owM9bPDeFQ0zvcK\ndUkPtD7AXtk/vFhKjwLRLeB3UTz+YhoVaUH1daPHUMlMEH+eJQESKAxgCeuJAj8GZnyT7+cw0TT7\ncjpaqS0H1C0WUL6EFh9/Re8yGO0a8+1Wp5GoD3ceJ9EingExgibnx1rZ3dLJ8Hmf4F6c97FHtUGj\nWWra/KN5WoCJrdl6TSdm2vPt/3JFImXL3VxVhD1lHg5jk87q0UvPEFJbe56oPyUDYIHorFMXCtkB\nSp0+FG2szkowh6Po7B7p6lTueX4hCfE63q/RjQu0vNkacOGXYHvO/nT/7D6KtFG9OpRZwtuB5emu\nCGXEsehh9FDIFrOpVZN7q6ME4mkpcEBoVM5qdWoVt/3gUeGi7NoO+67+Xub8tmwmHzbP8nOXg3X9\nfNoTD1RXYZyvLZE4fAJJsmUmaxheX5QZ7wY+viDhcuVgAlnxxX0LLauJsgSdLdbbADd1bV5VS5Lr\n7B78FfM0LvFrQA5ay6ZN+k3078VR8KQ77wOOtuiXuls/asxNNLGEZe3j1Oqa8f4PJaCMlo6GC4Fw\nG3ADbVBwDp6yZwFL+jqVJcecF0yGso2WSscQ2vtmwXqV/rt1ntgPMcrqJSBUCsg3n8UAqSqyrJMP\nFl3aW/zxO8e34gRl8Gb+Av7qEDyqQnJbSeqv+bQRtgG85qT9oO8xyqlwpsHqHY98338C2Doe0qWE\nihq/+PAb/4nr9c5kJKMC6aqGRJYAD0fox21bybPmT4ZB2ZffeOrw36ME+hNkiBhNVDEW0j4LFPfC\nYTBRPHdDBONBGboUy+sX0hhLEFqDxD/pZ5nuulAJ1Gnpq5tYOdAVxsaLS4xVsiN6zvxKorSgpp8N\n6MetCHR0J1sVQSDbgLtEnrJ7/7F0wLUSS9jjxyJk3JHSRXyJQkLPrGjNvsgaaZ2+lUq84JavE4TW\n9WVMjvOBSoHbjCPnbFZC8a49DiHvK1W7MjjzSoFWxEqbJf55ZKbmbZgJvRBEMomcR2nX6WZLbKWd\noRt3xjhQXyyiLw7QmCKsylEF4+dhqgHIebhz0y70vdoOeqc0rMJsm2eLHLngRgytaRry7GtPEs5k\nEPzKLb4IzUud4aHQuqMS48KrQWjqCoEMqJC+/cyg0GMCPX8DoZ9NTjThi3KQ0Zm7ccl0zBlw3HJO\n4qeihfn5PUbsuXiimxdpDSOITExdNX2hgIYo6AHvcXqMa/5Srf1HuJLKLN77iqK19L2yGGkfG4cT\nPp+WIn1zd33WLqzGEEGFwucN4QrfZT0Mk0WseahDZbW80vLs1NuEfK2AfMYWc+gVKQjjNjUOEeA9\nEL0nVCajyreQL1X77MQ/Z3f7MKXlMZIKZ9st9Pqja1Wqt63i3HjrSEDh1cr7EQru3+zBo7gAIJNr\n9GzPVfhPzNmlRJyLd29w63i3/hPgjFiRB2yI01ijIow79xNLQev0WpGBJKnLZIkIGQdHfPjySCPp\nLNOOluCTX9RiV7C2yt65IAYwEE3Rmu0QeEMTSJr8M6cwP8mkQHG7TC26sVsjzhaVJ31m5gOTplWS\neyBIdXbYZgIWt1obgM5qbXkjN05FCv5jjW3R13d0x6cAu0lu1EIU8Otrn3d7K7abyyOqc6fFOCWC\nFarr8sTVDJSYHojX+adnx0hjaUrcMBbGBTKORHKWrTFaDAPouT+Wyu7oCi+Hh5VqU+mZe/qB7Kxj\nlgqWgjbbdcxQ8ViVvicBe5q/Ovu9OX/S/BryWWNVpNVVPrNNP7Ud6AruH/fVFpmbyTL55m/dllDf\nEsoSG4IV4Iq8y+AEYbXrUUN6PUiM0B/GGx4FWgf8LDcPntO8P7KQcTV6F6MLG/Me/gsMqJg9cTka\nGebbtdVE3YGk4XTN1vGthwkfPh1Bj6hbaXmcvd1KVqWndHf7ySukioyKHVdLKfaleKZQjgYrFC3+\nk9M5UF8iyFNdxOHcn2vCBKWVc1I2pd6ZMR0eYCpW3Bl+UUc551rT4YjvRrmtgQDJa6pyO3YU8u8d\n4WmETh5BlAaqkEDHrICLy8G5Yep8lSuyYflQRyJlV2xhgVqOUJTgtQij9t35ogixJNN+XdeAvnZN\nYp/xoGGboGv2dQbh1AB6/hISTyoeoxiUiY8Nc+wJ43jxi7Zof2SnRGiGZO+DEU5xvGRXl2Ws30bG\nF6+Am3Fvx6BC8+k+3uh9EM9dWQfSBMnHdb3idchTHaECxrWgQ6YbLbIwFuEO5ZH79Vq0tBc5et4I\nGX9TavQlby9lMDPpsiWQoFMzvCBc3iZ+lZJau9LWocl+f/9BM5rtOdI0HmACQiXtU54IhGtfHCn8\navgoEX6YeYOtrL13mkeqZNMTwp9lDG2/ChB8jfBoeD2759DTTH3o0cL9Sf5OTcuPA3V6/lQNTJTO\nF17UEFBwpnizy/n8XdzKpjU+gDcJsRcp/WGYombRXjSxfOEcYeRGaNBkgmqcV6xbHB9voCeSyNZQ\n3NYbjLsDuHnQ5i0saD+Yo1ryDiGFJoetyr6nXA1l8onA/40QGdAL14rfQV6HmaKHRVYCsF5tQoxH\nG29OdGuI0EVOUfIt+T29zFbaLde+rv8aqiogYctNjvILupJVMCrUy3eB1cYL1r4cE8vDpaIrVw3S\nlXsgoXh2LK7PC3REaCHJDLS9oq0Nxu43MiAuaSZ6DZp0U5rHH4DcUGKGK4LxiKC1fKZB2YXk8CXg\n4JmMulWsBZyVc1Hs2STEooc5NEZRynFPyNx6sPwUKpBlwvxgPIz8ashYeArr7pgtazIlQCV8RsbB\no3WNCfSTrHDscYbNhNGSN15ujTXyZIxf0xmw1NxhW4VE0LbVbU4Q9muynFksh/f+O3sz79eTs2Wk\ncj94qweFDzzDSKfo+fYFxr35zCg/FefHqD9FPNrkArUiafPmFRWLGkm6SWycHTHW2dmOUxqBLDnS\nKOU4i53LrnwJtNlnnNbR9vCnTV3HZkrvTaGD1GJiRzC/es+XDUFHEb7YDM8JUKlRbU33uV+CnXcq\nE5Afnqcfch6xTfp4W24eBeAxeKZEXYdjLxisOYvQ03BbLnt/ao+HyqjiaVos86B9Z8guiTv7Y7vm\nU0QBEPyFWR0ehm2yrjUy2ZOjpN+dN8ptlOpi+8jkgisg6gYT2U8e1S2pPCrAtZwj51rEayRg6gp+\nfZ1+HBHDLTW++YMQshPGSEXZMzn40VO97CNjgrh8ovSvROZzPoujNet0XF4Xl+0pRfUzN08GGTzc\nCDNZWKvs7QQNI0+Jzy3TOqD5OoFWQbRf3ETptGJEjsxTG4xPlNBT393qN4TMLuz9Lu1DCUKN/auR\nkZ2FO6X5bGfE7IJXmo05JK9M+NQ17wS6A/rJrHFTFQG3i3U1xyCqWFjTpJJamaXa8Ap24WYvz6dc\n098Zr90dPEFqCDwe6hxyVvY5RfffPzDqQb5DMiiFBA0+l1lXQ6msvQO0/PjN67FDr+p4RuZxhV6p\nTCZm4lrQ47Q5/Asnv2QX7XT23yACOPXvT5VII5iJx66cZDW8PqcokaLa+pAtVqbgZDPxZD1C4NXw\nAoObbkqulKoJobs7EjZSIpKQqr5GCZ3QjgDDwPruhevdnzONX5uBvI19+JYqusyuR333F376uyvK\nn6F+d/zNdvSAV3gIz9JaPPEhjbKgsUOFhdyDoaXdydwVHrAB1SkIhNzpfNl62QU0h9m1rX0tPNdt\nUnlnjJPMTjVt7hS8vJhfgtk+39dFB37FS3rVDWUD/97MlcR8z6MEGzbLsGSRtQgzQXSzXL4ruX2E\n7F8oaVsrywznJGiEc+2zzA1QekJQuy5dxS2hvHftZoajaCqWhhrACvQAE5HTIr8etonzlt70MhBX\nR4L2Kdszs+cuKe7YCn41vp6yn+jkXCpOzLOekgT30vVB2cScqwhXUnoA4eD5oeMK/VvSG8OomIto\nmaCJiv0wLgJ7kJsprJEeL16mqTkMwmvay2FtiWlIWbKIs9hgg5RqP5ftklAYWiA/4wg9CMMoH2hp\nuZ1nni2cWWGynf2ne0XC1qDqennT2JyNAQtk9Jw0eXHvjVLarN4YgyFvFTr0C5rV9472azo3UE8A\ndbhgNUf94/74joOWhz9K0BX6hu6u9am3nZfHjzT8iT3pq3MtSlLDx/+vqR09j1sBXhBoyiyASoio\nhAQyBIlf137OHYUONIvyzXe1M6PgVDfdvFr6g7VVEpVZDeSgkN1SXdnbZwYBVLOYe3JTzPfiCNmw\nPL+c0DJ8OwN91pieUcftyhX8/4nraUP0jfbmoqYneAn2aizdgj+uYZDayM1DDIqG7HkWgfoTyOux\nFto6L/LvFuzFDe+ipcLHg/txvv/oK16fIF31ETqIDIKRU1LBbQAbPUwEZxC+TEnpkcr6oVT0hwHN\nJuTLW8ZHgsVNC5YQaLbTIU0uVZ2AYfXpD5jXx2DHxpFmqpwAA10PEvjjBwEXurS92XYW6Vlh3vag\nh8071PI4Y8h0dlx5dPI/VyJA5MsaecCPh9Wc3Mu9ju7CmJzmdnouyGW49lVc7T+BFgn8vY84W4Jy\n0EOJqxtbldn/b0RL9qNfkmndlxOOYUGpkoTDXOeKNtd7HyleHoQUnqsrJltt7n1TUWyBkUSvmr2e\nhIco9V0pfGLnQmBrcS8ESf7JoDfid3dd9xhfTYd7x95o4BpLRW9VbAnUv/qzO2Ql4PsXD4elhlqQ\nIX/zvEAslyulqRlaIojF5lfyR5gs5T3XDgy9J3wvtzGMB2e/OdhArVKDlyiGKVBCwObJBltJLdrm\nqQtoqvfdCn+V9EPh8P1tILiKhp/pxpNcMLi4F54Ss1mMT6eOjdsUUk2NgxCMXJ9DCe3Vzm8uyZL7\ngcN4jfAg3E1rqk3m/i6KHng7yyFwHWIWhDG1pdVdgHnmaVWwnYivlzpB/S7eNw4unSB3dd2BlnzG\nRb5PE2fCqQmV6WZPnzyEbQbON8IXydg2GwqhVl7d+KhVvB9u2DtRSUwccaSTmzQitYkii0ktito/\nOZn5ZAWREOagH6xk2jSJtB+raBOlZD/StDmobLXWmpcaSlaEkDEyTAMr+crVbeg3vAGSoSOK9IbG\nhEMMVUnbYc1PtZV+vY21I6ppYt5T/zHwORuaK4UahSEs+tc11E84gYKfibx4zaxbrR6PIWoRhFpx\nfygJGI82fQqpK8rIAfb84Z6eXjnfx8vNe3ePHTI9pkZghZ1vx44M7VPJerWd7U5zd1C45avIo7bJ\n7u6tesU5+cplrvIG+231DuhICa8DH9UF72c/JWk3FiHDqhpde5ScS3IcWx1hhrKBvi5FXoH10veQ\nlHicTS5ZPF03XuljrC096UTByid0LNhm3MEYNMhJHDAg//PphATDzK9kPRVEqWJNnUXtQxCtfaGv\nDDm9ZwguZj9gqtu4FYLLYUIYBSERRP0P3uA20WOHJw+chMy+nL/5NJ5IbO3bDpRrULtw20tfYeXd\nMEZRrVydMWKNjYU3WDHTREgJjguTG/o0uckR8jUjDqND8/aBClo3a38CpFmPcWL6ws4xn7mPX0eQ\ndm04/XpCC8K8rCxBby0gOx53dNfuWePoTZANSnjGGiUI5BxmFdAWSo6va4tcRBNNZMPM97o0kVhv\nEPnfc3/sGE1x3k8/zSHbDc8HaQOXTo9W3rmPsM1cLrN9t27Iox3uo8H8MKqn1YcA0ilt5LAjrSV+\ntUKxL0hO5/r4sVSAigD8X48thLABHsoJPxsvEF8LqbeF6ar28+m3HKCwEkXmuDsb2D9EH9UPETzk\noU7Zlu+cBilAsNow3MhIVGRoQMJ90wjs5tMHHN0coijGoZTA0lcU/s6NGNC2TOBj1w5bSDX8FKiM\nS07TxyW3rw6YTaoFIbD66Rq/NSP/31Z3DELdKtPR9xDQKSDKf8jWDeUMJczhi6nWPBQbN7UQtmrO\nLkeWuAHdvStParHRMDHlyl76hJKPEZy48fg9N9UdnO+Pd1Ald+lem+PCsHHf+OqbXStJyJ7sNQPS\njKJNQgifRKxMJxi0ijJ0y77hsBxInqwKBywtcfVKlXs5gwB5+HzKqctr1bzPf+oUVROtD4s7C8n8\nPRAVBiiazwsrGoCKpXRTQdmcPIWk5o/ljibexkeIJdZGOflQLAG79TkQP4VR589A9TEHqrbDA8Ow\niEvue5OjEfXk8v35rM5k036b2nWDRQjwgH6Ww3B4Lm4ynLAYQGTB96U9XWkAnWLiLp5m8zvFZdDi\nE+meA0JkE6eMo9xpSCwtthR9qC/ZN+oxyhOIxOtsuOB79uBllrVRyxq5F8q9Jv+a7IKcvLMc3+Sk\nZmbgOAgVLYMQnsj7C+GgRoA181qNGBLLADnDESGgJ/3VlMRVMiOvVQ+AWmMuns4aRjO7TJj0T4gj\nOtQxN5mRSOWygf4wDNFbjjzdk9Wrb+YtBxxP67a1DBY73E4f8rq4GAGOc+uA+vYPxN2cpzQMxn67\ntST3yTFSN0HU+TLzADeDsR9fli+VCAO40pjEmfvnmz8uX4ieAh1/bmsrpCB4hddDi4K7Pm6hCPVZ\nlNMu2yUJ2Gv7pSfim/c6uDmTOvuyKRHsEtHBss9V0SHiF7zsCw9jC1Gw1Z3hAWIEE9MWxlQFYCc/\nOJl2e+2sT7p7D6B+NL5udUm7nX8gB74q1PUFWPsGYpD2pu3lCBVsQcSipoVTozPzXTMu9GhiBbtD\nKMVzVgZKLQb85zYLEfk9esGkaaAa/IMlXBYyZ3KgxHNEQVVYLd/28z6Bgq4z92uZ+nUjAQQNhNbd\nihUSeLisI8jS+p0o5SqzysX2BhJTA73Dl1qC80tYYxi+Dgt6Ix5T5JgkBeZt5XKSBj+tWhDWKCDx\n6uUFw/ci6OktwfqL5KZVOMkEwPLWW0W3S4EwFRv/nqulclXjxaiEmI1qy2g3i4xu4ozAzfvuY4PX\n4TNsbHRGXKHnbUq3OX7WWl0FoO0CnTw7uzXYj3goIj+2ppauZVSQt3oGFMco07p5c7AG791rM2wx\n+pZL5s5qBaL9pScdRgmtmuslKlqootc7gQJ5OxR6mvoMhOnphhgyojQnOr+SJEtDMMD5rHlXoSgW\nUJGwt8q/XT7s+tAVwEfFZwcio0IPbQNDOOsdHChnWoWh82tTu2wWSgR7Kg3fahsm6lpYDnkid7j5\nkTGihYKRKRkvpg2Ws63TmPYjpdul3WC+b4ZOhk6v3C1IdjpjOJ5UG4l9tMkYVfoW7y024BquSO5/\nMPPdTM2nWYdjbgO42K4Zxv4zLj2NSkWZm3pkgJP8LOnt+bV9C5AceuFe2YEcYfHP2NnzCbPkW3DX\n7OB2UfViC3Mm7S4KKuGfnRC4dEAlRwcrCwYneuiP6uS0A1MNUvCnPn8WEs3qpVOweX2aJkYS5ur/\nR1bloUhVQUshGkVfjwbVCpNKA1Z9uzEmBMAoQ7XvphL37Gw4A6IF6IP0hE2sLueqpM8yW6YP/n2m\nThOWH112SQ7B6Cl1xkrSYRy2fRhCPLiOb/AIOrOXBfO7Htq4hRh8mLjn9tsBdxQiCauhjPtftHqA\nbnkLa4np5WOkVect6L/DVTK0V5YtCK3SVmMRX5+n/iH5KjTBdbJDG5zE1+cZIZUf1jHOQT1zGeYb\nPcdKviHtuX/dxA/zR96YYgE+6kvpWexwOMkvDnMeZrFWV3YA2Q4yzl1IMz7mxXAYg+xr1XhyQAHh\nbvAoPX1ZX/f/hT0d5tm7H0+hzJGpOMNmOb9uWoxbURr1oTe7Aub9LGHM7MeHGjRy0eeNA4l9a3ZY\nWaNVI8NHq1/gTMRD2P454oSx+FPyBOny6Sx3+WAXKWV4raTpFUBs/OkARVapcvZtqOP0JQyWm7PT\nCLXQurpYYnK+M5sJwh9q8N5Ymi5B7RVWKXSw3bTt5UpCMFF8w3wqLBnB20ai9FBNCmCWLZmqK1BW\nOT5Z9SWGsFad4wD/ykn7EphW/XOoLWY4gWTRReb8kUiyK4uYq3GdyedGWQMQubbwsw4Yf9XLQOCA\nveyvPmR0nXWIDyie/P517DyAPPR3QSsQaXWL6OwedlZe9/pJZvpyVuCkMvohDO0OiZBnKhw8c6g7\nQDxVJpr+PzuscPWWNvWsRleF9CtP6o3lVCPYofb5eni3/gew6UuMOOPdq96vjfol+ipMOitig/EK\n5KSSJc4ignVV1rpPdS8jKt1uRzdiIG04lIgKV/iTrGxulwFTYWn0YXZ70j00M7akJBpgtHYtEwg7\ntuFwF87SDt98jOPD/WHKwoeleWTKwDzN8dUG6rIIjciM7ttKAupuKB8zcngy2+VEd8SJsoOuiVXv\nI1jEkJzWfyF9h+BgpXXoFGfSUjm4PqBwqBTsya3TbfnxMusFwVAmhcgkODyoaBE2aPevUBLTPEyg\noXiZdFn96TTFBTSKxfbvfoWmBfJLQG+IUMH6XUArLaDvPsOewnpCrh+xOPs2VUJvRJlbOoQA8hhc\nBYFw9C/vaE8JPImPCF8Mcml3atuzrH8J+M55leKZ+Ahyde17lDJYmLaTtLVQgqkyaZyHgYJabqrL\nfvxMvqW5F5ysEsk4uLDBFDd26mKkWfaYPU1SQDCVe5TX6ZCrMoOF7QT3xo/dGRKOrgxhF80rEBSA\npbHEX09kRVpK/s7dJePfIDBOH4wslJSyr+cpQWARs1LDsRdJqfBnbx5MEQ4E2qk0F1V6P0Uu3APK\nPs8KsBhcdUXgUqbGbsEQmLHNmMsW9PItMgYMqBKVjCWjmnu7XFM+2WPGuA22GFgbq/HHjTvb4+a/\nhNHFvP4EGDou4Pq063a7EtIFFh0VzxeE8It65f8GizD4Z/YaE5NBdVql7NOdDECr3l5vqCI3HnNC\nrd00HANISl5oyA2MuYTQR+GQaXrKUzZ0cDbvQZ7P2epot1a+MCmRzUKtgRQlP3GEAOvl/z6jyNGl\n0i9gClFCTubmketbUNA8oLzc5tOCpMdeyfZX7wq1Mj84m63g4WECc1S400lGBZhiUvaRIgsEnvQo\n0/oWeneHemIMitJgnp4Mf5PvMfKmyud8ED+o05VrGt2n1P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protect end_protected\n", "num_lines": 1219}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\ngazeSTBrENHvbt5mZLx18dRtoyW+Km4t51uVxxH7ZGNnmTTcoKqZyFpOrZ3w8kS9aFoiQlh5unYf\nVMD36zgB+w==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nJaIcYFxN5pqUbzepnqrpmFHdFIYWDYoimv/QCWvvIMmet78lyyCu7OmAbUWaZA7w0zL3MGnfxCUN\nn3vQGmg/2D1qvx/q2zy23sfhZfE87aSbXcNL67XF+GYu6OLKGGPH8rnW6exQAoemSF54SZgfsVR+\nZQSjSgAEtaKfNJS48WA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfa+581mCG4lxTJxvsYAMI+Y0/3DEJVi5IASCLU/HkCRmXkai01uuifj6HPVqiueReLeiWI0bzNp5\nJVlbpO/kKqg9MkQMgg1uBw2FFsg7gfVjpDJV9TVBp9Tm4YsSrWm6yWxzb6uMaHsxRa5Y+E4WUKp7\nkFXmUM1qfaMPGyGNdQg20KAvKFwwN0302/mi6GDcLvLNvvne93tcew0yQIxg/gqJlcURIlak/g5o\ntVj030iWkuj/kKp5guYfq3gEFKVEr4SV1BC/f5KX961SkhTxXGKLNLPd//Gm7akdx9a4SnpGY1Jj\ndKETnZJbnXtrvqcZUh2N1o7nl+YTs0mjObgM4A==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nQPlIuDrSSApp/O5dvtKOql3r2+lVEipJtAA3M9T5a18Cd2E2LeOe6u54LQRqvqSgFUElg4Mk3hH/\nGPHlO6wLGkc68a2QHrQWBA8YylrYUj+OZbum9kUQm5R3TPU5Wchw/mhpqWpgPlWvyK/cO9FxrB5n\nHD5ZuDk7iJeShjEmKewIRdMZqkkvQahMZk1eJ8aT2jahULqIomSMODM8v16Cxv6S3q0ohUtT2DVH\nwOkY6nsqo58T1MDDOffgorFUWVqkQwGQ/maDu/KENCo/JCJZOAmODbmBfBAsXvg7bqGZKB9VPp6h\nTMfEboGK0PjL8yhECxqeqwtqHk+eixHOqSANVQ==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nb4dHNcYwRRv3ODYilIe7aZan8VP5sGFpEcM4Sk9B84EsHlTRadyHodV0BfhfsPQB7kezG88HW5h6\nWNkuMny+KpZj54uRmnCQmrVIyZTZC+1+fpR1i46q7pc1ZFH0ByfdNqY/66Ew72bJ3bqt98VUJ+b1\nKDNSnYmqrLKj6TtcYAc=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUFVtDvwzUgfeTJK5RQPCu5bEQXOVNdg/Ctt3LMq1WwNKEczcihJ2sl86P3NdRo0ERI8ueQtux6aa\neHgbxrha+qncx9ha9CjfRUqPzzsOn3Y7i1ixq84ynt9jVyhbj9UUv8UyPbi4K5iayWqESAXrtTyL\n4izB0qPIWl4//8zsVriy5QoAxHYuCOVTFT74KhP0GfBhGq8gl2pE4gyETTs/8CEabnJ3ERkaoy22\nqOEPUjVTsxS8vgRq8tS716SKeECQKpsy4XCSTfx1d1knluz73QztnOOUXoIisTy9nHoSAbC1cRDx\n3ja7kCl2MkDQsfmBWkq0ozzVuY4qo/oIb33DVw==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nYC06/kx9685ntAX7i3acgvLk/EwgC2VW4WVhE+P9S0QST/y6VSJ0oBWMmzsdOs5O1+nblcA3DkpX\niLfXgmvlzh61Du6yn0zIyDDTLrMYWINvRbXV5FG9pLM3G/U+6fTbBV97iUYMHPWk0A2DdkXIWMP3\nmcLuMBQc2y0dm038tnqa7fuMeTcvxPhQ4wTWwHXvp54ejwq4bTAhNgyJeExmEzOvR+zWXm2VgpLp\nqcMFWAA6nlUIG5ZF4M15/u9UyutQPOLlX5+QPwfoMVi/kyC+JK5AUrviJ1QU+rzwvU3tw3rXqAgE\nsMTi8fHZ/Nt42HIXty0cXb5zEQDuP6pPBNW6XA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nHg7KeQWoQfRjpmFIAWAFbtestpXMcHBDYTZuLUSbL+kKuRGBZWT+FXknqinVcx0pJ+q5acUTBtyX\n7dcJkS4qdpYpoaBETZeL/wcOfYFz/CcO2z0+LWoGRDW3DzXn1oRWWZyJwgJkigyMIHPH5qxsjDO6\nJPKj81fkKJMHi/vC0LbmZMiKSmWL7sQNeQyH9Dn6VLxtXovGL9yVh0SoMlG0/v81wA1TX/bXmqKJ\neUvzBU070O5AHkn3Z9WRSK5S2L7x/k+ltWDFho5jtXYcevcbA/14blQqT6/9PetAyFmzvbIS+6Sy\ncJ54zu+VswtKtSOWyzlOnfx1Jgt9q/yLpCG10A==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nn/U5obQaKe7e57D8Mwxo0WeDlQ4fxz4sWCrMViskbh2tk4bDpeUf1ENBUputMkID5xX5gqlPeFYH\n/lod/5hBiFEecXymoK17ADl/jmNo1MjfVQ/nqN6xaJWL8VqmPoJ2XUvVt/nh5gTeI6QOH0BkigMy\npLFieK53VJ/5XRJXmLUeyAKMuQYF3FZPQdvCn1NDG/xTrxv61UqQKbL35Q6DuG8ZqHIJKSJFVln1\nchCHgEOHDKo7nJ9MCjYRgwBWPGvr+w4IgHNPDhatfWTGz3wjSXmjYynT7/3ZWqR/d7FCLN+lZ/ht\nr87GH/juUmy47PmZd6QhKuuc19/j3eDrwcHg8g==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25472)\n`pragma protect data_block\nrVD/wL4DHCsEfzFEf1VoQTKecFocJw604Tk0NgO7M3ODm6t/6/biD0QPzz/Fzy1UxKBEqQ8Nxpt0\nkd5dp5nyCwOVRYlAXNcBHWyWuF3ImZ0fp1y2c4napTVULuw+XU5nSbEmfo3EFsLjHWHYarc33XNE\neccwGpgfFccdUa90fp+q6imfJMIuCWHWowLNMDGdb8ZqNKZUIE8ob6W2adzfUxW6BcwKDMhYtONy\nphGaaPcir/7ub5AXgPuxZ+H/dTq9wgn1aTqOJAp1ucnPzVq3IUtg1OC2yU2vi0qMrGvEVqZa5al3\nShGeBdw/lrrv+XpB0FfkT2KARuuSvzee9a4oDMMvB9rD6SluK40ECZ1+yy9NV8VPy1Z2E7wjjpHJ\nomuIJmTDG6P4NMgl9qjKSn4GSHvEJtg8Hs/pMVAdAds6SMK+O9p7rBsB9TJ+Jfe+EKBicHLzhqUf\nYcNZCfyCtkGAWU7HcdbTu9BHbBM7GuhixBjPG1gZBzSE0WtB6MGt0YXj5LC9B2B4gUc+LuNxNcc9\nUKE7AQ6OnNorwxgTIT1j4f2lTdDpN7naMjcc0dFrzhwLEt7EYhpH25Cb1lTtbt3ny3KVcWNrvcLk\nv09yJ3wThnjJnQl+GUiERUgWu8ROGl8TiZbUBs5yecOS/BsLolr6ykQh3uUot6ZrpLggo7e2zZy4\n3svfbA7sVv+IfBOnba21zodL6jR5Io/8RZ9dAtTSxEkwNKn6woPbXr0vzkNOcXmNshPgXMNfn7kP\nhh71P3gVjrM1Z4XR2k5FHBKIFP7xvG46B9zLPPSpe9cKzJ4DSqgt0aNr031h/E4RKIrUZmmfW0JP\nOP5eFKLhkwM5x+n5EaEHSfUgoGX++y4UkfnBJWjFbVIWdkTMzBCFia7/hFiP4k87QX08uk84BfEf\nsgKGgULddxVYXIDV7mrWaO9Cy6yLEYGh6+7ZOBVM7Zy6cqp9LP7Kc0FPdoy8x9BVG6p/reTiiw1v\nNn3v32uEnt3XP6T+LoaKu/6mrF1npJimdRr7SstYkFy0LoyzKWhUHUz/VQ3iwILTJ0JnGP770FqV\nmvyHmvHBk6MZTTlNhtcVSTTwbM0lw0LvHbExAUCD9Laa09kQXtQstGMFqjckEvN2jqCALunjsEkp\nBQy8rtux02oSB0O2baktMwI571Rh+4HmnparL2+x49hG7tthybchylTgZbFDHKBCvdQBZkzVuo3Q\nj7Y3oKUrm2bmuJSbom1St7TbGFQq8d0b0kTXHL3I2ohjaio0dcvYDfVg+yWz93shEUO3Jy4PUuCC\nxhV2WTmsBi64HHIJgemiKEoZqO3e18N4F8cdUteag8hQdvF+6ZlNnZ/ms6TH575Di4UiksGkL0FR\n3sJm4AQ9V6tp6J/S+c+1flwE89qo+Xsg1/cG+L8vSsQxqyAk/ovRsYwYHiS7Yy4/606czKjJjQLN\n/Od4Z/RzSCDTe9OkRgKnHt5zK3yQjI9keM6uYHLPJND8bpBNdWrqOdAkXjDHjM3I9U6L2JJqeXVK\njIP4ArCrIq1ZHjpvCnFaxB+/+BBdYcUPUm1A5us5vUT7+x9nSm5EoMOVcMVFqrdJ27v3WAGi6+E4\nKO2C+XigT9fiGzmzXlKKtsTeS9pPq+XJ+3ohj5rZIoPhbrKxWjCzmpLqwAJ0gNd1WFfrHgE2LOe/\nH0ryLItmrp8oOSGEdzqkIi3IjIWzEJsFuNK57sg85CLkLBrD/2GAE829x/TXqmIJN9TXeNtV2gKP\nzoR4NFQendQZY0s22N8NsE4Y00GMNZhaQdHbxhimdXjmLk0d7qaq06rLRbHcsoP5Sq1QJlF2K1qR\nCGKoiuDSQoQ4Ys7EOeerLV2n/FRB2yqoN8xeHjway1HTDoAPAet9wYutlxLTBUccGt+zU65u6OaV\ns1H2YlNFqtwE716Dp39IzGvOD4w6IjA/vBYiXj/dOVHbBBfQr0u5i5m07Mu8+ql9fOGoJP2wqBln\neGByChXLhb4uLoe6Bht9vwf98nzSbRmiaYLyALBXHgZKs5L5Udkanozr2NM301M2pzP8QIPa2aQb\n64OnBA4icxCxWwz320VkF/K5BM1ObCLOipn/07v1naPYJx/9aT/ZVupp+QL9cBnPp8LZtldMFsxi\nZojdTH/u0pOw8jx+SH84VqjOEloFoTxTXkAMHKRulU7yj7ZmWlEviMhxT+f63SOqtMW6bd8ndq86\nbFiDcjGNkZC4YUerGzbOM6M+me6Qe5RcwL5VJARilQoyPMlPtvzSwMzUJQyUmabaCEispxMMZ3QX\ndNb4c+W7FDY4fxsytOmuPwhCZS3ytA1vCB92ukP2KVeOien0DKc4mIwjdBllzW9+QN+GNSzRe5LN\n/YyvlmAWUmlNSB8smtrpmB84JVKlWaXOOrpOLxRHtFaYpnmpmXJcNveKAB4LMvGTHJdEDlR6LZ5n\nCgWcU34eHvwxJ0N7D9kxlxL15EDsPFjxeT/vykJmOvcwVPmia0M2nwFaolKZW5cm0pZvf3bzkkBt\nkxFF4vDu3VKJBPN1qqR6ngJ8w5cII2VcSG+TZBxeAg/XH5mW1JuetQkNdLK940Rk85qvx9Z5tYFu\nFKrDM/P9zlRri+ggEpi73JzEUnuwXVzjIe4bn+BCJz+SYBKbr3OlasPo2GXinaCm5ZjGwKSqBbnw\nJNQvpJstSIPLThwNEK3IT7qyWtVrGoCDNiYO4H+x3es6P4VqLqh4r/0++vkRSTM4Ov8V4lO1aK+/\na/Wba1G4sbX+xCKKd66y0Rr3rr77pOo7IC0W9booS++rNRLvt64SbPyun/PqLmZi9rwotRAJRA4k\n7TXOcgtq4Ki6pKRKU7oKP5pQXRmGEVr/qGRqcX/IFcGkvR76WQxcFoASm0Yj/3Xu7bvEHJDX02tK\n4cAJxbC+4JkeI2Yc4e6V27wCtFNv8VAnJEAIJxM8w8Y+uK3Wdth00+HnMr/teyh9PAFI23BCDQ8k\nP3/TGEk+2X9AelM3jnJ1cx55xK7Y/PsWkiPKyUozhHYOyR4SaETBIxAtZ3ttpyHm7JPgipayDsI8\n7gYw9SePFZFjYEZhCtfrBAzTmKhxEJ4BYA2Yq5/1Djk3dqr1Y7XDyyIaLjVim9C05XBvKk/3JjmK\no/4wBHIRPWEui8ORGTOUvziQUj+FDTHjthpKosRq4PYd0gugZGbbhdlEj9IDDCDNxkVM9Xyk3ytf\nEqvvgLtYOih3D2Pq4LqFEqHahfAKS8ugstEsKmEWOeBnP50FSppoksT7QdPuZ9PWlAatvnkJv763\n5BXALS8jMNlPIJvelWHd2qCx6OhCgLmUmRPNd7LCMMydqv2c9uA7voFh6jp9JGAvPu53dzjWz83r\ncFeBSw11OeeiKRsJaiHddsq8L7nMEeMcZshhvcS5y26j+2tp1zr6sVBFicGgokYH1CKTQFIpiTib\nXPL5vAVDlvFDdaC5VNkFNCs76Bou5yWCTAwG2DcN88BLMV7QS7M/iGZSbCw8JV01LKDRqeheVsxP\njaLYS5XkKHDpYtsCzcVvCn6u+nDFLOLhz20cYL4vxwmt1pMKikYG15ONmScVDm5/xQBKe7nWsOKz\nSN1w6zj36KQ/C80gFY0GXtFZkG2CqAMt0M3uDfWx3VKuW6ObJNUb3R0TpZri4OwLbrrUpL5UT8yt\nITdov+Beft7qZpxoMu9KLHhncLx4TJH0gBzyTVfAPg4ljeaBsL7cmVfDmZ1PxNBQWN2/Ms5XhA42\nF3BDbS8YdOU8JUxHPgD9tCaXHqmt/co4uhm7Qtmm+DeDE3O6ljX5zbblXhS0345LHi4MFfhCkb81\nJ5XdY0hze86Ye/grd4KM1+hLV49/08mXyM5oQSWFRPGDY5ivO4n9anEwslLWZ2OKFvXtW0ZjW0tT\nRXEjOIOyE8jyr36AQDMI1LnOl15xPMnKxb/u3VpCatxnNlgTk/jzmFAD36PDOdzIPJr58KDGvKFS\nG18BSpcfrx+8cPWzVMM9M9Xk88D3Mxb+hWAv6UC/efp1x3+Hvihd9zDuubo8/FLjegZC0fa3een9\ndOTgEIsRfcfWWWdtQEDcPKuUn7WhoHt0SvpvO5dTcLaAmCPwcROmaH0teqy1XjMnZYp+sKIWZe7h\naa/hTWP68T4UHeFB8IDD9md4MZDlB/L2ac5XlcVY7UmN/GXG3pc7Gbc6uN0CzGUQcYa/v04G+11h\nT8nRzZQJdZlq0lH1U8k7gR7YudvLKtUfLHu1xmyJshSEKbRWUUdGRnwfJUm+3jGXNSoyoDu4eVa0\nmvh2E9+h8tpc6Hdxbe0/dRAb6sSYseeMuPA07z/+SsPa5oJMBS4zBtxgDX7xBkPmnOmMnJAKzWdI\n2/zXRzhP8OaEODsQLJm6++pIgkkHCqOGr6GeXrHTdMP3idL7UslwV4Lad1r2Y9+61kW7fcGSJ1KP\nG39vh0sAfFWWeb9d5TVQgwz+KIoe74xDJPYPPSkVl5kx3YFKk6vty4CYAB+5DVSd9bLaBnJ4/6l1\nJ76KqFbRsqIPDPWm7OcGTLW7JIMmU/Ofpv4nidkb4LPNVbPMfVS+Z32QG6FXVhOpIqgiKe8BfVka\nxk1jg5/fA0RQ/P5VlZhWUzEHywD2+khTh9xwSLldzJ30El7YZ++yRrsgkGW93hRzZdx/r1YMGGS/\nQBmRuRM3FKMkS0svshNKaNg8DySBg+q2X6Ky9IjA3dznU49GnthwMKhx58ThDxQ+szVA0MrLc0o9\n+rEmk+wXvMx1gpwkFLsJocOcBtoyq3atxI33E/X4g0N1mdf0f7XCxqKCPRyQfjfDQQv222kEzPfK\no/j6pJzL/bq2QCtQD62ViO655dAFs1zzuPSuwrN0eWO5sKLw4bi9ekjxE61AGmPACWDjdfaFWJ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dNrJi4eDjTX7egADR1lPi7IHJnaNzULLyzuO3tY20xdNoS1WZ9Cd6zJ3177q62zFD9IqW5Lu\nqwbBMBn9Srz8L15/PmeO818lgnRA+Obqkway5NlS5ktpFQ+pamj3jyYU+gi61IJh4yOrdmG+0YNr\nYFfUfUywA+Vb0DyVlm6VO+PiHnezjyvHEOcYEa8umdPJ9zJG7DIv0F2B2RqLChYKcamD2eAeDTbH\nfV0/YaWwv1GhQ+Ao8z4mbGlH71ah+UI4VMNU5k94werdUcmCZDFEnscd9SO86QRSF05j+ffi1CCi\nv+ySBxYK9APjuLQjNVrNKkjo3sgO/wtZFTimlVD9eKKZO3oJ+8ImII4d0IrCjHSBC0BNLtUvbme9\nmUJX8cvZmqs02dF+ATX/gcguP3DCUJDAUSvbg94oU5zILWF5KshRjRmpg3/63m3Mqua565kXaXW0\nqSB075zLeZeUTxd874xUJdwhzrCH1TkgjtNBULzc+e1zgGneUDlKpF7+GM3E4g2yPDntlKDSV4tq\nZg/J9yLjn1WZ+g3OXJp3EuqNpixt4tWc7g4zpFD+6PkEQHyikmzegOPhSHkmz2B78XcqHnVlVRT6\nu+h8+OajG4S+2zUQ2+y9ii2QR22KHBEnoriSV0FkkgCt9aEB2YKRRKtPBMXtQpeLYxm70Z3gLSUA\nW29k0A/vnaVEOuEOlY/jqfFKbKb1K4q9aVjX+++COWTPhV5kly9w8ujzb69MbaQWfX7p+PvJCGyF\nTwCS/7D3fUAjuzGmkdfDhZccW80v40olYz+LXAUl7tUuByKyy15G+0BKB5YEi6hGFv6lEz3GSGxe\n8/uUmYAPkJ1u1STOydIjaaYXqD83ZO/ZOVEKqhVutfVl2hSHLzYw6/gUFpFcMwZWXX5eOGNLl2/T\nFF4MzK6u9+0KXGdOAvATi0btUYD6QYMM1f5b1kBWZjJcC1//GBYKhkVUuwduwTVT6aj/2wzH5gz7\nQ8qEmTw4zYRBtJXQgOs/voolLCe3EfZEyqm2uQ/r1PchYuV1+d7io3uQFszexWSuf/eYepqWnq/v\nz2Gz7GegP8v46bRpzZKV61eoGO59seLhOTjvp7L/gdDO8xjlrHxYtOpMrNrj06dtbzUUacmPBceR\nd/N3VW3ovm04JbtMLrbwXdgY4PIFgeC5ldjlU2bnibhXKkE2/MjYx8B5HonlmJU3YGnjfnMzuVhi\nsfVEj1uJaRWKiNw0ZAITwD1bMfhDZShTe0WQqn6LrI1/UH5oUhqovpbWw70bz+ENp+D4TDwsZS0s\nSpmlHT0fP8DbRP044UI6dumqUBh6K1XNWgERFQD7UXK8EUV+Idp/rnr1NbNDOlaD0+dhG+p4Id+F\niQe8It9F8OXKRtsV/b7VJ70PE+RuIgrdPemrpm67UkBWnBSKixKvX9kJd4ecWPpr0hHeiPZFRA8U\nD+ACqk7FL3Q4yr05PC//O0H2Vym+cbqKruXPHgWLbH9CI9zSMFo/j+Fq7Aq+EDCG58e6G9X+bmFP\nH/5XNkvZhbeggLK+WQr8H9GQIZLZMQCboRvhX9u+eUuhUUvRU9gwFbtDrSz8K8kJBMzb8blG5UwM\nC2N2y41I2+paR+I2m5hEXkKM9tXl7VclIQIsYF6NoNH3ncc1x4HOPwxgUUR36L2amu/bzBn8MXVJ\nftczkKFdZiYMB5xIcDLovipakJFSH/w2xu6WVXWMOiA5kvgUvu+hbbVi6sHkQNFHYKIAjobH3q+3\nDrc09phW+ROYO+aTcQbKrIjZd71OhsV5rzwZ2JQ7ki7NSzGWrG6x8vZodBDEMCl2MIjkqJ+PHIov\ngo1cRx+oS/5Dae9iXLZjx04CKFNUWUSPyHHrfbNDyOPrdvGCTFr/67j/rGj1J8vVNCxtLm1bEQpc\nSIhvaUaLDRXNEjLHerJ79+3XQHd7IqCcBLemBhPmU+/fiAWJozadBEb+HGZqlMPDNzwkut2l43PB\n24M9Sj7odg/0kwUb+nkDDFoZdwlMwRh+gKg8uvy1/fK1j0sJaMju2Livjx2dKdE1F0GLrtHWI04A\nauTXE9SM5DeEDogTpQeQZPSjlINIteGYpH+oQKh9ZNsv/7z+zVFuvjSsLxXZy0AmwKADhVa+Xh1q\nPOrIzFEtf3FEPdGmEyelpCcZbjgkSf1KggQSt4O4YkgNwswY8tEBLIDAXDQExIjCYv/AIeVtzzzl\n+gKWU0UQjKYMVQCWH9zUlHQz8rQcLCB8EgUlMKDsQVoRJbvQR365CNfAX3W8rMVy4nTztqh7zU8Y\npTMGjwCCnBVie6sRytRY79AmqVpgvBPcuQdAMszg+wqIOS/YOXfWuVWaAHwDpxw6UNFMhWcFKSOH\n05VPD72EbnrzamjHK7JEkayKLgR8VVQaXYvT1jVmwbJ6/f9Gfy8CZaZuJJhKPAbeo8mMHuGWa9HL\nA8hVOZll51JKNbAGr5wPKjPHhfBCcWJqs7VIW00Fms/7xNFGllj/SZtUXSzpO/+2FCnmtjO36lw7\nuBLmHLf7CfjRZYUEgQLNVQA07zta/IkjSnwAojzCOOGiriJKJh6Xxrq7QrpLKKMpwb75V+Bf7UIq\nXCrPo45BCxCLgZ/361L4yE1xbmngU707NlaRF24SuFTe7juhvITEAy3wY6U7A7XsGp1GhBBNaYzx\n63YNFYggmHPw2SyXoCLq+pVuz+tvr1PMqnV3zzb1XvR/5Y4Tsp3bIfi00nNB+tv7WU3mCiKl+KDn\nWulilfdt2qcMkdt7dtmcPpClSu9KfkwSQANc0ehkxDHMf0CT2X361QRvY1BiIqs5wfHnQurPZVvW\nIHViiyTAS3AZ/VOpqQJ9UeATGNz/qAOHlu4l0AAE6xdtAPmQ/ccoAbLOCtCJRlTP4bk+mK/UXsj4\nG5Fs43hzF3JxJ4LR9C2FvUvkNnM4hsoGeWg5/PI3h1hXU7vUZJWEgYReDK1L7mkquUjzkWOBvs/Z\ndZTkag4LuLtNIBkAuT8lMHzT6gfGfl8FX5+8nSILKBx072cjdYwUpvNqyRE2Z/RnolUwJalgqWFb\njwYgWT1LgrAf9zDNpkiBuskNgatldY/dyAyHZ8aoMboKqqPiZMkqJKavv+FSK4leOWqG8/2gaZke\nxNn4gg7BPj+xor4DbD81mH/cZ6YSEZbXxAo5ynx3BpP6mXWX3Q9BVYMbSPDKd5LP/sL+FLO4lhXe\nHGsXA3ZwJficyeFbwqcUF4WXXjftNC8xtQgoYUdMYTmtiO2Wko7wUYf5VzXvf3iAJh6h+ii7bnNk\nQD8LnpXLyWkBAxCxXLS439nKagcl9eGoV9S59YSrP18BCUxHteCTtVutmEwT40IhND3eY4xiK2gJ\n1mJGaWYTHkCq+0qg0+pobyEVhuMvAbp+hax+P5gFIK4xkXaUrJY/rnaXTMMpPlU/ew3xGKHRD6Rn\naz43KtCgy0a0LgYTDuQkkWgfEbeC3Qc3rv1tAYrQoiVSwPN1Ppmyb500ZaLxhfGyslQtV6Cj8IKf\ncHcbEG1SU/vgXR+I/iJitzfGYck2dBP6Hc9bkQiJgCaJyzVJKT2nLPrMra+TZpxLjAf8bfzTaIR7\nyBzAM1+ONLzI4NZwoabqZphQMBeLgkvRZ4iutHq9/65XXwPhJ9rawATImQizNXIWZ/Xc/dBdeYci\ncXlh4cNi9lXr86kv42EtzQO8wiXxvpJNllzagqcYzoDS/2+v9gDA81y/sHczLBSXich8fCL9sHnk\n5HEPy+MWeoxHTXzk4NVKhoDg310u7DNHN/iqdC9jowVF45NxlX5xEGTagsxET2kbWxiMiA+l/seJ\n6hm9WQ5oT/E2yZHcl+/+7WtuGZN65uRALxVa5/5f/aiPVjAc+nbCopYK6mlCZQ1fe6EPe8V6UAwu\nmK6Uxk5h9aHjCoxyl5jtUOUpA3Z2E0IY5HjWDUmo2bW13KxWLnEpTdxtgduawTSy7y1brrIDV9Ou\nthZNeteFd9ZEFakDiqLVxSlFcVeSaMOlBtkUpVqZgEIwE4RUExVbKFs+H5eWDhOO8OZe9cSg9acu\nYYhr68IKC7t9VpDYX5OOgNcj2vxcsNVFwYRGOiq0HeDo2RS36LOmkhoHKBwolhA0gBjZd70RygkT\ne+ujgmuAfYLnTYLZ2nHTE2bGOp0zk1L9xPoBXxIvdp+k5T53k9MUi7R5IRINuNmzr5bC5Qfp1foo\nokZfB1U6tHv1oEOoThzFFHi5MhTQsKEn/ks7GCTg2bAFKYJNuuE7GjA61F1+6Pfp7NPIjUwbK7bN\nTlw/pFPKgsPwRciluwLrUwG/LcAxhFFcg+lpOR6KrBVha2FXaGyrxGufH4oJo5wlwekT/MUb5pmW\nZJgQFHqzjiiXpwW275Qpn8xplJiwEhsVfRYaQIzC5HzBQtBD0Z5xnctY48i77DbgIyL0hIwb/9pW\nQhRC7/N0v7qdT27P0pl+jumTiuNVZta8YTC7G0xouZu+vXxOvE/NO0wbDODHNploJXlfweCV1oyP\nI1N1H5/jXLW0L2eiuCupnTrqSGPbGlL5ABfwLqaZsT5pSY34+77u60VZWbsIexLeWmMfjCRnwqdW\nlazA/KsFkNe9O1U2719btMuPKm+/4TvoYxbpn1POEQsMuuwf9Pu5ujFjLAJq7KtmxM83P+hUfwbr\nG2G0JYCgS4d2fxUgAQiic7SD6J+PBgVi9fHwO7v/rbC/r7wgRKqfvQmlWmB1raUV5e7qFyPgMl91\nDb8DOYHV7Rpd6qEz88xkcQTRT4wIs2PzJ7zBQmRJXb+XbWW88jQEJVpOwGMGWqG33QS7T/CszEl2\n8G/UzSnCH9i0fIkX5bB8hX1jdnr9OkaiXmXu43+ixOyLIbZDRN2aRFEU4bczxAuR5mDXA3WX1DWF\n1LMX3PBCA3DIdqjhKv1+o7MLR+9Hree79XghCuZgtetNgzE+BgpYsP/L+wq4AzZceo2gx/0A3Ad2\nJHE71pWJ/OStHuQFDk7oCr02NKijAhZT/5I73DLzWpVMrpPwG0706DOFl5+bko+2xhL+vKkL4s9G\n43sC21ZYXx40qplG+nB4fhtMI7Lx12xMc6QgJO/DJGJbPIp5sPUk5yZyzFSb6vxhQcGKzF0jRKk2\nblj8QeOpzwmj2vNpKnM80a3UxpPiqfN7qiNdQV/oGE4utr7yunmZfyhLjo/uE0vfzSjmvB87f5Xq\nlSz9CuGzxhmVUGtT60TctfVAGIWcvXELEXV9HRvbEvzJ/XxlarWtZBkumvhDxv+H3/qxTBYBB3VL\nEE7GwzXzsRqrfwK5sZNZBrnzd+XIfp91Cnc96mK+7oU/+LV+A6NtqwEEdxNXA9EK6BlqTOYrfmNU\nUAyIzodRgP4dyJKUwF0WnCNbwi+WgWfKxeD6J6U5fRGoUSwKaIxOmNvBMgeSQ2eA+671h0YMe4NP\nqggDfVx9cXGcpytVWFntnxs6aQPg4qSpVOZkJHP2/oUPTaeW/+Hvyja+m3VTiajRHS+lfWABSwkq\n7pRAbCjzIbKeOM6sY4W63453Ewo296f3xh5ZY65u0scQgUyXtB48n3211e4tIIKNN/AwXo08/bhL\n8gThWAG9WhH2kzkFX3M7AZm47XgemDZnxChGhAXlif7chETEzzJtM8Ytn6zgg/ph9GV3i/Z6aun0\nmrCG0LMtrg4CJo+4mHmQUG27Gtd/PIm9eqWdt4ywk02K4gGJ67YvXnm+EhJHkApngBbKhp+I52ee\nZtUw0Li4xW6bs49i2dOUAjx86jsKeU7uJiWkirUvQ+aK37MPYTPcfME8nYmJNlOwZWzbVKfm00HL\nk0qmK6iDSmL/DSdx9VnPtGsNRFDgI1hAkSsqoGO2mCxxCyfAc48cWKxErLRoVWoO8VSl834ogKht\noeVK58ezIAHphOWtGVwz6GZwBiIy//1koxIMb3oR/qvXYhyucGPrvWOoGAHfpFsQPqwrb+rEKn03\nScU9PlrRZFhZOONC3GwM8Pssp2AOJT6RI+RXmNsMX2QRDtwDnC4vmHwen9MePiN3F/jppJhwA8RW\n/Rm1C2FX8ODUUj/mJU2oyh2u1HV75vH1uvUNFzDmB27k9IBiPpU0jjvuSXAJRPkzve4rYPV9xTL8\nfvi3Vtkjj6ahvzGVcsAVgAX4iWHLuRCHlAmMaXvPjURqSCU6XRgDTx1ia0CoytuL3y2O+KSUqBEK\nUqmtax5Wn+VzUtROS462rJdrp3YARn//1bxpXyg/j1/juWv0yJPQgUYcU3d3JuYIp8Q8jjoVodhn\nP1QPd79DXNB/Pwd711DNxOb0sk8yEPXHXc1Xcnnuz7a1WrYqeU+Ww/PpVga/3biOfdSOi339aWgB\nfndekDI0qMl0s9pWT+9CPjkyL0nbVWARb/uVgNpjHNmro4Nbj0HpFXKX9fwsBDeBmD2lgBrmbKj6\nbdRKGMZutn+k3xVU2uNfdFPeVpbC5lod/2xvC8Ful+0xSpTdyyvsUgfPwPgPtL/SOrLFT0nutxzZ\nkz8gjdMQ4dFDPg5YoKfi+ICV/qlSloXDse3ooI5N1ZuDqcKdcXjzm46vsfHbCZCzGxIgo+W3tT29\nAKYT0/xSqJTbX1kkMmCMOiQqCfGf29k8J1SaP1lrOC5l1AA8nrKBjm3OvciG8hf+5r02GNnwBp8Z\nZDCjx/Atsr+9LAHvecc6HiHJPuNCINcP5TLiSfF0jgcdsQm3869+RWCQUX5yLZWiVCpuQxFzPLPm\n9mjy+MRdZRDrfpkdPkHapHE3kPmPVWQXDTnhLYOgE4vdcljB4tWrpeCNm+JgRQ03G+v+wSPN9TYb\nrwX2GUhJoR/ax47EWPbYauv7LNZ2bJGfOb9s/o8KYw68eXkgj+FDljZzzP0dKUQqYjNgIw2TGCxY\ngcJ7cxv8BTZJ/JTxk7ZL577zd1AInIq0wuKBFqp2t/9tMsxSXegD0PLlzMB2fDYVGmncDtT4PzlE\nozcuiUJRipjY6DoesJlfHKyxNqJNNxjDOW3SjMiKtI8JtSQNH0BSyrRIyGNGXzX/uQArTH65IiPY\nkbNFkh5LMdN5Wn42QqnWV583GGVqmNlGzHkdprd4C+xMN4kkWbjaJVSDHQGeVbUdqT7K6j1Sa/gY\nKGZmys+BhBpakUrOXa2ouadrpwLjtjwhGHVq+zFPcxNyMBIuT43rLb116BwmRtaHmmQRa1Y9fgPg\n7LWLlkhNqEKOAPWFDQUuPpJqYr94vCP0A9arjsxYSzLkGGUsYf0r35nsW4eRMZjFyywzOyktfHup\nchvurg5EDDibgz8QtOdlGNqjerLNTRx+XGEqla27/jSiw8H1kgGrPDAeYsfAVs5y2+3WJNAsw9hT\nZzFM8t/CCIgXX2pj4yrJxSskmH6QjRspvr+VxbpVgFbgSKw/l1lDbmJDDPgX89Wmo0Bog+C8R21R\nqseSnoWZu17XsTWPMkOBeLmus/g7Aw7CMHMIYuQ4A4cJu9j0Gc6RVLvud7iLe2FMoSn0HdrObS/v\nRUAkfW832KW7aEdntoOLUdjtzOQ5QKD8YnNfz4LAzm3OhInLz/DshGnUdxR3EAL159zxjVlLZKGK\nElxu0aK5Jr8coyzWWtm+4HX92C+Qb5vXEXsmqRgIZoQPp5RpRukTUGg4zq4uAWspaTKNzxxlIEYI\npM4B/sIKkQ7sHptRAgZ/K8sDCJolRdeda8ln2ywDEJkz2nu1Kw0jm/+XghX8j1SIOG0qWiz6/Ybc\nzdbJO4Plp4J+X39ZxONVdiGg1EbaJ8UYFl+7inGY0c+VUCclN6lhgWULVKgp0ZbB3yLpKvdDBKgD\n7ZPXHoHemwi+R5aEY7fxs2S9MQcCvo7n2z8hTeHWb+DA5zq8/x/8eWhaI77HZ3DTvtkC2mVsiImR\nwjAkfk0z5JHXQ10Dqdwey7NVkAHLKwgXQG7SZFqrdI2PQV9HHw8bn3m6P+f7/EAy4MkYv8OHlwCg\nAz44PcpP9zXgPo5kl094cZivvFVVOC9A14EHv5xaRJSbue3ckHwAaVgXMonasMWqzQXHHWB4pM/2\nzq4cgM+X11VuzcRfROlRKdmu9umzZJq3sAFpM5xM4oyWtBLLHCdk+kmOffwThUPQcFT6Cp9se2Wv\nBQ3DldAMEtZ/j40qXaVivpsdHisEwN5FZQdxBMQqzZaP4UxldJ4xWKA3n61Muv4KIfoUKajddLuS\nZ5bqFL3zAkvxOf3JPUroU3wJfi2PGRcFmrNSWgp7VEHsWiBw//1PEbEYYXNzlCG322IbiY2RL6iR\nA7vI7/83fM4uY75AhDlBhuQHcEG1mL/9OfaC8TOhJiCwn2ByChDEFZhloTgtP/ZWa3aVGajOfbb2\n9X2Q7O2fzO9lBbF49OOnRLGTGH3jggbIELpZYfUF2wHdMdRJa3vJce8DTqVv771jzqUjE+fnwOv1\n269F8crvbc0cn13uXMkAyw1nN0wpG1H9l1P6jnVhrYq74DkOPEjkiK4unQKlx0aZI/YIHcAfszVM\nY0VIC2djUXZXrZlW3Y4bUmtoO4kMwI/iMgrYuA2cnHULO79HXnYXhrsdAAv9xYSiCAVQv1w7trDt\nXOmMVGvsc7eY3BpFegOKEqPqYIb5cwa75vy47XFo1zUtjPohgZ/g+MCSwqRz13l5N9vQlFSUL857\nRIPEeotyNTAsdh3vFX/jYfsonxch698ZbFLAAZ2uagiQ4oDuMeZpgeUnzcsT64lJa8GhO9cVASuE\ny0F6GpshZvVOe791qrdIB+EJ+FSESXq7IBlZ7u8nKzT3vwJbAFCmo2FIPqzBzR6n3aAQnYVuJIKN\n5Sg85UzY90qoBTGnu7wz2Z8lnZ8kGtpDSDOGhDFHBOGL1+xytbC3IeWxpkSUppE4dMh3UBtUpQpc\nrznsPHtwQusNoU5UHNl+ro08V1FXkHUs3BGo7cjO1E5mEsXECd0Yh+x/PAAC2sove1R0oZM6sGqv\n+cCCB7Vc9Az/Ei+rKcaQ7/cztvAERpeXYbhXrHeIwzJOeo6SllZ6eWAU0t9Umj75FZpWqfPlVngg\nxspwNQyDQ+pzoelgqX6CDTSoJJVBX6ypQoRpbQK004AUM2ODfMQeGrXJroVW7Dn/UvFzPHrPglZC\nHQmAG7G0MAv1OywENidA/tXzqhJYQ8VCtT2y/tKc3sh+T2PofUFs/sXPkTtUY9ALHm3DeX3H4CQP\n3Rb+ibBMospJV/C4wY8lXWgxxVCfBnLgO5r4RdQZ9iG+D+jNnqOzIsmOWgzNE+mbRYtKgPjmCs5w\nkpDjZCTmayxeTJBGAHsyCqnJxUhm0lia66LtCTkMcuB6j6i35CZ97kDpwIOi7AutER7n7lPH++Gn\nm3D321MZdm8kTkBVzTPhrnCA4JFEy+muDff1jfJIYuipA9VLqGCgficM2pPxl5PAt10RYCFRIczP\nImS8vQ89vm3/mEJLxVdbhKLSSIOUe0SyhbZ2qI77n7Pds4qv2SY5jt+R+iIhRASw7/v/kNYUxdiU\nd2whz+3cp4AylBxKxxEOrtr+SEwv9Onfj3IHTQtGHr7vZ7YgYe0YTvUebilhEDptwX6Bk4wHVH18\nELtY4IKlOENXltTlk4Fmfj2DWrqzrYwE27mXmVsBkrge382vltAomA/zHyDmmVAR9fSNI8kJqPv9\nBf0kt+ri0IU1ZZg9Woj0aa6yJritF6/2sxQwnu7hDud4nxN6agLEuHlhB37LbdL4HSPtvvRyQBEA\neetF5eYD5jUT+9nAbGZ+gGiyc7is+4wBcp5djCDST+xp/aqAUweRDNoGPk9chJw7tOrYGAsiLigf\nXAdVxBdEHR7w35WoJZOKR/ohU4uVHNlLcsqfPX8Dvr6UBD0lPGmwIq2vqjVCbdb7t6yILuEq9Ufm\nMGfARBYUMcz0CLCaO6fMddLXYb3+7JNc6BfgeNNs4c+og1l/7cS5kyAZ7etGCS4NmxOe8lgxHUWw\n8IO0tvTl6ukkA/6HFwXkZ0AbJcHifOFomjCv7anv2hOfuO9oEeFpp3WDj12n2Td+ZsWkf1AmoukR\neHaSxklqdCPcEI+UKHxQLNyr8pAOYswoRRGZbIqYW/ta17ZpL5ObFe7L0dnkTerzaK6+7QuQcXN4\nPEGg/nZtybL619pmNPfMj7PZjzIQeW/8N19FXPNLpPAoVClkPHG4Jw2tWKC4w+NgfUpUZJV5/oLG\nE0Qzbcl2mu8ISb5O1UcRkK4QStBrSta2QNvkxAkqOMW/jbQTViSnlFGnQPa3JBnvZ5xx8kSZDoL4\nzRzW+5sj6EamucW1FGMHEcaRnfoI9HYpQXf/8IyKuWe1UyYuhDL/2GkuQjpJTaIy21kze3sprXk6\nwpt1QJZ0Edtv5/8ks9db7hw2IbtXZBpSZpvE9ugD0lLiq5rPGhEahktiI7dZ3qbKT0bTXgXhrq9q\nSUMqwZoXaG/OkXvzEGInn5k3AP8V71EZfoxn5fn/UOuomkWmITLVKtg7tWd1LyrVbmJiZZFDZ7qI\np/XN53yVoQSXwoT4AshECVSbN/qX2+Qwu9Li7N8ET6x0aZ5qsJoEZr2yW2YVjQfbzCQy2cyj06/R\nMr7wwHXXa9rwr8iPvJZqmheEb7Y0AT8RjFFkICCE3TaRpLpc5GXvlm30aMqecTG2WVjbcnNiR+4F\n/C2wlDxRVm2bYvBdaKYVpicEjIE4yUAuMM8LkISEeRh569nRfVlQvmBwU9/WwXT3Ti/9jnbnlYvr\n+Ahjwb2/qNZd5qdcZoIm53BHEPFH6Vq1H/Gh/kzAJKdFN/PoXZKFLX463Mi70+9jrOYA1OiCHndK\no3zf7txPRp00vR2xJpj4unJbmpT4ffdThfuCSmKXRBTTZrgzY9yS6ftKCkee51Ztt+U6nPNlUpAN\nllyRhHkTPq060dxFuYOAoh9z58j+mdFB8eni0jqIqTlySXsVysNMX8AEngW2l89h7oV7E6W3Cthj\nLMSiKmG2/uMLyVm+c2btxBH1BiQRhQ1Rv9q39KwMbuGrzU1o1P3FtPG5HSsyJGmJtp6rDaNiiwxb\npFvHTWhTiDlj/0drNkTzFhG1JwaNzt0kOuewsLPdSir3uklbO6ecYaPK8Z4jgXerghf6lEyknZLS\nAYkKYA3rNh+45AAi1hRUOi3cp/pEHV/rSRmAPuczKvBZi/XmAqj6LGPxNcENDgMujqSw+7+uJJ0U\nQ9Yc5CELdrqvZ7mpxDFUx8QeiSww/sXE6aExkV68LMQHbrd4YaV96mjBcBLcyVqzRhLPDyuNzEFw\np4qk0TDXF1ACMNds2+Dt/Uuq9fxkmO5/q/GV1TyqO2RLP/z8GSXYvfZqOpJDtkFNGW4YcUU9OabN\nad+Q/9AomAx6BhJN0djqPBEafbnO0Jt3UVlPRE+gFekn0MvN+Tvw8vtBYQDL9VjaXZ350tmEqM5n\n8r4nQDI2NKf2AqFC1h6yx1D80OPYltLCRgU0y2GMZwp5ffMxpciUQYx48wteQkIj1vSGxelD7w3D\nFp/RHW7VRDRDzGez/pb0ZUlkmUzN7U1Eo3XRciUGIqIIUNn/ONyb3yvpQQA8wPiq1mwZIKZxyItD\n0U/CJNypm/F4npGM0VnY7fDcgFt7D29oorNPtCf2GAGAwDgKQmSNPmHVa8jJsYiuDcpw9URnTY9V\ntlH1HgWU+Tvr/riLXwOUqSufAPwmdP3p7nNAJVhufvf+5dLe5d3hxHtLxI6kjQwypWq3UBSwzQs2\nLO1+IJ1O4ds3iOra8+5J6u94UI1YsUbGYPOJwvzJ6SjHcLu8x6cWFhaUV2G6xs1fpi+7XO3lbm0y\n5W27tdy11ymOBHal9SdMg+tCFS62wxb2pPE8ZYDSXcwFxnU2QoKifLjZMYzKxXJFwweri6WL3VCt\niqEVBjol27uPCleezJI93TjZrRwL5CETU1b0nUl7hB5tni/KeEvIgKJ04f3KhE3w8g2abb6a0kXC\nuIlTQIIPxUM1ALbGJ+4f5qlVpvJ7nwT2bZ394BwTsH2S8eP241Bq2eVSuOi3Ab6tapNU4YNxIpBL\nDzcIQ/Jq3ToPenfueZrnGr3xKjeXYHJFhki5fzQIs0UkV8rvZP5qWUrko6dILN62pdzGOFJ+y4W0\nXfyMB2uKuXJv6Utx9fFydtYUyEj8Zrn90goiFM+NQU0iFdZ4QEvl1Ts+dv8/rrQH3eJTZqvI/yE3\n12TofYflRc2uRuGlx0r+Q6/3+33yPzrfr6U/aRx1N2E+vcv/L2kGVucq16ibQzJGIZqfHdBints2\nnB/xvJob2flgExd0M73QfeiBCRHzrKKyzj9Xy/YqcQjnpVZHJ0z8Khrxyx3uHHEjnFnVbod7bFEU\nc9ZV++TR2/rvd4/6tgAzf4slQhJqLWCG50xvRj+FPZPCbvxvtFnpArHuGPLhQP58M+qu8J1r6I7s\nag7qtFsFsPbykd8JxRwlB3lt4K7cNC1bKu6iSfT4vsU6XRY/ascVBykqvZDfh/zsnUvrZgmKCCBr\np5h8nDwS5zWHjQ5jShlMEqUr1g8tXsoh0g0RCOAYfHMpevkuPO3hdOrwj6+xJKkkfvuUKAJ15Siq\nsfGhPHOKEye2SzkPITZCk6Epg3vCrRweshnptUBNLAAEgZFGjAcsUQpnC+ckfUoseyAmdGwL2gw7\njQTTYXUrHvMyk+sKl6YTqd1bkaKW4kkUvaZ/rhWQefXwi759KpCKAStFGqfBO0P0buiDMWT3NQZW\nSLbgrltCu/0xvuYiq4t2Dq4pEfgQhWDCTXNAaavjbEt3oNWVDk2/oLH9DhhaEGJ7cp8+e6N6+QOS\n0bspQnURwauJmMJ8yUNYyf9ta8c40Np3aJDOareux0hbEISmQSc4Ibt8NqJFXqF7N2NWS5A+gSsi\norAZxPtzThjQ23JkrwJ0ZPNmbmcrPw1mfTOehFBdqoWPx/V1eDm5NNyriTd6LoYLbfHomQ+8WALR\nvZEOzoN+xewA5Uyk1S3+MzmEKZ3CVhK3GHoxuIMA7jpKebjYySo4sCnlQMb6qqT/bEYEyIsnWvcy\n82f7UbQc9TnIkHDhaRJw2m92dRvylHLCW54hHu6QLRMVKvHYeJNzEdtEit7GocKKSTkPn4BPI/Yi\nDB78TGR7uT3b85v7IOyxHBzEe9as39kKuQRced8pqdr9rbXMTxKG9fjurivrGePnZUbfZnOrpVRL\nkKCb+IpI64a/68XG/DR/SKALmfHrlb33vpCSd0LPcJ9gJUYGctaIA7XC5VtBzhDIcR9PBU+tTm9W\nau9psrwiInRr05n+P2ka3juxmJUvRjj+VYdfHsFkpNtAyitihSAmtBzaFQ/GCY9qd7kXWuxltG51\nrFrtLeXwN+9Dnr+9ExBWRWkyD107BNXg7Q127EZxGeVB9VR/X1KLOqjRClcK7lJrRpdva5kHRJ54\nKhRZV1sepRiHDRVCJIhJ9U6FWd/rQgWMmmcGawdgO1OX8kC5EdLJpXpkSeH5Yjqv3zzjASPu7K1e\nwWPiAxuwVgjdGKJIbluw6G5pJQ2uXDR5Xa5xsfAdroYQ0IRUvAkeOY3tND4Lkw/XVvx8KeFAWTNp\nXenmRJ5/iBqiIfM/c/rIofFpZCA5QqrNEMfQtDBkAJrxtq1sol50O0rih87WaJ+mdtwngYU7HOXS\nRQ+QLH1ciUq6EcJ73P+0hPAOokjzgjhqaori7+/iLyN1C/AWI1S59VXo4s8Lrl4s1/kVBR4QHr5V\nNiVmq4cDDDzuL1SP1j/K7bkn0GyS/RY8DPXrsujE06j3tTvjvnMGY/HaviTzAHivPGFzfXWofpT/\nFOBIBBwbn4pUVoeGWQJXIoNTcyeIxLLEOiJ2zYAUEwEdsOn+f8+dtBaERYpwAhYE4NLbwH6ple55\nRwSPKczzLDMieRAXxc+iQjGV4j/5oqHAmcwgXN7zvk/aGpMYPyA2berXcmFw0LSY1sepZIKYaWuj\noYF9Y7ElShrguXYyk1lAuvOX8VPhIpudfS7dnJHZRceapQi/Xl8DlsQg5fPaQo7gvh+5Hxbe5/dt\nsNmxiidiIGAyoTi091EqBHlEwjR9IhtjBB9469BfzhnT6ccPVCINNxJpiUBJiEOtublFQ/M7KWIP\nfC2d0pCxn06H9bmLT9zfhWsyldmMeBU9AEB2Ck/kn+c75sFlRezkk8wmqlFM2NcAvQcSf8GR2hO/\ncFxi9ZzXFOJCgdfy/9zY0YFHKKnurAgHZlgOdBl8inDgvgC2RlDXnzIuz23kNA9RxHQ2/FXl0z61\nnYwe+SCMNDzoPcUZcUBhPZonJ+3irIWLUdjkbb7qTGymgjf5KR/XMuWA/VX/8uRtjWSOc95Nbt8a\nCaci43oMh2lwO79FoeUffZYmZV3fldqnDs1ze/aOGywPwqcT1jntje94qn3lvQoQ/BJ/k93rEy+2\n5x0vRK6gNlXO4KtnS9D9Ypwk0VbvxdQ8n1IGdI8B9XTjg6ENjqtUbomhDPSFQCjwicweZXrRfUOD\nh+cPfCp22/DQgxGK2DHVgSjAS7NgTpMzbMt2/jQdh7ewO5Ek07NBPGfI47RJujdhRIoS6lFB2L5i\nM2Ly8kjyyAQreVG7AMc6P3r5WOlcr9TujTmvWGh8TOwQ1LDhVNVKJ+JGG1AzuIFYfDJBzzcZd1A5\nteF80j/Z0cUfa1hdkR4d4OTqS5QotD9WNh4QCndwopopxD6G1h9s/s5UVf0blaIfjDBU0/Nx9WVK\n6t/6Ruyhta8hQ9IxRw2VqEEY6Evx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protect end_protected\n", "num_lines": 530}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_0 (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [63 : 0] probe1;\ninput [0 : 0] probe2;\ninput [0 : 0] probe3;\ninput [63 : 0] probe4;\ninput [0 : 0] probe5;\n\n\nendmodule\n", "num_lines": 73}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"ila_0,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_0,ila,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=6.2,x_ipLanguage=VERILOG,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=virtexu,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=6,C_DATA_DEPTH=1024,C_MAJOR_VERSION=2020,C_MINOR_VERSION=2,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=6,C_CORE_MINOR_VER=2,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=2,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=0,C_EN_DDR_ILA=0,C_DDR_CLK_GEN=0,C_CLK_FREQ=200,C_CLK_PERIOD=5.0,C_CLKFBOUT_MULT_F=10,C_DIVCLK_DIVIDE=3,C_CLKOUT0_DIVIDE_F=10,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=4,ALL_PROBE_SAME_MU=false,ALL_PROBE_SAME_MU_CNT=1,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_ILA_CLK_FREQ=2000000,C_PROBE0_WIDTH=1,C_PROBE1_WIDTH=64,C_PROBE2_WIDTH=1,C_PROBE3_WIDTH=1,C_PROBE4_WIDTH=64,C_PROBE5_WIDTH=1,C_PROBE6_WIDTH=1,C_PROBE7_WIDTH=1,C_PROBE8_WIDTH=1,C_PROBE9_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE12_WIDTH=1,C_PROBE13_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE18_WIDTH=1,C_PROBE19_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE22_WIDTH=1,C_PROBE23_WIDTH=1,C_PROBE24_WIDTH=1,C_PROBE25_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE52_WIDTH=1,C_PROBE53_WIDTH=1,\\\nC_PROBE54_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE70_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE80_WIDTH=1,C_PROBE81_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE108_WIDTH=1,C_PROBE109_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE131_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE134_WIDTH=1,C_PROBE135_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE153_WIDTH=1,\\\nC_PROBE154_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE156_WIDTH=1,C_PROBE157_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE160_WIDTH=1,C_PROBE161_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE184_WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE187_WIDTH=1,C_PROBE188_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE210_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE213_WIDTH=1,C_PROBE214_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE226_WIDTH=1,C_PR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BE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1,C_PROBE0_TYPE=0,C_PROBE1_TYPE=0,C_PROBE2_TYPE=0,C_PROBE3_TYPE=0,C_PROBE4_TYPE=0,C_PROBE5_TYPE=0,\\\nC_PROBE6_TYPE=1,C_PROBE7_TYPE=1,C_PROBE8_TYPE=1,C_PROBE9_TYPE=1,C_PROBE10_TYPE=1,C_PROBE11_TYPE=1,C_PROBE12_TYPE=1,C_PROBE13_TYPE=1,C_PROBE14_TYPE=1,C_PROBE15_TYPE=1,C_PROBE16_TYPE=1,C_PROBE17_TYPE=1,C_PROBE18_TYPE=1,C_PROBE19_TYPE=1,C_PROBE20_TYPE=1,C_PROBE21_TYPE=1,C_PROBE22_TYPE=1,C_PROBE23_TYPE=1,C_PROBE24_TYPE=1,C_PROBE25_TYPE=1,C_PROBE26_TYPE=1,C_PROBE27_TYPE=1,C_PROBE28_TYPE=1,C_PROBE29_TYPE=1,C_PROBE30_TYPE=1,C_PROBE31_TYPE=1,C_PROBE32_TYPE=1,C_PROBE33_TYPE=1,C_PROBE34_TYPE=1,C_PROBE35_TYPE=1,C_PROBE36_TYPE=1,C_PROBE37_TYPE=1,C_PROBE38_TYPE=1,C_PROBE39_TYPE=1,C_PROBE40_TYPE=1,C_PROBE41_TYPE=1,C_PROBE42_TYPE=1,C_PROBE43_TYPE=1,C_PROBE44_TYPE=1,C_PROBE45_TYPE=1,C_PROBE46_TYPE=1,C_PROBE47_TYPE=1,C_PROBE48_TYPE=1,C_PROBE49_TYPE=1,C_PROBE50_TYPE=1,C_PROBE51_TYPE=1,C_PROBE52_TYPE=1,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,\\\nC_PROBE106_TYPE=1,C_PROBE107_TYPE=1,C_PROBE108_TYPE=1,C_PROBE109_TYPE=1,C_PROBE110_TYPE=1,C_PROBE111_TYPE=1,C_PROBE112_TYPE=1,C_PROBE113_TYPE=1,C_PROBE114_TYPE=1,C_PROBE115_TYPE=1,C_PROBE116_TYPE=1,C_PROBE117_TYPE=1,C_PROBE118_TYPE=1,C_PROBE119_TYPE=1,C_PROBE120_TYPE=1,C_PROBE121_TYPE=1,C_PROBE122_TYPE=1,C_PROBE123_TYPE=1,C_PROBE124_TYPE=1,C_PROBE125_TYPE=1,C_PROBE126_TYPE=1,C_PROBE127_TYPE=1,C_PROBE128_TYPE=1,C_PROBE129_TYPE=1,C_PROBE130_TYPE=1,C_PROBE131_TYPE=1,C_PROBE132_TYPE=1,C_PROBE133_TYPE=1,C_PROBE134_TYPE=1,C_PROBE135_TYPE=1,C_PROBE136_TYPE=1,C_PROBE137_TYPE=1,C_PROBE138_TYPE=1,C_PROBE139_TYPE=1,C_PROBE140_TYPE=1,C_PROBE141_TYPE=1,C_PROBE142_TYPE=1,C_PROBE143_TYPE=1,C_PROBE144_TYPE=1,C_PROBE145_TYPE=1,C_PROBE146_TYPE=1,C_PROBE147_TYPE=1,C_PROBE148_TYPE=1,C_PROBE149_TYPE=1,C_PROBE150_TYPE=1,C_PROBE151_TYPE=1,C_PROBE152_TYPE=1,C_PROBE153_TYPE=1,C_PROBE154_TYPE=1,C_PROBE155_TYPE=1,C_PROBE156_TYPE=1,C_PROBE157_TYPE=1,C_PROBE158_TYPE=1,C_PROBE159_TYPE=1,C_PROBE160_TYPE=1,C_PROBE161_TYPE=1,C_PROBE162_TYPE=1,C_PROBE163_TYPE=1,C_PROBE164_TYPE=1,C_PROBE165_TYPE=1,C_PROBE166_TYPE=1,C_PROBE167_TYPE=1,C_PROBE168_TYPE=1,C_PROBE169_TYPE=1,C_PROBE170_TYPE=1,C_PROBE171_TYPE=1,C_PROBE172_TYPE=1,C_PROBE173_TYPE=1,C_PROBE174_TYPE=1,C_PROBE175_TYPE=1,C_PROBE176_TYPE=1,C_PROBE177_TYPE=1,C_PROBE178_TYPE=1,C_PROBE179_TYPE=1,C_PROBE180_TYPE=1,C_PROBE181_TYPE=1,C_PROBE182_TYPE=1,C_PROBE183_TYPE=1,C_PROBE184_TYPE=1,C_PROBE185_TYPE=1,C_PROBE186_TYPE=1,C_PROBE187_TYPE=1,C_PROBE188_TYPE=1,C_PROBE189_TYPE=1,C_PROBE190_TYPE=1,C_PROBE191_TYPE=1,C_PROBE192_TYPE=1,C_PROBE193_TYPE=1,C_PROBE194_TYPE=1,C_PROBE195_TYPE=1,C_PROBE196_TYPE=1,C_PROBE197_TYPE=1,C_PROBE198_TYPE=1,C_PROBE199_TYPE=1,C_PROBE200_TYPE=1,C_PROBE201_TYPE=1,C_PROBE202_TYPE=1,C_PROBE203_TYPE=1,C_PROBE204_TYPE=1,C_PROBE205_TYPE=1,\\\nC_PROBE206_TYPE=1,C_PROBE207_TYPE=1,C_PROBE208_TYPE=1,C_PROBE209_TYPE=1,C_PROBE210_TYPE=1,C_PROBE211_TYPE=1,C_PROBE212_TYPE=1,C_PROBE213_TYPE=1,C_PROBE214_TYPE=1,C_PROBE215_TYPE=1,C_PROBE216_TYPE=1,C_PROBE217_TYPE=1,C_PROBE218_TYPE=1,C_PROBE219_TYPE=1,C_PROBE220_TYPE=1,C_PROBE221_TYPE=1,C_PROBE222_TYPE=1,C_PROBE223_TYPE=1,C_PROBE224_TYPE=1,C_PROBE225_TYPE=1,C_PROBE226_TYPE=1,C_PROBE227_TYPE=1,C_PROBE228_TYPE=1,C_PROBE229_TYPE=1,C_PROBE230_TYPE=1,C_PROBE231_TYPE=1,C_PROBE232_TYPE=1,C_PROBE233_TYPE=1,C_PROBE234_TYPE=1,C_PROBE235_TYPE=1,C_PROBE236_TYPE=1,C_PROBE237_TYPE=1,C_PROBE238_TYPE=1,C_PROBE239_TYPE=1,C_PROBE240_TYPE=1,C_PROBE241_TYPE=1,C_PROBE242_TYPE=1,C_PROBE243_TYPE=1,C_PROBE244_TYPE=1,C_PROBE245_TYPE=1,C_PROBE246_TYPE=1,C_PROBE247_TYPE=1,C_PRO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525_TYPE=1,C_PROBE526_TYPE=1,C_PROBE527_TYPE=1,C_PROBE528_TYPE=1,C_PROBE529_TYPE=1,C_PROBE530_TYPE=1,C_PROBE531_TYPE=1,C_PROBE532_TYPE=1,C_PROBE533_TYPE=1,C_PROBE534_TYPE=1,C_PROBE535_TYPE=1,C_PROBE536_TYPE=1,C_PROBE537_TYPE=1,C_PROBE538_TYPE=1,C_PROBE539_TYPE=1,C_PROBE540_TYPE=1,C_PROBE541_TYPE=1,C_PROBE542_TYPE=1,C_PROBE543_TYPE=1,C_PROBE544_TYPE=1,C_PROBE545_TYPE=1,C_PROBE546_TYPE=1,C_PROBE547_TYPE=1,C_PROBE548_TYPE=1,C_PROBE549_TYPE=1,C_PROBE550_TYPE=1,C_PROBE551_TYPE=1,C_PROBE552_TYPE=1,C_PROBE553_TYPE=1,C_PROBE554_TYPE=1,C_PROBE555_TYPE=1,C_PROBE556_TYPE=1,C_PROBE557_TYPE=1,C_PROBE558_TYPE=1,C_PROBE559_TYPE=1,C_PROBE560_TYPE=1,C_PROBE561_TYPE=1,C_PROBE562_TYPE=1,C_PROBE563_TYPE=1,C_PROBE564_TYPE=1,C_PROBE565_TYPE=1,C_PROBE566_TYPE=1,C_PROBE567_TYPE=1,C_PROBE568_TYPE=1,C_PROBE569_TYPE=1,C_PROBE570_TYPE=1,C_PROBE571_TYPE=1,C_PROBE572_TYPE=1,C_PROBE573_TYPE=1,C_PROBE574_TYPE=1,C_PROBE575_TYPE=1,C_PROBE576_TYPE=1,C_PROBE577_TYPE=1,C_PROBE578_TYPE=1,C_PROBE579_TYPE=1,C_PROBE580_TYPE=1,C_PROBE581_TYPE=1,C_PROBE582_TYPE=1,C_PROBE583_TYPE=1,C_PROBE584_TYPE=1,C_PROBE585_TYPE=1,C_PROBE586_TYPE=1,C_PROBE587_TYPE=1,C_PROBE588_TYPE=1,C_PROBE589_TYPE=1,C_PROBE590_TYPE=1,C_PROBE591_TYPE=1,C_PROBE592_TYPE=1,C_PROBE593_TYPE=1,C_PROBE594_TYPE=1,C_PROBE595_TYPE=1,C_PROBE596_TYPE=1,C_PROBE597_TYPE=1,C_PROBE598_TYPE=1,C_PROBE599_TYPE=1,C_PROBE600_TYPE=1,C_PROBE601_TYPE=1,C_PROBE602_TYPE=1,C_PROBE603_TYPE=1,C_PROBE604_TYPE=1,C_PROBE605_TYPE=1,\\\nC_PROBE606_TYPE=1,C_PROBE607_TYPE=1,C_PROBE608_TYPE=1,C_PROBE609_TYPE=1,C_PROBE610_TYPE=1,C_PROBE611_TYPE=1,C_PROBE612_TYPE=1,C_PROBE613_TYPE=1,C_PROBE614_TYPE=1,C_PROBE615_TYPE=1,C_PROBE616_TYPE=1,C_PROBE617_TYPE=1,C_PROBE618_TYPE=1,C_PROBE619_TYPE=1,C_PROBE620_TYPE=1,C_PROBE621_TYPE=1,C_PROBE622_TYPE=1,C_PROBE623_TYPE=1,C_PROBE624_TYPE=1,C_PROBE625_TYPE=1,C_PROBE626_TYPE=1,C_PROBE627_TYPE=1,C_PROBE628_TYPE=1,C_PROBE629_TYPE=1,C_PROBE630_TYPE=1,C_PROBE631_TYPE=1,C_PROBE632_TYPE=1,C_PROBE633_TYPE=1,C_PROBE634_TYPE=1,C_PROBE635_TYPE=1,C_PROBE636_TYPE=1,C_PROBE637_TYPE=1,C_PROBE638_TYPE=1,C_PROBE639_TYPE=1,C_PROBE640_TYPE=1,C_PROBE641_TYPE=1,C_PROBE642_TYPE=1,C_PROBE643_TYPE=1,C_PROBE644_TYPE=1,C_PROBE645_TYPE=1,C_PROBE646_TYPE=1,C_PROBE647_TYPE=1,C_PROBE648_TYPE=1,C_PROBE649_TYPE=1,C_PROBE650_TYPE=1,C_PROBE651_TYPE=1,C_PROBE652_TYPE=1,C_PROBE653_TYPE=1,C_PROBE654_TYPE=1,C_PROBE655_TYPE=1,C_PROBE656_TYPE=1,C_PROBE657_TYPE=1,C_PROBE658_TYPE=1,C_PROBE659_TYPE=1,C_PROBE660_TYPE=1,C_PROBE661_TYPE=1,C_PROBE662_TYPE=1,C_PROBE663_TYPE=1,C_PROBE664_TYPE=1,C_PROBE665_TYPE=1,C_PROBE666_TYPE=1,C_PROBE667_TYPE=1,C_PROBE668_TYPE=1,C_PROBE669_TYPE=1,C_PROBE670_TYPE=1,C_PROBE671_TYPE=1,C_PROBE672_TYPE=1,C_PROBE673_TYPE=1,C_PROBE674_TYPE=1,C_PROBE675_TYPE=1,C_PROBE676_TYPE=1,C_PROBE677_TYPE=1,C_PROBE678_TYPE=1,C_PROBE679_TYPE=1,C_PROBE680_TYPE=1,C_PROBE681_TYPE=1,C_PROBE682_TYPE=1,C_PROBE683_TYPE=1,C_PROBE684_TYPE=1,C_PROBE685_TYPE=1,C_PROBE686_TYPE=1,C_PROBE687_TYPE=1,C_PROBE688_TYPE=1,C_PROBE689_TYPE=1,C_PROBE690_TYPE=1,C_PROBE691_TYPE=1,C_PROBE692_TYPE=1,C_PROBE693_TYPE=1,C_PROBE694_TYPE=1,C_PROBE695_TYPE=1,C_PROBE696_TYPE=1,C_PROBE697_TYPE=1,C_PROBE698_TYPE=1,C_PROBE699_TYPE=1,C_PROBE700_TYPE=1,C_PROBE701_TYPE=1,C_PROBE702_TYPE=1,C_PROBE703_TYPE=1,C_PROBE704_TYPE=1,C_PROBE705_TYPE=1,\\\nC_PROBE706_TYPE=1,C_PROBE707_TYPE=1,C_PROBE708_TYPE=1,C_PROBE709_TYPE=1,C_PROBE710_TYPE=1,C_PROBE711_TYPE=1,C_PROBE712_TYPE=1,C_PROBE713_TYPE=1,C_PROBE714_TYPE=1,C_PROBE715_TYPE=1,C_PROBE716_TYPE=1,C_PROBE717_TYPE=1,C_PROBE718_TYPE=1,C_PROBE719_TYPE=1,C_PROBE720_TYPE=1,C_PROBE721_TYPE=1,C_PROBE722_TYPE=1,C_PROBE723_TYPE=1,C_PROBE724_TYPE=1,C_PROBE725_TYPE=1,C_PROBE726_TYPE=1,C_PROBE727_TYPE=1,C_PROBE728_TYPE=1,C_PROBE729_TYPE=1,C_PROBE730_TYPE=1,C_PROBE731_TYPE=1,C_PROBE732_TYPE=1,C_PROBE733_TYPE=1,C_PROBE734_TYPE=1,C_PROBE735_TYPE=1,C_PROBE736_TYPE=1,C_PROBE737_TYPE=1,C_PROBE738_TYPE=1,C_PROBE739_TYPE=1,C_PROBE740_TYPE=1,C_PROBE741_TYPE=1,C_PROBE742_TYPE=1,C_PROBE743_TYPE=1,C_PROBE744_TYPE=1,C_PROBE745_TYPE=1,C_PROBE746_TYPE=1,C_PROBE747_TYPE=1,C_PROBE748_TYPE=1,C_PROBE749_TYPE=1,C_PROBE750_TYPE=1,C_PROBE751_TYPE=1,C_PROBE752_TYPE=1,C_PROBE753_TYPE=1,C_PROBE754_TYPE=1,C_PROBE755_TYPE=1,C_PROBE756_TYPE=1,C_PROBE757_TYPE=1,C_PROBE758_TYPE=1,C_PROBE759_TYPE=1,C_PROBE760_TYPE=1,C_PROBE761_TYPE=1,C_PROBE762_TYPE=1,C_PROBE763_TYPE=1,C_PROBE764_TYPE=1,C_PROBE765_TYPE=1,C_PROBE766_TYPE=1,C_PROBE767_TYPE=1,C_PROBE768_TYPE=1,C_PROBE769_TYPE=1,C_PROBE770_TYPE=1,C_PROBE771_TYPE=1,C_PROBE772_TYPE=1,C_PROBE773_TYPE=1,C_PROBE774_TYPE=1,C_PROBE775_TYPE=1,C_PROBE776_TYPE=1,C_PROBE777_TYPE=1,C_PROBE778_TYPE=1,C_PROBE779_TYPE=1,C_PROBE780_TYPE=1,C_PROBE781_TYPE=1,C_PROBE782_TYPE=1,C_PROBE783_TYPE=1,C_PROBE784_TYPE=1,C_PROBE785_TYPE=1,C_PROBE786_TYPE=1,C_PROBE787_TYPE=1,C_PROBE788_TYPE=1,C_PROBE789_TYPE=1,C_PROBE790_TYPE=1,C_PROBE791_TYPE=1,C_PROBE792_TYPE=1,C_PROBE793_TYPE=1,C_PROBE794_TYPE=1,C_PROBE795_TYPE=1,C_PROBE796_TYPE=1,C_PROBE797_TYPE=1,C_PROBE798_TYPE=1,C_PROBE799_TYPE=1,C_PROBE800_TYPE=1,C_PROBE801_TYPE=1,C_PROBE802_TYPE=1,C_PROBE803_TYPE=1,C_PROBE804_TYPE=1,C_PROBE805_TYPE=1,\\\nC_PROBE806_TYPE=1,C_PROBE807_TYPE=1,C_PROBE808_TYPE=1,C_PROBE809_TYPE=1,C_PROBE810_TYPE=1,C_PROBE811_TYPE=1,C_PROBE812_TYPE=1,C_PROBE813_TYPE=1,C_PROBE814_TYPE=1,C_PROBE815_TYPE=1,C_PROBE816_TYPE=1,C_PROBE817_TYPE=1,C_PROBE818_TYPE=1,C_PROBE819_TYPE=1,C_PROBE820_TYPE=1,C_PROBE821_TYPE=1,C_PROBE822_TYPE=1,C_PROBE823_TYPE=1,C_PROBE824_TYPE=1,C_PROBE825_TYPE=1,C_PROBE826_TYPE=1,C_PROBE827_TYPE=1,C_PROBE828_TYPE=1,C_PROBE829_TYPE=1,C_PROBE830_TYPE=1,C_PROBE831_TYPE=1,C_PROBE832_TYPE=1,C_PROBE833_TYPE=1,C_PROBE834_TYPE=1,C_PROBE835_TYPE=1,C_PROBE836_TYPE=1,C_PROBE837_TYPE=1,C_PROBE838_TYPE=1,C_PROBE839_TYPE=1,C_PROBE840_TYPE=1,C_PROBE841_TYPE=1,C_PROBE842_TYPE=1,C_PROBE843_TYPE=1,C_PROBE844_TYPE=1,C_PROBE845_TYPE=1,C_PROBE846_TYPE=1,C_PROBE847_TYPE=1,C_PROBE848_TYPE=1,C_PROBE849_TYPE=1,C_PROBE850_TYPE=1,C_PROBE851_TYPE=1,C_PROBE852_TYPE=1,C_PROBE853_TYPE=1,C_PROBE854_TYPE=1,C_PROBE855_TYPE=1,C_PROBE856_TYPE=1,C_PROBE857_TYPE=1,C_PROBE858_TYPE=1,C_PROBE859_TYPE=1,C_PROBE860_TYPE=1,C_PROBE861_TYPE=1,C_PROBE862_TYPE=1,C_PROBE863_TYPE=1,C_PROBE864_TYPE=1,C_PROBE865_TYPE=1,C_PROBE866_TYPE=1,C_PROBE867_TYPE=1,C_PROBE868_TYPE=1,C_PROBE869_TYPE=1,C_PROBE870_TYPE=1,C_PROBE871_TYPE=1,C_PROBE872_TYPE=1,C_PROBE873_TYPE=1,C_PROBE874_TYPE=1,C_PROBE875_TYPE=1,C_PROBE876_TYPE=1,C_PROBE877_TYPE=1,C_PROBE878_TYPE=1,C_PROBE879_TYPE=1,C_PROBE880_TYPE=1,C_PROBE881_TYPE=1,C_PROBE882_TYPE=1,C_PROBE883_TYPE=1,C_PROBE884_TYPE=1,C_PROBE885_TYPE=1,C_PROBE886_TYPE=1,C_PROBE887_TYPE=1,C_PROBE888_TYPE=1,C_PROBE889_TYPE=1,C_PROBE890_TYPE=1,C_PROBE891_TYPE=1,C_PROBE892_TYPE=1,C_PROBE893_TYPE=1,C_PROBE894_TYPE=1,C_PROBE895_TYPE=1,C_PROBE896_TYPE=1,C_PROBE897_TYPE=1,C_PROBE898_TYPE=1,C_PROBE899_TYPE=1,C_PROBE900_TYPE=1,C_PROBE901_TYPE=1,C_PROBE902_TYPE=1,C_PROBE903_TYPE=1,C_PROBE904_TYPE=1,C_PROBE905_TYPE=1,\\\nC_PROBE906_TYPE=1,C_PROBE907_TYPE=1,C_PROBE908_TYPE=1,C_PROBE909_TYPE=1,C_PROBE910_TYPE=1,C_PROBE911_TYPE=1,C_PROBE912_TYPE=1,C_PROBE913_TYPE=1,C_PROBE914_TYPE=1,C_PROBE915_TYPE=1,C_PROBE916_TYPE=1,C_PROBE917_TYPE=1,C_PROBE918_TYPE=1,C_PROBE919_TYPE=1,C_PROBE920_TYPE=1,C_PROBE921_TYPE=1,C_PROBE922_TYPE=1,C_PROBE923_TYPE=1,C_PROBE924_TYPE=1,C_PROBE925_TYPE=1,C_PROBE926_TYPE=1,C_PROBE927_TYPE=1,C_PROBE928_TYPE=1,C_PROBE929_TYPE=1,C_PROBE930_TYPE=1,C_PROBE931_TYPE=1,C_PROBE932_TYPE=1,C_PROBE933_TYPE=1,C_PROBE934_TYPE=1,C_PROBE935_TYPE=1,C_PROBE936_TYPE=1,C_PROBE937_TYPE=1,C_PROBE938_TYPE=1,C_PROBE939_TYPE=1,C_PROBE940_TYPE=1,C_PROBE941_TYPE=1,C_PROBE942_TYPE=1,C_PROBE943_TYPE=1,C_PROBE944_TYPE=1,C_PROBE945_TYPE=1,C_PROBE946_TYPE=1,C_PROBE947_TYPE=1,C_PROBE948_TYPE=1,C_PROBE949_TYPE=1,C_PROBE950_TYPE=1,C_PROBE951_TYPE=1,C_PROBE952_TYPE=1,C_PROBE953_TYPE=1,C_PROBE954_TYPE=1,C_PROBE955_TYPE=1,C_PROBE956_TYPE=1,C_PROBE957_TYPE=1,C_PROBE958_TYPE=1,C_PROBE959_TYPE=1,C_PROBE960_TYPE=1,C_PROBE961_TYPE=1,C_PROBE962_TYPE=1,C_PROBE963_TYPE=1,C_PROBE964_TYPE=1,C_PROBE965_TYPE=1,C_PROBE966_TYPE=1,C_PROBE967_TYPE=1,C_PROBE968_TYPE=1,C_PROBE969_TYPE=1,C_PROBE970_TYPE=1,C_PROBE971_TYPE=1,C_PROBE972_TYPE=1,C_PROBE973_TYPE=1,C_PROBE974_TYPE=1,C_PROBE975_TYPE=1,C_PROBE976_TYPE=1,C_PROBE977_TYPE=1,C_PROBE978_TYPE=1,C_PROBE979_TYPE=1,C_PROBE980_TYPE=1,C_PROBE981_TYPE=1,C_PROBE982_TYPE=1,C_PROBE983_TYPE=1,C_PROBE984_TYPE=1,C_PROBE985_TYPE=1,C_PROBE986_TYPE=1,C_PROBE987_TYPE=1,C_PROBE988_TYPE=1,C_PROBE989_TYPE=1,C_PROBE990_TYPE=1,C_PROBE991_TYPE=1,C_PROBE992_TYPE=1,C_PROBE993_TYPE=1,C_PROBE994_TYPE=1,C_PROBE995_TYPE=1,C_PROBE996_TYPE=1,C_PROBE997_TYPE=1,C_PROBE998_TYPE=1,C_PROBE999_TYPE=1,C_PROBE1000_TYPE=1,C_PROBE1001_TYPE=1,C_PROBE1002_TYPE=1,C_PROBE1003_TYPE=1,C_PROBE1004_TYPE=1,C_PROBE1005_TYPE=1,\\\nC_PROBE1006_TYPE=1,C_PROBE1007_TYPE=1,C_PROBE1008_TYPE=1,C_PROBE1009_TYPE=1,C_PROBE1010_TYPE=1,C_PROBE1011_TYPE=1,C_PROBE1012_TYPE=1,C_PROBE1013_TYPE=1,C_PROBE1014_TYPE=1,C_PROBE1015_TYPE=1,C_PROBE1016_TYPE=1,C_PROBE1017_TYPE=1,C_PROBE1018_TYPE=1,C_PROBE1019_TYPE=1,C_PROBE1020_TYPE=1,C_PROBE1021_TYPE=1,C_PROBE1022_TYPE=1,C_PROBE1023_TYPE=1}\" *)\n\nmodule ila_0 (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [63 : 0] probe1;\ninput [0 : 0] probe2;\ninput [0 : 0] probe3;\ninput [63 : 0] probe4;\ninput [0 : 0] probe5;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_11_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(6),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2020),\n.C_MINOR_VERSION(2),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(0),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(4),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH (32),\n.C_ILA_CLK_FREQ(2000000),\n.C_PROBE0_WIDTH(1),\n.C_PROBE1_WIDTH(64),\n.C_PROBE2_WIDTH(1),\n.C_PROBE3_WIDTH(1),\n.C_PROBE4_WIDTH(64),\n.C_PROBE5_WIDTH(1),\n.C_PROBE6_WIDTH(1),\n.C_PROBE7_WIDTH(1),\n.C_PROBE8_WIDTH(1),\n.C_PROBE9_WIDTH(1),\n.C_PROBE10_WIDTH(1),\n.C_PROBE11_WIDTH(1),\n.C_PROBE12_WIDTH(1),\n.C_PROBE13_WIDTH(1),\n.C_PROBE14_WIDTH(1),\n.C_PROBE15_WIDTH(1),\n.C_PROBE16_WIDTH(1),\n.C_PROBE17_WIDTH(1),\n.C_PROBE18_WIDTH(1),\n.C_PROBE19_WIDTH(1),\n.C_PROBE20_WIDTH(1),\n.C_PROBE21_WIDTH(1),\n.C_PROBE22_WIDTH(1),\n.C_PROBE23_WIDTH(1),\n.C_PROBE24_WIDTH(1),\n.C_PROBE25_WIDTH(1),\n.C_PROBE26_WIDTH(1),\n.C_PROBE27_WIDTH(1),\n.C_PROBE28_WIDTH(1),\n.C_PROBE29_WIDTH(1),\n.C_PROBE30_WIDTH(1),\n.C_PROBE31_WIDTH(1),\n.C_PROBE32_WIDTH(1),\n.C_PROBE33_WIDTH(1),\n.C_PROBE34_WIDTH(1),\n.C_PROBE35_WIDTH(1),\n.C_PROBE36_WIDTH(1),\n.C_PROBE37_WIDTH(1),\n.C_PROBE38_WIDTH(1),\n.C_PROBE39_WIDTH(1),\n.C_PROBE40_WIDTH(1),\n.C_PROBE41_WIDTH(1),\n.C_PROBE42_WIDTH(1),\n.C_PROBE43_WIDTH(1),\n.C_PROBE44_WIDTH(1),\n.C_PROBE45_WIDTH(1),\n.C_PROBE46_WIDTH(1),\n.C_PROBE47_WIDTH(1),\n.C_PROBE48_WIDTH(1),\n.C_PROBE49_WIDTH(1),\n.C_PROBE50_WIDTH(1),\n.C_PROBE51_WIDTH(1),\n.C_PROBE52_WIDTH(1),\n.C_PROBE53_WIDTH(1),\n.C_PROBE54_WIDTH(1),\n.C_PROBE55_WIDTH(1),\n.C_PROBE56_WIDTH(1),\n.C_PROBE57_WIDTH(1),\n.C_PROBE58_WIDTH(1),\n.C_PROBE59_WIDTH(1),\n.C_PROBE60_WIDTH(1),\n.C_PROBE61_WIDTH(1),\n.C_PROBE62_WIDTH(1),\n.C_PROBE63_WIDTH(1),\n.C_PROBE64_WIDTH(1),\n.C_PROBE65_WIDTH(1),\n.C_PROBE66_WIDTH(1),\n.C_PROBE67_WIDTH(1),\n.C_PROBE68_WIDTH(1),\n.C_PROBE69_WIDTH(1),\n.C_PROBE70_WIDTH(1),\n.C_PROBE71_WIDTH(1),\n.C_PROBE72_WIDTH(1),\n.C_PROBE73_WIDTH(1),\n.C_PROBE74_WIDTH(1),\n.C_PROBE75_WIDTH(1),\n.C_PROBE76_WIDTH(1),\n.C_PROBE77_WIDTH(1),\n.C_PROBE78_WIDTH(1),\n.C_PROBE79_WIDTH(1),\n.C_PROBE80_WIDTH(1),\n.C_PROBE81_WIDTH(1),\n.C_PROBE82_WIDTH(1),\n.C_PROBE83_WIDTH(1),\n.C_PROBE84_WIDTH(1),\n.C_PROBE85_WIDTH(1),\n.C_PROBE86_WIDTH(1),\n.C_PROBE87_WIDTH(1),\n.C_PROBE88_WIDTH(1),\n.C_PROBE89_WIDTH(1),\n.C_PROBE90_WIDTH(1),\n.C_PROBE91_WIDTH(1),\n.C_PROBE92_WIDTH(1),\n.C_PROBE93_WIDTH(1),\n.C_PROBE94_WIDTH(1),\n.C_PROBE95_WIDTH(1),\n.C_PROBE96_WIDTH(1),\n.C_PROBE97_WIDTH(1),\n.C_PROBE98_WIDTH(1),\n.C_PROBE99_WIDTH(1),\n.C_PROBE100_WIDTH(1),\n.C_PROBE101_WIDTH(1),\n.C_PROBE102_WIDTH(1),\n.C_PROBE103_WIDTH(1),\n.C_PROBE104_WIDTH(1),\n.C_PROBE105_WIDTH(1),\n.C_PROBE106_WIDTH(1),\n.C_PROBE107_WIDTH(1),\n.C_PROBE108_WIDTH(1),\n.C_PROBE109_WIDTH(1),\n.C_PROBE110_WIDTH(1),\n.C_PROBE111_WIDTH(1),\n.C_PROBE112_WIDTH(1),\n.C_PROBE113_WIDTH(1),\n.C_PROBE114_WIDTH(1),\n.C_PROBE115_WIDTH(1),\n.C_PROBE116_WIDTH(1),\n.C_PROBE117_WIDTH(1),\n.C_PROBE118_WIDTH(1),\n.C_PROBE119_WIDTH(1),\n.C_PROBE120_WIDTH(1),\n.C_PROBE121_WIDTH(1),\n.C_PROBE122_WIDTH(1),\n.C_PROBE123_WIDTH(1),\n.C_PROBE124_WIDTH(1),\n.C_PROBE125_WIDTH(1),\n.C_PROBE126_WIDTH(1),\n.C_PROBE127_WIDTH(1),\n.C_PROBE128_WIDTH(1),\n.C_PROBE129_WIDTH(1),\n.C_PROBE130_WIDTH(1),\n.C_PROBE131_WIDTH(1),\n.C_PROBE132_WIDTH(1),\n.C_PROBE133_WIDTH(1),\n.C_PROBE134_WIDTH(1),\n.C_PROBE135_WIDTH(1),\n.C_PROBE136_WIDTH(1),\n.C_PROBE137_WIDTH(1),\n.C_PROBE138_WIDTH(1),\n.C_PROBE139_WIDTH(1),\n.C_PROBE140_WIDTH(1),\n.C_PROBE141_WIDTH(1),\n.C_PROBE142_WIDTH(1),\n.C_PROBE143_WIDTH(1),\n.C_PROBE144_WIDTH(1),\n.C_PROBE145_WIDTH(1),\n.C_PROBE146_WIDTH(1),\n.C_PROBE147_WIDTH(1),\n.C_PROBE148_WIDTH(1),\n.C_PROBE149_WIDTH(1),\n.C_PROBE150_WIDTH(1),\n.C_PROBE151_WIDTH(1),\n.C_PROBE152_WIDTH(1),\n.C_PROBE153_WIDTH(1),\n.C_PROBE154_WIDTH(1),\n.C_PROBE155_WIDTH(1),\n.C_PROBE156_WIDTH(1),\n.C_PROBE157_WIDTH(1),\n.C_PROBE158_WIDTH(1),\n.C_PROBE159_WIDTH(1),\n.C_PROBE160_WIDTH(1),\n.C_PROBE161_WIDTH(1),\n.C_PROBE162_WIDTH(1),\n.C_PROBE163_WIDTH(1),\n.C_PROBE164_WIDTH(1),\n.C_PROBE165_WIDTH(1),\n.C_PROBE166_WIDTH(1),\n.C_PROBE167_WIDTH(1),\n.C_PROBE168_WIDTH(1),\n.C_PROBE169_WIDTH(1),\n.C_PROBE170_WIDTH(1),\n.C_PROBE171_WIDTH(1),\n.C_PROBE172_WIDTH(1),\n.C_PROBE173_WIDTH(1),\n.C_PROBE174_WIDTH(1),\n.C_PROBE175_WIDTH(1),\n.C_PROBE176_WIDTH(1),\n.C_PROBE177_WIDTH(1),\n.C_PROBE178_WIDTH(1),\n.C_PROBE179_WIDTH(1),\n.C_PROBE180_WIDTH(1),\n.C_PROBE181_WIDTH(1),\n.C_PROBE182_WIDTH(1),\n.C_PROBE183_WIDTH(1),\n.C_PROBE184_WIDTH(1),\n.C_PROBE185_WIDTH(1),\n.C_PROBE186_WIDTH(1),\n.C_PROBE187_WIDTH(1),\n.C_PROBE188_WIDTH(1),\n.C_PROBE189_WIDTH(1),\n.C_PROBE190_WIDTH(1),\n.C_PROBE191_WIDTH(1),\n.C_PROBE192_WIDTH(1),\n.C_PROBE193_WIDTH(1),\n.C_PROBE194_WIDTH(1),\n.C_PROBE195_WIDTH(1),\n.C_PROBE196_WIDTH(1),\n.C_PROBE197_WIDTH(1),\n.C_PROBE198_WIDTH(1),\n.C_PROBE199_WIDTH(1),\n.C_PROBE200_WIDTH(1),\n.C_PROBE201_WIDTH(1),\n.C_PROBE202_WIDTH(1),\n.C_PROBE203_WIDTH(1),\n.C_PROBE204_WIDTH(1),\n.C_PROBE205_WIDTH(1),\n.C_PROBE206_WIDTH(1),\n.C_PROBE207_WIDTH(1),\n.C_PROBE208_WIDTH(1),\n.C_PROBE209_WIDTH(1),\n.C_PROBE210_WIDTH(1),\n.C_PROBE211_WIDTH(1),\n.C_PROBE212_WIDTH(1),\n.C_PROBE213_WIDTH(1),\n.C_PROBE214_WIDTH(1),\n.C_PROBE215_WIDTH(1),\n.C_PROBE216_WIDTH(1),\n.C_PROBE217_WIDTH(1),\n.C_PROBE218_WIDTH(1),\n.C_PROBE219_WIDTH(1),\n.C_PROBE220_WI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_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT(1),\n.C_PROBE275_MU_CNT(1),\n.C_PROBE276_MU_CNT(1),\n.C_PROBE277_MU_CNT(1),\n.C_PROBE278_MU_CNT(1),\n.C_PROBE279_MU_CNT(1),\n.C_PROBE280_MU_CNT(1),\n.C_PROBE281_MU_CNT(1),\n.C_PROBE282_MU_CNT(1),\n.C_PROBE283_MU_CNT(1),\n.C_PROBE284_MU_CNT(1),\n.C_PROBE285_MU_CNT(1),\n.C_PROBE286_MU_CNT(1),\n.C_PROBE287_MU_CNT(1),\n.C_PROBE288_MU_CNT(1),\n.C_PROBE289_MU_CNT(1),\n.C_PROBE290_MU_CNT(1),\n.C_PROBE291_MU_CNT(1),\n.C_PROBE292_MU_CNT(1),\n.C_PROBE293_MU_CNT(1),\n.C_PROBE294_MU_CNT(1),\n.C_PROBE295_MU_CNT(1),\n.C_PROBE296_MU_CNT(1),\n.C_PROBE297_MU_CNT(1),\n.C_PROBE298_MU_CNT(1),\n.C_PROBE299_MU_CNT(1),\n.C_PROBE300_MU_CNT(1),\n.C_PROBE301_MU_CNT(1),\n.C_PROBE302_MU_CNT(1),\n.C_PROBE303_MU_CNT(1),\n.C_PROBE304_MU_CNT(1),\n.C_PROBE305_MU_CNT(1),\n.C_PROBE306_MU_CNT(1),\n.C_PROBE307_MU_CNT(1),\n.C_PROBE308_MU_CNT(1),\n.C_PROBE309_MU_CNT(1),\n.C_PROBE310_MU_CNT(1),\n.C_PROBE311_MU_CNT(1),\n.C_PROBE312_MU_CNT(1),\n.C_PROBE313_MU_CNT(1),\n.C_PROBE314_MU_CNT(1),\n.C_PROBE315_MU_CNT(1),\n.C_PROBE316_MU_CNT(1),\n.C_PROBE317_MU_CNT(1),\n.C_PROBE318_MU_CNT(1),\n.C_PROBE319_MU_CNT(1),\n.C_PROBE320_MU_CNT(1),\n.C_PROBE321_MU_CNT(1),\n.C_PROBE322_MU_CNT(1),\n.C_PROBE323_MU_CNT(1),\n.C_PROBE324_MU_CNT(1),\n.C_PROBE325_MU_CNT(1),\n.C_PROBE326_MU_CNT(1),\n.C_PROBE327_MU_CNT(1),\n.C_PROBE328_MU_CNT(1),\n.C_PROBE329_MU_CNT(1),\n.C_PROBE330_MU_CNT(1),\n.C_PROBE331_MU_CNT(1),\n.C_PROBE332_MU_CNT(1),\n.C_PROBE333_MU_CNT(1),\n.C_PROBE334_MU_CNT(1),\n.C_PROBE335_MU_CNT(1),\n.C_PROBE336_MU_CNT(1),\n.C_PROBE337_MU_CNT(1),\n.C_PROBE338_MU_CNT(1),\n.C_PROBE339_MU_CNT(1),\n.C_PROBE340_MU_CNT(1),\n.C_PROBE341_MU_CNT(1),\n.C_PROBE342_MU_CNT(1),\n.C_PROBE343_MU_CNT(1),\n.C_PROBE344_MU_CNT(1),\n.C_PROBE345_MU_CNT(1),\n.C_PROBE346_MU_CNT(1),\n.C_PROBE347_MU_CNT(1),\n.C_PROBE348_MU_CNT(1),\n.C_PROBE349_MU_CNT(1),\n.C_PROBE350_MU_CNT(1),\n.C_PROBE351_MU_CNT(1),\n.C_PROBE352_MU_CNT(1),\n.C_PROBE353_MU_CNT(1),\n.C_PROBE354_MU_CNT(1),\n.C_PROBE355_MU_CNT(1),\n.C_PROBE356_MU_CNT(1),\n.C_PROBE357_MU_CNT(1),\n.C_PROBE358_MU_CNT(1),\n.C_PROBE359_MU_CNT(1),\n.C_PROBE360_MU_CNT(1),\n.C_PROBE361_MU_CNT(1),\n.C_PROBE362_MU_CNT(1),\n.C_PROBE363_MU_CNT(1),\n.C_PROBE364_MU_CNT(1),\n.C_PROBE365_MU_CNT(1),\n.C_PROBE366_MU_CNT(1),\n.C_PROBE367_MU_CNT(1),\n.C_PROBE368_MU_CNT(1),\n.C_PROBE369_MU_CNT(1),\n.C_PROBE370_MU_CNT(1),\n.C_PROBE371_MU_CNT(1),\n.C_PROBE372_MU_CNT(1),\n.C_PROBE373_MU_CNT(1),\n.C_PROBE374_MU_CNT(1),\n.C_PROBE375_MU_CNT(1),\n.C_PROBE376_MU_CNT(1),\n.C_PROBE377_MU_CNT(1),\n.C_PROBE378_MU_CNT(1),\n.C_PROBE379_MU_CNT(1),\n.C_PROBE380_MU_CNT(1),\n.C_PROBE381_MU_CNT(1),\n.C_PROBE382_MU_CNT(1),\n.C_PROBE383_MU_CNT(1),\n.C_PROBE384_MU_CNT(1),\n.C_PROBE385_MU_CNT(1),\n.C_PROBE386_MU_CNT(1),\n.C_PROBE387_MU_CNT(1),\n.C_PROBE388_MU_CNT(1),\n.C_PROBE389_MU_CNT(1),\n.C_PROBE390_MU_CNT(1),\n.C_PROBE391_MU_CNT(1),\n.C_PROBE392_MU_CNT(1),\n.C_PROBE393_MU_CNT(1),\n.C_PROBE394_MU_CNT(1),\n.C_PROBE395_MU_CNT(1),\n.C_PROBE396_MU_CNT(1),\n.C_PROBE397_MU_CNT(1),\n.C_PROBE398_MU_CNT(1),\n.C_PROBE399_MU_CNT(1),\n.C_PROBE400_MU_CNT(1),\n.C_PROBE401_MU_CNT(1),\n.C_PROBE402_MU_CNT(1),\n.C_PROBE403_MU_CNT(1),\n.C_PROBE404_MU_CNT(1),\n.C_PROBE405_MU_CNT(1),\n.C_PROBE406_MU_CNT(1),\n.C_PROBE407_MU_CNT(1),\n.C_PROBE408_MU_CNT(1),\n.C_PROBE409_MU_CNT(1),\n.C_PROBE410_MU_CNT(1),\n.C_PROBE411_MU_CNT(1),\n.C_PROBE412_MU_CNT(1),\n.C_PROBE413_MU_CNT(1),\n.C_PROBE414_MU_CNT(1),\n.C_PROBE415_MU_CNT(1),\n.C_PROBE416_MU_CNT(1),\n.C_PROBE417_MU_CNT(1),\n.C_PROBE418_MU_CNT(1),\n.C_PROBE419_MU_CNT(1),\n.C_PROBE420_MU_CNT(1),\n.C_PROBE421_MU_CNT(1),\n.C_PROBE422_MU_CNT(1),\n.C_PROBE423_MU_CNT(1),\n.C_PROBE424_MU_CNT(1),\n.C_PROBE425_MU_CNT(1),\n.C_PROBE426_MU_CNT(1),\n.C_PROBE427_MU_CNT(1),\n.C_PROBE428_MU_CNT(1),\n.C_PROBE429_MU_CNT(1),\n.C_PROBE430_MU_CNT(1),\n.C_PROBE431_MU_CNT(1),\n.C_PROBE432_MU_CNT(1),\n.C_PROBE433_MU_CNT(1),\n.C_PROBE434_MU_CNT(1),\n.C_PROBE435_MU_CNT(1),\n.C_PROBE436_MU_CNT(1),\n.C_PROBE437_MU_CNT(1),\n.C_PROBE438_MU_CNT(1),\n.C_PROBE439_MU_CNT(1),\n.C_PROBE440_MU_CNT(1),\n.C_PROBE441_MU_CNT(1),\n.C_PROBE442_MU_CNT(1),\n.C_PROBE443_MU_CNT(1),\n.C_PROBE444_MU_CNT(1),\n.C_PROBE445_MU_CNT(1),\n.C_PROBE446_MU_CNT(1),\n.C_PROBE447_MU_CNT(1),\n.C_PROBE448_MU_CNT(1),\n.C_PROBE449_MU_CNT(1),\n.C_PROBE450_MU_CNT(1),\n.C_PROBE451_MU_CNT(1),\n.C_PROBE452_MU_CNT(1),\n.C_PROBE453_MU_CNT(1),\n.C_PROBE454_MU_CNT(1),\n.C_PROBE455_MU_CNT(1),\n.C_PROBE456_MU_CNT(1),\n.C_PROBE457_MU_CNT(1),\n.C_PROBE458_MU_CNT(1),\n.C_PROBE459_MU_CNT(1),\n.C_PROBE460_MU_CNT(1),\n.C_PROBE461_MU_CNT(1),\n.C_PROBE462_MU_CNT(1),\n.C_PROBE463_MU_CNT(1),\n.C_PROBE464_MU_CNT(1),\n.C_PROBE465_MU_CNT(1),\n.C_PROBE466_MU_CNT(1),\n.C_PROBE467_MU_CNT(1),\n.C_PROBE468_MU_CNT(1),\n.C_PROBE469_MU_CNT(1),\n.C_PROBE470_MU_CNT(1),\n.C_PROBE471_MU_CNT(1),\n.C_PROBE472_MU_CNT(1),\n.C_PROBE473_MU_CNT(1),\n.C_PROBE474_MU_CNT(1),\n.C_PROBE475_MU_CNT(1),\n.C_PROBE476_MU_CNT(1),\n.C_PROBE477_MU_CNT(1),\n.C_PROBE478_MU_CNT(1),\n.C_PROBE479_MU_CNT(1),\n.C_PROBE480_MU_CNT(1),\n.C_PROBE481_MU_CNT(1),\n.C_PROBE482_MU_CNT(1),\n.C_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1),\n.C_PROBE691_MU_CNT(1),\n.C_PROBE692_MU_CNT(1),\n.C_PROBE693_MU_CNT(1),\n.C_PROBE694_MU_CNT(1),\n.C_PROBE695_MU_CNT(1),\n.C_PROBE696_MU_CNT(1),\n.C_PROBE697_MU_CNT(1),\n.C_PROBE698_MU_CNT(1),\n.C_PROBE699_MU_CNT(1),\n.C_PROBE700_MU_CNT(1),\n.C_PROBE701_MU_CNT(1),\n.C_PROBE702_MU_CNT(1),\n.C_PROBE703_MU_CNT(1),\n.C_PROBE704_MU_CNT(1),\n.C_PROBE705_MU_CNT(1),\n.C_PROBE706_MU_CNT(1),\n.C_PROBE707_MU_CNT(1),\n.C_PROBE708_MU_CNT(1),\n.C_PROBE709_MU_CNT(1),\n.C_PROBE710_MU_CNT(1),\n.C_PROBE711_MU_CNT(1),\n.C_PROBE712_MU_CNT(1),\n.C_PROBE713_MU_CNT(1),\n.C_PROBE714_MU_CNT(1),\n.C_PROBE715_MU_CNT(1),\n.C_PROBE716_MU_CNT(1),\n.C_PROBE717_MU_CNT(1),\n.C_PROBE718_MU_CNT(1),\n.C_PROBE719_MU_CNT(1),\n.C_PROBE720_MU_CNT(1),\n.C_PROBE721_MU_CNT(1),\n.C_PROBE722_MU_CNT(1),\n.C_PROBE723_MU_CNT(1),\n.C_PROBE724_MU_CNT(1),\n.C_PROBE725_MU_CNT(1),\n.C_PROBE726_MU_CNT(1),\n.C_PROBE727_MU_CNT(1),\n.C_PROBE728_MU_CNT(1),\n.C_PROBE729_MU_CNT(1),\n.C_PROBE730_MU_CNT(1),\n.C_PROBE731_MU_CNT(1),\n.C_PROBE732_MU_CNT(1),\n.C_PROBE733_MU_CNT(1),\n.C_PROBE734_MU_CNT(1),\n.C_PROBE735_MU_CNT(1),\n.C_PROBE736_MU_CNT(1),\n.C_PROBE737_MU_CNT(1),\n.C_PROBE738_MU_CNT(1),\n.C_PROBE739_MU_CNT(1),\n.C_PROBE740_MU_CNT(1),\n.C_PROBE741_MU_CNT(1),\n.C_PROBE742_MU_CNT(1),\n.C_PROBE743_MU_CNT(1),\n.C_PROBE744_MU_CNT(1),\n.C_PROBE745_MU_CNT(1),\n.C_PROBE746_MU_CNT(1),\n.C_PROBE747_MU_CNT(1),\n.C_PROBE748_MU_CNT(1),\n.C_PROBE749_MU_CNT(1),\n.C_PROBE750_MU_CNT(1),\n.C_PROBE751_MU_CNT(1),\n.C_PROBE752_MU_CNT(1),\n.C_PROBE753_MU_CNT(1),\n.C_PROBE754_MU_CNT(1),\n.C_PROBE755_MU_CNT(1),\n.C_PROBE756_MU_CNT(1),\n.C_PROBE757_MU_CNT(1),\n.C_PROBE758_MU_CNT(1),\n.C_PROBE759_MU_CNT(1),\n.C_PROBE760_MU_CNT(1),\n.C_PROBE761_MU_CNT(1),\n.C_PROBE762_MU_CNT(1),\n.C_PROBE763_MU_CNT(1),\n.C_PROBE764_MU_CNT(1),\n.C_PROBE765_MU_CNT(1),\n.C_PROBE766_MU_CNT(1),\n.C_PROBE767_MU_CNT(1),\n.C_PROBE768_MU_CNT(1),\n.C_PROBE769_MU_CNT(1),\n.C_PROBE770_MU_CNT(1),\n.C_PROBE771_MU_CNT(1),\n.C_PROBE772_MU_CNT(1),\n.C_PROBE773_MU_CNT(1),\n.C_PROBE774_MU_CNT(1),\n.C_PROBE775_MU_CNT(1),\n.C_PROBE776_MU_CNT(1),\n.C_PROBE777_MU_CNT(1),\n.C_PROBE778_MU_CNT(1),\n.C_PROBE779_MU_CNT(1),\n.C_PROBE780_MU_CNT(1),\n.C_PROBE781_MU_CNT(1),\n.C_PROBE782_MU_CNT(1),\n.C_PROBE783_MU_CNT(1),\n.C_PROBE784_MU_CNT(1),\n.C_PROBE785_MU_CNT(1),\n.C_PROBE786_MU_CNT(1),\n.C_PROBE787_MU_CNT(1),\n.C_PROBE788_MU_CNT(1),\n.C_PROBE789_MU_CNT(1),\n.C_PROBE790_MU_CNT(1),\n.C_PROBE791_MU_CNT(1),\n.C_PROBE792_MU_CNT(1),\n.C_PROBE793_MU_CNT(1),\n.C_PROBE794_MU_CNT(1),\n.C_PROBE795_MU_CNT(1),\n.C_PROBE796_MU_CNT(1),\n.C_PROBE797_MU_CNT(1),\n.C_PROBE798_MU_CNT(1),\n.C_PROBE799_MU_CNT(1),\n.C_PROBE800_MU_CNT(1),\n.C_PROBE801_MU_CNT(1),\n.C_PROBE802_MU_CNT(1),\n.C_PROBE803_MU_CNT(1),\n.C_PROBE804_MU_CNT(1),\n.C_PROBE805_MU_CNT(1),\n.C_PROBE806_MU_CNT(1),\n.C_PROBE807_MU_CNT(1),\n.C_PROBE808_MU_CNT(1),\n.C_PROBE809_MU_CNT(1),\n.C_PROBE810_MU_CNT(1),\n.C_PROBE811_MU_CNT(1),\n.C_PROBE812_MU_CNT(1),\n.C_PROBE813_MU_CNT(1),\n.C_PROBE814_MU_CNT(1),\n.C_PROBE815_MU_CNT(1),\n.C_PROBE816_MU_CNT(1),\n.C_PROBE817_MU_CNT(1),\n.C_PROBE818_MU_CNT(1),\n.C_PROBE819_MU_CNT(1),\n.C_PROBE820_MU_CNT(1),\n.C_PROBE821_MU_CNT(1),\n.C_PROBE822_MU_CNT(1),\n.C_PROBE823_MU_CNT(1),\n.C_PROBE824_MU_CNT(1),\n.C_PROBE825_MU_CNT(1),\n.C_PROBE826_MU_CNT(1),\n.C_PROBE827_MU_CNT(1),\n.C_PROBE828_MU_CNT(1),\n.C_PROBE829_MU_CNT(1),\n.C_PROBE830_MU_CNT(1),\n.C_PROBE831_MU_CNT(1),\n.C_PROBE832_MU_CNT(1),\n.C_PROBE833_MU_CNT(1),\n.C_PROBE834_MU_CNT(1),\n.C_PROBE835_MU_CNT(1),\n.C_PROBE836_MU_CNT(1),\n.C_PROBE837_MU_CNT(1),\n.C_PROBE838_MU_CNT(1),\n.C_PROBE839_MU_CNT(1),\n.C_PROBE840_MU_CNT(1),\n.C_PROBE841_MU_CNT(1),\n.C_PROBE842_MU_CNT(1),\n.C_PROBE843_MU_CNT(1),\n.C_PROBE844_MU_CNT(1),\n.C_PROBE845_MU_CNT(1),\n.C_PROBE846_MU_CNT(1),\n.C_PROBE847_MU_CNT(1),\n.C_PROBE848_MU_CNT(1),\n.C_PROBE849_MU_CNT(1),\n.C_PROBE850_MU_CNT(1),\n.C_PROBE851_MU_CNT(1),\n.C_PROBE852_MU_CNT(1),\n.C_PROBE853_MU_CNT(1),\n.C_PROBE854_MU_CNT(1),\n.C_PROBE855_MU_CNT(1),\n.C_PROBE856_MU_CNT(1),\n.C_PROBE857_MU_CNT(1),\n.C_PROBE858_MU_CNT(1),\n.C_PROBE859_MU_CNT(1),\n.C_PROBE860_MU_CNT(1),\n.C_PROBE861_MU_CNT(1),\n.C_PROBE862_MU_CNT(1),\n.C_PROBE863_MU_CNT(1),\n.C_PROBE864_MU_CNT(1),\n.C_PROBE865_MU_CNT(1),\n.C_PROBE866_MU_CNT(1),\n.C_PROBE867_MU_CNT(1),\n.C_PROBE868_MU_CNT(1),\n.C_PROBE869_MU_CNT(1),\n.C_PROBE870_MU_CNT(1),\n.C_PROBE871_MU_CNT(1),\n.C_PROBE872_MU_CNT(1),\n.C_PROBE873_MU_CNT(1),\n.C_PROBE874_MU_CNT(1),\n.C_PROBE875_MU_CNT(1),\n.C_PROBE876_MU_CNT(1),\n.C_PROBE877_MU_CNT(1),\n.C_PROBE878_MU_CNT(1),\n.C_PROBE879_MU_CNT(1),\n.C_PROBE880_MU_CNT(1),\n.C_PROBE881_MU_CNT(1),\n.C_PROBE882_MU_CNT(1),\n.C_PROBE883_MU_CNT(1),\n.C_PROBE884_MU_CNT(1),\n.C_PROBE885_MU_CNT(1),\n.C_PROBE886_MU_CNT(1),\n.C_PROBE887_MU_CNT(1),\n.C_PROBE888_MU_CNT(1),\n.C_PROBE889_MU_CNT(1),\n.C_PROBE890_MU_CNT(1),\n.C_PROBE891_MU_CNT(1),\n.C_PROBE892_MU_CNT(1),\n.C_PROBE893_MU_CNT(1),\n.C_PROBE894_MU_CNT(1),\n.C_PROBE895_MU_CNT(1),\n.C_PROBE896_MU_CNT(1),\n.C_PROBE897_MU_CNT(1),\n.C_PROBE898_MU_CNT(1),\n.C_PROBE899_MU_CNT(1),\n.C_PROBE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synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4251}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nXvoWuyjysN5V55U4xsjyWg2bXI++8I1KAZgJ0eiQkY3L8ns1PfNti9fujmr8wvFQA6ycwh4K6mSp\nINQjc8TyLQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nbD05I2IKef08FLVG4C2ftkJOY+/UsvagxY6ta+A0N1USwLQivKTmRt7LJlQ+5UJqrfPvhHMyYrLN\nrjoJbClg85XfNTYCnalRVvg3mmCcjtJkCLf6S5E9Q6UF92b6bwgtMTsr0BndJhdItlJtr0dYZtoP\nAEskMBthh6RdNMkZ3CA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nvLo4Yp/zX6HvZ92VMA2Xr4EIhMWPNGq2EvSBkjiZd5sCSFAX+37MKx4gdbrsGvhUMl1njqvSaoP7\nKrAa29/cm3QWjPgpaCsR/MhnaG5+7aUvxA5iCqVHXdriMlgx9kzxkB9SD+mOC8XR5LtYA0bPhbZ9\njQzWpWxdaOGYFF25DU0O9M7LMc7SLfKunYH/cQ91D37m0LjgZh1/uZv8chFzvCBbkHqUU0qi17/k\nZTWIIzqb1oycbuhZZrWLl95xQ/aaTxZ30sONWd/axZtO3Cd57huCbCxLuOH51qq6erD9AVszmxL8\noEoM+KW88P1S3LJ/EcIQN4LU0/nyN/f7xEmy2w==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nj99ihkoCqIO9DhRZEJdEqlRF2P+IwS2wuYmoh3hWFCDXbmGTwTqc+3EMjxY8Z4uDixuazjlTMiEH\nCk4MdTkVZ55pPhFb4druHTap3Twn20B3SWvOy2nf84OpTkdBnbK4qagABgZXs9/mAtQxbF++/F6Y\n+OOE3yUNTWvHiVGvpTJavfADkB2CL5wEIlBSnYRwtLp71JokDsMvjq2l3o3hxAjvtdg9ej7NKx4I\nkAZfrpZH7Ebv2hfXrTVI2kDTAl5Etr+4oSqxIhABJut2WaeWJrsSbL+dz9s2ZmYDMb1BCQdRexck\nbMMvUaS+P7sSGuR9BTVynHOY5GdQelHO1aazQw==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nHuzbd0U90PuPKn40554Cnki98HuQSq7dg6ZyXufEWFHsji6rteNupAY3HQsuLpXjFVxsNlS4bcHj\nAAOnDcL0hCCVbSkU011mqhhlkFmWqeBBECGfP+T7/+l9KBu+9ynszhlhaVhmZMffsEuohDl5x084\nFnzFCdxrFyvqrOyWDac=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\neoQKmSsNWNEOJcUApe0UhUNGRDkxOLedPbjyDILgUJWMG+WVCpL9MC2MXZeZ6/oVwAYRlZTZsF1h\nUsVo6BO7IAuHuJAHeIQgEs2oIMj/I2qZxm9wUsOzWoK5/Jz4SS4sTE3TgOJXaX1GNAJlbUrCBtnM\nqIiavU164vZjX5BFoPGuHp4kICN8A4Wr9y2w2Lh0/IdiHjr/Ruk5PpVNyl7tW9EaSFY1AL4aoQpd\nRFDdUFRk4tMBtmFxi/B+pLVFE0hAUZnlVCsSaf4B0lN/m4CME7lgy7oXElp7ov4fMnD9VI8HLGMX\nWBSQjD8F6BB0Wblgm9lJNc0h0VqxxD4DbRleKA==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nyrn0K+G4SU1wuMdE7DJlKWErX/N5nCqD3+dP+4ONmo8yuM983VHfjLhCoeQMbM26e49U4PPdXcDR\ny0rRemqJACoi5H5NvzXohhKZI9q+WKME4TkhFzfKvIwyta1m/uNSe/A0+52Dzbg5uAxYihw0IdZR\nZMywfa3deZ8IUMz3kWSlMs1P4wESz2pKpdYGs0FpvovucuNn4OhZKH7RGX8z8Zy4E9juZRgnSQnX\nmvRtisgVB9uL2J0vl9XjW/1990VYZi0nrZJ8gQL38HLTz62vDuMuYjiFbbnDCujJNKOCHh/xJTdt\n73nsz+dY3We4tQdnxuESibzLQLGF1l8+d9FPDA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nJPIGH1v6BG8bvo+3pHrWlum+XEDtFDlKP+4Toq88+g/eeinS/p8A0zMVVYj4wfjGDhx3kGvJ9XAx\ngxYpezvlgnz+IEGWQzepCMSp4iHz9TEdGkc5LTQj50VJj4+HGz2Qhrw96Hw0c+5RDrv238ILy3p7\nuzIPIzxKEl8D7gK6b8ZPrzx95KMPuGZyju4JUHBWdjDx0hhhIl+L3Ju/bVyWaWd7w1xI0mreJtAN\noOdcObOESJpTuj0KqFtfA3UY7v9n9Lj/I/vMaPX7LnSIZuS+tHyiD8D+t+Kf6XiIl3sYDL9erP7t\nSpHvPfG9bOfGRxM7dmsvKj+XqHeXg23wyS1Nfg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nrxmK0sxFw5opGoAsi+RHBRwE0wYNls8LL+oURMgLNuoRDOPNH7up4F86jASnrdlvXLShGHMZnaJ6\ny1orZ0uAZ6xxM2PeKAxvxBI02HOu0aXd/SMNxr16dADlCYK6R1DVdq3DC+T8bQTLWyyHr9r4m4En\nW5DcJ2hEs5b31PUg/DoCNTpHm2swT7sLG9qRkSfTddaSyGTADcvRXYjnHKHin6TQlOCZufWMm54P\nPJeCQmj1MjyycQGpsvFNX7VMxW49ashO7EGmRdy7lMGRoHDqLWBxcIlwAS4L28iuln/NdC/QV538\nQei7EbcqeUmfs07XP8FKxdA3hi3Aq2Upg9DkOw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64736)\n`pragma protect data_block\npJdOORWQloxSGvgvy0l4tBp1HqnYdonsYgNOe99SLH3qi9BP+2tNlaoelqmLJLSHNsBn3TJxXlZa\nnIZxc0/l2jA1h9Jz15QEEgUR0MqZaESeIPQdEbADnul6xUXY0J6g//n8Vnzph99nb1v9j4yp0I8W\nmF2Bvdz/qHJcUcV5zedPk5PkPVS8cmwYFQWer3rOMl6Or1E/YoHi9T9wfbgxxTs6yzqYqVGUBlz5\nAlhSoRF+xXB1Z4h2Ny4v4u05pGtbpnnDj+JhauZ7AfT+uRL3JZ7hNdSiI3coyNU077RtI/1VAmYO\npJoj/3tO2z4y9phvRShE/Otch4qxfx53IywqoRQmUF57yV4NjbkGPW8j7U6iQ8Ls1911ZAOgZIga\nmynl1jCs8ajbsNdraT0wfsPf1kWJOCuUGyItYv2eEwfh7iEYRrpT0V6YT5gENAgDuriQCZuFtnJE\ndhvImjwTXy3d76buWun43bM5pyUNSUzm90uucXHtbfsv8HZTM/chDluZJ4cMeW8D9Pwjtvo6lXLx\nYJM6v2cUpOTIMOcKDxrRTFomRQ1DwRsa4wQGal4q2dhrokLR6YNhu1ED6+AbEAN+FWui25yRPN2c\nRifAbYj3+oa+z6kUON22gegvkiRIe3iVn5MeyImok+P+5dmykiOW6L7J+GDFd4UZtYwJkwUH4ijt\ny9tlvkg7bhgKKY/VRht7EZFg6U4GjUBwLTEWIsD/6R8LgyENKTNO1FVyOJge9+hJYOxJpk93nMac\n0dR2cl0TLESIEfZQ8wSlqKcnzibNa/Mwa+gyj8uNmBtlGMv9GLnh914fnVrJPaJYjkLNLesy5uKF\nWOOHFhlsuqMHkybog57X/W2y+bzzdtaWoQ8/DU/QWGyTt3Vhlmu4YBKvv/DBB51RUj7naprx+CNR\nK7/l3uoheqcD/zy4ipVqZ/mSOTxjqNwJ88tpKUTD7UHuLf8rEeiu80iR1raYJGMHzUS7FcK/APPf\nbBCJIKpjoq1C63MJYurbOeqWcRL3DDPi/z3C66E9WG/nFKs7vMkhbVhClFUAjy+DwMCS7VjbvUvn\nCbr4m+kTXY7ipbBxU7YIDWHssBAAjeM1Rdxx9VvDqABN+rFZAA7C08PNPUeOiVYCFO3gmbAqYK8f\nEPeBaPUk6eskVX2sXw5/qrh1a5mqGk/sYCFZItuYZ6SMz1BFuaZz+ac8Feq8+d7gH2f1DuK4EG20\nOgLh0liUdRk5TCUZsSZTlhRd1FA4SqglWHYk+GIL1WEcVBskAEiY2YIK1TGXzUQaG00TT5TRBNmv\nsPnVI8z6bWwqXomyqcYSelXrfl2izqtjadlA+3+0O2A1XhL9tmMhT3v0nQIlobxn4nFE376czv08\n2+xLHI/chXlg2WvKMK3NCBbWGw7tnHSdJc47JRdiCkb0tIr9wocUbWPbM7W5G3Ku+bQZQXPM0lNy\nstFAjwukEDL4vbC72EJbEwf+6kzkzLjBrc0JDEzvjqnYQYiwloQ0qi9k/yE3bXcnEHvgw8ig5Y/S\nt9SttzL9mNMXwbouRg1seAZ89RrLrTNZiBk2TlhzdIfvWsbvdBYdIhaMqKRGJFpWxZgPm+JbW+09\nfF1z2nf/18EW+WziUuICezISE4+2HDfqFOEltKV6AdesQWDrloYiby+MezSSORPfWkx+nVGv8JEs\nI01podsuoWFRpVmbt/Dua5qZk9EOHGFBRgvYNnlH47YVREn5j8l2T/0bBlGUrv4r0tmSTvb5Rk62\nTtYvXt/3/jJe7TX05O4Uz8CDBe02LhhwyNkyyNYPm6hcqislaGMW5IrlUBR19xoKivY5xsi9WHEp\nOscK7GlXBFf+1ZdqPUIFBzo8CoanS+vY6N5dX/zhH9ka7wSGlru7qjqAyYG3VOzYi+lIUT1D0l0A\nhIuLJhQlgGIPioPMX5r9G+nJX9J1xhmQmslUobJCrtsIfoshA1m3sO8FVq/uKShEPK85uU48DmE1\nBM73G3APR/Pn3q4udJagFjB+ngJWARXqQX1U/fZdrs1d4U8E/KLlkVQywLtM4ImADW15ZRE2zwbt\n93vD21KzRF0gTEp32+Y94DZJmilvEITUz6i6Uf3GIhk/8VlW2sgoZBxyIXdlfZU0hAeWoF6z0y8i\nsz3YJBSL59bOXPeovsUY+1K4JWkThiLh9WlHMd3YfANHBPnf+imIQZm0bk8SniIn386MI5OOzHz4\nE4NRinoFBZ2QveSs8W7mDkgRcm6PoFPVY3QRUGVKM/cdavafi55CMHzsrvtIU+GTn9VIn3xNt55T\nvun82PwGiZ2FiwhlNlG8Wy4O+LFNA76IijNkkamPOoINY3NpvBlYJ4sMSw1dZ/S+Qd509gN+YqK/\njuugLi10dq5ezC717GDkCW4fL6XMF1BLctfTjFHbDnQePKJIiB57aUuvbzah60QCKQnwYsO2mNs3\nlX8Tl9YL68F88dwoxH0JclrQ/K+4uYuofKZNpcUqyesWLZ7Ajkjo1V/LWCNdqLb7jaE2Z0v+PGsJ\nbQ2zY2rbw1xVbkOFkWnJb00IZlS5AfKLW2JwtTjSc9R5cytj7Kj8rVyPRdWixjwHVXwb9oIhCtsZ\nr9zdlcsnNvnrEk8HWDJmg9t+Ss3qdeobuZBvC1qVhW9OeCSeLWFmmlBTM7zlf4bIM7BPobwINrOH\na+x81+t4Xk/8bAWK5b1pfO/q6usi0t9Z1NTJb3ix47MRkhAbStRfFBfBwzDQr/YBXixPzFiRd7RK\nKHM5pI4NGo4x/1eUa3I9iGFb0JwOlvTvmyLF4CY35sdztuKueaGq0YUi4X3SbBVUihPbcPvhcn3q\nULcb1JlytkOdtyHtyrm7/EOiSLmMn3uCPXQDioYj1f6NsIRA8BV+t4V5VK8a2hNJ+Ci6U9tBmG7R\n2AfVDNWXakk0eYIUYcZuIPVd4sH7Be8PANt6YH+bxeZtBfUel13RoATsMc/l+Vz7BvaZ9ZhPoxu0\nMpG5BKJTAuGZ3OqNXDuuvsvuBv8s5hC8JKvLoL76k+rFk8PlyNwEnYoc7nFhCrqDHeOr/8E3maxP\nPv/AiEhEzjU5PQBF457AHnjeQ3eTwpDPSnYJ6nuR0WhnaxbVcRDXmfQc5Pm+RgJOQXySVRlfAtO/\nJmM8oWf9Wd57qYf2P95KvohDPW6vlFW5UOuYJRNedw/Vofmtj6gUXmSUtZzX9x+pGUbZK1L7qaRH\n4Bl+RKLFFF3ULv72pe+uhZoyumhCUE9nTUfh/0bbyfQ0/7E4OjNceJy3IuQXZAelpm4/lyIClM6a\nbcA7XaiUNtUxRgOk+Gm4bXDK/lbpfHAo3ZLrOeIIrJSFdGgfIjMAMcPO2agXDXysM9w0LXX4XzKa\nAk5Ctu+YxqwaE3xbxVfqa3Xiwxzu9RezCh2I21Ysg1ckJugmX+s7525qUeaUizKlxcu5ef5xX40W\nh5pW3QA7UPCugDISw+aX406IO2drov2E5eUNDLRRG/nY7aG606JFGCFgUNVLl22BloATVP6ZeMDr\nmifoHBORyaJvgAndCrygYyJGcy9labne+Cqn0A1qtn323sFNB43FEMX42WIgtgc4oPab1AYsEQum\ns46nWTCUaZAyRO+53Dzben+MOJEy1iKP7o1PMZDKjaQ4Atrpot1Ix9OivbbWL8nNOjFG3rRgc8Tf\nLOVtiwqq/r+IiSB/HQOV/ZHmkDTL9dtw3UFvBE6wRo6XaWDbKDi/T7PaYAC3GGNaQZw3CTXVFb6P\nSvTMYdICAhD7YCZDr6aVLiD1Mgc225aXecHZoluSWOck9HO5ezjlCFCPDSTSj5OnC9v9zUcFbNOa\nri/TT7JdgqdBMKQjvpVrljLeuPPWvSxLMEar6iv8iFwj9w4fIGsSX5D1h0fx53Dosj7c99OjPOKJ\n43ciuUlKmUrl8zGTv1bTsvgQBspvbQjDlKlZcFGKkJ5y+h+FKT7sLG0T7X0OsNyJhlkV8Oh1B7s0\nnzc4JG92kvRVvDmVljLF5q7kSbo4pOg+r9MMh209JANj1imzsRTwNlFhL4KQmOy32YKv975WzfpE\n5gOHTY5gj/9beHVy72SphX1PvZ/GvMrFHu0Q1SdMOxiDJO/8Vv+UogST5Z+pm6YS50RKp917SJLr\npQGNrqMBt2q0TjdKoF10330Oq2OQnGbPQBcF5wAOKor3lUhuKlgi4yfTsE7g0RlphaWiUi0kfQnJ\nxJaR/v3zWkal8YKuqBUOk2zAI58JgLOCGfkeP4lLDigas6lR86dIFm2ehEwWiuUxA0rMWk7MxUFq\nIvlNP2JTSuRX5d7mSS5TdZoich5Z28tzuAxtmfX/HVgsAiDJsXeq2lNJnPI4t7OJcjw+/LTBFn4u\nGkaeVQKsrDg0XjypHHAcx3Htai3F8S3SrSZThLhmNA0UuPAVwrWM/YxdRJdPCFxRV9DIfFLc78ED\nrxRf+2hm2iIX0v9lJubvukxj3RKg3bWedHf9X7fBwzCzmT3xpSVT/orUQHTM7BJi1uX619EAPHfH\nEslFnO9xBhBE/NfxEOIr6puKJWQy0vcdu3KHp/98gdYKgnVg5mCXI4uGSJL+j3Mo34LyWj6jofG1\nRpvUjZOY2WsTY2U7akBl0Uyiv66vuAVFTYtHxbLeKihdYSSxteod2tWquqRvLeBirXL2qi69vijg\n+WXGPNEs1ioW+W6cjl9Kt1V92qIp1LbqTEC9jDdj5VHq36eM3zGGY1FX+VH47w4FoxWcrGaGXkXO\nhGXHGyLwe6ssZ273qYR1N0RhvtgHnAdUHIPdsqqRbjeld0f7uZDVEUjGCA5HvEPmaA4qaz1HEmEX\nMSbcEbGOwM4/lsTSso35cqWlqf9VepPPahniUNw1bY7j79iM/o0F8kJkfL5NumCR5VM7RsWuHT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C99kqfj/UVOTB5eheZdHy7EcqBeNR/+6GsibmPncbobTk24qcaqVJt3wgZyWp0s45X+9wMv8\naq7nxbvk+JD5cuPi785YB4Is1gg85t6bvpA9Qfzb3O9Wk32ecemuYY7hfv+wXPcCciMC61K8t1VJ\nDxofEz9Nxh0L6M2gdZhrIeECMYqp9YunMryNLeqc7YQLvKIjonC1l4sbrYWZ+Vr/tRAksYUVxldM\nWs7rdbIReyHwkW9Q3eVk5tGNZYwsTJZ3LLHqX4k4QW4fN5SrXF7tpu0Nh6B20X5kbA57dL9bI0Mg\ngdCKLlB0s2kqOmSFFGQ2qiGM4gLCtJKTcJvH0QXyq3PoTYgnvqWXAi7962ulHUUvjiqAbTLGRYQR\ngd6pRfridQ9QkVVZ3q8/Wwg9RSEsbZuIJ9bsY3KxRk+Bv/QJmfbw9otM2ufRS79SLoJDUzayREpA\nzPDRjhDoGxRqrI6rV3uPDIkmG/IgiRjrOM3CMltuf+l5zCRv72lm/BooJKYufHaSMAUyCUXJp/Uc\nFu0s9YVH+QVUDZtdn/t+XoUZ1zviEEgoAEoY2VYry4fCJ8DYaSDlP46tShiJjQrOJdERGgL/xQBx\nO6uzJrNrt7Cf6kh0YFyp6QRAfTkuf7kwETESQMUFV2MR8wr0hZHmd/UBOQiPTPb8DscsuSAYh8Zc\nrknuK0zKex9YiHkZeDo7D/PSeuh+WG2d2zJdkM3Td3eMS6WVDFMFl2b5W8/jYjNABrnjK1XwThFh\nYLnSLJi/Op7SthgN17FwYwSwj+AcsR63hVzcnfiVu3ZUXHEZJEyz2HWtWt0RLaZ7MNZccAta93yH\ngOMoJdpfeYUKCCFDGcTyJlFegiSY/R9BWXq/NR5ouF0kpaoEUa+kWjoHoOiSEaQs4XEhSuNjRynD\nrVhVZzcmzBTJAU/E9/o/Hq/uvAStcm39QbP3OeAuNYGNe3sCFCFik9NxiyTW3OEmJSjBcrOnO+Qw\nx7FcS9UJ/wQfURM4P12Z7osL0N6s5Am8NipjMtQyeAtwOcmnJoNC+0+NUiyPWlCuXP/3Z4arSgFa\nZR7xsOv//tsF4wlUna5iH3TC56YNk8nUsFEw6Ge6ZSuhEVsfIeY4wG2IxxjFm7GLEm+Qi2fnWvFp\nirwOxF+K+U92WcMWV9jGmnuJKdDgr9f0rTsSnyJoE6abD5qCwAUSiMOFTLyqf0omOu5SrdwPvxDF\ndftrQ5R+oqkHgkZje/QojcIA5MmPjkCLRdKv8Qe8et8c4lmY6vRi/j86jriaKSwx4Y+Mw85SnPR2\n2j1hg4L1bm3Y95mODLr49QGkDVB7kvY4Qy33Bsp2CTuOWo05KgZSEEXL/7U+fWGzRHjASwfcbgCg\niVFHnASo+4H+F8SItbh9vW9aZB7dvzb/sp41V3sOiSQ/lvFv36hNky3d5TPRgeWxk7ahEnAeBvcU\nN36JNzslIJ0QcFbUJcrGjbreKWGwtRudHbvZZiy3VBuJefbL+K/nA5GKYex5vaF8VvW2JtNaz6nG\nO2mf0K1OaIC26ble9NY9pYrqytCcdTpOisFBK/sWMwJTDavyPDcaK3b2r0z6l8yWe/+kZORkwM1n\n+vS+mBxXx0tf6GtBwKVn9Wq5PBEpboQb7z+jnDgqEVQGEQk44+zDxF6mTiYHaVCLhGP1x2L8Qxtw\nPkf1ixuZGNM5w3J6JjwoYA1WqjGzNXQ/2I4IFQ7+zOL2BVVm8a+5aGNvBOtcu4B12kHIJpqjtEJq\n3tU1eussVADMAsGVV8uDeYtJPvulbF/idSwsgG8crk6BAOKJo99VQxAzmHr6hzse35prsun1dsY+\ntbANM8RyL4weuRCRdH+gaMfEFjRTXyRtKzs19VCSRxpLGUewvAFPajZ9ighUQ2DOA7Kr/rcMTxxd\nrh6hpvfsAFBAQjLiKMsH8ZMXPqNGDBjA8s7TGxd1KmM66Kj1RfzFBtlBuz9LglC/dRn/arEJkYKW\ngOxCUP9SwP1tqpMfyCFKkHci/RYZqmjbNlLH12cl5zMhmsQpiIcZXYfQL8enrVutyHkc8Oplycxn\njTecEx2W4yyRww+b9SpNrQwNcQAZHfUmu5afg1rtbUHZmBW//Afpurxew4MlsTVbE/q+GW4sYS08\n5hT4/ITaA2T979WNydM1h2SItDPecKYro2NCBuNGPCj2smuGGwIqTTedt7kY0lTXqc1QprlIXDOv\n7A/WEW6Ks/DyDbzo5ebBQ9k/Or/ERzVfh5qWgkq8yG0qonueIlbVexyJM/7sKO/BjOR3x/FKDD5A\nPOch29mk1tOqyzjUVo2fdU4B2P5yIWUu4LyA1+iW0TzGEcAlb+9A3LJHWtdxf5XRYSDst39xRNq/\njlN38Ihbn61REmPKmA+LoB8LUMaREXZsyBT2mkJjbCqOmNANgzEAOIj9ceuS25Y2KtrSdejGBdIE\nvCBEfvsJHNzt4EujHKaeJh7o4NDjqLcdEp7ed4Ep3cSOHMCOA874EICbE2zaW5mDE8TG62+kJMaF\nV28mlwI5fMFxipXSTKgVDY4Vj5EWSGuC9St7IfruwsQ039cqwvbAOIuBDwEDSJc6lCmXs/qZhmZt\nnFv7j6yW+vhyh9F/M49mYXMIrZDI2IQn1meVK5DQbu4ISFnSDGJl+UGx+F0w292X7x/NZlrDFxjU\n8F8hH3SoFUjtp3cdqR6J0qgyyvNuJIK0pC2nq9IzjvH1k+PjKgFH3e23kG7suulbVb/rfU+4p0A0\nUw/8qfFdt9ZBcVINnpEPSUJScU20uwWwAzXtPblYceO4Nbetd/Rru6gMmzl4QBV6dHDFv9Llj35m\nrcJlg8L6gZdUkbc5dWUef9LywyJ3ifFwzOukFPVGj0p1G9hRSiNUqdgpYFlexuLPL30vERjJltwu\nf4LrTIZ2VSuuoDz3yvK7YYnre2MTp1IvJIRPF0FnWr5WUuDhARBzNlManehpegpS4ik+5bBOARnk\n2ikf25Ea+euX4IRwUJwiPzAGTUbPzL3cODFaJ4mHcPv972AeFd1T3djc/nkOpMRfzLbUHz1h++GZ\nfguK3eWFxgEnwvmTBOSV/2pqlydJB+j2kzDoBOhHJ7yMYPINzLTm+GvY8+PE6TGpMumpLB79DVsR\nwtH293Qaqs60uwABd29zk+xMrOUEivDU8FIBU3QFpa33/+/A4nI1MVfVSHknip/yEcpuNY2qPJsT\nYuN68cBSWDFeSQJE5yXwjpRVFkSAHd8nML/bKhBZiplgzijzI6AXJOmkqclzuE3gbvl06XzNvh5g\niwbchkuC2q85hHpT3w63G6WwlR9OlnKpzSBsWJI5MiFvl09L3irrYtbw529xtermE/blvOxQYxuJ\nA3+cCbwrhbuASE/lxx/+CQSXsAGEFsG+rJZf02gTem+flBUQWxgYw7USLAXlR/yGYO6KKUiU5mYp\nMcLp5SF0ptsnO4GjOAmsRzhq+nFaThfDeXAXowTEeuWN+d56AInospMZc/eW0bFPTbgOjid6z1Vd\n+9+s7tiYNg6b6j0iAwEiBa8LX50Gz1E8B8Xk0bA4iCfVG+pXzxngp/ZgDAxA6x4B4xS8JSzvBqG9\n3fF/tpaS1x0ZYZNKrC0vl9eX2oeN5I3CbgEuLOUU1xIlzEYHqt8Ta5ZEnYRUtbhiunpXdVyqirCN\n2dgXkldd9U31gMhMY7qFkzBGBtdUApeaRyAGLxKnyg+nwnmirKX9Y3rBKSd6L+R5qhO6n0UbbSzD\n+4en4Cmiy/ti0HItxFAe4vWNWKSwEzlKaZ2HLEPHIUlwN4xiAAyIeXLQP3SyqcvdMzkhMFVdQYhH\nM2F1yAOo3G/JqR2EjrPkiLCy80ya2Cey9fh2IrTFABUwl8LswS7gb3noQTWyDJTWhVsMOvXawU6k\n9W4Jitv0d/+g4QNb1K05p1NtcnLpsIbcTsGei35vIairYz2Wpukkc+QIjcnbRoRYwr386Jd+y7da\n3/zxTz0ylTc2RMTh2TEZRm4kwoCvMb5bRjiCs5p4VDLdB5NKcfMPq/J+LOvbN9BdKd2e8etvM1x9\nZ83qLpzhi7vatfxsU6M1tYzeP0N1fDEQPFerPkzA/sJJfcYa5H+94+uMTRANw63xIlLDhmnCm9fB\nvFsT1znWi0KNE5YxMVAP5Nj3aNk30viM/aEGcXN1+348mdh8cJXP6Se0n9M2ShPtIh6uOzHcNN4F\nXvgZxyI06BOFPCh6pPn8pM/4wkj6M+5Q3d37NGdAT8T8ei4zfuLUhoasw2cJjrdrZ3LNelT1XVzr\ngtfkU+onSthCPR4WS6Xrw7Ok/kkEQoYmkdI7UB9unluvVVQ764ldp5OlFSL6uGJlq53fikq1mMPd\nHtYt08ogxQnb+cC85LdLrpUdkov30YC0DE++eB3VOpsBoGUdgSzOw4L/wn+VuAsCWq5ABwRe4fqT\no7SyMEpq1RX0wDx7yvM1IrLxDdnN/w9pE9XQ1ww/ANlsQf3806Yc1bxBlnH0iwF7F5dr6ExWX02C\nm4GMD+POG+syw7glXgXQ0OUc8vp22qMR4sD57/Oul0voKncx2id8UccXB9vsMZIBhX8NK9iQyJK7\nYG53Y6spKPwBaJ+D6oCzIRdMrl47suvOHOFMlq9EgcKZSM8cW1EeM34Q9wneG+hmi1jxmgRg05WA\nNvs9ns0cBAUoExbeKaTDf+UdQg8kQpTj787x73pVcySGZAe6vE/iMHRuSiZo8GQ7v7UaVF9ntzDG\nTtrPWvFHyuV/SDdzax+LPSONzmqYuZtNNGc7rSFNjipVg81YgVclfSx1PGAIfydo7Z24e3Gz6NIU\nMwj2TtlQKBbeM3mx05abZdGgKr2KZg/G7mtpHcWqPBAwGoOynrpV4ZdlOI7jP3SkujjjiUQJ8FdQ\n9dU1KADRL9hr5MOS92p0+2CDZXdgK1l4EzeYC6fuN9IyAXHsqWhfswpOubjlkJfdxHP/GX3hjyHO\nUvlaWBcZDw7BAWM+AX28BwSssw+yc8sPIxzjHKVjNVz51Vpi6eQgVAZfgVeW/CVd4po9zDauDBPe\nLW3Ffrt6P9FU45qwQ7MWE7oZ3zsTc0evg2krhbb9dLqiCoz6VuCkphBd+BhX2nSPTl+BrGC3EtT8\naS6sDKIiJlBJL+8+GJ5RSEQoTGfqIs6ND98n26dELJI8S0uXSltTPxBhra5yloAd2F4/mmmPjyWr\nTQxaz9QC3JZaY5ciYNddoc6aIflLXGP2kZlT/V1zu+CW+BExE9WpMnVToGI8RRt4jv0a874Y0An6\nHhiPkeDYN6VUowNBrQ5rQnTkFaMpJk4oWUQE3v6avp7Y5alYEE4wCED+ItD2AgaKwC/nFgLMfAnZ\nktUhijy2X1yEewInb5S1xc28GWJeUEjeegaSJijHmFVUCwrnggKTZlbyJ2a2ezSse3QS7DNzMLsw\ns3lvV7VDvQazHXN8RAgvOB0B/CgfYjwZQnyysjBMCOEXr9ltmJw3ogG/vxGHBu667EeL5qOCFKZS\nK2yY/1setEN3lBeyWFiOt84crc97yyhIN9WLadvrh/f0YfzTa8/jZpqi6C6YM8s4vbQgQayL34x2\n47QkQV/JCgk47e027m4LJl2YsaOwIdm0CLnMgOgEGQPFdyZktwDaQcho9eG3wdeeDVrkyzQormhu\n9aXm2HxMwA7LFBoLoLMTe/h9G0EmWJjSZJbpYBym7mGdw7mGASxg/8DfPNQ061R+2X3xcnmG+cIO\nvl0+UTTis+WrgnTXMMvcqbanhkRzuTaNKehiSLRg6bGYM0soIp56mfxn+lCOLxRvrFVCb4SESUTQ\nh41pLzHt1noaHrzs6Gg5F6h/f/xdaHC5qixpm+GAiRp0dMj0xX0roGySULb0Pg5Ik9k6Txub6XiO\nZgO5zmj4Zg5w8I0AnXTXRWRQrHzuRzUxeqeeMsb/JspTSY5oZj06H3vlmxUcBhypLvXrMLcXh/Ls\nc3bNxQvpWzLBqqdhy2tGJ8fAWkun0YPhNwlUU8lBB4Gk06kgUQm222XRVdAheeWAjR8NbiAop06S\n8Wy+XiAj+daeCKkiouMukARqbllP0jcynVe076LG+ZgkcNqoPU37HDyH9n2pGf6ZkAQuwFeIbkSF\nPg4iQ36vkP+KaDnRItQq5Ii+DKzEOXGkFXjeyB2kGs1noDV9eD6DHXsQa0azeB+0c9fKSA7nV4Mx\n1BtiwRMnJT7JPQOciedKCuaoP0Aq+hvnG6MBlo+nAOOlQfvZ8qQxlg0laf4f6XLVWOpAeGt6y0pr\nAw0YlMDiAyvjsrh3t8P4eyWaZSoFPRIJLol9+5QCyrLlm2aVeoMUtwJ1/53pTKnTEHcZIZfi1n7e\npjP+HdzVIccamu4mef1McNibQT4nUfu60LdH+ZQICzwZKDu6slLfWc1KaTXs71UCJzmFmBNREiS2\nXy7c04shnL9MVkGQUM4rVvlqeU7hjpj2FNlt0nq2A7NHDHkEArM25UeIzO+An0jC3tn+qfMDBZmx\npl24RVKkzC2NhWcwhhc3TGrk1gzXt5aE3zkSTGv9pEL/s8V0XrlWQBLq2XFeBXgLpSAzseg2st1r\n71IH25LcYi65u03YZ8TaQSNK5ZQxrVBVO+JVdqF5H+UcYmJxyBsmvTOso+y/z+nGXXnu6Wxeb2K3\nPMCSNT7G7TIbSFmkl2cSMzEeMwmt7AyMdckkJzv6cvcC0j0fLIcJ+ygBucF6mrNY7OMFKMatX0PI\n4UdpryZPtTB7sdMGLH8FqHkw0PoHM+53+V3rRDIo+ImSU7g97SHk4uMmW9/lU3+h4QEVhf1SsCoH\nD9SCjVbJmWSx+5ck3SWahLdUTGE0c66fdQ50VOj3xxA9nvsgL6x8+drW1LZr6SHG4Ma07PvqbId/\ncOHrnVi5FevEja28niNJV/635eMPcCA8uWcnSyTm1J3Fe+CyROmWWUPs1QOJLqlM/Ai2tsSCIaui\nrBVtakmXqv0aMhA33NdtZu3vrog0aJfleoLXQUuDYIGcGc8kfavMyQBG72eZnrVz6/tupr3lLY4Q\nxVGFP4Jxgxq1oFD+d8nf2DrnUh9AyNvtyyOCKi7z+ReLuwDg4jFzd3U9eZQ7WTDxuOYKmerT5+UO\nG4qs6dNLomx30eVvW25a2Z2qtWBywQq/MaVipSr2RmdVavfkdvSb4lRU8c/OXc2j2EjLF9uwD9ij\nR+SremaAbHZZKoNbBX79rPCGwHPTuu2e/3veCG7t4yv5s3WUvVkFPocYD2rO92YBt3DE5NjJ8kgM\nBCj48v+cPe2x069u+Nco6d7scSnHpPHHPSM+6Py5/LgYVagzcTfjK8PlJARVcAMsLJiBvfzpO+zb\na4Rs26CnEdvlCgaKBV1YLeJ2dXWhGAXTQg7SIPEe+qxZanakqfbbb2xT8QLylB2wpP6fAVc2MhM7\n8GAoec89XNo9PAPakTkcl0WxeigJFRkS527gXqWbZigV+8fVkzfLL8ARih7A5Y8faOuGrHTI1D3/\nzLMHy7/g+ESSQUAfGIeRgrKCYK7EMouPFRuxC5uxAYpm5W/pKsdIPrBHWTqvC0PZClvqzFXBi97p\n9keo4Q8i5+/jCqoMSKdh43uf/t7GW8Dcg5wWxhGnjWC7PMUgwEzMeruqNa0zB76K0zeUaOmh69WT\nQE+NgpCq0rrPFoR4W/hxQ5lqPWMYVQs08oixXrdi4qxOlpMbrxoLJ9dbreMCg21g+h8idnl0Tl1L\ntZ5uVIyA0sfNcXr37h71rInz9wjZ2D+cn1MJf9A+S9uhwm3BGTz/4NlrrXLFirxI7VfKkYEQ5kS9\nUmJtizU6dQ6Ehg6JDdHxuh5l52FvU7VuMVMozDJdJMvbkeQHAh3I0RSRxjaUk9t20AqO38NUWado\ngkUnSoEZCLnKpWk0YPx/LgMwFeFUGPMwCcZ+o4LM/G/XVGe5eO/pecve0eHmEnfeVBoIeGUVNgM+\np5FXp1hflAYwWYzb3FqUrZM6TMi1jBAtwoA8RkCsrYN61H3rOO2e29xzDffAshtKB1dXBUfI0Zxp\nVN8o0s2S0sIOL0Z6Y2+38Wn6hSTm9pUH+2vQjPt5mmWo7cg22+s7MbGkZISOJNCM1mCrD3s08ZAJ\nwSe0IXxQ9GoXKl71fWfyxDOEN80E97kYHfLwT/anINNK4DYOqinZPKwL6lPcmfztT/jkkYeC47vc\n2LKundEqdpIO8cT/NlrAVtDH6t3Fm9VABN/HIsAxIiNvOpHUSrLSF1keYvjZzNPJ5FRQgPns+eTv\nGP8JvC15MCNYsPYO03i0V8tim0p2g1ZGaidN0DRZ+8QURKlhGPX747Npc+Sns6GK2hOpqQs5xmC/\nkg05svfxeKyBc+mnkDT3BuW6tl06gkPpjvfgTxknS3UtGnjHnLRzXmIjQMl2IQ0m0gzzccVzi/72\niZtemsxeuumi+UP3MrCWaN+wN9xfBDV49pifJbqDeSGoznX/Zcb2XT9kvtBFWMmlBG27ZlbXviyw\nPnR21Qdpe9Ga3f0oQjJGGlKrEtk8kpZXg8bTyYQAlP0cxQpKZU2EjD5JPPrHfj1jG8shz+Fu/9Ho\nMoczpTM2n3rQNUp7R8v0cHO6ikm9/A1cUv3WjysTiu7SuCs4gBkotSNY2Xk68SXZWzYgFxmK8HXy\ntx9sdKEH13yEbULEXA+4COwl/PywoPj/Nl+Ew4Pwcm3TnoqS0GSPt7HJPOo2hoOxxqB08tPM+X0t\nB9E3nmeN6WGtdPk5mkipZRl6B32i/Zgg+ya/eRdCQdf9fg9Wyl1aioGzWlZgA8sH0At8Y7gl7NYv\nGsBJKYY9eIu3oVdG89uBhlUj0AOPcTOGIyt2OwESMxURJPXjak9Yh0eSBLOasPf3rxt91kWGROIx\njBiT8eMt0OnS2yu5HO2Eg40cmIqsC2vwtJoj9wOdu3zeceXfhMsdMoEsk85U9XUNedzDXBDY+d/K\ni529zO4iKsBwTRgnL3+Qq6lgmFdlFvr4PT7x/PusFTxAe30moNx7vtlthoDXjY69raOtJEVg3oac\nlEa+QrsLiy6szONetja8Xwm35OWq22kBLLd/fhaSvhSgxFNpHlINTa+dJ4OHbZshSM479f3oy6Gw\n36CHvvAUHpTmQiWWOqNmmUHHHnMRxvyySNkV7J8hlPk547mUpXPDCAheNrbQCq7Zg9QcaiQWd9qJ\ngnrFkLP+BjGxkvJwrV+1jUS4ymZ8io4U0EOc64Tuk3B2OXy4e8bHbNs90VoNbogNJ2JBBrluJx1L\nQ4+/oI2p1bd9BrWyi9lb2v+KL4o85RzAFnSU5vGSjrIx3lm/ZH/QN8/90o4qJsXwnwzwywuIEieB\nDYWlvqUtcnk46xKGSj9rr/PSTZBd7gFkW0W3nLbd5MKKjVDxtdiKjSV30e6iwgDQZ5rKvLaEPVul\npiJd8wgHGnnZRT6oMODzea5SMDG1Mx/Uu8SQZWcFTOb11D7MmcZD74Dh6kGsUS+qfY/P6LK5ZyoN\nHNMkZtEiQINbI3DG2LexnjcnXgKqZm2ZXGavRz/1f3A+4d4Rw6KoWfXIZOVUdNn/l4FxU3xw44SI\noKl1tT8NUagrB/gafvUWFBenLnxPxW0TaqMp+/lnAdDvwHLTwf2p56K21HxTlxXAb2QmgQlZB6bU\nDuYRjWtw96PcNIcEhaffTdNRFC37g/+Rw8qIWX4+euwL7s7q0kxKR4/TG/OfLrnBR/5+jgJGxj+u\ndtyDwjwrtChjTru6KPXODLvAm97PhZ8NRtb2Yzn5a9LjbWYSBpxjf4eyfAdYjEw9yPbjJpi9AJAW\nmwhWv/9b5rkxkeCEr4yQ7tXZTLx9l9hQktow08Zlh6pE4/8M86ah/0BFrTA8TwV1MQM9W2oncjGH\n+9q2b04TNO3wbncrECEi4DtBvtfYup7Ewyn3GlaO5eYLTg2/jiNmLP8fy893XZvRFmwsQRwnyXCo\n2nYZv3H6iAokmm54kiA8wDeKeZH5bMVRb8coUhzn+OdVrFqyf8myg0lyTJzy+bzzY4Pah1/xh3/L\nbI1bdfdg2OoVS3n1aXMOJQSoBQzk8F4lkSgV14x0kEgcg+6I2cD6IG6bQHCLflY17NMmKnX7MQeQ\n9ARoZL9Ftb6h6jt+Yj9TqigvDbbli6iYyt/3iLvMaE7nKbkI+BcyGR8FeD5rz5Sukk8W6WTDkgsD\nYzu0DTmAkRvyAwCKiwy6bzCh4dzKWJOK4GMV+psXZepr0io43Re5pRIkbdTsNzCzimW21WR9ePZ8\noWGZGUVoCCHkoM+VhFyZgrFBCuEGtlTrL1OhJnn8G/vmj6GzP7ppzjqtQOJdd1NT3mIJtM2MU2jK\nSJ1bL9b1YgSVmGnENvIHBs2oDoiFeYB/AdsDKbam8Ofe08wTbM09FVlDEjl4Kvym/+mlqBqdjB8W\nBTlVuLz1Npwe2Rqin9pAfmf2mro+7Q+P1t2MkMMBq7+mNXk6t7f1EZ9CP//mfVK5vfUlm1bJwc7h\n7zjymmmA2J7MYyTiTZCFm7zKpr2m0yARdirGbh5+XEerjM0JG1JFcunC/BfW4EJW+aPNSQhpCcmS\ntpvSqc1TiSkWDACL+Kld4mtOaUOVAjJ4IPoOKrJtnDz5EYLStpqmXsohKLCt+sy9YZ7t7NEdk0SI\n+i8nrAQsijEAoguMLC2r4fcfepagdfAzf18AS3Z8t8vItfUFlgvlByAWPD0pAxEeL6gRPo34mHvp\nqtb02SaAbEWUaCCZNhoIT+MAPCCwxxu6OEN9VW7YQw/hmrD4e4GyB19xhrNtuyh4zHoN+FX72opr\nxOkXzzghtXGGsQ2q3/6cNaNiE7P1xigeetIkjYaEOogeiEI0BuF1fbJDaLfReX9e6jXiLvhJ5AQe\ngiPAl3g0FjDUcmDqjRteAhE/PNHfoJUSgu55pPfO0NY2t2Z2Ye8DF9v/uGaVuFA1bhi9O6ZJfE0V\ndCrNoO9JVtPWadZbKqRoRYR64EhOYf8QMWXpQea8J6pNasP5XG62E3mNJmZhsEhO8da14ofQAFnr\nuw1npXWWvVGW2OGong7N2Kwh7SRpeKL+2tVeUM5oyRkkegprU8oY6yDTmkgW4gzR3iUD9r2yEQQR\nEUrnBqjowX6/a2UbkSvengDsfeYrIn57XZhpweU0dH5uBYP5FkquBKbngRzDWRIhRjpZOeNBuquj\nX6fJiQEmJedr3pyKIPHyXEepzbIAgL5Wuhzk/LNljrsUkTz1/vK9wk75QbxTXjCCi0MlhBUnf0Rn\nT9gWptFSKOOspcWHZzz1bR3qAF6yX2iGIpC7CBqaPPjOSnOIr1Qhts3FByUz2W7IrG7VFIApG2Qr\nZEpY3450S8oEjLqImCdG2XYabHF3KyViSlBMveVAn1qZGku+UFjoqKXKLREhng3hLqooi6ugvH3F\nhLD0lteBKSVsoGT5MDZ10f0FHDYuDu8pt7Yx+avdWuF0XQUqscn1y0GeYS5kr86t+F4ToSMW3ovR\nH9BqBMW/e94nritukUh+pUU2ENfgPglvuqcA55FabulEONPo2iV/4CdTcW3iZD/sNsGF1UHqf12a\nGB0N+vCYNuUpx9LspYpJWTeHOQslPRs7vWN8S54MBEJuS2EKLe8/vgESL+G2BnW7yrnXdPGpYRi7\nantqD/KGvHSTv4C2mNcnINFPsx4e4JPlmwJwsIHL8ez4LDfzGkbQo3znuwcl1FgqMpr/rZfAbjGd\nJnMlIYAo47jNmAfLXWB+SdpPEJgdYuuRi2GQKLWkI8JUR+/CMdKDssgcEyaJyvWOzURvv1hQUUs8\nPkMdKt81i7zFYQjiItlszd2C8zczwlH0eWE2I/wYLwBYMkRn868QftUBc7WCXFXvjBndT65IzaLk\ntS+XJHy1Fk4Cnnkwhr5UiOJVKXMm45H5EKxjwXZ8si08tIgWT/TPY7OcTvYc4EdO5sqbIrOIlxcJ\nA9IOjMcJqGbEoWMAtk2ASak4RNiXlg1zb+mt4fLZDqvemjQOEytIdpDjsKXex4b1kwug4wZmGlki\n8NSMfJNHvGf+G1NZ/qm5S3ZV2kDMvsq1CbBFSw/PxZ+mi7bChotalY0y4uMUAOBSP9kunqJAUrMn\nS2uohKVUiU917LWN5sndUR/DPUfV8pwKaCkdxF5wwUhxZriym4suG9nSYCjgTo7RtHPM8zJ6jadr\nTOy4MQeh/41kZsJ/XYpc5ElRTokVajxpABDhLz+d8fs3DQLWhTQ7dAQFzaxKEHPQYD5+qYLkSURA\n9WeBKvZqJTRRibHc4nbOfxRMxaQc+EAAjELMdOKS89L0XejFvCUujsz2fzQBJkpDyfKoXWLRko92\npzHpWTlhRDA9s5b8PX/AR77wA5ArUGNjqLmVzA1pp9zbxZdgpjqCLi9BNmyv/dg2HOuQs4tgw0Wa\nhIkwx7jfZ3N+FEnXqMihEhWujWBIpFVWJJg9UJ8Cj597k6j613fhjn+fQC3KCwnC2yGWi5ohm/8M\nSpdCBPF0n3F7iEKeRYOe9LRZGXKsa7cPF1dK3NOLqS9L8s/I5RGmzzYpuJX9J3AdnFkFX+eNJqg0\nKMrTPSxtaHUEe+by0YZm0zlcR9t+oiatQXde6yVVzmFWgcmsoz/fDx/AOOCTGxthX7cLvkDnRut2\nzdGY+x0SPOUVq9Up20+HVCHHJVdvlDHnRcwiopLP9EVVJJ3+8+zXcRwdR/W0qU3e3tjHMQeLcQKh\nJEXrK+Byiw8OmW0QMfzy1sWD0q0/sbMxlvt4eq0rHv2LvmpDayo5mQXKasNBMKdsSCFzmjkeVXkL\nx6lrIBNQrnRK3F9WHeo1St/Vlx7gKX61STdUZx3s6I2o9Fu5kQ/n87oY5kGnfIYy/Sqe7poccG8s\nnwtvT0W1l8YAgjLp+y4ttwVZN1u2Tib7vNpCGWTeUR4N4HZlfTWLkfxHA9E6qHgLyLhFdQxD5MjF\nzFCW5kFcsPysIWupF6wd+bHTvxMd9+e6km+LqJvwX9TJm0/Tuhv5smOEetrL85LZL4hoOD3gkOD9\nux8mkIV156Zn5qAXgRhGCBzTAoc3gdEEAZuM9CMnvGFt7nYQqUWozJbVNIu84YUuW9UaohW0MdBq\n9OmTNAp1jaYXjqH+ZcW4yCPJEkJKLw97SJqnlj0ts5ypvSx0AsRbwVqIUkBHIRTEuqdwXy7ffZPz\nSuwzY87QGmpoKvLB/NF/8a/XOC/8ekWrTlyNU7kOVZdUUan4xgg+rmtb5dxRQOg2+Cg5yB2KYpFZ\nGLIJEaN5ePx6OuNsKyGAnoL8VB4CVbYL2YhLksaWv9aVH0MSEQBH+d+Hhh/hyb08on14QDQ3IPn5\nPOfH37BX1Kt4ZT9FhH9AqYK9+IYyvlY1QZqMYqku6WF19aB5M1k1mnxoD9qP2OCDsvW0PulTcPwe\nbZWzXBB+yCTURvqwPmCCGg7Botgo7UemIA/YDo6uZQhRsrlLBqrNEpQRRJvwcCZadPmql+bxVLoB\nHRd0slNjme8ocHNUYblDKhFKIO4zGW4vkVS2xu86jFCJP+AUtWtEoBbRuFb6se1EPWSEZccg/tdG\n3S+yZwJXmSQIKiocBNNsoQl0ZuYObaHJFh/ghdUlIm9QpTkoUQwAdD6P2fVXHsUxXitYILj9Eao4\nnl7koAUxv+egJe38T+XzWu3qJvZlze2xvOmAAXEjVQQfE0DmYJfZVFKcDVdg5jYqF8G8FxSmQcxC\ntIn4gkrqg6EV87gisbn7qspi0sacZ6Q/1gQAURtDxooDDK5gsV0NEhI7EyoinLXjZJ9SY84+Bzcw\n+VD19FvREqBGtziYVyJ2+YAO9kUgWbuDuEy3aFnNOeTv9ze33bOAoAhBDtbJ4BJZt+eGcbWYWlP0\npMcWI4mKtcX18daNTCZR+LgCAw6J/bR3KiArm9ML52M7oEzMMSX7skvxyTaIj1zojGgXeZXvki/H\ntGHQauTSObrzhFf+YE5t50078XpPzdQQVhn63OgOKp+6Rie0Q2OZJJP1G9PXiAViKajwJ0U6IoUK\nVG0LJhSYwAOF+ditODWEnyYQJx6u4HFg1/OYPbRRf5SL0HEyB2SOhxzRc+QylENCwbGWxkJ/MjpF\nucxP9yehbXSUmmAXr6u8e0PlT+0MEcL5+hML6XanaR4sMnepTVUB5OQKCOhz5bVdYkfJf/AZhI5u\n1tj4AjxaqRwn5RhHqqcjspa9oAXyD6fTTd6VkJtf79obE2Vn0/CkZx5Gc/vEV6Y/UUsQa0+HNWxC\n0KxJ/LqbD+0Xo9hk30nIOWumBfNHVFNABhSH0FO6hXe1h7DRvhESnhSo7kGWpv0N7/A4SIRMybQt\nC3MeWIdBm09lya/sOlRRHwnjh6BgZeBEtPqYX++mSFDadrZ5912qAYsGsdIFlk7+p6xospuH+IyQ\n1PP4r9wg6I1iF+wSIukIJgfswFgAGBtqgDHhfMaea99tCTbBODCxTlvVOkbfZwEcdfqDQJioj+nY\nkY//DSMVhLeq/3yvLCdiembO06ynPh1byTgwmALsU/RT7uf5DrZBontbQhHqEaFGqtf8irH9r7Cg\nJC23F1/SWnAd16dLnUjiqbXwbIoLMHbD3pnqvbyyqy7FNroWPX4qTHJMm5LbSMWNMGR/l4ucWMxV\nky/QnNMEU4wvxoK1RI+mCtU7cdIjq7I9Jx8vXkCdnLnAXFb9QNHosk8LwZfmibS/xe8bBW7lTtzc\ndbpZwB90QL9ATHHTbwX997qQwU6f8Q6ZjTVx8VzS23VGBt3KmFvGycKB6dmPyzvkFWiQW+Cs8bpN\nvwr1sTQF8HierHVZSIDcGGnQ2RcE9sHY9ywA2gug29YJOrasaChUvfzGHMkvgAeWBLoNN45Ptoq1\nHNYIOiNBDDt8b2NxtHOlftvoV+KQTNTItY8HuSuvucGLRFZ/ijxZMp7Gka8hw0omBjJ3K/Canqk0\np/nI+kfZ/ww8PnWSkJCV3iTei8yb9akSyGPtimN3DRXg+nm9F1vhe6ZjwvfxYdXsR9RM2YFddDJj\nPJ/7sbG2ySqr5AI3utiP/mJsP9zsIUtciEXpzIiY17AGEzEf9WZc01mBXJheccBxjLpk2hOmp7DW\n/bolFGQo1u0HwOCjvUQEN/VnOXBf9dUC8dHNpljvbvcpY97VkVLl1hhLXJ1B6CZ5pcmV49ukA2yP\nHUvkv0kKuJDG2kjj4LUJ5YXaAGBdch2MCw/ET+X9R1Lbz7Tm0oYfP/vj2oQjxfHEux6lD/Urc2oI\n1tAqwKd6r/F2M/RmthYfXTEpVDUbiw91v8Sh4I0wwtXOQr1qrn4qwtP90lOT+tlF2M8TKR+rerOz\n/5Xgv0CCYjY7xCg4tuF//w6fpvgs0Xp8n+/+RRHW9SZuYLcjNkECku4X/bNTWgMoAfJIJLIPFZEg\nKFFHSa7PwlQqsQtO7f3M30QtV+S6oPKAnAqXuAd8gNhhlzMJ4O71NOrGSrsYdqyKFMu1pulAegSk\nQZ+uiKAj5kh/P0Ce6xKJQVPByIdBLuUdKWrNSvLdkjayB5YrzBXr2uR8Z3qtXmVTRrfhblbKcmVx\nbSlQCkpVPIWCxkOIc1vH7QfvkHgkz0Vh1O4Br6JIiEDbSD3WhYk8pT3YrbNfBhL9XWekVTilmC+E\ncoRGgWwOOnLGcaI7bxVfNZzqrCajMQSnYQUipkO9bAkBHiMkdegZfmnOCpQgUhIRZAmdKCA5IYZs\nhcQolXWCTRNRgfH7AkKeeObiP8KDY1vJ1LZx2YPiRrfGHoQeAVKnpo5Q+XF4nsb5FDWlbSF9WK4x\n3r2tGTKoamdzjbn2uks7TO7uFcTC1hsh2iFiECPnECYbt25QcuA6GhkCaQDMVCRlC72dzdy8cM0X\nNLgdEMCfAuh/pfO5Soab4eZFkdYi0lUKw2JYfFUm0MsvAYUhYEY0Hv6jh5aRNCEz+5cuDw7ufd7P\nmvD82HTyuLstpgQVz9MqL2IrFX7zOwsr4Iki/sE9jhAIqK6UNb2lrwHuhRS6OETJDguQycwqveDU\ni5P15/S9l0xzS0bAffASHIiHDS/nna1mXJMzNA92v5SHt6iND+4NgaspRFj5McYl13C+pzciz3D4\nX0zSkKlDQTpJZAjzqyduOgXcU5sROz6raPi+V12shPmKE5aTU+nt5baf0/qBBo47q2UjQMY75tMF\nRVal05IPRf/HOpHBowN7F02gfVE7H44F4ERDK/Hq1xEtrOFK7H2U3ec851+lya2zTCJR/Xcf3VBe\nlxb4RN1NWaePQkEcv/YWnNpQx+wtJntRzhd2+4ZsxawcWl10ffFyNr4ZHupqLvX7v4I/hqx48thY\niV2fchI4tKi54R4OpsCf7NZMQeEvUspEGjrcQxpHVgtMx1vXC3/lApBlX1jOD1aTwr7ThB9FbEPp\nc37PFCi99PpLZuExy4twaIUSOK+4IOfnhrNzP4+bb4TObcMe1gbmAED5+fDlwoMUWWRMMzWsyN/A\n1xIrOrM7zcDWgLZLcIOfS0spfbW4l41PKSCbIcNrB3jFSBrcwm0pQbneAUYkURTiw0Js/NskmPQ1\nqg+UnXhDdicyH0Wfn4tVGjaPXG+qMWBP4Fx3Z4tA7m0jIrR68Ao8aX+cbhBeS0kMS/j246amm0/s\nCXDiO60Fcdr+vOQpO10O+LjBwZ5qsiJnpnjeaJqXT+Et9/jkV5Fjp1xJ3EnlachHDM//79eNvK8/\n/JKOSm4wMLqBigZLP0jzbtnwgaUT77pjjr7T1mI5GQzeY3nuBOxgyscRlg6qA+96hZ+yXXtVArTR\nnf8MO1ycpLPgEkAEsRETTvNnDrfQAd3EFl4I5oisHtpNwuZC9DBflnl5hDZaZW8INJHxcaYffeOA\nI4SZqRyHEDisnaRsUSDIwcwj+tUhOyJyOMFqPYPu3W8unFFJc5VDswkGf2v1azZ9sqH/+QC2r1+q\nvmU/p4fmXXsNumWv6mJCHSInANf3xj65XGYYVUADHApABy4FLykn1IX80gOG/DkB8tArpTRIvOnL\nymsyFKe7bYMu0tUnlo2TPt/h8MeCWZiDdodmrMWa35AxrWLyT0U3n0ZtHC6/Vdt/e3T6oziJ/eVg\nlSZVzkrl/F5IvDwa6bvb6U0s/exSaMcTOHYms2e8B986/g+KZ9CjNQx8CSaf/8NGvuVEXtnONlx3\nLAWQZyLkf9AlRhWJk8otSYNkhQ30sHgRnkTwxaL/hxEClk6MEI+Z5UJt9ycXKODHuULHepLOcPZ6\n14Qufb3ZpVjOTbYmikm1m0IX3bCoKrUhj9oXXboV9woaTYxH8fx08ABGoDz1wA4F8VMn3QUY+F4A\nsb8WtvEmh+XEuRlB1edUNrN8WEkKjj3TwLKejJhrheVTvDZR3LGzRN5p/Fiz3f35bZUALgirF+Xu\npJhpoFYB7CAMH8og/F+Jlma38Ms96J/JN2SLV6bxpjWe5s/aAFb/m5T2WMr6f/Fi+hR3bYw2ANUU\nuDrYb3BZizZl8oAm3Y8N/HtMXtiLLPo1FuXhV/I/dqimr5RkGNYv2vmFyIRzlTWvf1OoQdCpp/8e\njsVRC2nOL5aja1Gbrsb6xLI7v7zOy3OXXnL3A+5G/aRzJIi6OYRIU9iBmF4cPrBOeljwsiThjyIo\nKFFxbCwY3TLsY5DzxbRnwXg5/kBxZOaES7X3X+zHI5eyla9CnQbfH3EUEvY3EV/37+8QTasY1tOI\ny905e4+8SABe51gkubKLjrhy29UKH7O2fYpuytamltn64Cdq4NhqTcnJzHCqZsFlQR2d3NCt85uw\nAMhm34FtpsIt7/67XzcvPhzNtotKCiLKN/Cgm6WqDNXxXQdqWBpk2t0ruAhp3IlUhukD3Wg+LyXf\n/ZO143HqZM09ejrB30WW0BvJbccuf5qb0GgBxnj7M/eDXJJPxea5jNDgIz5AJ0m2xwLDSCHWb2Wv\n2gTrQlIYnhFqNF51eS9oTQcHL1NUd8J5WhoKC/tnFnYhqZPSXTiC1F8H3rMUITUwIwR4Eq5f/SMy\n9vvjUuHFbAre0sYO884yH76/735dC/HbyF81vbM7uEaXpOBXKXUyFJwP5E5GfEcWXmllf5c8aS/0\nX1aavdNjFTbB38PKSNPR7vE4GYr8QZDsjsYzycp5vB/F1X1R55r1oHlKyB4lyggTZMjolN7L0+/K\nh0SaDpL1hBSp0datucCgpkHAK1ECDvvnZz/EYs4aUJdU/3zroy9RYIfB24/4jNs5h5aCBTMkmeiR\nAMIDLVnyEReJ7oVzZ6u1b6EZKmUGyoE/NAWcRmSPjTUJgrzF4ERtajmDO5hzZdyTOkti/h4tFdJl\nsaYMNAKg0w+186Fz7c25LLBkit7BG/wjrAPz2cW6JI3S4ru5pGGi85VQsoeLOW80nnosEnFDip+V\nJ7aDxGq9BSwM50DlrWdIxbvLObiVnLR8Ar9HAyYTzspjd0FPpeLqQVnWy9kn6nIT5CqukkpCwcLo\nSlct2bLxTcQhrwQucx5/LHBYpKkrp7rrzkHZ6P+cTUcLHJNyJPZkZK3heV/f0OcEsM4EKLZpD0g1\nJv8wATCKBeecm7/VqyQllTUUWvP69Owt0G4XzttdIBz8DTPtaI6ts0hlmbOkcDTTvBf5mZ3rNmnw\nlg1mysjyO/US6Fuiq9t9+3Xofstc4bHEm4YBjGCH1IHTDzvQccKfnM/cqleRvo7H5eXiFsZtPp1G\n6GOcsXHa95RzZj79MoKZNjnpEY+t8YauJ+ETl9KG2HPb5yLpP6Q6cV2HTp5GNHhvtcCoWQBAiqHO\nbxr7/HrkWj51SqQJe0KV/R6u46GvpDHfkVkDlouZTZy9uiFGVIo58fKeM3Te6Crcktg/2o5vSjkO\na7Z8yu/uzD4/L9K5yC9W0SCtqS8uulGQZpEHMWNlzCWY+pOvRSTSp73IL0EUO6DI/7fF2UjEWTyP\nl7qk/O9HvnOrrWAV5MLHT2Axk1W7H5akhnhcPAA7Lx/Q/Q5iLoPNHVWxjlvlwLlwWq9OaQICR4jq\nGDNMi14HM8VyANmSUU50AAoSn5ABDzSXJ9eUaJT/oU+O6OyAckpg07u/yYW4BkTMw8xIioyNOSqn\nvyJ7cBAB7X6KOj/KjRLLt2J94Qj6UBECe8x1PJ+/oKc1U5SNGmaDsiJPYE42OuvkHxD9CXzez4zx\nMiigISEAWNHfQrcy73vctjtz9y0ieOjN163Or2pLp5RE+4EnBTO68tZ7DiFsYAvgyApEJfTwTzS/\nH+NfjaRftQPoB23DSbd4otwB9wqCTcgyKeHfwrA2tWNoBnRRDh43MiB/X3InWXASYwMqfd2bTAXB\nO2ZNmuvDjFCqHdc6XOPqtha0OlB3JmvtCjQqmRjfwBDEg9nRrUo5OrhjinJ1ZZwsA6X9Oc2M1jUP\nlgQgjlV0P/hsZqt/GDjLt30k3e6DvQg5Ye+Kvn8MkqXne8Omnj4K3lzvEKXPYgWrAr6+t3IuGKRO\nr/774W4XqSnQXDXYSsPlm5VAGXmAqncVo5ekdQw9di1hmya76/G8VcN4QK0J/Q5c7xhsRvZUhBbD\naoZnX74rF3GIzaxID8PujDrYDMP2QkRZijphPCywc/l0jsldhR2NB4RW/kYPN3uUqK75cVesEaL5\n5v/AR9/c4p8tdoJRCWfRRBN5m9RRDQl3XFMUCUPifDExugkQfos7EIKRGrXely/Hf1bqQd84KBHw\nQgmROHDt2QlItAPE/wtivVzftCklyirO4+OmfkftzxGbX1/QGxAlJyR0gmm6RvKa1YoKUrKgK5S7\nXscl6MYwHWn1FJriTwerIP4mWdDdbOdCyCWKVqrv72q1sgu9Oofps4WpH4Id8HnAUAeoyYdHVdyf\nJnSE8viWhzvF+yf1tjrLZZySiZWT+ad44uIZkAqC4GRPwpOiYMPcB2Wa+1jl9Sjtp6expmx+u/5h\nAqCBE5nVYwwbNJ5/97wkl/T0DZm9KVtrlWoLxqYBUhTAfQ/Vdd5kx3Es/xK0tvL1c62UXivN7/I9\nVqga2Z9NvKTT8owc+ZOI0CANprFE4IK8JbXKrTc2NMiULmEnCU8OGYBYIMnkxGLerH12+A3ChuLx\nHIhcg1avfqvOounj2H362C2fJYDtmMVv5i0y8x0+v2FBjrTzdrisolTypKmUZ2MHXga5ZGY7mXqn\ndgkFBZOS64qYD1nIn48V5Vlsi7LF5aLMCOZWlXOw8WmIF6glbehcEFsPSnmyeQWeFK9duIjIEiYC\n2S0COsdbabYyYPGGFpz+iI9h675DoLj4BC552U1qA3tp95Z5GrD+9NcJQeNA3QjGp8mHde/skpX4\nYkex6WxEDA5ppcdy4YJO/pIrDUz4Y+KJm2AHQ8G/1UYNLy3QQm2xvEdP165sZy/GgTk/MxGtmTrE\nUumAVGVSTzDM3pMWOXMbHsDiCoY+LxKBmOofdTajcbPQor9UnJOOh3bk79plZvZkj/kjgc1ipavu\njT6UFxbm9ghBi9L6eUME4BbN+EiorSLlyWruDKS6fq83mX+4iaCshfP6nQnuTU1728nJ1U7J8h9l\nq+nruftauizB/m2VnGlEUGvC5d/olcqk6pWiMeuemTJM5+/BeAZ82XblX62hnpwo2kJhh0byu56B\npAUGKnLdamBw437+UlRRmPWEp2UG5OrqjLR0JMf02lGeO+AXXllC0ji5T+qUuITeYpHEadr7rg4V\n4vCNuTSmTymv06ja7bmoQR69HQxh8GWBKzTOLLC0knyElBbtUMaLTK8ocsuJxklx/fiJ6dcTfyay\n17QKT9aSN/+h/kzJsmdd/rSI6eJuQzg5lq1pM9nNggWdnDkZteF0Zg9YFqHbGfJMRqZuHxiWWHYf\nhs6BYwa1Si9yITAbky6OYkMYRRXLKB11R+pmRoUoiwr0xLh07t5UF7xEWYTqv+9KueNxtSOeV/+f\nEdo7uzq0Dii7Z8WTX2z7Aga6oO50BUYS7Zu9EQqXr8lj66On35fDlpEVb6h0feMPSn8Z7CCYxZxv\nrrgpc+B2PXhRlSumar1I9au3GrGSzbXaP9tYa1pWTWneUxksfdk/VkDLBuWlUN3jc5hvC0URlDsn\nV9FN14sxPOVWYbJt04oVou/R5XA4BNMUei+KMqaZ9LsMWy3qKESHAs0vomXA0Q1xxXac/zDN7LsB\nRTS+2gszGrNQQd961iFcXZUTQQaittUszpL3Z1wklSTLGQ3Do9eYkpQ4MXTmKjEcUcTkDd/8NA7M\nahK/cQ2y1mYEyJRkYFICvafpDj2h3+Vrzbg9cJ/+E1y9pNY2lS19jiEtaCisx04TRLUodD8TP7UQ\n4/ijc61VHaWa3tTgXuk6D9hD0oCiJOSUItz8iavDq1u7eDRCMKfEuHf2v8Ddhmkd04t2N/NQRTRb\nIoNNHHHBrQ/dszA1gWrgEV1xZ0dKWps4R/gk47Ow72agtIRoPMhVUyWaBgxaaEF9NAB/0Knc79/h\npDrIRM3UDEfbvOJJfBhGpmEXa5waa5PjxFrms+lsyTs58QeBBGPyfXH1r00fkBCCrhrlsM1QQTrU\n048xf/oyN0tUcjE/B1ZIBe410V5kNJfAtxAh2VPfvVbgbecLqGm3bRUljE8ozf1n6ARxD6GASLmc\n3GOh/dMJqp5oJn2sOFwv+B+AYOeGsnY8Qc0sa1DnEwTVUhDCZ2M775dMR3zZGEM/kk1pALwGQ6Im\nCnigap8WJ3+AQ+x5TZJsjWnnsZFbKiAITDP4+5gG9BpBQwVL7bSQYfWAYV+HsZNkpN9DYVKoz2u/\nbNnXohT5+gKpBQYKTg+h6XWaT/lwjspKXQkftnXwIgZC2EoA3j1BVjXTu6ePnVHr0azUwa7rhzUe\nSNoCfmOWeqnZSvRbVB+fRNZRI4hAVPpgptKPpCgL7DekF+8a8+X+Rca6jH9KFM6Vat3qvo4j81hW\nxg4glHb86eHWcUlzAW4wQR/D6gOuwjzvEi1jMpNNzZda2vtnd6b2QWQHKGtf2V3gPQNE7qp0z6tn\n8zMGcmW/WdC4n3Sc9GSGmsVAzNkoJmkCpBSMUwSbM1Tu1dX8eqXtI53zosOPO/buxyAkhN9sXDC/\nt5lVZdFQB3QqqT4xDjY+CwXxguwKeogUHQlcmu2PyndG1/ZlougRvZrmb/Lkw6bwLFHnuYLBZbov\nvAFBpbSKNKvQkZfTSwYiDNvc8BMFjMmjcFamwmizpssKFLlKIIbAUGDo7/9giFPRr+jOsQsmEYM4\nvL/nKadZokw3N0FCPbZNG7oP3I1wFyii7Klje6QNyIu/MqYQmb/XY51Tt3uPm7Xfc3/tNrmlri9s\nqzbMC9eeiwC2HkXHim2p0c4EKVWinPJkmzzHhHD5XqOMojAJPhX+ZblrNiwdx7yZ9FDd+udt11t5\nKBAtGk+DkDqFAWmcK77O05i4wt2nbfCYpoKyN224bqN/dwJBUcvQDeGU7zCkK9cY/M1RyGyOrSBv\nuZdwpqjj52VMyhC4eSw0VKnH/dkjXE6ob2Bu4okt1VlwfosxgTLiKv30Nxqa6xsSgUBdLW76YgRM\nSSxCp+DlI4KsYaCpTLqAkTsNbWs/XXcz+KkpZwGT3Ak7gUk9gWYDThPEGhAMifMZoNiuB/frOteo\nErLJDy9+/CBi+mwbqwhlM1mSLtEL+QjKXQtFXnAoKwlV0A0S3Y1F3eZVIt6N7EGpp+GqKm6pbvJi\n19Uv96Xgojy6KuRIp/r7ylJhgsaZmktjQVHgyTwbhlwc443FUjShzjYUNu1v/lv/ma3v07n/Nu1v\n5Ygxneefjd/BazNEjUTdLMV+xI/8Z5v2ZgRVVM/EjyzoDUtDR+/Fc3MUuqiQt7vYIQ3vJshwAQ7H\nq6dkx314RtY4hRvZUCGU+rnX/qCmenpVXFV2xn6Cc/5OF4EXbr6RN/qhCuiD81yAQd/NbjNEOtMW\nVmqXqTPsOOPY+FHam5EW4IxjWPRsAIX3P6My6Rer1kJd1F5zhDJbArwUbEm54c9GQkVXxhTWYIqF\nvH+Qp0Yy9tyMUnRlASj5jMvgwe3cUuHPxlyPUuZK+rK5ayJVxweBf8s8NsE58TFti+6DGNH+GMoj\niJrcHMl7JIRez9U7WoBdNSTa6Wu4FsIQskSZAPRnqG1YIhSSsLnEaonRZ5jHn6PxFIsGHWLkRRTM\nPYYKNKVMipW3WnaHIgiN57KTb5pXBGnXQxTZWgNJ4Oc1Hb/CLPxx+jpJFEHcrEa1chVQZd0SORaJ\nC0zRLJ3K6naY4bpkuEtRGvqnEiC69i7rkR5IYJVZn4T0L/IaF+HxfL2jZBzUqPiEpBIkGRIoRoal\nnAnVsez+Tf1g3sKGGb8Jc7Bvv9mbKP5r+ciY4SkeEHFCjRtXAHTU2sIxj+cVDrOGcwgj04QZg1CG\nf9j+AucjM1EmfmYfM6GMwlJ+jju7bvRNsowv0BBNlF7J8l98+ikv4vmUYM4WSkRV/jc+XOLWD2y5\nyNpM1OjVk1/KAG/In+VQAh+vgz1+4/xoyotLH/qRGT+bFxn9tomW0+Yzn/gahFC7LGrb3bI0eQTp\nQSejapmUj3nSlxVQ7dpQNZ0NrLwA+G/GycUyauRzRBxKtZMNHDmjfuBZX7Tcy7YiatzCZ6M2eST9\n05E4HperTb/cfGMm16ME0VdyxSZXAmb+OckEFGyGvWLoIVi1AdQUkJAh5rbT1QIkSS95m6iNjS13\ntFc+QIFe0S9X0DKXeRy730ZfGzxDHl3mt004W60VSMKldSaBLcHxxkrXUno6fZskEcRQEFd8weJj\neZkjtL6rtwkKjYV6x+cAqIRIH2CIcwgvi1MM+SbuB7Ej2OHbWGsH+ae6kDWlG5RxNhyL9DD4xcf0\nDdxElbdQ8rphwwoJvoNEe02bsY8iwtjuSyD6Y6clNaL27fwyCzjLujIWDUy4CHvK7Vl7a2PLD+dw\ny3uIbO9kn1IMMIKHSlomNpPap52CEIksHGtfk+4XSYfSkQKKp/kNqVVR1RPQGFToDqSveiV0bWAu\nSEee8c2awA4VDSIte3mzaYqUYDEfpBfjlJ1kfUOttH4qAi0IgL4BL+9FkiKjuwGeHVs7r+v2X30a\ngWOPSwAX10NabuD1IZjK3kIAgJJXnmco2ziHkW63XC2rKj3imToI3yyPwL11wtrAgJETZGrJTxO+\nMfLO+/2U61Knhu2slj+hYdaJqoIn0DCviHnI7DIQ2fAgjjaBl5/Er7USC8yzu0STnipb7cjZiTZP\naakr4i4vGo4b9Bd1itUaJzJtsdWrkVcFA2gSmBCHTYdro1jelehFneB/aDR7mxtnjz4PoHdES47A\nOuvVgKpCzNoMR43wGwKzG0B32o2W4cyo5fewsH6eHMn+T4EedcuHmgurYiN62uO0nz+M7aIaaBjS\nbPAJW3sIHIEEdl1P1Qtj5bpN+FoHJO1S7NGnxpS9OU7QMPd0thdPovlaO1Whwj23a2G2ry9SoW1z\nY5olooVHpgXYzMH7/aKVZy7EIaC6Pq6ILrl+N6Ql3+UuOAhOVuIGmgA3U234T48fYm736NjR5Gul\nrSbC9/WbAzLVLiCWKyxHmQqbSEsaOrjhz+ddTL3rcvzVLwFzhjTqRWQsPbtItebs41tdPf8MvInt\nkHYDIMP1RHhTu/5dAS9h/X3tQYAQgRhCHOAE/4uMtfdvIjgAe8fs2gC8QK99+EappIfJfUkvZKML\nn7JtFbyd4wN7CU5dpNIk8/RsvM3z2u7jtDa1yIZZIHNQfTaJ8WmsrUrjGpbjbT5lPZoMiQt/jblL\nk5uJo5y4kpVNE9Mg+OlMSMqekZyUeFSHuGOBn2smMqko+UVNaCFxXInWjz4TYpqXp288S605F7cL\nLmqsI1yHvV6yXa/8DztLhmbusW0vtxUKU3I2h/KupFTrxLHKOWOrxyix7kJ4L/g8/PutXuU1kAoI\nAu9OkaBF9G4qAHp30Eb2fxolsyRqSg7tDREIfyA6rPwj7+gY9z+2g65bC2+O5XyzC979ETBl5EmI\nPjuXiDRlRRDNtKsOLoz98L/9GAnV0AudrPU+sgVjxwcNfKaRqib2icBzWMIIsL3QLhhQxLI6bZwp\neya26npYMw+VI6+huptBzOaBV//Yonn62HLD3MBmDEsZRbSRiedUiuv7FO2kTlQi66FK9h02Uf30\nzrbGSKr4sRI666hzuzBE11QBkJqOosb4dDlHX01MQSKIc2w5pKvfi1MECCATgZMZ7ilhizyPHPhM\nqYR6erClv/4mrKlfdy/eRyaWBenWkK0J9aQB62+fNvXWRJ3F5SQA4xtCLxOlSKoqQVV+311DUvax\nEm5l0r5y8XMpy8Ig9W/TOidKG2ruNkmtRHwn7fomGNnG+YRWvlHPYkKcrMXXVZYEHhVwrwv0FRdw\nqqilhFaMowQStCU6A/Mch+SK8shJHK11OJnt4E6n7GSS0VWWIoddIm5+RK6+DVbhGIGMWvq2c+/r\nUMAozYzqqMD/iC/ZUuMEFaGnsRaf7fDLta1A7VFGGX1JrfJ84/D89+TUzIoiJt2a+mlOv47F/nIt\nDAgtzOSYGKb1NhXlkc5js+oaoygWm3Nl2B3F52XQd7P+eJfDpWK2TjB4F1BX9GMnOlI5S3kWAp+y\n8m67tK5JQgHqpN0CZ6yLbololzSu4PX3gW8kafdkgnx/s11MMaGgmdlGj2EpOY3RmzfYb0zUcv6x\nrDj6PCQU7tjBx85GxXzUZpzyoW0vswvtkLufpFueFe13Lj/xkjdwrV9ztjg3RmEWpqEDhb/ewj9w\nMDgzH1m5Waee3zV6RsdM8OywzwGB7r3QEi4+TJUT7n93NRH2bl++VBegv12aakTzLHKbSb6HyWdE\nUctb0DJhxi6aBKuzwBDJ8IXilBnK5vb0oGMpyvR0+SIG/WehKC+lUhfpwyKzZ/x+BMz/AakXAFHB\ngprixyoHCJS+IyJRNTufZoRpXGD/NdpZEyuZEAOBoY4iuamF/oaWgXBZgaa0NGa7axmq8VyYXhhS\nXRaEXo0XFlyt34x/Hs3t5P2AwUqFOhBalvgxSFuIdt8s1SfXHA48jwEBSY2mRa/LrKm9DL7CVsfd\nW7AcoaS+xAkMd1ZA7zGD1+xV5kFBSJ+oUm+BHq35pBGjxdwPM4IYx5qL8t5y6LkBzYVXQeXrYz3n\nAPikEn834V2RN3BXwNBi++a9RQG/9kyZFKAgjy/EIEDqsZ2Fz1a5AD+kRnZMq4Gy8FqfvtzaDX51\n/24gW4s+KdESku5GMoJiIdxYoPSC5yYdU6maW2zfvhU7j/VxHIVkEAuL1jggslz7UvWmLvDQSvyg\nAOiGhRngYu4hcVry1NbfF4Y9YOxx5VSFvbZcdVav2L76PYXQvfZa6b5zAj8nMtYby/auDzpCGggX\nIFig1IHnalQgAmlg++abElpqAE9+F7wlpvxSuMr9qjsXMJFa1NLhTAuYn6KSATMLJtmc5ZgFjtV/\nqZI83QMNaqgB/sFXO/zdaW6lc3DKYv0khan0DLyxC9ZYoU56KxHnwcsy316h2kq+KlFI9JUD4R5K\nk+NKgW87SF7e2IsYnl9F4WoeUQ9uu1TrYwvbBQikWhMo5zGJ+jDNnZE0hXYvD7zLnrpjNxk8u1jB\nVI3+wFkgF3y9dft9r//mAputCiFpTIwLsQE06NCVgTlG73PCHAGOQBkEBW1i6c/u8at890aDr9FL\nJulPXrkRHnyQlGS6bml0RA8vNJpoVwFRl2QRt2qUo3qTbXDEV9aj3xXdfeEseUR6MQCshhixhNj0\nKU4YYyNjpsnXLYyHerXk3ioDeukDGLEyA51ZK07Szu2UDcIFqZ+ab2ZHiovr68NcLfw6YE1qkg9c\nYLT5Dk89XCyGIdn3pgnES+Sd0tcg+T5Pp7nx1EigHx3ZihMi8Oxe/D6guDWy5TSL1G0ZaC8BvFYa\nh1C5Pfr43DjEoojJFMUyz4w/w5lCEUBEh6E8gXjAMVjzFAsA7vDjdWz08GsKz+CFWPXVVrVAaIRy\n19k1gGQ1MRtI7CUf1wWh7f416K2hwjHgzz6cmETCt7TexIThgarGxn+VSXO5pr5O1/Fs179fijJE\nLmwfZInZ5GW/PJnyfU80Z3xD7Jf8tA9KEhVmkiNE+SX7QVCho8sBVQhT5B26NKZrKHXkuFWKcBsM\nBhB6mZkvndJIuBm6ALke5fJITcrvcci6rA987B6eGw2NVJK11fP8ugBJBkmiSCxH3U6uXThxgqMz\nPujL2p61OUB/0gPUXs/sr7qt6X9/kYDGwejPI9ievkME+XteHvCyDtPlq/mjoWYawo1wDIP2NnLV\n+0QatxMMZBMlG6naoEf4pifcaMe3CAyIAlbYCkFgKoMf0qVgdHd05KcNusDkLqz+bNqx0PyHucx6\ntQNR+G/WKS4eXcAdwTudTPLXuqY4T5dXr3EU/fhG2oKFgHJRrAIllJQn5it+B1ljBrm8BMXVZC50\nkm/y/Dv2k1RZg83xH6UoGk0OEw29nx+XrBNqjLBViBHSdzLAg7XUs4irDXyfhxGycqBdvG0a98Nk\nxNU46vJazVxZWSL6U6mAe6Sv3Sr9jGmNIgA/VdbNk/SIP/AhthEjNhk/19pheo85ryTp4KL24Vhw\nrSotkbHebmTArYBspDLozvV51DeBkxnLdq1AwEdI+kiwzBbiud1p9rJEfRCLlqRYOI2rNY48L9Lz\nVwjSLp1+SKY7ERb2h+5bygkAImLrivJNuv0yj8p03GAPfu6DwfwlYjr/ZSn5C713pe6Imf5odEyk\n2g27gNss5gKol+0fnIRlZrAdBphbK+HDGns5LVFnXt6nhEEzzrhmhY5q8YS8OBSR09NzveOjphSo\nMFsa7DV6Mx6FidSa3xeL8Kiq98kSg/JzKmT917YSdmFImgN839ZxMPonkiRYfizHC0bcdFfVJC9P\ney50x1ZvNhADKvxaQoVppfhgjgY4RAL3yo8CNeL+8diNOvxxv7VXL6VmkVHb0OPSK9T7jM0UNC7g\nx2kdywCP5JyEAE1ZYgyfhp0cZseW8D3oJ03+f6aWUefyoDW+U7lhbahfjP9EC67VrkOC0aA2r1qb\n0EGdy+Wgbo8LwZqlv+i0kT6JJVzJAs9m9mIkVRdSau7A6EtZ++Gui0K56HTnHxdBZpKPLfaMY/Vq\ncO5ShwiXPBEzE8G5dKmjHC+z12W1EDxgsCLar9+YOAjxKhgHkBGfg69+NmO0ydwiFZtkb9kQn2n2\ncakas/WtmPRcBrFKxTJv7hrqsa0tATeeQxEfLYe4qtlUzpbtLY2FdoNRQlSxUGJ4pGgiCSx+x5ri\n5dbUwJzYin9/1AkNrajyQ1igqFH63Oe5iA05U0OBHL1TZbqVJu91v+1hHGccThB7kV/xn+sWCL0Q\nmMULWQqEWLR9aFsTO9vP+2fvOf6Zwuefn0MzofCFTwq/kYuMgyppHBeqD0San0S3+DlRWFbvQxtd\n/2tSB+nGWbiKevmP/K3gE8oRdXigzg7xbPH+gh2lCC0wJmKwTgQwHIC31x50ZJkg8cci6fVAAw/C\nVHXrDrjZSiroK8utPInMK9UgiLiJZaxnv6VMTQfV26pYRuUPBEPpZ4PLypuOIcDs1tS4X6nUNDU2\nfNyzzsyS7Fs6nTKsfTb13JGw+dOOt4lMUIBEU84U5RQKL+jrymEyKK/sSA4kuQYjQXLCHUIIG8G5\nHUgZ9GKsNo3ugw6mpQdnfJ5cW5I10H8JLWrMiCExw/s1EXPyeM59eTd7T9tDoN1rAZKPHG/JN8dV\nh0oYFXVBv9sIAGpOy1+yMXyrapdwkmnq9M75xOw+4tdRAWNlhGUgeer4qaGwM1AiZOh9ICdC5zLx\nBQ6+b4pwzgxHxvbCVYSY3J/6A1H2OWZ/DJsHbkCJzKyyIJI6c9Sj+iL7IWOEz3kPoTdwojbxnFjE\nFHyzNYqDISswQg6KXYsPWTEGpB/obQREvd+ABflTfjzhr3Tjftzcg8LURNmOgUQANWT1DWQSbC19\nmfeCmEA3Y+mKQXkzlCARoH1uXMPPUpVC1ipWTPqeH7TcwHjaNCNhXgDS/uk2Z5GBD8YiHzSvAuVf\nKZvULyg1j21LI/bSkfQ7+lk8ROtqWPv7/JtmfKo4EJbyI7aQPWjlTqdH9mV0ELtfD7EbTPEhwZZQ\nHGWfHrL778ObaVgVlJ+4cur5V5ysxaYVfZvWa3RzOCv0QqOo2lYVW6b1BV6cZPLYruo7o4VgOq4K\nzMz6Tv5RTu1X/Q0sXm1kmGF9b7w0Pc5x3QBxIGCO+NzcC9HZekrjxRIqqqG9SREDtovJy40tvW9B\nVLyL0e4LS6wq+BG21T5Tm3wStOhCHnyJAneG91iZNFnrTY57YkATwIja/JJiSnDtzisBcdOXsnE+\njF+WIPe/OXaP7EXFwWnvQcMy3CEeH0v9WQ8R0k7m5/5LJUSKZegVF2vImSnXZte3+N1jLmIspK2X\nLSW00mKB9e7X0tmoffFcNa5K91v5qCKZP+jH9FlXfo6FyNfnHZeBtYWE1rFrWkkNoyffdTydMxU3\nHsE7+QvtoAiGifQOxWPvyL6jtcKpDsPkZKwWMaDS6t6CrUW2+7FIzIySi4GPD+UtldMfOgfX/xY4\nRwOLpHM0qz77Vk7F8r5igDm3YdRUclJRj/9p3PhuaGURCCOfvYY/1YtGyn4pRScUV0eI5mWn2HkY\nPB1KwhTPUTGwVWu7Y3fD26njzSehEGb15soneI8/j2u57nBdio7e76zBGd1Ae28DCxlw6eheUL+t\nVfbb+l1BrerQeAHVxnm+duuLE+rNrPfp+17NGTOlB2Qf1rcFqQWYCmgEI+VzyOhWARntifEQ91cL\neG3JS8IW02lPLDfwgGnw1jdsBDrP490+YoZQxAo1kmK8lSjgUXuTchXZtHz6I8/mHaTDsZ3ZJQA3\nNXIjfP4KlMMnUOG5LiaeDZ03uItPx33c7XIlhC8wCHIeOQHEnRoS7Ah4f7M3FP3oommN4YQxreJR\n/uAHpkr0sCdoRVU3J+7N2vwSP685CNjrqyl78reB2aX7Ty3g0hVKTHlyPzRgA62N3Gfb9vMrk+W0\nY78yHpQHiYOQTwAsjZvyYBwT9f/ldXZVwC1YIvI20GQ7kL8uvhV/+zbXVzv6kyjHg6HZIY+D/+rY\n9JnqgDOXkANYZNab/6uv2j1ojjDqBOeZShxkJkbTwoWc1yT8OmnQVIXLmeGTpGuabFKI9Zi6Q/06\n+HPwkG5LawIar0MHYUs4lb8X9uKIVauJZHO3fCfDJpfE7p0weI+DMayYvriGCPSu2+0cO66waMD8\nkoQKpOmFxHOrio+PflCURVPrWAdtiOVWfTKpPdCUgyjcX/0SNGNc+GsKLpPgnseR5baF4rxbWWCj\nkZQJhVLuPemR09jsCHluA70+mz9AXQAg/pa7bfPbMldU69lewVO7xbwqdUDy4hdTZYJCwX9TNp1P\nNpCzdGsgoswj/88Cy3icvq+rPBdxfqogbUZXI0ZcBQuBSscM9RPagLxJRYfOWbvPYakgaarvMURQ\nUKkmvS7oHX3jyOH166f1V6kX7iU1FtSODnMP0RTIiVB1jMY8PPv20LD5653dtu8nhpW/yxdeaulB\n6HrUOModOutJHPogWpEpYquKf+DCjyztBIiWtsXp0rIdpdackzsWc3l3gZdiLtsV1BhLCsj0FJw2\nU26qRLCKKxk0axjYCW1xbCcNn2Ui03uJuYtzjrQJU/ng+M40qPAoIOoonXkN2va+Z/XjAlJvXRLl\npvwhi82zybVUV7GX+GBE0mShC/h7yvkzFiRrRDA/RwRQur+2okCdE6dK8hr1zzFE10JBP0d9TUS0\npK2XqZN2VJ/BQSHEd38SApjeg4BZNbFB4+Qm5v2hy9XGHVWFBr86STemwiPK/HTKyvHbsTG8gt94\n4Y361rCNBFPqISw38qIcz8ooUjFi622Y/CWCjDz21lLX3iFDIFf/ZxxqVSlJM1NoqsTHOTYaVwF7\nhlfj1vG0b3l+cGCZNArEGD9fxGx3Z8OwL7Bzs63ULFNDz9lM2zFr4UU6eL3vuRH3yJfuI3H4I77P\nffLuBWlPBg9kdeOw+bZrrzSRIRmKmYS6kOz3Uyn/i0ejd+TPM5dR+qHmiFt7OZjjSaf6pYIDxuFA\nDZ6PvZDVBcTDMavNkIcSkwsm+B0NwELE2BV7pbI7jpTpkuTQpZAIcuURtrHRXOohYiktQX0f2DId\nGDX2juPGYqAkqHn2O6TuzV+PKfUMTryW3TwkT2rIqBqzrGBtN1hU0JVrCaZAM1J928FQGECowe4C\nYw3phOU/wxWfcpsDd+JjsNmQP1GrNaLeCvX9iiM91ya+u8I0UPBSSpBhbDExnHRQ8x8L+Nxrv2P0\njVZpcPraT1DfqxmICYoVm6AY7rdTgJrjclMbYmafOsUk5wRRTQVAYPBpGcA93u8qLRqEvvDHhnS2\n9RKzGmNUV0hKqNIF4f426z0tJi0IkRW0znccZmt2d8TXKzYkCOfKAliSBqpZS7bodKplqMqc4voE\njaPXEf1vKkbUQOV5HqmvUiJPI5Y7jQrosCCg5VL2/oqN5DodmIqCCTd3vdAm/tt/b0IuI5mRfpP6\nV2Y/cRCrmE+MumRavYpcem+l50tCbeSbglB4grrAtBooNSiWou5vd+6WISoDxewgOeJQGew6HhaX\nO3eGe6KfJ6TaL3fiJuZF3hZ9XXqyDuGrb8nQoAt6dqqzzDpGo1JaPScwI3EIpud4EhFE1Qti5v5a\nV3Vl1+6/UJSBa8V/BrByhZyt7xmrFz+1Bgy6E+Z8DAH3rQXV6mKOieQAoUPkW2mh9tx9xnFpbSsZ\nTPYhbec2cj4bGLI5crXAxEScCC7qH6wD4Zgnd+qNl2NdDJqKJO+4hUlTbuc5wXXvarGBBhgjMHLs\nXGdXVwHOm+Cc8rKXJvr7+5PUUtnwD8gWKxJXPimyS72D9CW6d7dkhkbP7lFlaWAatkkLR5ARwFbx\nMZAF9W53PRE329iWi8zBjf2WDZBSN2Q0TcA10dOE5nbnbfeT01IkqmqARAkQh+nTwL9T3bR2A8Pf\ngmwCqBj1+5rRlYslJ8CZOrLDQgDuLDJ0EbX+JSDcQd6jEyne6hgAaoZs41ByP/8g/PE2alqR1kRZ\nTYhiSUk5FbaPSLijYoL5o1w7Zy0qqdH/p9GBtm4JO9CVzc6hI09H8Uk2lQbJPzvt9YSlv3v92sQz\n2TKxXXtBQ+mUlziFQ/8BYitiRqoE2cdR+mE5f1X1YvM49qIirMbEuumBGiHJqvkqNUZBHU0ZgVKg\nvobG6mF+vwwH28e3no4tQ7zOa/fDVprzZjLGnvdPUjym+XCgbrKyypqUWKJ4/T/4PjaanyzPvvXt\nRlcGp/nhqI4n2u93okHPDK6jV/5phIyTYsLiXu3CKgu+8IRYdXYOiIo/e1Y5WDTKYgQhmBVshF3g\np1hGuj0SPHrrAaGaEG0egjAyMEWxwFicIsMjvHDzms9wj7SGPo6CFt4YMfar870S3Mr4rqPPTLEl\nKaX83QSEnw2lHk1wIWIFRH/7JbyQRSmJQSWe1dyCNY3CJc9ckpBwv+ZE3JjOz/eE9hu5cxojJXoW\nlr5td8y7IAWzChiI0YLBwLJRGcSEKYwgbLcICqV6JillP9J4X92YlMW6BHoBsMhB1DOl6TyZgMNQ\nVlZGWfNoYelupoRkIT8M7MzXISDSzqoDIKM5mr9eoSAo8ib6YK3ODFN1Ipi0Hm+qUVh97Qb3LCXy\nJ6TLZ7yBPe3PyN9tI0DKKMQaEf7MIeR/pJVXBGsWw1J8lMeUKMZGj/PNQ8jCoeKR8IQWRQA+u08l\nvi2HhJO/OOKzrT7wWfTqQ8JQJWoego0wyxREKsmJVph5puuURbW1rqMZ59X/1NWVNk/LbJ1gpEhD\nRDB7m4Z37EdY60O5sOgWAgfgocCGN+qw4b+xKacYxMN4HjXO+wJq18wCTE6+j/Riq53L1N8BhQ8Y\nGzmRansnzeytnsaTfsvP369sjt22XF5RMpCRvIpwnBzhVtSbsoEOecovV9J60ihS9Fe3klm6gBY7\nO27ky2+Nqy6V5sFI8PXp8SBwkwq5pNi/BqYrHGV+KbX8d32v1RUYbRrV4F6ptibJnNz0aU+HQQBw\ns4RzTcJUIJhlCEM+J8xX7HwyaUGYXM4Vblpw6Pdu9uJT0tjyon29wMG41c5BLhYFL9bVxSB0rylA\no9dhCoNanyu2VfmWH0K1eh+YJaNXtEb0ysEmWhCOAN/BB005lvi/w2S97ehdtGEWfujIFXRsvCgY\n+RCIDAxVVZqHL8q746Y3NWuLClwgx1vHx1NcQUcDBNsRytgo9Gb0DigkKNt+dAAIGmfD2l8RTA00\ni2rxwGF3erRv9z6mzledqzEO17RKC31VFamUnhcuZiDRaRRCBnE8GuE5BHaK8rw79pL1YSIawfMd\nLK7hHkbaDI3kT4s0uTl+t99PyWMS/B/0yfBkHsKDGfriLreKrAncpEeUpJVFKdFGrPl1HIHS5ZEX\ns1gVTXjNJJrMestKVYaEs4nViCstGD9zSan6JhEmfaifIkJ7GLKw+NimA9uOzyKvxUxfRCCFUSvF\nMprZGCfJ4ltS0NYsdjAs1KQSH/5sn/PQ6OIeDHlZ/n3Of315bRk57pzLC1/aVqAi8XLsSRefF/uG\ng/x4R0AMUW0mo2mdnHH/TY/0iT8LYCmwQO5G/dkxHjhJRFJDZ3qUZid99q56MwmCVIj6WDNBu+KO\nQN6QM5N82dHzc1QI4OMalKCyGwtF1fJoK6eNGi3dVQTES3YoHYpJwy9mkxPa0rvrWLS6/4KyUv+I\nEDZZY6lbAg/ozYCu+01v8P5fYavZmOXKq7EICFKOmUroiCAKQb7RAGvnYqGcYPcJRAsDYdAoIFDU\nroKp2Ovcei4dqjC/IMmPpx2utomxn1moEPZkeviZ/h4Jw8M+YkT9VrkRWpAoADxDnDqVJm9CyRZ3\nZYi06cQ7Xi+nISoqnuU0wG4niseJcLPhRyK/eN25gKr33zC0KA1F90dGy8K2XjjGkAy166Fm+3nU\nL2M0OoqaJrHkmiE5GOorVEOvOcgQPi5mcLYVduX9edasttXX1GWuqS6e+TdcltrvITA2mCaGW9W3\nuLXjKkSpq982wMXZ6Lezt5GVq0xxPV/hocBpYZGNk1GnQrKh6TZ2oDCwL3BfXTqGPrO2BfEl6Gt4\n/y3kZDSf1MYEfz0iQOKOy+lWAlsnuPolMTRzT1cOGY/Xo5ZfvbKryDcTb6bhVTvO6/ytROqjAUmQ\nTHPlyl8CeG7hdq6DGm/TlWk+DtDGTXDeiF5IwFeBRsJPlaQ//IAkaAdtGnFztK5xLzNvyFs87v/9\njkbEu4pvPLRGn8alKJB8ZZ/E12VD5owB7dVz3WdKnfFS+ewUVFFKFM/LqRQIoLDfau36JyDEBIoK\nCc9QhI4knWpjgd3rc0Ror6hYufUfdIhZvbYz3935zgckWWECuvAIgdz5z2ckO8J2UHAmrLdWFxtz\n7NFYheF0uQVqIWu7hRMmfPVEgJNVslEfrtSENg19NvNy3vkke892kD/uoMfkVuyjAkS8PzGBrXJ7\nSQqI6VjMifzTsYMS/WQ+kXXwPhjx09QEncMmZSp0thPdg5CZk8eEvrZGprWuaWpDs9S3lN+NV/qh\nEaMcIGIuEMxbxMgD5WtZb20rxjLc674wYAzoVZKd1k0L9/5C0iSgJUwYBe49dyDOKYUMctmkESxi\nVd7eT/IqusXB5Q/PLFKKSpIjnafKrHv8yGyfnTaBC+kzTlVpb2G++mJNfwSbkDuqAvAoKjPAVHv+\nqzQVAKQ0+UOmw3T+29c4atCHzi2+uB2N0pr3kiOHQ8yooLRMdkn24q9cxynSkIZo1/dARHNNdxa3\nCJv1zraDIX2a9McxBdYXYYPeFRe//3X0Icj+fafoR1L6ZnzJ8pkqjZSGr7s9acLQGxabvRMGFAlH\nVSEB3Y7eWvxapneBKniIGGujM8MXaz15lv9RmTiEqxfRsxRhgthrhqNWOlGWfz21p8uZT/iV0h9Y\nfzfelebsnPN2uqnYGEKFTYTm43VLTKdViucgm0FyCsC5i7j0MIw20+J+3xPhA7x4++Bg0WIc2oa6\nyZWBWrw09oorWa4VXS9O4jd/qCs1lXQO9qyI4RaWmg1w/2nMaDgx3InEckVMCboMIeiaxntF0Oan\nPBiBdb1PPzTtsMmzVNpv4Fjv/cOEPRIRFPibNg3qhLCCRI7H9mgzfUzv90GEsJjMVTCAhWsuuHo9\nwGzpvadtd3ZPmPsOFa01NwPTRw0Ka+zQf07NZ5o1vtUsD8QeGQdLQQ/Q5OKw2HbA/bmpERHgtPaO\nU2pjfnadcng5L589GtL1Yn1o8CLSPo3GBOJXJ+EEsGHxmSytk2TceD72Fzn1at8SRZcjtsb4Puy5\nD6IOS7UeaGPeKQA6l11RgJHgfZbUgaJmK6tPYXZqXja2NBHNAlJGUGSUdtTyFwrSw1v9Kvbta3nm\n9dSQggcFLN0jfOh4Wx4PkZqrNAn4aYXAl1hVDrYSJYeIi/g9UWvt4lKEKzII7sSP+/Smvc+DQI7c\nKrUPoBrCwwSIULOWIvTrmc/9H9lyRuvvalVYoO1UJ4h1QZ8l8Awyua3XBfn+LhsE5y8En3VMKVBK\nHDDhGXOo1ly3kQ8NfiYxpwcHcNdNtrv6maO8YQ5GRGqef7AdwOaB88p4d8Lo4SDu62Dzf2fkdySN\nvx+zps0lGn2ew4IFCknQaUtUaHVrSDUG/NZZQabVDl4WAdblcpbCOW8uTiNoFIKFX8dP4RYXgq+N\n0wODhInglAFqObFfIC84RBfDlEA6t/45rPMvS12+uDunWBSZHyVY1Uwvwu/pnI48lV9m61OsJCLO\nOIgrpGewilIwhStXkjxdI/PB+Vez075WfTee96epvw8Gy7kPD7RFvqrDDIrSGm93FKnRHplTj8O5\n5uu+yfmzGBWYcqCbo4mJK6V0M/SJnB1HCGbgLiRxGy/WnHWjaYx9bBqMbBHImuGlpEzPmfDKvgV7\nAlHvpdpzcBlf2iAEr4jhpXqh/KwnRQ4vJL1P84YbChWf4s+IKE0AZ6f0vl7phKgUVq+P+ULvZdoT\nqnWO0Ig8FCSr/a6sZumTd2V59t1HdZTvc9V7LHv7XW1ar8fwPredD5AYEDMepb6AgFxec1FiOc3D\nykbfBhIXJE6n+Yn+BkBfyPaHQtr6CygbQYqPxrWvwqNaGqiR4M1+SnXc1ZPUCuO3jpsqErNCpGur\n86gev9iN95nwRZl1czxWVa9z2Vups+DUDYNl6OGsA3VaU6eY+zfjdw22WdfBTQW1yLZbKdfPdglM\nk0W3fK6xVQmWd7Q0MFJx12rohylS2M3jRt6ymRYDuj9G2x7e5COQAH4HvGSj1xQao0Oqt1esrJ4a\nYIqOffOvsSJq932yvAK//wpl7jU/meranK6kL+SFodAzXhE5O9i3yUroUaSX5y59xIfZoFg4NHP0\nM7zEBF6QB2GW8onP2jBMjRx1c2YyjCZC9I2gxLVNFMuAynr8b5R66ZPqvrh/8y6Mqr83orbrcV1X\njrDazLR6yHEOtNQ4bi8mN7w1RxzLuL2h058RZGlSsTBsO8xP6HAr5Kp2wBfbvI57lK6CxqUspCj8\neO92O5CNgGOfYdotXRnXfVffA4XKFtgvw2Me/hq6OXRjQJn4ru2BJA8kDP43xdNfLhkeKIZM3AoG\nTcMCW6giOWLiADsnkr2ofGgeUFbW+ngIOyctXvMwRFMD+1K5RpwKmd9uVYsHK5u+PLBnvBGoyoS7\n8/m4+m5zQh1ucW8F1QfRwl/sKSrRq0ciF10lQ6zYZB4lLAem6FOmUFaoyuBVPiQdDA1ZsbW/Oy9h\nCVMHPZwPrJ3UnrPvs6YOfXs2Jlfc4nyTMV9gez2SwA0MbPHMnpIcvsBYMqVf1NbZumEG5UI4mVji\nsP+Lo3Q+cV56vHImYilS916X7mZ0gHna6WTTGV9UyJ+Du3k0Tl5TlYLHL/ob4uKWbj822Gt7tv23\nAJnMLGCkgZQbYYRLwv5C7jFKxzPsaYrdBbnhN8Hzj8uWglOv5NmXOcg2pNyIv6Xp7o3P4/taZy/s\nbavizNn1qFu+wczAKyYeOCD1GOD150qXMwDfJGIaD722D5IfvLbBJkBz14/nzS42fO+i/NSflxqQ\nIh8W1dHgXZR1+1xGFhfpNgJ73eVqPltXA5/xNtE6EWKAK2h01+j9T0mPP+TCq80DejbANcjNu+ug\nQ7qp1/IN1oZBnRQf0DNejhOdZ3Ik88Xhwy2Bn0jLmvR81NTNbmVEoZf6/LBhkmC++d5tWUODaE3V\nMmjV73rV8eAB0kRkj3yGu5GLwWEtbau6TqRGb0BcVzUlzqvF5MPetFqKTBQY6sJENoTXq1XQjWm6\n9wH63KFczwcmFRWNgBpkvjQZUGWcCIlioS4fuoQg+RfiCszpQm6etlOglZq6tbo35s7iHLifH2fJ\nXgBvGhw1Mzh5WLkhF0SZtXs1flSvmLCyJM6MwWBe9Vg1rncHvsaqt33+9kknBEsl8yJuvLzpWHIq\nIOyjgBz9NEl5RNUhBXzOzvIRK9F3Z+fejM0uOy+z5JQfMyUHKAEhEtGivvnuKn5Iv1yGYQbKcWzf\nrLxAQP1WA+5zJeTLRbU+kco9GYRaVaIvruvNy1wYXHcRnwEui9exP//Ej02tNULykhUHv7P7iTnf\nYCwad9m+QexSnt0Sf+x7TTYZGucEUC7Y4EDC2m9MsTtXFuhHgin2e9eHMTm7cMiFUf3O8h8Qszop\nwzWvIQZOkkv91HzJT8h4L2b0+s0LMTK978OOGCGHEcqUPGyAWN7nOu16o2UjvQGFPn79rD1sub3W\nU+zCmNvAttFgu659SJhYDXnvhUoNWhfY6acclg3KD38v/SOAfl/eq+85NRYWvJtweiJRYYtk0vVs\nu6EitsHfSy055na+HIelCMTPbv3+3OwB8KNeJGveU0qxSv4okxF8YWWxztNlTRVWwx6fC7LrHTJS\nXhjvKRWBJrdBkAn903FdNO406+gwfbMP6VAaTCMo2gsunicIpS8xTA9jcMdcnCyP4GXLvQi4UckD\nQNgqbWYvw5fxTLOWyf1Qu4u6Ul1cRBRNRqZ3sZG1iD58EIMSS69VEvYM1w5CWdFFkYZesNsF2ZAC\n4RTSQLixyOWbPHcCckgl3/E4FZCkIi1A0xsbsyirad4r4OdBa4ELnPi0ASWPuCJZp8QxIx9ohBTU\ncXKA+rgTrCgCLzavqrmNtp3Gr4WW1sfls95t68GeO6SScz+13sR+D3gkP998Q+3+9ENk5i7fJ9/i\nQcLd8GqnDZaJ/h36F7+cUQZg67jcA5APE29UEhwTU72sbZWGcGykxoFo6Wu8gG9xLNC2pPVSdS6a\nF55fpU0b9k7eoRIM9wJyDoF5jVRrL+wNULRlvZpfiLOpSwjUKnZ6ljjKtTt6qfsye31ZSpQbTEDi\nei67gpANY9oE+l8zI+oIf8eBQod4TXK0aotrRsx0T048+WvCuIiR+iczHejTE8Pdi8+enWorNp6u\nCcR1yfG23NU1xEPqbMjQdnMIw2T7xx8WBpnaS+nBJ1gNENmT+JS56BNxD6xy5OvTLAQXjtm+KiG5\ncnsBBCY/Am/rByb+pNGepykPoma6lXmXc5FMpKsySFKxXx7y5zorfRE9gSbCmTG5Ltvw4142R91i\n812qH7JQQPaumVCKm33BGCVGuitsJfOfv/98p8oQPsV6SftmQusOjQSyn5Qm+dlpy2+VymZDEnTc\neJlGz99qQGTvq8/CnYHNoTodEyCv3uGGGoA0TqUo53dr7ssSRbAFgdsyRHMDxepGAcjkw7T6laTd\nqtTg6VF8hWTkI7MN6+pMfl4m1JUI3jCTvL3r/vgV6Kz3ppGiAoXiSzxy4keXJ6PAPwFmbGMVtZay\nWyEhiliGvUyzaYlZPptWWhQOtNFU7fxXPiYE32GVZIx+SiWJLnWydxbRC/WlhwgNYcGsyqSZMFit\nsNGCmXGtYx50tvzGxQwzehYg0nZ2T3/PJDCx29bJ47EO9lmaIUUPuHUmene0vI1Pu3WArggyDcZm\nv2T2/rnn/OkCTuK9/cnfLCkG9PZvw+b6Q8iqL81fUCaMHPspDM/w/iL0pGUM68CLdUwOhsuz9jrD\nADfcq+EHTkeSm1tRfg+5QtFa4PgsUd1tA9j3+oO8OS4wuERtXT8tItcS8PjZuyin4U0+G5ec8xRq\nNXig33Ho45rUFp/dzkeNN1A0r9jrBnzIxzHAQZgfdTuGWuttmgbHPe/8AhXQ1iFepoTAzqrCqBln\ndNdMPtSzeK2ZoMaHjCWqZs+s8/+1seQjregjKaPbNxtmkplWus0EExT+udkoO7IXvlQq7BgPYo4r\nRpjeAfQC8Li0QA1OIq++poHELmQg9Sv753ldrgUe7HlrntwA8pnVfa3P2xWCC5ti+tEdtMl2Z3R5\nahgZisYsB8c1LNpju99Cd5thHlHl4q8bD77qMmBldsN89OKNqPHdYrbQUxFuR0cSUly501EUip2r\nJwNftGERUEMKhO82u2cZQzDhz17Ttkor/7NeO+Z+DrmO2e4BlNdtNXxiWIprq5n7njgKw0+Y31Z9\no5bBl4zCMvNHlQ/IuBUEEIcDEP1SH8hlHzzCrOoA3/6P17v4Px9APMiiv33ExsXH8T1i0iteJS07\nzLASBPvauUC9xNjitpan8V2eHxBVPDkLlNHX8+hobBnp5vRMSQcBO0JFm33M2lSRBE9ZNcgYf+g3\nkB2CVDaFyDLLvhVdXW034NGCc2deKjNDfZrSkVEFJH0aDJoEYzxeEnMh9d5rIKx3VYmcYHgw6JGg\nJBhUkNHmCjfh0vCo+hjMCPwH95m3vUFe1wKhOoXsIWyk1QJ+QTR9t+hZTowkYlQprcv5t2gWHJYG\nys6npKLa+KanvsrGVrXB32uysIZliELY0rvCu1lnLfOVG5o6VxHS66qJPHimhiy6XX4IgXd6zZiW\nYO7BOZluVxA1fF+ajFTsjY32A70kD/tRSPQpYwH9EMaoF76kkDLhsIobb2kYNomgtk7M503onnCd\nu64Y7Grs+FvIkcG6rJ/SZUqfoPbCZmvMJtxhS3d9eDphfgzSyg0uEcbc30Scvx3MW/Ka45FcPqWU\nTTJuaFa5sYSLgrtp0/xa2z1ZrvplfUMOfs1Ir4WbJ9S9rWOTG+MOlyxRJVANozxhNnL+p0UxBvIK\nFUnFSYxOeTffvL/9AiuwYKEGlG8TP4W0kgfeL3hMAL5gpcXggAW/2zDLba/syJhMD6Tp62ZpzZTH\nz/IPQv4NIEnBLbQy6BH4d0wGaSLfPyXvaUjY7YQ+ntuC31nihw1bQwaZ+MUWyZRcmiX5r9u7+XdL\nI1L1yZBLfdvFM+nIfXra/bYYxC99jIKFf7pNPlxoLNMW5ArXRg/FY+4oEjkoCU5VQUgZUNAuJNxU\nkjCdWYT/MrC1tV8BTjT8vgZqsUVG+9Q9BiJFhhAhyxYKch4SAtURNyGrLtp0SSnIYJ3B/ZVjzn7I\nxuxZZ2v2AflGdJfcDL+Rr6aLQdbjGj/+0zoSVfLZv4JbXBQwhr85A0tkeg6cGcxR9Vza/zc7+M6g\nJ5ccWZqPWubJGmJvKwm8cnMa+pcVTxa27WsCDyvS0Y68jalHosyqevLvcB3xDPTsn2uHlV+VpQcj\nV0VFxSXFpQmg8i91a+zS4L7xHHbrjcRUly+muThjtgw6ig/wF5IxtSpj5x7igdPnhA36Go4s6ycI\nIiK57NlcBNfiebdpAbi/w5sM+taV1uXqviHauEuFjtQA33Ok8ch86BdmtrhnfMrEJ8rHapBXrVht\nIdcFv0tQUfg2nx+8xWmAW0dbKjOV9EeqQp0I4g9LeZD5GoAP9n3P9uxbxza4GAUXxvg8YQn638cD\npJ08vWFIXQz+R7QyyTo9sX+L/8OhlUe57VaGzoGGHeg2RfhPUXKQ5g4vkHkUQq05nbCCuLIsc/NF\nA9VSgYsetAZd8ab3oI/3nSeVQn9BqI6eeK76MN9q/uGinlJrJwDKg2lAwE4Sx1NtxZUDL5Qng1z2\n+lwVJzNItzXwfBtFu0TCpNDRouYbIY10OgzqrgN8p1Iw4yC4fdfmvvoeJBaWzueEUdTT0lR9CbXg\nnCIcYnStmgLfad7bKNKuZF0N2BdtTyt02DP4LzxwMUX9zaxXo2s/7FBfFcU3FJuvYBvJNxclo8rd\nK99uOpDhoAF68Cp8f3U1xGQs9hcQFsIiZxeJK3ILBP5gp+CyPPneqHwgN07Z3h+9wvOFgwV7PuNs\nihcq9INZE5hivSIUv1J4uqxZxw2YOvj+4XtgILMDsLBUh2/CeiJHDnRXHHXa8xyHN/VEZlvP995w\nphboRlruPD5mR/ocPYK7UdxRiSWJM3aJzUcLRi955umxUm0bw6N0pSJ7JahT+I2XC34PwpktoFJK\ncnszLXBWbxz29fPMUkVIgrJLImaca+mZQRabAzDdtkZVBJfpiL95/WLyAlyEFqHx6pOn9YdqK/x8\nls+aAzMGETkfnoOlM6je/dTzj3l6Qegyttg6hacm7+dwNcr5RLP10+lmLI47KpEZMRH0JtDps/ey\nRtCY/uN6O1UaJdOhdtyZCpou6ZZrao39nAAK3hsYPS++aZgjVAM+j0HZPfDxzqTE4Wp2AHE0vEVb\nsbWOC5JkhFUEsNgxf3CZZek4tylhZBFe2qAPmca7Nr8cX+/fGwJa4zsstW1RSHzzXp+ga7T04RRj\nqKwX8lhMp83DKrFARIncMkCPhC9OchoFv6Gq/qOjB5ENUspxDy4S/IOsNdRpKsjsoA/E6+aiSeQp\n3DWa071ADqC3V/jEDFQxKj++OP+/pINq6Y1craLIugETiEcpuMZtIfeNmTtUQ9bQlnnIHSMgiiLk\nEYO/fwfSTz7trn+YBvKL5vAPEgd8EXnJTQmYglGi3iPtfYZCecyOfq3JykNYoLGzlc8l+lgHht6D\njBryf+zujUdATobQ6vmyUQSCtmPgv044olqWdpLhzoc9ASuMzv1Tf60b+vX3nQLZbSJuYh7SHxUc\nGxaQJbaAUNbtxB873Z2xQaexfwD0XIgmIrV4nTsGA8CKeZGD44WmVGfF2zAEj0Suw90pvxZ6ak52\npnNXRoiYA1GbUbaAPifn9es5nNMox1WMhiiFqkfTt6QT/LPDaI6pctEEKbhZABvzuC+AFV6ApkFQ\n9sEbC67oJqc2L/F5+EIi5bC2E4TuVw5PGllkgLBAmBS9ZJXLt8W/7AZzh2zXOiztarPYrGxcQWQi\n1NqD9kbqMfjq4GgxdfOh6GXp+/8hzguNrB0XOLT57jqu3ukdyPI/38f/tdSR8rVLm9ctklpFxIp1\natcGe6ZzLhkmrAWaEgXu+rkvalDeJJzYMCdssUggP9sbyIBqNm+bu0hs27axwtzO0aLTdEmRy7BX\n02mW+0eM4axPDPBXp7Km1zDETT9OuwhMcrmk9IDiDrbaUj5u9Is6RN5ZNoT9chv4XZJKvLR2ut3e\nQGCvbdUAVHxPLCOslYfGfXiNFdwL9ygx5Xv94ULNBynBX65Yc0v5uokgRUlQFr4KxsdMcxhnJrjd\n5mKOOdcKDyXcYKKk1YrFmxp2Mqa1iRK0gm7BoGrH6dy8ZY4obArr8X7BYzzkf4oUx8I+5e2BLyig\nSCmP33zMkZFpk/Auh1rgfxz/PbMciaPSHZvrsiCsT3mIopE+JgltnrrCcjK7GAdB5hrTS3w3SR1y\nGBavVYxjiEqnr8WlVGP5HbH08fIsOBlMX7LO5sciII0cGlRpn364mCbdp91BslmVrQoxcPaj+TC9\nO0MZi9C8aOZsUVk7GGBEye2EQ6zuEpA0PE6X2sUd4HqfaTrtQg1EivraNouAMLztKnLgN7pU/ETf\nK4iMYGGJzip/SjpXL4XIr62c0IMMYJzIXHBaTyrZ4idSxkM6S6Q/VUPOjO00HKdaRqOIH4Fl7siD\nQGdPpuIRj0b31W/7wIswcFZmCuzoZQGgj7b7P4nLZ1ugw4MHnHQ0p0zWM+A+R01iDJDTBdfEPSsz\ntVdGAoTuJ+O5nYpHMc+IAOA29tvUF0hLHKvwz719ElO2436olcY+xVc88CWad1ptcp6aodqcFyUM\nOlHeSnAgLnQRB4lEfJKprHEnN1TrjL67oHO/cABupwcFGBhTJebJn1u/nizRAVf+CKSUryUX1plf\nq1Wg9A52pO4nv4UPs5j2/i4PgDiSZY8dZu2YgE043PYJ5dEjNrmyvjaWkjFwtziqqKJ/zAwzxSfY\nFx5VOVen0XsXcoLpFHKH06Nbml4lnpDAxCdCAQlBhJagIUqVZUEIMzzBgaOUj7Y0E/Sx/MU06AAm\nb+hjKhJ4ht+9FDe3q31ngEpHms3C2CB73sGjLP85VrkgocaNNOGwWb85+dtp6SbR1oOXKGSgDIuW\nWa9nFDdb80zA/9MYuiTLZB0pGf2ysznBH4gVaJ86M27pJbE/oidnAlTQUPvFB38TOYQNTSnCNbmC\nBY/7Vz2hDC+A4DHGgWSJ/wWGblIidbsZpgHg1Xo8ekbgWacICP4eJRnFY0h99QUPrb9rr7nSKoVD\n4fgt/CUrqX9nvnFnEEI8eiWD+oHVrQKGRK6TnOP/839TpPTKpwfa5Qlp8j3ABCliKMAkPP6HOX+K\ndwjGgNzWtsIMFH+5fIx94smDLYyUxaUiQLsy44s+y54eVCf5XtKV7oMkEfvPoBAXlmhHKys2EraD\nKquLZQqsoRYc87pUW7KZ+/FGw76fQKeccRJfucdYfj2hHBcIaBuJUIPKrC592N7/WwEBhSd8nLa1\nLZKRMwzDGxXGYlmDMwf56Zf6OgqrCqSI/SnvV5mzligO5Au0AT5y8UGRR9x2hTLAohR3HhVudEXO\nowk0UJg8YDcoxxu0VpwoNbMLIcaEY1pemBsAdLqJhGMTRnneNxKrTtSgUwFN30HpP1fHg8FLhkHd\nFEhXXm6zT2mMHNhNgq8nbsHlIZj6lPdOCqJht4xkSQhmq+b4kwFjsVIOsR+y6Mo+C1vtZM89MyCi\n6SWt8fabXIQhJg+XGRqdh6vVWl5/YYso5T332zDvVQTlJAIu30bYPbZTre/xqhs/eG5/01Gy6nQd\nsONvdiK5TjgFj1gAUliaaUHi3VsgkrNExifz+rXAoecbj8lpEh36t3rEyvXjjGsAl6nV1UgQiCOU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mjmT3stzC/Xv3U+2KUtVN3IyoZysXfApjzYPxRGoY14wxVxml3cjWkid8wTZt/\nqKiZ8+DNGhOWsKqtYFfzvK3ApRuFrMQI4nmfP0ioaEsTGAw0TGjMc/edUC/KrxwpP9WbWlpcR1Mn\nyRmHmO1G980fLf1P/q5GKog5mVjHFI3YGEOry1qcHAJR2dzO40KJ0/5N3/Pxa7i6wNIJh/mHzFZ+\n31kRMiX98q/i5AnwSm6CIHRH2WptfuJJu8bOdHyEc2X/ZykVW5x17fso5tTlUjx5p+HR96FFUaBH\nlCZQUHaHREVDgLoo37xNLUuVkMHZqp9r/Bd63iatA1vtI53HEnJpU6AsMLIsCdkY+Lf82Feavy1/\nXEAxqjo7H1QoA9YuFHqbS5WP7hI7NfNQMDjoqprgcz9/UB7xC5WYr8rq2d5mgeAbnstt5tE7sQm6\nQgLlHockY4CJK8Xvmv4d4SblYXDAds1reKTgyhuI4ZtI4IEsIdiA6/FCJ2Vtw+GFFB0zIWutZ9Qg\nvRS3DxbGOPG7mDhBr7DndSkrx0aocMGbybimWSBSg54OO8poGqinGYfYKzIcnpmV8De9rNUYTd70\nICpozYFwIfHD6uW/tcf8vX5K9TD61i5pXIBimaenR5BI2PMYIhZxYqmWN5m2C4lpq7eUVSFU6cJU\nDopA56H0YzS1Yghkaz6ccapw4+IWSfmbW+U+xxGGT3wNd/C0LkyFKJzdCEZLxeZWC2Om6YAKNHn+\niFQ0gxa5wWQPwuJ8ZhYyqSk/q1Ta/GqqRzNbWLlZC4xztgz3JY1yx0g4gGXDKlO705YMD2H1sVzh\ny8FE+koC6h6l4i41cL/DFsmJm5Jqj52bd3iigktOLK6QtleXtA6WLojTYOnJOguFYPtthxaSvmGm\nqQTuLmCdlOWgPxQizNJRMRBTiuN87BktKycizvXRwigxNRv5V2btiXkJPtyPyqkLA4WN6rCMZBko\niXN3m7e9ovTge7aNZ42IWrAY75oe3jrfzduFMjJB7BHwVaV1dNpZqNe+ZP4gzGhO6yKU6gUhhLjo\nhuML+408orbEV4f3IS8O1PfQ+c9afO72/Ivqt12Iq1YNG3EKdwt+NulV+j6oevJWc1U/vV8MrQa0\nbeVkn5LMWMAilgmbX61R6wISQo0NfBGdFL7yL76BwJ5wauMZ3beZYu5smvlVxpEwVhQ8fFxH5Xpo\noihRZCSnp0L/BG8e+f6/sZJ3g939OWCjOd7v+b1g7lOXhRH12gLTb/5yvbYNu6R73tarKDzA+EDC\nV6Cjc0uuB1aWJB/N+OrNOcVXKhZcotiTMF4vDqfRNuqt4Lr8gjOQdRbrQEveoS5Z3dGPAUi07lqg\nqVZaKQNTSVTGNdFooKDV6jxrbpDI7VfHYQeRlcfaGQ1FG1NFjzlHBtwZAFGM65hXUyuLRvTsfmyJ\nKoaS6UFC1MuuQS/l45/VFm1tfQmlNWunhV0kpPrB8jg4HzKBk9f2BfqoHchtOGcUKTenprkzbPfn\nw4lemz9G4I8Lj5ly28uFVHheaCmKS4+8HGNam+xtZvyfd5dpBY8AcoNMtHr6i4UmfWaURIdijXdH\n4Bmll6uW4Pbk+DGTBh4mPSh2on/JXHVKOI+tXmcYauiEje985N91S+0Na3tbw+coqe0WLnAcRjrm\nq0HRhBFaPvHkoNwuQKN20uBjwavtz72na95RG+VD89klPSBmoG9U09U91P6sJ18GtlDxXCP0UAvS\nYwS5AWhwvu1ZBenlPuvRWL5SCxKd60mnVbKgePL10ztCgNJWKHL/tYG5erl6R7VpWRMeuAsivG4L\nvlZh1VMUk7WcEFtlQ8ewoghZgp/iUiIGdB8UYFsMC2n0jF2KlbD0qxkuacheyV42MhjTNrWOGJpP\nb8cLqovTnWaUaEQR4ox7qhg+i7lW7pFMSIP9k6dZSVrywanuiKxyZEM8txnRmifM5BWdVlFe7o4Q\n6LDdZw4TPzfPC/79pncGr4kcfXBeItIkCz2Kb37YPXMbPvCbBJ3buirX4xlN4U9Fzi5U0OI8rI/m\nxEaubhXYIo1C1wVEbMmhjjAYqm9mdtqwtK34nKt6UA8yzfBAKUcRS9C7ComgLKAnsqqYmQ6+d9du\nQEqBOA+dGyP5ei6S8XQuTmoeHBEzJtkaDcSReujBlwUYKT5jEDk0nET2T3W05RN8O+I1iuCL2zEk\nCBa9XojaCW7WnyD9fHIfIlVP3k5fyrMDshYPSJRoF+L3za8tcsFxoTB29Q6BjKAxZ/R2U7piuOIo\n3MRAXcIwBS55HqoJGM2SsAP+FtMEdbi9rvWNynjnYLT3VWrn9y4dpa1PzuBknAAIADZ1iJy8w45l\nKMoZndthreWqtx5WJ/NDeCbjKlRUXo+VcTOw5wfPGjtROIJrk+a0pBEvk9IgkLPXS67zcTg3SmX6\nqQGKLp8Q4wEM9wWWnL2h6O0wifvd8KNCNPziDdUS1b31LePR/mZo4s8QhVTskrjHFAb4QUbPl7a6\nHLudISZ7yV3Gmp6lxCIVCJYIiPkLiVfwQRSQViwIUWt6BCc960d/MqoOz0fwpsTkdjYr+EqA4FGJ\nwxJLPlTgl2lMVKdWumgkU6nREoX2fmCnx53Jl2LcDzdxTiKv4g72G/QzytkzP/3csANiNniXJKyb\nyPEYM+lewTjlwyBrvA1Hseq0rwEyuZIohPauQrtMD/CqgPghUCPc1zEUWqtbD7Cs6Wa9Q6i9cZe6\noygam6u4DqOHve4zENyA4vn6BeFcxUULrbhaf00LyIK8JhVfO3PgfxROzcPGkUTDn9lNMcgSYFw1\nF5h0O+k4KTZAuh5WmzhA07pUadrHIEWS84zpb597LkMmlP/Ir2b5DSd3a9WrRzXtffoW6wj+dqC7\npakKeVaDaFLsKew4NQn/5Gv2SSsl4XFUnLgN38g3e2L47gMZVmWlB+Y2pxNwsAyXV5zrfZ66+6NO\n/atnQFy39BdJa/QlM1kXvILZzqUOXKGZVYZLaTWJEug9PUV3sxznlaY+cyInU/Zyp4GnlbQ0XVJM\njjTgTXNLU2xwchHYZ2fBegrJgvIFGdryBZ0iiPdHvP0oKTrobiiLLzbV6OGhFV17NAM1UtiiGvmX\nCecPeJZhMWSNd1sR0zXBMsmK0TzQz9wCoe+6xVsyVVjA7V2FOPwHS/UUbVQY48xEuz3BqvoRTDza\n/Upe/JHbXSk9IhwLJhuQT51Ra6cPMWmXfgxXBAUVwMzzMx5nf38uLxEbI8HuxHJNoAr5GGRdDbDM\nvIaZdGD58IBnjKY6oHp0HRYu4WKaLDRblLUdGdvRRYTa8gDWhSNjXPohCsckVTdJP+6e2e4QOj4j\nERJFaK63X5h0QsmZOgpBr0rJwPTHnVY6GB3YKBw354eubQ9K7LofK66j6q3zT4Guf8RJUbdEAwPX\nO76Nk2K/YZetp9kO7l+c5cAIr8TwXPfl9w6+CZ8CwysJcd4GCwCkfBAE6qXqEVKayXnkzL+/gi9q\nYhodZUcg9N6TE/MQblA4jb3J2ttB1IdT6RQqaipYfiglppdRbRW1Qij7hpryOT2LWAgda1QDnOCw\nN/aRmOHe3cYkOP7spl87Ts3hk7E2Ax/UCeVxagIHpfy+FrsHZ4qiX+k649T/cfEl5rBbvmxA/xiL\nCwG9iyKqxglcf46ESxutKiDbBbgTxm51oe53JUdUJ80WTQ9/VQIlCKHVZPeWam1by0CZhhQ+FHPz\niRM7iAkCLl0ad6jbmsTBDB4Yo3j9GzlRn4OwfvkX+1X6Br/jpb7Ods5R9sYdCU8iirwHrrDeyl4P\n5Oa3TjRfEeRc/j9P7DyMx3ksTLodItG9x/vZWgOy4iFOa215lI7+X25rZS1Ummp/5i+Xpg/2bqL1\nYc6h7fbQjdpHUXjn4QUz0LYvmc+BNdDxx7TgSkeXOeHhdOTNPZBaDLDk2cy+lw8H7HLME+RVBt1k\nsXgcUBHjvvnpcteXo3EY/4mNbR/ZqLeXimXlWhSbjhCGYDzmqa5rgtz3n/CYymQhxCskPAQGw+sz\nezc1Bd1Gs8eiRp5AYUfgRpr4jbtwjt6z++6Vu8p97biVpBs1ExN2/VFrFqgpOJw9uA6QDmVZnx8t\ntsVnG09ksxL5q7LXryPT74zfhepy7+7aTH5YUpDpb2waeTIFvBdg8gmxXZB2ZJNSvEFEPglZ4KhP\ns5Wo15NcuLVfQySWiiEeFOZVqadoOuNZDghUEifrUf+33tFg6SeVx+zBDJbH89YDSGPONwYA8KZ1\nllfpAVGLBseobFKvocGgdqQf5YsUQQL2aNanPQqWDHJHr30u4IJBVKuluk8tjx90eD5z0fjoCqq3\nJds3DQnYjrQ7BU2xCixiaN26VICrnw47sIinfFcVXPidugt7ZC/KdJ/aQIVQbkrgDLjDxprUS7W1\nFffseESv5PsMOXQPCsFvlKPUCAAM4JKznpl/d5fx73jhcyMXizSXCoL3+8p/2BFB2u1ZYbisTH6V\nHLzAnIYsfS7eDvpwedtN7UZnmo/srjqJdMDTnCXrvGjHEr7252l6Ipuygr6C+WLPMQU9rrfvIwyN\n7t6vCh04Uqaszzc5CY9Aglhmwt/2Y5fx9JkGZumJynrdGXP33p2621iPJ4AevXZ3fdpNsCsmXnzc\n03cELWhMybwOw1YYoFbfYaz0s7PGleQIeLnk/884jAZTBzjHWSoLCwehSZqGTEAap+F/qiwHr9if\nuKfdQfIf1sOFlHlFnmEytGa24c0rloKQYqZPkuEVY7dS+SDs3W/Bcfs8x0goY2jaXFj4ZMP5UuTc\nyYDHI66HFcvlFknDksj2QlDgRfqZvhK4nKn/ov1YLKpHRhjo71lyHjJm2VbSQ+0OKQv8nqczLIpC\n2mynrP+VJILPijymLq5vCPGo6QllgLdqvuNKBIsJJrlMhIMyMmnRNJvVS+sTiwwsxinybxQicOf4\n34R6e7oY72ItEWWzrwJMtmMMcQrNBoRVgZsDnDu3B/iLN9B445+Ia/2xI8tg4h4bWVtfUrPF/GHF\nCCMcBaai/7iqersKU25P9YqCrW5gzK4yd6hHRVmP/GReTSC8etOcS/dQ+iH7YAw6g+VqwGCE9NNq\nrDHzSFNHzcuTFPuPTnjdDyBuk8tgZ2P8L+upWmAB8WRT08N0FYWxRVHTgdWwIb++kpR4oah3SMVh\ncMdDNeDMRXWOPYx+eoBFG4TdDky/+Rpt3Y3t+kXs5rBtuM3mN6lO/N62N0YIWBy9PPROt6ABLhjn\nkTSPxHFYPlq+2tW7Yq6PpB3gOJgIpw6Jd2FVY/nnHFVGLeti1SuPxoqA/zB+RqAZ1ugF1/HuD/no\nlOzP6btVSLptufMfKGXQlqJurAbPNswzU1SgOzKKgJWsBc8A1dZhUmmODZr7QJWHHjXRe7yJioTB\nSe+1t1P79UExlkY2Av53wBpm/Qf4fP4wQc1SW3DW0IMbQtjt9uv9/X9fGV6/G4GCcNq3idyucymc\n5DsqZ30iU7nUPo5TDk2xTfYTo5J6KDFbWg68PBTUjc9YU+xUqFwxcpfCVXhHxosuzfUSnP6d8DrK\n3sQNP4khBnas9LtuKIEewVH1iv2IiKUdT79XbsL/vFcNBq0+Sqvvg8Mk/IozOebCZTqLA+pRh8j1\nPO0dg1EYBx38k9kKMWWaaucDeaXpyGKEurCt+rNNj6O3iZ4CRZX9o1/noytgel7upuLBzZqGwGps\n73AtMGLpnD77WEcHmk7vCb/9ZIQ/1JqILIS7tWQrpz13TnS0vYnHyN54RndRSVrH3tV5/OmRT8Vr\n86wb6pLSlRI3+LytODQtXr5Pjm9zRxy6ohZ3KULiJ++p02B77O1XtFtNs3jRNxHwmT1DpOf+e3YF\n7zwucJ1nuZyIc7dAzGodikj09oxWDfGZLpGvUv8slbHALDP09Q1sZYzbZb1WMxARlYmMMbOMv6bp\nqXEGb6OxN9Z+GzBYi3Txjse2FDv2HMAimBoCXDRXlk+yVpwUiCn5LTOOrLgekPXApsjOz7wN1iAF\nuPCOno030qg47WpIfuuAkwTBNanyjM9t9kGvHBUbYvNGJkbeRm8WiEhVGVnfSDbFg1e8sBlL0Lu3\naMpK5PBpegs+vk8K2IkOGYvR5Aow1ZeA5q1rcMpEdIMR3mvYVfmtKdsviHZ0E9byAXZKlxdLV500\nemm5GQ0btI6qUDeat0/afCtAal+KQNfrpHPt/BKEshvW65onuKtkGdVhgINJh2YjRt6jDRwNZQy0\nt2/zk33lRdcQQQ8LBhOyDN4ulcQycDTY8OirqCVBDoNZ+9yHallJ2KKSJ36/U8NF0hahr7y5qtSM\nA/CkX1Sq/WW9AUQghL6/flbo6xyPz6Bk2CrrAkVR1m8WMsMYMTJzDzfobDkq/uOLuUcYSHS8GNM6\nIdJqSHQHu56KgPK0O/DnWxNXJkyeBTmFrEEAeToW3FoLlXfLwtvWmC06ciSqRnbm4gQimtKLA186\n3MaT356eSiGNv5qN+OQ8jv9hOKg17JmP9W2QWQxotOSiN3CpHK96mnBgBkpBqeksHSwkZ0Ym0Qlr\nWv4lGLAVFUI/rN/rGeRGjup/z4iwy542LcR9kEYZOCDY7F+46FcaQVcgrEM3BbZM1pZ7vMLZbBAB\nNIp2+fxvCHdPb2MYCkQJEi/lNoxzKSXQtUF/XliVdGDd/gJwms8Xkb0HYbyyJaWmfe/7DA0SWmmI\n5fHk2ePB/BvngIkwjKN6KMMHlozyCxLMBeUviR479mhHY3qV5gjKRE18cK3t6WtqD1l/r8fKmf2w\nmzxkLYc44rJqGUZqz2o47L0QXKUl4KpIGJ/PgoMPvA1kf0RdRqeBduHyjVFsKxHnVpN5TcWOPpEw\nsnzFSf8uh2B3xmR8tN3FtBy76kvQdN+6jOgMRDMtqYF7sGVg9vWPkeNNYzWk3rNC82l1Zzzx1ztQ\nJPblX9T7Eopb8dQclIpQtlVlyIvKm//abXhCgGVhBiQO4HX0Mien3FDZ990Z+ACbN0ccUL4Q1a8i\nxBtv+PWgZCeEA7utiTzOAPee3+34gAm6naicmXjXFCr2YvuZ5nD8J4hTINSaASRF8YaSrvYywwTy\n0iiBeMiahZnjX6Ra2SrDx7v34srF6/hoMCA8DyH1mFmdEUrCRgE4t6Hi1YVAINEphDeCGVVAVZ2N\nPykajTZihGf35IIRqjlR4U376Y0tBRNDAGp0Q6kPtvejvKlrZKN4G7r1lJAyP09bE7KDPRmbs/fs\nNyVC8RFydYUivRE6veitQTKDOMDm6JNj7qAaWp77cujnVGbn64Bd4xm7WZeKIKIm4aYSnUwJl5hL\nD+LcQnpAu6AAfc5YHgN5y5HYw1yEUhRnMl/L5Bjz/LberH5kV5CAMGc35Dn5CCsgW62MH0Klur3t\nqvDQ3OvhGmDL4Y2xOoW4kBC/Rjs4GjGtRYrXT4e2tlpknnpaKlAKV1YKawJ0W5ajt598+Y5C55Xi\nFrK/U1x+yGGVlKNimaW2agOl9VuEcCh6glCflnLynYngd4XXKA2JKIVNlRW01Xgdtfi10B5ipXZS\nZVEoJ/hncNBjVQcHqAeGhnptqMCqfg7CcyShKr61kfcsAc5VLbEphtId0rpP5V0qOrtNJAKxoEaN\n0ppVGEAI9TOF73jTYNy5e79+kav+WYHx6AgbaL192QJxAqG6252UlyKD+TN3wBZoObX12Adr3vX0\nj8zGgO0he4Dx9Cc1zYRKQf+J+yMSyWdmVEp+MKCbgyK6LEYoIp17fcKhZNmAg+ZS36UfkshviFTK\n+POKT3AT1fvcHL8OYw/QdRPMaLWPsOWPzcq4yVgeUMUgiaSnDUCDUB2yCO1vrkhPMwKhlhn0LwuZ\nwfM3h+czZAHuZRighzjAJUXwkEsN1Pgt9F4Ga9v4FpSBRve37ucHHuEn5jrX7b93oBywaPyG4za/\nsKerqFfobeFqou+l5uZHAWu9PB7G/36xCuN+gmjhdwI/5TjKnJGVa/Y4mrJHsK6xloq5ez4C0iUi\nDmzKDqJoGdws5uiPusdI5CZWqgii+tJ8UWOIJHe9wGCyFsM8DcbrnffJ/viThaJpSCiPR0zFv6En\nui3LW356UdHeYjk/6ZLmILb75WrZlIL0kBuk74qo9+iFxkDdId6A9FExjyh5C0dP0BDu7B53lknF\nihlFcZBGxzYFi0FbzdfCEM2K3tcVp8899GthOJgGu1N/qgTjg7ZC/hyW+NBVWOcsA/YI7H3p0zgC\nXErEvovgf4PesV8V5YrcnbNOLDkF2F+Hf+2W32/JFOuPVvcNZ0gw633lx0jeGk6zfpU4S+UqC6Z5\nlv2D7EYFebe8OBLKCmRA2kE6MXcrMBmFn7B6+0q/HxIcCLbSLBhEYooIbwK4lBvBHwt3ZNID9S46\nrlt9jHIYAJJLaDmqvniX1DClRh9zTvsHpSGG3mOKpwD1pbAsE/8AMN715F7VM9sLDloqgirm14c6\n6KaiDL34h1u3UPQcAYa/iUBBFD/omsncOZqodQoWJn1t78iJvCBlDiE/KRD+shi7MBiWR2qJzUV6\nvszTfqHmcpXqEKqJvAXBiNAYngR+GmMYIbTgB1YEwXQCZD0LToUOiwp5anTrAhDmS/ZUfyPA3O6e\nTeDJzu+g6CkNKGT6qnI9zSYRkn59rzdWimTbmd31+E9sE3oldZ7yukJKGm9HcrjmEn5iIHN2ksfy\n/bkuKAzgYebyoHDYTZZ4VZqRJkKaocRo0fbIi3zd65Gp3s5K7YmVN1cvTb30eNMvckNTr5tRJMXB\nQ1bruBwB0ntnrr5x/IGxj/XRZ7/oSwIkJdyNApk2te/birUbUR6UnGc4y4ttNTCDEuqggW3Cbfx9\n9tQdOjLwh43tPYA8H/M++ZwOf3HhfJjQQKysv0lOWY4S7ARJ3OrEoqKqyXAWdXniajcpDVbynsa8\nNsjwPf5WL5HPa+3iczXjARgydFiLFoxXOvEHjL7tJu91ngVLoHuKCc1sVCOdlfYThGi23uWH7vJ0\nYOLKmVWobVhcf5VpB8+yu1Am0dOHkBdHCr3rrgZdInlMue8oop0PLaPmJVMowyGjsverdCv6z6UE\nOqIUWtaPVpiBpHHD9Yw6XYxDCAiGibe+Gl6m/28e8Ym+QSzsogPaSQBf0SelV7KrqzHbId7aPJEq\ngRCDJzmPbD1Avv3QgG3iKsbrPI2KxWvxVP0dALSOEGlaW1luiCFhyVQZMjhvB2qkJbqeiTDhS7h7\n3EUa4i+fV/sjeR56deRJoqqk3M2q5B2q8M8jiW3dXI4Bxnmf1g7J8vrQ+iXPrLgC2JkSbeRZ/eFF\nCnM7HWHG7fLPw+dEcoxCvhyjiLG4nrEVGBWGXhUmx7lCGjGBUwRSXgUKYTNM+tVB/GGQSLqO1BXa\nqonr6lyJ9aQG7gc66GT96wZBQGclYbR4btuwY1dBNSMp+euELOd1xEiLYTm8oFfu+4GyZNtxGaNH\nQPGRCGjL34JDEnum18YLX1sqaLAaI4Vd3oohNrCZpQUGEPboSGGh1OhTL0TcjUaI1kzx5pnFFlQW\num+7966tMQzGB0widT/dnC203OehdRUxF3mVKO3vyZQS/QQL0LhvmTW6F2yZftZZwGor4BAllquC\n557VhXbkeLpl/vbtt0chG5IT/u9C7bdHihJPK9UT4R88nM21DYUK11SdT+pomG5JH2mJc3Io3YzG\nZcfbv8KIZsybNllnnP/EBy1sp1maLL9qN6kF8hDFHfB/Jr2elZJJ01JYHPOQCHNy+UA2Gl5QwPr8\nc9SHuUtr8rz+WAOCvege7emLx4Jt5ytymFbSfrvoRM+ZUxFmqe62SfHTEzg7ml6FYKGwZFzHxAVP\nqClbYQVma1hfPRcOQ2EPNB+IDQvSMtnMgfNCRvCXzR+Q+46QsNEdqQLttQrMkLWYUWQ/PxH/abKm\naMyBEKhbB0uA37pA7d7nNWme6VWCZ7Phlw4sTGZ9usfSAF2iks+dhfHFUczhnkRr5kLs2nN//1Hm\nujL9S2Xh+YR8mZbK/X/DNNxk5vMeM2BEVm1PZoxk2SRTp2R/vYNolwEbwelAj06fIHNm5MpYsL1E\n7ncTpnND/46Rp+9dC46VWjFitJhw6xYQBnAnAUgK5XKJoMd1ULWbXo9Obn6RduRPzN0a789FLdcx\n4OyYK3f61tQF3inIYC1r1HHOGDrI2xRZVZNZNDzADjAcygRu1Sw4WL8VBi/vYsKqVoNERt38KOEl\n9NyG3q3+6TPPg72wauvsj9vXnxr/ERZ9FdkR/nhOatd9PJBBtPaEAMYvPNJ01ByAr1H9v7EusrNo\ndtHZtpRoWhrKsTvw8ChWSzj4E7jptyFhnLEslaw4KGbKc0rKYK/kNZB6DrrEl2aCV7QHsdkX9Bj1\nPKcOWqa37YQlp97WsyhXrowmbd3CistDmVeRnzDx4swr7Q6boEig1BCH+1d5aIEO9ffvu2QbMvti\nAbcrVFpP6sBalPmiLjS15uhWV8KEGw781zQ4mqnoVw3oCKOuwjvvK/9OhNoout6ggrrMMfHFLop/\n7TagcwxVB59eehfgXDHC5RxEwiKlLkX4TdQk3bJgWiNKjaUI0iF5sXdRTcu76owM9bPDeFQ0zvcK\ndUkPtD7AXtk/vFhKjwLRLeB3UTz+YhoVaUH1daPHUMlMEH+eJQESKAxgCeuJAj8GZnyT7+cw0TT7\ncjpaqS0H1C0WUL6EFh9/Re8yGO0a8+1Wp5GoD3ceJ9EingExgibnx1rZ3dLJ8Hmf4F6c97FHtUGj\nWWra/KN5WoCJrdl6TSdm2vPt/3JFImXL3VxVhD1lHg5jk87q0UvPEFJbe56oPyUDYIHorFMXCtkB\nSp0+FG2szkowh6Po7B7p6lTueX4hCfE63q/RjQu0vNkacOGXYHvO/nT/7D6KtFG9OpRZwtuB5emu\nCGXEsehh9FDIFrOpVZN7q6ME4mkpcEBoVM5qdWoVt/3gUeGi7NoO+67+Xub8tmwmHzbP8nOXg3X9\nfNoTD1RXYZyvLZE4fAJJsmUmaxheX5QZ7wY+viDhcuVgAlnxxX0LLauJsgSdLdbbADd1bV5VS5Lr\n7B78FfM0LvFrQA5ay6ZN+k3078VR8KQ77wOOtuiXuls/asxNNLGEZe3j1Oqa8f4PJaCMlo6GC4Fw\nG3ADbVBwDp6yZwFL+jqVJcecF0yGso2WSscQ2vtmwXqV/rt1ntgPMcrqJSBUCsg3n8UAqSqyrJMP\nFl3aW/zxO8e34gRl8Gb+Av7qEDyqQnJbSeqv+bQRtgG85qT9oO8xyqlwpsHqHY98338C2Doe0qWE\nihq/+PAb/4nr9c5kJKMC6aqGRJYAD0fox21bybPmT4ZB2ZffeOrw36ME+hNkiBhNVDEW0j4LFPfC\nYTBRPHdDBONBGboUy+sX0hhLEFqDxD/pZ5nuulAJ1Gnpq5tYOdAVxsaLS4xVsiN6zvxKorSgpp8N\n6MetCHR0J1sVQSDbgLtEnrJ7/7F0wLUSS9jjxyJk3JHSRXyJQkLPrGjNvsgaaZ2+lUq84JavE4TW\n9WVMjvOBSoHbjCPnbFZC8a49DiHvK1W7MjjzSoFWxEqbJf55ZKbmbZgJvRBEMomcR2nX6WZLbKWd\noRt3xjhQXyyiLw7QmCKsylEF4+dhqgHIebhz0y70vdoOeqc0rMJsm2eLHLngRgytaRry7GtPEs5k\nEPzKLb4IzUud4aHQuqMS48KrQWjqCoEMqJC+/cyg0GMCPX8DoZ9NTjThi3KQ0Zm7ccl0zBlw3HJO\n4qeihfn5PUbsuXiimxdpDSOITExdNX2hgIYo6AHvcXqMa/5Srf1HuJLKLN77iqK19L2yGGkfG4cT\nPp+WIn1zd33WLqzGEEGFwucN4QrfZT0Mk0WseahDZbW80vLs1NuEfK2AfMYWc+gVKQjjNjUOEeA9\nEL0nVCajyreQL1X77MQ/Z3f7MKXlMZIKZ9st9Pqja1Wqt63i3HjrSEDh1cr7EQru3+zBo7gAIJNr\n9GzPVfhPzNmlRJyLd29w63i3/hPgjFiRB2yI01ijIow79xNLQev0WpGBJKnLZIkIGQdHfPjySCPp\nLNOOluCTX9RiV7C2yt65IAYwEE3Rmu0QeEMTSJr8M6cwP8mkQHG7TC26sVsjzhaVJ31m5gOTplWS\neyBIdXbYZgIWt1obgM5qbXkjN05FCv5jjW3R13d0x6cAu0lu1EIU8Otrn3d7K7abyyOqc6fFOCWC\nFarr8sTVDJSYHojX+adnx0hjaUrcMBbGBTKORHKWrTFaDAPouT+Wyu7oCi+Hh5VqU+mZe/qB7Kxj\nlgqWgjbbdcxQ8ViVvicBe5q/Ovu9OX/S/BryWWNVpNVVPrNNP7Ud6AruH/fVFpmbyTL55m/dllDf\nEsoSG4IV4Iq8y+AEYbXrUUN6PUiM0B/GGx4FWgf8LDcPntO8P7KQcTV6F6MLG/Me/gsMqJg9cTka\nGebbtdVE3YGk4XTN1vGthwkfPh1Bj6hbaXmcvd1KVqWndHf7ySukioyKHVdLKfaleKZQjgYrFC3+\nk9M5UF8iyFNdxOHcn2vCBKWVc1I2pd6ZMR0eYCpW3Bl+UUc551rT4YjvRrmtgQDJa6pyO3YU8u8d\n4WmETh5BlAaqkEDHrICLy8G5Yep8lSuyYflQRyJlV2xhgVqOUJTgtQij9t35ogixJNN+XdeAvnZN\nYp/xoGGboGv2dQbh1AB6/hISTyoeoxiUiY8Nc+wJ43jxi7Zof2SnRGiGZO+DEU5xvGRXl2Ws30bG\nF6+Am3Fvx6BC8+k+3uh9EM9dWQfSBMnHdb3idchTHaECxrWgQ6YbLbIwFuEO5ZH79Vq0tBc5et4I\nGX9TavQlby9lMDPpsiWQoFMzvCBc3iZ+lZJau9LWocl+f/9BM5rtOdI0HmACQiXtU54IhGtfHCn8\navgoEX6YeYOtrL13mkeqZNMTwp9lDG2/ChB8jfBoeD2759DTTH3o0cL9Sf5OTcuPA3V6/lQNTJTO\nF17UEFBwpnizy/n8XdzKpjU+gDcJsRcp/WGYombRXjSxfOEcYeRGaNBkgmqcV6xbHB9voCeSyNZQ\n3NYbjLsDuHnQ5i0saD+Yo1ryDiGFJoetyr6nXA1l8onA/40QGdAL14rfQV6HmaKHRVYCsF5tQoxH\nG29OdGuI0EVOUfIt+T29zFbaLde+rv8aqiogYctNjvILupJVMCrUy3eB1cYL1r4cE8vDpaIrVw3S\nlXsgoXh2LK7PC3REaCHJDLS9oq0Nxu43MiAuaSZ6DZp0U5rHH4DcUGKGK4LxiKC1fKZB2YXk8CXg\n4JmMulWsBZyVc1Hs2STEooc5NEZRynFPyNx6sPwUKpBlwvxgPIz8ashYeArr7pgtazIlQCV8RsbB\no3WNCfSTrHDscYbNhNGSN15ujTXyZIxf0xmw1NxhW4VE0LbVbU4Q9muynFksh/f+O3sz79eTs2Wk\ncj94qweFDzzDSKfo+fYFxr35zCg/FefHqD9FPNrkArUiafPmFRWLGkm6SWycHTHW2dmOUxqBLDnS\nKOU4i53LrnwJtNlnnNbR9vCnTV3HZkrvTaGD1GJiRzC/es+XDUFHEb7YDM8JUKlRbU33uV+CnXcq\nE5Afnqcfch6xTfp4W24eBeAxeKZEXYdjLxisOYvQ03BbLnt/ao+HyqjiaVos86B9Z8guiTv7Y7vm\nU0QBEPyFWR0ehm2yrjUy2ZOjpN+dN8ptlOpi+8jkgisg6gYT2U8e1S2pPCrAtZwj51rEayRg6gp+\nfZ1+HBHDLTW++YMQshPGSEXZMzn40VO97CNjgrh8ovSvROZzPoujNet0XF4Xl+0pRfUzN08GGTzc\nCDNZWKvs7QQNI0+Jzy3TOqD5OoFWQbRf3ETptGJEjsxTG4xPlNBT393qN4TMLuz9Lu1DCUKN/auR\nkZ2FO6X5bGfE7IJXmo05JK9M+NQ17wS6A/rJrHFTFQG3i3U1xyCqWFjTpJJamaXa8Ap24WYvz6dc\n098Zr90dPEFqCDwe6hxyVvY5RfffPzDqQb5DMiiFBA0+l1lXQ6msvQO0/PjN67FDr+p4RuZxhV6p\nTCZm4lrQ47Q5/Asnv2QX7XT23yACOPXvT5VII5iJx66cZDW8PqcokaLa+pAtVqbgZDPxZD1C4NXw\nAoObbkqulKoJobs7EjZSIpKQqr5GCZ3QjgDDwPruhevdnzONX5uBvI19+JYqusyuR333F376uyvK\nn6F+d/zNdvSAV3gIz9JaPPEhjbKgsUOFhdyDoaXdydwVHrAB1SkIhNzpfNl62QU0h9m1rX0tPNdt\nUnlnjJPMTjVt7hS8vJhfgtk+39dFB37FS3rVDWUD/97MlcR8z6MEGzbLsGSRtQgzQXSzXL4ruX2E\n7F8oaVsrywznJGiEc+2zzA1QekJQuy5dxS2hvHftZoajaCqWhhrACvQAE5HTIr8etonzlt70MhBX\nR4L2Kdszs+cuKe7YCn41vp6yn+jkXCpOzLOekgT30vVB2cScqwhXUnoA4eD5oeMK/VvSG8OomIto\nmaCJiv0wLgJ7kJsprJEeL16mqTkMwmvay2FtiWlIWbKIs9hgg5RqP5ftklAYWiA/4wg9CMMoH2hp\nuZ1nni2cWWGynf2ne0XC1qDqennT2JyNAQtk9Jw0eXHvjVLarN4YgyFvFTr0C5rV9472azo3UE8A\ndbhgNUf94/74joOWhz9K0BX6hu6u9am3nZfHjzT8iT3pq3MtSlLDx/+vqR09j1sBXhBoyiyASoio\nhAQyBIlf137OHYUONIvyzXe1M6PgVDfdvFr6g7VVEpVZDeSgkN1SXdnbZwYBVLOYe3JTzPfiCNmw\nPL+c0DJ8OwN91pieUcftyhX8/4nraUP0jfbmoqYneAn2aizdgj+uYZDayM1DDIqG7HkWgfoTyOux\nFto6L/LvFuzFDe+ipcLHg/txvv/oK16fIF31ETqIDIKRU1LBbQAbPUwEZxC+TEnpkcr6oVT0hwHN\nJuTLW8ZHgsVNC5YQaLbTIU0uVZ2AYfXpD5jXx2DHxpFmqpwAA10PEvjjBwEXurS92XYW6Vlh3vag\nh8071PI4Y8h0dlx5dPI/VyJA5MsaecCPh9Wc3Mu9ju7CmJzmdnouyGW49lVc7T+BFgn8vY84W4Jy\n0EOJqxtbldn/b0RL9qNfkmndlxOOYUGpkoTDXOeKNtd7HyleHoQUnqsrJltt7n1TUWyBkUSvmr2e\nhIco9V0pfGLnQmBrcS8ESf7JoDfid3dd9xhfTYd7x95o4BpLRW9VbAnUv/qzO2Ql4PsXD4elhlqQ\nIX/zvEAslyulqRlaIojF5lfyR5gs5T3XDgy9J3wvtzGMB2e/OdhArVKDlyiGKVBCwObJBltJLdrm\nqQtoqvfdCn+V9EPh8P1tILiKhp/pxpNcMLi4F54Ss1mMT6eOjdsUUk2NgxCMXJ9DCe3Vzm8uyZL7\ngcN4jfAg3E1rqk3m/i6KHng7yyFwHWIWhDG1pdVdgHnmaVWwnYivlzpB/S7eNw4unSB3dd2BlnzG\nRb5PE2fCqQmV6WZPnzyEbQbON8IXydg2GwqhVl7d+KhVvB9u2DtRSUwccaSTmzQitYkii0ktito/\nOZn5ZAWREOagH6xk2jSJtB+raBOlZD/StDmobLXWmpcaSlaEkDEyTAMr+crVbeg3vAGSoSOK9IbG\nhEMMVUnbYc1PtZV+vY21I6ppYt5T/zHwORuaK4UahSEs+tc11E84gYKfibx4zaxbrR6PIWoRhFpx\nfygJGI82fQqpK8rIAfb84Z6eXjnfx8vNe3ePHTI9pkZghZ1vx44M7VPJerWd7U5zd1C45avIo7bJ\n7u6tesU5+cplrvIG+231DuhICa8DH9UF72c/JWk3FiHDqhpde5ScS3IcWx1hhrKBvi5FXoH10veQ\nlHicTS5ZPF03XuljrC096UTByid0LNhm3MEYNMhJHDAg//PphATDzK9kPRVEqWJNnUXtQxCtfaGv\nDDm9ZwguZj9gqtu4FYLLYUIYBSERRP0P3uA20WOHJw+chMy+nL/5NJ5IbO3bDpRrULtw20tfYeXd\nMEZRrVydMWKNjYU3WDHTREgJjguTG/o0uckR8jUjDqND8/aBClo3a38CpFmPcWL6ws4xn7mPX0eQ\ndm04/XpCC8K8rCxBby0gOx53dNfuWePoTZANSnjGGiUI5BxmFdAWSo6va4tcRBNNZMPM97o0kVhv\nEPnfc3/sGE1x3k8/zSHbDc8HaQOXTo9W3rmPsM1cLrN9t27Iox3uo8H8MKqn1YcA0ilt5LAjrSV+\ntUKxL0hO5/r4sVSAigD8X48thLABHsoJPxsvEF8LqbeF6ar28+m3HKCwEkXmuDsb2D9EH9UPETzk\noU7Zlu+cBilAsNow3MhIVGRoQMJ90wjs5tMHHN0coijGoZTA0lcU/s6NGNC2TOBj1w5bSDX8FKiM\nS07TxyW3rw6YTaoFIbD66Rq/NSP/31Z3DELdKtPR9xDQKSDKf8jWDeUMJczhi6nWPBQbN7UQtmrO\nLkeWuAHdvStParHRMDHlyl76hJKPEZy48fg9N9UdnO+Pd1Ald+lem+PCsHHf+OqbXStJyJ7sNQPS\njKJNQgifRKxMJxi0ijJ0y77hsBxInqwKBywtcfVKlXs5gwB5+HzKqctr1bzPf+oUVROtD4s7C8n8\nPRAVBiiazwsrGoCKpXRTQdmcPIWk5o/ljibexkeIJdZGOflQLAG79TkQP4VR589A9TEHqrbDA8Ow\niEvue5OjEfXk8v35rM5k036b2nWDRQjwgH6Ww3B4Lm4ynLAYQGTB96U9XWkAnWLiLp5m8zvFZdDi\nE+meA0JkE6eMo9xpSCwtthR9qC/ZN+oxyhOIxOtsuOB79uBllrVRyxq5F8q9Jv+a7IKcvLMc3+Sk\nZmbgOAgVLYMQnsj7C+GgRoA181qNGBLLADnDESGgJ/3VlMRVMiOvVQ+AWmMuns4aRjO7TJj0T4gj\nOtQxN5mRSOWygf4wDNFbjjzdk9Wrb+YtBxxP67a1DBY73E4f8rq4GAGOc+uA+vYPxN2cpzQMxn67\ntST3yTFSN0HU+TLzADeDsR9fli+VCAO40pjEmfvnmz8uX4ieAh1/bmsrpCB4hddDi4K7Pm6hCPVZ\nlNMu2yUJ2Gv7pSfim/c6uDmTOvuyKRHsEtHBss9V0SHiF7zsCw9jC1Gw1Z3hAWIEE9MWxlQFYCc/\nOJl2e+2sT7p7D6B+NL5udUm7nX8gB74q1PUFWPsGYpD2pu3lCBVsQcSipoVTozPzXTMu9GhiBbtD\nKMVzVgZKLQb85zYLEfk9esGkaaAa/IMlXBYyZ3KgxHNEQVVYLd/28z6Bgq4z92uZ+nUjAQQNhNbd\nihUSeLisI8jS+p0o5SqzysX2BhJTA73Dl1qC80tYYxi+Dgt6Ix5T5JgkBeZt5XKSBj+tWhDWKCDx\n6uUFw/ci6OktwfqL5KZVOMkEwPLWW0W3S4EwFRv/nqulclXjxaiEmI1qy2g3i4xu4ozAzfvuY4PX\n4TNsbHRGXKHnbUq3OX7WWl0FoO0CnTw7uzXYj3goIj+2ppauZVSQt3oGFMco07p5c7AG791rM2wx\n+pZL5s5qBaL9pScdRgmtmuslKlqootc7gQJ5OxR6mvoMhOnphhgyojQnOr+SJEtDMMD5rHlXoSgW\nUJGwt8q/XT7s+tAVwEfFZwcio0IPbQNDOOsdHChnWoWh82tTu2wWSgR7Kg3fahsm6lpYDnkid7j5\nkTGihYKRKRkvpg2Ws63TmPYjpdul3WC+b4ZOhk6v3C1IdjpjOJ5UG4l9tMkYVfoW7y024BquSO5/\nMPPdTM2nWYdjbgO42K4Zxv4zLj2NSkWZm3pkgJP8LOnt+bV9C5AceuFe2YEcYfHP2NnzCbPkW3DX\n7OB2UfViC3Mm7S4KKuGfnRC4dEAlRwcrCwYneuiP6uS0A1MNUvCnPn8WEs3qpVOweX2aJkYS5ur/\nR1bloUhVQUshGkVfjwbVCpNKA1Z9uzEmBMAoQ7XvphL37Gw4A6IF6IP0hE2sLueqpM8yW6YP/n2m\nThOWH112SQ7B6Cl1xkrSYRy2fRhCPLiOb/AIOrOXBfO7Htq4hRh8mLjn9tsBdxQiCauhjPtftHqA\nbnkLa4np5WOkVect6L/DVTK0V5YtCK3SVmMRX5+n/iH5KjTBdbJDG5zE1+cZIZUf1jHOQT1zGeYb\nPcdKviHtuX/dxA/zR96YYgE+6kvpWexwOMkvDnMeZrFWV3YA2Q4yzl1IMz7mxXAYg+xr1XhyQAHh\nbvAoPX1ZX/f/hT0d5tm7H0+hzJGpOMNmOb9uWoxbURr1oTe7Aub9LGHM7MeHGjRy0eeNA4l9a3ZY\nWaNVI8NHq1/gTMRD2P454oSx+FPyBOny6Sx3+WAXKWV4raTpFUBs/OkARVapcvZtqOP0JQyWm7PT\nCLXQurpYYnK+M5sJwh9q8N5Ymi5B7RVWKXSw3bTt5UpCMFF8w3wqLBnB20ai9FBNCmCWLZmqK1BW\nOT5Z9SWGsFad4wD/ykn7EphW/XOoLWY4gWTRReb8kUiyK4uYq3GdyedGWQMQubbwsw4Yf9XLQOCA\nveyvPmR0nXWIDyie/P517DyAPPR3QSsQaXWL6OwedlZe9/pJZvpyVuCkMvohDO0OiZBnKhw8c6g7\nQDxVJpr+PzuscPWWNvWsRleF9CtP6o3lVCPYofb5eni3/gew6UuMOOPdq96vjfol+ipMOitig/EK\n5KSSJc4ignVV1rpPdS8jKt1uRzdiIG04lIgKV/iTrGxulwFTYWn0YXZ70j00M7akJBpgtHYtEwg7\ntuFwF87SDt98jOPD/WHKwoeleWTKwDzN8dUG6rIIjciM7ttKAupuKB8zcngy2+VEd8SJsoOuiVXv\nI1jEkJzWfyF9h+BgpXXoFGfSUjm4PqBwqBTsya3TbfnxMusFwVAmhcgkODyoaBE2aPevUBLTPEyg\noXiZdFn96TTFBTSKxfbvfoWmBfJLQG+IUMH6XUArLaDvPsOewnpCrh+xOPs2VUJvRJlbOoQA8hhc\nBYFw9C/vaE8JPImPCF8Mcml3atuzrH8J+M55leKZ+Ahyde17lDJYmLaTtLVQgqkyaZyHgYJabqrL\nfvxMvqW5F5ysEsk4uLDBFDd26mKkWfaYPU1SQDCVe5TX6ZCrMoOF7QT3xo/dGRKOrgxhF80rEBSA\npbHEX09kRVpK/s7dJePfIDBOH4wslJSyr+cpQWARs1LDsRdJqfBnbx5MEQ4E2qk0F1V6P0Uu3APK\nPs8KsBhcdUXgUqbGbsEQmLHNmMsW9PItMgYMqBKVjCWjmnu7XFM+2WPGuA22GFgbq/HHjTvb4+a/\nhNHFvP4EGDou4Pq063a7EtIFFh0VzxeE8It65f8GizD4Z/YaE5NBdVql7NOdDECr3l5vqCI3HnNC\nrd00HANISl5oyA2MuYTQR+GQaXrKUzZ0cDbvQZ7P2epot1a+MCmRzUKtgRQlP3GEAOvl/z6jyNGl\n0i9gClFCTubmketbUNA8oLzc5tOCpMdeyfZX7wq1Mj84m63g4WECc1S400lGBZhiUvaRIgsEnvQo\n0/oWeneHemIMitJgnp4Mf5PvMfKmyud8ED+o05VrGt2n1P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protect end_protected\n", "num_lines": 1219}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\ngazeSTBrENHvbt5mZLx18dRtoyW+Km4t51uVxxH7ZGNnmTTcoKqZyFpOrZ3w8kS9aFoiQlh5unYf\nVMD36zgB+w==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nJaIcYFxN5pqUbzepnqrpmFHdFIYWDYoimv/QCWvvIMmet78lyyCu7OmAbUWaZA7w0zL3MGnfxCUN\nn3vQGmg/2D1qvx/q2zy23sfhZfE87aSbXcNL67XF+GYu6OLKGGPH8rnW6exQAoemSF54SZgfsVR+\nZQSjSgAEtaKfNJS48WA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfa+581mCG4lxTJxvsYAMI+Y0/3DEJVi5IASCLU/HkCRmXkai01uuifj6HPVqiueReLeiWI0bzNp5\nJVlbpO/kKqg9MkQMgg1uBw2FFsg7gfVjpDJV9TVBp9Tm4YsSrWm6yWxzb6uMaHsxRa5Y+E4WUKp7\nkFXmUM1qfaMPGyGNdQg20KAvKFwwN0302/mi6GDcLvLNvvne93tcew0yQIxg/gqJlcURIlak/g5o\ntVj030iWkuj/kKp5guYfq3gEFKVEr4SV1BC/f5KX961SkhTxXGKLNLPd//Gm7akdx9a4SnpGY1Jj\ndKETnZJbnXtrvqcZUh2N1o7nl+YTs0mjObgM4A==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nQPlIuDrSSApp/O5dvtKOql3r2+lVEipJtAA3M9T5a18Cd2E2LeOe6u54LQRqvqSgFUElg4Mk3hH/\nGPHlO6wLGkc68a2QHrQWBA8YylrYUj+OZbum9kUQm5R3TPU5Wchw/mhpqWpgPlWvyK/cO9FxrB5n\nHD5ZuDk7iJeShjEmKewIRdMZqkkvQahMZk1eJ8aT2jahULqIomSMODM8v16Cxv6S3q0ohUtT2DVH\nwOkY6nsqo58T1MDDOffgorFUWVqkQwGQ/maDu/KENCo/JCJZOAmODbmBfBAsXvg7bqGZKB9VPp6h\nTMfEboGK0PjL8yhECxqeqwtqHk+eixHOqSANVQ==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nb4dHNcYwRRv3ODYilIe7aZan8VP5sGFpEcM4Sk9B84EsHlTRadyHodV0BfhfsPQB7kezG88HW5h6\nWNkuMny+KpZj54uRmnCQmrVIyZTZC+1+fpR1i46q7pc1ZFH0ByfdNqY/66Ew72bJ3bqt98VUJ+b1\nKDNSnYmqrLKj6TtcYAc=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUFVtDvwzUgfeTJK5RQPCu5bEQXOVNdg/Ctt3LMq1WwNKEczcihJ2sl86P3NdRo0ERI8ueQtux6aa\neHgbxrha+qncx9ha9CjfRUqPzzsOn3Y7i1ixq84ynt9jVyhbj9UUv8UyPbi4K5iayWqESAXrtTyL\n4izB0qPIWl4//8zsVriy5QoAxHYuCOVTFT74KhP0GfBhGq8gl2pE4gyETTs/8CEabnJ3ERkaoy22\nqOEPUjVTsxS8vgRq8tS716SKeECQKpsy4XCSTfx1d1knluz73QztnOOUXoIisTy9nHoSAbC1cRDx\n3ja7kCl2MkDQsfmBWkq0ozzVuY4qo/oIb33DVw==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nYC06/kx9685ntAX7i3acgvLk/EwgC2VW4WVhE+P9S0QST/y6VSJ0oBWMmzsdOs5O1+nblcA3DkpX\niLfXgmvlzh61Du6yn0zIyDDTLrMYWINvRbXV5FG9pLM3G/U+6fTbBV97iUYMHPWk0A2DdkXIWMP3\nmcLuMBQc2y0dm038tnqa7fuMeTcvxPhQ4wTWwHXvp54ejwq4bTAhNgyJeExmEzOvR+zWXm2VgpLp\nqcMFWAA6nlUIG5ZF4M15/u9UyutQPOLlX5+QPwfoMVi/kyC+JK5AUrviJ1QU+rzwvU3tw3rXqAgE\nsMTi8fHZ/Nt42HIXty0cXb5zEQDuP6pPBNW6XA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nHg7KeQWoQfRjpmFIAWAFbtestpXMcHBDYTZuLUSbL+kKuRGBZWT+FXknqinVcx0pJ+q5acUTBtyX\n7dcJkS4qdpYpoaBETZeL/wcOfYFz/CcO2z0+LWoGRDW3DzXn1oRWWZyJwgJkigyMIHPH5qxsjDO6\nJPKj81fkKJMHi/vC0LbmZMiKSmWL7sQNeQyH9Dn6VLxtXovGL9yVh0SoMlG0/v81wA1TX/bXmqKJ\neUvzBU070O5AHkn3Z9WRSK5S2L7x/k+ltWDFho5jtXYcevcbA/14blQqT6/9PetAyFmzvbIS+6Sy\ncJ54zu+VswtKtSOWyzlOnfx1Jgt9q/yLpCG10A==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nn/U5obQaKe7e57D8Mwxo0WeDlQ4fxz4sWCrMViskbh2tk4bDpeUf1ENBUputMkID5xX5gqlPeFYH\n/lod/5hBiFEecXymoK17ADl/jmNo1MjfVQ/nqN6xaJWL8VqmPoJ2XUvVt/nh5gTeI6QOH0BkigMy\npLFieK53VJ/5XRJXmLUeyAKMuQYF3FZPQdvCn1NDG/xTrxv61UqQKbL35Q6DuG8ZqHIJKSJFVln1\nchCHgEOHDKo7nJ9MCjYRgwBWPGvr+w4IgHNPDhatfWTGz3wjSXmjYynT7/3ZWqR/d7FCLN+lZ/ht\nr87GH/juUmy47PmZd6QhKuuc19/j3eDrwcHg8g==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25472)\n`pragma protect data_block\nrVD/wL4DHCsEfzFEf1VoQTKecFocJw604Tk0NgO7M3ODm6t/6/biD0QPzz/Fzy1UxKBEqQ8Nxpt0\nkd5dp5nyCwOVRYlAXNcBHWyWuF3ImZ0fp1y2c4napTVULuw+XU5nSbEmfo3EFsLjHWHYarc33XNE\neccwGpgfFccdUa90fp+q6imfJMIuCWHWowLNMDGdb8ZqNKZUIE8ob6W2adzfUxW6BcwKDMhYtONy\nphGaaPcir/7ub5AXgPuxZ+H/dTq9wgn1aTqOJAp1ucnPzVq3IUtg1OC2yU2vi0qMrGvEVqZa5al3\nShGeBdw/lrrv+XpB0FfkT2KARuuSvzee9a4oDMMvB9rD6SluK40ECZ1+yy9NV8VPy1Z2E7wjjpHJ\nomuIJmTDG6P4NMgl9qjKSn4GSHvEJtg8Hs/pMVAdAds6SMK+O9p7rBsB9TJ+Jfe+EKBicHLzhqUf\nYcNZCfyCtkGAWU7HcdbTu9BHbBM7GuhixBjPG1gZBzSE0WtB6MGt0YXj5LC9B2B4gUc+LuNxNcc9\nUKE7AQ6OnNorwxgTIT1j4f2lTdDpN7naMjcc0dFrzhwLEt7EYhpH25Cb1lTtbt3ny3KVcWNrvcLk\nv09yJ3wThnjJnQl+GUiERUgWu8ROGl8TiZbUBs5yecOS/BsLolr6ykQh3uUot6ZrpLggo7e2zZy4\n3svfbA7sVv+IfBOnba21zodL6jR5Io/8RZ9dAtTSxEkwNKn6woPbXr0vzkNOcXmNshPgXMNfn7kP\nhh71P3gVjrM1Z4XR2k5FHBKIFP7xvG46B9zLPPSpe9cKzJ4DSqgt0aNr031h/E4RKIrUZmmfW0JP\nOP5eFKLhkwM5x+n5EaEHSfUgoGX++y4UkfnBJWjFbVIWdkTMzBCFia7/hFiP4k87QX08uk84BfEf\nsgKGgULddxVYXIDV7mrWaO9Cy6yLEYGh6+7ZOBVM7Zy6cqp9LP7Kc0FPdoy8x9BVG6p/reTiiw1v\nNn3v32uEnt3XP6T+LoaKu/6mrF1npJimdRr7SstYkFy0LoyzKWhUHUz/VQ3iwILTJ0JnGP770FqV\nmvyHmvHBk6MZTTlNhtcVSTTwbM0lw0LvHbExAUCD9Laa09kQXtQstGMFqjckEvN2jqCALunjsEkp\nBQy8rtux02oSB0O2baktMwI571Rh+4HmnparL2+x49hG7tthybchylTgZbFDHKBCvdQBZkzVuo3Q\nj7Y3oKUrm2bmuJSbom1St7TbGFQq8d0b0kTXHL3I2ohjaio0dcvYDfVg+yWz93shEUO3Jy4PUuCC\nxhV2WTmsBi64HHIJgemiKEoZqO3e18N4F8cdUteag8hQdvF+6ZlNnZ/ms6TH575Di4UiksGkL0FR\n3sJm4AQ9V6tp6J/S+c+1flwE89qo+Xsg1/cG+L8vSsQxqyAk/ovRsYwYHiS7Yy4/606czKjJjQLN\n/Od4Z/RzSCDTe9OkRgKnHt5zK3yQjI9keM6uYHLPJND8bpBNdWrqOdAkXjDHjM3I9U6L2JJqeXVK\njIP4ArCrIq1ZHjpvCnFaxB+/+BBdYcUPUm1A5us5vUT7+x9nSm5EoMOVcMVFqrdJ27v3WAGi6+E4\nKO2C+XigT9fiGzmzXlKKtsTeS9pPq+XJ+3ohj5rZIoPhbrKxWjCzmpLqwAJ0gNd1WFfrHgE2LOe/\nH0ryLItmrp8oOSGEdzqkIi3IjIWzEJsFuNK57sg85CLkLBrD/2GAE829x/TXqmIJN9TXeNtV2gKP\nzoR4NFQendQZY0s22N8NsE4Y00GMNZhaQdHbxhimdXjmLk0d7qaq06rLRbHcsoP5Sq1QJlF2K1qR\nCGKoiuDSQoQ4Ys7EOeerLV2n/FRB2yqoN8xeHjway1HTDoAPAet9wYutlxLTBUccGt+zU65u6OaV\ns1H2YlNFqtwE716Dp39IzGvOD4w6IjA/vBYiXj/dOVHbBBfQr0u5i5m07Mu8+ql9fOGoJP2wqBln\neGByChXLhb4uLoe6Bht9vwf98nzSbRmiaYLyALBXHgZKs5L5Udkanozr2NM301M2pzP8QIPa2aQb\n64OnBA4icxCxWwz320VkF/K5BM1ObCLOipn/07v1naPYJx/9aT/ZVupp+QL9cBnPp8LZtldMFsxi\nZojdTH/u0pOw8jx+SH84VqjOEloFoTxTXkAMHKRulU7yj7ZmWlEviMhxT+f63SOqtMW6bd8ndq86\nbFiDcjGNkZC4YUerGzbOM6M+me6Qe5RcwL5VJARilQoyPMlPtvzSwMzUJQyUmabaCEispxMMZ3QX\ndNb4c+W7FDY4fxsytOmuPwhCZS3ytA1vCB92ukP2KVeOien0DKc4mIwjdBllzW9+QN+GNSzRe5LN\n/YyvlmAWUmlNSB8smtrpmB84JVKlWaXOOrpOLxRHtFaYpnmpmXJcNveKAB4LMvGTHJdEDlR6LZ5n\nCgWcU34eHvwxJ0N7D9kxlxL15EDsPFjxeT/vykJmOvcwVPmia0M2nwFaolKZW5cm0pZvf3bzkkBt\nkxFF4vDu3VKJBPN1qqR6ngJ8w5cII2VcSG+TZBxeAg/XH5mW1JuetQkNdLK940Rk85qvx9Z5tYFu\nFKrDM/P9zlRri+ggEpi73JzEUnuwXVzjIe4bn+BCJz+SYBKbr3OlasPo2GXinaCm5ZjGwKSqBbnw\nJNQvpJstSIPLThwNEK3IT7qyWtVrGoCDNiYO4H+x3es6P4VqLqh4r/0++vkRSTM4Ov8V4lO1aK+/\na/Wba1G4sbX+xCKKd66y0Rr3rr77pOo7IC0W9booS++rNRLvt64SbPyun/PqLmZi9rwotRAJRA4k\n7TXOcgtq4Ki6pKRKU7oKP5pQXRmGEVr/qGRqcX/IFcGkvR76WQxcFoASm0Yj/3Xu7bvEHJDX02tK\n4cAJxbC+4JkeI2Yc4e6V27wCtFNv8VAnJEAIJxM8w8Y+uK3Wdth00+HnMr/teyh9PAFI23BCDQ8k\nP3/TGEk+2X9AelM3jnJ1cx55xK7Y/PsWkiPKyUozhHYOyR4SaETBIxAtZ3ttpyHm7JPgipayDsI8\n7gYw9SePFZFjYEZhCtfrBAzTmKhxEJ4BYA2Yq5/1Djk3dqr1Y7XDyyIaLjVim9C05XBvKk/3JjmK\no/4wBHIRPWEui8ORGTOUvziQUj+FDTHjthpKosRq4PYd0gugZGbbhdlEj9IDDCDNxkVM9Xyk3ytf\nEqvvgLtYOih3D2Pq4LqFEqHahfAKS8ugstEsKmEWOeBnP50FSppoksT7QdPuZ9PWlAatvnkJv763\n5BXALS8jMNlPIJvelWHd2qCx6OhCgLmUmRPNd7LCMMydqv2c9uA7voFh6jp9JGAvPu53dzjWz83r\ncFeBSw11OeeiKRsJaiHddsq8L7nMEeMcZshhvcS5y26j+2tp1zr6sVBFicGgokYH1CKTQFIpiTib\nXPL5vAVDlvFDdaC5VNkFNCs76Bou5yWCTAwG2DcN88BLMV7QS7M/iGZSbCw8JV01LKDRqeheVsxP\njaLYS5XkKHDpYtsCzcVvCn6u+nDFLOLhz20cYL4vxwmt1pMKikYG15ONmScVDm5/xQBKe7nWsOKz\nSN1w6zj36KQ/C80gFY0GXtFZkG2CqAMt0M3uDfWx3VKuW6ObJNUb3R0TpZri4OwLbrrUpL5UT8yt\nITdov+Beft7qZpxoMu9KLHhncLx4TJH0gBzyTVfAPg4ljeaBsL7cmVfDmZ1PxNBQWN2/Ms5XhA42\nF3BDbS8YdOU8JUxHPgD9tCaXHqmt/co4uhm7Qtmm+DeDE3O6ljX5zbblXhS0345LHi4MFfhCkb81\nJ5XdY0hze86Ye/grd4KM1+hLV49/08mXyM5oQSWFRPGDY5ivO4n9anEwslLWZ2OKFvXtW0ZjW0tT\nRXEjOIOyE8jyr36AQDMI1LnOl15xPMnKxb/u3VpCatxnNlgTk/jzmFAD36PDOdzIPJr58KDGvKFS\nG18BSpcfrx+8cPWzVMM9M9Xk88D3Mxb+hWAv6UC/efp1x3+Hvihd9zDuubo8/FLjegZC0fa3een9\ndOTgEIsRfcfWWWdtQEDcPKuUn7WhoHt0SvpvO5dTcLaAmCPwcROmaH0teqy1XjMnZYp+sKIWZe7h\naa/hTWP68T4UHeFB8IDD9md4MZDlB/L2ac5XlcVY7UmN/GXG3pc7Gbc6uN0CzGUQcYa/v04G+11h\nT8nRzZQJdZlq0lH1U8k7gR7YudvLKtUfLHu1xmyJshSEKbRWUUdGRnwfJUm+3jGXNSoyoDu4eVa0\nmvh2E9+h8tpc6Hdxbe0/dRAb6sSYseeMuPA07z/+SsPa5oJMBS4zBtxgDX7xBkPmnOmMnJAKzWdI\n2/zXRzhP8OaEODsQLJm6++pIgkkHCqOGr6GeXrHTdMP3idL7UslwV4Lad1r2Y9+61kW7fcGSJ1KP\nG39vh0sAfFWWeb9d5TVQgwz+KIoe74xDJPYPPSkVl5kx3YFKk6vty4CYAB+5DVSd9bLaBnJ4/6l1\nJ76KqFbRsqIPDPWm7OcGTLW7JIMmU/Ofpv4nidkb4LPNVbPMfVS+Z32QG6FXVhOpIqgiKe8BfVka\nxk1jg5/fA0RQ/P5VlZhWUzEHywD2+khTh9xwSLldzJ30El7YZ++yRrsgkGW93hRzZdx/r1YMGGS/\nQBmRuRM3FKMkS0svshNKaNg8DySBg+q2X6Ky9IjA3dznU49GnthwMKhx58ThDxQ+szVA0MrLc0o9\n+rEmk+wXvMx1gpwkFLsJocOcBtoyq3atxI33E/X4g0N1mdf0f7XCxqKCPRyQfjfDQQv222kEzPfK\no/j6pJzL/bq2QCtQD62ViO655dAFs1zzuPSuwrN0eWO5sKLw4bi9ekjxE61AGmPACWDjdfaFWJ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dNrJi4eDjTX7egADR1lPi7IHJnaNzULLyzuO3tY20xdNoS1WZ9Cd6zJ3177q62zFD9IqW5Lu\nqwbBMBn9Srz8L15/PmeO818lgnRA+Obqkway5NlS5ktpFQ+pamj3jyYU+gi61IJh4yOrdmG+0YNr\nYFfUfUywA+Vb0DyVlm6VO+PiHnezjyvHEOcYEa8umdPJ9zJG7DIv0F2B2RqLChYKcamD2eAeDTbH\nfV0/YaWwv1GhQ+Ao8z4mbGlH71ah+UI4VMNU5k94werdUcmCZDFEnscd9SO86QRSF05j+ffi1CCi\nv+ySBxYK9APjuLQjNVrNKkjo3sgO/wtZFTimlVD9eKKZO3oJ+8ImII4d0IrCjHSBC0BNLtUvbme9\nmUJX8cvZmqs02dF+ATX/gcguP3DCUJDAUSvbg94oU5zILWF5KshRjRmpg3/63m3Mqua565kXaXW0\nqSB075zLeZeUTxd874xUJdwhzrCH1TkgjtNBULzc+e1zgGneUDlKpF7+GM3E4g2yPDntlKDSV4tq\nZg/J9yLjn1WZ+g3OXJp3EuqNpixt4tWc7g4zpFD+6PkEQHyikmzegOPhSHkmz2B78XcqHnVlVRT6\nu+h8+OajG4S+2zUQ2+y9ii2QR22KHBEnoriSV0FkkgCt9aEB2YKRRKtPBMXtQpeLYxm70Z3gLSUA\nW29k0A/vnaVEOuEOlY/jqfFKbKb1K4q9aVjX+++COWTPhV5kly9w8ujzb69MbaQWfX7p+PvJCGyF\nTwCS/7D3fUAjuzGmkdfDhZccW80v40olYz+LXAUl7tUuByKyy15G+0BKB5YEi6hGFv6lEz3GSGxe\n8/uUmYAPkJ1u1STOydIjaaYXqD83ZO/ZOVEKqhVutfVl2hSHLzYw6/gUFpFcMwZWXX5eOGNLl2/T\nFF4MzK6u9+0KXGdOAvATi0btUYD6QYMM1f5b1kBWZjJcC1//GBYKhkVUuwduwTVT6aj/2wzH5gz7\nQ8qEmTw4zYRBtJXQgOs/voolLCe3EfZEyqm2uQ/r1PchYuV1+d7io3uQFszexWSuf/eYepqWnq/v\nz2Gz7GegP8v46bRpzZKV61eoGO59seLhOTjvp7L/gdDO8xjlrHxYtOpMrNrj06dtbzUUacmPBceR\nd/N3VW3ovm04JbtMLrbwXdgY4PIFgeC5ldjlU2bnibhXKkE2/MjYx8B5HonlmJU3YGnjfnMzuVhi\nsfVEj1uJaRWKiNw0ZAITwD1bMfhDZShTe0WQqn6LrI1/UH5oUhqovpbWw70bz+ENp+D4TDwsZS0s\nSpmlHT0fP8DbRP044UI6dumqUBh6K1XNWgERFQD7UXK8EUV+Idp/rnr1NbNDOlaD0+dhG+p4Id+F\niQe8It9F8OXKRtsV/b7VJ70PE+RuIgrdPemrpm67UkBWnBSKixKvX9kJd4ecWPpr0hHeiPZFRA8U\nD+ACqk7FL3Q4yr05PC//O0H2Vym+cbqKruXPHgWLbH9CI9zSMFo/j+Fq7Aq+EDCG58e6G9X+bmFP\nH/5XNkvZhbeggLK+WQr8H9GQIZLZMQCboRvhX9u+eUuhUUvRU9gwFbtDrSz8K8kJBMzb8blG5UwM\nC2N2y41I2+paR+I2m5hEXkKM9tXl7VclIQIsYF6NoNH3ncc1x4HOPwxgUUR36L2amu/bzBn8MXVJ\nftczkKFdZiYMB5xIcDLovipakJFSH/w2xu6WVXWMOiA5kvgUvu+hbbVi6sHkQNFHYKIAjobH3q+3\nDrc09phW+ROYO+aTcQbKrIjZd71OhsV5rzwZ2JQ7ki7NSzGWrG6x8vZodBDEMCl2MIjkqJ+PHIov\ngo1cRx+oS/5Dae9iXLZjx04CKFNUWUSPyHHrfbNDyOPrdvGCTFr/67j/rGj1J8vVNCxtLm1bEQpc\nSIhvaUaLDRXNEjLHerJ79+3XQHd7IqCcBLemBhPmU+/fiAWJozadBEb+HGZqlMPDNzwkut2l43PB\n24M9Sj7odg/0kwUb+nkDDFoZdwlMwRh+gKg8uvy1/fK1j0sJaMju2Livjx2dKdE1F0GLrtHWI04A\nauTXE9SM5DeEDogTpQeQZPSjlINIteGYpH+oQKh9ZNsv/7z+zVFuvjSsLxXZy0AmwKADhVa+Xh1q\nPOrIzFEtf3FEPdGmEyelpCcZbjgkSf1KggQSt4O4YkgNwswY8tEBLIDAXDQExIjCYv/AIeVtzzzl\n+gKWU0UQjKYMVQCWH9zUlHQz8rQcLCB8EgUlMKDsQVoRJbvQR365CNfAX3W8rMVy4nTztqh7zU8Y\npTMGjwCCnBVie6sRytRY79AmqVpgvBPcuQdAMszg+wqIOS/YOXfWuVWaAHwDpxw6UNFMhWcFKSOH\n05VPD72EbnrzamjHK7JEkayKLgR8VVQaXYvT1jVmwbJ6/f9Gfy8CZaZuJJhKPAbeo8mMHuGWa9HL\nA8hVOZll51JKNbAGr5wPKjPHhfBCcWJqs7VIW00Fms/7xNFGllj/SZtUXSzpO/+2FCnmtjO36lw7\nuBLmHLf7CfjRZYUEgQLNVQA07zta/IkjSnwAojzCOOGiriJKJh6Xxrq7QrpLKKMpwb75V+Bf7UIq\nXCrPo45BCxCLgZ/361L4yE1xbmngU707NlaRF24SuFTe7juhvITEAy3wY6U7A7XsGp1GhBBNaYzx\n63YNFYggmHPw2SyXoCLq+pVuz+tvr1PMqnV3zzb1XvR/5Y4Tsp3bIfi00nNB+tv7WU3mCiKl+KDn\nWulilfdt2qcMkdt7dtmcPpClSu9KfkwSQANc0ehkxDHMf0CT2X361QRvY1BiIqs5wfHnQurPZVvW\nIHViiyTAS3AZ/VOpqQJ9UeATGNz/qAOHlu4l0AAE6xdtAPmQ/ccoAbLOCtCJRlTP4bk+mK/UXsj4\nG5Fs43hzF3JxJ4LR9C2FvUvkNnM4hsoGeWg5/PI3h1hXU7vUZJWEgYReDK1L7mkquUjzkWOBvs/Z\ndZTkag4LuLtNIBkAuT8lMHzT6gfGfl8FX5+8nSILKBx072cjdYwUpvNqyRE2Z/RnolUwJalgqWFb\njwYgWT1LgrAf9zDNpkiBuskNgatldY/dyAyHZ8aoMboKqqPiZMkqJKavv+FSK4leOWqG8/2gaZke\nxNn4gg7BPj+xor4DbD81mH/cZ6YSEZbXxAo5ynx3BpP6mXWX3Q9BVYMbSPDKd5LP/sL+FLO4lhXe\nHGsXA3ZwJficyeFbwqcUF4WXXjftNC8xtQgoYUdMYTmtiO2Wko7wUYf5VzXvf3iAJh6h+ii7bnNk\nQD8LnpXLyWkBAxCxXLS439nKagcl9eGoV9S59YSrP18BCUxHteCTtVutmEwT40IhND3eY4xiK2gJ\n1mJGaWYTHkCq+0qg0+pobyEVhuMvAbp+hax+P5gFIK4xkXaUrJY/rnaXTMMpPlU/ew3xGKHRD6Rn\naz43KtCgy0a0LgYTDuQkkWgfEbeC3Qc3rv1tAYrQoiVSwPN1Ppmyb500ZaLxhfGyslQtV6Cj8IKf\ncHcbEG1SU/vgXR+I/iJitzfGYck2dBP6Hc9bkQiJgCaJyzVJKT2nLPrMra+TZpxLjAf8bfzTaIR7\nyBzAM1+ONLzI4NZwoabqZphQMBeLgkvRZ4iutHq9/65XXwPhJ9rawATImQizNXIWZ/Xc/dBdeYci\ncXlh4cNi9lXr86kv42EtzQO8wiXxvpJNllzagqcYzoDS/2+v9gDA81y/sHczLBSXich8fCL9sHnk\n5HEPy+MWeoxHTXzk4NVKhoDg310u7DNHN/iqdC9jowVF45NxlX5xEGTagsxET2kbWxiMiA+l/seJ\n6hm9WQ5oT/E2yZHcl+/+7WtuGZN65uRALxVa5/5f/aiPVjAc+nbCopYK6mlCZQ1fe6EPe8V6UAwu\nmK6Uxk5h9aHjCoxyl5jtUOUpA3Z2E0IY5HjWDUmo2bW13KxWLnEpTdxtgduawTSy7y1brrIDV9Ou\nthZNeteFd9ZEFakDiqLVxSlFcVeSaMOlBtkUpVqZgEIwE4RUExVbKFs+H5eWDhOO8OZe9cSg9acu\nYYhr68IKC7t9VpDYX5OOgNcj2vxcsNVFwYRGOiq0HeDo2RS36LOmkhoHKBwolhA0gBjZd70RygkT\ne+ujgmuAfYLnTYLZ2nHTE2bGOp0zk1L9xPoBXxIvdp+k5T53k9MUi7R5IRINuNmzr5bC5Qfp1foo\nokZfB1U6tHv1oEOoThzFFHi5MhTQsKEn/ks7GCTg2bAFKYJNuuE7GjA61F1+6Pfp7NPIjUwbK7bN\nTlw/pFPKgsPwRciluwLrUwG/LcAxhFFcg+lpOR6KrBVha2FXaGyrxGufH4oJo5wlwekT/MUb5pmW\nZJgQFHqzjiiXpwW275Qpn8xplJiwEhsVfRYaQIzC5HzBQtBD0Z5xnctY48i77DbgIyL0hIwb/9pW\nQhRC7/N0v7qdT27P0pl+jumTiuNVZta8YTC7G0xouZu+vXxOvE/NO0wbDODHNploJXlfweCV1oyP\nI1N1H5/jXLW0L2eiuCupnTrqSGPbGlL5ABfwLqaZsT5pSY34+77u60VZWbsIexLeWmMfjCRnwqdW\nlazA/KsFkNe9O1U2719btMuPKm+/4TvoYxbpn1POEQsMuuwf9Pu5ujFjLAJq7KtmxM83P+hUfwbr\nG2G0JYCgS4d2fxUgAQiic7SD6J+PBgVi9fHwO7v/rbC/r7wgRKqfvQmlWmB1raUV5e7qFyPgMl91\nDb8DOYHV7Rpd6qEz88xkcQTRT4wIs2PzJ7zBQmRJXb+XbWW88jQEJVpOwGMGWqG33QS7T/CszEl2\n8G/UzSnCH9i0fIkX5bB8hX1jdnr9OkaiXmXu43+ixOyLIbZDRN2aRFEU4bczxAuR5mDXA3WX1DWF\n1LMX3PBCA3DIdqjhKv1+o7MLR+9Hree79XghCuZgtetNgzE+BgpYsP/L+wq4AzZceo2gx/0A3Ad2\nJHE71pWJ/OStHuQFDk7oCr02NKijAhZT/5I73DLzWpVMrpPwG0706DOFl5+bko+2xhL+vKkL4s9G\n43sC21ZYXx40qplG+nB4fhtMI7Lx12xMc6QgJO/DJGJbPIp5sPUk5yZyzFSb6vxhQcGKzF0jRKk2\nblj8QeOpzwmj2vNpKnM80a3UxpPiqfN7qiNdQV/oGE4utr7yunmZfyhLjo/uE0vfzSjmvB87f5Xq\nlSz9CuGzxhmVUGtT60TctfVAGIWcvXELEXV9HRvbEvzJ/XxlarWtZBkumvhDxv+H3/qxTBYBB3VL\nEE7GwzXzsRqrfwK5sZNZBrnzd+XIfp91Cnc96mK+7oU/+LV+A6NtqwEEdxNXA9EK6BlqTOYrfmNU\nUAyIzodRgP4dyJKUwF0WnCNbwi+WgWfKxeD6J6U5fRGoUSwKaIxOmNvBMgeSQ2eA+671h0YMe4NP\nqggDfVx9cXGcpytVWFntnxs6aQPg4qSpVOZkJHP2/oUPTaeW/+Hvyja+m3VTiajRHS+lfWABSwkq\n7pRAbCjzIbKeOM6sY4W63453Ewo296f3xh5ZY65u0scQgUyXtB48n3211e4tIIKNN/AwXo08/bhL\n8gThWAG9WhH2kzkFX3M7AZm47XgemDZnxChGhAXlif7chETEzzJtM8Ytn6zgg/ph9GV3i/Z6aun0\nmrCG0LMtrg4CJo+4mHmQUG27Gtd/PIm9eqWdt4ywk02K4gGJ67YvXnm+EhJHkApngBbKhp+I52ee\nZtUw0Li4xW6bs49i2dOUAjx86jsKeU7uJiWkirUvQ+aK37MPYTPcfME8nYmJNlOwZWzbVKfm00HL\nk0qmK6iDSmL/DSdx9VnPtGsNRFDgI1hAkSsqoGO2mCxxCyfAc48cWKxErLRoVWoO8VSl834ogKht\noeVK58ezIAHphOWtGVwz6GZwBiIy//1koxIMb3oR/qvXYhyucGPrvWOoGAHfpFsQPqwrb+rEKn03\nScU9PlrRZFhZOONC3GwM8Pssp2AOJT6RI+RXmNsMX2QRDtwDnC4vmHwen9MePiN3F/jppJhwA8RW\n/Rm1C2FX8ODUUj/mJU2oyh2u1HV75vH1uvUNFzDmB27k9IBiPpU0jjvuSXAJRPkzve4rYPV9xTL8\nfvi3Vtkjj6ahvzGVcsAVgAX4iWHLuRCHlAmMaXvPjURqSCU6XRgDTx1ia0CoytuL3y2O+KSUqBEK\nUqmtax5Wn+VzUtROS462rJdrp3YARn//1bxpXyg/j1/juWv0yJPQgUYcU3d3JuYIp8Q8jjoVodhn\nP1QPd79DXNB/Pwd711DNxOb0sk8yEPXHXc1Xcnnuz7a1WrYqeU+Ww/PpVga/3biOfdSOi339aWgB\nfndekDI0qMl0s9pWT+9CPjkyL0nbVWARb/uVgNpjHNmro4Nbj0HpFXKX9fwsBDeBmD2lgBrmbKj6\nbdRKGMZutn+k3xVU2uNfdFPeVpbC5lod/2xvC8Ful+0xSpTdyyvsUgfPwPgPtL/SOrLFT0nutxzZ\nkz8gjdMQ4dFDPg5YoKfi+ICV/qlSloXDse3ooI5N1ZuDqcKdcXjzm46vsfHbCZCzGxIgo+W3tT29\nAKYT0/xSqJTbX1kkMmCMOiQqCfGf29k8J1SaP1lrOC5l1AA8nrKBjm3OvciG8hf+5r02GNnwBp8Z\nZDCjx/Atsr+9LAHvecc6HiHJPuNCINcP5TLiSfF0jgcdsQm3869+RWCQUX5yLZWiVCpuQxFzPLPm\n9mjy+MRdZRDrfpkdPkHapHE3kPmPVWQXDTnhLYOgE4vdcljB4tWrpeCNm+JgRQ03G+v+wSPN9TYb\nrwX2GUhJoR/ax47EWPbYauv7LNZ2bJGfOb9s/o8KYw68eXkgj+FDljZzzP0dKUQqYjNgIw2TGCxY\ngcJ7cxv8BTZJ/JTxk7ZL577zd1AInIq0wuKBFqp2t/9tMsxSXegD0PLlzMB2fDYVGmncDtT4PzlE\nozcuiUJRipjY6DoesJlfHKyxNqJNNxjDOW3SjMiKtI8JtSQNH0BSyrRIyGNGXzX/uQArTH65IiPY\nkbNFkh5LMdN5Wn42QqnWV583GGVqmNlGzHkdprd4C+xMN4kkWbjaJVSDHQGeVbUdqT7K6j1Sa/gY\nKGZmys+BhBpakUrOXa2ouadrpwLjtjwhGHVq+zFPcxNyMBIuT43rLb116BwmRtaHmmQRa1Y9fgPg\n7LWLlkhNqEKOAPWFDQUuPpJqYr94vCP0A9arjsxYSzLkGGUsYf0r35nsW4eRMZjFyywzOyktfHup\nchvurg5EDDibgz8QtOdlGNqjerLNTRx+XGEqla27/jSiw8H1kgGrPDAeYsfAVs5y2+3WJNAsw9hT\nZzFM8t/CCIgXX2pj4yrJxSskmH6QjRspvr+VxbpVgFbgSKw/l1lDbmJDDPgX89Wmo0Bog+C8R21R\nqseSnoWZu17XsTWPMkOBeLmus/g7Aw7CMHMIYuQ4A4cJu9j0Gc6RVLvud7iLe2FMoSn0HdrObS/v\nRUAkfW832KW7aEdntoOLUdjtzOQ5QKD8YnNfz4LAzm3OhInLz/DshGnUdxR3EAL159zxjVlLZKGK\nElxu0aK5Jr8coyzWWtm+4HX92C+Qb5vXEXsmqRgIZoQPp5RpRukTUGg4zq4uAWspaTKNzxxlIEYI\npM4B/sIKkQ7sHptRAgZ/K8sDCJolRdeda8ln2ywDEJkz2nu1Kw0jm/+XghX8j1SIOG0qWiz6/Ybc\nzdbJO4Plp4J+X39ZxONVdiGg1EbaJ8UYFl+7inGY0c+VUCclN6lhgWULVKgp0ZbB3yLpKvdDBKgD\n7ZPXHoHemwi+R5aEY7fxs2S9MQcCvo7n2z8hTeHWb+DA5zq8/x/8eWhaI77HZ3DTvtkC2mVsiImR\nwjAkfk0z5JHXQ10Dqdwey7NVkAHLKwgXQG7SZFqrdI2PQV9HHw8bn3m6P+f7/EAy4MkYv8OHlwCg\nAz44PcpP9zXgPo5kl094cZivvFVVOC9A14EHv5xaRJSbue3ckHwAaVgXMonasMWqzQXHHWB4pM/2\nzq4cgM+X11VuzcRfROlRKdmu9umzZJq3sAFpM5xM4oyWtBLLHCdk+kmOffwThUPQcFT6Cp9se2Wv\nBQ3DldAMEtZ/j40qXaVivpsdHisEwN5FZQdxBMQqzZaP4UxldJ4xWKA3n61Muv4KIfoUKajddLuS\nZ5bqFL3zAkvxOf3JPUroU3wJfi2PGRcFmrNSWgp7VEHsWiBw//1PEbEYYXNzlCG322IbiY2RL6iR\nA7vI7/83fM4uY75AhDlBhuQHcEG1mL/9OfaC8TOhJiCwn2ByChDEFZhloTgtP/ZWa3aVGajOfbb2\n9X2Q7O2fzO9lBbF49OOnRLGTGH3jggbIELpZYfUF2wHdMdRJa3vJce8DTqVv771jzqUjE+fnwOv1\n269F8crvbc0cn13uXMkAyw1nN0wpG1H9l1P6jnVhrYq74DkOPEjkiK4unQKlx0aZI/YIHcAfszVM\nY0VIC2djUXZXrZlW3Y4bUmtoO4kMwI/iMgrYuA2cnHULO79HXnYXhrsdAAv9xYSiCAVQv1w7trDt\nXOmMVGvsc7eY3BpFegOKEqPqYIb5cwa75vy47XFo1zUtjPohgZ/g+MCSwqRz13l5N9vQlFSUL857\nRIPEeotyNTAsdh3vFX/jYfsonxch698ZbFLAAZ2uagiQ4oDuMeZpgeUnzcsT64lJa8GhO9cVASuE\ny0F6GpshZvVOe791qrdIB+EJ+FSESXq7IBlZ7u8nKzT3vwJbAFCmo2FIPqzBzR6n3aAQnYVuJIKN\n5Sg85UzY90qoBTGnu7wz2Z8lnZ8kGtpDSDOGhDFHBOGL1+xytbC3IeWxpkSUppE4dMh3UBtUpQpc\nrznsPHtwQusNoU5UHNl+ro08V1FXkHUs3BGo7cjO1E5mEsXECd0Yh+x/PAAC2sove1R0oZM6sGqv\n+cCCB7Vc9Az/Ei+rKcaQ7/cztvAERpeXYbhXrHeIwzJOeo6SllZ6eWAU0t9Umj75FZpWqfPlVngg\nxspwNQyDQ+pzoelgqX6CDTSoJJVBX6ypQoRpbQK004AUM2ODfMQeGrXJroVW7Dn/UvFzPHrPglZC\nHQmAG7G0MAv1OywENidA/tXzqhJYQ8VCtT2y/tKc3sh+T2PofUFs/sXPkTtUY9ALHm3DeX3H4CQP\n3Rb+ibBMospJV/C4wY8lXWgxxVCfBnLgO5r4RdQZ9iG+D+jNnqOzIsmOWgzNE+mbRYtKgPjmCs5w\nkpDjZCTmayxeTJBGAHsyCqnJxUhm0lia66LtCTkMcuB6j6i35CZ97kDpwIOi7AutER7n7lPH++Gn\nm3D321MZdm8kTkBVzTPhrnCA4JFEy+muDff1jfJIYuipA9VLqGCgficM2pPxl5PAt10RYCFRIczP\nImS8vQ89vm3/mEJLxVdbhKLSSIOUe0SyhbZ2qI77n7Pds4qv2SY5jt+R+iIhRASw7/v/kNYUxdiU\nd2whz+3cp4AylBxKxxEOrtr+SEwv9Onfj3IHTQtGHr7vZ7YgYe0YTvUebilhEDptwX6Bk4wHVH18\nELtY4IKlOENXltTlk4Fmfj2DWrqzrYwE27mXmVsBkrge382vltAomA/zHyDmmVAR9fSNI8kJqPv9\nBf0kt+ri0IU1ZZg9Woj0aa6yJritF6/2sxQwnu7hDud4nxN6agLEuHlhB37LbdL4HSPtvvRyQBEA\neetF5eYD5jUT+9nAbGZ+gGiyc7is+4wBcp5djCDST+xp/aqAUweRDNoGPk9chJw7tOrYGAsiLigf\nXAdVxBdEHR7w35WoJZOKR/ohU4uVHNlLcsqfPX8Dvr6UBD0lPGmwIq2vqjVCbdb7t6yILuEq9Ufm\nMGfARBYUMcz0CLCaO6fMddLXYb3+7JNc6BfgeNNs4c+og1l/7cS5kyAZ7etGCS4NmxOe8lgxHUWw\n8IO0tvTl6ukkA/6HFwXkZ0AbJcHifOFomjCv7anv2hOfuO9oEeFpp3WDj12n2Td+ZsWkf1AmoukR\neHaSxklqdCPcEI+UKHxQLNyr8pAOYswoRRGZbIqYW/ta17ZpL5ObFe7L0dnkTerzaK6+7QuQcXN4\nPEGg/nZtybL619pmNPfMj7PZjzIQeW/8N19FXPNLpPAoVClkPHG4Jw2tWKC4w+NgfUpUZJV5/oLG\nE0Qzbcl2mu8ISb5O1UcRkK4QStBrSta2QNvkxAkqOMW/jbQTViSnlFGnQPa3JBnvZ5xx8kSZDoL4\nzRzW+5sj6EamucW1FGMHEcaRnfoI9HYpQXf/8IyKuWe1UyYuhDL/2GkuQjpJTaIy21kze3sprXk6\nwpt1QJZ0Edtv5/8ks9db7hw2IbtXZBpSZpvE9ugD0lLiq5rPGhEahktiI7dZ3qbKT0bTXgXhrq9q\nSUMqwZoXaG/OkXvzEGInn5k3AP8V71EZfoxn5fn/UOuomkWmITLVKtg7tWd1LyrVbmJiZZFDZ7qI\np/XN53yVoQSXwoT4AshECVSbN/qX2+Qwu9Li7N8ET6x0aZ5qsJoEZr2yW2YVjQfbzCQy2cyj06/R\nMr7wwHXXa9rwr8iPvJZqmheEb7Y0AT8RjFFkICCE3TaRpLpc5GXvlm30aMqecTG2WVjbcnNiR+4F\n/C2wlDxRVm2bYvBdaKYVpicEjIE4yUAuMM8LkISEeRh569nRfVlQvmBwU9/WwXT3Ti/9jnbnlYvr\n+Ahjwb2/qNZd5qdcZoIm53BHEPFH6Vq1H/Gh/kzAJKdFN/PoXZKFLX463Mi70+9jrOYA1OiCHndK\no3zf7txPRp00vR2xJpj4unJbmpT4ffdThfuCSmKXRBTTZrgzY9yS6ftKCkee51Ztt+U6nPNlUpAN\nllyRhHkTPq060dxFuYOAoh9z58j+mdFB8eni0jqIqTlySXsVysNMX8AEngW2l89h7oV7E6W3Cthj\nLMSiKmG2/uMLyVm+c2btxBH1BiQRhQ1Rv9q39KwMbuGrzU1o1P3FtPG5HSsyJGmJtp6rDaNiiwxb\npFvHTWhTiDlj/0drNkTzFhG1JwaNzt0kOuewsLPdSir3uklbO6ecYaPK8Z4jgXerghf6lEyknZLS\nAYkKYA3rNh+45AAi1hRUOi3cp/pEHV/rSRmAPuczKvBZi/XmAqj6LGPxNcENDgMujqSw+7+uJJ0U\nQ9Yc5CELdrqvZ7mpxDFUx8QeiSww/sXE6aExkV68LMQHbrd4YaV96mjBcBLcyVqzRhLPDyuNzEFw\np4qk0TDXF1ACMNds2+Dt/Uuq9fxkmO5/q/GV1TyqO2RLP/z8GSXYvfZqOpJDtkFNGW4YcUU9OabN\nad+Q/9AomAx6BhJN0djqPBEafbnO0Jt3UVlPRE+gFekn0MvN+Tvw8vtBYQDL9VjaXZ350tmEqM5n\n8r4nQDI2NKf2AqFC1h6yx1D80OPYltLCRgU0y2GMZwp5ffMxpciUQYx48wteQkIj1vSGxelD7w3D\nFp/RHW7VRDRDzGez/pb0ZUlkmUzN7U1Eo3XRciUGIqIIUNn/ONyb3yvpQQA8wPiq1mwZIKZxyItD\n0U/CJNypm/F4npGM0VnY7fDcgFt7D29oorNPtCf2GAGAwDgKQmSNPmHVa8jJsYiuDcpw9URnTY9V\ntlH1HgWU+Tvr/riLXwOUqSufAPwmdP3p7nNAJVhufvf+5dLe5d3hxHtLxI6kjQwypWq3UBSwzQs2\nLO1+IJ1O4ds3iOra8+5J6u94UI1YsUbGYPOJwvzJ6SjHcLu8x6cWFhaUV2G6xs1fpi+7XO3lbm0y\n5W27tdy11ymOBHal9SdMg+tCFS62wxb2pPE8ZYDSXcwFxnU2QoKifLjZMYzKxXJFwweri6WL3VCt\niqEVBjol27uPCleezJI93TjZrRwL5CETU1b0nUl7hB5tni/KeEvIgKJ04f3KhE3w8g2abb6a0kXC\nuIlTQIIPxUM1ALbGJ+4f5qlVpvJ7nwT2bZ394BwTsH2S8eP241Bq2eVSuOi3Ab6tapNU4YNxIpBL\nDzcIQ/Jq3ToPenfueZrnGr3xKjeXYHJFhki5fzQIs0UkV8rvZP5qWUrko6dILN62pdzGOFJ+y4W0\nXfyMB2uKuXJv6Utx9fFydtYUyEj8Zrn90goiFM+NQU0iFdZ4QEvl1Ts+dv8/rrQH3eJTZqvI/yE3\n12TofYflRc2uRuGlx0r+Q6/3+33yPzrfr6U/aRx1N2E+vcv/L2kGVucq16ibQzJGIZqfHdBints2\nnB/xvJob2flgExd0M73QfeiBCRHzrKKyzj9Xy/YqcQjnpVZHJ0z8Khrxyx3uHHEjnFnVbod7bFEU\nc9ZV++TR2/rvd4/6tgAzf4slQhJqLWCG50xvRj+FPZPCbvxvtFnpArHuGPLhQP58M+qu8J1r6I7s\nag7qtFsFsPbykd8JxRwlB3lt4K7cNC1bKu6iSfT4vsU6XRY/ascVBykqvZDfh/zsnUvrZgmKCCBr\np5h8nDwS5zWHjQ5jShlMEqUr1g8tXsoh0g0RCOAYfHMpevkuPO3hdOrwj6+xJKkkfvuUKAJ15Siq\nsfGhPHOKEye2SzkPITZCk6Epg3vCrRweshnptUBNLAAEgZFGjAcsUQpnC+ckfUoseyAmdGwL2gw7\njQTTYXUrHvMyk+sKl6YTqd1bkaKW4kkUvaZ/rhWQefXwi759KpCKAStFGqfBO0P0buiDMWT3NQZW\nSLbgrltCu/0xvuYiq4t2Dq4pEfgQhWDCTXNAaavjbEt3oNWVDk2/oLH9DhhaEGJ7cp8+e6N6+QOS\n0bspQnURwauJmMJ8yUNYyf9ta8c40Np3aJDOareux0hbEISmQSc4Ibt8NqJFXqF7N2NWS5A+gSsi\norAZxPtzThjQ23JkrwJ0ZPNmbmcrPw1mfTOehFBdqoWPx/V1eDm5NNyriTd6LoYLbfHomQ+8WALR\nvZEOzoN+xewA5Uyk1S3+MzmEKZ3CVhK3GHoxuIMA7jpKebjYySo4sCnlQMb6qqT/bEYEyIsnWvcy\n82f7UbQc9TnIkHDhaRJw2m92dRvylHLCW54hHu6QLRMVKvHYeJNzEdtEit7GocKKSTkPn4BPI/Yi\nDB78TGR7uT3b85v7IOyxHBzEe9as39kKuQRced8pqdr9rbXMTxKG9fjurivrGePnZUbfZnOrpVRL\nkKCb+IpI64a/68XG/DR/SKALmfHrlb33vpCSd0LPcJ9gJUYGctaIA7XC5VtBzhDIcR9PBU+tTm9W\nau9psrwiInRr05n+P2ka3juxmJUvRjj+VYdfHsFkpNtAyitihSAmtBzaFQ/GCY9qd7kXWuxltG51\nrFrtLeXwN+9Dnr+9ExBWRWkyD107BNXg7Q127EZxGeVB9VR/X1KLOqjRClcK7lJrRpdva5kHRJ54\nKhRZV1sepRiHDRVCJIhJ9U6FWd/rQgWMmmcGawdgO1OX8kC5EdLJpXpkSeH5Yjqv3zzjASPu7K1e\nwWPiAxuwVgjdGKJIbluw6G5pJQ2uXDR5Xa5xsfAdroYQ0IRUvAkeOY3tND4Lkw/XVvx8KeFAWTNp\nXenmRJ5/iBqiIfM/c/rIofFpZCA5QqrNEMfQtDBkAJrxtq1sol50O0rih87WaJ+mdtwngYU7HOXS\nRQ+QLH1ciUq6EcJ73P+0hPAOokjzgjhqaori7+/iLyN1C/AWI1S59VXo4s8Lrl4s1/kVBR4QHr5V\nNiVmq4cDDDzuL1SP1j/K7bkn0GyS/RY8DPXrsujE06j3tTvjvnMGY/HaviTzAHivPGFzfXWofpT/\nFOBIBBwbn4pUVoeGWQJXIoNTcyeIxLLEOiJ2zYAUEwEdsOn+f8+dtBaERYpwAhYE4NLbwH6ple55\nRwSPKczzLDMieRAXxc+iQjGV4j/5oqHAmcwgXN7zvk/aGpMYPyA2berXcmFw0LSY1sepZIKYaWuj\noYF9Y7ElShrguXYyk1lAuvOX8VPhIpudfS7dnJHZRceapQi/Xl8DlsQg5fPaQo7gvh+5Hxbe5/dt\nsNmxiidiIGAyoTi091EqBHlEwjR9IhtjBB9469BfzhnT6ccPVCINNxJpiUBJiEOtublFQ/M7KWIP\nfC2d0pCxn06H9bmLT9zfhWsyldmMeBU9AEB2Ck/kn+c75sFlRezkk8wmqlFM2NcAvQcSf8GR2hO/\ncFxi9ZzXFOJCgdfy/9zY0YFHKKnurAgHZlgOdBl8inDgvgC2RlDXnzIuz23kNA9RxHQ2/FXl0z61\nnYwe+SCMNDzoPcUZcUBhPZonJ+3irIWLUdjkbb7qTGymgjf5KR/XMuWA/VX/8uRtjWSOc95Nbt8a\nCaci43oMh2lwO79FoeUffZYmZV3fldqnDs1ze/aOGywPwqcT1jntje94qn3lvQoQ/BJ/k93rEy+2\n5x0vRK6gNlXO4KtnS9D9Ypwk0VbvxdQ8n1IGdI8B9XTjg6ENjqtUbomhDPSFQCjwicweZXrRfUOD\nh+cPfCp22/DQgxGK2DHVgSjAS7NgTpMzbMt2/jQdh7ewO5Ek07NBPGfI47RJujdhRIoS6lFB2L5i\nM2Ly8kjyyAQreVG7AMc6P3r5WOlcr9TujTmvWGh8TOwQ1LDhVNVKJ+JGG1AzuIFYfDJBzzcZd1A5\nteF80j/Z0cUfa1hdkR4d4OTqS5QotD9WNh4QCndwopopxD6G1h9s/s5UVf0blaIfjDBU0/Nx9WVK\n6t/6Ruyhta8hQ9IxRw2VqEEY6Evx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protect end_protected\n", "num_lines": 530}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_1 (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26,\nprobe27,\nprobe28,\nprobe29,\nprobe30,\nprobe31,\nprobe32,\nprobe33,\nprobe34,\nprobe35,\nprobe36,\nprobe37,\nprobe38,\nprobe39,\nprobe40,\nprobe41,\nprobe42,\nprobe43\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [63 : 0] probe1;\ninput [1 : 0] probe2;\ninput [0 : 0] probe3;\ninput [0 : 0] probe4;\ninput [63 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [0 : 0] probe8;\ninput [0 : 0] probe9;\ninput [511 : 0] probe10;\ninput [0 : 0] probe11;\ninput [0 : 0] probe12;\ninput [1 : 0] probe13;\ninput [511 : 0] probe14;\ninput [63 : 0] probe15;\ninput [0 : 0] probe16;\ninput [2 : 0] probe17;\ninput [2 : 0] probe18;\ninput [4 : 0] probe19;\ninput [4 : 0] probe20;\ninput [7 : 0] probe21;\ninput [0 : 0] probe22;\ninput [2 : 0] probe23;\ninput [1 : 0] probe24;\ninput [4 : 0] probe25;\ninput [0 : 0] probe26;\ninput [7 : 0] probe27;\ninput [2 : 0] probe28;\ninput [1 : 0] probe29;\ninput [0 : 0] probe30;\ninput [3 : 0] probe31;\ninput [3 : 0] probe32;\ninput [3 : 0] probe33;\ninput [3 : 0] probe34;\ninput [0 : 0] probe35;\ninput [3 : 0] probe36;\ninput [3 : 0] probe37;\ninput [4 : 0] probe38;\ninput [0 : 0] probe39;\ninput [0 : 0] probe40;\ninput [0 : 0] probe41;\ninput [0 : 0] probe42;\ninput [0 : 0] probe43;\n\n\nendmodule\n", "num_lines": 149}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"ila_1,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_1,ila,{x_ipProduct=Vivado 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C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993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*)\n\nmodule ila_1 (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26,\nprobe27,\nprobe28,\nprobe29,\nprobe30,\nprobe31,\nprobe32,\nprobe33,\nprobe34,\nprobe35,\nprobe36,\nprobe37,\nprobe38,\nprobe39,\nprobe40,\nprobe41,\nprobe42,\nprobe43\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [63 : 0] probe1;\ninput [1 : 0] probe2;\ninput [0 : 0] probe3;\ninput [0 : 0] probe4;\ninput [63 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [0 : 0] probe8;\ninput [0 : 0] probe9;\ninput [511 : 0] probe10;\ninput [0 : 0] probe11;\ninput [0 : 0] probe12;\ninput [1 : 0] probe13;\ninput [511 : 0] probe14;\ninput [63 : 0] probe15;\ninput [0 : 0] probe16;\ninput [2 : 0] probe17;\ninput [2 : 0] probe18;\ninput [4 : 0] probe19;\ninput [4 : 0] probe20;\ninput [7 : 0] probe21;\ninput [0 : 0] probe22;\ninput [2 : 0] probe23;\ninput [1 : 0] probe24;\ninput [4 : 0] probe25;\ninput [0 : 0] probe26;\ninput [7 : 0] probe27;\ninput [2 : 0] probe28;\ninput [1 : 0] probe29;\ninput [0 : 0] probe30;\ninput [3 : 0] probe31;\ninput [3 : 0] probe32;\ninput [3 : 0] probe33;\ninput [3 : 0] probe34;\ninput [0 : 0] probe35;\ninput [3 : 0] probe36;\ninput [3 : 0] probe37;\ninput [4 : 0] probe38;\ninput [0 : 0] probe39;\ninput [0 : 0] probe40;\ninput [0 : 0] probe41;\ninput [0 : 0] probe42;\ninput [0 : 0] probe43;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_11_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(44),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2020),\n.C_MINOR_VERSION(2),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(0),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(4),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH 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65_MU_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT(1),\n.C_PROBE275_MU_CNT(1),\n.C_PROBE276_MU_CNT(1),\n.C_PROBE277_MU_CNT(1),\n.C_PROBE278_MU_CNT(1),\n.C_PROBE279_MU_CNT(1),\n.C_PROBE280_MU_CNT(1),\n.C_PROBE281_MU_CNT(1),\n.C_PROBE282_MU_CNT(1),\n.C_PROBE283_MU_CNT(1),\n.C_PROBE284_MU_CNT(1),\n.C_PROBE285_MU_CNT(1),\n.C_PROBE286_MU_CNT(1),\n.C_PROBE287_MU_CNT(1),\n.C_PROBE288_MU_CNT(1),\n.C_PROBE289_MU_CNT(1),\n.C_PROBE290_MU_CNT(1),\n.C_PROBE291_MU_CNT(1),\n.C_PROBE292_MU_CNT(1),\n.C_PROBE293_MU_CNT(1),\n.C_PROBE294_MU_CNT(1),\n.C_PROBE295_MU_CNT(1),\n.C_PROBE296_MU_CNT(1),\n.C_PROBE297_MU_CNT(1),\n.C_PROBE298_MU_CNT(1),\n.C_PROBE299_MU_CNT(1),\n.C_PROBE300_MU_CNT(1),\n.C_PROBE301_MU_CNT(1),\n.C_PROBE302_MU_CNT(1),\n.C_PROBE303_MU_CNT(1),\n.C_PROBE304_MU_CNT(1),\n.C_PROBE305_MU_CNT(1),\n.C_PROBE306_MU_CNT(1),\n.C_PROBE307_MU_CNT(1),\n.C_PROBE308_MU_CNT(1),\n.C_PROBE309_MU_CNT(1),\n.C_PROBE310_MU_CNT(1),\n.C_PROBE311_MU_CNT(1),\n.C_PROBE312_MU_CNT(1),\n.C_PROBE313_MU_CNT(1),\n.C_PROBE314_MU_CNT(1),\n.C_PROBE315_MU_CNT(1),\n.C_PROBE316_MU_CNT(1),\n.C_PROBE317_MU_CNT(1),\n.C_PROBE318_MU_CNT(1),\n.C_PROBE319_MU_CNT(1),\n.C_PROBE320_MU_CNT(1),\n.C_PROBE321_MU_CNT(1),\n.C_PROBE322_MU_CNT(1),\n.C_PROBE323_MU_CNT(1),\n.C_PROBE324_MU_CNT(1),\n.C_PROBE325_MU_CNT(1),\n.C_PROBE326_MU_CNT(1),\n.C_PROBE327_MU_CNT(1),\n.C_PROBE328_MU_CNT(1),\n.C_PROBE329_MU_CNT(1),\n.C_PROBE330_MU_CNT(1),\n.C_PROBE331_MU_CNT(1),\n.C_PROBE332_MU_CNT(1),\n.C_PROBE333_MU_CNT(1),\n.C_PROBE334_MU_CNT(1),\n.C_PROBE335_MU_CNT(1),\n.C_PROBE336_MU_CNT(1),\n.C_PROBE337_MU_CNT(1),\n.C_PROBE338_MU_CNT(1),\n.C_PROBE339_MU_CNT(1),\n.C_PROBE340_MU_CNT(1),\n.C_PROBE341_MU_CNT(1),\n.C_PROBE342_MU_CNT(1),\n.C_PROBE343_MU_CNT(1),\n.C_PROBE344_MU_CNT(1),\n.C_PROBE345_MU_CNT(1),\n.C_PROBE346_MU_CNT(1),\n.C_PROBE347_MU_CNT(1),\n.C_PROBE348_MU_CNT(1),\n.C_PROBE349_MU_CNT(1),\n.C_PROBE350_MU_CNT(1),\n.C_PROBE351_MU_CNT(1),\n.C_PROBE352_MU_CNT(1),\n.C_PROBE353_MU_CNT(1),\n.C_PROBE354_MU_CNT(1),\n.C_PROBE355_MU_CNT(1),\n.C_PROBE356_MU_CNT(1),\n.C_PROBE357_MU_CNT(1),\n.C_PROBE358_MU_CNT(1),\n.C_PROBE359_MU_CNT(1),\n.C_PROBE360_MU_CNT(1),\n.C_PROBE361_MU_CNT(1),\n.C_PROBE362_MU_CNT(1),\n.C_PROBE363_MU_CNT(1),\n.C_PROBE364_MU_CNT(1),\n.C_PROBE365_MU_CNT(1),\n.C_PROBE366_MU_CNT(1),\n.C_PROBE367_MU_CNT(1),\n.C_PROBE368_MU_CNT(1),\n.C_PROBE369_MU_CNT(1),\n.C_PROBE370_MU_CNT(1),\n.C_PROBE371_MU_CNT(1),\n.C_PROBE372_MU_CNT(1),\n.C_PROBE373_MU_CNT(1),\n.C_PROBE374_MU_CNT(1),\n.C_PROBE375_MU_CNT(1),\n.C_PROBE376_MU_CNT(1),\n.C_PROBE377_MU_CNT(1),\n.C_PROBE378_MU_CNT(1),\n.C_PROBE379_MU_CNT(1),\n.C_PROBE380_MU_CNT(1),\n.C_PROBE381_MU_CNT(1),\n.C_PROBE382_MU_CNT(1),\n.C_PROBE383_MU_CNT(1),\n.C_PROBE384_MU_CNT(1),\n.C_PROBE385_MU_CNT(1),\n.C_PROBE386_MU_CNT(1),\n.C_PROBE387_MU_CNT(1),\n.C_PROBE388_MU_CNT(1),\n.C_PROBE389_MU_CNT(1),\n.C_PROBE390_MU_CNT(1),\n.C_PROBE391_MU_CNT(1),\n.C_PROBE392_MU_CNT(1),\n.C_PROBE393_MU_CNT(1),\n.C_PROBE394_MU_CNT(1),\n.C_PROBE395_MU_CNT(1),\n.C_PROBE396_MU_CNT(1),\n.C_PROBE397_MU_CNT(1),\n.C_PROBE398_MU_CNT(1),\n.C_PROBE399_MU_CNT(1),\n.C_PROBE400_MU_CNT(1),\n.C_PROBE401_MU_CNT(1),\n.C_PROBE402_MU_CNT(1),\n.C_PROBE403_MU_CNT(1),\n.C_PROBE404_MU_CNT(1),\n.C_PROBE405_MU_CNT(1),\n.C_PROBE406_MU_CNT(1),\n.C_PROBE407_MU_CNT(1),\n.C_PROBE408_MU_CNT(1),\n.C_PROBE409_MU_CNT(1),\n.C_PROBE410_MU_CNT(1),\n.C_PROBE411_MU_CNT(1),\n.C_PROBE412_MU_CNT(1),\n.C_PROBE413_MU_CNT(1),\n.C_PROBE414_MU_CNT(1),\n.C_PROBE415_MU_CNT(1),\n.C_PROBE416_MU_CNT(1),\n.C_PROBE417_MU_CNT(1),\n.C_PROBE418_MU_CNT(1),\n.C_PROBE419_MU_CNT(1),\n.C_PROBE420_MU_CNT(1),\n.C_PROBE421_MU_CNT(1),\n.C_PROBE422_MU_CNT(1),\n.C_PROBE423_MU_CNT(1),\n.C_PROBE424_MU_CNT(1),\n.C_PROBE425_MU_CNT(1),\n.C_PROBE426_MU_CNT(1),\n.C_PROBE427_MU_CNT(1),\n.C_PROBE428_MU_CNT(1),\n.C_PROBE429_MU_CNT(1),\n.C_PROBE430_MU_CNT(1),\n.C_PROBE431_MU_CNT(1),\n.C_PROBE432_MU_CNT(1),\n.C_PROBE433_MU_CNT(1),\n.C_PROBE434_MU_CNT(1),\n.C_PROBE435_MU_CNT(1),\n.C_PROBE436_MU_CNT(1),\n.C_PROBE437_MU_CNT(1),\n.C_PROBE438_MU_CNT(1),\n.C_PROBE439_MU_CNT(1),\n.C_PROBE440_MU_CNT(1),\n.C_PROBE441_MU_CNT(1),\n.C_PROBE442_MU_CNT(1),\n.C_PROBE443_MU_CNT(1),\n.C_PROBE444_MU_CNT(1),\n.C_PROBE445_MU_CNT(1),\n.C_PROBE446_MU_CNT(1),\n.C_PROBE447_MU_CNT(1),\n.C_PROBE448_MU_CNT(1),\n.C_PROBE449_MU_CNT(1),\n.C_PROBE450_MU_CNT(1),\n.C_PROBE451_MU_CNT(1),\n.C_PROBE452_MU_CNT(1),\n.C_PROBE453_MU_CNT(1),\n.C_PROBE454_MU_CNT(1),\n.C_PROBE455_MU_CNT(1),\n.C_PROBE456_MU_CNT(1),\n.C_PROBE457_MU_CNT(1),\n.C_PROBE458_MU_CNT(1),\n.C_PROBE459_MU_CNT(1),\n.C_PROBE460_MU_CNT(1),\n.C_PROBE461_MU_CNT(1),\n.C_PROBE462_MU_CNT(1),\n.C_PROBE463_MU_CNT(1),\n.C_PROBE464_MU_CNT(1),\n.C_PROBE465_MU_CNT(1),\n.C_PROBE466_MU_CNT(1),\n.C_PROBE467_MU_CNT(1),\n.C_PROBE468_MU_CNT(1),\n.C_PROBE469_MU_CNT(1),\n.C_PROBE470_MU_CNT(1),\n.C_PROBE471_MU_CNT(1),\n.C_PROBE472_MU_CNT(1),\n.C_PROBE473_MU_CNT(1),\n.C_PROBE474_MU_CNT(1),\n.C_PROBE475_MU_CNT(1),\n.C_PROBE476_MU_CNT(1),\n.C_PROBE477_MU_CNT(1),\n.C_PROBE478_MU_CNT(1),\n.C_PROBE479_MU_CNT(1),\n.C_PROBE480_MU_CNT(1),\n.C_PROBE481_MU_CNT(1),\n.C_PROBE482_MU_CNT(1),\n.C_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1),\n.C_PROBE691_MU_CNT(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synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4327}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nXvoWuyjysN5V55U4xsjyWg2bXI++8I1KAZgJ0eiQkY3L8ns1PfNti9fujmr8wvFQA6ycwh4K6mSp\nINQjc8TyLQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nbD05I2IKef08FLVG4C2ftkJOY+/UsvagxY6ta+A0N1USwLQivKTmRt7LJlQ+5UJqrfPvhHMyYrLN\nrjoJbClg85XfNTYCnalRVvg3mmCcjtJkCLf6S5E9Q6UF92b6bwgtMTsr0BndJhdItlJtr0dYZtoP\nAEskMBthh6RdNMkZ3CA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nvLo4Yp/zX6HvZ92VMA2Xr4EIhMWPNGq2EvSBkjiZd5sCSFAX+37MKx4gdbrsGvhUMl1njqvSaoP7\nKrAa29/cm3QWjPgpaCsR/MhnaG5+7aUvxA5iCqVHXdriMlgx9kzxkB9SD+mOC8XR5LtYA0bPhbZ9\njQzWpWxdaOGYFF25DU0O9M7LMc7SLfKunYH/cQ91D37m0LjgZh1/uZv8chFzvCBbkHqUU0qi17/k\nZTWIIzqb1oycbuhZZrWLl95xQ/aaTxZ30sONWd/axZtO3Cd57huCbCxLuOH51qq6erD9AVszmxL8\noEoM+KW88P1S3LJ/EcIQN4LU0/nyN/f7xEmy2w==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nj99ihkoCqIO9DhRZEJdEqlRF2P+IwS2wuYmoh3hWFCDXbmGTwTqc+3EMjxY8Z4uDixuazjlTMiEH\nCk4MdTkVZ55pPhFb4druHTap3Twn20B3SWvOy2nf84OpTkdBnbK4qagABgZXs9/mAtQxbF++/F6Y\n+OOE3yUNTWvHiVGvpTJavfADkB2CL5wEIlBSnYRwtLp71JokDsMvjq2l3o3hxAjvtdg9ej7NKx4I\nkAZfrpZH7Ebv2hfXrTVI2kDTAl5Etr+4oSqxIhABJut2WaeWJrsSbL+dz9s2ZmYDMb1BCQdRexck\nbMMvUaS+P7sSGuR9BTVynHOY5GdQelHO1aazQw==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nHuzbd0U90PuPKn40554Cnki98HuQSq7dg6ZyXufEWFHsji6rteNupAY3HQsuLpXjFVxsNlS4bcHj\nAAOnDcL0hCCVbSkU011mqhhlkFmWqeBBECGfP+T7/+l9KBu+9ynszhlhaVhmZMffsEuohDl5x084\nFnzFCdxrFyvqrOyWDac=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\neoQKmSsNWNEOJcUApe0UhUNGRDkxOLedPbjyDILgUJWMG+WVCpL9MC2MXZeZ6/oVwAYRlZTZsF1h\nUsVo6BO7IAuHuJAHeIQgEs2oIMj/I2qZxm9wUsOzWoK5/Jz4SS4sTE3TgOJXaX1GNAJlbUrCBtnM\nqIiavU164vZjX5BFoPGuHp4kICN8A4Wr9y2w2Lh0/IdiHjr/Ruk5PpVNyl7tW9EaSFY1AL4aoQpd\nRFDdUFRk4tMBtmFxi/B+pLVFE0hAUZnlVCsSaf4B0lN/m4CME7lgy7oXElp7ov4fMnD9VI8HLGMX\nWBSQjD8F6BB0Wblgm9lJNc0h0VqxxD4DbRleKA==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nyrn0K+G4SU1wuMdE7DJlKWErX/N5nCqD3+dP+4ONmo8yuM983VHfjLhCoeQMbM26e49U4PPdXcDR\ny0rRemqJACoi5H5NvzXohhKZI9q+WKME4TkhFzfKvIwyta1m/uNSe/A0+52Dzbg5uAxYihw0IdZR\nZMywfa3deZ8IUMz3kWSlMs1P4wESz2pKpdYGs0FpvovucuNn4OhZKH7RGX8z8Zy4E9juZRgnSQnX\nmvRtisgVB9uL2J0vl9XjW/1990VYZi0nrZJ8gQL38HLTz62vDuMuYjiFbbnDCujJNKOCHh/xJTdt\n73nsz+dY3We4tQdnxuESibzLQLGF1l8+d9FPDA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nJPIGH1v6BG8bvo+3pHrWlum+XEDtFDlKP+4Toq88+g/eeinS/p8A0zMVVYj4wfjGDhx3kGvJ9XAx\ngxYpezvlgnz+IEGWQzepCMSp4iHz9TEdGkc5LTQj50VJj4+HGz2Qhrw96Hw0c+5RDrv238ILy3p7\nuzIPIzxKEl8D7gK6b8ZPrzx95KMPuGZyju4JUHBWdjDx0hhhIl+L3Ju/bVyWaWd7w1xI0mreJtAN\noOdcObOESJpTuj0KqFtfA3UY7v9n9Lj/I/vMaPX7LnSIZuS+tHyiD8D+t+Kf6XiIl3sYDL9erP7t\nSpHvPfG9bOfGRxM7dmsvKj+XqHeXg23wyS1Nfg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nrxmK0sxFw5opGoAsi+RHBRwE0wYNls8LL+oURMgLNuoRDOPNH7up4F86jASnrdlvXLShGHMZnaJ6\ny1orZ0uAZ6xxM2PeKAxvxBI02HOu0aXd/SMNxr16dADlCYK6R1DVdq3DC+T8bQTLWyyHr9r4m4En\nW5DcJ2hEs5b31PUg/DoCNTpHm2swT7sLG9qRkSfTddaSyGTADcvRXYjnHKHin6TQlOCZufWMm54P\nPJeCQmj1MjyycQGpsvFNX7VMxW49ashO7EGmRdy7lMGRoHDqLWBxcIlwAS4L28iuln/NdC/QV538\nQei7EbcqeUmfs07XP8FKxdA3hi3Aq2Upg9DkOw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64736)\n`pragma protect data_block\npJdOORWQloxSGvgvy0l4tBp1HqnYdonsYgNOe99SLH3qi9BP+2tNlaoelqmLJLSHNsBn3TJxXlZa\nnIZxc0/l2jA1h9Jz15QEEgUR0MqZaESeIPQdEbADnul6xUXY0J6g//n8Vnzph99nb1v9j4yp0I8W\nmF2Bvdz/qHJcUcV5zedPk5PkPVS8cmwYFQWer3rOMl6Or1E/YoHi9T9wfbgxxTs6yzqYqVGUBlz5\nAlhSoRF+xXB1Z4h2Ny4v4u05pGtbpnnDj+JhauZ7AfT+uRL3JZ7hNdSiI3coyNU077RtI/1VAmYO\npJoj/3tO2z4y9phvRShE/Otch4qxfx53IywqoRQmUF57yV4NjbkGPW8j7U6iQ8Ls1911ZAOgZIga\nmynl1jCs8ajbsNdraT0wfsPf1kWJOCuUGyItYv2eEwfh7iEYRrpT0V6YT5gENAgDuriQCZuFtnJE\ndhvImjwTXy3d76buWun43bM5pyUNSUzm90uucXHtbfsv8HZTM/chDluZJ4cMeW8D9Pwjtvo6lXLx\nYJM6v2cUpOTIMOcKDxrRTFomRQ1DwRsa4wQGal4q2dhrokLR6YNhu1ED6+AbEAN+FWui25yRPN2c\nRifAbYj3+oa+z6kUON22gegvkiRIe3iVn5MeyImok+P+5dmykiOW6L7J+GDFd4UZtYwJkwUH4ijt\ny9tlvkg7bhgKKY/VRht7EZFg6U4GjUBwLTEWIsD/6R8LgyENKTNO1FVyOJge9+hJYOxJpk93nMac\n0dR2cl0TLESIEfZQ8wSlqKcnzibNa/Mwa+gyj8uNmBtlGMv9GLnh914fnVrJPaJYjkLNLesy5uKF\nWOOHFhlsuqMHkybog57X/W2y+bzzdtaWoQ8/DU/QWGyTt3Vhlmu4YBKvv/DBB51RUj7naprx+CNR\nK7/l3uoheqcD/zy4ipVqZ/mSOTxjqNwJ88tpKUTD7UHuLf8rEeiu80iR1raYJGMHzUS7FcK/APPf\nbBCJIKpjoq1C63MJYurbOeqWcRL3DDPi/z3C66E9WG/nFKs7vMkhbVhClFUAjy+DwMCS7VjbvUvn\nCbr4m+kTXY7ipbBxU7YIDWHssBAAjeM1Rdxx9VvDqABN+rFZAA7C08PNPUeOiVYCFO3gmbAqYK8f\nEPeBaPUk6eskVX2sXw5/qrh1a5mqGk/sYCFZItuYZ6SMz1BFuaZz+ac8Feq8+d7gH2f1DuK4EG20\nOgLh0liUdRk5TCUZsSZTlhRd1FA4SqglWHYk+GIL1WEcVBskAEiY2YIK1TGXzUQaG00TT5TRBNmv\nsPnVI8z6bWwqXomyqcYSelXrfl2izqtjadlA+3+0O2A1XhL9tmMhT3v0nQIlobxn4nFE376czv08\n2+xLHI/chXlg2WvKMK3NCBbWGw7tnHSdJc47JRdiCkb0tIr9wocUbWPbM7W5G3Ku+bQZQXPM0lNy\nstFAjwukEDL4vbC72EJbEwf+6kzkzLjBrc0JDEzvjqnYQYiwloQ0qi9k/yE3bXcnEHvgw8ig5Y/S\nt9SttzL9mNMXwbouRg1seAZ89RrLrTNZiBk2TlhzdIfvWsbvdBYdIhaMqKRGJFpWxZgPm+JbW+09\nfF1z2nf/18EW+WziUuICezISE4+2HDfqFOEltKV6AdesQWDrloYiby+MezSSORPfWkx+nVGv8JEs\nI01podsuoWFRpVmbt/Dua5qZk9EOHGFBRgvYNnlH47YVREn5j8l2T/0bBlGUrv4r0tmSTvb5Rk62\nTtYvXt/3/jJe7TX05O4Uz8CDBe02LhhwyNkyyNYPm6hcqislaGMW5IrlUBR19xoKivY5xsi9WHEp\nOscK7GlXBFf+1ZdqPUIFBzo8CoanS+vY6N5dX/zhH9ka7wSGlru7qjqAyYG3VOzYi+lIUT1D0l0A\nhIuLJhQlgGIPioPMX5r9G+nJX9J1xhmQmslUobJCrtsIfoshA1m3sO8FVq/uKShEPK85uU48DmE1\nBM73G3APR/Pn3q4udJagFjB+ngJWARXqQX1U/fZdrs1d4U8E/KLlkVQywLtM4ImADW15ZRE2zwbt\n93vD21KzRF0gTEp32+Y94DZJmilvEITUz6i6Uf3GIhk/8VlW2sgoZBxyIXdlfZU0hAeWoF6z0y8i\nsz3YJBSL59bOXPeovsUY+1K4JWkThiLh9WlHMd3YfANHBPnf+imIQZm0bk8SniIn386MI5OOzHz4\nE4NRinoFBZ2QveSs8W7mDkgRcm6PoFPVY3QRUGVKM/cdavafi55CMHzsrvtIU+GTn9VIn3xNt55T\nvun82PwGiZ2FiwhlNlG8Wy4O+LFNA76IijNkkamPOoINY3NpvBlYJ4sMSw1dZ/S+Qd509gN+YqK/\njuugLi10dq5ezC717GDkCW4fL6XMF1BLctfTjFHbDnQePKJIiB57aUuvbzah60QCKQnwYsO2mNs3\nlX8Tl9YL68F88dwoxH0JclrQ/K+4uYuofKZNpcUqyesWLZ7Ajkjo1V/LWCNdqLb7jaE2Z0v+PGsJ\nbQ2zY2rbw1xVbkOFkWnJb00IZlS5AfKLW2JwtTjSc9R5cytj7Kj8rVyPRdWixjwHVXwb9oIhCtsZ\nr9zdlcsnNvnrEk8HWDJmg9t+Ss3qdeobuZBvC1qVhW9OeCSeLWFmmlBTM7zlf4bIM7BPobwINrOH\na+x81+t4Xk/8bAWK5b1pfO/q6usi0t9Z1NTJb3ix47MRkhAbStRfFBfBwzDQr/YBXixPzFiRd7RK\nKHM5pI4NGo4x/1eUa3I9iGFb0JwOlvTvmyLF4CY35sdztuKueaGq0YUi4X3SbBVUihPbcPvhcn3q\nULcb1JlytkOdtyHtyrm7/EOiSLmMn3uCPXQDioYj1f6NsIRA8BV+t4V5VK8a2hNJ+Ci6U9tBmG7R\n2AfVDNWXakk0eYIUYcZuIPVd4sH7Be8PANt6YH+bxeZtBfUel13RoATsMc/l+Vz7BvaZ9ZhPoxu0\nMpG5BKJTAuGZ3OqNXDuuvsvuBv8s5hC8JKvLoL76k+rFk8PlyNwEnYoc7nFhCrqDHeOr/8E3maxP\nPv/AiEhEzjU5PQBF457AHnjeQ3eTwpDPSnYJ6nuR0WhnaxbVcRDXmfQc5Pm+RgJOQXySVRlfAtO/\nJmM8oWf9Wd57qYf2P95KvohDPW6vlFW5UOuYJRNedw/Vofmtj6gUXmSUtZzX9x+pGUbZK1L7qaRH\n4Bl+RKLFFF3ULv72pe+uhZoyumhCUE9nTUfh/0bbyfQ0/7E4OjNceJy3IuQXZAelpm4/lyIClM6a\nbcA7XaiUNtUxRgOk+Gm4bXDK/lbpfHAo3ZLrOeIIrJSFdGgfIjMAMcPO2agXDXysM9w0LXX4XzKa\nAk5Ctu+YxqwaE3xbxVfqa3Xiwxzu9RezCh2I21Ysg1ckJugmX+s7525qUeaUizKlxcu5ef5xX40W\nh5pW3QA7UPCugDISw+aX406IO2drov2E5eUNDLRRG/nY7aG606JFGCFgUNVLl22BloATVP6ZeMDr\nmifoHBORyaJvgAndCrygYyJGcy9labne+Cqn0A1qtn323sFNB43FEMX42WIgtgc4oPab1AYsEQum\ns46nWTCUaZAyRO+53Dzben+MOJEy1iKP7o1PMZDKjaQ4Atrpot1Ix9OivbbWL8nNOjFG3rRgc8Tf\nLOVtiwqq/r+IiSB/HQOV/ZHmkDTL9dtw3UFvBE6wRo6XaWDbKDi/T7PaYAC3GGNaQZw3CTXVFb6P\nSvTMYdICAhD7YCZDr6aVLiD1Mgc225aXecHZoluSWOck9HO5ezjlCFCPDSTSj5OnC9v9zUcFbNOa\nri/TT7JdgqdBMKQjvpVrljLeuPPWvSxLMEar6iv8iFwj9w4fIGsSX5D1h0fx53Dosj7c99OjPOKJ\n43ciuUlKmUrl8zGTv1bTsvgQBspvbQjDlKlZcFGKkJ5y+h+FKT7sLG0T7X0OsNyJhlkV8Oh1B7s0\nnzc4JG92kvRVvDmVljLF5q7kSbo4pOg+r9MMh209JANj1imzsRTwNlFhL4KQmOy32YKv975WzfpE\n5gOHTY5gj/9beHVy72SphX1PvZ/GvMrFHu0Q1SdMOxiDJO/8Vv+UogST5Z+pm6YS50RKp917SJLr\npQGNrqMBt2q0TjdKoF10330Oq2OQnGbPQBcF5wAOKor3lUhuKlgi4yfTsE7g0RlphaWiUi0kfQnJ\nxJaR/v3zWkal8YKuqBUOk2zAI58JgLOCGfkeP4lLDigas6lR86dIFm2ehEwWiuUxA0rMWk7MxUFq\nIvlNP2JTSuRX5d7mSS5TdZoich5Z28tzuAxtmfX/HVgsAiDJsXeq2lNJnPI4t7OJcjw+/LTBFn4u\nGkaeVQKsrDg0XjypHHAcx3Htai3F8S3SrSZThLhmNA0UuPAVwrWM/YxdRJdPCFxRV9DIfFLc78ED\nrxRf+2hm2iIX0v9lJubvukxj3RKg3bWedHf9X7fBwzCzmT3xpSVT/orUQHTM7BJi1uX619EAPHfH\nEslFnO9xBhBE/NfxEOIr6puKJWQy0vcdu3KHp/98gdYKgnVg5mCXI4uGSJL+j3Mo34LyWj6jofG1\nRpvUjZOY2WsTY2U7akBl0Uyiv66vuAVFTYtHxbLeKihdYSSxteod2tWquqRvLeBirXL2qi69vijg\n+WXGPNEs1ioW+W6cjl9Kt1V92qIp1LbqTEC9jDdj5VHq36eM3zGGY1FX+VH47w4FoxWcrGaGXkXO\nhGXHGyLwe6ssZ273qYR1N0RhvtgHnAdUHIPdsqqRbjeld0f7uZDVEUjGCA5HvEPmaA4qaz1HEmEX\nMSbcEbGOwM4/lsTSso35cqWlqf9VepPPahniUNw1bY7j79iM/o0F8kJkfL5NumCR5VM7RsWuHT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C99kqfj/UVOTB5eheZdHy7EcqBeNR/+6GsibmPncbobTk24qcaqVJt3wgZyWp0s45X+9wMv8\naq7nxbvk+JD5cuPi785YB4Is1gg85t6bvpA9Qfzb3O9Wk32ecemuYY7hfv+wXPcCciMC61K8t1VJ\nDxofEz9Nxh0L6M2gdZhrIeECMYqp9YunMryNLeqc7YQLvKIjonC1l4sbrYWZ+Vr/tRAksYUVxldM\nWs7rdbIReyHwkW9Q3eVk5tGNZYwsTJZ3LLHqX4k4QW4fN5SrXF7tpu0Nh6B20X5kbA57dL9bI0Mg\ngdCKLlB0s2kqOmSFFGQ2qiGM4gLCtJKTcJvH0QXyq3PoTYgnvqWXAi7962ulHUUvjiqAbTLGRYQR\ngd6pRfridQ9QkVVZ3q8/Wwg9RSEsbZuIJ9bsY3KxRk+Bv/QJmfbw9otM2ufRS79SLoJDUzayREpA\nzPDRjhDoGxRqrI6rV3uPDIkmG/IgiRjrOM3CMltuf+l5zCRv72lm/BooJKYufHaSMAUyCUXJp/Uc\nFu0s9YVH+QVUDZtdn/t+XoUZ1zviEEgoAEoY2VYry4fCJ8DYaSDlP46tShiJjQrOJdERGgL/xQBx\nO6uzJrNrt7Cf6kh0YFyp6QRAfTkuf7kwETESQMUFV2MR8wr0hZHmd/UBOQiPTPb8DscsuSAYh8Zc\nrknuK0zKex9YiHkZeDo7D/PSeuh+WG2d2zJdkM3Td3eMS6WVDFMFl2b5W8/jYjNABrnjK1XwThFh\nYLnSLJi/Op7SthgN17FwYwSwj+AcsR63hVzcnfiVu3ZUXHEZJEyz2HWtWt0RLaZ7MNZccAta93yH\ngOMoJdpfeYUKCCFDGcTyJlFegiSY/R9BWXq/NR5ouF0kpaoEUa+kWjoHoOiSEaQs4XEhSuNjRynD\nrVhVZzcmzBTJAU/E9/o/Hq/uvAStcm39QbP3OeAuNYGNe3sCFCFik9NxiyTW3OEmJSjBcrOnO+Qw\nx7FcS9UJ/wQfURM4P12Z7osL0N6s5Am8NipjMtQyeAtwOcmnJoNC+0+NUiyPWlCuXP/3Z4arSgFa\nZR7xsOv//tsF4wlUna5iH3TC56YNk8nUsFEw6Ge6ZSuhEVsfIeY4wG2IxxjFm7GLEm+Qi2fnWvFp\nirwOxF+K+U92WcMWV9jGmnuJKdDgr9f0rTsSnyJoE6abD5qCwAUSiMOFTLyqf0omOu5SrdwPvxDF\ndftrQ5R+oqkHgkZje/QojcIA5MmPjkCLRdKv8Qe8et8c4lmY6vRi/j86jriaKSwx4Y+Mw85SnPR2\n2j1hg4L1bm3Y95mODLr49QGkDVB7kvY4Qy33Bsp2CTuOWo05KgZSEEXL/7U+fWGzRHjASwfcbgCg\niVFHnASo+4H+F8SItbh9vW9aZB7dvzb/sp41V3sOiSQ/lvFv36hNky3d5TPRgeWxk7ahEnAeBvcU\nN36JNzslIJ0QcFbUJcrGjbreKWGwtRudHbvZZiy3VBuJefbL+K/nA5GKYex5vaF8VvW2JtNaz6nG\nO2mf0K1OaIC26ble9NY9pYrqytCcdTpOisFBK/sWMwJTDavyPDcaK3b2r0z6l8yWe/+kZORkwM1n\n+vS+mBxXx0tf6GtBwKVn9Wq5PBEpboQb7z+jnDgqEVQGEQk44+zDxF6mTiYHaVCLhGP1x2L8Qxtw\nPkf1ixuZGNM5w3J6JjwoYA1WqjGzNXQ/2I4IFQ7+zOL2BVVm8a+5aGNvBOtcu4B12kHIJpqjtEJq\n3tU1eussVADMAsGVV8uDeYtJPvulbF/idSwsgG8crk6BAOKJo99VQxAzmHr6hzse35prsun1dsY+\ntbANM8RyL4weuRCRdH+gaMfEFjRTXyRtKzs19VCSRxpLGUewvAFPajZ9ighUQ2DOA7Kr/rcMTxxd\nrh6hpvfsAFBAQjLiKMsH8ZMXPqNGDBjA8s7TGxd1KmM66Kj1RfzFBtlBuz9LglC/dRn/arEJkYKW\ngOxCUP9SwP1tqpMfyCFKkHci/RYZqmjbNlLH12cl5zMhmsQpiIcZXYfQL8enrVutyHkc8Oplycxn\njTecEx2W4yyRww+b9SpNrQwNcQAZHfUmu5afg1rtbUHZmBW//Afpurxew4MlsTVbE/q+GW4sYS08\n5hT4/ITaA2T979WNydM1h2SItDPecKYro2NCBuNGPCj2smuGGwIqTTedt7kY0lTXqc1QprlIXDOv\n7A/WEW6Ks/DyDbzo5ebBQ9k/Or/ERzVfh5qWgkq8yG0qonueIlbVexyJM/7sKO/BjOR3x/FKDD5A\nPOch29mk1tOqyzjUVo2fdU4B2P5yIWUu4LyA1+iW0TzGEcAlb+9A3LJHWtdxf5XRYSDst39xRNq/\njlN38Ihbn61REmPKmA+LoB8LUMaREXZsyBT2mkJjbCqOmNANgzEAOIj9ceuS25Y2KtrSdejGBdIE\nvCBEfvsJHNzt4EujHKaeJh7o4NDjqLcdEp7ed4Ep3cSOHMCOA874EICbE2zaW5mDE8TG62+kJMaF\nV28mlwI5fMFxipXSTKgVDY4Vj5EWSGuC9St7IfruwsQ039cqwvbAOIuBDwEDSJc6lCmXs/qZhmZt\nnFv7j6yW+vhyh9F/M49mYXMIrZDI2IQn1meVK5DQbu4ISFnSDGJl+UGx+F0w292X7x/NZlrDFxjU\n8F8hH3SoFUjtp3cdqR6J0qgyyvNuJIK0pC2nq9IzjvH1k+PjKgFH3e23kG7suulbVb/rfU+4p0A0\nUw/8qfFdt9ZBcVINnpEPSUJScU20uwWwAzXtPblYceO4Nbetd/Rru6gMmzl4QBV6dHDFv9Llj35m\nrcJlg8L6gZdUkbc5dWUef9LywyJ3ifFwzOukFPVGj0p1G9hRSiNUqdgpYFlexuLPL30vERjJltwu\nf4LrTIZ2VSuuoDz3yvK7YYnre2MTp1IvJIRPF0FnWr5WUuDhARBzNlManehpegpS4ik+5bBOARnk\n2ikf25Ea+euX4IRwUJwiPzAGTUbPzL3cODFaJ4mHcPv972AeFd1T3djc/nkOpMRfzLbUHz1h++GZ\nfguK3eWFxgEnwvmTBOSV/2pqlydJB+j2kzDoBOhHJ7yMYPINzLTm+GvY8+PE6TGpMumpLB79DVsR\nwtH293Qaqs60uwABd29zk+xMrOUEivDU8FIBU3QFpa33/+/A4nI1MVfVSHknip/yEcpuNY2qPJsT\nYuN68cBSWDFeSQJE5yXwjpRVFkSAHd8nML/bKhBZiplgzijzI6AXJOmkqclzuE3gbvl06XzNvh5g\niwbchkuC2q85hHpT3w63G6WwlR9OlnKpzSBsWJI5MiFvl09L3irrYtbw529xtermE/blvOxQYxuJ\nA3+cCbwrhbuASE/lxx/+CQSXsAGEFsG+rJZf02gTem+flBUQWxgYw7USLAXlR/yGYO6KKUiU5mYp\nMcLp5SF0ptsnO4GjOAmsRzhq+nFaThfDeXAXowTEeuWN+d56AInospMZc/eW0bFPTbgOjid6z1Vd\n+9+s7tiYNg6b6j0iAwEiBa8LX50Gz1E8B8Xk0bA4iCfVG+pXzxngp/ZgDAxA6x4B4xS8JSzvBqG9\n3fF/tpaS1x0ZYZNKrC0vl9eX2oeN5I3CbgEuLOUU1xIlzEYHqt8Ta5ZEnYRUtbhiunpXdVyqirCN\n2dgXkldd9U31gMhMY7qFkzBGBtdUApeaRyAGLxKnyg+nwnmirKX9Y3rBKSd6L+R5qhO6n0UbbSzD\n+4en4Cmiy/ti0HItxFAe4vWNWKSwEzlKaZ2HLEPHIUlwN4xiAAyIeXLQP3SyqcvdMzkhMFVdQYhH\nM2F1yAOo3G/JqR2EjrPkiLCy80ya2Cey9fh2IrTFABUwl8LswS7gb3noQTWyDJTWhVsMOvXawU6k\n9W4Jitv0d/+g4QNb1K05p1NtcnLpsIbcTsGei35vIairYz2Wpukkc+QIjcnbRoRYwr386Jd+y7da\n3/zxTz0ylTc2RMTh2TEZRm4kwoCvMb5bRjiCs5p4VDLdB5NKcfMPq/J+LOvbN9BdKd2e8etvM1x9\nZ83qLpzhi7vatfxsU6M1tYzeP0N1fDEQPFerPkzA/sJJfcYa5H+94+uMTRANw63xIlLDhmnCm9fB\nvFsT1znWi0KNE5YxMVAP5Nj3aNk30viM/aEGcXN1+348mdh8cJXP6Se0n9M2ShPtIh6uOzHcNN4F\nXvgZxyI06BOFPCh6pPn8pM/4wkj6M+5Q3d37NGdAT8T8ei4zfuLUhoasw2cJjrdrZ3LNelT1XVzr\ngtfkU+onSthCPR4WS6Xrw7Ok/kkEQoYmkdI7UB9unluvVVQ764ldp5OlFSL6uGJlq53fikq1mMPd\nHtYt08ogxQnb+cC85LdLrpUdkov30YC0DE++eB3VOpsBoGUdgSzOw4L/wn+VuAsCWq5ABwRe4fqT\no7SyMEpq1RX0wDx7yvM1IrLxDdnN/w9pE9XQ1ww/ANlsQf3806Yc1bxBlnH0iwF7F5dr6ExWX02C\nm4GMD+POG+syw7glXgXQ0OUc8vp22qMR4sD57/Oul0voKncx2id8UccXB9vsMZIBhX8NK9iQyJK7\nYG53Y6spKPwBaJ+D6oCzIRdMrl47suvOHOFMlq9EgcKZSM8cW1EeM34Q9wneG+hmi1jxmgRg05WA\nNvs9ns0cBAUoExbeKaTDf+UdQg8kQpTj787x73pVcySGZAe6vE/iMHRuSiZo8GQ7v7UaVF9ntzDG\nTtrPWvFHyuV/SDdzax+LPSONzmqYuZtNNGc7rSFNjipVg81YgVclfSx1PGAIfydo7Z24e3Gz6NIU\nMwj2TtlQKBbeM3mx05abZdGgKr2KZg/G7mtpHcWqPBAwGoOynrpV4ZdlOI7jP3SkujjjiUQJ8FdQ\n9dU1KADRL9hr5MOS92p0+2CDZXdgK1l4EzeYC6fuN9IyAXHsqWhfswpOubjlkJfdxHP/GX3hjyHO\nUvlaWBcZDw7BAWM+AX28BwSssw+yc8sPIxzjHKVjNVz51Vpi6eQgVAZfgVeW/CVd4po9zDauDBPe\nLW3Ffrt6P9FU45qwQ7MWE7oZ3zsTc0evg2krhbb9dLqiCoz6VuCkphBd+BhX2nSPTl+BrGC3EtT8\naS6sDKIiJlBJL+8+GJ5RSEQoTGfqIs6ND98n26dELJI8S0uXSltTPxBhra5yloAd2F4/mmmPjyWr\nTQxaz9QC3JZaY5ciYNddoc6aIflLXGP2kZlT/V1zu+CW+BExE9WpMnVToGI8RRt4jv0a874Y0An6\nHhiPkeDYN6VUowNBrQ5rQnTkFaMpJk4oWUQE3v6avp7Y5alYEE4wCED+ItD2AgaKwC/nFgLMfAnZ\nktUhijy2X1yEewInb5S1xc28GWJeUEjeegaSJijHmFVUCwrnggKTZlbyJ2a2ezSse3QS7DNzMLsw\ns3lvV7VDvQazHXN8RAgvOB0B/CgfYjwZQnyysjBMCOEXr9ltmJw3ogG/vxGHBu667EeL5qOCFKZS\nK2yY/1setEN3lBeyWFiOt84crc97yyhIN9WLadvrh/f0YfzTa8/jZpqi6C6YM8s4vbQgQayL34x2\n47QkQV/JCgk47e027m4LJl2YsaOwIdm0CLnMgOgEGQPFdyZktwDaQcho9eG3wdeeDVrkyzQormhu\n9aXm2HxMwA7LFBoLoLMTe/h9G0EmWJjSZJbpYBym7mGdw7mGASxg/8DfPNQ061R+2X3xcnmG+cIO\nvl0+UTTis+WrgnTXMMvcqbanhkRzuTaNKehiSLRg6bGYM0soIp56mfxn+lCOLxRvrFVCb4SESUTQ\nh41pLzHt1noaHrzs6Gg5F6h/f/xdaHC5qixpm+GAiRp0dMj0xX0roGySULb0Pg5Ik9k6Txub6XiO\nZgO5zmj4Zg5w8I0AnXTXRWRQrHzuRzUxeqeeMsb/JspTSY5oZj06H3vlmxUcBhypLvXrMLcXh/Ls\nc3bNxQvpWzLBqqdhy2tGJ8fAWkun0YPhNwlUU8lBB4Gk06kgUQm222XRVdAheeWAjR8NbiAop06S\n8Wy+XiAj+daeCKkiouMukARqbllP0jcynVe076LG+ZgkcNqoPU37HDyH9n2pGf6ZkAQuwFeIbkSF\nPg4iQ36vkP+KaDnRItQq5Ii+DKzEOXGkFXjeyB2kGs1noDV9eD6DHXsQa0azeB+0c9fKSA7nV4Mx\n1BtiwRMnJT7JPQOciedKCuaoP0Aq+hvnG6MBlo+nAOOlQfvZ8qQxlg0laf4f6XLVWOpAeGt6y0pr\nAw0YlMDiAyvjsrh3t8P4eyWaZSoFPRIJLol9+5QCyrLlm2aVeoMUtwJ1/53pTKnTEHcZIZfi1n7e\npjP+HdzVIccamu4mef1McNibQT4nUfu60LdH+ZQICzwZKDu6slLfWc1KaTXs71UCJzmFmBNREiS2\nXy7c04shnL9MVkGQUM4rVvlqeU7hjpj2FNlt0nq2A7NHDHkEArM25UeIzO+An0jC3tn+qfMDBZmx\npl24RVKkzC2NhWcwhhc3TGrk1gzXt5aE3zkSTGv9pEL/s8V0XrlWQBLq2XFeBXgLpSAzseg2st1r\n71IH25LcYi65u03YZ8TaQSNK5ZQxrVBVO+JVdqF5H+UcYmJxyBsmvTOso+y/z+nGXXnu6Wxeb2K3\nPMCSNT7G7TIbSFmkl2cSMzEeMwmt7AyMdckkJzv6cvcC0j0fLIcJ+ygBucF6mrNY7OMFKMatX0PI\n4UdpryZPtTB7sdMGLH8FqHkw0PoHM+53+V3rRDIo+ImSU7g97SHk4uMmW9/lU3+h4QEVhf1SsCoH\nD9SCjVbJmWSx+5ck3SWahLdUTGE0c66fdQ50VOj3xxA9nvsgL6x8+drW1LZr6SHG4Ma07PvqbId/\ncOHrnVi5FevEja28niNJV/635eMPcCA8uWcnSyTm1J3Fe+CyROmWWUPs1QOJLqlM/Ai2tsSCIaui\nrBVtakmXqv0aMhA33NdtZu3vrog0aJfleoLXQUuDYIGcGc8kfavMyQBG72eZnrVz6/tupr3lLY4Q\nxVGFP4Jxgxq1oFD+d8nf2DrnUh9AyNvtyyOCKi7z+ReLuwDg4jFzd3U9eZQ7WTDxuOYKmerT5+UO\nG4qs6dNLomx30eVvW25a2Z2qtWBywQq/MaVipSr2RmdVavfkdvSb4lRU8c/OXc2j2EjLF9uwD9ij\nR+SremaAbHZZKoNbBX79rPCGwHPTuu2e/3veCG7t4yv5s3WUvVkFPocYD2rO92YBt3DE5NjJ8kgM\nBCj48v+cPe2x069u+Nco6d7scSnHpPHHPSM+6Py5/LgYVagzcTfjK8PlJARVcAMsLJiBvfzpO+zb\na4Rs26CnEdvlCgaKBV1YLeJ2dXWhGAXTQg7SIPEe+qxZanakqfbbb2xT8QLylB2wpP6fAVc2MhM7\n8GAoec89XNo9PAPakTkcl0WxeigJFRkS527gXqWbZigV+8fVkzfLL8ARih7A5Y8faOuGrHTI1D3/\nzLMHy7/g+ESSQUAfGIeRgrKCYK7EMouPFRuxC5uxAYpm5W/pKsdIPrBHWTqvC0PZClvqzFXBi97p\n9keo4Q8i5+/jCqoMSKdh43uf/t7GW8Dcg5wWxhGnjWC7PMUgwEzMeruqNa0zB76K0zeUaOmh69WT\nQE+NgpCq0rrPFoR4W/hxQ5lqPWMYVQs08oixXrdi4qxOlpMbrxoLJ9dbreMCg21g+h8idnl0Tl1L\ntZ5uVIyA0sfNcXr37h71rInz9wjZ2D+cn1MJf9A+S9uhwm3BGTz/4NlrrXLFirxI7VfKkYEQ5kS9\nUmJtizU6dQ6Ehg6JDdHxuh5l52FvU7VuMVMozDJdJMvbkeQHAh3I0RSRxjaUk9t20AqO38NUWado\ngkUnSoEZCLnKpWk0YPx/LgMwFeFUGPMwCcZ+o4LM/G/XVGe5eO/pecve0eHmEnfeVBoIeGUVNgM+\np5FXp1hflAYwWYzb3FqUrZM6TMi1jBAtwoA8RkCsrYN61H3rOO2e29xzDffAshtKB1dXBUfI0Zxp\nVN8o0s2S0sIOL0Z6Y2+38Wn6hSTm9pUH+2vQjPt5mmWo7cg22+s7MbGkZISOJNCM1mCrD3s08ZAJ\nwSe0IXxQ9GoXKl71fWfyxDOEN80E97kYHfLwT/anINNK4DYOqinZPKwL6lPcmfztT/jkkYeC47vc\n2LKundEqdpIO8cT/NlrAVtDH6t3Fm9VABN/HIsAxIiNvOpHUSrLSF1keYvjZzNPJ5FRQgPns+eTv\nGP8JvC15MCNYsPYO03i0V8tim0p2g1ZGaidN0DRZ+8QURKlhGPX747Npc+Sns6GK2hOpqQs5xmC/\nkg05svfxeKyBc+mnkDT3BuW6tl06gkPpjvfgTxknS3UtGnjHnLRzXmIjQMl2IQ0m0gzzccVzi/72\niZtemsxeuumi+UP3MrCWaN+wN9xfBDV49pifJbqDeSGoznX/Zcb2XT9kvtBFWMmlBG27ZlbXviyw\nPnR21Qdpe9Ga3f0oQjJGGlKrEtk8kpZXg8bTyYQAlP0cxQpKZU2EjD5JPPrHfj1jG8shz+Fu/9Ho\nMoczpTM2n3rQNUp7R8v0cHO6ikm9/A1cUv3WjysTiu7SuCs4gBkotSNY2Xk68SXZWzYgFxmK8HXy\ntx9sdKEH13yEbULEXA+4COwl/PywoPj/Nl+Ew4Pwcm3TnoqS0GSPt7HJPOo2hoOxxqB08tPM+X0t\nB9E3nmeN6WGtdPk5mkipZRl6B32i/Zgg+ya/eRdCQdf9fg9Wyl1aioGzWlZgA8sH0At8Y7gl7NYv\nGsBJKYY9eIu3oVdG89uBhlUj0AOPcTOGIyt2OwESMxURJPXjak9Yh0eSBLOasPf3rxt91kWGROIx\njBiT8eMt0OnS2yu5HO2Eg40cmIqsC2vwtJoj9wOdu3zeceXfhMsdMoEsk85U9XUNedzDXBDY+d/K\ni529zO4iKsBwTRgnL3+Qq6lgmFdlFvr4PT7x/PusFTxAe30moNx7vtlthoDXjY69raOtJEVg3oac\nlEa+QrsLiy6szONetja8Xwm35OWq22kBLLd/fhaSvhSgxFNpHlINTa+dJ4OHbZshSM479f3oy6Gw\n36CHvvAUHpTmQiWWOqNmmUHHHnMRxvyySNkV7J8hlPk547mUpXPDCAheNrbQCq7Zg9QcaiQWd9qJ\ngnrFkLP+BjGxkvJwrV+1jUS4ymZ8io4U0EOc64Tuk3B2OXy4e8bHbNs90VoNbogNJ2JBBrluJx1L\nQ4+/oI2p1bd9BrWyi9lb2v+KL4o85RzAFnSU5vGSjrIx3lm/ZH/QN8/90o4qJsXwnwzwywuIEieB\nDYWlvqUtcnk46xKGSj9rr/PSTZBd7gFkW0W3nLbd5MKKjVDxtdiKjSV30e6iwgDQZ5rKvLaEPVul\npiJd8wgHGnnZRT6oMODzea5SMDG1Mx/Uu8SQZWcFTOb11D7MmcZD74Dh6kGsUS+qfY/P6LK5ZyoN\nHNMkZtEiQINbI3DG2LexnjcnXgKqZm2ZXGavRz/1f3A+4d4Rw6KoWfXIZOVUdNn/l4FxU3xw44SI\noKl1tT8NUagrB/gafvUWFBenLnxPxW0TaqMp+/lnAdDvwHLTwf2p56K21HxTlxXAb2QmgQlZB6bU\nDuYRjWtw96PcNIcEhaffTdNRFC37g/+Rw8qIWX4+euwL7s7q0kxKR4/TG/OfLrnBR/5+jgJGxj+u\ndtyDwjwrtChjTru6KPXODLvAm97PhZ8NRtb2Yzn5a9LjbWYSBpxjf4eyfAdYjEw9yPbjJpi9AJAW\nmwhWv/9b5rkxkeCEr4yQ7tXZTLx9l9hQktow08Zlh6pE4/8M86ah/0BFrTA8TwV1MQM9W2oncjGH\n+9q2b04TNO3wbncrECEi4DtBvtfYup7Ewyn3GlaO5eYLTg2/jiNmLP8fy893XZvRFmwsQRwnyXCo\n2nYZv3H6iAokmm54kiA8wDeKeZH5bMVRb8coUhzn+OdVrFqyf8myg0lyTJzy+bzzY4Pah1/xh3/L\nbI1bdfdg2OoVS3n1aXMOJQSoBQzk8F4lkSgV14x0kEgcg+6I2cD6IG6bQHCLflY17NMmKnX7MQeQ\n9ARoZL9Ftb6h6jt+Yj9TqigvDbbli6iYyt/3iLvMaE7nKbkI+BcyGR8FeD5rz5Sukk8W6WTDkgsD\nYzu0DTmAkRvyAwCKiwy6bzCh4dzKWJOK4GMV+psXZepr0io43Re5pRIkbdTsNzCzimW21WR9ePZ8\noWGZGUVoCCHkoM+VhFyZgrFBCuEGtlTrL1OhJnn8G/vmj6GzP7ppzjqtQOJdd1NT3mIJtM2MU2jK\nSJ1bL9b1YgSVmGnENvIHBs2oDoiFeYB/AdsDKbam8Ofe08wTbM09FVlDEjl4Kvym/+mlqBqdjB8W\nBTlVuLz1Npwe2Rqin9pAfmf2mro+7Q+P1t2MkMMBq7+mNXk6t7f1EZ9CP//mfVK5vfUlm1bJwc7h\n7zjymmmA2J7MYyTiTZCFm7zKpr2m0yARdirGbh5+XEerjM0JG1JFcunC/BfW4EJW+aPNSQhpCcmS\ntpvSqc1TiSkWDACL+Kld4mtOaUOVAjJ4IPoOKrJtnDz5EYLStpqmXsohKLCt+sy9YZ7t7NEdk0SI\n+i8nrAQsijEAoguMLC2r4fcfepagdfAzf18AS3Z8t8vItfUFlgvlByAWPD0pAxEeL6gRPo34mHvp\nqtb02SaAbEWUaCCZNhoIT+MAPCCwxxu6OEN9VW7YQw/hmrD4e4GyB19xhrNtuyh4zHoN+FX72opr\nxOkXzzghtXGGsQ2q3/6cNaNiE7P1xigeetIkjYaEOogeiEI0BuF1fbJDaLfReX9e6jXiLvhJ5AQe\ngiPAl3g0FjDUcmDqjRteAhE/PNHfoJUSgu55pPfO0NY2t2Z2Ye8DF9v/uGaVuFA1bhi9O6ZJfE0V\ndCrNoO9JVtPWadZbKqRoRYR64EhOYf8QMWXpQea8J6pNasP5XG62E3mNJmZhsEhO8da14ofQAFnr\nuw1npXWWvVGW2OGong7N2Kwh7SRpeKL+2tVeUM5oyRkkegprU8oY6yDTmkgW4gzR3iUD9r2yEQQR\nEUrnBqjowX6/a2UbkSvengDsfeYrIn57XZhpweU0dH5uBYP5FkquBKbngRzDWRIhRjpZOeNBuquj\nX6fJiQEmJedr3pyKIPHyXEepzbIAgL5Wuhzk/LNljrsUkTz1/vK9wk75QbxTXjCCi0MlhBUnf0Rn\nT9gWptFSKOOspcWHZzz1bR3qAF6yX2iGIpC7CBqaPPjOSnOIr1Qhts3FByUz2W7IrG7VFIApG2Qr\nZEpY3450S8oEjLqImCdG2XYabHF3KyViSlBMveVAn1qZGku+UFjoqKXKLREhng3hLqooi6ugvH3F\nhLD0lteBKSVsoGT5MDZ10f0FHDYuDu8pt7Yx+avdWuF0XQUqscn1y0GeYS5kr86t+F4ToSMW3ovR\nH9BqBMW/e94nritukUh+pUU2ENfgPglvuqcA55FabulEONPo2iV/4CdTcW3iZD/sNsGF1UHqf12a\nGB0N+vCYNuUpx9LspYpJWTeHOQslPRs7vWN8S54MBEJuS2EKLe8/vgESL+G2BnW7yrnXdPGpYRi7\nantqD/KGvHSTv4C2mNcnINFPsx4e4JPlmwJwsIHL8ez4LDfzGkbQo3znuwcl1FgqMpr/rZfAbjGd\nJnMlIYAo47jNmAfLXWB+SdpPEJgdYuuRi2GQKLWkI8JUR+/CMdKDssgcEyaJyvWOzURvv1hQUUs8\nPkMdKt81i7zFYQjiItlszd2C8zczwlH0eWE2I/wYLwBYMkRn868QftUBc7WCXFXvjBndT65IzaLk\ntS+XJHy1Fk4Cnnkwhr5UiOJVKXMm45H5EKxjwXZ8si08tIgWT/TPY7OcTvYc4EdO5sqbIrOIlxcJ\nA9IOjMcJqGbEoWMAtk2ASak4RNiXlg1zb+mt4fLZDqvemjQOEytIdpDjsKXex4b1kwug4wZmGlki\n8NSMfJNHvGf+G1NZ/qm5S3ZV2kDMvsq1CbBFSw/PxZ+mi7bChotalY0y4uMUAOBSP9kunqJAUrMn\nS2uohKVUiU917LWN5sndUR/DPUfV8pwKaCkdxF5wwUhxZriym4suG9nSYCjgTo7RtHPM8zJ6jadr\nTOy4MQeh/41kZsJ/XYpc5ElRTokVajxpABDhLz+d8fs3DQLWhTQ7dAQFzaxKEHPQYD5+qYLkSURA\n9WeBKvZqJTRRibHc4nbOfxRMxaQc+EAAjELMdOKS89L0XejFvCUujsz2fzQBJkpDyfKoXWLRko92\npzHpWTlhRDA9s5b8PX/AR77wA5ArUGNjqLmVzA1pp9zbxZdgpjqCLi9BNmyv/dg2HOuQs4tgw0Wa\nhIkwx7jfZ3N+FEnXqMihEhWujWBIpFVWJJg9UJ8Cj597k6j613fhjn+fQC3KCwnC2yGWi5ohm/8M\nSpdCBPF0n3F7iEKeRYOe9LRZGXKsa7cPF1dK3NOLqS9L8s/I5RGmzzYpuJX9J3AdnFkFX+eNJqg0\nKMrTPSxtaHUEe+by0YZm0zlcR9t+oiatQXde6yVVzmFWgcmsoz/fDx/AOOCTGxthX7cLvkDnRut2\nzdGY+x0SPOUVq9Up20+HVCHHJVdvlDHnRcwiopLP9EVVJJ3+8+zXcRwdR/W0qU3e3tjHMQeLcQKh\nJEXrK+Byiw8OmW0QMfzy1sWD0q0/sbMxlvt4eq0rHv2LvmpDayo5mQXKasNBMKdsSCFzmjkeVXkL\nx6lrIBNQrnRK3F9WHeo1St/Vlx7gKX61STdUZx3s6I2o9Fu5kQ/n87oY5kGnfIYy/Sqe7poccG8s\nnwtvT0W1l8YAgjLp+y4ttwVZN1u2Tib7vNpCGWTeUR4N4HZlfTWLkfxHA9E6qHgLyLhFdQxD5MjF\nzFCW5kFcsPysIWupF6wd+bHTvxMd9+e6km+LqJvwX9TJm0/Tuhv5smOEetrL85LZL4hoOD3gkOD9\nux8mkIV156Zn5qAXgRhGCBzTAoc3gdEEAZuM9CMnvGFt7nYQqUWozJbVNIu84YUuW9UaohW0MdBq\n9OmTNAp1jaYXjqH+ZcW4yCPJEkJKLw97SJqnlj0ts5ypvSx0AsRbwVqIUkBHIRTEuqdwXy7ffZPz\nSuwzY87QGmpoKvLB/NF/8a/XOC/8ekWrTlyNU7kOVZdUUan4xgg+rmtb5dxRQOg2+Cg5yB2KYpFZ\nGLIJEaN5ePx6OuNsKyGAnoL8VB4CVbYL2YhLksaWv9aVH0MSEQBH+d+Hhh/hyb08on14QDQ3IPn5\nPOfH37BX1Kt4ZT9FhH9AqYK9+IYyvlY1QZqMYqku6WF19aB5M1k1mnxoD9qP2OCDsvW0PulTcPwe\nbZWzXBB+yCTURvqwPmCCGg7Botgo7UemIA/YDo6uZQhRsrlLBqrNEpQRRJvwcCZadPmql+bxVLoB\nHRd0slNjme8ocHNUYblDKhFKIO4zGW4vkVS2xu86jFCJP+AUtWtEoBbRuFb6se1EPWSEZccg/tdG\n3S+yZwJXmSQIKiocBNNsoQl0ZuYObaHJFh/ghdUlIm9QpTkoUQwAdD6P2fVXHsUxXitYILj9Eao4\nnl7koAUxv+egJe38T+XzWu3qJvZlze2xvOmAAXEjVQQfE0DmYJfZVFKcDVdg5jYqF8G8FxSmQcxC\ntIn4gkrqg6EV87gisbn7qspi0sacZ6Q/1gQAURtDxooDDK5gsV0NEhI7EyoinLXjZJ9SY84+Bzcw\n+VD19FvREqBGtziYVyJ2+YAO9kUgWbuDuEy3aFnNOeTv9ze33bOAoAhBDtbJ4BJZt+eGcbWYWlP0\npMcWI4mKtcX18daNTCZR+LgCAw6J/bR3KiArm9ML52M7oEzMMSX7skvxyTaIj1zojGgXeZXvki/H\ntGHQauTSObrzhFf+YE5t50078XpPzdQQVhn63OgOKp+6Rie0Q2OZJJP1G9PXiAViKajwJ0U6IoUK\nVG0LJhSYwAOF+ditODWEnyYQJx6u4HFg1/OYPbRRf5SL0HEyB2SOhxzRc+QylENCwbGWxkJ/MjpF\nucxP9yehbXSUmmAXr6u8e0PlT+0MEcL5+hML6XanaR4sMnepTVUB5OQKCOhz5bVdYkfJf/AZhI5u\n1tj4AjxaqRwn5RhHqqcjspa9oAXyD6fTTd6VkJtf79obE2Vn0/CkZx5Gc/vEV6Y/UUsQa0+HNWxC\n0KxJ/LqbD+0Xo9hk30nIOWumBfNHVFNABhSH0FO6hXe1h7DRvhESnhSo7kGWpv0N7/A4SIRMybQt\nC3MeWIdBm09lya/sOlRRHwnjh6BgZeBEtPqYX++mSFDadrZ5912qAYsGsdIFlk7+p6xospuH+IyQ\n1PP4r9wg6I1iF+wSIukIJgfswFgAGBtqgDHhfMaea99tCTbBODCxTlvVOkbfZwEcdfqDQJioj+nY\nkY//DSMVhLeq/3yvLCdiembO06ynPh1byTgwmALsU/RT7uf5DrZBontbQhHqEaFGqtf8irH9r7Cg\nJC23F1/SWnAd16dLnUjiqbXwbIoLMHbD3pnqvbyyqy7FNroWPX4qTHJMm5LbSMWNMGR/l4ucWMxV\nky/QnNMEU4wvxoK1RI+mCtU7cdIjq7I9Jx8vXkCdnLnAXFb9QNHosk8LwZfmibS/xe8bBW7lTtzc\ndbpZwB90QL9ATHHTbwX997qQwU6f8Q6ZjTVx8VzS23VGBt3KmFvGycKB6dmPyzvkFWiQW+Cs8bpN\nvwr1sTQF8HierHVZSIDcGGnQ2RcE9sHY9ywA2gug29YJOrasaChUvfzGHMkvgAeWBLoNN45Ptoq1\nHNYIOiNBDDt8b2NxtHOlftvoV+KQTNTItY8HuSuvucGLRFZ/ijxZMp7Gka8hw0omBjJ3K/Canqk0\np/nI+kfZ/ww8PnWSkJCV3iTei8yb9akSyGPtimN3DRXg+nm9F1vhe6ZjwvfxYdXsR9RM2YFddDJj\nPJ/7sbG2ySqr5AI3utiP/mJsP9zsIUtciEXpzIiY17AGEzEf9WZc01mBXJheccBxjLpk2hOmp7DW\n/bolFGQo1u0HwOCjvUQEN/VnOXBf9dUC8dHNpljvbvcpY97VkVLl1hhLXJ1B6CZ5pcmV49ukA2yP\nHUvkv0kKuJDG2kjj4LUJ5YXaAGBdch2MCw/ET+X9R1Lbz7Tm0oYfP/vj2oQjxfHEux6lD/Urc2oI\n1tAqwKd6r/F2M/RmthYfXTEpVDUbiw91v8Sh4I0wwtXOQr1qrn4qwtP90lOT+tlF2M8TKR+rerOz\n/5Xgv0CCYjY7xCg4tuF//w6fpvgs0Xp8n+/+RRHW9SZuYLcjNkECku4X/bNTWgMoAfJIJLIPFZEg\nKFFHSa7PwlQqsQtO7f3M30QtV+S6oPKAnAqXuAd8gNhhlzMJ4O71NOrGSrsYdqyKFMu1pulAegSk\nQZ+uiKAj5kh/P0Ce6xKJQVPByIdBLuUdKWrNSvLdkjayB5YrzBXr2uR8Z3qtXmVTRrfhblbKcmVx\nbSlQCkpVPIWCxkOIc1vH7QfvkHgkz0Vh1O4Br6JIiEDbSD3WhYk8pT3YrbNfBhL9XWekVTilmC+E\ncoRGgWwOOnLGcaI7bxVfNZzqrCajMQSnYQUipkO9bAkBHiMkdegZfmnOCpQgUhIRZAmdKCA5IYZs\nhcQolXWCTRNRgfH7AkKeeObiP8KDY1vJ1LZx2YPiRrfGHoQeAVKnpo5Q+XF4nsb5FDWlbSF9WK4x\n3r2tGTKoamdzjbn2uks7TO7uFcTC1hsh2iFiECPnECYbt25QcuA6GhkCaQDMVCRlC72dzdy8cM0X\nNLgdEMCfAuh/pfO5Soab4eZFkdYi0lUKw2JYfFUm0MsvAYUhYEY0Hv6jh5aRNCEz+5cuDw7ufd7P\nmvD82HTyuLstpgQVz9MqL2IrFX7zOwsr4Iki/sE9jhAIqK6UNb2lrwHuhRS6OETJDguQycwqveDU\ni5P15/S9l0xzS0bAffASHIiHDS/nna1mXJMzNA92v5SHt6iND+4NgaspRFj5McYl13C+pzciz3D4\nX0zSkKlDQTpJZAjzqyduOgXcU5sROz6raPi+V12shPmKE5aTU+nt5baf0/qBBo47q2UjQMY75tMF\nRVal05IPRf/HOpHBowN7F02gfVE7H44F4ERDK/Hq1xEtrOFK7H2U3ec851+lya2zTCJR/Xcf3VBe\nlxb4RN1NWaePQkEcv/YWnNpQx+wtJntRzhd2+4ZsxawcWl10ffFyNr4ZHupqLvX7v4I/hqx48thY\niV2fchI4tKi54R4OpsCf7NZMQeEvUspEGjrcQxpHVgtMx1vXC3/lApBlX1jOD1aTwr7ThB9FbEPp\nc37PFCi99PpLZuExy4twaIUSOK+4IOfnhrNzP4+bb4TObcMe1gbmAED5+fDlwoMUWWRMMzWsyN/A\n1xIrOrM7zcDWgLZLcIOfS0spfbW4l41PKSCbIcNrB3jFSBrcwm0pQbneAUYkURTiw0Js/NskmPQ1\nqg+UnXhDdicyH0Wfn4tVGjaPXG+qMWBP4Fx3Z4tA7m0jIrR68Ao8aX+cbhBeS0kMS/j246amm0/s\nCXDiO60Fcdr+vOQpO10O+LjBwZ5qsiJnpnjeaJqXT+Et9/jkV5Fjp1xJ3EnlachHDM//79eNvK8/\n/JKOSm4wMLqBigZLP0jzbtnwgaUT77pjjr7T1mI5GQzeY3nuBOxgyscRlg6qA+96hZ+yXXtVArTR\nnf8MO1ycpLPgEkAEsRETTvNnDrfQAd3EFl4I5oisHtpNwuZC9DBflnl5hDZaZW8INJHxcaYffeOA\nI4SZqRyHEDisnaRsUSDIwcwj+tUhOyJyOMFqPYPu3W8unFFJc5VDswkGf2v1azZ9sqH/+QC2r1+q\nvmU/p4fmXXsNumWv6mJCHSInANf3xj65XGYYVUADHApABy4FLykn1IX80gOG/DkB8tArpTRIvOnL\nymsyFKe7bYMu0tUnlo2TPt/h8MeCWZiDdodmrMWa35AxrWLyT0U3n0ZtHC6/Vdt/e3T6oziJ/eVg\nlSZVzkrl/F5IvDwa6bvb6U0s/exSaMcTOHYms2e8B986/g+KZ9CjNQx8CSaf/8NGvuVEXtnONlx3\nLAWQZyLkf9AlRhWJk8otSYNkhQ30sHgRnkTwxaL/hxEClk6MEI+Z5UJt9ycXKODHuULHepLOcPZ6\n14Qufb3ZpVjOTbYmikm1m0IX3bCoKrUhj9oXXboV9woaTYxH8fx08ABGoDz1wA4F8VMn3QUY+F4A\nsb8WtvEmh+XEuRlB1edUNrN8WEkKjj3TwLKejJhrheVTvDZR3LGzRN5p/Fiz3f35bZUALgirF+Xu\npJhpoFYB7CAMH8og/F+Jlma38Ms96J/JN2SLV6bxpjWe5s/aAFb/m5T2WMr6f/Fi+hR3bYw2ANUU\nuDrYb3BZizZl8oAm3Y8N/HtMXtiLLPo1FuXhV/I/dqimr5RkGNYv2vmFyIRzlTWvf1OoQdCpp/8e\njsVRC2nOL5aja1Gbrsb6xLI7v7zOy3OXXnL3A+5G/aRzJIi6OYRIU9iBmF4cPrBOeljwsiThjyIo\nKFFxbCwY3TLsY5DzxbRnwXg5/kBxZOaES7X3X+zHI5eyla9CnQbfH3EUEvY3EV/37+8QTasY1tOI\ny905e4+8SABe51gkubKLjrhy29UKH7O2fYpuytamltn64Cdq4NhqTcnJzHCqZsFlQR2d3NCt85uw\nAMhm34FtpsIt7/67XzcvPhzNtotKCiLKN/Cgm6WqDNXxXQdqWBpk2t0ruAhp3IlUhukD3Wg+LyXf\n/ZO143HqZM09ejrB30WW0BvJbccuf5qb0GgBxnj7M/eDXJJPxea5jNDgIz5AJ0m2xwLDSCHWb2Wv\n2gTrQlIYnhFqNF51eS9oTQcHL1NUd8J5WhoKC/tnFnYhqZPSXTiC1F8H3rMUITUwIwR4Eq5f/SMy\n9vvjUuHFbAre0sYO884yH76/735dC/HbyF81vbM7uEaXpOBXKXUyFJwP5E5GfEcWXmllf5c8aS/0\nX1aavdNjFTbB38PKSNPR7vE4GYr8QZDsjsYzycp5vB/F1X1R55r1oHlKyB4lyggTZMjolN7L0+/K\nh0SaDpL1hBSp0datucCgpkHAK1ECDvvnZz/EYs4aUJdU/3zroy9RYIfB24/4jNs5h5aCBTMkmeiR\nAMIDLVnyEReJ7oVzZ6u1b6EZKmUGyoE/NAWcRmSPjTUJgrzF4ERtajmDO5hzZdyTOkti/h4tFdJl\nsaYMNAKg0w+186Fz7c25LLBkit7BG/wjrAPz2cW6JI3S4ru5pGGi85VQsoeLOW80nnosEnFDip+V\nJ7aDxGq9BSwM50DlrWdIxbvLObiVnLR8Ar9HAyYTzspjd0FPpeLqQVnWy9kn6nIT5CqukkpCwcLo\nSlct2bLxTcQhrwQucx5/LHBYpKkrp7rrzkHZ6P+cTUcLHJNyJPZkZK3heV/f0OcEsM4EKLZpD0g1\nJv8wATCKBeecm7/VqyQllTUUWvP69Owt0G4XzttdIBz8DTPtaI6ts0hlmbOkcDTTvBf5mZ3rNmnw\nlg1mysjyO/US6Fuiq9t9+3Xofstc4bHEm4YBjGCH1IHTDzvQccKfnM/cqleRvo7H5eXiFsZtPp1G\n6GOcsXHa95RzZj79MoKZNjnpEY+t8YauJ+ETl9KG2HPb5yLpP6Q6cV2HTp5GNHhvtcCoWQBAiqHO\nbxr7/HrkWj51SqQJe0KV/R6u46GvpDHfkVkDlouZTZy9uiFGVIo58fKeM3Te6Crcktg/2o5vSjkO\na7Z8yu/uzD4/L9K5yC9W0SCtqS8uulGQZpEHMWNlzCWY+pOvRSTSp73IL0EUO6DI/7fF2UjEWTyP\nl7qk/O9HvnOrrWAV5MLHT2Axk1W7H5akhnhcPAA7Lx/Q/Q5iLoPNHVWxjlvlwLlwWq9OaQICR4jq\nGDNMi14HM8VyANmSUU50AAoSn5ABDzSXJ9eUaJT/oU+O6OyAckpg07u/yYW4BkTMw8xIioyNOSqn\nvyJ7cBAB7X6KOj/KjRLLt2J94Qj6UBECe8x1PJ+/oKc1U5SNGmaDsiJPYE42OuvkHxD9CXzez4zx\nMiigISEAWNHfQrcy73vctjtz9y0ieOjN163Or2pLp5RE+4EnBTO68tZ7DiFsYAvgyApEJfTwTzS/\nH+NfjaRftQPoB23DSbd4otwB9wqCTcgyKeHfwrA2tWNoBnRRDh43MiB/X3InWXASYwMqfd2bTAXB\nO2ZNmuvDjFCqHdc6XOPqtha0OlB3JmvtCjQqmRjfwBDEg9nRrUo5OrhjinJ1ZZwsA6X9Oc2M1jUP\nlgQgjlV0P/hsZqt/GDjLt30k3e6DvQg5Ye+Kvn8MkqXne8Omnj4K3lzvEKXPYgWrAr6+t3IuGKRO\nr/774W4XqSnQXDXYSsPlm5VAGXmAqncVo5ekdQw9di1hmya76/G8VcN4QK0J/Q5c7xhsRvZUhBbD\naoZnX74rF3GIzaxID8PujDrYDMP2QkRZijphPCywc/l0jsldhR2NB4RW/kYPN3uUqK75cVesEaL5\n5v/AR9/c4p8tdoJRCWfRRBN5m9RRDQl3XFMUCUPifDExugkQfos7EIKRGrXely/Hf1bqQd84KBHw\nQgmROHDt2QlItAPE/wtivVzftCklyirO4+OmfkftzxGbX1/QGxAlJyR0gmm6RvKa1YoKUrKgK5S7\nXscl6MYwHWn1FJriTwerIP4mWdDdbOdCyCWKVqrv72q1sgu9Oofps4WpH4Id8HnAUAeoyYdHVdyf\nJnSE8viWhzvF+yf1tjrLZZySiZWT+ad44uIZkAqC4GRPwpOiYMPcB2Wa+1jl9Sjtp6expmx+u/5h\nAqCBE5nVYwwbNJ5/97wkl/T0DZm9KVtrlWoLxqYBUhTAfQ/Vdd5kx3Es/xK0tvL1c62UXivN7/I9\nVqga2Z9NvKTT8owc+ZOI0CANprFE4IK8JbXKrTc2NMiULmEnCU8OGYBYIMnkxGLerH12+A3ChuLx\nHIhcg1avfqvOounj2H362C2fJYDtmMVv5i0y8x0+v2FBjrTzdrisolTypKmUZ2MHXga5ZGY7mXqn\ndgkFBZOS64qYD1nIn48V5Vlsi7LF5aLMCOZWlXOw8WmIF6glbehcEFsPSnmyeQWeFK9duIjIEiYC\n2S0COsdbabYyYPGGFpz+iI9h675DoLj4BC552U1qA3tp95Z5GrD+9NcJQeNA3QjGp8mHde/skpX4\nYkex6WxEDA5ppcdy4YJO/pIrDUz4Y+KJm2AHQ8G/1UYNLy3QQm2xvEdP165sZy/GgTk/MxGtmTrE\nUumAVGVSTzDM3pMWOXMbHsDiCoY+LxKBmOofdTajcbPQor9UnJOOh3bk79plZvZkj/kjgc1ipavu\njT6UFxbm9ghBi9L6eUME4BbN+EiorSLlyWruDKS6fq83mX+4iaCshfP6nQnuTU1728nJ1U7J8h9l\nq+nruftauizB/m2VnGlEUGvC5d/olcqk6pWiMeuemTJM5+/BeAZ82XblX62hnpwo2kJhh0byu56B\npAUGKnLdamBw437+UlRRmPWEp2UG5OrqjLR0JMf02lGeO+AXXllC0ji5T+qUuITeYpHEadr7rg4V\n4vCNuTSmTymv06ja7bmoQR69HQxh8GWBKzTOLLC0knyElBbtUMaLTK8ocsuJxklx/fiJ6dcTfyay\n17QKT9aSN/+h/kzJsmdd/rSI6eJuQzg5lq1pM9nNggWdnDkZteF0Zg9YFqHbGfJMRqZuHxiWWHYf\nhs6BYwa1Si9yITAbky6OYkMYRRXLKB11R+pmRoUoiwr0xLh07t5UF7xEWYTqv+9KueNxtSOeV/+f\nEdo7uzq0Dii7Z8WTX2z7Aga6oO50BUYS7Zu9EQqXr8lj66On35fDlpEVb6h0feMPSn8Z7CCYxZxv\nrrgpc+B2PXhRlSumar1I9au3GrGSzbXaP9tYa1pWTWneUxksfdk/VkDLBuWlUN3jc5hvC0URlDsn\nV9FN14sxPOVWYbJt04oVou/R5XA4BNMUei+KMqaZ9LsMWy3qKESHAs0vomXA0Q1xxXac/zDN7LsB\nRTS+2gszGrNQQd961iFcXZUTQQaittUszpL3Z1wklSTLGQ3Do9eYkpQ4MXTmKjEcUcTkDd/8NA7M\nahK/cQ2y1mYEyJRkYFICvafpDj2h3+Vrzbg9cJ/+E1y9pNY2lS19jiEtaCisx04TRLUodD8TP7UQ\n4/ijc61VHaWa3tTgXuk6D9hD0oCiJOSUItz8iavDq1u7eDRCMKfEuHf2v8Ddhmkd04t2N/NQRTRb\nIoNNHHHBrQ/dszA1gWrgEV1xZ0dKWps4R/gk47Ow72agtIRoPMhVUyWaBgxaaEF9NAB/0Knc79/h\npDrIRM3UDEfbvOJJfBhGpmEXa5waa5PjxFrms+lsyTs58QeBBGPyfXH1r00fkBCCrhrlsM1QQTrU\n048xf/oyN0tUcjE/B1ZIBe410V5kNJfAtxAh2VPfvVbgbecLqGm3bRUljE8ozf1n6ARxD6GASLmc\n3GOh/dMJqp5oJn2sOFwv+B+AYOeGsnY8Qc0sa1DnEwTVUhDCZ2M775dMR3zZGEM/kk1pALwGQ6Im\nCnigap8WJ3+AQ+x5TZJsjWnnsZFbKiAITDP4+5gG9BpBQwVL7bSQYfWAYV+HsZNkpN9DYVKoz2u/\nbNnXohT5+gKpBQYKTg+h6XWaT/lwjspKXQkftnXwIgZC2EoA3j1BVjXTu6ePnVHr0azUwa7rhzUe\nSNoCfmOWeqnZSvRbVB+fRNZRI4hAVPpgptKPpCgL7DekF+8a8+X+Rca6jH9KFM6Vat3qvo4j81hW\nxg4glHb86eHWcUlzAW4wQR/D6gOuwjzvEi1jMpNNzZda2vtnd6b2QWQHKGtf2V3gPQNE7qp0z6tn\n8zMGcmW/WdC4n3Sc9GSGmsVAzNkoJmkCpBSMUwSbM1Tu1dX8eqXtI53zosOPO/buxyAkhN9sXDC/\nt5lVZdFQB3QqqT4xDjY+CwXxguwKeogUHQlcmu2PyndG1/ZlougRvZrmb/Lkw6bwLFHnuYLBZbov\nvAFBpbSKNKvQkZfTSwYiDNvc8BMFjMmjcFamwmizpssKFLlKIIbAUGDo7/9giFPRr+jOsQsmEYM4\nvL/nKadZokw3N0FCPbZNG7oP3I1wFyii7Klje6QNyIu/MqYQmb/XY51Tt3uPm7Xfc3/tNrmlri9s\nqzbMC9eeiwC2HkXHim2p0c4EKVWinPJkmzzHhHD5XqOMojAJPhX+ZblrNiwdx7yZ9FDd+udt11t5\nKBAtGk+DkDqFAWmcK77O05i4wt2nbfCYpoKyN224bqN/dwJBUcvQDeGU7zCkK9cY/M1RyGyOrSBv\nuZdwpqjj52VMyhC4eSw0VKnH/dkjXE6ob2Bu4okt1VlwfosxgTLiKv30Nxqa6xsSgUBdLW76YgRM\nSSxCp+DlI4KsYaCpTLqAkTsNbWs/XXcz+KkpZwGT3Ak7gUk9gWYDThPEGhAMifMZoNiuB/frOteo\nErLJDy9+/CBi+mwbqwhlM1mSLtEL+QjKXQtFXnAoKwlV0A0S3Y1F3eZVIt6N7EGpp+GqKm6pbvJi\n19Uv96Xgojy6KuRIp/r7ylJhgsaZmktjQVHgyTwbhlwc443FUjShzjYUNu1v/lv/ma3v07n/Nu1v\n5Ygxneefjd/BazNEjUTdLMV+xI/8Z5v2ZgRVVM/EjyzoDUtDR+/Fc3MUuqiQt7vYIQ3vJshwAQ7H\nq6dkx314RtY4hRvZUCGU+rnX/qCmenpVXFV2xn6Cc/5OF4EXbr6RN/qhCuiD81yAQd/NbjNEOtMW\nVmqXqTPsOOPY+FHam5EW4IxjWPRsAIX3P6My6Rer1kJd1F5zhDJbArwUbEm54c9GQkVXxhTWYIqF\nvH+Qp0Yy9tyMUnRlASj5jMvgwe3cUuHPxlyPUuZK+rK5ayJVxweBf8s8NsE58TFti+6DGNH+GMoj\niJrcHMl7JIRez9U7WoBdNSTa6Wu4FsIQskSZAPRnqG1YIhSSsLnEaonRZ5jHn6PxFIsGHWLkRRTM\nPYYKNKVMipW3WnaHIgiN57KTb5pXBGnXQxTZWgNJ4Oc1Hb/CLPxx+jpJFEHcrEa1chVQZd0SORaJ\nC0zRLJ3K6naY4bpkuEtRGvqnEiC69i7rkR5IYJVZn4T0L/IaF+HxfL2jZBzUqPiEpBIkGRIoRoal\nnAnVsez+Tf1g3sKGGb8Jc7Bvv9mbKP5r+ciY4SkeEHFCjRtXAHTU2sIxj+cVDrOGcwgj04QZg1CG\nf9j+AucjM1EmfmYfM6GMwlJ+jju7bvRNsowv0BBNlF7J8l98+ikv4vmUYM4WSkRV/jc+XOLWD2y5\nyNpM1OjVk1/KAG/In+VQAh+vgz1+4/xoyotLH/qRGT+bFxn9tomW0+Yzn/gahFC7LGrb3bI0eQTp\nQSejapmUj3nSlxVQ7dpQNZ0NrLwA+G/GycUyauRzRBxKtZMNHDmjfuBZX7Tcy7YiatzCZ6M2eST9\n05E4HperTb/cfGMm16ME0VdyxSZXAmb+OckEFGyGvWLoIVi1AdQUkJAh5rbT1QIkSS95m6iNjS13\ntFc+QIFe0S9X0DKXeRy730ZfGzxDHl3mt004W60VSMKldSaBLcHxxkrXUno6fZskEcRQEFd8weJj\neZkjtL6rtwkKjYV6x+cAqIRIH2CIcwgvi1MM+SbuB7Ej2OHbWGsH+ae6kDWlG5RxNhyL9DD4xcf0\nDdxElbdQ8rphwwoJvoNEe02bsY8iwtjuSyD6Y6clNaL27fwyCzjLujIWDUy4CHvK7Vl7a2PLD+dw\ny3uIbO9kn1IMMIKHSlomNpPap52CEIksHGtfk+4XSYfSkQKKp/kNqVVR1RPQGFToDqSveiV0bWAu\nSEee8c2awA4VDSIte3mzaYqUYDEfpBfjlJ1kfUOttH4qAi0IgL4BL+9FkiKjuwGeHVs7r+v2X30a\ngWOPSwAX10NabuD1IZjK3kIAgJJXnmco2ziHkW63XC2rKj3imToI3yyPwL11wtrAgJETZGrJTxO+\nMfLO+/2U61Knhu2slj+hYdaJqoIn0DCviHnI7DIQ2fAgjjaBl5/Er7USC8yzu0STnipb7cjZiTZP\naakr4i4vGo4b9Bd1itUaJzJtsdWrkVcFA2gSmBCHTYdro1jelehFneB/aDR7mxtnjz4PoHdES47A\nOuvVgKpCzNoMR43wGwKzG0B32o2W4cyo5fewsH6eHMn+T4EedcuHmgurYiN62uO0nz+M7aIaaBjS\nbPAJW3sIHIEEdl1P1Qtj5bpN+FoHJO1S7NGnxpS9OU7QMPd0thdPovlaO1Whwj23a2G2ry9SoW1z\nY5olooVHpgXYzMH7/aKVZy7EIaC6Pq6ILrl+N6Ql3+UuOAhOVuIGmgA3U234T48fYm736NjR5Gul\nrSbC9/WbAzLVLiCWKyxHmQqbSEsaOrjhz+ddTL3rcvzVLwFzhjTqRWQsPbtItebs41tdPf8MvInt\nkHYDIMP1RHhTu/5dAS9h/X3tQYAQgRhCHOAE/4uMtfdvIjgAe8fs2gC8QK99+EappIfJfUkvZKML\nn7JtFbyd4wN7CU5dpNIk8/RsvM3z2u7jtDa1yIZZIHNQfTaJ8WmsrUrjGpbjbT5lPZoMiQt/jblL\nk5uJo5y4kpVNE9Mg+OlMSMqekZyUeFSHuGOBn2smMqko+UVNaCFxXInWjz4TYpqXp288S605F7cL\nLmqsI1yHvV6yXa/8DztLhmbusW0vtxUKU3I2h/KupFTrxLHKOWOrxyix7kJ4L/g8/PutXuU1kAoI\nAu9OkaBF9G4qAHp30Eb2fxolsyRqSg7tDREIfyA6rPwj7+gY9z+2g65bC2+O5XyzC979ETBl5EmI\nPjuXiDRlRRDNtKsOLoz98L/9GAnV0AudrPU+sgVjxwcNfKaRqib2icBzWMIIsL3QLhhQxLI6bZwp\neya26npYMw+VI6+huptBzOaBV//Yonn62HLD3MBmDEsZRbSRiedUiuv7FO2kTlQi66FK9h02Uf30\nzrbGSKr4sRI666hzuzBE11QBkJqOosb4dDlHX01MQSKIc2w5pKvfi1MECCATgZMZ7ilhizyPHPhM\nqYR6erClv/4mrKlfdy/eRyaWBenWkK0J9aQB62+fNvXWRJ3F5SQA4xtCLxOlSKoqQVV+311DUvax\nEm5l0r5y8XMpy8Ig9W/TOidKG2ruNkmtRHwn7fomGNnG+YRWvlHPYkKcrMXXVZYEHhVwrwv0FRdw\nqqilhFaMowQStCU6A/Mch+SK8shJHK11OJnt4E6n7GSS0VWWIoddIm5+RK6+DVbhGIGMWvq2c+/r\nUMAozYzqqMD/iC/ZUuMEFaGnsRaf7fDLta1A7VFGGX1JrfJ84/D89+TUzIoiJt2a+mlOv47F/nIt\nDAgtzOSYGKb1NhXlkc5js+oaoygWm3Nl2B3F52XQd7P+eJfDpWK2TjB4F1BX9GMnOlI5S3kWAp+y\n8m67tK5JQgHqpN0CZ6yLbololzSu4PX3gW8kafdkgnx/s11MMaGgmdlGj2EpOY3RmzfYb0zUcv6x\nrDj6PCQU7tjBx85GxXzUZpzyoW0vswvtkLufpFueFe13Lj/xkjdwrV9ztjg3RmEWpqEDhb/ewj9w\nMDgzH1m5Waee3zV6RsdM8OywzwGB7r3QEi4+TJUT7n93NRH2bl++VBegv12aakTzLHKbSb6HyWdE\nUctb0DJhxi6aBKuzwBDJ8IXilBnK5vb0oGMpyvR0+SIG/WehKC+lUhfpwyKzZ/x+BMz/AakXAFHB\ngprixyoHCJS+IyJRNTufZoRpXGD/NdpZEyuZEAOBoY4iuamF/oaWgXBZgaa0NGa7axmq8VyYXhhS\nXRaEXo0XFlyt34x/Hs3t5P2AwUqFOhBalvgxSFuIdt8s1SfXHA48jwEBSY2mRa/LrKm9DL7CVsfd\nW7AcoaS+xAkMd1ZA7zGD1+xV5kFBSJ+oUm+BHq35pBGjxdwPM4IYx5qL8t5y6LkBzYVXQeXrYz3n\nAPikEn834V2RN3BXwNBi++a9RQG/9kyZFKAgjy/EIEDqsZ2Fz1a5AD+kRnZMq4Gy8FqfvtzaDX51\n/24gW4s+KdESku5GMoJiIdxYoPSC5yYdU6maW2zfvhU7j/VxHIVkEAuL1jggslz7UvWmLvDQSvyg\nAOiGhRngYu4hcVry1NbfF4Y9YOxx5VSFvbZcdVav2L76PYXQvfZa6b5zAj8nMtYby/auDzpCGggX\nIFig1IHnalQgAmlg++abElpqAE9+F7wlpvxSuMr9qjsXMJFa1NLhTAuYn6KSATMLJtmc5ZgFjtV/\nqZI83QMNaqgB/sFXO/zdaW6lc3DKYv0khan0DLyxC9ZYoU56KxHnwcsy316h2kq+KlFI9JUD4R5K\nk+NKgW87SF7e2IsYnl9F4WoeUQ9uu1TrYwvbBQikWhMo5zGJ+jDNnZE0hXYvD7zLnrpjNxk8u1jB\nVI3+wFkgF3y9dft9r//mAputCiFpTIwLsQE06NCVgTlG73PCHAGOQBkEBW1i6c/u8at890aDr9FL\nJulPXrkRHnyQlGS6bml0RA8vNJpoVwFRl2QRt2qUo3qTbXDEV9aj3xXdfeEseUR6MQCshhixhNj0\nKU4YYyNjpsnXLYyHerXk3ioDeukDGLEyA51ZK07Szu2UDcIFqZ+ab2ZHiovr68NcLfw6YE1qkg9c\nYLT5Dk89XCyGIdn3pgnES+Sd0tcg+T5Pp7nx1EigHx3ZihMi8Oxe/D6guDWy5TSL1G0ZaC8BvFYa\nh1C5Pfr43DjEoojJFMUyz4w/w5lCEUBEh6E8gXjAMVjzFAsA7vDjdWz08GsKz+CFWPXVVrVAaIRy\n19k1gGQ1MRtI7CUf1wWh7f416K2hwjHgzz6cmETCt7TexIThgarGxn+VSXO5pr5O1/Fs179fijJE\nLmwfZInZ5GW/PJnyfU80Z3xD7Jf8tA9KEhVmkiNE+SX7QVCho8sBVQhT5B26NKZrKHXkuFWKcBsM\nBhB6mZkvndJIuBm6ALke5fJITcrvcci6rA987B6eGw2NVJK11fP8ugBJBkmiSCxH3U6uXThxgqMz\nPujL2p61OUB/0gPUXs/sr7qt6X9/kYDGwejPI9ievkME+XteHvCyDtPlq/mjoWYawo1wDIP2NnLV\n+0QatxMMZBMlG6naoEf4pifcaMe3CAyIAlbYCkFgKoMf0qVgdHd05KcNusDkLqz+bNqx0PyHucx6\ntQNR+G/WKS4eXcAdwTudTPLXuqY4T5dXr3EU/fhG2oKFgHJRrAIllJQn5it+B1ljBrm8BMXVZC50\nkm/y/Dv2k1RZg83xH6UoGk0OEw29nx+XrBNqjLBViBHSdzLAg7XUs4irDXyfhxGycqBdvG0a98Nk\nxNU46vJazVxZWSL6U6mAe6Sv3Sr9jGmNIgA/VdbNk/SIP/AhthEjNhk/19pheo85ryTp4KL24Vhw\nrSotkbHebmTArYBspDLozvV51DeBkxnLdq1AwEdI+kiwzBbiud1p9rJEfRCLlqRYOI2rNY48L9Lz\nVwjSLp1+SKY7ERb2h+5bygkAImLrivJNuv0yj8p03GAPfu6DwfwlYjr/ZSn5C713pe6Imf5odEyk\n2g27gNss5gKol+0fnIRlZrAdBphbK+HDGns5LVFnXt6nhEEzzrhmhY5q8YS8OBSR09NzveOjphSo\nMFsa7DV6Mx6FidSa3xeL8Kiq98kSg/JzKmT917YSdmFImgN839ZxMPonkiRYfizHC0bcdFfVJC9P\ney50x1ZvNhADKvxaQoVppfhgjgY4RAL3yo8CNeL+8diNOvxxv7VXL6VmkVHb0OPSK9T7jM0UNC7g\nx2kdywCP5JyEAE1ZYgyfhp0cZseW8D3oJ03+f6aWUefyoDW+U7lhbahfjP9EC67VrkOC0aA2r1qb\n0EGdy+Wgbo8LwZqlv+i0kT6JJVzJAs9m9mIkVRdSau7A6EtZ++Gui0K56HTnHxdBZpKPLfaMY/Vq\ncO5ShwiXPBEzE8G5dKmjHC+z12W1EDxgsCLar9+YOAjxKhgHkBGfg69+NmO0ydwiFZtkb9kQn2n2\ncakas/WtmPRcBrFKxTJv7hrqsa0tATeeQxEfLYe4qtlUzpbtLY2FdoNRQlSxUGJ4pGgiCSx+x5ri\n5dbUwJzYin9/1AkNrajyQ1igqFH63Oe5iA05U0OBHL1TZbqVJu91v+1hHGccThB7kV/xn+sWCL0Q\nmMULWQqEWLR9aFsTO9vP+2fvOf6Zwuefn0MzofCFTwq/kYuMgyppHBeqD0San0S3+DlRWFbvQxtd\n/2tSB+nGWbiKevmP/K3gE8oRdXigzg7xbPH+gh2lCC0wJmKwTgQwHIC31x50ZJkg8cci6fVAAw/C\nVHXrDrjZSiroK8utPInMK9UgiLiJZaxnv6VMTQfV26pYRuUPBEPpZ4PLypuOIcDs1tS4X6nUNDU2\nfNyzzsyS7Fs6nTKsfTb13JGw+dOOt4lMUIBEU84U5RQKL+jrymEyKK/sSA4kuQYjQXLCHUIIG8G5\nHUgZ9GKsNo3ugw6mpQdnfJ5cW5I10H8JLWrMiCExw/s1EXPyeM59eTd7T9tDoN1rAZKPHG/JN8dV\nh0oYFXVBv9sIAGpOy1+yMXyrapdwkmnq9M75xOw+4tdRAWNlhGUgeer4qaGwM1AiZOh9ICdC5zLx\nBQ6+b4pwzgxHxvbCVYSY3J/6A1H2OWZ/DJsHbkCJzKyyIJI6c9Sj+iL7IWOEz3kPoTdwojbxnFjE\nFHyzNYqDISswQg6KXYsPWTEGpB/obQREvd+ABflTfjzhr3Tjftzcg8LURNmOgUQANWT1DWQSbC19\nmfeCmEA3Y+mKQXkzlCARoH1uXMPPUpVC1ipWTPqeH7TcwHjaNCNhXgDS/uk2Z5GBD8YiHzSvAuVf\nKZvULyg1j21LI/bSkfQ7+lk8ROtqWPv7/JtmfKo4EJbyI7aQPWjlTqdH9mV0ELtfD7EbTPEhwZZQ\nHGWfHrL778ObaVgVlJ+4cur5V5ysxaYVfZvWa3RzOCv0QqOo2lYVW6b1BV6cZPLYruo7o4VgOq4K\nzMz6Tv5RTu1X/Q0sXm1kmGF9b7w0Pc5x3QBxIGCO+NzcC9HZekrjxRIqqqG9SREDtovJy40tvW9B\nVLyL0e4LS6wq+BG21T5Tm3wStOhCHnyJAneG91iZNFnrTY57YkATwIja/JJiSnDtzisBcdOXsnE+\njF+WIPe/OXaP7EXFwWnvQcMy3CEeH0v9WQ8R0k7m5/5LJUSKZegVF2vImSnXZte3+N1jLmIspK2X\nLSW00mKB9e7X0tmoffFcNa5K91v5qCKZP+jH9FlXfo6FyNfnHZeBtYWE1rFrWkkNoyffdTydMxU3\nHsE7+QvtoAiGifQOxWPvyL6jtcKpDsPkZKwWMaDS6t6CrUW2+7FIzIySi4GPD+UtldMfOgfX/xY4\nRwOLpHM0qz77Vk7F8r5igDm3YdRUclJRj/9p3PhuaGURCCOfvYY/1YtGyn4pRScUV0eI5mWn2HkY\nPB1KwhTPUTGwVWu7Y3fD26njzSehEGb15soneI8/j2u57nBdio7e76zBGd1Ae28DCxlw6eheUL+t\nVfbb+l1BrerQeAHVxnm+duuLE+rNrPfp+17NGTOlB2Qf1rcFqQWYCmgEI+VzyOhWARntifEQ91cL\neG3JS8IW02lPLDfwgGnw1jdsBDrP490+YoZQxAo1kmK8lSjgUXuTchXZtHz6I8/mHaTDsZ3ZJQA3\nNXIjfP4KlMMnUOG5LiaeDZ03uItPx33c7XIlhC8wCHIeOQHEnRoS7Ah4f7M3FP3oommN4YQxreJR\n/uAHpkr0sCdoRVU3J+7N2vwSP685CNjrqyl78reB2aX7Ty3g0hVKTHlyPzRgA62N3Gfb9vMrk+W0\nY78yHpQHiYOQTwAsjZvyYBwT9f/ldXZVwC1YIvI20GQ7kL8uvhV/+zbXVzv6kyjHg6HZIY+D/+rY\n9JnqgDOXkANYZNab/6uv2j1ojjDqBOeZShxkJkbTwoWc1yT8OmnQVIXLmeGTpGuabFKI9Zi6Q/06\n+HPwkG5LawIar0MHYUs4lb8X9uKIVauJZHO3fCfDJpfE7p0weI+DMayYvriGCPSu2+0cO66waMD8\nkoQKpOmFxHOrio+PflCURVPrWAdtiOVWfTKpPdCUgyjcX/0SNGNc+GsKLpPgnseR5baF4rxbWWCj\nkZQJhVLuPemR09jsCHluA70+mz9AXQAg/pa7bfPbMldU69lewVO7xbwqdUDy4hdTZYJCwX9TNp1P\nNpCzdGsgoswj/88Cy3icvq+rPBdxfqogbUZXI0ZcBQuBSscM9RPagLxJRYfOWbvPYakgaarvMURQ\nUKkmvS7oHX3jyOH166f1V6kX7iU1FtSODnMP0RTIiVB1jMY8PPv20LD5653dtu8nhpW/yxdeaulB\n6HrUOModOutJHPogWpEpYquKf+DCjyztBIiWtsXp0rIdpdackzsWc3l3gZdiLtsV1BhLCsj0FJw2\nU26qRLCKKxk0axjYCW1xbCcNn2Ui03uJuYtzjrQJU/ng+M40qPAoIOoonXkN2va+Z/XjAlJvXRLl\npvwhi82zybVUV7GX+GBE0mShC/h7yvkzFiRrRDA/RwRQur+2okCdE6dK8hr1zzFE10JBP0d9TUS0\npK2XqZN2VJ/BQSHEd38SApjeg4BZNbFB4+Qm5v2hy9XGHVWFBr86STemwiPK/HTKyvHbsTG8gt94\n4Y361rCNBFPqISw38qIcz8ooUjFi622Y/CWCjDz21lLX3iFDIFf/ZxxqVSlJM1NoqsTHOTYaVwF7\nhlfj1vG0b3l+cGCZNArEGD9fxGx3Z8OwL7Bzs63ULFNDz9lM2zFr4UU6eL3vuRH3yJfuI3H4I77P\nffLuBWlPBg9kdeOw+bZrrzSRIRmKmYS6kOz3Uyn/i0ejd+TPM5dR+qHmiFt7OZjjSaf6pYIDxuFA\nDZ6PvZDVBcTDMavNkIcSkwsm+B0NwELE2BV7pbI7jpTpkuTQpZAIcuURtrHRXOohYiktQX0f2DId\nGDX2juPGYqAkqHn2O6TuzV+PKfUMTryW3TwkT2rIqBqzrGBtN1hU0JVrCaZAM1J928FQGECowe4C\nYw3phOU/wxWfcpsDd+JjsNmQP1GrNaLeCvX9iiM91ya+u8I0UPBSSpBhbDExnHRQ8x8L+Nxrv2P0\njVZpcPraT1DfqxmICYoVm6AY7rdTgJrjclMbYmafOsUk5wRRTQVAYPBpGcA93u8qLRqEvvDHhnS2\n9RKzGmNUV0hKqNIF4f426z0tJi0IkRW0znccZmt2d8TXKzYkCOfKAliSBqpZS7bodKplqMqc4voE\njaPXEf1vKkbUQOV5HqmvUiJPI5Y7jQrosCCg5VL2/oqN5DodmIqCCTd3vdAm/tt/b0IuI5mRfpP6\nV2Y/cRCrmE+MumRavYpcem+l50tCbeSbglB4grrAtBooNSiWou5vd+6WISoDxewgOeJQGew6HhaX\nO3eGe6KfJ6TaL3fiJuZF3hZ9XXqyDuGrb8nQoAt6dqqzzDpGo1JaPScwI3EIpud4EhFE1Qti5v5a\nV3Vl1+6/UJSBa8V/BrByhZyt7xmrFz+1Bgy6E+Z8DAH3rQXV6mKOieQAoUPkW2mh9tx9xnFpbSsZ\nTPYhbec2cj4bGLI5crXAxEScCC7qH6wD4Zgnd+qNl2NdDJqKJO+4hUlTbuc5wXXvarGBBhgjMHLs\nXGdXVwHOm+Cc8rKXJvr7+5PUUtnwD8gWKxJXPimyS72D9CW6d7dkhkbP7lFlaWAatkkLR5ARwFbx\nMZAF9W53PRE329iWi8zBjf2WDZBSN2Q0TcA10dOE5nbnbfeT01IkqmqARAkQh+nTwL9T3bR2A8Pf\ngmwCqBj1+5rRlYslJ8CZOrLDQgDuLDJ0EbX+JSDcQd6jEyne6hgAaoZs41ByP/8g/PE2alqR1kRZ\nTYhiSUk5FbaPSLijYoL5o1w7Zy0qqdH/p9GBtm4JO9CVzc6hI09H8Uk2lQbJPzvt9YSlv3v92sQz\n2TKxXXtBQ+mUlziFQ/8BYitiRqoE2cdR+mE5f1X1YvM49qIirMbEuumBGiHJqvkqNUZBHU0ZgVKg\nvobG6mF+vwwH28e3no4tQ7zOa/fDVprzZjLGnvdPUjym+XCgbrKyypqUWKJ4/T/4PjaanyzPvvXt\nRlcGp/nhqI4n2u93okHPDK6jV/5phIyTYsLiXu3CKgu+8IRYdXYOiIo/e1Y5WDTKYgQhmBVshF3g\np1hGuj0SPHrrAaGaEG0egjAyMEWxwFicIsMjvHDzms9wj7SGPo6CFt4YMfar870S3Mr4rqPPTLEl\nKaX83QSEnw2lHk1wIWIFRH/7JbyQRSmJQSWe1dyCNY3CJc9ckpBwv+ZE3JjOz/eE9hu5cxojJXoW\nlr5td8y7IAWzChiI0YLBwLJRGcSEKYwgbLcICqV6JillP9J4X92YlMW6BHoBsMhB1DOl6TyZgMNQ\nVlZGWfNoYelupoRkIT8M7MzXISDSzqoDIKM5mr9eoSAo8ib6YK3ODFN1Ipi0Hm+qUVh97Qb3LCXy\nJ6TLZ7yBPe3PyN9tI0DKKMQaEf7MIeR/pJVXBGsWw1J8lMeUKMZGj/PNQ8jCoeKR8IQWRQA+u08l\nvi2HhJO/OOKzrT7wWfTqQ8JQJWoego0wyxREKsmJVph5puuURbW1rqMZ59X/1NWVNk/LbJ1gpEhD\nRDB7m4Z37EdY60O5sOgWAgfgocCGN+qw4b+xKacYxMN4HjXO+wJq18wCTE6+j/Riq53L1N8BhQ8Y\nGzmRansnzeytnsaTfsvP369sjt22XF5RMpCRvIpwnBzhVtSbsoEOecovV9J60ihS9Fe3klm6gBY7\nO27ky2+Nqy6V5sFI8PXp8SBwkwq5pNi/BqYrHGV+KbX8d32v1RUYbRrV4F6ptibJnNz0aU+HQQBw\ns4RzTcJUIJhlCEM+J8xX7HwyaUGYXM4Vblpw6Pdu9uJT0tjyon29wMG41c5BLhYFL9bVxSB0rylA\no9dhCoNanyu2VfmWH0K1eh+YJaNXtEb0ysEmWhCOAN/BB005lvi/w2S97ehdtGEWfujIFXRsvCgY\n+RCIDAxVVZqHL8q746Y3NWuLClwgx1vHx1NcQUcDBNsRytgo9Gb0DigkKNt+dAAIGmfD2l8RTA00\ni2rxwGF3erRv9z6mzledqzEO17RKC31VFamUnhcuZiDRaRRCBnE8GuE5BHaK8rw79pL1YSIawfMd\nLK7hHkbaDI3kT4s0uTl+t99PyWMS/B/0yfBkHsKDGfriLreKrAncpEeUpJVFKdFGrPl1HIHS5ZEX\ns1gVTXjNJJrMestKVYaEs4nViCstGD9zSan6JhEmfaifIkJ7GLKw+NimA9uOzyKvxUxfRCCFUSvF\nMprZGCfJ4ltS0NYsdjAs1KQSH/5sn/PQ6OIeDHlZ/n3Of315bRk57pzLC1/aVqAi8XLsSRefF/uG\ng/x4R0AMUW0mo2mdnHH/TY/0iT8LYCmwQO5G/dkxHjhJRFJDZ3qUZid99q56MwmCVIj6WDNBu+KO\nQN6QM5N82dHzc1QI4OMalKCyGwtF1fJoK6eNGi3dVQTES3YoHYpJwy9mkxPa0rvrWLS6/4KyUv+I\nEDZZY6lbAg/ozYCu+01v8P5fYavZmOXKq7EICFKOmUroiCAKQb7RAGvnYqGcYPcJRAsDYdAoIFDU\nroKp2Ovcei4dqjC/IMmPpx2utomxn1moEPZkeviZ/h4Jw8M+YkT9VrkRWpAoADxDnDqVJm9CyRZ3\nZYi06cQ7Xi+nISoqnuU0wG4niseJcLPhRyK/eN25gKr33zC0KA1F90dGy8K2XjjGkAy166Fm+3nU\nL2M0OoqaJrHkmiE5GOorVEOvOcgQPi5mcLYVduX9edasttXX1GWuqS6e+TdcltrvITA2mCaGW9W3\nuLXjKkSpq982wMXZ6Lezt5GVq0xxPV/hocBpYZGNk1GnQrKh6TZ2oDCwL3BfXTqGPrO2BfEl6Gt4\n/y3kZDSf1MYEfz0iQOKOy+lWAlsnuPolMTRzT1cOGY/Xo5ZfvbKryDcTb6bhVTvO6/ytROqjAUmQ\nTHPlyl8CeG7hdq6DGm/TlWk+DtDGTXDeiF5IwFeBRsJPlaQ//IAkaAdtGnFztK5xLzNvyFs87v/9\njkbEu4pvPLRGn8alKJB8ZZ/E12VD5owB7dVz3WdKnfFS+ewUVFFKFM/LqRQIoLDfau36JyDEBIoK\nCc9QhI4knWpjgd3rc0Ror6hYufUfdIhZvbYz3935zgckWWECuvAIgdz5z2ckO8J2UHAmrLdWFxtz\n7NFYheF0uQVqIWu7hRMmfPVEgJNVslEfrtSENg19NvNy3vkke892kD/uoMfkVuyjAkS8PzGBrXJ7\nSQqI6VjMifzTsYMS/WQ+kXXwPhjx09QEncMmZSp0thPdg5CZk8eEvrZGprWuaWpDs9S3lN+NV/qh\nEaMcIGIuEMxbxMgD5WtZb20rxjLc674wYAzoVZKd1k0L9/5C0iSgJUwYBe49dyDOKYUMctmkESxi\nVd7eT/IqusXB5Q/PLFKKSpIjnafKrHv8yGyfnTaBC+kzTlVpb2G++mJNfwSbkDuqAvAoKjPAVHv+\nqzQVAKQ0+UOmw3T+29c4atCHzi2+uB2N0pr3kiOHQ8yooLRMdkn24q9cxynSkIZo1/dARHNNdxa3\nCJv1zraDIX2a9McxBdYXYYPeFRe//3X0Icj+fafoR1L6ZnzJ8pkqjZSGr7s9acLQGxabvRMGFAlH\nVSEB3Y7eWvxapneBKniIGGujM8MXaz15lv9RmTiEqxfRsxRhgthrhqNWOlGWfz21p8uZT/iV0h9Y\nfzfelebsnPN2uqnYGEKFTYTm43VLTKdViucgm0FyCsC5i7j0MIw20+J+3xPhA7x4++Bg0WIc2oa6\nyZWBWrw09oorWa4VXS9O4jd/qCs1lXQO9qyI4RaWmg1w/2nMaDgx3InEckVMCboMIeiaxntF0Oan\nPBiBdb1PPzTtsMmzVNpv4Fjv/cOEPRIRFPibNg3qhLCCRI7H9mgzfUzv90GEsJjMVTCAhWsuuHo9\nwGzpvadtd3ZPmPsOFa01NwPTRw0Ka+zQf07NZ5o1vtUsD8QeGQdLQQ/Q5OKw2HbA/bmpERHgtPaO\nU2pjfnadcng5L589GtL1Yn1o8CLSPo3GBOJXJ+EEsGHxmSytk2TceD72Fzn1at8SRZcjtsb4Puy5\nD6IOS7UeaGPeKQA6l11RgJHgfZbUgaJmK6tPYXZqXja2NBHNAlJGUGSUdtTyFwrSw1v9Kvbta3nm\n9dSQggcFLN0jfOh4Wx4PkZqrNAn4aYXAl1hVDrYSJYeIi/g9UWvt4lKEKzII7sSP+/Smvc+DQI7c\nKrUPoBrCwwSIULOWIvTrmc/9H9lyRuvvalVYoO1UJ4h1QZ8l8Awyua3XBfn+LhsE5y8En3VMKVBK\nHDDhGXOo1ly3kQ8NfiYxpwcHcNdNtrv6maO8YQ5GRGqef7AdwOaB88p4d8Lo4SDu62Dzf2fkdySN\nvx+zps0lGn2ew4IFCknQaUtUaHVrSDUG/NZZQabVDl4WAdblcpbCOW8uTiNoFIKFX8dP4RYXgq+N\n0wODhInglAFqObFfIC84RBfDlEA6t/45rPMvS12+uDunWBSZHyVY1Uwvwu/pnI48lV9m61OsJCLO\nOIgrpGewilIwhStXkjxdI/PB+Vez075WfTee96epvw8Gy7kPD7RFvqrDDIrSGm93FKnRHplTj8O5\n5uu+yfmzGBWYcqCbo4mJK6V0M/SJnB1HCGbgLiRxGy/WnHWjaYx9bBqMbBHImuGlpEzPmfDKvgV7\nAlHvpdpzcBlf2iAEr4jhpXqh/KwnRQ4vJL1P84YbChWf4s+IKE0AZ6f0vl7phKgUVq+P+ULvZdoT\nqnWO0Ig8FCSr/a6sZumTd2V59t1HdZTvc9V7LHv7XW1ar8fwPredD5AYEDMepb6AgFxec1FiOc3D\nykbfBhIXJE6n+Yn+BkBfyPaHQtr6CygbQYqPxrWvwqNaGqiR4M1+SnXc1ZPUCuO3jpsqErNCpGur\n86gev9iN95nwRZl1czxWVa9z2Vups+DUDYNl6OGsA3VaU6eY+zfjdw22WdfBTQW1yLZbKdfPdglM\nk0W3fK6xVQmWd7Q0MFJx12rohylS2M3jRt6ymRYDuj9G2x7e5COQAH4HvGSj1xQao0Oqt1esrJ4a\nYIqOffOvsSJq932yvAK//wpl7jU/meranK6kL+SFodAzXhE5O9i3yUroUaSX5y59xIfZoFg4NHP0\nM7zEBF6QB2GW8onP2jBMjRx1c2YyjCZC9I2gxLVNFMuAynr8b5R66ZPqvrh/8y6Mqr83orbrcV1X\njrDazLR6yHEOtNQ4bi8mN7w1RxzLuL2h058RZGlSsTBsO8xP6HAr5Kp2wBfbvI57lK6CxqUspCj8\neO92O5CNgGOfYdotXRnXfVffA4XKFtgvw2Me/hq6OXRjQJn4ru2BJA8kDP43xdNfLhkeKIZM3AoG\nTcMCW6giOWLiADsnkr2ofGgeUFbW+ngIOyctXvMwRFMD+1K5RpwKmd9uVYsHK5u+PLBnvBGoyoS7\n8/m4+m5zQh1ucW8F1QfRwl/sKSrRq0ciF10lQ6zYZB4lLAem6FOmUFaoyuBVPiQdDA1ZsbW/Oy9h\nCVMHPZwPrJ3UnrPvs6YOfXs2Jlfc4nyTMV9gez2SwA0MbPHMnpIcvsBYMqVf1NbZumEG5UI4mVji\nsP+Lo3Q+cV56vHImYilS916X7mZ0gHna6WTTGV9UyJ+Du3k0Tl5TlYLHL/ob4uKWbj822Gt7tv23\nAJnMLGCkgZQbYYRLwv5C7jFKxzPsaYrdBbnhN8Hzj8uWglOv5NmXOcg2pNyIv6Xp7o3P4/taZy/s\nbavizNn1qFu+wczAKyYeOCD1GOD150qXMwDfJGIaD722D5IfvLbBJkBz14/nzS42fO+i/NSflxqQ\nIh8W1dHgXZR1+1xGFhfpNgJ73eVqPltXA5/xNtE6EWKAK2h01+j9T0mPP+TCq80DejbANcjNu+ug\nQ7qp1/IN1oZBnRQf0DNejhOdZ3Ik88Xhwy2Bn0jLmvR81NTNbmVEoZf6/LBhkmC++d5tWUODaE3V\nMmjV73rV8eAB0kRkj3yGu5GLwWEtbau6TqRGb0BcVzUlzqvF5MPetFqKTBQY6sJENoTXq1XQjWm6\n9wH63KFczwcmFRWNgBpkvjQZUGWcCIlioS4fuoQg+RfiCszpQm6etlOglZq6tbo35s7iHLifH2fJ\nXgBvGhw1Mzh5WLkhF0SZtXs1flSvmLCyJM6MwWBe9Vg1rncHvsaqt33+9kknBEsl8yJuvLzpWHIq\nIOyjgBz9NEl5RNUhBXzOzvIRK9F3Z+fejM0uOy+z5JQfMyUHKAEhEtGivvnuKn5Iv1yGYQbKcWzf\nrLxAQP1WA+5zJeTLRbU+kco9GYRaVaIvruvNy1wYXHcRnwEui9exP//Ej02tNULykhUHv7P7iTnf\nYCwad9m+QexSnt0Sf+x7TTYZGucEUC7Y4EDC2m9MsTtXFuhHgin2e9eHMTm7cMiFUf3O8h8Qszop\nwzWvIQZOkkv91HzJT8h4L2b0+s0LMTK978OOGCGHEcqUPGyAWN7nOu16o2UjvQGFPn79rD1sub3W\nU+zCmNvAttFgu659SJhYDXnvhUoNWhfY6acclg3KD38v/SOAfl/eq+85NRYWvJtweiJRYYtk0vVs\nu6EitsHfSy055na+HIelCMTPbv3+3OwB8KNeJGveU0qxSv4okxF8YWWxztNlTRVWwx6fC7LrHTJS\nXhjvKRWBJrdBkAn903FdNO406+gwfbMP6VAaTCMo2gsunicIpS8xTA9jcMdcnCyP4GXLvQi4UckD\nQNgqbWYvw5fxTLOWyf1Qu4u6Ul1cRBRNRqZ3sZG1iD58EIMSS69VEvYM1w5CWdFFkYZesNsF2ZAC\n4RTSQLixyOWbPHcCckgl3/E4FZCkIi1A0xsbsyirad4r4OdBa4ELnPi0ASWPuCJZp8QxIx9ohBTU\ncXKA+rgTrCgCLzavqrmNtp3Gr4WW1sfls95t68GeO6SScz+13sR+D3gkP998Q+3+9ENk5i7fJ9/i\nQcLd8GqnDZaJ/h36F7+cUQZg67jcA5APE29UEhwTU72sbZWGcGykxoFo6Wu8gG9xLNC2pPVSdS6a\nF55fpU0b9k7eoRIM9wJyDoF5jVRrL+wNULRlvZpfiLOpSwjUKnZ6ljjKtTt6qfsye31ZSpQbTEDi\nei67gpANY9oE+l8zI+oIf8eBQod4TXK0aotrRsx0T048+WvCuIiR+iczHejTE8Pdi8+enWorNp6u\nCcR1yfG23NU1xEPqbMjQdnMIw2T7xx8WBpnaS+nBJ1gNENmT+JS56BNxD6xy5OvTLAQXjtm+KiG5\ncnsBBCY/Am/rByb+pNGepykPoma6lXmXc5FMpKsySFKxXx7y5zorfRE9gSbCmTG5Ltvw4142R91i\n812qH7JQQPaumVCKm33BGCVGuitsJfOfv/98p8oQPsV6SftmQusOjQSyn5Qm+dlpy2+VymZDEnTc\neJlGz99qQGTvq8/CnYHNoTodEyCv3uGGGoA0TqUo53dr7ssSRbAFgdsyRHMDxepGAcjkw7T6laTd\nqtTg6VF8hWTkI7MN6+pMfl4m1JUI3jCTvL3r/vgV6Kz3ppGiAoXiSzxy4keXJ6PAPwFmbGMVtZay\nWyEhiliGvUyzaYlZPptWWhQOtNFU7fxXPiYE32GVZIx+SiWJLnWydxbRC/WlhwgNYcGsyqSZMFit\nsNGCmXGtYx50tvzGxQwzehYg0nZ2T3/PJDCx29bJ47EO9lmaIUUPuHUmene0vI1Pu3WArggyDcZm\nv2T2/rnn/OkCTuK9/cnfLCkG9PZvw+b6Q8iqL81fUCaMHPspDM/w/iL0pGUM68CLdUwOhsuz9jrD\nADfcq+EHTkeSm1tRfg+5QtFa4PgsUd1tA9j3+oO8OS4wuERtXT8tItcS8PjZuyin4U0+G5ec8xRq\nNXig33Ho45rUFp/dzkeNN1A0r9jrBnzIxzHAQZgfdTuGWuttmgbHPe/8AhXQ1iFepoTAzqrCqBln\ndNdMPtSzeK2ZoMaHjCWqZs+s8/+1seQjregjKaPbNxtmkplWus0EExT+udkoO7IXvlQq7BgPYo4r\nRpjeAfQC8Li0QA1OIq++poHELmQg9Sv753ldrgUe7HlrntwA8pnVfa3P2xWCC5ti+tEdtMl2Z3R5\nahgZisYsB8c1LNpju99Cd5thHlHl4q8bD77qMmBldsN89OKNqPHdYrbQUxFuR0cSUly501EUip2r\nJwNftGERUEMKhO82u2cZQzDhz17Ttkor/7NeO+Z+DrmO2e4BlNdtNXxiWIprq5n7njgKw0+Y31Z9\no5bBl4zCMvNHlQ/IuBUEEIcDEP1SH8hlHzzCrOoA3/6P17v4Px9APMiiv33ExsXH8T1i0iteJS07\nzLASBPvauUC9xNjitpan8V2eHxBVPDkLlNHX8+hobBnp5vRMSQcBO0JFm33M2lSRBE9ZNcgYf+g3\nkB2CVDaFyDLLvhVdXW034NGCc2deKjNDfZrSkVEFJH0aDJoEYzxeEnMh9d5rIKx3VYmcYHgw6JGg\nJBhUkNHmCjfh0vCo+hjMCPwH95m3vUFe1wKhOoXsIWyk1QJ+QTR9t+hZTowkYlQprcv5t2gWHJYG\nys6npKLa+KanvsrGVrXB32uysIZliELY0rvCu1lnLfOVG5o6VxHS66qJPHimhiy6XX4IgXd6zZiW\nYO7BOZluVxA1fF+ajFTsjY32A70kD/tRSPQpYwH9EMaoF76kkDLhsIobb2kYNomgtk7M503onnCd\nu64Y7Grs+FvIkcG6rJ/SZUqfoPbCZmvMJtxhS3d9eDphfgzSyg0uEcbc30Scvx3MW/Ka45FcPqWU\nTTJuaFa5sYSLgrtp0/xa2z1ZrvplfUMOfs1Ir4WbJ9S9rWOTG+MOlyxRJVANozxhNnL+p0UxBvIK\nFUnFSYxOeTffvL/9AiuwYKEGlG8TP4W0kgfeL3hMAL5gpcXggAW/2zDLba/syJhMD6Tp62ZpzZTH\nz/IPQv4NIEnBLbQy6BH4d0wGaSLfPyXvaUjY7YQ+ntuC31nihw1bQwaZ+MUWyZRcmiX5r9u7+XdL\nI1L1yZBLfdvFM+nIfXra/bYYxC99jIKFf7pNPlxoLNMW5ArXRg/FY+4oEjkoCU5VQUgZUNAuJNxU\nkjCdWYT/MrC1tV8BTjT8vgZqsUVG+9Q9BiJFhhAhyxYKch4SAtURNyGrLtp0SSnIYJ3B/ZVjzn7I\nxuxZZ2v2AflGdJfcDL+Rr6aLQdbjGj/+0zoSVfLZv4JbXBQwhr85A0tkeg6cGcxR9Vza/zc7+M6g\nJ5ccWZqPWubJGmJvKwm8cnMa+pcVTxa27WsCDyvS0Y68jalHosyqevLvcB3xDPTsn2uHlV+VpQcj\nV0VFxSXFpQmg8i91a+zS4L7xHHbrjcRUly+muThjtgw6ig/wF5IxtSpj5x7igdPnhA36Go4s6ycI\nIiK57NlcBNfiebdpAbi/w5sM+taV1uXqviHauEuFjtQA33Ok8ch86BdmtrhnfMrEJ8rHapBXrVht\nIdcFv0tQUfg2nx+8xWmAW0dbKjOV9EeqQp0I4g9LeZD5GoAP9n3P9uxbxza4GAUXxvg8YQn638cD\npJ08vWFIXQz+R7QyyTo9sX+L/8OhlUe57VaGzoGGHeg2RfhPUXKQ5g4vkHkUQq05nbCCuLIsc/NF\nA9VSgYsetAZd8ab3oI/3nSeVQn9BqI6eeK76MN9q/uGinlJrJwDKg2lAwE4Sx1NtxZUDL5Qng1z2\n+lwVJzNItzXwfBtFu0TCpNDRouYbIY10OgzqrgN8p1Iw4yC4fdfmvvoeJBaWzueEUdTT0lR9CbXg\nnCIcYnStmgLfad7bKNKuZF0N2BdtTyt02DP4LzxwMUX9zaxXo2s/7FBfFcU3FJuvYBvJNxclo8rd\nK99uOpDhoAF68Cp8f3U1xGQs9hcQFsIiZxeJK3ILBP5gp+CyPPneqHwgN07Z3h+9wvOFgwV7PuNs\nihcq9INZE5hivSIUv1J4uqxZxw2YOvj+4XtgILMDsLBUh2/CeiJHDnRXHHXa8xyHN/VEZlvP995w\nphboRlruPD5mR/ocPYK7UdxRiSWJM3aJzUcLRi955umxUm0bw6N0pSJ7JahT+I2XC34PwpktoFJK\ncnszLXBWbxz29fPMUkVIgrJLImaca+mZQRabAzDdtkZVBJfpiL95/WLyAlyEFqHx6pOn9YdqK/x8\nls+aAzMGETkfnoOlM6je/dTzj3l6Qegyttg6hacm7+dwNcr5RLP10+lmLI47KpEZMRH0JtDps/ey\nRtCY/uN6O1UaJdOhdtyZCpou6ZZrao39nAAK3hsYPS++aZgjVAM+j0HZPfDxzqTE4Wp2AHE0vEVb\nsbWOC5JkhFUEsNgxf3CZZek4tylhZBFe2qAPmca7Nr8cX+/fGwJa4zsstW1RSHzzXp+ga7T04RRj\nqKwX8lhMp83DKrFARIncMkCPhC9OchoFv6Gq/qOjB5ENUspxDy4S/IOsNdRpKsjsoA/E6+aiSeQp\n3DWa071ADqC3V/jEDFQxKj++OP+/pINq6Y1craLIugETiEcpuMZtIfeNmTtUQ9bQlnnIHSMgiiLk\nEYO/fwfSTz7trn+YBvKL5vAPEgd8EXnJTQmYglGi3iPtfYZCecyOfq3JykNYoLGzlc8l+lgHht6D\njBryf+zujUdATobQ6vmyUQSCtmPgv044olqWdpLhzoc9ASuMzv1Tf60b+vX3nQLZbSJuYh7SHxUc\nGxaQJbaAUNbtxB873Z2xQaexfwD0XIgmIrV4nTsGA8CKeZGD44WmVGfF2zAEj0Suw90pvxZ6ak52\npnNXRoiYA1GbUbaAPifn9es5nNMox1WMhiiFqkfTt6QT/LPDaI6pctEEKbhZABvzuC+AFV6ApkFQ\n9sEbC67oJqc2L/F5+EIi5bC2E4TuVw5PGllkgLBAmBS9ZJXLt8W/7AZzh2zXOiztarPYrGxcQWQi\n1NqD9kbqMfjq4GgxdfOh6GXp+/8hzguNrB0XOLT57jqu3ukdyPI/38f/tdSR8rVLm9ctklpFxIp1\natcGe6ZzLhkmrAWaEgXu+rkvalDeJJzYMCdssUggP9sbyIBqNm+bu0hs27axwtzO0aLTdEmRy7BX\n02mW+0eM4axPDPBXp7Km1zDETT9OuwhMcrmk9IDiDrbaUj5u9Is6RN5ZNoT9chv4XZJKvLR2ut3e\nQGCvbdUAVHxPLCOslYfGfXiNFdwL9ygx5Xv94ULNBynBX65Yc0v5uokgRUlQFr4KxsdMcxhnJrjd\n5mKOOdcKDyXcYKKk1YrFmxp2Mqa1iRK0gm7BoGrH6dy8ZY4obArr8X7BYzzkf4oUx8I+5e2BLyig\nSCmP33zMkZFpk/Auh1rgfxz/PbMciaPSHZvrsiCsT3mIopE+JgltnrrCcjK7GAdB5hrTS3w3SR1y\nGBavVYxjiEqnr8WlVGP5HbH08fIsOBlMX7LO5sciII0cGlRpn364mCbdp91BslmVrQoxcPaj+TC9\nO0MZi9C8aOZsUVk7GGBEye2EQ6zuEpA0PE6X2sUd4HqfaTrtQg1EivraNouAMLztKnLgN7pU/ETf\nK4iMYGGJzip/SjpXL4XIr62c0IMMYJzIXHBaTyrZ4idSxkM6S6Q/VUPOjO00HKdaRqOIH4Fl7siD\nQGdPpuIRj0b31W/7wIswcFZmCuzoZQGgj7b7P4nLZ1ugw4MHnHQ0p0zWM+A+R01iDJDTBdfEPSsz\ntVdGAoTuJ+O5nYpHMc+IAOA29tvUF0hLHKvwz719ElO2436olcY+xVc88CWad1ptcp6aodqcFyUM\nOlHeSnAgLnQRB4lEfJKprHEnN1TrjL67oHO/cABupwcFGBhTJebJn1u/nizRAVf+CKSUryUX1plf\nq1Wg9A52pO4nv4UPs5j2/i4PgDiSZY8dZu2YgE043PYJ5dEjNrmyvjaWkjFwtziqqKJ/zAwzxSfY\nFx5VOVen0XsXcoLpFHKH06Nbml4lnpDAxCdCAQlBhJagIUqVZUEIMzzBgaOUj7Y0E/Sx/MU06AAm\nb+hjKhJ4ht+9FDe3q31ngEpHms3C2CB73sGjLP85VrkgocaNNOGwWb85+dtp6SbR1oOXKGSgDIuW\nWa9nFDdb80zA/9MYuiTLZB0pGf2ysznBH4gVaJ86M27pJbE/oidnAlTQUPvFB38TOYQNTSnCNbmC\nBY/7Vz2hDC+A4DHGgWSJ/wWGblIidbsZpgHg1Xo8ekbgWacICP4eJRnFY0h99QUPrb9rr7nSKoVD\n4fgt/CUrqX9nvnFnEEI8eiWD+oHVrQKGRK6TnOP/839TpPTKpwfa5Qlp8j3ABCliKMAkPP6HOX+K\ndwjGgNzWtsIMFH+5fIx94smDLYyUxaUiQLsy44s+y54eVCf5XtKV7oMkEfvPoBAXlmhHKys2EraD\nKquLZQqsoRYc87pUW7KZ+/FGw76fQKeccRJfucdYfj2hHBcIaBuJUIPKrC592N7/WwEBhSd8nLa1\nLZKRMwzDGxXGYlmDMwf56Zf6OgqrCqSI/SnvV5mzligO5Au0AT5y8UGRR9x2hTLAohR3HhVudEXO\nowk0UJg8YDcoxxu0VpwoNbMLIcaEY1pemBsAdLqJhGMTRnneNxKrTtSgUwFN30HpP1fHg8FLhkHd\nFEhXXm6zT2mMHNhNgq8nbsHlIZj6lPdOCqJht4xkSQhmq+b4kwFjsVIOsR+y6Mo+C1vtZM89MyCi\n6SWt8fabXIQhJg+XGRqdh6vVWl5/YYso5T332zDvVQTlJAIu30bYPbZTre/xqhs/eG5/01Gy6nQd\nsONvdiK5TjgFj1gAUliaaUHi3VsgkrNExifz+rXAoecbj8lpEh36t3rEyvXjjGsAl6nV1UgQiCOU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mjmT3stzC/Xv3U+2KUtVN3IyoZysXfApjzYPxRGoY14wxVxml3cjWkid8wTZt/\nqKiZ8+DNGhOWsKqtYFfzvK3ApRuFrMQI4nmfP0ioaEsTGAw0TGjMc/edUC/KrxwpP9WbWlpcR1Mn\nyRmHmO1G980fLf1P/q5GKog5mVjHFI3YGEOry1qcHAJR2dzO40KJ0/5N3/Pxa7i6wNIJh/mHzFZ+\n31kRMiX98q/i5AnwSm6CIHRH2WptfuJJu8bOdHyEc2X/ZykVW5x17fso5tTlUjx5p+HR96FFUaBH\nlCZQUHaHREVDgLoo37xNLUuVkMHZqp9r/Bd63iatA1vtI53HEnJpU6AsMLIsCdkY+Lf82Feavy1/\nXEAxqjo7H1QoA9YuFHqbS5WP7hI7NfNQMDjoqprgcz9/UB7xC5WYr8rq2d5mgeAbnstt5tE7sQm6\nQgLlHockY4CJK8Xvmv4d4SblYXDAds1reKTgyhuI4ZtI4IEsIdiA6/FCJ2Vtw+GFFB0zIWutZ9Qg\nvRS3DxbGOPG7mDhBr7DndSkrx0aocMGbybimWSBSg54OO8poGqinGYfYKzIcnpmV8De9rNUYTd70\nICpozYFwIfHD6uW/tcf8vX5K9TD61i5pXIBimaenR5BI2PMYIhZxYqmWN5m2C4lpq7eUVSFU6cJU\nDopA56H0YzS1Yghkaz6ccapw4+IWSfmbW+U+xxGGT3wNd/C0LkyFKJzdCEZLxeZWC2Om6YAKNHn+\niFQ0gxa5wWQPwuJ8ZhYyqSk/q1Ta/GqqRzNbWLlZC4xztgz3JY1yx0g4gGXDKlO705YMD2H1sVzh\ny8FE+koC6h6l4i41cL/DFsmJm5Jqj52bd3iigktOLK6QtleXtA6WLojTYOnJOguFYPtthxaSvmGm\nqQTuLmCdlOWgPxQizNJRMRBTiuN87BktKycizvXRwigxNRv5V2btiXkJPtyPyqkLA4WN6rCMZBko\niXN3m7e9ovTge7aNZ42IWrAY75oe3jrfzduFMjJB7BHwVaV1dNpZqNe+ZP4gzGhO6yKU6gUhhLjo\nhuML+408orbEV4f3IS8O1PfQ+c9afO72/Ivqt12Iq1YNG3EKdwt+NulV+j6oevJWc1U/vV8MrQa0\nbeVkn5LMWMAilgmbX61R6wISQo0NfBGdFL7yL76BwJ5wauMZ3beZYu5smvlVxpEwVhQ8fFxH5Xpo\noihRZCSnp0L/BG8e+f6/sZJ3g939OWCjOd7v+b1g7lOXhRH12gLTb/5yvbYNu6R73tarKDzA+EDC\nV6Cjc0uuB1aWJB/N+OrNOcVXKhZcotiTMF4vDqfRNuqt4Lr8gjOQdRbrQEveoS5Z3dGPAUi07lqg\nqVZaKQNTSVTGNdFooKDV6jxrbpDI7VfHYQeRlcfaGQ1FG1NFjzlHBtwZAFGM65hXUyuLRvTsfmyJ\nKoaS6UFC1MuuQS/l45/VFm1tfQmlNWunhV0kpPrB8jg4HzKBk9f2BfqoHchtOGcUKTenprkzbPfn\nw4lemz9G4I8Lj5ly28uFVHheaCmKS4+8HGNam+xtZvyfd5dpBY8AcoNMtHr6i4UmfWaURIdijXdH\n4Bmll6uW4Pbk+DGTBh4mPSh2on/JXHVKOI+tXmcYauiEje985N91S+0Na3tbw+coqe0WLnAcRjrm\nq0HRhBFaPvHkoNwuQKN20uBjwavtz72na95RG+VD89klPSBmoG9U09U91P6sJ18GtlDxXCP0UAvS\nYwS5AWhwvu1ZBenlPuvRWL5SCxKd60mnVbKgePL10ztCgNJWKHL/tYG5erl6R7VpWRMeuAsivG4L\nvlZh1VMUk7WcEFtlQ8ewoghZgp/iUiIGdB8UYFsMC2n0jF2KlbD0qxkuacheyV42MhjTNrWOGJpP\nb8cLqovTnWaUaEQR4ox7qhg+i7lW7pFMSIP9k6dZSVrywanuiKxyZEM8txnRmifM5BWdVlFe7o4Q\n6LDdZw4TPzfPC/79pncGr4kcfXBeItIkCz2Kb37YPXMbPvCbBJ3buirX4xlN4U9Fzi5U0OI8rI/m\nxEaubhXYIo1C1wVEbMmhjjAYqm9mdtqwtK34nKt6UA8yzfBAKUcRS9C7ComgLKAnsqqYmQ6+d9du\nQEqBOA+dGyP5ei6S8XQuTmoeHBEzJtkaDcSReujBlwUYKT5jEDk0nET2T3W05RN8O+I1iuCL2zEk\nCBa9XojaCW7WnyD9fHIfIlVP3k5fyrMDshYPSJRoF+L3za8tcsFxoTB29Q6BjKAxZ/R2U7piuOIo\n3MRAXcIwBS55HqoJGM2SsAP+FtMEdbi9rvWNynjnYLT3VWrn9y4dpa1PzuBknAAIADZ1iJy8w45l\nKMoZndthreWqtx5WJ/NDeCbjKlRUXo+VcTOw5wfPGjtROIJrk+a0pBEvk9IgkLPXS67zcTg3SmX6\nqQGKLp8Q4wEM9wWWnL2h6O0wifvd8KNCNPziDdUS1b31LePR/mZo4s8QhVTskrjHFAb4QUbPl7a6\nHLudISZ7yV3Gmp6lxCIVCJYIiPkLiVfwQRSQViwIUWt6BCc960d/MqoOz0fwpsTkdjYr+EqA4FGJ\nwxJLPlTgl2lMVKdWumgkU6nREoX2fmCnx53Jl2LcDzdxTiKv4g72G/QzytkzP/3csANiNniXJKyb\nyPEYM+lewTjlwyBrvA1Hseq0rwEyuZIohPauQrtMD/CqgPghUCPc1zEUWqtbD7Cs6Wa9Q6i9cZe6\noygam6u4DqOHve4zENyA4vn6BeFcxUULrbhaf00LyIK8JhVfO3PgfxROzcPGkUTDn9lNMcgSYFw1\nF5h0O+k4KTZAuh5WmzhA07pUadrHIEWS84zpb597LkMmlP/Ir2b5DSd3a9WrRzXtffoW6wj+dqC7\npakKeVaDaFLsKew4NQn/5Gv2SSsl4XFUnLgN38g3e2L47gMZVmWlB+Y2pxNwsAyXV5zrfZ66+6NO\n/atnQFy39BdJa/QlM1kXvILZzqUOXKGZVYZLaTWJEug9PUV3sxznlaY+cyInU/Zyp4GnlbQ0XVJM\njjTgTXNLU2xwchHYZ2fBegrJgvIFGdryBZ0iiPdHvP0oKTrobiiLLzbV6OGhFV17NAM1UtiiGvmX\nCecPeJZhMWSNd1sR0zXBMsmK0TzQz9wCoe+6xVsyVVjA7V2FOPwHS/UUbVQY48xEuz3BqvoRTDza\n/Upe/JHbXSk9IhwLJhuQT51Ra6cPMWmXfgxXBAUVwMzzMx5nf38uLxEbI8HuxHJNoAr5GGRdDbDM\nvIaZdGD58IBnjKY6oHp0HRYu4WKaLDRblLUdGdvRRYTa8gDWhSNjXPohCsckVTdJP+6e2e4QOj4j\nERJFaK63X5h0QsmZOgpBr0rJwPTHnVY6GB3YKBw354eubQ9K7LofK66j6q3zT4Guf8RJUbdEAwPX\nO76Nk2K/YZetp9kO7l+c5cAIr8TwXPfl9w6+CZ8CwysJcd4GCwCkfBAE6qXqEVKayXnkzL+/gi9q\nYhodZUcg9N6TE/MQblA4jb3J2ttB1IdT6RQqaipYfiglppdRbRW1Qij7hpryOT2LWAgda1QDnOCw\nN/aRmOHe3cYkOP7spl87Ts3hk7E2Ax/UCeVxagIHpfy+FrsHZ4qiX+k649T/cfEl5rBbvmxA/xiL\nCwG9iyKqxglcf46ESxutKiDbBbgTxm51oe53JUdUJ80WTQ9/VQIlCKHVZPeWam1by0CZhhQ+FHPz\niRM7iAkCLl0ad6jbmsTBDB4Yo3j9GzlRn4OwfvkX+1X6Br/jpb7Ods5R9sYdCU8iirwHrrDeyl4P\n5Oa3TjRfEeRc/j9P7DyMx3ksTLodItG9x/vZWgOy4iFOa215lI7+X25rZS1Ummp/5i+Xpg/2bqL1\nYc6h7fbQjdpHUXjn4QUz0LYvmc+BNdDxx7TgSkeXOeHhdOTNPZBaDLDk2cy+lw8H7HLME+RVBt1k\nsXgcUBHjvvnpcteXo3EY/4mNbR/ZqLeXimXlWhSbjhCGYDzmqa5rgtz3n/CYymQhxCskPAQGw+sz\nezc1Bd1Gs8eiRp5AYUfgRpr4jbtwjt6z++6Vu8p97biVpBs1ExN2/VFrFqgpOJw9uA6QDmVZnx8t\ntsVnG09ksxL5q7LXryPT74zfhepy7+7aTH5YUpDpb2waeTIFvBdg8gmxXZB2ZJNSvEFEPglZ4KhP\ns5Wo15NcuLVfQySWiiEeFOZVqadoOuNZDghUEifrUf+33tFg6SeVx+zBDJbH89YDSGPONwYA8KZ1\nllfpAVGLBseobFKvocGgdqQf5YsUQQL2aNanPQqWDHJHr30u4IJBVKuluk8tjx90eD5z0fjoCqq3\nJds3DQnYjrQ7BU2xCixiaN26VICrnw47sIinfFcVXPidugt7ZC/KdJ/aQIVQbkrgDLjDxprUS7W1\nFffseESv5PsMOXQPCsFvlKPUCAAM4JKznpl/d5fx73jhcyMXizSXCoL3+8p/2BFB2u1ZYbisTH6V\nHLzAnIYsfS7eDvpwedtN7UZnmo/srjqJdMDTnCXrvGjHEr7252l6Ipuygr6C+WLPMQU9rrfvIwyN\n7t6vCh04Uqaszzc5CY9Aglhmwt/2Y5fx9JkGZumJynrdGXP33p2621iPJ4AevXZ3fdpNsCsmXnzc\n03cELWhMybwOw1YYoFbfYaz0s7PGleQIeLnk/884jAZTBzjHWSoLCwehSZqGTEAap+F/qiwHr9if\nuKfdQfIf1sOFlHlFnmEytGa24c0rloKQYqZPkuEVY7dS+SDs3W/Bcfs8x0goY2jaXFj4ZMP5UuTc\nyYDHI66HFcvlFknDksj2QlDgRfqZvhK4nKn/ov1YLKpHRhjo71lyHjJm2VbSQ+0OKQv8nqczLIpC\n2mynrP+VJILPijymLq5vCPGo6QllgLdqvuNKBIsJJrlMhIMyMmnRNJvVS+sTiwwsxinybxQicOf4\n34R6e7oY72ItEWWzrwJMtmMMcQrNBoRVgZsDnDu3B/iLN9B445+Ia/2xI8tg4h4bWVtfUrPF/GHF\nCCMcBaai/7iqersKU25P9YqCrW5gzK4yd6hHRVmP/GReTSC8etOcS/dQ+iH7YAw6g+VqwGCE9NNq\nrDHzSFNHzcuTFPuPTnjdDyBuk8tgZ2P8L+upWmAB8WRT08N0FYWxRVHTgdWwIb++kpR4oah3SMVh\ncMdDNeDMRXWOPYx+eoBFG4TdDky/+Rpt3Y3t+kXs5rBtuM3mN6lO/N62N0YIWBy9PPROt6ABLhjn\nkTSPxHFYPlq+2tW7Yq6PpB3gOJgIpw6Jd2FVY/nnHFVGLeti1SuPxoqA/zB+RqAZ1ugF1/HuD/no\nlOzP6btVSLptufMfKGXQlqJurAbPNswzU1SgOzKKgJWsBc8A1dZhUmmODZr7QJWHHjXRe7yJioTB\nSe+1t1P79UExlkY2Av53wBpm/Qf4fP4wQc1SW3DW0IMbQtjt9uv9/X9fGV6/G4GCcNq3idyucymc\n5DsqZ30iU7nUPo5TDk2xTfYTo5J6KDFbWg68PBTUjc9YU+xUqFwxcpfCVXhHxosuzfUSnP6d8DrK\n3sQNP4khBnas9LtuKIEewVH1iv2IiKUdT79XbsL/vFcNBq0+Sqvvg8Mk/IozOebCZTqLA+pRh8j1\nPO0dg1EYBx38k9kKMWWaaucDeaXpyGKEurCt+rNNj6O3iZ4CRZX9o1/noytgel7upuLBzZqGwGps\n73AtMGLpnD77WEcHmk7vCb/9ZIQ/1JqILIS7tWQrpz13TnS0vYnHyN54RndRSVrH3tV5/OmRT8Vr\n86wb6pLSlRI3+LytODQtXr5Pjm9zRxy6ohZ3KULiJ++p02B77O1XtFtNs3jRNxHwmT1DpOf+e3YF\n7zwucJ1nuZyIc7dAzGodikj09oxWDfGZLpGvUv8slbHALDP09Q1sZYzbZb1WMxARlYmMMbOMv6bp\nqXEGb6OxN9Z+GzBYi3Txjse2FDv2HMAimBoCXDRXlk+yVpwUiCn5LTOOrLgekPXApsjOz7wN1iAF\nuPCOno030qg47WpIfuuAkwTBNanyjM9t9kGvHBUbYvNGJkbeRm8WiEhVGVnfSDbFg1e8sBlL0Lu3\naMpK5PBpegs+vk8K2IkOGYvR5Aow1ZeA5q1rcMpEdIMR3mvYVfmtKdsviHZ0E9byAXZKlxdLV500\nemm5GQ0btI6qUDeat0/afCtAal+KQNfrpHPt/BKEshvW65onuKtkGdVhgINJh2YjRt6jDRwNZQy0\nt2/zk33lRdcQQQ8LBhOyDN4ulcQycDTY8OirqCVBDoNZ+9yHallJ2KKSJ36/U8NF0hahr7y5qtSM\nA/CkX1Sq/WW9AUQghL6/flbo6xyPz6Bk2CrrAkVR1m8WMsMYMTJzDzfobDkq/uOLuUcYSHS8GNM6\nIdJqSHQHu56KgPK0O/DnWxNXJkyeBTmFrEEAeToW3FoLlXfLwtvWmC06ciSqRnbm4gQimtKLA186\n3MaT356eSiGNv5qN+OQ8jv9hOKg17JmP9W2QWQxotOSiN3CpHK96mnBgBkpBqeksHSwkZ0Ym0Qlr\nWv4lGLAVFUI/rN/rGeRGjup/z4iwy542LcR9kEYZOCDY7F+46FcaQVcgrEM3BbZM1pZ7vMLZbBAB\nNIp2+fxvCHdPb2MYCkQJEi/lNoxzKSXQtUF/XliVdGDd/gJwms8Xkb0HYbyyJaWmfe/7DA0SWmmI\n5fHk2ePB/BvngIkwjKN6KMMHlozyCxLMBeUviR479mhHY3qV5gjKRE18cK3t6WtqD1l/r8fKmf2w\nmzxkLYc44rJqGUZqz2o47L0QXKUl4KpIGJ/PgoMPvA1kf0RdRqeBduHyjVFsKxHnVpN5TcWOPpEw\nsnzFSf8uh2B3xmR8tN3FtBy76kvQdN+6jOgMRDMtqYF7sGVg9vWPkeNNYzWk3rNC82l1Zzzx1ztQ\nJPblX9T7Eopb8dQclIpQtlVlyIvKm//abXhCgGVhBiQO4HX0Mien3FDZ990Z+ACbN0ccUL4Q1a8i\nxBtv+PWgZCeEA7utiTzOAPee3+34gAm6naicmXjXFCr2YvuZ5nD8J4hTINSaASRF8YaSrvYywwTy\n0iiBeMiahZnjX6Ra2SrDx7v34srF6/hoMCA8DyH1mFmdEUrCRgE4t6Hi1YVAINEphDeCGVVAVZ2N\nPykajTZihGf35IIRqjlR4U376Y0tBRNDAGp0Q6kPtvejvKlrZKN4G7r1lJAyP09bE7KDPRmbs/fs\nNyVC8RFydYUivRE6veitQTKDOMDm6JNj7qAaWp77cujnVGbn64Bd4xm7WZeKIKIm4aYSnUwJl5hL\nD+LcQnpAu6AAfc5YHgN5y5HYw1yEUhRnMl/L5Bjz/LberH5kV5CAMGc35Dn5CCsgW62MH0Klur3t\nqvDQ3OvhGmDL4Y2xOoW4kBC/Rjs4GjGtRYrXT4e2tlpknnpaKlAKV1YKawJ0W5ajt598+Y5C55Xi\nFrK/U1x+yGGVlKNimaW2agOl9VuEcCh6glCflnLynYngd4XXKA2JKIVNlRW01Xgdtfi10B5ipXZS\nZVEoJ/hncNBjVQcHqAeGhnptqMCqfg7CcyShKr61kfcsAc5VLbEphtId0rpP5V0qOrtNJAKxoEaN\n0ppVGEAI9TOF73jTYNy5e79+kav+WYHx6AgbaL192QJxAqG6252UlyKD+TN3wBZoObX12Adr3vX0\nj8zGgO0he4Dx9Cc1zYRKQf+J+yMSyWdmVEp+MKCbgyK6LEYoIp17fcKhZNmAg+ZS36UfkshviFTK\n+POKT3AT1fvcHL8OYw/QdRPMaLWPsOWPzcq4yVgeUMUgiaSnDUCDUB2yCO1vrkhPMwKhlhn0LwuZ\nwfM3h+czZAHuZRighzjAJUXwkEsN1Pgt9F4Ga9v4FpSBRve37ucHHuEn5jrX7b93oBywaPyG4za/\nsKerqFfobeFqou+l5uZHAWu9PB7G/36xCuN+gmjhdwI/5TjKnJGVa/Y4mrJHsK6xloq5ez4C0iUi\nDmzKDqJoGdws5uiPusdI5CZWqgii+tJ8UWOIJHe9wGCyFsM8DcbrnffJ/viThaJpSCiPR0zFv6En\nui3LW356UdHeYjk/6ZLmILb75WrZlIL0kBuk74qo9+iFxkDdId6A9FExjyh5C0dP0BDu7B53lknF\nihlFcZBGxzYFi0FbzdfCEM2K3tcVp8899GthOJgGu1N/qgTjg7ZC/hyW+NBVWOcsA/YI7H3p0zgC\nXErEvovgf4PesV8V5YrcnbNOLDkF2F+Hf+2W32/JFOuPVvcNZ0gw633lx0jeGk6zfpU4S+UqC6Z5\nlv2D7EYFebe8OBLKCmRA2kE6MXcrMBmFn7B6+0q/HxIcCLbSLBhEYooIbwK4lBvBHwt3ZNID9S46\nrlt9jHIYAJJLaDmqvniX1DClRh9zTvsHpSGG3mOKpwD1pbAsE/8AMN715F7VM9sLDloqgirm14c6\n6KaiDL34h1u3UPQcAYa/iUBBFD/omsncOZqodQoWJn1t78iJvCBlDiE/KRD+shi7MBiWR2qJzUV6\nvszTfqHmcpXqEKqJvAXBiNAYngR+GmMYIbTgB1YEwXQCZD0LToUOiwp5anTrAhDmS/ZUfyPA3O6e\nTeDJzu+g6CkNKGT6qnI9zSYRkn59rzdWimTbmd31+E9sE3oldZ7yukJKGm9HcrjmEn5iIHN2ksfy\n/bkuKAzgYebyoHDYTZZ4VZqRJkKaocRo0fbIi3zd65Gp3s5K7YmVN1cvTb30eNMvckNTr5tRJMXB\nQ1bruBwB0ntnrr5x/IGxj/XRZ7/oSwIkJdyNApk2te/birUbUR6UnGc4y4ttNTCDEuqggW3Cbfx9\n9tQdOjLwh43tPYA8H/M++ZwOf3HhfJjQQKysv0lOWY4S7ARJ3OrEoqKqyXAWdXniajcpDVbynsa8\nNsjwPf5WL5HPa+3iczXjARgydFiLFoxXOvEHjL7tJu91ngVLoHuKCc1sVCOdlfYThGi23uWH7vJ0\nYOLKmVWobVhcf5VpB8+yu1Am0dOHkBdHCr3rrgZdInlMue8oop0PLaPmJVMowyGjsverdCv6z6UE\nOqIUWtaPVpiBpHHD9Yw6XYxDCAiGibe+Gl6m/28e8Ym+QSzsogPaSQBf0SelV7KrqzHbId7aPJEq\ngRCDJzmPbD1Avv3QgG3iKsbrPI2KxWvxVP0dALSOEGlaW1luiCFhyVQZMjhvB2qkJbqeiTDhS7h7\n3EUa4i+fV/sjeR56deRJoqqk3M2q5B2q8M8jiW3dXI4Bxnmf1g7J8vrQ+iXPrLgC2JkSbeRZ/eFF\nCnM7HWHG7fLPw+dEcoxCvhyjiLG4nrEVGBWGXhUmx7lCGjGBUwRSXgUKYTNM+tVB/GGQSLqO1BXa\nqonr6lyJ9aQG7gc66GT96wZBQGclYbR4btuwY1dBNSMp+euELOd1xEiLYTm8oFfu+4GyZNtxGaNH\nQPGRCGjL34JDEnum18YLX1sqaLAaI4Vd3oohNrCZpQUGEPboSGGh1OhTL0TcjUaI1kzx5pnFFlQW\num+7966tMQzGB0widT/dnC203OehdRUxF3mVKO3vyZQS/QQL0LhvmTW6F2yZftZZwGor4BAllquC\n557VhXbkeLpl/vbtt0chG5IT/u9C7bdHihJPK9UT4R88nM21DYUK11SdT+pomG5JH2mJc3Io3YzG\nZcfbv8KIZsybNllnnP/EBy1sp1maLL9qN6kF8hDFHfB/Jr2elZJJ01JYHPOQCHNy+UA2Gl5QwPr8\nc9SHuUtr8rz+WAOCvege7emLx4Jt5ytymFbSfrvoRM+ZUxFmqe62SfHTEzg7ml6FYKGwZFzHxAVP\nqClbYQVma1hfPRcOQ2EPNB+IDQvSMtnMgfNCRvCXzR+Q+46QsNEdqQLttQrMkLWYUWQ/PxH/abKm\naMyBEKhbB0uA37pA7d7nNWme6VWCZ7Phlw4sTGZ9usfSAF2iks+dhfHFUczhnkRr5kLs2nN//1Hm\nujL9S2Xh+YR8mZbK/X/DNNxk5vMeM2BEVm1PZoxk2SRTp2R/vYNolwEbwelAj06fIHNm5MpYsL1E\n7ncTpnND/46Rp+9dC46VWjFitJhw6xYQBnAnAUgK5XKJoMd1ULWbXo9Obn6RduRPzN0a789FLdcx\n4OyYK3f61tQF3inIYC1r1HHOGDrI2xRZVZNZNDzADjAcygRu1Sw4WL8VBi/vYsKqVoNERt38KOEl\n9NyG3q3+6TPPg72wauvsj9vXnxr/ERZ9FdkR/nhOatd9PJBBtPaEAMYvPNJ01ByAr1H9v7EusrNo\ndtHZtpRoWhrKsTvw8ChWSzj4E7jptyFhnLEslaw4KGbKc0rKYK/kNZB6DrrEl2aCV7QHsdkX9Bj1\nPKcOWqa37YQlp97WsyhXrowmbd3CistDmVeRnzDx4swr7Q6boEig1BCH+1d5aIEO9ffvu2QbMvti\nAbcrVFpP6sBalPmiLjS15uhWV8KEGw781zQ4mqnoVw3oCKOuwjvvK/9OhNoout6ggrrMMfHFLop/\n7TagcwxVB59eehfgXDHC5RxEwiKlLkX4TdQk3bJgWiNKjaUI0iF5sXdRTcu76owM9bPDeFQ0zvcK\ndUkPtD7AXtk/vFhKjwLRLeB3UTz+YhoVaUH1daPHUMlMEH+eJQESKAxgCeuJAj8GZnyT7+cw0TT7\ncjpaqS0H1C0WUL6EFh9/Re8yGO0a8+1Wp5GoD3ceJ9EingExgibnx1rZ3dLJ8Hmf4F6c97FHtUGj\nWWra/KN5WoCJrdl6TSdm2vPt/3JFImXL3VxVhD1lHg5jk87q0UvPEFJbe56oPyUDYIHorFMXCtkB\nSp0+FG2szkowh6Po7B7p6lTueX4hCfE63q/RjQu0vNkacOGXYHvO/nT/7D6KtFG9OpRZwtuB5emu\nCGXEsehh9FDIFrOpVZN7q6ME4mkpcEBoVM5qdWoVt/3gUeGi7NoO+67+Xub8tmwmHzbP8nOXg3X9\nfNoTD1RXYZyvLZE4fAJJsmUmaxheX5QZ7wY+viDhcuVgAlnxxX0LLauJsgSdLdbbADd1bV5VS5Lr\n7B78FfM0LvFrQA5ay6ZN+k3078VR8KQ77wOOtuiXuls/asxNNLGEZe3j1Oqa8f4PJaCMlo6GC4Fw\nG3ADbVBwDp6yZwFL+jqVJcecF0yGso2WSscQ2vtmwXqV/rt1ntgPMcrqJSBUCsg3n8UAqSqyrJMP\nFl3aW/zxO8e34gRl8Gb+Av7qEDyqQnJbSeqv+bQRtgG85qT9oO8xyqlwpsHqHY98338C2Doe0qWE\nihq/+PAb/4nr9c5kJKMC6aqGRJYAD0fox21bybPmT4ZB2ZffeOrw36ME+hNkiBhNVDEW0j4LFPfC\nYTBRPHdDBONBGboUy+sX0hhLEFqDxD/pZ5nuulAJ1Gnpq5tYOdAVxsaLS4xVsiN6zvxKorSgpp8N\n6MetCHR0J1sVQSDbgLtEnrJ7/7F0wLUSS9jjxyJk3JHSRXyJQkLPrGjNvsgaaZ2+lUq84JavE4TW\n9WVMjvOBSoHbjCPnbFZC8a49DiHvK1W7MjjzSoFWxEqbJf55ZKbmbZgJvRBEMomcR2nX6WZLbKWd\noRt3xjhQXyyiLw7QmCKsylEF4+dhqgHIebhz0y70vdoOeqc0rMJsm2eLHLngRgytaRry7GtPEs5k\nEPzKLb4IzUud4aHQuqMS48KrQWjqCoEMqJC+/cyg0GMCPX8DoZ9NTjThi3KQ0Zm7ccl0zBlw3HJO\n4qeihfn5PUbsuXiimxdpDSOITExdNX2hgIYo6AHvcXqMa/5Srf1HuJLKLN77iqK19L2yGGkfG4cT\nPp+WIn1zd33WLqzGEEGFwucN4QrfZT0Mk0WseahDZbW80vLs1NuEfK2AfMYWc+gVKQjjNjUOEeA9\nEL0nVCajyreQL1X77MQ/Z3f7MKXlMZIKZ9st9Pqja1Wqt63i3HjrSEDh1cr7EQru3+zBo7gAIJNr\n9GzPVfhPzNmlRJyLd29w63i3/hPgjFiRB2yI01ijIow79xNLQev0WpGBJKnLZIkIGQdHfPjySCPp\nLNOOluCTX9RiV7C2yt65IAYwEE3Rmu0QeEMTSJr8M6cwP8mkQHG7TC26sVsjzhaVJ31m5gOTplWS\neyBIdXbYZgIWt1obgM5qbXkjN05FCv5jjW3R13d0x6cAu0lu1EIU8Otrn3d7K7abyyOqc6fFOCWC\nFarr8sTVDJSYHojX+adnx0hjaUrcMBbGBTKORHKWrTFaDAPouT+Wyu7oCi+Hh5VqU+mZe/qB7Kxj\nlgqWgjbbdcxQ8ViVvicBe5q/Ovu9OX/S/BryWWNVpNVVPrNNP7Ud6AruH/fVFpmbyTL55m/dllDf\nEsoSG4IV4Iq8y+AEYbXrUUN6PUiM0B/GGx4FWgf8LDcPntO8P7KQcTV6F6MLG/Me/gsMqJg9cTka\nGebbtdVE3YGk4XTN1vGthwkfPh1Bj6hbaXmcvd1KVqWndHf7ySukioyKHVdLKfaleKZQjgYrFC3+\nk9M5UF8iyFNdxOHcn2vCBKWVc1I2pd6ZMR0eYCpW3Bl+UUc551rT4YjvRrmtgQDJa6pyO3YU8u8d\n4WmETh5BlAaqkEDHrICLy8G5Yep8lSuyYflQRyJlV2xhgVqOUJTgtQij9t35ogixJNN+XdeAvnZN\nYp/xoGGboGv2dQbh1AB6/hISTyoeoxiUiY8Nc+wJ43jxi7Zof2SnRGiGZO+DEU5xvGRXl2Ws30bG\nF6+Am3Fvx6BC8+k+3uh9EM9dWQfSBMnHdb3idchTHaECxrWgQ6YbLbIwFuEO5ZH79Vq0tBc5et4I\nGX9TavQlby9lMDPpsiWQoFMzvCBc3iZ+lZJau9LWocl+f/9BM5rtOdI0HmACQiXtU54IhGtfHCn8\navgoEX6YeYOtrL13mkeqZNMTwp9lDG2/ChB8jfBoeD2759DTTH3o0cL9Sf5OTcuPA3V6/lQNTJTO\nF17UEFBwpnizy/n8XdzKpjU+gDcJsRcp/WGYombRXjSxfOEcYeRGaNBkgmqcV6xbHB9voCeSyNZQ\n3NYbjLsDuHnQ5i0saD+Yo1ryDiGFJoetyr6nXA1l8onA/40QGdAL14rfQV6HmaKHRVYCsF5tQoxH\nG29OdGuI0EVOUfIt+T29zFbaLde+rv8aqiogYctNjvILupJVMCrUy3eB1cYL1r4cE8vDpaIrVw3S\nlXsgoXh2LK7PC3REaCHJDLS9oq0Nxu43MiAuaSZ6DZp0U5rHH4DcUGKGK4LxiKC1fKZB2YXk8CXg\n4JmMulWsBZyVc1Hs2STEooc5NEZRynFPyNx6sPwUKpBlwvxgPIz8ashYeArr7pgtazIlQCV8RsbB\no3WNCfSTrHDscYbNhNGSN15ujTXyZIxf0xmw1NxhW4VE0LbVbU4Q9muynFksh/f+O3sz79eTs2Wk\ncj94qweFDzzDSKfo+fYFxr35zCg/FefHqD9FPNrkArUiafPmFRWLGkm6SWycHTHW2dmOUxqBLDnS\nKOU4i53LrnwJtNlnnNbR9vCnTV3HZkrvTaGD1GJiRzC/es+XDUFHEb7YDM8JUKlRbU33uV+CnXcq\nE5Afnqcfch6xTfp4W24eBeAxeKZEXYdjLxisOYvQ03BbLnt/ao+HyqjiaVos86B9Z8guiTv7Y7vm\nU0QBEPyFWR0ehm2yrjUy2ZOjpN+dN8ptlOpi+8jkgisg6gYT2U8e1S2pPCrAtZwj51rEayRg6gp+\nfZ1+HBHDLTW++YMQshPGSEXZMzn40VO97CNjgrh8ovSvROZzPoujNet0XF4Xl+0pRfUzN08GGTzc\nCDNZWKvs7QQNI0+Jzy3TOqD5OoFWQbRf3ETptGJEjsxTG4xPlNBT393qN4TMLuz9Lu1DCUKN/auR\nkZ2FO6X5bGfE7IJXmo05JK9M+NQ17wS6A/rJrHFTFQG3i3U1xyCqWFjTpJJamaXa8Ap24WYvz6dc\n098Zr90dPEFqCDwe6hxyVvY5RfffPzDqQb5DMiiFBA0+l1lXQ6msvQO0/PjN67FDr+p4RuZxhV6p\nTCZm4lrQ47Q5/Asnv2QX7XT23yACOPXvT5VII5iJx66cZDW8PqcokaLa+pAtVqbgZDPxZD1C4NXw\nAoObbkqulKoJobs7EjZSIpKQqr5GCZ3QjgDDwPruhevdnzONX5uBvI19+JYqusyuR333F376uyvK\nn6F+d/zNdvSAV3gIz9JaPPEhjbKgsUOFhdyDoaXdydwVHrAB1SkIhNzpfNl62QU0h9m1rX0tPNdt\nUnlnjJPMTjVt7hS8vJhfgtk+39dFB37FS3rVDWUD/97MlcR8z6MEGzbLsGSRtQgzQXSzXL4ruX2E\n7F8oaVsrywznJGiEc+2zzA1QekJQuy5dxS2hvHftZoajaCqWhhrACvQAE5HTIr8etonzlt70MhBX\nR4L2Kdszs+cuKe7YCn41vp6yn+jkXCpOzLOekgT30vVB2cScqwhXUnoA4eD5oeMK/VvSG8OomIto\nmaCJiv0wLgJ7kJsprJEeL16mqTkMwmvay2FtiWlIWbKIs9hgg5RqP5ftklAYWiA/4wg9CMMoH2hp\nuZ1nni2cWWGynf2ne0XC1qDqennT2JyNAQtk9Jw0eXHvjVLarN4YgyFvFTr0C5rV9472azo3UE8A\ndbhgNUf94/74joOWhz9K0BX6hu6u9am3nZfHjzT8iT3pq3MtSlLDx/+vqR09j1sBXhBoyiyASoio\nhAQyBIlf137OHYUONIvyzXe1M6PgVDfdvFr6g7VVEpVZDeSgkN1SXdnbZwYBVLOYe3JTzPfiCNmw\nPL+c0DJ8OwN91pieUcftyhX8/4nraUP0jfbmoqYneAn2aizdgj+uYZDayM1DDIqG7HkWgfoTyOux\nFto6L/LvFuzFDe+ipcLHg/txvv/oK16fIF31ETqIDIKRU1LBbQAbPUwEZxC+TEnpkcr6oVT0hwHN\nJuTLW8ZHgsVNC5YQaLbTIU0uVZ2AYfXpD5jXx2DHxpFmqpwAA10PEvjjBwEXurS92XYW6Vlh3vag\nh8071PI4Y8h0dlx5dPI/VyJA5MsaecCPh9Wc3Mu9ju7CmJzmdnouyGW49lVc7T+BFgn8vY84W4Jy\n0EOJqxtbldn/b0RL9qNfkmndlxOOYUGpkoTDXOeKNtd7HyleHoQUnqsrJltt7n1TUWyBkUSvmr2e\nhIco9V0pfGLnQmBrcS8ESf7JoDfid3dd9xhfTYd7x95o4BpLRW9VbAnUv/qzO2Ql4PsXD4elhlqQ\nIX/zvEAslyulqRlaIojF5lfyR5gs5T3XDgy9J3wvtzGMB2e/OdhArVKDlyiGKVBCwObJBltJLdrm\nqQtoqvfdCn+V9EPh8P1tILiKhp/pxpNcMLi4F54Ss1mMT6eOjdsUUk2NgxCMXJ9DCe3Vzm8uyZL7\ngcN4jfAg3E1rqk3m/i6KHng7yyFwHWIWhDG1pdVdgHnmaVWwnYivlzpB/S7eNw4unSB3dd2BlnzG\nRb5PE2fCqQmV6WZPnzyEbQbON8IXydg2GwqhVl7d+KhVvB9u2DtRSUwccaSTmzQitYkii0ktito/\nOZn5ZAWREOagH6xk2jSJtB+raBOlZD/StDmobLXWmpcaSlaEkDEyTAMr+crVbeg3vAGSoSOK9IbG\nhEMMVUnbYc1PtZV+vY21I6ppYt5T/zHwORuaK4UahSEs+tc11E84gYKfibx4zaxbrR6PIWoRhFpx\nfygJGI82fQqpK8rIAfb84Z6eXjnfx8vNe3ePHTI9pkZghZ1vx44M7VPJerWd7U5zd1C45avIo7bJ\n7u6tesU5+cplrvIG+231DuhICa8DH9UF72c/JWk3FiHDqhpde5ScS3IcWx1hhrKBvi5FXoH10veQ\nlHicTS5ZPF03XuljrC096UTByid0LNhm3MEYNMhJHDAg//PphATDzK9kPRVEqWJNnUXtQxCtfaGv\nDDm9ZwguZj9gqtu4FYLLYUIYBSERRP0P3uA20WOHJw+chMy+nL/5NJ5IbO3bDpRrULtw20tfYeXd\nMEZRrVydMWKNjYU3WDHTREgJjguTG/o0uckR8jUjDqND8/aBClo3a38CpFmPcWL6ws4xn7mPX0eQ\ndm04/XpCC8K8rCxBby0gOx53dNfuWePoTZANSnjGGiUI5BxmFdAWSo6va4tcRBNNZMPM97o0kVhv\nEPnfc3/sGE1x3k8/zSHbDc8HaQOXTo9W3rmPsM1cLrN9t27Iox3uo8H8MKqn1YcA0ilt5LAjrSV+\ntUKxL0hO5/r4sVSAigD8X48thLABHsoJPxsvEF8LqbeF6ar28+m3HKCwEkXmuDsb2D9EH9UPETzk\noU7Zlu+cBilAsNow3MhIVGRoQMJ90wjs5tMHHN0coijGoZTA0lcU/s6NGNC2TOBj1w5bSDX8FKiM\nS07TxyW3rw6YTaoFIbD66Rq/NSP/31Z3DELdKtPR9xDQKSDKf8jWDeUMJczhi6nWPBQbN7UQtmrO\nLkeWuAHdvStParHRMDHlyl76hJKPEZy48fg9N9UdnO+Pd1Ald+lem+PCsHHf+OqbXStJyJ7sNQPS\njKJNQgifRKxMJxi0ijJ0y77hsBxInqwKBywtcfVKlXs5gwB5+HzKqctr1bzPf+oUVROtD4s7C8n8\nPRAVBiiazwsrGoCKpXRTQdmcPIWk5o/ljibexkeIJdZGOflQLAG79TkQP4VR589A9TEHqrbDA8Ow\niEvue5OjEfXk8v35rM5k036b2nWDRQjwgH6Ww3B4Lm4ynLAYQGTB96U9XWkAnWLiLp5m8zvFZdDi\nE+meA0JkE6eMo9xpSCwtthR9qC/ZN+oxyhOIxOtsuOB79uBllrVRyxq5F8q9Jv+a7IKcvLMc3+Sk\nZmbgOAgVLYMQnsj7C+GgRoA181qNGBLLADnDESGgJ/3VlMRVMiOvVQ+AWmMuns4aRjO7TJj0T4gj\nOtQxN5mRSOWygf4wDNFbjjzdk9Wrb+YtBxxP67a1DBY73E4f8rq4GAGOc+uA+vYPxN2cpzQMxn67\ntST3yTFSN0HU+TLzADeDsR9fli+VCAO40pjEmfvnmz8uX4ieAh1/bmsrpCB4hddDi4K7Pm6hCPVZ\nlNMu2yUJ2Gv7pSfim/c6uDmTOvuyKRHsEtHBss9V0SHiF7zsCw9jC1Gw1Z3hAWIEE9MWxlQFYCc/\nOJl2e+2sT7p7D6B+NL5udUm7nX8gB74q1PUFWPsGYpD2pu3lCBVsQcSipoVTozPzXTMu9GhiBbtD\nKMVzVgZKLQb85zYLEfk9esGkaaAa/IMlXBYyZ3KgxHNEQVVYLd/28z6Bgq4z92uZ+nUjAQQNhNbd\nihUSeLisI8jS+p0o5SqzysX2BhJTA73Dl1qC80tYYxi+Dgt6Ix5T5JgkBeZt5XKSBj+tWhDWKCDx\n6uUFw/ci6OktwfqL5KZVOMkEwPLWW0W3S4EwFRv/nqulclXjxaiEmI1qy2g3i4xu4ozAzfvuY4PX\n4TNsbHRGXKHnbUq3OX7WWl0FoO0CnTw7uzXYj3goIj+2ppauZVSQt3oGFMco07p5c7AG791rM2wx\n+pZL5s5qBaL9pScdRgmtmuslKlqootc7gQJ5OxR6mvoMhOnphhgyojQnOr+SJEtDMMD5rHlXoSgW\nUJGwt8q/XT7s+tAVwEfFZwcio0IPbQNDOOsdHChnWoWh82tTu2wWSgR7Kg3fahsm6lpYDnkid7j5\nkTGihYKRKRkvpg2Ws63TmPYjpdul3WC+b4ZOhk6v3C1IdjpjOJ5UG4l9tMkYVfoW7y024BquSO5/\nMPPdTM2nWYdjbgO42K4Zxv4zLj2NSkWZm3pkgJP8LOnt+bV9C5AceuFe2YEcYfHP2NnzCbPkW3DX\n7OB2UfViC3Mm7S4KKuGfnRC4dEAlRwcrCwYneuiP6uS0A1MNUvCnPn8WEs3qpVOweX2aJkYS5ur/\nR1bloUhVQUshGkVfjwbVCpNKA1Z9uzEmBMAoQ7XvphL37Gw4A6IF6IP0hE2sLueqpM8yW6YP/n2m\nThOWH112SQ7B6Cl1xkrSYRy2fRhCPLiOb/AIOrOXBfO7Htq4hRh8mLjn9tsBdxQiCauhjPtftHqA\nbnkLa4np5WOkVect6L/DVTK0V5YtCK3SVmMRX5+n/iH5KjTBdbJDG5zE1+cZIZUf1jHOQT1zGeYb\nPcdKviHtuX/dxA/zR96YYgE+6kvpWexwOMkvDnMeZrFWV3YA2Q4yzl1IMz7mxXAYg+xr1XhyQAHh\nbvAoPX1ZX/f/hT0d5tm7H0+hzJGpOMNmOb9uWoxbURr1oTe7Aub9LGHM7MeHGjRy0eeNA4l9a3ZY\nWaNVI8NHq1/gTMRD2P454oSx+FPyBOny6Sx3+WAXKWV4raTpFUBs/OkARVapcvZtqOP0JQyWm7PT\nCLXQurpYYnK+M5sJwh9q8N5Ymi5B7RVWKXSw3bTt5UpCMFF8w3wqLBnB20ai9FBNCmCWLZmqK1BW\nOT5Z9SWGsFad4wD/ykn7EphW/XOoLWY4gWTRReb8kUiyK4uYq3GdyedGWQMQubbwsw4Yf9XLQOCA\nveyvPmR0nXWIDyie/P517DyAPPR3QSsQaXWL6OwedlZe9/pJZvpyVuCkMvohDO0OiZBnKhw8c6g7\nQDxVJpr+PzuscPWWNvWsRleF9CtP6o3lVCPYofb5eni3/gew6UuMOOPdq96vjfol+ipMOitig/EK\n5KSSJc4ignVV1rpPdS8jKt1uRzdiIG04lIgKV/iTrGxulwFTYWn0YXZ70j00M7akJBpgtHYtEwg7\ntuFwF87SDt98jOPD/WHKwoeleWTKwDzN8dUG6rIIjciM7ttKAupuKB8zcngy2+VEd8SJsoOuiVXv\nI1jEkJzWfyF9h+BgpXXoFGfSUjm4PqBwqBTsya3TbfnxMusFwVAmhcgkODyoaBE2aPevUBLTPEyg\noXiZdFn96TTFBTSKxfbvfoWmBfJLQG+IUMH6XUArLaDvPsOewnpCrh+xOPs2VUJvRJlbOoQA8hhc\nBYFw9C/vaE8JPImPCF8Mcml3atuzrH8J+M55leKZ+Ahyde17lDJYmLaTtLVQgqkyaZyHgYJabqrL\nfvxMvqW5F5ysEsk4uLDBFDd26mKkWfaYPU1SQDCVe5TX6ZCrMoOF7QT3xo/dGRKOrgxhF80rEBSA\npbHEX09kRVpK/s7dJePfIDBOH4wslJSyr+cpQWARs1LDsRdJqfBnbx5MEQ4E2qk0F1V6P0Uu3APK\nPs8KsBhcdUXgUqbGbsEQmLHNmMsW9PItMgYMqBKVjCWjmnu7XFM+2WPGuA22GFgbq/HHjTvb4+a/\nhNHFvP4EGDou4Pq063a7EtIFFh0VzxeE8It65f8GizD4Z/YaE5NBdVql7NOdDECr3l5vqCI3HnNC\nrd00HANISl5oyA2MuYTQR+GQaXrKUzZ0cDbvQZ7P2epot1a+MCmRzUKtgRQlP3GEAOvl/z6jyNGl\n0i9gClFCTubmketbUNA8oLzc5tOCpMdeyfZX7wq1Mj84m63g4WECc1S400lGBZhiUvaRIgsEnvQo\n0/oWeneHemIMitJgnp4Mf5PvMfKmyud8ED+o05VrGt2n1P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protect end_protected\n", "num_lines": 1219}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\ngazeSTBrENHvbt5mZLx18dRtoyW+Km4t51uVxxH7ZGNnmTTcoKqZyFpOrZ3w8kS9aFoiQlh5unYf\nVMD36zgB+w==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nJaIcYFxN5pqUbzepnqrpmFHdFIYWDYoimv/QCWvvIMmet78lyyCu7OmAbUWaZA7w0zL3MGnfxCUN\nn3vQGmg/2D1qvx/q2zy23sfhZfE87aSbXcNL67XF+GYu6OLKGGPH8rnW6exQAoemSF54SZgfsVR+\nZQSjSgAEtaKfNJS48WA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfa+581mCG4lxTJxvsYAMI+Y0/3DEJVi5IASCLU/HkCRmXkai01uuifj6HPVqiueReLeiWI0bzNp5\nJVlbpO/kKqg9MkQMgg1uBw2FFsg7gfVjpDJV9TVBp9Tm4YsSrWm6yWxzb6uMaHsxRa5Y+E4WUKp7\nkFXmUM1qfaMPGyGNdQg20KAvKFwwN0302/mi6GDcLvLNvvne93tcew0yQIxg/gqJlcURIlak/g5o\ntVj030iWkuj/kKp5guYfq3gEFKVEr4SV1BC/f5KX961SkhTxXGKLNLPd//Gm7akdx9a4SnpGY1Jj\ndKETnZJbnXtrvqcZUh2N1o7nl+YTs0mjObgM4A==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nQPlIuDrSSApp/O5dvtKOql3r2+lVEipJtAA3M9T5a18Cd2E2LeOe6u54LQRqvqSgFUElg4Mk3hH/\nGPHlO6wLGkc68a2QHrQWBA8YylrYUj+OZbum9kUQm5R3TPU5Wchw/mhpqWpgPlWvyK/cO9FxrB5n\nHD5ZuDk7iJeShjEmKewIRdMZqkkvQahMZk1eJ8aT2jahULqIomSMODM8v16Cxv6S3q0ohUtT2DVH\nwOkY6nsqo58T1MDDOffgorFUWVqkQwGQ/maDu/KENCo/JCJZOAmODbmBfBAsXvg7bqGZKB9VPp6h\nTMfEboGK0PjL8yhECxqeqwtqHk+eixHOqSANVQ==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nb4dHNcYwRRv3ODYilIe7aZan8VP5sGFpEcM4Sk9B84EsHlTRadyHodV0BfhfsPQB7kezG88HW5h6\nWNkuMny+KpZj54uRmnCQmrVIyZTZC+1+fpR1i46q7pc1ZFH0ByfdNqY/66Ew72bJ3bqt98VUJ+b1\nKDNSnYmqrLKj6TtcYAc=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUFVtDvwzUgfeTJK5RQPCu5bEQXOVNdg/Ctt3LMq1WwNKEczcihJ2sl86P3NdRo0ERI8ueQtux6aa\neHgbxrha+qncx9ha9CjfRUqPzzsOn3Y7i1ixq84ynt9jVyhbj9UUv8UyPbi4K5iayWqESAXrtTyL\n4izB0qPIWl4//8zsVriy5QoAxHYuCOVTFT74KhP0GfBhGq8gl2pE4gyETTs/8CEabnJ3ERkaoy22\nqOEPUjVTsxS8vgRq8tS716SKeECQKpsy4XCSTfx1d1knluz73QztnOOUXoIisTy9nHoSAbC1cRDx\n3ja7kCl2MkDQsfmBWkq0ozzVuY4qo/oIb33DVw==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nYC06/kx9685ntAX7i3acgvLk/EwgC2VW4WVhE+P9S0QST/y6VSJ0oBWMmzsdOs5O1+nblcA3DkpX\niLfXgmvlzh61Du6yn0zIyDDTLrMYWINvRbXV5FG9pLM3G/U+6fTbBV97iUYMHPWk0A2DdkXIWMP3\nmcLuMBQc2y0dm038tnqa7fuMeTcvxPhQ4wTWwHXvp54ejwq4bTAhNgyJeExmEzOvR+zWXm2VgpLp\nqcMFWAA6nlUIG5ZF4M15/u9UyutQPOLlX5+QPwfoMVi/kyC+JK5AUrviJ1QU+rzwvU3tw3rXqAgE\nsMTi8fHZ/Nt42HIXty0cXb5zEQDuP6pPBNW6XA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nHg7KeQWoQfRjpmFIAWAFbtestpXMcHBDYTZuLUSbL+kKuRGBZWT+FXknqinVcx0pJ+q5acUTBtyX\n7dcJkS4qdpYpoaBETZeL/wcOfYFz/CcO2z0+LWoGRDW3DzXn1oRWWZyJwgJkigyMIHPH5qxsjDO6\nJPKj81fkKJMHi/vC0LbmZMiKSmWL7sQNeQyH9Dn6VLxtXovGL9yVh0SoMlG0/v81wA1TX/bXmqKJ\neUvzBU070O5AHkn3Z9WRSK5S2L7x/k+ltWDFho5jtXYcevcbA/14blQqT6/9PetAyFmzvbIS+6Sy\ncJ54zu+VswtKtSOWyzlOnfx1Jgt9q/yLpCG10A==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nn/U5obQaKe7e57D8Mwxo0WeDlQ4fxz4sWCrMViskbh2tk4bDpeUf1ENBUputMkID5xX5gqlPeFYH\n/lod/5hBiFEecXymoK17ADl/jmNo1MjfVQ/nqN6xaJWL8VqmPoJ2XUvVt/nh5gTeI6QOH0BkigMy\npLFieK53VJ/5XRJXmLUeyAKMuQYF3FZPQdvCn1NDG/xTrxv61UqQKbL35Q6DuG8ZqHIJKSJFVln1\nchCHgEOHDKo7nJ9MCjYRgwBWPGvr+w4IgHNPDhatfWTGz3wjSXmjYynT7/3ZWqR/d7FCLN+lZ/ht\nr87GH/juUmy47PmZd6QhKuuc19/j3eDrwcHg8g==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25472)\n`pragma protect data_block\nrVD/wL4DHCsEfzFEf1VoQTKecFocJw604Tk0NgO7M3ODm6t/6/biD0QPzz/Fzy1UxKBEqQ8Nxpt0\nkd5dp5nyCwOVRYlAXNcBHWyWuF3ImZ0fp1y2c4napTVULuw+XU5nSbEmfo3EFsLjHWHYarc33XNE\neccwGpgfFccdUa90fp+q6imfJMIuCWHWowLNMDGdb8ZqNKZUIE8ob6W2adzfUxW6BcwKDMhYtONy\nphGaaPcir/7ub5AXgPuxZ+H/dTq9wgn1aTqOJAp1ucnPzVq3IUtg1OC2yU2vi0qMrGvEVqZa5al3\nShGeBdw/lrrv+XpB0FfkT2KARuuSvzee9a4oDMMvB9rD6SluK40ECZ1+yy9NV8VPy1Z2E7wjjpHJ\nomuIJmTDG6P4NMgl9qjKSn4GSHvEJtg8Hs/pMVAdAds6SMK+O9p7rBsB9TJ+Jfe+EKBicHLzhqUf\nYcNZCfyCtkGAWU7HcdbTu9BHbBM7GuhixBjPG1gZBzSE0WtB6MGt0YXj5LC9B2B4gUc+LuNxNcc9\nUKE7AQ6OnNorwxgTIT1j4f2lTdDpN7naMjcc0dFrzhwLEt7EYhpH25Cb1lTtbt3ny3KVcWNrvcLk\nv09yJ3wThnjJnQl+GUiERUgWu8ROGl8TiZbUBs5yecOS/BsLolr6ykQh3uUot6ZrpLggo7e2zZy4\n3svfbA7sVv+IfBOnba21zodL6jR5Io/8RZ9dAtTSxEkwNKn6woPbXr0vzkNOcXmNshPgXMNfn7kP\nhh71P3gVjrM1Z4XR2k5FHBKIFP7xvG46B9zLPPSpe9cKzJ4DSqgt0aNr031h/E4RKIrUZmmfW0JP\nOP5eFKLhkwM5x+n5EaEHSfUgoGX++y4UkfnBJWjFbVIWdkTMzBCFia7/hFiP4k87QX08uk84BfEf\nsgKGgULddxVYXIDV7mrWaO9Cy6yLEYGh6+7ZOBVM7Zy6cqp9LP7Kc0FPdoy8x9BVG6p/reTiiw1v\nNn3v32uEnt3XP6T+LoaKu/6mrF1npJimdRr7SstYkFy0LoyzKWhUHUz/VQ3iwILTJ0JnGP770FqV\nmvyHmvHBk6MZTTlNhtcVSTTwbM0lw0LvHbExAUCD9Laa09kQXtQstGMFqjckEvN2jqCALunjsEkp\nBQy8rtux02oSB0O2baktMwI571Rh+4HmnparL2+x49hG7tthybchylTgZbFDHKBCvdQBZkzVuo3Q\nj7Y3oKUrm2bmuJSbom1St7TbGFQq8d0b0kTXHL3I2ohjaio0dcvYDfVg+yWz93shEUO3Jy4PUuCC\nxhV2WTmsBi64HHIJgemiKEoZqO3e18N4F8cdUteag8hQdvF+6ZlNnZ/ms6TH575Di4UiksGkL0FR\n3sJm4AQ9V6tp6J/S+c+1flwE89qo+Xsg1/cG+L8vSsQxqyAk/ovRsYwYHiS7Yy4/606czKjJjQLN\n/Od4Z/RzSCDTe9OkRgKnHt5zK3yQjI9keM6uYHLPJND8bpBNdWrqOdAkXjDHjM3I9U6L2JJqeXVK\njIP4ArCrIq1ZHjpvCnFaxB+/+BBdYcUPUm1A5us5vUT7+x9nSm5EoMOVcMVFqrdJ27v3WAGi6+E4\nKO2C+XigT9fiGzmzXlKKtsTeS9pPq+XJ+3ohj5rZIoPhbrKxWjCzmpLqwAJ0gNd1WFfrHgE2LOe/\nH0ryLItmrp8oOSGEdzqkIi3IjIWzEJsFuNK57sg85CLkLBrD/2GAE829x/TXqmIJN9TXeNtV2gKP\nzoR4NFQendQZY0s22N8NsE4Y00GMNZhaQdHbxhimdXjmLk0d7qaq06rLRbHcsoP5Sq1QJlF2K1qR\nCGKoiuDSQoQ4Ys7EOeerLV2n/FRB2yqoN8xeHjway1HTDoAPAet9wYutlxLTBUccGt+zU65u6OaV\ns1H2YlNFqtwE716Dp39IzGvOD4w6IjA/vBYiXj/dOVHbBBfQr0u5i5m07Mu8+ql9fOGoJP2wqBln\neGByChXLhb4uLoe6Bht9vwf98nzSbRmiaYLyALBXHgZKs5L5Udkanozr2NM301M2pzP8QIPa2aQb\n64OnBA4icxCxWwz320VkF/K5BM1ObCLOipn/07v1naPYJx/9aT/ZVupp+QL9cBnPp8LZtldMFsxi\nZojdTH/u0pOw8jx+SH84VqjOEloFoTxTXkAMHKRulU7yj7ZmWlEviMhxT+f63SOqtMW6bd8ndq86\nbFiDcjGNkZC4YUerGzbOM6M+me6Qe5RcwL5VJARilQoyPMlPtvzSwMzUJQyUmabaCEispxMMZ3QX\ndNb4c+W7FDY4fxsytOmuPwhCZS3ytA1vCB92ukP2KVeOien0DKc4mIwjdBllzW9+QN+GNSzRe5LN\n/YyvlmAWUmlNSB8smtrpmB84JVKlWaXOOrpOLxRHtFaYpnmpmXJcNveKAB4LMvGTHJdEDlR6LZ5n\nCgWcU34eHvwxJ0N7D9kxlxL15EDsPFjxeT/vykJmOvcwVPmia0M2nwFaolKZW5cm0pZvf3bzkkBt\nkxFF4vDu3VKJBPN1qqR6ngJ8w5cII2VcSG+TZBxeAg/XH5mW1JuetQkNdLK940Rk85qvx9Z5tYFu\nFKrDM/P9zlRri+ggEpi73JzEUnuwXVzjIe4bn+BCJz+SYBKbr3OlasPo2GXinaCm5ZjGwKSqBbnw\nJNQvpJstSIPLThwNEK3IT7qyWtVrGoCDNiYO4H+x3es6P4VqLqh4r/0++vkRSTM4Ov8V4lO1aK+/\na/Wba1G4sbX+xCKKd66y0Rr3rr77pOo7IC0W9booS++rNRLvt64SbPyun/PqLmZi9rwotRAJRA4k\n7TXOcgtq4Ki6pKRKU7oKP5pQXRmGEVr/qGRqcX/IFcGkvR76WQxcFoASm0Yj/3Xu7bvEHJDX02tK\n4cAJxbC+4JkeI2Yc4e6V27wCtFNv8VAnJEAIJxM8w8Y+uK3Wdth00+HnMr/teyh9PAFI23BCDQ8k\nP3/TGEk+2X9AelM3jnJ1cx55xK7Y/PsWkiPKyUozhHYOyR4SaETBIxAtZ3ttpyHm7JPgipayDsI8\n7gYw9SePFZFjYEZhCtfrBAzTmKhxEJ4BYA2Yq5/1Djk3dqr1Y7XDyyIaLjVim9C05XBvKk/3JjmK\no/4wBHIRPWEui8ORGTOUvziQUj+FDTHjthpKosRq4PYd0gugZGbbhdlEj9IDDCDNxkVM9Xyk3ytf\nEqvvgLtYOih3D2Pq4LqFEqHahfAKS8ugstEsKmEWOeBnP50FSppoksT7QdPuZ9PWlAatvnkJv763\n5BXALS8jMNlPIJvelWHd2qCx6OhCgLmUmRPNd7LCMMydqv2c9uA7voFh6jp9JGAvPu53dzjWz83r\ncFeBSw11OeeiKRsJaiHddsq8L7nMEeMcZshhvcS5y26j+2tp1zr6sVBFicGgokYH1CKTQFIpiTib\nXPL5vAVDlvFDdaC5VNkFNCs76Bou5yWCTAwG2DcN88BLMV7QS7M/iGZSbCw8JV01LKDRqeheVsxP\njaLYS5XkKHDpYtsCzcVvCn6u+nDFLOLhz20cYL4vxwmt1pMKikYG15ONmScVDm5/xQBKe7nWsOKz\nSN1w6zj36KQ/C80gFY0GXtFZkG2CqAMt0M3uDfWx3VKuW6ObJNUb3R0TpZri4OwLbrrUpL5UT8yt\nITdov+Beft7qZpxoMu9KLHhncLx4TJH0gBzyTVfAPg4ljeaBsL7cmVfDmZ1PxNBQWN2/Ms5XhA42\nF3BDbS8YdOU8JUxHPgD9tCaXHqmt/co4uhm7Qtmm+DeDE3O6ljX5zbblXhS0345LHi4MFfhCkb81\nJ5XdY0hze86Ye/grd4KM1+hLV49/08mXyM5oQSWFRPGDY5ivO4n9anEwslLWZ2OKFvXtW0ZjW0tT\nRXEjOIOyE8jyr36AQDMI1LnOl15xPMnKxb/u3VpCatxnNlgTk/jzmFAD36PDOdzIPJr58KDGvKFS\nG18BSpcfrx+8cPWzVMM9M9Xk88D3Mxb+hWAv6UC/efp1x3+Hvihd9zDuubo8/FLjegZC0fa3een9\ndOTgEIsRfcfWWWdtQEDcPKuUn7WhoHt0SvpvO5dTcLaAmCPwcROmaH0teqy1XjMnZYp+sKIWZe7h\naa/hTWP68T4UHeFB8IDD9md4MZDlB/L2ac5XlcVY7UmN/GXG3pc7Gbc6uN0CzGUQcYa/v04G+11h\nT8nRzZQJdZlq0lH1U8k7gR7YudvLKtUfLHu1xmyJshSEKbRWUUdGRnwfJUm+3jGXNSoyoDu4eVa0\nmvh2E9+h8tpc6Hdxbe0/dRAb6sSYseeMuPA07z/+SsPa5oJMBS4zBtxgDX7xBkPmnOmMnJAKzWdI\n2/zXRzhP8OaEODsQLJm6++pIgkkHCqOGr6GeXrHTdMP3idL7UslwV4Lad1r2Y9+61kW7fcGSJ1KP\nG39vh0sAfFWWeb9d5TVQgwz+KIoe74xDJPYPPSkVl5kx3YFKk6vty4CYAB+5DVSd9bLaBnJ4/6l1\nJ76KqFbRsqIPDPWm7OcGTLW7JIMmU/Ofpv4nidkb4LPNVbPMfVS+Z32QG6FXVhOpIqgiKe8BfVka\nxk1jg5/fA0RQ/P5VlZhWUzEHywD2+khTh9xwSLldzJ30El7YZ++yRrsgkGW93hRzZdx/r1YMGGS/\nQBmRuRM3FKMkS0svshNKaNg8DySBg+q2X6Ky9IjA3dznU49GnthwMKhx58ThDxQ+szVA0MrLc0o9\n+rEmk+wXvMx1gpwkFLsJocOcBtoyq3atxI33E/X4g0N1mdf0f7XCxqKCPRyQfjfDQQv222kEzPfK\no/j6pJzL/bq2QCtQD62ViO655dAFs1zzuPSuwrN0eWO5sKLw4bi9ekjxE61AGmPACWDjdfaFWJ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dNrJi4eDjTX7egADR1lPi7IHJnaNzULLyzuO3tY20xdNoS1WZ9Cd6zJ3177q62zFD9IqW5Lu\nqwbBMBn9Srz8L15/PmeO818lgnRA+Obqkway5NlS5ktpFQ+pamj3jyYU+gi61IJh4yOrdmG+0YNr\nYFfUfUywA+Vb0DyVlm6VO+PiHnezjyvHEOcYEa8umdPJ9zJG7DIv0F2B2RqLChYKcamD2eAeDTbH\nfV0/YaWwv1GhQ+Ao8z4mbGlH71ah+UI4VMNU5k94werdUcmCZDFEnscd9SO86QRSF05j+ffi1CCi\nv+ySBxYK9APjuLQjNVrNKkjo3sgO/wtZFTimlVD9eKKZO3oJ+8ImII4d0IrCjHSBC0BNLtUvbme9\nmUJX8cvZmqs02dF+ATX/gcguP3DCUJDAUSvbg94oU5zILWF5KshRjRmpg3/63m3Mqua565kXaXW0\nqSB075zLeZeUTxd874xUJdwhzrCH1TkgjtNBULzc+e1zgGneUDlKpF7+GM3E4g2yPDntlKDSV4tq\nZg/J9yLjn1WZ+g3OXJp3EuqNpixt4tWc7g4zpFD+6PkEQHyikmzegOPhSHkmz2B78XcqHnVlVRT6\nu+h8+OajG4S+2zUQ2+y9ii2QR22KHBEnoriSV0FkkgCt9aEB2YKRRKtPBMXtQpeLYxm70Z3gLSUA\nW29k0A/vnaVEOuEOlY/jqfFKbKb1K4q9aVjX+++COWTPhV5kly9w8ujzb69MbaQWfX7p+PvJCGyF\nTwCS/7D3fUAjuzGmkdfDhZccW80v40olYz+LXAUl7tUuByKyy15G+0BKB5YEi6hGFv6lEz3GSGxe\n8/uUmYAPkJ1u1STOydIjaaYXqD83ZO/ZOVEKqhVutfVl2hSHLzYw6/gUFpFcMwZWXX5eOGNLl2/T\nFF4MzK6u9+0KXGdOAvATi0btUYD6QYMM1f5b1kBWZjJcC1//GBYKhkVUuwduwTVT6aj/2wzH5gz7\nQ8qEmTw4zYRBtJXQgOs/voolLCe3EfZEyqm2uQ/r1PchYuV1+d7io3uQFszexWSuf/eYepqWnq/v\nz2Gz7GegP8v46bRpzZKV61eoGO59seLhOTjvp7L/gdDO8xjlrHxYtOpMrNrj06dtbzUUacmPBceR\nd/N3VW3ovm04JbtMLrbwXdgY4PIFgeC5ldjlU2bnibhXKkE2/MjYx8B5HonlmJU3YGnjfnMzuVhi\nsfVEj1uJaRWKiNw0ZAITwD1bMfhDZShTe0WQqn6LrI1/UH5oUhqovpbWw70bz+ENp+D4TDwsZS0s\nSpmlHT0fP8DbRP044UI6dumqUBh6K1XNWgERFQD7UXK8EUV+Idp/rnr1NbNDOlaD0+dhG+p4Id+F\niQe8It9F8OXKRtsV/b7VJ70PE+RuIgrdPemrpm67UkBWnBSKixKvX9kJd4ecWPpr0hHeiPZFRA8U\nD+ACqk7FL3Q4yr05PC//O0H2Vym+cbqKruXPHgWLbH9CI9zSMFo/j+Fq7Aq+EDCG58e6G9X+bmFP\nH/5XNkvZhbeggLK+WQr8H9GQIZLZMQCboRvhX9u+eUuhUUvRU9gwFbtDrSz8K8kJBMzb8blG5UwM\nC2N2y41I2+paR+I2m5hEXkKM9tXl7VclIQIsYF6NoNH3ncc1x4HOPwxgUUR36L2amu/bzBn8MXVJ\nftczkKFdZiYMB5xIcDLovipakJFSH/w2xu6WVXWMOiA5kvgUvu+hbbVi6sHkQNFHYKIAjobH3q+3\nDrc09phW+ROYO+aTcQbKrIjZd71OhsV5rzwZ2JQ7ki7NSzGWrG6x8vZodBDEMCl2MIjkqJ+PHIov\ngo1cRx+oS/5Dae9iXLZjx04CKFNUWUSPyHHrfbNDyOPrdvGCTFr/67j/rGj1J8vVNCxtLm1bEQpc\nSIhvaUaLDRXNEjLHerJ79+3XQHd7IqCcBLemBhPmU+/fiAWJozadBEb+HGZqlMPDNzwkut2l43PB\n24M9Sj7odg/0kwUb+nkDDFoZdwlMwRh+gKg8uvy1/fK1j0sJaMju2Livjx2dKdE1F0GLrtHWI04A\nauTXE9SM5DeEDogTpQeQZPSjlINIteGYpH+oQKh9ZNsv/7z+zVFuvjSsLxXZy0AmwKADhVa+Xh1q\nPOrIzFEtf3FEPdGmEyelpCcZbjgkSf1KggQSt4O4YkgNwswY8tEBLIDAXDQExIjCYv/AIeVtzzzl\n+gKWU0UQjKYMVQCWH9zUlHQz8rQcLCB8EgUlMKDsQVoRJbvQR365CNfAX3W8rMVy4nTztqh7zU8Y\npTMGjwCCnBVie6sRytRY79AmqVpgvBPcuQdAMszg+wqIOS/YOXfWuVWaAHwDpxw6UNFMhWcFKSOH\n05VPD72EbnrzamjHK7JEkayKLgR8VVQaXYvT1jVmwbJ6/f9Gfy8CZaZuJJhKPAbeo8mMHuGWa9HL\nA8hVOZll51JKNbAGr5wPKjPHhfBCcWJqs7VIW00Fms/7xNFGllj/SZtUXSzpO/+2FCnmtjO36lw7\nuBLmHLf7CfjRZYUEgQLNVQA07zta/IkjSnwAojzCOOGiriJKJh6Xxrq7QrpLKKMpwb75V+Bf7UIq\nXCrPo45BCxCLgZ/361L4yE1xbmngU707NlaRF24SuFTe7juhvITEAy3wY6U7A7XsGp1GhBBNaYzx\n63YNFYggmHPw2SyXoCLq+pVuz+tvr1PMqnV3zzb1XvR/5Y4Tsp3bIfi00nNB+tv7WU3mCiKl+KDn\nWulilfdt2qcMkdt7dtmcPpClSu9KfkwSQANc0ehkxDHMf0CT2X361QRvY1BiIqs5wfHnQurPZVvW\nIHViiyTAS3AZ/VOpqQJ9UeATGNz/qAOHlu4l0AAE6xdtAPmQ/ccoAbLOCtCJRlTP4bk+mK/UXsj4\nG5Fs43hzF3JxJ4LR9C2FvUvkNnM4hsoGeWg5/PI3h1hXU7vUZJWEgYReDK1L7mkquUjzkWOBvs/Z\ndZTkag4LuLtNIBkAuT8lMHzT6gfGfl8FX5+8nSILKBx072cjdYwUpvNqyRE2Z/RnolUwJalgqWFb\njwYgWT1LgrAf9zDNpkiBuskNgatldY/dyAyHZ8aoMboKqqPiZMkqJKavv+FSK4leOWqG8/2gaZke\nxNn4gg7BPj+xor4DbD81mH/cZ6YSEZbXxAo5ynx3BpP6mXWX3Q9BVYMbSPDKd5LP/sL+FLO4lhXe\nHGsXA3ZwJficyeFbwqcUF4WXXjftNC8xtQgoYUdMYTmtiO2Wko7wUYf5VzXvf3iAJh6h+ii7bnNk\nQD8LnpXLyWkBAxCxXLS439nKagcl9eGoV9S59YSrP18BCUxHteCTtVutmEwT40IhND3eY4xiK2gJ\n1mJGaWYTHkCq+0qg0+pobyEVhuMvAbp+hax+P5gFIK4xkXaUrJY/rnaXTMMpPlU/ew3xGKHRD6Rn\naz43KtCgy0a0LgYTDuQkkWgfEbeC3Qc3rv1tAYrQoiVSwPN1Ppmyb500ZaLxhfGyslQtV6Cj8IKf\ncHcbEG1SU/vgXR+I/iJitzfGYck2dBP6Hc9bkQiJgCaJyzVJKT2nLPrMra+TZpxLjAf8bfzTaIR7\nyBzAM1+ONLzI4NZwoabqZphQMBeLgkvRZ4iutHq9/65XXwPhJ9rawATImQizNXIWZ/Xc/dBdeYci\ncXlh4cNi9lXr86kv42EtzQO8wiXxvpJNllzagqcYzoDS/2+v9gDA81y/sHczLBSXich8fCL9sHnk\n5HEPy+MWeoxHTXzk4NVKhoDg310u7DNHN/iqdC9jowVF45NxlX5xEGTagsxET2kbWxiMiA+l/seJ\n6hm9WQ5oT/E2yZHcl+/+7WtuGZN65uRALxVa5/5f/aiPVjAc+nbCopYK6mlCZQ1fe6EPe8V6UAwu\nmK6Uxk5h9aHjCoxyl5jtUOUpA3Z2E0IY5HjWDUmo2bW13KxWLnEpTdxtgduawTSy7y1brrIDV9Ou\nthZNeteFd9ZEFakDiqLVxSlFcVeSaMOlBtkUpVqZgEIwE4RUExVbKFs+H5eWDhOO8OZe9cSg9acu\nYYhr68IKC7t9VpDYX5OOgNcj2vxcsNVFwYRGOiq0HeDo2RS36LOmkhoHKBwolhA0gBjZd70RygkT\ne+ujgmuAfYLnTYLZ2nHTE2bGOp0zk1L9xPoBXxIvdp+k5T53k9MUi7R5IRINuNmzr5bC5Qfp1foo\nokZfB1U6tHv1oEOoThzFFHi5MhTQsKEn/ks7GCTg2bAFKYJNuuE7GjA61F1+6Pfp7NPIjUwbK7bN\nTlw/pFPKgsPwRciluwLrUwG/LcAxhFFcg+lpOR6KrBVha2FXaGyrxGufH4oJo5wlwekT/MUb5pmW\nZJgQFHqzjiiXpwW275Qpn8xplJiwEhsVfRYaQIzC5HzBQtBD0Z5xnctY48i77DbgIyL0hIwb/9pW\nQhRC7/N0v7qdT27P0pl+jumTiuNVZta8YTC7G0xouZu+vXxOvE/NO0wbDODHNploJXlfweCV1oyP\nI1N1H5/jXLW0L2eiuCupnTrqSGPbGlL5ABfwLqaZsT5pSY34+77u60VZWbsIexLeWmMfjCRnwqdW\nlazA/KsFkNe9O1U2719btMuPKm+/4TvoYxbpn1POEQsMuuwf9Pu5ujFjLAJq7KtmxM83P+hUfwbr\nG2G0JYCgS4d2fxUgAQiic7SD6J+PBgVi9fHwO7v/rbC/r7wgRKqfvQmlWmB1raUV5e7qFyPgMl91\nDb8DOYHV7Rpd6qEz88xkcQTRT4wIs2PzJ7zBQmRJXb+XbWW88jQEJVpOwGMGWqG33QS7T/CszEl2\n8G/UzSnCH9i0fIkX5bB8hX1jdnr9OkaiXmXu43+ixOyLIbZDRN2aRFEU4bczxAuR5mDXA3WX1DWF\n1LMX3PBCA3DIdqjhKv1+o7MLR+9Hree79XghCuZgtetNgzE+BgpYsP/L+wq4AzZceo2gx/0A3Ad2\nJHE71pWJ/OStHuQFDk7oCr02NKijAhZT/5I73DLzWpVMrpPwG0706DOFl5+bko+2xhL+vKkL4s9G\n43sC21ZYXx40qplG+nB4fhtMI7Lx12xMc6QgJO/DJGJbPIp5sPUk5yZyzFSb6vxhQcGKzF0jRKk2\nblj8QeOpzwmj2vNpKnM80a3UxpPiqfN7qiNdQV/oGE4utr7yunmZfyhLjo/uE0vfzSjmvB87f5Xq\nlSz9CuGzxhmVUGtT60TctfVAGIWcvXELEXV9HRvbEvzJ/XxlarWtZBkumvhDxv+H3/qxTBYBB3VL\nEE7GwzXzsRqrfwK5sZNZBrnzd+XIfp91Cnc96mK+7oU/+LV+A6NtqwEEdxNXA9EK6BlqTOYrfmNU\nUAyIzodRgP4dyJKUwF0WnCNbwi+WgWfKxeD6J6U5fRGoUSwKaIxOmNvBMgeSQ2eA+671h0YMe4NP\nqggDfVx9cXGcpytVWFntnxs6aQPg4qSpVOZkJHP2/oUPTaeW/+Hvyja+m3VTiajRHS+lfWABSwkq\n7pRAbCjzIbKeOM6sY4W63453Ewo296f3xh5ZY65u0scQgUyXtB48n3211e4tIIKNN/AwXo08/bhL\n8gThWAG9WhH2kzkFX3M7AZm47XgemDZnxChGhAXlif7chETEzzJtM8Ytn6zgg/ph9GV3i/Z6aun0\nmrCG0LMtrg4CJo+4mHmQUG27Gtd/PIm9eqWdt4ywk02K4gGJ67YvXnm+EhJHkApngBbKhp+I52ee\nZtUw0Li4xW6bs49i2dOUAjx86jsKeU7uJiWkirUvQ+aK37MPYTPcfME8nYmJNlOwZWzbVKfm00HL\nk0qmK6iDSmL/DSdx9VnPtGsNRFDgI1hAkSsqoGO2mCxxCyfAc48cWKxErLRoVWoO8VSl834ogKht\noeVK58ezIAHphOWtGVwz6GZwBiIy//1koxIMb3oR/qvXYhyucGPrvWOoGAHfpFsQPqwrb+rEKn03\nScU9PlrRZFhZOONC3GwM8Pssp2AOJT6RI+RXmNsMX2QRDtwDnC4vmHwen9MePiN3F/jppJhwA8RW\n/Rm1C2FX8ODUUj/mJU2oyh2u1HV75vH1uvUNFzDmB27k9IBiPpU0jjvuSXAJRPkzve4rYPV9xTL8\nfvi3Vtkjj6ahvzGVcsAVgAX4iWHLuRCHlAmMaXvPjURqSCU6XRgDTx1ia0CoytuL3y2O+KSUqBEK\nUqmtax5Wn+VzUtROS462rJdrp3YARn//1bxpXyg/j1/juWv0yJPQgUYcU3d3JuYIp8Q8jjoVodhn\nP1QPd79DXNB/Pwd711DNxOb0sk8yEPXHXc1Xcnnuz7a1WrYqeU+Ww/PpVga/3biOfdSOi339aWgB\nfndekDI0qMl0s9pWT+9CPjkyL0nbVWARb/uVgNpjHNmro4Nbj0HpFXKX9fwsBDeBmD2lgBrmbKj6\nbdRKGMZutn+k3xVU2uNfdFPeVpbC5lod/2xvC8Ful+0xSpTdyyvsUgfPwPgPtL/SOrLFT0nutxzZ\nkz8gjdMQ4dFDPg5YoKfi+ICV/qlSloXDse3ooI5N1ZuDqcKdcXjzm46vsfHbCZCzGxIgo+W3tT29\nAKYT0/xSqJTbX1kkMmCMOiQqCfGf29k8J1SaP1lrOC5l1AA8nrKBjm3OvciG8hf+5r02GNnwBp8Z\nZDCjx/Atsr+9LAHvecc6HiHJPuNCINcP5TLiSfF0jgcdsQm3869+RWCQUX5yLZWiVCpuQxFzPLPm\n9mjy+MRdZRDrfpkdPkHapHE3kPmPVWQXDTnhLYOgE4vdcljB4tWrpeCNm+JgRQ03G+v+wSPN9TYb\nrwX2GUhJoR/ax47EWPbYauv7LNZ2bJGfOb9s/o8KYw68eXkgj+FDljZzzP0dKUQqYjNgIw2TGCxY\ngcJ7cxv8BTZJ/JTxk7ZL577zd1AInIq0wuKBFqp2t/9tMsxSXegD0PLlzMB2fDYVGmncDtT4PzlE\nozcuiUJRipjY6DoesJlfHKyxNqJNNxjDOW3SjMiKtI8JtSQNH0BSyrRIyGNGXzX/uQArTH65IiPY\nkbNFkh5LMdN5Wn42QqnWV583GGVqmNlGzHkdprd4C+xMN4kkWbjaJVSDHQGeVbUdqT7K6j1Sa/gY\nKGZmys+BhBpakUrOXa2ouadrpwLjtjwhGHVq+zFPcxNyMBIuT43rLb116BwmRtaHmmQRa1Y9fgPg\n7LWLlkhNqEKOAPWFDQUuPpJqYr94vCP0A9arjsxYSzLkGGUsYf0r35nsW4eRMZjFyywzOyktfHup\nchvurg5EDDibgz8QtOdlGNqjerLNTRx+XGEqla27/jSiw8H1kgGrPDAeYsfAVs5y2+3WJNAsw9hT\nZzFM8t/CCIgXX2pj4yrJxSskmH6QjRspvr+VxbpVgFbgSKw/l1lDbmJDDPgX89Wmo0Bog+C8R21R\nqseSnoWZu17XsTWPMkOBeLmus/g7Aw7CMHMIYuQ4A4cJu9j0Gc6RVLvud7iLe2FMoSn0HdrObS/v\nRUAkfW832KW7aEdntoOLUdjtzOQ5QKD8YnNfz4LAzm3OhInLz/DshGnUdxR3EAL159zxjVlLZKGK\nElxu0aK5Jr8coyzWWtm+4HX92C+Qb5vXEXsmqRgIZoQPp5RpRukTUGg4zq4uAWspaTKNzxxlIEYI\npM4B/sIKkQ7sHptRAgZ/K8sDCJolRdeda8ln2ywDEJkz2nu1Kw0jm/+XghX8j1SIOG0qWiz6/Ybc\nzdbJO4Plp4J+X39ZxONVdiGg1EbaJ8UYFl+7inGY0c+VUCclN6lhgWULVKgp0ZbB3yLpKvdDBKgD\n7ZPXHoHemwi+R5aEY7fxs2S9MQcCvo7n2z8hTeHWb+DA5zq8/x/8eWhaI77HZ3DTvtkC2mVsiImR\nwjAkfk0z5JHXQ10Dqdwey7NVkAHLKwgXQG7SZFqrdI2PQV9HHw8bn3m6P+f7/EAy4MkYv8OHlwCg\nAz44PcpP9zXgPo5kl094cZivvFVVOC9A14EHv5xaRJSbue3ckHwAaVgXMonasMWqzQXHHWB4pM/2\nzq4cgM+X11VuzcRfROlRKdmu9umzZJq3sAFpM5xM4oyWtBLLHCdk+kmOffwThUPQcFT6Cp9se2Wv\nBQ3DldAMEtZ/j40qXaVivpsdHisEwN5FZQdxBMQqzZaP4UxldJ4xWKA3n61Muv4KIfoUKajddLuS\nZ5bqFL3zAkvxOf3JPUroU3wJfi2PGRcFmrNSWgp7VEHsWiBw//1PEbEYYXNzlCG322IbiY2RL6iR\nA7vI7/83fM4uY75AhDlBhuQHcEG1mL/9OfaC8TOhJiCwn2ByChDEFZhloTgtP/ZWa3aVGajOfbb2\n9X2Q7O2fzO9lBbF49OOnRLGTGH3jggbIELpZYfUF2wHdMdRJa3vJce8DTqVv771jzqUjE+fnwOv1\n269F8crvbc0cn13uXMkAyw1nN0wpG1H9l1P6jnVhrYq74DkOPEjkiK4unQKlx0aZI/YIHcAfszVM\nY0VIC2djUXZXrZlW3Y4bUmtoO4kMwI/iMgrYuA2cnHULO79HXnYXhrsdAAv9xYSiCAVQv1w7trDt\nXOmMVGvsc7eY3BpFegOKEqPqYIb5cwa75vy47XFo1zUtjPohgZ/g+MCSwqRz13l5N9vQlFSUL857\nRIPEeotyNTAsdh3vFX/jYfsonxch698ZbFLAAZ2uagiQ4oDuMeZpgeUnzcsT64lJa8GhO9cVASuE\ny0F6GpshZvVOe791qrdIB+EJ+FSESXq7IBlZ7u8nKzT3vwJbAFCmo2FIPqzBzR6n3aAQnYVuJIKN\n5Sg85UzY90qoBTGnu7wz2Z8lnZ8kGtpDSDOGhDFHBOGL1+xytbC3IeWxpkSUppE4dMh3UBtUpQpc\nrznsPHtwQusNoU5UHNl+ro08V1FXkHUs3BGo7cjO1E5mEsXECd0Yh+x/PAAC2sove1R0oZM6sGqv\n+cCCB7Vc9Az/Ei+rKcaQ7/cztvAERpeXYbhXrHeIwzJOeo6SllZ6eWAU0t9Umj75FZpWqfPlVngg\nxspwNQyDQ+pzoelgqX6CDTSoJJVBX6ypQoRpbQK004AUM2ODfMQeGrXJroVW7Dn/UvFzPHrPglZC\nHQmAG7G0MAv1OywENidA/tXzqhJYQ8VCtT2y/tKc3sh+T2PofUFs/sXPkTtUY9ALHm3DeX3H4CQP\n3Rb+ibBMospJV/C4wY8lXWgxxVCfBnLgO5r4RdQZ9iG+D+jNnqOzIsmOWgzNE+mbRYtKgPjmCs5w\nkpDjZCTmayxeTJBGAHsyCqnJxUhm0lia66LtCTkMcuB6j6i35CZ97kDpwIOi7AutER7n7lPH++Gn\nm3D321MZdm8kTkBVzTPhrnCA4JFEy+muDff1jfJIYuipA9VLqGCgficM2pPxl5PAt10RYCFRIczP\nImS8vQ89vm3/mEJLxVdbhKLSSIOUe0SyhbZ2qI77n7Pds4qv2SY5jt+R+iIhRASw7/v/kNYUxdiU\nd2whz+3cp4AylBxKxxEOrtr+SEwv9Onfj3IHTQtGHr7vZ7YgYe0YTvUebilhEDptwX6Bk4wHVH18\nELtY4IKlOENXltTlk4Fmfj2DWrqzrYwE27mXmVsBkrge382vltAomA/zHyDmmVAR9fSNI8kJqPv9\nBf0kt+ri0IU1ZZg9Woj0aa6yJritF6/2sxQwnu7hDud4nxN6agLEuHlhB37LbdL4HSPtvvRyQBEA\neetF5eYD5jUT+9nAbGZ+gGiyc7is+4wBcp5djCDST+xp/aqAUweRDNoGPk9chJw7tOrYGAsiLigf\nXAdVxBdEHR7w35WoJZOKR/ohU4uVHNlLcsqfPX8Dvr6UBD0lPGmwIq2vqjVCbdb7t6yILuEq9Ufm\nMGfARBYUMcz0CLCaO6fMddLXYb3+7JNc6BfgeNNs4c+og1l/7cS5kyAZ7etGCS4NmxOe8lgxHUWw\n8IO0tvTl6ukkA/6HFwXkZ0AbJcHifOFomjCv7anv2hOfuO9oEeFpp3WDj12n2Td+ZsWkf1AmoukR\neHaSxklqdCPcEI+UKHxQLNyr8pAOYswoRRGZbIqYW/ta17ZpL5ObFe7L0dnkTerzaK6+7QuQcXN4\nPEGg/nZtybL619pmNPfMj7PZjzIQeW/8N19FXPNLpPAoVClkPHG4Jw2tWKC4w+NgfUpUZJV5/oLG\nE0Qzbcl2mu8ISb5O1UcRkK4QStBrSta2QNvkxAkqOMW/jbQTViSnlFGnQPa3JBnvZ5xx8kSZDoL4\nzRzW+5sj6EamucW1FGMHEcaRnfoI9HYpQXf/8IyKuWe1UyYuhDL/2GkuQjpJTaIy21kze3sprXk6\nwpt1QJZ0Edtv5/8ks9db7hw2IbtXZBpSZpvE9ugD0lLiq5rPGhEahktiI7dZ3qbKT0bTXgXhrq9q\nSUMqwZoXaG/OkXvzEGInn5k3AP8V71EZfoxn5fn/UOuomkWmITLVKtg7tWd1LyrVbmJiZZFDZ7qI\np/XN53yVoQSXwoT4AshECVSbN/qX2+Qwu9Li7N8ET6x0aZ5qsJoEZr2yW2YVjQfbzCQy2cyj06/R\nMr7wwHXXa9rwr8iPvJZqmheEb7Y0AT8RjFFkICCE3TaRpLpc5GXvlm30aMqecTG2WVjbcnNiR+4F\n/C2wlDxRVm2bYvBdaKYVpicEjIE4yUAuMM8LkISEeRh569nRfVlQvmBwU9/WwXT3Ti/9jnbnlYvr\n+Ahjwb2/qNZd5qdcZoIm53BHEPFH6Vq1H/Gh/kzAJKdFN/PoXZKFLX463Mi70+9jrOYA1OiCHndK\no3zf7txPRp00vR2xJpj4unJbmpT4ffdThfuCSmKXRBTTZrgzY9yS6ftKCkee51Ztt+U6nPNlUpAN\nllyRhHkTPq060dxFuYOAoh9z58j+mdFB8eni0jqIqTlySXsVysNMX8AEngW2l89h7oV7E6W3Cthj\nLMSiKmG2/uMLyVm+c2btxBH1BiQRhQ1Rv9q39KwMbuGrzU1o1P3FtPG5HSsyJGmJtp6rDaNiiwxb\npFvHTWhTiDlj/0drNkTzFhG1JwaNzt0kOuewsLPdSir3uklbO6ecYaPK8Z4jgXerghf6lEyknZLS\nAYkKYA3rNh+45AAi1hRUOi3cp/pEHV/rSRmAPuczKvBZi/XmAqj6LGPxNcENDgMujqSw+7+uJJ0U\nQ9Yc5CELdrqvZ7mpxDFUx8QeiSww/sXE6aExkV68LMQHbrd4YaV96mjBcBLcyVqzRhLPDyuNzEFw\np4qk0TDXF1ACMNds2+Dt/Uuq9fxkmO5/q/GV1TyqO2RLP/z8GSXYvfZqOpJDtkFNGW4YcUU9OabN\nad+Q/9AomAx6BhJN0djqPBEafbnO0Jt3UVlPRE+gFekn0MvN+Tvw8vtBYQDL9VjaXZ350tmEqM5n\n8r4nQDI2NKf2AqFC1h6yx1D80OPYltLCRgU0y2GMZwp5ffMxpciUQYx48wteQkIj1vSGxelD7w3D\nFp/RHW7VRDRDzGez/pb0ZUlkmUzN7U1Eo3XRciUGIqIIUNn/ONyb3yvpQQA8wPiq1mwZIKZxyItD\n0U/CJNypm/F4npGM0VnY7fDcgFt7D29oorNPtCf2GAGAwDgKQmSNPmHVa8jJsYiuDcpw9URnTY9V\ntlH1HgWU+Tvr/riLXwOUqSufAPwmdP3p7nNAJVhufvf+5dLe5d3hxHtLxI6kjQwypWq3UBSwzQs2\nLO1+IJ1O4ds3iOra8+5J6u94UI1YsUbGYPOJwvzJ6SjHcLu8x6cWFhaUV2G6xs1fpi+7XO3lbm0y\n5W27tdy11ymOBHal9SdMg+tCFS62wxb2pPE8ZYDSXcwFxnU2QoKifLjZMYzKxXJFwweri6WL3VCt\niqEVBjol27uPCleezJI93TjZrRwL5CETU1b0nUl7hB5tni/KeEvIgKJ04f3KhE3w8g2abb6a0kXC\nuIlTQIIPxUM1ALbGJ+4f5qlVpvJ7nwT2bZ394BwTsH2S8eP241Bq2eVSuOi3Ab6tapNU4YNxIpBL\nDzcIQ/Jq3ToPenfueZrnGr3xKjeXYHJFhki5fzQIs0UkV8rvZP5qWUrko6dILN62pdzGOFJ+y4W0\nXfyMB2uKuXJv6Utx9fFydtYUyEj8Zrn90goiFM+NQU0iFdZ4QEvl1Ts+dv8/rrQH3eJTZqvI/yE3\n12TofYflRc2uRuGlx0r+Q6/3+33yPzrfr6U/aRx1N2E+vcv/L2kGVucq16ibQzJGIZqfHdBints2\nnB/xvJob2flgExd0M73QfeiBCRHzrKKyzj9Xy/YqcQjnpVZHJ0z8Khrxyx3uHHEjnFnVbod7bFEU\nc9ZV++TR2/rvd4/6tgAzf4slQhJqLWCG50xvRj+FPZPCbvxvtFnpArHuGPLhQP58M+qu8J1r6I7s\nag7qtFsFsPbykd8JxRwlB3lt4K7cNC1bKu6iSfT4vsU6XRY/ascVBykqvZDfh/zsnUvrZgmKCCBr\np5h8nDwS5zWHjQ5jShlMEqUr1g8tXsoh0g0RCOAYfHMpevkuPO3hdOrwj6+xJKkkfvuUKAJ15Siq\nsfGhPHOKEye2SzkPITZCk6Epg3vCrRweshnptUBNLAAEgZFGjAcsUQpnC+ckfUoseyAmdGwL2gw7\njQTTYXUrHvMyk+sKl6YTqd1bkaKW4kkUvaZ/rhWQefXwi759KpCKAStFGqfBO0P0buiDMWT3NQZW\nSLbgrltCu/0xvuYiq4t2Dq4pEfgQhWDCTXNAaavjbEt3oNWVDk2/oLH9DhhaEGJ7cp8+e6N6+QOS\n0bspQnURwauJmMJ8yUNYyf9ta8c40Np3aJDOareux0hbEISmQSc4Ibt8NqJFXqF7N2NWS5A+gSsi\norAZxPtzThjQ23JkrwJ0ZPNmbmcrPw1mfTOehFBdqoWPx/V1eDm5NNyriTd6LoYLbfHomQ+8WALR\nvZEOzoN+xewA5Uyk1S3+MzmEKZ3CVhK3GHoxuIMA7jpKebjYySo4sCnlQMb6qqT/bEYEyIsnWvcy\n82f7UbQc9TnIkHDhaRJw2m92dRvylHLCW54hHu6QLRMVKvHYeJNzEdtEit7GocKKSTkPn4BPI/Yi\nDB78TGR7uT3b85v7IOyxHBzEe9as39kKuQRced8pqdr9rbXMTxKG9fjurivrGePnZUbfZnOrpVRL\nkKCb+IpI64a/68XG/DR/SKALmfHrlb33vpCSd0LPcJ9gJUYGctaIA7XC5VtBzhDIcR9PBU+tTm9W\nau9psrwiInRr05n+P2ka3juxmJUvRjj+VYdfHsFkpNtAyitihSAmtBzaFQ/GCY9qd7kXWuxltG51\nrFrtLeXwN+9Dnr+9ExBWRWkyD107BNXg7Q127EZxGeVB9VR/X1KLOqjRClcK7lJrRpdva5kHRJ54\nKhRZV1sepRiHDRVCJIhJ9U6FWd/rQgWMmmcGawdgO1OX8kC5EdLJpXpkSeH5Yjqv3zzjASPu7K1e\nwWPiAxuwVgjdGKJIbluw6G5pJQ2uXDR5Xa5xsfAdroYQ0IRUvAkeOY3tND4Lkw/XVvx8KeFAWTNp\nXenmRJ5/iBqiIfM/c/rIofFpZCA5QqrNEMfQtDBkAJrxtq1sol50O0rih87WaJ+mdtwngYU7HOXS\nRQ+QLH1ciUq6EcJ73P+0hPAOokjzgjhqaori7+/iLyN1C/AWI1S59VXo4s8Lrl4s1/kVBR4QHr5V\nNiVmq4cDDDzuL1SP1j/K7bkn0GyS/RY8DPXrsujE06j3tTvjvnMGY/HaviTzAHivPGFzfXWofpT/\nFOBIBBwbn4pUVoeGWQJXIoNTcyeIxLLEOiJ2zYAUEwEdsOn+f8+dtBaERYpwAhYE4NLbwH6ple55\nRwSPKczzLDMieRAXxc+iQjGV4j/5oqHAmcwgXN7zvk/aGpMYPyA2berXcmFw0LSY1sepZIKYaWuj\noYF9Y7ElShrguXYyk1lAuvOX8VPhIpudfS7dnJHZRceapQi/Xl8DlsQg5fPaQo7gvh+5Hxbe5/dt\nsNmxiidiIGAyoTi091EqBHlEwjR9IhtjBB9469BfzhnT6ccPVCINNxJpiUBJiEOtublFQ/M7KWIP\nfC2d0pCxn06H9bmLT9zfhWsyldmMeBU9AEB2Ck/kn+c75sFlRezkk8wmqlFM2NcAvQcSf8GR2hO/\ncFxi9ZzXFOJCgdfy/9zY0YFHKKnurAgHZlgOdBl8inDgvgC2RlDXnzIuz23kNA9RxHQ2/FXl0z61\nnYwe+SCMNDzoPcUZcUBhPZonJ+3irIWLUdjkbb7qTGymgjf5KR/XMuWA/VX/8uRtjWSOc95Nbt8a\nCaci43oMh2lwO79FoeUffZYmZV3fldqnDs1ze/aOGywPwqcT1jntje94qn3lvQoQ/BJ/k93rEy+2\n5x0vRK6gNlXO4KtnS9D9Ypwk0VbvxdQ8n1IGdI8B9XTjg6ENjqtUbomhDPSFQCjwicweZXrRfUOD\nh+cPfCp22/DQgxGK2DHVgSjAS7NgTpMzbMt2/jQdh7ewO5Ek07NBPGfI47RJujdhRIoS6lFB2L5i\nM2Ly8kjyyAQreVG7AMc6P3r5WOlcr9TujTmvWGh8TOwQ1LDhVNVKJ+JGG1AzuIFYfDJBzzcZd1A5\nteF80j/Z0cUfa1hdkR4d4OTqS5QotD9WNh4QCndwopopxD6G1h9s/s5UVf0blaIfjDBU0/Nx9WVK\n6t/6Ruyhta8hQ9IxRw2VqEEY6Evx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{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_vio_counter (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [0 : 0] probe1;\ninput [7 : 0] probe2;\ninput [15 : 0] probe3;\ninput [0 : 0] probe4;\ninput [0 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [7 : 0] probe8;\ninput [15 : 0] probe9;\ninput [15 : 0] probe10;\n\n\nendmodule\n", "num_lines": 83}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"ila_vio_counter,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_vio_counter,ila,{x_ipProduct=Vivado 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OBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1,C_PROBE0_TYPE=0,C_PROBE1_TYPE=0,C_PROBE2_TYPE=0,C_PROBE3_TYPE=0,C_PROBE4_TYPE=0,C_PROBE5_TYPE=0,\\\nC_PROBE6_TYPE=0,C_PROBE7_TYPE=0,C_PROBE8_TYPE=0,C_PROBE9_TYPE=0,C_PROBE10_TYPE=0,C_PROBE11_TYPE=1,C_PROBE12_TYPE=1,C_PROBE13_TYPE=1,C_PROBE14_TYPE=1,C_PROBE15_TYPE=1,C_PROBE16_TYPE=1,C_PROBE17_TYPE=1,C_PROBE18_TYPE=1,C_PROBE19_TYPE=1,C_PROBE20_TYPE=1,C_PROBE21_TYPE=1,C_PROBE22_TYPE=1,C_PROBE23_TYPE=1,C_PROBE24_TYPE=1,C_PROBE25_TYPE=1,C_PROBE26_TYPE=1,C_PROBE27_TYPE=1,C_PROBE28_TYPE=1,C_PROBE29_TYPE=1,C_PROBE30_TYPE=1,C_PROBE31_TYPE=1,C_PROBE32_TYPE=1,C_PROBE33_TYPE=1,C_PROBE34_TYPE=1,C_PROBE35_TYPE=1,C_PROBE36_TYPE=1,C_PROBE37_TYPE=1,C_PROBE38_TYPE=1,C_PROBE39_TYPE=1,C_PROBE40_TYPE=1,C_PROBE41_TYPE=1,C_PROBE42_TYPE=1,C_PROBE43_TYPE=1,C_PROBE44_TYPE=1,C_PROBE45_TYPE=1,C_PROBE46_TYPE=1,C_PROBE47_TYPE=1,C_PROBE48_TYPE=1,C_PROBE49_TYPE=1,C_PROBE50_TYPE=1,C_PROBE51_TYPE=1,C_PROBE52_TYPE=1,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,\\\nC_PROBE106_TYPE=1,C_PROBE107_TYPE=1,C_PROBE108_TYPE=1,C_PROBE109_TYPE=1,C_PROBE110_TYPE=1,C_PROBE111_TYPE=1,C_PROBE112_TYPE=1,C_PROBE113_TYPE=1,C_PROBE114_TYPE=1,C_PROBE115_TYPE=1,C_PROBE116_TYPE=1,C_PROBE117_TYPE=1,C_PROBE118_TYPE=1,C_PROBE119_TYPE=1,C_PROBE120_TYPE=1,C_PROBE121_TYPE=1,C_PROBE122_TYPE=1,C_PROBE123_TYPE=1,C_PROBE124_TYPE=1,C_PROBE125_TYPE=1,C_PROBE126_TYPE=1,C_PROBE127_TYPE=1,C_PROBE128_TYPE=1,C_PROBE129_TYPE=1,C_PROBE130_TYPE=1,C_PROBE131_TYPE=1,C_PROBE132_TYPE=1,C_PROBE133_TYPE=1,C_PROBE134_TYPE=1,C_PROBE135_TYPE=1,C_PROBE136_TYPE=1,C_PROBE137_TYPE=1,C_PROBE138_TYPE=1,C_PROBE139_TYPE=1,C_PROBE140_TYPE=1,C_PROBE141_TYPE=1,C_PROBE142_TYPE=1,C_PROBE143_TYPE=1,C_PROBE144_TYPE=1,C_PROBE145_TYPE=1,C_PROBE146_TYPE=1,C_PROBE147_TYPE=1,C_PROBE148_TYPE=1,C_PROBE149_TYPE=1,C_PROBE150_TYPE=1,C_PROBE151_TYPE=1,C_PROBE152_TYPE=1,C_PROBE153_TYPE=1,C_PROBE154_TYPE=1,C_PROBE155_TYPE=1,C_PROBE156_TYPE=1,C_PROBE157_TYPE=1,C_PROBE158_TYPE=1,C_PROBE159_TYPE=1,C_PROBE160_TYPE=1,C_PROBE161_TYPE=1,C_PROBE162_TYPE=1,C_PROBE163_TYPE=1,C_PROBE164_TYPE=1,C_PROBE165_TYPE=1,C_PROBE166_TYPE=1,C_PROBE167_TYPE=1,C_PROBE168_TYPE=1,C_PROBE169_TYPE=1,C_PROBE170_TYPE=1,C_PROBE171_TYPE=1,C_PROBE172_TYPE=1,C_PROBE173_TYPE=1,C_PROBE174_TYPE=1,C_PROBE175_TYPE=1,C_PROBE176_TYPE=1,C_PROBE177_TYPE=1,C_PROBE178_TYPE=1,C_PROBE179_TYPE=1,C_PROBE180_TYPE=1,C_PROBE181_TYPE=1,C_PROBE182_TYPE=1,C_PROBE183_TYPE=1,C_PROBE184_TYPE=1,C_PROBE185_TYPE=1,C_PROBE186_TYPE=1,C_PROBE187_TYPE=1,C_PROBE188_TYPE=1,C_PROBE189_TYPE=1,C_PROBE190_TYPE=1,C_PROBE191_TYPE=1,C_PROBE192_TYPE=1,C_PROBE193_TYPE=1,C_PROBE194_TYPE=1,C_PROBE195_TYPE=1,C_PROBE196_TYPE=1,C_PROBE197_TYPE=1,C_PROBE198_TYPE=1,C_PROBE199_TYPE=1,C_PROBE200_TYPE=1,C_PROBE201_TYPE=1,C_PROBE202_TYPE=1,C_PROBE203_TYPE=1,C_PROBE204_TYPE=1,C_PROBE205_TYPE=1,\\\nC_PROBE206_TYPE=1,C_PROBE207_TYPE=1,C_PROBE208_TYPE=1,C_PROBE209_TYPE=1,C_PROBE210_TYPE=1,C_PROBE211_TYPE=1,C_PROBE212_TYPE=1,C_PROBE213_TYPE=1,C_PROBE214_TYPE=1,C_PROBE215_TYPE=1,C_PROBE216_TYPE=1,C_PROBE217_TYPE=1,C_PROBE218_TYPE=1,C_PROBE219_TYPE=1,C_PROBE220_TYPE=1,C_PROBE221_TYPE=1,C_PROBE222_TYPE=1,C_PROBE223_TYPE=1,C_PROBE224_TYPE=1,C_PROBE225_TYPE=1,C_PROBE226_TYPE=1,C_PROBE227_TYPE=1,C_PROBE228_TYPE=1,C_PROBE229_TYPE=1,C_PROBE230_TYPE=1,C_PROBE231_TYPE=1,C_PROBE232_TYPE=1,C_PROBE233_TYPE=1,C_PROBE234_TYPE=1,C_PROBE235_TYPE=1,C_PROBE236_TYPE=1,C_PROBE237_TYPE=1,C_PROBE238_TYPE=1,C_PROBE239_TYPE=1,C_PROBE240_TYPE=1,C_PROBE241_TYPE=1,C_PROBE242_TYPE=1,C_PROBE243_TYPE=1,C_PROBE244_TYPE=1,C_PROBE245_TYPE=1,C_PROBE246_TYPE=1,C_PROBE247_TYPE=1,C_PR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E525_TYPE=1,C_PROBE526_TYPE=1,C_PROBE527_TYPE=1,C_PROBE528_TYPE=1,C_PROBE529_TYPE=1,C_PROBE530_TYPE=1,C_PROBE531_TYPE=1,C_PROBE532_TYPE=1,C_PROBE533_TYPE=1,C_PROBE534_TYPE=1,C_PROBE535_TYPE=1,C_PROBE536_TYPE=1,C_PROBE537_TYPE=1,C_PROBE538_TYPE=1,C_PROBE539_TYPE=1,C_PROBE540_TYPE=1,C_PROBE541_TYPE=1,C_PROBE542_TYPE=1,C_PROBE543_TYPE=1,C_PROBE544_TYPE=1,C_PROBE545_TYPE=1,C_PROBE546_TYPE=1,C_PROBE547_TYPE=1,C_PROBE548_TYPE=1,C_PROBE549_TYPE=1,C_PROBE550_TYPE=1,C_PROBE551_TYPE=1,C_PROBE552_TYPE=1,C_PROBE553_TYPE=1,C_PROBE554_TYPE=1,C_PROBE555_TYPE=1,C_PROBE556_TYPE=1,C_PROBE557_TYPE=1,C_PROBE558_TYPE=1,C_PROBE559_TYPE=1,C_PROBE560_TYPE=1,C_PROBE561_TYPE=1,C_PROBE562_TYPE=1,C_PROBE563_TYPE=1,C_PROBE564_TYPE=1,C_PROBE565_TYPE=1,C_PROBE566_TYPE=1,C_PROBE567_TYPE=1,C_PROBE568_TYPE=1,C_PROBE569_TYPE=1,C_PROBE570_TYPE=1,C_PROBE571_TYPE=1,C_PROBE572_TYPE=1,C_PROBE573_TYPE=1,C_PROBE574_TYPE=1,C_PROBE575_TYPE=1,C_PROBE576_TYPE=1,C_PROBE577_TYPE=1,C_PROBE578_TYPE=1,C_PROBE579_TYPE=1,C_PROBE580_TYPE=1,C_PROBE581_TYPE=1,C_PROBE582_TYPE=1,C_PROBE583_TYPE=1,C_PROBE584_TYPE=1,C_PROBE585_TYPE=1,C_PROBE586_TYPE=1,C_PROBE587_TYPE=1,C_PROBE588_TYPE=1,C_PROBE589_TYPE=1,C_PROBE590_TYPE=1,C_PROBE591_TYPE=1,C_PROBE592_TYPE=1,C_PROBE593_TYPE=1,C_PROBE594_TYPE=1,C_PROBE595_TYPE=1,C_PROBE596_TYPE=1,C_PROBE597_TYPE=1,C_PROBE598_TYPE=1,C_PROBE599_TYPE=1,C_PROBE600_TYPE=1,C_PROBE601_TYPE=1,C_PROBE602_TYPE=1,C_PROBE603_TYPE=1,C_PROBE604_TYPE=1,C_PROBE605_TYPE=1,\\\nC_PROBE606_TYPE=1,C_PROBE607_TYPE=1,C_PROBE608_TYPE=1,C_PROBE609_TYPE=1,C_PROBE610_TYPE=1,C_PROBE611_TYPE=1,C_PROBE612_TYPE=1,C_PROBE613_TYPE=1,C_PROBE614_TYPE=1,C_PROBE615_TYPE=1,C_PROBE616_TYPE=1,C_PROBE617_TYPE=1,C_PROBE618_TYPE=1,C_PROBE619_TYPE=1,C_PROBE620_TYPE=1,C_PROBE621_TYPE=1,C_PROBE622_TYPE=1,C_PROBE623_TYPE=1,C_PROBE624_TYPE=1,C_PROBE625_TYPE=1,C_PROBE626_TYPE=1,C_PROBE627_TYPE=1,C_PROBE628_TYPE=1,C_PROBE629_TYPE=1,C_PROBE630_TYPE=1,C_PROBE631_TYPE=1,C_PROBE632_TYPE=1,C_PROBE633_TYPE=1,C_PROBE634_TYPE=1,C_PROBE635_TYPE=1,C_PROBE636_TYPE=1,C_PROBE637_TYPE=1,C_PROBE638_TYPE=1,C_PROBE639_TYPE=1,C_PROBE640_TYPE=1,C_PROBE641_TYPE=1,C_PROBE642_TYPE=1,C_PROBE643_TYPE=1,C_PROBE644_TYPE=1,C_PROBE645_TYPE=1,C_PROBE646_TYPE=1,C_PROBE647_TYPE=1,C_PROBE648_TYPE=1,C_PROBE649_TYPE=1,C_PROBE650_TYPE=1,C_PROBE651_TYPE=1,C_PROBE652_TYPE=1,C_PROBE653_TYPE=1,C_PROBE654_TYPE=1,C_PROBE655_TYPE=1,C_PROBE656_TYPE=1,C_PROBE657_TYPE=1,C_PROBE658_TYPE=1,C_PROBE659_TYPE=1,C_PROBE660_TYPE=1,C_PROBE661_TYPE=1,C_PROBE662_TYPE=1,C_PROBE663_TYPE=1,C_PROBE664_TYPE=1,C_PROBE665_TYPE=1,C_PROBE666_TYPE=1,C_PROBE667_TYPE=1,C_PROBE668_TYPE=1,C_PROBE669_TYPE=1,C_PROBE670_TYPE=1,C_PROBE671_TYPE=1,C_PROBE672_TYPE=1,C_PROBE673_TYPE=1,C_PROBE674_TYPE=1,C_PROBE675_TYPE=1,C_PROBE676_TYPE=1,C_PROBE677_TYPE=1,C_PROBE678_TYPE=1,C_PROBE679_TYPE=1,C_PROBE680_TYPE=1,C_PROBE681_TYPE=1,C_PROBE682_TYPE=1,C_PROBE683_TYPE=1,C_PROBE684_TYPE=1,C_PROBE685_TYPE=1,C_PROBE686_TYPE=1,C_PROBE687_TYPE=1,C_PROBE688_TYPE=1,C_PROBE689_TYPE=1,C_PROBE690_TYPE=1,C_PROBE691_TYPE=1,C_PROBE692_TYPE=1,C_PROBE693_TYPE=1,C_PROBE694_TYPE=1,C_PROBE695_TYPE=1,C_PROBE696_TYPE=1,C_PROBE697_TYPE=1,C_PROBE698_TYPE=1,C_PROBE699_TYPE=1,C_PROBE700_TYPE=1,C_PROBE701_TYPE=1,C_PROBE702_TYPE=1,C_PROBE703_TYPE=1,C_PROBE704_TYPE=1,C_PROBE705_TYPE=1,\\\nC_PROBE706_TYPE=1,C_PROBE707_TYPE=1,C_PROBE708_TYPE=1,C_PROBE709_TYPE=1,C_PROBE710_TYPE=1,C_PROBE711_TYPE=1,C_PROBE712_TYPE=1,C_PROBE713_TYPE=1,C_PROBE714_TYPE=1,C_PROBE715_TYPE=1,C_PROBE716_TYPE=1,C_PROBE717_TYPE=1,C_PROBE718_TYPE=1,C_PROBE719_TYPE=1,C_PROBE720_TYPE=1,C_PROBE721_TYPE=1,C_PROBE722_TYPE=1,C_PROBE723_TYPE=1,C_PROBE724_TYPE=1,C_PROBE725_TYPE=1,C_PROBE726_TYPE=1,C_PROBE727_TYPE=1,C_PROBE728_TYPE=1,C_PROBE729_TYPE=1,C_PROBE730_TYPE=1,C_PROBE731_TYPE=1,C_PROBE732_TYPE=1,C_PROBE733_TYPE=1,C_PROBE734_TYPE=1,C_PROBE735_TYPE=1,C_PROBE736_TYPE=1,C_PROBE737_TYPE=1,C_PROBE738_TYPE=1,C_PROBE739_TYPE=1,C_PROBE740_TYPE=1,C_PROBE741_TYPE=1,C_PROBE742_TYPE=1,C_PROBE743_TYPE=1,C_PROBE744_TYPE=1,C_PROBE745_TYPE=1,C_PROBE746_TYPE=1,C_PROBE747_TYPE=1,C_PROBE748_TYPE=1,C_PROBE749_TYPE=1,C_PROBE750_TYPE=1,C_PROBE751_TYPE=1,C_PROBE752_TYPE=1,C_PROBE753_TYPE=1,C_PROBE754_TYPE=1,C_PROBE755_TYPE=1,C_PROBE756_TYPE=1,C_PROBE757_TYPE=1,C_PROBE758_TYPE=1,C_PROBE759_TYPE=1,C_PROBE760_TYPE=1,C_PROBE761_TYPE=1,C_PROBE762_TYPE=1,C_PROBE763_TYPE=1,C_PROBE764_TYPE=1,C_PROBE765_TYPE=1,C_PROBE766_TYPE=1,C_PROBE767_TYPE=1,C_PROBE768_TYPE=1,C_PROBE769_TYPE=1,C_PROBE770_TYPE=1,C_PROBE771_TYPE=1,C_PROBE772_TYPE=1,C_PROBE773_TYPE=1,C_PROBE774_TYPE=1,C_PROBE775_TYPE=1,C_PROBE776_TYPE=1,C_PROBE777_TYPE=1,C_PROBE778_TYPE=1,C_PROBE779_TYPE=1,C_PROBE780_TYPE=1,C_PROBE781_TYPE=1,C_PROBE782_TYPE=1,C_PROBE783_TYPE=1,C_PROBE784_TYPE=1,C_PROBE785_TYPE=1,C_PROBE786_TYPE=1,C_PROBE787_TYPE=1,C_PROBE788_TYPE=1,C_PROBE789_TYPE=1,C_PROBE790_TYPE=1,C_PROBE791_TYPE=1,C_PROBE792_TYPE=1,C_PROBE793_TYPE=1,C_PROBE794_TYPE=1,C_PROBE795_TYPE=1,C_PROBE796_TYPE=1,C_PROBE797_TYPE=1,C_PROBE798_TYPE=1,C_PROBE799_TYPE=1,C_PROBE800_TYPE=1,C_PROBE801_TYPE=1,C_PROBE802_TYPE=1,C_PROBE803_TYPE=1,C_PROBE804_TYPE=1,C_PROBE805_TYPE=1,\\\nC_PROBE806_TYPE=1,C_PROBE807_TYPE=1,C_PROBE808_TYPE=1,C_PROBE809_TYPE=1,C_PROBE810_TYPE=1,C_PROBE811_TYPE=1,C_PROBE812_TYPE=1,C_PROBE813_TYPE=1,C_PROBE814_TYPE=1,C_PROBE815_TYPE=1,C_PROBE816_TYPE=1,C_PROBE817_TYPE=1,C_PROBE818_TYPE=1,C_PROBE819_TYPE=1,C_PROBE820_TYPE=1,C_PROBE821_TYPE=1,C_PROBE822_TYPE=1,C_PROBE823_TYPE=1,C_PROBE824_TYPE=1,C_PROBE825_TYPE=1,C_PROBE826_TYPE=1,C_PROBE827_TYPE=1,C_PROBE828_TYPE=1,C_PROBE829_TYPE=1,C_PROBE830_TYPE=1,C_PROBE831_TYPE=1,C_PROBE832_TYPE=1,C_PROBE833_TYPE=1,C_PROBE834_TYPE=1,C_PROBE835_TYPE=1,C_PROBE836_TYPE=1,C_PROBE837_TYPE=1,C_PROBE838_TYPE=1,C_PROBE839_TYPE=1,C_PROBE840_TYPE=1,C_PROBE841_TYPE=1,C_PROBE842_TYPE=1,C_PROBE843_TYPE=1,C_PROBE844_TYPE=1,C_PROBE845_TYPE=1,C_PROBE846_TYPE=1,C_PROBE847_TYPE=1,C_PROBE848_TYPE=1,C_PROBE849_TYPE=1,C_PROBE850_TYPE=1,C_PROBE851_TYPE=1,C_PROBE852_TYPE=1,C_PROBE853_TYPE=1,C_PROBE854_TYPE=1,C_PROBE855_TYPE=1,C_PROBE856_TYPE=1,C_PROBE857_TYPE=1,C_PROBE858_TYPE=1,C_PROBE859_TYPE=1,C_PROBE860_TYPE=1,C_PROBE861_TYPE=1,C_PROBE862_TYPE=1,C_PROBE863_TYPE=1,C_PROBE864_TYPE=1,C_PROBE865_TYPE=1,C_PROBE866_TYPE=1,C_PROBE867_TYPE=1,C_PROBE868_TYPE=1,C_PROBE869_TYPE=1,C_PROBE870_TYPE=1,C_PROBE871_TYPE=1,C_PROBE872_TYPE=1,C_PROBE873_TYPE=1,C_PROBE874_TYPE=1,C_PROBE875_TYPE=1,C_PROBE876_TYPE=1,C_PROBE877_TYPE=1,C_PROBE878_TYPE=1,C_PROBE879_TYPE=1,C_PROBE880_TYPE=1,C_PROBE881_TYPE=1,C_PROBE882_TYPE=1,C_PROBE883_TYPE=1,C_PROBE884_TYPE=1,C_PROBE885_TYPE=1,C_PROBE886_TYPE=1,C_PROBE887_TYPE=1,C_PROBE888_TYPE=1,C_PROBE889_TYPE=1,C_PROBE890_TYPE=1,C_PROBE891_TYPE=1,C_PROBE892_TYPE=1,C_PROBE893_TYPE=1,C_PROBE894_TYPE=1,C_PROBE895_TYPE=1,C_PROBE896_TYPE=1,C_PROBE897_TYPE=1,C_PROBE898_TYPE=1,C_PROBE899_TYPE=1,C_PROBE900_TYPE=1,C_PROBE901_TYPE=1,C_PROBE902_TYPE=1,C_PROBE903_TYPE=1,C_PROBE904_TYPE=1,C_PROBE905_TYPE=1,\\\nC_PROBE906_TYPE=1,C_PROBE907_TYPE=1,C_PROBE908_TYPE=1,C_PROBE909_TYPE=1,C_PROBE910_TYPE=1,C_PROBE911_TYPE=1,C_PROBE912_TYPE=1,C_PROBE913_TYPE=1,C_PROBE914_TYPE=1,C_PROBE915_TYPE=1,C_PROBE916_TYPE=1,C_PROBE917_TYPE=1,C_PROBE918_TYPE=1,C_PROBE919_TYPE=1,C_PROBE920_TYPE=1,C_PROBE921_TYPE=1,C_PROBE922_TYPE=1,C_PROBE923_TYPE=1,C_PROBE924_TYPE=1,C_PROBE925_TYPE=1,C_PROBE926_TYPE=1,C_PROBE927_TYPE=1,C_PROBE928_TYPE=1,C_PROBE929_TYPE=1,C_PROBE930_TYPE=1,C_PROBE931_TYPE=1,C_PROBE932_TYPE=1,C_PROBE933_TYPE=1,C_PROBE934_TYPE=1,C_PROBE935_TYPE=1,C_PROBE936_TYPE=1,C_PROBE937_TYPE=1,C_PROBE938_TYPE=1,C_PROBE939_TYPE=1,C_PROBE940_TYPE=1,C_PROBE941_TYPE=1,C_PROBE942_TYPE=1,C_PROBE943_TYPE=1,C_PROBE944_TYPE=1,C_PROBE945_TYPE=1,C_PROBE946_TYPE=1,C_PROBE947_TYPE=1,C_PROBE948_TYPE=1,C_PROBE949_TYPE=1,C_PROBE950_TYPE=1,C_PROBE951_TYPE=1,C_PROBE952_TYPE=1,C_PROBE953_TYPE=1,C_PROBE954_TYPE=1,C_PROBE955_TYPE=1,C_PROBE956_TYPE=1,C_PROBE957_TYPE=1,C_PROBE958_TYPE=1,C_PROBE959_TYPE=1,C_PROBE960_TYPE=1,C_PROBE961_TYPE=1,C_PROBE962_TYPE=1,C_PROBE963_TYPE=1,C_PROBE964_TYPE=1,C_PROBE965_TYPE=1,C_PROBE966_TYPE=1,C_PROBE967_TYPE=1,C_PROBE968_TYPE=1,C_PROBE969_TYPE=1,C_PROBE970_TYPE=1,C_PROBE971_TYPE=1,C_PROBE972_TYPE=1,C_PROBE973_TYPE=1,C_PROBE974_TYPE=1,C_PROBE975_TYPE=1,C_PROBE976_TYPE=1,C_PROBE977_TYPE=1,C_PROBE978_TYPE=1,C_PROBE979_TYPE=1,C_PROBE980_TYPE=1,C_PROBE981_TYPE=1,C_PROBE982_TYPE=1,C_PROBE983_TYPE=1,C_PROBE984_TYPE=1,C_PROBE985_TYPE=1,C_PROBE986_TYPE=1,C_PROBE987_TYPE=1,C_PROBE988_TYPE=1,C_PROBE989_TYPE=1,C_PROBE990_TYPE=1,C_PROBE991_TYPE=1,C_PROBE992_TYPE=1,C_PROBE993_TYPE=1,C_PROBE994_TYPE=1,C_PROBE995_TYPE=1,C_PROBE996_TYPE=1,C_PROBE997_TYPE=1,C_PROBE998_TYPE=1,C_PROBE999_TYPE=1,C_PROBE1000_TYPE=1,C_PROBE1001_TYPE=1,C_PROBE1002_TYPE=1,C_PROBE1003_TYPE=1,C_PROBE1004_TYPE=1,C_PROBE1005_TYPE=1,\\\nC_PROBE1006_TYPE=1,C_PROBE1007_TYPE=1,C_PROBE1008_TYPE=1,C_PROBE1009_TYPE=1,C_PROBE1010_TYPE=1,C_PROBE1011_TYPE=1,C_PROBE1012_TYPE=1,C_PROBE1013_TYPE=1,C_PROBE1014_TYPE=1,C_PROBE1015_TYPE=1,C_PROBE1016_TYPE=1,C_PROBE1017_TYPE=1,C_PROBE1018_TYPE=1,C_PROBE1019_TYPE=1,C_PROBE1020_TYPE=1,C_PROBE1021_TYPE=1,C_PROBE1022_TYPE=1,C_PROBE1023_TYPE=1}\" *)\n\nmodule ila_vio_counter (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [0 : 0] probe1;\ninput [7 : 0] probe2;\ninput [15 : 0] probe3;\ninput [0 : 0] probe4;\ninput [0 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [7 : 0] probe8;\ninput [15 : 0] probe9;\ninput [15 : 0] probe10;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_11_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(11),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2020),\n.C_MINOR_VERSION(2),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(0),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(4),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH (32),\n.C_ILA_CLK_FREQ(2000000),\n.C_PROBE0_WIDTH(1),\n.C_PROBE1_WIDTH(1),\n.C_PROBE2_WIDTH(8),\n.C_PROBE3_WIDTH(16),\n.C_PROBE4_WIDTH(1),\n.C_PROBE5_WIDTH(1),\n.C_PROBE6_WIDTH(1),\n.C_PROBE7_WIDTH(1),\n.C_PROBE8_WIDTH(8),\n.C_PROBE9_WIDTH(16),\n.C_PROBE10_WIDTH(16),\n.C_PROBE11_WIDTH(1),\n.C_PROBE12_WIDTH(1),\n.C_PROBE13_WIDTH(1),\n.C_PROBE14_WIDTH(1),\n.C_PROBE15_WIDTH(1),\n.C_PROBE16_WIDTH(1),\n.C_PROBE17_WIDTH(1),\n.C_PROBE18_WIDTH(1),\n.C_PROBE19_WIDTH(1),\n.C_PROBE20_WIDTH(1),\n.C_PROBE21_WIDTH(1),\n.C_PROBE22_WIDTH(1),\n.C_PROBE23_WIDTH(1),\n.C_PROBE24_WIDTH(1),\n.C_PROBE25_WIDTH(1),\n.C_PROBE26_WIDTH(1),\n.C_PROBE27_WIDTH(1),\n.C_PROBE28_WIDTH(1),\n.C_PROBE29_WIDTH(1),\n.C_PROBE30_WIDTH(1),\n.C_PROBE31_WIDTH(1),\n.C_PROBE32_WIDTH(1),\n.C_PROBE33_WIDTH(1),\n.C_PROBE34_WIDTH(1),\n.C_PROBE35_WIDTH(1),\n.C_PROBE36_WIDTH(1),\n.C_PROBE37_WIDTH(1),\n.C_PROBE38_WIDTH(1),\n.C_PROBE39_WIDTH(1),\n.C_PROBE40_WIDTH(1),\n.C_PROBE41_WIDTH(1),\n.C_PROBE42_WIDTH(1),\n.C_PROBE43_WIDTH(1),\n.C_PROBE44_WIDTH(1),\n.C_PROBE45_WIDTH(1),\n.C_PROBE46_WIDTH(1),\n.C_PROBE47_WIDTH(1),\n.C_PROBE48_WIDTH(1),\n.C_PROBE49_WIDTH(1),\n.C_PROBE50_WIDTH(1),\n.C_PROBE51_WIDTH(1),\n.C_PROBE52_WIDTH(1),\n.C_PROBE53_WIDTH(1),\n.C_PROBE54_WIDTH(1),\n.C_PROBE55_WIDTH(1),\n.C_PROBE56_WIDTH(1),\n.C_PROBE57_WIDTH(1),\n.C_PROBE58_WIDTH(1),\n.C_PROBE59_WIDTH(1),\n.C_PROBE60_WIDTH(1),\n.C_PROBE61_WIDTH(1),\n.C_PROBE62_WIDTH(1),\n.C_PROBE63_WIDTH(1),\n.C_PROBE64_WIDTH(1),\n.C_PROBE65_WIDTH(1),\n.C_PROBE66_WIDTH(1),\n.C_PROBE67_WIDTH(1),\n.C_PROBE68_WIDTH(1),\n.C_PROBE69_WIDTH(1),\n.C_PROBE70_WIDTH(1),\n.C_PROBE71_WIDTH(1),\n.C_PROBE72_WIDTH(1),\n.C_PROBE73_WIDTH(1),\n.C_PROBE74_WIDTH(1),\n.C_PROBE75_WIDTH(1),\n.C_PROBE76_WIDTH(1),\n.C_PROBE77_WIDTH(1),\n.C_PROBE78_WIDTH(1),\n.C_PROBE79_WIDTH(1),\n.C_PROBE80_WIDTH(1),\n.C_PROBE81_WIDTH(1),\n.C_PROBE82_WIDTH(1),\n.C_PROBE83_WIDTH(1),\n.C_PROBE84_WIDTH(1),\n.C_PROBE85_WIDTH(1),\n.C_PROBE86_WIDTH(1),\n.C_PROBE87_WIDTH(1),\n.C_PROBE88_WIDTH(1),\n.C_PROBE89_WIDTH(1),\n.C_PROBE90_WIDTH(1),\n.C_PROBE91_WIDTH(1),\n.C_PROBE92_WIDTH(1),\n.C_PROBE93_WIDTH(1),\n.C_PROBE94_WIDTH(1),\n.C_PROBE95_WIDTH(1),\n.C_PROBE96_WIDTH(1),\n.C_PROBE97_WIDTH(1),\n.C_PROBE98_WIDTH(1),\n.C_PROBE99_WIDTH(1),\n.C_PROBE100_WIDTH(1),\n.C_PROBE101_WIDTH(1),\n.C_PROBE102_WIDTH(1),\n.C_PROBE103_WIDTH(1),\n.C_PROBE104_WIDTH(1),\n.C_PROBE105_WIDTH(1),\n.C_PROBE106_WIDTH(1),\n.C_PROBE107_WIDTH(1),\n.C_PROBE108_WIDTH(1),\n.C_PROBE109_WIDTH(1),\n.C_PROBE110_WIDTH(1),\n.C_PROBE111_WIDTH(1),\n.C_PROBE112_WIDTH(1),\n.C_PROBE113_WIDTH(1),\n.C_PROBE114_WIDTH(1),\n.C_PROBE115_WIDTH(1),\n.C_PROBE116_WIDTH(1),\n.C_PROBE117_WIDTH(1),\n.C_PROBE118_WIDTH(1),\n.C_PROBE119_WIDTH(1),\n.C_PROBE120_WIDTH(1),\n.C_PROBE121_WIDTH(1),\n.C_PROBE122_WIDTH(1),\n.C_PROBE123_WIDTH(1),\n.C_PROBE124_WIDTH(1),\n.C_PROBE125_WIDTH(1),\n.C_PROBE126_WIDTH(1),\n.C_PROBE127_WIDTH(1),\n.C_PROBE128_WIDTH(1),\n.C_PROBE129_WIDTH(1),\n.C_PROBE130_WIDTH(1),\n.C_PROBE131_WIDTH(1),\n.C_PROBE132_WIDTH(1),\n.C_PROBE133_WIDTH(1),\n.C_PROBE134_WIDTH(1),\n.C_PROBE135_WIDTH(1),\n.C_PROBE136_WIDTH(1),\n.C_PROBE137_WIDTH(1),\n.C_PROBE138_WIDTH(1),\n.C_PROBE139_WIDTH(1),\n.C_PROBE140_WIDTH(1),\n.C_PROBE141_WIDTH(1),\n.C_PROBE142_WIDTH(1),\n.C_PROBE143_WIDTH(1),\n.C_PROBE144_WIDTH(1),\n.C_PROBE145_WIDTH(1),\n.C_PROBE146_WIDTH(1),\n.C_PROBE147_WIDTH(1),\n.C_PROBE148_WIDTH(1),\n.C_PROBE149_WIDTH(1),\n.C_PROBE150_WIDTH(1),\n.C_PROBE151_WIDTH(1),\n.C_PROBE152_WIDTH(1),\n.C_PROBE153_WIDTH(1),\n.C_PROBE154_WIDTH(1),\n.C_PROBE155_WIDTH(1),\n.C_PROBE156_WIDTH(1),\n.C_PROBE157_WIDTH(1),\n.C_PROBE158_WIDTH(1),\n.C_PROBE159_WIDTH(1),\n.C_PROBE160_WIDTH(1),\n.C_PROBE161_WIDTH(1),\n.C_PROBE162_WIDTH(1),\n.C_PROBE163_WIDTH(1),\n.C_PROBE164_WIDTH(1),\n.C_PROBE165_WIDTH(1),\n.C_PROBE166_WIDTH(1),\n.C_PROBE167_WIDTH(1),\n.C_PROBE168_WIDTH(1),\n.C_PROBE169_WIDTH(1),\n.C_PROBE170_WIDTH(1),\n.C_PROBE171_WIDTH(1),\n.C_PROBE172_WIDTH(1),\n.C_PROBE173_WIDTH(1),\n.C_PROBE174_WIDTH(1),\n.C_PROBE175_WIDTH(1),\n.C_PROBE176_WIDTH(1),\n.C_PROBE177_WIDTH(1),\n.C_PROBE178_WIDTH(1),\n.C_PROBE179_WIDTH(1),\n.C_PROBE180_WIDTH(1),\n.C_PROBE181_WIDTH(1),\n.C_PROBE182_WIDTH(1),\n.C_PROBE183_WIDTH(1),\n.C_PROBE184_WIDTH(1),\n.C_PROBE185_WIDTH(1),\n.C_PROBE186_WIDTH(1),\n.C_PROBE187_WIDTH(1),\n.C_PROBE188_WIDTH(1),\n.C_PROBE189_WIDTH(1),\n.C_PROBE190_WIDTH(1),\n.C_PROBE191_WIDTH(1),\n.C_PROBE192_WIDTH(1),\n.C_PROBE193_WIDTH(1),\n.C_PROBE194_WIDTH(1),\n.C_PROBE195_WIDTH(1),\n.C_PROBE196_WIDTH(1),\n.C_PROBE197_WIDTH(1),\n.C_PROBE198_WIDTH(1),\n.C_PROBE199_WIDTH(1),\n.C_PROBE200_WIDTH(1),\n.C_PROBE201_WIDTH(1),\n.C_PROBE202_WIDTH(1),\n.C_PROBE203_WIDTH(1),\n.C_PROBE204_WIDTH(1),\n.C_PROBE205_WIDTH(1),\n.C_PROBE206_WIDTH(1),\n.C_PROBE207_WIDTH(1),\n.C_PROBE208_WIDTH(1),\n.C_PROBE209_WIDTH(1),\n.C_PROBE210_WIDTH(1),\n.C_PROBE211_WIDTH(1),\n.C_PROBE212_WIDTH(1),\n.C_PROBE213_WIDTH(1),\n.C_PROBE214_WIDTH(1),\n.C_PROBE215_WIDTH(1),\n.C_PROBE216_WIDTH(1),\n.C_PROBE217_WIDTH(1),\n.C_PROBE218_WIDTH(1),\n.C_PROBE219_WIDTH(1),\n.C_PROBE220_W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U_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT(1),\n.C_PROBE275_MU_CNT(1),\n.C_PROBE276_MU_CNT(1),\n.C_PROBE277_MU_CNT(1),\n.C_PROBE278_MU_CNT(1),\n.C_PROBE279_MU_CNT(1),\n.C_PROBE280_MU_CNT(1),\n.C_PROBE281_MU_CNT(1),\n.C_PROBE282_MU_CNT(1),\n.C_PROBE283_MU_CNT(1),\n.C_PROBE284_MU_CNT(1),\n.C_PROBE285_MU_CNT(1),\n.C_PROBE286_MU_CNT(1),\n.C_PROBE287_MU_CNT(1),\n.C_PROBE288_MU_CNT(1),\n.C_PROBE289_MU_CNT(1),\n.C_PROBE290_MU_CNT(1),\n.C_PROBE291_MU_CNT(1),\n.C_PROBE292_MU_CNT(1),\n.C_PROBE293_MU_CNT(1),\n.C_PROBE294_MU_CNT(1),\n.C_PROBE295_MU_CNT(1),\n.C_PROBE296_MU_CNT(1),\n.C_PROBE297_MU_CNT(1),\n.C_PROBE298_MU_CNT(1),\n.C_PROBE299_MU_CNT(1),\n.C_PROBE300_MU_CNT(1),\n.C_PROBE301_MU_CNT(1),\n.C_PROBE302_MU_CNT(1),\n.C_PROBE303_MU_CNT(1),\n.C_PROBE304_MU_CNT(1),\n.C_PROBE305_MU_CNT(1),\n.C_PROBE306_MU_CNT(1),\n.C_PROBE307_MU_CNT(1),\n.C_PROBE308_MU_CNT(1),\n.C_PROBE309_MU_CNT(1),\n.C_PROBE310_MU_CNT(1),\n.C_PROBE311_MU_CNT(1),\n.C_PROBE312_MU_CNT(1),\n.C_PROBE313_MU_CNT(1),\n.C_PROBE314_MU_CNT(1),\n.C_PROBE315_MU_CNT(1),\n.C_PROBE316_MU_CNT(1),\n.C_PROBE317_MU_CNT(1),\n.C_PROBE318_MU_CNT(1),\n.C_PROBE319_MU_CNT(1),\n.C_PROBE320_MU_CNT(1),\n.C_PROBE321_MU_CNT(1),\n.C_PROBE322_MU_CNT(1),\n.C_PROBE323_MU_CNT(1),\n.C_PROBE324_MU_CNT(1),\n.C_PROBE325_MU_CNT(1),\n.C_PROBE326_MU_CNT(1),\n.C_PROBE327_MU_CNT(1),\n.C_PROBE328_MU_CNT(1),\n.C_PROBE329_MU_CNT(1),\n.C_PROBE330_MU_CNT(1),\n.C_PROBE331_MU_CNT(1),\n.C_PROBE332_MU_CNT(1),\n.C_PROBE333_MU_CNT(1),\n.C_PROBE334_MU_CNT(1),\n.C_PROBE335_MU_CNT(1),\n.C_PROBE336_MU_CNT(1),\n.C_PROBE337_MU_CNT(1),\n.C_PROBE338_MU_CNT(1),\n.C_PROBE339_MU_CNT(1),\n.C_PROBE340_MU_CNT(1),\n.C_PROBE341_MU_CNT(1),\n.C_PROBE342_MU_CNT(1),\n.C_PROBE343_MU_CNT(1),\n.C_PROBE344_MU_CNT(1),\n.C_PROBE345_MU_CNT(1),\n.C_PROBE346_MU_CNT(1),\n.C_PROBE347_MU_CNT(1),\n.C_PROBE348_MU_CNT(1),\n.C_PROBE349_MU_CNT(1),\n.C_PROBE350_MU_CNT(1),\n.C_PROBE351_MU_CNT(1),\n.C_PROBE352_MU_CNT(1),\n.C_PROBE353_MU_CNT(1),\n.C_PROBE354_MU_CNT(1),\n.C_PROBE355_MU_CNT(1),\n.C_PROBE356_MU_CNT(1),\n.C_PROBE357_MU_CNT(1),\n.C_PROBE358_MU_CNT(1),\n.C_PROBE359_MU_CNT(1),\n.C_PROBE360_MU_CNT(1),\n.C_PROBE361_MU_CNT(1),\n.C_PROBE362_MU_CNT(1),\n.C_PROBE363_MU_CNT(1),\n.C_PROBE364_MU_CNT(1),\n.C_PROBE365_MU_CNT(1),\n.C_PROBE366_MU_CNT(1),\n.C_PROBE367_MU_CNT(1),\n.C_PROBE368_MU_CNT(1),\n.C_PROBE369_MU_CNT(1),\n.C_PROBE370_MU_CNT(1),\n.C_PROBE371_MU_CNT(1),\n.C_PROBE372_MU_CNT(1),\n.C_PROBE373_MU_CNT(1),\n.C_PROBE374_MU_CNT(1),\n.C_PROBE375_MU_CNT(1),\n.C_PROBE376_MU_CNT(1),\n.C_PROBE377_MU_CNT(1),\n.C_PROBE378_MU_CNT(1),\n.C_PROBE379_MU_CNT(1),\n.C_PROBE380_MU_CNT(1),\n.C_PROBE381_MU_CNT(1),\n.C_PROBE382_MU_CNT(1),\n.C_PROBE383_MU_CNT(1),\n.C_PROBE384_MU_CNT(1),\n.C_PROBE385_MU_CNT(1),\n.C_PROBE386_MU_CNT(1),\n.C_PROBE387_MU_CNT(1),\n.C_PROBE388_MU_CNT(1),\n.C_PROBE389_MU_CNT(1),\n.C_PROBE390_MU_CNT(1),\n.C_PROBE391_MU_CNT(1),\n.C_PROBE392_MU_CNT(1),\n.C_PROBE393_MU_CNT(1),\n.C_PROBE394_MU_CNT(1),\n.C_PROBE395_MU_CNT(1),\n.C_PROBE396_MU_CNT(1),\n.C_PROBE397_MU_CNT(1),\n.C_PROBE398_MU_CNT(1),\n.C_PROBE399_MU_CNT(1),\n.C_PROBE400_MU_CNT(1),\n.C_PROBE401_MU_CNT(1),\n.C_PROBE402_MU_CNT(1),\n.C_PROBE403_MU_CNT(1),\n.C_PROBE404_MU_CNT(1),\n.C_PROBE405_MU_CNT(1),\n.C_PROBE406_MU_CNT(1),\n.C_PROBE407_MU_CNT(1),\n.C_PROBE408_MU_CNT(1),\n.C_PROBE409_MU_CNT(1),\n.C_PROBE410_MU_CNT(1),\n.C_PROBE411_MU_CNT(1),\n.C_PROBE412_MU_CNT(1),\n.C_PROBE413_MU_CNT(1),\n.C_PROBE414_MU_CNT(1),\n.C_PROBE415_MU_CNT(1),\n.C_PROBE416_MU_CNT(1),\n.C_PROBE417_MU_CNT(1),\n.C_PROBE418_MU_CNT(1),\n.C_PROBE419_MU_CNT(1),\n.C_PROBE420_MU_CNT(1),\n.C_PROBE421_MU_CNT(1),\n.C_PROBE422_MU_CNT(1),\n.C_PROBE423_MU_CNT(1),\n.C_PROBE424_MU_CNT(1),\n.C_PROBE425_MU_CNT(1),\n.C_PROBE426_MU_CNT(1),\n.C_PROBE427_MU_CNT(1),\n.C_PROBE428_MU_CNT(1),\n.C_PROBE429_MU_CNT(1),\n.C_PROBE430_MU_CNT(1),\n.C_PROBE431_MU_CNT(1),\n.C_PROBE432_MU_CNT(1),\n.C_PROBE433_MU_CNT(1),\n.C_PROBE434_MU_CNT(1),\n.C_PROBE435_MU_CNT(1),\n.C_PROBE436_MU_CNT(1),\n.C_PROBE437_MU_CNT(1),\n.C_PROBE438_MU_CNT(1),\n.C_PROBE439_MU_CNT(1),\n.C_PROBE440_MU_CNT(1),\n.C_PROBE441_MU_CNT(1),\n.C_PROBE442_MU_CNT(1),\n.C_PROBE443_MU_CNT(1),\n.C_PROBE444_MU_CNT(1),\n.C_PROBE445_MU_CNT(1),\n.C_PROBE446_MU_CNT(1),\n.C_PROBE447_MU_CNT(1),\n.C_PROBE448_MU_CNT(1),\n.C_PROBE449_MU_CNT(1),\n.C_PROBE450_MU_CNT(1),\n.C_PROBE451_MU_CNT(1),\n.C_PROBE452_MU_CNT(1),\n.C_PROBE453_MU_CNT(1),\n.C_PROBE454_MU_CNT(1),\n.C_PROBE455_MU_CNT(1),\n.C_PROBE456_MU_CNT(1),\n.C_PROBE457_MU_CNT(1),\n.C_PROBE458_MU_CNT(1),\n.C_PROBE459_MU_CNT(1),\n.C_PROBE460_MU_CNT(1),\n.C_PROBE461_MU_CNT(1),\n.C_PROBE462_MU_CNT(1),\n.C_PROBE463_MU_CNT(1),\n.C_PROBE464_MU_CNT(1),\n.C_PROBE465_MU_CNT(1),\n.C_PROBE466_MU_CNT(1),\n.C_PROBE467_MU_CNT(1),\n.C_PROBE468_MU_CNT(1),\n.C_PROBE469_MU_CNT(1),\n.C_PROBE470_MU_CNT(1),\n.C_PROBE471_MU_CNT(1),\n.C_PROBE472_MU_CNT(1),\n.C_PROBE473_MU_CNT(1),\n.C_PROBE474_MU_CNT(1),\n.C_PROBE475_MU_CNT(1),\n.C_PROBE476_MU_CNT(1),\n.C_PROBE477_MU_CNT(1),\n.C_PROBE478_MU_CNT(1),\n.C_PROBE479_MU_CNT(1),\n.C_PROBE480_MU_CNT(1),\n.C_PROBE481_MU_CNT(1),\n.C_PROBE482_MU_CNT(1),\n.C_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1),\n.C_PROBE691_MU_CNT(1),\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synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4261}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_master #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_SUPPORTS_NARROW = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1,\n   parameter [C_AXI_ADDR_WIDTH-1:0] C_AXI_ADDR = 0,  // Base address\n   parameter integer C_NUM_ADDR = 1,  // Number of address iterations; range 1..2**16 (fixed increment = 32'h10000\n   parameter integer C_NUM_ID = 1,  // Number of ID iterations; range 1..2**C_ID_WIDTH (base = 0; fixed increment = 1)\n   parameter integer C_NUM_LEN = 1,  // Number of LEN iterations; range 1..9 (base = 0; value = 2**i - 1)\n   parameter integer C_NUM_TRANS = 1  // Number of transactions; range >=1 (read and write)\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_awvalid,\n  input  wire                            m_axi_awready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_awburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_awlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_awlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_awid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]    m_axi_awuser = 'b0,\n  /**************** Write Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_wid,\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]      m_axi_wdata,\n  (* dont_touch=\"true\" *) output reg [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb = {(C_AXI_DATA_WIDTH/8){1'b1}},\n  (* dont_touch=\"true\" *) output wire                             m_axi_wvalid,\n  input  wire                            m_axi_wready,\n  (* dont_touch=\"true\" *) output wire                             m_axi_wlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]     m_axi_wuser = 'b0,\n  /**************** Write Response Channel Signals ****************/\n  input  wire [2-1:0]                    m_axi_bresp,\n  input  wire                            m_axi_bvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_bready,\n  input  wire [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]     m_axi_buser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_bid,\n  /**************** Read Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_arvalid,\n  input  wire                            m_axi_arready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_arburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_arlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_arlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_arid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]    m_axi_aruser = 'b0,\n  /**************** Read Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]      m_axi_rdata,\n  input  wire [2-1:0]                    m_axi_rresp,\n  input  wire                            m_axi_rvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_rready,\n  input  wire                            m_axi_rlast,\n  input  wire [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]     m_axi_ruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_rid,\n  /**************** System Signals ****************/\n  input  wire                            aclk,\n  input  wire                            aresetn\n  );\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n  localparam integer  P_NUM_ID_LOG = f_ceil_log2(C_NUM_ID);\n  localparam integer  P_NUM_ADDR_LOG = f_ceil_log2(C_NUM_ADDR);\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL==0 ? 8 : C_AXI_PROTOCOL==1 ? 4 : 1);\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer               P_M_AXI_DATA_BYTES = (C_AXI_DATA_WIDTH / 8);\n  localparam integer               P_M_AXI_DONE_WIDTH = f_ceil_log2(C_NUM_TRANS<2?2:C_NUM_TRANS);\n  localparam integer               P_M_AXI_SIZE = f_ceil_log2(C_AXI_DATA_WIDTH)-3;\n\n  /**************** Internal Wires/Regs - Global ****************/\n   wire                            done;\n    wire                            dummy ;\n  reg                         done_i;\n  reg                         done_sel;\n  wire                         done_cycle;\n  reg                          done_d1 = 1'b0;\n  reg                   areset = 1'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] arcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] rcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [3:0]                    acc_r_i = 4'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] awcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] wcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] bcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [2:0]                    acc_b_i = 3'b0;\n\n  // Register Reset\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    \n    /**************** Internal Wires/Regs - Read Channels ****************/\n    wire                         read_xaction_done_i;\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_arid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_ADDR_WIDTH:0]      araddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  arprot_i = 3'b0;\n    reg [3-1:0]                  arsize_i = 3'b0;\n    reg [2-1:0]                  arburst_i = 2'b0;\n    reg [4-1:0]                  arcache_i = 4'b0;\n    reg [2-1:0]                  arlock_i = 2'b0;\n    reg [P_LEN_WIDTH-1:0]     arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [4-1:0]                  arqos_i = 4'b0;\n    reg [P_ID_WIDTH-1:0]        arid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [2-1:0]                  rresp_i = 2'b00;\n    reg [C_AXI_RUSER_WIDTH:0]   ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      rid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_arvalid_i = 1'b0;\n    reg                        m_axi_rready_i = 1'b0;\n    reg [P_NUM_ADDR_LOG:0]    araddr_cnt = 0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign read_xaction_done_i = m_axi_rvalid && m_axi_rready_i && ((C_AXI_PROTOCOL==2)?1'b1:m_axi_rlast);\n    assign m_axi_arvalid = m_axi_arvalid_i;\n    assign m_axi_rready = m_axi_rready_i;\n    assign m_axi_araddr = m_axi_araddr_i;\n    assign m_axi_arlen = m_axi_arlen_i;\n    always @(posedge aclk) begin\n      m_axi_arprot <= dummy ? arprot_i : 3'b000;\n      m_axi_arsize <= dummy ? arsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_arburst <= dummy ? arburst_i : 2'b01;\n      m_axi_arlock <= dummy ? arlock_i : 1'b0;\n      m_axi_arcache <= dummy ? arcache_i : 4'h3;\n      m_axi_arqos <= dummy  ? arqos_i : 4'h0;\n      m_axi_aruser <= dummy ? aruser_i : 0;\n    end\n  \n    //**********************************************\n    // Read Channel: ARVALID, ARADDR, ARLEN, RREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_arvalid_i <= 1'b0;\n        arcnt_i <= C_NUM_TRANS;\n        m_axi_arlen_i <= 0;\n        m_axi_araddr_i <= C_AXI_ADDR;\n        m_axi_arid_i <= 1;\n        araddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_arready & m_axi_arvalid_i) begin\n          arcnt_i <= arcnt_i - 1;\n          if (araddr_cnt == 1) begin\n            m_axi_araddr_i <= dummy ? araddr_i : C_AXI_ADDR;\n            araddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_araddr_i <= m_axi_araddr_i + 32'h10000;\n            araddr_cnt <= araddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_arlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_arlen_i <= dummy ? arlen_i : 0;\n          end else begin\n            m_axi_arlen_i <= (m_axi_arlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_arid_i == C_NUM_ID)) begin\n            m_axi_arid <= dummy ? arid_i : 0;\n            m_axi_arid_i <= 1;\n          end else begin\n            m_axi_arid <= m_axi_arid_i;\n            m_axi_arid_i <= m_axi_arid_i + 1;\n          end\n          if (arcnt_i == 1) begin\n            m_axi_arvalid_i <= 1'b0;\n          end\n        end else if (arcnt_i != 0) begin\n          m_axi_arvalid_i <= 1'b1;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      araddr_i <= {araddr_i, ~araddr_i[C_AXI_ADDR_WIDTH]};\n      arprot_i <= {arprot_i, ~arprot_i[3-1]};\n      arlen_i <= {arlen_i, ~arlen_i[P_LEN_WIDTH-1]};\n      arsize_i <= {arsize_i, ~arsize_i[3-1]};\n      arburst_i <= {arburst_i, ~arburst_i[2-1]};\n      arlock_i <= {arlock_i, ~arlock_i[2-1]};\n      arcache_i <= {arcache_i, ~arcache_i[4-1]};\n      arqos_i <= {arqos_i, ~arqos_i[4-1]};\n      aruser_i <= {aruser_i, ~aruser_i[C_AXI_ARUSER_WIDTH]};\n      arid_i <= {arid_i, ~arid_i[P_ID_WIDTH-1]};\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        m_axi_rready_i <= 1'b0;\n        rcnt_i <= C_NUM_TRANS;\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        rresp_i <= {2{1'b0}};\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n        rid_i <= {P_ID_WIDTH{1'b0}};\n        acc_r_i <= 4'b0;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_rvalid & m_axi_rready_i) begin\n          m_axi_rready_i <= 1'b0;\n          rdata_i <= m_axi_rdata;\n            acc_r_i[0] <= rdata_i[0];\n          rresp_i <= m_axi_rresp;\n            acc_r_i[1] <= rresp_i[0];\n          ruser_i <= m_axi_ruser;\n            acc_r_i[2] <= ruser_i[0];\n          rid_i <= m_axi_rid;\n            acc_r_i[3] <= rid_i[0];\n          if (m_axi_rlast) begin\n            rcnt_i <= rcnt_i - 1;\n          end\n        end else begin\n          rdata_i <= rdata_i>>1;\n          rresp_i <= rresp_i>>1;\n          ruser_i <= ruser_i>>1;\n          rid_i <= rid_i>>1;\n          acc_r_i <= acc_r_i>>1;\n          if (m_axi_rvalid) begin\n            m_axi_rready_i <= 1'b1;\n          end\n        end\n      end\n    end\n    \n    assign dummy = rdata_i[0];\n    \n    \n\n    /**************** Internal Wires/Regs - Write Channels ****************/\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_awid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [8-1:0]                  xfer_w_i = 8'h00;\n    wire                         write_burst_done_i;\n    reg [C_AXI_ADDR_WIDTH:0]      awaddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  awprot_i = 3'b0;\n    reg [P_LEN_WIDTH-1:0]     awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [3-1:0]                  awsize_i = 3'b0;\n    reg [2-1:0]                  awburst_i = 2'b0;\n    reg [4-1:0]                  awcache_i = 4'b0;\n    reg [2-1:0]                  awlock_i = 2'b0;\n    reg [4-1:0]                  awqos_i = 4'b0;\n    reg [P_ID_WIDTH:0]        awid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_AWUSER_WIDTH:0]    awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg [P_M_AXI_DATA_BYTES-1:0] wstrb_i = {P_M_AXI_DATA_BYTES{1'b1}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]        wid_i = {P_ID_WIDTH{1'b0}};\n    reg [2-1:0]                  bresp_i = 2'b00;\n    reg [C_AXI_BUSER_WIDTH:0]   buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      bid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_awvalid_i = 1'b0;\n    reg                        m_axi_wvalid_i = 1'b0;\n    reg                        m_axi_bready_i = 1'b0;\n    reg                        m_axi_wlast_i = 1'b0;\n    reg                        m_axi_wid_i = {P_ID_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]     wlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [P_NUM_ADDR_LOG:0]    awaddr_cnt = 0;\n  \n    /**************** Assign Write Channel Outputs ****************/\n    assign m_axi_wdata = {wdata_i, done};\n    assign write_burst_done_i = m_axi_wready && m_axi_wvalid_i && ((C_AXI_PROTOCOL==2) || m_axi_wlast_i);\n    assign m_axi_awvalid = m_axi_awvalid_i;\n    assign m_axi_wvalid = m_axi_wvalid_i;\n    assign m_axi_bready = m_axi_bready_i;\n    assign m_axi_wlast = m_axi_wlast_i;\n    assign m_axi_awaddr = m_axi_awaddr_i;\n    assign m_axi_awlen = m_axi_awlen_i;\n    assign m_axi_wid = m_axi_wid_i;\n    always @(posedge aclk) begin\n      m_axi_awprot <= dummy ? awprot_i : 3'b000;\n      m_axi_awsize <= dummy ? awsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_awburst <= dummy ? awburst_i : 2'b01;\n      m_axi_awlock <= dummy ? awlock_i : 1'b0;\n      m_axi_awcache <= dummy ? awcache_i : 4'h3;\n      m_axi_awqos <= dummy ? awqos_i : 4'h0;\n      m_axi_wstrb <= dummy ? wstrb_i : {P_M_AXI_DATA_BYTES{1'b1}};\n      m_axi_awuser <= dummy ?  awuser_i : 0;\n      m_axi_wuser <= dummy ?  wuser_i : 0;\n    end\n  \n    //**********************************************\n    // Write Channel: AWVALID, AWADDR, AWLEN, WVALID, WLAST, BREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_awvalid_i <= 1'b0;\n        m_axi_wvalid_i <= 1'b0;\n        awcnt_i <= C_NUM_TRANS;\n        wcnt_i <= C_NUM_TRANS;\n        xfer_w_i <= 8'h00;\n        m_axi_awlen_i <= 0;\n        m_axi_awaddr_i <= C_AXI_ADDR;\n        m_axi_awid_i <= 1;\n        m_axi_wid_i <= 0;\n        m_axi_wlast_i <= 1'b0;\n        wlen_i <= 0;\n        wid_i <= 0;\n        awaddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_awvalid_i <= 1'b0;\n          awcnt_i <= awcnt_i - 1;\n          if (awaddr_cnt == 1) begin\n            m_axi_awaddr_i <= dummy ? awaddr_i : C_AXI_ADDR;\n            awaddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_awaddr_i <= m_axi_awaddr_i + 32'h10000;\n            awaddr_cnt <= awaddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_awlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_awlen_i <= dummy ? awlen_i : 0;\n          end else begin\n            m_axi_awlen_i <= (m_axi_awlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_awid_i == C_NUM_ID)) begin\n            m_axi_awid <= dummy ? awid_i : 0;\n            m_axi_awid_i <= 1;\n          end else begin\n            m_axi_awid <= m_axi_awid_i;\n            m_axi_awid_i <= m_axi_awid_i + 1;\n          end\n        end else if (~m_axi_wvalid_i) begin\n          if (awcnt_i != 0) begin\n            m_axi_awvalid_i <= 1'b1;\n          end\n        end\n  \n        /**************** Write Data Channel ****************/\n\n        if (m_axi_wready && m_axi_wvalid_i) begin\n          xfer_w_i <= xfer_w_i - 1'b1;\n          if (m_axi_wlast_i) begin\n            m_axi_wvalid_i <= 1'b0;\n            wcnt_i <= wcnt_i - 1'b1;\n          end else begin\n            m_axi_wlast_i <=  (xfer_w_i == 1);\n          end\n        end else if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_wvalid_i <= 1'b1;\n          xfer_w_i <= m_axi_awlen_i;\n          m_axi_wlast_i <= (m_axi_awlen_i==0);\n          m_axi_wid_i <= m_axi_awid_i;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: WDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        wdata_i <= (m_axi_wvalid_i && m_axi_wready) ? {wdata_i[C_AXI_DATA_WIDTH-2 : 0], ~wdata_i[C_AXI_DATA_WIDTH-1]} : wdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      awaddr_i <= {awaddr_i, ~awaddr_i[C_AXI_ADDR_WIDTH]};\n      awprot_i <= {awprot_i[3-2:0], ~awprot_i[3-1]};\n      wstrb_i <= {wstrb_i, ~wstrb_i[C_AXI_DATA_WIDTH/8-1]};\n      awlen_i <= {awlen_i, ~awlen_i[P_LEN_WIDTH-1]};\n      awsize_i <= {awsize_i, ~awsize_i[3-1]};\n      awburst_i <= {awburst_i, ~awburst_i[2-1]};\n      awlock_i <= {awlock_i, ~awlock_i[2-1]};\n      awcache_i <= {awcache_i, ~awcache_i[4-1]};\n      awqos_i <= {awqos_i, ~awqos_i[4-1]};\n      awid_i <= {awid_i, ~awid_i[P_ID_WIDTH-1]};\n      awuser_i <= {awuser_i, ~awuser_i[C_AXI_AWUSER_WIDTH]};\n      wuser_i <= {wuser_i, ~wuser_i[C_AXI_WUSER_WIDTH]};\n    end\n  \n    //**********************************************\n    // Write Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_bready_i <= 1'b0;\n        bcnt_i <= C_NUM_TRANS;\n        bresp_i <= {2{1'b0}};\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n        bid_i <= {P_ID_WIDTH{1'b0}};\n        acc_b_i <= 3'b0;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_bvalid & m_axi_bready_i) begin\n          m_axi_bready_i <= 1'b0;\n          bresp_i <= m_axi_bresp;\n            acc_b_i[0] <= bresp_i[0];\n          buser_i <= m_axi_buser;\n            acc_b_i[1] <= buser_i[0];\n          bid_i <= m_axi_bid;\n            acc_b_i[2] <= bid_i[0];\n          bcnt_i <= bcnt_i - 1;\n        end else begin\n          bresp_i <= bresp_i>>1;\n          buser_i <= buser_i>>1;\n          bid_i <= bid_i>>1;\n          acc_b_i <= acc_b_i>>1;\n          if (m_axi_bvalid) begin\n            m_axi_bready_i <= 1'b1;\n          end\n        end\n      end\n    end\n\n\n  //**********************************************\n  // Assert Done\n  //**********************************************\n  always @(posedge aclk) begin\n    if (~aresetn) begin\n      done_d1 <= 1'b0;\n    end else begin\n      done_d1 <= done_i;\n    end\n  end\n\n  assign done = done_sel ? done_i : done_d1;\n  assign done_cycle = done_i & ~done_d1;\n  \n  always @ * begin\n    if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_readonly_done\n       done_i = rcnt_i==0;\n       done_sel = acc_r_i[0];\n    end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_writeonly_done\n       done_i = bcnt_i==0;\n       done_sel = acc_b_i[0];\n    end else begin : gen_readwrite_done\n       done_i = (rcnt_i==0) && (bcnt_i==0);\n       done_sel = acc_r_i[0] ^ acc_b_i[0];\n    end\n  end\n  \nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n  input  wire [3-1:0]                   s_axi_awprot,\n  input  wire                           s_axi_awvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_awready,\n  input  wire [3-1:0]                   s_axi_awsize,\n  input  wire [2-1:0]                   s_axi_awburst,\n  input  wire [4-1:0]                   s_axi_awcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_awlen,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_awlock,\n  input  wire [4-1:0]                   s_axi_awqos,\n  input  wire [4-1:0]                   s_axi_awregion,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_awid,\n  input  wire [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]   s_axi_awuser,\n  /**************** Write Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n  input  wire                           s_axi_wvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_wready,\n  input  wire                           s_axi_wlast,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_wid,\n  input  wire [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]    s_axi_wuser,\n  /**************** Write Response Channel Signals ****************/\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_bresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_bvalid,\n  input  wire                           s_axi_bready,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]    s_axi_buser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_bid = 'b0,\n  /**************** Read Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n  input  wire [3-1:0]                   s_axi_arprot,\n  input  wire                           s_axi_arvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_arready,\n  input  wire [3-1:0]                   s_axi_arsize,\n  input  wire [2-1:0]                   s_axi_arburst,\n  input  wire [4-1:0]                   s_axi_arcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_arlock,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_arlen,\n  input  wire [4-1:0]                   s_axi_arqos,\n  input  wire [4-1:0]                   s_axi_arregion,\n  input  wire [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]   s_axi_aruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_arid,\n  /**************** Read Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_rresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rvalid,\n  input  wire                           s_axi_rready,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]    s_axi_ruser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_rid = 'b0,\n  /**************** System Signals ****************/\n  input  wire                           aclk,\n  input  wire                           aresetn\n   );\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL == 1) ? 4 : 8;\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer P_S_AXI_DATA_BYTES = 32/8;\n  localparam integer P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n\n  /**************** Internal Wires/Regs - Global ****************/\n  reg                   areset = 1'b0;\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    /**************** Internal Wires/Regs - Read Channels ****************/\n    reg [8-1:0]                   xfer_r_cnt = 8'h00;\n    reg [16-1:0]                  arcnt_i = 16'h0000;\n    wire                          read_xaction_done_i;\n    reg [C_AXI_DATA_WIDTH-1:0]     rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]      arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg                           arvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     araddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   arprot_i = 3'b000;\n    reg [3-1:0]                   arsize_i = 3'b000;\n    reg [2-1:0]                   arburst_i = 2'b00;\n    reg [4-1:0]                   arcache_i = 4'b0000;\n    reg [1-1:0]     arlock_i = 1'b0;\n    reg [4-1:0]                   arqos_i = 4'b0000;\n    reg [4-1:0]                   arregion_i = 4'b0000;\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_RUSER_WIDTH:0]     ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_ar_i = 9'b0;\n    reg                           s_axi_rvalid_i = 1'b0;\n    reg                           s_axi_arready_i = 1'b0;\n    reg                           s_axi_rlast_i = 1'b0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign s_axi_rdata = rdata_i;\n    assign read_xaction_done_i = (s_axi_rready && s_axi_rvalid_i && s_axi_rlast_i);\n    assign s_axi_rvalid = s_axi_rvalid_i;\n    assign s_axi_arready = s_axi_arready_i;\n    assign s_axi_rlast = s_axi_rlast_i;\n    //**********************************************\n    // Read Channel: ARREADY, RVALID, RLAST, RID\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        xfer_r_cnt <= 8'h00;\n        arcnt_i <= 16'h0000;\n        arlen_i <= {P_LEN_WIDTH{1'b0}};\n        s_axi_rlast_i <= 1'b0;\n      end else begin\n        /**************** Read Address Channel ****************/\n        // arready\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_arready_i <= 1'b0;\n          arcnt_i <= arcnt_i + 1'b1;\n        end else if (~s_axi_rvalid_i) begin\n          s_axi_arready_i <= 1'b1;\n        end\n  \n        /**************** Read Data Channel ****************/\n        // rvalid\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_rvalid_i <= 1'b1;\n          s_axi_rid <= s_axi_arid;\n          s_axi_ruser <= ruser_i;\n        end else if(read_xaction_done_i) begin\n          s_axi_rvalid_i <= 1'b0;\n        end\n  \n        // rlast\n        if(s_axi_rready && s_axi_rvalid_i) begin\n          xfer_r_cnt <= xfer_r_cnt - 1;\n          if(xfer_r_cnt == 1) begin\n            s_axi_rlast_i <= 1'b1;\n          end\n        end else if(s_axi_arready_i && s_axi_arvalid) begin\n          xfer_r_cnt <= s_axi_arlen;\n          s_axi_rlast_i <= (s_axi_arlen==0);\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Read Channel: RDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        rdata_i <= (s_axi_rready && s_axi_rvalid_i) ? {rdata_i[C_AXI_DATA_WIDTH-2 : 0], ~rdata_i[C_AXI_DATA_WIDTH-1]} : rdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_rresp <= {2{1'b0}};\n      end else if (~s_axi_rvalid_i) begin\n        s_axi_rresp <= {acc_ar_i[0], 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n      end else begin\n        ruser_i <= (s_axi_arready_i && s_axi_arvalid) ? {ruser_i, ~ruser_i[C_AXI_RUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        araddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        arprot_i <= {3{1'b0}};\n        arsize_i <= {3{1'b0}};\n        arburst_i <= {2{1'b0}};\n        arcache_i <= {4{1'b0}};\n        arlock_i <= {1{1'b0}};\n        arqos_i <= {4{1'b0}};\n        arregion_i <= {4{1'b0}};\n        aruser_i <= {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n        acc_ar_i <= 9'b0;\n      end else if (s_axi_arvalid) begin\n        // Register Inputs\n        araddr_i <= s_axi_araddr;\n          acc_ar_i[0] <= araddr_i[0];\n        arprot_i <= s_axi_arprot;\n          acc_ar_i[1] <= arprot_i[0];\n        arsize_i <= s_axi_arsize;\n          acc_ar_i[2] <= arsize_i[0];\n        arburst_i <= s_axi_arburst;\n          acc_ar_i[3] <= arburst_i[0];\n        arcache_i <= s_axi_arcache;\n          acc_ar_i[4] <= arcache_i[0];\n        arlock_i <= s_axi_arlock;\n          acc_ar_i[5] <= arlock_i[0];\n        arqos_i <= s_axi_arqos;\n          acc_ar_i[6] <= arqos_i[0];\n        arregion_i <= s_axi_arregion;\n          acc_ar_i[7] <= arregion_i[0];\n        aruser_i <= s_axi_aruser;\n          acc_ar_i[8] <= aruser_i[0];\n      end else begin\n        araddr_i <= araddr_i>>1;\n        arprot_i <= arprot_i>>1;\n        arsize_i <= arsize_i>>1;\n        arburst_i <= arburst_i>>1;\n        arcache_i <= arcache_i>>1;\n        arlock_i <= arlock_i>>1;\n        arqos_i <= arqos_i>>1;\n        arregion_i <= arregion_i>>1;\n        aruser_i <= aruser_i>>1;\n        acc_ar_i <= acc_ar_i>>1;\n      end\n    end\n  \n  \n    /**************** Internal Wires/Regs - Write Channels ****************/\n    wire                          write_burst_done_i;\n    reg [16-1:0]                  awcnt_i = 16'h0000;\n    reg                           awvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     awaddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   awprot_i = 3'b000;\n    reg [3-1:0]                   awsize_i = 3'b000;\n    reg [2-1:0]                   awburst_i = 2'b00;\n    reg [4-1:0]                   awcache_i = 4'b0000;\n    reg [P_LEN_WIDTH-1:0]      awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [1-1:0]     awlock_i = 1'b0;\n    reg [4-1:0]                   awqos_i = 4'b0000;\n    reg [4-1:0]                   awregion_i = 4'b0000;\n    reg [C_AXI_AWUSER_WIDTH:0]     awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg                           wvalid_i = 1'b0;\n    reg [C_AXI_DATA_WIDTH-1:0]     wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH/8-1:0]   wstrb_i = {(C_AXI_DATA_WIDTH/8){1'b0}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_BUSER_WIDTH:0]     buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_aw_i = 9'b0;\n    reg [3:0]                     acc_w_i = 4'b0;\n    reg                           s_axi_bvalid_i = 1'b0;\n    reg                           s_axi_awready_i = 1'b0;\n    reg                           s_axi_wready_i = 1'b0;\n    /**************** Assign Write Channel Outputs ****************/\n    assign write_burst_done_i =s_axi_wready_i && s_axi_wvalid && ((C_AXI_PROTOCOL == 2) ? 1'b1 : s_axi_wlast);\n    assign s_axi_bvalid = s_axi_bvalid_i;\n    assign s_axi_awready = s_axi_awready_i;\n    assign s_axi_wready = s_axi_wready_i;\n  \n    //**********************************************\n    // Write Channel: AWREADY, WREADY, BVALID, BID\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awcnt_i <= 16'h0000;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        /**************** Write Address Channel ****************/\n        // awready\n        if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_awready_i <= 1'b0;\n          awcnt_i <= awcnt_i + 1'b1;\n          s_axi_bid <= s_axi_awid;\n          s_axi_buser <= buser_i;\n        end else if(~s_axi_wready_i & ~s_axi_bvalid_i) begin\n          s_axi_awready_i <= 1'b1;\n        end\n  \n        /**************** Write Data Channel ****************/\n        // wready\n        if(write_burst_done_i) begin\n          s_axi_wready_i <= 1'b0;\n        end else if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_wready_i <= 1'b1;\n        end\n  \n        /**************** Write Response Channel ****************/\n        // bvalid\n        if(write_burst_done_i) begin\n          s_axi_bvalid_i <= 1'b1;\n        end else if(s_axi_bready && s_axi_bvalid_i) begin\n          s_axi_bvalid_i <= 1'b0;\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Write Channel: BRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_bresp <= {2{1'b0}};\n      end else if (~s_axi_bvalid_i) begin\n        s_axi_bresp <= {(acc_aw_i[0] ^ acc_w_i[0]), 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: BUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (aresetn) begin\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n      end else begin\n        buser_i <= (s_axi_awready_i && s_axi_awvalid) ? {buser_i, ~buser_i[C_AXI_BUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Write Address Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awaddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        awprot_i <= {3{1'b0}};\n        awsize_i <= {3{1'b0}};\n        awburst_i <= {2{1'b0}};\n        awcache_i <= {4{1'b0}};\n        awlen_i <= {P_LEN_WIDTH{1'b0}};\n        awlock_i <= {1{1'b0}};\n        awqos_i <= {4{1'b0}};\n        awregion_i <= {4{1'b0}};\n        awuser_i <= {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n        acc_aw_i <= 9'b0;\n      end else if (s_axi_awvalid) begin\n        // Register Inputs\n        awaddr_i <= s_axi_awaddr;\n          acc_aw_i[0] <= awaddr_i[0];\n        awprot_i <= s_axi_awprot;\n          acc_aw_i[1] <= awprot_i[0];\n        awsize_i <= s_axi_awsize;\n          acc_aw_i[2] <= awsize_i[0];\n        awburst_i <= s_axi_awburst;\n          acc_aw_i[3] <= awburst_i[0];\n        awcache_i <= s_axi_awcache;\n          acc_aw_i[4] <= awcache_i[0];\n        awlock_i <= s_axi_awlock;\n          acc_aw_i[5] <= awlock_i[0];\n        awqos_i <= s_axi_awqos;\n          acc_aw_i[6] <= awqos_i[0];\n        awregion_i <= s_axi_awregion;\n          acc_aw_i[7] <= awregion_i[0];\n        awuser_i <= s_axi_awuser;\n          acc_aw_i[8] <= awuser_i[0];\n      end else begin\n        awaddr_i <= awaddr_i>>1;\n        awprot_i <= awprot_i>>1;\n        awsize_i <= awsize_i>>1;\n        awburst_i <= awburst_i>>1;\n        awcache_i <= awcache_i>>1;\n        awlock_i <= awlock_i>>1;\n        awqos_i <= awqos_i>>1;\n        awregion_i <= awregion_i>>1;\n        awuser_i <= awuser_i>>1;\n        acc_aw_i <= acc_aw_i>>1;\n      end\n    end\n  \n    //**********************************************\n    // Write Data Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        wstrb_i <= {(C_AXI_DATA_WIDTH/8){1'b0}};\n        wuser_i <= {(C_AXI_WUSER_WIDTH+1){1'b0}};\n        acc_w_i <= 4'b0;\n      end else if (s_axi_wvalid) begin\n        // Register Inputs\n        wdata_i <= s_axi_wdata;\n          acc_w_i[0] <= wdata_i[0];\n        wstrb_i <= s_axi_wstrb;\n          acc_w_i[1] <= wstrb_i[0];\n        wuser_i <= s_axi_wuser;\n          acc_w_i[2] <= wuser_i[0];\n      end else begin\n        wdata_i <= wdata_i>>1;\n        wstrb_i <= wstrb_i>>1;\n        wuser_i <= wuser_i>>1;\n        acc_w_i <= acc_w_i>>1;\n      end\n    end\n  \nendmodule\n\n\n\n//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_22_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \n(* autopipeline_module=\"yes\" *)\nmodule axi_register_slice_v2_1_22_auto_slr #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n    wire                    handshake_pipe;\n    wire                    ready_pipe;\n    wire [C_DATA_WIDTH-1:0] payload_pipe;\n    (* keep=\"true\" *)                                                                reg  s_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  s_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  s_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  s_areset_resp2 = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  m_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  m_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_areset_resp2 = 1'b0;\n    \n  // Global Reset pipelining\n  \n    always @(posedge ACLK) begin\n      s_aclear       <= ~ARESETN;\n      s_areset_fwd   <= ~ARESETN; \n      s_areset_resp  <= s_areset_fwd;  // Auto-pipeline\n      s_areset_resp2 <= s_areset_resp; // Auto-pipeline\n    end\n    \n    always @(posedge ACLK) begin\n      m_aclear       <= ~ARESETN;\n      m_areset_fwd   <= ~ARESETN; \n      m_areset_resp  <= m_areset_fwd;  // Auto-pipeline\n      m_areset_resp2 <= m_areset_resp; // Auto-pipeline\n    end\n    \n  // Source-side submodule\n    \n    axi_register_slice_v2_1_22_auto_src #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_src\n      (\n       .ACLK             (ACLK),    \n       .s_aclear         (s_aclear),\n       .s_areset_resp2   (s_areset_resp2),  \n       .S_VALID          (S_VALID),  \n       .S_READY          (S_READY), \n       .S_PAYLOAD_DATA   (S_PAYLOAD_DATA),\n       .ready_pipe        (ready_pipe), \n       .handshake_pipe    (handshake_pipe),\n       .payload_pipe      (payload_pipe)  \n      );\n    \n  // Destination-side submodule\n    \n    axi_register_slice_v2_1_22_auto_dest #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_dest\n      (\n       .ACLK           (ACLK),    \n       .m_aclear       (m_aclear),\n       .m_areset_resp2 (m_areset_resp2),  \n       .M_READY        (M_READY), \n       .M_VALID        (M_VALID),  \n       .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n       .handshake_pipe  (handshake_pipe),\n       .ready_pipe      (ready_pipe),  \n       .payload_pipe    (payload_pipe)  \n      );\n    \nendmodule  // auto_slr\n\nmodule axi_register_slice_v2_1_22_auto_src #\n  (\n   parameter integer C_DATA_WIDTH = 32\n  )\n  (\n   input  wire ACLK,\n   input  wire s_aclear,\n   input  wire s_areset_resp2,\n   input  wire S_VALID,\n   input  wire ready_pipe,\n   output wire S_READY,\n   output wire handshake_pipe,\n   output wire  [C_DATA_WIDTH-1:0] payload_pipe,\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA\n   );\n    \n   (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  [C_DATA_WIDTH-1:0] payload_pipe_r;\n    (* keep=\"true\" *) reg [2:0] s_aresetn_resp4 = 3'b000;\n    wire s_aresetn_resp3;\n    wire s_aresetn_d;\n    wire s_aresetn_q;\n    wire s_handshake_d;\n    wire s_ready_i;\n    \n    assign S_READY = s_ready_i & s_aresetn_q;\n    assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;\n    assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;\n    assign payload_pipe = payload_pipe_r;\n    \n    always @(posedge ACLK or posedge s_aclear) begin\n      if (s_aclear) begin\n        s_aresetn_resp4 <= 3'b000;\n      end else begin\n        s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      payload_pipe_r <= S_PAYLOAD_DATA;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) s_aresetn_resp3_inst (\n        .Q   (s_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~s_areset_resp2)\n     );\n    \n    // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (s_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_aresetn_d)\n     );\n    \n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (handshake_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_handshake_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (s_ready_i),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (ready_pipe)\n     );\n    \nendmodule  // auto_src\n\nmodule axi_register_slice_v2_1_22_auto_dest #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   input  wire ACLK,\n   input  wire m_aclear,\n   input  wire m_areset_resp2,\n   input  wire M_READY,\n   input  wire handshake_pipe,\n   output wire ready_pipe,\n   output wire M_VALID,\n   input  wire [C_DATA_WIDTH-1:0] payload_pipe,\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n   );\n    \n    (* keep=\"true\" *) reg [2:0] m_aresetn_resp4 = 3'b000;\n    wire m_aresetn_resp3;\n    wire m_aresetn_d;\n    wire m_aresetn_q;\n    wire m_valid_i;\n    wire pop;\n    wire m_ready_d;\n    wire m_handshake_q;\n    reg  [C_DATA_WIDTH-1:0] m_payload_q;\n    \n    assign M_VALID = m_valid_i;\n    assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;\n    assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;\n    assign pop     = M_READY & m_valid_i;\n    \n    always @(posedge ACLK or posedge m_aclear) begin\n      if (m_aclear) begin\n        m_aresetn_resp4 <= 3'b000;\n      end else begin\n        m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      m_payload_q <= payload_pipe;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) m_aresetn_resp3_inst (\n        .Q   (m_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~m_areset_resp2)\n     );\n    \n    // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (m_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_aresetn_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (m_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (handshake_pipe)\n     );\n    \n    (* autopipeline_group=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (ready_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_ready_d)\n     );\n    \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  (5)  \n      )\n      srl_fifo\n      (\n       .aclk    (ACLK),    \n       .areset  (~m_aresetn_q),\n       .aclear  (m_aclear),  \n       .s_mesg  (m_payload_q),  \n       .s_valid (m_handshake_q), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      );\n    \nendmodule  // auto_dest\n\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      reg s_valid_d;\n      reg s_ready_d = 1'b0;\n      reg s_ready_reg = 1'b0;\n      reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_22_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_RESP_MIDDLE2_LATENCY = C_PIPELINES_SLAVE + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_22_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      .ACLK           (ACLK),\n      .ARESETN         (ARESETN),\n      .S_PAYLOAD_DATA (S_PAYLOAD_DATA),\n      .S_VALID        (S_VALID),\n      .S_READY        (S_READY),\n      .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n      .M_VALID        (M_VALID),\n      .M_READY        (M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_reset;\n    wire src_ready;\n    wire dummy_reset;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  ( C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( dummy_reset   ) ,\n        .laguna_s_reset_in  ( src_reset   ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset   ) ,\n        .laguna_m_reset_in  ( src_reset  ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset2   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n      \n  end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] mid_payload;\n    wire mid_handshake;\n    wire mid_ready;\n    wire mid_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n    wire dummy_reset3;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( mid_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( mid_reset    ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset3   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset3   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out (  dummy_reset2  ) ,\n        .laguna_m_reset_in  ( mid_reset   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE2_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( mid_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2   ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset3   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset3    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n   \n  generate\n\n  (* keep=\"true\" *) reg s_reset_dd = 1'b0;\n  (* keep=\"true\" *) reg m_reset_dd = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n  \n  assign laguna_s_reset_out = laguna_s_reset_out_i;\n  assign laguna_m_reset_out = laguna_m_reset_out_i;\n  \n  always @(posedge ACLK) begin\n    laguna_s_reset_in_d <= laguna_s_reset_in;\n    laguna_m_reset_in_d <= laguna_m_reset_in;\n    s_reset_dd <= laguna_s_reset_in_d;\n    m_reset_dd <= laguna_m_reset_in_d;\n    laguna_s_reset_out_i <= C_PIPELINES==0 ? laguna_m_reset_in_d : m_reset_dd;\n    laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;\n  end\n  \n  wire ACLEAR;\n  assign ACLEAR = ~ARESETN;\n  \n  if (1) begin : common\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire laguna_s_handshake_q;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, laguna_m_ready_d}; \n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else if (p==C_PIPELINES+1) begin\n          laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n\n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = handshake_i[C_PIPELINES];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_m_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* keep=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_22_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_m_reset_out = laguna_m_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_m_reset_in_d <= laguna_m_reset_in;\n      aresetn_d <= C_CHANNEL==P_FORWARD ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? areset_dly[15]  : laguna_m_reset_in_d;\n      laguna_m_reset_out_i <= areset_d;  // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n  \n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* keep=\"true\" *)  reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      ready_d <= {ready_d, laguna_m_ready_d}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid_q;\n      assign payload_valid_d = (p==0) ? (S_VALID & s_ready_i) : handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==C_PIPELINES) begin\n          laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else if (p==0) begin\n          payload_data <= S_PAYLOAD_DATA;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n      \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_s_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* keep=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_s_reset_out = laguna_s_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_s_reset_in_d <= laguna_s_reset_in;\n      aresetn_d <= C_CHANNEL==P_RESPONSE ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? laguna_s_reset_in_d : areset_dly[15];\n      laguna_s_reset_out_i <= areset_d;  // For forward channels, reflect laguna_s_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n\n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    wire laguna_s_handshake_q;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      laguna_s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n        \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n        \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)  \n      )\n      srl_fifo_0\n      (\n       .aclk    (ACLK),    \n       .areset  (areset_d),  \n       .aclear  (ACLEAR),\n       .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n       .s_valid (push), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      ); \n  \n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  reg areset_d = 1'b0;\n  reg [3:0] areset_dly = 4'b0;\n  always @(posedge ACLK) begin\n    areset_dly <= {4{~ARESETN}} | (areset_dly<<1);\n    areset_d <= areset_dly[3];\n  end\n  \n  if (1) begin : common\n    reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID & s_ready_i;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* keep=\"true\" *)  reg payload_valid = 1'b0;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          payload_data <= S_PAYLOAD_DATA;\n          payload_valid <= S_VALID & s_ready_i & ~areset_d;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n          payload_valid <= handshake_i[((p>0)?(p-1):0)];\n        end\n      end\n    end\n    \n    if (C_PIPELINES==0) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),\n         .aclear  (1'b0),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire                        aclear,  // Async clear\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    wire [1:0] state;  // State vector register\n    reg  [1:0] next;           // Next state value\n    wire [1:0] next_qual;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    reg  m_valid_d;\n    wire m_valid_q;\n    \n    assign m_valid = m_valid_q;\n    assign next_qual = areset ? K_EMPTY : next;\n    assign m_mesg  = mesg_reg;\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_mvalid_inst (\n        .Q   (m_valid_q),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (m_valid_d)\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state0_inst (\n        .Q   (state[0]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[0])\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state1_inst (\n        .Q   (state[1]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[1])\n     );\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      m_valid_d = m_valid_q & ~areset;\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid & ~areset) begin\n            next = K_HAS1;\n            m_valid_d = 1'b0;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              m_valid_d = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n              m_valid_d = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          m_valid_d = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      (* keep_hierarchy = \"yes\" *) axi_register_slice_v2_1_22_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule  // axic_reg_srl_fifo\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   //   16 -> Auto-pipelining\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_RESERVE_MODE = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n  \n  if (C_RESERVE_MODE==1) begin : gen_reserve_si\n  \n    axi_register_slice_v2_1_22_test_slave #(\n      .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n      .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n      .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n      .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n      .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n      .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n      .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n      .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n      .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .s_axi_awaddr(s_axi_awaddr),\n      .s_axi_awprot(s_axi_awprot),\n      .s_axi_awvalid(s_axi_awvalid),\n      .s_axi_awready(s_axi_awready),\n      .s_axi_awsize(s_axi_awsize),\n      .s_axi_awburst(s_axi_awburst),\n      .s_axi_awcache(s_axi_awcache),\n      .s_axi_awlen(s_axi_awlen),\n      .s_axi_awlock(s_axi_awlock),\n      .s_axi_awqos(s_axi_awqos),\n      .s_axi_awregion(s_axi_awregion),\n      .s_axi_awid(s_axi_awid),\n      .s_axi_awuser(s_axi_awuser),\n      .s_axi_wdata(s_axi_wdata),\n      .s_axi_wstrb(s_axi_wstrb),\n      .s_axi_wvalid(s_axi_wvalid),\n      .s_axi_wready(s_axi_wready),\n      .s_axi_wlast(s_axi_wlast),\n      .s_axi_wid(s_axi_wid),\n      .s_axi_wuser(s_axi_wuser),\n      .s_axi_bresp(s_axi_bresp),\n      .s_axi_bvalid(s_axi_bvalid),\n      .s_axi_bready(s_axi_bready),\n      .s_axi_buser(s_axi_buser),\n      .s_axi_bid(s_axi_bid),\n      .s_axi_araddr(s_axi_araddr),\n      .s_axi_arprot(s_axi_arprot),\n      .s_axi_arvalid(s_axi_arvalid),\n      .s_axi_arready(s_axi_arready),\n      .s_axi_arsize(s_axi_arsize),\n      .s_axi_arburst(s_axi_arburst),\n      .s_axi_arcache(s_axi_arcache),\n      .s_axi_arlock(s_axi_arlock),\n      .s_axi_arlen(s_axi_arlen),\n      .s_axi_arqos(s_axi_arqos),\n      .s_axi_arregion(s_axi_arregion),\n      .s_axi_aruser(s_axi_aruser),\n      .s_axi_arid(s_axi_arid),\n      .s_axi_rdata(s_axi_rdata),\n      .s_axi_rresp(s_axi_rresp),\n      .s_axi_rvalid(s_axi_rvalid),\n      .s_axi_rready(s_axi_rready),\n      .s_axi_rlast(s_axi_rlast),\n      .s_axi_ruser(s_axi_ruser),\n      .s_axi_rid(s_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign m_axi_awid     = 0;\n     assign m_axi_awaddr   = 0;\n     assign m_axi_awlen    = 0;\n     assign m_axi_awsize   = 0;\n     assign m_axi_awburst  = 0;\n     assign m_axi_awlock   = 0;\n     assign m_axi_awcache  = 0;\n     assign m_axi_awprot   = 0;\n     assign m_axi_awregion = 0;\n     assign m_axi_awqos    = 0;\n     assign m_axi_awuser   = 0;\n     assign m_axi_awvalid  = 0;\n     assign m_axi_wid      = 0;\n     assign m_axi_wdata    = 0;\n     assign m_axi_wstrb    = 0;\n     assign m_axi_wlast    = 0;\n     assign m_axi_wuser    = 0;\n     assign m_axi_wvalid   = 0;\n     assign m_axi_bready   = 0;\n     assign m_axi_arid     = 0;\n     assign m_axi_araddr   = 0;\n     assign m_axi_arlen    = 0;\n     assign m_axi_arsize   = 0;\n     assign m_axi_arburst  = 0;\n     assign m_axi_arlock   = 0;\n     assign m_axi_arcache  = 0;\n     assign m_axi_arprot   = 0;\n     assign m_axi_arregion = 0;\n     assign m_axi_arqos    = 0;\n     assign m_axi_aruser   = 0;\n     assign m_axi_arvalid  = 0;\n     assign m_axi_rready   = 0;\n      \n  end else if (C_RESERVE_MODE==2) begin : gen_reserve_mi\n    \n    axi_register_slice_v2_1_22_test_master #(\n    .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n    .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .m_axi_awaddr(m_axi_awaddr),\n      .m_axi_awprot(m_axi_awprot),\n      .m_axi_awvalid(m_axi_awvalid),\n      .m_axi_awready(m_axi_awready),\n      .m_axi_awsize(m_axi_awsize),\n      .m_axi_awburst(m_axi_awburst),\n      .m_axi_awcache(m_axi_awcache),\n      .m_axi_awlen(m_axi_awlen),\n      .m_axi_awlock(m_axi_awlock),\n      .m_axi_awqos(m_axi_awqos),\n      .m_axi_awid(m_axi_awid),\n      .m_axi_awuser(m_axi_awuser),\n      .m_axi_wid(m_axi_wid),\n      .m_axi_wdata(m_axi_wdata),\n      .m_axi_wstrb(m_axi_wstrb),\n      .m_axi_wvalid(m_axi_wvalid),\n      .m_axi_wready(m_axi_wready),\n      .m_axi_wlast(m_axi_wlast),\n      .m_axi_wuser(m_axi_wuser),\n      .m_axi_bresp(m_axi_bresp),\n      .m_axi_bvalid(m_axi_bvalid),\n      .m_axi_bready(m_axi_bready),\n      .m_axi_buser(m_axi_buser),\n      .m_axi_bid(m_axi_bid),\n      .m_axi_araddr(m_axi_araddr),\n      .m_axi_arprot(m_axi_arprot),\n      .m_axi_arvalid(m_axi_arvalid),\n      .m_axi_arready(m_axi_arready),\n      .m_axi_arsize(m_axi_arsize),\n      .m_axi_arburst(m_axi_arburst),\n      .m_axi_arcache(m_axi_arcache),\n      .m_axi_arlen(m_axi_arlen),\n      .m_axi_arlock(m_axi_arlock),\n      .m_axi_arqos(m_axi_arqos),\n      .m_axi_arid(m_axi_arid),\n      .m_axi_aruser(m_axi_aruser),\n      .m_axi_rdata(m_axi_rdata),\n      .m_axi_rresp(m_axi_rresp),\n      .m_axi_rvalid(m_axi_rvalid),\n      .m_axi_rready(m_axi_rready),\n      .m_axi_rlast(m_axi_rlast),\n      .m_axi_ruser(m_axi_ruser),\n      .m_axi_rid(m_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign s_axi_awready = 0;\n     assign s_axi_wready  = 0;\n     assign s_axi_bid     = 0;\n     assign s_axi_bresp   = 0;\n     assign s_axi_buser   = 0;\n     assign s_axi_bvalid  = 0;\n     assign s_axi_arready = 0;\n     assign s_axi_rid     = 0;\n     assign s_axi_rdata   = 0;\n     assign s_axi_rresp   = 0;\n     assign s_axi_rlast   = 0;\n     assign s_axi_ruser   = 0;\n     assign s_axi_rvalid  = 0;\n\n  end else begin : gen_reg_slice  // Any normal reg-slice mode\n\n    axi_infrastructure_v1_1_0_axi2vector #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    axi2vector_0 ( \n      .s_axi_awid      ( s_axi_awid      ) ,\n      .s_axi_awaddr    ( s_axi_awaddr    ) ,\n      .s_axi_awlen     ( s_axi_awlen     ) ,\n      .s_axi_awsize    ( s_axi_awsize    ) ,\n      .s_axi_awburst   ( s_axi_awburst   ) ,\n      .s_axi_awlock    ( s_axi_awlock    ) ,\n      .s_axi_awcache   ( s_axi_awcache   ) ,\n      .s_axi_awprot    ( s_axi_awprot    ) ,\n      .s_axi_awqos     ( s_axi_awqos     ) ,\n      .s_axi_awuser    ( s_axi_awuser    ) ,\n      .s_axi_awregion  ( s_axi_awregion  ) ,\n      .s_axi_wid       ( s_axi_wid       ) ,\n      .s_axi_wdata     ( s_axi_wdata     ) ,\n      .s_axi_wstrb     ( s_axi_wstrb     ) ,\n      .s_axi_wlast     ( s_axi_wlast     ) ,\n      .s_axi_wuser     ( s_axi_wuser     ) ,\n      .s_axi_bid       ( s_axi_bid       ) ,\n      .s_axi_bresp     ( s_axi_bresp     ) ,\n      .s_axi_buser     ( s_axi_buser     ) ,\n      .s_axi_arid      ( s_axi_arid      ) ,\n      .s_axi_araddr    ( s_axi_araddr    ) ,\n      .s_axi_arlen     ( s_axi_arlen     ) ,\n      .s_axi_arsize    ( s_axi_arsize    ) ,\n      .s_axi_arburst   ( s_axi_arburst   ) ,\n      .s_axi_arlock    ( s_axi_arlock    ) ,\n      .s_axi_arcache   ( s_axi_arcache   ) ,\n      .s_axi_arprot    ( s_axi_arprot    ) ,\n      .s_axi_arqos     ( s_axi_arqos     ) ,\n      .s_axi_aruser    ( s_axi_aruser    ) ,\n      .s_axi_arregion  ( s_axi_arregion  ) ,\n      .s_axi_rid       ( s_axi_rid       ) ,\n      .s_axi_rdata     ( s_axi_rdata     ) ,\n      .s_axi_rresp     ( s_axi_rresp     ) ,\n      .s_axi_rlast     ( s_axi_rlast     ) ,\n      .s_axi_ruser     ( s_axi_ruser     ) ,\n      .s_awpayload ( s_awpayload ) ,\n      .s_wpayload  ( s_wpayload  ) ,\n      .s_bpayload  ( s_bpayload  ) ,\n      .s_arpayload ( s_arpayload ) ,\n      .s_rpayload  ( s_rpayload  ) \n    );\n    \n    axi_infrastructure_v1_1_0_vector2axi #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    vector2axi_0 ( \n      .m_awpayload    ( m_awpayload    ) ,\n      .m_wpayload     ( m_wpayload     ) ,\n      .m_bpayload     ( m_bpayload     ) ,\n      .m_arpayload    ( m_arpayload    ) ,\n      .m_rpayload     ( m_rpayload     ) ,\n      .m_axi_awid     ( m_axi_awid     ) ,\n      .m_axi_awaddr   ( m_axi_awaddr   ) ,\n      .m_axi_awlen    ( m_axi_awlen    ) ,\n      .m_axi_awsize   ( m_axi_awsize   ) ,\n      .m_axi_awburst  ( m_axi_awburst  ) ,\n      .m_axi_awlock   ( m_axi_awlock   ) ,\n      .m_axi_awcache  ( m_axi_awcache  ) ,\n      .m_axi_awprot   ( m_axi_awprot   ) ,\n      .m_axi_awqos    ( m_axi_awqos    ) ,\n      .m_axi_awuser   ( m_axi_awuser   ) ,\n      .m_axi_awregion ( m_axi_awregion ) ,\n      .m_axi_wid      ( m_axi_wid      ) ,\n      .m_axi_wdata    ( m_axi_wdata    ) ,\n      .m_axi_wstrb    ( m_axi_wstrb    ) ,\n      .m_axi_wlast    ( m_axi_wlast    ) ,\n      .m_axi_wuser    ( m_axi_wuser    ) ,\n      .m_axi_bid      ( m_axi_bid      ) ,\n      .m_axi_bresp    ( m_axi_bresp    ) ,\n      .m_axi_buser    ( m_axi_buser    ) ,\n      .m_axi_arid     ( m_axi_arid     ) ,\n      .m_axi_araddr   ( m_axi_araddr   ) ,\n      .m_axi_arlen    ( m_axi_arlen    ) ,\n      .m_axi_arsize   ( m_axi_arsize   ) ,\n      .m_axi_arburst  ( m_axi_arburst  ) ,\n      .m_axi_arlock   ( m_axi_arlock   ) ,\n      .m_axi_arcache  ( m_axi_arcache  ) ,\n      .m_axi_arprot   ( m_axi_arprot   ) ,\n      .m_axi_arqos    ( m_axi_arqos    ) ,\n      .m_axi_aruser   ( m_axi_aruser   ) ,\n      .m_axi_arregion ( m_axi_arregion ) ,\n      .m_axi_rid      ( m_axi_rid      ) ,\n      .m_axi_rdata    ( m_axi_rdata    ) ,\n      .m_axi_rresp    ( m_axi_rresp    ) ,\n      .m_axi_rlast    ( m_axi_rlast    ) ,\n      .m_axi_ruser    ( m_axi_ruser    ) \n    );\n    \n  end  // Reserve SI/MI branch\n\n  if ((C_REG_CONFIG_AW <= 9) && (C_RESERVE_MODE==0)) begin : aw\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 15) && (C_RESERVE_MODE==0)) begin : aw15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 16) && (C_RESERVE_MODE==0)) begin : aw16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) \n    )\n    aw_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if ((C_REG_CONFIG_W <= 9) && (C_RESERVE_MODE==0)) begin : w\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 15) && (C_RESERVE_MODE==0)) begin : w15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 16) && (C_RESERVE_MODE==0)) begin : w16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) \n    )\n    w_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if ((C_REG_CONFIG_B <= 9) && (C_RESERVE_MODE==0)) begin : b\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if ((C_REG_CONFIG_B == 15) && (C_RESERVE_MODE==0)) begin : b15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if ((C_REG_CONFIG_B == 16) && (C_RESERVE_MODE==0)) begin : b16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) \n    )\n    b_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if ((C_REG_CONFIG_AR <= 9) && (C_RESERVE_MODE==0)) begin : ar\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 15) && (C_RESERVE_MODE==0)) begin : ar15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 16) && (C_RESERVE_MODE==0)) begin : ar16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) \n    )\n    ar_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if ((C_REG_CONFIG_R <= 9) && (C_RESERVE_MODE==0)) begin : r\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 15) && (C_RESERVE_MODE==0)) begin : r15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 16) && (C_RESERVE_MODE==0)) begin : r16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) \n    )\n    r_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 4844}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule src_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(1),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(9),\n    .C_REG_CONFIG_AR(1),\n    .C_REG_CONFIG_R(9),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"src_register_slice,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"src_register_slice,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=16,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=1,C_REG_CONFIG_W=1,\\\nC_REG_CONFIG_B=9,C_REG_CONFIG_AR=1,C_REG_CONFIG_R=9,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule src_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(1),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(9),\n    .C_REG_CONFIG_AR(1),\n    .C_REG_CONFIG_R(9),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nXvoWuyjysN5V55U4xsjyWg2bXI++8I1KAZgJ0eiQkY3L8ns1PfNti9fujmr8wvFQA6ycwh4K6mSp\nINQjc8TyLQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nbD05I2IKef08FLVG4C2ftkJOY+/UsvagxY6ta+A0N1USwLQivKTmRt7LJlQ+5UJqrfPvhHMyYrLN\nrjoJbClg85XfNTYCnalRVvg3mmCcjtJkCLf6S5E9Q6UF92b6bwgtMTsr0BndJhdItlJtr0dYZtoP\nAEskMBthh6RdNMkZ3CA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nvLo4Yp/zX6HvZ92VMA2Xr4EIhMWPNGq2EvSBkjiZd5sCSFAX+37MKx4gdbrsGvhUMl1njqvSaoP7\nKrAa29/cm3QWjPgpaCsR/MhnaG5+7aUvxA5iCqVHXdriMlgx9kzxkB9SD+mOC8XR5LtYA0bPhbZ9\njQzWpWxdaOGYFF25DU0O9M7LMc7SLfKunYH/cQ91D37m0LjgZh1/uZv8chFzvCBbkHqUU0qi17/k\nZTWIIzqb1oycbuhZZrWLl95xQ/aaTxZ30sONWd/axZtO3Cd57huCbCxLuOH51qq6erD9AVszmxL8\noEoM+KW88P1S3LJ/EcIQN4LU0/nyN/f7xEmy2w==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nj99ihkoCqIO9DhRZEJdEqlRF2P+IwS2wuYmoh3hWFCDXbmGTwTqc+3EMjxY8Z4uDixuazjlTMiEH\nCk4MdTkVZ55pPhFb4druHTap3Twn20B3SWvOy2nf84OpTkdBnbK4qagABgZXs9/mAtQxbF++/F6Y\n+OOE3yUNTWvHiVGvpTJavfADkB2CL5wEIlBSnYRwtLp71JokDsMvjq2l3o3hxAjvtdg9ej7NKx4I\nkAZfrpZH7Ebv2hfXrTVI2kDTAl5Etr+4oSqxIhABJut2WaeWJrsSbL+dz9s2ZmYDMb1BCQdRexck\nbMMvUaS+P7sSGuR9BTVynHOY5GdQelHO1aazQw==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nHuzbd0U90PuPKn40554Cnki98HuQSq7dg6ZyXufEWFHsji6rteNupAY3HQsuLpXjFVxsNlS4bcHj\nAAOnDcL0hCCVbSkU011mqhhlkFmWqeBBECGfP+T7/+l9KBu+9ynszhlhaVhmZMffsEuohDl5x084\nFnzFCdxrFyvqrOyWDac=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\neoQKmSsNWNEOJcUApe0UhUNGRDkxOLedPbjyDILgUJWMG+WVCpL9MC2MXZeZ6/oVwAYRlZTZsF1h\nUsVo6BO7IAuHuJAHeIQgEs2oIMj/I2qZxm9wUsOzWoK5/Jz4SS4sTE3TgOJXaX1GNAJlbUrCBtnM\nqIiavU164vZjX5BFoPGuHp4kICN8A4Wr9y2w2Lh0/IdiHjr/Ruk5PpVNyl7tW9EaSFY1AL4aoQpd\nRFDdUFRk4tMBtmFxi/B+pLVFE0hAUZnlVCsSaf4B0lN/m4CME7lgy7oXElp7ov4fMnD9VI8HLGMX\nWBSQjD8F6BB0Wblgm9lJNc0h0VqxxD4DbRleKA==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nyrn0K+G4SU1wuMdE7DJlKWErX/N5nCqD3+dP+4ONmo8yuM983VHfjLhCoeQMbM26e49U4PPdXcDR\ny0rRemqJACoi5H5NvzXohhKZI9q+WKME4TkhFzfKvIwyta1m/uNSe/A0+52Dzbg5uAxYihw0IdZR\nZMywfa3deZ8IUMz3kWSlMs1P4wESz2pKpdYGs0FpvovucuNn4OhZKH7RGX8z8Zy4E9juZRgnSQnX\nmvRtisgVB9uL2J0vl9XjW/1990VYZi0nrZJ8gQL38HLTz62vDuMuYjiFbbnDCujJNKOCHh/xJTdt\n73nsz+dY3We4tQdnxuESibzLQLGF1l8+d9FPDA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nJPIGH1v6BG8bvo+3pHrWlum+XEDtFDlKP+4Toq88+g/eeinS/p8A0zMVVYj4wfjGDhx3kGvJ9XAx\ngxYpezvlgnz+IEGWQzepCMSp4iHz9TEdGkc5LTQj50VJj4+HGz2Qhrw96Hw0c+5RDrv238ILy3p7\nuzIPIzxKEl8D7gK6b8ZPrzx95KMPuGZyju4JUHBWdjDx0hhhIl+L3Ju/bVyWaWd7w1xI0mreJtAN\noOdcObOESJpTuj0KqFtfA3UY7v9n9Lj/I/vMaPX7LnSIZuS+tHyiD8D+t+Kf6XiIl3sYDL9erP7t\nSpHvPfG9bOfGRxM7dmsvKj+XqHeXg23wyS1Nfg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nrxmK0sxFw5opGoAsi+RHBRwE0wYNls8LL+oURMgLNuoRDOPNH7up4F86jASnrdlvXLShGHMZnaJ6\ny1orZ0uAZ6xxM2PeKAxvxBI02HOu0aXd/SMNxr16dADlCYK6R1DVdq3DC+T8bQTLWyyHr9r4m4En\nW5DcJ2hEs5b31PUg/DoCNTpHm2swT7sLG9qRkSfTddaSyGTADcvRXYjnHKHin6TQlOCZufWMm54P\nPJeCQmj1MjyycQGpsvFNX7VMxW49ashO7EGmRdy7lMGRoHDqLWBxcIlwAS4L28iuln/NdC/QV538\nQei7EbcqeUmfs07XP8FKxdA3hi3Aq2Upg9DkOw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64736)\n`pragma protect data_block\npJdOORWQloxSGvgvy0l4tBp1HqnYdonsYgNOe99SLH3qi9BP+2tNlaoelqmLJLSHNsBn3TJxXlZa\nnIZxc0/l2jA1h9Jz15QEEgUR0MqZaESeIPQdEbADnul6xUXY0J6g//n8Vnzph99nb1v9j4yp0I8W\nmF2Bvdz/qHJcUcV5zedPk5PkPVS8cmwYFQWer3rOMl6Or1E/YoHi9T9wfbgxxTs6yzqYqVGUBlz5\nAlhSoRF+xXB1Z4h2Ny4v4u05pGtbpnnDj+JhauZ7AfT+uRL3JZ7hNdSiI3coyNU077RtI/1VAmYO\npJoj/3tO2z4y9phvRShE/Otch4qxfx53IywqoRQmUF57yV4NjbkGPW8j7U6iQ8Ls1911ZAOgZIga\nmynl1jCs8ajbsNdraT0wfsPf1kWJOCuUGyItYv2eEwfh7iEYRrpT0V6YT5gENAgDuriQCZuFtnJE\ndhvImjwTXy3d76buWun43bM5pyUNSUzm90uucXHtbfsv8HZTM/chDluZJ4cMeW8D9Pwjtvo6lXLx\nYJM6v2cUpOTIMOcKDxrRTFomRQ1DwRsa4wQGal4q2dhrokLR6YNhu1ED6+AbEAN+FWui25yRPN2c\nRifAbYj3+oa+z6kUON22gegvkiRIe3iVn5MeyImok+P+5dmykiOW6L7J+GDFd4UZtYwJkwUH4ijt\ny9tlvkg7bhgKKY/VRht7EZFg6U4GjUBwLTEWIsD/6R8LgyENKTNO1FVyOJge9+hJYOxJpk93nMac\n0dR2cl0TLESIEfZQ8wSlqKcnzibNa/Mwa+gyj8uNmBtlGMv9GLnh914fnVrJPaJYjkLNLesy5uKF\nWOOHFhlsuqMHkybog57X/W2y+bzzdtaWoQ8/DU/QWGyTt3Vhlmu4YBKvv/DBB51RUj7naprx+CNR\nK7/l3uoheqcD/zy4ipVqZ/mSOTxjqNwJ88tpKUTD7UHuLf8rEeiu80iR1raYJGMHzUS7FcK/APPf\nbBCJIKpjoq1C63MJYurbOeqWcRL3DDPi/z3C66E9WG/nFKs7vMkhbVhClFUAjy+DwMCS7VjbvUvn\nCbr4m+kTXY7ipbBxU7YIDWHssBAAjeM1Rdxx9VvDqABN+rFZAA7C08PNPUeOiVYCFO3gmbAqYK8f\nEPeBaPUk6eskVX2sXw5/qrh1a5mqGk/sYCFZItuYZ6SMz1BFuaZz+ac8Feq8+d7gH2f1DuK4EG20\nOgLh0liUdRk5TCUZsSZTlhRd1FA4SqglWHYk+GIL1WEcVBskAEiY2YIK1TGXzUQaG00TT5TRBNmv\nsPnVI8z6bWwqXomyqcYSelXrfl2izqtjadlA+3+0O2A1XhL9tmMhT3v0nQIlobxn4nFE376czv08\n2+xLHI/chXlg2WvKMK3NCBbWGw7tnHSdJc47JRdiCkb0tIr9wocUbWPbM7W5G3Ku+bQZQXPM0lNy\nstFAjwukEDL4vbC72EJbEwf+6kzkzLjBrc0JDEzvjqnYQYiwloQ0qi9k/yE3bXcnEHvgw8ig5Y/S\nt9SttzL9mNMXwbouRg1seAZ89RrLrTNZiBk2TlhzdIfvWsbvdBYdIhaMqKRGJFpWxZgPm+JbW+09\nfF1z2nf/18EW+WziUuICezISE4+2HDfqFOEltKV6AdesQWDrloYiby+MezSSORPfWkx+nVGv8JEs\nI01podsuoWFRpVmbt/Dua5qZk9EOHGFBRgvYNnlH47YVREn5j8l2T/0bBlGUrv4r0tmSTvb5Rk62\nTtYvXt/3/jJe7TX05O4Uz8CDBe02LhhwyNkyyNYPm6hcqislaGMW5IrlUBR19xoKivY5xsi9WHEp\nOscK7GlXBFf+1ZdqPUIFBzo8CoanS+vY6N5dX/zhH9ka7wSGlru7qjqAyYG3VOzYi+lIUT1D0l0A\nhIuLJhQlgGIPioPMX5r9G+nJX9J1xhmQmslUobJCrtsIfoshA1m3sO8FVq/uKShEPK85uU48DmE1\nBM73G3APR/Pn3q4udJagFjB+ngJWARXqQX1U/fZdrs1d4U8E/KLlkVQywLtM4ImADW15ZRE2zwbt\n93vD21KzRF0gTEp32+Y94DZJmilvEITUz6i6Uf3GIhk/8VlW2sgoZBxyIXdlfZU0hAeWoF6z0y8i\nsz3YJBSL59bOXPeovsUY+1K4JWkThiLh9WlHMd3YfANHBPnf+imIQZm0bk8SniIn386MI5OOzHz4\nE4NRinoFBZ2QveSs8W7mDkgRcm6PoFPVY3QRUGVKM/cdavafi55CMHzsrvtIU+GTn9VIn3xNt55T\nvun82PwGiZ2FiwhlNlG8Wy4O+LFNA76IijNkkamPOoINY3NpvBlYJ4sMSw1dZ/S+Qd509gN+YqK/\njuugLi10dq5ezC717GDkCW4fL6XMF1BLctfTjFHbDnQePKJIiB57aUuvbzah60QCKQnwYsO2mNs3\nlX8Tl9YL68F88dwoxH0JclrQ/K+4uYuofKZNpcUqyesWLZ7Ajkjo1V/LWCNdqLb7jaE2Z0v+PGsJ\nbQ2zY2rbw1xVbkOFkWnJb00IZlS5AfKLW2JwtTjSc9R5cytj7Kj8rVyPRdWixjwHVXwb9oIhCtsZ\nr9zdlcsnNvnrEk8HWDJmg9t+Ss3qdeobuZBvC1qVhW9OeCSeLWFmmlBTM7zlf4bIM7BPobwINrOH\na+x81+t4Xk/8bAWK5b1pfO/q6usi0t9Z1NTJb3ix47MRkhAbStRfFBfBwzDQr/YBXixPzFiRd7RK\nKHM5pI4NGo4x/1eUa3I9iGFb0JwOlvTvmyLF4CY35sdztuKueaGq0YUi4X3SbBVUihPbcPvhcn3q\nULcb1JlytkOdtyHtyrm7/EOiSLmMn3uCPXQDioYj1f6NsIRA8BV+t4V5VK8a2hNJ+Ci6U9tBmG7R\n2AfVDNWXakk0eYIUYcZuIPVd4sH7Be8PANt6YH+bxeZtBfUel13RoATsMc/l+Vz7BvaZ9ZhPoxu0\nMpG5BKJTAuGZ3OqNXDuuvsvuBv8s5hC8JKvLoL76k+rFk8PlyNwEnYoc7nFhCrqDHeOr/8E3maxP\nPv/AiEhEzjU5PQBF457AHnjeQ3eTwpDPSnYJ6nuR0WhnaxbVcRDXmfQc5Pm+RgJOQXySVRlfAtO/\nJmM8oWf9Wd57qYf2P95KvohDPW6vlFW5UOuYJRNedw/Vofmtj6gUXmSUtZzX9x+pGUbZK1L7qaRH\n4Bl+RKLFFF3ULv72pe+uhZoyumhCUE9nTUfh/0bbyfQ0/7E4OjNceJy3IuQXZAelpm4/lyIClM6a\nbcA7XaiUNtUxRgOk+Gm4bXDK/lbpfHAo3ZLrOeIIrJSFdGgfIjMAMcPO2agXDXysM9w0LXX4XzKa\nAk5Ctu+YxqwaE3xbxVfqa3Xiwxzu9RezCh2I21Ysg1ckJugmX+s7525qUeaUizKlxcu5ef5xX40W\nh5pW3QA7UPCugDISw+aX406IO2drov2E5eUNDLRRG/nY7aG606JFGCFgUNVLl22BloATVP6ZeMDr\nmifoHBORyaJvgAndCrygYyJGcy9labne+Cqn0A1qtn323sFNB43FEMX42WIgtgc4oPab1AYsEQum\ns46nWTCUaZAyRO+53Dzben+MOJEy1iKP7o1PMZDKjaQ4Atrpot1Ix9OivbbWL8nNOjFG3rRgc8Tf\nLOVtiwqq/r+IiSB/HQOV/ZHmkDTL9dtw3UFvBE6wRo6XaWDbKDi/T7PaYAC3GGNaQZw3CTXVFb6P\nSvTMYdICAhD7YCZDr6aVLiD1Mgc225aXecHZoluSWOck9HO5ezjlCFCPDSTSj5OnC9v9zUcFbNOa\nri/TT7JdgqdBMKQjvpVrljLeuPPWvSxLMEar6iv8iFwj9w4fIGsSX5D1h0fx53Dosj7c99OjPOKJ\n43ciuUlKmUrl8zGTv1bTsvgQBspvbQjDlKlZcFGKkJ5y+h+FKT7sLG0T7X0OsNyJhlkV8Oh1B7s0\nnzc4JG92kvRVvDmVljLF5q7kSbo4pOg+r9MMh209JANj1imzsRTwNlFhL4KQmOy32YKv975WzfpE\n5gOHTY5gj/9beHVy72SphX1PvZ/GvMrFHu0Q1SdMOxiDJO/8Vv+UogST5Z+pm6YS50RKp917SJLr\npQGNrqMBt2q0TjdKoF10330Oq2OQnGbPQBcF5wAOKor3lUhuKlgi4yfTsE7g0RlphaWiUi0kfQnJ\nxJaR/v3zWkal8YKuqBUOk2zAI58JgLOCGfkeP4lLDigas6lR86dIFm2ehEwWiuUxA0rMWk7MxUFq\nIvlNP2JTSuRX5d7mSS5TdZoich5Z28tzuAxtmfX/HVgsAiDJsXeq2lNJnPI4t7OJcjw+/LTBFn4u\nGkaeVQKsrDg0XjypHHAcx3Htai3F8S3SrSZThLhmNA0UuPAVwrWM/YxdRJdPCFxRV9DIfFLc78ED\nrxRf+2hm2iIX0v9lJubvukxj3RKg3bWedHf9X7fBwzCzmT3xpSVT/orUQHTM7BJi1uX619EAPHfH\nEslFnO9xBhBE/NfxEOIr6puKJWQy0vcdu3KHp/98gdYKgnVg5mCXI4uGSJL+j3Mo34LyWj6jofG1\nRpvUjZOY2WsTY2U7akBl0Uyiv66vuAVFTYtHxbLeKihdYSSxteod2tWquqRvLeBirXL2qi69vijg\n+WXGPNEs1ioW+W6cjl9Kt1V92qIp1LbqTEC9jDdj5VHq36eM3zGGY1FX+VH47w4FoxWcrGaGXkXO\nhGXHGyLwe6ssZ273qYR1N0RhvtgHnAdUHIPdsqqRbjeld0f7uZDVEUjGCA5HvEPmaA4qaz1HEmEX\nMSbcEbGOwM4/lsTSso35cqWlqf9VepPPahniUNw1bY7j79iM/o0F8kJkfL5NumCR5VM7RsWuHT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C99kqfj/UVOTB5eheZdHy7EcqBeNR/+6GsibmPncbobTk24qcaqVJt3wgZyWp0s45X+9wMv8\naq7nxbvk+JD5cuPi785YB4Is1gg85t6bvpA9Qfzb3O9Wk32ecemuYY7hfv+wXPcCciMC61K8t1VJ\nDxofEz9Nxh0L6M2gdZhrIeECMYqp9YunMryNLeqc7YQLvKIjonC1l4sbrYWZ+Vr/tRAksYUVxldM\nWs7rdbIReyHwkW9Q3eVk5tGNZYwsTJZ3LLHqX4k4QW4fN5SrXF7tpu0Nh6B20X5kbA57dL9bI0Mg\ngdCKLlB0s2kqOmSFFGQ2qiGM4gLCtJKTcJvH0QXyq3PoTYgnvqWXAi7962ulHUUvjiqAbTLGRYQR\ngd6pRfridQ9QkVVZ3q8/Wwg9RSEsbZuIJ9bsY3KxRk+Bv/QJmfbw9otM2ufRS79SLoJDUzayREpA\nzPDRjhDoGxRqrI6rV3uPDIkmG/IgiRjrOM3CMltuf+l5zCRv72lm/BooJKYufHaSMAUyCUXJp/Uc\nFu0s9YVH+QVUDZtdn/t+XoUZ1zviEEgoAEoY2VYry4fCJ8DYaSDlP46tShiJjQrOJdERGgL/xQBx\nO6uzJrNrt7Cf6kh0YFyp6QRAfTkuf7kwETESQMUFV2MR8wr0hZHmd/UBOQiPTPb8DscsuSAYh8Zc\nrknuK0zKex9YiHkZeDo7D/PSeuh+WG2d2zJdkM3Td3eMS6WVDFMFl2b5W8/jYjNABrnjK1XwThFh\nYLnSLJi/Op7SthgN17FwYwSwj+AcsR63hVzcnfiVu3ZUXHEZJEyz2HWtWt0RLaZ7MNZccAta93yH\ngOMoJdpfeYUKCCFDGcTyJlFegiSY/R9BWXq/NR5ouF0kpaoEUa+kWjoHoOiSEaQs4XEhSuNjRynD\nrVhVZzcmzBTJAU/E9/o/Hq/uvAStcm39QbP3OeAuNYGNe3sCFCFik9NxiyTW3OEmJSjBcrOnO+Qw\nx7FcS9UJ/wQfURM4P12Z7osL0N6s5Am8NipjMtQyeAtwOcmnJoNC+0+NUiyPWlCuXP/3Z4arSgFa\nZR7xsOv//tsF4wlUna5iH3TC56YNk8nUsFEw6Ge6ZSuhEVsfIeY4wG2IxxjFm7GLEm+Qi2fnWvFp\nirwOxF+K+U92WcMWV9jGmnuJKdDgr9f0rTsSnyJoE6abD5qCwAUSiMOFTLyqf0omOu5SrdwPvxDF\ndftrQ5R+oqkHgkZje/QojcIA5MmPjkCLRdKv8Qe8et8c4lmY6vRi/j86jriaKSwx4Y+Mw85SnPR2\n2j1hg4L1bm3Y95mODLr49QGkDVB7kvY4Qy33Bsp2CTuOWo05KgZSEEXL/7U+fWGzRHjASwfcbgCg\niVFHnASo+4H+F8SItbh9vW9aZB7dvzb/sp41V3sOiSQ/lvFv36hNky3d5TPRgeWxk7ahEnAeBvcU\nN36JNzslIJ0QcFbUJcrGjbreKWGwtRudHbvZZiy3VBuJefbL+K/nA5GKYex5vaF8VvW2JtNaz6nG\nO2mf0K1OaIC26ble9NY9pYrqytCcdTpOisFBK/sWMwJTDavyPDcaK3b2r0z6l8yWe/+kZORkwM1n\n+vS+mBxXx0tf6GtBwKVn9Wq5PBEpboQb7z+jnDgqEVQGEQk44+zDxF6mTiYHaVCLhGP1x2L8Qxtw\nPkf1ixuZGNM5w3J6JjwoYA1WqjGzNXQ/2I4IFQ7+zOL2BVVm8a+5aGNvBOtcu4B12kHIJpqjtEJq\n3tU1eussVADMAsGVV8uDeYtJPvulbF/idSwsgG8crk6BAOKJo99VQxAzmHr6hzse35prsun1dsY+\ntbANM8RyL4weuRCRdH+gaMfEFjRTXyRtKzs19VCSRxpLGUewvAFPajZ9ighUQ2DOA7Kr/rcMTxxd\nrh6hpvfsAFBAQjLiKMsH8ZMXPqNGDBjA8s7TGxd1KmM66Kj1RfzFBtlBuz9LglC/dRn/arEJkYKW\ngOxCUP9SwP1tqpMfyCFKkHci/RYZqmjbNlLH12cl5zMhmsQpiIcZXYfQL8enrVutyHkc8Oplycxn\njTecEx2W4yyRww+b9SpNrQwNcQAZHfUmu5afg1rtbUHZmBW//Afpurxew4MlsTVbE/q+GW4sYS08\n5hT4/ITaA2T979WNydM1h2SItDPecKYro2NCBuNGPCj2smuGGwIqTTedt7kY0lTXqc1QprlIXDOv\n7A/WEW6Ks/DyDbzo5ebBQ9k/Or/ERzVfh5qWgkq8yG0qonueIlbVexyJM/7sKO/BjOR3x/FKDD5A\nPOch29mk1tOqyzjUVo2fdU4B2P5yIWUu4LyA1+iW0TzGEcAlb+9A3LJHWtdxf5XRYSDst39xRNq/\njlN38Ihbn61REmPKmA+LoB8LUMaREXZsyBT2mkJjbCqOmNANgzEAOIj9ceuS25Y2KtrSdejGBdIE\nvCBEfvsJHNzt4EujHKaeJh7o4NDjqLcdEp7ed4Ep3cSOHMCOA874EICbE2zaW5mDE8TG62+kJMaF\nV28mlwI5fMFxipXSTKgVDY4Vj5EWSGuC9St7IfruwsQ039cqwvbAOIuBDwEDSJc6lCmXs/qZhmZt\nnFv7j6yW+vhyh9F/M49mYXMIrZDI2IQn1meVK5DQbu4ISFnSDGJl+UGx+F0w292X7x/NZlrDFxjU\n8F8hH3SoFUjtp3cdqR6J0qgyyvNuJIK0pC2nq9IzjvH1k+PjKgFH3e23kG7suulbVb/rfU+4p0A0\nUw/8qfFdt9ZBcVINnpEPSUJScU20uwWwAzXtPblYceO4Nbetd/Rru6gMmzl4QBV6dHDFv9Llj35m\nrcJlg8L6gZdUkbc5dWUef9LywyJ3ifFwzOukFPVGj0p1G9hRSiNUqdgpYFlexuLPL30vERjJltwu\nf4LrTIZ2VSuuoDz3yvK7YYnre2MTp1IvJIRPF0FnWr5WUuDhARBzNlManehpegpS4ik+5bBOARnk\n2ikf25Ea+euX4IRwUJwiPzAGTUbPzL3cODFaJ4mHcPv972AeFd1T3djc/nkOpMRfzLbUHz1h++GZ\nfguK3eWFxgEnwvmTBOSV/2pqlydJB+j2kzDoBOhHJ7yMYPINzLTm+GvY8+PE6TGpMumpLB79DVsR\nwtH293Qaqs60uwABd29zk+xMrOUEivDU8FIBU3QFpa33/+/A4nI1MVfVSHknip/yEcpuNY2qPJsT\nYuN68cBSWDFeSQJE5yXwjpRVFkSAHd8nML/bKhBZiplgzijzI6AXJOmkqclzuE3gbvl06XzNvh5g\niwbchkuC2q85hHpT3w63G6WwlR9OlnKpzSBsWJI5MiFvl09L3irrYtbw529xtermE/blvOxQYxuJ\nA3+cCbwrhbuASE/lxx/+CQSXsAGEFsG+rJZf02gTem+flBUQWxgYw7USLAXlR/yGYO6KKUiU5mYp\nMcLp5SF0ptsnO4GjOAmsRzhq+nFaThfDeXAXowTEeuWN+d56AInospMZc/eW0bFPTbgOjid6z1Vd\n+9+s7tiYNg6b6j0iAwEiBa8LX50Gz1E8B8Xk0bA4iCfVG+pXzxngp/ZgDAxA6x4B4xS8JSzvBqG9\n3fF/tpaS1x0ZYZNKrC0vl9eX2oeN5I3CbgEuLOUU1xIlzEYHqt8Ta5ZEnYRUtbhiunpXdVyqirCN\n2dgXkldd9U31gMhMY7qFkzBGBtdUApeaRyAGLxKnyg+nwnmirKX9Y3rBKSd6L+R5qhO6n0UbbSzD\n+4en4Cmiy/ti0HItxFAe4vWNWKSwEzlKaZ2HLEPHIUlwN4xiAAyIeXLQP3SyqcvdMzkhMFVdQYhH\nM2F1yAOo3G/JqR2EjrPkiLCy80ya2Cey9fh2IrTFABUwl8LswS7gb3noQTWyDJTWhVsMOvXawU6k\n9W4Jitv0d/+g4QNb1K05p1NtcnLpsIbcTsGei35vIairYz2Wpukkc+QIjcnbRoRYwr386Jd+y7da\n3/zxTz0ylTc2RMTh2TEZRm4kwoCvMb5bRjiCs5p4VDLdB5NKcfMPq/J+LOvbN9BdKd2e8etvM1x9\nZ83qLpzhi7vatfxsU6M1tYzeP0N1fDEQPFerPkzA/sJJfcYa5H+94+uMTRANw63xIlLDhmnCm9fB\nvFsT1znWi0KNE5YxMVAP5Nj3aNk30viM/aEGcXN1+348mdh8cJXP6Se0n9M2ShPtIh6uOzHcNN4F\nXvgZxyI06BOFPCh6pPn8pM/4wkj6M+5Q3d37NGdAT8T8ei4zfuLUhoasw2cJjrdrZ3LNelT1XVzr\ngtfkU+onSthCPR4WS6Xrw7Ok/kkEQoYmkdI7UB9unluvVVQ764ldp5OlFSL6uGJlq53fikq1mMPd\nHtYt08ogxQnb+cC85LdLrpUdkov30YC0DE++eB3VOpsBoGUdgSzOw4L/wn+VuAsCWq5ABwRe4fqT\no7SyMEpq1RX0wDx7yvM1IrLxDdnN/w9pE9XQ1ww/ANlsQf3806Yc1bxBlnH0iwF7F5dr6ExWX02C\nm4GMD+POG+syw7glXgXQ0OUc8vp22qMR4sD57/Oul0voKncx2id8UccXB9vsMZIBhX8NK9iQyJK7\nYG53Y6spKPwBaJ+D6oCzIRdMrl47suvOHOFMlq9EgcKZSM8cW1EeM34Q9wneG+hmi1jxmgRg05WA\nNvs9ns0cBAUoExbeKaTDf+UdQg8kQpTj787x73pVcySGZAe6vE/iMHRuSiZo8GQ7v7UaVF9ntzDG\nTtrPWvFHyuV/SDdzax+LPSONzmqYuZtNNGc7rSFNjipVg81YgVclfSx1PGAIfydo7Z24e3Gz6NIU\nMwj2TtlQKBbeM3mx05abZdGgKr2KZg/G7mtpHcWqPBAwGoOynrpV4ZdlOI7jP3SkujjjiUQJ8FdQ\n9dU1KADRL9hr5MOS92p0+2CDZXdgK1l4EzeYC6fuN9IyAXHsqWhfswpOubjlkJfdxHP/GX3hjyHO\nUvlaWBcZDw7BAWM+AX28BwSssw+yc8sPIxzjHKVjNVz51Vpi6eQgVAZfgVeW/CVd4po9zDauDBPe\nLW3Ffrt6P9FU45qwQ7MWE7oZ3zsTc0evg2krhbb9dLqiCoz6VuCkphBd+BhX2nSPTl+BrGC3EtT8\naS6sDKIiJlBJL+8+GJ5RSEQoTGfqIs6ND98n26dELJI8S0uXSltTPxBhra5yloAd2F4/mmmPjyWr\nTQxaz9QC3JZaY5ciYNddoc6aIflLXGP2kZlT/V1zu+CW+BExE9WpMnVToGI8RRt4jv0a874Y0An6\nHhiPkeDYN6VUowNBrQ5rQnTkFaMpJk4oWUQE3v6avp7Y5alYEE4wCED+ItD2AgaKwC/nFgLMfAnZ\nktUhijy2X1yEewInb5S1xc28GWJeUEjeegaSJijHmFVUCwrnggKTZlbyJ2a2ezSse3QS7DNzMLsw\ns3lvV7VDvQazHXN8RAgvOB0B/CgfYjwZQnyysjBMCOEXr9ltmJw3ogG/vxGHBu667EeL5qOCFKZS\nK2yY/1setEN3lBeyWFiOt84crc97yyhIN9WLadvrh/f0YfzTa8/jZpqi6C6YM8s4vbQgQayL34x2\n47QkQV/JCgk47e027m4LJl2YsaOwIdm0CLnMgOgEGQPFdyZktwDaQcho9eG3wdeeDVrkyzQormhu\n9aXm2HxMwA7LFBoLoLMTe/h9G0EmWJjSZJbpYBym7mGdw7mGASxg/8DfPNQ061R+2X3xcnmG+cIO\nvl0+UTTis+WrgnTXMMvcqbanhkRzuTaNKehiSLRg6bGYM0soIp56mfxn+lCOLxRvrFVCb4SESUTQ\nh41pLzHt1noaHrzs6Gg5F6h/f/xdaHC5qixpm+GAiRp0dMj0xX0roGySULb0Pg5Ik9k6Txub6XiO\nZgO5zmj4Zg5w8I0AnXTXRWRQrHzuRzUxeqeeMsb/JspTSY5oZj06H3vlmxUcBhypLvXrMLcXh/Ls\nc3bNxQvpWzLBqqdhy2tGJ8fAWkun0YPhNwlUU8lBB4Gk06kgUQm222XRVdAheeWAjR8NbiAop06S\n8Wy+XiAj+daeCKkiouMukARqbllP0jcynVe076LG+ZgkcNqoPU37HDyH9n2pGf6ZkAQuwFeIbkSF\nPg4iQ36vkP+KaDnRItQq5Ii+DKzEOXGkFXjeyB2kGs1noDV9eD6DHXsQa0azeB+0c9fKSA7nV4Mx\n1BtiwRMnJT7JPQOciedKCuaoP0Aq+hvnG6MBlo+nAOOlQfvZ8qQxlg0laf4f6XLVWOpAeGt6y0pr\nAw0YlMDiAyvjsrh3t8P4eyWaZSoFPRIJLol9+5QCyrLlm2aVeoMUtwJ1/53pTKnTEHcZIZfi1n7e\npjP+HdzVIccamu4mef1McNibQT4nUfu60LdH+ZQICzwZKDu6slLfWc1KaTXs71UCJzmFmBNREiS2\nXy7c04shnL9MVkGQUM4rVvlqeU7hjpj2FNlt0nq2A7NHDHkEArM25UeIzO+An0jC3tn+qfMDBZmx\npl24RVKkzC2NhWcwhhc3TGrk1gzXt5aE3zkSTGv9pEL/s8V0XrlWQBLq2XFeBXgLpSAzseg2st1r\n71IH25LcYi65u03YZ8TaQSNK5ZQxrVBVO+JVdqF5H+UcYmJxyBsmvTOso+y/z+nGXXnu6Wxeb2K3\nPMCSNT7G7TIbSFmkl2cSMzEeMwmt7AyMdckkJzv6cvcC0j0fLIcJ+ygBucF6mrNY7OMFKMatX0PI\n4UdpryZPtTB7sdMGLH8FqHkw0PoHM+53+V3rRDIo+ImSU7g97SHk4uMmW9/lU3+h4QEVhf1SsCoH\nD9SCjVbJmWSx+5ck3SWahLdUTGE0c66fdQ50VOj3xxA9nvsgL6x8+drW1LZr6SHG4Ma07PvqbId/\ncOHrnVi5FevEja28niNJV/635eMPcCA8uWcnSyTm1J3Fe+CyROmWWUPs1QOJLqlM/Ai2tsSCIaui\nrBVtakmXqv0aMhA33NdtZu3vrog0aJfleoLXQUuDYIGcGc8kfavMyQBG72eZnrVz6/tupr3lLY4Q\nxVGFP4Jxgxq1oFD+d8nf2DrnUh9AyNvtyyOCKi7z+ReLuwDg4jFzd3U9eZQ7WTDxuOYKmerT5+UO\nG4qs6dNLomx30eVvW25a2Z2qtWBywQq/MaVipSr2RmdVavfkdvSb4lRU8c/OXc2j2EjLF9uwD9ij\nR+SremaAbHZZKoNbBX79rPCGwHPTuu2e/3veCG7t4yv5s3WUvVkFPocYD2rO92YBt3DE5NjJ8kgM\nBCj48v+cPe2x069u+Nco6d7scSnHpPHHPSM+6Py5/LgYVagzcTfjK8PlJARVcAMsLJiBvfzpO+zb\na4Rs26CnEdvlCgaKBV1YLeJ2dXWhGAXTQg7SIPEe+qxZanakqfbbb2xT8QLylB2wpP6fAVc2MhM7\n8GAoec89XNo9PAPakTkcl0WxeigJFRkS527gXqWbZigV+8fVkzfLL8ARih7A5Y8faOuGrHTI1D3/\nzLMHy7/g+ESSQUAfGIeRgrKCYK7EMouPFRuxC5uxAYpm5W/pKsdIPrBHWTqvC0PZClvqzFXBi97p\n9keo4Q8i5+/jCqoMSKdh43uf/t7GW8Dcg5wWxhGnjWC7PMUgwEzMeruqNa0zB76K0zeUaOmh69WT\nQE+NgpCq0rrPFoR4W/hxQ5lqPWMYVQs08oixXrdi4qxOlpMbrxoLJ9dbreMCg21g+h8idnl0Tl1L\ntZ5uVIyA0sfNcXr37h71rInz9wjZ2D+cn1MJf9A+S9uhwm3BGTz/4NlrrXLFirxI7VfKkYEQ5kS9\nUmJtizU6dQ6Ehg6JDdHxuh5l52FvU7VuMVMozDJdJMvbkeQHAh3I0RSRxjaUk9t20AqO38NUWado\ngkUnSoEZCLnKpWk0YPx/LgMwFeFUGPMwCcZ+o4LM/G/XVGe5eO/pecve0eHmEnfeVBoIeGUVNgM+\np5FXp1hflAYwWYzb3FqUrZM6TMi1jBAtwoA8RkCsrYN61H3rOO2e29xzDffAshtKB1dXBUfI0Zxp\nVN8o0s2S0sIOL0Z6Y2+38Wn6hSTm9pUH+2vQjPt5mmWo7cg22+s7MbGkZISOJNCM1mCrD3s08ZAJ\nwSe0IXxQ9GoXKl71fWfyxDOEN80E97kYHfLwT/anINNK4DYOqinZPKwL6lPcmfztT/jkkYeC47vc\n2LKundEqdpIO8cT/NlrAVtDH6t3Fm9VABN/HIsAxIiNvOpHUSrLSF1keYvjZzNPJ5FRQgPns+eTv\nGP8JvC15MCNYsPYO03i0V8tim0p2g1ZGaidN0DRZ+8QURKlhGPX747Npc+Sns6GK2hOpqQs5xmC/\nkg05svfxeKyBc+mnkDT3BuW6tl06gkPpjvfgTxknS3UtGnjHnLRzXmIjQMl2IQ0m0gzzccVzi/72\niZtemsxeuumi+UP3MrCWaN+wN9xfBDV49pifJbqDeSGoznX/Zcb2XT9kvtBFWMmlBG27ZlbXviyw\nPnR21Qdpe9Ga3f0oQjJGGlKrEtk8kpZXg8bTyYQAlP0cxQpKZU2EjD5JPPrHfj1jG8shz+Fu/9Ho\nMoczpTM2n3rQNUp7R8v0cHO6ikm9/A1cUv3WjysTiu7SuCs4gBkotSNY2Xk68SXZWzYgFxmK8HXy\ntx9sdKEH13yEbULEXA+4COwl/PywoPj/Nl+Ew4Pwcm3TnoqS0GSPt7HJPOo2hoOxxqB08tPM+X0t\nB9E3nmeN6WGtdPk5mkipZRl6B32i/Zgg+ya/eRdCQdf9fg9Wyl1aioGzWlZgA8sH0At8Y7gl7NYv\nGsBJKYY9eIu3oVdG89uBhlUj0AOPcTOGIyt2OwESMxURJPXjak9Yh0eSBLOasPf3rxt91kWGROIx\njBiT8eMt0OnS2yu5HO2Eg40cmIqsC2vwtJoj9wOdu3zeceXfhMsdMoEsk85U9XUNedzDXBDY+d/K\ni529zO4iKsBwTRgnL3+Qq6lgmFdlFvr4PT7x/PusFTxAe30moNx7vtlthoDXjY69raOtJEVg3oac\nlEa+QrsLiy6szONetja8Xwm35OWq22kBLLd/fhaSvhSgxFNpHlINTa+dJ4OHbZshSM479f3oy6Gw\n36CHvvAUHpTmQiWWOqNmmUHHHnMRxvyySNkV7J8hlPk547mUpXPDCAheNrbQCq7Zg9QcaiQWd9qJ\ngnrFkLP+BjGxkvJwrV+1jUS4ymZ8io4U0EOc64Tuk3B2OXy4e8bHbNs90VoNbogNJ2JBBrluJx1L\nQ4+/oI2p1bd9BrWyi9lb2v+KL4o85RzAFnSU5vGSjrIx3lm/ZH/QN8/90o4qJsXwnwzwywuIEieB\nDYWlvqUtcnk46xKGSj9rr/PSTZBd7gFkW0W3nLbd5MKKjVDxtdiKjSV30e6iwgDQZ5rKvLaEPVul\npiJd8wgHGnnZRT6oMODzea5SMDG1Mx/Uu8SQZWcFTOb11D7MmcZD74Dh6kGsUS+qfY/P6LK5ZyoN\nHNMkZtEiQINbI3DG2LexnjcnXgKqZm2ZXGavRz/1f3A+4d4Rw6KoWfXIZOVUdNn/l4FxU3xw44SI\noKl1tT8NUagrB/gafvUWFBenLnxPxW0TaqMp+/lnAdDvwHLTwf2p56K21HxTlxXAb2QmgQlZB6bU\nDuYRjWtw96PcNIcEhaffTdNRFC37g/+Rw8qIWX4+euwL7s7q0kxKR4/TG/OfLrnBR/5+jgJGxj+u\ndtyDwjwrtChjTru6KPXODLvAm97PhZ8NRtb2Yzn5a9LjbWYSBpxjf4eyfAdYjEw9yPbjJpi9AJAW\nmwhWv/9b5rkxkeCEr4yQ7tXZTLx9l9hQktow08Zlh6pE4/8M86ah/0BFrTA8TwV1MQM9W2oncjGH\n+9q2b04TNO3wbncrECEi4DtBvtfYup7Ewyn3GlaO5eYLTg2/jiNmLP8fy893XZvRFmwsQRwnyXCo\n2nYZv3H6iAokmm54kiA8wDeKeZH5bMVRb8coUhzn+OdVrFqyf8myg0lyTJzy+bzzY4Pah1/xh3/L\nbI1bdfdg2OoVS3n1aXMOJQSoBQzk8F4lkSgV14x0kEgcg+6I2cD6IG6bQHCLflY17NMmKnX7MQeQ\n9ARoZL9Ftb6h6jt+Yj9TqigvDbbli6iYyt/3iLvMaE7nKbkI+BcyGR8FeD5rz5Sukk8W6WTDkgsD\nYzu0DTmAkRvyAwCKiwy6bzCh4dzKWJOK4GMV+psXZepr0io43Re5pRIkbdTsNzCzimW21WR9ePZ8\noWGZGUVoCCHkoM+VhFyZgrFBCuEGtlTrL1OhJnn8G/vmj6GzP7ppzjqtQOJdd1NT3mIJtM2MU2jK\nSJ1bL9b1YgSVmGnENvIHBs2oDoiFeYB/AdsDKbam8Ofe08wTbM09FVlDEjl4Kvym/+mlqBqdjB8W\nBTlVuLz1Npwe2Rqin9pAfmf2mro+7Q+P1t2MkMMBq7+mNXk6t7f1EZ9CP//mfVK5vfUlm1bJwc7h\n7zjymmmA2J7MYyTiTZCFm7zKpr2m0yARdirGbh5+XEerjM0JG1JFcunC/BfW4EJW+aPNSQhpCcmS\ntpvSqc1TiSkWDACL+Kld4mtOaUOVAjJ4IPoOKrJtnDz5EYLStpqmXsohKLCt+sy9YZ7t7NEdk0SI\n+i8nrAQsijEAoguMLC2r4fcfepagdfAzf18AS3Z8t8vItfUFlgvlByAWPD0pAxEeL6gRPo34mHvp\nqtb02SaAbEWUaCCZNhoIT+MAPCCwxxu6OEN9VW7YQw/hmrD4e4GyB19xhrNtuyh4zHoN+FX72opr\nxOkXzzghtXGGsQ2q3/6cNaNiE7P1xigeetIkjYaEOogeiEI0BuF1fbJDaLfReX9e6jXiLvhJ5AQe\ngiPAl3g0FjDUcmDqjRteAhE/PNHfoJUSgu55pPfO0NY2t2Z2Ye8DF9v/uGaVuFA1bhi9O6ZJfE0V\ndCrNoO9JVtPWadZbKqRoRYR64EhOYf8QMWXpQea8J6pNasP5XG62E3mNJmZhsEhO8da14ofQAFnr\nuw1npXWWvVGW2OGong7N2Kwh7SRpeKL+2tVeUM5oyRkkegprU8oY6yDTmkgW4gzR3iUD9r2yEQQR\nEUrnBqjowX6/a2UbkSvengDsfeYrIn57XZhpweU0dH5uBYP5FkquBKbngRzDWRIhRjpZOeNBuquj\nX6fJiQEmJedr3pyKIPHyXEepzbIAgL5Wuhzk/LNljrsUkTz1/vK9wk75QbxTXjCCi0MlhBUnf0Rn\nT9gWptFSKOOspcWHZzz1bR3qAF6yX2iGIpC7CBqaPPjOSnOIr1Qhts3FByUz2W7IrG7VFIApG2Qr\nZEpY3450S8oEjLqImCdG2XYabHF3KyViSlBMveVAn1qZGku+UFjoqKXKLREhng3hLqooi6ugvH3F\nhLD0lteBKSVsoGT5MDZ10f0FHDYuDu8pt7Yx+avdWuF0XQUqscn1y0GeYS5kr86t+F4ToSMW3ovR\nH9BqBMW/e94nritukUh+pUU2ENfgPglvuqcA55FabulEONPo2iV/4CdTcW3iZD/sNsGF1UHqf12a\nGB0N+vCYNuUpx9LspYpJWTeHOQslPRs7vWN8S54MBEJuS2EKLe8/vgESL+G2BnW7yrnXdPGpYRi7\nantqD/KGvHSTv4C2mNcnINFPsx4e4JPlmwJwsIHL8ez4LDfzGkbQo3znuwcl1FgqMpr/rZfAbjGd\nJnMlIYAo47jNmAfLXWB+SdpPEJgdYuuRi2GQKLWkI8JUR+/CMdKDssgcEyaJyvWOzURvv1hQUUs8\nPkMdKt81i7zFYQjiItlszd2C8zczwlH0eWE2I/wYLwBYMkRn868QftUBc7WCXFXvjBndT65IzaLk\ntS+XJHy1Fk4Cnnkwhr5UiOJVKXMm45H5EKxjwXZ8si08tIgWT/TPY7OcTvYc4EdO5sqbIrOIlxcJ\nA9IOjMcJqGbEoWMAtk2ASak4RNiXlg1zb+mt4fLZDqvemjQOEytIdpDjsKXex4b1kwug4wZmGlki\n8NSMfJNHvGf+G1NZ/qm5S3ZV2kDMvsq1CbBFSw/PxZ+mi7bChotalY0y4uMUAOBSP9kunqJAUrMn\nS2uohKVUiU917LWN5sndUR/DPUfV8pwKaCkdxF5wwUhxZriym4suG9nSYCjgTo7RtHPM8zJ6jadr\nTOy4MQeh/41kZsJ/XYpc5ElRTokVajxpABDhLz+d8fs3DQLWhTQ7dAQFzaxKEHPQYD5+qYLkSURA\n9WeBKvZqJTRRibHc4nbOfxRMxaQc+EAAjELMdOKS89L0XejFvCUujsz2fzQBJkpDyfKoXWLRko92\npzHpWTlhRDA9s5b8PX/AR77wA5ArUGNjqLmVzA1pp9zbxZdgpjqCLi9BNmyv/dg2HOuQs4tgw0Wa\nhIkwx7jfZ3N+FEnXqMihEhWujWBIpFVWJJg9UJ8Cj597k6j613fhjn+fQC3KCwnC2yGWi5ohm/8M\nSpdCBPF0n3F7iEKeRYOe9LRZGXKsa7cPF1dK3NOLqS9L8s/I5RGmzzYpuJX9J3AdnFkFX+eNJqg0\nKMrTPSxtaHUEe+by0YZm0zlcR9t+oiatQXde6yVVzmFWgcmsoz/fDx/AOOCTGxthX7cLvkDnRut2\nzdGY+x0SPOUVq9Up20+HVCHHJVdvlDHnRcwiopLP9EVVJJ3+8+zXcRwdR/W0qU3e3tjHMQeLcQKh\nJEXrK+Byiw8OmW0QMfzy1sWD0q0/sbMxlvt4eq0rHv2LvmpDayo5mQXKasNBMKdsSCFzmjkeVXkL\nx6lrIBNQrnRK3F9WHeo1St/Vlx7gKX61STdUZx3s6I2o9Fu5kQ/n87oY5kGnfIYy/Sqe7poccG8s\nnwtvT0W1l8YAgjLp+y4ttwVZN1u2Tib7vNpCGWTeUR4N4HZlfTWLkfxHA9E6qHgLyLhFdQxD5MjF\nzFCW5kFcsPysIWupF6wd+bHTvxMd9+e6km+LqJvwX9TJm0/Tuhv5smOEetrL85LZL4hoOD3gkOD9\nux8mkIV156Zn5qAXgRhGCBzTAoc3gdEEAZuM9CMnvGFt7nYQqUWozJbVNIu84YUuW9UaohW0MdBq\n9OmTNAp1jaYXjqH+ZcW4yCPJEkJKLw97SJqnlj0ts5ypvSx0AsRbwVqIUkBHIRTEuqdwXy7ffZPz\nSuwzY87QGmpoKvLB/NF/8a/XOC/8ekWrTlyNU7kOVZdUUan4xgg+rmtb5dxRQOg2+Cg5yB2KYpFZ\nGLIJEaN5ePx6OuNsKyGAnoL8VB4CVbYL2YhLksaWv9aVH0MSEQBH+d+Hhh/hyb08on14QDQ3IPn5\nPOfH37BX1Kt4ZT9FhH9AqYK9+IYyvlY1QZqMYqku6WF19aB5M1k1mnxoD9qP2OCDsvW0PulTcPwe\nbZWzXBB+yCTURvqwPmCCGg7Botgo7UemIA/YDo6uZQhRsrlLBqrNEpQRRJvwcCZadPmql+bxVLoB\nHRd0slNjme8ocHNUYblDKhFKIO4zGW4vkVS2xu86jFCJP+AUtWtEoBbRuFb6se1EPWSEZccg/tdG\n3S+yZwJXmSQIKiocBNNsoQl0ZuYObaHJFh/ghdUlIm9QpTkoUQwAdD6P2fVXHsUxXitYILj9Eao4\nnl7koAUxv+egJe38T+XzWu3qJvZlze2xvOmAAXEjVQQfE0DmYJfZVFKcDVdg5jYqF8G8FxSmQcxC\ntIn4gkrqg6EV87gisbn7qspi0sacZ6Q/1gQAURtDxooDDK5gsV0NEhI7EyoinLXjZJ9SY84+Bzcw\n+VD19FvREqBGtziYVyJ2+YAO9kUgWbuDuEy3aFnNOeTv9ze33bOAoAhBDtbJ4BJZt+eGcbWYWlP0\npMcWI4mKtcX18daNTCZR+LgCAw6J/bR3KiArm9ML52M7oEzMMSX7skvxyTaIj1zojGgXeZXvki/H\ntGHQauTSObrzhFf+YE5t50078XpPzdQQVhn63OgOKp+6Rie0Q2OZJJP1G9PXiAViKajwJ0U6IoUK\nVG0LJhSYwAOF+ditODWEnyYQJx6u4HFg1/OYPbRRf5SL0HEyB2SOhxzRc+QylENCwbGWxkJ/MjpF\nucxP9yehbXSUmmAXr6u8e0PlT+0MEcL5+hML6XanaR4sMnepTVUB5OQKCOhz5bVdYkfJf/AZhI5u\n1tj4AjxaqRwn5RhHqqcjspa9oAXyD6fTTd6VkJtf79obE2Vn0/CkZx5Gc/vEV6Y/UUsQa0+HNWxC\n0KxJ/LqbD+0Xo9hk30nIOWumBfNHVFNABhSH0FO6hXe1h7DRvhESnhSo7kGWpv0N7/A4SIRMybQt\nC3MeWIdBm09lya/sOlRRHwnjh6BgZeBEtPqYX++mSFDadrZ5912qAYsGsdIFlk7+p6xospuH+IyQ\n1PP4r9wg6I1iF+wSIukIJgfswFgAGBtqgDHhfMaea99tCTbBODCxTlvVOkbfZwEcdfqDQJioj+nY\nkY//DSMVhLeq/3yvLCdiembO06ynPh1byTgwmALsU/RT7uf5DrZBontbQhHqEaFGqtf8irH9r7Cg\nJC23F1/SWnAd16dLnUjiqbXwbIoLMHbD3pnqvbyyqy7FNroWPX4qTHJMm5LbSMWNMGR/l4ucWMxV\nky/QnNMEU4wvxoK1RI+mCtU7cdIjq7I9Jx8vXkCdnLnAXFb9QNHosk8LwZfmibS/xe8bBW7lTtzc\ndbpZwB90QL9ATHHTbwX997qQwU6f8Q6ZjTVx8VzS23VGBt3KmFvGycKB6dmPyzvkFWiQW+Cs8bpN\nvwr1sTQF8HierHVZSIDcGGnQ2RcE9sHY9ywA2gug29YJOrasaChUvfzGHMkvgAeWBLoNN45Ptoq1\nHNYIOiNBDDt8b2NxtHOlftvoV+KQTNTItY8HuSuvucGLRFZ/ijxZMp7Gka8hw0omBjJ3K/Canqk0\np/nI+kfZ/ww8PnWSkJCV3iTei8yb9akSyGPtimN3DRXg+nm9F1vhe6ZjwvfxYdXsR9RM2YFddDJj\nPJ/7sbG2ySqr5AI3utiP/mJsP9zsIUtciEXpzIiY17AGEzEf9WZc01mBXJheccBxjLpk2hOmp7DW\n/bolFGQo1u0HwOCjvUQEN/VnOXBf9dUC8dHNpljvbvcpY97VkVLl1hhLXJ1B6CZ5pcmV49ukA2yP\nHUvkv0kKuJDG2kjj4LUJ5YXaAGBdch2MCw/ET+X9R1Lbz7Tm0oYfP/vj2oQjxfHEux6lD/Urc2oI\n1tAqwKd6r/F2M/RmthYfXTEpVDUbiw91v8Sh4I0wwtXOQr1qrn4qwtP90lOT+tlF2M8TKR+rerOz\n/5Xgv0CCYjY7xCg4tuF//w6fpvgs0Xp8n+/+RRHW9SZuYLcjNkECku4X/bNTWgMoAfJIJLIPFZEg\nKFFHSa7PwlQqsQtO7f3M30QtV+S6oPKAnAqXuAd8gNhhlzMJ4O71NOrGSrsYdqyKFMu1pulAegSk\nQZ+uiKAj5kh/P0Ce6xKJQVPByIdBLuUdKWrNSvLdkjayB5YrzBXr2uR8Z3qtXmVTRrfhblbKcmVx\nbSlQCkpVPIWCxkOIc1vH7QfvkHgkz0Vh1O4Br6JIiEDbSD3WhYk8pT3YrbNfBhL9XWekVTilmC+E\ncoRGgWwOOnLGcaI7bxVfNZzqrCajMQSnYQUipkO9bAkBHiMkdegZfmnOCpQgUhIRZAmdKCA5IYZs\nhcQolXWCTRNRgfH7AkKeeObiP8KDY1vJ1LZx2YPiRrfGHoQeAVKnpo5Q+XF4nsb5FDWlbSF9WK4x\n3r2tGTKoamdzjbn2uks7TO7uFcTC1hsh2iFiECPnECYbt25QcuA6GhkCaQDMVCRlC72dzdy8cM0X\nNLgdEMCfAuh/pfO5Soab4eZFkdYi0lUKw2JYfFUm0MsvAYUhYEY0Hv6jh5aRNCEz+5cuDw7ufd7P\nmvD82HTyuLstpgQVz9MqL2IrFX7zOwsr4Iki/sE9jhAIqK6UNb2lrwHuhRS6OETJDguQycwqveDU\ni5P15/S9l0xzS0bAffASHIiHDS/nna1mXJMzNA92v5SHt6iND+4NgaspRFj5McYl13C+pzciz3D4\nX0zSkKlDQTpJZAjzqyduOgXcU5sROz6raPi+V12shPmKE5aTU+nt5baf0/qBBo47q2UjQMY75tMF\nRVal05IPRf/HOpHBowN7F02gfVE7H44F4ERDK/Hq1xEtrOFK7H2U3ec851+lya2zTCJR/Xcf3VBe\nlxb4RN1NWaePQkEcv/YWnNpQx+wtJntRzhd2+4ZsxawcWl10ffFyNr4ZHupqLvX7v4I/hqx48thY\niV2fchI4tKi54R4OpsCf7NZMQeEvUspEGjrcQxpHVgtMx1vXC3/lApBlX1jOD1aTwr7ThB9FbEPp\nc37PFCi99PpLZuExy4twaIUSOK+4IOfnhrNzP4+bb4TObcMe1gbmAED5+fDlwoMUWWRMMzWsyN/A\n1xIrOrM7zcDWgLZLcIOfS0spfbW4l41PKSCbIcNrB3jFSBrcwm0pQbneAUYkURTiw0Js/NskmPQ1\nqg+UnXhDdicyH0Wfn4tVGjaPXG+qMWBP4Fx3Z4tA7m0jIrR68Ao8aX+cbhBeS0kMS/j246amm0/s\nCXDiO60Fcdr+vOQpO10O+LjBwZ5qsiJnpnjeaJqXT+Et9/jkV5Fjp1xJ3EnlachHDM//79eNvK8/\n/JKOSm4wMLqBigZLP0jzbtnwgaUT77pjjr7T1mI5GQzeY3nuBOxgyscRlg6qA+96hZ+yXXtVArTR\nnf8MO1ycpLPgEkAEsRETTvNnDrfQAd3EFl4I5oisHtpNwuZC9DBflnl5hDZaZW8INJHxcaYffeOA\nI4SZqRyHEDisnaRsUSDIwcwj+tUhOyJyOMFqPYPu3W8unFFJc5VDswkGf2v1azZ9sqH/+QC2r1+q\nvmU/p4fmXXsNumWv6mJCHSInANf3xj65XGYYVUADHApABy4FLykn1IX80gOG/DkB8tArpTRIvOnL\nymsyFKe7bYMu0tUnlo2TPt/h8MeCWZiDdodmrMWa35AxrWLyT0U3n0ZtHC6/Vdt/e3T6oziJ/eVg\nlSZVzkrl/F5IvDwa6bvb6U0s/exSaMcTOHYms2e8B986/g+KZ9CjNQx8CSaf/8NGvuVEXtnONlx3\nLAWQZyLkf9AlRhWJk8otSYNkhQ30sHgRnkTwxaL/hxEClk6MEI+Z5UJt9ycXKODHuULHepLOcPZ6\n14Qufb3ZpVjOTbYmikm1m0IX3bCoKrUhj9oXXboV9woaTYxH8fx08ABGoDz1wA4F8VMn3QUY+F4A\nsb8WtvEmh+XEuRlB1edUNrN8WEkKjj3TwLKejJhrheVTvDZR3LGzRN5p/Fiz3f35bZUALgirF+Xu\npJhpoFYB7CAMH8og/F+Jlma38Ms96J/JN2SLV6bxpjWe5s/aAFb/m5T2WMr6f/Fi+hR3bYw2ANUU\nuDrYb3BZizZl8oAm3Y8N/HtMXtiLLPo1FuXhV/I/dqimr5RkGNYv2vmFyIRzlTWvf1OoQdCpp/8e\njsVRC2nOL5aja1Gbrsb6xLI7v7zOy3OXXnL3A+5G/aRzJIi6OYRIU9iBmF4cPrBOeljwsiThjyIo\nKFFxbCwY3TLsY5DzxbRnwXg5/kBxZOaES7X3X+zHI5eyla9CnQbfH3EUEvY3EV/37+8QTasY1tOI\ny905e4+8SABe51gkubKLjrhy29UKH7O2fYpuytamltn64Cdq4NhqTcnJzHCqZsFlQR2d3NCt85uw\nAMhm34FtpsIt7/67XzcvPhzNtotKCiLKN/Cgm6WqDNXxXQdqWBpk2t0ruAhp3IlUhukD3Wg+LyXf\n/ZO143HqZM09ejrB30WW0BvJbccuf5qb0GgBxnj7M/eDXJJPxea5jNDgIz5AJ0m2xwLDSCHWb2Wv\n2gTrQlIYnhFqNF51eS9oTQcHL1NUd8J5WhoKC/tnFnYhqZPSXTiC1F8H3rMUITUwIwR4Eq5f/SMy\n9vvjUuHFbAre0sYO884yH76/735dC/HbyF81vbM7uEaXpOBXKXUyFJwP5E5GfEcWXmllf5c8aS/0\nX1aavdNjFTbB38PKSNPR7vE4GYr8QZDsjsYzycp5vB/F1X1R55r1oHlKyB4lyggTZMjolN7L0+/K\nh0SaDpL1hBSp0datucCgpkHAK1ECDvvnZz/EYs4aUJdU/3zroy9RYIfB24/4jNs5h5aCBTMkmeiR\nAMIDLVnyEReJ7oVzZ6u1b6EZKmUGyoE/NAWcRmSPjTUJgrzF4ERtajmDO5hzZdyTOkti/h4tFdJl\nsaYMNAKg0w+186Fz7c25LLBkit7BG/wjrAPz2cW6JI3S4ru5pGGi85VQsoeLOW80nnosEnFDip+V\nJ7aDxGq9BSwM50DlrWdIxbvLObiVnLR8Ar9HAyYTzspjd0FPpeLqQVnWy9kn6nIT5CqukkpCwcLo\nSlct2bLxTcQhrwQucx5/LHBYpKkrp7rrzkHZ6P+cTUcLHJNyJPZkZK3heV/f0OcEsM4EKLZpD0g1\nJv8wATCKBeecm7/VqyQllTUUWvP69Owt0G4XzttdIBz8DTPtaI6ts0hlmbOkcDTTvBf5mZ3rNmnw\nlg1mysjyO/US6Fuiq9t9+3Xofstc4bHEm4YBjGCH1IHTDzvQccKfnM/cqleRvo7H5eXiFsZtPp1G\n6GOcsXHa95RzZj79MoKZNjnpEY+t8YauJ+ETl9KG2HPb5yLpP6Q6cV2HTp5GNHhvtcCoWQBAiqHO\nbxr7/HrkWj51SqQJe0KV/R6u46GvpDHfkVkDlouZTZy9uiFGVIo58fKeM3Te6Crcktg/2o5vSjkO\na7Z8yu/uzD4/L9K5yC9W0SCtqS8uulGQZpEHMWNlzCWY+pOvRSTSp73IL0EUO6DI/7fF2UjEWTyP\nl7qk/O9HvnOrrWAV5MLHT2Axk1W7H5akhnhcPAA7Lx/Q/Q5iLoPNHVWxjlvlwLlwWq9OaQICR4jq\nGDNMi14HM8VyANmSUU50AAoSn5ABDzSXJ9eUaJT/oU+O6OyAckpg07u/yYW4BkTMw8xIioyNOSqn\nvyJ7cBAB7X6KOj/KjRLLt2J94Qj6UBECe8x1PJ+/oKc1U5SNGmaDsiJPYE42OuvkHxD9CXzez4zx\nMiigISEAWNHfQrcy73vctjtz9y0ieOjN163Or2pLp5RE+4EnBTO68tZ7DiFsYAvgyApEJfTwTzS/\nH+NfjaRftQPoB23DSbd4otwB9wqCTcgyKeHfwrA2tWNoBnRRDh43MiB/X3InWXASYwMqfd2bTAXB\nO2ZNmuvDjFCqHdc6XOPqtha0OlB3JmvtCjQqmRjfwBDEg9nRrUo5OrhjinJ1ZZwsA6X9Oc2M1jUP\nlgQgjlV0P/hsZqt/GDjLt30k3e6DvQg5Ye+Kvn8MkqXne8Omnj4K3lzvEKXPYgWrAr6+t3IuGKRO\nr/774W4XqSnQXDXYSsPlm5VAGXmAqncVo5ekdQw9di1hmya76/G8VcN4QK0J/Q5c7xhsRvZUhBbD\naoZnX74rF3GIzaxID8PujDrYDMP2QkRZijphPCywc/l0jsldhR2NB4RW/kYPN3uUqK75cVesEaL5\n5v/AR9/c4p8tdoJRCWfRRBN5m9RRDQl3XFMUCUPifDExugkQfos7EIKRGrXely/Hf1bqQd84KBHw\nQgmROHDt2QlItAPE/wtivVzftCklyirO4+OmfkftzxGbX1/QGxAlJyR0gmm6RvKa1YoKUrKgK5S7\nXscl6MYwHWn1FJriTwerIP4mWdDdbOdCyCWKVqrv72q1sgu9Oofps4WpH4Id8HnAUAeoyYdHVdyf\nJnSE8viWhzvF+yf1tjrLZZySiZWT+ad44uIZkAqC4GRPwpOiYMPcB2Wa+1jl9Sjtp6expmx+u/5h\nAqCBE5nVYwwbNJ5/97wkl/T0DZm9KVtrlWoLxqYBUhTAfQ/Vdd5kx3Es/xK0tvL1c62UXivN7/I9\nVqga2Z9NvKTT8owc+ZOI0CANprFE4IK8JbXKrTc2NMiULmEnCU8OGYBYIMnkxGLerH12+A3ChuLx\nHIhcg1avfqvOounj2H362C2fJYDtmMVv5i0y8x0+v2FBjrTzdrisolTypKmUZ2MHXga5ZGY7mXqn\ndgkFBZOS64qYD1nIn48V5Vlsi7LF5aLMCOZWlXOw8WmIF6glbehcEFsPSnmyeQWeFK9duIjIEiYC\n2S0COsdbabYyYPGGFpz+iI9h675DoLj4BC552U1qA3tp95Z5GrD+9NcJQeNA3QjGp8mHde/skpX4\nYkex6WxEDA5ppcdy4YJO/pIrDUz4Y+KJm2AHQ8G/1UYNLy3QQm2xvEdP165sZy/GgTk/MxGtmTrE\nUumAVGVSTzDM3pMWOXMbHsDiCoY+LxKBmOofdTajcbPQor9UnJOOh3bk79plZvZkj/kjgc1ipavu\njT6UFxbm9ghBi9L6eUME4BbN+EiorSLlyWruDKS6fq83mX+4iaCshfP6nQnuTU1728nJ1U7J8h9l\nq+nruftauizB/m2VnGlEUGvC5d/olcqk6pWiMeuemTJM5+/BeAZ82XblX62hnpwo2kJhh0byu56B\npAUGKnLdamBw437+UlRRmPWEp2UG5OrqjLR0JMf02lGeO+AXXllC0ji5T+qUuITeYpHEadr7rg4V\n4vCNuTSmTymv06ja7bmoQR69HQxh8GWBKzTOLLC0knyElBbtUMaLTK8ocsuJxklx/fiJ6dcTfyay\n17QKT9aSN/+h/kzJsmdd/rSI6eJuQzg5lq1pM9nNggWdnDkZteF0Zg9YFqHbGfJMRqZuHxiWWHYf\nhs6BYwa1Si9yITAbky6OYkMYRRXLKB11R+pmRoUoiwr0xLh07t5UF7xEWYTqv+9KueNxtSOeV/+f\nEdo7uzq0Dii7Z8WTX2z7Aga6oO50BUYS7Zu9EQqXr8lj66On35fDlpEVb6h0feMPSn8Z7CCYxZxv\nrrgpc+B2PXhRlSumar1I9au3GrGSzbXaP9tYa1pWTWneUxksfdk/VkDLBuWlUN3jc5hvC0URlDsn\nV9FN14sxPOVWYbJt04oVou/R5XA4BNMUei+KMqaZ9LsMWy3qKESHAs0vomXA0Q1xxXac/zDN7LsB\nRTS+2gszGrNQQd961iFcXZUTQQaittUszpL3Z1wklSTLGQ3Do9eYkpQ4MXTmKjEcUcTkDd/8NA7M\nahK/cQ2y1mYEyJRkYFICvafpDj2h3+Vrzbg9cJ/+E1y9pNY2lS19jiEtaCisx04TRLUodD8TP7UQ\n4/ijc61VHaWa3tTgXuk6D9hD0oCiJOSUItz8iavDq1u7eDRCMKfEuHf2v8Ddhmkd04t2N/NQRTRb\nIoNNHHHBrQ/dszA1gWrgEV1xZ0dKWps4R/gk47Ow72agtIRoPMhVUyWaBgxaaEF9NAB/0Knc79/h\npDrIRM3UDEfbvOJJfBhGpmEXa5waa5PjxFrms+lsyTs58QeBBGPyfXH1r00fkBCCrhrlsM1QQTrU\n048xf/oyN0tUcjE/B1ZIBe410V5kNJfAtxAh2VPfvVbgbecLqGm3bRUljE8ozf1n6ARxD6GASLmc\n3GOh/dMJqp5oJn2sOFwv+B+AYOeGsnY8Qc0sa1DnEwTVUhDCZ2M775dMR3zZGEM/kk1pALwGQ6Im\nCnigap8WJ3+AQ+x5TZJsjWnnsZFbKiAITDP4+5gG9BpBQwVL7bSQYfWAYV+HsZNkpN9DYVKoz2u/\nbNnXohT5+gKpBQYKTg+h6XWaT/lwjspKXQkftnXwIgZC2EoA3j1BVjXTu6ePnVHr0azUwa7rhzUe\nSNoCfmOWeqnZSvRbVB+fRNZRI4hAVPpgptKPpCgL7DekF+8a8+X+Rca6jH9KFM6Vat3qvo4j81hW\nxg4glHb86eHWcUlzAW4wQR/D6gOuwjzvEi1jMpNNzZda2vtnd6b2QWQHKGtf2V3gPQNE7qp0z6tn\n8zMGcmW/WdC4n3Sc9GSGmsVAzNkoJmkCpBSMUwSbM1Tu1dX8eqXtI53zosOPO/buxyAkhN9sXDC/\nt5lVZdFQB3QqqT4xDjY+CwXxguwKeogUHQlcmu2PyndG1/ZlougRvZrmb/Lkw6bwLFHnuYLBZbov\nvAFBpbSKNKvQkZfTSwYiDNvc8BMFjMmjcFamwmizpssKFLlKIIbAUGDo7/9giFPRr+jOsQsmEYM4\nvL/nKadZokw3N0FCPbZNG7oP3I1wFyii7Klje6QNyIu/MqYQmb/XY51Tt3uPm7Xfc3/tNrmlri9s\nqzbMC9eeiwC2HkXHim2p0c4EKVWinPJkmzzHhHD5XqOMojAJPhX+ZblrNiwdx7yZ9FDd+udt11t5\nKBAtGk+DkDqFAWmcK77O05i4wt2nbfCYpoKyN224bqN/dwJBUcvQDeGU7zCkK9cY/M1RyGyOrSBv\nuZdwpqjj52VMyhC4eSw0VKnH/dkjXE6ob2Bu4okt1VlwfosxgTLiKv30Nxqa6xsSgUBdLW76YgRM\nSSxCp+DlI4KsYaCpTLqAkTsNbWs/XXcz+KkpZwGT3Ak7gUk9gWYDThPEGhAMifMZoNiuB/frOteo\nErLJDy9+/CBi+mwbqwhlM1mSLtEL+QjKXQtFXnAoKwlV0A0S3Y1F3eZVIt6N7EGpp+GqKm6pbvJi\n19Uv96Xgojy6KuRIp/r7ylJhgsaZmktjQVHgyTwbhlwc443FUjShzjYUNu1v/lv/ma3v07n/Nu1v\n5Ygxneefjd/BazNEjUTdLMV+xI/8Z5v2ZgRVVM/EjyzoDUtDR+/Fc3MUuqiQt7vYIQ3vJshwAQ7H\nq6dkx314RtY4hRvZUCGU+rnX/qCmenpVXFV2xn6Cc/5OF4EXbr6RN/qhCuiD81yAQd/NbjNEOtMW\nVmqXqTPsOOPY+FHam5EW4IxjWPRsAIX3P6My6Rer1kJd1F5zhDJbArwUbEm54c9GQkVXxhTWYIqF\nvH+Qp0Yy9tyMUnRlASj5jMvgwe3cUuHPxlyPUuZK+rK5ayJVxweBf8s8NsE58TFti+6DGNH+GMoj\niJrcHMl7JIRez9U7WoBdNSTa6Wu4FsIQskSZAPRnqG1YIhSSsLnEaonRZ5jHn6PxFIsGHWLkRRTM\nPYYKNKVMipW3WnaHIgiN57KTb5pXBGnXQxTZWgNJ4Oc1Hb/CLPxx+jpJFEHcrEa1chVQZd0SORaJ\nC0zRLJ3K6naY4bpkuEtRGvqnEiC69i7rkR5IYJVZn4T0L/IaF+HxfL2jZBzUqPiEpBIkGRIoRoal\nnAnVsez+Tf1g3sKGGb8Jc7Bvv9mbKP5r+ciY4SkeEHFCjRtXAHTU2sIxj+cVDrOGcwgj04QZg1CG\nf9j+AucjM1EmfmYfM6GMwlJ+jju7bvRNsowv0BBNlF7J8l98+ikv4vmUYM4WSkRV/jc+XOLWD2y5\nyNpM1OjVk1/KAG/In+VQAh+vgz1+4/xoyotLH/qRGT+bFxn9tomW0+Yzn/gahFC7LGrb3bI0eQTp\nQSejapmUj3nSlxVQ7dpQNZ0NrLwA+G/GycUyauRzRBxKtZMNHDmjfuBZX7Tcy7YiatzCZ6M2eST9\n05E4HperTb/cfGMm16ME0VdyxSZXAmb+OckEFGyGvWLoIVi1AdQUkJAh5rbT1QIkSS95m6iNjS13\ntFc+QIFe0S9X0DKXeRy730ZfGzxDHl3mt004W60VSMKldSaBLcHxxkrXUno6fZskEcRQEFd8weJj\neZkjtL6rtwkKjYV6x+cAqIRIH2CIcwgvi1MM+SbuB7Ej2OHbWGsH+ae6kDWlG5RxNhyL9DD4xcf0\nDdxElbdQ8rphwwoJvoNEe02bsY8iwtjuSyD6Y6clNaL27fwyCzjLujIWDUy4CHvK7Vl7a2PLD+dw\ny3uIbO9kn1IMMIKHSlomNpPap52CEIksHGtfk+4XSYfSkQKKp/kNqVVR1RPQGFToDqSveiV0bWAu\nSEee8c2awA4VDSIte3mzaYqUYDEfpBfjlJ1kfUOttH4qAi0IgL4BL+9FkiKjuwGeHVs7r+v2X30a\ngWOPSwAX10NabuD1IZjK3kIAgJJXnmco2ziHkW63XC2rKj3imToI3yyPwL11wtrAgJETZGrJTxO+\nMfLO+/2U61Knhu2slj+hYdaJqoIn0DCviHnI7DIQ2fAgjjaBl5/Er7USC8yzu0STnipb7cjZiTZP\naakr4i4vGo4b9Bd1itUaJzJtsdWrkVcFA2gSmBCHTYdro1jelehFneB/aDR7mxtnjz4PoHdES47A\nOuvVgKpCzNoMR43wGwKzG0B32o2W4cyo5fewsH6eHMn+T4EedcuHmgurYiN62uO0nz+M7aIaaBjS\nbPAJW3sIHIEEdl1P1Qtj5bpN+FoHJO1S7NGnxpS9OU7QMPd0thdPovlaO1Whwj23a2G2ry9SoW1z\nY5olooVHpgXYzMH7/aKVZy7EIaC6Pq6ILrl+N6Ql3+UuOAhOVuIGmgA3U234T48fYm736NjR5Gul\nrSbC9/WbAzLVLiCWKyxHmQqbSEsaOrjhz+ddTL3rcvzVLwFzhjTqRWQsPbtItebs41tdPf8MvInt\nkHYDIMP1RHhTu/5dAS9h/X3tQYAQgRhCHOAE/4uMtfdvIjgAe8fs2gC8QK99+EappIfJfUkvZKML\nn7JtFbyd4wN7CU5dpNIk8/RsvM3z2u7jtDa1yIZZIHNQfTaJ8WmsrUrjGpbjbT5lPZoMiQt/jblL\nk5uJo5y4kpVNE9Mg+OlMSMqekZyUeFSHuGOBn2smMqko+UVNaCFxXInWjz4TYpqXp288S605F7cL\nLmqsI1yHvV6yXa/8DztLhmbusW0vtxUKU3I2h/KupFTrxLHKOWOrxyix7kJ4L/g8/PutXuU1kAoI\nAu9OkaBF9G4qAHp30Eb2fxolsyRqSg7tDREIfyA6rPwj7+gY9z+2g65bC2+O5XyzC979ETBl5EmI\nPjuXiDRlRRDNtKsOLoz98L/9GAnV0AudrPU+sgVjxwcNfKaRqib2icBzWMIIsL3QLhhQxLI6bZwp\neya26npYMw+VI6+huptBzOaBV//Yonn62HLD3MBmDEsZRbSRiedUiuv7FO2kTlQi66FK9h02Uf30\nzrbGSKr4sRI666hzuzBE11QBkJqOosb4dDlHX01MQSKIc2w5pKvfi1MECCATgZMZ7ilhizyPHPhM\nqYR6erClv/4mrKlfdy/eRyaWBenWkK0J9aQB62+fNvXWRJ3F5SQA4xtCLxOlSKoqQVV+311DUvax\nEm5l0r5y8XMpy8Ig9W/TOidKG2ruNkmtRHwn7fomGNnG+YRWvlHPYkKcrMXXVZYEHhVwrwv0FRdw\nqqilhFaMowQStCU6A/Mch+SK8shJHK11OJnt4E6n7GSS0VWWIoddIm5+RK6+DVbhGIGMWvq2c+/r\nUMAozYzqqMD/iC/ZUuMEFaGnsRaf7fDLta1A7VFGGX1JrfJ84/D89+TUzIoiJt2a+mlOv47F/nIt\nDAgtzOSYGKb1NhXlkc5js+oaoygWm3Nl2B3F52XQd7P+eJfDpWK2TjB4F1BX9GMnOlI5S3kWAp+y\n8m67tK5JQgHqpN0CZ6yLbololzSu4PX3gW8kafdkgnx/s11MMaGgmdlGj2EpOY3RmzfYb0zUcv6x\nrDj6PCQU7tjBx85GxXzUZpzyoW0vswvtkLufpFueFe13Lj/xkjdwrV9ztjg3RmEWpqEDhb/ewj9w\nMDgzH1m5Waee3zV6RsdM8OywzwGB7r3QEi4+TJUT7n93NRH2bl++VBegv12aakTzLHKbSb6HyWdE\nUctb0DJhxi6aBKuzwBDJ8IXilBnK5vb0oGMpyvR0+SIG/WehKC+lUhfpwyKzZ/x+BMz/AakXAFHB\ngprixyoHCJS+IyJRNTufZoRpXGD/NdpZEyuZEAOBoY4iuamF/oaWgXBZgaa0NGa7axmq8VyYXhhS\nXRaEXo0XFlyt34x/Hs3t5P2AwUqFOhBalvgxSFuIdt8s1SfXHA48jwEBSY2mRa/LrKm9DL7CVsfd\nW7AcoaS+xAkMd1ZA7zGD1+xV5kFBSJ+oUm+BHq35pBGjxdwPM4IYx5qL8t5y6LkBzYVXQeXrYz3n\nAPikEn834V2RN3BXwNBi++a9RQG/9kyZFKAgjy/EIEDqsZ2Fz1a5AD+kRnZMq4Gy8FqfvtzaDX51\n/24gW4s+KdESku5GMoJiIdxYoPSC5yYdU6maW2zfvhU7j/VxHIVkEAuL1jggslz7UvWmLvDQSvyg\nAOiGhRngYu4hcVry1NbfF4Y9YOxx5VSFvbZcdVav2L76PYXQvfZa6b5zAj8nMtYby/auDzpCGggX\nIFig1IHnalQgAmlg++abElpqAE9+F7wlpvxSuMr9qjsXMJFa1NLhTAuYn6KSATMLJtmc5ZgFjtV/\nqZI83QMNaqgB/sFXO/zdaW6lc3DKYv0khan0DLyxC9ZYoU56KxHnwcsy316h2kq+KlFI9JUD4R5K\nk+NKgW87SF7e2IsYnl9F4WoeUQ9uu1TrYwvbBQikWhMo5zGJ+jDNnZE0hXYvD7zLnrpjNxk8u1jB\nVI3+wFkgF3y9dft9r//mAputCiFpTIwLsQE06NCVgTlG73PCHAGOQBkEBW1i6c/u8at890aDr9FL\nJulPXrkRHnyQlGS6bml0RA8vNJpoVwFRl2QRt2qUo3qTbXDEV9aj3xXdfeEseUR6MQCshhixhNj0\nKU4YYyNjpsnXLYyHerXk3ioDeukDGLEyA51ZK07Szu2UDcIFqZ+ab2ZHiovr68NcLfw6YE1qkg9c\nYLT5Dk89XCyGIdn3pgnES+Sd0tcg+T5Pp7nx1EigHx3ZihMi8Oxe/D6guDWy5TSL1G0ZaC8BvFYa\nh1C5Pfr43DjEoojJFMUyz4w/w5lCEUBEh6E8gXjAMVjzFAsA7vDjdWz08GsKz+CFWPXVVrVAaIRy\n19k1gGQ1MRtI7CUf1wWh7f416K2hwjHgzz6cmETCt7TexIThgarGxn+VSXO5pr5O1/Fs179fijJE\nLmwfZInZ5GW/PJnyfU80Z3xD7Jf8tA9KEhVmkiNE+SX7QVCho8sBVQhT5B26NKZrKHXkuFWKcBsM\nBhB6mZkvndJIuBm6ALke5fJITcrvcci6rA987B6eGw2NVJK11fP8ugBJBkmiSCxH3U6uXThxgqMz\nPujL2p61OUB/0gPUXs/sr7qt6X9/kYDGwejPI9ievkME+XteHvCyDtPlq/mjoWYawo1wDIP2NnLV\n+0QatxMMZBMlG6naoEf4pifcaMe3CAyIAlbYCkFgKoMf0qVgdHd05KcNusDkLqz+bNqx0PyHucx6\ntQNR+G/WKS4eXcAdwTudTPLXuqY4T5dXr3EU/fhG2oKFgHJRrAIllJQn5it+B1ljBrm8BMXVZC50\nkm/y/Dv2k1RZg83xH6UoGk0OEw29nx+XrBNqjLBViBHSdzLAg7XUs4irDXyfhxGycqBdvG0a98Nk\nxNU46vJazVxZWSL6U6mAe6Sv3Sr9jGmNIgA/VdbNk/SIP/AhthEjNhk/19pheo85ryTp4KL24Vhw\nrSotkbHebmTArYBspDLozvV51DeBkxnLdq1AwEdI+kiwzBbiud1p9rJEfRCLlqRYOI2rNY48L9Lz\nVwjSLp1+SKY7ERb2h+5bygkAImLrivJNuv0yj8p03GAPfu6DwfwlYjr/ZSn5C713pe6Imf5odEyk\n2g27gNss5gKol+0fnIRlZrAdBphbK+HDGns5LVFnXt6nhEEzzrhmhY5q8YS8OBSR09NzveOjphSo\nMFsa7DV6Mx6FidSa3xeL8Kiq98kSg/JzKmT917YSdmFImgN839ZxMPonkiRYfizHC0bcdFfVJC9P\ney50x1ZvNhADKvxaQoVppfhgjgY4RAL3yo8CNeL+8diNOvxxv7VXL6VmkVHb0OPSK9T7jM0UNC7g\nx2kdywCP5JyEAE1ZYgyfhp0cZseW8D3oJ03+f6aWUefyoDW+U7lhbahfjP9EC67VrkOC0aA2r1qb\n0EGdy+Wgbo8LwZqlv+i0kT6JJVzJAs9m9mIkVRdSau7A6EtZ++Gui0K56HTnHxdBZpKPLfaMY/Vq\ncO5ShwiXPBEzE8G5dKmjHC+z12W1EDxgsCLar9+YOAjxKhgHkBGfg69+NmO0ydwiFZtkb9kQn2n2\ncakas/WtmPRcBrFKxTJv7hrqsa0tATeeQxEfLYe4qtlUzpbtLY2FdoNRQlSxUGJ4pGgiCSx+x5ri\n5dbUwJzYin9/1AkNrajyQ1igqFH63Oe5iA05U0OBHL1TZbqVJu91v+1hHGccThB7kV/xn+sWCL0Q\nmMULWQqEWLR9aFsTO9vP+2fvOf6Zwuefn0MzofCFTwq/kYuMgyppHBeqD0San0S3+DlRWFbvQxtd\n/2tSB+nGWbiKevmP/K3gE8oRdXigzg7xbPH+gh2lCC0wJmKwTgQwHIC31x50ZJkg8cci6fVAAw/C\nVHXrDrjZSiroK8utPInMK9UgiLiJZaxnv6VMTQfV26pYRuUPBEPpZ4PLypuOIcDs1tS4X6nUNDU2\nfNyzzsyS7Fs6nTKsfTb13JGw+dOOt4lMUIBEU84U5RQKL+jrymEyKK/sSA4kuQYjQXLCHUIIG8G5\nHUgZ9GKsNo3ugw6mpQdnfJ5cW5I10H8JLWrMiCExw/s1EXPyeM59eTd7T9tDoN1rAZKPHG/JN8dV\nh0oYFXVBv9sIAGpOy1+yMXyrapdwkmnq9M75xOw+4tdRAWNlhGUgeer4qaGwM1AiZOh9ICdC5zLx\nBQ6+b4pwzgxHxvbCVYSY3J/6A1H2OWZ/DJsHbkCJzKyyIJI6c9Sj+iL7IWOEz3kPoTdwojbxnFjE\nFHyzNYqDISswQg6KXYsPWTEGpB/obQREvd+ABflTfjzhr3Tjftzcg8LURNmOgUQANWT1DWQSbC19\nmfeCmEA3Y+mKQXkzlCARoH1uXMPPUpVC1ipWTPqeH7TcwHjaNCNhXgDS/uk2Z5GBD8YiHzSvAuVf\nKZvULyg1j21LI/bSkfQ7+lk8ROtqWPv7/JtmfKo4EJbyI7aQPWjlTqdH9mV0ELtfD7EbTPEhwZZQ\nHGWfHrL778ObaVgVlJ+4cur5V5ysxaYVfZvWa3RzOCv0QqOo2lYVW6b1BV6cZPLYruo7o4VgOq4K\nzMz6Tv5RTu1X/Q0sXm1kmGF9b7w0Pc5x3QBxIGCO+NzcC9HZekrjxRIqqqG9SREDtovJy40tvW9B\nVLyL0e4LS6wq+BG21T5Tm3wStOhCHnyJAneG91iZNFnrTY57YkATwIja/JJiSnDtzisBcdOXsnE+\njF+WIPe/OXaP7EXFwWnvQcMy3CEeH0v9WQ8R0k7m5/5LJUSKZegVF2vImSnXZte3+N1jLmIspK2X\nLSW00mKB9e7X0tmoffFcNa5K91v5qCKZP+jH9FlXfo6FyNfnHZeBtYWE1rFrWkkNoyffdTydMxU3\nHsE7+QvtoAiGifQOxWPvyL6jtcKpDsPkZKwWMaDS6t6CrUW2+7FIzIySi4GPD+UtldMfOgfX/xY4\nRwOLpHM0qz77Vk7F8r5igDm3YdRUclJRj/9p3PhuaGURCCOfvYY/1YtGyn4pRScUV0eI5mWn2HkY\nPB1KwhTPUTGwVWu7Y3fD26njzSehEGb15soneI8/j2u57nBdio7e76zBGd1Ae28DCxlw6eheUL+t\nVfbb+l1BrerQeAHVxnm+duuLE+rNrPfp+17NGTOlB2Qf1rcFqQWYCmgEI+VzyOhWARntifEQ91cL\neG3JS8IW02lPLDfwgGnw1jdsBDrP490+YoZQxAo1kmK8lSjgUXuTchXZtHz6I8/mHaTDsZ3ZJQA3\nNXIjfP4KlMMnUOG5LiaeDZ03uItPx33c7XIlhC8wCHIeOQHEnRoS7Ah4f7M3FP3oommN4YQxreJR\n/uAHpkr0sCdoRVU3J+7N2vwSP685CNjrqyl78reB2aX7Ty3g0hVKTHlyPzRgA62N3Gfb9vMrk+W0\nY78yHpQHiYOQTwAsjZvyYBwT9f/ldXZVwC1YIvI20GQ7kL8uvhV/+zbXVzv6kyjHg6HZIY+D/+rY\n9JnqgDOXkANYZNab/6uv2j1ojjDqBOeZShxkJkbTwoWc1yT8OmnQVIXLmeGTpGuabFKI9Zi6Q/06\n+HPwkG5LawIar0MHYUs4lb8X9uKIVauJZHO3fCfDJpfE7p0weI+DMayYvriGCPSu2+0cO66waMD8\nkoQKpOmFxHOrio+PflCURVPrWAdtiOVWfTKpPdCUgyjcX/0SNGNc+GsKLpPgnseR5baF4rxbWWCj\nkZQJhVLuPemR09jsCHluA70+mz9AXQAg/pa7bfPbMldU69lewVO7xbwqdUDy4hdTZYJCwX9TNp1P\nNpCzdGsgoswj/88Cy3icvq+rPBdxfqogbUZXI0ZcBQuBSscM9RPagLxJRYfOWbvPYakgaarvMURQ\nUKkmvS7oHX3jyOH166f1V6kX7iU1FtSODnMP0RTIiVB1jMY8PPv20LD5653dtu8nhpW/yxdeaulB\n6HrUOModOutJHPogWpEpYquKf+DCjyztBIiWtsXp0rIdpdackzsWc3l3gZdiLtsV1BhLCsj0FJw2\nU26qRLCKKxk0axjYCW1xbCcNn2Ui03uJuYtzjrQJU/ng+M40qPAoIOoonXkN2va+Z/XjAlJvXRLl\npvwhi82zybVUV7GX+GBE0mShC/h7yvkzFiRrRDA/RwRQur+2okCdE6dK8hr1zzFE10JBP0d9TUS0\npK2XqZN2VJ/BQSHEd38SApjeg4BZNbFB4+Qm5v2hy9XGHVWFBr86STemwiPK/HTKyvHbsTG8gt94\n4Y361rCNBFPqISw38qIcz8ooUjFi622Y/CWCjDz21lLX3iFDIFf/ZxxqVSlJM1NoqsTHOTYaVwF7\nhlfj1vG0b3l+cGCZNArEGD9fxGx3Z8OwL7Bzs63ULFNDz9lM2zFr4UU6eL3vuRH3yJfuI3H4I77P\nffLuBWlPBg9kdeOw+bZrrzSRIRmKmYS6kOz3Uyn/i0ejd+TPM5dR+qHmiFt7OZjjSaf6pYIDxuFA\nDZ6PvZDVBcTDMavNkIcSkwsm+B0NwELE2BV7pbI7jpTpkuTQpZAIcuURtrHRXOohYiktQX0f2DId\nGDX2juPGYqAkqHn2O6TuzV+PKfUMTryW3TwkT2rIqBqzrGBtN1hU0JVrCaZAM1J928FQGECowe4C\nYw3phOU/wxWfcpsDd+JjsNmQP1GrNaLeCvX9iiM91ya+u8I0UPBSSpBhbDExnHRQ8x8L+Nxrv2P0\njVZpcPraT1DfqxmICYoVm6AY7rdTgJrjclMbYmafOsUk5wRRTQVAYPBpGcA93u8qLRqEvvDHhnS2\n9RKzGmNUV0hKqNIF4f426z0tJi0IkRW0znccZmt2d8TXKzYkCOfKAliSBqpZS7bodKplqMqc4voE\njaPXEf1vKkbUQOV5HqmvUiJPI5Y7jQrosCCg5VL2/oqN5DodmIqCCTd3vdAm/tt/b0IuI5mRfpP6\nV2Y/cRCrmE+MumRavYpcem+l50tCbeSbglB4grrAtBooNSiWou5vd+6WISoDxewgOeJQGew6HhaX\nO3eGe6KfJ6TaL3fiJuZF3hZ9XXqyDuGrb8nQoAt6dqqzzDpGo1JaPScwI3EIpud4EhFE1Qti5v5a\nV3Vl1+6/UJSBa8V/BrByhZyt7xmrFz+1Bgy6E+Z8DAH3rQXV6mKOieQAoUPkW2mh9tx9xnFpbSsZ\nTPYhbec2cj4bGLI5crXAxEScCC7qH6wD4Zgnd+qNl2NdDJqKJO+4hUlTbuc5wXXvarGBBhgjMHLs\nXGdXVwHOm+Cc8rKXJvr7+5PUUtnwD8gWKxJXPimyS72D9CW6d7dkhkbP7lFlaWAatkkLR5ARwFbx\nMZAF9W53PRE329iWi8zBjf2WDZBSN2Q0TcA10dOE5nbnbfeT01IkqmqARAkQh+nTwL9T3bR2A8Pf\ngmwCqBj1+5rRlYslJ8CZOrLDQgDuLDJ0EbX+JSDcQd6jEyne6hgAaoZs41ByP/8g/PE2alqR1kRZ\nTYhiSUk5FbaPSLijYoL5o1w7Zy0qqdH/p9GBtm4JO9CVzc6hI09H8Uk2lQbJPzvt9YSlv3v92sQz\n2TKxXXtBQ+mUlziFQ/8BYitiRqoE2cdR+mE5f1X1YvM49qIirMbEuumBGiHJqvkqNUZBHU0ZgVKg\nvobG6mF+vwwH28e3no4tQ7zOa/fDVprzZjLGnvdPUjym+XCgbrKyypqUWKJ4/T/4PjaanyzPvvXt\nRlcGp/nhqI4n2u93okHPDK6jV/5phIyTYsLiXu3CKgu+8IRYdXYOiIo/e1Y5WDTKYgQhmBVshF3g\np1hGuj0SPHrrAaGaEG0egjAyMEWxwFicIsMjvHDzms9wj7SGPo6CFt4YMfar870S3Mr4rqPPTLEl\nKaX83QSEnw2lHk1wIWIFRH/7JbyQRSmJQSWe1dyCNY3CJc9ckpBwv+ZE3JjOz/eE9hu5cxojJXoW\nlr5td8y7IAWzChiI0YLBwLJRGcSEKYwgbLcICqV6JillP9J4X92YlMW6BHoBsMhB1DOl6TyZgMNQ\nVlZGWfNoYelupoRkIT8M7MzXISDSzqoDIKM5mr9eoSAo8ib6YK3ODFN1Ipi0Hm+qUVh97Qb3LCXy\nJ6TLZ7yBPe3PyN9tI0DKKMQaEf7MIeR/pJVXBGsWw1J8lMeUKMZGj/PNQ8jCoeKR8IQWRQA+u08l\nvi2HhJO/OOKzrT7wWfTqQ8JQJWoego0wyxREKsmJVph5puuURbW1rqMZ59X/1NWVNk/LbJ1gpEhD\nRDB7m4Z37EdY60O5sOgWAgfgocCGN+qw4b+xKacYxMN4HjXO+wJq18wCTE6+j/Riq53L1N8BhQ8Y\nGzmRansnzeytnsaTfsvP369sjt22XF5RMpCRvIpwnBzhVtSbsoEOecovV9J60ihS9Fe3klm6gBY7\nO27ky2+Nqy6V5sFI8PXp8SBwkwq5pNi/BqYrHGV+KbX8d32v1RUYbRrV4F6ptibJnNz0aU+HQQBw\ns4RzTcJUIJhlCEM+J8xX7HwyaUGYXM4Vblpw6Pdu9uJT0tjyon29wMG41c5BLhYFL9bVxSB0rylA\no9dhCoNanyu2VfmWH0K1eh+YJaNXtEb0ysEmWhCOAN/BB005lvi/w2S97ehdtGEWfujIFXRsvCgY\n+RCIDAxVVZqHL8q746Y3NWuLClwgx1vHx1NcQUcDBNsRytgo9Gb0DigkKNt+dAAIGmfD2l8RTA00\ni2rxwGF3erRv9z6mzledqzEO17RKC31VFamUnhcuZiDRaRRCBnE8GuE5BHaK8rw79pL1YSIawfMd\nLK7hHkbaDI3kT4s0uTl+t99PyWMS/B/0yfBkHsKDGfriLreKrAncpEeUpJVFKdFGrPl1HIHS5ZEX\ns1gVTXjNJJrMestKVYaEs4nViCstGD9zSan6JhEmfaifIkJ7GLKw+NimA9uOzyKvxUxfRCCFUSvF\nMprZGCfJ4ltS0NYsdjAs1KQSH/5sn/PQ6OIeDHlZ/n3Of315bRk57pzLC1/aVqAi8XLsSRefF/uG\ng/x4R0AMUW0mo2mdnHH/TY/0iT8LYCmwQO5G/dkxHjhJRFJDZ3qUZid99q56MwmCVIj6WDNBu+KO\nQN6QM5N82dHzc1QI4OMalKCyGwtF1fJoK6eNGi3dVQTES3YoHYpJwy9mkxPa0rvrWLS6/4KyUv+I\nEDZZY6lbAg/ozYCu+01v8P5fYavZmOXKq7EICFKOmUroiCAKQb7RAGvnYqGcYPcJRAsDYdAoIFDU\nroKp2Ovcei4dqjC/IMmPpx2utomxn1moEPZkeviZ/h4Jw8M+YkT9VrkRWpAoADxDnDqVJm9CyRZ3\nZYi06cQ7Xi+nISoqnuU0wG4niseJcLPhRyK/eN25gKr33zC0KA1F90dGy8K2XjjGkAy166Fm+3nU\nL2M0OoqaJrHkmiE5GOorVEOvOcgQPi5mcLYVduX9edasttXX1GWuqS6e+TdcltrvITA2mCaGW9W3\nuLXjKkSpq982wMXZ6Lezt5GVq0xxPV/hocBpYZGNk1GnQrKh6TZ2oDCwL3BfXTqGPrO2BfEl6Gt4\n/y3kZDSf1MYEfz0iQOKOy+lWAlsnuPolMTRzT1cOGY/Xo5ZfvbKryDcTb6bhVTvO6/ytROqjAUmQ\nTHPlyl8CeG7hdq6DGm/TlWk+DtDGTXDeiF5IwFeBRsJPlaQ//IAkaAdtGnFztK5xLzNvyFs87v/9\njkbEu4pvPLRGn8alKJB8ZZ/E12VD5owB7dVz3WdKnfFS+ewUVFFKFM/LqRQIoLDfau36JyDEBIoK\nCc9QhI4knWpjgd3rc0Ror6hYufUfdIhZvbYz3935zgckWWECuvAIgdz5z2ckO8J2UHAmrLdWFxtz\n7NFYheF0uQVqIWu7hRMmfPVEgJNVslEfrtSENg19NvNy3vkke892kD/uoMfkVuyjAkS8PzGBrXJ7\nSQqI6VjMifzTsYMS/WQ+kXXwPhjx09QEncMmZSp0thPdg5CZk8eEvrZGprWuaWpDs9S3lN+NV/qh\nEaMcIGIuEMxbxMgD5WtZb20rxjLc674wYAzoVZKd1k0L9/5C0iSgJUwYBe49dyDOKYUMctmkESxi\nVd7eT/IqusXB5Q/PLFKKSpIjnafKrHv8yGyfnTaBC+kzTlVpb2G++mJNfwSbkDuqAvAoKjPAVHv+\nqzQVAKQ0+UOmw3T+29c4atCHzi2+uB2N0pr3kiOHQ8yooLRMdkn24q9cxynSkIZo1/dARHNNdxa3\nCJv1zraDIX2a9McxBdYXYYPeFRe//3X0Icj+fafoR1L6ZnzJ8pkqjZSGr7s9acLQGxabvRMGFAlH\nVSEB3Y7eWvxapneBKniIGGujM8MXaz15lv9RmTiEqxfRsxRhgthrhqNWOlGWfz21p8uZT/iV0h9Y\nfzfelebsnPN2uqnYGEKFTYTm43VLTKdViucgm0FyCsC5i7j0MIw20+J+3xPhA7x4++Bg0WIc2oa6\nyZWBWrw09oorWa4VXS9O4jd/qCs1lXQO9qyI4RaWmg1w/2nMaDgx3InEckVMCboMIeiaxntF0Oan\nPBiBdb1PPzTtsMmzVNpv4Fjv/cOEPRIRFPibNg3qhLCCRI7H9mgzfUzv90GEsJjMVTCAhWsuuHo9\nwGzpvadtd3ZPmPsOFa01NwPTRw0Ka+zQf07NZ5o1vtUsD8QeGQdLQQ/Q5OKw2HbA/bmpERHgtPaO\nU2pjfnadcng5L589GtL1Yn1o8CLSPo3GBOJXJ+EEsGHxmSytk2TceD72Fzn1at8SRZcjtsb4Puy5\nD6IOS7UeaGPeKQA6l11RgJHgfZbUgaJmK6tPYXZqXja2NBHNAlJGUGSUdtTyFwrSw1v9Kvbta3nm\n9dSQggcFLN0jfOh4Wx4PkZqrNAn4aYXAl1hVDrYSJYeIi/g9UWvt4lKEKzII7sSP+/Smvc+DQI7c\nKrUPoBrCwwSIULOWIvTrmc/9H9lyRuvvalVYoO1UJ4h1QZ8l8Awyua3XBfn+LhsE5y8En3VMKVBK\nHDDhGXOo1ly3kQ8NfiYxpwcHcNdNtrv6maO8YQ5GRGqef7AdwOaB88p4d8Lo4SDu62Dzf2fkdySN\nvx+zps0lGn2ew4IFCknQaUtUaHVrSDUG/NZZQabVDl4WAdblcpbCOW8uTiNoFIKFX8dP4RYXgq+N\n0wODhInglAFqObFfIC84RBfDlEA6t/45rPMvS12+uDunWBSZHyVY1Uwvwu/pnI48lV9m61OsJCLO\nOIgrpGewilIwhStXkjxdI/PB+Vez075WfTee96epvw8Gy7kPD7RFvqrDDIrSGm93FKnRHplTj8O5\n5uu+yfmzGBWYcqCbo4mJK6V0M/SJnB1HCGbgLiRxGy/WnHWjaYx9bBqMbBHImuGlpEzPmfDKvgV7\nAlHvpdpzcBlf2iAEr4jhpXqh/KwnRQ4vJL1P84YbChWf4s+IKE0AZ6f0vl7phKgUVq+P+ULvZdoT\nqnWO0Ig8FCSr/a6sZumTd2V59t1HdZTvc9V7LHv7XW1ar8fwPredD5AYEDMepb6AgFxec1FiOc3D\nykbfBhIXJE6n+Yn+BkBfyPaHQtr6CygbQYqPxrWvwqNaGqiR4M1+SnXc1ZPUCuO3jpsqErNCpGur\n86gev9iN95nwRZl1czxWVa9z2Vups+DUDYNl6OGsA3VaU6eY+zfjdw22WdfBTQW1yLZbKdfPdglM\nk0W3fK6xVQmWd7Q0MFJx12rohylS2M3jRt6ymRYDuj9G2x7e5COQAH4HvGSj1xQao0Oqt1esrJ4a\nYIqOffOvsSJq932yvAK//wpl7jU/meranK6kL+SFodAzXhE5O9i3yUroUaSX5y59xIfZoFg4NHP0\nM7zEBF6QB2GW8onP2jBMjRx1c2YyjCZC9I2gxLVNFMuAynr8b5R66ZPqvrh/8y6Mqr83orbrcV1X\njrDazLR6yHEOtNQ4bi8mN7w1RxzLuL2h058RZGlSsTBsO8xP6HAr5Kp2wBfbvI57lK6CxqUspCj8\neO92O5CNgGOfYdotXRnXfVffA4XKFtgvw2Me/hq6OXRjQJn4ru2BJA8kDP43xdNfLhkeKIZM3AoG\nTcMCW6giOWLiADsnkr2ofGgeUFbW+ngIOyctXvMwRFMD+1K5RpwKmd9uVYsHK5u+PLBnvBGoyoS7\n8/m4+m5zQh1ucW8F1QfRwl/sKSrRq0ciF10lQ6zYZB4lLAem6FOmUFaoyuBVPiQdDA1ZsbW/Oy9h\nCVMHPZwPrJ3UnrPvs6YOfXs2Jlfc4nyTMV9gez2SwA0MbPHMnpIcvsBYMqVf1NbZumEG5UI4mVji\nsP+Lo3Q+cV56vHImYilS916X7mZ0gHna6WTTGV9UyJ+Du3k0Tl5TlYLHL/ob4uKWbj822Gt7tv23\nAJnMLGCkgZQbYYRLwv5C7jFKxzPsaYrdBbnhN8Hzj8uWglOv5NmXOcg2pNyIv6Xp7o3P4/taZy/s\nbavizNn1qFu+wczAKyYeOCD1GOD150qXMwDfJGIaD722D5IfvLbBJkBz14/nzS42fO+i/NSflxqQ\nIh8W1dHgXZR1+1xGFhfpNgJ73eVqPltXA5/xNtE6EWKAK2h01+j9T0mPP+TCq80DejbANcjNu+ug\nQ7qp1/IN1oZBnRQf0DNejhOdZ3Ik88Xhwy2Bn0jLmvR81NTNbmVEoZf6/LBhkmC++d5tWUODaE3V\nMmjV73rV8eAB0kRkj3yGu5GLwWEtbau6TqRGb0BcVzUlzqvF5MPetFqKTBQY6sJENoTXq1XQjWm6\n9wH63KFczwcmFRWNgBpkvjQZUGWcCIlioS4fuoQg+RfiCszpQm6etlOglZq6tbo35s7iHLifH2fJ\nXgBvGhw1Mzh5WLkhF0SZtXs1flSvmLCyJM6MwWBe9Vg1rncHvsaqt33+9kknBEsl8yJuvLzpWHIq\nIOyjgBz9NEl5RNUhBXzOzvIRK9F3Z+fejM0uOy+z5JQfMyUHKAEhEtGivvnuKn5Iv1yGYQbKcWzf\nrLxAQP1WA+5zJeTLRbU+kco9GYRaVaIvruvNy1wYXHcRnwEui9exP//Ej02tNULykhUHv7P7iTnf\nYCwad9m+QexSnt0Sf+x7TTYZGucEUC7Y4EDC2m9MsTtXFuhHgin2e9eHMTm7cMiFUf3O8h8Qszop\nwzWvIQZOkkv91HzJT8h4L2b0+s0LMTK978OOGCGHEcqUPGyAWN7nOu16o2UjvQGFPn79rD1sub3W\nU+zCmNvAttFgu659SJhYDXnvhUoNWhfY6acclg3KD38v/SOAfl/eq+85NRYWvJtweiJRYYtk0vVs\nu6EitsHfSy055na+HIelCMTPbv3+3OwB8KNeJGveU0qxSv4okxF8YWWxztNlTRVWwx6fC7LrHTJS\nXhjvKRWBJrdBkAn903FdNO406+gwfbMP6VAaTCMo2gsunicIpS8xTA9jcMdcnCyP4GXLvQi4UckD\nQNgqbWYvw5fxTLOWyf1Qu4u6Ul1cRBRNRqZ3sZG1iD58EIMSS69VEvYM1w5CWdFFkYZesNsF2ZAC\n4RTSQLixyOWbPHcCckgl3/E4FZCkIi1A0xsbsyirad4r4OdBa4ELnPi0ASWPuCJZp8QxIx9ohBTU\ncXKA+rgTrCgCLzavqrmNtp3Gr4WW1sfls95t68GeO6SScz+13sR+D3gkP998Q+3+9ENk5i7fJ9/i\nQcLd8GqnDZaJ/h36F7+cUQZg67jcA5APE29UEhwTU72sbZWGcGykxoFo6Wu8gG9xLNC2pPVSdS6a\nF55fpU0b9k7eoRIM9wJyDoF5jVRrL+wNULRlvZpfiLOpSwjUKnZ6ljjKtTt6qfsye31ZSpQbTEDi\nei67gpANY9oE+l8zI+oIf8eBQod4TXK0aotrRsx0T048+WvCuIiR+iczHejTE8Pdi8+enWorNp6u\nCcR1yfG23NU1xEPqbMjQdnMIw2T7xx8WBpnaS+nBJ1gNENmT+JS56BNxD6xy5OvTLAQXjtm+KiG5\ncnsBBCY/Am/rByb+pNGepykPoma6lXmXc5FMpKsySFKxXx7y5zorfRE9gSbCmTG5Ltvw4142R91i\n812qH7JQQPaumVCKm33BGCVGuitsJfOfv/98p8oQPsV6SftmQusOjQSyn5Qm+dlpy2+VymZDEnTc\neJlGz99qQGTvq8/CnYHNoTodEyCv3uGGGoA0TqUo53dr7ssSRbAFgdsyRHMDxepGAcjkw7T6laTd\nqtTg6VF8hWTkI7MN6+pMfl4m1JUI3jCTvL3r/vgV6Kz3ppGiAoXiSzxy4keXJ6PAPwFmbGMVtZay\nWyEhiliGvUyzaYlZPptWWhQOtNFU7fxXPiYE32GVZIx+SiWJLnWydxbRC/WlhwgNYcGsyqSZMFit\nsNGCmXGtYx50tvzGxQwzehYg0nZ2T3/PJDCx29bJ47EO9lmaIUUPuHUmene0vI1Pu3WArggyDcZm\nv2T2/rnn/OkCTuK9/cnfLCkG9PZvw+b6Q8iqL81fUCaMHPspDM/w/iL0pGUM68CLdUwOhsuz9jrD\nADfcq+EHTkeSm1tRfg+5QtFa4PgsUd1tA9j3+oO8OS4wuERtXT8tItcS8PjZuyin4U0+G5ec8xRq\nNXig33Ho45rUFp/dzkeNN1A0r9jrBnzIxzHAQZgfdTuGWuttmgbHPe/8AhXQ1iFepoTAzqrCqBln\ndNdMPtSzeK2ZoMaHjCWqZs+s8/+1seQjregjKaPbNxtmkplWus0EExT+udkoO7IXvlQq7BgPYo4r\nRpjeAfQC8Li0QA1OIq++poHELmQg9Sv753ldrgUe7HlrntwA8pnVfa3P2xWCC5ti+tEdtMl2Z3R5\nahgZisYsB8c1LNpju99Cd5thHlHl4q8bD77qMmBldsN89OKNqPHdYrbQUxFuR0cSUly501EUip2r\nJwNftGERUEMKhO82u2cZQzDhz17Ttkor/7NeO+Z+DrmO2e4BlNdtNXxiWIprq5n7njgKw0+Y31Z9\no5bBl4zCMvNHlQ/IuBUEEIcDEP1SH8hlHzzCrOoA3/6P17v4Px9APMiiv33ExsXH8T1i0iteJS07\nzLASBPvauUC9xNjitpan8V2eHxBVPDkLlNHX8+hobBnp5vRMSQcBO0JFm33M2lSRBE9ZNcgYf+g3\nkB2CVDaFyDLLvhVdXW034NGCc2deKjNDfZrSkVEFJH0aDJoEYzxeEnMh9d5rIKx3VYmcYHgw6JGg\nJBhUkNHmCjfh0vCo+hjMCPwH95m3vUFe1wKhOoXsIWyk1QJ+QTR9t+hZTowkYlQprcv5t2gWHJYG\nys6npKLa+KanvsrGVrXB32uysIZliELY0rvCu1lnLfOVG5o6VxHS66qJPHimhiy6XX4IgXd6zZiW\nYO7BOZluVxA1fF+ajFTsjY32A70kD/tRSPQpYwH9EMaoF76kkDLhsIobb2kYNomgtk7M503onnCd\nu64Y7Grs+FvIkcG6rJ/SZUqfoPbCZmvMJtxhS3d9eDphfgzSyg0uEcbc30Scvx3MW/Ka45FcPqWU\nTTJuaFa5sYSLgrtp0/xa2z1ZrvplfUMOfs1Ir4WbJ9S9rWOTG+MOlyxRJVANozxhNnL+p0UxBvIK\nFUnFSYxOeTffvL/9AiuwYKEGlG8TP4W0kgfeL3hMAL5gpcXggAW/2zDLba/syJhMD6Tp62ZpzZTH\nz/IPQv4NIEnBLbQy6BH4d0wGaSLfPyXvaUjY7YQ+ntuC31nihw1bQwaZ+MUWyZRcmiX5r9u7+XdL\nI1L1yZBLfdvFM+nIfXra/bYYxC99jIKFf7pNPlxoLNMW5ArXRg/FY+4oEjkoCU5VQUgZUNAuJNxU\nkjCdWYT/MrC1tV8BTjT8vgZqsUVG+9Q9BiJFhhAhyxYKch4SAtURNyGrLtp0SSnIYJ3B/ZVjzn7I\nxuxZZ2v2AflGdJfcDL+Rr6aLQdbjGj/+0zoSVfLZv4JbXBQwhr85A0tkeg6cGcxR9Vza/zc7+M6g\nJ5ccWZqPWubJGmJvKwm8cnMa+pcVTxa27WsCDyvS0Y68jalHosyqevLvcB3xDPTsn2uHlV+VpQcj\nV0VFxSXFpQmg8i91a+zS4L7xHHbrjcRUly+muThjtgw6ig/wF5IxtSpj5x7igdPnhA36Go4s6ycI\nIiK57NlcBNfiebdpAbi/w5sM+taV1uXqviHauEuFjtQA33Ok8ch86BdmtrhnfMrEJ8rHapBXrVht\nIdcFv0tQUfg2nx+8xWmAW0dbKjOV9EeqQp0I4g9LeZD5GoAP9n3P9uxbxza4GAUXxvg8YQn638cD\npJ08vWFIXQz+R7QyyTo9sX+L/8OhlUe57VaGzoGGHeg2RfhPUXKQ5g4vkHkUQq05nbCCuLIsc/NF\nA9VSgYsetAZd8ab3oI/3nSeVQn9BqI6eeK76MN9q/uGinlJrJwDKg2lAwE4Sx1NtxZUDL5Qng1z2\n+lwVJzNItzXwfBtFu0TCpNDRouYbIY10OgzqrgN8p1Iw4yC4fdfmvvoeJBaWzueEUdTT0lR9CbXg\nnCIcYnStmgLfad7bKNKuZF0N2BdtTyt02DP4LzxwMUX9zaxXo2s/7FBfFcU3FJuvYBvJNxclo8rd\nK99uOpDhoAF68Cp8f3U1xGQs9hcQFsIiZxeJK3ILBP5gp+CyPPneqHwgN07Z3h+9wvOFgwV7PuNs\nihcq9INZE5hivSIUv1J4uqxZxw2YOvj+4XtgILMDsLBUh2/CeiJHDnRXHHXa8xyHN/VEZlvP995w\nphboRlruPD5mR/ocPYK7UdxRiSWJM3aJzUcLRi955umxUm0bw6N0pSJ7JahT+I2XC34PwpktoFJK\ncnszLXBWbxz29fPMUkVIgrJLImaca+mZQRabAzDdtkZVBJfpiL95/WLyAlyEFqHx6pOn9YdqK/x8\nls+aAzMGETkfnoOlM6je/dTzj3l6Qegyttg6hacm7+dwNcr5RLP10+lmLI47KpEZMRH0JtDps/ey\nRtCY/uN6O1UaJdOhdtyZCpou6ZZrao39nAAK3hsYPS++aZgjVAM+j0HZPfDxzqTE4Wp2AHE0vEVb\nsbWOC5JkhFUEsNgxf3CZZek4tylhZBFe2qAPmca7Nr8cX+/fGwJa4zsstW1RSHzzXp+ga7T04RRj\nqKwX8lhMp83DKrFARIncMkCPhC9OchoFv6Gq/qOjB5ENUspxDy4S/IOsNdRpKsjsoA/E6+aiSeQp\n3DWa071ADqC3V/jEDFQxKj++OP+/pINq6Y1craLIugETiEcpuMZtIfeNmTtUQ9bQlnnIHSMgiiLk\nEYO/fwfSTz7trn+YBvKL5vAPEgd8EXnJTQmYglGi3iPtfYZCecyOfq3JykNYoLGzlc8l+lgHht6D\njBryf+zujUdATobQ6vmyUQSCtmPgv044olqWdpLhzoc9ASuMzv1Tf60b+vX3nQLZbSJuYh7SHxUc\nGxaQJbaAUNbtxB873Z2xQaexfwD0XIgmIrV4nTsGA8CKeZGD44WmVGfF2zAEj0Suw90pvxZ6ak52\npnNXRoiYA1GbUbaAPifn9es5nNMox1WMhiiFqkfTt6QT/LPDaI6pctEEKbhZABvzuC+AFV6ApkFQ\n9sEbC67oJqc2L/F5+EIi5bC2E4TuVw5PGllkgLBAmBS9ZJXLt8W/7AZzh2zXOiztarPYrGxcQWQi\n1NqD9kbqMfjq4GgxdfOh6GXp+/8hzguNrB0XOLT57jqu3ukdyPI/38f/tdSR8rVLm9ctklpFxIp1\natcGe6ZzLhkmrAWaEgXu+rkvalDeJJzYMCdssUggP9sbyIBqNm+bu0hs27axwtzO0aLTdEmRy7BX\n02mW+0eM4axPDPBXp7Km1zDETT9OuwhMcrmk9IDiDrbaUj5u9Is6RN5ZNoT9chv4XZJKvLR2ut3e\nQGCvbdUAVHxPLCOslYfGfXiNFdwL9ygx5Xv94ULNBynBX65Yc0v5uokgRUlQFr4KxsdMcxhnJrjd\n5mKOOdcKDyXcYKKk1YrFmxp2Mqa1iRK0gm7BoGrH6dy8ZY4obArr8X7BYzzkf4oUx8I+5e2BLyig\nSCmP33zMkZFpk/Auh1rgfxz/PbMciaPSHZvrsiCsT3mIopE+JgltnrrCcjK7GAdB5hrTS3w3SR1y\nGBavVYxjiEqnr8WlVGP5HbH08fIsOBlMX7LO5sciII0cGlRpn364mCbdp91BslmVrQoxcPaj+TC9\nO0MZi9C8aOZsUVk7GGBEye2EQ6zuEpA0PE6X2sUd4HqfaTrtQg1EivraNouAMLztKnLgN7pU/ETf\nK4iMYGGJzip/SjpXL4XIr62c0IMMYJzIXHBaTyrZ4idSxkM6S6Q/VUPOjO00HKdaRqOIH4Fl7siD\nQGdPpuIRj0b31W/7wIswcFZmCuzoZQGgj7b7P4nLZ1ugw4MHnHQ0p0zWM+A+R01iDJDTBdfEPSsz\ntVdGAoTuJ+O5nYpHMc+IAOA29tvUF0hLHKvwz719ElO2436olcY+xVc88CWad1ptcp6aodqcFyUM\nOlHeSnAgLnQRB4lEfJKprHEnN1TrjL67oHO/cABupwcFGBhTJebJn1u/nizRAVf+CKSUryUX1plf\nq1Wg9A52pO4nv4UPs5j2/i4PgDiSZY8dZu2YgE043PYJ5dEjNrmyvjaWkjFwtziqqKJ/zAwzxSfY\nFx5VOVen0XsXcoLpFHKH06Nbml4lnpDAxCdCAQlBhJagIUqVZUEIMzzBgaOUj7Y0E/Sx/MU06AAm\nb+hjKhJ4ht+9FDe3q31ngEpHms3C2CB73sGjLP85VrkgocaNNOGwWb85+dtp6SbR1oOXKGSgDIuW\nWa9nFDdb80zA/9MYuiTLZB0pGf2ysznBH4gVaJ86M27pJbE/oidnAlTQUPvFB38TOYQNTSnCNbmC\nBY/7Vz2hDC+A4DHGgWSJ/wWGblIidbsZpgHg1Xo8ekbgWacICP4eJRnFY0h99QUPrb9rr7nSKoVD\n4fgt/CUrqX9nvnFnEEI8eiWD+oHVrQKGRK6TnOP/839TpPTKpwfa5Qlp8j3ABCliKMAkPP6HOX+K\ndwjGgNzWtsIMFH+5fIx94smDLYyUxaUiQLsy44s+y54eVCf5XtKV7oMkEfvPoBAXlmhHKys2EraD\nKquLZQqsoRYc87pUW7KZ+/FGw76fQKeccRJfucdYfj2hHBcIaBuJUIPKrC592N7/WwEBhSd8nLa1\nLZKRMwzDGxXGYlmDMwf56Zf6OgqrCqSI/SnvV5mzligO5Au0AT5y8UGRR9x2hTLAohR3HhVudEXO\nowk0UJg8YDcoxxu0VpwoNbMLIcaEY1pemBsAdLqJhGMTRnneNxKrTtSgUwFN30HpP1fHg8FLhkHd\nFEhXXm6zT2mMHNhNgq8nbsHlIZj6lPdOCqJht4xkSQhmq+b4kwFjsVIOsR+y6Mo+C1vtZM89MyCi\n6SWt8fabXIQhJg+XGRqdh6vVWl5/YYso5T332zDvVQTlJAIu30bYPbZTre/xqhs/eG5/01Gy6nQd\nsONvdiK5TjgFj1gAUliaaUHi3VsgkrNExifz+rXAoecbj8lpEh36t3rEyvXjjGsAl6nV1UgQiCOU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mjmT3stzC/Xv3U+2KUtVN3IyoZysXfApjzYPxRGoY14wxVxml3cjWkid8wTZt/\nqKiZ8+DNGhOWsKqtYFfzvK3ApRuFrMQI4nmfP0ioaEsTGAw0TGjMc/edUC/KrxwpP9WbWlpcR1Mn\nyRmHmO1G980fLf1P/q5GKog5mVjHFI3YGEOry1qcHAJR2dzO40KJ0/5N3/Pxa7i6wNIJh/mHzFZ+\n31kRMiX98q/i5AnwSm6CIHRH2WptfuJJu8bOdHyEc2X/ZykVW5x17fso5tTlUjx5p+HR96FFUaBH\nlCZQUHaHREVDgLoo37xNLUuVkMHZqp9r/Bd63iatA1vtI53HEnJpU6AsMLIsCdkY+Lf82Feavy1/\nXEAxqjo7H1QoA9YuFHqbS5WP7hI7NfNQMDjoqprgcz9/UB7xC5WYr8rq2d5mgeAbnstt5tE7sQm6\nQgLlHockY4CJK8Xvmv4d4SblYXDAds1reKTgyhuI4ZtI4IEsIdiA6/FCJ2Vtw+GFFB0zIWutZ9Qg\nvRS3DxbGOPG7mDhBr7DndSkrx0aocMGbybimWSBSg54OO8poGqinGYfYKzIcnpmV8De9rNUYTd70\nICpozYFwIfHD6uW/tcf8vX5K9TD61i5pXIBimaenR5BI2PMYIhZxYqmWN5m2C4lpq7eUVSFU6cJU\nDopA56H0YzS1Yghkaz6ccapw4+IWSfmbW+U+xxGGT3wNd/C0LkyFKJzdCEZLxeZWC2Om6YAKNHn+\niFQ0gxa5wWQPwuJ8ZhYyqSk/q1Ta/GqqRzNbWLlZC4xztgz3JY1yx0g4gGXDKlO705YMD2H1sVzh\ny8FE+koC6h6l4i41cL/DFsmJm5Jqj52bd3iigktOLK6QtleXtA6WLojTYOnJOguFYPtthxaSvmGm\nqQTuLmCdlOWgPxQizNJRMRBTiuN87BktKycizvXRwigxNRv5V2btiXkJPtyPyqkLA4WN6rCMZBko\niXN3m7e9ovTge7aNZ42IWrAY75oe3jrfzduFMjJB7BHwVaV1dNpZqNe+ZP4gzGhO6yKU6gUhhLjo\nhuML+408orbEV4f3IS8O1PfQ+c9afO72/Ivqt12Iq1YNG3EKdwt+NulV+j6oevJWc1U/vV8MrQa0\nbeVkn5LMWMAilgmbX61R6wISQo0NfBGdFL7yL76BwJ5wauMZ3beZYu5smvlVxpEwVhQ8fFxH5Xpo\noihRZCSnp0L/BG8e+f6/sZJ3g939OWCjOd7v+b1g7lOXhRH12gLTb/5yvbYNu6R73tarKDzA+EDC\nV6Cjc0uuB1aWJB/N+OrNOcVXKhZcotiTMF4vDqfRNuqt4Lr8gjOQdRbrQEveoS5Z3dGPAUi07lqg\nqVZaKQNTSVTGNdFooKDV6jxrbpDI7VfHYQeRlcfaGQ1FG1NFjzlHBtwZAFGM65hXUyuLRvTsfmyJ\nKoaS6UFC1MuuQS/l45/VFm1tfQmlNWunhV0kpPrB8jg4HzKBk9f2BfqoHchtOGcUKTenprkzbPfn\nw4lemz9G4I8Lj5ly28uFVHheaCmKS4+8HGNam+xtZvyfd5dpBY8AcoNMtHr6i4UmfWaURIdijXdH\n4Bmll6uW4Pbk+DGTBh4mPSh2on/JXHVKOI+tXmcYauiEje985N91S+0Na3tbw+coqe0WLnAcRjrm\nq0HRhBFaPvHkoNwuQKN20uBjwavtz72na95RG+VD89klPSBmoG9U09U91P6sJ18GtlDxXCP0UAvS\nYwS5AWhwvu1ZBenlPuvRWL5SCxKd60mnVbKgePL10ztCgNJWKHL/tYG5erl6R7VpWRMeuAsivG4L\nvlZh1VMUk7WcEFtlQ8ewoghZgp/iUiIGdB8UYFsMC2n0jF2KlbD0qxkuacheyV42MhjTNrWOGJpP\nb8cLqovTnWaUaEQR4ox7qhg+i7lW7pFMSIP9k6dZSVrywanuiKxyZEM8txnRmifM5BWdVlFe7o4Q\n6LDdZw4TPzfPC/79pncGr4kcfXBeItIkCz2Kb37YPXMbPvCbBJ3buirX4xlN4U9Fzi5U0OI8rI/m\nxEaubhXYIo1C1wVEbMmhjjAYqm9mdtqwtK34nKt6UA8yzfBAKUcRS9C7ComgLKAnsqqYmQ6+d9du\nQEqBOA+dGyP5ei6S8XQuTmoeHBEzJtkaDcSReujBlwUYKT5jEDk0nET2T3W05RN8O+I1iuCL2zEk\nCBa9XojaCW7WnyD9fHIfIlVP3k5fyrMDshYPSJRoF+L3za8tcsFxoTB29Q6BjKAxZ/R2U7piuOIo\n3MRAXcIwBS55HqoJGM2SsAP+FtMEdbi9rvWNynjnYLT3VWrn9y4dpa1PzuBknAAIADZ1iJy8w45l\nKMoZndthreWqtx5WJ/NDeCbjKlRUXo+VcTOw5wfPGjtROIJrk+a0pBEvk9IgkLPXS67zcTg3SmX6\nqQGKLp8Q4wEM9wWWnL2h6O0wifvd8KNCNPziDdUS1b31LePR/mZo4s8QhVTskrjHFAb4QUbPl7a6\nHLudISZ7yV3Gmp6lxCIVCJYIiPkLiVfwQRSQViwIUWt6BCc960d/MqoOz0fwpsTkdjYr+EqA4FGJ\nwxJLPlTgl2lMVKdWumgkU6nREoX2fmCnx53Jl2LcDzdxTiKv4g72G/QzytkzP/3csANiNniXJKyb\nyPEYM+lewTjlwyBrvA1Hseq0rwEyuZIohPauQrtMD/CqgPghUCPc1zEUWqtbD7Cs6Wa9Q6i9cZe6\noygam6u4DqOHve4zENyA4vn6BeFcxUULrbhaf00LyIK8JhVfO3PgfxROzcPGkUTDn9lNMcgSYFw1\nF5h0O+k4KTZAuh5WmzhA07pUadrHIEWS84zpb597LkMmlP/Ir2b5DSd3a9WrRzXtffoW6wj+dqC7\npakKeVaDaFLsKew4NQn/5Gv2SSsl4XFUnLgN38g3e2L47gMZVmWlB+Y2pxNwsAyXV5zrfZ66+6NO\n/atnQFy39BdJa/QlM1kXvILZzqUOXKGZVYZLaTWJEug9PUV3sxznlaY+cyInU/Zyp4GnlbQ0XVJM\njjTgTXNLU2xwchHYZ2fBegrJgvIFGdryBZ0iiPdHvP0oKTrobiiLLzbV6OGhFV17NAM1UtiiGvmX\nCecPeJZhMWSNd1sR0zXBMsmK0TzQz9wCoe+6xVsyVVjA7V2FOPwHS/UUbVQY48xEuz3BqvoRTDza\n/Upe/JHbXSk9IhwLJhuQT51Ra6cPMWmXfgxXBAUVwMzzMx5nf38uLxEbI8HuxHJNoAr5GGRdDbDM\nvIaZdGD58IBnjKY6oHp0HRYu4WKaLDRblLUdGdvRRYTa8gDWhSNjXPohCsckVTdJP+6e2e4QOj4j\nERJFaK63X5h0QsmZOgpBr0rJwPTHnVY6GB3YKBw354eubQ9K7LofK66j6q3zT4Guf8RJUbdEAwPX\nO76Nk2K/YZetp9kO7l+c5cAIr8TwXPfl9w6+CZ8CwysJcd4GCwCkfBAE6qXqEVKayXnkzL+/gi9q\nYhodZUcg9N6TE/MQblA4jb3J2ttB1IdT6RQqaipYfiglppdRbRW1Qij7hpryOT2LWAgda1QDnOCw\nN/aRmOHe3cYkOP7spl87Ts3hk7E2Ax/UCeVxagIHpfy+FrsHZ4qiX+k649T/cfEl5rBbvmxA/xiL\nCwG9iyKqxglcf46ESxutKiDbBbgTxm51oe53JUdUJ80WTQ9/VQIlCKHVZPeWam1by0CZhhQ+FHPz\niRM7iAkCLl0ad6jbmsTBDB4Yo3j9GzlRn4OwfvkX+1X6Br/jpb7Ods5R9sYdCU8iirwHrrDeyl4P\n5Oa3TjRfEeRc/j9P7DyMx3ksTLodItG9x/vZWgOy4iFOa215lI7+X25rZS1Ummp/5i+Xpg/2bqL1\nYc6h7fbQjdpHUXjn4QUz0LYvmc+BNdDxx7TgSkeXOeHhdOTNPZBaDLDk2cy+lw8H7HLME+RVBt1k\nsXgcUBHjvvnpcteXo3EY/4mNbR/ZqLeXimXlWhSbjhCGYDzmqa5rgtz3n/CYymQhxCskPAQGw+sz\nezc1Bd1Gs8eiRp5AYUfgRpr4jbtwjt6z++6Vu8p97biVpBs1ExN2/VFrFqgpOJw9uA6QDmVZnx8t\ntsVnG09ksxL5q7LXryPT74zfhepy7+7aTH5YUpDpb2waeTIFvBdg8gmxXZB2ZJNSvEFEPglZ4KhP\ns5Wo15NcuLVfQySWiiEeFOZVqadoOuNZDghUEifrUf+33tFg6SeVx+zBDJbH89YDSGPONwYA8KZ1\nllfpAVGLBseobFKvocGgdqQf5YsUQQL2aNanPQqWDHJHr30u4IJBVKuluk8tjx90eD5z0fjoCqq3\nJds3DQnYjrQ7BU2xCixiaN26VICrnw47sIinfFcVXPidugt7ZC/KdJ/aQIVQbkrgDLjDxprUS7W1\nFffseESv5PsMOXQPCsFvlKPUCAAM4JKznpl/d5fx73jhcyMXizSXCoL3+8p/2BFB2u1ZYbisTH6V\nHLzAnIYsfS7eDvpwedtN7UZnmo/srjqJdMDTnCXrvGjHEr7252l6Ipuygr6C+WLPMQU9rrfvIwyN\n7t6vCh04Uqaszzc5CY9Aglhmwt/2Y5fx9JkGZumJynrdGXP33p2621iPJ4AevXZ3fdpNsCsmXnzc\n03cELWhMybwOw1YYoFbfYaz0s7PGleQIeLnk/884jAZTBzjHWSoLCwehSZqGTEAap+F/qiwHr9if\nuKfdQfIf1sOFlHlFnmEytGa24c0rloKQYqZPkuEVY7dS+SDs3W/Bcfs8x0goY2jaXFj4ZMP5UuTc\nyYDHI66HFcvlFknDksj2QlDgRfqZvhK4nKn/ov1YLKpHRhjo71lyHjJm2VbSQ+0OKQv8nqczLIpC\n2mynrP+VJILPijymLq5vCPGo6QllgLdqvuNKBIsJJrlMhIMyMmnRNJvVS+sTiwwsxinybxQicOf4\n34R6e7oY72ItEWWzrwJMtmMMcQrNBoRVgZsDnDu3B/iLN9B445+Ia/2xI8tg4h4bWVtfUrPF/GHF\nCCMcBaai/7iqersKU25P9YqCrW5gzK4yd6hHRVmP/GReTSC8etOcS/dQ+iH7YAw6g+VqwGCE9NNq\nrDHzSFNHzcuTFPuPTnjdDyBuk8tgZ2P8L+upWmAB8WRT08N0FYWxRVHTgdWwIb++kpR4oah3SMVh\ncMdDNeDMRXWOPYx+eoBFG4TdDky/+Rpt3Y3t+kXs5rBtuM3mN6lO/N62N0YIWBy9PPROt6ABLhjn\nkTSPxHFYPlq+2tW7Yq6PpB3gOJgIpw6Jd2FVY/nnHFVGLeti1SuPxoqA/zB+RqAZ1ugF1/HuD/no\nlOzP6btVSLptufMfKGXQlqJurAbPNswzU1SgOzKKgJWsBc8A1dZhUmmODZr7QJWHHjXRe7yJioTB\nSe+1t1P79UExlkY2Av53wBpm/Qf4fP4wQc1SW3DW0IMbQtjt9uv9/X9fGV6/G4GCcNq3idyucymc\n5DsqZ30iU7nUPo5TDk2xTfYTo5J6KDFbWg68PBTUjc9YU+xUqFwxcpfCVXhHxosuzfUSnP6d8DrK\n3sQNP4khBnas9LtuKIEewVH1iv2IiKUdT79XbsL/vFcNBq0+Sqvvg8Mk/IozOebCZTqLA+pRh8j1\nPO0dg1EYBx38k9kKMWWaaucDeaXpyGKEurCt+rNNj6O3iZ4CRZX9o1/noytgel7upuLBzZqGwGps\n73AtMGLpnD77WEcHmk7vCb/9ZIQ/1JqILIS7tWQrpz13TnS0vYnHyN54RndRSVrH3tV5/OmRT8Vr\n86wb6pLSlRI3+LytODQtXr5Pjm9zRxy6ohZ3KULiJ++p02B77O1XtFtNs3jRNxHwmT1DpOf+e3YF\n7zwucJ1nuZyIc7dAzGodikj09oxWDfGZLpGvUv8slbHALDP09Q1sZYzbZb1WMxARlYmMMbOMv6bp\nqXEGb6OxN9Z+GzBYi3Txjse2FDv2HMAimBoCXDRXlk+yVpwUiCn5LTOOrLgekPXApsjOz7wN1iAF\nuPCOno030qg47WpIfuuAkwTBNanyjM9t9kGvHBUbYvNGJkbeRm8WiEhVGVnfSDbFg1e8sBlL0Lu3\naMpK5PBpegs+vk8K2IkOGYvR5Aow1ZeA5q1rcMpEdIMR3mvYVfmtKdsviHZ0E9byAXZKlxdLV500\nemm5GQ0btI6qUDeat0/afCtAal+KQNfrpHPt/BKEshvW65onuKtkGdVhgINJh2YjRt6jDRwNZQy0\nt2/zk33lRdcQQQ8LBhOyDN4ulcQycDTY8OirqCVBDoNZ+9yHallJ2KKSJ36/U8NF0hahr7y5qtSM\nA/CkX1Sq/WW9AUQghL6/flbo6xyPz6Bk2CrrAkVR1m8WMsMYMTJzDzfobDkq/uOLuUcYSHS8GNM6\nIdJqSHQHu56KgPK0O/DnWxNXJkyeBTmFrEEAeToW3FoLlXfLwtvWmC06ciSqRnbm4gQimtKLA186\n3MaT356eSiGNv5qN+OQ8jv9hOKg17JmP9W2QWQxotOSiN3CpHK96mnBgBkpBqeksHSwkZ0Ym0Qlr\nWv4lGLAVFUI/rN/rGeRGjup/z4iwy542LcR9kEYZOCDY7F+46FcaQVcgrEM3BbZM1pZ7vMLZbBAB\nNIp2+fxvCHdPb2MYCkQJEi/lNoxzKSXQtUF/XliVdGDd/gJwms8Xkb0HYbyyJaWmfe/7DA0SWmmI\n5fHk2ePB/BvngIkwjKN6KMMHlozyCxLMBeUviR479mhHY3qV5gjKRE18cK3t6WtqD1l/r8fKmf2w\nmzxkLYc44rJqGUZqz2o47L0QXKUl4KpIGJ/PgoMPvA1kf0RdRqeBduHyjVFsKxHnVpN5TcWOPpEw\nsnzFSf8uh2B3xmR8tN3FtBy76kvQdN+6jOgMRDMtqYF7sGVg9vWPkeNNYzWk3rNC82l1Zzzx1ztQ\nJPblX9T7Eopb8dQclIpQtlVlyIvKm//abXhCgGVhBiQO4HX0Mien3FDZ990Z+ACbN0ccUL4Q1a8i\nxBtv+PWgZCeEA7utiTzOAPee3+34gAm6naicmXjXFCr2YvuZ5nD8J4hTINSaASRF8YaSrvYywwTy\n0iiBeMiahZnjX6Ra2SrDx7v34srF6/hoMCA8DyH1mFmdEUrCRgE4t6Hi1YVAINEphDeCGVVAVZ2N\nPykajTZihGf35IIRqjlR4U376Y0tBRNDAGp0Q6kPtvejvKlrZKN4G7r1lJAyP09bE7KDPRmbs/fs\nNyVC8RFydYUivRE6veitQTKDOMDm6JNj7qAaWp77cujnVGbn64Bd4xm7WZeKIKIm4aYSnUwJl5hL\nD+LcQnpAu6AAfc5YHgN5y5HYw1yEUhRnMl/L5Bjz/LberH5kV5CAMGc35Dn5CCsgW62MH0Klur3t\nqvDQ3OvhGmDL4Y2xOoW4kBC/Rjs4GjGtRYrXT4e2tlpknnpaKlAKV1YKawJ0W5ajt598+Y5C55Xi\nFrK/U1x+yGGVlKNimaW2agOl9VuEcCh6glCflnLynYngd4XXKA2JKIVNlRW01Xgdtfi10B5ipXZS\nZVEoJ/hncNBjVQcHqAeGhnptqMCqfg7CcyShKr61kfcsAc5VLbEphtId0rpP5V0qOrtNJAKxoEaN\n0ppVGEAI9TOF73jTYNy5e79+kav+WYHx6AgbaL192QJxAqG6252UlyKD+TN3wBZoObX12Adr3vX0\nj8zGgO0he4Dx9Cc1zYRKQf+J+yMSyWdmVEp+MKCbgyK6LEYoIp17fcKhZNmAg+ZS36UfkshviFTK\n+POKT3AT1fvcHL8OYw/QdRPMaLWPsOWPzcq4yVgeUMUgiaSnDUCDUB2yCO1vrkhPMwKhlhn0LwuZ\nwfM3h+czZAHuZRighzjAJUXwkEsN1Pgt9F4Ga9v4FpSBRve37ucHHuEn5jrX7b93oBywaPyG4za/\nsKerqFfobeFqou+l5uZHAWu9PB7G/36xCuN+gmjhdwI/5TjKnJGVa/Y4mrJHsK6xloq5ez4C0iUi\nDmzKDqJoGdws5uiPusdI5CZWqgii+tJ8UWOIJHe9wGCyFsM8DcbrnffJ/viThaJpSCiPR0zFv6En\nui3LW356UdHeYjk/6ZLmILb75WrZlIL0kBuk74qo9+iFxkDdId6A9FExjyh5C0dP0BDu7B53lknF\nihlFcZBGxzYFi0FbzdfCEM2K3tcVp8899GthOJgGu1N/qgTjg7ZC/hyW+NBVWOcsA/YI7H3p0zgC\nXErEvovgf4PesV8V5YrcnbNOLDkF2F+Hf+2W32/JFOuPVvcNZ0gw633lx0jeGk6zfpU4S+UqC6Z5\nlv2D7EYFebe8OBLKCmRA2kE6MXcrMBmFn7B6+0q/HxIcCLbSLBhEYooIbwK4lBvBHwt3ZNID9S46\nrlt9jHIYAJJLaDmqvniX1DClRh9zTvsHpSGG3mOKpwD1pbAsE/8AMN715F7VM9sLDloqgirm14c6\n6KaiDL34h1u3UPQcAYa/iUBBFD/omsncOZqodQoWJn1t78iJvCBlDiE/KRD+shi7MBiWR2qJzUV6\nvszTfqHmcpXqEKqJvAXBiNAYngR+GmMYIbTgB1YEwXQCZD0LToUOiwp5anTrAhDmS/ZUfyPA3O6e\nTeDJzu+g6CkNKGT6qnI9zSYRkn59rzdWimTbmd31+E9sE3oldZ7yukJKGm9HcrjmEn5iIHN2ksfy\n/bkuKAzgYebyoHDYTZZ4VZqRJkKaocRo0fbIi3zd65Gp3s5K7YmVN1cvTb30eNMvckNTr5tRJMXB\nQ1bruBwB0ntnrr5x/IGxj/XRZ7/oSwIkJdyNApk2te/birUbUR6UnGc4y4ttNTCDEuqggW3Cbfx9\n9tQdOjLwh43tPYA8H/M++ZwOf3HhfJjQQKysv0lOWY4S7ARJ3OrEoqKqyXAWdXniajcpDVbynsa8\nNsjwPf5WL5HPa+3iczXjARgydFiLFoxXOvEHjL7tJu91ngVLoHuKCc1sVCOdlfYThGi23uWH7vJ0\nYOLKmVWobVhcf5VpB8+yu1Am0dOHkBdHCr3rrgZdInlMue8oop0PLaPmJVMowyGjsverdCv6z6UE\nOqIUWtaPVpiBpHHD9Yw6XYxDCAiGibe+Gl6m/28e8Ym+QSzsogPaSQBf0SelV7KrqzHbId7aPJEq\ngRCDJzmPbD1Avv3QgG3iKsbrPI2KxWvxVP0dALSOEGlaW1luiCFhyVQZMjhvB2qkJbqeiTDhS7h7\n3EUa4i+fV/sjeR56deRJoqqk3M2q5B2q8M8jiW3dXI4Bxnmf1g7J8vrQ+iXPrLgC2JkSbeRZ/eFF\nCnM7HWHG7fLPw+dEcoxCvhyjiLG4nrEVGBWGXhUmx7lCGjGBUwRSXgUKYTNM+tVB/GGQSLqO1BXa\nqonr6lyJ9aQG7gc66GT96wZBQGclYbR4btuwY1dBNSMp+euELOd1xEiLYTm8oFfu+4GyZNtxGaNH\nQPGRCGjL34JDEnum18YLX1sqaLAaI4Vd3oohNrCZpQUGEPboSGGh1OhTL0TcjUaI1kzx5pnFFlQW\num+7966tMQzGB0widT/dnC203OehdRUxF3mVKO3vyZQS/QQL0LhvmTW6F2yZftZZwGor4BAllquC\n557VhXbkeLpl/vbtt0chG5IT/u9C7bdHihJPK9UT4R88nM21DYUK11SdT+pomG5JH2mJc3Io3YzG\nZcfbv8KIZsybNllnnP/EBy1sp1maLL9qN6kF8hDFHfB/Jr2elZJJ01JYHPOQCHNy+UA2Gl5QwPr8\nc9SHuUtr8rz+WAOCvege7emLx4Jt5ytymFbSfrvoRM+ZUxFmqe62SfHTEzg7ml6FYKGwZFzHxAVP\nqClbYQVma1hfPRcOQ2EPNB+IDQvSMtnMgfNCRvCXzR+Q+46QsNEdqQLttQrMkLWYUWQ/PxH/abKm\naMyBEKhbB0uA37pA7d7nNWme6VWCZ7Phlw4sTGZ9usfSAF2iks+dhfHFUczhnkRr5kLs2nN//1Hm\nujL9S2Xh+YR8mZbK/X/DNNxk5vMeM2BEVm1PZoxk2SRTp2R/vYNolwEbwelAj06fIHNm5MpYsL1E\n7ncTpnND/46Rp+9dC46VWjFitJhw6xYQBnAnAUgK5XKJoMd1ULWbXo9Obn6RduRPzN0a789FLdcx\n4OyYK3f61tQF3inIYC1r1HHOGDrI2xRZVZNZNDzADjAcygRu1Sw4WL8VBi/vYsKqVoNERt38KOEl\n9NyG3q3+6TPPg72wauvsj9vXnxr/ERZ9FdkR/nhOatd9PJBBtPaEAMYvPNJ01ByAr1H9v7EusrNo\ndtHZtpRoWhrKsTvw8ChWSzj4E7jptyFhnLEslaw4KGbKc0rKYK/kNZB6DrrEl2aCV7QHsdkX9Bj1\nPKcOWqa37YQlp97WsyhXrowmbd3CistDmVeRnzDx4swr7Q6boEig1BCH+1d5aIEO9ffvu2QbMvti\nAbcrVFpP6sBalPmiLjS15uhWV8KEGw781zQ4mqnoVw3oCKOuwjvvK/9OhNoout6ggrrMMfHFLop/\n7TagcwxVB59eehfgXDHC5RxEwiKlLkX4TdQk3bJgWiNKjaUI0iF5sXdRTcu76owM9bPDeFQ0zvcK\ndUkPtD7AXtk/vFhKjwLRLeB3UTz+YhoVaUH1daPHUMlMEH+eJQESKAxgCeuJAj8GZnyT7+cw0TT7\ncjpaqS0H1C0WUL6EFh9/Re8yGO0a8+1Wp5GoD3ceJ9EingExgibnx1rZ3dLJ8Hmf4F6c97FHtUGj\nWWra/KN5WoCJrdl6TSdm2vPt/3JFImXL3VxVhD1lHg5jk87q0UvPEFJbe56oPyUDYIHorFMXCtkB\nSp0+FG2szkowh6Po7B7p6lTueX4hCfE63q/RjQu0vNkacOGXYHvO/nT/7D6KtFG9OpRZwtuB5emu\nCGXEsehh9FDIFrOpVZN7q6ME4mkpcEBoVM5qdWoVt/3gUeGi7NoO+67+Xub8tmwmHzbP8nOXg3X9\nfNoTD1RXYZyvLZE4fAJJsmUmaxheX5QZ7wY+viDhcuVgAlnxxX0LLauJsgSdLdbbADd1bV5VS5Lr\n7B78FfM0LvFrQA5ay6ZN+k3078VR8KQ77wOOtuiXuls/asxNNLGEZe3j1Oqa8f4PJaCMlo6GC4Fw\nG3ADbVBwDp6yZwFL+jqVJcecF0yGso2WSscQ2vtmwXqV/rt1ntgPMcrqJSBUCsg3n8UAqSqyrJMP\nFl3aW/zxO8e34gRl8Gb+Av7qEDyqQnJbSeqv+bQRtgG85qT9oO8xyqlwpsHqHY98338C2Doe0qWE\nihq/+PAb/4nr9c5kJKMC6aqGRJYAD0fox21bybPmT4ZB2ZffeOrw36ME+hNkiBhNVDEW0j4LFPfC\nYTBRPHdDBONBGboUy+sX0hhLEFqDxD/pZ5nuulAJ1Gnpq5tYOdAVxsaLS4xVsiN6zvxKorSgpp8N\n6MetCHR0J1sVQSDbgLtEnrJ7/7F0wLUSS9jjxyJk3JHSRXyJQkLPrGjNvsgaaZ2+lUq84JavE4TW\n9WVMjvOBSoHbjCPnbFZC8a49DiHvK1W7MjjzSoFWxEqbJf55ZKbmbZgJvRBEMomcR2nX6WZLbKWd\noRt3xjhQXyyiLw7QmCKsylEF4+dhqgHIebhz0y70vdoOeqc0rMJsm2eLHLngRgytaRry7GtPEs5k\nEPzKLb4IzUud4aHQuqMS48KrQWjqCoEMqJC+/cyg0GMCPX8DoZ9NTjThi3KQ0Zm7ccl0zBlw3HJO\n4qeihfn5PUbsuXiimxdpDSOITExdNX2hgIYo6AHvcXqMa/5Srf1HuJLKLN77iqK19L2yGGkfG4cT\nPp+WIn1zd33WLqzGEEGFwucN4QrfZT0Mk0WseahDZbW80vLs1NuEfK2AfMYWc+gVKQjjNjUOEeA9\nEL0nVCajyreQL1X77MQ/Z3f7MKXlMZIKZ9st9Pqja1Wqt63i3HjrSEDh1cr7EQru3+zBo7gAIJNr\n9GzPVfhPzNmlRJyLd29w63i3/hPgjFiRB2yI01ijIow79xNLQev0WpGBJKnLZIkIGQdHfPjySCPp\nLNOOluCTX9RiV7C2yt65IAYwEE3Rmu0QeEMTSJr8M6cwP8mkQHG7TC26sVsjzhaVJ31m5gOTplWS\neyBIdXbYZgIWt1obgM5qbXkjN05FCv5jjW3R13d0x6cAu0lu1EIU8Otrn3d7K7abyyOqc6fFOCWC\nFarr8sTVDJSYHojX+adnx0hjaUrcMBbGBTKORHKWrTFaDAPouT+Wyu7oCi+Hh5VqU+mZe/qB7Kxj\nlgqWgjbbdcxQ8ViVvicBe5q/Ovu9OX/S/BryWWNVpNVVPrNNP7Ud6AruH/fVFpmbyTL55m/dllDf\nEsoSG4IV4Iq8y+AEYbXrUUN6PUiM0B/GGx4FWgf8LDcPntO8P7KQcTV6F6MLG/Me/gsMqJg9cTka\nGebbtdVE3YGk4XTN1vGthwkfPh1Bj6hbaXmcvd1KVqWndHf7ySukioyKHVdLKfaleKZQjgYrFC3+\nk9M5UF8iyFNdxOHcn2vCBKWVc1I2pd6ZMR0eYCpW3Bl+UUc551rT4YjvRrmtgQDJa6pyO3YU8u8d\n4WmETh5BlAaqkEDHrICLy8G5Yep8lSuyYflQRyJlV2xhgVqOUJTgtQij9t35ogixJNN+XdeAvnZN\nYp/xoGGboGv2dQbh1AB6/hISTyoeoxiUiY8Nc+wJ43jxi7Zof2SnRGiGZO+DEU5xvGRXl2Ws30bG\nF6+Am3Fvx6BC8+k+3uh9EM9dWQfSBMnHdb3idchTHaECxrWgQ6YbLbIwFuEO5ZH79Vq0tBc5et4I\nGX9TavQlby9lMDPpsiWQoFMzvCBc3iZ+lZJau9LWocl+f/9BM5rtOdI0HmACQiXtU54IhGtfHCn8\navgoEX6YeYOtrL13mkeqZNMTwp9lDG2/ChB8jfBoeD2759DTTH3o0cL9Sf5OTcuPA3V6/lQNTJTO\nF17UEFBwpnizy/n8XdzKpjU+gDcJsRcp/WGYombRXjSxfOEcYeRGaNBkgmqcV6xbHB9voCeSyNZQ\n3NYbjLsDuHnQ5i0saD+Yo1ryDiGFJoetyr6nXA1l8onA/40QGdAL14rfQV6HmaKHRVYCsF5tQoxH\nG29OdGuI0EVOUfIt+T29zFbaLde+rv8aqiogYctNjvILupJVMCrUy3eB1cYL1r4cE8vDpaIrVw3S\nlXsgoXh2LK7PC3REaCHJDLS9oq0Nxu43MiAuaSZ6DZp0U5rHH4DcUGKGK4LxiKC1fKZB2YXk8CXg\n4JmMulWsBZyVc1Hs2STEooc5NEZRynFPyNx6sPwUKpBlwvxgPIz8ashYeArr7pgtazIlQCV8RsbB\no3WNCfSTrHDscYbNhNGSN15ujTXyZIxf0xmw1NxhW4VE0LbVbU4Q9muynFksh/f+O3sz79eTs2Wk\ncj94qweFDzzDSKfo+fYFxr35zCg/FefHqD9FPNrkArUiafPmFRWLGkm6SWycHTHW2dmOUxqBLDnS\nKOU4i53LrnwJtNlnnNbR9vCnTV3HZkrvTaGD1GJiRzC/es+XDUFHEb7YDM8JUKlRbU33uV+CnXcq\nE5Afnqcfch6xTfp4W24eBeAxeKZEXYdjLxisOYvQ03BbLnt/ao+HyqjiaVos86B9Z8guiTv7Y7vm\nU0QBEPyFWR0ehm2yrjUy2ZOjpN+dN8ptlOpi+8jkgisg6gYT2U8e1S2pPCrAtZwj51rEayRg6gp+\nfZ1+HBHDLTW++YMQshPGSEXZMzn40VO97CNjgrh8ovSvROZzPoujNet0XF4Xl+0pRfUzN08GGTzc\nCDNZWKvs7QQNI0+Jzy3TOqD5OoFWQbRf3ETptGJEjsxTG4xPlNBT393qN4TMLuz9Lu1DCUKN/auR\nkZ2FO6X5bGfE7IJXmo05JK9M+NQ17wS6A/rJrHFTFQG3i3U1xyCqWFjTpJJamaXa8Ap24WYvz6dc\n098Zr90dPEFqCDwe6hxyVvY5RfffPzDqQb5DMiiFBA0+l1lXQ6msvQO0/PjN67FDr+p4RuZxhV6p\nTCZm4lrQ47Q5/Asnv2QX7XT23yACOPXvT5VII5iJx66cZDW8PqcokaLa+pAtVqbgZDPxZD1C4NXw\nAoObbkqulKoJobs7EjZSIpKQqr5GCZ3QjgDDwPruhevdnzONX5uBvI19+JYqusyuR333F376uyvK\nn6F+d/zNdvSAV3gIz9JaPPEhjbKgsUOFhdyDoaXdydwVHrAB1SkIhNzpfNl62QU0h9m1rX0tPNdt\nUnlnjJPMTjVt7hS8vJhfgtk+39dFB37FS3rVDWUD/97MlcR8z6MEGzbLsGSRtQgzQXSzXL4ruX2E\n7F8oaVsrywznJGiEc+2zzA1QekJQuy5dxS2hvHftZoajaCqWhhrACvQAE5HTIr8etonzlt70MhBX\nR4L2Kdszs+cuKe7YCn41vp6yn+jkXCpOzLOekgT30vVB2cScqwhXUnoA4eD5oeMK/VvSG8OomIto\nmaCJiv0wLgJ7kJsprJEeL16mqTkMwmvay2FtiWlIWbKIs9hgg5RqP5ftklAYWiA/4wg9CMMoH2hp\nuZ1nni2cWWGynf2ne0XC1qDqennT2JyNAQtk9Jw0eXHvjVLarN4YgyFvFTr0C5rV9472azo3UE8A\ndbhgNUf94/74joOWhz9K0BX6hu6u9am3nZfHjzT8iT3pq3MtSlLDx/+vqR09j1sBXhBoyiyASoio\nhAQyBIlf137OHYUONIvyzXe1M6PgVDfdvFr6g7VVEpVZDeSgkN1SXdnbZwYBVLOYe3JTzPfiCNmw\nPL+c0DJ8OwN91pieUcftyhX8/4nraUP0jfbmoqYneAn2aizdgj+uYZDayM1DDIqG7HkWgfoTyOux\nFto6L/LvFuzFDe+ipcLHg/txvv/oK16fIF31ETqIDIKRU1LBbQAbPUwEZxC+TEnpkcr6oVT0hwHN\nJuTLW8ZHgsVNC5YQaLbTIU0uVZ2AYfXpD5jXx2DHxpFmqpwAA10PEvjjBwEXurS92XYW6Vlh3vag\nh8071PI4Y8h0dlx5dPI/VyJA5MsaecCPh9Wc3Mu9ju7CmJzmdnouyGW49lVc7T+BFgn8vY84W4Jy\n0EOJqxtbldn/b0RL9qNfkmndlxOOYUGpkoTDXOeKNtd7HyleHoQUnqsrJltt7n1TUWyBkUSvmr2e\nhIco9V0pfGLnQmBrcS8ESf7JoDfid3dd9xhfTYd7x95o4BpLRW9VbAnUv/qzO2Ql4PsXD4elhlqQ\nIX/zvEAslyulqRlaIojF5lfyR5gs5T3XDgy9J3wvtzGMB2e/OdhArVKDlyiGKVBCwObJBltJLdrm\nqQtoqvfdCn+V9EPh8P1tILiKhp/pxpNcMLi4F54Ss1mMT6eOjdsUUk2NgxCMXJ9DCe3Vzm8uyZL7\ngcN4jfAg3E1rqk3m/i6KHng7yyFwHWIWhDG1pdVdgHnmaVWwnYivlzpB/S7eNw4unSB3dd2BlnzG\nRb5PE2fCqQmV6WZPnzyEbQbON8IXydg2GwqhVl7d+KhVvB9u2DtRSUwccaSTmzQitYkii0ktito/\nOZn5ZAWREOagH6xk2jSJtB+raBOlZD/StDmobLXWmpcaSlaEkDEyTAMr+crVbeg3vAGSoSOK9IbG\nhEMMVUnbYc1PtZV+vY21I6ppYt5T/zHwORuaK4UahSEs+tc11E84gYKfibx4zaxbrR6PIWoRhFpx\nfygJGI82fQqpK8rIAfb84Z6eXjnfx8vNe3ePHTI9pkZghZ1vx44M7VPJerWd7U5zd1C45avIo7bJ\n7u6tesU5+cplrvIG+231DuhICa8DH9UF72c/JWk3FiHDqhpde5ScS3IcWx1hhrKBvi5FXoH10veQ\nlHicTS5ZPF03XuljrC096UTByid0LNhm3MEYNMhJHDAg//PphATDzK9kPRVEqWJNnUXtQxCtfaGv\nDDm9ZwguZj9gqtu4FYLLYUIYBSERRP0P3uA20WOHJw+chMy+nL/5NJ5IbO3bDpRrULtw20tfYeXd\nMEZRrVydMWKNjYU3WDHTREgJjguTG/o0uckR8jUjDqND8/aBClo3a38CpFmPcWL6ws4xn7mPX0eQ\ndm04/XpCC8K8rCxBby0gOx53dNfuWePoTZANSnjGGiUI5BxmFdAWSo6va4tcRBNNZMPM97o0kVhv\nEPnfc3/sGE1x3k8/zSHbDc8HaQOXTo9W3rmPsM1cLrN9t27Iox3uo8H8MKqn1YcA0ilt5LAjrSV+\ntUKxL0hO5/r4sVSAigD8X48thLABHsoJPxsvEF8LqbeF6ar28+m3HKCwEkXmuDsb2D9EH9UPETzk\noU7Zlu+cBilAsNow3MhIVGRoQMJ90wjs5tMHHN0coijGoZTA0lcU/s6NGNC2TOBj1w5bSDX8FKiM\nS07TxyW3rw6YTaoFIbD66Rq/NSP/31Z3DELdKtPR9xDQKSDKf8jWDeUMJczhi6nWPBQbN7UQtmrO\nLkeWuAHdvStParHRMDHlyl76hJKPEZy48fg9N9UdnO+Pd1Ald+lem+PCsHHf+OqbXStJyJ7sNQPS\njKJNQgifRKxMJxi0ijJ0y77hsBxInqwKBywtcfVKlXs5gwB5+HzKqctr1bzPf+oUVROtD4s7C8n8\nPRAVBiiazwsrGoCKpXRTQdmcPIWk5o/ljibexkeIJdZGOflQLAG79TkQP4VR589A9TEHqrbDA8Ow\niEvue5OjEfXk8v35rM5k036b2nWDRQjwgH6Ww3B4Lm4ynLAYQGTB96U9XWkAnWLiLp5m8zvFZdDi\nE+meA0JkE6eMo9xpSCwtthR9qC/ZN+oxyhOIxOtsuOB79uBllrVRyxq5F8q9Jv+a7IKcvLMc3+Sk\nZmbgOAgVLYMQnsj7C+GgRoA181qNGBLLADnDESGgJ/3VlMRVMiOvVQ+AWmMuns4aRjO7TJj0T4gj\nOtQxN5mRSOWygf4wDNFbjjzdk9Wrb+YtBxxP67a1DBY73E4f8rq4GAGOc+uA+vYPxN2cpzQMxn67\ntST3yTFSN0HU+TLzADeDsR9fli+VCAO40pjEmfvnmz8uX4ieAh1/bmsrpCB4hddDi4K7Pm6hCPVZ\nlNMu2yUJ2Gv7pSfim/c6uDmTOvuyKRHsEtHBss9V0SHiF7zsCw9jC1Gw1Z3hAWIEE9MWxlQFYCc/\nOJl2e+2sT7p7D6B+NL5udUm7nX8gB74q1PUFWPsGYpD2pu3lCBVsQcSipoVTozPzXTMu9GhiBbtD\nKMVzVgZKLQb85zYLEfk9esGkaaAa/IMlXBYyZ3KgxHNEQVVYLd/28z6Bgq4z92uZ+nUjAQQNhNbd\nihUSeLisI8jS+p0o5SqzysX2BhJTA73Dl1qC80tYYxi+Dgt6Ix5T5JgkBeZt5XKSBj+tWhDWKCDx\n6uUFw/ci6OktwfqL5KZVOMkEwPLWW0W3S4EwFRv/nqulclXjxaiEmI1qy2g3i4xu4ozAzfvuY4PX\n4TNsbHRGXKHnbUq3OX7WWl0FoO0CnTw7uzXYj3goIj+2ppauZVSQt3oGFMco07p5c7AG791rM2wx\n+pZL5s5qBaL9pScdRgmtmuslKlqootc7gQJ5OxR6mvoMhOnphhgyojQnOr+SJEtDMMD5rHlXoSgW\nUJGwt8q/XT7s+tAVwEfFZwcio0IPbQNDOOsdHChnWoWh82tTu2wWSgR7Kg3fahsm6lpYDnkid7j5\nkTGihYKRKRkvpg2Ws63TmPYjpdul3WC+b4ZOhk6v3C1IdjpjOJ5UG4l9tMkYVfoW7y024BquSO5/\nMPPdTM2nWYdjbgO42K4Zxv4zLj2NSkWZm3pkgJP8LOnt+bV9C5AceuFe2YEcYfHP2NnzCbPkW3DX\n7OB2UfViC3Mm7S4KKuGfnRC4dEAlRwcrCwYneuiP6uS0A1MNUvCnPn8WEs3qpVOweX2aJkYS5ur/\nR1bloUhVQUshGkVfjwbVCpNKA1Z9uzEmBMAoQ7XvphL37Gw4A6IF6IP0hE2sLueqpM8yW6YP/n2m\nThOWH112SQ7B6Cl1xkrSYRy2fRhCPLiOb/AIOrOXBfO7Htq4hRh8mLjn9tsBdxQiCauhjPtftHqA\nbnkLa4np5WOkVect6L/DVTK0V5YtCK3SVmMRX5+n/iH5KjTBdbJDG5zE1+cZIZUf1jHOQT1zGeYb\nPcdKviHtuX/dxA/zR96YYgE+6kvpWexwOMkvDnMeZrFWV3YA2Q4yzl1IMz7mxXAYg+xr1XhyQAHh\nbvAoPX1ZX/f/hT0d5tm7H0+hzJGpOMNmOb9uWoxbURr1oTe7Aub9LGHM7MeHGjRy0eeNA4l9a3ZY\nWaNVI8NHq1/gTMRD2P454oSx+FPyBOny6Sx3+WAXKWV4raTpFUBs/OkARVapcvZtqOP0JQyWm7PT\nCLXQurpYYnK+M5sJwh9q8N5Ymi5B7RVWKXSw3bTt5UpCMFF8w3wqLBnB20ai9FBNCmCWLZmqK1BW\nOT5Z9SWGsFad4wD/ykn7EphW/XOoLWY4gWTRReb8kUiyK4uYq3GdyedGWQMQubbwsw4Yf9XLQOCA\nveyvPmR0nXWIDyie/P517DyAPPR3QSsQaXWL6OwedlZe9/pJZvpyVuCkMvohDO0OiZBnKhw8c6g7\nQDxVJpr+PzuscPWWNvWsRleF9CtP6o3lVCPYofb5eni3/gew6UuMOOPdq96vjfol+ipMOitig/EK\n5KSSJc4ignVV1rpPdS8jKt1uRzdiIG04lIgKV/iTrGxulwFTYWn0YXZ70j00M7akJBpgtHYtEwg7\ntuFwF87SDt98jOPD/WHKwoeleWTKwDzN8dUG6rIIjciM7ttKAupuKB8zcngy2+VEd8SJsoOuiVXv\nI1jEkJzWfyF9h+BgpXXoFGfSUjm4PqBwqBTsya3TbfnxMusFwVAmhcgkODyoaBE2aPevUBLTPEyg\noXiZdFn96TTFBTSKxfbvfoWmBfJLQG+IUMH6XUArLaDvPsOewnpCrh+xOPs2VUJvRJlbOoQA8hhc\nBYFw9C/vaE8JPImPCF8Mcml3atuzrH8J+M55leKZ+Ahyde17lDJYmLaTtLVQgqkyaZyHgYJabqrL\nfvxMvqW5F5ysEsk4uLDBFDd26mKkWfaYPU1SQDCVe5TX6ZCrMoOF7QT3xo/dGRKOrgxhF80rEBSA\npbHEX09kRVpK/s7dJePfIDBOH4wslJSyr+cpQWARs1LDsRdJqfBnbx5MEQ4E2qk0F1V6P0Uu3APK\nPs8KsBhcdUXgUqbGbsEQmLHNmMsW9PItMgYMqBKVjCWjmnu7XFM+2WPGuA22GFgbq/HHjTvb4+a/\nhNHFvP4EGDou4Pq063a7EtIFFh0VzxeE8It65f8GizD4Z/YaE5NBdVql7NOdDECr3l5vqCI3HnNC\nrd00HANISl5oyA2MuYTQR+GQaXrKUzZ0cDbvQZ7P2epot1a+MCmRzUKtgRQlP3GEAOvl/z6jyNGl\n0i9gClFCTubmketbUNA8oLzc5tOCpMdeyfZX7wq1Mj84m63g4WECc1S400lGBZhiUvaRIgsEnvQo\n0/oWeneHemIMitJgnp4Mf5PvMfKmyud8ED+o05VrGt2n1P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protect end_protected\n", "num_lines": 1219}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nReplC5Ahoe/ekHadJrZrmcxktMbPXmgewEOVkFltxDCtp7tjIROEjR2J0SX8SJSOj28503HOqCPD\n5HwauVkxEw==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\ndq0jjzDFNxyZLuCz/pQfvevO7zrYA9e/RXFtC0zs9vJkavN7vpFs4dWp1T45tmALQCanKasqmhhA\nbRrgjw4a32LZXERx90Sp9x8VBmLXOfw9Xg/LRBctRS+xLJvPuQPnD61fU2yD+DHHuAh4V7z97iBY\nW3qQSUzTTNMN1JprB7Q=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfslYTuc1ifY4iZRomp+98coaTdM+sERsLRzARKGgfhdyl4ejm0X1439hhlJZ7d7tGRtc9wOwzpsg\n/BjAHfhI0GN98FPbTMXmwIVZ4xb8F6OfUvJz71o+5oFDkZBQA5t9GaBxUno9++/GrhnRLkDhBhE6\nqqZtEGogfxjP7u3D1TCkD57v8OrsqHuuLKBzwJzuoxeo8w98GmBS0W1HbRoWI1ihFZb8bi6u07hw\n6G/59mB0i1MeTrA/nlfp4ZqwFcMwUkVv7BNdFPdniOghdGRFQwXzx6glpgnvSkzxIUcz9YddAzDR\nz9lTjMsWZaJg/1VTBaZLzzRjVS4NidlGCWcAtQ==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nNuhRHq63Nn7DJ7N9KmLTkmFO/pzyN322hkWuLK9DFqmNH1Sh/KUkgVIzA4YEJIlgTsfdGyxmXhIz\nye2BkQBEOyNZ9V8Yy0f0wvu/732rGkqabthdyRagbuLIY+po+fNOV3Mh+L2sobV0cCL9+FkFM9WG\nudMRIHdqJoU5F1Uyivp9XQ5p1DqVBUEeKGqb4oI5hyk7rgBR/wdsMmZaySBunPsOQOM+GCZmCwia\nOxj7Y7YMR/AuildHo/MG6rH7+TPk72luhTUoxeUU4RFZ+OBOXVV8A746tcjYIW954lHFuz1lOjyX\n6s/E2ZGSB1daVYsVGbXZCDGXztOubhxgABsydw==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nQ+3bSvkzpWqHz+Js8pO2JND+aLH8PVPx7Ga566/XW/zU52UJgqgvgfPO06Rxm0MrzgGVOeqcgfjk\nl8f8T74yQPJFxYE97dwn6Ek9c/4P015WcEt3HbSC2NgCSmyf6Fk4N4oPC6TDJ0KdzaunhIg/uT+M\nVNWRiEQq4BZ2NwoyIQg=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nKA+Enx0zxUaNQLmFOIuxV6NZpy5a6Hxgt6WW0NNg9/X6V6LK2SDqokbj3Y94Ev+d+qhLiOhG46Pt\nYdBx1YsEGgnXq9yoAf5eTiIZ0pbsxXvuh+v7YNLrVKsfNOTds0cDPcKfUIP8DTK2xNkgnlDRwXRZ\nbKquTuXNS5VL7rAeehT5VDDQmEkchpOsvfMZJh64nsWjV0Jw9Pd9l7GLuLK6FpAX8UFdoIV6Aq7J\nLzWlDwrKxbpeRz+KN3PyqsAAMIJ7xGaNHyPcGgYdeGqw6Y1OGYPhl+r0a7Rw5wZV+TAdgvDlqs0k\nHsWo+wgX0B9Jelrlwtkvf2GAQqWbLnOHJBSnag==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\naey/uF+AZUbOHsLVgq2yoW++LygRP1Vg+GXLrXqJeFzf1kNoqXKfMmZrr6DoVtdrKYjYJY/4phwJ\nx6NUIOO+ZQKagJunMRjq4qbAwGbdQw+1XgVGc39UoYm2j68ZVloHkU6g31JOErPBOLipxXru1NOM\nbYHk6hX3yCAMag8cPPtYksM2IgSUMKyF2BvLEcSY+j39CKMZ8W29pswu1O/IttaTmrZg0/AHW3SI\nz+L4nEJ/PL9raatcU1EfLGc099QF6JRJ3TqLL54a0dSJhhkRDSBS25Eht06P7uZJJSrrQ++fS9C9\nufKM73pD99Q5rIACsX+NQnZjsU83743A7FPGyg==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nXlLvtlTSSF8sH+XfrSClMgxkHY98hTFFc0DfYcUZStFT6OX+TcKGYnahL6GaeVbR6KRu1l3MH+Qf\nNDhEuzz5kIqW0tm1tK1YhKnOYisr/bS+V0CRsII4wrWg58kws17hF/r0yKdFf4bwt4c6y24h1mC8\nISdrxHZC5OqMjzEWUD8j7+Fvew5PPt6grZV7ZiuDXkDcPhtSCqsckTGVdIv33bQNrkaTbRVmkRX5\ni7RUiBWd7bTvtedYFq4fsKOvOs+58u3isvemYL+GdrsXg2rUc8W831Y6erY4tiGWaosrxd8JGkTY\n571QUO48QJbtifeSvfEFj/kAdp9w6JzGqAW81Q==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nGurT/+cXPnDploCER5sXenqGF2E/6XdlV1uohiMfTt+RD3ORIPtULbgYMgE0zAH0FZNWAeecY2mq\ni5jQhq64mRQZBmUrwq2MV3chNXYs5uWtowtSRLvTeU8bJFoUlBaLACw4A55OW9IC7dFhUwt5AkUj\nzOTNpUTxfbRdVlU+3UaIVos8qq5kOOrGSTcH1WsntkO07bNmD3j9jvKJIETKjO2tWEo6wLhFkmau\nv2zJMitY6QD++SRwNV6dDA/jI8EDOz+Jx+SfGauVRnRgBGznV80pjt/6MpYts6WVHTdvvsBhZFlx\nsAUEosByPj92SgAWwCJMqXWMLQb7Q+QArt1PNQ==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 12464)\n`pragma protect data_block\n/GT65feKxOxX3rp61AY7iVqPNpUvHZre1qx5IYW8XFNcDOv8hsfJTckNb/4sItSw80KlGJa6Dgt8\n585Ji46DGYiRsRRAaWAKQZ8+rXO9LwLWU6mWk412J4DXvTSc4w3I+29qXdx35aS5MdSxK6Lcp05M\nolbZ5c5tQSv8I/tkE3ioRxirAcEafjs3HHpgXPqKDbSzoM1S2m8KC1JZhVfzqU0HvmYHvOsB+q8H\nNYHoUokv/Fjz2d+4V5sAw8P/0NLVUdR+QRviin4OWuARNm25/5BzeVaHUi1EQxPqLRx4LNvmEo6Y\nlBEHQSkG0uqB/tps+73AG6zP+00EJlteJqHXkkwhaa7RWNIVOAl+GosWyZuG4pcnPYW9q/5ke2vz\njuaWPu2iKNuw5Fip5S1rhT0CTZDkCWO3hbkhSYPks7bA6dM16LAi6e5WdUee+gv2DCoxJP7wZBWl\n0s5iiVsPhm4+kS7Bf8VUsQU7o5BqZ9o+uYAzbvLnoQsReih/MpfnpMyV7DbDUK7kePTo1ml4BTIb\nJpyCjntk7e73f5XWABRYLUU619vxVKYmrycopAN1ar+nlRfPMIB7hukKv4d9leC1WZ5pYy/6PZif\nEYFpD6ZINE+vfwn0LY9erCBnSUFJYY4p6FQrytVOnbMW807bBcgsz/v01SKm39iED3NScBqTWG3D\nRo47Mh4BGsGuutZ0wans2YRDFdMxWsrg8Busy7JoaWBFT0duX8/kDUS927nlAbK4fFD+5xvXMlKb\nMc12cCao2Myqepc9gZbBGJzhYO0fcmqOLg9UOZ4OhPc7f1EPJqFJ6xeFjsi3J5uhJP7ku0GhgOBC\nC/TwWNxlyJXma4Rjc70Evs2PfjfwBAVnDEQXuohVqLkJIsU53wThiWD7x3D6sgxE+Z4d7QK6B5hS\nGm9a+QJvraJwcL6iD1NunChc6ccrEBTGglwrce0NM0zG0i/iBp4xA/x+QjBuM9CnKbsrNjvol7GI\nOnb/W6br0lavPRLeV/Oy7Gg9S99cCycR1p44O7rsG4WOCAqvKNEBSmJbk70mdVzQgSyJUTmYRlFl\nWGM9FVZR5UmV9g8UYT+FmI52RIS/uVF629XCFY5V2cQ1ZmitT1dJXw/gdBaHrDO4gtyPzA/glk37\nAA67Ic/z604a+l2YNgdug6LiL88fzhwc1420PRx7Da9jRvf3Esam39AWWAVcredW+N7kER4rBwT2\nh99rmMGW6VdnB9dVoIetp0AK0gahvvXWZQNuIiiIVtaiYWiXmqyM388XpkLbBc3sKLNweL3Om82R\n+dSJAWvEQsrD7neM8iiuBwh6cCNQvP/J8Aumdyp0hTRCti7iB98GYyqb50r0PX3mWEn6aIvBXe5k\nGhK9QRBngqu8lxIXVOLtWnEZX9k/TLd4blae94Az/sUUURXZXPbJZs7BOtOQ6+8hKPQsZ4exsgOi\nfGfVTfevmFLzPBx915ymMw8v64xjUd6dDhTfJnzBd6msCIEoTPSvQtOFbhR3sGlEq1/S3GPeRvDT\nO47S92WYSyrWEiRVBC5lJD7dWwEN2ywy2uoDhLO5ISJPKwkQMchKQ9MRGgxgoXNggEgDYnWmizoG\nmejkXPKg1y5zZXz46iIZ1xkvS9+emX7nNlwZriJwLPnawbXkHqauUTeOXglOyfSio8Wx59g2rUcn\ndsDNcrWEZK1TB1PG1XE/MVgqb9RjnNKrZf7Tn2H6R52dBI+XwQq75BbYwOuD7Q3SZhepCyrZYM2K\nAEITrl585Q4GiuX2xku1/viLeh4VNnL0QxBUiA1DMLxSqVX8FWj8ATIkhfIlwe0YiO33raMeHaHj\nvRdbUQk+QZFMm5g/lZGP73OFAABltFhrwPxG7mgw3ZvjHc8fFSJe5u/GWEZLM03grq7QKMlQQWl7\nB3AsfmNAUFcWgrCDtKRKOHhnYq64xkyGhm4bXgURw8iUQxnmc5EQGI9IS8M7OXPKJsVij4+CCMY5\nGNuLXR20Bz/N9mrD+LpkWQQGuvbYiym3wcfXGcbp3omy+KAfM3CoXbNE1RTJTrl1oCBDOmYJyxBw\ns1TaCVWJag1tas9KRsq3yzK1Mf+jqrhMgY8f+R/GLCVnFvyBXO3CFAT1lHf3JyQT4DJse3r7VL+g\nMp5pHFWqdZ8CQ3ck0wRo2OejKZ9hr8RlNwPDdI6ZVd2UoblCASViolT7lRE5M+S5RZ/fJcgw3mxO\nSfKDK/ncxAtsNdN/4WTYwb4IQItjSaV0dTSrP+63FU/bFUHo6fOhSb3Ji1XBC2KWQRshFpVmebML\ncx9eCP3is0rbFRo24rvJ6UbNdNDH1OKrT+gLFifHyt7C63jRV1jwxBvUiVvvkNL+qllYcG+9R59e\nByKsGZLh832ZON/7jwCsHfwH7PMPuu/w5MiO+pC9tiZWYXEZITwEf1S6TFGjP9GoWgZhZ4qYD/PR\nUcMYV7kSp43XZzvBFEETt6SIT8VV+bwKap2nc4CfEeM7AxcjuyedRI08U4KEQXZkPvn7ImNvs1Us\nao3cyB1aE+4RNDG7WbpdHq9KbDPEKWgft/CG8JL1Zoig2wHjkN7GHbGeWqsMuznn13FQbMTBy89v\n5giPHxQfIr7DsKJLsCE5qncP+u3Bpcm/bzh9NADdXOFva+YobZcHjp8klk3DxFS/ZVWHthppXOBP\nA6k4n9Heex0jjOBpNhrWYBYPsui19Sypw5KUryqiLwNeRaIxoMT3OgHR1/9sR+VwRVuepXekDwcV\n8KNYNJ+b6x5KLSyh0o3E2TiJmpQzdG4gRX+7LN/h/C84hGEa1jxaSp6yof73EqkWlRWkmeAX30KG\nyLKcOBZVphqCxkRuDmc8WgFFuZzPizcksOb0NUXZyWEGGmawCGdHF7R20wUCwMyzs8NjV+FmR0LO\nNNxfjFX+tKNrEd1ipD9xQcgYZJzA2a0HvUARS9sBPrJ+exAeiQqdSN9GYKy/HUIjEuBtvp+GavLf\nA61jEz2H6k3bL5naAdpq8rDWH6J+8ReUQWrvAW37yX6BHk+DciMVutTHFkv7+4bQrVlvCGJiCjkw\nHam1gycVcOOCrNJzBU/yczjXMr0JGw1uvX/aI8QmofpYEZiZ1OW5PjkWKQ0ENElhw/It5NAkGL5S\nBkADaru3F7m4i0j6RVv4QoAGhYVNdb7qO3mfwlZUs11sxLWfvWglkypoSeYnn65mo1m6bxBt4+d8\naUx6Q+CEulB9ugVXHTPlLfADAK5v8mudXYpIHlUbcfjhqs7FX8YhZ8pSwwSojzkp1I2+oo/R4UtO\n2OxkI/BNlbBlrk7PbuZr2yKjrgRS7+UciaHtyN3+7mTyTii5B88YDLwLrWQk2IuJ/t9pXIl81fm2\nmSfkPmEtyAbH8L5N9tzD6CAEzLIDWnayMmgie6SVKjukIZWa1+YiALr5tDlMRinmwgprfQqy0O08\n+3zGF9ufwPgPTqHMz0iXXsQk/kqYj22KkXG6wXob3G3Q282b0GFPxOMbyoB3VhCVIwYjyKfsrZXr\nsH7dAbAFwFJgfR9YGT07FF9ISnoE/fCHaSrwhusJ0tKUVOuCibFGR7vKfT51UAqKG5OLNz0o/xvU\nbuOz02Y5eIOrdWoyCfVWeAhU6zdOhzVveFDNprsmLKfgps/QR3wgYRPimUegT2MSfKhTCrYSda8W\n04WTeDxFNcFEV0Tr0Xwg9eRYasc8P8SgNrio3kmAY4W95sBZOJYhgfbpf8jkySvurRvFao43LcsW\nfmjP5iJWQElHpVYb79/amcQRpFVbCILepes6UzVezT/BKYsB6TzFWYb5SXBxla9SKLi4uAuGW8uW\nRbK2dTD+al+QA4jYSUoMXynitONOmBpWS3eEr3r2lMP/iyQzeU8K/HfqaGVvXtW4lQRhLX6dLdor\nLz8uvD1mANX60AZQzhbFAQ8pC4iOliAI2wSbNaZjtl3qyxZwCijZjjZrLgAukRSSyPRrxGiAXs8L\ncV/LEnNnpMP0kKWOf52Ht8BH17TKRV63nxKC0n3B3Lq0eeUDlM49B7KFd+wEebPs2ifchwfG9bKb\nGhI7QjFMzX/qkK9/oo4220VDC9YY6mz6Ezol+Oev4AGEZBvILY1UdkX1nbItevV06k78OanwOC84\nDICFWFV751b/roKKDtWej/Kvz6RiGj8o+TJH1qC24laAt0wFZTkW13VkIP+ngbnmGkoZx9BDxEOG\n/uSAGqXAgibeXGNnpvE2OF9b6Ryz4yAJuz0vE3eNNS1Kk0CO9Ia3p6Wmo/fDzrIpdUihB2GOWRIu\n66HU3LEAKzCvcLbd4FSiZIQZ2AIMRmwdJ0hnCs9RXmYHJ41un9Ui4lz7pPrhYTG+5tjGIA9JfwRm\nspOO2L36wQcUuZHdvo0rwoHgLqVUHO3h0FL/yNEwBgFbpCvrzd3Exdb6f6GEaIklZlebIjuF570g\niDmTBWWaG3/MHY1fAbjqfU0XLdZAH7tEl6kzfz4fO0is3Lkm5NooxRDBQiVlOcSVLy2SXRujkly8\n0RLn50A+XRiH9/9hvrMxT4HsLvCawIt/c6ymk17DfJrGNCz2WgF12RzWxR/T7M3R4j7bfkS5GQkG\nfuEVKPlWq79mc0FcltwwZ+XA0j6RrYW8SXa/hfJwrIDw1f23hUPpYEEgX7YK+tSFFFD6eA0wtbKH\nDS3TsoSGLbMAooSuHIQ58sr1rojxg+cJ+y+mu7mIjPoJSyHq07Kws1bdylX8jOGhz92ftuJc10ic\nSVtnCxag1wLoLoS03T+ibSZ6v5MtOIsb7jzLBWWMAN63tSOjbnpKffdOVO2qnTjxWvOkQRvMAh3f\nl78YBgyyzhEw2TBJJXsNDISbKqe3L2aL5q9q6Uop/5kG+coDxwoKEOni8bTWuHDEXCIBzs10V7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QQ5u8fdckcHh484JO+OD5JXAjeMAyWKvNWp+dOPDpt1TPPHl27k6FPdFVTZcst6i\nLDniiX4HJYXroT7D9vYWwArypAxRMCkob0PXd5kvtdY2VkcqwkZAwqwu+0U1ONBqxeLtvil0NXK4\n867XxQdLnVxC/ax+ENOLoIG0CRhP6CJS9E6Zcv3tiHQdrqDWdsNYDnuvEVs2Tglp4JbY7Or6quOe\nWgYABVTmwUOJkjCWjAKWf2T2+UMODkTHlGmT59nQIdIkU2B2PL3Op5IPDIQGVmayOmZod/ybIutQ\n8QvBPEWLidYmKIDRB9AcUTSd5/OSfPuzKaS4mRg/Sy/K7xx66JxNXau747+wwXlJj0Jj7ObPA+Ch\n2KidAx2oJQgMj7Kd1s/e+PdQ6ag/OgBtuV3CTOzTDOwcTIvf1VRUDGrTRVjPAVjm7RxsoXQHB8P+\nTyAcj7od26aaqIZROXMLKhyYCvu55ESx/974rFWjtOu2u6jeXeWR+6rmVIWNb7rv6kJLQM+7Fnax\nc2ZzqVjOAEjiMbkpWsP+KSQ1eBSqq6lrdM/ZAVu4pph7A7vmTRxEFvqy1Ue/JIFEFKN27FaqRkDr\nvP0uhcZeXP+erBdsQdo8eLPS243I3Ml8axS8zjpcS8xXqknascrws77dLtuU488T0TL+PGojWRgt\n7SnJoLEXwXZQM37TwDH70sUXoWh0NrcyoCLSveYkbvAGfBpe5lu4zSdV/fyuSiaHn59scICPACD/\n/343VXearCtLvU9+aZMEiwy/gBmoaL68/f8wpsW2Il3I4nq3BNddZZNzarPNffUjZbYPGdXHFekf\nIUyDysgvh6V9NYJfWkN+BhUubKI6cQWCRqxO2IzCLeLYeRj3OOqXf4Ixu1I3B6vxOmwSv6eDWyLF\nVyILPRqstDQFlZshH7yIrWvG4I1KHXYVe7novipDwfKpHRAvBnv8/OD2PHG+oXE1sSB6g7Zo8yE3\nCUUF6muW0EYjCnIvJsVkkbKkSx9awIG4kY/i3NZ/eMRCk1KPxji2iUNL5HRYjAFrmDyOV/AnxrMn\nqXEbVNxvhFt1giMHZ5Cg26/fwxgzhTuZGRYGjxT8ZwzRJk5V1sCHUaZmmOWiMjLDltXFWp8LoMRq\n9lryZlRrzfMO2kUf9Vrio9HUYlxjkWkcoJ49SmVVLI/++47ybENMAMGfsfYl5GfhCwF99bRMsVFs\nmhHu8YV8Q9yaKeiuibm0mIWTZ+bpHkUVoXIVieHRVqwlSKXfIfhn8B+ZnVIQXcWUOVW7YxsoSV6J\nn3nqMk0fVEgIx0LSefe0uHrIgiIEynz8icSApGGOp1pdUEp+u7lHMxRXlPm6iHRKroR7GBZMtN/m\ngOAxCcREEi/R879QAelCOEOiX9+3y6obtj849d2PCRLEJp3zh1PP/72aZysvm4lM3SveAVHJDdCx\nCg63p2kn/BwkuQPtWdzTAEWfoZs+X9oO5zYeSJB/8k2x/pmj7Gv4PlvE3IhwkJGkm6K/xHDbiBm0\n5VEpBKSFuZ6PTKciVXBNhUTCGBBG3Cm0eo0SbljExlfWiBzI7ZDMSJjbrsx5IbgvZZ80kmMF3Q0n\ndoLFEe9Tcey3Z19NBCU3UYIlg1Z6sKNBc30N4/qGxnM8/myRb3/I58ErBAju0ExIxF3S/3qxX1Se\nhl1hw7mYnhywHwFrSVJ+bpHSQrQrDjXx9RqbP3MJrlShC7H7SsM9A++FjRYOlUTdBhm/4t98uN0P\nLjHFJw6tjJlfOe9HMOKEIU2fdwp0uO1/EiioM3W0sgzHmUQx9ecq9UH4xVTO8f45THfA0GRBIUn9\nscuc4I+jtdX/LQ0tkX04ak/VsOXt03Q/JxwmXvtPyS3Rl6P1P3CqBwt6Oe/PI47jVQoMuxdlil0u\nR0uzuwyxtlAGSw5PgPw3bDa0Ff4La7N4uePsH2RKauR17XJFLraC+7pZzylY/QeU/uMKWf7PKn8g\naq7S1e4WHiY8/Sew+DTpTYCydkxWbn5nnYnuBwewiHUFztkJu3c=\n`pragma protect end_protected\n", "num_lines": 302}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nReplC5Ahoe/ekHadJrZrmcxktMbPXmgewEOVkFltxDCtp7tjIROEjR2J0SX8SJSOj28503HOqCPD\n5HwauVkxEw==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\ndq0jjzDFNxyZLuCz/pQfvevO7zrYA9e/RXFtC0zs9vJkavN7vpFs4dWp1T45tmALQCanKasqmhhA\nbRrgjw4a32LZXERx90Sp9x8VBmLXOfw9Xg/LRBctRS+xLJvPuQPnD61fU2yD+DHHuAh4V7z97iBY\nW3qQSUzTTNMN1JprB7Q=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfslYTuc1ifY4iZRomp+98coaTdM+sERsLRzARKGgfhdyl4ejm0X1439hhlJZ7d7tGRtc9wOwzpsg\n/BjAHfhI0GN98FPbTMXmwIVZ4xb8F6OfUvJz71o+5oFDkZBQA5t9GaBxUno9++/GrhnRLkDhBhE6\nqqZtEGogfxjP7u3D1TCkD57v8OrsqHuuLKBzwJzuoxeo8w98GmBS0W1HbRoWI1ihFZb8bi6u07hw\n6G/59mB0i1MeTrA/nlfp4ZqwFcMwUkVv7BNdFPdniOghdGRFQwXzx6glpgnvSkzxIUcz9YddAzDR\nz9lTjMsWZaJg/1VTBaZLzzRjVS4NidlGCWcAtQ==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nNuhRHq63Nn7DJ7N9KmLTkmFO/pzyN322hkWuLK9DFqmNH1Sh/KUkgVIzA4YEJIlgTsfdGyxmXhIz\nye2BkQBEOyNZ9V8Yy0f0wvu/732rGkqabthdyRagbuLIY+po+fNOV3Mh+L2sobV0cCL9+FkFM9WG\nudMRIHdqJoU5F1Uyivp9XQ5p1DqVBUEeKGqb4oI5hyk7rgBR/wdsMmZaySBunPsOQOM+GCZmCwia\nOxj7Y7YMR/AuildHo/MG6rH7+TPk72luhTUoxeUU4RFZ+OBOXVV8A746tcjYIW954lHFuz1lOjyX\n6s/E2ZGSB1daVYsVGbXZCDGXztOubhxgABsydw==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nQ+3bSvkzpWqHz+Js8pO2JND+aLH8PVPx7Ga566/XW/zU52UJgqgvgfPO06Rxm0MrzgGVOeqcgfjk\nl8f8T74yQPJFxYE97dwn6Ek9c/4P015WcEt3HbSC2NgCSmyf6Fk4N4oPC6TDJ0KdzaunhIg/uT+M\nVNWRiEQq4BZ2NwoyIQg=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nKA+Enx0zxUaNQLmFOIuxV6NZpy5a6Hxgt6WW0NNg9/X6V6LK2SDqokbj3Y94Ev+d+qhLiOhG46Pt\nYdBx1YsEGgnXq9yoAf5eTiIZ0pbsxXvuh+v7YNLrVKsfNOTds0cDPcKfUIP8DTK2xNkgnlDRwXRZ\nbKquTuXNS5VL7rAeehT5VDDQmEkchpOsvfMZJh64nsWjV0Jw9Pd9l7GLuLK6FpAX8UFdoIV6Aq7J\nLzWlDwrKxbpeRz+KN3PyqsAAMIJ7xGaNHyPcGgYdeGqw6Y1OGYPhl+r0a7Rw5wZV+TAdgvDlqs0k\nHsWo+wgX0B9Jelrlwtkvf2GAQqWbLnOHJBSnag==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\naey/uF+AZUbOHsLVgq2yoW++LygRP1Vg+GXLrXqJeFzf1kNoqXKfMmZrr6DoVtdrKYjYJY/4phwJ\nx6NUIOO+ZQKagJunMRjq4qbAwGbdQw+1XgVGc39UoYm2j68ZVloHkU6g31JOErPBOLipxXru1NOM\nbYHk6hX3yCAMag8cPPtYksM2IgSUMKyF2BvLEcSY+j39CKMZ8W29pswu1O/IttaTmrZg0/AHW3SI\nz+L4nEJ/PL9raatcU1EfLGc099QF6JRJ3TqLL54a0dSJhhkRDSBS25Eht06P7uZJJSrrQ++fS9C9\nufKM73pD99Q5rIACsX+NQnZjsU83743A7FPGyg==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nXlLvtlTSSF8sH+XfrSClMgxkHY98hTFFc0DfYcUZStFT6OX+TcKGYnahL6GaeVbR6KRu1l3MH+Qf\nNDhEuzz5kIqW0tm1tK1YhKnOYisr/bS+V0CRsII4wrWg58kws17hF/r0yKdFf4bwt4c6y24h1mC8\nISdrxHZC5OqMjzEWUD8j7+Fvew5PPt6grZV7ZiuDXkDcPhtSCqsckTGVdIv33bQNrkaTbRVmkRX5\ni7RUiBWd7bTvtedYFq4fsKOvOs+58u3isvemYL+GdrsXg2rUc8W831Y6erY4tiGWaosrxd8JGkTY\n571QUO48QJbtifeSvfEFj/kAdp9w6JzGqAW81Q==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nGurT/+cXPnDploCER5sXenqGF2E/6XdlV1uohiMfTt+RD3ORIPtULbgYMgE0zAH0FZNWAeecY2mq\ni5jQhq64mRQZBmUrwq2MV3chNXYs5uWtowtSRLvTeU8bJFoUlBaLACw4A55OW9IC7dFhUwt5AkUj\nzOTNpUTxfbRdVlU+3UaIVos8qq5kOOrGSTcH1WsntkO07bNmD3j9jvKJIETKjO2tWEo6wLhFkmau\nv2zJMitY6QD++SRwNV6dDA/jI8EDOz+Jx+SfGauVRnRgBGznV80pjt/6MpYts6WVHTdvvsBhZFlx\nsAUEosByPj92SgAWwCJMqXWMLQb7Q+QArt1PNQ==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 281264)\n`pragma protect data_block\n/GT65feKxOxX3rp61AY7iXHp/L5e58ZqLm/cTFXpb2NvXXVNxItFTykMUbkPkGUYoWm51UAlkE1E\nztNoFa3ObnjNvEq2qCOqN2eKDhMt29cy43NY3QwpKJF4tVFQ3QE354I22HWf9+Uro1icahnjDhhI\n8XnSv/QcqRPW3frCqbdomSgyLTQrFzDt1RJ7y77Bv3gNI45zUpMYFzgPW33wg+jQvO9vud9YkWEo\n5EEWbM2eKEMRexTosfEOkDNK0wzVbKyoQsJJ3+8ryXZ6+Nvyqhd0voC+ozAhRWa3DCKeMIvqWfK0\nESKtQAJ1yVPqZh6ca9byV2dAw3MmcnvjTQXanyTKOBGhvtpgCYebCFC64n+G0Jz5wCJVGJ3jAMY2\nmTyNdzgomt4DcvRvwsYXIox9NBkToHGRtcuOB1OhLbSGGAaC2NLXUpuOOVgr8kFRx5bG38eKZyxB\nfYMMOjzNGgooeGpJ7KAPGRsSU8M4zU5ZWvZX44kqkOpl+2F2oHsHjtKR3YRmtyiX1LbArT/L+5wv\nRtJ9eaKwDXqVrKUO/GIS3wPGwf8qYgtDK4nnFVw/8Vl4yW8QD7ySZxV01EFS4mrA7LmHIhHzy2i7\nO8au3Omp6URoWNM73VkKZb3jmw00b2E+32UVir64Dwx8blgfS7r4r9kzuD64EYfa0MPuX5cV3MhT\niYPhMN38LV56wA1ge6xbvWDrtDQ0KGF+Ou/TM/4FdK54ZgLQEfxNTY2pZ3DfaFD0s0N1/qQw5QD2\ntSc4QKIGT56IYiq49VUW1VxozXPw9vgN9hX8Z2ImYmnqs5nXfe/OBxz+2AGeLdi6GdTZr8tGBkN2\nFgXPRe0jlF7+CLFy7o77ZEz0yiraQRmt7JT0ldrlR9nygVCJeUn7v3sPuvvLaGdUU7nnCXY6KOQy\naW4ZUEPEdLTEFr1wq0R7F4RrEoFpeO4OMMBF93pLByQBo+ZkrK6KfhQavQNRgrvLWQJGzdHfZEJR\nqwqsj60DPem9ql+KfMHrx2q7ZtCqDOkROou9MNa8B3NqRoTOxO1QTnWO6zKht8TTU5lp0XNnCKGg\nplW5LtZIWmX707lerOpcVntZ3+nPQysZ1cA0WmiaRShJ+ev7bnZa4hEbsY+fV26P7uejbxBMbfIj\nQej0fbbKNcoAJXM/j7vXaJG7vZwjMF2qo4Cf1/rGItyAoWSIaOW7wG1HBdTnTb3Nafo62/PsBbcT\n5i8vu02ncrpBQNmo0C5rQwKhfbHJz15IZgEoRmPPtMgL9GbL+BfuI0LiFS6ALl8+B2/tXkccek6H\nlOA7TIqGDVo9voJQoyyVNjHFpbCM4naTa3LHNlb0hlV2EFsJ+VvvmbIHqPgW6YvE/i9v5vxyjon2\nMa8xloQ9B0mnKwdBZVJgtcmRRjKuSJQPV5nxxv8jcop7GeyEIwDZHTbpqdF6m9O03zzQ80PwYjvp\nQCeUkPBALgdfaNZLdIyFGR+4XQWFc5pxMzQRpNa5fscPBrtpoqB4EBQNoywtvx3lIbojhZYY36uY\ngJOhK+yMYIZng9tT9t0x5MkShaAutQ+biW28DuTV5xdHyHYlBzyxyAHMUgFhIgUZltyR5RSAB5Sy\nB/v70qImq11HfnIWWWu/VY3XMmrqicGqWPeE8KmbJ+vjb3XRV58KcrcuXwSeBuxBUhHNw1a0dsTg\nrao+VQWsii+rK1qxkPjHm+2yIIf7f7u1JN1d8jsrdTFmLNugQxicB9/tG1mUdhB3dSPYVJEffWMZ\nxFg5ZJaldi3GKyLdSqy+AZiv498C7hFbiVG30trGS/9gnquErKWZaXC7F/XecNRI1lpyyZBXhNKc\nbhCrOA0HCrFXBKfeSNf8d7/8WTsD8aGs+tLOGvJhxMgIjRNtOdVjQHQMeB8wN83b6RtUvuZ4GGNX\ns4NHPKmUwalCDUC+zsMOuvyX1cJ8sQPnARXaLpiwyZN9JCMStkbO7vHfv0SBaqBaCCYg1vj4B9PA\nsJebhBEGaweDrxPTfL408ppDdbt2qtNfJrcvuVPTZCLEyFQFyc9kml5KpOpmnjxHyNHVknHF8QvX\n6NS01vYaiwcb2VehoY4DsGw8FvXw4qzdiaKvL3kizDdaUlfoye0FvYLBGQycamkXxlDImGIuKc2F\no8WIu3Ke3QXEWieaArc48gC3aN5NjX0HkCWksgIs876qal5Wsd8an/4FIXnQLoiJhLcMMMmaq6Iv\nTh4EKFu/C3c6VHnKys17pN84kfnAWJaOLjrlQ05P3SCGbXvcKLiOqzfeTcjrxXkBZ5o7hYNIX7bg\n8d0VbD/cL3wnTkJM0Esu08folZa75Rx7/ThO5ah56TlM81l2PO9uxBhP79aTKbm6JWvijfuftro0\nvyugonR4SCzahRyPryk4CdUKGDjJRx+OU5D2+3OUXJcpMOZPds0PbCu++KEa9jU+bkVHz7nUqI8o\nHMOYDVehCRtcOXwCnPQv+tcf3wZq2XRmuGwoRAppQBS+zSonAZ3oWL4pRvbxSk4v7tgZ+QA9eGJP\nLKq+T3Dm9T4nmm/Vgc2MimrdrtILMHkFOJqIeLE0s5+eBqINHKqeXT7AfReRbjiPhzIlFkaQDH3A\nK98HUfoPAU2dhzQb9QazlNZq3vFm1JjTsEQrvTA/+z2NO+MSyqo3dwcs6eM6qDDC3FH3P6ieTkUS\nY4W3/78oRUM66VWTQnPXGTd/2rj6Bwwfoc6W29vXzum3RJNSCCzZu8OMSp3HN3Yi61xDOM4i9wYm\nvwDYszZz+KG4ajBFMb6ZI1mcw9+D0L9Sgd/3g8cu38GMDk90TwjNPbY94t60R1ye/oN01kG79O6H\n6fFarapEuwFDU+zU2xyohe4LbsJAUzWQbuf2Ak+vQ4iltv+CbT0Q/YJgqt/gtimQknDYJqlRwfbz\nuNtTJib5rGSsMGbjyNrLVpsKgUJVP8O0kPFGqJ2OOOSrYVC67Iyaoe0hcMKF7Yi33f3xn2UdOvCe\nBNlABzkyQm15OxaxlWLiLF/ccVp5LmZGNR1MfeiXO/iTEhsrRNDvb+J6Qq0+cR5KLIAr1de9FEBD\nWh1GWjm9hUFoJSUNUY4u9P4n2X6pt5lqCOqtYjdvEW/BOmR29Qus6ZOOrtjefYWBjKQ2ZjxMo5RQ\nLLb0K/vjbAiQlxg3c8Q4Axb2TZM7tZcjILwTP6t9CBvlDSpoTMDOJwYAaSRjetV/GTsuf8sccMKO\n7d2lbsx76F5N7+qi2UJMhEio5SFCIm0N4bDiz/D3sC8UcraAC2jKLdrJKowNkERNC3ndHSP7YnHP\n4QaHL8hJhyAOhpXkgD1jKpnN040bkBsFX9/hdkBGQbbMqhDHBCG7uENkn9RZTfLPv/qYGUnqlqco\nf5AA9FzjzmnJAnB37l0WlFkIbWhaOB5p6fPK5cBjo05tiCEBsKV2tosDGc9X78aJVb9CvKuKYdUf\nJPA5bdLrA6SVFwIe+8AH+GZTIQjgh+OnC5bo1cQ5XCvBkrMSVpL9HN+SxnanseFuE8fW4kYefquv\nZTAnE49TiCJPGZhEeB2NM8l6rVJjM/HGZT9FPavjf6cVAScbb0XfeSDX4TD9x0WQOOz89mUaXAb+\nSa5uJdIjJefwBk3pLjTQlsu/6h1hqxu6Od+Tmc8b4rQ7uW+yHwWVnt+jG+GQzqcV/rXK9II//zx4\nzzFR5JvYoZ1YK2VrN7xcI1tsbP8jlaPwHeH9GKfLCJkieZBrwUVx9qMAiepPHp1nZZeySc36m51D\n5IJJ20nC/bXGRsFwKSc1J5TdP9mqruxlS3ZSVKitje1wPhdFUE0mPFTXr+PvPPx9s9tusgTmmOjN\nRekzNzMDVHPxNGwVk2sHWDhNnmu8saetQgZFVF6WxJsvEDG9GNvRohRTurxc6wxbA5bZzk7dElyN\n0NmQCGORMGgk7toTCik8IZNkLpye4mdo1MDoQOpiCAYNUlPKv+ezXvHKphSkFS81ELrEqThrRaTn\nkCvgWCUUi1QQYqGZsKQJHqTs/Yn4Qb9W5SHb/fw8z1tqCMDt+GJiL8AUWi4xiGgovkpl/NWmUtyO\nfCUHDfcwNDOsE2i3NvuDQdIpS54zDqK+HHP2KhBf26jCqFMDUsLXlQLYUizeadZ8WWzbShRmZB9C\n8zDJha/GJjwdx8cVXCg6M3QTpOEOt30i0CpdWvecGPFy2rjhByMP7WD2zXtZkrptx6UstllQq5W5\nxlgu28JJXdC5nTCy6PPZNeXf8nNc9QvjHi/t2/u+7zGXKiwSfOYkDolMCnFqdpPwwfnVz3J4hqo6\nyCZDl7zPLIIknVS8qsfpKxe/jKtJZ0m4tHcaUhhL966KKpykL9Hn3oc4oIxuC8Ee6OISIdpMUOsv\nvYO0o/IyKBUO29KnX//HrcOqKtNtQABx5zOqMf+NEIu7A+McH4+jyU3S4PWv+SH/ZBfiGeF1777/\nCzC30665FhcsDMwmZhqFbFfx1RW1IuAk1u6kg8BOUfDZHJG5N0hPh31PgIInK1V1WEvvJfe93VMO\nqUkLtkvlLs6Lw52HfE8nbZmH6dJZkisuiNRDt1Ea4UGxOQipm/4nN3uIYl2ilIJDOL1RUIRtTgDg\nfKDHoBJMplV3idKB6gmCRGs7Jg2u4555F3t3al4+qb6I8CLp3zP7GoRqAWwlBrZ97UkpDucGl5gz\nGtd7sgaKrA1oA28lDu6PDuRpJyOttCntHnMBjEeBDYgzz8P0kJezEyw4NnZhoTRYWa2EbPodiEsC\ndGuu/j4Rhu1KDGu3uNz3X0GhCD6CCtt1Kj07+SzhdNIR8c+hfCij1zswF0gV1tuDfNKLH+aVWJxv\nCes4BSaOytIId2zG+n9s+Bu4Q5Zaew5FSAhf/boymI90MbcNjrsCJdgDRV7roaYAp3V4XKNKMi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luToDPakM+pkiAUpRTpw00ODwHN7VUgbqd2KS2PinJlzcVUEjdgRNUmE2N9R+6nUbPBDLOVq\nFBl+C4MwaeVLJetwhIYaBFv42X8LX1ZBfHzWRl5i8luN+GaBdp2j0WvFshIBwTVYMKuYx0cpM+Ui\ndFX+1u7Eky7eYn5QriE9kveZs3kD/p+4667p+AFrJOMgLECP1aYojCTu17POHPl4MgHPZGNbNKZ9\nORHVFza0jbPzSTLN34HUHOB1DUi/dt7xmyMnJ1X+H8wHTQg5zsFjI7sKAFaDS5b9wMZsGuab9LSA\nJraXEcoAV66/T8RCFZIYsFyTXFMahApL92O5zc9WhWzq8sUxXhaZSJWgvS2Em0wgCr2+f524E3Sl\ngBjuxc/5yHLmc0KVWRmWjupJSP8EXV7B5u5Aqgfqx/gmpHdwgfdGAuEvqsvpV7h67rRGmYpyKGqc\nGr0uZbKIfYT1uPXfZ+1sYY/h7HwrLx1Yjff4gPoWVQZFQx6856YAHwnz6Xx7yXCmdXFt7VWu6oNw\nIUtwu4Joepq4zpMQkuxdeakEXX4mQ2VE8OS84a7k7XY7MI3go/O8cxJJCWLOSzyqARQ3ArhXyq8O\naOL0BzFXr9ntoXls4mzT9wzhUIFIb8Jvxj1aL3ZhLFgI07VZK5kJpb1w0rABgxPBwaDIiGdYGPE1\nujAXIkSG6P41/HRUoc3rpTmx+tGolPCuiMzhW4VlBpUPNoh3UVYrjvP8NF1t6klzHrHmY1enkPj1\nV9KPeKSuEAnfPQdQsvUkeaq7+dnK2I45ow8H6N/U9mGeC3kU0BAfjTz7YV7qEVzCD97s8XuqFuRB\nH7b+A5ZlV3hyZke07QubGLTsus+RJ8INlZXhEYVfkstfuObflsYaxPIBJY5gej7voejrRIer620z\nshvAvTWl4oiPt/5X3cIPGK0lrcTr1CML+PUa2rQyTpIBbD6nTjVErPFDgxgt2zkwH5hNUPWyVIG6\nS/8CDDlDyaXQMNMHhTh99bQ0S4sU//5yfvZVCfm5h+v/pMi7jwjnAQ3tEE5UwDHLq4uYzD2yRdCO\nYhFEIqJO67JADW0Ta8wOivnvrIDvae5jdV9gvoYu5PSF52hghBTQlOxQH7j1IYKU+727aRPiieCj\nfr5VQcXlq9bmoTbjy794GlUh9d7pbpZCHi37lOOXD2PoW3QT202ftf2op/05dk9p0vKQID868FWM\nl7RNDsPjKwz0zzUdl/0t131M6Nv4wOeM0t32xMrG/n6DdhqlUCuPIElWoJtkeSUf/ibMNj+2KAKs\nURiPwcBehSC9eKdBwU6H9DEJ/pBYCRVM+ao0zs/g7LpDiBIRdjGZQbYM/izWr5L6651ruHxq8Am3\nEc3s139OXALgsi4Cy8+2itgjBKGmEXDDI8Dd0DRfikK7yPavpg/lefeWTZJFUP9hjkZbPMF0QgAv\nukU3MafILjGTeCXSEE2rbrejgktIWI4gQQWcqJYtF1hPenVsmMXzulVgKzpIqLD51JEyQxooRNxL\nOHGxyGvJGMt1eCSrnBPKXV0EkBHNOfCy0rjBq6MiUdAXt7jSZJkpLJuLMtpL51LtroHEQxh04I3d\nazDYNEBag5Kg11AvCs0BoqxTJ5RBEYkA4FOf6/9nJjlY5DaeG7ITrCZ22rzDDZ4Fa3l5bMRnuFWa\nBuG/ie57SrTSqcOyOGQl0/WWu7+fddpNgkH4ol96np/Oh4EwdCAzQYqO7mlqnoU/lH90mgaWTeQl\nBPINMJWz51l8Az1R3P4Ji6jwv5G+O2OkEEBqA9M1r3YFxqwLDzXVZgmfe+yTgmOPnMx1+MGD0yX/\n2evK3UlMtC9YWH1iOV5+kaxrWzHWlVcnA5HyCGkaU7HDBp8SQqmOEccpDNOnN7OVzjEjdjusJ4iy\nd1vrFj8L3qzkaefp7q2mK8thvbtVXj3nq2y6G/YkF+76LKknDRAm8LERfkGZgXTp/9mO10qmx0B8\nHdKbQMmrdDh4nyfkqdOpnzKxxw1xFDgYuaOTkA8S6aZFNfsqEyZXeWfAbNENZUkIUSeMpMD6RsFf\nKfxZNpiWNaK0WOaeAc1AyGRTXVh7WPEje4XFKOG9NuG3Tfp+tViDq2b0Ds3rnPiwfGV3PhBOR7WE\ndm+2waGFPd/GJzMUG9w3BWQc9DrCdb7Xp8hCZlBfXeCI5aJqDDBjeDp7+dlTUKXreFGcH0fXPL+N\n4/cDVZe3DTQJDQsropuwPjDkS5WMvJ1dfHjxS9Tgqto0mezS8dtcQd2vc9f3xHVB2XSKQKPJ2Obk\nZStJ4oEQQpoStW70MQtPD+06gCKNgFQyddB0ag0exLGLuct840duweSbxfJToNzFTWQf15uDT+k2\nvLNlspUivGYn/WrTqZuZEOAAkoU9GYulE9eAmJg59Nir/62WmMnEufjE5JleV2P/zOJrJTmSu3kF\nIlMN5YMgioGIYj46iQYX3FNg8sg4fQB9FuCmkTmHzHVgoppUi639LOHnGLhb0UW44Pgo8oGaHXes\n8LHfgf4vf0sC42rQ46PBJx7Y6JANv4ONmYoYDI2TGIBEmxXbUUlaCuQ/HpGQSPZUaShRauBf0KDg\nSjKPy3sa6LIcxfgficC7xKWLRI2M2VD0kHAhiMZqHE1KD/bohOt24wLmlm/bt0Ktfvz6OYQ7dC8O\ndELVZBBwXOXIHk5QLCiKS6AQEFVoGVLfGLKZPskMSQdpQpQeI82rqz8IR050b+imt3+87Jyc/2il\niYFroWctNAkC9GiBlyF6wVS0jtxe0P57uVrKgcTce+5aszlKT/yJ36NwLfQg6WrS064ZXRkJMfOe\nDSgdsCWJDBJqp/6KJhHRNePfB6d47AAqYx76z7db1+t3vZ0WjsRbWPcZ2I/fYv1yd1bmICVVE0KV\nY74bAY3llXsNBwra8TjTAU7pFIJD1xw5ApZkPLOjdtR7vgGvATjABslEkEh8kqky+V4KU2Cjkoih\nEcTFP/z+SwmZG91LLtY1G7kBcTe6SK2mGQrx5Cu2Onhe3WpGqJsMh8sI9GS7Qq12BliWwOF2iiUK\nMRAUIuOFL6qL843w9IcpJaVr1Q+RUrDa8Pr4nnalJmgzSbeqvj+MYRPEZNgvEgNvF3hCLbAzjN3U\n34r/Go1V7Dm/LhHtstfueNZPR8AaCklTBn/xLp6oKQdrbF2SgG03Qrb1y9lFxp2V/TghksDiMOhj\nIT1FPCBzjrIBMxUM3bcIV/m/WGpTZLTZBTihMTzwEHka/raeOx+k9tf1GTIhqmLsrGdE/Tw9+Tr0\nYunM9gzEk8az8gbY58Eym8SgBXvHY+JWrjYzvEpJH9NuXDI2vm3aSihiC/Cc6Eg0cNXBXPUq/Ffp\nW+gD8ywxf3huRG6CeFsjwwdPq65ms1VDIuly7b0zjbeMN8rbYxvyQGW3UfMrgijNLJK1Q9SM0LUv\n9X1gkqYBn5kdLC6glQOUuigHEpvmKvAOouSMH37PL9SHBirYMn2Cm4Ydh+pt4BphH/Nu6/tjIvCA\nrY7wvWp+m1R5Bm19rgjFxM6GbLtX8vXe4qPsZjiPreCwh7BnfLiZ0T0K7Ag+ktxIOVMaOh5AN8dF\nK3jPRHQg7YKVOZSW1UwGdLL9o04SjGeXwVYHsh+dImEaRTAm/oRseOKfJ7N/ypBhi386sTNrSwc9\nidtN8u9P1Uz53++UZHga66pko9u/P5BiJcrFQAKinRLrsYA4pUSSFq8EBJAn72SmpDofZj72ERbL\n462tlN4DDrZYAMmDZnxZ98G3ZpuEa3PS8hzLG52j9Bjuhgv4VENXRJTFjFwJiMr6JduyGJ8aUshj\n96wwoXK77A/YcCod5iEha9Gb8XfN2dfllJfKqQHrn+/reosNJs37KdWpFt11K0ua0hTC29Lj5dnI\nA+1cZ5jO2hbTFC7ovhZEA0XoviCBVb8erKSsEG/jo/afu2mj4n7hidqibyKK7CoigXVNK0TmDXmh\nV0f0DY/q+yMRVyFEYFQXsPwon7sTvJXb6hpQn9B/DL17IubPlkHf7bq7Dmj/D89sqww1/vsQoAh4\niDj22NsSJsAZwtcekyCYjJxMdrBjgyTFyo6Uzey5lZ8MRA6ZAulbAy6B6ajFm6P0rmQaJ0TbaBtl\nVEjajUqe/1saQl/YoQKlsuzY2h3pnrq2UiuArHfzkA1zymeLwP8inkSwwRqbcDUT42xudIhh8oZL\nqG7jokBMTX1ex5XOvAUgFMaQgtfLjc06LEvcVZ91eF3SgUvlLtDt0E4N/zhU+jKmDcAQMAEdED9a\n57ao5dP1JiVGH5hul7TnPkUNaTd0FS9BiXzF+YAKoUqVVqWZKJh702uyDeGur5Z3KV0Q5QPq0VcH\nGJE+MVS5OgOZyJ5K1AWwbRkjHgII3S8RiKlJftospoRJsBnN9GT1Wup98FS8CXW10xosmFcQnibM\nxxbcP2E0Bslq7E5orVV/bALqXqYbZZ0/q/cBIAiwfJBLNAWfrZ7IYvyaILzHNrzhaMdE9m0nWrng\nUNllwqtqqUiEvC1IKq+IejaDkiDxwBi8xchO2V4ipgj2A5gLBdGbcFxALZfTNQoECU5tDghIhiEq\nwQofCEn6oRPA6GfaaPRickkr2I4RaVWInx1oX8pbcZJsuXbYr16PeA+hgPWfv0tt9SHDTQ9M4DUN\nOxb5cBdClQCXba060B/zihIeOPAzGgfwnA1J5XE8fbOSVr70nXsO0xin0FjmRlCNh/aQ7rvzNxHr\nE/L1kfx1wr9S2nePmLDr/LB7So9TCCcDkMmKy6SW1gafdX2v186LaW7jyBOd3PfQQ+XY4P/p18OV\nsihVtafLv8AN4TvDYMZbRvk31AcytGwE71E1YnK95lGT6h/Ljh9RhVlkwrz5CTUhXG+iglvQOuDo\n6jfyE2QjUzs/mQIltMOsEw/79ZiwXdTdOGrpX4ntXE2sF7khyXX4r2sSs5Eqsb2UcesrmnrKEh1k\nsNeRDR2b5bLg4kr2vFTRr0XMwBKIrDEiVa6vsJb1wmNThi+WDRCupnkJS7jOBlrY5YnJDB2NLDOh\n/wTYlnDx/o/XaEddYHXc6fTZPoEkCdD05Uk2wmQ+IhsVkQWjfIC4FCt27NUvtJI2LOpOF0z20zDL\n8I3d/cTxAOjL6KPgkDadeP3376LfMqkIyXz4zD6g3PW+PYcDcKc+hr2OTTvPaUEtlmdqbYaeD6PD\nHr8BQekTfHGds0NVtX7bZKHU6udbHkbXBl/lqTxG0mKpjMXZELsRf+miJDKPmHsOe7hnvdz870mz\niGz1ZDhTLvGWLCua5oQeidSUtcLgPVCGbx2UzXYXXGkKnPLG3DmMY7g/UoRrUntBbNHagWZnuSKG\nlbqbmeGKslTRQYDj7onTArfOa029SjIsSP+TeIgKps50vST4iGwe1eUZqRXjvygPKAVIsuqFJmmy\nCu39AFY4jzvuiqVE4WDOaGA9OER3H4q621jI61qewU6q1SY3xCwHH2zvYpGVXU+hZKPNf3djQ1OC\nrwEzUOjJ94K+om6dvaom+qmm+TEQe43gstvgIuU6bOHhQxyfrIrJ5tra7FhRNjPLV6f+jXudIUJ+\nFQnSkFs+xHrDHE4v906/KAmKQRjOGbVRjkMt8g+d9CGUUU4/o34eg7CiTP/B7PUJEyunYUSQNTj5\nJMMgqXbhi02r07ThVaxb5rFjk4pA4MWp4PXKYc3t+t0b7+IH9Hohy6elRdBVQiDSZVoBi4qy9uvS\nl3wDr2KKxd92eI3KmPgIHBOoMyzYcV0sH/JoI+qnBVZDw+PeL105l83k/oDR8bRiOZnhMVHT+e2x\nuXQWSqxlVbvDy0vTHqXrgRIMgN4ihXbcF+i9hOTFOZlubGrYiNI9/c3jm6aLhYELxwEb698WTKC8\nXfHEAYyEDYmoL9OHj/4TkaaQYxcMiIMHf11ay9L2MKUBVkDfCnubRXIQCqdmNC6PS0EfJ+bZhpFO\nxm88fXiuk2CUr9Z53g4y3KIY9gT/GKZKkipE/ycmD1Cp1rPfPpRSs3snunDlnIalSnTDZntRRBlh\nngL3Qbm3c9VF1gAXBBUyY9gOTim7utEcGP2R9jXFKFCXMgcZ/Ew6em84whpy7bp00rjocQpDIQMs\nhCh1g4rDHSnbAyUJpd+2azfyWYaVc/e7mqFdfUNoatacYn19uS88HrqmykfBmZKvKatkhE1ldvyG\nlduFQpJRGtVTghc8+Eraa8Mhg/qpokIU1NiwmUBczXzw0/pRBQpupNY/z2Xp6j78ZnNZtJe4/PPY\nYwqhO3QsgeIK5HVBu7N9ij7fwlcofzFig0IMw4dC7WR8kC1sTDejRJJuxWb+ThgJyKcHr6p3gWkx\nzesZWOUPLn5ypKA1MK2+vN8+9Zh5AQnrm5CIcf0QCnYqUFU9oLm/RXc2bJO5ZvYhd3K6vkuoUJPw\naYxfqY852SGhGhDgPDDkUt/EqHadmQmF7pP25eMDZcyRj6CUBL692f9eknVfDqkssa2dYcAINjiu\nFNRj6NLN8dvT+gWacueQwpnb6woXmfwtIc+0spLLpTzU40xIZ4yJMX7+mQ4h5tcLTodnybP4Myh6\noYyKqID6dR8TswoVKtkLdHemPUSE1MmZ5xgLwB5LFuBLS6Y7oC4iyJ+kKuWrBkh1+YASOYnk+Ovo\nfnZGT75HI8kNGa6XjH3quYicueyzlCrYLHb9ju4cee3wvcDvaTCNGPxsrFL9a7kfBgXP1yxn1Nxv\nQBkuvDnFcXmi/Xf+k3/JL2lTIp+ONtbnnkteX5AXXQMtw2SjqOqe/tcJl6LmYuLzxiS9ItOJBu6y\nGBm6Yntwf5VzH0uurbXlMkq3b0vmn6Xw/40GocyP4KKjXforr0XdyEEjF8SxzPuFtUaIXunt+MsI\nSEuf3X4XiOfLIR/t2g6tSWIRKyzyu2GfQoI6dG4ZQPMWH6zeAqoqnWHxmRMuKGLzL97vanDju/Mh\nA3jLB+J5+civ+iqS5XmKLA3YiAwOhQzCEme8HWGIp3TS0IQea2zYmaZSraMitmP34wPnRA40c0tS\n1qe3J1AP0c/SCMfznTQaMSaScIi0F2KD+rMEbYIUg0dit6X11Cjm5Fsls4ZF+GLFKo9RXM5654Tl\nJO2A3lgderrEBqw4ETCglD2uMSCcQIWYB7LTcKWxTTsDFwKQg3yp5rT5bY02kZV++3b9BEZ/8/VW\n2qNV8bkplbDabP8OsBsIMQHKGwixQ/O9s16KFoRKcf/1yiqAoaZNkv+7wNsAqfOit8z4r1SYIjy1\n/eB2VQ418eyjX3e/wAmrSPr1KvLQjNaPMZlLEDWPGT3cyEP//eG1u2Et51c/b6SdBdKm/UhZ8CTT\nSoR1IZUqd0uWuRP0xtuRqogKnmLR0Jt2w7ArnlJsid3qU2GHXN8HSPWpHKBqRnO4LDo7y5LVA975\nWohCmQXKbRH01hc6/hTYjJIiJ59k3wefVSuqS4M1SPMsxVB071AzNOKClZVoVMzH3CN+DURzeuoV\nTsWHKhjCTeoSZeRQ2mSCuYqRjkPkh9DsFmavLVzHJVsYOBWI6SsX3CMbdBSgMcHUQso+cMunYdns\ndX6vcufgvaB3slVLoCi3d8oC/U+1TGmstyVdf9oqwXOwuqG10BO7KJl6FiwaV+CpnNwOE+oas2+Q\ntVdzb/ukJqkXmlJol4RpXArqPf282c0U1EHMk2jX+tufH14FgpMi6M3kD+vx13UggIpktFk7L/Cq\nVsDdtHIHLTugAzRiBIzmz2k5goROsAFGYbylHkEkST8NrMPQ8uIdEsFhCl8aNYQIST3caOmhFJ5M\noyQTamCgg/jg6UEZ1yvnwDJMViB3RwfKJkerJ2i2kr2HAXTzD7x6Le7T2AUSECTDju0jHenNoHpb\n8+qO0g5+m8hzh+bO7lol9ow/I7hN+TetulB1StL4/YhydKNHWl8VO/X64obYrTnarA8apRr+yEtz\n3FTHdZPphOJNm0f97LGhfj9OhbvHXTimP5IOVng6CaUQGWCpjZ0qmyeyG5FC1sBxQ8AEK3y3GzYh\nkoY8OxjRB3EyhszyvgdWINhLO7qDTU5lNA3qzxn6OlNIbL0B5OwFGGcSz9GxBGEk93s6iUlUh1fw\nixzz3N3DgyFGrTHwM9BzC7DN8qdcbZ/Cp6LNOSsLzi6W6iu8kbBHQThTa5bs3acey9GMzNYDYNgv\n6Gs2WySCGRjsQP599tiOgNN1s2KLm5BnujouUtGkOMmjLDXxuQ3dw8zopRppCi/9IEuMMFocyGmU\nL9P3cXVqL2gG+Lhmb3m+tjmx0lNsgSTxCsa9MorWdwJ29EOLM5D3yQApo3Et0ffWwAOkCt5wi+lI\nhDpy5PKaOg+tTYTV3d/wM419FWRyFnIOWFOY1oQ0Xnz/DFPN2xHgXWRTswJXD7Z7Rgyq5lcSGNCX\nrJa5OJC8nJh94cd6zAg87XSy3djFnxRSNElpClgouOSHpE4XYbzBrVlwHkkcl7mHkX1c6XtclucC\nOnmUVUET8+d2Yp4xbvhCjs3QHiHOak+Op9qUKr2y7ymdwIsmlCiCTAN6aKrfJLC4zARxfpO7vwUe\nE11bUlC/SNBjWDrO9yXHnoapo63RtS53a8gH8f5sxhDvXvVdwfHINirgPrj3t7ncvZjXAi+Lr3Gz\ngKuD28IkxrjJJvT8QBdD36Q4rz+zUg4X7L6mkfCCyFPf/0DOUemUUt5oDOqKFJ9Mo+1Y+Av7H0UU\nhHNILEx6rJwHzlr9TmSYKDmWPQ590nwOAL6RM1izasSthQDjQVst8yHQiGI+J/rIzWlUPz6NSRYL\nhGjc4v/vISjzXEGvn6FQj/gyKp/zykoNsepYKMDFohxARcJ879mHx8omgjtQw88KAvXGQ8qiYfH5\n4Z+flOAXTFIMna0pjtfMx2zoizZrwPVSaVdu04WW28J3jAK0Iq2jjGDU4FBVcFJ/5bZad2Lw0Zov\nUS2v2Ra2L8clyRFnV/VQ5Ii2EovZtY+nmXtcOulJ9iTC1rFDYzM0S/IqI0S6pkZeoBxDE4NT2mfX\nX0TwqggMcg9KRiV1gn9VNIrXK7G9BEmzZp/g9aMmfJOCKNzOk10NaMftV+Syqygf99hM19ca/w2/\nfnq22+06eOw/i1CdKe0QIYxO2VM/+OyD/kYdGdkpZuMFxuqM3aIOTgMWKj/44ge7g595DfkSOkw1\nwZK9QzmunfIHdxIrlOkgB4IVIsI8J5TQaFInFhDuQNl8zZ+YxpwUfwPY/Kd+JTkl1w+QPpskNcHD\ncgooKWba8jp9pNlZCqCe8mHLN5UWQRIBOqJ6uvqzCay/orFn2sXbLuBA7zruL1MqrbGAvNKl2xTG\nKkIemiXtev4GvaIbTrn3WD6tnaMZ71wFzFyzxOL+97g4tu6/UnOiT8L61PSH7Mgd0cx6GFX+yqZW\nYluzCeaKcgo5MtiHn1RmPBXKzvXu0/gXN2gg7Jscnh9Pkjkkc5oEPwcHFE3lyIElFEiKDbYuENUn\nfJq4h7Yw1pkYwBrM/iyeRuwgIhM7Wcg3UpF4Vqwv75l/0JWI8PKR2Wk8AWA9kzTEabR58OVNoISu\nqZTw3HIV7lNmlBc6F/tKOV2z5dyFmYIa/dY+20dU1jrbngx6zfxvjrIOh5AWHEbUav1bOS4MgvQ5\nKwawYR9n9TxKLctB5gSjjEDYsmbMSn+FPYcxbrAleYz3gKjLerVfdjH8eTac9OViSQCmKdAn90gp\nRBAv1ehFWAbZ8IJn2BPUjXQow82GGJFBEnztOZFu4kWTAP3UXOvy85KWCuSn7cfxcajenW4W6iQ3\nreM8NKafNfMJaSSmHZKeLgAuCMAjB81zzmJ3DhGf39fFMXpR6NIj5dYVOKkzdrymeHpza0yA9mkw\n/834RAQJY0Ymv1ji889lg6v9Oo4614MlajyZB209dbcyIWOVRvCG1XRsdi4UXftCncJQF4GMPR5j\nrWpeAuBEXTMLaGdPoRKT2pdhHfYffK2Asr45URRAjxLL+fFU6i9nT0piglb4A8387mDIMN1sQj6W\nq82xCnQqUaYB4YijpVppinUcrBYjSlYRGvFShhNrIX4VWaRnHh/Ii7SgLmyAHBmxkb4sn4dlDWOe\n/SqxhQCAJfGrh7C2lXFXPaU01jnsLr5j4O0hErOOZHQktZUtA25Cm3SbOO3bQpHsBlWjwjgupWVX\nsSdIjKWEljbsXyksW6C9P4Kh1o7BffVrmmLsuwB7ENYhXao+q6BQM5kJXjzMerrW6C7XFoQZTYPT\nldFz+XoJtUAeXqwXw90pPwplXf5i5EVkrRb5KRrS77l5zLnEAybKFlu4zUXWjprf2WfL1FexA1ux\nEdqepv8RaWgX8P7YRfM+qiAnK2M1qSPHZFkYEbW6Vcvu2TUHOeUxpKMQaGqjsV8/uRNGct2YdjLL\nWoPCTKQtVOI5AasWy1M2/PmAiE4Q7ZkDqjCgq9F9sL68wenD+FPftOMMlfOUsDDTD7VJF9cMSjeq\nIYE55H7foUwobK3CNddhfC1unWPxSNoThZ5evGMgRN/AxD8lbX7FNd/W9d4a5hImon7MZqqBSMF+\nKIs4HzoVPYXI2UxWRom8Y6WmMnvuJ0lmGbRepjFRGtrv+Lp/tRfPKspKCadUFZiwTEdGzmZovXpf\noI0k9FTjcMFJiyKdwazwG+SR9kVNYfZcvKbbBtYswdillC0AGF7rTEEJTIkdWGSU6OP/msUceEx3\nXQvK0uV/u9U4KkAXl2FYZQJnnVSV16N0u7zTupLI2IWE47EbJRVAJC2P6P9upcho9yBGJ2nuRThi\nNQ8V+n8GV2jtxaCV2ykSZWkfGBM4AvLm7hDewit90SgPKMmPh2p8JgbO4D+3mPMFzwN1UH8vZRTZ\nWeCOp4BC+F4c08pJwbtzttN4J2ptlO+nVx9DNK9ZKvFo2bznGXgfmCU+EOyJHwbaEaiNeuHYVq8U\nNia/Pr6yGrs82FtyGvLM0TuOrTIqzId5hBnkQeF0q1J+fT+eDlI7jvzHKzzr288qyprEt0VVnZLs\n88lbq+27kdAFA2FTULRyd+bNo8fMW8/XxDKMC6at47xXqtrYy72XgeR9AT1XERw6FXr79+YCaG4S\n+e9aaN7OiHs9sAfmvan+UapK3eC9gePljOoT4iKRL1p4pFLWGDb1PPdhJyk5dl1gkrIDAEVT/31d\nCnfWO7bES/FfOk33WBX3MZiSeto6D5E0XSEE7Kcgpr+s3Y2N8kV93iVhAMFkyCd2EzmeQrsijoxK\nHJH+u8cKwhhon6npb9KUHSU4YhW2gwAGlnlPoV/oDRf3HW0SqTmzey16K+7B5tE4PY5GjzVAMq6g\njWcnOxER3muT6Rg5mt+bvsB1NuF6/OkiyyZyQZRqbigXjEkyxqMLDLYhDjGP30sC2yZy6mgUHRDG\ngH2pvDQ2o2YclDsZnQ1W1Xye5DDNuOXYCCi8kNMQAboZTHsu0INjPb1vSudnpY/hHGbK0oUiRhsb\n13LIKrPHxYBIBpWxy8RETVVl/DyvW32UH1VQ8ALvkFo3YlkmaI9+OYkPOBqPNapiARh1w3yzPDDA\ni1UAkTq79G1B+tMIOQH51kB3z7YywJm0tTFAkUHe9p3OpV5sS9b3wpP+OMCfnKo18sY+fQvXiSuP\nABaF7Y8GDHwgetiN8Z3s2xdRi4eA8NowaYJT8tZz4Ao53x914WHEiHT64+j0Yhr+KZ1xzXk0UCbf\nPC4YmQ4UvRUMf4oet+C+wkjsIZDp5bnes3Em3+BN9XNcfwwrqCioXJju+fT1+D/E013vau05kaJg\n9Lvj4McIp0tIO9GjsuuGvLuvaMV4Iu1/uGxSCVGg+7VeWb8EJvqEjm7S5c34ehC9GacusQKUhkFm\nuCnFie3Ji/vNL9OXWioCkpKpYG79oX8yRt7b7G4yKwGT2U5AT3PdOg6FmXjPdHtMjFbqWXtS91C7\nV/crqNDp0TXUQBFpPZ3YI6dEKa3aAXnCZT/gjnB8+WWh6moPPWMlYeFqHvVjnD4/EAfMssQFPTnX\nPV2HZLdcCWbRbUmOyDngSayJO0ad184rXhHDEf+qFsMSrsHRLRN3LnowC57YgnytEavASo4nhrlB\nAYGARHijl2CHGGwhuyjf1rUVKd21YCDiG8Ywvm0iSv9TT1GF2Sd3OdaQnfMz83ctwvDJhp2zrSmB\nv2hJjJWnbKUxHn2BHLt3Uv6LiSQ2Cx8S+ivo4Ogr8gtB/aa0JmtCAIV0N+WHNGTasOtpFatOJk1j\noWPec9XCKgi5uUGtFXgvnly5tLjW9hmBS3T7ngSdYZNUdCcPEz/ebfU1D6gqb0NPXFlc75vL+POx\nQ7RXD8X+CBTJseXUkJISRuJw1QOGHcNMPCBRJJ6m6KYbOCgTAzPGSQ/uLoNzDGtmKFyc3SEMRTwy\nKgx7yjgjp/ZOUQ/oVJzlHoAxUsBY+0Kv1pLaeF+W7P6vY4pMfS2iZUWgQUOHFtrhOtHKaEBgi5al\n6ahRYfYT2lcmaS7syQBnS09xQeLnZcM93QJIpgFt3pTcxzZG5Gws3yYEPzWk+SFFGd+RT1dXgNfm\nc5n/TPiKpufcBA+gNVjIRgHW6S45vdRZ8OFmsJYSvwglgcI4MhqOsUCEcxxettPGY/oJqI/dAA8z\n+WhM6f2nx29yzVn76PDItfWl6/zQJLoRXMmLqjtyXY9WmzJFA8kPUU3DlaMSSOqrPABVMOynsjkk\nT+fbpfXp5yaGrPoyux0VoFvTyCpuI7rW+PbLaieJoYwr9SqvZVqNEjbRt1QdPBn/Whwvo+2EhkrG\nRi90xuexWIdkDMwkJZJOFjF+pblk4zK6dNiZowcC+NfjGsY4plsNQTMLXCO5eBqjXw1PE0r/9brO\naMjs54Awh4K7xSBxKIUmKgomi8H6b4FDpdxA2F7mhR1h0beHRBzyeSi42OZkT9+lkbWnR2Mr+pMk\nasTe4QN50QYP1qmh7z8PYo85EyOMqLvkIJOH7qAbDWIlFJdKDfCFev9u5Me7IISmRuLRA9iHOtGd\nockkcdJgNo+OMYwvj89HSoxsaC178xAmVKRHy+DvOSf6ejrWf0m0YVKB2FxlxraW15gd4B7umdBc\nSogdhl4dl0+jsUNtlDYSMG/s32ahSDn1JtM1314msciCebnmHK6a+BqJ7scYMp/MUM6gfkQsELMw\nkC5sQFwC699Kpbiyp0n7RkiIFgFcxou10D4tp5o8YG/DgrFokng31PnYqCEnsTYP+GDt8l7D2vXj\n9hSLM4UU7RD88pFnChJIjIJ0B7f6MdgHbJPPuqBkYfTc6MMkLMXdCuuf/RS9M3EIb6sZpH9vvbRo\nJ2FfClTWP21lajcZ/cyCo2LE2RWTH1t4UMfEkBN9dO5kUt2DJ/q0IHb7Mt4buuDOUyfFyS7aQ44s\ncJq+lM1l9pgFq35i9Gv+IQoh8PBoHW9rRpWwANZ5K2P0uvRDmRjhy0OY9Bo7kx4CKEXeO7c9uv0E\neql1JXRp0Dx4+YdVPGoAMbVyVXMzOlY9v+/5LSCQoRIckyCJQggczsCvXDWJMUjvUfDQ1TbgY4a4\n7y0MS3nnstpgBQw+hrJ6Y9B2Jmjz6SGw/dCXWIiJOUf9RhSE7TEsmsYd3/OfAQVqvgH7fOkj/xEE\nPKy+7Jyt36eRFB/I9qHWQtBBzKw8uGJ1eoxerH/WT4Muza6pM/9VEoh5/W4LvxvRce93bLP98cIP\nscJ5B3Yr5YbRYupC81qKfcUoS3pM6zEsjAeUKI40POD7luUmpbga6o7eIMmhmIJ/mUEJ30WmnE2B\n9P7SDY/0IbAw08pkhAT/J0EBkO5V982OHIyiuJHixWmqVA6t5hmwPGT1Cgz7L7Ga4x8UgKFo3+rR\nnD89cfbQ99yRw8pY68992AgmWZ8FptoO0hq3zncbNhvOJYik3yZHNqOfsKsbHbntCkluFkiszxHn\nNF3zujN1sQ+Smid9rwbx03V5S3kAL9XXoRE4WDz5fy7zw8lII2KpuEup/yWDylkuDnEr34PltJNZ\n2y3rH0XqEyeHBLLo3rxU4XOSrJCX5O5x9d9sfObtmYYPsUfbr3u12qLkdQ+qgqf81L8yrJMukVks\n0oBjHM01Rb2uFsAU6Lj6PUcvAraYfkmYIv8YlUWpBkEMHlXH/UKZosavQfFHr6Ej4dVvpz/dVebM\n2umN0zP0Q6Rn8Une7kHyqPrt4LoUuXljPF6beTKdyeWyZFQquEZNoGUve3mqmD3qatLVl/u4QTb3\n+KAwM7VH3TcRtcIhOzrN5yAi56nU4km82enCr0s201o/NcV5BbC1tMtvHFR7SiNyAWln3UEooHBD\npW+X8xD8NE/zNl+pZuNZfw+5zt1lWYY0xhN+Jo0GDR+nfie9uM7NsX2xnvqBDJoUmTtmYSzBMawI\nkQqpbfPI/g2Wtb2YAqqBu/hkKImJbqn5ugDuZJ+oHHJkGc+XXNPVqWGd32iiEMCK8laW5tCi0B4J\nCElSsWpg4RbB9coxx0RcDx2Sqn1QYd2odQI9gL4u78g8hvwvTo/MqL0+yhwilnt86P6sZe+CreU5\n45iTqsWIKV4HXAuumo+fFLjvZscLwgSL+6mwPFbmEPsQtFBt4ZsZ/vYzrw3KVjks5BmlHkLfTGoF\ntDy0YsMq5+ViB0tlagkRtTjuKH+P3lJNdruyqExJZFyF9VuNaRM1rY2ZuM+EZz0HkUZ+NnKymxwc\n17lAiTQz5KpY0o4PlB04NtiH5l2ylNPzRmoWMooKPpm8d1OUL2E/Li98cx+IEqNGdOxcbzMsxecM\nla+HvNr2LcGw/k8zyUZjpEe+9Rbk/xARf/n9VcFmB6vd05jM33voRFRmDux/FoT7r0YHQQffUY/X\nI+pYf/lDfEpefGDTGoLvga5wljeWkfFPEguFgXwpWcr/xN34i/zlAfu4rAnvAtVvdTlWqEBlofXH\nJH8rEuN3q3IXkPr+QlwUBo6+f85rrJXpijRB+NDBbeAJbuOaF6Tvr4BNurv1DEr0LEMakxdmVM6B\nRzwDoP+75QwfLDR10Ie9kmRYMzZbG82hXpZ0zTzK2VVC4+egDzl1v2ZcKeaA9WFEvhNiePhPRrUH\nlRwYAvluOib/gOnGfJBDeWdEQ27l9kIaHGndN1JNTmKqQNK6yRcdHc7n4Kp6a6Y+dCzALyc+7//E\nfxbGkMWf/u2e5vGgfrWk3dUj7jGkHVO2gq/XYvheJ1/zBF3Q05E+wYgE1RsVp5BUreQHk0OijZeS\nEttXXdWTgy8wkvXJBlGzmCN9vtdMFQQONANlMboMlQSQWHKtDPSKoHr5FBKkjSAxk2kFKX9YruRk\nOjDX7AsA15TjnIF3lmJKJeyD2FxjQIcQGTDMJHEpGW0+Uqy4akDPVHS12Ha6g3glG2rB6U801ixc\nw6wXw5zBaTCsEEwk4ktdUDRETsc1fCq5QohGSuiDGOAGV/hvxSCDlrTZlP443PTNbwsi/UT7WYgg\n562rsFefdoX5yr7NFBWXyj0ykYgwf7M4q8Hu9Na6jLGQTQ0Ld9gIyBzV7nIIXYihbCJQrpT8AT4t\nexwHu/Q1Np52iga0p3MLL7/GHSif/kKSgtZwJ2I63iw6aLwcoB2bg+bGeXJNFqVcAS3J4Q+dcVY+\n7BVVYeIahrxUbRckCsWh415G70YPrSNYDNGmAOeKCnHK+r3L9Dp9BHjeHwqw3QbTKvat1GQcpy1O\n8jj0IxjzBQoM+tiCz1ZCOiqSaVGyDUAVjwVo8rYHWw4ZQYF7H090UhrCYdJvDpJ+xmALYs6Zb5lp\n851y6BfQRxH7uIX9h7qa7znHIrw9+q10SR8ZgaYU6LFp0GnWrFnLtDQBPkNTsBrn/tuRwVB9hdG3\n0fxGbjJt3VHLGqUHFThY/fjrvnjfPQ6UpDhijWgMz7CLV8edmMAg4u5kCP+fXviZSmwWMdwgHapV\n5F0Llsl338BDFiZy9kphbUNP1Wzaml4rNKpaMEWLXVlZNGNz/bZOyPUxOYa64hR4H8nRMykv/dvv\nNbP3tjUatK6j3U385MUNPcihPMud41a+QvENE4EBKV1XupP4BIzzsfITI3uj0Ptr61CRaj2i2zAI\nvyre/uewvDCoAlRRS7neCwhVZRSm2kOooti2vviYRuNcq7XDwe2LVa63QDbuqOZRZuC+1KxMyRx7\nVNKxpYW5yDm2JI027wRpXpyvSCwc+7/M77myzTaqSyPmaiN6oqAFJY8e7Q6SyX99eKTq9d08RbS1\n2HIRLozLfaSQ4AYIwargWEY7I8r+6HwKNAVWSmTDFUiSsSmSSoaeHtYVjYqBdeOSGyoy2evR9CCa\nyyTINekDC60Lueoc+2mjzy1TGNF+ytZnH3NDZyVKkvRvxxwaaO3kDr2dKXePQrfDzKL5cIYHkiVZ\nroKnVc6tU1xfvALIXZouYFenq0MLWiL+Ouo3FPy+LvsgxX+lD/sZJbCHCbNQZqrtRDCClJ15ePn1\ngUtoU5rl+xXB4UhtffeGYHsrc1mggxVLIbxTXbTg6RL0fUo6QYnMBQMJdr8aNcKL31ymmO9zRZn4\n+vQpFBJyUA3q7IHPJhkV+gZkHLm/qIw56LOvNEqcTFL5Zff/MZxgzt05Bkuvir+MTB4LthqkBjDI\nIgu6wCv4qDJa97MgfKrs62wAlmMWwUzPBF8t5mWhVBRrRebdFVey+o0wWY9Jq4hU1rXPgIGcgpi2\n6JqTH3X7oFOLCygRIZ5UsLBxBSDurhf/0fDMSRiWfw7DAjelHjP1TX526N0u5voaXesWArqwBqM8\n9vAK0pzHYGUHYxezOmpGf8b8PCmtswBDVe7HrW1O+uw0xzbhRT0grsHkR7o9Z7RxDYavp3IjTFy/\nkGWWtcVjp8iLNMJSq8HdpCUQ+x3Cb3wn8BU4ai/dKAoTcypnYGZonWPv6iwvbu376d0l0HHU/eqz\nw6TeInWfCHQSnYxLam6+ytHP49WUL5jsAI5WZZXrRQ+hO1EGeekvohTlGadBXB4ujMo3u2tstoLN\ncihireH8zwJ/sbZi+b29AZ5tMlw9ZuCIzt2WepiW/vp01EuHXwrkR+0XAM1wW68sFHW6oQuKlxHz\n9uzdC4TJaKw8UelcVhxlqoCdlftgc5woarRSySEoQSa1yYP/jZJpUKEkFs4ll/DaaRyoBbrzKIW9\nCw71wKTAQtxIOMuy/L1XExDJd/EKXf8/Ls9pb2FSe7vOD5mE8fOF/zxjeynhDtNIWuBGWgr9Kc9X\nQuezurgfPwL4WlGdg6dNMIaMa2XUgFABZL2EHlPau1VJIoQ3T/nQc6SV3dYyzwTRNXClMUV69sT/\n1+6DRaVONQFmBeBbz1tYnliEV3XerXyI+6B74EZyUYQGLKFl4nbpG6JndFotAHqjxQ0EXIy2Zlb+\nmg1TZVwh5JmD6qyHfoBPs2CoRzlR96WfBmhLs7OLGFlJv+oTrhiCfdwpYM7/CKbxsKE/kdWZov9q\n2sjvqpyE5NQxY+UuMTiKxo72H5Dhl51IJ+89aLIedydykhiNJ1q+berBJQxDG1PBXbrJIvvZuzqU\nkMBFDrJz8AO48uPntmR3f55P+yjPHiBJa7QsAqPq3IK776d+wnKUAehjwNd/iX9GyHHzl1zq6TH8\n1D5wbK16xNm18klLOA8f0O3RVoLy6Q+tUBO3eebjNB1w9yz2oxwuq8wuwmNWayiCnYZ4GrN1RjwB\n4cYTDDq2GA6xU7IMPcmz10ve2iigiK3kZ94+DLXPsecpZqZkGLK1dGlAukkW+Dq7S5X0hr8mEB5L\nDN+13Rg4ZHY9Hdw9cYkZMPDkypo4hpixjoR3FWSK2l9N8Sjxfc6Q6jWQtV1c4IvEH2xWeFsDXE3k\n5nvMYIG8w49ENjSPywB8y7YKn0BeWRXVf2vorwk8cakQaBvlXWiynKUA6KfbA3gvGA5yJ1hewhFg\nqWODNi2UqMOWTC7B7JVyPYuPaATtHtzjNwyfPzM4QU8XxBeML9o6ZwNfs7MZt7bckKn28Ll5/ESd\nhNvEEIihhZyZVKue+Yn8xwO03kI2QgutoTTlEH4rLYeSAT2xD9XAZbnzsL6m5dI2oaVdb+Ny/LAS\nUAcbMExyaOcBnkI/PibZj9dChg/+/4id1V3kvo8Z7FmMbK+w8911aLCN8Ts7DpA3Mph98HzbP04p\nue4q/we6K+SkiwPrroMc8rM1IsNlwasTB1AthaHN5lP0KI5+lknPdy5H+wizPa/jNnKo4136yCHW\n7hIcNe6qAwwalsSrpUv3HpvmXJ8SqEXW3YwpPIiwxGt80XizRMFfF/fuI3g6fmeDOtKbYPsdpig0\niR+BlHlqtSm2iNuYpKDrZ4OZXWR/0mDMX1JW2lPwpHlD9ul0QuQ/8pVp75p8mDpEqyY6Z5MBYOfV\nkB+sxPQbG8E1bQwZQsQdJpgzBjtjowZj2vxIhfm5ncJOrNtjQjIEb3uztkiQ4K5YSCgEZ4xUmAVe\ni6Jgg8zGD+oBsUM8DLtuyZijjW3wIHhbQZowD/XDFuw9es0zU79sxY0Bvqi8fxxvmyl+BLiBcwkQ\nhAVYg/HPM+ryLjHTp0RPa5hXMnDjDjQkV76ht6kLR1qzH1780XzXcdhdIvq6f9K+gcw4S6n1ZVl2\nvQDiWuY56XV3a1nXdl8mjWxrgJax5pEW7BY6S6yJ1hBhtoEWucxPCipNqxK3qKDKDDn0QZ5EuRuL\n3rTW6Q5qiQZA36a6jyXmOyODaT8sMtd/Ra4QWurUGV6kEKRYFNLsDIJVx5fcnxz/btx0VKwPwUKG\nGVLFRgQFzJrABQ4/l+7+3kX57KATJMI+gm74cbz3LL3w10Ax7+t6rLnL4O3WBh8LtqO7A7zjNKPI\nnOJOwCNOqRiINgBrrgu3A5rxjDFf/sHHXCZPfiuvBXrZx9C5LoR/dF5vYv2bA7sA1Nv+snk2yxyz\nrkb1gLWc90SMo2397w8XmW8bX2YpfxkRyGYnbExU2dsiVUNilgaSDrJBKc+beG+gyac/SJpn0ZQ0\nkd0jM1PfGoMuFnUQ/tZo5MtSmFROoiy0fYda0ijnFasIjV+ZVi8YMI0V2Z/IWxUf5JSXUc+ebFP8\nwQlGiDPcl548o3nglD8PYyUkaaCVPIcGQXmnsdyAAU5n6ZNPECufyoM+4wVGZMAjox9lj/fOBGPS\neOV8QDpQjw1BKc7/oCHLwtcOgqe1NWwy32rn4nmCb3QJN55ryzgJoeMAN3aHuiKaMrgAzQlTw75k\n6StLMh6/Gv0SyytN1SgS8LrAPjA3lAoNJU8CXw0swZF9dxLP8EZN+9031ivvU75yaJ6rDwTIEtfP\nHnKMPMwb82pLOLp2mzNK6SeDqnW5eFmEi8A/HYYCuQmJCXYEmyM3HQfl/kYToPsU1wLPlY5iKymh\nEmPqorSgwZRNZMH7CPhKwIeISW73O8VCTeSM+6MDvGI3q+mtmGWXUs9U0WWfhcIbI4AlEmc5szL/\n1bSrNdZKj9G7sqEFedi9KuamTLBxsisCyQkpvpzINjcIoVs0dLFgzm2x9fvqJasR3eWA+R2rJ5vR\nK0bYxFnVsb4PfaEGOPSTeSNQWsx0ei9eFZaeJl5M38VCaRhUvbG/C+yFoTRRKKlHia22OcV8/beG\n7PGtGMlMk9BdLCt1fG+pbL/sN2ECGaD2X6OxFFhiaQCJPBEcaVE8srH5RTEtOJi92kM04GSo0mpE\n4ksJOG2oPvGHl+MHrrN6MTvKwVvdu6UzX75md7cRqJdkaz3fROAfovihvZBmApBfKJtsq8b6PFQ0\nD2o1wRaPd8om9OpF3Lj+2BjMMR3TjIL5IjEdB5WZ6/Qi6NYRjaXKzeq1IzwlcRF3PY7snFxcXhuP\n3WWUq0VQ8TI6OFe82EK+CAklLcHjtrXmTqfmMW8HxR1r3bqpue9/Sgn4VbqtOYaPbjWoR1PGI+ZU\nsrAb/MeLEECFcOsVxKDLptRd8gqGk0AeujCPU4YM2F9MI/2TUlnsIrYItd40EROp8aSMufBnfdDB\nhmjo2wq55HFb4zoYs5UAufJsp+7fwoIkA3S0NWQPT1jjGRfekMGk325rqEmr9/kR5Y3H5USBvTjl\n1iJH8LUp5x0eYUtNwQB2TGQrwIW52MK8pSx+2CKy4pYL0BFoJEubKp4tpsuguKFW+TDSxYpPPDcF\nbqQYYc0FaAXqERdQu/Ur8HAIH/2js1RRR5UjPtDXWLgUzI0XhcEErmHkdjQb6cx8JfnkXA5MRRec\n/kZE0IA6agR2G7UtFwXCWQ5ExHrCtXtZgWUvtH/2ZznhLUE5mxhJbTHdhYB3hXZDtWJ2L4wmxy6M\nPvCJ8fAkOxB2Jm0KVkGYqbb/qvMVZT/HmGrTETxVSguZoI4pRWwarntpywXv7hIWINbae6aoQL55\nVZQtSGzCeDx7KNcisGVQlaceCIvMkNDg1LqQgzUzjAmWaSlEAC9q4ajxPg5pr+o8wpZua14/184J\n/Rg5PCzCcCFnqbc20UwIvwkdBJTnwbTq3XUzV1oBUMfZEV+kLXFFQs46vbvonKfTYG2APiUizbDh\n5TYzTn2BAP0Ba6HVTfnnZGwoSCv7IKJfKRcEC2SlWbXogejxYr5LA2RJcvCcfeVKYhc4KzEHagTH\nGO/5EU81kUIW8P0Wr6nDOuG18cJlRxUp5Guv/xT3dwe2bVEwnknZ2/qXSR5Pqcnw273QWzfNiugt\n16JefeegriqerDXfMDrhu4rfEpwS/OljFToTPKt96GDN0frs92Vrx62DN7WtSswRdIa+tpjhXsTr\n1Cjnp5jQcDP3VhXbHYrlsu+x1gJhJkaeo6tySz0bdgemop287CXFelih1mVS0nBhns7bbNZoeBU2\nfqjD5OZPY0gigTXaEoReTZUBmBc0Vce/STFCZUHCSU/NVsOHHTQ/aFiAnHeNMUCT37MfFB67ZjvX\nhbtT7kfR1PKPveXm3Z8nFID1YOz4IyLYAn2O4086phOXzBVNEflhq4EuJ9IZwPLuzMaR903+ajx7\nTNC85mjC9iAoBxEcR9D4ZYXZ65wI3meADPofBRSwSsTIrAVC0ggShZlfbbLm3fDsngu6833htWfZ\nDqQoe1Yf3adGdsx1buOtlrIJd2A7ZlGYiheoB6LaOZ/HHaK9R5Hg7AZkJHY/Bxj721jAWvIuLXNe\nim9+N2pDMyfqLaTvrPKjXhXG+WqmHDH8L5xrPUYkZ5ztJtPy3fdfFHQUdCmKmp7/IzQi5dUx++Li\n8Gmbz7UZDRsznLKCjGrPplz+qpTFOZwGZSzjTxSlwx/R2OFKEguhTdZTXxiLovbdeAfnxeft5qRf\nxC3QyQ/ypM3JrlJ2xwBiFLi0UJrqCc+jEBRROuElt4v+shtJWkjfVEA47UR1NZwUDTl4YGRG97Jc\nBRNSJBDHEx3bMIGA+2PCdJWRGstB6W0EPDv0gwxvyNAz66i/dnXT5+DfNOlXFMfj3qaYJp5HM96l\nwNmOZwb+aGmp+4P9tKQ8ro0smm7FcpmvERHDRJ6LS65JBACr6ElA3Zl8xkooQhgqYH29542HJeZK\nLIuFcYbLf7nejT9vbGH2V1LBLT5dlL9Jud+ybVD4gW+0Winl9iXkgUOioJdpPBtuWws5B34E4hs5\nHnPKCtCU9nTMY799ePaNfo50ZR/yvnaJPisWwC5MzZEvcK6e5piNk8XbkWPlrb20xevz9pM/wZxc\nJnDc9rHWwekXIZ5xjaMIjqerl0TmYvGCPg6OBpiDd24jr85sl2dSMckaBDk32XUQrEXOP0Gr9QA2\n7ZgEeUQohFuINgDqqdY/rKrAM2Zam/eGxh2pL5YQuuv5LnKrzX+Ay22B0s5+xsYP7nRhmCKJ9DWc\nZZ2A6y5L6DaJHKlWDJ2hr0GY/ck2eiqUdHOWjamV6Vs/5RmvwUiuFsN7MrZJo3giqCx+kC/8DSh/\nliIu5m6wfE069dErZ28n1UdC1OEzRU23NpjyMQ4RjDVSRqkFulqyXRxDkt4QeAtlMjyQoZ2gZHvr\nz4MExwoBJ7N8fwcphDq382vHFapDLINCTJSvTOwdNFWLu3mc6iMlVFqk2vzlPySWNVVrgJjo9RIS\n5ELIhEliYxm5Z6H0PhYoz8WC0zrhxBE+5NCwy7r7sASXuWo+ZdnbD6DSdP6h/DmZEIfli4S2c7PH\nWkl/L/qPA8TG7Td8/5A9bJgWGn0fUjnZd7N5BEw+LQXnzlGMHiPY5FKWgEH2UbUS1OKBDmJSdxaH\nvAQa8vjipYmLqrrHvaT1pwIvIMC7DU3CtSKD2SQebaA2v2anzln2S0jOaKFG3+e0EUJi6Od923ao\nvxLT3pWhC2DigOQzYH9YH9/svAf+2GgJA4TXEG6RLvtGK4r341iJAJM8i5Cif1JlPr7NB43p2aHF\nJ1bySci5dC057N3SFqkjzAQqq7rUTtys1+I0TnHQcbpLDlGA+vOenH76Yvoza07pAwPqS66GfSov\nPe6M4/6Ny8srlCBPqFgy1HWpXj9oVm0ZaKzU/FqUfTpALCO9hFOFRSxqRV/4wWqsyTalmj0XrN6R\nT8Z+rRihD/lojLAHvJwOPvWCx1PM2otB6X/LqyupJDbBp+WGgMbbEbuzGvKgUef79rPzHTOfW7aT\nQLIE6YrVKY3axDvbCRhaWcV20d8/kp7HOf3S1teMM014SsePjqVt0/FOTGnv/D61VkxJWzIsJNJU\nxDEdHG96+cYsqkBG2aQl1bglEG6VHMyoXf5oENVoUE+tny4X5S3PiLWtd8nkjioIHtlo+Q2jtgnk\n9HierpCAwK3FEOFL0uPmmAYwrnUxEkyH2qb5IHNObeDQOY1d6Y+6RNHwDzT64G5vi/phBzqb4bLY\nFiW4VvurKqCxbk84Wf6ZS1zjXBjSKMEylMPIGDphDrLq8BCxqUAn/iaa8GOu51/A+NIZ/WhfkQY9\ngzgvID8PIMPPnMr3B+z2axk8b2jzVBpP+a/fyE5j8Me9d6bcQ6ROlsVsSB06vPq44n68oC4wdCNV\nPuODScq+3KLnPR/cjhfBTnwF8CMeI3Ubb/H7Mg620S2CClq+cbHc15GQiyucnH4Teh78Tm2n84/T\n3jyMOdKf+hcbj2fLO9WotCwk/GdvjC5kpMF+ZMHuayGPzvN+ABKbak3+5flMXlnWYMtyBy5EKQ63\nJBiphH0T/pa3NsnE/GhyfbXireqqucg+txJI489Ygfs3eKrIEgGy/H8n6qumVLPAnN/ytb4+1mdE\nZtlKCSyE+TnIRv4UWaxsJppOtgMAS36GvmZCJM3zuuDYcKIhz/CmMpzFVbV4SeXbd45RoCnb7PAK\nqPvBIdonyrwRWXT4NyjOCvF/KeH4JdB++B42GtXr75QpONkBJEvXv21zVZGYLhIneNVMZdE9/3wh\n4sTSThzX7zz/LR5rX8hN8c2AmAXb8huw9eZLTv1fGj3/6TDuWxn7k4u1AmbrCqLHWiGcgOdRlZ6u\nk3u5HqMpKYNjEjG+LtmHUsx/vaQNGkSPISP8Oem+DmHIgR0rL/YVcDqQ8ALhvOkQ35qgahc9P2Hq\nkiW6TxgAtUwwEed7rTUX5oIQAKb3e0R7Yikf0/Du5/9cx9gmAUSc4QoSGWlIbRK9dYeNcuxTnzJX\nbl83iaRF4sazGA3ietqBrLP6nMpwCSWBPUpLG1zLQCIVirBfQQauKtC9YZRQwdaiEdo7d3bWOfSv\npDqjq9OyDPy0HHBnQrs37MqUgTeu34s16YKv+LDLl0VYQhsNzNL2CLffkpCe9lWovqi6K9rTykjC\nkp8GvbF0HgCMm7HbwIo4RZlOXcI4SNjLaFc7iS5dw77Epml5e7UfzmRJ7WJt7v9XMKit8zfad2Fx\nd7IVqOr4Rr59itCUbBVRHjmS3nRXNIplhmWQ8y3543D2AUA7KMrp2VkMqzA1i0wRgLr4q3AVdyT4\nkouJ6EWzOZWWPdJ5DD1HiU6stLFPwIETpJMDy4Tw+qHQkyDOSpAc49W25FscA9xy1bVG3Ka/NtCO\nI++zckHfL2C0slR+eZ6Uxa6PmaxcVn6voDLq8UmpD/7AzwQvxeCIdg6lUQ9QgJ3KMz03a97IhGnF\nGYHFqKIN/UIKhNWPla2BW+sguvH6owIlOGA4KdKrWniE6qLuB8Tq3TKy15hyxeSUJUqrljEXQ5S2\nNo2Ns0oXpRVVrLsChdZhQ1lUTcI5fOvSVZNcyDTYeNfboyDzKLvJAS1q9TzDqE4Rfps/zRL/KkZn\noHSF/9lgZSDXQToxL3Pgs+9ehXWMwE+2EPUuFnC4PXd/eapgokBnpl2dPrmYXIGZIg730Ez2oCyW\nRQYSt1YNvmgyNwQ7ZDadn7QOlikamwlC0ri7bZ3ZPVYb4/0dPxEIXjI+NiaEmgBmDtUaeC6h8hD/\nefVBnDDMV7058+hOEaPDkEhOsS/ZvndMqqrqTBp0eAuIWQ8R6VJc0dTf1KdldWVrvxtW9ONsziTg\njlPAvXfhhzhMJi2irglrgoZcRwS5jv8jbwzUbJyD2cb1NydRVZYUlxvRh9bXgkaeDYOPuLDCgyPd\nrYSVAOvrabr5BIs06Qd+BCptS6yDyBb6Ox4gI5SILSia3eI7QDEKEbbqgM9IDGjJpCmD7A1xoYX5\nfQELRuYjmleJ5pMQtApjYgKPq+3Dhh17iVwVhPjVfG7bguVprtS69LXzEasfAeyWYoRfZAwZBHRA\ncuGcASni2JCPEkgu/qeM+qGBmwrTlSSOjS0PrBQjKNp8i9/3BVY+FdtFm1AGMVvkBQ35yuLTbK3i\na7YwCAKdn+yDaNTgEaSiLluaSAqInmODK1uNNzpPw6A6oEDLp0qxW+kp7qP8ZLivDeysQ+avD+Xx\nioiBc42nyBXc5VdQ1/xEbcL7a1vxACyzRSVT7TrKdH5OGXFiB6pkpoePUqhxK0pPo2qSRaRz/3kG\nx97AP1FCKffp5ZPaDR2FNFPBEQe17QAEn5LYqBYv7FY8UdNuRHkRKZQmJeFIwOYmZXGFlnFSVbtK\nxFoQboVwmfPiNGJBC0qUU29+Gn0VLLLn1CJtMM6dwyJx5dvxUIoMXZ2iNVYqxMjlWXPAZ76yDLKo\nO/npw/GNzI4P6oGjavGpL3vVI/WLZVb3HZr4Jj47zwvgOhF10D2p5e/20A9mWg1gD48N3gkP1VPS\nnkVj4rDLzyRYk/T36uhnTcud5ePFPmVRugM68nNN68kMhHc9RkKTZDTYcsmRskksvzqENbtvjop7\n2+iVbP9p6YCLuzL+FJJX84IsBELFwzD5FyktOg4djnkkbCnxcYRAuGPyyzuTpg3HFFel1a81kzJx\ngbLtR/FpCC3OxA83d0woxE36GxqlLrIdCQExiK6K4XggkIt8qyU0EycvOHBsahhwoybJpacsqasx\nh4riqqfQEmq72AsEX2xK7JRLI8CWAAm2DkEQCfS02Q7IO5SKpCMdk46XDJhDUb+ccTphqWZT3dwV\n5DH7gob86z8PP1xM0FSotPy2kUtbSbwhbAdTK0+owApkATMKnQ8MDUSFgmMBlhJq1I0Zo1zWz4IS\nG7M0chLpAWvxNO1Fw6y54OqKz4w/AIK4L6L5WPwjZJRGoAOGoSy/rqhbi2HlaVcioRdVmexaIhpX\nDPgum8ntbkjrs7IuPRaTAav/1Aqau7J34FkobGlaC7Vt/PoXCE+jhZozIQ22KCGnl2RJhS4vJh73\nOprZkjLoXDrrsMSbtyPUrV4896fxgQMYHeVpNomcEWHgj969wbJvRi9DI0Do96M194Cg52vDhVqZ\nWj+PqBq3GxjACebHkSd+XRbwPAvkoMs/bxQv0WomPNIl4/acJuPEuSqcmsxW0Z1wlywjOO5jXLGG\nDaZmCC/Tn7AgB/J6zM/4ex34Ybxgg2YXMIs5T9wtOjO1Yvu5FoRp1VOSiamgqz+jw9utR8GSw0U2\n5VLpyNwXhahZVu6Re7RDGsns1Tq53mCn92IGUIvWciea1bIBSeIPAg4VS05nVYPczjShRUGCssMb\nD69OIvDr0nQVG3QMLrRgeA+lKCtFkWR+VvVwOSReqFajSTFJ1zja5GzfpibZFsNPlWBdwFSmT+wR\nxtNw/99hkk6yvmlrdcjiSmJ5/nwgEferQdNZCR2GgT2/aACJhF4guCzHrrd+HHB8kPVRq+NO1xK8\n3AkERkQdOMv+BIZ7xI7JFPvAhkwPSq8/D1iB7XHLlKkEnJzmjQQrrlXmQySCJhj0x+QihPYQJWdB\nyrTighqrSJhWdiF+PCeB0i1nZdKDczja4N7YbX4qJj/wTZXx4SHNY5kgD5EM/HkNhzcgUhUO4ZB4\nKDP2SKECye4Ps/t+V+LxvO6uYI61gmVMRbZhMlTAKL45yHMY7DgRqi5W0m7HBfXq5L73nDQWg2xY\nAhIW224m8nGIcOWl5cbh2t0tQNVqt9ELlE84UlBUhL6rcJFsQ6NzJrGS9ZIW/vMBqo+zUJuPm1L3\nFX/PAFPec+GObU+maPSO1M+G9JTC1kfMQbYnwPeiI8U2b3eEVbQGuyBJoWrG0yrCEd/4MX7BBIur\nNRyI9JzoDkC4OtansDB8eqwNrLYPRRlfBuYJKhEOiDo0pJHtPYpdvMvvb0EEYNUDSH0/nUYEFLKz\nV9OE5p9bINeYgdhpya8p7wGcR+3FAvEnjFK/TFc2wuWPOBjbB1Xi31ADGbRW3ZcfnfbyRWpbf2Qv\n55FRIdcoBMVxVCCQVe1egVKy9KPnkvVvIXaBQDIqtjMBaUgS3vcSYqg1xpT8zn/gEW3iEdFQtJ+6\nh0bfP2ikFH98FgROlj1mHqhp9aWrF6ji6fAtsuCmHQHRjSqxP+JEVC+frdZuBXOI6DXIKQ0e5MqV\nTiMs3mtyGpd1EtDofzS6tYWVQArC3Y9JUyxuz23wPuXcrDxn2WfXJuWV5rAksUqgdyCFsXtXAVym\n2ySNy8jfKanYIPpVaf1mfITaw/Y6ixwBz5A1ibxMiAaUlPcfEto6rGYQhhokT1UguVdW9InEPR0P\n1Ts7IyskC0LbAnyx3Oa1PzvUeu9Q6f/J9p7FS/CQ20eG3u+P1dRY1dS7ynP5yL1v0pMNpQigfgjw\nnZQxpfdK3RTLfIYpGw6YCDi9Hz7FPH/RFW0Bl2KM3dyT0G4GgekgqxIgmMqC1RLxomwLBi47QcFg\nfAYvxwo58K559ZJcTKirgwze2xa5S8WnJVSslX21KK6GaALreUaaou8cBbDzrY13vH36HEP5neeI\nUIZbmBhdygrigYPn9ExrpRkBKRmqPFpgRPIruQm5ZmP2IjYTZ+bYTp9jRVIHU9OVOssXIb+1chi+\nBSN4F9nsielDghwQwDD9aMWKImwU5TpZ76w+UttLwsOJkuruQYInGbd6erxSNzHoRh7Sm0DNUtWV\nBcQIuC5Z1yn1Px6i3vh7VkFoZbFCFWdUsiJSL4P1zFbFLXWqKm76hLSo3/3jMa73eJGzqpZUYeJS\niMb2oyI/jU+9KdbsbVdhHlmfBI4dRYCdzoMNZI6kR3kGkHUB/zTM0m/0ALsSziTG+4YslgSac8tT\nc3e37552KnECWqK31Hwkly6qWQAGEG6SoeKTGcVlP6Gf2UrBilexqgF8RoQXyk+yXJhGt0zQiChS\nUOZvOJVDJcsTqxKz/mHm5I5RUN9+ej8TFRq3Q0UWtHdUvmEpSIroaLAWjkm8MQr+uXOMBqQ6rWN0\novUT93IGkeAH+37Cdyib/vfY+KKTkImvSckH73ny+SZXJmrRiehIzywYSOHOuUFX4ktmqi+Fj7QI\nm9sWSdhrx0S32rvh+BCZWStZMSrW5ZRqqXCsabNuq+Fp3DolcwF9fSnGx/1PeRF31sFf3tSvHg5P\nnc02QXAHXCi+x9Gijfa6vQSHWb5VjA9viW2b43QGL/JWKTzRYbJKz9hnjs/kiwdxjMlFuGLaQeqW\nMuy3utHzXm4Qwo+HcEj+7t2BFriNm/hkB3GmH3mpexZWI0RRWK88kCBQgDRDg+NyjL8AEI4/I4Yo\n7UN39IOtO/O4A0nuJZ1NOMPJjL24aUikjIpecrLSe3/gQCj1aEyhYEhn++CinWT1EAj6FhlFmYCy\ntJ80i/ezJxTpIVlaLV+OEhfMGM472tn/DpE+pdDv8eGWJ3logJXibB2kVu+6h117XqiNuSztPKY8\nWG/lvAlbu4gojoYlgK7gdzpB5Aw1Z3XlBgD3hO6NScc7c8gfGRiUlqwC0uTGbJeAzYbQ+gvbUh11\nA8mFay5MVgn0RLVb2MaDCfJ0g3lNhaa3OczGODoE7DA6MFxM5wBGqQIxn4aEKl0+LZEqA1qGfeut\nojsyPrMcjfzHhhRTNu0ARU6du0VgugX2CM6EiVhMPN3oUoWHmbMgg3r3iV1kZwaVLSKP0+O+UUME\nDuc0QS5VnIL0NuHYYlZkV8hPpq+XNRp3yd1xlDRbl21nyMwOrKVsKi+L9SI0S9Sybio0hgSy4o6F\nTGPP17P3w5wamgTp0b4VUipN0SAxt2MVYUHIx7L67daEtRMjv27Bo99vyNsELKyA2bMtSAx0fRY3\nAdKURPCupTZh3DkB+HuD0as3LyA3UHdo9/OyvLbhadT64y8QdxI69gjXvkNnBzl+LgDuTBXNyhQX\nUl4PxbufK6pvTxc+/KdZNZruKnbyruJwzqSQwxfzHrgnjhKN5RCUcWw8Edn6KOFI3AokFWDCim3v\nfdFlhP60PEH8XnWiFz6GFUOIwGy+HQdy9i1Z1oxIoZyffNaqm29dDkjvtDAJu8yS+eVyhfRyJ9sZ\nau8PzaIjZE7Ntb7IyDQChJDBPOET4aP39ntDO9kEGQKX2VSdlrjm8Inuzn+TqJtJUPEw5deEVEXt\nlIiKtde6Teg/+SPeP2MUctVoc5Ds/LmWAzBD9YSIA0uCwJg5LpXNGmhix+j0CoNlPDvyASVCPkRc\nJhuqz7GgJM1b0/n1zQUEJ0+LhcZRqVvqqpHCx9bZicZwNRGKg9024Uf6DF2vJ4Umi9/7bCTxp+mG\naGawHEJ0sXJ8mZVH2Pzea5Pk60jz8m0p9T3hAYhOhKGGQOPxzNPD9rsmIq26eUo5LaOCIYnFGTzY\n9HNgcBELHTl0epNrmuqsIDleZHW21AOWGQZI6SuuioU2NZXxCAF1BvNUdqn3DLtFcw6tlC0ArOSP\nLQx0/MCBHxh/3J9mI7isY+a6buAmteuxwb2qK//J1sa3mcc/8D0FmYOfdI7gNgrzU3kXE+d7Gx7b\nUGk+ztw8WujFWi0JG6gUeC2I1VrcfP72XkfrzjirMCq0Q4IOXDIjHUJSQnXCw4Hn1cDXj5P+XOSr\ny07HNj+owOc/HUOmQDjWa9auDqdZI5mRur0KjEFtoIeY95cJgOqWQK9xxqdvk/vJwDyjBFkVqHUW\n/cG/A3TjWaHxMzpNR8RlJK+F0CZ+ujpBsX4EI91a7eqF9gtCJFD7heFiX0TcZ6lu0ug9pj2aniIy\neDfwVZOirpZITk6jWOoAxZO+bPzovKlpUkPjox/4GF3DcNgqFpT5YSdT+EgRgdIv1yMvVsWp8M7A\nRR0DB9vEH46wN+zWU7K21L98nD9X+if+zCjhekvmiuwNg3cPJ8+NzMfOQIDDfam6BVFVsiNPBJo/\n+w0bE9Q2gwf+VNoOEgTyNlGSLODJD04PCp4v7LZiTuNRcqvb3dUgg6aOjnf/rv+K65gwcHMhZsCo\n3JwfFEUxEAxe1FCOjPTvtv/iwWpJU1UGq93TezYvJdbG+XsUMJd6YQwRaodc1amOu/8z03v773a+\n/JFgj5x63AsSRcAJEFFg0zbcJn8BrFxk122O+rO38JgbEEgLErO52bqYnYQWONptMU9vuBoYq4zq\nk9hR05WY1ijAPQ0wxTp2A9v16hr1OdvBu/Yhx4+fGkRWpflPRxzECFJWPHIC5gtv0HzYLYrtoy/a\nFHqLBKACvkVsVZjUZLsDG0CBl1LTHfkv7Mq1cTBH90xfvkaDvEcdSfBFVw6C4FeeoRmDJpMvV3BQ\nuvJW88u0KBGI1Zk8krQaxueZtuz9zsgMXFhT/7hXP63zyJVPhoBXR8t4zg/on1JdrmLHtIlA3Dt2\n5v9F1hTVH4w4mm9D3bVKPnM5hA7ZHlvOm54oog0YESIELd4AW0LEjkK7FbyoIcORiZTsxzZwRzTQ\nYBdT6x542AE1m+I71MgehxioIAF2ky+GIHE1Xc3R3khvAlCKaURwB0aK8xiOSA7gE4hVtHtcPf+l\nocfEFV63c/jVLj/qoDxSHKcleRgS8a3HslTQOfjUwdTT8WCJl+jcFw4SRkpie7l213z6jM31E+NI\nYXALlaMoNGyNphRHLrmNcLtXlAYsOhzu+pChMVAsogaEv7af1jHTOTtvarOqdxC70YCZKcQhnbVT\nWTt2NXzQscma0OOHYbMEWdoIXrnHQtUzNPXIUH/W8+8BzKiocT9/5PP/7g2TSJMAHQ/Fl8Bw8X0n\nxaTPb+TmhSZ3cYHrJlrlRIJ3ThPlLESRKfi+fHFJxYybxqPhXbECW+NUZ1ggbt4yCTcd6/YLK7Yq\nG7/aRwLnKIKL4ypI1Jmxv3ooFcJhpQIk/h2+MOk/8YkC+HWKJBpSBzjLWhUBRsTZwQNkAPrVMZpP\noK2TRKblTYpJqylZ93Y6CUUoADVg9kibIWZQsvVYrDAB1JdukNV1ZF1fOR9FgHv9LLv1d7z7EZnn\nF6lZEBJkRRXwsNRDX1kuF/6tQt6aNHULf/qmVrIqG9uRbdoDgo35NuU3ybcrvWIFqB6SkwRFjfCp\nRi2tEBI08tck4Xoqx840JhPUk9Zrtq0AkiJTGUoAMMW957W1JXMDsrKHyia5iXA3qYoL7Yz1LDcK\n4YIiCNl/sb/o/J8cDeuqGbFAHGSjFhnm2OVjK1BP9FDItyJBnH+sGD31Vmb3QCnAhYSDKzXA2rWa\nDSNIteaWyKh0d04OJCz66BrrtdOLC4xvdNZ9RKAwerPf2D0y7ZglwN8IRyFZuWk2H8HnURUnFnBD\nR4Oa9F2EJZbmcPD14Ziqu/WNQ4XKjHdlcMOQ3Sz7SlqnbMnDpQPxPBsxAJms6VDWEIMBiTAQXSzl\nH1gCsgCA4YbbI9u8VKfEyWqFaMUBZbTqi+wpooFJUbbefy1P41ez53uC2ilE0b14gaQDzglBBNKx\n4DTd20ZmJ+DqRAam8G7EMT6QYupHzb5YADQapXUCb29poEqbw6HSJZ0QzpUja7Laq9Z9NGZ6al1j\nIc2avOETip5A2bnb3k8aPjNv+1E3Uv/BLBwwqM7Z18nTcnnXjjQfeAfidPhLIRvDeZkRDCa95dtw\nHHCYlODblGNCkh+xQu2o6jsgFmMhPEjfUej2nkAmsC3mQOi7bm5P639OizzEkPHjA5jtvsvCagOY\nHrbXCv9NmS1DyJ49hU94OGL9ewNwj8kawzSaNEAt+r8kbkF03/mP2MhrnFZqNStwIOh/oEpuXbQ+\n/z5ZPlzQkyn4Cc6pPcOABs5mIdXAyi90pzsL6jCoV1/8mqgfvsIaFxmpA0kJZCu5PsTHopC5sdDx\ntSFIepUvlims4HQAmuyoHiZ+Zn25CQTJ6iiXv8GwSaR0nT3ratKZQpIKafFeqEuhMJ2kKSHHbF4f\nBxw8PZMvEV9yL+cFU41UKX46yMRQWJbeHh2pGJikKzvvPd+9acaZv7DQSuLleOx3juIrlEfOkD8M\nwGfsKy00+nvCWDXmDwNrn9nJkdPyCTUcI6/WletPGKkorXMiODhfHwJnstPo+B/lrcb9k8Ssi1L8\nVIF1SFEkBCMvGrQ6ysADD2jOboVuD3Ru3i4kGdc+wyq+sjnqbXfcAfzM7+yz1/IdJXdx3LTCOk5r\nct4ISzSRT/YC+LHqKIeNU+jTfB1Ut4jNiSAdbCCWzM50nWIMwvUPMtXor7kifYaBT6JdmtKKbhN6\n/TMo+D8vha2ipk7GSmzb1+S/1xxmNSAMqitNB2PZtF+qsUKaAqqX0TwAyG0vR8IHQIRANFi2L5dH\nyGL0kAmbmMJ/6VoLs+IhT7BpR0TAHRwQ9V8uNPecNrk5wBzexX4MRBELjh3BqiwRtzflyX0UT46c\nMJFiHlApA3xrXgqKiH7z6wrv8G8uoqAUvKViPnT1v4oQakyRac7cw/Oxb+iwhYBdfuRW3JWoZwyr\nBwbMtmloYmz/BfDam7dMfqZ9Ij174RFYJ8b9WXrMmqqdfA72e9JHlXY6iSuMpAerun1jMxVU7Req\nVJpuwxjhM9DgiLDy4wSFjL7b1oJpWMvVnlCOsXKZWocGrF+Po4pEv5/zcweODo3X1rTSNLIIsoei\nqTzwCpk5HOs/AeDR3Gr0HSG2xuLozyEk5KlQ9EFei/Fc2w5cWbmzL10x4E2KgUj8NUng3xaQDJ+b\nidX557kDah4OQI8z6Tyr2xT9+d8bezR4VuNpijtLVfFcFsFA4CC2Zzzu+uwwesN0Yl+6nxG0emFY\nBwBZbrsgPVIX8cp7U9zBRaXMznsm+KTMiDxLdYjiK4ixGMDd5rTtso5XrhdIZZ2AXv3UvaFnFBLF\naSyCc0jkEU5AQu0+iUR6XRbaZW9qUDPif6kXIATaNRwQqxaJTdgHIhGc+l6eM160uVjXW+0pWDrs\nAcSsTBne3oNrO2ZkcKqNE0inaIiiAC3Zvs0511PJTOu3Q6nsY7ejKZPKVSspBfYBJuQ2ojHfvE6h\ngewK/Fyrwj1lePwIWjgCA5q/Di9BEPCkIxynksPLPDv+7i11ZxZKsX3hJQEZu2PKhB46YQS7Uj63\np6bPAibsm1o5pTbiC8+Lb1OZsRmL4a1GmAWMGEBXLfT21IIQ7CMNg9XiauXnaQ+H9CSIyn0b/dy8\nk6C91P2WZkNpMBCKp4hVh5KhYBWr36WgberxSUY8S2Z7QiJ2P2JfSC1HIhXD99v+G5RbC9Z6GXWB\nIfqRq3vgaRjLiBA46EppfMTYHRDBsPRrYwFdd0NacdjwhkYbjRMa9m4B0b5awGtI2orNkizy/P6k\nvBE4+N4NksctGjrzmq6ov5JO5y5WBIkIdmCgE7OQs9waau29e2EifYVy/oTeqVi0SI9135eRfoA4\nEjvBmhq3VlMgEt5nKogtGQn7NEZYFfdKooxaGLueY5l3uJBl1c4RPHxdTFXWGd3oQf6nPo+dxdvT\n0Poxpb9miME4quk6mjZJeEucPgFe//ds0Ej7Yh/9rGRun5M6OfGv7w0DJ9c7VvEvWpYD8FQ+BJ7r\n6LIyU9rmr00vAwA37uTdEsITI9Yje0W6vXemk2er5vaXfKKSoQNm+57k3d5CE38P2fKW7Q2iK3Wg\nDbkbPv5iSKGDytvTyvwelLK4y5M4y++E42tTwgON8DRlBlxwD1IeF3rewCnmveFzCgkIk5Tg45Zu\nG4AXgxJcbX2LH6QCW7CMP0tqPrB2N04mky3XKtq8fsJJr6jnsU6E6IKJQ7gH8OE++F+uEJ8b8Gbb\nb+dXsP2TdkIfhZh/dtPuToS8wABTpaysxAF5D/TyKOTlHwAqpZ9GlPbIAaA1iXlT84OtEwn+kTSf\nhvxgPBPMYZK0aWvmgyEhAZcKJprdxdVs/S5QMADHmOcWr2Pt3R+vSDXoPvhzWBzdom/HWlyK/0EX\n6CJ5b4VRiv5AuFu3g3Ekpyonk1nA8Op1yBNY60S8WVd8Znvo2vpJiKEw6qgRhdYNCiYp+NBQTSaX\nC41878217J7pzAYDmrQFP7DLG5w6DofqPWaj6Z5kdLZfID18mG5o1sjo/xzFfgebh/Xi42lvSN2P\nL7r+6yYBcDf5bcD2BphSJ6mLD0t112qUWwGI40FrLzmvz4FlRNMYnTIkC76wZdv8R4pONRlD1DWj\ntgfEhz7QznSc2jed/HOmlUJDTjPTuwVaCGzGcLrQ9AS4Z2sIm6DdCK7b1Lwa4qRIIP3hSRfZJZig\nZB0b9JO58gaSty1oUJO21s7ok3pxar3/UK0jAzpVh9gHBzd0/7chZPEw1rulnEckwIlBM38nkjmm\nyVYxhNsEPC8FzsQ2KCaTZitIaxCQTYCTlecz4rKrGsXTtCwTyFQl69Q5BT8sz9ZmCehXW4NmFbzx\n/78F4Qpg4W4NnnqytnTY83RQxO8+5fE7gw76LXMsHgeJiHHzd557Wvo+x7wK/ZpOpnnxQ6oCOVnu\nXwku6RumJ6GimEr/9pfkmPGvLfrcsouT+UEePH4hKRRXqd/vayKDR1JkX8b4bF4nU4VM6bw4GBOZ\nIXVeH2lcr5GFcLmyq9RorN6facMVqopgeh3DWvan0ocsCGUEtxAtWjXd/jYxyFhs9Cj5XhBP2wZF\nP6pvTs2lsiDp4pJIYmv34AVTMfAMxZuD6bJQs8UgQiTr6DwjMZtsjMAeHVIGE8qBCoRhb6iu31gt\npkbXMmCiTHRXdLVHPr7E6HN1wvA6XOPhrpHGxrXczvlRJBGDD2hRTgbGBdwAPFOfFq7MRmEMfji3\nT3I/hDupfrwrI9obJTyXtA1tVImy2Lhsm0rq3KKDm8uym+7mWZIEhHxycF9YGt6OPSTVXJteyM8k\naykOf2zl8u0Pn1Qhw8Z561nUM87skdv6O+Um5Nk0zGXoGsYw7PldxhXYDtySeARCgSpERnowIDUX\nsKHUFgQiUPBY4Aq/2vo/2icQpQc08ZIWx+lbfDJb1jQ5Z9xGRrkzwOa79idaeK1Ists1GI1iOms0\nznbiJ/GV1T3pJbUJG63bQfgVFxEcxFL4kqHgWWU1QG92iWI7WsOzQBHNmjPY6qG765GPCCWXOOrM\ncjXRu++6FkCr5Ua+QE1hKLUpHC5M8Nj3Z1GQm6+JzY99SMjhJaCjKlv47CyM7MYOxFuTY6ZAEK4D\n0LhhcsPwaT4v2qkgklS2TExvbSIWHeV5E+PPnJbuB92+pCcb9xYpDHNSe0WEVo1uGJJnokZYGKYi\np5cJrF8kgurbXyiNonpwTXq4buTmHaKlfb/MOdhnXx8zwlgPmuQ+EhA3UwB6GLUkyerME5TvJuGd\nT7yGW9sBbkxdkhI/o7lsLYRKJiOPkt6qxA3yFDKsRif7rh9WQ+2TBKQg455pQtKA3KZO651hvIY3\nNV9tTs954VfC1GC3Cqj2gC4ZIGh2OG04HiK5AolWnAsTJbnXY7EoGRhyrf4rVrdYLPaFQVKzZuYX\n0OITFNpCTYEJw4CkKlavz2tnhWGWyiurOyMXLJk231ovVdLpTMVJOvNNr0cHn3DIP0EOQm4qsAA0\nNp+cH4tGx3YneBtMxi7afFHG7EtgUmqi8Dwl/49z7+5q1hKtylV0W0k/Vd33m8/wU1YYJMfKqydX\nn7YaEz1rSbrDQd1XD6S3rqf6Q4/muGLFmhXZdjfABKMTlTWRjCo7uew3xLcBlob/3dUAWpOgv5E5\nz8da5xGi7h97wH+oIuFyuJp5sMwwcs4u8RzcE2jPRHZtw+eeXulgRfghplGxq4D207hjIXShtFi0\ns2lN0J5++EQYwZlohXmYlOF88Da7QYvBzkk67sMsgpD/LpKGGsDYGy6WFrkmw2Z3/wa0Jl5NGm1Y\n0AWj0KhNFX95ixtsZqZZQfTtjYgMpYaHzxJF/+P3ttY6ZEcTQdHw88ErpksWswca2gacAPMOmsiP\nakP1m9Gy/AVz9ZlFIG+ar54ccQDerSaIjze+jrjdGIIeYqjq5sRQ30flJM9SKigP0KrmkzkkpGcn\nMVOPTJOyf1jGrVE0q7Bkhvpjngh/p27RfmDjo2qI5mjgVZRZOTjfXOjjWJYc1J6nRWVHsxngNJwU\nKdmzaV0u4vRhuuuV06nu0H99P8G18OxMQrJEtBbaI1feQkCcBQukc327Q4EtEvmtzRJq1NLjV6a3\n/qdq2U+n9grjMxQaswC4mcRhNQfqWCvc1PAaFlpgwQNV3W8+JlHbB0VThm9w2yXBaq+kruNF2PyT\nQsEbwvAY/Ctuzr+Jj+V2g+/zTTztMxDCdDmLZtXDoDsRpLWOLVdt27RtQ4zM9CiR0MF194d7mcLN\n2xXATkIidrkmeRffESn+ixWO+tfb2l7xc/wKdHVEgLmmsnne57wud5mRxkPohPU/XwwbaTZ0w0tk\nEEo7Ae7wUQve7cLuO4gZp9Xy7I3wxU/kYQZT0EfUXSEjyB0IPlP5pEae6EgM7KBLXSCt/BDLBxqU\naD07LhqhYsTkzoiuQolTPfZwRX89ekwywShjj6zmC5wJU310K00ZeL0QxNwe82vEpKJJUHcx3RFj\nP2JirFA8xg5SK7vAwLvyfXw+QOtWxKRKuD6Pzen72JQQmnp1CQ9lcY6KXgdd4cM28/GGKRjtZtnm\nENCZxoj0Q8MV1MYDp8DmNy5+Mw6rrJi5Js8qD7ioVdBSHyJ00DcLEspNsFIlBIqSOqrrj6I9CSJB\n395FN4uNriUehNUzMWrUcvzdXWG1aOkUkRNgqerN/qH9ebL8JZIg4LQ7YoK+Up/JBQWCZuFXI5Ws\n11hTPGty6JebbXvJf8ze0/4evO3SfCzd/DZwBA3RBiFqL5flj5MQ9VE6Y9iszlQE2Y7on6SDdnwC\nHWYZXQuI7vI1hXqZWJYcmNoDbHaQR5s9G96KBVIbCfBrSgDB1It2iMnyOdcgtz6DEnoNE1dNJImI\nWTCn5J709ikNpNWc16XDM2ViklkOirXoByCUsPjqnvpERZwBqgvXmGnZ5VkdpE0RZKgVN+h/eRhJ\nTLuNDMgqA3Zwn6He43JWarLn6cCPIGxUz2rHFxl2TB2Nnx/h+9bDsKGezMm2i7Cc5rXn4NZqU1BX\n9GXaIb/vdqrBMxGxU7IC4ew7/zzuXB0+D3zS9V4aqbK3bigs8Dg2IOKYlbL7xUblNNJykOmg0J1w\nXviqXo5Orfu/zZkMtDR4zsjy0C6M3lfuF1opli8FaX7aDjr/iPnmQ9ZgPjGTo6lKYP8t5Y7OE/bh\n164OP+gLJI3TFRnm2lepGnvvpKkq3Ss0cRwDJenyc1K6UVyqbdiAyOkWsp2SpAe0HhbMQDckVf+E\nMekJdHfVRF9jJBifeKYo+cp5E0DT3BRR4NnGFz2CxMiScbCD8z7Nj22yE8uR2P6pO+x0+IdFQ4ON\nTZzDAvJLs+BdgLu947A6TIbwuKsWx/sy+7YbJw6fXRRH29pZzJrw7Q8CNfuXCJhL+8Ng/zNBncz5\n1/UYLrsmccYhdR+TdWE3sjqeTPkCu7Gn7EpgG21CcQhl9mMoVCCQSjzyckAEHviPyWRNnz8E9+bs\nvAhybuPtj2O802S/dNczc2+8g5/ccLV/eJW4LndP4Ona3xwbJd+sRFPV6lbS33BGLPKi2/TXzei3\nDgzUYEvaO55ztzk9odyovt/EHdi14Mjbq/xOA5KduHkAnsKg14aBsIhDQv+0q8MX+cGIM9uZlZwU\nKQborAM3mwB+jDpyp2D3HwuF+RqAAg5kXKjTgjIGAf5EB4jwEu6oiK8hm6hwVjYo6gw1bQUizZE9\n98DCLgNUeAZZIDPYNmi3yswjxSIO7Sc24bX2iciYCf0diQqih4Jcz+s5gfhN3gSFnyFDk2JOu0xM\n4Ty/t7IJJkGn0tMU+KmQo9VVGaTz8hr90tI3zn9NC145kU7JdfahSf7k5h0ZN/zFyQgh0fWtTtOk\nd9oLlg5K6BI0haRCKHI6ibGZ2SAFlMwPG/PsxrsRA4qu4WZPco8dIC2tx42U5gf7tHslKtVDObui\nVmPILstbLvKf9C5U4DpgkbBQFz/mFYMgkxjqNBO7dtj7ZGUuWQpdg1n0W3A1vBwHRqYCrveiYR/o\nN8RlnjosP9oOeZ/dAl+ObuNxAvEE4eVYV0m93OreMuQsXjxipqfZBlldkyu5UsLsy18mQsxiNMSY\ny/FGm9jKMSFv9YpmYTq5KdQy7EWov1KILWvBjuBsUZFd2Z7o3vXfRe4IdOSs8rM00nuRaggNcobd\np7IpziKiG+RQdYMcJJ4vDh5P2X/TgPv7qvMWzIBFu/rOf5RNqEHVAQIulg7IE7luZ1S5Mrc3em0j\n++wuOhiJ8/x/pRGiCc3c/4pVWD5H1x4WYxk7nkCAqj5Q5Id2KIec+u0BxdbA6+CP5sKj2FlQG2q/\nkMmt/QBVjSWjH0fSKF/mVL2JNUBwuduMX9J2fjPemGmQqZ3Ul5s1AA8viIfkUw3vR5r0w0cY2sNB\n+msep1R56nsJDMQCmOPrNZfKdnh7IL6mBpmy5+vwhOjd1rmdBYG0oRkAK5xfRen90FiO342UIrbD\n7BQOfMVCiaSk35OLUpAcm0Wd/wTxn6KJPYOJAHjLGtr0f99qpT/TKUcqrc6q7eQz4o5qCI4d1XLn\nT5UyM6MuLLMUF6GDabDVg82sI//hmC8yUWoej90TtnGPPRSHjepKBLAsnY/OhU/76L401SwkSyrE\nqlwP0ZAMKRRq1MH23qhBVnqK7pOmDxF2/YElu5UIvE2MUzD83JHBW6rZbaKfiEZbOr5jBJWrsRGe\nRN0X5MJ8MZ7M6yH01oUGfXaFsBvfa3g9EQbtKh9OOaqLYyHkmXB+h3zaolqVjfe1Tzx0OfTj64kC\nkzZt3zAoXwHIOYvDsQdE1KcXJVLtuvBhkX8zCiG6+qb+rZmlzVfzRrDzRROrROmM2Jx7jxkEXC8i\ng60IiyKt0G31fhH1UqZn57ai6HrdowtGgQEDsB7e6kZTIHDfDQj0sPBuK9WYlYmSdD7EeqpTeTG/\nWCcC5g0L7gHYD4+ewqaJjzWeN0+X/AFG4w0o3u8pzHqW+EOARHDawtxsWYBezkLxK5h8tQGq4soi\n/ykG+nompM7khFfGJV3nyHodHdPRu5D1fA9dKekrR0fiINx/4FG8PsMStlDThjLY3pxd9NO7QDco\naTq1HRzU7GnW7CnSvD0+oN+HX6irfeJbdgMN0NU/F42a6fXwH6XlYAZ1to117tEaZdV9uuxb2eLL\niDl11JBlT4YEVzw/0OCxw1Jrv7XPRxiYOmaxSv/mmqO3Zb14hk44kmFTWsnqX+pjE70IilE61aNX\nqEAzwogh2g+X3IU4zoNXtrc5oO0CkmodLjJd5+rJiuwVGyNCz7WolkW6dz21oOD848y+HIwN04B4\nVHh/2KwBNOGIkbTLf2/Q7WrmVbI9lXXfVzkLeunoVHK5abs88Ji4GMUqpO8gMvndeeqeEt9lWRgw\nFgPSZYKxdNG+3CqmRhUl4az2SmfZ5IWuM2nOH7NREwEsaE80ELxALXhNOXd3qsTV51WBzytJR3J2\n8zCzJEp2Po/wY8iylA+TPDNyhvcA2+28La02c7OTsqp0zdYgthQyNJlCeqtmp6tlxyKAkjckyUCc\nmkBMaOms7jrGXP5lWfbt/Tfm6t6i+Ba/c2OfaEjcDj5ZIvYRab3UatxjX4YiRXk7X7dhyPl9j5Gc\nj7854hUQpaINUntqPzdxi3FlL0x7jwpV0C/TpPLXiQMHmeis1E4d6dLFJjnZ/jD86XYOx05BEgMR\nQ3/Z+yJOky5JMynHxfFkJYEhSJyw+C4wT+Y9xgiJ4tVmYesvQQ9V+fnwMDjyqtlE7t+SUceXm36B\nJL3CcDzG/PAHxqU9q5YBs492NTkn1Nd4355eLmZzwSJEwGSmZDRGeQtyD7NbPRWbOXpBLPUtyyuZ\n51MyrnYZ+mZQ91ONvNCt8LQb/ppVAlEp5mxRFxZAaHTtkgBMP1jHruY2J/BFzyGNx1wQpEVOmJZ1\n3NkraxQTZsLrzGhYNI4qoPjiOwoNbMh4vkRaz9Upl1aR1qVlCoQefyDCplSntQCGN7bBl4+iklsO\niZ7+Io5AcQI0eCYGV0WBj9jziyDWKLP0DVVNAQF4PIOgayN1Z88X99xrdONjY1dJftxa/ml37+EW\nBL2Tugp10EkBxBz7NOFIJgToKE4W/fwfBrYae6I7TTX1ZSzN8LX7+O/2hEHoiIF7MP55WOecqfTr\nU2N2/HkXizfiMnOHaX+bVzpDx1sqG7X3euBd30Amml2p2uRk3+qIhvb3PnwNryvwQjhJYqESVPR4\nQfHFRP4fg4FAhp9Lc8k61OE/RyD6Jtx4RSCNN7rDwnKaPyCeRkJJ/kofTRTdOHQ3SlscD6DzUTCu\nMm5JAs/2kp06sOk72qw6Slh37TIVCK16DmZ8pC+I9hL0XGaeg9/1v8Bn9EOrrpxMPFPzU0YuMUhD\nCkuB4f6dUpY8IM9bQAgHJWQsAXhv6amnzYbJ0ssfqERETLC1GW2GtBRJSd/uCRjWw+BKa/rlwONo\nZPC1kUC2kHGtBhWsHEHF0he8bcpWTFUIBJ9g7t7QnbKDn+2bpgONXQOqCfsgcQ/AVkAPs1idV1R4\n5WRrufDvGN4wTx3/wPyNKiuwWTuheU04VnE4z508Bh6UxMwB8K8l69l53vcmWHLs1ixXMIUo1PBR\nIYjP7k2a/vWiskVfeJ7zzPBJewH440WRo9xa6gIa6wFRXYEmzItYy+5ANjb4abDIakgV3iyq04Lw\nSPNXdEhNJDXJ9c6RbUDW8YmJsFXiHvE1E7RHLFDJsZc/S8OOcj3IeIYiher96fwt6RVeYspqOdAv\nHT1LL9pnbI/Sp64XtcVwHJQekubgwg2gfMDUzglOdxWJCEziWfv9PbIEB8wAEyzQo+3TH59rAaIy\nqXV0bo29IR9ah8IByostaAuqMJEcsJ0Rie3TSfxGo0ffhJe6tucUNZDy6z7X6PE/hO9MTA7bAzGF\n5LgCDV5PDETneALfq5fgVXnCLjs1w4y7N2IG1Kcn7s7pHc2dpnai6R9oBmcwXijFgv+By0y5iUmN\nlH5zIoRRweaxTZozqYtrT/d9kc+N8R3njUAV635/t7mYsjfZXarIB54nK5evwOT/jPikj1EeiwVq\n+UMuLnGBtWA4muO0tktJIW4Xy7k0YDFHwYrKPPMtws/LpGnG7XB6quhCbzi0Y2che5ijJogqi56x\ncKSsgiEiI2sU8DMaECT01o9Dp8ayOaV9y9g8P2KOpBLYQl8U9vgaUHXOpiB7HBp98+2lbCLPiQnD\n7b8JvAHQb6ZWuwhWJukkMTba3wJvzFQjR2q7vFJ70D2aVCMWJOEogVysfs4z1LYJpaw35qczkMyz\n1/b28GI8sYa0xr2d3qN9A+axim3QTS53yKBTBbDHZbE+Od+RLubX09N7L8T51jb+wJbmr3ukOq/y\n/zA9pIcIZRI89NQTSnY5CBcOrDPiKkL+kiOiSpzvQRKfRu0kfu/7YxzJCzuYdm/2jMsnP8V8hwbY\nWbnQ0pTcmaDhbw+IidmJveSQEhi+TXFHH0iD4V01sNAggousdhf5U4ZfWwHHGG6tmFiqmja7aOIu\nnqgEKI6trhpdvCM1ZFz/1RyUUDeLq4S9+l8b14WHPOHfGKb1/dGk9wdn8iqOVtmfeA37Of4lxIe5\n2Kf52JI+DcEuSyOpC7ferp/tCjDl/odnpEkzeOzNrUbu90XN20qvJ2/2/v88A0jgcBpkfL7kx47I\ny6rVgQP+9Z13ZnsaJfqI8fh4Etwb0xg6DIlFh1Qt107sLewWQ28bA4OWt4KmDSrCUG6u3wsMr5wl\nfEa/qTIMGmfKZuG9nO+HygnAXVaMBidP5FtqVyNjZD9ZJ8dLAPJUB+1Kt4aHyjcDsglE2Tjie8iz\no4spl4ixY8RGshrbuR3zG8+f+TVtxdvCAa+o5iybW86YX0sonMCX5w4OkHdJxfMW1/liz3Zz4cK/\nxTrYYa0PjSG01EUOon4sD6yDrzoxUf7toOCcI+o2AiI/rE1S9ZSXZGw8LJ3dHA2qIzDyN/zVLgrn\ntBBXj0b9naehR9CjT68d4VvOaTQY2oOUvMA4wBukSIHzMokfCLSrpe1XZPNICp83p94mdfYBW3su\nxJyWRTngpyLz+jJ3rDu7j8YdphFdb6+iJTJEb5iPX0tzV58istJWVmLh1Ktpyqwb/glIbeX9+T+d\n6myJsZLoVwsqSUTuI/hnbjk9fO39stSMuTh+f+JjihVRJsK0ghL/hjeeWimNU+vllkgxS0uYu9GP\nwiAJABNEXEeEwvzcO2tMraLugy3wta6/i8GFg8Uqgg5e/2j5ozrr9H39bZCP1iC9aoz/KWM9IFJd\nJ9+pKN6WazLNXf2aFvO7GTxP6zZrNGI3yoIGznD+2xeCPCwxQ/2zIGs8JY+5Lh6STabzx4Q4Vs+F\n1U2nQcXqXc48vnFQ9sJVxwrBU/a29pRL+K7NqJBQhAYtk55oRQrNQrvFB3DJNqqpjdOBaW7dIK0h\n9XkccroP67Y/Jpirptg8iBGwUTBPM+RU/wcUTktgthmaXoAxGVXu0JhPVW8HKhSDLWlpCvc97vdR\nr9yWy1DOWZNYsk+hCaqaEaVp7NjnDtA0XqzrkfscpIYnBE9RNomnNDdMbjp0lHtdf3Iy61Rc5htM\nTqmvzbdjcShfYfffqTeEbT/q5KbM6W2yJF6wCy7opOvWiIv2XIilK1KwhBpZHaSNzGgPEFQYmMQE\nQK5qjvXgBnc+lil6wdlFiE6iZUCUrMYE67Cjes2TfoDRuGQjgGAzufdGJSVJFsaINzE6RVUdqkjB\n00dH0jnjQANxUeHHQO4KfobYSOcr+4ShmRmVQrZK78SlOaj1b1xuKUEpFtHmJs44E0hCOtYneIPQ\nq4pJPj+W/ib/QrXETLAYrxxu60kX+aEcKFzPCwRnE9MzGWYf5duFQiByDUlDEkQTEdZXqnW+j/+S\nAvj/9mfYRRMhBIqvR4BV/Bi1lajb/zdRKcTPkKmqwzrJNe1El2e+Et7ppjLjYj+Gf+hBWNWjrbeQ\nqeKI8PueTqpeI9ndiTZmy8WuUMsBPdXu6BHk9wdLJAuPY19HmucrBbVy+jNcCClPH6HEh5tr06jD\n1Wl/Rrc4d///lYQBNrBSUo+X4Js2YPeJZc6irHj5InoFwRsqv0oEFLlrlu/HZsyXTkqNLyC7/xSo\nMrXfzdPbGMGRnXDxATc0l5eAXFJIxelTLuHLlum1lKC+w4uBaEgzegU2AVKFwWGYP+6QtY7jI7ai\nFDB04u9ayLh8d4eul50zeNes7IH4vqQlzxWKYj7t1BR0f+VR5/aFnbb2FovW/I6K+TGeCLmHw3bY\nO7khyHO4OirL4X2dJhGMcJtwRt5+C6/FJPyfatYyfBjHYbtnF2BXeIQEApShhrOCB0/l2Th60iAx\nDcS155Nqx1gB4sd1aqpvvbJkrXv6sHnQljsPnme35tszH7M6x1VT6mfp3DC35xQhl0QG7VjDIX9G\nJGLZS2uKqSmAz/58dw2EI+zTVT6jMcHUGyl4lJZU9W7WZvGr0rZ+WDV6bPTwRzVqWlaDiq9MRDq0\nVyQM7MnL6ynbe+Fi7bMOdOdkcHgqqRBGWObS0DF49h6g1LqdKHpayT8vFJKLCaBmkk3QndqGfdSZ\nBrVKPISV8W6DslCOcIMTFtImVd7cUzC3cflKvECbWPJO2Elbt7ziTmBo75wLutiCfn3KKtj0Ffcu\nQeKf8NQVq7HtTQHrbPwh8jnGLNdVlqgkaXj3JQGYWTN0oslL8nbxO+2YFwRzrYIuqhUlAk1MB1A9\nKGUkTSnjHxFPXb+BBzkZMkEn1kyQQ4/q/7uhtw+9C3qV1vI7cruzLy50jXqhp3hTEIM3dOb9z51b\nUFUvNBqGZWXAxnOpWb82+74AdsByIq3zGgFnln+zuIBOoMyBrprnNDSxApRyQYir5Z9UixPq8cdq\nHwK+YYSLFJ4gg14obWRt39d9FU2im6x5B/rLkH7ioO+eN2MuVXKqzaxJFYE0hoQp02qZoMH2vBc9\n2ObcguNJweeB4CUmPYmSTSsZveGqfn9qof1lSfppMjfdNH2zAH2YJfjjmS+qMYePbMQwQtxgncKr\nlB6Vw5jYNGxfpy9OkCjalnazZLmYtLiEuaPppjYR2Pl8dC39Ypzk0XEyverF3eFrSzRtN/j2Q8ZB\nvYmNI4SC6TuL8WuIlVsNwZxaqCiLCegdrhFoZJfSQ04uF10qel0rkuryFijCvp5hE+EICBqzucwz\nV0Cw67t+Ju6IpCLx++YgH+jv2+2z7H9M0c1izK1WMZNLYBd7EMmBohiNXM6+ci5LTT55JCh1qYdo\nvn/flV5sG9bBv0lwDybu6AShnvpEpjD/Nh1kenyagSX+vVSjCFxzqQN9Y/6ZrJ8gzulmjPyfqSeX\n7l3/jSE7O7AqXSoa9YeQWNw/EAsmLQpCmbP8PzcJBh+zzMgNZwLQJ+O+MrAIyR+dmWe7JQVxJzGc\nd989343qQjddHI1OdNO9aCOZ+grbhP6ObWhN9V1TMXDg42trGiqCPse7iZwRmEIpbFmpiwLWy0Bb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yaZYFgCAdbiWG6mrs+IIXXe7x/uuUhJUTV9gSpjFcVr/LZmLLxH+Jg7odw514/\nz5PrF1cUYjDakvwj9D0JxvAfe8w4egh+yF6cutvSoiUYlqOlQj1G01SwLWpx+GUsQgd2yNiiNVsR\n7zFL5QKUCnatCt74mCZtdtfxm9OWqC7LgFPg3lEmy3uYMCGKxuda4CMjzeFAmWpD5bIbY8haBlgr\nRqo3r2w5muJTsgk1XsKnzjMH1MkX/3wqK4T1ZZkoBfi6oy36nLxWtfgIb2y1IAC/UgVUqCKpWet/\nVGgtTJtoBsPaySK/Wdr8mXsd6NcieLqp83CGCkC0P8tJ9bZjTMkIDi6b1PCAAG07tLAsi7GdThyr\nSZbfmK9Mad2n05VZaQ85fzzth52fJBMEPlAdSS8Q/AeKQ6QQ8vUKzDchn6aF2eApAMmycb+ImU5m\naEsX/DWptZnB5UYX5SmzwugmtQKIl89FIXROs16z4pxodYNUv0LOa3gEOopJOEQUiu6GG2KBcIYc\nBvbLbEGPMbGTjAG+dT2qan7Q9twu368Z8hkHnD7br3e5XtxPLWialaSYO6U/lOcSt3MoTkfwXtHf\n41NsQCQq4ACpBGFfWb9kic2vU3fX/86kZeI05OidyM/A0fEsBfUrzFYiTpT+PbrjmtIrXrL9HRCv\ndFIm0Kh+GxKEWZ6Dk0CfGq4Me2yx8sSF8B+B4UVSTyrcJSQ1J/zkajZL6VOXd2XH9pNshyWGdr0v\nZ+E9EsUm+WowElBsvyP+2xF5pBXw4Nh1QRpA0R8B0Z1hwuTKvmzMyrzxs1J1/V9gpxnONQC7UYoK\ntDnHH5WspLO4CMHRjY4XqOwIFJZCHbRCceMeTRjmoiQ/v0nX3sKxSE3ZID5jOinPiJCTSkcbpVX+\niHFQNdXpVPwaZV9Sk88xDRdb+HPucUDguJaugq/VAo2IUD0Od/dD5CYENob0+OZ0nMMyusqKU07G\nb8SwJlij/iOaYFwXVWgzrPgg9dEnu42t/mB5FAFAq2jLEIq4UMW+1dfoqpz+L0R4KvnaP661xIVb\nnU0Lz8NFkfFWehVbqM4ly2cEQD6mj4HoXqWXcyleRF+Sm6t0/ieNqEUfF647TWEoMb/Ip+vQdzHk\n+nXPesy9Q4+MWsQpldicSEVZ4DY0HJY2iuqUO3/gisC/lMw76pz9sE6/LVMx6Q0I3ZWlY8NbDl87\nAhrhSiFB2Ld3c0IUrPLBlHBuza4NNWIdj9KIXE/FTLvOdqyDe4JP054Tc92zWSZvlS11dksOHw6j\nM1K0qoIf0p/A9/Q32/B+j1LSkO4p5rWPzqST64cflqXNKydvx72aMW1FgUjLiVZSZ6/ftTySaNBc\nBz0FLme2Zsh7RP6jRR0iat5nPe1Xi1uUgkZp99bAHRUvs6J5y23MJoqGPFJUAnybDYaGslYFCeeb\n4hMWmVnNwk9sLG8OYBdDdPhcud0zrjRMNUgbd1ERm3sEGyE3GlR0hVcwXN7bPuw55Gyc7Ddd6mYp\nplrfLoELuxIrAt2Mr69XVZeT/GOPqE0kgThgOcHWAFGuAPqw9WKlmXvUTd7jPicnwgWlme3PdCPt\nNMgiMyDx0e0QR821hXsBq8/OK1I/LUjsA+979DRiLp8J61ITwk/Z61F6C1mQ933VC7p/BJxzuSaX\nN+bGOfNz6+v6kKYSifpcj1EM36m90WcArMdYeV9Ngs51ippPZ3vrbhMQrkDIDHjkdRr2vJbonbr1\nZFzuCL4pmSuzt8984n/5EV5OeRYBRIbnuSOAXXH0Cksv/rq1BXjJhxObiC2+aSq/2I/YbFEguvlf\ncasSj27TVI8GS55e8WGzEguDRVL0jXMjqJJy0G8MASvVtUpKSbtd6D5yh+GUtcu+VklUjm2/33GC\nKuzEV4Zhp42Y5tl3Tq8H9fnBYQj6+YK6cwdBAUyHsxr6hSdP+5mdJyUZiiBCE+fghZBGDUqPfQAK\niSlYH030FjI8xXQ0xzissKDwweJVl0PrZdjhyOLZn+v8Yt5iLPE3A29vK6YezlgbU8nxXktNhNBy\nBhXwDFTOpujC5XuW16QyvF2eEGpaHD3ZQWk+ho1lQL+rNwyKR3aQ+FpO2jaAtOcffAydhF9VsbyM\nSf5j6M9wvR+qQuRfOLlxBznQcYyyxJbuiuTfdtU3ojDSo/dD4BFIf+agX1Xsb/oyubt900DoHy5G\nw1X6ycOCuoyunsc6L1bUidZpUIEmoONb1c17UVo7LPYM8ArM/lGYUO8TgvL35/h1dfg4XlDSQEVg\nF1NjzPNrw6Up7gzrL3OS4hpAQdPojj5TBtZsdo6NorgTxFLhzNzWrjOzHywDbsyEGCNlVBA0ONKE\nrzi9maSghRjjFiGS79m/Za4/ikfIjLyyC8b+IWyDgAzpBt8BvxBWLkxr++JPRYwmpZnxwKkZwibm\n76sk5jnhDKkhnahGTCCEqQXZmoXK2jYfo7JSSsKhGitBqi7n5bBKgndueFfKA9S12P2nSdmssKd0\neQm3bqUIdWLRVPU2kTsNOnN4/kBJeRWtzNyzlkUyipo8qaR1RgasLJinJ16TOVaJHHzjbNUcaNm1\nu+C7WELadK+LNs9gdHU2a5+/953OdST2tekpsYWy4YjA8iZfzOk5i3YiOucIGcixNR3F0S6IimU8\nslj9LiCHxy7BcB/DshcGVu4GyrrWY10B2lzKpNZ9BD04HM8A7PkDoqzat5Io5UhsIBPRd4teBvR9\nPPxmJy5YYXlS47I6GGELTxzBb2SSU9UcLXGhofOWmJfQ7kY8Xrwx1KV06s1i2zm2rnmGgonAJwC+\nB4JjnfZpqaw6tzfnm1tdS2iwsie8EN7mz52yQCWUpqmLSGBGLbhV3FcE+HfKbpQQLY7knDtTS1F0\nAz7mUx94snnqG+N92YnddEv1nr/iT+f9IhaslXDcpaDQaS1nj+TiS315Ivm+dqycejZoAP6KbSN3\n5pRjVDINWRAoTdiy32nr6HYp//kBJj2MU6V024tQ/bwSNreC5BRnK4kVT9pgOZcQMwXr3FiZE8Va\nuyovlnLppp2TJgLyidXK5L46zoOiAlPg6ir2txPsjHVNKGLh4UHju3Ef1pvlHb/J073vs5ieW8V0\n3l8e0zvnn88J8Jh4j6Tshn6v6svHVgxRjURfFBGLNwm6x8dCeRs5Gtc5/WTV7tDTY028JObmkwI3\nWl6vR7khLM6IjIqGEAP9NXUnl3easdQp6R0WgwCN4mbXWMIdtTlfCkFlKt1Lr1ZOarkMwuKErooW\n338DJ9SEzWA/GjRSjzhc1w9nvXXxg9pzqD4PoR0+UnkCb4K9AY93HQP1sqkP7aXmg9Vicwv2+40j\nyaL+I1eM6HOmexLvwLMdklygtpWHAJ8nSau7SAlR0wpDBjI7v2iqCAvepjygRjNRyj22vGY59jBi\noEd8u3ist4XVXsFl6WlksL3PvM3+BpOqUi42vPjojBgN0HFlr2wUjamkj30ks4Ewo0VOu447yuW2\nj9pvSN41CNAO5XoBT+hL+iukUd6W5cDfQgWutfamqX1t/jEl8INqDXdmNnUYuIwK1gprmt3k3YpM\nZz2ilJVKGUJi0f5qsdPBHPjR4S2iSeAXI0WenH0keTzfP5UHLWzFhA45lO779u8ZWfjVPLHG9Dnh\n4493GnDM83S0k+PP2Hn1C/EG5uVpE9haI+7ie4r62dr5buf11vLsCFe8mU062S5YImqt304t1WKR\nNpYoC6ryvrzFKSgs85vhuANQ1c1ATfHBu/jLTjiAblbLk2zC1PSaO1RX21pQUjAigO0iX7EQaT+8\nYoobs81Z6yzpakzexene7d4HxB8A0NtLFAVYrT8aoZ5+phTBQP1Zjs1fV4F5OebN94q8ePfhv4TO\nkY61KmtVZ9d0XVp0YJMA8DQUoK98QEtK/+KVkqLcfWJvYIvauSuApTM9rzfMWaj1efGzFatQZI6Z\n1aeJ9NzDUzPAM5jmGWObbGnhatxa5nYE52rJpIjnlGOMRJRBmBvcsrOipQBUcUNGHC15I7T8z+/B\niWxKojR6mY2L53qLv1k191A74CtIj4f1uIICZ58qlFkr4VW/Hbo/EKnEKAt2ePaBvWcm5Rr6zi2L\nlBKPFa+Ios62xRrhUflD0PJYsrh6dRh9KbT91lptADZ237WcfaBkyZ0/PkvRFZt7XZ2ky0bE6VRV\nH/mWp5ntkQ93XNzeZ8X8qj6JRxqHVlhLcoo6TT7OZ9KhOipk3ZLN0D+1UlYmacZ4fmFGdAmAg7TT\nIz6VouJtywPQNZ89NeOUqUfzzK72kmGsQzbxxZ6RNSFPNfURkDlRTHfTLSBDsAf/n8GhTA7Cvtaj\nhP4yzPAYP/vxnG8dzj9hKkU3iYwbEx4Gvku7CedxmF3UKLlofiq+ecRdXSUv/TW+phNUy7IpALBR\n9wth0ocvom3Q3WYrHJbKGh9G9abErJnqlde2tjlsAbkKYNblYaQYLXntChIiu1GRtpD3ExclseiJ\n+ray5fwS0UbQVHAonwKK0GDMpo3aJkOO80BEZvm1iHi14xqLc+JFT8LDJ5JLK1Bm0uU1Cr1R6ByS\ntP0jVWzPpCv8MprVvc1xXg3m5kfUCwXLNq0pN8ngB4VFoapPP7gBauSDWLrgFM5dwG1NaCn+1o1u\nTaacmRAche8AflyDeaVv3qCvVI2OJLrzFhw52bS+84ECj94bAE8HN796ZRKQhbdF92MfQaBbEVPF\navGaYISMrxbA2S7SvAIAU19AG2ZQynv0e+b5Qjhouf+1XAqncv40aVycnCEefsekCLUDB/thbO/V\n0+FxW7Sh3UMxkiXjzZq0bSPjMgVZVn0aKC6sDPyb8J6m3UJdCp3ZWqqsr64aFeAy+QBfzNHnT1Y3\n+TaxubKmZifd48UpfjxnaKRTwpljpyr4wk4Ggi3hMd+TRu1aocfbicJxNw0fkzGCpWeqbCOi6Ptr\nOX0dT5WYeBwnSLxwb+nN5+TTPgqTw4lP/tjwTH+kdSXI5PKcEKc/xEByUJGGhDJ9ta4x01A1FQJd\nWrX4U1AeMemO6YUG3z89qTv7iUogrAHHVZ9FBCfoByKlqWaQEB6ZYR1Rt7rOVf1mpvDDgsjqHfpd\nBPU5H88z9hKFlUbSWRz5HC3GDdDYF/fwkLTXspy+VrKNXJ+MVRTCyeDlouO4c2xLsBFXQXHsfKLW\n919+JIMicbp4fH4/l0Sew+x8uueBRbphrmdmYPeSuTxSkUiBZDy0/ySevsDL46D/iwerdRLrLekx\nGK4icfdBcikn6iCwPrEVeYbFQfb8U5ddinq6xL38rxHWUOt6wXVCJUbfGBdEuouh8dJRUDQUN32G\n3zH/Lt9kAp2WaypJG7XvLOJ41AnuctB6TtCGxqPpSZqHVyqDWAHPAOToZNdexkN+OEURseiTKZWm\nvwxJv4+tHb5otBUBZRbpjFB8TlRiQsogkllssPlmiKyuowxc2j5FI79ObJiQs2IR2eHRZwLxJX+p\nLp1fMTyb0rF/amW3SPafbH9I/e46YBQHNU7aIK47dgZ1cUxDPlvvx+yacQWY3v1fRJrHNDqKvRQj\nP7o9PObsI8BlHOIhVeAw20HbF5LuFABIaEK0E1CChk6HCuCGbuVF0CoM8nwxNZv8fkWOXas4eg3d\nc08Jwpzu8K27Kfnf/xYCjObMAvv/oFnMApFYpoG1CK7B9csxXgiIS065y01qhDm0tYMFrW/skekG\n2QfCIroEboVuYSOuG4dVUkTXiSKN5843fCyynkCp0+U8BlH7E4j9GIj9iafKWL/rCVEM6aE4QcNr\nHSXgXXcmj8YALRJSv0hyQj7GgWl9rYfUKAUbJWN/wXUXWcEE235umHV8my1+6Ng5QxDVYH8MNpKA\nw6stI7j59mBzdlO20aWhdZw8IMukgmp/fXVBluWxo1PQF4RwtsPKq1Et+Q97PmOy+CTfAfIalMp/\nenM1rIZAzAbw0q/bQrGr0iWK5r2hXPJxHy0hENNqPOmwlzdcs70VssW15hSiySgR69u0s+gX2NZg\nwPgUKUtCE4uq19l1E/XKgNCuJ9Y/07uXXhZxwCwPQlLR4NUp7IIw/27iIyrw43FOUFT7BECHLAZn\n51sp7quH+oIW010ozyNRjfeUxXpdJ6nCGtSS9wChPG/J/KPvzC6l3Rqi6TP8jE1vfVlF83QeZeV6\nWo58DWRpHiidgKgq6GOJZ+XCYrsp0t9wUcbOmf/DIxonX/LGS2Y8lQeNXzXvSndiOt4eqIVgSCXt\nNHM9GcFg7WDmFhzD4NgbD73j9HODn9cf9/aYzdr8TSN7iVCudouSK4D5vbnB+66SQzoRUEMHvBMY\n68nj47dCQennrUcNCf2zIcsyT5z+ibBptquc1XdhpNmu/TiRL6kYp/pt2fYliyHt34vvc02ieF/b\n3p4VXh5r+ADgpEhaqESjQfQOPNmDtOTolHAsaQMqTcy4S7ICJTZWTEDKo9jn7gbr1uwRbVNx6aul\nqfpXeFwa5V28q1mc5HtryB0xBEBjO73Ry8K8Y/15x5C+38nFAebHCIfO8YnsZE5gxX77q7zbTVmt\nnkK1jVxme8MAPo/9iN0KOcGaiMzANOPLaUztcg6M7bad0zyONuZEExv616oOA18P0lek6moUmJ0e\n8gixWc5H3e/3iDedJmmMNZW/sGwOw0UYulHx3lliRDoolX0Qt3xyr4HoaswQukvaljOYY5UUPYYd\nT7hmnDtZ5+Jcok4o2RTX37CXkuROTRt6fS/iE9OlL1v6eL1DUZXzGtnQbQzXI+kFypbLygONmgS+\nraS53yWrLWY4GfM4pam2+RJRVlQBg9uOzln5EWcPyw/4BM3+RshErmNUul4e0rtBCEfzTwZNDlI7\n8OPWXsP/i2JBa350fJtEL0B68KvuSQNMaknJaorFX/Itbgxp/l6QU6CJBP/bWNhdg0B5JqsaV7M1\nGppWWV+u0pWsN7MecF5HZMKqdhNr4t+R9ym6iBzd5IITFkxc/GIQktUiX69Xex2rs0DqfEmYRz1h\ni0ghB0nRRXTlq82PbND2BOHYUlzEHMZv/fRzlBnzfF6h6bVtgBBhPq0tYYEDiq1VC3G16VsGwIHp\nNWGwTnvvdXZ91vsNwbSv4Ftffw2wsiAY2yVjWtl0SUXm2U7yQd+iluiXmyAY13Br2es7pUFxkrLT\n5yyY+eul4ayOi0aMDaQawGsDXTXlmnWEltb2A5NGk0v6hJVB5hOcgNDCSnE42kN8lI7odJ9+TSw7\n6DwHl05hOe/WyocIDRW/5nQH96Ar0n+xmmYJyoQJKOR/hGXRxJBTuOvcGXANnfImSiEouR+bn+O6\nlmJDOBB4T1LfPsZQSjLCef0M3QODYO4W1xwRcJLx7d3JKEww+8gCillzUvfMPh5b2d9i6Zw5drbV\nK4l39aVXK+XR4KYs36UC5FXJXulV++T9Xq5ArQTA/mvFstNnjgqwSltDHLHgt4872PkAsp5g7+Rx\nI5VEx7VmKWF1DDwwtP7vnWfaSjlnTd9fdxb9mpsogBTc8w7m4LKX/40/vbQQu2hrUSVwNNWJVbAs\nqbxvMReLLkaCJC8paHSOwpNcbFesEOmzy/YF1jMZlWgcSb+GNPMXHqAEqkNAq2nrxQGG6tSkTvhi\ndMYAVtEbkAo8FprTOlPkmACVoheittPJ8IFC/IC9E9OIz+9AnIFAXgL+ocfWFy7w88UiHknczxcv\nvdoN6M3sWqyfnvJsb2Dyy/5UJRdYQrxg3DCcu2EZus3+zDw6P/y/15Ko8Cm25/sYe7g0JTaZY25E\nXbU2ls8dR1UxKYcBt0eTuBZjmJQhlQ5zcExHn+bNmtncLgEUut/h2IS8758EOvCsNlLQ2SMdXQ0f\nsX6yYGwUBhE8Lv+RZM4Mt8bMkTBFmOKFz6Qvdn3AlEvtqS017Bp/m+qOnnLZnthFRTp/bUgwcJf4\nKjLNVdByxyidQcCt58fPdSLU0L9iDFHaiyQql/UpdKDklziUi+m3/wIVA8phPM05m60GCl3CsoJJ\n9ta6zHVCGmSDAj2n4UiaWcYTdFlRRK9TUBSX6SR+aQJnQOvptHgbmOV1zyb2s2dlwReguzh2fLKT\n0DVDN7gsln37H89ncwcAZfgHRtVOsLRqxL8j7XqG7p08ae52W04CzHDg+r/0n7PuxFgkEY+gg8TZ\nf4wjhHksUjewgU2yaWwLSI0Ua55zuGnjIidwdBJhgdrAmJyfjXnY7esguYV79WxruX6kWNnkemRN\ni/TWWEz/lQTxwcB8JWiT/pQ5VWAE5+19DrO4feixlcmUTlaLtuzKIJ8P4hEwxuFTECxv9Xu+gruw\n/Rn3+AlGrKvFetS4fBK6KJ+NIb0bjhCumHk0t0SFFQwgBCtlELoc0vvsXWUDG9HHtKTIX+S1Oa4S\nzJVFDRTF215DfAIrhzxq3K3y/6DMDPURs4SuW+98/jwegwOH7ka4Z8uODnVOPjWnA1NLPn+bqsQx\nlYIKOptx4M09BqSpJJrmnaQXQZjWA/Afqs4WwpUEgFo+1RNACXIlIVyGQl2yAITmbiCqbk03650h\nFiq9AYH8STFF2W1cXZ9XxX1PGADjtCWp5Ci1pXg60UFOSWrGHMxELVAQDwJjb6WoMHOTcxQScmVz\n26UgHzQEf6HbhyQMCZRp5zfTsqAym+w9OrHsfH/e/EdjLJ2wi2fO4TAloIU65VA/OEEWFoYB8hyf\nlj3RQepiJ0qI5NPacazneEvNKVoqicyyBb6axd/+gvzTwbyHv0H6zTIOwgXgrf6ku44sW0cw7z/a\nhXNdvAbX0JwTWT5NV+6vaVv2bB1ob9yQdCM/sa5inpe719Gf/ConDM2baMV+/3XnOIALI5xHyCyV\nft7djjktp+kbUDRRDMDUpF1p2k2+O57mLFmidPTIIGWVRzkgbfCt+RapeRTkPU+NI/oecbFmoTNH\n9dEyo14ETWzqfzToBCQankkMgXKKL2NRJuE8rczNRdrsG6WkMK3VfzkRrojUuLaDz1yfAR7/eQnN\nW7KNRxDZUi9YItcPxra1P7XqAMgclFOb3xgKiLwEX9xlSh8WvB7IMe260DnnV27Vc/Rz0lafnJ+C\ntag1Q63xBX1rX0lBcG1fExR3RgELbjB/rGnjeSl8oXq4Nz5nT9NRuCh2cxRvs/FDZ5qvnW9siqve\n2ZJlwVlmzWeCQp/UjmofWX6JDyinOkprJGF+dWU5j/RggfHtqnf9aEGEzPJtnZqMzH291KFkY2RH\n3GcmCtwEkCdhSFw1N+TnOymEVLjI4GVog2wQVHpM8jaINqr8McAKwHsoxl6J7eaVZ+2ftiEuFFHZ\nNtyc5fmBWYs/EZ0y5ioYNzX/LvD257mmYHvSWnPd4Znpmfs/Xxz4OWgc5XciL6HZllR+sevY165r\nE2S7ZI0j97sLA3ffkC7m6DWLMC+4qje5Fr7wCQU/XM7B9Dm16AWUcxbqX4YoRVMxrzwYS51yrl0H\nnBpbfJC1UETjHOHn6yc21opRq5JYiMZW8SEb4J69odFKg0L1tvOAIdzr/m62AwUBarRp9LZ41Hj3\nWHfov90lifyngyQlhHaJs7mQSv/fSmX8D82tr+hB71sy1j44A3dSnqldTn1B2KL/tb+T583xi2Mu\na2SKFr0F7ZuvMo+jB0/57YKdIi/wdbPqsXVQa2YWleMFjhTzZxhHeVztYra9Y+HEptMdgDFxi579\nCLFoTeAFwlHFz77yHCdZ219B6+7TydsOr1eNApS6VdHpNT2eD+PI58er5WOpYig0n+PYAq6G1g5N\nNZejsqf8EVafzUieYrXD3hHIRxOCLl76JdIR1Hx8PC7V7UBUfyI2ZATgzEODyyELuUpUsm/5NBkO\neFfWZJzepvojby999EvgZvkgZNjIUmhRj+Z8BCmFjxulsaKC9Am7LKnWycIg+vjN46iTNCcGIA8j\nr/QQIB3UlLkDmopL3RyrNet9PmxuzAQIldfM2sIMDOp74ePCpIjTTrRR9F+Ana46nOIiaLhZMzBo\n4ORL3jYW/GHLKu1/dzGFJSR1XGe3zMYjQKWe1TjH55lB0nDlOoBNMxe0lPVzyR046VmwPvqa5Map\nfRs/OZJKJ3wLCmyCgMeBBmFN0rZaQrAx7u5FMB4jqFDXMFqtyFqwWSq4fiEMtF4TpmRQjguZGRIy\nxDM/IRYj87ovIgvHMyV6cm/4Ug+YXLs+f4j4yzXQdj+5/gotiH/9vJaVqivH3jaM9wbZIYLwhFLy\n0PeXZGkC6IqWfutG/EVwcEVywbg+P4thk9nXwIOd3pNEVm5Oree5aTRGktDk8cLeEK8ghqxmve/H\nxfDy6niCPRcnetRWjqXNthq/yoKdjFVzTQ1tZJ39rRQIN2aeokaKA+bq3ssZj+iErT9APeC2lDLH\n+Ww0PCu4F9V0eGZ9QXkUHFmHJGbm3Gl2tteio0R21aTACl4RezdlPqmJ3meXenFSLQ40tjjCksJb\nFhl0MaZrJ5/9R89Od06MI/Sv+n1OkSRpRR4iGkuC8R6jXzJ19dV0fgbejsJsb4RC35O+QYY+7+XD\n2WEh8neRXhXTBa7e9qo6MGGu7/wkm/kjY7EL4JDLMjNaWCprvXS168/b3hnfeYCxz8cESURoQpNA\nNLGrG4ozcluivvRtdzF8lHkm4ZfKnoCJfk2eK0A1hiamd0lB7udV+6mYRq2vn7tnpDLKYPmolZd3\nPClcT2C+2RSH/3pS0dU+xqX1oVqZCAw5Looj4V/xU/h0zH29GeS8FxNMMRIO6KLpz3iKRpPZzx+u\npTvyH4OGU2Qd1dFmE4tvKuPNN6f1zidcS+KPdQXj8sW15m4u8Lv8i5wLu5yKtt1Nun8w30r36T1q\nCPZwvQ078p4GAjLijGEm1f+BZCU0GwoQnx2VvgXVqgC5DKe4zzy9sD0xNGWfcOe8j4q15V0WXcAi\nx+nV04xPmz9cRqfWDs84DdkHs51hJF2LnyiUa9+e3vA/PtbdL6SUZt0P/9rwQUL931ryJK8R9IKK\nXqZyxvLgOeFHVw9JmB9VRC0N/fGxFO40YJHzuJGvfTFs8KRAFYYyAwLrZ+IT29/qjBZe58i/6ORm\nX1fjg4hGZDiHVZE1aego9Nt1Q1sgOp2l4ZqHAjJB5vPRzoyPGRZSCjnOFp4RVrGe+7WU0/X+AnV1\nUTMJxS88tKC4qRK2M8rhhUbBmL/5wV0KcFWWxBnce1GAfzYmGtItkvo+0T4sj76FLaCe9WPr4je0\natVaTutrKPZHRbNIhD2ApfPk9wbWhsr/2DQS3Z/zQjT+k95pzD+Cjf52LJKmOuHbr8Y9yHmp26yM\nzbJmEfP7cJu69inDwwy4lILavEWvEuYI/CLLuGz/koLY0wMl54ThtgPslxjqRHbGbaqwonkAvk35\nC2tc1q+gWjCau9FVdnN+cp29l7rShXD0ynr+CSV/ssGoCxaif95jCwRYRrI2mUIKzZ3h+hZEKQOG\nuI0eW4Emf4o7dremMINY2YbQb70027H0mDfaJFca3pTDh2mKfw8MyiGsxjSBa8dIC2XwF1+CROj0\n0iAXG9HTniDqQxWfQMJoLY5Ow/+tFWuWqdgrvK5GP2lMXF9xEXtxOakfoxhM4v3wB1f004bQVrrj\nZzuiowdpAYJ8Pbp2nF4sCOeRYyed1N21e66XRXATfnPd41V/aApl86jGquhMI49IvDp28haxNNrr\nWbJLvP6x8/UT3fjQYiIcnYhJh+EF6HbQA78w2j6E0bGjXznxTe0KKRC9jBn3TMVHAQpr+5dZgav6\n7JFyjO3DCh9gsE6WL0Q5EC63MdgQXxAmNVol5ARnT8Vg1bPZgeM8iGSBJbD+kP/o3tlwhbIFnnQr\ncLPgY9+PUI4rehP1EY9Bcr9j100UV3RfYq2yaUiF8sf/mKjdZm82D6sOn4oRThUzKb6CjpHShZws\nMSN38IDqWpXDOSTonFeN0DQligjJPaU7Ep6NLzym/RqtChzyf4uVuZIGl1YP76RuDwowng9J2y55\n8nFfLGkNGw0GJZreWdBxdsBzK6FrNd8pyAXWXna82EcRu7HmpMkGVXes7H42ty51HVOl4C37xPDD\naJKSfbfHI6610lrAw5jbs6x2N2ROn3vcuKHxvj3+VZOSV29Nwq5Db59Yqda/I+UNk4ZaHTejDSVO\nOYrYPC7XOTuJ3vSr2BwI9bkp3Z/89O5VMuPU7GTJhqy1vZFt2ED2d0GTHNThPCqJ1v8ELzDIISUy\nAKQYy+XcFsYZXzPfBN7R/yolbd2PU7zVChoW8vvSldnSYghaQpH9Y2hG86uM64bjqkrPukgWpJTN\nArmSv3ofrHMGtuXCDpGAtLjWlYksnf6szzvhSrGzVSvVBN85Y+3w6XZOV28B4cOanKcjKsQaZQdS\nsilardWJsOqraoeLbbk57+YXaISP1hCqk5+NheFbKdX3MRNSOk5KkJlcggMswjSCGM+BJpmjJ9yp\nhM0mWEVQfpWVWPJfftm8jf9IeNbHioFW2QITa1KctOrVIzsgZw3J7hFmjwlW5KuljXZOvE25WPEK\nbfGJRwnOC2j7uGuCP3at0fsfimTQ+5OvGqqAsMbRaY28MtlGd4zJBI0HZFsG9ZCsYdGiPddlfoor\nLvpLvffT6Z8FcgHum8iSNztDbwqpuozlXKH6caZCKHdBOFBUQyxmA6/3GNZglJXKNd2vPW1ZOawq\niZjOMKqDfDoavkU6g3WxsxsJS+0Sh/Q5F8XYzYagjO7jCFtCoKl7XL5BOnrF9IwMiGkP2fiNDX4h\nwG7puming4KhiLp4r3WsR9+iUsqOpZoTPmhrYkF5LgiX9irJNz/YQlBrZS2Gk1mkZEKLasXUmTs2\nRyCcQANOqowitygDy0u99tre5j9eSNIXzzX6EagQJd+qsrv50hh++6wTWxDRavho9D9aVVl8XdGl\n+HU9F2v4L1E4HhbxL3tFwb5bHUnlcz8wOqsC/mqmWdi/SCZ0jaIG6jZdGPbQW1whZih7ynbOh4d1\naMAE348HZeAGEw4LQ4L5LWBhpKnAymTk4HdmqNBlK1veNUnQ0MVzU+SNasXIz+P8CpUznjagxTHu\n0N2zbIccoRk0UFjw9HG6GEOseQFC3i7iOG2fNSJ9CQwQV34RJVjRpKXTWJl/VKyGhPG1RlUEACx9\nLpUVCSrer+s/4iXrVwiIQlVTWIkMj087j2Aqa91UbtwDNRZG70m/8CwgGAP3eOGu/ABe36+GiMdh\nqFK22BwcE3UGZYUj1BrjLmddjhqDX8B8BqtdhiYgidb9AekdrR6iT8SCU21D+86KsgscDKl2IhFD\ngKvgR00XgGdgEbsX2ZJprMMdFWEa9PhvIDjSSGcgnPLD2Q1+bOQ4j/IHIcuFuYHrvZBuuGuHwjDz\nxv09jgeeA6IYa3DIT4gxa6Cvb5emqYXSRFoj1CBH9T7HDjXR664y999OtkXIjPqtQNc4KqHiAnsN\n1IvhlDAAgqr3C28KfPAUXacUnVtsxud4YfXZuX0Y3JDQAf4cnCeUveq6aa98moi1cDVX5V6NHVmw\n00L6SKy9CgPWa1LJEwPUmXq8XlFe5ApxupliU3HVu4cATMHmUiciQW4imTF8r3YTXAtE8YDId1Oe\nJz/d+7P6CDHBK90hvdwQ0VFx/mxkTrd14+RBCbW0UWDuBRNMcNc1X9PK/WqYQTJAcowQta5A6GGI\n+D1QxsMihRglobsIupLZ+pva6iEWALfrf3TZparJryHeotacj/845z2/nuTPHcK77Fbp0LbsbBmu\nQRReptbv5zR6sWBTEciRgcZ1Nch1+Fwjlsi9KfPjqAzakbpPokOiNYB8vXBiD+UnQw3uPDrCOJ94\n7ordiFAczuszq08lD9qre7FH4N0Hlkg7xFvh6S+ceKgJnML891mdChy7ccU3DSHgEffBD9bAQsaW\nX7UtNN630m2xfPaBUIiglvYn2ZM6D3dZDWBLSyQo4TvHGtOSfysuz8p1UULQlMssfDBNxj6wmxsa\nrNhbqS6TeqDJYZIR5r7+sMxqxN1ikhHLVzjSiHyusZzG+ixxZg2/fuQi3LpWwz7JHLLwto0tWlxW\npmDS2vn080DPNabn5S6R3yDgZzUC+MQSH0Sj0GvqzPaN77bQnVdMWVQfIjO5utnFrBqmzuZxoGCM\n5FTiBxdnu/jSYUbAAPCpxRRk0jZnJ17jlz/urCWy7OYKEI/kbzRFskHHv4i1A35lOH4B2Rrs6Mt1\nklKl/k0xg9AhSS/K8gXWaQGKIbCp54+Eti7pNxUHdnHZeIlQyqlUrB5vlHI4LAhNnOT2Y+JoM9Z8\nOxw4poUXLaURLmFS2GYZnbVyCvtJwdBhYr4fuHaEV2Qw4ZJR468827wxhZfWj20HmY5RXB2wilgN\nGwC+dg0AHxfqh8tngBheZujA8fPxYBMFQ4/gxUh8uTdYtyCVyxtFZcC3gfuP/GtTqgYVDWYdy/hD\nJidnTz9DZ9KHwp2KnEEQR3ux5YgYmTQwiM9ob1mSirWm4vXCOPc5d4KmOvAlnuQFzAjPV1qahyGs\nSvKiOGfwWWzqZQ6pnJB4HsVhHs3kpipQ/YT0a5KbCd0Fz4ZE4fGiFC+fGIYXg9MwbZImHF7yMKm2\n/Cu5Hb9uoo5VBcckpKfr/bn7R6oUIU+stYOBCHQlVLQGKxxSch/47TJXxnInUg4O51i6hMs4NkL4\n1VA+93jsmPM1OFW/2jzGyiC4Y0AMIbv8Uwun6p7lBOJm1MbvDqGyTYE1SI5iBqUBAvR6YCwaZZkX\noGXe/IdHFsCnbzm5bZlj/qflqao/myr5wA+WcyJgqm40tah6CULFT0IEI1PKjM3uLxX9VpkCKGVh\nc1QUWWVXk+uhjrKkXgJvwrkYNauthB/8t3Xg540hQxCXzYig5kArs6oGM5PAfKWwN0b1uZ2RD6Am\niDGt7xrbJUSHp3MzgG73TBbR1DK715a8pshKt5DmOXFcjyWzuFmI/InIJW8+bjT6dKIIjg8F3cg6\nav0oKe7fbWerz1v9iipZ/MflRAty8Kq5p+gsQBmi6MC+ys8Mp6X//Sk3XGdWr5M7d1uymZ6NTp2h\n7+nj6960gM4qOKjGvGIHkKXma2LOU6c/RcRDjFKzbmPtGfs2nMS8w3+IbRv3IGnydz89OfgylcNk\nkikIXE/MPDBy1Tbp185pai9avh8BHzebm7OMxMneUUa9hvscv9eIZ4hlnTOvdic8INt5ZHKxRkek\nsa8mAOVMIEWpxDq5owpon3iABhJLdgc7pW0AvpJp0U3cpwNBjkcDlgCytkLy/NrrO4kdkoWjgq+I\nwxoSLZ+eSPmRupyfUfBgOKFhupvxtphUUrh3JoiS67YoaFDoO+U85IjB7L9yO44QxwFbo3HDpG9I\noCa7q9tq9l3Xc1eWK3VVXeIJC0T8mBOxJP16ldnArO0+2XEk9TSCQVH86fZSJrnfL0XLc68R0kz+\nd56VngUWfl6Z0+e3VJeZoGm8rfS6+ov3yWgMwoaCE/qnNRp4shEIx3eM6URt/q4rTzF2Qhi4fpTw\n42gcxhACCqRIbF3S4OmeAUJJDRW1tUYTA6340TfY3KmPdU4XeX4RBqgvm9giZ9JEAQ6Bs0rVCHpy\nsJw7BRsCcVg54QxaHeMsRdLtmz7rSHRLTFtYkeNDmflwGtZ/XPiTP4+equi2+xRjsOyDR2NRfE5z\n4IoGu9ftJHb2eU7N4Qk/hplK61VAZdCYigQ04GgQIed+uFB2l57CSkFZzBnvbpFFZhtak6Wy2yy7\nDltAPhNdrxOs8AywkzVFnoN6kK9Gwy42yDxbLsTOGR1dHYH/n4Kk+8jr/ib2U9ht9ozi2t2QV7MX\nwthuJgTRxSb959MkE3ti3zYd4zRDgjVuxRG/kjyqYK+xzY/RsK24HW7Bzlu/2c5aR7HFyoKzRF5v\nu5cLsRe2nEvUopps9UDiO6vybMIlWvfrmmjXc15I7CWUzPr7dA6ceAtg1XR4IWDdo/dAMxQ8B7C4\nbTml8m40P/WnpAzB5/tup8ZnZxByM+g5T3oAD4hJIkLaEZBPNHRz8AjT2QXfsapfS2De2EfRMr63\nVQFDIljxKUGdwz7Ko0KUWXspqvTYLYDDYb23njMyxRwQeOIXUIP1CHagj5t0OvcCyuihPXvvuyJ9\nvC6iO441E3RBmjnkPPZllVZyrkrjBKENRqyVsNdDIKWHzfp3H93w7wgBykG152OF1ID2OCKy41I9\n/P9Z7X131Z4uBCZ3/Y1eO9pDdHIJEVVZdFviBEUMkc89cMX04MvQKDXI7zU7xIdWLyywvVxEBLUR\nUOkOHhBOiA1+C7giXsWrcK2vUJOTJe097N7axQClzRdY1SM8DBA2MN8eOfTZiQBJTQBFD/i0eOiV\nO+PgsdEnzGE6tfS/nWA/+IsMMrPbHH8KVlHe82Mn5WEZ08VTOjCnqmPdPpbbw/agzWZS2Jxn37Iy\neh4ovdNnxKX1H5jOemP0yr69uM3gZk3wcbutn4thzUUg/wzC4rtksLwg2MOuYmMQkvwMh/ZyfFnN\n8yi8zkXA9dsmHg6Pa3/1/AnwfyY+6w2Jrwu7Ha9PdzcajruwJJ//ak+H+08zmPJqvTEW5edEwJe9\nZ/AyfWqV1VDl8h6yVacBg62cQbNb+YI5fLwZ/HzEb3zWsxsB+jsBhsNmGOC8GScF2yAzYcy2jdUb\nyNdZ0uygrzlWhocRB3rr+KpdnB7nr8SgM4S3N0JwmrBYXzJgyVR7phZMQHMCB+wopPzNKXmp5uWO\n4v/uFZVG3nbpwElh3+hjEmNMTcTAa0fxU9Vr2wx73FdLiTuumhcNmcRv+HUdEAq9s+7MvsKmNoHk\ne2xU3JhR+KjGkP9b+56L+Ql3BqNT12W0mNwiRNwOtO3bnvaqyMixDUTw5ptWpHyYahgyDHAoO8mv\n5wDbLvjkyiiSpz4ISk96l7kbANVXSfEdHosJaSlTJg5iwHbrbWEv7CgM/uYkKqdbW61ITkJlVJxz\n53psCt6/bq/9pjOg+Fmc66jakrvRCxS0ux9XR5WHotKcEoAbX6yu2rehNNVjOSUEEFdiRpLpO7+1\ndtMGivTIfrZHOxCqTZN7f+iBvln80H0U/LPW5anClyxWJIsz2+8+/56KoyN/c3kC2UmOLfhlSB3u\nD2RItY7KJt/yK2rhILgcaUFn9mAneL+LE3xMEQWF4it2fm4kUGg6rrd0Ew1JM8fTMv3d+6IS1KwT\nMQZnKEIZsweeSCJekMIWoSaDzDGXZzx8S4srp/P75SH98mmxww4+pnI6okBIL1JaYwAsxDF/PxST\n8XVyQ/x8YFWQhFSqkK92Hg/UkD5Yl2KUkkPzJKw/QCmiBuE2w1FQ+nQyXSoD/cNQwMFGl7Q8E41n\n8SFB8L5FX3/TSqyCoOcvIaUA3ZRDHFiBOb2fuI45xxMrMNfQ5LMfZPXPQwN5C2lKWlcBa5FvZHBz\nVBpM+gOk10kZK9ulzGz+WDs3JG2UohLW1gK4uZPspBEPMMIvP3E6jaPVvrJCv8ql+pPX0p35WKRN\nsdgNELkbeza/UuithHMnx/mGXRwgcuRvLm2zZ53FiGlsxF0RsEFHhm2BSeTGUao+nmsR5ME0SJol\nhHLXeMgf8QbZ2RgdfdZZyrFEzZnS3abF9iui3tP8qnyf69lCwbKJPnlkbJsWnEStHdQIOWfThoFA\nra2xrXUcWns03zqQ4IbillAhLb5sHnh45d3J2zSGVdkFeA0cqs+YkDIT8VE1hL0vii6gCeVKeITM\nHPgAPFuhULDP63hdprko/njNUSUjSp/fESHVacWcBhtvyofHXB/Vk0uOOaDXhZWxeH9ZM+EHpzvV\ngHyW/cNsfEEOFW5WZpM5KMnDvD+hvI4LuXjemCLFEKmnHMO7h3pqC+G4hpZQ7mUbQDJ4uUpebOcn\nwu30QbKkpW1rZM0UCzw6n+OAceIP6rl8Do3A4GLlVB5XHWyAywjT4g0CHf7mtnsKkGoPpA/+pUOp\nF6i3JTnuGHfvhpjMV7CzOv1HAWBoooyVx33sthEzRfKpSjbRO3p/E7Xv+zKNzzu4QgTru4gqfP+S\nlpa0kwdT9YDCLjbc9l3vF1G5uZPSeEJB/FzSAecpbsIsLZyeiVQasf3MHf/v2NncNcelr2TUabKy\njM4IoDmAoHZLqaS/DSKH/cMGhySAF5QXoDOjD6BBEpnBuIHsRz5D0cDNA8kseDGrH2ledUhAdKqt\nIu1sOHjyCgpj5iddkpbPWgd2h3VyCRARy6Y90mKTY8jzuAp+uj7RXciPnNVei71oN1rK7Bh3oCoL\nOsCicA11krbUiC42tliG0BnlwuwdmFbIdBlw3ctN3D4fDwivxOhOfCTCwuX0Htn5jCAlD3v5yGj1\n0xPOD8keGetPmFUAPmxIf4b8D115oZlSvcOPAjzn01vnb9GeDNK9L88kDKi6PRSdIxaLegDoZ895\nA7TmaSzIzMGRq8hQYxk1lDQtX6fosJIcR+NbHbdAkIKsQBwMd0YjvWTNFVcOdjpeNTgvjukaBdF4\nYUmYVNpamDI5oJKJhiOilck2YvVY8bihBoBe23f0xZ47SPa6zKsCG7VhGXrzs+KRxYQVc3Lysfq3\nST8ZiL/f7rHaySCf3Peew6wDEVD5xQx/5sXNF2pZ23v4U77melxj1L359/rJ4HDd+Ofe1p48kgbf\n3uyCAN3S1XgJ5MI5VKGa+3cJk5OwbgSUO6SGISo4KsfAivueoqMqOOG/j7Qqa8HnYvWPUmttU3C1\nE8ZGLOsRgVJY/dhHQFqfMUjZTreuQP1UsnIE2bq9H+25wwX9N8p8LQZvoCpQoKyPMTKE/zeW2YHE\nml3URHxkOTV4u7CZaTFWR50UvaLqBGiesNiLFhHtBv6n7I7bb7RSHhiVcP0ByNFwDVoSXWhw37+5\ngGc47NggblYoDDsqcX0PBQGNKrAadQJigU/QB4k5PfWiu2mumFL9s/GLDQY+vHlTyK8hHXt7CCG8\nmot/JpHOBGcoFsZzmzgg+tCvoP8iG28TDL7U41XhAYvm4WvLQFoD2y0L48v6JpWR2TFVuaEqqmV6\nYI4yvFhO84ap7Q5IxiuL1dkZs0w+Pa3cwwYMLaAzo3UA+InqOIfydUXMn/krnfRF/y90p1e6KLaU\nEvx/R8w+r2PPtwI/4HaKnZNpApMMWqP5EzrgzV8SKyFg00AIo/xkxgYpmTn0xo/3h56aP0gextPx\nl81YPN5ScimdkFxx9QhAnhrsYN+lFUh5I1A8fsm+YEapaSq5/L9nyvSjG29m5nrJU4WfJJXH6EsI\nqd7N7U+hSQdoeyPcyc+p26DGZAEooMIeg3iag5LzStZYvOiOS32ufnx4L1YUfrRrywO1sFfuHosL\nat4/muTKfWE7jY1xDZDZ6lJfBYhPoO4gwwB+dFInR3aB80ovZmybN8yscojapEOrrgCDKVWBfAaP\nzCayq6e8hHn+HUWlxi2GcdAvQ6afetCIsd0j6P6OclnR9ic/OFgGmmWUn3ef4Nn6aVDxi6ct/RNb\nJzV+KJ97aZ4nICHJ3NfcwQHbwOA1bVAJbAtev8H3mfRKjUwKH3AjAdiyHoHCG2iO9t8iLX3tWWsG\nVKEPiugguniFrlfjwmzjJThda7IM0L6pKaofEKZabHigqU4ziKV30/lMBnai65hLpsyE501Zkq5W\nxCuLQk+ZVOp1YqDWuPTRZe7Gr8qS8fx/dZqnDplPr6rNCLqUh3wJ2pR7emKyFmcYrqSiXjeRLXCx\n1PgDtHzd/3ncM2wFs0dlMDUiobmsfB/eX7C73O+U1ecXWPltxTKD0M+w8OKYwvsu2Ob7xNo6Rnjv\nSNf8naXNNL3jzPLnS8OEkrMCWwwri7vBBfZJCStQoqRRMt2S+PEOdJp+JAq9isj3UvPjGqIUwJP2\noQhniF1LUhC9JiWeoveA2ExDkWe3LP0smbH7Y0g1H23KPSoT9uUNX9icoVYwapjws0v30ieLZ9KY\nh8BydOhgWDPzDw0UxLhQlRHena2hN5mRY2fsaPLoeVUJqI2hcHGTdEhySjRaxVefYhFQJQ/0TKDQ\n7OsoOFyADeFdE5y4ILzOxXLh6V7xGJRvnvoWdid1uCTarDQpVhXLuMca4LXL2VKloYKcAGSkFIsb\n+xjmnQUDrD9y85z0oCN90n9tGcM3ps8GRjVsWGoAixUNseV6tkp9v7+2NVJujBFXbvTmLcCDuWOK\n1UM6odSIC1ZjkmSy5MB/A87Xg00h3PhfT6s95lZCc/1ZR3ohK4pyTwv+2urj2Mj7+DKGZGLBqQVf\nZShzn7g4ywLHJp8J6mgc3k5nWXn+9Agi/tFLWhpCAqzAsjVuV+6157seEHIxFTPG6X9UK0tX3cld\n1vM43wXJn2gr7DxMWPQHTDpcEFXn5BGit4BBGNa5hY8l8vMg2vUy118Ke5+47Us9O0mZBYsvguH/\n5cyP28Enh8O7YsaLWmEaSq/8shMZq1SSslwFsed4ZhTbobFeid6PPvbqswnwEuuMBW+NHbEYs5BF\nJjavY93RaTuNAtb0RBmjnKjCNmDA+Np9W19bJ8IvYKWwOfUmT9SDmMB3X7VEX/FnSAdxS1Y4gQtm\n3De845avK8se6mtr5MgysRmRCFaue7J1dH3+r58XvzfOwQBaMwHsiwVMkm+Dqd/Becw4XKz7ZXHK\nJoeg+erAR0vhKOaK08chHHr3JYxXuWYON4SHSGLtRjPkboPCyKYp24/IFodUEtFEFQD/iy2gCeqQ\nL0+x98c/AUbYejyMN6jyBIL0CkUMkGDPQCLR3E3IbT5XU9ja5BVfL97Ufz7+qc8akkQJiRvI6/aB\nuP+2hizoMFhJrWtxEdIb/4VVpQiPdiJls/sv591HL2nhq5xsinZJkO15+c6Kni/zTKkXZG+0pmTO\nnwEa67OFewmcIWaNNnFWX9YBZMxKQ6muPCS0LcaRZlRXsScmViQnKAayiFv7RJD+WvaX+cSHUvMt\ntquH/hUbnxPKOv+MK8p+bXH4XWlvk4i3Kl6V33NLZdQsT5Fq3pYjfM6myCOMQhr+YDrUmILRBeaJ\n7W9UZQ028gGe0nU3/nPylLFl7MNHWzCVvk5NThP79Ik4tLNscReFnpo5Bj/wBp40Dv1dGsUgc/tP\nTTmRfCNB88NL0XOpg03V6npzJDlTWkhS1amkp5OE4LIU9jKc6iDxTgTr10uf6KHPebQEV9YRBcs8\nIWljsGVGWGrmsQ0jdLynWSRt8MMBsOurXxdoru0gEENyvlJouOl1GUyZjhF5/qPWWZcVxVBB45t3\nIPf919j0tmQ2qYA7z/Gj09l52LhZDBAHgrFA8AxMkmkD8McWILk3aeAqH/6p2FCPV+M7ZGzvRmwB\nsepRf6hTyVpZT8Gt7oRO58JOs1XrkupTzJCpWE9erfDkd0jQF/kflFqU2XbQesttZMXWQTHMb3oy\nwpotbfL6ExLhAVBk6NIcXmmVteQpaZRDne7ZoU7kLWX4wZ16NuPZJVoTMtEaAmqkDZPyT9Yi3TF4\n0TczSi0MkWmPV/CbWk1HHFgRy5caAf7BqndikEJC2EoUs+WamRc8/TlTqJVNVjfUNluJXbwC0NV9\nJvee9lqihjrC9i9DUG2Z4Y3ubsRbZxlaewBLqxJ4M0kQpKtN2TRV+ldSmJ8iIqTO/UVtzUyTh8HP\nd1J66AUFuvm6yIgDSuTxytm8XvqLTB+CMz9cKhCHmD4IbMTgmwcdPDGE2xSmo4fy8z82d/FhLGp2\nNfQmtyyJ1JoXlsEePwGmPgCFE9Xy2GQ29WKj7OwgWbzpkK9tGwVojJo8HuO/4rd8Mk0DMKcQSgNz\nnhVmxOX9UTCRpIcF9gpdBj3rw3w5T5VvHwihVf//NocJWMiSVKgvoZHxcYZ+jqLQNY6wSKSmoeYs\nuEziErT8OS5rLWAxM8gqerxdeBm6UL0Z6nLb0z0YOr+5gFH/IcBfjAK5Iey9L9nPAxi+O8gb59P7\nfFbJ2JSZWK1FD1t6AVbHzqs3AgbxCk5yRkWkV7aGKsEQRfyOlRe4Cf2g/5w5WtOzDLl311P5U05O\nHCx3EoeHNKfzRD2+9aIAoNHEfhOU07YKTJ92sBPgu63wo/krVhgdbynmhaVc36fJKhbapTY9WUMO\nRqrVcWdB05tNIKRCn/Xas6o79WhOonhNHyG07QdOUo6C9xL0/z/sCRsZJSX7fIVJqjG5K9fq1TAD\nTHaXSTP+ZXD8BESgYqYRwIYl1MIwXdBGUZ70hNDQBR9f6GuwUEUDEbf+RVkB3jspVBJngNStyxe3\ngs8Tgtm/kgZpXau9b8riMYARqNXbOYMpAoSKXwFp1Qeg6qWDe6EZeXsm1VNOwOz//4SYj7kjJI+V\nXOQgCRQ4jnUJ8suynYiwNSCw3EKX/9oPlerkrsM4Zl+O8oTD0MO9Koa9eU/tVNjK+6bGoXmmalXS\nVZMshTLvQrFyh6vlDgBTpFuaZkEloxc4qVsId9rQDTYVbFHhE4CoMPJwDw+0RzDsrnezrR6lGuwM\nGgxUDuYzG4TD1GFktTMzMmJARod3CkFGH6Y4MnEA2pOCjtarmqwuOaB2PunXUcm9Ikpvy4j2ip1N\nh269npZuV5LdAadHiGTd7ZrdjKUlqNkKBJMcTURqcfwXG2w7zKL0Zdx+z4QHH/tsD7g2YwToYcII\nX5yHiNZzURBlO6XfKTnu7Q1+0j6HmT+OnFCxjIfIfEPep92SPkmZvuGr0I4+KI5rnCSxcOxImVH3\nZsxPSHASMtuBpmhd9bVOt8SZ/58dK82tibUpYjR79apSYL5noRNv3SPjrTEMlq7efn2kDBs00yT+\nfkeB8UZz4+4/yDfPPoDeiltspB4VS6cwJbNMrmR+GvMWxdTeGR/JvjO3gRIwiB1jpfXPSKodZKo2\nAYfyGEKsUV+PfmyqE3fehWoIo5lNsBQ15K6W9vPo7ucy2ALTMR7rzxr93ZFEAtU9BXtn/67sFRw4\ntCsUWW+qxSM+XQoW3BBSpqAc3gGUsaKIv66MMNTnTHkKn8F/mOKsmnEZ6ipv0774/J1GPtVRBKKM\nUFbTUMTzY5nLEa7R+tueoAUcVpfs9LK9PqL5CZzPKRZhJuFNm0Re4PFQBLLBWPBBgnXakbBReOE6\nFeSoioQ7aeEubiPD6VKOjurCLlvqm2TduIEOSYjRNug9+5oMNN1ArRb3ehtoe4ZCDsfh2G5+S1qz\nPviKsPCJzWG7PT4OmH35HFsybP1NLWfAvVz+3eCwEUpYCVEEYG5UyinVuFO6tZXr2KNAiwMen6tG\nTsnWyNbarF6g+KtOE4BHrbdAqMFofu3ImMqs/JG4ZEUevcU4LyfZyFn4/Zx7Od8rOBoOyPkmwIoQ\nPgBrprqk5TPaDb2xRIkJmMrwQYqX6q6G94sOq7ETlEEqXG1ForDMeL2pmaW/riirBdLSHm+vvHrv\nkyV0dqbFgbGOBzzaF470AK2sqbAjYCuk1A+nbvx4Bu9pMBjz90t3SSHVl39oZGxy42eSfIqKdUdJ\nhHgLXiI0kOj+NwWcU0npKovHG1Iob8t7+zlj1RBvdceXYASdPbl2iZnfQnF+uVmrePEcwGMxfY5j\nr5Oe7hGkyNEJJhiRWdy3TDiqTkJCxViAGEELPHXSe2YswvcQaxszFx0GwQ6NhgeEsQIlstKhTsVR\nsPvqB93CHTfdfsWCcyeSUYp8sztUQtXyE4DLICR1606qQ5e7fZyeth+inoCS28TI/E/6PQw4GN3c\nI3UCnHfpnVC61Un7oEdeO0fIJUU2kE3ZghBTSqH5RvgbrvlCD1XnknzebXo+0Czqdxbvu4qar4JS\nLr4UrTem5z8+YeTsgh4aS6kxM8Os3350MCxiPbIXvWdtUpDGPd41R23L8q9tfV3Kz718TJBBqzn+\nUPThz2lWtbFh8ew+PsySf/mJ4BKbuzzpXZXSOil49ftq2Vj4pQ6Ul8J6ZaYpM4ai5WwsXRmfEsxo\nZf3k/IXIxrOzJ+OvoCD6mRy62kQFAcfj2tt2koM+UMX+zwUKE0vpi3h2hVMezpcExDNGAPlbK2Kc\nDDN50SRXK9DpmKDjYLqy5vlxls2ZnTe9ReqeKtLyJY12if8HZRRfOnqPplwHi2EtmsZ+2mcYLzRd\nRDrIqYx+MHUFUtEvFEravmQkh05F9ggFoMlz72t4hOdCwt06UHeWXkd01jNp/VIM9ux/bNxHPP7N\nc67XheO/2kd8yC2l4WCD7IXWqa2HJOXvCxkBGZKQc/NScPGUML50r9Xg8IF6JwAlKA9mpVMW0VxT\nWQ27UW82Y6gW12i4s4P6Wn96SA7rRUelBt/QVUXWDiN/Pn4h8QaXviVh6+MVoBcVAIdaI6ox3ay1\nLGwgg17UMmEuaKw1rZb91ncUkaxGZvhHD+wAQD6pawfSuSmzrHCvnLpwt+P/bUmSanXUANvNaAey\nMYkl1nVSsJjnqarFDzEwxbJIsXg6/p5X9UN5TYEjdU0SPL4OfzpGRO5p301kJ27GAai2cS0sd6Jk\nDBXx1G+GGuGKa7UFMwehNaDW+u+eRz1rOWbSmv20/wS/dSFFXUpc9ihVRmLDYOVC8AgGXnygLc0X\nGmrB3ZeSxvy4cOK0T9giJZFEbnU76uldlumJAKQz9f37A+4k0AdlGQVQYLO9OYOZ7NDzM8ISElOx\njA/qN6iA7QwzGOHnh0KIl4DIFU9iQcW5UvXnN8Fs19Djez+FPk+MQjCGhwv/EXi07PKa4OKhptTW\n3wvNRhXjfLpi8MBT8KX5JUS8jqRodU6720uCs1JED2rFY/bneMqKGxS0W+I4/hO4C5/RwM0K2kdK\na3S2llvymEzlUqa5UTVZoEB6iRwjb4QlCfSLlRHZ74K7np+LEXYlz/cZSuXeuVLZANk/TGo+1yGz\nB1id/wG/80AuEFVIwRPRjMFwaWunsTbdZzPAYf+IEiEnpz+Mg+EwIsf9QBvEbAiinn2NCi8KvJ/l\nWzBfND4SFlygGTFjBegzbuZpWjQgYEl+pYWRD7gHrDyalyzz13Lw2bcXwLdxKZR6eCLZrmJsIrwX\nYosSPdHnEQot249x8ua1CZ+9Tt9rY2FbL7X1ge9lCn9AQxcHWya02T2p53Fxurv8kYXmcFDsoKIw\n2DPAFHQKdMFYlvuib75JRtuZZOKNw2x8sTf0Hx7CfhOpdWkHjpZSbGuyG3768FlAYaoebXd17Tye\nzFsKrU0Y+EkNmxpH0SsEpyewJTjgV2SnyEAbseGf44EvcEGILQPqtez9RVm5DeKeCwpVoG78M4Db\nSLdUmZhAroU4NHl4EgAJzwtnR3ECMk6w+dTOEQfw91zX8bFdhMRDgLjYIMbzm9bwibBRUWREd1kV\n+n1e797f62BYrW1EkkJIWTBdpyktuAuV0hgsaWjRDTU1jSQU6QrVsFtCRU6pZ8fDW/VtEiVOB9BQ\nNRq0BqTDA8sp5AA2IK3+oHt/ne+rnFh2R7SfPGsUN08ZcRK9PiA9RNE9m/tUBRbL6TCNIAYJauDa\nu2yl932Rw7/15yp4RmB2NqHMZA9rFShIEwI95bUN3Ss1LdvAku4ECaVXiGjXmcvGLf2R5OFdaYgF\n6nKBO2u6zlnD4iPWUxztzxU069UaSA2OOSB/8f5704X74tstrGT8yuSEyFkOrZbTafEXHfpYnupF\nDRrSCtVK+/9CMTWJ3cZFuSHBFnPSyzctDD3hZ/zqWJ3JR0hIQufT/DryVFMlWB3+S7IeRkIFI6YA\n/H4zcwj/4CJZVdHnkG98SXYlwFfB+NPLQqfwsNgUsSeMox8Gls17IrDkLXZI5UJUf1dskADPAZ9C\ntuJs26G9H5XHFjZvjMYm/awsX9hXyMDf8tpiSD78rBbciRtuNw3T7OioyLuJfvgMaIJA5ZPyPGE0\nolQmSCdwcLis8bBmoYEqQsIX7UR5w9GM2GKmhqJPRCNXN+Bo0eh2OENItLTqAd4TQaIYqxWC0M39\nRT8kGP5B3mg7BSbqsExulJ1tyKsGeuqklrTzyf7DS6nQyQ8ykElmPd1gHpTwpT5XyvXIVqB7lq8M\nB9TAFKxVDoTVdZwP/bFRuN/FbZFy6Ab2TYQAg3GRi3cB3PJQ1VSiVsG68BFxnkoUYyAgo7ICc5vv\n6xkBb/fP9qXb+NK4oUEVjJToxT43FHgu/qPLRuLNEVF5UI8ljC2iEiGe1DABqIiNuPBKso3K+PJ/\nEUT1mn7GgRZ7Uecrt0KMm5LCE3Qit6oyVH/a40J/tJXSFK9SMtIVI2mmuePOZuADY3cBvi4siFqj\nMih3s7ldrOs6xMyRMYWtkP0/WCQNdrDyVqNGxrMCtP95R85CFW+shAy4LRlmpgfL/CmW3PEbzNMv\n2lQnw6clwHaR8IkQVRuP2vlzrARsrZIO7VnQAd3ypBWP2FA7MZo9hOvF8d0MjKtIcvXK74urX/Fv\niQD7MfyQGE1CoxpN2+uZBU8A8C/g9JmEljrJJfeGSSoaGXG0zH173ekoBRg/iILxnU76fw3NXY8f\nIKNt1vWja7aAFow0RPWL1bwmC5bgn43mjqWZxOIlOE2NErZ49gLp3MNZzroXpD1CL1l2aE4LDj24\n9kv77Aop7S4liqW7wJIDexrmH9l8orRbS2UPZ/R3mQGNJ2iPvWReXNINgIk3bLdbO7KKjjMIyChL\npyuaXowxFaJpb+UKq4eLP8p9SF3L6F6Eq+4gBqxP9G3igtC3kj9Zxvh6WX+cJQlthClQiH0lkKpi\nfSSIpWp2Hou6sj+Jra8gz58oM4nrA78I77PiSHa/0rCY0vr6ROqxer7vChZe5HIHjEfuRXKVub3g\nSmVI7q3dXxNMIeA5ViVmC9zOWm1JyX1LIG09AlSjkGOfhR9NsDmmW8ylIfJvRbafUGFim5lN+yAo\nrU1qlHH6uuHyTt/5CwFrM5uifPPnC0qwkqY3G3TTM5sYE8CFZf/JigbIEBZ42de9SJvc1h37LPJB\nNTsmCBIsyI3Dex7Zm1nmKPAJ/ayZyQdTY6JYJILfC+L6wicLqw2oN/nhS8OvL3rFj4aKBWF5rt8I\n01aKba0mYRQvyf3C0y3RRhJlg6hzrIblCCnUdMdEgIWtWn7VQ4np7+v1w8BM2FNqNUPZMFhdbVQ1\nlH8yxAx5wiauB916IXUE6Lq39N8tWo8DSoDb1QWfFF/BToIKuPijRPjS54vXXpASsM86fyXIOmjm\nB79V6mx/NufXvRL+nE+Eu76RiPoKEBbpArqwxejRGwrSVhX+i8xOsmvfSO9DPF+ijpu7q3s+O3c+\nNIgZgD5NlQlPG+URz+MrmG5/svtWh3dTcpM76X5C0LKOls6tlShI5neeBrY5EuJff0oFPrzpnpeM\nzk8b023GdHLRqV2Ikuyz75upYvu35ue8mEeity8TAERGjlXEoTypLCEEy/VkUMr14ONgRhsZDutB\napqpdELZ4RLAhiKvs5iIK/wiOIqk7sHfJ6I7vr3pt2D8tu8VaWc0UxSGOqcKr7D7/3OVEWkvZOnv\n8fJoRmEj+oxh5jkVndsOf06FuegH2oPjxipkxbQGTT0LZUoWBC0gyXwt7i2Zz7vZQw7fGlP3vveW\nYszeVe+tu4rWcKbakK5yYjNmuccI2PiU/oJdrUvtITIR64/sgFq/t59l+QESDcYpBSU4K0QoEPe1\nd4Qm+SqUmv+R4zk0qTJsfjRPeME83FuEj0W0Vvw0XkhpoG3sU7DDETawm18tXxhm+8nPOTxVjkIX\nUJxL9yic1gMDeoeE5qaPJgLUGa0iBjEiAted/I1PDS5BydsZZxPW0Xh+jmAiBh9hxPYIGJQ7W610\nc/ZCbfCOn7uf9QiupLagphGGHnrFVLI7CkLxUOag5icgdUJzMppFOzjF1U+jQq5yIK4k3qfg6m+m\nN+cj6J5HPzW7P9w+ub3V7v1+UzrL9bOsL8+xtKHY/FYuoMWA3AL+iGJE/p69eaoqkZadJ3QPEGdk\n7mpepz1GLUyqxbMbLMtKY7gtItlCbMxL1vCqy+JURAN+lZndGwDcPE4MKxUhy1rxzdjNll0ZgzaA\nygAWY8k/IO4INEjXl6drzIJaEtw4y1yk7Y/+z90FyrlSOcXjLdrKiSWeJNMuJPhpgBk18qQaIi9z\neDSc3xrh9kYSiowceaDitdlNxMmHXr46y2qgSN30CseN5CfC6EBmjhegAAckdwEQ+tz5cCpDNP2u\niv9oMqNywyWkszXfmsxc7q1MMtxhsG/EQ44qjlbToDsDW0vZBa9HQWGGC4G8HJOi2xr4xi0agG7+\nLeKPl12o9bPLRzo4WVgm7rVyVfrUxuROXoEeDVKqZsz6BEh25SElhXUp+Atv9MpW/8Eh0uubnktI\nwIjZWZJqwxmD7xLftxsKZaFfiYE+FvDHyR0+bVCFRsBnG5Mp4eNX6wyZXR/vXoUlYKqPkvYE17P3\nmbHmtkK0Roz0Qt/87saAfDLfG+n+mKd2u+tcXgxTH9JNT/d+KuwVV/zTrsYM9dNEyRoScdjHbCiQ\n3z26vVMkpI2jbYzD1u1izcdX0YWOsOE3oyEPTTMxNPFUuzKVmHN3cIg26QewIsGH6FLcQneqAW4N\nplQNvfUYdf2B7/1wnWxcS1yjTuxYaXRE25TUNE0eUgJvC8uXx1RvuWXEbho0RUKaGatCvQdprTaH\ngMixytrT+UjDgp3L/Iqc7u4UZx3rnRCfWBZ7WJNWyDWQLc+BBfdD84X+yjneGF2zS6N0tETGyYQ4\nvDvkIq0j6jffWAQ2uCez0Y6WnWmOSAFw8BvBPwi25+ALBQVs+edH+/K/C85HQV4cPQSV1XI9T5ex\nEJ+6w9LPE0XnlHI10LctSlVNgiYI5ezq0Z3+4L+/b/CUrhLwcle+oZjw9G34vgzqmKGpVO5FwGqa\nlRx/q5AMt8ib7ZBXlJgLC/F9BiTLdtzAWAGE9PoEbGBHfihjy6p4oGwxReHYpEaQySlV2l6L06Ke\nSlLNrhmv9Eo6OmlBdhDA3i4I/8hT8brEHw7VFdKYvAeJZZGWbFkw6uNA1zPrJbgGquqBLuO1GjGr\nknpu7mzBWIN2T6f3VtOUWyJvgzkf7QSYjCp6dPum7Z6+/gxKaeUeZSbYjzcd6uCAKP43z61gJdBW\nCDRKHPmueR5lS8Q3sWqvlERFFM9ln86u/kH5qeyVzCk39o8guT/pk9MJui9ogHJ0DxcPnZIRql0E\nMad6RKnBhdnFSiXcKvCojmE3v5qRGNdY8qe60zHF4p3haQyrpJJwBBRjRCeolgEqRV0UWaLhmV8w\nBFy5WXwpqK3BmD8mK8MV8YfwrYk4N7P8QQDLgScEuHpebvvbF2PKqbC+KJAv3Z1B/UUaWHLmGFXO\naX/VJ3QKOlRml0xS83SiLGuv31dr6/jer3LUrZ4EisQq12zDUwmUltOerRdbl0evDE8Jwj+abn0R\nFV0qCn5pUwm83ukG4m3vQVv1OmzEU4JIqTz2/tpSp2i9/WVkVm+XnuMOb5dqWWdZcMeOJW9YraJy\n6WCgoP62DLKPpNQ+JHZxz/mjANdGGDlbwl8gwFzxDfanbmoLBE+hRh6etHkWoQM4r/hL5xqrXuyR\n0snXDgVPIx82emND+hzPw0LcA/nKOmuRIB1efqDtTHBOU85MttWbzcTtV4Cd9S6cNRUVX/CQzjt0\naU/prM5pwmlZRusjJlQIbJPz6J39yHvR9oQWmu7PUg8ht4b9bao6QLIWW53Se0aR9lnqeHE1MLf2\nixeJf+Uhzwdpt7K0FQWQPA9wbQRvb+pfDrsz9NyaoiQH41RJJ2PoNIeElyFQlfmTFLVv0lgRYJH/\neZpMxXafNm7OiRLuy3HuTVVeQk3lApBXKu0a3xcGLABxaYVuqZN0PzfUoWVUCf8bf2Qx6MpSaIN9\niIbEpq7CkFPY6oSZ0mOlY2QckwlcmO48UZdHa+75V2l0PhfcgrUyHBg8xayAoN78ltjdYLPyKfkk\np1ivdNu+Bd6qTD19PM7qY4d/w5nYFbn0oFkeNxittd1K1tpAcOfnzK4asHG/0sm1GP/ei5JcI0Ut\nH/PvduaDHG4cZ3MEUGxcl6/2fbBiy32mns4mfYgzpHHQIV0+JXBaJttTNorzlG09lILEXL6TLU4/\njdaYkrfKHP4QQKPgk/mMhCOPAPZV5uVGG+LGRn9V2Lk/aT3h9SQJvQyWk6ScqUu7MwiHeB6hVf0N\niUabBJBc0QvVokLNJVoncMD3tP/jUscFt3T2/3O1BeVLHKdq9luQFfAZOOR1OCfX+0tbR8VB7g1r\nQ/b3/Y4HxOw7n2L4kNFkw0ODgR2N9AJbkDQrNKlz34MiOXWjQbucZtnkTwaxRr8cYlsi2ryyfmd8\niZjRdCHHaprTSBfY7IXG2kaCMz9XwFPdd6rFjRHdvn3aa3YY94kSseE5R0yTGYv8qSOscHYKKZvg\nVwez4yiFwUuEMLqSAVRyOuZ3L+kCZ+q0z9oH8bGR6hyO5pD+TLxiA465wcB0MXLZXawRdu2fHymz\nkXDnf0sZdFc+FuFuj1YStDz8IbpFQNNKuAMK3zLMVwyhvUqLkwOsUE1tIf76wqxWlF+FU2cWTEtk\nDmwbS+s5BqxX8kwstGhkcUNFDjuOKF9xxEUFzbUrZIcVdqNeKFSUgw1e5yYIUpMkgRJ6qEKjShm0\nLvBTb99pS6Yl7ClKGBPUujxmhdPxnvBWH7mftLDsJaRQDjCDdXHpdIcw+k7ctrjXl23N+hUkMgHp\nlzHoLWvVdAjchd06TVE540DEMXWSBoGM9vJjUbBt1U0yd5iHa0cjY2rj4PwPV6zj8Hd4mmFmvrEJ\n1KzynKxSk4qBDKOWavMJ5ErN3Fx0crY4HO1KrW33m9LohPD3XNmOg9efFiNIdRmxH1yP5D0OXJg9\nlUSaEaPU5y8Tu66lLs/thRvmuhJVd/GRmQlIsXQ+W8iuUiDma6hkAMFPZvznaORsV6wplvAz2pyP\nCccS2irQ3DcDMtUQ4ZkesW9kXIopH7M1zT/CEl6dJZ8TPgJ+CFMeepBBosoj1fMYihhw8O5azlh4\nMfKjFnfQm06s/3tw38JevWzI/wclg8hhqFyfwfHm6AXLrKrX3KhurjXh3iFKuuV67TD9NfwTe/xp\nUnc/pwuimmGLO/N7q8D9j3pV2qeGsGUWuhfHdw0Xy3GkEmI4210pr1iJVgAnm1wgQk0YDxkrCRGe\nzbbGutvCCaLLRQrmRU3WdZ6Qg3+mlJgWbszpsRucTj6Vs2DgorA3qBePZrAoinMd6mEuOEkUMS8M\no34KdIZVKUJH7BWBtJ9Ev5YZ5KVrqGrvsBR0bsL2ZH0T/GVBdP4JyZIqDTysCos1k5++u1xJHs4V\n/YDLFA8IHh6pW9rwxg1nBkvAl3ophXlZTZC6YFFOVL4fOEV7YDWOE2fa8J6Gy9HC7uYMJunNTy/r\nxGh6mPhrdCwXNmgDLvkvEG+5+nUyKB4yq9114H5yUJJW64Hrp4b+y7KxUjTWP9Bie5JhKJlym7SB\nW++ZWCfbLqDir50i0LkfmNaPRtPB/A+k3STKuZsnHGH3T9fKx7F+jUsQrPIj+EpABU9HmP6XKa0t\neqyXzJeD98fKj5UmQoO8aWb7mq5V67SU3TRjxb/QnYtQW4ng9HUd92gWEMtYytRCLUCGopz8nuUW\ntBPDJqAIHtE4QlGpOch89E08iCsaNiRNmtMCjO+ayf9I+i3+XCcL7YIuq1xEkogCcofO1kKI5Xj8\nbwZ+212jeNpjVKJ63/KMxzwMDC0JTxfJ0pAJaJbl37a7KOZkUW4O4zG8sN8VEWlhf4vPCglbPzMY\nM9uRdM8b+EiFMPjYzmWgooA+m/v20Ma3TDVxJwuYNcrP+zTqlrRaBSWuzAAr1qSnvu1qkalz/uP6\nKmwKC5yHbXLFvCVn4d64uBKnfiqe+V0GbNpCVs9LBtOA+qBfPJsYpjG3viPatAZ+kT1VG83eD0t+\nDgo7EZddmZtr9+oG3fcHe2JcwYt8zhr11BQfZr8Gg50iZ3GMzDQzO3H5JAe7LdOOADeSs7aeQ/21\nH4K8rA4SHOZGLQsf/iZs/DoRcOP4lrRnvb9x4tZT6t5JHDwCh4hincNrXMYFoph46jfftHQzyVfr\ncuneaxNYg1ICGbdM+SzAarI0j/EX0jmmxWnnBqx7mtpeMu1J1XdSDHO13UTMeAl0plcKb860Q3Wj\nzX0GOQ5r8zINwBecxZDUMjpyim561PNzKAVxfVSuhpjAmw29PGgkqxFpKkYFABA3FIygkikCVOea\nLGI6+Za4MoHM22iqX+Fmqnt02J/TrkZhCyAOGPgfhfgJPwg0PnNhM4r1I5LmUU8Pou9R+GIxKs/y\ntc3qPxRJGgEKOQn/6lghe8EX75FvEGKUBJ4tZil61VFhm10iIqjqkxbiA3FKUmW6/ivJ0zsYXP/a\nouGJz6SdjzWOWAYartMLhHMIz9qIAW0PllP3Xe5mhrU5dZXDRluLhzCDriuesGUbnZ2VNE0Y2NoM\nRVjIGcUF2TeEi6+o6DS1rKTmvkB6sN7AAHwBZYVT1rAGJeZzbsV3H1JeSLDtzEwk9cVb/IJ1VZaf\nCGWuXziYJWc+0wzImlkpnN1Cvjfxf13skw6GKcYhNUkPXqJbmcQv92B9O0h414nT/7yTV8VIuBb1\nO1UPRPQBbyAjnvu/7zhjTvRGOp3Xpgqt8x8RoiDwMC3Ud2sUIwAW0zp0uL/kYuwm0DaaZdXmoVnc\nMIbSKK9Wk+6Rgp38NynIhTGObCAmntJjGGSlbOrgfD32ynH9Lih7/GwIjhH7SGXI3MEzS1JnMbbE\nBqxYucKT0IyArMIf2n0NuKNFYwpuRCkDymeYJGVTDZ1ZxyakI0ER0C5cSsNBGT0IQNX5o7MgPURG\n4y8+nOEMbUClmXkhF/b8M2DqwTczTqRM0hJqtvZa761YC26hvYuk7On1pJxVwsSe4YLegn4UsE4k\nEMh4ySf5KuqY/XM1CJH6BJxvaSiwdGWOoF/EsHfRp+3cKtV7A2bLJsr7ujrEEtZ+Rh7yRK3ljp2i\nrU0UMriqHKZtYJsw3Ll2z48A8fnuKkkqPmiaG7rbEvXzS2mMo+aXGBhm61q0OiTadnNGuvUi5X4G\n/t9f3Aq0ykA65VEB4Mu7J5/vjCofUZyIQfzukVtr/FU1w4eiTYBoRPsPmlAk1CO6Dt77s/yHHigd\n+4B2Jg75T5MtdwdKckikeqj5Befl5zsqo6a7B7VpEbeb2bTV7hGKXe0BRU40iBQ5PaQF7ebp+tJN\n+nKlxrnfXmrGLMZWObdeOIDwmDuKwxndirYX8JrLVCg3YVRe55Bzyd52w+MjY3c43nF5orIWtj5d\nEV+R/7LcrYc4+YxiACE14HUzJtZoameKgUjswOnWi+XdxQlXRVvZ6v6YG3dm6LzWclGw5x8HxPix\n3Rp28i7Lu2XJfCbbf7XEbIDKrHsE3kLRQ+MCGvJ4AVkNGHxsfImuIBF0UX+E/d14ox+gBNrxJUXd\nk2FtyYut3mIT6NkjyLuugGaZoqO45NvktT1bNDLFDt1NHHGfAsgcWfuF8G9G0p6OAej3yvCacTLP\nD2/s2NLg5BCun8jdGP6TY8skVfz1DqKzsAqFXRaPgYKneuNFoHFCCjR4vSSONM/+uIqsJCtEo9BW\nU31HOfA/HDTwYLToXcHsAgbiR4zpz9zAUpq844q9SN/alJ+chDlXUpwdCKJGbTwsO1Yw1o6nIbdP\nKL6rPtYEw82aRK+iY5uDJRBtHx5BGhW5TU3EMsO5LIe8fzblxry2NYJmbTmci40SbFqSoRwaLoMq\nTp0N8bKkz7eLMulX/f8LRNmSoASlc0pLWgBzXV8GJCu7jyuQyEbJ477k5d7zKq3gqsxcM8BuA5NK\nQU2/dV9FfHaZYU10J7n93ly48wMw20JamD1CxUxsCoR6wJvfHB3eTe7v7/4jJuTu1wC40RcYxX8T\n8aYE5jin2sA5uATMPPVKNbjEG1QknUlmFTLMv3VvQNfaCbYPsvc2Y90rpMGEhHZb3lo5zQz3A6rR\nGHIeA5lrU6IXjzQJpAPuVQ6lRV+Hvb4Hh6c9qylildIhAqSdRgh2aksPicznNwBBzzsHHRO5upCD\nIGp7eVMgkkjb1XTkkcKqkb0ygAIcrFXrhSmjXsC1KC0zr1QjjK9Ms19Tjhqp4OATx9faH2Lee7m6\nX9Liot8WcNnnHlf8FWPqLU+4YuYJUP6kk49wo6pS1WoJ9K8ZPyvVXqUpFDn0Bd/xXDVXnftpeZRP\nHsiGwGXomE12/XBadfRq/seo+9MuycGurG3FPCG1gyWvF+2nAKdrG/VjFmSiIO4+QBnmNGQrtpS+\n2rYP5BaDjx49iL8RfKatXx68b/O5ySNSSWh2JHLVi6/M8GloXl9hlf+HiPCFXIJOr4dfJU3dbKA9\ntlf77ifY1H//Oq3s0+jZ8Ho+gGWPRqFYJqpRek6ImdcNhv83ZvnVJjOC6PJifGIpZjLaYLPsZzLT\nK5AnjibhsBR7qfXGLF4Fq7YpO4mqJfRzZBD9iMa6LZ1pYWlAHq5B8AwWl1Xps7SjAN1tHqN6ncjv\nKHEmLjBoa4ipcGPlotcWAWNsuCCRCYl2oA7XAsxHKPkPCZRqC/Sa2vUl07QfKeH/LiNIEH7yDNKM\ncWa3N+8XwJotwcY+R1K6OEJ1dnIm/MjVy2Xaqt0UI6rfvfYd0zk9G+dg37jDfnOeNnye3WkTMORk\nZsoGFp7lgo4nL8mw7AK5bFW27TYwRcWDdhoXUuL6IMiO2C2npe8vnbvrM3s1CayTrl5rtdFFhXA7\n1KOlSMrh1PfD48Jj4R5lNCq7aVkdKJ6Xb9VAqLWvllKIsWcR7WGbTv6JSQTi1mrp1JDc/R339SB3\nGVJX2CX9ZS2L5zRK2DHMNFxn7dftEb7ozD8XwURwlWmYrA4eqJR5wbh30jd/GC/5i+W0s5z0ll3N\nftJ9Ahb+kBXtT23zTkTzDM28ur+PAHHumldySi4hnSEKOdy1Lk6KbKKRqVK4qOyn/kvO4DLl9rlg\n2GAmRAOwOAgIDK7Ve6BhT00ZJEIYQAu4XOY2qDJIf5lIYo5th4ZGrOwJkcEFWTcxyDcu/M983bkv\nmGEcrswNjTW+yJ1H8wHYznfMN1r+jAauwjZF9lRVgvVbCkt4vcsYuT1670PltEsZUN7VSG8HKmN9\n6fKCmoCzH45bNAknmw4Vtcr9N8a/9+Kuq3Wn7BmoCxxSV2qKM6QC4sl6K/jYaXIg40aMIWx+5bKV\nEe60fjYnQSlEdhxtRSsdOasG5TuEUaE1INqGqyYSge2Oe+iMlWpzWY9i9qsNfMnmgy1Z7N4RUZnv\nn0XadssMr8rl4qSEuk+To3bquBktA1CqgLw3sDC+UHDkHF+7Dv0CXJoG+9tyZSSqBPYFC86x1g6t\nxVi4MMRZFgOuE3vi+A4LOqbFWLS+Vghecg61gyTcV38qoTL/AbH2ADNWvw9zBwuNDxuPJP/jCeHH\nAvYFZzEa9lQe3Aq2gygbgsSvLkuhYjcWrKVepniQHR6RE0Qc+HmMfRbuSOOjlMeG43T/28YFr5ht\nXsDRt2c7QkaEd6qPaXGzkbpAlH26eZryE0HKpFb4OhKOq54KW/k19PKHCWwcZqSc3om7aG89S8VC\nqlxoyQrxf0G1EoM8JfOGWF1hLRNt6wlcc+OZXedWkw2j7FdL9YkwhAgklXxNSic329b9FqyaLywT\nXykfBf/iV7VcqLZrLY1TxIEqS9gz0YIDmsGZR2wI5eQZw+gC591mgUlsU4Q33xUmpEwRbovtPBvw\ngM/7jkdby3mOvCGfIOKF6BklA9SztAn3das51JOP4BZtxb2Kc2Uq5d215YudSgtCkJjHDz/3+2EA\neHudRspc0Muvx3Kn8858qxksCTQjhlg//Uio0BulHQN6axImGCv3vKjWbJJQ/IYPnNfqvtAIJxXT\nNerLButbfECfOPEnXYEr1sFiXIMDr6qes/+49600hdmTJjIAknJo6NRnsEpmq0llBYQgbrhmwQF1\nn3otUUQSAjqcv3B5nnTkBIh9r7cot2ubb4LMu5KiUCs586Uamol4AgQzpvRiCuzf49UmyBpTYYGD\nDo8E3rnDQBb0SGPGR+RV+p2bmdjkHCwpB2Qogot8+FKJOko/GNURCsOnErZR0cDnL6G0Vcu/AZ4H\nYlN7Vhf8n7S6z9UpR3itZsPP00lh+ix+ztZSrXMnC6H8HRRIk6qgCPZb1uswmQWTC4+gy64uDCAT\nP01DnMc6pjoCq1VklDVmzYkpGYizirqXNkHQTvlMOPcP77XbzcQjYIUYPsCsNJ/BxageK5jUJgRF\n/KaBZB1Aad2I09/YLSjJv4C+Ic7ZJ0szDgoT42uSNptENpUcic78uUankleiH+8pz5HJtc3v+GGC\n7w4Xdv1fXfr0TSmoCvJwB1I/kRG4jjbm2nYQzmcfEkZm///9U2Cwc7SxLUYtzHB8xcxxAyZvmQT5\nsjuGu/3KqkNAWhdBkBvKE72RgQH3gbvCVMAZP/IjzxXPWjNe719EHjpBKQI0svEzPTuTLTJl0D5e\nA/qJFluvbTq5GbvAEp/lAq5AFg7EzOr1bpo9p12hhudIhYIs2gCSfqriW0HQoFA1ntFznqJ7XB5l\nziSMapPRWIJJbK6HPl1rYn+6yGPwlTBjQqMrvKVao+PKkTUyrQT2VeTmZpIiHcI0FoQ+Ry5EFkEp\napfMmvs0e5mgFNa+IdQjYtCkcV1MiUsJiB3fKzsI3F3iqaNiq9TYeAjZkW0y5Hq68HA8CJaGVt6/\n/4bGytTp0pBIsqPpXfjV17Af/GPBU4rp1IYIVJlYc47NVAqyv0MeRv2dO45N3pZU89y8b9PnEK/N\nXcHOMnMUp37ucLlkaAhjs7Bi4NmGamnP6alKR2gtcNd9HQIGe+b5/oD2IIEdfBoEwAvg47EIY0+U\n9TmsCtVW1WUxVTMKKL8PorcVHsf52pASYhaM1vWeLIEC1cbIldvn41Yj6v9vkVTOYJjywf69zyng\nrMKHX2ftiZOFmiyX0Cfg8NypnhF7rbIquNfyJWRh6Jq7r4EA4SjLJWHmmS2V7GQ9E2EryuD69bDR\nPUizO82EpjaXzr1yC3zUPOqADmHNFHfymb+WeqpJ2aDmQruv1+pxkUrpMaKpdtebJzted19DLDaZ\n/uKz22h5AV9UbJvzresToYlC7Va2OwFXTGKv0m8+f9TNWYQPsZQMiRSJsOgQgrIjBIK4k7HqqefV\nvwHVmaGUWGs9mun4uC4GPD7v7P5V/BZTTB4NxelNSevIQdJ0R+TSZxuxpQiv2W1aifTRpgOfUEj9\nIYbtb+J+I1uaxNKtICrZ0NlsbEDKIIHNLdgF3F5rbyin+jVDBlPOacfj6TzcrJT43z8Hw9vydhw6\nnqJA/hyky+SkaqL8qnQlJobXtTbwWG+XJfdfr3AYajmf8N2yp5m1mL28gAEDX18v+IzbAaJEYnNA\n2BE5UJbP0uLJfsFRyxVC0e/CvLYKjcFUpCISY+r1gItfeDgr+6HIS9Lg0POVqcznatEzT1I7V5aw\ncoosPsTm3Ms6ymoS6vg7b+APtaS4mrZNL63vqhmIAGdE4FNsWbeopC4P5oZCm6zGJ/kOkSYcQ8Lt\nLOa2W2f+uY9ad4LPVdluvxCKTKxtSJJCimi66u+IkYrYopI12ALAiKylCY0+YNum/d8X0QKv7pG5\nI+OLzvvIpeGb/xOEvRkcj11SoMnH9WzDiowt6T1pIb3jHTj4FehxQq2CJWzXAraFWJNpjA+fFtVi\nEyme3OheIwiNl1W/YTlfmoWBKsi/Y6GVxbLuh70PpptBMfLy0RM8Qso9MEozKLq2505huFUhQQ0r\nnXW2vgwRy/04xS5K1xFQj/e51rjLmmD2rDDvuMafW2kikulyohUI9ysJpN8MEE5zP1DpO+oEovor\n4nLLYLVYRus9q5wLi6jh02cs3rQmKu9p0bC4g5qxPJBh87oWF4q4O9Dr5cc81w5vfBTj9K9Mc4bx\ns9uT7J1m1dU/csB6ayCClP+nbJ3bsD43bCzGmRlb2FMl/H6vjp53n7FzEVIrRCgI/BTPWtqK9nkN\nMNYvtzZRaGQIvTTjPVpNGjehPm/FErXoxhlPhCt8mca1uqsT++uCYhC1r+9nezfNwODHfYwbkBUR\nMxN6xrkuNxl6CjzKIowgPy3mE4Lhfhay6skORXqISkOb0v1JKuuKOgOPX7TAbc2gbNU8p26KSeXR\nIBf7+HomNn6PnJrky0Wh3AjBRdb3/reMIj7M8s5OFJ87DaWmHfq+RIVbDZmePPpMICacji5vxsU3\nrHhdq0pmb3k3aJL3HhojY8/4Z/C85x0y7ZDFVTWXzcIQJvHMsvNrLjpDNE7TbfkwpWk75kAqiG3f\norI3hlBTyGc1ANF0KFpaV6jj8xRmNybJVIZ9TwtY3y30m7EIVPLC+0tJlqxrEOPrqlAEWAljOfYk\nvWRuDRPDKx7f1GQ2y5DKRB5zyU1dv12tKvNLv68wXJVjA0CeTVyx6k8W8XMptHEts5DntrB9U00m\n+5oKxVwGjah4R2eiWvZlZdv7XQzUqxhZW0CTdEZbBIlDXEjw2kZHRleR4hjfXFG3hcdLqB73GKZ3\nRHpLI0sgzR085BpNjWNI4WVBOk4zIY2693Es9OG8mjLHnUyY15VYgBSuBDr8us0RA0nDspTh4mOd\nRHmtxTt4r9BNaOapAeOhEl0uSOaujBxR7urtl3eSsiVx7ZpHjF7z98yftonYINCFbmt5MRFfGL6N\nfTpWWSmnK7hpMperBAguhPlDsuuDX0zCQCWKl8WjeJtHw8JDf5C5UVHxy5V5OluyiirnyiAbIbQ0\nidcDR0+C8k6uj/1DsVlfIDgcrRcmHRv3heEcZ1VMD3KL4xxOjPChNBPFGDRD1H+5w9aqkxv14i15\naZdx/q0O9pb3/rH1F6RdGSb2/MMCL5gKLIP6+UnFZdv9XvV7qu+Zx+iPWUhjbLOm+bxWFB+Al5ly\nxz8sln5Ucz0+IGwALDsf5S9wDLFRNwjgLn0CTUU+6BSGoNIIzBgjUQqCu4mlhQpEX06tLiz8MEzd\npixKVbfv9H7Hcw77Tk4E/6cWNQMWsLagTAUrI9/SxR1O43xQ3DyLZszrTh1/RHfqrgGweO/rzrfC\naas6+queFE0MfOZ5Ilhi34tGHqvx3wW8LgVh+m+LP3IOurZKFyijJWbEs+3w3DCsdTyPdijVFVQI\nZ2XNjC+LC5QJURxy5Cg1yYJzfjbNO5/xij4NWlGPzuqLelLT7vnzsCbB1fdjq4kE84Iqwg0HHLj/\nASOs9xLfourMSxAW2EkNDMvJvTamaWBtcQsTDBzXVilczKgbT6YRvCisPO/gR/InPhqd4XLTQgg6\nOCyBFpbZiq90iRdpd/7GndHVID9UsgRY/jq6AZYh6UHYnBFUTrRJlaesyhF+NAjjVbRp74divVyy\n6MAYU2jwKz3ef/QnsuNLLprrSbJdzRtQg27mSM2Q8BvYa/EuCYYmzmMQbdYDdY4NheRKSnnnkrNn\njrwViyreIoovhpgDROwFTJeI6WDe52O7lkMspwmt9SjOKCCebGmdKRWzfXhMF8D3K744aomE1JJX\nOcHEY+BD1i8Gko1bPRBchNOmITV4b8Cn+8JmlGB/0kZlsAiQeQt7/Z7CQNRfR+45kDL97fWPxCHz\n7ARyp+Mf2QupXbussA8z32Qi2caQWTKJMnwb8qoaddOMDvX6hF1MZKAqSmVEcDPT7BqkAg+BaBEp\ng3PEs/KNIzyK8QVFyLzeSJeLEwJSLBWIioMbinDl7DBrCc1UL87ZYr7JNrjFLFqOjf99JibfRQ8t\nOfuz462d0G9pbIYewUdW1ZaNPCCPeH7+bO+jw1CEMj5Sr+eRnPiMkmeqZ/dLV7/9l+6OEMhzNVW3\nWxi5FRFBrUq7XO9aM4p1HrID1VV4tK9/+Y5792AZXDdnAWSNI3H13hyLenam+Zh/0RYIZnUPPndC\nduiGhAEhF3ZKX7hTRUPAHEVt+M3A7FzkPbbqr4ldsH2EbOJnfNLk0HqktnOOq6G62WeudYTgLFmU\nx8NAVfqhBrausQY5ZL4wlxNlejGsHCkOtDE6sr/PffbCgI4EXoAFTkVYBxMsT7+63X7h0XtdtUyA\nGm6JU0QXsoPtyTueV8Eugw3IVrMlGDhax1WMYCJwHRzi5jCRdhXjyLWXx73cW2CPbeuT3fiRHwyg\n9rLyECvptl8+8QAGa53NsSrpvKgLMTc84j1LWG8vT9GNfE/UMPXw6MPflZmyG8PcoTNNY06XHmIo\ntJ3/V+zcUuQxZMX8lRjdAMMEccVkKVW2TnBkYKJ/T69xtSNOzs4cDhyvYa5Fr8ZyY3jt6C1YmfJT\nuMFH9htoqpcdI83U+CsNowBnVdNnP2ppJDqYCeSR3d7fvWJnEeZeVefmySKIEp/vUNzbZy22Ii1L\nHGlf6RYqAUKYcXgZ4iLXfO3KbnTPVVtbzRoJ1UdkWEvrVLVMelo+crunrQfhyxCmPByHJn0KL29g\nxoxhio1PFs4oyKfVZ0wpGaNUgiV9j3EUZ/LVEap8kCjiZ9GVEvw7YEb1Ry/0IQ0y5xLZiE3QGbHu\nWLLwNc47XPiZpW/ukwdz7pHmmHef04rcR3CsJW65tHIC4nM2aLYHnaEzSWsn0/XWPhKhI3jwRgId\nZAUcb3J0Ov+w8E1NmUdfHra4Tp+GLhkNyx8ff6WWwagLRvUVReIN3Gha16k6u9jaDK6U53+aj6H2\nImHIc1nhn3LFjmUO5eBFt6hUsuVPtl0MkvP0a92YosAmAko4LuBRulwTYRpL2PE4OokOovorBX4k\n/U9Tx32xJUL8muMGqqDXFU5HRxdby7Ys6JmUj08C7UQ5bs2SR0xNXN0Z4btiLOd3RokIzZt0YGVt\nzaS0pW/HVofRDr1AnV9/RxbYK2p5lY+1ZTjn5rpr0zEErF2l4kwvdmoKnKqHkqZQ2Jms3R2MDP4W\n+AkosnHC7LhMyiaP1tIm1K2U+CYAq8oV9faa66khVRkRwDNFzp5Rz4K6PSXacecypQo3zB0xt2cX\nudkeEyUc48XoznYVIpgDs7QnTl3/wPRrFlHXxedue1W4cRP6EYmItuPMjR+pr6DT+rvuxG25sVsg\n4KGiTqKfah78JXeqUnNS2KKhuLe+5cy+kt/lINvM8MDTh4XCdXlIxzTD5CdDJxUe9sZ6LsxDwJfW\nM6JOg5q8wakJ4KqH9KpytKjFMMVmFfJOWkif8a/Bjt9NuuvIFJar5tiX/1moacdbmey7ziK1pD9q\n0/yCum5jd0OY7z6Zv8WeFcpsuf3dn/zDcr0T0xwQq5ZPpZ4Sw2twlKSHffUpgsUvlfE/yNYE3qX7\n/980zJbf96++yvfmmV/LUGuNHRSOmnA+z+x4sxxJqpwD9Qb/BrN11ijlukAFBE0QVLwGxUN2ZzoQ\nAWby7PFJ/o6iHV0Oo3StCBdsTwSZiKktDwmKBebmO7BkNJgpcov/cTvj9TBaDod6/SYVtk8qwdJ1\nJ+q6yS78onM8ryEg1YUdKU/Gy1M9S1TprLgN7PgWo4lO6IlibXpdPS2C2uM54p6IKj/dk9wkpLhA\nKH4A1QhjmXAMCnAYupnbancevU+tVYtEG7eb+u+OyeI6hIgIyHE6Og871weFu2vzSg6g2LIYKn7j\nAvvsgRTyVmo/DI5Vxi7EjzcZwQ+m3SoMxh3KMt+OfbnAKz0DBORi+R4Wl34KIxA2QKk7SjpMADpZ\neRi56OJ3ZT1Ngwifb9t5AqgtkKWiFdwzUxmMkGaHUjkFJNF5Gu1FI4oibReL1cF7O015fPUb1wE3\nvLCriiI1vpNw6Lhv6CKEywt2hmbIyvn8TGkCCfr+0COi3/QBSAnN5Y6cdSw0g4Amc7FERyAt0GyS\nRatjJp4qovPaAgi+HrnulOAvDKD3Hxp4+Ntm+LeYYFw354/w/2oIKgvELaVgxzRUSN8SSYNjuHAv\nZdRLbnZWCvn5J4FXIfJDKud9s7KS2Xo6FtR65HIEKhV+ZqoPMQBJ1wTxGudMipE8XdOw+FcCq1uJ\nTjwhQ9Tav7y/3TSTZB+dExshDW9uq5lQdAjpjks1d0bul705XsotntvM3ATSjZvWJ0pLLsoyKX1H\nawiIZQS8CGJwgW0tDnuJ6cwjujqDzJid4KlJ6lfStgaA7dwkQFG/gGpzBLzFkBgkhHhPX/WPBg6v\n6alwkYWMsgcwPC0ewH0yUFqgk8X4wm+cOKrCq7NcwPbhFrqJlI8Z5JHu6trxdA7imm5FjEAMuINF\nodfwsI9Y92gh7Kp41B02n8ttgjVJfirT4duVDo4i/7HfViBcH4FaBRljntzHQyc2indp074jxNma\npAKbFvRejUdoJG+hSEK3opglz+RqK1AwAgnb6TKpb4xANobu94j5fw4Omiz9hQOSqyhIz1joVI/C\ndSfIflkZ/na84qQA7LFdGWT+h+5vZGxjFuERD2VzFQggqO5oTvKzMl/S2njm7G00uffGbJm4MPIO\nqNmijL0a6oOZscFJYbHne+EZZge3XbGcuoGaUUJYkr0v649WdThN1X4ksdPCiqwYlGrrrOS+Sw7c\nNSxeEEIKHOYuLhlc/fGt86GTnubVPXsNMyN6D5Oh8Wk4U5B3fhgaYC+eT5OCQxwtOh+KQ7QRwzeL\nluFPl3KN74oJ7WcsBLU6ZDKRiC+n33t4iVz5QJI8Ag1HZ/O98tijD9uq2NDM0R3t/Tm7fH359KxB\nUbljd/PjKCBZoLJHhgCN7jWq3yrnhtUHucwnsx1Uba1lPXY75zlh1wILCJWdyy925Pa0ivBparX3\n9RHACK74mjpPeyTS7KxMqHX94RAEdW90rV7K31om3I3yWzbepp/m9mU19LXyFgGQJYv9SRidjA/F\nzqTa29O6r5oftrR9nk8fp588yHzqsNn8Y8Sv4gE2cTnuqvoTsVwrI7D/G3qlTge41hk4L+/4jMPW\nkh2mp+wyfwinqJpjfBRcWrjOALhnlzVwU24Ru3irNNzT012FphbBYVpAMcUNoeWPQAv73E8w4ijy\n0fXDQsy8rlB6NYh5UTqLPdRLt+r93RB/KDJkvsew4ofd4R4NVGWfCBrnlXpU9IH0BBPzFsvJoOzT\nwe5zbgHBIl6+pwOLFy3z3kzVXnZSSR9P+UWTdv+PtOpdbdQpBgDp3PrW41G0LWvthr21AdhVt+6g\nWKqMDP1tM8r8SKpvZyDp4TdYrpX2pWlWb29hx49ty34u0e3thr9qmfslCzdJt63tVBuI7W11eFl/\nF7uh/ZTBgUefXh2wJRlfs+bUINOCa6oN3XW+t8FFtdpepPHxoZ897GPC2CZTEwSR5jDYMHCvxnZG\nsnaTXkXM+M3Mt8Kl/pHk29egMWMhPRmpxB3QYY427cfJRoYod8Tq0c5XT1TgRLa6BDbDa+9tgDWR\n8OjGobVd2vGzE9DkqarBp9Ev0HqvuINhrfRtWDyclKbokW/4nS/r7urKLScCeNzZpRFFMZVgDYo5\nzSABd4Sr9XSIZYdqHj08G9DlLcxAfeug1c5Mzc2ZoQBgUtNRIS0uIUUWwHc33Xf1swfSQTOstAO1\n+ND5SNH3p98eSDSJpybyqpLV64rNbjTzdBVxYuTP1hnrKNbVkqvh7Stc7RsU2biWfKMU3EL+qjLD\npIrbJQpN6nD2gFvqagAFTidMaUXwDsg97a7fsYwt0C/xMBxF9dDqXDtAXz2kHe7fJgV80F0vq9HZ\nbMLXIN/Aslx2Ujt2OxAsdBjrlpOxLlHZ94TQOfMOak8iVP+gg+GbtenrxbDEPfTR55CEBmWMxc0t\nrMRDU9VnmNrE0dEwqJORpFQXDnb0vbR94mq5zPVCQM229utup45hXjuOSbw2tAoSdBMmc4brA43b\nxFjg5YqJYqOCatp9b5809gyDYvvbri17UkOS8h/ifTmDbdAND17zP8lk/Os8cUBQ1M6HJh4yypjm\nFlIteWsqO9+Q5r6ruB+ri4G+k/4uRIGbpUsZgOJLRMUpkPBsSS/OxP4avorsyGaXf0kze+8jWyKM\nr/dMv1SbFilMQB/8tg9o+WzQKziqwMnVrSlYcWg3QPYVP08Pk4jHzhQgZSWUCx+uYBt6aZc5JiR0\nGtZibc6L4msonXuDCvZ1+kdBymI0J4m/WF0LFP2EsH9PQTL/xdQB1PcFyp7mGVmVquIyU/ODHkdJ\nnZe90m4RbpSRMVJn+LDTZIuAkLEUEjdx3ojknLLc6j/E7M+0C4vE8IAELQl7UfqjcaXqynXqHwJo\nyPtPoYXnWYDNTyn64NeY5G/+lgcZnIpKMcwrIWui6lUMqwPwL8qGkAB1uraMxdz11MV0GD9ijNC/\nNYfqrf1G6oF+dfHua3VBcCCrpWOIde49TuMUjM8TNLcnuCKTxsWn9HbTtuBW6aneFwPtCeZHfEKc\nEkCt5xY9oYGxqInIOrGzRq9nbeltUFFhKAVJ09KNg9/hBbsQW2YEzPlylEudD0lxrvmcZrMzNlZP\nCdgq9GX+JsrU/GHFB2SzZBp1aqspB/Gr1V/AMAdqqGbk16ODJllHhl5kwaGLnFaLXgq5RL1LQ57u\nVMgk4udL56BLFkYBnmLJHLsbDhNLvcA957TDq/0vu+W8XMxrQ5zOO9dqVA4Sx0s0jHB3jkn760p+\nXbyRHaptH7gfIMa0fP3RyvWOIorSxSH9TMIIaR21hlyAkQG7rgOTbTHuEkhncMPLka72uIT5u/bk\n8BS+j+6OjrrgJOCR4DU8trtB5sliXc/HRNoFxeuKkdSf4qUBwx3YxySj+Xa8gwfmpUeNv/RafaWK\nK8bpxYZFzGt1pamixyE6Gm3yUm696U234thfmgfiZW9IxB+wD6Pr2mqDtqju05lOy4RXBuf15Adc\nVcJ4ZKrxrq7ynanaFe0K9HP7S600CrJ6LmWae6l9Pz/iu4QTUiRDD1v2mJnHIBqN/2qoZ94acshb\nxen8rhh9EkFmRjE8i7885pHPI0tuy0nIv5306RSVHePnYnomUNwR83hTI0TpdEhnras648tQyAZD\nyLNcBFz76y+JYyFNLQQ0f7J8Pwpk7rZQn3YIf5cjLGcS6j2xg1rbdMtOkaIoNQPbqMpjlx7ya0+K\nY+utyRg8/SFv1DXx5h9gJTc/H/tHdi8YDacYSWAoocm8X7qJGrQ4Wm7oP5BiHsUjmdIASjd9jRCi\ndGBNLh/IS8s2SqgrwoLawovLY5xvkZTnOZjxan7HZjIAVL/xnXC83cTHXHNW2IfgroZYCctQCt4N\nZiaYNeY5CFnYjlIO1DsWu9rr6dM1YOZOETeNN2nEazFxdUSiIL+Cp9KNomsvlL/lvKCjVbElT3MQ\ncK9PA4hSw80bl1EQz8c1wewOcEdXmW3FhoCD2fzS8fD9n6NHHloD4T02xerIPVxCY+G81LtPzKav\nA5qUBhrIYmZu2nkp/tZgcOolDcR6cjJwLwQHu+MeW7VFFqvr/WK8f6SO2hMyKNZRsDeeIlnonFBC\nVDwafpWDJdH+Dm8uDpiEmhYo183WmxfwZxYRnbuFneY7aXQVXdMkMkj8m9OPxJqT2zXXkBa1fFvX\nMoU+zBBjyVJg4NiUHtqvbQPeZONh+Xl5JHc0CN+wv5kXe6KdQe7wPQReu4YiajHue11P9xhedViD\nTZaeLRXK64YbI1rGc/tG40tngmAha108iOoSszi4T3h4Bk0b0kzNz5pSB8Z8detd5xEXY1H8O7D9\nprdRO/umf2V0vGgWC97Hpkzfi7vBux47rpkx4686dfIb4wsW5e/+24kaxMIHjSmSdhsIYRZpoqTv\n/61bW1Q31WUasDarLBChZpXCcAs3wVwcO+sQIrDBU5jZJInlBGx/OWX9m4oGkbjIoiiEZUajy4pJ\ndNtBoO+AlnFcuEVoOhwIRzoyoMUwQxQV/EIw43nqgD2C17QlsDjx1yN4ETNOniebRFMVoDHnLTAj\nMnIcZEVxIQ6DLULVJF5BWojhOpAsRcoZJO2O0h2a56q8uJ9/jU1CGHKEdhaoeg7d39rzqmEZ5Lz4\nma/3uWWaSLtbki6kO3SaS9DnUzh1QmncC+AJ/ggtclOHyIHOg1roV6AV4Zoj0RZz5SUrL/lMqR7K\nIMs1dvo3d+Kyysu11SsT1hACaVq8/iJIEjQhd+zW9x55GQ/u+YhU2j8NbEmE7B+SOC2uuJrjh7XW\nz9vWpt3TqX4zOOAW27s3TWGylv4YZU7w/Vvuqd44G2WB2adQe1KaYPj3bDe70i59KMwnFY+uvx9q\n/fMVEEiBZz9j1sCY2Q+ZXea2AoQtTQe5+C1WCYt4blx4/WbvmLy5tfbLyXudU3sKAOq2O/5VZioS\nDFKccHv7i8d/0E784nSXFoFWis7esrHdTa7MHUqvd3X2ZdDgbN+GE5ht6JTvnr4SAvtUFO1ccnWI\nYg0a0Ip00ySAMas1ZxEleSpzead93O90Y7a26XMyvOczGiq+9OifmQrcJK1J7sMPZA1GKgG1ZDxz\nILEzoUHRENZtf9wm81eopjj9XZJ9HAa7rz7KwZKs0qFs5qHMtZ+s82xeKtWFuJ3d/2MSDCIZo0MN\nUITWrSjmkqgGuIjCX9jhbbTwlujWq5gIWH0SZaq4vjUEH7HQ9JnCAVs/yhFKHyQt3Vagpvusr1eA\nFLbrYEF1oX+/53s+xJUzf7jzdYAFkN7kRWvwRNrM191fQZj5f/Oykdf2jA5cXbqVICcOiLIHXqim\nymoIJiRIpjNRhQAYzQ0bKfRgRZbKYxtTTf8nQOXxIgqecN0AuEa4YD/EGHDKuNxmfCUYnWsAhbxf\n8wfeOkLTqZRtNfD7MAsrVaRkb/DwKVmHjDSd5EeMhSKgY1jc+guk2LI5R8IlxWy4yW7PBE4g/nCd\nagjEFUHrsJrpGhUe7/fztwDDNsgBig/Y/1vQytfnCd0ST17cKjl8KSBlcWyrA0921kT3GkLq0KJt\nrYAWI9wDKCvOMr7xjjznaQnmuWsbslq+BAyKPnqeG6kDvmrbatLZLxtw+lo7jmhf18LMVEKxOoM8\nNRE64X5OmyvWmocNp5l332dB1oRRNIRuHLoQcWkQ8h6QPTFqKSsI5Oi84+JBgwB2Verj0fhBLs50\nqn97bcHEfWXCnGFf1MJLLvHQ2/w8oOEUufYN2T/raCg2zQhs8GtGK59WPnsiW4uZ9m0flTtnoZbo\na9MbtavVSRfp10wigCOhhiKOVVedOi9tN48i9WqreweFIwqmpbT/kIGV+LsjwKyTRxfo0MriDzau\nTlKMKHnlAah2PEvK1R+RcF7Jf5oM8J3nb6VkSGr7rbm+BF6vsccZvJaZu8SaEHrPEBmqfXhm3NPe\nW+4ex/FmiC+5Tnm1CmI+871n22c4wExSvE4xzmJL9CP0m73Zjoufgbdo163jmcI/Rlo35RgNSvlK\nbH+Vpx8VWuZ0ccRzzF14BDsf6XIczlLqWihQX3Q+BZ0UCqlEOJ2YUMbPoEkd4s2P1nYzML7gSArI\ng2puqrlyTX8+ZSSeDBQ1RkL8aKasEr2XTOTKYp6VWiiJcHUXgL4DYaGdNgXDxdHM5OaQukMbyKOp\nZ8lUTx/tCZ7JMi3RBUWbzG8yaHgd1rgB7gOesNEdwE5kcnLOADCRhztMrG/mQr4ErUBoSaEvjQgG\ni2veNHK5a+R1LTRuuhM/5ugyh6jsGkp+v5dEkJCfZ6lZEcQ2KCXiDps9q5BP+BkwB6ZaL7f/ivbx\ncXOVTyOAgvsE1iH5hBb5OdgeEZf7SaK8hBKOXgSVEwnwuU8ayU+2zARKYcTMzGPmYxXDowrfvLVj\nnkP5pIi09pJVp7gRkndJ929O3Jn3y0+8uvYFIVgbeL8aL8JsXVTLiJtTbJfwkqZNcfhDV8F7atYQ\n9jgyeo1/zcLJi0hBOVx25lK+Zydw9vNK6ogLTCoKoeu/hcT0TLzNClqr+RT7jaIGaMYyMs4IFlPe\ngyy/KLE1jBwhXKcrbX6Xm29Ef5/gQpj5tYWcuwLOWK5XPrEMb388AZE9vwTmRhq5Mb4lJ1VpU+cQ\ntb5joSHuZZWkndO0QcAUIoAK11KpLN5vmyeU2yRYubn8HiHdwwBeIoZM5F6YiF1fUe19OB96wEAY\nxBKsyH5t8Bcuwj5wo4Bg7zMhKUylfXB1uzDMMhilBYP5hg51mSXKvlmzmEof5xSHHRemWAE/dYUV\nAP+Bf+9kVh6aMEuanJ/GGkPrIM0v7D3mMcH1enrv/dlgfNs78BFIvkYZpJCFbdJiGAm3AFA23Q6w\nfSfWUQFICQTW5CIuvzBbgroZsBFEYO4pWpe2ok9G7bi26vo6VEXQzzbfc1ymaXmAQ0JiX0nQGh0n\nYanHWYxjqXGvDyQE+edWhPIMsqs2O5JydhNvk47E3YF3Iu/YOjfxOeLzpGne65Y0XYcGdHP8VwC2\njkVj7WODvLYH8HTrSmaL1Qtiq9ZscDc7qCuhWfPLo8jXYI7o2O06UdPOI4m/I7EIKI7HTBCsfrYY\nzIV6TGhwErzo2Q4g2YKal23HJAC3255+7Ii2xzk1hJoqClGDNOYAhnoz2ak1eHdhjkQx8FTqr1FK\nSFhm/7+2kgG4Q98heYV49FxIIImnudAI1ON2BdlZMzjw1XoFG2Ui/hkZ2e7TE8m7qV+YrHfW3hIv\nr0ovWG4FXZSWLhjplpLrtO+hudWPgmMYVXctJLtJlQdiR5e5D0iqcjj9fuYpfC/RsiLMo5dWkJNr\nWroX4ucqmlOO6hEs9Kj6NEa4QdJwY1FztCfUAGlYswKt2ONCHwLSV4MzJ2xN7NzpY/8XbQPTouq+\ngQxmvxWCOoeuG7GKHJzf06pohikF453/UK8QTeHVFPDmTder5n6+QcOgUctUxbNPcBc+In7toJIr\n/copnUSmKAHAVp5VyP3ugz0lpItUGqw7AfTtfxk8TtE22fgICcWZCKVKAkFVt+675tH+oD2PLFJG\nRCWx7n+4CM2XLT+dUUnEmpCfpAQgKygs2hjpWoH4DjnvrBWbfN7HQNrc2Bq8vllmjnc1AnGOEmRV\nBqnJQhwWD1GOd1pYoAB4SWk/zz8qBi/6NdcVVBCvKM/H4tJIc8gWs94hyJ8XUe/4OAJrr2OaH4oC\nb5SxQVwjSsRHCUBAhPpwPsZmZ3rQ2oC9dB3JU2juttVvrla4pmZ4BDyhbo52YgqOb/DiH8fOdGDU\nvHZSyy/SK9htTkN7M5KyER72RHuhNM3RdsyuzRBUKEvQ7eY529pX231lS1nSMn5FWI3RNtSqOl1i\n7hlisRC8Cl5ikyX/F7dk8JlMp90gjUUTarWTVzJnePHu3oGrhLzKbtaxrdw6p6KWWCUbmc7R0gCi\nJoofa/VexzFz9RVti0Vud+aucNW0NxDBzIJHhjZmYxgrFXgIeilE5rLJMeJVSrJqtrL9LvZC2MNZ\ntAhQpHg61AopLU8edP2qyUPdsyFodLy/ETHyht06BWD5hgu4L4J4Q1eTeZ+uLRdpKotqVJkYR/IW\n45u81Xbse5pVKQydmtnH/ST9d/HECozAaKV7y3GSy8AhI/5yY557c3QvkcMW++09ZGTv6wt/Iyx0\nK6HWUwfsYG/JVgWqGS1P35Pzjl5Tmfi32prK1vqqQz76eB31XXvXUaHI/KX6hyQ5V+WzECURosLS\ndoQqUaRYKoZe5sZRxuBbyhRsik1tpTZkTCClkyP06l6sS6lcic53JLxv2HIpQIcprAaNcQrrT2zE\nQm9ZrIrzX9eVr9Uxa2hbfyLgi8cDsmJrmTslW2/WID2hZudJlFjnS9sBIfrWZqyXJVOoIlaziB0U\nnvgHaorDItOFhocHvKgYz8eFzAEBLj7zwQ7QLcA2BX9YGl1Lob+XspA82J+lYeMAhkYLajY/Raa9\n/aAPga2b01vwfyLUsTEWbFpRwwmWOvWJb36HNCZyFJI/vmjvYJSqqIqR7KEk0NFW9CPlCC3tDX9q\nTCrUeKIkg9zDQvybya8av2w6XYUAi1ZOszYskE9veyMgscSWq/LcgLj82nb/A9Qi6bitgDFWNifI\nfVc/g4WBGM4LQt2wDr1Yzikijo4LQwy1jtR6F0r6gk9ng6fJ8aSRd31Lc4DcdNBgjIrIfV2k6Tf4\na6oy4OTTxVSYfkHTR0ECdOYLom2M/GJMi00UcdrYgNI9tGgWl8hMux4wzqR5hBcLryP455y/vJqa\nPINof8qXYIQqmNZQ1L1d/KL0mpaSOo5cXDxXptrdr/Cp/812xSUL4yvomv16LTYrb0ZDa2Lh1+oO\nAVK8UU1k3Oq7T3vVvKI1IeX1hzg7QWoNk3QtqeJdbsBT1/s18GE+CWPhyxDf9AgVhZdFrMgIhBZG\nXTKNf1KNUudTPxsS1knIQSRPVsZoIlIyEdOZpzJyNSXUrj9inMhPjDfEjVC+Qf5MOm+yjuqgJWGo\nY+Hu4D1WdCpYMUJxRXljxz1iq507D2qdNZEca7JylxW6LQAJ0vYOIqIPgWQ4AsV2zuhIq3m1YJuX\nKD3yAVX16dECAYIpGVLz8kUN3d3/ItcN5esC1+Vh+2bkZzRYtIACPlDd9ZT48H4CFwGJ+2CAucgn\nHP8QHU3HeIQlJwBWDG4rjc4GU/BOPVJ0Ml+KOam/3yW1gKTMonCNppyCS1Qdj3X3jYIIyRJ1pBr/\nbCxjsvoME4fkNk01SvW3MJW+eiXucZaQim2jcQ8Nr2F+WmXfdbTZe1aUc1gHmNYwDnMMOnCGRe0r\nhH5EaVOcaaEi7dFBSlcy1k3h38zB3E2Rt9dav7fStKQhExPBBFYgWS7ARmk+iW6PFuT/X3k+6SQU\nZ8cGte8Mtg2jamMSo+KbnFj9qKU1BIxOB7y98HxpcpwbYR5mZ9q5QLmVPdhNDmxh+tedYTOEkYjS\n0bU16tzQUrRQL5gOqpxt5D7RUwpmZzNiht58uEI756Q9BGzsBPMwLik+8g5cbZKHqGo0o2rvTxfH\nzi3DGk6WHzOrwJ9WLVBjKyP4VGk6+825FWfbac8WkOJniNHFyRxHaSRpzxeA149N3ENoYoZsN/0Y\nzp5oAQ/n9JrMPixWjJzYbvh3tldVZOyUEJbZUuOw/M+2tgEtV4AlOHdNc76ieFP44PPASbqvm6Lh\n7E9Y+Nx+9f4yz/ubwmz4M5/9uSyAXmnN/e264roipbCHq8lwnNCvRGsSiyNCGMZRWHukYkIu9sow\nxNPecE//2u/xXKA45TPRzweEdKpHbJ3Oo09YtOL/HvgTyEDdp0w6lr3xLRDgudo3ntt7RkKvDn1F\nmaLwpL/w758VQ3OgrR4P32ZlzfBV6MTBxrOV0951kuSf2HBhtQABZu5ia6tXBgHIAXakEhyR5+jg\nVJh5L4phm/voHnzFg/QK2RbsCuw7nu1OeT+/5R34xF3UsJfd7TQMl5Fx5g/0d915np9ww9kAB5xg\nfKT/DL7QFwS4freqdB71x501RH6mXHw/MK83bAIOIyjBHOWwYJKtDlMa/kQRJ4RMNTIKqfiUg9nN\nFSvRnse045HDlfFn9aPXpsRC+BpwvftumGIlUPiqstpHCu4wHiDCyxNR8/dG4kTvJ8ImTbTCV24R\n1bP5rdNoqwSzymuPL+HvOjHkyFsI9JNGpKMP1du7jjHYBPP5o4mpizTGxXdb7wCfg3AxkWwYOVz0\n6aV4tTgm5sH0+MrBbAwCSGtF3sWpJjV9DHa6XfW/t0IRJUNUgrnCjMSlrrgBCVowopcMx5Tg9HTK\nlrSHRhwMd9Hr9P+0ZuerF0qjOYUiC1aGz055AERPjGhLuyDH1ddczETrCQ5BtEbsTQAbswNOFuou\ngx8jaLAcO8LO6azPPhgf8k6+1ajbHU2jzostoOIQt0TXNoHg74xsjBNRJpPapzwF/pkTJf3YHE0D\nL7FBCBMjho0D6A/JAg+Uc2EahvZmma63XaLto5FvRjHA+fik2MlPBEQ7pBpFf1yNo//GWe1UnyX2\nqfGotB6AuEBMKR/Ep5pCcx2M6uq7+PjeMVXRLKfr7IHGEJqT2WkIVjWtcxMFuBIgDRyBtcqB/GJs\n7mOK9Hk5kPzIqw7SNttRUyYwizLEZFm8syNJmGgMWLDhy1C08+H+1MAsJ5ZLdAOTQJbW2a3F7zu0\nmjdQFe2khfKWV3VRVW21xd1ZKG4CiuPjp+zWf8mZUPGrIHrzVbTBm3QJMkNQdfV3swvUsr3zX5Qr\n36V3L1m3OL1ExDiodRjf0K5+TogtSXQmCUlKgdSkx+LRNEyJsInkWaIaS1lv/MZDFXmLU5HedJU+\nlWYOdCUZ6J2nlop/U2rUB8aUEVydL4VawEjtBqovNEa1Jw3I0N5Ssya5InbnEp9jfwNldEAUUyS5\nShD1nggYr/s6bo8WMw7BwyrZAVebVWUyyqxyHFwhtrQNFJT36e3GWjyd/oNBj8DtpmJUOdMaj969\nHK0fC1ERvr7hIFRB6v01yq6V0UjYhwSNyOTXmIcxozTT5nlB/ADFnu1v8sg4Mvyeh/K35mkFtvay\nd4aSEuXTqpdy1aWLG+25Im0xRSyvN8e03opI7d9wl93syrMfaaSL/DwkuV1aUOwM+6JtgTHh4C5u\nGJHL1lkig1RDMqKCj7dgI4yziQGjUEKUPHkkRp3JlC46/JeBhKHqrobyqFU9+41ijcFkcLGplOSM\nymgSZEufYr8uzdvXRviYDXTTyS6RJw/iU3005Xly9Kw1X5f874yVdkQCi0DDbo6M9Crkk+mmrdQa\nYv7kY+5eVo3V7kNYTWQl55Xrg6x917Exetjti9/wlBdombG+4xTYo81ptH3qctC5tCUqUNIHGQXt\nsOubU896IvuBrq1feM+QjLDYf+5413yFx35jXZh1OenHgpl4CBa8466lPGmy8eru0hVIcPf92oLw\n1bqmcJrFgoz3lRH7n9EplnkEggAl4DiyJxPyCqYJ27+rhgIabSJnm1ICLcZ5aTF7fQublY5qCXUK\nybsLsL591a/vl2wKICOvOFHN6s/GA2bb/9KRRQKS83fh5zXtrEFIa18GFjot9CsPSZqE53bDEAdE\n2LgFPN+rzDNKcX4aeVhHRr1hG1ZpFQINbW0efGCTpJkNigky/jBz0wupjx++Tov5k3mFyt+mah7u\nWONx/k9yVrwsFz7WmIOV2u31ABR1zg8iOTOF+l/dkBEzTzjhoUIZNhPZgAWaOJ84JFYoESk8ul4W\nOImf3y1weos050DxIOCVNQkxT3d58u7+PJLNQoEYT1/B5wNMqp55Q/64VgH2vqNpzxzc/msdB+j3\nV30gqKmKCigYi2A5WYwVhDRsyhKhfaTruDOZ1yoANMRraitZnLg393k0XaspWcmOuCDUdwPRQ7DD\n5fCWt++EqzmBDsKlv5LeKTc5AmQXYgCeDLU7iP48P21DVhpmOW6wGOijWQA9ss+zdS9DANLpTtMC\nQN+P3Vm6VIopBWmYOP5Mvlhq2AxRMWQjrKCLV7dHDyEPLY+pqRK1W5zFTI7J9aomgYmwM86i57Fd\nE+BNxa6yNPdhwSS7Ylp5l5LvLstktQqNr2H1DPlaAJHys2/xEfBhmE63Cx+YDrthBcbCqTgePriK\nYDNv8+yCOCxdZtu7Il0+lLeDNNNuQgU6M88P4YZ/eKs/chGDQIVMratBAUFfvZp994h1TDBkCM2X\nh1QaoLnnzLabqOIpPr4R7/C9DZJBU302w9jePYT8d4jgUfsLXKxugyJ9G50LBK+NNdqHXw+h89Nx\nMR/mnBj4eSpssSCqaZvLoqZxWSNk5omTHXY42A12BCItxXQ34gg7vR/kbJ9dbVQaPzK+WooeLCQA\nfyYaxN+SWTywygfH2ybt40TosMkueB0uBr7dBEkYWzFnSkVVPMqXzR7a3FQCCcT/+4lxtY6/SQ2n\ntNjqzdIq4OT/3wFEcla6pWJUhGx/wRoE2trseonvqnbplfJUSpuEYw+hA+k2lTpATL+FuzuoTZaW\n4qpIsitXAQFHUKpvQRHSxz7nFnpS2rczkfcvHacT9yFeE40ABo4zQyBDaHyfnxf428KFALYS+4kX\nqX9+wO7v7jzIuQRn+I+ShEBFawDfa7ErbBlLvByZC0Ooro3mrl3E0YniYCiyxumMcxDJ58rDU7xj\npMrWd4vWmw5TgtyhV7m9TXzH45SdA5oxsQtP2hIN9cW1mmIG75sldf1L5CeRjmCAeae7dj/INwJK\nzk/ZAJDNy8GYhC/2YKXiUvcLAEUVDzZgqqEPG4U72GDKzFQQO7rNlwiGw5IPbvnBpjJGXJvC0c+f\n2kEOGwGMrRntg9pUhqJ5l0elVrmwkyTzUnDCPbrN+/X1vPO3NOJnjo5sNMHMJCF0rh3QNDOIr4IO\nzO45k8dl1fReJBdCIDmzOze8/DxVLZeLTuffWjfx30cDs7ec8YjMdsJdcksykYAZYCSu1AVlX91m\n29yyH40rYntfjebc4IwouxNzpYvHs7/i0lRLT1nKUitCloKJt+9H+JCh/5bge2AhEvhE6Y7j1pTl\n9BldMHMauKhb43pVMqXwEzAhwOVfmfo5Yqiy7H5pr4mPXu7A08Vqckht+hF4tNejsCd/3Aqv/uLm\nfdNBHsVwBeyUv0bzm38ELFpSa3bdiIwFA06FvU/OQ3Us9ef3gcwDXVtz47U8ZN2sLfJiNPwBk2iF\nIz3Sr4qqKAggKtkUnesAw5HghZiZqLjHcr6XKKj6EKJEKsfLz2ML3bkUlUMMSgctVwV2F8gpQi7m\nf34RmNCd1eM+SEZp04x7GLsxIUBiWVd+GTU6VkrB1u7Ae7PNtTHte2D5MaCAjBzCSG3r1IIB3zqR\ne04H84z0KAguQ3KPV81wG+IQqegKEVA8gU6AkL0DTVFV6ysuhZl4eHJDu32KJaD0KyOwghltZK/q\n5pD17Vqx0GVPj2+vFJbXF+WB9kUDciVUMlykGI6MU5NIfXowvOToYQfzYa0luN7QvJ8oqqn2Aj7w\nhOAUav/TWT2Cy95gHmaSy9QwuslFun/vlRipJEC+7Fl94nCmQ7GOp3ic9pJZTej0IBeAMGE22jE+\npVxTWoC/xkhqiRO0Bja69kMnjl3+tlBn2XR5qPt8xBLZmlSmNs7Ecys8GaRMlquBQre20Y95QOjL\nmE/vV8H2BDkZHU8OXKROYMeGAVllq6zMytpAji7jrwAvwid6dhUryj1+BPH8HiLu8Z1VkAXiwV98\nU/Ss3R54RCFLT9r/kkFbEAEUIySZIWW4N3OQYlBePjt8CTmeO/NHjmBesUk/rlWruw5Nuvw8A83h\nqh06KbMajh59HgboJ1iEXggaltXzKvs0cwmlBVeJjJZ62z0lB4fgilyTVuFzE68gbrvd6x+O9vI4\n27KG13EIHKfcXoUDBNYM68e0KGZAQogkRcXEziLWjBF6MX/pkcC+oklNI3Gs/gZ+vmBxz6DifQkz\nU1tnjv37W9KmfKCzDPooP8xIWGKQ4Q71Y7a+0FsoDeWcPuEGOmpTv3l4U/7hMwOfNaB5PhbrpBOj\nU6p4MFokFbSm3Pc0NsusQ9qwFD9pgZ3WlepprE7mepW5jMBDsVMGBWk1ZSxxcjEohQp9LzHSY95d\naePuYKS4QZZp4Om6OXcWSFnS8kO/IazK9g/tUOg5lm5DGIIXwLs9Ownl4VvJEWpAX63ScQZC8TMe\n7ydRB3+f0pBl3B/uIqA7SlRZPv+m9VulNhFUKjufr4CA0Kd/+GmsIneaKr/IAU6lNEy+QdS5jpCc\nZoLJQuGjP2NUGX/Jg0T9VDlac0ka8vxMZsOeJLp4JTOQCWpA1tascKSCfvGSlU+UxbFhQR997rGc\nzO/Yad1G/E5iWv10z8k8Dl5QAq4uMytCm9K3C8VE7q8ljnfKh4HxQbos17ASA/UH/KUbm1Vyc8oM\nJGoOaaSMSW3dpm+IsXD9vQ7apnxMDa8/dr/Bxe8Dmx31MN31qhC0KL9nVs0y/cpbQ0h/kenwbmAr\n8Jp9T7BJWDGV23pKPp7/kQyECZkTrGQKcPCv49+hqcq1P/copkvNxPrexPpdswujRHcY8shfkkxW\nrhXm/92ljDYLbcMIVfYtHQzBlVyIn9LeDgV7jar2s+slqfnBFE5iou7iAN9PcQCSlVaoJcDokn01\n3uq5Oq04HqH4AgwkbuB4DjXjylI6jlryCGdok6c9bKsbMV60HPXnKKgCxN4ZUSIq5lTCVCU2UXct\n9lX8mlTYcyFbTvhgahavj13t0R0frHH6qqYlRlxsRcvAm6/ZIOYGll/bvxS5QtKGV5+FMl2PM3nt\nDXXCuPyN7zH2bvCOSo4XRml6vJ8woqqer3Al+lFYkHKhNFpYJ58njfxJVatQziXAarDaehegLn8p\n64mIM834mV3cTo6fE6m37SsBE+FaOUL/+Grgn79OUDoeA0FnlYjVi2fLCZImrYmVFiviVcE24BcO\nLpSZVFCkSQdYSBo1sYxbo4o69Ap8B3te615hKCe5+vu4l6Jfz3AzR6bZK3C90Ri1p93M+2yoCPNF\n2c8mUhhCf8H5O5QAyKWEawPLS9VjV3lV/mZUjoaZafyTvxxZ985wynkP88y1Yllte3KO65vzp3sH\nyf5AnZmZOiUc/DJKjDs6vq7VQeDlExobEfYMQo8aWLSuXubBgKHe/e9OkIiHuOHrJ04c7ByTBIbb\nv7pwgtmcyVKoffFYI24yATt4GWgf39XkAzpkXh0Syod4duZdatRGXnHZGwOz3mKhyBQ+iyWX09DE\n2v0rZZTXmTJ5P0FhVdWncu896/w2OXEQIgi+ymUc4I8Z/b9N8a8KBwiXrJL19NbYiSbAeHe9BKOG\n0mb/oJrMT1Tjjt5CHN2u6phe6amWhSsTib/iV7EXe14lo98ajjcFqRbK/Sks20Pti5B+5nbqCzuS\nFcH5dfZEudSja+ynRfCt2C34A0zheJ502+99gMeJwzwjOeRjs5EHqElPq3Oz5bT3AW5QxoETJE1o\nYADVkuGXmSy586Jb9fCDmJkhRIINRVju9juR6smyruKkp/MbUBhGnYuSfeXdQGdpDf+z6dTpDUmN\nwEA1s0kfTt2wjmge7nvu1LoKq8pQsqBRF4UmRUJwZclSFgR6tlSNTd3MWR005BoyK99u4AUJ57fI\nb9w2IU8a8njFHRcFVVO/cRAzb0beMsQYxNGwqt5sLpECL8mbiDq3h19DsEMdwDJSpxf7sGrp3eoq\nl7RlsGq2/2b5rPoVyL5bebV9FtGBxS65dJipU1LU4zK9zvxNouWvr9lKdDXfy/MLiuN8ENP9qK5w\nrsS0sYSMRdnSge2nXKFjT8M2gLysC2CxZVi5+VSRIjPSecYjNV3OHATw1/Pxp7Yn9EdR1StSyrE/\nKn/uG2t3USVv32kFb7/EJdW9TROW7qeaHABKRRWn7E9bFCUeabO+aTiMfI1dW4CUvl0dL7vaR4Nf\n7gdtyCFeuRxHtvIGBoYWMM6dU3m4JuMkxV9sb3SCX2LIkTjMuVqqoEYqigpzxoc9Xz/XNxY4p5HO\nQF2mDhB977JL63jVoMtCCJ7nqEt+0F5kXq1mhDdMiH/XHucajwY+UW0ja74VXcxFKBeMx7opL9M3\ndxQlWueqw1a8EFSu2yDbbv2LjSafjSx7MzgHTo1kQzb+oe+5IWSEp8dzZz3Ehr3GO313EZhqDLCJ\nyo1cahPNbeWe5y9/iF29OKxnj3171g/q35nkqP0cFb2hVGQKl5xjdtJBcDRxgvdjMl5yVgLU2Y9b\nrWMc0J/qMf6vh3H+8m9e14K2oMtRUOxNAJetHzvZ04Xho3WY2e5vS8sZCG6dpavxRbLqF+J846Xq\nfW6iHuEJcV6DYL5/nJQN1VjaWrU58E3WGiTuNCo7TT7zwSVixJmFk3rujd8bEG0z7TuG1XTHp96o\ngIotYDFLuhBJiEkG9h635N+DuHDcpjSLG59bWaD4MulB6Cr21EwrQRi5EmD4qrfX2kSulW9lg2+T\nSxQBApx6L5b4XbQCYdmmH52GO55M+joKrrx9loNCo/RCcwbV9VBIFZTAcpK867qktCCEVwx/Dd+h\n5pkrJ7hiLtwEFZRT2ZislK2uLL4to6XAEeAUDtxqr7GbNB94K1mPXaotsiR76kUvYQuOJYjEuADV\nOf6VrAuwbyVTdBVSmNIlHwxsxbOMk/0y405/BU1d5RfEmU28YEjvOLEOUnZEYmFq2TpCz/Vx2BDD\nyAW/P5JFTM0U+aSlbnXCpNdtTQ9z30R1jiNiJ9agXUkYneoMm4OUYmLh+MQbAr9OCWhI3he22Igq\nEW9cFCa+j3nh2/7cpbm1n36x6TK1o5A4Rv8dxbFwPOOrfAX0F1kCrnfwMsZPTVgKIvnxcM7/x0xm\nlByzyuJQ3BOd5mcHrVbFc+ag+T4wxWu5q38WDX5YXu5kJqG8W6iKBbBlOQMcCdx2nOeEQde/jNm2\nD019hojvLUQtNfcyBpmYNINUuTW2gQ/y5G1kO5NrPVCFZB2LZuCTBd5+jgpL9tFW2st4hiCvSlLu\nichX9D1u6Ofi+bnWV2X4ZYgPRp43BpzDo3ueScSZd0Bd05z/8KuIcFduGl+Zp69OE0qF/GEGcWpl\nAeztSszzda7HMenaM9kE1krdXCiAUB0Ajz/wozETFLzKW2B+3LXexCohOfTd0mVfO6eZaRAame55\ntGRtQ11CK5ZbpZgJyKXFLCMvQuUPjG5TMYupevxtHg996d5P6vZiJ6c309oITgKYCQTIXd3yGwZ0\nYAdT6b4z3oyndo3gn+5NGTK8I784Si/tzNeBRahnLMohdiJBIZq07tMIHXnJ9jgSriomJRYlnvrI\nr2Co0DQyoaWtmG7/bxpojTGGnujddcpy4p47zux4wux+X3gsIxuGThypOvm3p9s3xDfJPyl5BtMB\nzm4dyFFlMDjY0T/iEMgc/PILkLMvpeX/o0KkjWHcjeMvjbUydFanl23wFuJ13hfgkYdBXtNrxaSt\nfQ2wug2M6MQZ8LhIeDolTyOeFbfDfZr9KloIeBY60JcyThg7h+hUrjlexvX5p4/wAOyoozpTb14A\n3OQzyJB212FMJeQAqnzivRM5H/t6TNkZrmxyjJTSlKPFRGtJdPFq1OZo+SZ/ZcKDkVQra1pLTfVx\ngKvuQ5DrxsRbmWk2tXvvcjR9HlO9vsgBi8YwwLCUxiES+kSly+QCcDhQFrS4uuPvLBGlvNE+qypT\ngNhoqT5omTrutTCsodH/r8ZtHzu3ac+KUWaTnS+hBl68l7C2gSpYQ6ev9MiWDfgnwp5sVu5nE8mx\n/U1k3lBrVRDp9HQQHl31eYMlRA3YYGNrlERa8KNRy7BB2gnqSNvg7MZ9cLRLXzEwCxLvZ6FXGOPe\nZXOZRvZhBE3/rbYcXAGolgMBq3L0GogQoVwXjOP/Lp9G+YCCsvJPmlulYpyi+yL+t+3uDrkkGXBz\nyt4LZK+9Dxtt7sz7kojNmhRi8l322KZWUTrqrFsga4uAsnQUKGIvCHECsDVus3trG/Jw28NdLhJw\n5SB/UCFRmQiSNOgu7qMbv3CQvsDdh/F4f/p8UrR7zs2QpCCdAz6fyUSM2uMtAQuhzOOWSZoKkXBX\nkZivZ0cYdpBM54ggQukKYW+MZVAUpOnpOijtNEcfDonhsxh90B+mGMDLpLKrNMMk2raR+Ny9dwWL\n0RbCeq1i2L0QhPIWQfauSL4/637GKz4Gl/3Ql/pJYnN++tJA97AWcEusf5A2KkfoIlhecxBFff7i\njP7PdcVbCIUdDlBMgJXA8euhybHk2g1d/aXCoF5kMYl2/C571d+hgTyNMflnd2zyt94wxzp+G34y\n+TypwKOOTT6pfy9RtUcbhcPfmgXvMf8Pn+/Bt0jh+piQn1/lcF5Ru651dmZLDUTz2Nn3CGSpbEoa\nvuBhGmfuyWALsHZS8ReZJh9h5NWtIpst5hylDs25wYVWBovObmtsbRMZ2CxXijcFbjN2VNytXc3a\nwXTc3oJMksMhk6Zsm6Wst37x5XW7WKeyI1kASTtx5wYMVAlmJ4w410QgFt4t4YJffV1TE+/5jWbX\n3uJv2SoKj3A4tU/v7pE1CSfzlR5Qj+rbRX9mVviCtSDJw4RPbVjLXz763BZNlTd8F9lqUIgojNYJ\na0Zg/6nSctDAuSTC6E0yLPxYjihPW73Xb9l6hSt5NBHgtC1c11/1isoAhmXbzJ0Ih/fsjIeH9DSO\nyVMpNCmjZKq0TH3dNIFdgK7RpcWxOfQjpBuRG3SEOQcaOnDRnsuyV6nPH3TsjkNBxRmus4+glAtc\n68WnBSyhO088MDCHcPrALvTOR4dipQjiQqcondvi/P12bArUHKz4tqLVM3lU6+HhhSZYsOJTWN0A\n8RWMHDIQpSsmI9QSecrSUHxzcXSgiLUzY5wAXwrwboMWZkKLil+3N9nKyBADythgfBmZPUSDiQ8p\nw0q8G1W+1NllU6qrVMax5xl6CQ7aPgAiKi073hmkvsfwNHhftDbwm4tJpbkpuiZCpuS9IYL9wXyN\nrQxkh2bIfkvEbpbjICECrZBPlb1HraWomc+Q7wB5+YyswRmsRFXJsttqDJuMYopK+i/Tt8fV8+QU\nRq5autg/hBEFm2dIH2sP68TDZTxPnb2fdiz8spru4WgcWTtMolhJtscqX1WN3U5TwKLVlbkmdihj\nFzq9FPZyevKYPmuVCx5FFImmbQV4u3cbBBJzBEi9iqgQWLR9dXEnqqRSGObmQd3s/4GEg18NOv/u\nFDNInYQbZa2h0PwRJTZFdyT/oZJnbMOOwJ8VV9Yw1nNR/6KTSHUDXp+MZQ84nd3Ib65KrPaPWjeM\n7aQ+YnbtIO8lCbcYqm4KZyQbqKg2cSBa8S3P2HJvhkhOz8ysiWwhFZKWV1YhcCHhR7MHmBUWwt5f\n1doPV4dmbeOMOr5+7SGJTVc2KWinUXPty0/cZBmTRBTJsI4SQGa+gNWJyDnUHJmwCiPWNU1Ybk8D\nMB5hDek1P++XUjly8XN2aznRewYffk+gQ6dv9Gd+urPvQ71lH2nKbnstVGKJxpvLXjREEEPeyy9W\n1/K335OAbTryL/VzgzGLfcmIoZ/rg5EHdis7EHWS4Z9YiNh5LMJJiTsA7JepDVzWWzCrBDbhlNGC\nQW7bsWvSTKb5DeCx32RIrR8+9sALeo20aiBUXHStCKGfzB2Ea1gqf2l5cHKa5UF3ew7K5umkH9J3\nXy12TjJssr5K+z/fBZhEvP7A1xF9rV+hBWU2DhXAN3rPMKb86dj37STlx0e4WlaVe1behb7sI69n\nF65/LgnjQQNcZPPfnRkK1ZqcS/FsrRCPj9gbQwBUjLeQ2CTxCD9gAL29J460Gryv8V52h8QwL7Wp\nX2yTMG0i980DlF1kVZWgrJz0ARaKPigRYBHzCKBklRYLwTHfrFDB5GKJ09pZ/WIrksaemNTjq2Wz\n8RfVF3bbOCH8Ez2gqiP4vTWlWy7ravKcbm1hlf8yL7OWUuDN3qXTCPIsyNkea+OprKEb1V9c1vVB\nGoIKJJzsHCSAuDP9OrqVQjbldGq3iVxbtqTFOz/H+Q5evaZT4ePMeoyV9xc0qxx+wwc8SjRkXsY2\ngUSIWaCqGEm6gZBPpLmW3+u8dUpx+GYT7vE+gm/TmN0UfVNydTj+xiT5iQWlb9a5qfoeDZCxUNef\nCUt96bxV7dMu+d7CeHzpw0yqVEgxeIL+LzeddTXZ8IdMIvNSTlY3IpxTrasT+xqSapwhmUXeq5WZ\ne9hpm04afULBOn+fQMlNlUWaq5I+NKj2vWPQKqW/4hKGpZXR524D9j+XkQr913EBtmfUawhAjhvN\n1LH87k76gyNo0aoBgZVvI0FjRLeTZPZ+uQU5dGkSPFeLC6MHq1PfWZiig8vXxLlHXxtt8QgMIRBh\niVQqO7l4zqS/RuGG3+CJhmRuWZQDUUv9mt5glJlzECar5GeLnqk39n6YPzYUIL89SJ87FvICeXnO\nOYm4+xpKUY8YyRLoI1x74uJebj4QJQQERvouZbI2qqoUx3sDefDjCU0aKPOiyM2VP3E0c0QYF3SA\nXloTlVOL/V6d9pdettTOWHGomQpM65vkBotrUMDIm4Kg/03FicoVVsJ8hytsfj6d95zm2qR2K4LN\nTxr066pIJymcV/utnFICE4Wx/wesfoo9RqaDKrYDPskGmAVvbUtW4BBk7bQRhn9xmqJg1cmg+WqC\nq9y7J8ivw89IADCWu0HqXU9/rpOwuoBtPW5vYSTSgwhcpqqsclTxtGemkg3YDxzSkS8MqJIoZVXR\nyZL/lPiizAvCPTD+8svK2jNdvSX1sLBTncvEFWE8/xNenAGTxkjPO74Q845lu3pL+NQLR7+uUAIK\n9ajzwvr//+Udx2T/xhFFY+q9J9V6HyU/ANDnnOifo/kLNC22wKNRDR2V5z70IdlxjA0uUXkU5Pvt\n0dsOBEJbfmnJxdSN5dNhFFZ+5k2hGPNj3g27AkiMC88K0BxAy34kkGVtpVNXH8PM3gsiTs9DD3Sr\ngMs9OumlKLBNBOfBLstlAQPTQIV6JzsK1q45xzQ/r+6vh/1p2tnzaMjEt8jVDOG66jhVlU+ZefiB\nppMEiULy4t30RjCNWyuYx7r+FcsLlH7f4BG4why86ciFSa68t974eQGHTsDmiWI41osjm+oGQvXr\n5Kybws5ceQP47XQClLgoiOCtl3Rm0Kzhrpribo7m4YoeYG/JKhJIBPu2kX9pXmq2xexb5BbrHu0H\nLsIfPCsFW5+xh81L1i8ilygAaHYYdKbRe3kl+s9h0EzEN9RKuWchLRm4v0g6AHpxzfQtTVFedPAA\nXNHcaaXnnkDQf7QKMflNsFsOu0RzzmIzpDCd0aZ8icVA9/JXWCx3hOcCxO9a5VfRzWop1NUb0qDq\n3yL8qJ6aSvCNx7F3ZsQXrHhouM01r5/GFgjkgzJQs1hf+AbaDi4aog8pBS0ZFzQPLmPe3d+CQK6t\n0SBcfjJFp1hJF3stBzcp1IDJtN66rDgUV0e5/6E2jqLMj7t+k14qLU9YJxO+wPz36NmAKFl87K8s\nKleAT/bcGlsDAsYEUewBdbmid4fjrVBWHaY17I/crfviiWkJ3PJFPBxMjnxbz3jAsQAQ3ebM0eqU\ndP44I6osOfbc/LEgEVzNjB/MAuxLVba1gFgRrvcGi9WMUyKNgIwo4oyKP9kNk+oJ08TIEkI6ypS6\nq02apDtw1pafX1wGr3f/l0E9noRU2QKEw8XRJKY0GRo626q92FVyqy9McN9auU62xSYZzV2ENT0d\n8zMRXSuPfc6k2wBCZZe3fpu9MoDZ1clFm+1OiJUY85UAEaYlACjuDcbeMiJCW+vmF4QQ7fgaS+Pe\n+Jaosfs1R3P2+wsQNe0C3jCStCn12zT27mMQhONS/kP9EfQMYaIGwCr9IoJ0DvVAoHHNpS4M/9Ak\nxWXQj4SXcVjffpbZnrhX8gbawaJfQqCV3aWdpzia9Tit3QRiuaKD+85IsPrRZEtHEiZRCszFocVi\nWCJHROY+i/ewpdWO53AmSAM4ohn/vb9AwCftusuyGU7WTlftQGy5Lqn+BvdaXhlbsLoj0LT9bFWS\n4SGJLRDJVF6ZDV5sVLBDr29JfyxP4z3iDtorbLvQ3Jje0ddJAaS6XMsYDJDtuDCTFhr6JIczx1Ry\nay+xdHEQ6oa8dvFmc8ewwH8lSMaRed/JtEZ1O+25EzBt+qGlkF8dZg/zYKQwj9877M3XFqbmPAFj\nyik8/e1bIlXeeOVlfCqhevZBQ0mfvzsPijOdmKqBePOwOK8yPTtQ+0EiFsGFRjNovxZ3c/73pYGg\nnaVbFE2Bik3DwnE3VsUrQ/aT4AfQV8FSnRflVlcdxHqInvzzosA0uEYlBeBgmpszh2WHwFzx/p2o\neX63zUXRfrihqSEg5DwmbPBdRBO1aJ7v6ZlGdMLYJWHOEZYCRHFiJKMdLEo8MvUqBAlWWWIwzC0X\nkKRl9yHPXx9iD7bHzZKVXv645aCLQAtwK+1hX8/pYx2ogKr1COlTnWKvyC+2Ts8FvUQ1WqcBDwNm\nXAbHiCTKR2Komh35BhQpIIdufLeJ50brxLeePeFzT77dRBExpA43OmmdrgOj7OJbFMyUXfJDFNc7\nqLtibMNcWqBJptnziS/cdhhYgzrcH4ulSU4vqGXYZXxK6WzwRa/ZTDybX0nq2IF5NhibD+g7p7Bq\n0Y0iyuZdKPy1PJo2rlamRQ2BfbKtISnrZnKlLd1oxapfTGousVJ1DtD0kles+QtM/Eo8DGGPozrx\nmz/3Y5ggKl8OGZtLwq32a2nKisZLsgYjnO9pw3lXDK2vddPVmsSOVRfsVlqhCpHRbl7d6WEBO2l1\nxVWRSjBGC2q2zK9qRYb78J0zQKGJvB3No8Z89+xFftIgjsw34qGWO0LpC1dwB4EATuIKbRT/9qOz\n7cMJzY+QoJ/NxXJ2XLvUhedA5TIoJw0jNsameuikdR7Xh/pxQvJnizDxn9o7cfMP9AKV5KzCzdWr\nWoF5uXCZpIEXweDi/4ZC+27x4jsDzOFY83EfTUk+YPKCClUcCP1KzZY35SGPme5CFkI7G/i81OGC\n1w3mhWE+3dK2SqT+e2Vy5xA5NuSgRnniYvH/8wTxhVwy4c/i72Hx9uO0jY/6MlpmzBKVvzMnXh6I\nlzWY8GS4nqcMFxuYVpg9I/4ROvT36kntn4FThkSmf7oFHCbw3gPeDF15PjTEj99VXQegYkNEygdG\nWbor9xaVXaZAGqT35RDu1CwqjWVEgTh6cRyaw1t1dl6hqxYF69kKdZ9vVXsw+uoKbh0bqijacnIV\nP3M5uuvQIaAU8GYu7pD2Fa1qSLBjJC33RY/M1M2kl3UwpNyCMQNtFp10RsQP1CFVDRdWW+v8GwEF\nZ4UFR148ddBHtiv/0mY88ET2F5k590BThenIwYmJ3yN4rr4ZaAPuk1W6pUaRRE+V4OzmEb3p778r\nMa/L4ZuYjA47R3zyVf2cXcZKS5klhHfXbxUe7NU6By1P9plvZ2Rt9MA2vFyzzTLzPvdn2oQ93/F0\nAc1UiEZ7NAC20VNplvgEQkCY0Wpaaijkh81IDeSErjLwkg5N35qCKKfy/UCzON3q/xIIfry5aLO+\nwnVGB6E3jx5hkYbDfeRXsZmGX1SngmeeL7Mw2uCzE0ZF+PpBzfihDASoN0e5UDZJBOyEsQ6eB7yS\nb/KVr8USuiya2TlVtqcSmqYTZjN3wAssB4Sjfn+nBNNyx6cGmEF1hazr7JZ7pe0DVaZjiR4D/y6G\nIUbTmrkUj4mg7VGIjbDTOya66g8vkJavE3leVLH7A+Zv48qUJR4P2damE98Yvp9RBW8jieGk5x/e\nVOSsQHQjcBYU2Qv/YDOtbiCGQD1H0bcrc1W0LCDzQT2N0EDprBycPMz+JoN7lztOtPQVDJZWIuMJ\nrREgdiiqf2crVv5VfBWukCPl22MXrurqd5hyFudvxcZZ3VZu26TXPEhWLjmtzinGUpOrGZmoUR8I\nsuYBrAMF13xjDhuK2kpbMHexkLdIUk9XQ9o1elC/OPT1DeGGUPOWIj3BSwhafp1T/IzVlx4lr2sk\naLbm7/gKQQbTwunzOBpRbm3mS7MWWdzkA6Q9uAp1/fmNfws4knqj12rNZ/oKOAg6eunZ3AGHcEpK\ncVZxTZ7voVXLrnMxfFDg/iS8g9ysKfeb9BZJcj5EgmeV1blLOz4t5lsNN35P5MIEQzipI/Xe1H69\nchOoiPtKyC17qNQMUM7nGPBk5kGfITCoEJHMZnzb3PyqghtvXllwKOf8gc5J4BYOKgLY+J9osqGY\nVzP83I06J6X+S0YnyDInYsOAyHCJxItdlajiXYHJcC4LyBzPE2NjFgu2PbZKDu2E8O5j/EpJlb4s\nry+t055JEroxb2tCu3n6bwimiyRybussiu7OR7gFiOEWiNZINUngh5E83G93sQE+VdHWPlpo5WXr\nBTOWKDfViNm8jFEsLFkHrsmWhyFF2FLtOkXY1ClXh2KuJGNhF9JfwSsEoaVgAUONaqFJzz0tEKWv\nkr0Rj+nV3Cs/qWw+gJtHkX5Ln2FfYURYOkKfbeaEeQsk/HsfcJ7MISvUrjPvoAl2Sp7dx4fOglGu\naEA2K9nx+kcNB+y3VlShrPF/zC80abl2nXax5oxxLKr59qK3LiqxGYNlroAK2lhntjaIm/MN/dke\nobLPvMCATBu58pKeKiOiAwBxScxr366owAZHN5Dm3XzS6d5q4+bqxK3aEpcqJ9+QGv63Mzetwz91\nxRCEUbCeuN5KwAeeaLQgDqM5FZCw/SNrwPFpzXYIkt8A3KLms4UCOdhvHDvPLOeSbG/Usb1wf8n/\nBkmiJkAIPN56OhQZH31uArgIFmZvVa8v4GOpFHVuTk76RY/pNo+vIhbE1aGHyzC1ZjmvdlQVz4gL\nCGA5Pe0tVKQZJzt7tUwCSRfB9UDEOQfbPYtH04FE77qSUSXyqS9GCQeb0lHX6+9rD21OYymfamTa\ny3mQYvEajojk5LOgNgvRDvamDtmzjezQ4la91Kg3thy0amc9t9A1h39zbdIux2QVQZlvW9oWn9us\noiG2gFdEc9vl0YPTdkZy1Z86anqK0GP+4y731EnDUy8sFXF8wwqQvYovFBLD5jsW7kRDocCPP/jU\nW9TwuRBydI/EaxwzFeNXxYDOeKC9go09CAoB4jEbxCysaxzYaIaviASwPXY0lcFSZqHjVwieTLiW\n+52naLi8UlKXX5Wk88IXiiO78+XWcU8pYYvz9rXGU8Gpv4hd/aG8x/T2wSG4aN/GcJjwx75IsCDP\njCAd6gQK4icFnR4MeYSOog0jLnruZO1aICqgHrFKVvz79RWZA1pQ/Gb2Qk0BNAxOtuE1K00MDQjP\nu1o5rsa0CnvlyEcNpZKOocn6k+4x7eA+rSZfz85Xy1G7gPxbnfgK8dfGre8Fa5FA4kTPJhCucNop\nhVfavXantqjtKIQerOLo6XDlM3m9ZfZQ1JvfSey86sQAzVOwzB09OYhRr1dBNBInKXpJV2zfENpX\nL/w79oHUMVaGIZwdWUxRi2x5BgdFv++rwnP7WV6i5V0nqEZRq3I6CTaALZbJ5/x+9urw4DrwKJPb\npj4IFVDGerspwcqUExG1iNFVUeIaUcd/QnGi/HDg04QhkdPqNmPQOA+UZwCDP5qBR39VvNbuwnUj\nOeOLccNbQoPDs5RmZk1dX0Fk2D5d2/bjuzRz655Fml3s7MsifinmkDci4s33/jyEr305losfrw8r\n2GuDjVl/oTyHuW5j+TK8y5gWxELKIE5E6NUTGYdDFppKsOJHvM27w/o0NuZQHs2tRczDkCPyI1y2\nymKxBGv//8V54Ch0dBUZtxv7Vb6kvvZ/Mz97GwxnsP6s3Z4ZGj3JeNkBqt/9DKdhjs3lVFXx3DSv\n6yaVPmeIXIHdhUU9Znnd4cXb/s5j9mQ8tjx58ypBskENDaL3syx6Pvqr1MgDWznrFqdkSLP59NAF\nKjmer1gPRNqgiaqZgkoCLMbFLT8qTVeWbFAfZhdKRfnEPiaG6ujInKrPuKRvpUmOY3jjKidFqrKC\nfNwSVqi3zoeQvi/V3pJs0YhvBWhvYKeMe91soJVd9lwzwtPBsFGJqzf9afgqN1k/D1zG0ix60ynZ\n9wuiBPPS6rOD0vL6L1vtMRWxU6mOQwK2/UjiANzeZNYlbE8RyFEkEXvSiq3oWm+MwRGLVob4y+fA\nH5S2UX5ufhpJ5cvdI+9fBu3JxigjwlFJtiQQWgZdRo1CQbYYaHQjxzycMLVSQE6JOcfYU94LIU5A\nUwT5TTAoTnC+JxulWJRvpj96KqNlJWaHG1Ahtt+bdSYEoS0CofPlHNxBWQbnzFAX3tnT/mYenXeA\nrt69v7ba3bOXdxxjDvh/AgP0cOf2SxqZGhzOTN4oaU++tHGD/ZVu8Kqu4Yp5zb8ZfAlyNkdHRjJN\ncCtrui6fCn+FtTM5x5quWiRDt7fUjbYh7In0xZUCiMnWjeEfn9pJlPf0GA2PXSeQqD8HYOS+NJCB\nVHXyiq5JUpxvZft8LWpkdbZfzZGkO6kVF1aN92WicGRMUgMJWVBphunFYS/+VEmoDKHBszfZ0OWx\n++9mzAJAUFqjNysjPCKk6hsLm/dpEOa0KtDDDpvNwPWSi/xX/B3y0jwzR1FrjP/lz8ar+crM+f9R\nen07LQf2OROO/mIQ+XdSdOWr1DSV7T8i+3Hz9S2ZEc10AlymMBKSZRnR0hiHA4CglfovnTplE5AJ\nZGZbMWLNQpuyWUfbgtspI6YfBZLOepJC+hf5M2vBpQZXjwH38+jTJKI7otrnOYWG6t6N4KEYf1eX\nIL58KbvMNkBgjjS2SZczbaB9qkMWatxSO9ADhEPs50Uj5zd38HZvlu3gJn1KBGCSRoWqNej2TdE0\nXvghOC1um1JVFDU7UP711bsaJZh36hLZchPOrplvkOyfBfLoJU0jlR561QncrLIqkDh+HKRX3CZp\n2GazvKjH4bflVhfpj0kgrxrKFNLcwrJ1Y6ql0LDQS0sKMHK9Tf1CWL4djp0uMwihRe0IYd6T09Xl\n/QDa6gsDep1NPv3aUkH6/IG21MuINGV5jMLWi8x3wlltqhgCQmXvSqHyt5IDDVrWVL3QStonFx7m\nnJwCEZHf64lSt7hxTcOw9V48EDLP4+TaNwoLUJwaeFfTv3ckVHH+NR2c5I6a+AbEqKAkuAxu/l/v\nofUDsTeEG6nSe9CgdMbS5kCkXqQRs9NGyNq/187I/367uoCgKFjQMKXOAWrB5pIhyWGIT0/ZUs2e\nutKYwlNxqeB1fOmmgg9CSnjWrXY04r7GKEefoEzuj2iZllmBdbnD/UpG3qYpf3PA0beA5gMPGcvF\ncdDLXs1OJwJgPQSVWCarOydXIwtbRmjK+ucsiz7DPXEnuH6VPKk+7pqs6dJnK3HaUnPL2/LFl8i3\nSEAumdaHma1MYyG3SLg7jLZnP3O+3MSUV1uCPLaJJqzWBpXSPEgsxKQv/UNnBBByo55IMuaYLEGg\n3qPUdgrBvQmMwlo4DFbGz1YEPPtfU6o1mGylE0tQPS7bSE5sM3XWoygIMAQxnGitxpDrEYU4AZAh\n+PmTWzrEo9762fvKRN8+usz9LEvKMHEkN2WvKPP3j33ZAH6kBK2Ow6VO1XYj2HDq4hSjPQvD3SPP\nS3JBbTNONrukiXUy46HnG1ZAnnGQguHrHfoXqKpwbpWPh3pihdFcoIpuN93Ghntvl8/Uko3jRA7v\npoFys/qfsbQ/4UCex375jeKLFB9OmWLXMJxX472o8FW3UvMT5U59f3yXnab9eHnMgWcqqbuAcqCv\nCUPpsrrseXWpZAaJTJqoLaZv4/XoYDfm5dLSHx7slE7FhjuK7+rsyVRYunDvN02OnD2oEGTt0VMi\n6mpYaYorouGLulqh0jgRAz639HJepEbnVJLMUui39XjjnNFfTvwx4J+R50h5wZKUgNt3h9b6fb0T\nc30pJWD5+Xp4aKZKk6C4l5BSDXROl/1DcU+NjP7ieVtcRPAlMiUJ+Af98oorgLqEDlfS0O+N4CQP\nTLnDBNbyUDp6Ezyv88eYedhjzIWuZNOtZ8hbu5gkKkKRl3CBcq6RrmjPfsltfohZGAK4PBQ3tFMc\n+V8qsTQVCbvMxu7E+HIDSBaByvCAHFuZYcZoQ4bLs5NJZXImOiybpCZ8LLgJ1tbvipFl+EK/AKBx\nN2gpnBHt7RepFV7165a24YW5ATpqNwS5M2JEOD+bH0KcAu8t2X0VaK/BVcbg+zpOKCicmaDlZVNu\nNaaAP3OyHATcotesbGqrDRjTT+om2NYRkCbwiuDTw+qk4k6KE3kUKYhdUbJmYvD0ypLFYZuv+Rvh\nyb9fzlnio4X26iYiMroRHxLbdwNfrm/4LvTMV48bXwtHAAQ16w0jrcsn+LDjb/IC7elnbMCxZWSf\nt5snRDRrswymXWZTNrzD8jCknbQiUKuMkJY1KLuum5pw30u6FSc0gyqiLHUrl/5SMO0sgRHkamSS\nQIldFfzniIIKJ+noXgkBwHV5UjR1BP7dKv3jvMmv0/0+EpyzhtZplR4Akv8LQbjI3wrlR3LCg7Dw\n/jZp0VEDDx8OcXnpNXVpRmcceW/1jjyGMEsOhDgabjMcB6cWcz0FcaKXouG1gCpdGUT2gTB5+HuC\n3cOcgDw06nuVMSeQOfkiwIAnzsYL90Kxs3HcoHQTBcdFweeUxTm/iCH3jl9fSq9QtlcypQIZwfbP\nLFllg3R2yDYGkMtmL9BwKc+FjsqCvacSS3VkXtJJWZL6xHcJJGtvVXtPJRHsvlumDm8dp2p0TGPw\nisHENGqigWE4HYZZT7JfiJ3Ogcqjn624frTNo5XBUTyiZQg7aNY4Vnq+INKmT1Y+GY3kIuGn7UT3\ne2EzeMB0X8opb3paDeCUt/IYsyQdaos7c09JBWzp5mO0gIgBsDQdOdv5QGSLcZCCyOf0nDIP7rjj\n4ihTQ9sEt6yYwLpeyaFSQTiXi890tj1FHeaKisit3LXZexWjlKR9ku3Xgp+2XRuZah1C08VucvLb\nl19t3oGzcXXo34M7/iaerIB5aA5EsCPH4ii8E39sn32oCrspYZ5MXx13Tm827SmknLcT7f+FKgGz\n4v6xOlvawEA1JB08y7Th3uBx28Wld3iH94X+PMIiTZY6mmjPs/V6au79xE4Erw1O0DPysWPrX0IP\n2BcJZPWsC3oBGHjfVUw3WBmqOXIx7uqv+3tMYwYdCTP0Cw9MT4g90vqozVwBZSuEA5gsGEHIau+h\nLMiRia23cQL21ucEq8Qh3xEuiIzAHzf5hO2Zu6T61mAm2jI5nRCZbe+6T2KkkpBuJ5foWeyf5JEh\nyl+MSeiI8XbgsdRpzJ/lc7Czyk4ol2PFkNt4M3698gektRaP4zSrJ2je4QRjxRdYmEoYME5N3/SS\nEnc3oQ8I8Z1fRvtxMw4XqgwmWepIYwBGPS/qZzvm8pZOpkdTEGaqTJ2sMdBV2hl5OgYCNlPbWBCo\nG6qQAxQ5B930QwYB/ruPP+FlUlWTw01qRqRhLDQifY8V6fdPr81wKtfjeyg0zD1EqCZcHf+9tHvO\nOJcSqpOD0nJyIahCZM0KkiBJ9i2ac0D0tsuKKI/kQ8VJtWkUn3v/1ZxSj+hYNBpwsAJf01qqWS2z\nL4jhyPbj9NdNtEOxX9wgieAhwHPOFjnBKSUTI9wak+i14zO1pCYAwxzSSBhZDVi3S8S2gGuhrj4L\nYAVVAbS+hjyyM9/2jI5YOc7KWI8vZVZqanuI452tQ8Vlf9yxgmA8U/ET/rLVkJWxlWpiRqJn7l7J\nEATcsGXQqPimbkGgD09pGGuzOWJJi6dKRJc7weJyxIM5pPW5Lf3Mc/41fU2C2X03qBuT0D7RNNdY\nv3vyaCJnwDuH4akfW6VZWc0EiSoXgTuxIz4taQWcqAZgtOQYuGGHzAR/awKzUX3rbKXc2qkAB4K2\ni065jfcMK6hhwAZSFMBpypSz7ZiNmcUWtskGGNmFYN/RZ/9d7UG+q9AmkQd0VLu5Ps/UIbmSCc9A\nh/JyeqqH4sOk2cPfAMRbwxXaCDiwnbWvxpowktBw4CGxQJ7xL1Kj9hybInCvP7tebUCzMflFj9YG\nHBztCvEYvabM7o/0G8fzzNndRaK5CdLRDCQ1NnJyANHN07BAWqahQMJplvgjInTnO8kIta8MU9WN\nAct7VFGlc/A5NbjTet7NLI2MxQi1nuKymcwLGBbXIGL+rckDV2Z+gkCH7pgUjMXqdREmgeggpZJW\ntZr1B00qcBtUys7PBSjpqKeQvyDl0vf788FdmjA6Jm5R2U4Lmd0IHGn4xPylAHBaFbb2y+QZugFb\n0ylWI3rSBcW3D4u3SSJeAWNcuV8bv7/ltvQUawU9EjjufYxgg+Jqb2NdFuVh7mkz4TWKwGTgD3cs\nyxJ/jWJ64AfrGQIQS9vlfz/6A7TEYl1Ji4eMIu69IVBAAI/rs0tRc76k0BGB7Qt/7xH3D3jpciKh\nLfusb6fxNeGLMQKg4xh9gMvz5eK+0AIawE4xUEz3SqlCvHtmzKBo4Jc112/nptJA6RUX3OvJff5e\nFvvMToeoL04gkZff5nUYwTzKRy9m/tPFhvoI4YOpO5vNTW7NHG3ddtSD6dxq4xaNdXPxKbKhIP77\nj1ESsJFcfZFP06IWlmcLtzbczDQn3jXh1TGyXhcQ0SxQMgzz4z27JN2MrXXuc3EqCtXqH+JNe5bl\n9O9IUK6Pw1YxF+dLjmJJr4wwWxtJ5D+ZLLob95ZWLsvuCK0HvBEF+7zFq6OmLGdN6Sv8nLivtRap\nfVOtbFP+WitWeYYqnAMpqqzO6WnURtV13OFnOz3ozpii8haM0G1ecWB9SC387zdcEEMyWqkosG1P\nyITsBffO4ANNZiigL8jMLSUys0Wit2KK89EFead1KYEuVfKKGXuH0SUJxyf13ETTbF528tutFRsI\ngYSSFGuTihStp3cKIKDGa1AgKNsYaX75X0eDpAhtxhj4xoX3Vcgyu3oQnuH2WDzX7Ym42g/yg/QB\nv0T4kIs9Mbk4JoVfPPXL5sfowzwlEEFP3bUgyWuwOrPt4JLBEyCQoO5uTKh1Pqp5P8+0eVSIp+Ze\nhmLAZ/wM/eUnwkeq/NmRUV71zhOTx6Pc6WA2ugb8bpUtFKackVQ9NqatdKN0pom1aS9txdFwqCkP\nxT3t/1a0MHNf0kXb1LPpOMhkZv9uwfg/+gx/F1yqHlVOe6AWWRUweJVqqwiHpn0TxgxNGNkYpeIe\nkkdrFPzq0hlKgM+Hr4HjvVvt/zwoJiUC2/xbm8waFX/P1R5xT+dZZFEWsyLJaQzGVgEZREN1n4Fk\nsnOpSpM14mTEJkvSTPSYI4lGE7etATmQrEK8a7OaTRaSposDoIoeCLc6EmRqbwmD8IwhMLVebJhY\nPNOuL0Pcem2Fw/Cy0yMYqsCWvFn1M+sTHT2+y77he78tfz7zRA+ijzMCaQoU6Pc5qYKoNDHK2ff3\nieJt2jUeiKbjU6Fzzykae3nUT2KMP04OVhFM37WPGmAptGMoTbh6WMRPsJNh488uQgZw23PKaCXh\n/hlzltRWzeWYnU/oMzbWQvcnt1RcqKWOwk7t/BJsV0zb8yuhOr8NeeTqqZmXSuckHvFb5J0HO+8J\na3nh0UX5XH0yBfIsrbjio616E8HQ4fYfVs4LOftn6LdNQ0wrX7wOw5cun2NRNsJkFCp89ZkCnutF\nWWfCcT8X8PjoPQlBGWraPK6RzDvVJhtYIZoj8IHiwE2tpVneePFcqISBlZIl38Xu0CP1A3CmyMcq\nPeNxKC06bTHcWnHVd8+kjGoNjugX9TP3BxZ+hN5k6+kmoEWAN6n1y6bVthFXXCaKtvU/rI1PWFyQ\nCwXDNash/YOt8afMmGm2z8niRl08td41iBVzIsmXq4JAglvgPR7gwUqAAEVoKF9Fb+hpwOsv5qv0\nfZ4TbMhuf4Hxiw0RkBN+syqmxsGBO3IuFY6tYr9XpwvXaEIDNepj06jh7KTJx26WNgGdMzF5yHxY\nIuszxtKiejxAnTe379isIJT4Pr1PA42tYrstLs7zj2JegW3d8dOSB8oHanUE2lAyAkQaYhwDTI3N\nhLUqmF8ShsQAcgG8dIjMGM0AE3KGGzTk92SQtygIsa+nU+vHunemxBI4C2MgwgV+NBpaoZeQHoAc\n3cwE0B3lB0uPLnh6KJ7lVyPxe7+6FOf62NfZzChn/z1OE8noa7U9ebCA9lK8Yu07/yZzXi3lSl4M\nwa7wlrXuMRJDN3Fzf0xjUZT4kX/or5g8G6knQc2417bKzfNsF7si1in3KUa4W+V8Q5P4Hy0XTfD8\nHsPGvfWvuEjG9qpjgjbQvldQMEk6mSFb0dzQgxjZELolERpatlUbXXPs7PD95/8aknLvUsjlKYyA\nf/CMnSQX0QkR35tHkD3W0iLJSr4DtezZ6ct8K6krP4uH2Yn50KZno8bmJQaiJfL0uS+HKpgDf0Uy\njZPjdrDr+x80cxIpIe1+VSiEXnV2uq5BOz4A8959xITYm8UyXABbzPXj1Swi2yK8iKzpIw/Ff+Ey\nmLXpZAln6/PcXz1kRbu+Xb8CgO7kVivOJuQkyIEm1odTPohJuWxVsApdBEB3kDeOzPmWVfQ7Mr3k\nThnBBPycGuAGhj3uHV2fSvtMwh/lK/MBXqfteUvcuUBgPMuPttG6iL1bjhjsg4MV27mhtZ414oOq\n4rPAjiglxL5RdbMgHx1i0dXjTYOmN3mabk3ph77DbmyK6sYfzxTDll4wFlWJOEAnH77l0nk1YfM1\nJ8N8xyFAA3CmO2ie2gauaj9yJPZsLwXoiwx+4Q8dRodg8WmXsSkOWCW1AIYLbnG6EfJCJ0xaBK0C\nkkvdCHkxqTIS/0LKHEQ1D1kiqCW+gS4bgnbw+2Wi3Tt8icZziZFrG9AtWZNjJXbtPHaqxLFpJGCx\n1BdDrlhIKm/OMW7LSxMkYPHHkkY0IPiI22Xq4MPjW3SjKhWRRKchnydwLympY8Z8iGaIxMiwcPGk\ncSWFL9I+ULM9CBqyS0eRie9cgAo+LApBSL7IhaiRV1h1Bnhp2gtPDwlEIMq9UQ6s6n/XAu2CbIX0\nI0NEkXJh1Vfj9teC6lT6AsWykaz4hcXjpfLo0UW1o7bP4vo5rlfZqASVhmMTchjLD4BrnYxC0Mb2\nBnw9KhGg2F8vdHO1LuwAdiJCNwooix63G7Gcuxl/bT38qV3XMD2Etx0dUv/sNw/o0I6+aDtZ0fVD\njgHj7pbgyaBBAqa7O+liSyj0wrXWzE0NyEaoZsNmxfyusrQ0ncyzwHUogt8QEGszsxFcC+gpc2FK\nHzD3OJIKby3G1xh5KMDsOYrqyhT04Ey1lNcTL7NCtqt/xqUyt+lkUVwCFUwutOxoVOY1WEURmFkf\nSDufX6samDjBIG+hrp87h6klEHWlSXM07u5sobZYXzwyUS6Xphm+Ac9Vudc2coznXsrf3C01VN7K\nTlX/J5VX5eyhimCUAMbuCUU9myorYQ+99yVOoGkEshpvvbr/edOTm7CSo9E4SxsiHTYtBTJ+yJtA\nJi+AQPm1FDr0+icU+neI0jpOrVZ99BKBhGNyo+skAX7AMh35uGEDJb58WBM6NKLoQiKNqaDujSD/\n4C4ZBsszLoB9R9OwPJBWg/kNvl+W626JBVkmOZ0wy2KWFiho3XTu4h/bms20QpLDxWgpxWke8/0R\nxpt9fms/SDbYDu+y1qKcv1KGn/ltK2ax7PKg90v68PF18G4izswKaXL3aQvWGBbKWzrzt0O6Srww\nOW7lEyknLYUBXzCc3UOYDIB/HZLizRak3xaeyK5zQH7efb9qU7naw4VNWso0HkmL7GBCBBA2wQPt\n8UONZ8rNQX3rNMdr9bI7d4QbH8Wgo2AoDATIm+fnY7RTau9hFg5u+SRCHG6jbu0D4Eog1HOIvSt6\ndJeTDuCDhBh+DbUJYgb4X9XHZOVDMuoubzvFeyJ2WKpvF7NQU0tRBKnV/d3wCZtfCm0GiFIFTF+J\n2Oj8ZmHpk/+JdSe7tQ7BYAmRBwcEJrih+muViCQBeueXDaqsTnl1w7gOgnYeAcftRxvBHzhoR9Ka\nh8w5YS73tphvmJKbRTZUYq9AsUZ/lyzyQjSCIJUV9xlEgP5ORmQNOF/GXwjgtDJlDxA9Rx9B6XLh\nRv3JfQbIYCpLYje3OkDktkgZQR/CkjMdlP8k0JQCVzM83l9XiclNArDTchR9sVTJaBw+LrB4/Z7t\ngbuhDmbmMXNshgOICHxp3AFRYCmvWEmHRsVlJkktwqONVUqj6lQ3AuJwxln1zYDaF0ldlicyuhdC\nrsvYE1cXKnuY9tIMDtPuIGKbNSIDtCVcrXp9igJBGE35/6ac4ULFxFxv4CaI+EYe53Cz+9cSlVmy\nIuphGp2CTM+3uDt3Cj1oGpvY3sJIKggef2vPjCxT9QjNpUhiu6EP0WwYw0F4G7uJkEpCGqguOQfU\nI5iF4gd9BEN2nABt3pWVKvowBkT2PI9AR0GuBFNKnDelpMxgJmmf5VDp72K2JKT6kh2F2xYm7etv\nhFTtASdLNdg3JSRIFTiJM6oWO00gSf1RX4DBDRB2zUmqrwl03JS4VUlNbmADB/xh96i8HaVFqcRF\nC+sG8XqQA94kX0pizyXoRsrAVjk7dP1vMhg4L05zseMMSOZVD8Fm1hvYY8+6d7BdNelc8yN3oId9\nU+9si5NnMZopLEX4BxTcHt99yJz+i3HaF3KQ9LaOQDkpmxWxPuLNCn+HfOM+Ok/tGUg3xQZvXru1\n8ua90lys5DTnwmiO72TCBnmYlgoNki9txQ+S+1PjuRPLhTtVPrIL/iMSYAmzvi1ByOGOLeQ/8I7s\nI05yO65pJNSMeb/B0vRiRZEIYoVGSCcBoWdAGYHgXqIBsXFnNJomvHDczHdXv67ssx+Q3HPJJ/bE\nnfxWOLsIxr+Hj+4pagzJBkEjn6FId+/BXozmmIaQO5hMJEDPNu4exDc8rIuopKy8ef6r80ky9W0E\nyBx4xRw1K5aK3asxS9GplnTQobBcWsaSLv9Ot9HcoCXs2vFH2wmAcxRV0PnwVgId+Bw9XjeoIhkj\nxln4/EqehqSNt4BpoWyMKPcvhiONg1pKxpZY9M9I/zR0bfKtiVaFPMvWELR2gOynYYAH6dqVxeZt\nhks72UWvzRxvR8f7V7u0OgvJ4diejuLLDVscdltQr+vY1QQthnzFlSFnvrDrgsOrPe9zyBpwEjOO\nEAkhp8c6CghDs6SPyo+HwFBJSxSRR6L8IVFin/FGJEW+kYdat0O/F6x6edpIYTV10vYANb66gu9S\nCuLbRwwz1OpKquqcOoXXioc/HpJu16+QhCY75YKdx537X6AcLxvp17Q2vCt+xl1DsEQJuAbpsUPl\nwGYT+qXydYs13PtzWV4168UFej3pQReAfLB6tk1mtzqaFSe8ktHtJj8vrdYJmU/qDCpEdmE4o1O2\nd/VDMwsHfxsgUu9NsZLBRtkQQrg2U3GySROPBxTj1AJzirUHrNDiGCYTZw/RZAh3BSNplKZ9rCXw\nRXjJ9WxpibqeKaR5HFZQbDAoEX34ZET9ONx079lDd4AYrb0X+cU3dbphqeATV1cRK+pf54gLr1cB\naIJEj8dLCohF9WgfRFeDGPx9smlv39WDD2t1IDyGVvkA3Kk5wE/2SePlpX+Wa9cn0dLYp3e2wc2J\nIHb3u+URLgxb+ZeHveVDKp39iKZdeh+csGPOqJqF+KhTgR99X65OSBN7FK2HzdpQUCkPDIsDx36o\nOulc7vqxBIUyUGqUaIlK+MG5+P2pUN14djL6O5gyjcw0+0B3fq2oO+i0EDGltvpap7LDw/MKPsVj\nnbrt6jVDiHe3EiOlssVz7ctl3pzgNL3LWoG82e/pweD1lCYaZmaqlWz6Lv/5107Ee05w+/Grnwik\nHca0gSSRnPO+RL0Qw2LiTMO5YphtFRvC76KelIooyv2iUEObprboOZfXio0bNe72fItChIyvAiH9\nqDrtfXA+VyMRj26J24FmBOwJxNZ3CBJpbczRZDvSC8I6Fl8mCAxrFsFZWHPTNfEYvSdTPPoxJqgJ\nIUjSa3RdbcbaSJJGiS0gOowr8xn1/tfXNF//EnZxxqZBE9M3mA4xIiKairCcQOxzT0yGB9PGyrG6\nyF6FN3lJn2+97aUaVIR9Uq5g35Qg0AetAgD0VbG1uC+TK+i3ErKWY72hwzKdH7vbVdDyld4mSe07\nnMtAXyGAdzXX65aIH9L0h5BRQeAgzWZ5juRz1v9pfM5pVOMAhaKbU+uCUww1iteBY9qFqHIfZ8QB\nqu6uzPkUAn2umhi+xGxD9dKvP93Z+BbHtpgj8wCjq38SevaUpKnceaHHvnKfzYsqwaDY1YqVCwx4\npxXn5SLaYLN39cfx1ECC7yUO3ZLXctxz1swHynm+xj9Mqj8FL0z+Yl0tejvWVKZXUj7lXXpwJoY8\nXOYBCst6yZLxkGTCqTUzzGlGhc/bmbcPSYcG0U5bM77y8RDkM5lUMo3OL4QO38Nz3bkPY9H+2kzc\nzwc10I793m617pwaADgotXHAeRXm12HMB5OmzPZ8B6eEyyPwxbpsEsRLBBXKBWmC0w9+rtRF0sE9\nToi3gBplDamYaYoNRDp4Hor51OfAA4fZsPbUryNF7u5/KzTMUsVeSYHIHwLJnpSm7CFEI/+EkZhC\ne72wNuD0wP27Bk9+IK0LrJYZeXowobd7eIxT19J9qkr+uMW+ef1MYY0HsjSdpLv4Ty/oOdEHhAp2\nypRD911MgvGzalg5zu3s9wRTPM1/To3ExuVj0vp7cPMrW8lQpbBdTz/eFY81Uay7RZKZHKwH9pVA\n1/IP9/hMHVfdi9WRHYGjSX1xcUbgrBUcGfS7AZeLipHFfKYhL2rXQBIkXy4bln7PWv991tynPOTF\nJWj7mpV4hX0PdbmCXrJUNQOOluBCG3o/PYLrmoxFQ/BYHyIKTwP0SvgOwSVNhDib011J0PZ6xWg7\nyOAoBmcN+yKeyNMEPIbQ7gnVk8alnUi/ton6SVRdYAyJAxegAxqLubVKGHGvbkuL/7PgL1Fjqcwd\nDGhEhvvIJWlvaJUSVNPiakDxsq1SyoCfm3Stx2mFa35jgOCcTknuq51vMWgECAlV2wk5QeAkAMIu\nnNYq6BipX5MIVrZCwy1uEpJV4HJv+X1qBDTfqKmtQe8GDxiMYN1LRgZRFgu1R+IglmquR97e3S1W\n5LGqDEFt6qTMg2/EC1Si2uSuFLSsu3xYNFOKLhEx4fme1S22hAv8jmCFUF2CsXmUYyvkWKGfqvCa\nnBZ60r508d8//NYMFGevyYXN7SVZrIgkJRR1MLPIlL69gxs8VVj/ioyj4tCzlSJ2bgo/aWuzHg9s\n62tYwr8QqpfE881U+GTAZcDS/GvIU/pJSEfolvBGdEYjEjf8DbcNjb+3rAe3/c7U9DfEENxBqnz3\n4X1EmqWV9dO0EQF9oUHOmJvtE9156KgOBQFqfOWLgtCOUSa+JEPkU1WI/bUlQo6eXJxsC9GCY62W\nrZaP/Xyf6ksY58hnqc9QrRRfL47ROJfuFKqxc8/Ifa5LhwX/0oDVOKVS+KAt9EMpsEER9B9IaMeM\nqH3VcgBhnZQ2rzTDD4VCJMEhFpthnIn+kTUHCrkjys0G9zKC750FJyOZDrpeHDGj/HsPqnBptqO1\nOilfL5dpim4aZkhM62invXIildkyDgb7oNBGL80SiGLStfK4Pm47bRlFRdJsFNLT1gZNiTeTSYfz\nZqrL0/pl//yK7hxMtu1MO2CoM4CK1rrqtvPoKSKNkW61p7c++ZYsml1FLNTpSuxNp1E5g1fpm22e\n0thRXur3wf1sZou1K8Vjxr0g4rUQwWoM1gyU2AmTCpmXQzOekB7hrvfQpX063pF5AIBKbJ8y2/gh\n+lfZ7cQF3pGPsGdJxejBylnYMlb8alEVpks+1+SGW4bYOpeRm274NiB5BxHuTVsSoKixNvlKVuma\nKdPQRtj59Zvraz+Uw11FNMg4m/qcbM0xF6IpFvXziqsNYEy/76FvF7caCIppqh0P/fI3VFKpXbzw\nQkmY6RXaqqJMJfk6lRAaeyZQpW4uz/HPuW09OjMFRIn4xSvIUqHhfNpc7/Y6O6Y77MVYM2mz4uxQ\n/S6aBqM9XKZg8obNa44P8sSNI50nEWtgv0G1fhki4QQcywkTudqWXQA7dJYAWT4QdbBK/CjvxJ9R\nmBFTMhon+ly8tzg0Fh2aA5D0Uk6Nqfx5GU5tf+dseB2GfbIwuXiZ4EqdRfwJACBZ+cgut4hXXDcb\nn9ZQyHrqcTzApebBohfpGAh+dH6X0Y406G129v1ntQEnpWxroGhvudoWhEe1RZrh+CUwmf526u4w\nM3AGVzQpqgQbSk3qspE8/pdNdvnL6YJHc58FOzuXUiitscnFHgLgQVfXbQYz/6tWWGszrxZhmUga\nUUC/KMKSucMuX79MBRJUU257YbwtQPr+/NRhcwWorjTiFlnpPxufcYEsCJvaFbd7zzziNNnlM8AZ\njjf+4vW5m5LkC0cM/ors2e57Lzclw2rlLv6cQgmTJdYZZnHzmydFxmGtgu+iJp2qQyuKWONF72Vn\ngGHPOMdn6rwPNYOeP966Wsul0uR2bV1mImRsZRIXC8aS6QZ3Hj/POvxRgnIcB+zpkO8/khafmwSF\nuha64tQ+uFwsXXuLZFPVlX4ZRI1gO/m3Oy0Ee2wLiPWEYUK8g6eyYXVK6bjoQ5w0SxyS52sUOHb4\n04sqVbAUgU0sv4KR2yinPwQDFGAo9/qd8GF+exxOyB/AXZd9bQIgyqKO2MgQwR2O1laVaT7BuHY7\nG1QjXt/bZg/BJBCoOgczjj+vpeoM7LWGJZsIgtR4z7SowKxPxhpTTuOL/SbYggWdpPCYHkhEhnTl\noq3Bvj5CMwHpnbEszIFO6hyQkjcOmxbquCuSGL5L4WtA7zX4VXzRhEv+ybbEMRWBSODmmkRe4rE3\nQmTBDkxsb+4m9aJVSULUFGUwGmHsm5VV7cmImO160DN6wZotG/AUCfDovDqRN6wn4pvkXHbiUsEd\n+d9HTRjOHOtOR61GFmjt9kSYyS7PTNT66S04BQisRky9SfICVD+QLXWjk8ugkqBODrOYLDuTPmm7\nJER3/t/ZoIBZDWmBF57BFYy+MA4dWJFjPfY+xQFDDvv6ll8WSAaZuo6X0ECAwVVHXUro78VVVQ11\nVjxgbP+P4OhLKjZAf+yCpGksgp9jJR2ilOsAMartaCBe13WntHuXBaon/A6e4bx4KUAsVE2DeCeK\nxgUqpBYAON9N5l7zMgdHR873vDs1yfcJ6q7aUrSpwAbtfQeuyB5h2xeFTyKC4BI1ltM5CtYLfc/d\n/bqJC7G5MZPBLOH3zYJtriASBMR4WOPQrJ9NWxS+CI7YAcCADObr8xRRlO2U/fhU3mifJhnXdDwM\nMsQ6l8T+Le7naI+zFz83RvDyXG8ENktHT8n/5rwrlhtljWJAteVeG/AF2cf6Xj4wiVxKi8QcH93Q\ncQM+jBeUFkA9hgL11lJqdii8uKfBgnknET6qTksr3HGFBz1zmJKrBDZdYpj0+lYNnwisv1vuFkbT\ne/GgP94qjBOpVSaHbaIamt+WPgJPh3i9+ixjAdTshsQxR955LNTQ6//8jSfQLW57WFYkPWuzVPmm\nty6/QJMaylKZCZmXhrIF6EiRwgTRUaWd8NnMuWq9xlmx1/Zb/GazRGtdZrkxl9ExBo8CVgHYJvd2\n5mGvtaydfns0t2T6gOn2bK+janniiGAcCvOuKSWJ080Y3zFDsShJ/GRXIRggSvHJL2B0xn6vxWi+\n7CBj9dirrssKbDygkQfZjZnrIUb3pGVubgrcJWdc3iLDSK6wHP/sd5PFUdmQCFY6FtbOzzGCiXWP\n8e7Ka9skPDxi+/ZrBkn+oEE8816XGtRA/4PHNUdLFiyjO3qqGn1tOp3pvQWHmxPuYRJfeRGESfEX\nVxPp5bySGY11bTKgydUsMfyR/g/xIX/EvZqgs3ewdUiwlKsrvL5L/r2rdVd7jWKhi1vjmrILsEVb\nNUdixIk2ctGVgISfVKZ5rDuaSnf9WqaLlbJ9TK2LlB1nLf8YYgPe6DsCy4Ge2QA9nQQDxvPrqFiV\nm0VEJBzjvX4gG7CmYA/XY9V8LkiSWiNRVXvdRdTrumW1wRp+36b84SsRRMdPRTsGzU4/UEFnjFuR\nOjbcf7k2J5Fp9dDw7vgg1YMCS6lWvhQu5A3xp23Xn7iRaky7x7MLQWOZSqcCeq271FVf7R3FI8x8\nlnipAltY/zLmS8LRUDhR1lJkbIAnKc6Pwi15/DDDVVtMdIG83II0ytPQp9HEC79bCC/reO/tt3Il\nu4fkAFaWd7cpUr38E245dqH3PDLGtrVzF+h9GvJ93yUtAiGuXMTJ0zFXqcx9oWxl57KHNlu+cfQS\n6WZB9qU7SiGH1Daf48S6w6XqVeKVxUonduYooQR/gzmhzedQtSXMdLHckkGKBLVkVzbGdqbf5uRL\nBVZxWM1010UuEN9EB0RP0tteAuGUqhqKJzjuA3oqeDGnk0bdzydMy0L9T8MRzy7HJngPXoPASHoo\n6y8hMwYHvbP3jOd4YSlQ8MEpqMNBvPo/E8aE0zmWkZAa0hyyoGDeNTpMk6cj+5vIsHYR5nNQSUEi\nSF1ndu5UMpGP5vaXnGnzezmn115poTZovBmfnO1WaBCya2Sre/Q+em1+5P5GSv30sxW7GLuJrhlj\nAigWUndqFKae08ljiCJrz2iylzMS/cKEY9sv/xmq4+dNFjgZ5bk7jBRhizV5RHEIbrxolQ304AXt\nfhbi53XbI6/K1f+7XGvsXs84Ak+wfljy6VFPXajp6MaQxVesa6Zm5vqeQKRYjHJgrZQw5qshMTVz\nftpszcOOZIberlVsggiyACplUxY3mgGOuJLUiCYKsK+NkS+DRf/G3WIR4g5zVBZLbkzrWsjmg9P+\n2NJnz0TgfEypRJidjVFb5uSCvA3TgKl8r4ig/sUiX74Q9LaxOB6Sr+qChDLmAwWfyC9NCFZt/FFQ\nOHMSYj0mmIHxp78H0u0JD8YvTtaExAgzc7vs3my+nW4hogn7nScCXRxs5QadSbuuZxj56FXezV28\nz2h5QMxrTI/l4AQ28NlaHooEZScD5WDpEQRxYIME6O1+ByUJO3UC29+UKTW3uWIeTYx2ToFa6Io8\nYs8A/7oMGMiZHwC2DGnWa5t1S868X2yruJjx0ELTh0VnOZIIaAxVIRWN+cHGQaDOGPihckpUCwff\njsghlSQVGkLeFFoCxmz/DQCZXJVb4JhplG4o9+WrJV9c5w7NtwE2Lcwt0FhEKpnBJMfN6RHweEtR\nPPixFGRe0/q5fiKHA3wsWv5W5nTqdxQpfZ2eyiN8xPJ8qX4lg5UQZsQIggIhiwbu/K0JAOAzSuyo\nTKAHTbBT6O6Co74si81hSV0PLuEdile06Zbv68sACqmnK6vtMejasRoS2ALUSsMJjxAktZTX8900\nV0JXNuuOMbu+z3CrwDNbLnUvh4o/bkqqHKZZvPVWBaL4Nwdg5s0V1y8WVhNOfHo/i1SLXAtm7dz5\nidnV5CIdl6uvIC53wvANRfEyNsYr0TbQppWeleHyiHqhP1dbjBYP/5GXtpgPapY4njAhOK1r5FVC\nWPJ14ahgDNxZG2rkW+MKJyw+E0R8rVHTzMrCAZXG/80gyO0VHff1PTpeQrFnrGqZjf9N02XgEFWL\nvuHUpqBmwpG4+bVU/cH828wqhLGSt2lEGHaIaRUe1cvWloOda3rdLIC+r3YuMzFJKNjF0CsVBZKV\nbIMblTP9jViEkGUoFJF6iaat7t8waskwHtpb680uATQBROQ6eknG6+Us9o5A5g5tbKolHHqDtqUx\nV4PqCdE/o6Jw3vyfy1Xg7Ah5d3vuWUNFpkguU0af/51I/cuMPM3VOJfr3m25x3x4XmNbHIkf3ja1\nwTgIe8gQINkNXbp8QZefFQKgS6CAZ9KdK3FSImwePseJCMTfg6CNzI5TxlUNsP5ZBJaeJfK+WwQ5\nf1/IJbXzrZlbfC2AiIWj7PYdN/Kw1hKe0FTU1RNyolT1QO4y3McYyzQkZRSmN4hBo6wxLSC5HuOy\n7t4XTNbYU3SGtoeFXw7hn5IRYeyq86lLks5dZSssWWR6H5OHlcM4zEFc53U4mQlp1Dzpp5yJFkOL\n9zIMrVBbUEvQQSKgqNf+mqRntL4gpoE18V4nzo/x7EDYiha36edl7AJP1FX9t1w1RGDwHfK8Uytd\nmf4foSmFjXMJtCj21CzqUo/SjG6+XtLcOkrivRIcLAoME7fVEn3/XQ1oFTZ/s2+6KstqJjaCoHdg\ngmkEE6/wHGjQsTdYQjRkjsCzn9ctx76RPkBuWgt5E6EmeQNb8Lf4l4igjjRWrFtLApd9TaorftUI\nAQ/YyOs6mFOKZlq7mOAxZUpz26bWFyRN5P0WFx/h0Vpjr86Omn9Rss9nMqZeBhLaPhhKXXlElhoH\nMIWW6f+4Lxs4heYjFF/eB7OAmFyoifROc3X7Nw2jVb8DpQUSMWy5cbKywMt8EwkB0HpZo5zuO7qS\nnuVeZIVSjrXftQh2lPC/t7PPX0xILkxWGj2Gig2ojdVRCIMSWv8gAlcgqjwHHneNf3QCjb5yAnDM\nEJSY4zCckEqVgIUSNpYn3kTJYk04lNCge3LpTSHbWkSH0tskvVSFNGxkuJdFtInodqM+BLmpwWJU\n9opTL5JZYxVfxJEqV267Biyzhc+fY9QK3SDI3i8HWChndh/2ELlYNcddvnWNCwZExseTFo1uqjhJ\nU9/FD8INJMqZNXWyBKeNsjzw6lb908YwxaKkZPfEC138yfuyBnWNW0jh3DDwBqm8hEzLgVLcS74L\nPY4xpg0hi60eCPTwo9LFLHBk+4+h1YtbezKYbbbqjvBiz+6ssJUJNokU5oRJjN/R7u4BAitOMUBR\ns7+2SoEhW11k/7WoGHSV3E6/M4ikeQS9wNUCqSo9uco/N0mBrDPA6tqBAih+Vl0Q4W1q7suTld6/\n856x0etS3gBny2doKouibRIIIj8exU2Wgs0I2/FQz7MocDiCh5M1UE71Z0zuygjBgDwOUxDTZpKR\nv/xXAFErhDA7BqqobZO0l+XNYmW3ew8JBSkZ3S4nq8s4Rjxo9I7trlb3vRDBb+W6B82kcFvzspsq\n3kSY9kDyc4az7ZWHd8BDhlTptmjD+6BV0v+ugW/lBWDEirWRhmzPxXoozs1XF7X8BqeFSg5b1YUX\nbgaQfl/HbR6Ip/GasKAiK0ASSMrU2arqOPfKgc0TipjX0bQKM0uR561Ao7+ShOnOhVRqftUai9KM\nFN5S32Dn/huZYNR1WTp4Z70yDkkOsq6mPlGPufNof+mlKKKAzYq8dahfx1eFVb9/iRuAY3WER6L+\nYeVHR07Zxrzir9pzm7LiSr/uKkCiXUayZJZQZSkCiwua4kHhqwQs3cTi2mbyxSq4CtpPkhosbqqT\n4wraFGGm7j0llIFZ3gNnkcJ9nTY9m8KLVZIQ9elep3py9/cQabl+QtRmplXlko3PpGXHQt+V9J8n\nuF0cMSmH2eImRdcWMXdxsL7bYcGFGi3F0Me5x+1pMEJpyC0+036+cl3lgk0pk4Us9fM4BRsbi7Gx\n0/rzhDZ5YOYlk24Tm7dM4uQmCPdJUx+TggbPfDAGN9WLjJJxs01elMV+teR1Jfx36lQY2AnYs4EU\nXqN2ZKXsH6hOP63tPVnYNw9Ro6zMZ0rw3w4OV55BqQ8xUypQP6EtVE/BqWDjpbqsPG1WXdUCbvfe\nGkYKrjOcqwQ3GasBoOOcZe/328GFidi4mME8DlQ/Y0DyPvPzf7sO2Vkcoze93Nft1MxiyIkIwedp\nWtxFw3Rcx1O5Npg6Xq0O8n4+UPGJv6D5DtsMrbtxOgetRd/6c3En3rGOlYmlCOijeKjVJp0U2i3a\ngt5tSUd5RXlMyC7Zh5tiJq+r6BZXyHQ42pdvRJXdpswDTXuVwTJQRZpxxttX87t9X+KhL5N3378D\nZpcTWRaodpVOJlsIqM3vT7Gqh5cB4gZYOcI3eIa3CBCGjn40m/IykE2P5QWrVOEo7ZDuniUDrpVY\nYSSZVzPMhut13IZahcT0Hneou7w8B2OjGoE4ycBuO3gRb8lzyWWdE8GKpvCkF4I+bPBvvqltsfYG\nKWn7rBXJXHhF78Leobclf436dwL5Hu+xk3aWFZMtKFNCV+gYuahsJhFRRGWMkcHD+EOHH0zyPAfw\nXWcD1T4hf32OCxElfnaLhgCNS9j7D+81NZrNE59dcAGrIz9LBlGRgwzi4bMYKCUghfnKEpg4a2LP\nEazYkwfd7dkQm3Q97KlaA7siVnU3F2XiET1GiDicE+YBK/gssq8EwIWfQJ3CRxX/BbwASM53DcpP\nSblWFwx4n85HVxQNTNELwHub0rPfsOF8MsMwYRNQE3fjUe+1Te1rteBBrfAz2ZbZHE06yPyZb/yP\nUU3biFOnqhRcYnNtDwZ7YpCqdfTvey0pX3Pc0O1C2ZX/TxlBzVrCL0r4mDVh2/cPgjqvxWaQNmGJ\nEYDFQ1eUIMZQ63RjITHu91SwSBmg8hx6KEvCHVTMnPn/RGgThghn/IOclL0JfiRedoYaae88M1Z6\nlQof5PuPGTlIp7ZtTPf/Qgtl/mSf5HN3cPh6xMQ7Pd/3mJ4aVJsMN+YVhdR9D7V3NB9/MM9fQ0at\nz+x1kZjJbV51kOv45N+sJRH6O4H3WVbDqqTmisGUaRpNNdus6usUiueWfYHoMsOepSbVrNsdt9zt\ntwAkKByDTYnV9jxTlOsE3AFQVwnggwECnCtx2LBXfTrtEHeMHN807NrzkCSzMHU1tefyDxy+E7Ui\no+vYzoimF58zEcgbf3P1ETgN1s9FC3dSCotc8EIz2/VtedAxy374/HUKLCCKZ3xQSqmk/lVx5NYh\nG75UGypaaO71r+omYhRHuPzlzagJvihlTJ2fWajEr4m472cKQyLXCtZnodm+Q0WwUGqkVUKViiWr\nW1vKOr1/0iT5s1czkSY1B0b42ouTNP0lDsxzeGchBazBaNZ6cInzmuv1Vm1BGtzUzsIHVWYx2Un/\n9YAQAFc8vGTW4I+1DpQynb5yY4ll8cT4x6NlX+khZYe3rLDmsGNb7K5KdOvkA1DqNbFF2Q9U8NkE\nBvcVCMz96WyU50OXVB/S9TJY4hfGRn5mSWVoNgLAUyWmx/vIh+b7V9ePvkHSxMREw/ZtlWPz1SrE\nnSfBco2T7L0RFAfLQfI5AbXfDjSHiYUIAMAIP8qS23f31VCiU93zp3qrwUh818z4Sd5oyv+4SMP9\nOJOlxwJKe/6yZ+Tw7KVV7f3FD57I/Hd/GLEoCqvdEmehxPuuaWw7mck/6+2e3sanCANHr2Lro22S\nFg3zuWTL39+oRp/kg27zvdr8EYDUaJ/5X9P1xbHztv7L/52VeJ3d6FF/r/nusfWlKd0VXoeGE83S\nFbMs6dmdoTqHEzeSA0dCedPwiW0ath+wvqoLd+IjFbTEgSsy6Z/BfoCj9R/C96Fmahhs5GX5TmNH\nNxOrXUqKTt5pPn5+rcUGoh6nXkUFvIXb2pw7537yy1d0+RUkABhasEgEZeTcwAPr0a06hA0JmTIv\nu/kXdo2VJzWNzPULXjAHf3hXXQRHtrlo8GF7sylH+558q/ivCIPpFVgNToR/0oYnIR0b6zS8U/VT\n7VBIrDloRaI7xs4YKroVYvl2e5fJ2aneTtYfcmW5C23bMsQB7IF/zQVZDjEQdkc2DWgNY2SXdbT8\naBCA6tKWWMPuPw0mtJqnOc273PqPIkCpSJVer5KI3QI5g3jXUCAWI5MdHE3kIlmFl548++pHUjky\n+FGW0oKpup42QvRmw/sTTuzIVRwKFtlqth0EGhqTJQ96YlX9hmFp1Qz1hZOhN1gFHQksJiHgVWIH\n/lD8gwKrf0OrRbZXx3KqjvznfPQ40slqrXB+rUntroaH0n3zWdSaS/ZRaLBAkWc7ZmkPbVjYeVVG\nW1rrcNLFRYcqRR6HioZIzA0tGOoPOI9MB0rEZ1VfGlZMG2s5fL/xaxRRZ1lcVm8yMZ5J7qizo+0b\nD8jyswWoiGojFgKO0VEcBRoikci/usTH8if8/RmM2Xd36uRbV+1JL6p/R73opGtkAgEiUqjrXTbf\nbeOcezT6Xk3/pReIeXXbRsLoNNxMz4FuFbo3MNX9JKRKl1uvaNBoJ9cX7PZzeW1K0/gGBsuPSjOK\nK0eIFGsXjzvI2enm/rJx2dKp8646oOB2IfJVne+DPhx6QCMSSEWbt7yYdk+dOMrIq7vCu2jkwXGE\nEfQvCPkG5C6hXddVZRoh2vNXV3sBgnWMFO/GqpdCZzEeILO9CBgzUSnyxcurlbg6MioORBTrR2dE\nUcAdl2igI3Eq3r/t870+uptqm/riTF2q7nBn/5aZSidgGIQ2WI0AFLzGTiWPPVLui7xrthzYnqUM\nepM/jILZJwCIFSQNvEv98+ILhlItUWOLEGV5EHWjsoviR04ktIsPZ11JgymGFHkUYSP26RG9lIaM\nyzpRmbasNzoPDZ7jhIOzX6LY4WWry2bD1Io2k+prkmelMpgH9hBjIXMuvsmkinNVK7PgQ828ioRG\nedL5sIEp/nVXmvmDuvzRwKRZqJhBdIRIXbRGl5qNP6fXQxUkCyje+p/HD4F5UHj+NF8QM0bOFY3q\nM1HtqB6YZlJK6zI94hkBCiP4ewsYHxygKbnbbvLBFgeKGxbfaI7Rbxjj6gITnEjdBo90AIg5jhYZ\nQhjGbChdtEc/S+toNgVibqbRn8lefOpGniiyIWwxqc6I3DDpaCjG5O9+5mEoyV2iTF3CRSSw67dW\nK02hTnn7rgKPErYIqVMmr/ayz+/yNZ/o4QiyPeYnDEhbR3qyFjb9X5zFTdEzmAlsfvkgbw1m6R38\nQfCXPzOxm/jI0GLN6OYXxaVvdVBCyo9i5Tx8Yf6b/lLI7m9VJ+NoYFsr8eZr962FgipqP5Fwe4/N\nORVIsDRhsIFlFeSnug+34W/4+RBkvcMrVIgVhvwwgyA0Fh/j3Wz1VFTGhjXlZoMCwFdZlugE71cz\nXG1Oieemi6TKyGEnN7DzPdb/vOwOgbLSOvfTvTyWUd9YcxACULDp4/2QvcqC6PoP97DP+AKVkDqg\njRdnuPrBh0xZKKuxAPRnjkpsJnnD/TJEc4GubL0/j95+k7oJoIUOezO/5tLi+RxhKIoZerG8MpT6\nZahyka/GNUDo0ACc8c4vHp0mvM5usdDf8WVebGbuCZI2kdpWxovq8KGFf4r5YiwNcnNmR2lvInx1\nT+muDULXukc2w4sw8Fv7EQ8/bHQpNUWJzk/Re+qqrmeSe/oLgo0gzdVundYRq/IOQ94VvUUMkGRB\nsEloCnF5sEYZszEBhhO5fVpCnpJHjqbyM2eXCwCc8WD/XNNYYETUk0XYD1jb0TB3WuXvHtjzm5W2\nHvtZG1QRMMgitcaOZ030BITCiZYVlAkPjDtSL2q0N4sQsi0WkkHaRLKjx+rLqYRf0sDmuYknwhVX\nBXoEXIZwYtcRgAyTRc5+fH3ThBhncSdcIJFtC/Hssg0QWi08i+hgqkBF5YpkXgqp4oC7YmjD8gst\n6X6KCHV38k0DH3urYbRBLYvo/YhiRQBbP+jcDepTd1M0L50/V0RmPiubrkuqMsZ53AYCpid52E+G\nKurzEpN8zp1u/vr1BWuEUdzm2x+3i2fMkaldeYLLx4WS0X204EWpdCGqvz6dNe0635yqejkpPIGw\nbZjNo7DErx8ufmmjpHnS9pVPiIwSIYhyFtcWZKtx6AGp5EccXhB74ZMHLIUp6wKGQkCSzdllvzXn\nPtRMmvGXAGaR5W1TbuWYezU7jr4R3sHWDYAWaCkO4FiBZGaZTfM7B7ej4VJOjVOinxMl2N8M9sCW\nxsQ4pU5Y7HJRI0D5sMC0zC72nxEZJg8+/6nyCpgWr4/URd3w1G2Wqd7SAQeeMlGDTCTSYfhRJ/4H\nCMnQDIkOKwTd55/4twdRJXgC/O/GmV1vDvBvc9qjjOT71EfSzVtcBBuzmxR7Zk0l0zLz01O2ZBvw\nA0zKfvYI242OA8VxUyeA79hJeIwAFKtZ9aKSCcl6cn+FQHvxhyJeNByHPu8A3PjdWNmKrKaki7ec\nmg2t+Yn2T6yslAQESXyCjoDJ3Prlj4EqgGQ2ZslTH+V2u5pGvvXrUNlmQGtiGeKd+rJNmL01ROgJ\nlW5RcXtOrSguWPjRPFByVNgUIlbq7CV5RG1IVAQo4xWYRM494GH2dQDNzQnqCepUr8wDgYbECqQg\nUBJjfzBjBdrzHpMH6RanKhXGjdYNk817t1vbqTHNiJwBKE28MmL2quU2YF8xQXEcomajCb51qQEf\nJWl6mB7KLLu9Pze3WijW4n6IQHIRr/SCx/CqNmm5ZZqRzSp17dTBuUuMx7UeOOZeGU+ri7J7KWKh\nvj/FzxpDfvwviyN61743zsoNmnJK6rydTCX6MsFV2A7koIrXOfxoZ4bsO8jovpW8arSWSY6WLWzc\nsMahu7I0AlnWd72eVMiMXXUEZAM5rT6fefzRkyrlItFeluiscPRVZL/iBaJi9xTdO4w1cXXbTrBM\nYxCXLxEXBq6syfwNNyKouHfP3gmY9V0o8T53nhSsNgyQzVss5DaEoseqikHwSf7eQDRoP/mb/Iog\nVYkL8eN6xVaX4M9FhvugejQDrEDrsuSEc5YdzQLC+Fb3QE1Lmk2tPJIZFgxsNRWPUggbHHAVmYk4\n+qL2W36HPjFSWKSSoy6qSPegRb0rOEYeRqsOZljO0CMfyZ+ZhOKSL/5H1mDEEaejC4+5NauPCEuw\ns71y6AIAlmA1A9AyURN1xZSJZzmqXBssa3QzeLMSTXt10LboKKv2D+0XqRHigf3xv2grErbF0sS9\nMh7wzFZt6WWOEYJTJ19gd+07qsBAopgnXiJptbAnQ7yNaaDxI0AtNMTjL+qhm8Mtwn+LgdxfwqWg\nIAFpHqgPjb1wa3KgtSlm5Hqum4aIF2kS46G9EmCh9yCIVmyZkhb1AkyZU5MXCsBxJI/Hdyyoiw2h\n2dq1j3Qh7X2LB8QaxmXGbMdcJUCIrIUIQ78I999Nf2VCbOAXEigMF/Z92/g3d57Sm2gjKtKZwCFB\nHMOVXrt2ilbB6HLKaqjRWVFlIJPjbsiWq9EOfcHdf5XBdL6HujRXftzata7VTxihcZpBer6SUBDv\n5HjUdEp74yzRyYqOq6x/tPxQV4Kn30LWRZ5Xs/jPKBZm+IAotzbVhA0uuPJpwrvGXLVIZ73DjB11\np7pVJEGorzsXxpXVv7ghAotsVZaYJTInRAMCw65RMGveT3EJqddTFpuCnbJlAsFiAWhZEqf9mhBm\n8h6PMasTgZDmeyDLTXH/I3xjkKjFzipqhxTJ8Ce0fvv9AMzYm8Ed9NpNqI9AoKhjeZqus/dfJYep\npK7M+Nzc6hnfL+6BgVT7DulRkt+tODXv/9EkR2bsDnV7CMXQzJzpFMpmUDPrX8wshcBQAZQe2z8C\nTMpg30dRK25T1zt3krZefwm7XWLbD0M54CENpRBdmgYk4adBF0A8tGed+NPXH5/ptNu0hRO0Vqzh\np0GN0Pi3ltMbP1iDO251SlEsNxPynBJTJnrpQTRoJCI4RmhrFlNr83SXHqOii+IMLed5Ei1yA6cO\nIW7owIoWjhDLyBT1rDeCWRVHGKFO+/34OAAig00W6IWAs1wHXLvFumtck6aMHHbr0BwvV56tSQFC\nOBXgEKcecTuwVYL0av/EGZCqyNzpKbPkqDRJLKbMawG4A3rtBbDGP52Tu2NCxrfLZKB5kcOAxXPD\nfpTLwbb2SdtcVBfYVuPZ8M187Qn414UrSv7knH8vOZhKpClsOxkMwJYIykj/EgnLae5p3jSMc+/T\nu2y3kKmwo26urEg5xfj2aULlF60tcgztCexBomcB5r2FJQTXbUBvAnXhd91/yj3NiKNDaY6tN4Wf\nNyr/nyVqilQFzlv/C1EFMhAo0qbbEB7y8NICNr2E1dxJtss1hyKKhsxOoycYAMQX7nKKP/sCnj/r\n2+3LIeIeM7OLEQTDCs6fjShhDVp0v5lUgcZHsBfi6qW3WoT4DY92hZUTNbnE4nPQm6kc6/6GsfOr\nTfuUQdi1WrhETUsykFDCYzW5BqIVE6KSLOmRh1r30G58RZ8tBD5T8rVC4OigLyp3vL8gFY6c99Co\n/w4GmG2c5x4v6P4/4MIZpd84La44b8aa/lOtb6s9LEz6X3nGEBLjkaD2uY2DuVo2hlxyyZAimXWO\nrPP+OjuSRJDIAFgS0cw/NNUrVKYzWGJXLN1UQlolLeLCI3yOQlweyc0K0iTIKquB4hk9B/gBjma8\n/4Mk/SC4kXKNDVoOtMm4P8fuAebZixnb9s7rPZ0cQtTzlB2VsMt1m5Xi973l3ol5tE1hdv2FbkYq\njlhWaBNpahQJU4UWch3XTKtIl3whrvvtX2mFBAIC9ANBLJe14ek+2RdtK30ucQSIt2oxEksQKSKJ\n08x89u/XtTrU1ozmPs1xGcXGyGP1m55ppNtqsEcPfIGaweWcF2+IoT/So66KbBRgFay1885wQFeV\nhqo0dRtolmIi+rGfzTTKWeTN2vLfhW89t14rTa/VbdyD5woXZ/DeyzVMYbcth5Mj/mN6k5WfVpQJ\nm0w4P9XcmxiDXw/GOpqFGCM9kUcnlTxdL4W6b3zcC2TAstXz2gNPQnabMy8P0mxVxU7qKYJTv2hC\ntWKxG5mBM3HwycSSPNXO3m3y5C4fc5hUncJ6QcNSuMQMSaj6QqwN/4IDHfMPF4jAvd6u1GNf5k9C\nOqvu0uM55Uhxe4JUfzHJYB4XVHzO6ypI20jfIduBlfrPaLR8pusO8Db3FpuAUdI9BDZdE2IKyxtI\nNVwzuesedunS8VZTxZMfSJEYiTP5nZXjYbyFdsvg3oWJOVCzvyadCwVFqP0Zq5QnNE1w105Bg1jg\n+uFZpDzDIAdSsdNyjva98N229zUhmmMGCSPvtyW+f5QSWMJZiYjKIlCgxS1YyUsTqSNMeNNHdPf5\n9IBHCfdVRayTO5HojE6Ac7kIObEkRa4ej7Rm8IWs7V9A80M80RZhh6/Q9u9lqnzvglzfF2rZexS7\n4n8QZU41miyHjZqu4jjTiLj7vXuo/8sudQBsmAwefQBlz3Zs9Slbghcq4OokUDMiHJRh9Kp7h0HM\nt8XsznL91oNbD5FuMr93tiaJGqiEBbtJLazPv25l3tSdWCA7DhvCEKXjdONjQVQLoobPAh4czE1T\nSmpn/mwwgisRIsdmw5WJD23Oat8MEze2pNtqmPz8z20NZKniDilclTw0u2awqu7LmTki1zZlZxwM\nbshQo97hDiQNwDKrNyeKHSwuIE68texevSze2uZzrK2QFxtv965SAxh/kgczPVn/ikGmzkdyRJBI\n7N3QgCNscs9chn4qxASdklgden/IwpXF7HkMhPd1qJj3hFpVDbo0EMVixk8KQ/1rSO1DY9VZ/L0u\nDCOMWUPgYvQ+Q9B/YjAZDaxKKo70Oz13GeQn0a8CvlscdYRSs43NdxPohP95N/1sY6uVnMCY/6sz\nS9uWzCapHM94RBo9UyYwTzIBnI8GXXXvW08KE8weOcxtCKN5WSebAGsYlbOT1QBm7l/tuh3ZJJL8\nc3nvT0XsiryO+kxJuQLcVihMc0Twusml4UH/+0skGBow0OuuuB5sYdC9ZpMFuykKVBOpe032d/fO\nOuS1KMyOTHx3Fzb12DUIUqMN8x4dCI8PDwWBj6/hOmNrQg6LdbT5vvvqKFkpL68jgpNuevVVP1cQ\n9NvXncYgZEV3pZb/lUhziZgN3w8sfNTuT7Ku+8MqE4Xu61I0uwSSzVSywsOqTd8PneJS8RA0Avrt\nncNOgDonFgCtXb86ArmDlYADoFStA2xewxNj0oHWacFUjLsGuOypHv766l9o0FQS3DLa2SYc9q8l\n7XNfir8N98ZIGFG7Ll3/8kznCIXqrR3YiI6ZF3j4NkVmb0iUqOJGHXysNFaJapMht0ThguwFHG4q\n3Q3RGGUCXzT34lETJWMqvXMhHC1xxD70nGs/XEoawT+WcO5Phc9HU2HcbRusfyFn479cSeTXiSRK\nk2NpvY55vE28/aFK2xQz405MgGsMjb2t2RpW7sFMDjPqgm/sKw3fjUSlXGRR1TlfVDrJ4ObxBKYl\n8tAKWwVgKCTl0Z1KaEzepcr/y4GIRdMb8q/QTHsqRfOnOFUu5Jjc/BgbqJM1Ai/fqYjLG/mhuT+C\npN4NgZlZhK1r8Bkx5d9vc6w508mzweIuIUkHmGFYkjKqSyFqsY9zLa+hhzJYMqSXkxP1ZZywlGDb\nWt4M5/Mq0i/p4W4ETzDuljZ1PWZvVQiiIhkqBbCpYsIllqJ5fu+TA0o6MZHJmTAwzS1aAEJCQFi4\nTttqEcBUO4u+bbPw/saNjf5k+yT9uDXedGpaSGC52icvL59+sg63njorl1OzLVxyLUGR0DJtE7QA\ngmTBvMBr3/P3JDBsitRtkvmSxB4iWJduFCA6QjV8uh5WAA5ubSqPNhbNc5IfWZ5DVOGjmeWAleU2\nGnSpg7uF65WxhyK+15Kb9qRGwvKnuNnkaZwSGCUox1BEnVWuLUDY1By7J9cySsEFXpVYZGC+9kJl\nz+7uJckaSsLNMpeZP1sVaXNFs70x/IVcAKMAFLa1s726BQ6WDIRU3+38he9XmybdXWQdNIWThvlB\n6Myuh/qia4aTcV4ufk3ycSVkgTGfs+tEGegTfFljozjNBZu9bTCjKqhisQ03hqLvFlRRAmXy2SkI\nkwUUPwFAZ/rlwqekOQ3x7YidWpjufamE5Bv2JxrTgct17euM2FIwkgbESrnWvFrL2f35UOTnA0Qm\napVTkcGYu47nw8tZZJXPMsiX1SkGL+KWqlYcY7CTlk7atb7gZKjnoo7leWzMcHRFbJc4CWCHv/1B\ngrDSg1b4Futbyy4/enxRFPJ4bQWs/BUsYhlbGK7P6cw71RFoSjLBNZOuYsCGYOjAVEPgc/xOu/Xo\nw6FQD5sf93l89zBB3pi4S5kj0w3ghl7YHOA1xYEJbFbGCj+g3y4+KiuMsiLA0H0pBL2ayJCDsbno\nhDy63NkCQnnmJxt9gOBpjP1maSfYC53dMYcwDNpIFZ7DmG48ZF/ai6SDxgqfy/bbPQEXIPpWuruM\ny6id/tKIhUf2aYnLD9MQPDaSwrdxmysGxXI1WAKxwSkYHw0lQvQ9kcQqEk9ILi/TsihRVjose2qj\n81y3BetACczm6aIeOMzDVP3nHwPmQCzGso4bnYbHSqxxoEh59LPSKkrF9hPkx9fQiVjC00payhH2\n+jiXM4Pk3/1LyVFrZTACRTPG1/fHEqewgPaMnLJFb4jH1wq9m6lAWls6cCX8G8YlQ5QMkKpXnB/s\nJATEy2r/C280e+gAPKNiD+TSsK+ZutJiHdCyuwFCyJaTDb/X0SVPM6777ZkLnsRraQi6Vs6Q4A/2\nVrDbqv0lViPEJzR4pGg9Nv9A15oRbFxY6NsUEjxDz/7ny+PgNbeJUvb2pbrR9nYFOkr5EZAZz0AE\nhw+fSUpJiKUie5F+J1uIQWImm2VsaOogq/3D/trCwz3PDa+6qVMGIs9iKlqKlEb9tcnvrdmuFi8D\n/jy8DK1Jlrg7/AFIIelo1yidI4lrKi4CtJLSOBW9mO6O8G/S4d8UkyqWFP4gzSs4py45OkarTOCD\nS/VFy8Jq7tjjgovyJQzhH+9FcNY8f+v5r8B+NCkWNM5RrpYAEWcABeYkwzviuzUoqdrlXX+d5VmM\nXJMpE6cxhWvfJ9PXqV/cILAq8Nwhhe3Ty4JAA0imI+5lo7fJ04G88NkIlJnwb6THxdTtrhufQR5S\n5xU4owGdShLA9n0g3q18m3QHrDkluMeJ81XXB2CXOTHHaCUT6Nt+Flme/lAXHj74b5sWPueYdn9H\nYEAbTEAXj15BO4SIDLcLUf7ituInlup3V7c68IrXVhCbWiKLhFiucM7I974jruVIDiCI7qe/eZNF\n0WmL3jFQ0scAnqox9ZFlCcBPCNK2wRDBpicJi0Il5LHEA0MkLHSlQTniXOV+z2Ccg9I7ckOXGYSl\nXW0z8cQXJPM7yj0Trtdm1FL8Cdf8dRjQIiThCoFP/7gKHdHdabUDHUk/gjrJWFxmocoJjiSwUwA7\nOEAvSZ6hh8aBEmusnuvxZmYYlPYhh6Rxv2hIsIvyQwChxdXBirykz21I5X6saL+WN986mPOBKeWi\nxscqn6T8PkscoKrx8BJZ1T+JnmID1/Ycpm3vQFwBBBYmxFZD58RxQNLc4YRdIcJ8tvEuKYw9+vzZ\nieleDRRplnQQBzp9C2wVfVsfB1YZxKmO3U58fq8YIYI3S4ozE1CW3D1jGARHG/dnMu1f5/obS0cW\nzuzaNDNtxM64Foyqe1MclT6Y6dElRwV6A89O3Jd2wdc8WOXSVLjxlHZXIzdh4+Dm15fVQz2t1ltV\nh19DIxoo7kPPazuK8ru7Tg09pQssFscQqhQgagj/RqNwZlOAAI1NC7+OzUdBj5z/t9agO4Vl/2aG\nG8tY7ilpU7p7FrKbSlZbjS5EVzMPHzxKHKOYIpPpBGcRp5G/Lf+fd0h+JIyFx8cbhqGB9sWSpthN\nXIdCNf340qshaD9qzKIutS18kLP3FZ+bhnO0CMj36sr9ESKk5OPRs+RrPod0zIGwt9BqR/ASMbfC\nmRO5eyaf2AzarzO1ABimrMff/eJuq+MicVty6J1Rm2sxKoBBp4fc8oyuQ/r6C0s1b+UNco+xsWgX\ne7IxFPH8ITNBffslNYAvjRAMGPYtOfu6hd57u9AWD5l9/sKMM3lkjM74DRL129PijT3MkQIQd+p3\n2Lp0k48yOjLc2b2XyyQKyT8ftndoGHrnYvBiXws0e02J1+SuHodRysckDn2MQSpan7wXkNfO0TL2\nqroIDV1jDSHgVGTX5lHF8qxlK2VgM93CBw0FJwsuBfukSCVdQfBTCVobTsYQx274U0aq+XL16hzu\nEXu8BDa9nUmJkK+gfC7MWWh2B9re4Z1pO7rJ/9YWXB802yNWdk5ZBE2PwDMzpTI/zvJ8TSy54QcH\n0WKhlp555bRmVJkAU67JfdBy9RFSkqD1ZycTPzcNrNc8LybP0eLuDcJOyz5sLJ0p0HRn7M0gc9mW\n4NzdaCFQiQ3Z5qfG1OjriMfIJ/mpzpor+rtNFKM6Zxcl0urdHnhlbq+x60dzVdiT/2aCjQar/Nt6\ncCxEJv/EXEoAgWhZ/vdR1o+E4SbBu4LLkRbKQBmnl82QBK2eSr6bmMa/EzjHPbqmwPTroMvVfVNw\nyiE6AuKrbD2ax6WTAPz0y7Ird/3oZ26oNDCuAehL1yHzjtUtlKetEu4dYhESh/l6nC7NylG+DzSY\nXuDqKqkmk/rsDCn8ud/uRcoH/8pPM8UtWxg4e2hOH/X//lpfNsxnaHXRyoVtiNRz+QIwQasuzk8C\njddFAJrt8Eo0J0ZoU4+pd8CQu6G3H6b7q9JtyVLnt/1G4JwHf89m5/Nj5xeryUfw/csRdKy6qSmD\nmKVDNhtC3Y1kJmAuvOgIDEypEIZBUYtzkvRYquh+mw6VsPQJlc5Q7CTRvHeWKLPUCMggKOkAGyrJ\nr+xZ8Qm/69ICTHUU77cqhYcP8OKLJtJASUwV4xTA28I/ujT5MQIXYpJO+wLBHdo5ZyMfHOz96kSu\nBNVUIyrGH54aKlCMj7PJzaqh7l18fgcfJymNvGMphd0D1fBZRZ+OS0/MgLF1G/6YIuNyFYQqwlVo\nkhBU0+tI2w4v2Q9xO/Tk/qQO0vaZcjwADglBMob7yYEGTlCCOMiF5McUEPxXgt19V/ZiSlTrzRbk\nYoLCltJUWeSs0fgIAMnGChFZsc6Qfor63JMftiQysOnJ63lE1x7e/rgbuHzX0RI8yxGku+2/0A8V\nu4ll1gT8BlK6YrfacqzopSKtG9rCc7ZeGmtNG006CKn223EkKNyQZ84mAX3yTzkYZPUSrSp5tM5n\nyLgb+KFZbfQL2jG4OWu+wHYJEgNpl0Mc8A2b6PwgyTE/3S1cO019W7VcERYNX+SxZ7lNmFeHj0/E\nRF7gOUI2w7gW/yRp2LbBbA/e5aWaC3aMHHcwEzHagunwiK2HJU8UKf0nz3jr3I9Hg3gLMYOJTm4M\nMD8n0IlXCngfG2ZTQJa65OqzzfFo2Y9dIncZQ0SA58nVKEOCcbHiFh4S3LMVgOzaM/gqtclLtN9q\nsse6z/ih1dhjmsZf1RdeYQGwV7sxxGBz2ENsry7BP81wRWddl3ygohI2QjCLeEkvgOEGTQ8fW1dP\n569uhsVXtBwQKzBFO4ZSxQbnZnjvevAMfoDhjE3SyBqvwZU6PpDWlOpczjhlyrozh/aLuAI1aT0s\n2HmUARkpqCkKykUEYU5UFqQ/fvDUcCwzo1U6Ai2TDGN95cd8wnoY8iQYD9oasE9uHq+knpnBB0Om\nwGqTvT0fqFzhUrIXjvGWu2I7QAsLtKgKQ2ZOKhBUOuhmmNFBwF1618h5m9E+BHJiSFoOBgfaNPeM\nyRygxUrY8p3PLhjx35nqlh7LquBLfYi7fWydGFbI+lmaGB5PzH0WPU/MhC1XWe5ePUDFidEoJIzy\nW9idm3SY3DunG4Lo2xxlOZTumtjvPgq3TDhxGbh0JpgjFmxSZMvJm21b7hDJqAJlX4zn0PMCgTEC\naVAZW3nEPjjXjHOikfLlgNnSU9rIG0iASzCH3A0vDZNAho6atGTVNsCNV2naobHBVxBe3YkGSI0N\nE3BX8DSv5FUY/IpsE0tkIkAOP0nXvkzyXd0VvHuDMi3YjaOyT3ML7a8S+bWWoHV5sIZkkjx15kSo\nVAIIsU680mGzuXJrxzSniiGah3aSwrUsRiOK/ykIMfDl2z/TwFtQ8n/RgGp4V9QTvvqz0obzp9N7\neg6BowrZmewDJnZiot7im9usXdZPSxCDq1Q845ZG8Vd9pZu1ZXJA9tNDL34WhN0HItCcocX2Be72\nV3dMFbw4OD9K4QVXiVTfQJPP2gFly23HZj6gvXhRPP/2/NIkekJnCAB5L/TDzdVh2hZe702ra28+\nWeWGMDau/ulQT/Hz3+4VOrQ9EUu/+fzyey/uQbnx/RglWU38oCnvBbz8DNL68FcaVUWSIMntTPYf\nqKLLdh7CNcdsdz5m4jvtcX10WulBhwyjisRsU6g+b+aQhN2SPE49aWjtRIIaDTe1IJiZ2qZbRtjl\niq1AvLIcY/NjvKAXiRsN0la+z/3dkhI8IEsjMZr2mJLSZFwMTvs8OCsZawsMD7j8fSmymYqxA8OI\nlSPSoFYH+MbriB+CROKcnawe56Vcxdnc04PjwULDcKI8+2DV600DoFxJY/oYLNgkfmKNKEzHrqQi\n0q0jbvKj1PiGXUwPc8YuNShbgUeGtfT4D8B1wsh3+r/BUWD1rM1RuwUitKmffeCwUCH63JpJ4z5m\nyhIwLO0QAJ29gQ7wxv0D6Hj+qvAjx3/2LP4q3OU8jbW6V+WUL+iDIL2NCoi6HhKAQV1eLnDT5Dw8\ndsL2XnXqu5ZKd0w952i/AGCt34Q5vjjewFODdfobJILG1Op4yqQsOd6tCJ+jxtysZHs8nel4X9to\n69pya9KgkdzRfYn54ZGaXD82Hb04y169WJS9s9MJZjLaTQMykmgW8GyR5nPxGVXDYO8oyvFAmHWg\nfH2rVPe7hpDpOmYrlRQ/Zagp5TuZGbAaz/2xKHqTpJ3y1VAuI/9NJa3kIae5fx82/SGLQV1cISj7\nsu8d6BbPcn8TBTdZY9fZH6bgpc+VUvzQJwo84ymVyA0StHU0fqmnWba/wIIjI0Lt5oZvHsWfjrO9\n5N6iOG7YMNAbMxBV5Vf7nQ1dDoohPPbUo7iZ29eJMrwYldMHuH/OrhPph6ztyfKOudgR+z9xiHie\n6Zbi9rFDIfM3LgTGYkIdTeK7UkVw+1cwkvfFkpnuANRxlf7LV7UicA5kHCZ1/bWK7UJdpRRtsDtU\nGNF1GLeZMYYaWUv4UY4apwWn92A5L7TcbSmFy8hda4z8Fbjl1PGg1Tt3hD3bp5zYnpPChl14vyso\nmv0tHoxn5krugdwQqsBmEe7crYNW2oG9d2kyJam8XBn/qtaaWRRhNGZ0YGRjjRGhobRUGsbdA1lf\nyB1QCv99lkBRzFMYBcDwF7uBTYiJ9dgqheUfUpIoqmIK+FwkMgqnFD0vpSJCequpneyjClTwC3oT\niFx6n8i+Wk8ml1Qvx/mq3HIJKU+Fbwo59k7PQ0dAIhMHnLMuaH4GT3yueWpGVdczthc0AoY6XX4j\n2/346cP+8LJWw7jq0yuZF2+Z7RTySb4M1NTJQRCExGFZJl3DDQfYBkq3hdTO35YDiC7hkASXTK4j\nU76xpKQ7ULrpsVuT8ZIyRAOXzP+wBCe8TlNS2yH3yRI6lO6tn5qQLh/GdyZNjpsaBye+MS/bnGMo\nz+n8MrY7KAffFFjrFADDknoIdclpJ93KPlQSe9LJZShEPoBdfln++G/UCZrE+0u95Hi3MUxi3kAM\n7Q1h4kOnV13BAr1vH/8ke9UUMW9BQR0WPxc5aIb9MJyWLOCe3ZE0l3EfuN1mJX3J1PwqW4bfsCVq\niMsuCsH70+67yzWQSqjvYxRFs6QjVtWsiFyrSWZEg/vvQyMYD4Ll5lL9lsWodxeyINvrwCSC+wyz\nYOPNOA8J9/xK+svQB0rOz/L9ZqGiGutVRyAKRPvqRXaBFqEalppo9gMN6kb51ddgdEI0FYWl7f2O\nOpN6oqDTsPjvKBf5+SPvo1EiCI8lBCG9Ul4nyL+bvnpGGaC2ijn80VhR0GxOR58ahTTwLRNxigaj\nZGhDHgyY1C+QgLJ8UED8Q2RtbaKC01o30QPC945XrzlWf7uT/ZSq2Fdy7H08V6cp9jVcENG842ol\nBywtv/zTJSR+lH1mkbr4s2pW8fQc7Qpr+IXNKbI5i7zNUbaj5mJPdzJ9zRZgE2CNfAH2E/AccKAj\n7zoCPpwIDq0bcpRzZoGePfnu1+MES0jZAWJoGkZr0vZX212fRjpHDkTsiTn7Aa7OAoKCLcWp/gpK\n8R+mjSHjkLlwApDqzpvQQbmAvoIZ2JLkBQ119rKvs1vpO5L7zUSB4y0HVWDPOPMy2ZJqWgs8O/X+\n2eHllbtVwgpL5iQrskXCMEP0sCuXnaIrmcdxRt5c8mCc/KjiWs77SgwSxLbiEYTUXmpbum6pmVMw\ngoyTZR9byD0+xN5AOTssXUTiWin6DhAYZEEF83fLzPA78Wu5Ds3CXIE6gdiq/5MrMXraivrdS+wY\njqhpLm2WJSRYWMkad0NFSwfvZexJFdvdTMEM033uAxVb/G6hb6q0R7LrfgciMq7rfJb/cpKUBzH+\nb9LbGJYafmSGQePYYFCrfl5QD6DRZXBpt/4RpWKKD0HT6LZY0usJeLfaUp1ZeJmq1Vv9LLIfvvx2\ndaN5hr43PYlA89gfRbN8O59utSZcy1iumyMEAGjLJkB+jTufZHbjUj63rbKrXhEboouqfFCzmMXP\nOtnd2vQyhrX9xXsym+MMbM+YHV6PqU1e1Svo07r3MEXU7KAE8KFOtRMN+PZ2kX+s+tWD+U4duzog\nn/Fmf8Ty2Zbhljt2XnuMsrK2SS8E1+lYJgdvGJ3X3skNOgW2ZMG132oGq61PjIU1NOs0GMv8QzZF\nZFQDLrePmFlFywMZdvXUgzJND1749aR9Dr/Mp4vf1I6lQe2uQ1B1tn6W18CfMs+bF1uk6IW9Ac4X\nGze2RPpZbsaIERu0iS98y2pKLeRFYBD3OrtcvfeGqFHZD9byQVmIaCXGiKYhrJP94XQF5RUy711t\n/e+VYun6GtZaoJ5umhM+JdbpLwNhUSnc08ZZoFw3RNXpIdFgtJNBzGHZDpHYEL1Jh+jgKzZyRspM\nSO/K55Y47UqiZDoQ0PTvKXM57kZR5vjfhjRmK0S7Fkt8ojgorJqTxwvjK3HNN2E12so4IL0RkJfZ\nISZCqvNsZLtpBy+dqyWvn79bmPSlwJSqfCjISFSunsgLqjBjk+yKS86A3/EPZKrkPkZ9pfPBIyaA\n7E4nrK9avZFGwVHmrS93hUDyl+JV2UTOi2qiV3qfNxiiqAd6dciSDpFP+AFAmS7fr12M/b7YbmN1\nknfs/kk3wLjQacxeeMY29cPrYbDHaZMae9RaGQ0KlaZh55tptYWQtHBIkCyPOkYNOBsTJUsaZfm2\nICLS1p8tCwcfcUizH3VOGz6R77s6yUJl+7vtcZklcNyDb7KTD7FErux6ukjXaiuwI9WDEXuBCL6f\n3Hhb+kTSbLih4K8PLMF9VWhxi+elKVfdMmx3+mGHR6xtl1940FSeJ2f6E5Je6cKcR3JJpLfurX6S\nPAJPsWd5AjjHh2mkdIl1HkdQiGS5oFogKqv32IVuSnSus9q82C2CqEy6+XLFCbse9YU2xHp9srg6\nBvmwodJV68HEyCwrSZbNdvDa0ptK0Wu174SiIH2OS0MT3Mhef8kriibArev7BVXOFGs8xSUoP2Vw\n+9sKumZvdWQnMp7HbG6Mk4ytEKvYbkjgQlGTU8irGBAZOZouLZlEgeiCAU0BP3yP25hn3vkpIC8k\nEwRpo7YW/JkAAOvruQdb5ijy6Ncw2X2qHXRZuFLF/4DR6NrngBEh9rTxSP/zPj8LjihEdZnRr1Jf\nbPsZbZbp6JCxfGR7f0U1ns0ReQgW0rZUpmB1gsuans6zgPu0EP4KJLGzVGY0KBiv9a0yYP01WwGr\npEaFPqoMtauE6LYzm+xwacnpXIfsJa4V4VzhGk5kmiHJ4xM//TZRqCv5qyj/MmrK56/pPJ8zp2X1\nl1qwE2KM7fohM+YGGBcx7NM6bsBaEP9o9zSo5+OPtS6+0TTAtJn23FcKoaz3BFtV2s07cdm54jrz\nFShdU1I4a23cOWjBilI2RpTexKm/pmLciNqhyLi1Y/Zvb1vQ/frgx80pjQRfP2JLUfuVoPUQYley\n77zZ6iY7SF19kUbhL4OI5msb93/g4acC49Xhy8EHC2uhQGelW2PXOxwOy1NUeKWXzurAlV+hwIyR\nTZy7HHFq3LQS3XeXSkG0Ko6iWOhdWva7vZV/ZhwJhEl8M+MkrGsTBl93BYJaYQgrHuPepqNeDrbJ\nZF/ed17DHmMcIDD5AbdGot0fK50ZnOjZ/SzRYd8TVYxnWGaVEKuH1tJKNsiEH16reWiKEgdp06Ro\nnUPOum9mQoBRRP4WZd5aA95HqKR1LEvk1QvEm2K2opjRBaJ8k9DHZsyo+I5v4F4k+mYu5A/w7EW4\nOElZByJHTeB6VDaSNwI2CHDUNYeQr5U4ST3OgeA82B3MQHDgvd7DjiI9dIf7UFVgSljZmcmsFQGQ\nXWCNALWKYAYsHEP4IPcAvak1xEt7Z6RzLxVcKUvaklCmXGav+1X35BEKaB3Ohj2HkUrwrZOC4i16\ndiCJaBdM82PDfbcEM4Ng/ppZrdXYt5CZCbgnxH0wtAfYdzr2LkVrOvCKxFJN/V+YuUZv8ZHVFnIU\nSfFeDR8RafuFOtDSF19qYXXy7vdG6TjN7Cq9gQWpkgSrop6fTqVdz/CdRdT3MvgTUEQbAH8+7ZAk\n6HEjte3hN/9XOiPj+gZCHMUz+3RqQ2khtw5dRiaGLvVWM2QzgokGFalACtrskxgncZgIcXDq690A\no9lLrypy7gQqvENsi9v9MLTGhlzM1HRnPf/OCvBSbuFoauxeR0v8rYA/sESeMyiTFqmOfS/rwU0G\n2qfJ/NF4qpRVQuU+XOVoKhaz2YcfLLiFCjiNwSK6NTArZIsdwf40nxfCIrNX7vdtnh3jdhzVOQvI\nhHBAEAO3VX6V1dXsaxpTKduvYGXbZZ7yH+DHfHtDWsuHKouaZIlG/gqey6XFHnm3r9Ru1OI+m6GB\nWeFjPa7HfBWjGxBqk4Y9ceAVd2i11Lj32zxAHyW9S75vzPtU49i6RyklCUtXKt5nlE6Q8yj6MaXx\nM+JfnilpDBiz2uThBB6pVAT77Uj1Iuz8vSnK7erXMCiz6Z+xbgRUlABEQ1Jqv6/bNPm1dCYbhEXR\nezvXJDaF8oab9mtpeEJug3cRDYcriEITFn3DUlYnYjDpImqzY4DtLj6O0EziQ8e9gikTAm7fIyE+\nL3XS8ZH/JQTEQS1nLDhXJ895m32U9FEpuRl8G6GakynBj9zaHANaDyAfiLOZ5DXtEAhnKPTWRE1i\nlTfbUfUAMRnq8g7eKh9GC49k1Om6WQlB4ttiajampZlOuSWegg+BLBuxhTX6EwovSD5W+DsoyMti\nym9Via6JgHxHGp5xhTb20ZIHQBV2+O6IC+4dgvRgYfUMvRl7xLxYjBBVJNvrd8LnpuiXExm9U6gc\nnqaeI5dzOuRIuMB7tn4JqHSb9C2u21SX+Hb1Mm8RM6jqdQrKyRVxdh91B9s6ActQzTSLj1xts1g7\n+zgwhjWJ3VcibqebLsJuL0rIHKkq2cTAZh16aGhBsi3s4z+xFSj/Re+RNHDBbxXbbUdOYeAGhow3\nHOCx5PDUTiENaYnPQtlm/WbwbYjmtRw02Z4I0jSCocjGj3ESGxEuA8e7qeZpMS/qzzdu5XTeiwWJ\nVJCpnJcrxdBoKWEI0M/2gw0EAmIgw1gTm68YMkZHsTOARK0j4YNUvN2J6CnhvPpqoZv7GI9d0OzU\nYn50l8KQSjKDY65Hz65eGrHz46WaIjAGxxYed6hOeVeAi60lL5wzZwoHvHzdkniXNjHk0JTk+8O+\nzoFnDpPEY5RT1yIr2efaKezWSVY3oneyqQ6qX0LS1m9R1ulr4/BclDQJVZwYjEFQXhUpWRXgPoJn\nlDpDrF9C2nKe8noaInP/0t0l9UwSUEuPVZvu6uxsu+ectsA/K2Y5BJDOhuHT05hobfdDvif5IFYA\nbHEmBlqjcBRiKjMl0QHthlJK5gzL+87QclnMvvJ+Y35LbzWx7K8tarwllqIv3tn7Gg/5sVIZ6vv6\nOYOODO0saJBNZFQPEMY/KEKbEUVn2a2+ublisrdUF5ItmD/Ey7lttUSg9+32Dp4dffgMSkrZoCYA\nGuEWXkE0p8E4kcpghccWs5YyMGp3ro5IXYPT2f72pFwfLx1w9K0eIgfwoAjVs1NgxCLiVyYP4jC+\nSki12L8b4T9Q6MNGD+SLAXy2zyyzTKLdfRDI+rb37XxEoKNz5u3i0xzFAUhTo3HDrdOojEfe6uZk\n24sd8PoQKoFIegAvj/n4RZhAZ20Kg/580vwHWrH1PgOkaFEA8rCW0OnL/5ZN9DfZwxesmUxuDYsx\nwLDrpa0vCYAmDPvJ/rAHDuiam+zZYavTr+biHUXhfCpaA1eGwW/FHcHvapURdcWkK+wW6b9XicEk\npN8suRWivCHcgShoHTpNSdvFyYEK46lSaB2fRWxIkY6nAsKoBQzk9q7z7bLDGDnBpSt0XGTVvH9D\nDlDZ5EzKodSgIa8Oe7Aw9gXREY8da9bYtbtxDfS004xjayqqY14OJHUDOSYaWbmr5CZIH+ekFbJJ\nX/xhqIpLyWaY1J4X7PpTuwP2BPqstDxi7ytuFTT+ZOUEFyAjlNe/WPr62C6Os0Wdd36FbR/9ekf5\nj7FzOYvLwh0MLpIWlHD4VDPTr2YrgJBs0lf5S2HU8lmqVZViQJ2xkKGPd5qwdHDG95kfG5BOL2Y3\nACPDc7s7v9Dd9rgrPsVBSzbPSfPmYkolzccn87KiR80esa17GVtsnCnO9KliPEnsjPMxdwnq6I5G\n48zQrxZNmJMpSzw5Ki3hHOqr7tOCSL4EZSXKZ5i2ia4/I7kVVqpgkl3GHR9B0IgsSisby3dMx5lr\nBXi1vO+gZlICctvPxo9PZwlmcueUxrBAOTGr7ijRalG7U4YavQIeGArqVqMJ1SIb75sQ/enFicGf\nC3+c8wD92UqEcgdt6FySpBu3WJ+AYF6BwStPc/r0UIz1wfiyCOTQOCnR8PqrJ2NvoocXFTqpJ5PS\ncP9WjxdZTXprtLAfBSvJYP/FjVv3KVRZTt/LQst6fc+7KXxUyZ65jhjKKxzueJNI26Sh+EJfnZab\nC1sBCcnEjsNfYlzCWM2D5KHfnTNnhkOqKphzf1mQx0k/6CHnJvGRYup2GPRJWRCFUIWgXJ6DLrYF\n1nj1Lu9+Zy7ZxcHTodt654RWqKEZQ1oMjSfIYDxVUrW8oDd3867FkyGRTxstdD61CT3tDZZD1us6\nyGI/5lgmqmGTlC0xjK8EMxfC9kS1yeAUDdvj4NsQN+2ygKvcG5W7d3IUOgrwluPyeNhStrpjA4Mj\nvHce8TszzvRHgHguypp+8kzrRVqqF+1J7SbxD99H0JFASzvj3H51EfYNM9ONWBNABJeRXnOHRrgK\n08qoxrsRA63sdcEfrIq38DZLFxl7SoCVM7C93bMNCktLpodjR0adOHqibnIb/y5MJpwNLn8oMni4\n+l+Y/LnBHyJvElLl7g7Y7+qdmrOo53OCjrfH0QU0kVuno8Lxz3cxgT6/W2TgFV/Hg8wzb8VyEIiS\n6hfDjxq80WmjTNYd1WTrTsvuwQkWGdT/6onyPUg8UMz7FTBfGcT6UziST7pe1tyNPWadumqCBGfy\nhEdBNtbRpmVaJJq0kSLukoiIVOMhWP0JZ7eEJM5qA8lSGfRy49jFnNWDRDsf4w8vu22jpzVu5lz8\npKvICC8RW4SAO/HmQJmkmonpQU663ry2nZ79kagjVSh5oJlQZejj5QlUmIVHq1e8OZyE63oL86Fn\nvQI2j7sAxAKkmumkFUCWFy/bpUY6b6pCQ23BE3UOuxvUCs3G+ssQUYRJPol0BWIEOPa2K5nU/GEv\nAPkFM/twp89k7Yn3UDbIQhpk8xq3roSY1meSVG066JqJV9rW5OXS5chmAtD8WFGIFtBkt+YwDmxL\nxcjJTRAswKQDkzhhx2Cdq8aSv8sUyQXe5EJXRSZNrUVVvE8Ea9ZthPc2iZLDHgogrdcbPTrl1M34\ng1609Gm95AmQHsCCOu8vTRZz/SimiKFz7H8HOKFZewmP84Ta1UKP1dhIJRa3CEhSYN4hwkoTAe6f\n0gEUPygzUahaRsD07siqu6m9WQSfg164yYYffsO/LTRjk/Xjx2j+hcQDMZbheaDGrYIm5RLBlfUf\nsY6RGN4L6ihuggBTuRbnl3jjQpSfCnhOJcEQCcaEr6M1p9D81lnmjdwLeldEfuw+aRJb0OtYbDwB\nZqGPmiFvBuA/uANRYfB50EYLT83p3xYmEiUDXeJi4Fz76KyR8jZcZEfJPASnSMQ4OhB5vVFvb+Eh\nuo9FMV4JQ3Z0uHLfVRMqVVqLPs10ymsFJ2lQmJTW0OPpY9spXASDmLgBTu14/cfaidQz9d5AYn8a\nKu6O4GdgNqZnp2bi0kruHxByWLxtPXxYGh8DgUhBnkaE81RalY3ZoB6Sl6HQQAOxZ2UvKbu0pbSB\nlyYasqkFMIV/lEbUZDYS1fzFFSbx9a3M0Xm70WRLN/R10Uft6LzIg9xIzVW+bxFHI6dETy83JGkf\nfiFXiQk5XBqc25XPPRZGSsDNSr/Ls8a/YlKHUHUU2mQ6eOTtpXWLyB65ZotACywqTJmT9lzagLFZ\n2xn/5ckHXBaLcQX0iNfxDkxoEtRSL646iUdRkX3PWK3yMUyxjIXV6SnzN4c3WxEiAq7ZtKeVHcRk\nRF6reikA25+0wNlFjd210XwyN0R8oVPlvAb06Ruoa5RkAiw/PxgSgZHdqBGcEiNMGYqOdxg012xn\noa7oZvwza3EtuTHLV0N8qqJhFBsFBqzw+HIigYP9MOZwPPiIbmRKEPXKeWH0jRITlhpszLSidis1\nVs6oSFH5Cw1E5WVjNjbwsw5z5qaAYP7xf6xfuVe/GtlAzgn+LJQjTizeuqpEBHQPCdKG0VlO1lC1\ndrbpA965Z5zCIagpyvvz3apjdBQ4NdSDDFpICxvlvZcRGG/1qfslZtYUfyt8l/4HtEjfER+tvzCq\nE0WIraKUXMFZdVSAKqb/Z7/Yjcz8Nh/2CM8kVH8mqCMsyL3OP7Uama2VFd83C1Gco2EIK3GSaNw7\nrMbcAsdKoW/RrdEAuSy6giLu76+9JTvtvE/TqTVEsusPqoIaOrYt3mWzTz56KeRT068B0mEHAqqs\nZDft21ScnNL1hWz+fTVtYzmegg/IdKhkVJKxE6gfa8WR+FRjinPiEmcVDNGdKTAw61rzkPRpHK/a\ny6EtP+N5VsTQ06pKMaOJoCtHjleRGx6gxplmLYbrZTCcTAAEoNC0UkJmzG5Ml4SI6MBVQ/pxo8Rx\nH7TbP1AIm7oPpjKD157teJphXzJDw6jYw3sJDnowLISeC6vDpX/FqfBA5ZwiSH3HVUuS/Pptyckg\nPrjDv+YgJj7uDgjYXGHou3LNr0qG2rdQcSN7P73f7x/LbFAm54zFloV/cz5AMyXPng0cdjAIUWFQ\nurKzWRoGAOXinSMO3ER/rE05/v5l71DfEMAFs+qoW/9J3u5jkDEtwn2leuhkhgb+FIyKrOk7euqe\nSRTYjsXIr0JXQxLdL71yoROJ653wXvUsb/ePL9RBKUZbpKSfRcvbnSAk07+UxmUmsI/69UzFbYLt\n3u8WekrBuLZ+en08w7e1O/wgdxIdPdyNoM6DyZBYsWw/1vq/h04LXFD8HRtipK5GcaZMxfvwOJh0\n6yP/ejUZBgGTiQZYiweKEvu2CbS+k49O+8GkGvZHVQtSwrhQhSm3upaBVUKgMVJj90lHvC/wPmaJ\nGBj39L5PVkGpYRA+8HSK3XPxBLKx0PjLaaVyAeKSwBtnooRLmkPJoIsIZBcyX/+b+rx6PIdCKs0K\ns++HmmuLpUdx2wopeJmYKt8hswOwcYQPotO1zLs5Ia2yAU8M8oaQaxicOEhH0YzkHAP3/8GBkmn+\nkgn+tDwTZoW+r0Ml2mZDxLJw4UINiiDSzs03mouQ1atIUGtMZzLiQqtcvSx5W0Y730Ho8QnPV1NF\nphFL7VoI2gigJnr9R1oieN0ZVJUw40myhOqL9VYZIKIByVC82AKPMJoynUnaRUAsGmasiQhWbCH9\n30qPC07qd/S78DaKA3TNHSVxVJzUYWaj/dshnb14clfbj8p3mmkJHQXswD7Dj1NrRXHbJb0QuVg5\nYVAVgJAWDyCKFT40ppmeHMQzlL3YDh5eYJ3JmNTMYMjGNwwH61DCWapczirYQTJfA6swy7+Shhjh\nEHyLuRhmBU7b5TEjwd8h7VRRTuVfHlcXikax9zKumYbeJpPv0lS5Eah2lYpagqV4T5It27f9AjMJ\nOfRcq2fs0acLYlaYPGnREjbroZZjS0ArC524l5u2W+zx8k0FuNdn/JO2WaffZsUFje2oZoFPGAXg\njb0cUBdbXhtMqKR9k9EE3Qqdu5lvFWwt3MG4tp1ahSozcye/I/FA1kgjxH3jf56q3mPBMm+eLgnW\n+WEGM56PbwNApbvPFDf5uoEk5+fptgAzn9XSzBwWCPGJ98a75QZP40+jHupmdQ1JpOYbVcuQfq8N\nBduucGyF3EJzmx3J76b6LNBCCItaSg6skD2HlTC5mcgGyxO4bAVnKmMczwx2dB7QL5si/Ut3wI2w\nv9CW9Jy/ySBUyIGTB2Z5MKF2nFuIeUQGdXn9ZM5SE6l/W9jiKCfMMtuFBM1izMh+gN/C8ccw4Go9\nmFnns8a0Rl3wAVmUf9B1bLRPfttE4B60sdtgvVvObq5iBkDS3Ewj8lsjQAh4rZzn89t3IJbxt1Qn\nIZrpfw1dOErT+RYgVUSPeA02ZEBFENlysK9Xz9eBj1bBg249vBCDlMCCeEVVK+Csv2IjYWuRmS4M\nIMJVjx/E/rSboIrR+7Uw8WRnLTtC+o1nnKg0INBhaT3qkvCFBBjg/7NZaFsv/gBTt9uy17pILVWD\nZSO0HGL5eRWii5n+ySDXQPRuC0EQPTOL09vpiGsGW8S7hMZ/ofDjXh7R2kHT0o57a4lhyt3oK8Ry\nrHHSfx3Ky9GmtcGNEkGkDJRP/XNUnCV2H1dztXzyrrXRHzW34RrDmV2+pZ2YcWXcfQihunYHWCVO\nyODPzBHmzTa9dUwfwhVP/mOKAqtyqSmvtc2qFEmBkHO2dEEEmW4yCIqLMLzo6/UTxYGSP17HU3Ui\n/mC6B5tkI5Hfpb5T+cXuJfuWZYEbzCr3PIGA39PASkTDRS4U8vkSBLgNH4whWp44k6Gp0brQ3zLL\nGs68GsfjH+657Bcg76oEHmItPk52N6ncq+HHRiV5iAPyZx4dVH6LBLv35Lz1cau9mby6jI0fSkDO\nHuwhHAi9CUm/YrfIJqoZRi+Y3T9kEizHtQu2rCGOG7MqjJHfeqnW+dKEg2/yJOu3UDqtH4PiCUAT\n6OaClJKsSBYamBiJXOeAx+TBsMwVnSrg8WyOhytkjGmlgYXSlKc/A5b2uA4aOgFPoAV8ZBwSZc8F\nXfmwASe0j0uKWQ7gn0s3JvWsuC4of7RGY7KrcOY0NngzRtdZzNOZocadKbJKxiF1q22FYvmfxd//\nQpdoSevU9PQTMobGOPCCsGrgS5BchzUtyE4kBinZ8jCVe1H98eIGoUbHNhzsAeDJrLFdXfWd4rGU\nCrK40v1cwKNy7sOwAImOVWRl8m6C8X8Y2N22GNJkJe2FnT9bIwE+u23KQ/5JMAwz/dw0WrUPePG+\nWKevUGnd9P24I/IViOM/Qn5gtAn28R0qenkilnZmKM8jKmpBSaPNzY0NthRl1Q/xMj1QJn/WHPEF\nGnteOeEQkuTjmEm2lNpmP72JDolt0JP3OmfeuLTOFbIQB7838XX8JsmvaVaxIxF/jjOoO5uHEzlH\nkqlJeZiTB0sSkN8w8fojCUFn8lfYx6omYOAEdGHg5p3KAni7mBP2tD7KBRwgcoGsDBGoUb33S0Y/\nr/to+Pf8zVAMyKfC8xeKeBfJxY7apl9PBsPYfX0tCMdhFVb2Vvtus86qaGNhPeRx0KliiZpxzRXo\n1Kc0pVpcPwFuSfuRewO7ibNFpQ8EGWY9niYjcDivHCpM//yrW8FRpnYNSOLYPMaEKSiHnx3kj3Vz\n9dpH/HF9IIe35RkAiyTaYShT5RJ+N3BXIylICCg319w/xEZz8xOlun+BV9BQql8D0uinT/D5dibl\nGgcEA3lhPKODxq5eaLIpd4p2ATmsAZS8kcRGFTshm1J+OCjHq4MGicshcF1PB1qbde/3qRvllyDi\nBR7P21tL1hCxhNTEQ9eaxobqXSNpkc/2Vm7tJUfAFJoW2XjYu8vJe0SI1c0ECqLKPEpwmSVwVvTX\nFKyEOVVNIdpLN/l/uOCcH4xIu0vJvS9CB2BfMffgk2DMg0GXsfccKAcYM9qxPdDBYiTk1qOUZBlK\nDpsq5Jrvm1jOy0S/0yFov/Ag/nV9oqcESybTrUdBvSFDjbSfz9Fas/TTRvE0dZENzvHaHhxJYMl+\np5pVssV6fduHUXFpUG7mLLnRuOjGxfk4UXKI6z3+5w/xOv/G7/NhpKEPIflRCiF6Uk63AClp17lo\nKjOXYcFc6Lu52FhrZMdPrbIUXcKGKhR7Db0moZhTOLlwOcjGkaj9tTpTDxlXxESZ6AuC5ldEiF35\ng5Il6jFKlh5tUpbYIwusmZG7mnkh9EPFBPq8AqLcsCV1FA042meN/LtzeGGH/rtkSl8pcKFZ6fe+\n2oYyWE33TYmERuFpbWGFXPGW3P89wJoxXRfD1W55U14s7Xvu2gx2+gpJ6VhwG8A3JU4KzAzp8BCT\nVzTQovfxXE4wtOB5zcVbB7lK8fmjFeO2X8Z3gmOOpHurIRQifU12NEbCA7Gyjb0EE7m0sV+09oQL\nvlig8v0WRvDyDgiGJ/facQxgYyGz1UDMbKcDQivWrSiHOF3Xxu0i+APChQFQ6/Fx+VOe8f108+m2\n6VFQciyZU/Raci2jHYy/4GdPXoleTR1vCjyAC/QHvZsRuIjoS8/uj2DzwF91ENnAeLcYs/gNFzsv\nU4v6Z+nhszUK77WgXLhp2pqM4ssS9UAJaHmAPZfUXwpPBo3xT+/bHY/xXs1j7+UMQ2cpZq2/kWzm\nx8Lc8V6Jyg1EQ/iTaQuM3PCHecJFChcAdFsnIJ5Do+fK8uCjwv8AX6KFuCMXC/+y0OpDlJ3soRN7\nGLDgjxP8bfH2G+dJknW/YRGUFFTDC68ILtoTuejwfv5Q8OHrHsH02nexbkoYBTNdeZhHFIrvOKr8\n2prlr63tkKu82MbpoU+kmkWt8ZOz9zc1hgP887wSgfmJf/EK9ORbsBczQOmKBkcLD/AnDwoiYYlN\nOxL7Qvkgp/51N4LHF/Vv6HOsRQuCC1SFrZw4rC4+8b7xlU/bu3f9mt9w3TO05Qp+xYYkOXdd+1hy\ny82GTvrMlku95L1rvr7Vjvn+KVAsl+x59NByJ3BMR7ekl2n+2A4PJh3XRyRKWdkuqlO5ESnIXlE2\nZoivI/AkzR7a4MrsBdmtluSCSfpwX/nujwFLRomx6o5V6F8DUO3UzWU/mb9BbyRelloRIvN3gsRH\nqmxYHayfp6R1sCeAKUhrqlFi0lVCwNrB6+RSdbubvpG05e6d66a0n/2+/Cc38uOOeVvzJKaYCSLF\nHyhqno7S9TF4uCUKWro+84Qfbw8AALMb0WaULd787UNbNBEM/lI17mpxeKT7Tclu1csecUz/26md\nD/CM74HkpL3hlaFO96XVkWOZBWUbOaZKaDrb/gjwrvCZ+NOvCQoFTl6his+6P5w9mk8bYrEzt6wh\nzhsdQum8Yg0XGPfV0QM82B159x9PTD7SJZV0AI/V6y3EVkARkUelX3ZdXkNynGVezd/Mq5os56Hg\nVEsOwVEVzm6GtTBBW5jWJfH7E8b6j6QSCu6txHQJ7Nq3f14nqnkJumx89+Xpd8SVBs30bFktD+fM\nTBw0S9f9WtUwfHzgb04SWssUx6RkXIZ3Namp71WAj+YDHp2njwThvGs+gYvklAeLSuBXhf98tl2k\nJ5ZAp4H2C61OzY+jCFOeJPR18+iNN7Xn0MwoNossJrNw8fP2cAF4XD9NFGGIJWqxHtSDroT0q82H\n/q3D/PtyizDxYkzdUTnNvsgJQHKHRIwXVgTd2psY/PcKQMAB9Bfaa2eIPNZubITASFjf7eV2NDyg\nowc3Y7HVHHdfBV2Nf4cBxxK8p8KKbU+Ce1DCk4HSZlqPwnzRDklIv798xAdo9Cl3IxLfq9mPtiHG\nh5VYHl3OOB0mOvglcJOofcNPyQjGPEwYnD7OhG55SeF+Nsjwbc5Co0gRBPywm29Gl9DYCyS/+3eM\n2DZy+isxpL5rD8/k0qyCY5kB0sNZhmTwV0CO1gFG0FJFZtWlP3hePAyqpABxkLYdHjyzhSHL+4v8\n48RVPdCuzQbht6yDvRSYsCutVu9sptrJtobHwrQKvRGg1U+dGbQ0ikv6YpzktrZKOunS+Xk+nsR9\nbko9mtCIYKxaoK02gq1Y8p8clJIhy/60pkcz0P8hKbJAOEKFZRlaaaO642mbMc6o23+sg5Vaox/J\nx/Yj7WUuk+rjXhVmm1jX2/4hkbUbDZpjn0PZEFK80soYUO85gAa8F8RXzUlaYQl0zW18Ks1dxlkM\nxTlJxSbA6R72uocvf8V0YIcX3zQkgO4Z1Id4RLYF29vzomh1ryn7yJWFif2TIqaifnrWVqo5IRF4\nKtERY0TMkNgPFN4MWlQb11lPhgtR89aliQrufTGBpjnl9cPYFsMcINrbf0PjZXW/zvENIgeFSxcF\nGqK2g620knP0e19dWRjnZfz9d/FrAT8Hne8hB3UgnZfyvF5wD1Hm/xZ2Rz0Io1J6ATghfD9j13EF\nqiIL5BurZrahsI/nntmHm4vKWg58spqJHWbdDkFAgB+9P4exQXTqq5X9otj55FcuOJX642T6BwiA\nGqWVqxIwDMfX6nVCw+eM4+A9RWzfYMvCUrYKj4P7g6LtAOxfyg3H5N3AKy2AGHO6P0fEAlfDsLaV\n69r93eHDBASiupz2fdil1fzYasTcmtKDd6yJL0uT7jGFG+OdYgi/tDUgTnJ61CeoO5DIJjHD6bm5\nwtIFgz0j5zFxfWb5h4CHSRmCdn3aBGRyw2eNxmcK1KSCevu3e61QZLoJC5Vch74QexRjOSdRd1Mj\nsDmprY9d/7zpEMc9xQTclaZIs6NX4GeCXQ2AqurskgTeT6d/6Q+sHano7JqbDAbHvZVrQiPZae+W\nJL0dyXJJ1cOE8rHnIwkyWM0y5AYcf5mDDIK+VbHXvhshhgQ/Wht6nQBmReYluWkXFRPRcn0Px/bM\ncefQB2uSuZMKCaCCE62Nq6SitPDFucm6u3RtckEgaIppjW4lp3kld0vEgKnhbl7TsTgkEzbss+Ca\nOD94vvtTT7XidMtAdcOm2g+mOgGLf3ep4ucT43mm7DOUHW1oJCeojJiOXJLtqQMOJmZXFU7ClWIy\nBaNGvzF/dK8RChC5h1xzNb4VL61K6/icI6SJ5VNYSAup8GSamm+q8j/CS72cr0wIg5jLkQ8ZRL6v\nEc+PkOEeTJ2/3yccumJieIJsAQ40kq9lDAib4xSoZC5wvEHusgQNDF+Q1rO21g/5hwV0bHSR/FWl\n6XkHWniRbuTK2GwFD61rLI+1ZsN3UQMxxteYd8lVB0t5C+umL5XasQl4YtpJAUgjFZ20mgQvJdeg\nx/GeIhDWButAg3PKnouL+BsGqnvGgjdhPKLwdah4EQ/INvglnpkiVQAC1jYnjLrr2Pfl7WgD7LCs\nFh+kusKNEYS4sH7ZChTdbNa4ihWs9Xngtccuw2qWB4M/K6mteqgNU/8AtWKJPFmU/iYgiXFWf45M\n1Njiz/gMhGadKi6VGabVjoU1BOxw2JHCUPqT8zZ6eGJ5TgQ/LbBPobgvsz04U2UKrZ7Jxo339Tll\nSOYfMLgkrwX96hURjtFfIkAKEFa2JEOB8CF7IW6+vjYyCQCE/xrXntWyaKY5uQLxzD6OOmGcD8Je\n7NwQIcjLciRMGrcuV6T7qUVlxsg50GimPfTImUK3cRKhqQLGup25s+ziT/bK/nn3YDUDAAdAnIuV\nXqLuU5BM4PTknl+aiB9cqEwaR3q40jEJglcK9yFS3v3wSioaVSoHaTH25hYLgLnpIKatk3zW6eoZ\nVRpFY+ffTyJTJKWmbbWlMgNsSmQaaKGp+hGrlejAwT3GxTT7Wu2miIvAx0VSanBejGzMqpCTycvz\nsE46H28C/8w2Kx86ZczjVwh6685HEthGx8bDWEvVzOcJGo7rKXKmVTN6ImwBIb3hu/4olRhwdX+2\nH0XJ7fw9zbg6KfHm5AktBx6pl/bo54vHjroervO4Y4vMGCQ6uKo30FvzhH0GDWP5udAkbbKoZaEx\nVvMrGPm2htNiuCO3SO8+4JtHVaJKyjWyiw7EUd5Y4PvDv1D4eZnCudVnowjEHxe5Njoto/ZYgTDE\nSy59oZhU5AnnntuA8hcj+nvAj91TBOvaAlNKOSEdx0vdz2S6hHAe8+mZxL0HtQ09ydciTLRVCc8r\nA+ewCmZ8OqhGvoR8adeW2/4aTpI+V9l56hm2TlM8d7fz2FovPtXN4QgnGyt7MFp6e4Dsm6fr7/UD\nnqmBj82wXOGUbKBp99GNwNhlYKKbtA65HT+v5PiwZnir1yQFUSD1Ia6cFIkgLAqzPX7TgW0kKCFn\nssnyVvMlfDL7OFSo/FqWIi5K3Ji+Y7GW89afJyERSwZpul34/ywCc4fere+gQL3qVVhIp+63PIpk\nFBKgzE9e1PWmqhY4daLuU+AU7kIh6xNlmzVLik5i5Gutut8rDOMz4r3Yq4DVKYKP9AcOt38MIVyg\n9IlZioP6ru+JIrgCVZ7OiV8N5Ei+IdwirmJJR3CMSeV6xUYM8q0YQpkoqAAI8/M24KVOzbBbeWdF\nxrzu7njSGIjZ+MhCbNY97EJjDwIdI/+6D4zSawZzIx0uWBL9Kc7eqYLQ0fkri5YgwWrJeXhj8V6P\nYfJurM2BKeL67AbQWgzhS8+2BBIfA35sgyQMHb9wKE6vyGwr26aEUfKKjEuSaYH6uvkt32+7JsiT\nsiS0ARexOZkm0TFi+uGuNWfIYKsn5o+uKYq4ocVh2hP13or+D9OJv6Q1sEWYa6Wtq0Fkb+/PwOx3\nIhb37bikOcZjis1rjq3HfGq6OI6DZmULkrBB+Wnh5YBJSnT8DKKt9gpciBrYqZJpc6KqY57iJjt9\nzYxWjqWpO0ul5mkPaurDVydV7Nbv0UVRCf8pb9uT7JtdRXic7fO2Xd72uT/PxcikRmYGOJ/F/M/A\nk1V+KTF7So9xb9iRxGk78fG7+iXAmG8yEjmh/OLwEFmfBiTfNh+lGbsOBNi+R/JFHECR15LG4LzT\nM5McaAlllLiYS2Gn27g2w4AqQ28GXlkp5U+S7Yam8Hk1KToP9FKve6UVJe2kczb0ZB4d2NopM6VK\nUBSNV0pkh/YdPDg+O282oxoVhBt/ezj97lc3/Kf7QvN8q9sHclqMRhNPe5hR3zNUZxRsTJyJ6/Lb\nKNpMVq8+2PLxuqZDopVKwR7RF6+mQht8IhYI554P5lLdRYTtefz1TZv/jd+3fZMrlnb5nNxY1OoL\naCJZ2zKZZGqerQ7A+GKqcznHU6+hOxjOH9osehiPX73vAHHP5WScWBuNc9iVyvsoLQk8fCVo8E9A\naOT4vZEBiSEe4RbYLsZtqKpHdmCItsnQRa0dQmwlTT6Nnchh1dEsEnlbc0pcXtUadfigS6vL31Jl\nNt7AY4bWYlPuOnLISOIOkKT1CEUP4CcThjUB1FFc9U0CDgW/HZfURMcc6goOMqOAmgV1OCWqajy8\n64LkfARss//8pIaLTsj6ryPF3YoitBBsL3irQs8E61yHJnbwaHZO0jDg9pi9lclMUPUkDtEUnvWG\nINOKJraTKodmya4pjTNpfSnRdtcU9zKYZdTEqUc1Y4dxgnSvCHL0Nsi2VVUVx/o8VVsBSh1hzaRW\nXqV2TY5lFdQSabqa1jdy7v2FOhqT+Gn2Dj2IeGMaoV4RV/04fHx82x9ABIXY+60BFrzGVc8lYxRu\nvCLYUJO6mxJIbh13mHMtsWPrOOI4DrnElTgtVq2camG2RcEcaiq4LhjNzsSrH+T8BIRO/ZQJJlLY\nu3+NVzxctDQtKcnQ2rSmbr2quAXSMGe4mnD2mPp9vVCUEcOG8Xq+cEVUEDxl66xQDNMmZsmLTb+I\nYTHRIq2C3Z6JW3JR3RaCWn89oHtEc/vphd/G39tm0E5y/0XwoutbnuasK46MlewiGesEeifG6s8I\noI1fOFA+RjYxqfYgfM5OR2VqnJz2lC6wK+5sK1/JSQv+RkWoOcvtO9OTR/tYKeOGaiFUQgvy+v/G\n7kTqR1MUVeCU74NW72n43sEIEevOQ8cXH18suddS6pGWVrdocP/LVQZtbxL4GL3UIXbqkRcMNk8/\nEGn0raVp9HnvM6w52PXFV2A035LjX8oY0gY086kTxbm5B4qInHii34huY4tS7ipFkeVNzzUnm5Mi\napFdwiKiDTN0gNRYyTjfq3b6kd90zh2LYdUXPtTbZmQLQ3uXUbY9aWJKTvMURFpJiG8VtUP002jA\nZKebN58mTleGBMwHYUrOf2l0bsVxZNFXr43q6GHXEbIbA7RGaYklY4yU/zZGgKjD/9n2OvvVHv7I\npUha/0ZoKVUHgdZeLizoiFCAgoPvG5fU+tWluHigCUoAXXajvP/GIDivoGqotKHXasHYOKMzzocF\npsG5gd2b2VZliTytSl0CQkluLJd0FnrbYtFwg9kDANRm0CvTeLQeR6gUN4S1yS4atV0M8Ci9xo9+\ny7I++1PQig1+G8GEm3WJ9RI3800Yw4dfRETccSX1xH1R75P9JycJuiHfBYHoyqdyAKJ3DveO1jqI\ndTREsXrgKWC/5xqHXGcQn7HPcWKjxSw179sPYR7VT71asz7NPYA0vnIFYQFzAOGdev0dGW6HwMEF\n+x36DvgUSzTHb8Lmo9wxapE/ziI1MgBEuuHrYQMS+f9PszBQqi8G8i4xj9N2jDDw/Q0SW8gA3Iop\np3chS5jPmJ9u7hA+bvPItLCQkaBOB3AfRyLXX+IjeetCWSlHG2CcjFHwZ5Co3tqjiyJzkN5NUkSG\nwYjXVo2C/hVfgKx7kGKghZ57kAu1bgMvY1uw5c+CtZJ5rJtBjWqbTpbLvwlgtLRQ5zBCMbEbR78H\nbvYr8Ma97BREpTW3LgM4SDoAVpfuhSshSok625fU77p7WBj/PyVWz6Opa2lGtdMfhEm8yjEODAS2\nbZAy/G41sxHnjPETwY/gcRjOUCdZxt6MCrPkig/cgckJmoFyUJEiG/A+vr1SRE68MkZFn3jsonKL\nrnoedVjMbkntUL4v1k1lYncmSnCgebrxOaOEEA8k7nQZpS5+GD0HRJcoEsWdPJGzqs6zNuIw2Q8F\nc72IndmfR/7Gtscp479Bl2PoaGacHYv0zNyiAbLy/t5I/pGXEE1x3SxXiy6DMRP3pwiZSOepu9fu\n41pfag1WjbvW6k/J12tWHtdrZxWHUdnR9NMpsIxIjOi+UtbJoxDu/QUpTZfv9+31ioXZhy7bz/hS\nVvWIQE588OZnuWqF1w8mczO0YeGefDTXTWpSbmte68J5Oau+oF2WPfrbYMtB8xOTyYdgD5cpHRTa\nTHnsB+C9NtmhwqEG1On6U0sE/UjGKTzhftas27X6qljCsKmr9fRql4JuQhDait2aqiVynU1ec+9B\nl+n9Yh7Jaqnz4/2SoqJu6xzwf3LeaM2FWBsTJENJtEmMQTbkCldMq3h0KLEghla8I6ogu8a8weCh\n+JhpDk+7dqDs3F2wtNkLmZt8FINoUpQXxTDQb+LGMd7OYUbFWIO1TYBnyvqRePPrcLzEx6VTitJT\nBwLN0/k3NaYiaF9Kos8QG5u/JuWCBlBTY8sZQeNqoYV9VpQ0RjkES9WeFJECultzmjM8uEEbzvzz\nO5PNBcrovvQJsblUJ1xL6Oh4X8TcMnJ3ywv2pKFsstUk9Y+tAaXOD49va2GPBipf3TmbioIxaaEK\njqkn/dQMrXgFLhX4XdJpcElsWY9xwSansZ/DBhsS4B4eTAyNfC80qD5TsNbttHvaldZTR3vSogft\nThP54B2tkTO9e6Hofv8Nw61Owbt+pn8/+Exl+Pa1zipb1cbh0UUfa8x3AHqMhl2gzMJu0m75bvDQ\n6l1Ep9kOIZ0x4KbLZ2jtsmHO75aPGOzOquY/DY0zpmODtG2Tdi31OuUvZ7CfPzCaKLuO421D7Ajo\nZQUK4OA1w0wVilVmzVtjztwzMf+P76MvLBggm+QqB2aBw+iYH88lc0EL6li5k6b2O1T1l3QjN+76\np1sm6c+Q1kGpkHxrJMmcViwfBP7iaFwA/lPO/LxZ9MEwwB974okjaHC2lze/M8sh6P6i5/EPr7Di\n2vHQ5EY4t2BVn5/phX5vFeFnU/yAAzXflpErQErj0aYSfjNS7EUOKPV/5J/k37MQE6ClBzw0SWVq\nuczSy7Ti8vKChXLnQl6GBZ9ObG/gFeLmPqXAOry8mF23s97GHr2KfgANKwcggOeaZVerjrrD5EJf\nCFWc/L6yUfRfhRFMZ5GNTvtB6Y9RVxQalZymx2jmZj5ol5/1viB5/YLhFMoYnmFXVshin+E0dJHm\nfMZi2fhDypaf0Ksk3+cu0gkV2kYRzoQcL2BBwMGXAzA1H3iIfXrD+YBHBSXE57t+8yL6oWa5w60O\nJU3w3krylWplN2A765R1iImPuUmzx0vtWkgCeE3a7La2PZ+r20OXcyuH7lo2rAHRj9SNK5mAkpQe\nzyYOEuBw1evygEyRDox/aoOf7HRsbhUThc9cbyj8OqZMiYVUaHwZzpGwCbdrSthKAGYZOIw028Uj\n/Zx8p+ptusB4//PDR054FN4/brinYWgxrlqnXsXe+wyuDIEkv1KYLiCWR1dSmYyGT8fc5GTNHGXQ\n2HsNLAfOa7MQeRqS28ndc3esG/meBSi0MPpGooWurgIRt1lXz/vrwvS9lIT1nbMSwtx0eLRJIx5C\n8bE0bpIp8ZL8e+cozFkNkKYguV1hCi2LVNWpjZndtfHOPZ/MOHe2l+l6TRJSRZwZpCT8X3sLE2/W\nxvwrNqn+6lGGHrEiuUJPT+v2f9C1ceeY8WE2j/XlX8nVAqytx1kljNN0orpVqTY1lQl35OBW0Dfn\nrqWjo87XTPDLptEPaeNqlT0d283gQjcgqj8utkKZVk2D8EVNZdnX5+AEqk1TYzzPiBtmeT/mxbQT\nHo+oPVxP2L4FOWcouT8+W6dX9yYP5Y7Y3ljQ4OyXODnxXEwT1O2obTLK4bMFhVuzSWvwgWP9EC7r\nFLpxqNc53pFY8o/4Xu7UQgD2JzQolttjsZuY+8qEcesQ+SAWEhEViX5SJjd0pfhBqiU7ekMxtNth\nvZh07O7hMV05XKb8ai0JKxAX9TMgw4sESHby1slN/TWwGN76ElMWlqwjw9iVR6LfkaNt3WJW4nI8\nAMrVCkYLqNkrgZORYwpTkBopvoUmULAgX6wYrI3vICP9lD2oRtdukr1egqQ3TNsyARUC4ni7WYvB\nquAZoizTATFFWigKbQqFjyztKF/0DOaAcMIvPoFtDi+5PX3mVGCOwDR/a5E7GF7hreRktR/dQZfE\nkc7VWBjoM9YX9520vUg7rX3xeKZb4z2BijJLw+uwqhnY5pJvFSV8fvv+jnkuo1hFs+6KN9d2I398\nNLIzqhMHylYeC6AT+lLFH32o+c4i6xFq75wvMi1+s75abiKJlVXVm1mJhr/JzDdAIyDW4F0sJHWi\n0oP/hz9EHOdvMn2RARCc1Tj1MiaLoGiHjyIX1blbRg2aVZlh7gplbjJ+qXrxQe3KaDs8iR51GIDa\nmshffGDaVNUFfwJ9YFvVQF7CtzBHQqx78nKXx7X6D8E3dLh4i+jze79FDBjcDtY2BMbddk51kca+\nxhl4nrnAyEli1vr0AW+6oJpXbfUAboIFKDJFCIJ7ekAZDoCBtvt8u8QimUSWyiuvS0qtYUFnc/YP\nHjIdR8/hROdxIDBt3Y4k1HvB9k6dslIKdOn1aZf6gEThkGXOtDKrbYWEiU0+CXGRxugIoJbgUSQR\nu/NzRJUIPgIzwC0IWdIKfJkH8TzgEj3diXC4PXCRsYJaRrKwO3bvGed+nq4GquSKAyFALyU9Q/QW\nNDwDww7u7R7+YxRCW0FKclYIJqC9/Man7tkoB+f6++G5c5phKYtzfEHmeXcxMMA5AVRfm5VSZcGQ\nNQdbuVQyWlT8+is97cdfRScTWZc7/sdj3jId3HQ66RP6epNL/6qrK0ho4hdpw9a5ullZyVzvIWCh\n4rvrFESX3zl1SwFjs/7cQj+13QppzHPG2dANWf+mEW5ZNLzTVOUylLqvDrbXOXdCDCyRApWhwRnn\n0GsKHA15dkFWjgwJWt7+ey98TuxjDHQw3jEoah9sx4e5aIJv1t9+UKiS6mEqJdHlkOWOAXKrfZPJ\nxGscLy6Cy2pCyw7DzRXZRu3fbbq/7d/FcyafSA02eJirF8/BaSiZ0QIZiig0zsbZL71zQByjsFvL\nX/OZo20DPNu0zAglfzAj4VW/BRTTkDCMgcSS+fcFiw8ag65e4j0m82UFTPFn0ZyD8PeLd8K8kI0/\nYrnGNSSe1lg1xgsSClaXjB/mQRznCdhLIqi9ZIlICsk1yvnIHSlWtn0Wx1vpfPrLwdmi+90hI99k\nQ6fUJCX0wjc0qFINj3dY8KH6H4Z8IGTPqO4O4xBG9ycoeO8BzyL96wLwlNwWB/Rx5CD67IHaoGYu\nwsVfE4sXd6YTWXnAY8Nbwjw49KReIB01b5NhVdgGNBvIeLKuFvFxLjUoOlC0Iu0jEHRSUGUEU6BJ\nO6lC9mcs53SygToe2ZLs4Lx36AezgeRvMFuxZCSlfdDnOQfxRZ3DtCDtShewLfkqPFtgqyzQeoZE\nNVerkcXddXYFZ1CHh0QhaCi+/IuZ/p0C435ACJaEoEU4tZjy/sJXx5KDPom5DlY7lOLZEiriTKqt\nwQRBsT79CY2na8O45DRSMn/0K6kLIlrjQKyoihtV0zZxHaZccw9lwEKjtarJeEBSSiahG39VR8de\nqQXbB1k19q/qklWb60VaPY3JdViBCRMdwOv04IWO26NQ9lrAvqQh1F9+2i2MNAuMxHjq4/TKOHcf\nDDxAy0Rl/s96YgWANWwQGuy+5+o8aIkCHCHE3vnaHfIHRQaKO9zZkvtRXZAhJ6A7vPjsbzOSmNE0\nfbtvM6QYYv0ZlVLVdVAWcG66t6LtAHiSpdaeH44Ov/E5Kord4OxBcjkOjoJI4H1A3Ucnt0fUscK3\nm4BWhWWxQaLtM2Cna8wR6Zouwnm2lKfrrzL78GFnhjkdRLhBJyZ4PizdoCN6179hGaC+Qr4cIq7r\nN33gPbMFaUpwmTla7OkseMtFb8I3+nCGFIAPq4A9TPbRMYLIswn6+XLRwYZkhDElY8vrgmTcl+ZR\ngrX1VrNMC6ncTl6Fvyjayt3a0PjbacCbFdpfXVZmAvRmIghyKMW1liPM2eXul2qk/CoYzrUQhMb4\n898NeFwzKDO90yfcSm9PvGVgYgaZH3y3IMRGOUu3HO50XqcIWJkZ/A+EGhS9cTrzAZQTKoVHcAGl\nq5N8pI6TfwMHIuX8NCK0lzfytNCdpRhKSkPtv2YrlXcvXSgVXoH1Sdlu5vOxqM82+ZjfS6hcif/c\nQb8x9C8w96YZ+LvIEGVD2ozJ1lcY3Opepl726ZitURIDTLKrjoChoR4BqXFauQG9BrKXL0y7Kn7Y\n/enpoRww7PNuXNT6HMrhuP0je45bEWmCcYAtmwoaqITLqGIgMid2VL0nx9TJAbw2akApIGfWZJ4b\nSeog6ySZfdNFWsvkpuvn3rWq+GwXMZNXi2i8dZid4Tbn4BaAaNMUK5OhpSco8TVwarO9MssohIzN\nSMWA2fluMh0luw+udMf2FokBurrqVEWFNQnk8wydJc2Z4DJQXyuJa4vnBq7KofwQj/HvcCb13fXq\nRC2sksGEU/B8pgarDOJ3Mbv/ve8ZoKjxfUz2FEe8LNv+MCpmnI/e5vFmgOx2cHj9ZTTX0u9iAO2P\niTNR/A2ub9gT+nIjurAd2ftVmN7gDq4TBNKs3vavXnCgjH/5bohFLQMxlYCaATvr0bvhns6Ul3/K\nHFr83MmrCqEtzu6B8sHb3dU7fVOyESvItw6zhBiwxhHRaee6pwGKKicyLx/H9elhgk5gsjFvn3kZ\nPq4rxx+rzsRgnlK6vG8hWT60G4JEPtWShmoBkrN1gTWvCjRxTwA/8YM4n4hsJSwituB+QZw4h6S/\nz6QCqVVqHR5q6HKlxKH9yZXMf6795Bb4CTqNtG8/1cN7VHO0EkTikz3PQpZUe2/WQhzbrScpOK/N\nt/Th1pXNeWf+n94wF7iLZFuHiOgs/7hReqwk+HmitYUfufffEz8OZ78mozXcmgKY1s/fIKGgvkd0\nMZCbnnRHbRdCFjIOHZVgKgqPmglh6WZLz7ac+zD7G9NZGDpd38xUHDevzu6yCmVL6w/3u90KTr6E\nGarduqryhf8jP6SpTqGcEo2tE7bU+hInBWSSKVcVqVgHklPqmpuTT3nj2t/9xf5lzXPh51K3posg\nE/w7odLpNSE9w3g9gsOb61NCQ2icGwTAC/mld4RjV6iySl56JJ43bE7Zz7QVeg0Hup/eyrriLuZE\nlCQQilYoeUdZl45ZzeLX4Woyq20O8KDQNrGGJRV20eG9Prqf4gyhvClYBIsk824E5jW++VffUulB\nY7LLCzvuByEc3hzHdRfYR/uid3LY1CgfQrSk+dFnE93wIb4+e70XPlaTIbl5nm/QzCdwyLQI9zs4\nEsDTvNtS+sQT8GO+YfIoGtMc3cziXS+WSIOqZL5NSgC9LBZCTfqQRBvyL/jPnLloDoeM70jLFqoO\nxCCCkYNFml16voxg6+eDONHt1Vsf7NMRSXE28gR+AUo1h2tDt5XKErhelzACX6w4IwHqFaUN0wf7\ntjz8RoN3LakbiZU0flNKZkjkCes0wHR6kglfMIaZ3EN/G7FEp0qBJ9qyHQOXqQxqqv8+DUBZsCx8\nJlN1ygz18gblzZyqISEY9+4saEZ/Xrx6svkXQDFy33bk/RPxPl6W4B4xnZ7AIx9OZlZOfYDuvZzV\niaD8kVp6VPgonYDmwnI7wVeCfo+befScX62fbBXelx51eMgKJm40by2Z/D3bAu/1cocG8KyO3JjW\nxyo+zbkBPgDpGpcD++lOafp5/wqk5g0ZzSzfLNMkrq4pbB6TZ7wEJBsm4+XQYk0ci+4oHOwH3XHy\nUWFtfJcAKOoSRkXW258e+bXAgO0iZmFjbe+opffoGLN88F1I3BrUe7liYh0PHr+SMKAQ0+aGlXEG\n8+Zi6rCvXoaCIZdhZAuw8UXoLJrbIC0PuFLN+O8/6htWvWHauBigvm67SeRwk1KSnNrI5uPXCimE\nbFVzE6GWNRJPzOYNY6c40xg9YQ5SyC/ufh+IpkrJ78DV4RihOCCLbd37FBlwwwBND89HMUeL1J8L\nAVRfOWLU+KY41EpapZB05v17AUESKg1illfLGtVqKwcEJDPBPk+Bcg0olDtkpo4btQS0XPLhCozs\nHhf0JafNtNadpLyp6TrkOVIrlK9DFwrOn6mJ/zEl6DD7I6s4/1vr7sF6c+y4+IH56KQ4lbij0//N\npBDHNZoh4vtqIEPYXN3/6KpAIJ0H+4JxQQduuqfI9nGasLvBLVDS/HS8HKpmpxSfbTUhnYpGTC2J\n1kiiLBsfx9xPCc2afbfuoiuoO86oy0vzaQ+EDRC1Q7Feji+Svtg4nTJ0YyeVxAnjfk9pV8t/Fssx\n6bKfeCS7hFFNd+mbiCOvZw9lXtDkA9YGRGx2AXqmm4BqNgtuUcPqIfW+hjvAbyrK0jrd0jSZw3s/\nkwXbytokntFenJ9yLwG0rwd6S4O/vgBaP3KRS4YVguFK1LSGWb/FXJ+H3F2HefFRr9yEQKWpujvJ\ntsvXvr/n+87uaKuUE4XcHur+WzxcJhol8cYeqCJSnOF3wseq1E/lH9GD7ZQfK6U/XKPqqh4cZ06I\nB5avn/4ZKydiKSc5Xq2fd/b7poO2tHhVV5RGB50OnbPL3soK3/wwuA0sNocniss2gWM73c5W6Sxm\nw9+V1nma+j9Of5oVnCS+0LxYEkhq+53K6hqn226TnIU1rV9hjIEWpXIfUZHnQjlRmsM0tnmvgeaY\nBUBOJ8fmdskF0nr2KbX5zxVPB/NrKdUzqyrQpJEouWiH1R4tcSfVxsw/ewDxsp4v7G4iPmzavKQ7\ny6aMDzOpsY2r88vP3/3UkC+E69OKlHE0A2GAr1qNQ771tkwUzSjtBGCcZNNz6OWzYj4MC6iJ7MoH\nRl0NyzW3H+IjhI14EMyY6E9A9/9DH0JUWUj1MNAmt+zc2pFKBKzHYJg1sxeGruR/o1wHNQjXYQVV\nxa6vKncBKJ0QVqaWRAHao5/P83LlIYoYfaUlg9DvI3AWL6AK5Gj816SO20T7mTnAGthw4tJoDytO\ntk2c+nwuRyrtm3/MgFCM05FpaeMpIkwJwI+jDWjH+sLm5vo2YWvYZ/htjDEspZLYMHN/bb94MvdN\n7+FfSFAWV78fNWViC8DLXwPW53B7U1CJ/10UqB7uM6YQ1NFv1Wardvo71TRpnX4zPhYRPxe+UInd\n31pVzpSDCTiafp4a7QdqSCWc7BNnrU8x/d/ZwnYq9Twnmmorr+cUO/+seIYIOVoI8GjsevZA3Fnu\n5lO63wEqgPXppr3s6WpDoN5OCVVBlLZR2dFOa94n+xLIwB46xP0WzgKWcsiHflPKr7yOiYbXQGRY\nQis1BY0r8H7GH3lJANYfvQVPrjovPz5MY26uwbuL8Lc/8XVH+xlti3kZWooXez5jTxoJbcFaaiHj\nS/r0NV6EHZYz0Ir8bP7PKeN35ExlJa+ggrJ9Ll8laWhBWnFWe5gePgTjxskzXsA3wuxrVclpeWg5\ngnDST46F3huyrB5k2dSkrLXwrRr27odLzPhTcunuls+J4yS/hzGRll3COjTEPEgwMoxHnHr2R7+U\ngK/GYcvwdDN89BohDdBKuXqwp/CIIteRJri4s3zdMQwp7X6oJdUOLNvqY31T7yWwk6MNMfFiw5b3\n5+d2tyxmTh2kqwh4mI5+uNDWJkf3lMPN0whsOEzIztjLJWsOBlNAAJkWyFrWGFjbch8/a/F+BUhy\nE6fTqumwXOXXaB8JqbSvuuyltZTrsLFWEGFU92C3J5VB9svYePaD/1EHjTDOV6E8EJrAnVI9UgVR\nRe2/6ILPALLhDGVNQQEaK3nb4XNioLKwMpG2vPgiW3jgWVabjVs42B0RS7m1MWXwvLX9mMYX8z0t\nxdsGixCt/k0bGOWY2uP9x1Efta8VytH5NeM+H55vovTOF/nH8PQSxEIEXQBnCTT5FgAF7OQ8k63y\n7HrCSupfn9OyY2/YO55utmiBaEip0wkh0jvzSmPLjsi1y/8KZxn2vf0Rd0h+7fSfm92qOQzllzCY\nl8/LJtMd/cEY84w2bv8UGBMPwM+CsL8cyou2+opZh3OY5hGOm5i6waTuh5s313OJk8QzVFoLflHQ\nPG+vx/jgVbsIG8n07WYyFV22i1D9S22dqzurDt998cbavI0zYu9cBjBF0QYLEcnSFjclNGeMcLM+\nsC9lzo60UGJy4JxzhjekLyjN9csbUDmjCO46KlFlNyehC46ScSdYupy4C6x+WgkqkVxu+wojSapP\nL9585UhWl3KTYUsk1A+IlXGfaA3Tu6r/h+DcPxD0kZxRo1exCG4W8s2un0dBtlxCjX465tNhiaTr\nqiiAS8kXX8FZI9mfgS540/9UhG987gF1AL8Qc1WuR3R33nMCYCCfXQfyT0HmpTID2hLh8mPq4Oxt\n7B2jN5j7IPOWnN2X3DkO8E63QfrjLdPvG/Rb3vRdTixOmQAxbrOOtKYH/oV6X0Qs8qK/c0N9ZSU0\nESSr8BH44Ae/VbKbes1GIDAVoYIDIST3uNHAxO44O9hp8v89q1N4LvHT4hO5XgpY87BsUsJp+WyY\nq5J9c+kKVlnj9FstmruwYbApwV92OLOWJhdQpL+1AXlQKnbH1onqC4LJ4bJjAWxEMOZcuz5Vf8HF\nweINzuo9GtHBifotA5op71Adewc3WZtfDvB0kBqJi39LWMAIXwcDDxSRuujJx2zm0X+wKSRwnlOg\nDNVaeZcNKohWeNcC66UjExz9ttZifeFAuh/yKq8sLlYVJ0g2jl0pbvA0jDKnGMaWp0ApHptYnoAb\ntjUSYXhQGug92EthJWGE8uWsByKyA9N00boqeekGrBEZ5b34m2Mr9wdR4ffpNh9mEdGsBXczKYru\nXxMLeyYqnU3JmwQZZI12EMRljUYhVyRjtzmdP3/zWLh0wWso4t+2rwb9gyG/iYSgAowBXpdz7Ki1\nFcAG7GC1N5B5NeqQ/jsYYWangPh/MH48EMu+lzZlJui3jIoKniXwHquLboyPUWp84TWb/jdEJhbJ\n0CBLqQTofvUhgPsYHpmyhw5Tf+qQQ/141Ye96h8/7CYNJxKUjomZJ8H9KCdNyvCdbmhE87Z96kUi\nz6w1ot7iSx6AoONVaUrPFcvtgIF7gcpVVzAj43eMbj2VwsiODlQ/ijjtMhnF6aAwE0BgQ15oQODI\nFm9MMpVbTY5ai9eEAvDDpc9WrDqQ6c98AG2sVXfgRTGm6Lf+J5R+lGPsmUx8Gb/EZJLs8fI8YWO9\nkzLqc55KFZTlqhfeoFLo/NWTKpV74XaFm+YFctpTnqKv870XOVl9l7E/VD/kcJ5rXyJ8HPoQTVta\nOqAoY7nJyPlhYAVfjfAEZYmYoG09SrnGNOonRgYPyXH9SUV6RuWU+7BLWW0DuOuti1QUV7U3HHxs\na7VAFp4lcelZuR2dQlHuxmUKipeYNW+lh46YK2Jq4XgyuAJS/8LV4cQaF9SKp3M6sg/D6PS0u/iP\nTk9kczr7yL+Ko0P540R2oyyK8gti4W2bDklXoq3KerLKsb1OyyXjV655V012LKpieNvdecbdZdHt\nbVKItGHNtch/X2Wmzrn++ufDfJQdMNCdpaW3XuFJ7cckICzkQALwnRLQ3KYqpRVsnvtAd1DXlCnS\nFhaEBmxv9vMIxnzipkdZJh3NDOxvnUvBjq1WIbn7NIeRqkTjmaFGoU1lOu1VBN5holVQOUymrN8q\nOuO6/QcAiXfQd1d1pzqK/qWi4Nqyf17wt+1X0LBTPpSRFycYILIQJ0NCwBRlQfUg47LC/CWZYE/z\nbero/MKvMuxFYLjPY7VthT98uwIKBrJWr+/22nYFKN27btmhmc86kBcingXxGddifEZOMOo9r+0v\niK7IaiX0Fk20yn4uPyBKDn51jXUSOWZHTdnB6RRKTr32s8BC0lub/NPue4F+l9kdpp+9AxSdEEXZ\n3Jca5uBvwQT/PG3nSLnTSPeFq6exVh9xa76G4ubYxWTZQm8/9VUgyeECfOGRcWSGsRFmLyqSa5IT\n6JARjNn+EWBDnTf/KxBp88L8Gn0c+h665z05M5vDAPYvKbtFrBDpfAAIgGGpK1k6P+4DddvHCiZ/\nBZKMmUSbUXqdpOjkBAOFXxD2MXT/tFcHPhDc/jl0vGgfOHSJlKnfZQk9Qf2sX49pc/6GsgUaQqbq\nSIfy7l9g75HnkM057efINmkistyEFIPDFlICCSbjMAeGFq2enMA6JJaxjNpBHpfm3leReAvtJ8Pn\nuCNE6XdJvPBDrrdw+WrtrkO06CObXGMTy71oQPoD20xQ3rA5WKgYOva+oct3g4p2HEYWC1KxoT6B\nB/Gm5Pa975AKWtiIbrZS/pBWAE35CbBk7SjG8pNcCD3V5bEUF2GknrfOk/X95chDtE+tVr4F0oCG\njnO0ssaJHpaWFQB17wxrpPT2Fl4pO1znuWdml7o7Y4P21J+3v6jgzYWOZ96Izm1E6aNfGck8+Q/n\n9eqgVUH5I39WybVJcF09sPKDvmtYsIqsJrB/OujtEvq6Ek2pAWqpYlgjnuxHhsALKy4EbqE253In\nslIW1vrvCXISt3CxWAGbfKZJxl3c0yJr3bk/wKjYl8+wMgLm9s6ftps/GPT+Wwkf279IPlhelFbe\ndOu9XXpe+LomIZqQ8S0IqULcxGfOUx9N+BoONuPLlLf+kW/9+pbyOkCeJFxAMhyDpIu2odE8crC7\nvMolzgmbnPxjj+ZcSKvfJsFTl2hOq/nKAoBm7amjktph/mYwk3kC54PgF7mUf8Gcu1GXZ57udyg3\nqCDtJcDVeOgRZF+1TfdovyUWjaShs3c2yZbbGoqF4rgapYtYHxsuIYn2Vv8kaJ6Dg//Gum4dFN2x\nnJh3LV/7cNhmag141D1lxINHYOfZGTFEW/8ufUvn52VlavJ6W6ukDnOP7AvtiJe1GBcWg2QqxxeV\nLMTQkREl7Z8TvNtUZMX5YhyceLycQJjohm9bxRem8alfCqJXNGG7cPY9yR1zZkknPW+iwYtq5XW6\nV5Jjv7Zzpv6KQZPHsBEiPy466hl2heyB/Xfg3q/ugP7vDT8Xpu+tnW81w4Gpi6bD+JRKvJbp5Qsj\nGMxJ4uwsMK0aGjpLf9NX0vhMTKHj+ud0GVpzVPj7BDKGQDA0dUEDeSjFn5KVgVUUvgOKvHNDbaqF\n6IdD4gTw1O2p1fuE3hkPikU3jXEkSvTPZoTC6Lh1zFsIiMSv4AbGw0n66F6frIJN+fRt2JgTCnqw\nVW6zyPR+iTjh7K3Un8XcYRdQDCJtfbEFPz6Ii4AkBCoMGFlqw6Tj3g9croUkCJp+dW0e/5/1+/2W\nJoRBkFvlifbh54wEM2ScuLVyfs60A0AovRv1sVPE3uIncXsEltnysXVptozVKpcqMXjPrbLCEH+t\n3XTSzNYzmhZ3NNw5lMd5NzxcDcptkKThZ82wJ8gpk3qfDbz8ergXm+rKJw6/nHP4bIEl/g+CB1L3\n4fLMtmaYxlO2Z2/HT2GkyKfJjRmae2aQJw4qVAxFigmJrogPH1sxek19qWJAX9/+qcYHwpdUOXWX\nVqiFki3trExLMGF/AdzfRLSPX8+9WqX5QO8zi5GalkPt6jD3SnpMYPziEt2wvgb/0NniPzWOzt7t\nRjij7ChcG6qJY8q5h5tz9JpKJeb5Yy4/lI8dJS54T8NiuVKNEje3+u9D9rB1CVLrDRo/M0fuvGTZ\ny+lwgStlOQVRiv1I+vwIIqTvDHY3J5LAE8ujSy+TJhrlBcqt2HKPJcZFpq8dQSau6KxzabI9Z/yG\nwJJkhr1R/aTeIzBH/tzGVpAAELM5xUBeQv2VqpJUfRg6mB3Ls2VQ4rCXPfoVXDcDBxY8wkrEnnle\nyoMS/1JhwqFS1gwGXBfxEvg62PTBuotMlHgPoCVCWh0hHQ/gcatMZ9lfil2bhoh2XQmK453zp3BE\n3IiS7Do3qYQA7bb7MZq+HGJXjPG3XXreW6HaFqu+fe6l8AEKK8Wrl3R/AXuRZbTbrXHY0vXRI9q9\nj+DBe9nUDd5BPGKjvtWqGuVRWEgZZBzjDOw5sz2IWIBEVYfICCctFqgBz+lJQ5KfEvkEwOKuqTP/\nFAU89ey8vzQgx8owABqaul4vim7CjSgwKm1qtg7dtcGHSSjrLO28sXcxsAP5LKXWyIBwAkQWrkJJ\nBf8jqJgScvQMpcEJFUoeh9wt1O/fQhkWhoflreAoaJ/t1zkmwBtOpyCZVeE4OG2EhUtpf2gzjXuU\nLSLG+HDSNdoAiNs1f3tnFKzWrG1FtnIfrf1EYIeOGypQppvFumfH6Ak0eHB1BLSNJ4R9yU/tx9D5\nCagKiy7eh2YMXYYEU1VMIfd8Kc6P1OJo8PU0lCll5KXRxPpv8x3tLhjFDvmxd/ItWpHkrFouMg8Q\nySMqYgT3NwVzdzIm9hPd7LnrqVGsaXnhKH3lHPzOms+zQmXtKo5k9sDblIBPUoCtgGc2Da7H+Ms8\nWnvCf6rrZD1Eeh8MAy6+9lZhwxvgQYP6cDkNcUMSi1Y1zZZVk8PrJdOWsRAC8Lv77kFGV0Yas2BH\nsZyXB+yeiWBowqGByluM4arIWrYK8MgAidM8igYifhS3Fy/9pTZyS878xwwgIpYadc/ry4CqaUpj\nRy3KG6pf/VfWC94FP/dDYS3hY9QIeSJTCSLrj+Ahtvv4wkU9+onFXSwaM+99nk5BNCIxPZnEvG9W\niSyPnSSCSLXySg4SXxDS8xuAa/v7ki4CLOsCCdxmYG8oayc/zqsbxV38kBbMnCf/nolP/PX9a5pN\nMM1XrKc/1gXU2w4QziIIpyEtlrZNuvS1o71UsPw4WlytogRFT+sK16+X0UfeGkliopUWAv0U9pm6\n+mGeKB2oZvbt6f7EqRTw0mvbikqqTS45IuugX0ODGlWfALbi+UI0OfjArIEaoJa60JWUHJ3JjW12\nOC1oYbs4KcyAbP9MmkRII9eO6arq9j3r9XY0/JG/t6AvuiptICCtpmgZG1VaOWtHiaJp7t6MaIqr\npDHUL+D51xgr20sJthEDE+ONij9TqCVdBuFoIt0WKpcW/kE3GJU0ULLlvivzt6Bum+cpY59MfyRi\n4dgGIi9rh9Z6boO/cLmGmLCnVaLw5kbuERrbmMw69UERtCdQeBrPylXiAuhBmFY7kuwW38egZTav\n91qd6jm2bgaTWf8DGS1lf4Wo8FbBOhed9PHEQrro7sJpXQtLBIx00KydxxMruvPvxSr2R9unCo+C\n1xluNwPdiFPDv2VUuHy8gndaMUd9T0sAfajVbQ4LjgZPj9gL6G9lQelfgNRJmjC3tnOt1hX1c//o\nAIFR+9n9m2CIzr5CFBhE8VSFaLQnQUjWOUljt54JOoOwQqJfK3hTkDqunKtdWguDEOzOE1idhsUG\nZ8059UOD6RyjnRjg1v4PBJI1p5a3FjAFcoM89kd15WydIvPRlhV0SQAGQkTn/GbB+mMksWXLeAWm\nG6vkwxH6O7u4IWJ5HImrYJxZrISY7EMXNdOuzfskCqtBribLfKTJHzk8jRCqwKjHA9M49k/g5Nhv\n4RS6Za0A8DjAgjEANPtcGvFkLNJVaO1TIJbW5+X1OmWwpv6z1sV6jGKG/hlswZhyW4J5EZRziu/K\nl9d0epheKlpg4khqPI7gRQJbXcOPrNgCiHC4BOeuXgVa3VAl4LSlE7uTu0WLmzkoHxH28dyqp2M9\n1psH0SJqEpNG1FwRZcnRaNdKXjIrEAqxCTU4Dd4ZzJSySyvwB0lE8+1GxRbapddj3zhw54nQc7cp\n97BTb/Rym5OmfOifieKB2/14M7oD7I0HFgB/8P2NJMMFBzoC9aszfLhsx56uZ83Q33VDoDB2k4m6\njr3uRABI61imi1Z7dRqC35GrL0qMpy9kSZiphp/au+U5J6OV6pJosS35z6SrwpDBHJwbU+u2S07C\nIoylBmvk4A6Ivxs0OwtgJPZSaoPH20g+IN22WIER9r2Y2ujDurnToDQDpCaGG33Tc3AJ/6VYcref\n9So4kz00XQggRLGjvjAup2W4Otz1nJZeutOpcZqyeK/qFNP75MZSHvUNEOcjsrV375n/fB8ZsAI4\nHvnJ4AqPdfWWxidDkNEXRbESccIrbD5PgRIz45MsFkZgW06LrmzjmjPR601WUTRKYDS2W/VmwBPR\nwjY64zfZW3TfP6NyhRogtBkQ7bPx4VLR1GIyyuk4Gzux0j7PHg7QsG2MTwzooIXUncF9WS4tGptu\nIq0o/Vfessp5MNrYR1n2INpz5qZexjWNC1cnDMCY7pMtDluqS5T3Jzz+5cF5brOLUWhzPBlJH4uB\nzHoEWGt1o54Jyy60QR53m6GsDQFdb2+YVfCWfE6TXlbfQpOzbLbjJhNacbePd6MZCoEFH71FLCky\nTMCRDIEg4WACXTe5f2PGwbRE89+PWnvU35pIP+bYlG3/t1Xofp/dNoBHKvmfpybTI/TxhuCWmPgY\nRmKUhTlkbr/zJTHXLgcaprWTuSK0OTvkplhjTcinm4PesYzTfl4i3TUxFonv+83kgp4uVdJbAey0\nvKrbVpXZyPU7DxdlWI7+1WNd2IK5BcTQWyVBFhiednIOaxT3OpEe44KhwxEBqnvYT1A8mgwiXR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f1/Uq96VN2WVK5EExjAZe7s6uyal/Et4K3omAnk0TV9E0WGUp5ti9FOD+iumbFfTDES+hNRc\nJgrC5qPDPzL/Y4FueLb2xg3NvllZsAdHODvmpkdxw0Mqli3tlnDTrkjpajEMjnp2PY1C2cnYWgMp\n8ihSXL5iOx/8U8W4FghaoCdL7nvTJ+p3YJjTv4RRW5ho+lqovghyP0IxQanZXSJDVyQ3MoJh1XwW\nNCfKNfkp31ZFrC51/IfFAll0lYfhgyBjuZRWPfsWEZHlUij+mFN1AALKhF1IzGJop/YNMZtZp5Zs\nAtrWTWaDonSL+f+EuMpMkvIHGzBJziq5MvDSGX/CzE19+LhdiXzpf9tj1/C3Q7X2H8jdx7XwFC8y\nTyxYxc8LxZ5JVnnJucbCIH9ySVDyrH3JAQWYl7wO/7dKT4l2DvFZ8qb8TBfvLVMSiOCILeG2E49O\nZJHGrLn5QA+NYHgkajyGVFiKNekU/49dOAz1O1vSmmEu3Cfmtl0oYfqg9nCzoGhQ+BAtXAb19B3r\nUqsMlazbE1Cev4nU0mWPByMIfFz7H1f5vmbCrFzgh4yAZ+GdAi41WXHKFzYLzPk0ye3NpHGNIsdD\ncS5h9DTaeotSe5E+8dc5ClzeVyyEzb6Q+HUtJ8M4IHd27UxGBLTM5SPcEGOv6FH1T5F3vzYUSysp\nFTq5JFK2TGG+cMQBohqTK6FEE54UntFqXWCiaD+xpPTSLwRfrd6vBrcEVdKnovCO30nDdNKjJ9Sg\nznHqQHKkOCQx181cQ+0zqgzyJo3Xk4MNB5ykA4uNTC1S34rpxZqyjbOCSvTg0VHa48iVnShFDalU\nvlaQGJMO35+515lMfu0qnh/osFnZhEj0TyiC255TcAVZtZrE7eRYVDD21XZDOCUjy0AwHi+vmEwn\n/MoP//e8cHMCfxIJYmFvI0Zu5dOOF85EAL2bsutcbs9hVWHtGmkedS8re+SCM/CGGTpkRvQTkZ8j\nQnMWkMa653N9ZMRkFtg8+gc6AZaob9bXnfxpQo0yZglzohiOBpJCfbkesc2y3VmH6svGKydtAeqj\njVmue3VvCXko8wGRnBRfvUUN8JOe5TQAW6e0VBdkWmZ0n9jTxI1/Re2jgj9ZqBBpk/YfJJgQwHcC\nfCjH8/j0W/UFswUNVrr0Y2ntvHWHJfyFO3V12ixzwDNs5YMC5CTDyPNM4KaSPG1jHVmKEnUs34Or\nxLxT177GXydg9/udU6qQKuWmzRVl0AL7ElxyDpvOOTPt5lPJU5BrtL2Z0OyrdEeX4Jl/ZTWQT02+\nd4Cc+WWmIK80c4uqLKJ4jvya3fPuylC6KLx6UCx9Xr5tOFtSERSQANOOG0q2h8Qyn6M/EV6HLCp+\nhUYFXwQt//FuxGmKmbxFdFnf67c+qRdpcIAQaceLBjPPbdN+h8z3g5wrbQgEyvurksp/jXVrOXI1\nEVELkUaqKyhm00f6gX78Tk9nTITkJp2yEdDZonlw8V5cjtiR8s0qp/34DaeS/Ku0sXZ05NUD97+f\n7b7uy0cuw1+gVZfPzgopoqpWZHIcBuAItT2h70mfg3rY0KRnABDXIk2ZDYWMQoNHaA2zjk+NZ25/\neLBt9B0kPXm8KRzXyVo6HiCGF4ggO/676hflNDd+8Wpr4vryWp0XaQtwP2r5IJIjfZeYl15RzABY\n7nwTC2cP0zyTxg437zdDicZcmyUjc9QHtiq/+TmS3VunO9P3YwtQ+7AznwSjWI/dqTxm4mUrk1hl\nR9UZGGqff/lbVur4HYhJCCyj81oYyfDJHuNnU4WreLe0dkEJOqk2jMR+zxPYejZ4n0OtbtiYTgM2\ngMCBfCq6+r1BytQ0WEnEkXAnKTm7gsylPElObyMpA7b7ICdNGe+D4g71CglfzMonv+V+olJg5xUJ\n8rpWrWMxT8OEK482g9DFxendiANIZQGPZaHo+hs93f5mKwYKxfkXx8GHMsGa0DrzOpSKGa9iVrpM\nnZkunhMzuqtAeI6Vx/v3MXBcIARnGhCDVLT8kMkeqcK9LiJCMwuw0Ues7AJIGgJf42uIfxRmYErk\nYEHUrpuoB68KOtV8KeBDEWUT+Sm8uinnrQpSjIf7pLXy/oSJ2QBltM6g0C+BMH1X170JRaX2FM+u\nRxqCJyfukqNvbqy8Rx2GasQepr+t9xCI90H21xgNGCzyytFFVR8nOCzNuEI94RoTF0HJoFJgyi2R\nt3FuPfjnhTaJsPsq2lHra10MeA1KpEXTwiJObUWFpl4BOpPQ4up0qH3KjtIZYW/unmZV35Gw9M0Q\nVieePKlPzpxDm/HetPwStnK+NZxIxe2PPHMk8NIcpcg4rOBZRpxuwoXP8mN+O1yQAi9ICArlGG/I\n0FWgA/d//LhSEh18a1gyOVQT+ZFK40X+lh+IXaf6MRuxhvoW3dg5RPbGRupSldLFyAhsefYiy+zC\n5wP8L6VKxL7FX6d6dJnzHK+kWv7ec4f7E9iUzc3kRVhFl5nsvbd4uweRM1BXwT+c5b21xsWdzO83\nM231hwF13fKyBP1uJeWhpiYDKeT1ZhnDJJCJEOqqkxXwbwaSC2ZXpl1o3FFmcFjKjiBod7fdeEgL\n1EYTl4A//fhIDMTQ8OQ1od44/hJUAQa/vgB2NSvKNjX4q6ohGDfCxoqvjYW55vOwp6unaW8FG9/6\nMrJuWbFAfkDheLVQc9odRtNKKLXEMeOFXLALmPBOA+gBofQH7j9zZB8NSdierDhqZ9CIns1J6OG/\nNmfU4AilR1XEuCoMIdbvFyXa0y7IZffERyzY5YcMAwfqIHHlITvQHXz8qZCTVI4Ht1RIEURI/Ff+\nee1FiJ7H5CvNv3vkmQI7AL7cb3djcfhNWra0lSxFFoOrrZ5XTRcsaPuMyUX49Pago8ROMC53izCj\nLUfU7zeK/pb+so3pmBW80s6rUGA5nmSeH3b192fVjA5z99pSn1rO0uACeZ8wp3uwfzjj66WOVT6s\nXWQHpWbLfn2DW5dsrLkuQ2z9R76u7qZc0vhwr1jUkMIWK2ONUh1Z+gRZF2DK1pvJ3QRVDtgGv7w/\n226pay8Cqj3SY5Hkc8QRj6sOTW0NTCy0NnhbJiybFhTGDLtMbIt1pagUMbpueFyg3EiitBvKuHMa\nDGobWaWWw+MlbiXWRQX4w6qNiAI7cb0uB3tl5mpLNzIUIO2EK25MnFhVgIXF5wa/Vs4JBvKVnjkd\nyNYJAoKEdFh926jHcGUgnSkhNM3+AZMZbza+Tz3AS6iDe+saUMbIGdOcNk36cQxnoYw/JKPS5USA\ntEYvm+V/SQirtektFG/Qovf70y9Gdyp/1Ry6/lErBvpvgfnY19ipuI3EGL0tGlA6lK36eWCoURJS\n8r4q/daScF7H/sxwkHQVtQUWcrvlECm+8wG20yw0LB+3GLR+w6DTqjqfWztrTY1YAAgi7mjMAnPe\nS3ebVrUpoMt7NhhtRSc58HVVQBaGf/DTJ+xbcPPEWAhEm86I9Vf5yAns2XMvVgOwO9erEDO4rezz\nwprgG/L37pWwK2q7Us0stRNzY4ttnoTm5/vAL/HwcvKxgMk8ajkNnnuxrwHNnJp24QpWsxCAtaEj\nUT+PfVEB2q0IkfzgHREYjzdhyF1q/qcxIoD5G9yk5OxKCLdQOmUgUTy4Fyi/A4rnrTDeZlwTLTjl\nG8ggsnqeIynv6GQTvB27cw2qq2Il+CUWVS3Q2MdMmTcmw7eBYeIfDwmOo5IeztpUP+53C0FwOmxL\nflOTOaa6kIZhI/obBdcgDtCPD4JLHwV5B63gWflqg0MjhlskwlmOvnjDSYbHfHiRgGxw4sN58lYK\n/8Bj2I8Udw/LxCVfb7ZwGWct/p1q9OCXBT8Ja0rLtwIJygJwEUh4zpHgerJJuY2DK2cnFgZ+Ac33\nfuYlbRlifhJZdj0hdATkKxTdgf6Lr4TQ/uNoJcLCrEWEDrjpMjJYPmvKNsCaQN3TntU8eDhHb+nv\n57V9i7eeBNNFc2dNKtmdHL4yavLnzCr10f/gGXqoXM/FYzbvEZVf/iWAm3obe6uEZdJUMV+E0lc4\ndzQmIVyOjqEQH3XK3oTIUJMZQsJgsHiqZ0xRukhr2UwPqX8JtGTsdT7r/wKET8OCUANUWvuHvhqK\n6C2pUXgqs4SsN3X09g3YXBk8kpK+OMccYte7bfpElrkl4Ps9UaeCsqbFOO9pCtt88WouipR5dNBm\nbCpLXNV2sIzUiDNzvn6ezlmKMwMeCNLc5dfVBybIjMKeDDFpHJe/YTWgXHy2AXqxfGJf8fvLB1ny\n+k7JkP8QlWf4PftItA96jpmQyO2uinMkWkzcg/rebWoCXWozzaEdCDj9QI2INYshOp6Y4AMr5jEC\nsWTAP6/TIKdL7ERlRXyfuGyBNLsEAyyzPcdHFAK1MfOhJfdvBTZKo3HRwz8TYzeEE9wMQQChfQcq\n/OSsEbBs4awDKqOeLMIQo0vcrf2/U5REJHL1UGupt1jX4GQcgQl2k9COrAwQtUwyezUqU54vPkFr\n4rM6G3p/DeuMjVnSeXzTWb6w2pAuRY8Y0jf6EFJ8a02bmt2yAgHfADNbIv2B2D+8A1EY3EMANBdV\nPg0qrBc66Zr8aRs7rH1ifYUGq45fczcEavqrVz7TM3/xh7xOvfuBcdQUgbjBWJqBJ5l5bsvmPVtr\nyBsgq+VoOJQ8Kdl7nOowHS+A5a+8JugPcrT4bf5jSSAWl5VAJFE3RtI/LD0JixjgmlwdsWevJVn+\n1IEkotWlZeJkI7KAU4X9VIpdXxltZRevzV4vD8I+qGC+wAeNzhv5ZLaxj8GqX9nIr+/JZXeP4sNb\nhpTtaahN4v9WQ9cLDQILZOlbpKQaoMowvDuz5K2P3sm5UIrsmjyLcxOECihTP1ri/UsANM/l8qWe\nuwZnIsFnDYmLdJgWezjF3H2PFEgOQ7SaWhaBAP7BWoqgoHCKQFkID8TYTs5poo/WrLJ3Wd+4xs3I\nuzXsJIFAYlQgIc/5wIFP2eE3gz5PBnO/vXO3ATHAEcTRJMGX+IqEoTlTMxMiJvuqjBtYGE7pYgey\n3dg6i4nM1WZsR3c1jQjmxGGerZLMLuuzxrFlpU9oJwMQylpoURE2CVh1u5euHIjkZdEfu13F+rfV\neVVz8jqcQP/3XpUPowFa0MctsicvjZeB6pPMNe/5PfaDXux4xFGee/ZCZXElJ8nEszueXi+AZIsm\nVeJJ4zX9UvMBe5+6c0YWnuVwqp9dMkaLJyXXdABMSOehE9HNT5sSYV06L8UvBC5ndPv3oeMbYZtG\nXeRT8KCrjN8s3F4NL23SWEZ6gerNIY3AEBLh4XsrkwaxsR4NTRHIPHBMHzrIMDygQ/IbTZsbdrBx\n/x5MXBYH+BFhjOlP0r8uCD6EX7Y3nLT8dLLH9aKVTwss6icU2OLx1Y6k8p3YqOU4s4Vvclmjxc7m\nMVsqBdCNQE75rZx117UttDwnkyF3Q0UEAakCuwce2+uTYbm72gTrKufHeW0s+MMrqKJoQ/9Hzj3Q\nTPtJa/ZuyTpvDxVPMeZgxj/7TA3Ugn2/V1zB+WyK7qxLy2YNhWLZOJx4YyWcvcRBvcj0z++D0Enu\n/j7kk+i9xLqiucS4aAknnT3Vl06aUVK7dJganKJYPGCxowMSUW1GirNUR2cyP04d91YW/BkcVVY9\nPP8BKkiSBuRutQvYG+eVJ8TqIYTczQUHKVnwxJdKBfQr/tCE7c+BhGfAbH6ZglCAjdJCnDF8Iznq\nlR9z8ZvhjTFFHnclKWjfM1PnYjFlSOngku30p8pdQeGD1u3lW3EoL5IgcB1FvnnGGcMYOJRPR7EK\nxWukdC7MZbY05Pft+K8dAbM9R6vHFsYM3ezXZ30WN491e6rplMieB71wLDMrP9RFkh55hqn9pPMU\nBJSTfLMWJShEVClHvoZy28AxQ1Co0AD1YS0yh0Aw8NetSsazDHZyu3TZkKk8yRHCe4Rt4LqKwj5F\nZPms/tK1YLAYomWQt1k7ycVJxKQPeOGGP8On6FkdN6IyqJKc/rDyq3/YD6s1hBi3dGPPpe+JAwz+\nAHYDTvm1H1bWpppY/kaXClAz8FNiDKTjAc9Yv7CsXaX331J7EzKuf1Q1ClT+x8LpfPHZLPexO1Sh\nYN4ceMmYXjq/+o/AZ5UCHTKIru0daH+MGJTnLH9Xau/uL2QNhRnU+c/3DbVYccLMGRy6GclHo1tW\nd+A8MwoYSrqwB+egtrblEFngtKkz5vbawcLRHcGfrUalaimmWNpj10t1TB+qGWwpjWo5eOg7tGY0\nqMdjFbMVH3Jop6WcDY2rTIwxaMT4VJL8JNKYWtABYlQPrJQ15K7hAmY35LzzSZ5cEwrDb3k6arhK\n4NOO0MVJsf+MSiki+dxMtoR07jrHhtDOsAPWWeoj8CUpii2eps1QaAzs9PiTAsQ5qIO5ybEZ/cul\nsb5/S6CedWyuKUVqqUN+wu9OpDKoQYDVzwacu1gcaZbGToSSXHJoqif2q5Ua9G0A9OQ0MUFHQxdj\nwG6LfGzpsPhRGspRMmGNDA5yDTvmwY7ufSUETRZWl1Dola0Smksofhp3DjyE4q6CAnbCPMKLLlEp\n8qwPzxFCDGBtvYcwKRXDxBi/+qs+JL9Tixz83fyFWIdUtSjLOZ/S7HKObw7zhqjHihsvU2X/N9ep\n6xrbMySZJAVA2S4kF80ohKuSZ+iqkHXvS4VA+A1afGHzo7SP4MSaLryDJDOKwWiWBHmLqa7c2xHh\nnlxSagfJIQasmq2V5MABfNIvGl8TWkj/eOzTQOOSNiCFOnFbM7xdfFCyw7Z3dUzhRyy4E5T1Fz0W\n+DZzmzItHOq37Ucm/nFbQnzGQPXERtVtzkWW0/ggauIzmFL/i+aPsx1dEuDv2Vza2KkBpeR8+u9H\n/F5SdRtYbTtHMPVUrZjDLF9pklKlmWA0n8Nhbw+w/W8+riVdtZsCuvtfMMu2yz8cWiZaFjUCZi6f\nbmWVVmE9FuyZV6qRLHyPiKL13XRz68IgdjyNBN6hPNKPj/58xLl/t0zxvdQ3Vtll1GFZfHmw31pk\n2+g3rfEZylfuKXY4vcRkI+IFos4OHt4VXlb3GUwYfg6JDFSd9XkVODz69hLVisCWj4s4Vmi8VQlB\ng0NTwC+tG+u8q+LEkbmKebE7C5F3B65wLY2RrDAX68LzgsumE02pKv/fqIXCKEgzQfmczSxzeWoa\nmYw+pMLLBgchH7KN08Q1ivXgp+EKqt3vVloY/3+yHhhvzsY7k0TYvhH6iKrWTkEQ0EB6OV9Jjl/E\nMCN6POom40Iq3QvMXCryCYs5CMkfISeqfild42gPpV/waXXSbqIwR1pfVIMJicbUPNYG/kUDl6WQ\nDHWJ1JH0Qhif9mh90IlLPnKSjiU6N6kewlVvcn4ZwX2JAupxVQhHF/rpw8v1uK2mendLG9H9eeSl\ncvpWHJl3p5qpaBCrCwyWoJQp4u+E1p2m1FHO6XcoU0WOxF4kHFNC9YAHP6vNjYppz82xmMKxje20\n9fb+5ds46L1vLQZAXvyQ3TSpN9I3EotPyOUlQEbYJLo5NLvEtN6jOuDGj6VzfirFXlCPYy8p1ojj\ntm/UO9ecjBlhvuxfibOZTehIxoK1cMJuzcm3QejU1xSGKremESnBFAUiuG4WazyI/WJEfYrc6ajV\noG39jS/jCGRO3fqWXoiUU56Qs0gQEojGBEW0GJtSV5spEETiehnS4qBS+Z4AJ6bDdsBtEbwsdIw5\nOyhv9RjUGzXR0RobNyLhV3qCrcxmUyuyFW3V5YCgebaojuaJ5+r+9FM5/PmDaOOS0jBf6+jagT9u\n4BCNon3q71UPkyP5P2OjBDOxpQS8oVqAJz2IVeSfl/o3pNekUw4rgOhQnKgkCDRK73vDrVR75gwG\n8+Weivt15FGgJ3QHmMcBcNrIfsXHHqNe5K9Yyn94Hua5OMPatEYgf3otlydwg8rOZyG6ReqYYKFT\nhU8CtppQzbARkBRJNWV3BjeFQ2yMrkuPGcK+hUSO6VODGlACf4PME2jrQVVrUt5IVvP412fDLxyn\n5LDNCreF3nauMV18ZY5a9FSFSTN9uGDSDs9T+Ta4pyp62lpWQ9bNIze0XUoEWmUyQg0sjyeKZEPg\nb+er1y12GD4INFnARkCGL6nh0i4+KX0XYjBed5aNMNsiV1qtzGFwtdRkhC3V1hU9fB9o4N2d48tj\no/RgHoxyTReDje7Lb5TJvWn6ze/F0ftQVO9LqCK0kxtslpIOoCTuoe/y10B45WCj5OtHmyGW/LYh\nY2JmjvQsdo2+2ry+sifGv5s3j8hik7SWn4Qg6eJy0iuSjRIFMf1SEyvc5JRnP5cHmdutYFefQpbh\n0p5QEbVn2oeNfSRuQZ9da6ZY+IvM4QWUeJ18QtbLjisExDsg3txDbmJTAV33/fIZfht6mLolkrXy\naadKYZDcx1XKHCFxco6hmjQrcVP6ITkT17F3onrTe5YCPPAPcBW6vJIpbR1UENthDgSmMakNDwYq\nZab1qBIbknbUyp7mIIKQtaRny9BpJBIPpauzSs9R1mKHuji0E+fVSYAV9i5EJI/+xksbVyw5yT9Q\not4HdwTw3e8SA9PAVoC9PXdlNb5wXf96LXcQnGCQ7ahPqYLpCWQsUsVFMBLPfQLWw0M76TuXhhGg\nw5P2gRG7SoEFYhkJziZK/znavBouLycKdVECmqKtDU/Lb0GQGDVYJfGGVXl6RMC65V7jYx/OW2kz\nfXSTEFpql4DN2pmkbmUj8nhDmhwG4Esud+aARBOAqp9CpCEFn/xkfQZBWe9iWGJP2xqRYRMapVxB\nrXNMERp6TFPuVmjCtZ4uL1CtRRoI8cr/1a7o1teO8WyygLGG4FO2vj8V4a3eOcje9wFVUVT4M6yp\n0/4P/UWAxM9jKlZrWq4yMQNWclTXZzNTyYIv0Rx2/qscVL9UIlGiQkmrDE5+RZ9Yr5BIJwG4LoNo\n6NuYz6ug6uDQ/ydgsyr7559JnLlQlShjCvVrw9uE6T4HTukAWykVw48vihYpYtvqpbC/B2usZJm9\njv+KR70xs68O8aev1hRg67QWiYhJMME20kBcT3QUhcq8LWMN04bDCHz2eh0woONTDv93B6OlpT3p\nc42+dlLVgFTtllQa7BT4qRwxs6CRFt1VzV+fqyh2KeNsNHe26IkVOZeVtVihCwhVKrSWNyL3LnNQ\nWNX8F0asxX71dTPk2a9bewQirYm9l4T3fgtsmO4BmqBUfnJlvLVadR00tg9pQVbIysBrr4EPRChz\nJyAtdjQynSmqBTtxaniYVmmsSJqrGQA6LsQk0p+LuD6A7w3AWY80wbOG9S+XFe23FZWdVBKojimm\n78SK6O1smbwuNI2JH1zupbsDYIyHEwj6ULg37o420FF9AaibWH6GKYFIEyudlWfFHbnAY4ec2m4w\n9rXov5YAQvvXTDUbWTQ2mpcVPu0zk3FByRZ3KpVgfwCLrlLFqQ6AwyxjSMDeX4mGAfSx1vn927N6\nhlp5d0XE7qeNbBK8eCJeBaKVZvVEu4l10YqYviabsYn/HU/vQdvSbaLb98aYNjSVaphlWU+D6NA7\n+L/ZGlHGII9I9Nb6kIM0KV0++g02mreTUvhLBV4GuHeEZUIJzj/Sc4yy/VpGdY78A2PDTfBgRiD1\nnp8kXoGkssZKk7yUWFp3ywqockk6R8q2GUwNCDjvvr/aJxteYgonH+O6/2ZetHVqmzfGvJjgBOk1\nV0d32L2P2sjObGXaa/ijPcNENDEC02TynmBEzLPIcnIc7gT/HaR1WQrlaahdBVtlNSXWHgJvRZPi\nSwNe+CgEdtSThZKj6CsALVhEStKqYtXdvNRiqVHb+yHnHJT4RDTJdknFRXiUISbG/m2pj9TK6svf\nHCReDmkFcHCjWsGNuUvUkg4m5AabYTH7TJjjbMZA7OtyCJLxvih1qUK0P/4I1p+xUIiYQN8WvtUn\nusrydxMvAzYG58tWl9Btr3T1YzZFqQ1/aq/NZPgR+bfowHXA577J1ABIMW3MbnIRmM/evf8S911u\nuOKHbWHZ/C6szT/zBVjSHTfakrOkjCTl15q9SJSMIitdY+bo05UsOFXboJLi7/6y0oXKSkpn83GE\nrhKKNuILSUXBPBOFZJTihsOwZo/9xB9uxD0A3gkEd/A05RT2cA6+jylmnWuJUO1QQtZgM/NyHg91\nIIJlARIk/exKsg9Z/twpf8sMXkiPm1i1J82DaXxEeXJXcy0hnAgXy7Hh+gtVZQfFH15zAoQwxbmi\nldiENS+qlWk/UVPeqilCXlrEOZKEzhk+aTg1mMdGXSbrY+EpqRqoVtKk+WtNnbm22EfS7TlsuJWV\npxqeL2Dh04042nV976N4ukCXQ5Qr+6YiUxZ6dQ1nV/JsAIVTL+yJDrQSFJIcChLRGSBPYEw2IHVR\nmo3AavaC9HAxDbbUoMZvV2C2w3R5DctMJRppdhD27y0REQnKdUIdEDWV79RHfFzmq/QgphCaIJnC\n/UK7E1uuFq0AK2DP3kFTDddwkRZzBLbUHL1Gu5RivT1mbfwgsmX7uVoxWhSu8NPlt31tRjqbT1hN\neeidR1ROCAR07a+NizryOZHunvPW9MzD0b5/OV5XTG+jfWSZqblIacNpJwU6rmjkF8DWPXn1LRMA\nZcNqdH9hyHXKdrB62zuwl3GGzK/RJujim/QZMkMAEb6aJK7vtK2vV1eaIGErsSPSJlbF2uymHOOn\nMQaiZuyMomzvCrtoWZlOuI7RXZl80tw6yUDJiczir+L9wIZSK2qJ01Fip3tIdnxxYhdm4ehzBX6M\ntewxpbzln/zpIXJEz2mCzW8GW4vaS/rSdVyBx0f4ZlZyNIDe9ECBQMOAGx9USznIrET6cz4WufUd\nb6NLjU65vG970HXYhQdStBMnnpD5uNZwxwUAMXsUaq5o76ofBv/ajjjG/Vp1lSIhAwgYuD+EHoWC\n6DMmHbHoa7RxORClykLoRIK2vYCXqn7GbYI8u0aZhlFOl9d3fMT12v6XZUpMW6oDzcEQ0byFgCWk\nDF3w3iMPOGKqrW17jCFNkx7qrhTGCEX/ug8bbNkegLOMy9teglLRs9/wg8/cocSxJuVp5Ek60JkZ\ni7d73hHR6k/n2JQZmgqg9JqHjJ1u6sDYsDbo0pPSJ+NoR1Om6ZWxsZitFexzpiWUhVMUmHjlV9Ux\nTYzlsBWQPFs6sX7Lka9pK5zywHBYgyZK7A9CeX7SMqYGtzSQioBGixzGG1bwK6MMuWlAyM8p0xTe\ngpMjtIildlX6BdJhN2J7kLeylJBixUz0iYRzeXAlqESe15jF0hKDLk9NPw2Eb+3+silx91LjPu66\np35Am8EG8XLUQ+hahMXXUwWtT2h4S0kpw0DzsPTq6Xft6iBEUaQ4bk8P5eq7cPeBlRapxe65AdVF\nUZWDhLvbNH8IlFf7EEceU5Hhm4hdheCFS1D4d1tzNg4CNL0LnXZ1Xg9V74HhlcoKA15lsbOuS2Ij\nnlkwab1H+/vUFrTUnbGt5gg2J20N4lEULbOQ6NhoGbs9hhFLDiyy+jguzr651frBD1eB/bHq1mDT\nx5dC0m/Jzgd0ZQb2fMwXC4mRB1kNBAdQuh3VPKNAqQeLqJMi3c3l5AhdriVX/smtQCYN5W43Z8nH\nSGUpGbGsS5sb/AdE1XYu/hQd34Das0sOVffSiYntLHjiFB6ct63H3h08ADoKdwyv1Jm4b3GIfvyn\nvOX0yVoaQUhzDRN3K8gWHQBbXBm12yPo9Ouhd+1GGJ351mCLZA+1/g8HMbunpj0+95r7dSJzcVW3\nRl7GwgsxXawk4JTgpvH6E+xyRoXOwJ8XD7WnkGYJCVLlW3ZHd5OAifW5byETZwKFrWno19tq6a74\nWEgq8ApscihVsBCJb5QuPrHNlSb5uoa/yFDSU1RxoAr3NW4qtT7G42JsjrrebY5Vm20eccil/wa+\n1tiNC6bPlc+BO3tsVH5USlYkxpxr1vSlDLqR412+u8EGWmpUP0qaw/mExLM527rKGei57dXSuUHO\nrDqtLAabd++zeBMF28E/MyzENvRhfq3dtmkutVEt91jO5o7A5uQ6FrbSyGax0W3DbhwOhXQnN7oF\nVaadQyaViaLCPIT/h4+TRuCrhqFx3NFZDIYe87lQ9zOCsiMBMrsk6gq7fRpTzmIraBXfoJ+wWpBz\nRbS1WbEKnuoO6DxGqSp7C7eBQwfspAiAUfdZ5LuznsG+cSHBekL9O1NHeynzfNIyvxbfO/JlqxBO\ne/Zs+z9dc9Y4Tmi8PYh2xrp4lY89zzHLceX+ToDk8l4I8Jl0R5vxzYeWHKzsaEFCEJXXaoV+KooR\nUpWJgBamiVR8rAEQciqdzaSrgoiMVR0s8rHj/EM/hfS7LLIQzUIKAgZcyn2Nc25eZahSPgJAKznm\ntLVnwKetBPKtzyGitSGyL6g4DD5jcAekkhyK0QHZBj6h1FXZhDp6RVhHmRztPkS0ZCIqRN+PMlOM\nuE/lqBA+zkdPPFPTiC0IOavLXiBs6z05G6vLRUolUAhfQkK0RHdwYrJnSzwDaU78VL1c9d9s1o2X\n18MhEwB5WquqQChrkvkhThR9WcvS1IGHrZOIzvV4noA9QqCpAIW37q11yX58TOCrixsPSDJVJzY4\nH0tVBLdh7uwvk5u3EEkFhccH2/FEimbj8v9/5/z8o6vvFCTAPzZwBhv0pxinfQVyXkoM9Q98PBjp\nK5JJcYDW8oMxNBwjC2g5hIivaeP8qm4FVhngjKXtSGW3ox/rhqlqngtFakaJjemU3PSK5F3Fs8LU\nq7XKpgt60H/ic6QbV+HC8Fo/gaDi16EijwIba/FX+fg86VfIyDB9+HVFxDrUyicSLI6h9jZ5SXIp\ndGNbmRXZqWzkE/coiLsJZ0EzMsUtqdQgmYP8F73ArnGjrotPARurx3OnskatQpCMkTXcJQQSFteb\neiGsXQ7wse7Asp+wTe0G5KmJHSr1ZiScUYph1QTTqSOBL76ICftwYCaORqqJwOQQFNdx/ploJbMq\nOUUMyJGLhMT00Svv0pUw67L04nzL9FVFbkZRCrDcXm7wUi4dko6u4midaN9lQCNsuFx+UjCTKOuM\nuzd6es0/6xJAzHKL41c77okWSsJSDWV2pN9pGJMWkilPb7c2IZXsqx3qCvXN1Dbw4dl+8MZ74r54\nwTBbv2Lw+ZzUCh/tnG5mE4IPcfcPdI6XZkff4ndp33b6Wboxid8CWx8jubsi+2BEyj6J7DJjC6o8\nwSxmv35i0i5cEU7mmrIWs9vRIICCfXgucifL4xUFMvKB7Yh25Rm7UgbyxUAJ1BHSLyUBC6ewedkY\nHpzaE+VkicH9sl29+unhY356DMcihDc5fRFFbYgWmk6v2Cr2brcCUXcJNsdRBxVbuQFt+H0RFX8W\ngWccQ/xk52nWEW30gCFkHHu7xzF/yA8qH7k1gcvnQ4fFYRNUVHctPUfivPwfNAFf2Kw9EwH+g50c\nShN0YFnwZEBeSnnSxpIeZ5b35GpH9BFov+ouPBiFqs6oJcrYdczGOl449XOnAw6ut77ioeGn8L0j\nfCD41DR30jzuwkfjvWiet3YC7xbbJwCBEk95FmLnnaJ9idwHYr1LZdJCOwNapAuT25T2PgTl8on1\nkwURHVdTGwZdUD3oJGtdf+tLKnx60w9Qg0WdgRSKyqJrXUndlXGLv9z2ofpvG4G4TpOeZvhGoKRI\n1gbqJgIaJlheuNI0jeiQBTe0c1KU/e4EiVk7hzTYpZpIc+34j+4LGzCQhtaU/QlC94u+GKPjmyPC\nq3/+PmOfhjhAFl3yKdCHTTTFklnSMVGU47QRhN9p0EClAJeFWP1u7/iwlyM2NKE0QLPwOJGq7Hbh\nbpHLLVzpUogpdbFJCWYrPeFLqVpaLdpF5wd6MqQ24IaUHiGFijdBPw30aYceJRSczPva9hNZ+783\nk8ZaeVctnDBaCRPsou17PQ4C164NowshOMoQlliL80YKKCb16th1B9g5MWv5m6P8qebinMSZF961\nK40B+5/NIWjr3zP9ODj+bf8YpUiU127Rh0LQfResiwrDYiQtxhI4WD8zX/8KC0MFhr4ctZQmkZ1g\ny7zT7L+ZT7Ku1GdSJkdd6LwcxBZ2qC9CMAvPH48KJ58g91OhQ5WQx243z11q8xXvpvi61Uh5JLNP\nKYVt8IHa+Gkv0IzuL8WJ69ypfWJZ75TgU1E6dzNZ9j9YkK6tNtlSSBY5XUSPCkcas1Z9K+lx+tC2\nNjbUtWp8DbaWbflRbJ/7LL5zM8wZdOgZesRDiaX8bho/aZB3BncVmEtdCKaozPHFBCrFAaVx7gJh\nqfLk6zJrDZJkPiJL2bYKZZUTpjK7+6KiF6Rf3XjIpW1TYolGIK8hgQJTVNORP7RNQHYkx3I9UocX\n/+/hRSOaJygEDK26y0lCGsndjC2CbQISVB3ZMxIe4L31gfqKraiISOXi+7pFRdi2Z6OdbZpFHn9R\nTTmvRnjB8NTCiSCYKX5xFw9gnwuIrXYl4l1ZthQAbx7pIGyMqjmvCocKUYusDgZxZyReUVp1SQDd\nAqQZsMSzAz2t0rSZnsybmDC7g9zNmW7GzAR2Ek4Uy0W7rcaQfQN33TCDhKEpq9Uqcm7HfSV4Ldyg\nA5SOBolp/wkBWBNPtzEHRIW1ocUL6rNGIfhxf83zT1coDg5MGfZ/tfV3Q2My4jHtNolFX8Ue0T4X\n63DaskeiikHNj3Q6d296aEfmEIEYH8zwWHK5rMPIMaJEQzKRL8eetBHir+HicC21d8sVupY7uW7E\ncfsi0GAXpklpLeuslLq5Exs81NmBbeoJM+KMe1vKIZcowkxwHeI8lH7l7bubVrJaCYb69jDt/YBG\nRkRcJi5mAXCBU4w/LegepTqXSf3pvTNzhk7uBAHfMUFh+qrf1GJuTJPtV2s9It8sdZ/Ewz5pGhe9\nmPkyIp4BFHg+RkboLRiIEa78NDucxecBBeoGfb90BFwxg8JAmF22ECdWKKEI8dSUy5NzLtMAeXMm\n6grQYf9Ny5o2IBrgJ0U17cfUCOqQn698kjHVM6uRHLRpPu7q/EoBNDzvVaiEN0SFkFZfo7agYPYw\nQLLVrBFg0R0W9J/eoIwjahxe0rrq+Z8QZN3I0GpGQC2UlPh+Bzg6mn8AtMmCXwL+fZQuZCpVMZGY\n5JTJ50WxRnv+VtGg8yajt/YyRqqV6B/urXnkTE+Ay2fm1M/MSF0FOuCAwrztyut5WIWHEdUZGqvI\nLi3qTPpr3LWl6yIQtrDdPaFLudT0ofAWeyZZVdH6rH+i7z58v/zJbA8TK/GacME/QzTF1rGKaE11\njh2KKl4+g9e5tN9OfQDAdOxxxql8BWA7qD4AddSUZui7mF7GATSmfzLimkH0GG0H4a7bRR6Jaagu\ni9ahyoSfiEzRKOpF/3Lps6Yr0h22XS3B0+D6a19D7FrbsCIHSDJS5wNh2nSY3caT2lQb5qwNiD1P\ndd6GjnnA53b8nReQLjrC+n2Egg7kUNyc6dkVKnv5FaYhxAlk9VtFowoonI7/xGOJ2/dQ28vBZP5/\nSXSv+WE6IpPdqzmYE9+/dvFZRlx7AiCh3WoU9mOfYQ9eYFWW5kjMnzN2l2Qp9eGFQp1HR0mT9I6N\ncE1moedoSd+fHCGuWH7cT01lTqkLcmJstkJ/lDp9DVIM2sADy2pkHv2rEEGXXcy8y7tfcNE9UXfQ\n3qO63MZX+XwsZMuRC9/yFSrP+dg34fn/4dGxQba+Hg7SPfUEpT70U4iZ7eEaYv9IjtwF3kQNzCgt\nDSis+iio3EW9xDYZfOar9r62IgIb6iXUW/kL5BP47LlTsyGAPYb+G5KzPczHu0e89H0NChzpc/yR\nliwWZ5FQ0tgFQogS9kaDv1ci3bCSBbK4fNWfp68hKRxcnpQglyUSRzqRstE1y1H8RpO53HQu9FSO\nm1uN79ZhqyFlLSGO0pIDRo+fC4sqmRH/6m7GUZxBf5SGnwc8XsNXT/7sVFyqFadkrxGIe5+IbX3H\nKd01VXwvfiHde2uq6cikJPIw7sygu9vPtpLg1oZmPv4+DxiQ2krYkl+qcBj71yO7xjc5M008NDyC\nUB0GJl3hddXnYiE0Dqh1vKdBCwHqwXCi5FoReah7+oWMZG/VfaAVA/E5HObwLlFaMNrhSLCfHIZ7\nbLQTvHipps/ZzUZskZMuivSwaHz8iJ4RYdmcpGbnCxMrpR3NF3rfa8zhgIgfJI9/HZAWeL3Jmr0r\nVLVNp1AkRxaAXXrXBPsTV8D1tSEjEhbZoACI2mZs6usfAQC62GSBuDZTWQGa2cN7CzU0Wdzxmn2q\ndW3hCoAcLCiSEZbcg3cG1W36fVGYXaDHt++AjF/JnEGNc6l48lFM5aE/szofn6HXKlYVSaleSBtV\nHkhlOpL26lMHd2P8OmPNa/vSeHq7o0Wgjdg1FpCCL+Xp2jYt9Mfqlatr8wtJmM13exJugfwJcLYD\neG6s+z+9dTyS2mbqfL0slrm7XRNaii2b8hn53NGL/A0bvfMi4LEKRcylH1SuPYUb2KlB6mXOKUFw\nWD7euysZk848ceeLCtyswk+n7ZwAlwIvCPtUt0osh0U/2rz3Wuk8UUCPsR/NX7I1IJXfIBq+heuq\noC1W32auIbdg3oG/vK91xOybey67OsfLhtb85wefwebMeUwQyfWwy0rCjt50GnXjvDeH2RmGXbgK\nPBra/kFh5gvtnhdSBI/xe7wdOAL/6t1PIzQwC8ahneTYIbMLds7NISHyMwDrE9HXPsaOUnlOcdyg\n7p2694dLuYdwqZXjRNZ/lBqfkm5uWyLvacNB5tb/R7GZeFDwp1MqopvQw8w+EUuPqFa+HRF69jVH\nUx/N1Cym4+fnuuCDhfsNqJ4hHeWdGccn9PRvbBSOce8GlJ/Oe89h0BJrJkIcza+nxp4RTp1ZY+J3\n1oaYEaRKJAag5M5LrC27z7hXvfdb7qqQ3+sROAfBrm0xptByYzSnyfDQm3fu7hfgrusBbRVzvTJ5\nGVqaEsCvsWtMqbjXmCZzUP2Pcf9kepigJ7fjoVWLcZLCnN3VZjQxflcRqcMnh3zhPXz4SACSEuJB\nhp6nCrmfY0Vl532fpx0ITtMli+BGIItnUlK0+nyofv+tRgFPioWw+wh2gOfu/rtXaIPCQI7/mG3Z\nL6Q8IQBYsyveCdzqSFYgW3KqJUURvPCTm8qPEsz/c41ketWw4KupYqo3byADqP4DP9B6wwmUiesf\nGVa2YwKdwdWM1cxjYcrbrcjdiD7oAiR+0O6sJxQBM7iXJ9NqFQUOfkuLVNWTB8B14GZN9XxsjguN\nZ1h6gsx+4uJB0XaGL4j47SfPTizEfSB5tkPmpkKNnW6kN3OEtXTP1+ILmQ9OEH6wjq2u14ZI4NnS\nYVsQxlfdLWTK9/j4SFyTUWYzuVkQ0lojq4/Uly6fMbA4JNq7hZRxeOmlBYkZE/8IdBYL+jGUc3hn\ns+BIeect59xDYJRCE9N00sQBIvCTy5U6Vo0QpMXR5qf4wE5pGUx7PntkZ3xNNmK9G2mdvN9VA4oK\n38mDlkj7QG6Bf2EhrMIah+bFdHDfVIOrJBUGBKKT/R1zijabXsFOMI+c2uZNj5o4g2P6tHHh+aO0\nfj1+fG4X16/CnKTnGYoq1jZqvMP+7vsUZQT8l3k3qbGJQgrXp3zz0j9+OLaEXgdyxztfpGpwTlCV\nhqjuiQCFratxqnV8yI52Aj7kpLa7gVrh9kQ16Aw/e2NT1VsQRfZ0n4DB4xij2AGq4m35pqCFPj7Y\nfqOat0b6eeQLZ/7ttO+t1/N7d+ljdZ7tQEp4VtnRs5IdGHNBx58ojKBTSSu2QdUcTX3igptAkKP6\nWG0bfvcR4DdwHgiyh7x70MnOtsYpyiNaokM/lIok2KgaCNxvcCqA8yaRVJVkrp9m7twm3rFOO3XG\nMw2huCVe3Rlw4yEKluuul6yc9kSkaCQKsvy2ubx3ifsh3iV3y0r/TJa43IDjER4Lv7xIW6jErXev\nlMZyiX2dveAID5DdaluRQDYEaTbuTx65egrge4Aqfxe94c1lr0qFg4nUyY+ken71eZ8sl1d1Xah/\ncquxnKUsos6f3zMhS6jdahQiwmOfmGL3/DjlloM6/k/qNK+xXzyXqKivK5Vo0/kgqaCltiRXNbUi\nSocAbeqwR8iodxTYqirDmmoYuN8AZAyn/FGIjuM3IYQLalYa/qbiU51XFUJw0vNUcfEDw4BEMC4c\nTWV2MyimfMxNrAUNE2TwPp1WUVM5dP83MKbP1KAUE4oy5/x1YBlwTWoAgmJ78MIp2pJBeIK06USZ\naS290vtLmlLGsIHn0X4vqVJu0ENrvA9LXo8CnUK4QtKWJD0D72DcQ/paLjY2UscjjavxhWW74Ewp\nyGUQwVsdKr3LAhdYfWBayNBFgho/Vl40OyAi5qF3fs/eQ9n8KJGFCxR+jKfWRJPuwOy5+zYLJWJK\nP/R67zIgZTLAGar+IKX+cYmnix2JYa5jh3G7VOXPfPce19PKTvX27iw8KrnZP6icTcWAtjFjaxeA\nGYbjOMXrYNSV8CTS2NS7FmdfEi8nKkO9xGlplc44SEVQvUEBVqpzZrw7PyaM2X+jzeDe+mkqmsvO\nGTuUCbbqH1sJ8ehKdihcjivHqZQ6gP7WQB7MTtsPeSZYSR1SYPZAbBdMHRvQPyuKcBpMtBM/6kzv\nREnFiuOJ3zWl64EfuYzkLliSbI/UwyCFzgCQ09RenKSXVKezpmlXlio87fbI6syRRcmZYj3FwlHt\nWcQPvlpzfsmLIFtKrtvTOK55Jnfm9xm3zXLKV77vx+TdWDnQ6gK8lQb7pArFmXxDboZeMgAC7ao6\nUeE7mLR2htAVouLTxxsvkXHVVoezumUyYEghHUvDibRHdYhTeH9kfZWr/1L1Xar8xdUbtQ57oTQE\n/87cZ+RQMPmtRQ+dbgCp+hZt1vaciB+D9He7GYobzMAkDYnh7WPD08UlGJTsG88LvyJ51UJsBInK\njkHTtAVkEeoe6e+jEDM94PVDGcS0SuHFF0bujwKhvSykwIhgWICmAP0KulA2yhn3l5ZuM/k/zHCq\nMw21NpcD3Mx4EaJHGPpna0UQKwka5yovG/XFzH3hE8K3P/ZcxvOPAUXOqr5DMXU+YyuEWCyDv6is\n+WQpPj3HuJaSkL96Glo4Nv69kF5rnZrpTcIMPf1wJUalX0AY+TZNjzp0+7eIxfiSSuD1Ejpzn/MQ\n7Ml2SshOk8WmOyUTW0q70LKf5cG7VL0FHNAeXkYlCLZW0a0V70olseBMS/OXcX9l91N9oJzuDMxj\n8wsPvPVcd4oTtNZzHDyTwCtNsAszh61Epy5gSir7+7VfxaTvgy5psRP3TyvNvcGcsTDBX2XHh/eY\nZfaU/j154GgdWj8eKXKAIs+gC4geVGo8S6DuMjub3ao90sM7KgfjwSIS9Cv21nhbezBl1d6EGkr+\nXp0NkFobTbVcWy2n3RSbNnA8QmZh/lrsXXvS4/jM6vuSK1CrErASrobcSMZCmcptMzCSOf4nzBHv\nDql0T6KiXIAxYO3J8d3QYS13LsNwr4RdHQSvPqKiAkzRaEHYQC/WBiYwDcV26WjUZeLJTnZ0rGCv\ny2+7Mrng4pPPt3ZTePSvqEcTJ4gon1R200QunS5JFxHWWJswIeHSbCewwLIoNXy5s/qOzKxCGh3g\nyqKVSw9lgpjLI/BfsBsv2IXewN0qGApykjou+7bMF7SlsuN3/Y1ilgoTZZoLTzyi8UwbKJVQW3ut\nOJ8uDPeSh77LvJfWT/SrBDN5MaAgmrzMjMYZMhSgexe/XCJE5rbFrj0VoyRkDupJJVyviX2Eqvph\nu6aa5/Fc2uJT2KfkZOoCUn7Iqq8TIHBR+OqAKNBsUWynI+iTiKCfO0ZZIEMFmcyWj52sdZRtP/iU\n78jFhKiOtpNIa9VhX+qHJJmLgbnT8OPT9HqguGb24EUqnpH0J5sPIk8XD/K4uiIwj1HDGDnQzVey\n9qEY3xF38PVWmvU19qtv6Djlj0F3rocjUfJhBVE7pFhKL43I4XUpYWSQUCC77cdJTQFXrvq9O+Fn\n7jPxvIYqGImGWk6DbmHdJ6wSgmWWvzD7DyFJ9bWqpQbstAIaQaB8KFRpcmli4iWzUiVtTJqFEd/o\n1GdNwfSe5W7I8aH7yoRKHVu1QeuJQtdqrbZkTZfz/Tu3fXN+R7KgVnwKakGTOsjqJG96Ug9TwIxN\n7fHYEoFyCjUcWXr7RvG2bq4EJuc6UmsSMsRY8SoKVhDR1XAYvPJdttZkiYU4U+1R8AiekisdkdfF\nHNqQMWqWTjzYWTvclYPa/jhfFjoNGHysC7lAPqRxz1XN6jLD8jOhFUF318HTLh/d9zoOeVvuEuQJ\n3kyy9k/iVGbfHV5R1xpf0x1REZN/G16TL9IxTTg7P8u0w/ZB1pFXUBxHQisCDuLkaAYfxmnCKgk5\nuliD1DIpOLZYFY/hu7tyI5jtLTns9uLnm1WkqhJ0rGBKEG9o/m6rM3pprEIptGV053u9Rst9ncdu\n6u4WqOuRM60VGB750HKypmaKOddWx8CJEc3oUOpBUpDnF9qRI5Xe6ygS7U19ccz1AVeflQGf6AF6\nqQ3yIE3VGPsdgs+4eWZtTYT/+akCD/oCVt8yKXNKupwBp4bXFh6wSsyhiZbwQqfesigrv8PmLnsz\niA/a9nzlzvjxXIn6RJTo1d/QWSr/lYLdPSHCVmFw/ca/F9EdqQLbvkeW8EHJS59XQDtEsF98TaFl\ngTse4/nEyXXnNXQsRCDgZNTxcLlPr2EbC4qQKfQIMU0/4HW+0sRJ/PTSgPJy4LyQVwDsIdwO2TW7\nKfaKzL+1mTjmh1NkFoAgBlvU8NS7QCtO2tXNrjcEa4hcBfpV4u1Q+ChqRwEuDX/A0zAVGLwAChhX\nPu+/qN0K8dIpvmKvHxVeWjUp+SQq4al8YRFSYqQfRUlQE9s4lmR38a4YC2GWv63eBTs/qN2TeJCl\nopfpsUxLW9bdL6Ne50jzMeM97oFowc7xxGxjxUI7QvaOnPPXRnwexliqckxbpjwcBghDq702YvMm\nlLUUlhbiIsD6fWDPnSORnrT2EF5gK1Gy6UpgjQSAz9HAVG/mh0cJXq8oDbwf1hlFJW4eC+2xu41r\n8/9nBYOwcwEz3OeEIIGKpwS8p9vnVI3mGW36o/+5Fp0tqCKssofKB0xh0+qIG76/pEGv6CVUdDNU\nJLizq3B7y9k3bOYrWcukCobcJmFpRc378b1SJIY7IBDnX1na0NyKtnD02S+1cuetgEY/lq0jAIE+\ngXycNWDo2KmMEiUOvy+dgT/QgvIoU4PufLj2y4RfASoGw72n9jT76PooS7ndN7P9rPTFukxu4epS\nZ1aUEeuZmF2CJ7bSiuXXkEmGpffq2vkxetjW4Tx2ShFlW2sEnnIZAjrDh3+WiVvRDpHV7KBc/NqV\noXgooWeNpIAfHP6CTOwBfLE4BVPCWoxHkJiDU+WC0lWixmMfwxjV+713CD+egqbU+bsngi4Yy0Q0\nAG4Voua2oJMQNoj5qHV7WvluMl4ZUhSe6NA0sKwVD14oQiUnGLqsizwyXwdHQc6dYUFLwo3doV94\nZcGEMHsEJrkmWUP34jkGaVDI7AQBv+hPTM8dZbhY+2e1lii7NsJJVHZcZN2ptXexHOynX2z1bVFs\nu6BEvmEJezajPndbB40LrYdiZEpUN28g30ZtAei5zlCxOrHWOkjs7yrpVCNlJ0XTQvvDNDfHExNN\nnMX9GFj4dhJugQDglt15lhe0EfDofcePBQysQhshIDHJe2hnWzVZFhE/c0DZdOCXxRWgT//1d73D\n3gfSwWvw5+AYBwBpjg1HBFUzyQp6pNmjOiiE507lR8JF/w2pe53CBbvAj2rsmywIzDLIbSwo3/Q5\nqP2AKmBKYuaGuridrwcoe35huDSN02M6gYtnLz6TT7TWVWEWJ8c/fBlo/xXPluri6zBgIcD7GH82\nXD4qX0cEjIZr83hF6HRb0afaeDF4e8cZoP7na0/0v5q8PLYCiRonu/YIg66j3GXGFG9nffSaW3bc\nIsizgR//2rawH3Zc7DCm6ZScANoNt8w/DpOLInV8uwc77hkqn4mLC0+jirLGiEkzwxLMUlXhHmLY\nCfLia5PNLaRmIXqC4BWBJXxETqyKClp3waOFS1335sgRuUSlz70tHocXER16eXv5vvjvX0qf1Q8E\n4FEoeyptvEwp0unBcH2dwwP8ajNQsDVz1d6fsU5zDHgfO3O+OQE17JFUNuf7SrCMe5r5LCAUmFWs\n8XRlyFEUNkHaySSIe6bcVBizFWpVyVOIKaYDMah5sp/3Bee0CqxN0d9IkULmfkrkFYSNepfjp8be\nZ/s1MyThZW8VZu/Gu+VlzUaSet/1JdxC+/BqR1vzTGb2n3XSAKTl5s7csJJBPkENanZ7k5E18KRP\nwfIhY7trRQb0FVFOiHK8uH1Y3tVzx7m+7UBNKEkOgFLUwZNE8mv6aW0kYF6MD0adP7Rzg7LCK4Cz\nN3VLheIA+W5L2uRH2y20zEn0RkimNlMwWpyZlAzA/4Z3FFmOjclcl0OgNI1WvpdK0IEuPlIglku7\nszO+wm2+2FJZ5TIsfRCO5HzENpdmLZyuFBZoasRbpgZM+7WEyLtCeuyuAQWAkzsndqnARH0/GlDO\nSA/QcdbyVnd5wVOibU9JbhCGI+mVXN+0YhuykZIs4oaAGzX5YJ5NlNcX6xoHcaS3mJXCOgKVIguH\nnxa6hb0YtQuwReoIqgueXQPqqlbhJAMRNbwy8fbzutzaQfP8ivV6BpaULHKu+9OrIFghuug/M5h1\nJYueo2Hyw0aOJ1MnT86+aTCgkOw/HipaCaWvMLw5E0IiQO6AJRUUHKCIfQua/fqboKP6oPcvRiTC\nfWoGnKVLEnrjlcb5v2B6hx7xCMqeDXVPoejN48ImHKDhAV8XHj7MBs4/2uB0FIV/L1Hf/xn+P8nt\ngvYfOG4dO/y0ilbzj3/zOR+3+tYJUU7oS2i/YfCd9papwiz2fuZQ3IVDf+N0dlB1b0E2nrWJbUod\ntqWl6rXNcSt17x5TIKKAJppTXInXmwE4t6CyCfNKaUbRaCuI8RznVxE4NuYa440S4dyfZ3CWKovn\novM166J96Tr4Tevl0dC0fHYJYv0fZwh2fSkZQwzDUNXmGSZOWZP5dqv1pJCp5idbGm1k3afnxrIL\nkYhVWYP33cRpf6Qr/Vf5Bb+k++rvhvuRqOGkUplaG5lqWz2DwHCi8nhANq0Azf/zAH9AN3Snw+4b\naiBA1OVf8G+ab4BYPTnvstfOfST9W3vm+AwbG9lKOtWX/w4fO79OP7Q2pq9RdT7jkxYZbLLxDFcC\n/h0k1fsoHdLpTSRBae7XdnYyBcoIxqzqLnPrb+6D2P/guOuWIbdjw9wQblE/FxQCOwbN2wgMwZ53\npLUadKbLNgC3VlYnb1uZyplMOkR83K2SXjbWKT7U8smwilkqMZ3FUNk6Vdmc5S0XllCtPxr6eJKX\nSSddzxsvdoUoWqNriqrQCMfm0fqg71bksYdnnbDp65zya7jCH4v0m6sN7co1RleX1UzFM/oZmjy8\npSkvpIDfiIueep8ehBCi3Tp83qafHLeOrl+vEVNTd6WbduaAFhsEhauH1bdzCyM8oju/hhHVTICv\nFQ/QW6FQbZrDUJn9sn9+FwiFQR6HR0rogM8sgxaGEek5VCI12u2eqhHBdGajWpm4wMAx70c/PuFV\nBn0tFF6OAQWUf8+l2wP2Yg5LTy7bUs01p4/OxbWYi/SV0+sBjGjBnlSBaB4auh7614xNDHY8Fk7o\nuwM03z3JQdJk+CEw+QrAQySR5DpzKTHu8TsmEi2WkuAmpO8qV8Gnrb7d3+30Ev25zJxygMUDJKAy\nFOpAuj8WsKImbqn/w7BG/HOMWHQ0S8q1q59Pt4D6kwghvVouae8vj1HnPHSR340t9fLuH3+BRpkm\nDzNRpMwcYcJ5UdG9EgAycsPn1iAW4y6OAlfNK2J24aV0ubCFxoztdvk9OouuMdFEHRCeBg5yFF+P\nPYzDv3muXyXyn2UMOlcHahy8+d1gcQ9O5ZpS7xuhdLA3lcyXZchaPFmxxAOibvxmCBgiiOQKfyVd\nD/eX8iKUoyV0pgt0Xal6udEAlXPHJLp7/vxo5hI9fJcR7uos1bTklpFkPO0JvCvcsTtP8ZFudfR1\nEFgnAnQpn0NuSVKobED4+8q4OlROgZbhoRjSBDCl20hnTTHNk9CrU4uPAar9BvAeKxVWCGpSawuh\nJxi6teBd4OXXL1m3f59KooGGHDhzFjQq/HBCLO2ZXsWexmHxlm0wKkf2ThLuaZPJPtA/mxdqzPXv\nwa8qirk5e8K/Ty3YVJMa2/Nl6Ssurano8S6OKvqntA0zg2gLNH2qpsU23QdIVX9SNENjFnkdzMCi\nTYF58O/AQXAAB+ILNVfHnyGIeaXFabNZrQSYmz4DI+101Mwg9VPN2OOcUOFDroo1nHez7AitoCT6\nR7CA/T4cL8C3unAM0CUl4HYvDHI6J72zMfImM4u490B2T4D6iCsWCs1l7DCcnwgta8a/gbvfk9I8\n6tPwjgpZpBhyRaGyuwB3lIbOSqNpz2T0vnf8nss5N6yaKiil+tuaTWugIqL9V0gcbD+KttCIlmGs\n/hoFz/8r8Vb73p/174vCn2oh3UN4OX5wPLRoRYJLK+zldSFAPdHtMwslUza4VsUM3FcCoMehA70K\nWrI2Zb3EScdG1j6+ncV/nfctjpncp2aM/lGb8fB3hy7+NE2ICaVOpdDSf9RLJgfI7Qswk/o3d6uu\nKN1H9EqqYu0QJcBsKHidbiFEziJY/+gxWA1UsF/xcUerQQtAYdoW1NA0iS8T1uA3McGHHcsOyBD6\n4Mv5kwUhOn/e+GnW5ArfN+I3Nd1LHEXX8DCR/wRImdHJ2uYl2GEKln478fWLijVJU7q46KKTCXQE\nJFg/TVlIVipfdpbFs9ls7yFBpvI69nayzqjlEnPwEzjXapgGY28YFOwy9ABoBaeYOouAu/h6OBtS\nmAe8EL4DVi9uiQlP90nyrgi/Rw7YajPxtKNTx6RpEpRAwvqsXL3OZiLeIF9I9pVNDa5ON2b4dXPZ\nGOjkaROX9siUailCS7J5lnMzT64uSaIXB+kFeX4mgv1nQTt5sDwSZPXwCFj9IlMJV4zQkln5n80r\n68PLWTCZfz4FxwoQWLLsWclVYRwt4P/fbIdBG81sDj8Zk+RLy77sx8+Ph0rJanxH6/BKcaqMBvLV\ng8EMaPO1Lx6fnw25jLbBQ7IrdCqlcDsuDQNgyhdElXKG/Fs/T9yBjA5gqRXT1JuzKs7GhE7Ug7+Q\nFaKJz50GYzo6bgvn+iifgHk73x/tIcg1hNq81Wt63KT2LdcymyZSY6NwPi2EAKLVn+Tok7r6TerT\ntI+cIFP4jP69tnAHBuPMfugp9dGaJxzREZLyr9m2TQP2iHrI58kpJbSJYtpZoxU9et8yXgQTQPWD\nbJxcpqfMfNFe99YZO6wLB7jLVVa/b00PUg/HFe41WxJUubBpNEa/coMyqpIe+B9zm1NEiIjIkDg7\nnw/s8ymCOkowYQVNIo8UcuPsKrD1asXs5wChAG/7tKaAT7XrNodBmaz8VyTvP+Ah+TBs3iLINVXg\nq9wb8VcbUStUYs8UsOPGno/0jMQvUojnocikkv/bYgnPcr8JrWVNau9sbnq9qxiUu/m2/ADmijpL\noKkECIkR4rFKPLE5VgPrH2V08L+XGK5NRTrQsHdW2dpogQPdh6tOExphQLD6nR48y0fcCnemWcEV\nRPV2tCC/LteHVG9ypU2hwO/t90DYccxKn/WJA453qvXWpYCLFZT+Il5fASwc3Mr+jkIxfR2h+KQs\npddVdyHoVEAS5aaO2QRKoItY+noJENmPrOc3oReHqRNUZ7yk4i/1V0mPS0whkA9mQ3afZvnRR62P\nAMm4dyeEqPKs7dI7q4ftrNOKpXfvTybWWvIayjOn1qK/JJB5KXLrG27uDJQnz6W+3cobfI7b1gGw\nY6hs7CrTtwmkwD7gRZmf/qoVJ/t/pTHAW4qXylCL9i0T+pZO2eK/mF1q85skRLlVgopxPu1S2eya\n7C8o33sXLExsHQmFATPh4GK66KPPBCfZ9zOqOB8PRs6GVqHQ6eAZ30GZxqYxNiVk3JxTA5cNQO5Y\nTbTpbYYj0AS99C8pw1LB9CrLcjnyPS9utMGk3twhgZyHX/wZE21bvIcWRQgJuGvUnNQNzW+EAxdf\nE37jwImdDd17S/yXodVMvRq26Usopr9u3Bvrgido/9buQJZJPO5bfzVrxjha9eh1ZH92vwTlYj2L\noHXEOjPUperrTjheQRwu4xwk01bREbFpTPBI4Qwl5DzdNYurBuFNW00KbFzsUEqZGK34MKIPsTBW\nJEdg+Bz2OfJNXAHbtVVWcAlWbKONbuJj0KaHC5/BTxMLGXOkc+jRGvRtriwYzFZZieCUwt1J4stj\naAxAP4uW22zixfVZ+V9ADUOFc04mPu1WYt/MEdZga/kZbf0f0DKKvvk27K7BKheGva5RRMePL7b9\nmXN4VP+8jS5OGpihIopCape5ncmd5+Yi92gFhXnPC8vfvO2BHIYmXXgTZA2WjIStXOqtu1tXJ62l\ngBsaczQqRMe6Ib1bWuKcDcj/saAJ8HuE1vX4tBE5cROggtOVPhgxRLnXNMTGZ4eLURdcZibL/qGJ\nAFGE2dB2zLq++O+zxJ/aFEz1CTnsDI6M3uW45lfUmlwXET4sdMGPz/nHIMOUs8OXxPbZkbQpfg4M\nXwx2T0ydcePcLf/pZVBcXoA1vH0ZekkBRTCHQE61BYikdj/3B/wg8YSKipVD8J/sFdWuwY1F44Qy\n0Qq89YHpowwH+689uL7I8JS1F3rb8rHKgGHOMZsz0SU70iOALd8Wu7TGylyr1Y7iFARUeuNHGVFL\nEmGHSB3YBBcugr7bbQteWYKatv8Ke+j1Oei/7LMIXHh9NWNs0jtTP+41NTlVwgMjgsAK18df43oM\nRH+ljr5ooEgq7sRX+5IOhzXAyc/ghTv4sPmCyAt7e2jTOKRYgVoL5ihOzNvWr34H8232drIX58/J\nYQId81zUlSh+5lFObUu/tXRR2YoXOSO0BcHmUb6+U2ZYqlc3t9lhp6FfWovNWIogLk/8NdJbc7mK\n+fJ0yTf2iDp4drl2hooSW+/+jrnFGd3dK5A88kjcbKs+LmiG5YPXxm3FSn/YDYoyNCX6/ophCxr3\nDZ0uzFpi9N6WBI9BV5tqUuADB+6M7aC7M//bRTr1QnwJS2Q2AO0ZiVhlNuQlcInbAQMcarjNJqml\nEY3MqR2mKz4tTnqAE9fwq7Ou2T3LQswKFyWWzuLuUfwr7IFJ2LbABshzk6eFJI+vdGa7F0wjhYrd\n/Dn1oZVasrfNpcBJjd3l3eHalVSy4+lh/r+/hA5ba+CNFvEkf1snYJcqwRzHmcE9GbqESJwfzq5g\nMD0y3ZgGCZ/5Hyzy/k2uwtaz10iZyjriw5smBS0Utf+UupcwSPjajRcBZEsl3kTCpeM9d6ibe8Ty\ncOdHPLpoFN15rqgIXBCgZlIdhhJfuQGjSBLE4IbDoLxoAn/+JOPdDpJQdfSa+y39GfqcScCr7W0l\nxjdo5DLQWDg8sc3p3B/M0Zhp5LyT0rFLM7mOPSBIwl6eXYuB3xX7EjDzlUPuVZ6Qvo1vQ4aKgRm0\npE/b826zJp4CIdzaq1qG2gjr6T+sAiES2lAqlCQQ9SznOQzgp8Drv5UKtvtJ20GX7Qqyxo3H8um4\nAniPOUGs0aP6b/QUZQWap/dhvlEkwPOuqZfkStz2F4n03Zibqw863qhOwp9SogmZwSJsd7OZBc5f\n4u3hQrqhrQg6vaWklU/wzADPUQgZBgojGmDgEo2gqb7UAGZWC3U80jcyJtMqkPxSj5GzidoEujM/\nEV/1NpbDFp7QpYJ/PBG1/T1AioM1Ys7GRtdxN+/ZsPeiusX6eYhZkLkWlogF73fwnfulzqXtNa2W\nahgBoHbgTEKm+envefLSbCmW2VRwkIY/0IMoeADuIi/qZzk7foy4TF5QM4DnWbrQx+ZcHlceubk2\nzg1t+9s8nG0IbQpk4juLv8JUYeeabelX+Bx26oNuFt8u5zy8DepKgxppVIcog1yQxO4O6hKBurft\nH+yFjhriOcIFt4h58xiSlR5Vm1NkBDaLXCuoS6O0Psy8JySN0JkFE/dtEx1EsumUwOgoQKguVVeJ\nhyfY02nVYis0aQGVTO0Au+iDXJwR50IEilZ1I53sUtGuywyx/zAO+dHShxIY6qko3hGeHc7BVsQD\nh4lYHpeLG1BbA/aZMK6pEVH+clTEQLG1Qrkm1DqcOP3YW66WARDy3UNDZk3hx2iNZR0fKHdl1B8n\n+n8w+pTI1gEcVoEklnXUZgBXoVzfSZdHmBv1Rkeqa0a6CmbZiu4oL2ZEh0XjF4QDI5KqfF2olu8F\n6pKBcj0CKN1IQGrhjka5LBNl0IE/gZ+9CDrkCYUxqFyPX7OOdFl+5bRpP93aUGci6ju8m7Q0nCvo\nkTXR4hDjcue0r5HdfB6h9omxjUUDTW5f9Xl/9x0+ExtUM+V0ZMWlkd4Cld87PY5OBGAZXHK7cNzd\nN0xlv1Z8Cww7LsrRlwhRWKX85N5qtPCtcaXE+eQKt/cE69UxDhkGJVimAZqnq+hVPlVD43sFA2pZ\n3sxz8lDsD0X6KAlpzLYI7z8YK3nMrHU1LAGP6pRoFAzO2npCSRwGLq+evEX8DXeT8r7gGFO4ZCFB\nIQMaI1pYWo5mrwlcI85Xy2pBf2J/ADJJSXBqU6Bq+kHzoXPfMkjfyxQEB+lzni5SPgm7FLMmHYY7\ntfeLH4U9OBMhEWHnzByjod5aqBZXtSY//+XC30JHzNAdC006Joo6n2g0QZMWvZ/IS04p0PxmJBjj\nRGIu8clm6uyV1uw0FR3fTq705ELIRrj6PSRMJ2aKuH3A9itwPJd1UQbxxdXHAYScUZ/WzOnvQ2dN\ns7uWWp9nvG4A3P22B3Ui8yDO5HFjJl3THBgsjo5H6TEB/qdhp+Lr5U0RmwnxcqT+zhsVn+5RqNqF\nSTrBPAAefHzIiPLvKUNzEqlnaCrCfJE+ngRhtKWJSM1PdJjw8UrN+DxWHY2vgAb6fc6i1OpfFK0x\nfGrR++W1B14UYGSGacBa2TmXUhWLYVRNXqiJ2NVHv3LPYGzFwQgoL0yY+ag3wP6HNzD+0cbssYS9\nwdnTLZmZZhSy+P1F5beaXHl5RhHSSXIue8sdlyqu34qY4YCXHee5dawUQNeNhzdjl5g/2HvM2TN4\nIy3q6/EL3WMsfGI12DIRkgPZVMpMffyh+rqrxmZr+JCfbeytnZ08i+sY/bFKHYhsZaBE8Sx6GCPg\n2eZbH+yaAx8qK41DDZlZqDeKx7wnGzCoid2r+bASTDQjWpkDiMHsAVui0c1OudfrR56wHomZ9yiW\nHouG6P8QeiWmJjd9A18H+olaVDkzv3ETzbLDzSZnhKIqrlQ+u2s+L8u6aHwY7WsTDIk0oy1Nf+H1\nSAoHtdaNmvNwD1Gq+CZvU15tD7mUFSFK30eRuJszJrd3U0jNywQXj7ZyDGI4iMVjX2jA1fpY517Z\njaXdBJjJfcKQBxU+ER+Q19Praywvufplcx52jVY7rnBfwNOJCE+nyP9cRUQ0VGG1tUqgnXRiEUVf\nFzV421XO+Z9pYVPbZmvv0+NxEmhsW3+bxOGEbKZuoM7CDdzZebu2zJdDTKZ212IBidfqz9Z42Jx9\nSIJp0FQfnIiSJRzCHf4jz+z/3KqBRM/05GK0MPWsVE8DFwwMkc9CWSuYfGFHG9iHgTDkpdOIXA3l\naNjDWufJDefhZg+Oeg5AXUFa5JEo3nh+TEB09XMIvImD1gxwVcbvMAagFNVZhRMobThfDFlW4PPg\ncwINiBd8tIF6Js5D2vzcK7qTxWe+pMx7CsuZL5HjGwm2G+JEs/hkLkXO30dSfPgoTul6kydZdsLd\njYXYT9TyUOYlus+ri5M6SWFgr31K87M87sm9a6xl02sLwg3XFHTu+V/1/awNSzql41/lMrzZOV+Q\n+oFXigB7JYG2tFaj+eAd4yu3LZ2Xv7nDn1TcqjpdSAC5HDxQWXvem4CDnI1XGvOCJZu+/d54ELED\n2ViHmo4xtMkbtcdUJ4BfxuoCmvJYdrKFQzYKVczqlIksw/Y2AQXOiu5e5wpfzLcW/D8dyWSGiZ+8\nGIoUP7gz/rqju9ybJ8bMnJVPTCEBP+Vtw3ebaXoT+QH56880dIS4XxusoHBpqZ41gJo3L9kR3rSs\nLXFT47IXLpTpHOAiOIA7nBNEhEfxBACfv+1h6Wv2Ml1xKB3tiaIIEaOxLdQ2Tw9eN/TVIc6D09jq\nwBVsO2eodx29+EnsNBlbWyYL4R6G5mc5m6miXdwKdpFVDS0YsEsAgWUBwIwJCdwZ8PsMC1R33fnL\n4hhxVMXIB8mTxSMCTMo2U4QJ6QSWABVsW45P1GjAmLa8kp2mR/I8x7IDJPVLu3q0wc2vkK5aOuIS\nlLToRxpiekE7VBk8ykDOvu7gupJHCDM5qvZXmTx7Vk7bJrcqolvo2ifU3DAbN6QQG7QXTex8FYOk\nvAHWUE4FCtsRMqka2JKSqNTTvyRBY7jYeKvo+O5IJhNYfx1iY0zR2XrgAfORSVG6NsJH3Jfz8TSe\ntDm1kh49aNU0nTo8C0ly8nilWHZuFexXI1ZrhWnki+Yp0w4nYCC3s29DyW5tfzkmGDngHkXR3XXx\nnLaLNyvyql/hMrK6zluOwM1/HxgE7k01X5Nh1ZiH7PpadypgT6YZk2+BQmhnnxHzC8Rt9WWMbCSK\ngylpOq6ejmhSggwXM8YAe1h5PR2+RfqoYsxMHxDXDRjTEQ/1X2/MbD2EzZ8909G4hdaQlkS2nGrT\noVZ8mpbBuC1a6P6MkoIp3ur575pw8fdG9sV3vDRZrArtvAp4yjSxm9l/d4l3mcQgqm/4hZ4BsSAv\n1+7jkw1lpZ/XYNfJwnF0In3NwEs5zgIAfrXi+ihAJJZeApaoIrP7UWI/NtW3a0t5Ll0sy56/bCyg\nb2BiqIim7m6Le4EiFRaaqdEHkhVUMAtx11d8IdW7V2SUk6yEuwz0J91jHuGTEPXtZ86m9AzB+xSl\njRbEh8eCIW0kTDWEA1hHrHNAg2AA6SNlqAK/29MyOz/CKhYc0Cq5P+zEWprkT3n0xqHpQLwBN+xl\nTeOt2yzmIlky27OYQbYdcC7LN6ICfixDixcp9+n/yvQ2QlKID9yzKyc0AOrXeyb8NFc3KAaaHoex\nn+WfAJUn04uZY1qkXI86+MYOHtVSMBRdI4IqjsTFrStJqn/Tp7bYF1FORQyQbCGHd6X1wdJOgsWF\ntN6/Gn9mUXxiye1/DpbX2wPBgGrAr9UFpGiQLevnoAvxe/xVDtdjQ9qyjRNvyp6ekKnZ9mXLwoqB\nyx9fb4x44UZZ29Y89BW22SPuUhW1+AXRN4BWUGS2gRWEA+p3axH5dUal8B/lnZE4aF4z9hndWcNl\n89NFS5zDbflAMGzz0m4I8RJirQ43lDBEhyDk6wD6RtAC6KeBEIWc90HoT0C1GHuc/Q/81SEZfwi+\nx0d8zCb3wXORM4axlej21dJSMNNkDnEuYkCQuR524osytqyiI2oCIdEch2OYoiokRuhZSRXi0Fu8\nu1hLGHRUH7DeqaL12aObgfiXgQa4bDcgJALDWiPOcbmXDPQWWZb7D3WSlcoAWWVVdLBR2aTMBhkY\ne3yLC163gQuVOmdblq/B+NSmq5IhFrZZUT20Nxbz4ee/zqmidFitgdnS1z2h8xZpJC3W8YvCAwdL\n+IF/0ZhVGe1n6eWLT4EjQ4sPQknSRtETUciDaP5xfaXt/R5dfWCEg07yxmNpkwwRfNzGGugo1y/r\nURoiq4fHhs0GGZQK9j8SA40Zf7bqayRzKbBDZqQRVjAn8F+CtHkjcZcdacGMypzHwBBRV85rzPHr\nSQj+J1izomqxwMoyoPWkWEUCMxItRhBLsD8+CLa3xy4JmyBIsdeMszJwcFuMm40RJmLUQpR47hV8\nAhQA7lbJHJ1kNbF4HdmY4ipldK6aTg61wJEiisVlurBX4xR7O/YfQZdILkMRXsWO4IkaAvwZQm9X\nH1YzpINXhh9osZhPC2yR74ZJeNZgP/JPPF1/57+UbqPwqIIeQLRoI1Cqj/RR0+S2gALCc3VrxpxQ\nvREdH12arGztF+24qQibnYUIw5d5dDpm93fbXMnuqXGms/9WmItH6Rh3lHe/QFINI51svZkFvS6Q\n2oYR7AFIOmv8KDp1Bscw1jBfqDVjuu6W/Gxsq4yGWgzwwRyctG7nYmQ4xAFGUIZ5GwfeWbIMqsl0\nGSQot+2yxXQBT/YKarPRqq3IuSrKXpVp3peyCR30a/bEDbtOaPqC/wIVTGcyQFky6bMHl5eCC0OG\nU3NyjOHI//YbAYxS1F2T318F+cqFsV/Vt3Ih7EVPurwZtjZfT7gXCapPkIFq2NU3BL3YLoEet1x8\nna9ORdd0UM3eeVmOFvXb84yq7c8kcVAGYzkJZHcUcj8vVTzxd7BlGkPA223OQR1aN6psjS40ml26\njpBi53vqJf8Qwpht+6wDN1pFjF4Ot5GcEMO5iW8GyOyEHs4aXa0ij9+7BsU7g/eZTFubGko0kBvK\nkn+0vLyhsYCv+amPxTz59akZGU58qT28ZfyWxptNka7GT2tck6FgqiaLp0h5f3ZTdl8PEWSkUzz/\npcDVat5na5TyGI9d+EbOwdS7ejYcTqd6q1mIu5DrTjDtYccXC1mR4lBoBsBY7WCpTKYeTVSuNwoF\nsv8U7jl+u5npyglNIyclnlV031M/mef/jsXdb8sxQnQup/Q297qJBH3WbT0VCEQ2DwWHyIEhBQLX\nLxUh4xIlqJYSR2yfjlruVQETyq/75QEkd7dH42a8uusKyrMpRTPONims0x3R9DM+D5/xqnbJ77k7\nvg7KJl11GnVNP6pvwbopAs4o6tz6xssBnNDN5poTcTCDqPFtsp3xv/qVlLcwZpsNliNdNzyS7S2R\nysd3H2CMrMfkfpgWnOF6ttV4bWtNjVkuBLLD6ShiWbJjXWlV2rYNKjtmQrbzQaPIkLo3z9VDNGH+\nipVWAtpe4kpQEpmJUyJnz7XWMip35IRaptPbq6NjN5B281sVsfnPOmJmWUMK9lhCFFu0WXiBO7UL\nGXLgyJALkVgnrirNkP+jghjvrU+d7Ahzaft9GgL4u0EyY4oL2NHWGyznJMGd1mkukidGWW7rR7Hk\ndRbwhi1ziD+WTa9kWsdASmH4PTrrEY9WfUyMyh13rod5Xzu0XLNYmt+s/ic3zSjRnhN2wY7OaQV1\nB1DWbMdKjeuL8vGXE8yhVSEFK6ocNmMSOVLvT1VAGW7w0Dup3ox8QOraZzSu6cQz1OEqoluptJlV\n4Azyo1FK+v2fzuXpo9DCeOy6OZPx+ZzKOp4uzXwG+9en6YF1XwLTWiWhFur4qUtQt8UuztXOyOOS\ntFjVif+G2oeGewBik/p5/Y5+QKqX1yvesttQ9bmRe1y9lVpUak12NHSkZoeYrGStqVsb50KE0UYk\n7kwm99ydr0x+XhpQGAB0yWdVacmOa0RnoAww1X14SfTe+/5pRfbF5GSpwsrlV+ZD2QO925mrzeap\nCBpnQDuTMd9dEKLaN3oWd2zHNOGD37fez2d988y+cCwzNnWRmsK9bTndK7QxXyxkqPJ8MuoLF8e0\nuECHhjNMDXiDKl5WN96kdN4o0dtDWCnr0S9baza/2ohzp9zCFlYIsJKPEKYmKkTZm6rBbCxuVj6Z\nXaWvIgH5t1ntm3AOHod4/cbphpnl3LuXUFEhEIClV6oYQUgo0suSGjimp73E+1mZSNvGZg95j05v\nkS5jsWHMBPDsS0F4xY+BfEjqRb37Kbboidxo5z2C7vmwTMcOpwTz/sVgk7r5iYXZN/Q/NS31NHM/\nwDEJ6c6n1Bubw7tE88iduc5+9Emqyzoew84JUdF4Rk85x19Oi/B2faHe8jrnseaJKeLXgGDws8X6\ncsZVH6sYqel7p4RHvLBfncHEqVNXYiaQZI0qSuaKy2jbj+RZ5ap7bEJ3q4DosL+ITbK+iiCXRO71\nHM9K3OxDiAw0IlBWC4UUFavC+yEzgJB707ofkD6YK7+f2ywQL3V7sJ5O7PWa7byAi2JTPGJa1cuZ\n1o2RAhAuOjku3rWsCnLBnyRCsRZeFW6whvPdgyTICARVdRnSXUbY+STVeOYgPxuFIXm0Mz3AL5l6\nHP1bv4wxDBxx/87m0i1evWGZCGDPvCUHsqihGTma4A8dRBxIHAdfgEBnxyHGf2JYiRHSHfTVWCO6\nygtxL/c+AZoN2jjdFJOL7v+ibpCeTMg3Mr5KB6BWwsP/cQRMvpx9hrbloMDkVygOyIAhnjF7AEJW\nrM+1J7RQRtQ/FMBtx/jCooXg00NfqJtkX//MXFiymhORw1VqY6Dlei0rTPn1hkZBW0936nrgLlSA\nQ/zLcoozr+C8pPLz2uiGUGVcFm9r2If7kHObpq19TS2FPbAJWXUS66n4p644d4VD7SMxUoAOGk9Z\nXF+tQaWkM51W+LaVGuJJjcAhedO+Ff3OkCNbjHdNDmFbd4YcoUFyiV3120s/n6VlRIUvPmltFDiU\nqJx7b6WI+EsedHD0BKfWHmWIEc9CCFGE5pwmpRqD7Pywded1k3X69pLUONxjNr3dcIB/uOXzLVeq\nzyeAthjTvz/hSAZD59i36wQnqXMCLheF7+E7CA2OzAlTmara/vS/6+JD9NfvhRiO+hJs1G2CBmpL\nhQIvRMJ4P/+Ty2mm+cA0ubxLNArKbRx08QE2lfPItY4Mnsx28FNvGiym6PlhwPD9xUFG7R9xsi16\nahKTRcqbyv+GpTYvtBboskbPI884uuYUX1UchBNnsJv45c0f0AjE3BlpJ5SKPFy5nZQyRreV/kJb\nsJooTIrPrqy6t6GfA8AHrjtSgoP7GJQozMzCsxLsBSWB+Z07M/ZHvXyilp7z0kq7ur/VUfk5ujyA\ncpKFH7HPrdcIT2x7hrSmOKafP7Xz65X7GdeArWw83c7hCbgRBcW/acIaI83e/+08rmwN8vnyWQyT\nV6X+3EyyRAKV87a3OBfB5VcYecqUWBY75C2pJ1n8WxF9s2BJo28L8vx7DWplWQ5xgMNp0LtlHbzl\nNTjy8Lu0W5CvbxGZrkd8rrV+NSdXYNFnc1WEOoIwyFfKMmXccTN2ybJGJiHOmNwrDb3D4dWqdNKU\nwzWRlUFk7LFerDqFzl+l7PepZ1gbVfpiKZ1schXVku/aRQPyfK9hx44RR0Ve/SwCZZJIFjc3rtkP\njGYuYbw4yDwUBC/6bJzPEXSiH4/L442UMQqGspWghSVX/D/24dmmgceKKFTVyB/LYeyuV1GsS2E2\neu7i0B0zwFpGqAyzOGkSY8Yi75r4a9ZFkw6A3Cxw2Sar9e9/tNskgSE13WYPqXiOu1Xh9qTlo34Q\nAIn/qLNQeKPn0i4VwcetrOqPL4dEssyyHUGxNCRwq+xvtW4IzkKwJCfNplnkVrY69FwP176x9bTY\n89SN5Lh3aNMNCE42+CjCsL6ClEA9vLG060EcCHBwmsS9ZazMD2R/nyUt5Ak02ZRbewBa248iSCLB\nwHaspvJwI14w3Fwgto9LTQRCpRnXmT+cFlgOy9iRVw+f9GG0H81BNTj0/xGWMIb13p6cs1usrwC1\nG/8jRi7Rrt1U9hRJF5qROORfCp39EhqO/sK4UItlxO+WbAQsft0RF+Qk/aAExhEmwctqJNB68ggN\nIxLQKTJJrLwHf9Wez4yRyJ+MktsN56innylMxYv9DYTZr3cfxMLn7wWbl5BqOA1u07fcHwyeUskz\nZWMrO85mDo4dCyw2Og2Y0JAEmqWMWWygSN0uMO+pZlNEj4cCOMTsMpcJAabX/0lKmruxhbXfGslp\nN4+cqm6W1nKwOJ8lfA0aeRxZ3kUVsQo3553nKF82ViQA91/hiyH1Y8vSAlHnSKw88sKu/Arh8fN6\nCbPGKkcdt8lvhgekY8yaU/9GIhgDOf0tqvSp8JckIyxf1qAs1GqVPrGF3/C3XjJuwGa6RK940Jwg\nukYvqRkgAku/IinitGVZvqJUDkjI6G3m5lH8tMatHl3Zqsa7HaVxHvICNrwwwtKRiqbc128zJHK4\n6F0MAhVZ7xXbJomuHFkSEBsA4AFyGzCRXiA7Z7hW5dK19HUv+XfJRWNMZHsmXRRm07h2UH4YhcAh\nOmgGGV58QAKGSqRqKdSVqAdX5TfADy8PeCWp66WY+Z9efF/awYIvppVs5Tqle6mqdf4uRBZmRadJ\nUlZek2xa/lVx3BImX27X3cZvx9bNv9ug9id5Eov6NhOfOlpUyzguVp93N3oEkB1rhmr1SDJjXcSD\nXCq3Zz600wkakloxdZoQr4jDO+BNXDOqX5tbRLsojukH9T5k61eJ87cx/MAJ4Ry8VyRBS13ojKOw\nmHdOkgelQ3BhLYctB/ucaUTBwewTvPEcnZGYY6xDkpkmGwGkpAmO4+IsDqIz3DrLDYEyItUhwQpP\nr2Txn+j3pIEzsGu8dgIIBf86EDMMnVzvVPiCCC9HRt+5DzfKapxv+JKSh2BQ8NA41s2NRx/GROOA\n8gPz3a4C6ivZvA51jMQJPmwDNulgQVgEW5AFWn3BFx4H3NNVx/g8t2CaLe3P15zucYSdNoKTcUYl\n7GHGbQdoaRAnRSeMqHef0qfvT0dR7LIESAjQyPKu7QM4QNql/tvncBelFhNIaloAKWVxI1jC+rnA\nidnvAT0u3Nm8FbCAQS+FZYd/G0qvAmUaTdHSY5YQBu598M52triIqPfwnrYkcPTihkbzok4Jj5VN\n02WuYm95k9kxRBiEaHsA5FsJXYFqMrHhBmEV57lgvUOlXxkwjQzpFPvmlzUQNp2lzJInOPFmiFo5\nzMMyEAMabQ0UMxSEDTmmdefcGb+5ge9Y+EsF6RLpc7UeVX13avfMD4o1+QKqaoEFtdyc65TG1sN4\nK+vwuU+qlkgzP53vlLjabwB7Hy2zM6EICdSI9DO1CVEo3QwwzuOK4BGViWJPvt/CB/+5xFbU1RCI\nI8Zb8l0aUedAwsWOUWEEJsD8R/2CRCOWHivSDj9gDawU40bX4U1Qd1MC9Lo3SJOk89j+CiS724H6\nHb/qF3AtkszYGlurniI1/eoqdTONG49xVRDUoyAcp9SucxC6dlLkfeLDVoTujJyTTeN8CKvCyXUD\n3g2QfSMPuqKsd2lSD0RgBcNbDa8ZTiXg9I1tkz6ECDvKVYB4wgdCff0BK2GmQu3XD1GmYbPTyhcl\nFcYmu7h0p77CIK1Kk1NogiBM77nhXEbtncdoW6+FyWxr5952fHaiL+P5qsgGigkx7ZUaV0BUxygd\n3QfJ0weNBgp1i0MLMfXZPWw4x8jGakU4IfkFcKXIImVygYceNyP8RIqxHOpTlwUU+XdW81ZlbcaL\nOM7oZyRunS01y8ZBLxxb7WkY4kP7YLpoAEP/dzGzSd/HQm1lzrKwvNlcpvBY2mXxdKXSwASLilyP\nnt6W9IN4dhET86MM6huDnALHXtA/wxypyYioJ/hjiOujG5e6aXGdUAnFeEJydE3EeBLBcrPgOP4t\nvlMeIK4KcOzOD6nvxMHBBreXrGkDIVEdD3O9oJjMwRu8krYXrIEug0aTbYgxNsOs4BgVFdWXStrk\nIqYk5AxnNiavg13gorMqdI1CLL8YVjzZX0H9FAm6g3IDf+5nNoYa8XP2WQ4cNVaAmItXLTB8PoAu\nyIMgmN9VpAGeVsjF0UGI4NKm8vWmNAOOLIIZQjgbeAlOm60gFMRXjkYpbR5FRS25I+EJjqdrnAbM\nE75moXvfyLIizPm/P0hKczvAahUVa9a/dNVDl4+gYh4oGJaT4BwiPGIT99Rh+xnbqwaiUsEDSBVZ\nXbR/zkDna1iaITHvnNGA5wtgWxmi98qz/EVfZb1vZJSIMt8I3jufZXJOFgSNCXaGNJ2NbQHpDJ37\nX94nwiIv+jHrgemcfoEpyPl2R54eyF0y5IC+k+kUp/8JYvkRG1mjL1DySafKB2xylm5+xCypB8+I\nMY6t2sPxD1MoTsJQuiLhQpf2rrVMR5DDE5KHG8BmvyNknW1hpH2uqopTLc2y/puPiPTcuSUYnTt3\nOuL4qss3h8RIX2k8aShGbhSW23+GLmXA4v5fKFCS6ykKAWm5gLWz53MRzhBYwb9UBcbKuV0zi9EL\nFUKX9VgO3jFPoOXD+IIZj0/D14h6N0TWsnTAz93hBQA8CivSjqLOLnwMMVm4iRMpxbMsDrg2EI3o\nhuev5nBTlLsTmxUnlCtsPcnjmZIB2SmXlRyyruE7Q6TG6DAeIeDqfC3pttmCZhhTdGLKswPtXDzC\nD5YvU+/gdBQpP9VHGdWIrXsb/Jd6Dz7q8HZx2rLJ5zMbnHhgndrdWXsQzE4drNZ4Vw/2Zkg8xy5D\nUm0oTwQQcDTJLoIRo/x5DkndsTueDBp8U6DIkx82PniqNJTiq3asvS76jjTZPnpLJFhivYIfnKWj\nQ6+X+UTnQTN/6UApRBrAEx38fH48X7fg5robVlWoJdk3W5FnbG+8Qhn9huPCFWnK3CeCkR0jWApW\n6Mi1spvKosOZDXf/ioRSsbqbP42EOATRrY5Ibl8Hr/o4x0LQpPUKjV42C1ASdtPth5t7dwtzGtf9\nEgaS2EAi7MlqsWM+lgvKdeHroED+81qrwuu1+Wqg0zAHXqPHB9kcVvBDdGtr1PW4kynIPWyuvKLU\nkWa3ZTZLdHCfmcfaj3i+PwKLJzGMFrPeSfKXUw0R+Tq2bdiNPavboVwQmnLZNNYkyKE29UsDivjw\n/dFfRwrdat1a3p1/22fzNnC/wgSI4JLCFExhWZ7MdJG/GD6h2AIUvi1KN3OT+aFVmsNNMrGoEB9o\neMGDfYKc6z6Vp9PzzrDEUBLcFJePmo1Fwp7Vx9dvLMJS7Y9DX/VrApwXNi0xro7X6GCYwdkFCFLJ\ntgA5Q6aWT0/1mz5kheKwmY/mLuNm4PjCy9R0j0C8syNHPbpToWbJ3jkTzumMx7EwvPGGT5ACkMYL\nNBvkkmCueM3yey+wI/EEgCgw8jVFhlrOalJYmaUJO75tQRuZ6twLPesD2U/yr7nvqk2DL350Tqz+\nqyMlOyYsMoOkHY3+4VeGjYup/5vEg6dVnSIDwTMkIhwfq0sadTqTTeWB//ejlA3t6+Fk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j+Cfw37MsBQbT57g53rBMerORc7ryFxm95xjTusU+axm116fXAFywBnav6OY54\noRR5V55S/GIdRT0ita55wz7c9csX9MI4ez+Eha4eqbO3is05RP+6EK62kXlzTm4DS6iHP9jK3XYp\nKauVqviIbqyqmhuzAe7U1WNBiMYV1D0EZ2jNScKL+FK0ufv3wPCcqo9MIgvLOrGnNZU8Pcu7FU1E\nmUb5TtoUPf3n+uMkJrTM1ykB0ao14WN8eh03YT07Xh4sDJJ+rkvMz0M4tSz14udfoIdQEJxGDAZy\n8q3oz0oBcnezYmEO6+etv5K4fY5LjJ1WWCKtXc7VbbraKnkOt+JOgOcUQNQmNFzuowP8YFjkgUvr\n0Pmf4TfsCJfnnNX2aYJsOYtXnHfYBJmuTP6qsD47gg1Y5z6ptJumj/IHhG4HT+KLb6jdBUJwXxVT\n29o4ayeZARUa/AjZ3O58/EkabQB7SmZw1H5Cz0/3BUH17AbveCf4ODT+6BqGLXgKwlHsomdFH5BJ\n1YltM+qn47jgCnnWA/j5H5T/+NDyhdnWsjsRzR+3WX+65bNnTQsT2VTv3kRyAesYg8ITlsAsEkKO\n7TxD9wrmD2VuD888T2NAcWc/zvblUvNZeC2s1E/XsQ5Lgdg2gwHQkyYNz55R3a2R5r2bZuDX0be2\nGMAQZO/L52oALOXvn2djHPWFqcHgmCE3hgR2OHEm0Lv27l3NW3XgJe0xijJ+sRWzzbHFlGP0J5/3\naExSF709uXkvxxg02CiO+okGM3FZ8rvF7JUPfFUx7Xk76pltJQEqWstqnVCqp06x5vVIOvReIozC\nnSBce0AP08DJAbHddh52ASWpBHzihU3M9dyXGzYcTtfAs5WRue0dQid3KvV93QMl8KttHf6b43oN\njiO5e16Id7AtEsXQ5LHyb5PvVnfubwzDNiUAnaRNooQY2hGuvnJ7WXy3a7ZT/XypExNkQzaem/u6\n33Zht28MJWvVmPz8H1dDcbVhzCz42L8Pzll5JysEuvLD82B8vyiGOroCHHgfry4MPUTaz1pf4Iug\n2vWAvIZLOg5vcfzl6Q5t5Oi7mqUya1URwtqUwKhyEan/fQRtNeosdwDabd324ZVg3m1IE9UxaesC\nafkCcaFg8YFPM/yNUJ47FCpyr/yhSzrxdK+fwbqXoQWQe7gzDTkEfWj9mxFS6ag46KurNXR3+uMa\nnI50pZ7f4IkM0BoEKzvIBtf2NLegzGPlJAQEL+hsBdn0qKLF5IX/thn+Ia9GbTe0slTlsGbfx+ON\nv1jDA1AC2miovrhzxdqgVde1z+RzUBC4sH58t/LLBPYHpZvWxD5V1spsgOhlNhg8w/xVuzV6IGfl\nXIdRMsBnsaZfRBhsisAcEC7zeQ3vlsStSI5oJVPFGuyyuYWoDZRXvvx1hMzxEDe9yY22DD4gckzM\n/FAdpoxBv8VT0S8NHv2L9+DUbs1l2zt1b47J/OzmhLZ7/OirgyOFMOJBLYNriZN033PJsWyO2W5Y\nl8ByZ11TfjJfDekxcT8X+pz8qjKh4m6s5zG8UZ2Ki/+5EFDj8OiTQ3uM+wFI/rPQWtjZj1l4AfUI\nOjQAsJLaIBd3Ongf2RDI+nvELbRB0eZbQ7G8800kNQCzuyKLdhijjwz8rmuMMe21Frbb98Hzvx2v\nUrMPw4tiLDDwm8UmGs4DspSiKLbVwwPIOnK88yLjC7ut8n/JngCxhoNRX/dQ9PDMItclBn37fXQ8\nQo/sj3DiEvpm/3S/1TLxiUiH4dROeg7jQehI3N1qo01/rKVzsy6CHOJdLxvW9yG02Dae4BBm+A1c\n8D0ne5r8PoPmsZhJ7+gtnqUD3u7vWGBZVN3Ee3R+8pkFp1SyeGtpp371rmcJAbyaN4nzxeMAjnRr\ne241+0S6Qr5z31/4faoPe7j2BuyuDSsfAfKlDwBPlc5guWgzHGRp4ZZEZNTwLwhX55hOSX4sEJ1Z\nPC97p8EC88PodAF16iXwmg2UmGkAVKqdbApPeyLqs05Ggt8yZLTPYHATxCF/Oa/OWTxSRQOiX27h\n+9EhVM7159xq6lwZAYHAMSMyWaMRsUKbzORz8K7mCOssh8i/u/TpTL5pg1XyIjvk0BG4DXUvplou\n6jwvTFugADovXdFKxAD0PKEejjgAsEBMKQdfYhdXcYe4ATft3KxDOHbKCdiU5Fyqr+bqz4LHvx1q\ne6tW0FeJT/lsC08kL65iGpt4slIMT4EqT0whqPCpSbLfbvVTEHffSM1SfwM//dBov7Y3ffBrnMxN\nvBLn/cXBbyHE1YqlPBo6AC7acz4xGpfyZqZpjWMGLzTBaGYMPHkjivBhmP7AzMdx3qtlDlwgngSj\nCGHGzSrvzwgpCHmZ1M5MD7c32cbwq9xzw5OBU1ug6wxZ7+oZRHLJZK63OsXqXTjz3ZPx24GBkZiK\n1ZA7bNQJhcAd30B8zXefcYaMKCuf6p2Pn5Td8yKAhOuMQm5Dp9H2MUdwVOScpMKBLRMCftMyeZNJ\nyFeHhh9rvDnTKBGQnsTdetLbkpbSKTV0Khjq11VuBaoJ9jyEmqaLFNh73yl8DI0AH5gVla2Uea9r\njBpxlCR2R3MNRZr2f20Pl7QXkhJQrBruDHBfsB0uXuSIFDnDaYn2CnCu0pgAOMRtp0RtWC9IROXA\nJcGoyH1Qj5WwCl/CIFUockfKOutrYS9AVhWmRi0lMcEenEyhivOx9acOtOW3mDipgVemh6YPk2SP\nzNGPMEs1SrXr1D5W0d13PjPiRhuZVK60uNTJ+qnAc8zViCko3sLgn6+21qkEt/KXnNi5tPuWZ3ZX\nwFkm2rvPSIqp49m6zvdeuuvigOhNwtNW9/MwJoHdsObZOVC6I+hPhfqq37PHr3ixJmguJHB1h6ZY\nMaa1KLtpUreuhsWeBC2EP9plwltwLj+t3oyYOkauhKbZQ0wbSr0QmK/gPUmBiXZuZPJMZ/Cr8t80\nLdhAuYu/LsMvDvMi47FAfzerdNw1gmm+VeyQmU6lnV4VsqlRecBN2RI7z7//wPyflTMgnIXQceez\nihB9NFJWtWE3xB525j6RFzz3D2j81vJ82dAmoVCy5dd9fSbAlbldvowY95Eb3WAzqlyMeuMmKsk2\n9fQpIclafHuXWiCm6HvtfMAesiz83W/xdRz3OO1HoiY16RT7mV/tjrs7MOZlodHoLUDmBUrOtBle\nQUpti/j0lPOMXDNhGrlFnl3w5Dvj4dVyMPMvtWIhxTh6hiF0fjmBx0lH01VnsL+vmmQ3NIzyKyXW\nCIpYAMb0W1Uj+VQ0tjDjVWHvnR2A/KWAByBfHqWjEdmp/CCVW6z/BP3hfTLr9AZ3+92dX7nA7Hi/\n15Uoei1DyP+5vC210Uokorvpzvzb0ylI6eJX2o0GdCCLYPTsH2R2tyS1bxGgF4bqFMNp5cpfICVY\nRzvXjFzARkgTm9jZJUmwgtwDui/Uxhhwr61u8zO5WsGhB/YVyEGVvlGGa3rFN0REmtXLj1vqyomf\nzSYCKdFZh7N3XkB2i1KLlran/51tWM4ayET6wOLAM7sBVALves/tqKTDE5TDiev5PMBETq/BmMfJ\npzgW1F5BQERJFjH5/QQ0BrMesOv6xfzIsb5jTMe0ArXwjcYGFkCuI+NYSj560Ux3yh0aLMJHrXgg\nLzWamLaMcL7cMaLosBbCjI/AFNkB85hT8bx0puob3sXZlf2E9wi/zxhs7vr51GL93Z4Np+jn5FIu\nh6Sa+LaYz1R7gx17e+jyO3Lv20elyDeMRUMDXeu7VH7GYh12c80awotJWQulCzlwz2o8JUZbQOQv\nOnlUjFxiWUNtHwxzPI7PjufT4Pe4AwrNP46bwItDfCX2I7GAV4+YCo+SJFxBmtMXGDRrGaH5pjAp\nzN7h7FLAS9BaxYyYQZbi7JSaphlzh74KeNdZxZU0sUxGNMGLSYM1sakS5Hk8JdELxXLkmGvqNU+u\npfGa83YLyTozrwwnxkYAuFh8od2CX82Sep4KBd4nfZ/AAcyGnB6/YmvWFQ9GcKC9OPrKb97O5OsH\nWQU7mOVHLMOLTrpRtekPtfRH8kCF63TojYH0YfNW5ahbvUx3NWSPPPxnM6SUIR7hLacpcRIH/+JS\nu/aXqGQMgigXg6aNeGzMW6Z4bxV/KltwChV0hHplVuln8ow7j7/0Yi+NLJqkTHCnUd/4TkQAhM4g\nrl11SqrnjXYxlK0PM/TmC835bd/D/HHmDXsWrCRhDFezuKPgQh7dpXUDdIXi2if+T3VOLZQL2rGu\nSFd+PiSTZzaQeLmj6YH1aJvzLMUwF+E5n1t/j2z1xEfQwHe0TpobMOuESFcFznlV2nV9cdajbKk9\ngBea/7vJAgk1PI/3yTisuZPI6xFLJUZ6+nT9TD2bjILQSczUCcMnm2OVPpQGzt23Eu0XdoeBJRl8\nyLGjHgl67R/xG7il/Icmo6OcbL39sAiOOgEHboDlJv/H6OW/kWO4YEiax5zKnmS5Hczu+0r2R6RV\n2fLgfFxWtuXnDhXemf3pWPksSbfymvRssVRXAnzo+FVi51EI8IluTdAKgX9TflM4LcpS7TXwVbt/\nnY0vxCGY2+55IS5YGtJAdrmlvTEZJB+SxR3ubMJp7U4WFXKih2wxWkXyuRKSa3SrHz++owohV/XX\nDgqWGZtID19FXAGPQ9IICUcnyDtTTVj6ExbfMgmPb7zBrZOTh+NJzFwR+5aXJL2LteEpEYijEEjB\nRtKsIb5b8IaUmWGzVrGuOMPmteHKh5OMUXtUxF6Iub0rbFUVxk8ZnfwxRtCFvCdXpuxBWpEOWUnY\nNLE6uy0Nvp3jVzkITz7dAQCFynXssstQNlVz6MFkhe4Fa1L47Zk/GWZyjrwA74LK342BnOvMAldw\nMfpTXLZ2bmDk6qRzaCPsHn4JyDG3WuKWXSnL2PXKKosnhmITmAmbPPvKkRHxMbyD6Wcn+NQ1Na7u\nE9XdjR+5XUZWhzMHUHEkVKabBRa4edljJI7AFyS2UkO3AWnvW7ngXXm17lzdUv421tea0kKCOeWI\nnzAlrQYTP7uoDOeb4mFgQZqWGpc7D4fMF4jisUAZ5cQ3VAZoyvizNoDRX2Z4Tzlhxt0VbMTapbD2\nRPPyWWDuDkaESqi20IaZaMl5BNborESQ+XfwJbnroaTmVDHIJka2rL8ND/Wrbmq+3kI7EOrEaEO3\nF+dN5cb3hjD05jUmnpfBybdQjWCoWd7fNe33LYfxZfMUyS0Qg+KVmOVBrvVZu4rTlpk6xRMOh51C\nJTybid5KEDjkYQR4qKMaDi7vQjWdvwHkBvnTMeC1LI3SEyAetKvXAl3OqFr5CO0LF6ur6MhewyoC\nEXwhywzgKl0tCXjnPy5vJsWiH7DYeqZOcI/LlIuDaFXpNaWW6F/srOMkAKx7tQFoEVTBpPtGRVRj\ndFejy935WgUVG7AJCa/bo/AO+VNu/zClTf87Dt57XAY4n6rW/guQJicGbcHZxL0nd9RQcxSx7ypr\n+3YNT7vC5lRkBl+KJLguf8y/s6eLkWFvGaU0dLDYo9UeZNfgc5xFAjl3mH/oH/e00JclC0KKsZgX\nyhFd2n1n9Gv/FNSUy4eEqBAB1L/fK7KrgvSQeIhO6nbvqohfQwa8OGC+DfgIXf3s8mohzmoee3P5\nEIaobJ9CCatAgjbbTkzKDD8x3nUrOV760207rE6IBNgZ4h2YS38eXW2LdSGG3ciJu0ZjbNx9BL5n\nIu1/uQNcYneyszfp0H239thXd+TFSpguz8zOKPu4orLwCxkfBVNxkEtDbR1IRoSd8LaXfmHw4JoL\nwhX+ujfI4VSndNsWwb67mdmQea+nIe1QXbzotui2NONrIkumkUm0uMDvl9vVIoEr55K4rrlNwtHy\n7xQCEAj2RRGh+8uTK2BvMoCnNN3bdUfS6nIrM1kK+Ux3z/M+xcsbZRzB4JTYI5wyl9gcWm8s4tO5\nrOdl06VQEb55yo04vNqymYtXI+nZ6j4lJp0xhIMI9cO84Cst97RuSGH+Sn58T00Gi9SyBv9ybwuI\nwz7YutN8eFAtio92LRJk5fUeYDU1x2iKhUH0uKxzh66pA63d04NvBqVb8HIA8j1AUhDIeI++3w+A\nLJoB6oAK6AE9kt/3lMF+TOztIX4Wjj8jH0UUT/mk4TLThCPvnFVyNVKtZ3NEBXVnVWkZWhcv/KLX\nPY/CkrFFjahJAmwM4Cu9b7z9DG+sStNISfc0fWDs5Y+Rm021muREdjvHujVCqkyNKRs6J+ZI/ziF\nnMQl5c8UqNn+ck9OC1jYwxBIk7hNwQaT5bUCV91CklCjDoUcfkigFy7COMGPFUQ29Qc4yb4hFv+y\nCeXySIq7JDwm5ONBLfdFAYYe2u4GGS/yVpa2dIBLBCr3OnrcROoZi2nlEgxFalVhbyBya4ot2CH6\ndyH5XQJPb9aCfmaA74J7gXnZCnPVmclgr4mI+blDuNL6N7FDT5VM3hnggCb0tYDM8rtykAH+gQXD\nydcBNaLxL4oL8BZ4rcuRonQr9aPjGXhP3b5J2JyVL94gPSIvqPBzj0WEP0ROUv+3jn9u8/Erm8Z0\n9bvbuclXP6VOvXE/cAgG0YgN4843Tv/nrO12NjuroOHtCj+KsRhus05ciZe4/dSoeP4r0p6tHeXE\nedx/UooBnUQQkQIyhgbqLQamDGYBPgp7aMEizN4sZPPqWXbIxbD6MD3iUVDp/750TvH5KamhB2bB\nBTtQK9Tv5TFhVL1PNbRnsd5lVhoPCWZFz/iX+1S3WpAOo90GzuFuri+INSk7RH8ugMiqlinrt1B6\nFeYaJ/6LOV6shkLcr10QpRA4fuwbTnAD4XRARAlb/SQKZjfM+ESxPRYUJVXyTnPXNZ54AjfIUDlv\nEccw/qbSnd6G1MWfrElHYFw8AIJ2Vvp3AY4ed6tg+LRrnMwz9/lJShOlWcHPd6ZY1TpakMV8G/mM\n4noDqixZNSgiNMXB4z3eBuot+lo7s009iYls0VJBXh3afqSXMEvDUpQnfPz1WUYFmjhQpCr3Rp9b\ncrN+emcXrdg2qgYH2/GDweFa47gLquGOPPz7LZd0vOTCYrrjuSyBiCfJ4ljlK0d6i8llTkyL+jPW\npC7QLSXnGLIxD8r0JgRrap+2vfCU9KoAqe5HBtxjJXO04KB/dRzZvwDTlIJHvetlu51+N54rYEhv\n5WX9gllnoitGLeqAARfAdelA4jUnN04nXLAvGSW/piWaGHrLjK1LUsmK4qYnJy7Zdhzge66iGsHJ\nCHolHtQRs/FWaBgrRaMtweTzqHjBPeN1mwBwYb9JvNG0OGs60oQMD07Ca6PB/rXz6onpwY9t+TWP\nNX/RxhyDGVLMF4sV3fNn70EJ0QN2JV3SUYIBKB/sQJIQSVkyXA2P0whyiwvXwVR31y+5RpACeGtm\nZKiGVdRLpSw/VBntDbLsFqwHjHDF8yOgLbPcAMTzhiRWXaEpN7g3UfZoirImFNy74AFkbicq92cB\nGfUfwnKB33jZIrksRKyidDRG6CKqaHXprKwuTrnxwWTOAGa2ZN5s2aMQHG3ECRNEVgizy23wdAeL\nvh6jDimu4c+n6T3zI+78mFcwcAL+vTBAo6JUwM8TTbrIjTjVLpGfjWl613k6Tr1tETOsR/KwTSEO\ngzuBbPNdyes/iI2TC9jqcO66Tko7rRsqG7XFrJ1joqWoMYlEGF3lJr3dJll7CLZnQ3pCmmjnwsbP\n5KJdw93+TCDD9zTzBilgh6Mo7NNg0+b1lzVR3LfI8AZOqKX/tdxEB/LfGDFvfzZGmlkqn279uLxQ\noXP+9BLZpjyS6bcf8L3fNf0u2/Fm8z1JdtM7bQK8t4jk3gB2vpYwAXab1wLUr8sL6Mq7cCF1Fvvb\nBWrfZWcFgwc0iXxqHUJiA1TZRIkVsclkRNYcR8P5MwLMP+bhxfX7J9ywRFRNEmXuLmNpp71VcFob\nq84A+hXofZS7uFuj3oUJfZnuftmwsDrH8/vqRI3AVK4GgIAKUnzJAZaAe66TPOxx9kjAq9EeKwHt\n9mFo3M7+GSxcZhtkxR9LjWXO/rj4n9+8vBUQbGUChmPLLHe9t+UnBVl1OSSvTjkVppgZ8UiYmuh7\nXuHgTcBvkUkYfh+sk1gADnpuXG+yH4iPEkCOU2Gp/URNz0W78V4SpkNf4+bEKNuRbJjUkGDYX/2E\nb4ihi0gd7mvLSPtdk6Wo6JlgJzpfkTTmEp494fTpzFA5Uznd2dgjYAj1E34IOBjzXQl8cVs7jWfL\nfdUsMQ4Bur4GIhGnsHwKLlBt9ley/dw6US7gfqcYUBNG/mCD9oJiJSnbFYc7URN5wZjqr8CK1Y1X\n97EmfO6q/Qch/+WxLUVvpqYYb3bTBF4Z1MAVLSkmGXADnOz0KfzY7kHEUQCZxnChjLufCXVyHOek\nzW/4kjhRMXJtNePHfL24CQeaPz3kXh7iS/uSlmOzCXN1WBPdv7X0ZPKUKcNEYIdOVnop3u4noUG2\nYuCKuWNWR6r49lEvRBRpo7pFmM2THXnxu+4oqJ5/fKCYbDjMCBZiUnY8wfyOSe4m7T6+ElHk23Hk\n8OQpD4lFXokkzsl/fMD66eJvgVXgtxr9ogZtK0b8+P1a/69IRlHc3vVTq65kZ387nL4h0j8GYypl\ndRzdVoYeMCLhGwa/jjuVmosBj8jNFwZhF8IJO++z1GHJ0cQEmVRHWXDxVwPFiq85/ttl9X3p0+xA\noEhM63iHRpYrm5swsp7hLCcKCLG4eVt9/1JoO5S8w0GyGcXdCRVRZ1QYp0RTIc5Ub+FZlXuM5Bkd\n/6Acv6C5CwpJXua1J3J+q/E9cGv2roWcMVn4eFgVYxaEOQAoD4pGR+BziDMYhD9CbbrfguxqbBSc\nFfHrSgYQywkGg2sEsOwSru0GAgPsD1gOZyBQ4PJqnxECV1jR0+8Io3Prqt2712ZYbeoVSgONtc8C\nczwcM/dkCwb7HDrO8bydIbe5PzeJhVOtYJxINnw3OPCBjqI/ZDNB7Zsszc9OK3PU5YJ+LFA5EUzH\nFp23e8G6mD9FPJWH/PM+ZKnRd5BNEb9OU5rrnC7887WPpR0TGlHQNRjeBbJdjS5+XzFuRUBQm95s\nyfJL5GcytnYY0T4l570OZu5zMHYmqDPv4TvZdE567u2sf+s47WwEAhDQ/nVamSmD0miTORTQz3bp\nh917Qrdh4qgxN51caY0HaRS7vp+MIENj3mmUt9JcQqjheCNas4pjQ4/vohcTTIrDQeAHz6dicbAF\nFiVsVyvUl8SeroUMkymW1ex2YSW3FeOvmfKewI5Xw9kLe6FRqel1xS5kX1caIN2r2IZeQM65tVVl\nHM/ai9GbqV8e+ZzzpOQpd350CCDiwowlR3Aa0NOfliZc14X8ivq4ROzb2475yFrfxHgqhmz4ySPA\n8KOoSu2cDxFZXP4wls81A/LmhndsdBzNcX8/Ol7u53Pws/TjE/irazYiy0zwLZboeBUNugiRcO81\nvnLZ0JXyk/BXzczKypr2FCuplBtsfWxh8PCs6rSplmadhRcNmxUAfz+L+SSkuK1jpcFTeZLaQEeU\n5UiBc36FlnxZK8Txu9+blQ8xycGu6S8VEBRRyXhAy1UPpChsn905SfjkUNKmETrkpJmuqdMDszUq\nflbNDCVOu19SlcasyftCBRolllxfqa5x5iClYigZW/635ji+nZ4CowwQXsh4++a4hkkfrbHn30GE\n5FvVUmKIqRpAOyiLr/pPfKkihS3GQzoVWU49QVmxLbAiT6ApBXGAJbxijNQbN/os0donJ6cZqsOJ\nnuHOOb0G2cSYwpWRNMpoZ3int2pKk9TBfmh6Km0/53X3mXaOmzbHJAVa9xYbuyeCgbzV9e79fjYw\nXZoNoJqJWlJIhLMaZPLYwzjnUEo+OYQXe5W1o+RpfPYJvBjQDdtZQB0ZFS+3X39fjEXWGyYO6gEW\nU8ZW7cOqCjiAtH6fXQH4lVKWA6uJb6l+1+wy25v46S2tNIZoRC0jYzJ6Zb/wqBD6nfZCA8dQMZgz\nH3i1cXfzdetvO/7Hncfk7xKUKXhxD+Amtu+bLOt1o9yofetPY+YoFKh96+uwwcRTLeM3P+eLcScR\ngT29wMMJFC/+e47x1kz+AsAhPE71RAaol1o6KSSoJOcMemk//MWnq5WgKH+VPp5cz4tmjJGldQvK\nNTbu5I6dSU6LPG8qDqn73F/wL1W+/rlrVuuS8AFzehqoasyQsv3Sghq9dbgsWjUxmE6W1jUYtaw2\nrawBLDSZLKHpYoHwZeUcp53s5LhRNGF7+ZBgCcDFTiBfewQFuGvnS/U/UUZii/RDkMW+4UvtJ2IS\nqNn6H69I2vMxICuizi3O8YndssXbrlpv7i3EmJlUplPeoaqFmUJhsa95hQmgBZEkxh8UB8eHZ5Kx\n8hqV/r36zEvz0XR5i7AUWeTu/TEQKrmrcPs3AKl5Ioyi/9VVDf8XeutYE4Cxr9Ci9NnosWETxu1Z\npcmbSek3gOwNlwes//MXx1GzIFJ7miSiG9GV0j7HSUAbWdZzwB4Wvwqwc+VZt4ta1ckeIknVjVqp\nY8rcRiZGxfJcfF6NDojqzJuUKkpxZpJJ2msIutqcFSRyec7wv8TCcAqXhXohMKNHQV+NyVpJ8IZy\nP3qgeH9xpQLIwGwjWsVu+bs2jLz6b+2HBGkrJbw9sgeogPoUNppb/5A3IxBKE562i6oFjJ/kmN+K\n0/5Zo7yK3fm1zn3O1ArOWt+1tNV+QR1eMxyhXTDeer77socAetXY1NeYVLJHck4o/pI1MknE9cXW\nXpOPnp6blBiNgKM26rIs+Lp9AOgZlmnR1T8eehRW83yVw0UHkHOWM7S8hbT5NdhcbhdrRkH5modI\nGQKWN0dM6pmSec1vC8GsKnIodkT9XX6sG/4P70tRU753ulmiB5IJwKVM3CUQ/g0A3nrOkH3CGVYm\ngvZysCfIMq895matvgm2pJp0Xp6vN1eQvPkDQqm0wSjloLzGN+eIUI3fYTzOKvk0c4Hv0AFt2lkj\nfG6TGSSe7JEJ3Vl3iQINDi3hL2yi+ivAYmYxsx79Jv/vM1QYgf7z2qye+OvC2rAH0ZFx6j942rvP\ndExKp9rGmP2KPSNANDckU7Xe//flyV4WgK8FrJQG7jn3b6efj/DMjjarBkJs0p4td30kZKsbxAOn\ncMZY0iSlRqKvZvI19sZrQsO+FTfH1C8+p/N7Ozvpuf9lxEC/gtBdm7A/HtVqmOOZ6TxdQXTHAn4S\nWbcNPP1KHuBCF3UheMWPYZRP4YqdH+RB6NacMBDdHcRwMdFb5m8qPTEK0hzbNRRKHmxTb8MxkK+r\nVRWLaAVBdTWl4Zv/Hdg0O+PvF9+jDqSudZ6y8hiugNtbHwgTug63znnpTHu+0uC/hVCu0X5ysWLs\nYdDNTdXjn0L61HP51nQT2KMVnCP5FYikMbZKzIWYJhIM/vTVYluH/lbpBQwtZZN3rv+VEQ2VIHy6\nqP/JLDRIHkk0GppmF8JZf/XIGhae5jITmB7pxL5UUaYiiW0vHJL/kYW+CLwVK1Cm10NGdlt9t5ii\n8ndHn1BiKBhNmaPO2cWYctCbGNIAP6PaEl+k5G7Hq9oAhM0NxVSf66tEqjFBDz0yeCeyKLLEPDzh\nVRi8PvJFxNbbLV5xOcvHfb8J0OktESsRnkGpyyEbnBZOFLqGgWjfBGcsWHaUnFirlghZj9nEs5qh\ntndh9rIs0YAcKW0YirX+/bmf+sR31DjMEscJcErcNuc4w84IOu2K1Ys9Ox3GU1wvK5i92XbyXF8b\n0npzv4Cym4Q+aSAkR/tYPpQe54b2ibn117M4z0x49+swHRVJ549tL4j+/Sc4m/ZZYS6hJUqcUzKy\nT3Nkg1FIuLj4vlP094eK0H5GtXQCJilyaKsLbV3iXMsi8kjTPY7oxp7yKuuiuxZKaZ8eNoHpmUBl\n2xnlaB+oVARdjUtAQ/iFqltXIP9vH2K/QRncO9mHJYUpNXubMIXFvzhooE4x35rzUjiQ8IPDu+MP\n0XsYIoqklhDwrLK8kTCBnPUl5ivDYnZuyLHMauPtS0VwRIna51qz3wzXnkmfasrYYiu92K0zMbGL\niS7gJKLTFO5HsxWtuLTFTKxAUMzvQCsV0Ss/sSnSv0k8vCTiqvz7/LaUUeGRYK+UDOsWwSxOrzFt\nSQ226IRWAolvE7PwOw0ZAcbCK2rq0Wy+7038v1w5IOj00W8LW04pg5KLEu9OwIv1vik3zJsBfGGE\nYzNhip/WyqA5z+NlwqrEZhyEr4MIUanFbOq0OPUvOHI2I7ThCAo+avbSm30gCYa0hC3Oc1fr/vNk\nK1afGnpgDEz9HpuwWatXX4SKXqjpUC2hjqjRdF6WGMWDkAGHzIses0/xxK+TPdnTXQxHUJmWYK3n\nRC8LoJpcroo5g0tLBUc1asyVlvUthZolU1jAKslsCvS2AJZhkvIfkc7yS547BRpp9A6TfdqYYWqR\nmo1YHwBNphKDcXzwWT424Kah48WaddmdzSYwj8UXRBYZXvLrrksfzI+gNpKgvzjfHboZgdFaQYKA\nLm4tnx6pCo2IgdK2luFOVM0StpEJOCHWXp6tpS6cM5k4hIagiVP74q811sQxmI+nt5F9129tYwuJ\n8LxxhniARFr5x2gmeQfEB0OWZ608jovYyZJaCmSBWIdw69kiR7cXLJR0NintA+L8EmW+jIYyBGIK\ni7QADWyM8UAWuv35PkJFNqvBDwOwHLtj8hoKzQQ+Eg7IxYz5EqyZP5s/kmyuUqHwqcZI1/4iGJZ3\n44XKkFLlNjQNoy+KsP+rWqck3qte5pvza1ILv9JHBDqag0j6liwmx+sf1Vm4lnGIJnM84HdrySaC\ndaKn+JXpUvOTCob7zP+MTCz2RHj4yoYZnOBy9Mejxqc7iwOb0yapQzFgC8tOIlwE3x1urRC6bHnk\nzmjrgZZowl1waVVzzAZEkWlso1mdpt7JXx3yF8/N47hpd8ldAuw1x7gqPB2kzCQLtqamt8ZP6Mar\np1cCdJ1BBTg6ROqgGtSsJRlO7tGtq59RDnURWh9kAstr4MjosyJeV7SzMzFO3N4N+Jah8IBg73Wj\nGERONgegcIzn2KtPcMVHusI5hGS1ORqJYsCLeiWvyAVEJ7EtKbzWZqJryBRP7Lu/l9IoCepgBhno\nRo9etAUIlJLcUUxood5uo8xXBde0SroMGTYvgCftccVIj0RfXH/KrM0VBvfXITJSTXB9QU49OeuI\n11hVMMyDHz9QlifcOgs1xmGouYX7OPr+C+9U2gt39r+hvo1zsKIyeH7X3nEFXVbdSz/jqbG9zGbx\nmFH0D1CRtPJv+P5HS+JlodOKfsVvxqX7xDelamLf/YAIq/gzDrr/ENt53/b+1HlRHsgA0U8Xo/p3\nudmfGdy+W2Nlf9uOYThin8aqPaFW3RRgJGDzalLgGZecaw5rNJzyVNgqUN4kkf20YOdWelY34pJ3\nL1q0pFjGoIUrTWA4eTYZw8OoXR5uG2+vLcuRm6HFhtxaK8Ffg6MeUnZxTKTbSyZwL/VJybuIySXK\nxsMmvtT0WLqaJT8fowfKUmywhJOqrWklwtEZAYjzKZBdreg2TfmEpnNM4xOeAuhdFqSzEKxHcq/Z\nuJnR5ZJJhRvde8BiYfQ/p5ajpJwYNIb9svmFP/a/FxEJ/eLQiaewa43R5QRF9IhCCejEJsEUFJBU\n7M5Akgm89NYU3VKOLD6E+zROa+FZq3fJYIOD14IKhM7/Q6CCVEM8dBsvjIQO5ZWYwVOIia7D7qiN\nDS94QsOM4rIp03nlfEtnQ6D8nKTEn+fW2Jt4g41gBaFlJfXC9wYbt0wZ/0jmmyuPs6W1XSCuK1Qw\nQDsPjdr+2PKzOea8tLgms8Su+4ZoQk9v9bMXnCOAwIsW6lrW7Sigsfeny/QhLgwvXnTL18hyAdji\nDD7zaM8MBVB7vhL02mlkwS+Yz9bgcwEgdeIqfC9uwzZYqfE2BMr0BcSB0uGrJLsKMq9h8uRcC6pu\n2b/XhUcHW+ItpCPr4572DTUIZTWidJyRcU5MvpAH1uZShE5bSuNsWlQWFMLPW9HukeJ227iuezNN\nQdKRdsmvrggGdqjOcPUckxra00e65F1OEcw1G3LTpsqdAVvwmmNx6Ly6Bd/vVOGeag+VVJBvxf5o\nrMyoSzW1v2Uyh8p5djNGNHJFttxl1O9vnMrFaks7XW6j8ozzz1UCeoNBwJvTOumSMcfP1qxOKi/P\nT/q3CVEEy2J4BY6BPuVBgiSezVext/kdro8gCckmewDuL4om7pzsK80j5GsupQzkluHn+uc2+jXT\nuBBB4NBo5oxpdDPJtOtn3ZNwmJqMgiJIKX852f4+yxaNPG0tZZT+6PfSzhNy8Fp76NNUEuov06oO\nQuCUUPheCr3QguYXeezOmlqf6VNDfd6QO/ZMW+krYSCfErF8DAF5O81y7mkTEA6oP52VrM0at/3G\nUgnciJX1HmT5Y06DbNHNv1U6iLjyqpD6nmCyKMsEdk6VnQJTVhWuP0Rtto06nAmszyNK8KO0D0d5\nNUP/gPYvfCFyufHTUkRUe7DRUGtst4C/H+a9qU/Ti3kddUyYytNr24n+snyzLCcN2x7qzX4B0AHJ\nojZnJBJXGOi35Voq/gFeLatiG+wrfq+xz0PQvhAHgi/BqhkJyg4lqbPj+WZAjz6L8skai7T6eAA9\nz4zYMIixZaOBj0I9bGxyfxQakJWX7VqY0wLmbgPuxAl9FxNk7VlAt+ic5H94knl4hZqa9j5qV6rF\nBhwijZCNdRK4fjVBWKcUVo+AUGkNzrQ77t7mH/2VMgR4dbU+GfLgdsbZUWcqlKJdvAZR1n4tA89Y\nk5Vl788WgcYuBxM7QiiqcqQWDSgrurchp0Uej1CE8TFfBmLQ26YLwipmz6RV3+nionCWV5ICXD4K\nIt+TQG0XB61wwUKOMB3eJlh2jCV5V1LdJmY4714vMTeYNvkgvT6rlRlbbKPmhh4f5WkkTzhjTxix\nzUqsYa2CF0YmKic8Zaz9Upu/Yqv6fgJj25EQ5T1s6aTPiGc3KXDbu5MA7bdSuPHV75igKBgtOrOi\nQU8DCVsRnRrBsEoCipDcJzZr5Rfyw9HKMD9wIscAgPwTA+5IHw94FYrHkWSViHwP2jCT3p+dPn3z\nCzqMji/xZcs/4Owbrg8E6PxERFw+AjSFrER8Y6GNexbjUKHw+DSKS6I5ea3SGNDsHKMuD3r3Mkay\ngx6UbaulcE0t7PM3dCqbZQ9BP+83/gsIgJpHIPb8sbzD5jGynf9Wejhh0MD4H1QMOSOPZu8Npjt6\nPn1w9jrrAG1EJ0A3sAmGRpKSWxvd3VNFMpmISobIhuHMHGTUuKiDnwFnyitDEFYr4fcm+qtSm3GV\nR9mklSbQekfyQCIBB21MdV4oyox9SWEfDMWTPFn5rGm7GbwGxkrNPssrSLKBt9zTmy+4VQ1dGC6I\n+xQIK1rNw97wSd8/Sx/BKdKcV7rs8zRlp09Y8iM0fvLj6scZPT7X7TH9vf/WmsPkB52trm9mX2Oo\nmLIC0WAcpoh5mMaGKjdROCsI9pbrrpOVtG+wT6S9ZnQRWWTZRPPLHfyWX2LzRXSLy+XLJZwRnUyn\n45cfS3wWvpb1Vg3XyFiNNvYEY1keugJMUGx5EESp0Nm5CyQDyQ9qo2XrrRh48Akc4EQF1G7SGa1z\n8W7PWZF6eKZk0azr4QKnbC0/1biAHjvdDbOymP76EfS4UTM11v3RzWxqlUFm2kqNeVpHZPy2NKRu\nNpKxrJDFC1d2QpsJlT1jQzW8LV10+SSSPj51YUKirZWYYa4wYMugtIQlohEOvdTLdt7T97Kgkw9Z\no5N8WM95BbPTWfiAEwTDYM6kGhQOCh+7SwDNIHx9fQCEoE7ud1hkS2U70ByEP4YTI9rYa6ZvMDxi\nF6s2qU3uqA5kpU9UD0/AI8rP3wqB4xG88d/9JeK/fV6pF/A1s3V2EQsY8rXOGghpNiy2R0gNYa9D\nHi+fjXiS9EaEkgM31M2gWo+oUpyyCsNKOUDjSLmF7B9D7HXuSn5v/axhadcur5njTtr6O6jPfX81\nNTzKcyIndJ7n/KY7EQEDTiBOqtPU46/+tvrggOIJduC/klcmGiJOGggMr0QOjBL/hmWpz0ut5cC6\n2IQBl67p3mwOtj3ok/FfMLx6h6bt9zUcEvq+f/JvCCEyZHBCoWIuTyAqpd0lsiOtPX9xiiS19gGk\nZiO5klN2P7ucRJFNm5fGrWBHjl6td8Y2jVFB2bmhiHxj+LzxSkHLZKx3hlzclumt663rykZV7J/V\nOpQnoLOhm1VnPG0a2RwOI50uK1h49bcjHAPf8IeH23eFtg8KfRKTLZ3tMZgtWyxK5mPM3XsxsmbQ\nRDQ5U4luxzHz9zY6O+Jp9DsMfvFJOYoMAd/Xf0/1OtDJPxwpSwrIlBPItlBz2XiJPyd9bo9xZwF4\njZsTZfJKt18ckYdg0vSq1Y6chPr+58JEG+R8Eoyh82/JnUgXqeDSDo3x+ZevFCtUN1lqKfONmwUI\nOkES8kRfJbYI4NKhIAyqiUcbdi4m0uVkMsp2GIq11Ok8qGMdCc1sTT92Vy16v9s12wUJqOmjYiJ3\nN7yQESissgaWzDOFR7QLobhaOisupX1t72or9KtxgLvmwfOp3nVCOwtjdymUySOh7e0zQrS90IO8\nDMoUCKj8phiVBovw6oqIdocKhgYAaVcG1O+GZbfsJzohnk8xh4VaR34Lv55Bhof2AjdbAeBnQebF\nyTHhnnnTn9BkFGhnpWr135xc3iEdB1yoaSF1q7UOfAN+jqoxuoucjglLnFZTQhuQq9PpZYSa6qF8\nTeivjaZxGDbkyYWWL/mYtqk0WyphJmNy0u7whly2EU/DoKhN/eRXMtOXjM/00uqhJ7JkyMzAzE9r\nmUD3n2dl0CPLmPp1gK0wYPYtuvSljftl/MAUIPRSORtUtXm/y1uP/U/Y3L2xsG0Ohe7scOnXBsHT\ndchQ9mJDXhqs4RaspWBB9pGcfDuAWFmLTVWNYXTYwaA1THhgpjvb6ZkQho0h2Cnnu8/1kbl0RB/u\nNSfDkNDtV0Grb+Yr+kMRdQ+KG0Lh5L2nr/aqWGnTUHYsKKBfLXDWDfz7XmNLdzCibYSUeGejKDxt\nzJVE4+riZIRoFHXw670hdRKtpykl3AGs64HFWAXJRmB6q07KDdzQa4S44D4hPVFlq7LX3GRkj62k\n2Ab1JTglaWBPwajeRO1Uf9BBc9W/xOAyW/mo5dr5UZA+HgP4mMF2RpG6f9kn3R/K5koqQFoce0Qx\nRkp68YwPn2ATuoyq7V6KsukrqpUiqNiGyVgUAxSQ1N0SYamfjXchVCDrjybUZXUqiCUoLNXxBZBX\nVJG1mH38TKeO6BHuCf4ME1J3AeHx6uW6ToXGg4OERC7ir5TmyfX1zbN8kfjUx72YHK97+nVzggPf\nhV6PSNPyKapvR1hP6KBtwOQThChn1Rha8jrWU7qk4pYuMmTO+8FPkiLzhUJg7stmXs4vO7A9O4k8\np4SynjxIoUWmvnwHNn/nmUdxMc+9Z7oruUXfW+/aQtTF0JR4s945UDO6/kd8G3xE5qe7Vy9xyoa3\nNoZyoOd2PSkxIlN85HBjNCL/qE5MI5kpuFEkWjRezqzktKGsbzjACTlB2feYN69/qwaiLrk5U5Jl\nRAspfMm/2Klr/ZyHoQP33X5s1yZwQmir6QqCsRghUh09U3l+s7mz/z/r+EgI81b3R0NOfnC5vNfu\n0ZInci8q/I+mx8H3rqYBWMT2fCeLkYEAAi+Z6Ppr5hNKXHo05Dr/TYBVTzzeAID60+nn1saBr3PG\nHOiE1+yWjaUYdld7cDPOi5Sg+qQ9MWy7ubQy/lZ7Mc6eVHHl/Zi4z3Aig0StkCLXUz8xC3PmoizR\naQmW8TyVLS1vvHEFzvw/FWgPki9508eOITzFfG4gEUW9CxlJOKyNTvUhVqdorkWUng2q6ssNc/dx\nbB3u1uMLZqHfye+9zoMGQb+FLvXH48IyUwpRsya70EVrdGtFGz/eJSomQJHT6mD0UUzbf9VWVXoA\nBlVEjDlvWqEypgNEkL/oaxZkDc/1eRfnKjHPXXPaBlkcdkxsDIBmu+qurAv8o6tna34A5xpjVD5o\niGD/GxnBCej1BDP45StBuQhwkzRUE5TI24MV8iRGZ+t6CMtHXWq6Ec/EXx+s+eMe51x7F56ZxXs9\nMo23Jen4ojXg4tZp2euH0Cs1p8vTwuBo3yA5lnBwO3OuwHvii/DTmGGAHK2a7DzVI2BXirlDP7Og\nikZSZhmGJKeMw4VG3DTYQR1Apm5U647jH3s9QAv2nrsEiCgW8APAZ1n8cIJENS6nElC/PlD7enCk\na7mqzQe9cG2orQ1Ktj4BmNwrbb98Ls37ssjSb9Jx+FSWg/TYmAji+3WqoM+j83OY8YEai/PWkEfS\nW/3A0njXyb51hCZC1gU2lfHaTucwdnnn8y11HRt3AtyaXJD2aefzU2h7PSk7jbXKwBBQZQHRM0uE\nDbFbxKjKSqv7UBlF8B2hg89FtxJ2elEq98HAZ7BjPEGPxGBFKQ5rpsiQBJ4c73hZdzvWk6sJgsQX\nSNGmVPnkyllQZRoNczb3OcA7kWrd19zRsuyW8bIBT//3nhueZ9ZD4fsrGGmxs0YL3hU6mz1N8oBW\nvK1DFOgjnL9u6f51K5ZcIf44q5T0id9+6pa7Im9qyI9YRkENyXX1R19YxtOS2OEn7CXxCrXEAvee\nqb67T/P3CBFDoW5wPve11RL5cFD2NkcRfv7GvKHYNzpLFASMGzli/XyfsvJdREgdAxXfJ+P2oLv9\nR/WPfJ9MrRfhXB+N9yVgS0+/uLJpsAPwSlkqr5mWR2ynT8f9dwLD9kq/6KMoXPwulnkrb4RdVW8f\nlu1uUhnfez74mJeB3HNuVgDhvspNVMRmgKO7doJ6P1TJHUylNnoYQ2OOcNA0ZALgbIAo9DjavBTR\nWfuMngkoCpxePRCI55Yx2lW9VLkke9nKfxwgzZjQiLdmGjhbhGGdhMn3bNLvvQ16U7wD9iB44r1y\n/E75B0b4JeII9324Y2yhW9qtWL/VftpZST7GJuG/i7q7XgcIM3OCinME4YbE4eKzxpRWtKrEmgkI\na7JM6bpkjhe7fCBc+tq5Sfh86GFORN+jKo0w4NGLf7UP0laAgWKgKf6d7oKMRR3cP9a9/Zeut9zS\npgZCXFPSXno2Y7+clV2ofOcqQxL2s1QHjoup08B9O08Y0qcY87G5x55C/p5/oW0zdRk8RC8mOC7C\nkm++49eNIf3ssG9lkE1lnYYYrHSiZvxB/4evG/JBSRUmaLSrP/W/qskh34H/2YIaklHJ4SfafFvP\ngG4YcODaFis1FLyyToE1f1wLg+D3IIW1QJRi+5CeAbbSb2kmQ5a0l1Bqk572U3yR4PfW5kkVBlfq\nymdPpUl3PoSvhDtUR3xkAxGHAz6UqWcc319nJILKwLcH1z2ffUj7WdiUH0HI3X4QU02ArKjIh7dv\nhiC/Zx1AcOBQKhZ4m2qm+EobLULWuM0PWeStmZxYFy5E/XZTGGWOlHsSaRP81JQefyJn34jkqiFZ\njqo9mw0J492fwA2JYya7RzTECKjm+LP/I+Krppsjh8VVXycF5KiOIFIcm7Mkc1q2fvfiC/qhhrcx\nIkhOCQHPn9hEuOgDxKmS9sC5QmmXLoQyU6BMq+dnKUIh5gab1ghF5VKQCg+a97qK+JOq+V5rbzkY\nWNc9q1QRvUOe5UimJGMM5kz0HDH6uj+GXVGMj2Gh9cSyyQ9Bxu4KW6UL3nGYaCpcquTAyxOoWk2s\nkz2g3NF7X2pNP9P7JhEM+/b1fqk82ce6BnmqP1A3m3i/keLgw7ESg4JCN5Gm/GN2atbReOft0bht\nWn+YuXJf7CE60OtgRo/Ag9/OXwfBBYlnEsazQVGmBQceXqnEZm28ZnmSnL0YlFSl8cfFyOsgi4aR\no8dJWZO7A450GkHBnng+idVd5UZm6tTeQ3jr7NAMAiK2RwW297lMKmd7MD87eF4bMX6+h58baT1D\nD45nfNjcdCwGHU+YF3/1a/wkTgtYZYGqWm0PHPjEuBailGTvmOs3FIz+EXDwmWXzkgraGFjJUciF\ngpvrRdXC0Lis8wQMM/Yf6ZYqaR4cMDq2ryowgD4rJGLDYYQd1LDT+Ay2TfBPkNBOe1yPbj4ZGvFi\nEW1NA1AXcnlmyXf2I/Q4eBUSJRAV2JGrMHQsWaM76HM3R5vf6ddPbHxyAteHULIvGpJQ2wyIV/Ty\nKaPEEZxk/Od8xSSkyZfFF/aP8dY5qL0LAnokeQrBcFci9kIiNhB9RotAhBtURWiy64MGw05tWMDQ\nSD7PTEEaFQVRpB9GIkxPXqP/PKPmGbc34XfWdaCHwDO+CP/ZiGHJf0cE4C4JaS9VZ2t95puaDS+l\n60bMo+qiHfi/aIvqIcM7h8s6OBKhGWWHwDqiYToybqQkf6kEq/vC3XSBSe2KEQ5pzMIeG7eTTtmU\niK3unJg//lCXHH7v3eBZykBYU5jr2CW8V8U094N12SlAjUV5WlJHPJ1c1XByNEXLZyPrPmjkFYOq\nL/m7pKPhv6muIk7AWp7o8ofhyGPI5Gq59y5778BvnFcBM6LsDRzxda/kCdV9OVoUvE2k0tVDE+dE\n36hkvpsEV7ouccRINpDNQhug+uKJPqbyymBKrNSpU2bbxs6CicC2EqFXn4SQsof2I5OSx3E47V9o\nROgMSi7MkM8fRNazKSt/W1SgAe3go2K8yw2/b48uikD6JP5GDgUPS/GJU3SCuj0IS/tNxDQp4c+E\nSWDaPNU+bIhXNHV4PxOyS4yN1mA9DqKdkFFWo1TyWsw88jL44aWiFmZYcCwIqQYmRliKV5eQcqWC\nsmikz4YnEXKWjU4iVpSW31RVRJ/iKPsnX0dyHd7mH4RnIJ6CvFm/QFJcQ4y2SlqBJX2mWQr6i6S7\nhQe1WxlzJhdqhcrax2ggUBgVF+U4X+7xXu9Yyk6Ox41jhJPLLXl2L5vxRuAd03jO8mCNIlzjKMH8\n/MRyjeh3jHm/8+XsX4HKe0VJDj42OYj75UEg1xnkD+p0cDyqMNN1JwHN4VDOfPvPmdWaiVm4KHdy\nTp7lr7LBeA9y4Ij1pa64DiGrBZ7yXYsuOWIy8PL9zKuVy9UXRrutTi6q0l3oQyFCdj6rX74bGX1+\n7uC/5vYjg8dg4AgBwd4EyR65+NmD+4abjSUqnFMzxND6KKFprHTMJM1G0Xekd5Hm4RniwNdPW+wy\nMmn2mVAm0ziFpc59pzOYjenNtD7FDKO80tM35kRuXQWiEM9j6mtci876JKgNB8Sut1vgeFPjXW2U\nePYuoyfobJzVADIRPmzSJCaz06L2TlVE6v72JNCzzC2YFEpzQrNs1UWNcEPGDlWatv+XkeL8vEYy\nAtsAfTBQWexSLUrWYb1gw2bTV+v6oGUo3a94iwjXpUD0+udgthtitWRCY1PvizAO9OHHPAopFD6H\nbGG+fBw3I0ARV31UEN501q+TCC94ZH8s7TylZzY47Q3IZbQVcmzat5sv7cjGXubVlUeducDnB9MF\nsKqXQUkQK1U0HOurDr0n/miwraaOQcXjPgopYsZ+1QzwQJRLuZmBJJgHA9RIdxZi2fV9x1cuRKHB\nQZZzFbBtBE4hPVNHboKyWtX+X5MBE1s2t7V6fDGX3VQ/xA9un+HImFLQ4zUrR4XqPrHgzVoeZDpW\nvp5F1leiM8+hDKZuoPk3E+rRN88QEX6i+pz0K++3N+e/OhQ1c7JlDBm9ibbjXCFqd1Y1GYwEX3+q\nagShxl2wmZ+tpcR9yzczZ3bH01YJjVU/7411HvSy0JblyailvSuDaAHtS2gGiNK+3LZwkG1byKb+\nvGJxdzhKni09FUF6+sCoXhCUMeLKPYeZ8qubqwu+q31gFcYiAOwgqVnUtwLqJeGEOP9uyVJwfOt4\nWtIKq4gkG4Eh2rFgfGTch+XTs06IEhrrrZ7GQMmUlMY2YnS+bgA9VdfGqmndpJk102I0xYBMELd6\nsVkLqSblDZf9muBKG8AgzAkiYsDxwTU0E6yAH65MLFNz5F3W0qZZV1CKT0nHH3qFf09K9CKAM40D\nx6Uc88tEOFsKiIT7UTGrv05/Mn2STirjyywdQfjkKcJpwqNuBoad2ohKIcKWUxvNyyYRoIhc7T7Q\nHqUw9Ewv8cNvRMXjWGfjn3ADinlVJSz7uhM7oDuavUPjlTZyC3PxUMKEAVcw+EIgoj7Y+SHcB1f4\nGsZtLYb16UfcTST+D77Ul3mNN8RivDfFQ9UqBe6AWH/scaP2uB4f6AOItbley0ccLObu+ZQu7tXa\nMTuatLllc7Rf84Bp+cfx1snDkoFY+xoLGwqx21Fl6EPeG9038MqQSbTPTDeVF+Au3QzixZBfD/nO\nyvQ2XpVOHzBLdB0VSIs4TYy4sF9dFmlFf48YggADX0uQnS/2vb04ABz1vzZvKF4RKVAjTyWyACsB\nVf6KhqegN0MgV4Z9fWsdrhrZnAQHb04agGe8wqSRYbEtHr7WVJUd1tglKP5CrPhslqu3h9Ier1GS\nMNsHYq0pC5zuAu5vV0WAZrkbVJsGVzH48xE3CCX/UGRlYeHid+QXBrFnoEZm4+vKqztIxz8JGI60\n8tiue5wZKDJZA/WMrAydNwrP/FmNt6yt0LA9cRcmYR+snH9CJLK2K3Fi6Dx1uKLRwLXl7r3+FLc9\n9szMVpqaU4K0yGgXux2jDaRH+A4Sg6ItNrDuabqMr99WY00ICMZGAUHxgFwau6fjlOtg0YUDrICx\npSkvrzRZiyba0lAwL0zATMKYlYOHWDJ92hHNILO6fVxhn6Vj5LRLP4hS/KKqeHFSf+DEplap4MqI\nUtveYsvA7g/dhz8oJ2FwKUnQMicyK+r7oJj4OjOxUcLU4ZU2vbRaVmfgy968gWqs8DNqFDNViW6V\nBy1HD9NwdcNMbg9S0QIUSkBidGb0yYTfYrYGP9Xvu2BM6NsrvZZXYJL/HBp2tnNdjT4cIFwum3cf\nelDLB9qkzrGBBIkok8ywHs0H6+XVLdd4h5yj/tZMC7yDTXGkuKRWhn/Qbexrssl2rUrU3+zDi3+/\nNa8B45lL1h3JAksZlbAf1OmzG3G0XP6+IyGQCV/WyR/N7zyaRkAYMQV6Orb8QGcN1GRJONkDFu0L\nepGDOY9Q87pEghCUvs+veOqYSyYf1WZnFwMoImn/dyoMwJcIy+tRRFN59x4AqfK+eRYyd1oiEPd3\nty7LliR854/kgSc6qWXCNfUixKllSHgAbHep9StrFIbQL8D6vcXACNgYuyopmhJovCKpGOnbMhrW\nk5hpZE055rPAHijpMfg25EKP+ra7Id1wu4CZMRAXLHLQU2cSkci3GTSovDiZ/I+3aeWdpelEO9F2\nEUazfjcxdubRNiGSH7AcY2fDvBi2L02hn0RJqzbIsdbp4r5+1jjyTTCNuoNnj5VOUH+WS4bL1YWW\nqoJkNX8j9qrMcBHdqMFj2xwNDZ/4ooYGsliaETsHDNdBKCBaY3UJwe6ZDL3g3f4yZXLPeuwjvqyW\nVK/z2VpwdRUgYglI0mFF88y7+05dXm/2d9Jgp5GJnQlNgP6WazLf3UFXFUW8iNbkS26zstKlwqtk\nkM2juHyumvYu9thV8r4cf7SXkeEW3l7i39h/hcJesLLYqeIegDmZw7+tceS2IdberB2zTF9oY/3i\ny1Qpi2sVaKAuKe7fqqzYDGJR5fDkfq3kCuz1B+PfxpSF0ogxBfYJKHy73ute5wrsxoaRQjYeydsq\npfb0NJso5vMOYybgK0hrwsH97MR6KGWf9dRf1zawwuWhAGzDoG4gwxQ6O2s+CuSHa02JY8eJgC54\nwUEHi4IWgEGv/15g7HamrFTcmyKxJHPbIsDoSRM9iN8tBi33AU1y6B+tWTWkYe2sVt5sancFVl4W\nvgciaxoBRXNgrLFo9qej6ILriqP8eAvKz5NeHXdCQ73W4oDSk1saQjQqSO7w2voNnkT9PHOGSpqm\nlYGSAVDbelg80OQOvQ4Nj6i031QXMTON/t2S2LfPiapZEOJzKan/OIe+H/giAF9KUCeft/lFNqZK\nKUD9L+oMIMqHFs3kW8y2jUORPNw97spJMiTDedTN+QLAtLEvB67n7J2WCgxlmRUGZ4hgxVNZFwN/\ns262TFL0utg4Wylf7B5TqpOgRNyenuIUWYXnD576599yRq8UhGBOGCnbyXxuGpBREJZOPYBU3u3O\nGj1gRMLSFID2KZec2CQtGX8XjrvNWeeM67wxomAQeWZqvNxfzMslOvb5JB2mrwBYNPYRWqFvauYO\n3awSQT7D6lArEsn1oE3a4fYfrnfd5NH6ltMSoNsbGW6wTu9+UoR6Ox6nAMx5Huak3idkxZc4uFs/\nI2HqBNQITyKBADov9WtdK0A6nzmmioPs65MaSEBQtHW7uMmd3SXBY0mLf40XJEIEliw/S3XzyHEd\nVXZJfNERB1pv3uGBRTkC4vzVne2rEOnpNCePZRpq05Pc8n1oTRAVn8krJylxrbB6KyDqqBnqZPYQ\ncgXU/MTDnc1bo/5jH6YbS4TaWSKp5F9P/xJYL5wTjQF+QiwtQAe2T1CUSaJyxGhx5KrWCCRqF16p\nQQgISK5DjAaeC7MvO8vpdNpRTsCWOlUHXvjRRij6UXmUGdpNqQBcXFxuzETJ39/8VrHeD0cA5c90\nzv5HKYG/p3omUAxwj/IqMd43jRg9UvHyB12s9FmiNBHqtChqRoGaLJ81+ANBVIOrTKqBU3EKYMtN\nH2+26VO9KlivhU/+ZxSxlEnCaZ6aaJhbc4ohIP/ojtRmQ1U3PsguRfpkLYFJxBnxEgP616L6qF5x\nxMTaIEYXiEApJhYn1dFFTJxckKkI0H6mlvxLfgtQhfw0dM/PS1vC2zKTXnhYFD0IBo537wphFBkR\nqdbjuphT9NhVKWN8Wl0C+VXLeMhfT+gWgVMWzQWD85gT2i9zxqUtVckYVO1lVMSYff4DU28ofkKH\nD72y2WgKGyaw0ag1wXT/dq/fZeR8LVyziFh4u2JN+5BShbmO8V2Xk8RUkJzrjK4fiFt/g6yYMlgO\nYl15c3pZx6kHiW/ckUlMTojgOFgSETXa1FOWAPwoAys1Wt0tscgMAFdUTZIt/CFTb5qKc5yDJ2c4\nBwF615AMYBlMzRf8Mao51F83L5VL7iICbzdI4pjt6vEHYm/bA8whViJemEKxV79BJ64MDftD7Vzc\nXyYUxA2/d2cfeubMPWwpBYI5PBObB245VnJddZLCjgv+zgllTrCk1wZf1pt4cRe3c3Uoa0Ly4XOW\nxpXbiL91SwqAr6RYQxwmhy4alsXf2odG2Os5V0pNxgLLUU4hp1i1osOdJpcQxYgValvjAuWVc5Uh\n3RQBnaWm/SMm6W8avIxpahbiMdP0SIU8RmUFcbdiI6qz+mY/mFNdB155UMAJKhLq85hWWrRgwN+R\nY2VNc8eP0awXNxAoncb/ECX+nzGIPL0TY+3fklyhBq7Uvwepppq4J4Mxnsa3Pd54+3aUrDwbOyMb\nilphgDTCsJgR/emMcwOyuzhu1aO0s0fT4vNKhVJSjzn8Z4ykTF/wU11s+/7zOMeFs1AAmEWcwDwc\nZ9vClo8h7om7xHs82VhEqDCL33wyHUMBO3yYa7zqevDYpqYNhJIkD+GlJDCw7fxRTIb6sZFLaNiC\n6SY38ihJA8uMYF7A6G0g+YCuGeuPp1olZtc8gWJsT62JoZWa6VlLSL7C4YDdxBNFZUuGgiqWniv6\n8ZeuN02TLgbtUpqfFDQqIvCpMzsRifmLsR3078zxdPJKT08gbK8M/NLyac6PQQwrgbdl2kyuVbFd\n2xodCIw3OzQlbH9Bm5VaXsLRBR+Ir6NIdaCbztB64C5dNZ/y9kknIDy74+3qTowSR2SrOkD7k6Av\nd5IWZ76z9UZL7Yo7HVj805TLHCeXiLFznxOpGqqBDd4No3MFcRH3aZeSa1wvhkd954D2/d+KHAsj\nYAz+YbNFaDo1BIV0/kTghjj+oHeZkWJ+2j2/omUc3QO5wBD7jijQ+Z54Gh+OCAH3WDQEws3ULQin\nJcevYDy74pqhRQWagT7/afbf+Rcan3aK/JM7mPQdCQsR5nchas5NTV7ZOJjQbIffMuCk91qUOhMt\nwjv3EXtB9tcjuHG8/k7MNCwDDmxm99Naj0Dxa8k5DfpNw0thp4CAWdzh3xLUYU1S7ZBMNlZwQUMs\n75wjDY2yMCqJoSVNey2vLCxDnEoJc326rWJKxs9n6VyNsA+ypRs+PJD2LBb3j6b5F25ZhxAMI+E6\nq5BjixaC4UqadXHMr8gLjte17sZqcSZQShcdqcD7SDHQ1fVozvRyhYVMgI50zIYol2HQhZhpgPT2\ne69PtGNbceyBavfkSRTROcz/EVQpFI6tYcKO+Rph9fhHKM5/Ktt5aAHUaUUyfLnwXOd7IQQT2wSr\nqwH15itB854rdhmlpCEFKK4sLQARMy90l+pZ8FkjtA+Uh6bXzYP10idg1a2Yuywk7fB9up1CUoSo\nWM0LPUoQQosjZmPxleaq8oZq8A45iSa3R3t0OpGWtI4iT2uO5TdqeE7P9/hCyREaYx+5psSS/Wyn\n+egqLw27j86TRYre/TgeKhF4yKBwhPVX9JpiP/KIvA8mpkPy7pJgWSDnnGQ3AfBC+becxsY6zUXj\nsgi27/gHYdM5JpicOs3z+/kT59v0SZYsLsYlKuu5SXmbMyPa1Bt2GDJg0Rc1p93QYxy/wXHBs/rZ\n1XqkCwBg8iDKGFF56lBRg7EsNu1iYG7HkMSqKjEnwj4U5jkvh9V9SuicjIGFcr1pWpJIaZcSWNM8\n/dcfk80bPSp01JjlJzowbmsS6TuXoZxe1a3x+qBPU6ddmDuu4ZkrV7DB71Dl/oGnYTkYCfH571Ai\nSO0Y59/L6x1azSLrE2SJqA+HICB+EL5XXPXcEAAQNwMS9chYxKaprkwLOlqgOU246ucXPYCq8lJ2\n4ZTe6lvILX1qwI99aZIxYxm4GCOiDY/vYJoMmQCpS6rzkCBVTSam4jTPicHatHLxavi9mw+gB5tQ\n7xQ59H3vdbMsxm0LyFyP0o2Ot5mNek0azemUsSwQcr37suK+72hyBRKUqBhdb3qInlhETKe3Od0r\n/C2mzJ6yZK2pkuVQvUR61Xjr3xF5WGGrHClOldrcuMzVnJyYPH4IzUfW5rDeAotBUMbGj4y3aP03\nk+bIvoIA2qgQBdny8HT0E8KlXZJ5kM1t4oc594YKzplHuhpS0AwuI8XLXfO6bmEuaJH8lDTdHVrR\ncR9QS4tDMaY00JOfCVa+VtI0P75Zxt1ByqQw1L/n6kfCy8wtxR5HucNAdgcJl3qDT7O+VHnsux8o\nBDUqjifWr9qEo4sN/ece5e3fw4eiH4nfQkW/OtcvShc2t0DbbQGnAtxKQNdW4OsvrHii0NfoZBzH\n4Dwhtih8AJ7CtZnBFMYpktmhU6k9ZmFrE7BSjwCSW4GqQU5fH4ynSeVVvouvksnzNJOinH+S0Uiu\nTO2iHdZP4nnyNFM8bsMXmXfXgesPwNP2hwP4KUDEGyyzX+iaZHlAD2uslvZ3RTHwtqRE1p3cdmrP\n11/bAKEELtgi5GSZTgwATfNUVSQakOuZFiF9Jd8XYcOV1vGaFX2qflcsxdnKp2RGZ0D3D4hJLL5t\n/vxKSD4E6aXyxJMfEnaqtX2PAY61kymfrW1zENc/V+KzxSsljqZurfyYPF1BJ3F+eoyPQnsfs6f2\n9D0q1QUtzDncvSVaP5eSF/efJ0ygTsHctOn4s8zvBNJbzF4x5684P9nP/rtHGQsc8Y45efDM0Dhk\nn/8/Ze18DfIptb3MAp7K/hie/1Uv7Y1zUrK0Hzvl/F1zWxhWxa9n+IsfnMyJPlJPEjqgp7bMqygr\ne3BXH2D4heRCq/vGoUzAY+V2HTdNwGyXHRw70td5pg1C+h6IBdJ1qNPp24alhnnJyqHjk6078OGT\nQ2VIwmmHAHcM9KMX8t5RyGPJUg9BR1Cbo5TQIYbKTwnAv27tzpZUJyGvjU7d+B1oIG/7hkcXeQFR\n/l2ZKjNZYWni7Yt0S3eV/tejKANYuA1mLBlYS2TBrTiPHED6LGDEaDqnecE/4G6uzHvwNUQhAFva\nPhChQEtJHIxAf9TcIUPLnoUR0iHkyvf17V18VefVZz2ErwWbAVmiu55PUL/GBQfmisBbV92gYowv\nQe/4cvNddd2LqsySpVHa1h2FeM0tBBRSWh/ZihN1m5tl7ZWpEFfpVAnDHzL92/88dzAsawjTlI1y\n+IBnM3gx7s+8IryLcfexNm7PDogGBL+AWdIRvTSPVnsguflZLmuyidKXKrMlhEapoJko+H9/cI1a\nkj5NPNLuBQ8gqnpTg5IRnYV7L9N0bjs7g/dv1v1drAOPRL3CYpKrmTxJCNliLN3i3LdaRay30g3a\nCO7tsSC8gftJLcW+WvqzU/+VTH9z4Ck10BF7i4pPEpYq0HlltvxkOhmn6Kle5JLvKN8fhStFNmID\nCQEHRDtsknTr5BLh/BQBwRgTHNs8qAcR4cUOKs1s9s8+tmkmWgTMnmwi1qvwd7HCpCS1xrjWMZLi\npWwGuIKXM+tGYB3MjR3tR/QWg45QMuALDRhzUStGwMsU4CqcozREet87o9lSxQm6AFPtzvmNPdmL\nIKK3BUEN8OFjMBaZwp2DXnPfbiG4AguA4G/vjdLknN42nAbTWdIbF1hs8vL5/Z9xZbY92njcDQP7\nOcYOdPAwGpKZbSfiakqGuZIqiu2vcKuKD0TODy+irkRUavo3OdMlH+xP6NgJOk0nd0VPL27tQUU+\npSKJIoOnrV/U15BD8HMTvJ0NA70gFPjZLUcDnq3Z+NVKWKNmKUfXT15+yQFykML/oJNRUBglA471\nWBmN5HD24Fqc/amIB1AaZFPMM8JI5+qdc4x4dqOyWFnVXFwvQjWvK8cpbYl+wXiv4HG8Knq3qzxD\nSCejiSul23zoRldV+W83KpH/GmKlpgVqpP2lnd6PEDr4UmgDFUuBChwrVui+F73kSz1KaLUOQW74\ndGmpd3+xLSQOzd9dwQPjsnGubDSH9+uL+51FceWmynRp4tboCM+GXxFVSImCQak8/kLIS9FWbVER\nkuPLOdqaSRNlXFaX5dqLu9FOs6NafiDhG2vPFKj25mZw3NWsde3yeWLNYEZaBvQHsDFiWs8S2XN3\nLTtiovGNVA6sSQcuRRfyVMI/ha3MdUdKnwi442zgHK6v9Uq70joIyMKnlt+kKp7if/xdTRwNRyUZ\ncLcCJJ0vICERuj/w8bxXidDJ+5AJJQRx41QkM/sdlpybrSa21SN9I2gMLiCK0i7skDqe94g9gw8H\n1ElUfsf59yeHoSWDVRpIZTCvSlTQcMGi4bMC106DOUWlSnZEpbxl3pMmLh4NvetlTLuQWZKgyMdP\nxVP0KMJG1oMxFFwR7Pa4dKQwv0h4DX+M+gkzhr7N/mBS1CuanB/SVR4qXVHE5fqDEdTh19EVBMXP\nVuDWKfZgHgHyYTr3NodtMZcqZzajj4p5w4d3GmR1fNBfOfhT0Y0eTQNnIOrkoN/P6yZsnQVv1RlA\nDQ15az07JPF31fZqv6KHXSjxZRS642041nTADzgHJfd4srOEo6ar/xrmFzsAQwGKAjrOeiHhj7k7\nJ7HG2pINVGIe20OymsxCgsh7RNctTRKVcSWfgR/HhW00tqKw1Bt4qHOHRWLoBLuYoeQiirQcqDI1\n2QRqRI4MS+yPUkNIUe9hHYVhd6VTGEJXnL8dFCl7dkZnygrv83vLtwrhJVSLDDjZ+DAOXok1Qo4n\narWWg5kVC7XlB6/xe7WULKkhEk7ehngXgHLoWBgwJKv9qZIF/uXGdgPsTv0YQ+rs8NoejLZXpcfI\nGAztS0+hZHt7/7xC1cz+UxTCWGWqd5blcrlnqcGrSfTmD/2JfkDgGKLPMbEDaUcW5YkKXpSBUKPn\nLcApBcXUD2Q5OcdoJYCSfnUKzk1RAksACQmLGaHBCdaORAmwh41ZvO0wscOXZSiVBGLMuqC71Vn5\nkrGwefW8gG0sTAmG9kqrtc7zcK8jml64H48eUvVhDz+rogi9YVU72dDhzy/r+ul4jFAvBW5ULWkn\ng3k5DGRDnxAEEecS/D5MRh6+gFzUoNoDGWTnD65swWx5fd1kgPSoBxMLxr2jxypz2GIbUsIcKIk7\nTdxUfdnbH3/oS55UvcFF0kNW/pJjEn+HH80tqLHte1Pusesz0qhnltdYzQnLzKo8GyD9zpIRqN1T\nWt/ziUcfVClFxA53+xQ1oWlPYB9Oahd4tJtxrdfYdJeZmYEfw2DnrrdGwZL4TT8YE7nKGfJLQLoz\nkaTFljAqGYBDUIaY6aQZtSjB6GtDC/PZQGhkA2vx9Jl1tpLddl9aWJ38GSd5DIHC1EKmI4QqovFF\nZbAVbBXHoA7G1Esb6sB/B2QdjooCgBzwlrWKl8Y9k3olVw6lPtENtEhHgKEhZJM7PvtRX1fMaspY\nOJaK491y3gu471RDJSYXzLVulR63t2uXY6NyKNo35KGU/N5SsmZMlSP42HaloAyDvfJzAD1TvjE0\nHq4o11+b2hlzoc1oVyZa7gLmuDy0cPdk5j4HNB1w1B2wrAuQ3pL3RGUqRypLPH1Dx1HyeYC8o5b2\nstmzfd587YfJfthSYEgGPaozKtpb1Dq01BaORma4S4EDqkJiUxmPGEatrBH6D8ywS7/kxhlWp1qv\nLxEkrxtWr7B4pkG3I6/OvKn1MXj8F9rzuhyPtrxMmCD5Y2JFgLQJxTo78DNIxZQUkA4KVvSr91S8\nTwK6E4ISw7mh5UwbICzRWS5SXYCBkyjxhWUvUjZGiX8mWqUflwy+xCnzL9SATWCNuqy4vr+HSH7a\nKjjrHPYqE3CssjYh2Yr7NXgiFDL93iBeRznf0IniUZI1K4UmfvC1IcEGkTvYUgc4wV1p+34uyKZ+\nKcopoBeME42MRGnWYTJT+13msDO+RE8OomB4a3P+lx1aVN39FNdJjcT80itlp1H4kiYK38ojyFew\ncUwEwFpTqZuDSIylxxukQYdVMHtBm9Tk5qH2E+gKR22vFKRr4iDuCgnf+gxvDHlVipErUC1EozNj\nqskFIiX/EYP9ltN6QehRcxXO9IvmGfauut+VBGyfG0JW/J/ehPcQt1cKUdx/kCdehpC8hzHXV5Ly\nqQSDZ8EXiO4wNFGYycy7rbSNyimXnI8QROfvB0wQhoite26y/2SKIUeCC4WBPARhE5ziVzQNEQJL\ncPyf7Hyci+Fp3EiLJjsBU++EKX9zJ5EKtzQrKdvcR6TvmbcHMra64m8OjXjybGZ0vSF4EFZsb1zX\noYRI+X/WDWO6plpPHMx9acO3kip3zm1ZLeQelMwuAUZQj/iGeEdBLy0ap0mhYErB8ZH5UWbETP6r\nSB6NStZryM6J3awA5aHL9qYtnyRZiy+AnQb/2yuZeR7MCBImtkrsPPzwxXmlM+gT3dN7j52qWiiV\nF71BAfbnF8VnLowIVyCp36C5vWElRzdLMjEoe5A4Bi4T+/XZ3nk0sQN3bgrr3Sxy5BTfIh0mqj4i\nqxnonv2nOqFFjvy5c2J66N6ChbPa4uFbTEaizv6r1oOsfzA/mP8KydsBNjzKTKTXPZBooEMET0vc\nSdYp87VEDLCBdwhCTnCgsM+HIAs71V4WCFFe6lGrLNBE8StlwbRYDMXoVKDaWdcKLIAmNfg6dtZh\nOsJbyXc0nsWp9j4q9Azn6ngjLXMryua6TgyB8+XKR4xGNItS/Q+YkhfFz3r3OxadpryCc/a+v9fk\nGXRssaIs2mIYjl1UJ379PGriwmrXzgUT3uqMbZgR8kX6MDZGIeA1UIRExOvTpBWsRTg3GzrP550U\nbXWWobW4GaqTfyG6Jh1/x3OW2t5wIQatmT6YRQ3u2S65N5bCnU3uzMwCR4M6lCqpWhASUmSsww2Q\nP875far4IB+WZkI4ReHN4i3x04yecZbHbT3F3EoPNv+mBp+QQ9Hc6o7NRgxpzvKoZLBv/dHRX2mi\nN8Ank7pDaKppp2JRp5NvMFRsfKLDYZffwTjvw1Lf/A7nTxYgG7QxMuSv3zbYllTCnWJ9uwvdwk/Z\no4i9IC7gjaUc54V1e0G3GVsdd3xHD6OnJhfn8+4I5AUeYc925YRMa5UmNjeODnd3HZXQx4MkbGGQ\nCR1lOmNd8Fj5P485RG+jBnL/fOOWa5MEa3SBVBrYrMHVzX7QDz6fUrDGon55PX9GaaGwH6Z11epW\n1Qlgi7WMrUSX2G7CNCB7HlIIndh/dc0qoELiWD9l9mX9j7VBPJnq6TiHqdMZC6Hgdnqrpi3R7FfC\n8lOp+04Co82uXjmQNo0Iczd+2xr/7OTboQBafBPSie7Q2F6z0z0qOUk6usSC9QBwHUpvbEMFK5bU\nM6iueiQg0+5h2yi4fFr8VA6Sz1HxOYEbZz0Fa6pp2k1wy0EQlLoUPYjarR+SFUfshcEYF0D9s0o8\n44vyzCKjZIAuK6IEZV4KkS4E47TVYS6TZNpxnJjvRz6omquE6TcjYylJBynRuN0+RBu6RK/NiTFQ\n8HPNr3jvQMArx8zKl7hlGzI90MrAxYTqcFm3A8VW0zop/Zl9A0hVirVi4OOVJ1jGABljmq85LkX5\nleZmVA76a8NRhpho+1ZMzvPXafAut5WMLqBJiZHoe/uo7fK55afMZz72DThdck9jCpWYunHem50/\nD+u5oV7xG5JaZUGXane8xjq98nvgK1OxlNtvdMhZwOga8E4bGM/MnzZD2RN+07J71taEx9g2MZqf\nARnkl5s5fVI/RCjBQipGsIErpoCR96CwfwqVJqzjN/eQr8gQwwU8qXYUcG2+J4h++EfpHuppQJYr\nyUUF7OabsN8mGVd8YXg+ZLV4L5g+x9KoEzextUxJwfzDt0nhyKE2WGShZNZq3TZKIhnmC4GRBSsV\n/FQ3roATg8wqIMwqsk7KDZFUflV8Eppo2+xN3DnXkGH3W2eSeZF9Rh8d6680FdiYfVK72V83Ln4e\nKq3J+q8E6N7XX7E42bW9kvPds9Mmwm2VSclc7EIrV4uZjyzNyS0JaFNw0n3/pf0H9dAYyVzyEda1\nhY/o5FEsGQh/dF2by4sQn1VB93tuW+8AaID3jdShCY0Et4yO0qE/g39nEKuSXvnhm+KXflUgrBT2\nKrIt2eZ6Y9fs300nEEgrZfLspO+rEVJa6hIKW7rA/I8lkvYI8lUXpzksZnSd91SKdIJTUVV8AkCx\nPM7xZ3RBep+w5YoMOK6TwE0z0VFqVPqKGuLRchvjFX8lW3LYhKcQlIOHsQ1G7bjWZoliFKjVXJl6\nl2P6lVcyiCpG2Eb5HPssJMVt7pcztBp9rtMPh2ZqnAwh8Gq9+71+GkxGgcHZqzLzCJ+4348knY4A\ncJnbjTbcYwXtnHrNGnZlifNFYmw9GIOQUbVs3Ub7ZO8ZrbFKdQAZKXrqybTbeXfxEAIVilRuE1qh\nfp3LOwxFN/LysIPng5YeaMYWk7peAzNF0TrtmLW5Drlkn1FDBYVulgrPJ/RInPKPvcvbBqqFquFA\nL4KP76iR0dLPcl4oPIBvemk9UBQr8glQmWdIz5UaaULck0WlM6A0RqM1VZrU2p/dh84BcNqhiNVf\nacq5NZWVLBcKCMxuMQZfzPVd0TMDR13+frm5X59TvpA+c5xCosjQ+rSmwC34cYQ1FaBte6pBEfWd\ngFnRWi8hJlicd3+YamZHkHI2I9i/iDemhLsBvFd8e3rM6QlzToXjWPSBL8sWq5rgv3aVms1cf5qn\nz3zpzqy9cBrKmrRGNzVMajYCQtSJbCYNicHucoEJhyQmaARHDXYYgcAEtRHdpvIjKTeocl7KhIn4\nvaj0BfoLrnCsie6hTcShPdydvIwRZ3DR+3CQGD7EdkyEtN/+mbUGsuuNV/pXiPt7+5u/lhma1/a4\nbDXS7pCz/xGIPTD5i/0EmoMAUQtWO4VaBfB3/hNg2j3nPPBX87YEDykZlyOEp8VO6kFojRX+jj3f\nPrZXxw/n5ZatROVD6fxbACcOiBeCbPH6+nh06wdJk5TJm9GnvLPA4oPbmJFNlTOi+6efN/AWU4+f\nYKNay8VA/g7NitQYsH0o52EKzkYNC+U9TKDkIZakGQL0h1oji7tq/0OtIcYmgYiNSuttysjmhEw9\nMkhQzJpQdSf0EmEyZ0h9amWi+RfoZvDHwd0Fn5EcYbmaKnyfs37JMGbkgc69MDurpilDtWpQ8Nqt\nHkrZyhjidkufh6gboIH9l8STdqjik/d+8q9uhS8J6VoZ0oxiozynnqcqWFLRAu8NKqsg9YQgf1qQ\ncuuaelrsBqS5E4hu1ou+EkLXhDIKdSDiusmfxDe+0BSIBuSvH69avq/mUz1+4OdBNbO6WTnOg6r3\n805/pDoW2cu0pnrc/PbOb1PMXbLUal60Z3wYTlc8d8LwZRQwiKrpKQAobQmhI9qL1np5QHj19F54\n91wlOSaqCZCBC4dEEL13nuXvq1crCh002JXZfA3eXqS0GX938+NiOgJp7/iv3RgE5RsVHYwXun6S\nAoNNct0e19FKUGgF5tiSQzU/rDBZPXzlq44qSTyr+T0xv8KRxMhtcJ02nvAcNTNgR0QX9bpdkB+L\nxxHeCNQaWAxupYyXLSnf6z0c91+P7FKec8F755h+S0H2/Me0V3kJgPSCNV3Rn0KRpZ4wkAn6C9PP\nEt1hLR9CH0UxwVG5be4JEcbGoiPla3BXmPK3/+t2wNIYBIb4f6QZg7DGCVdUYrNlZ0LS/Nmzwl9l\navNo7Ms1NIFw2uougE7ZagDp50TD0gg6xbh+sIRu+8ZESh6Wo0xRAKthGBWXonoi6K0uR8T+dD1W\nOCv01D1jEPCihS8C3Fv3L7fwp6KomhFVsBoz496SfkZsc49WhyUZzuwXZ4a53jmEipmF1nNqu5VA\ncAOKZnhEzqDiCZ/3cxveHaStZ1B7H2rEiyR5s+59Z7ojfCBlKf9XdT3X/I0mrPaTrN2lS6CrZ6xO\nnRCxyI9UF+Hl2oGZAsGkCWgjyCdmZCjqFogp1QgwZxEhfPBnpbX+ystuX5HgzCCabGHhBVLhjPg5\nIi8VUzyJZVln2kp7gnzZO/4pyIIS0Zlur0ux5ZJ/a4PqEl3O7OjL4rCdcGGZJn2G45w2Ztj4jrJ0\nK1YfoFJpVENcAAmunS7Gq+53cSX2Gwk0dIcFYNiGJW5bxAj+H6L5DSZ6/Cb7+CypHlFqUZNK2dxj\nl272+lAKSfaqhHEtWHraKxJNclyzwFICAVt6ZEjRjYBfbErYXoi32LoEKHyyWkjJPxqx50n6042t\nfGGHJgweZ11inO0vFLQncnW+Cbs0wilFkQXRUX5K0YvqfOALRJUtKQmmY6NqmYqiuDHWNN7QJxzq\naT6iURSiRVJImpcyC/4EDKu/3NewooAo995/V6D2GvJYincFQpRaIQalv7ccHjKjRdYSOF+R9cif\n97BD2EJnXseHWyWcnHKdcTL+AvyiSfACTL8Rod1gIxlFSs57LYTE6ehIVF5IKfYiZhbvw0rXmMZf\nZX1EN4Ld1wRkp48+Ge2JTZhrBXTd+e52N55/fOBAKs+HRyyAYwWClBjXIhUGoRgF7xZf9zruuANY\nKnqdZksv5G5yeB7G//Zyil2ixpIENXBLIkl3jliiWuwBC4Su8fleYf+Nj9TdJ3OwuHH9wJ/3kP/P\n9JFF/MZsMIjyC2rI7cmsOzRPB60X8dPurA7XR1LB1qr589QtV2CMY5k5xs4Zs54BdNyiqmEB+kuM\nIur5BxPj65EvpW/I8WujpEmanfzMPFwosxRxj20lpfM2EWKCbsyHVhHH8nFrUnZld24fofB6EMVr\nl79vtB4UpIM3jN+2SQkEZxPMO9kI2H9d5Apau47AR8FmkRJHPr3EwEkr8Wx3ZbVC7SD7TQL5SX70\nxgypBQ1XCNzIvJCWwSW3radZnhotvJyJGrTWJMEPdLHGI7y2Pn9hWM6iBgOES9QWa5PzJt0ToFKV\nvOGNZhSYaIkJnPZYwVdXftE21A/SEKHRNkjmEc3S7zmzz9XG/Dqh+YyuCNpgFtdW5WQ8BgNbWMqT\nJOBrnXyushMiB7KJSdvKuM8Am+jWpxxQyIg8R8ljHQpXMCMKfY3z2lSjsakg2EnF9XCbYwudwI85\nHMGRhrItXuCAdMJJtWkoLQKDbhVw9IcDUqi2JjOP3LuIHDF+/uii8lNf/NLOeafGreQqbSlIlHe7\nYJY35L/MTkKagcJ2+cYo1Y0bJky53yVoFAD7KayWP+pFgT0QzBLXr/V0jR1Fv64gnJYRHeTVKfPY\nrRu1QB7koWIzJ07W/pEsffYFQq3rfGtDNsmTqj63xu9dX7WIP+5Ws+VPWDmx3eC+14LLDX9AiqB2\nX14DjsyzKwItEh4HOFj+i7vKYnVPjQLddBVILh+cmTaL7s2VOmKvnQBFCbMjXG5CDx9mQ9Stqsix\n7PJ1bPo0MQdrnAJIaZi+IbOQqdq0ApoDSwSNioMSZ6uDrcF6lMdrtB+jJQt4iAehuqa44VzfuqzI\nf/zUyf4/YIje11G9qsCU3lvoFaIAv6/iv9Ts7S4QIRFTH6THhYUh0XoHM6XJknkmbNXtrU7WfDAa\n8lP+6rRGpFjtaooVIJNxhL3Al67E8UomaAkha1RUl8WEzWd8uukFnUMpyxNTSX289u4qZyo8DynR\n/QFuXL8o4dOu2dPas+8pi6mRFsjUIivWUShUFx2XOT2eUQD2ZvIRk6O6GjnbvBEad0Mf/5du/3pZ\nPH+v39AQA55Oh7S1yqdqVBFiTmIrSEQauOWxqIaxP0WfWoB/bx1ilPF4AZ/w2gfYXUeuRNAGJQu7\ntCpIzBI6Mmse9zyFqPUVli4O82Gt3656i5jiCKurgN6qZo7lc+88bzAnb57F0OCGAcQ4ujYsFOB3\n9YqNoiRtllKJfevNltSnZgj5dQs6zh6zu95x6ZkEguOAbVrFbEETHeG7xQZyP/OPxMFitmU8AMXt\nRoWHBzweGOPgT0eUH//W80VPvzaD/QlLSAWvmTbGNa751miwhzsnAz4cg61fZMpfOwz8D7GkAB3L\nyKCAFsWJ9Ch5z2ZJp15sx33fKF61Qii7ds7NmITHuT8tVWtmek25QL1Ivb/B3nvZKYyhgZoSPXoh\n5j8LSBK8pkyHGAFEjdf+P5Z4FWD7hhb6Uj+2KcBZYzBNczOGJ4yebDtKvtdNP6ONMNZiVI8jqibX\n4ARtNCxhToRd2waMr4+DRR8Tuz+OtdFSNc5YMkMLo2owWzhHWonSD0GKbW0FeBqg09x2hdxTLDmQ\njCx8aTZOy59v3Nswn6YA5vKKYcoP3YbVSTEiz0m2N7hKWGq6eVuT+l+SvCdxKyH95MBus5OdsbNd\n4rLRS+ATa00SaKzUYFt/CFOmFMnHzsZ3xcTBDLgfq3cYx5CQv/cDNsePnLKgcLR10tSO60nLE+vs\nu+TJiuGbuya0SdYet37d+JtmwGym8vhN8PR/xtzJyeiXwMFjSNiaib2qDQdoIATpVHD2AezYpqu0\nmVJzuxP/AlXkylAAPrtZkcSBSNgjnbCa+MxtJ+ycXOoRBkrotbUBk2Wxo0uF0Al+/8Tr3MxsdP10\nMDneY6Pw2TEzM6AxgWDl+WCt5vEr4kgLcAeKjI4Qr/ZsA4Wib6FOTI/HmzZdWZvQu9qkQ5EXIwfj\nmlFH0cBGttN1u0LeBHzoyZP88e4mMd+zrFggeI1clSNDYt53EC1ldITrqK3sL5euyF7iRydwL1JA\nfDtwKhjW2hWx+gSjCzYXdjlLpFFUK8xFcc+p/QJatmGI8atlcHHObnrwRyeM/9MD4ULDrHsx1tTf\nHObGv5g8g1IFR1DRv3VhFt6hZs9F4gjL/raTAapiVyBSltZFAyDCsWbtzGaOv4E5DodO7Nb8T+rn\ndc7rObtC8ZoFqAGf/1180vTPWJqBkcfP89N7SNy50k5CPI3Rf8B2ohWcjOLUNiTbJ81AINu0P7Tj\nWlGv4awC27OYSfqK391U79t69H7cXDL5xZAwDCKZnKyCjX1WNXmO38GoxHl8T3+0r6WfTFoieBpu\n9fLDorbJz80cdy5HN57wPwrdXtJ2Nfxptsbg2nSGSt9L/3r6Q++rxU6m2cNi4tTsHLCu9uEUPeEl\nbYsQAcomn9gM7HphMUjLAJkEfh3aRyEbpL2lPCwbo25gmATke+sWDGfQ8Mec3mKAiVsp2v0LZk/X\nwzWwN4DJQHgPHMQ1bBlIlqMvOXXP6PD/RNj8C9PcAanwNmBYIu69i8fHg9cJm5n73ARQacmde2+Y\nLdNzWz27jCrVG2tpyHRoy8Epstw2/L+sZ8ILYsltl6/YJ3inALsfW+6Q/GBsJfj4bi3sNpJshHsw\n6tpul3wSZcWpgQ0WjC3Cz7o3qUX5FEaPeSqdKAF122nrNYIJl4UZK9KPo1YMSESMTCePMB/Spl6Y\n/irqFKucHn7jTcm7C66K1bSfyuE9bb8dpMm0WRRiueR2UIJ3p1q+wludZifxmE56ADbJhcG6hI+Q\n+1OzOJvBj5k60x4sQqPeYzIoInS7gdIoGnHEsRQuLJ2yr21+Ajaff7/3fsnOplvO5YKZZdUqW2ee\ndUfiYBfJTIPRc04Y01JZYc25ByNZqBYyYde0eKasckjVTr9EYu39x1WjMc4vekrEzonFbmNBMiHQ\nCsqG9FfNSajmwARndAgb8Zx7PnZ/8E1kcguO9LU7SZb38VZcPS5t+U2Z+ifkoGunm+PW8ooNNOYp\nPLj1pN7A+yM6t+eDV/VnTXjLhC6PT64Qc2JQJ+d0eVcp4K/fG/A7oMTJ9Ydv68U3CdRkwr8VvJT/\nn/CoilNnAZFBCr0ty+Xm3wy+l5CkyAQc+ZB112KHGaGab5UAmnHl9mkHH/mw8NZ2u79vJqNshD9p\nDQvXQesMPT2sgkncvuWo3O4NcXorJv8Fwe5kAgq/5LpU1Hze1uiYR5E2OM6ygpJt9aWTHEEAWqDR\nnXUQvLPKiDiH4nRxef07trRckQzy+ky+sH95PvbOx2WRztt52UT0RNlXcr43iejttpQ16HT6zV8z\nRg0keSYVxhUHNI5zCLnhPk1c2d6IVxODYZmiBAsr66so/6TroQYY0WgyYXRH0A4PUeG2stP3IBNk\n3uNaTLupi3XLME6p7pc5p7xnsXT5SlMt9QGc0+G6xAl2uTzqo5FTkJVNdPMlU4AtsxkPvmZlTRCI\nAk6h9ta09NFhZjcFY1jMCG0TPQ/71VfsaKFLD6CrwHixNcqfAr7VRmQOvDZuqALsr70JMKgUlvjg\nJe6Gc247XjNHRbMJD1jtYLReqnBOnVEdqyhqaCM+79D+EbuMonj0tChFkdEwfT0NMnI7OmWTuXeQ\nU5P8LFHGNcm4341Xlk+NKxjcYQtkT8hSF+ljD79LHB/c1BC95YtOtB+36W0Tb/VGHMS3YvyhpAVo\nIjMlSB0RNQJgyxs7yfcj94N8wapDIqqYtIRHZ7ggofCilhAnW7MFehZVF4nQc2SKsaszAN/HopMx\nk4hq110yRJ14JCS9d3hbkUgTXTO58ZmMWpdnmxEK31D25YfjpFa5rNNJsfWQunFG3HFavxpb5j3a\nw+A1D+iFz3qh1Z4JDXCSWGhIVebI+kkle26hoxz7dDXVovKlaCh+ojf6maWNbCVq5IhZxHeaqZln\nGsqnOC7+4USzZWvvTJI82k2HfPawYQGVE5N43P8oHaa+oXFeBUOOgWRFlPhpNIDn53xdh6kkWczd\nHolDLPMRurpG6Jy3L9ZOfeNZ55PHCXsyehjkekFiLqJTgEyiCYg2hgq0CDkLrbBBRin6y9K7JTSv\n7V2So0ObOlph/kYNKtAYyeetOwc4jj1lfPtpH85nhpOinwHILCo2IHWpqLoWxUsY/nUH5kk7VRol\ny384dewjc8sIGF7PH9BgDrimVND8PLuoI36frv+BZdHKBCqgFm8gMR9jTyLDi331rmssCB5xPPaO\n3zLvip2TiOXSAKLiZP2fbT2NlYkd/ISZyg+QO3Y/kgn3h+R1jVFORBH/OVC0bVGLlLoBn2bhTZhl\nDMSKXMl24Cjx88RNhH3+nRGxxPK5UOFvFruRKeNN762vkuOLNarht/WALfUhFbBzdMn8vcwcO7zj\nppOX3k2eBfMszbtT3rsYe3JVnhqtLpM/YbRJ94m5N6x6ZGbuhh/VXekdpULvyxALnm4A0FQ5SHNH\nA5DVOWLx3eYDmuhmvNBdnqqiachrLBWPpFQpGRwjdiRAzHLyewQRFxUiUaDu5fESJPJnUrVp1SzG\nuEjHdAvWyrFzHCa9YVc1s/3fpVfRIIkZXxAVQZuUESpg+LGXH6J+eC4LmCfOiRV61sByJ6fe6q7U\nNIvi5tBfyrV4E+0kqAr6yRAKm3SU27wZrpi479cyf33+gD2I0G5KaTZYmYzptTdPNpRp/goEY9Lr\n8RvmlCyHf3aXw27KdhS1zJXVm+IQV6+vVdRnFnb2h0TaWiz6V/SHOUWsDlUhNk0kCZY9BqKqtAbB\nICUbZ8ml3F9vBXV0bvYfnkNa7l0BOKXvMGyGzJWugeoGmji9iGiC33g4X2F8NAtfAj0FNbFXJUrn\nBA8y0IP+QrDS09eaft8VaHhDBBXgS5wVNZ1AMnXzKmTKEp7aJosywAiM0ARobcdUnyXx4NLPJCY2\nsbBFLK4wmDrGDhE/dYZJThOEw78eXD5De34/2xI55yWNXW/mZZkWUC6L6+NOGw8xumxL+BEe4TVB\n+D419LbKWfbn1a8cX4cdTk/LkIoi7wPi8Y6RPu/mumRqvpk4IWzSoRofTN28a3HmCZpZNUWLLwfA\nsDl/VOvqEBk9xpfMx7PqkpVhY3hCBsdflHV+ACTl1DLoC8goigg0zWXlE8Id8fCYEgjSiUiHPvGV\nAQfSV/1jyM92e+rwhn/7l1W31XzChQ4yuSdiEU0Zfn7PyTNvvtI/E6dx7OnMgA7cY0ZseMm8sru1\nyRGVIwLFIXZqVkn6lCflZhZ9rgvmXMjC/7ynSmjwx/J2KrP1//or0ok3ujIkwp0Eg3V/rZ+itugT\nC3HFxevIjUpdEc0B1d4kTmgC5geFaBWKc1sVu04R8zsP6unevq4PuW4y10O9y3Q/HRfMHFHyO8Ds\n1vmRfk1eLRaAOs/XPDZPZbE8GJyDk4gDP8up8kIQtUxb/Gu8brvM7RVv0Y6yGEQ9S9rywfuIhK87\nmXfbJqpqrdxPpqkR/5bQ62j5Wn4Ne/Q5VNCf7dEImHwM5wwy2l8oAQAdyFbXmD0J2EWWZOokqdbm\nhruLjMoGH28JosttxWkrn1j9EbDWpVUBnDXmk7gyo4oBUK46Ws9nXtdWW6CExTyYR3mKvVDCn7g4\ncTNAOTSAJlbhq+1AEMqW/5U6pC5sTGdGT8T2QM1dt9jxbzb2pqT4H6KPO6fTuEnkdMWmXs+yTLO1\nxPyPfy+LzTY2R0fodOINkQqGpRoJ8kn+7OD0rnF1K3js0i+af8zp7K1hs0xqnhKrb2vM1KidVJ7/\nUI6hamP+4KNl50Tn8Lbw0/cvNZbI4vYoGd7w7socIlvXsVI70FpUXbKZ3F4BuOHSmXRwZIJ6NaWt\n61TV1Y4nopsF+UDMbQ1oQs5x+IdHusbyTW/MYT+A5goQbTDuBTR+W/X1ofCbV9mBimfNJZi8d1A+\nzJBJOtDvHMqpjPI1FXg9543hPeU9/ot77U1jrNlsGs0t8rJUfkqm+m7Nnbjgt93gVY1as1/FTfrK\npQ+IaBaSr2Kv5PYImav7+EEtucC+afnKJGDGzuXMQTEHIwJvp9ULRL9DPOgRZ+oUEsEMXWrWZDIS\nTWRDt1yzqbS5QCOwjUYyNshSqmxTeZwaB+1r8uCsSVD1t3nVugj4qo7K7qwtHnHScxm3XE3TegtW\ngX7liXEXADZSQEx0COBYcOFOWxHGtCji1IBCWKCzi+aEyssI1zwmj7vqDCLBbenLspgOriAB5xE+\nDl6Kdtm+NvLPPJOnEyp1yTJPLJc4fDO50NA52QwFpnytW6H51XbYfbZWRZWWusBmlaB+n/iYi63X\nnOEe2bKeuuqA56UaJTTUOz1RK21NwnbQUbdQszFrtuH6aGbA3JZvuS+8ufmQHsZ0R4KEZQ1/jFxJ\nv8njYjxMVNXvaLcOOlDET08GNoaMooGbXGW6GH1Xda7DFlWwNKC4ZnUdYoEAEruIWST0req6RmEG\nj6rHJeehI1thHm6GSB5yquEitlC8Ryw2XzoOVOdryT/uRC8We5g3yG4VqwzIXdLnCP9GE02nSrWV\npbOwG4tenkLm0FihYLaMbvOsVBCcOcqmLjAzVT6Zs/hF4k1CzymQX2d9j9UQc+DZxyystVIFqn6Y\nfsHHUVyJQyVnoNszb8Qn9MtwNt4ieZprwP3ProPwMDWHGjVbZEGfuLeDcBIIIhY/HgvdjLrfSg/r\nobfkkxi/FYM3gj5bbiWdESCVM5cpIuahYa7FevzDqlSbKr2rjREYGYGq7RNWJZ6+cus/QLFh9baH\nxaX9iPp4OBCyYY+tSgmF7j48ysshUBf12gXYJIEdxqAUik6R8RLHGO6dJ3P4r0USqiVjHOJoei6I\nf9inHKm7ZhM2cMk3UO8OQfLA6EcvWLGoqw/EfdNI9x4Yy0uIZ5/xIh6P88BBxjjLRIzqDc/Rb53h\nGG20hpiZU8mabYqBu+NKL6FlNymmez8P8cJXEVV6Xfv0jWqVBQUuD17FTzsWGUjdh2v/UkyPc0FS\np8bI8vpfPt5cgmU+SDi3gQjdklNWgakfVAIklzgCRLfVawCwVbFFi8fNBBAlkzGn8EoMTiLT6u5Z\nijPffwgqyM8HMJMIlFM+Md1K4cSPffJVIvpv1zTQCOd2rNr27g2Al2Ik/mzsh7eGbQsfzP8sUlp7\nsfu/n2RQsWVF7JgOAYiJGYkIjM0avuaLQMlKHDLGMqFWjjBbRrORTpdfyHH3jQKcT6X9DeIIaYUi\nMDZUmxpWDMs25rIgVQo/vBTQ05/2FU0W20pafr2MDajzkrGOVAfeph0eoiqedotyrqWn7a7Xp2mb\nf2LdP2znBFcrqNk2Bbx93/acTap3vvTWyyU8V7cRgv51QM/k1XqMF/3bI7apg73tSdU6Nud64vBl\no0YuOIYMS4dmqLk35zjzrU0O4B7gGLOEVV0nk192MZJqQgfeyUnK6zo/XpEXYtUUpLkNhmO0e9kt\nKYk1K8pYXdF8PdWcDryhFYPjRy0c+L5vYIqtmCSOeATb6Br8/qN/iP3f2c6iTajDUTe78gJz4w1E\n35lxW+ktYRuNlBrtG74OMoFsmfHXUnGDACjZRE9Dree/MdoQqiTgkigmQmN2viAnBEU/QrJcwCn5\nPW+BcSwKfe6T+cn79AdsMNm6Ut0SU3XxVPJeEZhhrwvHqKMPNgybwb+mk87txn+8NKrTpHLU4mCe\nYqiPLRSjjMaT+ix1lM3oNcdTNkkGSS2wMCA5eM4glJR5yY6Dkym3KA/jr+xxhJouZQpTCKjc6ELf\nY1PFwhAeb5v4Skxb2rEALid+xFpzS1tqWLE3+eqE212DzU02lG4CpgOS0UlwZZKrxQx9LYSipLmd\nyEzBSEy4GVGLpoN0GroAb0TExF2TOk6w85TklYspi4hM/n6V4YQJWGO6lhTGRxcTWpqKb9FOP/u1\nupAQZfix21M5/xv54Pdwz5lIhKLcLx7F1QbrZUUiFQDTj1xQgrkhoL2wXEpqSlgX2xQTBsXcGr7B\ncEJRNPGn9+PoC9ldOI/t9QIfQ9XSzlGZXzQ/ZNl5f1/qXV1GgGayhLxfFch7oFgLsB2898jBomrv\n9xv7zZihVHFeJiNLN32MbSSZfwjoNUgQj+M48bsz1fijC6iZa0q1fO0IgisbZ9Gh/ezcxG4f6PPX\ngoCzyzf3GxBQix0FwDx1/ZXowTaj+C7xIQCp/WXvt4DH40rAwqKKljVeCuTxPo6qrEpmsvRUdoCY\n2sm/Npv8+vaiJi5kkRZDUmtFnl1mUgoOueZ0KjNROvzqOUlj5P4sQo9/37vR/XYy64ibJFlUMK+2\nxvEyJqBXnoTL3QJeaHy0ktHAXk0mz5laEORzXsUZlWeEl0Xp/1xNyi5ds95mQO5DRKrcNoxlUvxU\nO+MMICt2HZDeHOMhdFF2Qk39699AnWcLqo6MO63ph3KL6vCaYvY4HJb2MJublZKmTkM1xziP7TBc\noFWSyMEdI4+VEs0GzRatnFgtWtOHquiGeNEZd7ZxRjNgElw+wmvbGghzrgWZX/PWD7ydRgmrC5yN\nHCoZ00krWkcBHS5RCQWijDlqcm9tPwBkHAp3YQ6ZrdvTdOsYLdDWWuMhZhRsq0cVbJc+Lq03Hg7x\nZ5bqLGFwqzHKp3StkSgT+FyZ4LHysejI6rc03mYl8wtFuesfB9/q2qWl7+9Kg4mc6h6dDkXBbFF3\nkatV21PNaHAY7z7Mm46qEM2fSIBYKDB0Iw1yiFphsP364GF+e4nb//VpuaK2a0QrFDLl8J0Z/GOF\nDTJZO7Ly29NBNxnGQFU9dHWhI4xoxay6gxxuWQArVn0uJwKu8thrLWTjRR/oPVt9LRXMj6kDLizM\n31RKe308yQhcv5WMhgjBwayCrjrh+rY46ROumwu81VX7vthLudmpuFVG4mGsqLi+crhsyAFDHE1/\nuMnH3J8gUMytmy/Mg8MB3e2ZLpauiZ9hM7suuuYOffrkkBmdzhfJzTbXjxsGFEtpRykkflVOxu4q\n8wtZu/LDfD13tPNxyWwBLMZ7tXV31m9/+lrDv5ibaHU8LiWJ8DQEQt84HHRzN90HaebFLyf/JMVE\ni5hkb6THI7+R0nWtt5e7In+gm5JeLORx6XqGHiW6Ie9iZeVYEGkeA4XQVayOfpKKk/iNLR6gckPx\nWo7KQjG/QWN2ERctvewC0lAqAwpk+FL37jx1mAWLJWduZPswr3dkV/5Qs2psYpxmQ5vnxLH+LHY9\nxkOL1hfIbjNBQQulcv/oIKyUX2DPIgwofMG6KIIAi4BCyrjSJ/EosKfPa7LW7t0CZnmPep4bBSgK\noDhHUBoWMH2EnzlBcnGfzMwtvMIM1TeccT5xYt1sFsfUfFK51gUvh8R9MlmmNvjOZC/EI3gn0eo/\nhfZT/NOkd21j8CO57vpyMsSRCNVEPytYOwj+Wn61XgAB3omFk0KKt6vlqtT3uGgjEitGt1/wPZ6a\nvHwc7EJShbKFkZH0YmVKqQd/fBZv6YM7MlKLHLs2gZrpKcggEAppePcRFbB9Op+M4KqbXdSHfk+A\na50OnBaC9Q7y2qsD6ksba/VgJCnHTCd9L3tFmu4pOy8Lq2s0E7CnRzlldPbv/JliU/1wcFq51rL4\nZzpSRH9YuJqa0ROd+J8Qplzlk9omGGqGAy+dJZDrO1e3veIBchF93+kzHdEid/QTmbuJ+5pHFIml\nsPIDsb2oZi+u5pvBGWpGy3ZdQcRONgtuDPseygn5WesmITASS8ff/12m7f+ZIaJ9Mg5+zPI7pUXg\nPmv7FHyN2sEGgfaQA6CJcNYA7hsr1mGxq+K5EmS3l7b7eNBjLFyF4x+6VejY+MJfx0Zed0ODReJ9\nq7C9WRqOKDk9eAUP/WeOnCTEzLeb9uow8IgVudDAo8vGBAnPx2X/Bj17b4tUExDcxRcDSyn/PqFd\n3PKc59uPGumFcnjU9Yhf0XndbMkBzzMHoUW9XnV6Q9nt9jrMXf06OkEVCi9hLoZfrRgx0WBwDqKc\nzKIhlF/WR0XrRGgEnUmgBIehvVTRP+rZOpCy69HZCb2fZmhNwU3RkwZOpV3K/4XnkFakXGR1UJ6Z\n0nq15bGQeXnwb3fZLtWdsilds107YerZ6GyeufZhGtxIl4lTz30pDtHBmRmkV3NKntnJZyCntq49\nuEio+RClBXsKcT+P7Z/M/9Qz/owbImoDLFSdiDiuLEV/lennVJB2gQ1USktoOE5q+qngDnC0ub/A\nbraMAev00F/hGe+TjlxvBDJQhKl1RoTZvjSHtFHA19F7bXmi3csNWBN0oaiuhxYeGqaiKsifhwgA\nD1N9QILelVLEZv2mL/6O/jG64Gi7z7EnwfGyvL5UxW4Svq1wi15D7oHklHdg0GvzYlLLoEIej5Gj\nWnBmTLZcVGKnLu+XsW/y5NT+Lv91oaXKSjzRtIYgEM71P5V0GdYC6B2FXulPSwk19krUK3ZLIbVb\nTOqfqaVCu6izLnopC1ZTKQLCTwWud+246Hpbaeok6PZiWpUs86rRl1msZwgNKIlKZscWfn9x1eZa\nW7JoFQp+1gHYcF1F8Aq4lxLz2wED1iwSBWDROtbeMt2ZxVBQ1B50v2rl99vg6e2zPsrbJZfVaIBk\nyTbUMKhfqUfJ4rSZHE8S7uDN/ThbpWHE8NIiWxkNGz0DJMGYoIEEkIG5Uv3OBkolKzm1KKb0Pus3\n7K/Zxs21TMKYCjmQzCRrMKAYOV7zWvTqfIlUoF/f6HWboT/xDT8cixcsNYReTFd1JMOpOEI4oQd7\nwxSMpWg6hnd8k6oEzKS/n5ts/OXXOowqVIXmHHpNgO9HcaYpsb8/lzLBjFkPzCTDCbLb7TGpiKyJ\nIQ6emEOJLk1xJq6HLP6BT/aVDjXNwiMtH1ANFPH2xUd3mO3iuQkMYvXnvAEcfY3IJax5eSZP54UO\nsDSoZPs2hfYkgjFKpC8t1pJZiGlS8BmqLZBvhhI2sui+HY+Idre9XL0la8NJuKH6kZrA3YXXfLSk\ndPSdmr5VSCObddNDXR5KEGxv/1KiMrCpfFf5C2qfaszClBtQIaKrPS9T1iLUuHkhbOS8R6qWW/HA\nnmm+U55ei6NCiRgZQvgLgivspB4areYeoz1KgzLo9R8qmxMLb4/xfNNHNvar3PwDn2L4huG7iXGX\nNTV92tBDYxpOmEqinc7Da+cUU4tNCElpkjqW7qeBNNkj7mpSFSkirDEQtYpYkvyQddXrDhcC9wCp\n5ZPrI7gLtoUKL+Me3VUGFlSifAkNcRdYt3drm56tP5V58ysrAXKOWDjSGRf4iBQGClE9U8x7p5Hp\neAvWvWF4yJngczTlq6vZapEtp61w5PCwYmkJC/ZeQ4JP841QINknGYFfKLMq9w60ONN4zWXSdOtG\nXfIQ1SzAkdBrRrTn+iIpuNaQHWaF8oXcu7feEQWG9SvCH493dhSFWnZW7kt0OJq+RgByO0RyMUwb\nYkmUERIeOpXBx1ixx6uDi2SmUqwWRslD6WeOKT5RE8mInhcezFSkzfBbjav/ww4YPxs5I7+CaUUT\nBuD/V/P5jKpOELDua5bW7CkF/JkeR5PRWzLOmMz8uqgDLp5DYiKpkwuiyscUZJxLZLrveVcAi39y\nJDGOiQBaBmYasjNlgc9tqY96PG2wWl1Dzz0/pcqFiQ2PGQxnV5vwa2NSCt+GtNva1xBIKzi6ET3c\nt8sIiV5hHMMV2sLNC3VKCey+fb8daugt/PUUqXLuk+Ycptw5VPkA5yqqsLZqKTk6FYOpOHRjHZey\ngaPlrxP+FDmJ7i0eOg/fvR+1SZy0ErhgBoL5nixcviyds2TTW2d7AW0K+Oq6OxkOL0U0NkFEEH9+\nV+LlfBcGwlNuZQXcTqyAnVajvEDf6NWmXUmZPCyK6HnvAtbOLV/bwZ1S0PBKwIQTUwqU2383fWtJ\ncP8nKsUUXtIxMQcXXehCorEVeXdkYCStsnvdgkwDDupG2wxmhBC1VOXr8lHSzUZutbbUEAsnjdiA\nN2Cz5VaANGXFnNYwaYOi+zE2DdEMnW2Vbxk7aJku+aLQ9wGpHg7Ec2q19sJe+GcWAlVvlovbwXq3\nrU6vO+tPqXeIvzANnCS05v+VJQat2sLPkgVtG6GxAVaH/zR6cPcFw0l/sEeT37IudCwbb2neeFNl\nUvSmHyt1JGu+0bQ6DQGNihmGdIVNW+50jxaHcdw8vM55qfr7jQ9wCFcvesGj+vM21i3kAUJ5h51Q\nbeWXoqVk3W/P06M1wodyKKZJqlndM/130yJaSBM2kycQrpfL+Os6+KTEUR2nYdPXJnZ+KQ2SfLr0\nxB1BdrJU8QFoVMokqZC+HusrhnQhmkLEwLNs1UuVCuG4px0NS+pUO0Dl0o8xwCEww7DLwZWng9IO\ncusfpcupuVggip6rEw0d6HKhhaVShnZYG32bG49KLlpUwmUNvQikFqdsJmIa4WPbpjI0vUPU6Tf6\noOuuc6Wc87ZRKXT3Sp5WeLZTpt58vtmBFNrtt6h6RHIMHaB3k1eAQ1MtruCycTEu/5DmUI1LIMbk\n4HlfjSCWJ8n8CD9XMck5A6Wwd/hzBFFguPHWutyxPafx2+vl777gMzq7Ez5/dGJx56XKUz1gvGFN\ncebdqT83DPH+jyglzz2atVRick8pYbCcTYMvlxfkiWMpEVUluSNJMrS9E/NM+VqCxd6Yyfmv17Iz\ngXL9Bnvjyx92PvxoPBOCP3DuUnirUQr2CqxSE1qh/EYNnLELmUge7R9vOpEfhutQffMbbcXE2nZq\nufBgn75Xl6Mj2Qcehaa5d6dGA5kL4HV2NfnOxJWj4KXncKJZu/MU18yyg7QyCMXS0+woPw2dMdhE\nXfFeP1zTKlBtui6iXrgQ49XSWnexOPevdMBmtMLRrGXByzH6yKeLNxxBYBw3RJYhc+Rp1udayrCu\nXCYzYcbArMajjU/nItDLcIRgievi+jo6bCUOCajkZVAQu7xNHKzuHJfWFXhwgl915uXEcWEkN7jB\nmWx0q1+8GfGAl6/n5FIRoYROxkqyBzHwKvru/TCok4fN6gsOqBUASXI9sPLsxmruKUFGrmKb+6mL\njaXYuIKNZ7eEbdCnt+VVJo0ORWkjPavGn/6jWtrSkoGq1MBpkOoySiS4KXWnn2zRVLv3eVSUlduD\nKQnuU+9OL6njEFcc7joBx/KkV72lCJd8o0/AI+A4uKLXD8W5gyYd/7xnYA1f4SRurH1TTIO9s4Uq\n3xmhjZxAX4E80PhwhaBBQDqn4XZAKD1D01WARmttcO/uhQcGku8H6Ci83N2Bzrg0X9k9TIKTntrz\nYpCOIguBCu7qtM2UwMfsZWh41MKvngKIXgFyhS+d7nzgggX+cZ0ecK6Op1msayErtP6YnyPTYmp1\ntJ9sikTymk9AZYZ03oYgTP51t/ChaXfY8nYlPZoqkF7/WZKcxVgvfkECgM4LXGv30VYIwaq8A2aK\nE61i8eomgMLmZistiXiUzliXsVHCu3TEebgjNClZ4WSaBs82J2Gxs5QIOw6RTg1uqLgSWL+82a4X\n7CxBn7zC9mtVRw7TUPfrUNb2fDGdIdan8uI4scftd1EVL77JAyM211WYjSDUxmOlgkEscOklbYHE\nAmA+QzGnyZem7iP6uvqYFGucfXTO83SzGEwVit2B74aOUiFepKARK3Hm/PtXXh1J0+izs3PUhV8R\n0ycKABe2vqlQ4xufPQe6eruGAAg5S29qFZqIIkoDbU0s5Mr8K9jjWKthGOBAdcZN7uTHzpZkaE2C\nfyBd77pHW7UF0ZwcN0Ilq9NQdzlUdmd2EE0oRWRCKGLFqxVdX79nVj8i+E/E05qaMddOyta81Tt3\n/Rpu6WYsw11iE7xRlpUfH61Qz2OKDuSjSLL/hdhD6ElIU51yGxqXvDjHpmJ2xizHiMnYiSyYK6vX\n06H4ZnKK9D9hqpGAE3wviDUGFHagRbTaWql8ek6zjJKsMRDs5r7JHkzcHHnU4itWbBDzMSLLl7Tp\ngdWd4yCZankDM1/ZqOKzu7EOc0+Vg3vt3omqxM56leRF+xlYsWmljbG04Nx4GfjWW+5QP109uUl8\n8q4YkeFWc78UGud5ZBZC53hhHECXMfojiu1jE2MHr1jkQBbqTEDNEN1XNmIfr/ENDhQFmRfBLfN2\nycCZOV9W10XUWyGYIkkw5kZwou/u+6RuMiDWq4sdGhrC677D3D43keV8UDj5lAI1p3cFa3udzK2k\nVkqGZcPunsGQrUSyA7clYx4H4HFZ6+yfCLOxHqZIyg3ssg540AomsgCQw33ErWPpSyMJdzsbt/3X\nAxuOf/uJXttMYEg/vsvIR64RK7n430IxcWmyYdSYsuOr4l3HFyQSENU4W2P+7E7y6nZZ5fdWrTfY\nilD33oBoDQMaMVxivH1wRQozitOP0XfyoDNVWj4omPx36D16bl376JOltiffUsrykE++846DLzdT\n/1/z5JTMRahcxyMxaXOTO/i5x2plL0QRmg4iwwVGowXTednuRTbUOojAkbeptK7i/lU3Dj4f167B\nupaw1uOUcMf0qmOnwYlx9y3Aa6BYFdbGLkdwYRytMJiNjbNpDHM6I0EvJ+/mLNdN+msivODYSSQC\ni/Cvb0LiNMTB5pkS0Vwv7m5f0Vh0siHDetx/XnZWmZxEegzcUj6YjZUtGAvHYOOkxUT1dVc5RhAA\n8kvMsLFzBu1pSPCCNbtidzzNe/kZFi/C8DJ0MtqKx0x54Afsky3ss+X+P4+eRRX4i+QvKR/u7QUy\nw6v/izd4z48Rc8LnS0abQsAQ4FuyraN2mtbkCCrIyL/8qxeU/yUPUeQoDZ0YL9KualTbg3H9xWGa\nfQgBWrpAk4pvYROtxFLN8JkQIXk4MKKxww3ovpxIOQ0G2/JQYUk6Uq4OkrcjJWEYoYkZhT5loALQ\n9tMK7fVmRYjZ8jSknn9A3zqZvamMMe8v7U6+TDCSYzbTU4oMR1bGpWZw/nEW5YnELp1aM5A0HV0c\nCviQws5TAhEOHviv+nQDz1IxvBStwTllxRhMKoWBuspN8AwUvp/T7Ssl0CbC/oSq1yGzMyV2QQVe\no68zH7i2WQCGc7ZmcUL31AaXcDpZDQgkHmSd1Wl+c0/lWNOgBH/Hk1OxaLH+b7m6F44z4OzAB0hx\nBKUW3R7XbPRzbIULCHGcHc1+tG5M36MpWJTpUnDsZEeG6WyQHIiOrtPLA/lcSxRzqctHC/XUiSAO\nJ8HBMLM/chxVaCt9NCoom7TrCE1rauTvFMJSCrd4nNLxUbJXjnP2mcDmaewv1LvZ3alAaL++vVzX\nh1Om5BUC1R8dT/IoQ9MlaQcfaT6H+Vi8LF6s98I55nVmD563VuRxKAsCkh+wpnpjj5ZOOeNjn0r+\nUGrFFPvJVWJeM/frt4wbM0ygNzkPIRVllk9JbQvyy151sWMTlNRU9ivMwh1NHbLemlR2A0Q9gS/+\nSEpmWm2LomXHp3yefTMRlFuXBkQ3Il+Jo8lI8ksC3qpP2FJvOvd9hyq96scfXE2NF1U4AL7+nz6b\nDDln5XrI3000o2s1V0URNj3SV+EMiK8fe55DUtxFm99q18juKz3Htj9226ZiUQvMTPQqpLikV6tI\noJ8raMP91y06imgCEqChgybACXu/bGCBdOzSVcu275Gy4DEmxWxJpuXFIm60bGe4KGsIdDpbSbR+\nfPaFT5+remoF7pD2uTIjqvdIJoui6GpX0CRQMYASK2ZR5DCWXZ4LLu2TmpRQYrTSCR0uP6xLGm+C\nL58vK8CI/yFmV2GSVHA6sGQPvGgSm1z+ZJxeSKb7JYCRfo1z+AGu2aAndn/3RXpbAr3YuHXGpcgn\nC0kor5nSx5L8k+MH/q4GsKoQ7SoggCttZISapMK+67HgLhcB5VDR18j61WLUyM3++t61C67/AOkz\n+IJMVM8AQLZUQ/edw1f+eEcn3FH1eOICUyg2bc8ZPtrlVUyW+r8x18p2FTTcIrNkaWK3vk5vvzB3\nxgXQA0ABxQBk5gaycggFy+aDkkLtqFzzjv/y/bQ2Qr4/no9HxhX+fRinrpJEF8NQCCrWCeeZil06\nzmW/iz506fItrRTVhh5dwep05ucnEWW7UWFQxq169YMaIl+XM4+PlBBY3SoS1tC2xvoF2ibanS7o\npO0UNbBabQ4XZ17E0tkkT0cfpWKyaaECSmr4IoBnNZNL5LWXL6fopD2SM91hv6XPoWqmiZVaIpue\n3Say9XyFz64SfqUxnaFuP1VgB+lP5PuI63bqTuk5LRcLfTwZ8ekdAYVV040KUIXsE7J/l9XjHBIK\nlNVUpuf0xS2QjDit7gG1EhM3h2uMY+mwMjEb2aAWb+n8/GYyQB5TSpk/dIODV79aFLghCZlFQNzM\n3Vc/7nWAKCGa+Qlrp2N1X//xVR0kOpIQXz65nr+zf57QaMZImxEh7YiurnLlny3XVKBuwjPasml0\nX+SdbCYrtSC6XjoYpvDQD3jVw9kKnh50Qkvpp+nKss/2ESeDFIwm+yAwo6sf+n/v9d8HRfCwsQUL\nTDYgTUt/7d5YocIPJslKqAfv3rcyLDvkx3nvxkGQ197xw1DIz/1sPlnYyRHPGH2qziUJcH093AS3\n5YqT7IsKkWuBT7I2IB9OjjVvnhwLuZptKCsHlkJO1mLvr8D4qdHOrxrf2oRs1wTV7icCDw6Ti57n\nDld6pk2ZNJxKVguDHOsaLddgcWzUbY/xZH4LW0BFKw0jVZKg69DORN7lrfJQje34oQH6PVZPz5R9\n4r11CDYcNnzlkdfJt42pG0CV5HLVGOgHPzd2Zs+cwy0P/6AC5R343rNUGy2zjwa7/xKtekcmS7Rg\nLAl8Bn5juagcA+ebFnGK/jV+UulfUktxX9WnZbZd66TIbmnnTedHJdrdPbMfL7Xsn6mwhBtMT+i4\nBfN38A1J+WWe3C+XnzMZ2SVB9UgFDYq6a62XEvyw2Xykm/Cr2M4CuxPosYrZFl/J5WfaDp0z3dx7\nBBRX0CP8c5FeNhyPx0Aa4AvhQ7o8aAU48i+t6japZTALHzQDBNz9Lav9Jo+WhSpr+JhJy5SP5KbO\n5DlrY6WZxmZV4eZSwcOk5IjZEFQGcAquPk2eM0nTvaqi4dTL8nNMzgp9xAUx+DUDAkSZBWSNt4WH\n3ltlSuZNUzV4OIspZ6g3JSCWkjBbC906BiEUWQ4uaYMfe5WvQloBVxH+50gpyFTiba7a1z35GMVN\n4Ag0H9rmyXdbBL+nLXNNP+WQQkR02FNowavRCop/YCBpm/2pRTMsitK/yspzQFVNC8scWxhtfGzL\nnqSuvpRGkObG7Nt96nwG3HlpZwpaIxYr3f+T56L1e9UmF0KwylrBzGmV5Oxtm3r+/+TLuyZHHrY5\nveBRHQ3DMc/grtY3ecQD9A3GH4VgD7hHMs+P6ijLSzJsQgseAG2ACfgUrxdu099IuP9jgYFfCXGS\n4itpm0TAS/9FdW55iC5Lu3z7XlZ45SBkWUxQxh/L091ENMGFjM8BamRls12M5VT6jGhApKvbOpAc\n1MhWCVd2xXH94Zz839zTminzBcxRFmcQJrFvBseDcdbt1DXdvD0do6AQcSiNEu46DROMXOo/Fnet\nzFAfQqk2TUo5eXT5D4z0U3W6FuWfq83W2r+RezebBO5fceGozA4FOp7aIxdhWZY8NiKpmReF0eQC\nhqa328S0/eml58im88s+iH7MDRUUWskjkeF+d+anaymnU6qfhJ02TYfw89E6zCf1EN7RIkUy7fpK\njT4jZ8qqL/QoWsIKYV4xD8qwCf5rrQSk1nsjoY7oyan+ZN7BYxEW8uQpHgO/owDOuXOolg6BMxxR\nEqgk5CS0JzsrogIwEUtB2gN9ahsSuyqBlMc1oyxoHRnhRDCvBtS38A6hvoW8ikWogejBwjvo3+ei\n3lkC3xgzjDTKy0b23Z3Ymikav01KMFqBGKYEeSgLnxQlhu/KZ8jDixhdki9dcds3BSG5Lsa2RjDl\nzlu7Mq8aNuMf04ACWGPIjm4o3vuzeLqPpyRjCsjLK0O3RUdT6vSLRtZFdF9kUG3zfrmaLYkgpafi\nh4PiIwUtiF+D195Qru+8rFLYHNHb0sSfDA18UHUaHHI0s2mD5GH3z692KGRjb5MZraKgpgNyiadv\nzbES2J1S+QyYcKS9/F3+JsumPZtUgXbThHkFov0CdC/uoEa9fcdX8o0GsAlctqvHkz1UW36gosDs\nbHTsvharIqpT1HNxyMUlZxka4Yzj/bzI6zSYVCzJhb93eaNzQyfCnveTjw3Y4aNVCldzr3yU/rON\ndiYkIO/2n0EQAuEOcj5yY4QoXRNBvTAbiOSYjvl77yKR22Q13tSviAuvpXAUWar15QLKkQfuYqJs\nDUA60qL4DjemXb2pabsM+ySGk8MTA8tKFRVpSL+Xw6ltgeynZb/eM60neKJNxUmxiteDmMa+ZQDM\nKaKdeg/z2V7381sGcsw5WZYN2vvjTEy5Lp+uDnBOASoMMZ1AXLoqogE1qdeQ0Jdws5gmAxQajPaX\nrkMegjZof8oHOSVahkOC6NA5/OUFBHw4MqaJV88CPW0oYN22iByXOLYEuOgnt3264WfmEqDpJnIC\nTFy9WIUKpGOiRMgKrLiKBQoq9XjHGA4Sqxf/zRIpdRTqxiM3Y2RsI87h3NapRRcQOR/+SUDW8lA1\n3pSIZz+RFWEBMPBo0IHvDUfiHdUZ1U+vy1mVCkheANb9TCwEFwoodL73JIBDgOpp5rrnzKYfJlA2\n46JiZo8qGs6GPGJxTygYnRrU27tHI35XEjCvOMk/YgI9Wx+3QA5IW7AR4UoM/UsRavevV+z3UmuX\nigUIeP1zdnxYAHYuC00PwtkxpuvVxm2ofOWbi/l+M45CwOUQcZAikLdTz2Y5jfUYhKo6T/nZkC3y\nqlHqtQu0OSUs1h3qKayMigzKvHHhfTNsuCZYdqzH+xXvvCshb6oJSNrk0MbV6vZlf41J3IKoVO5h\noyG/ELfdPHJLhQzO+l28wONhyHtPztA8wM9uq1iG3WBw+iX73RW7RaiiXnWqVL5lrlS0CyAUUxry\nNUJPN8jnbQ4uK1ioR7YmGh0+Dfb/XKsNJjlL2feLLfz3WwOpb5YLzZ7WrI8/XTvVENZFbOP/6vdG\n3a0CNnMB6A7O1dHbUWWCPEFlwLpMznFD8oJBa2z/0jw5FMzl/IMfEsK+5u3gl8qGrHHCC5zg0+vk\nE+FMlint8OxthQwNZr/9wVsNmQ8wZ3snYJuAGQOmhkwNM+oYNtc+vKJKgAJtuLTudrAQnPR4QYZO\neIdq9l+lR9fuIh5q05Inq6KUPWIzgOX6S3QQC8h5efHlkRGG3fD5/3RxAVgB+RCaZV4IsULnyP7k\nWF/mSWZ5zc7wu5xoF9Ou5DSsQtCnSynxlwY2DbVBZWWr/vGQ0jux+e/8CPZfUknRPPm9DGtFAocW\ndYZlCeQ/Tnt2AIp2k3lqreNvsWELtO9TbFQg020n7pPEram0sGGvX2wEhMTI0mlKdIGgwbrrHZNS\nZ3ZjIGe8WLGwNksfSZkaTEZkim+1S6Qz80dFPQx/GzOY67KWBIlqX/fGhSudjJmNxil3o8/xUnP3\nIioBvRWJ30QjjDNcHUkaUCdncleiWhlOH7ptTOr9rkZR6LCM25SAZ73r8H36Kv88kjzXvk8UOCc0\np/Ja+p05uoLPlBsOko5ocbqMGloxlU0m4gBCQySr66QTt0qqZmQMUZJpS5Vivf6BVNkVXjR/QLK9\nLHce24dow3H47/pjXSQPS714l2uRsOTEbrlhk6JGXG8G9e6NQh6lRMGKcQPi9DdAUzSjEFCao8Zh\nqUeDfVResGNsfvhl1Era6H4laA0DiizyhdTXvO4oCXVkGvauOcSrRHE+IeTobJcOTXVq2gn7QZSz\nrG4Eev0Nk51Uxb8Ov9ZS0bKtK50SxYex0E2lfljyE+7b6i75zSsxdBco/D93BzpVIoWdEV4JoP1B\nsFaw0lCbeXLO3Erq26KKmiJlaxm4lJYNyLo3jWfR3MpBaLPGmDqXJb566lJbAnqWVQ34f4WMbWQm\nB9Io0UH4A86JKmt4Z3jPqqiR/EnvMH58m+se4LwLNfm7kcqrY7VMOFMD8FAXzn7leGNaSXhWDCyY\n3xiIgvV/xguc+ORGAEzosRGaZERTT4JTZPLaigh2S9hVQD2HtB/f9bzBv5z+Wluby1V8rLRjdwSq\nxTrcePEvHf8dQ+WmrLVahRyUq7r/oJ/wg0KTSfTjh6roqbhpUsx219xJnWuqjLeg5chGKITGHce0\n2jlrokr/RWsd/Ep4jnfN25tHvO3tYfwQlcElgAeIM1Q+BudXjdXG0jQN2XGXazNY132ATyNAVKSh\nbVvIiG6hkX2MvY0yBVqkb2PFVm59XqncdxXLYJqFdFrsPZRzQ5xAYRCoEb45ewS+T3yfsYEgCZ6v\nOHnWiWA7xnTcXpzkzb1cISP/6tm3YcZSHT2qWXp+tCZ3wu5LqPExC67Wii1B/L0mVNnsnsJj+KfA\n2VHLsC/zgQ22cvbdX+WQrjp13iFfZf/kdGhDssHTghl7IrQr7GYMn4IZl8zcVdS0ZQVOwNZKRT8e\nkvlOwVQcI2oqPepwCOIYoDu6BhM2wMWZ5X6p8RfTlSPXZfBlit0RdDwenM3eKmt5/eLV2B8wcvNU\nPtSTbk2os4X+1gy5flvaItoXThpK8ZLVquqza7MkYAbMt4dXDedwFO8yWuS5oDNINXUug/6l80uL\nWCmkNlHQ1A4av1NV+27bE/Ol5LF1v5UhfDCpTt8qQ8Lhjn4jQkvCv9eFcI2Oeu5VmQDCFgArDVvU\nDcrzqy9K0tN0pohbperrmnsu2WV9MSkp5ANADeAdgdHvFM917Wd36Xi9S83BmVRevUlyOcwDV6Ly\nAtGCB7fv+KvWsp8SeVw1MabyZpqUpJ2VUB96LEjNmURAhgjDTZz+aHg79wC5RlACIcxUNUopJ0SC\nu9oU01zMLcykXTbg5CmEFxVpIE4ZKZhRvgxkm+0bYOq6HhurtQep6C+oxSWmYVPj3LjxJbnat9Is\nZgAmAM3ykFylmHGSe5mI+RyZYPZqnuyiDDmzA2w/3sw7ZVtCLyeleiq9SB3nrqUE0y5EXK6pZcEU\nTIws2oYgDxBkT4+JURkwx/+8HDALfgIT+LiAURWQxPszZCaoqADYBQ+9/FxLpyp7gwNHw0rUkpQD\nlGF14z0jHKS9K1SsAy5eFf1Ihrk7U+4VTU0uk8xk4PP955i7a9aArqoW3A8KZo22uKSUHL/n+o8Q\nCbWU8AyxlP73/xJDM4u2Gu3SXp0ZSWM17e5iFVH/A5r5qiuCAvG7J/Q7CZnrI3jLLq9WGclNm55e\nORn/8wwuH6aW+nzdzLLaVI/XL9gpW2qTHZ9NTojdfQGQvJC0njkgxjCGk0gxOXk0roU4MfLAEOwt\n5knJdjMMRNI7/acv7q282B6ERlg8Zlu4rhlQGoB6eMPM5XkhOOiPRtCQ/0IuoeP3f984b0fJB+1Z\n4b/5k4dXvtLwJcci2BcZsspHngVgNgXvjiYAJIQ2wco4/3OPi128WqMC4zToSQVquIFBkr8eW148\nNleuh3qqfWYp5ukWSwsEqbcnCjBSLhvTV4X+ZNbKmCE+9V4UEgPcZ2cZpdie5dJQxPmSWcp4GdAF\nAbhUTEJ8z4H9YrnSXsbr1FwwVS19NtHsY+6qdD0tZOjyM0gg+8SJQPhNujRbp7jclY72fo15m6WZ\ncAgWRvT+1Nn5Y4/9af1xdjfe0Jn2n8HQ1HWGPs+fZDXyUDZCGWHrUqg4t//3p0MHXKjYQ0Iu8hEr\npS+oOyg5mBg0vFZzQHgvXsulDcY087HT+JE61N/D/a3fNPFB3WrxjcH6AI/yktoY18hgTyJbgsVq\nJxYWhkipA6NSpi60iLbMZVCxQWkf8kAsb3CzNM6YFCcUkzgan/yKiVe7vFQdgK4GPjKBX2hqKqlM\nSM96u2XEZhpOtao/5pAayi9unSRG1/C9SQyy1JNIdWJV6+jSRxWRTiXYxfIcFYS/LUpKw7Y5BlwR\nFNPS7kiRkfMnKYF3ou/NLYTaM/jzQnTvxJnJAocOv5dEsuUy4WmRUdCjL175Pt7WSoalQCCMPrDM\nmhDW3hLNEkIieu2rOPAWi58PYcc9it0ZGn+w3VMsnW0TduHas+SkwMgSV8l/0bJrxFDsiRe6Zp3j\nMHopZVaPx+oOriVoY3Tn01X0JQnX4/kIrnMeFCIZqNDRJv1pgIZSObDOw2MHqJVJ49ykUO0BZZQh\nVSAwZyh7Pg37y+pzFXT5dFc0odbcCw4SHOxaJ4MIfX2A06lVdWsDd3rCbgsXMIdt8a5oMGiRDsmI\n+ExRDDiYzaFs/I0mWdAtDY28vRVuE9B1Dd50QkFo19dlwtUZoaqkAiLhlCRvOVTlUtFTwEg0VUHJ\nYHmjmO4vjxfYZsl4Avz8bR4aaGcydl/C1/CF4ImAyxheX4sVVTvFTqkU0EF4aW5i0+zJurDpr+jp\n4i8dr8cA+iA72951MC8n+qj0EgNclUksqF4aPTZzB6AVZ2NSImYBvVYr8WmsTGfn3R+fwxUDdaqx\nVi5xI6hrYpzOIWlJ1qbq5vg1W7E7Qq2YkGFdhEZjv3yCPdJIz4wOmru/uPvrSrFf+9NpiZLHWupo\nKcejnXS6jRYpi0hHbVyFY8pO9i4Nd9tQ7b6e1onT+bE3SVX0oJBWb0+NmVuC5aVxLHICnzttO85Q\n7GR4xhfdZrTSuRJKFXj3dMAoiwxWkYbFCB0HJ+g3kAYPjfsm0SD6UdvL0VxFdtDcpGoHUdPwebs1\nyImBI4zO8uTVbLZuAX9eLhSFa0WAd+YQebwfjO9BPa6P2arCpEmTLOhr961C8vIll1F1DLGsbWle\nEr2/m26cy/hZBOyPRq5lffyJ5Ne7zZ5UTpq30BQJgqck6nytq6JU7tB2UHooB2t6AJ0XZVpww4ob\nWFDzRcMu3D1fh9lMdJjUj2KMs5plewnH2H+o+zNG1+6oxpT3y/1cBLjulgpCGLlRWYg2lKt7NiVG\nbKvZ8+djXtsrZcHuAvMcWBodgSKRYfGhmdGkTJRORE2wuoOKEKjo47gh/uPg9WfZ4PtXm8DulRih\nfJkZDEM7hNdW2cL8iBOEtq1K5cVCWNkZUaPT2IBTSV2Ck6KaeuorOwEq7w7OhX5BcZLCk4T36eO1\nDYufRbC44Z+RDL1u0jhvkKfV5qElvdev4hLOsA2ezAaW3MutsLRDwJh485GeaE6S9TjbhCI1v9uH\nHM1QMeYb6E0iB0z8+jxPjw2aTZW+OHOjFvvhBresFDLGI+AVy9R4y8Ab6GnCSz0ZL9+hTwVy9K07\nr65Z4ufdm7a7bPhZReNVTStVORdqFN1pS8oNczXF6NcEgUTsNCSQ1TGy033I94kiSIxMe/o66AjE\noYAkONm5VY9cKq1IeVIDTV/N9TDDpnn7Mfvy/p9FXOLlwRwupohWrk6eZk7Jvi6x/QpwyFHXyUXx\nq1ETkec1tEU0V8D/WDBaaXBO3ZWTgDOkn32S06BuDjmLObrsqUVSF61QWzhrUQA0Fg5iKItgQvJs\nE8gATioh/jr0Cd4uJWfNHtjq6/QDKsJ+DZC7KoiY90jEejU2GE6Mi78lxrHkz3t7fzrrann4G+7i\nvcuP6QkBAdSBdQpYFxPZ5LlGJlESPAQUK0cYNV0l4XNl53yo4p0eC3D453lqPn930BAcYhraIBop\na0KE7luB+eV9l1duU6C1iqQQd/hczBbwJtWhSDaaWL0aDJpdmo5DIpK+W6zHRgjF4kHqrLEhTVfo\nkQtTsdjhFpxpOfpzN6Yl//rhn+v7Z9a9K9F0tFQOfxB10YvZL1owQICiLCtN7/F5bfc/I8CeiVF0\npHGF9PRAzW/p9BsybJDapD9EbWSXRLe6zZFQbsAkxc/sH/ZZJJZ4db+OLGuQEb8TX92I48v4mNH3\n4DfqX2jdtvjSNsbXvwTJEDRiWANCzVV0gaEh7hcwZVj+JWvaAAZ0imTo0ykhQaY6esRWpOtUSBxx\n+iaQkuSOYIiT2/6mTh38qAootAjsk20KQPsCe9NpkVRwslebWjCl3e96zQOWC/1Ti4oYmYYmE3Mo\nu0pE7coHZMlEvjLuYEcGZn8mapufk7QPaZGaO8or5DWesIQqoUlHhOyLpUrTZuMASeB2hFCMDAx4\nO12cxmiFTOPOdKh0tGev6kYifIEOEHlKob6Q1ubi6XyzJLZ8WTen+CxfMwp726LAFAqI7mOu1lcw\nEK29NPQZSHBXleyOgZbWTn0gcPsqLqaJFbzKKFEvFH6FWaKl4nQCS+96x0BwCKl4UG+iPyEkieaP\n812qmoQlNMekMal26Tvv2k976HRBdTUnIlOpwPCmyVA7KBtP0jXNrXzwC5t5P9Cdfy+UomzKK5sm\nsreX7UsoawxJAJK7xaMD9/vXGenTzsXKYz0CExN40jKQlwPMi3M6t+3wKuLo1o9YxY+L73bfNpWP\nAp1uIaE0ONdH9Y2PCwxtf7AlsldXMCQz91kuhPUS3ymF48MaJ1K9xrkc6CtqWPSXvN5d3472ShzJ\nkhGoAadIO5TAeMftxGmiut4X51kxN9hgylx1YypjxIFku+b9Y6qU3dax8r8x3nfRw6RxXpqijpZB\nRndCIaeVjx6c6kPJZ0fbdCoVou71KNauds8CkOm7Z1jKt2iiKez1wV8AK73otZhcy/bfLTeuYgTk\nTfg/qBfcX4Ar23IwDqVYMfw87VM/15jy0Il1ph/8r0X3psEb1cnJLrAbits3khfXkGBMDZ0lrC8D\nDf6k2bjIv2zgYwhEXuWU1N8iab/p0HnUh1T32/RYlPTJ79fFMQsk4udY4jARsxefP0fVAlsbjfLA\n3glP5U9/jmmUgBNuxMh74yNFlE5QcUADieggUUV3Xt4QXEGwNnI/i/zxdh9bnCJgjg2N/fbr+jpN\nLp5Ozi7A80IIGNITLdjaNoWRHSFo3hD3/JgINejrvVVSFL6xQKwJAe5CoC7rP6jObe+OpKFt1PEK\ngvuuN8i4etRGsJi5TYDuSSEIeA2/SB7qgtRzESeiKBsPJBScaEcyGez6Xl64XsCowyb62g6f5wVQ\n8h2+IArK+pjn1nX+wkYPbr/rB7xJnWVbkTTbrKqlV/rrqqFtPFWbgs3VZ2Xar/gqyv6ZwS6fuj9B\nMm/Q7QKnUPfarqOLNVfS+BFIBdcBf+yhGhbTIjfZf+9mKP3PV4g8S6vYQ/dWx4tEQCPhy69v3PP5\ncJV1vA4Z4RIWmIHQkIuWM/msHmLkKI8EjHfEDy7/g68H4aM/Gg0gHjgl0XniD8VLk7yZvKaGY5va\nXQFqKgJWR3lGcDRdTOLdNH3n4DY6cFfdrq7+zSutz7Zbqnj2YcJQ7NfEDaRDtr5fw/cWIxzhJS+y\nj4zVHvxdJEgi14uvgK/ZaMCxmpMBIFwhBpXwObgEk3b8eCqnpKNvM3hLEbBQW9o3MRqrPoPLcfKC\ncYfYLJBHa9YdzOc3X599s/nVuYffq6GmoEqeY2+Kdd19T/26/Pfx4Q6ASdk0lNoDfevy74aYf91w\nvPcFAHgqIogeVg4TU7+ZFVsIO4RcgZsFL2kdqTWhxha8PdCA19plEQepfcL+QEnMQYWvLAgi91lS\nBBk2xixBkpaqwKU51+OnErXxbDwv6oirm6XJ3VLOvc3+N+CSHVJgaZHZFO/bPKIJ4ztwF6PsZqdV\nF/hLeE+fv+qBwgjKYdsQ6FOkmwr82PPYrVSAPi3/FhdneqHABOMxnbLozt0mfQSsJ0JXTQ6vW+lf\nPb9g6nIUyBlfWWcxEl30UbsLxLUSYh846RHB5y17/EaQ3jcRbNoTpUJkL+W37BpGZw9lIFko/KpB\nbXJRH8EQe2kdCoJHARUzBG8LHmFTTVQ4lXciJKMVm/OYmrF0BcHHz/AkDxirOXsXoe0KATEmEKdc\nUt1C1decSA75gZG7sVNGjftIbNQI3x33D3pL59SkxFNL4TnYslfKeJW0XGWs69jAQE1VEpmmnxFn\naJMu7OxcLr0QNgcuyBlAXfAwGY6cRyP0vysp1Ptl4iX6hf7URfsMhUj5OJIQS3DZ0GYkqJ1oCFXF\nwk3ZfKAq75Hi73yOgReE2X/uSBfREStxjMmUGpCxGPDKE97SCMdobpj86ccqUdoWlRuNn9FnX5V3\nGoFkba2WVi0ta1ki3wfgfk6XvYQukRhi/RDcaI5RaHYLym46gkPY95AUH27yAV694Dqy+M5iBPyI\n3sVoUVMYv6BvvVF2fT3rQnDpLfHJ310CK/imSjIJMpgbyo2sduPxxR3OTVUloPdDiF3D6udoNW58\nod0nHoH81aaV+TPo1NhdH+oILDCyaDeT7REaBxJM+4EHgfTBiJAjbtUC6Dt41RAWaZcYSX2/iLqN\nE2zmmi37sobS6dEQGPhwDfPOHABVKRSUMszlnN0xtEfB8vJgKMIGqH7iItV0k/rwH4HSDMxzA+8v\nt8wrAdK/ZgHPZNQZ9ms2JlJhFX5K35EHoGdEMPUpmnCYadipmd2T6wJqSmy5skwuISsKVTbRzSml\noigs6OnLExWei+dFR56s4umPkjir3U27oab/aiul4HFgJx0TfgSSreM+0wgfAVTMij2sc4bUuuJZ\nQVxA1GBEl8CRX4SFtXG4Q3USnt4gJ7LD4NvigCnl060BC4tjq90vaOskpgW0ivk57AP+9MLR8NjA\n0rIq1q/u3rrYZWyAByOiQZsvu3x9dOQ901ygmlc93m4i6sCiQozEPoEXG86y/M/3p5wtyp5BPpvH\ndWxYmv8VbROZPaTCmftkGVED3fKuqpXadjO3/7OztaQ1eipvsNtHvE1sGCfUDx5bCd8wspOC27AL\nBRDvfT9dE9XMukgG4nKT0+Zgs9woyhkHJDDMVQvwYRjabeNCFM5ccJjQpHdVrAps9AyTR5XEsk6f\n6S9IK7bhdXLKen4DxTpQ7CvbmMl3yNtg5+NGUMSHJpy6toRydENGnELRSQ/7AoOo/Xq0fYg8pdUG\naUzhIUOBPN+3+196DvN0Mpsyr7q5t8k5NB0tuBDBCUG+ltjxKP3tYCo3+AxRWZ5GONdPRVVx7R5W\nLA/e86KjvXnh3ZjgXFvQeaOHYIvIg8JooXmRoMb0wwpNnaoYoPM7I9jDRVR2Tb7Lzc/11uN0pobE\nEefpvEiuJGT1fQxbINBPuKUv5TgOAkyqANKEiEHndq2MLi2lL6GYcZjSGbNR8mqAcLG6IGu6736Y\nY4h7ZKHiOz6Xt6411pRYuhhdXxbDCemDA+VVJfEvbnZ2IZrG3qcMe3GemfNHjujNrWl+lxIohXbl\nXhVAl/uxdxq9JvSjEjUFQsxffRrQTyt/ek3sUNN3+UagRZlEz2jQLqIKxkU+wFEKUCyXWNeRXeEj\nGS96eczjfsw+MCKlvZy/8oo0L9bvaSCaZSLhwEN9sB597lcriSjMDAdER9220JRFJWCCt5NGo3Ne\nrqFKbTvX3bV0h7bCHcedqa73GOtBIVcdhPT10rsPPXoRHAwkdilB78iNbzeM9olbP77IO9QwzeLW\np/dTvczz0zwP/gnSwa1v8yJSYFbKf10x0yozNq7dq5xk28jP4grpIUR6rLF+c5GmuG+ktUD46uJP\nzSZVNOK1iYspDBgEwkbZ/sjBQTAjTQoxHEiNWTqosX14NPxERbR/drMoKPFbpB/1rme39D3OwOxY\nGlkfi0iQ8ZyyaG1zQ/SqF4U5SV3NoVDEx8UZnf1lKFivghtTgPBzrGBH2cMxdUuDescgp/cQw40l\n3vccRvGplhkQQYVU3AvaUDVm0O0Fylm/B1HN6SP0/+tSR1qgUL+VkIDW6I0RhZUmPkOt34pN52YV\n8Nfmekmdnn3V/9Dt64CRFR7g0Ol3VkCjW3/BnUenCfcvwdHoxNpB0KslpmWdeTHLCz+3KgCYFKi6\nrL9S6KHL7QjLh3F5WCzNe3N9MQnhQPbxHkTSKByHDbeQuJLqx/gg2WaVRw9x71/rf3Cxk8iNSWMM\nUo/OKWVqd1HcdWyWQb7QaRaXDWb8tXv4ENGeUZfHv3v7bvR+CqH4aR9XScWiHhZarsw6aUVkCGxr\ndn3flJErlqH5b2VPgsQJWOsjlicExGvUbIdVCnPcpWuhhMg2gWgzHlfERpRlxvrbDJc2AXAMw03g\nM1tbE6Sv0z1zK2TWJXNGJbJpCFAm7GDJYLtnRTSTFAH9CUKeqa7RqShCqQzvkdEJtVYwB4iaH8xO\n2+xwv1XRn483QgOYp695QjlMkBNGJOHNCGjwHZLA3V3nisQschXigOkvZKqgJA6njLjMfcPrSUIt\nYtrrga1hAev/sZxyrh5ilOCZqkzd/wjz3gbS5/dtmYhr147VFKGeigW0ZgZTKOcm/VEkjOClqrNW\n4Y8q703VCNvwc2cMsUHrCppRVhjOwO2MAalIxzkgvPpuzPDSs8hkM4Ip70mSudssr73rQFpdNnPR\nUIMXqLIvxMbSwdj80QpuNerDRiBIMsk307BdDW4cjBcIvKdXvGJhEGK16WZGCAw+OG2RtzRMm4gM\nguXOoTkpUWFu3wHoURgn8LFagn+GgSLcQT670dn3ar56ky5p+9kORfBs0CEY0UUjCTaXoC9Uw5iC\ntJshHUPcKlkw1+pteyldDGaLwN+2GTsqruDkY9fhFaBgnl5IGDsbkks06SnWlVn6StcU89G/Po/4\nnj8AFPYLm8ZUnnpl2xfBsBkZazv6ADW6xRkecHi4MVO4nWATpR8WeTopSeJBAJWdTlWY1C3tqPxE\n+cjXmfBKZuuDC3zVru3lw6L16O3795Wd4YW3XlckSlWxhf2G6d/49tM4oyjsaM5hJ9ZEKCJkfMC7\nuuxlu3qAxW1GpyVoSHTr4vS01RT/7gHRtRLaS5fg3GaQfGgjjcForhSJ01br+vvsNQNylOUeiR/M\nbmSwLbP91X54qxjaajv3cprJesUxdjleWHICihh9tUgMsX2CkhtgV8r1R3O8E3xLn5b1ys4hcb3p\nnYW9mPhPyNCVgNxQXKn0pVcPXhQHp0S5nAV4NWUFiWVXSy9xi7CTzicYxJbjeqmM+sqF6HKxcTaJ\nXEWe+3hrLaIFFRzlXmC7atgGuJveEQzG/GRbsc7qE87qPzjJsRM+sqhtsJbd7d/gElwySoVmDQhU\nl9ofXyj0skrfQSL7NtUYVuNn0eNdUEVkfmLAxqo8B1UMvTlz7TuN1wMcEoXkSk0kt+X4OjOtXRDq\nTr1BbeVAwPWA41b7tV1a5RHQbzDgeFs1clTZLw+N5mO+GexVN6a6hImw+1WXITE6uWfGpcOnk7Vd\nCjtk6CrtcCmHK6DfpHXTpI9cg2t0Q24z5X/n7pQ2CLU7wdwBefDCygMzf+20sV/ELxY+n52ROCng\n5eh3x92Rylm7r3bRFLWsUIHDL6KKJos567Cmfb2R8903HE/XqIHiFU/zI6C4q+UsWpJNIv3T/wMa\n5Rk9AL9hCMBR1n8+npYBj2J/Z4xEqFRnRpcVjlOZFFX/gvZIlih6s/zC6Gqaz7t5bQpBCPoLF5RY\nWovKl+kfmxPoHvFYH2HuptjedAw643h4LkndLJHRfNuGDEgROVwmpuYUMDBmyBCisy3fo71sFA1L\ndH3d+z0GtRuLUXVgnpA2eN5yntlmr2OFfIVGNRrsMyEZEeChqPTYDHSDdsf0jCCt0ls+LgdzUzRF\nP8qWE8X/oXJ2uXtEdCrUC4G1bfQ0It6Y6iHdQ6iGBLY/DwdS/bp9281m2AQgqQS4P/YRvuMQOT36\nY80AHPYajf+EC4Qi75hkpX8gkUsngccplVC113SXRltTMcDNJWvWjQ9oI3lV4zQAxTEkbH4NzDpL\ngt15eail3hnxo/o1MozDOM+PaChaTHSDeoJMngj8b23xUwa5wsEFi1BBKimgBRz9WR91lb46e904\n/hwv24BJKgi9E7XhzK4y/3CzmJxbO7zPxgp7JDDl1dZA490IgCp3FSxbaSiA5y1zxPJ1QUB0njwe\nADthZPGKJrlhuPZD7gmxZeSwyPfZbBjcfrd5wXb7SY6q7M51368h9MPGcwF4SK12ks+uvnv66OE0\nEX3YcbwL1mYlzL6h2D66LWfTq5V+PdHB2+aWivqihJja3SDu6E1e1xsi16fQob5FB5/rpQbn6ZsQ\nzexoaNgx6x6rZruCW77Vlg5VAX/gaOQEw7Un8UJKazkVFelRHbc4RCuIBIj7+ZpYZpaXq61DfLoz\ndGguPvPcYARafI67EI2uWpBK7KAhwDivjBP1ZPRFJvXAVpqcb9WWsijewRcWHQd75gxxj0A5ReeS\njrDgsWTVcnZB4gg240Oi1HtSHOaUc95AMxEg1jzRZSM1h8hHKRrdOGTEf4Ax9pGXqKMfOW+wrNM9\nJnaJKiIqFHIHuIssyr24DXUk1ezXNzykdbYGPKTWmdBO8gzNxog+J3lOz/9zhTlLDI9r/eg/QJM3\nMtMTtJ5EG4dF8YOX5SI0DvVjQJC2h9cdYy7RksHtZk6V5JHOVANgLJq1Srwinx+0ye3ZgiqMDtI3\nrUhl7t9v0YkDljymU03adXBGA4vxLVf5RGHIMxqw/iBopB+v2zejIPfRHen3dvZm0WCHIMKaG1bg\nV+ez2lr8MejbDnb4A3m7vB2lnkEKEhjQItXWosmZVCPz3dNN/mFPSfLbxBvCKxHlr/QS2TURS3vA\np3vZeWfF5R/rk3M4NX+bdGVTEZOolHvBROe9FbuWjKhjGwQgKBQn2AAPuxEXnWqCI9DnFzcwTLnn\nvqMKKmHQ2hyYfZO8ycumNP5znlHNcTrHr41amYh2euxBA08jlHKeyad6TRiSmqEtYP4QYD4hkDGT\ntdRwuoBV5bfyWixvZW4soowepV0SCZyHXmiar7cVw32UHOKnNww5+g5Uz5AbP7nfygMVM2zAswjD\nG/KRDInC5gx+8C/C+H4w0vFVH3q//bzv2VkBBMN8NsCxo+/9Y1uX3RGdLNnkR7Of2u7+z1GCJXox\nszv6OWNNm7bMt/H1RrNv5FYLsOCfggOHMJeD2IEVW6L56nt5CrvRPNLpHo24jyGKmpJWGwhQPg/5\nCYHsu22E1RYkxxytnRguyIL9LrerkeaaKutZ2nuDBaO7c/eR5Ow6iUxGnV2vO+dsO2y+evD/eJOM\nxKUBuEXMJmdkBHye6brGSueQbwAj8kirAXgZ4vIIyENB1cF5AimTPnn0Vm0bwgmjspBAtaNHzb7a\n/Gd4eDzl3HcY+w+w2c02vjaXnzf1fWif2pFC8SNKsaj2Zg4Jr0SAqu7dt+1LywtEmj0L8AvRsuoR\nX+7puu+h95LZlgmhq3jg8ggy9qg2B2mPHVxkSnjfd0oFFV3xbTnMeUojpup/0Y5lDHN/1tflPUnF\nVheRy8d3SixjeoLLb7zjNRPe2C2rIE1ZZ2yU51I9bRtnM+x3ci0jgEscHLzLDcJXsSd5TKblgomr\nEWud1gK5biNvA9N1+IvV94ef066F/Vo1iK8rxDTd6E73c6xMZi7r8d1j1JyoBIHI3Li8xeFNWuQm\nrBiFOL+eBgyISGmc5Wz/YcAy6m3R77E1mfrxEXL9ykQw4mSQ40k9a3Bmzy8InIBB3Rjdr9l+SKOD\nI7eBvRyPNaF/46hwb1LJryesmSTAVxgBKsK9tIbLxKiJl+ubbCfyLfrntRuRSFhl/Kd2XQrLXu/f\nxkv3DEgys7cO8o+mMtWSnHkIHvOrqGEY04pPBynbErb8QmiUsbbuH/BvQzWzHg56MVS5WfnrGUxu\nEe6w8PhdUull9xJwxMKbbadq4ms8E7CK0pvjJcT+bwWvAaqxg0E8MxEzHC5kUKOZn5XltT/5FumF\nMsu4d2jCi4GvT3IOlmh6Z5izdJXzjhhuAA1tu8Bfx2x13rByFCOHhNiv0DLIwdXtil5Bu1qNs10F\nnlMnz7D7YToxFegv3ZW59lGMnfJzweQ33B+cL0Akdkt6iKN8nqMJtO/5vqh2V6FvFrXAEFYyDvbG\nzDntLI7yo3acXVqpdgLy0uG3bB5V6wc0vhEJ5pzXH1b//XnQN2iQI34WaECL879xfSSjYd8yFUze\n6JJvpx6gPwypx7qJFmIlzCjugxTw1akrRvNM8zW/V98JmHdnFLHLBU1l+2CwHMl5BmYeMFNTo6SJ\nqd5NM3WDiKgRw9RHAo+ElfTctpsBrQpksSMgD+vGGrZ8QU05e/2gZ/gOnRQ5NL6m0OmGIYHPLaV+\nU5rD8WZJQ54E0TU/gwdW3mZ9UcBqNpZpRX84mE7pSgVLbR5gykyTV/zHSbKPnXdHZKAHgFXcuhrI\ndzAcZ9gMHFOCPXLusy2xM5YTTuf/eC8/TiTr8foM2Gjxa+p7SjHyggphs2Vp3htnGAX1QMBd/+kZ\n2dV9O4/l1k2Vmnk+9/eraWOdK4XGAasuMjSAwvY1sJ8ubEdHVmZYlxZjMLl4S9RtTv9HTqkyXysT\njpO/F+BGtdHmsUUYE0ZzQj51IFPWIozcbkbPPuq7oeCmplZCQq6L4jkJdBehre/kPKRTKz9VgtSV\nSIl5rkjQvdTq5mlZMvru8KjID52jNUEcb/hpK0RdzSr5YRl0aaHeCF1zU0GpA7gKZfneVhdESmMo\n+CiGrqHyOHMxwlPb0U+mowoPqpbr6i3G2Qboq1Jjw61ozjgmItpmR9l4S7qUosnHuk6vz5olxMTC\n8HbaMCeF+kJoKHLizNleUdIMKCs4McW0E9aWLuT1QOurTQxBpSkpHDv3WyjEAY6wDndnD4coAlBD\nQI0qg6BNPd9ohuGzApx5dr7AvpgASrSGbu3suiWn8kglb47G9p9e8K17pHrN+Nkj8jwig/wJJE9A\nJD1gPQw3hcNlIGIBDPrvYQDHag1vIzyJQH4D6gpEVmt/rL2u6uRxx5GtRr9nuL2a2w2cYnwrRYCh\nAadR77uR0wXCCf7BLQgEU9Ni5P/4cY65kve1+P9DRQJaii9ejVuS2+g7LbocRPj3Y2zc6rTlJJN4\n/OiE7rIdwwt7BMLDQHUVVsXAXJtRDMF89KqeQHnFhS9xV59H+SJo0eQpGipPtLB7BbPJ/y/TGnnb\nFo+LiLEk/A3AdIIMAkILK5WoYPrHkjkeJ73GU939cx2dbU55ZCx8/kylru9oqjlrglVflGcL1KCL\nzwviD64s0DKHLJHdJAxBBN473Nla2L8WcbDL1UG+VzvEPG80u6d++ax8od727WSL8ISnruwptTll\n81H29YEZR0hNwnMsnhGSZERu+K9Y9L5EZppyOApQHxQNkg4RncnA7Cpwp/TvCvFm8GvwmGhz251L\nFyO0+4Plurc5ZLnGIrLH69si8Y6NnOLj+xzKtnKXA8DmvYkcUmZAN7hx4IRA8D7g1MgHJgZLzWhu\nxL1uXzJ5ojawYVnwnkfWWGt6LEoyhqZzPhLwhKG89gPpsnhAY2jpJZVkaHNSES722X5Ty5cLFRJO\n36ENXiLbsTaUcIPcrv/AYGE4NMaGJF2MbIyAP58BJOYnK3QqxUdostdgSG2goVGLVQgGE3ofWdHE\nZmh0dBS0t1xglOJa+FEDf70QBqs1OEvhhMhgOH/qw4i5x9M/JW3psQNv7e2reIczCaaoXj/au+Rr\nyQN/x+zYpnr/hfSfjrsW1LJ+LdqTAaftNQ/NQXJl360ieYDZ8UHy7vQT76oRgT4qhzbh3TRchQ1y\nuvn+EFK4qI02kJksKXrtNW2o5WKM3cjy2y4ApF8I1bKA+NUpexL6U+QYZwXedoHNJhVMuB9PiNVW\n1VMt+0vs+uYGW+bTNXyWaMfw6WPOhiC7YC2oer3mYoam/edo6iCkyI57HHGBOJYaamRKrNYYRblq\nyD75VDrrSeXSA+oPEQDsIeWI0vdVcKZVr+BYOHjAB5RO1InFNyLn9FKspHdzdKQC6bRobjjpQX/9\nGhvMmW8t5BYVcphvM6b8ofo5Ybbj/ynYtwUgN1+iU+NOV0+50+M1ufbEMrnld4WNekY747wpGbUI\nxDgKSHYhmK/NVCVh0Dsfo5nE80jNPt9Te24L4yHOnuZSzItG8GnvI4Y60Fx+VL685r9bcXChzU7w\nEomShk6ruVhe/Se51lFLstM+/6/lGbNyNvYQtdReqcqezYcHClZDaL3seVMvWbwpVyXtZR2TNlKs\nNioNkEcIDUKlT259fsCOL4iU0qb47/kSYrNHAXV1oecg9IN0iZK63NBykvNQ5Bg45QAuuu3lzE8Y\nLzomJ0MoLHraud9CFL5t4UUuSIdKS/Xp7ohEvy6yiVm1Y1j1DtWdEpKlozwtaMWUecMvDPNnt10x\nipn9yd87v4ncJeeDn6k3Lc/Mzlalo3NP1ntFAiGORZonUZMIqkS8B+ZuNskYKEjQVaWLsTG0NWJX\ndBXchjcufPBpuB4lCDv58l6R9c+qZallbm2TgCP/rYqxMHcH9gyZsVvijbPjBjLoWd9kUiZG+cwN\nXvelEU27/ybJpVp0CqKugXqlfhP/0emiF1/TfJ1BKv9SrQ7/Szte4R/vGdnorSkadgCyM+khRvo7\nvePOHbwI6OGyHnr8rqCr1JBy5rqEilY3JlzNN8mMWil+TzoCgc7JAKtVk/wlIYyM4t4lv+nUX6lR\nZjUqPoZ437knlatvtbgaqr3ZfJSxlz0agfTUeALLvOoGByxZLxORiU51Rl2BEuTUTggnZgtMcmDe\nsUheGDELLaL+89R4n74BDLpxEezXH+5IRxsBT4u7HdmYJ1TbF7SUe4pdg8IoNDW2UjyjjI7JumQU\ni+V93AKsQNdIv3BIcEfXgWsaud9YgC9howX/lEGGwEHnpq38VR2nrpCCrT0qI7xVv0LW2U1nl/kR\nYTeWvx6v8KO66kzjTUFBkqMQr5srlweBEzUQ9jFm97+woZ58/NlW7Gh5iJzwTlb4GZXIm3JuC10x\nW7d9ue5yszyyQRm7iayvlcdRUsi+5HfEjYtmWKBtJ0ybjo0IZMALX/leod/P438BAj9HoGdT6jH2\nSeu4I/sY7+JNPDoYariBWLDiA/T7dz8Hloe9dbyW6UNqQxhQwm0HSZkiOwmVClFcmJK2P9pgGc4R\ni9/mGwnAsYi8N+G1+m29nCimRQWZMhdvZ+pufwMQwFv+FjpJCARiUwalWsgGvmv44a5m/m/5z56g\nSO58xsDSUBnbpNIdRXPmv6keAS0ki100HRwrYoZcA3EITE1zpXsc0uMMzE+QH29HeIud3z9tyYds\nz+F8RSmITbAiXuK9bCRenqKhvwaRoWagtSeYD3TPF/SYmmmVeleZPwLvKPSFuRiIqSy85KeR3Fpk\nmGPRWVtTHdAY7HQdIYLgDzQEbXJnumfvFVX7z2v0WQqEODZqSYV3K82R+d2XtpqzJuEueTz44B/H\nEtps80hbqSsmgIlBow1J3FucGRJeo5dGbP/ukqKzHC/mMDHY2ytfW8zXmUaU1Piy9stBx5IXoOyd\n0bKbZJWZNewz+j7dVKXSJNLVLf8E1RufBVsQF+RJ63qK7KioVAWC4TDXj6TujXCItH70M33TDDDE\nBMVguJv4lcAQ/1thR3hhl8+visWQWFzIChPC4lNFGVsd0aes72Z7GmcYuxnx1abwDIfDbxM0ZNxj\n7SXAWNlUmPqCdD9LzaGOnJC1HzOpLjMi/1OcQnoEIWZtrdhGWgT5VIUHznxBo/3mGFfvwp3qT0Kk\nMksUEtnj1kT/nCgrK3KJCk//P2FRN988InSoACPjUSKnHzJo4s4rIKsXI2ztyTffCgh39hPqM+HQ\nGHzHsTRxHzAybx3EZvQqz8aq5Js7JwEU8Q/yFh7hP43lYu1YwfdZQIc2YKD1DnICjvyISKuNNZLf\n3OKMDkkF5mrYxOCQlGMt0fZMSnus+vF6KArkjq89gw76Xe2WD/8DXN4/lYZh21LwzVSyGugsNsIH\n/WL9HsrBiJk50tNvQINeBBHS5xAQLRv7ZEESf+XJhzed/OnoXEwHrtnJDbG4rWXv32hUdHEyWDC7\nQ7X0iOBCOgwLB+ZmVjfFdaSn4dEsdiPiiyf+w7LHoOsD4jKD4exYhgOBXdzj9Gb6z9tDI7bSOoZ5\nj/OYw5yN5nOSs+QLYM7/sawTQFFqdgRJxl3A39EvmIR5JkfQWf7knE8U0fgRvqvAWZHTqBSaNP3i\nZ1nZSjpZIQuWvNTsOOwj+zETyGSGbGtpe0ObNlE3IkFqEC/iAJ8BVfEoTlaygq6tYLolNpX/9rB6\nqJphoKq5GddFAyBcyiM2IEajQZvw7wauM4TTyRTyAkXdtq/52Kc5C2cLGAbeh97j0ox5qyEJOGQl\nheZoKFTlVKyCZMPSsznWGbgkh7aDmnZfdHmlG5iC29iLaeQf+Q3gbJtsFeqYnyAHKfVZLpwRTL7Y\n8D6kT369qJlwvXz4P+c3WqvUIWrk5yspStL7odX1gRMo9FE4zC21JVO//sFYotut1rfPA0YBhSpm\nvZuFfLdRzmcw9Jdao7EyY8mDOB+DFZrAIrJjhAVfzGF22C27NZqhnphJBCRuvvTgYaGKT/fbopV5\n7pyMQC+Gxfo9zAfe+i2XHNcy7JqVcHGZhDMcmQQVyMnjWOGzC4GjFgIHbIg8iZ1Izs7AtoQDN2KM\nHHKV+NjQiPFzYhI/57rYRybd0tyQa8Z9q1Yr3GYT0/8V8fvQCsVK/bN/Qhsk9Z2Se0WMMdx4fTaz\nzSJ5pf57qprDYSDATQu6XEqtCAlOGmzy7lZuwrZqb1PxkZ/ueKRO4ddVM9cDHNowB7etB9bJKMiT\nB9LxZg4Gd85WdkArdxrnd9eS2SBOfOYLvRikyKrtwIFNMmbJZhS+9ylwq2hpBR8s58ykSaRkeuBN\nkZmsk3Q9XJ183BEjlk6hVPbj6v/OQamMJGahfpumtK7oQ9NSvEF09EhK2GwOQJTg5Qq4PQqpK33Z\nD21N3mEL8zLNxFpr6zy5JmrfAWngoDX/zad3fx0bK19RtIRIqUWftjmj/cReGwVtcKSSHKvi1yWM\nDdg22/UogI+L1dU73IKs38EvSp5L02fod3Uwywdnx121+uVLHvqFlTrv87W8VLRtOFQ+5dlE28oK\nYE1Pfx4BHvlLWMszTyt7MSL33ozcuedqmkH8pjgCNq7igg6zsQNZXgEISARsHyTHBTF5dY2dEkXj\n/BPZOKu0KZuCQ4CjBLV0O38TlKIPFyQkt/jFJjN5GqhfzXUIJbHMQyHh2VTGbP/SO/7uP2hV0iaz\nHX3AZXjj/szqpwEYa/Py0L43nM8p2HkMBQ/fqbaKKzbVNKEg3mqlBRhbmw4NfRGyAoTuKI5udyyo\nhQTN9yfFjGc/gSJUOTn1waRMtshH6GIKp5UMxJcK6C+AupbddePf5Dah0u5JS5TD06HzYoMjFz1H\nhlSPWrOR7fOBNUK+f14xfVTYbwYBU5z/RoXu3WOOwDqK7ZHXufpRaLWuW84E6b7C+9W1LtiMwaPO\nPaFBXfNtmFRznjmf7fEBstPbf32g/UlRyokyWs/tS/OHCyzok5onma2hjh2JuoW2wu5hpBLXTYP+\n2jYKeYgV2uET5HwqZ5VtQ0lEhhIovpLXLA1GRljkBAvyKiCFr/KQmTUD+pDvzLWg5El2LFrxQLSM\npZ/VDB6ZMQjibfeD1tOSiQ3htbPhacdjSGBkYIXf+YJsYJxdl/vjTDpfjq98Ar+/jdCFdeUroTiE\nuKx1W/IwTIf+mORpXxMs1UuXMltBCLE38WUccG8kRT6vtW7PFL6uUMrYR/bHhd7zcmBu5T3CRghX\nwuHSB2i5M871nyDO5GbpDpRfBdatGPmVRGE9TCUVHGHvDIvbT2ywkr7tUGlgLOxqIuC03290GLD5\n5NdT8O+nHUvJF0ONFJICT+mklm0ZxWajRCfoktwimCUd0S4LEayWqFoGKSS+rR13oxUlcJu0octH\nkP9TUchvnh2rvcHjcr/+Cr7uQa4fB2In44nl00HgMDTjCeb+b0IDdocLsk/xmjT/6jUymnNXNXPU\ntZyL8rGrJcKWjVVKbZCb7P0KCDa053E0qUm7c7VaSFJOBedLr4wAFcigVB1Xn7XlueZ0lPk2bER4\nn1Ivyv4j3q88HaQlJ5Ybw0wpgp3xqlnucVMQjtlcC8596Ck0LljZtme5AMw+KuE7coKbmF8KnUpR\ncu7RefAP+B8MiSWLioO/xLSVFWhmO63ZVfiQeqjeoosrfO77sisURcV2inuRonzQ6rjUxfllIjT5\nUVB8wnoQtPXWpmPSnZwsiMjCzcYPYzox5xFXjY3/eWlrwKVAKb4fpgbfFX6uAkqLMaRsUeQQRxOj\ntUXPy+3w08I/LpGiuSoXGKsqOdqdnSFw+BNmrpUIpYOJLweEy2W3z3+65FtK0rTRAOWzoJltDJp4\nEv6fIjlI9uSQowRqKXgD3XOsbIBTEu/NSnM6UlryG7uZ4aA8hivO+ODKrcjrnnGkDARCgGxQrxMt\nvHXeQJTBF6Pbqm3qEOeypaydGJ6gsban0bRJrG8H/Trew7uvBdp2pJ6Goyv9j9iW2olRCHxj8xAQ\n77iO8uuOabRuN9WcRr1/Y6TC+8nAowISAoQXa+n9ghO9gUBZU4tNb46I0Q3AWXNJ7EeQggw6aJC/\nXHgd8eH90tg8lNu39TdLgoXuLBkBGVpD2FPaHuoYNTBAu3xFXM7uYvcelwPGV/YGvNipXLwP2j0Y\nDh82/G8cb/7YXSV9/P9Or0rfcYB2wbALf0jHb3xaBWqDFjw5emnxNzNLrfiN3zdPfU9wVZVkANsJ\nXbrU4WAR1CI3nC1tswwYUJJS1U+CLWn0aFJb2dr83DqOCC0IxSZObfiJtj0spzXOi3KkIROvv3T7\npXtSwyd5OkBsMffefKejh+3li/vYrZZKS2NYXdmWTq9RetxC4P+SunxnxH7kPOcBTIlVOnnImf8t\nov9OCECpj0pKunVjJH/8XeEvs50/2urXRRmxcvsMDRyaeCfucmrxsv3px9pJlfmZgMC4n+uDM85a\nCl4gAn0fZrAmCP8L4mq6D6tjHTj1+lIxcUMk9TpkZvavmx6jziEJnX9d6JWQJigedGOTp+UNLF3W\nK5bSvjXthXSYT/+CC7RFtSnL8aY4RIzPXDhrYrSXT1vyYNULFlyi1oVhSj++Mybxb3za1sUrPpsp\nEI2RAR7ZChzeXm/vFRn2e1H6H/teHebxA/F1ybmZ/RsOIHWW2QtqlSZHfe1toNAbM5eYW1x5ToDI\n+09tRUYbAHKt0SsWs4fDiZL9h8MJiNNKwowFIf5oovxguOQLjf+b4qIVWps76DJCdAyb6kq+9Lnj\n4jXsxeoarVPtJi/3d9XmWZ9ceN+h86Z295O1CZ5Xe2toKcUFpS7kNz1Mabins+rwYHt+5mezQuwv\nHK0orlOYctkEge8gUPN+wM2esm2aXPDA0MeubXnrGPCiwH7VDFChRXXeqx7wjejE40c9Q+fuZgbh\n+cMsnNdRitJ1jGSsvVolUxOn6g/9OYwXWwoFJZGYXqK+k+BUIv4FJ47XHYTMlymH+oJGnbYNXBzY\nOceAXdzRl8oeZnhhsLiei07UpwHVrD4N8W5aqbtji+eCQo4JhjDsTykVLz2lvRTyxzjt5prRoN2U\nhRlCtK1Js8fosNk/QXwbRg/YPDPTHzs2LhvgNvpciSuEA20WS3b9Zk/EKqe3Yyy/DGpEfqDa3aAX\neWBOF4OS737pJN5xCYgSsJGwAukHaZ+05b2WUsl6NlXoKHKSSh5wJVoFPdoE92kBrFvoJHNjSl4r\nFasHmMG791tAX7Jil4DmnZI0KShj52DGR0oaDeppwwUjVJknZKuZyromc1o5HJ+umf4zH/gKFtvB\nPQfqFkl5K+bcFB5pHJB1roX1UuImb/vDR6zjScBhpHaoPpzwltwl8dE114zZXA3jyU8K4/5zzD3u\nwhzdznzb7Th8yR/+MkknBHqtzzRZzB8lgYiH4QuVG8+s0yZmxKaZpiS3vu5x0hdb44duKQIEbW3O\nZ5wI5gw+sA5O5Kq5KVg/79Pv65RAgdomWDSHU34fTRmznXGZ+SRb2m7zKnBAl6xY2MjLs1KWZu0/\nyMYBLjrSZLzurX3kKh5F90ZoMy2z+2TLVxrPu2jM5KvaDIKrYCMAYqbjnooyV8iBzwXyYzQxKjr1\nxHwXwWRJXAYddrg75Yvm3byU+glfZn3YcujqWGsSd4WMae9aPNf9Id5RxTC29pinLAVhhfy7pWI8\ndKO41wQ6wk4S55hJQ5gAQjP+V9BhITkHSRYGcsllRfU3B+TAqhCRxEj2zjT5hEwpR77dH5vvuHV3\n3udxVH2jJ2Y/7wC3ewu5QTLlS0Pem1Wa8Idr+PoMZyAlKd/7fHriQa8/DwP6HtgaoOvsvq7ArpUH\nFgU9uAs8deZVSEXnwD1wyLeRHg323ghYpgf+0bu9fbiF5uWuQXOEU/0Hz+3fSEXzBUvw7Ak8qGNt\n0Xn9gi1sn285hOORunafrX23FYkXVhVX1FknPAm1EIPX3+oPvOpQjnPGjE36krJvycBA18aA4RuU\nXAfjyXZoDVvWlpfr1Ht3m8Idq/tidh1C4NzcOVg8FBS+GRk2Jj4xqYlTjdbTVmruOBix+MPKxMoU\nA72u4Ef+6XHX47/hPyCQjzLt3et4ywo0fTBkcSvSZIJBqv9QVAnCj37yTK1C1l1L8XTgA/BN6p+R\n4Wci/E4/Y1Ue9YLqnPS5Gp/Glq6YJWtOCCPkq3etDdZsSGIpeCLuwgfp+NHSr6VOxozxYpDwo03z\n79gKPcupo3atCPNfKaXRQIDeSVz669+Kh3wpxXmsRIs2aRUrhKSsmKH4Fb/+CxXuxFVWmskPG9xO\nJG05r+HOfp7+kJPB/nQuT1jGetDWk69soK3Hdc1w7OuyKRpPQte2OfnNyYftcfVvivYOWLhe6Jle\nvApklAPNjBI+eqa9RlSIL7cfWxr9bZ4HbjnTXVmanm6xkdfw4GETPCdB7y1hvF2UpnfjONFz8Gyi\nkLT2ieNn0dr+Dwt+2qXKi2jyMLL0MwjkV+L6pbyMpftlV1CKNeE+xrLCZxT6/7TPMVpx0+WanQDJ\nVBc/vcTpCQo8eED9NFte+vl/23Wzq7nQilbdo95Vy6kIoCi/0KgSiERivW+ARhLvuY/9E/Sb/3E4\nyILKksT5VkX0QgIoNHgrr/9RMJoOSmigAYWCS5X9Y/AtiybHASVcmKP19q4nHHZcsZ6tnm/bCaTL\n/Jsdeg35gPM7P6Q8DnQcYnAlss7L8P3lVeUlGfghWPpx3O/ODT6y1fRf7x4SF/u3Gh5iFPkwbShf\nNzDL1xGqcBp6nnwFGoOQPN+Q7EnXlXPKePZY6fwg/nEG1M1NnczYjCZBV2ETkmuR81VaMRWpKdxj\nnUl+X0vkJNP9emarCQFSo4Y8wi/2mGJrPUB135ZBBBMmpnmLbI3ySsrvqUU2iLCH1oEUw3BvH4+1\nE7y8WHYvecBY7FO2rxOf43UcUt14KTSfDYMq8Pg0htdcGHufgkH39eWYBcwxlqeWTbvAigjFYdRC\nE6PPydLSYSmiYaUGulaaQllPu6zjPlKS51mQ43HwpEwQh3IgcpHcOm3UH6OCxvqXvYYgE/pUqnxB\nMV91s/blCreQxU9UiwL4mlAW213BhiRJOqsgMHappuaYI8/80cnxhezTTGROya2PU6Oa7f3IXtw9\n9lGfxLRq26fe0vn+txy3r2B42Elunm10KHbKZK/fpF9g2X0+tpb1dGlox7dzMltmOb/bhnN9lCfA\ncYhbh1zPMytTSeXSggqodVzpfQDACJ7H99DrU4JPwpGaC6xe7cu9IGDFLxRO866ja5jEaZCyc5J4\nZgwncGvLcmjNZlqTj/zqM56NntOwp9Uvr81xKJV7qgN+pU2b9yPXC2v3xmIIM023NPAnFhcxZdfb\nb52SsqWZxgaHOtItbREFEB2cZmbLGqvidGj9aVoWnVDjLMK7pcolFGLnegC9tZUDrt/KS0K/9fTD\nGqc/Qps/TX3uLi4F/r3fjT4hIBmLzebvrZiI6Z3onPAVEVS42bRagcUssYCmBUHCr5QKeXmj1mHe\nKliV1eFhtEmtVWiZ/TusTALy9TKlcaW/VkeLdJhJxIxh8idd125uokFnO1vRvhbE4g9ZKpt8tnID\n4EMIpBXDPgogmdyAGqi8jgH6uJjMfwSm7Rw/+Iz90f085rG/4QcVQQLpCMxQjOV4/zNAmaWauFN3\nfEzUwsmIBvRFAu/OHoyuuQVmX+ZrmBd3Frqq+Q3bQlwrC5lRc+uYK8xtDV/T4sDYfbTRMIRXE/4u\n7rAvh2SUlv4phazPL3WMva6+GGIyrqnSszopcS/v5mabLLzS1H42Heq9R21ePuO1ADg5odbTpX+c\nmTYTEIrb5awUs5KDLxm4Ln1EGqUvVCoLpef2ZihfWq0kPtF3WxEqAZAYER2cQW9JiMJFCD9vXDGf\noJ/BSQV2R68U/xhTMgORRh+aYfa8pLY2kpx4DQZGWANn58l3pcKZpnEo0Q8+9ND9xOrjjGdU8jwc\nIdnTI/jAmNT6Yjxv+IbF2T3tTbmI19ZSLJGfiY3+kBjnW6DWjusxQX8Ex9lfvPR9wy0pXsMzWF3s\nqiF2Ja4zJErN2woJoNiVISOJtvCOcNQL9rUT/e0a/3ZfyoGYUhAsYxgUl/gAs9lgVorXkZO9u2Lj\nH4DGSeamUBuBplR7hOZh7/DmquUbjGMgkaEcq0uQ4hw11MiLQjqhqmcyZtmHvB37yyFe8EGT+93B\nXk8QXIJPehyHYqxnHYJ8xcXRTmS7pgWZsY525UwlEkbw/C/gd3caSNz9fUWSt7zO95FWoT/Rs9DF\nmT4y8L2kOlKC0KFb+t8VbWA5VAO00Ama/U5W4k1UaPEnCTOup21iNEj9E3EP7JQAmbqTJk7Lg9lB\nNwbv3DSZzS+cqdaUIqttfNLHoOj05nTxg1zVlCkRBBgorAB/VbX5kIPwFGNGoH+iAGHBvTqcYT4F\nHO1W8jlWaV8mTcSt7qOjatUlJVtjpwWlDw2DbhZxqpWrFgovUVbpCu1d7yzf1hc2uFn5xS9A/1P2\nrWO1bD2RdRVYl+jLOuovoTCzwWWT69siknsWmU7GmHv4Eun96yTBfum2JBc0W6RT0Gln0YcZ+zmj\naN+piqTj07Zz6kXAXVFLgz7dKngs6uK2YLewsJWT64to/IzICAWZhYPoCCd5KC5iAKUO8j6YOXAD\n9JebGuJ5Q0pwUUKt5hOzhGebeunzbocUiKoMHFmlqgvknLWEG8FEC0g+4DxBJ13Uv71mLS0brpfG\n1dg2LE9wumjpqSC8xSAl5AQaE22xtBQBtx7dCXag8v7VC57tv3cG7fzE/zlEVdkK6hUyb7t7XJhu\nx+bxaPg6SR1TDsn4Qe8XtJn7rMi4797XS+0aIHpCuC2O9iO/FokOje1A+t5FyGqpDy5TmwkX19qt\nhGPlwrUUo42UZ/TP+cTbsqwtWIT3bjGzj7g+MqDWWzDonb7neibCTpZTO5Hj0sJ9Y1/OVfJRX1wm\n+gjiXlKcMgGHHzzxfXqySrYnf3QUo0ZRrs3YjSO7SkiMm/n8SDHvIpN2/HaC+h1xhkYbTeM8fSmr\nfcC/H29sqNImllOILuKCQVsl5sXBE2XyLz2gw5xY51HOwO8WYT8QrX9WMQvBKMfBnwxNiRK27xRr\npr8EY6o9l1XURJidENTLIy2wabMPMiEe5Bt0oWUC4TFnQOVkEI9OaBFKPUh4j4Kr7j4qpxeS0uO4\nrfFuLqGzWLHa89a5nlZR7eCjNh+xmhl+bdp4FcgfqBp03yhSzs/JUWxudxic1Ss+knIbaMgc9Uz/\nmnAIh/8zZePtOsyWnp97DGwaFHPlAu+njso2P2ZsHHXvLy0HjbwwkUtMxYi8zCBsFLB74B6D7FBn\nJrTFxMrb1O6Ag1/QqdwWgNZcMFUETMX3UFGoTSziM/RGVHCKp1pFJ4JV+uGHq2BCtxKpPuPVBm1i\naXDpuqB/4d18f7+uz5LaBEcwtEbIH9gUmlWD+Hp9StLe5bF4yyru3D2FZ5cNO8U06qkNJo44fYT/\nFeigM13R1i7YLOs2BP9FLBrOkRRYKCeWQWYbm3q/Fz0Nt17oN53GoVdN/i/PT5JOee6VPie1boAH\nYD4cse4zf8igKWof/AA7+MZ1nn3F9gShaml5jDtnonWVSz1nDwNvqGzi4BVPNWn+fMRQzwzB1bWX\nGzpbn1ICVXP/6ogU0gzZg2cec1HPcug9XU+es/ej0t9v8IHmfJPiD7Ji6Go7ftNU+qRhrPfCojQj\nJGR/CgTHb73c1zzpSYEtkgbyYU3S5mjjbttz2Jg9Ux6n5Z08AOpzbbKsDr1HIrmtdZweh+8FaZqK\nJg47h1KEwGH/6CpxGJK8wjTbhOeXni7xY9izeCljOfy6v0hh69o7T2CwTuoAK/lqZZZ5hLCEVjF4\nyCgqpWR579ftWxrvYTibys1fxjTTLjWBhQNVppWCz+tJpeVQW0gOcDUOPkS+RbloG/nDuaT2pDP6\n8uNiyJnBG6mfEIy2XjDcNrxja4jtx6JhVMFrvnHvtYznhLnBQZBtwmI9KIZqSS3UlDKGF86yh8gJ\n2dOcLwddeTvG/vAwICqD9Tm+QWJudMqAwHsXEYHC8JNFJhsif1fZZsR2lgqryruf/kZ8Dq/qrTok\n3/fCEDKngxA3i9tu4iUMFo7EV4v9x8HNWyKhQHmAAwMExVZhohx+0B3D8P7ruajSc6rLE/2UPQII\n8XBU0wKVw7KHHXQd9osAvXCkNTQBRme9KFWJuKn1mtprVxkqWpi/rRi5TqCxy+1bbAjJoYafZkHg\nzPee9rfJKSFu1DFKZZR2XD0Dh0j6XJYFW6tSiXrmLzfp3XjcuWBeGHCGxGWrOyeTtYG1q9Pbdl3i\nGAVn/EfHZkuqcBaAnziAHmlm4c9Nj40/B531Uib1BI0+5t74esUChW5Kr4uq5z9toZ7viIj1xjPL\n/m8jNXIJ8NWF2+TpqRTqEy5knLTwqIj+pBlMTXgAbOjabZBm8JGNgQZJPNDpVHhvzzQ5pSgxFNGf\nda++9zhUWWVI2L7jM3ixp+NvSfrhqcTzHAKVlbWB+1GV1b1rUoHLuDTblsWIduLNoyMNGJbbJyAS\nq0eW8MBFq3nSIdsFF2YewHH7rivenPFmtb6+2WeGmlMFFhaksR2GXw2sY1YR9nMcJvKAUG+RAc29\n0YiOu0nSWZbS5SY19VZTPMEzlKShwgDKH7k0prbKUo0ATFfjqXvayKeO3TUxeecZedXOpleuY5PE\nJlolFdoB+KFlsCAZVrqicDnyKedag1ROXrKTcVPfPfKDFDWy+ChaK+P7funoTs+8jfWcYWCD+7Vl\n99jdyZYaeUy4IDXPP7ZpGn2QH2WANV8iHjA3xZcPtfQTqGGwD/aMRjToWmJOMB9n5tf5pfRN1RFJ\nlPaC0RH2vBBqxmv1Y5fJJYRwPg3HrZBB63A7rbFXyW9nlJ5qwfQVMpgOOgv/Wb49Z2LfiSv/lyOP\nkSJa2FwcGFk8mxtwVlw27YMtIzOCzwQyiaQNdCZyRCKdkM7APaxMufoPJY07TLkyohZ4RX4IqaCh\nltvk2RfTC3fPZ4kuueNCgYDTK4vu7i6YxRz++hE+A3ni2NuEHyuJGaMOCbbEsRG9OuvjGV+U4Fal\nGxkNA+lkF0vvq20efdf52s88cvHnh+HsvMXmLmns469D9LC7WfIunhnLEcix2hcgC0lBJqwNE6ld\nxcXkbWJUbD+lip44P3QhCdfaY5PiaC+JbgDnxYj3pSEUnCBNRGwGbuI8qyuhHhfyMtI9BdwGGvMX\nfa2861LwcvfdxdOBUi4qyO1qcHdFJ9kvCoS1Zxh0Xogq0P80qRD6T3zbBv2OdfxZfYNa4RswUpgD\nK9fJGEwj8sY2tPulPT7cGWE68pCZMrRfOy1qFf8mTS2Xee4R6HEUBAdB39Sf+ySiaYt5bGWjFGRS\nsWvPM2edL6feJZOam5vnPwUt2Bz8G6+2WFptpobhgC2XG2wpy5qSphoW3I/+9zJW8waO+8LB8/hU\nK/ZhlZhCHWitIKHaa4uDYa+i/XzjYxUt6z5xojrXzZszpmweOF0oo+1loW7meCydN5JE9W3GCtog\nYGQqdpikmoxp2Joxn6f46wR2KqT1PUD2h3ZHho/D2SSm58KF2o+PGJmYz6PE379fJNWb16xjlzIR\n7uS/GYqSW4Yc1cXF+UfNT7Q7/2A3TlsqUfi56BL/ZAzgE9sQ/bylYX3rdweeusbfhrGIlnPS2VME\noewOctd7kG96opKd5K2+XM7a8JdeczkLJVuOaXutc+F0o9vHzExEmHEgt5XIaNs/KPmboqrfvYFp\noon7Oo7pk4U02HX0CAWTvdzu8IK/u4IGo1DHgM2lJQd/jS2lme5wnhYOgXl/alTnklBpwK9Cjhyo\n8KYpbELv1h0gTHlIIDEUSHipblCLAbZklP1D/BqqbmIY9DAyBJaRIcCioB57BzmqnNduVmPLfYJA\n8JrQwamydtLt/83D+whK0MnswL8YZ3HiBCQ63NWbRtomjTZvDP41unkGJ1VrIcCLMWwPc5ud8/H/\nhvQUpgUfHRpTTX4PJIqe6ZmWMkZokOetT5i+ghbV5abCb10K57+f6g/KKukBgXdhqpnUV8YDh1b9\n3hpYznSbO0TMFBE2hggDjc8MqXWGap/OTFwPB3NIzrefEf+0pcrIaUjDJVz00vSUO1geBBB0qjjA\nxHCY0g4UIJiEpqeeJSCSxYLcZEWgsWDvVWo5L1VJ8lGzx4lFIN6KsSPa25R05lqGhOuzT0ec9Bmf\nK7bo8E4omxlM4DlY12u6CmT9d+QbN4oHJmf4CNOV8WuYxXKozWCSjhNiGq8seQKKbHGizWQohewN\nRNLyHX9MLTLIefXQIc6wT3Ho6s527qa/cZKmZKTASbo6HIDZzhAntO+lj4fYFT6YFMOLVgwdz+Fg\ncJ0PdDm5+eDkyBpUj6fhkNlnmmrzRj+tjqWqnY3TNqNG2SL0suNbKHYZEv/22P/A8pdd+tOoAnaT\nEf2D3DtiuCwiUlqkMXSZHDk+zt1Y2hHzwYT25f4Qg4Y8LyZzBkVhcWwT1Z1UU7EHBqaCZGYLT4hJ\nDp1dB+H4SRaFva9SqyluxotziZnshKrdygvrVzyw56BqofQF2yWSZrqgcor+qJJDTb5sEsVIgxrJ\nHYpaHNZaDD8cdWTi8G77WLnzeG7tHjz08Lf3JQaNxoJyDkwjPcK52ZKLR6I3dU4UbDbsKSpsAwea\n0UIDqIo8N1JTvS/Q0oQlFsndrcsGmfLaT6jcSqVDq+Lc5uvQsPhq2H6xXexIiNxjp6rcoQgnqfxA\njIdsa1GQpJuVdSsAWevMkRGQrEUO91OQx3bgSY7iBvQyKD76a8jlEvL3e7izb6NLt9Q5SsmKUFP7\nP2v6pGcBWRe9oB1pj8o/r+yT7HQPzzk+EYTVrX2AumB2exON1CUeBvXL2HzoqGg+V/aKMLKyHXFP\ntxdAdIPsEOczy/NIAPh5m8IdAm2O+JvPGvaopFyiuDrQ0iY3ud8Ir9fOV7kcOTEEt6MkpvaBjOaA\nfvwRIqx86vhwmgqZOl5/G25MxT4+S5MDvce2G4D1pT5alf05ebu7CwVZHhK4lHzK070J2q7lmZkC\ndIeMbkz172+YWHrlxlQ1XdkrMTmV77w6dvckk96wR560zHr/gafuMOrrNmug9OvoH6vIrFBqVz1z\nUrXsrohOVOPLCpitmr1ae4FM7tBnR33UCZjcYcL8MAtUWTAHkuOq/UEnmoT4bdfPlK8w/M7y2U3j\nXXrMTpaPOhcvWed4QtDP+STgvlnK5paXt3hvtRqj7MvOAvNPvEAKaRwsCsOdGP4pr1RUjxiXY358\nNuyu08WaSZOBSIjeZFSjQBq0aJud2q5l6DmsuPoZ1MZIqcstcIjTIAWve/tsHu9qamkjMrloqr4D\nDTU7f/09V7uZSHHIVrzWBw4FlTYgoFfYFg+lDgs2VSfeu4c0x5TDLQ3/riHuqNR0/K/jPJuXKOh+\nkymdFloGfL27xV3UYXw6lRQRX7lTPY5UOkgGa2YWnh7iqTp4f3/QESRJVTCHi68FrFwQ1/j/rgL9\nJweyMN0JXFXlLv6qY7dNAQ2/2JLjcKvFCrh2ScEJk4YZXrYnHeqTBoOOHt0ZbxIkJ+1yhetZTJ0t\nJO3sArhQFcKByckkq1aJdfL7Ki+r++QsWz5DF70SL5ClpIjLKKIryrMLxZDSALFeQdYmYUV2dh7k\nuzOWOwt++2zfGLQeKbtbQb8EGl73/LBLtRDa2c7HjXv2VCRoYjkNTbW/obN0dYm+TQKpEbgpnnWl\nFXJfvyIqn1ovGgWxkbyb0ZFVM6ZWcL4eSWmLLmoDMjwqmnSoqsrHe8eY15bMOM1E11MGKp+udcmr\nF3AsPuGpArswdU38ht9fobjgwgEa7GrJAazP7um0z44yF5D8uCKM6QRJr8PKnJ5/6kmLLpq1xWX7\nzXe4w12qYcz9k2BJqkIUmFMWaIeJLlN9kyWkpiRoDcGdXdOET6vhnUHLvxCmzpb+v0/MO87wry9Z\nvhn0Xjv1OEVWsBc7wNCyzasG9KfW3da9pPp8DAfesqTvG9BPHCln2vesQ9Fy5fIK2bGTkXqezdz1\niQMZ1dl9VpfKzAbInM5KVQy7nRD+untAvDpSWXE8tAPnRdmmslli1R/epFi0QRuXE9E28IGwIIYD\nBQYBA346tjpQc1slFOBfOKelMGTLlEjUrocE9usHFhMbeA7WNykETkAsOqcMWzR9zoWyPxGcZIec\nm9/hioNiCP4htHT2rM91aqRmQS+fhNfk0RZALsbUeaBf5gKkPy7sMxaVTyBa/GPvZUJUIDtkoUTW\nHW0nOM5v2+i2hknabNshG6/O7yzoBuNcPyQWBIPF5yBF8CgIsFz+jedC++1w61hMnnPXnEAaqqj1\n2SPCrvQL4dFZynGM0iuZLRFdMml9CHN4vHfprdHGJHBICzVhWrRrfk66WDnfpnmlbnekxzmdhYYC\nYce3S0ZJnzlNLhpdTyIAqYjHtGWB/RnUs+n5DPOBmLrDOW64hMhr14VVkrx701ROosCE8pVy8jQ4\nuKmYHZmsAH4Muu7/21vzQKntqiy2wICku/tZ0tOCwifE8EzV5h3fbtatxXXe30Tk/XdhpBTJRUYu\nJvRywZ6+b03bgN98PESv1XJjJV+n7VhiBtTSEB88DEMjAGqkLmPvog9iiZCubydz5kaUiNE1+0T/\nagIxfbpOJ8YX4ODCOsMijcpnErrXNrGLHcTrxeMsMKd3P2jBzTg8i4cTIudPH8NVuYwXl+VciJ7Y\nMcMXZoJQ+0oIxaH7UUofcEXDcxGb6TD2mKybGQY9JqAV8cT6eLvRzBzais+yOe6pFcmp3fUzFd0z\nRcDLiX19vEyFZIZBeeuU75SGcQVcVhIGSDsjn27Tdy/JjvDaDsQ6bqANWmjKbrsPrYNzI0n0AZSy\nphILzSxlhj0lFATH7IA27r3B7P24Dm47MkXCe7oDs8xY6kUvmONohsgb+jpUSsl3knQE8ZAY7FpN\nuc3kvTBvHzyuTdue1ytLNK6DriKnwQ8Ggz8TDI2uv1Ow+bQsjCaN62nm1oRmjo/ukDg75NnsiGFq\nCdKs51OAtVLWPakXN7CByjru06e3Rp6kRXRACw7iMGScgaTDmcqLN0nfCwyeDOwG8k9I+q7u4+56\n2A/BMXw3vbpU/adhGn4p2EUC/CTEb1x99KJ3peTiAOVzOieSAmtmYDSMDFOaPeBFi22q7ZutZ8PC\nZH25LJXrqBYqGhIFUNV5haZds/Tr+tmQHTV29n2dPmebzwvWsWToqCq2IaYER9y4+L3fE8VHnDWK\noHRlhwMmiGu5kfakEZDNGO0dJdPCkX69gZQxsJPvWVhhL1kM6fJoaKYPhKLMMFuOEYMawsC4jdAL\nef+lutL2zqy5OSS0hxCbdI83tKQY0PheSt+WLVWTLiNu1w3BP5KhzawCPSoykAGdl/RtNVeeb9db\n5sxkm5LM59qCA9oJwPdCclao0jaXhzYK1x2K6RPIN6nLrrccfIQA1dl/iXBl5Es7f0tL2hiV7EGo\nzmqT/jxe9Q0226gD+vPhHBH65qZMHvtZ2kreFlYAaQQBXoddL72QnOvRz/H5kIa7y4JmJu1kuUX5\n4HUYA5GjIY4v5DB9Ryaj/fTH+T8945ROh70Jilrmkc1g401zHSYQrJkIuslSmm8A5m78jTfcTtSe\nXtqC+8KBhxA02Wkd7YH1jC+v36YlFYFgAV+mRCXx4QhmOr61d6kKEAsEJf8zdNq1HCUGsLUgg6hC\nbulSL7HNopRSAjeyd/adtGLD62dtGU5QUBnNb034ScobETFgEsUtwP9tH4Q1rjSj0a8SOQ2nfPxh\nJekgSVJ6qm1FCY41VLN+z9FBruKxptQ7URrf02r0Jjg1yqGAfuA4O0fpdA32KHkMgB9ZS7k+id5d\n6ZXpsoP2dQTPLj96FVVhRyGG0k2ZIUKn1V4+TnzejSml9w1Vd9zvYEBURGYGBG/Z793DW8Mo+jFa\njHXB0wmprxQrhuXlir5HQSgeGosjUck2Hs+zOAEfSXkxmE9ovdS/wP1UI9xYWNxJJJzDA7fCcDYz\nZdRLUzr1N0BXhaaILYTLgLQ41BrthcULJFI8LlXv9F+F2aH61i/XF7iMVUYnPVodwl0z8JcvJ3lh\nScxMM9ill9uPY+0sKMI4DJprF9QIaFfobhcHeGou5Bm22TtvV2DziXlyLuXfbMaiS1RfxQjTnaF4\nD+lJKdolGpbPrZa7bndJU9eCRHS1y8T8ymp/35hlDnM6jgpcn8XNhQLAAUnCoPUGEIklWqCgdK1w\ncSHyW6BcJpLwa3F0I/FJChpurwEj96Bd5iZM916H7q1Bzce96SP8BN3gcvgH5G5Dorb4450axvAR\nqW8uyUOp83entDgTAbvrguG3ozD6PLt1PYOUQf2KX8AWQ6Rb0F0B806dsvadjngqNpjreS3f7qp7\nFvPS26/KYKNM7C+X4kCsytcnZs4fTz1REu+HZGklpF1QxsEYvU55GUpk7suYygpb/GkxMehTRXQ4\ndBJ71UOQBmCUtjtImDLoiFUTMXR2GgoBl5s/rOqwFkWbqn0Mz8FAftEEFv2e+3/nApigooO9aIke\n2YuFYNwTBGJe33x0znavAjhbG9SJfLK1MW4iKETj/okr4JU4Xfw03IwDMRR/u7xQpI+0E3sEPZwr\nHifwOTGeyUcEyY20WGEdlMpn9jBTRKN5ycmJ3aLdLL1EX2PvFy1rgYrX+Djoed48hcmPlxzqwCGz\n1GrksbTsIztZnhGCfscHGKZy5wkdD3sNXMXgluSwDB+1ewJXfejfP6MnHekqxWYtYl3Vk1kSCa+a\nkLXU96jUKDWCKtpsyGcMETNv9unlSPgHrfYxytzyK4FrExv6q50sEMIRB160kSNG1IsxQVHDLhcN\ntKyHNn07iwO75tjNhIYAOw7/1u01XXSfBBnVQ46wyt3j6TbO2CfbNXZBrQ6XShoGQGpm08w4QSMr\nA61Tr5WRtmL+Zu1ZQebMYXRxwJgCekXKvs3ZcluuBb49Mwkk56NoRgZLGyEYJ+1IxEJz1BwVm4CJ\nsd+UjbZAYzvA1pCQvzv3r+DFMBpughNx4ec+/y2sxVir4GpcxHQVwt7aNlXmm1gtQD+gZDg0KVcT\nlKACz+CEVcLihTpM7ibQdx7UQRMQ8YEmHNrMyMl65Jh3J1qPb7k/KvxiUm9zDqgchtp0/Hj08too\niHRhnNA7UxoGRPCLYhwVyFCogCteAykzUgpvFwgshq2zPRa/L8e7TTDJhRVf7wt4XCTbUGb3UQoH\n7dp+GJKu/jrIDw4P61m8FnHIEDAn56gQ/JyYYaK7qyPXDpGxBOhvjJnFij8r0OY6NDXkOI/8M0Di\nENW6dOI5QYnQpI18+5JsSoLG/aadGaK7D0/kHZLxWP1bfk0gTHfbBjqyUFwaE+yMK1NNs08IqC69\nDsgEtvZnB+3svy1EeMJSxfY9S1NkOHP/PS3t3XYkgY7vXlqLWTSpZcvz0tQyXEoGuVZ0EMCOPWiz\nS0Rjt5pItZ89kqiBxZkVTJwjnGulFTVWv0R9CyoL8/sqsZuCEw+ZLvYfXVBnWnCp2CbRtd/PVYQa\njDhgOsTDOkHq4K5A2xmIB/v10oYtAiAWGQxiO7Y32EnneZnPR3qrNjPtAOP9dTBg/D7km/j0W/bz\n0H1hgf6AaLlefGMWf46Wmuz5txY1EdsdUAnI9W9tAVsyWb5imz5E4zeFSLm4TfuLlaIUGeTaRpv6\nWpUicSuE/kLFZD8lOESIOLDBJTHmIWtYXTB3JTUYr8AFdvxJwDQPMcLaCXXQuc3/RlT+Icc/HwjQ\nHdTZffINd76bkTJjv+t5S6P/b7J5a8PnPw4u0NsDwInbH1moxCpAxNuzf73Q0esKEYnWOB2QCNDT\nklPntYHzypdHOBsz05vph5PeZHRsbSrkDe4LbZ04S5zzkqbFuuHWhPeL7sVw1eoBgDFs/gKL1q4z\n+kXHUvwWcUfxzfjx4A0tIwT3knlPNUq6CeH07vEvq3uho0PVwBZivHbVI2oEs+KgNo8sWgR4gK5z\nFAacAwbPOKYDCcjoMC+VSBsBuK6SPksiycpClpqYo7ctPALK4vtsjTLEyUU0fwnF8KzZbMcloRQX\n7/eSUnbYtZ2i0bcT9gcTXk9IevbcP75L/js/Vx6RXo9zN7PohQYZrEjeoUSaOz0VHZidi9pnQJI1\nTUJI4ZP2azdGgHTw1o7t4v9t3yat6JTacs6HK9MEOn08k184Msj9e4GAPSpsEp1aQD4DsKQ3RJZY\nHwhWFam315UpraBflGW013RjfIYhdJaK1euCFuafhOgKTr8oVLlYkm7lP1Ouol79v55j589DXcQm\nj+8WHaubwUyQ6T3ZVMJH2UfvlooqY9aBSPCLI9SBrSLZ332NDwdvHHQNG3h3F244meO1fXrMjzyW\n/I8Mc/kG8AsSQMWt6lDmU2jWUHi77MJ/SCaGXUFyzzQpt18kDcL8fVUZMLHjSZ5FfI/yNEzS3S1C\nk1vZI/QWu7ZLJnNXnA3NqXvqsxg8g8/loMzhI9AwCM115SikwW3YLV5iJEhI+EhZZjEO1gEyfMsW\nL4IYslHgNKUELCUgF4eN4msqZgkVKy7cF92EiQIQnsCWOG5pNlnA0TazBQHHdAdGi5aaDIBq45DZ\ngPr275Ofx1NQ4g+1Bo1oR5Flc9Z7o0ulfgC+CtPfAtCgKtYD3oKzHtphfDfK6h9Lmv4xU6BfnPVF\n1KBWAPA9qZTMQg9FJFm/Ci/gT/zPcSa+E4EBusn+eohNdN2FPMHbhQSetLIllC057lX5Al0tOcTe\n4hs2tVQbXsKn9vau4AYmTbLae/ZGISKT7DDrDmumxdvAvRzZMCz/iLlv2gxO9KQE4B2Rl/hIrLNr\n18l0OQATijqS2NRIlknpwTFLihYQerQ5Kqt6zbE6Gbwvt3aaQ/q0bjbkzZ4OlXO9cbazAV+Lc1MX\npQ+mXyZek5tQWIzJjQ/CJe+U1wNdMNFp8Isvj0C0DuVtPHIMR2g4m8LuCYgzGuDtWO0A1Asb/ZLF\nR/Rl9mOST8AW3xOHOo7CvCjU52i+1AbNzheXyASw8keBuCKc6sbsBzCJ9+3FiiLhLuhdBA03SPZA\n7rdI3Y7PaR66yjg/LEUkqxxMLxK7c2uyVeoNE/O9+uttHMqToltijBT2jUL9XBcCiQw8w043IwGX\nUQ0cw8qFM6jRJBl3LjP3zZfAvdITDa5R3718Ay+AqrBdMqo5Qdz1vLd9hxqNGpP1FPjkdUvIiiEd\nUmH8s7/8SovNuLC/Vn9Bjc3y14QnILqDjZkQPLd3h+uohOYikSznhO/Oq358LKZa6VDgLjbuDWQE\nTV4E4lrqxy3zxyINOfBAR1+LsFwD4PNmMXktMhR4eDpDbcIGXzgZ1gQ+Uz8CXZi1w6UTpAVDdjL0\njzBLZnc1acrfVGnPHYmUUr1v7miMfVv7RK2ySCCfUyEnC868tfyfZv8kyK1sP7egJrpCvJEwHd6k\n1mdsFyRMcv02NbCXrT7VhU3MNoYw3vpRGgI4a3bgUvDqOM3xJmjAuNNEih9D26koMHLIx+NahPST\nnKFPJzlJOMmEJCkVS2h+gLnrjiHiNXc98c7+PEbTCVzPhoxQ86SFqFinogctDHWofAAZoEXd9Zd3\noAhWghtdxMbBMBXIy3Ww38m3jZV0w/tlExCrJ8YuC1fX9er53QgF5LL51UT5qT620I1ag160OBL+\nFgB5244/PZ1T7CNiMd0995dCBH+Qg1NZJO8iUHjvjJhVAmmtnUDCoaw3rEJ9eXutXSWH+T7WUnfz\nG0I0IB6gXeJInb856HGM4LzqGjvHFM6GlWjrp7g5XgQ8BV6MlaS2dPSfCbgASkr6ciBV+VEDtxvv\nLecBMA+FbolUT8IlyL4KYZS+gay2R3JA1YMsqoTMreBxd0Lo61UwuCeDM4GcFrzI/ZfDH+IU+1v4\nLr/bLUrJgNFp5269KdwTbH8rD/b1Nv9MbI3h8VbCMMZbzVtinhke41AM95BPNVUzRR+IKC4ftkHF\nXLOJxM1huPMZKDILeclF+Qtl3rBJjefSgYRt/KxFCzVN2UOmqnwxb/GO3jeobVur121+VAhh0hgc\n6U9NwO43Pr7QqyN+7wJT8bWuyIOb97Bs4R+gdqZSxpQwyYcWNWb3+Wh7DNKn4JAHCfhwJTsj6XpH\n7ZiUeTk7UX5z/iJz4V9/msHOdP9Y/CWSHB2I8nWTpBl7hNj6lUcxTRqocrolXhDYU9lt2Np1scwW\nDzDnFrGzPphcytpZbGXv7sR3S52iB5e9B7GhJw0HgxtesuNpMLfsRzK86syhaQMCEomCu6pxRccG\nfElsvk2eedjv8DMYATSMusBPZ6NYgylQX0G2szz6nEM2bTTPNjcx5p5RmxGk/lpoINImu7V/wj8c\nEuw8JiNh/MqAn73cmc+vCM69qL4wk/Ln1BIi2TGf7JOpcSxO0gcPCJko/TjcmgYHevzjvJSE8xYL\n1dCxtKR4x16qUYamg9y5/V7eyM5936PU3b5Z1zc2F+41tsyLOmFOmZuSPlnmYEyKuzyp484S3rTJ\n7WE2vcUb3WCJSEU8HDAHbKOcnuDSNn1ZBX7l8imKUj2zQ6EMC2z890q/MqRRo+g0kcmRYRR7Xlfd\nDcFhdSrwUEzmU6WZgVjJuPIxV2UEOFLJreGnxRzB0KZhLMJ6CuWFBYHsO6sJb9FDfn/1nv0rdctx\nVVqEgTspRTyuD9ZiGLpwx49jNyJLCJVd/uQNCAMHG3WwfwaLXX1P6eqWG5sFdbcIBQTBumYzdYV8\nHnmsFv67jD2ramLOWG4fQrZo4l7G19y9EHzWYuBgxFE1d1VHBT/VkIyhld8McoOUWlfkH2SqNsoN\n26vdW3NOIbpaheU4eH7LMfOr1kYyNAfpRSUcIDXmKhBvZXRhOUChkmlalpSiDFDKxJ7jmw+Jnur5\naWm8FXg1dSof0VlLk2JW4c3pQjhbrm4VWRkwU2gOU+oUCHz0LJ6Of/4zG3Ib85ImF4POpuvvWVzT\npx5FGgi/0FsssO49D8+2itQVxaiVzdjrmPm+NnwMTzWDDh+NQfQJFRvsf+BeaHRiHMsp8xdW+ERG\npTTNrPN+D2Lc0SVEWA+vzj3xp+r3tOTHBB4XKXeDpUiqr60vIYH8K3UAka3jduXqXTQzvJXvXUfe\n6DxGH8ZC3pbasp2jSXkMtJd4HHteSbRfIUiE3uyPmjSgqLQ3QZY3KYnEwEMLfv3Pa2ygbBBs3CeZ\nUt6Y77lq90njxgm6i5vNGheVAbtpqPHyfdFE6anYRzF5A9/MA4QcARcPuHkbiMTI8HEdyucfDdmr\nEkGzWCF1H/4f+wLuYCKu77fjQiPk9RbOMccWO86no4MJucf1KIjG2fk4KS1qVlqlpA5yAiIh+jPV\nNX6lCRRuZ+KxChvzBNKb98qZqVoPemfc2jwuD1PKJ3+iPNvhVvgogE3bT60rymlqUNy7O8VURkoW\nTL8jgN/6L9gOHZMqiTIwH8FTI+jihn8HS2Xs1vX9DgVT9YoWfLGwl5jyrHwbrzn4vsDgRpKMDyYv\nyYga8TN5uF/IDb65QwvjxTzZb6Y+b5DZVQ9xANqrQaKA/qJwjjekNt/wBRR8uxXoyjOK64BW85XV\n5nKEX0FsyQz3Tpkh2zKn4VjCZsYcAkqMN8bfu+yJwmUz/Ko0WEuOq8nbV5cbvyMY12q7xI/d7CMu\nAGOw/CihZ4JYCK41K2vxH95TlEMohGp6CHuLRJrcrAQ2FxthU/mHRApJd1VcjK67GFy/rI4Izl/I\nonAA0nGgfVFLUN3flY6Ah3djnRtw9gOoDaM+6Gcg2txPWZtoFt+UWoWnIlq+IHp7X3WUHo/0Rhs5\n8qD0NwIiMN2OkbDY0LxY35o1ANNnANmUwSgIE/j60oCIeVC/FFwirRxYDS27gMrY/WKdw61fI1YD\n/JknXxa05Lnpg0rB5RCVpmcLIYzHGPGlVvroFlG3lWw7bmVDbOCtpk+Xq/ZUbgvjwEL64g6WRLXy\nJCbzEUU77qlEyy9mA2znG4GA/mgBEqbSStYMb71wOoFEqVCPhE4iFkkbmxJ1vQatgiqbb1fp9/S4\nk4Rz37BSFmp4vg9DvQasuRw2KKooa8bbtuVNhyCxN3j4L9BnLXI9NxP7hP8lMBYVxu10tG8LDeOr\nRO9Tm6m7b7AvasY5acQJIPu2Z3f81FFl5N0xFjJFxhXLtJ91QUjxvcu/AYVKZiYg1TLGtWeyBBAy\nyAXNrpwiWFuIDwD2S+QYuIxyqp0YkIPa5RLXdW1qaS4hTAOMRCaRku0SaOf0lCU2GHAbWRkAdp4B\nhGlr3wdn42E+QHvqgJXatmSGMsGYRAf9pO5IkDWW8p/7Ae+ItefEz14swOPVw+hFzjkgKj+N1lnL\nZABD+1Zq5av62BaeC/o7+PzQAK0qLnwbinA/8zoZkn89bM8vNSBgbkQaScNq5XE8rgD6nqAcLiMW\naj8x8/6ylUnylx/rg484udVfjv8M++g0npvbXK12ezuwPRYAE7l0AORKc1BW41Qb/RX/8CoUa7Ui\nl5HncnUA421aTmt0RL05imF4h/euBvbKCEs+eDoHwljoXkXaQ+zQDwhIWSkLVVeyHauDhydCXBWR\n70Aw7T6aYQxA4/3/LqTLCdl0I+6u127Ntp7SXlQYPlk09RpptKs59aN6U5wD3YSzjaUOcVVHHSKr\nIkAPlO57FG6DMfQ/W8STtpTZHg5lxsV8azWY59o2lKDKeV1T0p1id/k9ezPLJud89lEHeSw1QMdf\nOMvYrPfAZvDpsCKak4cplQ5S+YlwKV3BjBTuLsND2JifopCOqsvooZ4WzuemQPfKvjnfp8MPgJWu\nz8G36dXZnZDClGzeylf3fx/TFfl1Cc8ayw2KDxlDRwtbZLNdd1YKN9QO9VYKxQAVm98vbfMong2C\n8z00FwSa6rZDJrv8Hyqjoyr6K0US/Aj8QbCx/4ZIQwKCVW0rP+GoaCfRFqRs6oMAxObyBq7wCLIt\nfzQc1JLlhV7PATR5bKcIcZng3Yvyh5Zy3Oe/AAmuziBeha6039ffwofKalSRvNs13CVOrJQ3MUHX\nX7z3oQGzGEGphydPfZQQvbgr+8LmUC6b/iEk8xyYero8D893IFh8wVJ5o7xVo0z8T6+bZUh5tIzV\nPZjpe0o9/1pK/FznzEnsYOWJ26TTJqMmz3wmiWO4pyCweI0Etc0FiTwRpHv8hxf/AceK97+UIsw/\nmc22b8vOGt42wGzW/ew6hfaBcwedfG4RQ1mlajrURZKlXud5gCW64msjFFiFLGjq2wDCrta/1/4W\n2vwTywQxQM8fhfUc6NeyysmQyYmVEfZ2FwDy0ASp1duUvyx5HIgDJJmmeOhYmroGI1B1U/sN5EJ/\n6Xmg/jXYfAZ1qHh3zsVTOmr60U/yfEOf3EUi996Bgoik/fC60IVz0ONsk6QJ3H3D9RZ1ZOlTIjeN\nGH5nW2QLKA/hQXOO+pQ3ox9dT55XA8FpxCJ99rohIhUOC0BYGhoGoMQNmGOxDZw1kw2hnwGaL+JE\n8FpVFv+GohFIGZYme92nZKY0gizOpmHnJM/icFcxpMODJsAGh/Dtos+wbaJuFeyW1aEXtWQriyt5\npwXd429xQ28mFeHze2CIrfJJj5CZJlu7uGqHUHBgPjRJYUNn3S2DcXOr9Ce4pIkrVMzbQAea/VTC\nsCGdvR569PwDNhlTYJ6Q/xC9sLP+Zc4GAYSqVkXGwbmckXDbyfA+E0aHeRLSdQfUn135jMxo4K0R\nbzRvnM2dw1FYFnd8viVBQIWJqPAqMgnvdgMEeL2TyxFIdyH71Y8YaoUreqMi2K8zrwhsPasLgvq2\nQ49LiGhuUT9NJqrC4byAgVQCo2/4yU7zga4K0GdPMB4Dhlb4VDo3Xf+caFwScHs5DMNho5H2UQ5r\nu4MF6ZJybmcDARHSSs65i7nBeHjutYt9VzwXp7/QtScBzqn2QhAl4zww22nq3Jx18jqLCXRATdBH\nlcQuJ60uaH/cHTfeTJ2nBkph4z3k0nw3R3ooa5+vn4yOZA+ApnfL9HKwbg8XwOlCnFc3eVeBLQDr\nJ0L5KtIwprH/UjIjbnrbIRZWK30N7SzPpWyVAe6AMvK0O4zybrMgiXsApk/KA+Mh7DIxB8EgIlKI\niA3Yt/KtekTa4uMQut/EOuAMIw+2xCL4X7t0vupJs2SfNzcfw04GAl/R8YUfZxVSHrfw8nzaEJ7w\nqjBDh+Oe1D6UFzsn99gkalY/19suZXirYpZfwjXZwsItwOBtGaEpvoZ8M76MSIal+cauC5sem9gc\nSWkUAmr55D/XGW3ycF9JUFuCu1nlgUpm4ZK+6aqcone/6VbeQh1J4gyAHA1JnSTCbPDtrQx9bqh4\ncRmD9oeUlirLs90iLzPozq/8PkavElbMWMh4DTOqL9Bs0qGElwKhTybuuYSPCGuhR3mE8oxsKsp0\nWYPNd3HWDX/gnpnLmwwaVl42y/fvCoUua2V+cZMTGtUW5mtedg/CiOJ4mIDlY0JGTFkOKaTEDTiX\nSy9qEJZdM86N0Hs83ldmSQvvyHk+mM0DxEslhcTC+/MumFGbhmMqu5Qz//6fdoyHyib66AGe7+3V\n2p3/PeJMSF1vkEiTZIcjow7cdKeoBE1RtUsr4sOFoMbS5GnzPGO6+lusk/7s9zofs9YSf2GDL2Kl\nZqA9ro1FHEcRBVKdPUM0A0l7FIwJnIQvZLtSrGqq3n7Fj7sPO55s+s69c+NI4k0+4AtO3Jb9J4S8\nsJEkFqABX26A4JP6+p+PPGoq70asKuAuO9hzWcfhyLdXNiT0fBTrdywU4gG+sDujdfRPNm6ttJOk\nZjHbAbnjEvl53hEXVw+NNylGl8kLv1HnXhP5VogGV57CB8tfrVtypSRo6qsWteq67+FOkZvPvPhw\nx+oOaDhvj9BYylf/kEkQsg6ECK+Z9EVP6Ahk9AY2tsrZfiUg2sSqkTMglC+wGHz8ZFLuwNyw4CEf\nGjoFmPUkXw0BcLUCY2UG09xexhIjrIWJQ9C5NpmSPieZPeqJIVjQvbelldK6c4lZjGIBguT2Vmep\nfTG128d22dMpwOUgi+VJ8lj5bgWeSNH6IhQ9+WljexVniDBuNgyflU9sXtQAwZwwLnStG2JOlk+O\nQjqeOQJuDgLQleSqhxRXYkr780nNLGDO3vKbBNKA8MQTtbbW4DpM59DCTjADOOqwgaB0E8kV/IKF\nWWSKOcAtW7lOiJzsXvwbuR0CWUbcA8yehGUWmx2R7qKnR8L92GY/+NL1jArvlw5G24uEkDtdBG3L\nREYq/AWn6ymvTXqVCU6O3Ybaly0Qt8f0QN5kpoHacqP+05Gt7DFKXdAKNKyZ3OW2pi91vkvAcB23\n/ZeC4MWpbJnFwRASUAypvd0Eh1UO9rXF80gkK+uDvRVPoWNKRfg04ry9A0MMr0FkxWK+iPp8B8ot\neaN+5pFRyEQONa0VShWj/Gohent5S3UKZf/dqFyhEmNtqbjEpYTIy8uR8JdBjLqmKfUNrCTJiyeD\nsUKqwu1epV0DXakflCTBn22NB9ZR/pP6Bsu7spnmr3frbf1LH1f1qWonuovtSNSWAx5uMLVthi2f\ndJoLerhOzvE/1h03rkd+igCZKucLEPPutTdpjfgPtjfdqWEEQyT0mx7WyNmHFOTjOD+dpYOj2GOa\nwtRQ5Gsfpq5pPxhYwdo9hXvU/EmlzKFf+AUaLSZje741qsLYhxPtRR1nuNcdK1+q1i6zGD3I/lio\nroZ8btQMucydA9VkKK2ZV4RTIF0cgEHqAj7bpUmVFVDf0xs0iqp4eAA4enMjLzFWXUIwVzF1+r76\nqaBJph5V5SP327vqp6zDDoiYioqHoIZ7MMCacgdgdQQz+8rrfmTJnR/geV8syT8wAS62LSZiCBEK\nWKUY6gVIVmrIejPCVl0Mp8H5AtLTdxPVq3UPYvO/M1fhdvZG7ZTe3Jt5VMrdmaM5YktZuCo1nMIS\na/TuQMvhDX3txYHu9fdLMoXGSYlRen6YtlY1oWiQfz4JrvYJPeRGCRUQinYbNjpRA1NoEBcoiQiE\nMdJmlxnH4d5XrI9ZfW8MjY38NxLNtVrrR2HV26SAx4Et5sLbUzgVJFhqbA5iXPhcDLXbTBVu5LvA\n0zY/yOQg6VAo1+Me73OXUcMANSxCcEqXeSdVOZmEVe1Nt4Het6npy6Zx0FRo+5L5GpMNDbDrfE8G\nVDr3WMrXLoNAf3VEdZ4RoyBEqZNsXEVZEb9IXmVMlxNtXTJ6dtZLObn5/wOK+jAle7+m18KlmDbu\njmP1hHkulSHR3r5BZX6hv4jgVTsGcbFOk1qVjo1Ks/IyxaDd3ZRrAFe0+YtW3r9UINOYZg6DlZFW\naKK7jZ0Gyz24buZg2laPbOr4F7YYDVHrULXpT9kZYoebkvzItcYZxgZLJMuwHlgIBREqES96CGsK\n6RS9iDGugiZBK0W+a3W/RZVaCo1uXkjruLlIkqUNv24gJTfbp+O8Fmwi+6gTjL7X/WawjAeHMsCm\nSuXuQv+K5TJmJ3OTEOjb9cYxrx8YwDJ+QNftwipzMpfRBifksW8Nksk0Jnjn3onTiQrNY6eB3EaU\nYdbqiEVvz0+B2eBnUZPruM0dgjYOfYiD61mE7ytOabm5l73y6vM4VigHG3Rra4msikUZpq7AkNjK\nKzjpo7IFVi0MV/kVfApjnhXdV4amQE0AzuPXU/FZZBBnt4AQl2b1UbHHLe5+UyNSNP4/yyjRjx0Z\n8ff+zWMaReptipW4gkO6LF8nYurJnGYk/6uPrPS+suArvSCWDXOwsqeciBrR1dKqB9sFCdB1g5Js\nSdIkCEUJM4ZNQ6j/MPyzVkuuDGImo49msAZZ1nwCRqX5lL26N5auG6G0CHdj3TTwQGgJhX2TBD7x\n/a0o9/kgUO7kkT4FQEm8YoVWES59ADJugfon+i9dltoqZFzK+Kz4H7CBQy51aZcBd1Z/sSJ+tRaa\nlLhutLatD4dQAs9nbQVwyZ3bnXwoUsOcGWDTfWFavtDQaUYf2E4Rv5WvYFkeORjuVkAhEiVSQTRQ\nysidLe4XhdF0oDxB0rezR2SARmLT6hChaxgAA8lQSleaaBsHAttpCY80fhTQgREQoq1oR28uEzN5\nYS1FwYh1DSAnQRt538pDKyuzXTZomct7G3mMIDChLv8SuddfAbUlMjTBu6CFVLqb/GMFADDq6P36\nxVD0Vd98LrGAiUGrkGD+gx/gpo8RInfpYbGtgTawYVoUJ50fiD0JsB5IbRphUn8AdzoZLLCBXUSF\nDxTTrcQ3HKL8DO/jcq8W4Lz4PCwZzuDU8PrBX+F3FkBok313VUvS4WMb10zgdM4iKAnqL5NCPlG9\nn8Yq2uMOQJcWSzhLWQjUpGdIOY18x88Z8j+LSFYytCVUATIvUOE0vsHUX2K+BWaZ2JYwY1gch9Hz\nRADFHkmuA1blcOacCctpAtFIa0sbamGgKT5KGXwIEELQvR9/1U2H9votxoz0wLQqJe9HXWlj0qE3\ngDaSeaLQpg7UQkFN0YFPaiGc41DIzINXiY27I3DABxnicleDxi+npA548W3v6LwdceW1LlxfYcfI\nn5PKAHytRxSfqnpXZtiCP69ZpMzK+3xDJDBA1DzJQun0P/8DN1BgwimKKcGHHmy6MSx8eRAIXnr3\nhNu0SKlNoFYsC0dZMtgzTo3wxDsRU3/nmme67/OweQlWowCVvttXfS5ZPvMDEH71aF3IiX/dRJDb\najtqNWmCcNNuGfy6TG58/CbvGC2yqPKjun5yA4CL5+Q1rn4vv1Ns3aK2h9iVjjZyuv9dGwFNZJK6\nOT248gam8IaRqu1jLVP4EMD+fclclPWUoVdVmF82A5VAX61PQNrWxjIcSCgZzXQYxIax5gp5G8WJ\nRlsqCtOHSwRIuDdSPa4thBM48hwiqPRGMVq+t1JMgP+90CEYli1M1/gANz2CBetTpRWWVclTwQmP\nS27nQAH1mQxJhvAaK9DYi2irgpUJnx7WQIOC9EawzgB32i3FMUNxZzSjZNXre9/kvIEcYWkDge+A\nBLALSB0WWXltAvtuAKmNxCKYIUzJlltF6QmQiiArAflNS3D8Fc4IdL9p807KVozdaAW9mKzIhARp\nO2GIMYvPJJy+I2WdZ+VGu/oaDDHwtcskW5WmbYiQR8J0vJHXZARoUY4miuMiPyAlog3woGeUL71v\n3kgSSxuM3OJ3HgI+jhJvLZFmAqXme8pt3tl7MB2wIF/NsPPz3mJOhEScL4YlrfHSEEJH6SqyBrF2\nPUrbeInPyM6J1UO3p3UyKkZkwPKm11Tg6nfkslHFUvd0spn4aeJWe1IpZIcNU5nxkI5KFKsyxW/P\nlohfj/2/16qXHq9WGPPU2C7rhe99z73OXWJkwxFbGp7DxNHrG3qAZtpW02GrMaqYkBI3W8kNq8S3\nVKmdCsktg6IGc7vICnTjsc2GsWDuYx0xi893VcBnt54L9MGVIYmVBdplIfR3XQsLGXldq1+1Y7z2\nfnCwrZPeqhxrqMr0ukA7DCFeFROzKhrbGA4R0hrrQw/q/vfrufsY7LTcCpMekiNX7MxxHRNJBgyV\nX0uG4EbFrsuQWmw6aNd2Oa+ndWsnkZ1/Qzlg5nP/m3VtcDmLl+Bh0zsm5VzSGXmIZ6lbYXbC1Vsj\nqIzjOhZM0VWqEvkCoz5XJ1eirUc8kfJvou/G1fM8ad3mKKj7j5+U/cy7FHo5QF9hvTC1Q0RFyoPr\n4FRCxVmiKh4c/4GKaszu65RObJ29S/aN7iIOZ0tNtjyp/ek3VHgu31KnfH7X7kGleGXCF81tPVTJ\nXMCLNlINk/ZNBMnsF0BZm/v2nXzC4gcEoJMsp9bSQeWWeVslGFpBmuqej9lFxhYQtuzow42Wd+2i\n5wlWphfhHY6WTwUPQSNZjkEvRrsZYvf0OH+8Dr6Ob1QrHaDSR3rcM+smW2pWEytcvB9gOM3iWMP0\njFhFddu8CpAoHGHdBoGhXXHnDCUSCAqZvscWPXezrGaa6cyaX9va1l/hum08byjfdU4wgrFGYgO7\n/44xFHDMbL12FlRfbGlYq7j/ZCnvb7v4HlLVzO/lpwWdcArS7SCn/IhfGilX/zKNPTgWcCO8HZSS\nIUcGnR2jqs+XccHj/5Lhp1NhOXmcaf7fLUe9z/5wbBJ0+iE2DODoMEUSEWZ4KkN33a764ufAAo7k\nqGiUDi2igAHxe8UW2ecnHviT4vmPdAlK/xYYKyVNmcEmPsx6tRDyougusVb4KLERzf2Hqqg0urg0\n8lY7iWHsenBWJSReGFSFlzot5rW3gIyP/f/3ALEKnHnF4wwCR/kCg3Y0NmllTO+pbonpFeYCs5My\nq6npW1gGJ5+CjAX85/v83lAoecOmcpp+SIZVXn2DiBIl5riFp0csm+V2iHIe9qhUYjo0VzjdJvVC\nKCirQG/T+nlk5KqaHAZQlns0DU36FYjtA0U6zjMGik5toUfjZOACBG4hoXL9TMPh51/BcO3Lbh3N\nXHz6jxzxtvhL2VJHbd5NQjybpPJS/fWW8MqgDx9PHunn/ER9xVWQQ7fNgjTciTQQRVApwzKnx8UK\n8vPCfEVu3pbp3iX4tXvYhpkfS1S9kboPPGaAgzNgjbA8jaIshB+ajpaHpfiNKFW+UOzl2okkw9VR\nuRfUGurZITwEeiMbvY20LC+g2OBkB6RRMW1/qySqbAIehUaVw++CCu74Z0vxIsnlHkAC+UP8cBb1\ntiVRnzi3ahlfxH0kZWzD46My9DwRkMQZaiJ9tqzGEdKzFh2ckiixmC4+f2QnBXiOnMUMsFvM5ce1\n+8vJGfQY1/Eo1uS1i+avrIzrS4LZmjQvtq+XO7wQrFfghoTUmKsoOa5cA1DKf4w07V3/POK2F+cU\ntWV8JOUijogfE3hpgscbGW4uYLiNnHgsQA9OvbMICdpSxfg3nsQwQx08oJbBATP0l231H52U7Bhk\n4qRnaKInzpV1fBSoEWrpcYspk/csKPaSmRIzp/keJRCQ2ST30a5s+2hulKhk+PUP38xe5LbN7tgg\n0sjLhwlEJNyYNbY3GHb5+L1DL1aVU4G0KJTNKbB1r8rTHBcP8XZtNh1OkZ1WojMfgSkGNRQA+u9Z\n+qZ9OAISVM5JW8TfcHA7vIWqWEx+sRcottR+YnvqK9P28xtt0rsqapaJYIecOX81nmsJVPvITJQ1\nTFnQRWajieo6Tbo3XpqaC/MhSNZMRyVo6IwOmK5KpWHdq76w3vyuVKh1O1dU7fvwNRnH40AGTTBO\nvpkQfa3g4mQxyQevG8tGyL2t0B7maFnfQYOjwgzLOfvZOytBNsyVMn520jaoF6VITg4AvNVU7EDd\ntZ9mssgF+XcsOvqLdXeylPcBOF3Ag1Z2UL1dt5XieFEg+3Qy5NacY3Bmv4q3MsiY5g6OPaBsfIq3\nC9fHqTUW6vlVmU3JGAPzTolkd6XICYBmIbcxRqq1Bl6zGOD3uecShbOlKEvDnjr96sweP8kbWhHV\nkjhoz0cCtssP0GGJhui2Iob6fOf7alniLcdV6Kp0UNeJYa4tEETTb2hFs1G43ozEZdohUSyCFi3G\nIzlI8pLXMQzAhTqNUYPZ6Yq+IS87Ab/bcprjWNSIXxss6enpMIJLNpKIWdnRtm845wgwckdTrsGV\nwptAiHGdS+dw7WITp6Id8fS4WaKlZReyvjSbpi7rOzQsKroNWEsZl9CD+s2aWIecC9Xp2/95gTPr\njxAKukD05CULBOpoGF7AL08JfoD0rBR4XK+CTPg0EUWBVZ1u+SsftWgSsGLnleVvxizEu0On3Nkh\nTJP4XBRYOc401Hb/DfDQlDYzGVQPVri3NoKaKuSMpBJqHs32IlPW4b367vQMQ9T6eivoypugTPAP\nn0edlinph0fPV5EWHf4ZVB8z6ZumQCkUFFnZiChtB7IhyRz5Ndh05H2wmN8Q4tKDVZtdXJUrsXOu\nOx2NgaJ4COimBSJSYJYXNVX8nI8e3tFkx/yR0gMaXJyAj5C7WSvJC4RpfLaVkoun6UW4OeHEN/E1\nqSk1IoIVeiRP1bUe9jvIbB8srtkBh42cqapFPwTKo1TZZriKtjdNUOoAmNvsVRBYH9nTwvdevOSY\n4hnYudep5M3Dt5h9mr0RtU1zn/N2sQK352Txr9HJxMdMz9u4a9ADB8Swtj7qWtWxyUcHwnDtV4Jl\n0+BEmOSrteLGZfOO1/+FJzyCuvK0I5s0OnJVO1nvDgrqiZOVXIVSLFISrw8VzGYoB3RFr8yyAMbH\nu7wxFuHEGL1aid9izu1JEzZTpLnF64WltqMJnqWBbDSxakc0nptmKiGGTCQDn0ypCPv/u5shA/vn\nagQJ4c5bjkUV1nx7c9cP1lGsVm/07r2H4udbejlNTOIEUDlBvndNbVp94N7B7QL6hqEg/5OdtwW7\nY9PGPBVeTanNukyGCCHx6bFSDG759fm0X/MFlbyFabI+/OBsibD1it4eqAYbK7me70SotN/MP/oV\nQwaCpDQb6x2esHwrB4CVwmD2Akc1NO+t+NcaRuCow+uumlXBau2YWGWPVtwraqBbhrUNgsqxh3k9\nceItbpZMZc6ll0uXcd7Wu+UvQ/bGnwfsT8zOl5zCbMj/6FI+WHUBnWNAg7TLVuAEmol4VkQL1tSf\nWGHYqnY41Vm78l4jndLrPpK/XOm1o2hgstHUpoO5aycH13TcuSWm/NI/VKFGfnVTDXJT3dPkaIyS\nd6T+JnX0kSFDBEKc7u+UjbhLMBV8FhFt5Ho8V5mP0UmvKi2QzQqqq5zKLmPfdBAKoquUESNwwwAk\nlZqh9Ypd+0OXD5uMDLwIYesDPbSpvXC4Fxv2rY7bniwx0COc4+WAlTeMSMLIwAdoYYZqKTTczufR\nD/4fM+QQ3JOb+yvUUqc36w6j6U0uCRRtSbiDyw9bTBCQWNi/Jtek/QKJdBx2p/yVLBa2Z4nqnNpF\nfayjxRESpprStGC2X94df376fSkoanjv9S/SSRrOXVgfZrlMPgBNpAsbbIOZaP/bgbpbah36GptD\nEd8uI9KhT9p4Xotg+5bDJg7Lr+VktyEnvZkCXsVlDYdHt59DDamfkbLqxJhERv5gqg5rfPv8n+RA\nT5qXlSyjXUXd3rbT+s29NbqItEdI2PiQF7nAeApz1KfR8Cn8WadCnIIuiYu87arDzb6xATmefOB7\nhI5e1jm8FmhA+W4t4NQ6yfolYXOazgwb3s/4rg1HjkZsErUJugrcBtgY0JRi32nR6vyj8RwcE9uT\nQ0LQQ5MxEP6mK/XE70FJ1XQBOe+OoKA1JOkVlh4HKTmSlOzfXoH3ZMd7Qep2m5tZ4aCBbMk89N2s\nJKCxgGpkl+dWOOFFwB+UeSYoaOicML2Jj35MY9lAK6yv7/DAp9Pd8gDTrarh6E1Buf6fvYkb095m\nBale7lbwlRDVDEKERLD4RkzxJZ3cioegrxgJ98H15DnRlnlJEUT4AtP+7xJ/8gVckkAhNWnOD622\nT4poHPIgAH08kecGhqJBpwvto9cXh10MToMSnYTOhS0jj8FPs6Lng24FS/EY+ARqgMlDV2sDYoVO\n+JeW4KWlDiTV6NBBAyqoRYkGlt17RTB0GLdGvbtWd3ccQSOfnhKdxQ3CyuRf4b4x+Pdj5j4NaMSW\nNOTUntzUK/cWoRa5GmMVHiykDqG34ho33xNIUw3Zv0H4HShYwcRoLvxEUEASsXWGVCJI18Q7Pl7H\nAtNO8807Cu0YCJwZH3DGmFqSzlJpTVlMiNTFID738g+THzTi+ZCv0Uye6/sPKs/VFXfy+4psaR0o\n+8Uws+yLsNYxF/kCZm/poclMMhrzRapV1hxw/2F3g3IJ//LKAW5xP3rwXhFCp71E43QywnJizITJ\nAa5MrK7XL1MLg6sU1Z2U9QAM6AyctbSxR6Yk2BASRV54eX5Qcub5nD/7oCg9M4hGxkmJ7ScTTabh\nZTGgzUBEo1HdgcruMnI9eMiSyWcuSHZ338YjccwujpYHMnOwseRoQZag74IYWauDklVL7XHUo1Su\nKnf9i46O7PZ1L0BiEZpBjEpJsIe+SopKRN1SBW8/QGTTKrOn3ufiBvYEJd1jUaMPI1BrAqIwstEC\nb+3KnYH5kW95O6AHVUyTDKdLwgFqaPUtWQOEMLYcs4YO9TjTf+lOf8Ri8tKeS1FuIBo53JHO6hZP\nt24cU+CxcvXsFOIRFrO6c8J0qxNL+zfKYl3QlXcFEdSslT7T8UnZ0nEKvTdWeMpDJfZHmNhn1D6u\nuwxJ0HQRzTmdTbNtqYupXYoJRr/2qO6KCNu37OXE/hLr0I8Gw3j9Uwy/dKCTqbZFJ4q4yy/XboUV\n4TRgoJzAWka0imX6Y1Aa4KcnbA1CrIwyBKh6lSsJ2a/wt+V7zkctm9GxZoi5f4zEiG/uC4v/n/mP\ns+MAnouXnKqXAOd9kiPKqayh18VWwm9vED4Zmn6pb+XKVoiGt+oVdl9QzuCL3SaO/DU1vPmmsFdP\nDtC0tYMBVXeE2/O+KOzoqqXTtavTDiPS4hCFrONMVOjI29J9M2s8d4YhnIRBPwLLLtUIlOHFmjDJ\ns3IHqNoTcc007iQuJrceerrRECk7PHTDN9sd6QDs9wqtm9k1vXOFShaQtuNttY6F5VATaZxj6Wwo\nYbr5Sr8gWBcKYCA5qJkZeNJtsSiBWdhWXwbFu/ozbuTozB0hgvIFZ/F0gk665ID4nTDYorFpGuVb\nbsT46sWBZgFyT5MRPBv6EwD3NXKM6FkzIy+LneULKYk4wxqBoqc+07fmQ1kmEx4tikXnpU2rBJ9e\nHglCFTDB+siyDG27s64wbKxXJuKILFb6YqyRqxqHOSGEOFN9uRwm7LzGjCHIL0PA9RLI5jGa6JFi\nKrhf6WFPD4Ar7f9sIv7HBS7Xx5fnk67vpbO929bqYwGYVLx+Ytk8e0rZTxd+kqoX4IQQoedrJndD\n1uYXSxxk9vTh3KDNyGfaLnPZNuos/0z6KqNXYNKh3Bfv34YY5gwgF77FNXWpD5PSTNMSzp0zR2Rl\n2+vV0cgGKLZXDVVI0hVNImkunrCfylKogj9zKmsgvLjRe0Lwhi8GUO+47MvOlH5Id0Jd2Falsrb7\nWMvWzE5KJNragmQ2tcmCqWCyzFODN4wZMJxbb2ezNtQNEDkYfMdsheRwtkNjS4jlj8lJ79LKggXz\nwxMl5XXnQITc79WJyMuVk8GQkD9xFJnoGeRXBIWhCz2cM4UWnoAUxS0P9fSdJeJOrpsrMo0GBG9k\nvmkyq9mnNaeIHrugdXmhHe4sMDYpQYjts73gxw6Uro+NHl+Acn69A8AxYSF154sMAkjZxtBhNb+Y\nx37sDMI1tUENHFRiR5GSJrIk/6lWQSC+3CE8YBk1mKZ5tlAhveHxuf4zCDV7l39YXt3xrJSmhw93\ntb14cuzsQdkMAEIfJCaUi01oAr5QAexhYA0wnqZajXo5EgnbVm5QwCK8+4FoHqGcj/B2ex25eHet\nBOcdPnZEktlU1gBZt7OnL1ifd2hIJIHRx2dYg89wGROyMgZIK7XMLjjhXRzuxp1G+IMGoRzqXx2o\nVmzshX1xeg6GX/hipB3eLG9eThC+ACnTtRnlIb9AN1pRJdYz1yYOkMvFIMs9aWboGKio9w7y2AAm\nNqBLljOn1tRox/zFuqkAbGWEb7wjoPN2LK+5HffKvH5N6CZqegXWUFRW8c7FAdZ7A1eiA2r5AxC8\nGPUCLNuRwOxcc6vPOwjyMmj86jzrCvt8YaUFAweqTYROHE7UjJB1fwAw9XwBMIkJG1wEj3Conha6\ndTLue7r6Zs9PGzbV4onyUoG59n9oep6xdwT1Wlt5oDGBqzx6qK3YxEx/qfxaz0toxyNfzbiDAd5u\nfqxG9mA3Qg8r1brF50etdB8AQfnG9fY5zv5oRB0iw1/ByWLnhj+A2LacuYRyvY0WQT8xB71Z5c4d\nnIfU1C6sNX9hnVlbH9WEKFuna9DMXuiFBZNDAMZFTK03tZ+NchWP39DKMyhMPFmZwYhygf8Gsc+e\nygEUrUjQHR1bW3iyqU1nz5j6T8ZkvM9jl8T5O7t+ZGgwCVYFxL3eQ1u0ep5112LpLX8gvNCrnDG7\nSaqEJQfYxruURw/idNqFMA28bFcueltKeyn/Xgs44IrmY2JAhu2DBlR7hEZd9WPl2JSzOV3Zs7vD\nHmGoAfEpB5uWqonM3PHyiW18cbeMlRiFAb6IJ1L9EPQ20cBUgGAmWsRUT4EtrT++FX4E8fZrJ6Dx\nNgy1orxr0GMbFhig+AV7wrGocWW+E/GLcVZKvUd3g/lWJaAMcnDBcTDoLWDaIkeDNPyDgMNny0dw\nHMVAXYAOfi/9aai3xj/a7F6xm2aerj3GeLoe6DG2LW7R4N+6iNnjBHlyhPqfU3s1gYSl0afTDeiH\niS71x4UUoeewsSzuNhNucHd+Z0KykJZAUxzEo3DtbawEzDgPXZt5EQ+6sKwMCGeZ5GX8r2cWsIX8\neATTEi0thNqgjHax5wjf5MTs1tKFUYe0JlToiw25gmX1Uf7CjfJBczEjpoXeWZCGJhpDynRBKniG\n2X5PT0VJVfwOdpzJgRbOUcx/v8KyieJU7fR3s0wo0RqZYQLWEcxZzxoUvPmz+F+RrwkLFrAEYd+t\n/2Mb+Oer9LYnObWQP7M4lYAMdG0IjGwNpVjOciAB1PqQkqQfcOFi4veAju0C7TtamKMFduJxQmiP\nla6vBSHeBIMPgBr8Xny0vSdHW8nYN8qUPOWj/h9xUBIda2BGrWvBGzicVgeDMwNlG4GJyXuHOj4B\n/qaC8Kt0afcPO+yy1v95WjiKcTl7LyZyRdxkqnem1YvMJHZkU0ojKeeR+UYWI4iRyksFKoVqsr5L\ncO5XfZsEI/3beFwdV4hnfYSNcbT9au2cL1fQxsVql6/X3o1pLv8hEj4J2lx+O8FKdX+ZsgCwV07e\ngXzosqw7DqxmyPDEciZZ6qk/d0moVQr/QZT9aDITk+l2b+WItq9ZeoF3Fpmo/cS99dX42+DF9f09\naOK8lXiSOuJMGraIHvhAMbw4hdlXdpBzaOL1lp3yzUyIWS8hVARTgHF3QSe51BwZY+N55QD9Wd4F\nmvAMo2GXTB94NtaaSUMVWpFv81RY2TMT1Cxh6AXt52nA5RzK9YLU/DmN/bqrGRTX1mZxJHPrMjLl\nk1S2Vldi0JmcL96xik9zz8NM9+1yt1FP6782CXcOYlvQcsNSsygT3TJD8Q9wLxSQAM/YJQ9v1qH0\nhsiDdmcrp15QPXmN7BEnWEJYbkEe5MhDdu1yOv5P1KncTWNBa3dZuK6DJJVvkymsppZza3UzGJzF\n0yyTN3fJ+jeH7HU5UbdH1th45ullkWvvpF3f1NrRMcaijpQUJoN+cPAsVBhK87+iqko5d0AXkpTc\nkTeCmbYDtjHYv/hjlv8x0tMpRpMESUncjoqp6aAclXwepaTW0HGahkwlUCL3zE0Fs2BihhsvyfnW\nscwh6TdnM9dxIEU4rotLq10+ZMhN6wpm0Cf3Fd2tRp4EH26x3SfSvuq5+1jBU0/LioQb+7uJNnqs\n21n3uFBiek3zW0uRZLLW3ncQjOd9RE08BgSWJDkjim6ClKqCZQ016ol97rQ1GDzupj5cfp8ySDhJ\nG7aWYcpzxaphd4TShpLyBUnz0e7IE8RVHpk3SEIk4AvDTrlRwfamqR7KpdW2i9G5fQT/hLeHcZkZ\nVgG6AjYcUBwYlQfxEuiL/j/59luO2NdIygvbqtbBnoTHvBQf8CNR9woKKIKNblzNRtJoMVKch1Bv\nGPapsz0pinSuPeVtqefBqj5lKkB0otfeLDgzjFL5rue+MOsK/prUjJo6nKRtXBEhw9G2M4buVyJZ\n0bccZw4Ixq//1hh6gTvLi4cK1z9ZsDRe2SAXozmyoSQU60zrhPMe4b+ZEeg5nb8MJLHijsTX2TlP\n+rrDTotSTfxqJkUndqid/HyTC6ch5Z7I2QSz4qPu5V5UYFc4lG3NQN7j8NglcnZz85wWtwoo2SYw\njaWIx5Vrclriu0fm+tDFgj92u/d5A6wrygm65SHgLaUl1MuQlZzAF10oqMUy3utSwm3aaQzNkjur\ncB9yiE1ikkYy951pQw257bQ5sJy5V1DO7r9lKZWL9x1QIO7gMC77dvTc14mKc6MkdnDUFrXp8P8L\nz4ldtCzkRVd3kREGCI76Mx6pSxWyK5SyeVGpm1j94iBnO4EZwzg1xMecH7iKR8ZgRSZ+nI3oFcji\nC0SIz8/HN15w6+M1jrReVkbaao6KDPlRKnrJ+1Q/kBwUPuDRXkfUMFX7AVtE36NX8zujyfDGIRHp\niFCdffbhrQ0dl8sqC7GU+dwRQy9LfJ3AfLCQkfsjzYd8De6oRxwKN4PuY/hkyl+2AeMLDc4453Lw\npnTNap8fQSFwjmSUZAroNdZSFYYaDuGAz37LKeJ/sUi9ZXC9bJglPWjMsxU9t4i+tmSIcCmH1rZ1\nzng+W2p/jKFf+EdbTgw2+TjlmAT+OzxwEnxKuUfi37iyLD9rVip2kRyVW9bO3D6BgzIRjMRO3OZI\nSJaTek10EItMqPQQyodBCmAcxqOoYoj7PMbTLu4ps+tfpQeNj9b1z3+nhSpRbOBMk+rNTF39DWqR\nf6yDIrN5AVvR1NWAtS6JfnQo2QOgexpmja9V2u+RvY2NUhmcGojsyj/1zpaeBT8D2fFoN3BugCOo\npauKzhW2QHzZjL7CFbU8E66YquFgx5n2qsEuGx6cjT607PyiL8toURB5QwQLtwTnizz/pKXvwKVe\nB5M1M6YQ3cUIJFHpMJX8Jhod29JrxIVmuhc6m1XTeNybW13uBPyYQbcSCn+EOEhQBuEkMP21c6An\nm3/HwPCVY3DS28HP0m27JclpLSvN52fbbkG5i9k24WeonV/HmEpjhn6DQllOqphcln45xgeBTdKJ\nOcNdCfVZr/2RfOiRqUQCmpTi5IVPBcGjDEq3S7c9ngvTxsgxaF4BrI3G8efkTAbfxzbmiT+5UjLv\n6wgZQ3TAn8cjNmLj2dTa2xaYQkExL6wb6Kl9+rbtJeb11MNHEWjqmPrgGiUmTzDA40mxuQuzSkRJ\nn8+X2kjWJb/gPPRBqXql8Cax87b8JXBqtQsO6RpbeLd+Uo92RLyf8LXD4Bi6/krZTdvQeyJ9Y184\nOsD/4aaWz3gXNZjs0LxyR3ne85nePACCV7rvizP13tFBPZr+CGY+Z0H/ES5w1JvhCOBWxZBxXNmC\nZuiikmgtiB/rOSTP9Ux8z4EpysIcJHrhE4bnGuKi9k3sEEYE2L1leF1bXTpdhfC46gKucW9TObc2\nNcF/jdw7etIHps/XajOnxS2z2/+SagTRttiWFUurEIQHzsvbc6z/S7T0ddpY4dKwk8iFeGa1sB14\nP2+zo1yLia7FMxHfewfPMoyN+9vSb+BqmutR9nsoCFBRBFsCZq3SHSwC0hEpeFH1O1gkJFHptyqd\nHIg/tBtzDICTQSgUXElLpjM6MQf/90EJUiaPWp7XfR+ExG07tDsVEtc/4IYVXBuhl3+qZRYI73JT\nwGiylULoE2kVOwMn8gXDAbzgsBAVtbOXZ5lQuvuC8yba41JsO+w8oaDS0lpVKNaQ0QELoFsMynKc\n08TGrelrnNC4BRM0IMvaJkT3NDqmRER/VjiIT6H7u34z2WBvo4y4ggyMrikYH6Ib18sF3Sf9C3oZ\n6ecmNcWKlWo3+ldox2OueRalExvXwgqgCjnQb20hy71WUbaNxHBVcJ8uLDvfb7mdgBIFJ1b7goYI\nc23Kc+QMDTzMCGSFiwdGSPnllcCk0bUWzK+/sltM5USRnDtuS22kOprp3Dg9TSDszp+kcoS1hSTx\nPI1Cjw5jL9CYTYgzWQ3WdpTOFw3WFL9nJSUeG09fk4uKaiwdM7IhUGMkl8w366Lpi6zxiFuPuHoR\nLQuCbkMIQ9t/mewqvfwE+/nQ4CEIE3dG6RK62QxhBYIl4hsIGnu83jYRUN3HZWzlW9LBkzT6Tr98\n41bE715JwI0922t1kg/HkZt7d3uEVKfbEozhf9o2f/x+oWo0ePjicm0mkIKCNdQAC5ctGH8HPTzm\nZJ6/SGLiz8C28+2yMVJ6+VF4YAJBVX9J0NspMNZq9M4xVKmFiBNE9ns5/pj2MKtK36bSbDTyDwdV\nAVgm8Bl2d793jjCxhPLvdkPiQ0tz+imMMPMZo7nXohhhpBvz4EoPquKUsjV0d3PZ5rIg5FIP7jy4\nqZBeaJb5qBL/qhc9C/oJfGCi1Kh0nKMtX42dSh2AdKlxMv/NKBMjRhQnZ8i5DGGSdXc15L7ntASU\nh79muv0uFccDAq9ILx0sH3mfz/dp9IRyF93a0kFI2Kbj836S/jgst1tzUrqHsvFoQGMfI8vusydf\nXXodQ3EFIiH9njloxYlCxt8zjjSuTra0WI9c4gdZQA0aSLFKbH94Y+EILQEZ5YtfzSyHpB7AO4ik\nGtNbTGkpNmhNH2ponuRlWqbpBcx7kx7N6fCG83NIb/e3ALPE7knJ1oUbD/x4PZlywIE3sLPav0co\n65eRk6TlA870wygUJhFUBS+9xh9M9k5KuCWbVMQ84yRefkFvcgTak29Fb0mrFYfxsQOt6XQuZwcZ\nlsI3KZJ2w6L4gWTBoBFpQLtm83tDQ79vRBvPgbDW7f0qtENhFtSDqEGwYY9KjNV0Ut/ZncS9nDk2\nyT28iyTnZgb48OP5vr435Q37zFfyaQ4zqaeJmEV6+SWYDcxg7GxlujdguAxUjw9qRhmPwwPYZaz2\nfAg4NnHjw4aTzzkm4TJyGMXtQNbO9wKwy5tvOw7BFgqCF7Ui2qoQvN51m3mQaIRO/MW5almgWdp6\nATYs79Iz2SRglBkv+5lANYAROHO6pZCA1kmm+eEbnDI2EfyNY1kDSsTG25Xao1hBux5FND9RejSP\nPMr9erV/SGss85V9a3excPMg36tDjYUR9kWGIWfqrFLFjEmIiRU0uiEBXdwVCsx/fHV2RkhY/dnN\nf+Y683hJWBECjsK5LEDm+icoWK8nBPscR1yHWS6uMqaWU6PXzi81xvs904ZWXxRjgPZwoZ52aFHQ\nNf4bRD+AdxQnHRXjB5Zh/5pXOGy1VFnS4WR77LhkX2pyH/iAlBLluSdZ7aTEyQH8AdSSlshcF1sa\n1WvhDKWqpuM6/CnOfvLV9He+hXwQmvjOqRTkbj1x3g5f9ORTBp7oUGqwfxQL1cG+IyG7GhJjq/59\nC81X94vghRXNpfHLWWimRvMGLtcmJjukcUjrOTH1Cwt8snVi6ltOw7L76K0fUWwky0y3pdWJTiRB\n1g581aD8K2hgo7wVHVJH/9l/laS5mVeoZd7WAux6k0WqOO6XSCpg7cPicpoSRBLML0hovJurIraC\nhQO4QLw3vZOfE6lvBjPAU34jzGcg6rY0uzAF9nrTzwBeKecc6lmZ0ll9ROjxbd/rZzUcOVIj1Gm0\n/N5s4CNmrU9hPvdPxtcFk4XCKmyx+0Sgqi+ngC+/MEq4qQn9yPQHpIJC5cJ3zh2XP9PAtwFccaAr\nV+j3OVSBSFyqPhAjjP/jeBQiEDYu9sD8izblBjiu4JRGFWtyf+Hbhs4gm+umzYZ5fIsCMTwTOQ17\nW21H6fU6s0IyoTTx9y5D6RilW8bayei15i/SMNintI8O2o05D/XajK35XX6LRuT1rMFpbcDEO7Ut\nR/QZJW6fuz3FPGiH9McsWfTKogd3qitWk+Qq/IsI/saWvGi8gag+tP2+hXJQ6MJaV2+rh5xmcL8L\n8g53LZJn5i2z6u5XArbKOmwcxPqDRJGZN3qTIlHp7T2mGR/TSYDR6WfdsDc5IiW44Wyb7ThfTGzX\n/jsbjlzjDJJ+Geo822SPOQhEoi1+3kjtgfJY/ZigqMhalZSUBzEtz8fV+Z30+DwuDBys7WNw7B3I\neBMoOIispzecLuiOm1BkEzNbqRdr/lVI97M66xR801CUnKAs4f4oZLxXav0CERRn70UHDYQ30JNC\n9e1BpOqQK2G7NBHE7ljLYFBs/sihes2ccKVJaI9rYeET4p6aSEing8faZsD/9R4thw1uBfg6VaI8\nvwzoC5fTaI3ktXakrHzEFkwpMZ6hhmt2/jjFoXz+aCTS8CinhQwaNojYPchWOf707fmmsrKp9FFg\nW4AAtERdWQ0ERNM2vVKBkCbBYigATR9Pj9UZZ15Am3WXRbaqwJWaWrUQ0ixU88o9jaDcOuh/ZNGb\nSWtbJMoP+URFkMtc81H/3PN21vKIGtiY7ZZjek3IZiS6ID0tiWBzm1b0f+t/os6RWOqm+eTXTseA\nKhsWRrsKEQoCKtatjrkXnNBzezqWHw/qrFbsQYeBdaw2/R5qdjtQgwOyLZ8uOeQkC3LP0QGf7lgn\nsERBiiTsL7gGpFt43RbePVRLvBDMx5KtqF3F1hmOefEcToJA6/XqVxpOA3+/qDr6dvFBdd25SWTK\nHHDxtLnWIxAFE70VhD5O/Ry3SUSmRrRJnBY433VD/RUXgCDOqvBupBVjRfMJ3gQ3AAf4OZYOJA/u\nN4QOIK6cw+hqkWB6BWMyj7Vsu8lYiBzngBfHifwJbYgLFefcJuci9R2KmpG0leOYSg2+CIGO4tHZ\ndAdK2RRbYRgEisa5Xhru7NtDHxpLdUJ5GKXcMY49QlkXnWfHjEnLNqh0d+LCcaHuthcHIBiqRRdw\nFqQ+ebuUiKwPpefUuhwCQHqUROCFmaEeEwByxG7s3e1ScdpTvnaRLytqo5obmiSf3E8MrP9JsZbK\nVJTo7CWQC0Sc4olb2DN4kP5rZ0KWNcF1t//J569OXmjZUCPULnrjJCR+Lj/Ij+By7olGN726Aqks\nfMwFHhuY6LSz65rtkijpmvR38vFfJB87V+UPkwK5w6Rz0vjGRh7DlWUsHbGI3ZkXYRj9Sea14BFd\nJhmuxdfW11BN6dy3BX8fWB3s8UGVB0qgoN5eQ5r6b5IEF96USSoLyEwBsBFiWeWbBFwoMcp5v1PO\n5H6+izgpoTsXGGbHQvIuIrg9Xd9NtKK2puyDrh2BqKdlXtZ6EFhWwa6gaKX1gdYp8BPFrMDEXqjG\nyRMetG0Y6HPqAdRAkpoqIa4KuIXHLkdVUxZEpsf0Gf6qg7o4QmeLsUDQ1uBX1tW/6pfzESsvhWmP\n5NQfGcHAiRBSSYCRaEHteREpgNrtdotlNK8RAItPGnF5q+Yy9xW8NE4+csv6DibNykkpFqyCkfa2\nSzHq3rwgOvI3ArZLnTlrcYQgsNmA7gPfn/1/SQGz1lBXhWCdW5oOH4ycrjcZAT2syal9bx9Styj8\nn2MwTtXp3EZPlFW+zLh1mu+00RvIE4aLHq/dxFMrqs+h0ycB32D07gZtD+llmteK4kqjmxJ1PVnX\nFPGwcfLCaHhUv3W/NlM9+qElVMxs4h5e/2/hJoUu583IaQRPI8MSJlW7jXCVA7U5sqVpLcC+9mz8\nt5EbGJhAEjZDLPVL8GXAlGUwGmF2RuqjS/PjsDLbiQVxnejtF3VCk5eulc9lFSRuXaZissViKl9t\nXQ5gck8z25ONgcYR4NrzG+8qo8S6isSeYGL4i6dlOtMh2DQiAz4nmHz8/9NnI+NdfeQ7pqAv2NRX\ns/em+3qKonJ75sVDIJ10bLrb7DRR7czSDdgRIv71H1BmNJWKJDyruDt8FqcZ1V9wfHuxG8pqnlvE\nclkG2kPoiYTD+ftr/Lqe61BiRgy3sqMsU1657aLbkgIVXzedBKtzeRxR9CLTI0Zngtu7mqCSB6id\nhkh5QtA585//gR8RT6aU56DpfNXbrKneVOFVpUbdjY0IOtkC5xYJz0Ql98rh5qCGZUGoVSrUcHz7\n2VdxFIodb1vs3Vin2ca08EvJL4sBoMqgYFvJYrhSKzyr9rNOmSAFsFoXMqEMp5E6jR4JwhPHx/pv\nGdClwnEBYu/NlUmArgSvD/y2MqDdCRo0KDunej4lnvooArUcmJX+xReoTsWsnkGcAkvgpadiYigT\nEyLv3+oaBx01BSkHfB/6uSsQtaXN5HnxpJ/QGJQRvKFv7M6gbfhgTiLkFZXITR/mjB1lQ26ZGL7p\ngFJAICfIoWxFPEUHssfY3EVK8HaU8JDesk/dVc4JMA1//s2u0jDe7x/QnbhMgJPN4EPuF+BPm5Dy\nyW0u2TTKowdftZ4fd7Fypaz3to2Z5trRLNtP8aTt7q58W9tI3uxyboINgigvDHADDb43h0HhubQ+\nOn3d1hdFZzApCgNve4g69flgqKJYcWnsYcIPVXbdCO2fUBxWSBLkIkLVsOJJ1HnfmU1S7S2TP1aQ\n4sDl1GSQzqoUen/zH9r5xu0MyTxcL2Hh7UO6o7VxVO1/ANqdfZWpmVGd/+wT0tB6DlRB/OKmYEFY\nJ03aDfWI2xrLVI13cdyM6K09Q/xZuMQpQeIZVgLpsioehJb4YGOyO+RJf9xP13mgsSn49j2Nbt/c\nr2wAR9vs3DCLLg2lHMbMfhHvETAMZMrOODta5jPDNJU5CdOUAZxopeqx26E8vKwmSg2lhtLO/FUl\nnSW55MaEV9HUUTN+2qcNTXU9p2K2P1LSFuu+qP6tj7qeAV3dKdZPYKY83fihO2YLMrCOtaHOFAqa\nECRoxM5Lvvf3IO2m2HRCB/KImtCITWyIVtCr+oAudBdpt9GEqJ4PQRP5IapDUDlb9DkgeOp27aP0\n7NhlNOgVz6bCc5eR+yh1/4WwoK35svMX+Ql3NlwwqxLkyDUVW7FaLUkXCnoewziy+r5PtCR5FnRC\nXxpSbFlpu0NyZMPItY/sMLf0MgIyfG9eEGtcXKdSsj8GTtNxR5CcR9yGOImzRVNYptFoH03XWM5b\nnG0C3kIl8XNarP5yQ5O712wNbo1mUO9yvzabvEA5ZBSBydKNp1iQ+QWrqbW/g2BBG5vHVnoJeHsQ\n41EvxCexRAcCTx4jpmGIjek8y1MCIZqalrqaZu/9Px3VAsedQcFQ2h9ebEdpxMCeHRSk3xRmtwpy\nARGvR3dTattSQqaHKtoAp0sxHPnbLexwDsowajUlruUFGLAUAa+HuUMOzeF+/FzjQxjhScBXx22A\nLZPNmBnfjH8RTP4rUzI4vftPXfi7mhI8hHnTfC0y6fDSmPQaaqfpD/zFs/l+Db3lIuRX5xYHkKBN\n24oItfaS9SwXwI84FI2DEhBdx2ePKStRdqs53JYTn2RfsAGmjHw7sn//5lXqrhxTxbAlfLs4EEoM\neawCCfOVTeO4RfwoXyLXuABzvAoMyf9n++WRUSxhZva114+rvNCM4/bE4+Fhiy7IazfBaUkeHX9n\n8p9afp0XbXnWD7GiJI2XxJi+35IDzkLUZ7rAWWiOFqwW5RMo173brtPZxOPhWjPdhCE2dNnYTOuj\nlgg++wPqIE2ShluqgAvkasaKCSCyQhzN4Tkqzfx4rXqZQTiFnrp4vTIjz9OeFV58XPEdBj5PbXSi\nN2pvuz5anTe92IGnk4J0ioZKlBhgR/rwhMlxG6CFjtVXkAVHbVVjjMQzlT5KVZvO6rRqjxmdL9uw\n9ViRGqfpqQOn4SXiU2YO3GgKHet5nGBKj2qnW/NSZ3Qbh70PIoH3mXsHnJYRav/dvqc9am4qPNS7\n+bdID+vVMLTIp0JTJS1k9Dsrl8Kij7CVuHD2JBNGT23/w1QhFKZpYS1tdgvDaA3R5+Q3ohjrtPYZ\nBr0RVttXbxwFe7ovaoBp8EyJw9246NrW8ZoH14E+QJy4Xp+kU/0fydU8gSvEJ/NXS4E8RckTQO0r\niPIEVGoG0hgGWkTpJH1BPGu/iLrgov/c8Bn41Qa7R2iaO1f6q58xObfar65yuAugHWPh2lGx5lF+\neckeWx1ShgtINqEXtBtcwTW8HHjps9XVRXRqMEdoozpH9doJlDsquIne791xPqjQcInAVGIho4A0\nQjQ7q16ez/Htb01v+lLOh9ZYkeGd1HniGlwt9tjzASydzdIpTMlxmBwbOScemeP+gEuJJYLqfJNa\ndJY/1n94r764C0TrwERWtEfH2jhqkxGeB7jHaJHRrkwUOK7JRrdjLHRaTBRnP9z3FzxYKR0zkvbc\nCGgmk8QjsvWSlh8SuLVSfKdgDo7lDAmj0AmlI8JvynA/LckBug+oK7tZb2Zjkkk9mB8kw00dxw55\nlKj4l5TTpWcB7y1WyxIpYHmSvWUtLYVd0tHSZsU70u3XuHfODe+iVFsSpd86rx3qtpTLnnykLFYC\nczPuua3rbi44Zy9GcHuTe3hHBE7BKdt6iBP2372lu3g5+r97xd2Bra5Bo7vLH4MzrksADi6Qpayw\nOEJjtvxhPPI1kl7snXAjkWii+nmHacgBp+BFyoOzFG9B7TagCUwJPcam5wVYG1brsuHf3puXq+Br\nmvMkGuiH24Nfa25fxw5Bsrm+h34l4t9+hGd0ZZUa0kX9SJ4JOcGX2yhA0BRUfEfoEz1MyRpzOqDw\nSN29BQudhlL3YLJRpVFzhMuUxs7nDoDiRawduOsv5ooDlq7QIOPmUHoSkCsU+QeSm+tIQ5MXoSqw\n0exc/+p5yPnHFaZuB0od1KYTXQiDDc1VTwstDJiigP/7CGBlVB4uBUdyRBMZi6IQD7Jk5Dv7YSBQ\nBZTjxgUW9nGc0YxhlHw3z04h39U3Hd6SaX7GBAsU1t1HXNAppGu2pnfJHPgz4FiLH0vYlg+xI0C2\nW5l63YTsShnHrBdXJ7O2FyBeHUN0XeibF9DjmDsJSd3UInPgvFsmfmWpAF6pbmuS84dhGpddtaMr\n6TcCioZ3j9lBwU3/WDBlCdVPHGPKZKIUAvh+h8J/1jUQCg8MEyKis8D0a9cT0KZgdcpZHbkso7Y3\nOa0XugZyCVVqoy6yEL2IqPbh1ErJlWxmleQczbkbTd6nJt6q4SB77CkswO+BVUfbgu9w1I5M1Yj6\nEeh9qpeFUc3TG/N1Jt3iYfhYMfipE7PtFT2PDPGC76/C5k84NNqPg2bQEIfJk9Ieao3nZqQCqTK2\nQntHycWU9qwgN1fpw2chsHEMLsyjU8G6iXU5U864IgtsBrtw55wQoxiEssod7Mx9lOB2pYXVO8EW\n3rgBaN5Xgv4X/GSen1IEXCXu6tTy/8ChpiLEy4rUVydO2KMHXh7rcuAY1lBWaauubFlpyPaJYuNz\nHTCVo850svMqhCA/knoG51+EUscHBBKa0S6lfk2ePwDUfWChNOoeiZLTbma68Jo+KclswR3e8K+D\nvADfanXefBbX2+MEZeIZjszH0GTwyp23PmRMvjYqbCaZvkmtR7XIbUfkIdcQnq/1Is1YDt72HPgW\nZi9mA2XG9lcr7943C2h7vIDN8djKfLtP/XP3wSGSy7xAjD0YLnFVSK1buGa4NxEyi+vbLR0Jcdbm\nSLaBdUY4PcXZf/pTnOuE0aFttQuAbIYvu6D/KRPSsY6XACHS14Qok9ZU49y3y4VaZxGLk46v0m4m\nMwyIX4uAK/NlxU0WTXuyUYvCGzTOZAykxP5bTnkCMEbuL9xBDPXn9ow4yrRspglFd8hQwIYvRkOt\nxjX2IWNhbcuZvHBGuU+iuvKyeAGr5EHqj860jKDGdfUJ9cO7narYsRTRYqQ4ZD3R2CsM9sHrbLFt\nxHvnyA4iVMFwEu9uJrui15DyMiKPtLEu0E/Xy9Ef2nmAofkhUwPN5BW4PXDzOPFezlUZshmjb98h\nhT7gdW8VIcTFdqoUCgCzYhoUHk6fZsGjznefhlOYvzfihDGyKhbIePaud4gv3Hs2Slvmcu1vbDWl\nnNmqetUKwf0UE1NcBfNhlLS72uqDxi7iOPQH4jhF2G4e1dJfMbb8dW88M8tFdKGmfD2PZrtDWN91\nh1XXOh+iy0c9LB42/died2mWubSdT6FfAtMoVIjU+UzyIUd70oePSvO1pLKtdQf/wsnVSJz7P9gt\nAZitPXf7DdooE1g8XnACeQu/vtgSjs+Zug6b/jxsH+kQK/ts5KAzrDKNS60RqFZZQ5sXYMROK+3d\nuJvoxl3f2FtEOOa4mMw0NPbabnyxx7bhUCL/rodGFohYVjt09fTL1StTGPAy5IDQTz6L2Gh6Xa4B\nrcfagh7Cm+xVDWR7udxxMDcovPSD7djdqUa65haf3kou5CEa2SMnAHWjUbwHI8lBoIOb9ZnpYhR3\nFcJrOWqFj4lvz7lLZK0Y/wNEJKg527n8rfw16R3e3RigUEWHeCtQ+SIl0PQAfwCESxyhgk4aCrmS\nfK4fQGgIoQAHkQnOScef0NxOl0imZZmpaqxoI37lhbyTYYlF2O5FDmRHXBNUYQPLmFaX7F/i7VTz\nHr192oELo4zZGktWun4sKH4BUtddqEKfhXT4LE/KlFQLM2kJNheDdQ9IGOrLg2B7BSnoSGIUWKWV\nzPp2ijDtq0A6UVZdqFwnA2msxtHQEVqFaHtividlhrHBcBiCRZ+gCDqbRdTJ8dajqF3HHLB3iZhO\nSVuLJYzEPnlxVr4jEQo20VesCtJxmXSCIhv6R3CNvE4xdtRfx3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protect end_protected\n", "num_lines": 5018}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\ngazeSTBrENHvbt5mZLx18dRtoyW+Km4t51uVxxH7ZGNnmTTcoKqZyFpOrZ3w8kS9aFoiQlh5unYf\nVMD36zgB+w==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nJaIcYFxN5pqUbzepnqrpmFHdFIYWDYoimv/QCWvvIMmet78lyyCu7OmAbUWaZA7w0zL3MGnfxCUN\nn3vQGmg/2D1qvx/q2zy23sfhZfE87aSbXcNL67XF+GYu6OLKGGPH8rnW6exQAoemSF54SZgfsVR+\nZQSjSgAEtaKfNJS48WA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfa+581mCG4lxTJxvsYAMI+Y0/3DEJVi5IASCLU/HkCRmXkai01uuifj6HPVqiueReLeiWI0bzNp5\nJVlbpO/kKqg9MkQMgg1uBw2FFsg7gfVjpDJV9TVBp9Tm4YsSrWm6yWxzb6uMaHsxRa5Y+E4WUKp7\nkFXmUM1qfaMPGyGNdQg20KAvKFwwN0302/mi6GDcLvLNvvne93tcew0yQIxg/gqJlcURIlak/g5o\ntVj030iWkuj/kKp5guYfq3gEFKVEr4SV1BC/f5KX961SkhTxXGKLNLPd//Gm7akdx9a4SnpGY1Jj\ndKETnZJbnXtrvqcZUh2N1o7nl+YTs0mjObgM4A==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nQPlIuDrSSApp/O5dvtKOql3r2+lVEipJtAA3M9T5a18Cd2E2LeOe6u54LQRqvqSgFUElg4Mk3hH/\nGPHlO6wLGkc68a2QHrQWBA8YylrYUj+OZbum9kUQm5R3TPU5Wchw/mhpqWpgPlWvyK/cO9FxrB5n\nHD5ZuDk7iJeShjEmKewIRdMZqkkvQahMZk1eJ8aT2jahULqIomSMODM8v16Cxv6S3q0ohUtT2DVH\nwOkY6nsqo58T1MDDOffgorFUWVqkQwGQ/maDu/KENCo/JCJZOAmODbmBfBAsXvg7bqGZKB9VPp6h\nTMfEboGK0PjL8yhECxqeqwtqHk+eixHOqSANVQ==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nb4dHNcYwRRv3ODYilIe7aZan8VP5sGFpEcM4Sk9B84EsHlTRadyHodV0BfhfsPQB7kezG88HW5h6\nWNkuMny+KpZj54uRmnCQmrVIyZTZC+1+fpR1i46q7pc1ZFH0ByfdNqY/66Ew72bJ3bqt98VUJ+b1\nKDNSnYmqrLKj6TtcYAc=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUFVtDvwzUgfeTJK5RQPCu5bEQXOVNdg/Ctt3LMq1WwNKEczcihJ2sl86P3NdRo0ERI8ueQtux6aa\neHgbxrha+qncx9ha9CjfRUqPzzsOn3Y7i1ixq84ynt9jVyhbj9UUv8UyPbi4K5iayWqESAXrtTyL\n4izB0qPIWl4//8zsVriy5QoAxHYuCOVTFT74KhP0GfBhGq8gl2pE4gyETTs/8CEabnJ3ERkaoy22\nqOEPUjVTsxS8vgRq8tS716SKeECQKpsy4XCSTfx1d1knluz73QztnOOUXoIisTy9nHoSAbC1cRDx\n3ja7kCl2MkDQsfmBWkq0ozzVuY4qo/oIb33DVw==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nYC06/kx9685ntAX7i3acgvLk/EwgC2VW4WVhE+P9S0QST/y6VSJ0oBWMmzsdOs5O1+nblcA3DkpX\niLfXgmvlzh61Du6yn0zIyDDTLrMYWINvRbXV5FG9pLM3G/U+6fTbBV97iUYMHPWk0A2DdkXIWMP3\nmcLuMBQc2y0dm038tnqa7fuMeTcvxPhQ4wTWwHXvp54ejwq4bTAhNgyJeExmEzOvR+zWXm2VgpLp\nqcMFWAA6nlUIG5ZF4M15/u9UyutQPOLlX5+QPwfoMVi/kyC+JK5AUrviJ1QU+rzwvU3tw3rXqAgE\nsMTi8fHZ/Nt42HIXty0cXb5zEQDuP6pPBNW6XA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nHg7KeQWoQfRjpmFIAWAFbtestpXMcHBDYTZuLUSbL+kKuRGBZWT+FXknqinVcx0pJ+q5acUTBtyX\n7dcJkS4qdpYpoaBETZeL/wcOfYFz/CcO2z0+LWoGRDW3DzXn1oRWWZyJwgJkigyMIHPH5qxsjDO6\nJPKj81fkKJMHi/vC0LbmZMiKSmWL7sQNeQyH9Dn6VLxtXovGL9yVh0SoMlG0/v81wA1TX/bXmqKJ\neUvzBU070O5AHkn3Z9WRSK5S2L7x/k+ltWDFho5jtXYcevcbA/14blQqT6/9PetAyFmzvbIS+6Sy\ncJ54zu+VswtKtSOWyzlOnfx1Jgt9q/yLpCG10A==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nn/U5obQaKe7e57D8Mwxo0WeDlQ4fxz4sWCrMViskbh2tk4bDpeUf1ENBUputMkID5xX5gqlPeFYH\n/lod/5hBiFEecXymoK17ADl/jmNo1MjfVQ/nqN6xaJWL8VqmPoJ2XUvVt/nh5gTeI6QOH0BkigMy\npLFieK53VJ/5XRJXmLUeyAKMuQYF3FZPQdvCn1NDG/xTrxv61UqQKbL35Q6DuG8ZqHIJKSJFVln1\nchCHgEOHDKo7nJ9MCjYRgwBWPGvr+w4IgHNPDhatfWTGz3wjSXmjYynT7/3ZWqR/d7FCLN+lZ/ht\nr87GH/juUmy47PmZd6QhKuuc19/j3eDrwcHg8g==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25472)\n`pragma protect data_block\nrVD/wL4DHCsEfzFEf1VoQTKecFocJw604Tk0NgO7M3ODm6t/6/biD0QPzz/Fzy1UxKBEqQ8Nxpt0\nkd5dp5nyCwOVRYlAXNcBHWyWuF3ImZ0fp1y2c4napTVULuw+XU5nSbEmfo3EFsLjHWHYarc33XNE\neccwGpgfFccdUa90fp+q6imfJMIuCWHWowLNMDGdb8ZqNKZUIE8ob6W2adzfUxW6BcwKDMhYtONy\nphGaaPcir/7ub5AXgPuxZ+H/dTq9wgn1aTqOJAp1ucnPzVq3IUtg1OC2yU2vi0qMrGvEVqZa5al3\nShGeBdw/lrrv+XpB0FfkT2KARuuSvzee9a4oDMMvB9rD6SluK40ECZ1+yy9NV8VPy1Z2E7wjjpHJ\nomuIJmTDG6P4NMgl9qjKSn4GSHvEJtg8Hs/pMVAdAds6SMK+O9p7rBsB9TJ+Jfe+EKBicHLzhqUf\nYcNZCfyCtkGAWU7HcdbTu9BHbBM7GuhixBjPG1gZBzSE0WtB6MGt0YXj5LC9B2B4gUc+LuNxNcc9\nUKE7AQ6OnNorwxgTIT1j4f2lTdDpN7naMjcc0dFrzhwLEt7EYhpH25Cb1lTtbt3ny3KVcWNrvcLk\nv09yJ3wThnjJnQl+GUiERUgWu8ROGl8TiZbUBs5yecOS/BsLolr6ykQh3uUot6ZrpLggo7e2zZy4\n3svfbA7sVv+IfBOnba21zodL6jR5Io/8RZ9dAtTSxEkwNKn6woPbXr0vzkNOcXmNshPgXMNfn7kP\nhh71P3gVjrM1Z4XR2k5FHBKIFP7xvG46B9zLPPSpe9cKzJ4DSqgt0aNr031h/E4RKIrUZmmfW0JP\nOP5eFKLhkwM5x+n5EaEHSfUgoGX++y4UkfnBJWjFbVIWdkTMzBCFia7/hFiP4k87QX08uk84BfEf\nsgKGgULddxVYXIDV7mrWaO9Cy6yLEYGh6+7ZOBVM7Zy6cqp9LP7Kc0FPdoy8x9BVG6p/reTiiw1v\nNn3v32uEnt3XP6T+LoaKu/6mrF1npJimdRr7SstYkFy0LoyzKWhUHUz/VQ3iwILTJ0JnGP770FqV\nmvyHmvHBk6MZTTlNhtcVSTTwbM0lw0LvHbExAUCD9Laa09kQXtQstGMFqjckEvN2jqCALunjsEkp\nBQy8rtux02oSB0O2baktMwI571Rh+4HmnparL2+x49hG7tthybchylTgZbFDHKBCvdQBZkzVuo3Q\nj7Y3oKUrm2bmuJSbom1St7TbGFQq8d0b0kTXHL3I2ohjaio0dcvYDfVg+yWz93shEUO3Jy4PUuCC\nxhV2WTmsBi64HHIJgemiKEoZqO3e18N4F8cdUteag8hQdvF+6ZlNnZ/ms6TH575Di4UiksGkL0FR\n3sJm4AQ9V6tp6J/S+c+1flwE89qo+Xsg1/cG+L8vSsQxqyAk/ovRsYwYHiS7Yy4/606czKjJjQLN\n/Od4Z/RzSCDTe9OkRgKnHt5zK3yQjI9keM6uYHLPJND8bpBNdWrqOdAkXjDHjM3I9U6L2JJqeXVK\njIP4ArCrIq1ZHjpvCnFaxB+/+BBdYcUPUm1A5us5vUT7+x9nSm5EoMOVcMVFqrdJ27v3WAGi6+E4\nKO2C+XigT9fiGzmzXlKKtsTeS9pPq+XJ+3ohj5rZIoPhbrKxWjCzmpLqwAJ0gNd1WFfrHgE2LOe/\nH0ryLItmrp8oOSGEdzqkIi3IjIWzEJsFuNK57sg85CLkLBrD/2GAE829x/TXqmIJN9TXeNtV2gKP\nzoR4NFQendQZY0s22N8NsE4Y00GMNZhaQdHbxhimdXjmLk0d7qaq06rLRbHcsoP5Sq1QJlF2K1qR\nCGKoiuDSQoQ4Ys7EOeerLV2n/FRB2yqoN8xeHjway1HTDoAPAet9wYutlxLTBUccGt+zU65u6OaV\ns1H2YlNFqtwE716Dp39IzGvOD4w6IjA/vBYiXj/dOVHbBBfQr0u5i5m07Mu8+ql9fOGoJP2wqBln\neGByChXLhb4uLoe6Bht9vwf98nzSbRmiaYLyALBXHgZKs5L5Udkanozr2NM301M2pzP8QIPa2aQb\n64OnBA4icxCxWwz320VkF/K5BM1ObCLOipn/07v1naPYJx/9aT/ZVupp+QL9cBnPp8LZtldMFsxi\nZojdTH/u0pOw8jx+SH84VqjOEloFoTxTXkAMHKRulU7yj7ZmWlEviMhxT+f63SOqtMW6bd8ndq86\nbFiDcjGNkZC4YUerGzbOM6M+me6Qe5RcwL5VJARilQoyPMlPtvzSwMzUJQyUmabaCEispxMMZ3QX\ndNb4c+W7FDY4fxsytOmuPwhCZS3ytA1vCB92ukP2KVeOien0DKc4mIwjdBllzW9+QN+GNSzRe5LN\n/YyvlmAWUmlNSB8smtrpmB84JVKlWaXOOrpOLxRHtFaYpnmpmXJcNveKAB4LMvGTHJdEDlR6LZ5n\nCgWcU34eHvwxJ0N7D9kxlxL15EDsPFjxeT/vykJmOvcwVPmia0M2nwFaolKZW5cm0pZvf3bzkkBt\nkxFF4vDu3VKJBPN1qqR6ngJ8w5cII2VcSG+TZBxeAg/XH5mW1JuetQkNdLK940Rk85qvx9Z5tYFu\nFKrDM/P9zlRri+ggEpi73JzEUnuwXVzjIe4bn+BCJz+SYBKbr3OlasPo2GXinaCm5ZjGwKSqBbnw\nJNQvpJstSIPLThwNEK3IT7qyWtVrGoCDNiYO4H+x3es6P4VqLqh4r/0++vkRSTM4Ov8V4lO1aK+/\na/Wba1G4sbX+xCKKd66y0Rr3rr77pOo7IC0W9booS++rNRLvt64SbPyun/PqLmZi9rwotRAJRA4k\n7TXOcgtq4Ki6pKRKU7oKP5pQXRmGEVr/qGRqcX/IFcGkvR76WQxcFoASm0Yj/3Xu7bvEHJDX02tK\n4cAJxbC+4JkeI2Yc4e6V27wCtFNv8VAnJEAIJxM8w8Y+uK3Wdth00+HnMr/teyh9PAFI23BCDQ8k\nP3/TGEk+2X9AelM3jnJ1cx55xK7Y/PsWkiPKyUozhHYOyR4SaETBIxAtZ3ttpyHm7JPgipayDsI8\n7gYw9SePFZFjYEZhCtfrBAzTmKhxEJ4BYA2Yq5/1Djk3dqr1Y7XDyyIaLjVim9C05XBvKk/3JjmK\no/4wBHIRPWEui8ORGTOUvziQUj+FDTHjthpKosRq4PYd0gugZGbbhdlEj9IDDCDNxkVM9Xyk3ytf\nEqvvgLtYOih3D2Pq4LqFEqHahfAKS8ugstEsKmEWOeBnP50FSppoksT7QdPuZ9PWlAatvnkJv763\n5BXALS8jMNlPIJvelWHd2qCx6OhCgLmUmRPNd7LCMMydqv2c9uA7voFh6jp9JGAvPu53dzjWz83r\ncFeBSw11OeeiKRsJaiHddsq8L7nMEeMcZshhvcS5y26j+2tp1zr6sVBFicGgokYH1CKTQFIpiTib\nXPL5vAVDlvFDdaC5VNkFNCs76Bou5yWCTAwG2DcN88BLMV7QS7M/iGZSbCw8JV01LKDRqeheVsxP\njaLYS5XkKHDpYtsCzcVvCn6u+nDFLOLhz20cYL4vxwmt1pMKikYG15ONmScVDm5/xQBKe7nWsOKz\nSN1w6zj36KQ/C80gFY0GXtFZkG2CqAMt0M3uDfWx3VKuW6ObJNUb3R0TpZri4OwLbrrUpL5UT8yt\nITdov+Beft7qZpxoMu9KLHhncLx4TJH0gBzyTVfAPg4ljeaBsL7cmVfDmZ1PxNBQWN2/Ms5XhA42\nF3BDbS8YdOU8JUxHPgD9tCaXHqmt/co4uhm7Qtmm+DeDE3O6ljX5zbblXhS0345LHi4MFfhCkb81\nJ5XdY0hze86Ye/grd4KM1+hLV49/08mXyM5oQSWFRPGDY5ivO4n9anEwslLWZ2OKFvXtW0ZjW0tT\nRXEjOIOyE8jyr36AQDMI1LnOl15xPMnKxb/u3VpCatxnNlgTk/jzmFAD36PDOdzIPJr58KDGvKFS\nG18BSpcfrx+8cPWzVMM9M9Xk88D3Mxb+hWAv6UC/efp1x3+Hvihd9zDuubo8/FLjegZC0fa3een9\ndOTgEIsRfcfWWWdtQEDcPKuUn7WhoHt0SvpvO5dTcLaAmCPwcROmaH0teqy1XjMnZYp+sKIWZe7h\naa/hTWP68T4UHeFB8IDD9md4MZDlB/L2ac5XlcVY7UmN/GXG3pc7Gbc6uN0CzGUQcYa/v04G+11h\nT8nRzZQJdZlq0lH1U8k7gR7YudvLKtUfLHu1xmyJshSEKbRWUUdGRnwfJUm+3jGXNSoyoDu4eVa0\nmvh2E9+h8tpc6Hdxbe0/dRAb6sSYseeMuPA07z/+SsPa5oJMBS4zBtxgDX7xBkPmnOmMnJAKzWdI\n2/zXRzhP8OaEODsQLJm6++pIgkkHCqOGr6GeXrHTdMP3idL7UslwV4Lad1r2Y9+61kW7fcGSJ1KP\nG39vh0sAfFWWeb9d5TVQgwz+KIoe74xDJPYPPSkVl5kx3YFKk6vty4CYAB+5DVSd9bLaBnJ4/6l1\nJ76KqFbRsqIPDPWm7OcGTLW7JIMmU/Ofpv4nidkb4LPNVbPMfVS+Z32QG6FXVhOpIqgiKe8BfVka\nxk1jg5/fA0RQ/P5VlZhWUzEHywD2+khTh9xwSLldzJ30El7YZ++yRrsgkGW93hRzZdx/r1YMGGS/\nQBmRuRM3FKMkS0svshNKaNg8DySBg+q2X6Ky9IjA3dznU49GnthwMKhx58ThDxQ+szVA0MrLc0o9\n+rEmk+wXvMx1gpwkFLsJocOcBtoyq3atxI33E/X4g0N1mdf0f7XCxqKCPRyQfjfDQQv222kEzPfK\no/j6pJzL/bq2QCtQD62ViO655dAFs1zzuPSuwrN0eWO5sKLw4bi9ekjxE61AGmPACWDjdfaFWJ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dNrJi4eDjTX7egADR1lPi7IHJnaNzULLyzuO3tY20xdNoS1WZ9Cd6zJ3177q62zFD9IqW5Lu\nqwbBMBn9Srz8L15/PmeO818lgnRA+Obqkway5NlS5ktpFQ+pamj3jyYU+gi61IJh4yOrdmG+0YNr\nYFfUfUywA+Vb0DyVlm6VO+PiHnezjyvHEOcYEa8umdPJ9zJG7DIv0F2B2RqLChYKcamD2eAeDTbH\nfV0/YaWwv1GhQ+Ao8z4mbGlH71ah+UI4VMNU5k94werdUcmCZDFEnscd9SO86QRSF05j+ffi1CCi\nv+ySBxYK9APjuLQjNVrNKkjo3sgO/wtZFTimlVD9eKKZO3oJ+8ImII4d0IrCjHSBC0BNLtUvbme9\nmUJX8cvZmqs02dF+ATX/gcguP3DCUJDAUSvbg94oU5zILWF5KshRjRmpg3/63m3Mqua565kXaXW0\nqSB075zLeZeUTxd874xUJdwhzrCH1TkgjtNBULzc+e1zgGneUDlKpF7+GM3E4g2yPDntlKDSV4tq\nZg/J9yLjn1WZ+g3OXJp3EuqNpixt4tWc7g4zpFD+6PkEQHyikmzegOPhSHkmz2B78XcqHnVlVRT6\nu+h8+OajG4S+2zUQ2+y9ii2QR22KHBEnoriSV0FkkgCt9aEB2YKRRKtPBMXtQpeLYxm70Z3gLSUA\nW29k0A/vnaVEOuEOlY/jqfFKbKb1K4q9aVjX+++COWTPhV5kly9w8ujzb69MbaQWfX7p+PvJCGyF\nTwCS/7D3fUAjuzGmkdfDhZccW80v40olYz+LXAUl7tUuByKyy15G+0BKB5YEi6hGFv6lEz3GSGxe\n8/uUmYAPkJ1u1STOydIjaaYXqD83ZO/ZOVEKqhVutfVl2hSHLzYw6/gUFpFcMwZWXX5eOGNLl2/T\nFF4MzK6u9+0KXGdOAvATi0btUYD6QYMM1f5b1kBWZjJcC1//GBYKhkVUuwduwTVT6aj/2wzH5gz7\nQ8qEmTw4zYRBtJXQgOs/voolLCe3EfZEyqm2uQ/r1PchYuV1+d7io3uQFszexWSuf/eYepqWnq/v\nz2Gz7GegP8v46bRpzZKV61eoGO59seLhOTjvp7L/gdDO8xjlrHxYtOpMrNrj06dtbzUUacmPBceR\nd/N3VW3ovm04JbtMLrbwXdgY4PIFgeC5ldjlU2bnibhXKkE2/MjYx8B5HonlmJU3YGnjfnMzuVhi\nsfVEj1uJaRWKiNw0ZAITwD1bMfhDZShTe0WQqn6LrI1/UH5oUhqovpbWw70bz+ENp+D4TDwsZS0s\nSpmlHT0fP8DbRP044UI6dumqUBh6K1XNWgERFQD7UXK8EUV+Idp/rnr1NbNDOlaD0+dhG+p4Id+F\niQe8It9F8OXKRtsV/b7VJ70PE+RuIgrdPemrpm67UkBWnBSKixKvX9kJd4ecWPpr0hHeiPZFRA8U\nD+ACqk7FL3Q4yr05PC//O0H2Vym+cbqKruXPHgWLbH9CI9zSMFo/j+Fq7Aq+EDCG58e6G9X+bmFP\nH/5XNkvZhbeggLK+WQr8H9GQIZLZMQCboRvhX9u+eUuhUUvRU9gwFbtDrSz8K8kJBMzb8blG5UwM\nC2N2y41I2+paR+I2m5hEXkKM9tXl7VclIQIsYF6NoNH3ncc1x4HOPwxgUUR36L2amu/bzBn8MXVJ\nftczkKFdZiYMB5xIcDLovipakJFSH/w2xu6WVXWMOiA5kvgUvu+hbbVi6sHkQNFHYKIAjobH3q+3\nDrc09phW+ROYO+aTcQbKrIjZd71OhsV5rzwZ2JQ7ki7NSzGWrG6x8vZodBDEMCl2MIjkqJ+PHIov\ngo1cRx+oS/5Dae9iXLZjx04CKFNUWUSPyHHrfbNDyOPrdvGCTFr/67j/rGj1J8vVNCxtLm1bEQpc\nSIhvaUaLDRXNEjLHerJ79+3XQHd7IqCcBLemBhPmU+/fiAWJozadBEb+HGZqlMPDNzwkut2l43PB\n24M9Sj7odg/0kwUb+nkDDFoZdwlMwRh+gKg8uvy1/fK1j0sJaMju2Livjx2dKdE1F0GLrtHWI04A\nauTXE9SM5DeEDogTpQeQZPSjlINIteGYpH+oQKh9ZNsv/7z+zVFuvjSsLxXZy0AmwKADhVa+Xh1q\nPOrIzFEtf3FEPdGmEyelpCcZbjgkSf1KggQSt4O4YkgNwswY8tEBLIDAXDQExIjCYv/AIeVtzzzl\n+gKWU0UQjKYMVQCWH9zUlHQz8rQcLCB8EgUlMKDsQVoRJbvQR365CNfAX3W8rMVy4nTztqh7zU8Y\npTMGjwCCnBVie6sRytRY79AmqVpgvBPcuQdAMszg+wqIOS/YOXfWuVWaAHwDpxw6UNFMhWcFKSOH\n05VPD72EbnrzamjHK7JEkayKLgR8VVQaXYvT1jVmwbJ6/f9Gfy8CZaZuJJhKPAbeo8mMHuGWa9HL\nA8hVOZll51JKNbAGr5wPKjPHhfBCcWJqs7VIW00Fms/7xNFGllj/SZtUXSzpO/+2FCnmtjO36lw7\nuBLmHLf7CfjRZYUEgQLNVQA07zta/IkjSnwAojzCOOGiriJKJh6Xxrq7QrpLKKMpwb75V+Bf7UIq\nXCrPo45BCxCLgZ/361L4yE1xbmngU707NlaRF24SuFTe7juhvITEAy3wY6U7A7XsGp1GhBBNaYzx\n63YNFYggmHPw2SyXoCLq+pVuz+tvr1PMqnV3zzb1XvR/5Y4Tsp3bIfi00nNB+tv7WU3mCiKl+KDn\nWulilfdt2qcMkdt7dtmcPpClSu9KfkwSQANc0ehkxDHMf0CT2X361QRvY1BiIqs5wfHnQurPZVvW\nIHViiyTAS3AZ/VOpqQJ9UeATGNz/qAOHlu4l0AAE6xdtAPmQ/ccoAbLOCtCJRlTP4bk+mK/UXsj4\nG5Fs43hzF3JxJ4LR9C2FvUvkNnM4hsoGeWg5/PI3h1hXU7vUZJWEgYReDK1L7mkquUjzkWOBvs/Z\ndZTkag4LuLtNIBkAuT8lMHzT6gfGfl8FX5+8nSILKBx072cjdYwUpvNqyRE2Z/RnolUwJalgqWFb\njwYgWT1LgrAf9zDNpkiBuskNgatldY/dyAyHZ8aoMboKqqPiZMkqJKavv+FSK4leOWqG8/2gaZke\nxNn4gg7BPj+xor4DbD81mH/cZ6YSEZbXxAo5ynx3BpP6mXWX3Q9BVYMbSPDKd5LP/sL+FLO4lhXe\nHGsXA3ZwJficyeFbwqcUF4WXXjftNC8xtQgoYUdMYTmtiO2Wko7wUYf5VzXvf3iAJh6h+ii7bnNk\nQD8LnpXLyWkBAxCxXLS439nKagcl9eGoV9S59YSrP18BCUxHteCTtVutmEwT40IhND3eY4xiK2gJ\n1mJGaWYTHkCq+0qg0+pobyEVhuMvAbp+hax+P5gFIK4xkXaUrJY/rnaXTMMpPlU/ew3xGKHRD6Rn\naz43KtCgy0a0LgYTDuQkkWgfEbeC3Qc3rv1tAYrQoiVSwPN1Ppmyb500ZaLxhfGyslQtV6Cj8IKf\ncHcbEG1SU/vgXR+I/iJitzfGYck2dBP6Hc9bkQiJgCaJyzVJKT2nLPrMra+TZpxLjAf8bfzTaIR7\nyBzAM1+ONLzI4NZwoabqZphQMBeLgkvRZ4iutHq9/65XXwPhJ9rawATImQizNXIWZ/Xc/dBdeYci\ncXlh4cNi9lXr86kv42EtzQO8wiXxvpJNllzagqcYzoDS/2+v9gDA81y/sHczLBSXich8fCL9sHnk\n5HEPy+MWeoxHTXzk4NVKhoDg310u7DNHN/iqdC9jowVF45NxlX5xEGTagsxET2kbWxiMiA+l/seJ\n6hm9WQ5oT/E2yZHcl+/+7WtuGZN65uRALxVa5/5f/aiPVjAc+nbCopYK6mlCZQ1fe6EPe8V6UAwu\nmK6Uxk5h9aHjCoxyl5jtUOUpA3Z2E0IY5HjWDUmo2bW13KxWLnEpTdxtgduawTSy7y1brrIDV9Ou\nthZNeteFd9ZEFakDiqLVxSlFcVeSaMOlBtkUpVqZgEIwE4RUExVbKFs+H5eWDhOO8OZe9cSg9acu\nYYhr68IKC7t9VpDYX5OOgNcj2vxcsNVFwYRGOiq0HeDo2RS36LOmkhoHKBwolhA0gBjZd70RygkT\ne+ujgmuAfYLnTYLZ2nHTE2bGOp0zk1L9xPoBXxIvdp+k5T53k9MUi7R5IRINuNmzr5bC5Qfp1foo\nokZfB1U6tHv1oEOoThzFFHi5MhTQsKEn/ks7GCTg2bAFKYJNuuE7GjA61F1+6Pfp7NPIjUwbK7bN\nTlw/pFPKgsPwRciluwLrUwG/LcAxhFFcg+lpOR6KrBVha2FXaGyrxGufH4oJo5wlwekT/MUb5pmW\nZJgQFHqzjiiXpwW275Qpn8xplJiwEhsVfRYaQIzC5HzBQtBD0Z5xnctY48i77DbgIyL0hIwb/9pW\nQhRC7/N0v7qdT27P0pl+jumTiuNVZta8YTC7G0xouZu+vXxOvE/NO0wbDODHNploJXlfweCV1oyP\nI1N1H5/jXLW0L2eiuCupnTrqSGPbGlL5ABfwLqaZsT5pSY34+77u60VZWbsIexLeWmMfjCRnwqdW\nlazA/KsFkNe9O1U2719btMuPKm+/4TvoYxbpn1POEQsMuuwf9Pu5ujFjLAJq7KtmxM83P+hUfwbr\nG2G0JYCgS4d2fxUgAQiic7SD6J+PBgVi9fHwO7v/rbC/r7wgRKqfvQmlWmB1raUV5e7qFyPgMl91\nDb8DOYHV7Rpd6qEz88xkcQTRT4wIs2PzJ7zBQmRJXb+XbWW88jQEJVpOwGMGWqG33QS7T/CszEl2\n8G/UzSnCH9i0fIkX5bB8hX1jdnr9OkaiXmXu43+ixOyLIbZDRN2aRFEU4bczxAuR5mDXA3WX1DWF\n1LMX3PBCA3DIdqjhKv1+o7MLR+9Hree79XghCuZgtetNgzE+BgpYsP/L+wq4AzZceo2gx/0A3Ad2\nJHE71pWJ/OStHuQFDk7oCr02NKijAhZT/5I73DLzWpVMrpPwG0706DOFl5+bko+2xhL+vKkL4s9G\n43sC21ZYXx40qplG+nB4fhtMI7Lx12xMc6QgJO/DJGJbPIp5sPUk5yZyzFSb6vxhQcGKzF0jRKk2\nblj8QeOpzwmj2vNpKnM80a3UxpPiqfN7qiNdQV/oGE4utr7yunmZfyhLjo/uE0vfzSjmvB87f5Xq\nlSz9CuGzxhmVUGtT60TctfVAGIWcvXELEXV9HRvbEvzJ/XxlarWtZBkumvhDxv+H3/qxTBYBB3VL\nEE7GwzXzsRqrfwK5sZNZBrnzd+XIfp91Cnc96mK+7oU/+LV+A6NtqwEEdxNXA9EK6BlqTOYrfmNU\nUAyIzodRgP4dyJKUwF0WnCNbwi+WgWfKxeD6J6U5fRGoUSwKaIxOmNvBMgeSQ2eA+671h0YMe4NP\nqggDfVx9cXGcpytVWFntnxs6aQPg4qSpVOZkJHP2/oUPTaeW/+Hvyja+m3VTiajRHS+lfWABSwkq\n7pRAbCjzIbKeOM6sY4W63453Ewo296f3xh5ZY65u0scQgUyXtB48n3211e4tIIKNN/AwXo08/bhL\n8gThWAG9WhH2kzkFX3M7AZm47XgemDZnxChGhAXlif7chETEzzJtM8Ytn6zgg/ph9GV3i/Z6aun0\nmrCG0LMtrg4CJo+4mHmQUG27Gtd/PIm9eqWdt4ywk02K4gGJ67YvXnm+EhJHkApngBbKhp+I52ee\nZtUw0Li4xW6bs49i2dOUAjx86jsKeU7uJiWkirUvQ+aK37MPYTPcfME8nYmJNlOwZWzbVKfm00HL\nk0qmK6iDSmL/DSdx9VnPtGsNRFDgI1hAkSsqoGO2mCxxCyfAc48cWKxErLRoVWoO8VSl834ogKht\noeVK58ezIAHphOWtGVwz6GZwBiIy//1koxIMb3oR/qvXYhyucGPrvWOoGAHfpFsQPqwrb+rEKn03\nScU9PlrRZFhZOONC3GwM8Pssp2AOJT6RI+RXmNsMX2QRDtwDnC4vmHwen9MePiN3F/jppJhwA8RW\n/Rm1C2FX8ODUUj/mJU2oyh2u1HV75vH1uvUNFzDmB27k9IBiPpU0jjvuSXAJRPkzve4rYPV9xTL8\nfvi3Vtkjj6ahvzGVcsAVgAX4iWHLuRCHlAmMaXvPjURqSCU6XRgDTx1ia0CoytuL3y2O+KSUqBEK\nUqmtax5Wn+VzUtROS462rJdrp3YARn//1bxpXyg/j1/juWv0yJPQgUYcU3d3JuYIp8Q8jjoVodhn\nP1QPd79DXNB/Pwd711DNxOb0sk8yEPXHXc1Xcnnuz7a1WrYqeU+Ww/PpVga/3biOfdSOi339aWgB\nfndekDI0qMl0s9pWT+9CPjkyL0nbVWARb/uVgNpjHNmro4Nbj0HpFXKX9fwsBDeBmD2lgBrmbKj6\nbdRKGMZutn+k3xVU2uNfdFPeVpbC5lod/2xvC8Ful+0xSpTdyyvsUgfPwPgPtL/SOrLFT0nutxzZ\nkz8gjdMQ4dFDPg5YoKfi+ICV/qlSloXDse3ooI5N1ZuDqcKdcXjzm46vsfHbCZCzGxIgo+W3tT29\nAKYT0/xSqJTbX1kkMmCMOiQqCfGf29k8J1SaP1lrOC5l1AA8nrKBjm3OvciG8hf+5r02GNnwBp8Z\nZDCjx/Atsr+9LAHvecc6HiHJPuNCINcP5TLiSfF0jgcdsQm3869+RWCQUX5yLZWiVCpuQxFzPLPm\n9mjy+MRdZRDrfpkdPkHapHE3kPmPVWQXDTnhLYOgE4vdcljB4tWrpeCNm+JgRQ03G+v+wSPN9TYb\nrwX2GUhJoR/ax47EWPbYauv7LNZ2bJGfOb9s/o8KYw68eXkgj+FDljZzzP0dKUQqYjNgIw2TGCxY\ngcJ7cxv8BTZJ/JTxk7ZL577zd1AInIq0wuKBFqp2t/9tMsxSXegD0PLlzMB2fDYVGmncDtT4PzlE\nozcuiUJRipjY6DoesJlfHKyxNqJNNxjDOW3SjMiKtI8JtSQNH0BSyrRIyGNGXzX/uQArTH65IiPY\nkbNFkh5LMdN5Wn42QqnWV583GGVqmNlGzHkdprd4C+xMN4kkWbjaJVSDHQGeVbUdqT7K6j1Sa/gY\nKGZmys+BhBpakUrOXa2ouadrpwLjtjwhGHVq+zFPcxNyMBIuT43rLb116BwmRtaHmmQRa1Y9fgPg\n7LWLlkhNqEKOAPWFDQUuPpJqYr94vCP0A9arjsxYSzLkGGUsYf0r35nsW4eRMZjFyywzOyktfHup\nchvurg5EDDibgz8QtOdlGNqjerLNTRx+XGEqla27/jSiw8H1kgGrPDAeYsfAVs5y2+3WJNAsw9hT\nZzFM8t/CCIgXX2pj4yrJxSskmH6QjRspvr+VxbpVgFbgSKw/l1lDbmJDDPgX89Wmo0Bog+C8R21R\nqseSnoWZu17XsTWPMkOBeLmus/g7Aw7CMHMIYuQ4A4cJu9j0Gc6RVLvud7iLe2FMoSn0HdrObS/v\nRUAkfW832KW7aEdntoOLUdjtzOQ5QKD8YnNfz4LAzm3OhInLz/DshGnUdxR3EAL159zxjVlLZKGK\nElxu0aK5Jr8coyzWWtm+4HX92C+Qb5vXEXsmqRgIZoQPp5RpRukTUGg4zq4uAWspaTKNzxxlIEYI\npM4B/sIKkQ7sHptRAgZ/K8sDCJolRdeda8ln2ywDEJkz2nu1Kw0jm/+XghX8j1SIOG0qWiz6/Ybc\nzdbJO4Plp4J+X39ZxONVdiGg1EbaJ8UYFl+7inGY0c+VUCclN6lhgWULVKgp0ZbB3yLpKvdDBKgD\n7ZPXHoHemwi+R5aEY7fxs2S9MQcCvo7n2z8hTeHWb+DA5zq8/x/8eWhaI77HZ3DTvtkC2mVsiImR\nwjAkfk0z5JHXQ10Dqdwey7NVkAHLKwgXQG7SZFqrdI2PQV9HHw8bn3m6P+f7/EAy4MkYv8OHlwCg\nAz44PcpP9zXgPo5kl094cZivvFVVOC9A14EHv5xaRJSbue3ckHwAaVgXMonasMWqzQXHHWB4pM/2\nzq4cgM+X11VuzcRfROlRKdmu9umzZJq3sAFpM5xM4oyWtBLLHCdk+kmOffwThUPQcFT6Cp9se2Wv\nBQ3DldAMEtZ/j40qXaVivpsdHisEwN5FZQdxBMQqzZaP4UxldJ4xWKA3n61Muv4KIfoUKajddLuS\nZ5bqFL3zAkvxOf3JPUroU3wJfi2PGRcFmrNSWgp7VEHsWiBw//1PEbEYYXNzlCG322IbiY2RL6iR\nA7vI7/83fM4uY75AhDlBhuQHcEG1mL/9OfaC8TOhJiCwn2ByChDEFZhloTgtP/ZWa3aVGajOfbb2\n9X2Q7O2fzO9lBbF49OOnRLGTGH3jggbIELpZYfUF2wHdMdRJa3vJce8DTqVv771jzqUjE+fnwOv1\n269F8crvbc0cn13uXMkAyw1nN0wpG1H9l1P6jnVhrYq74DkOPEjkiK4unQKlx0aZI/YIHcAfszVM\nY0VIC2djUXZXrZlW3Y4bUmtoO4kMwI/iMgrYuA2cnHULO79HXnYXhrsdAAv9xYSiCAVQv1w7trDt\nXOmMVGvsc7eY3BpFegOKEqPqYIb5cwa75vy47XFo1zUtjPohgZ/g+MCSwqRz13l5N9vQlFSUL857\nRIPEeotyNTAsdh3vFX/jYfsonxch698ZbFLAAZ2uagiQ4oDuMeZpgeUnzcsT64lJa8GhO9cVASuE\ny0F6GpshZvVOe791qrdIB+EJ+FSESXq7IBlZ7u8nKzT3vwJbAFCmo2FIPqzBzR6n3aAQnYVuJIKN\n5Sg85UzY90qoBTGnu7wz2Z8lnZ8kGtpDSDOGhDFHBOGL1+xytbC3IeWxpkSUppE4dMh3UBtUpQpc\nrznsPHtwQusNoU5UHNl+ro08V1FXkHUs3BGo7cjO1E5mEsXECd0Yh+x/PAAC2sove1R0oZM6sGqv\n+cCCB7Vc9Az/Ei+rKcaQ7/cztvAERpeXYbhXrHeIwzJOeo6SllZ6eWAU0t9Umj75FZpWqfPlVngg\nxspwNQyDQ+pzoelgqX6CDTSoJJVBX6ypQoRpbQK004AUM2ODfMQeGrXJroVW7Dn/UvFzPHrPglZC\nHQmAG7G0MAv1OywENidA/tXzqhJYQ8VCtT2y/tKc3sh+T2PofUFs/sXPkTtUY9ALHm3DeX3H4CQP\n3Rb+ibBMospJV/C4wY8lXWgxxVCfBnLgO5r4RdQZ9iG+D+jNnqOzIsmOWgzNE+mbRYtKgPjmCs5w\nkpDjZCTmayxeTJBGAHsyCqnJxUhm0lia66LtCTkMcuB6j6i35CZ97kDpwIOi7AutER7n7lPH++Gn\nm3D321MZdm8kTkBVzTPhrnCA4JFEy+muDff1jfJIYuipA9VLqGCgficM2pPxl5PAt10RYCFRIczP\nImS8vQ89vm3/mEJLxVdbhKLSSIOUe0SyhbZ2qI77n7Pds4qv2SY5jt+R+iIhRASw7/v/kNYUxdiU\nd2whz+3cp4AylBxKxxEOrtr+SEwv9Onfj3IHTQtGHr7vZ7YgYe0YTvUebilhEDptwX6Bk4wHVH18\nELtY4IKlOENXltTlk4Fmfj2DWrqzrYwE27mXmVsBkrge382vltAomA/zHyDmmVAR9fSNI8kJqPv9\nBf0kt+ri0IU1ZZg9Woj0aa6yJritF6/2sxQwnu7hDud4nxN6agLEuHlhB37LbdL4HSPtvvRyQBEA\neetF5eYD5jUT+9nAbGZ+gGiyc7is+4wBcp5djCDST+xp/aqAUweRDNoGPk9chJw7tOrYGAsiLigf\nXAdVxBdEHR7w35WoJZOKR/ohU4uVHNlLcsqfPX8Dvr6UBD0lPGmwIq2vqjVCbdb7t6yILuEq9Ufm\nMGfARBYUMcz0CLCaO6fMddLXYb3+7JNc6BfgeNNs4c+og1l/7cS5kyAZ7etGCS4NmxOe8lgxHUWw\n8IO0tvTl6ukkA/6HFwXkZ0AbJcHifOFomjCv7anv2hOfuO9oEeFpp3WDj12n2Td+ZsWkf1AmoukR\neHaSxklqdCPcEI+UKHxQLNyr8pAOYswoRRGZbIqYW/ta17ZpL5ObFe7L0dnkTerzaK6+7QuQcXN4\nPEGg/nZtybL619pmNPfMj7PZjzIQeW/8N19FXPNLpPAoVClkPHG4Jw2tWKC4w+NgfUpUZJV5/oLG\nE0Qzbcl2mu8ISb5O1UcRkK4QStBrSta2QNvkxAkqOMW/jbQTViSnlFGnQPa3JBnvZ5xx8kSZDoL4\nzRzW+5sj6EamucW1FGMHEcaRnfoI9HYpQXf/8IyKuWe1UyYuhDL/2GkuQjpJTaIy21kze3sprXk6\nwpt1QJZ0Edtv5/8ks9db7hw2IbtXZBpSZpvE9ugD0lLiq5rPGhEahktiI7dZ3qbKT0bTXgXhrq9q\nSUMqwZoXaG/OkXvzEGInn5k3AP8V71EZfoxn5fn/UOuomkWmITLVKtg7tWd1LyrVbmJiZZFDZ7qI\np/XN53yVoQSXwoT4AshECVSbN/qX2+Qwu9Li7N8ET6x0aZ5qsJoEZr2yW2YVjQfbzCQy2cyj06/R\nMr7wwHXXa9rwr8iPvJZqmheEb7Y0AT8RjFFkICCE3TaRpLpc5GXvlm30aMqecTG2WVjbcnNiR+4F\n/C2wlDxRVm2bYvBdaKYVpicEjIE4yUAuMM8LkISEeRh569nRfVlQvmBwU9/WwXT3Ti/9jnbnlYvr\n+Ahjwb2/qNZd5qdcZoIm53BHEPFH6Vq1H/Gh/kzAJKdFN/PoXZKFLX463Mi70+9jrOYA1OiCHndK\no3zf7txPRp00vR2xJpj4unJbmpT4ffdThfuCSmKXRBTTZrgzY9yS6ftKCkee51Ztt+U6nPNlUpAN\nllyRhHkTPq060dxFuYOAoh9z58j+mdFB8eni0jqIqTlySXsVysNMX8AEngW2l89h7oV7E6W3Cthj\nLMSiKmG2/uMLyVm+c2btxBH1BiQRhQ1Rv9q39KwMbuGrzU1o1P3FtPG5HSsyJGmJtp6rDaNiiwxb\npFvHTWhTiDlj/0drNkTzFhG1JwaNzt0kOuewsLPdSir3uklbO6ecYaPK8Z4jgXerghf6lEyknZLS\nAYkKYA3rNh+45AAi1hRUOi3cp/pEHV/rSRmAPuczKvBZi/XmAqj6LGPxNcENDgMujqSw+7+uJJ0U\nQ9Yc5CELdrqvZ7mpxDFUx8QeiSww/sXE6aExkV68LMQHbrd4YaV96mjBcBLcyVqzRhLPDyuNzEFw\np4qk0TDXF1ACMNds2+Dt/Uuq9fxkmO5/q/GV1TyqO2RLP/z8GSXYvfZqOpJDtkFNGW4YcUU9OabN\nad+Q/9AomAx6BhJN0djqPBEafbnO0Jt3UVlPRE+gFekn0MvN+Tvw8vtBYQDL9VjaXZ350tmEqM5n\n8r4nQDI2NKf2AqFC1h6yx1D80OPYltLCRgU0y2GMZwp5ffMxpciUQYx48wteQkIj1vSGxelD7w3D\nFp/RHW7VRDRDzGez/pb0ZUlkmUzN7U1Eo3XRciUGIqIIUNn/ONyb3yvpQQA8wPiq1mwZIKZxyItD\n0U/CJNypm/F4npGM0VnY7fDcgFt7D29oorNPtCf2GAGAwDgKQmSNPmHVa8jJsYiuDcpw9URnTY9V\ntlH1HgWU+Tvr/riLXwOUqSufAPwmdP3p7nNAJVhufvf+5dLe5d3hxHtLxI6kjQwypWq3UBSwzQs2\nLO1+IJ1O4ds3iOra8+5J6u94UI1YsUbGYPOJwvzJ6SjHcLu8x6cWFhaUV2G6xs1fpi+7XO3lbm0y\n5W27tdy11ymOBHal9SdMg+tCFS62wxb2pPE8ZYDSXcwFxnU2QoKifLjZMYzKxXJFwweri6WL3VCt\niqEVBjol27uPCleezJI93TjZrRwL5CETU1b0nUl7hB5tni/KeEvIgKJ04f3KhE3w8g2abb6a0kXC\nuIlTQIIPxUM1ALbGJ+4f5qlVpvJ7nwT2bZ394BwTsH2S8eP241Bq2eVSuOi3Ab6tapNU4YNxIpBL\nDzcIQ/Jq3ToPenfueZrnGr3xKjeXYHJFhki5fzQIs0UkV8rvZP5qWUrko6dILN62pdzGOFJ+y4W0\nXfyMB2uKuXJv6Utx9fFydtYUyEj8Zrn90goiFM+NQU0iFdZ4QEvl1Ts+dv8/rrQH3eJTZqvI/yE3\n12TofYflRc2uRuGlx0r+Q6/3+33yPzrfr6U/aRx1N2E+vcv/L2kGVucq16ibQzJGIZqfHdBints2\nnB/xvJob2flgExd0M73QfeiBCRHzrKKyzj9Xy/YqcQjnpVZHJ0z8Khrxyx3uHHEjnFnVbod7bFEU\nc9ZV++TR2/rvd4/6tgAzf4slQhJqLWCG50xvRj+FPZPCbvxvtFnpArHuGPLhQP58M+qu8J1r6I7s\nag7qtFsFsPbykd8JxRwlB3lt4K7cNC1bKu6iSfT4vsU6XRY/ascVBykqvZDfh/zsnUvrZgmKCCBr\np5h8nDwS5zWHjQ5jShlMEqUr1g8tXsoh0g0RCOAYfHMpevkuPO3hdOrwj6+xJKkkfvuUKAJ15Siq\nsfGhPHOKEye2SzkPITZCk6Epg3vCrRweshnptUBNLAAEgZFGjAcsUQpnC+ckfUoseyAmdGwL2gw7\njQTTYXUrHvMyk+sKl6YTqd1bkaKW4kkUvaZ/rhWQefXwi759KpCKAStFGqfBO0P0buiDMWT3NQZW\nSLbgrltCu/0xvuYiq4t2Dq4pEfgQhWDCTXNAaavjbEt3oNWVDk2/oLH9DhhaEGJ7cp8+e6N6+QOS\n0bspQnURwauJmMJ8yUNYyf9ta8c40Np3aJDOareux0hbEISmQSc4Ibt8NqJFXqF7N2NWS5A+gSsi\norAZxPtzThjQ23JkrwJ0ZPNmbmcrPw1mfTOehFBdqoWPx/V1eDm5NNyriTd6LoYLbfHomQ+8WALR\nvZEOzoN+xewA5Uyk1S3+MzmEKZ3CVhK3GHoxuIMA7jpKebjYySo4sCnlQMb6qqT/bEYEyIsnWvcy\n82f7UbQc9TnIkHDhaRJw2m92dRvylHLCW54hHu6QLRMVKvHYeJNzEdtEit7GocKKSTkPn4BPI/Yi\nDB78TGR7uT3b85v7IOyxHBzEe9as39kKuQRced8pqdr9rbXMTxKG9fjurivrGePnZUbfZnOrpVRL\nkKCb+IpI64a/68XG/DR/SKALmfHrlb33vpCSd0LPcJ9gJUYGctaIA7XC5VtBzhDIcR9PBU+tTm9W\nau9psrwiInRr05n+P2ka3juxmJUvRjj+VYdfHsFkpNtAyitihSAmtBzaFQ/GCY9qd7kXWuxltG51\nrFrtLeXwN+9Dnr+9ExBWRWkyD107BNXg7Q127EZxGeVB9VR/X1KLOqjRClcK7lJrRpdva5kHRJ54\nKhRZV1sepRiHDRVCJIhJ9U6FWd/rQgWMmmcGawdgO1OX8kC5EdLJpXpkSeH5Yjqv3zzjASPu7K1e\nwWPiAxuwVgjdGKJIbluw6G5pJQ2uXDR5Xa5xsfAdroYQ0IRUvAkeOY3tND4Lkw/XVvx8KeFAWTNp\nXenmRJ5/iBqiIfM/c/rIofFpZCA5QqrNEMfQtDBkAJrxtq1sol50O0rih87WaJ+mdtwngYU7HOXS\nRQ+QLH1ciUq6EcJ73P+0hPAOokjzgjhqaori7+/iLyN1C/AWI1S59VXo4s8Lrl4s1/kVBR4QHr5V\nNiVmq4cDDDzuL1SP1j/K7bkn0GyS/RY8DPXrsujE06j3tTvjvnMGY/HaviTzAHivPGFzfXWofpT/\nFOBIBBwbn4pUVoeGWQJXIoNTcyeIxLLEOiJ2zYAUEwEdsOn+f8+dtBaERYpwAhYE4NLbwH6ple55\nRwSPKczzLDMieRAXxc+iQjGV4j/5oqHAmcwgXN7zvk/aGpMYPyA2berXcmFw0LSY1sepZIKYaWuj\noYF9Y7ElShrguXYyk1lAuvOX8VPhIpudfS7dnJHZRceapQi/Xl8DlsQg5fPaQo7gvh+5Hxbe5/dt\nsNmxiidiIGAyoTi091EqBHlEwjR9IhtjBB9469BfzhnT6ccPVCINNxJpiUBJiEOtublFQ/M7KWIP\nfC2d0pCxn06H9bmLT9zfhWsyldmMeBU9AEB2Ck/kn+c75sFlRezkk8wmqlFM2NcAvQcSf8GR2hO/\ncFxi9ZzXFOJCgdfy/9zY0YFHKKnurAgHZlgOdBl8inDgvgC2RlDXnzIuz23kNA9RxHQ2/FXl0z61\nnYwe+SCMNDzoPcUZcUBhPZonJ+3irIWLUdjkbb7qTGymgjf5KR/XMuWA/VX/8uRtjWSOc95Nbt8a\nCaci43oMh2lwO79FoeUffZYmZV3fldqnDs1ze/aOGywPwqcT1jntje94qn3lvQoQ/BJ/k93rEy+2\n5x0vRK6gNlXO4KtnS9D9Ypwk0VbvxdQ8n1IGdI8B9XTjg6ENjqtUbomhDPSFQCjwicweZXrRfUOD\nh+cPfCp22/DQgxGK2DHVgSjAS7NgTpMzbMt2/jQdh7ewO5Ek07NBPGfI47RJujdhRIoS6lFB2L5i\nM2Ly8kjyyAQreVG7AMc6P3r5WOlcr9TujTmvWGh8TOwQ1LDhVNVKJ+JGG1AzuIFYfDJBzzcZd1A5\nteF80j/Z0cUfa1hdkR4d4OTqS5QotD9WNh4QCndwopopxD6G1h9s/s5UVf0blaIfjDBU0/Nx9WVK\n6t/6Ruyhta8hQ9IxRw2VqEEY6Evx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protect end_protected\n", "num_lines": 530}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule vio_0 (\nclk,\nprobe_in0,probe_in1,probe_in2,probe_in3,\nprobe_out0,\nprobe_out1,\nprobe_out2,\nprobe_out3,\nprobe_out4,\nprobe_out5,\nprobe_out6\n);\n\ninput clk;\ninput [0 : 0] probe_in0;\ninput [0 : 0] probe_in1;\ninput [7 : 0] probe_in2;\ninput [15 : 0] probe_in3;\n\noutput reg [0 : 0] probe_out0 = 'h0 ;\noutput reg [0 : 0] probe_out1 = 'h0 ;\noutput reg [0 : 0] probe_out2 = 'h1 ;\noutput reg [0 : 0] probe_out3 = 'h0 ;\noutput reg [7 : 0] probe_out4 = 'h00 ;\noutput reg [15 : 0] probe_out5 = 'h0000 ;\noutput reg [15 : 0] probe_out6 = 'h0000 ;\n\n\nendmodule\n", "num_lines": 77}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n\n(* X_CORE_INFO = \"vio,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"vio_0,vio,{}\" *)\n(* CORE_GENERATION_INFO = \"vio_0,vio,{x_ipProduct=Vivado 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_WIDTH=1,C_PROBE_OUT179_WIDTH=1,C_PROBE_OUT180_WIDTH=1,C_PROBE_OUT181_WIDTH=1,C_PROBE_OUT182_WIDTH=1,C_PROBE_OUT183_WIDTH=1,C_PROBE_OUT184_WIDTH=1,C_PROBE_OUT185_WIDTH=1,C_PROBE_OUT186_WIDTH=1,C_PROBE_OUT187_WIDTH=1,C_PROBE_OUT188_WIDTH=1,C_PROBE_OUT189_WIDTH=1,C_PROBE_OUT190_WIDTH=1,C_PROBE_OUT191_WIDTH=1,C_PROBE_OUT192_WIDTH=1,C_PROBE_OUT193_WIDTH=1,C_PROBE_OUT194_WIDTH=1,C_PROBE_OUT195_WIDTH=1,C_PROBE_OUT196_WIDTH=1,C_PROBE_OUT197_WIDTH=1,C_PROBE_OUT198_WIDTH=1,C_PROBE_OUT199_WIDTH=1,C_PROBE_OUT200_WIDTH=1,C_PROBE_OUT201_WIDTH=1,C_PROBE_OUT202_WIDTH=1,C_PROBE_OUT203_WIDTH=1,C_PROBE_OUT204_WIDTH=1,C_PROBE_OUT205_WIDTH=1,C_PROBE_OUT206_WIDTH=1,C_PROBE_OUT207_WIDTH=1,C_PROBE_OUT208_WIDTH=1,C_PROBE_OUT209_WIDTH=1,C_PROBE_OUT210_WIDTH=1,C_PROBE_OUT211_WIDTH=1,C_PROBE_OUT212_WIDTH=1,C_PROBE_OUT213_WIDTH=1,C_PROBE_OUT214_WIDTH=1,C_PROBE_OUT215_WIDTH=1,C_PROBE_OUT216_WIDTH=1,\\\nC_PROBE_OUT217_WIDTH=1,C_PROBE_OUT218_WIDTH=1,C_PROBE_OUT219_WIDTH=1,C_PROBE_OUT220_WIDTH=1,C_PROBE_OUT221_WIDTH=1,C_PROBE_OUT222_WIDTH=1,C_PROBE_OUT223_WIDTH=1,C_PROBE_OUT224_WIDTH=1,C_PROBE_OUT225_WIDTH=1,C_PROBE_OUT226_WIDTH=1,C_PROBE_OUT227_WIDTH=1,C_PROBE_OUT228_WIDTH=1,C_PROBE_OUT229_WIDTH=1,C_PROBE_OUT230_WIDTH=1,C_PROBE_OUT231_WIDTH=1,C_PROBE_OUT232_WIDTH=1,C_PROBE_OUT233_WIDTH=1,C_PROBE_OUT234_WIDTH=1,C_PROBE_OUT235_WIDTH=1,C_PROBE_OUT236_WIDTH=1,C_PROBE_OUT237_WIDTH=1,C_PROBE_OUT238_WIDTH=1,C_PROBE_OUT239_WIDTH=1,C_PROBE_OUT240_WIDTH=1,C_PROBE_OUT241_WIDTH=1,C_PROBE_OUT242_WIDTH=1,C_PROBE_OUT243_WIDTH=1,C_PROBE_OUT244_WIDTH=1,C_PROBE_OUT245_WIDTH=1,C_PROBE_OUT246_WIDTH=1,C_PROBE_OUT247_WIDTH=1,C_PROBE_OUT248_WIDTH=1,C_PROBE_OUT249_WIDTH=1,C_PROBE_OUT250_WIDTH=1,C_PROBE_OUT251_WIDTH=1,C_PROBE_OUT252_WIDTH=1,C_PROBE_OUT253_WIDTH=1,C_PROBE_OUT254_WIDTH=1,C_PROBE_OUT255_WIDTH=1,C_PROBE_OUT0_INIT_VAL=0x0,C_PROBE_OUT1_INIT_VAL=0x0,C_PROBE_OUT2_INIT_VAL=0x1,C_PROBE_OUT3_INIT_VAL=0x0,C_PROBE_OUT4_INIT_VAL=0x00,C_PROBE_OUT5_INIT_VAL=0x0000,C_PROBE_OUT6_INIT_VAL=0x0000,C_PROBE_OUT7_INIT_VAL=0,C_PROBE_OUT8_INIT_VAL=0,C_PROBE_OUT9_INIT_VAL=0,C_PROBE_OUT10_INIT_VAL=0,C_PROBE_OUT11_INIT_VAL=0,C_PROBE_OUT12_INIT_VAL=0,C_PROBE_OUT13_INIT_VAL=0,C_PROBE_OUT14_INIT_VAL=0,C_PROBE_OUT15_INIT_VAL=0,C_PROBE_OUT16_INIT_VAL=0,C_PROBE_OUT17_INIT_VAL=0,C_PROBE_OUT18_INIT_VAL=0,C_PROBE_OUT19_INIT_VAL=0,C_PROBE_OUT20_INIT_VAL=0,C_PROBE_OUT21_INIT_VAL=0,C_PROBE_OUT22_INIT_VAL=0,C_PROBE_OUT23_INIT_VAL=0,C_PROBE_OUT24_INIT_VAL=0,C_PROBE_OUT25_INIT_VAL=0,C_PROBE_OUT26_INIT_VAL=0,C_PROBE_OUT27_INIT_VAL=0,C_PROBE_OUT28_INIT_VAL=0,C_PROBE_OUT29_INIT_VAL=0,C_PROBE_OUT30_INIT_VAL=0,C_PROBE_OUT31_INIT_VAL=0,C_PROBE_OUT32_INIT_VAL=0,C_PROBE_OUT33_INIT_VAL=0,C_PROBE_OUT34_INIT_VAL=0,C_PROBE_OUT35_INIT_VAL=0,C_PROBE_OUT36_INIT_VAL=0,C_PROBE_OUT37_INIT_VAL=0,C_PROBE_OUT38_INIT_VAL=0,C_PROBE_OUT39_INIT_VAL=0,C_PROBE_OUT40_INIT_VAL=0,C_PROBE_OUT41_INIT_VAL=0,C_PROBE_OUT42_INIT_VAL=0,C_PROBE_OUT43_INIT_VAL=0,C_PROBE_OUT44_INIT_VAL=0,C_PROBE_OUT45_INIT_VAL=0,C_PROBE_OUT46_INIT_VAL=0,C_PROBE_OUT47_INIT_VAL=0,C_PROBE_OUT48_INIT_VAL=0,C_PROBE_OUT49_INIT_VAL=0,C_PROBE_OUT50_INIT_VAL=0,C_PROBE_OUT51_INIT_VAL=0,C_PROBE_OUT52_INIT_VAL=0,C_PROBE_OUT53_INIT_VAL=0,C_PROBE_OUT54_INIT_VAL=0,C_PROBE_OUT55_INIT_VAL=0,C_PROBE_OUT56_INIT_VAL=0,C_PROBE_OUT57_INIT_VAL=0,C_PROBE_OUT58_INIT_VAL=0,C_PROBE_OUT59_INIT_VAL=0,C_PROBE_OUT60_INIT_VAL=0,\\\nC_PROBE_OUT61_INIT_VAL=0,C_PROBE_OUT62_INIT_VAL=0,C_PROBE_OUT63_INIT_VAL=0,C_PROBE_OUT64_INIT_VAL=0,C_PROBE_OUT65_INIT_VAL=0,C_PROBE_OUT66_INIT_VAL=0,C_PROBE_OUT67_INIT_VAL=0,C_PROBE_OUT68_INIT_VAL=0,C_PROBE_OUT69_INIT_VAL=0,C_PROBE_OUT70_INIT_VAL=0,C_PROBE_OUT71_INIT_VAL=0,C_PROBE_OUT72_INIT_VAL=0,C_PROBE_OUT73_INIT_VAL=0,C_PROBE_OUT74_INIT_VAL=0,C_PROBE_OUT75_INIT_VAL=0,C_PROBE_OUT76_INIT_VAL=0,C_PROBE_OUT77_INIT_VAL=0,C_PROBE_OUT78_INIT_VAL=0,C_PROBE_OUT79_INIT_VAL=0,C_PROBE_OUT80_INIT_VAL=0,C_PROBE_OUT81_INIT_VAL=0,C_PROBE_OUT82_INIT_VAL=0,C_PROBE_OUT83_INIT_VAL=0,C_PROBE_OUT84_INIT_VAL=0,C_PROBE_OUT85_INIT_VAL=0,C_PROBE_OUT86_INIT_VAL=0,C_PROBE_OUT87_INIT_VAL=0,C_PROBE_OUT88_INIT_VAL=0,C_PROBE_OUT89_INIT_VAL=0,C_PROBE_OUT90_INIT_VAL=0,C_PROBE_OUT91_INIT_VAL=0,C_PROBE_OUT92_INIT_VAL=0,C_PROBE_OUT93_INIT_VAL=0,C_PROBE_OUT94_INIT_VAL=0,C_PROBE_OUT95_INIT_VAL=0,C_PROBE_OUT96_INIT_VAL=0,C_PROBE_OUT97_INIT_VAL=0,C_PROBE_OUT98_INIT_VAL=0,C_PROBE_OUT99_INIT_VAL=0,C_PROBE_OUT100_INIT_VAL=0,C_PROBE_OUT101_INIT_VAL=0,C_PROBE_OUT102_INIT_VAL=0,C_PROBE_OUT103_INIT_VAL=0,C_PROBE_OUT104_INIT_VAL=0,C_PROBE_OUT105_INIT_VAL=0,C_PROBE_OUT106_INIT_VAL=0,C_PROBE_OUT107_INIT_VAL=0,C_PROBE_OUT108_INIT_VAL=0,C_PROBE_OUT109_INIT_VAL=0,C_PROBE_OUT110_INIT_VAL=0,C_PROBE_OUT111_INIT_VAL=0,C_PROBE_OUT112_INIT_VAL=0,C_PROBE_OUT113_INIT_VAL=0,C_PROBE_OUT114_INIT_VAL=0,C_PROBE_OUT115_INIT_VAL=0,C_PROBE_OUT116_INIT_VAL=0,C_PROBE_OUT117_INIT_VAL=0,C_PROBE_OUT118_INIT_VAL=0,C_PROBE_OUT119_INIT_VAL=0,C_PROBE_OUT120_INIT_VAL=0,C_PROBE_OUT121_INIT_VAL=0,C_PROBE_OUT122_INIT_VAL=0,C_PROBE_OUT123_INIT_VAL=0,C_PROBE_OUT124_INIT_VAL=0,C_PROBE_OUT125_INIT_VAL=0,C_PROBE_OUT126_INIT_VAL=0,C_PROBE_OUT127_INIT_VAL=0,C_PROBE_OUT128_INIT_VAL=0,C_PROBE_OUT129_INIT_VAL=0,C_PROBE_OUT130_INIT_VAL=0,C_PROBE_OUT131_INIT_VAL=0,C_PROBE_OUT132_INIT_VAL=0,C_PROBE_OUT133_INIT_VAL=0,C_PROBE_OUT134_INIT_VAL=0,C_PROBE_OUT135_INIT_VAL=0,C_PROBE_OUT136_INIT_VAL=0,C_PROBE_OUT137_INIT_VAL=0,C_PROBE_OUT138_INIT_VAL=0,C_PROBE_OUT139_INIT_VAL=0,C_PROBE_OUT140_INIT_VAL=0,C_PROBE_OUT141_INIT_VAL=0,C_PROBE_OUT142_INIT_VAL=0,C_PROBE_OUT143_INIT_VAL=0,C_PROBE_OUT144_INIT_VAL=0,C_PROBE_OUT145_INIT_VAL=0,C_PROBE_OUT146_INIT_VAL=0,C_PROBE_OUT147_INIT_VAL=0,C_PROBE_OUT148_INIT_VAL=0,C_PROBE_OUT149_INIT_VAL=0,C_PROBE_OUT150_INIT_VAL=0,C_PROBE_OUT151_INIT_VAL=0,C_PROBE_OUT152_INIT_VAL=0,C_PROBE_OUT153_INIT_VAL=0,C_PROBE_OUT154_INIT_VAL=0,C_PROBE_OUT155_INIT_VAL=0,C_PROBE_OUT156_INIT_VAL=0,C_PROBE_OUT157_INIT_VAL=0,C_PROBE_OUT158_INIT_VAL=0,C_PROBE_OUT159_INIT_VAL=0,C_PROBE_OUT160_INIT_VAL=0,\\\nC_PROBE_OUT161_INIT_VAL=0,C_PROBE_OUT162_INIT_VAL=0,C_PROBE_OUT163_INIT_VAL=0,C_PROBE_OUT164_INIT_VAL=0,C_PROBE_OUT165_INIT_VAL=0,C_PROBE_OUT166_INIT_VAL=0,C_PROBE_OUT167_INIT_VAL=0,C_PROBE_OUT168_INIT_VAL=0,C_PROBE_OUT169_INIT_VAL=0,C_PROBE_OUT170_INIT_VAL=0,C_PROBE_OUT171_INIT_VAL=0,C_PROBE_OUT172_INIT_VAL=0,C_PROBE_OUT173_INIT_VAL=0,C_PROBE_OUT174_INIT_VAL=0,C_PROBE_OUT175_INIT_VAL=0,C_PROBE_OUT176_INIT_VAL=0,C_PROBE_OUT177_INIT_VAL=0,C_PROBE_OUT178_INIT_VAL=0,C_PROBE_OUT179_INIT_VAL=0,C_PROBE_OUT180_INIT_VAL=0,C_PROBE_OUT181_INIT_VAL=0,C_PROBE_OUT182_INIT_VAL=0,C_PROBE_OUT183_INIT_VAL=0,C_PROBE_OUT184_INIT_VAL=0,C_PROBE_OUT185_INIT_VAL=0,C_PROBE_OUT186_INIT_VAL=0,C_PROBE_OUT187_INIT_VAL=0,C_PROBE_OUT188_INIT_VAL=0,C_PROBE_OUT189_INIT_VAL=0,C_PROBE_OUT190_INIT_VAL=0,C_PROBE_OUT191_INIT_VAL=0,C_PROBE_OUT192_INIT_VAL=0,C_PROBE_OUT193_INIT_VAL=0,C_PROBE_OUT194_INIT_VAL=0,C_PROBE_OUT195_INIT_VAL=0,C_PROBE_OUT196_INIT_VAL=0,C_PROBE_OUT197_INIT_VAL=0,C_PROBE_OUT198_INIT_VAL=0,C_PROBE_OUT199_INIT_VAL=0,C_PROBE_OUT200_INIT_VAL=0,C_PROBE_OUT201_INIT_VAL=0,C_PROBE_OUT202_INIT_VAL=0,C_PROBE_OUT203_INIT_VAL=0,C_PROBE_OUT204_INIT_VAL=0,C_PROBE_OUT205_INIT_VAL=0,C_PROBE_OUT206_INIT_VAL=0,C_PROBE_OUT207_INIT_VAL=0,C_PROBE_OUT208_INIT_VAL=0,C_PROBE_OUT209_INIT_VAL=0,C_PROBE_OUT210_INIT_VAL=0,C_PROBE_OUT211_INIT_VAL=0,C_PROBE_OUT212_INIT_VAL=0,C_PROBE_OUT213_INIT_VAL=0,C_PROBE_OUT214_INIT_VAL=0,C_PROBE_OUT215_INIT_VAL=0,C_PROBE_OUT216_INIT_VAL=0,C_PROBE_OUT217_INIT_VAL=0,C_PROBE_OUT218_INIT_VAL=0,C_PROBE_OUT219_INIT_VAL=0,C_PROBE_OUT220_INIT_VAL=0,C_PROBE_OUT221_INIT_VAL=0,C_PROBE_OUT222_INIT_VAL=0,C_PROBE_OUT223_INIT_VAL=0,C_PROBE_OUT224_INIT_VAL=0,C_PROBE_OUT225_INIT_VAL=0,C_PROBE_OUT226_INIT_VAL=0,C_PROBE_OUT227_INIT_VAL=0,C_PROBE_OUT228_INIT_VAL=0,C_PROBE_OUT229_INIT_VAL=0,C_PROBE_OUT230_INIT_VAL=0,C_PROBE_OUT231_INIT_VAL=0,C_PROBE_OUT232_INIT_VAL=0,C_PROBE_OUT233_INIT_VAL=0,C_PROBE_OUT234_INIT_VAL=0,C_PROBE_OUT235_INIT_VAL=0,C_PROBE_OUT236_INIT_VAL=0,C_PROBE_OUT237_INIT_VAL=0,C_PROBE_OUT238_INIT_VAL=0,C_PROBE_OUT239_INIT_VAL=0,C_PROBE_OUT240_INIT_VAL=0,C_PROBE_OUT241_INIT_VAL=0,C_PROBE_OUT242_INIT_VAL=0,C_PROBE_OUT243_INIT_VAL=0,C_PROBE_OUT244_INIT_VAL=0,C_PROBE_OUT245_INIT_VAL=0,C_PROBE_OUT246_INIT_VAL=0,C_PROBE_OUT247_INIT_VAL=0,C_PROBE_OUT248_INIT_VAL=0,C_PROBE_OUT249_INIT_VAL=0,C_PROBE_OUT250_INIT_VAL=0,C_PROBE_OUT251_INIT_VAL=0,C_PROBE_OUT252_INIT_VAL=0,C_PROBE_OUT253_INIT_VAL=0,C_PROBE_OUT254_INIT_VAL=0,C_PROBE_OUT255_INIT_VAL=0}\" *)\nmodule vio_0 (\nclk,\nprobe_in0,probe_in1,probe_in2,probe_in3,\nprobe_out0,\nprobe_out1,\nprobe_out2,\nprobe_out3,\nprobe_out4,\nprobe_out5,\nprobe_out6\n);\n\ninput clk;\ninput [0 : 0] probe_in0;\ninput [0 : 0] probe_in1;\ninput [7 : 0] probe_in2;\ninput [15 : 0] probe_in3;\n\noutput [0 : 0] probe_out0;\noutput [0 : 0] probe_out1;\noutput [0 : 0] probe_out2;\noutput [0 : 0] probe_out3;\noutput [7 : 0] probe_out4;\noutput [15 : 0] probe_out5;\noutput [15 : 0] probe_out6;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nvio_v3_0_19_vio #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexuplus\"),\n.C_CORE_TYPE(2),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_NUM_PROBE_IN(4),\n.C_EN_PROBE_IN_ACTIVITY(1),\n.C_NUM_PROBE_OUT(7),\n.C_MAJOR_VERSION(2013),\n.C_MINOR_VERSION(1),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(2),\n.C_CORE_MINOR_VER(0),\n.C_CORE_MINOR_ALPHA_VER(97),\n.C_XSDB_SLAVE_TYPE(33),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(1),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(0),\n.C_PROBE_IN0_WIDTH(1),\n.C_PROBE_IN1_WIDTH(1),\n.C_PROBE_IN2_WIDTH(8),\n.C_PROBE_IN3_WIDTH(16),\n.C_PROBE_IN4_WIDTH(1),\n.C_PROBE_IN5_WIDTH(1),\n.C_PROBE_IN6_WIDTH(1),\n.C_PROBE_IN7_WIDTH(1),\n.C_PROBE_IN8_WIDTH(1),\n.C_PROBE_IN9_WIDTH(1),\n.C_PROBE_IN10_WIDTH(1),\n.C_PROBE_IN11_WIDTH(1),\n.C_PROBE_IN12_WIDTH(1),\n.C_PROBE_IN13_WIDTH(1),\n.C_PROBE_IN14_WIDTH(1),\n.C_PROBE_IN15_WIDTH(1),\n.C_PROBE_IN16_WIDTH(1),\n.C_PROBE_IN17_WIDTH(1),\n.C_PROBE_IN18_WIDTH(1),\n.C_PROBE_IN19_WIDTH(1),\n.C_PROBE_IN20_WIDTH(1),\n.C_PROBE_IN21_WIDTH(1),\n.C_PROBE_IN22_WIDTH(1),\n.C_PROBE_IN23_WIDTH(1),\n.C_PROBE_IN24_WIDTH(1),\n.C_PROBE_IN25_WIDTH(1),\n.C_PROBE_IN26_WIDTH(1),\n.C_PROBE_IN27_WIDTH(1),\n.C_PROBE_IN28_WIDTH(1),\n.C_PROBE_IN29_WIDTH(1),\n.C_PROBE_IN30_WIDTH(1),\n.C_PROBE_IN31_WIDTH(1),\n.C_PROBE_IN32_WIDTH(1),\n.C_PROBE_IN33_WIDTH(1),\n.C_PROBE_IN34_WIDTH(1),\n.C_PROBE_IN35_WIDTH(1),\n.C_PROBE_IN36_WIDTH(1),\n.C_PROBE_IN37_WIDTH(1),\n.C_PROBE_IN38_WIDTH(1),\n.C_PROBE_IN39_WIDTH(1),\n.C_PROBE_IN40_WIDTH(1),\n.C_PROBE_IN41_WIDTH(1),\n.C_PROBE_IN42_WIDTH(1),\n.C_PROBE_IN43_WIDTH(1),\n.C_PROBE_IN44_WIDTH(1),\n.C_PROBE_IN45_WIDTH(1),\n.C_PROBE_IN46_WIDTH(1),\n.C_PROBE_IN47_WIDTH(1),\n.C_PROBE_IN48_WIDTH(1),\n.C_PROBE_IN49_WIDTH(1),\n.C_PROBE_IN50_WIDTH(1),\n.C_PROBE_IN51_WIDTH(1),\n.C_PROBE_IN52_WIDTH(1),\n.C_PROBE_IN53_WIDTH(1),\n.C_PROBE_IN54_WIDTH(1),\n.C_PROBE_IN55_WIDTH(1),\n.C_PROBE_IN56_WIDTH(1),\n.C_PROBE_IN57_WIDTH(1),\n.C_PROBE_IN58_WIDTH(1),\n.C_PROBE_IN59_WIDTH(1),\n.C_PROBE_IN60_WIDTH(1),\n.C_PROBE_IN61_WIDTH(1),\n.C_PROBE_IN62_WIDTH(1),\n.C_PROBE_IN63_WIDTH(1),\n.C_PROBE_IN64_WIDTH(1),\n.C_PROBE_IN65_WIDTH(1),\n.C_PROBE_IN66_WIDTH(1),\n.C_PROBE_IN67_WIDTH(1),\n.C_PROBE_IN68_WIDTH(1),\n.C_PROBE_IN69_WIDTH(1),\n.C_PROBE_IN70_WIDTH(1),\n.C_PROBE_IN71_WIDTH(1),\n.C_PROBE_IN72_WIDTH(1),\n.C_PROBE_IN73_WIDTH(1),\n.C_PROBE_IN74_WIDTH(1),\n.C_PROBE_IN75_WIDTH(1),\n.C_PROBE_IN76_WIDTH(1),\n.C_PROBE_IN77_WIDTH(1),\n.C_PROBE_IN78_WIDTH(1),\n.C_PROBE_IN79_WIDTH(1),\n.C_PROBE_IN80_WIDTH(1),\n.C_PROBE_IN81_WIDTH(1),\n.C_PROBE_IN82_WIDTH(1),\n.C_PROBE_IN83_WIDTH(1),\n.C_PROBE_IN84_WIDTH(1),\n.C_PROBE_IN85_WIDTH(1),\n.C_PROBE_IN86_WIDTH(1),\n.C_PROBE_IN87_WIDTH(1),\n.C_PROBE_IN88_WIDTH(1),\n.C_PROBE_IN89_WIDTH(1),\n.C_PROBE_IN90_WIDTH(1),\n.C_PROBE_IN91_WIDTH(1),\n.C_PROBE_IN92_WIDTH(1),\n.C_PROBE_IN93_WIDTH(1),\n.C_PROBE_IN94_WIDTH(1),\n.C_PROBE_IN95_WIDTH(1),\n.C_PROBE_IN96_WIDTH(1),\n.C_PROBE_IN97_WIDTH(1),\n.C_PROBE_IN98_WIDTH(1),\n.C_PROBE_IN99_WIDTH(1),\n.C_PROBE_IN100_WIDTH(1),\n.C_PROBE_IN101_WIDTH(1),\n.C_PROBE_IN102_WIDTH(1),\n.C_PROBE_IN103_WIDTH(1),\n.C_PROBE_IN104_WIDTH(1),\n.C_PROBE_IN105_WIDTH(1),\n.C_PROBE_IN106_WIDTH(1),\n.C_PROBE_IN107_WIDTH(1),\n.C_PROBE_IN108_WIDTH(1),\n.C_PROBE_IN109_WIDTH(1),\n.C_PROBE_IN110_WIDTH(1),\n.C_PROBE_IN111_WIDTH(1),\n.C_PROBE_IN112_WIDTH(1),\n.C_PROBE_IN113_WIDTH(1),\n.C_PROBE_IN114_WIDTH(1),\n.C_PROBE_IN115_WIDTH(1),\n.C_PROBE_IN116_WIDTH(1),\n.C_PROBE_IN117_WIDTH(1),\n.C_PROBE_IN118_WIDTH(1),\n.C_PROBE_IN119_WIDTH(1),\n.C_PROBE_IN120_WIDTH(1),\n.C_PROBE_IN121_WIDTH(1),\n.C_PROBE_IN122_WIDTH(1),\n.C_PROBE_IN123_WIDTH(1),\n.C_PROBE_IN124_WIDTH(1),\n.C_PROBE_IN125_WIDTH(1),\n.C_PROBE_IN126_WIDTH(1),\n.C_PROBE_IN127_WIDTH(1),\n.C_PROBE_IN128_WIDTH(1),\n.C_PROBE_IN129_WIDTH(1),\n.C_PROBE_IN130_WIDTH(1),\n.C_PROBE_IN131_WIDTH(1),\n.C_PROBE_IN132_WIDTH(1),\n.C_PROBE_IN133_WIDTH(1),\n.C_PROBE_IN134_WIDTH(1),\n.C_PROBE_IN135_WIDTH(1),\n.C_PROBE_IN136_WIDTH(1),\n.C_PROBE_IN137_WIDTH(1),\n.C_PROBE_IN138_WIDTH(1),\n.C_PROBE_IN139_WIDTH(1),\n.C_PROBE_IN140_WIDTH(1),\n.C_PROBE_IN141_WIDTH(1),\n.C_PROBE_IN142_WIDTH(1),\n.C_PROBE_IN143_WIDTH(1),\n.C_PROBE_IN144_WIDTH(1),\n.C_PROBE_IN145_WIDTH(1),\n.C_PROBE_IN146_WIDTH(1),\n.C_PROBE_IN147_WIDTH(1),\n.C_PROBE_IN148_WIDTH(1),\n.C_PROBE_IN149_WIDTH(1),\n.C_PROBE_IN150_WIDTH(1),\n.C_PROBE_IN151_WIDTH(1),\n.C_PROBE_IN152_WIDTH(1),\n.C_PROBE_IN153_WIDTH(1),\n.C_PROBE_IN154_WIDTH(1),\n.C_PROBE_IN155_WIDTH(1),\n.C_PROBE_IN156_WIDTH(1),\n.C_PROBE_IN157_WIDTH(1),\n.C_PROBE_IN158_WIDTH(1),\n.C_PROBE_IN159_WIDTH(1),\n.C_PROBE_IN160_WIDTH(1),\n.C_PROBE_IN161_WIDTH(1),\n.C_PROBE_IN162_WIDTH(1),\n.C_PROBE_IN163_WIDTH(1),\n.C_PROBE_IN164_WIDTH(1),\n.C_PROBE_IN165_WIDTH(1),\n.C_PROBE_IN166_WIDTH(1),\n.C_PROBE_IN167_WIDTH(1),\n.C_PROBE_IN168_WIDTH(1),\n.C_PROBE_IN169_WIDTH(1),\n.C_PROBE_IN170_WIDTH(1),\n.C_PROBE_IN171_WIDTH(1),\n.C_PROBE_IN172_WIDTH(1),\n.C_PROBE_IN173_WIDTH(1),\n.C_PROBE_IN174_WIDTH(1),\n.C_PROBE_IN175_WIDTH(1),\n.C_PROBE_IN176_WIDTH(1),\n.C_PROBE_IN177_WIDTH(1),\n.C_PROBE_IN178_WIDTH(1),\n.C_PROBE_IN179_WIDTH(1),\n.C_PROBE_IN180_WIDTH(1),\n.C_PROBE_IN181_WIDTH(1),\n.C_PROBE_IN182_WIDTH(1),\n.C_PROBE_IN183_WIDTH(1),\n.C_PROBE_IN184_WIDTH(1),\n.C_PROBE_IN185_WIDTH(1),\n.C_PROBE_IN186_WIDTH(1),\n.C_PROBE_IN187_WIDTH(1),\n.C_PROBE_IN188_WIDTH(1),\n.C_PROBE_IN189_WIDTH(1),\n.C_PROBE_IN190_WIDTH(1),\n.C_PROBE_IN191_WIDTH(1),\n.C_PROBE_IN192_WIDTH(1),\n.C_PROBE_IN193_WIDTH(1),\n.C_PROBE_IN194_WIDTH(1),\n.C_PROBE_IN195_WIDTH(1),\n.C_PROBE_IN196_WIDTH(1),\n.C_PROBE_IN197_WIDTH(1),\n.C_PROBE_IN198_WIDTH(1),\n.C_PROBE_IN199_WIDTH(1),\n.C_PROBE_IN200_WIDTH(1),\n.C_PROBE_IN201_WIDTH(1),\n.C_PROBE_IN202_WIDTH(1),\n.C_PROBE_IN203_WIDTH(1),\n.C_PROBE_IN204_WIDTH(1),\n.C_PROBE_IN205_WIDTH(1),\n.C_PROBE_IN206_WIDTH(1),\n.C_PROBE_IN207_WIDTH(1),\n.C_PROBE_IN208_WIDTH(1),\n.C_PROBE_IN209_WIDTH(1),\n.C_PROBE_IN210_WIDTH(1),\n.C_PROBE_IN211_WIDTH(1),\n.C_PROBE_IN212_WIDTH(1),\n.C_PROBE_IN213_WIDTH(1),\n.C_PROBE_IN214_WIDTH(1),\n.C_PROBE_IN215_WIDTH(1),\n.C_PROBE_IN216_WIDTH(1),\n.C_PROBE_IN217_WIDTH(1),\n.C_PROBE_IN218_WIDTH(1),\n.C_PROBE_IN219_WIDTH(1),\n.C_PROBE_IN220_WIDTH(1),\n.C_PROBE_IN221_WIDTH(1),\n.C_PROBE_IN222_WIDTH(1),\n.C_PROBE_IN223_WIDTH(1),\n.C_PROBE_IN224_WIDTH(1),\n.C_PROBE_IN225_WIDTH(1),\n.C_PROBE_IN226_WIDTH(1),\n.C_PROBE_IN227_WIDTH(1),\n.C_PROBE_IN228_WIDTH(1),\n.C_PROBE_IN229_WIDTH(1),\n.C_PROBE_IN230_WIDTH(1),\n.C_PROBE_IN231_WIDTH(1),\n.C_PROBE_IN232_WIDTH(1),\n.C_PROBE_IN233_WIDTH(1),\n.C_PROBE_IN234_WIDTH(1),\n.C_PROBE_IN235_WIDTH(1),\n.C_PROBE_IN236_WIDTH(1),\n.C_PROBE_IN237_WIDTH(1),\n.C_PROBE_IN238_WIDTH(1),\n.C_PROBE_IN239_WIDTH(1),\n.C_PROBE_IN240_WIDTH(1),\n.C_PROBE_IN241_WIDTH(1),\n.C_PROBE_IN242_WIDTH(1),\n.C_PROBE_IN243_WIDTH(1),\n.C_PROBE_IN244_WIDTH(1),\n.C_PROBE_IN245_WIDTH(1),\n.C_PROBE_IN246_WIDTH(1),\n.C_PROBE_IN247_WIDTH(1),\n.C_PROBE_IN248_WIDTH(1),\n.C_PROBE_IN249_WIDTH(1),\n.C_PROBE_IN250_WIDTH(1),\n.C_PROBE_IN251_WIDTH(1),\n.C_PROBE_IN252_WIDTH(1),\n.C_PROBE_IN253_WIDTH(1),\n.C_PROBE_IN254_WIDTH(1),\n.C_PROBE_IN255_WIDTH(1),\n.C_PROBE_OUT0_WIDTH(1),\n.C_PROBE_OUT1_WIDTH(1),\n.C_PROBE_OUT2_WIDTH(1),\n.C_PROBE_OUT3_WIDTH(1),\n.C_PROBE_OUT4_WIDTH(8),\n.C_PROBE_OUT5_WIDTH(16),\n.C_PROBE_OUT6_WIDTH(16),\n.C_PROBE_OUT7_WIDTH(1),\n.C_PROBE_OUT8_WIDTH(1),\n.C_PROBE_OUT9_WIDTH(1),\n.C_PROBE_OUT10_WIDTH(1),\n.C_PROBE_OUT11_WIDTH(1),\n.C_PROBE_OUT12_WIDTH(1),\n.C_PROBE_OUT13_WIDTH(1),\n.C_PROBE_OUT14_WIDTH(1),\n.C_PROBE_OUT15_WIDTH(1),\n.C_PROBE_OUT16_WIDTH(1),\n.C_PROBE_OUT17_WIDTH(1),\n.C_PROBE_OUT18_WIDTH(1),\n.C_PROBE_OUT19_WIDTH(1),\n.C_PROBE_OUT20_WIDTH(1),\n.C_PROBE_OUT21_WIDTH(1),\n.C_PROBE_OUT22_WIDTH(1),\n.C_PROBE_OUT23_WIDTH(1),\n.C_PROBE_OUT24_WIDTH(1),\n.C_PROBE_OUT25_WIDTH(1),\n.C_PROBE_OUT26_WIDTH(1),\n.C_PROBE_OUT27_WIDTH(1),\n.C_PROBE_OUT28_WIDTH(1),\n.C_PROBE_OUT29_WIDTH(1),\n.C_PROBE_OUT30_WIDTH(1),\n.C_PROBE_OUT31_WIDTH(1),\n.C_PROBE_OUT32_WIDTH(1),\n.C_PROBE_OUT33_WIDTH(1),\n.C_PROBE_OUT34_WIDTH(1),\n.C_PROBE_OUT35_WIDTH(1),\n.C_PROBE_OUT36_WIDTH(1),\n.C_PROBE_OUT37_WIDTH(1),\n.C_PROBE_OUT38_WIDTH(1),\n.C_PROBE_OUT39_WIDTH(1),\n.C_PROBE_OUT40_WIDTH(1),\n.C_PROBE_OUT41_WIDTH(1),\n.C_PROBE_OUT42_WIDTH(1),\n.C_PROBE_OUT43_WIDTH(1),\n.C_PROBE_OUT44_WIDTH(1),\n.C_PROBE_OUT45_WIDTH(1),\n.C_PROBE_OUT46_WIDTH(1),\n.C_PROBE_OUT47_WIDTH(1),\n.C_PROBE_OUT48_WIDTH(1),\n.C_PROBE_OUT49_WIDTH(1),\n.C_PROBE_OUT50_WIDTH(1),\n.C_PROBE_OUT51_WIDTH(1),\n.C_PROBE_OUT52_WIDTH(1),\n.C_PROBE_OUT53_WIDTH(1),\n.C_PROBE_OUT54_WIDTH(1),\n.C_PROBE_OUT55_WIDTH(1),\n.C_PROBE_OUT56_WIDTH(1),\n.C_PROBE_OUT57_WIDTH(1),\n.C_PROBE_OUT58_WIDTH(1),\n.C_PROBE_OUT59_WIDTH(1),\n.C_PROBE_OUT60_WIDTH(1),\n.C_PROBE_OUT61_WIDTH(1),\n.C_PROBE_OUT62_WIDTH(1),\n.C_PROBE_OUT63_WIDTH(1),\n.C_PROBE_OUT64_WIDTH(1),\n.C_PROBE_OUT65_WIDTH(1),\n.C_PROBE_OUT66_WIDTH(1),\n.C_PROBE_OUT67_WIDTH(1),\n.C_PROBE_OUT68_WIDTH(1),\n.C_PROBE_OUT69_WIDTH(1),\n.C_PROBE_OUT70_WIDTH(1),\n.C_PROBE_OUT71_WIDTH(1),\n.C_PROBE_OUT72_WIDTH(1),\n.C_PROBE_OUT73_WIDTH(1),\n.C_PROBE_OUT74_WIDTH(1),\n.C_PROBE_OUT75_WIDTH(1),\n.C_PROBE_OUT76_WIDTH(1),\n.C_PROBE_OUT77_WIDTH(1),\n.C_PROBE_OUT78_WIDTH(1),\n.C_PROBE_OUT79_WIDTH(1),\n.C_PROBE_OUT80_WIDTH(1),\n.C_PROBE_OUT81_WIDTH(1),\n.C_PROBE_OUT82_WIDTH(1),\n.C_PROBE_OUT83_WIDTH(1),\n.C_PROBE_OUT84_WIDTH(1),\n.C_PROBE_OUT85_WIDTH(1),\n.C_PROBE_OUT86_WIDTH(1),\n.C_PROBE_OUT87_WIDTH(1),\n.C_PROBE_OUT88_WIDTH(1),\n.C_PROBE_OUT89_WIDTH(1),\n.C_PROBE_OUT90_WIDTH(1),\n.C_PROBE_OUT91_WIDTH(1),\n.C_PROBE_OUT92_WIDTH(1),\n.C_PROBE_OUT93_WIDTH(1),\n.C_PROBE_OUT94_WIDTH(1),\n.C_PROBE_OUT95_WIDTH(1),\n.C_PROBE_OUT96_WIDTH(1),\n.C_PROBE_OUT97_WIDTH(1),\n.C_PROBE_OUT98_WIDTH(1),\n.C_PROBE_OUT99_WIDTH(1),\n.C_PROBE_OUT100_WIDTH(1),\n.C_PROBE_OUT101_WIDTH(1),\n.C_PROBE_OUT102_WIDTH(1),\n.C_PROBE_OUT103_WIDTH(1),\n.C_PROBE_OUT104_WIDTH(1),\n.C_PROBE_OUT105_WIDTH(1),\n.C_PROBE_OUT106_WIDTH(1),\n.C_PROBE_OUT107_WIDTH(1),\n.C_PROBE_OUT108_WIDTH(1),\n.C_PROBE_OUT109_WIDTH(1),\n.C_PROBE_OUT110_WIDTH(1),\n.C_PROBE_OUT111_WIDTH(1),\n.C_PROBE_OUT112_WIDTH(1),\n.C_PROBE_OUT113_WIDTH(1),\n.C_PROBE_OUT114_WIDTH(1),\n.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inst (\n.clk(clk),\n.sl_iport0(sl_iport0),\n.sl_oport0(sl_oport0),\n.probe_in0(probe_in0),\n.probe_in1(probe_in1),\n.probe_in2(probe_in2),\n.probe_in3(probe_in3),\n.probe_in4(0),\n.probe_in5(0),\n.probe_in6(0),\n.probe_in7(0),\n.probe_in8(0),\n.probe_in9(0),\n.probe_in10(0),\n.probe_in11(0),\n.probe_in12(0),\n.probe_in13(0),\n.probe_in14(0),\n.probe_in15(0),\n.probe_in16(0),\n.probe_in17(0),\n.probe_in18(0),\n.probe_in19(0),\n.probe_in20(0),\n.probe_in21(0),\n.probe_in22(0),\n.probe_in23(0),\n.probe_in24(0),\n.probe_in25(0),\n.probe_in26(0),\n.probe_in27(0),\n.probe_in28(0),\n.probe_in29(0),\n.probe_in30(0),\n.probe_in31(0),\n.probe_in32(0),\n.probe_in33(0),\n.probe_in34(0),\n.probe_in35(0),\n.probe_in36(0),\n.probe_in37(0),\n.probe_in38(0),\n.probe_in39(0),\n.probe_in40(0),\n.probe_in41(0),\n.probe_in42(0),\n.probe_in43(0),\n.probe_in44(0),\n.probe_in45(0),\n.probe_in46(0),\n.probe_in47(0),\n.probe_in48(0),\n.probe_in49(0),\n.probe_in50(0),\n.probe_in51(0),\n.probe_in52(0),\n.probe_in53(0),\n.probe_in54(0),\n.probe_in55(0),\n.probe_in56(0),\n.probe_in57(0),\n.probe_in58(0),\n.probe_in59(0),\n.probe_in60(0),\n.probe_in61(0),\n.probe_in62(0),\n.probe_in63(0),\n.probe_in64(0),\n.probe_in65(0),\n.probe_in66(0),\n.probe_in67(0),\n.probe_in68(0),\n.probe_in69(0),\n.probe_in70(0),\n.probe_in71(0),\n.probe_in72(0),\n.probe_in73(0),\n.probe_in74(0),\n.probe_in75(0),\n.probe_in76(0),\n.probe_in77(0),\n.probe_in78(0),\n.probe_in79(0),\n.probe_in80(0),\n.probe_in81(0),\n.probe_in82(0),\n.probe_in83(0),\n.probe_in84(0),\n.probe_in85(0),\n.probe_in86(0),\n.probe_in87(0),\n.probe_in88(0),\n.probe_in89(0),\n.probe_in90(0),\n.probe_in91(0),\n.probe_in92(0),\n.probe_in93(0),\n.probe_in94(0),\n.probe_in95(0),\n.probe_in96(0),\n.probe_in97(0),\n.probe_in98(0),\n.probe_in99(0),\n.probe_in100(0),\n.probe_in101(0),\n.probe_in102(0),\n.probe_in103(0),\n.probe_in104(0),\n.probe_in105(0),\n.probe_in106(0),\n.probe_in107(0),\n.probe_in108(0),\n.probe_in109(0),\n.probe_in110(0),\n.probe_in111(0),\n.probe_in112(0),\n.probe_in113(0),\n.probe_in114(0),\n.probe_in115(0),\n.probe_in116(0),\n.probe_in117(0),\n.probe_in118(0),\n.probe_in119(0),\n.probe_in120(0),\n.probe_in121(0),\n.probe_in122(0),\n.probe_in123(0),\n.probe_in124(0),\n.probe_in125(0),\n.probe_in126(0),\n.probe_in127(0),\n.probe_in128(0),\n.probe_in129(0),\n.probe_in130(0),\n.probe_in131(0),\n.probe_in132(0),\n.probe_in133(0),\n.probe_in134(0),\n.probe_in135(0),\n.probe_in136(0),\n.probe_in137(0),\n.probe_in138(0),\n.probe_in139(0),\n.probe_in140(0),\n.probe_in141(0),\n.probe_in142(0),\n.probe_in143(0),\n.probe_in144(0),\n.probe_in145(0),\n.probe_in146(0),\n.probe_in147(0),\n.probe_in148(0),\n.probe_in149(0),\n.probe_in150(0),\n.probe_in151(0),\n.probe_in152(0),\n.probe_in153(0),\n.probe_in154(0),\n.probe_in155(0),\n.probe_in156(0),\n.probe_in157(0),\n.probe_in158(0),\n.probe_in159(0),\n.probe_in160(0),\n.probe_in161(0),\n.probe_in162(0),\n.probe_in163(0),\n.probe_in164(0),\n.probe_in165(0),\n.probe_in166(0),\n.probe_in167(0),\n.probe_in168(0),\n.probe_in169(0),\n.probe_in170(0),\n.probe_in171(0),\n.probe_in172(0),\n.probe_in173(0),\n.probe_in174(0),\n.probe_in175(0),\n.probe_in176(0),\n.probe_in177(0),\n.probe_in178(0),\n.probe_in179(0),\n.probe_in180(0),\n.probe_in181(0),\n.probe_in182(0),\n.probe_in183(0),\n.probe_in184(0),\n.probe_in185(0),\n.probe_in186(0),\n.probe_in187(0),\n.probe_in188(0),\n.probe_in189(0),\n.probe_in190(0),\n.probe_in191(0),\n.probe_in192(0),\n.probe_in193(0),\n.probe_in194(0),\n.probe_in195(0),\n.probe_in196(0),\n.probe_in197(0),\n.probe_in198(0),\n.probe_in199(0),\n.probe_in200(0),\n.probe_in201(0),\n.probe_in202(0),\n.probe_in203(0),\n.probe_in204(0),\n.probe_in205(0),\n.probe_in206(0),\n.probe_in207(0),\n.probe_in208(0),\n.probe_in209(0),\n.probe_in210(0),\n.probe_in211(0),\n.probe_in212(0),\n.probe_in213(0),\n.probe_in214(0),\n.probe_in215(0),\n.probe_in216(0),\n.probe_in217(0),\n.probe_in218(0),\n.probe_in219(0),\n.probe_in220(0),\n.probe_in221(0),\n.probe_in222(0),\n.probe_in223(0),\n.probe_in224(0),\n.probe_in225(0),\n.probe_in226(0),\n.probe_in227(0),\n.probe_in228(0),\n.probe_in229(0),\n.probe_in230(0),\n.probe_in231(0),\n.probe_in232(0),\n.probe_in233(0),\n.probe_in234(0),\n.probe_in235(0),\n.probe_in236(0),\n.probe_in237(0),\n.probe_in238(0),\n.probe_in239(0),\n.probe_in240(0),\n.probe_in241(0),\n.probe_in242(0),\n.probe_in243(0),\n.probe_in244(0),\n.probe_in245(0),\n.probe_in246(0),\n.probe_in247(0),\n.probe_in248(0),\n.probe_in249(0),\n.probe_in250(0),\n.probe_in251(0),\n.probe_in252(0),\n.probe_in253(0),\n.probe_in254(0),\n.probe_in255(0),\n.probe_out0(probe_out0),\n.probe_out1(probe_out1),\n.probe_out2(probe_out2),\n.probe_out3(probe_out3),\n.probe_out4(probe_out4),\n.probe_out5(probe_out5),\n.probe_out6(probe_out6),\n.probe_out7(),\n.probe_out8(),\n.probe_out9(),\n.probe_out10(),\n.probe_out11(),\n.probe_out12(),\n.probe_out13(),\n.probe_out14(),\n.probe_out15(),\n.probe_out16(),\n.probe_out17(),\n.probe_out18(),\n.probe_out19(),\n.probe_out20(),\n.probe_out21(),\n.probe_out22(),\n.probe_out23(),\n.probe_out24(),\n.probe_out25(),\n.probe_out26(),\n.probe_out27(),\n.probe_out28(),\n.probe_out29(),\n.probe_out30(),\n.probe_out31(),\n.probe_out32(),\n.probe_out33(),\n.probe_out34(),\n.probe_out35(),\n.probe_out36(),\n.probe_out37(),\n.probe_out38(),\n.probe_out39(),\n.probe_out40(),\n.probe_out41(),\n.probe_out42(),\n.probe_out43(),\n.probe_out44(),\n.probe_out45(),\n.probe_out46(),\n.probe_out47(),\n.probe_out48(),\n.probe_out49(),\n.probe_out50(),\n.probe_out51(),\n.probe_out52(),\n.probe_out53(),\n.probe_out54(),\n.probe_out55(),\n.probe_out56(),\n.probe_out57(),\n.probe_out58(),\n.probe_out59(),\n.probe_out60(),\n.probe_out61(),\n.probe_out62(),\n.probe_out63(),\n.probe_out64(),\n.probe_out65(),\n.probe_out66(),\n.probe_out67(),\n.probe_out68(),\n.probe_out69(),\n.probe_out70(),\n.probe_out71(),\n.probe_out72(),\n.probe_out73(),\n.probe_out74(),\n.probe_out75(),\n.probe_out76(),\n.probe_out77(),\n.probe_out78(),\n.probe_out79(),\n.probe_out80(),\n.probe_out81(),\n.probe_out82(),\n.probe_out83(),\n.probe_out84(),\n.probe_out85(),\n.probe_out86(),\n.probe_out87(),\n.probe_out88(),\n.probe_out89(),\n.probe_out90(),\n.probe_out91(),\n.probe_out92(),\n.probe_out93(),\n.probe_out94(),\n.probe_out95(),\n.probe_out96(),\n.probe_out97(),\n.probe_out98(),\n.probe_out99(),\n.probe_out100(),\n.probe_out101(),\n.probe_out102(),\n.probe_out103(),\n.probe_out104(),\n.probe_out105(),\n.probe_out106(),\n.probe_out107(),\n.probe_out108(),\n.probe_out109(),\n.probe_out110(),\n.probe_out111(),\n.probe_out112(),\n.probe_out113(),\n.probe_out114(),\n.probe_out115(),\n.probe_out116(),\n.probe_out117(),\n.probe_out118(),\n.probe_out119(),\n.probe_out120(),\n.probe_out121(),\n.probe_out122(),\n.probe_out123(),\n.probe_out124(),\n.probe_out125(),\n.probe_out126(),\n.probe_out127(),\n.probe_out128(),\n.probe_out129(),\n.probe_out130(),\n.probe_out131(),\n.probe_out132(),\n.probe_out133(),\n.probe_out134(),\n.probe_out135(),\n.probe_out136(),\n.probe_out137(),\n.probe_out138(),\n.probe_out139(),\n.probe_out140(),\n.probe_out141(),\n.probe_out142(),\n.probe_out143(),\n.probe_out144(),\n.probe_out145(),\n.probe_out146(),\n.probe_out147(),\n.probe_out148(),\n.probe_out149(),\n.probe_out150(),\n.probe_out151(),\n.probe_out152(),\n.probe_out153(),\n.probe_out154(),\n.probe_out155(),\n.probe_out156(),\n.probe_out157(),\n.probe_out158(),\n.probe_out159(),\n.probe_out160(),\n.probe_out161(),\n.probe_out162(),\n.probe_out163(),\n.probe_out164(),\n.probe_out165(),\n.probe_out166(),\n.probe_out167(),\n.probe_out168(),\n.probe_out169(),\n.probe_out170(),\n.probe_out171(),\n.probe_out172(),\n.probe_out173(),\n.probe_out174(),\n.probe_out175(),\n.probe_out176(),\n.probe_out177(),\n.probe_out178(),\n.probe_out179(),\n.probe_out180(),\n.probe_out181(),\n.probe_out182(),\n.probe_out183(),\n.probe_out184(),\n.probe_out185(),\n.probe_out186(),\n.probe_out187(),\n.probe_out188(),\n.probe_out189(),\n.probe_out190(),\n.probe_out191(),\n.probe_out192(),\n.probe_out193(),\n.probe_out194(),\n.probe_out195(),\n.probe_out196(),\n.probe_out197(),\n.probe_out198(),\n.probe_out199(),\n.probe_out200(),\n.probe_out201(),\n.probe_out202(),\n.probe_out203(),\n.probe_out204(),\n.probe_out205(),\n.probe_out206(),\n.probe_out207(),\n.probe_out208(),\n.probe_out209(),\n.probe_out210(),\n.probe_out211(),\n.probe_out212(),\n.probe_out213(),\n.probe_out214(),\n.probe_out215(),\n.probe_out216(),\n.probe_out217(),\n.probe_out218(),\n.probe_out219(),\n.probe_out220(),\n.probe_out221(),\n.probe_out222(),\n.probe_out223(),\n.probe_out224(),\n.probe_out225(),\n.probe_out226(),\n.probe_out227(),\n.probe_out228(),\n.probe_out229(),\n.probe_out230(),\n.probe_out231(),\n.probe_out232(),\n.probe_out233(),\n.probe_out234(),\n.probe_out235(),\n.probe_out236(),\n.probe_out237(),\n.probe_out238(),\n.probe_out239(),\n.probe_out240(),\n.probe_out241(),\n.probe_out242(),\n.probe_out243(),\n.probe_out244(),\n.probe_out245(),\n.probe_out246(),\n.probe_out247(),\n.probe_out248(),\n.probe_out249(),\n.probe_out250(),\n.probe_out251(),\n.probe_out252(),\n.probe_out253(),\n.probe_out254(),\n.probe_out255()\n)/* synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 1395}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_master #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_SUPPORTS_NARROW = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1,\n   parameter [C_AXI_ADDR_WIDTH-1:0] C_AXI_ADDR = 0,  // Base address\n   parameter integer C_NUM_ADDR = 1,  // Number of address iterations; range 1..2**16 (fixed increment = 32'h10000\n   parameter integer C_NUM_ID = 1,  // Number of ID iterations; range 1..2**C_ID_WIDTH (base = 0; fixed increment = 1)\n   parameter integer C_NUM_LEN = 1,  // Number of LEN iterations; range 1..9 (base = 0; value = 2**i - 1)\n   parameter integer C_NUM_TRANS = 1  // Number of transactions; range >=1 (read and write)\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_awvalid,\n  input  wire                            m_axi_awready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_awburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_awlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_awlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_awid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]    m_axi_awuser = 'b0,\n  /**************** Write Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_wid,\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]      m_axi_wdata,\n  (* dont_touch=\"true\" *) output reg [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb = {(C_AXI_DATA_WIDTH/8){1'b1}},\n  (* dont_touch=\"true\" *) output wire                             m_axi_wvalid,\n  input  wire                            m_axi_wready,\n  (* dont_touch=\"true\" *) output wire                             m_axi_wlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]     m_axi_wuser = 'b0,\n  /**************** Write Response Channel Signals ****************/\n  input  wire [2-1:0]                    m_axi_bresp,\n  input  wire                            m_axi_bvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_bready,\n  input  wire [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]     m_axi_buser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_bid,\n  /**************** Read Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_arvalid,\n  input  wire                            m_axi_arready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_arburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_arlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_arlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_arid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]    m_axi_aruser = 'b0,\n  /**************** Read Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]      m_axi_rdata,\n  input  wire [2-1:0]                    m_axi_rresp,\n  input  wire                            m_axi_rvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_rready,\n  input  wire                            m_axi_rlast,\n  input  wire [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]     m_axi_ruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_rid,\n  /**************** System Signals ****************/\n  input  wire                            aclk,\n  input  wire                            aresetn\n  );\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n  localparam integer  P_NUM_ID_LOG = f_ceil_log2(C_NUM_ID);\n  localparam integer  P_NUM_ADDR_LOG = f_ceil_log2(C_NUM_ADDR);\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL==0 ? 8 : C_AXI_PROTOCOL==1 ? 4 : 1);\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer               P_M_AXI_DATA_BYTES = (C_AXI_DATA_WIDTH / 8);\n  localparam integer               P_M_AXI_DONE_WIDTH = f_ceil_log2(C_NUM_TRANS<2?2:C_NUM_TRANS);\n  localparam integer               P_M_AXI_SIZE = f_ceil_log2(C_AXI_DATA_WIDTH)-3;\n\n  /**************** Internal Wires/Regs - Global ****************/\n   wire                            done;\n    wire                            dummy ;\n  reg                         done_i;\n  reg                         done_sel;\n  wire                         done_cycle;\n  reg                          done_d1 = 1'b0;\n  reg                   areset = 1'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] arcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] rcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [3:0]                    acc_r_i = 4'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] awcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] wcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] bcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [2:0]                    acc_b_i = 3'b0;\n\n  // Register Reset\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    \n    /**************** Internal Wires/Regs - Read Channels ****************/\n    wire                         read_xaction_done_i;\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_arid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_ADDR_WIDTH:0]      araddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  arprot_i = 3'b0;\n    reg [3-1:0]                  arsize_i = 3'b0;\n    reg [2-1:0]                  arburst_i = 2'b0;\n    reg [4-1:0]                  arcache_i = 4'b0;\n    reg [2-1:0]                  arlock_i = 2'b0;\n    reg [P_LEN_WIDTH-1:0]     arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [4-1:0]                  arqos_i = 4'b0;\n    reg [P_ID_WIDTH-1:0]        arid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [2-1:0]                  rresp_i = 2'b00;\n    reg [C_AXI_RUSER_WIDTH:0]   ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      rid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_arvalid_i = 1'b0;\n    reg                        m_axi_rready_i = 1'b0;\n    reg [P_NUM_ADDR_LOG:0]    araddr_cnt = 0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign read_xaction_done_i = m_axi_rvalid && m_axi_rready_i && ((C_AXI_PROTOCOL==2)?1'b1:m_axi_rlast);\n    assign m_axi_arvalid = m_axi_arvalid_i;\n    assign m_axi_rready = m_axi_rready_i;\n    assign m_axi_araddr = m_axi_araddr_i;\n    assign m_axi_arlen = m_axi_arlen_i;\n    always @(posedge aclk) begin\n      m_axi_arprot <= dummy ? arprot_i : 3'b000;\n      m_axi_arsize <= dummy ? arsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_arburst <= dummy ? arburst_i : 2'b01;\n      m_axi_arlock <= dummy ? arlock_i : 1'b0;\n      m_axi_arcache <= dummy ? arcache_i : 4'h3;\n      m_axi_arqos <= dummy  ? arqos_i : 4'h0;\n      m_axi_aruser <= dummy ? aruser_i : 0;\n    end\n  \n    //**********************************************\n    // Read Channel: ARVALID, ARADDR, ARLEN, RREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_arvalid_i <= 1'b0;\n        arcnt_i <= C_NUM_TRANS;\n        m_axi_arlen_i <= 0;\n        m_axi_araddr_i <= C_AXI_ADDR;\n        m_axi_arid_i <= 1;\n        araddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_arready & m_axi_arvalid_i) begin\n          arcnt_i <= arcnt_i - 1;\n          if (araddr_cnt == 1) begin\n            m_axi_araddr_i <= dummy ? araddr_i : C_AXI_ADDR;\n            araddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_araddr_i <= m_axi_araddr_i + 32'h10000;\n            araddr_cnt <= araddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_arlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_arlen_i <= dummy ? arlen_i : 0;\n          end else begin\n            m_axi_arlen_i <= (m_axi_arlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_arid_i == C_NUM_ID)) begin\n            m_axi_arid <= dummy ? arid_i : 0;\n            m_axi_arid_i <= 1;\n          end else begin\n            m_axi_arid <= m_axi_arid_i;\n            m_axi_arid_i <= m_axi_arid_i + 1;\n          end\n          if (arcnt_i == 1) begin\n            m_axi_arvalid_i <= 1'b0;\n          end\n        end else if (arcnt_i != 0) begin\n          m_axi_arvalid_i <= 1'b1;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      araddr_i <= {araddr_i, ~araddr_i[C_AXI_ADDR_WIDTH]};\n      arprot_i <= {arprot_i, ~arprot_i[3-1]};\n      arlen_i <= {arlen_i, ~arlen_i[P_LEN_WIDTH-1]};\n      arsize_i <= {arsize_i, ~arsize_i[3-1]};\n      arburst_i <= {arburst_i, ~arburst_i[2-1]};\n      arlock_i <= {arlock_i, ~arlock_i[2-1]};\n      arcache_i <= {arcache_i, ~arcache_i[4-1]};\n      arqos_i <= {arqos_i, ~arqos_i[4-1]};\n      aruser_i <= {aruser_i, ~aruser_i[C_AXI_ARUSER_WIDTH]};\n      arid_i <= {arid_i, ~arid_i[P_ID_WIDTH-1]};\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        m_axi_rready_i <= 1'b0;\n        rcnt_i <= C_NUM_TRANS;\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        rresp_i <= {2{1'b0}};\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n        rid_i <= {P_ID_WIDTH{1'b0}};\n        acc_r_i <= 4'b0;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_rvalid & m_axi_rready_i) begin\n          m_axi_rready_i <= 1'b0;\n          rdata_i <= m_axi_rdata;\n            acc_r_i[0] <= rdata_i[0];\n          rresp_i <= m_axi_rresp;\n            acc_r_i[1] <= rresp_i[0];\n          ruser_i <= m_axi_ruser;\n            acc_r_i[2] <= ruser_i[0];\n          rid_i <= m_axi_rid;\n            acc_r_i[3] <= rid_i[0];\n          if (m_axi_rlast) begin\n            rcnt_i <= rcnt_i - 1;\n          end\n        end else begin\n          rdata_i <= rdata_i>>1;\n          rresp_i <= rresp_i>>1;\n          ruser_i <= ruser_i>>1;\n          rid_i <= rid_i>>1;\n          acc_r_i <= acc_r_i>>1;\n          if (m_axi_rvalid) begin\n            m_axi_rready_i <= 1'b1;\n          end\n        end\n      end\n    end\n    \n    assign dummy = rdata_i[0];\n    \n    \n\n    /**************** Internal Wires/Regs - Write Channels ****************/\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_awid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [8-1:0]                  xfer_w_i = 8'h00;\n    wire                         write_burst_done_i;\n    reg [C_AXI_ADDR_WIDTH:0]      awaddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  awprot_i = 3'b0;\n    reg [P_LEN_WIDTH-1:0]     awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [3-1:0]                  awsize_i = 3'b0;\n    reg [2-1:0]                  awburst_i = 2'b0;\n    reg [4-1:0]                  awcache_i = 4'b0;\n    reg [2-1:0]                  awlock_i = 2'b0;\n    reg [4-1:0]                  awqos_i = 4'b0;\n    reg [P_ID_WIDTH:0]        awid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_AWUSER_WIDTH:0]    awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg [P_M_AXI_DATA_BYTES-1:0] wstrb_i = {P_M_AXI_DATA_BYTES{1'b1}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]        wid_i = {P_ID_WIDTH{1'b0}};\n    reg [2-1:0]                  bresp_i = 2'b00;\n    reg [C_AXI_BUSER_WIDTH:0]   buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      bid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_awvalid_i = 1'b0;\n    reg                        m_axi_wvalid_i = 1'b0;\n    reg                        m_axi_bready_i = 1'b0;\n    reg                        m_axi_wlast_i = 1'b0;\n    reg                        m_axi_wid_i = {P_ID_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]     wlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [P_NUM_ADDR_LOG:0]    awaddr_cnt = 0;\n  \n    /**************** Assign Write Channel Outputs ****************/\n    assign m_axi_wdata = {wdata_i, done};\n    assign write_burst_done_i = m_axi_wready && m_axi_wvalid_i && ((C_AXI_PROTOCOL==2) || m_axi_wlast_i);\n    assign m_axi_awvalid = m_axi_awvalid_i;\n    assign m_axi_wvalid = m_axi_wvalid_i;\n    assign m_axi_bready = m_axi_bready_i;\n    assign m_axi_wlast = m_axi_wlast_i;\n    assign m_axi_awaddr = m_axi_awaddr_i;\n    assign m_axi_awlen = m_axi_awlen_i;\n    assign m_axi_wid = m_axi_wid_i;\n    always @(posedge aclk) begin\n      m_axi_awprot <= dummy ? awprot_i : 3'b000;\n      m_axi_awsize <= dummy ? awsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_awburst <= dummy ? awburst_i : 2'b01;\n      m_axi_awlock <= dummy ? awlock_i : 1'b0;\n      m_axi_awcache <= dummy ? awcache_i : 4'h3;\n      m_axi_awqos <= dummy ? awqos_i : 4'h0;\n      m_axi_wstrb <= dummy ? wstrb_i : {P_M_AXI_DATA_BYTES{1'b1}};\n      m_axi_awuser <= dummy ?  awuser_i : 0;\n      m_axi_wuser <= dummy ?  wuser_i : 0;\n    end\n  \n    //**********************************************\n    // Write Channel: AWVALID, AWADDR, AWLEN, WVALID, WLAST, BREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_awvalid_i <= 1'b0;\n        m_axi_wvalid_i <= 1'b0;\n        awcnt_i <= C_NUM_TRANS;\n        wcnt_i <= C_NUM_TRANS;\n        xfer_w_i <= 8'h00;\n        m_axi_awlen_i <= 0;\n        m_axi_awaddr_i <= C_AXI_ADDR;\n        m_axi_awid_i <= 1;\n        m_axi_wid_i <= 0;\n        m_axi_wlast_i <= 1'b0;\n        wlen_i <= 0;\n        wid_i <= 0;\n        awaddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_awvalid_i <= 1'b0;\n          awcnt_i <= awcnt_i - 1;\n          if (awaddr_cnt == 1) begin\n            m_axi_awaddr_i <= dummy ? awaddr_i : C_AXI_ADDR;\n            awaddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_awaddr_i <= m_axi_awaddr_i + 32'h10000;\n            awaddr_cnt <= awaddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_awlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_awlen_i <= dummy ? awlen_i : 0;\n          end else begin\n            m_axi_awlen_i <= (m_axi_awlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_awid_i == C_NUM_ID)) begin\n            m_axi_awid <= dummy ? awid_i : 0;\n            m_axi_awid_i <= 1;\n          end else begin\n            m_axi_awid <= m_axi_awid_i;\n            m_axi_awid_i <= m_axi_awid_i + 1;\n          end\n        end else if (~m_axi_wvalid_i) begin\n          if (awcnt_i != 0) begin\n            m_axi_awvalid_i <= 1'b1;\n          end\n        end\n  \n        /**************** Write Data Channel ****************/\n\n        if (m_axi_wready && m_axi_wvalid_i) begin\n          xfer_w_i <= xfer_w_i - 1'b1;\n          if (m_axi_wlast_i) begin\n            m_axi_wvalid_i <= 1'b0;\n            wcnt_i <= wcnt_i - 1'b1;\n          end else begin\n            m_axi_wlast_i <=  (xfer_w_i == 1);\n          end\n        end else if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_wvalid_i <= 1'b1;\n          xfer_w_i <= m_axi_awlen_i;\n          m_axi_wlast_i <= (m_axi_awlen_i==0);\n          m_axi_wid_i <= m_axi_awid_i;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: WDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        wdata_i <= (m_axi_wvalid_i && m_axi_wready) ? {wdata_i[C_AXI_DATA_WIDTH-2 : 0], ~wdata_i[C_AXI_DATA_WIDTH-1]} : wdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      awaddr_i <= {awaddr_i, ~awaddr_i[C_AXI_ADDR_WIDTH]};\n      awprot_i <= {awprot_i[3-2:0], ~awprot_i[3-1]};\n      wstrb_i <= {wstrb_i, ~wstrb_i[C_AXI_DATA_WIDTH/8-1]};\n      awlen_i <= {awlen_i, ~awlen_i[P_LEN_WIDTH-1]};\n      awsize_i <= {awsize_i, ~awsize_i[3-1]};\n      awburst_i <= {awburst_i, ~awburst_i[2-1]};\n      awlock_i <= {awlock_i, ~awlock_i[2-1]};\n      awcache_i <= {awcache_i, ~awcache_i[4-1]};\n      awqos_i <= {awqos_i, ~awqos_i[4-1]};\n      awid_i <= {awid_i, ~awid_i[P_ID_WIDTH-1]};\n      awuser_i <= {awuser_i, ~awuser_i[C_AXI_AWUSER_WIDTH]};\n      wuser_i <= {wuser_i, ~wuser_i[C_AXI_WUSER_WIDTH]};\n    end\n  \n    //**********************************************\n    // Write Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_bready_i <= 1'b0;\n        bcnt_i <= C_NUM_TRANS;\n        bresp_i <= {2{1'b0}};\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n        bid_i <= {P_ID_WIDTH{1'b0}};\n        acc_b_i <= 3'b0;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_bvalid & m_axi_bready_i) begin\n          m_axi_bready_i <= 1'b0;\n          bresp_i <= m_axi_bresp;\n            acc_b_i[0] <= bresp_i[0];\n          buser_i <= m_axi_buser;\n            acc_b_i[1] <= buser_i[0];\n          bid_i <= m_axi_bid;\n            acc_b_i[2] <= bid_i[0];\n          bcnt_i <= bcnt_i - 1;\n        end else begin\n          bresp_i <= bresp_i>>1;\n          buser_i <= buser_i>>1;\n          bid_i <= bid_i>>1;\n          acc_b_i <= acc_b_i>>1;\n          if (m_axi_bvalid) begin\n            m_axi_bready_i <= 1'b1;\n          end\n        end\n      end\n    end\n\n\n  //**********************************************\n  // Assert Done\n  //**********************************************\n  always @(posedge aclk) begin\n    if (~aresetn) begin\n      done_d1 <= 1'b0;\n    end else begin\n      done_d1 <= done_i;\n    end\n  end\n\n  assign done = done_sel ? done_i : done_d1;\n  assign done_cycle = done_i & ~done_d1;\n  \n  always @ * begin\n    if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_readonly_done\n       done_i = rcnt_i==0;\n       done_sel = acc_r_i[0];\n    end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_writeonly_done\n       done_i = bcnt_i==0;\n       done_sel = acc_b_i[0];\n    end else begin : gen_readwrite_done\n       done_i = (rcnt_i==0) && (bcnt_i==0);\n       done_sel = acc_r_i[0] ^ acc_b_i[0];\n    end\n  end\n  \nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n  input  wire [3-1:0]                   s_axi_awprot,\n  input  wire                           s_axi_awvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_awready,\n  input  wire [3-1:0]                   s_axi_awsize,\n  input  wire [2-1:0]                   s_axi_awburst,\n  input  wire [4-1:0]                   s_axi_awcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_awlen,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_awlock,\n  input  wire [4-1:0]                   s_axi_awqos,\n  input  wire [4-1:0]                   s_axi_awregion,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_awid,\n  input  wire [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]   s_axi_awuser,\n  /**************** Write Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n  input  wire                           s_axi_wvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_wready,\n  input  wire                           s_axi_wlast,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_wid,\n  input  wire [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]    s_axi_wuser,\n  /**************** Write Response Channel Signals ****************/\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_bresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_bvalid,\n  input  wire                           s_axi_bready,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]    s_axi_buser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_bid = 'b0,\n  /**************** Read Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n  input  wire [3-1:0]                   s_axi_arprot,\n  input  wire                           s_axi_arvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_arready,\n  input  wire [3-1:0]                   s_axi_arsize,\n  input  wire [2-1:0]                   s_axi_arburst,\n  input  wire [4-1:0]                   s_axi_arcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_arlock,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_arlen,\n  input  wire [4-1:0]                   s_axi_arqos,\n  input  wire [4-1:0]                   s_axi_arregion,\n  input  wire [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]   s_axi_aruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_arid,\n  /**************** Read Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_rresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rvalid,\n  input  wire                           s_axi_rready,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]    s_axi_ruser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_rid = 'b0,\n  /**************** System Signals ****************/\n  input  wire                           aclk,\n  input  wire                           aresetn\n   );\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL == 1) ? 4 : 8;\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer P_S_AXI_DATA_BYTES = 32/8;\n  localparam integer P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n\n  /**************** Internal Wires/Regs - Global ****************/\n  reg                   areset = 1'b0;\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    /**************** Internal Wires/Regs - Read Channels ****************/\n    reg [8-1:0]                   xfer_r_cnt = 8'h00;\n    reg [16-1:0]                  arcnt_i = 16'h0000;\n    wire                          read_xaction_done_i;\n    reg [C_AXI_DATA_WIDTH-1:0]     rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]      arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg                           arvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     araddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   arprot_i = 3'b000;\n    reg [3-1:0]                   arsize_i = 3'b000;\n    reg [2-1:0]                   arburst_i = 2'b00;\n    reg [4-1:0]                   arcache_i = 4'b0000;\n    reg [1-1:0]     arlock_i = 1'b0;\n    reg [4-1:0]                   arqos_i = 4'b0000;\n    reg [4-1:0]                   arregion_i = 4'b0000;\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_RUSER_WIDTH:0]     ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_ar_i = 9'b0;\n    reg                           s_axi_rvalid_i = 1'b0;\n    reg                           s_axi_arready_i = 1'b0;\n    reg                           s_axi_rlast_i = 1'b0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign s_axi_rdata = rdata_i;\n    assign read_xaction_done_i = (s_axi_rready && s_axi_rvalid_i && s_axi_rlast_i);\n    assign s_axi_rvalid = s_axi_rvalid_i;\n    assign s_axi_arready = s_axi_arready_i;\n    assign s_axi_rlast = s_axi_rlast_i;\n    //**********************************************\n    // Read Channel: ARREADY, RVALID, RLAST, RID\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        xfer_r_cnt <= 8'h00;\n        arcnt_i <= 16'h0000;\n        arlen_i <= {P_LEN_WIDTH{1'b0}};\n        s_axi_rlast_i <= 1'b0;\n      end else begin\n        /**************** Read Address Channel ****************/\n        // arready\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_arready_i <= 1'b0;\n          arcnt_i <= arcnt_i + 1'b1;\n        end else if (~s_axi_rvalid_i) begin\n          s_axi_arready_i <= 1'b1;\n        end\n  \n        /**************** Read Data Channel ****************/\n        // rvalid\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_rvalid_i <= 1'b1;\n          s_axi_rid <= s_axi_arid;\n          s_axi_ruser <= ruser_i;\n        end else if(read_xaction_done_i) begin\n          s_axi_rvalid_i <= 1'b0;\n        end\n  \n        // rlast\n        if(s_axi_rready && s_axi_rvalid_i) begin\n          xfer_r_cnt <= xfer_r_cnt - 1;\n          if(xfer_r_cnt == 1) begin\n            s_axi_rlast_i <= 1'b1;\n          end\n        end else if(s_axi_arready_i && s_axi_arvalid) begin\n          xfer_r_cnt <= s_axi_arlen;\n          s_axi_rlast_i <= (s_axi_arlen==0);\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Read Channel: RDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        rdata_i <= (s_axi_rready && s_axi_rvalid_i) ? {rdata_i[C_AXI_DATA_WIDTH-2 : 0], ~rdata_i[C_AXI_DATA_WIDTH-1]} : rdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_rresp <= {2{1'b0}};\n      end else if (~s_axi_rvalid_i) begin\n        s_axi_rresp <= {acc_ar_i[0], 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n      end else begin\n        ruser_i <= (s_axi_arready_i && s_axi_arvalid) ? {ruser_i, ~ruser_i[C_AXI_RUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        araddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        arprot_i <= {3{1'b0}};\n        arsize_i <= {3{1'b0}};\n        arburst_i <= {2{1'b0}};\n        arcache_i <= {4{1'b0}};\n        arlock_i <= {1{1'b0}};\n        arqos_i <= {4{1'b0}};\n        arregion_i <= {4{1'b0}};\n        aruser_i <= {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n        acc_ar_i <= 9'b0;\n      end else if (s_axi_arvalid) begin\n        // Register Inputs\n        araddr_i <= s_axi_araddr;\n          acc_ar_i[0] <= araddr_i[0];\n        arprot_i <= s_axi_arprot;\n          acc_ar_i[1] <= arprot_i[0];\n        arsize_i <= s_axi_arsize;\n          acc_ar_i[2] <= arsize_i[0];\n        arburst_i <= s_axi_arburst;\n          acc_ar_i[3] <= arburst_i[0];\n        arcache_i <= s_axi_arcache;\n          acc_ar_i[4] <= arcache_i[0];\n        arlock_i <= s_axi_arlock;\n          acc_ar_i[5] <= arlock_i[0];\n        arqos_i <= s_axi_arqos;\n          acc_ar_i[6] <= arqos_i[0];\n        arregion_i <= s_axi_arregion;\n          acc_ar_i[7] <= arregion_i[0];\n        aruser_i <= s_axi_aruser;\n          acc_ar_i[8] <= aruser_i[0];\n      end else begin\n        araddr_i <= araddr_i>>1;\n        arprot_i <= arprot_i>>1;\n        arsize_i <= arsize_i>>1;\n        arburst_i <= arburst_i>>1;\n        arcache_i <= arcache_i>>1;\n        arlock_i <= arlock_i>>1;\n        arqos_i <= arqos_i>>1;\n        arregion_i <= arregion_i>>1;\n        aruser_i <= aruser_i>>1;\n        acc_ar_i <= acc_ar_i>>1;\n      end\n    end\n  \n  \n    /**************** Internal Wires/Regs - Write Channels ****************/\n    wire                          write_burst_done_i;\n    reg [16-1:0]                  awcnt_i = 16'h0000;\n    reg                           awvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     awaddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   awprot_i = 3'b000;\n    reg [3-1:0]                   awsize_i = 3'b000;\n    reg [2-1:0]                   awburst_i = 2'b00;\n    reg [4-1:0]                   awcache_i = 4'b0000;\n    reg [P_LEN_WIDTH-1:0]      awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [1-1:0]     awlock_i = 1'b0;\n    reg [4-1:0]                   awqos_i = 4'b0000;\n    reg [4-1:0]                   awregion_i = 4'b0000;\n    reg [C_AXI_AWUSER_WIDTH:0]     awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg                           wvalid_i = 1'b0;\n    reg [C_AXI_DATA_WIDTH-1:0]     wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH/8-1:0]   wstrb_i = {(C_AXI_DATA_WIDTH/8){1'b0}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_BUSER_WIDTH:0]     buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_aw_i = 9'b0;\n    reg [3:0]                     acc_w_i = 4'b0;\n    reg                           s_axi_bvalid_i = 1'b0;\n    reg                           s_axi_awready_i = 1'b0;\n    reg                           s_axi_wready_i = 1'b0;\n    /**************** Assign Write Channel Outputs ****************/\n    assign write_burst_done_i =s_axi_wready_i && s_axi_wvalid && ((C_AXI_PROTOCOL == 2) ? 1'b1 : s_axi_wlast);\n    assign s_axi_bvalid = s_axi_bvalid_i;\n    assign s_axi_awready = s_axi_awready_i;\n    assign s_axi_wready = s_axi_wready_i;\n  \n    //**********************************************\n    // Write Channel: AWREADY, WREADY, BVALID, BID\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awcnt_i <= 16'h0000;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        /**************** Write Address Channel ****************/\n        // awready\n        if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_awready_i <= 1'b0;\n          awcnt_i <= awcnt_i + 1'b1;\n          s_axi_bid <= s_axi_awid;\n          s_axi_buser <= buser_i;\n        end else if(~s_axi_wready_i & ~s_axi_bvalid_i) begin\n          s_axi_awready_i <= 1'b1;\n        end\n  \n        /**************** Write Data Channel ****************/\n        // wready\n        if(write_burst_done_i) begin\n          s_axi_wready_i <= 1'b0;\n        end else if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_wready_i <= 1'b1;\n        end\n  \n        /**************** Write Response Channel ****************/\n        // bvalid\n        if(write_burst_done_i) begin\n          s_axi_bvalid_i <= 1'b1;\n        end else if(s_axi_bready && s_axi_bvalid_i) begin\n          s_axi_bvalid_i <= 1'b0;\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Write Channel: BRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_bresp <= {2{1'b0}};\n      end else if (~s_axi_bvalid_i) begin\n        s_axi_bresp <= {(acc_aw_i[0] ^ acc_w_i[0]), 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: BUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (aresetn) begin\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n      end else begin\n        buser_i <= (s_axi_awready_i && s_axi_awvalid) ? {buser_i, ~buser_i[C_AXI_BUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Write Address Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awaddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        awprot_i <= {3{1'b0}};\n        awsize_i <= {3{1'b0}};\n        awburst_i <= {2{1'b0}};\n        awcache_i <= {4{1'b0}};\n        awlen_i <= {P_LEN_WIDTH{1'b0}};\n        awlock_i <= {1{1'b0}};\n        awqos_i <= {4{1'b0}};\n        awregion_i <= {4{1'b0}};\n        awuser_i <= {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n        acc_aw_i <= 9'b0;\n      end else if (s_axi_awvalid) begin\n        // Register Inputs\n        awaddr_i <= s_axi_awaddr;\n          acc_aw_i[0] <= awaddr_i[0];\n        awprot_i <= s_axi_awprot;\n          acc_aw_i[1] <= awprot_i[0];\n        awsize_i <= s_axi_awsize;\n          acc_aw_i[2] <= awsize_i[0];\n        awburst_i <= s_axi_awburst;\n          acc_aw_i[3] <= awburst_i[0];\n        awcache_i <= s_axi_awcache;\n          acc_aw_i[4] <= awcache_i[0];\n        awlock_i <= s_axi_awlock;\n          acc_aw_i[5] <= awlock_i[0];\n        awqos_i <= s_axi_awqos;\n          acc_aw_i[6] <= awqos_i[0];\n        awregion_i <= s_axi_awregion;\n          acc_aw_i[7] <= awregion_i[0];\n        awuser_i <= s_axi_awuser;\n          acc_aw_i[8] <= awuser_i[0];\n      end else begin\n        awaddr_i <= awaddr_i>>1;\n        awprot_i <= awprot_i>>1;\n        awsize_i <= awsize_i>>1;\n        awburst_i <= awburst_i>>1;\n        awcache_i <= awcache_i>>1;\n        awlock_i <= awlock_i>>1;\n        awqos_i <= awqos_i>>1;\n        awregion_i <= awregion_i>>1;\n        awuser_i <= awuser_i>>1;\n        acc_aw_i <= acc_aw_i>>1;\n      end\n    end\n  \n    //**********************************************\n    // Write Data Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        wstrb_i <= {(C_AXI_DATA_WIDTH/8){1'b0}};\n        wuser_i <= {(C_AXI_WUSER_WIDTH+1){1'b0}};\n        acc_w_i <= 4'b0;\n      end else if (s_axi_wvalid) begin\n        // Register Inputs\n        wdata_i <= s_axi_wdata;\n          acc_w_i[0] <= wdata_i[0];\n        wstrb_i <= s_axi_wstrb;\n          acc_w_i[1] <= wstrb_i[0];\n        wuser_i <= s_axi_wuser;\n          acc_w_i[2] <= wuser_i[0];\n      end else begin\n        wdata_i <= wdata_i>>1;\n        wstrb_i <= wstrb_i>>1;\n        wuser_i <= wuser_i>>1;\n        acc_w_i <= acc_w_i>>1;\n      end\n    end\n  \nendmodule\n\n\n\n//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_22_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \n(* autopipeline_module=\"yes\" *)\nmodule axi_register_slice_v2_1_22_auto_slr #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n    wire                    handshake_pipe;\n    wire                    ready_pipe;\n    wire [C_DATA_WIDTH-1:0] payload_pipe;\n    (* keep=\"true\" *)                                                                reg  s_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  s_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  s_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  s_areset_resp2 = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  m_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  m_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_areset_resp2 = 1'b0;\n    \n  // Global Reset pipelining\n  \n    always @(posedge ACLK) begin\n      s_aclear       <= ~ARESETN;\n      s_areset_fwd   <= ~ARESETN; \n      s_areset_resp  <= s_areset_fwd;  // Auto-pipeline\n      s_areset_resp2 <= s_areset_resp; // Auto-pipeline\n    end\n    \n    always @(posedge ACLK) begin\n      m_aclear       <= ~ARESETN;\n      m_areset_fwd   <= ~ARESETN; \n      m_areset_resp  <= m_areset_fwd;  // Auto-pipeline\n      m_areset_resp2 <= m_areset_resp; // Auto-pipeline\n    end\n    \n  // Source-side submodule\n    \n    axi_register_slice_v2_1_22_auto_src #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_src\n      (\n       .ACLK             (ACLK),    \n       .s_aclear         (s_aclear),\n       .s_areset_resp2   (s_areset_resp2),  \n       .S_VALID          (S_VALID),  \n       .S_READY          (S_READY), \n       .S_PAYLOAD_DATA   (S_PAYLOAD_DATA),\n       .ready_pipe        (ready_pipe), \n       .handshake_pipe    (handshake_pipe),\n       .payload_pipe      (payload_pipe)  \n      );\n    \n  // Destination-side submodule\n    \n    axi_register_slice_v2_1_22_auto_dest #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_dest\n      (\n       .ACLK           (ACLK),    \n       .m_aclear       (m_aclear),\n       .m_areset_resp2 (m_areset_resp2),  \n       .M_READY        (M_READY), \n       .M_VALID        (M_VALID),  \n       .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n       .handshake_pipe  (handshake_pipe),\n       .ready_pipe      (ready_pipe),  \n       .payload_pipe    (payload_pipe)  \n      );\n    \nendmodule  // auto_slr\n\nmodule axi_register_slice_v2_1_22_auto_src #\n  (\n   parameter integer C_DATA_WIDTH = 32\n  )\n  (\n   input  wire ACLK,\n   input  wire s_aclear,\n   input  wire s_areset_resp2,\n   input  wire S_VALID,\n   input  wire ready_pipe,\n   output wire S_READY,\n   output wire handshake_pipe,\n   output wire  [C_DATA_WIDTH-1:0] payload_pipe,\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA\n   );\n    \n   (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  [C_DATA_WIDTH-1:0] payload_pipe_r;\n    (* keep=\"true\" *) reg [2:0] s_aresetn_resp4 = 3'b000;\n    wire s_aresetn_resp3;\n    wire s_aresetn_d;\n    wire s_aresetn_q;\n    wire s_handshake_d;\n    wire s_ready_i;\n    \n    assign S_READY = s_ready_i & s_aresetn_q;\n    assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;\n    assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;\n    assign payload_pipe = payload_pipe_r;\n    \n    always @(posedge ACLK or posedge s_aclear) begin\n      if (s_aclear) begin\n        s_aresetn_resp4 <= 3'b000;\n      end else begin\n        s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      payload_pipe_r <= S_PAYLOAD_DATA;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) s_aresetn_resp3_inst (\n        .Q   (s_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~s_areset_resp2)\n     );\n    \n    // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (s_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_aresetn_d)\n     );\n    \n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (handshake_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_handshake_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (s_ready_i),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (ready_pipe)\n     );\n    \nendmodule  // auto_src\n\nmodule axi_register_slice_v2_1_22_auto_dest #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   input  wire ACLK,\n   input  wire m_aclear,\n   input  wire m_areset_resp2,\n   input  wire M_READY,\n   input  wire handshake_pipe,\n   output wire ready_pipe,\n   output wire M_VALID,\n   input  wire [C_DATA_WIDTH-1:0] payload_pipe,\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n   );\n    \n    (* keep=\"true\" *) reg [2:0] m_aresetn_resp4 = 3'b000;\n    wire m_aresetn_resp3;\n    wire m_aresetn_d;\n    wire m_aresetn_q;\n    wire m_valid_i;\n    wire pop;\n    wire m_ready_d;\n    wire m_handshake_q;\n    reg  [C_DATA_WIDTH-1:0] m_payload_q;\n    \n    assign M_VALID = m_valid_i;\n    assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;\n    assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;\n    assign pop     = M_READY & m_valid_i;\n    \n    always @(posedge ACLK or posedge m_aclear) begin\n      if (m_aclear) begin\n        m_aresetn_resp4 <= 3'b000;\n      end else begin\n        m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      m_payload_q <= payload_pipe;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) m_aresetn_resp3_inst (\n        .Q   (m_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~m_areset_resp2)\n     );\n    \n    // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (m_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_aresetn_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (m_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (handshake_pipe)\n     );\n    \n    (* autopipeline_group=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (ready_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_ready_d)\n     );\n    \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  (5)  \n      )\n      srl_fifo\n      (\n       .aclk    (ACLK),    \n       .areset  (~m_aresetn_q),\n       .aclear  (m_aclear),  \n       .s_mesg  (m_payload_q),  \n       .s_valid (m_handshake_q), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      );\n    \nendmodule  // auto_dest\n\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      reg s_valid_d;\n      reg s_ready_d = 1'b0;\n      reg s_ready_reg = 1'b0;\n      reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_22_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_RESP_MIDDLE2_LATENCY = C_PIPELINES_SLAVE + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_22_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      .ACLK           (ACLK),\n      .ARESETN         (ARESETN),\n      .S_PAYLOAD_DATA (S_PAYLOAD_DATA),\n      .S_VALID        (S_VALID),\n      .S_READY        (S_READY),\n      .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n      .M_VALID        (M_VALID),\n      .M_READY        (M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_reset;\n    wire src_ready;\n    wire dummy_reset;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  ( C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( dummy_reset   ) ,\n        .laguna_s_reset_in  ( src_reset   ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset   ) ,\n        .laguna_m_reset_in  ( src_reset  ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset2   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n      \n  end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] mid_payload;\n    wire mid_handshake;\n    wire mid_ready;\n    wire mid_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n    wire dummy_reset3;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( mid_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( mid_reset    ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset3   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset3   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out (  dummy_reset2  ) ,\n        .laguna_m_reset_in  ( mid_reset   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE2_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( mid_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2   ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset3   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset3    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n   \n  generate\n\n  (* keep=\"true\" *) reg s_reset_dd = 1'b0;\n  (* keep=\"true\" *) reg m_reset_dd = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n  \n  assign laguna_s_reset_out = laguna_s_reset_out_i;\n  assign laguna_m_reset_out = laguna_m_reset_out_i;\n  \n  always @(posedge ACLK) begin\n    laguna_s_reset_in_d <= laguna_s_reset_in;\n    laguna_m_reset_in_d <= laguna_m_reset_in;\n    s_reset_dd <= laguna_s_reset_in_d;\n    m_reset_dd <= laguna_m_reset_in_d;\n    laguna_s_reset_out_i <= C_PIPELINES==0 ? laguna_m_reset_in_d : m_reset_dd;\n    laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;\n  end\n  \n  wire ACLEAR;\n  assign ACLEAR = ~ARESETN;\n  \n  if (1) begin : common\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire laguna_s_handshake_q;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, laguna_m_ready_d}; \n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else if (p==C_PIPELINES+1) begin\n          laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n\n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = handshake_i[C_PIPELINES];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_m_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* keep=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_22_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_m_reset_out = laguna_m_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_m_reset_in_d <= laguna_m_reset_in;\n      aresetn_d <= C_CHANNEL==P_FORWARD ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? areset_dly[15]  : laguna_m_reset_in_d;\n      laguna_m_reset_out_i <= areset_d;  // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n  \n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* keep=\"true\" *)  reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      ready_d <= {ready_d, laguna_m_ready_d}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid_q;\n      assign payload_valid_d = (p==0) ? (S_VALID & s_ready_i) : handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==C_PIPELINES) begin\n          laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else if (p==0) begin\n          payload_data <= S_PAYLOAD_DATA;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n      \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_s_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* keep=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_s_reset_out = laguna_s_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_s_reset_in_d <= laguna_s_reset_in;\n      aresetn_d <= C_CHANNEL==P_RESPONSE ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? laguna_s_reset_in_d : areset_dly[15];\n      laguna_s_reset_out_i <= areset_d;  // For forward channels, reflect laguna_s_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n\n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    wire laguna_s_handshake_q;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      laguna_s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n        \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n        \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)  \n      )\n      srl_fifo_0\n      (\n       .aclk    (ACLK),    \n       .areset  (areset_d),  \n       .aclear  (ACLEAR),\n       .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n       .s_valid (push), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      ); \n  \n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  reg areset_d = 1'b0;\n  reg [3:0] areset_dly = 4'b0;\n  always @(posedge ACLK) begin\n    areset_dly <= {4{~ARESETN}} | (areset_dly<<1);\n    areset_d <= areset_dly[3];\n  end\n  \n  if (1) begin : common\n    reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID & s_ready_i;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* keep=\"true\" *)  reg payload_valid = 1'b0;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          payload_data <= S_PAYLOAD_DATA;\n          payload_valid <= S_VALID & s_ready_i & ~areset_d;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n          payload_valid <= handshake_i[((p>0)?(p-1):0)];\n        end\n      end\n    end\n    \n    if (C_PIPELINES==0) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),\n         .aclear  (1'b0),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire                        aclear,  // Async clear\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    wire [1:0] state;  // State vector register\n    reg  [1:0] next;           // Next state value\n    wire [1:0] next_qual;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    reg  m_valid_d;\n    wire m_valid_q;\n    \n    assign m_valid = m_valid_q;\n    assign next_qual = areset ? K_EMPTY : next;\n    assign m_mesg  = mesg_reg;\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_mvalid_inst (\n        .Q   (m_valid_q),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (m_valid_d)\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state0_inst (\n        .Q   (state[0]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[0])\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state1_inst (\n        .Q   (state[1]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[1])\n     );\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      m_valid_d = m_valid_q & ~areset;\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid & ~areset) begin\n            next = K_HAS1;\n            m_valid_d = 1'b0;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              m_valid_d = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n              m_valid_d = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          m_valid_d = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      (* keep_hierarchy = \"yes\" *) axi_register_slice_v2_1_22_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule  // axic_reg_srl_fifo\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   //   16 -> Auto-pipelining\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_RESERVE_MODE = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n  \n  if (C_RESERVE_MODE==1) begin : gen_reserve_si\n  \n    axi_register_slice_v2_1_22_test_slave #(\n      .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n      .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n      .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n      .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n      .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n      .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n      .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n      .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n      .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .s_axi_awaddr(s_axi_awaddr),\n      .s_axi_awprot(s_axi_awprot),\n      .s_axi_awvalid(s_axi_awvalid),\n      .s_axi_awready(s_axi_awready),\n      .s_axi_awsize(s_axi_awsize),\n      .s_axi_awburst(s_axi_awburst),\n      .s_axi_awcache(s_axi_awcache),\n      .s_axi_awlen(s_axi_awlen),\n      .s_axi_awlock(s_axi_awlock),\n      .s_axi_awqos(s_axi_awqos),\n      .s_axi_awregion(s_axi_awregion),\n      .s_axi_awid(s_axi_awid),\n      .s_axi_awuser(s_axi_awuser),\n      .s_axi_wdata(s_axi_wdata),\n      .s_axi_wstrb(s_axi_wstrb),\n      .s_axi_wvalid(s_axi_wvalid),\n      .s_axi_wready(s_axi_wready),\n      .s_axi_wlast(s_axi_wlast),\n      .s_axi_wid(s_axi_wid),\n      .s_axi_wuser(s_axi_wuser),\n      .s_axi_bresp(s_axi_bresp),\n      .s_axi_bvalid(s_axi_bvalid),\n      .s_axi_bready(s_axi_bready),\n      .s_axi_buser(s_axi_buser),\n      .s_axi_bid(s_axi_bid),\n      .s_axi_araddr(s_axi_araddr),\n      .s_axi_arprot(s_axi_arprot),\n      .s_axi_arvalid(s_axi_arvalid),\n      .s_axi_arready(s_axi_arready),\n      .s_axi_arsize(s_axi_arsize),\n      .s_axi_arburst(s_axi_arburst),\n      .s_axi_arcache(s_axi_arcache),\n      .s_axi_arlock(s_axi_arlock),\n      .s_axi_arlen(s_axi_arlen),\n      .s_axi_arqos(s_axi_arqos),\n      .s_axi_arregion(s_axi_arregion),\n      .s_axi_aruser(s_axi_aruser),\n      .s_axi_arid(s_axi_arid),\n      .s_axi_rdata(s_axi_rdata),\n      .s_axi_rresp(s_axi_rresp),\n      .s_axi_rvalid(s_axi_rvalid),\n      .s_axi_rready(s_axi_rready),\n      .s_axi_rlast(s_axi_rlast),\n      .s_axi_ruser(s_axi_ruser),\n      .s_axi_rid(s_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign m_axi_awid     = 0;\n     assign m_axi_awaddr   = 0;\n     assign m_axi_awlen    = 0;\n     assign m_axi_awsize   = 0;\n     assign m_axi_awburst  = 0;\n     assign m_axi_awlock   = 0;\n     assign m_axi_awcache  = 0;\n     assign m_axi_awprot   = 0;\n     assign m_axi_awregion = 0;\n     assign m_axi_awqos    = 0;\n     assign m_axi_awuser   = 0;\n     assign m_axi_awvalid  = 0;\n     assign m_axi_wid      = 0;\n     assign m_axi_wdata    = 0;\n     assign m_axi_wstrb    = 0;\n     assign m_axi_wlast    = 0;\n     assign m_axi_wuser    = 0;\n     assign m_axi_wvalid   = 0;\n     assign m_axi_bready   = 0;\n     assign m_axi_arid     = 0;\n     assign m_axi_araddr   = 0;\n     assign m_axi_arlen    = 0;\n     assign m_axi_arsize   = 0;\n     assign m_axi_arburst  = 0;\n     assign m_axi_arlock   = 0;\n     assign m_axi_arcache  = 0;\n     assign m_axi_arprot   = 0;\n     assign m_axi_arregion = 0;\n     assign m_axi_arqos    = 0;\n     assign m_axi_aruser   = 0;\n     assign m_axi_arvalid  = 0;\n     assign m_axi_rready   = 0;\n      \n  end else if (C_RESERVE_MODE==2) begin : gen_reserve_mi\n    \n    axi_register_slice_v2_1_22_test_master #(\n    .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n    .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .m_axi_awaddr(m_axi_awaddr),\n      .m_axi_awprot(m_axi_awprot),\n      .m_axi_awvalid(m_axi_awvalid),\n      .m_axi_awready(m_axi_awready),\n      .m_axi_awsize(m_axi_awsize),\n      .m_axi_awburst(m_axi_awburst),\n      .m_axi_awcache(m_axi_awcache),\n      .m_axi_awlen(m_axi_awlen),\n      .m_axi_awlock(m_axi_awlock),\n      .m_axi_awqos(m_axi_awqos),\n      .m_axi_awid(m_axi_awid),\n      .m_axi_awuser(m_axi_awuser),\n      .m_axi_wid(m_axi_wid),\n      .m_axi_wdata(m_axi_wdata),\n      .m_axi_wstrb(m_axi_wstrb),\n      .m_axi_wvalid(m_axi_wvalid),\n      .m_axi_wready(m_axi_wready),\n      .m_axi_wlast(m_axi_wlast),\n      .m_axi_wuser(m_axi_wuser),\n      .m_axi_bresp(m_axi_bresp),\n      .m_axi_bvalid(m_axi_bvalid),\n      .m_axi_bready(m_axi_bready),\n      .m_axi_buser(m_axi_buser),\n      .m_axi_bid(m_axi_bid),\n      .m_axi_araddr(m_axi_araddr),\n      .m_axi_arprot(m_axi_arprot),\n      .m_axi_arvalid(m_axi_arvalid),\n      .m_axi_arready(m_axi_arready),\n      .m_axi_arsize(m_axi_arsize),\n      .m_axi_arburst(m_axi_arburst),\n      .m_axi_arcache(m_axi_arcache),\n      .m_axi_arlen(m_axi_arlen),\n      .m_axi_arlock(m_axi_arlock),\n      .m_axi_arqos(m_axi_arqos),\n      .m_axi_arid(m_axi_arid),\n      .m_axi_aruser(m_axi_aruser),\n      .m_axi_rdata(m_axi_rdata),\n      .m_axi_rresp(m_axi_rresp),\n      .m_axi_rvalid(m_axi_rvalid),\n      .m_axi_rready(m_axi_rready),\n      .m_axi_rlast(m_axi_rlast),\n      .m_axi_ruser(m_axi_ruser),\n      .m_axi_rid(m_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign s_axi_awready = 0;\n     assign s_axi_wready  = 0;\n     assign s_axi_bid     = 0;\n     assign s_axi_bresp   = 0;\n     assign s_axi_buser   = 0;\n     assign s_axi_bvalid  = 0;\n     assign s_axi_arready = 0;\n     assign s_axi_rid     = 0;\n     assign s_axi_rdata   = 0;\n     assign s_axi_rresp   = 0;\n     assign s_axi_rlast   = 0;\n     assign s_axi_ruser   = 0;\n     assign s_axi_rvalid  = 0;\n\n  end else begin : gen_reg_slice  // Any normal reg-slice mode\n\n    axi_infrastructure_v1_1_0_axi2vector #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    axi2vector_0 ( \n      .s_axi_awid      ( s_axi_awid      ) ,\n      .s_axi_awaddr    ( s_axi_awaddr    ) ,\n      .s_axi_awlen     ( s_axi_awlen     ) ,\n      .s_axi_awsize    ( s_axi_awsize    ) ,\n      .s_axi_awburst   ( s_axi_awburst   ) ,\n      .s_axi_awlock    ( s_axi_awlock    ) ,\n      .s_axi_awcache   ( s_axi_awcache   ) ,\n      .s_axi_awprot    ( s_axi_awprot    ) ,\n      .s_axi_awqos     ( s_axi_awqos     ) ,\n      .s_axi_awuser    ( s_axi_awuser    ) ,\n      .s_axi_awregion  ( s_axi_awregion  ) ,\n      .s_axi_wid       ( s_axi_wid       ) ,\n      .s_axi_wdata     ( s_axi_wdata     ) ,\n      .s_axi_wstrb     ( s_axi_wstrb     ) ,\n      .s_axi_wlast     ( s_axi_wlast     ) ,\n      .s_axi_wuser     ( s_axi_wuser     ) ,\n      .s_axi_bid       ( s_axi_bid       ) ,\n      .s_axi_bresp     ( s_axi_bresp     ) ,\n      .s_axi_buser     ( s_axi_buser     ) ,\n      .s_axi_arid      ( s_axi_arid      ) ,\n      .s_axi_araddr    ( s_axi_araddr    ) ,\n      .s_axi_arlen     ( s_axi_arlen     ) ,\n      .s_axi_arsize    ( s_axi_arsize    ) ,\n      .s_axi_arburst   ( s_axi_arburst   ) ,\n      .s_axi_arlock    ( s_axi_arlock    ) ,\n      .s_axi_arcache   ( s_axi_arcache   ) ,\n      .s_axi_arprot    ( s_axi_arprot    ) ,\n      .s_axi_arqos     ( s_axi_arqos     ) ,\n      .s_axi_aruser    ( s_axi_aruser    ) ,\n      .s_axi_arregion  ( s_axi_arregion  ) ,\n      .s_axi_rid       ( s_axi_rid       ) ,\n      .s_axi_rdata     ( s_axi_rdata     ) ,\n      .s_axi_rresp     ( s_axi_rresp     ) ,\n      .s_axi_rlast     ( s_axi_rlast     ) ,\n      .s_axi_ruser     ( s_axi_ruser     ) ,\n      .s_awpayload ( s_awpayload ) ,\n      .s_wpayload  ( s_wpayload  ) ,\n      .s_bpayload  ( s_bpayload  ) ,\n      .s_arpayload ( s_arpayload ) ,\n      .s_rpayload  ( s_rpayload  ) \n    );\n    \n    axi_infrastructure_v1_1_0_vector2axi #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    vector2axi_0 ( \n      .m_awpayload    ( m_awpayload    ) ,\n      .m_wpayload     ( m_wpayload     ) ,\n      .m_bpayload     ( m_bpayload     ) ,\n      .m_arpayload    ( m_arpayload    ) ,\n      .m_rpayload     ( m_rpayload     ) ,\n      .m_axi_awid     ( m_axi_awid     ) ,\n      .m_axi_awaddr   ( m_axi_awaddr   ) ,\n      .m_axi_awlen    ( m_axi_awlen    ) ,\n      .m_axi_awsize   ( m_axi_awsize   ) ,\n      .m_axi_awburst  ( m_axi_awburst  ) ,\n      .m_axi_awlock   ( m_axi_awlock   ) ,\n      .m_axi_awcache  ( m_axi_awcache  ) ,\n      .m_axi_awprot   ( m_axi_awprot   ) ,\n      .m_axi_awqos    ( m_axi_awqos    ) ,\n      .m_axi_awuser   ( m_axi_awuser   ) ,\n      .m_axi_awregion ( m_axi_awregion ) ,\n      .m_axi_wid      ( m_axi_wid      ) ,\n      .m_axi_wdata    ( m_axi_wdata    ) ,\n      .m_axi_wstrb    ( m_axi_wstrb    ) ,\n      .m_axi_wlast    ( m_axi_wlast    ) ,\n      .m_axi_wuser    ( m_axi_wuser    ) ,\n      .m_axi_bid      ( m_axi_bid      ) ,\n      .m_axi_bresp    ( m_axi_bresp    ) ,\n      .m_axi_buser    ( m_axi_buser    ) ,\n      .m_axi_arid     ( m_axi_arid     ) ,\n      .m_axi_araddr   ( m_axi_araddr   ) ,\n      .m_axi_arlen    ( m_axi_arlen    ) ,\n      .m_axi_arsize   ( m_axi_arsize   ) ,\n      .m_axi_arburst  ( m_axi_arburst  ) ,\n      .m_axi_arlock   ( m_axi_arlock   ) ,\n      .m_axi_arcache  ( m_axi_arcache  ) ,\n      .m_axi_arprot   ( m_axi_arprot   ) ,\n      .m_axi_arqos    ( m_axi_arqos    ) ,\n      .m_axi_aruser   ( m_axi_aruser   ) ,\n      .m_axi_arregion ( m_axi_arregion ) ,\n      .m_axi_rid      ( m_axi_rid      ) ,\n      .m_axi_rdata    ( m_axi_rdata    ) ,\n      .m_axi_rresp    ( m_axi_rresp    ) ,\n      .m_axi_rlast    ( m_axi_rlast    ) ,\n      .m_axi_ruser    ( m_axi_ruser    ) \n    );\n    \n  end  // Reserve SI/MI branch\n\n  if ((C_REG_CONFIG_AW <= 9) && (C_RESERVE_MODE==0)) begin : aw\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 15) && (C_RESERVE_MODE==0)) begin : aw15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 16) && (C_RESERVE_MODE==0)) begin : aw16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) \n    )\n    aw_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if ((C_REG_CONFIG_W <= 9) && (C_RESERVE_MODE==0)) begin : w\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 15) && (C_RESERVE_MODE==0)) begin : w15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 16) && (C_RESERVE_MODE==0)) begin : w16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) \n    )\n    w_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if ((C_REG_CONFIG_B <= 9) && (C_RESERVE_MODE==0)) begin : b\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if ((C_REG_CONFIG_B == 15) && (C_RESERVE_MODE==0)) begin : b15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if ((C_REG_CONFIG_B == 16) && (C_RESERVE_MODE==0)) begin : b16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) \n    )\n    b_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if ((C_REG_CONFIG_AR <= 9) && (C_RESERVE_MODE==0)) begin : ar\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 15) && (C_RESERVE_MODE==0)) begin : ar15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 16) && (C_RESERVE_MODE==0)) begin : ar16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) \n    )\n    ar_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if ((C_REG_CONFIG_R <= 9) && (C_RESERVE_MODE==0)) begin : r\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 15) && (C_RESERVE_MODE==0)) begin : r15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 16) && (C_RESERVE_MODE==0)) begin : r16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) \n    )\n    r_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 4844}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m01_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m02_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m03_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_s00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_s01_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_crossbar:2.1\n// IP Revision: 23\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_xbar_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLKIF, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLKIF CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RSTIF RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [6:0] [13:7]\" *)\ninput wire [13 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]\" *)\ninput wire [15 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]\" *)\ninput wire [3 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [511:0] [1023:512]\" *)\ninput wire [1023 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [6:0] [13:7]\" *)\noutput wire [13 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]\" *)\noutput wire [3 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [6:0] [13:7]\" *)\ninput wire [13 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]\" *)\ninput wire [15 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]\" *)\ninput wire [3 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [6:0] [13:7]\" *)\noutput wire [13 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [511:0] [1023:512]\" *)\noutput wire [1023 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]\" *)\noutput wire [3 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_\\\nTHREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME S01_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0\\\n00, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI AWID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI AWID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI AWID [6:0] [27:21]\" *)\noutput wire [27 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI AWLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI AWLEN [7:0] [31:24]\" *)\noutput wire [31 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI AWBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI AWBURST [1:0] [7:6]\" *)\noutput wire [7 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWREGION [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWQOS [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [511:0] [1023:512], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [511:0] [1535:1024], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [511:0] [2047:1536]\" *)\noutput wire [2047 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WLAST [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI BID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI BID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI BID [6:0] [27:21]\" *)\ninput wire [27 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]\" *)\ninput wire [7 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI ARID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI ARID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI ARID [6:0] [27:21]\" *)\noutput wire [27 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI ARLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI ARLEN [7:0] [31:24]\" *)\noutput wire [31 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI ARBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI ARBURST [1:0] [7:6]\" *)\noutput wire [7 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARREGION [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARQOS [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI RID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI RID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI RID [6:0] [27:21]\" *)\ninput wire [27 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [511:0] [1023:512], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [511:0] [1535:1024], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [511:0] [2047:1536]\" *)\ninput wire [2047 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]\" *)\ninput wire [7 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RLAST [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE\\\n_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0\\\n.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ\\\n_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, \\\nHAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_rready;\n\n  axi_crossbar_v2_1_23_axi_crossbar #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_NUM_SLAVE_SLOTS(2),\n    .C_NUM_MASTER_SLOTS(4),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_PROTOCOL(0),\n    .C_NUM_ADDR_RANGES(1),\n    .C_M_AXI_BASE_ADDR(256'H0000000c00000000000000080000000000000004000000000000000000000000),\n    .C_M_AXI_ADDR_WIDTH(128'H00000022000000220000002200000022),\n    .C_S_AXI_BASE_ID(64'H0000004000000000),\n    .C_S_AXI_THREAD_ID_WIDTH(64'H0000000600000006),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_M_AXI_WRITE_CONNECTIVITY(128'H00000003000000030000000300000003),\n    .C_M_AXI_READ_CONNECTIVITY(128'H00000003000000030000000300000003),\n    .C_R_REGISTER(0),\n    .C_S_AXI_SINGLE_THREAD(64'H0000000000000000),\n    .C_S_AXI_WRITE_ACCEPTANCE(64'H0000002000000020),\n    .C_S_AXI_READ_ACCEPTANCE(64'H0000002000000020),\n    .C_M_AXI_WRITE_ISSUING(128'H00000010000000100000001000000010),\n    .C_M_AXI_READ_ISSUING(128'H00000010000000100000001000000010),\n    .C_S_AXI_ARB_PRIORITY(64'H0000000000000000),\n    .C_M_AXI_SECURE(128'H00000000000000000000000000000000),\n    .C_CONNECTIVITY_MODE(1)\n  ) inst (\n    .aclk(aclk),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(2'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(14'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(2'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(2'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(4'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(4'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 427}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020\n//Date        : Wed Dec 15 00:42:21 2021\n//Host        : a-21awsprq4sria running 64-bit Amazon Linux release 2 (Karoo)\n//Command     : generate_target cl_axi_interconnect.bd\n//Design      : cl_axi_interconnect\n//Purpose     : IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=cl_axi_interconnect,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=14,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}\" *) (* HW_HANDOFF = \"cl_axi_interconnect.hwdef\" *) \nmodule cl_axi_interconnect\n   (ACLK,\n    ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.ACLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF S00_AXI:M00_AXI:M01_AXI:M02_AXI:M03_AXI:S01_AXI, ASSOCIATED_RESET ARESETN, CLK_DOMAIN cl_axi_interconnect_ACLK, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input ACLK;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.ARESETN RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW\" *) input ARESETN;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M00_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M00_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARBURST\" *) output [1:0]M00_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE\" *) output [3:0]M00_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARID\" *) output [6:0]M00_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLEN\" *) output [7:0]M00_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK\" *) output [0:0]M00_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARPROT\" *) output [2:0]M00_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARQOS\" *) output [3:0]M00_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREADY\" *) input M00_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREGION\" *) output [3:0]M00_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE\" *) output [2:0]M00_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARVALID\" *) output M00_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWADDR\" *) output [63:0]M00_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWBURST\" *) output [1:0]M00_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE\" *) output [3:0]M00_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWID\" *) output [6:0]M00_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLEN\" *) output [7:0]M00_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK\" *) output [0:0]M00_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWPROT\" *) output [2:0]M00_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWQOS\" *) output [3:0]M00_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREADY\" *) input M00_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREGION\" *) output [3:0]M00_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE\" *) output [2:0]M00_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWVALID\" *) output M00_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BID\" *) input [6:0]M00_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BREADY\" *) output M00_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BRESP\" *) input [1:0]M00_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BVALID\" *) input M00_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RDATA\" *) input [511:0]M00_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RID\" *) input [6:0]M00_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RLAST\" *) input M00_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RREADY\" *) output M00_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RRESP\" *) input [1:0]M00_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RVALID\" *) input M00_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WDATA\" *) output [511:0]M00_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WLAST\" *) output M00_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WREADY\" *) input M00_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WSTRB\" *) output [63:0]M00_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WVALID\" *) output M00_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M01_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M01_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARBURST\" *) output [1:0]M01_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE\" *) output [3:0]M01_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARID\" *) output [6:0]M01_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARLEN\" *) output [7:0]M01_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK\" *) output [0:0]M01_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARPROT\" *) output [2:0]M01_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARQOS\" *) output [3:0]M01_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARREADY\" *) input M01_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARREGION\" *) output [3:0]M01_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE\" *) output [2:0]M01_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARVALID\" *) output M01_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWADDR\" *) output [63:0]M01_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWBURST\" *) output [1:0]M01_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE\" *) output [3:0]M01_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWID\" *) output [6:0]M01_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWLEN\" *) output [7:0]M01_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK\" *) output [0:0]M01_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWPROT\" *) output [2:0]M01_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWQOS\" *) output [3:0]M01_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWREADY\" *) input M01_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWREGION\" *) output [3:0]M01_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE\" *) output [2:0]M01_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWVALID\" *) output M01_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BID\" *) input [6:0]M01_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BREADY\" *) output M01_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BRESP\" *) input [1:0]M01_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BVALID\" *) input M01_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RDATA\" *) input [511:0]M01_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RID\" *) input [6:0]M01_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RLAST\" *) input M01_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RREADY\" *) output M01_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RRESP\" *) input [1:0]M01_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RVALID\" *) input M01_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WDATA\" *) output [511:0]M01_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WLAST\" *) output M01_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WREADY\" *) input M01_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WSTRB\" *) output [63:0]M01_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WVALID\" *) output M01_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M02_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M02_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARBURST\" *) output [1:0]M02_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE\" *) output [3:0]M02_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARID\" *) output [6:0]M02_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARLEN\" *) output [7:0]M02_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK\" *) output [0:0]M02_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARPROT\" *) output [2:0]M02_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARQOS\" *) output [3:0]M02_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARREADY\" *) input M02_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARREGION\" *) output [3:0]M02_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE\" *) output [2:0]M02_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARVALID\" *) output M02_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWADDR\" *) output [63:0]M02_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWBURST\" *) output [1:0]M02_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE\" *) output [3:0]M02_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWID\" *) output [6:0]M02_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWLEN\" *) output [7:0]M02_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK\" *) output [0:0]M02_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWPROT\" *) output [2:0]M02_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWQOS\" *) output [3:0]M02_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWREADY\" *) input M02_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWREGION\" *) output [3:0]M02_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE\" *) output [2:0]M02_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWVALID\" *) output M02_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BID\" *) input [6:0]M02_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BREADY\" *) output M02_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BRESP\" *) input [1:0]M02_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BVALID\" *) input M02_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RDATA\" *) input [511:0]M02_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RID\" *) input [6:0]M02_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RLAST\" *) input M02_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RREADY\" *) output M02_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RRESP\" *) input [1:0]M02_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RVALID\" *) input M02_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WDATA\" *) output [511:0]M02_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WLAST\" *) output M02_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WREADY\" *) input M02_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WSTRB\" *) output [63:0]M02_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WVALID\" *) output M02_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M03_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M03_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARBURST\" *) output [1:0]M03_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE\" *) output [3:0]M03_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARID\" *) output [6:0]M03_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARLEN\" *) output [7:0]M03_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK\" *) output [0:0]M03_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARPROT\" *) output [2:0]M03_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARQOS\" *) output [3:0]M03_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARREADY\" *) input M03_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARREGION\" *) output [3:0]M03_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE\" *) output [2:0]M03_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARVALID\" *) output M03_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWADDR\" *) output [63:0]M03_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWBURST\" *) output [1:0]M03_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE\" *) output [3:0]M03_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWID\" *) output [6:0]M03_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWLEN\" *) output [7:0]M03_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK\" *) output [0:0]M03_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWPROT\" *) output [2:0]M03_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWQOS\" *) output [3:0]M03_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWREADY\" *) input M03_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWREGION\" *) output [3:0]M03_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE\" *) output [2:0]M03_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWVALID\" *) output M03_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BID\" *) input [6:0]M03_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BREADY\" *) output M03_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BRESP\" *) input [1:0]M03_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BVALID\" *) input M03_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RDATA\" *) input [511:0]M03_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RID\" *) input [6:0]M03_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RLAST\" *) input M03_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RREADY\" *) output M03_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RRESP\" *) input [1:0]M03_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RVALID\" *) input M03_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WDATA\" *) output [511:0]M03_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WLAST\" *) output M03_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WREADY\" *) input M03_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WSTRB\" *) output [63:0]M03_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WVALID\" *) output M03_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S00_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 6, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 32, NUM_READ_THREADS 16, NUM_WRITE_OUTSTANDING 32, NUM_WRITE_THREADS 16, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) input [63:0]S00_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARBURST\" *) input [1:0]S00_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE\" *) input [3:0]S00_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARID\" *) input [5:0]S00_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLEN\" *) input [7:0]S00_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK\" *) input [0:0]S00_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARPROT\" *) input [2:0]S00_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARQOS\" *) input [3:0]S00_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREADY\" *) output S00_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREGION\" *) input [3:0]S00_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE\" *) input [2:0]S00_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARVALID\" *) input S00_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWADDR\" *) input [63:0]S00_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWBURST\" *) input [1:0]S00_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE\" *) input [3:0]S00_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWID\" *) input [5:0]S00_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLEN\" *) input [7:0]S00_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK\" *) input [0:0]S00_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWPROT\" *) input [2:0]S00_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWQOS\" *) input [3:0]S00_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREADY\" *) output S00_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREGION\" *) input [3:0]S00_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE\" *) input [2:0]S00_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWVALID\" *) input S00_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BID\" *) output [5:0]S00_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BREADY\" *) input S00_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BRESP\" *) output [1:0]S00_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BVALID\" *) output S00_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RDATA\" *) output [511:0]S00_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RID\" *) output [5:0]S00_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RLAST\" *) output S00_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RREADY\" *) input S00_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RRESP\" *) output [1:0]S00_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RVALID\" *) output S00_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WDATA\" *) input [511:0]S00_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WLAST\" *) input S00_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WREADY\" *) output S00_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WSTRB\" *) input [63:0]S00_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WVALID\" *) input S00_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S01_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 6, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 32, NUM_READ_THREADS 16, NUM_WRITE_OUTSTANDING 32, NUM_WRITE_THREADS 16, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) input [63:0]S01_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARBURST\" *) input [1:0]S01_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE\" *) input [3:0]S01_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARID\" *) input [5:0]S01_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARLEN\" *) input [7:0]S01_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK\" *) input [0:0]S01_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARPROT\" *) input [2:0]S01_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARQOS\" *) input [3:0]S01_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARREADY\" *) output S01_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARREGION\" *) input [3:0]S01_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE\" *) input [2:0]S01_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARVALID\" *) input S01_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWADDR\" *) input [63:0]S01_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWBURST\" *) input [1:0]S01_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE\" *) input [3:0]S01_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWID\" *) input [5:0]S01_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWLEN\" *) input [7:0]S01_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK\" *) input [0:0]S01_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWPROT\" *) input [2:0]S01_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWQOS\" *) input [3:0]S01_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWREADY\" *) output S01_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWREGION\" *) input [3:0]S01_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE\" *) input [2:0]S01_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWVALID\" *) input S01_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BID\" *) output [5:0]S01_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BREADY\" *) input S01_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BRESP\" *) output [1:0]S01_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BVALID\" *) output S01_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RDATA\" *) output [511:0]S01_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RID\" *) output [5:0]S01_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RLAST\" *) output S01_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RREADY\" *) input S01_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RRESP\" *) output [1:0]S01_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RVALID\" *) output S01_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WDATA\" *) input [511:0]S01_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WLAST\" *) input S01_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WREADY\" *) output S01_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WSTRB\" *) input [63:0]S01_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WVALID\" *) input S01_AXI_wvalid;\n\n  wire ACLK_1;\n  wire ARESETN_1;\n  wire [63:0]S00_AXI_1_ARADDR;\n  wire [1:0]S00_AXI_1_ARBURST;\n  wire [3:0]S00_AXI_1_ARCACHE;\n  wire [5:0]S00_AXI_1_ARID;\n  wire [7:0]S00_AXI_1_ARLEN;\n  wire [0:0]S00_AXI_1_ARLOCK;\n  wire [2:0]S00_AXI_1_ARPROT;\n  wire [3:0]S00_AXI_1_ARQOS;\n  wire S00_AXI_1_ARREADY;\n  wire [3:0]S00_AXI_1_ARREGION;\n  wire [2:0]S00_AXI_1_ARSIZE;\n  wire S00_AXI_1_ARVALID;\n  wire [63:0]S00_AXI_1_AWADDR;\n  wire [1:0]S00_AXI_1_AWBURST;\n  wire [3:0]S00_AXI_1_AWCACHE;\n  wire [5:0]S00_AXI_1_AWID;\n  wire [7:0]S00_AXI_1_AWLEN;\n  wire [0:0]S00_AXI_1_AWLOCK;\n  wire [2:0]S00_AXI_1_AWPROT;\n  wire [3:0]S00_AXI_1_AWQOS;\n  wire S00_AXI_1_AWREADY;\n  wire [3:0]S00_AXI_1_AWREGION;\n  wire [2:0]S00_AXI_1_AWSIZE;\n  wire S00_AXI_1_AWVALID;\n  wire [5:0]S00_AXI_1_BID;\n  wire S00_AXI_1_BREADY;\n  wire [1:0]S00_AXI_1_BRESP;\n  wire S00_AXI_1_BVALID;\n  wire [511:0]S00_AXI_1_RDATA;\n  wire [5:0]S00_AXI_1_RID;\n  wire S00_AXI_1_RLAST;\n  wire S00_AXI_1_RREADY;\n  wire [1:0]S00_AXI_1_RRESP;\n  wire S00_AXI_1_RVALID;\n  wire [511:0]S00_AXI_1_WDATA;\n  wire S00_AXI_1_WLAST;\n  wire S00_AXI_1_WREADY;\n  wire [63:0]S00_AXI_1_WSTRB;\n  wire S00_AXI_1_WVALID;\n  wire [63:0]S01_AXI_1_ARADDR;\n  wire [1:0]S01_AXI_1_ARBURST;\n  wire [3:0]S01_AXI_1_ARCACHE;\n  wire [5:0]S01_AXI_1_ARID;\n  wire [7:0]S01_AXI_1_ARLEN;\n  wire [0:0]S01_AXI_1_ARLOCK;\n  wire [2:0]S01_AXI_1_ARPROT;\n  wire [3:0]S01_AXI_1_ARQOS;\n  wire S01_AXI_1_ARREADY;\n  wire [3:0]S01_AXI_1_ARREGION;\n  wire [2:0]S01_AXI_1_ARSIZE;\n  wire S01_AXI_1_ARVALID;\n  wire [63:0]S01_AXI_1_AWADDR;\n  wire [1:0]S01_AXI_1_AWBURST;\n  wire [3:0]S01_AXI_1_AWCACHE;\n  wire [5:0]S01_AXI_1_AWID;\n  wire [7:0]S01_AXI_1_AWLEN;\n  wire [0:0]S01_AXI_1_AWLOCK;\n  wire [2:0]S01_AXI_1_AWPROT;\n  wire [3:0]S01_AXI_1_AWQOS;\n  wire S01_AXI_1_AWREADY;\n  wire [3:0]S01_AXI_1_AWREGION;\n  wire [2:0]S01_AXI_1_AWSIZE;\n  wire S01_AXI_1_AWVALID;\n  wire [5:0]S01_AXI_1_BID;\n  wire S01_AXI_1_BREADY;\n  wire [1:0]S01_AXI_1_BRESP;\n  wire S01_AXI_1_BVALID;\n  wire [511:0]S01_AXI_1_RDATA;\n  wire [5:0]S01_AXI_1_RID;\n  wire S01_AXI_1_RLAST;\n  wire S01_AXI_1_RREADY;\n  wire [1:0]S01_AXI_1_RRESP;\n  wire S01_AXI_1_RVALID;\n  wire [511:0]S01_AXI_1_WDATA;\n  wire S01_AXI_1_WLAST;\n  wire S01_AXI_1_WREADY;\n  wire [63:0]S01_AXI_1_WSTRB;\n  wire S01_AXI_1_WVALID;\n  wire [63:0]axi_interconnect_0_M00_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M00_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M00_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M00_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M00_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M00_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARQOS;\n  wire axi_interconnect_0_M00_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M00_AXI_ARSIZE;\n  wire axi_interconnect_0_M00_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M00_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M00_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M00_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M00_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M00_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M00_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWQOS;\n  wire axi_interconnect_0_M00_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M00_AXI_AWSIZE;\n  wire axi_interconnect_0_M00_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M00_AXI_BID;\n  wire axi_interconnect_0_M00_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M00_AXI_BRESP;\n  wire axi_interconnect_0_M00_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M00_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M00_AXI_RID;\n  wire axi_interconnect_0_M00_AXI_RLAST;\n  wire axi_interconnect_0_M00_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M00_AXI_RRESP;\n  wire axi_interconnect_0_M00_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M00_AXI_WDATA;\n  wire axi_interconnect_0_M00_AXI_WLAST;\n  wire axi_interconnect_0_M00_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M00_AXI_WSTRB;\n  wire axi_interconnect_0_M00_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M01_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M01_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M01_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M01_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M01_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M01_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARQOS;\n  wire axi_interconnect_0_M01_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M01_AXI_ARSIZE;\n  wire axi_interconnect_0_M01_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M01_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M01_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M01_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M01_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M01_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M01_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWQOS;\n  wire axi_interconnect_0_M01_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M01_AXI_AWSIZE;\n  wire axi_interconnect_0_M01_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M01_AXI_BID;\n  wire axi_interconnect_0_M01_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M01_AXI_BRESP;\n  wire axi_interconnect_0_M01_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M01_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M01_AXI_RID;\n  wire axi_interconnect_0_M01_AXI_RLAST;\n  wire axi_interconnect_0_M01_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M01_AXI_RRESP;\n  wire axi_interconnect_0_M01_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M01_AXI_WDATA;\n  wire axi_interconnect_0_M01_AXI_WLAST;\n  wire axi_interconnect_0_M01_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M01_AXI_WSTRB;\n  wire axi_interconnect_0_M01_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M02_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M02_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M02_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M02_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M02_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M02_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARQOS;\n  wire axi_interconnect_0_M02_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M02_AXI_ARSIZE;\n  wire axi_interconnect_0_M02_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M02_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M02_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M02_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M02_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M02_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M02_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWQOS;\n  wire axi_interconnect_0_M02_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M02_AXI_AWSIZE;\n  wire axi_interconnect_0_M02_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M02_AXI_BID;\n  wire axi_interconnect_0_M02_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M02_AXI_BRESP;\n  wire axi_interconnect_0_M02_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M02_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M02_AXI_RID;\n  wire axi_interconnect_0_M02_AXI_RLAST;\n  wire axi_interconnect_0_M02_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M02_AXI_RRESP;\n  wire axi_interconnect_0_M02_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M02_AXI_WDATA;\n  wire axi_interconnect_0_M02_AXI_WLAST;\n  wire axi_interconnect_0_M02_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M02_AXI_WSTRB;\n  wire axi_interconnect_0_M02_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M03_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M03_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M03_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M03_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M03_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M03_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARQOS;\n  wire axi_interconnect_0_M03_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M03_AXI_ARSIZE;\n  wire axi_interconnect_0_M03_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M03_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M03_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M03_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M03_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M03_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M03_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWQOS;\n  wire axi_interconnect_0_M03_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M03_AXI_AWSIZE;\n  wire axi_interconnect_0_M03_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M03_AXI_BID;\n  wire axi_interconnect_0_M03_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M03_AXI_BRESP;\n  wire axi_interconnect_0_M03_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M03_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M03_AXI_RID;\n  wire axi_interconnect_0_M03_AXI_RLAST;\n  wire axi_interconnect_0_M03_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M03_AXI_RRESP;\n  wire axi_interconnect_0_M03_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M03_AXI_WDATA;\n  wire axi_interconnect_0_M03_AXI_WLAST;\n  wire axi_interconnect_0_M03_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M03_AXI_WSTRB;\n  wire axi_interconnect_0_M03_AXI_WVALID;\n\n  assign ACLK_1 = ACLK;\n  assign ARESETN_1 = ARESETN;\n  assign M00_AXI_araddr[63:0] = axi_interconnect_0_M00_AXI_ARADDR;\n  assign M00_AXI_arburst[1:0] = axi_interconnect_0_M00_AXI_ARBURST;\n  assign M00_AXI_arcache[3:0] = axi_interconnect_0_M00_AXI_ARCACHE;\n  assign M00_AXI_arid[6:0] = axi_interconnect_0_M00_AXI_ARID;\n  assign M00_AXI_arlen[7:0] = axi_interconnect_0_M00_AXI_ARLEN;\n  assign M00_AXI_arlock[0] = axi_interconnect_0_M00_AXI_ARLOCK;\n  assign M00_AXI_arprot[2:0] = axi_interconnect_0_M00_AXI_ARPROT;\n  assign M00_AXI_arqos[3:0] = axi_interconnect_0_M00_AXI_ARQOS;\n  assign M00_AXI_arregion[3:0] = axi_interconnect_0_M00_AXI_ARREGION;\n  assign M00_AXI_arsize[2:0] = axi_interconnect_0_M00_AXI_ARSIZE;\n  assign M00_AXI_arvalid = axi_interconnect_0_M00_AXI_ARVALID;\n  assign M00_AXI_awaddr[63:0] = axi_interconnect_0_M00_AXI_AWADDR;\n  assign M00_AXI_awburst[1:0] = axi_interconnect_0_M00_AXI_AWBURST;\n  assign M00_AXI_awcache[3:0] = axi_interconnect_0_M00_AXI_AWCACHE;\n  assign M00_AXI_awid[6:0] = axi_interconnect_0_M00_AXI_AWID;\n  assign M00_AXI_awlen[7:0] = axi_interconnect_0_M00_AXI_AWLEN;\n  assign M00_AXI_awlock[0] = axi_interconnect_0_M00_AXI_AWLOCK;\n  assign M00_AXI_awprot[2:0] = axi_interconnect_0_M00_AXI_AWPROT;\n  assign M00_AXI_awqos[3:0] = axi_interconnect_0_M00_AXI_AWQOS;\n  assign M00_AXI_awregion[3:0] = axi_interconnect_0_M00_AXI_AWREGION;\n  assign M00_AXI_awsize[2:0] = axi_interconnect_0_M00_AXI_AWSIZE;\n  assign M00_AXI_awvalid = axi_interconnect_0_M00_AXI_AWVALID;\n  assign M00_AXI_bready = axi_interconnect_0_M00_AXI_BREADY;\n  assign M00_AXI_rready = axi_interconnect_0_M00_AXI_RREADY;\n  assign M00_AXI_wdata[511:0] = axi_interconnect_0_M00_AXI_WDATA;\n  assign M00_AXI_wlast = axi_interconnect_0_M00_AXI_WLAST;\n  assign M00_AXI_wstrb[63:0] = axi_interconnect_0_M00_AXI_WSTRB;\n  assign M00_AXI_wvalid = axi_interconnect_0_M00_AXI_WVALID;\n  assign M01_AXI_araddr[63:0] = axi_interconnect_0_M01_AXI_ARADDR;\n  assign M01_AXI_arburst[1:0] = axi_interconnect_0_M01_AXI_ARBURST;\n  assign M01_AXI_arcache[3:0] = axi_interconnect_0_M01_AXI_ARCACHE;\n  assign M01_AXI_arid[6:0] = axi_interconnect_0_M01_AXI_ARID;\n  assign M01_AXI_arlen[7:0] = axi_interconnect_0_M01_AXI_ARLEN;\n  assign M01_AXI_arlock[0] = axi_interconnect_0_M01_AXI_ARLOCK;\n  assign M01_AXI_arprot[2:0] = axi_interconnect_0_M01_AXI_ARPROT;\n  assign M01_AXI_arqos[3:0] = axi_interconnect_0_M01_AXI_ARQOS;\n  assign M01_AXI_arregion[3:0] = axi_interconnect_0_M01_AXI_ARREGION;\n  assign M01_AXI_arsize[2:0] = axi_interconnect_0_M01_AXI_ARSIZE;\n  assign M01_AXI_arvalid = axi_interconnect_0_M01_AXI_ARVALID;\n  assign M01_AXI_awaddr[63:0] = axi_interconnect_0_M01_AXI_AWADDR;\n  assign M01_AXI_awburst[1:0] = axi_interconnect_0_M01_AXI_AWBURST;\n  assign M01_AXI_awcache[3:0] = axi_interconnect_0_M01_AXI_AWCACHE;\n  assign M01_AXI_awid[6:0] = axi_interconnect_0_M01_AXI_AWID;\n  assign M01_AXI_awlen[7:0] = axi_interconnect_0_M01_AXI_AWLEN;\n  assign M01_AXI_awlock[0] = axi_interconnect_0_M01_AXI_AWLOCK;\n  assign M01_AXI_awprot[2:0] = axi_interconnect_0_M01_AXI_AWPROT;\n  assign M01_AXI_awqos[3:0] = axi_interconnect_0_M01_AXI_AWQOS;\n  assign M01_AXI_awregion[3:0] = axi_interconnect_0_M01_AXI_AWREGION;\n  assign M01_AXI_awsize[2:0] = axi_interconnect_0_M01_AXI_AWSIZE;\n  assign M01_AXI_awvalid = axi_interconnect_0_M01_AXI_AWVALID;\n  assign M01_AXI_bready = axi_interconnect_0_M01_AXI_BREADY;\n  assign M01_AXI_rready = axi_interconnect_0_M01_AXI_RREADY;\n  assign M01_AXI_wdata[511:0] = axi_interconnect_0_M01_AXI_WDATA;\n  assign M01_AXI_wlast = axi_interconnect_0_M01_AXI_WLAST;\n  assign M01_AXI_wstrb[63:0] = axi_interconnect_0_M01_AXI_WSTRB;\n  assign M01_AXI_wvalid = axi_interconnect_0_M01_AXI_WVALID;\n  assign M02_AXI_araddr[63:0] = axi_interconnect_0_M02_AXI_ARADDR;\n  assign M02_AXI_arburst[1:0] = axi_interconnect_0_M02_AXI_ARBURST;\n  assign M02_AXI_arcache[3:0] = axi_interconnect_0_M02_AXI_ARCACHE;\n  assign M02_AXI_arid[6:0] = axi_interconnect_0_M02_AXI_ARID;\n  assign M02_AXI_arlen[7:0] = axi_interconnect_0_M02_AXI_ARLEN;\n  assign M02_AXI_arlock[0] = axi_interconnect_0_M02_AXI_ARLOCK;\n  assign M02_AXI_arprot[2:0] = axi_interconnect_0_M02_AXI_ARPROT;\n  assign M02_AXI_arqos[3:0] = axi_interconnect_0_M02_AXI_ARQOS;\n  assign M02_AXI_arregion[3:0] = axi_interconnect_0_M02_AXI_ARREGION;\n  assign M02_AXI_arsize[2:0] = axi_interconnect_0_M02_AXI_ARSIZE;\n  assign M02_AXI_arvalid = axi_interconnect_0_M02_AXI_ARVALID;\n  assign M02_AXI_awaddr[63:0] = axi_interconnect_0_M02_AXI_AWADDR;\n  assign M02_AXI_awburst[1:0] = axi_interconnect_0_M02_AXI_AWBURST;\n  assign M02_AXI_awcache[3:0] = axi_interconnect_0_M02_AXI_AWCACHE;\n  assign M02_AXI_awid[6:0] = axi_interconnect_0_M02_AXI_AWID;\n  assign M02_AXI_awlen[7:0] = axi_interconnect_0_M02_AXI_AWLEN;\n  assign M02_AXI_awlock[0] = axi_interconnect_0_M02_AXI_AWLOCK;\n  assign M02_AXI_awprot[2:0] = axi_interconnect_0_M02_AXI_AWPROT;\n  assign M02_AXI_awqos[3:0] = axi_interconnect_0_M02_AXI_AWQOS;\n  assign M02_AXI_awregion[3:0] = axi_interconnect_0_M02_AXI_AWREGION;\n  assign M02_AXI_awsize[2:0] = axi_interconnect_0_M02_AXI_AWSIZE;\n  assign M02_AXI_awvalid = axi_interconnect_0_M02_AXI_AWVALID;\n  assign M02_AXI_bready = axi_interconnect_0_M02_AXI_BREADY;\n  assign M02_AXI_rready = axi_interconnect_0_M02_AXI_RREADY;\n  assign M02_AXI_wdata[511:0] = axi_interconnect_0_M02_AXI_WDATA;\n  assign M02_AXI_wlast = axi_interconnect_0_M02_AXI_WLAST;\n  assign M02_AXI_wstrb[63:0] = axi_interconnect_0_M02_AXI_WSTRB;\n  assign M02_AXI_wvalid = axi_interconnect_0_M02_AXI_WVALID;\n  assign M03_AXI_araddr[63:0] = axi_interconnect_0_M03_AXI_ARADDR;\n  assign M03_AXI_arburst[1:0] = axi_interconnect_0_M03_AXI_ARBURST;\n  assign M03_AXI_arcache[3:0] = axi_interconnect_0_M03_AXI_ARCACHE;\n  assign M03_AXI_arid[6:0] = axi_interconnect_0_M03_AXI_ARID;\n  assign M03_AXI_arlen[7:0] = axi_interconnect_0_M03_AXI_ARLEN;\n  assign M03_AXI_arlock[0] = axi_interconnect_0_M03_AXI_ARLOCK;\n  assign M03_AXI_arprot[2:0] = axi_interconnect_0_M03_AXI_ARPROT;\n  assign M03_AXI_arqos[3:0] = axi_interconnect_0_M03_AXI_ARQOS;\n  assign M03_AXI_arregion[3:0] = axi_interconnect_0_M03_AXI_ARREGION;\n  assign M03_AXI_arsize[2:0] = axi_interconnect_0_M03_AXI_ARSIZE;\n  assign M03_AXI_arvalid = axi_interconnect_0_M03_AXI_ARVALID;\n  assign M03_AXI_awaddr[63:0] = axi_interconnect_0_M03_AXI_AWADDR;\n  assign M03_AXI_awburst[1:0] = axi_interconnect_0_M03_AXI_AWBURST;\n  assign M03_AXI_awcache[3:0] = axi_interconnect_0_M03_AXI_AWCACHE;\n  assign M03_AXI_awid[6:0] = axi_interconnect_0_M03_AXI_AWID;\n  assign M03_AXI_awlen[7:0] = axi_interconnect_0_M03_AXI_AWLEN;\n  assign M03_AXI_awlock[0] = axi_interconnect_0_M03_AXI_AWLOCK;\n  assign M03_AXI_awprot[2:0] = axi_interconnect_0_M03_AXI_AWPROT;\n  assign M03_AXI_awqos[3:0] = axi_interconnect_0_M03_AXI_AWQOS;\n  assign M03_AXI_awregion[3:0] = axi_interconnect_0_M03_AXI_AWREGION;\n  assign M03_AXI_awsize[2:0] = axi_interconnect_0_M03_AXI_AWSIZE;\n  assign M03_AXI_awvalid = axi_interconnect_0_M03_AXI_AWVALID;\n  assign M03_AXI_bready = axi_interconnect_0_M03_AXI_BREADY;\n  assign M03_AXI_rready = axi_interconnect_0_M03_AXI_RREADY;\n  assign M03_AXI_wdata[511:0] = axi_interconnect_0_M03_AXI_WDATA;\n  assign M03_AXI_wlast = axi_interconnect_0_M03_AXI_WLAST;\n  assign M03_AXI_wstrb[63:0] = axi_interconnect_0_M03_AXI_WSTRB;\n  assign M03_AXI_wvalid = axi_interconnect_0_M03_AXI_WVALID;\n  assign S00_AXI_1_ARADDR = S00_AXI_araddr[63:0];\n  assign S00_AXI_1_ARBURST = S00_AXI_arburst[1:0];\n  assign S00_AXI_1_ARCACHE = S00_AXI_arcache[3:0];\n  assign S00_AXI_1_ARID = S00_AXI_arid[5:0];\n  assign S00_AXI_1_ARLEN = S00_AXI_arlen[7:0];\n  assign S00_AXI_1_ARLOCK = S00_AXI_arlock[0];\n  assign S00_AXI_1_ARPROT = S00_AXI_arprot[2:0];\n  assign S00_AXI_1_ARQOS = S00_AXI_arqos[3:0];\n  assign S00_AXI_1_ARREGION = S00_AXI_arregion[3:0];\n  assign S00_AXI_1_ARSIZE = S00_AXI_arsize[2:0];\n  assign S00_AXI_1_ARVALID = S00_AXI_arvalid;\n  assign S00_AXI_1_AWADDR = S00_AXI_awaddr[63:0];\n  assign S00_AXI_1_AWBURST = S00_AXI_awburst[1:0];\n  assign S00_AXI_1_AWCACHE = S00_AXI_awcache[3:0];\n  assign S00_AXI_1_AWID = S00_AXI_awid[5:0];\n  assign S00_AXI_1_AWLEN = S00_AXI_awlen[7:0];\n  assign S00_AXI_1_AWLOCK = S00_AXI_awlock[0];\n  assign S00_AXI_1_AWPROT = S00_AXI_awprot[2:0];\n  assign S00_AXI_1_AWQOS = S00_AXI_awqos[3:0];\n  assign S00_AXI_1_AWREGION = S00_AXI_awregion[3:0];\n  assign S00_AXI_1_AWSIZE = S00_AXI_awsize[2:0];\n  assign S00_AXI_1_AWVALID = S00_AXI_awvalid;\n  assign S00_AXI_1_BREADY = S00_AXI_bready;\n  assign S00_AXI_1_RREADY = S00_AXI_rready;\n  assign S00_AXI_1_WDATA = S00_AXI_wdata[511:0];\n  assign S00_AXI_1_WLAST = S00_AXI_wlast;\n  assign S00_AXI_1_WSTRB = S00_AXI_wstrb[63:0];\n  assign S00_AXI_1_WVALID = S00_AXI_wvalid;\n  assign S00_AXI_arready = S00_AXI_1_ARREADY;\n  assign S00_AXI_awready = S00_AXI_1_AWREADY;\n  assign S00_AXI_bid[5:0] = S00_AXI_1_BID;\n  assign S00_AXI_bresp[1:0] = S00_AXI_1_BRESP;\n  assign S00_AXI_bvalid = S00_AXI_1_BVALID;\n  assign S00_AXI_rdata[511:0] = S00_AXI_1_RDATA;\n  assign S00_AXI_rid[5:0] = S00_AXI_1_RID;\n  assign S00_AXI_rlast = S00_AXI_1_RLAST;\n  assign S00_AXI_rresp[1:0] = S00_AXI_1_RRESP;\n  assign S00_AXI_rvalid = S00_AXI_1_RVALID;\n  assign S00_AXI_wready = S00_AXI_1_WREADY;\n  assign S01_AXI_1_ARADDR = S01_AXI_araddr[63:0];\n  assign S01_AXI_1_ARBURST = S01_AXI_arburst[1:0];\n  assign S01_AXI_1_ARCACHE = S01_AXI_arcache[3:0];\n  assign S01_AXI_1_ARID = S01_AXI_arid[5:0];\n  assign S01_AXI_1_ARLEN = S01_AXI_arlen[7:0];\n  assign S01_AXI_1_ARLOCK = S01_AXI_arlock[0];\n  assign S01_AXI_1_ARPROT = S01_AXI_arprot[2:0];\n  assign S01_AXI_1_ARQOS = S01_AXI_arqos[3:0];\n  assign S01_AXI_1_ARREGION = S01_AXI_arregion[3:0];\n  assign S01_AXI_1_ARSIZE = S01_AXI_arsize[2:0];\n  assign S01_AXI_1_ARVALID = S01_AXI_arvalid;\n  assign S01_AXI_1_AWADDR = S01_AXI_awaddr[63:0];\n  assign S01_AXI_1_AWBURST = S01_AXI_awburst[1:0];\n  assign S01_AXI_1_AWCACHE = S01_AXI_awcache[3:0];\n  assign S01_AXI_1_AWID = S01_AXI_awid[5:0];\n  assign S01_AXI_1_AWLEN = S01_AXI_awlen[7:0];\n  assign S01_AXI_1_AWLOCK = S01_AXI_awlock[0];\n  assign S01_AXI_1_AWPROT = S01_AXI_awprot[2:0];\n  assign S01_AXI_1_AWQOS = S01_AXI_awqos[3:0];\n  assign S01_AXI_1_AWREGION = S01_AXI_awregion[3:0];\n  assign S01_AXI_1_AWSIZE = S01_AXI_awsize[2:0];\n  assign S01_AXI_1_AWVALID = S01_AXI_awvalid;\n  assign S01_AXI_1_BREADY = S01_AXI_bready;\n  assign S01_AXI_1_RREADY = S01_AXI_rready;\n  assign S01_AXI_1_WDATA = S01_AXI_wdata[511:0];\n  assign S01_AXI_1_WLAST = S01_AXI_wlast;\n  assign S01_AXI_1_WSTRB = S01_AXI_wstrb[63:0];\n  assign S01_AXI_1_WVALID = S01_AXI_wvalid;\n  assign S01_AXI_arready = S01_AXI_1_ARREADY;\n  assign S01_AXI_awready = S01_AXI_1_AWREADY;\n  assign S01_AXI_bid[5:0] = S01_AXI_1_BID;\n  assign S01_AXI_bresp[1:0] = S01_AXI_1_BRESP;\n  assign S01_AXI_bvalid = S01_AXI_1_BVALID;\n  assign S01_AXI_rdata[511:0] = S01_AXI_1_RDATA;\n  assign S01_AXI_rid[5:0] = S01_AXI_1_RID;\n  assign S01_AXI_rlast = S01_AXI_1_RLAST;\n  assign S01_AXI_rresp[1:0] = S01_AXI_1_RRESP;\n  assign S01_AXI_rvalid = S01_AXI_1_RVALID;\n  assign S01_AXI_wready = S01_AXI_1_WREADY;\n  assign axi_interconnect_0_M00_AXI_ARREADY = M00_AXI_arready;\n  assign axi_interconnect_0_M00_AXI_AWREADY = M00_AXI_awready;\n  assign axi_interconnect_0_M00_AXI_BID = M00_AXI_bid[6:0];\n  assign axi_interconnect_0_M00_AXI_BRESP = M00_AXI_bresp[1:0];\n  assign axi_interconnect_0_M00_AXI_BVALID = M00_AXI_bvalid;\n  assign axi_interconnect_0_M00_AXI_RDATA = M00_AXI_rdata[511:0];\n  assign axi_interconnect_0_M00_AXI_RID = M00_AXI_rid[6:0];\n  assign axi_interconnect_0_M00_AXI_RLAST = M00_AXI_rlast;\n  assign axi_interconnect_0_M00_AXI_RRESP = M00_AXI_rresp[1:0];\n  assign axi_interconnect_0_M00_AXI_RVALID = M00_AXI_rvalid;\n  assign axi_interconnect_0_M00_AXI_WREADY = M00_AXI_wready;\n  assign axi_interconnect_0_M01_AXI_ARREADY = M01_AXI_arready;\n  assign axi_interconnect_0_M01_AXI_AWREADY = M01_AXI_awready;\n  assign axi_interconnect_0_M01_AXI_BID = M01_AXI_bid[6:0];\n  assign axi_interconnect_0_M01_AXI_BRESP = M01_AXI_bresp[1:0];\n  assign axi_interconnect_0_M01_AXI_BVALID = M01_AXI_bvalid;\n  assign axi_interconnect_0_M01_AXI_RDATA = M01_AXI_rdata[511:0];\n  assign axi_interconnect_0_M01_AXI_RID = M01_AXI_rid[6:0];\n  assign axi_interconnect_0_M01_AXI_RLAST = M01_AXI_rlast;\n  assign axi_interconnect_0_M01_AXI_RRESP = M01_AXI_rresp[1:0];\n  assign axi_interconnect_0_M01_AXI_RVALID = M01_AXI_rvalid;\n  assign axi_interconnect_0_M01_AXI_WREADY = M01_AXI_wready;\n  assign axi_interconnect_0_M02_AXI_ARREADY = M02_AXI_arready;\n  assign axi_interconnect_0_M02_AXI_AWREADY = M02_AXI_awready;\n  assign axi_interconnect_0_M02_AXI_BID = M02_AXI_bid[6:0];\n  assign axi_interconnect_0_M02_AXI_BRESP = M02_AXI_bresp[1:0];\n  assign axi_interconnect_0_M02_AXI_BVALID = M02_AXI_bvalid;\n  assign axi_interconnect_0_M02_AXI_RDATA = M02_AXI_rdata[511:0];\n  assign axi_interconnect_0_M02_AXI_RID = M02_AXI_rid[6:0];\n  assign axi_interconnect_0_M02_AXI_RLAST = M02_AXI_rlast;\n  assign axi_interconnect_0_M02_AXI_RRESP = M02_AXI_rresp[1:0];\n  assign axi_interconnect_0_M02_AXI_RVALID = M02_AXI_rvalid;\n  assign axi_interconnect_0_M02_AXI_WREADY = M02_AXI_wready;\n  assign axi_interconnect_0_M03_AXI_ARREADY = M03_AXI_arready;\n  assign axi_interconnect_0_M03_AXI_AWREADY = M03_AXI_awready;\n  assign axi_interconnect_0_M03_AXI_BID = M03_AXI_bid[6:0];\n  assign axi_interconnect_0_M03_AXI_BRESP = M03_AXI_bresp[1:0];\n  assign axi_interconnect_0_M03_AXI_BVALID = M03_AXI_bvalid;\n  assign axi_interconnect_0_M03_AXI_RDATA = M03_AXI_rdata[511:0];\n  assign axi_interconnect_0_M03_AXI_RID = M03_AXI_rid[6:0];\n  assign axi_interconnect_0_M03_AXI_RLAST = M03_AXI_rlast;\n  assign axi_interconnect_0_M03_AXI_RRESP = M03_AXI_rresp[1:0];\n  assign axi_interconnect_0_M03_AXI_RVALID = M03_AXI_rvalid;\n  assign axi_interconnect_0_M03_AXI_WREADY = M03_AXI_wready;\n  cl_axi_interconnect_axi_interconnect_0_0 axi_interconnect_0\n       (.ACLK(ACLK_1),\n        .ARESETN(ARESETN_1),\n        .M00_ACLK(ACLK_1),\n        .M00_ARESETN(ARESETN_1),\n        .M00_AXI_araddr(axi_interconnect_0_M00_AXI_ARADDR),\n        .M00_AXI_arburst(axi_interconnect_0_M00_AXI_ARBURST),\n        .M00_AXI_arcache(axi_interconnect_0_M00_AXI_ARCACHE),\n        .M00_AXI_arid(axi_interconnect_0_M00_AXI_ARID),\n        .M00_AXI_arlen(axi_interconnect_0_M00_AXI_ARLEN),\n        .M00_AXI_arlock(axi_interconnect_0_M00_AXI_ARLOCK),\n        .M00_AXI_arprot(axi_interconnect_0_M00_AXI_ARPROT),\n        .M00_AXI_arqos(axi_interconnect_0_M00_AXI_ARQOS),\n        .M00_AXI_arready(axi_interconnect_0_M00_AXI_ARREADY),\n        .M00_AXI_arregion(axi_interconnect_0_M00_AXI_ARREGION),\n        .M00_AXI_arsize(axi_interconnect_0_M00_AXI_ARSIZE),\n        .M00_AXI_arvalid(axi_interconnect_0_M00_AXI_ARVALID),\n        .M00_AXI_awaddr(axi_interconnect_0_M00_AXI_AWADDR),\n        .M00_AXI_awburst(axi_interconnect_0_M00_AXI_AWBURST),\n        .M00_AXI_awcache(axi_interconnect_0_M00_AXI_AWCACHE),\n        .M00_AXI_awid(axi_interconnect_0_M00_AXI_AWID),\n        .M00_AXI_awlen(axi_interconnect_0_M00_AXI_AWLEN),\n        .M00_AXI_awlock(axi_interconnect_0_M00_AXI_AWLOCK),\n        .M00_AXI_awprot(axi_interconnect_0_M00_AXI_AWPROT),\n        .M00_AXI_awqos(axi_interconnect_0_M00_AXI_AWQOS),\n        .M00_AXI_awready(axi_interconnect_0_M00_AXI_AWREADY),\n        .M00_AXI_awregion(axi_interconnect_0_M00_AXI_AWREGION),\n        .M00_AXI_awsize(axi_interconnect_0_M00_AXI_AWSIZE),\n        .M00_AXI_awvalid(axi_interconnect_0_M00_AXI_AWVALID),\n        .M00_AXI_bid(axi_interconnect_0_M00_AXI_BID),\n        .M00_AXI_bready(axi_interconnect_0_M00_AXI_BREADY),\n        .M00_AXI_bresp(axi_interconnect_0_M00_AXI_BRESP),\n        .M00_AXI_bvalid(axi_interconnect_0_M00_AXI_BVALID),\n        .M00_AXI_rdata(axi_interconnect_0_M00_AXI_RDATA),\n        .M00_AXI_rid(axi_interconnect_0_M00_AXI_RID),\n        .M00_AXI_rlast(axi_interconnect_0_M00_AXI_RLAST),\n        .M00_AXI_rready(axi_interconnect_0_M00_AXI_RREADY),\n        .M00_AXI_rresp(axi_interconnect_0_M00_AXI_RRESP),\n        .M00_AXI_rvalid(axi_interconnect_0_M00_AXI_RVALID),\n        .M00_AXI_wdata(axi_interconnect_0_M00_AXI_WDATA),\n        .M00_AXI_wlast(axi_interconnect_0_M00_AXI_WLAST),\n        .M00_AXI_wready(axi_interconnect_0_M00_AXI_WREADY),\n        .M00_AXI_wstrb(axi_interconnect_0_M00_AXI_WSTRB),\n        .M00_AXI_wvalid(axi_interconnect_0_M00_AXI_WVALID),\n        .M01_ACLK(ACLK_1),\n        .M01_ARESETN(ARESETN_1),\n        .M01_AXI_araddr(axi_interconnect_0_M01_AXI_ARADDR),\n        .M01_AXI_arburst(axi_interconnect_0_M01_AXI_ARBURST),\n        .M01_AXI_arcache(axi_interconnect_0_M01_AXI_ARCACHE),\n        .M01_AXI_arid(axi_interconnect_0_M01_AXI_ARID),\n        .M01_AXI_arlen(axi_interconnect_0_M01_AXI_ARLEN),\n        .M01_AXI_arlock(axi_interconnect_0_M01_AXI_ARLOCK),\n        .M01_AXI_arprot(axi_interconnect_0_M01_AXI_ARPROT),\n        .M01_AXI_arqos(axi_interconnect_0_M01_AXI_ARQOS),\n        .M01_AXI_arready(axi_interconnect_0_M01_AXI_ARREADY),\n        .M01_AXI_arregion(axi_interconnect_0_M01_AXI_ARREGION),\n        .M01_AXI_arsize(axi_interconnect_0_M01_AXI_ARSIZE),\n        .M01_AXI_arvalid(axi_interconnect_0_M01_AXI_ARVALID),\n        .M01_AXI_awaddr(axi_interconnect_0_M01_AXI_AWADDR),\n        .M01_AXI_awburst(axi_interconnect_0_M01_AXI_AWBURST),\n        .M01_AXI_awcache(axi_interconnect_0_M01_AXI_AWCACHE),\n        .M01_AXI_awid(axi_interconnect_0_M01_AXI_AWID),\n        .M01_AXI_awlen(axi_interconnect_0_M01_AXI_AWLEN),\n        .M01_AXI_awlock(axi_interconnect_0_M01_AXI_AWLOCK),\n        .M01_AXI_awprot(axi_interconnect_0_M01_AXI_AWPROT),\n        .M01_AXI_awqos(axi_interconnect_0_M01_AXI_AWQOS),\n        .M01_AXI_awready(axi_interconnect_0_M01_AXI_AWREADY),\n        .M01_AXI_awregion(axi_interconnect_0_M01_AXI_AWREGION),\n        .M01_AXI_awsize(axi_interconnect_0_M01_AXI_AWSIZE),\n        .M01_AXI_awvalid(axi_interconnect_0_M01_AXI_AWVALID),\n        .M01_AXI_bid(axi_interconnect_0_M01_AXI_BID),\n        .M01_AXI_bready(axi_interconnect_0_M01_AXI_BREADY),\n        .M01_AXI_bresp(axi_interconnect_0_M01_AXI_BRESP),\n        .M01_AXI_bvalid(axi_interconnect_0_M01_AXI_BVALID),\n        .M01_AXI_rdata(axi_interconnect_0_M01_AXI_RDATA),\n        .M01_AXI_rid(axi_interconnect_0_M01_AXI_RID),\n        .M01_AXI_rlast(axi_interconnect_0_M01_AXI_RLAST),\n        .M01_AXI_rready(axi_interconnect_0_M01_AXI_RREADY),\n        .M01_AXI_rresp(axi_interconnect_0_M01_AXI_RRESP),\n        .M01_AXI_rvalid(axi_interconnect_0_M01_AXI_RVALID),\n        .M01_AXI_wdata(axi_interconnect_0_M01_AXI_WDATA),\n        .M01_AXI_wlast(axi_interconnect_0_M01_AXI_WLAST),\n        .M01_AXI_wready(axi_interconnect_0_M01_AXI_WREADY),\n        .M01_AXI_wstrb(axi_interconnect_0_M01_AXI_WSTRB),\n        .M01_AXI_wvalid(axi_interconnect_0_M01_AXI_WVALID),\n        .M02_ACLK(ACLK_1),\n        .M02_ARESETN(ARESETN_1),\n        .M02_AXI_araddr(axi_interconnect_0_M02_AXI_ARADDR),\n        .M02_AXI_arburst(axi_interconnect_0_M02_AXI_ARBURST),\n        .M02_AXI_arcache(axi_interconnect_0_M02_AXI_ARCACHE),\n        .M02_AXI_arid(axi_interconnect_0_M02_AXI_ARID),\n        .M02_AXI_arlen(axi_interconnect_0_M02_AXI_ARLEN),\n        .M02_AXI_arlock(axi_interconnect_0_M02_AXI_ARLOCK),\n        .M02_AXI_arprot(axi_interconnect_0_M02_AXI_ARPROT),\n        .M02_AXI_arqos(axi_interconnect_0_M02_AXI_ARQOS),\n        .M02_AXI_arready(axi_interconnect_0_M02_AXI_ARREADY),\n        .M02_AXI_arregion(axi_interconnect_0_M02_AXI_ARREGION),\n        .M02_AXI_arsize(axi_interconnect_0_M02_AXI_ARSIZE),\n        .M02_AXI_arvalid(axi_interconnect_0_M02_AXI_ARVALID),\n        .M02_AXI_awaddr(axi_interconnect_0_M02_AXI_AWADDR),\n        .M02_AXI_awburst(axi_interconnect_0_M02_AXI_AWBURST),\n        .M02_AXI_awcache(axi_interconnect_0_M02_AXI_AWCACHE),\n        .M02_AXI_awid(axi_interconnect_0_M02_AXI_AWID),\n        .M02_AXI_awlen(axi_interconnect_0_M02_AXI_AWLEN),\n        .M02_AXI_awlock(axi_interconnect_0_M02_AXI_AWLOCK),\n        .M02_AXI_awprot(axi_interconnect_0_M02_AXI_AWPROT),\n        .M02_AXI_awqos(axi_interconnect_0_M02_AXI_AWQOS),\n        .M02_AXI_awready(axi_interconnect_0_M02_AXI_AWREADY),\n        .M02_AXI_awregion(axi_interconnect_0_M02_AXI_AWREGION),\n        .M02_AXI_awsize(axi_interconnect_0_M02_AXI_AWSIZE),\n        .M02_AXI_awvalid(axi_interconnect_0_M02_AXI_AWVALID),\n        .M02_AXI_bid(axi_interconnect_0_M02_AXI_BID),\n        .M02_AXI_bready(axi_interconnect_0_M02_AXI_BREADY),\n        .M02_AXI_bresp(axi_interconnect_0_M02_AXI_BRESP),\n        .M02_AXI_bvalid(axi_interconnect_0_M02_AXI_BVALID),\n        .M02_AXI_rdata(axi_interconnect_0_M02_AXI_RDATA),\n        .M02_AXI_rid(axi_interconnect_0_M02_AXI_RID),\n        .M02_AXI_rlast(axi_interconnect_0_M02_AXI_RLAST),\n        .M02_AXI_rready(axi_interconnect_0_M02_AXI_RREADY),\n        .M02_AXI_rresp(axi_interconnect_0_M02_AXI_RRESP),\n        .M02_AXI_rvalid(axi_interconnect_0_M02_AXI_RVALID),\n        .M02_AXI_wdata(axi_interconnect_0_M02_AXI_WDATA),\n        .M02_AXI_wlast(axi_interconnect_0_M02_AXI_WLAST),\n        .M02_AXI_wready(axi_interconnect_0_M02_AXI_WREADY),\n        .M02_AXI_wstrb(axi_interconnect_0_M02_AXI_WSTRB),\n        .M02_AXI_wvalid(axi_interconnect_0_M02_AXI_WVALID),\n        .M03_ACLK(ACLK_1),\n        .M03_ARESETN(ARESETN_1),\n        .M03_AXI_araddr(axi_interconnect_0_M03_AXI_ARADDR),\n        .M03_AXI_arburst(axi_interconnect_0_M03_AXI_ARBURST),\n        .M03_AXI_arcache(axi_interconnect_0_M03_AXI_ARCACHE),\n        .M03_AXI_arid(axi_interconnect_0_M03_AXI_ARID),\n        .M03_AXI_arlen(axi_interconnect_0_M03_AXI_ARLEN),\n        .M03_AXI_arlock(axi_interconnect_0_M03_AXI_ARLOCK),\n        .M03_AXI_arprot(axi_interconnect_0_M03_AXI_ARPROT),\n        .M03_AXI_arqos(axi_interconnect_0_M03_AXI_ARQOS),\n        .M03_AXI_arready(axi_interconnect_0_M03_AXI_ARREADY),\n        .M03_AXI_arregion(axi_interconnect_0_M03_AXI_ARREGION),\n        .M03_AXI_arsize(axi_interconnect_0_M03_AXI_ARSIZE),\n        .M03_AXI_arvalid(axi_interconnect_0_M03_AXI_ARVALID),\n        .M03_AXI_awaddr(axi_interconnect_0_M03_AXI_AWADDR),\n        .M03_AXI_awburst(axi_interconnect_0_M03_AXI_AWBURST),\n        .M03_AXI_awcache(axi_interconnect_0_M03_AXI_AWCACHE),\n        .M03_AXI_awid(axi_interconnect_0_M03_AXI_AWID),\n        .M03_AXI_awlen(axi_interconnect_0_M03_AXI_AWLEN),\n        .M03_AXI_awlock(axi_interconnect_0_M03_AXI_AWLOCK),\n        .M03_AXI_awprot(axi_interconnect_0_M03_AXI_AWPROT),\n        .M03_AXI_awqos(axi_interconnect_0_M03_AXI_AWQOS),\n        .M03_AXI_awready(axi_interconnect_0_M03_AXI_AWREADY),\n        .M03_AXI_awregion(axi_interconnect_0_M03_AXI_AWREGION),\n        .M03_AXI_awsize(axi_interconnect_0_M03_AXI_AWSIZE),\n        .M03_AXI_awvalid(axi_interconnect_0_M03_AXI_AWVALID),\n        .M03_AXI_bid(axi_interconnect_0_M03_AXI_BID),\n        .M03_AXI_bready(axi_interconnect_0_M03_AXI_BREADY),\n        .M03_AXI_bresp(axi_interconnect_0_M03_AXI_BRESP),\n        .M03_AXI_bvalid(axi_interconnect_0_M03_AXI_BVALID),\n        .M03_AXI_rdata(axi_interconnect_0_M03_AXI_RDATA),\n        .M03_AXI_rid(axi_interconnect_0_M03_AXI_RID),\n        .M03_AXI_rlast(axi_interconnect_0_M03_AXI_RLAST),\n        .M03_AXI_rready(axi_interconnect_0_M03_AXI_RREADY),\n        .M03_AXI_rresp(axi_interconnect_0_M03_AXI_RRESP),\n        .M03_AXI_rvalid(axi_interconnect_0_M03_AXI_RVALID),\n        .M03_AXI_wdata(axi_interconnect_0_M03_AXI_WDATA),\n        .M03_AXI_wlast(axi_interconnect_0_M03_AXI_WLAST),\n        .M03_AXI_wready(axi_interconnect_0_M03_AXI_WREADY),\n        .M03_AXI_wstrb(axi_interconnect_0_M03_AXI_WSTRB),\n        .M03_AXI_wvalid(axi_interconnect_0_M03_AXI_WVALID),\n        .S00_ACLK(ACLK_1),\n        .S00_ARESETN(ARESETN_1),\n        .S00_AXI_araddr(S00_AXI_1_ARADDR),\n        .S00_AXI_arburst(S00_AXI_1_ARBURST),\n        .S00_AXI_arcache(S00_AXI_1_ARCACHE),\n        .S00_AXI_arid(S00_AXI_1_ARID),\n        .S00_AXI_arlen(S00_AXI_1_ARLEN),\n        .S00_AXI_arlock(S00_AXI_1_ARLOCK),\n        .S00_AXI_arprot(S00_AXI_1_ARPROT),\n        .S00_AXI_arqos(S00_AXI_1_ARQOS),\n        .S00_AXI_arready(S00_AXI_1_ARREADY),\n        .S00_AXI_arregion(S00_AXI_1_ARREGION),\n        .S00_AXI_arsize(S00_AXI_1_ARSIZE),\n        .S00_AXI_arvalid(S00_AXI_1_ARVALID),\n        .S00_AXI_awaddr(S00_AXI_1_AWADDR),\n        .S00_AXI_awburst(S00_AXI_1_AWBURST),\n        .S00_AXI_awcache(S00_AXI_1_AWCACHE),\n        .S00_AXI_awid(S00_AXI_1_AWID),\n        .S00_AXI_awlen(S00_AXI_1_AWLEN),\n        .S00_AXI_awlock(S00_AXI_1_AWLOCK),\n        .S00_AXI_awprot(S00_AXI_1_AWPROT),\n        .S00_AXI_awqos(S00_AXI_1_AWQOS),\n        .S00_AXI_awready(S00_AXI_1_AWREADY),\n        .S00_AXI_awregion(S00_AXI_1_AWREGION),\n        .S00_AXI_awsize(S00_AXI_1_AWSIZE),\n        .S00_AXI_awvalid(S00_AXI_1_AWVALID),\n        .S00_AXI_bid(S00_AXI_1_BID),\n        .S00_AXI_bready(S00_AXI_1_BREADY),\n        .S00_AXI_bresp(S00_AXI_1_BRESP),\n        .S00_AXI_bvalid(S00_AXI_1_BVALID),\n        .S00_AXI_rdata(S00_AXI_1_RDATA),\n        .S00_AXI_rid(S00_AXI_1_RID),\n        .S00_AXI_rlast(S00_AXI_1_RLAST),\n        .S00_AXI_rready(S00_AXI_1_RREADY),\n        .S00_AXI_rresp(S00_AXI_1_RRESP),\n        .S00_AXI_rvalid(S00_AXI_1_RVALID),\n        .S00_AXI_wdata(S00_AXI_1_WDATA),\n        .S00_AXI_wlast(S00_AXI_1_WLAST),\n        .S00_AXI_wready(S00_AXI_1_WREADY),\n        .S00_AXI_wstrb(S00_AXI_1_WSTRB),\n        .S00_AXI_wvalid(S00_AXI_1_WVALID),\n        .S01_ACLK(ACLK_1),\n        .S01_ARESETN(ARESETN_1),\n        .S01_AXI_araddr(S01_AXI_1_ARADDR),\n        .S01_AXI_arburst(S01_AXI_1_ARBURST),\n        .S01_AXI_arcache(S01_AXI_1_ARCACHE),\n        .S01_AXI_arid(S01_AXI_1_ARID),\n        .S01_AXI_arlen(S01_AXI_1_ARLEN),\n        .S01_AXI_arlock(S01_AXI_1_ARLOCK),\n        .S01_AXI_arprot(S01_AXI_1_ARPROT),\n        .S01_AXI_arqos(S01_AXI_1_ARQOS),\n        .S01_AXI_arready(S01_AXI_1_ARREADY),\n        .S01_AXI_arregion(S01_AXI_1_ARREGION),\n        .S01_AXI_arsize(S01_AXI_1_ARSIZE),\n        .S01_AXI_arvalid(S01_AXI_1_ARVALID),\n        .S01_AXI_awaddr(S01_AXI_1_AWADDR),\n        .S01_AXI_awburst(S01_AXI_1_AWBURST),\n        .S01_AXI_awcache(S01_AXI_1_AWCACHE),\n        .S01_AXI_awid(S01_AXI_1_AWID),\n        .S01_AXI_awlen(S01_AXI_1_AWLEN),\n        .S01_AXI_awlock(S01_AXI_1_AWLOCK),\n        .S01_AXI_awprot(S01_AXI_1_AWPROT),\n        .S01_AXI_awqos(S01_AXI_1_AWQOS),\n        .S01_AXI_awready(S01_AXI_1_AWREADY),\n        .S01_AXI_awregion(S01_AXI_1_AWREGION),\n        .S01_AXI_awsize(S01_AXI_1_AWSIZE),\n        .S01_AXI_awvalid(S01_AXI_1_AWVALID),\n        .S01_AXI_bid(S01_AXI_1_BID),\n        .S01_AXI_bready(S01_AXI_1_BREADY),\n        .S01_AXI_bresp(S01_AXI_1_BRESP),\n        .S01_AXI_bvalid(S01_AXI_1_BVALID),\n        .S01_AXI_rdata(S01_AXI_1_RDATA),\n        .S01_AXI_rid(S01_AXI_1_RID),\n        .S01_AXI_rlast(S01_AXI_1_RLAST),\n        .S01_AXI_rready(S01_AXI_1_RREADY),\n        .S01_AXI_rresp(S01_AXI_1_RRESP),\n        .S01_AXI_rvalid(S01_AXI_1_RVALID),\n        .S01_AXI_wdata(S01_AXI_1_WDATA),\n        .S01_AXI_wlast(S01_AXI_1_WLAST),\n        .S01_AXI_wready(S01_AXI_1_WREADY),\n        .S01_AXI_wstrb(S01_AXI_1_WSTRB),\n        .S01_AXI_wvalid(S01_AXI_1_WVALID));\nendmodule\n\nmodule cl_axi_interconnect_axi_interconnect_0_0\n   (ACLK,\n    ARESETN,\n    M00_ACLK,\n    M00_ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_ACLK,\n    M01_ARESETN,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_ACLK,\n    M02_ARESETN,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_ACLK,\n    M03_ARESETN,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_ACLK,\n    S00_ARESETN,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_ACLK,\n    S01_ARESETN,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  input ACLK;\n  input ARESETN;\n  input M00_ACLK;\n  input M00_ARESETN;\n  output [63:0]M00_AXI_araddr;\n  output [1:0]M00_AXI_arburst;\n  output [3:0]M00_AXI_arcache;\n  output [6:0]M00_AXI_arid;\n  output [7:0]M00_AXI_arlen;\n  output [0:0]M00_AXI_arlock;\n  output [2:0]M00_AXI_arprot;\n  output [3:0]M00_AXI_arqos;\n  input M00_AXI_arready;\n  output [3:0]M00_AXI_arregion;\n  output [2:0]M00_AXI_arsize;\n  output M00_AXI_arvalid;\n  output [63:0]M00_AXI_awaddr;\n  output [1:0]M00_AXI_awburst;\n  output [3:0]M00_AXI_awcache;\n  output [6:0]M00_AXI_awid;\n  output [7:0]M00_AXI_awlen;\n  output [0:0]M00_AXI_awlock;\n  output [2:0]M00_AXI_awprot;\n  output [3:0]M00_AXI_awqos;\n  input M00_AXI_awready;\n  output [3:0]M00_AXI_awregion;\n  output [2:0]M00_AXI_awsize;\n  output M00_AXI_awvalid;\n  input [6:0]M00_AXI_bid;\n  output M00_AXI_bready;\n  input [1:0]M00_AXI_bresp;\n  input M00_AXI_bvalid;\n  input [511:0]M00_AXI_rdata;\n  input [6:0]M00_AXI_rid;\n  input M00_AXI_rlast;\n  output M00_AXI_rready;\n  input [1:0]M00_AXI_rresp;\n  input M00_AXI_rvalid;\n  output [511:0]M00_AXI_wdata;\n  output M00_AXI_wlast;\n  input M00_AXI_wready;\n  output [63:0]M00_AXI_wstrb;\n  output M00_AXI_wvalid;\n  input M01_ACLK;\n  input M01_ARESETN;\n  output [63:0]M01_AXI_araddr;\n  output [1:0]M01_AXI_arburst;\n  output [3:0]M01_AXI_arcache;\n  output [6:0]M01_AXI_arid;\n  output [7:0]M01_AXI_arlen;\n  output [0:0]M01_AXI_arlock;\n  output [2:0]M01_AXI_arprot;\n  output [3:0]M01_AXI_arqos;\n  input M01_AXI_arready;\n  output [3:0]M01_AXI_arregion;\n  output [2:0]M01_AXI_arsize;\n  output M01_AXI_arvalid;\n  output [63:0]M01_AXI_awaddr;\n  output [1:0]M01_AXI_awburst;\n  output [3:0]M01_AXI_awcache;\n  output [6:0]M01_AXI_awid;\n  output [7:0]M01_AXI_awlen;\n  output [0:0]M01_AXI_awlock;\n  output [2:0]M01_AXI_awprot;\n  output [3:0]M01_AXI_awqos;\n  input M01_AXI_awready;\n  output [3:0]M01_AXI_awregion;\n  output [2:0]M01_AXI_awsize;\n  output M01_AXI_awvalid;\n  input [6:0]M01_AXI_bid;\n  output M01_AXI_bready;\n  input [1:0]M01_AXI_bresp;\n  input M01_AXI_bvalid;\n  input [511:0]M01_AXI_rdata;\n  input [6:0]M01_AXI_rid;\n  input M01_AXI_rlast;\n  output M01_AXI_rready;\n  input [1:0]M01_AXI_rresp;\n  input M01_AXI_rvalid;\n  output [511:0]M01_AXI_wdata;\n  output M01_AXI_wlast;\n  input M01_AXI_wready;\n  output [63:0]M01_AXI_wstrb;\n  output M01_AXI_wvalid;\n  input M02_ACLK;\n  input M02_ARESETN;\n  output [63:0]M02_AXI_araddr;\n  output [1:0]M02_AXI_arburst;\n  output [3:0]M02_AXI_arcache;\n  output [6:0]M02_AXI_arid;\n  output [7:0]M02_AXI_arlen;\n  output [0:0]M02_AXI_arlock;\n  output [2:0]M02_AXI_arprot;\n  output [3:0]M02_AXI_arqos;\n  input M02_AXI_arready;\n  output [3:0]M02_AXI_arregion;\n  output [2:0]M02_AXI_arsize;\n  output M02_AXI_arvalid;\n  output [63:0]M02_AXI_awaddr;\n  output [1:0]M02_AXI_awburst;\n  output [3:0]M02_AXI_awcache;\n  output [6:0]M02_AXI_awid;\n  output [7:0]M02_AXI_awlen;\n  output [0:0]M02_AXI_awlock;\n  output [2:0]M02_AXI_awprot;\n  output [3:0]M02_AXI_awqos;\n  input M02_AXI_awready;\n  output [3:0]M02_AXI_awregion;\n  output [2:0]M02_AXI_awsize;\n  output M02_AXI_awvalid;\n  input [6:0]M02_AXI_bid;\n  output M02_AXI_bready;\n  input [1:0]M02_AXI_bresp;\n  input M02_AXI_bvalid;\n  input [511:0]M02_AXI_rdata;\n  input [6:0]M02_AXI_rid;\n  input M02_AXI_rlast;\n  output M02_AXI_rready;\n  input [1:0]M02_AXI_rresp;\n  input M02_AXI_rvalid;\n  output [511:0]M02_AXI_wdata;\n  output M02_AXI_wlast;\n  input M02_AXI_wready;\n  output [63:0]M02_AXI_wstrb;\n  output M02_AXI_wvalid;\n  input M03_ACLK;\n  input M03_ARESETN;\n  output [63:0]M03_AXI_araddr;\n  output [1:0]M03_AXI_arburst;\n  output [3:0]M03_AXI_arcache;\n  output [6:0]M03_AXI_arid;\n  output [7:0]M03_AXI_arlen;\n  output [0:0]M03_AXI_arlock;\n  output [2:0]M03_AXI_arprot;\n  output [3:0]M03_AXI_arqos;\n  input M03_AXI_arready;\n  output [3:0]M03_AXI_arregion;\n  output [2:0]M03_AXI_arsize;\n  output M03_AXI_arvalid;\n  output [63:0]M03_AXI_awaddr;\n  output [1:0]M03_AXI_awburst;\n  output [3:0]M03_AXI_awcache;\n  output [6:0]M03_AXI_awid;\n  output [7:0]M03_AXI_awlen;\n  output [0:0]M03_AXI_awlock;\n  output [2:0]M03_AXI_awprot;\n  output [3:0]M03_AXI_awqos;\n  input M03_AXI_awready;\n  output [3:0]M03_AXI_awregion;\n  output [2:0]M03_AXI_awsize;\n  output M03_AXI_awvalid;\n  input [6:0]M03_AXI_bid;\n  output M03_AXI_bready;\n  input [1:0]M03_AXI_bresp;\n  input M03_AXI_bvalid;\n  input [511:0]M03_AXI_rdata;\n  input [6:0]M03_AXI_rid;\n  input M03_AXI_rlast;\n  output M03_AXI_rready;\n  input [1:0]M03_AXI_rresp;\n  input M03_AXI_rvalid;\n  output [511:0]M03_AXI_wdata;\n  output M03_AXI_wlast;\n  input M03_AXI_wready;\n  output [63:0]M03_AXI_wstrb;\n  output M03_AXI_wvalid;\n  input S00_ACLK;\n  input S00_ARESETN;\n  input [63:0]S00_AXI_araddr;\n  input [1:0]S00_AXI_arburst;\n  input [3:0]S00_AXI_arcache;\n  input [5:0]S00_AXI_arid;\n  input [7:0]S00_AXI_arlen;\n  input [0:0]S00_AXI_arlock;\n  input [2:0]S00_AXI_arprot;\n  input [3:0]S00_AXI_arqos;\n  output S00_AXI_arready;\n  input [3:0]S00_AXI_arregion;\n  input [2:0]S00_AXI_arsize;\n  input S00_AXI_arvalid;\n  input [63:0]S00_AXI_awaddr;\n  input [1:0]S00_AXI_awburst;\n  input [3:0]S00_AXI_awcache;\n  input [5:0]S00_AXI_awid;\n  input [7:0]S00_AXI_awlen;\n  input [0:0]S00_AXI_awlock;\n  input [2:0]S00_AXI_awprot;\n  input [3:0]S00_AXI_awqos;\n  output S00_AXI_awready;\n  input [3:0]S00_AXI_awregion;\n  input [2:0]S00_AXI_awsize;\n  input S00_AXI_awvalid;\n  output [5:0]S00_AXI_bid;\n  input S00_AXI_bready;\n  output [1:0]S00_AXI_bresp;\n  output S00_AXI_bvalid;\n  output [511:0]S00_AXI_rdata;\n  output [5:0]S00_AXI_rid;\n  output S00_AXI_rlast;\n  input S00_AXI_rready;\n  output [1:0]S00_AXI_rresp;\n  output S00_AXI_rvalid;\n  input [511:0]S00_AXI_wdata;\n  input S00_AXI_wlast;\n  output S00_AXI_wready;\n  input [63:0]S00_AXI_wstrb;\n  input S00_AXI_wvalid;\n  input S01_ACLK;\n  input S01_ARESETN;\n  input [63:0]S01_AXI_araddr;\n  input [1:0]S01_AXI_arburst;\n  input [3:0]S01_AXI_arcache;\n  input [5:0]S01_AXI_arid;\n  input [7:0]S01_AXI_arlen;\n  input [0:0]S01_AXI_arlock;\n  input [2:0]S01_AXI_arprot;\n  input [3:0]S01_AXI_arqos;\n  output S01_AXI_arready;\n  input [3:0]S01_AXI_arregion;\n  input [2:0]S01_AXI_arsize;\n  input S01_AXI_arvalid;\n  input [63:0]S01_AXI_awaddr;\n  input [1:0]S01_AXI_awburst;\n  input [3:0]S01_AXI_awcache;\n  input [5:0]S01_AXI_awid;\n  input [7:0]S01_AXI_awlen;\n  input [0:0]S01_AXI_awlock;\n  input [2:0]S01_AXI_awprot;\n  input [3:0]S01_AXI_awqos;\n  output S01_AXI_awready;\n  input [3:0]S01_AXI_awregion;\n  input [2:0]S01_AXI_awsize;\n  input S01_AXI_awvalid;\n  output [5:0]S01_AXI_bid;\n  input S01_AXI_bready;\n  output [1:0]S01_AXI_bresp;\n  output S01_AXI_bvalid;\n  output [511:0]S01_AXI_rdata;\n  output [5:0]S01_AXI_rid;\n  output S01_AXI_rlast;\n  input S01_AXI_rready;\n  output [1:0]S01_AXI_rresp;\n  output S01_AXI_rvalid;\n  input [511:0]S01_AXI_wdata;\n  input S01_AXI_wlast;\n  output S01_AXI_wready;\n  input [63:0]S01_AXI_wstrb;\n  input S01_AXI_wvalid;\n\n  wire axi_interconnect_0_ACLK_net;\n  wire axi_interconnect_0_ARESETN_net;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_ARADDR;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_ARBURST;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARCACHE;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_ARID;\n  wire [7:0]axi_interconnect_0_to_s00_couplers_ARLEN;\n  wire [0:0]axi_interconnect_0_to_s00_couplers_ARLOCK;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_ARPROT;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARQOS;\n  wire axi_interconnect_0_to_s00_couplers_ARREADY;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARREGION;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_ARSIZE;\n  wire axi_interconnect_0_to_s00_couplers_ARVALID;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_AWADDR;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_AWBURST;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWCACHE;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_AWID;\n  wire [7:0]axi_interconnect_0_to_s00_couplers_AWLEN;\n  wire [0:0]axi_interconnect_0_to_s00_couplers_AWLOCK;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_AWPROT;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWQOS;\n  wire axi_interconnect_0_to_s00_couplers_AWREADY;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWREGION;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_AWSIZE;\n  wire axi_interconnect_0_to_s00_couplers_AWVALID;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_BID;\n  wire axi_interconnect_0_to_s00_couplers_BREADY;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_BRESP;\n  wire axi_interconnect_0_to_s00_couplers_BVALID;\n  wire [511:0]axi_interconnect_0_to_s00_couplers_RDATA;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_RID;\n  wire axi_interconnect_0_to_s00_couplers_RLAST;\n  wire axi_interconnect_0_to_s00_couplers_RREADY;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_RRESP;\n  wire axi_interconnect_0_to_s00_couplers_RVALID;\n  wire [511:0]axi_interconnect_0_to_s00_couplers_WDATA;\n  wire axi_interconnect_0_to_s00_couplers_WLAST;\n  wire axi_interconnect_0_to_s00_couplers_WREADY;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_WSTRB;\n  wire axi_interconnect_0_to_s00_couplers_WVALID;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_ARADDR;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_ARBURST;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARCACHE;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_ARID;\n  wire [7:0]axi_interconnect_0_to_s01_couplers_ARLEN;\n  wire [0:0]axi_interconnect_0_to_s01_couplers_ARLOCK;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_ARPROT;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARQOS;\n  wire axi_interconnect_0_to_s01_couplers_ARREADY;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARREGION;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_ARSIZE;\n  wire axi_interconnect_0_to_s01_couplers_ARVALID;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_AWADDR;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_AWBURST;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWCACHE;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_AWID;\n  wire [7:0]axi_interconnect_0_to_s01_couplers_AWLEN;\n  wire [0:0]axi_interconnect_0_to_s01_couplers_AWLOCK;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_AWPROT;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWQOS;\n  wire axi_interconnect_0_to_s01_couplers_AWREADY;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWREGION;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_AWSIZE;\n  wire axi_interconnect_0_to_s01_couplers_AWVALID;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_BID;\n  wire axi_interconnect_0_to_s01_couplers_BREADY;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_BRESP;\n  wire axi_interconnect_0_to_s01_couplers_BVALID;\n  wire [511:0]axi_interconnect_0_to_s01_couplers_RDATA;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_RID;\n  wire axi_interconnect_0_to_s01_couplers_RLAST;\n  wire axi_interconnect_0_to_s01_couplers_RREADY;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_RRESP;\n  wire axi_interconnect_0_to_s01_couplers_RVALID;\n  wire [511:0]axi_interconnect_0_to_s01_couplers_WDATA;\n  wire axi_interconnect_0_to_s01_couplers_WLAST;\n  wire axi_interconnect_0_to_s01_couplers_WREADY;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_WSTRB;\n  wire axi_interconnect_0_to_s01_couplers_WVALID;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m00_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m00_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARQOS;\n  wire m00_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m00_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m00_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m00_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWQOS;\n  wire m00_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m00_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_BID;\n  wire m00_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_BRESP;\n  wire m00_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m00_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_RID;\n  wire m00_couplers_to_axi_interconnect_0_RLAST;\n  wire m00_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_RRESP;\n  wire m00_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m00_couplers_to_axi_interconnect_0_WDATA;\n  wire m00_couplers_to_axi_interconnect_0_WLAST;\n  wire m00_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_WSTRB;\n  wire m00_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m01_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m01_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARQOS;\n  wire m01_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m01_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m01_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m01_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWQOS;\n  wire m01_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m01_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_BID;\n  wire m01_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_BRESP;\n  wire m01_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m01_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_RID;\n  wire m01_couplers_to_axi_interconnect_0_RLAST;\n  wire m01_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_RRESP;\n  wire m01_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m01_couplers_to_axi_interconnect_0_WDATA;\n  wire m01_couplers_to_axi_interconnect_0_WLAST;\n  wire m01_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_WSTRB;\n  wire m01_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m02_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m02_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARQOS;\n  wire m02_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m02_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m02_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m02_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWQOS;\n  wire m02_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m02_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_BID;\n  wire m02_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_BRESP;\n  wire m02_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m02_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_RID;\n  wire m02_couplers_to_axi_interconnect_0_RLAST;\n  wire m02_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_RRESP;\n  wire m02_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m02_couplers_to_axi_interconnect_0_WDATA;\n  wire m02_couplers_to_axi_interconnect_0_WLAST;\n  wire m02_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_WSTRB;\n  wire m02_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m03_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m03_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARQOS;\n  wire m03_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m03_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m03_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m03_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWQOS;\n  wire m03_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m03_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_BID;\n  wire m03_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_BRESP;\n  wire m03_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m03_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_RID;\n  wire m03_couplers_to_axi_interconnect_0_RLAST;\n  wire m03_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_RRESP;\n  wire m03_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m03_couplers_to_axi_interconnect_0_WDATA;\n  wire m03_couplers_to_axi_interconnect_0_WLAST;\n  wire m03_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_WSTRB;\n  wire m03_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]s00_couplers_to_xbar_ARADDR;\n  wire [1:0]s00_couplers_to_xbar_ARBURST;\n  wire [3:0]s00_couplers_to_xbar_ARCACHE;\n  wire [5:0]s00_couplers_to_xbar_ARID;\n  wire [7:0]s00_couplers_to_xbar_ARLEN;\n  wire [0:0]s00_couplers_to_xbar_ARLOCK;\n  wire [2:0]s00_couplers_to_xbar_ARPROT;\n  wire [3:0]s00_couplers_to_xbar_ARQOS;\n  wire [0:0]s00_couplers_to_xbar_ARREADY;\n  wire [2:0]s00_couplers_to_xbar_ARSIZE;\n  wire s00_couplers_to_xbar_ARVALID;\n  wire [63:0]s00_couplers_to_xbar_AWADDR;\n  wire [1:0]s00_couplers_to_xbar_AWBURST;\n  wire [3:0]s00_couplers_to_xbar_AWCACHE;\n  wire [5:0]s00_couplers_to_xbar_AWID;\n  wire [7:0]s00_couplers_to_xbar_AWLEN;\n  wire [0:0]s00_couplers_to_xbar_AWLOCK;\n  wire [2:0]s00_couplers_to_xbar_AWPROT;\n  wire [3:0]s00_couplers_to_xbar_AWQOS;\n  wire [0:0]s00_couplers_to_xbar_AWREADY;\n  wire [2:0]s00_couplers_to_xbar_AWSIZE;\n  wire s00_couplers_to_xbar_AWVALID;\n  wire [6:0]s00_couplers_to_xbar_BID;\n  wire s00_couplers_to_xbar_BREADY;\n  wire [1:0]s00_couplers_to_xbar_BRESP;\n  wire [0:0]s00_couplers_to_xbar_BVALID;\n  wire [511:0]s00_couplers_to_xbar_RDATA;\n  wire [6:0]s00_couplers_to_xbar_RID;\n  wire [0:0]s00_couplers_to_xbar_RLAST;\n  wire s00_couplers_to_xbar_RREADY;\n  wire [1:0]s00_couplers_to_xbar_RRESP;\n  wire [0:0]s00_couplers_to_xbar_RVALID;\n  wire [511:0]s00_couplers_to_xbar_WDATA;\n  wire s00_couplers_to_xbar_WLAST;\n  wire [0:0]s00_couplers_to_xbar_WREADY;\n  wire [63:0]s00_couplers_to_xbar_WSTRB;\n  wire s00_couplers_to_xbar_WVALID;\n  wire [63:0]s01_couplers_to_xbar_ARADDR;\n  wire [1:0]s01_couplers_to_xbar_ARBURST;\n  wire [3:0]s01_couplers_to_xbar_ARCACHE;\n  wire [5:0]s01_couplers_to_xbar_ARID;\n  wire [7:0]s01_couplers_to_xbar_ARLEN;\n  wire [0:0]s01_couplers_to_xbar_ARLOCK;\n  wire [2:0]s01_couplers_to_xbar_ARPROT;\n  wire [3:0]s01_couplers_to_xbar_ARQOS;\n  wire [1:1]s01_couplers_to_xbar_ARREADY;\n  wire [2:0]s01_couplers_to_xbar_ARSIZE;\n  wire s01_couplers_to_xbar_ARVALID;\n  wire [63:0]s01_couplers_to_xbar_AWADDR;\n  wire [1:0]s01_couplers_to_xbar_AWBURST;\n  wire [3:0]s01_couplers_to_xbar_AWCACHE;\n  wire [5:0]s01_couplers_to_xbar_AWID;\n  wire [7:0]s01_couplers_to_xbar_AWLEN;\n  wire [0:0]s01_couplers_to_xbar_AWLOCK;\n  wire [2:0]s01_couplers_to_xbar_AWPROT;\n  wire [3:0]s01_couplers_to_xbar_AWQOS;\n  wire [1:1]s01_couplers_to_xbar_AWREADY;\n  wire [2:0]s01_couplers_to_xbar_AWSIZE;\n  wire s01_couplers_to_xbar_AWVALID;\n  wire [13:7]s01_couplers_to_xbar_BID;\n  wire s01_couplers_to_xbar_BREADY;\n  wire [3:2]s01_couplers_to_xbar_BRESP;\n  wire [1:1]s01_couplers_to_xbar_BVALID;\n  wire [1023:512]s01_couplers_to_xbar_RDATA;\n  wire [13:7]s01_couplers_to_xbar_RID;\n  wire [1:1]s01_couplers_to_xbar_RLAST;\n  wire s01_couplers_to_xbar_RREADY;\n  wire [3:2]s01_couplers_to_xbar_RRESP;\n  wire [1:1]s01_couplers_to_xbar_RVALID;\n  wire [511:0]s01_couplers_to_xbar_WDATA;\n  wire s01_couplers_to_xbar_WLAST;\n  wire [1:1]s01_couplers_to_xbar_WREADY;\n  wire [63:0]s01_couplers_to_xbar_WSTRB;\n  wire s01_couplers_to_xbar_WVALID;\n  wire [63:0]xbar_to_m00_couplers_ARADDR;\n  wire [1:0]xbar_to_m00_couplers_ARBURST;\n  wire [3:0]xbar_to_m00_couplers_ARCACHE;\n  wire [6:0]xbar_to_m00_couplers_ARID;\n  wire [7:0]xbar_to_m00_couplers_ARLEN;\n  wire [0:0]xbar_to_m00_couplers_ARLOCK;\n  wire [2:0]xbar_to_m00_couplers_ARPROT;\n  wire [3:0]xbar_to_m00_couplers_ARQOS;\n  wire xbar_to_m00_couplers_ARREADY;\n  wire [3:0]xbar_to_m00_couplers_ARREGION;\n  wire [2:0]xbar_to_m00_couplers_ARSIZE;\n  wire [0:0]xbar_to_m00_couplers_ARVALID;\n  wire [63:0]xbar_to_m00_couplers_AWADDR;\n  wire [1:0]xbar_to_m00_couplers_AWBURST;\n  wire [3:0]xbar_to_m00_couplers_AWCACHE;\n  wire [6:0]xbar_to_m00_couplers_AWID;\n  wire [7:0]xbar_to_m00_couplers_AWLEN;\n  wire [0:0]xbar_to_m00_couplers_AWLOCK;\n  wire [2:0]xbar_to_m00_couplers_AWPROT;\n  wire [3:0]xbar_to_m00_couplers_AWQOS;\n  wire xbar_to_m00_couplers_AWREADY;\n  wire [3:0]xbar_to_m00_couplers_AWREGION;\n  wire [2:0]xbar_to_m00_couplers_AWSIZE;\n  wire [0:0]xbar_to_m00_couplers_AWVALID;\n  wire [6:0]xbar_to_m00_couplers_BID;\n  wire [0:0]xbar_to_m00_couplers_BREADY;\n  wire [1:0]xbar_to_m00_couplers_BRESP;\n  wire xbar_to_m00_couplers_BVALID;\n  wire [511:0]xbar_to_m00_couplers_RDATA;\n  wire [6:0]xbar_to_m00_couplers_RID;\n  wire xbar_to_m00_couplers_RLAST;\n  wire [0:0]xbar_to_m00_couplers_RREADY;\n  wire [1:0]xbar_to_m00_couplers_RRESP;\n  wire xbar_to_m00_couplers_RVALID;\n  wire [511:0]xbar_to_m00_couplers_WDATA;\n  wire [0:0]xbar_to_m00_couplers_WLAST;\n  wire xbar_to_m00_couplers_WREADY;\n  wire [63:0]xbar_to_m00_couplers_WSTRB;\n  wire [0:0]xbar_to_m00_couplers_WVALID;\n  wire [127:64]xbar_to_m01_couplers_ARADDR;\n  wire [3:2]xbar_to_m01_couplers_ARBURST;\n  wire [7:4]xbar_to_m01_couplers_ARCACHE;\n  wire [13:7]xbar_to_m01_couplers_ARID;\n  wire [15:8]xbar_to_m01_couplers_ARLEN;\n  wire [1:1]xbar_to_m01_couplers_ARLOCK;\n  wire [5:3]xbar_to_m01_couplers_ARPROT;\n  wire [7:4]xbar_to_m01_couplers_ARQOS;\n  wire xbar_to_m01_couplers_ARREADY;\n  wire [7:4]xbar_to_m01_couplers_ARREGION;\n  wire [5:3]xbar_to_m01_couplers_ARSIZE;\n  wire [1:1]xbar_to_m01_couplers_ARVALID;\n  wire [127:64]xbar_to_m01_couplers_AWADDR;\n  wire [3:2]xbar_to_m01_couplers_AWBURST;\n  wire [7:4]xbar_to_m01_couplers_AWCACHE;\n  wire [13:7]xbar_to_m01_couplers_AWID;\n  wire [15:8]xbar_to_m01_couplers_AWLEN;\n  wire [1:1]xbar_to_m01_couplers_AWLOCK;\n  wire [5:3]xbar_to_m01_couplers_AWPROT;\n  wire [7:4]xbar_to_m01_couplers_AWQOS;\n  wire xbar_to_m01_couplers_AWREADY;\n  wire [7:4]xbar_to_m01_couplers_AWREGION;\n  wire [5:3]xbar_to_m01_couplers_AWSIZE;\n  wire [1:1]xbar_to_m01_couplers_AWVALID;\n  wire [6:0]xbar_to_m01_couplers_BID;\n  wire [1:1]xbar_to_m01_couplers_BREADY;\n  wire [1:0]xbar_to_m01_couplers_BRESP;\n  wire xbar_to_m01_couplers_BVALID;\n  wire [511:0]xbar_to_m01_couplers_RDATA;\n  wire [6:0]xbar_to_m01_couplers_RID;\n  wire xbar_to_m01_couplers_RLAST;\n  wire [1:1]xbar_to_m01_couplers_RREADY;\n  wire [1:0]xbar_to_m01_couplers_RRESP;\n  wire xbar_to_m01_couplers_RVALID;\n  wire [1023:512]xbar_to_m01_couplers_WDATA;\n  wire [1:1]xbar_to_m01_couplers_WLAST;\n  wire xbar_to_m01_couplers_WREADY;\n  wire [127:64]xbar_to_m01_couplers_WSTRB;\n  wire [1:1]xbar_to_m01_couplers_WVALID;\n  wire [191:128]xbar_to_m02_couplers_ARADDR;\n  wire [5:4]xbar_to_m02_couplers_ARBURST;\n  wire [11:8]xbar_to_m02_couplers_ARCACHE;\n  wire [20:14]xbar_to_m02_couplers_ARID;\n  wire [23:16]xbar_to_m02_couplers_ARLEN;\n  wire [2:2]xbar_to_m02_couplers_ARLOCK;\n  wire [8:6]xbar_to_m02_couplers_ARPROT;\n  wire [11:8]xbar_to_m02_couplers_ARQOS;\n  wire xbar_to_m02_couplers_ARREADY;\n  wire [11:8]xbar_to_m02_couplers_ARREGION;\n  wire [8:6]xbar_to_m02_couplers_ARSIZE;\n  wire [2:2]xbar_to_m02_couplers_ARVALID;\n  wire [191:128]xbar_to_m02_couplers_AWADDR;\n  wire [5:4]xbar_to_m02_couplers_AWBURST;\n  wire [11:8]xbar_to_m02_couplers_AWCACHE;\n  wire [20:14]xbar_to_m02_couplers_AWID;\n  wire [23:16]xbar_to_m02_couplers_AWLEN;\n  wire [2:2]xbar_to_m02_couplers_AWLOCK;\n  wire [8:6]xbar_to_m02_couplers_AWPROT;\n  wire [11:8]xbar_to_m02_couplers_AWQOS;\n  wire xbar_to_m02_couplers_AWREADY;\n  wire [11:8]xbar_to_m02_couplers_AWREGION;\n  wire [8:6]xbar_to_m02_couplers_AWSIZE;\n  wire [2:2]xbar_to_m02_couplers_AWVALID;\n  wire [6:0]xbar_to_m02_couplers_BID;\n  wire [2:2]xbar_to_m02_couplers_BREADY;\n  wire [1:0]xbar_to_m02_couplers_BRESP;\n  wire xbar_to_m02_couplers_BVALID;\n  wire [511:0]xbar_to_m02_couplers_RDATA;\n  wire [6:0]xbar_to_m02_couplers_RID;\n  wire xbar_to_m02_couplers_RLAST;\n  wire [2:2]xbar_to_m02_couplers_RREADY;\n  wire [1:0]xbar_to_m02_couplers_RRESP;\n  wire xbar_to_m02_couplers_RVALID;\n  wire [1535:1024]xbar_to_m02_couplers_WDATA;\n  wire [2:2]xbar_to_m02_couplers_WLAST;\n  wire xbar_to_m02_couplers_WREADY;\n  wire [191:128]xbar_to_m02_couplers_WSTRB;\n  wire [2:2]xbar_to_m02_couplers_WVALID;\n  wire [255:192]xbar_to_m03_couplers_ARADDR;\n  wire [7:6]xbar_to_m03_couplers_ARBURST;\n  wire [15:12]xbar_to_m03_couplers_ARCACHE;\n  wire [27:21]xbar_to_m03_couplers_ARID;\n  wire [31:24]xbar_to_m03_couplers_ARLEN;\n  wire [3:3]xbar_to_m03_couplers_ARLOCK;\n  wire [11:9]xbar_to_m03_couplers_ARPROT;\n  wire [15:12]xbar_to_m03_couplers_ARQOS;\n  wire xbar_to_m03_couplers_ARREADY;\n  wire [15:12]xbar_to_m03_couplers_ARREGION;\n  wire [11:9]xbar_to_m03_couplers_ARSIZE;\n  wire [3:3]xbar_to_m03_couplers_ARVALID;\n  wire [255:192]xbar_to_m03_couplers_AWADDR;\n  wire [7:6]xbar_to_m03_couplers_AWBURST;\n  wire [15:12]xbar_to_m03_couplers_AWCACHE;\n  wire [27:21]xbar_to_m03_couplers_AWID;\n  wire [31:24]xbar_to_m03_couplers_AWLEN;\n  wire [3:3]xbar_to_m03_couplers_AWLOCK;\n  wire [11:9]xbar_to_m03_couplers_AWPROT;\n  wire [15:12]xbar_to_m03_couplers_AWQOS;\n  wire xbar_to_m03_couplers_AWREADY;\n  wire [15:12]xbar_to_m03_couplers_AWREGION;\n  wire [11:9]xbar_to_m03_couplers_AWSIZE;\n  wire [3:3]xbar_to_m03_couplers_AWVALID;\n  wire [6:0]xbar_to_m03_couplers_BID;\n  wire [3:3]xbar_to_m03_couplers_BREADY;\n  wire [1:0]xbar_to_m03_couplers_BRESP;\n  wire xbar_to_m03_couplers_BVALID;\n  wire [511:0]xbar_to_m03_couplers_RDATA;\n  wire [6:0]xbar_to_m03_couplers_RID;\n  wire xbar_to_m03_couplers_RLAST;\n  wire [3:3]xbar_to_m03_couplers_RREADY;\n  wire [1:0]xbar_to_m03_couplers_RRESP;\n  wire xbar_to_m03_couplers_RVALID;\n  wire [2047:1536]xbar_to_m03_couplers_WDATA;\n  wire [3:3]xbar_to_m03_couplers_WLAST;\n  wire xbar_to_m03_couplers_WREADY;\n  wire [255:192]xbar_to_m03_couplers_WSTRB;\n  wire [3:3]xbar_to_m03_couplers_WVALID;\n\n  assign M00_AXI_araddr[63:0] = m00_couplers_to_axi_interconnect_0_ARADDR;\n  assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_interconnect_0_ARBURST;\n  assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M00_AXI_arid[6:0] = m00_couplers_to_axi_interconnect_0_ARID;\n  assign M00_AXI_arlen[7:0] = m00_couplers_to_axi_interconnect_0_ARLEN;\n  assign M00_AXI_arlock[0] = m00_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_interconnect_0_ARPROT;\n  assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_interconnect_0_ARQOS;\n  assign M00_AXI_arregion[3:0] = m00_couplers_to_axi_interconnect_0_ARREGION;\n  assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M00_AXI_arvalid = m00_couplers_to_axi_interconnect_0_ARVALID;\n  assign M00_AXI_awaddr[63:0] = m00_couplers_to_axi_interconnect_0_AWADDR;\n  assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_interconnect_0_AWBURST;\n  assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M00_AXI_awid[6:0] = m00_couplers_to_axi_interconnect_0_AWID;\n  assign M00_AXI_awlen[7:0] = m00_couplers_to_axi_interconnect_0_AWLEN;\n  assign M00_AXI_awlock[0] = m00_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_interconnect_0_AWPROT;\n  assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_interconnect_0_AWQOS;\n  assign M00_AXI_awregion[3:0] = m00_couplers_to_axi_interconnect_0_AWREGION;\n  assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M00_AXI_awvalid = m00_couplers_to_axi_interconnect_0_AWVALID;\n  assign M00_AXI_bready = m00_couplers_to_axi_interconnect_0_BREADY;\n  assign M00_AXI_rready = m00_couplers_to_axi_interconnect_0_RREADY;\n  assign M00_AXI_wdata[511:0] = m00_couplers_to_axi_interconnect_0_WDATA;\n  assign M00_AXI_wlast = m00_couplers_to_axi_interconnect_0_WLAST;\n  assign M00_AXI_wstrb[63:0] = m00_couplers_to_axi_interconnect_0_WSTRB;\n  assign M00_AXI_wvalid = m00_couplers_to_axi_interconnect_0_WVALID;\n  assign M01_AXI_araddr[63:0] = m01_couplers_to_axi_interconnect_0_ARADDR;\n  assign M01_AXI_arburst[1:0] = m01_couplers_to_axi_interconnect_0_ARBURST;\n  assign M01_AXI_arcache[3:0] = m01_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M01_AXI_arid[6:0] = m01_couplers_to_axi_interconnect_0_ARID;\n  assign M01_AXI_arlen[7:0] = m01_couplers_to_axi_interconnect_0_ARLEN;\n  assign M01_AXI_arlock[0] = m01_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M01_AXI_arprot[2:0] = m01_couplers_to_axi_interconnect_0_ARPROT;\n  assign M01_AXI_arqos[3:0] = m01_couplers_to_axi_interconnect_0_ARQOS;\n  assign M01_AXI_arregion[3:0] = m01_couplers_to_axi_interconnect_0_ARREGION;\n  assign M01_AXI_arsize[2:0] = m01_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M01_AXI_arvalid = m01_couplers_to_axi_interconnect_0_ARVALID;\n  assign M01_AXI_awaddr[63:0] = m01_couplers_to_axi_interconnect_0_AWADDR;\n  assign M01_AXI_awburst[1:0] = m01_couplers_to_axi_interconnect_0_AWBURST;\n  assign M01_AXI_awcache[3:0] = m01_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M01_AXI_awid[6:0] = m01_couplers_to_axi_interconnect_0_AWID;\n  assign M01_AXI_awlen[7:0] = m01_couplers_to_axi_interconnect_0_AWLEN;\n  assign M01_AXI_awlock[0] = m01_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M01_AXI_awprot[2:0] = m01_couplers_to_axi_interconnect_0_AWPROT;\n  assign M01_AXI_awqos[3:0] = m01_couplers_to_axi_interconnect_0_AWQOS;\n  assign M01_AXI_awregion[3:0] = m01_couplers_to_axi_interconnect_0_AWREGION;\n  assign M01_AXI_awsize[2:0] = m01_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M01_AXI_awvalid = m01_couplers_to_axi_interconnect_0_AWVALID;\n  assign M01_AXI_bready = m01_couplers_to_axi_interconnect_0_BREADY;\n  assign M01_AXI_rready = m01_couplers_to_axi_interconnect_0_RREADY;\n  assign M01_AXI_wdata[511:0] = m01_couplers_to_axi_interconnect_0_WDATA;\n  assign M01_AXI_wlast = m01_couplers_to_axi_interconnect_0_WLAST;\n  assign M01_AXI_wstrb[63:0] = m01_couplers_to_axi_interconnect_0_WSTRB;\n  assign M01_AXI_wvalid = m01_couplers_to_axi_interconnect_0_WVALID;\n  assign M02_AXI_araddr[63:0] = m02_couplers_to_axi_interconnect_0_ARADDR;\n  assign M02_AXI_arburst[1:0] = m02_couplers_to_axi_interconnect_0_ARBURST;\n  assign M02_AXI_arcache[3:0] = m02_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M02_AXI_arid[6:0] = m02_couplers_to_axi_interconnect_0_ARID;\n  assign M02_AXI_arlen[7:0] = m02_couplers_to_axi_interconnect_0_ARLEN;\n  assign M02_AXI_arlock[0] = m02_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M02_AXI_arprot[2:0] = m02_couplers_to_axi_interconnect_0_ARPROT;\n  assign M02_AXI_arqos[3:0] = m02_couplers_to_axi_interconnect_0_ARQOS;\n  assign M02_AXI_arregion[3:0] = m02_couplers_to_axi_interconnect_0_ARREGION;\n  assign M02_AXI_arsize[2:0] = m02_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M02_AXI_arvalid = m02_couplers_to_axi_interconnect_0_ARVALID;\n  assign M02_AXI_awaddr[63:0] = m02_couplers_to_axi_interconnect_0_AWADDR;\n  assign M02_AXI_awburst[1:0] = m02_couplers_to_axi_interconnect_0_AWBURST;\n  assign M02_AXI_awcache[3:0] = m02_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M02_AXI_awid[6:0] = m02_couplers_to_axi_interconnect_0_AWID;\n  assign M02_AXI_awlen[7:0] = m02_couplers_to_axi_interconnect_0_AWLEN;\n  assign M02_AXI_awlock[0] = m02_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M02_AXI_awprot[2:0] = m02_couplers_to_axi_interconnect_0_AWPROT;\n  assign M02_AXI_awqos[3:0] = m02_couplers_to_axi_interconnect_0_AWQOS;\n  assign M02_AXI_awregion[3:0] = m02_couplers_to_axi_interconnect_0_AWREGION;\n  assign M02_AXI_awsize[2:0] = m02_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M02_AXI_awvalid = m02_couplers_to_axi_interconnect_0_AWVALID;\n  assign M02_AXI_bready = m02_couplers_to_axi_interconnect_0_BREADY;\n  assign M02_AXI_rready = m02_couplers_to_axi_interconnect_0_RREADY;\n  assign M02_AXI_wdata[511:0] = m02_couplers_to_axi_interconnect_0_WDATA;\n  assign M02_AXI_wlast = m02_couplers_to_axi_interconnect_0_WLAST;\n  assign M02_AXI_wstrb[63:0] = m02_couplers_to_axi_interconnect_0_WSTRB;\n  assign M02_AXI_wvalid = m02_couplers_to_axi_interconnect_0_WVALID;\n  assign M03_AXI_araddr[63:0] = m03_couplers_to_axi_interconnect_0_ARADDR;\n  assign M03_AXI_arburst[1:0] = m03_couplers_to_axi_interconnect_0_ARBURST;\n  assign M03_AXI_arcache[3:0] = m03_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M03_AXI_arid[6:0] = m03_couplers_to_axi_interconnect_0_ARID;\n  assign M03_AXI_arlen[7:0] = m03_couplers_to_axi_interconnect_0_ARLEN;\n  assign M03_AXI_arlock[0] = m03_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M03_AXI_arprot[2:0] = m03_couplers_to_axi_interconnect_0_ARPROT;\n  assign M03_AXI_arqos[3:0] = m03_couplers_to_axi_interconnect_0_ARQOS;\n  assign M03_AXI_arregion[3:0] = m03_couplers_to_axi_interconnect_0_ARREGION;\n  assign M03_AXI_arsize[2:0] = m03_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M03_AXI_arvalid = m03_couplers_to_axi_interconnect_0_ARVALID;\n  assign M03_AXI_awaddr[63:0] = m03_couplers_to_axi_interconnect_0_AWADDR;\n  assign M03_AXI_awburst[1:0] = m03_couplers_to_axi_interconnect_0_AWBURST;\n  assign M03_AXI_awcache[3:0] = m03_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M03_AXI_awid[6:0] = m03_couplers_to_axi_interconnect_0_AWID;\n  assign M03_AXI_awlen[7:0] = m03_couplers_to_axi_interconnect_0_AWLEN;\n  assign M03_AXI_awlock[0] = m03_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M03_AXI_awprot[2:0] = m03_couplers_to_axi_interconnect_0_AWPROT;\n  assign M03_AXI_awqos[3:0] = m03_couplers_to_axi_interconnect_0_AWQOS;\n  assign M03_AXI_awregion[3:0] = m03_couplers_to_axi_interconnect_0_AWREGION;\n  assign M03_AXI_awsize[2:0] = m03_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M03_AXI_awvalid = m03_couplers_to_axi_interconnect_0_AWVALID;\n  assign M03_AXI_bready = m03_couplers_to_axi_interconnect_0_BREADY;\n  assign M03_AXI_rready = m03_couplers_to_axi_interconnect_0_RREADY;\n  assign M03_AXI_wdata[511:0] = m03_couplers_to_axi_interconnect_0_WDATA;\n  assign M03_AXI_wlast = m03_couplers_to_axi_interconnect_0_WLAST;\n  assign M03_AXI_wstrb[63:0] = m03_couplers_to_axi_interconnect_0_WSTRB;\n  assign M03_AXI_wvalid = m03_couplers_to_axi_interconnect_0_WVALID;\n  assign S00_AXI_arready = axi_interconnect_0_to_s00_couplers_ARREADY;\n  assign S00_AXI_awready = axi_interconnect_0_to_s00_couplers_AWREADY;\n  assign S00_AXI_bid[5:0] = axi_interconnect_0_to_s00_couplers_BID;\n  assign S00_AXI_bresp[1:0] = axi_interconnect_0_to_s00_couplers_BRESP;\n  assign S00_AXI_bvalid = axi_interconnect_0_to_s00_couplers_BVALID;\n  assign S00_AXI_rdata[511:0] = axi_interconnect_0_to_s00_couplers_RDATA;\n  assign S00_AXI_rid[5:0] = axi_interconnect_0_to_s00_couplers_RID;\n  assign S00_AXI_rlast = axi_interconnect_0_to_s00_couplers_RLAST;\n  assign S00_AXI_rresp[1:0] = axi_interconnect_0_to_s00_couplers_RRESP;\n  assign S00_AXI_rvalid = axi_interconnect_0_to_s00_couplers_RVALID;\n  assign S00_AXI_wready = axi_interconnect_0_to_s00_couplers_WREADY;\n  assign S01_AXI_arready = axi_interconnect_0_to_s01_couplers_ARREADY;\n  assign S01_AXI_awready = axi_interconnect_0_to_s01_couplers_AWREADY;\n  assign S01_AXI_bid[5:0] = axi_interconnect_0_to_s01_couplers_BID;\n  assign S01_AXI_bresp[1:0] = axi_interconnect_0_to_s01_couplers_BRESP;\n  assign S01_AXI_bvalid = axi_interconnect_0_to_s01_couplers_BVALID;\n  assign S01_AXI_rdata[511:0] = axi_interconnect_0_to_s01_couplers_RDATA;\n  assign S01_AXI_rid[5:0] = axi_interconnect_0_to_s01_couplers_RID;\n  assign S01_AXI_rlast = axi_interconnect_0_to_s01_couplers_RLAST;\n  assign S01_AXI_rresp[1:0] = axi_interconnect_0_to_s01_couplers_RRESP;\n  assign S01_AXI_rvalid = axi_interconnect_0_to_s01_couplers_RVALID;\n  assign S01_AXI_wready = axi_interconnect_0_to_s01_couplers_WREADY;\n  assign axi_interconnect_0_ACLK_net = ACLK;\n  assign axi_interconnect_0_ARESETN_net = ARESETN;\n  assign axi_interconnect_0_to_s00_couplers_ARADDR = S00_AXI_araddr[63:0];\n  assign axi_interconnect_0_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];\n  assign axi_interconnect_0_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARID = S00_AXI_arid[5:0];\n  assign axi_interconnect_0_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0];\n  assign axi_interconnect_0_to_s00_couplers_ARLOCK = S00_AXI_arlock[0];\n  assign axi_interconnect_0_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];\n  assign axi_interconnect_0_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARREGION = S00_AXI_arregion[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];\n  assign axi_interconnect_0_to_s00_couplers_ARVALID = S00_AXI_arvalid;\n  assign axi_interconnect_0_to_s00_couplers_AWADDR = S00_AXI_awaddr[63:0];\n  assign axi_interconnect_0_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];\n  assign axi_interconnect_0_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWID = S00_AXI_awid[5:0];\n  assign axi_interconnect_0_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0];\n  assign axi_interconnect_0_to_s00_couplers_AWLOCK = S00_AXI_awlock[0];\n  assign axi_interconnect_0_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];\n  assign axi_interconnect_0_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWREGION = S00_AXI_awregion[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];\n  assign axi_interconnect_0_to_s00_couplers_AWVALID = S00_AXI_awvalid;\n  assign axi_interconnect_0_to_s00_couplers_BREADY = S00_AXI_bready;\n  assign axi_interconnect_0_to_s00_couplers_RREADY = S00_AXI_rready;\n  assign axi_interconnect_0_to_s00_couplers_WDATA = S00_AXI_wdata[511:0];\n  assign axi_interconnect_0_to_s00_couplers_WLAST = S00_AXI_wlast;\n  assign axi_interconnect_0_to_s00_couplers_WSTRB = S00_AXI_wstrb[63:0];\n  assign axi_interconnect_0_to_s00_couplers_WVALID = S00_AXI_wvalid;\n  assign axi_interconnect_0_to_s01_couplers_ARADDR = S01_AXI_araddr[63:0];\n  assign axi_interconnect_0_to_s01_couplers_ARBURST = S01_AXI_arburst[1:0];\n  assign axi_interconnect_0_to_s01_couplers_ARCACHE = S01_AXI_arcache[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARID = S01_AXI_arid[5:0];\n  assign axi_interconnect_0_to_s01_couplers_ARLEN = S01_AXI_arlen[7:0];\n  assign axi_interconnect_0_to_s01_couplers_ARLOCK = S01_AXI_arlock[0];\n  assign axi_interconnect_0_to_s01_couplers_ARPROT = S01_AXI_arprot[2:0];\n  assign axi_interconnect_0_to_s01_couplers_ARQOS = S01_AXI_arqos[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARREGION = S01_AXI_arregion[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARSIZE = S01_AXI_arsize[2:0];\n  assign axi_interconnect_0_to_s01_couplers_ARVALID = S01_AXI_arvalid;\n  assign axi_interconnect_0_to_s01_couplers_AWADDR = S01_AXI_awaddr[63:0];\n  assign axi_interconnect_0_to_s01_couplers_AWBURST = S01_AXI_awburst[1:0];\n  assign axi_interconnect_0_to_s01_couplers_AWCACHE = S01_AXI_awcache[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWID = S01_AXI_awid[5:0];\n  assign axi_interconnect_0_to_s01_couplers_AWLEN = S01_AXI_awlen[7:0];\n  assign axi_interconnect_0_to_s01_couplers_AWLOCK = S01_AXI_awlock[0];\n  assign axi_interconnect_0_to_s01_couplers_AWPROT = S01_AXI_awprot[2:0];\n  assign axi_interconnect_0_to_s01_couplers_AWQOS = S01_AXI_awqos[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWREGION = S01_AXI_awregion[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWSIZE = S01_AXI_awsize[2:0];\n  assign axi_interconnect_0_to_s01_couplers_AWVALID = S01_AXI_awvalid;\n  assign axi_interconnect_0_to_s01_couplers_BREADY = S01_AXI_bready;\n  assign axi_interconnect_0_to_s01_couplers_RREADY = S01_AXI_rready;\n  assign axi_interconnect_0_to_s01_couplers_WDATA = S01_AXI_wdata[511:0];\n  assign axi_interconnect_0_to_s01_couplers_WLAST = S01_AXI_wlast;\n  assign axi_interconnect_0_to_s01_couplers_WSTRB = S01_AXI_wstrb[63:0];\n  assign axi_interconnect_0_to_s01_couplers_WVALID = S01_AXI_wvalid;\n  assign m00_couplers_to_axi_interconnect_0_ARREADY = M00_AXI_arready;\n  assign m00_couplers_to_axi_interconnect_0_AWREADY = M00_AXI_awready;\n  assign m00_couplers_to_axi_interconnect_0_BID = M00_AXI_bid[6:0];\n  assign m00_couplers_to_axi_interconnect_0_BRESP = M00_AXI_bresp[1:0];\n  assign m00_couplers_to_axi_interconnect_0_BVALID = M00_AXI_bvalid;\n  assign m00_couplers_to_axi_interconnect_0_RDATA = M00_AXI_rdata[511:0];\n  assign m00_couplers_to_axi_interconnect_0_RID = M00_AXI_rid[6:0];\n  assign m00_couplers_to_axi_interconnect_0_RLAST = M00_AXI_rlast;\n  assign m00_couplers_to_axi_interconnect_0_RRESP = M00_AXI_rresp[1:0];\n  assign m00_couplers_to_axi_interconnect_0_RVALID = M00_AXI_rvalid;\n  assign m00_couplers_to_axi_interconnect_0_WREADY = M00_AXI_wready;\n  assign m01_couplers_to_axi_interconnect_0_ARREADY = M01_AXI_arready;\n  assign m01_couplers_to_axi_interconnect_0_AWREADY = M01_AXI_awready;\n  assign m01_couplers_to_axi_interconnect_0_BID = M01_AXI_bid[6:0];\n  assign m01_couplers_to_axi_interconnect_0_BRESP = M01_AXI_bresp[1:0];\n  assign m01_couplers_to_axi_interconnect_0_BVALID = M01_AXI_bvalid;\n  assign m01_couplers_to_axi_interconnect_0_RDATA = M01_AXI_rdata[511:0];\n  assign m01_couplers_to_axi_interconnect_0_RID = M01_AXI_rid[6:0];\n  assign m01_couplers_to_axi_interconnect_0_RLAST = M01_AXI_rlast;\n  assign m01_couplers_to_axi_interconnect_0_RRESP = M01_AXI_rresp[1:0];\n  assign m01_couplers_to_axi_interconnect_0_RVALID = M01_AXI_rvalid;\n  assign m01_couplers_to_axi_interconnect_0_WREADY = M01_AXI_wready;\n  assign m02_couplers_to_axi_interconnect_0_ARREADY = M02_AXI_arready;\n  assign m02_couplers_to_axi_interconnect_0_AWREADY = M02_AXI_awready;\n  assign m02_couplers_to_axi_interconnect_0_BID = M02_AXI_bid[6:0];\n  assign m02_couplers_to_axi_interconnect_0_BRESP = M02_AXI_bresp[1:0];\n  assign m02_couplers_to_axi_interconnect_0_BVALID = M02_AXI_bvalid;\n  assign m02_couplers_to_axi_interconnect_0_RDATA = M02_AXI_rdata[511:0];\n  assign m02_couplers_to_axi_interconnect_0_RID = M02_AXI_rid[6:0];\n  assign m02_couplers_to_axi_interconnect_0_RLAST = M02_AXI_rlast;\n  assign m02_couplers_to_axi_interconnect_0_RRESP = M02_AXI_rresp[1:0];\n  assign m02_couplers_to_axi_interconnect_0_RVALID = M02_AXI_rvalid;\n  assign m02_couplers_to_axi_interconnect_0_WREADY = M02_AXI_wready;\n  assign m03_couplers_to_axi_interconnect_0_ARREADY = M03_AXI_arready;\n  assign m03_couplers_to_axi_interconnect_0_AWREADY = M03_AXI_awready;\n  assign m03_couplers_to_axi_interconnect_0_BID = M03_AXI_bid[6:0];\n  assign m03_couplers_to_axi_interconnect_0_BRESP = M03_AXI_bresp[1:0];\n  assign m03_couplers_to_axi_interconnect_0_BVALID = M03_AXI_bvalid;\n  assign m03_couplers_to_axi_interconnect_0_RDATA = M03_AXI_rdata[511:0];\n  assign m03_couplers_to_axi_interconnect_0_RID = M03_AXI_rid[6:0];\n  assign m03_couplers_to_axi_interconnect_0_RLAST = M03_AXI_rlast;\n  assign m03_couplers_to_axi_interconnect_0_RRESP = M03_AXI_rresp[1:0];\n  assign m03_couplers_to_axi_interconnect_0_RVALID = M03_AXI_rvalid;\n  assign m03_couplers_to_axi_interconnect_0_WREADY = M03_AXI_wready;\n  m00_couplers_imp_1QBJ6U2 m00_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m00_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m00_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m00_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m00_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m00_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m00_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m00_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m00_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m00_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m00_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m00_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m00_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m00_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m00_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m00_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m00_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m00_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m00_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m00_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m00_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m00_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m00_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m00_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m00_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m00_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m00_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m00_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m00_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m00_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m00_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m00_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m00_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m00_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m00_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m00_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m00_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m00_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m00_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m00_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m00_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m00_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m00_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m00_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m00_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m00_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m00_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m00_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m00_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m00_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m00_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m00_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m00_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m00_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m00_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m00_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m00_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m00_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m00_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m00_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m00_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m00_couplers_BID),\n        .S_AXI_bready(xbar_to_m00_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m00_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m00_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m00_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m00_couplers_RID),\n        .S_AXI_rlast(xbar_to_m00_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m00_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m00_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m00_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m00_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m00_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m00_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m00_couplers_WVALID));\n  m01_couplers_imp_10IMR9A m01_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m01_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m01_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m01_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m01_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m01_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m01_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m01_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m01_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m01_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m01_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m01_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m01_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m01_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m01_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m01_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m01_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m01_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m01_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m01_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m01_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m01_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m01_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m01_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m01_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m01_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m01_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m01_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m01_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m01_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m01_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m01_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m01_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m01_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m01_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m01_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m01_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m01_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m01_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m01_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m01_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m01_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m01_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m01_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m01_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m01_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m01_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m01_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m01_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m01_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m01_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m01_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m01_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m01_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m01_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m01_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m01_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m01_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m01_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m01_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m01_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m01_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m01_couplers_BID),\n        .S_AXI_bready(xbar_to_m01_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m01_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m01_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m01_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m01_couplers_RID),\n        .S_AXI_rlast(xbar_to_m01_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m01_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m01_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m01_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m01_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m01_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m01_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m01_couplers_WVALID));\n  m02_couplers_imp_APDUS2 m02_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m02_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m02_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m02_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m02_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m02_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m02_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m02_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m02_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m02_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m02_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m02_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m02_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m02_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m02_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m02_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m02_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m02_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m02_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m02_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m02_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m02_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m02_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m02_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m02_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m02_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m02_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m02_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m02_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m02_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m02_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m02_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m02_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m02_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m02_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m02_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m02_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m02_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m02_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m02_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m02_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m02_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m02_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m02_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m02_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m02_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m02_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m02_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m02_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m02_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m02_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m02_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m02_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m02_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m02_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m02_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m02_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m02_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m02_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m02_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m02_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m02_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m02_couplers_BID),\n        .S_AXI_bready(xbar_to_m02_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m02_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m02_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m02_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m02_couplers_RID),\n        .S_AXI_rlast(xbar_to_m02_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m02_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m02_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m02_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m02_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m02_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m02_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m02_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m02_couplers_WVALID));\n  m03_couplers_imp_JAYOMU m03_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m03_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m03_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m03_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m03_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m03_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m03_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m03_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m03_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m03_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m03_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m03_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m03_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m03_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m03_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m03_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m03_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m03_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m03_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m03_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m03_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m03_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m03_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m03_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m03_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m03_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m03_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m03_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m03_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m03_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m03_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m03_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m03_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m03_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m03_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m03_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m03_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m03_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m03_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m03_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m03_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m03_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m03_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m03_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m03_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m03_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m03_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m03_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m03_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m03_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m03_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m03_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m03_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m03_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m03_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m03_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m03_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m03_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m03_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m03_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m03_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m03_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m03_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m03_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m03_couplers_BID),\n        .S_AXI_bready(xbar_to_m03_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m03_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m03_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m03_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m03_couplers_RID),\n        .S_AXI_rlast(xbar_to_m03_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m03_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m03_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m03_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m03_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m03_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m03_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m03_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m03_couplers_WVALID));\n  s00_couplers_imp_QICM5G s00_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(s00_couplers_to_xbar_ARADDR),\n        .M_AXI_arburst(s00_couplers_to_xbar_ARBURST),\n        .M_AXI_arcache(s00_couplers_to_xbar_ARCACHE),\n        .M_AXI_arid(s00_couplers_to_xbar_ARID),\n        .M_AXI_arlen(s00_couplers_to_xbar_ARLEN),\n        .M_AXI_arlock(s00_couplers_to_xbar_ARLOCK),\n        .M_AXI_arprot(s00_couplers_to_xbar_ARPROT),\n        .M_AXI_arqos(s00_couplers_to_xbar_ARQOS),\n        .M_AXI_arready(s00_couplers_to_xbar_ARREADY),\n        .M_AXI_arsize(s00_couplers_to_xbar_ARSIZE),\n        .M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),\n        .M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),\n        .M_AXI_awburst(s00_couplers_to_xbar_AWBURST),\n        .M_AXI_awcache(s00_couplers_to_xbar_AWCACHE),\n        .M_AXI_awid(s00_couplers_to_xbar_AWID),\n        .M_AXI_awlen(s00_couplers_to_xbar_AWLEN),\n        .M_AXI_awlock(s00_couplers_to_xbar_AWLOCK),\n        .M_AXI_awprot(s00_couplers_to_xbar_AWPROT),\n        .M_AXI_awqos(s00_couplers_to_xbar_AWQOS),\n        .M_AXI_awready(s00_couplers_to_xbar_AWREADY),\n        .M_AXI_awsize(s00_couplers_to_xbar_AWSIZE),\n        .M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),\n        .M_AXI_bid(s00_couplers_to_xbar_BID),\n        .M_AXI_bready(s00_couplers_to_xbar_BREADY),\n        .M_AXI_bresp(s00_couplers_to_xbar_BRESP),\n        .M_AXI_bvalid(s00_couplers_to_xbar_BVALID),\n        .M_AXI_rdata(s00_couplers_to_xbar_RDATA),\n        .M_AXI_rid(s00_couplers_to_xbar_RID),\n        .M_AXI_rlast(s00_couplers_to_xbar_RLAST),\n        .M_AXI_rready(s00_couplers_to_xbar_RREADY),\n        .M_AXI_rresp(s00_couplers_to_xbar_RRESP),\n        .M_AXI_rvalid(s00_couplers_to_xbar_RVALID),\n        .M_AXI_wdata(s00_couplers_to_xbar_WDATA),\n        .M_AXI_wlast(s00_couplers_to_xbar_WLAST),\n        .M_AXI_wready(s00_couplers_to_xbar_WREADY),\n        .M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),\n        .M_AXI_wvalid(s00_couplers_to_xbar_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(axi_interconnect_0_to_s00_couplers_ARADDR),\n        .S_AXI_arburst(axi_interconnect_0_to_s00_couplers_ARBURST),\n        .S_AXI_arcache(axi_interconnect_0_to_s00_couplers_ARCACHE),\n        .S_AXI_arid(axi_interconnect_0_to_s00_couplers_ARID),\n        .S_AXI_arlen(axi_interconnect_0_to_s00_couplers_ARLEN),\n        .S_AXI_arlock(axi_interconnect_0_to_s00_couplers_ARLOCK),\n        .S_AXI_arprot(axi_interconnect_0_to_s00_couplers_ARPROT),\n        .S_AXI_arqos(axi_interconnect_0_to_s00_couplers_ARQOS),\n        .S_AXI_arready(axi_interconnect_0_to_s00_couplers_ARREADY),\n        .S_AXI_arregion(axi_interconnect_0_to_s00_couplers_ARREGION),\n        .S_AXI_arsize(axi_interconnect_0_to_s00_couplers_ARSIZE),\n        .S_AXI_arvalid(axi_interconnect_0_to_s00_couplers_ARVALID),\n        .S_AXI_awaddr(axi_interconnect_0_to_s00_couplers_AWADDR),\n        .S_AXI_awburst(axi_interconnect_0_to_s00_couplers_AWBURST),\n        .S_AXI_awcache(axi_interconnect_0_to_s00_couplers_AWCACHE),\n        .S_AXI_awid(axi_interconnect_0_to_s00_couplers_AWID),\n        .S_AXI_awlen(axi_interconnect_0_to_s00_couplers_AWLEN),\n        .S_AXI_awlock(axi_interconnect_0_to_s00_couplers_AWLOCK),\n        .S_AXI_awprot(axi_interconnect_0_to_s00_couplers_AWPROT),\n        .S_AXI_awqos(axi_interconnect_0_to_s00_couplers_AWQOS),\n        .S_AXI_awready(axi_interconnect_0_to_s00_couplers_AWREADY),\n        .S_AXI_awregion(axi_interconnect_0_to_s00_couplers_AWREGION),\n        .S_AXI_awsize(axi_interconnect_0_to_s00_couplers_AWSIZE),\n        .S_AXI_awvalid(axi_interconnect_0_to_s00_couplers_AWVALID),\n        .S_AXI_bid(axi_interconnect_0_to_s00_couplers_BID),\n        .S_AXI_bready(axi_interconnect_0_to_s00_couplers_BREADY),\n        .S_AXI_bresp(axi_interconnect_0_to_s00_couplers_BRESP),\n        .S_AXI_bvalid(axi_interconnect_0_to_s00_couplers_BVALID),\n        .S_AXI_rdata(axi_interconnect_0_to_s00_couplers_RDATA),\n        .S_AXI_rid(axi_interconnect_0_to_s00_couplers_RID),\n        .S_AXI_rlast(axi_interconnect_0_to_s00_couplers_RLAST),\n        .S_AXI_rready(axi_interconnect_0_to_s00_couplers_RREADY),\n        .S_AXI_rresp(axi_interconnect_0_to_s00_couplers_RRESP),\n        .S_AXI_rvalid(axi_interconnect_0_to_s00_couplers_RVALID),\n        .S_AXI_wdata(axi_interconnect_0_to_s00_couplers_WDATA),\n        .S_AXI_wlast(axi_interconnect_0_to_s00_couplers_WLAST),\n        .S_AXI_wready(axi_interconnect_0_to_s00_couplers_WREADY),\n        .S_AXI_wstrb(axi_interconnect_0_to_s00_couplers_WSTRB),\n        .S_AXI_wvalid(axi_interconnect_0_to_s00_couplers_WVALID));\n  s01_couplers_imp_GSTXQ8 s01_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(s01_couplers_to_xbar_ARADDR),\n        .M_AXI_arburst(s01_couplers_to_xbar_ARBURST),\n        .M_AXI_arcache(s01_couplers_to_xbar_ARCACHE),\n        .M_AXI_arid(s01_couplers_to_xbar_ARID),\n        .M_AXI_arlen(s01_couplers_to_xbar_ARLEN),\n        .M_AXI_arlock(s01_couplers_to_xbar_ARLOCK),\n        .M_AXI_arprot(s01_couplers_to_xbar_ARPROT),\n        .M_AXI_arqos(s01_couplers_to_xbar_ARQOS),\n        .M_AXI_arready(s01_couplers_to_xbar_ARREADY),\n        .M_AXI_arsize(s01_couplers_to_xbar_ARSIZE),\n        .M_AXI_arvalid(s01_couplers_to_xbar_ARVALID),\n        .M_AXI_awaddr(s01_couplers_to_xbar_AWADDR),\n        .M_AXI_awburst(s01_couplers_to_xbar_AWBURST),\n        .M_AXI_awcache(s01_couplers_to_xbar_AWCACHE),\n        .M_AXI_awid(s01_couplers_to_xbar_AWID),\n        .M_AXI_awlen(s01_couplers_to_xbar_AWLEN),\n        .M_AXI_awlock(s01_couplers_to_xbar_AWLOCK),\n        .M_AXI_awprot(s01_couplers_to_xbar_AWPROT),\n        .M_AXI_awqos(s01_couplers_to_xbar_AWQOS),\n        .M_AXI_awready(s01_couplers_to_xbar_AWREADY),\n        .M_AXI_awsize(s01_couplers_to_xbar_AWSIZE),\n        .M_AXI_awvalid(s01_couplers_to_xbar_AWVALID),\n        .M_AXI_bid(s01_couplers_to_xbar_BID),\n        .M_AXI_bready(s01_couplers_to_xbar_BREADY),\n        .M_AXI_bresp(s01_couplers_to_xbar_BRESP),\n        .M_AXI_bvalid(s01_couplers_to_xbar_BVALID),\n        .M_AXI_rdata(s01_couplers_to_xbar_RDATA),\n        .M_AXI_rid(s01_couplers_to_xbar_RID),\n        .M_AXI_rlast(s01_couplers_to_xbar_RLAST),\n        .M_AXI_rready(s01_couplers_to_xbar_RREADY),\n        .M_AXI_rresp(s01_couplers_to_xbar_RRESP),\n        .M_AXI_rvalid(s01_couplers_to_xbar_RVALID),\n        .M_AXI_wdata(s01_couplers_to_xbar_WDATA),\n        .M_AXI_wlast(s01_couplers_to_xbar_WLAST),\n        .M_AXI_wready(s01_couplers_to_xbar_WREADY),\n        .M_AXI_wstrb(s01_couplers_to_xbar_WSTRB),\n        .M_AXI_wvalid(s01_couplers_to_xbar_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(axi_interconnect_0_to_s01_couplers_ARADDR),\n        .S_AXI_arburst(axi_interconnect_0_to_s01_couplers_ARBURST),\n        .S_AXI_arcache(axi_interconnect_0_to_s01_couplers_ARCACHE),\n        .S_AXI_arid(axi_interconnect_0_to_s01_couplers_ARID),\n        .S_AXI_arlen(axi_interconnect_0_to_s01_couplers_ARLEN),\n        .S_AXI_arlock(axi_interconnect_0_to_s01_couplers_ARLOCK),\n        .S_AXI_arprot(axi_interconnect_0_to_s01_couplers_ARPROT),\n        .S_AXI_arqos(axi_interconnect_0_to_s01_couplers_ARQOS),\n        .S_AXI_arready(axi_interconnect_0_to_s01_couplers_ARREADY),\n        .S_AXI_arregion(axi_interconnect_0_to_s01_couplers_ARREGION),\n        .S_AXI_arsize(axi_interconnect_0_to_s01_couplers_ARSIZE),\n        .S_AXI_arvalid(axi_interconnect_0_to_s01_couplers_ARVALID),\n        .S_AXI_awaddr(axi_interconnect_0_to_s01_couplers_AWADDR),\n        .S_AXI_awburst(axi_interconnect_0_to_s01_couplers_AWBURST),\n        .S_AXI_awcache(axi_interconnect_0_to_s01_couplers_AWCACHE),\n        .S_AXI_awid(axi_interconnect_0_to_s01_couplers_AWID),\n        .S_AXI_awlen(axi_interconnect_0_to_s01_couplers_AWLEN),\n        .S_AXI_awlock(axi_interconnect_0_to_s01_couplers_AWLOCK),\n        .S_AXI_awprot(axi_interconnect_0_to_s01_couplers_AWPROT),\n        .S_AXI_awqos(axi_interconnect_0_to_s01_couplers_AWQOS),\n        .S_AXI_awready(axi_interconnect_0_to_s01_couplers_AWREADY),\n        .S_AXI_awregion(axi_interconnect_0_to_s01_couplers_AWREGION),\n        .S_AXI_awsize(axi_interconnect_0_to_s01_couplers_AWSIZE),\n        .S_AXI_awvalid(axi_interconnect_0_to_s01_couplers_AWVALID),\n        .S_AXI_bid(axi_interconnect_0_to_s01_couplers_BID),\n        .S_AXI_bready(axi_interconnect_0_to_s01_couplers_BREADY),\n        .S_AXI_bresp(axi_interconnect_0_to_s01_couplers_BRESP),\n        .S_AXI_bvalid(axi_interconnect_0_to_s01_couplers_BVALID),\n        .S_AXI_rdata(axi_interconnect_0_to_s01_couplers_RDATA),\n        .S_AXI_rid(axi_interconnect_0_to_s01_couplers_RID),\n        .S_AXI_rlast(axi_interconnect_0_to_s01_couplers_RLAST),\n        .S_AXI_rready(axi_interconnect_0_to_s01_couplers_RREADY),\n        .S_AXI_rresp(axi_interconnect_0_to_s01_couplers_RRESP),\n        .S_AXI_rvalid(axi_interconnect_0_to_s01_couplers_RVALID),\n        .S_AXI_wdata(axi_interconnect_0_to_s01_couplers_WDATA),\n        .S_AXI_wlast(axi_interconnect_0_to_s01_couplers_WLAST),\n        .S_AXI_wready(axi_interconnect_0_to_s01_couplers_WREADY),\n        .S_AXI_wstrb(axi_interconnect_0_to_s01_couplers_WSTRB),\n        .S_AXI_wvalid(axi_interconnect_0_to_s01_couplers_WVALID));\n  cl_axi_interconnect_xbar_0 xbar\n       (.aclk(axi_interconnect_0_ACLK_net),\n        .aresetn(axi_interconnect_0_ARESETN_net),\n        .m_axi_araddr({xbar_to_m03_couplers_ARADDR,xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),\n        .m_axi_arburst({xbar_to_m03_couplers_ARBURST,xbar_to_m02_couplers_ARBURST,xbar_to_m01_couplers_ARBURST,xbar_to_m00_couplers_ARBURST}),\n        .m_axi_arcache({xbar_to_m03_couplers_ARCACHE,xbar_to_m02_couplers_ARCACHE,xbar_to_m01_couplers_ARCACHE,xbar_to_m00_couplers_ARCACHE}),\n        .m_axi_arid({xbar_to_m03_couplers_ARID,xbar_to_m02_couplers_ARID,xbar_to_m01_couplers_ARID,xbar_to_m00_couplers_ARID}),\n        .m_axi_arlen({xbar_to_m03_couplers_ARLEN,xbar_to_m02_couplers_ARLEN,xbar_to_m01_couplers_ARLEN,xbar_to_m00_couplers_ARLEN}),\n        .m_axi_arlock({xbar_to_m03_couplers_ARLOCK,xbar_to_m02_couplers_ARLOCK,xbar_to_m01_couplers_ARLOCK,xbar_to_m00_couplers_ARLOCK}),\n        .m_axi_arprot({xbar_to_m03_couplers_ARPROT,xbar_to_m02_couplers_ARPROT,xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}),\n        .m_axi_arqos({xbar_to_m03_couplers_ARQOS,xbar_to_m02_couplers_ARQOS,xbar_to_m01_couplers_ARQOS,xbar_to_m00_couplers_ARQOS}),\n        .m_axi_arready({xbar_to_m03_couplers_ARREADY,xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),\n        .m_axi_arregion({xbar_to_m03_couplers_ARREGION,xbar_to_m02_couplers_ARREGION,xbar_to_m01_couplers_ARREGION,xbar_to_m00_couplers_ARREGION}),\n        .m_axi_arsize({xbar_to_m03_couplers_ARSIZE,xbar_to_m02_couplers_ARSIZE,xbar_to_m01_couplers_ARSIZE,xbar_to_m00_couplers_ARSIZE}),\n        .m_axi_arvalid({xbar_to_m03_couplers_ARVALID,xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),\n        .m_axi_awaddr({xbar_to_m03_couplers_AWADDR,xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),\n        .m_axi_awburst({xbar_to_m03_couplers_AWBURST,xbar_to_m02_couplers_AWBURST,xbar_to_m01_couplers_AWBURST,xbar_to_m00_couplers_AWBURST}),\n        .m_axi_awcache({xbar_to_m03_couplers_AWCACHE,xbar_to_m02_couplers_AWCACHE,xbar_to_m01_couplers_AWCACHE,xbar_to_m00_couplers_AWCACHE}),\n        .m_axi_awid({xbar_to_m03_couplers_AWID,xbar_to_m02_couplers_AWID,xbar_to_m01_couplers_AWID,xbar_to_m00_couplers_AWID}),\n        .m_axi_awlen({xbar_to_m03_couplers_AWLEN,xbar_to_m02_couplers_AWLEN,xbar_to_m01_couplers_AWLEN,xbar_to_m00_couplers_AWLEN}),\n        .m_axi_awlock({xbar_to_m03_couplers_AWLOCK,xbar_to_m02_couplers_AWLOCK,xbar_to_m01_couplers_AWLOCK,xbar_to_m00_couplers_AWLOCK}),\n        .m_axi_awprot({xbar_to_m03_couplers_AWPROT,xbar_to_m02_couplers_AWPROT,xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}),\n        .m_axi_awqos({xbar_to_m03_couplers_AWQOS,xbar_to_m02_couplers_AWQOS,xbar_to_m01_couplers_AWQOS,xbar_to_m00_couplers_AWQOS}),\n        .m_axi_awready({xbar_to_m03_couplers_AWREADY,xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),\n        .m_axi_awregion({xbar_to_m03_couplers_AWREGION,xbar_to_m02_couplers_AWREGION,xbar_to_m01_couplers_AWREGION,xbar_to_m00_couplers_AWREGION}),\n        .m_axi_awsize({xbar_to_m03_couplers_AWSIZE,xbar_to_m02_couplers_AWSIZE,xbar_to_m01_couplers_AWSIZE,xbar_to_m00_couplers_AWSIZE}),\n        .m_axi_awvalid({xbar_to_m03_couplers_AWVALID,xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),\n        .m_axi_bid({xbar_to_m03_couplers_BID,xbar_to_m02_couplers_BID,xbar_to_m01_couplers_BID,xbar_to_m00_couplers_BID}),\n        .m_axi_bready({xbar_to_m03_couplers_BREADY,xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),\n        .m_axi_bresp({xbar_to_m03_couplers_BRESP,xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),\n        .m_axi_bvalid({xbar_to_m03_couplers_BVALID,xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),\n        .m_axi_rdata({xbar_to_m03_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),\n        .m_axi_rid({xbar_to_m03_couplers_RID,xbar_to_m02_couplers_RID,xbar_to_m01_couplers_RID,xbar_to_m00_couplers_RID}),\n        .m_axi_rlast({xbar_to_m03_couplers_RLAST,xbar_to_m02_couplers_RLAST,xbar_to_m01_couplers_RLAST,xbar_to_m00_couplers_RLAST}),\n        .m_axi_rready({xbar_to_m03_couplers_RREADY,xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),\n        .m_axi_rresp({xbar_to_m03_couplers_RRESP,xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),\n        .m_axi_rvalid({xbar_to_m03_couplers_RVALID,xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),\n        .m_axi_wdata({xbar_to_m03_couplers_WDATA,xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),\n        .m_axi_wlast({xbar_to_m03_couplers_WLAST,xbar_to_m02_couplers_WLAST,xbar_to_m01_couplers_WLAST,xbar_to_m00_couplers_WLAST}),\n        .m_axi_wready({xbar_to_m03_couplers_WREADY,xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),\n        .m_axi_wstrb({xbar_to_m03_couplers_WSTRB,xbar_to_m02_couplers_WSTRB,xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),\n        .m_axi_wvalid({xbar_to_m03_couplers_WVALID,xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),\n        .s_axi_araddr({s01_couplers_to_xbar_ARADDR,s00_couplers_to_xbar_ARADDR}),\n        .s_axi_arburst({s01_couplers_to_xbar_ARBURST,s00_couplers_to_xbar_ARBURST}),\n        .s_axi_arcache({s01_couplers_to_xbar_ARCACHE,s00_couplers_to_xbar_ARCACHE}),\n        .s_axi_arid({1'b0,s01_couplers_to_xbar_ARID,1'b0,s00_couplers_to_xbar_ARID}),\n        .s_axi_arlen({s01_couplers_to_xbar_ARLEN,s00_couplers_to_xbar_ARLEN}),\n        .s_axi_arlock({s01_couplers_to_xbar_ARLOCK,s00_couplers_to_xbar_ARLOCK}),\n        .s_axi_arprot({s01_couplers_to_xbar_ARPROT,s00_couplers_to_xbar_ARPROT}),\n        .s_axi_arqos({s01_couplers_to_xbar_ARQOS,s00_couplers_to_xbar_ARQOS}),\n        .s_axi_arready({s01_couplers_to_xbar_ARREADY,s00_couplers_to_xbar_ARREADY}),\n        .s_axi_arsize({s01_couplers_to_xbar_ARSIZE,s00_couplers_to_xbar_ARSIZE}),\n        .s_axi_arvalid({s01_couplers_to_xbar_ARVALID,s00_couplers_to_xbar_ARVALID}),\n        .s_axi_awaddr({s01_couplers_to_xbar_AWADDR,s00_couplers_to_xbar_AWADDR}),\n        .s_axi_awburst({s01_couplers_to_xbar_AWBURST,s00_couplers_to_xbar_AWBURST}),\n        .s_axi_awcache({s01_couplers_to_xbar_AWCACHE,s00_couplers_to_xbar_AWCACHE}),\n        .s_axi_awid({1'b0,s01_couplers_to_xbar_AWID,1'b0,s00_couplers_to_xbar_AWID}),\n        .s_axi_awlen({s01_couplers_to_xbar_AWLEN,s00_couplers_to_xbar_AWLEN}),\n        .s_axi_awlock({s01_couplers_to_xbar_AWLOCK,s00_couplers_to_xbar_AWLOCK}),\n        .s_axi_awprot({s01_couplers_to_xbar_AWPROT,s00_couplers_to_xbar_AWPROT}),\n        .s_axi_awqos({s01_couplers_to_xbar_AWQOS,s00_couplers_to_xbar_AWQOS}),\n        .s_axi_awready({s01_couplers_to_xbar_AWREADY,s00_couplers_to_xbar_AWREADY}),\n        .s_axi_awsize({s01_couplers_to_xbar_AWSIZE,s00_couplers_to_xbar_AWSIZE}),\n        .s_axi_awvalid({s01_couplers_to_xbar_AWVALID,s00_couplers_to_xbar_AWVALID}),\n        .s_axi_bid({s01_couplers_to_xbar_BID,s00_couplers_to_xbar_BID}),\n        .s_axi_bready({s01_couplers_to_xbar_BREADY,s00_couplers_to_xbar_BREADY}),\n        .s_axi_bresp({s01_couplers_to_xbar_BRESP,s00_couplers_to_xbar_BRESP}),\n        .s_axi_bvalid({s01_couplers_to_xbar_BVALID,s00_couplers_to_xbar_BVALID}),\n        .s_axi_rdata({s01_couplers_to_xbar_RDATA,s00_couplers_to_xbar_RDATA}),\n        .s_axi_rid({s01_couplers_to_xbar_RID,s00_couplers_to_xbar_RID}),\n        .s_axi_rlast({s01_couplers_to_xbar_RLAST,s00_couplers_to_xbar_RLAST}),\n        .s_axi_rready({s01_couplers_to_xbar_RREADY,s00_couplers_to_xbar_RREADY}),\n        .s_axi_rresp({s01_couplers_to_xbar_RRESP,s00_couplers_to_xbar_RRESP}),\n        .s_axi_rvalid({s01_couplers_to_xbar_RVALID,s00_couplers_to_xbar_RVALID}),\n        .s_axi_wdata({s01_couplers_to_xbar_WDATA,s00_couplers_to_xbar_WDATA}),\n        .s_axi_wlast({s01_couplers_to_xbar_WLAST,s00_couplers_to_xbar_WLAST}),\n        .s_axi_wready({s01_couplers_to_xbar_WREADY,s00_couplers_to_xbar_WREADY}),\n        .s_axi_wstrb({s01_couplers_to_xbar_WSTRB,s00_couplers_to_xbar_WSTRB}),\n        .s_axi_wvalid({s01_couplers_to_xbar_WVALID,s00_couplers_to_xbar_WVALID}));\nendmodule\n\nmodule m00_couplers_imp_1QBJ6U2\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m00_couplers_to_m00_regslice_ARADDR;\n  wire [1:0]m00_couplers_to_m00_regslice_ARBURST;\n  wire [3:0]m00_couplers_to_m00_regslice_ARCACHE;\n  wire [6:0]m00_couplers_to_m00_regslice_ARID;\n  wire [7:0]m00_couplers_to_m00_regslice_ARLEN;\n  wire [0:0]m00_couplers_to_m00_regslice_ARLOCK;\n  wire [2:0]m00_couplers_to_m00_regslice_ARPROT;\n  wire [3:0]m00_couplers_to_m00_regslice_ARQOS;\n  wire m00_couplers_to_m00_regslice_ARREADY;\n  wire [3:0]m00_couplers_to_m00_regslice_ARREGION;\n  wire [2:0]m00_couplers_to_m00_regslice_ARSIZE;\n  wire m00_couplers_to_m00_regslice_ARVALID;\n  wire [63:0]m00_couplers_to_m00_regslice_AWADDR;\n  wire [1:0]m00_couplers_to_m00_regslice_AWBURST;\n  wire [3:0]m00_couplers_to_m00_regslice_AWCACHE;\n  wire [6:0]m00_couplers_to_m00_regslice_AWID;\n  wire [7:0]m00_couplers_to_m00_regslice_AWLEN;\n  wire [0:0]m00_couplers_to_m00_regslice_AWLOCK;\n  wire [2:0]m00_couplers_to_m00_regslice_AWPROT;\n  wire [3:0]m00_couplers_to_m00_regslice_AWQOS;\n  wire m00_couplers_to_m00_regslice_AWREADY;\n  wire [3:0]m00_couplers_to_m00_regslice_AWREGION;\n  wire [2:0]m00_couplers_to_m00_regslice_AWSIZE;\n  wire m00_couplers_to_m00_regslice_AWVALID;\n  wire [6:0]m00_couplers_to_m00_regslice_BID;\n  wire m00_couplers_to_m00_regslice_BREADY;\n  wire [1:0]m00_couplers_to_m00_regslice_BRESP;\n  wire m00_couplers_to_m00_regslice_BVALID;\n  wire [511:0]m00_couplers_to_m00_regslice_RDATA;\n  wire [6:0]m00_couplers_to_m00_regslice_RID;\n  wire m00_couplers_to_m00_regslice_RLAST;\n  wire m00_couplers_to_m00_regslice_RREADY;\n  wire [1:0]m00_couplers_to_m00_regslice_RRESP;\n  wire m00_couplers_to_m00_regslice_RVALID;\n  wire [511:0]m00_couplers_to_m00_regslice_WDATA;\n  wire m00_couplers_to_m00_regslice_WLAST;\n  wire m00_couplers_to_m00_regslice_WREADY;\n  wire [63:0]m00_couplers_to_m00_regslice_WSTRB;\n  wire m00_couplers_to_m00_regslice_WVALID;\n  wire [63:0]m00_regslice_to_m00_couplers_ARADDR;\n  wire [1:0]m00_regslice_to_m00_couplers_ARBURST;\n  wire [3:0]m00_regslice_to_m00_couplers_ARCACHE;\n  wire [6:0]m00_regslice_to_m00_couplers_ARID;\n  wire [7:0]m00_regslice_to_m00_couplers_ARLEN;\n  wire [0:0]m00_regslice_to_m00_couplers_ARLOCK;\n  wire [2:0]m00_regslice_to_m00_couplers_ARPROT;\n  wire [3:0]m00_regslice_to_m00_couplers_ARQOS;\n  wire m00_regslice_to_m00_couplers_ARREADY;\n  wire [3:0]m00_regslice_to_m00_couplers_ARREGION;\n  wire [2:0]m00_regslice_to_m00_couplers_ARSIZE;\n  wire m00_regslice_to_m00_couplers_ARVALID;\n  wire [63:0]m00_regslice_to_m00_couplers_AWADDR;\n  wire [1:0]m00_regslice_to_m00_couplers_AWBURST;\n  wire [3:0]m00_regslice_to_m00_couplers_AWCACHE;\n  wire [6:0]m00_regslice_to_m00_couplers_AWID;\n  wire [7:0]m00_regslice_to_m00_couplers_AWLEN;\n  wire [0:0]m00_regslice_to_m00_couplers_AWLOCK;\n  wire [2:0]m00_regslice_to_m00_couplers_AWPROT;\n  wire [3:0]m00_regslice_to_m00_couplers_AWQOS;\n  wire m00_regslice_to_m00_couplers_AWREADY;\n  wire [3:0]m00_regslice_to_m00_couplers_AWREGION;\n  wire [2:0]m00_regslice_to_m00_couplers_AWSIZE;\n  wire m00_regslice_to_m00_couplers_AWVALID;\n  wire [6:0]m00_regslice_to_m00_couplers_BID;\n  wire m00_regslice_to_m00_couplers_BREADY;\n  wire [1:0]m00_regslice_to_m00_couplers_BRESP;\n  wire m00_regslice_to_m00_couplers_BVALID;\n  wire [511:0]m00_regslice_to_m00_couplers_RDATA;\n  wire [6:0]m00_regslice_to_m00_couplers_RID;\n  wire m00_regslice_to_m00_couplers_RLAST;\n  wire m00_regslice_to_m00_couplers_RREADY;\n  wire [1:0]m00_regslice_to_m00_couplers_RRESP;\n  wire m00_regslice_to_m00_couplers_RVALID;\n  wire [511:0]m00_regslice_to_m00_couplers_WDATA;\n  wire m00_regslice_to_m00_couplers_WLAST;\n  wire m00_regslice_to_m00_couplers_WREADY;\n  wire [63:0]m00_regslice_to_m00_couplers_WSTRB;\n  wire m00_regslice_to_m00_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m00_regslice_to_m00_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m00_regslice_to_m00_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m00_regslice_to_m00_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m00_regslice_to_m00_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m00_regslice_to_m00_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m00_regslice_to_m00_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m00_regslice_to_m00_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m00_regslice_to_m00_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m00_regslice_to_m00_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m00_regslice_to_m00_couplers_ARSIZE;\n  assign M_AXI_arvalid = m00_regslice_to_m00_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m00_regslice_to_m00_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m00_regslice_to_m00_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m00_regslice_to_m00_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m00_regslice_to_m00_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m00_regslice_to_m00_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m00_regslice_to_m00_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m00_regslice_to_m00_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m00_regslice_to_m00_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m00_regslice_to_m00_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m00_regslice_to_m00_couplers_AWSIZE;\n  assign M_AXI_awvalid = m00_regslice_to_m00_couplers_AWVALID;\n  assign M_AXI_bready = m00_regslice_to_m00_couplers_BREADY;\n  assign M_AXI_rready = m00_regslice_to_m00_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m00_regslice_to_m00_couplers_WDATA;\n  assign M_AXI_wlast = m00_regslice_to_m00_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m00_regslice_to_m00_couplers_WSTRB;\n  assign M_AXI_wvalid = m00_regslice_to_m00_couplers_WVALID;\n  assign S_AXI_arready = m00_couplers_to_m00_regslice_ARREADY;\n  assign S_AXI_awready = m00_couplers_to_m00_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m00_couplers_to_m00_regslice_BID;\n  assign S_AXI_bresp[1:0] = m00_couplers_to_m00_regslice_BRESP;\n  assign S_AXI_bvalid = m00_couplers_to_m00_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m00_couplers_to_m00_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m00_couplers_to_m00_regslice_RID;\n  assign S_AXI_rlast = m00_couplers_to_m00_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m00_couplers_to_m00_regslice_RRESP;\n  assign S_AXI_rvalid = m00_couplers_to_m00_regslice_RVALID;\n  assign S_AXI_wready = m00_couplers_to_m00_regslice_WREADY;\n  assign m00_couplers_to_m00_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m00_couplers_to_m00_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m00_couplers_to_m00_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m00_couplers_to_m00_regslice_ARID = S_AXI_arid[6:0];\n  assign m00_couplers_to_m00_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m00_couplers_to_m00_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m00_couplers_to_m00_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m00_couplers_to_m00_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m00_couplers_to_m00_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m00_couplers_to_m00_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m00_couplers_to_m00_regslice_ARVALID = S_AXI_arvalid;\n  assign m00_couplers_to_m00_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m00_couplers_to_m00_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m00_couplers_to_m00_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m00_couplers_to_m00_regslice_AWID = S_AXI_awid[6:0];\n  assign m00_couplers_to_m00_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m00_couplers_to_m00_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m00_couplers_to_m00_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m00_couplers_to_m00_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m00_couplers_to_m00_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m00_couplers_to_m00_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m00_couplers_to_m00_regslice_AWVALID = S_AXI_awvalid;\n  assign m00_couplers_to_m00_regslice_BREADY = S_AXI_bready;\n  assign m00_couplers_to_m00_regslice_RREADY = S_AXI_rready;\n  assign m00_couplers_to_m00_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m00_couplers_to_m00_regslice_WLAST = S_AXI_wlast;\n  assign m00_couplers_to_m00_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m00_couplers_to_m00_regslice_WVALID = S_AXI_wvalid;\n  assign m00_regslice_to_m00_couplers_ARREADY = M_AXI_arready;\n  assign m00_regslice_to_m00_couplers_AWREADY = M_AXI_awready;\n  assign m00_regslice_to_m00_couplers_BID = M_AXI_bid[6:0];\n  assign m00_regslice_to_m00_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m00_regslice_to_m00_couplers_BVALID = M_AXI_bvalid;\n  assign m00_regslice_to_m00_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m00_regslice_to_m00_couplers_RID = M_AXI_rid[6:0];\n  assign m00_regslice_to_m00_couplers_RLAST = M_AXI_rlast;\n  assign m00_regslice_to_m00_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m00_regslice_to_m00_couplers_RVALID = M_AXI_rvalid;\n  assign m00_regslice_to_m00_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m00_regslice_0 m00_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m00_regslice_to_m00_couplers_ARADDR),\n        .m_axi_arburst(m00_regslice_to_m00_couplers_ARBURST),\n        .m_axi_arcache(m00_regslice_to_m00_couplers_ARCACHE),\n        .m_axi_arid(m00_regslice_to_m00_couplers_ARID),\n        .m_axi_arlen(m00_regslice_to_m00_couplers_ARLEN),\n        .m_axi_arlock(m00_regslice_to_m00_couplers_ARLOCK),\n        .m_axi_arprot(m00_regslice_to_m00_couplers_ARPROT),\n        .m_axi_arqos(m00_regslice_to_m00_couplers_ARQOS),\n        .m_axi_arready(m00_regslice_to_m00_couplers_ARREADY),\n        .m_axi_arregion(m00_regslice_to_m00_couplers_ARREGION),\n        .m_axi_arsize(m00_regslice_to_m00_couplers_ARSIZE),\n        .m_axi_arvalid(m00_regslice_to_m00_couplers_ARVALID),\n        .m_axi_awaddr(m00_regslice_to_m00_couplers_AWADDR),\n        .m_axi_awburst(m00_regslice_to_m00_couplers_AWBURST),\n        .m_axi_awcache(m00_regslice_to_m00_couplers_AWCACHE),\n        .m_axi_awid(m00_regslice_to_m00_couplers_AWID),\n        .m_axi_awlen(m00_regslice_to_m00_couplers_AWLEN),\n        .m_axi_awlock(m00_regslice_to_m00_couplers_AWLOCK),\n        .m_axi_awprot(m00_regslice_to_m00_couplers_AWPROT),\n        .m_axi_awqos(m00_regslice_to_m00_couplers_AWQOS),\n        .m_axi_awready(m00_regslice_to_m00_couplers_AWREADY),\n        .m_axi_awregion(m00_regslice_to_m00_couplers_AWREGION),\n        .m_axi_awsize(m00_regslice_to_m00_couplers_AWSIZE),\n        .m_axi_awvalid(m00_regslice_to_m00_couplers_AWVALID),\n        .m_axi_bid(m00_regslice_to_m00_couplers_BID),\n        .m_axi_bready(m00_regslice_to_m00_couplers_BREADY),\n        .m_axi_bresp(m00_regslice_to_m00_couplers_BRESP),\n        .m_axi_bvalid(m00_regslice_to_m00_couplers_BVALID),\n        .m_axi_rdata(m00_regslice_to_m00_couplers_RDATA),\n        .m_axi_rid(m00_regslice_to_m00_couplers_RID),\n        .m_axi_rlast(m00_regslice_to_m00_couplers_RLAST),\n        .m_axi_rready(m00_regslice_to_m00_couplers_RREADY),\n        .m_axi_rresp(m00_regslice_to_m00_couplers_RRESP),\n        .m_axi_rvalid(m00_regslice_to_m00_couplers_RVALID),\n        .m_axi_wdata(m00_regslice_to_m00_couplers_WDATA),\n        .m_axi_wlast(m00_regslice_to_m00_couplers_WLAST),\n        .m_axi_wready(m00_regslice_to_m00_couplers_WREADY),\n        .m_axi_wstrb(m00_regslice_to_m00_couplers_WSTRB),\n        .m_axi_wvalid(m00_regslice_to_m00_couplers_WVALID),\n        .s_axi_araddr(m00_couplers_to_m00_regslice_ARADDR),\n        .s_axi_arburst(m00_couplers_to_m00_regslice_ARBURST),\n        .s_axi_arcache(m00_couplers_to_m00_regslice_ARCACHE),\n        .s_axi_arid(m00_couplers_to_m00_regslice_ARID),\n        .s_axi_arlen(m00_couplers_to_m00_regslice_ARLEN),\n        .s_axi_arlock(m00_couplers_to_m00_regslice_ARLOCK),\n        .s_axi_arprot(m00_couplers_to_m00_regslice_ARPROT),\n        .s_axi_arqos(m00_couplers_to_m00_regslice_ARQOS),\n        .s_axi_arready(m00_couplers_to_m00_regslice_ARREADY),\n        .s_axi_arregion(m00_couplers_to_m00_regslice_ARREGION),\n        .s_axi_arsize(m00_couplers_to_m00_regslice_ARSIZE),\n        .s_axi_arvalid(m00_couplers_to_m00_regslice_ARVALID),\n        .s_axi_awaddr(m00_couplers_to_m00_regslice_AWADDR),\n        .s_axi_awburst(m00_couplers_to_m00_regslice_AWBURST),\n        .s_axi_awcache(m00_couplers_to_m00_regslice_AWCACHE),\n        .s_axi_awid(m00_couplers_to_m00_regslice_AWID),\n        .s_axi_awlen(m00_couplers_to_m00_regslice_AWLEN),\n        .s_axi_awlock(m00_couplers_to_m00_regslice_AWLOCK),\n        .s_axi_awprot(m00_couplers_to_m00_regslice_AWPROT),\n        .s_axi_awqos(m00_couplers_to_m00_regslice_AWQOS),\n        .s_axi_awready(m00_couplers_to_m00_regslice_AWREADY),\n        .s_axi_awregion(m00_couplers_to_m00_regslice_AWREGION),\n        .s_axi_awsize(m00_couplers_to_m00_regslice_AWSIZE),\n        .s_axi_awvalid(m00_couplers_to_m00_regslice_AWVALID),\n        .s_axi_bid(m00_couplers_to_m00_regslice_BID),\n        .s_axi_bready(m00_couplers_to_m00_regslice_BREADY),\n        .s_axi_bresp(m00_couplers_to_m00_regslice_BRESP),\n        .s_axi_bvalid(m00_couplers_to_m00_regslice_BVALID),\n        .s_axi_rdata(m00_couplers_to_m00_regslice_RDATA),\n        .s_axi_rid(m00_couplers_to_m00_regslice_RID),\n        .s_axi_rlast(m00_couplers_to_m00_regslice_RLAST),\n        .s_axi_rready(m00_couplers_to_m00_regslice_RREADY),\n        .s_axi_rresp(m00_couplers_to_m00_regslice_RRESP),\n        .s_axi_rvalid(m00_couplers_to_m00_regslice_RVALID),\n        .s_axi_wdata(m00_couplers_to_m00_regslice_WDATA),\n        .s_axi_wlast(m00_couplers_to_m00_regslice_WLAST),\n        .s_axi_wready(m00_couplers_to_m00_regslice_WREADY),\n        .s_axi_wstrb(m00_couplers_to_m00_regslice_WSTRB),\n        .s_axi_wvalid(m00_couplers_to_m00_regslice_WVALID));\nendmodule\n\nmodule m01_couplers_imp_10IMR9A\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m01_couplers_to_m01_regslice_ARADDR;\n  wire [1:0]m01_couplers_to_m01_regslice_ARBURST;\n  wire [3:0]m01_couplers_to_m01_regslice_ARCACHE;\n  wire [6:0]m01_couplers_to_m01_regslice_ARID;\n  wire [7:0]m01_couplers_to_m01_regslice_ARLEN;\n  wire [0:0]m01_couplers_to_m01_regslice_ARLOCK;\n  wire [2:0]m01_couplers_to_m01_regslice_ARPROT;\n  wire [3:0]m01_couplers_to_m01_regslice_ARQOS;\n  wire m01_couplers_to_m01_regslice_ARREADY;\n  wire [3:0]m01_couplers_to_m01_regslice_ARREGION;\n  wire [2:0]m01_couplers_to_m01_regslice_ARSIZE;\n  wire m01_couplers_to_m01_regslice_ARVALID;\n  wire [63:0]m01_couplers_to_m01_regslice_AWADDR;\n  wire [1:0]m01_couplers_to_m01_regslice_AWBURST;\n  wire [3:0]m01_couplers_to_m01_regslice_AWCACHE;\n  wire [6:0]m01_couplers_to_m01_regslice_AWID;\n  wire [7:0]m01_couplers_to_m01_regslice_AWLEN;\n  wire [0:0]m01_couplers_to_m01_regslice_AWLOCK;\n  wire [2:0]m01_couplers_to_m01_regslice_AWPROT;\n  wire [3:0]m01_couplers_to_m01_regslice_AWQOS;\n  wire m01_couplers_to_m01_regslice_AWREADY;\n  wire [3:0]m01_couplers_to_m01_regslice_AWREGION;\n  wire [2:0]m01_couplers_to_m01_regslice_AWSIZE;\n  wire m01_couplers_to_m01_regslice_AWVALID;\n  wire [6:0]m01_couplers_to_m01_regslice_BID;\n  wire m01_couplers_to_m01_regslice_BREADY;\n  wire [1:0]m01_couplers_to_m01_regslice_BRESP;\n  wire m01_couplers_to_m01_regslice_BVALID;\n  wire [511:0]m01_couplers_to_m01_regslice_RDATA;\n  wire [6:0]m01_couplers_to_m01_regslice_RID;\n  wire m01_couplers_to_m01_regslice_RLAST;\n  wire m01_couplers_to_m01_regslice_RREADY;\n  wire [1:0]m01_couplers_to_m01_regslice_RRESP;\n  wire m01_couplers_to_m01_regslice_RVALID;\n  wire [511:0]m01_couplers_to_m01_regslice_WDATA;\n  wire m01_couplers_to_m01_regslice_WLAST;\n  wire m01_couplers_to_m01_regslice_WREADY;\n  wire [63:0]m01_couplers_to_m01_regslice_WSTRB;\n  wire m01_couplers_to_m01_regslice_WVALID;\n  wire [63:0]m01_regslice_to_m01_couplers_ARADDR;\n  wire [1:0]m01_regslice_to_m01_couplers_ARBURST;\n  wire [3:0]m01_regslice_to_m01_couplers_ARCACHE;\n  wire [6:0]m01_regslice_to_m01_couplers_ARID;\n  wire [7:0]m01_regslice_to_m01_couplers_ARLEN;\n  wire [0:0]m01_regslice_to_m01_couplers_ARLOCK;\n  wire [2:0]m01_regslice_to_m01_couplers_ARPROT;\n  wire [3:0]m01_regslice_to_m01_couplers_ARQOS;\n  wire m01_regslice_to_m01_couplers_ARREADY;\n  wire [3:0]m01_regslice_to_m01_couplers_ARREGION;\n  wire [2:0]m01_regslice_to_m01_couplers_ARSIZE;\n  wire m01_regslice_to_m01_couplers_ARVALID;\n  wire [63:0]m01_regslice_to_m01_couplers_AWADDR;\n  wire [1:0]m01_regslice_to_m01_couplers_AWBURST;\n  wire [3:0]m01_regslice_to_m01_couplers_AWCACHE;\n  wire [6:0]m01_regslice_to_m01_couplers_AWID;\n  wire [7:0]m01_regslice_to_m01_couplers_AWLEN;\n  wire [0:0]m01_regslice_to_m01_couplers_AWLOCK;\n  wire [2:0]m01_regslice_to_m01_couplers_AWPROT;\n  wire [3:0]m01_regslice_to_m01_couplers_AWQOS;\n  wire m01_regslice_to_m01_couplers_AWREADY;\n  wire [3:0]m01_regslice_to_m01_couplers_AWREGION;\n  wire [2:0]m01_regslice_to_m01_couplers_AWSIZE;\n  wire m01_regslice_to_m01_couplers_AWVALID;\n  wire [6:0]m01_regslice_to_m01_couplers_BID;\n  wire m01_regslice_to_m01_couplers_BREADY;\n  wire [1:0]m01_regslice_to_m01_couplers_BRESP;\n  wire m01_regslice_to_m01_couplers_BVALID;\n  wire [511:0]m01_regslice_to_m01_couplers_RDATA;\n  wire [6:0]m01_regslice_to_m01_couplers_RID;\n  wire m01_regslice_to_m01_couplers_RLAST;\n  wire m01_regslice_to_m01_couplers_RREADY;\n  wire [1:0]m01_regslice_to_m01_couplers_RRESP;\n  wire m01_regslice_to_m01_couplers_RVALID;\n  wire [511:0]m01_regslice_to_m01_couplers_WDATA;\n  wire m01_regslice_to_m01_couplers_WLAST;\n  wire m01_regslice_to_m01_couplers_WREADY;\n  wire [63:0]m01_regslice_to_m01_couplers_WSTRB;\n  wire m01_regslice_to_m01_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m01_regslice_to_m01_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m01_regslice_to_m01_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m01_regslice_to_m01_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m01_regslice_to_m01_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m01_regslice_to_m01_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m01_regslice_to_m01_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m01_regslice_to_m01_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m01_regslice_to_m01_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m01_regslice_to_m01_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m01_regslice_to_m01_couplers_ARSIZE;\n  assign M_AXI_arvalid = m01_regslice_to_m01_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m01_regslice_to_m01_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m01_regslice_to_m01_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m01_regslice_to_m01_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m01_regslice_to_m01_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m01_regslice_to_m01_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m01_regslice_to_m01_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m01_regslice_to_m01_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m01_regslice_to_m01_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m01_regslice_to_m01_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m01_regslice_to_m01_couplers_AWSIZE;\n  assign M_AXI_awvalid = m01_regslice_to_m01_couplers_AWVALID;\n  assign M_AXI_bready = m01_regslice_to_m01_couplers_BREADY;\n  assign M_AXI_rready = m01_regslice_to_m01_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m01_regslice_to_m01_couplers_WDATA;\n  assign M_AXI_wlast = m01_regslice_to_m01_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m01_regslice_to_m01_couplers_WSTRB;\n  assign M_AXI_wvalid = m01_regslice_to_m01_couplers_WVALID;\n  assign S_AXI_arready = m01_couplers_to_m01_regslice_ARREADY;\n  assign S_AXI_awready = m01_couplers_to_m01_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m01_couplers_to_m01_regslice_BID;\n  assign S_AXI_bresp[1:0] = m01_couplers_to_m01_regslice_BRESP;\n  assign S_AXI_bvalid = m01_couplers_to_m01_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m01_couplers_to_m01_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m01_couplers_to_m01_regslice_RID;\n  assign S_AXI_rlast = m01_couplers_to_m01_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m01_couplers_to_m01_regslice_RRESP;\n  assign S_AXI_rvalid = m01_couplers_to_m01_regslice_RVALID;\n  assign S_AXI_wready = m01_couplers_to_m01_regslice_WREADY;\n  assign m01_couplers_to_m01_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m01_couplers_to_m01_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m01_couplers_to_m01_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m01_couplers_to_m01_regslice_ARID = S_AXI_arid[6:0];\n  assign m01_couplers_to_m01_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m01_couplers_to_m01_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m01_couplers_to_m01_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m01_couplers_to_m01_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m01_couplers_to_m01_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m01_couplers_to_m01_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m01_couplers_to_m01_regslice_ARVALID = S_AXI_arvalid;\n  assign m01_couplers_to_m01_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m01_couplers_to_m01_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m01_couplers_to_m01_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m01_couplers_to_m01_regslice_AWID = S_AXI_awid[6:0];\n  assign m01_couplers_to_m01_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m01_couplers_to_m01_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m01_couplers_to_m01_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m01_couplers_to_m01_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m01_couplers_to_m01_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m01_couplers_to_m01_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m01_couplers_to_m01_regslice_AWVALID = S_AXI_awvalid;\n  assign m01_couplers_to_m01_regslice_BREADY = S_AXI_bready;\n  assign m01_couplers_to_m01_regslice_RREADY = S_AXI_rready;\n  assign m01_couplers_to_m01_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m01_couplers_to_m01_regslice_WLAST = S_AXI_wlast;\n  assign m01_couplers_to_m01_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m01_couplers_to_m01_regslice_WVALID = S_AXI_wvalid;\n  assign m01_regslice_to_m01_couplers_ARREADY = M_AXI_arready;\n  assign m01_regslice_to_m01_couplers_AWREADY = M_AXI_awready;\n  assign m01_regslice_to_m01_couplers_BID = M_AXI_bid[6:0];\n  assign m01_regslice_to_m01_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m01_regslice_to_m01_couplers_BVALID = M_AXI_bvalid;\n  assign m01_regslice_to_m01_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m01_regslice_to_m01_couplers_RID = M_AXI_rid[6:0];\n  assign m01_regslice_to_m01_couplers_RLAST = M_AXI_rlast;\n  assign m01_regslice_to_m01_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m01_regslice_to_m01_couplers_RVALID = M_AXI_rvalid;\n  assign m01_regslice_to_m01_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m01_regslice_0 m01_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m01_regslice_to_m01_couplers_ARADDR),\n        .m_axi_arburst(m01_regslice_to_m01_couplers_ARBURST),\n        .m_axi_arcache(m01_regslice_to_m01_couplers_ARCACHE),\n        .m_axi_arid(m01_regslice_to_m01_couplers_ARID),\n        .m_axi_arlen(m01_regslice_to_m01_couplers_ARLEN),\n        .m_axi_arlock(m01_regslice_to_m01_couplers_ARLOCK),\n        .m_axi_arprot(m01_regslice_to_m01_couplers_ARPROT),\n        .m_axi_arqos(m01_regslice_to_m01_couplers_ARQOS),\n        .m_axi_arready(m01_regslice_to_m01_couplers_ARREADY),\n        .m_axi_arregion(m01_regslice_to_m01_couplers_ARREGION),\n        .m_axi_arsize(m01_regslice_to_m01_couplers_ARSIZE),\n        .m_axi_arvalid(m01_regslice_to_m01_couplers_ARVALID),\n        .m_axi_awaddr(m01_regslice_to_m01_couplers_AWADDR),\n        .m_axi_awburst(m01_regslice_to_m01_couplers_AWBURST),\n        .m_axi_awcache(m01_regslice_to_m01_couplers_AWCACHE),\n        .m_axi_awid(m01_regslice_to_m01_couplers_AWID),\n        .m_axi_awlen(m01_regslice_to_m01_couplers_AWLEN),\n        .m_axi_awlock(m01_regslice_to_m01_couplers_AWLOCK),\n        .m_axi_awprot(m01_regslice_to_m01_couplers_AWPROT),\n        .m_axi_awqos(m01_regslice_to_m01_couplers_AWQOS),\n        .m_axi_awready(m01_regslice_to_m01_couplers_AWREADY),\n        .m_axi_awregion(m01_regslice_to_m01_couplers_AWREGION),\n        .m_axi_awsize(m01_regslice_to_m01_couplers_AWSIZE),\n        .m_axi_awvalid(m01_regslice_to_m01_couplers_AWVALID),\n        .m_axi_bid(m01_regslice_to_m01_couplers_BID),\n        .m_axi_bready(m01_regslice_to_m01_couplers_BREADY),\n        .m_axi_bresp(m01_regslice_to_m01_couplers_BRESP),\n        .m_axi_bvalid(m01_regslice_to_m01_couplers_BVALID),\n        .m_axi_rdata(m01_regslice_to_m01_couplers_RDATA),\n        .m_axi_rid(m01_regslice_to_m01_couplers_RID),\n        .m_axi_rlast(m01_regslice_to_m01_couplers_RLAST),\n        .m_axi_rready(m01_regslice_to_m01_couplers_RREADY),\n        .m_axi_rresp(m01_regslice_to_m01_couplers_RRESP),\n        .m_axi_rvalid(m01_regslice_to_m01_couplers_RVALID),\n        .m_axi_wdata(m01_regslice_to_m01_couplers_WDATA),\n        .m_axi_wlast(m01_regslice_to_m01_couplers_WLAST),\n        .m_axi_wready(m01_regslice_to_m01_couplers_WREADY),\n        .m_axi_wstrb(m01_regslice_to_m01_couplers_WSTRB),\n        .m_axi_wvalid(m01_regslice_to_m01_couplers_WVALID),\n        .s_axi_araddr(m01_couplers_to_m01_regslice_ARADDR),\n        .s_axi_arburst(m01_couplers_to_m01_regslice_ARBURST),\n        .s_axi_arcache(m01_couplers_to_m01_regslice_ARCACHE),\n        .s_axi_arid(m01_couplers_to_m01_regslice_ARID),\n        .s_axi_arlen(m01_couplers_to_m01_regslice_ARLEN),\n        .s_axi_arlock(m01_couplers_to_m01_regslice_ARLOCK),\n        .s_axi_arprot(m01_couplers_to_m01_regslice_ARPROT),\n        .s_axi_arqos(m01_couplers_to_m01_regslice_ARQOS),\n        .s_axi_arready(m01_couplers_to_m01_regslice_ARREADY),\n        .s_axi_arregion(m01_couplers_to_m01_regslice_ARREGION),\n        .s_axi_arsize(m01_couplers_to_m01_regslice_ARSIZE),\n        .s_axi_arvalid(m01_couplers_to_m01_regslice_ARVALID),\n        .s_axi_awaddr(m01_couplers_to_m01_regslice_AWADDR),\n        .s_axi_awburst(m01_couplers_to_m01_regslice_AWBURST),\n        .s_axi_awcache(m01_couplers_to_m01_regslice_AWCACHE),\n        .s_axi_awid(m01_couplers_to_m01_regslice_AWID),\n        .s_axi_awlen(m01_couplers_to_m01_regslice_AWLEN),\n        .s_axi_awlock(m01_couplers_to_m01_regslice_AWLOCK),\n        .s_axi_awprot(m01_couplers_to_m01_regslice_AWPROT),\n        .s_axi_awqos(m01_couplers_to_m01_regslice_AWQOS),\n        .s_axi_awready(m01_couplers_to_m01_regslice_AWREADY),\n        .s_axi_awregion(m01_couplers_to_m01_regslice_AWREGION),\n        .s_axi_awsize(m01_couplers_to_m01_regslice_AWSIZE),\n        .s_axi_awvalid(m01_couplers_to_m01_regslice_AWVALID),\n        .s_axi_bid(m01_couplers_to_m01_regslice_BID),\n        .s_axi_bready(m01_couplers_to_m01_regslice_BREADY),\n        .s_axi_bresp(m01_couplers_to_m01_regslice_BRESP),\n        .s_axi_bvalid(m01_couplers_to_m01_regslice_BVALID),\n        .s_axi_rdata(m01_couplers_to_m01_regslice_RDATA),\n        .s_axi_rid(m01_couplers_to_m01_regslice_RID),\n        .s_axi_rlast(m01_couplers_to_m01_regslice_RLAST),\n        .s_axi_rready(m01_couplers_to_m01_regslice_RREADY),\n        .s_axi_rresp(m01_couplers_to_m01_regslice_RRESP),\n        .s_axi_rvalid(m01_couplers_to_m01_regslice_RVALID),\n        .s_axi_wdata(m01_couplers_to_m01_regslice_WDATA),\n        .s_axi_wlast(m01_couplers_to_m01_regslice_WLAST),\n        .s_axi_wready(m01_couplers_to_m01_regslice_WREADY),\n        .s_axi_wstrb(m01_couplers_to_m01_regslice_WSTRB),\n        .s_axi_wvalid(m01_couplers_to_m01_regslice_WVALID));\nendmodule\n\nmodule m02_couplers_imp_APDUS2\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m02_couplers_to_m02_regslice_ARADDR;\n  wire [1:0]m02_couplers_to_m02_regslice_ARBURST;\n  wire [3:0]m02_couplers_to_m02_regslice_ARCACHE;\n  wire [6:0]m02_couplers_to_m02_regslice_ARID;\n  wire [7:0]m02_couplers_to_m02_regslice_ARLEN;\n  wire [0:0]m02_couplers_to_m02_regslice_ARLOCK;\n  wire [2:0]m02_couplers_to_m02_regslice_ARPROT;\n  wire [3:0]m02_couplers_to_m02_regslice_ARQOS;\n  wire m02_couplers_to_m02_regslice_ARREADY;\n  wire [3:0]m02_couplers_to_m02_regslice_ARREGION;\n  wire [2:0]m02_couplers_to_m02_regslice_ARSIZE;\n  wire m02_couplers_to_m02_regslice_ARVALID;\n  wire [63:0]m02_couplers_to_m02_regslice_AWADDR;\n  wire [1:0]m02_couplers_to_m02_regslice_AWBURST;\n  wire [3:0]m02_couplers_to_m02_regslice_AWCACHE;\n  wire [6:0]m02_couplers_to_m02_regslice_AWID;\n  wire [7:0]m02_couplers_to_m02_regslice_AWLEN;\n  wire [0:0]m02_couplers_to_m02_regslice_AWLOCK;\n  wire [2:0]m02_couplers_to_m02_regslice_AWPROT;\n  wire [3:0]m02_couplers_to_m02_regslice_AWQOS;\n  wire m02_couplers_to_m02_regslice_AWREADY;\n  wire [3:0]m02_couplers_to_m02_regslice_AWREGION;\n  wire [2:0]m02_couplers_to_m02_regslice_AWSIZE;\n  wire m02_couplers_to_m02_regslice_AWVALID;\n  wire [6:0]m02_couplers_to_m02_regslice_BID;\n  wire m02_couplers_to_m02_regslice_BREADY;\n  wire [1:0]m02_couplers_to_m02_regslice_BRESP;\n  wire m02_couplers_to_m02_regslice_BVALID;\n  wire [511:0]m02_couplers_to_m02_regslice_RDATA;\n  wire [6:0]m02_couplers_to_m02_regslice_RID;\n  wire m02_couplers_to_m02_regslice_RLAST;\n  wire m02_couplers_to_m02_regslice_RREADY;\n  wire [1:0]m02_couplers_to_m02_regslice_RRESP;\n  wire m02_couplers_to_m02_regslice_RVALID;\n  wire [511:0]m02_couplers_to_m02_regslice_WDATA;\n  wire m02_couplers_to_m02_regslice_WLAST;\n  wire m02_couplers_to_m02_regslice_WREADY;\n  wire [63:0]m02_couplers_to_m02_regslice_WSTRB;\n  wire m02_couplers_to_m02_regslice_WVALID;\n  wire [63:0]m02_regslice_to_m02_couplers_ARADDR;\n  wire [1:0]m02_regslice_to_m02_couplers_ARBURST;\n  wire [3:0]m02_regslice_to_m02_couplers_ARCACHE;\n  wire [6:0]m02_regslice_to_m02_couplers_ARID;\n  wire [7:0]m02_regslice_to_m02_couplers_ARLEN;\n  wire [0:0]m02_regslice_to_m02_couplers_ARLOCK;\n  wire [2:0]m02_regslice_to_m02_couplers_ARPROT;\n  wire [3:0]m02_regslice_to_m02_couplers_ARQOS;\n  wire m02_regslice_to_m02_couplers_ARREADY;\n  wire [3:0]m02_regslice_to_m02_couplers_ARREGION;\n  wire [2:0]m02_regslice_to_m02_couplers_ARSIZE;\n  wire m02_regslice_to_m02_couplers_ARVALID;\n  wire [63:0]m02_regslice_to_m02_couplers_AWADDR;\n  wire [1:0]m02_regslice_to_m02_couplers_AWBURST;\n  wire [3:0]m02_regslice_to_m02_couplers_AWCACHE;\n  wire [6:0]m02_regslice_to_m02_couplers_AWID;\n  wire [7:0]m02_regslice_to_m02_couplers_AWLEN;\n  wire [0:0]m02_regslice_to_m02_couplers_AWLOCK;\n  wire [2:0]m02_regslice_to_m02_couplers_AWPROT;\n  wire [3:0]m02_regslice_to_m02_couplers_AWQOS;\n  wire m02_regslice_to_m02_couplers_AWREADY;\n  wire [3:0]m02_regslice_to_m02_couplers_AWREGION;\n  wire [2:0]m02_regslice_to_m02_couplers_AWSIZE;\n  wire m02_regslice_to_m02_couplers_AWVALID;\n  wire [6:0]m02_regslice_to_m02_couplers_BID;\n  wire m02_regslice_to_m02_couplers_BREADY;\n  wire [1:0]m02_regslice_to_m02_couplers_BRESP;\n  wire m02_regslice_to_m02_couplers_BVALID;\n  wire [511:0]m02_regslice_to_m02_couplers_RDATA;\n  wire [6:0]m02_regslice_to_m02_couplers_RID;\n  wire m02_regslice_to_m02_couplers_RLAST;\n  wire m02_regslice_to_m02_couplers_RREADY;\n  wire [1:0]m02_regslice_to_m02_couplers_RRESP;\n  wire m02_regslice_to_m02_couplers_RVALID;\n  wire [511:0]m02_regslice_to_m02_couplers_WDATA;\n  wire m02_regslice_to_m02_couplers_WLAST;\n  wire m02_regslice_to_m02_couplers_WREADY;\n  wire [63:0]m02_regslice_to_m02_couplers_WSTRB;\n  wire m02_regslice_to_m02_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m02_regslice_to_m02_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m02_regslice_to_m02_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m02_regslice_to_m02_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m02_regslice_to_m02_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m02_regslice_to_m02_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m02_regslice_to_m02_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m02_regslice_to_m02_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m02_regslice_to_m02_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m02_regslice_to_m02_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m02_regslice_to_m02_couplers_ARSIZE;\n  assign M_AXI_arvalid = m02_regslice_to_m02_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m02_regslice_to_m02_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m02_regslice_to_m02_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m02_regslice_to_m02_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m02_regslice_to_m02_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m02_regslice_to_m02_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m02_regslice_to_m02_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m02_regslice_to_m02_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m02_regslice_to_m02_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m02_regslice_to_m02_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m02_regslice_to_m02_couplers_AWSIZE;\n  assign M_AXI_awvalid = m02_regslice_to_m02_couplers_AWVALID;\n  assign M_AXI_bready = m02_regslice_to_m02_couplers_BREADY;\n  assign M_AXI_rready = m02_regslice_to_m02_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m02_regslice_to_m02_couplers_WDATA;\n  assign M_AXI_wlast = m02_regslice_to_m02_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m02_regslice_to_m02_couplers_WSTRB;\n  assign M_AXI_wvalid = m02_regslice_to_m02_couplers_WVALID;\n  assign S_AXI_arready = m02_couplers_to_m02_regslice_ARREADY;\n  assign S_AXI_awready = m02_couplers_to_m02_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m02_couplers_to_m02_regslice_BID;\n  assign S_AXI_bresp[1:0] = m02_couplers_to_m02_regslice_BRESP;\n  assign S_AXI_bvalid = m02_couplers_to_m02_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m02_couplers_to_m02_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m02_couplers_to_m02_regslice_RID;\n  assign S_AXI_rlast = m02_couplers_to_m02_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m02_couplers_to_m02_regslice_RRESP;\n  assign S_AXI_rvalid = m02_couplers_to_m02_regslice_RVALID;\n  assign S_AXI_wready = m02_couplers_to_m02_regslice_WREADY;\n  assign m02_couplers_to_m02_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m02_couplers_to_m02_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m02_couplers_to_m02_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m02_couplers_to_m02_regslice_ARID = S_AXI_arid[6:0];\n  assign m02_couplers_to_m02_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m02_couplers_to_m02_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m02_couplers_to_m02_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m02_couplers_to_m02_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m02_couplers_to_m02_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m02_couplers_to_m02_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m02_couplers_to_m02_regslice_ARVALID = S_AXI_arvalid;\n  assign m02_couplers_to_m02_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m02_couplers_to_m02_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m02_couplers_to_m02_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m02_couplers_to_m02_regslice_AWID = S_AXI_awid[6:0];\n  assign m02_couplers_to_m02_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m02_couplers_to_m02_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m02_couplers_to_m02_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m02_couplers_to_m02_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m02_couplers_to_m02_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m02_couplers_to_m02_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m02_couplers_to_m02_regslice_AWVALID = S_AXI_awvalid;\n  assign m02_couplers_to_m02_regslice_BREADY = S_AXI_bready;\n  assign m02_couplers_to_m02_regslice_RREADY = S_AXI_rready;\n  assign m02_couplers_to_m02_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m02_couplers_to_m02_regslice_WLAST = S_AXI_wlast;\n  assign m02_couplers_to_m02_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m02_couplers_to_m02_regslice_WVALID = S_AXI_wvalid;\n  assign m02_regslice_to_m02_couplers_ARREADY = M_AXI_arready;\n  assign m02_regslice_to_m02_couplers_AWREADY = M_AXI_awready;\n  assign m02_regslice_to_m02_couplers_BID = M_AXI_bid[6:0];\n  assign m02_regslice_to_m02_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m02_regslice_to_m02_couplers_BVALID = M_AXI_bvalid;\n  assign m02_regslice_to_m02_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m02_regslice_to_m02_couplers_RID = M_AXI_rid[6:0];\n  assign m02_regslice_to_m02_couplers_RLAST = M_AXI_rlast;\n  assign m02_regslice_to_m02_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m02_regslice_to_m02_couplers_RVALID = M_AXI_rvalid;\n  assign m02_regslice_to_m02_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m02_regslice_0 m02_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m02_regslice_to_m02_couplers_ARADDR),\n        .m_axi_arburst(m02_regslice_to_m02_couplers_ARBURST),\n        .m_axi_arcache(m02_regslice_to_m02_couplers_ARCACHE),\n        .m_axi_arid(m02_regslice_to_m02_couplers_ARID),\n        .m_axi_arlen(m02_regslice_to_m02_couplers_ARLEN),\n        .m_axi_arlock(m02_regslice_to_m02_couplers_ARLOCK),\n        .m_axi_arprot(m02_regslice_to_m02_couplers_ARPROT),\n        .m_axi_arqos(m02_regslice_to_m02_couplers_ARQOS),\n        .m_axi_arready(m02_regslice_to_m02_couplers_ARREADY),\n        .m_axi_arregion(m02_regslice_to_m02_couplers_ARREGION),\n        .m_axi_arsize(m02_regslice_to_m02_couplers_ARSIZE),\n        .m_axi_arvalid(m02_regslice_to_m02_couplers_ARVALID),\n        .m_axi_awaddr(m02_regslice_to_m02_couplers_AWADDR),\n        .m_axi_awburst(m02_regslice_to_m02_couplers_AWBURST),\n        .m_axi_awcache(m02_regslice_to_m02_couplers_AWCACHE),\n        .m_axi_awid(m02_regslice_to_m02_couplers_AWID),\n        .m_axi_awlen(m02_regslice_to_m02_couplers_AWLEN),\n        .m_axi_awlock(m02_regslice_to_m02_couplers_AWLOCK),\n        .m_axi_awprot(m02_regslice_to_m02_couplers_AWPROT),\n        .m_axi_awqos(m02_regslice_to_m02_couplers_AWQOS),\n        .m_axi_awready(m02_regslice_to_m02_couplers_AWREADY),\n        .m_axi_awregion(m02_regslice_to_m02_couplers_AWREGION),\n        .m_axi_awsize(m02_regslice_to_m02_couplers_AWSIZE),\n        .m_axi_awvalid(m02_regslice_to_m02_couplers_AWVALID),\n        .m_axi_bid(m02_regslice_to_m02_couplers_BID),\n        .m_axi_bready(m02_regslice_to_m02_couplers_BREADY),\n        .m_axi_bresp(m02_regslice_to_m02_couplers_BRESP),\n        .m_axi_bvalid(m02_regslice_to_m02_couplers_BVALID),\n        .m_axi_rdata(m02_regslice_to_m02_couplers_RDATA),\n        .m_axi_rid(m02_regslice_to_m02_couplers_RID),\n        .m_axi_rlast(m02_regslice_to_m02_couplers_RLAST),\n        .m_axi_rready(m02_regslice_to_m02_couplers_RREADY),\n        .m_axi_rresp(m02_regslice_to_m02_couplers_RRESP),\n        .m_axi_rvalid(m02_regslice_to_m02_couplers_RVALID),\n        .m_axi_wdata(m02_regslice_to_m02_couplers_WDATA),\n        .m_axi_wlast(m02_regslice_to_m02_couplers_WLAST),\n        .m_axi_wready(m02_regslice_to_m02_couplers_WREADY),\n        .m_axi_wstrb(m02_regslice_to_m02_couplers_WSTRB),\n        .m_axi_wvalid(m02_regslice_to_m02_couplers_WVALID),\n        .s_axi_araddr(m02_couplers_to_m02_regslice_ARADDR),\n        .s_axi_arburst(m02_couplers_to_m02_regslice_ARBURST),\n        .s_axi_arcache(m02_couplers_to_m02_regslice_ARCACHE),\n        .s_axi_arid(m02_couplers_to_m02_regslice_ARID),\n        .s_axi_arlen(m02_couplers_to_m02_regslice_ARLEN),\n        .s_axi_arlock(m02_couplers_to_m02_regslice_ARLOCK),\n        .s_axi_arprot(m02_couplers_to_m02_regslice_ARPROT),\n        .s_axi_arqos(m02_couplers_to_m02_regslice_ARQOS),\n        .s_axi_arready(m02_couplers_to_m02_regslice_ARREADY),\n        .s_axi_arregion(m02_couplers_to_m02_regslice_ARREGION),\n        .s_axi_arsize(m02_couplers_to_m02_regslice_ARSIZE),\n        .s_axi_arvalid(m02_couplers_to_m02_regslice_ARVALID),\n        .s_axi_awaddr(m02_couplers_to_m02_regslice_AWADDR),\n        .s_axi_awburst(m02_couplers_to_m02_regslice_AWBURST),\n        .s_axi_awcache(m02_couplers_to_m02_regslice_AWCACHE),\n        .s_axi_awid(m02_couplers_to_m02_regslice_AWID),\n        .s_axi_awlen(m02_couplers_to_m02_regslice_AWLEN),\n        .s_axi_awlock(m02_couplers_to_m02_regslice_AWLOCK),\n        .s_axi_awprot(m02_couplers_to_m02_regslice_AWPROT),\n        .s_axi_awqos(m02_couplers_to_m02_regslice_AWQOS),\n        .s_axi_awready(m02_couplers_to_m02_regslice_AWREADY),\n        .s_axi_awregion(m02_couplers_to_m02_regslice_AWREGION),\n        .s_axi_awsize(m02_couplers_to_m02_regslice_AWSIZE),\n        .s_axi_awvalid(m02_couplers_to_m02_regslice_AWVALID),\n        .s_axi_bid(m02_couplers_to_m02_regslice_BID),\n        .s_axi_bready(m02_couplers_to_m02_regslice_BREADY),\n        .s_axi_bresp(m02_couplers_to_m02_regslice_BRESP),\n        .s_axi_bvalid(m02_couplers_to_m02_regslice_BVALID),\n        .s_axi_rdata(m02_couplers_to_m02_regslice_RDATA),\n        .s_axi_rid(m02_couplers_to_m02_regslice_RID),\n        .s_axi_rlast(m02_couplers_to_m02_regslice_RLAST),\n        .s_axi_rready(m02_couplers_to_m02_regslice_RREADY),\n        .s_axi_rresp(m02_couplers_to_m02_regslice_RRESP),\n        .s_axi_rvalid(m02_couplers_to_m02_regslice_RVALID),\n        .s_axi_wdata(m02_couplers_to_m02_regslice_WDATA),\n        .s_axi_wlast(m02_couplers_to_m02_regslice_WLAST),\n        .s_axi_wready(m02_couplers_to_m02_regslice_WREADY),\n        .s_axi_wstrb(m02_couplers_to_m02_regslice_WSTRB),\n        .s_axi_wvalid(m02_couplers_to_m02_regslice_WVALID));\nendmodule\n\nmodule m03_couplers_imp_JAYOMU\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m03_couplers_to_m03_regslice_ARADDR;\n  wire [1:0]m03_couplers_to_m03_regslice_ARBURST;\n  wire [3:0]m03_couplers_to_m03_regslice_ARCACHE;\n  wire [6:0]m03_couplers_to_m03_regslice_ARID;\n  wire [7:0]m03_couplers_to_m03_regslice_ARLEN;\n  wire [0:0]m03_couplers_to_m03_regslice_ARLOCK;\n  wire [2:0]m03_couplers_to_m03_regslice_ARPROT;\n  wire [3:0]m03_couplers_to_m03_regslice_ARQOS;\n  wire m03_couplers_to_m03_regslice_ARREADY;\n  wire [3:0]m03_couplers_to_m03_regslice_ARREGION;\n  wire [2:0]m03_couplers_to_m03_regslice_ARSIZE;\n  wire m03_couplers_to_m03_regslice_ARVALID;\n  wire [63:0]m03_couplers_to_m03_regslice_AWADDR;\n  wire [1:0]m03_couplers_to_m03_regslice_AWBURST;\n  wire [3:0]m03_couplers_to_m03_regslice_AWCACHE;\n  wire [6:0]m03_couplers_to_m03_regslice_AWID;\n  wire [7:0]m03_couplers_to_m03_regslice_AWLEN;\n  wire [0:0]m03_couplers_to_m03_regslice_AWLOCK;\n  wire [2:0]m03_couplers_to_m03_regslice_AWPROT;\n  wire [3:0]m03_couplers_to_m03_regslice_AWQOS;\n  wire m03_couplers_to_m03_regslice_AWREADY;\n  wire [3:0]m03_couplers_to_m03_regslice_AWREGION;\n  wire [2:0]m03_couplers_to_m03_regslice_AWSIZE;\n  wire m03_couplers_to_m03_regslice_AWVALID;\n  wire [6:0]m03_couplers_to_m03_regslice_BID;\n  wire m03_couplers_to_m03_regslice_BREADY;\n  wire [1:0]m03_couplers_to_m03_regslice_BRESP;\n  wire m03_couplers_to_m03_regslice_BVALID;\n  wire [511:0]m03_couplers_to_m03_regslice_RDATA;\n  wire [6:0]m03_couplers_to_m03_regslice_RID;\n  wire m03_couplers_to_m03_regslice_RLAST;\n  wire m03_couplers_to_m03_regslice_RREADY;\n  wire [1:0]m03_couplers_to_m03_regslice_RRESP;\n  wire m03_couplers_to_m03_regslice_RVALID;\n  wire [511:0]m03_couplers_to_m03_regslice_WDATA;\n  wire m03_couplers_to_m03_regslice_WLAST;\n  wire m03_couplers_to_m03_regslice_WREADY;\n  wire [63:0]m03_couplers_to_m03_regslice_WSTRB;\n  wire m03_couplers_to_m03_regslice_WVALID;\n  wire [63:0]m03_regslice_to_m03_couplers_ARADDR;\n  wire [1:0]m03_regslice_to_m03_couplers_ARBURST;\n  wire [3:0]m03_regslice_to_m03_couplers_ARCACHE;\n  wire [6:0]m03_regslice_to_m03_couplers_ARID;\n  wire [7:0]m03_regslice_to_m03_couplers_ARLEN;\n  wire [0:0]m03_regslice_to_m03_couplers_ARLOCK;\n  wire [2:0]m03_regslice_to_m03_couplers_ARPROT;\n  wire [3:0]m03_regslice_to_m03_couplers_ARQOS;\n  wire m03_regslice_to_m03_couplers_ARREADY;\n  wire [3:0]m03_regslice_to_m03_couplers_ARREGION;\n  wire [2:0]m03_regslice_to_m03_couplers_ARSIZE;\n  wire m03_regslice_to_m03_couplers_ARVALID;\n  wire [63:0]m03_regslice_to_m03_couplers_AWADDR;\n  wire [1:0]m03_regslice_to_m03_couplers_AWBURST;\n  wire [3:0]m03_regslice_to_m03_couplers_AWCACHE;\n  wire [6:0]m03_regslice_to_m03_couplers_AWID;\n  wire [7:0]m03_regslice_to_m03_couplers_AWLEN;\n  wire [0:0]m03_regslice_to_m03_couplers_AWLOCK;\n  wire [2:0]m03_regslice_to_m03_couplers_AWPROT;\n  wire [3:0]m03_regslice_to_m03_couplers_AWQOS;\n  wire m03_regslice_to_m03_couplers_AWREADY;\n  wire [3:0]m03_regslice_to_m03_couplers_AWREGION;\n  wire [2:0]m03_regslice_to_m03_couplers_AWSIZE;\n  wire m03_regslice_to_m03_couplers_AWVALID;\n  wire [6:0]m03_regslice_to_m03_couplers_BID;\n  wire m03_regslice_to_m03_couplers_BREADY;\n  wire [1:0]m03_regslice_to_m03_couplers_BRESP;\n  wire m03_regslice_to_m03_couplers_BVALID;\n  wire [511:0]m03_regslice_to_m03_couplers_RDATA;\n  wire [6:0]m03_regslice_to_m03_couplers_RID;\n  wire m03_regslice_to_m03_couplers_RLAST;\n  wire m03_regslice_to_m03_couplers_RREADY;\n  wire [1:0]m03_regslice_to_m03_couplers_RRESP;\n  wire m03_regslice_to_m03_couplers_RVALID;\n  wire [511:0]m03_regslice_to_m03_couplers_WDATA;\n  wire m03_regslice_to_m03_couplers_WLAST;\n  wire m03_regslice_to_m03_couplers_WREADY;\n  wire [63:0]m03_regslice_to_m03_couplers_WSTRB;\n  wire m03_regslice_to_m03_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m03_regslice_to_m03_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m03_regslice_to_m03_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m03_regslice_to_m03_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m03_regslice_to_m03_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m03_regslice_to_m03_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m03_regslice_to_m03_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m03_regslice_to_m03_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m03_regslice_to_m03_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m03_regslice_to_m03_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m03_regslice_to_m03_couplers_ARSIZE;\n  assign M_AXI_arvalid = m03_regslice_to_m03_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m03_regslice_to_m03_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m03_regslice_to_m03_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m03_regslice_to_m03_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m03_regslice_to_m03_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m03_regslice_to_m03_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m03_regslice_to_m03_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m03_regslice_to_m03_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m03_regslice_to_m03_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m03_regslice_to_m03_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m03_regslice_to_m03_couplers_AWSIZE;\n  assign M_AXI_awvalid = m03_regslice_to_m03_couplers_AWVALID;\n  assign M_AXI_bready = m03_regslice_to_m03_couplers_BREADY;\n  assign M_AXI_rready = m03_regslice_to_m03_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m03_regslice_to_m03_couplers_WDATA;\n  assign M_AXI_wlast = m03_regslice_to_m03_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m03_regslice_to_m03_couplers_WSTRB;\n  assign M_AXI_wvalid = m03_regslice_to_m03_couplers_WVALID;\n  assign S_AXI_arready = m03_couplers_to_m03_regslice_ARREADY;\n  assign S_AXI_awready = m03_couplers_to_m03_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m03_couplers_to_m03_regslice_BID;\n  assign S_AXI_bresp[1:0] = m03_couplers_to_m03_regslice_BRESP;\n  assign S_AXI_bvalid = m03_couplers_to_m03_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m03_couplers_to_m03_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m03_couplers_to_m03_regslice_RID;\n  assign S_AXI_rlast = m03_couplers_to_m03_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m03_couplers_to_m03_regslice_RRESP;\n  assign S_AXI_rvalid = m03_couplers_to_m03_regslice_RVALID;\n  assign S_AXI_wready = m03_couplers_to_m03_regslice_WREADY;\n  assign m03_couplers_to_m03_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m03_couplers_to_m03_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m03_couplers_to_m03_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m03_couplers_to_m03_regslice_ARID = S_AXI_arid[6:0];\n  assign m03_couplers_to_m03_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m03_couplers_to_m03_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m03_couplers_to_m03_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m03_couplers_to_m03_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m03_couplers_to_m03_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m03_couplers_to_m03_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m03_couplers_to_m03_regslice_ARVALID = S_AXI_arvalid;\n  assign m03_couplers_to_m03_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m03_couplers_to_m03_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m03_couplers_to_m03_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m03_couplers_to_m03_regslice_AWID = S_AXI_awid[6:0];\n  assign m03_couplers_to_m03_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m03_couplers_to_m03_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m03_couplers_to_m03_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m03_couplers_to_m03_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m03_couplers_to_m03_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m03_couplers_to_m03_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m03_couplers_to_m03_regslice_AWVALID = S_AXI_awvalid;\n  assign m03_couplers_to_m03_regslice_BREADY = S_AXI_bready;\n  assign m03_couplers_to_m03_regslice_RREADY = S_AXI_rready;\n  assign m03_couplers_to_m03_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m03_couplers_to_m03_regslice_WLAST = S_AXI_wlast;\n  assign m03_couplers_to_m03_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m03_couplers_to_m03_regslice_WVALID = S_AXI_wvalid;\n  assign m03_regslice_to_m03_couplers_ARREADY = M_AXI_arready;\n  assign m03_regslice_to_m03_couplers_AWREADY = M_AXI_awready;\n  assign m03_regslice_to_m03_couplers_BID = M_AXI_bid[6:0];\n  assign m03_regslice_to_m03_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m03_regslice_to_m03_couplers_BVALID = M_AXI_bvalid;\n  assign m03_regslice_to_m03_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m03_regslice_to_m03_couplers_RID = M_AXI_rid[6:0];\n  assign m03_regslice_to_m03_couplers_RLAST = M_AXI_rlast;\n  assign m03_regslice_to_m03_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m03_regslice_to_m03_couplers_RVALID = M_AXI_rvalid;\n  assign m03_regslice_to_m03_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m03_regslice_0 m03_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m03_regslice_to_m03_couplers_ARADDR),\n        .m_axi_arburst(m03_regslice_to_m03_couplers_ARBURST),\n        .m_axi_arcache(m03_regslice_to_m03_couplers_ARCACHE),\n        .m_axi_arid(m03_regslice_to_m03_couplers_ARID),\n        .m_axi_arlen(m03_regslice_to_m03_couplers_ARLEN),\n        .m_axi_arlock(m03_regslice_to_m03_couplers_ARLOCK),\n        .m_axi_arprot(m03_regslice_to_m03_couplers_ARPROT),\n        .m_axi_arqos(m03_regslice_to_m03_couplers_ARQOS),\n        .m_axi_arready(m03_regslice_to_m03_couplers_ARREADY),\n        .m_axi_arregion(m03_regslice_to_m03_couplers_ARREGION),\n        .m_axi_arsize(m03_regslice_to_m03_couplers_ARSIZE),\n        .m_axi_arvalid(m03_regslice_to_m03_couplers_ARVALID),\n        .m_axi_awaddr(m03_regslice_to_m03_couplers_AWADDR),\n        .m_axi_awburst(m03_regslice_to_m03_couplers_AWBURST),\n        .m_axi_awcache(m03_regslice_to_m03_couplers_AWCACHE),\n        .m_axi_awid(m03_regslice_to_m03_couplers_AWID),\n        .m_axi_awlen(m03_regslice_to_m03_couplers_AWLEN),\n        .m_axi_awlock(m03_regslice_to_m03_couplers_AWLOCK),\n        .m_axi_awprot(m03_regslice_to_m03_couplers_AWPROT),\n        .m_axi_awqos(m03_regslice_to_m03_couplers_AWQOS),\n        .m_axi_awready(m03_regslice_to_m03_couplers_AWREADY),\n        .m_axi_awregion(m03_regslice_to_m03_couplers_AWREGION),\n        .m_axi_awsize(m03_regslice_to_m03_couplers_AWSIZE),\n        .m_axi_awvalid(m03_regslice_to_m03_couplers_AWVALID),\n        .m_axi_bid(m03_regslice_to_m03_couplers_BID),\n        .m_axi_bready(m03_regslice_to_m03_couplers_BREADY),\n        .m_axi_bresp(m03_regslice_to_m03_couplers_BRESP),\n        .m_axi_bvalid(m03_regslice_to_m03_couplers_BVALID),\n        .m_axi_rdata(m03_regslice_to_m03_couplers_RDATA),\n        .m_axi_rid(m03_regslice_to_m03_couplers_RID),\n        .m_axi_rlast(m03_regslice_to_m03_couplers_RLAST),\n        .m_axi_rready(m03_regslice_to_m03_couplers_RREADY),\n        .m_axi_rresp(m03_regslice_to_m03_couplers_RRESP),\n        .m_axi_rvalid(m03_regslice_to_m03_couplers_RVALID),\n        .m_axi_wdata(m03_regslice_to_m03_couplers_WDATA),\n        .m_axi_wlast(m03_regslice_to_m03_couplers_WLAST),\n        .m_axi_wready(m03_regslice_to_m03_couplers_WREADY),\n        .m_axi_wstrb(m03_regslice_to_m03_couplers_WSTRB),\n        .m_axi_wvalid(m03_regslice_to_m03_couplers_WVALID),\n        .s_axi_araddr(m03_couplers_to_m03_regslice_ARADDR),\n        .s_axi_arburst(m03_couplers_to_m03_regslice_ARBURST),\n        .s_axi_arcache(m03_couplers_to_m03_regslice_ARCACHE),\n        .s_axi_arid(m03_couplers_to_m03_regslice_ARID),\n        .s_axi_arlen(m03_couplers_to_m03_regslice_ARLEN),\n        .s_axi_arlock(m03_couplers_to_m03_regslice_ARLOCK),\n        .s_axi_arprot(m03_couplers_to_m03_regslice_ARPROT),\n        .s_axi_arqos(m03_couplers_to_m03_regslice_ARQOS),\n        .s_axi_arready(m03_couplers_to_m03_regslice_ARREADY),\n        .s_axi_arregion(m03_couplers_to_m03_regslice_ARREGION),\n        .s_axi_arsize(m03_couplers_to_m03_regslice_ARSIZE),\n        .s_axi_arvalid(m03_couplers_to_m03_regslice_ARVALID),\n        .s_axi_awaddr(m03_couplers_to_m03_regslice_AWADDR),\n        .s_axi_awburst(m03_couplers_to_m03_regslice_AWBURST),\n        .s_axi_awcache(m03_couplers_to_m03_regslice_AWCACHE),\n        .s_axi_awid(m03_couplers_to_m03_regslice_AWID),\n        .s_axi_awlen(m03_couplers_to_m03_regslice_AWLEN),\n        .s_axi_awlock(m03_couplers_to_m03_regslice_AWLOCK),\n        .s_axi_awprot(m03_couplers_to_m03_regslice_AWPROT),\n        .s_axi_awqos(m03_couplers_to_m03_regslice_AWQOS),\n        .s_axi_awready(m03_couplers_to_m03_regslice_AWREADY),\n        .s_axi_awregion(m03_couplers_to_m03_regslice_AWREGION),\n        .s_axi_awsize(m03_couplers_to_m03_regslice_AWSIZE),\n        .s_axi_awvalid(m03_couplers_to_m03_regslice_AWVALID),\n        .s_axi_bid(m03_couplers_to_m03_regslice_BID),\n        .s_axi_bready(m03_couplers_to_m03_regslice_BREADY),\n        .s_axi_bresp(m03_couplers_to_m03_regslice_BRESP),\n        .s_axi_bvalid(m03_couplers_to_m03_regslice_BVALID),\n        .s_axi_rdata(m03_couplers_to_m03_regslice_RDATA),\n        .s_axi_rid(m03_couplers_to_m03_regslice_RID),\n        .s_axi_rlast(m03_couplers_to_m03_regslice_RLAST),\n        .s_axi_rready(m03_couplers_to_m03_regslice_RREADY),\n        .s_axi_rresp(m03_couplers_to_m03_regslice_RRESP),\n        .s_axi_rvalid(m03_couplers_to_m03_regslice_RVALID),\n        .s_axi_wdata(m03_couplers_to_m03_regslice_WDATA),\n        .s_axi_wlast(m03_couplers_to_m03_regslice_WLAST),\n        .s_axi_wready(m03_couplers_to_m03_regslice_WREADY),\n        .s_axi_wstrb(m03_couplers_to_m03_regslice_WSTRB),\n        .s_axi_wvalid(m03_couplers_to_m03_regslice_WVALID));\nendmodule\n\nmodule s00_couplers_imp_QICM5G\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [5:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [5:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [5:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [5:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [5:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [5:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire S_ACLK_1;\n  wire S_ARESETN_1;\n  wire [63:0]s00_couplers_to_s00_regslice_ARADDR;\n  wire [1:0]s00_couplers_to_s00_regslice_ARBURST;\n  wire [3:0]s00_couplers_to_s00_regslice_ARCACHE;\n  wire [5:0]s00_couplers_to_s00_regslice_ARID;\n  wire [7:0]s00_couplers_to_s00_regslice_ARLEN;\n  wire [0:0]s00_couplers_to_s00_regslice_ARLOCK;\n  wire [2:0]s00_couplers_to_s00_regslice_ARPROT;\n  wire [3:0]s00_couplers_to_s00_regslice_ARQOS;\n  wire s00_couplers_to_s00_regslice_ARREADY;\n  wire [3:0]s00_couplers_to_s00_regslice_ARREGION;\n  wire [2:0]s00_couplers_to_s00_regslice_ARSIZE;\n  wire s00_couplers_to_s00_regslice_ARVALID;\n  wire [63:0]s00_couplers_to_s00_regslice_AWADDR;\n  wire [1:0]s00_couplers_to_s00_regslice_AWBURST;\n  wire [3:0]s00_couplers_to_s00_regslice_AWCACHE;\n  wire [5:0]s00_couplers_to_s00_regslice_AWID;\n  wire [7:0]s00_couplers_to_s00_regslice_AWLEN;\n  wire [0:0]s00_couplers_to_s00_regslice_AWLOCK;\n  wire [2:0]s00_couplers_to_s00_regslice_AWPROT;\n  wire [3:0]s00_couplers_to_s00_regslice_AWQOS;\n  wire s00_couplers_to_s00_regslice_AWREADY;\n  wire [3:0]s00_couplers_to_s00_regslice_AWREGION;\n  wire [2:0]s00_couplers_to_s00_regslice_AWSIZE;\n  wire s00_couplers_to_s00_regslice_AWVALID;\n  wire [5:0]s00_couplers_to_s00_regslice_BID;\n  wire s00_couplers_to_s00_regslice_BREADY;\n  wire [1:0]s00_couplers_to_s00_regslice_BRESP;\n  wire s00_couplers_to_s00_regslice_BVALID;\n  wire [511:0]s00_couplers_to_s00_regslice_RDATA;\n  wire [5:0]s00_couplers_to_s00_regslice_RID;\n  wire s00_couplers_to_s00_regslice_RLAST;\n  wire s00_couplers_to_s00_regslice_RREADY;\n  wire [1:0]s00_couplers_to_s00_regslice_RRESP;\n  wire s00_couplers_to_s00_regslice_RVALID;\n  wire [511:0]s00_couplers_to_s00_regslice_WDATA;\n  wire s00_couplers_to_s00_regslice_WLAST;\n  wire s00_couplers_to_s00_regslice_WREADY;\n  wire [63:0]s00_couplers_to_s00_regslice_WSTRB;\n  wire s00_couplers_to_s00_regslice_WVALID;\n  wire [63:0]s00_regslice_to_s00_couplers_ARADDR;\n  wire [1:0]s00_regslice_to_s00_couplers_ARBURST;\n  wire [3:0]s00_regslice_to_s00_couplers_ARCACHE;\n  wire [5:0]s00_regslice_to_s00_couplers_ARID;\n  wire [7:0]s00_regslice_to_s00_couplers_ARLEN;\n  wire [0:0]s00_regslice_to_s00_couplers_ARLOCK;\n  wire [2:0]s00_regslice_to_s00_couplers_ARPROT;\n  wire [3:0]s00_regslice_to_s00_couplers_ARQOS;\n  wire s00_regslice_to_s00_couplers_ARREADY;\n  wire [2:0]s00_regslice_to_s00_couplers_ARSIZE;\n  wire s00_regslice_to_s00_couplers_ARVALID;\n  wire [63:0]s00_regslice_to_s00_couplers_AWADDR;\n  wire [1:0]s00_regslice_to_s00_couplers_AWBURST;\n  wire [3:0]s00_regslice_to_s00_couplers_AWCACHE;\n  wire [5:0]s00_regslice_to_s00_couplers_AWID;\n  wire [7:0]s00_regslice_to_s00_couplers_AWLEN;\n  wire [0:0]s00_regslice_to_s00_couplers_AWLOCK;\n  wire [2:0]s00_regslice_to_s00_couplers_AWPROT;\n  wire [3:0]s00_regslice_to_s00_couplers_AWQOS;\n  wire s00_regslice_to_s00_couplers_AWREADY;\n  wire [2:0]s00_regslice_to_s00_couplers_AWSIZE;\n  wire s00_regslice_to_s00_couplers_AWVALID;\n  wire [6:0]s00_regslice_to_s00_couplers_BID;\n  wire s00_regslice_to_s00_couplers_BREADY;\n  wire [1:0]s00_regslice_to_s00_couplers_BRESP;\n  wire s00_regslice_to_s00_couplers_BVALID;\n  wire [511:0]s00_regslice_to_s00_couplers_RDATA;\n  wire [6:0]s00_regslice_to_s00_couplers_RID;\n  wire s00_regslice_to_s00_couplers_RLAST;\n  wire s00_regslice_to_s00_couplers_RREADY;\n  wire [1:0]s00_regslice_to_s00_couplers_RRESP;\n  wire s00_regslice_to_s00_couplers_RVALID;\n  wire [511:0]s00_regslice_to_s00_couplers_WDATA;\n  wire s00_regslice_to_s00_couplers_WLAST;\n  wire s00_regslice_to_s00_couplers_WREADY;\n  wire [63:0]s00_regslice_to_s00_couplers_WSTRB;\n  wire s00_regslice_to_s00_couplers_WVALID;\n\n  assign M_AXI_araddr[63:0] = s00_regslice_to_s00_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = s00_regslice_to_s00_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = s00_regslice_to_s00_couplers_ARCACHE;\n  assign M_AXI_arid[5:0] = s00_regslice_to_s00_couplers_ARID;\n  assign M_AXI_arlen[7:0] = s00_regslice_to_s00_couplers_ARLEN;\n  assign M_AXI_arlock[0] = s00_regslice_to_s00_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = s00_regslice_to_s00_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = s00_regslice_to_s00_couplers_ARQOS;\n  assign M_AXI_arsize[2:0] = s00_regslice_to_s00_couplers_ARSIZE;\n  assign M_AXI_arvalid = s00_regslice_to_s00_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = s00_regslice_to_s00_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = s00_regslice_to_s00_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = s00_regslice_to_s00_couplers_AWCACHE;\n  assign M_AXI_awid[5:0] = s00_regslice_to_s00_couplers_AWID;\n  assign M_AXI_awlen[7:0] = s00_regslice_to_s00_couplers_AWLEN;\n  assign M_AXI_awlock[0] = s00_regslice_to_s00_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = s00_regslice_to_s00_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = s00_regslice_to_s00_couplers_AWQOS;\n  assign M_AXI_awsize[2:0] = s00_regslice_to_s00_couplers_AWSIZE;\n  assign M_AXI_awvalid = s00_regslice_to_s00_couplers_AWVALID;\n  assign M_AXI_bready = s00_regslice_to_s00_couplers_BREADY;\n  assign M_AXI_rready = s00_regslice_to_s00_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = s00_regslice_to_s00_couplers_WDATA;\n  assign M_AXI_wlast = s00_regslice_to_s00_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = s00_regslice_to_s00_couplers_WSTRB;\n  assign M_AXI_wvalid = s00_regslice_to_s00_couplers_WVALID;\n  assign S_ACLK_1 = S_ACLK;\n  assign S_ARESETN_1 = S_ARESETN;\n  assign S_AXI_arready = s00_couplers_to_s00_regslice_ARREADY;\n  assign S_AXI_awready = s00_couplers_to_s00_regslice_AWREADY;\n  assign S_AXI_bid[5:0] = s00_couplers_to_s00_regslice_BID;\n  assign S_AXI_bresp[1:0] = s00_couplers_to_s00_regslice_BRESP;\n  assign S_AXI_bvalid = s00_couplers_to_s00_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = s00_couplers_to_s00_regslice_RDATA;\n  assign S_AXI_rid[5:0] = s00_couplers_to_s00_regslice_RID;\n  assign S_AXI_rlast = s00_couplers_to_s00_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = s00_couplers_to_s00_regslice_RRESP;\n  assign S_AXI_rvalid = s00_couplers_to_s00_regslice_RVALID;\n  assign S_AXI_wready = s00_couplers_to_s00_regslice_WREADY;\n  assign s00_couplers_to_s00_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign s00_couplers_to_s00_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign s00_couplers_to_s00_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign s00_couplers_to_s00_regslice_ARID = S_AXI_arid[5:0];\n  assign s00_couplers_to_s00_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign s00_couplers_to_s00_regslice_ARLOCK = S_AXI_arlock[0];\n  assign s00_couplers_to_s00_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign s00_couplers_to_s00_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign s00_couplers_to_s00_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign s00_couplers_to_s00_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign s00_couplers_to_s00_regslice_ARVALID = S_AXI_arvalid;\n  assign s00_couplers_to_s00_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign s00_couplers_to_s00_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign s00_couplers_to_s00_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign s00_couplers_to_s00_regslice_AWID = S_AXI_awid[5:0];\n  assign s00_couplers_to_s00_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign s00_couplers_to_s00_regslice_AWLOCK = S_AXI_awlock[0];\n  assign s00_couplers_to_s00_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign s00_couplers_to_s00_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign s00_couplers_to_s00_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign s00_couplers_to_s00_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign s00_couplers_to_s00_regslice_AWVALID = S_AXI_awvalid;\n  assign s00_couplers_to_s00_regslice_BREADY = S_AXI_bready;\n  assign s00_couplers_to_s00_regslice_RREADY = S_AXI_rready;\n  assign s00_couplers_to_s00_regslice_WDATA = S_AXI_wdata[511:0];\n  assign s00_couplers_to_s00_regslice_WLAST = S_AXI_wlast;\n  assign s00_couplers_to_s00_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign s00_couplers_to_s00_regslice_WVALID = S_AXI_wvalid;\n  assign s00_regslice_to_s00_couplers_ARREADY = M_AXI_arready;\n  assign s00_regslice_to_s00_couplers_AWREADY = M_AXI_awready;\n  assign s00_regslice_to_s00_couplers_BID = M_AXI_bid[6:0];\n  assign s00_regslice_to_s00_couplers_BRESP = M_AXI_bresp[1:0];\n  assign s00_regslice_to_s00_couplers_BVALID = M_AXI_bvalid;\n  assign s00_regslice_to_s00_couplers_RDATA = M_AXI_rdata[511:0];\n  assign s00_regslice_to_s00_couplers_RID = M_AXI_rid[6:0];\n  assign s00_regslice_to_s00_couplers_RLAST = M_AXI_rlast;\n  assign s00_regslice_to_s00_couplers_RRESP = M_AXI_rresp[1:0];\n  assign s00_regslice_to_s00_couplers_RVALID = M_AXI_rvalid;\n  assign s00_regslice_to_s00_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_s00_regslice_0 s00_regslice\n       (.aclk(S_ACLK_1),\n        .aresetn(S_ARESETN_1),\n        .m_axi_araddr(s00_regslice_to_s00_couplers_ARADDR),\n        .m_axi_arburst(s00_regslice_to_s00_couplers_ARBURST),\n        .m_axi_arcache(s00_regslice_to_s00_couplers_ARCACHE),\n        .m_axi_arid(s00_regslice_to_s00_couplers_ARID),\n        .m_axi_arlen(s00_regslice_to_s00_couplers_ARLEN),\n        .m_axi_arlock(s00_regslice_to_s00_couplers_ARLOCK),\n        .m_axi_arprot(s00_regslice_to_s00_couplers_ARPROT),\n        .m_axi_arqos(s00_regslice_to_s00_couplers_ARQOS),\n        .m_axi_arready(s00_regslice_to_s00_couplers_ARREADY),\n        .m_axi_arsize(s00_regslice_to_s00_couplers_ARSIZE),\n        .m_axi_arvalid(s00_regslice_to_s00_couplers_ARVALID),\n        .m_axi_awaddr(s00_regslice_to_s00_couplers_AWADDR),\n        .m_axi_awburst(s00_regslice_to_s00_couplers_AWBURST),\n        .m_axi_awcache(s00_regslice_to_s00_couplers_AWCACHE),\n        .m_axi_awid(s00_regslice_to_s00_couplers_AWID),\n        .m_axi_awlen(s00_regslice_to_s00_couplers_AWLEN),\n        .m_axi_awlock(s00_regslice_to_s00_couplers_AWLOCK),\n        .m_axi_awprot(s00_regslice_to_s00_couplers_AWPROT),\n        .m_axi_awqos(s00_regslice_to_s00_couplers_AWQOS),\n        .m_axi_awready(s00_regslice_to_s00_couplers_AWREADY),\n        .m_axi_awsize(s00_regslice_to_s00_couplers_AWSIZE),\n        .m_axi_awvalid(s00_regslice_to_s00_couplers_AWVALID),\n        .m_axi_bid(s00_regslice_to_s00_couplers_BID[5:0]),\n        .m_axi_bready(s00_regslice_to_s00_couplers_BREADY),\n        .m_axi_bresp(s00_regslice_to_s00_couplers_BRESP),\n        .m_axi_bvalid(s00_regslice_to_s00_couplers_BVALID),\n        .m_axi_rdata(s00_regslice_to_s00_couplers_RDATA),\n        .m_axi_rid(s00_regslice_to_s00_couplers_RID[5:0]),\n        .m_axi_rlast(s00_regslice_to_s00_couplers_RLAST),\n        .m_axi_rready(s00_regslice_to_s00_couplers_RREADY),\n        .m_axi_rresp(s00_regslice_to_s00_couplers_RRESP),\n        .m_axi_rvalid(s00_regslice_to_s00_couplers_RVALID),\n        .m_axi_wdata(s00_regslice_to_s00_couplers_WDATA),\n        .m_axi_wlast(s00_regslice_to_s00_couplers_WLAST),\n        .m_axi_wready(s00_regslice_to_s00_couplers_WREADY),\n        .m_axi_wstrb(s00_regslice_to_s00_couplers_WSTRB),\n        .m_axi_wvalid(s00_regslice_to_s00_couplers_WVALID),\n        .s_axi_araddr(s00_couplers_to_s00_regslice_ARADDR),\n        .s_axi_arburst(s00_couplers_to_s00_regslice_ARBURST),\n        .s_axi_arcache(s00_couplers_to_s00_regslice_ARCACHE),\n        .s_axi_arid(s00_couplers_to_s00_regslice_ARID),\n        .s_axi_arlen(s00_couplers_to_s00_regslice_ARLEN),\n        .s_axi_arlock(s00_couplers_to_s00_regslice_ARLOCK),\n        .s_axi_arprot(s00_couplers_to_s00_regslice_ARPROT),\n        .s_axi_arqos(s00_couplers_to_s00_regslice_ARQOS),\n        .s_axi_arready(s00_couplers_to_s00_regslice_ARREADY),\n        .s_axi_arregion(s00_couplers_to_s00_regslice_ARREGION),\n        .s_axi_arsize(s00_couplers_to_s00_regslice_ARSIZE),\n        .s_axi_arvalid(s00_couplers_to_s00_regslice_ARVALID),\n        .s_axi_awaddr(s00_couplers_to_s00_regslice_AWADDR),\n        .s_axi_awburst(s00_couplers_to_s00_regslice_AWBURST),\n        .s_axi_awcache(s00_couplers_to_s00_regslice_AWCACHE),\n        .s_axi_awid(s00_couplers_to_s00_regslice_AWID),\n        .s_axi_awlen(s00_couplers_to_s00_regslice_AWLEN),\n        .s_axi_awlock(s00_couplers_to_s00_regslice_AWLOCK),\n        .s_axi_awprot(s00_couplers_to_s00_regslice_AWPROT),\n        .s_axi_awqos(s00_couplers_to_s00_regslice_AWQOS),\n        .s_axi_awready(s00_couplers_to_s00_regslice_AWREADY),\n        .s_axi_awregion(s00_couplers_to_s00_regslice_AWREGION),\n        .s_axi_awsize(s00_couplers_to_s00_regslice_AWSIZE),\n        .s_axi_awvalid(s00_couplers_to_s00_regslice_AWVALID),\n        .s_axi_bid(s00_couplers_to_s00_regslice_BID),\n        .s_axi_bready(s00_couplers_to_s00_regslice_BREADY),\n        .s_axi_bresp(s00_couplers_to_s00_regslice_BRESP),\n        .s_axi_bvalid(s00_couplers_to_s00_regslice_BVALID),\n        .s_axi_rdata(s00_couplers_to_s00_regslice_RDATA),\n        .s_axi_rid(s00_couplers_to_s00_regslice_RID),\n        .s_axi_rlast(s00_couplers_to_s00_regslice_RLAST),\n        .s_axi_rready(s00_couplers_to_s00_regslice_RREADY),\n        .s_axi_rresp(s00_couplers_to_s00_regslice_RRESP),\n        .s_axi_rvalid(s00_couplers_to_s00_regslice_RVALID),\n        .s_axi_wdata(s00_couplers_to_s00_regslice_WDATA),\n        .s_axi_wlast(s00_couplers_to_s00_regslice_WLAST),\n        .s_axi_wready(s00_couplers_to_s00_regslice_WREADY),\n        .s_axi_wstrb(s00_couplers_to_s00_regslice_WSTRB),\n        .s_axi_wvalid(s00_couplers_to_s00_regslice_WVALID));\nendmodule\n\nmodule s01_couplers_imp_GSTXQ8\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [5:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [5:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [5:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [5:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [5:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [5:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire S_ACLK_1;\n  wire S_ARESETN_1;\n  wire [63:0]s01_couplers_to_s01_regslice_ARADDR;\n  wire [1:0]s01_couplers_to_s01_regslice_ARBURST;\n  wire [3:0]s01_couplers_to_s01_regslice_ARCACHE;\n  wire [5:0]s01_couplers_to_s01_regslice_ARID;\n  wire [7:0]s01_couplers_to_s01_regslice_ARLEN;\n  wire [0:0]s01_couplers_to_s01_regslice_ARLOCK;\n  wire [2:0]s01_couplers_to_s01_regslice_ARPROT;\n  wire [3:0]s01_couplers_to_s01_regslice_ARQOS;\n  wire s01_couplers_to_s01_regslice_ARREADY;\n  wire [3:0]s01_couplers_to_s01_regslice_ARREGION;\n  wire [2:0]s01_couplers_to_s01_regslice_ARSIZE;\n  wire s01_couplers_to_s01_regslice_ARVALID;\n  wire [63:0]s01_couplers_to_s01_regslice_AWADDR;\n  wire [1:0]s01_couplers_to_s01_regslice_AWBURST;\n  wire [3:0]s01_couplers_to_s01_regslice_AWCACHE;\n  wire [5:0]s01_couplers_to_s01_regslice_AWID;\n  wire [7:0]s01_couplers_to_s01_regslice_AWLEN;\n  wire [0:0]s01_couplers_to_s01_regslice_AWLOCK;\n  wire [2:0]s01_couplers_to_s01_regslice_AWPROT;\n  wire [3:0]s01_couplers_to_s01_regslice_AWQOS;\n  wire s01_couplers_to_s01_regslice_AWREADY;\n  wire [3:0]s01_couplers_to_s01_regslice_AWREGION;\n  wire [2:0]s01_couplers_to_s01_regslice_AWSIZE;\n  wire s01_couplers_to_s01_regslice_AWVALID;\n  wire [5:0]s01_couplers_to_s01_regslice_BID;\n  wire s01_couplers_to_s01_regslice_BREADY;\n  wire [1:0]s01_couplers_to_s01_regslice_BRESP;\n  wire s01_couplers_to_s01_regslice_BVALID;\n  wire [511:0]s01_couplers_to_s01_regslice_RDATA;\n  wire [5:0]s01_couplers_to_s01_regslice_RID;\n  wire s01_couplers_to_s01_regslice_RLAST;\n  wire s01_couplers_to_s01_regslice_RREADY;\n  wire [1:0]s01_couplers_to_s01_regslice_RRESP;\n  wire s01_couplers_to_s01_regslice_RVALID;\n  wire [511:0]s01_couplers_to_s01_regslice_WDATA;\n  wire s01_couplers_to_s01_regslice_WLAST;\n  wire s01_couplers_to_s01_regslice_WREADY;\n  wire [63:0]s01_couplers_to_s01_regslice_WSTRB;\n  wire s01_couplers_to_s01_regslice_WVALID;\n  wire [63:0]s01_regslice_to_s01_couplers_ARADDR;\n  wire [1:0]s01_regslice_to_s01_couplers_ARBURST;\n  wire [3:0]s01_regslice_to_s01_couplers_ARCACHE;\n  wire [5:0]s01_regslice_to_s01_couplers_ARID;\n  wire [7:0]s01_regslice_to_s01_couplers_ARLEN;\n  wire [0:0]s01_regslice_to_s01_couplers_ARLOCK;\n  wire [2:0]s01_regslice_to_s01_couplers_ARPROT;\n  wire [3:0]s01_regslice_to_s01_couplers_ARQOS;\n  wire s01_regslice_to_s01_couplers_ARREADY;\n  wire [2:0]s01_regslice_to_s01_couplers_ARSIZE;\n  wire s01_regslice_to_s01_couplers_ARVALID;\n  wire [63:0]s01_regslice_to_s01_couplers_AWADDR;\n  wire [1:0]s01_regslice_to_s01_couplers_AWBURST;\n  wire [3:0]s01_regslice_to_s01_couplers_AWCACHE;\n  wire [5:0]s01_regslice_to_s01_couplers_AWID;\n  wire [7:0]s01_regslice_to_s01_couplers_AWLEN;\n  wire [0:0]s01_regslice_to_s01_couplers_AWLOCK;\n  wire [2:0]s01_regslice_to_s01_couplers_AWPROT;\n  wire [3:0]s01_regslice_to_s01_couplers_AWQOS;\n  wire s01_regslice_to_s01_couplers_AWREADY;\n  wire [2:0]s01_regslice_to_s01_couplers_AWSIZE;\n  wire s01_regslice_to_s01_couplers_AWVALID;\n  wire [6:0]s01_regslice_to_s01_couplers_BID;\n  wire s01_regslice_to_s01_couplers_BREADY;\n  wire [1:0]s01_regslice_to_s01_couplers_BRESP;\n  wire s01_regslice_to_s01_couplers_BVALID;\n  wire [511:0]s01_regslice_to_s01_couplers_RDATA;\n  wire [6:0]s01_regslice_to_s01_couplers_RID;\n  wire s01_regslice_to_s01_couplers_RLAST;\n  wire s01_regslice_to_s01_couplers_RREADY;\n  wire [1:0]s01_regslice_to_s01_couplers_RRESP;\n  wire s01_regslice_to_s01_couplers_RVALID;\n  wire [511:0]s01_regslice_to_s01_couplers_WDATA;\n  wire s01_regslice_to_s01_couplers_WLAST;\n  wire s01_regslice_to_s01_couplers_WREADY;\n  wire [63:0]s01_regslice_to_s01_couplers_WSTRB;\n  wire s01_regslice_to_s01_couplers_WVALID;\n\n  assign M_AXI_araddr[63:0] = s01_regslice_to_s01_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = s01_regslice_to_s01_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = s01_regslice_to_s01_couplers_ARCACHE;\n  assign M_AXI_arid[5:0] = s01_regslice_to_s01_couplers_ARID;\n  assign M_AXI_arlen[7:0] = s01_regslice_to_s01_couplers_ARLEN;\n  assign M_AXI_arlock[0] = s01_regslice_to_s01_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = s01_regslice_to_s01_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = s01_regslice_to_s01_couplers_ARQOS;\n  assign M_AXI_arsize[2:0] = s01_regslice_to_s01_couplers_ARSIZE;\n  assign M_AXI_arvalid = s01_regslice_to_s01_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = s01_regslice_to_s01_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = s01_regslice_to_s01_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = s01_regslice_to_s01_couplers_AWCACHE;\n  assign M_AXI_awid[5:0] = s01_regslice_to_s01_couplers_AWID;\n  assign M_AXI_awlen[7:0] = s01_regslice_to_s01_couplers_AWLEN;\n  assign M_AXI_awlock[0] = s01_regslice_to_s01_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = s01_regslice_to_s01_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = s01_regslice_to_s01_couplers_AWQOS;\n  assign M_AXI_awsize[2:0] = s01_regslice_to_s01_couplers_AWSIZE;\n  assign M_AXI_awvalid = s01_regslice_to_s01_couplers_AWVALID;\n  assign M_AXI_bready = s01_regslice_to_s01_couplers_BREADY;\n  assign M_AXI_rready = s01_regslice_to_s01_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = s01_regslice_to_s01_couplers_WDATA;\n  assign M_AXI_wlast = s01_regslice_to_s01_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = s01_regslice_to_s01_couplers_WSTRB;\n  assign M_AXI_wvalid = s01_regslice_to_s01_couplers_WVALID;\n  assign S_ACLK_1 = S_ACLK;\n  assign S_ARESETN_1 = S_ARESETN;\n  assign S_AXI_arready = s01_couplers_to_s01_regslice_ARREADY;\n  assign S_AXI_awready = s01_couplers_to_s01_regslice_AWREADY;\n  assign S_AXI_bid[5:0] = s01_couplers_to_s01_regslice_BID;\n  assign S_AXI_bresp[1:0] = s01_couplers_to_s01_regslice_BRESP;\n  assign S_AXI_bvalid = s01_couplers_to_s01_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = s01_couplers_to_s01_regslice_RDATA;\n  assign S_AXI_rid[5:0] = s01_couplers_to_s01_regslice_RID;\n  assign S_AXI_rlast = s01_couplers_to_s01_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = s01_couplers_to_s01_regslice_RRESP;\n  assign S_AXI_rvalid = s01_couplers_to_s01_regslice_RVALID;\n  assign S_AXI_wready = s01_couplers_to_s01_regslice_WREADY;\n  assign s01_couplers_to_s01_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign s01_couplers_to_s01_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign s01_couplers_to_s01_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign s01_couplers_to_s01_regslice_ARID = S_AXI_arid[5:0];\n  assign s01_couplers_to_s01_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign s01_couplers_to_s01_regslice_ARLOCK = S_AXI_arlock[0];\n  assign s01_couplers_to_s01_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign s01_couplers_to_s01_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign s01_couplers_to_s01_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign s01_couplers_to_s01_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign s01_couplers_to_s01_regslice_ARVALID = S_AXI_arvalid;\n  assign s01_couplers_to_s01_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign s01_couplers_to_s01_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign s01_couplers_to_s01_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign s01_couplers_to_s01_regslice_AWID = S_AXI_awid[5:0];\n  assign s01_couplers_to_s01_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign s01_couplers_to_s01_regslice_AWLOCK = S_AXI_awlock[0];\n  assign s01_couplers_to_s01_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign s01_couplers_to_s01_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign s01_couplers_to_s01_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign s01_couplers_to_s01_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign s01_couplers_to_s01_regslice_AWVALID = S_AXI_awvalid;\n  assign s01_couplers_to_s01_regslice_BREADY = S_AXI_bready;\n  assign s01_couplers_to_s01_regslice_RREADY = S_AXI_rready;\n  assign s01_couplers_to_s01_regslice_WDATA = S_AXI_wdata[511:0];\n  assign s01_couplers_to_s01_regslice_WLAST = S_AXI_wlast;\n  assign s01_couplers_to_s01_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign s01_couplers_to_s01_regslice_WVALID = S_AXI_wvalid;\n  assign s01_regslice_to_s01_couplers_ARREADY = M_AXI_arready;\n  assign s01_regslice_to_s01_couplers_AWREADY = M_AXI_awready;\n  assign s01_regslice_to_s01_couplers_BID = M_AXI_bid[6:0];\n  assign s01_regslice_to_s01_couplers_BRESP = M_AXI_bresp[1:0];\n  assign s01_regslice_to_s01_couplers_BVALID = M_AXI_bvalid;\n  assign s01_regslice_to_s01_couplers_RDATA = M_AXI_rdata[511:0];\n  assign s01_regslice_to_s01_couplers_RID = M_AXI_rid[6:0];\n  assign s01_regslice_to_s01_couplers_RLAST = M_AXI_rlast;\n  assign s01_regslice_to_s01_couplers_RRESP = M_AXI_rresp[1:0];\n  assign s01_regslice_to_s01_couplers_RVALID = M_AXI_rvalid;\n  assign s01_regslice_to_s01_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_s01_regslice_0 s01_regslice\n       (.aclk(S_ACLK_1),\n        .aresetn(S_ARESETN_1),\n        .m_axi_araddr(s01_regslice_to_s01_couplers_ARADDR),\n        .m_axi_arburst(s01_regslice_to_s01_couplers_ARBURST),\n        .m_axi_arcache(s01_regslice_to_s01_couplers_ARCACHE),\n        .m_axi_arid(s01_regslice_to_s01_couplers_ARID),\n        .m_axi_arlen(s01_regslice_to_s01_couplers_ARLEN),\n        .m_axi_arlock(s01_regslice_to_s01_couplers_ARLOCK),\n        .m_axi_arprot(s01_regslice_to_s01_couplers_ARPROT),\n        .m_axi_arqos(s01_regslice_to_s01_couplers_ARQOS),\n        .m_axi_arready(s01_regslice_to_s01_couplers_ARREADY),\n        .m_axi_arsize(s01_regslice_to_s01_couplers_ARSIZE),\n        .m_axi_arvalid(s01_regslice_to_s01_couplers_ARVALID),\n        .m_axi_awaddr(s01_regslice_to_s01_couplers_AWADDR),\n        .m_axi_awburst(s01_regslice_to_s01_couplers_AWBURST),\n        .m_axi_awcache(s01_regslice_to_s01_couplers_AWCACHE),\n        .m_axi_awid(s01_regslice_to_s01_couplers_AWID),\n        .m_axi_awlen(s01_regslice_to_s01_couplers_AWLEN),\n        .m_axi_awlock(s01_regslice_to_s01_couplers_AWLOCK),\n        .m_axi_awprot(s01_regslice_to_s01_couplers_AWPROT),\n        .m_axi_awqos(s01_regslice_to_s01_couplers_AWQOS),\n        .m_axi_awready(s01_regslice_to_s01_couplers_AWREADY),\n        .m_axi_awsize(s01_regslice_to_s01_couplers_AWSIZE),\n        .m_axi_awvalid(s01_regslice_to_s01_couplers_AWVALID),\n        .m_axi_bid(s01_regslice_to_s01_couplers_BID[5:0]),\n        .m_axi_bready(s01_regslice_to_s01_couplers_BREADY),\n        .m_axi_bresp(s01_regslice_to_s01_couplers_BRESP),\n        .m_axi_bvalid(s01_regslice_to_s01_couplers_BVALID),\n        .m_axi_rdata(s01_regslice_to_s01_couplers_RDATA),\n        .m_axi_rid(s01_regslice_to_s01_couplers_RID[5:0]),\n        .m_axi_rlast(s01_regslice_to_s01_couplers_RLAST),\n        .m_axi_rready(s01_regslice_to_s01_couplers_RREADY),\n        .m_axi_rresp(s01_regslice_to_s01_couplers_RRESP),\n        .m_axi_rvalid(s01_regslice_to_s01_couplers_RVALID),\n        .m_axi_wdata(s01_regslice_to_s01_couplers_WDATA),\n        .m_axi_wlast(s01_regslice_to_s01_couplers_WLAST),\n        .m_axi_wready(s01_regslice_to_s01_couplers_WREADY),\n        .m_axi_wstrb(s01_regslice_to_s01_couplers_WSTRB),\n        .m_axi_wvalid(s01_regslice_to_s01_couplers_WVALID),\n        .s_axi_araddr(s01_couplers_to_s01_regslice_ARADDR),\n        .s_axi_arburst(s01_couplers_to_s01_regslice_ARBURST),\n        .s_axi_arcache(s01_couplers_to_s01_regslice_ARCACHE),\n        .s_axi_arid(s01_couplers_to_s01_regslice_ARID),\n        .s_axi_arlen(s01_couplers_to_s01_regslice_ARLEN),\n        .s_axi_arlock(s01_couplers_to_s01_regslice_ARLOCK),\n        .s_axi_arprot(s01_couplers_to_s01_regslice_ARPROT),\n        .s_axi_arqos(s01_couplers_to_s01_regslice_ARQOS),\n        .s_axi_arready(s01_couplers_to_s01_regslice_ARREADY),\n        .s_axi_arregion(s01_couplers_to_s01_regslice_ARREGION),\n        .s_axi_arsize(s01_couplers_to_s01_regslice_ARSIZE),\n        .s_axi_arvalid(s01_couplers_to_s01_regslice_ARVALID),\n        .s_axi_awaddr(s01_couplers_to_s01_regslice_AWADDR),\n        .s_axi_awburst(s01_couplers_to_s01_regslice_AWBURST),\n        .s_axi_awcache(s01_couplers_to_s01_regslice_AWCACHE),\n        .s_axi_awid(s01_couplers_to_s01_regslice_AWID),\n        .s_axi_awlen(s01_couplers_to_s01_regslice_AWLEN),\n        .s_axi_awlock(s01_couplers_to_s01_regslice_AWLOCK),\n        .s_axi_awprot(s01_couplers_to_s01_regslice_AWPROT),\n        .s_axi_awqos(s01_couplers_to_s01_regslice_AWQOS),\n        .s_axi_awready(s01_couplers_to_s01_regslice_AWREADY),\n        .s_axi_awregion(s01_couplers_to_s01_regslice_AWREGION),\n        .s_axi_awsize(s01_couplers_to_s01_regslice_AWSIZE),\n        .s_axi_awvalid(s01_couplers_to_s01_regslice_AWVALID),\n        .s_axi_bid(s01_couplers_to_s01_regslice_BID),\n        .s_axi_bready(s01_couplers_to_s01_regslice_BREADY),\n        .s_axi_bresp(s01_couplers_to_s01_regslice_BRESP),\n        .s_axi_bvalid(s01_couplers_to_s01_regslice_BVALID),\n        .s_axi_rdata(s01_couplers_to_s01_regslice_RDATA),\n        .s_axi_rid(s01_couplers_to_s01_regslice_RID),\n        .s_axi_rlast(s01_couplers_to_s01_regslice_RLAST),\n        .s_axi_rready(s01_couplers_to_s01_regslice_RREADY),\n        .s_axi_rresp(s01_couplers_to_s01_regslice_RRESP),\n        .s_axi_rvalid(s01_couplers_to_s01_regslice_RVALID),\n        .s_axi_wdata(s01_couplers_to_s01_regslice_WDATA),\n        .s_axi_wlast(s01_couplers_to_s01_regslice_WLAST),\n        .s_axi_wready(s01_couplers_to_s01_regslice_WREADY),\n        .s_axi_wstrb(s01_couplers_to_s01_regslice_WSTRB),\n        .s_axi_wvalid(s01_couplers_to_s01_regslice_WVALID));\nendmodule\n", "num_lines": 5426}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sync_clock_converter\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axic_sync_clock_converter # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_FAMILY     = \"virtex6\",\n  parameter integer C_PAYLOAD_WIDTH = 32,\n  parameter integer C_S_ACLK_RATIO = 1,\n  parameter integer C_M_ACLK_RATIO = 1 ,\n  parameter integer C_MODE = 0  // 0 = light-weight (1-deep); 1 = fully-pipelined (2-deep)\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input wire                    SAMPLE_CYCLE_EARLY,\n  input wire                    SAMPLE_CYCLE,\n  // Slave side\n  input  wire                        S_ACLK,\n  input  wire                        S_ARESETN,\n  input  wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD,\n  input  wire                        S_VALID,\n  output wire                        S_READY,\n\n  // Master side\n  input  wire                        M_ACLK,\n  input  wire                        M_ARESETN,\n  output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD,\n  output wire                        M_VALID,\n  input  wire                        M_READY\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam [1:0] ZERO = 2'b10;\nlocalparam [1:0] ONE  = 2'b11;\nlocalparam [1:0] TWO  = 2'b01;\nlocalparam [1:0] INIT = 2'b00;\nlocalparam integer P_LIGHT_WT = 0;\nlocalparam integer P_FULLY_REG = 1;\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\ngenerate\n  if (C_S_ACLK_RATIO == C_M_ACLK_RATIO) begin : gen_passthru\n    assign M_PAYLOAD = S_PAYLOAD;\n    assign M_VALID   = S_VALID;\n    assign S_READY   = M_READY;      \n  end else begin : gen_sync_clock_converter\n    wire s_sample_cycle;\n    wire s_sample_cycle_early;\n    wire m_sample_cycle;\n    wire m_sample_cycle_early;\n\n    wire slow_aclk;\n    wire slow_areset;\n    wire s_areset_r;\n    wire m_areset_r;\n   \n    reg  s_tready_r = 1'b0; \n    wire s_tready_ns; \n    reg  m_tvalid_r = 1'b0; \n    wire m_tvalid_ns; \n    reg  [C_PAYLOAD_WIDTH-1:0] m_tpayload_r;\n    reg  [C_PAYLOAD_WIDTH-1:0] m_tstorage_r;\n    wire [C_PAYLOAD_WIDTH-1:0] m_tpayload_ns; \n    wire [C_PAYLOAD_WIDTH-1:0] m_tstorage_ns; \n    reg  m_tready_hold = 1'b0;\n    wire m_tready_sample;\n    wire load_tpayload;\n    wire load_tstorage;\n    wire load_tpayload_from_tstorage;\n    reg [1:0] state = INIT;\n    reg [1:0] next_state;\n    \n    reg s_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge S_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        s_aresetn_r <= 1'b0;\n      end else begin\n        s_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign s_areset_r = ~s_aresetn_r;\n\n    reg m_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge M_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        m_aresetn_r <= 1'b0;\n      end else begin\n        m_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign m_areset_r = ~m_aresetn_r;\n\n    if (C_S_ACLK_RATIO > C_M_ACLK_RATIO) begin : gen_slowclk_mi\n      assign slow_aclk = M_ACLK;\n    end else begin : gen_slowclk_si\n      assign slow_aclk = S_ACLK;\n    end\n  \n    assign slow_areset = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? m_areset_r : s_areset_r;\n    assign s_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE_EARLY : 1'b1;\n    assign s_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE : 1'b1;\n    assign m_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE_EARLY;\n    assign m_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE;\n\n    // Output flop for S_READY, value is encoded into state machine.\n    assign s_tready_ns = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? state[1] & (state != INIT) : next_state[1];\n\n    always @(posedge S_ACLK) begin \n      if (s_areset_r) begin\n        s_tready_r <= 1'b0;\n      end\n      else begin\n        s_tready_r <= s_sample_cycle_early ? s_tready_ns : 1'b0;\n      end\n    end\n\n    assign S_READY = s_tready_r;\n\n    // Output flop for M_VALID\n    assign m_tvalid_ns = next_state[0];\n\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tvalid_r <= 1'b0;\n      end\n      else begin\n        m_tvalid_r <= m_sample_cycle ? m_tvalid_ns : m_tvalid_r & ~M_READY;\n      end\n    end\n\n    assign M_VALID = m_tvalid_r;\n\n    // Hold register for M_READY when M_ACLK is fast.\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tready_hold <= 1'b0;\n      end\n      else begin\n        m_tready_hold <= m_sample_cycle ? 1'b0 : m_tready_sample;\n      end\n    end\n\n    assign m_tready_sample = (M_READY ) | m_tready_hold;\n    // Output/storage flops for PAYLOAD\n    assign m_tpayload_ns = ~load_tpayload ? m_tpayload_r :\n                           load_tpayload_from_tstorage ? m_tstorage_r : \n                           S_PAYLOAD;\n\n    assign m_tstorage_ns = C_MODE ? (load_tstorage ? S_PAYLOAD : m_tstorage_r) : 0;\n\n    always @(posedge slow_aclk) begin \n      m_tpayload_r <= m_tpayload_ns;\n      m_tstorage_r <= C_MODE ? m_tstorage_ns : 0;\n    end\n\n    assign M_PAYLOAD = m_tpayload_r;\n\n    // load logic\n    assign load_tstorage = C_MODE && (state != TWO);\n    assign load_tpayload = m_tready_sample || (state == ZERO);\n    assign load_tpayload_from_tstorage = C_MODE && (state == TWO) && m_tready_sample;\n    \n    // State machine\n    always @(posedge slow_aclk) begin \n      state <= next_state;\n    end\n\n    always @* begin \n      if (slow_areset) begin \n        next_state = INIT;\n      end else begin\n        case (state)\n          INIT: begin\n            next_state = ZERO;\n          end\n          // No transaction stored locally\n          ZERO: begin\n            if (S_VALID) begin\n              next_state = C_MODE ? ONE : TWO; // Push from empty\n            end\n            else begin\n              next_state = ZERO;\n            end\n          end\n\n          // One transaction stored locally\n          ONE: begin\n            if (C_MODE == 0) begin\n              next_state = TWO;  // State ONE is inaccessible when C_MODE=0\n            end \n            else if (m_tready_sample & ~S_VALID) begin \n              next_state = ZERO; // Read out one so move to ZERO\n            end\n            else if (~m_tready_sample & S_VALID) begin\n              next_state = TWO;  // Got another one so move to TWO\n            end\n            else begin\n              next_state = ONE;\n            end\n          end\n\n          // Storage registers full\n          TWO: begin \n            if (m_tready_sample) begin\n              next_state = C_MODE ? ONE : ZERO; // Pop from full\n            end\n            else begin\n              next_state = TWO;\n            end\n          end\n        endcase // case (state)\n      end\n    end\n  end // gen_sync_clock_converter\n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sample_cycle_ratio\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axic_sample_cycle_ratio # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_RATIO = 2 // Must be > 0\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    SLOW_ACLK,\n  input  wire                    FAST_ACLK,\n\n  output wire                    SAMPLE_CYCLE_EARLY,\n  output wire                    SAMPLE_CYCLE\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam P_DELAY = C_RATIO > 2 ? C_RATIO-1 : C_RATIO-1; \n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_aclk_div2 = 1'b0;\nreg                posedge_finder_first = 1'b0;\nreg                posedge_finder_second = 1'b0;\nwire               first_edge;\nwire               second_edge;\nwire               any_edge;\nreg  [P_DELAY-1:0] sample_cycle_d = {P_DELAY{1'b0}};\n(* shreg_extract = \"no\" *) reg                sample_cycle_r = 1'b0;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\ngenerate\n  if (C_RATIO == 1) begin : gen_always_sample\n    assign SAMPLE_CYCLE_EARLY = 1'b1;\n    assign SAMPLE_CYCLE = 1'b1;\n  end\n  else begin : gen_sample_cycle\n    genvar i;\n    always @(posedge SLOW_ACLK) begin \n      slow_aclk_div2 <= ~slow_aclk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_aclk_div2 onto faster clock\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_first <= slow_aclk_div2;\n    end\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_second <= ~slow_aclk_div2;\n    end\n\n    assign first_edge = slow_aclk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;\n    assign any_edge = first_edge | second_edge;\n   \n    // delay the posedge alignment by C_RATIO - 1 to set the sample cycle as\n    // the clock one cycle before the posedge.\n    for (i = P_DELAY-1; i > 0; i = i - 1) begin : gen_delay\n      always @(posedge FAST_ACLK) begin\n        if (i == P_DELAY-1) begin\n          sample_cycle_d[i-1] <= any_edge;\n        end else begin\n          sample_cycle_d[i-1] <= sample_cycle_d[i];\n        end\n      end\n    end\n\n    always @(posedge FAST_ACLK) begin \n      sample_cycle_r <= (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    end\n    assign SAMPLE_CYCLE_EARLY = (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    assign SAMPLE_CYCLE = sample_cycle_r;\n  end\nendgenerate\n\nendmodule // axisc_sample_cycle_ratio\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2010 - 2016 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and\n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Clock converter module\n//   Asynchronous clock converter when asynchronous M:N conversion\n//   Bypass when synchronous and ratio between S and M clock is 1:1\n//   Synchronous clock converter (S:M or M:S must be integer ratio)\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_clock_conv\n//     fifo_generator\n//     axic_sync_clock_converter\n//       axic_sample_cycle_ratio\n//\n// PROTECTED NAMES:\n//   Instance names \"asyncfifo_*\" are pattern-matched in core-level UCF.\n//   Signal names \"*_resync\" are pattern-matched in core-level UCF.\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_lite_async #(\n  parameter integer C_DEST_SYNC_FF = 3,\n  parameter integer C_SRC_SYNC_FF  = 3,\n  parameter integer C_WIDTH        = 1\n) (\n  input wire                s_aclk,\n  input wire                m_aclk,\n  input wire                s_aresetn,\n  input wire                m_aresetn,\n  input wire                s_valid,\n  output wire                s_ready,\n  input wire [C_WIDTH-1:0]  s_payld,\n  output wire                m_valid,\n  input wire                m_ready,\n  output wire [C_WIDTH-1:0] m_payld\n);\n\nreg [C_SRC_SYNC_FF:0] s_areset_dly = {C_SRC_SYNC_FF+1{1'b0}};\nreg [C_DEST_SYNC_FF:0] m_areset_dly = {C_DEST_SYNC_FF+1{1'b0}};\nreg                s_ready_i = 1'b0;\nreg                m_valid_i = 1'b0;\nreg   src_send = 1'b0;\nreg   dest_ack = 1'b0;\nwire  src_rcv;\nwire  dest_req;\n\nassign s_ready = s_ready_i;\nassign m_valid = m_valid_i;\n\nlocalparam SRC_IDLE           = 2'b00;\nlocalparam SRC_DRV_SEND       = 2'b01;\nlocalparam SRC_WAIT_RCV_DONE  = 2'b10;\nreg [1:0] src_state = SRC_IDLE;\n\nalways @(posedge s_aclk) begin\n  s_areset_dly <= {C_SRC_SYNC_FF+1{~s_aresetn}} | (s_areset_dly<<1);\n  if (s_areset_dly[C_SRC_SYNC_FF]) begin\n    s_ready_i <= 1'b0;\n    src_send <= 1'b0;\n    src_state <= SRC_IDLE;\n  end else begin\n    case (src_state)\n      SRC_IDLE: begin\n        if (s_valid) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end\n      end\n      SRC_DRV_SEND: begin\n        if (src_rcv) begin\n          s_ready_i <= 1'b1;\n          src_send <= 1'b0;\n          src_state <= SRC_WAIT_RCV_DONE;\n        end\n      end\n      SRC_WAIT_RCV_DONE: begin\n        s_ready_i <= 1'b0;\n        if (s_valid & !src_rcv) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end else if (!src_rcv) begin\n          src_state <= SRC_IDLE;\n        end\n      end\n      default: begin\n        s_ready_i <= 1'b0;\n        src_send <= 1'b0;\n        src_state <= SRC_IDLE;\n      end\n    endcase\n  end\nend\n\nlocalparam DEST_IDLE           = 2'b00;\nlocalparam DEST_DRV_VALID      = 2'b01;\nlocalparam DEST_DRV_ACK        = 2'b10;\nreg [1:0] dest_state = DEST_IDLE;\n\nalways @(posedge m_aclk) begin\n  m_areset_dly <= {C_DEST_SYNC_FF+1{~m_aresetn}} | (m_areset_dly<<1);\n  if (m_areset_dly[C_DEST_SYNC_FF]) begin\n    m_valid_i <= 1'b0;\n    dest_ack <= 1'b0;\n    dest_state <= DEST_IDLE;\n  end else begin\n    case (dest_state)\n      DEST_IDLE: begin\n        if (dest_req) begin\n          dest_state <= DEST_DRV_VALID;\n          m_valid_i <= 1'b1;\n        end else begin\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b0;\n        end\n      end\n      DEST_DRV_VALID: begin\n        if (m_ready & m_valid_i) begin\n          dest_state <= DEST_DRV_ACK;\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b1;\n        end\n      end\n      DEST_DRV_ACK: begin\n        if (!dest_req) begin\n          dest_state <= DEST_IDLE;\n          dest_ack <= 1'b0;\n        end\n      end\n      default: begin\n        m_valid_i <= 1'b0;\n        dest_ack <= 1'b0;\n        dest_state <= DEST_IDLE;\n      end\n    endcase\n  end\nend\n\nxpm_cdc_handshake #(\n  .DEST_SYNC_FF   (C_DEST_SYNC_FF),\n  .SRC_SYNC_FF    (C_SRC_SYNC_FF),\n  .WIDTH          (C_WIDTH)\n) handshake (\n  .src_clk  (s_aclk),\n  .src_in   (s_payld),\n  .src_send (src_send),\n  .src_rcv  (src_rcv),\n  .dest_clk (m_aclk),\n  .dest_out (m_payld),\n  .dest_req (dest_req),\n  .dest_ack (dest_ack)\n);\n\nendmodule\n\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axi_clock_converter #\n  (parameter         C_FAMILY = \"virtex7\",\n   parameter integer C_AXI_ID_WIDTH = 5,                    // Width of all ID signals on SI and MI side.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ADDR_WIDTH = 32,                 // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and\n                                                            // m_axi_araddr.\n                                                            // Range: 32.\n   parameter integer C_AXI_DATA_WIDTH = 32,       // Width of WDATA and RDATA (either side).\n                                                            // Format: Bit32;\n                                                            // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.\n   parameter integer C_S_AXI_ACLK_RATIO = 1,     // Clock frequency ratio of SI w.r.t. MI.\n   parameter integer C_M_AXI_ACLK_RATIO = 1,     // (Slowest of all clock inputs should have ratio=1.)\n                                                            // S:M or M:S must be integer ratio.\n                                                            // Format: Bit32; Range: >='h00000001.\n   parameter integer C_AXI_IS_ACLK_ASYNC = 1,            // Indicates whether S and M clocks are asynchronous.\n                                                            // FUTURE FEATURE\n                                                            // Format: Bit1. Range = 1'b0.\n   parameter integer C_AXI_PROTOCOL = 0,         // Protocol of this SI/MI slot.\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS  = 1,      // 1 = Propagate all USER signals, 0 = Do not propagate.\n   parameter integer C_AXI_AWUSER_WIDTH = 1,                // Width of AWUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ARUSER_WIDTH = 1,                // Width of ARUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_WUSER_WIDTH = 1,                 // Width of WUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_RUSER_WIDTH = 1,                 // Width of RUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_BUSER_WIDTH = 1,                 // Width of BUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,              // Implement AXI write channels\n   parameter integer C_AXI_SUPPORTS_READ = 1,               // Implement AXI read channels\n   parameter integer C_SYNCHRONIZER_STAGE = 3\n  )\n\n  (\n   // Slave Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n   input  wire [4-1:0]                    s_axi_awcache,\n   input  wire [3-1:0]                    s_axi_awprot,\n   input  wire [4-1:0]                    s_axi_awregion,\n   input  wire [4-1:0]                    s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0]   s_axi_awuser,\n   input  wire                            s_axi_awvalid,\n   output wire                            s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n   input  wire                            s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]    s_axi_wuser,\n   input  wire                            s_axi_wvalid,\n   output wire                            s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_bid,\n   output wire [2-1:0]                    s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0]    s_axi_buser,\n   output wire                            s_axi_bvalid,\n   input  wire                            s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n   input  wire [3-1:0]                    s_axi_arsize,\n   input  wire [2-1:0]                    s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n   input  wire [4-1:0]                    s_axi_arcache,\n   input  wire [3-1:0]                    s_axi_arprot,\n   input  wire [4-1:0]                    s_axi_arregion,\n   input  wire [4-1:0]                    s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0]   s_axi_aruser,\n   input  wire                            s_axi_arvalid,\n   output wire                            s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n   output wire [2-1:0]                    s_axi_rresp,\n   output wire                            s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0]    s_axi_ruser,\n   output wire                            s_axi_rvalid,\n   input  wire                            s_axi_rready,\n\n   // Master Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aresetn,\n\n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n   output wire [3-1:0]                    m_axi_awsize,\n   output wire [2-1:0]                    m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n   output wire [4-1:0]                    m_axi_awcache,\n   output wire [3-1:0]                    m_axi_awprot,\n   output wire [4-1:0]                    m_axi_awregion,\n   output wire [4-1:0]                    m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0]   m_axi_awuser,\n   output wire                            m_axi_awvalid,\n   input  wire                            m_axi_awready,\n\n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0]   m_axi_wstrb,\n   output wire                            m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]    m_axi_wuser,\n   output wire                            m_axi_wvalid,\n   input  wire                            m_axi_wready,\n\n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_bid,\n   input  wire [2-1:0]                    m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0]    m_axi_buser,\n   input  wire                            m_axi_bvalid,\n   output wire                            m_axi_bready,\n\n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n   output wire [3-1:0]                    m_axi_arsize,\n   output wire [2-1:0]                    m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n   output wire [4-1:0]                    m_axi_arcache,\n   output wire [3-1:0]                    m_axi_arprot,\n   output wire [4-1:0]                    m_axi_arregion,\n   output wire [4-1:0]                    m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0]   m_axi_aruser,\n   output wire                            m_axi_arvalid,\n   input  wire                            m_axi_arready,\n\n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     m_axi_rdata,\n   input  wire [2-1:0]                    m_axi_rresp,\n   input  wire                            m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0]    m_axi_ruser,\n   input  wire                            m_axi_rvalid,\n   output wire                            m_axi_rready);\n\n  localparam integer P_AXI4 = 0;\n  localparam integer P_AXI3 = 1;\n  localparam integer P_AXILITE = 2;\n  localparam integer P_LIGHT_WT = 0;\n  localparam integer P_FULLY_REG = 1;\n  localparam integer P_LUTRAM_ASYNC = 12;\n\n  // Sample cycle ratio\n  localparam  P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);\n  localparam integer P_ROUNDING_OFFSET = P_SI_LT_MI ? (C_S_AXI_ACLK_RATIO/2) : (C_M_AXI_ACLK_RATIO/2);\n  localparam integer P_ACLK_RATIO = P_SI_LT_MI ?\n    ((C_M_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_S_AXI_ACLK_RATIO) :\n    ((C_S_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_M_AXI_ACLK_RATIO);\n\n  // Write Address Port bit positions\n  localparam integer C_AWUSER_RIGHT   = 0;\n  localparam integer C_AWUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_AWUSER_WIDTH : 0;\n  localparam integer C_AWQOS_RIGHT    = C_AWUSER_RIGHT + C_AWUSER_WIDTH;\n  localparam integer C_AWQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWREGION_RIGHT = C_AWQOS_RIGHT + C_AWQOS_WIDTH;\n  localparam integer C_AWREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_AWPROT_RIGHT   = C_AWREGION_RIGHT + C_AWREGION_WIDTH;\n  localparam integer C_AWPROT_WIDTH     = 3;\n  localparam integer C_AWCACHE_RIGHT  = C_AWPROT_RIGHT + C_AWPROT_WIDTH;\n  localparam integer C_AWCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWLOCK_RIGHT   = C_AWCACHE_RIGHT + C_AWCACHE_WIDTH;\n  localparam integer C_AWLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_AWBURST_RIGHT  = C_AWLOCK_RIGHT + C_AWLOCK_WIDTH;\n  localparam integer C_AWBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_AWSIZE_RIGHT   = C_AWBURST_RIGHT + C_AWBURST_WIDTH;\n  localparam integer C_AWSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_AWLEN_RIGHT    = C_AWSIZE_RIGHT + C_AWSIZE_WIDTH;\n  localparam integer C_AWLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_AWADDR_RIGHT   = C_AWLEN_RIGHT + C_AWLEN_WIDTH;\n  localparam integer C_AWADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_AWID_RIGHT     = C_AWADDR_RIGHT + C_AWADDR_WIDTH;\n  localparam integer C_AWID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AW_WIDTH        = C_AWID_RIGHT + C_AWID_WIDTH;\n  localparam integer C_FIFO_AW_WIDTH   = C_AWUSER_WIDTH+C_AWQOS_WIDTH+C_AWQOS_WIDTH+3+C_AWCACHE_WIDTH+C_AWLOCK_WIDTH+C_AWBURST_WIDTH+C_AWSIZE_WIDTH+C_AWLEN_WIDTH+C_AXI_ADDR_WIDTH+C_AWID_WIDTH;\n\n  // Write Data Port bit positions\n  localparam integer C_WUSER_RIGHT   = 0;\n  localparam integer C_WUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_WUSER_WIDTH : 0;\n  localparam integer C_WLAST_RIGHT   = C_WUSER_RIGHT + C_WUSER_WIDTH;\n  localparam integer C_WLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_WSTRB_RIGHT   = C_WLAST_RIGHT + C_WLAST_WIDTH;\n  localparam integer C_WSTRB_WIDTH     = C_AXI_DATA_WIDTH/8;\n  localparam integer C_WDATA_RIGHT   = C_WSTRB_RIGHT + C_WSTRB_WIDTH;\n  localparam integer C_WDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_WID_RIGHT     = C_WDATA_RIGHT + C_WDATA_WIDTH;\n  localparam integer C_WID_WIDTH       = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_W_WIDTH        = C_WID_RIGHT + C_WID_WIDTH;\n  localparam integer C_FIFO_W_WIDTH   = C_WUSER_WIDTH + C_WLAST_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_DATA_WIDTH + C_WID_WIDTH;\n\n  // Write Response Port bit positions\n  localparam integer C_BUSER_RIGHT   = 0;\n  localparam integer C_BUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_BUSER_WIDTH : 0;\n  localparam integer C_BRESP_RIGHT   = C_BUSER_RIGHT + C_BUSER_WIDTH;\n  localparam integer C_BRESP_WIDTH     = 2;\n  localparam integer C_BID_RIGHT     = C_BRESP_RIGHT + C_BRESP_WIDTH;\n  localparam integer C_BID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_B_WIDTH        = C_BID_RIGHT + C_BID_WIDTH;\n  localparam integer C_FIFO_B_WIDTH    = C_BUSER_WIDTH + 2 + C_BID_WIDTH;\n\n  // Read Address Port bit positions\n  localparam integer C_ARUSER_RIGHT   = 0;\n  localparam integer C_ARUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_ARUSER_WIDTH : 0;\n  localparam integer C_ARQOS_RIGHT    = C_ARUSER_RIGHT + C_ARUSER_WIDTH;\n  localparam integer C_ARQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARREGION_RIGHT = C_ARQOS_RIGHT + C_ARQOS_WIDTH;\n  localparam integer C_ARREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_ARPROT_RIGHT   = C_ARREGION_RIGHT + C_ARREGION_WIDTH;\n  localparam integer C_ARPROT_WIDTH     = 3;\n  localparam integer C_ARCACHE_RIGHT  = C_ARPROT_RIGHT + C_ARPROT_WIDTH;\n  localparam integer C_ARCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARLOCK_RIGHT   = C_ARCACHE_RIGHT + C_ARCACHE_WIDTH;\n  localparam integer C_ARLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_ARBURST_RIGHT  = C_ARLOCK_RIGHT + C_ARLOCK_WIDTH;\n  localparam integer C_ARBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_ARSIZE_RIGHT   = C_ARBURST_RIGHT + C_ARBURST_WIDTH;\n  localparam integer C_ARSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_ARLEN_RIGHT    = C_ARSIZE_RIGHT + C_ARSIZE_WIDTH;\n  localparam integer C_ARLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_ARADDR_RIGHT   = C_ARLEN_RIGHT + C_ARLEN_WIDTH;\n  localparam integer C_ARADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_ARID_RIGHT     = C_ARADDR_RIGHT + C_ARADDR_WIDTH;\n  localparam integer C_ARID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AR_WIDTH        = C_ARID_RIGHT + C_ARID_WIDTH;\n  localparam integer C_FIFO_AR_WIDTH   = C_ARUSER_WIDTH+C_ARQOS_WIDTH+C_ARQOS_WIDTH+3+C_ARCACHE_WIDTH+C_ARLOCK_WIDTH+C_ARBURST_WIDTH+C_ARSIZE_WIDTH+C_ARLEN_WIDTH+C_AXI_ADDR_WIDTH+C_ARID_WIDTH;\n\n  // Read Data Ports bit positions\n  localparam integer C_RUSER_RIGHT   = 0;\n  localparam integer C_RUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_RUSER_WIDTH : 0;\n  localparam integer C_RLAST_RIGHT   = C_RUSER_RIGHT + C_RUSER_WIDTH;\n  localparam integer C_RLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_RRESP_RIGHT   = C_RLAST_RIGHT + C_RLAST_WIDTH;\n  localparam integer C_RRESP_WIDTH     = 2;\n  localparam integer C_RDATA_RIGHT   = C_RRESP_RIGHT + C_RRESP_WIDTH;\n  localparam integer C_RDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_RID_RIGHT     = C_RDATA_RIGHT + C_RDATA_WIDTH;\n  localparam integer C_RID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_R_WIDTH        = C_RID_RIGHT + C_RID_WIDTH;\n  localparam integer C_FIFO_R_WIDTH   = C_RUSER_WIDTH + C_RLAST_WIDTH + 2 + C_AXI_DATA_WIDTH + C_RID_WIDTH;\n\n  generate\n    if ((C_AXI_IS_ACLK_ASYNC == 0) && (P_ACLK_RATIO == 1)) begin : gen_bypass\n      \n      // Write address port\n      assign m_axi_awid     = s_axi_awid;\n      assign m_axi_awaddr   = s_axi_awaddr;\n      assign m_axi_awlen    = s_axi_awlen;\n      assign m_axi_awsize   = s_axi_awsize;\n      assign m_axi_awburst  = s_axi_awburst;\n      assign m_axi_awlock   = s_axi_awlock;\n      assign m_axi_awcache  = s_axi_awcache;\n      assign m_axi_awprot   = s_axi_awprot;\n      assign m_axi_awregion = s_axi_awregion;\n      assign m_axi_awqos    = s_axi_awqos;\n      assign m_axi_awuser   = s_axi_awuser;\n      assign m_axi_awvalid  = s_axi_awvalid;\n      assign s_axi_awready  = m_axi_awready;\n\n      // Write Data Port\n      assign m_axi_wid      = s_axi_wid;\n      assign m_axi_wdata    = s_axi_wdata;\n      assign m_axi_wstrb    = s_axi_wstrb;\n      assign m_axi_wlast    = s_axi_wlast;\n      assign m_axi_wuser    = s_axi_wuser;\n      assign m_axi_wvalid   = s_axi_wvalid;\n      assign s_axi_wready   = m_axi_wready;\n\n      // Write Response Port\n      assign s_axi_bid      = m_axi_bid;\n      assign s_axi_bresp    = m_axi_bresp;\n      assign s_axi_buser    = m_axi_buser;\n      assign s_axi_bvalid   = m_axi_bvalid;\n      assign m_axi_bready   = s_axi_bready;\n\n      // Read Address Port\n      assign m_axi_arid     = s_axi_arid;\n      assign m_axi_araddr   = s_axi_araddr;\n      assign m_axi_arlen    = s_axi_arlen;\n      assign m_axi_arsize   = s_axi_arsize;\n      assign m_axi_arburst  = s_axi_arburst;\n      assign m_axi_arlock   = s_axi_arlock;\n      assign m_axi_arcache  = s_axi_arcache;\n      assign m_axi_arprot   = s_axi_arprot;\n      assign m_axi_arregion = s_axi_arregion;\n      assign m_axi_arqos    = s_axi_arqos;\n      assign m_axi_aruser   = s_axi_aruser;\n      assign m_axi_arvalid  = s_axi_arvalid;\n      assign s_axi_arready  = m_axi_arready;\n\n      // Read Data Port\n      assign s_axi_rid      = m_axi_rid;\n      assign s_axi_rdata    = m_axi_rdata;\n      assign s_axi_rresp    = m_axi_rresp;\n      assign s_axi_rlast    = m_axi_rlast;\n      assign s_axi_ruser    = m_axi_ruser;\n      assign s_axi_rvalid   = m_axi_rvalid;\n      assign m_axi_rready   = s_axi_rready;\n      \n    end else begin : gen_clock_conv\n      \n      wire fast_aclk;\n      wire slow_aclk;\n      wire sample_cycle;\n      wire sample_cycle_early;\n    \n      // Write Address Port FIFO data read and write\n      wire [C_AW_WIDTH-1:0] s_aw_mesg ;\n      wire [C_AW_WIDTH-1:0] m_aw_mesg ;\n    \n      // Write Data Port FIFO data read and write\n      wire [C_W_WIDTH-1:0] s_w_mesg;\n      wire [C_W_WIDTH-1:0] m_w_mesg;\n    \n      // Write Response Port FIFO data read and write\n      wire [C_B_WIDTH-1:0] s_b_mesg;\n      wire [C_B_WIDTH-1:0] m_b_mesg;\n    \n      // Read Address Port FIFO data read and write\n      wire [C_AR_WIDTH-1:0] s_ar_mesg;\n      wire [C_AR_WIDTH-1:0] m_ar_mesg;\n    \n      // Read Data Ports FIFO data read and write\n      wire [C_R_WIDTH-1:0] s_r_mesg;\n      wire [C_R_WIDTH-1:0] m_r_mesg;\n    \n      wire async_conv_reset_n;\n      assign async_conv_reset_n = ~(~s_axi_aresetn | ~m_axi_aresetn);\n      \n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_awlen           ;\n      wire [3-1:0]                       si_cc_awsize          ;\n      wire [2-1:0]                       si_cc_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_awlock          ;\n      wire [4-1:0]                       si_cc_awcache         ;\n      wire [3-1:0]                       si_cc_awprot          ;\n      wire [4-1:0]                       si_cc_awregion        ;\n      wire [4-1:0]                       si_cc_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]      si_cc_awuser          ;\n      wire                               si_cc_awvalid         ;\n      wire                               si_cc_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_wid            ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]      si_cc_wstrb           ;\n      wire                               si_cc_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]       si_cc_wuser           ;\n      wire                               si_cc_wvalid          ;\n      wire                               si_cc_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_bid             ;\n      wire [2-1:0]                       si_cc_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]       si_cc_buser           ;\n      wire                               si_cc_bvalid          ;\n      wire                               si_cc_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_arlen           ;\n      wire [3-1:0]                       si_cc_arsize          ;\n      wire [2-1:0]                       si_cc_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_arlock          ;\n      wire [4-1:0]                       si_cc_arcache         ;\n      wire [3-1:0]                       si_cc_arprot          ;\n      wire [4-1:0]                       si_cc_arregion        ;\n      wire [4-1:0]                       si_cc_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]      si_cc_aruser          ;\n      wire                               si_cc_arvalid         ;\n      wire                               si_cc_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_rdata           ;\n      wire [2-1:0]                       si_cc_rresp           ;\n      wire                               si_cc_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]       si_cc_ruser           ;\n      wire                               si_cc_rvalid          ;\n      wire                               si_cc_rready          ;\n      \n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_awlen           ;\n      wire [3-1:0]                      cc_mi_awsize          ;\n      wire [2-1:0]                      cc_mi_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_awlock          ;\n      wire [4-1:0]                      cc_mi_awcache         ;\n      wire [3-1:0]                      cc_mi_awprot          ;\n      wire [4-1:0]                      cc_mi_awregion        ;\n      wire [4-1:0]                      cc_mi_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]     cc_mi_awuser          ;\n      wire                              cc_mi_awvalid         ;\n      wire                              cc_mi_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_wid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]     cc_mi_wstrb           ;\n      wire                              cc_mi_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]      cc_mi_wuser           ;\n      wire                              cc_mi_wvalid          ;\n      wire                              cc_mi_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_bid             ;\n      wire [2-1:0]                      cc_mi_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]      cc_mi_buser           ;\n      wire                              cc_mi_bvalid          ;\n      wire                              cc_mi_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_arlen           ;\n      wire [3-1:0]                      cc_mi_arsize          ;\n      wire [2-1:0]                      cc_mi_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_arlock          ;\n      wire [4-1:0]                      cc_mi_arcache         ;\n      wire [3-1:0]                      cc_mi_arprot          ;\n      wire [4-1:0]                      cc_mi_arregion        ;\n      wire [4-1:0]                      cc_mi_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]     cc_mi_aruser          ;\n      wire                              cc_mi_arvalid         ;\n      wire                              cc_mi_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_rdata           ;\n      wire [2-1:0]                      cc_mi_rresp           ;\n      wire                              cc_mi_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]      cc_mi_ruser           ;\n      wire                              cc_mi_rvalid          ;\n      wire                              cc_mi_rready          ;\n      \n    // Tie-offs\n      assign si_cc_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awid : 0 ;\n      assign si_cc_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awaddr : 0 ;\n      assign si_cc_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_awlen : {4'b0000, s_axi_awlen[3:0]}) : 0 ;\n      assign si_cc_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize : 0 ;\n      assign si_cc_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst : 0 ;\n      assign si_cc_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_awlock : {1'b0, s_axi_awlock[0]}) : 0 ;\n      assign si_cc_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache : 0 ;\n      assign si_cc_awprot    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awprot : 0 ;\n      assign si_cc_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos : 0 ;\n      assign si_cc_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion : 0 ;\n      assign si_cc_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser : 0 ;\n      assign si_cc_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awvalid : 0 ;\n      assign si_cc_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? s_axi_wid : 0 ;\n      assign si_cc_wdata     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wdata : 0 ;\n      assign si_cc_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wstrb : 0 ;\n      assign si_cc_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast : 1'b0 ;\n      assign si_cc_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser : 0 ;\n      assign si_cc_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wvalid : 0 ;\n      assign si_cc_bready    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_bready : 0 ;\n      assign si_cc_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arid : 0 ;\n      assign si_cc_araddr    = (C_AXI_SUPPORTS_READ ) ? s_axi_araddr : 0 ;\n      assign si_cc_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_arlen : {4'b0000, s_axi_arlen[3:0]}) : 0 ;\n      assign si_cc_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize : 0 ;\n      assign si_cc_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst : 0 ;\n      assign si_cc_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_arlock : {1'b0, s_axi_arlock[0]}) : 0 ;\n      assign si_cc_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache : 0 ;\n      assign si_cc_arprot    = (C_AXI_SUPPORTS_READ ) ? s_axi_arprot : 0 ;\n      assign si_cc_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos : 0 ;\n      assign si_cc_arregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion : 0 ;\n      assign si_cc_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser : 0 ;\n      assign si_cc_arvalid   = (C_AXI_SUPPORTS_READ ) ? s_axi_arvalid : 0 ;\n      assign si_cc_rready    = (C_AXI_SUPPORTS_READ ) ? s_axi_rready : 0 ;                                       \n                                                                                               \n      assign s_axi_awready   = (C_AXI_SUPPORTS_WRITE ) ? si_cc_awready : 0 ;\n      assign s_axi_wready    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_wready : 0 ;\n      assign s_axi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_bid : 0 ;\n      assign s_axi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bresp : 0 ;\n      assign s_axi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_buser : 0 ;\n      assign s_axi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bvalid : 0 ;\n      assign s_axi_arready   = (C_AXI_SUPPORTS_READ ) ? si_cc_arready : 0 ;\n      assign s_axi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rid : 0 ;\n      assign s_axi_rdata     = (C_AXI_SUPPORTS_READ ) ? si_cc_rdata : 0 ;\n      assign s_axi_rresp     = (C_AXI_SUPPORTS_READ ) ? si_cc_rresp : 0 ;\n      assign s_axi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rlast : 0 ;\n      assign s_axi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_ruser : 0 ;\n      assign s_axi_rvalid    = (C_AXI_SUPPORTS_READ ) ? si_cc_rvalid : 0 ;\n\n      assign m_axi_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awid : 0 ;\n      assign m_axi_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awaddr : 0 ;\n      assign m_axi_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_awlen : cc_mi_awlen[3:0]) : 0 ;\n      assign m_axi_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awsize : 0 ;\n      assign m_axi_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awburst : 0 ;\n      assign m_axi_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_awlock : cc_mi_awlock[0]) : 0 ;\n      assign m_axi_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awcache : 0 ;\n      assign m_axi_awprot    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awprot : 0 ;\n      assign m_axi_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_awregion : 0 ;\n      assign m_axi_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awqos : 0 ;\n      assign m_axi_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_awuser : 0 ;\n      assign m_axi_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awvalid : 0 ;\n      assign m_axi_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? cc_mi_wid : 0 ;\n      assign m_axi_wdata     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wdata : 0 ;\n      assign m_axi_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wstrb : 0 ;\n      assign m_axi_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_wlast : 0 ;\n      assign m_axi_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_wuser : 0 ;\n      assign m_axi_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wvalid : 0 ;\n      assign m_axi_bready    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_bready : 0 ;\n      assign m_axi_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arid : 0 ;\n      assign m_axi_araddr    = (C_AXI_SUPPORTS_READ ) ? cc_mi_araddr : 0 ;\n      assign m_axi_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_arlen : cc_mi_arlen[3:0]) : 0 ;\n      assign m_axi_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arsize : 0 ;\n      assign m_axi_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arburst : 0 ;\n      assign m_axi_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_arlock : cc_mi_arlock[0]) : 0 ;\n      assign m_axi_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arcache : 0 ;\n      assign m_axi_arprot    = (C_AXI_SUPPORTS_READ ) ? cc_mi_arprot : 0 ;\n      assign m_axi_arregion  = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_arregion : 0 ;\n      assign m_axi_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arqos : 0 ;\n      assign m_axi_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_aruser : 0 ;\n      assign m_axi_arvalid   = (C_AXI_SUPPORTS_READ ) ? cc_mi_arvalid : 0 ;\n      assign m_axi_rready    = (C_AXI_SUPPORTS_READ ) ? cc_mi_rready : 0 ;\n                                                                                                                                                                                                                                                                                        \n      assign cc_mi_awready   = (C_AXI_SUPPORTS_WRITE ) ? m_axi_awready : 0 ;\n      assign cc_mi_wready    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_wready : 0 ;\n      assign cc_mi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid : 0 ;\n      assign cc_mi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bresp : 0 ;\n      assign cc_mi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser : 0 ;\n      assign cc_mi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bvalid : 0 ;\n      assign cc_mi_arready   = (C_AXI_SUPPORTS_READ ) ? m_axi_arready : 0 ;\n      assign cc_mi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid : 0 ;\n      assign cc_mi_rdata     = (C_AXI_SUPPORTS_READ ) ? m_axi_rdata : 0 ;\n      assign cc_mi_rresp     = (C_AXI_SUPPORTS_READ ) ? m_axi_rresp : 0 ;\n      assign cc_mi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast : 1'b0 ;\n      assign cc_mi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser : 0 ;\n      assign cc_mi_rvalid    = (C_AXI_SUPPORTS_READ ) ? m_axi_rvalid : 0 ;\n      \n      if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL!=P_AXILITE)) begin : gen_async_conv\n        \n        fifo_generator_v13_2_5 #(\n          .C_EN_SAFETY_CKT(0),\n          .C_SELECT_XPM(0),\n          .C_INTERFACE_TYPE(2),\n          .C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ? 3 : 2),\n          .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n          .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n          .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n          .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n          .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n          .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),\n          .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n          .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n          .C_HAS_AXI_ID((C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0),\n          .C_AXI_LEN_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 8 : 4),\n          .C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 1 : 2),\n          .C_HAS_AXI_ARUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_AWUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_BUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_RUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_WUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_DIN_WIDTH_RACH(C_FIFO_AR_WIDTH),\n          .C_DIN_WIDTH_RDCH(C_FIFO_R_WIDTH),\n          .C_DIN_WIDTH_WACH(C_FIFO_AW_WIDTH),\n          .C_DIN_WIDTH_WDCH(C_FIFO_W_WIDTH),\n          .C_DIN_WIDTH_WRCH(C_FIFO_B_WIDTH),\n          .C_HAS_AXI_RD_CHANNEL(C_AXI_SUPPORTS_READ),\n          .C_HAS_AXI_WR_CHANNEL(C_AXI_SUPPORTS_WRITE),\n          .C_RACH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_RDCH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_WACH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WDCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WRCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),\n          .C_COMMON_CLOCK(0),\n          .C_COUNT_TYPE(0),\n          .C_DATA_COUNT_WIDTH(10),\n          .C_DEFAULT_VALUE(\"BlankString\"),\n          .C_DIN_WIDTH(18),\n          .C_DOUT_RST_VAL(\"0\"),\n          .C_DOUT_WIDTH(18),\n          .C_ENABLE_RLOCS(0),\n          .C_FAMILY(C_FAMILY),\n          .C_FULL_FLAGS_RST_VAL(1),\n          .C_HAS_ALMOST_EMPTY(0),\n          .C_HAS_ALMOST_FULL(0),\n          .C_HAS_BACKUP(0),\n          .C_HAS_DATA_COUNT(0),\n          .C_HAS_INT_CLK(0),\n          .C_HAS_MEMINIT_FILE(0),\n          .C_HAS_OVERFLOW(0),\n          .C_HAS_RD_DATA_COUNT(0),\n          .C_HAS_RD_RST(0),\n          .C_HAS_RST(1),\n          .C_HAS_SRST(0),\n          .C_HAS_UNDERFLOW(0),\n          .C_HAS_VALID(0),\n          .C_HAS_WR_ACK(0),\n          .C_HAS_WR_DATA_COUNT(0),\n          .C_HAS_WR_RST(0),\n          .C_IMPLEMENTATION_TYPE(0),\n          .C_INIT_WR_PNTR_VAL(0),\n          .C_MEMORY_TYPE(1),\n          .C_MIF_FILE_NAME(\"BlankString\"),\n          .C_OPTIMIZATION_MODE(0),\n          .C_OVERFLOW_LOW(0),\n          .C_PRELOAD_LATENCY(1),\n          .C_PRELOAD_REGS(0),\n          .C_PRIM_FIFO_TYPE(\"4kx4\"),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),\n          .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),\n          .C_PROG_EMPTY_TYPE(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL(1022),\n          .C_PROG_FULL_THRESH_NEGATE_VAL(1021),\n          .C_PROG_FULL_TYPE(0),\n          .C_RD_DATA_COUNT_WIDTH(10),\n          .C_RD_DEPTH(1024),\n          .C_RD_FREQ(1),\n          .C_RD_PNTR_WIDTH(10),\n          .C_UNDERFLOW_LOW(0),\n          .C_USE_DOUT_RST(1),\n          .C_USE_ECC(0),\n          .C_USE_EMBEDDED_REG(0),\n          .C_USE_FIFO16_FLAGS(0),\n          .C_USE_FWFT_DATA_COUNT(0),\n          .C_VALID_LOW(0),\n          .C_WR_ACK_LOW(0),\n          .C_WR_DATA_COUNT_WIDTH(10),\n          .C_WR_DEPTH(1024),\n          .C_WR_FREQ(1),\n          .C_WR_PNTR_WIDTH(10),\n          .C_WR_RESPONSE_LATENCY(1),\n          .C_MSGON_VAL(1),\n          .C_ENABLE_RST_SYNC(1),\n          .C_ERROR_INJECTION_TYPE(0),\n          .C_HAS_SLAVE_CE(0),\n          .C_HAS_MASTER_CE(0),\n          .C_ADD_NGC_CONSTRAINT(0),\n          .C_USE_COMMON_OVERFLOW(0),\n          .C_USE_COMMON_UNDERFLOW(0),\n          .C_USE_DEFAULT_SETTINGS(0),\n          .C_HAS_AXIS_TDATA(1),\n          .C_HAS_AXIS_TID(0),\n          .C_HAS_AXIS_TDEST(0),\n          .C_HAS_AXIS_TUSER(1),\n          .C_HAS_AXIS_TREADY(1),\n          .C_HAS_AXIS_TLAST(0),\n          .C_HAS_AXIS_TSTRB(0),\n          .C_HAS_AXIS_TKEEP(0),\n          .C_AXIS_TDATA_WIDTH(8),\n          .C_AXIS_TID_WIDTH(1),\n          .C_AXIS_TDEST_WIDTH(1),\n          .C_AXIS_TUSER_WIDTH(4),\n          .C_AXIS_TSTRB_WIDTH(1),\n          .C_AXIS_TKEEP_WIDTH(1),\n          .C_AXIS_TYPE(0),\n          .C_IMPLEMENTATION_TYPE_WACH(12),\n          .C_IMPLEMENTATION_TYPE_WDCH(12),\n          .C_IMPLEMENTATION_TYPE_WRCH(12),\n          .C_IMPLEMENTATION_TYPE_RACH(12),\n          .C_IMPLEMENTATION_TYPE_RDCH(12),\n          .C_IMPLEMENTATION_TYPE_AXIS(11),\n          .C_APPLICATION_TYPE_WACH(0),\n          .C_APPLICATION_TYPE_WDCH(0),\n          .C_APPLICATION_TYPE_WRCH(0),\n          .C_APPLICATION_TYPE_RACH(0),\n          .C_APPLICATION_TYPE_RDCH(0),\n          .C_APPLICATION_TYPE_AXIS(0),\n          .C_USE_ECC_WACH(0),\n          .C_USE_ECC_WDCH(0),\n          .C_USE_ECC_WRCH(0),\n          .C_USE_ECC_RACH(0),\n          .C_USE_ECC_RDCH(0),\n          .C_USE_ECC_AXIS(0),\n          .C_ERROR_INJECTION_TYPE_WACH(0),\n          .C_ERROR_INJECTION_TYPE_WDCH(0),\n          .C_ERROR_INJECTION_TYPE_WRCH(0),\n          .C_ERROR_INJECTION_TYPE_RACH(0),\n          .C_ERROR_INJECTION_TYPE_RDCH(0),\n          .C_ERROR_INJECTION_TYPE_AXIS(0),\n          .C_DIN_WIDTH_AXIS(1),\n          .C_WR_DEPTH_WACH(16),\n          .C_WR_DEPTH_WDCH(16),\n          .C_WR_DEPTH_WRCH(16),\n          .C_WR_DEPTH_RACH(16),\n          .C_WR_DEPTH_RDCH(16),\n          .C_WR_DEPTH_AXIS(1024),\n          .C_WR_PNTR_WIDTH_WACH(4),\n          .C_WR_PNTR_WIDTH_WDCH(4),\n          .C_WR_PNTR_WIDTH_WRCH(4),\n          .C_WR_PNTR_WIDTH_RACH(4),\n          .C_WR_PNTR_WIDTH_RDCH(4),\n          .C_WR_PNTR_WIDTH_AXIS(10),\n          .C_HAS_DATA_COUNTS_WACH(0),\n          .C_HAS_DATA_COUNTS_WDCH(0),\n          .C_HAS_DATA_COUNTS_WRCH(0),\n          .C_HAS_DATA_COUNTS_RACH(0),\n          .C_HAS_DATA_COUNTS_RDCH(0),\n          .C_HAS_DATA_COUNTS_AXIS(0),\n          .C_HAS_PROG_FLAGS_WACH(0),\n          .C_HAS_PROG_FLAGS_WDCH(0),\n          .C_HAS_PROG_FLAGS_WRCH(0),\n          .C_HAS_PROG_FLAGS_RACH(0),\n          .C_HAS_PROG_FLAGS_RDCH(0),\n          .C_HAS_PROG_FLAGS_AXIS(0),\n          .C_PROG_FULL_TYPE_WACH(0),\n          .C_PROG_FULL_TYPE_WDCH(0),\n          .C_PROG_FULL_TYPE_WRCH(0),\n          .C_PROG_FULL_TYPE_RACH(0),\n          .C_PROG_FULL_TYPE_RDCH(0),\n          .C_PROG_FULL_TYPE_AXIS(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),\n          .C_PROG_EMPTY_TYPE_WACH(0),\n          .C_PROG_EMPTY_TYPE_WDCH(0),\n          .C_PROG_EMPTY_TYPE_WRCH(0),\n          .C_PROG_EMPTY_TYPE_RACH(0),\n          .C_PROG_EMPTY_TYPE_RDCH(0),\n          .C_PROG_EMPTY_TYPE_AXIS(0),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1021),\n          .C_REG_SLICE_MODE_WACH(0),\n          .C_REG_SLICE_MODE_WDCH(0),\n          .C_REG_SLICE_MODE_WRCH(0),\n          .C_REG_SLICE_MODE_RACH(0),\n          .C_REG_SLICE_MODE_RDCH(0),\n          .C_REG_SLICE_MODE_AXIS(0)\n          )\n          asyncfifo_axi (\n            .s_aclk(s_axi_aclk),\n            .m_aclk(m_axi_aclk),\n            .s_aresetn(async_conv_reset_n),\n            .s_axi_awid           (si_cc_awid),\n            .s_axi_awaddr         (si_cc_awaddr),\n            .s_axi_awlen          (si_cc_awlen),\n            .s_axi_awsize         (si_cc_awsize),\n            .s_axi_awburst        (si_cc_awburst),\n            .s_axi_awlock         (si_cc_awlock),\n            .s_axi_awcache        (si_cc_awcache),\n            .s_axi_awprot         (si_cc_awprot),\n            .s_axi_awqos          (si_cc_awqos),\n            .s_axi_awregion       (si_cc_awregion),\n            .s_axi_awuser         (si_cc_awuser),\n            .s_axi_awvalid        (si_cc_awvalid),\n            .s_axi_awready        (si_cc_awready),\n            .s_axi_wid            (si_cc_wid),\n            .s_axi_wdata          (si_cc_wdata),\n            .s_axi_wstrb          (si_cc_wstrb),\n            .s_axi_wlast          (si_cc_wlast),\n            .s_axi_wuser          (si_cc_wuser),\n            .s_axi_wvalid         (si_cc_wvalid),\n            .s_axi_wready         (si_cc_wready),\n            .s_axi_bid            (si_cc_bid),\n            .s_axi_bresp          (si_cc_bresp),\n            .s_axi_buser          (si_cc_buser),\n            .s_axi_bvalid         (si_cc_bvalid),\n            .s_axi_bready         (si_cc_bready),\n            .m_axi_awid           (cc_mi_awid),\n            .m_axi_awaddr         (cc_mi_awaddr),\n            .m_axi_awlen          (cc_mi_awlen),\n            .m_axi_awsize         (cc_mi_awsize),\n            .m_axi_awburst        (cc_mi_awburst),\n            .m_axi_awlock         (cc_mi_awlock),\n            .m_axi_awcache        (cc_mi_awcache),\n            .m_axi_awprot         (cc_mi_awprot),\n            .m_axi_awqos          (cc_mi_awqos),\n            .m_axi_awregion       (cc_mi_awregion),\n            .m_axi_awuser         (cc_mi_awuser),\n            .m_axi_awvalid        (cc_mi_awvalid),\n            .m_axi_awready        (cc_mi_awready),\n            .m_axi_wid            (cc_mi_wid),\n            .m_axi_wdata          (cc_mi_wdata),\n            .m_axi_wstrb          (cc_mi_wstrb),\n            .m_axi_wlast          (cc_mi_wlast),\n            .m_axi_wuser          (cc_mi_wuser),\n            .m_axi_wvalid         (cc_mi_wvalid),\n            .m_axi_wready         (cc_mi_wready),\n            .m_axi_bid            (cc_mi_bid),\n            .m_axi_bresp          (cc_mi_bresp),\n            .m_axi_buser          (cc_mi_buser),\n            .m_axi_bvalid         (cc_mi_bvalid),\n            .m_axi_bready         (cc_mi_bready),\n            .s_axi_arid           (si_cc_arid),\n            .s_axi_araddr         (si_cc_araddr),\n            .s_axi_arlen          (si_cc_arlen),\n            .s_axi_arsize         (si_cc_arsize),\n            .s_axi_arburst        (si_cc_arburst),\n            .s_axi_arlock         (si_cc_arlock),\n            .s_axi_arcache        (si_cc_arcache),\n            .s_axi_arprot         (si_cc_arprot),\n            .s_axi_arqos          (si_cc_arqos),\n            .s_axi_arregion       (si_cc_arregion),\n            .s_axi_aruser         (si_cc_aruser),\n            .s_axi_arvalid        (si_cc_arvalid),\n            .s_axi_arready        (si_cc_arready),\n            .s_axi_rid            (si_cc_rid),\n            .s_axi_rdata          (si_cc_rdata),\n            .s_axi_rresp          (si_cc_rresp),\n            .s_axi_rlast          (si_cc_rlast),\n            .s_axi_ruser          (si_cc_ruser),\n            .s_axi_rvalid         (si_cc_rvalid),\n            .s_axi_rready         (si_cc_rready),\n            .m_axi_arid           (cc_mi_arid),\n            .m_axi_araddr         (cc_mi_araddr),\n            .m_axi_arlen          (cc_mi_arlen),\n            .m_axi_arsize         (cc_mi_arsize),\n            .m_axi_arburst        (cc_mi_arburst),\n            .m_axi_arlock         (cc_mi_arlock),\n            .m_axi_arcache        (cc_mi_arcache),\n            .m_axi_arprot         (cc_mi_arprot),\n            .m_axi_arqos          (cc_mi_arqos),\n            .m_axi_arregion       (cc_mi_arregion),\n            .m_axi_aruser         (cc_mi_aruser),\n            .m_axi_arvalid        (cc_mi_arvalid),\n            .m_axi_arready        (cc_mi_arready),\n            .m_axi_rid            (cc_mi_rid),\n            .m_axi_rdata          (cc_mi_rdata),\n            .m_axi_rresp          (cc_mi_rresp),\n            .m_axi_rlast          (cc_mi_rlast),\n            .m_axi_ruser          (cc_mi_ruser),\n            .m_axi_rvalid         (cc_mi_rvalid),\n            .m_axi_rready         (cc_mi_rready),\n            .m_aclk_en(1'b1),\n            .s_aclk_en(1'b1),\n            .almost_empty(),\n            .almost_full(),\n            .axis_data_count(),\n            .axis_dbiterr(),\n            .axis_injectdbiterr(1'b0),\n            .axis_injectsbiterr(1'b0),\n            .axis_overflow(),\n            .axis_prog_empty(),\n            .axis_prog_empty_thresh(10'b0),\n            .axis_prog_full(),\n            .axis_prog_full_thresh(10'b0),\n            .axis_rd_data_count(),\n            .axis_sbiterr(),\n            .axis_underflow(),\n            .axis_wr_data_count(),\n            .axi_ar_data_count(),\n            .axi_ar_dbiterr(),\n            .axi_ar_injectdbiterr(1'b0),\n            .axi_ar_injectsbiterr(1'b0),\n            .axi_ar_overflow(),\n            .axi_ar_prog_empty(),\n            .axi_ar_prog_empty_thresh(4'b0),\n            .axi_ar_prog_full(),\n            .axi_ar_prog_full_thresh(4'b0),\n            .axi_ar_rd_data_count(),\n            .axi_ar_sbiterr(),\n            .axi_ar_underflow(),\n            .axi_ar_wr_data_count(),\n            .axi_aw_data_count(),\n            .axi_aw_dbiterr(),\n            .axi_aw_injectdbiterr(1'b0),\n            .axi_aw_injectsbiterr(1'b0),\n            .axi_aw_overflow(),\n            .axi_aw_prog_empty(),\n            .axi_aw_prog_empty_thresh(4'b0),\n            .axi_aw_prog_full(),\n            .axi_aw_prog_full_thresh(4'b0),\n            .axi_aw_rd_data_count(),\n            .axi_aw_sbiterr(),\n            .axi_aw_underflow(),\n            .axi_aw_wr_data_count(),\n            .axi_b_data_count(),\n            .axi_b_dbiterr(),\n            .axi_b_injectdbiterr(1'b0),\n            .axi_b_injectsbiterr(1'b0),\n            .axi_b_overflow(),\n            .axi_b_prog_empty(),\n            .axi_b_prog_empty_thresh(4'b0),\n            .axi_b_prog_full(),\n            .axi_b_prog_full_thresh(4'b0),\n            .axi_b_rd_data_count(),\n            .axi_b_sbiterr(),\n            .axi_b_underflow(),\n            .axi_b_wr_data_count(),\n            .axi_r_data_count(),\n            .axi_r_dbiterr(),\n            .axi_r_injectdbiterr(1'b0),\n            .axi_r_injectsbiterr(1'b0),\n            .axi_r_overflow(),\n            .axi_r_prog_empty(),\n            .axi_r_prog_empty_thresh(4'b0),\n            .axi_r_prog_full(),\n            .axi_r_prog_full_thresh(4'b0),\n            .axi_r_rd_data_count(),\n            .axi_r_sbiterr(),\n            .axi_r_underflow(),\n            .axi_r_wr_data_count(),\n            .axi_w_data_count(),\n            .axi_w_dbiterr(),\n            .axi_w_injectdbiterr(1'b0),\n            .axi_w_injectsbiterr(1'b0),\n            .axi_w_overflow(),\n            .axi_w_prog_empty(),\n            .axi_w_prog_empty_thresh(4'b0),\n            .axi_w_prog_full(),\n            .axi_w_prog_full_thresh(4'b0),\n            .axi_w_rd_data_count(),\n            .axi_w_sbiterr(),\n            .axi_w_underflow(),\n            .axi_w_wr_data_count(),\n            .backup(1'b0),\n            .backup_marker(1'b0),\n            .clk(1'b0),\n            .data_count(),\n            .dbiterr(),\n            .din(18'b0),\n            .dout(),\n            .empty(),\n            .full(),\n            .injectdbiterr(1'b0),\n            .injectsbiterr(1'b0),\n            .int_clk(1'b0),\n            .m_axis_tdata(),\n            .m_axis_tdest(),\n            .m_axis_tid(),\n            .m_axis_tkeep(),\n            .m_axis_tlast(),\n            .m_axis_tready(1'b0),\n            .m_axis_tstrb(),\n            .m_axis_tuser(),\n            .m_axis_tvalid(),\n            .overflow(),\n            .prog_empty(),\n            .prog_empty_thresh(10'b0),\n            .prog_empty_thresh_assert(10'b0),\n            .prog_empty_thresh_negate(10'b0),\n            .prog_full(),\n            .prog_full_thresh(10'b0),\n            .prog_full_thresh_assert(10'b0),\n            .prog_full_thresh_negate(10'b0),\n            .rd_clk(1'b0),\n            .rd_data_count(),\n            .rd_en(1'b0),\n            .rd_rst(1'b0),\n            .rst(1'b0),\n            .sbiterr(),\n            .srst(1'b0),\n            .s_axis_tdata(8'b0),\n            .s_axis_tdest(1'b0),\n            .s_axis_tid(1'b0),\n            .s_axis_tkeep(1'b0),\n            .s_axis_tlast(1'b0),\n            .s_axis_tready(),\n            .s_axis_tstrb(1'b0),\n            .s_axis_tuser(4'b0),\n            .s_axis_tvalid(1'b0),\n            .underflow(),\n            .valid(),\n            .wr_ack(),\n            .wr_clk(1'b0),\n            .wr_data_count(),\n            .wr_en(1'b0),\n            .wr_rst(1'b0),\n            .wr_rst_busy(),\n            .rd_rst_busy(),\n            .sleep(1'b0)\n        );\n      end else if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_async_lite_conv\n        localparam C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n        `include \"axi_infrastructure_v1_1_0.vh\"\n\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n        axi_infrastructure_v1_1_0_axi2vector #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        axi2vec ( \n          .s_axi_awid      ( si_cc_awid      ) ,\n          .s_axi_awaddr    ( si_cc_awaddr    ) ,\n          .s_axi_awlen     ( s_axi_awlen     ) ,\n          .s_axi_awsize    ( si_cc_awsize    ) ,\n          .s_axi_awburst   ( si_cc_awburst   ) ,\n          .s_axi_awlock    ( s_axi_awlock    ) ,\n          .s_axi_awcache   ( si_cc_awcache   ) ,\n          .s_axi_awprot    ( si_cc_awprot    ) ,\n          .s_axi_awqos     ( si_cc_awqos     ) ,\n          .s_axi_awuser    ( si_cc_awuser    ) ,\n          .s_axi_awregion  ( si_cc_awregion  ) ,\n          .s_axi_wid       ( si_cc_wid       ) ,\n          .s_axi_wdata     ( si_cc_wdata     ) ,\n          .s_axi_wstrb     ( si_cc_wstrb     ) ,\n          .s_axi_wlast     ( si_cc_wlast     ) ,\n          .s_axi_wuser     ( si_cc_wuser     ) ,\n          .s_axi_bid       ( si_cc_bid       ) ,\n          .s_axi_bresp     ( si_cc_bresp     ) ,\n          .s_axi_buser     ( si_cc_buser     ) ,\n          .s_axi_arid      ( si_cc_arid      ) ,\n          .s_axi_araddr    ( si_cc_araddr    ) ,\n          .s_axi_arlen     ( s_axi_arlen     ) ,\n          .s_axi_arsize    ( si_cc_arsize    ) ,\n          .s_axi_arburst   ( si_cc_arburst   ) ,\n          .s_axi_arlock    ( s_axi_arlock    ) ,\n          .s_axi_arcache   ( si_cc_arcache   ) ,\n          .s_axi_arprot    ( si_cc_arprot    ) ,\n          .s_axi_arqos     ( si_cc_arqos     ) ,\n          .s_axi_aruser    ( si_cc_aruser    ) ,\n          .s_axi_arregion  ( si_cc_arregion  ) ,\n          .s_axi_rid       ( si_cc_rid       ) ,\n          .s_axi_rdata     ( si_cc_rdata     ) ,\n          .s_axi_rresp     ( si_cc_rresp     ) ,\n          .s_axi_rlast     ( si_cc_rlast     ) ,\n          .s_axi_ruser     ( si_cc_ruser     ) ,\n          .s_awpayload     ( s_awpayload ) ,\n          .s_wpayload      ( s_wpayload  ) ,\n          .s_bpayload      ( s_bpayload  ) ,\n          .s_arpayload     ( s_arpayload ) ,\n          .s_rpayload      ( s_rpayload  ) \n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_AWPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_aw (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_awvalid),\n          .s_ready  (si_cc_awready),\n          .s_payld  (s_awpayload),\n          .m_valid  (cc_mi_awvalid),\n          .m_ready  (cc_mi_awready),\n          .m_payld  (m_awpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_ARPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_ar (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_arvalid),\n          .s_ready  (si_cc_arready),\n          .s_payld  (s_arpayload),\n          .m_valid  (cc_mi_arvalid),\n          .m_ready  (cc_mi_arready),\n          .m_payld  (m_arpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_WPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_w (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_wvalid),\n          .s_ready  (si_cc_wready),\n          .s_payld  (s_wpayload),\n          .m_valid  (cc_mi_wvalid),\n          .m_ready  (cc_mi_wready),\n          .m_payld  (m_wpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_BPAYLOAD_WIDTH)\n        ) clock_conv_lite_resp_b (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_bvalid),\n          .s_ready  (cc_mi_bready),\n          .s_payld  (m_bpayload),\n          .m_valid  (si_cc_bvalid),\n          .m_ready  (si_cc_bready),\n          .m_payld  (s_bpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_RPAYLOAD_WIDTH)\n        ) clock_conv_lite_resp_r (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_rvalid),\n          .s_ready  (cc_mi_rready),\n          .s_payld  (m_rpayload),\n          .m_valid  (si_cc_rvalid),\n          .m_ready  (si_cc_rready),\n          .m_payld  (s_rpayload)\n        );\n\n        axi_infrastructure_v1_1_0_vector2axi #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        vec2axi ( \n          .m_awpayload    ( m_awpayload    ) ,\n          .m_wpayload     ( m_wpayload     ) ,\n          .m_bpayload     ( m_bpayload     ) ,\n          .m_arpayload    ( m_arpayload    ) ,\n          .m_rpayload     ( m_rpayload     ) ,\n          .m_axi_awid     ( cc_mi_awid     ) ,\n          .m_axi_awaddr   ( cc_mi_awaddr   ) ,\n          .m_axi_awlen    ( cc_mi_awlen    ) ,\n          .m_axi_awsize   ( cc_mi_awsize   ) ,\n          .m_axi_awburst  ( cc_mi_awburst  ) ,\n          .m_axi_awlock   ( cc_mi_awlock   ) ,\n          .m_axi_awcache  ( cc_mi_awcache  ) ,\n          .m_axi_awprot   ( cc_mi_awprot   ) ,\n          .m_axi_awqos    ( cc_mi_awqos    ) ,\n          .m_axi_awuser   ( cc_mi_awuser   ) ,\n          .m_axi_awregion ( cc_mi_awregion ) ,\n          .m_axi_wid      ( cc_mi_wid      ) ,\n          .m_axi_wdata    ( cc_mi_wdata    ) ,\n          .m_axi_wstrb    ( cc_mi_wstrb    ) ,\n          .m_axi_wlast    ( cc_mi_wlast    ) ,\n          .m_axi_wuser    ( cc_mi_wuser    ) ,\n          .m_axi_bid      ( cc_mi_bid      ) ,\n          .m_axi_bresp    ( cc_mi_bresp    ) ,\n          .m_axi_buser    ( cc_mi_buser    ) ,\n          .m_axi_arid     ( cc_mi_arid     ) ,\n          .m_axi_araddr   ( cc_mi_araddr   ) ,\n          .m_axi_arlen    ( cc_mi_arlen    ) ,\n          .m_axi_arsize   ( cc_mi_arsize   ) ,\n          .m_axi_arburst  ( cc_mi_arburst  ) ,\n          .m_axi_arlock   ( cc_mi_arlock   ) ,\n          .m_axi_arcache  ( cc_mi_arcache  ) ,\n          .m_axi_arprot   ( cc_mi_arprot   ) ,\n          .m_axi_arqos    ( cc_mi_arqos    ) ,\n          .m_axi_aruser   ( cc_mi_aruser   ) ,\n          .m_axi_arregion ( cc_mi_arregion ) ,\n          .m_axi_rid      ( cc_mi_rid      ) ,\n          .m_axi_rdata    ( cc_mi_rdata    ) ,\n          .m_axi_rresp    ( cc_mi_rresp    ) ,\n          .m_axi_rlast    ( cc_mi_rlast    ) ,\n          .m_axi_ruser    ( cc_mi_ruser    ) \n        );\n\n      end else begin : gen_sync_conv\n        \n        assign {fast_aclk, slow_aclk} = P_SI_LT_MI ? {m_axi_aclk, s_axi_aclk} : {s_axi_aclk, m_axi_aclk};\n    \n        // Sample cycle used to determine when to assert a signal on a fast clock\n        // to be flopped onto a slow clock.\n        axi_clock_converter_v2_1_21_axic_sample_cycle_ratio #(\n          .C_RATIO ( P_ACLK_RATIO )\n        )\n        axic_sample_cycle_inst (\n          .SLOW_ACLK          ( slow_aclk               ) ,\n          .FAST_ACLK          ( fast_aclk               ) ,\n          .SAMPLE_CYCLE_EARLY ( sample_cycle_early ) ,\n          .SAMPLE_CYCLE       ( sample_cycle       )\n        );\n    \n      ////////////////////////////////////////////////////////////////////////////////\n      // AXI write channels\n      ////////////////////////////////////////////////////////////////////////////////\n        if (C_AXI_SUPPORTS_WRITE) begin : gen_conv_write_ch\n    \n          // Write Address Port\n          assign s_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH]     = si_cc_awaddr   ;\n          assign s_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH]     = si_cc_awprot   ;\n          assign cc_mi_awaddr   = m_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH];\n          assign cc_mi_awprot   = m_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_aw_axi4\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen    ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock[0] ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH] = si_cc_awregion ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awregion = m_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_aw_axi3\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen[3:0] ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock   ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_aw_user\n            assign s_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH]  = si_cc_awuser;\n            assign cc_mi_awuser = m_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AW_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          aw_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_aw_mesg ) ,\n            .S_VALID   ( si_cc_awvalid   ) ,\n            .S_READY   ( si_cc_awready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_aw_mesg ) ,\n            .M_VALID   ( cc_mi_awvalid   ) ,\n            .M_READY   ( cc_mi_awready   )\n          );\n    \n          // Write Data Port\n          assign s_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH] = si_cc_wdata; \n          assign s_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH] = si_cc_wstrb; \n          assign cc_mi_wdata    = m_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH];\n          assign cc_mi_wstrb    = m_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_w_axi4\n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_w_axi3\n            assign s_w_mesg[C_WID_RIGHT+:C_WID_WIDTH]     = si_cc_wid; \n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wid      = m_w_mesg[C_WID_RIGHT+:C_WID_WIDTH];\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_w_user\n            assign s_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH]  = si_cc_wuser;\n            assign cc_mi_wuser = m_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH  ( C_W_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE           ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          w_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_w_mesg ) ,\n            .S_VALID   ( si_cc_wvalid   ) ,\n            .S_READY   ( si_cc_wready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_w_mesg ) ,\n            .M_VALID   ( cc_mi_wvalid   ) ,\n            .M_READY   ( cc_mi_wready   )\n          );\n    \n          // Write Response Port\n          assign m_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH] = cc_mi_bresp;\n          assign si_cc_bresp    = s_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_b_axi\n            assign m_b_mesg[C_BID_RIGHT+:C_BID_WIDTH]     = cc_mi_bid;\n            assign si_cc_bid      = s_b_mesg[C_BID_RIGHT+:C_BID_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_b_user\n            assign m_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH] = cc_mi_buser;\n            assign si_cc_buser  = s_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_B_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          b_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_b_mesg ) ,\n            .S_VALID   ( cc_mi_bvalid   ) ,\n            .S_READY   ( cc_mi_bready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_b_mesg ) ,\n            .M_VALID   ( si_cc_bvalid   ) ,\n            .M_READY   ( si_cc_bready   )\n          );\n    \n        end else begin : gen_tieoff_write_ch\n    \n          // Write address port\n          assign cc_mi_awid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_awaddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_awlen    = {8{1'b0}};\n          assign cc_mi_awsize   = {3{1'b0}};\n          assign cc_mi_awburst  = {2{1'b0}};\n          assign cc_mi_awlock   = {2{1'b0}};\n          assign cc_mi_awcache  = {4{1'b0}};\n          assign cc_mi_awprot   = {3{1'b0}};\n          assign cc_mi_awregion = {4{1'b0}};\n          assign cc_mi_awqos    = {4{1'b0}};\n          assign cc_mi_awuser   = {C_AXI_AWUSER_WIDTH{1'b0}};\n          assign cc_mi_awvalid  = 1'b0;\n          assign si_cc_awready  = 1'b0;\n    \n          // Write data port\n          assign cc_mi_wid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_wdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign cc_mi_wstrb    = {C_AXI_DATA_WIDTH/8{1'b0}};\n          assign cc_mi_wlast    = 1'b0;\n          assign cc_mi_wuser    = {C_AXI_WUSER_WIDTH{1'b0}};\n          assign cc_mi_wvalid   = 1'b0;\n          assign si_cc_wready   = 1'b0;\n    \n          // Write response port\n          assign si_cc_bid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_bresp    = {2{1'b0}};\n          assign si_cc_buser    = {C_AXI_BUSER_WIDTH{1'b0}};\n          assign si_cc_bvalid   = 1'b0;\n          assign cc_mi_bready   = 1'b0;\n        end\n    \n        ////////////////////////////////////////////////////////////////////////////////\n        // AXI read channels\n        ////////////////////////////////////////////////////////////////////////////////\n    \n        if (C_AXI_SUPPORTS_READ) begin : gen_conv_read_ch\n    \n          // Read Address Port\n          assign s_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH]     = si_cc_araddr   ;\n          assign s_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH]     = si_cc_arprot   ;\n          assign cc_mi_araddr   = m_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH];\n          assign cc_mi_arprot   = m_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_ar_axi4\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen    ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock[0] ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH] = si_cc_arregion ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arregion = m_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_ar_axi3\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen[3:0] ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock   ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_ar_user\n            assign s_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH]  = si_cc_aruser;\n            assign cc_mi_aruser = m_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AR_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          ar_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_ar_mesg ) ,\n            .S_VALID   ( si_cc_arvalid   ) ,\n            .S_READY   ( si_cc_arready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN  ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_ar_mesg ) ,\n            .M_VALID   ( cc_mi_arvalid   ) ,\n            .M_READY   ( cc_mi_arready   )\n          );\n    \n          // Read Data Port\n          assign m_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH] = cc_mi_rdata; \n          assign m_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH] = cc_mi_rresp; \n          assign si_cc_rdata    = s_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH];\n          assign si_cc_rresp    = s_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_r_axi\n            assign m_r_mesg[C_RID_RIGHT+:C_RID_WIDTH]     = cc_mi_rid;   \n            assign m_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH] = cc_mi_rlast;\n            assign si_cc_rid      = s_r_mesg[C_RID_RIGHT+:C_RID_WIDTH];\n            assign si_cc_rlast    = s_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_r_user\n            assign m_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH] = cc_mi_ruser;\n            assign si_cc_ruser  = s_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_R_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          r_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_r_mesg ) ,\n            .S_VALID   ( cc_mi_rvalid   ) ,\n            .S_READY   ( cc_mi_rready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_r_mesg ) ,\n            .M_VALID   ( si_cc_rvalid   ) ,\n            .M_READY   ( si_cc_rready   )\n          );\n    \n        end else begin : gen_tieoff_read_ch\n    \n          // Read Address Port\n          assign cc_mi_arid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_araddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_arlen    = {8{1'b0}};\n          assign cc_mi_arsize   = {3{1'b0}};\n          assign cc_mi_arburst  = {2{1'b0}};\n          assign cc_mi_arlock   = {2{1'b0}};\n          assign cc_mi_arcache  = {4{1'b0}};\n          assign cc_mi_arprot   = {3{1'b0}};\n          assign cc_mi_arregion = {4{1'b0}};\n          assign cc_mi_arqos    = {4{1'b0}};\n          assign cc_mi_aruser   = {C_AXI_ARUSER_WIDTH{1'b0}};\n          assign cc_mi_arvalid  = 1'b0;\n          assign si_cc_arready  = 1'b0;\n    \n          // Read data port\n          assign si_cc_rid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_rdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign si_cc_rresp    = {2{1'b0}};\n          assign si_cc_rlast    = 1'b0;\n          assign si_cc_ruser    = {C_AXI_RUSER_WIDTH{1'b0}};\n          assign si_cc_rvalid   = 1'b0;\n          assign cc_mi_rready   = 1'b0;\n        end\n      end\n    end\n\n  endgenerate\n\nendmodule\n\n\n\n", "num_lines": 2178}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_master #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_SUPPORTS_NARROW = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1,\n   parameter [C_AXI_ADDR_WIDTH-1:0] C_AXI_ADDR = 0,  // Base address\n   parameter integer C_NUM_ADDR = 1,  // Number of address iterations; range 1..2**16 (fixed increment = 32'h10000\n   parameter integer C_NUM_ID = 1,  // Number of ID iterations; range 1..2**C_ID_WIDTH (base = 0; fixed increment = 1)\n   parameter integer C_NUM_LEN = 1,  // Number of LEN iterations; range 1..9 (base = 0; value = 2**i - 1)\n   parameter integer C_NUM_TRANS = 1  // Number of transactions; range >=1 (read and write)\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_awvalid,\n  input  wire                            m_axi_awready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_awburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_awlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_awlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_awid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]    m_axi_awuser = 'b0,\n  /**************** Write Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_wid,\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]      m_axi_wdata,\n  (* dont_touch=\"true\" *) output reg [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb = {(C_AXI_DATA_WIDTH/8){1'b1}},\n  (* dont_touch=\"true\" *) output wire                             m_axi_wvalid,\n  input  wire                            m_axi_wready,\n  (* dont_touch=\"true\" *) output wire                             m_axi_wlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]     m_axi_wuser = 'b0,\n  /**************** Write Response Channel Signals ****************/\n  input  wire [2-1:0]                    m_axi_bresp,\n  input  wire                            m_axi_bvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_bready,\n  input  wire [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]     m_axi_buser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_bid,\n  /**************** Read Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_arvalid,\n  input  wire                            m_axi_arready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_arburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_arlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_arlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_arid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]    m_axi_aruser = 'b0,\n  /**************** Read Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]      m_axi_rdata,\n  input  wire [2-1:0]                    m_axi_rresp,\n  input  wire                            m_axi_rvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_rready,\n  input  wire                            m_axi_rlast,\n  input  wire [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]     m_axi_ruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_rid,\n  /**************** System Signals ****************/\n  input  wire                            aclk,\n  input  wire                            aresetn\n  );\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n  localparam integer  P_NUM_ID_LOG = f_ceil_log2(C_NUM_ID);\n  localparam integer  P_NUM_ADDR_LOG = f_ceil_log2(C_NUM_ADDR);\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL==0 ? 8 : C_AXI_PROTOCOL==1 ? 4 : 1);\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer               P_M_AXI_DATA_BYTES = (C_AXI_DATA_WIDTH / 8);\n  localparam integer               P_M_AXI_DONE_WIDTH = f_ceil_log2(C_NUM_TRANS<2?2:C_NUM_TRANS);\n  localparam integer               P_M_AXI_SIZE = f_ceil_log2(C_AXI_DATA_WIDTH)-3;\n\n  /**************** Internal Wires/Regs - Global ****************/\n   wire                            done;\n    wire                            dummy ;\n  reg                         done_i;\n  reg                         done_sel;\n  wire                         done_cycle;\n  reg                          done_d1 = 1'b0;\n  reg                   areset = 1'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] arcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] rcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [3:0]                    acc_r_i = 4'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] awcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] wcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] bcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [2:0]                    acc_b_i = 3'b0;\n\n  // Register Reset\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    \n    /**************** Internal Wires/Regs - Read Channels ****************/\n    wire                         read_xaction_done_i;\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_arid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_ADDR_WIDTH:0]      araddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  arprot_i = 3'b0;\n    reg [3-1:0]                  arsize_i = 3'b0;\n    reg [2-1:0]                  arburst_i = 2'b0;\n    reg [4-1:0]                  arcache_i = 4'b0;\n    reg [2-1:0]                  arlock_i = 2'b0;\n    reg [P_LEN_WIDTH-1:0]     arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [4-1:0]                  arqos_i = 4'b0;\n    reg [P_ID_WIDTH-1:0]        arid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [2-1:0]                  rresp_i = 2'b00;\n    reg [C_AXI_RUSER_WIDTH:0]   ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      rid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_arvalid_i = 1'b0;\n    reg                        m_axi_rready_i = 1'b0;\n    reg [P_NUM_ADDR_LOG:0]    araddr_cnt = 0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign read_xaction_done_i = m_axi_rvalid && m_axi_rready_i && ((C_AXI_PROTOCOL==2)?1'b1:m_axi_rlast);\n    assign m_axi_arvalid = m_axi_arvalid_i;\n    assign m_axi_rready = m_axi_rready_i;\n    assign m_axi_araddr = m_axi_araddr_i;\n    assign m_axi_arlen = m_axi_arlen_i;\n    always @(posedge aclk) begin\n      m_axi_arprot <= dummy ? arprot_i : 3'b000;\n      m_axi_arsize <= dummy ? arsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_arburst <= dummy ? arburst_i : 2'b01;\n      m_axi_arlock <= dummy ? arlock_i : 1'b0;\n      m_axi_arcache <= dummy ? arcache_i : 4'h3;\n      m_axi_arqos <= dummy  ? arqos_i : 4'h0;\n      m_axi_aruser <= dummy ? aruser_i : 0;\n    end\n  \n    //**********************************************\n    // Read Channel: ARVALID, ARADDR, ARLEN, RREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_arvalid_i <= 1'b0;\n        arcnt_i <= C_NUM_TRANS;\n        m_axi_arlen_i <= 0;\n        m_axi_araddr_i <= C_AXI_ADDR;\n        m_axi_arid_i <= 1;\n        araddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_arready & m_axi_arvalid_i) begin\n          arcnt_i <= arcnt_i - 1;\n          if (araddr_cnt == 1) begin\n            m_axi_araddr_i <= dummy ? araddr_i : C_AXI_ADDR;\n            araddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_araddr_i <= m_axi_araddr_i + 32'h10000;\n            araddr_cnt <= araddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_arlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_arlen_i <= dummy ? arlen_i : 0;\n          end else begin\n            m_axi_arlen_i <= (m_axi_arlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_arid_i == C_NUM_ID)) begin\n            m_axi_arid <= dummy ? arid_i : 0;\n            m_axi_arid_i <= 1;\n          end else begin\n            m_axi_arid <= m_axi_arid_i;\n            m_axi_arid_i <= m_axi_arid_i + 1;\n          end\n          if (arcnt_i == 1) begin\n            m_axi_arvalid_i <= 1'b0;\n          end\n        end else if (arcnt_i != 0) begin\n          m_axi_arvalid_i <= 1'b1;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      araddr_i <= {araddr_i, ~araddr_i[C_AXI_ADDR_WIDTH]};\n      arprot_i <= {arprot_i, ~arprot_i[3-1]};\n      arlen_i <= {arlen_i, ~arlen_i[P_LEN_WIDTH-1]};\n      arsize_i <= {arsize_i, ~arsize_i[3-1]};\n      arburst_i <= {arburst_i, ~arburst_i[2-1]};\n      arlock_i <= {arlock_i, ~arlock_i[2-1]};\n      arcache_i <= {arcache_i, ~arcache_i[4-1]};\n      arqos_i <= {arqos_i, ~arqos_i[4-1]};\n      aruser_i <= {aruser_i, ~aruser_i[C_AXI_ARUSER_WIDTH]};\n      arid_i <= {arid_i, ~arid_i[P_ID_WIDTH-1]};\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        m_axi_rready_i <= 1'b0;\n        rcnt_i <= C_NUM_TRANS;\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        rresp_i <= {2{1'b0}};\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n        rid_i <= {P_ID_WIDTH{1'b0}};\n        acc_r_i <= 4'b0;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_rvalid & m_axi_rready_i) begin\n          m_axi_rready_i <= 1'b0;\n          rdata_i <= m_axi_rdata;\n            acc_r_i[0] <= rdata_i[0];\n          rresp_i <= m_axi_rresp;\n            acc_r_i[1] <= rresp_i[0];\n          ruser_i <= m_axi_ruser;\n            acc_r_i[2] <= ruser_i[0];\n          rid_i <= m_axi_rid;\n            acc_r_i[3] <= rid_i[0];\n          if (m_axi_rlast) begin\n            rcnt_i <= rcnt_i - 1;\n          end\n        end else begin\n          rdata_i <= rdata_i>>1;\n          rresp_i <= rresp_i>>1;\n          ruser_i <= ruser_i>>1;\n          rid_i <= rid_i>>1;\n          acc_r_i <= acc_r_i>>1;\n          if (m_axi_rvalid) begin\n            m_axi_rready_i <= 1'b1;\n          end\n        end\n      end\n    end\n    \n    assign dummy = rdata_i[0];\n    \n    \n\n    /**************** Internal Wires/Regs - Write Channels ****************/\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_awid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [8-1:0]                  xfer_w_i = 8'h00;\n    wire                         write_burst_done_i;\n    reg [C_AXI_ADDR_WIDTH:0]      awaddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  awprot_i = 3'b0;\n    reg [P_LEN_WIDTH-1:0]     awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [3-1:0]                  awsize_i = 3'b0;\n    reg [2-1:0]                  awburst_i = 2'b0;\n    reg [4-1:0]                  awcache_i = 4'b0;\n    reg [2-1:0]                  awlock_i = 2'b0;\n    reg [4-1:0]                  awqos_i = 4'b0;\n    reg [P_ID_WIDTH:0]        awid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_AWUSER_WIDTH:0]    awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg [P_M_AXI_DATA_BYTES-1:0] wstrb_i = {P_M_AXI_DATA_BYTES{1'b1}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]        wid_i = {P_ID_WIDTH{1'b0}};\n    reg [2-1:0]                  bresp_i = 2'b00;\n    reg [C_AXI_BUSER_WIDTH:0]   buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      bid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_awvalid_i = 1'b0;\n    reg                        m_axi_wvalid_i = 1'b0;\n    reg                        m_axi_bready_i = 1'b0;\n    reg                        m_axi_wlast_i = 1'b0;\n    reg                        m_axi_wid_i = {P_ID_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]     wlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [P_NUM_ADDR_LOG:0]    awaddr_cnt = 0;\n  \n    /**************** Assign Write Channel Outputs ****************/\n    assign m_axi_wdata = {wdata_i, done};\n    assign write_burst_done_i = m_axi_wready && m_axi_wvalid_i && ((C_AXI_PROTOCOL==2) || m_axi_wlast_i);\n    assign m_axi_awvalid = m_axi_awvalid_i;\n    assign m_axi_wvalid = m_axi_wvalid_i;\n    assign m_axi_bready = m_axi_bready_i;\n    assign m_axi_wlast = m_axi_wlast_i;\n    assign m_axi_awaddr = m_axi_awaddr_i;\n    assign m_axi_awlen = m_axi_awlen_i;\n    assign m_axi_wid = m_axi_wid_i;\n    always @(posedge aclk) begin\n      m_axi_awprot <= dummy ? awprot_i : 3'b000;\n      m_axi_awsize <= dummy ? awsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_awburst <= dummy ? awburst_i : 2'b01;\n      m_axi_awlock <= dummy ? awlock_i : 1'b0;\n      m_axi_awcache <= dummy ? awcache_i : 4'h3;\n      m_axi_awqos <= dummy ? awqos_i : 4'h0;\n      m_axi_wstrb <= dummy ? wstrb_i : {P_M_AXI_DATA_BYTES{1'b1}};\n      m_axi_awuser <= dummy ?  awuser_i : 0;\n      m_axi_wuser <= dummy ?  wuser_i : 0;\n    end\n  \n    //**********************************************\n    // Write Channel: AWVALID, AWADDR, AWLEN, WVALID, WLAST, BREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_awvalid_i <= 1'b0;\n        m_axi_wvalid_i <= 1'b0;\n        awcnt_i <= C_NUM_TRANS;\n        wcnt_i <= C_NUM_TRANS;\n        xfer_w_i <= 8'h00;\n        m_axi_awlen_i <= 0;\n        m_axi_awaddr_i <= C_AXI_ADDR;\n        m_axi_awid_i <= 1;\n        m_axi_wid_i <= 0;\n        m_axi_wlast_i <= 1'b0;\n        wlen_i <= 0;\n        wid_i <= 0;\n        awaddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_awvalid_i <= 1'b0;\n          awcnt_i <= awcnt_i - 1;\n          if (awaddr_cnt == 1) begin\n            m_axi_awaddr_i <= dummy ? awaddr_i : C_AXI_ADDR;\n            awaddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_awaddr_i <= m_axi_awaddr_i + 32'h10000;\n            awaddr_cnt <= awaddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_awlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_awlen_i <= dummy ? awlen_i : 0;\n          end else begin\n            m_axi_awlen_i <= (m_axi_awlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_awid_i == C_NUM_ID)) begin\n            m_axi_awid <= dummy ? awid_i : 0;\n            m_axi_awid_i <= 1;\n          end else begin\n            m_axi_awid <= m_axi_awid_i;\n            m_axi_awid_i <= m_axi_awid_i + 1;\n          end\n        end else if (~m_axi_wvalid_i) begin\n          if (awcnt_i != 0) begin\n            m_axi_awvalid_i <= 1'b1;\n          end\n        end\n  \n        /**************** Write Data Channel ****************/\n\n        if (m_axi_wready && m_axi_wvalid_i) begin\n          xfer_w_i <= xfer_w_i - 1'b1;\n          if (m_axi_wlast_i) begin\n            m_axi_wvalid_i <= 1'b0;\n            wcnt_i <= wcnt_i - 1'b1;\n          end else begin\n            m_axi_wlast_i <=  (xfer_w_i == 1);\n          end\n        end else if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_wvalid_i <= 1'b1;\n          xfer_w_i <= m_axi_awlen_i;\n          m_axi_wlast_i <= (m_axi_awlen_i==0);\n          m_axi_wid_i <= m_axi_awid_i;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: WDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        wdata_i <= (m_axi_wvalid_i && m_axi_wready) ? {wdata_i[C_AXI_DATA_WIDTH-2 : 0], ~wdata_i[C_AXI_DATA_WIDTH-1]} : wdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      awaddr_i <= {awaddr_i, ~awaddr_i[C_AXI_ADDR_WIDTH]};\n      awprot_i <= {awprot_i[3-2:0], ~awprot_i[3-1]};\n      wstrb_i <= {wstrb_i, ~wstrb_i[C_AXI_DATA_WIDTH/8-1]};\n      awlen_i <= {awlen_i, ~awlen_i[P_LEN_WIDTH-1]};\n      awsize_i <= {awsize_i, ~awsize_i[3-1]};\n      awburst_i <= {awburst_i, ~awburst_i[2-1]};\n      awlock_i <= {awlock_i, ~awlock_i[2-1]};\n      awcache_i <= {awcache_i, ~awcache_i[4-1]};\n      awqos_i <= {awqos_i, ~awqos_i[4-1]};\n      awid_i <= {awid_i, ~awid_i[P_ID_WIDTH-1]};\n      awuser_i <= {awuser_i, ~awuser_i[C_AXI_AWUSER_WIDTH]};\n      wuser_i <= {wuser_i, ~wuser_i[C_AXI_WUSER_WIDTH]};\n    end\n  \n    //**********************************************\n    // Write Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_bready_i <= 1'b0;\n        bcnt_i <= C_NUM_TRANS;\n        bresp_i <= {2{1'b0}};\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n        bid_i <= {P_ID_WIDTH{1'b0}};\n        acc_b_i <= 3'b0;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_bvalid & m_axi_bready_i) begin\n          m_axi_bready_i <= 1'b0;\n          bresp_i <= m_axi_bresp;\n            acc_b_i[0] <= bresp_i[0];\n          buser_i <= m_axi_buser;\n            acc_b_i[1] <= buser_i[0];\n          bid_i <= m_axi_bid;\n            acc_b_i[2] <= bid_i[0];\n          bcnt_i <= bcnt_i - 1;\n        end else begin\n          bresp_i <= bresp_i>>1;\n          buser_i <= buser_i>>1;\n          bid_i <= bid_i>>1;\n          acc_b_i <= acc_b_i>>1;\n          if (m_axi_bvalid) begin\n            m_axi_bready_i <= 1'b1;\n          end\n        end\n      end\n    end\n\n\n  //**********************************************\n  // Assert Done\n  //**********************************************\n  always @(posedge aclk) begin\n    if (~aresetn) begin\n      done_d1 <= 1'b0;\n    end else begin\n      done_d1 <= done_i;\n    end\n  end\n\n  assign done = done_sel ? done_i : done_d1;\n  assign done_cycle = done_i & ~done_d1;\n  \n  always @ * begin\n    if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_readonly_done\n       done_i = rcnt_i==0;\n       done_sel = acc_r_i[0];\n    end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_writeonly_done\n       done_i = bcnt_i==0;\n       done_sel = acc_b_i[0];\n    end else begin : gen_readwrite_done\n       done_i = (rcnt_i==0) && (bcnt_i==0);\n       done_sel = acc_r_i[0] ^ acc_b_i[0];\n    end\n  end\n  \nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n  input  wire [3-1:0]                   s_axi_awprot,\n  input  wire                           s_axi_awvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_awready,\n  input  wire [3-1:0]                   s_axi_awsize,\n  input  wire [2-1:0]                   s_axi_awburst,\n  input  wire [4-1:0]                   s_axi_awcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_awlen,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_awlock,\n  input  wire [4-1:0]                   s_axi_awqos,\n  input  wire [4-1:0]                   s_axi_awregion,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_awid,\n  input  wire [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]   s_axi_awuser,\n  /**************** Write Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n  input  wire                           s_axi_wvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_wready,\n  input  wire                           s_axi_wlast,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_wid,\n  input  wire [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]    s_axi_wuser,\n  /**************** Write Response Channel Signals ****************/\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_bresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_bvalid,\n  input  wire                           s_axi_bready,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]    s_axi_buser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_bid = 'b0,\n  /**************** Read Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n  input  wire [3-1:0]                   s_axi_arprot,\n  input  wire                           s_axi_arvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_arready,\n  input  wire [3-1:0]                   s_axi_arsize,\n  input  wire [2-1:0]                   s_axi_arburst,\n  input  wire [4-1:0]                   s_axi_arcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_arlock,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_arlen,\n  input  wire [4-1:0]                   s_axi_arqos,\n  input  wire [4-1:0]                   s_axi_arregion,\n  input  wire [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]   s_axi_aruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_arid,\n  /**************** Read Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_rresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rvalid,\n  input  wire                           s_axi_rready,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]    s_axi_ruser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_rid = 'b0,\n  /**************** System Signals ****************/\n  input  wire                           aclk,\n  input  wire                           aresetn\n   );\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL == 1) ? 4 : 8;\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer P_S_AXI_DATA_BYTES = 32/8;\n  localparam integer P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n\n  /**************** Internal Wires/Regs - Global ****************/\n  reg                   areset = 1'b0;\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    /**************** Internal Wires/Regs - Read Channels ****************/\n    reg [8-1:0]                   xfer_r_cnt = 8'h00;\n    reg [16-1:0]                  arcnt_i = 16'h0000;\n    wire                          read_xaction_done_i;\n    reg [C_AXI_DATA_WIDTH-1:0]     rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]      arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg                           arvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     araddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   arprot_i = 3'b000;\n    reg [3-1:0]                   arsize_i = 3'b000;\n    reg [2-1:0]                   arburst_i = 2'b00;\n    reg [4-1:0]                   arcache_i = 4'b0000;\n    reg [1-1:0]     arlock_i = 1'b0;\n    reg [4-1:0]                   arqos_i = 4'b0000;\n    reg [4-1:0]                   arregion_i = 4'b0000;\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_RUSER_WIDTH:0]     ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_ar_i = 9'b0;\n    reg                           s_axi_rvalid_i = 1'b0;\n    reg                           s_axi_arready_i = 1'b0;\n    reg                           s_axi_rlast_i = 1'b0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign s_axi_rdata = rdata_i;\n    assign read_xaction_done_i = (s_axi_rready && s_axi_rvalid_i && s_axi_rlast_i);\n    assign s_axi_rvalid = s_axi_rvalid_i;\n    assign s_axi_arready = s_axi_arready_i;\n    assign s_axi_rlast = s_axi_rlast_i;\n    //**********************************************\n    // Read Channel: ARREADY, RVALID, RLAST, RID\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        xfer_r_cnt <= 8'h00;\n        arcnt_i <= 16'h0000;\n        arlen_i <= {P_LEN_WIDTH{1'b0}};\n        s_axi_rlast_i <= 1'b0;\n      end else begin\n        /**************** Read Address Channel ****************/\n        // arready\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_arready_i <= 1'b0;\n          arcnt_i <= arcnt_i + 1'b1;\n        end else if (~s_axi_rvalid_i) begin\n          s_axi_arready_i <= 1'b1;\n        end\n  \n        /**************** Read Data Channel ****************/\n        // rvalid\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_rvalid_i <= 1'b1;\n          s_axi_rid <= s_axi_arid;\n          s_axi_ruser <= ruser_i;\n        end else if(read_xaction_done_i) begin\n          s_axi_rvalid_i <= 1'b0;\n        end\n  \n        // rlast\n        if(s_axi_rready && s_axi_rvalid_i) begin\n          xfer_r_cnt <= xfer_r_cnt - 1;\n          if(xfer_r_cnt == 1) begin\n            s_axi_rlast_i <= 1'b1;\n          end\n        end else if(s_axi_arready_i && s_axi_arvalid) begin\n          xfer_r_cnt <= s_axi_arlen;\n          s_axi_rlast_i <= (s_axi_arlen==0);\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Read Channel: RDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        rdata_i <= (s_axi_rready && s_axi_rvalid_i) ? {rdata_i[C_AXI_DATA_WIDTH-2 : 0], ~rdata_i[C_AXI_DATA_WIDTH-1]} : rdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_rresp <= {2{1'b0}};\n      end else if (~s_axi_rvalid_i) begin\n        s_axi_rresp <= {acc_ar_i[0], 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n      end else begin\n        ruser_i <= (s_axi_arready_i && s_axi_arvalid) ? {ruser_i, ~ruser_i[C_AXI_RUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        araddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        arprot_i <= {3{1'b0}};\n        arsize_i <= {3{1'b0}};\n        arburst_i <= {2{1'b0}};\n        arcache_i <= {4{1'b0}};\n        arlock_i <= {1{1'b0}};\n        arqos_i <= {4{1'b0}};\n        arregion_i <= {4{1'b0}};\n        aruser_i <= {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n        acc_ar_i <= 9'b0;\n      end else if (s_axi_arvalid) begin\n        // Register Inputs\n        araddr_i <= s_axi_araddr;\n          acc_ar_i[0] <= araddr_i[0];\n        arprot_i <= s_axi_arprot;\n          acc_ar_i[1] <= arprot_i[0];\n        arsize_i <= s_axi_arsize;\n          acc_ar_i[2] <= arsize_i[0];\n        arburst_i <= s_axi_arburst;\n          acc_ar_i[3] <= arburst_i[0];\n        arcache_i <= s_axi_arcache;\n          acc_ar_i[4] <= arcache_i[0];\n        arlock_i <= s_axi_arlock;\n          acc_ar_i[5] <= arlock_i[0];\n        arqos_i <= s_axi_arqos;\n          acc_ar_i[6] <= arqos_i[0];\n        arregion_i <= s_axi_arregion;\n          acc_ar_i[7] <= arregion_i[0];\n        aruser_i <= s_axi_aruser;\n          acc_ar_i[8] <= aruser_i[0];\n      end else begin\n        araddr_i <= araddr_i>>1;\n        arprot_i <= arprot_i>>1;\n        arsize_i <= arsize_i>>1;\n        arburst_i <= arburst_i>>1;\n        arcache_i <= arcache_i>>1;\n        arlock_i <= arlock_i>>1;\n        arqos_i <= arqos_i>>1;\n        arregion_i <= arregion_i>>1;\n        aruser_i <= aruser_i>>1;\n        acc_ar_i <= acc_ar_i>>1;\n      end\n    end\n  \n  \n    /**************** Internal Wires/Regs - Write Channels ****************/\n    wire                          write_burst_done_i;\n    reg [16-1:0]                  awcnt_i = 16'h0000;\n    reg                           awvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     awaddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   awprot_i = 3'b000;\n    reg [3-1:0]                   awsize_i = 3'b000;\n    reg [2-1:0]                   awburst_i = 2'b00;\n    reg [4-1:0]                   awcache_i = 4'b0000;\n    reg [P_LEN_WIDTH-1:0]      awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [1-1:0]     awlock_i = 1'b0;\n    reg [4-1:0]                   awqos_i = 4'b0000;\n    reg [4-1:0]                   awregion_i = 4'b0000;\n    reg [C_AXI_AWUSER_WIDTH:0]     awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg                           wvalid_i = 1'b0;\n    reg [C_AXI_DATA_WIDTH-1:0]     wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH/8-1:0]   wstrb_i = {(C_AXI_DATA_WIDTH/8){1'b0}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_BUSER_WIDTH:0]     buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_aw_i = 9'b0;\n    reg [3:0]                     acc_w_i = 4'b0;\n    reg                           s_axi_bvalid_i = 1'b0;\n    reg                           s_axi_awready_i = 1'b0;\n    reg                           s_axi_wready_i = 1'b0;\n    /**************** Assign Write Channel Outputs ****************/\n    assign write_burst_done_i =s_axi_wready_i && s_axi_wvalid && ((C_AXI_PROTOCOL == 2) ? 1'b1 : s_axi_wlast);\n    assign s_axi_bvalid = s_axi_bvalid_i;\n    assign s_axi_awready = s_axi_awready_i;\n    assign s_axi_wready = s_axi_wready_i;\n  \n    //**********************************************\n    // Write Channel: AWREADY, WREADY, BVALID, BID\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awcnt_i <= 16'h0000;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        /**************** Write Address Channel ****************/\n        // awready\n        if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_awready_i <= 1'b0;\n          awcnt_i <= awcnt_i + 1'b1;\n          s_axi_bid <= s_axi_awid;\n          s_axi_buser <= buser_i;\n        end else if(~s_axi_wready_i & ~s_axi_bvalid_i) begin\n          s_axi_awready_i <= 1'b1;\n        end\n  \n        /**************** Write Data Channel ****************/\n        // wready\n        if(write_burst_done_i) begin\n          s_axi_wready_i <= 1'b0;\n        end else if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_wready_i <= 1'b1;\n        end\n  \n        /**************** Write Response Channel ****************/\n        // bvalid\n        if(write_burst_done_i) begin\n          s_axi_bvalid_i <= 1'b1;\n        end else if(s_axi_bready && s_axi_bvalid_i) begin\n          s_axi_bvalid_i <= 1'b0;\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Write Channel: BRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_bresp <= {2{1'b0}};\n      end else if (~s_axi_bvalid_i) begin\n        s_axi_bresp <= {(acc_aw_i[0] ^ acc_w_i[0]), 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: BUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (aresetn) begin\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n      end else begin\n        buser_i <= (s_axi_awready_i && s_axi_awvalid) ? {buser_i, ~buser_i[C_AXI_BUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Write Address Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awaddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        awprot_i <= {3{1'b0}};\n        awsize_i <= {3{1'b0}};\n        awburst_i <= {2{1'b0}};\n        awcache_i <= {4{1'b0}};\n        awlen_i <= {P_LEN_WIDTH{1'b0}};\n        awlock_i <= {1{1'b0}};\n        awqos_i <= {4{1'b0}};\n        awregion_i <= {4{1'b0}};\n        awuser_i <= {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n        acc_aw_i <= 9'b0;\n      end else if (s_axi_awvalid) begin\n        // Register Inputs\n        awaddr_i <= s_axi_awaddr;\n          acc_aw_i[0] <= awaddr_i[0];\n        awprot_i <= s_axi_awprot;\n          acc_aw_i[1] <= awprot_i[0];\n        awsize_i <= s_axi_awsize;\n          acc_aw_i[2] <= awsize_i[0];\n        awburst_i <= s_axi_awburst;\n          acc_aw_i[3] <= awburst_i[0];\n        awcache_i <= s_axi_awcache;\n          acc_aw_i[4] <= awcache_i[0];\n        awlock_i <= s_axi_awlock;\n          acc_aw_i[5] <= awlock_i[0];\n        awqos_i <= s_axi_awqos;\n          acc_aw_i[6] <= awqos_i[0];\n        awregion_i <= s_axi_awregion;\n          acc_aw_i[7] <= awregion_i[0];\n        awuser_i <= s_axi_awuser;\n          acc_aw_i[8] <= awuser_i[0];\n      end else begin\n        awaddr_i <= awaddr_i>>1;\n        awprot_i <= awprot_i>>1;\n        awsize_i <= awsize_i>>1;\n        awburst_i <= awburst_i>>1;\n        awcache_i <= awcache_i>>1;\n        awlock_i <= awlock_i>>1;\n        awqos_i <= awqos_i>>1;\n        awregion_i <= awregion_i>>1;\n        awuser_i <= awuser_i>>1;\n        acc_aw_i <= acc_aw_i>>1;\n      end\n    end\n  \n    //**********************************************\n    // Write Data Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        wstrb_i <= {(C_AXI_DATA_WIDTH/8){1'b0}};\n        wuser_i <= {(C_AXI_WUSER_WIDTH+1){1'b0}};\n        acc_w_i <= 4'b0;\n      end else if (s_axi_wvalid) begin\n        // Register Inputs\n        wdata_i <= s_axi_wdata;\n          acc_w_i[0] <= wdata_i[0];\n        wstrb_i <= s_axi_wstrb;\n          acc_w_i[1] <= wstrb_i[0];\n        wuser_i <= s_axi_wuser;\n          acc_w_i[2] <= wuser_i[0];\n      end else begin\n        wdata_i <= wdata_i>>1;\n        wstrb_i <= wstrb_i>>1;\n        wuser_i <= wuser_i>>1;\n        acc_w_i <= acc_w_i>>1;\n      end\n    end\n  \nendmodule\n\n\n\n//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_22_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \n(* autopipeline_module=\"yes\" *)\nmodule axi_register_slice_v2_1_22_auto_slr #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n    wire                    handshake_pipe;\n    wire                    ready_pipe;\n    wire [C_DATA_WIDTH-1:0] payload_pipe;\n    (* keep=\"true\" *)                                                                reg  s_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  s_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  s_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  s_areset_resp2 = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  m_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  m_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_areset_resp2 = 1'b0;\n    \n  // Global Reset pipelining\n  \n    always @(posedge ACLK) begin\n      s_aclear       <= ~ARESETN;\n      s_areset_fwd   <= ~ARESETN; \n      s_areset_resp  <= s_areset_fwd;  // Auto-pipeline\n      s_areset_resp2 <= s_areset_resp; // Auto-pipeline\n    end\n    \n    always @(posedge ACLK) begin\n      m_aclear       <= ~ARESETN;\n      m_areset_fwd   <= ~ARESETN; \n      m_areset_resp  <= m_areset_fwd;  // Auto-pipeline\n      m_areset_resp2 <= m_areset_resp; // Auto-pipeline\n    end\n    \n  // Source-side submodule\n    \n    axi_register_slice_v2_1_22_auto_src #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_src\n      (\n       .ACLK             (ACLK),    \n       .s_aclear         (s_aclear),\n       .s_areset_resp2   (s_areset_resp2),  \n       .S_VALID          (S_VALID),  \n       .S_READY          (S_READY), \n       .S_PAYLOAD_DATA   (S_PAYLOAD_DATA),\n       .ready_pipe        (ready_pipe), \n       .handshake_pipe    (handshake_pipe),\n       .payload_pipe      (payload_pipe)  \n      );\n    \n  // Destination-side submodule\n    \n    axi_register_slice_v2_1_22_auto_dest #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_dest\n      (\n       .ACLK           (ACLK),    \n       .m_aclear       (m_aclear),\n       .m_areset_resp2 (m_areset_resp2),  \n       .M_READY        (M_READY), \n       .M_VALID        (M_VALID),  \n       .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n       .handshake_pipe  (handshake_pipe),\n       .ready_pipe      (ready_pipe),  \n       .payload_pipe    (payload_pipe)  \n      );\n    \nendmodule  // auto_slr\n\nmodule axi_register_slice_v2_1_22_auto_src #\n  (\n   parameter integer C_DATA_WIDTH = 32\n  )\n  (\n   input  wire ACLK,\n   input  wire s_aclear,\n   input  wire s_areset_resp2,\n   input  wire S_VALID,\n   input  wire ready_pipe,\n   output wire S_READY,\n   output wire handshake_pipe,\n   output wire  [C_DATA_WIDTH-1:0] payload_pipe,\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA\n   );\n    \n   (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  [C_DATA_WIDTH-1:0] payload_pipe_r;\n    (* keep=\"true\" *) reg [2:0] s_aresetn_resp4 = 3'b000;\n    wire s_aresetn_resp3;\n    wire s_aresetn_d;\n    wire s_aresetn_q;\n    wire s_handshake_d;\n    wire s_ready_i;\n    \n    assign S_READY = s_ready_i & s_aresetn_q;\n    assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;\n    assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;\n    assign payload_pipe = payload_pipe_r;\n    \n    always @(posedge ACLK or posedge s_aclear) begin\n      if (s_aclear) begin\n        s_aresetn_resp4 <= 3'b000;\n      end else begin\n        s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      payload_pipe_r <= S_PAYLOAD_DATA;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) s_aresetn_resp3_inst (\n        .Q   (s_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~s_areset_resp2)\n     );\n    \n    // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (s_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_aresetn_d)\n     );\n    \n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (handshake_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_handshake_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (s_ready_i),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (ready_pipe)\n     );\n    \nendmodule  // auto_src\n\nmodule axi_register_slice_v2_1_22_auto_dest #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   input  wire ACLK,\n   input  wire m_aclear,\n   input  wire m_areset_resp2,\n   input  wire M_READY,\n   input  wire handshake_pipe,\n   output wire ready_pipe,\n   output wire M_VALID,\n   input  wire [C_DATA_WIDTH-1:0] payload_pipe,\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n   );\n    \n    (* keep=\"true\" *) reg [2:0] m_aresetn_resp4 = 3'b000;\n    wire m_aresetn_resp3;\n    wire m_aresetn_d;\n    wire m_aresetn_q;\n    wire m_valid_i;\n    wire pop;\n    wire m_ready_d;\n    wire m_handshake_q;\n    reg  [C_DATA_WIDTH-1:0] m_payload_q;\n    \n    assign M_VALID = m_valid_i;\n    assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;\n    assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;\n    assign pop     = M_READY & m_valid_i;\n    \n    always @(posedge ACLK or posedge m_aclear) begin\n      if (m_aclear) begin\n        m_aresetn_resp4 <= 3'b000;\n      end else begin\n        m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      m_payload_q <= payload_pipe;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) m_aresetn_resp3_inst (\n        .Q   (m_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~m_areset_resp2)\n     );\n    \n    // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (m_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_aresetn_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (m_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (handshake_pipe)\n     );\n    \n    (* autopipeline_group=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (ready_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_ready_d)\n     );\n    \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  (5)  \n      )\n      srl_fifo\n      (\n       .aclk    (ACLK),    \n       .areset  (~m_aresetn_q),\n       .aclear  (m_aclear),  \n       .s_mesg  (m_payload_q),  \n       .s_valid (m_handshake_q), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      );\n    \nendmodule  // auto_dest\n\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      reg s_valid_d;\n      reg s_ready_d = 1'b0;\n      reg s_ready_reg = 1'b0;\n      reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_22_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_RESP_MIDDLE2_LATENCY = C_PIPELINES_SLAVE + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_22_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      .ACLK           (ACLK),\n      .ARESETN         (ARESETN),\n      .S_PAYLOAD_DATA (S_PAYLOAD_DATA),\n      .S_VALID        (S_VALID),\n      .S_READY        (S_READY),\n      .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n      .M_VALID        (M_VALID),\n      .M_READY        (M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_reset;\n    wire src_ready;\n    wire dummy_reset;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  ( C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( dummy_reset   ) ,\n        .laguna_s_reset_in  ( src_reset   ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset   ) ,\n        .laguna_m_reset_in  ( src_reset  ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset2   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n      \n  end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] mid_payload;\n    wire mid_handshake;\n    wire mid_ready;\n    wire mid_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n    wire dummy_reset3;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( mid_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( mid_reset    ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset3   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset3   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out (  dummy_reset2  ) ,\n        .laguna_m_reset_in  ( mid_reset   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE2_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( mid_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2   ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset3   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset3    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n   \n  generate\n\n  (* keep=\"true\" *) reg s_reset_dd = 1'b0;\n  (* keep=\"true\" *) reg m_reset_dd = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n  \n  assign laguna_s_reset_out = laguna_s_reset_out_i;\n  assign laguna_m_reset_out = laguna_m_reset_out_i;\n  \n  always @(posedge ACLK) begin\n    laguna_s_reset_in_d <= laguna_s_reset_in;\n    laguna_m_reset_in_d <= laguna_m_reset_in;\n    s_reset_dd <= laguna_s_reset_in_d;\n    m_reset_dd <= laguna_m_reset_in_d;\n    laguna_s_reset_out_i <= C_PIPELINES==0 ? laguna_m_reset_in_d : m_reset_dd;\n    laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;\n  end\n  \n  wire ACLEAR;\n  assign ACLEAR = ~ARESETN;\n  \n  if (1) begin : common\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire laguna_s_handshake_q;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, laguna_m_ready_d}; \n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else if (p==C_PIPELINES+1) begin\n          laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n\n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = handshake_i[C_PIPELINES];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_m_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* keep=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_22_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_m_reset_out = laguna_m_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_m_reset_in_d <= laguna_m_reset_in;\n      aresetn_d <= C_CHANNEL==P_FORWARD ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? areset_dly[15]  : laguna_m_reset_in_d;\n      laguna_m_reset_out_i <= areset_d;  // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n  \n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* keep=\"true\" *)  reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      ready_d <= {ready_d, laguna_m_ready_d}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid_q;\n      assign payload_valid_d = (p==0) ? (S_VALID & s_ready_i) : handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==C_PIPELINES) begin\n          laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else if (p==0) begin\n          payload_data <= S_PAYLOAD_DATA;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n      \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_s_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* keep=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_s_reset_out = laguna_s_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_s_reset_in_d <= laguna_s_reset_in;\n      aresetn_d <= C_CHANNEL==P_RESPONSE ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? laguna_s_reset_in_d : areset_dly[15];\n      laguna_s_reset_out_i <= areset_d;  // For forward channels, reflect laguna_s_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n\n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    wire laguna_s_handshake_q;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      laguna_s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n        \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n        \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)  \n      )\n      srl_fifo_0\n      (\n       .aclk    (ACLK),    \n       .areset  (areset_d),  \n       .aclear  (ACLEAR),\n       .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n       .s_valid (push), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      ); \n  \n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  reg areset_d = 1'b0;\n  reg [3:0] areset_dly = 4'b0;\n  always @(posedge ACLK) begin\n    areset_dly <= {4{~ARESETN}} | (areset_dly<<1);\n    areset_d <= areset_dly[3];\n  end\n  \n  if (1) begin : common\n    reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID & s_ready_i;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* keep=\"true\" *)  reg payload_valid = 1'b0;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          payload_data <= S_PAYLOAD_DATA;\n          payload_valid <= S_VALID & s_ready_i & ~areset_d;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n          payload_valid <= handshake_i[((p>0)?(p-1):0)];\n        end\n      end\n    end\n    \n    if (C_PIPELINES==0) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),\n         .aclear  (1'b0),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire                        aclear,  // Async clear\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    wire [1:0] state;  // State vector register\n    reg  [1:0] next;           // Next state value\n    wire [1:0] next_qual;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    reg  m_valid_d;\n    wire m_valid_q;\n    \n    assign m_valid = m_valid_q;\n    assign next_qual = areset ? K_EMPTY : next;\n    assign m_mesg  = mesg_reg;\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_mvalid_inst (\n        .Q   (m_valid_q),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (m_valid_d)\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state0_inst (\n        .Q   (state[0]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[0])\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state1_inst (\n        .Q   (state[1]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[1])\n     );\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      m_valid_d = m_valid_q & ~areset;\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid & ~areset) begin\n            next = K_HAS1;\n            m_valid_d = 1'b0;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              m_valid_d = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n              m_valid_d = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          m_valid_d = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      (* keep_hierarchy = \"yes\" *) axi_register_slice_v2_1_22_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule  // axic_reg_srl_fifo\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   //   16 -> Auto-pipelining\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_RESERVE_MODE = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n  \n  if (C_RESERVE_MODE==1) begin : gen_reserve_si\n  \n    axi_register_slice_v2_1_22_test_slave #(\n      .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n      .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n      .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n      .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n      .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n      .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n      .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n      .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n      .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .s_axi_awaddr(s_axi_awaddr),\n      .s_axi_awprot(s_axi_awprot),\n      .s_axi_awvalid(s_axi_awvalid),\n      .s_axi_awready(s_axi_awready),\n      .s_axi_awsize(s_axi_awsize),\n      .s_axi_awburst(s_axi_awburst),\n      .s_axi_awcache(s_axi_awcache),\n      .s_axi_awlen(s_axi_awlen),\n      .s_axi_awlock(s_axi_awlock),\n      .s_axi_awqos(s_axi_awqos),\n      .s_axi_awregion(s_axi_awregion),\n      .s_axi_awid(s_axi_awid),\n      .s_axi_awuser(s_axi_awuser),\n      .s_axi_wdata(s_axi_wdata),\n      .s_axi_wstrb(s_axi_wstrb),\n      .s_axi_wvalid(s_axi_wvalid),\n      .s_axi_wready(s_axi_wready),\n      .s_axi_wlast(s_axi_wlast),\n      .s_axi_wid(s_axi_wid),\n      .s_axi_wuser(s_axi_wuser),\n      .s_axi_bresp(s_axi_bresp),\n      .s_axi_bvalid(s_axi_bvalid),\n      .s_axi_bready(s_axi_bready),\n      .s_axi_buser(s_axi_buser),\n      .s_axi_bid(s_axi_bid),\n      .s_axi_araddr(s_axi_araddr),\n      .s_axi_arprot(s_axi_arprot),\n      .s_axi_arvalid(s_axi_arvalid),\n      .s_axi_arready(s_axi_arready),\n      .s_axi_arsize(s_axi_arsize),\n      .s_axi_arburst(s_axi_arburst),\n      .s_axi_arcache(s_axi_arcache),\n      .s_axi_arlock(s_axi_arlock),\n      .s_axi_arlen(s_axi_arlen),\n      .s_axi_arqos(s_axi_arqos),\n      .s_axi_arregion(s_axi_arregion),\n      .s_axi_aruser(s_axi_aruser),\n      .s_axi_arid(s_axi_arid),\n      .s_axi_rdata(s_axi_rdata),\n      .s_axi_rresp(s_axi_rresp),\n      .s_axi_rvalid(s_axi_rvalid),\n      .s_axi_rready(s_axi_rready),\n      .s_axi_rlast(s_axi_rlast),\n      .s_axi_ruser(s_axi_ruser),\n      .s_axi_rid(s_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign m_axi_awid     = 0;\n     assign m_axi_awaddr   = 0;\n     assign m_axi_awlen    = 0;\n     assign m_axi_awsize   = 0;\n     assign m_axi_awburst  = 0;\n     assign m_axi_awlock   = 0;\n     assign m_axi_awcache  = 0;\n     assign m_axi_awprot   = 0;\n     assign m_axi_awregion = 0;\n     assign m_axi_awqos    = 0;\n     assign m_axi_awuser   = 0;\n     assign m_axi_awvalid  = 0;\n     assign m_axi_wid      = 0;\n     assign m_axi_wdata    = 0;\n     assign m_axi_wstrb    = 0;\n     assign m_axi_wlast    = 0;\n     assign m_axi_wuser    = 0;\n     assign m_axi_wvalid   = 0;\n     assign m_axi_bready   = 0;\n     assign m_axi_arid     = 0;\n     assign m_axi_araddr   = 0;\n     assign m_axi_arlen    = 0;\n     assign m_axi_arsize   = 0;\n     assign m_axi_arburst  = 0;\n     assign m_axi_arlock   = 0;\n     assign m_axi_arcache  = 0;\n     assign m_axi_arprot   = 0;\n     assign m_axi_arregion = 0;\n     assign m_axi_arqos    = 0;\n     assign m_axi_aruser   = 0;\n     assign m_axi_arvalid  = 0;\n     assign m_axi_rready   = 0;\n      \n  end else if (C_RESERVE_MODE==2) begin : gen_reserve_mi\n    \n    axi_register_slice_v2_1_22_test_master #(\n    .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n    .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .m_axi_awaddr(m_axi_awaddr),\n      .m_axi_awprot(m_axi_awprot),\n      .m_axi_awvalid(m_axi_awvalid),\n      .m_axi_awready(m_axi_awready),\n      .m_axi_awsize(m_axi_awsize),\n      .m_axi_awburst(m_axi_awburst),\n      .m_axi_awcache(m_axi_awcache),\n      .m_axi_awlen(m_axi_awlen),\n      .m_axi_awlock(m_axi_awlock),\n      .m_axi_awqos(m_axi_awqos),\n      .m_axi_awid(m_axi_awid),\n      .m_axi_awuser(m_axi_awuser),\n      .m_axi_wid(m_axi_wid),\n      .m_axi_wdata(m_axi_wdata),\n      .m_axi_wstrb(m_axi_wstrb),\n      .m_axi_wvalid(m_axi_wvalid),\n      .m_axi_wready(m_axi_wready),\n      .m_axi_wlast(m_axi_wlast),\n      .m_axi_wuser(m_axi_wuser),\n      .m_axi_bresp(m_axi_bresp),\n      .m_axi_bvalid(m_axi_bvalid),\n      .m_axi_bready(m_axi_bready),\n      .m_axi_buser(m_axi_buser),\n      .m_axi_bid(m_axi_bid),\n      .m_axi_araddr(m_axi_araddr),\n      .m_axi_arprot(m_axi_arprot),\n      .m_axi_arvalid(m_axi_arvalid),\n      .m_axi_arready(m_axi_arready),\n      .m_axi_arsize(m_axi_arsize),\n      .m_axi_arburst(m_axi_arburst),\n      .m_axi_arcache(m_axi_arcache),\n      .m_axi_arlen(m_axi_arlen),\n      .m_axi_arlock(m_axi_arlock),\n      .m_axi_arqos(m_axi_arqos),\n      .m_axi_arid(m_axi_arid),\n      .m_axi_aruser(m_axi_aruser),\n      .m_axi_rdata(m_axi_rdata),\n      .m_axi_rresp(m_axi_rresp),\n      .m_axi_rvalid(m_axi_rvalid),\n      .m_axi_rready(m_axi_rready),\n      .m_axi_rlast(m_axi_rlast),\n      .m_axi_ruser(m_axi_ruser),\n      .m_axi_rid(m_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign s_axi_awready = 0;\n     assign s_axi_wready  = 0;\n     assign s_axi_bid     = 0;\n     assign s_axi_bresp   = 0;\n     assign s_axi_buser   = 0;\n     assign s_axi_bvalid  = 0;\n     assign s_axi_arready = 0;\n     assign s_axi_rid     = 0;\n     assign s_axi_rdata   = 0;\n     assign s_axi_rresp   = 0;\n     assign s_axi_rlast   = 0;\n     assign s_axi_ruser   = 0;\n     assign s_axi_rvalid  = 0;\n\n  end else begin : gen_reg_slice  // Any normal reg-slice mode\n\n    axi_infrastructure_v1_1_0_axi2vector #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    axi2vector_0 ( \n      .s_axi_awid      ( s_axi_awid      ) ,\n      .s_axi_awaddr    ( s_axi_awaddr    ) ,\n      .s_axi_awlen     ( s_axi_awlen     ) ,\n      .s_axi_awsize    ( s_axi_awsize    ) ,\n      .s_axi_awburst   ( s_axi_awburst   ) ,\n      .s_axi_awlock    ( s_axi_awlock    ) ,\n      .s_axi_awcache   ( s_axi_awcache   ) ,\n      .s_axi_awprot    ( s_axi_awprot    ) ,\n      .s_axi_awqos     ( s_axi_awqos     ) ,\n      .s_axi_awuser    ( s_axi_awuser    ) ,\n      .s_axi_awregion  ( s_axi_awregion  ) ,\n      .s_axi_wid       ( s_axi_wid       ) ,\n      .s_axi_wdata     ( s_axi_wdata     ) ,\n      .s_axi_wstrb     ( s_axi_wstrb     ) ,\n      .s_axi_wlast     ( s_axi_wlast     ) ,\n      .s_axi_wuser     ( s_axi_wuser     ) ,\n      .s_axi_bid       ( s_axi_bid       ) ,\n      .s_axi_bresp     ( s_axi_bresp     ) ,\n      .s_axi_buser     ( s_axi_buser     ) ,\n      .s_axi_arid      ( s_axi_arid      ) ,\n      .s_axi_araddr    ( s_axi_araddr    ) ,\n      .s_axi_arlen     ( s_axi_arlen     ) ,\n      .s_axi_arsize    ( s_axi_arsize    ) ,\n      .s_axi_arburst   ( s_axi_arburst   ) ,\n      .s_axi_arlock    ( s_axi_arlock    ) ,\n      .s_axi_arcache   ( s_axi_arcache   ) ,\n      .s_axi_arprot    ( s_axi_arprot    ) ,\n      .s_axi_arqos     ( s_axi_arqos     ) ,\n      .s_axi_aruser    ( s_axi_aruser    ) ,\n      .s_axi_arregion  ( s_axi_arregion  ) ,\n      .s_axi_rid       ( s_axi_rid       ) ,\n      .s_axi_rdata     ( s_axi_rdata     ) ,\n      .s_axi_rresp     ( s_axi_rresp     ) ,\n      .s_axi_rlast     ( s_axi_rlast     ) ,\n      .s_axi_ruser     ( s_axi_ruser     ) ,\n      .s_awpayload ( s_awpayload ) ,\n      .s_wpayload  ( s_wpayload  ) ,\n      .s_bpayload  ( s_bpayload  ) ,\n      .s_arpayload ( s_arpayload ) ,\n      .s_rpayload  ( s_rpayload  ) \n    );\n    \n    axi_infrastructure_v1_1_0_vector2axi #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    vector2axi_0 ( \n      .m_awpayload    ( m_awpayload    ) ,\n      .m_wpayload     ( m_wpayload     ) ,\n      .m_bpayload     ( m_bpayload     ) ,\n      .m_arpayload    ( m_arpayload    ) ,\n      .m_rpayload     ( m_rpayload     ) ,\n      .m_axi_awid     ( m_axi_awid     ) ,\n      .m_axi_awaddr   ( m_axi_awaddr   ) ,\n      .m_axi_awlen    ( m_axi_awlen    ) ,\n      .m_axi_awsize   ( m_axi_awsize   ) ,\n      .m_axi_awburst  ( m_axi_awburst  ) ,\n      .m_axi_awlock   ( m_axi_awlock   ) ,\n      .m_axi_awcache  ( m_axi_awcache  ) ,\n      .m_axi_awprot   ( m_axi_awprot   ) ,\n      .m_axi_awqos    ( m_axi_awqos    ) ,\n      .m_axi_awuser   ( m_axi_awuser   ) ,\n      .m_axi_awregion ( m_axi_awregion ) ,\n      .m_axi_wid      ( m_axi_wid      ) ,\n      .m_axi_wdata    ( m_axi_wdata    ) ,\n      .m_axi_wstrb    ( m_axi_wstrb    ) ,\n      .m_axi_wlast    ( m_axi_wlast    ) ,\n      .m_axi_wuser    ( m_axi_wuser    ) ,\n      .m_axi_bid      ( m_axi_bid      ) ,\n      .m_axi_bresp    ( m_axi_bresp    ) ,\n      .m_axi_buser    ( m_axi_buser    ) ,\n      .m_axi_arid     ( m_axi_arid     ) ,\n      .m_axi_araddr   ( m_axi_araddr   ) ,\n      .m_axi_arlen    ( m_axi_arlen    ) ,\n      .m_axi_arsize   ( m_axi_arsize   ) ,\n      .m_axi_arburst  ( m_axi_arburst  ) ,\n      .m_axi_arlock   ( m_axi_arlock   ) ,\n      .m_axi_arcache  ( m_axi_arcache  ) ,\n      .m_axi_arprot   ( m_axi_arprot   ) ,\n      .m_axi_arqos    ( m_axi_arqos    ) ,\n      .m_axi_aruser   ( m_axi_aruser   ) ,\n      .m_axi_arregion ( m_axi_arregion ) ,\n      .m_axi_rid      ( m_axi_rid      ) ,\n      .m_axi_rdata    ( m_axi_rdata    ) ,\n      .m_axi_rresp    ( m_axi_rresp    ) ,\n      .m_axi_rlast    ( m_axi_rlast    ) ,\n      .m_axi_ruser    ( m_axi_ruser    ) \n    );\n    \n  end  // Reserve SI/MI branch\n\n  if ((C_REG_CONFIG_AW <= 9) && (C_RESERVE_MODE==0)) begin : aw\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 15) && (C_RESERVE_MODE==0)) begin : aw15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 16) && (C_RESERVE_MODE==0)) begin : aw16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) \n    )\n    aw_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if ((C_REG_CONFIG_W <= 9) && (C_RESERVE_MODE==0)) begin : w\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 15) && (C_RESERVE_MODE==0)) begin : w15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 16) && (C_RESERVE_MODE==0)) begin : w16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) \n    )\n    w_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if ((C_REG_CONFIG_B <= 9) && (C_RESERVE_MODE==0)) begin : b\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if ((C_REG_CONFIG_B == 15) && (C_RESERVE_MODE==0)) begin : b15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if ((C_REG_CONFIG_B == 16) && (C_RESERVE_MODE==0)) begin : b16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) \n    )\n    b_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if ((C_REG_CONFIG_AR <= 9) && (C_RESERVE_MODE==0)) begin : ar\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 15) && (C_RESERVE_MODE==0)) begin : ar15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 16) && (C_RESERVE_MODE==0)) begin : ar16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) \n    )\n    ar_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if ((C_REG_CONFIG_R <= 9) && (C_RESERVE_MODE==0)) begin : r\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 15) && (C_RESERVE_MODE==0)) begin : r15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 16) && (C_RESERVE_MODE==0)) begin : r16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) \n    )\n    r_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 4844}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\ngeSCzw9gYjFCv0Dn0YxOXxhH+GZFMePCQPK3AjT+zbjt1urPphGbRmSIP212qcXhU3u6qBayOOuP\nzGTUOznyYQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nOnCSRn8bnLy+eSxgkIEXKk5zY3JDppSX+6N3lQVX9PeSypgnQ/2z4GTpmoL+rdMoco6U9R4G1u4m\nE0xhKuM4ba9nEk7cLfAxOQqKqsWQrZaIEmzIr1ET+cp4jOMvYA/MsN4jh93kbuKcSDuJ8zN13DFX\nRemIkmekhFjPkyUS5qM=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nMSBAO7tnsBVh2XpVImbQvPkv1Ik+6Bw1D0e9n6H/Bw1mXnRXzm0RzPaEYAIFuluPbWglTrw4pQSr\nJI/DSdCg6087Xmb+Q5zKawFvuZahx4HgmrKxTL15lZwamiIpmu3LGyxaEH/VbYGM9Ky0jp5PyDKU\nJeskyx64XVUPlRklhMjIKCtYITsgROzqjs+d1jIc494zqnDADEz0msJP38WdzHgwLDQ0NamfpodX\nBUqMR71hgPx1Rvdt7HagUbkfyaG3/12LxFvpAblT7W0W6RKBFEFgFrxWRFaDw+jzj4jgl9g+sjY0\ncveJYAA4UpZJwPSDIWehjmS+mOinzlnl8UP7jw==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUtIiSU3lZ1iUKAuaJuT083jLC5QokBuxbJC/zVsWXf8ozOCIDAvtpSufF02lDCCaNNheB40dXQFS\nI8VBcTtdWzNr2vj/HmW17e10D6T6mqn/8t0HnWx9c3modRuXup0Too1mNTU5gTH+v3utogTO5ztm\nHbJZ/+5ov0tPkaeJufJl5L/RZAfLmRnRYybtx5bbc7XiGyWaVk6KunsaWtX5zJtVnMeUOkg0N8oL\nRBeyFp3tFqTN7ecNUp7zom6BjZ3fR6euRy36u1XviJsqBjcxzASI1k+bn2lDs3oEdXuMHoRvcuWL\nmmMddzjwWr43L7YoB/WBz/Tw7t6iYI5B6imPUA==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nAMZ17uwJyVzW4KyzjD/YjCrX2GlLIDwW9HSuEat97pn8ZQ7QpDPhFLNx09klp1fHQ8yb1KlxCqpm\nIjAljp4A5oQHWcBw/s+Xhtpin6GMDGjsmd5KmAD2J5DQmzqPazc0M8vNO+pGpCJogvWarX5XrP6U\n56l9vH5mfyPmbT/09Kw=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\noAGTk8IFmmwAT5eT+h5xMK7MsqYCJnsMll3rq17njNu6wbVX2TAoOlVC5DzNg9T5ce7gVnuLuFG/\nFgNSnTJx8TlbP73KxlDubmAVofR56G/yHzaJfJ0fwNhrfXm5AFgmFaKFPTKNkrG/qjdNuwUeA8p4\niHoj1zvPx50myVHXSpHLQ8n92DLWgMUX/57aPLbMHmYu/gsD0kHOuQ8Fr2Mi2DxufAvq1gzT0kc+\nlxSntoseL+X1HLSvmKpEkR/sjaz6P9omIzqKlmOhvLeTZVEZcUtukVN1HTrlol+4/pTFDztcz0tZ\nXqYZKVNB/igvn1iP/Fej8fpkaeJOrk1YgJZ6xw==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nHM0OWTHTT9qkiqicwldwQlaXCXhAavOkOLtzdsXybVEqcdGTuInS8Xvu2i7fjfGdnZjc+o4ZayFd\nadCXUGMQZ+7u79Rm71DMtV7WL4PMhXZmItLJgXQmNzajU211AuWse/CyD7Am9ZDJuQcIK0fcqZQI\nXVJU6sMESVWiSWdCuqkcQLSuSoBY7TVLmCDoTF9n7MlYfcxCkkK6d+2Xs/gjaWO59GZ3TbWhAQLc\n9hHL9YUJUTzZ8yPC8tX+DLS/YrniD3lBpquxXGcl1FxHKFTSpMG/6pTH+7Y5u1s29iqS/KYCCOfR\nPqg3ikxxR4ywBL+umX+Ijv+Hqgol6tBnCkWh/g==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nDQuK/YuairmUNmnTZFN/Tbbjjk202ciTMNZWiES7z/c8BYrmlnBses/x7XzAVxFxOTns+S6gcbxv\nlho3MoYQI3b1wxR93ymMpbFY2AAKqfTaYrt9nuBi+J66NUkNb4mO5Ysrmk/FyxUuVMw2JeKhCxVf\n1Lkw2weXEA2RSHrWxd8764IFSbBqKoKUTMuqLxHovRaQHDy/mOdyefGG7/6ywGbKjVTlE8lXVH8E\n8QodSYZ7p8uod81sVFzJL26a9Tqu+u2tOgD/WqMuxrio7zRkYYC5P+/FtxLC4GaIZ6LivaJuTLOF\nbkAMneaa5dlfamLnRyzDXUCJu/DFpJtH5s1eLQ==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nDL1JbuaDxIhP8ir0jAdx6nea42/rMQ2VXG8PZEGqMkgF/yLmK8+UcPNvmkEnUbVxq6WNxCUUYBOO\neroUXvKd3hB7aza+lE1PkczDRQpe4dZWQ8yHCUSbqj/KnUKU7sMHOSk5MiYcbBazdC+B/zdSxJsr\nsUmnOLgp/SqygmZW7/oDYMIYyOExEOrIPD4CH/xXZGlvuNs4OjdmaSus7kQp/iaUxQz03NGaMv3/\nEuIfORb3j+mQPwXwEBQhecy81p8ky3bmOS0LK+CPuz0LF3VVvrDnnXUSBCWa2WW6t7burmoHvgPV\noB2jrvwkS6dNjRJ7CoyGvV0N6d60kiD0LjZg6Q==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 2400)\n`pragma protect data_block\nNayj+Ml813fDniWORR2jtIBWLUnTKLU73quUTC0r5jwck/h8GoDq9XKw8BqI5v1J3nTgkNVm5atb\ncAw/VaO3NkhfBheJQbSR69Nrz/dOO5tggQHH5bhiVgkyJ10J0IJijCkqHTEM7eqAUpRB+C+swn77\n0UbAbjpA6iLxZtySLCkfu1IDmIuJVGQQu5gx5HhJOOS9sbBqYLpKFtMkq0ekmdT8uVsJas5Dn/rL\nFK6cI0u3hF6jx7C6EuRP9bts5JinWmopHabvdIuMWogq/jEOmvK/YWa2F6a22JfPI9md2SGv001Z\nNF3S+OFUqWLkWcQuQiK1EeStnUgfx0DKmP44Rh49vAuwvoCnEGtGPoJcuqCj8kkx2HperJBoPMXF\nbwOXyBsVw8smubJpJUklj/jkYQU7Mhn0+1DDK4kkK06W5VS0PwpcHI/NCpCrtst2FFbkesNH2SsO\n5KIGW+Cfb4QrEDe5XavyjtAdc7Kf/olEw1ZvNmIwyZXSdJcT54GFCi4KQPPRS9kiaadQLPQS/WUP\nwP3P3JdX9YvFC5Sp1yq2sPWuL1eMLRyNl339wIhus+/wM5aQSDi/pHmJmMEl1YLUa+mN6EenORTG\n5MU9xnSDDk5SD4ObbT9KWXjRTWogMOCapY1Tv1MWBzOTNzXGtVtAJBw4cxOHMG+OFF0yGvhE/AiV\nUJBEeJzP8L2Bj71c8RCxIViFz07rXhaFlBxMGxkdgTscOVxJtGiXqO970qc+E+YhnpZrgzpPog3A\nHIxK9BG2bcC2sSeQO+WCrtfMMdvVUNZHntYQpZozeGZF5OTZeeqs2I0PvZblmP7/srlzJ/JzetZ0\nCpTygxJF6W9HlXHv9qS2in1MDX5LvPjFtN0zKGyxUv4X8CFSqcYRW0lPxKh8dQ8KfIf1/+JRuMUW\nCO3I17UAoMQyc5PLA35Nis/x1CGOS2Zq5QgnlIBPpFv5JGoS0wKJ/bIyq0i0w+v4KWN5TrLYWJ84\nsMf45/+/nnmUoNq90k8SrWlnr9pxaqXZeklZOtEGejWc0oYa3+O2lYV0522Cm+XAuCiLIx1oRyxa\n+u6HnsKXvR9DGb1osgt9gANalMh//k8N88W7tvMLcXwdkFi3uvBg/oZZeRm+o8p5swkqfDh2gQuZ\nGJ1QE8KWN8hTZ9fEsScunk4GbuTk3dg05a1sMGm1gkRzTfiEVCzyn5Hi3pFpbikjAO7g/FLU6yiZ\npKzI2Crm4XPWRCfhwxycS8r2s63JspfJUZBW7tfCcbmQHYqHgxL3ZiEIV4N4tCF6rLQe8eu8xVI4\n/ReaCvAsFB9k7r6h7vh2b/kor3j4v+vAAZs3NBd5vlKFfHc3a2phzTdGn9/IodWpqPp66h+D0hMB\n8NQHJ3785F0Znfee4XxCQdXvwh03Pq+vWOHfhxdV+GL/oYI5/3eX0cZlwNXNhgrBE/jjCvh+/qf+\nEuYKKMASHjIYzBihs/pCIBjKCya9eF6CKxRfp3KTjZ2nu0k/P00aR1alNLtPJR6SD3wEBMa7yNgY\nByaV1EQovQeu24Klh9zavCXFUHc3h3j8MqHxZrNfI/eUyIDoEuURBHymJZ13GIYA+mWIFdrXIC84\nSlX5spcjNcB+mHif2EzCB6nJP3AE9aq8cpOJcQjhkcPZHkg2t9l5F5EupuAFUvvfcTXN/y6F3qIr\nThqLyFGwSiGzZX0AwRaNpyXuZKQsNz1WTzj1BjvDSTF1//OlAgzx0F1UZOuh9Hzv4+IBl0yGCHiR\noGXeQvMTSxI1D0BcFoc61ga1nbv3+QY2aYafMEJ+LKq2sz3mGk0Vpzo+swUVCYeveAb11ugkLVq9\nRa5FHeyN5v+RwxysgCDPo+jBUyzguryY6OBJBtBUXJV3Vrg8TEC1JNfIuiaQGmXiWvUj7VD3fgFP\nA/Pax3F+Unn9dJaEhfgG23dLGZyo/H32CTtiWZfkWBJV8/W3g040xdKdNl+Y7sBtjuGt0IdS8lWJ\nbomc8CybMXpVp9SQkhVlf4135WYYZuozj6Kt0dv581TbcnOPMEkTrRnU/XCQOVj9mHD8kDE8BGPs\nu1WPZBZQ1Tfgb5SDwQQf3XYTIQNAnDzjLrEPaxy7I36CFdPTpJXR+DrTmbYH416q/LusHMxfzhkE\nw+OkHqm6czWhunOkfPBoECoA9j609E2s6JDyqqdyNGGw3KsGIu3zyudgD+AeIlbr5wvld3VhQu+k\nGbD1GKPT9sOuQylU6aG0R75sAjP0/RSbLUhGUdAL1NeNa2Q5utBg4b7xY2znf8k43uQuH9gDftQK\nMoCj+4M/kY5vFOehA+mgPmocoo8+ta7JVcwiLjJPyYN/N7RIRvu0bpPfTeQM+6DijB5NSetCHZeW\nKLrP7l1+niGT/aEUEZej5w42fhW5sZHSiMRrLyLeDxPtaeUE82Q8OzcJqmXqsrFMkgyVYOS6vWRE\np8+5qxoxSzeQ36exOktW+E2/pJPFVJYv608U/e/KsJ18RpOpuwdPQeazasQl0zwh9u34LrhV6Hgs\nG8DKy0o62/rCo+JVEb1RdF37hXvTDGFF//rlcyBQgVtwCOJFFL5geugUbu5A/8AzBEN9Pzw0vxPV\nfUaRNNckCcVybD5F7BZ3ielbt42QOneOK6+07rP2GQq6wu4Kocbpi5WXkAwDwn9iEsJT6Vh3Xz9A\nGjEIelxMlGde1Ett9oxHhKcMYEnPyv4evAmG7EErwlTCQd+vp8tPPTmVvXbIJEpz4ViA5GiW8eTI\nk/BkHd7IGq64iYXdddJ63IxopIFrccFbADHVy2LXr73bfFWYkRzvShUlQXRs2nK8iLqkmlEeNa8u\nxaG3JQj0CYQCzTlqrKFs7AK8b8BwqaXmZ3FB9Xfj65H3mkW01gIq4i7sdVBBe4FgjsQAPdA+QPyP\nFymbOZEQQPblH3qHCFfiQ9DDi/zDZi26sar4BjLeoS6GuI2juEmSKZLMcHezPShGjMq7TDo25lD6\nlTlVWv5FmEIE4aI6UTNu4lJ3xl7a4lWJea95qzcitsplCEQA3mhp4zu9euRzSrneC01njKmDnrPH\nmqzSlSiWOcwitRn6BFaIcXktL6gU0l0wbOKHkv4u6Wd4kbpRfHuZGrrcUU9JHlIQn9e7Rhx3a8Le\nWewZ4FHJqc4gDvS+d8JPbCOb0K5VOINAjyn78G8320oCOfCyv3IKlkmyNHvqFcKzpNFcaza/1v/w\nwP46e8ZI\n`pragma protect end_protected\n", "num_lines": 126}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_master #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_SUPPORTS_NARROW = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1,\n   parameter [C_AXI_ADDR_WIDTH-1:0] C_AXI_ADDR = 0,  // Base address\n   parameter integer C_NUM_ADDR = 1,  // Number of address iterations; range 1..2**16 (fixed increment = 32'h10000\n   parameter integer C_NUM_ID = 1,  // Number of ID iterations; range 1..2**C_ID_WIDTH (base = 0; fixed increment = 1)\n   parameter integer C_NUM_LEN = 1,  // Number of LEN iterations; range 1..9 (base = 0; value = 2**i - 1)\n   parameter integer C_NUM_TRANS = 1  // Number of transactions; range >=1 (read and write)\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_awvalid,\n  input  wire                            m_axi_awready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_awburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_awlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_awlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_awid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]    m_axi_awuser = 'b0,\n  /**************** Write Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_wid,\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]      m_axi_wdata,\n  (* dont_touch=\"true\" *) output reg [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb = {(C_AXI_DATA_WIDTH/8){1'b1}},\n  (* dont_touch=\"true\" *) output wire                             m_axi_wvalid,\n  input  wire                            m_axi_wready,\n  (* dont_touch=\"true\" *) output wire                             m_axi_wlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]     m_axi_wuser = 'b0,\n  /**************** Write Response Channel Signals ****************/\n  input  wire [2-1:0]                    m_axi_bresp,\n  input  wire                            m_axi_bvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_bready,\n  input  wire [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]     m_axi_buser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_bid,\n  /**************** Read Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_arvalid,\n  input  wire                            m_axi_arready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_arburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_arlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_arlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_arid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]    m_axi_aruser = 'b0,\n  /**************** Read Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]      m_axi_rdata,\n  input  wire [2-1:0]                    m_axi_rresp,\n  input  wire                            m_axi_rvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_rready,\n  input  wire                            m_axi_rlast,\n  input  wire [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]     m_axi_ruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_rid,\n  /**************** System Signals ****************/\n  input  wire                            aclk,\n  input  wire                            aresetn\n  );\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n  localparam integer  P_NUM_ID_LOG = f_ceil_log2(C_NUM_ID);\n  localparam integer  P_NUM_ADDR_LOG = f_ceil_log2(C_NUM_ADDR);\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL==0 ? 8 : C_AXI_PROTOCOL==1 ? 4 : 1);\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer               P_M_AXI_DATA_BYTES = (C_AXI_DATA_WIDTH / 8);\n  localparam integer               P_M_AXI_DONE_WIDTH = f_ceil_log2(C_NUM_TRANS<2?2:C_NUM_TRANS);\n  localparam integer               P_M_AXI_SIZE = f_ceil_log2(C_AXI_DATA_WIDTH)-3;\n\n  /**************** Internal Wires/Regs - Global ****************/\n   wire                            done;\n    wire                            dummy ;\n  reg                         done_i;\n  reg                         done_sel;\n  wire                         done_cycle;\n  reg                          done_d1 = 1'b0;\n  reg                   areset = 1'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] arcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] rcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [3:0]                    acc_r_i = 4'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] awcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] wcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] bcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [2:0]                    acc_b_i = 3'b0;\n\n  // Register Reset\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    \n    /**************** Internal Wires/Regs - Read Channels ****************/\n    wire                         read_xaction_done_i;\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_arid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_ADDR_WIDTH:0]      araddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  arprot_i = 3'b0;\n    reg [3-1:0]                  arsize_i = 3'b0;\n    reg [2-1:0]                  arburst_i = 2'b0;\n    reg [4-1:0]                  arcache_i = 4'b0;\n    reg [2-1:0]                  arlock_i = 2'b0;\n    reg [P_LEN_WIDTH-1:0]     arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [4-1:0]                  arqos_i = 4'b0;\n    reg [P_ID_WIDTH-1:0]        arid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [2-1:0]                  rresp_i = 2'b00;\n    reg [C_AXI_RUSER_WIDTH:0]   ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      rid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_arvalid_i = 1'b0;\n    reg                        m_axi_rready_i = 1'b0;\n    reg [P_NUM_ADDR_LOG:0]    araddr_cnt = 0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign read_xaction_done_i = m_axi_rvalid && m_axi_rready_i && ((C_AXI_PROTOCOL==2)?1'b1:m_axi_rlast);\n    assign m_axi_arvalid = m_axi_arvalid_i;\n    assign m_axi_rready = m_axi_rready_i;\n    assign m_axi_araddr = m_axi_araddr_i;\n    assign m_axi_arlen = m_axi_arlen_i;\n    always @(posedge aclk) begin\n      m_axi_arprot <= dummy ? arprot_i : 3'b000;\n      m_axi_arsize <= dummy ? arsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_arburst <= dummy ? arburst_i : 2'b01;\n      m_axi_arlock <= dummy ? arlock_i : 1'b0;\n      m_axi_arcache <= dummy ? arcache_i : 4'h3;\n      m_axi_arqos <= dummy  ? arqos_i : 4'h0;\n      m_axi_aruser <= dummy ? aruser_i : 0;\n    end\n  \n    //**********************************************\n    // Read Channel: ARVALID, ARADDR, ARLEN, RREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_arvalid_i <= 1'b0;\n        arcnt_i <= C_NUM_TRANS;\n        m_axi_arlen_i <= 0;\n        m_axi_araddr_i <= C_AXI_ADDR;\n        m_axi_arid_i <= 1;\n        araddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_arready & m_axi_arvalid_i) begin\n          arcnt_i <= arcnt_i - 1;\n          if (araddr_cnt == 1) begin\n            m_axi_araddr_i <= dummy ? araddr_i : C_AXI_ADDR;\n            araddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_araddr_i <= m_axi_araddr_i + 32'h10000;\n            araddr_cnt <= araddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_arlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_arlen_i <= dummy ? arlen_i : 0;\n          end else begin\n            m_axi_arlen_i <= (m_axi_arlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_arid_i == C_NUM_ID)) begin\n            m_axi_arid <= dummy ? arid_i : 0;\n            m_axi_arid_i <= 1;\n          end else begin\n            m_axi_arid <= m_axi_arid_i;\n            m_axi_arid_i <= m_axi_arid_i + 1;\n          end\n          if (arcnt_i == 1) begin\n            m_axi_arvalid_i <= 1'b0;\n          end\n        end else if (arcnt_i != 0) begin\n          m_axi_arvalid_i <= 1'b1;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      araddr_i <= {araddr_i, ~araddr_i[C_AXI_ADDR_WIDTH]};\n      arprot_i <= {arprot_i, ~arprot_i[3-1]};\n      arlen_i <= {arlen_i, ~arlen_i[P_LEN_WIDTH-1]};\n      arsize_i <= {arsize_i, ~arsize_i[3-1]};\n      arburst_i <= {arburst_i, ~arburst_i[2-1]};\n      arlock_i <= {arlock_i, ~arlock_i[2-1]};\n      arcache_i <= {arcache_i, ~arcache_i[4-1]};\n      arqos_i <= {arqos_i, ~arqos_i[4-1]};\n      aruser_i <= {aruser_i, ~aruser_i[C_AXI_ARUSER_WIDTH]};\n      arid_i <= {arid_i, ~arid_i[P_ID_WIDTH-1]};\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        m_axi_rready_i <= 1'b0;\n        rcnt_i <= C_NUM_TRANS;\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        rresp_i <= {2{1'b0}};\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n        rid_i <= {P_ID_WIDTH{1'b0}};\n        acc_r_i <= 4'b0;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_rvalid & m_axi_rready_i) begin\n          m_axi_rready_i <= 1'b0;\n          rdata_i <= m_axi_rdata;\n            acc_r_i[0] <= rdata_i[0];\n          rresp_i <= m_axi_rresp;\n            acc_r_i[1] <= rresp_i[0];\n          ruser_i <= m_axi_ruser;\n            acc_r_i[2] <= ruser_i[0];\n          rid_i <= m_axi_rid;\n            acc_r_i[3] <= rid_i[0];\n          if (m_axi_rlast) begin\n            rcnt_i <= rcnt_i - 1;\n          end\n        end else begin\n          rdata_i <= rdata_i>>1;\n          rresp_i <= rresp_i>>1;\n          ruser_i <= ruser_i>>1;\n          rid_i <= rid_i>>1;\n          acc_r_i <= acc_r_i>>1;\n          if (m_axi_rvalid) begin\n            m_axi_rready_i <= 1'b1;\n          end\n        end\n      end\n    end\n    \n    assign dummy = rdata_i[0];\n    \n    \n\n    /**************** Internal Wires/Regs - Write Channels ****************/\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_awid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [8-1:0]                  xfer_w_i = 8'h00;\n    wire                         write_burst_done_i;\n    reg [C_AXI_ADDR_WIDTH:0]      awaddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  awprot_i = 3'b0;\n    reg [P_LEN_WIDTH-1:0]     awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [3-1:0]                  awsize_i = 3'b0;\n    reg [2-1:0]                  awburst_i = 2'b0;\n    reg [4-1:0]                  awcache_i = 4'b0;\n    reg [2-1:0]                  awlock_i = 2'b0;\n    reg [4-1:0]                  awqos_i = 4'b0;\n    reg [P_ID_WIDTH:0]        awid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_AWUSER_WIDTH:0]    awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg [P_M_AXI_DATA_BYTES-1:0] wstrb_i = {P_M_AXI_DATA_BYTES{1'b1}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]        wid_i = {P_ID_WIDTH{1'b0}};\n    reg [2-1:0]                  bresp_i = 2'b00;\n    reg [C_AXI_BUSER_WIDTH:0]   buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      bid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_awvalid_i = 1'b0;\n    reg                        m_axi_wvalid_i = 1'b0;\n    reg                        m_axi_bready_i = 1'b0;\n    reg                        m_axi_wlast_i = 1'b0;\n    reg                        m_axi_wid_i = {P_ID_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]     wlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [P_NUM_ADDR_LOG:0]    awaddr_cnt = 0;\n  \n    /**************** Assign Write Channel Outputs ****************/\n    assign m_axi_wdata = {wdata_i, done};\n    assign write_burst_done_i = m_axi_wready && m_axi_wvalid_i && ((C_AXI_PROTOCOL==2) || m_axi_wlast_i);\n    assign m_axi_awvalid = m_axi_awvalid_i;\n    assign m_axi_wvalid = m_axi_wvalid_i;\n    assign m_axi_bready = m_axi_bready_i;\n    assign m_axi_wlast = m_axi_wlast_i;\n    assign m_axi_awaddr = m_axi_awaddr_i;\n    assign m_axi_awlen = m_axi_awlen_i;\n    assign m_axi_wid = m_axi_wid_i;\n    always @(posedge aclk) begin\n      m_axi_awprot <= dummy ? awprot_i : 3'b000;\n      m_axi_awsize <= dummy ? awsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_awburst <= dummy ? awburst_i : 2'b01;\n      m_axi_awlock <= dummy ? awlock_i : 1'b0;\n      m_axi_awcache <= dummy ? awcache_i : 4'h3;\n      m_axi_awqos <= dummy ? awqos_i : 4'h0;\n      m_axi_wstrb <= dummy ? wstrb_i : {P_M_AXI_DATA_BYTES{1'b1}};\n      m_axi_awuser <= dummy ?  awuser_i : 0;\n      m_axi_wuser <= dummy ?  wuser_i : 0;\n    end\n  \n    //**********************************************\n    // Write Channel: AWVALID, AWADDR, AWLEN, WVALID, WLAST, BREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_awvalid_i <= 1'b0;\n        m_axi_wvalid_i <= 1'b0;\n        awcnt_i <= C_NUM_TRANS;\n        wcnt_i <= C_NUM_TRANS;\n        xfer_w_i <= 8'h00;\n        m_axi_awlen_i <= 0;\n        m_axi_awaddr_i <= C_AXI_ADDR;\n        m_axi_awid_i <= 1;\n        m_axi_wid_i <= 0;\n        m_axi_wlast_i <= 1'b0;\n        wlen_i <= 0;\n        wid_i <= 0;\n        awaddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_awvalid_i <= 1'b0;\n          awcnt_i <= awcnt_i - 1;\n          if (awaddr_cnt == 1) begin\n            m_axi_awaddr_i <= dummy ? awaddr_i : C_AXI_ADDR;\n            awaddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_awaddr_i <= m_axi_awaddr_i + 32'h10000;\n            awaddr_cnt <= awaddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_awlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_awlen_i <= dummy ? awlen_i : 0;\n          end else begin\n            m_axi_awlen_i <= (m_axi_awlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_awid_i == C_NUM_ID)) begin\n            m_axi_awid <= dummy ? awid_i : 0;\n            m_axi_awid_i <= 1;\n          end else begin\n            m_axi_awid <= m_axi_awid_i;\n            m_axi_awid_i <= m_axi_awid_i + 1;\n          end\n        end else if (~m_axi_wvalid_i) begin\n          if (awcnt_i != 0) begin\n            m_axi_awvalid_i <= 1'b1;\n          end\n        end\n  \n        /**************** Write Data Channel ****************/\n\n        if (m_axi_wready && m_axi_wvalid_i) begin\n          xfer_w_i <= xfer_w_i - 1'b1;\n          if (m_axi_wlast_i) begin\n            m_axi_wvalid_i <= 1'b0;\n            wcnt_i <= wcnt_i - 1'b1;\n          end else begin\n            m_axi_wlast_i <=  (xfer_w_i == 1);\n          end\n        end else if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_wvalid_i <= 1'b1;\n          xfer_w_i <= m_axi_awlen_i;\n          m_axi_wlast_i <= (m_axi_awlen_i==0);\n          m_axi_wid_i <= m_axi_awid_i;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: WDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        wdata_i <= (m_axi_wvalid_i && m_axi_wready) ? {wdata_i[C_AXI_DATA_WIDTH-2 : 0], ~wdata_i[C_AXI_DATA_WIDTH-1]} : wdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      awaddr_i <= {awaddr_i, ~awaddr_i[C_AXI_ADDR_WIDTH]};\n      awprot_i <= {awprot_i[3-2:0], ~awprot_i[3-1]};\n      wstrb_i <= {wstrb_i, ~wstrb_i[C_AXI_DATA_WIDTH/8-1]};\n      awlen_i <= {awlen_i, ~awlen_i[P_LEN_WIDTH-1]};\n      awsize_i <= {awsize_i, ~awsize_i[3-1]};\n      awburst_i <= {awburst_i, ~awburst_i[2-1]};\n      awlock_i <= {awlock_i, ~awlock_i[2-1]};\n      awcache_i <= {awcache_i, ~awcache_i[4-1]};\n      awqos_i <= {awqos_i, ~awqos_i[4-1]};\n      awid_i <= {awid_i, ~awid_i[P_ID_WIDTH-1]};\n      awuser_i <= {awuser_i, ~awuser_i[C_AXI_AWUSER_WIDTH]};\n      wuser_i <= {wuser_i, ~wuser_i[C_AXI_WUSER_WIDTH]};\n    end\n  \n    //**********************************************\n    // Write Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_bready_i <= 1'b0;\n        bcnt_i <= C_NUM_TRANS;\n        bresp_i <= {2{1'b0}};\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n        bid_i <= {P_ID_WIDTH{1'b0}};\n        acc_b_i <= 3'b0;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_bvalid & m_axi_bready_i) begin\n          m_axi_bready_i <= 1'b0;\n          bresp_i <= m_axi_bresp;\n            acc_b_i[0] <= bresp_i[0];\n          buser_i <= m_axi_buser;\n            acc_b_i[1] <= buser_i[0];\n          bid_i <= m_axi_bid;\n            acc_b_i[2] <= bid_i[0];\n          bcnt_i <= bcnt_i - 1;\n        end else begin\n          bresp_i <= bresp_i>>1;\n          buser_i <= buser_i>>1;\n          bid_i <= bid_i>>1;\n          acc_b_i <= acc_b_i>>1;\n          if (m_axi_bvalid) begin\n            m_axi_bready_i <= 1'b1;\n          end\n        end\n      end\n    end\n\n\n  //**********************************************\n  // Assert Done\n  //**********************************************\n  always @(posedge aclk) begin\n    if (~aresetn) begin\n      done_d1 <= 1'b0;\n    end else begin\n      done_d1 <= done_i;\n    end\n  end\n\n  assign done = done_sel ? done_i : done_d1;\n  assign done_cycle = done_i & ~done_d1;\n  \n  always @ * begin\n    if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_readonly_done\n       done_i = rcnt_i==0;\n       done_sel = acc_r_i[0];\n    end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_writeonly_done\n       done_i = bcnt_i==0;\n       done_sel = acc_b_i[0];\n    end else begin : gen_readwrite_done\n       done_i = (rcnt_i==0) && (bcnt_i==0);\n       done_sel = acc_r_i[0] ^ acc_b_i[0];\n    end\n  end\n  \nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n  input  wire [3-1:0]                   s_axi_awprot,\n  input  wire                           s_axi_awvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_awready,\n  input  wire [3-1:0]                   s_axi_awsize,\n  input  wire [2-1:0]                   s_axi_awburst,\n  input  wire [4-1:0]                   s_axi_awcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_awlen,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_awlock,\n  input  wire [4-1:0]                   s_axi_awqos,\n  input  wire [4-1:0]                   s_axi_awregion,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_awid,\n  input  wire [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]   s_axi_awuser,\n  /**************** Write Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n  input  wire                           s_axi_wvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_wready,\n  input  wire                           s_axi_wlast,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_wid,\n  input  wire [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]    s_axi_wuser,\n  /**************** Write Response Channel Signals ****************/\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_bresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_bvalid,\n  input  wire                           s_axi_bready,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]    s_axi_buser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_bid = 'b0,\n  /**************** Read Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n  input  wire [3-1:0]                   s_axi_arprot,\n  input  wire                           s_axi_arvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_arready,\n  input  wire [3-1:0]                   s_axi_arsize,\n  input  wire [2-1:0]                   s_axi_arburst,\n  input  wire [4-1:0]                   s_axi_arcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_arlock,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_arlen,\n  input  wire [4-1:0]                   s_axi_arqos,\n  input  wire [4-1:0]                   s_axi_arregion,\n  input  wire [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]   s_axi_aruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_arid,\n  /**************** Read Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_rresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rvalid,\n  input  wire                           s_axi_rready,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]    s_axi_ruser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_rid = 'b0,\n  /**************** System Signals ****************/\n  input  wire                           aclk,\n  input  wire                           aresetn\n   );\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL == 1) ? 4 : 8;\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer P_S_AXI_DATA_BYTES = 32/8;\n  localparam integer P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n\n  /**************** Internal Wires/Regs - Global ****************/\n  reg                   areset = 1'b0;\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    /**************** Internal Wires/Regs - Read Channels ****************/\n    reg [8-1:0]                   xfer_r_cnt = 8'h00;\n    reg [16-1:0]                  arcnt_i = 16'h0000;\n    wire                          read_xaction_done_i;\n    reg [C_AXI_DATA_WIDTH-1:0]     rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]      arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg                           arvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     araddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   arprot_i = 3'b000;\n    reg [3-1:0]                   arsize_i = 3'b000;\n    reg [2-1:0]                   arburst_i = 2'b00;\n    reg [4-1:0]                   arcache_i = 4'b0000;\n    reg [1-1:0]     arlock_i = 1'b0;\n    reg [4-1:0]                   arqos_i = 4'b0000;\n    reg [4-1:0]                   arregion_i = 4'b0000;\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_RUSER_WIDTH:0]     ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_ar_i = 9'b0;\n    reg                           s_axi_rvalid_i = 1'b0;\n    reg                           s_axi_arready_i = 1'b0;\n    reg                           s_axi_rlast_i = 1'b0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign s_axi_rdata = rdata_i;\n    assign read_xaction_done_i = (s_axi_rready && s_axi_rvalid_i && s_axi_rlast_i);\n    assign s_axi_rvalid = s_axi_rvalid_i;\n    assign s_axi_arready = s_axi_arready_i;\n    assign s_axi_rlast = s_axi_rlast_i;\n    //**********************************************\n    // Read Channel: ARREADY, RVALID, RLAST, RID\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        xfer_r_cnt <= 8'h00;\n        arcnt_i <= 16'h0000;\n        arlen_i <= {P_LEN_WIDTH{1'b0}};\n        s_axi_rlast_i <= 1'b0;\n      end else begin\n        /**************** Read Address Channel ****************/\n        // arready\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_arready_i <= 1'b0;\n          arcnt_i <= arcnt_i + 1'b1;\n        end else if (~s_axi_rvalid_i) begin\n          s_axi_arready_i <= 1'b1;\n        end\n  \n        /**************** Read Data Channel ****************/\n        // rvalid\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_rvalid_i <= 1'b1;\n          s_axi_rid <= s_axi_arid;\n          s_axi_ruser <= ruser_i;\n        end else if(read_xaction_done_i) begin\n          s_axi_rvalid_i <= 1'b0;\n        end\n  \n        // rlast\n        if(s_axi_rready && s_axi_rvalid_i) begin\n          xfer_r_cnt <= xfer_r_cnt - 1;\n          if(xfer_r_cnt == 1) begin\n            s_axi_rlast_i <= 1'b1;\n          end\n        end else if(s_axi_arready_i && s_axi_arvalid) begin\n          xfer_r_cnt <= s_axi_arlen;\n          s_axi_rlast_i <= (s_axi_arlen==0);\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Read Channel: RDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        rdata_i <= (s_axi_rready && s_axi_rvalid_i) ? {rdata_i[C_AXI_DATA_WIDTH-2 : 0], ~rdata_i[C_AXI_DATA_WIDTH-1]} : rdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_rresp <= {2{1'b0}};\n      end else if (~s_axi_rvalid_i) begin\n        s_axi_rresp <= {acc_ar_i[0], 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n      end else begin\n        ruser_i <= (s_axi_arready_i && s_axi_arvalid) ? {ruser_i, ~ruser_i[C_AXI_RUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        araddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        arprot_i <= {3{1'b0}};\n        arsize_i <= {3{1'b0}};\n        arburst_i <= {2{1'b0}};\n        arcache_i <= {4{1'b0}};\n        arlock_i <= {1{1'b0}};\n        arqos_i <= {4{1'b0}};\n        arregion_i <= {4{1'b0}};\n        aruser_i <= {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n        acc_ar_i <= 9'b0;\n      end else if (s_axi_arvalid) begin\n        // Register Inputs\n        araddr_i <= s_axi_araddr;\n          acc_ar_i[0] <= araddr_i[0];\n        arprot_i <= s_axi_arprot;\n          acc_ar_i[1] <= arprot_i[0];\n        arsize_i <= s_axi_arsize;\n          acc_ar_i[2] <= arsize_i[0];\n        arburst_i <= s_axi_arburst;\n          acc_ar_i[3] <= arburst_i[0];\n        arcache_i <= s_axi_arcache;\n          acc_ar_i[4] <= arcache_i[0];\n        arlock_i <= s_axi_arlock;\n          acc_ar_i[5] <= arlock_i[0];\n        arqos_i <= s_axi_arqos;\n          acc_ar_i[6] <= arqos_i[0];\n        arregion_i <= s_axi_arregion;\n          acc_ar_i[7] <= arregion_i[0];\n        aruser_i <= s_axi_aruser;\n          acc_ar_i[8] <= aruser_i[0];\n      end else begin\n        araddr_i <= araddr_i>>1;\n        arprot_i <= arprot_i>>1;\n        arsize_i <= arsize_i>>1;\n        arburst_i <= arburst_i>>1;\n        arcache_i <= arcache_i>>1;\n        arlock_i <= arlock_i>>1;\n        arqos_i <= arqos_i>>1;\n        arregion_i <= arregion_i>>1;\n        aruser_i <= aruser_i>>1;\n        acc_ar_i <= acc_ar_i>>1;\n      end\n    end\n  \n  \n    /**************** Internal Wires/Regs - Write Channels ****************/\n    wire                          write_burst_done_i;\n    reg [16-1:0]                  awcnt_i = 16'h0000;\n    reg                           awvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     awaddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   awprot_i = 3'b000;\n    reg [3-1:0]                   awsize_i = 3'b000;\n    reg [2-1:0]                   awburst_i = 2'b00;\n    reg [4-1:0]                   awcache_i = 4'b0000;\n    reg [P_LEN_WIDTH-1:0]      awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [1-1:0]     awlock_i = 1'b0;\n    reg [4-1:0]                   awqos_i = 4'b0000;\n    reg [4-1:0]                   awregion_i = 4'b0000;\n    reg [C_AXI_AWUSER_WIDTH:0]     awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg                           wvalid_i = 1'b0;\n    reg [C_AXI_DATA_WIDTH-1:0]     wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH/8-1:0]   wstrb_i = {(C_AXI_DATA_WIDTH/8){1'b0}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_BUSER_WIDTH:0]     buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_aw_i = 9'b0;\n    reg [3:0]                     acc_w_i = 4'b0;\n    reg                           s_axi_bvalid_i = 1'b0;\n    reg                           s_axi_awready_i = 1'b0;\n    reg                           s_axi_wready_i = 1'b0;\n    /**************** Assign Write Channel Outputs ****************/\n    assign write_burst_done_i =s_axi_wready_i && s_axi_wvalid && ((C_AXI_PROTOCOL == 2) ? 1'b1 : s_axi_wlast);\n    assign s_axi_bvalid = s_axi_bvalid_i;\n    assign s_axi_awready = s_axi_awready_i;\n    assign s_axi_wready = s_axi_wready_i;\n  \n    //**********************************************\n    // Write Channel: AWREADY, WREADY, BVALID, BID\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awcnt_i <= 16'h0000;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        /**************** Write Address Channel ****************/\n        // awready\n        if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_awready_i <= 1'b0;\n          awcnt_i <= awcnt_i + 1'b1;\n          s_axi_bid <= s_axi_awid;\n          s_axi_buser <= buser_i;\n        end else if(~s_axi_wready_i & ~s_axi_bvalid_i) begin\n          s_axi_awready_i <= 1'b1;\n        end\n  \n        /**************** Write Data Channel ****************/\n        // wready\n        if(write_burst_done_i) begin\n          s_axi_wready_i <= 1'b0;\n        end else if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_wready_i <= 1'b1;\n        end\n  \n        /**************** Write Response Channel ****************/\n        // bvalid\n        if(write_burst_done_i) begin\n          s_axi_bvalid_i <= 1'b1;\n        end else if(s_axi_bready && s_axi_bvalid_i) begin\n          s_axi_bvalid_i <= 1'b0;\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Write Channel: BRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_bresp <= {2{1'b0}};\n      end else if (~s_axi_bvalid_i) begin\n        s_axi_bresp <= {(acc_aw_i[0] ^ acc_w_i[0]), 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: BUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (aresetn) begin\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n      end else begin\n        buser_i <= (s_axi_awready_i && s_axi_awvalid) ? {buser_i, ~buser_i[C_AXI_BUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Write Address Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awaddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        awprot_i <= {3{1'b0}};\n        awsize_i <= {3{1'b0}};\n        awburst_i <= {2{1'b0}};\n        awcache_i <= {4{1'b0}};\n        awlen_i <= {P_LEN_WIDTH{1'b0}};\n        awlock_i <= {1{1'b0}};\n        awqos_i <= {4{1'b0}};\n        awregion_i <= {4{1'b0}};\n        awuser_i <= {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n        acc_aw_i <= 9'b0;\n      end else if (s_axi_awvalid) begin\n        // Register Inputs\n        awaddr_i <= s_axi_awaddr;\n          acc_aw_i[0] <= awaddr_i[0];\n        awprot_i <= s_axi_awprot;\n          acc_aw_i[1] <= awprot_i[0];\n        awsize_i <= s_axi_awsize;\n          acc_aw_i[2] <= awsize_i[0];\n        awburst_i <= s_axi_awburst;\n          acc_aw_i[3] <= awburst_i[0];\n        awcache_i <= s_axi_awcache;\n          acc_aw_i[4] <= awcache_i[0];\n        awlock_i <= s_axi_awlock;\n          acc_aw_i[5] <= awlock_i[0];\n        awqos_i <= s_axi_awqos;\n          acc_aw_i[6] <= awqos_i[0];\n        awregion_i <= s_axi_awregion;\n          acc_aw_i[7] <= awregion_i[0];\n        awuser_i <= s_axi_awuser;\n          acc_aw_i[8] <= awuser_i[0];\n      end else begin\n        awaddr_i <= awaddr_i>>1;\n        awprot_i <= awprot_i>>1;\n        awsize_i <= awsize_i>>1;\n        awburst_i <= awburst_i>>1;\n        awcache_i <= awcache_i>>1;\n        awlock_i <= awlock_i>>1;\n        awqos_i <= awqos_i>>1;\n        awregion_i <= awregion_i>>1;\n        awuser_i <= awuser_i>>1;\n        acc_aw_i <= acc_aw_i>>1;\n      end\n    end\n  \n    //**********************************************\n    // Write Data Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        wstrb_i <= {(C_AXI_DATA_WIDTH/8){1'b0}};\n        wuser_i <= {(C_AXI_WUSER_WIDTH+1){1'b0}};\n        acc_w_i <= 4'b0;\n      end else if (s_axi_wvalid) begin\n        // Register Inputs\n        wdata_i <= s_axi_wdata;\n          acc_w_i[0] <= wdata_i[0];\n        wstrb_i <= s_axi_wstrb;\n          acc_w_i[1] <= wstrb_i[0];\n        wuser_i <= s_axi_wuser;\n          acc_w_i[2] <= wuser_i[0];\n      end else begin\n        wdata_i <= wdata_i>>1;\n        wstrb_i <= wstrb_i>>1;\n        wuser_i <= wuser_i>>1;\n        acc_w_i <= acc_w_i>>1;\n      end\n    end\n  \nendmodule\n\n\n\n//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_22_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \n(* autopipeline_module=\"yes\" *)\nmodule axi_register_slice_v2_1_22_auto_slr #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n    wire                    handshake_pipe;\n    wire                    ready_pipe;\n    wire [C_DATA_WIDTH-1:0] payload_pipe;\n    (* keep=\"true\" *)                                                                reg  s_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  s_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  s_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  s_areset_resp2 = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  m_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  m_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_areset_resp2 = 1'b0;\n    \n  // Global Reset pipelining\n  \n    always @(posedge ACLK) begin\n      s_aclear       <= ~ARESETN;\n      s_areset_fwd   <= ~ARESETN; \n      s_areset_resp  <= s_areset_fwd;  // Auto-pipeline\n      s_areset_resp2 <= s_areset_resp; // Auto-pipeline\n    end\n    \n    always @(posedge ACLK) begin\n      m_aclear       <= ~ARESETN;\n      m_areset_fwd   <= ~ARESETN; \n      m_areset_resp  <= m_areset_fwd;  // Auto-pipeline\n      m_areset_resp2 <= m_areset_resp; // Auto-pipeline\n    end\n    \n  // Source-side submodule\n    \n    axi_register_slice_v2_1_22_auto_src #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_src\n      (\n       .ACLK             (ACLK),    \n       .s_aclear         (s_aclear),\n       .s_areset_resp2   (s_areset_resp2),  \n       .S_VALID          (S_VALID),  \n       .S_READY          (S_READY), \n       .S_PAYLOAD_DATA   (S_PAYLOAD_DATA),\n       .ready_pipe        (ready_pipe), \n       .handshake_pipe    (handshake_pipe),\n       .payload_pipe      (payload_pipe)  \n      );\n    \n  // Destination-side submodule\n    \n    axi_register_slice_v2_1_22_auto_dest #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_dest\n      (\n       .ACLK           (ACLK),    \n       .m_aclear       (m_aclear),\n       .m_areset_resp2 (m_areset_resp2),  \n       .M_READY        (M_READY), \n       .M_VALID        (M_VALID),  \n       .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n       .handshake_pipe  (handshake_pipe),\n       .ready_pipe      (ready_pipe),  \n       .payload_pipe    (payload_pipe)  \n      );\n    \nendmodule  // auto_slr\n\nmodule axi_register_slice_v2_1_22_auto_src #\n  (\n   parameter integer C_DATA_WIDTH = 32\n  )\n  (\n   input  wire ACLK,\n   input  wire s_aclear,\n   input  wire s_areset_resp2,\n   input  wire S_VALID,\n   input  wire ready_pipe,\n   output wire S_READY,\n   output wire handshake_pipe,\n   output wire  [C_DATA_WIDTH-1:0] payload_pipe,\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA\n   );\n    \n   (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  [C_DATA_WIDTH-1:0] payload_pipe_r;\n    (* keep=\"true\" *) reg [2:0] s_aresetn_resp4 = 3'b000;\n    wire s_aresetn_resp3;\n    wire s_aresetn_d;\n    wire s_aresetn_q;\n    wire s_handshake_d;\n    wire s_ready_i;\n    \n    assign S_READY = s_ready_i & s_aresetn_q;\n    assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;\n    assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;\n    assign payload_pipe = payload_pipe_r;\n    \n    always @(posedge ACLK or posedge s_aclear) begin\n      if (s_aclear) begin\n        s_aresetn_resp4 <= 3'b000;\n      end else begin\n        s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      payload_pipe_r <= S_PAYLOAD_DATA;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) s_aresetn_resp3_inst (\n        .Q   (s_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~s_areset_resp2)\n     );\n    \n    // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (s_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_aresetn_d)\n     );\n    \n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (handshake_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_handshake_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (s_ready_i),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (ready_pipe)\n     );\n    \nendmodule  // auto_src\n\nmodule axi_register_slice_v2_1_22_auto_dest #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   input  wire ACLK,\n   input  wire m_aclear,\n   input  wire m_areset_resp2,\n   input  wire M_READY,\n   input  wire handshake_pipe,\n   output wire ready_pipe,\n   output wire M_VALID,\n   input  wire [C_DATA_WIDTH-1:0] payload_pipe,\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n   );\n    \n    (* keep=\"true\" *) reg [2:0] m_aresetn_resp4 = 3'b000;\n    wire m_aresetn_resp3;\n    wire m_aresetn_d;\n    wire m_aresetn_q;\n    wire m_valid_i;\n    wire pop;\n    wire m_ready_d;\n    wire m_handshake_q;\n    reg  [C_DATA_WIDTH-1:0] m_payload_q;\n    \n    assign M_VALID = m_valid_i;\n    assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;\n    assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;\n    assign pop     = M_READY & m_valid_i;\n    \n    always @(posedge ACLK or posedge m_aclear) begin\n      if (m_aclear) begin\n        m_aresetn_resp4 <= 3'b000;\n      end else begin\n        m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      m_payload_q <= payload_pipe;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) m_aresetn_resp3_inst (\n        .Q   (m_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~m_areset_resp2)\n     );\n    \n    // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (m_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_aresetn_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (m_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (handshake_pipe)\n     );\n    \n    (* autopipeline_group=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (ready_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_ready_d)\n     );\n    \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  (5)  \n      )\n      srl_fifo\n      (\n       .aclk    (ACLK),    \n       .areset  (~m_aresetn_q),\n       .aclear  (m_aclear),  \n       .s_mesg  (m_payload_q),  \n       .s_valid (m_handshake_q), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      );\n    \nendmodule  // auto_dest\n\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      reg s_valid_d;\n      reg s_ready_d = 1'b0;\n      reg s_ready_reg = 1'b0;\n      reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_22_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_RESP_MIDDLE2_LATENCY = C_PIPELINES_SLAVE + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_22_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      .ACLK           (ACLK),\n      .ARESETN         (ARESETN),\n      .S_PAYLOAD_DATA (S_PAYLOAD_DATA),\n      .S_VALID        (S_VALID),\n      .S_READY        (S_READY),\n      .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n      .M_VALID        (M_VALID),\n      .M_READY        (M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_reset;\n    wire src_ready;\n    wire dummy_reset;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  ( C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( dummy_reset   ) ,\n        .laguna_s_reset_in  ( src_reset   ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset   ) ,\n        .laguna_m_reset_in  ( src_reset  ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset2   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n      \n  end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] mid_payload;\n    wire mid_handshake;\n    wire mid_ready;\n    wire mid_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n    wire dummy_reset3;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( mid_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( mid_reset    ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset3   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset3   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out (  dummy_reset2  ) ,\n        .laguna_m_reset_in  ( mid_reset   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE2_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( mid_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2   ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset3   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset3    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n   \n  generate\n\n  (* keep=\"true\" *) reg s_reset_dd = 1'b0;\n  (* keep=\"true\" *) reg m_reset_dd = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n  \n  assign laguna_s_reset_out = laguna_s_reset_out_i;\n  assign laguna_m_reset_out = laguna_m_reset_out_i;\n  \n  always @(posedge ACLK) begin\n    laguna_s_reset_in_d <= laguna_s_reset_in;\n    laguna_m_reset_in_d <= laguna_m_reset_in;\n    s_reset_dd <= laguna_s_reset_in_d;\n    m_reset_dd <= laguna_m_reset_in_d;\n    laguna_s_reset_out_i <= C_PIPELINES==0 ? laguna_m_reset_in_d : m_reset_dd;\n    laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;\n  end\n  \n  wire ACLEAR;\n  assign ACLEAR = ~ARESETN;\n  \n  if (1) begin : common\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire laguna_s_handshake_q;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, laguna_m_ready_d}; \n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else if (p==C_PIPELINES+1) begin\n          laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n\n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = handshake_i[C_PIPELINES];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_m_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* keep=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_22_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_m_reset_out = laguna_m_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_m_reset_in_d <= laguna_m_reset_in;\n      aresetn_d <= C_CHANNEL==P_FORWARD ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? areset_dly[15]  : laguna_m_reset_in_d;\n      laguna_m_reset_out_i <= areset_d;  // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n  \n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* keep=\"true\" *)  reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      ready_d <= {ready_d, laguna_m_ready_d}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid_q;\n      assign payload_valid_d = (p==0) ? (S_VALID & s_ready_i) : handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==C_PIPELINES) begin\n          laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else if (p==0) begin\n          payload_data <= S_PAYLOAD_DATA;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n      \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_s_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* keep=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_s_reset_out = laguna_s_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_s_reset_in_d <= laguna_s_reset_in;\n      aresetn_d <= C_CHANNEL==P_RESPONSE ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? laguna_s_reset_in_d : areset_dly[15];\n      laguna_s_reset_out_i <= areset_d;  // For forward channels, reflect laguna_s_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n\n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    wire laguna_s_handshake_q;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      laguna_s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n        \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n        \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)  \n      )\n      srl_fifo_0\n      (\n       .aclk    (ACLK),    \n       .areset  (areset_d),  \n       .aclear  (ACLEAR),\n       .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n       .s_valid (push), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      ); \n  \n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  reg areset_d = 1'b0;\n  reg [3:0] areset_dly = 4'b0;\n  always @(posedge ACLK) begin\n    areset_dly <= {4{~ARESETN}} | (areset_dly<<1);\n    areset_d <= areset_dly[3];\n  end\n  \n  if (1) begin : common\n    reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID & s_ready_i;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* keep=\"true\" *)  reg payload_valid = 1'b0;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          payload_data <= S_PAYLOAD_DATA;\n          payload_valid <= S_VALID & s_ready_i & ~areset_d;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n          payload_valid <= handshake_i[((p>0)?(p-1):0)];\n        end\n      end\n    end\n    \n    if (C_PIPELINES==0) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),\n         .aclear  (1'b0),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire                        aclear,  // Async clear\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    wire [1:0] state;  // State vector register\n    reg  [1:0] next;           // Next state value\n    wire [1:0] next_qual;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    reg  m_valid_d;\n    wire m_valid_q;\n    \n    assign m_valid = m_valid_q;\n    assign next_qual = areset ? K_EMPTY : next;\n    assign m_mesg  = mesg_reg;\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_mvalid_inst (\n        .Q   (m_valid_q),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (m_valid_d)\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state0_inst (\n        .Q   (state[0]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[0])\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state1_inst (\n        .Q   (state[1]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[1])\n     );\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      m_valid_d = m_valid_q & ~areset;\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid & ~areset) begin\n            next = K_HAS1;\n            m_valid_d = 1'b0;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              m_valid_d = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n              m_valid_d = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          m_valid_d = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      (* keep_hierarchy = \"yes\" *) axi_register_slice_v2_1_22_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule  // axic_reg_srl_fifo\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   //   16 -> Auto-pipelining\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_RESERVE_MODE = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n  \n  if (C_RESERVE_MODE==1) begin : gen_reserve_si\n  \n    axi_register_slice_v2_1_22_test_slave #(\n      .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n      .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n      .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n      .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n      .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n      .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n      .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n      .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n      .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .s_axi_awaddr(s_axi_awaddr),\n      .s_axi_awprot(s_axi_awprot),\n      .s_axi_awvalid(s_axi_awvalid),\n      .s_axi_awready(s_axi_awready),\n      .s_axi_awsize(s_axi_awsize),\n      .s_axi_awburst(s_axi_awburst),\n      .s_axi_awcache(s_axi_awcache),\n      .s_axi_awlen(s_axi_awlen),\n      .s_axi_awlock(s_axi_awlock),\n      .s_axi_awqos(s_axi_awqos),\n      .s_axi_awregion(s_axi_awregion),\n      .s_axi_awid(s_axi_awid),\n      .s_axi_awuser(s_axi_awuser),\n      .s_axi_wdata(s_axi_wdata),\n      .s_axi_wstrb(s_axi_wstrb),\n      .s_axi_wvalid(s_axi_wvalid),\n      .s_axi_wready(s_axi_wready),\n      .s_axi_wlast(s_axi_wlast),\n      .s_axi_wid(s_axi_wid),\n      .s_axi_wuser(s_axi_wuser),\n      .s_axi_bresp(s_axi_bresp),\n      .s_axi_bvalid(s_axi_bvalid),\n      .s_axi_bready(s_axi_bready),\n      .s_axi_buser(s_axi_buser),\n      .s_axi_bid(s_axi_bid),\n      .s_axi_araddr(s_axi_araddr),\n      .s_axi_arprot(s_axi_arprot),\n      .s_axi_arvalid(s_axi_arvalid),\n      .s_axi_arready(s_axi_arready),\n      .s_axi_arsize(s_axi_arsize),\n      .s_axi_arburst(s_axi_arburst),\n      .s_axi_arcache(s_axi_arcache),\n      .s_axi_arlock(s_axi_arlock),\n      .s_axi_arlen(s_axi_arlen),\n      .s_axi_arqos(s_axi_arqos),\n      .s_axi_arregion(s_axi_arregion),\n      .s_axi_aruser(s_axi_aruser),\n      .s_axi_arid(s_axi_arid),\n      .s_axi_rdata(s_axi_rdata),\n      .s_axi_rresp(s_axi_rresp),\n      .s_axi_rvalid(s_axi_rvalid),\n      .s_axi_rready(s_axi_rready),\n      .s_axi_rlast(s_axi_rlast),\n      .s_axi_ruser(s_axi_ruser),\n      .s_axi_rid(s_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign m_axi_awid     = 0;\n     assign m_axi_awaddr   = 0;\n     assign m_axi_awlen    = 0;\n     assign m_axi_awsize   = 0;\n     assign m_axi_awburst  = 0;\n     assign m_axi_awlock   = 0;\n     assign m_axi_awcache  = 0;\n     assign m_axi_awprot   = 0;\n     assign m_axi_awregion = 0;\n     assign m_axi_awqos    = 0;\n     assign m_axi_awuser   = 0;\n     assign m_axi_awvalid  = 0;\n     assign m_axi_wid      = 0;\n     assign m_axi_wdata    = 0;\n     assign m_axi_wstrb    = 0;\n     assign m_axi_wlast    = 0;\n     assign m_axi_wuser    = 0;\n     assign m_axi_wvalid   = 0;\n     assign m_axi_bready   = 0;\n     assign m_axi_arid     = 0;\n     assign m_axi_araddr   = 0;\n     assign m_axi_arlen    = 0;\n     assign m_axi_arsize   = 0;\n     assign m_axi_arburst  = 0;\n     assign m_axi_arlock   = 0;\n     assign m_axi_arcache  = 0;\n     assign m_axi_arprot   = 0;\n     assign m_axi_arregion = 0;\n     assign m_axi_arqos    = 0;\n     assign m_axi_aruser   = 0;\n     assign m_axi_arvalid  = 0;\n     assign m_axi_rready   = 0;\n      \n  end else if (C_RESERVE_MODE==2) begin : gen_reserve_mi\n    \n    axi_register_slice_v2_1_22_test_master #(\n    .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n    .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .m_axi_awaddr(m_axi_awaddr),\n      .m_axi_awprot(m_axi_awprot),\n      .m_axi_awvalid(m_axi_awvalid),\n      .m_axi_awready(m_axi_awready),\n      .m_axi_awsize(m_axi_awsize),\n      .m_axi_awburst(m_axi_awburst),\n      .m_axi_awcache(m_axi_awcache),\n      .m_axi_awlen(m_axi_awlen),\n      .m_axi_awlock(m_axi_awlock),\n      .m_axi_awqos(m_axi_awqos),\n      .m_axi_awid(m_axi_awid),\n      .m_axi_awuser(m_axi_awuser),\n      .m_axi_wid(m_axi_wid),\n      .m_axi_wdata(m_axi_wdata),\n      .m_axi_wstrb(m_axi_wstrb),\n      .m_axi_wvalid(m_axi_wvalid),\n      .m_axi_wready(m_axi_wready),\n      .m_axi_wlast(m_axi_wlast),\n      .m_axi_wuser(m_axi_wuser),\n      .m_axi_bresp(m_axi_bresp),\n      .m_axi_bvalid(m_axi_bvalid),\n      .m_axi_bready(m_axi_bready),\n      .m_axi_buser(m_axi_buser),\n      .m_axi_bid(m_axi_bid),\n      .m_axi_araddr(m_axi_araddr),\n      .m_axi_arprot(m_axi_arprot),\n      .m_axi_arvalid(m_axi_arvalid),\n      .m_axi_arready(m_axi_arready),\n      .m_axi_arsize(m_axi_arsize),\n      .m_axi_arburst(m_axi_arburst),\n      .m_axi_arcache(m_axi_arcache),\n      .m_axi_arlen(m_axi_arlen),\n      .m_axi_arlock(m_axi_arlock),\n      .m_axi_arqos(m_axi_arqos),\n      .m_axi_arid(m_axi_arid),\n      .m_axi_aruser(m_axi_aruser),\n      .m_axi_rdata(m_axi_rdata),\n      .m_axi_rresp(m_axi_rresp),\n      .m_axi_rvalid(m_axi_rvalid),\n      .m_axi_rready(m_axi_rready),\n      .m_axi_rlast(m_axi_rlast),\n      .m_axi_ruser(m_axi_ruser),\n      .m_axi_rid(m_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign s_axi_awready = 0;\n     assign s_axi_wready  = 0;\n     assign s_axi_bid     = 0;\n     assign s_axi_bresp   = 0;\n     assign s_axi_buser   = 0;\n     assign s_axi_bvalid  = 0;\n     assign s_axi_arready = 0;\n     assign s_axi_rid     = 0;\n     assign s_axi_rdata   = 0;\n     assign s_axi_rresp   = 0;\n     assign s_axi_rlast   = 0;\n     assign s_axi_ruser   = 0;\n     assign s_axi_rvalid  = 0;\n\n  end else begin : gen_reg_slice  // Any normal reg-slice mode\n\n    axi_infrastructure_v1_1_0_axi2vector #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    axi2vector_0 ( \n      .s_axi_awid      ( s_axi_awid      ) ,\n      .s_axi_awaddr    ( s_axi_awaddr    ) ,\n      .s_axi_awlen     ( s_axi_awlen     ) ,\n      .s_axi_awsize    ( s_axi_awsize    ) ,\n      .s_axi_awburst   ( s_axi_awburst   ) ,\n      .s_axi_awlock    ( s_axi_awlock    ) ,\n      .s_axi_awcache   ( s_axi_awcache   ) ,\n      .s_axi_awprot    ( s_axi_awprot    ) ,\n      .s_axi_awqos     ( s_axi_awqos     ) ,\n      .s_axi_awuser    ( s_axi_awuser    ) ,\n      .s_axi_awregion  ( s_axi_awregion  ) ,\n      .s_axi_wid       ( s_axi_wid       ) ,\n      .s_axi_wdata     ( s_axi_wdata     ) ,\n      .s_axi_wstrb     ( s_axi_wstrb     ) ,\n      .s_axi_wlast     ( s_axi_wlast     ) ,\n      .s_axi_wuser     ( s_axi_wuser     ) ,\n      .s_axi_bid       ( s_axi_bid       ) ,\n      .s_axi_bresp     ( s_axi_bresp     ) ,\n      .s_axi_buser     ( s_axi_buser     ) ,\n      .s_axi_arid      ( s_axi_arid      ) ,\n      .s_axi_araddr    ( s_axi_araddr    ) ,\n      .s_axi_arlen     ( s_axi_arlen     ) ,\n      .s_axi_arsize    ( s_axi_arsize    ) ,\n      .s_axi_arburst   ( s_axi_arburst   ) ,\n      .s_axi_arlock    ( s_axi_arlock    ) ,\n      .s_axi_arcache   ( s_axi_arcache   ) ,\n      .s_axi_arprot    ( s_axi_arprot    ) ,\n      .s_axi_arqos     ( s_axi_arqos     ) ,\n      .s_axi_aruser    ( s_axi_aruser    ) ,\n      .s_axi_arregion  ( s_axi_arregion  ) ,\n      .s_axi_rid       ( s_axi_rid       ) ,\n      .s_axi_rdata     ( s_axi_rdata     ) ,\n      .s_axi_rresp     ( s_axi_rresp     ) ,\n      .s_axi_rlast     ( s_axi_rlast     ) ,\n      .s_axi_ruser     ( s_axi_ruser     ) ,\n      .s_awpayload ( s_awpayload ) ,\n      .s_wpayload  ( s_wpayload  ) ,\n      .s_bpayload  ( s_bpayload  ) ,\n      .s_arpayload ( s_arpayload ) ,\n      .s_rpayload  ( s_rpayload  ) \n    );\n    \n    axi_infrastructure_v1_1_0_vector2axi #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    vector2axi_0 ( \n      .m_awpayload    ( m_awpayload    ) ,\n      .m_wpayload     ( m_wpayload     ) ,\n      .m_bpayload     ( m_bpayload     ) ,\n      .m_arpayload    ( m_arpayload    ) ,\n      .m_rpayload     ( m_rpayload     ) ,\n      .m_axi_awid     ( m_axi_awid     ) ,\n      .m_axi_awaddr   ( m_axi_awaddr   ) ,\n      .m_axi_awlen    ( m_axi_awlen    ) ,\n      .m_axi_awsize   ( m_axi_awsize   ) ,\n      .m_axi_awburst  ( m_axi_awburst  ) ,\n      .m_axi_awlock   ( m_axi_awlock   ) ,\n      .m_axi_awcache  ( m_axi_awcache  ) ,\n      .m_axi_awprot   ( m_axi_awprot   ) ,\n      .m_axi_awqos    ( m_axi_awqos    ) ,\n      .m_axi_awuser   ( m_axi_awuser   ) ,\n      .m_axi_awregion ( m_axi_awregion ) ,\n      .m_axi_wid      ( m_axi_wid      ) ,\n      .m_axi_wdata    ( m_axi_wdata    ) ,\n      .m_axi_wstrb    ( m_axi_wstrb    ) ,\n      .m_axi_wlast    ( m_axi_wlast    ) ,\n      .m_axi_wuser    ( m_axi_wuser    ) ,\n      .m_axi_bid      ( m_axi_bid      ) ,\n      .m_axi_bresp    ( m_axi_bresp    ) ,\n      .m_axi_buser    ( m_axi_buser    ) ,\n      .m_axi_arid     ( m_axi_arid     ) ,\n      .m_axi_araddr   ( m_axi_araddr   ) ,\n      .m_axi_arlen    ( m_axi_arlen    ) ,\n      .m_axi_arsize   ( m_axi_arsize   ) ,\n      .m_axi_arburst  ( m_axi_arburst  ) ,\n      .m_axi_arlock   ( m_axi_arlock   ) ,\n      .m_axi_arcache  ( m_axi_arcache  ) ,\n      .m_axi_arprot   ( m_axi_arprot   ) ,\n      .m_axi_arqos    ( m_axi_arqos    ) ,\n      .m_axi_aruser   ( m_axi_aruser   ) ,\n      .m_axi_arregion ( m_axi_arregion ) ,\n      .m_axi_rid      ( m_axi_rid      ) ,\n      .m_axi_rdata    ( m_axi_rdata    ) ,\n      .m_axi_rresp    ( m_axi_rresp    ) ,\n      .m_axi_rlast    ( m_axi_rlast    ) ,\n      .m_axi_ruser    ( m_axi_ruser    ) \n    );\n    \n  end  // Reserve SI/MI branch\n\n  if ((C_REG_CONFIG_AW <= 9) && (C_RESERVE_MODE==0)) begin : aw\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 15) && (C_RESERVE_MODE==0)) begin : aw15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 16) && (C_RESERVE_MODE==0)) begin : aw16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) \n    )\n    aw_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if ((C_REG_CONFIG_W <= 9) && (C_RESERVE_MODE==0)) begin : w\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 15) && (C_RESERVE_MODE==0)) begin : w15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 16) && (C_RESERVE_MODE==0)) begin : w16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) \n    )\n    w_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if ((C_REG_CONFIG_B <= 9) && (C_RESERVE_MODE==0)) begin : b\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if ((C_REG_CONFIG_B == 15) && (C_RESERVE_MODE==0)) begin : b15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if ((C_REG_CONFIG_B == 16) && (C_RESERVE_MODE==0)) begin : b16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) \n    )\n    b_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if ((C_REG_CONFIG_AR <= 9) && (C_RESERVE_MODE==0)) begin : ar\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 15) && (C_RESERVE_MODE==0)) begin : ar15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 16) && (C_RESERVE_MODE==0)) begin : ar16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) \n    )\n    ar_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if ((C_REG_CONFIG_R <= 9) && (C_RESERVE_MODE==0)) begin : r\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 15) && (C_RESERVE_MODE==0)) begin : r15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 16) && (C_RESERVE_MODE==0)) begin : r16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) \n    )\n    r_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 4844}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/*\n *******************************************************************************\n *\n * FIFO Generator - Verilog Behavioral Model\n *\n *******************************************************************************\n *\n * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.\n *\n * This file contains confidential and proprietary information\n * of Xilinx, Inc. and is protected under U.S. and\n * international copyright and other intellectual property\n * laws.\n *\n * DISCLAIMER\n * This disclaimer is not a license and does not grant any\n * rights to the materials distributed herewith. Except as\n * otherwise provided in a valid license issued to you by\n * Xilinx, and to the maximum extent permitted by applicable\n * law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n * (2) Xilinx shall not be liable (whether in contract or tort,\n * including negligence, or under any other theory of\n * liability) for any loss or damage of any kind or nature\n * related to, arising under or in connection with these\n * materials, including for any direct, or any indirect,\n * special, incidental, or consequential loss or damage\n * (including loss of data, profits, goodwill, or any type of\n * loss or damage suffered as a result of any action brought\n * by a third party) even if such damage or loss was\n * reasonably foreseeable or Xilinx had been advised of the\n * possibility of the same.\n *\n * CRITICAL APPLICATIONS\n * Xilinx products are not designed or intended to be fail-\n * safe, or for use in any application requiring fail-safe\n * performance, such as life-support or safety devices or\n * systems, Class III medical devices, nuclear facilities,\n * applications related to the deployment of airbags, or any\n * other applications that could lead to death, personal\n * injury, or severe property or environmental damage\n * (individually and collectively, \"Critical\n * Applications\"). Customer assumes the sole risk and\n * liability of any use of Xilinx products in Critical\n * Applications, subject only to applicable laws and\n * regulations governing limitations on product liability.\n *\n * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n * PART OF THIS FILE AT ALL TIMES.\n *\n *******************************************************************************\n *******************************************************************************\n *\n * Filename: fifo_generator_vlog_beh.v\n *\n * Author     : Xilinx\n *\n *******************************************************************************\n * Structure:\n * \n * fifo_generator_vlog_beh.v\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_as\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_ss\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_preload0\n * \n *******************************************************************************\n * Description:\n *\n * The Verilog behavioral model for the FIFO Generator.\n *\n *   The behavioral model has three parts:\n *      - The behavioral model for independent clocks FIFOs (_as)\n *      - The behavioral model for common clock FIFOs (_ss)\n *      - The \"preload logic\" block which implements First-word Fall-through\n * \n *******************************************************************************\n * Description:\n *  The verilog behavioral model for the FIFO generator core.\n *\n *******************************************************************************\n */\n\n`timescale 1ps/1ps\n`ifndef TCQ\n `define TCQ 100\n`endif\n\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_vlog_beh\n  #(\n    //-----------------------------------------------------------------------\n    // Generic Declarations\n    //-----------------------------------------------------------------------\n    parameter C_COMMON_CLOCK                 = 0,\n    parameter C_COUNT_TYPE                   = 0,\n    parameter C_DATA_COUNT_WIDTH             = 2,\n    parameter C_DEFAULT_VALUE                = \"\",\n    parameter C_DIN_WIDTH                    = 8,\n    parameter C_DOUT_RST_VAL                 = \"\",\n    parameter C_DOUT_WIDTH                   = 8,\n    parameter C_ENABLE_RLOCS                 = 0,\n    parameter C_FAMILY                       = \"\",\n    parameter C_FULL_FLAGS_RST_VAL           = 1,\n    parameter C_HAS_ALMOST_EMPTY             = 0,\n    parameter C_HAS_ALMOST_FULL              = 0,\n    parameter C_HAS_BACKUP                   = 0,\n    parameter C_HAS_DATA_COUNT               = 0,\n    parameter C_HAS_INT_CLK                  = 0,\n    parameter C_HAS_MEMINIT_FILE             = 0,\n    parameter C_HAS_OVERFLOW                 = 0,\n    parameter C_HAS_RD_DATA_COUNT            = 0,\n    parameter C_HAS_RD_RST                   = 0,\n    parameter C_HAS_RST                      = 1,\n    parameter C_HAS_SRST                     = 0,\n    parameter C_HAS_UNDERFLOW                = 0,\n    parameter C_HAS_VALID                    = 0,\n    parameter C_HAS_WR_ACK                   = 0,\n    parameter C_HAS_WR_DATA_COUNT            = 0,\n    parameter C_HAS_WR_RST                   = 0,\n    parameter C_IMPLEMENTATION_TYPE          = 0,\n    parameter C_INIT_WR_PNTR_VAL             = 0,\n    parameter C_MEMORY_TYPE                  = 1,\n    parameter C_MIF_FILE_NAME                = \"\",\n    parameter C_OPTIMIZATION_MODE            = 0,\n    parameter C_OVERFLOW_LOW                 = 0,\n    parameter C_EN_SAFETY_CKT                = 0,\n    parameter C_PRELOAD_LATENCY              = 1,\n    parameter C_PRELOAD_REGS                 = 0,\n    parameter C_PRIM_FIFO_TYPE               = \"4kx4\",\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter C_PROG_EMPTY_TYPE              = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter C_PROG_FULL_TYPE               = 0,\n    parameter C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter C_RD_DEPTH                     = 256,\n    parameter C_RD_FREQ                      = 1,\n    parameter C_RD_PNTR_WIDTH                = 8,\n    parameter C_UNDERFLOW_LOW                = 0,\n    parameter C_USE_DOUT_RST                 = 0,\n    parameter C_USE_ECC                      = 0,\n    parameter C_USE_EMBEDDED_REG             = 0,\n    parameter C_USE_PIPELINE_REG             = 0,\n    parameter C_POWER_SAVING_MODE            = 0,\n    parameter C_USE_FIFO16_FLAGS             = 0,\n    parameter C_USE_FWFT_DATA_COUNT          = 0,\n    parameter C_VALID_LOW                    = 0,\n    parameter C_WR_ACK_LOW                   = 0,\n    parameter C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter C_WR_DEPTH                     = 256,\n    parameter C_WR_FREQ                      = 1,\n    parameter C_WR_PNTR_WIDTH                = 8,\n    parameter C_WR_RESPONSE_LATENCY          = 1,\n    parameter C_MSGON_VAL                    = 1,\n    parameter C_ENABLE_RST_SYNC              = 1,\n    parameter C_ERROR_INJECTION_TYPE         = 0,\n    parameter C_SYNCHRONIZER_STAGE           = 2,\n\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE               = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3\n    parameter C_AXI_TYPE                     = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3\n    parameter C_HAS_AXI_WR_CHANNEL           = 0,\n    parameter C_HAS_AXI_RD_CHANNEL           = 0,\n    parameter C_HAS_SLAVE_CE                 = 0,\n    parameter C_HAS_MASTER_CE                = 0,\n    parameter C_ADD_NGC_CONSTRAINT           = 0,\n    parameter C_USE_COMMON_UNDERFLOW         = 0,\n    parameter C_USE_COMMON_OVERFLOW          = 0,\n    parameter C_USE_DEFAULT_SETTINGS         = 0,\n\n    // AXI Full/Lite\n    parameter C_AXI_ID_WIDTH                 = 0,\n    parameter C_AXI_ADDR_WIDTH               = 0,\n    parameter C_AXI_DATA_WIDTH               = 0,\n    parameter C_AXI_LEN_WIDTH                = 8,\n    parameter C_AXI_LOCK_WIDTH               = 2,\n    parameter C_HAS_AXI_ID                   = 0,\n    parameter C_HAS_AXI_AWUSER               = 0,\n    parameter C_HAS_AXI_WUSER                = 0,\n    parameter C_HAS_AXI_BUSER                = 0,\n    parameter C_HAS_AXI_ARUSER               = 0,\n    parameter C_HAS_AXI_RUSER                = 0,\n    parameter C_AXI_ARUSER_WIDTH             = 0,\n    parameter C_AXI_AWUSER_WIDTH             = 0,\n    parameter C_AXI_WUSER_WIDTH              = 0,\n    parameter C_AXI_BUSER_WIDTH              = 0,\n    parameter C_AXI_RUSER_WIDTH              = 0,\n\n    // AXI Streaming\n    parameter C_HAS_AXIS_TDATA               = 0,\n    parameter C_HAS_AXIS_TID                 = 0,\n    parameter C_HAS_AXIS_TDEST               = 0,\n    parameter C_HAS_AXIS_TUSER               = 0,\n    parameter C_HAS_AXIS_TREADY              = 0,\n    parameter C_HAS_AXIS_TLAST               = 0,\n    parameter C_HAS_AXIS_TSTRB               = 0,\n    parameter C_HAS_AXIS_TKEEP               = 0,\n    parameter C_AXIS_TDATA_WIDTH             = 1,\n    parameter C_AXIS_TID_WIDTH               = 1,\n    parameter C_AXIS_TDEST_WIDTH             = 1,\n    parameter C_AXIS_TUSER_WIDTH             = 1,\n    parameter C_AXIS_TSTRB_WIDTH             = 1,\n    parameter C_AXIS_TKEEP_WIDTH             = 1,\n\n    // AXI Channel Type\n    // WACH --> Write Address Channel\n    // WDCH --> Write Data Channel\n    // WRCH --> Write Response Channel\n    // RACH --> Read Address Channel\n    // RDCH --> Read Data Channel\n    // AXIS --> AXI Streaming\n    parameter C_WACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic\n    parameter C_WDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_WRCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_AXIS_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n\n    // AXI Implementation Type\n    // 1 = Common Clock Block RAM FIFO\n    // 2 = Common Clock Distributed RAM FIFO\n    // 11 = Independent Clock Block RAM FIFO\n    // 12 = Independent Clock Distributed RAM FIFO\n    parameter C_IMPLEMENTATION_TYPE_WACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WRCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_AXIS     = 0,\n\n    // AXI FIFO Type\n    // 0 = Data FIFO\n    // 1 = Packet FIFO\n    // 2 = Low Latency Sync FIFO\n    // 3 = Low Latency Async FIFO\n    parameter C_APPLICATION_TYPE_WACH        = 0,\n    parameter C_APPLICATION_TYPE_WDCH        = 0,\n    parameter C_APPLICATION_TYPE_WRCH        = 0,\n    parameter C_APPLICATION_TYPE_RACH        = 0,\n    parameter C_APPLICATION_TYPE_RDCH        = 0,\n    parameter C_APPLICATION_TYPE_AXIS        = 0,\n\n    // AXI Built-in FIFO Primitive Type\n    // 512x36, 1kx18, 2kx9, 4kx4, etc\n    parameter C_PRIM_FIFO_TYPE_WACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WRCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_AXIS          = \"512x36\",\n\n    // Enable ECC\n    // 0 = ECC disabled\n    // 1 = ECC enabled\n    parameter C_USE_ECC_WACH                 = 0,\n    parameter C_USE_ECC_WDCH                 = 0,\n    parameter C_USE_ECC_WRCH                 = 0,\n    parameter C_USE_ECC_RACH                 = 0,\n    parameter C_USE_ECC_RDCH                 = 0,\n    parameter C_USE_ECC_AXIS                 = 0,\n\n    // ECC Error Injection Type\n    // 0 = No Error Injection\n    // 1 = Single Bit Error Injection\n    // 2 = Double Bit Error Injection\n    // 3 = Single Bit and Double Bit Error Injection\n    parameter C_ERROR_INJECTION_TYPE_WACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WRCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_AXIS    = 0,\n\n    // Input Data Width\n    // Accumulation of all AXI input signal's width\n    parameter C_DIN_WIDTH_WACH               = 1,\n    parameter C_DIN_WIDTH_WDCH               = 1,\n    parameter C_DIN_WIDTH_WRCH               = 1,\n    parameter C_DIN_WIDTH_RACH               = 1,\n    parameter C_DIN_WIDTH_RDCH               = 1,\n    parameter C_DIN_WIDTH_AXIS               = 1,\n\n    parameter C_WR_DEPTH_WACH                = 16,\n    parameter C_WR_DEPTH_WDCH                = 16,\n    parameter C_WR_DEPTH_WRCH                = 16,\n    parameter C_WR_DEPTH_RACH                = 16,\n    parameter C_WR_DEPTH_RDCH                = 16,\n    parameter C_WR_DEPTH_AXIS                = 16,\n\n    parameter C_WR_PNTR_WIDTH_WACH           = 4,\n    parameter C_WR_PNTR_WIDTH_WDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_WRCH           = 4,\n    parameter C_WR_PNTR_WIDTH_RACH           = 4,\n    parameter C_WR_PNTR_WIDTH_RDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_AXIS           = 4,\n\n    parameter C_HAS_DATA_COUNTS_WACH         = 0,\n    parameter C_HAS_DATA_COUNTS_WDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_WRCH         = 0,\n    parameter C_HAS_DATA_COUNTS_RACH         = 0,\n    parameter C_HAS_DATA_COUNTS_RDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_AXIS         = 0,\n\n    parameter C_HAS_PROG_FLAGS_WACH          = 0,\n    parameter C_HAS_PROG_FLAGS_WDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_WRCH          = 0,\n    parameter C_HAS_PROG_FLAGS_RACH          = 0,\n    parameter C_HAS_PROG_FLAGS_RDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_AXIS          = 0,\n\n    parameter C_PROG_FULL_TYPE_WACH          = 0,\n    parameter C_PROG_FULL_TYPE_WDCH          = 0,\n    parameter C_PROG_FULL_TYPE_WRCH          = 0,\n    parameter C_PROG_FULL_TYPE_RACH          = 0,\n    parameter C_PROG_FULL_TYPE_RDCH          = 0,\n    parameter C_PROG_FULL_TYPE_AXIS          = 0,\n\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS      = 0,\n\n    parameter C_PROG_EMPTY_TYPE_WACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WRCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_AXIS         = 0,\n\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS     = 0,\n\n    parameter C_REG_SLICE_MODE_WACH          = 0,\n    parameter C_REG_SLICE_MODE_WDCH          = 0,\n    parameter C_REG_SLICE_MODE_WRCH          = 0,\n    parameter C_REG_SLICE_MODE_RACH          = 0,\n    parameter C_REG_SLICE_MODE_RDCH          = 0,\n    parameter C_REG_SLICE_MODE_AXIS          = 0\n\n    )\n\n   (\n    //------------------------------------------------------------------------------\n    // Input and Output Declarations\n    //------------------------------------------------------------------------------\n\n    // Conventional FIFO Interface Signals\n    input                               backup,\n    input                               backup_marker,\n    input                               clk,\n    input                               rst,\n    input                               srst,\n    input                               wr_clk,\n    input                               wr_rst,\n    input                               rd_clk,\n    input                               rd_rst,\n    input [C_DIN_WIDTH-1:0]             din,\n    input                               wr_en,\n    input                               rd_en,\n    // Optional inputs\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_assert,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_negate,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_assert,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_negate,\n    input                               int_clk,\n    input                               injectdbiterr,\n    input                               injectsbiterr,\n    input                               sleep,\n\n    output [C_DOUT_WIDTH-1:0]           dout,\n    output                              full,\n    output                              almost_full,\n    output                              wr_ack,\n    output                              overflow,\n    output                              empty,\n    output                              almost_empty,\n    output                              valid,\n    output                              underflow,\n    output [C_DATA_COUNT_WIDTH-1:0]     data_count,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]  rd_data_count,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count,\n    output                              prog_full,\n    output                              prog_empty,\n    output                              sbiterr,\n    output                              dbiterr,\n    output                              wr_rst_busy,\n    output                              rd_rst_busy,\n\n\n    // AXI Global Signal\n    input                               m_aclk,\n    input                               s_aclk,\n    input                               s_aresetn,\n    input                               s_aclk_en,\n    input                               m_aclk_en,\n    \n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_awid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_awaddr,\n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_awlen,\n    input [3-1:0]                       s_axi_awsize,\n    input [2-1:0]                       s_axi_awburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_awlock,\n    input [4-1:0]                       s_axi_awcache,\n    input [3-1:0]                       s_axi_awprot,\n    input [4-1:0]                       s_axi_awqos,\n    input [4-1:0]                       s_axi_awregion,\n    input [C_AXI_AWUSER_WIDTH-1:0]      s_axi_awuser,\n    input                               s_axi_awvalid,\n    output                              s_axi_awready,\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_wid,\n    input [C_AXI_DATA_WIDTH-1:0]        s_axi_wdata,\n    input [C_AXI_DATA_WIDTH/8-1:0]      s_axi_wstrb,\n    input                               s_axi_wlast,\n    input [C_AXI_WUSER_WIDTH-1:0]       s_axi_wuser,\n    input                               s_axi_wvalid,\n    output                              s_axi_wready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_bid,\n    output [2-1:0]                      s_axi_bresp,\n    output [C_AXI_BUSER_WIDTH-1:0]      s_axi_buser,\n    output                              s_axi_bvalid,\n    input                               s_axi_bready,\n    \n    // AXI Full/Lite Master Write Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_awid,\n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_awlen,\n    output [3-1:0]                      m_axi_awsize,\n    output [2-1:0]                      m_axi_awburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_awlock,\n    output [4-1:0]                      m_axi_awcache,\n    output [3-1:0]                      m_axi_awprot,\n    output [4-1:0]                      m_axi_awqos,\n    output [4-1:0]                      m_axi_awregion,\n    output [C_AXI_AWUSER_WIDTH-1:0]     m_axi_awuser,\n    output                              m_axi_awvalid,\n    input                               m_axi_awready,\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_wid,\n    output [C_AXI_DATA_WIDTH-1:0]       m_axi_wdata,\n    output [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb,\n    output                              m_axi_wlast,\n    output [C_AXI_WUSER_WIDTH-1:0]      m_axi_wuser,\n    output                              m_axi_wvalid,\n    input                               m_axi_wready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_bid,\n    input [2-1:0]                       m_axi_bresp,\n    input [C_AXI_BUSER_WIDTH-1:0]       m_axi_buser,\n    input                               m_axi_bvalid,\n    output                              m_axi_bready,\n    \n    \n    // AXI Full/Lite Slave Read Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_arid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_araddr, \n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_arlen,\n    input [3-1:0]                       s_axi_arsize,\n    input [2-1:0]                       s_axi_arburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_arlock,\n    input [4-1:0]                       s_axi_arcache,\n    input [3-1:0]                       s_axi_arprot,\n    input [4-1:0]                       s_axi_arqos,\n    input [4-1:0]                       s_axi_arregion,\n    input [C_AXI_ARUSER_WIDTH-1:0]      s_axi_aruser,\n    input                               s_axi_arvalid,\n    output                              s_axi_arready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_rid,       \n    output [C_AXI_DATA_WIDTH-1:0]       s_axi_rdata, \n    output [2-1:0]                      s_axi_rresp,\n    output                              s_axi_rlast,\n    output [C_AXI_RUSER_WIDTH-1:0]      s_axi_ruser,\n    output                              s_axi_rvalid,\n    input                               s_axi_rready,\n    \n    \n    \n    // AXI Full/Lite Master Read Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_arid,        \n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,  \n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_arlen,\n    output [3-1:0]                      m_axi_arsize,\n    output [2-1:0]                      m_axi_arburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_arlock,\n    output [4-1:0]                      m_axi_arcache,\n    output [3-1:0]                      m_axi_arprot,\n    output [4-1:0]                      m_axi_arqos,\n    output [4-1:0]                      m_axi_arregion,\n    output [C_AXI_ARUSER_WIDTH-1:0]     m_axi_aruser,\n    output                              m_axi_arvalid,\n    input                               m_axi_arready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_rid,        \n    input [C_AXI_DATA_WIDTH-1:0]        m_axi_rdata,  \n    input [2-1:0]                       m_axi_rresp,\n    input                               m_axi_rlast,\n    input [C_AXI_RUSER_WIDTH-1:0]       m_axi_ruser,\n    input                               m_axi_rvalid,\n    output                              m_axi_rready,\n    \n    \n    // AXI Streaming Slave Signals (Write side)\n    input                               s_axis_tvalid,\n    output                              s_axis_tready,\n    input [C_AXIS_TDATA_WIDTH-1:0]      s_axis_tdata,\n    input [C_AXIS_TSTRB_WIDTH-1:0]      s_axis_tstrb,\n    input [C_AXIS_TKEEP_WIDTH-1:0]      s_axis_tkeep,\n    input                               s_axis_tlast,\n    input [C_AXIS_TID_WIDTH-1:0]        s_axis_tid,\n    input [C_AXIS_TDEST_WIDTH-1:0]      s_axis_tdest,\n    input [C_AXIS_TUSER_WIDTH-1:0]      s_axis_tuser,\n    \n    // AXI Streaming Master Signals (Read side)\n    output                              m_axis_tvalid,\n    input                               m_axis_tready,\n    output [C_AXIS_TDATA_WIDTH-1:0]     m_axis_tdata,\n    output [C_AXIS_TSTRB_WIDTH-1:0]     m_axis_tstrb,\n    output [C_AXIS_TKEEP_WIDTH-1:0]     m_axis_tkeep,\n    output                              m_axis_tlast,\n    output [C_AXIS_TID_WIDTH-1:0]       m_axis_tid,\n    output [C_AXIS_TDEST_WIDTH-1:0]     m_axis_tdest,\n    output [C_AXIS_TUSER_WIDTH-1:0]     m_axis_tuser,\n    \n           \n    \n    \n    // AXI Full/Lite Write Address Channel signals\n    input                               axi_aw_injectsbiterr,\n    input                               axi_aw_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_rd_data_count,\n    output                              axi_aw_sbiterr,\n    output                              axi_aw_dbiterr,\n    output                              axi_aw_overflow,\n    output                              axi_aw_underflow,\n    output                              axi_aw_prog_full,\n    output                              axi_aw_prog_empty,\n    \n    \n    // AXI Full/Lite Write Data Channel signals\n    input                               axi_w_injectsbiterr,\n    input                               axi_w_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_rd_data_count,\n    output                              axi_w_sbiterr,\n    output                              axi_w_dbiterr,\n    output                              axi_w_overflow,\n    output                              axi_w_underflow,\n    output                              axi_w_prog_full,\n    output                              axi_w_prog_empty,\n    \n    \n    // AXI Full/Lite Write Response Channel signals\n    input                               axi_b_injectsbiterr,\n    input                               axi_b_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_rd_data_count,\n    output                              axi_b_sbiterr,\n    output                              axi_b_dbiterr,\n    output                              axi_b_overflow,\n    output                              axi_b_underflow,\n    output                              axi_b_prog_full,\n    output                              axi_b_prog_empty,\n    \n    \n    \n    // AXI Full/Lite Read Address Channel signals\n    input                               axi_ar_injectsbiterr,\n    input                               axi_ar_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_rd_data_count,\n    output                              axi_ar_sbiterr,\n    output                              axi_ar_dbiterr,\n    output                              axi_ar_overflow,\n    output                              axi_ar_underflow,\n    output                              axi_ar_prog_full,\n    output                              axi_ar_prog_empty,\n\n    \n    // AXI Full/Lite Read Data Channel Signals\n    input                               axi_r_injectsbiterr,\n    input                               axi_r_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_rd_data_count,\n    output                              axi_r_sbiterr,\n    output                              axi_r_dbiterr,\n    output                              axi_r_overflow,\n    output                              axi_r_underflow,\n    output                              axi_r_prog_full,\n    output                              axi_r_prog_empty,\n\n    \n    // AXI Streaming FIFO Related Signals\n    input                               axis_injectsbiterr,\n    input                               axis_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_wr_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_rd_data_count,\n    output                              axis_sbiterr,\n    output                              axis_dbiterr,\n    output                              axis_overflow,\n    output                              axis_underflow,\n    output                              axis_prog_full,\n    output                              axis_prog_empty\n\n    );\n\n    wire                              BACKUP;\n    wire                              BACKUP_MARKER;\n    wire                              CLK;\n    wire                              RST;\n    wire                              SRST;\n    wire                              WR_CLK;\n    wire                              WR_RST;\n    wire                              RD_CLK;\n    wire                              RD_RST;\n    wire [C_DIN_WIDTH-1:0]            DIN;\n    wire                              WR_EN;\n    wire                              RD_EN;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_ASSERT;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_NEGATE;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_ASSERT;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_NEGATE;\n    wire                              INT_CLK;\n    wire                              INJECTDBITERR;\n    wire                              INJECTSBITERR;\n    wire                              SLEEP;\n    wire [C_DOUT_WIDTH-1:0]           DOUT;\n    wire                              FULL;\n    wire                              ALMOST_FULL;\n    wire                              WR_ACK;\n    wire                              OVERFLOW;\n    wire                              EMPTY;\n    wire                              ALMOST_EMPTY;\n    wire                              VALID;\n    wire                              UNDERFLOW;\n    wire [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT;\n    wire [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT;\n    wire                              PROG_FULL;\n    wire                              PROG_EMPTY;\n    wire                              SBITERR;\n    wire                              DBITERR;\n    wire                              WR_RST_BUSY;\n    wire                              RD_RST_BUSY;\n    wire                              M_ACLK;\n    wire                              S_ACLK;\n    wire                              S_ARESETN;\n    wire                              S_ACLK_EN;\n    wire                              M_ACLK_EN;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_AWLEN;\n    wire [3-1:0]                      S_AXI_AWSIZE;\n    wire [2-1:0]                      S_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_AWLOCK;\n    wire [4-1:0]                      S_AXI_AWCACHE;\n    wire [3-1:0]                      S_AXI_AWPROT;\n    wire [4-1:0]                      S_AXI_AWQOS;\n    wire [4-1:0]                      S_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     S_AXI_AWUSER;\n    wire                              S_AXI_AWVALID;\n    wire                              S_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     S_AXI_WSTRB;\n    wire                              S_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      S_AXI_WUSER;\n    wire                              S_AXI_WVALID;\n    wire                              S_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_BID;\n    wire [2-1:0]                      S_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      S_AXI_BUSER;\n    wire                              S_AXI_BVALID;\n    wire                              S_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_AWLEN;\n    wire [3-1:0]                      M_AXI_AWSIZE;\n    wire [2-1:0]                      M_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_AWLOCK;\n    wire [4-1:0]                      M_AXI_AWCACHE;\n    wire [3-1:0]                      M_AXI_AWPROT;\n    wire [4-1:0]                      M_AXI_AWQOS;\n    wire [4-1:0]                      M_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     M_AXI_AWUSER;\n    wire                              M_AXI_AWVALID;\n    wire                              M_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     M_AXI_WSTRB;\n    wire                              M_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      M_AXI_WUSER;\n    wire                              M_AXI_WVALID;\n    wire                              M_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_BID;\n    wire [2-1:0]                      M_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      M_AXI_BUSER;\n    wire                              M_AXI_BVALID;\n    wire                              M_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_ARID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_ARADDR; \n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_ARLEN;\n    wire [3-1:0]                      S_AXI_ARSIZE;\n    wire [2-1:0]                      S_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_ARLOCK;\n    wire [4-1:0]                      S_AXI_ARCACHE;\n    wire [3-1:0]                      S_AXI_ARPROT;\n    wire [4-1:0]                      S_AXI_ARQOS;\n    wire [4-1:0]                      S_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     S_AXI_ARUSER;\n    wire                              S_AXI_ARVALID;\n    wire                              S_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_RID;       \n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_RDATA; \n    wire [2-1:0]                      S_AXI_RRESP;\n    wire                              S_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      S_AXI_RUSER;\n    wire                              S_AXI_RVALID;\n    wire                              S_AXI_RREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_ARID;        \n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_ARADDR;  \n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_ARLEN;\n    wire [3-1:0]                      M_AXI_ARSIZE;\n    wire [2-1:0]                      M_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_ARLOCK;\n    wire [4-1:0]                      M_AXI_ARCACHE;\n    wire [3-1:0]                      M_AXI_ARPROT;\n    wire [4-1:0]                      M_AXI_ARQOS;\n    wire [4-1:0]                      M_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     M_AXI_ARUSER;\n    wire                              M_AXI_ARVALID;\n    wire                              M_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_RID;        \n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_RDATA;  \n    wire [2-1:0]                      M_AXI_RRESP;\n    wire                              M_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      M_AXI_RUSER;\n    wire                              M_AXI_RVALID;\n    wire                              M_AXI_RREADY;\n    wire                              S_AXIS_TVALID;\n    wire                              S_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     S_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     S_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     S_AXIS_TKEEP;\n    wire                              S_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       S_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     S_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     S_AXIS_TUSER;\n    wire                              M_AXIS_TVALID;\n    wire                              M_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     M_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     M_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     M_AXIS_TKEEP;\n    wire                              M_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       M_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     M_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     M_AXIS_TUSER;\n    wire                              AXI_AW_INJECTSBITERR;\n    wire                              AXI_AW_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_RD_DATA_COUNT;\n    wire                              AXI_AW_SBITERR;\n    wire                              AXI_AW_DBITERR;\n    wire                              AXI_AW_OVERFLOW;\n    wire                              AXI_AW_UNDERFLOW;\n    wire                              AXI_AW_PROG_FULL;\n    wire                              AXI_AW_PROG_EMPTY;\n    wire                              AXI_W_INJECTSBITERR;\n    wire                              AXI_W_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_RD_DATA_COUNT;\n    wire                              AXI_W_SBITERR;\n    wire                              AXI_W_DBITERR;\n    wire                              AXI_W_OVERFLOW;\n    wire                              AXI_W_UNDERFLOW;\n    wire                              AXI_W_PROG_FULL;\n    wire                              AXI_W_PROG_EMPTY;\n    wire                              AXI_B_INJECTSBITERR;\n    wire                              AXI_B_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_RD_DATA_COUNT;\n    wire                              AXI_B_SBITERR;\n    wire                              AXI_B_DBITERR;\n    wire                              AXI_B_OVERFLOW;\n    wire                              AXI_B_UNDERFLOW;\n    wire                              AXI_B_PROG_FULL;\n    wire                              AXI_B_PROG_EMPTY;\n    wire                              AXI_AR_INJECTSBITERR;\n    wire                              AXI_AR_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_RD_DATA_COUNT;\n    wire                              AXI_AR_SBITERR;\n    wire                              AXI_AR_DBITERR;\n    wire                              AXI_AR_OVERFLOW;\n    wire                              AXI_AR_UNDERFLOW;\n    wire                              AXI_AR_PROG_FULL;\n    wire                              AXI_AR_PROG_EMPTY;\n    wire                              AXI_R_INJECTSBITERR;\n    wire                              AXI_R_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_RD_DATA_COUNT;\n    wire                              AXI_R_SBITERR;\n    wire                              AXI_R_DBITERR;\n    wire                              AXI_R_OVERFLOW;\n    wire                              AXI_R_UNDERFLOW;\n    wire                              AXI_R_PROG_FULL;\n    wire                              AXI_R_PROG_EMPTY;\n    wire                              AXIS_INJECTSBITERR;\n    wire                              AXIS_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_RD_DATA_COUNT;\n    wire                              AXIS_SBITERR;\n    wire                              AXIS_DBITERR;\n    wire                              AXIS_OVERFLOW;\n    wire                              AXIS_UNDERFLOW;\n    wire                              AXIS_PROG_FULL;\n    wire                              AXIS_PROG_EMPTY;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count_in;\n    wire                              wr_rst_int;\n    wire                              rd_rst_int;\n    wire                              wr_rst_busy_o;\n    wire                              wr_rst_busy_ntve;\n    wire                              wr_rst_busy_axis;\n    wire                              wr_rst_busy_wach;\n    wire                              wr_rst_busy_wdch;\n    wire                              wr_rst_busy_wrch;\n    wire                              wr_rst_busy_rach;\n    wire                              wr_rst_busy_rdch;\n\n\n\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n\n\n\n    // Conventional FIFO Interface Signals\n    assign BACKUP                 = backup;\n    assign BACKUP_MARKER          = backup_marker;\n    assign CLK                    = clk;\n    assign RST                    = rst;\n    assign SRST                   = srst;\n    assign WR_CLK                 = wr_clk;\n    assign WR_RST                 = wr_rst;\n    assign RD_CLK                 = rd_clk;\n    assign RD_RST                 = rd_rst;\n    assign WR_EN                  = wr_en;\n    assign RD_EN                  = rd_en;\n    assign INT_CLK                = int_clk;\n    assign INJECTDBITERR          = injectdbiterr;\n    assign INJECTSBITERR          = injectsbiterr;\n    assign SLEEP                  = sleep;\n    assign full                   = FULL;\n    assign almost_full            = ALMOST_FULL;\n    assign wr_ack                 = WR_ACK;\n    assign overflow               = OVERFLOW;\n    assign empty                  = EMPTY;\n    assign almost_empty           = ALMOST_EMPTY;\n    assign valid                  = VALID;\n    assign underflow              = UNDERFLOW;\n    assign prog_full              = PROG_FULL;\n    assign prog_empty             = PROG_EMPTY;\n    assign sbiterr                = SBITERR;\n    assign dbiterr                = DBITERR;\n//    assign wr_rst_busy            = WR_RST_BUSY | wr_rst_busy_o;\n    assign wr_rst_busy            = wr_rst_busy_o;\n    assign rd_rst_busy            = RD_RST_BUSY;\n    assign M_ACLK                 = m_aclk;\n    assign S_ACLK                 = s_aclk;\n    assign S_ARESETN              = s_aresetn;\n    assign S_ACLK_EN              = s_aclk_en;\n    assign M_ACLK_EN              = m_aclk_en;\n    assign S_AXI_AWVALID          = s_axi_awvalid;\n    assign s_axi_awready          = S_AXI_AWREADY;\n    assign S_AXI_WLAST            = s_axi_wlast;\n    assign S_AXI_WVALID           = s_axi_wvalid;\n    assign s_axi_wready           = S_AXI_WREADY;\n    assign s_axi_bvalid           = S_AXI_BVALID;\n    assign S_AXI_BREADY           = s_axi_bready;\n    assign m_axi_awvalid          = M_AXI_AWVALID;\n    assign M_AXI_AWREADY          = m_axi_awready;\n    assign m_axi_wlast            = M_AXI_WLAST;\n    assign m_axi_wvalid           = M_AXI_WVALID;\n    assign M_AXI_WREADY           = m_axi_wready;\n    assign M_AXI_BVALID           = m_axi_bvalid;\n    assign m_axi_bready           = M_AXI_BREADY;\n    assign S_AXI_ARVALID          = s_axi_arvalid;\n    assign s_axi_arready          = S_AXI_ARREADY;\n    assign s_axi_rlast            = S_AXI_RLAST;\n    assign s_axi_rvalid           = S_AXI_RVALID;\n    assign S_AXI_RREADY           = s_axi_rready;\n    assign m_axi_arvalid          = M_AXI_ARVALID;\n    assign M_AXI_ARREADY          = m_axi_arready;\n    assign M_AXI_RLAST            = m_axi_rlast;\n    assign M_AXI_RVALID           = m_axi_rvalid;\n    assign m_axi_rready           = M_AXI_RREADY;\n    assign S_AXIS_TVALID          = s_axis_tvalid;\n    assign s_axis_tready          = S_AXIS_TREADY;\n    assign S_AXIS_TLAST           = s_axis_tlast;\n    assign m_axis_tvalid          = M_AXIS_TVALID;\n    assign M_AXIS_TREADY          = m_axis_tready;\n    assign m_axis_tlast           = M_AXIS_TLAST;\n    assign AXI_AW_INJECTSBITERR   = axi_aw_injectsbiterr;\n    assign AXI_AW_INJECTDBITERR   = axi_aw_injectdbiterr;\n    assign axi_aw_sbiterr         = AXI_AW_SBITERR;\n    assign axi_aw_dbiterr         = AXI_AW_DBITERR;\n    assign axi_aw_overflow        = AXI_AW_OVERFLOW;\n    assign axi_aw_underflow       = AXI_AW_UNDERFLOW;\n    assign axi_aw_prog_full       = AXI_AW_PROG_FULL;\n    assign axi_aw_prog_empty      = AXI_AW_PROG_EMPTY;\n    assign AXI_W_INJECTSBITERR    = axi_w_injectsbiterr;\n    assign AXI_W_INJECTDBITERR    = axi_w_injectdbiterr;\n    assign axi_w_sbiterr          = AXI_W_SBITERR;\n    assign axi_w_dbiterr          = AXI_W_DBITERR;\n    assign axi_w_overflow         = AXI_W_OVERFLOW;\n    assign axi_w_underflow        = AXI_W_UNDERFLOW;\n    assign axi_w_prog_full        = AXI_W_PROG_FULL;\n    assign axi_w_prog_empty       = AXI_W_PROG_EMPTY;\n    assign AXI_B_INJECTSBITERR    = axi_b_injectsbiterr;\n    assign AXI_B_INJECTDBITERR    = axi_b_injectdbiterr;\n    assign axi_b_sbiterr          = AXI_B_SBITERR;\n    assign axi_b_dbiterr          = AXI_B_DBITERR;\n    assign axi_b_overflow         = AXI_B_OVERFLOW;\n    assign axi_b_underflow        = AXI_B_UNDERFLOW;\n    assign axi_b_prog_full        = AXI_B_PROG_FULL;\n    assign axi_b_prog_empty       = AXI_B_PROG_EMPTY;\n    assign AXI_AR_INJECTSBITERR   = axi_ar_injectsbiterr;\n    assign AXI_AR_INJECTDBITERR   = axi_ar_injectdbiterr;\n    assign axi_ar_sbiterr         = AXI_AR_SBITERR;\n    assign axi_ar_dbiterr         = AXI_AR_DBITERR;\n    assign axi_ar_overflow        = AXI_AR_OVERFLOW;\n    assign axi_ar_underflow       = AXI_AR_UNDERFLOW;\n    assign axi_ar_prog_full       = AXI_AR_PROG_FULL;\n    assign axi_ar_prog_empty      = AXI_AR_PROG_EMPTY;\n    assign AXI_R_INJECTSBITERR    = axi_r_injectsbiterr;\n    assign AXI_R_INJECTDBITERR    = axi_r_injectdbiterr;\n    assign axi_r_sbiterr          = AXI_R_SBITERR;\n    assign axi_r_dbiterr          = AXI_R_DBITERR;\n    assign axi_r_overflow         = AXI_R_OVERFLOW;\n    assign axi_r_underflow        = AXI_R_UNDERFLOW;\n    assign axi_r_prog_full        = AXI_R_PROG_FULL;\n    assign axi_r_prog_empty       = AXI_R_PROG_EMPTY;\n    assign AXIS_INJECTSBITERR     = axis_injectsbiterr;\n    assign AXIS_INJECTDBITERR     = axis_injectdbiterr;\n    assign axis_sbiterr           = AXIS_SBITERR;\n    assign axis_dbiterr           = AXIS_DBITERR;\n    assign axis_overflow          = AXIS_OVERFLOW;\n    assign axis_underflow         = AXIS_UNDERFLOW;\n    assign axis_prog_full         = AXIS_PROG_FULL;\n    assign axis_prog_empty        = AXIS_PROG_EMPTY;\n\n\n    assign DIN                       = din;\n    assign PROG_EMPTY_THRESH         = prog_empty_thresh;\n    assign PROG_EMPTY_THRESH_ASSERT  = prog_empty_thresh_assert;\n    assign PROG_EMPTY_THRESH_NEGATE  = prog_empty_thresh_negate;\n    assign PROG_FULL_THRESH          = prog_full_thresh;\n    assign PROG_FULL_THRESH_ASSERT   = prog_full_thresh_assert;\n    assign PROG_FULL_THRESH_NEGATE   = prog_full_thresh_negate;\n    assign dout                      = DOUT;\n    assign data_count                = DATA_COUNT;\n    assign rd_data_count             = RD_DATA_COUNT;\n    assign wr_data_count             = WR_DATA_COUNT;\n    assign S_AXI_AWID                = s_axi_awid;\n    assign S_AXI_AWADDR              = s_axi_awaddr;\n    assign S_AXI_AWLEN               = s_axi_awlen;\n    assign S_AXI_AWSIZE              = s_axi_awsize;\n    assign S_AXI_AWBURST             = s_axi_awburst;\n    assign S_AXI_AWLOCK              = s_axi_awlock;\n    assign S_AXI_AWCACHE             = s_axi_awcache;\n    assign S_AXI_AWPROT              = s_axi_awprot;\n    assign S_AXI_AWQOS               = s_axi_awqos;\n    assign S_AXI_AWREGION            = s_axi_awregion;\n    assign S_AXI_AWUSER              = s_axi_awuser;\n    assign S_AXI_WID                 = s_axi_wid;\n    assign S_AXI_WDATA               = s_axi_wdata;\n    assign S_AXI_WSTRB               = s_axi_wstrb;\n    assign S_AXI_WUSER               = s_axi_wuser;\n    assign s_axi_bid                 = S_AXI_BID;\n    assign s_axi_bresp               = S_AXI_BRESP;\n    assign s_axi_buser               = S_AXI_BUSER;\n    assign m_axi_awid                = M_AXI_AWID;\n    assign m_axi_awaddr              = M_AXI_AWADDR;\n    assign m_axi_awlen               = M_AXI_AWLEN;\n    assign m_axi_awsize              = M_AXI_AWSIZE;\n    assign m_axi_awburst             = M_AXI_AWBURST;\n    assign m_axi_awlock              = M_AXI_AWLOCK;\n    assign m_axi_awcache             = M_AXI_AWCACHE;\n    assign m_axi_awprot              = M_AXI_AWPROT;\n    assign m_axi_awqos               = M_AXI_AWQOS;\n    assign m_axi_awregion            = M_AXI_AWREGION;\n    assign m_axi_awuser              = M_AXI_AWUSER;\n    assign m_axi_wid                 = M_AXI_WID;\n    assign m_axi_wdata               = M_AXI_WDATA;\n    assign m_axi_wstrb               = M_AXI_WSTRB;\n    assign m_axi_wuser               = M_AXI_WUSER;\n    assign M_AXI_BID                 = m_axi_bid;\n    assign M_AXI_BRESP               = m_axi_bresp;\n    assign M_AXI_BUSER               = m_axi_buser;\n    assign S_AXI_ARID                = s_axi_arid;\n    assign S_AXI_ARADDR              = s_axi_araddr; \n    assign S_AXI_ARLEN               = s_axi_arlen;\n    assign S_AXI_ARSIZE              = s_axi_arsize;\n    assign S_AXI_ARBURST             = s_axi_arburst;\n    assign S_AXI_ARLOCK              = s_axi_arlock;\n    assign S_AXI_ARCACHE             = s_axi_arcache;\n    assign S_AXI_ARPROT              = s_axi_arprot;\n    assign S_AXI_ARQOS               = s_axi_arqos;\n    assign S_AXI_ARREGION            = s_axi_arregion;\n    assign S_AXI_ARUSER              = s_axi_aruser;\n    assign s_axi_rid                 = S_AXI_RID;\n    assign s_axi_rdata               = S_AXI_RDATA;\n    assign s_axi_rresp               = S_AXI_RRESP;\n    assign s_axi_ruser               = S_AXI_RUSER;\n    assign m_axi_arid                = M_AXI_ARID;        \n    assign m_axi_araddr              = M_AXI_ARADDR;  \n    assign m_axi_arlen               = M_AXI_ARLEN;\n    assign m_axi_arsize              = M_AXI_ARSIZE;\n    assign m_axi_arburst             = M_AXI_ARBURST;\n    assign m_axi_arlock              = M_AXI_ARLOCK;\n    assign m_axi_arcache             = M_AXI_ARCACHE;\n    assign m_axi_arprot              = M_AXI_ARPROT;\n    assign m_axi_arqos               = M_AXI_ARQOS;\n    assign m_axi_arregion            = M_AXI_ARREGION;\n    assign m_axi_aruser              = M_AXI_ARUSER;\n    assign M_AXI_RID                 = m_axi_rid;        \n    assign M_AXI_RDATA               = m_axi_rdata;  \n    assign M_AXI_RRESP               = m_axi_rresp;\n    assign M_AXI_RUSER               = m_axi_ruser;\n    assign S_AXIS_TDATA              = s_axis_tdata;\n    assign S_AXIS_TSTRB              = s_axis_tstrb;\n    assign S_AXIS_TKEEP              = s_axis_tkeep;\n    assign S_AXIS_TID                = s_axis_tid;\n    assign S_AXIS_TDEST              = s_axis_tdest;\n    assign S_AXIS_TUSER              = s_axis_tuser;\n    assign m_axis_tdata              = M_AXIS_TDATA;\n    assign m_axis_tstrb              = M_AXIS_TSTRB;\n    assign m_axis_tkeep              = M_AXIS_TKEEP;\n    assign m_axis_tid                = M_AXIS_TID;\n    assign m_axis_tdest              = M_AXIS_TDEST;\n    assign m_axis_tuser              = M_AXIS_TUSER;\n    assign AXI_AW_PROG_FULL_THRESH   = axi_aw_prog_full_thresh;\n    assign AXI_AW_PROG_EMPTY_THRESH  = axi_aw_prog_empty_thresh;\n    assign axi_aw_data_count         = AXI_AW_DATA_COUNT;\n    assign axi_aw_wr_data_count      = AXI_AW_WR_DATA_COUNT;\n    assign axi_aw_rd_data_count      = AXI_AW_RD_DATA_COUNT;\n    assign AXI_W_PROG_FULL_THRESH    = axi_w_prog_full_thresh;\n    assign AXI_W_PROG_EMPTY_THRESH   = axi_w_prog_empty_thresh;\n    assign axi_w_data_count          = AXI_W_DATA_COUNT;\n    assign axi_w_wr_data_count       = AXI_W_WR_DATA_COUNT;\n    assign axi_w_rd_data_count       = AXI_W_RD_DATA_COUNT;\n    assign AXI_B_PROG_FULL_THRESH    = axi_b_prog_full_thresh;\n    assign AXI_B_PROG_EMPTY_THRESH   = axi_b_prog_empty_thresh;\n    assign axi_b_data_count          = AXI_B_DATA_COUNT;\n    assign axi_b_wr_data_count       = AXI_B_WR_DATA_COUNT;\n    assign axi_b_rd_data_count       = AXI_B_RD_DATA_COUNT;\n    assign AXI_AR_PROG_FULL_THRESH   = axi_ar_prog_full_thresh;\n    assign AXI_AR_PROG_EMPTY_THRESH  = axi_ar_prog_empty_thresh;\n    assign axi_ar_data_count         = AXI_AR_DATA_COUNT;\n    assign axi_ar_wr_data_count      = AXI_AR_WR_DATA_COUNT;\n    assign axi_ar_rd_data_count      = AXI_AR_RD_DATA_COUNT;\n    assign AXI_R_PROG_FULL_THRESH    = axi_r_prog_full_thresh;\n    assign AXI_R_PROG_EMPTY_THRESH   = axi_r_prog_empty_thresh;\n    assign axi_r_data_count          = AXI_R_DATA_COUNT;\n    assign axi_r_wr_data_count       = AXI_R_WR_DATA_COUNT;\n    assign axi_r_rd_data_count       = AXI_R_RD_DATA_COUNT;\n    assign AXIS_PROG_FULL_THRESH     = axis_prog_full_thresh;\n    assign AXIS_PROG_EMPTY_THRESH    = axis_prog_empty_thresh;\n    assign axis_data_count           = AXIS_DATA_COUNT;\n    assign axis_wr_data_count        = AXIS_WR_DATA_COUNT;\n    assign axis_rd_data_count        = AXIS_RD_DATA_COUNT;\n\n\n  generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_COMMON_CLOCK \t\t(C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DATA_COUNT_WIDTH\t\t(C_DATA_COUNT_WIDTH),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH),\n        .C_DOUT_RST_VAL\t\t\t(C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),\n        .C_DOUT_WIDTH\t\t\t(C_DOUT_WIDTH),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n        .C_HAS_ALMOST_EMPTY\t\t(C_HAS_ALMOST_EMPTY),\n        .C_HAS_ALMOST_FULL\t\t(C_HAS_ALMOST_FULL),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_DATA_COUNT\t\t(C_HAS_DATA_COUNT),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_HAS_RD_DATA_COUNT\t\t(C_HAS_RD_DATA_COUNT),\n        .C_HAS_RD_RST\t\t\t(C_HAS_RD_RST),\n        .C_HAS_RST\t\t\t(C_HAS_RST),\n        .C_HAS_SRST\t\t\t(C_HAS_SRST),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_HAS_VALID\t\t\t(C_HAS_VALID),\n        .C_HAS_WR_ACK\t\t\t(C_HAS_WR_ACK),\n        .C_HAS_WR_DATA_COUNT\t\t(C_HAS_WR_DATA_COUNT),\n        .C_HAS_WR_RST\t\t\t(C_HAS_WR_RST),\n        .C_IMPLEMENTATION_TYPE\t\t(C_IMPLEMENTATION_TYPE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_MEMORY_TYPE\t\t\t(C_MEMORY_TYPE),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n        .C_PRELOAD_LATENCY\t\t(C_PRELOAD_LATENCY),\n        .C_PRELOAD_REGS\t\t\t(C_PRELOAD_REGS),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL),\n        .C_PROG_EMPTY_THRESH_NEGATE_VAL\t(C_PROG_EMPTY_THRESH_NEGATE_VAL),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL),\n        .C_PROG_FULL_THRESH_NEGATE_VAL\t(C_PROG_FULL_THRESH_NEGATE_VAL),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_RD_DATA_COUNT_WIDTH),\n        .C_RD_DEPTH\t\t\t(C_RD_DEPTH),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_RD_PNTR_WIDTH\t\t(C_RD_PNTR_WIDTH),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n        .C_USE_ECC                      (C_USE_ECC),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_EN_SAFETY_CKT\t\t(C_EN_SAFETY_CKT),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_USE_FWFT_DATA_COUNT\t\t(C_USE_FWFT_DATA_COUNT),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_DATA_COUNT_WIDTH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (C_ENABLE_RST_SYNC),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE),\n        .C_AXI_TYPE                     (C_AXI_TYPE),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE)\n      )\n    fifo_generator_v13_2_5_conv_dut\n      (\n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .CLK                      (CLK),\n        .RST                      (RST),\n        .SRST                     (SRST),\n        .WR_CLK                   (WR_CLK),\n        .WR_RST                   (WR_RST),\n        .RD_CLK                   (RD_CLK),\n        .RD_RST                   (RD_RST),\n        .DIN                      (DIN),\n        .WR_EN                    (WR_EN),\n        .RD_EN                    (RD_EN),\n        .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),\n        .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),\n        .PROG_FULL_THRESH         (PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),\n        .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),\n        .INT_CLK                  (INT_CLK),\n        .INJECTDBITERR            (INJECTDBITERR), \n        .INJECTSBITERR            (INJECTSBITERR),\n  \n        .DOUT                     (DOUT),\n        .FULL                     (FULL),\n        .ALMOST_FULL              (ALMOST_FULL),\n        .WR_ACK                   (WR_ACK),\n        .OVERFLOW                 (OVERFLOW),\n        .EMPTY                    (EMPTY),\n        .ALMOST_EMPTY             (ALMOST_EMPTY),\n        .VALID                    (VALID),\n        .UNDERFLOW                (UNDERFLOW),\n        .DATA_COUNT               (DATA_COUNT),\n        .RD_DATA_COUNT            (RD_DATA_COUNT),\n        .WR_DATA_COUNT            (wr_data_count_in),\n        .PROG_FULL                (PROG_FULL),\n        .PROG_EMPTY               (PROG_EMPTY),\n        .SBITERR                  (SBITERR),\n        .DBITERR                  (DBITERR),\n        .wr_rst_busy_o            (wr_rst_busy_o),\n        .wr_rst_busy              (wr_rst_busy_i),\n        .rd_rst_busy              (rd_rst_busy),\n        .wr_rst_i_out             (wr_rst_int),\n        .rd_rst_i_out             (rd_rst_int)\n       );\n  end endgenerate\n\n\n\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n  localparam C_AXI_SIZE_WIDTH   = 3;\n  localparam C_AXI_BURST_WIDTH  = 2;\n  localparam C_AXI_CACHE_WIDTH  = 4;\n  localparam C_AXI_PROT_WIDTH   = 3;\n  localparam C_AXI_QOS_WIDTH    = 4;\n  localparam C_AXI_REGION_WIDTH = 4;\n  localparam C_AXI_BRESP_WIDTH  = 2;\n  localparam C_AXI_RRESP_WIDTH  = 2;\n\n  localparam IS_AXI_STREAMING  = C_INTERFACE_TYPE == 1 ? 1 : 0;\n  localparam TDATA_OFFSET      = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;\n  localparam TSTRB_OFFSET      = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;\n  localparam TKEEP_OFFSET      = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;\n  localparam TID_OFFSET        = C_HAS_AXIS_TID   == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;\n  localparam TDEST_OFFSET      = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;\n  localparam TUSER_OFFSET      = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;\n  localparam LOG_DEPTH_AXIS    = find_log2(C_WR_DEPTH_AXIS); \n  localparam LOG_WR_DEPTH      = find_log2(C_WR_DEPTH); \n\n\n  function [LOG_DEPTH_AXIS-1:0] bin2gray;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      begin\n         bin2gray = x ^ (x>>1);\n      end\n   endfunction\n\n  function [LOG_DEPTH_AXIS-1:0] gray2bin;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      integer                i;\n      begin\n         gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];\n         for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin\n            gray2bin[i] =  gray2bin[i+1] ^ x[i];\n         end\n      end\n   endfunction\n\nwire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;\nwire  [LOG_WR_DEPTH-1 : 0]  w_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;\nreg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;\nwire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;\nwire [LOG_WR_DEPTH : 0] r_inv_pad;\nwire [LOG_WR_DEPTH-1 : 0] d_cnt;\nreg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;\nreg adj_w_cnt_rd_pad_0 = 0;\nreg r_inv_pad_0 = 0;\n\n\n   genvar l;\n\n   generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (LOG_WR_DEPTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_int), \n         .CLK      (RD_CLK), \n         .DIN      (w_q[l-1]), \n         .DOUT     (w_q[l])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter\n    assign wr_eop_ad = WR_EN & !(FULL);\n    assign rd_eop_ad = RD_EN & !(EMPTY);\n\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt    <= 1'b0;\n      else if (wr_eop_ad)\n        w_cnt    <= w_cnt + 1;\n    end\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt_gc    <= 1'b0;\n      else \n        w_cnt_gc    <= bin2gray(w_cnt);\n    end\n\n\n    assign  w_q[0]  = w_cnt_gc;\n    assign  w_cnt_gc_asreg_last       = w_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        w_cnt_rd    <= 1'b0;\n      else \n        w_cnt_rd    <= gray2bin(w_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        r_cnt    <= 1'b0;\n      else if (rd_eop_ad)\n        r_cnt    <= r_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;\n   assign r_inv_pad[LOG_WR_DEPTH : 1]        = ~r_cnt;\n   assign adj_w_cnt_rd_pad[0]                = adj_w_cnt_rd_pad_0;\n   assign r_inv_pad[0]                       = r_inv_pad_0;\n\n\n  always @ ( rd_eop_ad )\n    begin\n      if (!rd_eop_ad) begin\n        adj_w_cnt_rd_pad_0    <= 1'b1;\n        r_inv_pad_0           <= 1'b1;\n      end else begin \n        adj_w_cnt_rd_pad_0    <= 1'b0;\n        r_inv_pad_0           <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        d_cnt_pad    <= 1'b0;\n      else \n        d_cnt_pad    <= adj_w_cnt_rd_pad + r_inv_pad ;\n    end\n\n   assign  d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;\n   assign  WR_DATA_COUNT = d_cnt;\n\n  end endgenerate // fifo_ic_adapter\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter\n   assign  WR_DATA_COUNT = wr_data_count_in;\n\n  end endgenerate // fifo_icn_adapter\n\n\n\n  wire                          inverted_reset = ~S_ARESETN;\n  wire                          axi_rs_rst;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_din          ;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_dout         ;\n  wire                          axis_full         ;\n  wire                          axis_almost_full  ;\n  wire                          axis_empty        ;\n  wire                          axis_s_axis_tready;\n  wire                          axis_m_axis_tvalid;\n  wire                          axis_wr_en        ;\n  wire                          axis_rd_en        ;\n  wire                          axis_we           ;\n  wire                          axis_re           ;\n  wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;\n  reg                           axis_pkt_read = 1'b0;\n  wire                          axis_rd_rst;\n  wire                          axis_wr_rst;\n\n  generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||\n               C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst\n      reg                           rst_d1 = 0        ;\n      reg                           rst_d2 = 0        ;\n      reg [3:0]                    axi_rst = 4'h0     ;\n      always @ (posedge inverted_reset or posedge S_ACLK) begin\n        if (inverted_reset) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          axi_rst        <= 4'hf;\n        end else begin\n          rst_d1         <= #`TCQ 1'b0;\n          rst_d2         <= #`TCQ rst_d1;\n          axi_rst        <= #`TCQ {axi_rst[2:0],1'b0};\n        end\n      end\n\n      assign axi_rs_rst = axi_rst[3];//rst_d2;\n  end endgenerate // gaxi_rs_rst\n\n  generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming\n\n    // Write protection when almost full or prog_full is high\n    assign axis_we    = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : \n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign axis_re    = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :\n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? axis_we & S_ACLK_EN : axis_we;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE               (C_INTERFACE_TYPE),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 2  || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_AXIS),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_AXIS),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),\n        .C_USE_ECC                      (C_USE_ECC_AXIS),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_AXIS),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_axis_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (axis_wr_en),\n        .RD_EN                    (axis_rd_en),\n        .PROG_FULL_THRESH         (AXIS_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXIS_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .INJECTDBITERR            (AXIS_INJECTDBITERR), \n        .INJECTSBITERR            (AXIS_INJECTSBITERR),\n  \n        .DIN                      (axis_din),\n        .DOUT                     (axis_dout),\n        .FULL                     (axis_full),\n        .EMPTY                    (axis_empty),\n        .ALMOST_FULL              (axis_almost_full),\n        .PROG_FULL                (AXIS_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXIS_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (AXIS_OVERFLOW),\n        .VALID                    (),\n        .UNDERFLOW                (AXIS_UNDERFLOW),\n        .DATA_COUNT               (axis_dc),\n        .RD_DATA_COUNT            (AXIS_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXIS_WR_DATA_COUNT),\n        .SBITERR                  (AXIS_SBITERR),\n        .DBITERR                  (AXIS_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_axis),\n        .rd_rst_busy              (rd_rst_busy_axis),\n        .wr_rst_i_out             (axis_wr_rst),\n        .rd_rst_i_out             (axis_rd_rst),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign axis_s_axis_tready    = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;\n    assign axis_m_axis_tvalid    = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;\n    assign S_AXIS_TREADY         = axis_s_axis_tready;\n    assign M_AXIS_TVALID         = axis_m_axis_tvalid;\n\n  end endgenerate // axi_streaming\n\n  wire axis_wr_eop;\n  reg  axis_wr_eop_d1 = 1'b0;\n  wire axis_rd_eop;\n  integer  axis_pkt_cnt;\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)\n        axis_pkt_read    <= 1'b0;\n      else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_wr_eop_d1    <= 1'b0;\n      else\n        axis_wr_eop_d1   <= axis_wr_eop;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_cnt    <= 0;\n      else if (axis_wr_eop_d1 && ~axis_rd_eop)\n        axis_pkt_cnt    <= axis_pkt_cnt + 1;\n      else if (axis_rd_eop && ~axis_wr_eop_d1)\n        axis_pkt_cnt    <= axis_pkt_cnt - 1;\n    end\n  end endgenerate // gaxis_pkt_fifo_cc\n\n\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;\nwire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;\nwire axis_rd_has_rst;\nwire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;\nwire  [LOG_DEPTH_AXIS-1 : 0]  wpkt_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;\nwire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;\nwire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;\nwire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;\nwire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;\nreg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;\nreg adj_axis_wpkt_cnt_rd_pad_0 = 0;\nreg rpkt_inv_pad_0 = 0;\nwire axis_af_rd ;\n\ngenerate if (C_HAS_RST == 1) begin : rst_blk_has\n  assign axis_rd_has_rst = axis_rd_rst;\nend endgenerate //rst_blk_has\n\ngenerate if (C_HAS_RST == 0) begin :rst_blk_no\n  assign axis_rd_has_rst = 1'b0;\nend endgenerate //rst_blk_no\n\n   genvar i;\n\n   generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (LOG_DEPTH_AXIS)\n        )\n     rd_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (wpkt_q[i-1]), \n         .DOUT     (wpkt_q[i])\n        );\n \n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (1)\n        )\n     wr_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (axis_af_q[i-1]), \n         .DOUT     (axis_af_q[i])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (diff_pkt_cnt == 1))\n        axis_pkt_read    <= 1'b0;\n      else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt    <= 1'b0;\n      else if (axis_wr_eop)\n        axis_wpkt_cnt    <= axis_wpkt_cnt + 1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt_gc    <= 1'b0;\n      else \n        axis_wpkt_cnt_gc    <= bin2gray(axis_wpkt_cnt);\n    end\n\n\n    assign  wpkt_q[0]  = axis_wpkt_cnt_gc;\n    assign  axis_wpkt_cnt_gc_asreg_last       = wpkt_q[C_SYNCHRONIZER_STAGE];\n    assign  axis_af_q[0]                      = axis_almost_full;\n    //assign  axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];\n    assign  axis_af_rd                        = axis_af_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_wpkt_cnt_rd    <= 1'b0;\n      else \n        axis_wpkt_cnt_rd    <= gray2bin(axis_wpkt_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_rpkt_cnt    <= 1'b0;\n      else if (axis_rd_eop)\n        axis_rpkt_cnt    <= axis_rpkt_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;\n   assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1]             = ~axis_rpkt_cnt;\n   assign adj_axis_wpkt_cnt_rd_pad[0]                                = adj_axis_wpkt_cnt_rd_pad_0;\n   assign rpkt_inv_pad[0]                                            = rpkt_inv_pad_0;\n\n\n  always @ ( axis_rd_eop )\n    begin\n      if (!axis_rd_eop) begin\n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b1;\n        rpkt_inv_pad_0                <= 1'b1;\n      end else begin \n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b0;\n        rpkt_inv_pad_0                <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        diff_pkt_cnt_pad    <= 1'b0;\n      else \n        diff_pkt_cnt_pad    <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;\n    end\n\n   assign  diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;\n\n\n\n\n\n   end endgenerate // gaxis_pkt_fifo_ic\n\n\n\n\n  // Generate the accurate data count for axi stream packet fifo configuration\n  reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_dc_pkt_fifo <= 0;\n      else if (axis_wr_en && (~axis_rd_en))\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;\n      else if (~axis_wr_en && axis_rd_en)\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;\n    end\n    assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;\n  end endgenerate // gdc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt\n    assign AXIS_DATA_COUNT = 0;\n  end endgenerate // gndc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc\n    assign AXIS_DATA_COUNT = axis_dc;\n  end endgenerate // gdc\n\n  // Register Slice for Write Address Channel\n  generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_AXIS),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_AXIS)\n            )\n    axis_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (axis_din),\n          .S_VALID                   (axis_wr_en),\n          .S_READY                   (S_AXIS_TREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (axis_dout),\n          .M_VALID                   (M_AXIS_TVALID),\n          .M_READY                   (axis_rd_en)\n          );\n  end endgenerate // gaxis_reg_slice\n\n\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata\n    assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;\n    assign M_AXIS_TDATA   = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb\n    assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;\n    assign M_AXIS_TSTRB   = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep\n    assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;\n    assign M_AXIS_TKEEP   = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid\n    assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;\n    assign M_AXIS_TID     = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest\n    assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;\n    assign M_AXIS_TDEST   = axis_dout[TID_OFFSET-1:TDEST_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser\n    assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;\n    assign M_AXIS_TUSER   = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast\n    assign axis_din[0] = S_AXIS_TLAST;\n    assign M_AXIS_TLAST   = axis_dout[0];\n  end endgenerate\n\n  //###########################################################################\n  //  AXI FULL Write Channel (axi_write_channel)\n  //###########################################################################\n\n  localparam IS_AXI_FULL       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;\n  localparam IS_AXI_LITE       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;\n\n  localparam IS_AXI_FULL_WACH  = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WDCH  = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WRCH  = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RACH  = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RDCH  = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_AXI_LITE_WACH  = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WDCH  = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WRCH  = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RACH  = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RDCH  = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_WR_ADDR_CH     = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;\n  localparam IS_WR_DATA_CH     = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;\n  localparam IS_WR_RESP_CH     = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;\n  localparam IS_RD_ADDR_CH     = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;\n  localparam IS_RD_DATA_CH     = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;\n\n  localparam AWID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;\n  localparam AWADDR_OFFSET     = AWID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam AWLEN_OFFSET      = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;\n  localparam AWSIZE_OFFSET     = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;\n  localparam AWBURST_OFFSET    = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;\n  localparam AWLOCK_OFFSET     = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;\n  localparam AWCACHE_OFFSET    = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;\n  localparam AWPROT_OFFSET     = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam AWQOS_OFFSET      = AWPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam AWREGION_OFFSET   = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;\n  localparam AWUSER_OFFSET     = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;\n\n  localparam WID_OFFSET        = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;\n  localparam WDATA_OFFSET      = WID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam WSTRB_OFFSET      = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;\n  localparam WUSER_OFFSET      = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;\n\n  localparam BID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;\n  localparam BRESP_OFFSET      = BID_OFFSET - C_AXI_BRESP_WIDTH;\n  localparam BUSER_OFFSET      = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;\n\n\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_din          ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout         ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout_pkt     ;\n  wire                          wach_full         ;\n  wire                          wach_almost_full  ;\n  wire                          wach_prog_full    ;\n  wire                          wach_empty        ;\n  wire                          wach_almost_empty ;\n  wire                          wach_prog_empty   ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_din          ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_dout         ;\n  wire                          wdch_full         ;\n  wire                          wdch_almost_full  ;\n  wire                          wdch_prog_full    ;\n  wire                          wdch_empty        ;\n  wire                          wdch_almost_empty ;\n  wire                          wdch_prog_empty   ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_din          ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_dout         ;\n  wire                          wrch_full         ;\n  wire                          wrch_almost_full  ;\n  wire                          wrch_prog_full    ;\n  wire                          wrch_empty        ;\n  wire                          wrch_almost_empty ;\n  wire                          wrch_prog_empty   ;\n  wire                          axi_aw_underflow_i;\n  wire                          axi_w_underflow_i ;\n  wire                          axi_b_underflow_i ;\n  wire                          axi_aw_overflow_i ;\n  wire                          axi_w_overflow_i  ;\n  wire                          axi_b_overflow_i  ;\n  wire                          axi_wr_underflow_i;\n  wire                          axi_wr_overflow_i ;\n  wire                          wach_s_axi_awready;\n  wire                          wach_m_axi_awvalid;\n  wire                          wach_wr_en        ;\n  wire                          wach_rd_en        ;\n  wire                          wdch_s_axi_wready ;\n  wire                          wdch_m_axi_wvalid ;\n  wire                          wdch_wr_en        ;\n  wire                          wdch_rd_en        ;\n  wire                          wrch_s_axi_bvalid ;\n  wire                          wrch_m_axi_bready ;\n  wire                          wrch_wr_en        ;\n  wire                          wrch_rd_en        ;\n  wire                          txn_count_up      ;\n  wire                          txn_count_down    ;\n  wire                          awvalid_en        ;\n  wire                          awvalid_pkt       ;\n  wire                          awready_pkt       ;\n  integer                       wr_pkt_count      ;\n  wire                          wach_we           ;\n  wire                          wach_re           ;\n  wire                          wdch_we           ;\n  wire                          wdch_re           ;\n  wire                          wrch_we           ;\n  wire                          wrch_re           ;\n\n  generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel\n    // Write protection when almost full or prog_full is high\n    assign wach_we    = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wach_re    = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        wach_m_axi_awvalid & awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY && wach_m_axi_awvalid :\n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY : 1'b0;\n    assign wach_wr_en = (C_HAS_SLAVE_CE == 1)  ? wach_we & S_ACLK_EN : wach_we;\n    assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 2  || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),\n        .C_USE_ECC                      (C_USE_ECC_WACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wach_wr_en),\n        .RD_EN                    (wach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AW_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AW_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AW_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AW_INJECTSBITERR),\n  \n        .DIN                      (wach_din),\n        .DOUT                     (wach_dout_pkt),\n        .FULL                     (wach_full),\n        .EMPTY                    (wach_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_AW_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_AW_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_aw_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_aw_underflow_i),\n        .DATA_COUNT               (AXI_AW_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AW_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AW_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AW_SBITERR),\n        .DBITERR                  (AXI_AW_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wach),\n        .rd_rst_busy              (rd_rst_busy_wach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wach_s_axi_awready    = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;\n    assign wach_m_axi_awvalid   = ~wach_empty;\n    assign S_AXI_AWREADY        = wach_s_axi_awready;\n\n    assign AXI_AW_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;\n    assign AXI_AW_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_aw_overflow_i  : 0;\n\n  end endgenerate // axi_write_address_channel\n\n  // Register Slice for Write Address Channel\n  generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WACH)\n            )\n    wach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_din),\n          .S_VALID                   (S_AXI_AWVALID),\n          .S_READY                   (S_AXI_AWREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n  end endgenerate // gwach_reg_slice\n  \n  generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (1)\n            )\n    wach_pkt_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_dout_pkt),\n          .S_VALID                   (awvalid_pkt),\n          .S_READY                   (awready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n\n    assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;\n\n    assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; \n    assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset == 1) begin\n\twr_pkt_count <= 0;\n      end else begin\n\tif(txn_count_up == 1 && txn_count_down == 0) begin\n\t  wr_pkt_count <= wr_pkt_count + 1;\n\tend else if(txn_count_up == 0 && txn_count_down == 1) begin\n\t  wr_pkt_count <= wr_pkt_count - 1;\n\tend\n      end\n    end //Always end\n    assign awvalid_en = (wr_pkt_count > 0)?1:0;\n  end endgenerate\n  \n  generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr\n    assign awvalid_en    = 1;    \n    assign wach_dout     = wach_dout_pkt;\n    assign M_AXI_AWVALID = wach_m_axi_awvalid;\n  end\n  endgenerate\n\n\n\n  generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel\n    // Write protection when almost full or prog_full is high\n    assign wdch_we    = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wdch_re    = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;\n    assign wdch_wr_en = (C_HAS_SLAVE_CE == 1)  ? wdch_we & S_ACLK_EN : wdch_we;\n    assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;\n\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 2  || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),\n        .C_USE_ECC                      (C_USE_ECC_WDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wdch_wr_en),\n        .RD_EN                    (wdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_W_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_W_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_W_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_W_INJECTSBITERR),\n  \n        .DIN                      (wdch_din),\n        .DOUT                     (wdch_dout),\n        .FULL                     (wdch_full),\n        .EMPTY                    (wdch_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_W_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_W_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_w_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_w_underflow_i),\n        .DATA_COUNT               (AXI_W_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_W_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_W_WR_DATA_COUNT),\n        .SBITERR                  (AXI_W_SBITERR),\n        .DBITERR                  (AXI_W_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wdch),\n        .rd_rst_busy              (rd_rst_busy_wdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wdch_s_axi_wready     = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;\n    assign wdch_m_axi_wvalid = ~wdch_empty;\n    assign S_AXI_WREADY      = wdch_s_axi_wready;\n    assign M_AXI_WVALID      = wdch_m_axi_wvalid;\n\n    assign AXI_W_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i  : 0;\n    assign AXI_W_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_w_overflow_i   : 0;\n\n  end endgenerate // axi_write_data_channel\n\n  // Register Slice for Write Data Channel\n  generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WDCH)\n            )\n    wdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wdch_din),\n          .S_VALID                   (S_AXI_WVALID),\n          .S_READY                   (S_AXI_WREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wdch_dout),\n          .M_VALID                   (M_AXI_WVALID),\n          .M_READY                   (M_AXI_WREADY)\n          );\n  end endgenerate // gwdch_reg_slice\n\n  generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel\n    // Write protection when almost full or prog_full is high\n    assign wrch_we    = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wrch_re    = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;\n    assign wrch_wr_en = (C_HAS_MASTER_CE == 1)  ? wrch_we & M_ACLK_EN : wrch_we;\n    assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 2  || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WRCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WRCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),\n        .C_USE_ECC                      (C_USE_ECC_WRCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WRCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WRCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wrch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wrch_wr_en),\n        .RD_EN                    (wrch_rd_en),\n        .PROG_FULL_THRESH         (AXI_B_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_B_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .INJECTDBITERR            (AXI_B_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_B_INJECTSBITERR),\n  \n        .DIN                      (wrch_din),\n        .DOUT                     (wrch_dout),\n        .FULL                     (wrch_full),\n        .EMPTY                    (wrch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_B_PROG_FULL),\n        .PROG_EMPTY               (AXI_B_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_b_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_b_underflow_i),\n        .DATA_COUNT               (AXI_B_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_B_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_B_WR_DATA_COUNT),\n        .SBITERR                  (AXI_B_SBITERR),\n        .DBITERR                  (AXI_B_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wrch),\n        .rd_rst_busy              (rd_rst_busy_wrch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wrch_s_axi_bvalid = ~wrch_empty;\n    assign wrch_m_axi_bready     = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;\n    assign S_AXI_BVALID      = wrch_s_axi_bvalid;\n    assign M_AXI_BREADY      = wrch_m_axi_bready;\n\n    assign AXI_B_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i  : 0;\n    assign AXI_B_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_b_overflow_i   : 0;\n  end endgenerate // axi_write_resp_channel\n\n  // Register Slice for Write Response Channel\n  generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WRCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WRCH)\n            )\n    wrch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wrch_din),\n          .S_VALID                   (M_AXI_BVALID),\n          .S_READY                   (M_AXI_BREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wrch_dout),\n          .M_VALID                   (S_AXI_BVALID),\n          .M_READY                   (S_AXI_BREADY)\n          );\n  end endgenerate // gwrch_reg_slice\n\n\n    assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW  == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;\n    assign axi_wr_overflow_i  = C_USE_COMMON_OVERFLOW   == 1 ? (axi_aw_overflow_i  || axi_w_overflow_i  || axi_b_overflow_i)  : 0;\n\n  generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output\n    assign M_AXI_AWADDR    = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];    \n    assign M_AXI_AWLEN     = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];    \n    assign M_AXI_AWSIZE    = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];    \n    assign M_AXI_AWBURST   = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];    \n    assign M_AXI_AWLOCK    = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];    \n    assign M_AXI_AWCACHE   = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];    \n    assign M_AXI_AWQOS     = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];    \n    assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET]    = S_AXI_AWADDR;\n    assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET]   = S_AXI_AWLEN;\n    assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET]   = S_AXI_AWSIZE;\n    assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;\n    assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;\n    assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;\n    assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;\n    assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET]   = S_AXI_AWQOS;\n  end endgenerate // axi_wach_output\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion\n    assign M_AXI_AWREGION  = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];    \n  end endgenerate // axi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion\n    assign M_AXI_AWREGION  = 0;    \n  end endgenerate // naxi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser\n    assign M_AXI_AWUSER  = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];    \n  end endgenerate // axi_awuser\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser\n    assign M_AXI_AWUSER  = 0;    \n  end endgenerate // naxi_awuser\n\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid\n    assign M_AXI_AWID      = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];\n  end endgenerate //axi_awid\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid\n    assign M_AXI_AWID      = 0;\n  end endgenerate //naxi_awid\n\n  generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output\n    assign M_AXI_WDATA     = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n    assign M_AXI_WLAST     = wdch_dout[0];\n    assign wdch_din[WID_OFFSET-1:WDATA_OFFSET]   = S_AXI_WDATA;\n    assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;\n    assign wdch_din[0]   = S_AXI_WLAST;\n  end endgenerate // axi_wdch_output\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin\n    assign M_AXI_WID       = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];\n  end endgenerate\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin\n    assign M_AXI_WID       = 0;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin\n    assign M_AXI_WUSER     = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];    \n  end endgenerate\n  generate if (C_HAS_AXI_WUSER == 0) begin\n    assign M_AXI_WUSER       = 0;\n  end endgenerate\n\n  generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output\n    assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; \n    assign wrch_din[BID_OFFSET-1:BRESP_OFFSET]   = M_AXI_BRESP;\n  end endgenerate // axi_wrch_output\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser\n    assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];\n  end endgenerate // axi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser\n    assign S_AXI_BUSER = 0;\n  end endgenerate // naxi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid\n    assign S_AXI_BID   =  wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];\n  end endgenerate // axi_bid\n  \n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid\n    assign S_AXI_BID   =  0 ;\n  end endgenerate // naxi_bid  \n\n\n  generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1\n    assign wach_din        = {S_AXI_AWADDR, S_AXI_AWPROT};\n    assign M_AXI_AWADDR    = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];    \n  end endgenerate // axi_wach_output1\n\n  generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1\n    assign wdch_din        = {S_AXI_WDATA, S_AXI_WSTRB};\n    assign M_AXI_WDATA     = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n  end endgenerate // axi_wdch_output1\n\n  generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1\n    assign wrch_din        = M_AXI_BRESP;\n    assign S_AXI_BRESP     = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; \n  end endgenerate // axi_wrch_output1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1\n    assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET]     = S_AXI_AWUSER;\n  end endgenerate // gwach_din1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2\n    assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET]     = S_AXI_AWID;\n  end endgenerate // gwach_din2\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3\n    assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET]     = S_AXI_AWREGION;\n  end endgenerate // gwach_din3\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1\n    assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;\n  end endgenerate // gwdch_din1\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2\n    assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;\n  end endgenerate // gwdch_din2\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1\n    assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET]    = M_AXI_BUSER;\n  end endgenerate // gwrch_din1\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2\n    assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET]    = M_AXI_BID;\n  end endgenerate // gwrch_din2\n\n  //end of  axi_write_channel\n\n  //###########################################################################\n  //  AXI FULL Read Channel (axi_read_channel)\n  //###########################################################################\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_din            ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout           ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout_pkt       ;\n  wire                               rach_full           ;\n  wire                               rach_almost_full    ;\n  wire                               rach_prog_full      ;\n  wire                               rach_empty          ;\n  wire                               rach_almost_empty   ;\n  wire                               rach_prog_empty     ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_din            ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_dout           ;\n  wire                               rdch_full           ;\n  wire                               rdch_almost_full    ;\n  wire                               rdch_prog_full      ;\n  wire                               rdch_empty          ;\n  wire                               rdch_almost_empty   ;\n  wire                               rdch_prog_empty     ;\n  wire                               axi_ar_underflow_i  ;\n  wire                               axi_r_underflow_i   ;\n  wire                               axi_ar_overflow_i   ;\n  wire                               axi_r_overflow_i    ;\n  wire                               axi_rd_underflow_i  ;\n  wire                               axi_rd_overflow_i   ;\n  wire                               rach_s_axi_arready  ;\n  wire                               rach_m_axi_arvalid  ;\n  wire                               rach_wr_en          ;\n  wire                               rach_rd_en          ;\n  wire                               rdch_m_axi_rready   ;\n  wire                               rdch_s_axi_rvalid   ;\n  wire                               rdch_wr_en          ;\n  wire                               rdch_rd_en          ;\n  wire                               arvalid_pkt         ;\n  wire                               arready_pkt         ;\n  wire                               arvalid_en          ;\n  wire                               rdch_rd_ok          ;\n  wire                               accept_next_pkt     ;\n  integer                            rdch_free_space     ;\n  integer                            rdch_commited_space ;\n  wire                               rach_we             ;\n  wire                               rach_re             ;\n  wire                               rdch_we             ;\n  wire                               rdch_re             ;\n\n  localparam ARID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;\n  localparam ARADDR_OFFSET     = ARID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam ARLEN_OFFSET      = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;\n  localparam ARSIZE_OFFSET     = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;\n  localparam ARBURST_OFFSET    = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;\n  localparam ARLOCK_OFFSET     = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;\n  localparam ARCACHE_OFFSET    = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;\n  localparam ARPROT_OFFSET     = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam ARQOS_OFFSET      = ARPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam ARREGION_OFFSET   = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;\n  localparam ARUSER_OFFSET     = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;\n\n  localparam RID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;\n  localparam RDATA_OFFSET      = RID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam RRESP_OFFSET      = RDATA_OFFSET - C_AXI_RRESP_WIDTH;\n  localparam RUSER_OFFSET      = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;\n\n\n  generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rach_we    = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;\n\n    // Read protection when almost empty or prog_empty is high\n//    assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;\n    assign rach_re    = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        rach_m_axi_arvalid & arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY && rach_m_axi_arvalid :\n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY : 1'b0;\n    assign rach_wr_en = (C_HAS_SLAVE_CE == 1)  ? rach_we & S_ACLK_EN : rach_we;\n    assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;\n\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 2  || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),\n        .C_USE_ECC                      (C_USE_ECC_RACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_rach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rach_wr_en),\n        .RD_EN                    (rach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AR_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AR_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AR_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AR_INJECTSBITERR),\n  \n        .DIN                      (rach_din),\n        .DOUT                     (rach_dout_pkt),\n        .FULL                     (rach_full),\n        .EMPTY                    (rach_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_AR_PROG_FULL),\n        .PROG_EMPTY               (AXI_AR_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_ar_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_ar_underflow_i),\n        .DATA_COUNT               (AXI_AR_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AR_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AR_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AR_SBITERR),\n        .DBITERR                  (AXI_AR_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rach),\n        .rd_rst_busy              (rd_rst_busy_rach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rach_s_axi_arready    = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;\n    assign rach_m_axi_arvalid = ~rach_empty;\n    assign S_AXI_ARREADY      = rach_s_axi_arready;\n\n    assign AXI_AR_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;\n    assign AXI_AR_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_ar_overflow_i  : 0;\n\n  end endgenerate // axi_read_addr_channel\n\n  // Register Slice for Read Address Channel\n  generate if (C_RACH_TYPE == 1) begin : grach_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RACH)\n            )\n    rach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_din),\n          .S_VALID                   (S_AXI_ARVALID),\n          .S_READY                   (S_AXI_ARREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice\n\n  // Register Slice for Read Address Channel for MM Packet FIFO\n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (1)\n            )\n    reg_slice_mm_pkt_fifo_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_dout_pkt),\n          .S_VALID                   (arvalid_pkt),\n          .S_READY                   (arready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice_mm_pkt_fifo\n\n  \n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid\n    assign M_AXI_ARVALID      = rach_m_axi_arvalid;\n    assign rach_dout          = rach_dout_pkt;\n  end endgenerate // grach_m_axi_arvalid\n  \n  \n  generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd\n    assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;\n    assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;\n    assign accept_next_pkt  = rach_m_axi_arvalid && arready_pkt && arvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset) begin\n\trdch_commited_space <= 0;\n      end else begin\n\tif(rdch_rd_ok && !accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space-1;\n\tend else if(!rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);\n\tend else if(rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);\n\tend\n      end\n    end //Always end\n\n    always@(*) begin\n      rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));\n    end\n\n    assign arvalid_en = (rdch_free_space >= 0)?1:0;\n  end\n  endgenerate\n  \n  generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd\n    assign arvalid_en = 1;    \n  end\n  endgenerate\n\n  generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rdch_we    = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready  & M_AXI_RVALID : M_AXI_RVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign rdch_re    = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid  & S_AXI_RREADY : S_AXI_RREADY;\n    assign rdch_wr_en = (C_HAS_MASTER_CE == 1)  ? rdch_we & M_ACLK_EN : rdch_we;\n    assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 2  || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),\n        .C_USE_ECC                      (C_USE_ECC_RDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_RDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_rdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rdch_wr_en),\n        .RD_EN                    (rdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_R_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_R_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_R_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_R_INJECTSBITERR),\n  \n        .DIN                      (rdch_din),\n        .DOUT                     (rdch_dout),\n        .FULL                     (rdch_full),\n        .EMPTY                    (rdch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_R_PROG_FULL),\n        .PROG_EMPTY               (AXI_R_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_r_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_r_underflow_i),\n        .DATA_COUNT               (AXI_R_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_R_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_R_WR_DATA_COUNT),\n        .SBITERR                  (AXI_R_SBITERR),\n        .DBITERR                  (AXI_R_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rdch),\n        .rd_rst_busy              (rd_rst_busy_rdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rdch_s_axi_rvalid = ~rdch_empty;\n    assign rdch_m_axi_rready     = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;\n    assign S_AXI_RVALID      = rdch_s_axi_rvalid;\n    assign M_AXI_RREADY      = rdch_m_axi_rready;\n\n    assign AXI_R_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i  : 0;\n    assign AXI_R_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_r_overflow_i   : 0;\n\n  end endgenerate //axi_read_data_channel\n\n  // Register Slice for read Data Channel\n  generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RDCH)\n            )\n    rdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rdch_din),\n          .S_VALID                   (M_AXI_RVALID),\n          .S_READY                   (M_AXI_RREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rdch_dout),\n          .M_VALID                   (S_AXI_RVALID),\n          .M_READY                   (S_AXI_RREADY)\n          );\n  end endgenerate // grdch_reg_slice\n\n\n    assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;\n    assign axi_rd_overflow_i  = C_USE_COMMON_OVERFLOW  == 1 ? (axi_ar_overflow_i  || axi_r_overflow_i) : 0;\n\n\n  generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output\n    assign M_AXI_ARADDR    = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];    \n    assign M_AXI_ARLEN     = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];    \n    assign M_AXI_ARSIZE    = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];    \n    assign M_AXI_ARBURST   = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];    \n    assign M_AXI_ARLOCK    = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];    \n    assign M_AXI_ARCACHE   = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];    \n    assign M_AXI_ARPROT    = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];    \n    assign M_AXI_ARQOS     = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];    \n    assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET]    = S_AXI_ARADDR;\n    assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET]   = S_AXI_ARLEN;\n    assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET]   = S_AXI_ARSIZE;\n    assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;\n    assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;\n    assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;\n    assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;\n    assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET]   = S_AXI_ARQOS;\n  end endgenerate // axi_full_rach_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion\n    assign M_AXI_ARREGION  = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];    \n  end endgenerate // axi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion\n    assign M_AXI_ARREGION  = 0;    \n  end endgenerate // naxi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser\n    assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];    \n  end endgenerate // axi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser\n    assign M_AXI_ARUSER = 0;    \n  end endgenerate // naxi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid\n    assign M_AXI_ARID      = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];\n  end endgenerate // axi_arid\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid\n    assign M_AXI_ARID      = 0;\n  end endgenerate // naxi_arid\n\n  generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output\n    assign S_AXI_RDATA     = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];\n    assign S_AXI_RRESP     = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n    assign S_AXI_RLAST     = rdch_dout[0];\n    assign rdch_din[RID_OFFSET-1:RDATA_OFFSET]   = M_AXI_RDATA;\n    assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;\n    assign rdch_din[0] = M_AXI_RLAST;\n  end endgenerate // axi_full_rdch_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output\n    assign S_AXI_RUSER     = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];\n  end endgenerate // axi_full_ruser_output\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output\n    assign S_AXI_RUSER     =  0;\n  end endgenerate // axi_full_nruser_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid\n    assign S_AXI_RID       = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];\n  end endgenerate // axi_rid\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid\n    assign S_AXI_RID       = 0;\n  end endgenerate // naxi_rid\n\n  generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1\n    assign rach_din      = {S_AXI_ARADDR, S_AXI_ARPROT};\n    assign M_AXI_ARADDR  = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];\n    assign M_AXI_ARPROT  = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];\n  end endgenerate // axi_lite_rach_output\n\n  generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1\n    assign rdch_din      = {M_AXI_RDATA, M_AXI_RRESP};\n    assign S_AXI_RDATA   = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];\n    assign S_AXI_RRESP   = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n  end endgenerate // axi_lite_rdch_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1\n    assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET]     = S_AXI_ARUSER;\n  end endgenerate // grach_din1\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2\n    assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET]     = S_AXI_ARID;\n  end endgenerate // grach_din2\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin\n    assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1\n    assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET]     = M_AXI_RUSER;\n  end endgenerate // grdch_din1\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2\n    assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;\n  end endgenerate // grdch_din2\n\n  //end of axi_read_channel\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf\n    assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :\n                       (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :\n                       (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;\n  end endgenerate // gaxi_comm_uf\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of\n    assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :\n                      (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :\n                      (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;\n  end endgenerate // gaxi_comm_of\n  \n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  // Pass Through Logic or Wiring Logic\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  \n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Write Address Channel\n  generate if (C_WACH_TYPE == 2) begin : gwach_pass_through\n    assign M_AXI_AWID      = S_AXI_AWID;\n    assign M_AXI_AWADDR    = S_AXI_AWADDR;\n    assign M_AXI_AWLEN     = S_AXI_AWLEN;\n    assign M_AXI_AWSIZE    = S_AXI_AWSIZE;\n    assign M_AXI_AWBURST   = S_AXI_AWBURST;\n    assign M_AXI_AWLOCK    = S_AXI_AWLOCK;\n    assign M_AXI_AWCACHE   = S_AXI_AWCACHE;\n    assign M_AXI_AWPROT    = S_AXI_AWPROT;\n    assign M_AXI_AWQOS     = S_AXI_AWQOS;\n    assign M_AXI_AWREGION  = S_AXI_AWREGION;\n    assign M_AXI_AWUSER    = S_AXI_AWUSER;\n    assign S_AXI_AWREADY   = M_AXI_AWREADY;\n    assign M_AXI_AWVALID   = S_AXI_AWVALID;\n  end endgenerate // gwach_pass_through;\n\n  // Wiring logic for Write Data Channel\n  generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through\n    assign M_AXI_WID       = S_AXI_WID;\n    assign M_AXI_WDATA     = S_AXI_WDATA;\n    assign M_AXI_WSTRB     = S_AXI_WSTRB;\n    assign M_AXI_WLAST     = S_AXI_WLAST;\n    assign M_AXI_WUSER     = S_AXI_WUSER;\n    assign S_AXI_WREADY    = M_AXI_WREADY;\n    assign M_AXI_WVALID    = S_AXI_WVALID;\n  end endgenerate // gwdch_pass_through;\n\n  // Wiring logic for Write Response Channel\n  generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through\n    assign S_AXI_BID       = M_AXI_BID;\n    assign S_AXI_BRESP     = M_AXI_BRESP;\n    assign S_AXI_BUSER     = M_AXI_BUSER;\n    assign M_AXI_BREADY    = S_AXI_BREADY;\n    assign S_AXI_BVALID    = M_AXI_BVALID;\n  end endgenerate // gwrch_pass_through;\n\n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Read Address Channel\n  generate if (C_RACH_TYPE == 2) begin : grach_pass_through\n    assign M_AXI_ARID      = S_AXI_ARID;\n    assign M_AXI_ARADDR    = S_AXI_ARADDR;\n    assign M_AXI_ARLEN     = S_AXI_ARLEN;\n    assign M_AXI_ARSIZE    = S_AXI_ARSIZE;\n    assign M_AXI_ARBURST   = S_AXI_ARBURST;\n    assign M_AXI_ARLOCK    = S_AXI_ARLOCK;\n    assign M_AXI_ARCACHE   = S_AXI_ARCACHE;\n    assign M_AXI_ARPROT    = S_AXI_ARPROT;\n    assign M_AXI_ARQOS     = S_AXI_ARQOS;\n    assign M_AXI_ARREGION  = S_AXI_ARREGION;\n    assign M_AXI_ARUSER    = S_AXI_ARUSER;\n    assign S_AXI_ARREADY   = M_AXI_ARREADY;\n    assign M_AXI_ARVALID   = S_AXI_ARVALID;\n  end endgenerate // grach_pass_through;\n\n  // Wiring logic for Read Data Channel \n  generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through\n    assign S_AXI_RID      = M_AXI_RID;\n    assign S_AXI_RLAST    = M_AXI_RLAST;\n    assign S_AXI_RUSER    = M_AXI_RUSER;\n    assign S_AXI_RDATA    = M_AXI_RDATA;\n    assign S_AXI_RRESP    = M_AXI_RRESP;\n    assign S_AXI_RVALID   = M_AXI_RVALID;\n    assign M_AXI_RREADY   = S_AXI_RREADY;\n  end endgenerate // grdch_pass_through;\n\n  // Wiring logic for AXI Streaming\n  generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through\n    assign M_AXIS_TDATA   = S_AXIS_TDATA;\n    assign M_AXIS_TSTRB   = S_AXIS_TSTRB;\n    assign M_AXIS_TKEEP   = S_AXIS_TKEEP;\n    assign M_AXIS_TID     = S_AXIS_TID;\n    assign M_AXIS_TDEST   = S_AXIS_TDEST;\n    assign M_AXIS_TUSER   = S_AXIS_TUSER;\n    assign M_AXIS_TLAST   = S_AXIS_TLAST;\n    assign S_AXIS_TREADY  = M_AXIS_TREADY;\n    assign M_AXIS_TVALID  = S_AXIS_TVALID;\n  end endgenerate // gaxis_pass_through;\n\n\nendmodule //fifo_generator_v13_2_5\n\n\n\n/*******************************************************************************\n * Declaration of top-level module for Conventional FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_CONV_VER\n  #(\n    parameter  C_COMMON_CLOCK                 = 0,\n    parameter  C_INTERFACE_TYPE               = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_COUNT_TYPE                   = 0,\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DEFAULT_VALUE                = \"\",\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_ENABLE_RLOCS                 = 0,\n    parameter  C_FAMILY                       = \"virtex7\", //Not allowed in Verilog model\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_BACKUP                   = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_INT_CLK                  = 0,\n    parameter  C_HAS_MEMINIT_FILE             = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RD_RST                   = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_RST                   = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_INIT_WR_PNTR_VAL             = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_MIF_FILE_NAME                = \"\",\n    parameter  C_OPTIMIZATION_MODE            = 0,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PRIM_FIFO_TYPE               = \"\",\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_FREQ                      = 1,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_ECC                      = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_USE_FIFO16_FLAGS             = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_FREQ                      = 1,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_WR_RESPONSE_LATENCY          = 1,\n    parameter  C_MSGON_VAL                    = 1,\n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2,\n    parameter  C_AXI_TYPE                     = 0\n   )\n\n  (\n   input                               BACKUP,\n   input                               BACKUP_MARKER,\n   input                               CLK,\n   input                               RST,\n   input                               SRST,\n   input                               WR_CLK,\n   input                               WR_RST,\n   input                               RD_CLK,\n   input                               RD_RST,\n   input [C_DIN_WIDTH-1:0]             DIN,\n   input                               WR_EN,\n   input                               RD_EN,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_ASSERT,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_NEGATE,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_ASSERT,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_NEGATE,\n   input                               INT_CLK,\n   input                               INJECTDBITERR,\n   input                               INJECTSBITERR,\n  \n   output [C_DOUT_WIDTH-1:0]           DOUT,\n   output                              FULL,\n   output                              ALMOST_FULL,\n   output                              WR_ACK,\n   output                              OVERFLOW,\n   output                              EMPTY,\n   output                              ALMOST_EMPTY,\n   output                              VALID,\n   output                              UNDERFLOW,\n   output [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT,\n   output [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT,\n   output [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT,\n   output                              PROG_FULL,\n   output                              PROG_EMPTY,\n   output                              SBITERR,\n   output                              DBITERR,\n   output                              wr_rst_busy_o,\n   output                              wr_rst_busy,\n   output                              rd_rst_busy,\n   output                              wr_rst_i_out,\n   output                              rd_rst_i_out\n  );\n\n/*\n ******************************************************************************\n * Definition of Parameters\n ******************************************************************************\n *     C_COMMON_CLOCK                : Common Clock (1), Independent Clocks (0)\n *     C_COUNT_TYPE                  :    *not used\n *     C_DATA_COUNT_WIDTH            : Width of DATA_COUNT bus\n *     C_DEFAULT_VALUE               :    *not used\n *     C_DIN_WIDTH                   : Width of DIN bus\n *     C_DOUT_RST_VAL                : Reset value of DOUT\n *     C_DOUT_WIDTH                  : Width of DOUT bus\n *     C_ENABLE_RLOCS                :    *not used\n *     C_FAMILY                      : not used in bhv model\n *     C_FULL_FLAGS_RST_VAL          : Full flags rst val (0 or 1)\n *     C_HAS_ALMOST_EMPTY            : 1=Core has ALMOST_EMPTY flag\n *     C_HAS_ALMOST_FULL             : 1=Core has ALMOST_FULL flag\n *     C_HAS_BACKUP                  :    *not used\n *     C_HAS_DATA_COUNT              : 1=Core has DATA_COUNT bus\n *     C_HAS_INT_CLK                 : not used in bhv model\n *     C_HAS_MEMINIT_FILE            :    *not used\n *     C_HAS_OVERFLOW                : 1=Core has OVERFLOW flag\n *     C_HAS_RD_DATA_COUNT           : 1=Core has RD_DATA_COUNT bus\n *     C_HAS_RD_RST                  :    *not used\n *     C_HAS_RST                     : 1=Core has Async Rst\n *     C_HAS_SRST                    : 1=Core has Sync Rst\n *     C_HAS_UNDERFLOW               : 1=Core has UNDERFLOW flag\n *     C_HAS_VALID                   : 1=Core has VALID flag\n *     C_HAS_WR_ACK                  : 1=Core has WR_ACK flag\n *     C_HAS_WR_DATA_COUNT           : 1=Core has WR_DATA_COUNT bus\n *     C_HAS_WR_RST                  :    *not used\n *     C_IMPLEMENTATION_TYPE         : 0=Common-Clock Bram/Dram\n *                                     1=Common-Clock ShiftRam\n *                                     2=Indep. Clocks Bram/Dram\n *                                     3=Virtex-4 Built-in\n *                                     4=Virtex-5 Built-in\n *     C_INIT_WR_PNTR_VAL            :   *not used\n *     C_MEMORY_TYPE                 : 1=Block RAM\n *                                     2=Distributed RAM\n *                                     3=Shift RAM\n *                                     4=Built-in FIFO\n *     C_MIF_FILE_NAME               :   *not used\n *     C_OPTIMIZATION_MODE           :   *not used\n *     C_OVERFLOW_LOW                : 1=OVERFLOW active low\n *     C_PRELOAD_LATENCY             : Latency of read: 0, 1, 2\n *     C_PRELOAD_REGS                : 1=Use output registers\n *     C_PRIM_FIFO_TYPE              : not used in bhv model\n *     C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold\n *     C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold\n *     C_PROG_EMPTY_TYPE             : 0=No programmable empty\n *                                     1=Single prog empty thresh constant\n *                                     2=Multiple prog empty thresh constants\n *                                     3=Single prog empty thresh input\n *                                     4=Multiple prog empty thresh inputs\n *     C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold\n *     C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold\n *     C_PROG_FULL_TYPE              : 0=No prog full\n *                                     1=Single prog full thresh constant\n *                                     2=Multiple prog full thresh constants\n *                                     3=Single prog full thresh input\n *                                     4=Multiple prog full thresh inputs\n *     C_RD_DATA_COUNT_WIDTH         : Width of RD_DATA_COUNT bus\n *     C_RD_DEPTH                    : Depth of read interface (2^N)\n *     C_RD_FREQ                     : not used in bhv model\n *     C_RD_PNTR_WIDTH               : always log2(C_RD_DEPTH)\n *     C_UNDERFLOW_LOW               : 1=UNDERFLOW active low\n *     C_USE_DOUT_RST                : 1=Resets DOUT on RST\n *     C_USE_ECC                     : Used for error injection purpose\n *     C_USE_EMBEDDED_REG            : 1=Use BRAM embedded output register\n *     C_USE_FIFO16_FLAGS            : not used in bhv model\n *     C_USE_FWFT_DATA_COUNT         : 1=Use extra logic for FWFT data count\n *     C_VALID_LOW                   : 1=VALID active low\n *     C_WR_ACK_LOW                  : 1=WR_ACK active low\n *     C_WR_DATA_COUNT_WIDTH         : Width of WR_DATA_COUNT bus\n *     C_WR_DEPTH                    : Depth of write interface (2^N)\n *     C_WR_FREQ                     : not used in bhv model\n *     C_WR_PNTR_WIDTH               : always log2(C_WR_DEPTH)\n *     C_WR_RESPONSE_LATENCY         :    *not used\n *     C_MSGON_VAL                   :    *not used by bhv model\n *     C_ENABLE_RST_SYNC             : 0 = Use WR_RST & RD_RST\n *                                     1 = Use RST\n *     C_ERROR_INJECTION_TYPE        : 0 = No error injection\n *                                     1 = Single bit error injection only\n *                                     2 = Double bit error injection only\n *                                     3 = Single and double bit error injection\n ******************************************************************************\n * Definition of Ports\n ******************************************************************************\n *   BACKUP       : Not used\n *   BACKUP_MARKER: Not used\n *   CLK          : Clock\n *   DIN          : Input data bus\n *   PROG_EMPTY_THRESH       : Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag\n *   PROG_FULL_THRESH        : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag\n *   RD_CLK       : Read Domain Clock\n *   RD_EN        : Read enable\n *   RD_RST       : Read Reset\n *   RST          : Asynchronous Reset\n *   SRST         : Synchronous Reset\n *   WR_CLK       : Write Domain Clock\n *   WR_EN        : Write enable\n *   WR_RST       : Write Reset\n *   INT_CLK      : Internal Clock\n *   INJECTSBITERR: Inject Signle bit error\n *   INJECTDBITERR: Inject Double bit error\n *   ALMOST_EMPTY : One word remaining in FIFO\n *   ALMOST_FULL  : One empty space remaining in FIFO\n *   DATA_COUNT   : Number of data words in fifo( synchronous to CLK)\n *   DOUT         : Output data bus\n *   EMPTY        : Empty flag\n *   FULL         : Full flag\n *   OVERFLOW     : Last write rejected\n *   PROG_EMPTY   : Programmable Empty Flag\n *   PROG_FULL    : Programmable Full Flag\n *   RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)\n *   UNDERFLOW    : Last read rejected\n *   VALID        : Last read acknowledged, DOUT bus VALID\n *   WR_ACK       : Last write acknowledged\n *   WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)\n *   SBITERR      : Single Bit ECC Error Detected\n *   DBITERR      : Double Bit ECC Error Detected\n ******************************************************************************\n */\n\n  //----------------------------------------------------------------------------\n  //- Internal Signals for delayed input signals\n  //- All the input signals except Clock are delayed by 100 ps and then given to\n  //- the models.\n  //----------------------------------------------------------------------------\n \n  reg                         rst_delayed                       ;\n  reg                         empty_fb                       ;\n  reg                         srst_delayed                      ;\n  reg                         wr_rst_delayed                    ;\n  reg                         rd_rst_delayed                    ;\n  reg                         wr_en_delayed                     ;\n  reg                         rd_en_delayed                     ;\n  reg  [C_DIN_WIDTH-1:0]      din_delayed                       ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_delayed         ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_assert_delayed  ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_negate_delayed  ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_delayed          ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_assert_delayed   ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_negate_delayed   ;\n  reg                         injectdbiterr_delayed             ;\n  reg                         injectsbiterr_delayed             ;\n   wire                        empty_p0_out;\n\n  always @* rst_delayed                       <= #`TCQ RST                      ;\n  always @* empty_fb                       <= #`TCQ empty_p0_out                      ;\n  always @* srst_delayed                      <= #`TCQ SRST                     ; \n  always @* wr_rst_delayed                    <= #`TCQ WR_RST                   ; \n  always @* rd_rst_delayed                    <= #`TCQ RD_RST                   ; \n  always @* din_delayed                       <= #`TCQ DIN                      ; \n  always @* wr_en_delayed                     <= #`TCQ WR_EN                    ; \n  always @* rd_en_delayed                     <= #`TCQ RD_EN                    ; \n  always @* prog_empty_thresh_delayed         <= #`TCQ PROG_EMPTY_THRESH        ; \n  always @* prog_empty_thresh_assert_delayed  <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; \n  always @* prog_empty_thresh_negate_delayed  <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; \n  always @* prog_full_thresh_delayed          <= #`TCQ PROG_FULL_THRESH         ; \n  always @* prog_full_thresh_assert_delayed   <= #`TCQ PROG_FULL_THRESH_ASSERT  ; \n  always @* prog_full_thresh_negate_delayed   <= #`TCQ PROG_FULL_THRESH_NEGATE  ; \n  always @* injectdbiterr_delayed             <= #`TCQ INJECTDBITERR            ; \n  always @* injectsbiterr_delayed             <= #`TCQ INJECTSBITERR            ; \n\n  /*****************************************************************************\n   * Derived parameters\n   ****************************************************************************/\n  //There are 2 Verilog behavioral models\n  // 0 = Common-Clock FIFO/ShiftRam FIFO\n  // 1 = Independent Clocks FIFO\n  // 2 = Low Latency Synchronous FIFO\n  // 3 = Low Latency Asynchronous FIFO\n  localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :\n                              (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n\n  //Internal reset signals\n  reg                                rd_rst_asreg    = 1'b0;\n  reg                                rd_rst_asreg_d1 = 1'b0;\n  reg                                rd_rst_asreg_d2 = 1'b0;\n  reg                                rd_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_reg      = 1'b0;\n  reg                                rd_rst_comb     = 1'b1;\n  reg                                rd_rst_comb_d1  = 1'b0;\n  reg                                wr_rst_d0       = 1'b0;\n  reg                                wr_rst_d1       = 1'b0;\n  reg                                wr_rst_d2       = 1'b0;\n  reg                                rd_rst_d0       = 1'b0;\n  reg                                rd_rst_d1       = 1'b0;\n  reg                                rd_rst_d2       = 1'b0;\n  reg                                rd_rst_d3       = 1'b0;\n  reg                                wrrst_done      = 1'b0;\n  reg                                rdrst_done      = 1'b0;\n  reg                                wr_rst_asreg    = 1'b0;\n  reg                                wr_rst_asreg_d1 = 1'b0;\n  reg                                wr_rst_asreg_d2 = 1'b0;\n  reg                                wr_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_wr_d0    = 1'b0;\n  reg                                rd_rst_wr_d1    = 1'b0;\n  reg                                rd_rst_wr_d2    = 1'b0;\n  reg                                wr_rst_reg      = 1'b0;\n  reg                                rst_active_i    = 1'b1;\n  reg                                rst_delayed_d1  = 1'b1;\n  reg                                rst_delayed_d2  = 1'b1;\n  reg                                wr_rst_comb     = 1'b1;\n  reg                                wr_rst_comb_d1  = 1'b0;\n  wire                               wr_rst_i;\n  wire                               rd_rst_i;\n  wire                               rst_i;\n\n  //Internal reset signals\n  reg                                rst_asreg     = 1'b0;\n  reg                                srst_asreg    = 1'b0;\n  reg                                rst_asreg_d1  = 1'b0;\n  reg                                rst_asreg_d2  = 1'b0;\n  reg                                srst_asreg_d1 = 1'b0;\n  reg                                srst_asreg_d2 = 1'b0;\n  reg                                rst_reg       = 1'b0;\n  reg                                srst_reg      = 1'b0;\n  reg                                rst_comb      = 1'b1;\n  reg                                rst_comb_d1   = 1'b0;\n  wire                               srst_comb;\n  reg                                rst_full_gen_i = 0;\n  reg                                rst_full_ff_i = 0;\n  reg  [2:0]                         sckt_ff0_bsy_o_i = {3{1'b0}};\n                                     \n  wire                               RD_CLK_P0_IN;\n  wire                               RST_P0_IN;\n  wire                               RD_EN_FIFO_IN;\n  wire                               RD_EN_P0_IN;\n\n  wire                               ALMOST_EMPTY_FIFO_OUT;\n  wire                               ALMOST_FULL_FIFO_OUT;\n  wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT_FIFO_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DOUT_FIFO_OUT;\n  wire                               EMPTY_FIFO_OUT;\n  wire                               fifo_empty_fb;\n  wire                               FULL_FIFO_OUT;\n  wire                               OVERFLOW_FIFO_OUT;\n  wire                               PROG_EMPTY_FIFO_OUT;\n  wire                               PROG_FULL_FIFO_OUT;\n  wire                               VALID_FIFO_OUT;\n  wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT_FIFO_OUT;\n  wire                               UNDERFLOW_FIFO_OUT;\n  wire                               WR_ACK_FIFO_OUT;\n  wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT_FIFO_OUT;\n\n\n  //***************************************************************************\n  // Internal Signals\n  //   The core uses either the internal_ wires or the preload0_ wires depending\n  //     on whether the core uses Preload0 or not.\n  //   When using preload0, the internal signals connect the internal core to\n  //     the preload logic, and the external core's interfaces are tied to the\n  //     preload0 signals from the preload logic.\n  //***************************************************************************\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_OUT;\n  wire                               VALID_P0_OUT;\n  wire                               EMPTY_P0_OUT;\n  wire                               ALMOSTEMPTY_P0_OUT;\n  reg                                EMPTY_P0_OUT_Q;\n  reg                                ALMOSTEMPTY_P0_OUT_Q;\n  wire                               UNDERFLOW_P0_OUT;\n  wire                               RDEN_P0_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_IN;\n  wire                               EMPTY_P0_IN;\n  reg  [31:0]                        DATA_COUNT_FWFT;\n  reg                                SS_FWFT_WR  ;\n  reg                                SS_FWFT_RD ;\n\n  wire                               sbiterr_fifo_out;\n  wire                               dbiterr_fifo_out;\n  wire                               inject_sbit_err;\n  wire                               inject_dbit_err;\n  wire                               sckt_wr_rst_i;\n  wire                               sckt_rd_rst_i;\n  reg                                sckt_wr_rst_i_q = 1'b0;\n \n  wire                               w_fab_read_data_valid_i;\n  wire                               w_read_data_valid_i;\n  wire                               w_ram_valid_i;\n  // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.\n  assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectsbiterr_delayed : 0;\n  assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectdbiterr_delayed : 0;\n                           \n  assign wr_rst_i_out = wr_rst_i;\n  assign rd_rst_i_out = rd_rst_i;\n  assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];\n  generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o\n    wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;\n    always @ (posedge clk_i)\n      sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; \n  end endgenerate \n// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL\n// parameter (1=Independent Clocks, 0=Common Clock)\n\n  localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;\ngenerate\ncase (C_VERILOG_IMPL)\n0 : begin : block1_ss\n  //Common Clock Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_ss\n  #(\n    .C_FAMILY                            (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                  (C_DATA_COUNT_WIDTH),            \n    .C_DIN_WIDTH                         (C_DIN_WIDTH),                   \n    .C_DOUT_RST_VAL                      (C_DOUT_RST_VAL),                \n    .C_DOUT_WIDTH                        (C_DOUT_WIDTH),                  \n    .C_FULL_FLAGS_RST_VAL                (FULL_FLAGS_RST_VAL),            \n    .C_HAS_ALMOST_EMPTY                  (C_HAS_ALMOST_EMPTY),            \n    .C_HAS_ALMOST_FULL                   ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),             \n    .C_HAS_DATA_COUNT                    (C_HAS_DATA_COUNT),              \n    .C_HAS_OVERFLOW                      (C_HAS_OVERFLOW),                \n    .C_HAS_RD_DATA_COUNT                 (C_HAS_RD_DATA_COUNT),           \n    .C_HAS_RST                           (C_EN_SAFETY_CKT?0:C_HAS_RST),                     \n    .C_HAS_SRST                          (C_EN_SAFETY_CKT?1:C_HAS_SRST),                    \n    .C_HAS_UNDERFLOW                     (C_HAS_UNDERFLOW),               \n    .C_HAS_VALID                         (C_HAS_VALID),                   \n    .C_HAS_WR_ACK                        (C_HAS_WR_ACK),                  \n    .C_HAS_WR_DATA_COUNT                 (C_HAS_WR_DATA_COUNT),           \n    .C_IMPLEMENTATION_TYPE               (C_IMPLEMENTATION_TYPE),         \n    .C_MEMORY_TYPE                       (C_MEMORY_TYPE),                 \n    .C_OVERFLOW_LOW                      (C_OVERFLOW_LOW),                \n    .C_PRELOAD_LATENCY                   (C_PRELOAD_LATENCY),             \n    .C_PRELOAD_REGS                      (C_PRELOAD_REGS),                \n    .C_PROG_EMPTY_THRESH_ASSERT_VAL      (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL      (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                   (C_PROG_EMPTY_TYPE),             \n    .C_PROG_FULL_THRESH_ASSERT_VAL       (C_PROG_FULL_THRESH_ASSERT_VAL), \n    .C_PROG_FULL_THRESH_NEGATE_VAL       (C_PROG_FULL_THRESH_NEGATE_VAL), \n    .C_PROG_FULL_TYPE                    (C_PROG_FULL_TYPE),              \n    .C_RD_DATA_COUNT_WIDTH               (C_RD_DATA_COUNT_WIDTH),         \n    .C_RD_DEPTH                          (C_RD_DEPTH),                    \n    .C_RD_PNTR_WIDTH                     (C_RD_PNTR_WIDTH),               \n    .C_UNDERFLOW_LOW                     (C_UNDERFLOW_LOW),               \n    .C_USE_DOUT_RST                      (C_USE_DOUT_RST),                \n    .C_USE_EMBEDDED_REG                  (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                     (C_EN_SAFETY_CKT),            \n    .C_USE_FWFT_DATA_COUNT               (C_USE_FWFT_DATA_COUNT),         \n    .C_VALID_LOW                         (C_VALID_LOW),                   \n    .C_WR_ACK_LOW                        (C_WR_ACK_LOW),                  \n    .C_WR_DATA_COUNT_WIDTH               (C_WR_DATA_COUNT_WIDTH),         \n    .C_WR_DEPTH                          (C_WR_DEPTH),                    \n    .C_WR_PNTR_WIDTH                     (C_WR_PNTR_WIDTH),               \n    .C_USE_ECC                           (C_USE_ECC),                     \n    .C_ENABLE_RST_SYNC                   (C_ENABLE_RST_SYNC),             \n    .C_ERROR_INJECTION_TYPE              (C_ERROR_INJECTION_TYPE),\n    .C_FIFO_TYPE                         (C_FIFO_TYPE)                     \n  )\n  gen_ss\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .CLK                      (CLK),\n    .RST                      (C_EN_SAFETY_CKT?1'b0:rst_i),\n    .SRST                     (C_EN_SAFETY_CKT?sckt_wr_rst_i:srst_delayed),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .USER_EMPTY_FB            (empty_fb),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .DATA_COUNT               (DATA_COUNT_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .WR_RST_BUSY              (wr_rst_busy),\n    .RD_RST_BUSY              (rd_rst_busy),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n1 : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT), \n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .fab_read_data_valid_i    (w_fab_read_data_valid_i),\n    .read_data_valid_i        (w_read_data_valid_i),\n    .ram_valid_i              (w_ram_valid_i),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\n2 : begin : ll_afifo_inst\n  fifo_generator_v13_2_5_beh_ver_ll_afifo\n  #(\n    .C_DIN_WIDTH                    (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                 (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                   (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_RD_DATA_COUNT            (C_HAS_RD_DATA_COUNT),\n    .C_HAS_WR_DATA_COUNT            (C_HAS_WR_DATA_COUNT),\n    .C_RD_DEPTH                     (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                (C_RD_PNTR_WIDTH),\n    .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n    .C_WR_DATA_COUNT_WIDTH          (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                     (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                (C_WR_PNTR_WIDTH),\n    .C_FIFO_TYPE                    (C_FIFO_TYPE)\n   )\n  gen_ll_afifo\n  (\n    .DIN                        (din_delayed),\n    .RD_CLK                     (RD_CLK),\n    .RD_EN                      (rd_en_delayed),\n    .WR_RST                     (wr_rst_i),\n    .RD_RST                     (rd_rst_i),\n    .WR_CLK                     (WR_CLK),\n    .WR_EN                      (wr_en_delayed),\n    .DOUT                       (DOUT),\n    .EMPTY                      (EMPTY),\n    .FULL                       (FULL)\n  );\nend\ndefault : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT),\n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\nendcase\nendgenerate\n\n\n   //**************************************************************************\n   // Connect Internal Signals\n   //   (Signals labeled internal_*)\n   //  In the normal case, these signals tie directly to the FIFO's inputs and\n   //    outputs.\n   //  In the case of Preload Latency 0 or 1, there are intermediate\n   //    signals between the internal FIFO and the preload logic.\n   //**************************************************************************\n   \n   \n   //***********************************************\n   // If First-Word Fall-Through, instantiate\n   // the preload0 (FWFT) module\n   //***********************************************\n   wire                        rd_en_to_fwft_fifo;\n   wire                        sbiterr_fwft;\n   wire                        dbiterr_fwft;\n   wire [C_DOUT_WIDTH-1:0]     dout_fwft;\n   wire                        empty_fwft;\n   wire                        rd_en_fifo_in;\n   wire                        stage2_reg_en_i;\n   wire [1:0]                  valid_stages_i;\n   wire                        rst_fwft;\n   //wire                        empty_p0_out;\n   reg  [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n   localparam IS_PKT_FIFO      = (C_FIFO_TYPE == 1) ? 1 : 0;\n   localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;\n   assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2_fwft\n\n\n         fifo_generator_v13_2_5_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_EMBEDDED_REG  (C_USE_EMBEDDED_REG),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (C_FIFO_TYPE)\n             )\n             fgpl0\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (RST_P0_IN),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (RD_EN_P0_IN),\n                .FIFOEMPTY        (EMPTY_P0_IN),\n                .FIFODATA         (DATA_P0_IN),\n                .FIFOSBITERR      (sbiterr_fifo_out),\n                .FIFODBITERR      (dbiterr_fifo_out),\n                // Output\n                .USERDATA         (dout_fwft),\n                .USERVALID        (VALID_P0_OUT),\n                .USEREMPTY        (empty_fwft),\n                .USERALMOSTEMPTY  (ALMOSTEMPTY_P0_OUT),\n                .USERUNDERFLOW    (UNDERFLOW_P0_OUT),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_fifo_in),\n                .USERSBITERR      (sbiterr_fwft),\n                .USERDBITERR      (dbiterr_fwft),\n                .STAGE2_REG_EN    (stage2_reg_en_i),\n                .fab_read_data_valid_i_o    (w_fab_read_data_valid_i),\n                .read_data_valid_i_o        (w_read_data_valid_i),\n                .ram_valid_i_o              (w_ram_valid_i),\n                .VALID_STAGES                (valid_stages_i)\n                );\n\n         \n         //***********************************************\n         // Connect inputs to preload (FWFT) module\n         //***********************************************\n         //Connect the RD_CLK of the Preload (FWFT) module to CLK if we \n         // have a common-clock FIFO, or RD_CLK if we have an \n         // independent clock FIFO\n         assign RD_CLK_P0_IN       = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);\n         assign RST_P0_IN          = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;\n         assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n         assign EMPTY_P0_IN        = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;\n         assign DATA_P0_IN         = DOUT_FIFO_OUT;\n         \n         //***********************************************\n         // Connect outputs from preload (FWFT) module\n         //***********************************************\n         assign VALID              = VALID_P0_OUT ;\n         assign ALMOST_EMPTY       = ALMOSTEMPTY_P0_OUT;\n         assign UNDERFLOW          = UNDERFLOW_P0_OUT ;\n         \n         assign RD_EN_FIFO_IN      = rd_en_fifo_in;\n         \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:\n           (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : \n           DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];  \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               EMPTY_P0_OUT_Q       <= 1;\n               ALMOSTEMPTY_P0_OUT_Q <= 1;\n            end else begin\n               EMPTY_P0_OUT_Q       <= #`TCQ empty_p0_out;\n//               EMPTY_P0_OUT_Q       <= #`TCQ EMPTY_FIFO_OUT;\n               ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;\n            end\n         end //always\n         \n         \n         //***********************************************\n         // logic for common-clock data count when FWFT is selected\n         //***********************************************\n         initial begin\n            SS_FWFT_RD = 1'b0;\n            DATA_COUNT_FWFT = 0 ;\n            SS_FWFT_WR   = 1'b0 ;\n         end //initial\n         \n         \n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter. SS_FWFT_WR and SS_FWFT_RD\n         // are the up/down enables for the counter.\n         //***********************************************\n         always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin\n            if (C_VALID_LOW == 1) begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;\n            end else begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;\n            end\n            SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT))  ;\n         end \n\n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter for FWFT. This always block \n         // calculates the counter.\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               DATA_COUNT_FWFT      <= 0;\n            end else begin\n               //if (srst_delayed && (C_HAS_SRST == 1) ) begin\n               if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin\n                  DATA_COUNT_FWFT      <= #`TCQ 0;\n               end else begin\n                  case ( {SS_FWFT_WR, SS_FWFT_RD})\n                    2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                    2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;\n                    2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;\n                    2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                  endcase  \n               end //if SRST\n            end //IF RST\n         end //always\n\n      end endgenerate // : block2\n\n    // AXI Streaming Packet FIFO\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_plus1 = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_reg   = 0;\n    reg                         partial_packet     = 0;\n    reg                         stage1_eop_d1      = 0;\n    reg                         rd_en_fifo_in_d1   = 0;\n    reg                         eop_at_stage2      = 0;\n    reg                         ram_pkt_empty      = 0;\n    reg                         ram_pkt_empty_d1   = 0;\n\n    wire [C_DOUT_WIDTH-1:0]     dout_p0_out;\n    wire                        packet_empty_wr;\n    wire                        wr_rst_fwft_pkt_fifo;\n    wire                        dummy_wr_eop;\n    wire                        ram_wr_en_pkt_fifo;\n    wire                        wr_eop;\n    wire                        ram_rd_en_compare;\n    wire                        stage1_eop;\n    wire                        pkt_ready_to_read;\n    wire                        rd_en_2_stage2;\n\n    // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)\n    // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP\n    // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of\n    // write packet count\n    generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop\n       always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n          if (wr_rst_fwft_pkt_fifo)\n             partial_packet   <= 1'b0;\n          else begin\n             if (srst_delayed | wr_rst_busy | rd_rst_busy)\n                partial_packet <= #`TCQ 1'b0;\n             else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))\n                partial_packet <= #`TCQ 1'b1;\n             else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)\n                partial_packet <= #`TCQ 1'b0;\n          end\n        end\n    end endgenerate // gdummy_wr_eop\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin : gpkt_fifo_fwft\n      assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;\n      assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);\n      assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];\n  \n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft) begin\n          stage1_eop_d1    <= 1'b0;\n          rd_en_fifo_in_d1 <= 1'b0;\n        end else begin\n          if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            stage1_eop_d1    <= #`TCQ 1'b0;\n            rd_en_fifo_in_d1 <= #`TCQ 1'b0;\n          end else begin\n            stage1_eop_d1    <= #`TCQ stage1_eop;\n            rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;\n          end\n        end\n      end\n      assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;\n      assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);\n      assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);\n      assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;\n\n\n         fifo_generator_v13_2_5_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (2) // Enable low latency fwft logic\n             )\n         pkt_fifo_fwft\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (rst_fwft),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (rd_en_delayed),\n                .FIFOEMPTY        (pkt_ready_to_read),\n                .FIFODATA         (dout_fwft),\n                .FIFOSBITERR      (sbiterr_fwft),\n                .FIFODBITERR      (dbiterr_fwft),\n                // Output\n                .USERDATA         (dout_p0_out),\n                .USERVALID        (),\n                .USEREMPTY        (empty_p0_out),\n                .USERALMOSTEMPTY  (),\n                .USERUNDERFLOW    (),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_2_stage2),\n                .USERSBITERR      (SBITERR),\n                .USERDBITERR      (DBITERR),\n                .STAGE2_REG_EN    (),\n                .VALID_STAGES     ()\n                );\n\n      assign pkt_ready_to_read  = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));\n      assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft)\n          eop_at_stage2 <= 1'b0;\n        else if (stage2_reg_en_i)\n          eop_at_stage2 <= #`TCQ stage1_eop;\n      end\n\n      //---------------------------------------------------------------------------\n      // Write and Read Packet Count\n      //---------------------------------------------------------------------------\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count  <= 0;\n         else if (srst_delayed  | wr_rst_busy | rd_rst_busy)\n            wr_pkt_count  <= #`TCQ 0;\n         else if (wr_eop)\n            wr_pkt_count  <= #`TCQ wr_pkt_count + 1;\n      end\n    \n    end endgenerate //: gpkt_fifo_fwft\n\n    assign DOUT               = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;\n    assign EMPTY              = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            rd_pkt_count       <= 0;\n            rd_pkt_count_plus1 <= 1;\n         end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            rd_pkt_count       <= #`TCQ 0;\n            rd_pkt_count_plus1 <= #`TCQ 1;\n         end else if (stage2_reg_en_i && stage1_eop) begin\n            rd_pkt_count       <= #`TCQ rd_pkt_count + 1;\n            rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;\n         end\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (SRST | wr_rst_busy | rd_rst_busy) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n    end endgenerate //grss_pkt_cnt\n    \n    localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;\n    reg  [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_b2g = 0;\n    wire [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_rd;\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt\n      // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count_b2g  <= 0;\n         else\n            wr_pkt_count_b2g  <= #`TCQ wr_pkt_count;\n      end\n\n      // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            wr_pkt_count_q       <= 0;\n         else\n            wr_pkt_count_q       <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};\n      end\n\n      always @* begin\n        if (stage1_eop)\n           rd_pkt_count    <= rd_pkt_count_reg + 1;\n        else\n           rd_pkt_count    <= rd_pkt_count_reg;\n      end\n\n      assign wr_pkt_count_rd    = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            rd_pkt_count_reg       <= 0;\n         else if (rd_en_fifo_in)\n            rd_pkt_count_reg       <= #`TCQ rd_pkt_count;\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (rd_pkt_count != wr_pkt_count_rd) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n\n      // Synchronize the empty in write domain\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            pkt_empty_sync  <= 'b1;\n         else\n            pkt_empty_sync  <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};\n      end\n\n    end endgenerate //gras_pkt_cnt\n\n   generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO\n\n     //***********************************************\n     // If NOT First-Word Fall-Through, wire the outputs\n     // of the internal _ss or _as FIFO directly to the\n     // output, and do not instantiate the preload0\n     // module.\n     //***********************************************\n\n     assign RD_CLK_P0_IN       = 0;\n     assign RST_P0_IN          = 0;\n     assign RD_EN_P0_IN        = 0;\n\n     assign RD_EN_FIFO_IN      = rd_en_delayed;\n\n     assign DOUT               = DOUT_FIFO_OUT;\n     assign DATA_P0_IN         = 0;\n     assign VALID              = VALID_FIFO_OUT;\n     assign EMPTY              = EMPTY_FIFO_OUT;\n     assign ALMOST_EMPTY       = ALMOST_EMPTY_FIFO_OUT;\n     assign EMPTY_P0_IN        = 0;\n     assign UNDERFLOW          = UNDERFLOW_FIFO_OUT;\n     assign DATA_COUNT         = DATA_COUNT_FIFO_OUT;\n     assign SBITERR            = sbiterr_fifo_out;\n     assign DBITERR            = dbiterr_fifo_out;\n\n   end endgenerate // STD_FIFO\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO\n     assign empty_p0_out       = empty_fwft;\n     assign SBITERR            = sbiterr_fwft;\n     assign DBITERR            = dbiterr_fwft;\n     assign DOUT               = dout_fwft;\n     assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n\n   end endgenerate // NO_PKT_FIFO\n\n   //***********************************************\n   // Connect user flags to internal signals\n   //***********************************************\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3\n      if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);\n      end //block_ic\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3\n   endgenerate\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30\n       if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30\n   endgenerate\n\n\n    \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both\n       if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30_both\n   endgenerate\n\n generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both\n      if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));\n      end //block_ic_both\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3_both\n   endgenerate\n\n\n   //If we are not using extra logic for the FWFT data count,\n   //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the\n   //internal FIFO instance  \n   generate\n      if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n   //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal\n   //FIFO instance\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1) begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n      else begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n\n   //Connect other flags to the internal FIFO instance\n   assign       FULL        = FULL_FIFO_OUT;\n   assign       ALMOST_FULL = ALMOST_FULL_FIFO_OUT;\n   assign       WR_ACK      = WR_ACK_FIFO_OUT;\n   assign       OVERFLOW    = OVERFLOW_FIFO_OUT;\n   assign       PROG_FULL   = PROG_FULL_FIFO_OUT;\n   assign       PROG_EMPTY  = PROG_EMPTY_FIFO_OUT;\n\n\n  /**************************************************************************\n  * find_log2\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n   // if an asynchronous FIFO has been selected, display a message that the FIFO\n   //   will not be cycle-accurate in simulation\n   initial begin\n      if (C_IMPLEMENTATION_TYPE == 2) begin\n         $display(\"WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.\");\n      end else if (C_MEMORY_TYPE == 4) begin\n         $display(\"FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.\");\n         $finish;\n      end\n\n      if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin\n         $display(\"FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.\");\n         $finish;\n      end\n\n      if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin\n         $display(\"FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.\");\n         $finish;\n      end\n\n      if (C_USE_ECC == 1) begin\n         if (C_DIN_WIDTH != C_DOUT_WIDTH) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.\");\n            $finish;\n         end\n         if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.\");\n            $finish;\n         end\n      end\n\n   end //initial\n\n  /**************************************************************************\n  * Internal reset logic\n  **************************************************************************/\n  assign wr_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg|sckt_wr_rst_i : 0;\n  assign rd_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg|sckt_rd_rst_i : 0;\n  assign rst_i            = C_HAS_RST ? rst_reg|sckt_wr_rst_i : 0;\n\n  wire rst_2_sync;\n  wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;\n\n  localparam RST_SYNC_STAGES = C_EN_SAFETY_CKT == 0 ? C_COMMON_CLOCK ? C_SYNCHRONIZER_STAGE : C_SYNCHRONIZER_STAGE+2 : 5;\n  localparam RST_BUSY_LEN    = 4;\n  reg  wr_rst_busy_i = 0;\n  reg  rd_rst_busy_i = 0;\n  generate\n      if (C_ENABLE_RST_SYNC == 0 || (C_HAS_RST == 0 && C_HAS_SRST == 0)) begin : gnrst_sync\n        always @* begin\n          wr_rst_reg <= wr_rst_delayed;\n          rd_rst_reg <= rd_rst_delayed;\n          rst_reg    <= 1'b0;\n          srst_reg    <= 1'b0;\n        end\n        assign rst_2_sync = wr_rst_delayed;\n        assign wr_rst_busy = 1'b0;\n        assign wr_rst_busy_o = 1'b0;\n        assign rd_rst_busy = 1'b0;\n        assign sckt_wr_rst_i = 1'b0;\n        assign sckt_rd_rst_i = 1'b0;\n      end // gnrst_sync\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 0) begin : g7s_ic_rst_nsckt\n        reg [1:0]                 arst_sync_wr  = 2'b11;\n        reg [1:0]                 arst_sync_rd  = 2'b11;\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge WR_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge RD_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_rd    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_rd    <= #`TCQ {arst_sync_rd[0], rst_delayed};\n        end\n        always @(posedge WR_CLK) begin\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n\tend\n        always @(posedge WR_CLK or posedge arst_sync_wr[1]) begin\n\t  if (arst_sync_wr[1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n            rd_rst_wr_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            rd_rst_wr_ext  <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t    if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t      sckt_wr_rst_ic <= #`TCQ 1'b0;\n            else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t      wr_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n        always @(posedge RD_CLK) begin\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], sckt_wr_rst_ic};\n\tend\n        always @(posedge RD_CLK or posedge arst_sync_rd[1]) begin\n\t  if (arst_sync_rd[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n            wr_rst_rd_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            wr_rst_rd_ext  <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t    if (wr_rst_rd_ext[1]) begin\n\t      sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t      rd_rst_busy_i  <= #`TCQ 1'b0;\n\t    end\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic|arst_sync_wr[1];\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic|arst_sync_rd[1];\n      end // g7s_ic_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 1) begin : g7s_ic_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] arst_sync_rd  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        always @(posedge WR_CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n          rd_rst_wr_ext    <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_wr[RST_SYNC_STAGES-1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n          end else if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t    sckt_wr_rst_ic <= #`TCQ 1'b0;\n          else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t    wr_rst_busy_i  <= #`TCQ 1'b0;\n\tend\n        always @(posedge RD_CLK) begin\n\t  arst_sync_rd     <= #`TCQ {arst_sync_rd[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n          wr_rst_rd_ext    <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_rd[RST_SYNC_STAGES-1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n\t  end else if (wr_rst_rd_ext[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t    rd_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic;\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic;\n      end // g7s_ic_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 0) begin : g7s_cc_rst_nsckt\n        reg [1:0]              arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge CLK) begin\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0] | arst_sync_wr[1]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc | arst_sync_wr[1];\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 1) begin : g7s_cc_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n\n        always @(posedge CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc;\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst\n        assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;\n        assign rd_rst_busy = rst_reg;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = rst_reg;\n        always @* rst_full_ff_i  <= 1'b0;\n        always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;\n\n        always @(posedge CLK) begin\n          rst_delayed_d1 <= #`TCQ srst_delayed;\n          rst_delayed_d2 <= #`TCQ rst_delayed_d1;\n          if (rst_reg || rst_delayed_d2) begin\n            rst_active_i <= #`TCQ 1'b1;\n          end else begin\n            rst_active_i <= #`TCQ rst_reg;\n          end    \n        end   \n        always @(posedge CLK) begin\n          if (~rst_reg && srst_delayed) begin\n             rst_reg <= #`TCQ 1'b1;\n           end else if (rst_reg) begin\n             rst_reg <= #`TCQ 1'b0;\n           end else begin\n             rst_reg <= #`TCQ rst_reg;\n           end    \n        end   \n      end // g8s_cc_rst\n      else if (IS_8SERIES != 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_srst\n        assign wr_rst_busy = srst_delayed;\n        assign rd_rst_busy = srst_delayed;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = srst_delayed;\n        always @* rst_full_ff_i  <= 1'b0;\n      end // g7s_cc_srst\n  endgenerate \n\n  reg rst_d1 = 1'b0;\n  reg rst_d2 = 1'b0;\n  reg rst_d3 = 1'b0;\n  reg rst_d4 = 1'b0;\n  generate\n    if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1\n    // RST_FULL_GEN replaces the reset falling edge detection used to de-assert\n    // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.\n\n    // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &\n    // PROG_FULL\n\n      always @ (posedge rst_2_sync or posedge clk_2_sync) begin\n        if (rst_2_sync && C_EN_SAFETY_CKT == 0) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          rst_d3         <= 1'b1;\n          rst_d4         <= 1'b0;\n        end else begin\n          if (srst_delayed) begin\n            rst_d1         <= #`TCQ 1'b1;\n            rst_d2         <= #`TCQ 1'b1;\n            rst_d3         <= #`TCQ 1'b1;\n            rst_d4         <= #`TCQ 1'b0;\n          end else begin\n            rst_d1         <= #`TCQ wr_rst_busy;//1'b0;\n            rst_d2         <= #`TCQ rst_d1;\n            rst_d3         <= #`TCQ rst_d2 | sckt_wr_rst_i;\n            rst_d4         <= #`TCQ rst_d3;\n          end\n        end\n      end\n\n      always @* rst_full_ff_i  <= C_HAS_SRST ? 1'b0 : rst_d2 | sckt_wr_rst_i;\n      always @* rst_full_gen_i <= C_HAS_SRST ? rst_d4 : rst_d3;\n\n    end else if (C_EN_SAFETY_CKT == 1 && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full_sckt\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end\n  endgenerate // grstd1\n\nendmodule //fifo_generator_v13_2_5_CONV_VER\n\n\nmodule fifo_generator_v13_2_5_sync_stage\n  #(\n    parameter  C_WIDTH          = 10\n   )\n   (\n    input                     RST,\n    input                     CLK,\n    input       [C_WIDTH-1:0] DIN,\n    output reg  [C_WIDTH-1:0] DOUT = 0\n   );\n   always @ (posedge RST or posedge CLK) begin\n     if (RST)\n       DOUT <= 0;\n     else\n       DOUT <= #`TCQ DIN;\n   end\nendmodule // fifo_generator_v13_2_5_sync_stage\n\n/*******************************************************************************\n * Declaration of Independent-Clocks FIFO Module\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_as\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2 \n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input                                         SAFETY_CKT_WR_RST,\n   input                                         SAFETY_CKT_RD_RST,\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_ASSERT,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_NEGATE,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_ASSERT,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_NEGATE,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         RD_EN_USER,\n   input                                         RST,\n   input                                         RST_FULL_GEN,\n   input                                         RST_FULL_FF,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   input                                         INJECTDBITERR,\n   input                                         INJECTSBITERR,\n   input                                         USER_EMPTY_FB,\n   input                                         fab_read_data_valid_i,\n   input                                         read_data_valid_i,\n   input                                         ram_valid_i,\n   output reg                                    ALMOST_EMPTY = 1'b1,\n   output reg                                    ALMOST_FULL = C_FULL_FLAGS_RST_VAL,\n   output      [C_DOUT_WIDTH-1:0]                DOUT,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    EMPTY_FB = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL,\n   output                                        OVERFLOW,\n   output                                        PROG_EMPTY,\n   output                                        PROG_FULL,\n   output                                        VALID,\n   output      [C_RD_DATA_COUNT_WIDTH-1:0]       RD_DATA_COUNT,\n   output                                        UNDERFLOW,\n   output                                        WR_ACK,\n   output      [C_WR_DATA_COUNT_WIDTH-1:0]       WR_DATA_COUNT,\n   output                                        SBITERR,\n   output                                        DBITERR\n  );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   \n  \n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   \n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;\n   // Array that holds the error injection type (single/double bit error) on \n   // a specific write operation, which is returned on read to corrupt the\n   // output data.\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   //The amount of data stored in the FIFO at any time is given\n   // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK\n   // domain.\n   //num_wr_bits is calculated by considering the total words in the FIFO,\n   // and the state of the read pointer (which may not have yet crossed clock\n   // domains.)\n   //num_rd_bits is calculated by considering the total words in the FIFO,\n   // and the state of the write pointer (which may not have yet crossed clock\n   // domains.)\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   wire                        wr_rst_i = WR_RST;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n   wire                        rd_rst_i = RD_RST;\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n\n\n\n   // Delayed ram_rd_en is needed only for STD Embedded register option\n   generate\n     if (C_PRELOAD_LATENCY == 2) begin : grd_d\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n       end\n     end\n   endgenerate\n   \n    generate\n     if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n           fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n       end\n     end\n   endgenerate\n\n  \n\n   // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;\n     end else begin : rdl // Read depth lesser than or equal to write depth\n       assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n     end\n   endgenerate\n\n   // Generate Empty and Almost Empty\n  // ram_rd_en used to determine EMPTY should depend on the EMPTY.\n   assign ram_rd_en        = RD_EN & !EMPTY;\n   assign empty_int        = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));\n   assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));\n\n   // Register Empty and Almost Empty\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else begin\n         rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};\n\n         if (empty_int)\n           EMPTY           <= #`TCQ 1'b1;\n         else\n           EMPTY           <= #`TCQ 1'b0;\n\n         if (!EMPTY) begin\n           if (almost_empty_int)\n             ALMOST_EMPTY  <= #`TCQ 1'b1;\n           else\n             ALMOST_EMPTY  <= #`TCQ 1'b0;\n         end\n       end // rd_rst_i\n     end // always\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY_FB     <= 1'b1;\n       end else begin\n         if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else if (empty_int)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else\n           EMPTY_FB   <= #`TCQ 1'b0;\n       end // rd_rst_i\n     end // always\n\n   // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;\n     end else begin : wdl // Write depth lesser than or equal to read depth\n       assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n     end\n   endgenerate\n\n  // Generate FULL and ALMOST_FULL\n  // ram_wr_en used to determine FULL should depend on the FULL.\n  assign ram_wr_en       = WR_EN & !FULL;\n  assign full_int        = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));\n  assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));\n\n   // Register FULL and ALMOST_FULL Empty\n   always @ (posedge WR_CLK or posedge RST_FULL_FF)\n     begin\n       if (RST_FULL_FF & C_HAS_RST) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else begin\n         if (full_int) begin\n           FULL           <= #`TCQ 1'b1;\n         end else begin\n           FULL           <= #`TCQ 1'b0;\n         end\n\n         if (RST_FULL_GEN) begin\n           ALMOST_FULL    <= #`TCQ 1'b0;\n         end else if (!FULL) begin\n           if (almost_full_int)\n             ALMOST_FULL  <= #`TCQ 1'b1;\n           else\n             ALMOST_FULL  <= #`TCQ 1'b0;\n         end\n       end // wr_rst_i\n     end // always\n   always @ (posedge WR_CLK or posedge wr_rst_i)\n     begin\n       if (wr_rst_i) begin\n         wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};\n       end else begin\n         wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};\n       end // wr_rst_i\n     end // always\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i) begin\n           stage1_valid     <= 0;\n           stage2_valid     <= 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n   //Pointers passed into opposite clock domain\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_EMPTY.\n   wire [31:0] num_read_words_pe = \n     num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_FULL.\n   wire [31:0] num_write_words_pf =\n     num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n    \n    \n   /***************************************************************************\n    * Internal registers and wires\n    **************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire [C_DOUT_WIDTH-1:0] ideal_dout_out;      \n   wire valid_i;\n   wire valid_out1;\n   wire valid_out2;\n   wire valid_out;  \n   wire underflow_i;\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]               err_type                 = 0;\n   reg [1:0]               err_type_d1              = 0;\n   reg [1:0]               err_type_both              = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout               = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_d1            = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_both            = 0;\n   reg                     ideal_wr_ack             = 0;\n   reg                     ideal_valid              = 0;\n   reg                     ideal_overflow           = C_OVERFLOW_LOW;\n   reg                     ideal_underflow          = C_UNDERFLOW_LOW;\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   reg         valid_d1     = 0;\n   reg         valid_d2     = 0; \n   \n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n   \n\n  /****************************************************************************\n   * Function Declarations\n   ***************************************************************************/\n\n  /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n      if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n    end\n  endtask\n\n  /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n  /***********************************************************************\n  * hexstr_conv\n  *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n  ***********************************************************************/\n  function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_d2           = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n    end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the \n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n    wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;   \n   wire RD_CLK;\n   wire RD_EN;\n   wire RST;\n   wire WR_CLK;\n   wire WR_EN;\n    */\n\n   //***************************************************************************\n   // Dout may change behavior based on latency\n   //***************************************************************************\n   assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?\n                         ideal_dout_d1: ideal_dout;   \n   assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; \n\n   //***************************************************************************\n   // Assign SBITERR and DBITERR based on latency \n   //***************************************************************************\n   assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                    (C_PRELOAD_LATENCY == 2 &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?\n                    err_type_d1[0]: err_type[0]; \n   assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                    (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                    err_type_d1[1]: err_type[1]; \n  \n   //***************************************************************************\n   // Safety-ckt logic with embedded reg/fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n       //  if (C_HAS_VALID == 1) begin\n       //       assign valid_out = valid_d1;\n       //  end\n             \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)\n          begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else \n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n          end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                  @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n           end\n           else begin\n                   if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                   end\n             end \n           end  \n      end \n      endgenerate   \n\n//***************************************************************************\n   // Safety-ckt logic with embedded reg + fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else begin\n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n               fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n          end\n        end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   ideal_dout_both <= #`TCQ dout_reset_val;\n              end\n           end else begin\n             if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n              \n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n             end\n           end \n         end      \n      end \n      endgenerate    \n \n   //***************************************************************************\n   // Overflow may be active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_OVERFLOW==1) begin : blockOF1\n   assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n      end\n   endgenerate\n\n   assign PROG_EMPTY = ideal_prog_empty;\n   assign PROG_FULL  = ideal_prog_full;\n\n   //***************************************************************************\n   // Valid may change behavior based on latency or active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_VALID==1) begin : blockVL1\n   assign valid_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;\n   assign valid_out1 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?\n                       valid_d1: valid_i;  \n   assign valid_out2 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?\n                       valid_d2: valid_i; \n   assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;\n   assign VALID     = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Underflow may change behavior based on latency or active-low   \n   //***************************************************************************\n   generate\n      if (C_HAS_UNDERFLOW==1) begin : blockUF1\n   assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;\n   assign UNDERFLOW   = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n    end\n   endgenerate\n\n   //***************************************************************************\n   // Write acknowledge may be active low\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_ACK==1) begin : blockWK1\n   assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext\n\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_wr_pntr = 0;\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_rd_pntr = 0;\n      wire [C_PNTR_WIDTH-1:0]  diff_wr_rd_tmp;\n      wire [C_PNTR_WIDTH:0]    diff_wr_rd;\n      reg  [C_PNTR_WIDTH:0]    wr_data_count_i  = 0;\n        always @* begin\n          if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = 0;\n            adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n          end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin\n            adjusted_rd_pntr = rd_pntr_wr;\n            adjusted_wr_pntr = 0;\n            adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n          end else begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = rd_pntr_wr;\n          end\n        end // always @*\n\n        assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;\n        assign diff_wr_rd     = {1'b0,diff_wr_rd_tmp};\n\n        always @ (posedge wr_rst_i or posedge WR_CLK)\n        begin\n            if (wr_rst_i)\n              wr_data_count_i <= 0;\n            else\n              wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;\n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n\n        always @* begin\n          if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];\n          else\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n        end // always @*\n      end // wdc_fwft_ext\n   endgenerate\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   reg  [C_RD_PNTR_WIDTH:0]    rdc_fwft_ext_as  = 0;\n\n   generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n\n\n   always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= 0;\n            end else begin\n              if (!stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 0;\n              else if (!stage1_valid && stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 1;\n              else\n                rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;\n            end \n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n      end // rdc_fwft_ext\n end\n   endgenerate\n\n\n  generate if (C_USE_EMBEDDED_REG == 3) begin\n     if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n        wire [C_RD_PNTR_WIDTH:0]  diff_rd_wr_1;\n   //     assign diff_rd_wr_1 = diff_rd_wr +2'h2;\n\n       always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= #`TCQ 0;\n            end else begin\n          //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))\n          //    rdc_fwft_ext_as <= 1'b0;\n          //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) \n          //    rdc_fwft_ext_as <= 1'b1;\n          //else\n            rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;\n        end\n\n\n\nend\nend\nend\nendgenerate\n          \n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1) begin : grdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?\n          rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :\n          rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?\n          wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :\n          wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n\n  /**************************************************************************\n  * Assorted registers for delayed versions of signals\n  **************************************************************************/\n  //Capture delayed version of valid\n  generate\n      if (C_HAS_VALID==1) begin : blockVL2\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n      valid_d1 <= 1'b0;\n      valid_d2 <= 1'b0;\n    end else begin\n      valid_d1 <= #`TCQ valid_i;\n      valid_d2 <= #`TCQ valid_d1;\n    end \n//    if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin\n  //      valid_d2 <= #`TCQ valid_d1;\n      //  end \n  end \n      end\n endgenerate  \n   \n  //Capture delayed version of dout\n  /**************************************************************************\n    *embedded/fabric reg with no safety ckt\n    **************************************************************************/\n  generate \n       if (C_USE_EMBEDDED_REG < 3) begin\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n       if (C_USE_DOUT_RST == 1'b1) begin\n         @(posedge RD_CLK)\n           ideal_dout_d1   <= #`TCQ dout_reset_val;\n           ideal_dout   <= #`TCQ dout_reset_val;\n       end\n      // Reset err_type only if ECC is not selected\n      if (C_USE_ECC == 0)\n        err_type_d1     <= #`TCQ 0;\n     end else if (ram_rd_en_d1) begin\n      ideal_dout_d1   <= #`TCQ ideal_dout;\n      err_type_d1     <= #`TCQ err_type;\n           end    \n  end  \n   \nend  \nendgenerate \n/**************************************************************************\n    *embedded + fabric reg with no safety ckt\n    **************************************************************************/\n\ngenerate \n  if (C_USE_EMBEDDED_REG == 3) begin\n    always @(posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i == 1'b1) begin\n        if (C_USE_DOUT_RST == 1'b1) begin\n           @(posedge RD_CLK)\n             ideal_dout    <= #`TCQ dout_reset_val;\n             ideal_dout_d1   <= #`TCQ dout_reset_val;\n             ideal_dout_both   <= #`TCQ dout_reset_val;\n        end\n        // Reset err_type only if ECC is not selected\n        if (C_USE_ECC == 0) begin\n          err_type_d1     <= #`TCQ 0;\n          err_type_both   <= #`TCQ 0;\n        end\n      end else begin\n         if (ram_rd_en_d1) begin\n           ideal_dout_both   <= #`TCQ ideal_dout;\n           err_type_both     <= #`TCQ err_type;\n         end    \n         if (fab_rd_en_d1) begin\n           ideal_dout_d1   <= #`TCQ ideal_dout_both;\n           err_type_d1     <= #`TCQ err_type_both;\n         end\n      end\n    end  \n  end  \nendgenerate \n\n  \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate\n     if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n       always @(posedge WR_CLK) begin\n         ideal_overflow    <= #`TCQ WR_EN & FULL;\n       end\n     end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n       always @(posedge WR_CLK) begin\n         //ideal_overflow    <= #`TCQ WR_EN & (FULL | wr_rst_i);\n         ideal_overflow    <= #`TCQ WR_EN & (FULL );\n       end\n     end\n   endgenerate\n\n   generate\n     if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ EMPTY & RD_EN;\n       end\n     end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ (EMPTY) & RD_EN;\n         //ideal_underflow    <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;\n       end\n     end\n   endgenerate\n\n   /**************************************************************************\n   * Write/Read Pointer Synchronization\n   **************************************************************************/\n   localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;\n   wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   genvar gss;\n\n   generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (C_WR_PNTR_WIDTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_i), \n         .CLK      (RD_CLK), \n         .DIN      (wr_pntr_sync_stgs[gss-1]), \n         .DOUT     (wr_pntr_sync_stgs[gss])\n        );\n \n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (C_RD_PNTR_WIDTH)\n        )\n     wr_stg_inst\n        (\n         .RST      (wr_rst_i), \n         .CLK      (WR_CLK), \n         .DIN      (rd_pntr_sync_stgs[gss-1]), \n         .DOUT     (rd_pntr_sync_stgs[gss])\n        );\n   end endgenerate // Sync_stage_inst\n\n   assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;\n   assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;\n   always@* begin\n     wr_pntr_rd           <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n     rd_pntr_wr           <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n   end\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp\n     if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)\n       wr_pntr           <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)\n       wr_pntr           <= #`TCQ 0;\n   end\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (wr_rst_i == 1'b1) begin\n       num_wr_bits       <= 0;\n       next_num_wr_bits   = 0;\n       wr_ptr            <= C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= C_RD_DEPTH - 1;\n       ideal_wr_ack      <= 0;\n       ideal_wr_count    <= 0;\n       tmp_wr_listsize    = 0;\n       rd_ptr_wrclk_next <= 0;\n       wr_pntr_rd1       <= 0;\n\n     end else begin //wr_rst_i==0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       //If this is a write, handle the write by adding the value\n       // to the linked list, and updating all outputs appropriately\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD \n             >= C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full, but reporting full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //With DEPTH-1 words in the FIFO, it is almost_full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n\n           //If the FIFO is completely empty, but it is\n           // reporting FULL for some reason (like reset)\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=\n                C_FIFO_WR_DEPTH-2) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //FIFO is really not close to full, so change flag status.\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n           end //(tmp_wr_listsize == 0)\n\n         end else begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=\n              C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack       <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count     <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;\n\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //This write is CAUSING the FIFO to go full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is 2 from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == \n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits =  next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Still 2 from full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is not close to being full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <\n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //wr_rst_i==0\n   end // gen_fifo_w\n\n\n  /***************************************************************************\n   * Programmable FULL flags\n   ***************************************************************************/\n\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;\n\n   generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;\n   end else begin // STD\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;\n   end endgenerate\n\n   always @(posedge WR_CLK or posedge wr_rst_i) begin\n\n     if (wr_rst_i == 1'b1) begin\n       diff_pntr         <= 0;\n     end else begin\n       if (ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);\n       else if (!ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);\n    end\n  end\n\n\n   always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf\n\n     if (RST_FULL_FF & C_HAS_RST) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else begin\n\n       if (RST_FULL_GEN)\n         ideal_prog_full   <= #`TCQ 0;\n       //Single Programmable Full Constant Threshold\n       else if (C_PROG_FULL_TYPE == 1) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else\n             ideal_prog_full <= #`TCQ 0;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Constant Thresholds\n       end else if (C_PROG_FULL_TYPE == 2) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else if (diff_pntr < pf_thr_negate_val)\n             ideal_prog_full <= #`TCQ 0;\n           else\n             ideal_prog_full <= #`TCQ ideal_prog_full;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Single Programmable Full Threshold Input\n       end else if (C_PROG_FULL_TYPE == 3) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH)\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Threshold Inputs\n       end else if (C_PROG_FULL_TYPE == 4) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH_ASSERT)\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < PROG_FULL_THRESH_NEGATE)\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       end // C_PROG_FULL_TYPE\n\n     end //wr_rst_i==0\n   end //\n\n   \n   /**************************************************************************\n   * Read Domain Logic\n   **************************************************************************/\n\n\n   /*********************************************************\n    * Programmable EMPTY flags\n    *********************************************************/\n   //Determine the Assert and Negate thresholds for Programmable Empty\n\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd      = 0;\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe\n\n     if (rd_rst_i & C_HAS_RST) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else begin\n       if (ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;\n       else if (!ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr);\n       else\n         diff_pntr_rd       <=  #`TCQ diff_pntr_rd;\n  \n       if (C_PROG_EMPTY_TYPE == 1) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 2) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 3) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 4) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end  //C_PROG_EMPTY_TYPE\n     end\n   end // gen_pe\n\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;\n   end endgenerate // single_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;\n   end endgenerate // multiple_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;\n   end endgenerate // single_multiple_pe_thr_const\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp\n     if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n       rd_pntr            <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)\n       rd_pntr            <= #`TCQ 0;\n   end\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rd_rst_i & C_HAS_RST) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n     end else begin //rd_rst_i==0\n\n       rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 1\n       /*****************************************************************/\n       if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Reminder that FIFO is still empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end // if (tmp_rd_listsize <= 0)\n\n             //If the FIFO is one from empty, but it is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 1)\n\n             //If the FIFO is two from empty, and is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Fifo has two words, so is neither empty or almost empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 2)\n\n             //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid <= #`TCQ 1'b0;\n                 //Note that the FIFO is No Longer Empty or Almost Empty\n\n                 ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n               end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n             end // else: if(ideal_empty == 1'b1)\n\n           else //if (ideal_empty == 1'b0)\n             begin\n\n               //If the FIFO is completely full, and we are successfully reading from it\n               if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)\n\n               //If the FIFO is not close to being empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n               //If the FIFO is two from empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Fifo is not yet empty. It is going almost_empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n\n               //If the FIFO is one from empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Note that FIFO is GOING empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 1)\n\n\n               //If the FIFO is completely empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n                 begin\n                   //Do not change the contents of the FIFO\n\n                   //Do not acknowledge the read from empty FIFO\n                   ideal_valid        <= #`TCQ 1'b0;\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize <= 0)\n\n             end // if (ideal_empty == 1'b0)\n\n           end //(RD_EN == 1'b1)\n\n         else //if (RD_EN == 1'b0)\n           begin\n             //If user did not attempt a read, do not give an ack or err\n             ideal_valid          <= #`TCQ 1'b0;\n\n             ideal_rd_count       <= #`TCQ num_read_words_sized_i;\n\n           end // else: !if(RD_EN == 1'b1)\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 0\n       /*****************************************************************/\n       end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty, but it is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty, and is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Fifo has two words, so is neither empty or almost empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                         (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that the FIFO is No Longer Empty or Almost Empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n           end else begin\n\n             //If the FIFO is completely full, and we are successfully reading from it\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is not close to being empty\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                          (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Fifo is not yet empty. It is going almost_empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Note that FIFO is GOING empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is completely empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if (tmp_rd_listsize <= 0)\n\n           end // if (ideal_empty == 1'b0)\n\n         end else begin//(RD_EN == 1'b0)\n\n         \n           //If user did not attempt a read, do not give an ack or err\n           ideal_valid           <= #`TCQ 1'b0;\n           ideal_rd_count        <= #`TCQ num_read_words_sized_i;\n\n         end // else: !if(RD_EN == 1'b1)\n       end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //rd_rst_i==0\n   end //always gen_fifo_r_as\n\nendmodule // fifo_generator_v13_2_5_bhv_ver_as\n\n\n/*******************************************************************************\n * Declaration of Low Latency Asynchronous FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_beh_ver_ll_afifo\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_FIFO_TYPE                    = 0\n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   output reg  [C_DOUT_WIDTH-1:0]                DOUT = 0,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL\n  );\n\n  //-----------------------------------------------------------------------------\n  // Low Latency Asynchronous FIFO\n  //-----------------------------------------------------------------------------\n\n  // Memory which will be used to simulate a FIFO\n  reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n  integer i;\n  initial begin\n    for (i = 0; i < C_WR_DEPTH; i = i + 1)\n      memory[i] = 0;\n  end\n\n  reg  [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;\n  wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;\n  reg  [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;\n  reg                        ll_afifo_full    = 1'b0;\n  reg                        ll_afifo_empty   = 1'b1;\n  wire                       write_allow;\n  wire                       read_allow;\n\n  assign write_allow = WR_EN & ~ll_afifo_full;\n  assign read_allow  = RD_EN & ~ll_afifo_empty;\n\n  //-----------------------------------------------------------------------------\n  // Write Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      wr_pntr_ll_afifo   <= 0;\n    else if (write_allow)\n      wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Read Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      rd_pntr_ll_afifo_q   <= 0;\n    else\n      rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;\n  end\n  assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;\n  \n  //-----------------------------------------------------------------------------\n  // Fill the Memory\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK) begin\n    if (write_allow)\n      memory[wr_pntr_ll_afifo] <= #`TCQ DIN;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate DOUT\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK) begin\n      DOUT <= #`TCQ memory[rd_pntr_ll_afifo];\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate EMPTY\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      ll_afifo_empty   <= 1'b1;\n    else\n      ll_afifo_empty   <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | \n                           (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate FULL\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      ll_afifo_full   <= 1'b1;\n    else\n      ll_afifo_full   <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | \n                           (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));\n  end\n\n  always @* begin\n    FULL  <= ll_afifo_full;\n    EMPTY <= ll_afifo_empty;\n  end\n\nendmodule // fifo_generator_v13_2_5_beh_ver_ll_afifo\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_ss\n   \n  /**************************************************************************\n   * Declare user parameters and their defaults\n   *************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0 \n   )\n   \n  /**************************************************************************\n   * Declare Input and Output Ports\n   *************************************************************************/\n   (\n    //Inputs\n    input                                 SAFETY_CKT_WR_RST,\n    input                                 CLK,\n    input       [C_DIN_WIDTH-1:0]         DIN,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_ASSERT,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_NEGATE,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_ASSERT,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_NEGATE,\n    input                                 RD_EN,\n    input                                 RD_EN_USER,\n    input                                 USER_EMPTY_FB,\n    input                                 RST,\n    input                                 RST_FULL_GEN,\n    input                                 RST_FULL_FF,\n    input                                 SRST,\n    input                                 WR_EN,\n    input                                 INJECTDBITERR,\n    input                                 INJECTSBITERR,\n    input                                 WR_RST_BUSY,\n    input                                 RD_RST_BUSY,\n                                    \n    //Outputs                       \n    output                                ALMOST_EMPTY,\n    output                                ALMOST_FULL,\n    output reg   [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,\n    output       [C_DOUT_WIDTH-1:0]       DOUT,\n    output                                EMPTY,\n    output reg                            EMPTY_FB = 1'b1,\n    output                                FULL,\n    output                                OVERFLOW,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]    RD_DATA_COUNT,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]    WR_DATA_COUNT,\n    output                                PROG_EMPTY,\n    output                                PROG_FULL,\n    output                                VALID,\n    output                                UNDERFLOW,\n    output                                WR_ACK,\n    output                                SBITERR,\n    output                                DBITERR\n   );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;\n   wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n   localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; \n\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n   localparam  EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //localparam  EXTRA_WORDS_PE_PARAM  = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not \n   //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.\n   // Therefore, during SRST, all the FULL flags reset to 0.\n   localparam                      C_HAS_FAST_FIFO = 0;\n   localparam                      C_FIFO_WR_DEPTH = C_WR_DEPTH;\n   localparam                      C_FIFO_RD_DEPTH = C_RD_DEPTH;\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;\n   localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;\n   localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;\n   localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n  localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; \n  localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; \n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   \n   /**************************************************************************\n    * Internal Registers and wires\n    *************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire                           underflow_i;\n   wire                           valid_i;\n   wire                           valid_out;\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_reg = 1'b0;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n   wire                         srst_rrst_busy;\n\n\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]                      err_type           = 0;\n   reg [1:0]                      err_type_d1        = 0;\n   reg [1:0]                      err_type_both      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout         = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_d1      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_both      = 0;\n   wire [C_DOUT_WIDTH-1:0]        ideal_dout_out;\n   wire                           fwft_enabled;\n   reg                            ideal_wr_ack       = 0;\n   reg                            ideal_valid        = 0;\n   reg                            ideal_overflow     = C_OVERFLOW_LOW;\n   reg                            ideal_underflow    = C_UNDERFLOW_LOW;\n\n   reg                            full_i             = C_FULL_FLAGS_RST_VAL;\n   reg                            full_i_temp        = 0;\n   reg                            empty_i            = 1;\n   reg                            almost_full_i      = 0;\n   reg                            almost_empty_i     = 1;\n   reg                            prog_full_i        = 0;\n   reg                            prog_empty_i       = 1;\n   reg [C_WR_PNTR_WIDTH-1:0]      wr_pntr            = 0;\n   reg [C_RD_PNTR_WIDTH-1:0]      rd_pntr            = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg [C_RD_PNTR_WIDTH-1:0]      diff_count         = 0;\n\n   reg                            write_allow_q      = 0;\n   reg                            read_allow_q       = 0;\n   reg                            valid_d1           = 0;\n   reg                            valid_both           = 0;\n   reg                            valid_d2           = 0;\n   wire                           rst_i;\n   wire                           srst_i;\n\n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]         dout_reset_val = 0;\n\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n\n\n\n   /****************************************************************************\n    * Function Declarations\n    ***************************************************************************/\n\n   /****************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***************************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin\n        case (def_data[7:0])\n          8'b00000000 : begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default : begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1) begin\n          if ((index*4)+j < C_DOUT_WIDTH) begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   //reg         valid_d1     = 0;\n   \n   \n   //user specified value for reseting the size of the fifo\n   //reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n\n\n /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n     if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n\n     end\n  endtask\n\n\n   \n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_dout_both    = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_both         = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n\n   end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the\n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n   wire CLK;\n   wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;\n   wire RD_EN;\n   wire RST;\n   wire WR_EN;\n    */\n\n  // Assign ALMOST_EPMTY\n  generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae\n    assign ALMOST_EMPTY = almost_empty_i;\n  end else begin : gnae\n    assign ALMOST_EMPTY = 0;\n  end endgenerate // gae\n\n  // Assign ALMOST_FULL\n  generate if (C_HAS_ALMOST_FULL==1) begin : gaf\n    assign ALMOST_FULL  = almost_full_i;\n  end else begin : gnaf\n    assign ALMOST_FULL  = 0;\n  end endgenerate // gaf\n\n   // Dout may change behavior based on latency\n  localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?\n                         ideal_dout_d1: ideal_dout; \n  assign DOUT = ideal_dout_out;\n\n  // Assign SBITERR and DBITERR based on latency \n  assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[0]: err_type[0]; \n  assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[1]: err_type[1]; \n\n  assign EMPTY         = empty_i;\n  assign FULL          = full_i;\n  //saftey_ckt with one register\n\n  generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)\n          begin\n          if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n              valid_d1 <= #`TCQ 1'b0;\n          end\n          else begin\n               ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n               valid_d1 <= #`TCQ valid_i;\n          end\n          end\n          \n           always@(posedge rst_delayed_sft2 or posedge CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n              end\n           else if (srst_rrst_busy == 1'b1) begin\n                   if (C_USE_DOUT_RST == 1'b1) begin\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   end\n           end else if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                end\n           end   \n      end //if \n      endgenerate   \n\n//safety ckt with both registers\n\ngenerate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK) begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            valid_d1 <= #`TCQ 1'b0;\n          end else begin\n            ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n            fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n            valid_both <= #`TCQ valid_i;\n            valid_d1 <= #`TCQ valid_both;\n          end\n        end\n\n        always@(posedge rst_delayed_sft2 or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                  ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else if (srst_rrst_busy == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else begin \n            if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n            end\n          end\n        end\n      end //if \n      endgenerate    \n \n \n  //Overflow may be active-low\n  generate if (C_HAS_OVERFLOW==1) begin : gof\n    assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n  end else begin : gnof\n    assign OVERFLOW = 0;\n  end endgenerate // gof\n\n  assign PROG_EMPTY    = prog_empty_i;\n  assign PROG_FULL     = prog_full_i;\n\n   //Valid may change behavior based on latency or active-low\n  generate if (C_HAS_VALID==1) begin : gvalid\n    assign valid_i       = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;\n    assign valid_out     = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?\n                            valid_d1 : valid_i; \n    assign VALID         = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n  end else begin : gnvalid\n    assign VALID         = 0;\n  end endgenerate // gvalid\n\n  //Trim data count differently depending on set widths\n  generate if (C_HAS_DATA_COUNT == 1) begin : gdc\n    always @* begin\n      diff_count <= wr_pntr - rd_pntr;\n      if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin\n        DATA_COUNT[C_RD_PNTR_WIDTH-1:0]  <= diff_count;\n        DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; \n      end else begin\n        DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];\n      end\n    end\n//  end else begin : gndc\n//    always @* DATA_COUNT <= 0;\n  end endgenerate // gdc\n\n  //Underflow may change behavior based on latency or active-low\n  generate if (C_HAS_UNDERFLOW==1) begin : guf\n    assign underflow_i   = ideal_underflow;\n    assign UNDERFLOW     = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n  end else begin : gnuf\n    assign UNDERFLOW     = 0;\n  end endgenerate // guf\n \n\n  //Write acknowledge may be active low \n  generate if (C_HAS_WR_ACK==1) begin : gwr_ack\n    assign WR_ACK        = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n  end else begin : gnwr_ack\n    assign WR_ACK        = 0;\n  end endgenerate // gwr_ack\n\n\n  /*****************************************************************************\n   * Internal reset logic \n   ****************************************************************************/\n  assign srst_i        = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;\n  assign rst_i            = C_HAS_RST ? RST : 0;\n  assign srst_wrst_busy   = srst_i;\n  assign srst_rrst_busy   = srst_i;\n\n   /**************************************************************************\n    * Assorted registers for delayed versions of signals\n    **************************************************************************/\n   //Capture delayed version of valid\n   generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20\n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1 <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n           end else begin\n              valid_d1 <= #`TCQ valid_i;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n     end \n   endgenerate // blockVL20\n\n  generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin \n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1   <= 1'b0;\n           valid_both <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n              valid_both <= #`TCQ 1'b0;\n              \n           end else begin\n              valid_both <= #`TCQ valid_i;\n               valid_d1 <= #`TCQ valid_both;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n  end\n endgenerate // blockVL20\n\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge CLK or posedge rst_i) begin\n         if (rst_i) begin\n           stage1_valid     <= #`TCQ 0;\n           stage2_valid     <= #`TCQ 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n\n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc\n       assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc\n       assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n   \n   //reg ram_rd_en_d1 = 1'b0;\n   //Capture delayed version of dout\n   generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         ram_rd_en_d1 <= #`TCQ 1'b0;\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n        end\n      end else begin\n         ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n         if (srst_rrst_busy) begin\n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            // Reset err_type only if ECC is not selected\n            if (C_USE_ECC == 0) begin\n               err_type_d1   <= #`TCQ 0;\n               err_type_both <= #`TCQ 0;\n            end\n            // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n            if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n            end \n         if (C_USE_DOUT_RST == 1) begin\n           // @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         end else begin\n            if (ram_rd_en_d1 ) begin\n            ideal_dout_d1 <= #`TCQ ideal_dout;\n            err_type_d1   <= #`TCQ err_type;\n            end\n         end\n      end    \n   end   // always\nend\nendgenerate \n\n//no safety ckt with both registers\n generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n          ram_rd_en_d1 <= #`TCQ 1'b0;\n          fab_rd_en_d1 <= #`TCQ 1'b0;\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val; \n            \n      end\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val;\n       end\n      end else begin\n         if (srst_rrst_busy) begin \n           ram_rd_en_d1 <= #`TCQ 1'b0;\n           fab_rd_en_d1 <= #`TCQ 1'b0;\n           // Reset err_type only if ECC is not selected\n           if (C_USE_ECC == 0) begin\n              err_type_d1   <= #`TCQ 0;\n              err_type_both <= #`TCQ 0;\n           end\n           // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n           if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n              ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end \n           if (C_USE_DOUT_RST == 1) begin\n             ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end\n         end else begin\n           ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n           fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);\n           if (ram_rd_en_d1 ) begin\n             ideal_dout_both <= #`TCQ ideal_dout;\n             err_type_both   <= #`TCQ err_type;\n           end\n           if (fab_rd_en_d1 ) begin\n             ideal_dout_d1 <= #`TCQ ideal_dout_both;\n             err_type_d1   <= #`TCQ err_type_both;\n           end\n         end\n      end    \n   end   // always\nend\nendgenerate \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n     always @(posedge CLK) begin\n       ideal_overflow    <= #`TCQ WR_EN & full_i;\n     end\n   end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n     always @(posedge CLK) begin\n       //ideal_overflow    <= #`TCQ WR_EN & (rst_i | full_i);\n       ideal_overflow    <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);\n     end\n   end endgenerate // blockOF20\n \n   generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n     always @(posedge CLK) begin\n       ideal_underflow   <= #`TCQ empty_i & RD_EN;\n     end\n   end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n     always @(posedge CLK) begin\n       //ideal_underflow   <= #`TCQ (rst_i | empty_i) & RD_EN;\n       ideal_underflow   <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;\n     end\n   end endgenerate // blockUF20\n\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n\n  /*************************************************************************\n   * Write and Read Logic  \n   ************************************************************************/\n   wire              write_allow;\n   wire              read_allow;\n   wire              read_allow_dc;\n   wire              write_only;\n   wire              read_only;\n   //wire              write_only_q;\n   reg              write_only_q;\n   //wire              read_only_q;\n   reg              read_only_q;\n   reg              full_reg;\n   reg              rst_full_ff_reg1;\n   reg              rst_full_ff_reg2;\n   wire              ram_full_comb;\n   wire              carry;\n   \n   assign write_allow  = WR_EN & ~full_i;\n   assign read_allow   = RD_EN & ~empty_i;\n   assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;\n   //assign write_only   = write_allow & ~read_allow;\n   //assign write_only_q = write_allow_q;\n   //assign read_only    = read_allow    & ~write_allow;\n   //assign read_only_q  = read_allow_q ;\n   wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;\n   wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;\n   wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;\n\n   assign diff_pntr_pe_max = DIFF_MAX_RD;\n   assign diff_pntr_max = DIFF_MAX_WR;\n\n\n\n   generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym\n    assign write_only   = write_allow & ~read_allow;\n    assign read_only    = read_allow    & ~write_allow;\n    end endgenerate\n    generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd\n     assign read_only   = read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;\n     assign write_only    = write_allow    & ~(read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n    generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr\n     assign read_only   = read_allow & ~(write_allow  & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n     assign write_only    = write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;\n    end endgenerate\n\n\n   //-----------------------------------------------------------------------------\n   // Write and Read pointer generation\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       wr_pntr         <= 0;\n       rd_pntr         <= 0;\n     end else begin\n       if (srst_i) begin\n         wr_pntr       <= #`TCQ 0;\n         rd_pntr       <= #`TCQ 0;\n       end else begin\n         if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;\n         if (read_allow)  rd_pntr <= #`TCQ rd_pntr + 1;\n       end\n     end\n   end\n\n   generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout\n   always @(posedge CLK) begin\n     if (write_allow) begin\n       if (ENABLE_ERR_INJECTION == 1)\n         memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};\n       else\n         memory[wr_pntr] <= #`TCQ DIN;\n     end\n   end\n\n   reg  [C_DATA_WIDTH-1:0] dout_tmp_q;\n   reg [C_DATA_WIDTH-1:0] dout_tmp = 0;\n   reg  [C_DATA_WIDTH-1:0] dout_tmp1 = 0;\n   always @(posedge CLK) begin\n     dout_tmp_q <= #`TCQ ideal_dout;\n   end\n\n\n\n     always @* begin\n       if (read_allow)\n         ideal_dout <= memory[rd_pntr];\n       else\n         ideal_dout <= dout_tmp_q;\n     end\n   end endgenerate // gll_dm_dout\n\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   assign ram_rd_en        = RD_EN & !EMPTY;\n\n   //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   generate if (C_FIFO_TYPE != 2) begin : gnll_din\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i == 1'b1) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n\n     end else begin //rst_i==0\n     if (srst_wrst_busy) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n     end else begin//srst_i=0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n         end else begin\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error  \n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           //end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //srst_i==0\n     end //wr_rst_i==0\n   end // gen_fifo_w\n    end endgenerate\n\n   generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout\n     always @(posedge CLK) begin\n       if (rst_i || srst_rrst_busy) begin\n         if (C_USE_DOUT_RST == 1) begin\n           ideal_dout <= #`TCQ dout_reset_val;\n           ideal_dout_both <= #`TCQ dout_reset_val;\n         end\n       end\n     end\n    end endgenerate\n\n\n\n\n   generate if (C_FIFO_TYPE != 2) begin : gnll_dout\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_r\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n\n     end else begin //rd_rst_i==0\n     if (srst_rrst_busy) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets synchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= #`TCQ 0;\n         err_type_both    <= #`TCQ 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n      end //srst_i\n      else begin\n\n       //rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n         if (RD_EN == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end \n           else \n             begin\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n         end\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //s_rst_i==0\n     end //rd_rst_i==0\n   end //always\n  end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate diff_pntr for PROG_FULL generation\n   // Generate diff_pntr_pe for PROG_EMPTY generation\n   //-----------------------------------------------------------------------------\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         write_only_q   <= 1'b0;\n         read_only_q    <= 1'b0;\n         diff_pntr_reg1       <= 0;\n         diff_pntr_pe_reg1    <= 0;\n         diff_pntr_reg2       <= 0;\n         diff_pntr_pe_reg2    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_rrst_busy) begin\n           read_only_q  <= #`TCQ 1'b0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n           diff_pntr_pe_reg2  <= #`TCQ 0;\n          end\n          if (srst_wrst_busy) begin\n           write_only_q <= #`TCQ 1'b0;\n           diff_pntr_reg1     <= #`TCQ 0;\n           diff_pntr_reg2     <= #`TCQ 0;\n          end\n         end else begin\n           write_only_q <= #`TCQ write_only;\n           read_only_q  <= #`TCQ read_only;\n           diff_pntr_reg2  <= #`TCQ diff_pntr_reg1;\n           diff_pntr_pe_reg2  <= #`TCQ diff_pntr_pe_reg1;\n\n           // Add 1 to the difference pointer value when only write happens.\n           if (write_only)  \n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;\n           else\n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;\n\n           // Add 1 to the difference pointer value when write or both write & read or no write & read happen.\n           if (read_only)  \n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;\n           else\n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;\n         end\n       end\n     end\n   assign diff_pntr_pe = diff_pntr_pe_reg1;\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow\n\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym\n    assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};\n    assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         diff_pntr_pe_asym    <= 0;\n         diff_pntr_reg1       <= 0;\n         full_reg             <= 0;\n         rst_full_ff_reg1     <= 1;\n         rst_full_ff_reg2     <= 1;\n         diff_pntr_pe_reg1    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_wrst_busy)\n           diff_pntr_reg1     <= #`TCQ 0;\n          if (srst_rrst_busy)\n           full_reg             <=  #`TCQ 0;\n           rst_full_ff_reg1     <=  #`TCQ 1;\n           rst_full_ff_reg2     <=  #`TCQ 1;\n           diff_pntr_pe_asym    <=  #`TCQ 0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n         end else begin\n             diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;\n             full_reg          <= #`TCQ full_i;\n             rst_full_ff_reg1  <=  #`TCQ RST_FULL_FF;\n             rst_full_ff_reg2  <=  #`TCQ rst_full_ff_reg1;\n           if (~full_i) begin  \n             diff_pntr_reg1 <=  #`TCQ wr_pntr - adj_rd_pntr_wr;\n          end\n         end\n       end\n     end\n   assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));\n   assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow_asym\n\n\n   //-----------------------------------------------------------------------------\n   // Generate FULL flag\n   //-----------------------------------------------------------------------------\n   wire                 comp0;\n   wire                 comp1;\n   wire                 going_full;\n   wire                 leaving_full;\n \n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin :  gpad \t\n    assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;\n    assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin :  gtrim \n    assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n  end endgenerate\n\n   assign comp1         = (adj_rd_pntr_wr == (wr_pntr + 1'b1));\n   assign comp0         = (adj_rd_pntr_wr == wr_pntr);\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp\n     assign going_full    = (comp1 & write_allow & ~read_allow);\n     assign leaving_full  = (comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym\n      assign going_full = (comp1 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_full = (comp0 & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp \n      assign going_full = (comp1 & write_allow & ~read_allow);\n      assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n\n   assign ram_full_comb = going_full | (~leaving_full & full_i);\n\n   generate if (C_HAS_RST == 1) begin : grst_full\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF & C_HAS_RST)\n         full_i   <= C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_SRST == 1) begin : gsrst_full\n     always @(posedge CLK) begin\n       if (srst_wrst_busy)\n         full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_full\n     always @(posedge CLK) begin\n         full_i   <= #`TCQ ram_full_comb;\n     end\n   end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate EMPTY flag\n   //-----------------------------------------------------------------------------\n   wire                 ecomp0;\n   wire                 ecomp1;\n   wire                 going_empty;\n   wire                 leaving_empty;\n   wire                 ram_empty_comb;\n\n  \n generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin :  pad \t\n    assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n    assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin :  trim \n    assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n  end endgenerate\n\n   assign ecomp1         = (adj_wr_pntr_rd == (rd_pntr + 1'b1));\n   assign ecomp0         = (adj_wr_pntr_rd == rd_pntr);\n\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp\n     assign going_empty    = (ecomp1 & ~write_allow & read_allow);\n     assign leaving_empty  = (ecomp0 & write_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp\n      assign going_empty = (ecomp1 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_empty = (ecomp0 & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp \n      assign going_empty = (ecomp1 & ~write_allow & read_allow);\n      assign leaving_empty =(ecomp0 & write_allow);\n    end endgenerate\n\n\n\n    assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);\n\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       empty_i  <= 1'b1;\n     else if (srst_rrst_busy)\n       empty_i  <= #`TCQ 1'b1;\n     else\n       empty_i  <= #`TCQ ram_empty_comb;\n    end\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       EMPTY_FB     <= 1'b1;\n     end else begin\n       if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))\n         EMPTY_FB   <= #`TCQ 1'b1;\n       else\n         EMPTY_FB   <= #`TCQ ram_empty_comb;\n     end\n   end // always\n\n   //-----------------------------------------------------------------------------\n   // Generate Read and write data counts for asymmetic common clock\n   //-----------------------------------------------------------------------------\n\n    reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; \n    wire [C_GRTR_PNTR_WIDTH :0] ratio; \n    wire decr_by_one;\n    wire incr_by_ratio;\n    wire incr_by_one;\n    wire decr_by_ratio;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n\n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr \n      assign ratio         = C_DEPTH_RATIO_RD;\n      assign decr_by_one   = (IS_FWFT == 1)? read_allow_dc : read_allow;\n      assign incr_by_ratio = write_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (decr_by_one) begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc - 1;\n           else\n\t    count_dc <= #`TCQ count_dc - 1  + ratio ;\n\t end\n\t else begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc + ratio ;\n\tend\n       end\n       end\n\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n\n    end endgenerate\n\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd \n      assign ratio         = C_DEPTH_RATIO_WR;\n      assign incr_by_one   = write_allow;\n      assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (incr_by_one) begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc + 1;\n           else\n\t    count_dc <= #`TCQ count_dc + 1  - ratio ;\n\t end\n\t else begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc - ratio ;\n\tend\n       end\n       end\n\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n\n    end endgenerate\n\n\n\n\n\n\n   //-----------------------------------------------------------------------------\n   // Generate WR_ACK flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_wr_ack  <= 1'b0;\n     else if (srst_wrst_busy)\n       ideal_wr_ack  <= #`TCQ 1'b0;\n     else if (WR_EN & ~full_i)\n       ideal_wr_ack  <= #`TCQ 1'b1;\n     else\n       ideal_wr_ack  <= #`TCQ 1'b0;\n    end\n\n   //-----------------------------------------------------------------------------\n   // Generate VALID flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_valid  <= 1'b0;\n     else if (srst_rrst_busy)\n       ideal_valid  <= #`TCQ 1'b0;\n     else if (RD_EN & ~empty_i)\n       ideal_valid  <= #`TCQ 1'b1;\n     else\n       ideal_valid  <= #`TCQ 1'b0;\n    end\n\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_FULL flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss\n\n     wire                 fcomp2;\n     wire                 going_afull;\n     wire                 leaving_afull;\n     wire                 ram_afull_comb;\n\n\n   assign fcomp2         = (adj_rd_pntr_wr == (wr_pntr + 2'h2));\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp\n     assign going_afull    = (fcomp2 & write_allow & ~read_allow);\n     assign leaving_afull  = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym\n      assign going_afull = (fcomp2 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_afull = (comp1 & (~write_allow) & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp \n      assign going_afull = (fcomp2 & write_allow & ~read_allow);\n      assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n     assign ram_afull_comb  = going_afull | (~leaving_afull & almost_full_i);\n\n\n    generate if (C_HAS_RST == 1) begin : grst_afull\n      always @(posedge CLK or posedge RST_FULL_FF) begin\n        if (RST_FULL_FF & C_HAS_RST)\n          almost_full_i   <= C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_SRST == 1) begin : gsrst_afull\n      always @(posedge CLK) begin\n        if (srst_wrst_busy)\n          almost_full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_afull\n      always @(posedge CLK) begin\n          almost_full_i   <= #`TCQ ram_afull_comb;\n      end\n    end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_EMPTY flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss\n\n     wire                 ecomp2;\n     wire                 going_aempty;\n     wire                 leaving_aempty;\n     wire                 ram_aempty_comb;\n      \n     assign ecomp2          = (adj_wr_pntr_rd == (rd_pntr + 2'h2));\n   \n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp\n     assign going_aempty    = (ecomp2 & ~write_allow & read_allow);\n     assign leaving_aempty  = (ecomp1 & write_allow & ~read_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp\n      assign going_aempty = (ecomp2 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp \n      assign going_aempty = (ecomp2 & ~write_allow & read_allow);\n      assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);\n    end endgenerate\n\n\n     assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);\n\n     always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         almost_empty_i  <= 1'b1;\n       else if (srst_rrst_busy)\n         almost_empty_i  <= #`TCQ 1'b1;\n       else\n         almost_empty_i  <= #`TCQ ram_aempty_comb;\n      end\n  // end endgenerate // gae_ss\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL\n   //-----------------------------------------------------------------------------\n\n   localparam  C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT \n                                  C_PROG_FULL_THRESH_ASSERT_VAL; // STD\n   localparam  C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT\n                                  C_PROG_FULL_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;   \n   generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin \n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n          prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr>= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  ((diff_pntr) < C_PF_ASSERT_VAL )\n        prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate // single_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr >= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n       else if  (diff_pntr < C_PF_NEGATE_VAL)\n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate //multiple_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT\n                                               PROG_FULL_THRESH; // STD\n   generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input\n\n     always @(posedge CLK or posedge RST_FULL_FF) begin//0\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin //1\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin//2 \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin//3\n           if (diff_pntr > pf3_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if (diff_pntr == pf3_assert_val) begin//4\n             if (read_only_q)\n               prog_full_i <= #`TCQ 1'b0;\n             else\n               prog_full_i <= #`TCQ 1'b1;\n           end else//4\n             prog_full_i <= #`TCQ 1'b0;\n         end else//3\n           prog_full_i <= #`TCQ prog_full_i;\n       end //2\n       else begin//5\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin//6 \n        if (diff_pntr >= pf3_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  (diff_pntr < pf3_assert_val) begin//7\n         prog_full_i <= #`TCQ 1'b0;\n       end//7\n       end//6\n      else\n           prog_full_i <= #`TCQ prog_full_i;\n       end//5\n     end//1\n     end//0\n   end endgenerate //single_pf_input\n  \n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_ASSERT; // STD\n   wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_NEGATE; // STD\n\n   generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin\n           if (diff_pntr >= pf_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if ((diff_pntr == pf_negate_val && read_only_q) ||\n                  diff_pntr < pf_negate_val)\n             prog_full_i <= #`TCQ 1'b0;\n           else\n             prog_full_i <= #`TCQ prog_full_i;\n         end else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin \n        if (diff_pntr >= pf_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n       else if (diff_pntr < pf_negate_val) \n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n\n     end\n   end\n   end endgenerate //multiple_pf_inputs\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY\n   //-----------------------------------------------------------------------------\n   localparam  C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD\n   localparam  C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i) \n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy) \n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL)\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > C_PE_ASSERT_VAL)\n         prog_empty_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n     end\n     end\n   end endgenerate // single_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > C_PE_NEGATE_VAL) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n\n     end\n\n     end\n   end endgenerate //multiple_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH -2) : // FWFT\n                                                PROG_EMPTY_THRESH; // STD\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe < pe3_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (diff_pntr_pe == pe3_assert_val) begin\n             if (write_only_q)\n               prog_empty_i <= #`TCQ 1'b0;\n             else\n               prog_empty_i <= #`TCQ 1'b1;\n           end else\n             prog_empty_i <= #`TCQ 1'b0;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe3_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > pe3_assert_val)\n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n\n     end\n   end endgenerate // single_pe_input\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_ASSERT; // STD\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_NEGATE; // STD\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n      else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe <= pe4_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || \n                     (diff_pntr_pe > pe4_negate_val)) begin\n             prog_empty_i <= #`TCQ 1'b0;\n           end else\n             prog_empty_i <= #`TCQ prog_empty_i;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe4_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > pe4_negate_val) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n     end\n   end endgenerate // multiple_pe_inputs\n\nendmodule // fifo_generator_v13_2_5_bhv_ver_ss\n\n\n\n/**************************************************************************\n * First-Word Fall-Through module (preload 0)\n **************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_preload0\n  #(\n    parameter  C_DOUT_RST_VAL            = \"\",\n    parameter  C_DOUT_WIDTH              = 8,\n    parameter  C_HAS_RST                 = 0,\n    parameter  C_ENABLE_RST_SYNC         = 0,\n    parameter  C_HAS_SRST                = 0,\n    parameter  C_USE_EMBEDDED_REG        = 0,\n    parameter  C_EN_SAFETY_CKT           = 0, \n    parameter  C_USE_DOUT_RST            = 0,\n    parameter  C_USE_ECC                 = 0,\n    parameter  C_USERVALID_LOW           = 0,\n    parameter  C_USERUNDERFLOW_LOW       = 0,\n    parameter  C_MEMORY_TYPE             = 0,\n    parameter  C_FIFO_TYPE               = 0\n  )\n  (\n    //Inputs\n    input                          SAFETY_CKT_RD_RST,\n    input                          RD_CLK,\n    input                          RD_RST,\n    input                          SRST,\n    input                          WR_RST_BUSY,\n    input                          RD_RST_BUSY,\n    input                          RD_EN,\n    input                          FIFOEMPTY,\n    input       [C_DOUT_WIDTH-1:0] FIFODATA,\n    input                          FIFOSBITERR,\n    input                          FIFODBITERR,\n   \n    //Outputs\n    output reg  [C_DOUT_WIDTH-1:0] USERDATA,\n    output                         USERVALID,\n    output                         USERUNDERFLOW,\n    output                         USEREMPTY,\n    output                         USERALMOSTEMPTY,\n    output                         RAMVALID,\n    output                         FIFORDEN,\n    output reg                     USERSBITERR,\n    output reg                     USERDBITERR,\n    output reg                     STAGE2_REG_EN,\n    output                         fab_read_data_valid_i_o,\n    output                         read_data_valid_i_o,\n    output                         ram_valid_i_o,\n    output      [1:0]              VALID_STAGES \n  );\n //Internal signals\n wire                      preloadstage1;\n wire                      preloadstage2;\n reg                       ram_valid_i;\n reg                       fab_valid;\n reg                       read_data_valid_i;\n reg                       fab_read_data_valid_i;\n reg                       fab_read_data_valid_i_1;\n reg                       ram_valid_i_d;\n reg                       read_data_valid_i_d;\n reg                       fab_read_data_valid_i_d;\n wire                      ram_regout_en;\n reg                       ram_regout_en_d1;\n reg                       ram_regout_en_d2;\n wire                      fab_regout_en;\n wire                      ram_rd_en;\n reg                       empty_i        = 1'b1;\n reg                       empty_sckt     = 1'b1;\n reg                       sckt_rrst_q    = 1'b0;\n reg                       sckt_rrst_done = 1'b0;\n reg                       empty_q        = 1'b1;\n reg                       rd_en_q        = 1'b0;\n reg                       almost_empty_i = 1'b1;\n reg                       almost_empty_q = 1'b1;\n wire                      rd_rst_i;\n wire                      srst_i;\n reg  [C_DOUT_WIDTH-1:0]   userdata_both;\n wire                      uservalid_both;\n wire                      uservalid_one;\n reg                       user_sbiterr_both = 1'b0;\n reg                       user_dbiterr_both = 1'b0;\n  \nassign ram_valid_i_o = ram_valid_i;\nassign read_data_valid_i_o = read_data_valid_i;\nassign fab_read_data_valid_i_o = fab_read_data_valid_i; \n\n\n\n/*************************************************************************\n* FUNCTIONS\n*************************************************************************/\n\n   /*************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***********************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n   \n   //*************************************************************************\n   //  Set power-on states for regs\n   //*************************************************************************\n   initial begin\n      ram_valid_i       = 1'b0;\n      fab_valid         = 1'b0;\n      read_data_valid_i = 1'b0;\n      fab_read_data_valid_i = 1'b0;\n      fab_read_data_valid_i_1 = 1'b0;\n      USERDATA          = hexstr_conv(C_DOUT_RST_VAL);\n      userdata_both          = hexstr_conv(C_DOUT_RST_VAL);\n      USERSBITERR       = 1'b0;\n      USERDBITERR       = 1'b0;\n      user_sbiterr_both = 1'b0;\n      user_dbiterr_both = 1'b0;\n   end //initial\n\n   //***************************************************************************\n   //  connect up optional reset\n   //***************************************************************************\n   assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;\n   assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;\n\n   reg  sckt_rd_rst_fwft = 1'b0;\n   reg  fwft_rst_done_i  = 1'b0;\n   wire fwft_rst_done;\n   assign fwft_rst_done = 1'b1;//C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;\n   always @ (posedge RD_CLK) begin\n     sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;\n   end\n\n   always @ (posedge rd_rst_i or posedge RD_CLK) begin\n     if (rd_rst_i)\n       fwft_rst_done_i  <= 1'b0;\n     else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)\n       fwft_rst_done_i  <= #`TCQ 1'b1;\n   end\n\n   localparam INVALID             = 0;\n   localparam STAGE1_VALID        = 2;\n   localparam STAGE2_VALID        = 1;\n   localparam BOTH_STAGES_VALID   = 3;\n\n   reg  [1:0] curr_fwft_state = INVALID;\n   reg  [1:0] next_fwft_state = INVALID;\n\n\ngenerate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin\n         always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n \n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n     \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n    \n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = preloadstage2;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;\n   end\nendgenerate // gnll_fifo\n\n   reg curr_state         = 0;\n   reg next_state         = 0;\n   reg leaving_empty_fwft = 0;\n   reg going_empty_fwft   = 0;\n   reg empty_i_q          = 0;\n   reg ram_rd_en_fwft     = 0;\n   generate if (C_FIFO_TYPE == 2) begin : gll_fifo\n     always @* begin // FSM fo FWFT\n       case (curr_state)\n         1'b0: begin\n           if (~FIFOEMPTY)\n             next_state <= 1'b1;\n           else\n             next_state <= 1'b0;\n           end\n         1'b1: begin\n           if (FIFOEMPTY && RD_EN)\n             next_state <= 1'b0;\n           else\n             next_state <= 1'b1;\n           end\n         default: next_state <= 1'b0;\n       endcase\n     end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_i       <= 1'b1;\n           empty_i_q     <= 1'b1;\n           ram_valid_i   <= 1'b0;\n        end else if (srst_i) begin\n           empty_i       <= #`TCQ 1'b1;\n           empty_i_q     <= #`TCQ 1'b1;\n           ram_valid_i   <= #`TCQ 1'b0;\n        end else begin\n           empty_i       <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);\n           empty_i_q     <= #`TCQ FIFOEMPTY;\n           ram_valid_i   <= #`TCQ next_state;\n        end\n     end //always\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n           curr_state    <= 1'b0;\n        end else if (srst_i) begin\n           curr_state    <= #`TCQ 1'b0;\n        end else begin\n           curr_state    <= #`TCQ next_state;\n        end\n     end //always\n\n     wire                  fe_of_empty; \n     assign fe_of_empty   = empty_i_q & ~FIFOEMPTY;\n\n     always @* begin // Finding leaving empty\n       case (curr_state)\n         1'b0:    leaving_empty_fwft <= fe_of_empty;\n         1'b1:    leaving_empty_fwft <= 1'b1;\n         default: leaving_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Finding going empty\n       case (curr_state)\n         1'b1:    going_empty_fwft <= FIFOEMPTY & RD_EN;\n         default: going_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Generating FWFT rd_en\n       case (curr_state)\n         1'b0:    ram_rd_en_fwft <= ~FIFOEMPTY;\n         1'b1:    ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;\n         default: ram_rd_en_fwft <= 1'b0;\n       endcase\n     end\n\n     assign ram_regout_en = ram_rd_en_fwft;\n     //assign ram_regout_en_d1 = ram_rd_en_fwft;\n     //assign ram_regout_en_d2 = ram_rd_en_fwft;\n     assign ram_rd_en     = ram_rd_en_fwft;\n   end endgenerate // gll_fifo\n\n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false.\n   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n   generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           ram_valid_i     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              ram_valid_i     <= #`TCQ 1'b0;\n           end else begin\n              if (ram_rd_en == 1'b1) begin\n                 ram_valid_i   <= #`TCQ 1'b1;\n              end else begin\n                 if (ram_regout_en == 1'b1)\n                   ram_valid_i <= #`TCQ 1'b0;\n                 else\n                   ram_valid_i <= #`TCQ ram_valid_i;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_ram_valid\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n  \n generate if(C_USE_EMBEDDED_REG < 3) begin\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else\n        read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);\n   end //always\nend \nendgenerate\n\n   \n   \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n generate if ( C_USE_EMBEDDED_REG < 3) begin\n  always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin         // asynchronous reset (active high)\n             almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ FIFOEMPTY;\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n   \n   \n     \n  // BRAM resets synchronously\n generate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin\n   always @ ( posedge rd_rst_i)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n           @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n             USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end  else if (fwft_rst_done) begin\n            if (ram_regout_en) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end\n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n//safety ckt with one register\ngenerate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n            @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n        end\n     end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n          //@(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end \n       end\n        else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n            //  @(posedge RD_CLK)\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end else if (fwft_rst_done) begin\n            if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end          \n          end\n        end\n       end //always\n  end //if\nendgenerate\n\n\ngenerate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin\n         \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d1 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d1 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d1 <= #`TCQ ram_regout_en;\n                 end\n            end //always\n   //  assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));\n       assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d2 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d2 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;\n                 end\n            end //always\n\n    \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n     always @ (posedge RD_CLK) begin\n        ram_valid_i_d <= #`TCQ ram_valid_i;\n        read_data_valid_i_d <= #`TCQ read_data_valid_i;\n        fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;\n\n     end\n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n    \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;\n   end\n   endgenerate // gnll_fifo\n\n   \n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n     generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid\n\n     \n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           fab_valid     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              fab_valid    <= #`TCQ 1'b0;\n           end else begin\n              if (ram_regout_en == 1'b1) begin\n                 fab_valid  <= #`TCQ 1'b1;\n              end else begin\n                 if (fab_regout_en == 1'b1)\n                   fab_valid <= #`TCQ 1'b0;\n                 else\n                   fab_valid <= #`TCQ fab_valid;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_fab_valid\n\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n    generate if(C_USE_EMBEDDED_REG == 3) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else begin\n        if (ram_regout_en == 1'b1) begin\n          read_data_valid_i <= #`TCQ 1'b1;\n        end else begin\n         if (fab_regout_en == 1'b1)\n          read_data_valid_i <= #`TCQ 1'b0;\n        else\n          read_data_valid_i <= #`TCQ read_data_valid_i;\n        end \n      end \n   end //always\nend\nendgenerate\n\n//generate if(C_USE_EMBEDDED_REG == 3) begin\n//   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n//      if (rd_rst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//      else if (srst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//\n//      if (ram_regout_en == 1'b1) begin\n//        fab_read_data_valid_i <= #`TCQ 1'b0;\n//      end else begin\n//       if (fab_regout_en == 1'b1)\n//        fab_read_data_valid_i <= #`TCQ 1'b1;\n//      else\n//        fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;\n//      end \n//   end //always\n//end\n//endgenerate\n\n     generate if(C_USE_EMBEDDED_REG == 3 ) begin \n    always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid\n      if (rd_rst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else \n        fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);\n   end //always\nend\nendgenerate\n \nalways @ (posedge RD_CLK ) begin : proc_del1\n             begin\n                 fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;\n              end\n            end //always\n \n \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty_both\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n   reg FIFOEMPTY_1;\n   generate if (C_USE_EMBEDDED_REG == 3 ) begin\n    always @(posedge RD_CLK) begin\n            FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;\n           end\n    end\nendgenerate\n    generate if (C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n   begin\n      if (rd_rst_i) begin         // asynchronous reset (active high)\n           almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ (~ram_valid_i);\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_sckt <= #`TCQ 1'b1;\n           sckt_rrst_q <= #`TCQ 1'b0;\n           sckt_rrst_done <= #`TCQ 1'b0;\n        end else begin\n           sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;\n           if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin\n              sckt_rrst_done <= #`TCQ 1'b1;\n           end else if (sckt_rrst_done) begin\n              // rising clock edge\n              empty_sckt <= #`TCQ 1'b0;\n           end\n        end\n     end //always\n   \n   \n//   assign USEREMPTY       = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;\n   assign USEREMPTY       = empty_i;\n   assign USERALMOSTEMPTY = almost_empty_i;\n   assign FIFORDEN        = ram_rd_en;\n   assign RAMVALID        = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;\n   assign uservalid_both       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3)  ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);\n   assign uservalid_one       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3)  ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);\n   assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;\n   assign USERUNDERFLOW   = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;\n//no safety ckt with both reg\ngenerate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n            USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              userdata_both   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end else begin\n            if (fwft_rst_done) begin\n              if (ram_regout_en) begin\n                 userdata_both     <= #`TCQ FIFODATA; \n                 user_dbiterr_both <= #`TCQ FIFODBITERR;\n                 user_sbiterr_both <= #`TCQ FIFOSBITERR; \n              end\n              if (fab_regout_en) begin\n                 USERDATA     <= #`TCQ userdata_both;\n                 USERDBITERR  <= #`TCQ user_dbiterr_both;\n                 USERSBITERR  <= #`TCQ user_sbiterr_both; \n              end             \n            end             \n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n\n//safety_ckt with both registers\n generate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always @ (posedge RD_CLK) begin\n          if (rd_rst_i || srst_i) begin\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n              @(posedge RD_CLK)\n              USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n               userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end\n        end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n     if (rd_rst_i) begin //asynchronous reset (active high)\n       if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n         USERSBITERR       <= #`TCQ 0;\n         USERDBITERR       <= #`TCQ 0;\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end\n       // DRAM resets asynchronously\n       if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n         USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end \n     end else begin // rising clock edge\n       if (srst_i) begin\n         if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n           USERSBITERR       <= #`TCQ 0;\n           USERDBITERR       <= #`TCQ 0;\n           user_sbiterr_both <= #`TCQ 0;\n           user_dbiterr_both <= #`TCQ 0;\n         end\n         if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n           USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end\n       end else if (fwft_rst_done) begin\n         if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            userdata_both     <= #`TCQ FIFODATA;\n            user_dbiterr_both <= #`TCQ FIFODBITERR;\n            user_sbiterr_both <= #`TCQ FIFOSBITERR; \n         end\n         if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            USERDATA          <= #`TCQ userdata_both;\n            USERDBITERR       <= #`TCQ user_dbiterr_both;\n            USERSBITERR       <= #`TCQ user_sbiterr_both;\n         end\n       end\n     end\n   end //always\n  end //if\nendgenerate\n\nendmodule //fifo_generator_v13_2_5_bhv_ver_preload0\n\n\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Register one AXI channel on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   reg_slice\n//\n//--------------------------------------------------------------------------\n\nmodule fifo_generator_v13_2_5_axic_reg_slice #\n  (\n   parameter C_FAMILY     = \"virtex7\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   )\n  (\n   // System Signals\n   input  wire                      ACLK,\n   input  wire                      ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0]   S_PAYLOAD_DATA,\n   input  wire                      S_VALID,\n   output wire                      S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0]   M_PAYLOAD_DATA,\n   output wire                      M_VALID,\n   input  wire                      M_READY\n   );\n\n  localparam RST_SYNC_STAGES = 5;\n  localparam RST_BUSY_LEN    = 6;\n  reg [1:0] arst_sync_wr  = 2'b11;\n  reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n  wire sync_reset;\n  wire extnd_reset;\n\n\n  always @(posedge ARESET or posedge ACLK) begin\n    if (ARESET)\n      arst_sync_wr <= 2'b11;\n    else\n      arst_sync_wr <= #`TCQ {arst_sync_wr[0], 1'b0};\n  end\n\n  always @(posedge ACLK) begin\n    sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[1]};\n  end\n\n  assign sync_reset     = |sckt_wr_rst_cc[RST_BUSY_LEN-5:0] | arst_sync_wr[1]; \n  assign extnd_reset    = |sckt_wr_rst_cc | arst_sync_wr[1];\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000)\n    begin\n      reg [1:0] state;\n      localparam [1:0] \n        ZERO = 2'b10,\n        ONE  = 2'b11,\n        TWO  = 2'b01;\n      \n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg [C_DATA_WIDTH-1:0] storage_data2 = 0;\n      reg                    load_s1;\n      wire                   load_s2;\n      wire                   load_s1_from_s2;\n      reg                    s_ready_i; //local signal of output\n      wire                   m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with either slave side data or from storage2\n      always @(posedge ACLK) \n      begin\n        if (load_s1)\n          if (load_s1_from_s2)\n            storage_data1 <= storage_data2;\n          else\n            storage_data1 <= S_PAYLOAD_DATA;        \n      end\n\n      // Load storage2 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data1;\n\n      // Always load s2 on a valid transaction even if it's unnecessary\n      assign load_s2 = S_VALID & s_ready_i;\n\n      // Loading s1\n      always @ *\n      begin\n        if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction\n             // Load when ONE if we both have read and write at the same time\n             ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||\n             // Load when TWO and we have a transaction on Master side\n             ((state == TWO) && (M_READY == 1)))\n          load_s1 = 1'b1;\n        else\n          load_s1 = 1'b0;\n      end // always @ *\n\n      assign load_s1_from_s2 = (state == TWO);\n                       \n      // State Machine for handling output signals\n      always @(posedge ACLK) begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          state <= ZERO;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          case (state)\n            // No transaction stored locally\n            ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE\n\n            // One transaction stored locally\n            ONE: begin\n              if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO\n              if (~M_READY & S_VALID) begin\n                state <= TWO;  // Got another one so move to TWO\n                s_ready_i <= 1'b0;\n              end\n            end\n\n            // TWO transaction stored locally\n            TWO: if (M_READY) begin\n              state <= ONE; // Read out one so move to ONE\n              s_ready_i <= 1'b1;\n            end\n          endcase // case (state)\n        end\n      end // always @ (posedge ACLK)\n      \n      assign m_valid_i = state[0];\n\n    end // if (C_REG_CONFIG == 1)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000001)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg                    s_ready_i; //local signal of output\n      reg                    m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b0;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else if (m_valid_i & M_READY) begin\n          s_ready_i <= 1'b1;\n          m_valid_i <= 1'b0;\n        end else if (S_VALID & s_ready_i) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b1;\n        end\n        if (~m_valid_i) begin\n          storage_data1 <= S_PAYLOAD_DATA;        \n        end\n      end\n      assign M_PAYLOAD_DATA = storage_data1;\n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // reg_slice\n", "num_lines": 10520}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sync_clock_converter\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_14_axic_sync_clock_converter # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_FAMILY     = \"virtex6\",\n  parameter integer C_PAYLOAD_WIDTH = 32,\n  parameter integer C_S_ACLK_RATIO = 1,\n  parameter integer C_M_ACLK_RATIO = 1 ,\n  parameter integer C_MODE = 0  // 0 = light-weight (1-deep); 1 = fully-pipelined (2-deep)\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input wire                    SAMPLE_CYCLE_EARLY,\n  input wire                    SAMPLE_CYCLE,\n  // Slave side\n  input  wire                        S_ACLK,\n  input  wire                        S_ARESETN,\n  input  wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD,\n  input  wire                        S_VALID,\n  output wire                        S_READY,\n\n  // Master side\n  input  wire                        M_ACLK,\n  input  wire                        M_ARESETN,\n  output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD,\n  output wire                        M_VALID,\n  input  wire                        M_READY\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam [1:0] ZERO = 2'b10;\nlocalparam [1:0] ONE  = 2'b11;\nlocalparam [1:0] TWO  = 2'b01;\nlocalparam [1:0] INIT = 2'b00;\nlocalparam integer P_LIGHT_WT = 0;\nlocalparam integer P_FULLY_REG = 1;\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\ngenerate\n  if (C_S_ACLK_RATIO == C_M_ACLK_RATIO) begin : gen_passthru\n    assign M_PAYLOAD = S_PAYLOAD;\n    assign M_VALID   = S_VALID;\n    assign S_READY   = M_READY;      \n  end else begin : gen_sync_clock_converter\n    wire s_sample_cycle;\n    wire s_sample_cycle_early;\n    wire m_sample_cycle;\n    wire m_sample_cycle_early;\n\n    wire slow_aclk;\n    wire slow_areset;\n    wire s_areset_r;\n    wire m_areset_r;\n   \n    reg  s_tready_r = 1'b0; \n    wire s_tready_ns; \n    reg  m_tvalid_r = 1'b0; \n    wire m_tvalid_ns; \n    reg  [C_PAYLOAD_WIDTH-1:0] m_tpayload_r;\n    reg  [C_PAYLOAD_WIDTH-1:0] m_tstorage_r;\n    wire [C_PAYLOAD_WIDTH-1:0] m_tpayload_ns; \n    wire [C_PAYLOAD_WIDTH-1:0] m_tstorage_ns; \n    reg  m_tready_hold = 1'b0;\n    wire m_tready_sample;\n    wire load_tpayload;\n    wire load_tstorage;\n    wire load_tpayload_from_tstorage;\n    reg [1:0] state = INIT;\n    reg [1:0] next_state;\n    \n    reg s_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge S_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        s_aresetn_r <= 1'b0;\n      end else begin\n        s_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign s_areset_r = ~s_aresetn_r;\n\n    reg m_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge M_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        m_aresetn_r <= 1'b0;\n      end else begin\n        m_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign m_areset_r = ~m_aresetn_r;\n\n    if (C_S_ACLK_RATIO > C_M_ACLK_RATIO) begin : gen_slowclk_mi\n      assign slow_aclk = M_ACLK;\n    end else begin : gen_slowclk_si\n      assign slow_aclk = S_ACLK;\n    end\n  \n    assign slow_areset = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? m_areset_r : s_areset_r;\n    assign s_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE_EARLY : 1'b1;\n    assign s_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE : 1'b1;\n    assign m_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE_EARLY;\n    assign m_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE;\n\n    // Output flop for S_READY, value is encoded into state machine.\n    assign s_tready_ns = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? state[1] & (state != INIT) : next_state[1];\n\n    always @(posedge S_ACLK) begin \n      if (s_areset_r) begin\n        s_tready_r <= 1'b0;\n      end\n      else begin\n        s_tready_r <= s_sample_cycle_early ? s_tready_ns : 1'b0;\n      end\n    end\n\n    assign S_READY = s_tready_r;\n\n    // Output flop for M_VALID\n    assign m_tvalid_ns = next_state[0];\n\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tvalid_r <= 1'b0;\n      end\n      else begin\n        m_tvalid_r <= m_sample_cycle ? m_tvalid_ns : m_tvalid_r & ~M_READY;\n      end\n    end\n\n    assign M_VALID = m_tvalid_r;\n\n    // Hold register for M_READY when M_ACLK is fast.\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tready_hold <= 1'b0;\n      end\n      else begin\n        m_tready_hold <= m_sample_cycle ? 1'b0 : m_tready_sample;\n      end\n    end\n\n    assign m_tready_sample = (M_READY ) | m_tready_hold;\n    // Output/storage flops for PAYLOAD\n    assign m_tpayload_ns = ~load_tpayload ? m_tpayload_r :\n                           load_tpayload_from_tstorage ? m_tstorage_r : \n                           S_PAYLOAD;\n\n    assign m_tstorage_ns = C_MODE ? (load_tstorage ? S_PAYLOAD : m_tstorage_r) : 0;\n\n    always @(posedge slow_aclk) begin \n      m_tpayload_r <= m_tpayload_ns;\n      m_tstorage_r <= C_MODE ? m_tstorage_ns : 0;\n    end\n\n    assign M_PAYLOAD = m_tpayload_r;\n\n    // load logic\n    assign load_tstorage = C_MODE && (state != TWO);\n    assign load_tpayload = m_tready_sample || (state == ZERO);\n    assign load_tpayload_from_tstorage = C_MODE && (state == TWO) && m_tready_sample;\n    \n    // State machine\n    always @(posedge slow_aclk) begin \n      state <= next_state;\n    end\n\n    always @* begin \n      if (slow_areset) begin \n        next_state = INIT;\n      end else begin\n        case (state)\n          INIT: begin\n            next_state = ZERO;\n          end\n          // No transaction stored locally\n          ZERO: begin\n            if (S_VALID) begin\n              next_state = C_MODE ? ONE : TWO; // Push from empty\n            end\n            else begin\n              next_state = ZERO;\n            end\n          end\n\n          // One transaction stored locally\n          ONE: begin\n            if (C_MODE == 0) begin\n              next_state = TWO;  // State ONE is inaccessible when C_MODE=0\n            end \n            else if (m_tready_sample & ~S_VALID) begin \n              next_state = ZERO; // Read out one so move to ZERO\n            end\n            else if (~m_tready_sample & S_VALID) begin\n              next_state = TWO;  // Got another one so move to TWO\n            end\n            else begin\n              next_state = ONE;\n            end\n          end\n\n          // Storage registers full\n          TWO: begin \n            if (m_tready_sample) begin\n              next_state = C_MODE ? ONE : ZERO; // Pop from full\n            end\n            else begin\n              next_state = TWO;\n            end\n          end\n        endcase // case (state)\n      end\n    end\n  end // gen_sync_clock_converter\n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sample_cycle_ratio\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_14_axic_sample_cycle_ratio # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_RATIO = 2 // Must be > 0\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    SLOW_ACLK,\n  input  wire                    FAST_ACLK,\n\n  output wire                    SAMPLE_CYCLE_EARLY,\n  output wire                    SAMPLE_CYCLE\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam P_DELAY = C_RATIO > 2 ? C_RATIO-1 : C_RATIO-1; \n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_aclk_div2 = 1'b0;\nreg                posedge_finder_first = 1'b0;\nreg                posedge_finder_second = 1'b0;\nwire               first_edge;\nwire               second_edge;\nwire               any_edge;\nreg  [P_DELAY-1:0] sample_cycle_d = {P_DELAY{1'b0}};\n(* shreg_extract = \"no\" *) reg                sample_cycle_r = 1'b0;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\ngenerate\n  if (C_RATIO == 1) begin : gen_always_sample\n    assign SAMPLE_CYCLE_EARLY = 1'b1;\n    assign SAMPLE_CYCLE = 1'b1;\n  end\n  else begin : gen_sample_cycle\n    genvar i;\n    always @(posedge SLOW_ACLK) begin \n      slow_aclk_div2 <= ~slow_aclk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_aclk_div2 onto faster clock\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_first <= slow_aclk_div2;\n    end\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_second <= ~slow_aclk_div2;\n    end\n\n    assign first_edge = slow_aclk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;\n    assign any_edge = first_edge | second_edge;\n   \n    // delay the posedge alignment by C_RATIO - 1 to set the sample cycle as\n    // the clock one cycle before the posedge.\n    for (i = P_DELAY-1; i > 0; i = i - 1) begin : gen_delay\n      always @(posedge FAST_ACLK) begin\n        if (i == P_DELAY-1) begin\n          sample_cycle_d[i-1] <= any_edge;\n        end else begin\n          sample_cycle_d[i-1] <= sample_cycle_d[i];\n        end\n      end\n    end\n\n    always @(posedge FAST_ACLK) begin \n      sample_cycle_r <= (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    end\n    assign SAMPLE_CYCLE_EARLY = (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    assign SAMPLE_CYCLE = sample_cycle_r;\n  end\nendgenerate\n\nendmodule // axisc_sample_cycle_ratio\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2010 - 2016 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and\n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Clock converter module\n//   Asynchronous clock converter when asynchronous M:N conversion\n//   Bypass when synchronous and ratio between S and M clock is 1:1\n//   Synchronous clock converter (S:M or M:S must be integer ratio)\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_clock_conv\n//     fifo_generator\n//     axic_sync_clock_converter\n//       axic_sample_cycle_ratio\n//\n// PROTECTED NAMES:\n//   Instance names \"asyncfifo_*\" are pattern-matched in core-level UCF.\n//   Signal names \"*_resync\" are pattern-matched in core-level UCF.\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_14_lite_async #(\n  parameter integer C_DEST_SYNC_FF = 2,\n  parameter integer C_SRC_SYNC_FF  = 2,\n  parameter integer C_WIDTH        = 1\n) (\n  input wire                s_aclk,\n  input wire                m_aclk,\n  input wire                s_aresetn,\n  input wire                m_aresetn,\n  input wire                s_valid,\n  output wire                s_ready,\n  input wire [C_WIDTH-1:0]  s_payld,\n  output wire                m_valid,\n  input wire                m_ready,\n  output wire [C_WIDTH-1:0] m_payld\n);\n\nreg                s_ready_i = 1'b0;\nreg                m_valid_i = 1'b0;\nreg   src_send = 1'b0;\nreg   dest_ack = 1'b0;\nwire  src_rcv;\nwire  dest_req;\n\nassign s_ready = s_ready_i;\nassign m_valid = m_valid_i;\n\nlocalparam SRC_IDLE           = 2'b00;\nlocalparam SRC_DRV_SEND       = 2'b01;\nlocalparam SRC_WAIT_RCV_DONE  = 2'b10;\nreg [1:0] src_state = SRC_IDLE;\n\nalways @(posedge s_aclk) begin\n  if (s_aresetn == 1'b0) begin\n    s_ready_i <= 1'b0;\n    src_send <= 1'b0;\n    src_state <= SRC_IDLE;\n  end else begin\n    case (src_state)\n      SRC_IDLE: begin\n        if (s_valid) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end\n      end\n      SRC_DRV_SEND: begin\n        if (src_rcv) begin\n          s_ready_i <= 1'b1;\n          src_send <= 1'b0;\n          src_state <= SRC_WAIT_RCV_DONE;\n        end\n      end\n      SRC_WAIT_RCV_DONE: begin\n        s_ready_i <= 1'b0;\n        if (s_valid & !src_rcv) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end else if (!src_rcv) begin\n          src_state <= SRC_IDLE;\n        end\n      end\n      default: begin\n        s_ready_i <= 1'b0;\n        src_send <= 1'b0;\n        src_state <= SRC_IDLE;\n      end\n    endcase\n  end\nend\n\nlocalparam DEST_IDLE           = 2'b00;\nlocalparam DEST_DRV_VALID      = 2'b01;\nlocalparam DEST_DRV_ACK        = 2'b10;\nreg [1:0] dest_state = DEST_IDLE;\n\nalways @(posedge m_aclk) begin\n  if (m_aresetn == 1'b0) begin\n    m_valid_i <= 1'b0;\n    dest_ack <= 1'b0;\n    dest_state <= DEST_IDLE;\n  end else begin\n    case (dest_state)\n      DEST_IDLE: begin\n        if (dest_req) begin\n          dest_state <= DEST_DRV_VALID;\n          m_valid_i <= 1'b1;\n        end else begin\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b0;\n        end\n      end\n      DEST_DRV_VALID: begin\n        if (m_ready & m_valid_i) begin\n          dest_state <= DEST_DRV_ACK;\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b1;\n        end\n      end\n      DEST_DRV_ACK: begin\n        if (!dest_req) begin\n          dest_state <= DEST_IDLE;\n          dest_ack <= 1'b0;\n        end\n      end\n      default: begin\n        m_valid_i <= 1'b0;\n        dest_ack <= 1'b0;\n        dest_state <= DEST_IDLE;\n      end\n    endcase\n  end\nend\n\nxpm_cdc_handshake #(\n  .DEST_SYNC_FF   (C_DEST_SYNC_FF),\n  .SRC_SYNC_FF    (C_SRC_SYNC_FF),\n  .WIDTH          (C_WIDTH)\n) handshake (\n  .src_clk  (s_aclk),\n  .src_in   (s_payld),\n  .src_send (src_send),\n  .src_rcv  (src_rcv),\n  .dest_clk (m_aclk),\n  .dest_out (m_payld),\n  .dest_req (dest_req),\n  .dest_ack (dest_ack)\n);\n\nendmodule\n\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_14_axi_clock_converter #\n  (parameter         C_FAMILY = \"virtex7\",\n   parameter integer C_AXI_ID_WIDTH = 5,                    // Width of all ID signals on SI and MI side.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ADDR_WIDTH = 32,                 // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and\n                                                            // m_axi_araddr.\n                                                            // Range: 32.\n   parameter integer C_AXI_DATA_WIDTH = 32,       // Width of WDATA and RDATA (either side).\n                                                            // Format: Bit32;\n                                                            // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.\n   parameter integer C_S_AXI_ACLK_RATIO = 1,     // Clock frequency ratio of SI w.r.t. MI.\n   parameter integer C_M_AXI_ACLK_RATIO = 1,     // (Slowest of all clock inputs should have ratio=1.)\n                                                            // S:M or M:S must be integer ratio.\n                                                            // Format: Bit32; Range: >='h00000001.\n   parameter integer C_AXI_IS_ACLK_ASYNC = 1,            // Indicates whether S and M clocks are asynchronous.\n                                                            // FUTURE FEATURE\n                                                            // Format: Bit1. Range = 1'b0.\n   parameter integer C_AXI_PROTOCOL = 0,         // Protocol of this SI/MI slot.\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS  = 1,      // 1 = Propagate all USER signals, 0 = Do not propagate.\n   parameter integer C_AXI_AWUSER_WIDTH = 1,                // Width of AWUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ARUSER_WIDTH = 1,                // Width of ARUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_WUSER_WIDTH = 1,                 // Width of WUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_RUSER_WIDTH = 1,                 // Width of RUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_BUSER_WIDTH = 1,                 // Width of BUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,              // Implement AXI write channels\n   parameter integer C_AXI_SUPPORTS_READ = 1,               // Implement AXI read channels\n   parameter integer C_SYNCHRONIZER_STAGE = 3\n  )\n\n  (\n   // Slave Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n   input  wire [4-1:0]                    s_axi_awcache,\n   input  wire [3-1:0]                    s_axi_awprot,\n   input  wire [4-1:0]                    s_axi_awregion,\n   input  wire [4-1:0]                    s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0]   s_axi_awuser,\n   input  wire                            s_axi_awvalid,\n   output wire                            s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n   input  wire                            s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]    s_axi_wuser,\n   input  wire                            s_axi_wvalid,\n   output wire                            s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_bid,\n   output wire [2-1:0]                    s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0]    s_axi_buser,\n   output wire                            s_axi_bvalid,\n   input  wire                            s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n   input  wire [3-1:0]                    s_axi_arsize,\n   input  wire [2-1:0]                    s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n   input  wire [4-1:0]                    s_axi_arcache,\n   input  wire [3-1:0]                    s_axi_arprot,\n   input  wire [4-1:0]                    s_axi_arregion,\n   input  wire [4-1:0]                    s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0]   s_axi_aruser,\n   input  wire                            s_axi_arvalid,\n   output wire                            s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n   output wire [2-1:0]                    s_axi_rresp,\n   output wire                            s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0]    s_axi_ruser,\n   output wire                            s_axi_rvalid,\n   input  wire                            s_axi_rready,\n\n   // Master Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aresetn,\n\n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n   output wire [3-1:0]                    m_axi_awsize,\n   output wire [2-1:0]                    m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n   output wire [4-1:0]                    m_axi_awcache,\n   output wire [3-1:0]                    m_axi_awprot,\n   output wire [4-1:0]                    m_axi_awregion,\n   output wire [4-1:0]                    m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0]   m_axi_awuser,\n   output wire                            m_axi_awvalid,\n   input  wire                            m_axi_awready,\n\n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0]   m_axi_wstrb,\n   output wire                            m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]    m_axi_wuser,\n   output wire                            m_axi_wvalid,\n   input  wire                            m_axi_wready,\n\n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_bid,\n   input  wire [2-1:0]                    m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0]    m_axi_buser,\n   input  wire                            m_axi_bvalid,\n   output wire                            m_axi_bready,\n\n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n   output wire [3-1:0]                    m_axi_arsize,\n   output wire [2-1:0]                    m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n   output wire [4-1:0]                    m_axi_arcache,\n   output wire [3-1:0]                    m_axi_arprot,\n   output wire [4-1:0]                    m_axi_arregion,\n   output wire [4-1:0]                    m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0]   m_axi_aruser,\n   output wire                            m_axi_arvalid,\n   input  wire                            m_axi_arready,\n\n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     m_axi_rdata,\n   input  wire [2-1:0]                    m_axi_rresp,\n   input  wire                            m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0]    m_axi_ruser,\n   input  wire                            m_axi_rvalid,\n   output wire                            m_axi_rready);\n\n  localparam integer P_AXI4 = 0;\n  localparam integer P_AXI3 = 1;\n  localparam integer P_AXILITE = 2;\n  localparam integer P_LIGHT_WT = 0;\n  localparam integer P_FULLY_REG = 1;\n  localparam integer P_LUTRAM_ASYNC = 12;\n\n  // Sample cycle ratio\n  localparam  P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);\n  localparam integer P_ROUNDING_OFFSET = P_SI_LT_MI ? (C_S_AXI_ACLK_RATIO/2) : (C_M_AXI_ACLK_RATIO/2);\n  localparam integer P_ACLK_RATIO = P_SI_LT_MI ?\n    ((C_M_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_S_AXI_ACLK_RATIO) :\n    ((C_S_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_M_AXI_ACLK_RATIO);\n\n  // Write Address Port bit positions\n  localparam integer C_AWUSER_RIGHT   = 0;\n  localparam integer C_AWUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_AWUSER_WIDTH : 0;\n  localparam integer C_AWQOS_RIGHT    = C_AWUSER_RIGHT + C_AWUSER_WIDTH;\n  localparam integer C_AWQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWREGION_RIGHT = C_AWQOS_RIGHT + C_AWQOS_WIDTH;\n  localparam integer C_AWREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_AWPROT_RIGHT   = C_AWREGION_RIGHT + C_AWREGION_WIDTH;\n  localparam integer C_AWPROT_WIDTH     = 3;\n  localparam integer C_AWCACHE_RIGHT  = C_AWPROT_RIGHT + C_AWPROT_WIDTH;\n  localparam integer C_AWCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWLOCK_RIGHT   = C_AWCACHE_RIGHT + C_AWCACHE_WIDTH;\n  localparam integer C_AWLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_AWBURST_RIGHT  = C_AWLOCK_RIGHT + C_AWLOCK_WIDTH;\n  localparam integer C_AWBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_AWSIZE_RIGHT   = C_AWBURST_RIGHT + C_AWBURST_WIDTH;\n  localparam integer C_AWSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_AWLEN_RIGHT    = C_AWSIZE_RIGHT + C_AWSIZE_WIDTH;\n  localparam integer C_AWLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_AWADDR_RIGHT   = C_AWLEN_RIGHT + C_AWLEN_WIDTH;\n  localparam integer C_AWADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_AWID_RIGHT     = C_AWADDR_RIGHT + C_AWADDR_WIDTH;\n  localparam integer C_AWID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AW_WIDTH        = C_AWID_RIGHT + C_AWID_WIDTH;\n  localparam integer C_FIFO_AW_WIDTH   = C_AWUSER_WIDTH+C_AWQOS_WIDTH+C_AWQOS_WIDTH+3+C_AWCACHE_WIDTH+C_AWLOCK_WIDTH+C_AWBURST_WIDTH+C_AWSIZE_WIDTH+C_AWLEN_WIDTH+C_AXI_ADDR_WIDTH+C_AWID_WIDTH;\n\n  // Write Data Port bit positions\n  localparam integer C_WUSER_RIGHT   = 0;\n  localparam integer C_WUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_WUSER_WIDTH : 0;\n  localparam integer C_WLAST_RIGHT   = C_WUSER_RIGHT + C_WUSER_WIDTH;\n  localparam integer C_WLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_WSTRB_RIGHT   = C_WLAST_RIGHT + C_WLAST_WIDTH;\n  localparam integer C_WSTRB_WIDTH     = C_AXI_DATA_WIDTH/8;\n  localparam integer C_WDATA_RIGHT   = C_WSTRB_RIGHT + C_WSTRB_WIDTH;\n  localparam integer C_WDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_WID_RIGHT     = C_WDATA_RIGHT + C_WDATA_WIDTH;\n  localparam integer C_WID_WIDTH       = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_W_WIDTH        = C_WID_RIGHT + C_WID_WIDTH;\n  localparam integer C_FIFO_W_WIDTH   = C_WUSER_WIDTH + C_WLAST_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_DATA_WIDTH + C_WID_WIDTH;\n\n  // Write Response Port bit positions\n  localparam integer C_BUSER_RIGHT   = 0;\n  localparam integer C_BUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_BUSER_WIDTH : 0;\n  localparam integer C_BRESP_RIGHT   = C_BUSER_RIGHT + C_BUSER_WIDTH;\n  localparam integer C_BRESP_WIDTH     = 2;\n  localparam integer C_BID_RIGHT     = C_BRESP_RIGHT + C_BRESP_WIDTH;\n  localparam integer C_BID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_B_WIDTH        = C_BID_RIGHT + C_BID_WIDTH;\n  localparam integer C_FIFO_B_WIDTH    = C_BUSER_WIDTH + 2 + C_BID_WIDTH;\n\n  // Read Address Port bit positions\n  localparam integer C_ARUSER_RIGHT   = 0;\n  localparam integer C_ARUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_ARUSER_WIDTH : 0;\n  localparam integer C_ARQOS_RIGHT    = C_ARUSER_RIGHT + C_ARUSER_WIDTH;\n  localparam integer C_ARQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARREGION_RIGHT = C_ARQOS_RIGHT + C_ARQOS_WIDTH;\n  localparam integer C_ARREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_ARPROT_RIGHT   = C_ARREGION_RIGHT + C_ARREGION_WIDTH;\n  localparam integer C_ARPROT_WIDTH     = 3;\n  localparam integer C_ARCACHE_RIGHT  = C_ARPROT_RIGHT + C_ARPROT_WIDTH;\n  localparam integer C_ARCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARLOCK_RIGHT   = C_ARCACHE_RIGHT + C_ARCACHE_WIDTH;\n  localparam integer C_ARLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_ARBURST_RIGHT  = C_ARLOCK_RIGHT + C_ARLOCK_WIDTH;\n  localparam integer C_ARBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_ARSIZE_RIGHT   = C_ARBURST_RIGHT + C_ARBURST_WIDTH;\n  localparam integer C_ARSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_ARLEN_RIGHT    = C_ARSIZE_RIGHT + C_ARSIZE_WIDTH;\n  localparam integer C_ARLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_ARADDR_RIGHT   = C_ARLEN_RIGHT + C_ARLEN_WIDTH;\n  localparam integer C_ARADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_ARID_RIGHT     = C_ARADDR_RIGHT + C_ARADDR_WIDTH;\n  localparam integer C_ARID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AR_WIDTH        = C_ARID_RIGHT + C_ARID_WIDTH;\n  localparam integer C_FIFO_AR_WIDTH   = C_ARUSER_WIDTH+C_ARQOS_WIDTH+C_ARQOS_WIDTH+3+C_ARCACHE_WIDTH+C_ARLOCK_WIDTH+C_ARBURST_WIDTH+C_ARSIZE_WIDTH+C_ARLEN_WIDTH+C_AXI_ADDR_WIDTH+C_ARID_WIDTH;\n\n  // Read Data Ports bit positions\n  localparam integer C_RUSER_RIGHT   = 0;\n  localparam integer C_RUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_RUSER_WIDTH : 0;\n  localparam integer C_RLAST_RIGHT   = C_RUSER_RIGHT + C_RUSER_WIDTH;\n  localparam integer C_RLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_RRESP_RIGHT   = C_RLAST_RIGHT + C_RLAST_WIDTH;\n  localparam integer C_RRESP_WIDTH     = 2;\n  localparam integer C_RDATA_RIGHT   = C_RRESP_RIGHT + C_RRESP_WIDTH;\n  localparam integer C_RDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_RID_RIGHT     = C_RDATA_RIGHT + C_RDATA_WIDTH;\n  localparam integer C_RID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_R_WIDTH        = C_RID_RIGHT + C_RID_WIDTH;\n  localparam integer C_FIFO_R_WIDTH   = C_RUSER_WIDTH + C_RLAST_WIDTH + 2 + C_AXI_DATA_WIDTH + C_RID_WIDTH;\n\n  generate\n    if ((C_AXI_IS_ACLK_ASYNC == 0) && (P_ACLK_RATIO == 1)) begin : gen_bypass\n      \n      // Write address port\n      assign m_axi_awid     = s_axi_awid;\n      assign m_axi_awaddr   = s_axi_awaddr;\n      assign m_axi_awlen    = s_axi_awlen;\n      assign m_axi_awsize   = s_axi_awsize;\n      assign m_axi_awburst  = s_axi_awburst;\n      assign m_axi_awlock   = s_axi_awlock;\n      assign m_axi_awcache  = s_axi_awcache;\n      assign m_axi_awprot   = s_axi_awprot;\n      assign m_axi_awregion = s_axi_awregion;\n      assign m_axi_awqos    = s_axi_awqos;\n      assign m_axi_awuser   = s_axi_awuser;\n      assign m_axi_awvalid  = s_axi_awvalid;\n      assign s_axi_awready  = m_axi_awready;\n\n      // Write Data Port\n      assign m_axi_wid      = s_axi_wid;\n      assign m_axi_wdata    = s_axi_wdata;\n      assign m_axi_wstrb    = s_axi_wstrb;\n      assign m_axi_wlast    = s_axi_wlast;\n      assign m_axi_wuser    = s_axi_wuser;\n      assign m_axi_wvalid   = s_axi_wvalid;\n      assign s_axi_wready   = m_axi_wready;\n\n      // Write Response Port\n      assign s_axi_bid      = m_axi_bid;\n      assign s_axi_bresp    = m_axi_bresp;\n      assign s_axi_buser    = m_axi_buser;\n      assign s_axi_bvalid   = m_axi_bvalid;\n      assign m_axi_bready   = s_axi_bready;\n\n      // Read Address Port\n      assign m_axi_arid     = s_axi_arid;\n      assign m_axi_araddr   = s_axi_araddr;\n      assign m_axi_arlen    = s_axi_arlen;\n      assign m_axi_arsize   = s_axi_arsize;\n      assign m_axi_arburst  = s_axi_arburst;\n      assign m_axi_arlock   = s_axi_arlock;\n      assign m_axi_arcache  = s_axi_arcache;\n      assign m_axi_arprot   = s_axi_arprot;\n      assign m_axi_arregion = s_axi_arregion;\n      assign m_axi_arqos    = s_axi_arqos;\n      assign m_axi_aruser   = s_axi_aruser;\n      assign m_axi_arvalid  = s_axi_arvalid;\n      assign s_axi_arready  = m_axi_arready;\n\n      // Read Data Port\n      assign s_axi_rid      = m_axi_rid;\n      assign s_axi_rdata    = m_axi_rdata;\n      assign s_axi_rresp    = m_axi_rresp;\n      assign s_axi_rlast    = m_axi_rlast;\n      assign s_axi_ruser    = m_axi_ruser;\n      assign s_axi_rvalid   = m_axi_rvalid;\n      assign m_axi_rready   = s_axi_rready;\n      \n    end else begin : gen_clock_conv\n      \n      wire fast_aclk;\n      wire slow_aclk;\n      wire sample_cycle;\n      wire sample_cycle_early;\n    \n      // Write Address Port FIFO data read and write\n      wire [C_AW_WIDTH-1:0] s_aw_mesg ;\n      wire [C_AW_WIDTH-1:0] m_aw_mesg ;\n    \n      // Write Data Port FIFO data read and write\n      wire [C_W_WIDTH-1:0] s_w_mesg;\n      wire [C_W_WIDTH-1:0] m_w_mesg;\n    \n      // Write Response Port FIFO data read and write\n      wire [C_B_WIDTH-1:0] s_b_mesg;\n      wire [C_B_WIDTH-1:0] m_b_mesg;\n    \n      // Read Address Port FIFO data read and write\n      wire [C_AR_WIDTH-1:0] s_ar_mesg;\n      wire [C_AR_WIDTH-1:0] m_ar_mesg;\n    \n      // Read Data Ports FIFO data read and write\n      wire [C_R_WIDTH-1:0] s_r_mesg;\n      wire [C_R_WIDTH-1:0] m_r_mesg;\n    \n      wire async_conv_reset_n;\n      assign async_conv_reset_n = ~(~s_axi_aresetn | ~m_axi_aresetn);\n      \n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_awlen           ;\n      wire [3-1:0]                       si_cc_awsize          ;\n      wire [2-1:0]                       si_cc_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_awlock          ;\n      wire [4-1:0]                       si_cc_awcache         ;\n      wire [3-1:0]                       si_cc_awprot          ;\n      wire [4-1:0]                       si_cc_awregion        ;\n      wire [4-1:0]                       si_cc_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]      si_cc_awuser          ;\n      wire                               si_cc_awvalid         ;\n      wire                               si_cc_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_wid            ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]      si_cc_wstrb           ;\n      wire                               si_cc_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]       si_cc_wuser           ;\n      wire                               si_cc_wvalid          ;\n      wire                               si_cc_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_bid             ;\n      wire [2-1:0]                       si_cc_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]       si_cc_buser           ;\n      wire                               si_cc_bvalid          ;\n      wire                               si_cc_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_arlen           ;\n      wire [3-1:0]                       si_cc_arsize          ;\n      wire [2-1:0]                       si_cc_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_arlock          ;\n      wire [4-1:0]                       si_cc_arcache         ;\n      wire [3-1:0]                       si_cc_arprot          ;\n      wire [4-1:0]                       si_cc_arregion        ;\n      wire [4-1:0]                       si_cc_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]      si_cc_aruser          ;\n      wire                               si_cc_arvalid         ;\n      wire                               si_cc_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_rdata           ;\n      wire [2-1:0]                       si_cc_rresp           ;\n      wire                               si_cc_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]       si_cc_ruser           ;\n      wire                               si_cc_rvalid          ;\n      wire                               si_cc_rready          ;\n      \n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_awlen           ;\n      wire [3-1:0]                      cc_mi_awsize          ;\n      wire [2-1:0]                      cc_mi_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_awlock          ;\n      wire [4-1:0]                      cc_mi_awcache         ;\n      wire [3-1:0]                      cc_mi_awprot          ;\n      wire [4-1:0]                      cc_mi_awregion        ;\n      wire [4-1:0]                      cc_mi_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]     cc_mi_awuser          ;\n      wire                              cc_mi_awvalid         ;\n      wire                              cc_mi_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_wid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]     cc_mi_wstrb           ;\n      wire                              cc_mi_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]      cc_mi_wuser           ;\n      wire                              cc_mi_wvalid          ;\n      wire                              cc_mi_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_bid             ;\n      wire [2-1:0]                      cc_mi_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]      cc_mi_buser           ;\n      wire                              cc_mi_bvalid          ;\n      wire                              cc_mi_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_arlen           ;\n      wire [3-1:0]                      cc_mi_arsize          ;\n      wire [2-1:0]                      cc_mi_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_arlock          ;\n      wire [4-1:0]                      cc_mi_arcache         ;\n      wire [3-1:0]                      cc_mi_arprot          ;\n      wire [4-1:0]                      cc_mi_arregion        ;\n      wire [4-1:0]                      cc_mi_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]     cc_mi_aruser          ;\n      wire                              cc_mi_arvalid         ;\n      wire                              cc_mi_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_rdata           ;\n      wire [2-1:0]                      cc_mi_rresp           ;\n      wire                              cc_mi_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]      cc_mi_ruser           ;\n      wire                              cc_mi_rvalid          ;\n      wire                              cc_mi_rready          ;\n      \n    // Tie-offs\n      assign si_cc_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awid : 0 ;\n      assign si_cc_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awaddr : 0 ;\n      assign si_cc_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_awlen : {4'b0000, s_axi_awlen[3:0]}) : 0 ;\n      assign si_cc_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize : 0 ;\n      assign si_cc_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst : 0 ;\n      assign si_cc_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_awlock : {1'b0, s_axi_awlock[0]}) : 0 ;\n      assign si_cc_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache : 0 ;\n      assign si_cc_awprot    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awprot : 0 ;\n      assign si_cc_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos : 0 ;\n      assign si_cc_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion : 0 ;\n      assign si_cc_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser : 0 ;\n      assign si_cc_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awvalid : 0 ;\n      assign si_cc_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? s_axi_wid : 0 ;\n      assign si_cc_wdata     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wdata : 0 ;\n      assign si_cc_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wstrb : 0 ;\n      assign si_cc_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast : 1'b0 ;\n      assign si_cc_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser : 0 ;\n      assign si_cc_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wvalid : 0 ;\n      assign si_cc_bready    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_bready : 0 ;\n      assign si_cc_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arid : 0 ;\n      assign si_cc_araddr    = (C_AXI_SUPPORTS_READ ) ? s_axi_araddr : 0 ;\n      assign si_cc_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_arlen : {4'b0000, s_axi_arlen[3:0]}) : 0 ;\n      assign si_cc_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize : 0 ;\n      assign si_cc_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst : 0 ;\n      assign si_cc_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_arlock : {1'b0, s_axi_arlock[0]}) : 0 ;\n      assign si_cc_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache : 0 ;\n      assign si_cc_arprot    = (C_AXI_SUPPORTS_READ ) ? s_axi_arprot : 0 ;\n      assign si_cc_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos : 0 ;\n      assign si_cc_arregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion : 0 ;\n      assign si_cc_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser : 0 ;\n      assign si_cc_arvalid   = (C_AXI_SUPPORTS_READ ) ? s_axi_arvalid : 0 ;\n      assign si_cc_rready    = (C_AXI_SUPPORTS_READ ) ? s_axi_rready : 0 ;                                       \n                                                                                               \n      assign s_axi_awready   = (C_AXI_SUPPORTS_WRITE ) ? si_cc_awready : 0 ;\n      assign s_axi_wready    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_wready : 0 ;\n      assign s_axi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_bid : 0 ;\n      assign s_axi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bresp : 0 ;\n      assign s_axi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_buser : 0 ;\n      assign s_axi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bvalid : 0 ;\n      assign s_axi_arready   = (C_AXI_SUPPORTS_READ ) ? si_cc_arready : 0 ;\n      assign s_axi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rid : 0 ;\n      assign s_axi_rdata     = (C_AXI_SUPPORTS_READ ) ? si_cc_rdata : 0 ;\n      assign s_axi_rresp     = (C_AXI_SUPPORTS_READ ) ? si_cc_rresp : 0 ;\n      assign s_axi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rlast : 0 ;\n      assign s_axi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_ruser : 0 ;\n      assign s_axi_rvalid    = (C_AXI_SUPPORTS_READ ) ? si_cc_rvalid : 0 ;\n\n      assign m_axi_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awid : 0 ;\n      assign m_axi_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awaddr : 0 ;\n      assign m_axi_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_awlen : cc_mi_awlen[3:0]) : 0 ;\n      assign m_axi_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awsize : 0 ;\n      assign m_axi_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awburst : 0 ;\n      assign m_axi_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_awlock : cc_mi_awlock[0]) : 0 ;\n      assign m_axi_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awcache : 0 ;\n      assign m_axi_awprot    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awprot : 0 ;\n      assign m_axi_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_awregion : 0 ;\n      assign m_axi_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awqos : 0 ;\n      assign m_axi_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_awuser : 0 ;\n      assign m_axi_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awvalid : 0 ;\n      assign m_axi_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? cc_mi_wid : 0 ;\n      assign m_axi_wdata     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wdata : 0 ;\n      assign m_axi_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wstrb : 0 ;\n      assign m_axi_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_wlast : 0 ;\n      assign m_axi_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_wuser : 0 ;\n      assign m_axi_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wvalid : 0 ;\n      assign m_axi_bready    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_bready : 0 ;\n      assign m_axi_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arid : 0 ;\n      assign m_axi_araddr    = (C_AXI_SUPPORTS_READ ) ? cc_mi_araddr : 0 ;\n      assign m_axi_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_arlen : cc_mi_arlen[3:0]) : 0 ;\n      assign m_axi_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arsize : 0 ;\n      assign m_axi_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arburst : 0 ;\n      assign m_axi_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_arlock : cc_mi_arlock[0]) : 0 ;\n      assign m_axi_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arcache : 0 ;\n      assign m_axi_arprot    = (C_AXI_SUPPORTS_READ ) ? cc_mi_arprot : 0 ;\n      assign m_axi_arregion  = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_arregion : 0 ;\n      assign m_axi_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arqos : 0 ;\n      assign m_axi_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_aruser : 0 ;\n      assign m_axi_arvalid   = (C_AXI_SUPPORTS_READ ) ? cc_mi_arvalid : 0 ;\n      assign m_axi_rready    = (C_AXI_SUPPORTS_READ ) ? cc_mi_rready : 0 ;\n                                                                                                                                                                                                                                                                                        \n      assign cc_mi_awready   = (C_AXI_SUPPORTS_WRITE ) ? m_axi_awready : 0 ;\n      assign cc_mi_wready    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_wready : 0 ;\n      assign cc_mi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid : 0 ;\n      assign cc_mi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bresp : 0 ;\n      assign cc_mi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser : 0 ;\n      assign cc_mi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bvalid : 0 ;\n      assign cc_mi_arready   = (C_AXI_SUPPORTS_READ ) ? m_axi_arready : 0 ;\n      assign cc_mi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid : 0 ;\n      assign cc_mi_rdata     = (C_AXI_SUPPORTS_READ ) ? m_axi_rdata : 0 ;\n      assign cc_mi_rresp     = (C_AXI_SUPPORTS_READ ) ? m_axi_rresp : 0 ;\n      assign cc_mi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast : 1'b0 ;\n      assign cc_mi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser : 0 ;\n      assign cc_mi_rvalid    = (C_AXI_SUPPORTS_READ ) ? m_axi_rvalid : 0 ;\n      \n      if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL!=P_AXILITE)) begin : gen_async_conv\n        \n        fifo_generator_v13_2_1 #(\n          .C_EN_SAFETY_CKT(0),\n          .C_SELECT_XPM(0),\n          .C_INTERFACE_TYPE(2),\n          .C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ? 3 : 2),\n          .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n          .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n          .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n          .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n          .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n          .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),\n          .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n          .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n          .C_HAS_AXI_ID((C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0),\n          .C_AXI_LEN_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 8 : 4),\n          .C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 1 : 2),\n          .C_HAS_AXI_ARUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_AWUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_BUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_RUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_WUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_DIN_WIDTH_RACH(C_FIFO_AR_WIDTH),\n          .C_DIN_WIDTH_RDCH(C_FIFO_R_WIDTH),\n          .C_DIN_WIDTH_WACH(C_FIFO_AW_WIDTH),\n          .C_DIN_WIDTH_WDCH(C_FIFO_W_WIDTH),\n          .C_DIN_WIDTH_WRCH(C_FIFO_B_WIDTH),\n          .C_HAS_AXI_RD_CHANNEL(C_AXI_SUPPORTS_READ),\n          .C_HAS_AXI_WR_CHANNEL(C_AXI_SUPPORTS_WRITE),\n          .C_RACH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_RDCH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_WACH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WDCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WRCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),\n          .C_COMMON_CLOCK(0),\n          .C_COUNT_TYPE(0),\n          .C_DATA_COUNT_WIDTH(10),\n          .C_DEFAULT_VALUE(\"BlankString\"),\n          .C_DIN_WIDTH(18),\n          .C_DOUT_RST_VAL(\"0\"),\n          .C_DOUT_WIDTH(18),\n          .C_ENABLE_RLOCS(0),\n          .C_FAMILY(C_FAMILY),\n          .C_FULL_FLAGS_RST_VAL(1),\n          .C_HAS_ALMOST_EMPTY(0),\n          .C_HAS_ALMOST_FULL(0),\n          .C_HAS_BACKUP(0),\n          .C_HAS_DATA_COUNT(0),\n          .C_HAS_INT_CLK(0),\n          .C_HAS_MEMINIT_FILE(0),\n          .C_HAS_OVERFLOW(0),\n          .C_HAS_RD_DATA_COUNT(0),\n          .C_HAS_RD_RST(0),\n          .C_HAS_RST(1),\n          .C_HAS_SRST(0),\n          .C_HAS_UNDERFLOW(0),\n          .C_HAS_VALID(0),\n          .C_HAS_WR_ACK(0),\n          .C_HAS_WR_DATA_COUNT(0),\n          .C_HAS_WR_RST(0),\n          .C_IMPLEMENTATION_TYPE(0),\n          .C_INIT_WR_PNTR_VAL(0),\n          .C_MEMORY_TYPE(1),\n          .C_MIF_FILE_NAME(\"BlankString\"),\n          .C_OPTIMIZATION_MODE(0),\n          .C_OVERFLOW_LOW(0),\n          .C_PRELOAD_LATENCY(1),\n          .C_PRELOAD_REGS(0),\n          .C_PRIM_FIFO_TYPE(\"4kx4\"),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),\n          .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),\n          .C_PROG_EMPTY_TYPE(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL(1022),\n          .C_PROG_FULL_THRESH_NEGATE_VAL(1021),\n          .C_PROG_FULL_TYPE(0),\n          .C_RD_DATA_COUNT_WIDTH(10),\n          .C_RD_DEPTH(1024),\n          .C_RD_FREQ(1),\n          .C_RD_PNTR_WIDTH(10),\n          .C_UNDERFLOW_LOW(0),\n          .C_USE_DOUT_RST(1),\n          .C_USE_ECC(0),\n          .C_USE_EMBEDDED_REG(0),\n          .C_USE_FIFO16_FLAGS(0),\n          .C_USE_FWFT_DATA_COUNT(0),\n          .C_VALID_LOW(0),\n          .C_WR_ACK_LOW(0),\n          .C_WR_DATA_COUNT_WIDTH(10),\n          .C_WR_DEPTH(1024),\n          .C_WR_FREQ(1),\n          .C_WR_PNTR_WIDTH(10),\n          .C_WR_RESPONSE_LATENCY(1),\n          .C_MSGON_VAL(1),\n          .C_ENABLE_RST_SYNC(1),\n          .C_ERROR_INJECTION_TYPE(0),\n          .C_HAS_SLAVE_CE(0),\n          .C_HAS_MASTER_CE(0),\n          .C_ADD_NGC_CONSTRAINT(0),\n          .C_USE_COMMON_OVERFLOW(0),\n          .C_USE_COMMON_UNDERFLOW(0),\n          .C_USE_DEFAULT_SETTINGS(0),\n          .C_HAS_AXIS_TDATA(1),\n          .C_HAS_AXIS_TID(0),\n          .C_HAS_AXIS_TDEST(0),\n          .C_HAS_AXIS_TUSER(1),\n          .C_HAS_AXIS_TREADY(1),\n          .C_HAS_AXIS_TLAST(0),\n          .C_HAS_AXIS_TSTRB(0),\n          .C_HAS_AXIS_TKEEP(0),\n          .C_AXIS_TDATA_WIDTH(8),\n          .C_AXIS_TID_WIDTH(1),\n          .C_AXIS_TDEST_WIDTH(1),\n          .C_AXIS_TUSER_WIDTH(4),\n          .C_AXIS_TSTRB_WIDTH(1),\n          .C_AXIS_TKEEP_WIDTH(1),\n          .C_AXIS_TYPE(0),\n          .C_IMPLEMENTATION_TYPE_WACH(12),\n          .C_IMPLEMENTATION_TYPE_WDCH(12),\n          .C_IMPLEMENTATION_TYPE_WRCH(12),\n          .C_IMPLEMENTATION_TYPE_RACH(12),\n          .C_IMPLEMENTATION_TYPE_RDCH(12),\n          .C_IMPLEMENTATION_TYPE_AXIS(11),\n          .C_APPLICATION_TYPE_WACH(0),\n          .C_APPLICATION_TYPE_WDCH(0),\n          .C_APPLICATION_TYPE_WRCH(0),\n          .C_APPLICATION_TYPE_RACH(0),\n          .C_APPLICATION_TYPE_RDCH(0),\n          .C_APPLICATION_TYPE_AXIS(0),\n          .C_USE_ECC_WACH(0),\n          .C_USE_ECC_WDCH(0),\n          .C_USE_ECC_WRCH(0),\n          .C_USE_ECC_RACH(0),\n          .C_USE_ECC_RDCH(0),\n          .C_USE_ECC_AXIS(0),\n          .C_ERROR_INJECTION_TYPE_WACH(0),\n          .C_ERROR_INJECTION_TYPE_WDCH(0),\n          .C_ERROR_INJECTION_TYPE_WRCH(0),\n          .C_ERROR_INJECTION_TYPE_RACH(0),\n          .C_ERROR_INJECTION_TYPE_RDCH(0),\n          .C_ERROR_INJECTION_TYPE_AXIS(0),\n          .C_DIN_WIDTH_AXIS(1),\n          .C_WR_DEPTH_WACH(16),\n          .C_WR_DEPTH_WDCH(16),\n          .C_WR_DEPTH_WRCH(16),\n          .C_WR_DEPTH_RACH(16),\n          .C_WR_DEPTH_RDCH(16),\n          .C_WR_DEPTH_AXIS(1024),\n          .C_WR_PNTR_WIDTH_WACH(4),\n          .C_WR_PNTR_WIDTH_WDCH(4),\n          .C_WR_PNTR_WIDTH_WRCH(4),\n          .C_WR_PNTR_WIDTH_RACH(4),\n          .C_WR_PNTR_WIDTH_RDCH(4),\n          .C_WR_PNTR_WIDTH_AXIS(10),\n          .C_HAS_DATA_COUNTS_WACH(0),\n          .C_HAS_DATA_COUNTS_WDCH(0),\n          .C_HAS_DATA_COUNTS_WRCH(0),\n          .C_HAS_DATA_COUNTS_RACH(0),\n          .C_HAS_DATA_COUNTS_RDCH(0),\n          .C_HAS_DATA_COUNTS_AXIS(0),\n          .C_HAS_PROG_FLAGS_WACH(0),\n          .C_HAS_PROG_FLAGS_WDCH(0),\n          .C_HAS_PROG_FLAGS_WRCH(0),\n          .C_HAS_PROG_FLAGS_RACH(0),\n          .C_HAS_PROG_FLAGS_RDCH(0),\n          .C_HAS_PROG_FLAGS_AXIS(0),\n          .C_PROG_FULL_TYPE_WACH(0),\n          .C_PROG_FULL_TYPE_WDCH(0),\n          .C_PROG_FULL_TYPE_WRCH(0),\n          .C_PROG_FULL_TYPE_RACH(0),\n          .C_PROG_FULL_TYPE_RDCH(0),\n          .C_PROG_FULL_TYPE_AXIS(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),\n          .C_PROG_EMPTY_TYPE_WACH(0),\n          .C_PROG_EMPTY_TYPE_WDCH(0),\n          .C_PROG_EMPTY_TYPE_WRCH(0),\n          .C_PROG_EMPTY_TYPE_RACH(0),\n          .C_PROG_EMPTY_TYPE_RDCH(0),\n          .C_PROG_EMPTY_TYPE_AXIS(0),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1021),\n          .C_REG_SLICE_MODE_WACH(0),\n          .C_REG_SLICE_MODE_WDCH(0),\n          .C_REG_SLICE_MODE_WRCH(0),\n          .C_REG_SLICE_MODE_RACH(0),\n          .C_REG_SLICE_MODE_RDCH(0),\n          .C_REG_SLICE_MODE_AXIS(0)\n          )\n          asyncfifo_axi (\n            .s_aclk(s_axi_aclk),\n            .m_aclk(m_axi_aclk),\n            .s_aresetn(async_conv_reset_n),\n            .s_axi_awid           (si_cc_awid),\n            .s_axi_awaddr         (si_cc_awaddr),\n            .s_axi_awlen          (si_cc_awlen),\n            .s_axi_awsize         (si_cc_awsize),\n            .s_axi_awburst        (si_cc_awburst),\n            .s_axi_awlock         (si_cc_awlock),\n            .s_axi_awcache        (si_cc_awcache),\n            .s_axi_awprot         (si_cc_awprot),\n            .s_axi_awqos          (si_cc_awqos),\n            .s_axi_awregion       (si_cc_awregion),\n            .s_axi_awuser         (si_cc_awuser),\n            .s_axi_awvalid        (si_cc_awvalid),\n            .s_axi_awready        (si_cc_awready),\n            .s_axi_wid            (si_cc_wid),\n            .s_axi_wdata          (si_cc_wdata),\n            .s_axi_wstrb          (si_cc_wstrb),\n            .s_axi_wlast          (si_cc_wlast),\n            .s_axi_wuser          (si_cc_wuser),\n            .s_axi_wvalid         (si_cc_wvalid),\n            .s_axi_wready         (si_cc_wready),\n            .s_axi_bid            (si_cc_bid),\n            .s_axi_bresp          (si_cc_bresp),\n            .s_axi_buser          (si_cc_buser),\n            .s_axi_bvalid         (si_cc_bvalid),\n            .s_axi_bready         (si_cc_bready),\n            .m_axi_awid           (cc_mi_awid),\n            .m_axi_awaddr         (cc_mi_awaddr),\n            .m_axi_awlen          (cc_mi_awlen),\n            .m_axi_awsize         (cc_mi_awsize),\n            .m_axi_awburst        (cc_mi_awburst),\n            .m_axi_awlock         (cc_mi_awlock),\n            .m_axi_awcache        (cc_mi_awcache),\n            .m_axi_awprot         (cc_mi_awprot),\n            .m_axi_awqos          (cc_mi_awqos),\n            .m_axi_awregion       (cc_mi_awregion),\n            .m_axi_awuser         (cc_mi_awuser),\n            .m_axi_awvalid        (cc_mi_awvalid),\n            .m_axi_awready        (cc_mi_awready),\n            .m_axi_wid            (cc_mi_wid),\n            .m_axi_wdata          (cc_mi_wdata),\n            .m_axi_wstrb          (cc_mi_wstrb),\n            .m_axi_wlast          (cc_mi_wlast),\n            .m_axi_wuser          (cc_mi_wuser),\n            .m_axi_wvalid         (cc_mi_wvalid),\n            .m_axi_wready         (cc_mi_wready),\n            .m_axi_bid            (cc_mi_bid),\n            .m_axi_bresp          (cc_mi_bresp),\n            .m_axi_buser          (cc_mi_buser),\n            .m_axi_bvalid         (cc_mi_bvalid),\n            .m_axi_bready         (cc_mi_bready),\n            .s_axi_arid           (si_cc_arid),\n            .s_axi_araddr         (si_cc_araddr),\n            .s_axi_arlen          (si_cc_arlen),\n            .s_axi_arsize         (si_cc_arsize),\n            .s_axi_arburst        (si_cc_arburst),\n            .s_axi_arlock         (si_cc_arlock),\n            .s_axi_arcache        (si_cc_arcache),\n            .s_axi_arprot         (si_cc_arprot),\n            .s_axi_arqos          (si_cc_arqos),\n            .s_axi_arregion       (si_cc_arregion),\n            .s_axi_aruser         (si_cc_aruser),\n            .s_axi_arvalid        (si_cc_arvalid),\n            .s_axi_arready        (si_cc_arready),\n            .s_axi_rid            (si_cc_rid),\n            .s_axi_rdata          (si_cc_rdata),\n            .s_axi_rresp          (si_cc_rresp),\n            .s_axi_rlast          (si_cc_rlast),\n            .s_axi_ruser          (si_cc_ruser),\n            .s_axi_rvalid         (si_cc_rvalid),\n            .s_axi_rready         (si_cc_rready),\n            .m_axi_arid           (cc_mi_arid),\n            .m_axi_araddr         (cc_mi_araddr),\n            .m_axi_arlen          (cc_mi_arlen),\n            .m_axi_arsize         (cc_mi_arsize),\n            .m_axi_arburst        (cc_mi_arburst),\n            .m_axi_arlock         (cc_mi_arlock),\n            .m_axi_arcache        (cc_mi_arcache),\n            .m_axi_arprot         (cc_mi_arprot),\n            .m_axi_arqos          (cc_mi_arqos),\n            .m_axi_arregion       (cc_mi_arregion),\n            .m_axi_aruser         (cc_mi_aruser),\n            .m_axi_arvalid        (cc_mi_arvalid),\n            .m_axi_arready        (cc_mi_arready),\n            .m_axi_rid            (cc_mi_rid),\n            .m_axi_rdata          (cc_mi_rdata),\n            .m_axi_rresp          (cc_mi_rresp),\n            .m_axi_rlast          (cc_mi_rlast),\n            .m_axi_ruser          (cc_mi_ruser),\n            .m_axi_rvalid         (cc_mi_rvalid),\n            .m_axi_rready         (cc_mi_rready),\n            .m_aclk_en(1'b1),\n            .s_aclk_en(1'b1),\n            .almost_empty(),\n            .almost_full(),\n            .axis_data_count(),\n            .axis_dbiterr(),\n            .axis_injectdbiterr(1'b0),\n            .axis_injectsbiterr(1'b0),\n            .axis_overflow(),\n            .axis_prog_empty(),\n            .axis_prog_empty_thresh(10'b0),\n            .axis_prog_full(),\n            .axis_prog_full_thresh(10'b0),\n            .axis_rd_data_count(),\n            .axis_sbiterr(),\n            .axis_underflow(),\n            .axis_wr_data_count(),\n            .axi_ar_data_count(),\n            .axi_ar_dbiterr(),\n            .axi_ar_injectdbiterr(1'b0),\n            .axi_ar_injectsbiterr(1'b0),\n            .axi_ar_overflow(),\n            .axi_ar_prog_empty(),\n            .axi_ar_prog_empty_thresh(4'b0),\n            .axi_ar_prog_full(),\n            .axi_ar_prog_full_thresh(4'b0),\n            .axi_ar_rd_data_count(),\n            .axi_ar_sbiterr(),\n            .axi_ar_underflow(),\n            .axi_ar_wr_data_count(),\n            .axi_aw_data_count(),\n            .axi_aw_dbiterr(),\n            .axi_aw_injectdbiterr(1'b0),\n            .axi_aw_injectsbiterr(1'b0),\n            .axi_aw_overflow(),\n            .axi_aw_prog_empty(),\n            .axi_aw_prog_empty_thresh(4'b0),\n            .axi_aw_prog_full(),\n            .axi_aw_prog_full_thresh(4'b0),\n            .axi_aw_rd_data_count(),\n            .axi_aw_sbiterr(),\n            .axi_aw_underflow(),\n            .axi_aw_wr_data_count(),\n            .axi_b_data_count(),\n            .axi_b_dbiterr(),\n            .axi_b_injectdbiterr(1'b0),\n            .axi_b_injectsbiterr(1'b0),\n            .axi_b_overflow(),\n            .axi_b_prog_empty(),\n            .axi_b_prog_empty_thresh(4'b0),\n            .axi_b_prog_full(),\n            .axi_b_prog_full_thresh(4'b0),\n            .axi_b_rd_data_count(),\n            .axi_b_sbiterr(),\n            .axi_b_underflow(),\n            .axi_b_wr_data_count(),\n            .axi_r_data_count(),\n            .axi_r_dbiterr(),\n            .axi_r_injectdbiterr(1'b0),\n            .axi_r_injectsbiterr(1'b0),\n            .axi_r_overflow(),\n            .axi_r_prog_empty(),\n            .axi_r_prog_empty_thresh(4'b0),\n            .axi_r_prog_full(),\n            .axi_r_prog_full_thresh(4'b0),\n            .axi_r_rd_data_count(),\n            .axi_r_sbiterr(),\n            .axi_r_underflow(),\n            .axi_r_wr_data_count(),\n            .axi_w_data_count(),\n            .axi_w_dbiterr(),\n            .axi_w_injectdbiterr(1'b0),\n            .axi_w_injectsbiterr(1'b0),\n            .axi_w_overflow(),\n            .axi_w_prog_empty(),\n            .axi_w_prog_empty_thresh(4'b0),\n            .axi_w_prog_full(),\n            .axi_w_prog_full_thresh(4'b0),\n            .axi_w_rd_data_count(),\n            .axi_w_sbiterr(),\n            .axi_w_underflow(),\n            .axi_w_wr_data_count(),\n            .backup(1'b0),\n            .backup_marker(1'b0),\n            .clk(1'b0),\n            .data_count(),\n            .dbiterr(),\n            .din(18'b0),\n            .dout(),\n            .empty(),\n            .full(),\n            .injectdbiterr(1'b0),\n            .injectsbiterr(1'b0),\n            .int_clk(1'b0),\n            .m_axis_tdata(),\n            .m_axis_tdest(),\n            .m_axis_tid(),\n            .m_axis_tkeep(),\n            .m_axis_tlast(),\n            .m_axis_tready(1'b0),\n            .m_axis_tstrb(),\n            .m_axis_tuser(),\n            .m_axis_tvalid(),\n            .overflow(),\n            .prog_empty(),\n            .prog_empty_thresh(10'b0),\n            .prog_empty_thresh_assert(10'b0),\n            .prog_empty_thresh_negate(10'b0),\n            .prog_full(),\n            .prog_full_thresh(10'b0),\n            .prog_full_thresh_assert(10'b0),\n            .prog_full_thresh_negate(10'b0),\n            .rd_clk(1'b0),\n            .rd_data_count(),\n            .rd_en(1'b0),\n            .rd_rst(1'b0),\n            .rst(1'b0),\n            .sbiterr(),\n            .srst(1'b0),\n            .s_axis_tdata(8'b0),\n            .s_axis_tdest(1'b0),\n            .s_axis_tid(1'b0),\n            .s_axis_tkeep(1'b0),\n            .s_axis_tlast(1'b0),\n            .s_axis_tready(),\n            .s_axis_tstrb(1'b0),\n            .s_axis_tuser(4'b0),\n            .s_axis_tvalid(1'b0),\n            .underflow(),\n            .valid(),\n            .wr_ack(),\n            .wr_clk(1'b0),\n            .wr_data_count(),\n            .wr_en(1'b0),\n            .wr_rst(1'b0),\n            .wr_rst_busy(),\n            .rd_rst_busy(),\n            .sleep(1'b0)\n        );\n      end else if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_async_lite_conv\n        localparam C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n        `include \"axi_infrastructure_v1_1_0.vh\"\n\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n        axi_infrastructure_v1_1_0_axi2vector #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        axi2vec ( \n          .s_axi_awid      ( si_cc_awid      ) ,\n          .s_axi_awaddr    ( si_cc_awaddr    ) ,\n          .s_axi_awlen     ( s_axi_awlen     ) ,\n          .s_axi_awsize    ( si_cc_awsize    ) ,\n          .s_axi_awburst   ( si_cc_awburst   ) ,\n          .s_axi_awlock    ( s_axi_awlock    ) ,\n          .s_axi_awcache   ( si_cc_awcache   ) ,\n          .s_axi_awprot    ( si_cc_awprot    ) ,\n          .s_axi_awqos     ( si_cc_awqos     ) ,\n          .s_axi_awuser    ( si_cc_awuser    ) ,\n          .s_axi_awregion  ( si_cc_awregion  ) ,\n          .s_axi_wid       ( si_cc_wid       ) ,\n          .s_axi_wdata     ( si_cc_wdata     ) ,\n          .s_axi_wstrb     ( si_cc_wstrb     ) ,\n          .s_axi_wlast     ( si_cc_wlast     ) ,\n          .s_axi_wuser     ( si_cc_wuser     ) ,\n          .s_axi_bid       ( si_cc_bid       ) ,\n          .s_axi_bresp     ( si_cc_bresp     ) ,\n          .s_axi_buser     ( si_cc_buser     ) ,\n          .s_axi_arid      ( si_cc_arid      ) ,\n          .s_axi_araddr    ( si_cc_araddr    ) ,\n          .s_axi_arlen     ( s_axi_arlen     ) ,\n          .s_axi_arsize    ( si_cc_arsize    ) ,\n          .s_axi_arburst   ( si_cc_arburst   ) ,\n          .s_axi_arlock    ( s_axi_arlock    ) ,\n          .s_axi_arcache   ( si_cc_arcache   ) ,\n          .s_axi_arprot    ( si_cc_arprot    ) ,\n          .s_axi_arqos     ( si_cc_arqos     ) ,\n          .s_axi_aruser    ( si_cc_aruser    ) ,\n          .s_axi_arregion  ( si_cc_arregion  ) ,\n          .s_axi_rid       ( si_cc_rid       ) ,\n          .s_axi_rdata     ( si_cc_rdata     ) ,\n          .s_axi_rresp     ( si_cc_rresp     ) ,\n          .s_axi_rlast     ( si_cc_rlast     ) ,\n          .s_axi_ruser     ( si_cc_ruser     ) ,\n          .s_awpayload     ( s_awpayload ) ,\n          .s_wpayload      ( s_wpayload  ) ,\n          .s_bpayload      ( s_bpayload  ) ,\n          .s_arpayload     ( s_arpayload ) ,\n          .s_rpayload      ( s_rpayload  ) \n        );\n\n        axi_clock_converter_v2_1_14_lite_async #(\n          .C_DEST_SYNC_FF (2),\n          .C_SRC_SYNC_FF  (2),\n          .C_WIDTH        (G_AXI_AWPAYLOAD_WIDTH)\n        ) aw_handshake (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_awvalid),\n          .s_ready  (si_cc_awready),\n          .s_payld  (s_awpayload),\n          .m_valid  (cc_mi_awvalid),\n          .m_ready  (cc_mi_awready),\n          .m_payld  (m_awpayload)\n        );\n\n        axi_clock_converter_v2_1_14_lite_async #(\n          .C_DEST_SYNC_FF (2),\n          .C_SRC_SYNC_FF  (2),\n          .C_WIDTH        (G_AXI_ARPAYLOAD_WIDTH)\n        ) ar_handshake (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_arvalid),\n          .s_ready  (si_cc_arready),\n          .s_payld  (s_arpayload),\n          .m_valid  (cc_mi_arvalid),\n          .m_ready  (cc_mi_arready),\n          .m_payld  (m_arpayload)\n        );\n\n        axi_clock_converter_v2_1_14_lite_async #(\n          .C_DEST_SYNC_FF (2),\n          .C_SRC_SYNC_FF  (2),\n          .C_WIDTH        (G_AXI_WPAYLOAD_WIDTH)\n        ) w_handshake (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_wvalid),\n          .s_ready  (si_cc_wready),\n          .s_payld  (s_wpayload),\n          .m_valid  (cc_mi_wvalid),\n          .m_ready  (cc_mi_wready),\n          .m_payld  (m_wpayload)\n        );\n\n        axi_clock_converter_v2_1_14_lite_async #(\n          .C_DEST_SYNC_FF (2),\n          .C_SRC_SYNC_FF  (2),\n          .C_WIDTH        (G_AXI_BPAYLOAD_WIDTH)\n        ) b_handshake (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_bvalid),\n          .s_ready  (cc_mi_bready),\n          .s_payld  (m_bpayload),\n          .m_valid  (si_cc_bvalid),\n          .m_ready  (si_cc_bready),\n          .m_payld  (s_bpayload)\n        );\n\n        axi_clock_converter_v2_1_14_lite_async #(\n          .C_DEST_SYNC_FF (2),\n          .C_SRC_SYNC_FF  (2),\n          .C_WIDTH        (G_AXI_RPAYLOAD_WIDTH)\n        ) r_handshake (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_rvalid),\n          .s_ready  (cc_mi_rready),\n          .s_payld  (m_rpayload),\n          .m_valid  (si_cc_rvalid),\n          .m_ready  (si_cc_rready),\n          .m_payld  (s_rpayload)\n        );\n\n        axi_infrastructure_v1_1_0_vector2axi #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        vec2axi ( \n          .m_awpayload    ( m_awpayload    ) ,\n          .m_wpayload     ( m_wpayload     ) ,\n          .m_bpayload     ( m_bpayload     ) ,\n          .m_arpayload    ( m_arpayload    ) ,\n          .m_rpayload     ( m_rpayload     ) ,\n          .m_axi_awid     ( cc_mi_awid     ) ,\n          .m_axi_awaddr   ( cc_mi_awaddr   ) ,\n          .m_axi_awlen    ( cc_mi_awlen    ) ,\n          .m_axi_awsize   ( cc_mi_awsize   ) ,\n          .m_axi_awburst  ( cc_mi_awburst  ) ,\n          .m_axi_awlock   ( cc_mi_awlock   ) ,\n          .m_axi_awcache  ( cc_mi_awcache  ) ,\n          .m_axi_awprot   ( cc_mi_awprot   ) ,\n          .m_axi_awqos    ( cc_mi_awqos    ) ,\n          .m_axi_awuser   ( cc_mi_awuser   ) ,\n          .m_axi_awregion ( cc_mi_awregion ) ,\n          .m_axi_wid      ( cc_mi_wid      ) ,\n          .m_axi_wdata    ( cc_mi_wdata    ) ,\n          .m_axi_wstrb    ( cc_mi_wstrb    ) ,\n          .m_axi_wlast    ( cc_mi_wlast    ) ,\n          .m_axi_wuser    ( cc_mi_wuser    ) ,\n          .m_axi_bid      ( cc_mi_bid      ) ,\n          .m_axi_bresp    ( cc_mi_bresp    ) ,\n          .m_axi_buser    ( cc_mi_buser    ) ,\n          .m_axi_arid     ( cc_mi_arid     ) ,\n          .m_axi_araddr   ( cc_mi_araddr   ) ,\n          .m_axi_arlen    ( cc_mi_arlen    ) ,\n          .m_axi_arsize   ( cc_mi_arsize   ) ,\n          .m_axi_arburst  ( cc_mi_arburst  ) ,\n          .m_axi_arlock   ( cc_mi_arlock   ) ,\n          .m_axi_arcache  ( cc_mi_arcache  ) ,\n          .m_axi_arprot   ( cc_mi_arprot   ) ,\n          .m_axi_arqos    ( cc_mi_arqos    ) ,\n          .m_axi_aruser   ( cc_mi_aruser   ) ,\n          .m_axi_arregion ( cc_mi_arregion ) ,\n          .m_axi_rid      ( cc_mi_rid      ) ,\n          .m_axi_rdata    ( cc_mi_rdata    ) ,\n          .m_axi_rresp    ( cc_mi_rresp    ) ,\n          .m_axi_rlast    ( cc_mi_rlast    ) ,\n          .m_axi_ruser    ( cc_mi_ruser    ) \n        );\n\n      end else begin : gen_sync_conv\n        \n        assign {fast_aclk, slow_aclk} = P_SI_LT_MI ? {m_axi_aclk, s_axi_aclk} : {s_axi_aclk, m_axi_aclk};\n    \n        // Sample cycle used to determine when to assert a signal on a fast clock\n        // to be flopped onto a slow clock.\n        axi_clock_converter_v2_1_14_axic_sample_cycle_ratio #(\n          .C_RATIO ( P_ACLK_RATIO )\n        )\n        axic_sample_cycle_inst (\n          .SLOW_ACLK          ( slow_aclk               ) ,\n          .FAST_ACLK          ( fast_aclk               ) ,\n          .SAMPLE_CYCLE_EARLY ( sample_cycle_early ) ,\n          .SAMPLE_CYCLE       ( sample_cycle       )\n        );\n    \n      ////////////////////////////////////////////////////////////////////////////////\n      // AXI write channels\n      ////////////////////////////////////////////////////////////////////////////////\n        if (C_AXI_SUPPORTS_WRITE) begin : gen_conv_write_ch\n    \n          // Write Address Port\n          assign s_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH]     = si_cc_awaddr   ;\n          assign s_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH]     = si_cc_awprot   ;\n          assign cc_mi_awaddr   = m_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH];\n          assign cc_mi_awprot   = m_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_aw_axi4\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen    ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock[0] ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH] = si_cc_awregion ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awregion = m_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_aw_axi3\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen[3:0] ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock   ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_aw_user\n            assign s_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH]  = si_cc_awuser;\n            assign cc_mi_awuser = m_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_14_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AW_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          aw_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_aw_mesg ) ,\n            .S_VALID   ( si_cc_awvalid   ) ,\n            .S_READY   ( si_cc_awready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_aw_mesg ) ,\n            .M_VALID   ( cc_mi_awvalid   ) ,\n            .M_READY   ( cc_mi_awready   )\n          );\n    \n          // Write Data Port\n          assign s_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH] = si_cc_wdata; \n          assign s_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH] = si_cc_wstrb; \n          assign cc_mi_wdata    = m_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH];\n          assign cc_mi_wstrb    = m_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_w_axi4\n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_w_axi3\n            assign s_w_mesg[C_WID_RIGHT+:C_WID_WIDTH]     = si_cc_wid; \n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wid      = m_w_mesg[C_WID_RIGHT+:C_WID_WIDTH];\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_w_user\n            assign s_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH]  = si_cc_wuser;\n            assign cc_mi_wuser = m_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_14_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH  ( C_W_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE           ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          w_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_w_mesg ) ,\n            .S_VALID   ( si_cc_wvalid   ) ,\n            .S_READY   ( si_cc_wready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_w_mesg ) ,\n            .M_VALID   ( cc_mi_wvalid   ) ,\n            .M_READY   ( cc_mi_wready   )\n          );\n    \n          // Write Response Port\n          assign m_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH] = cc_mi_bresp;\n          assign si_cc_bresp    = s_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_b_axi\n            assign m_b_mesg[C_BID_RIGHT+:C_BID_WIDTH]     = cc_mi_bid;\n            assign si_cc_bid      = s_b_mesg[C_BID_RIGHT+:C_BID_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_b_user\n            assign m_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH] = cc_mi_buser;\n            assign si_cc_buser  = s_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_14_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_B_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          b_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_b_mesg ) ,\n            .S_VALID   ( cc_mi_bvalid   ) ,\n            .S_READY   ( cc_mi_bready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_b_mesg ) ,\n            .M_VALID   ( si_cc_bvalid   ) ,\n            .M_READY   ( si_cc_bready   )\n          );\n    \n        end else begin : gen_tieoff_write_ch\n    \n          // Write address port\n          assign cc_mi_awid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_awaddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_awlen    = {8{1'b0}};\n          assign cc_mi_awsize   = {3{1'b0}};\n          assign cc_mi_awburst  = {2{1'b0}};\n          assign cc_mi_awlock   = {2{1'b0}};\n          assign cc_mi_awcache  = {4{1'b0}};\n          assign cc_mi_awprot   = {3{1'b0}};\n          assign cc_mi_awregion = {4{1'b0}};\n          assign cc_mi_awqos    = {4{1'b0}};\n          assign cc_mi_awuser   = {C_AXI_AWUSER_WIDTH{1'b0}};\n          assign cc_mi_awvalid  = 1'b0;\n          assign si_cc_awready  = 1'b0;\n    \n          // Write data port\n          assign cc_mi_wid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_wdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign cc_mi_wstrb    = {C_AXI_DATA_WIDTH/8{1'b0}};\n          assign cc_mi_wlast    = 1'b0;\n          assign cc_mi_wuser    = {C_AXI_WUSER_WIDTH{1'b0}};\n          assign cc_mi_wvalid   = 1'b0;\n          assign si_cc_wready   = 1'b0;\n    \n          // Write response port\n          assign si_cc_bid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_bresp    = {2{1'b0}};\n          assign si_cc_buser    = {C_AXI_BUSER_WIDTH{1'b0}};\n          assign si_cc_bvalid   = 1'b0;\n          assign cc_mi_bready   = 1'b0;\n        end\n    \n        ////////////////////////////////////////////////////////////////////////////////\n        // AXI read channels\n        ////////////////////////////////////////////////////////////////////////////////\n    \n        if (C_AXI_SUPPORTS_READ) begin : gen_conv_read_ch\n    \n          // Read Address Port\n          assign s_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH]     = si_cc_araddr   ;\n          assign s_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH]     = si_cc_arprot   ;\n          assign cc_mi_araddr   = m_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH];\n          assign cc_mi_arprot   = m_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_ar_axi4\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen    ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock[0] ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH] = si_cc_arregion ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arregion = m_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_ar_axi3\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen[3:0] ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock   ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_ar_user\n            assign s_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH]  = si_cc_aruser;\n            assign cc_mi_aruser = m_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_14_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AR_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          ar_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_ar_mesg ) ,\n            .S_VALID   ( si_cc_arvalid   ) ,\n            .S_READY   ( si_cc_arready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN  ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_ar_mesg ) ,\n            .M_VALID   ( cc_mi_arvalid   ) ,\n            .M_READY   ( cc_mi_arready   )\n          );\n    \n          // Read Data Port\n          assign m_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH] = cc_mi_rdata; \n          assign m_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH] = cc_mi_rresp; \n          assign si_cc_rdata    = s_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH];\n          assign si_cc_rresp    = s_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_r_axi\n            assign m_r_mesg[C_RID_RIGHT+:C_RID_WIDTH]     = cc_mi_rid;   \n            assign m_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH] = cc_mi_rlast;\n            assign si_cc_rid      = s_r_mesg[C_RID_RIGHT+:C_RID_WIDTH];\n            assign si_cc_rlast    = s_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_r_user\n            assign m_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH] = cc_mi_ruser;\n            assign si_cc_ruser  = s_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_14_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_R_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          r_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_r_mesg ) ,\n            .S_VALID   ( cc_mi_rvalid   ) ,\n            .S_READY   ( cc_mi_rready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_r_mesg ) ,\n            .M_VALID   ( si_cc_rvalid   ) ,\n            .M_READY   ( si_cc_rready   )\n          );\n    \n        end else begin : gen_tieoff_read_ch\n    \n          // Read Address Port\n          assign cc_mi_arid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_araddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_arlen    = {8{1'b0}};\n          assign cc_mi_arsize   = {3{1'b0}};\n          assign cc_mi_arburst  = {2{1'b0}};\n          assign cc_mi_arlock   = {2{1'b0}};\n          assign cc_mi_arcache  = {4{1'b0}};\n          assign cc_mi_arprot   = {3{1'b0}};\n          assign cc_mi_arregion = {4{1'b0}};\n          assign cc_mi_arqos    = {4{1'b0}};\n          assign cc_mi_aruser   = {C_AXI_ARUSER_WIDTH{1'b0}};\n          assign cc_mi_arvalid  = 1'b0;\n          assign si_cc_arready  = 1'b0;\n    \n          // Read data port\n          assign si_cc_rid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_rdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign si_cc_rresp    = {2{1'b0}};\n          assign si_cc_rlast    = 1'b0;\n          assign si_cc_ruser    = {C_AXI_RUSER_WIDTH{1'b0}};\n          assign si_cc_rvalid   = 1'b0;\n          assign cc_mi_rready   = 1'b0;\n        end\n      end\n    end\n\n  endgenerate\n\nendmodule\n\n\n\n", "num_lines": 2174}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_15_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      (* max_fanout = 66 *) reg s_valid_d;\n      (* max_fanout = 66 *) reg s_ready_d = 1'b0;\n      (* max_fanout = 66 *) reg s_ready_reg = 1'b0;\n      (* max_fanout = 66 *) reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_15_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS==2) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS==2) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_15_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      // System Signals\n      .ACLK(ACLK),\n      .ARESET(ARESET),\n\n      // Slave side\n      .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n      .S_VALID(S_VALID),\n      .S_READY(S_READY),\n\n      // Master side\n      .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n      .M_VALID(M_VALID),\n      .M_READY(M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK           ( ACLK ) ,\n        .ARESET         ( ARESET ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK           ( ACLK ) ,\n        .ARESET         ( ARESET ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (1) begin : common\n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    (* dont_touch=\"true\" *)  reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_handshake_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg [((C_PIPELINES>0)?(C_PIPELINES-1):0):0] ready_d = 0;\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0; \n        laguna_m_ready_d <= 1'b0; \n        ready_d <= 0;\n      end else begin\n        laguna_m_ready_d <= laguna_m_ready; \n        if (C_PIPELINES==0) begin\n          laguna_s_ready_i <= laguna_m_ready_d;\n        end else if (C_PIPELINES==1) begin\n          ready_d <= laguna_m_ready_d; \n          laguna_s_ready_i <= ready_d;\n        end else begin\n          ready_d <= {ready_d, laguna_m_ready_d}; \n          laguna_s_ready_i <= ready_d[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n        end\n      end\n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_d : payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, laguna_m_ready_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{laguna_m_ready_d}};\n            payload_valid_enable <= laguna_m_ready_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==0) begin\n                laguna_s_payload_d[i] <= laguna_s_payload[i];\n              end else if (p==C_PIPELINES+1) begin\n                laguna_m_payload_i[i] <= payload_i[C_PIPELINES*C_DATA_WIDTH + i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          if (areset_d) begin\n            laguna_s_handshake_d <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_s_handshake_d <= laguna_s_handshake;\n          end\n        end else if (p==C_PIPELINES+1) begin\n          if (areset_d) begin\n            laguna_m_handshake_i <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_m_handshake_i <= handshake_i[C_PIPELINES];\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (C_REG_CONFIG == 13) begin : tdm\n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* dont_touch=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_15_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_LATENCY = (C_PIPELINES>0) ? C_PIPELINES : 1;\n     \n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    (* dont_touch=\"true\" *)  reg laguna_m_handshake_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] ready_d = 0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_LATENCY-1];\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_ready_d <= 1'b0; \n        ready_d <= 0;\n      end else begin\n        laguna_m_ready_d <= laguna_m_ready; \n        if (C_PIPELINES>0) begin\n          ready_d <= {ready_d, laguna_m_ready_d}; \n        end\n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, laguna_m_ready_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{laguna_m_ready_d}};\n            payload_valid_enable <= laguna_m_ready_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (C_PIPELINES==0) begin\n          if (laguna_m_ready_d) begin\n            laguna_m_payload_i <= S_PAYLOAD_DATA;\n          end\n        end else begin\n          for (r=0; r<P_REPLICATION; r=r+1) begin\n            if (payload_data_enable[r]) begin\n              for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n                if (p==C_PIPELINES) begin\n                  laguna_m_payload_i[i] <= payload_i[((C_PIPELINES>0)?(C_PIPELINES-1):0)*C_DATA_WIDTH + i];\n                end else if (p==0) begin\n                  payload_data[i] <= S_PAYLOAD_DATA[i];\n                end else begin\n                  payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n                end\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (C_PIPELINES==0) begin\n          if (areset_d) begin\n            laguna_m_handshake_i <= 1'b0;\n          end else if (laguna_m_ready_d) begin\n            laguna_m_handshake_i <= S_VALID;\n          end\n        end else begin\n          if (p==C_PIPELINES) begin\n            if (areset_d) begin\n              laguna_m_handshake_i <= 1'b0;\n            end else if (payload_valid_enable) begin\n              laguna_m_handshake_i <= handshake_i[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n            end\n          end else if (p==0) begin\n            if (areset_d) begin\n              payload_valid <= 1'b0;\n            end else if (payload_valid_enable) begin\n              payload_valid <= S_VALID;\n            end\n          end else begin\n            if (areset_d) begin\n              payload_valid <= 1'b0;\n            end else if (payload_valid_enable) begin\n              payload_valid <= handshake_i[((p>0)?(p-1):0)];\n            end\n          end\n        end\n      end\n    end\n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_15_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (C_REG_CONFIG == 13) begin : tdm\n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n     \n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* dont_touch=\"true\" *)  reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg [((C_PIPELINES>0)?(C_PIPELINES-1):0):0] ready_d = 0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] push_enable_d = 0;\n    (* dont_touch=\"true\" *)  reg root_enable_d = 1'b0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    wire push_enable;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push_enable = push_enable_d[P_PIPE_LATENCY-1];\n    assign push = handshake_i[C_PIPELINES] & push_enable;      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0; \n        ready_d <= 0;\n        push_enable_d <= 0;\n        root_enable_d <= 1'b0; \n      end else begin\n        push_enable_d <= {push_enable_d, root_enable_d};\n        root_enable_d <= M_READY | ~m_valid_i;\n        if (C_PIPELINES==0) begin\n          laguna_s_ready_i <= root_enable_d;\n        end else if (C_PIPELINES==1) begin\n          ready_d <= root_enable_d; \n          laguna_s_ready_i <= ready_d;\n        end else begin\n          ready_d <= {ready_d, root_enable_d}; \n          laguna_s_ready_i <= ready_d[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n        end\n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_d : payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, root_enable_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{root_enable_d}};\n            payload_valid_enable <= root_enable_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==0) begin\n                laguna_s_payload_d[i] <= laguna_s_payload[i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          if (areset_d) begin\n            laguna_s_handshake_d <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_s_handshake_d <= laguna_s_handshake;\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n    if ((C_PIPELINES==0) && (C_SOURCE_LATENCY<=1)) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        ); \n  \n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_15_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_LATENCY = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (1) begin : common\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] ready_d = 0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] push_enable_d = 0;\n    (* dont_touch=\"true\" *)  reg root_enable_d = 1'b0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire s_ready_i;\n    wire push;\n    wire pop;\n    wire push_enable;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push_enable = (C_PIPELINES == 0) ? root_enable_d : push_enable_d[P_PIPE_LATENCY-1];\n    assign push = handshake_i[C_PIPELINES] & push_enable;      \n    assign M_VALID = m_valid_i;\n    assign s_ready_i = (C_PIPELINES == 0) ? root_enable_d : ready_d[P_PIPE_LATENCY-1];\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        ready_d <= 0;\n        push_enable_d <= 0;\n        root_enable_d <= 1'b0;\n      end else begin\n        root_enable_d <= M_READY | ~m_valid_i;\n        if (C_PIPELINES > 0) begin\n          ready_d <= {ready_d, root_enable_d}; \n          push_enable_d <= {push_enable_d, root_enable_d};\n        end\n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, root_enable_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{root_enable_d}};\n            payload_valid_enable <= root_enable_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==1) begin\n                payload_data[i] <= S_PAYLOAD_DATA[i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= S_VALID;\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n    if (C_PIPELINES<=1) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    (* fsm_encoding = \"none\" *) reg [1:0] state = K_EMPTY;  // State vector register\n    reg [1:0] next;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    \n    assign m_valid = state[0];  // Drive m_valid from state vector\n    assign m_mesg  = mesg_reg;\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid) begin\n            next = K_HAS1;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin\n      if (areset) begin\n        state <= K_EMPTY;\n      end else begin\n        state <= next;\n      end\n    end\n            \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      axi_register_slice_v2_1_15_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n\n  axi_infrastructure_v1_1_0_axi2vector #( \n    .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n    .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n    .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n    .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n    .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n    .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n    .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n    .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n    .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n    .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n    .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n    .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n    .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n    .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n    .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n    .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n  )\n  axi2vector_0 ( \n    .s_axi_awid      ( s_axi_awid      ) ,\n    .s_axi_awaddr    ( s_axi_awaddr    ) ,\n    .s_axi_awlen     ( s_axi_awlen     ) ,\n    .s_axi_awsize    ( s_axi_awsize    ) ,\n    .s_axi_awburst   ( s_axi_awburst   ) ,\n    .s_axi_awlock    ( s_axi_awlock    ) ,\n    .s_axi_awcache   ( s_axi_awcache   ) ,\n    .s_axi_awprot    ( s_axi_awprot    ) ,\n    .s_axi_awqos     ( s_axi_awqos     ) ,\n    .s_axi_awuser    ( s_axi_awuser    ) ,\n    .s_axi_awregion  ( s_axi_awregion  ) ,\n    .s_axi_wid       ( s_axi_wid       ) ,\n    .s_axi_wdata     ( s_axi_wdata     ) ,\n    .s_axi_wstrb     ( s_axi_wstrb     ) ,\n    .s_axi_wlast     ( s_axi_wlast     ) ,\n    .s_axi_wuser     ( s_axi_wuser     ) ,\n    .s_axi_bid       ( s_axi_bid       ) ,\n    .s_axi_bresp     ( s_axi_bresp     ) ,\n    .s_axi_buser     ( s_axi_buser     ) ,\n    .s_axi_arid      ( s_axi_arid      ) ,\n    .s_axi_araddr    ( s_axi_araddr    ) ,\n    .s_axi_arlen     ( s_axi_arlen     ) ,\n    .s_axi_arsize    ( s_axi_arsize    ) ,\n    .s_axi_arburst   ( s_axi_arburst   ) ,\n    .s_axi_arlock    ( s_axi_arlock    ) ,\n    .s_axi_arcache   ( s_axi_arcache   ) ,\n    .s_axi_arprot    ( s_axi_arprot    ) ,\n    .s_axi_arqos     ( s_axi_arqos     ) ,\n    .s_axi_aruser    ( s_axi_aruser    ) ,\n    .s_axi_arregion  ( s_axi_arregion  ) ,\n    .s_axi_rid       ( s_axi_rid       ) ,\n    .s_axi_rdata     ( s_axi_rdata     ) ,\n    .s_axi_rresp     ( s_axi_rresp     ) ,\n    .s_axi_rlast     ( s_axi_rlast     ) ,\n    .s_axi_ruser     ( s_axi_ruser     ) ,\n    .s_awpayload ( s_awpayload ) ,\n    .s_wpayload  ( s_wpayload  ) ,\n    .s_bpayload  ( s_bpayload  ) ,\n    .s_arpayload ( s_arpayload ) ,\n    .s_rpayload  ( s_rpayload  ) \n  );\n    \n  if (C_REG_CONFIG_AW <= 9) begin : aw\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_REG_CONFIG_AW == 15) begin : aw15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if (C_REG_CONFIG_W <= 9) begin : w\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_REG_CONFIG_W == 15) begin : w15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if (C_REG_CONFIG_B <= 9) begin : b\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if (C_REG_CONFIG_B == 15) begin : b15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if (C_REG_CONFIG_AR <= 9) begin : ar\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_REG_CONFIG_AR == 15) begin : ar15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if (C_REG_CONFIG_R <= 9) begin : r\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_REG_CONFIG_R == 15) begin : r15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\n  axi_infrastructure_v1_1_0_vector2axi #( \n    .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n    .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n    .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n    .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n    .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n    .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n    .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n    .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n    .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n    .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n    .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n    .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n    .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n    .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n    .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n    .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n  )\n  vector2axi_0 ( \n    .m_awpayload    ( m_awpayload    ) ,\n    .m_wpayload     ( m_wpayload     ) ,\n    .m_bpayload     ( m_bpayload     ) ,\n    .m_arpayload    ( m_arpayload    ) ,\n    .m_rpayload     ( m_rpayload     ) ,\n    .m_axi_awid     ( m_axi_awid     ) ,\n    .m_axi_awaddr   ( m_axi_awaddr   ) ,\n    .m_axi_awlen    ( m_axi_awlen    ) ,\n    .m_axi_awsize   ( m_axi_awsize   ) ,\n    .m_axi_awburst  ( m_axi_awburst  ) ,\n    .m_axi_awlock   ( m_axi_awlock   ) ,\n    .m_axi_awcache  ( m_axi_awcache  ) ,\n    .m_axi_awprot   ( m_axi_awprot   ) ,\n    .m_axi_awqos    ( m_axi_awqos    ) ,\n    .m_axi_awuser   ( m_axi_awuser   ) ,\n    .m_axi_awregion ( m_axi_awregion ) ,\n    .m_axi_wid      ( m_axi_wid      ) ,\n    .m_axi_wdata    ( m_axi_wdata    ) ,\n    .m_axi_wstrb    ( m_axi_wstrb    ) ,\n    .m_axi_wlast    ( m_axi_wlast    ) ,\n    .m_axi_wuser    ( m_axi_wuser    ) ,\n    .m_axi_bid      ( m_axi_bid      ) ,\n    .m_axi_bresp    ( m_axi_bresp    ) ,\n    .m_axi_buser    ( m_axi_buser    ) ,\n    .m_axi_arid     ( m_axi_arid     ) ,\n    .m_axi_araddr   ( m_axi_araddr   ) ,\n    .m_axi_arlen    ( m_axi_arlen    ) ,\n    .m_axi_arsize   ( m_axi_arsize   ) ,\n    .m_axi_arburst  ( m_axi_arburst  ) ,\n    .m_axi_arlock   ( m_axi_arlock   ) ,\n    .m_axi_arcache  ( m_axi_arcache  ) ,\n    .m_axi_arprot   ( m_axi_arprot   ) ,\n    .m_axi_arqos    ( m_axi_arqos    ) ,\n    .m_axi_aruser   ( m_axi_aruser   ) ,\n    .m_axi_arregion ( m_axi_arregion ) ,\n    .m_axi_rid      ( m_axi_rid      ) ,\n    .m_axi_rdata    ( m_axi_rdata    ) ,\n    .m_axi_rresp    ( m_axi_rresp    ) ,\n    .m_axi_rlast    ( m_axi_rlast    ) ,\n    .m_axi_ruser    ( m_axi_ruser    ) \n  );\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 3108}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nYpfMx9GvesTR0nGdN/CyBECjW9iz+5g/YsUCkmLyfcl9kUguiUzzNwVg3ON/A4BrqXdSVCEc4oc9\njf3mXlpRVA==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\ncsN9JMXmg9BJlgjFcEph5gOv1+p3hZIqsmwL5z2Czw9ZfUoTeQK8FE1D4XRyaYorfGhXvVrScPSF\n14EXvUeXM4z8gXl7ggoHA3zrbps1E0fuKYuJVXPPM4YvEgQ09ApyfPThDlQ60osC/OzCsb7WAWU6\n3ppy//9UC055RD8QArg=\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nEMnukfw+EF6W7W68TalTatBqzkeWepH6qfewzeutG3Q+uulyg7ZBqD9VY6MkOWr/5PVt3VvwPTv0\ncTqcPlL+v5/amIsFL6u84fyqMWdVKV+/QEiQiBDjGctlcblh2c8OMk6DpQaTNwhyN3D23UxA8+w7\niiVSaZ0o+KPcB6mYhbU=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nENtcLOHCNxDYI9wIzYepJfjNyw7YNxm9g2EJL0jkt9SXZIAPCKrT6yX7EgSe8KWiPlvUcB5Xf6lt\nXInmua4ZJi+zLfCh9FxCEZt27Funifdm0/53JKR79McWrEE1XHWqcwq0XDL8ZPDBILgHyz+l8d+R\nv/722mxUdGqIcEefgyNZATx1aHURCY9XO4KN9s0KEkVk/SaBeMo9HAxLkOm12jBFIZobuIc7GydH\nreLCALybcg3Td+1K/U8mDaPpzLbfOSZlmeXOUfvRxYANrnuJzcmqR+Kk6bIzQ2Zld9unF35AM6nu\nl73TF1pvbs8jZU9uKDkqqOpIesBTQUBjAU18Tw==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\ng98f31KFk932yZSp44BGJiVI84eiNM0aomH1rJ10xqNbK7Ace/1VwJ1bChweO2Olr46vTnnXLi86\npChf5tfT3of2mBtxgJk7aHrA6oA1NWlJT5SGAkTYtqJqmYfIoJsedjSjgN92lkePNbASK31ecyQo\n+pkILfAlx20IHRX7vRRotxahNFAzn39Si5+eLONMqhkPrLNXaKAJi2Lq2bZ8FpKeolihf6dLsFf8\nBr8Xd1s9cpRAAHDoE9OkdICG9MeUb755cRZovBOuJYFBSSvSDmx1bk1pXFWSxDG4Z7kQ78Cr4AAq\n2pSeJ+//Owp2/n0gWP+phsgpA3zegics2/gpRw==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinx_2016_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nSJKBkZFw7Efj+9dJLkxk1jngEsHj0sd8fIn4WQTY4TcrYB3t0c6gxiQubxvLLEJg4QgsvsgSLnD6\niFfpfDF5nj5X/fP3btucB79804nSQ2iTm2UxEOwbHTwKwaXqs0OIRH3AexAv6pYTksMqC6OPQi5/\nYJwjAqN+/W4Q1Yno+OKjz9/1vURz26EHmEcun6zS9kFfW08h9R57AWuSasizu2vGSd3THmF1+Sx5\ncvngOfWiK5CjeInipR9ydR6F4Ky87RfDTJmYSJKHrUne5+DadfO+yLtBH9UFKu4OcZA3ryLTKzXR\nyWltCNxGczDM62TEU1auvaKD9/cuoEdZHiKZvg==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 2368)\n`pragma protect data_block\ni9xS00la1AKc+pJxWfZRqs0vdEkUthXwAPplov4xkH6M1Oy3c17Ein1DprC9vsLj/Kix6nguoJkj\nKCod6CkRJgG9tSxBeQA7Z/oUhYIf7mvdK+6F5Kpd25sD1cB99b+wcRo1wX4AT/ryVDDJQ9r8w10n\nG32bDB64yxCmBb6jbg8UFFqCIP/s0r3d7HiC2IJHu81lSirXOnE0PBG597aHI1PvEhtreezy3KDB\nGEG5yVba/WMSPkiqzYE1L/YU73FuELj68OhfvcAbl3JLD5hqh6Wa0zLB0kpVIVbBjhgLErreoZRI\nTtlbCyjxPD7LIsrs0H08tqRMFbV2zi7ag2k0DLKA8z7uEvXfgWRqBLmwR5n68aiF7MJxWeYIPZ2k\neP1lhUPJAdpHbSUIbHeKrA85leRnmAIx4AjMV5ehyAfy1wFi6lTbzA1qRfy+bRi2YkIDaUR9+4+C\nbO8LnO6todEvhJ6NYaP/AukCAoaG+PjsaBBa7I43ylsdaxqAzRiPHN76FWfV5cCp+YYCED3MqXeK\nP9kWVzXnR50I7lMenjuhFCrbPDdSHGnSJE1/jNOIIwfXiWSkG45VRPxFaGmqZTownaT40ltJ+Uz8\n8QBnTao9a371YgNTVzMkvh+CxUb9O60aWXRC4Fl1l86tceST+blaHaHoU8wh8onQo0ag8cJdUeex\nul4iE+iaZH5Pq9PqQL+0JyY+ScclVTjn3lWgYgLYLBs2O4noyV7o8E8iDl8kNx5oyOq6nWrk8vJ6\n0rYffch66ELbnAkKJ7+HxuSIiNan856Ev/jDaj8arA96bInqV4Hyou/zhO0pNtZ8BofBSXII3KVv\nmUr9np+UC6PeIEl4ERCkoO725dESs6agRczlN3U3zi06YtKF4NHnNQF6Q5k/yFRDATvJFntSa5cX\nCq2riSlI5fD7HZ7AptAQ94GWFNE2vRKG/+7VqwXnvCJKhKXsUbkDulcIf34AbI7r7s7Bggm8vK1Q\nTxCGOHb7/txQtTj9kih0FQUbV68Wpcq8r2aXRFMa4xR9oJ6n/uON5rpZaTG0oWQubxKZ7vVhH6Bw\ngMA3qKO7tHqkQyarIZNw6rxijluCcVTlBw1Nv+A3WAZtZmiprqmbgmELrb//6VTWtOiwa5FayqfT\nOCvhEz0X61jHQ/bJQpQ8flkTToiL9Pnx++NvFRaTb9OL51VO4VV0A/WFyCmp9NZEFaQMuAdiiyi3\n8IU9vxp7jPvoBKCmvVcSbCnbylujhBT1j7hKlIFnwbdtdEGP+P3irmAfInLukus8V4vleb8yuZwc\nRJbxZsssfmdJgOp/T+xYcVUzTDRvBEgyl+6pvy9I/Neb8phhKPl5/JPGWj+jnWsh9QI7MG+W8kQC\n8gv8+Cw3E5qqdtHfQNIXNRqYZ9XvpxEXIo3GRBvfeZ36eoscT6C2sdA5sGMkDPTzTgPfKPDXFO75\nnuVOy/jeNaDHMbJdYKnpsW1IciGj/OyrhXQLw2OVWC4613A/RCXB/+IvUAwTO8TcAPN7fJZarIgg\nhRszeUDEbVlB/uvsptOs9WqbpYNmknXaqo4nl/lbhxCokfgjf6J9aCjZ6giiRZQhjraYsTTmgOR0\nmq8Z1cRwNjiEp5TB9CA2DOS4Oq5Jbupig1xdKM8QBsSfuG2pvmT2bcICutejSjadlgRpXBumeqdl\np5FxiBFjAyE0c/JkbHoUYXFTEWpwCndGVxtz+pU4uOHQiun8HME0Qp0d+60ECE8r+TtfFAVTK1Au\n0AW+/HbKSlWGTSYdIhpEvCXHyUbRZWyjjkttSvSyVbGey2fb7DcGkOIEhJ3EOjVaCiyL8iZPSiiu\nqk2HKfl04mGQ86Mk+NRgpxNsKnGsK0zU8gQO68bN2B3y8leN9y64VvO8FKnpe8Tg955t5LKNuDyE\nPuhgiOwXLPZGcvd1+vCJp0w1ykY9crDzlCcFhieGrLtqQvRLamarNoeVpAAWIebNPsULqskg8r9i\nP1M9To2EfMtFRIvqpa62MDBjCmO7JJSaExLI1ln5FrGUKnwPVqrD9TDw7tR/2/peBK/yH4aIMu0b\npauK4r7gzQV4ttelqKpGpKcv/nY3GaVPPLfS0sw6zXO8AepcgXn1BYoy74kPoeUAp+6HASxfwlS+\nyq/FAc/mSnKEykRQJf7b93w6hUOV1djXkg/gTUQP30vmrjLdz23bQBR6kFqB/IaYqUbnLnUdQdF+\nN0L43kGHdODb49/jQIPmUtPRF+2eOamdWnhI8He+tHC74whG1noCMH+vt/J/hOAlwR70V6P6r5C2\nxii06A18tR7AFDqOcHywfQ0SG66MJ1wfcK4WfmCeXptdl4MRr4yM6cjw5vwfOs7pXsPi8UcbDnxk\nQbI/K2zU75AQAKL8CnAkfQpaxWSbssrWEYtItkDsJ/g5iKO0v7a4XaFOEjZo0BIA/BglSJP2FK/o\n2cRqlWqdUQRq1zUfpT7T324k+yv9QHUpqIax6w0r7SklsNt9HqXZUrPphKA4qa7iOgFFI6b32zLJ\n3Tj/5UJcTEQHv1UDu71qoy0ogdwd53UD+X47b6YFP/2IQ/5kbtI9p0xy1uSkSRUEJh7tvTIaen49\nOk3sdK6UHd9DkD/Mp7zmfXmbKvruKMxgZh7siZsRhFhiug8DPXBo0+9llnkzPdgCuy+fnojuTmKH\nurAWObrpux7rdscEd6OoR26GxTudav49B9TpCQ/VI0OzaaAiHo7EYHa9TkW7x4n2sIyS1QioDcqS\nHqcIz7uaK/mn9i77fElGAObB2yfUPvV9lppH+1iWz2VPlFX5FWFUsSi1+52r4jhiIZkrqfZEpYQk\nMXjoJX860HOVFwRmDviJUzr9DTkU8KI2zuElz6AmLHvnIjuhvznKEFNPvHPINrqmRAn0CyLw0zSb\nnG2NHdM+uHlzEdCb4tCXaNUpI6cvsYadbkYFhR0yIV263LL4kHeL3hrnsd34TQBZ7cWbtpi3y47b\n2KZtkvJvMeM0uYgXXMC0B3BOewXOy3GQGB6gBeQoqKGj2lOJ5H/MfDxW6j1uH2uGy8qNYjPeSzCW\nGGQuiREDn9GNj3Vj6qN3IjPwi4qOwRqoPfMf0HHs8nJm00XYEmk0tda12Gu26T4+Uh+BCySqUnAC\nR1AkQAGI8bOcy4o+pmcjyoXC1nBZY0XGTNDKRbP8hg==\n`pragma protect end_protected\n", "num_lines": 98}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/*\n *******************************************************************************\n *\n * FIFO Generator - Verilog Behavioral Model\n *\n *******************************************************************************\n *\n * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.\n *\n * This file contains confidential and proprietary information\n * of Xilinx, Inc. and is protected under U.S. and\n * international copyright and other intellectual property\n * laws.\n *\n * DISCLAIMER\n * This disclaimer is not a license and does not grant any\n * rights to the materials distributed herewith. Except as\n * otherwise provided in a valid license issued to you by\n * Xilinx, and to the maximum extent permitted by applicable\n * law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n * (2) Xilinx shall not be liable (whether in contract or tort,\n * including negligence, or under any other theory of\n * liability) for any loss or damage of any kind or nature\n * related to, arising under or in connection with these\n * materials, including for any direct, or any indirect,\n * special, incidental, or consequential loss or damage\n * (including loss of data, profits, goodwill, or any type of\n * loss or damage suffered as a result of any action brought\n * by a third party) even if such damage or loss was\n * reasonably foreseeable or Xilinx had been advised of the\n * possibility of the same.\n *\n * CRITICAL APPLICATIONS\n * Xilinx products are not designed or intended to be fail-\n * safe, or for use in any application requiring fail-safe\n * performance, such as life-support or safety devices or\n * systems, Class III medical devices, nuclear facilities,\n * applications related to the deployment of airbags, or any\n * other applications that could lead to death, personal\n * injury, or severe property or environmental damage\n * (individually and collectively, \"Critical\n * Applications\"). Customer assumes the sole risk and\n * liability of any use of Xilinx products in Critical\n * Applications, subject only to applicable laws and\n * regulations governing limitations on product liability.\n *\n * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n * PART OF THIS FILE AT ALL TIMES.\n *\n *******************************************************************************\n *******************************************************************************\n *\n * Filename: fifo_generator_vlog_beh.v\n *\n * Author     : Xilinx\n *\n *******************************************************************************\n * Structure:\n * \n * fifo_generator_vlog_beh.v\n *    |\n *    +-fifo_generator_v13_2_1_bhv_ver_as\n *    |\n *    +-fifo_generator_v13_2_1_bhv_ver_ss\n *    |\n *    +-fifo_generator_v13_2_1_bhv_ver_preload0\n * \n *******************************************************************************\n * Description:\n *\n * The Verilog behavioral model for the FIFO Generator.\n *\n *   The behavioral model has three parts:\n *      - The behavioral model for independent clocks FIFOs (_as)\n *      - The behavioral model for common clock FIFOs (_ss)\n *      - The \"preload logic\" block which implements First-word Fall-through\n * \n *******************************************************************************\n * Description:\n *  The verilog behavioral model for the FIFO generator core.\n *\n *******************************************************************************\n */\n\n`timescale 1ps/1ps\n`ifndef TCQ\n `define TCQ 100\n`endif\n\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_vlog_beh\n  #(\n    //-----------------------------------------------------------------------\n    // Generic Declarations\n    //-----------------------------------------------------------------------\n    parameter C_COMMON_CLOCK                 = 0,\n    parameter C_COUNT_TYPE                   = 0,\n    parameter C_DATA_COUNT_WIDTH             = 2,\n    parameter C_DEFAULT_VALUE                = \"\",\n    parameter C_DIN_WIDTH                    = 8,\n    parameter C_DOUT_RST_VAL                 = \"\",\n    parameter C_DOUT_WIDTH                   = 8,\n    parameter C_ENABLE_RLOCS                 = 0,\n    parameter C_FAMILY                       = \"\",\n    parameter C_FULL_FLAGS_RST_VAL           = 1,\n    parameter C_HAS_ALMOST_EMPTY             = 0,\n    parameter C_HAS_ALMOST_FULL              = 0,\n    parameter C_HAS_BACKUP                   = 0,\n    parameter C_HAS_DATA_COUNT               = 0,\n    parameter C_HAS_INT_CLK                  = 0,\n    parameter C_HAS_MEMINIT_FILE             = 0,\n    parameter C_HAS_OVERFLOW                 = 0,\n    parameter C_HAS_RD_DATA_COUNT            = 0,\n    parameter C_HAS_RD_RST                   = 0,\n    parameter C_HAS_RST                      = 1,\n    parameter C_HAS_SRST                     = 0,\n    parameter C_HAS_UNDERFLOW                = 0,\n    parameter C_HAS_VALID                    = 0,\n    parameter C_HAS_WR_ACK                   = 0,\n    parameter C_HAS_WR_DATA_COUNT            = 0,\n    parameter C_HAS_WR_RST                   = 0,\n    parameter C_IMPLEMENTATION_TYPE          = 0,\n    parameter C_INIT_WR_PNTR_VAL             = 0,\n    parameter C_MEMORY_TYPE                  = 1,\n    parameter C_MIF_FILE_NAME                = \"\",\n    parameter C_OPTIMIZATION_MODE            = 0,\n    parameter C_OVERFLOW_LOW                 = 0,\n    parameter C_EN_SAFETY_CKT                = 0,\n    parameter C_PRELOAD_LATENCY              = 1,\n    parameter C_PRELOAD_REGS                 = 0,\n    parameter C_PRIM_FIFO_TYPE               = \"4kx4\",\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter C_PROG_EMPTY_TYPE              = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter C_PROG_FULL_TYPE               = 0,\n    parameter C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter C_RD_DEPTH                     = 256,\n    parameter C_RD_FREQ                      = 1,\n    parameter C_RD_PNTR_WIDTH                = 8,\n    parameter C_UNDERFLOW_LOW                = 0,\n    parameter C_USE_DOUT_RST                 = 0,\n    parameter C_USE_ECC                      = 0,\n    parameter C_USE_EMBEDDED_REG             = 0,\n    parameter C_USE_PIPELINE_REG             = 0,\n    parameter C_POWER_SAVING_MODE            = 0,\n    parameter C_USE_FIFO16_FLAGS             = 0,\n    parameter C_USE_FWFT_DATA_COUNT          = 0,\n    parameter C_VALID_LOW                    = 0,\n    parameter C_WR_ACK_LOW                   = 0,\n    parameter C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter C_WR_DEPTH                     = 256,\n    parameter C_WR_FREQ                      = 1,\n    parameter C_WR_PNTR_WIDTH                = 8,\n    parameter C_WR_RESPONSE_LATENCY          = 1,\n    parameter C_MSGON_VAL                    = 1,\n    parameter C_ENABLE_RST_SYNC              = 1,\n    parameter C_ERROR_INJECTION_TYPE         = 0,\n    parameter C_SYNCHRONIZER_STAGE           = 2,\n\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE               = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3\n    parameter C_AXI_TYPE                     = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3\n    parameter C_HAS_AXI_WR_CHANNEL           = 0,\n    parameter C_HAS_AXI_RD_CHANNEL           = 0,\n    parameter C_HAS_SLAVE_CE                 = 0,\n    parameter C_HAS_MASTER_CE                = 0,\n    parameter C_ADD_NGC_CONSTRAINT           = 0,\n    parameter C_USE_COMMON_UNDERFLOW         = 0,\n    parameter C_USE_COMMON_OVERFLOW          = 0,\n    parameter C_USE_DEFAULT_SETTINGS         = 0,\n\n    // AXI Full/Lite\n    parameter C_AXI_ID_WIDTH                 = 0,\n    parameter C_AXI_ADDR_WIDTH               = 0,\n    parameter C_AXI_DATA_WIDTH               = 0,\n    parameter C_AXI_LEN_WIDTH                = 8,\n    parameter C_AXI_LOCK_WIDTH               = 2,\n    parameter C_HAS_AXI_ID                   = 0,\n    parameter C_HAS_AXI_AWUSER               = 0,\n    parameter C_HAS_AXI_WUSER                = 0,\n    parameter C_HAS_AXI_BUSER                = 0,\n    parameter C_HAS_AXI_ARUSER               = 0,\n    parameter C_HAS_AXI_RUSER                = 0,\n    parameter C_AXI_ARUSER_WIDTH             = 0,\n    parameter C_AXI_AWUSER_WIDTH             = 0,\n    parameter C_AXI_WUSER_WIDTH              = 0,\n    parameter C_AXI_BUSER_WIDTH              = 0,\n    parameter C_AXI_RUSER_WIDTH              = 0,\n\n    // AXI Streaming\n    parameter C_HAS_AXIS_TDATA               = 0,\n    parameter C_HAS_AXIS_TID                 = 0,\n    parameter C_HAS_AXIS_TDEST               = 0,\n    parameter C_HAS_AXIS_TUSER               = 0,\n    parameter C_HAS_AXIS_TREADY              = 0,\n    parameter C_HAS_AXIS_TLAST               = 0,\n    parameter C_HAS_AXIS_TSTRB               = 0,\n    parameter C_HAS_AXIS_TKEEP               = 0,\n    parameter C_AXIS_TDATA_WIDTH             = 1,\n    parameter C_AXIS_TID_WIDTH               = 1,\n    parameter C_AXIS_TDEST_WIDTH             = 1,\n    parameter C_AXIS_TUSER_WIDTH             = 1,\n    parameter C_AXIS_TSTRB_WIDTH             = 1,\n    parameter C_AXIS_TKEEP_WIDTH             = 1,\n\n    // AXI Channel Type\n    // WACH --> Write Address Channel\n    // WDCH --> Write Data Channel\n    // WRCH --> Write Response Channel\n    // RACH --> Read Address Channel\n    // RDCH --> Read Data Channel\n    // AXIS --> AXI Streaming\n    parameter C_WACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic\n    parameter C_WDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_WRCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_AXIS_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n\n    // AXI Implementation Type\n    // 1 = Common Clock Block RAM FIFO\n    // 2 = Common Clock Distributed RAM FIFO\n    // 11 = Independent Clock Block RAM FIFO\n    // 12 = Independent Clock Distributed RAM FIFO\n    parameter C_IMPLEMENTATION_TYPE_WACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WRCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_AXIS     = 0,\n\n    // AXI FIFO Type\n    // 0 = Data FIFO\n    // 1 = Packet FIFO\n    // 2 = Low Latency Sync FIFO\n    // 3 = Low Latency Async FIFO\n    parameter C_APPLICATION_TYPE_WACH        = 0,\n    parameter C_APPLICATION_TYPE_WDCH        = 0,\n    parameter C_APPLICATION_TYPE_WRCH        = 0,\n    parameter C_APPLICATION_TYPE_RACH        = 0,\n    parameter C_APPLICATION_TYPE_RDCH        = 0,\n    parameter C_APPLICATION_TYPE_AXIS        = 0,\n\n    // AXI Built-in FIFO Primitive Type\n    // 512x36, 1kx18, 2kx9, 4kx4, etc\n    parameter C_PRIM_FIFO_TYPE_WACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WRCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_AXIS          = \"512x36\",\n\n    // Enable ECC\n    // 0 = ECC disabled\n    // 1 = ECC enabled\n    parameter C_USE_ECC_WACH                 = 0,\n    parameter C_USE_ECC_WDCH                 = 0,\n    parameter C_USE_ECC_WRCH                 = 0,\n    parameter C_USE_ECC_RACH                 = 0,\n    parameter C_USE_ECC_RDCH                 = 0,\n    parameter C_USE_ECC_AXIS                 = 0,\n\n    // ECC Error Injection Type\n    // 0 = No Error Injection\n    // 1 = Single Bit Error Injection\n    // 2 = Double Bit Error Injection\n    // 3 = Single Bit and Double Bit Error Injection\n    parameter C_ERROR_INJECTION_TYPE_WACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WRCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_AXIS    = 0,\n\n    // Input Data Width\n    // Accumulation of all AXI input signal's width\n    parameter C_DIN_WIDTH_WACH               = 1,\n    parameter C_DIN_WIDTH_WDCH               = 1,\n    parameter C_DIN_WIDTH_WRCH               = 1,\n    parameter C_DIN_WIDTH_RACH               = 1,\n    parameter C_DIN_WIDTH_RDCH               = 1,\n    parameter C_DIN_WIDTH_AXIS               = 1,\n\n    parameter C_WR_DEPTH_WACH                = 16,\n    parameter C_WR_DEPTH_WDCH                = 16,\n    parameter C_WR_DEPTH_WRCH                = 16,\n    parameter C_WR_DEPTH_RACH                = 16,\n    parameter C_WR_DEPTH_RDCH                = 16,\n    parameter C_WR_DEPTH_AXIS                = 16,\n\n    parameter C_WR_PNTR_WIDTH_WACH           = 4,\n    parameter C_WR_PNTR_WIDTH_WDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_WRCH           = 4,\n    parameter C_WR_PNTR_WIDTH_RACH           = 4,\n    parameter C_WR_PNTR_WIDTH_RDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_AXIS           = 4,\n\n    parameter C_HAS_DATA_COUNTS_WACH         = 0,\n    parameter C_HAS_DATA_COUNTS_WDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_WRCH         = 0,\n    parameter C_HAS_DATA_COUNTS_RACH         = 0,\n    parameter C_HAS_DATA_COUNTS_RDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_AXIS         = 0,\n\n    parameter C_HAS_PROG_FLAGS_WACH          = 0,\n    parameter C_HAS_PROG_FLAGS_WDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_WRCH          = 0,\n    parameter C_HAS_PROG_FLAGS_RACH          = 0,\n    parameter C_HAS_PROG_FLAGS_RDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_AXIS          = 0,\n\n    parameter C_PROG_FULL_TYPE_WACH          = 0,\n    parameter C_PROG_FULL_TYPE_WDCH          = 0,\n    parameter C_PROG_FULL_TYPE_WRCH          = 0,\n    parameter C_PROG_FULL_TYPE_RACH          = 0,\n    parameter C_PROG_FULL_TYPE_RDCH          = 0,\n    parameter C_PROG_FULL_TYPE_AXIS          = 0,\n\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS      = 0,\n\n    parameter C_PROG_EMPTY_TYPE_WACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WRCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_AXIS         = 0,\n\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS     = 0,\n\n    parameter C_REG_SLICE_MODE_WACH          = 0,\n    parameter C_REG_SLICE_MODE_WDCH          = 0,\n    parameter C_REG_SLICE_MODE_WRCH          = 0,\n    parameter C_REG_SLICE_MODE_RACH          = 0,\n    parameter C_REG_SLICE_MODE_RDCH          = 0,\n    parameter C_REG_SLICE_MODE_AXIS          = 0\n\n    )\n\n   (\n    //------------------------------------------------------------------------------\n    // Input and Output Declarations\n    //------------------------------------------------------------------------------\n\n    // Conventional FIFO Interface Signals\n    input                               backup,\n    input                               backup_marker,\n    input                               clk,\n    input                               rst,\n    input                               srst,\n    input                               wr_clk,\n    input                               wr_rst,\n    input                               rd_clk,\n    input                               rd_rst,\n    input [C_DIN_WIDTH-1:0]             din,\n    input                               wr_en,\n    input                               rd_en,\n    // Optional inputs\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_assert,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_negate,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_assert,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_negate,\n    input                               int_clk,\n    input                               injectdbiterr,\n    input                               injectsbiterr,\n    input                               sleep,\n\n    output [C_DOUT_WIDTH-1:0]           dout,\n    output                              full,\n    output                              almost_full,\n    output                              wr_ack,\n    output                              overflow,\n    output                              empty,\n    output                              almost_empty,\n    output                              valid,\n    output                              underflow,\n    output [C_DATA_COUNT_WIDTH-1:0]     data_count,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]  rd_data_count,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count,\n    output                              prog_full,\n    output                              prog_empty,\n    output                              sbiterr,\n    output                              dbiterr,\n    output                              wr_rst_busy,\n    output                              rd_rst_busy,\n\n\n    // AXI Global Signal\n    input                               m_aclk,\n    input                               s_aclk,\n    input                               s_aresetn,\n    input                               s_aclk_en,\n    input                               m_aclk_en,\n    \n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_awid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_awaddr,\n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_awlen,\n    input [3-1:0]                       s_axi_awsize,\n    input [2-1:0]                       s_axi_awburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_awlock,\n    input [4-1:0]                       s_axi_awcache,\n    input [3-1:0]                       s_axi_awprot,\n    input [4-1:0]                       s_axi_awqos,\n    input [4-1:0]                       s_axi_awregion,\n    input [C_AXI_AWUSER_WIDTH-1:0]      s_axi_awuser,\n    input                               s_axi_awvalid,\n    output                              s_axi_awready,\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_wid,\n    input [C_AXI_DATA_WIDTH-1:0]        s_axi_wdata,\n    input [C_AXI_DATA_WIDTH/8-1:0]      s_axi_wstrb,\n    input                               s_axi_wlast,\n    input [C_AXI_WUSER_WIDTH-1:0]       s_axi_wuser,\n    input                               s_axi_wvalid,\n    output                              s_axi_wready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_bid,\n    output [2-1:0]                      s_axi_bresp,\n    output [C_AXI_BUSER_WIDTH-1:0]      s_axi_buser,\n    output                              s_axi_bvalid,\n    input                               s_axi_bready,\n    \n    // AXI Full/Lite Master Write Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_awid,\n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_awlen,\n    output [3-1:0]                      m_axi_awsize,\n    output [2-1:0]                      m_axi_awburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_awlock,\n    output [4-1:0]                      m_axi_awcache,\n    output [3-1:0]                      m_axi_awprot,\n    output [4-1:0]                      m_axi_awqos,\n    output [4-1:0]                      m_axi_awregion,\n    output [C_AXI_AWUSER_WIDTH-1:0]     m_axi_awuser,\n    output                              m_axi_awvalid,\n    input                               m_axi_awready,\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_wid,\n    output [C_AXI_DATA_WIDTH-1:0]       m_axi_wdata,\n    output [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb,\n    output                              m_axi_wlast,\n    output [C_AXI_WUSER_WIDTH-1:0]      m_axi_wuser,\n    output                              m_axi_wvalid,\n    input                               m_axi_wready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_bid,\n    input [2-1:0]                       m_axi_bresp,\n    input [C_AXI_BUSER_WIDTH-1:0]       m_axi_buser,\n    input                               m_axi_bvalid,\n    output                              m_axi_bready,\n    \n    \n    // AXI Full/Lite Slave Read Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_arid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_araddr, \n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_arlen,\n    input [3-1:0]                       s_axi_arsize,\n    input [2-1:0]                       s_axi_arburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_arlock,\n    input [4-1:0]                       s_axi_arcache,\n    input [3-1:0]                       s_axi_arprot,\n    input [4-1:0]                       s_axi_arqos,\n    input [4-1:0]                       s_axi_arregion,\n    input [C_AXI_ARUSER_WIDTH-1:0]      s_axi_aruser,\n    input                               s_axi_arvalid,\n    output                              s_axi_arready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_rid,       \n    output [C_AXI_DATA_WIDTH-1:0]       s_axi_rdata, \n    output [2-1:0]                      s_axi_rresp,\n    output                              s_axi_rlast,\n    output [C_AXI_RUSER_WIDTH-1:0]      s_axi_ruser,\n    output                              s_axi_rvalid,\n    input                               s_axi_rready,\n    \n    \n    \n    // AXI Full/Lite Master Read Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_arid,        \n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,  \n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_arlen,\n    output [3-1:0]                      m_axi_arsize,\n    output [2-1:0]                      m_axi_arburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_arlock,\n    output [4-1:0]                      m_axi_arcache,\n    output [3-1:0]                      m_axi_arprot,\n    output [4-1:0]                      m_axi_arqos,\n    output [4-1:0]                      m_axi_arregion,\n    output [C_AXI_ARUSER_WIDTH-1:0]     m_axi_aruser,\n    output                              m_axi_arvalid,\n    input                               m_axi_arready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_rid,        \n    input [C_AXI_DATA_WIDTH-1:0]        m_axi_rdata,  \n    input [2-1:0]                       m_axi_rresp,\n    input                               m_axi_rlast,\n    input [C_AXI_RUSER_WIDTH-1:0]       m_axi_ruser,\n    input                               m_axi_rvalid,\n    output                              m_axi_rready,\n    \n    \n    // AXI Streaming Slave Signals (Write side)\n    input                               s_axis_tvalid,\n    output                              s_axis_tready,\n    input [C_AXIS_TDATA_WIDTH-1:0]      s_axis_tdata,\n    input [C_AXIS_TSTRB_WIDTH-1:0]      s_axis_tstrb,\n    input [C_AXIS_TKEEP_WIDTH-1:0]      s_axis_tkeep,\n    input                               s_axis_tlast,\n    input [C_AXIS_TID_WIDTH-1:0]        s_axis_tid,\n    input [C_AXIS_TDEST_WIDTH-1:0]      s_axis_tdest,\n    input [C_AXIS_TUSER_WIDTH-1:0]      s_axis_tuser,\n    \n    // AXI Streaming Master Signals (Read side)\n    output                              m_axis_tvalid,\n    input                               m_axis_tready,\n    output [C_AXIS_TDATA_WIDTH-1:0]     m_axis_tdata,\n    output [C_AXIS_TSTRB_WIDTH-1:0]     m_axis_tstrb,\n    output [C_AXIS_TKEEP_WIDTH-1:0]     m_axis_tkeep,\n    output                              m_axis_tlast,\n    output [C_AXIS_TID_WIDTH-1:0]       m_axis_tid,\n    output [C_AXIS_TDEST_WIDTH-1:0]     m_axis_tdest,\n    output [C_AXIS_TUSER_WIDTH-1:0]     m_axis_tuser,\n    \n           \n    \n    \n    // AXI Full/Lite Write Address Channel signals\n    input                               axi_aw_injectsbiterr,\n    input                               axi_aw_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_rd_data_count,\n    output                              axi_aw_sbiterr,\n    output                              axi_aw_dbiterr,\n    output                              axi_aw_overflow,\n    output                              axi_aw_underflow,\n    output                              axi_aw_prog_full,\n    output                              axi_aw_prog_empty,\n    \n    \n    // AXI Full/Lite Write Data Channel signals\n    input                               axi_w_injectsbiterr,\n    input                               axi_w_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_rd_data_count,\n    output                              axi_w_sbiterr,\n    output                              axi_w_dbiterr,\n    output                              axi_w_overflow,\n    output                              axi_w_underflow,\n    output                              axi_w_prog_full,\n    output                              axi_w_prog_empty,\n    \n    \n    // AXI Full/Lite Write Response Channel signals\n    input                               axi_b_injectsbiterr,\n    input                               axi_b_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_rd_data_count,\n    output                              axi_b_sbiterr,\n    output                              axi_b_dbiterr,\n    output                              axi_b_overflow,\n    output                              axi_b_underflow,\n    output                              axi_b_prog_full,\n    output                              axi_b_prog_empty,\n    \n    \n    \n    // AXI Full/Lite Read Address Channel signals\n    input                               axi_ar_injectsbiterr,\n    input                               axi_ar_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_rd_data_count,\n    output                              axi_ar_sbiterr,\n    output                              axi_ar_dbiterr,\n    output                              axi_ar_overflow,\n    output                              axi_ar_underflow,\n    output                              axi_ar_prog_full,\n    output                              axi_ar_prog_empty,\n\n    \n    // AXI Full/Lite Read Data Channel Signals\n    input                               axi_r_injectsbiterr,\n    input                               axi_r_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_rd_data_count,\n    output                              axi_r_sbiterr,\n    output                              axi_r_dbiterr,\n    output                              axi_r_overflow,\n    output                              axi_r_underflow,\n    output                              axi_r_prog_full,\n    output                              axi_r_prog_empty,\n\n    \n    // AXI Streaming FIFO Related Signals\n    input                               axis_injectsbiterr,\n    input                               axis_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_wr_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_rd_data_count,\n    output                              axis_sbiterr,\n    output                              axis_dbiterr,\n    output                              axis_overflow,\n    output                              axis_underflow,\n    output                              axis_prog_full,\n    output                              axis_prog_empty\n\n    );\n\n    wire                              BACKUP;\n    wire                              BACKUP_MARKER;\n    wire                              CLK;\n    wire                              RST;\n    wire                              SRST;\n    wire                              WR_CLK;\n    wire                              WR_RST;\n    wire                              RD_CLK;\n    wire                              RD_RST;\n    wire [C_DIN_WIDTH-1:0]            DIN;\n    wire                              WR_EN;\n    wire                              RD_EN;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_ASSERT;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_NEGATE;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_ASSERT;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_NEGATE;\n    wire                              INT_CLK;\n    wire                              INJECTDBITERR;\n    wire                              INJECTSBITERR;\n    wire                              SLEEP;\n    wire [C_DOUT_WIDTH-1:0]           DOUT;\n    wire                              FULL;\n    wire                              ALMOST_FULL;\n    wire                              WR_ACK;\n    wire                              OVERFLOW;\n    wire                              EMPTY;\n    wire                              ALMOST_EMPTY;\n    wire                              VALID;\n    wire                              UNDERFLOW;\n    wire [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT;\n    wire [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT;\n    wire                              PROG_FULL;\n    wire                              PROG_EMPTY;\n    wire                              SBITERR;\n    wire                              DBITERR;\n    wire                              WR_RST_BUSY;\n    wire                              RD_RST_BUSY;\n    wire                              M_ACLK;\n    wire                              S_ACLK;\n    wire                              S_ARESETN;\n    wire                              S_ACLK_EN;\n    wire                              M_ACLK_EN;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_AWLEN;\n    wire [3-1:0]                      S_AXI_AWSIZE;\n    wire [2-1:0]                      S_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_AWLOCK;\n    wire [4-1:0]                      S_AXI_AWCACHE;\n    wire [3-1:0]                      S_AXI_AWPROT;\n    wire [4-1:0]                      S_AXI_AWQOS;\n    wire [4-1:0]                      S_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     S_AXI_AWUSER;\n    wire                              S_AXI_AWVALID;\n    wire                              S_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     S_AXI_WSTRB;\n    wire                              S_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      S_AXI_WUSER;\n    wire                              S_AXI_WVALID;\n    wire                              S_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_BID;\n    wire [2-1:0]                      S_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      S_AXI_BUSER;\n    wire                              S_AXI_BVALID;\n    wire                              S_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_AWLEN;\n    wire [3-1:0]                      M_AXI_AWSIZE;\n    wire [2-1:0]                      M_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_AWLOCK;\n    wire [4-1:0]                      M_AXI_AWCACHE;\n    wire [3-1:0]                      M_AXI_AWPROT;\n    wire [4-1:0]                      M_AXI_AWQOS;\n    wire [4-1:0]                      M_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     M_AXI_AWUSER;\n    wire                              M_AXI_AWVALID;\n    wire                              M_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     M_AXI_WSTRB;\n    wire                              M_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      M_AXI_WUSER;\n    wire                              M_AXI_WVALID;\n    wire                              M_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_BID;\n    wire [2-1:0]                      M_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      M_AXI_BUSER;\n    wire                              M_AXI_BVALID;\n    wire                              M_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_ARID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_ARADDR; \n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_ARLEN;\n    wire [3-1:0]                      S_AXI_ARSIZE;\n    wire [2-1:0]                      S_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_ARLOCK;\n    wire [4-1:0]                      S_AXI_ARCACHE;\n    wire [3-1:0]                      S_AXI_ARPROT;\n    wire [4-1:0]                      S_AXI_ARQOS;\n    wire [4-1:0]                      S_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     S_AXI_ARUSER;\n    wire                              S_AXI_ARVALID;\n    wire                              S_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_RID;       \n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_RDATA; \n    wire [2-1:0]                      S_AXI_RRESP;\n    wire                              S_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      S_AXI_RUSER;\n    wire                              S_AXI_RVALID;\n    wire                              S_AXI_RREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_ARID;        \n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_ARADDR;  \n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_ARLEN;\n    wire [3-1:0]                      M_AXI_ARSIZE;\n    wire [2-1:0]                      M_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_ARLOCK;\n    wire [4-1:0]                      M_AXI_ARCACHE;\n    wire [3-1:0]                      M_AXI_ARPROT;\n    wire [4-1:0]                      M_AXI_ARQOS;\n    wire [4-1:0]                      M_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     M_AXI_ARUSER;\n    wire                              M_AXI_ARVALID;\n    wire                              M_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_RID;        \n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_RDATA;  \n    wire [2-1:0]                      M_AXI_RRESP;\n    wire                              M_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      M_AXI_RUSER;\n    wire                              M_AXI_RVALID;\n    wire                              M_AXI_RREADY;\n    wire                              S_AXIS_TVALID;\n    wire                              S_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     S_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     S_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     S_AXIS_TKEEP;\n    wire                              S_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       S_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     S_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     S_AXIS_TUSER;\n    wire                              M_AXIS_TVALID;\n    wire                              M_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     M_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     M_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     M_AXIS_TKEEP;\n    wire                              M_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       M_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     M_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     M_AXIS_TUSER;\n    wire                              AXI_AW_INJECTSBITERR;\n    wire                              AXI_AW_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_RD_DATA_COUNT;\n    wire                              AXI_AW_SBITERR;\n    wire                              AXI_AW_DBITERR;\n    wire                              AXI_AW_OVERFLOW;\n    wire                              AXI_AW_UNDERFLOW;\n    wire                              AXI_AW_PROG_FULL;\n    wire                              AXI_AW_PROG_EMPTY;\n    wire                              AXI_W_INJECTSBITERR;\n    wire                              AXI_W_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_RD_DATA_COUNT;\n    wire                              AXI_W_SBITERR;\n    wire                              AXI_W_DBITERR;\n    wire                              AXI_W_OVERFLOW;\n    wire                              AXI_W_UNDERFLOW;\n    wire                              AXI_W_PROG_FULL;\n    wire                              AXI_W_PROG_EMPTY;\n    wire                              AXI_B_INJECTSBITERR;\n    wire                              AXI_B_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_RD_DATA_COUNT;\n    wire                              AXI_B_SBITERR;\n    wire                              AXI_B_DBITERR;\n    wire                              AXI_B_OVERFLOW;\n    wire                              AXI_B_UNDERFLOW;\n    wire                              AXI_B_PROG_FULL;\n    wire                              AXI_B_PROG_EMPTY;\n    wire                              AXI_AR_INJECTSBITERR;\n    wire                              AXI_AR_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_RD_DATA_COUNT;\n    wire                              AXI_AR_SBITERR;\n    wire                              AXI_AR_DBITERR;\n    wire                              AXI_AR_OVERFLOW;\n    wire                              AXI_AR_UNDERFLOW;\n    wire                              AXI_AR_PROG_FULL;\n    wire                              AXI_AR_PROG_EMPTY;\n    wire                              AXI_R_INJECTSBITERR;\n    wire                              AXI_R_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_RD_DATA_COUNT;\n    wire                              AXI_R_SBITERR;\n    wire                              AXI_R_DBITERR;\n    wire                              AXI_R_OVERFLOW;\n    wire                              AXI_R_UNDERFLOW;\n    wire                              AXI_R_PROG_FULL;\n    wire                              AXI_R_PROG_EMPTY;\n    wire                              AXIS_INJECTSBITERR;\n    wire                              AXIS_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_RD_DATA_COUNT;\n    wire                              AXIS_SBITERR;\n    wire                              AXIS_DBITERR;\n    wire                              AXIS_OVERFLOW;\n    wire                              AXIS_UNDERFLOW;\n    wire                              AXIS_PROG_FULL;\n    wire                              AXIS_PROG_EMPTY;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count_in;\n    wire                              wr_rst_int;\n    wire                              rd_rst_int;\n    wire                              wr_rst_busy_o;\n    wire                              wr_rst_busy_ntve;\n    wire                              wr_rst_busy_axis;\n    wire                              wr_rst_busy_wach;\n    wire                              wr_rst_busy_wdch;\n    wire                              wr_rst_busy_wrch;\n    wire                              wr_rst_busy_rach;\n    wire                              wr_rst_busy_rdch;\n\n\n\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n\n\n\n    // Conventional FIFO Interface Signals\n    assign BACKUP                 = backup;\n    assign BACKUP_MARKER          = backup_marker;\n    assign CLK                    = clk;\n    assign RST                    = rst;\n    assign SRST                   = srst;\n    assign WR_CLK                 = wr_clk;\n    assign WR_RST                 = wr_rst;\n    assign RD_CLK                 = rd_clk;\n    assign RD_RST                 = rd_rst;\n    assign WR_EN                  = wr_en;\n    assign RD_EN                  = rd_en;\n    assign INT_CLK                = int_clk;\n    assign INJECTDBITERR          = injectdbiterr;\n    assign INJECTSBITERR          = injectsbiterr;\n    assign SLEEP                  = sleep;\n    assign full                   = FULL;\n    assign almost_full            = ALMOST_FULL;\n    assign wr_ack                 = WR_ACK;\n    assign overflow               = OVERFLOW;\n    assign empty                  = EMPTY;\n    assign almost_empty           = ALMOST_EMPTY;\n    assign valid                  = VALID;\n    assign underflow              = UNDERFLOW;\n    assign prog_full              = PROG_FULL;\n    assign prog_empty             = PROG_EMPTY;\n    assign sbiterr                = SBITERR;\n    assign dbiterr                = DBITERR;\n//    assign wr_rst_busy            = WR_RST_BUSY | wr_rst_busy_o;\n    assign wr_rst_busy            = wr_rst_busy_o;\n    assign rd_rst_busy            = RD_RST_BUSY;\n    assign M_ACLK                 = m_aclk;\n    assign S_ACLK                 = s_aclk;\n    assign S_ARESETN              = s_aresetn;\n    assign S_ACLK_EN              = s_aclk_en;\n    assign M_ACLK_EN              = m_aclk_en;\n    assign S_AXI_AWVALID          = s_axi_awvalid;\n    assign s_axi_awready          = S_AXI_AWREADY;\n    assign S_AXI_WLAST            = s_axi_wlast;\n    assign S_AXI_WVALID           = s_axi_wvalid;\n    assign s_axi_wready           = S_AXI_WREADY;\n    assign s_axi_bvalid           = S_AXI_BVALID;\n    assign S_AXI_BREADY           = s_axi_bready;\n    assign m_axi_awvalid          = M_AXI_AWVALID;\n    assign M_AXI_AWREADY          = m_axi_awready;\n    assign m_axi_wlast            = M_AXI_WLAST;\n    assign m_axi_wvalid           = M_AXI_WVALID;\n    assign M_AXI_WREADY           = m_axi_wready;\n    assign M_AXI_BVALID           = m_axi_bvalid;\n    assign m_axi_bready           = M_AXI_BREADY;\n    assign S_AXI_ARVALID          = s_axi_arvalid;\n    assign s_axi_arready          = S_AXI_ARREADY;\n    assign s_axi_rlast            = S_AXI_RLAST;\n    assign s_axi_rvalid           = S_AXI_RVALID;\n    assign S_AXI_RREADY           = s_axi_rready;\n    assign m_axi_arvalid          = M_AXI_ARVALID;\n    assign M_AXI_ARREADY          = m_axi_arready;\n    assign M_AXI_RLAST            = m_axi_rlast;\n    assign M_AXI_RVALID           = m_axi_rvalid;\n    assign m_axi_rready           = M_AXI_RREADY;\n    assign S_AXIS_TVALID          = s_axis_tvalid;\n    assign s_axis_tready          = S_AXIS_TREADY;\n    assign S_AXIS_TLAST           = s_axis_tlast;\n    assign m_axis_tvalid          = M_AXIS_TVALID;\n    assign M_AXIS_TREADY          = m_axis_tready;\n    assign m_axis_tlast           = M_AXIS_TLAST;\n    assign AXI_AW_INJECTSBITERR   = axi_aw_injectsbiterr;\n    assign AXI_AW_INJECTDBITERR   = axi_aw_injectdbiterr;\n    assign axi_aw_sbiterr         = AXI_AW_SBITERR;\n    assign axi_aw_dbiterr         = AXI_AW_DBITERR;\n    assign axi_aw_overflow        = AXI_AW_OVERFLOW;\n    assign axi_aw_underflow       = AXI_AW_UNDERFLOW;\n    assign axi_aw_prog_full       = AXI_AW_PROG_FULL;\n    assign axi_aw_prog_empty      = AXI_AW_PROG_EMPTY;\n    assign AXI_W_INJECTSBITERR    = axi_w_injectsbiterr;\n    assign AXI_W_INJECTDBITERR    = axi_w_injectdbiterr;\n    assign axi_w_sbiterr          = AXI_W_SBITERR;\n    assign axi_w_dbiterr          = AXI_W_DBITERR;\n    assign axi_w_overflow         = AXI_W_OVERFLOW;\n    assign axi_w_underflow        = AXI_W_UNDERFLOW;\n    assign axi_w_prog_full        = AXI_W_PROG_FULL;\n    assign axi_w_prog_empty       = AXI_W_PROG_EMPTY;\n    assign AXI_B_INJECTSBITERR    = axi_b_injectsbiterr;\n    assign AXI_B_INJECTDBITERR    = axi_b_injectdbiterr;\n    assign axi_b_sbiterr          = AXI_B_SBITERR;\n    assign axi_b_dbiterr          = AXI_B_DBITERR;\n    assign axi_b_overflow         = AXI_B_OVERFLOW;\n    assign axi_b_underflow        = AXI_B_UNDERFLOW;\n    assign axi_b_prog_full        = AXI_B_PROG_FULL;\n    assign axi_b_prog_empty       = AXI_B_PROG_EMPTY;\n    assign AXI_AR_INJECTSBITERR   = axi_ar_injectsbiterr;\n    assign AXI_AR_INJECTDBITERR   = axi_ar_injectdbiterr;\n    assign axi_ar_sbiterr         = AXI_AR_SBITERR;\n    assign axi_ar_dbiterr         = AXI_AR_DBITERR;\n    assign axi_ar_overflow        = AXI_AR_OVERFLOW;\n    assign axi_ar_underflow       = AXI_AR_UNDERFLOW;\n    assign axi_ar_prog_full       = AXI_AR_PROG_FULL;\n    assign axi_ar_prog_empty      = AXI_AR_PROG_EMPTY;\n    assign AXI_R_INJECTSBITERR    = axi_r_injectsbiterr;\n    assign AXI_R_INJECTDBITERR    = axi_r_injectdbiterr;\n    assign axi_r_sbiterr          = AXI_R_SBITERR;\n    assign axi_r_dbiterr          = AXI_R_DBITERR;\n    assign axi_r_overflow         = AXI_R_OVERFLOW;\n    assign axi_r_underflow        = AXI_R_UNDERFLOW;\n    assign axi_r_prog_full        = AXI_R_PROG_FULL;\n    assign axi_r_prog_empty       = AXI_R_PROG_EMPTY;\n    assign AXIS_INJECTSBITERR     = axis_injectsbiterr;\n    assign AXIS_INJECTDBITERR     = axis_injectdbiterr;\n    assign axis_sbiterr           = AXIS_SBITERR;\n    assign axis_dbiterr           = AXIS_DBITERR;\n    assign axis_overflow          = AXIS_OVERFLOW;\n    assign axis_underflow         = AXIS_UNDERFLOW;\n    assign axis_prog_full         = AXIS_PROG_FULL;\n    assign axis_prog_empty        = AXIS_PROG_EMPTY;\n\n\n    assign DIN                       = din;\n    assign PROG_EMPTY_THRESH         = prog_empty_thresh;\n    assign PROG_EMPTY_THRESH_ASSERT  = prog_empty_thresh_assert;\n    assign PROG_EMPTY_THRESH_NEGATE  = prog_empty_thresh_negate;\n    assign PROG_FULL_THRESH          = prog_full_thresh;\n    assign PROG_FULL_THRESH_ASSERT   = prog_full_thresh_assert;\n    assign PROG_FULL_THRESH_NEGATE   = prog_full_thresh_negate;\n    assign dout                      = DOUT;\n    assign data_count                = DATA_COUNT;\n    assign rd_data_count             = RD_DATA_COUNT;\n    assign wr_data_count             = WR_DATA_COUNT;\n    assign S_AXI_AWID                = s_axi_awid;\n    assign S_AXI_AWADDR              = s_axi_awaddr;\n    assign S_AXI_AWLEN               = s_axi_awlen;\n    assign S_AXI_AWSIZE              = s_axi_awsize;\n    assign S_AXI_AWBURST             = s_axi_awburst;\n    assign S_AXI_AWLOCK              = s_axi_awlock;\n    assign S_AXI_AWCACHE             = s_axi_awcache;\n    assign S_AXI_AWPROT              = s_axi_awprot;\n    assign S_AXI_AWQOS               = s_axi_awqos;\n    assign S_AXI_AWREGION            = s_axi_awregion;\n    assign S_AXI_AWUSER              = s_axi_awuser;\n    assign S_AXI_WID                 = s_axi_wid;\n    assign S_AXI_WDATA               = s_axi_wdata;\n    assign S_AXI_WSTRB               = s_axi_wstrb;\n    assign S_AXI_WUSER               = s_axi_wuser;\n    assign s_axi_bid                 = S_AXI_BID;\n    assign s_axi_bresp               = S_AXI_BRESP;\n    assign s_axi_buser               = S_AXI_BUSER;\n    assign m_axi_awid                = M_AXI_AWID;\n    assign m_axi_awaddr              = M_AXI_AWADDR;\n    assign m_axi_awlen               = M_AXI_AWLEN;\n    assign m_axi_awsize              = M_AXI_AWSIZE;\n    assign m_axi_awburst             = M_AXI_AWBURST;\n    assign m_axi_awlock              = M_AXI_AWLOCK;\n    assign m_axi_awcache             = M_AXI_AWCACHE;\n    assign m_axi_awprot              = M_AXI_AWPROT;\n    assign m_axi_awqos               = M_AXI_AWQOS;\n    assign m_axi_awregion            = M_AXI_AWREGION;\n    assign m_axi_awuser              = M_AXI_AWUSER;\n    assign m_axi_wid                 = M_AXI_WID;\n    assign m_axi_wdata               = M_AXI_WDATA;\n    assign m_axi_wstrb               = M_AXI_WSTRB;\n    assign m_axi_wuser               = M_AXI_WUSER;\n    assign M_AXI_BID                 = m_axi_bid;\n    assign M_AXI_BRESP               = m_axi_bresp;\n    assign M_AXI_BUSER               = m_axi_buser;\n    assign S_AXI_ARID                = s_axi_arid;\n    assign S_AXI_ARADDR              = s_axi_araddr; \n    assign S_AXI_ARLEN               = s_axi_arlen;\n    assign S_AXI_ARSIZE              = s_axi_arsize;\n    assign S_AXI_ARBURST             = s_axi_arburst;\n    assign S_AXI_ARLOCK              = s_axi_arlock;\n    assign S_AXI_ARCACHE             = s_axi_arcache;\n    assign S_AXI_ARPROT              = s_axi_arprot;\n    assign S_AXI_ARQOS               = s_axi_arqos;\n    assign S_AXI_ARREGION            = s_axi_arregion;\n    assign S_AXI_ARUSER              = s_axi_aruser;\n    assign s_axi_rid                 = S_AXI_RID;\n    assign s_axi_rdata               = S_AXI_RDATA;\n    assign s_axi_rresp               = S_AXI_RRESP;\n    assign s_axi_ruser               = S_AXI_RUSER;\n    assign m_axi_arid                = M_AXI_ARID;        \n    assign m_axi_araddr              = M_AXI_ARADDR;  \n    assign m_axi_arlen               = M_AXI_ARLEN;\n    assign m_axi_arsize              = M_AXI_ARSIZE;\n    assign m_axi_arburst             = M_AXI_ARBURST;\n    assign m_axi_arlock              = M_AXI_ARLOCK;\n    assign m_axi_arcache             = M_AXI_ARCACHE;\n    assign m_axi_arprot              = M_AXI_ARPROT;\n    assign m_axi_arqos               = M_AXI_ARQOS;\n    assign m_axi_arregion            = M_AXI_ARREGION;\n    assign m_axi_aruser              = M_AXI_ARUSER;\n    assign M_AXI_RID                 = m_axi_rid;        \n    assign M_AXI_RDATA               = m_axi_rdata;  \n    assign M_AXI_RRESP               = m_axi_rresp;\n    assign M_AXI_RUSER               = m_axi_ruser;\n    assign S_AXIS_TDATA              = s_axis_tdata;\n    assign S_AXIS_TSTRB              = s_axis_tstrb;\n    assign S_AXIS_TKEEP              = s_axis_tkeep;\n    assign S_AXIS_TID                = s_axis_tid;\n    assign S_AXIS_TDEST              = s_axis_tdest;\n    assign S_AXIS_TUSER              = s_axis_tuser;\n    assign m_axis_tdata              = M_AXIS_TDATA;\n    assign m_axis_tstrb              = M_AXIS_TSTRB;\n    assign m_axis_tkeep              = M_AXIS_TKEEP;\n    assign m_axis_tid                = M_AXIS_TID;\n    assign m_axis_tdest              = M_AXIS_TDEST;\n    assign m_axis_tuser              = M_AXIS_TUSER;\n    assign AXI_AW_PROG_FULL_THRESH   = axi_aw_prog_full_thresh;\n    assign AXI_AW_PROG_EMPTY_THRESH  = axi_aw_prog_empty_thresh;\n    assign axi_aw_data_count         = AXI_AW_DATA_COUNT;\n    assign axi_aw_wr_data_count      = AXI_AW_WR_DATA_COUNT;\n    assign axi_aw_rd_data_count      = AXI_AW_RD_DATA_COUNT;\n    assign AXI_W_PROG_FULL_THRESH    = axi_w_prog_full_thresh;\n    assign AXI_W_PROG_EMPTY_THRESH   = axi_w_prog_empty_thresh;\n    assign axi_w_data_count          = AXI_W_DATA_COUNT;\n    assign axi_w_wr_data_count       = AXI_W_WR_DATA_COUNT;\n    assign axi_w_rd_data_count       = AXI_W_RD_DATA_COUNT;\n    assign AXI_B_PROG_FULL_THRESH    = axi_b_prog_full_thresh;\n    assign AXI_B_PROG_EMPTY_THRESH   = axi_b_prog_empty_thresh;\n    assign axi_b_data_count          = AXI_B_DATA_COUNT;\n    assign axi_b_wr_data_count       = AXI_B_WR_DATA_COUNT;\n    assign axi_b_rd_data_count       = AXI_B_RD_DATA_COUNT;\n    assign AXI_AR_PROG_FULL_THRESH   = axi_ar_prog_full_thresh;\n    assign AXI_AR_PROG_EMPTY_THRESH  = axi_ar_prog_empty_thresh;\n    assign axi_ar_data_count         = AXI_AR_DATA_COUNT;\n    assign axi_ar_wr_data_count      = AXI_AR_WR_DATA_COUNT;\n    assign axi_ar_rd_data_count      = AXI_AR_RD_DATA_COUNT;\n    assign AXI_R_PROG_FULL_THRESH    = axi_r_prog_full_thresh;\n    assign AXI_R_PROG_EMPTY_THRESH   = axi_r_prog_empty_thresh;\n    assign axi_r_data_count          = AXI_R_DATA_COUNT;\n    assign axi_r_wr_data_count       = AXI_R_WR_DATA_COUNT;\n    assign axi_r_rd_data_count       = AXI_R_RD_DATA_COUNT;\n    assign AXIS_PROG_FULL_THRESH     = axis_prog_full_thresh;\n    assign AXIS_PROG_EMPTY_THRESH    = axis_prog_empty_thresh;\n    assign axis_data_count           = AXIS_DATA_COUNT;\n    assign axis_wr_data_count        = AXIS_WR_DATA_COUNT;\n    assign axis_rd_data_count        = AXIS_RD_DATA_COUNT;\n\n\n  generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_COMMON_CLOCK \t\t(C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DATA_COUNT_WIDTH\t\t(C_DATA_COUNT_WIDTH),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH),\n        .C_DOUT_RST_VAL\t\t\t(C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),\n        .C_DOUT_WIDTH\t\t\t(C_DOUT_WIDTH),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n        .C_HAS_ALMOST_EMPTY\t\t(C_HAS_ALMOST_EMPTY),\n        .C_HAS_ALMOST_FULL\t\t(C_HAS_ALMOST_FULL),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_DATA_COUNT\t\t(C_HAS_DATA_COUNT),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_HAS_RD_DATA_COUNT\t\t(C_HAS_RD_DATA_COUNT),\n        .C_HAS_RD_RST\t\t\t(C_HAS_RD_RST),\n        .C_HAS_RST\t\t\t(C_HAS_RST),\n        .C_HAS_SRST\t\t\t(C_HAS_SRST),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_HAS_VALID\t\t\t(C_HAS_VALID),\n        .C_HAS_WR_ACK\t\t\t(C_HAS_WR_ACK),\n        .C_HAS_WR_DATA_COUNT\t\t(C_HAS_WR_DATA_COUNT),\n        .C_HAS_WR_RST\t\t\t(C_HAS_WR_RST),\n        .C_IMPLEMENTATION_TYPE\t\t(C_IMPLEMENTATION_TYPE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_MEMORY_TYPE\t\t\t(C_MEMORY_TYPE),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n        .C_PRELOAD_LATENCY\t\t(C_PRELOAD_LATENCY),\n        .C_PRELOAD_REGS\t\t\t(C_PRELOAD_REGS),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL),\n        .C_PROG_EMPTY_THRESH_NEGATE_VAL\t(C_PROG_EMPTY_THRESH_NEGATE_VAL),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL),\n        .C_PROG_FULL_THRESH_NEGATE_VAL\t(C_PROG_FULL_THRESH_NEGATE_VAL),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_RD_DATA_COUNT_WIDTH),\n        .C_RD_DEPTH\t\t\t(C_RD_DEPTH),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_RD_PNTR_WIDTH\t\t(C_RD_PNTR_WIDTH),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n        .C_USE_ECC                      (C_USE_ECC),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_EN_SAFETY_CKT\t\t(C_EN_SAFETY_CKT),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_USE_FWFT_DATA_COUNT\t\t(C_USE_FWFT_DATA_COUNT),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_DATA_COUNT_WIDTH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (C_ENABLE_RST_SYNC),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE),\n        .C_AXI_TYPE                     (C_AXI_TYPE),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE)\n      )\n    fifo_generator_v13_2_1_conv_dut\n      (\n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .CLK                      (CLK),\n        .RST                      (RST),\n        .SRST                     (SRST),\n        .WR_CLK                   (WR_CLK),\n        .WR_RST                   (WR_RST),\n        .RD_CLK                   (RD_CLK),\n        .RD_RST                   (RD_RST),\n        .DIN                      (DIN),\n        .WR_EN                    (WR_EN),\n        .RD_EN                    (RD_EN),\n        .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),\n        .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),\n        .PROG_FULL_THRESH         (PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),\n        .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),\n        .INT_CLK                  (INT_CLK),\n        .INJECTDBITERR            (INJECTDBITERR), \n        .INJECTSBITERR            (INJECTSBITERR),\n  \n        .DOUT                     (DOUT),\n        .FULL                     (FULL),\n        .ALMOST_FULL              (ALMOST_FULL),\n        .WR_ACK                   (WR_ACK),\n        .OVERFLOW                 (OVERFLOW),\n        .EMPTY                    (EMPTY),\n        .ALMOST_EMPTY             (ALMOST_EMPTY),\n        .VALID                    (VALID),\n        .UNDERFLOW                (UNDERFLOW),\n        .DATA_COUNT               (DATA_COUNT),\n        .RD_DATA_COUNT            (RD_DATA_COUNT),\n        .WR_DATA_COUNT            (wr_data_count_in),\n        .PROG_FULL                (PROG_FULL),\n        .PROG_EMPTY               (PROG_EMPTY),\n        .SBITERR                  (SBITERR),\n        .DBITERR                  (DBITERR),\n        .wr_rst_busy_o            (wr_rst_busy_o),\n        .wr_rst_busy              (wr_rst_busy_i),\n        .rd_rst_busy              (rd_rst_busy),\n        .wr_rst_i_out             (wr_rst_int),\n        .rd_rst_i_out             (rd_rst_int)\n       );\n  end endgenerate\n\n\n\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n  localparam C_AXI_SIZE_WIDTH   = 3;\n  localparam C_AXI_BURST_WIDTH  = 2;\n  localparam C_AXI_CACHE_WIDTH  = 4;\n  localparam C_AXI_PROT_WIDTH   = 3;\n  localparam C_AXI_QOS_WIDTH    = 4;\n  localparam C_AXI_REGION_WIDTH = 4;\n  localparam C_AXI_BRESP_WIDTH  = 2;\n  localparam C_AXI_RRESP_WIDTH  = 2;\n\n  localparam IS_AXI_STREAMING  = C_INTERFACE_TYPE == 1 ? 1 : 0;\n  localparam TDATA_OFFSET      = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;\n  localparam TSTRB_OFFSET      = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;\n  localparam TKEEP_OFFSET      = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;\n  localparam TID_OFFSET        = C_HAS_AXIS_TID   == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;\n  localparam TDEST_OFFSET      = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;\n  localparam TUSER_OFFSET      = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;\n  localparam LOG_DEPTH_AXIS    = find_log2(C_WR_DEPTH_AXIS); \n  localparam LOG_WR_DEPTH      = find_log2(C_WR_DEPTH); \n\n\n  function [LOG_DEPTH_AXIS-1:0] bin2gray;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      begin\n         bin2gray = x ^ (x>>1);\n      end\n   endfunction\n\n  function [LOG_DEPTH_AXIS-1:0] gray2bin;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      integer                i;\n      begin\n         gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];\n         for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin\n            gray2bin[i] =  gray2bin[i+1] ^ x[i];\n         end\n      end\n   endfunction\n\nwire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;\nwire  [LOG_WR_DEPTH-1 : 0]  w_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;\nreg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;\nwire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;\nwire [LOG_WR_DEPTH : 0] r_inv_pad;\nwire [LOG_WR_DEPTH-1 : 0] d_cnt;\nreg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;\nreg adj_w_cnt_rd_pad_0 = 0;\nreg r_inv_pad_0 = 0;\n\n\n   genvar l;\n\n   generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage\n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (LOG_WR_DEPTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_int), \n         .CLK      (RD_CLK), \n         .DIN      (w_q[l-1]), \n         .DOUT     (w_q[l])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter\n    assign wr_eop_ad = WR_EN & !(FULL);\n    assign rd_eop_ad = RD_EN & !(EMPTY);\n\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt    <= 1'b0;\n      else if (wr_eop_ad)\n        w_cnt    <= w_cnt + 1;\n    end\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt_gc    <= 1'b0;\n      else \n        w_cnt_gc    <= bin2gray(w_cnt);\n    end\n\n\n    assign  w_q[0]  = w_cnt_gc;\n    assign  w_cnt_gc_asreg_last       = w_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        w_cnt_rd    <= 1'b0;\n      else \n        w_cnt_rd    <= gray2bin(w_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        r_cnt    <= 1'b0;\n      else if (rd_eop_ad)\n        r_cnt    <= r_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;\n   assign r_inv_pad[LOG_WR_DEPTH : 1]        = ~r_cnt;\n   assign adj_w_cnt_rd_pad[0]                = adj_w_cnt_rd_pad_0;\n   assign r_inv_pad[0]                       = r_inv_pad_0;\n\n\n  always @ ( rd_eop_ad )\n    begin\n      if (!rd_eop_ad) begin\n        adj_w_cnt_rd_pad_0    <= 1'b1;\n        r_inv_pad_0           <= 1'b1;\n      end else begin \n        adj_w_cnt_rd_pad_0    <= 1'b0;\n        r_inv_pad_0           <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        d_cnt_pad    <= 1'b0;\n      else \n        d_cnt_pad    <= adj_w_cnt_rd_pad + r_inv_pad ;\n    end\n\n   assign  d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;\n   assign  WR_DATA_COUNT = d_cnt;\n\n  end endgenerate // fifo_ic_adapter\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter\n   assign  WR_DATA_COUNT = wr_data_count_in;\n\n  end endgenerate // fifo_icn_adapter\n\n\n\n  wire                          inverted_reset = ~S_ARESETN;\n  wire                          axi_rs_rst;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_din          ;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_dout         ;\n  wire                          axis_full         ;\n  wire                          axis_almost_full  ;\n  wire                          axis_empty        ;\n  wire                          axis_s_axis_tready;\n  wire                          axis_m_axis_tvalid;\n  wire                          axis_wr_en        ;\n  wire                          axis_rd_en        ;\n  wire                          axis_we           ;\n  wire                          axis_re           ;\n  wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;\n  reg                           axis_pkt_read = 1'b0;\n  wire                          axis_rd_rst;\n  wire                          axis_wr_rst;\n\n  generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||\n               C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst\n      reg                           rst_d1 = 0        ;\n      reg                           rst_d2 = 0        ;\n      reg [3:0]                    axi_rst = 4'h0     ;\n      always @ (posedge inverted_reset or posedge S_ACLK) begin\n        if (inverted_reset) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          axi_rst        <= 4'hf;\n        end else begin\n          rst_d1         <= #`TCQ 1'b0;\n          rst_d2         <= #`TCQ rst_d1;\n          axi_rst        <= #`TCQ {axi_rst[2:0],1'b0};\n        end\n      end\n\n      assign axi_rs_rst = axi_rst[3];//rst_d2;\n  end endgenerate // gaxi_rs_rst\n\n  generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming\n\n    // Write protection when almost full or prog_full is high\n    assign axis_we    = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : \n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign axis_re    = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :\n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? axis_we & S_ACLK_EN : axis_we;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE               (C_INTERFACE_TYPE),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 2  || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_AXIS),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_AXIS),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),\n        .C_USE_ECC                      (C_USE_ECC_AXIS),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_AXIS),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_axis_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (axis_wr_en),\n        .RD_EN                    (axis_rd_en),\n        .PROG_FULL_THRESH         (AXIS_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXIS_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .INJECTDBITERR            (AXIS_INJECTDBITERR), \n        .INJECTSBITERR            (AXIS_INJECTSBITERR),\n  \n        .DIN                      (axis_din),\n        .DOUT                     (axis_dout),\n        .FULL                     (axis_full),\n        .EMPTY                    (axis_empty),\n        .ALMOST_FULL              (axis_almost_full),\n        .PROG_FULL                (AXIS_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXIS_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (AXIS_OVERFLOW),\n        .VALID                    (),\n        .UNDERFLOW                (AXIS_UNDERFLOW),\n        .DATA_COUNT               (axis_dc),\n        .RD_DATA_COUNT            (AXIS_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXIS_WR_DATA_COUNT),\n        .SBITERR                  (AXIS_SBITERR),\n        .DBITERR                  (AXIS_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_axis),\n        .rd_rst_busy              (rd_rst_busy_axis),\n        .wr_rst_i_out             (axis_wr_rst),\n        .rd_rst_i_out             (axis_rd_rst),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign axis_s_axis_tready    = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;\n    assign axis_m_axis_tvalid    = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;\n    assign S_AXIS_TREADY         = axis_s_axis_tready;\n    assign M_AXIS_TVALID         = axis_m_axis_tvalid;\n\n  end endgenerate // axi_streaming\n\n  wire axis_wr_eop;\n  reg  axis_wr_eop_d1 = 1'b0;\n  wire axis_rd_eop;\n  integer  axis_pkt_cnt;\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)\n        axis_pkt_read    <= 1'b0;\n      else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_wr_eop_d1    <= 1'b0;\n      else\n        axis_wr_eop_d1   <= axis_wr_eop;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_cnt    <= 0;\n      else if (axis_wr_eop_d1 && ~axis_rd_eop)\n        axis_pkt_cnt    <= axis_pkt_cnt + 1;\n      else if (axis_rd_eop && ~axis_wr_eop_d1)\n        axis_pkt_cnt    <= axis_pkt_cnt - 1;\n    end\n  end endgenerate // gaxis_pkt_fifo_cc\n\n\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;\nwire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;\nwire axis_rd_has_rst;\nwire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;\nwire  [LOG_DEPTH_AXIS-1 : 0]  wpkt_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;\nwire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;\nwire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;\nwire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;\nwire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;\nreg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;\nreg adj_axis_wpkt_cnt_rd_pad_0 = 0;\nreg rpkt_inv_pad_0 = 0;\nwire axis_af_rd ;\n\ngenerate if (C_HAS_RST == 1) begin : rst_blk_has\n  assign axis_rd_has_rst = axis_rd_rst;\nend endgenerate //rst_blk_has\n\ngenerate if (C_HAS_RST == 0) begin :rst_blk_no\n  assign axis_rd_has_rst = 1'b0;\nend endgenerate //rst_blk_no\n\n   genvar i;\n\n   generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage\n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (LOG_DEPTH_AXIS)\n        )\n     rd_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (wpkt_q[i-1]), \n         .DOUT     (wpkt_q[i])\n        );\n \n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (1)\n        )\n     wr_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (axis_af_q[i-1]), \n         .DOUT     (axis_af_q[i])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (diff_pkt_cnt == 1))\n        axis_pkt_read    <= 1'b0;\n      else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt    <= 1'b0;\n      else if (axis_wr_eop)\n        axis_wpkt_cnt    <= axis_wpkt_cnt + 1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt_gc    <= 1'b0;\n      else \n        axis_wpkt_cnt_gc    <= bin2gray(axis_wpkt_cnt);\n    end\n\n\n    assign  wpkt_q[0]  = axis_wpkt_cnt_gc;\n    assign  axis_wpkt_cnt_gc_asreg_last       = wpkt_q[C_SYNCHRONIZER_STAGE];\n    assign  axis_af_q[0]                      = axis_almost_full;\n    //assign  axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];\n    assign  axis_af_rd                        = axis_af_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_wpkt_cnt_rd    <= 1'b0;\n      else \n        axis_wpkt_cnt_rd    <= gray2bin(axis_wpkt_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_rpkt_cnt    <= 1'b0;\n      else if (axis_rd_eop)\n        axis_rpkt_cnt    <= axis_rpkt_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;\n   assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1]             = ~axis_rpkt_cnt;\n   assign adj_axis_wpkt_cnt_rd_pad[0]                                = adj_axis_wpkt_cnt_rd_pad_0;\n   assign rpkt_inv_pad[0]                                            = rpkt_inv_pad_0;\n\n\n  always @ ( axis_rd_eop )\n    begin\n      if (!axis_rd_eop) begin\n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b1;\n        rpkt_inv_pad_0                <= 1'b1;\n      end else begin \n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b0;\n        rpkt_inv_pad_0                <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        diff_pkt_cnt_pad    <= 1'b0;\n      else \n        diff_pkt_cnt_pad    <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;\n    end\n\n   assign  diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;\n\n\n\n\n\n   end endgenerate // gaxis_pkt_fifo_ic\n\n\n\n\n  // Generate the accurate data count for axi stream packet fifo configuration\n  reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_dc_pkt_fifo <= 0;\n      else if (axis_wr_en && (~axis_rd_en))\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;\n      else if (~axis_wr_en && axis_rd_en)\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;\n    end\n    assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;\n  end endgenerate // gdc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt\n    assign AXIS_DATA_COUNT = 0;\n  end endgenerate // gndc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc\n    assign AXIS_DATA_COUNT = axis_dc;\n  end endgenerate // gdc\n\n  // Register Slice for Write Address Channel\n  generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_AXIS),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_AXIS)\n            )\n    axis_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (axis_din),\n          .S_VALID                   (axis_wr_en),\n          .S_READY                   (S_AXIS_TREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (axis_dout),\n          .M_VALID                   (M_AXIS_TVALID),\n          .M_READY                   (axis_rd_en)\n          );\n  end endgenerate // gaxis_reg_slice\n\n\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata\n    assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;\n    assign M_AXIS_TDATA   = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb\n    assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;\n    assign M_AXIS_TSTRB   = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep\n    assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;\n    assign M_AXIS_TKEEP   = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid\n    assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;\n    assign M_AXIS_TID     = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest\n    assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;\n    assign M_AXIS_TDEST   = axis_dout[TID_OFFSET-1:TDEST_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser\n    assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;\n    assign M_AXIS_TUSER   = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast\n    assign axis_din[0] = S_AXIS_TLAST;\n    assign M_AXIS_TLAST   = axis_dout[0];\n  end endgenerate\n\n  //###########################################################################\n  //  AXI FULL Write Channel (axi_write_channel)\n  //###########################################################################\n\n  localparam IS_AXI_FULL       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;\n  localparam IS_AXI_LITE       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;\n\n  localparam IS_AXI_FULL_WACH  = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WDCH  = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WRCH  = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RACH  = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RDCH  = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_AXI_LITE_WACH  = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WDCH  = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WRCH  = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RACH  = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RDCH  = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_WR_ADDR_CH     = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;\n  localparam IS_WR_DATA_CH     = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;\n  localparam IS_WR_RESP_CH     = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;\n  localparam IS_RD_ADDR_CH     = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;\n  localparam IS_RD_DATA_CH     = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;\n\n  localparam AWID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;\n  localparam AWADDR_OFFSET     = AWID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam AWLEN_OFFSET      = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;\n  localparam AWSIZE_OFFSET     = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;\n  localparam AWBURST_OFFSET    = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;\n  localparam AWLOCK_OFFSET     = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;\n  localparam AWCACHE_OFFSET    = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;\n  localparam AWPROT_OFFSET     = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam AWQOS_OFFSET      = AWPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam AWREGION_OFFSET   = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;\n  localparam AWUSER_OFFSET     = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;\n\n  localparam WID_OFFSET        = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;\n  localparam WDATA_OFFSET      = WID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam WSTRB_OFFSET      = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;\n  localparam WUSER_OFFSET      = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;\n\n  localparam BID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;\n  localparam BRESP_OFFSET      = BID_OFFSET - C_AXI_BRESP_WIDTH;\n  localparam BUSER_OFFSET      = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;\n\n\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_din          ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout         ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout_pkt     ;\n  wire                          wach_full         ;\n  wire                          wach_almost_full  ;\n  wire                          wach_prog_full    ;\n  wire                          wach_empty        ;\n  wire                          wach_almost_empty ;\n  wire                          wach_prog_empty   ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_din          ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_dout         ;\n  wire                          wdch_full         ;\n  wire                          wdch_almost_full  ;\n  wire                          wdch_prog_full    ;\n  wire                          wdch_empty        ;\n  wire                          wdch_almost_empty ;\n  wire                          wdch_prog_empty   ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_din          ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_dout         ;\n  wire                          wrch_full         ;\n  wire                          wrch_almost_full  ;\n  wire                          wrch_prog_full    ;\n  wire                          wrch_empty        ;\n  wire                          wrch_almost_empty ;\n  wire                          wrch_prog_empty   ;\n  wire                          axi_aw_underflow_i;\n  wire                          axi_w_underflow_i ;\n  wire                          axi_b_underflow_i ;\n  wire                          axi_aw_overflow_i ;\n  wire                          axi_w_overflow_i  ;\n  wire                          axi_b_overflow_i  ;\n  wire                          axi_wr_underflow_i;\n  wire                          axi_wr_overflow_i ;\n  wire                          wach_s_axi_awready;\n  wire                          wach_m_axi_awvalid;\n  wire                          wach_wr_en        ;\n  wire                          wach_rd_en        ;\n  wire                          wdch_s_axi_wready ;\n  wire                          wdch_m_axi_wvalid ;\n  wire                          wdch_wr_en        ;\n  wire                          wdch_rd_en        ;\n  wire                          wrch_s_axi_bvalid ;\n  wire                          wrch_m_axi_bready ;\n  wire                          wrch_wr_en        ;\n  wire                          wrch_rd_en        ;\n  wire                          txn_count_up      ;\n  wire                          txn_count_down    ;\n  wire                          awvalid_en        ;\n  wire                          awvalid_pkt       ;\n  wire                          awready_pkt       ;\n  integer                       wr_pkt_count      ;\n  wire                          wach_we           ;\n  wire                          wach_re           ;\n  wire                          wdch_we           ;\n  wire                          wdch_re           ;\n  wire                          wrch_we           ;\n  wire                          wrch_re           ;\n\n  generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel\n    // Write protection when almost full or prog_full is high\n    assign wach_we    = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wach_re    = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        wach_m_axi_awvalid & awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY && wach_m_axi_awvalid :\n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY : 1'b0;\n    assign wach_wr_en = (C_HAS_SLAVE_CE == 1)  ? wach_we & S_ACLK_EN : wach_we;\n    assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 2  || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),\n        .C_USE_ECC                      (C_USE_ECC_WACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_wach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wach_wr_en),\n        .RD_EN                    (wach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AW_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AW_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AW_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AW_INJECTSBITERR),\n  \n        .DIN                      (wach_din),\n        .DOUT                     (wach_dout_pkt),\n        .FULL                     (wach_full),\n        .EMPTY                    (wach_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_AW_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_AW_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_aw_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_aw_underflow_i),\n        .DATA_COUNT               (AXI_AW_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AW_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AW_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AW_SBITERR),\n        .DBITERR                  (AXI_AW_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wach),\n        .rd_rst_busy              (rd_rst_busy_wach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wach_s_axi_awready    = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;\n    assign wach_m_axi_awvalid   = ~wach_empty;\n    assign S_AXI_AWREADY        = wach_s_axi_awready;\n\n    assign AXI_AW_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;\n    assign AXI_AW_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_aw_overflow_i  : 0;\n\n  end endgenerate // axi_write_address_channel\n\n  // Register Slice for Write Address Channel\n  generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WACH)\n            )\n    wach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_din),\n          .S_VALID                   (S_AXI_AWVALID),\n          .S_READY                   (S_AXI_AWREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n  end endgenerate // gwach_reg_slice\n  \n  generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (1)\n            )\n    wach_pkt_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_dout_pkt),\n          .S_VALID                   (awvalid_pkt),\n          .S_READY                   (awready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n\n    assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;\n\n    assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; \n    assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset == 1) begin\n\twr_pkt_count <= 0;\n      end else begin\n\tif(txn_count_up == 1 && txn_count_down == 0) begin\n\t  wr_pkt_count <= wr_pkt_count + 1;\n\tend else if(txn_count_up == 0 && txn_count_down == 1) begin\n\t  wr_pkt_count <= wr_pkt_count - 1;\n\tend\n      end\n    end //Always end\n    assign awvalid_en = (wr_pkt_count > 0)?1:0;\n  end endgenerate\n  \n  generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr\n    assign awvalid_en    = 1;    \n    assign wach_dout     = wach_dout_pkt;\n    assign M_AXI_AWVALID = wach_m_axi_awvalid;\n  end\n  endgenerate\n\n\n\n  generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel\n    // Write protection when almost full or prog_full is high\n    assign wdch_we    = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wdch_re    = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;\n    assign wdch_wr_en = (C_HAS_SLAVE_CE == 1)  ? wdch_we & S_ACLK_EN : wdch_we;\n    assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;\n\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 2  || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),\n        .C_USE_ECC                      (C_USE_ECC_WDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_wdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wdch_wr_en),\n        .RD_EN                    (wdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_W_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_W_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_W_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_W_INJECTSBITERR),\n  \n        .DIN                      (wdch_din),\n        .DOUT                     (wdch_dout),\n        .FULL                     (wdch_full),\n        .EMPTY                    (wdch_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_W_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_W_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_w_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_w_underflow_i),\n        .DATA_COUNT               (AXI_W_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_W_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_W_WR_DATA_COUNT),\n        .SBITERR                  (AXI_W_SBITERR),\n        .DBITERR                  (AXI_W_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wdch),\n        .rd_rst_busy              (rd_rst_busy_wdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wdch_s_axi_wready     = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;\n    assign wdch_m_axi_wvalid = ~wdch_empty;\n    assign S_AXI_WREADY      = wdch_s_axi_wready;\n    assign M_AXI_WVALID      = wdch_m_axi_wvalid;\n\n    assign AXI_W_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i  : 0;\n    assign AXI_W_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_w_overflow_i   : 0;\n\n  end endgenerate // axi_write_data_channel\n\n  // Register Slice for Write Data Channel\n  generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WDCH)\n            )\n    wdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wdch_din),\n          .S_VALID                   (S_AXI_WVALID),\n          .S_READY                   (S_AXI_WREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wdch_dout),\n          .M_VALID                   (M_AXI_WVALID),\n          .M_READY                   (M_AXI_WREADY)\n          );\n  end endgenerate // gwdch_reg_slice\n\n  generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel\n    // Write protection when almost full or prog_full is high\n    assign wrch_we    = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wrch_re    = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;\n    assign wrch_wr_en = (C_HAS_MASTER_CE == 1)  ? wrch_we & M_ACLK_EN : wrch_we;\n    assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 2  || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WRCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WRCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),\n        .C_USE_ECC                      (C_USE_ECC_WRCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WRCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WRCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_wrch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wrch_wr_en),\n        .RD_EN                    (wrch_rd_en),\n        .PROG_FULL_THRESH         (AXI_B_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_B_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .INJECTDBITERR            (AXI_B_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_B_INJECTSBITERR),\n  \n        .DIN                      (wrch_din),\n        .DOUT                     (wrch_dout),\n        .FULL                     (wrch_full),\n        .EMPTY                    (wrch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_B_PROG_FULL),\n        .PROG_EMPTY               (AXI_B_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_b_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_b_underflow_i),\n        .DATA_COUNT               (AXI_B_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_B_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_B_WR_DATA_COUNT),\n        .SBITERR                  (AXI_B_SBITERR),\n        .DBITERR                  (AXI_B_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wrch),\n        .rd_rst_busy              (rd_rst_busy_wrch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wrch_s_axi_bvalid = ~wrch_empty;\n    assign wrch_m_axi_bready     = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;\n    assign S_AXI_BVALID      = wrch_s_axi_bvalid;\n    assign M_AXI_BREADY      = wrch_m_axi_bready;\n\n    assign AXI_B_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i  : 0;\n    assign AXI_B_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_b_overflow_i   : 0;\n  end endgenerate // axi_write_resp_channel\n\n  // Register Slice for Write Response Channel\n  generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WRCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WRCH)\n            )\n    wrch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wrch_din),\n          .S_VALID                   (M_AXI_BVALID),\n          .S_READY                   (M_AXI_BREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wrch_dout),\n          .M_VALID                   (S_AXI_BVALID),\n          .M_READY                   (S_AXI_BREADY)\n          );\n  end endgenerate // gwrch_reg_slice\n\n\n    assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW  == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;\n    assign axi_wr_overflow_i  = C_USE_COMMON_OVERFLOW   == 1 ? (axi_aw_overflow_i  || axi_w_overflow_i  || axi_b_overflow_i)  : 0;\n\n  generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output\n    assign M_AXI_AWADDR    = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];    \n    assign M_AXI_AWLEN     = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];    \n    assign M_AXI_AWSIZE    = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];    \n    assign M_AXI_AWBURST   = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];    \n    assign M_AXI_AWLOCK    = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];    \n    assign M_AXI_AWCACHE   = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];    \n    assign M_AXI_AWQOS     = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];    \n    assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET]    = S_AXI_AWADDR;\n    assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET]   = S_AXI_AWLEN;\n    assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET]   = S_AXI_AWSIZE;\n    assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;\n    assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;\n    assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;\n    assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;\n    assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET]   = S_AXI_AWQOS;\n  end endgenerate // axi_wach_output\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion\n    assign M_AXI_AWREGION  = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];    \n  end endgenerate // axi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion\n    assign M_AXI_AWREGION  = 0;    \n  end endgenerate // naxi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser\n    assign M_AXI_AWUSER  = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];    \n  end endgenerate // axi_awuser\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser\n    assign M_AXI_AWUSER  = 0;    \n  end endgenerate // naxi_awuser\n\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid\n    assign M_AXI_AWID      = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];\n  end endgenerate //axi_awid\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid\n    assign M_AXI_AWID      = 0;\n  end endgenerate //naxi_awid\n\n  generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output\n    assign M_AXI_WDATA     = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n    assign M_AXI_WLAST     = wdch_dout[0];\n    assign wdch_din[WID_OFFSET-1:WDATA_OFFSET]   = S_AXI_WDATA;\n    assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;\n    assign wdch_din[0]   = S_AXI_WLAST;\n  end endgenerate // axi_wdch_output\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin\n    assign M_AXI_WID       = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];\n  end endgenerate\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin\n    assign M_AXI_WID       = 0;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin\n    assign M_AXI_WUSER     = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];    \n  end endgenerate\n  generate if (C_HAS_AXI_WUSER == 0) begin\n    assign M_AXI_WUSER       = 0;\n  end endgenerate\n\n  generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output\n    assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; \n    assign wrch_din[BID_OFFSET-1:BRESP_OFFSET]   = M_AXI_BRESP;\n  end endgenerate // axi_wrch_output\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser\n    assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];\n  end endgenerate // axi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser\n    assign S_AXI_BUSER = 0;\n  end endgenerate // naxi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid\n    assign S_AXI_BID   =  wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];\n  end endgenerate // axi_bid\n  \n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid\n    assign S_AXI_BID   =  0 ;\n  end endgenerate // naxi_bid  \n\n\n  generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1\n    assign wach_din        = {S_AXI_AWADDR, S_AXI_AWPROT};\n    assign M_AXI_AWADDR    = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];    \n  end endgenerate // axi_wach_output1\n\n  generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1\n    assign wdch_din        = {S_AXI_WDATA, S_AXI_WSTRB};\n    assign M_AXI_WDATA     = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n  end endgenerate // axi_wdch_output1\n\n  generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1\n    assign wrch_din        = M_AXI_BRESP;\n    assign S_AXI_BRESP     = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; \n  end endgenerate // axi_wrch_output1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1\n    assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET]     = S_AXI_AWUSER;\n  end endgenerate // gwach_din1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2\n    assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET]     = S_AXI_AWID;\n  end endgenerate // gwach_din2\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3\n    assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET]     = S_AXI_AWREGION;\n  end endgenerate // gwach_din3\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1\n    assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;\n  end endgenerate // gwdch_din1\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2\n    assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;\n  end endgenerate // gwdch_din2\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1\n    assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET]    = M_AXI_BUSER;\n  end endgenerate // gwrch_din1\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2\n    assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET]    = M_AXI_BID;\n  end endgenerate // gwrch_din2\n\n  //end of  axi_write_channel\n\n  //###########################################################################\n  //  AXI FULL Read Channel (axi_read_channel)\n  //###########################################################################\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_din            ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout           ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout_pkt       ;\n  wire                               rach_full           ;\n  wire                               rach_almost_full    ;\n  wire                               rach_prog_full      ;\n  wire                               rach_empty          ;\n  wire                               rach_almost_empty   ;\n  wire                               rach_prog_empty     ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_din            ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_dout           ;\n  wire                               rdch_full           ;\n  wire                               rdch_almost_full    ;\n  wire                               rdch_prog_full      ;\n  wire                               rdch_empty          ;\n  wire                               rdch_almost_empty   ;\n  wire                               rdch_prog_empty     ;\n  wire                               axi_ar_underflow_i  ;\n  wire                               axi_r_underflow_i   ;\n  wire                               axi_ar_overflow_i   ;\n  wire                               axi_r_overflow_i    ;\n  wire                               axi_rd_underflow_i  ;\n  wire                               axi_rd_overflow_i   ;\n  wire                               rach_s_axi_arready  ;\n  wire                               rach_m_axi_arvalid  ;\n  wire                               rach_wr_en          ;\n  wire                               rach_rd_en          ;\n  wire                               rdch_m_axi_rready   ;\n  wire                               rdch_s_axi_rvalid   ;\n  wire                               rdch_wr_en          ;\n  wire                               rdch_rd_en          ;\n  wire                               arvalid_pkt         ;\n  wire                               arready_pkt         ;\n  wire                               arvalid_en          ;\n  wire                               rdch_rd_ok          ;\n  wire                               accept_next_pkt     ;\n  integer                            rdch_free_space     ;\n  integer                            rdch_commited_space ;\n  wire                               rach_we             ;\n  wire                               rach_re             ;\n  wire                               rdch_we             ;\n  wire                               rdch_re             ;\n\n  localparam ARID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;\n  localparam ARADDR_OFFSET     = ARID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam ARLEN_OFFSET      = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;\n  localparam ARSIZE_OFFSET     = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;\n  localparam ARBURST_OFFSET    = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;\n  localparam ARLOCK_OFFSET     = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;\n  localparam ARCACHE_OFFSET    = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;\n  localparam ARPROT_OFFSET     = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam ARQOS_OFFSET      = ARPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam ARREGION_OFFSET   = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;\n  localparam ARUSER_OFFSET     = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;\n\n  localparam RID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;\n  localparam RDATA_OFFSET      = RID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam RRESP_OFFSET      = RDATA_OFFSET - C_AXI_RRESP_WIDTH;\n  localparam RUSER_OFFSET      = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;\n\n\n  generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rach_we    = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;\n\n    // Read protection when almost empty or prog_empty is high\n//    assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;\n    assign rach_re    = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        rach_m_axi_arvalid & arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY && rach_m_axi_arvalid :\n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY : 1'b0;\n    assign rach_wr_en = (C_HAS_SLAVE_CE == 1)  ? rach_we & S_ACLK_EN : rach_we;\n    assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;\n\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 2  || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),\n        .C_USE_ECC                      (C_USE_ECC_RACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_rach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rach_wr_en),\n        .RD_EN                    (rach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AR_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AR_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AR_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AR_INJECTSBITERR),\n  \n        .DIN                      (rach_din),\n        .DOUT                     (rach_dout_pkt),\n        .FULL                     (rach_full),\n        .EMPTY                    (rach_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_AR_PROG_FULL),\n        .PROG_EMPTY               (AXI_AR_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_ar_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_ar_underflow_i),\n        .DATA_COUNT               (AXI_AR_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AR_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AR_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AR_SBITERR),\n        .DBITERR                  (AXI_AR_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rach),\n        .rd_rst_busy              (rd_rst_busy_rach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rach_s_axi_arready    = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;\n    assign rach_m_axi_arvalid = ~rach_empty;\n    assign S_AXI_ARREADY      = rach_s_axi_arready;\n\n    assign AXI_AR_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;\n    assign AXI_AR_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_ar_overflow_i  : 0;\n\n  end endgenerate // axi_read_addr_channel\n\n  // Register Slice for Read Address Channel\n  generate if (C_RACH_TYPE == 1) begin : grach_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RACH)\n            )\n    rach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_din),\n          .S_VALID                   (S_AXI_ARVALID),\n          .S_READY                   (S_AXI_ARREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice\n\n  // Register Slice for Read Address Channel for MM Packet FIFO\n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (1)\n            )\n    reg_slice_mm_pkt_fifo_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_dout_pkt),\n          .S_VALID                   (arvalid_pkt),\n          .S_READY                   (arready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice_mm_pkt_fifo\n\n  \n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid\n    assign M_AXI_ARVALID      = rach_m_axi_arvalid;\n    assign rach_dout          = rach_dout_pkt;\n  end endgenerate // grach_m_axi_arvalid\n  \n  \n  generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd\n    assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;\n    assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;\n    assign accept_next_pkt  = rach_m_axi_arvalid && arready_pkt && arvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset) begin\n\trdch_commited_space <= 0;\n      end else begin\n\tif(rdch_rd_ok && !accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space-1;\n\tend else if(!rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);\n\tend else if(rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);\n\tend\n      end\n    end //Always end\n\n    always@(*) begin\n      rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));\n    end\n\n    assign arvalid_en = (rdch_free_space >= 0)?1:0;\n  end\n  endgenerate\n  \n  generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd\n    assign arvalid_en = 1;    \n  end\n  endgenerate\n\n  generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rdch_we    = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready  & M_AXI_RVALID : M_AXI_RVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign rdch_re    = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid  & S_AXI_RREADY : S_AXI_RREADY;\n    assign rdch_wr_en = (C_HAS_MASTER_CE == 1)  ? rdch_we & M_ACLK_EN : rdch_we;\n    assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 2  || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),\n        .C_USE_ECC                      (C_USE_ECC_RDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_RDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_rdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rdch_wr_en),\n        .RD_EN                    (rdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_R_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_R_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_R_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_R_INJECTSBITERR),\n  \n        .DIN                      (rdch_din),\n        .DOUT                     (rdch_dout),\n        .FULL                     (rdch_full),\n        .EMPTY                    (rdch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_R_PROG_FULL),\n        .PROG_EMPTY               (AXI_R_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_r_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_r_underflow_i),\n        .DATA_COUNT               (AXI_R_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_R_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_R_WR_DATA_COUNT),\n        .SBITERR                  (AXI_R_SBITERR),\n        .DBITERR                  (AXI_R_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rdch),\n        .rd_rst_busy              (rd_rst_busy_rdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rdch_s_axi_rvalid = ~rdch_empty;\n    assign rdch_m_axi_rready     = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;\n    assign S_AXI_RVALID      = rdch_s_axi_rvalid;\n    assign M_AXI_RREADY      = rdch_m_axi_rready;\n\n    assign AXI_R_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i  : 0;\n    assign AXI_R_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_r_overflow_i   : 0;\n\n  end endgenerate //axi_read_data_channel\n\n  // Register Slice for read Data Channel\n  generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RDCH)\n            )\n    rdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rdch_din),\n          .S_VALID                   (M_AXI_RVALID),\n          .S_READY                   (M_AXI_RREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rdch_dout),\n          .M_VALID                   (S_AXI_RVALID),\n          .M_READY                   (S_AXI_RREADY)\n          );\n  end endgenerate // grdch_reg_slice\n\n\n    assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;\n    assign axi_rd_overflow_i  = C_USE_COMMON_OVERFLOW  == 1 ? (axi_ar_overflow_i  || axi_r_overflow_i) : 0;\n\n\n  generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output\n    assign M_AXI_ARADDR    = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];    \n    assign M_AXI_ARLEN     = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];    \n    assign M_AXI_ARSIZE    = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];    \n    assign M_AXI_ARBURST   = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];    \n    assign M_AXI_ARLOCK    = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];    \n    assign M_AXI_ARCACHE   = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];    \n    assign M_AXI_ARPROT    = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];    \n    assign M_AXI_ARQOS     = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];    \n    assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET]    = S_AXI_ARADDR;\n    assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET]   = S_AXI_ARLEN;\n    assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET]   = S_AXI_ARSIZE;\n    assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;\n    assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;\n    assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;\n    assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;\n    assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET]   = S_AXI_ARQOS;\n  end endgenerate // axi_full_rach_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion\n    assign M_AXI_ARREGION  = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];    \n  end endgenerate // axi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion\n    assign M_AXI_ARREGION  = 0;    \n  end endgenerate // naxi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser\n    assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];    \n  end endgenerate // axi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser\n    assign M_AXI_ARUSER = 0;    \n  end endgenerate // naxi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid\n    assign M_AXI_ARID      = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];\n  end endgenerate // axi_arid\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid\n    assign M_AXI_ARID      = 0;\n  end endgenerate // naxi_arid\n\n  generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output\n    assign S_AXI_RDATA     = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];\n    assign S_AXI_RRESP     = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n    assign S_AXI_RLAST     = rdch_dout[0];\n    assign rdch_din[RID_OFFSET-1:RDATA_OFFSET]   = M_AXI_RDATA;\n    assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;\n    assign rdch_din[0] = M_AXI_RLAST;\n  end endgenerate // axi_full_rdch_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output\n    assign S_AXI_RUSER     = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];\n  end endgenerate // axi_full_ruser_output\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output\n    assign S_AXI_RUSER     =  0;\n  end endgenerate // axi_full_nruser_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid\n    assign S_AXI_RID       = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];\n  end endgenerate // axi_rid\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid\n    assign S_AXI_RID       = 0;\n  end endgenerate // naxi_rid\n\n  generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1\n    assign rach_din      = {S_AXI_ARADDR, S_AXI_ARPROT};\n    assign M_AXI_ARADDR  = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];\n    assign M_AXI_ARPROT  = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];\n  end endgenerate // axi_lite_rach_output\n\n  generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1\n    assign rdch_din      = {M_AXI_RDATA, M_AXI_RRESP};\n    assign S_AXI_RDATA   = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];\n    assign S_AXI_RRESP   = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n  end endgenerate // axi_lite_rdch_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1\n    assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET]     = S_AXI_ARUSER;\n  end endgenerate // grach_din1\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2\n    assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET]     = S_AXI_ARID;\n  end endgenerate // grach_din2\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin\n    assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1\n    assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET]     = M_AXI_RUSER;\n  end endgenerate // grdch_din1\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2\n    assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;\n  end endgenerate // grdch_din2\n\n  //end of axi_read_channel\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf\n    assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :\n                       (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :\n                       (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;\n  end endgenerate // gaxi_comm_uf\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of\n    assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :\n                      (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :\n                      (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;\n  end endgenerate // gaxi_comm_of\n  \n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  // Pass Through Logic or Wiring Logic\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  \n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Write Address Channel\n  generate if (C_WACH_TYPE == 2) begin : gwach_pass_through\n    assign M_AXI_AWID      = S_AXI_AWID;\n    assign M_AXI_AWADDR    = S_AXI_AWADDR;\n    assign M_AXI_AWLEN     = S_AXI_AWLEN;\n    assign M_AXI_AWSIZE    = S_AXI_AWSIZE;\n    assign M_AXI_AWBURST   = S_AXI_AWBURST;\n    assign M_AXI_AWLOCK    = S_AXI_AWLOCK;\n    assign M_AXI_AWCACHE   = S_AXI_AWCACHE;\n    assign M_AXI_AWPROT    = S_AXI_AWPROT;\n    assign M_AXI_AWQOS     = S_AXI_AWQOS;\n    assign M_AXI_AWREGION  = S_AXI_AWREGION;\n    assign M_AXI_AWUSER    = S_AXI_AWUSER;\n    assign S_AXI_AWREADY   = M_AXI_AWREADY;\n    assign M_AXI_AWVALID   = S_AXI_AWVALID;\n  end endgenerate // gwach_pass_through;\n\n  // Wiring logic for Write Data Channel\n  generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through\n    assign M_AXI_WID       = S_AXI_WID;\n    assign M_AXI_WDATA     = S_AXI_WDATA;\n    assign M_AXI_WSTRB     = S_AXI_WSTRB;\n    assign M_AXI_WLAST     = S_AXI_WLAST;\n    assign M_AXI_WUSER     = S_AXI_WUSER;\n    assign S_AXI_WREADY    = M_AXI_WREADY;\n    assign M_AXI_WVALID    = S_AXI_WVALID;\n  end endgenerate // gwdch_pass_through;\n\n  // Wiring logic for Write Response Channel\n  generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through\n    assign S_AXI_BID       = M_AXI_BID;\n    assign S_AXI_BRESP     = M_AXI_BRESP;\n    assign S_AXI_BUSER     = M_AXI_BUSER;\n    assign M_AXI_BREADY    = S_AXI_BREADY;\n    assign S_AXI_BVALID    = M_AXI_BVALID;\n  end endgenerate // gwrch_pass_through;\n\n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Read Address Channel\n  generate if (C_RACH_TYPE == 2) begin : grach_pass_through\n    assign M_AXI_ARID      = S_AXI_ARID;\n    assign M_AXI_ARADDR    = S_AXI_ARADDR;\n    assign M_AXI_ARLEN     = S_AXI_ARLEN;\n    assign M_AXI_ARSIZE    = S_AXI_ARSIZE;\n    assign M_AXI_ARBURST   = S_AXI_ARBURST;\n    assign M_AXI_ARLOCK    = S_AXI_ARLOCK;\n    assign M_AXI_ARCACHE   = S_AXI_ARCACHE;\n    assign M_AXI_ARPROT    = S_AXI_ARPROT;\n    assign M_AXI_ARQOS     = S_AXI_ARQOS;\n    assign M_AXI_ARREGION  = S_AXI_ARREGION;\n    assign M_AXI_ARUSER    = S_AXI_ARUSER;\n    assign S_AXI_ARREADY   = M_AXI_ARREADY;\n    assign M_AXI_ARVALID   = S_AXI_ARVALID;\n  end endgenerate // grach_pass_through;\n\n  // Wiring logic for Read Data Channel \n  generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through\n    assign S_AXI_RID      = M_AXI_RID;\n    assign S_AXI_RLAST    = M_AXI_RLAST;\n    assign S_AXI_RUSER    = M_AXI_RUSER;\n    assign S_AXI_RDATA    = M_AXI_RDATA;\n    assign S_AXI_RRESP    = M_AXI_RRESP;\n    assign S_AXI_RVALID   = M_AXI_RVALID;\n    assign M_AXI_RREADY   = S_AXI_RREADY;\n  end endgenerate // grdch_pass_through;\n\n  // Wiring logic for AXI Streaming\n  generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through\n    assign M_AXIS_TDATA   = S_AXIS_TDATA;\n    assign M_AXIS_TSTRB   = S_AXIS_TSTRB;\n    assign M_AXIS_TKEEP   = S_AXIS_TKEEP;\n    assign M_AXIS_TID     = S_AXIS_TID;\n    assign M_AXIS_TDEST   = S_AXIS_TDEST;\n    assign M_AXIS_TUSER   = S_AXIS_TUSER;\n    assign M_AXIS_TLAST   = S_AXIS_TLAST;\n    assign S_AXIS_TREADY  = M_AXIS_TREADY;\n    assign M_AXIS_TVALID  = S_AXIS_TVALID;\n  end endgenerate // gaxis_pass_through;\n\n\nendmodule //fifo_generator_v13_2_1\n\n\n\n/*******************************************************************************\n * Declaration of top-level module for Conventional FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_1_CONV_VER\n  #(\n    parameter  C_COMMON_CLOCK                 = 0,\n    parameter  C_INTERFACE_TYPE               = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_COUNT_TYPE                   = 0,\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DEFAULT_VALUE                = \"\",\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_ENABLE_RLOCS                 = 0,\n    parameter  C_FAMILY                       = \"virtex7\", //Not allowed in Verilog model\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_BACKUP                   = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_INT_CLK                  = 0,\n    parameter  C_HAS_MEMINIT_FILE             = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RD_RST                   = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_RST                   = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_INIT_WR_PNTR_VAL             = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_MIF_FILE_NAME                = \"\",\n    parameter  C_OPTIMIZATION_MODE            = 0,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PRIM_FIFO_TYPE               = \"\",\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_FREQ                      = 1,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_ECC                      = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_USE_FIFO16_FLAGS             = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_FREQ                      = 1,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_WR_RESPONSE_LATENCY          = 1,\n    parameter  C_MSGON_VAL                    = 1,\n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2,\n    parameter  C_AXI_TYPE                     = 0\n   )\n\n  (\n   input                               BACKUP,\n   input                               BACKUP_MARKER,\n   input                               CLK,\n   input                               RST,\n   input                               SRST,\n   input                               WR_CLK,\n   input                               WR_RST,\n   input                               RD_CLK,\n   input                               RD_RST,\n   input [C_DIN_WIDTH-1:0]             DIN,\n   input                               WR_EN,\n   input                               RD_EN,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_ASSERT,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_NEGATE,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_ASSERT,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_NEGATE,\n   input                               INT_CLK,\n   input                               INJECTDBITERR,\n   input                               INJECTSBITERR,\n  \n   output [C_DOUT_WIDTH-1:0]           DOUT,\n   output                              FULL,\n   output                              ALMOST_FULL,\n   output                              WR_ACK,\n   output                              OVERFLOW,\n   output                              EMPTY,\n   output                              ALMOST_EMPTY,\n   output                              VALID,\n   output                              UNDERFLOW,\n   output [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT,\n   output [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT,\n   output [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT,\n   output                              PROG_FULL,\n   output                              PROG_EMPTY,\n   output                              SBITERR,\n   output                              DBITERR,\n   output                              wr_rst_busy_o,\n   output                              wr_rst_busy,\n   output                              rd_rst_busy,\n   output                              wr_rst_i_out,\n   output                              rd_rst_i_out\n  );\n\n/*\n ******************************************************************************\n * Definition of Parameters\n ******************************************************************************\n *     C_COMMON_CLOCK                : Common Clock (1), Independent Clocks (0)\n *     C_COUNT_TYPE                  :    *not used\n *     C_DATA_COUNT_WIDTH            : Width of DATA_COUNT bus\n *     C_DEFAULT_VALUE               :    *not used\n *     C_DIN_WIDTH                   : Width of DIN bus\n *     C_DOUT_RST_VAL                : Reset value of DOUT\n *     C_DOUT_WIDTH                  : Width of DOUT bus\n *     C_ENABLE_RLOCS                :    *not used\n *     C_FAMILY                      : not used in bhv model\n *     C_FULL_FLAGS_RST_VAL          : Full flags rst val (0 or 1)\n *     C_HAS_ALMOST_EMPTY            : 1=Core has ALMOST_EMPTY flag\n *     C_HAS_ALMOST_FULL             : 1=Core has ALMOST_FULL flag\n *     C_HAS_BACKUP                  :    *not used\n *     C_HAS_DATA_COUNT              : 1=Core has DATA_COUNT bus\n *     C_HAS_INT_CLK                 : not used in bhv model\n *     C_HAS_MEMINIT_FILE            :    *not used\n *     C_HAS_OVERFLOW                : 1=Core has OVERFLOW flag\n *     C_HAS_RD_DATA_COUNT           : 1=Core has RD_DATA_COUNT bus\n *     C_HAS_RD_RST                  :    *not used\n *     C_HAS_RST                     : 1=Core has Async Rst\n *     C_HAS_SRST                    : 1=Core has Sync Rst\n *     C_HAS_UNDERFLOW               : 1=Core has UNDERFLOW flag\n *     C_HAS_VALID                   : 1=Core has VALID flag\n *     C_HAS_WR_ACK                  : 1=Core has WR_ACK flag\n *     C_HAS_WR_DATA_COUNT           : 1=Core has WR_DATA_COUNT bus\n *     C_HAS_WR_RST                  :    *not used\n *     C_IMPLEMENTATION_TYPE         : 0=Common-Clock Bram/Dram\n *                                     1=Common-Clock ShiftRam\n *                                     2=Indep. Clocks Bram/Dram\n *                                     3=Virtex-4 Built-in\n *                                     4=Virtex-5 Built-in\n *     C_INIT_WR_PNTR_VAL            :   *not used\n *     C_MEMORY_TYPE                 : 1=Block RAM\n *                                     2=Distributed RAM\n *                                     3=Shift RAM\n *                                     4=Built-in FIFO\n *     C_MIF_FILE_NAME               :   *not used\n *     C_OPTIMIZATION_MODE           :   *not used\n *     C_OVERFLOW_LOW                : 1=OVERFLOW active low\n *     C_PRELOAD_LATENCY             : Latency of read: 0, 1, 2\n *     C_PRELOAD_REGS                : 1=Use output registers\n *     C_PRIM_FIFO_TYPE              : not used in bhv model\n *     C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold\n *     C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold\n *     C_PROG_EMPTY_TYPE             : 0=No programmable empty\n *                                     1=Single prog empty thresh constant\n *                                     2=Multiple prog empty thresh constants\n *                                     3=Single prog empty thresh input\n *                                     4=Multiple prog empty thresh inputs\n *     C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold\n *     C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold\n *     C_PROG_FULL_TYPE              : 0=No prog full\n *                                     1=Single prog full thresh constant\n *                                     2=Multiple prog full thresh constants\n *                                     3=Single prog full thresh input\n *                                     4=Multiple prog full thresh inputs\n *     C_RD_DATA_COUNT_WIDTH         : Width of RD_DATA_COUNT bus\n *     C_RD_DEPTH                    : Depth of read interface (2^N)\n *     C_RD_FREQ                     : not used in bhv model\n *     C_RD_PNTR_WIDTH               : always log2(C_RD_DEPTH)\n *     C_UNDERFLOW_LOW               : 1=UNDERFLOW active low\n *     C_USE_DOUT_RST                : 1=Resets DOUT on RST\n *     C_USE_ECC                     : Used for error injection purpose\n *     C_USE_EMBEDDED_REG            : 1=Use BRAM embedded output register\n *     C_USE_FIFO16_FLAGS            : not used in bhv model\n *     C_USE_FWFT_DATA_COUNT         : 1=Use extra logic for FWFT data count\n *     C_VALID_LOW                   : 1=VALID active low\n *     C_WR_ACK_LOW                  : 1=WR_ACK active low\n *     C_WR_DATA_COUNT_WIDTH         : Width of WR_DATA_COUNT bus\n *     C_WR_DEPTH                    : Depth of write interface (2^N)\n *     C_WR_FREQ                     : not used in bhv model\n *     C_WR_PNTR_WIDTH               : always log2(C_WR_DEPTH)\n *     C_WR_RESPONSE_LATENCY         :    *not used\n *     C_MSGON_VAL                   :    *not used by bhv model\n *     C_ENABLE_RST_SYNC             : 0 = Use WR_RST & RD_RST\n *                                     1 = Use RST\n *     C_ERROR_INJECTION_TYPE        : 0 = No error injection\n *                                     1 = Single bit error injection only\n *                                     2 = Double bit error injection only\n *                                     3 = Single and double bit error injection\n ******************************************************************************\n * Definition of Ports\n ******************************************************************************\n *   BACKUP       : Not used\n *   BACKUP_MARKER: Not used\n *   CLK          : Clock\n *   DIN          : Input data bus\n *   PROG_EMPTY_THRESH       : Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag\n *   PROG_FULL_THRESH        : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag\n *   RD_CLK       : Read Domain Clock\n *   RD_EN        : Read enable\n *   RD_RST       : Read Reset\n *   RST          : Asynchronous Reset\n *   SRST         : Synchronous Reset\n *   WR_CLK       : Write Domain Clock\n *   WR_EN        : Write enable\n *   WR_RST       : Write Reset\n *   INT_CLK      : Internal Clock\n *   INJECTSBITERR: Inject Signle bit error\n *   INJECTDBITERR: Inject Double bit error\n *   ALMOST_EMPTY : One word remaining in FIFO\n *   ALMOST_FULL  : One empty space remaining in FIFO\n *   DATA_COUNT   : Number of data words in fifo( synchronous to CLK)\n *   DOUT         : Output data bus\n *   EMPTY        : Empty flag\n *   FULL         : Full flag\n *   OVERFLOW     : Last write rejected\n *   PROG_EMPTY   : Programmable Empty Flag\n *   PROG_FULL    : Programmable Full Flag\n *   RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)\n *   UNDERFLOW    : Last read rejected\n *   VALID        : Last read acknowledged, DOUT bus VALID\n *   WR_ACK       : Last write acknowledged\n *   WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)\n *   SBITERR      : Single Bit ECC Error Detected\n *   DBITERR      : Double Bit ECC Error Detected\n ******************************************************************************\n */\n\n  //----------------------------------------------------------------------------\n  //- Internal Signals for delayed input signals\n  //- All the input signals except Clock are delayed by 100 ps and then given to\n  //- the models.\n  //----------------------------------------------------------------------------\n \n  reg                         rst_delayed                       ;\n  reg                         empty_fb                       ;\n  reg                         srst_delayed                      ;\n  reg                         wr_rst_delayed                    ;\n  reg                         rd_rst_delayed                    ;\n  reg                         wr_en_delayed                     ;\n  reg                         rd_en_delayed                     ;\n  reg  [C_DIN_WIDTH-1:0]      din_delayed                       ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_delayed         ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_assert_delayed  ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_negate_delayed  ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_delayed          ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_assert_delayed   ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_negate_delayed   ;\n  reg                         injectdbiterr_delayed             ;\n  reg                         injectsbiterr_delayed             ;\n   wire                        empty_p0_out;\n\n  always @* rst_delayed                       <= #`TCQ RST                      ;\n  always @* empty_fb                       <= #`TCQ empty_p0_out                      ;\n  always @* srst_delayed                      <= #`TCQ SRST                     ; \n  always @* wr_rst_delayed                    <= #`TCQ WR_RST                   ; \n  always @* rd_rst_delayed                    <= #`TCQ RD_RST                   ; \n  always @* din_delayed                       <= #`TCQ DIN                      ; \n  always @* wr_en_delayed                     <= #`TCQ WR_EN                    ; \n  always @* rd_en_delayed                     <= #`TCQ RD_EN                    ; \n  always @* prog_empty_thresh_delayed         <= #`TCQ PROG_EMPTY_THRESH        ; \n  always @* prog_empty_thresh_assert_delayed  <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; \n  always @* prog_empty_thresh_negate_delayed  <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; \n  always @* prog_full_thresh_delayed          <= #`TCQ PROG_FULL_THRESH         ; \n  always @* prog_full_thresh_assert_delayed   <= #`TCQ PROG_FULL_THRESH_ASSERT  ; \n  always @* prog_full_thresh_negate_delayed   <= #`TCQ PROG_FULL_THRESH_NEGATE  ; \n  always @* injectdbiterr_delayed             <= #`TCQ INJECTDBITERR            ; \n  always @* injectsbiterr_delayed             <= #`TCQ INJECTSBITERR            ; \n\n  /*****************************************************************************\n   * Derived parameters\n   ****************************************************************************/\n  //There are 2 Verilog behavioral models\n  // 0 = Common-Clock FIFO/ShiftRam FIFO\n  // 1 = Independent Clocks FIFO\n  // 2 = Low Latency Synchronous FIFO\n  // 3 = Low Latency Asynchronous FIFO\n  localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :\n                              (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n\n  //Internal reset signals\n  reg                                rd_rst_asreg    = 1'b0;\n  reg                                rd_rst_asreg_d1 = 1'b0;\n  reg                                rd_rst_asreg_d2 = 1'b0;\n  reg                                rd_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_reg      = 1'b0;\n  reg                                rd_rst_comb     = 1'b1;\n  reg                                rd_rst_comb_d1  = 1'b0;\n  reg                                wr_rst_d0       = 1'b0;\n  reg                                wr_rst_d1       = 1'b0;\n  reg                                wr_rst_d2       = 1'b0;\n  reg                                rd_rst_d0       = 1'b0;\n  reg                                rd_rst_d1       = 1'b0;\n  reg                                rd_rst_d2       = 1'b0;\n  reg                                rd_rst_d3       = 1'b0;\n  reg                                wrrst_done      = 1'b0;\n  reg                                rdrst_done      = 1'b0;\n  reg                                wr_rst_asreg    = 1'b0;\n  reg                                wr_rst_asreg_d1 = 1'b0;\n  reg                                wr_rst_asreg_d2 = 1'b0;\n  reg                                wr_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_wr_d0    = 1'b0;\n  reg                                rd_rst_wr_d1    = 1'b0;\n  reg                                rd_rst_wr_d2    = 1'b0;\n  reg                                wr_rst_reg      = 1'b0;\n  reg                                rst_active_i    = 1'b1;\n  reg                                rst_delayed_d1  = 1'b1;\n  reg                                rst_delayed_d2  = 1'b1;\n  reg                                wr_rst_comb     = 1'b1;\n  reg                                wr_rst_comb_d1  = 1'b0;\n  wire                               wr_rst_i;\n  wire                               rd_rst_i;\n  wire                               rst_i;\n\n  //Internal reset signals\n  reg                                rst_asreg     = 1'b0;\n  reg                                srst_asreg    = 1'b0;\n  reg                                rst_asreg_d1  = 1'b0;\n  reg                                rst_asreg_d2  = 1'b0;\n  reg                                srst_asreg_d1 = 1'b0;\n  reg                                srst_asreg_d2 = 1'b0;\n  reg                                rst_reg       = 1'b0;\n  reg                                srst_reg      = 1'b0;\n  reg                                rst_comb      = 1'b1;\n  reg                                rst_comb_d1   = 1'b0;\n  wire                               srst_comb;\n  reg                                rst_full_gen_i = 0;\n  reg                                rst_full_ff_i = 0;\n  reg  [2:0]                         sckt_ff0_bsy_o_i = {3{1'b0}};\n                                     \n  wire                               RD_CLK_P0_IN;\n  wire                               RST_P0_IN;\n  wire                               RD_EN_FIFO_IN;\n  wire                               RD_EN_P0_IN;\n\n  wire                               ALMOST_EMPTY_FIFO_OUT;\n  wire                               ALMOST_FULL_FIFO_OUT;\n  wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT_FIFO_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DOUT_FIFO_OUT;\n  wire                               EMPTY_FIFO_OUT;\n  wire                               fifo_empty_fb;\n  wire                               FULL_FIFO_OUT;\n  wire                               OVERFLOW_FIFO_OUT;\n  wire                               PROG_EMPTY_FIFO_OUT;\n  wire                               PROG_FULL_FIFO_OUT;\n  wire                               VALID_FIFO_OUT;\n  wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT_FIFO_OUT;\n  wire                               UNDERFLOW_FIFO_OUT;\n  wire                               WR_ACK_FIFO_OUT;\n  wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT_FIFO_OUT;\n\n\n  //***************************************************************************\n  // Internal Signals\n  //   The core uses either the internal_ wires or the preload0_ wires depending\n  //     on whether the core uses Preload0 or not.\n  //   When using preload0, the internal signals connect the internal core to\n  //     the preload logic, and the external core's interfaces are tied to the\n  //     preload0 signals from the preload logic.\n  //***************************************************************************\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_OUT;\n  wire                               VALID_P0_OUT;\n  wire                               EMPTY_P0_OUT;\n  wire                               ALMOSTEMPTY_P0_OUT;\n  reg                                EMPTY_P0_OUT_Q;\n  reg                                ALMOSTEMPTY_P0_OUT_Q;\n  wire                               UNDERFLOW_P0_OUT;\n  wire                               RDEN_P0_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_IN;\n  wire                               EMPTY_P0_IN;\n  reg  [31:0]                        DATA_COUNT_FWFT;\n  reg                                SS_FWFT_WR  ;\n  reg                                SS_FWFT_RD ;\n\n  wire                               sbiterr_fifo_out;\n  wire                               dbiterr_fifo_out;\n  wire                               inject_sbit_err;\n  wire                               inject_dbit_err;\n  wire                               sckt_wr_rst_i;\n  wire                               sckt_rd_rst_i;\n  reg                                sckt_wr_rst_i_q = 1'b0;\n \n  wire                               w_fab_read_data_valid_i;\n  wire                               w_read_data_valid_i;\n  wire                               w_ram_valid_i;\n  // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.\n  assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectsbiterr_delayed : 0;\n  assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectdbiterr_delayed : 0;\n                           \n  assign wr_rst_i_out = wr_rst_i;\n  assign rd_rst_i_out = rd_rst_i;\n  assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];\n  generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o\n    wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;\n    always @ (posedge clk_i)\n      sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; \n  end endgenerate \n// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL\n// parameter (1=Independent Clocks, 0=Common Clock)\n\n  localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;\ngenerate\ncase (C_VERILOG_IMPL)\n0 : begin : block1_ss\n  //Common Clock Behavioral Model\n  fifo_generator_v13_2_1_bhv_ver_ss\n  #(\n    .C_FAMILY                            (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                  (C_DATA_COUNT_WIDTH),            \n    .C_DIN_WIDTH                         (C_DIN_WIDTH),                   \n    .C_DOUT_RST_VAL                      (C_DOUT_RST_VAL),                \n    .C_DOUT_WIDTH                        (C_DOUT_WIDTH),                  \n    .C_FULL_FLAGS_RST_VAL                (FULL_FLAGS_RST_VAL),            \n    .C_HAS_ALMOST_EMPTY                  (C_HAS_ALMOST_EMPTY),            \n    .C_HAS_ALMOST_FULL                   ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),             \n    .C_HAS_DATA_COUNT                    (C_HAS_DATA_COUNT),              \n    .C_HAS_OVERFLOW                      (C_HAS_OVERFLOW),                \n    .C_HAS_RD_DATA_COUNT                 (C_HAS_RD_DATA_COUNT),           \n    .C_HAS_RST                           (C_EN_SAFETY_CKT?0:C_HAS_RST),                     \n    .C_HAS_SRST                          (C_EN_SAFETY_CKT?1:C_HAS_SRST),                    \n    .C_HAS_UNDERFLOW                     (C_HAS_UNDERFLOW),               \n    .C_HAS_VALID                         (C_HAS_VALID),                   \n    .C_HAS_WR_ACK                        (C_HAS_WR_ACK),                  \n    .C_HAS_WR_DATA_COUNT                 (C_HAS_WR_DATA_COUNT),           \n    .C_IMPLEMENTATION_TYPE               (C_IMPLEMENTATION_TYPE),         \n    .C_MEMORY_TYPE                       (C_MEMORY_TYPE),                 \n    .C_OVERFLOW_LOW                      (C_OVERFLOW_LOW),                \n    .C_PRELOAD_LATENCY                   (C_PRELOAD_LATENCY),             \n    .C_PRELOAD_REGS                      (C_PRELOAD_REGS),                \n    .C_PROG_EMPTY_THRESH_ASSERT_VAL      (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL      (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                   (C_PROG_EMPTY_TYPE),             \n    .C_PROG_FULL_THRESH_ASSERT_VAL       (C_PROG_FULL_THRESH_ASSERT_VAL), \n    .C_PROG_FULL_THRESH_NEGATE_VAL       (C_PROG_FULL_THRESH_NEGATE_VAL), \n    .C_PROG_FULL_TYPE                    (C_PROG_FULL_TYPE),              \n    .C_RD_DATA_COUNT_WIDTH               (C_RD_DATA_COUNT_WIDTH),         \n    .C_RD_DEPTH                          (C_RD_DEPTH),                    \n    .C_RD_PNTR_WIDTH                     (C_RD_PNTR_WIDTH),               \n    .C_UNDERFLOW_LOW                     (C_UNDERFLOW_LOW),               \n    .C_USE_DOUT_RST                      (C_USE_DOUT_RST),                \n    .C_USE_EMBEDDED_REG                  (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                     (C_EN_SAFETY_CKT),            \n    .C_USE_FWFT_DATA_COUNT               (C_USE_FWFT_DATA_COUNT),         \n    .C_VALID_LOW                         (C_VALID_LOW),                   \n    .C_WR_ACK_LOW                        (C_WR_ACK_LOW),                  \n    .C_WR_DATA_COUNT_WIDTH               (C_WR_DATA_COUNT_WIDTH),         \n    .C_WR_DEPTH                          (C_WR_DEPTH),                    \n    .C_WR_PNTR_WIDTH                     (C_WR_PNTR_WIDTH),               \n    .C_USE_ECC                           (C_USE_ECC),                     \n    .C_ENABLE_RST_SYNC                   (C_ENABLE_RST_SYNC),             \n    .C_ERROR_INJECTION_TYPE              (C_ERROR_INJECTION_TYPE),\n    .C_FIFO_TYPE                         (C_FIFO_TYPE)                     \n  )\n  gen_ss\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .CLK                      (CLK),\n    .RST                      (C_EN_SAFETY_CKT?1'b0:rst_i),\n    .SRST                     (C_EN_SAFETY_CKT?sckt_wr_rst_i:srst_delayed),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .USER_EMPTY_FB            (empty_fb),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .DATA_COUNT               (DATA_COUNT_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .WR_RST_BUSY              (wr_rst_busy),\n    .RD_RST_BUSY              (rd_rst_busy),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n1 : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_1_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT), \n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .fab_read_data_valid_i    (w_fab_read_data_valid_i),\n    .read_data_valid_i        (w_read_data_valid_i),\n    .ram_valid_i              (w_ram_valid_i),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\n2 : begin : ll_afifo_inst\n  fifo_generator_v13_2_1_beh_ver_ll_afifo\n  #(\n    .C_DIN_WIDTH                    (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                 (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                   (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_RD_DATA_COUNT            (C_HAS_RD_DATA_COUNT),\n    .C_HAS_WR_DATA_COUNT            (C_HAS_WR_DATA_COUNT),\n    .C_RD_DEPTH                     (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                (C_RD_PNTR_WIDTH),\n    .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n    .C_WR_DATA_COUNT_WIDTH          (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                     (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                (C_WR_PNTR_WIDTH),\n    .C_FIFO_TYPE                    (C_FIFO_TYPE)\n   )\n  gen_ll_afifo\n  (\n    .DIN                        (din_delayed),\n    .RD_CLK                     (RD_CLK),\n    .RD_EN                      (rd_en_delayed),\n    .WR_RST                     (wr_rst_i),\n    .RD_RST                     (rd_rst_i),\n    .WR_CLK                     (WR_CLK),\n    .WR_EN                      (wr_en_delayed),\n    .DOUT                       (DOUT),\n    .EMPTY                      (EMPTY),\n    .FULL                       (FULL)\n  );\nend\ndefault : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_1_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT),\n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\nendcase\nendgenerate\n\n\n   //**************************************************************************\n   // Connect Internal Signals\n   //   (Signals labeled internal_*)\n   //  In the normal case, these signals tie directly to the FIFO's inputs and\n   //    outputs.\n   //  In the case of Preload Latency 0 or 1, there are intermediate\n   //    signals between the internal FIFO and the preload logic.\n   //**************************************************************************\n   \n   \n   //***********************************************\n   // If First-Word Fall-Through, instantiate\n   // the preload0 (FWFT) module\n   //***********************************************\n   wire                        rd_en_to_fwft_fifo;\n   wire                        sbiterr_fwft;\n   wire                        dbiterr_fwft;\n   wire [C_DOUT_WIDTH-1:0]     dout_fwft;\n   wire                        empty_fwft;\n   wire                        rd_en_fifo_in;\n   wire                        stage2_reg_en_i;\n   wire [1:0]                  valid_stages_i;\n   wire                        rst_fwft;\n   //wire                        empty_p0_out;\n   reg  [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n   localparam IS_PKT_FIFO      = (C_FIFO_TYPE == 1) ? 1 : 0;\n   localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;\n   assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2_fwft\n\n\n         fifo_generator_v13_2_1_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_EMBEDDED_REG  (C_USE_EMBEDDED_REG),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (C_FIFO_TYPE)\n             )\n             fgpl0\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (RST_P0_IN),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (RD_EN_P0_IN),\n                .FIFOEMPTY        (EMPTY_P0_IN),\n                .FIFODATA         (DATA_P0_IN),\n                .FIFOSBITERR      (sbiterr_fifo_out),\n                .FIFODBITERR      (dbiterr_fifo_out),\n                // Output\n                .USERDATA         (dout_fwft),\n                .USERVALID        (VALID_P0_OUT),\n                .USEREMPTY        (empty_fwft),\n                .USERALMOSTEMPTY  (ALMOSTEMPTY_P0_OUT),\n                .USERUNDERFLOW    (UNDERFLOW_P0_OUT),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_fifo_in),\n                .USERSBITERR      (sbiterr_fwft),\n                .USERDBITERR      (dbiterr_fwft),\n                .STAGE2_REG_EN    (stage2_reg_en_i),\n                .fab_read_data_valid_i_o    (w_fab_read_data_valid_i),\n                .read_data_valid_i_o        (w_read_data_valid_i),\n                .ram_valid_i_o              (w_ram_valid_i),\n                .VALID_STAGES                (valid_stages_i)\n                );\n\n         \n         //***********************************************\n         // Connect inputs to preload (FWFT) module\n         //***********************************************\n         //Connect the RD_CLK of the Preload (FWFT) module to CLK if we \n         // have a common-clock FIFO, or RD_CLK if we have an \n         // independent clock FIFO\n         assign RD_CLK_P0_IN       = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);\n         assign RST_P0_IN          = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;\n         assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n         assign EMPTY_P0_IN        = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;\n         assign DATA_P0_IN         = DOUT_FIFO_OUT;\n         \n         //***********************************************\n         // Connect outputs from preload (FWFT) module\n         //***********************************************\n         assign VALID              = VALID_P0_OUT ;\n         assign ALMOST_EMPTY       = ALMOSTEMPTY_P0_OUT;\n         assign UNDERFLOW          = UNDERFLOW_P0_OUT ;\n         \n         assign RD_EN_FIFO_IN      = rd_en_fifo_in;\n         \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:\n           (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : \n           DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];  \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               EMPTY_P0_OUT_Q       <= 1;\n               ALMOSTEMPTY_P0_OUT_Q <= 1;\n            end else begin\n               EMPTY_P0_OUT_Q       <= #`TCQ empty_p0_out;\n//               EMPTY_P0_OUT_Q       <= #`TCQ EMPTY_FIFO_OUT;\n               ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;\n            end\n         end //always\n         \n         \n         //***********************************************\n         // logic for common-clock data count when FWFT is selected\n         //***********************************************\n         initial begin\n            SS_FWFT_RD = 1'b0;\n            DATA_COUNT_FWFT = 0 ;\n            SS_FWFT_WR   = 1'b0 ;\n         end //initial\n         \n         \n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter. SS_FWFT_WR and SS_FWFT_RD\n         // are the up/down enables for the counter.\n         //***********************************************\n         always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin\n            if (C_VALID_LOW == 1) begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;\n            end else begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;\n            end\n            SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT))  ;\n         end \n\n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter for FWFT. This always block \n         // calculates the counter.\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               DATA_COUNT_FWFT      <= 0;\n            end else begin\n               //if (srst_delayed && (C_HAS_SRST == 1) ) begin\n               if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin\n                  DATA_COUNT_FWFT      <= #`TCQ 0;\n               end else begin\n                  case ( {SS_FWFT_WR, SS_FWFT_RD})\n                    2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                    2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;\n                    2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;\n                    2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                  endcase  \n               end //if SRST\n            end //IF RST\n         end //always\n\n      end endgenerate // : block2\n\n    // AXI Streaming Packet FIFO\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_plus1 = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_reg   = 0;\n    reg                         partial_packet     = 0;\n    reg                         stage1_eop_d1      = 0;\n    reg                         rd_en_fifo_in_d1   = 0;\n    reg                         eop_at_stage2      = 0;\n    reg                         ram_pkt_empty      = 0;\n    reg                         ram_pkt_empty_d1   = 0;\n\n    wire [C_DOUT_WIDTH-1:0]     dout_p0_out;\n    wire                        packet_empty_wr;\n    wire                        wr_rst_fwft_pkt_fifo;\n    wire                        dummy_wr_eop;\n    wire                        ram_wr_en_pkt_fifo;\n    wire                        wr_eop;\n    wire                        ram_rd_en_compare;\n    wire                        stage1_eop;\n    wire                        pkt_ready_to_read;\n    wire                        rd_en_2_stage2;\n\n    // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)\n    // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP\n    // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of\n    // write packet count\n    generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop\n       always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n          if (wr_rst_fwft_pkt_fifo)\n             partial_packet   <= 1'b0;\n          else begin\n             if (srst_delayed | wr_rst_busy | rd_rst_busy)\n                partial_packet <= #`TCQ 1'b0;\n             else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))\n                partial_packet <= #`TCQ 1'b1;\n             else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)\n                partial_packet <= #`TCQ 1'b0;\n          end\n        end\n    end endgenerate // gdummy_wr_eop\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin : gpkt_fifo_fwft\n      assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;\n      assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);\n      assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];\n  \n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft) begin\n          stage1_eop_d1    <= 1'b0;\n          rd_en_fifo_in_d1 <= 1'b0;\n        end else begin\n          if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            stage1_eop_d1    <= #`TCQ 1'b0;\n            rd_en_fifo_in_d1 <= #`TCQ 1'b0;\n          end else begin\n            stage1_eop_d1    <= #`TCQ stage1_eop;\n            rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;\n          end\n        end\n      end\n      assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;\n      assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);\n      assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);\n      assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;\n\n\n         fifo_generator_v13_2_1_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (2) // Enable low latency fwft logic\n             )\n         pkt_fifo_fwft\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (rst_fwft),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (rd_en_delayed),\n                .FIFOEMPTY        (pkt_ready_to_read),\n                .FIFODATA         (dout_fwft),\n                .FIFOSBITERR      (sbiterr_fwft),\n                .FIFODBITERR      (dbiterr_fwft),\n                // Output\n                .USERDATA         (dout_p0_out),\n                .USERVALID        (),\n                .USEREMPTY        (empty_p0_out),\n                .USERALMOSTEMPTY  (),\n                .USERUNDERFLOW    (),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_2_stage2),\n                .USERSBITERR      (SBITERR),\n                .USERDBITERR      (DBITERR),\n                .STAGE2_REG_EN    (),\n                .VALID_STAGES     ()\n                );\n\n      assign pkt_ready_to_read  = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));\n      assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft)\n          eop_at_stage2 <= 1'b0;\n        else if (stage2_reg_en_i)\n          eop_at_stage2 <= #`TCQ stage1_eop;\n      end\n\n      //---------------------------------------------------------------------------\n      // Write and Read Packet Count\n      //---------------------------------------------------------------------------\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count  <= 0;\n         else if (srst_delayed  | wr_rst_busy | rd_rst_busy)\n            wr_pkt_count  <= #`TCQ 0;\n         else if (wr_eop)\n            wr_pkt_count  <= #`TCQ wr_pkt_count + 1;\n      end\n    \n    end endgenerate //: gpkt_fifo_fwft\n\n    assign DOUT               = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;\n    assign EMPTY              = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            rd_pkt_count       <= 0;\n            rd_pkt_count_plus1 <= 1;\n         end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            rd_pkt_count       <= #`TCQ 0;\n            rd_pkt_count_plus1 <= #`TCQ 1;\n         end else if (stage2_reg_en_i && stage1_eop) begin\n            rd_pkt_count       <= #`TCQ rd_pkt_count + 1;\n            rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;\n         end\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (SRST | wr_rst_busy | rd_rst_busy) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n    end endgenerate //grss_pkt_cnt\n    \n    localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;\n    reg  [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_b2g = 0;\n    wire [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_rd;\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt\n      // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count_b2g  <= 0;\n         else\n            wr_pkt_count_b2g  <= #`TCQ wr_pkt_count;\n      end\n\n      // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            wr_pkt_count_q       <= 0;\n         else\n            wr_pkt_count_q       <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};\n      end\n\n      always @* begin\n        if (stage1_eop)\n           rd_pkt_count    <= rd_pkt_count_reg + 1;\n        else\n           rd_pkt_count    <= rd_pkt_count_reg;\n      end\n\n      assign wr_pkt_count_rd    = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            rd_pkt_count_reg       <= 0;\n         else if (rd_en_fifo_in)\n            rd_pkt_count_reg       <= #`TCQ rd_pkt_count;\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (rd_pkt_count != wr_pkt_count_rd) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n\n      // Synchronize the empty in write domain\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            pkt_empty_sync  <= 'b1;\n         else\n            pkt_empty_sync  <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};\n      end\n\n    end endgenerate //gras_pkt_cnt\n\n   generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO\n\n     //***********************************************\n     // If NOT First-Word Fall-Through, wire the outputs\n     // of the internal _ss or _as FIFO directly to the\n     // output, and do not instantiate the preload0\n     // module.\n     //***********************************************\n\n     assign RD_CLK_P0_IN       = 0;\n     assign RST_P0_IN          = 0;\n     assign RD_EN_P0_IN        = 0;\n\n     assign RD_EN_FIFO_IN      = rd_en_delayed;\n\n     assign DOUT               = DOUT_FIFO_OUT;\n     assign DATA_P0_IN         = 0;\n     assign VALID              = VALID_FIFO_OUT;\n     assign EMPTY              = EMPTY_FIFO_OUT;\n     assign ALMOST_EMPTY       = ALMOST_EMPTY_FIFO_OUT;\n     assign EMPTY_P0_IN        = 0;\n     assign UNDERFLOW          = UNDERFLOW_FIFO_OUT;\n     assign DATA_COUNT         = DATA_COUNT_FIFO_OUT;\n     assign SBITERR            = sbiterr_fifo_out;\n     assign DBITERR            = dbiterr_fifo_out;\n\n   end endgenerate // STD_FIFO\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO\n     assign empty_p0_out       = empty_fwft;\n     assign SBITERR            = sbiterr_fwft;\n     assign DBITERR            = dbiterr_fwft;\n     assign DOUT               = dout_fwft;\n     assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n\n   end endgenerate // NO_PKT_FIFO\n\n   //***********************************************\n   // Connect user flags to internal signals\n   //***********************************************\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3\n      if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);\n      end //block_ic\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3\n   endgenerate\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30\n       if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30\n   endgenerate\n\n\n    \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both\n       if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30_both\n   endgenerate\n\n generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both\n      if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));\n      end //block_ic_both\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3_both\n   endgenerate\n\n\n   //If we are not using extra logic for the FWFT data count,\n   //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the\n   //internal FIFO instance  \n   generate\n      if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n   //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal\n   //FIFO instance\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1) begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n      else begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n\n   //Connect other flags to the internal FIFO instance\n   assign       FULL        = FULL_FIFO_OUT;\n   assign       ALMOST_FULL = ALMOST_FULL_FIFO_OUT;\n   assign       WR_ACK      = WR_ACK_FIFO_OUT;\n   assign       OVERFLOW    = OVERFLOW_FIFO_OUT;\n   assign       PROG_FULL   = PROG_FULL_FIFO_OUT;\n   assign       PROG_EMPTY  = PROG_EMPTY_FIFO_OUT;\n\n\n  /**************************************************************************\n  * find_log2\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n   // if an asynchronous FIFO has been selected, display a message that the FIFO\n   //   will not be cycle-accurate in simulation\n   initial begin\n      if (C_IMPLEMENTATION_TYPE == 2) begin\n         $display(\"WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.\");\n      end else if (C_MEMORY_TYPE == 4) begin\n         $display(\"FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.\");\n         $finish;\n      end\n\n      if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin\n         $display(\"FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.\");\n         $finish;\n      end\n\n      if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin\n         $display(\"FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.\");\n         $finish;\n      end\n\n      if (C_USE_ECC == 1) begin\n         if (C_DIN_WIDTH != C_DOUT_WIDTH) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.\");\n            $finish;\n         end\n         if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.\");\n            $finish;\n         end\n      end\n\n   end //initial\n\n  /**************************************************************************\n  * Internal reset logic\n  **************************************************************************/\n  assign wr_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg|sckt_wr_rst_i : 0;\n  assign rd_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg|sckt_rd_rst_i : 0;\n  assign rst_i            = C_HAS_RST ? rst_reg|sckt_wr_rst_i : 0;\n\n  wire rst_2_sync;\n  wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;\n\n  localparam RST_SYNC_STAGES = C_EN_SAFETY_CKT == 0 ? C_COMMON_CLOCK ? C_SYNCHRONIZER_STAGE : C_SYNCHRONIZER_STAGE+2 : 5;\n  localparam RST_BUSY_LEN    = 4;\n  reg  wr_rst_busy_i = 0;\n  reg  rd_rst_busy_i = 0;\n  generate\n      if (C_ENABLE_RST_SYNC == 0 || (C_HAS_RST == 0 && C_HAS_SRST == 0)) begin : gnrst_sync\n        always @* begin\n          wr_rst_reg <= wr_rst_delayed;\n          rd_rst_reg <= rd_rst_delayed;\n          rst_reg    <= 1'b0;\n          srst_reg    <= 1'b0;\n        end\n        assign rst_2_sync = wr_rst_delayed;\n        assign wr_rst_busy = 1'b0;\n        assign wr_rst_busy_o = 1'b0;\n        assign rd_rst_busy = 1'b0;\n        assign sckt_wr_rst_i = 1'b0;\n      end // gnrst_sync\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 0) begin : g7s_ic_rst_nsckt\n        reg [1:0]                 arst_sync_wr  = 2'b11;\n        reg [1:0]                 arst_sync_rd  = 2'b11;\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge WR_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge RD_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_rd    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_rd    <= #`TCQ {arst_sync_rd[0], rst_delayed};\n        end\n        always @(posedge WR_CLK) begin\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n\tend\n        always @(posedge WR_CLK or posedge arst_sync_wr[1]) begin\n\t  if (arst_sync_wr[1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n            rd_rst_wr_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            rd_rst_wr_ext  <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t    if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t      sckt_wr_rst_ic <= #`TCQ 1'b0;\n            else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t      wr_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n        always @(posedge RD_CLK) begin\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], sckt_wr_rst_ic};\n\tend\n        always @(posedge RD_CLK or posedge arst_sync_rd[1]) begin\n\t  if (arst_sync_rd[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n            wr_rst_rd_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            wr_rst_rd_ext  <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t    if (wr_rst_rd_ext[1]) begin\n\t      sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t      rd_rst_busy_i  <= #`TCQ 1'b0;\n\t    end\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic|arst_sync_wr[1];\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic|arst_sync_rd[1];\n      end // g7s_ic_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 1) begin : g7s_ic_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] arst_sync_rd  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        always @(posedge WR_CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n          rd_rst_wr_ext    <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_wr[RST_SYNC_STAGES-1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n          end else if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t    sckt_wr_rst_ic <= #`TCQ 1'b0;\n          else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t    wr_rst_busy_i  <= #`TCQ 1'b0;\n\tend\n        always @(posedge RD_CLK) begin\n\t  arst_sync_rd     <= #`TCQ {arst_sync_rd[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n          wr_rst_rd_ext    <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_rd[RST_SYNC_STAGES-1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n\t  end else if (wr_rst_rd_ext[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t    rd_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic;\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic;\n      end // g7s_ic_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 0) begin : g7s_cc_rst_nsckt\n        reg [1:0]              arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge CLK) begin\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0] | arst_sync_wr[1]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc | arst_sync_wr[1];\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 1) begin : g7s_cc_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n\n        always @(posedge CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc;\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst\n        assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;\n        assign rd_rst_busy = rst_reg;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = rst_reg;\n        always @* rst_full_ff_i  <= 1'b0;\n        always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;\n\n        always @(posedge CLK) begin\n          rst_delayed_d1 <= #`TCQ srst_delayed;\n          rst_delayed_d2 <= #`TCQ rst_delayed_d1;\n          if (rst_reg || rst_delayed_d2) begin\n            rst_active_i <= #`TCQ 1'b1;\n          end else begin\n            rst_active_i <= #`TCQ rst_reg;\n          end    \n        end   \n        always @(posedge CLK) begin\n          if (~rst_reg && srst_delayed) begin\n             rst_reg <= #`TCQ 1'b1;\n           end else if (rst_reg) begin\n             rst_reg <= #`TCQ 1'b0;\n           end else begin\n             rst_reg <= #`TCQ rst_reg;\n           end    \n        end   \n      end // g8s_cc_rst\n      else if (IS_8SERIES != 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_srst\n        assign wr_rst_busy = srst_delayed;\n        assign rd_rst_busy = srst_delayed;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = srst_delayed;\n        always @* rst_full_ff_i  <= 1'b0;\n      end // g7s_cc_srst\n  endgenerate \n\n  reg rst_d1 = 1'b0;\n  reg rst_d2 = 1'b0;\n  reg rst_d3 = 1'b0;\n  reg rst_d4 = 1'b0;\n  generate\n    if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1\n    // RST_FULL_GEN replaces the reset falling edge detection used to de-assert\n    // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.\n\n    // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &\n    // PROG_FULL\n\n      always @ (posedge rst_2_sync or posedge clk_2_sync) begin\n        if (rst_2_sync && C_EN_SAFETY_CKT == 0) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          rst_d3         <= 1'b1;\n          rst_d4         <= 1'b0;\n        end else begin\n          if (srst_delayed) begin\n            rst_d1         <= #`TCQ 1'b1;\n            rst_d2         <= #`TCQ 1'b1;\n            rst_d3         <= #`TCQ 1'b1;\n            rst_d4         <= #`TCQ 1'b0;\n          end else begin\n            rst_d1         <= #`TCQ wr_rst_busy;//1'b0;\n            rst_d2         <= #`TCQ rst_d1;\n            rst_d3         <= #`TCQ rst_d2 | sckt_wr_rst_i;\n            rst_d4         <= #`TCQ rst_d3;\n          end\n        end\n      end\n\n      always @* rst_full_ff_i  <= C_HAS_SRST ? 1'b0 : rst_d2 | sckt_wr_rst_i;\n      always @* rst_full_gen_i <= C_HAS_SRST ? rst_d4 : rst_d3;\n\n    end else if (C_EN_SAFETY_CKT == 1 && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full_sckt\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end\n  endgenerate // grstd1\n\nendmodule //fifo_generator_v13_2_1_CONV_VER\n\n\nmodule fifo_generator_v13_2_1_sync_stage\n  #(\n    parameter  C_WIDTH          = 10\n   )\n   (\n    input                     RST,\n    input                     CLK,\n    input       [C_WIDTH-1:0] DIN,\n    output reg  [C_WIDTH-1:0] DOUT = 0\n   );\n   always @ (posedge RST or posedge CLK) begin\n     if (RST)\n       DOUT <= 0;\n     else\n       DOUT <= #`TCQ DIN;\n   end\nendmodule // fifo_generator_v13_2_1_sync_stage\n\n/*******************************************************************************\n * Declaration of Independent-Clocks FIFO Module\n ******************************************************************************/\nmodule fifo_generator_v13_2_1_bhv_ver_as\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2 \n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input                                         SAFETY_CKT_WR_RST,\n   input                                         SAFETY_CKT_RD_RST,\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_ASSERT,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_NEGATE,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_ASSERT,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_NEGATE,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         RD_EN_USER,\n   input                                         RST,\n   input                                         RST_FULL_GEN,\n   input                                         RST_FULL_FF,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   input                                         INJECTDBITERR,\n   input                                         INJECTSBITERR,\n   input                                         USER_EMPTY_FB,\n   input                                         fab_read_data_valid_i,\n   input                                         read_data_valid_i,\n   input                                         ram_valid_i,\n   output reg                                    ALMOST_EMPTY = 1'b1,\n   output reg                                    ALMOST_FULL = C_FULL_FLAGS_RST_VAL,\n   output      [C_DOUT_WIDTH-1:0]                DOUT,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    EMPTY_FB = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL,\n   output                                        OVERFLOW,\n   output                                        PROG_EMPTY,\n   output                                        PROG_FULL,\n   output                                        VALID,\n   output      [C_RD_DATA_COUNT_WIDTH-1:0]       RD_DATA_COUNT,\n   output                                        UNDERFLOW,\n   output                                        WR_ACK,\n   output      [C_WR_DATA_COUNT_WIDTH-1:0]       WR_DATA_COUNT,\n   output                                        SBITERR,\n   output                                        DBITERR\n  );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   \n  \n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   \n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;\n   // Array that holds the error injection type (single/double bit error) on \n   // a specific write operation, which is returned on read to corrupt the\n   // output data.\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   //The amount of data stored in the FIFO at any time is given\n   // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK\n   // domain.\n   //num_wr_bits is calculated by considering the total words in the FIFO,\n   // and the state of the read pointer (which may not have yet crossed clock\n   // domains.)\n   //num_rd_bits is calculated by considering the total words in the FIFO,\n   // and the state of the write pointer (which may not have yet crossed clock\n   // domains.)\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   wire                        wr_rst_i = WR_RST;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n   wire                        rd_rst_i = RD_RST;\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n\n\n\n   // Delayed ram_rd_en is needed only for STD Embedded register option\n   generate\n     if (C_PRELOAD_LATENCY == 2) begin : grd_d\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n       end\n     end\n   endgenerate\n   \n    generate\n     if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n           fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n       end\n     end\n   endgenerate\n\n  \n\n   // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;\n     end else begin : rdl // Read depth lesser than or equal to write depth\n       assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n     end\n   endgenerate\n\n   // Generate Empty and Almost Empty\n  // ram_rd_en used to determine EMPTY should depend on the EMPTY.\n   assign ram_rd_en        = RD_EN & !EMPTY;\n   assign empty_int        = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));\n   assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));\n\n   // Register Empty and Almost Empty\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else begin\n         rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};\n\n         if (empty_int)\n           EMPTY           <= #`TCQ 1'b1;\n         else\n           EMPTY           <= #`TCQ 1'b0;\n\n         if (!EMPTY) begin\n           if (almost_empty_int)\n             ALMOST_EMPTY  <= #`TCQ 1'b1;\n           else\n             ALMOST_EMPTY  <= #`TCQ 1'b0;\n         end\n       end // rd_rst_i\n     end // always\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY_FB     <= 1'b1;\n       end else begin\n         if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else if (empty_int)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else\n           EMPTY_FB   <= #`TCQ 1'b0;\n       end // rd_rst_i\n     end // always\n\n   // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;\n     end else begin : wdl // Write depth lesser than or equal to read depth\n       assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n     end\n   endgenerate\n\n  // Generate FULL and ALMOST_FULL\n  // ram_wr_en used to determine FULL should depend on the FULL.\n  assign ram_wr_en       = WR_EN & !FULL;\n  assign full_int        = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));\n  assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));\n\n   // Register FULL and ALMOST_FULL Empty\n   always @ (posedge WR_CLK or posedge RST_FULL_FF)\n     begin\n       if (RST_FULL_FF & C_HAS_RST) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else begin\n         if (full_int) begin\n           FULL           <= #`TCQ 1'b1;\n         end else begin\n           FULL           <= #`TCQ 1'b0;\n         end\n\n         if (RST_FULL_GEN) begin\n           ALMOST_FULL    <= #`TCQ 1'b0;\n         end else if (!FULL) begin\n           if (almost_full_int)\n             ALMOST_FULL  <= #`TCQ 1'b1;\n           else\n             ALMOST_FULL  <= #`TCQ 1'b0;\n         end\n       end // wr_rst_i\n     end // always\n   always @ (posedge WR_CLK or posedge wr_rst_i)\n     begin\n       if (wr_rst_i) begin\n         wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};\n       end else begin\n         wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};\n       end // wr_rst_i\n     end // always\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i) begin\n           stage1_valid     <= 0;\n           stage2_valid     <= 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n   //Pointers passed into opposite clock domain\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_EMPTY.\n   wire [31:0] num_read_words_pe = \n     num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_FULL.\n   wire [31:0] num_write_words_pf =\n     num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n    \n    \n   /***************************************************************************\n    * Internal registers and wires\n    **************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire [C_DOUT_WIDTH-1:0] ideal_dout_out;      \n   wire valid_i;\n   wire valid_out1;\n   wire valid_out2;\n   wire valid_out;  \n   wire underflow_i;\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]               err_type                 = 0;\n   reg [1:0]               err_type_d1              = 0;\n   reg [1:0]               err_type_both              = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout               = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_d1            = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_both            = 0;\n   reg                     ideal_wr_ack             = 0;\n   reg                     ideal_valid              = 0;\n   reg                     ideal_overflow           = C_OVERFLOW_LOW;\n   reg                     ideal_underflow          = C_UNDERFLOW_LOW;\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   reg         valid_d1     = 0;\n   reg         valid_d2     = 0; \n   \n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n   \n\n  /****************************************************************************\n   * Function Declarations\n   ***************************************************************************/\n\n  /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n      if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n    end\n  endtask\n\n  /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n  /***********************************************************************\n  * hexstr_conv\n  *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n  ***********************************************************************/\n  function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_d2           = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n    end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the \n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n    wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;   \n   wire RD_CLK;\n   wire RD_EN;\n   wire RST;\n   wire WR_CLK;\n   wire WR_EN;\n    */\n\n   //***************************************************************************\n   // Dout may change behavior based on latency\n   //***************************************************************************\n   assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?\n                         ideal_dout_d1: ideal_dout;   \n   assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; \n\n   //***************************************************************************\n   // Assign SBITERR and DBITERR based on latency \n   //***************************************************************************\n   assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                    (C_PRELOAD_LATENCY == 2 &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?\n                    err_type_d1[0]: err_type[0]; \n   assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                    (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                    err_type_d1[1]: err_type[1]; \n  \n   //***************************************************************************\n   // Safety-ckt logic with embedded reg/fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n       //  if (C_HAS_VALID == 1) begin\n       //       assign valid_out = valid_d1;\n       //  end\n             \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)\n          begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else \n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n          end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                  @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n           end\n           else begin\n                   if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                   end\n             end \n           end  \n      end \n      endgenerate   \n\n//***************************************************************************\n   // Safety-ckt logic with embedded reg + fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else begin\n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n               fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n          end\n        end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   ideal_dout_both <= #`TCQ dout_reset_val;\n              end\n           end else begin\n             if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n              \n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n             end\n           end \n         end      \n      end \n      endgenerate    \n \n   //***************************************************************************\n   // Overflow may be active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_OVERFLOW==1) begin : blockOF1\n   assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n      end\n   endgenerate\n\n   assign PROG_EMPTY = ideal_prog_empty;\n   assign PROG_FULL  = ideal_prog_full;\n\n   //***************************************************************************\n   // Valid may change behavior based on latency or active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_VALID==1) begin : blockVL1\n   assign valid_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;\n   assign valid_out1 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?\n                       valid_d1: valid_i;  \n   assign valid_out2 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?\n                       valid_d2: valid_i; \n   assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;\n   assign VALID     = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Underflow may change behavior based on latency or active-low   \n   //***************************************************************************\n   generate\n      if (C_HAS_UNDERFLOW==1) begin : blockUF1\n   assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;\n   assign UNDERFLOW   = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n    end\n   endgenerate\n\n   //***************************************************************************\n   // Write acknowledge may be active low\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_ACK==1) begin : blockWK1\n   assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext\n\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_wr_pntr = 0;\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_rd_pntr = 0;\n      wire [C_PNTR_WIDTH-1:0]  diff_wr_rd_tmp;\n      wire [C_PNTR_WIDTH:0]    diff_wr_rd;\n      reg  [C_PNTR_WIDTH:0]    wr_data_count_i  = 0;\n        always @* begin\n          if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = 0;\n            adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n          end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin\n            adjusted_rd_pntr = rd_pntr_wr;\n            adjusted_wr_pntr = 0;\n            adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n          end else begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = rd_pntr_wr;\n          end\n        end // always @*\n\n        assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;\n        assign diff_wr_rd     = {1'b0,diff_wr_rd_tmp};\n\n        always @ (posedge wr_rst_i or posedge WR_CLK)\n        begin\n            if (wr_rst_i)\n              wr_data_count_i <= 0;\n            else\n              wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;\n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n\n        always @* begin\n          if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];\n          else\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n        end // always @*\n      end // wdc_fwft_ext\n   endgenerate\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   reg  [C_RD_PNTR_WIDTH:0]    rdc_fwft_ext_as  = 0;\n\n   generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n\n\n   always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= 0;\n            end else begin\n              if (!stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 0;\n              else if (!stage1_valid && stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 1;\n              else\n                rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;\n            end \n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n      end // rdc_fwft_ext\n end\n   endgenerate\n\n\n  generate if (C_USE_EMBEDDED_REG == 3) begin\n     if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n        wire [C_RD_PNTR_WIDTH:0]  diff_rd_wr_1;\n   //     assign diff_rd_wr_1 = diff_rd_wr +2'h2;\n\n       always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= #`TCQ 0;\n            end else begin\n          //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))\n          //    rdc_fwft_ext_as <= 1'b0;\n          //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) \n          //    rdc_fwft_ext_as <= 1'b1;\n          //else\n            rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;\n        end\n\n\n\nend\nend\nend\nendgenerate\n          \n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1) begin : grdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?\n          rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :\n          rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?\n          wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :\n          wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n\n  /**************************************************************************\n  * Assorted registers for delayed versions of signals\n  **************************************************************************/\n  //Capture delayed version of valid\n  generate\n      if (C_HAS_VALID==1) begin : blockVL2\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n      valid_d1 <= 1'b0;\n      valid_d2 <= 1'b0;\n    end else begin\n      valid_d1 <= #`TCQ valid_i;\n      valid_d2 <= #`TCQ valid_d1;\n    end \n//    if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin\n  //      valid_d2 <= #`TCQ valid_d1;\n      //  end \n  end \n      end\n endgenerate  \n   \n  //Capture delayed version of dout\n  /**************************************************************************\n    *embedded/fabric reg with no safety ckt\n    **************************************************************************/\n  generate \n       if (C_USE_EMBEDDED_REG < 3) begin\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n       if (C_USE_DOUT_RST == 1'b1) begin\n         @(posedge RD_CLK)\n           ideal_dout_d1   <= #`TCQ dout_reset_val;\n           ideal_dout   <= #`TCQ dout_reset_val;\n       end\n      // Reset err_type only if ECC is not selected\n      if (C_USE_ECC == 0)\n        err_type_d1     <= #`TCQ 0;\n     end else if (ram_rd_en_d1) begin\n      ideal_dout_d1   <= #`TCQ ideal_dout;\n      err_type_d1     <= #`TCQ err_type;\n           end    \n  end  \n   \nend  \nendgenerate \n/**************************************************************************\n    *embedded + fabric reg with no safety ckt\n    **************************************************************************/\n\ngenerate \n  if (C_USE_EMBEDDED_REG == 3) begin\n    always @(posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i == 1'b1) begin\n        if (C_USE_DOUT_RST == 1'b1) begin\n           @(posedge RD_CLK)\n             ideal_dout    <= #`TCQ dout_reset_val;\n             ideal_dout_d1   <= #`TCQ dout_reset_val;\n             ideal_dout_both   <= #`TCQ dout_reset_val;\n        end\n        // Reset err_type only if ECC is not selected\n        if (C_USE_ECC == 0) begin\n          err_type_d1     <= #`TCQ 0;\n          err_type_both   <= #`TCQ 0;\n        end\n      end else begin\n         if (ram_rd_en_d1) begin\n           ideal_dout_both   <= #`TCQ ideal_dout;\n           err_type_both     <= #`TCQ err_type;\n         end    \n         if (fab_rd_en_d1) begin\n           ideal_dout_d1   <= #`TCQ ideal_dout_both;\n           err_type_d1     <= #`TCQ err_type_both;\n         end\n      end\n    end  \n  end  \nendgenerate \n\n  \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate\n     if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n       always @(posedge WR_CLK) begin\n         ideal_overflow    <= #`TCQ WR_EN & FULL;\n       end\n     end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n       always @(posedge WR_CLK) begin\n         //ideal_overflow    <= #`TCQ WR_EN & (FULL | wr_rst_i);\n         ideal_overflow    <= #`TCQ WR_EN & (FULL );\n       end\n     end\n   endgenerate\n\n   generate\n     if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ EMPTY & RD_EN;\n       end\n     end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ (EMPTY) & RD_EN;\n         //ideal_underflow    <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;\n       end\n     end\n   endgenerate\n\n   /**************************************************************************\n   * Write/Read Pointer Synchronization\n   **************************************************************************/\n   localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;\n   wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   genvar gss;\n\n   generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst\n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (C_WR_PNTR_WIDTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_i), \n         .CLK      (RD_CLK), \n         .DIN      (wr_pntr_sync_stgs[gss-1]), \n         .DOUT     (wr_pntr_sync_stgs[gss])\n        );\n \n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (C_RD_PNTR_WIDTH)\n        )\n     wr_stg_inst\n        (\n         .RST      (wr_rst_i), \n         .CLK      (WR_CLK), \n         .DIN      (rd_pntr_sync_stgs[gss-1]), \n         .DOUT     (rd_pntr_sync_stgs[gss])\n        );\n   end endgenerate // Sync_stage_inst\n\n   assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;\n   assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;\n   always@* begin\n     wr_pntr_rd           <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n     rd_pntr_wr           <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n   end\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp\n     if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)\n       wr_pntr           <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)\n       wr_pntr           <= #`TCQ 0;\n   end\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (wr_rst_i == 1'b1) begin\n       num_wr_bits       <= 0;\n       next_num_wr_bits   = 0;\n       wr_ptr            <= C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= C_RD_DEPTH - 1;\n       ideal_wr_ack      <= 0;\n       ideal_wr_count    <= 0;\n       tmp_wr_listsize    = 0;\n       rd_ptr_wrclk_next <= 0;\n       wr_pntr_rd1       <= 0;\n\n     end else begin //wr_rst_i==0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       //If this is a write, handle the write by adding the value\n       // to the linked list, and updating all outputs appropriately\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD \n             >= C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full, but reporting full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //With DEPTH-1 words in the FIFO, it is almost_full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n\n           //If the FIFO is completely empty, but it is\n           // reporting FULL for some reason (like reset)\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=\n                C_FIFO_WR_DEPTH-2) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //FIFO is really not close to full, so change flag status.\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n           end //(tmp_wr_listsize == 0)\n\n         end else begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=\n              C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack       <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count     <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;\n\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //This write is CAUSING the FIFO to go full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is 2 from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == \n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits =  next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Still 2 from full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is not close to being full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <\n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //wr_rst_i==0\n   end // gen_fifo_w\n\n\n  /***************************************************************************\n   * Programmable FULL flags\n   ***************************************************************************/\n\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;\n\n   generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;\n   end else begin // STD\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;\n   end endgenerate\n\n   always @(posedge WR_CLK or posedge wr_rst_i) begin\n\n     if (wr_rst_i == 1'b1) begin\n       diff_pntr         <= 0;\n     end else begin\n       if (ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);\n       else if (!ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);\n    end\n  end\n\n\n   always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf\n\n     if (RST_FULL_FF & C_HAS_RST) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else begin\n\n       if (RST_FULL_GEN)\n         ideal_prog_full   <= #`TCQ 0;\n       //Single Programmable Full Constant Threshold\n       else if (C_PROG_FULL_TYPE == 1) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else\n             ideal_prog_full <= #`TCQ 0;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Constant Thresholds\n       end else if (C_PROG_FULL_TYPE == 2) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else if (diff_pntr < pf_thr_negate_val)\n             ideal_prog_full <= #`TCQ 0;\n           else\n             ideal_prog_full <= #`TCQ ideal_prog_full;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Single Programmable Full Threshold Input\n       end else if (C_PROG_FULL_TYPE == 3) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH)\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Threshold Inputs\n       end else if (C_PROG_FULL_TYPE == 4) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH_ASSERT)\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < PROG_FULL_THRESH_NEGATE)\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       end // C_PROG_FULL_TYPE\n\n     end //wr_rst_i==0\n   end //\n\n   \n   /**************************************************************************\n   * Read Domain Logic\n   **************************************************************************/\n\n\n   /*********************************************************\n    * Programmable EMPTY flags\n    *********************************************************/\n   //Determine the Assert and Negate thresholds for Programmable Empty\n\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd      = 0;\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe\n\n     if (rd_rst_i & C_HAS_RST) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else begin\n       if (ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;\n       else if (!ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr);\n       else\n         diff_pntr_rd       <=  #`TCQ diff_pntr_rd;\n  \n       if (C_PROG_EMPTY_TYPE == 1) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 2) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 3) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 4) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end  //C_PROG_EMPTY_TYPE\n     end\n   end // gen_pe\n\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;\n   end endgenerate // single_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;\n   end endgenerate // multiple_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;\n   end endgenerate // single_multiple_pe_thr_const\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp\n     if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n       rd_pntr            <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)\n       rd_pntr            <= #`TCQ 0;\n   end\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rd_rst_i & C_HAS_RST) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n     end else begin //rd_rst_i==0\n\n       rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 1\n       /*****************************************************************/\n       if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Reminder that FIFO is still empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end // if (tmp_rd_listsize <= 0)\n\n             //If the FIFO is one from empty, but it is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 1)\n\n             //If the FIFO is two from empty, and is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Fifo has two words, so is neither empty or almost empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 2)\n\n             //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid <= #`TCQ 1'b0;\n                 //Note that the FIFO is No Longer Empty or Almost Empty\n\n                 ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n               end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n             end // else: if(ideal_empty == 1'b1)\n\n           else //if (ideal_empty == 1'b0)\n             begin\n\n               //If the FIFO is completely full, and we are successfully reading from it\n               if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)\n\n               //If the FIFO is not close to being empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n               //If the FIFO is two from empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Fifo is not yet empty. It is going almost_empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n\n               //If the FIFO is one from empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Note that FIFO is GOING empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 1)\n\n\n               //If the FIFO is completely empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n                 begin\n                   //Do not change the contents of the FIFO\n\n                   //Do not acknowledge the read from empty FIFO\n                   ideal_valid        <= #`TCQ 1'b0;\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize <= 0)\n\n             end // if (ideal_empty == 1'b0)\n\n           end //(RD_EN == 1'b1)\n\n         else //if (RD_EN == 1'b0)\n           begin\n             //If user did not attempt a read, do not give an ack or err\n             ideal_valid          <= #`TCQ 1'b0;\n\n             ideal_rd_count       <= #`TCQ num_read_words_sized_i;\n\n           end // else: !if(RD_EN == 1'b1)\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 0\n       /*****************************************************************/\n       end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty, but it is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty, and is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Fifo has two words, so is neither empty or almost empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                         (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that the FIFO is No Longer Empty or Almost Empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n           end else begin\n\n             //If the FIFO is completely full, and we are successfully reading from it\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is not close to being empty\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                          (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Fifo is not yet empty. It is going almost_empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Note that FIFO is GOING empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is completely empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if (tmp_rd_listsize <= 0)\n\n           end // if (ideal_empty == 1'b0)\n\n         end else begin//(RD_EN == 1'b0)\n\n         \n           //If user did not attempt a read, do not give an ack or err\n           ideal_valid           <= #`TCQ 1'b0;\n           ideal_rd_count        <= #`TCQ num_read_words_sized_i;\n\n         end // else: !if(RD_EN == 1'b1)\n       end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //rd_rst_i==0\n   end //always gen_fifo_r_as\n\nendmodule // fifo_generator_v13_2_1_bhv_ver_as\n\n\n/*******************************************************************************\n * Declaration of Low Latency Asynchronous FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_1_beh_ver_ll_afifo\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_FIFO_TYPE                    = 0\n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   output reg  [C_DOUT_WIDTH-1:0]                DOUT = 0,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL\n  );\n\n  //-----------------------------------------------------------------------------\n  // Low Latency Asynchronous FIFO\n  //-----------------------------------------------------------------------------\n\n  // Memory which will be used to simulate a FIFO\n  reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n  integer i;\n  initial begin\n    for (i = 0; i < C_WR_DEPTH; i = i + 1)\n      memory[i] = 0;\n  end\n\n  reg  [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;\n  wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;\n  reg  [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;\n  reg                        ll_afifo_full    = 1'b0;\n  reg                        ll_afifo_empty   = 1'b1;\n  wire                       write_allow;\n  wire                       read_allow;\n\n  assign write_allow = WR_EN & ~ll_afifo_full;\n  assign read_allow  = RD_EN & ~ll_afifo_empty;\n\n  //-----------------------------------------------------------------------------\n  // Write Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      wr_pntr_ll_afifo   <= 0;\n    else if (write_allow)\n      wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Read Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      rd_pntr_ll_afifo_q   <= 0;\n    else\n      rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;\n  end\n  assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;\n  \n  //-----------------------------------------------------------------------------\n  // Fill the Memory\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK) begin\n    if (write_allow)\n      memory[wr_pntr_ll_afifo] <= #`TCQ DIN;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate DOUT\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK) begin\n      DOUT <= #`TCQ memory[rd_pntr_ll_afifo];\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate EMPTY\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      ll_afifo_empty   <= 1'b1;\n    else\n      ll_afifo_empty   <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | \n                           (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate FULL\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      ll_afifo_full   <= 1'b1;\n    else\n      ll_afifo_full   <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | \n                           (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));\n  end\n\n  always @* begin\n    FULL  <= ll_afifo_full;\n    EMPTY <= ll_afifo_empty;\n  end\n\nendmodule // fifo_generator_v13_2_1_beh_ver_ll_afifo\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_v13_2_1_bhv_ver_ss\n   \n  /**************************************************************************\n   * Declare user parameters and their defaults\n   *************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0 \n   )\n   \n  /**************************************************************************\n   * Declare Input and Output Ports\n   *************************************************************************/\n   (\n    //Inputs\n    input                                 SAFETY_CKT_WR_RST,\n    input                                 CLK,\n    input       [C_DIN_WIDTH-1:0]         DIN,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_ASSERT,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_NEGATE,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_ASSERT,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_NEGATE,\n    input                                 RD_EN,\n    input                                 RD_EN_USER,\n    input                                 USER_EMPTY_FB,\n    input                                 RST,\n    input                                 RST_FULL_GEN,\n    input                                 RST_FULL_FF,\n    input                                 SRST,\n    input                                 WR_EN,\n    input                                 INJECTDBITERR,\n    input                                 INJECTSBITERR,\n    input                                 WR_RST_BUSY,\n    input                                 RD_RST_BUSY,\n                                    \n    //Outputs                       \n    output                                ALMOST_EMPTY,\n    output                                ALMOST_FULL,\n    output reg   [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,\n    output       [C_DOUT_WIDTH-1:0]       DOUT,\n    output                                EMPTY,\n    output reg                            EMPTY_FB = 1'b1,\n    output                                FULL,\n    output                                OVERFLOW,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]    RD_DATA_COUNT,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]    WR_DATA_COUNT,\n    output                                PROG_EMPTY,\n    output                                PROG_FULL,\n    output                                VALID,\n    output                                UNDERFLOW,\n    output                                WR_ACK,\n    output                                SBITERR,\n    output                                DBITERR\n   );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;\n   wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n   localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; \n\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n   localparam  EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //localparam  EXTRA_WORDS_PE_PARAM  = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not \n   //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.\n   // Therefore, during SRST, all the FULL flags reset to 0.\n   localparam                      C_HAS_FAST_FIFO = 0;\n   localparam                      C_FIFO_WR_DEPTH = C_WR_DEPTH;\n   localparam                      C_FIFO_RD_DEPTH = C_RD_DEPTH;\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;\n   localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;\n   localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;\n   localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n  localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; \n  localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; \n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   \n   /**************************************************************************\n    * Internal Registers and wires\n    *************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire                           underflow_i;\n   wire                           valid_i;\n   wire                           valid_out;\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_reg = 1'b0;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n   wire                         srst_rrst_busy;\n\n\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]                      err_type           = 0;\n   reg [1:0]                      err_type_d1        = 0;\n   reg [1:0]                      err_type_both      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout         = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_d1      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_both      = 0;\n   wire [C_DOUT_WIDTH-1:0]        ideal_dout_out;\n   wire                           fwft_enabled;\n   reg                            ideal_wr_ack       = 0;\n   reg                            ideal_valid        = 0;\n   reg                            ideal_overflow     = C_OVERFLOW_LOW;\n   reg                            ideal_underflow    = C_UNDERFLOW_LOW;\n\n   reg                            full_i             = C_FULL_FLAGS_RST_VAL;\n   reg                            full_i_temp        = 0;\n   reg                            empty_i            = 1;\n   reg                            almost_full_i      = 0;\n   reg                            almost_empty_i     = 1;\n   reg                            prog_full_i        = 0;\n   reg                            prog_empty_i       = 1;\n   reg [C_WR_PNTR_WIDTH-1:0]      wr_pntr            = 0;\n   reg [C_RD_PNTR_WIDTH-1:0]      rd_pntr            = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg [C_RD_PNTR_WIDTH-1:0]      diff_count         = 0;\n\n   reg                            write_allow_q      = 0;\n   reg                            read_allow_q       = 0;\n   reg                            valid_d1           = 0;\n   reg                            valid_both           = 0;\n   reg                            valid_d2           = 0;\n   wire                           rst_i;\n   wire                           srst_i;\n\n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]         dout_reset_val = 0;\n\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n\n\n\n   /****************************************************************************\n    * Function Declarations\n    ***************************************************************************/\n\n   /****************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***************************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin\n        case (def_data[7:0])\n          8'b00000000 : begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default : begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1) begin\n          if ((index*4)+j < C_DOUT_WIDTH) begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   //reg         valid_d1     = 0;\n   \n   \n   //user specified value for reseting the size of the fifo\n   //reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n\n\n /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n     if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n\n     end\n  endtask\n\n\n   \n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_dout_both    = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_both         = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n\n   end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the\n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n   wire CLK;\n   wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;\n   wire RD_EN;\n   wire RST;\n   wire WR_EN;\n    */\n\n  // Assign ALMOST_EPMTY\n  generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae\n    assign ALMOST_EMPTY = almost_empty_i;\n  end else begin : gnae\n    assign ALMOST_EMPTY = 0;\n  end endgenerate // gae\n\n  // Assign ALMOST_FULL\n  generate if (C_HAS_ALMOST_FULL==1) begin : gaf\n    assign ALMOST_FULL  = almost_full_i;\n  end else begin : gnaf\n    assign ALMOST_FULL  = 0;\n  end endgenerate // gaf\n\n   // Dout may change behavior based on latency\n  localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?\n                         ideal_dout_d1: ideal_dout; \n  assign DOUT = ideal_dout_out;\n\n  // Assign SBITERR and DBITERR based on latency \n  assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[0]: err_type[0]; \n  assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[1]: err_type[1]; \n\n  assign EMPTY         = empty_i;\n  assign FULL          = full_i;\n  //saftey_ckt with one register\n\n  generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)\n          begin\n          if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n              valid_d1 <= #`TCQ 1'b0;\n          end\n          else begin\n               ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n               valid_d1 <= #`TCQ valid_i;\n          end\n          end\n          \n           always@(posedge rst_delayed_sft2 or posedge CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n              end\n           else if (srst_rrst_busy == 1'b1) begin\n                   if (C_USE_DOUT_RST == 1'b1) begin\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   end\n           end else if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                end\n           end   \n      end //if \n      endgenerate   \n\n//safety ckt with both registers\n\ngenerate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK) begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            valid_d1 <= #`TCQ 1'b0;\n          end else begin\n            ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n            fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n            valid_both <= #`TCQ valid_i;\n            valid_d1 <= #`TCQ valid_both;\n          end\n        end\n\n        always@(posedge rst_delayed_sft2 or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                  ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else if (srst_rrst_busy == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else begin \n            if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n            end\n          end\n        end\n      end //if \n      endgenerate    \n \n \n  //Overflow may be active-low\n  generate if (C_HAS_OVERFLOW==1) begin : gof\n    assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n  end else begin : gnof\n    assign OVERFLOW = 0;\n  end endgenerate // gof\n\n  assign PROG_EMPTY    = prog_empty_i;\n  assign PROG_FULL     = prog_full_i;\n\n   //Valid may change behavior based on latency or active-low\n  generate if (C_HAS_VALID==1) begin : gvalid\n    assign valid_i       = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;\n    assign valid_out     = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?\n                            valid_d1 : valid_i; \n    assign VALID         = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n  end else begin : gnvalid\n    assign VALID         = 0;\n  end endgenerate // gvalid\n\n  //Trim data count differently depending on set widths\n  generate if (C_HAS_DATA_COUNT == 1) begin : gdc\n    always @* begin\n      diff_count <= wr_pntr - rd_pntr;\n      if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin\n        DATA_COUNT[C_RD_PNTR_WIDTH-1:0]  <= diff_count;\n        DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; \n      end else begin\n        DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];\n      end\n    end\n//  end else begin : gndc\n//    always @* DATA_COUNT <= 0;\n  end endgenerate // gdc\n\n  //Underflow may change behavior based on latency or active-low\n  generate if (C_HAS_UNDERFLOW==1) begin : guf\n    assign underflow_i   = ideal_underflow;\n    assign UNDERFLOW     = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n  end else begin : gnuf\n    assign UNDERFLOW     = 0;\n  end endgenerate // guf\n \n\n  //Write acknowledge may be active low \n  generate if (C_HAS_WR_ACK==1) begin : gwr_ack\n    assign WR_ACK        = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n  end else begin : gnwr_ack\n    assign WR_ACK        = 0;\n  end endgenerate // gwr_ack\n\n\n  /*****************************************************************************\n   * Internal reset logic \n   ****************************************************************************/\n  assign srst_i        = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;\n  assign rst_i            = C_HAS_RST ? RST : 0;\n  assign srst_wrst_busy   = srst_i;\n  assign srst_rrst_busy   = srst_i;\n\n   /**************************************************************************\n    * Assorted registers for delayed versions of signals\n    **************************************************************************/\n   //Capture delayed version of valid\n   generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20\n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1 <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n           end else begin\n              valid_d1 <= #`TCQ valid_i;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n     end \n   endgenerate // blockVL20\n\n  generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin \n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1   <= 1'b0;\n           valid_both <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n              valid_both <= #`TCQ 1'b0;\n              \n           end else begin\n              valid_both <= #`TCQ valid_i;\n               valid_d1 <= #`TCQ valid_both;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n  end\n endgenerate // blockVL20\n\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge CLK or posedge rst_i) begin\n         if (rst_i) begin\n           stage1_valid     <= #`TCQ 0;\n           stage2_valid     <= #`TCQ 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n\n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc\n       assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc\n       assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n   \n   //reg ram_rd_en_d1 = 1'b0;\n   //Capture delayed version of dout\n   generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         ram_rd_en_d1 <= #`TCQ 1'b0;\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n        end\n      end else begin\n         ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n         if (srst_rrst_busy) begin\n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            // Reset err_type only if ECC is not selected\n            if (C_USE_ECC == 0) begin\n               err_type_d1   <= #`TCQ 0;\n               err_type_both <= #`TCQ 0;\n            end\n            // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n            if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n            end \n         if (C_USE_DOUT_RST == 1) begin\n           // @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         end else begin\n            if (ram_rd_en_d1 ) begin\n            ideal_dout_d1 <= #`TCQ ideal_dout;\n            err_type_d1   <= #`TCQ err_type;\n            end\n         end\n      end    \n   end   // always\nend\nendgenerate \n\n//no safety ckt with both registers\n generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n          ram_rd_en_d1 <= #`TCQ 1'b0;\n          fab_rd_en_d1 <= #`TCQ 1'b0;\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val; \n            \n      end\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val;\n       end\n      end else begin\n         if (srst_rrst_busy) begin \n           ram_rd_en_d1 <= #`TCQ 1'b0;\n           fab_rd_en_d1 <= #`TCQ 1'b0;\n           // Reset err_type only if ECC is not selected\n           if (C_USE_ECC == 0) begin\n              err_type_d1   <= #`TCQ 0;\n              err_type_both <= #`TCQ 0;\n           end\n           // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n           if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n              ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end \n           if (C_USE_DOUT_RST == 1) begin\n             ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end\n         end else begin\n           ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n           fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);\n           if (ram_rd_en_d1 ) begin\n             ideal_dout_both <= #`TCQ ideal_dout;\n             err_type_both   <= #`TCQ err_type;\n           end\n           if (fab_rd_en_d1 ) begin\n             ideal_dout_d1 <= #`TCQ ideal_dout_both;\n             err_type_d1   <= #`TCQ err_type_both;\n           end\n         end\n      end    \n   end   // always\nend\nendgenerate \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n     always @(posedge CLK) begin\n       ideal_overflow    <= #`TCQ WR_EN & full_i;\n     end\n   end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n     always @(posedge CLK) begin\n       //ideal_overflow    <= #`TCQ WR_EN & (rst_i | full_i);\n       ideal_overflow    <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);\n     end\n   end endgenerate // blockOF20\n \n   generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n     always @(posedge CLK) begin\n       ideal_underflow   <= #`TCQ empty_i & RD_EN;\n     end\n   end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n     always @(posedge CLK) begin\n       //ideal_underflow   <= #`TCQ (rst_i | empty_i) & RD_EN;\n       ideal_underflow   <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;\n     end\n   end endgenerate // blockUF20\n\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n\n  /*************************************************************************\n   * Write and Read Logic  \n   ************************************************************************/\n   wire              write_allow;\n   wire              read_allow;\n   wire              read_allow_dc;\n   wire              write_only;\n   wire              read_only;\n   //wire              write_only_q;\n   reg              write_only_q;\n   //wire              read_only_q;\n   reg              read_only_q;\n   reg              full_reg;\n   reg              rst_full_ff_reg1;\n   reg              rst_full_ff_reg2;\n   wire              ram_full_comb;\n   wire              carry;\n   \n   assign write_allow  = WR_EN & ~full_i;\n   assign read_allow   = RD_EN & ~empty_i;\n   assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;\n   //assign write_only   = write_allow & ~read_allow;\n   //assign write_only_q = write_allow_q;\n   //assign read_only    = read_allow    & ~write_allow;\n   //assign read_only_q  = read_allow_q ;\n   wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;\n   wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;\n   wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;\n\n   assign diff_pntr_pe_max = DIFF_MAX_RD;\n   assign diff_pntr_max = DIFF_MAX_WR;\n\n\n\n   generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym\n    assign write_only   = write_allow & ~read_allow;\n    assign read_only    = read_allow    & ~write_allow;\n    end endgenerate\n    generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd\n     assign read_only   = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;\n     assign write_only    = write_allow    & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n    generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr\n     assign read_only   = read_allow & ~(write_allow  & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n     assign write_only    = write_allow &  &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;\n    end endgenerate\n\n\n   //-----------------------------------------------------------------------------\n   // Write and Read pointer generation\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       wr_pntr         <= 0;\n       rd_pntr         <= 0;\n     end else begin\n       if (srst_i) begin\n         wr_pntr       <= #`TCQ 0;\n         rd_pntr       <= #`TCQ 0;\n       end else begin\n         if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;\n         if (read_allow)  rd_pntr <= #`TCQ rd_pntr + 1;\n       end\n     end\n   end\n\n   generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout\n   always @(posedge CLK) begin\n     if (write_allow) begin\n       if (ENABLE_ERR_INJECTION == 1)\n         memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};\n       else\n         memory[wr_pntr] <= #`TCQ DIN;\n     end\n   end\n\n   reg  [C_DATA_WIDTH-1:0] dout_tmp_q;\n   reg [C_DATA_WIDTH-1:0] dout_tmp = 0;\n   reg  [C_DATA_WIDTH-1:0] dout_tmp1 = 0;\n   always @(posedge CLK) begin\n     dout_tmp_q <= #`TCQ ideal_dout;\n   end\n\n\n\n     always @* begin\n       if (read_allow)\n         ideal_dout <= memory[rd_pntr];\n       else\n         ideal_dout <= dout_tmp_q;\n     end\n   end endgenerate // gll_dm_dout\n\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   assign ram_rd_en        = RD_EN & !EMPTY;\n\n   //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   generate if (C_FIFO_TYPE != 2) begin : gnll_din\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i == 1'b1) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n\n     end else begin //rst_i==0\n     if (srst_wrst_busy) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n     end else begin//srst_i=0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n         end else begin\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error  \n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           //end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //srst_i==0\n     end //wr_rst_i==0\n   end // gen_fifo_w\n    end endgenerate\n\n   generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout\n     always @(posedge CLK) begin\n       if (rst_i || srst_rrst_busy) begin\n         if (C_USE_DOUT_RST == 1) begin\n           ideal_dout <= #`TCQ dout_reset_val;\n           ideal_dout_both <= #`TCQ dout_reset_val;\n         end\n       end\n     end\n    end endgenerate\n\n\n\n\n   generate if (C_FIFO_TYPE != 2) begin : gnll_dout\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_r\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n\n     end else begin //rd_rst_i==0\n     if (srst_rrst_busy) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets synchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= #`TCQ 0;\n         err_type_both    <= #`TCQ 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n      end //srst_i\n      else begin\n\n       //rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n         if (RD_EN == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end \n           else \n             begin\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n         end\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //s_rst_i==0\n     end //rd_rst_i==0\n   end //always\n  end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate diff_pntr for PROG_FULL generation\n   // Generate diff_pntr_pe for PROG_EMPTY generation\n   //-----------------------------------------------------------------------------\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         write_only_q   <= 1'b0;\n         read_only_q    <= 1'b0;\n         diff_pntr_reg1       <= 0;\n         diff_pntr_pe_reg1    <= 0;\n         diff_pntr_reg2       <= 0;\n         diff_pntr_pe_reg2    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_rrst_busy) begin\n           read_only_q  <= #`TCQ 1'b0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n           diff_pntr_pe_reg2  <= #`TCQ 0;\n          end\n          if (srst_wrst_busy) begin\n           write_only_q <= #`TCQ 1'b0;\n           diff_pntr_reg1     <= #`TCQ 0;\n           diff_pntr_reg2     <= #`TCQ 0;\n          end\n         end else begin\n           write_only_q <= #`TCQ write_only;\n           read_only_q  <= #`TCQ read_only;\n           diff_pntr_reg2  <= #`TCQ diff_pntr_reg1;\n           diff_pntr_pe_reg2  <= #`TCQ diff_pntr_pe_reg1;\n\n           // Add 1 to the difference pointer value when only write happens.\n           if (write_only)  \n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;\n           else\n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;\n\n           // Add 1 to the difference pointer value when write or both write & read or no write & read happen.\n           if (read_only)  \n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;\n           else\n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;\n         end\n       end\n     end\n   assign diff_pntr_pe = diff_pntr_pe_reg1;\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow\n\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym\n    assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};\n    assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         diff_pntr_pe_asym    <= 0;\n         diff_pntr_reg1       <= 0;\n         full_reg             <= 0;\n         rst_full_ff_reg1     <= 1;\n         rst_full_ff_reg2     <= 1;\n         diff_pntr_pe_reg1    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_wrst_busy)\n           diff_pntr_reg1     <= #`TCQ 0;\n          if (srst_rrst_busy)\n           full_reg             <=  #`TCQ 0;\n           rst_full_ff_reg1     <=  #`TCQ 1;\n           rst_full_ff_reg2     <=  #`TCQ 1;\n           diff_pntr_pe_asym    <=  #`TCQ 0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n         end else begin\n             diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;\n             full_reg          <= #`TCQ full_i;\n             rst_full_ff_reg1  <=  #`TCQ RST_FULL_FF;\n             rst_full_ff_reg2  <=  #`TCQ rst_full_ff_reg1;\n           if (~full_i) begin  \n             diff_pntr_reg1 <=  #`TCQ wr_pntr - adj_rd_pntr_wr;\n          end\n         end\n       end\n     end\n   assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));\n   assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow_asym\n\n\n   //-----------------------------------------------------------------------------\n   // Generate FULL flag\n   //-----------------------------------------------------------------------------\n   wire                 comp0;\n   wire                 comp1;\n   wire                 going_full;\n   wire                 leaving_full;\n \n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin :  gpad \t\n    assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;\n    assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin :  gtrim \n    assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n  end endgenerate\n\n   assign comp1         = (adj_rd_pntr_wr == (wr_pntr + 1'b1));\n   assign comp0         = (adj_rd_pntr_wr == wr_pntr);\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp\n     assign going_full    = (comp1 & write_allow & ~read_allow);\n     assign leaving_full  = (comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym\n      assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp \n      assign going_full = (comp1 & write_allow & ~read_allow);\n      assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n\n   assign ram_full_comb = going_full | (~leaving_full & full_i);\n\n   generate if (C_HAS_RST == 1) begin : grst_full\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF & C_HAS_RST)\n         full_i   <= C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_SRST == 1) begin : gsrst_full\n     always @(posedge CLK) begin\n       if (srst_wrst_busy)\n         full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_full\n     always @(posedge CLK) begin\n         full_i   <= #`TCQ ram_full_comb;\n     end\n   end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate EMPTY flag\n   //-----------------------------------------------------------------------------\n   wire                 ecomp0;\n   wire                 ecomp1;\n   wire                 going_empty;\n   wire                 leaving_empty;\n   wire                 ram_empty_comb;\n\n  \n generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin :  pad \t\n    assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n    assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin :  trim \n    assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n  end endgenerate\n\n   assign ecomp1         = (adj_wr_pntr_rd == (rd_pntr + 1'b1));\n   assign ecomp0         = (adj_wr_pntr_rd == rd_pntr);\n\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp\n     assign going_empty    = (ecomp1 & ~write_allow & read_allow);\n     assign leaving_empty  = (ecomp0 & write_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp\n      assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp \n      assign going_empty = (ecomp1 & ~write_allow & read_allow);\n      assign leaving_empty =(ecomp0 & write_allow);\n    end endgenerate\n\n\n\n    assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);\n\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       empty_i  <= 1'b1;\n     else if (srst_rrst_busy)\n       empty_i  <= #`TCQ 1'b1;\n     else\n       empty_i  <= #`TCQ ram_empty_comb;\n    end\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       EMPTY_FB     <= 1'b1;\n     end else begin\n       if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))\n         EMPTY_FB   <= #`TCQ 1'b1;\n       else\n         EMPTY_FB   <= #`TCQ ram_empty_comb;\n     end\n   end // always\n\n   //-----------------------------------------------------------------------------\n   // Generate Read and write data counts for asymmetic common clock\n   //-----------------------------------------------------------------------------\n\n    reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; \n    wire [C_GRTR_PNTR_WIDTH :0] ratio; \n    wire decr_by_one;\n    wire incr_by_ratio;\n    wire incr_by_one;\n    wire decr_by_ratio;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n\n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr \n      assign ratio         = C_DEPTH_RATIO_RD;\n      assign decr_by_one   = (IS_FWFT == 1)? read_allow_dc : read_allow;\n      assign incr_by_ratio = write_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (decr_by_one) begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc - 1;\n           else\n\t    count_dc <= #`TCQ count_dc - 1  + ratio ;\n\t end\n\t else begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc + ratio ;\n\tend\n       end\n       end\n\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n\n    end endgenerate\n\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd \n      assign ratio         = C_DEPTH_RATIO_WR;\n      assign incr_by_one   = write_allow;\n      assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (incr_by_one) begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc + 1;\n           else\n\t    count_dc <= #`TCQ count_dc + 1  - ratio ;\n\t end\n\t else begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc - ratio ;\n\tend\n       end\n       end\n\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n\n    end endgenerate\n\n\n\n\n\n\n   //-----------------------------------------------------------------------------\n   // Generate WR_ACK flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_wr_ack  <= 1'b0;\n     else if (srst_wrst_busy)\n       ideal_wr_ack  <= #`TCQ 1'b0;\n     else if (WR_EN & ~full_i)\n       ideal_wr_ack  <= #`TCQ 1'b1;\n     else\n       ideal_wr_ack  <= #`TCQ 1'b0;\n    end\n\n   //-----------------------------------------------------------------------------\n   // Generate VALID flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_valid  <= 1'b0;\n     else if (srst_rrst_busy)\n       ideal_valid  <= #`TCQ 1'b0;\n     else if (RD_EN & ~empty_i)\n       ideal_valid  <= #`TCQ 1'b1;\n     else\n       ideal_valid  <= #`TCQ 1'b0;\n    end\n\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_FULL flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss\n\n     wire                 fcomp2;\n     wire                 going_afull;\n     wire                 leaving_afull;\n     wire                 ram_afull_comb;\n\n\n   assign fcomp2         = (adj_rd_pntr_wr == (wr_pntr + 2'h2));\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp\n     assign going_afull    = (fcomp2 & write_allow & ~read_allow);\n     assign leaving_afull  = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym\n      assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp \n      assign going_afull = (fcomp2 & write_allow & ~read_allow);\n      assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n     assign ram_afull_comb  = going_afull | (~leaving_afull & almost_full_i);\n\n\n    generate if (C_HAS_RST == 1) begin : grst_afull\n      always @(posedge CLK or posedge RST_FULL_FF) begin\n        if (RST_FULL_FF & C_HAS_RST)\n          almost_full_i   <= C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_SRST == 1) begin : gsrst_afull\n      always @(posedge CLK) begin\n        if (srst_wrst_busy)\n          almost_full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_afull\n      always @(posedge CLK) begin\n          almost_full_i   <= #`TCQ ram_afull_comb;\n      end\n    end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_EMPTY flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss\n\n     wire                 ecomp2;\n     wire                 going_aempty;\n     wire                 leaving_aempty;\n     wire                 ram_aempty_comb;\n      \n     assign ecomp2          = (adj_wr_pntr_rd == (rd_pntr + 2'h2));\n   \n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp\n     assign going_aempty    = (ecomp2 & ~write_allow & read_allow);\n     assign leaving_aempty  = (ecomp1 & write_allow & ~read_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp\n      assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp \n      assign going_aempty = (ecomp2 & ~write_allow & read_allow);\n      assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);\n    end endgenerate\n\n\n     assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);\n\n     always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         almost_empty_i  <= 1'b1;\n       else if (srst_rrst_busy)\n         almost_empty_i  <= #`TCQ 1'b1;\n       else\n         almost_empty_i  <= #`TCQ ram_aempty_comb;\n      end\n  // end endgenerate // gae_ss\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL\n   //-----------------------------------------------------------------------------\n\n   localparam  C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT \n                                  C_PROG_FULL_THRESH_ASSERT_VAL; // STD\n   localparam  C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT\n                                  C_PROG_FULL_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;   \n   generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin \n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n          prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr>= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  ((diff_pntr) < C_PF_ASSERT_VAL )\n        prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate // single_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr >= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n       else if  (diff_pntr < C_PF_NEGATE_VAL)\n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate //multiple_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT\n                                               PROG_FULL_THRESH; // STD\n   generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input\n\n     always @(posedge CLK or posedge RST_FULL_FF) begin//0\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin //1\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin//2 \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin//3\n           if (diff_pntr > pf3_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if (diff_pntr == pf3_assert_val) begin//4\n             if (read_only_q)\n               prog_full_i <= #`TCQ 1'b0;\n             else\n               prog_full_i <= #`TCQ 1'b1;\n           end else//4\n             prog_full_i <= #`TCQ 1'b0;\n         end else//3\n           prog_full_i <= #`TCQ prog_full_i;\n       end //2\n       else begin//5\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin//6 \n        if (diff_pntr >= pf3_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  (diff_pntr < pf3_assert_val) begin//7\n         prog_full_i <= #`TCQ 1'b0;\n       end//7\n       end//6\n      else\n           prog_full_i <= #`TCQ prog_full_i;\n       end//5\n     end//1\n     end//0\n   end endgenerate //single_pf_input\n  \n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_ASSERT; // STD\n   wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_NEGATE; // STD\n\n   generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin\n           if (diff_pntr >= pf_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if ((diff_pntr == pf_negate_val && read_only_q) ||\n                  diff_pntr < pf_negate_val)\n             prog_full_i <= #`TCQ 1'b0;\n           else\n             prog_full_i <= #`TCQ prog_full_i;\n         end else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin \n        if (diff_pntr >= pf_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n       else if (diff_pntr < pf_negate_val) \n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n\n     end\n   end\n   end endgenerate //multiple_pf_inputs\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY\n   //-----------------------------------------------------------------------------\n   localparam  C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD\n   localparam  C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i) \n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy) \n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL)\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > C_PE_ASSERT_VAL)\n         prog_empty_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n     end\n     end\n   end endgenerate // single_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > C_PE_NEGATE_VAL) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n\n     end\n\n     end\n   end endgenerate //multiple_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH -2) : // FWFT\n                                                PROG_EMPTY_THRESH; // STD\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe < pe3_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (diff_pntr_pe == pe3_assert_val) begin\n             if (write_only_q)\n               prog_empty_i <= #`TCQ 1'b0;\n             else\n               prog_empty_i <= #`TCQ 1'b1;\n           end else\n             prog_empty_i <= #`TCQ 1'b0;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe3_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > pe3_assert_val)\n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n\n     end\n   end endgenerate // single_pe_input\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_ASSERT; // STD\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_NEGATE; // STD\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n      else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe <= pe4_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || \n                     (diff_pntr_pe > pe4_negate_val)) begin\n             prog_empty_i <= #`TCQ 1'b0;\n           end else\n             prog_empty_i <= #`TCQ prog_empty_i;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe4_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > pe4_negate_val) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n     end\n   end endgenerate // multiple_pe_inputs\n\nendmodule // fifo_generator_v13_2_1_bhv_ver_ss\n\n\n\n/**************************************************************************\n * First-Word Fall-Through module (preload 0)\n **************************************************************************/\nmodule fifo_generator_v13_2_1_bhv_ver_preload0\n  #(\n    parameter  C_DOUT_RST_VAL            = \"\",\n    parameter  C_DOUT_WIDTH              = 8,\n    parameter  C_HAS_RST                 = 0,\n    parameter  C_ENABLE_RST_SYNC         = 0,\n    parameter  C_HAS_SRST                = 0,\n    parameter  C_USE_EMBEDDED_REG        = 0,\n    parameter  C_EN_SAFETY_CKT           = 0, \n    parameter  C_USE_DOUT_RST            = 0,\n    parameter  C_USE_ECC                 = 0,\n    parameter  C_USERVALID_LOW           = 0,\n    parameter  C_USERUNDERFLOW_LOW       = 0,\n    parameter  C_MEMORY_TYPE             = 0,\n    parameter  C_FIFO_TYPE               = 0\n  )\n  (\n    //Inputs\n    input                          SAFETY_CKT_RD_RST,\n    input                          RD_CLK,\n    input                          RD_RST,\n    input                          SRST,\n    input                          WR_RST_BUSY,\n    input                          RD_RST_BUSY,\n    input                          RD_EN,\n    input                          FIFOEMPTY,\n    input       [C_DOUT_WIDTH-1:0] FIFODATA,\n    input                          FIFOSBITERR,\n    input                          FIFODBITERR,\n   \n    //Outputs\n    output reg  [C_DOUT_WIDTH-1:0] USERDATA,\n    output                         USERVALID,\n    output                         USERUNDERFLOW,\n    output                         USEREMPTY,\n    output                         USERALMOSTEMPTY,\n    output                         RAMVALID,\n    output                         FIFORDEN,\n    output reg                     USERSBITERR,\n    output reg                     USERDBITERR,\n    output reg                     STAGE2_REG_EN,\n    output                         fab_read_data_valid_i_o,\n    output                         read_data_valid_i_o,\n    output                         ram_valid_i_o,\n    output      [1:0]              VALID_STAGES \n  );\n //Internal signals\n wire                      preloadstage1;\n wire                      preloadstage2;\n reg                       ram_valid_i;\n reg                       fab_valid;\n reg                       read_data_valid_i;\n reg                       fab_read_data_valid_i;\n reg                       fab_read_data_valid_i_1;\n reg                       ram_valid_i_d;\n reg                       read_data_valid_i_d;\n reg                       fab_read_data_valid_i_d;\n wire                      ram_regout_en;\n reg                       ram_regout_en_d1;\n reg                       ram_regout_en_d2;\n wire                      fab_regout_en;\n wire                      ram_rd_en;\n reg                       empty_i        = 1'b1;\n reg                       empty_sckt     = 1'b1;\n reg                       sckt_rrst_q    = 1'b0;\n reg                       sckt_rrst_done = 1'b0;\n reg                       empty_q        = 1'b1;\n reg                       rd_en_q        = 1'b0;\n reg                       almost_empty_i = 1'b1;\n reg                       almost_empty_q = 1'b1;\n wire                      rd_rst_i;\n wire                      srst_i;\n reg  [C_DOUT_WIDTH-1:0]   userdata_both;\n wire                      uservalid_both;\n wire                      uservalid_one;\n reg                       user_sbiterr_both = 1'b0;\n reg                       user_dbiterr_both = 1'b0;\n  \nassign ram_valid_i_o = ram_valid_i;\nassign read_data_valid_i_o = read_data_valid_i;\nassign fab_read_data_valid_i_o = fab_read_data_valid_i; \n\n\n\n/*************************************************************************\n* FUNCTIONS\n*************************************************************************/\n\n   /*************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***********************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n   \n   //*************************************************************************\n   //  Set power-on states for regs\n   //*************************************************************************\n   initial begin\n      ram_valid_i       = 1'b0;\n      fab_valid         = 1'b0;\n      read_data_valid_i = 1'b0;\n      fab_read_data_valid_i = 1'b0;\n      fab_read_data_valid_i_1 = 1'b0;\n      USERDATA          = hexstr_conv(C_DOUT_RST_VAL);\n      userdata_both          = hexstr_conv(C_DOUT_RST_VAL);\n      USERSBITERR       = 1'b0;\n      USERDBITERR       = 1'b0;\n      user_sbiterr_both = 1'b0;\n      user_dbiterr_both = 1'b0;\n   end //initial\n\n   //***************************************************************************\n   //  connect up optional reset\n   //***************************************************************************\n   assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;\n   assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;\n\n   reg  sckt_rd_rst_fwft = 1'b0;\n   reg  fwft_rst_done_i  = 1'b0;\n   wire fwft_rst_done;\n   assign fwft_rst_done = 1'b1;//C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;\n   always @ (posedge RD_CLK) begin\n     sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;\n   end\n\n   always @ (posedge rd_rst_i or posedge RD_CLK) begin\n     if (rd_rst_i)\n       fwft_rst_done_i  <= 1'b0;\n     else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)\n       fwft_rst_done_i  <= #`TCQ 1'b1;\n   end\n\n   localparam INVALID             = 0;\n   localparam STAGE1_VALID        = 2;\n   localparam STAGE2_VALID        = 1;\n   localparam BOTH_STAGES_VALID   = 3;\n\n   reg  [1:0] curr_fwft_state = INVALID;\n   reg  [1:0] next_fwft_state = INVALID;\n\n\ngenerate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin\n         always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n \n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n     \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n    \n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = preloadstage2;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;\n   end\nendgenerate // gnll_fifo\n\n   reg curr_state         = 0;\n   reg next_state         = 0;\n   reg leaving_empty_fwft = 0;\n   reg going_empty_fwft   = 0;\n   reg empty_i_q          = 0;\n   reg ram_rd_en_fwft     = 0;\n   generate if (C_FIFO_TYPE == 2) begin : gll_fifo\n     always @* begin // FSM fo FWFT\n       case (curr_state)\n         1'b0: begin\n           if (~FIFOEMPTY)\n             next_state <= 1'b1;\n           else\n             next_state <= 1'b0;\n           end\n         1'b1: begin\n           if (FIFOEMPTY && RD_EN)\n             next_state <= 1'b0;\n           else\n             next_state <= 1'b1;\n           end\n         default: next_state <= 1'b0;\n       endcase\n     end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_i       <= 1'b1;\n           empty_i_q     <= 1'b1;\n           ram_valid_i   <= 1'b0;\n        end else if (srst_i) begin\n           empty_i       <= #`TCQ 1'b1;\n           empty_i_q     <= #`TCQ 1'b1;\n           ram_valid_i   <= #`TCQ 1'b0;\n        end else begin\n           empty_i       <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);\n           empty_i_q     <= #`TCQ FIFOEMPTY;\n           ram_valid_i   <= #`TCQ next_state;\n        end\n     end //always\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n           curr_state    <= 1'b0;\n        end else if (srst_i) begin\n           curr_state    <= #`TCQ 1'b0;\n        end else begin\n           curr_state    <= #`TCQ next_state;\n        end\n     end //always\n\n     wire                  fe_of_empty; \n     assign fe_of_empty   = empty_i_q & ~FIFOEMPTY;\n\n     always @* begin // Finding leaving empty\n       case (curr_state)\n         1'b0:    leaving_empty_fwft <= fe_of_empty;\n         1'b1:    leaving_empty_fwft <= 1'b1;\n         default: leaving_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Finding going empty\n       case (curr_state)\n         1'b1:    going_empty_fwft <= FIFOEMPTY & RD_EN;\n         default: going_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Generating FWFT rd_en\n       case (curr_state)\n         1'b0:    ram_rd_en_fwft <= ~FIFOEMPTY;\n         1'b1:    ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;\n         default: ram_rd_en_fwft <= 1'b0;\n       endcase\n     end\n\n     assign ram_regout_en = ram_rd_en_fwft;\n     //assign ram_regout_en_d1 = ram_rd_en_fwft;\n     //assign ram_regout_en_d2 = ram_rd_en_fwft;\n     assign ram_rd_en     = ram_rd_en_fwft;\n   end endgenerate // gll_fifo\n\n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false.\n   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n   generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           ram_valid_i     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              ram_valid_i     <= #`TCQ 1'b0;\n           end else begin\n              if (ram_rd_en == 1'b1) begin\n                 ram_valid_i   <= #`TCQ 1'b1;\n              end else begin\n                 if (ram_regout_en == 1'b1)\n                   ram_valid_i <= #`TCQ 1'b0;\n                 else\n                   ram_valid_i <= #`TCQ ram_valid_i;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_ram_valid\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n  \n generate if(C_USE_EMBEDDED_REG < 3) begin\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else\n        read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);\n   end //always\nend \nendgenerate\n\n   \n   \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n generate if ( C_USE_EMBEDDED_REG < 3) begin\n  always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin         // asynchronous reset (active high)\n             almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ FIFOEMPTY;\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n   \n   \n     \n  // BRAM resets synchronously\n generate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin\n   always @ ( posedge rd_rst_i)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n           @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n             USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end  else if (fwft_rst_done) begin\n            if (ram_regout_en) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end\n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n//safety ckt with one register\ngenerate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n            @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n        end\n     end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n          //@(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end \n       end\n        else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n            //  @(posedge RD_CLK)\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end else if (fwft_rst_done) begin\n            if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end          \n          end\n        end\n       end //always\n  end //if\nendgenerate\n\n\ngenerate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin\n         \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d1 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d1 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d1 <= #`TCQ ram_regout_en;\n                 end\n            end //always\n   //  assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));\n       assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d2 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d2 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;\n                 end\n            end //always\n\n    \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n     always @ (posedge RD_CLK) begin\n        ram_valid_i_d <= #`TCQ ram_valid_i;\n        read_data_valid_i_d <= #`TCQ read_data_valid_i;\n        fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;\n\n     end\n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n    \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;\n   end\n   endgenerate // gnll_fifo\n\n   \n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n     generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid\n\n     \n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           fab_valid     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              fab_valid    <= #`TCQ 1'b0;\n           end else begin\n              if (ram_regout_en == 1'b1) begin\n                 fab_valid  <= #`TCQ 1'b1;\n              end else begin\n                 if (fab_regout_en == 1'b1)\n                   fab_valid <= #`TCQ 1'b0;\n                 else\n                   fab_valid <= #`TCQ fab_valid;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_fab_valid\n\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n    generate if(C_USE_EMBEDDED_REG == 3) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else begin\n        if (ram_regout_en == 1'b1) begin\n          read_data_valid_i <= #`TCQ 1'b1;\n        end else begin\n         if (fab_regout_en == 1'b1)\n          read_data_valid_i <= #`TCQ 1'b0;\n        else\n          read_data_valid_i <= #`TCQ read_data_valid_i;\n        end \n      end \n   end //always\nend\nendgenerate\n\n//generate if(C_USE_EMBEDDED_REG == 3) begin\n//   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n//      if (rd_rst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//      else if (srst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//\n//      if (ram_regout_en == 1'b1) begin\n//        fab_read_data_valid_i <= #`TCQ 1'b0;\n//      end else begin\n//       if (fab_regout_en == 1'b1)\n//        fab_read_data_valid_i <= #`TCQ 1'b1;\n//      else\n//        fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;\n//      end \n//   end //always\n//end\n//endgenerate\n\n     generate if(C_USE_EMBEDDED_REG == 3 ) begin \n    always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid\n      if (rd_rst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else \n        fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);\n   end //always\nend\nendgenerate\n \nalways @ (posedge RD_CLK ) begin : proc_del1\n             begin\n                 fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;\n              end\n            end //always\n \n \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty_both\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n   reg FIFOEMPTY_1;\n   generate if (C_USE_EMBEDDED_REG == 3 ) begin\n    always @(posedge RD_CLK) begin\n            FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;\n           end\n    end\nendgenerate\n    generate if (C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n   begin\n      if (rd_rst_i) begin         // asynchronous reset (active high)\n           almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ (~ram_valid_i);\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_sckt <= #`TCQ 1'b1;\n           sckt_rrst_q <= #`TCQ 1'b0;\n           sckt_rrst_done <= #`TCQ 1'b0;\n        end else begin\n           sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;\n           if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin\n              sckt_rrst_done <= #`TCQ 1'b1;\n           end else if (sckt_rrst_done) begin\n              // rising clock edge\n              empty_sckt <= #`TCQ 1'b0;\n           end\n        end\n     end //always\n   \n   \n//   assign USEREMPTY       = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;\n   assign USEREMPTY       = empty_i;\n   assign USERALMOSTEMPTY = almost_empty_i;\n   assign FIFORDEN        = ram_rd_en;\n   assign RAMVALID        = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;\n   assign uservalid_both       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3)  ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);\n   assign uservalid_one       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3)  ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);\n   assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;\n   assign USERUNDERFLOW   = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;\n//no safety ckt with both reg\ngenerate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n            USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              userdata_both   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end else begin\n            if (fwft_rst_done) begin\n              if (ram_regout_en) begin\n                 userdata_both     <= #`TCQ FIFODATA; \n                 user_dbiterr_both <= #`TCQ FIFODBITERR;\n                 user_sbiterr_both <= #`TCQ FIFOSBITERR; \n              end\n              if (fab_regout_en) begin\n                 USERDATA     <= #`TCQ userdata_both;\n                 USERDBITERR  <= #`TCQ user_dbiterr_both;\n                 USERSBITERR  <= #`TCQ user_sbiterr_both; \n              end             \n            end             \n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n\n//safety_ckt with both registers\n generate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always @ (posedge RD_CLK) begin\n          if (rd_rst_i || srst_i) begin\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n              @(posedge RD_CLK)\n              USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n               userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end\n        end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n     if (rd_rst_i) begin //asynchronous reset (active high)\n       if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n         USERSBITERR       <= #`TCQ 0;\n         USERDBITERR       <= #`TCQ 0;\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end\n       // DRAM resets asynchronously\n       if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n         USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end \n     end else begin // rising clock edge\n       if (srst_i) begin\n         if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n           USERSBITERR       <= #`TCQ 0;\n           USERDBITERR       <= #`TCQ 0;\n           user_sbiterr_both <= #`TCQ 0;\n           user_dbiterr_both <= #`TCQ 0;\n         end\n         if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n           USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end\n       end else if (fwft_rst_done) begin\n         if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            userdata_both     <= #`TCQ FIFODATA;\n            user_dbiterr_both <= #`TCQ FIFODBITERR;\n            user_sbiterr_both <= #`TCQ FIFOSBITERR; \n         end\n         if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            USERDATA          <= #`TCQ userdata_both;\n            USERDBITERR       <= #`TCQ user_dbiterr_both;\n            USERSBITERR       <= #`TCQ user_sbiterr_both;\n         end\n       end\n     end\n   end //always\n  end //if\nendgenerate\n\nendmodule //fifo_generator_v13_2_1_bhv_ver_preload0\n\n\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Register one AXI channel on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   reg_slice\n//\n//--------------------------------------------------------------------------\n\nmodule fifo_generator_v13_2_1_axic_reg_slice #\n  (\n   parameter C_FAMILY     = \"virtex7\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   )\n  (\n   // System Signals\n   input  wire                      ACLK,\n   input  wire                      ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0]   S_PAYLOAD_DATA,\n   input  wire                      S_VALID,\n   output wire                      S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0]   M_PAYLOAD_DATA,\n   output wire                      M_VALID,\n   input  wire                      M_READY\n   );\n\n  localparam RST_SYNC_STAGES = 5;\n  localparam RST_BUSY_LEN    = 6;\n  reg [1:0] arst_sync_wr  = 2'b11;\n  reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n  wire sync_reset;\n  wire extnd_reset;\n\n\n  always @(posedge ARESET or posedge ACLK) begin\n    if (ARESET)\n      arst_sync_wr <= 2'b11;\n    else\n      arst_sync_wr <= #`TCQ {arst_sync_wr[0], 1'b0};\n  end\n\n  always @(posedge ACLK) begin\n    sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[1]};\n  end\n\n  assign sync_reset     = |sckt_wr_rst_cc[RST_BUSY_LEN-5:0] | arst_sync_wr[1]; \n  assign extnd_reset    = |sckt_wr_rst_cc | arst_sync_wr[1];\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000)\n    begin\n      reg [1:0] state;\n      localparam [1:0] \n        ZERO = 2'b10,\n        ONE  = 2'b11,\n        TWO  = 2'b01;\n      \n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg [C_DATA_WIDTH-1:0] storage_data2 = 0;\n      reg                    load_s1;\n      wire                   load_s2;\n      wire                   load_s1_from_s2;\n      reg                    s_ready_i; //local signal of output\n      wire                   m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with either slave side data or from storage2\n      always @(posedge ACLK) \n      begin\n        if (load_s1)\n          if (load_s1_from_s2)\n            storage_data1 <= storage_data2;\n          else\n            storage_data1 <= S_PAYLOAD_DATA;        \n      end\n\n      // Load storage2 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data1;\n\n      // Always load s2 on a valid transaction even if it's unnecessary\n      assign load_s2 = S_VALID & s_ready_i;\n\n      // Loading s1\n      always @ *\n      begin\n        if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction\n             // Load when ONE if we both have read and write at the same time\n             ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||\n             // Load when TWO and we have a transaction on Master side\n             ((state == TWO) && (M_READY == 1)))\n          load_s1 = 1'b1;\n        else\n          load_s1 = 1'b0;\n      end // always @ *\n\n      assign load_s1_from_s2 = (state == TWO);\n                       \n      // State Machine for handling output signals\n      always @(posedge ACLK) begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          state <= ZERO;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          case (state)\n            // No transaction stored locally\n            ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE\n\n            // One transaction stored locally\n            ONE: begin\n              if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO\n              if (~M_READY & S_VALID) begin\n                state <= TWO;  // Got another one so move to TWO\n                s_ready_i <= 1'b0;\n              end\n            end\n\n            // TWO transaction stored locally\n            TWO: if (M_READY) begin\n              state <= ONE; // Read out one so move to ONE\n              s_ready_i <= 1'b1;\n            end\n          endcase // case (state)\n        end\n      end // always @ (posedge ACLK)\n      \n      assign m_valid_i = state[0];\n\n    end // if (C_REG_CONFIG == 1)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000001)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg                    s_ready_i; //local signal of output\n      reg                    m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b0;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else if (m_valid_i & M_READY) begin\n          s_ready_i <= 1'b1;\n          m_valid_i <= 1'b0;\n        end else if (S_VALID & s_ready_i) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b1;\n        end\n        if (~m_valid_i) begin\n          storage_data1 <= S_PAYLOAD_DATA;        \n        end\n      end\n      assign M_PAYLOAD_DATA = storage_data1;\n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // reg_slice\n", "num_lines": 10519}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// Amazon FPGA Hardware Development Kit\n//\n// Copyright Amazon.com, Inc. or its affiliates. All Rights Reserved.\n// SPDX-License-Identifier: Apache-2.0\n`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nuVw5JhLL11X7sFlU0pAE+ly6TbXZG7ItJn3Ex9cXjSY7p1sc5OM17XcDMDqOEbaLgeEhUuwbGf++\nsY41qYpCyxKVTUSlo4RbifB6OdtPL5WbplRlVmZr6tVckowDKyf+KTfQD5yDuN/lqu/csQO2OWFG\n+FTZmZC2+4QJQc3yS24aV3ap6SiICL9zEXwFqFiBkzn/JHjRL0ul0SX2IlY2DGLf1ZP0frmZpeV5\njf+hw24P7s4xKjAFgaTp3id7hTx/VMEsA2ezH0GQbEMKybRgNRwMm93ZH7rKsmeh+vLM4uzdiiPH\nviyKgiHJcWlJF11UMelWbvVoYsF7uDJ90n/5Ww==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\ns7Yn4DABLzF4SLp/0V98P0CDCkZYnP8iqDei0IedIEX1lGPO+wDX247jQ5AIWSMu+s+1jQIMeWFm\nwwhaOWGt3o1acmXqPnf1xmu+ASh0sjaaro7Te7bhxTdbst8KbfW4m1RJX+UShZxi74/veNFylojR\nHiUek/GVQNWaepFc9Xo=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nSulZTeegbwtiqqiy6RNAoCNHsjD2rBzbr8ndOVV7AUZ0X/egfC2PVGUQ2Zwy0uxx/G5Py0ihEuGz\nMBiYAP/4TcshTSjLEVglOzGlp6fbSx9KYr1eCu1tcnF84602dfHBQHUV4WrLSSNvwXOKp/AKyOG7\n1ALfiTkaDf2vG5TjkzI=\n\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nVeIIJaaPUtlfe1VvZdR/BjuSRIXs9q5wYiTwm+LKSUDNMtXCl0A6nj2xESHweWlx4Lsjnho6VXem\n7zwg08AWnw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 7104)\n`pragma protect data_block\nwefYcOgqtn2tETmWi8Rbf/n6M5BAutN587juaTMCMKbYASYN238z7WFXImp+yjGBHm7wW2Qi2r+8\n4CRJlSWuxJt/0DjSKDEbzfKT3Ywf24s2HItiITNYHmiQcHbmwcaginWLJcD0kej9qvRWROT7Jdol\n6p1ceAC2CxqBZd8KtGKA1yOqZfjvM7YDupzNTlJ8EnI8spiXjcW/hk3QdzvAAT+3MvEBtuMYPwg9\n6lfyMWuzIMCb7mND59+z+A6Y9kmp4sJ1RgfrKaInNYqTVwGLVkKRUjCmdH7pptXLJFzQOfA5LFUW\nobrQsrQaXZr1Mz+i68t31XE12AhBmHbtN+SpVLApbX+A7sMdDFo2lpQqBa40lYnZyJF0g5cBx9eK\nu/YEW1iX6rq8HaTsVLk4BbMrZfJuq/ODD2Hp1/UIgsW2JSJqGaqwAQCFGNDS4mcRv8RLAnveqAZk\nQJ8psKOMHRMC4OGuZIkI4024u74khNdkgiCs1gth4R7narobPlg4Q1xuWpMbTFi7SaFjQWRMZYuD\nXCpsVXxX6vJGREZGrkT0uDJN8Q2kassteI7QYPLCqBCso1vuH8+WxUjwDI4MUv7K04VLAsg3wBK+\n0JIPZi/4FajT04MDy6kNpP+n0IuV23UORkPa5JOjr91sST7nORbqbnmCvN2fJXIJk7Fp9NQkdEwu\nxszleI12aemGZtWMSMo/Yw9cLBEm7dD+fyEi5AaB4AenenIBt0mhm/YqnEAVS5CyAJ4ZE7BiQ+i4\nlPsd5hxGf2V8/DRGh6IvQW83WVybzSIpKXqO6wZR7tsyNQi2AgJ+tz+mgLmCJ4qkHUYy2hX5liKy\nbPuyhZrK5eiNylPw6q423CflAgusNlPaO9suIp/Ta27JXKduOp/w4qos1f9BSXZ9DPBdjOcBbmQQ\nGKEYc4ykhwrSCAJbKyUc31uCRSR2vHBTA0uWvT1M8em3RURw8SEequIg8khij6hLbWSIZRqOVcBP\nqxurjqLk3i/fFqrn3BeY1wAlVCLZtKwtqZQ2Vm2JUaXy7kji2/DMv1EdIBqG4PjerdHcq1kLi8dz\nvQWrs7ahQcDnbtatpipQmYvFLSibcxgbv/Wy4zmPFBPxbDQ14gsIlGAGxSvfTAbdhz6aND0bYNAL\ng5AxZ7grqhvUL3vZLmRXTCr4E6K4B3SHixdvy1pjqydw4HWhrjRqYU/kYtbCbNP6Hu6T8bLYd3w/\neyGeXDpt3rX4qPYHFQh0CAJDQXBlfSgFRkGbUERcnTsFd4Kefn1ps1W1X86TjdD91zgxnVN00G7x\nQbiu2bMxC7GOXCb1dxT1qK3NCQnDZ+XmJbSRMR1V8WCT+zGUq6PAtBdtNsa6RgXpiQXQq+37FyoC\nHJEsBhWai0+IOpX0pp/Aj5uip51yQntzZYOPF0NEyXRRKkc+ApQjKOSfQPjp72Fz3Ssf6FRKD67Z\nHxpKJY+W5nNJWGckwAsl9xTFDX7i8J0KuFZnTjINILEHA2t3d+XPxSL/CBjqjYGwWr5tyet3UvOW\nvfpPXfNJEPcSDk2Tq/Ri3WnZMBs42waPIHQ5iEmPfqUSkJoRUbAQVZIMU1fuLLr3IU0Sm4NQsm7R\niBcGU3ZtCPjFCZ/JWLBtpVgS01bfyxn0w99Uw8hU6J5K7Nz4yC5rdWRo0f7JwzlMFK53HN/KerBc\nkk1UxRXXV7wMXPhAqh+7aaJuC5L4LLtPEqS6fnZpdmGeHPrsBAfGTOboziF33th9LNMlzfiCldSq\nI6Il8GGakTn5ITvWEK1zr247DtesEHNq2M/8CoP58Mjy+CXtVw9tdCVbqDikeDEMekaiA2ePeShx\n7MfcxfX1Uyio9Fel+QYF3/UlfS4wU6+gNlIvp6Kx7pwbr4NyOaZbPVsgw0apkRVga9J6O5ZuddBZ\nC8a9Iz4qs5NnSBaBDYVNu+o4RcupeeD7HaTcaOAB13glw5GYK/Ko97sTzBs+H4d+hU2dEMg78Meu\nD96CVhOJs8NdwBZrngVU1YhCZHNO1zguTlmltQQnRvVsmrKK2omvEWXhFnpifkhoxEMcARBXC6No\nGlmt/RT+zZJ1cq2e9hSUo7muggLroNn9LCdh24kSWKHLCPqQEDcs+VWql1s014FO8/YhAl+vgSOy\nMLKuB7ahyrHdqWxamWl2NjiEfqQbZhorqzecPvO3C+MIOjH+kc+8C2sjjeTlLvLEiNvSJUY2ScQq\n7k1w1wtXmnA5aCzy48N0W4dWyp4o6ggVYxUA3usZ62CEH3969mLAqKCH17d8NNiGAzTx9SvuqfH1\nPBIugYI8wdnk265EWMJ48pWELaJR84CUsyhrCdJcKZsWYFFwX0Xybptwcvdv3DrdgM1EtUw2T63a\nj52XnrbyMiLaL70QgAm1C9NM8wSkDd4p/3qJSFwm5nFZbxAT20sUjLX98hgjqgftnGHR0q1AX2vI\nGWS9EGeznXoeO0XKivK0RA2mWBAkSNmij5Ld/GIlvPk9rRtfj9f5Ea96eiOhhF5zBaI85OzzY7Xh\nHPwX4c88zzFHuo1fZAaNkKgl98ABmPOY5zA4O0wNaDZEaPZ1MYjryQWRBW25yQgBckj+lrUA2WLV\nAtKub0Syvb0DQOWSMHWbWZirghKqfXThee+BRsekENnno7s5JJaQAUKapZT5V9z0g6crTPyHR9xH\n0UR5hbvcjwVGuMKEqlS2asqpngEM1qA05Kyx3eGs0tH15B7oj7YHh9E4k0XflMmdYVhamgsxoNop\nBMfkbDLXN6Wd62I3UcksmvSKFEBT4X6wUZ7d0ee5xEqMorIiTL22CwJZEq2F2geLjXJw6nmkjmsQ\nuEoSQXdxsFzUD1DUsq/iYZXiqnoPsPOOqE7Wy7biuvztAApCx4bvTACdN5CrMbXyyijG0AB8x04C\nDvnnlL3R+YnzBPbhBOCWqOzPTDgPCWTKX7iqgxnUd/FN02uNTgBj/XfgEPYDfn6NSosMLGGO5jyK\n/EL5fWieF7VlM9Xw642jkqotOo5D1OEvpbok+gkLDUMi8uC7XRnG/+3VJpJI0xanVS4Wi67yb5DH\n15q6Q9iJ0QZ7m1eE7WxQzljO7VYDF7cPwUTRlSL1TWD62vbMcZXEY1JDOC3RUDpudW3kOA2v0MZd\nbizUm6VX34P8KVB+EoKiuW2u2lM+fuFJGRecdRHTdl9ma+WXYXrY6gHVYV9cPpwgR6QG6NgQ5h0U\nIt5jm/fEp/kp/bT/iAKAgWgwxQ7jNq7KnTdgWcudVm75OP8G7Kl36hUdVXRiRnh4F19jGHDQpOo9\nOcu2jggnXM5p1zo2+4pauk2pHmHkxbojSkSyuZDMw7NGALkigvsuTqArn9TMg2WpiiiBYP1W4fqp\nrzQRXJ0e32c9agUvg7n6iisaCrzBmamPHeBdNQvL7yVedfYyPkYuaAo+N1BfRWsj7UfA0hXExJXp\ns9SRL0BHvuDFV3IC0SLO41je/zPtegjXnwLF+r1MWLukp+D2+P6XSYAPJ+PbcpKs8Qyjqu2hj8aR\n+gs4UaHeltMKAp5YGD3eqLLrfrdVI1OhqNu6CdW6cr6ykNwIe9OivOfGrgQ0kpzi9tZ0ee99I6ij\nVpYa0Wcv7b5dMMQLLNTL+g4iXP7nOsFcOHWGAnz/V68vWUjbhAMxVypGQ1ZjMlRVvGaA+7NTG6DR\nARlTDjGD87LaapxJnCbZk7i/psXzrRKaxjqbLqtUexSO41esE/eWUSO8LoYXs4G32tyFgHuHSlTQ\nyJ2CYi+p/7E+TXbWhcWPpuxIALzg0E+nj34gYYvJ2TQqmmAmnktNBdOesvOPGUA0xWREY1KeYwl/\nnn+XI9NRI3zdWrGoWwVZcxZK+/fxGxFKR1o+yaS78liIadtPImR3vdRscgVWVBnNqiVzmdbH/qe2\nI3XKPkvviCY952zd6HPEY+2AqrK9G02vQC3EyMEIOAdIHoMhFh+j8woFa9I/dUWvZ5KMl0qd/ZBy\n5jx1Uh4Vhd1m1yVGO39Jr391I0qT80SfoFbqTMKP+cN3aY5SZR5n/v/gJ1mBuvGul5sJ4ckvn997\nPX8HxwG5r7+OpIEjM3jqRKs3SNcUaAQcZq47oaM3jYBbAcbmePUN+I0GT0XENdOx6fo9br/cSDXN\nrIrz7X+NgXR9xyjxzkxoo8LUMYGwfXa/LivuuCHd1ZY/oXLA4kkNX6wzz+EfS59w7YlQ1x6ym7/0\nlhL2fp5PLDL7Lutn6tEzDNLbQigU+AWiXbsVe9w//gq4J0rg0arJNpWk4bDTImBLn9JQrWZj7TCv\nTSPp7t/1Y+Ql8s4Zy738UcT16UGNjTkughC+eA3AwD0ue6EHENSybOw9xC8Jfn4EaF8RlD2APPV/\nT19fBHegE2NL2oSm5rJL5WvCbG+yzGJpA/1N0PlT30e1IZNWGrGHwzOZjy5LHbFQC9rb/5JcLl90\nPxNwiqyq7Y1wux6wZQAr0DQgQ2pQut2jPzMGEnRJDmv8+JFt63IZkv6sinlY548ReZpX945nKd25\n5ZIq7Cfek95Z8n3ULAnGHQrwVwOW0/VC2W6dA2qLZXt09TYWTG1PsMmZYovnoHEBsqlw9RxGfIJ6\nS3SxpXT3lX2jbLagMDjuxx3fYwMvJb6atVioJhSlysMNr8Hocg/B95SOuIK+jYAVBYbKvKNVF5Dx\nmFj9GdP4Q64FhYgUvehcWFHKGotEN+o6EIxrEi4UXphlXDJTxBtnZtpv2WIVhwq7k3AeiwW1V44/\nk4Vvaiyg2rttg6pl3VZZQfJXHpQKs1tDq7SbHxyTuawbM8NFisbhFNEZmdgPId4CUcNeeexSWAHM\n8SeRDlNWVd5h2NY0RzrpVyEl4R/VkGJsKks6mM1+rn1KgZVJ65EdnIMmWFCQJu3M8OKwIR/LRG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protect end_protected\n", "num_lines": 167}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// Amazon FPGA Hardware Development Kit\n//\n// Copyright Amazon.com, Inc. or its affiliates. All Rights Reserved.\n// SPDX-License-Identifier: Apache-2.0\n`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nYzI6RhCTbTb6xat5gHIeU45bfm2pOxmnaHqAF/ihtojvH1fxm05ID+E4jV65ljsSxg5hk/XNYq68\n5CkBs8aMWX2C/dCynTYKfDqEpu1XOG5vhg2rSwLazHMgBBiUX8dd/TfHBU43+45Jtb+i6MJjiXIT\nLBsrAhuqqlguwXMgFHWIpVMes70PJFciS4hmicgXcR8ADn99xdNaECHKlsOyP4wal/3xETbCLOgz\nrY0WTcy6+DeDqM50GUbu/OwxE/H7hE1bcXDowM9dJ67aUow8Jz9FWmx9rnWha+w0R2idFxiRDIkF\nqo2Q/g7aiLrgZhYsdr48/+HQ+hZdLV1ht2cUCw==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nxSa4lDWJPFFHiwekdDATEy0KtH6thL6nQyd1iZiJLJlNN0m72osWSdzXVg5vlTAOLu1Djn8YfwAS\n8Ci1p8N1sdRHih0qs3bR8EdQIdQgSH6Jvo7IeitExQzPQSHZX2FFBNfeFMSNWqy7rAf966pPa8x4\nuVfwS3Iqq45mqDrB+Fo=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nMauTOqq1ePQoCVfMD6s8BkjRyvniNKLMVJv97eUg2GNKwdp6+Pq3ihUtha7atOOqdhLkbr2DWntz\nDGYI4P4MrI/o9m4u8NYO4xNDlwHAyMABzkf+86pzXRQGz9LFVwrluUGiWtQQ0Y6xlUjx0xJUwINH\nsPrEw3NmP7E+F1pVM2A=\n\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nT1wGXZJPz+3eyrBmcY4j5dqmG1h41cDh5HE8W3W6NQEuDP2Md6yWbAfQdk8OYIwa/nvJab58+7LM\nDngjbM3YwQ==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 2864)\n`pragma protect data_block\nvR7+IXoeIJpBd3RFIeE3dOK6BypJOZY90p1Ac8F+1N5uMKLd4HYmm/VAQzJiaiYp9plobe/jVyh7\nmQpaUK5vPpi7nd2BtL2p8GAoeQOQ2B+uzqNcTJSjA/yudJDdSSkw3xy3GDWxPvHsixMHDu1aDGfJ\n8+mwwNJdr7qEJ6MPXswuWq174H6HCrUpQSsWW6qveCd7SOSmP+m9kCj/KdoOlzEfBVqOxVVLDuHE\nmdotE8mGo5jbnsJgBE8IuVMnxgHmNq3bhYzIYusn+nX+X9XXBXD1Qupk1OQYf3Nwc8GYoCGPzCk3\nojQwxOvS541fF/xn9NAj3hj1T/tXwrlkkoInomWJ/JS9TdEbKyQBCtyKf59hSolXzqmLfxPRU1/i\n6AOKABIOTjDiwOrz2iwIaal/D7d72iPZTY3UExoy9YutY2AmVI0WbL29SyDQDAeiXJiOAEU/8img\nbRDyi0c1UO4F10eyBYoWBsW71tV5cBGjrszeS+H5GIS97UVOQ1qVw1mQpd3ZpLztce3VhziNRr5R\nL/FYl+AzceFYPLynkpfKUB1UyaZgNypdcNmlvTBb2AtZARRt8TFA5M5KGl1A7lP5Bap1c1HY1hgP\n9lZit/phjdAvayLwFKcoOFXpqNhcSGH75lsvcf2a8Cb48BSnfh3vgpRkoLjxoVcaekA6ZrUHTwbB\nX6jVLd61+QuRAYZ7f7Yl4dIskRKaYQctxxvT8867KeyNW/Q9xRaUaKS7M6uZRzpRbR2Hd7VaUtx+\nkxP7w5bSIASjBIctHZvWgtmvkUGiKHarC/OGkM6vIylCEYOLlBv5YgKX81CvNjZH/4CfAp7GMHdy\nrmmy12YztImSsxhrNfHTy1HGxLcnwS1kQxUNlEkq02ZEF+mEMxMumfAGlHdJbOBXn1EE2fMm5zhk\nJVI0rja3v33WlGb2R5NHArLna5PNh0UaZSC+exqb8sUxNS89jUypbtCJkBBhVMEHgv6+Iu+c3Orc\n4jkk87BGuZI8nnGUbOwO8KCeFUcbT3XrxhokwjpqlcblZ5+D+EbjvE2dAR2dreFckak3RXIuam5h\nzKjWbpv4g2qThgwWedMBFBuGEltpMNpZp1S/eng2cVDqrR0xam5E1EwEspWIZvXat+eke0hv5uDC\nrpp3/ipF0m/GgD2tmdmBsFNZNLWjK2vpFF5Y+19xYc00QpzR9td2M9pzcmboiA0JHaC4E2wVFabm\nwn4sI3BFJEiRj4F8ag8IneahRFxNinQqejokeDQQKMB+b6/TqG4KSnbL05AHAuBYmo93SwKmHlu9\niQXEOaws0ck0A/mWpinx5U4ADgASu7aqFx+7QXYYvepDs1WMF0Jhr1NU9TckcYlQ0aiP1pEKcO4+\ndbZanSWH9iolIFNGzBgZtQ+j4dVeSiCwPCyAu8c36i1/bjc+N9wiAJhheLmq6fYOSn3V19ATajp7\npM+hflNQ6GlRXV/FMbNuUM17SVqy+TjJ8LFWFQKUN9bddyJFavGHr30DlQ5U1AgCVVZLI2EuQiok\n27B45wfZ2UgyqUHaS2eJggqOS9jsDgjsES64hjIsjorQlyZyRV9nVejQk0L9+Kf6ScRxGD/joWuY\nQ9eGnJnkwq0t6nF5xWh5nlNkaBEtZeeaE7P0LqhuE9k2zskOFFF1XOzovKHBEfuCYgE/0KADYDnK\nDkDbnj2xDjaJ4qJ0Kh6HUNS/xy5CHRoQAUPJ7H9eJLm3dsWcJQ3PWQodYEKz7vilSsiy6ryMymRo\n8X0nQHDQb5vOoxwNOOn7C+LkNow4w4aKhdC2s12H5M7SRmpnQ8CcEsh50ZdxWWlSVrFXHcgPmXHE\nKE/y8isAA8ZABU5Wr4Mm+lh2lFyZe5tDT17kiQvkBiJfAoFb9nrc9kvtKxFcbtWAOYq83zVh7sw2\nkBaTJ2DxxKMWEKaXwl4xsMuCsZ6OaVhW6UcGIITe1KdfnoBTWBM+xDwv3ck5rKWGb3AUqRnbUMsK\n8DgVGU9D8My1BDQgiRzJ5c+abFZ6kTSugULXCEq9ERntrWG1M+kX0IzzMZTVMAvybi4i+lq7jTK4\n6tS2Bpzt891+3GezNjhRbQzxlZIsuZ5TQ61RU/j5H44mnEEM61nPmQPcFhcCPx/wnin4WbViJC5a\n+UT6qm5fNii4cuiJqEhTBzr0CmdFPfjnv6SSEGvYy+cOcQdo1+gQkEcKWGT5dL8IdCjZSsAQWAFC\n+x3MH32YBUYwixG/o1AV2Ko/a9N5LRIX954/UCeYOJCe5hFcD9NKhmprzKMz2xwopfnh4yoXcdMJ\ntkkrhoiNs0DjPu5mKH6hoCDZOJeAIiPoPPc01Vo8w0aoTwhCWBHYR9RSu78Dmy0+MSHhDzxzvZYF\nGTxyfwwkV1t8YkxY75K1AtaHHhQLmUNoddAFtKroQBuplzNQEYrDosfqC/CFODAVjNC6S9l3FS4T\nWbi+jtJ0lQErhQl2Xr2LEMlp/cN7o9YlZcbp5K+wlVbB4R2RHR+4mqPbm49XOdE97IeqRWR5F7tF\nOj+iOH6D9v0nKJKHLIPnUNmigwODed8KwZ09HI3FLuqIcUqTlTZABuxPhqOc8xXkXLxrH+bzJjyl\nGMuLGUwplfc2bLbueKeSWuOQitcyDYjKbPGSky8qrtl4RhW/4YI5Hn3KVmxIad1e9vrOf5Ux7LqL\nzRw7be2tFjtsqpKJ/zFMTtK56IN6FXWcisEAn9lkk+pYDkBIr/dQwZarBPmbXJQtrKEPt/iz50kN\n3JtjeFB1l3lTNEm4ki+S+kpY6PmLV2P8Xwg9eSMBe606GzPYqWZg9XOPRWuDnP71jx+Ahj5kBiRB\n83BM3i9ZyPODeLP6tz+JBiQPNaKRfdzGlBTDUVUM7xUwrRFxbqNYG6KYj+493GKo0Kcn8+yVs78m\nuMsPjwBGYieWKbse0kBY3p2T9/KtA39rxUt8p2eISqVordD1KV/vIenzYMqZDok0QHwx768MwWU6\n1q57GzzyB8hd+YPOlTz8B8BMrrL1AJId1nJfL0z4W6NNKifE0dZLB4qFxus4d2AXgfnEDT9ZHZiV\nwwi3LdybbzpsM2mseT9w2HBSIuTgqwX6kdSfRPLxc/bpn7ZqAODF2bZ/kmm+8o7YI+/CTqfj4TLF\nk2+r95/P+ce/2a2g8o+RxpYehSNSiG0BK4oa4Zd8z4zVk7DBde0Yena1bdDCid9GsPyTGcbCWMdP\nGRGhsUeNSBcWi1h9gY0V2CGUJAT/rWqV9wwXGQVV6jEfosieq+6DmNYVIav+xvxPshfeulHrknPu\nCx1u5uoilA+a8nCZxYMa8dUYCihg8Ca4ftPjbbTIH3R0+z+GlweFNkdLbSuOGomo97DYoAiuig1Y\nYMf9kHMxqu/lmj2fr8kRuDKmk7deHFbxD3TTdX3fa/FhHTCBUTs4zDhko5t1d8vSjSD1HmIiS6lk\nwVcYyWoJ8JZOq4D/TJTY3QUualQEE+Vlu6NsX7bTye24cdOhPM+Ou0szgCHhtpweGrPt0l46DKtb\nwKZVhN3jMfTSCeAbYN/RjA4Gyb7mlIDSsuKQog9l2jP8yb0dRD0NAZ/c7UPGggwWIX7G8Eei7c2V\nobqHNG9fmiQFr1sa4P1qjfM53NzWwEg2AZUaDTn1p0mkJ3YC/GfucgquVbIbz91FjD+m+ehmp3vg\nYDzcoZvNKpq5J2VBYs9iKqn9UE6FObH4YupmYYb/xcq7Nu+mjc8wMq+3g6L7cAsayrobefUwCIDP\nEoUxh8G2NibYTXadOPt7oH21Z3IDfjxOccCqE7LepfQzE/OH2E500qlTRdKJY/Tmgcekh2bUnwu3\nXlQJsZphGfJyyvZyppk=\n`pragma protect end_protected\n", "num_lines": 93}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// Amazon FPGA Hardware Development Kit\n//\n// Copyright Amazon.com, Inc. or its affiliates. All Rights Reserved.\n// SPDX-License-Identifier: Apache-2.0\n\n`pragma protect begin_protected\n`pragma protect version = 2\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect begin_commonblock\n`pragma protect control error_handling=\"delegated\"\n`pragma protect end_commonblock\n`pragma protect begin_toolblock\n`pragma protect rights_digest_method=\"sha256\"\n`pragma protect key_keyowner = \"Xilinx\", key_keyname= \"xilinxt_2017_05\", key_method = \"rsa\", key_block\nEZ2tH3LeMVv7vukHaN/tv+pQmwZX81o7thyHVDWF7mM93FaXyNhCXTSyDdazJu7/59Py93a+cCj9\nEEEG/UMXcssv/u4GhJzoLhNbGUxPXLsX3SIGrTAhYMqUghm1uiPpNdST+Khvq3rfWs5cehEPvsWw\n8A52qamT0g71hscVONAjIadCoIAAQvF6wBVGan/xoUsiiuVj/StB/MRCaU1h33zJVnkJChMNuv1u\nGcwL2vTjF2mJSTLkMDWU4d3JqnNNe6JLK5eokUOlzu7E90SIv72KLBebeiWgyJXoUTk3vuN6RBcl\n1NLulevXSjI5J1IzTMQ8KdMirHBaVA6r1l2Wsw==\n\n`pragma protect control xilinx_configuration_visible = \"false\"\n`pragma protect control xilinx_enable_modification = \"false\"\n`pragma protect control xilinx_enable_probing = \"false\"\n`pragma protect end_toolblock=\"rUY20Sun5Njk38TaHPm9PEsmv9niNjWSTL+22BD4WpE=\"\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 7104)\n`pragma protect data_block\ns80ewUsMopuQpWnFB2sB+ONF6yKt/CFEoFhY8eN6Fd++8VwoecJwX+D+xdDD1B4a99zC2wgLlCPa\nLpG4B34md3a1iLti2ElPTT75bw6YhUJ3GFvtvWk43x4QV9jMJaVTQIQQC5q0jUynSr0bHfYCiI88\nyr6/+srQ6R6y+eENcHfUzONGqx+BfCa29/UbSZohsT1dVC59xufibiI0SvLZRvICksWXk9bL3dow\nWxrDptbLgNjVBIhyLPwiuQvDtZ5PMZWKKhwF8c2Kh4IGBpy4tY8doLEbF5CaNIcRp92hAQ/MOEYh\ni1gneLVYlLQiQR8nlBGPcYH4u7ymoTFvL+Sx0mMJSAxCrFziTeNdzNWf5te5fh2RxaZ+6l2QS9Zk\nOxAMKLy0ZmD/ND/8AXlSsLUughpPYFeij8vZmZ+WsDCp8B5ibGhpEZrjrZQNTgu0HU4wsgr3jbiv\nyDCQJIMTSWKKGwDHgVjti4ctxK+IjUu8zYEAdsjlLFKx0rGaJjnCGqD9L0DryHXvfojIT5xfvR8C\nqy5bTiLFSQawaXjWjJmXgdvIxazoE7yIsDENaKMCBdSafJsNkx+O/MR0plWJ/Pgx04t/pEP5Cy6W\notlG94pAmM47ogF4MnMHRF+rVpysu9p8m0sl3rUiPHfRhIOFWgHRKk1ZC3HOo4TQmeQaGWyTeWvM\n9OlrB+DE2U4vCjeoJV9O+vKiKC8tq3z9IfSvRqcW9Fhk7dEjs3qnCPaD1kYi8+UZCio/j6eYf7UN\nUKhq+I9qxsyR1BmhFNu6Af6B3hAY5Qeb6UH/KMbqHCoGlJEhXsfes2Kp8BvqBfl8/CdHhvLpK0aX\ntAfF+W+Uh/DfOmIE4/wtmA8TpolUsdEHfd6qFWx74M/+vi1cZgIN2YkyZ8GWTixSjIbciGE3+T5f\neVr2/IrDuPSuAn7sq89UGWxnDYMorw7GGSt1X28kEK3NaFs9f87SLlx0k/Z+/MFXs8PPrf5eIv2W\nLC0Y0bSmQY4Fk4j8+thYuNvWqXR/67m6PT0NlzZa5bDgn4+htU2HhH4eLs9ABfPQLT3pa2R5P2HP\nscuqY0NDBfGiyCKbUsAAqrURj+BP4avJ0C0mm2SM260c/HYpjQ+unBaY0G0yc9iXMTCmEDor4qav\nlQw2qFwUTFdc0WiZoeO80OZd27i9heulJJ301rqnlDvSz/9Fk7cUz7GFiKaHVCTqL+/u5J8xY+O9\nN/ahSBFZGwQR/ODX+M3OGTfJi3ZCKECD6qTDlmZqjqXd24O3YWSIo2+IT6QVV4XPZoXkLrOmVDnI\nr8LK+396XsuJ8HnkGihELPBRVQgg/Y2U/kCdTPFL9/+0rtJdAxLNGqJOdEeUz5gW9g7i+bvdSiyC\nvcYoq8wmOhoVRi+spru+R2/MUsriYLHXx24rxpeMNG04lEU10Hor/xAcwgmTI8tNwDJB4b0r80JM\nr+swUyO06BPv9ZsbHycD7I4g10HyBw/mu20EZ/yf5QcjEDjBrIdDIZPl+4FwDjq7McfG2NR6Vwau\nD5IS7YrxlAThTO0K1P2pE9MbOgfEQ1Rk4DZWkKil33leAcmvydIcK3HYtwtDU/YQPEcxWx448JRL\n+qaDsGmAxIA4wczgpXq7YKRq+f+3Hmu+PfOUTEUnwRQIjVl8R6IOpAh0WOMZQWCdOgrGPjGlCuRG\nSj34xTHAXX0+vONpgapnAJgA4gi493EuFeruDbwCdyanUOvJqUveFWtpF/0aJlHU/Df1tiLryl4G\n/GwLb58dMvdwNDSQrE0G3RroxyiyvK+EfLIKkCE+nHmsoBwCOn3V0+ZdOFfuj0Dr6dAyCYx6yDno\nyhkLi4iZLHxkUVs6Z8BKFIxza/StaoqYG8iGqRhRdGH0JfU1H7J/A+yjerNS61Ap4SQ7Vm1v/f7h\n2iRJeYDTWlK/2fL8HZBAG/PAjHDQf3E9YuObk+Xgu9fN1de5T5A1lQRGuneOwRHOofo/EXNtJAq/\nOl0V+IO/oPnzm9DMJrVbAVHm30VyzW9VxHsCliYJxoVEalwZJybjLwk+FdHFmb9246qlJwJbWnH4\ntXbVHikM/TbIGn4q8M4UCERAA1I/krb+5dLwu4egiG7NkuoUuuoABg4oN7dXc/r/Mm8NEFa+P4Hw\ne+1sp9vGpG+kHMIhaMTEDLIa/6KzlIXRsYsdYa0QpnyY06TR4l0Gy4ytHNPGLgqBD7PviK+eZzvf\nP8nygmraTiTwNwRtqoF5DkLMPY7KrNhHdsJTTgHFL/vhwfvTUgukqPrT5ehF3IK9BvQCfIRVdvDr\ngwbBGNbtI4SJJkYmHZH/m/KGnWlqoCOXNVvjVDavftAXr4mNtx5vSqVFx+9OMVmYlyn0EUCCGYtu\nEC3KGWAXVkH646lAaw8lNgp5NCLhLM6Hx3e+9V6h/Q6I/QDjA7/6NUF5Zf/Gcjobv2X/ey8c6eDl\n284v7ZAE1oBlpj8Y0/yDyt9KKkpq6RP70BnA+rfwWmLP4pygJWuO/cPHybgeC8CqCZ7GoeORZAXA\nU4r33uwqrqnIZSGSYXJMsnsybG/GrXXAIwRo3bH6SR0rX6gQJdotqEgabVXMX0P0hpouKaVn0M68\nuF9IZxrO+3PD+j1RpJ8LJHpEaJwyION/7PgQyBNXJ0SBSmbP1LLmxStNb4a9PMJ7VQO7xcHrVVXw\nlfMG4cbHHGmohg8vRFuAyWwTXUlQmISjk6tTQOsdVWJB/BoXku5d98fMhEEnHoZ0jJ1atIFuijgr\n828KNwZdmI3SZSmD5lVONV/zLFgtWrlNp7hcnl4q49r1tG8YgA71mEeB7XFAciZXDdRX10DdKQ/8\nueUhQ7XYmyKp+Yl5ILHf7G8htGitx9q5hDLIxDq8h3Z0R4PaX9WK87RP+mog7nObs8ajRs8bI5Rm\nu0hIk8VsLXzRr7pT92a89EPnBnGpkAEdBziznE+hxBHR5o4teEJvce0yQl52gWeO2dcql9BozfJE\nFL9If/OEfYyQdWi8qzS5fsl53esw7AH11jwoYPsxhQUUmeH1dAxMi+RkW3+WaQOgEJjRZxSIQJqL\n33lwu/jfnmRXWEII7s8SpUseLgIeo7HT6+ZmveNMOw8uguta78FJfrif6tpA1KBoCkNnb5bxhmb5\nzDhe/Q4Eg0UW7/VSpMZfi7ypuyIGzdWCY1KNWeDovzco0xeg13BFsxiVw29YpKKRcFQTLsJt6OWh\n87ouBHuJBg2984G5TcShmKAsBR8D0ZPEACu0MrWXeQw34UPWNdtrmvq996W5xNQHnqN8lPAWBvVI\n9rrYk6I2uook//PGmgLi/1WDq3Gix3OSNfPkDtUvbQJA1pEXOgYASEjgdyob1B5NpHQguqAqG/NP\nCBILzgyuQZ0/CDtPua+otMbnSz1hhu9UC8Na/QyhKNT0yHY0ug2C9+sruPezZJTWMnmEXRjxRPuz\n21KqzD4jhi/g6BMrG4QGVwUhahok3g5FtRrmVakP2xzBwhMX1cg/pKzY9ne9lAVLtwctLnxPlAzs\nGdi5Q7fg8K2NaopGE/r7Pv5DggEiCQ9Hi8nXlRSJMMKJwbFjikNyte8r4eQocIjYNj0UNQETMbk4\npe2gg2x7enboyWj99a97kTLiGsUF9TwCN287ECxoUJxcvX/1kbUGR+Xcp0y1L98rVe0eXeHsju3U\nUgzRncsty6h4r+hpjjBLgWmv5AJGYXEQ2BY9IvgZ24vfeM3HufVPfJdh/zmH/xq8f0MT5fPvMyVL\nle16t9riMoGhkW24elZpnNUmNLz4sByGsu23+ad/aelyWV4QEuFzRuUbM5E7bmkb1szuc0njsNcx\nLWcRDU7MTOM2fQ3FCQFxicl2wh+vW48qbL1ZT1JmiDqb8QYCEutTKcar6njaeXvBlFfiBTXdWp2C\n9X84Vc2EB5jCk1F7rUTlBtbGteCdD7P28n11GyVA+pJu5ixjtgg+tB9hxn6h/JBj8jChM+MC2PRB\nCZXXu5bTgSwmFO6yjYsFBkB145FV5v2dsyQFO9OgQZnZ21xVj2gik4U5hwFDrJtHeLUfmZ2cwR8P\ncoevnuwsBDXk4At8S24i8lNr4vgZRwV5SeMuVbH4V2ma6vze9/Ja8i4GxWzTlexnY4mdK6Bx7HFx\nWpAK3k5KxaKAUYf4H5I79b5ooSFwEhqeiVP5s/Ee3eGnqD50nAmNbwNVRfotlVzqtIljbTAPOHGP\nByBkZ/BRg4DqPQv/cn3Uw5zzE0jBTfisKxUrglduvQ2alHDWBbQbXcgI5VRf6HmZumEEnHzxByrm\n2EcwT3aOsJISSctNqu0oBvFtYuIFegeIfRZZ0HL50kRBPFsfJNmyukH9pWUsc89MqXDoA8MMJYdk\nHHbdKQeWkjL1tI4z4alE5OrwZeH49ome+bTTpxv02lLxfprer07a2Oq7k5q1Reql9rOR4QqiOMuM\nZyrwD1sLXYLE/6AmGYTArRQWEM0/9pehNoZvWq4Ilu8z8Yh8oydxsCCjEkTshdOUQ43xmPI+1/gZ\nBHpyvU12X7xqEd1HqLLFiGhilgpjSp/Fsbe4VQbfn4VZ/nUfYBGodDEK+gyjt/OT/atph4YN3JhS\nfuhY0wT3zaZbBXVXrt8yhz4IfVDN9d02WMFaBvPKYuGjiyDL8+CsYklbIhGZ8miP4nKqs1sUTyxZ\nn+K21cQoq7Ojc+A9Xo3KI00PBTw1lZA7EhzBOV2E9LjvwkadmwaRQvlFEk+Ocn5Hin0wkKeINBEo\n+SAMJFr8tRLPDnumTaH+zKX+VRFc3a78jKnRamRCqiZ+nVobBjl9sQT0rl6/J/Q+v6V4munc6L+/\n1Pdq84XnKdcQOj4fjFFVUzoyw2enbm0hc3ViDLtensCWwA0pa9d1mVjtgk8oweDzsRRtyCmCBX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protect end_protected\n", "num_lines": 155}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// Amazon FPGA Hardware Development Kit\n//\n// Copyright Amazon.com, Inc. or its affiliates. All Rights Reserved.\n// SPDX-License-Identifier: Apache-2.0\n\n`pragma protect begin_protected\n`pragma protect version = 2\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect begin_commonblock\n`pragma protect control error_handling=\"delegated\"\n`pragma protect end_commonblock\n`pragma protect begin_toolblock\n`pragma protect rights_digest_method=\"sha256\"\n`pragma protect key_keyowner = \"Xilinx\", key_keyname= \"xilinxt_2017_05\", key_method = \"rsa\", key_block\nvxYrgyihqymJKAP1U28sgDSyhejSTPCyoUjaqdt5WpBI9R20BcLbWe1TkPoIfiLoe5JcYoh8zcEy\n0EJbDuzXNpMlUsLCLACJKyYPFgeXm3JJjqNgDHxdT4SnSA+6wAkcS7u+0KKbWdDKoDGvhR0h8tUN\nw3uYUVG4qKcNbH3Lj2AtVob8BETwf+2i9aj1O6RkfV8/w5fzT6nAZbgaFIeP2n5jyxDhbzUod7zq\nvpH2JIlIoFJiS2SJPVXJnOMeLJjESPv4qaVrQETlfkJzB6BM+S9FHJwwyltBkbbw9lu2CJhM67vz\nXaH48z6tgRVlzhHMwLlMvbLnZdz9VLTy0g6N/A==\n\n`pragma protect control xilinx_configuration_visible = \"false\"\n`pragma protect control xilinx_enable_modification = \"false\"\n`pragma protect control xilinx_enable_probing = \"false\"\n`pragma protect end_toolblock=\"x+L9+fi2J1WDHSxBWt5lueyga5qkA+vDtQM6hMKDc1E=\"\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 2864)\n`pragma protect data_block\n5taEktq50cRsA2FFJCoSas6h/TCKO1CVAPgsswMGXGhqo89jI3VrZTh7SQbXb6QW5t0Qsr3Qm8UA\nLM3S186QWkudLr+GQUVrHMdLFhNN2Iq5q4wm4UTrtKDiZnG6U8shDJV0wIx6iPF0qWV6rxPoWmJM\n6vMB1J2dmpnHqjvaDEVjrjMJqeVARsfjyZPMkKdOsdZ4JABmvQlvkB3awwuePZ/fmtoQYjy7BiVQ\nbRykXvYs7Zcu7s/tZYAULiw+XT+bzD9F3+/dUBmOb4MDnJdEfide9Hjb07FrSGHJhYsigWpSnV7E\npLZ4k2SUT9FImUFhdq+2uH6qaY5jjJHtS4Azh4O5PagpjFuTrxngrBALm+RLx4yzWvnikosgRTGB\nuMC5E743faQ1fXmzhJtsYiCjNw2U1NgzTahU3gdIpPXG4ng23qPBlFBVPPw5CSTLsgkfN3+dLrAn\nseCaDcswFoN6ircxRELdg8PQ+VNXc7QQzTB1s3RuFigVLqu5YZ7VjSgJ7C1/Wb/RfJUEzEioMB3J\n73SSim6WfdSOUfzck+kREOv9ncUyCk2g3gvCSl9R9+TSJF/OHvAzegxI7s3b5DoYCnl4X5pJ5y8s\n5bbkLzpxFdhwxWXokP2GJ7hUY2TymJWPOw0yydphTXzfbDiITc6IeMeG18Fa3Y8JAtKPTMfoYKZz\nbf4KajYP0SWreoTpr/tsXqJfwXqDUgnAqeySH9cPyZmdocS5K8qxtT/tgDF4fb5DEQjv4bnxnZoo\nGGjJangAk+DKFm9EaqmJnySi/eiBQ+IjX7pS+71GFFQXAbyky0xUwD4p0bGfJNOOGyP2vi3OP2hC\nxWTgfnghzTlwZUa49zWoyqLYAxe0RadRXo1ktTwQcqAyWxPz6aUFnFyzC4WgJSVYb1/xUK0FAhCv\nAWBsqO14dK256a1t7Fk7oAJKwWa4KgXWnQkg2ks2IbiWn4NXCcN6+wOtCEBEq5ubcahtYD71iVvx\nikpW8w1LwDvsf4wC7E8Emk4/nRaYEvqnuDOXWFVox6O7psO7tY9cJs80XXDRROEXVEKSnbL1cS7H\nfMuMags3AHXr+ylq14rwmKgAJRDSR0u0R6nLbXEL6KM1NLXSOcUjw3/LXEWRnfAkj6Yf6ub/C+ER\nr2KYiyq5/doLwcVIyAojamSNmWPg6LeMnE48RIBnzUPm87UHajCzraztpiVzn85brW/qqydwYOZB\nWuIDmrAPelZvgSiOYKGeL0j764Idfi+zRHHehnKhelB4GJJBwt0EsFxZ0DOOz+PWUvp32JDsdXfx\n8uKmWb5Gma9ylHp5FSkVZsQbkn4PmzK72UwaUQFx1LvrQ+fi5DEUpDmkrkapEhBmsMq4dQ25arLt\nO2aGbF+w4SqF2IygkHe6GbTJH+2xO3ezQ9Z5nzQUBEcdyYSwos2WYy7VjSJHmtitPQjD432boeQj\njg24Vv4WttYBdXKyQNpclDyDVeXFS4YtFr1YVDFu+DYHKsYP2w4Axh62q65xeK3do1cTpT2nIVyB\nslqUvk13qIH1WWUDTXOLvHuGg7GgqVhRl17G1AhAR+ivzxvn+BN+6apWIb3oZH/1Ig8BbjkechJG\nyqWZcpCGrcEEOh3Ld/b4ZfvAlEAk1L3uvW1qNMTjyOn96iMj88mGfoULkQlA1ynrUxAvi/u4BBVE\n0AHUmX4S93UaltYkZJAjRbnhWZV5Flhd87wWnbGidmqd1mJmyS75csuA6vZ1JlNr3GEZqY1a69bG\n2F5MFJ3Zlcs8U8D7mdCMCBfZGjoQ7PCIBZ3bWKWTCHfko039pH0ilSTz4Vr/mcKh05hX+Nzcs8t9\nTSD6y1DMWKMEJgGMcZADjQsIcIzOBcqcXWnc7S0RY1blKGkNNBcDz+MWZgdd6sf+JZTej9sblrue\nkJQ8PZfHrbK61Cb9RK4+oZg4fPtdNsBDDhlga6DVDJb0DbTHRFpDvUMQwMRbFq9Lfty+lAElnf7u\nTa+/S+uc0Gn18671sm1/Oe6HYROdOG+x4YNCxlwU6VzICpEcv7dXYOZL0fdRa8VG957QeoZvgiuv\nQ6cbSXf/evWVXtN/snCnsmrF44kSZxMwYtKVBIYQVm1V/ve1c1kD8eMUGu4BCOykD0ma25e0BboL\nYTwhJTeVkRHsUP7tL87gLyqfsMB2TxYCeMhZ4Sp+AzB6wQVgg1dbgRarT5tx3gUH92pf+PXNrGxt\nMWSyPLnCk3GS7OXK1Sgod+pmzwtlyCGhypTVYNXmIWyZzmPro/zjFG4aeVZ2qpAO3Ep12/YiN3uZ\nojJqdDy3PXPAwq8TUFasbVWAxZGdkS4rrPFx4zIKCZJh4FzM/DgiVStDvn7sNB2ZOyhVlQEuksAl\nEek3OL9PBqkcKmjByLM0ykjFcuI1WXfw1cT/ntVWvLNsLWH7MI5/anG+Yh07FNNhOCRu0sWec8hV\nbutTOkBWjm5UUV4AJSSvRWhgJ+/FMjXPQUvEL8IkAdtZpwNCQmdbvS5VmKMFC/4DTCHOnqpVQ+T2\nsIkWpbPqUrHSM4Af06D2PeiKHgI+Xl/rBmNLI/Lij142EAhapTf8U8ct61FEUupggAmQfjO7ijtM\n5xtKWVMnymCXH30kUgqzjmuBK/+o3a4kkmzMs0KzWMGJA45gM7N/K0FywSBBEJdIqG54fW6IsbpW\nm/Z6iOXVPFnDIg04hh8ny5B1XrGmsg/5hECNTDIj0iIzI7CKr8sE4dN8phQrwMlKQ53rOCdzuvTi\nCYLgF9GBa/NEFw0Jut2nHn90X2AITHpM4tRgGTDoWcJUQkKxhvoKFKogeo4S4OiPan/VuG96vvoy\n5vJwvqHNIGqEjrraUCHfSTRhmOAhMsndoJUbMeS1Yu+2fUCzp07aypRaA/+nXUEyP1wn6/h2sp+f\nrpc39ww6BK/ozcBRNVYth38sf3ql7ZbSsErm+Exbq2tivUVp5DsR1P//Kj1H6lPUkbPVj2kDvwTi\nzF+S+T+6rS18i/vKYqz7rggdQRX9xoYvw1as4tCRQSs3wSsgW17YzPW1L74LqgZMbMbPKQxJio3G\nlFcbHQdHNt80DX9wqDu++zDI9mF7CC/s6jxnZL5WNXmlxwXD8RQXQKl//K7pKN/LO2qxAWCqGzOh\nQq00M8IpLWaFMqpIDGS8oZQWIh74sPqstcpgTJN6vXMtSrvdSjrPxsgxEiVPbLbXCIduWyanCJnX\nJ2eFxR1N9hshNBNOPi9mrLlHOXUROpVkvvKMXMNCpeCoYRtXVZiBh0GXesz/kLYTYSSqQNjlKW4u\nIg8hXlP1uGW34eyrd7uifQpwQUHSLvXn18f1ldLYH9XoLp3qElinpFPm6dp1hTcNPtFULXYK64Fj\na+92yCnj7/stq+5UuDereuLSe3icjDZYIBo8Oz3YwHP9bOe+GWanG+AtuPqE1bU+k6OsMuuCkbAz\nv7MEUbMSxKQDzzq4ObJeu3pwHw6U6/UAzSdLtJiZ6bU2r2XrSkwW15/v3+Ren7nEXjUQSEReo2Fj\n31H8jinz+FpmNhEe2mhFIg0vbkzIznHJwIjrqNAVsX6LejMxubwI/TvbcgQruQvR4nMmlBV0txet\nl2fcLkt33a3wMFaS1i0GmjfY0zbZN0NaEPwO6xYKe4zIy99cJ/mIJT9KTHbyWd5JB2MaI3Hrue3N\nP0R+NXDfASQi/zgWQ76EuyLK8F3RDXC/PNpi5KlHxPgiac3aTNUAUp5Lr461CY4gk97xV68zDyOD\nFl/rZwacKC5ffSrSDC0RXeIpN4Mw1zRSBCvMnATTxknYmpVnbU/gP+6VgFVKlINOrTv2AOjbNIr1\nUvDXqRks7iP9II8C2V8=\n`pragma protect end_protected\n", "num_lines": 81}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020\n//Date        : Wed Dec 15 00:42:23 2021\n//Host        : a-21awsprq4sria running 64-bit Amazon Linux release 2 (Karoo)\n//Command     : generate_target cl_axi_interconnect_wrapper.bd\n//Design      : cl_axi_interconnect_wrapper\n//Purpose     : IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule cl_axi_interconnect_wrapper\n   (ACLK,\n    ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  input ACLK;\n  input ARESETN;\n  output [63:0]M00_AXI_araddr;\n  output [1:0]M00_AXI_arburst;\n  output [3:0]M00_AXI_arcache;\n  output [6:0]M00_AXI_arid;\n  output [7:0]M00_AXI_arlen;\n  output [0:0]M00_AXI_arlock;\n  output [2:0]M00_AXI_arprot;\n  output [3:0]M00_AXI_arqos;\n  input M00_AXI_arready;\n  output [3:0]M00_AXI_arregion;\n  output [2:0]M00_AXI_arsize;\n  output M00_AXI_arvalid;\n  output [63:0]M00_AXI_awaddr;\n  output [1:0]M00_AXI_awburst;\n  output [3:0]M00_AXI_awcache;\n  output [6:0]M00_AXI_awid;\n  output [7:0]M00_AXI_awlen;\n  output [0:0]M00_AXI_awlock;\n  output [2:0]M00_AXI_awprot;\n  output [3:0]M00_AXI_awqos;\n  input M00_AXI_awready;\n  output [3:0]M00_AXI_awregion;\n  output [2:0]M00_AXI_awsize;\n  output M00_AXI_awvalid;\n  input [6:0]M00_AXI_bid;\n  output M00_AXI_bready;\n  input [1:0]M00_AXI_bresp;\n  input M00_AXI_bvalid;\n  input [511:0]M00_AXI_rdata;\n  input [6:0]M00_AXI_rid;\n  input M00_AXI_rlast;\n  output M00_AXI_rready;\n  input [1:0]M00_AXI_rresp;\n  input M00_AXI_rvalid;\n  output [511:0]M00_AXI_wdata;\n  output M00_AXI_wlast;\n  input M00_AXI_wready;\n  output [63:0]M00_AXI_wstrb;\n  output M00_AXI_wvalid;\n  output [63:0]M01_AXI_araddr;\n  output [1:0]M01_AXI_arburst;\n  output [3:0]M01_AXI_arcache;\n  output [6:0]M01_AXI_arid;\n  output [7:0]M01_AXI_arlen;\n  output [0:0]M01_AXI_arlock;\n  output [2:0]M01_AXI_arprot;\n  output [3:0]M01_AXI_arqos;\n  input M01_AXI_arready;\n  output [3:0]M01_AXI_arregion;\n  output [2:0]M01_AXI_arsize;\n  output M01_AXI_arvalid;\n  output [63:0]M01_AXI_awaddr;\n  output [1:0]M01_AXI_awburst;\n  output [3:0]M01_AXI_awcache;\n  output [6:0]M01_AXI_awid;\n  output [7:0]M01_AXI_awlen;\n  output [0:0]M01_AXI_awlock;\n  output [2:0]M01_AXI_awprot;\n  output [3:0]M01_AXI_awqos;\n  input M01_AXI_awready;\n  output [3:0]M01_AXI_awregion;\n  output [2:0]M01_AXI_awsize;\n  output M01_AXI_awvalid;\n  input [6:0]M01_AXI_bid;\n  output M01_AXI_bready;\n  input [1:0]M01_AXI_bresp;\n  input M01_AXI_bvalid;\n  input [511:0]M01_AXI_rdata;\n  input [6:0]M01_AXI_rid;\n  input M01_AXI_rlast;\n  output M01_AXI_rready;\n  input [1:0]M01_AXI_rresp;\n  input M01_AXI_rvalid;\n  output [511:0]M01_AXI_wdata;\n  output M01_AXI_wlast;\n  input M01_AXI_wready;\n  output [63:0]M01_AXI_wstrb;\n  output M01_AXI_wvalid;\n  output [63:0]M02_AXI_araddr;\n  output [1:0]M02_AXI_arburst;\n  output [3:0]M02_AXI_arcache;\n  output [6:0]M02_AXI_arid;\n  output [7:0]M02_AXI_arlen;\n  output [0:0]M02_AXI_arlock;\n  output [2:0]M02_AXI_arprot;\n  output [3:0]M02_AXI_arqos;\n  input M02_AXI_arready;\n  output [3:0]M02_AXI_arregion;\n  output [2:0]M02_AXI_arsize;\n  output M02_AXI_arvalid;\n  output [63:0]M02_AXI_awaddr;\n  output [1:0]M02_AXI_awburst;\n  output [3:0]M02_AXI_awcache;\n  output [6:0]M02_AXI_awid;\n  output [7:0]M02_AXI_awlen;\n  output [0:0]M02_AXI_awlock;\n  output [2:0]M02_AXI_awprot;\n  output [3:0]M02_AXI_awqos;\n  input M02_AXI_awready;\n  output [3:0]M02_AXI_awregion;\n  output [2:0]M02_AXI_awsize;\n  output M02_AXI_awvalid;\n  input [6:0]M02_AXI_bid;\n  output M02_AXI_bready;\n  input [1:0]M02_AXI_bresp;\n  input M02_AXI_bvalid;\n  input [511:0]M02_AXI_rdata;\n  input [6:0]M02_AXI_rid;\n  input M02_AXI_rlast;\n  output M02_AXI_rready;\n  input [1:0]M02_AXI_rresp;\n  input M02_AXI_rvalid;\n  output [511:0]M02_AXI_wdata;\n  output M02_AXI_wlast;\n  input M02_AXI_wready;\n  output [63:0]M02_AXI_wstrb;\n  output M02_AXI_wvalid;\n  output [63:0]M03_AXI_araddr;\n  output [1:0]M03_AXI_arburst;\n  output [3:0]M03_AXI_arcache;\n  output [6:0]M03_AXI_arid;\n  output [7:0]M03_AXI_arlen;\n  output [0:0]M03_AXI_arlock;\n  output [2:0]M03_AXI_arprot;\n  output [3:0]M03_AXI_arqos;\n  input M03_AXI_arready;\n  output [3:0]M03_AXI_arregion;\n  output [2:0]M03_AXI_arsize;\n  output M03_AXI_arvalid;\n  output [63:0]M03_AXI_awaddr;\n  output [1:0]M03_AXI_awburst;\n  output [3:0]M03_AXI_awcache;\n  output [6:0]M03_AXI_awid;\n  output [7:0]M03_AXI_awlen;\n  output [0:0]M03_AXI_awlock;\n  output [2:0]M03_AXI_awprot;\n  output [3:0]M03_AXI_awqos;\n  input M03_AXI_awready;\n  output [3:0]M03_AXI_awregion;\n  output [2:0]M03_AXI_awsize;\n  output M03_AXI_awvalid;\n  input [6:0]M03_AXI_bid;\n  output M03_AXI_bready;\n  input [1:0]M03_AXI_bresp;\n  input M03_AXI_bvalid;\n  input [511:0]M03_AXI_rdata;\n  input [6:0]M03_AXI_rid;\n  input M03_AXI_rlast;\n  output M03_AXI_rready;\n  input [1:0]M03_AXI_rresp;\n  input M03_AXI_rvalid;\n  output [511:0]M03_AXI_wdata;\n  output M03_AXI_wlast;\n  input M03_AXI_wready;\n  output [63:0]M03_AXI_wstrb;\n  output M03_AXI_wvalid;\n  input [63:0]S00_AXI_araddr;\n  input [1:0]S00_AXI_arburst;\n  input [3:0]S00_AXI_arcache;\n  input [5:0]S00_AXI_arid;\n  input [7:0]S00_AXI_arlen;\n  input [0:0]S00_AXI_arlock;\n  input [2:0]S00_AXI_arprot;\n  input [3:0]S00_AXI_arqos;\n  output S00_AXI_arready;\n  input [3:0]S00_AXI_arregion;\n  input [2:0]S00_AXI_arsize;\n  input S00_AXI_arvalid;\n  input [63:0]S00_AXI_awaddr;\n  input [1:0]S00_AXI_awburst;\n  input [3:0]S00_AXI_awcache;\n  input [5:0]S00_AXI_awid;\n  input [7:0]S00_AXI_awlen;\n  input [0:0]S00_AXI_awlock;\n  input [2:0]S00_AXI_awprot;\n  input [3:0]S00_AXI_awqos;\n  output S00_AXI_awready;\n  input [3:0]S00_AXI_awregion;\n  input [2:0]S00_AXI_awsize;\n  input S00_AXI_awvalid;\n  output [5:0]S00_AXI_bid;\n  input S00_AXI_bready;\n  output [1:0]S00_AXI_bresp;\n  output S00_AXI_bvalid;\n  output [511:0]S00_AXI_rdata;\n  output [5:0]S00_AXI_rid;\n  output S00_AXI_rlast;\n  input S00_AXI_rready;\n  output [1:0]S00_AXI_rresp;\n  output S00_AXI_rvalid;\n  input [511:0]S00_AXI_wdata;\n  input S00_AXI_wlast;\n  output S00_AXI_wready;\n  input [63:0]S00_AXI_wstrb;\n  input S00_AXI_wvalid;\n  input [63:0]S01_AXI_araddr;\n  input [1:0]S01_AXI_arburst;\n  input [3:0]S01_AXI_arcache;\n  input [5:0]S01_AXI_arid;\n  input [7:0]S01_AXI_arlen;\n  input [0:0]S01_AXI_arlock;\n  input [2:0]S01_AXI_arprot;\n  input [3:0]S01_AXI_arqos;\n  output S01_AXI_arready;\n  input [3:0]S01_AXI_arregion;\n  input [2:0]S01_AXI_arsize;\n  input S01_AXI_arvalid;\n  input [63:0]S01_AXI_awaddr;\n  input [1:0]S01_AXI_awburst;\n  input [3:0]S01_AXI_awcache;\n  input [5:0]S01_AXI_awid;\n  input [7:0]S01_AXI_awlen;\n  input [0:0]S01_AXI_awlock;\n  input [2:0]S01_AXI_awprot;\n  input [3:0]S01_AXI_awqos;\n  output S01_AXI_awready;\n  input [3:0]S01_AXI_awregion;\n  input [2:0]S01_AXI_awsize;\n  input S01_AXI_awvalid;\n  output [5:0]S01_AXI_bid;\n  input S01_AXI_bready;\n  output [1:0]S01_AXI_bresp;\n  output S01_AXI_bvalid;\n  output [511:0]S01_AXI_rdata;\n  output [5:0]S01_AXI_rid;\n  output S01_AXI_rlast;\n  input S01_AXI_rready;\n  output [1:0]S01_AXI_rresp;\n  output S01_AXI_rvalid;\n  input [511:0]S01_AXI_wdata;\n  input S01_AXI_wlast;\n  output S01_AXI_wready;\n  input [63:0]S01_AXI_wstrb;\n  input S01_AXI_wvalid;\n\n  wire ACLK;\n  wire ARESETN;\n  wire [63:0]M00_AXI_araddr;\n  wire [1:0]M00_AXI_arburst;\n  wire [3:0]M00_AXI_arcache;\n  wire [6:0]M00_AXI_arid;\n  wire [7:0]M00_AXI_arlen;\n  wire [0:0]M00_AXI_arlock;\n  wire [2:0]M00_AXI_arprot;\n  wire [3:0]M00_AXI_arqos;\n  wire M00_AXI_arready;\n  wire [3:0]M00_AXI_arregion;\n  wire [2:0]M00_AXI_arsize;\n  wire M00_AXI_arvalid;\n  wire [63:0]M00_AXI_awaddr;\n  wire [1:0]M00_AXI_awburst;\n  wire [3:0]M00_AXI_awcache;\n  wire [6:0]M00_AXI_awid;\n  wire [7:0]M00_AXI_awlen;\n  wire [0:0]M00_AXI_awlock;\n  wire [2:0]M00_AXI_awprot;\n  wire [3:0]M00_AXI_awqos;\n  wire M00_AXI_awready;\n  wire [3:0]M00_AXI_awregion;\n  wire [2:0]M00_AXI_awsize;\n  wire M00_AXI_awvalid;\n  wire [6:0]M00_AXI_bid;\n  wire M00_AXI_bready;\n  wire [1:0]M00_AXI_bresp;\n  wire M00_AXI_bvalid;\n  wire [511:0]M00_AXI_rdata;\n  wire [6:0]M00_AXI_rid;\n  wire M00_AXI_rlast;\n  wire M00_AXI_rready;\n  wire [1:0]M00_AXI_rresp;\n  wire M00_AXI_rvalid;\n  wire [511:0]M00_AXI_wdata;\n  wire M00_AXI_wlast;\n  wire M00_AXI_wready;\n  wire [63:0]M00_AXI_wstrb;\n  wire M00_AXI_wvalid;\n  wire [63:0]M01_AXI_araddr;\n  wire [1:0]M01_AXI_arburst;\n  wire [3:0]M01_AXI_arcache;\n  wire [6:0]M01_AXI_arid;\n  wire [7:0]M01_AXI_arlen;\n  wire [0:0]M01_AXI_arlock;\n  wire [2:0]M01_AXI_arprot;\n  wire [3:0]M01_AXI_arqos;\n  wire M01_AXI_arready;\n  wire [3:0]M01_AXI_arregion;\n  wire [2:0]M01_AXI_arsize;\n  wire M01_AXI_arvalid;\n  wire [63:0]M01_AXI_awaddr;\n  wire [1:0]M01_AXI_awburst;\n  wire [3:0]M01_AXI_awcache;\n  wire [6:0]M01_AXI_awid;\n  wire [7:0]M01_AXI_awlen;\n  wire [0:0]M01_AXI_awlock;\n  wire [2:0]M01_AXI_awprot;\n  wire [3:0]M01_AXI_awqos;\n  wire M01_AXI_awready;\n  wire [3:0]M01_AXI_awregion;\n  wire [2:0]M01_AXI_awsize;\n  wire M01_AXI_awvalid;\n  wire [6:0]M01_AXI_bid;\n  wire M01_AXI_bready;\n  wire [1:0]M01_AXI_bresp;\n  wire M01_AXI_bvalid;\n  wire [511:0]M01_AXI_rdata;\n  wire [6:0]M01_AXI_rid;\n  wire M01_AXI_rlast;\n  wire M01_AXI_rready;\n  wire [1:0]M01_AXI_rresp;\n  wire M01_AXI_rvalid;\n  wire [511:0]M01_AXI_wdata;\n  wire M01_AXI_wlast;\n  wire M01_AXI_wready;\n  wire [63:0]M01_AXI_wstrb;\n  wire M01_AXI_wvalid;\n  wire [63:0]M02_AXI_araddr;\n  wire [1:0]M02_AXI_arburst;\n  wire [3:0]M02_AXI_arcache;\n  wire [6:0]M02_AXI_arid;\n  wire [7:0]M02_AXI_arlen;\n  wire [0:0]M02_AXI_arlock;\n  wire [2:0]M02_AXI_arprot;\n  wire [3:0]M02_AXI_arqos;\n  wire M02_AXI_arready;\n  wire [3:0]M02_AXI_arregion;\n  wire [2:0]M02_AXI_arsize;\n  wire M02_AXI_arvalid;\n  wire [63:0]M02_AXI_awaddr;\n  wire [1:0]M02_AXI_awburst;\n  wire [3:0]M02_AXI_awcache;\n  wire [6:0]M02_AXI_awid;\n  wire [7:0]M02_AXI_awlen;\n  wire [0:0]M02_AXI_awlock;\n  wire [2:0]M02_AXI_awprot;\n  wire [3:0]M02_AXI_awqos;\n  wire M02_AXI_awready;\n  wire [3:0]M02_AXI_awregion;\n  wire [2:0]M02_AXI_awsize;\n  wire M02_AXI_awvalid;\n  wire [6:0]M02_AXI_bid;\n  wire M02_AXI_bready;\n  wire [1:0]M02_AXI_bresp;\n  wire M02_AXI_bvalid;\n  wire [511:0]M02_AXI_rdata;\n  wire [6:0]M02_AXI_rid;\n  wire M02_AXI_rlast;\n  wire M02_AXI_rready;\n  wire [1:0]M02_AXI_rresp;\n  wire M02_AXI_rvalid;\n  wire [511:0]M02_AXI_wdata;\n  wire M02_AXI_wlast;\n  wire M02_AXI_wready;\n  wire [63:0]M02_AXI_wstrb;\n  wire M02_AXI_wvalid;\n  wire [63:0]M03_AXI_araddr;\n  wire [1:0]M03_AXI_arburst;\n  wire [3:0]M03_AXI_arcache;\n  wire [6:0]M03_AXI_arid;\n  wire [7:0]M03_AXI_arlen;\n  wire [0:0]M03_AXI_arlock;\n  wire [2:0]M03_AXI_arprot;\n  wire [3:0]M03_AXI_arqos;\n  wire M03_AXI_arready;\n  wire [3:0]M03_AXI_arregion;\n  wire [2:0]M03_AXI_arsize;\n  wire M03_AXI_arvalid;\n  wire [63:0]M03_AXI_awaddr;\n  wire [1:0]M03_AXI_awburst;\n  wire [3:0]M03_AXI_awcache;\n  wire [6:0]M03_AXI_awid;\n  wire [7:0]M03_AXI_awlen;\n  wire [0:0]M03_AXI_awlock;\n  wire [2:0]M03_AXI_awprot;\n  wire [3:0]M03_AXI_awqos;\n  wire M03_AXI_awready;\n  wire [3:0]M03_AXI_awregion;\n  wire [2:0]M03_AXI_awsize;\n  wire M03_AXI_awvalid;\n  wire [6:0]M03_AXI_bid;\n  wire M03_AXI_bready;\n  wire [1:0]M03_AXI_bresp;\n  wire M03_AXI_bvalid;\n  wire [511:0]M03_AXI_rdata;\n  wire [6:0]M03_AXI_rid;\n  wire M03_AXI_rlast;\n  wire M03_AXI_rready;\n  wire [1:0]M03_AXI_rresp;\n  wire M03_AXI_rvalid;\n  wire [511:0]M03_AXI_wdata;\n  wire M03_AXI_wlast;\n  wire M03_AXI_wready;\n  wire [63:0]M03_AXI_wstrb;\n  wire M03_AXI_wvalid;\n  wire [63:0]S00_AXI_araddr;\n  wire [1:0]S00_AXI_arburst;\n  wire [3:0]S00_AXI_arcache;\n  wire [5:0]S00_AXI_arid;\n  wire [7:0]S00_AXI_arlen;\n  wire [0:0]S00_AXI_arlock;\n  wire [2:0]S00_AXI_arprot;\n  wire [3:0]S00_AXI_arqos;\n  wire S00_AXI_arready;\n  wire [3:0]S00_AXI_arregion;\n  wire [2:0]S00_AXI_arsize;\n  wire S00_AXI_arvalid;\n  wire [63:0]S00_AXI_awaddr;\n  wire [1:0]S00_AXI_awburst;\n  wire [3:0]S00_AXI_awcache;\n  wire [5:0]S00_AXI_awid;\n  wire [7:0]S00_AXI_awlen;\n  wire [0:0]S00_AXI_awlock;\n  wire [2:0]S00_AXI_awprot;\n  wire [3:0]S00_AXI_awqos;\n  wire S00_AXI_awready;\n  wire [3:0]S00_AXI_awregion;\n  wire [2:0]S00_AXI_awsize;\n  wire S00_AXI_awvalid;\n  wire [5:0]S00_AXI_bid;\n  wire S00_AXI_bready;\n  wire [1:0]S00_AXI_bresp;\n  wire S00_AXI_bvalid;\n  wire [511:0]S00_AXI_rdata;\n  wire [5:0]S00_AXI_rid;\n  wire S00_AXI_rlast;\n  wire S00_AXI_rready;\n  wire [1:0]S00_AXI_rresp;\n  wire S00_AXI_rvalid;\n  wire [511:0]S00_AXI_wdata;\n  wire S00_AXI_wlast;\n  wire S00_AXI_wready;\n  wire [63:0]S00_AXI_wstrb;\n  wire S00_AXI_wvalid;\n  wire [63:0]S01_AXI_araddr;\n  wire [1:0]S01_AXI_arburst;\n  wire [3:0]S01_AXI_arcache;\n  wire [5:0]S01_AXI_arid;\n  wire [7:0]S01_AXI_arlen;\n  wire [0:0]S01_AXI_arlock;\n  wire [2:0]S01_AXI_arprot;\n  wire [3:0]S01_AXI_arqos;\n  wire S01_AXI_arready;\n  wire [3:0]S01_AXI_arregion;\n  wire [2:0]S01_AXI_arsize;\n  wire S01_AXI_arvalid;\n  wire [63:0]S01_AXI_awaddr;\n  wire [1:0]S01_AXI_awburst;\n  wire [3:0]S01_AXI_awcache;\n  wire [5:0]S01_AXI_awid;\n  wire [7:0]S01_AXI_awlen;\n  wire [0:0]S01_AXI_awlock;\n  wire [2:0]S01_AXI_awprot;\n  wire [3:0]S01_AXI_awqos;\n  wire S01_AXI_awready;\n  wire [3:0]S01_AXI_awregion;\n  wire [2:0]S01_AXI_awsize;\n  wire S01_AXI_awvalid;\n  wire [5:0]S01_AXI_bid;\n  wire S01_AXI_bready;\n  wire [1:0]S01_AXI_bresp;\n  wire S01_AXI_bvalid;\n  wire [511:0]S01_AXI_rdata;\n  wire [5:0]S01_AXI_rid;\n  wire S01_AXI_rlast;\n  wire S01_AXI_rready;\n  wire [1:0]S01_AXI_rresp;\n  wire S01_AXI_rvalid;\n  wire [511:0]S01_AXI_wdata;\n  wire S01_AXI_wlast;\n  wire S01_AXI_wready;\n  wire [63:0]S01_AXI_wstrb;\n  wire S01_AXI_wvalid;\n\n  cl_axi_interconnect cl_axi_interconnect_i\n       (.ACLK(ACLK),\n        .ARESETN(ARESETN),\n        .M00_AXI_araddr(M00_AXI_araddr),\n        .M00_AXI_arburst(M00_AXI_arburst),\n        .M00_AXI_arcache(M00_AXI_arcache),\n        .M00_AXI_arid(M00_AXI_arid),\n        .M00_AXI_arlen(M00_AXI_arlen),\n        .M00_AXI_arlock(M00_AXI_arlock),\n        .M00_AXI_arprot(M00_AXI_arprot),\n        .M00_AXI_arqos(M00_AXI_arqos),\n        .M00_AXI_arready(M00_AXI_arready),\n        .M00_AXI_arregion(M00_AXI_arregion),\n        .M00_AXI_arsize(M00_AXI_arsize),\n        .M00_AXI_arvalid(M00_AXI_arvalid),\n        .M00_AXI_awaddr(M00_AXI_awaddr),\n        .M00_AXI_awburst(M00_AXI_awburst),\n        .M00_AXI_awcache(M00_AXI_awcache),\n        .M00_AXI_awid(M00_AXI_awid),\n        .M00_AXI_awlen(M00_AXI_awlen),\n        .M00_AXI_awlock(M00_AXI_awlock),\n        .M00_AXI_awprot(M00_AXI_awprot),\n        .M00_AXI_awqos(M00_AXI_awqos),\n        .M00_AXI_awready(M00_AXI_awready),\n        .M00_AXI_awregion(M00_AXI_awregion),\n        .M00_AXI_awsize(M00_AXI_awsize),\n        .M00_AXI_awvalid(M00_AXI_awvalid),\n        .M00_AXI_bid(M00_AXI_bid),\n        .M00_AXI_bready(M00_AXI_bready),\n        .M00_AXI_bresp(M00_AXI_bresp),\n        .M00_AXI_bvalid(M00_AXI_bvalid),\n        .M00_AXI_rdata(M00_AXI_rdata),\n        .M00_AXI_rid(M00_AXI_rid),\n        .M00_AXI_rlast(M00_AXI_rlast),\n        .M00_AXI_rready(M00_AXI_rready),\n        .M00_AXI_rresp(M00_AXI_rresp),\n        .M00_AXI_rvalid(M00_AXI_rvalid),\n        .M00_AXI_wdata(M00_AXI_wdata),\n        .M00_AXI_wlast(M00_AXI_wlast),\n        .M00_AXI_wready(M00_AXI_wready),\n        .M00_AXI_wstrb(M00_AXI_wstrb),\n        .M00_AXI_wvalid(M00_AXI_wvalid),\n        .M01_AXI_araddr(M01_AXI_araddr),\n        .M01_AXI_arburst(M01_AXI_arburst),\n        .M01_AXI_arcache(M01_AXI_arcache),\n        .M01_AXI_arid(M01_AXI_arid),\n        .M01_AXI_arlen(M01_AXI_arlen),\n        .M01_AXI_arlock(M01_AXI_arlock),\n        .M01_AXI_arprot(M01_AXI_arprot),\n        .M01_AXI_arqos(M01_AXI_arqos),\n        .M01_AXI_arready(M01_AXI_arready),\n        .M01_AXI_arregion(M01_AXI_arregion),\n        .M01_AXI_arsize(M01_AXI_arsize),\n        .M01_AXI_arvalid(M01_AXI_arvalid),\n        .M01_AXI_awaddr(M01_AXI_awaddr),\n        .M01_AXI_awburst(M01_AXI_awburst),\n        .M01_AXI_awcache(M01_AXI_awcache),\n        .M01_AXI_awid(M01_AXI_awid),\n        .M01_AXI_awlen(M01_AXI_awlen),\n        .M01_AXI_awlock(M01_AXI_awlock),\n        .M01_AXI_awprot(M01_AXI_awprot),\n        .M01_AXI_awqos(M01_AXI_awqos),\n        .M01_AXI_awready(M01_AXI_awready),\n        .M01_AXI_awregion(M01_AXI_awregion),\n        .M01_AXI_awsize(M01_AXI_awsize),\n        .M01_AXI_awvalid(M01_AXI_awvalid),\n        .M01_AXI_bid(M01_AXI_bid),\n        .M01_AXI_bready(M01_AXI_bready),\n        .M01_AXI_bresp(M01_AXI_bresp),\n        .M01_AXI_bvalid(M01_AXI_bvalid),\n        .M01_AXI_rdata(M01_AXI_rdata),\n        .M01_AXI_rid(M01_AXI_rid),\n        .M01_AXI_rlast(M01_AXI_rlast),\n        .M01_AXI_rready(M01_AXI_rready),\n        .M01_AXI_rresp(M01_AXI_rresp),\n        .M01_AXI_rvalid(M01_AXI_rvalid),\n        .M01_AXI_wdata(M01_AXI_wdata),\n        .M01_AXI_wlast(M01_AXI_wlast),\n        .M01_AXI_wready(M01_AXI_wready),\n        .M01_AXI_wstrb(M01_AXI_wstrb),\n        .M01_AXI_wvalid(M01_AXI_wvalid),\n        .M02_AXI_araddr(M02_AXI_araddr),\n        .M02_AXI_arburst(M02_AXI_arburst),\n        .M02_AXI_arcache(M02_AXI_arcache),\n        .M02_AXI_arid(M02_AXI_arid),\n        .M02_AXI_arlen(M02_AXI_arlen),\n        .M02_AXI_arlock(M02_AXI_arlock),\n        .M02_AXI_arprot(M02_AXI_arprot),\n        .M02_AXI_arqos(M02_AXI_arqos),\n        .M02_AXI_arready(M02_AXI_arready),\n        .M02_AXI_arregion(M02_AXI_arregion),\n        .M02_AXI_arsize(M02_AXI_arsize),\n        .M02_AXI_arvalid(M02_AXI_arvalid),\n        .M02_AXI_awaddr(M02_AXI_awaddr),\n        .M02_AXI_awburst(M02_AXI_awburst),\n        .M02_AXI_awcache(M02_AXI_awcache),\n        .M02_AXI_awid(M02_AXI_awid),\n        .M02_AXI_awlen(M02_AXI_awlen),\n        .M02_AXI_awlock(M02_AXI_awlock),\n        .M02_AXI_awprot(M02_AXI_awprot),\n        .M02_AXI_awqos(M02_AXI_awqos),\n        .M02_AXI_awready(M02_AXI_awready),\n        .M02_AXI_awregion(M02_AXI_awregion),\n        .M02_AXI_awsize(M02_AXI_awsize),\n        .M02_AXI_awvalid(M02_AXI_awvalid),\n        .M02_AXI_bid(M02_AXI_bid),\n        .M02_AXI_bready(M02_AXI_bready),\n        .M02_AXI_bresp(M02_AXI_bresp),\n        .M02_AXI_bvalid(M02_AXI_bvalid),\n        .M02_AXI_rdata(M02_AXI_rdata),\n        .M02_AXI_rid(M02_AXI_rid),\n        .M02_AXI_rlast(M02_AXI_rlast),\n        .M02_AXI_rready(M02_AXI_rready),\n        .M02_AXI_rresp(M02_AXI_rresp),\n        .M02_AXI_rvalid(M02_AXI_rvalid),\n        .M02_AXI_wdata(M02_AXI_wdata),\n        .M02_AXI_wlast(M02_AXI_wlast),\n        .M02_AXI_wready(M02_AXI_wready),\n        .M02_AXI_wstrb(M02_AXI_wstrb),\n        .M02_AXI_wvalid(M02_AXI_wvalid),\n        .M03_AXI_araddr(M03_AXI_araddr),\n        .M03_AXI_arburst(M03_AXI_arburst),\n        .M03_AXI_arcache(M03_AXI_arcache),\n        .M03_AXI_arid(M03_AXI_arid),\n        .M03_AXI_arlen(M03_AXI_arlen),\n        .M03_AXI_arlock(M03_AXI_arlock),\n        .M03_AXI_arprot(M03_AXI_arprot),\n        .M03_AXI_arqos(M03_AXI_arqos),\n        .M03_AXI_arready(M03_AXI_arready),\n        .M03_AXI_arregion(M03_AXI_arregion),\n        .M03_AXI_arsize(M03_AXI_arsize),\n        .M03_AXI_arvalid(M03_AXI_arvalid),\n        .M03_AXI_awaddr(M03_AXI_awaddr),\n        .M03_AXI_awburst(M03_AXI_awburst),\n        .M03_AXI_awcache(M03_AXI_awcache),\n        .M03_AXI_awid(M03_AXI_awid),\n        .M03_AXI_awlen(M03_AXI_awlen),\n        .M03_AXI_awlock(M03_AXI_awlock),\n        .M03_AXI_awprot(M03_AXI_awprot),\n        .M03_AXI_awqos(M03_AXI_awqos),\n        .M03_AXI_awready(M03_AXI_awready),\n        .M03_AXI_awregion(M03_AXI_awregion),\n        .M03_AXI_awsize(M03_AXI_awsize),\n        .M03_AXI_awvalid(M03_AXI_awvalid),\n        .M03_AXI_bid(M03_AXI_bid),\n        .M03_AXI_bready(M03_AXI_bready),\n        .M03_AXI_bresp(M03_AXI_bresp),\n        .M03_AXI_bvalid(M03_AXI_bvalid),\n        .M03_AXI_rdata(M03_AXI_rdata),\n        .M03_AXI_rid(M03_AXI_rid),\n        .M03_AXI_rlast(M03_AXI_rlast),\n        .M03_AXI_rready(M03_AXI_rready),\n        .M03_AXI_rresp(M03_AXI_rresp),\n        .M03_AXI_rvalid(M03_AXI_rvalid),\n        .M03_AXI_wdata(M03_AXI_wdata),\n        .M03_AXI_wlast(M03_AXI_wlast),\n        .M03_AXI_wready(M03_AXI_wready),\n        .M03_AXI_wstrb(M03_AXI_wstrb),\n        .M03_AXI_wvalid(M03_AXI_wvalid),\n        .S00_AXI_araddr(S00_AXI_araddr),\n        .S00_AXI_arburst(S00_AXI_arburst),\n        .S00_AXI_arcache(S00_AXI_arcache),\n        .S00_AXI_arid(S00_AXI_arid),\n        .S00_AXI_arlen(S00_AXI_arlen),\n        .S00_AXI_arlock(S00_AXI_arlock),\n        .S00_AXI_arprot(S00_AXI_arprot),\n        .S00_AXI_arqos(S00_AXI_arqos),\n        .S00_AXI_arready(S00_AXI_arready),\n        .S00_AXI_arregion(S00_AXI_arregion),\n        .S00_AXI_arsize(S00_AXI_arsize),\n        .S00_AXI_arvalid(S00_AXI_arvalid),\n        .S00_AXI_awaddr(S00_AXI_awaddr),\n        .S00_AXI_awburst(S00_AXI_awburst),\n        .S00_AXI_awcache(S00_AXI_awcache),\n        .S00_AXI_awid(S00_AXI_awid),\n        .S00_AXI_awlen(S00_AXI_awlen),\n        .S00_AXI_awlock(S00_AXI_awlock),\n        .S00_AXI_awprot(S00_AXI_awprot),\n        .S00_AXI_awqos(S00_AXI_awqos),\n        .S00_AXI_awready(S00_AXI_awready),\n        .S00_AXI_awregion(S00_AXI_awregion),\n        .S00_AXI_awsize(S00_AXI_awsize),\n        .S00_AXI_awvalid(S00_AXI_awvalid),\n        .S00_AXI_bid(S00_AXI_bid),\n        .S00_AXI_bready(S00_AXI_bready),\n        .S00_AXI_bresp(S00_AXI_bresp),\n        .S00_AXI_bvalid(S00_AXI_bvalid),\n        .S00_AXI_rdata(S00_AXI_rdata),\n        .S00_AXI_rid(S00_AXI_rid),\n        .S00_AXI_rlast(S00_AXI_rlast),\n        .S00_AXI_rready(S00_AXI_rready),\n        .S00_AXI_rresp(S00_AXI_rresp),\n        .S00_AXI_rvalid(S00_AXI_rvalid),\n        .S00_AXI_wdata(S00_AXI_wdata),\n        .S00_AXI_wlast(S00_AXI_wlast),\n        .S00_AXI_wready(S00_AXI_wready),\n        .S00_AXI_wstrb(S00_AXI_wstrb),\n        .S00_AXI_wvalid(S00_AXI_wvalid),\n        .S01_AXI_araddr(S01_AXI_araddr),\n        .S01_AXI_arburst(S01_AXI_arburst),\n        .S01_AXI_arcache(S01_AXI_arcache),\n        .S01_AXI_arid(S01_AXI_arid),\n        .S01_AXI_arlen(S01_AXI_arlen),\n        .S01_AXI_arlock(S01_AXI_arlock),\n        .S01_AXI_arprot(S01_AXI_arprot),\n        .S01_AXI_arqos(S01_AXI_arqos),\n        .S01_AXI_arready(S01_AXI_arready),\n        .S01_AXI_arregion(S01_AXI_arregion),\n        .S01_AXI_arsize(S01_AXI_arsize),\n        .S01_AXI_arvalid(S01_AXI_arvalid),\n        .S01_AXI_awaddr(S01_AXI_awaddr),\n        .S01_AXI_awburst(S01_AXI_awburst),\n        .S01_AXI_awcache(S01_AXI_awcache),\n        .S01_AXI_awid(S01_AXI_awid),\n        .S01_AXI_awlen(S01_AXI_awlen),\n        .S01_AXI_awlock(S01_AXI_awlock),\n        .S01_AXI_awprot(S01_AXI_awprot),\n        .S01_AXI_awqos(S01_AXI_awqos),\n        .S01_AXI_awready(S01_AXI_awready),\n        .S01_AXI_awregion(S01_AXI_awregion),\n        .S01_AXI_awsize(S01_AXI_awsize),\n        .S01_AXI_awvalid(S01_AXI_awvalid),\n        .S01_AXI_bid(S01_AXI_bid),\n        .S01_AXI_bready(S01_AXI_bready),\n        .S01_AXI_bresp(S01_AXI_bresp),\n        .S01_AXI_bvalid(S01_AXI_bvalid),\n        .S01_AXI_rdata(S01_AXI_rdata),\n        .S01_AXI_rid(S01_AXI_rid),\n        .S01_AXI_rlast(S01_AXI_rlast),\n        .S01_AXI_rready(S01_AXI_rready),\n        .S01_AXI_rresp(S01_AXI_rresp),\n        .S01_AXI_rvalid(S01_AXI_rvalid),\n        .S01_AXI_wdata(S01_AXI_wdata),\n        .S01_AXI_wlast(S01_AXI_wlast),\n        .S01_AXI_wready(S01_AXI_wready),\n        .S01_AXI_wstrb(S01_AXI_wstrb),\n        .S01_AXI_wvalid(S01_AXI_wvalid));\nendmodule\n", "num_lines": 961}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_m00_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_m00_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=7,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_\\\nREG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m01_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_m01_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_m01_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=7,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_\\\nREG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m01_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m02_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_m02_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_m02_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=7,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_\\\nREG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m02_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m03_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_m03_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_m03_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=7,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_\\\nREG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m03_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_s00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_s00_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_s00_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=6,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_\\\nREG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_s00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_s01_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_s01_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_s01_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=6,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_\\\nREG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_s01_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_crossbar:2.1\n// IP Revision: 23\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_xbar_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLKIF, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLKIF CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RSTIF RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [6:0] [13:7]\" *)\ninput wire [13 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]\" *)\ninput wire [15 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]\" *)\ninput wire [3 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [511:0] [1023:512]\" *)\ninput wire [1023 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [6:0] [13:7]\" *)\noutput wire [13 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]\" *)\noutput wire [3 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [6:0] [13:7]\" *)\ninput wire [13 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]\" *)\ninput wire [15 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]\" *)\ninput wire [3 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [6:0] [13:7]\" *)\noutput wire [13 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [511:0] [1023:512]\" *)\noutput wire [1023 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]\" *)\noutput wire [3 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_\\\nTHREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME S01_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0\\\n00, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI AWID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI AWID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI AWID [6:0] [27:21]\" *)\noutput wire [27 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI AWLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI AWLEN [7:0] [31:24]\" *)\noutput wire [31 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI AWBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI AWBURST [1:0] [7:6]\" *)\noutput wire [7 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWREGION [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWQOS [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [511:0] [1023:512], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [511:0] [1535:1024], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [511:0] [2047:1536]\" *)\noutput wire [2047 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WLAST [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI BID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI BID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI BID [6:0] [27:21]\" *)\ninput wire [27 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]\" *)\ninput wire [7 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI ARID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI ARID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI ARID [6:0] [27:21]\" *)\noutput wire [27 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI ARLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI ARLEN [7:0] [31:24]\" *)\noutput wire [31 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI ARBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI ARBURST [1:0] [7:6]\" *)\noutput wire [7 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARREGION [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARQOS [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI RID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI RID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI RID [6:0] [27:21]\" *)\ninput wire [27 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [511:0] [1023:512], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [511:0] [1535:1024], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [511:0] [2047:1536]\" *)\ninput wire [2047 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]\" *)\ninput wire [7 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RLAST [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE\\\n_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0\\\n.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ\\\n_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, \\\nHAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_rready;\n\n  axi_crossbar_v2_1_23_axi_crossbar #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_NUM_SLAVE_SLOTS(2),\n    .C_NUM_MASTER_SLOTS(4),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_PROTOCOL(0),\n    .C_NUM_ADDR_RANGES(1),\n    .C_M_AXI_BASE_ADDR(256'H0000000c00000000000000080000000000000004000000000000000000000000),\n    .C_M_AXI_ADDR_WIDTH(128'H00000022000000220000002200000022),\n    .C_S_AXI_BASE_ID(64'H0000004000000000),\n    .C_S_AXI_THREAD_ID_WIDTH(64'H0000000600000006),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_M_AXI_WRITE_CONNECTIVITY(128'H00000003000000030000000300000003),\n    .C_M_AXI_READ_CONNECTIVITY(128'H00000003000000030000000300000003),\n    .C_R_REGISTER(0),\n    .C_S_AXI_SINGLE_THREAD(64'H0000000000000000),\n    .C_S_AXI_WRITE_ACCEPTANCE(64'H0000002000000020),\n    .C_S_AXI_READ_ACCEPTANCE(64'H0000002000000020),\n    .C_M_AXI_WRITE_ISSUING(128'H00000010000000100000001000000010),\n    .C_M_AXI_READ_ISSUING(128'H00000010000000100000001000000010),\n    .C_S_AXI_ARB_PRIORITY(64'H0000000000000000),\n    .C_M_AXI_SECURE(128'H00000000000000000000000000000000),\n    .C_CONNECTIVITY_MODE(1)\n  ) inst (\n    .aclk(aclk),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(2'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(14'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(2'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(2'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(4'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(4'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 427}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_crossbar:2.1\n// IP Revision: 23\n\n(* X_CORE_INFO = \"axi_crossbar_v2_1_23_axi_crossbar,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_xbar_0,axi_crossbar_v2_1_23_axi_crossbar,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_xbar_0,axi_crossbar_v2_1_23_axi_crossbar,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=23,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_NUM_SLAVE_SLOTS=2,C_NUM_MASTER_SLOTS=4,C_AXI_ID_WIDTH=7,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_PROTOCOL=0,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x0000000c00000000000000080000000000000004000000000000000000000000,C_M_AXI_ADDR_WIDTH=0x00000022000\\\n000220000002200000022,C_S_AXI_BASE_ID=0x0000004000000000,C_S_AXI_THREAD_ID_WIDTH=0x0000000600000006,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000003000000030000000300000003,C_M_AXI_READ_CONNECTIVITY=0x00000003000000030000000300000003,C_R_REGISTER=0,C_S_AXI_SINGLE_THREAD=0x0000000000000000,C_S_AXI_WRITE_ACCEPTANCE=0x0000002000000020,C_S_AXI_READ_ACCEPTANCE=0x0000002000000020,C_\\\nM_AXI_WRITE_ISSUING=0x00000010000000100000001000000010,C_M_AXI_READ_ISSUING=0x00000010000000100000001000000010,C_S_AXI_ARB_PRIORITY=0x0000000000000000,C_M_AXI_SECURE=0x00000000000000000000000000000000,C_CONNECTIVITY_MODE=1}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_xbar_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLKIF, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLKIF CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RSTIF RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [6:0] [13:7]\" *)\ninput wire [13 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]\" *)\ninput wire [15 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]\" *)\ninput wire [3 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [511:0] [1023:512]\" *)\ninput wire [1023 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [6:0] [13:7]\" *)\noutput wire [13 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]\" *)\noutput wire [3 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [6:0] [13:7]\" *)\ninput wire [13 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]\" *)\ninput wire [15 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]\" *)\ninput wire [3 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [6:0] [13:7]\" *)\noutput wire [13 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [511:0] [1023:512]\" *)\noutput wire [1023 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]\" *)\noutput wire [3 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_\\\nTHREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME S01_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0\\\n00, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI AWID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI AWID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI AWID [6:0] [27:21]\" *)\noutput wire [27 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI AWLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI AWLEN [7:0] [31:24]\" *)\noutput wire [31 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI AWBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI AWBURST [1:0] [7:6]\" *)\noutput wire [7 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWREGION [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWQOS [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [511:0] [1023:512], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [511:0] [1535:1024], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [511:0] [2047:1536]\" *)\noutput wire [2047 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WLAST [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI BID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI BID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI BID [6:0] [27:21]\" *)\ninput wire [27 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]\" *)\ninput wire [7 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI ARID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI ARID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI ARID [6:0] [27:21]\" *)\noutput wire [27 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI ARLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI ARLEN [7:0] [31:24]\" *)\noutput wire [31 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI ARBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI ARBURST [1:0] [7:6]\" *)\noutput wire [7 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARREGION [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARQOS [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI RID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI RID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI RID [6:0] [27:21]\" *)\ninput wire [27 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [511:0] [1023:512], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [511:0] [1535:1024], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [511:0] [2047:1536]\" *)\ninput wire [2047 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]\" *)\ninput wire [7 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RLAST [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE\\\n_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0\\\n.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ\\\n_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, \\\nHAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_rready;\n\n  axi_crossbar_v2_1_23_axi_crossbar #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_NUM_SLAVE_SLOTS(2),\n    .C_NUM_MASTER_SLOTS(4),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_PROTOCOL(0),\n    .C_NUM_ADDR_RANGES(1),\n    .C_M_AXI_BASE_ADDR(256'H0000000c00000000000000080000000000000004000000000000000000000000),\n    .C_M_AXI_ADDR_WIDTH(128'H00000022000000220000002200000022),\n    .C_S_AXI_BASE_ID(64'H0000004000000000),\n    .C_S_AXI_THREAD_ID_WIDTH(64'H0000000600000006),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_M_AXI_WRITE_CONNECTIVITY(128'H00000003000000030000000300000003),\n    .C_M_AXI_READ_CONNECTIVITY(128'H00000003000000030000000300000003),\n    .C_R_REGISTER(0),\n    .C_S_AXI_SINGLE_THREAD(64'H0000000000000000),\n    .C_S_AXI_WRITE_ACCEPTANCE(64'H0000002000000020),\n    .C_S_AXI_READ_ACCEPTANCE(64'H0000002000000020),\n    .C_M_AXI_WRITE_ISSUING(128'H00000010000000100000001000000010),\n    .C_M_AXI_READ_ISSUING(128'H00000010000000100000001000000010),\n    .C_S_AXI_ARB_PRIORITY(64'H0000000000000000),\n    .C_M_AXI_SECURE(128'H00000000000000000000000000000000),\n    .C_CONNECTIVITY_MODE(1)\n  ) inst (\n    .aclk(aclk),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(2'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(14'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(2'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(2'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(4'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(4'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 430}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/*\n *******************************************************************************\n *\n * FIFO Generator - Verilog Behavioral Model\n *\n *******************************************************************************\n *\n * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.\n *\n * This file contains confidential and proprietary information\n * of Xilinx, Inc. and is protected under U.S. and\n * international copyright and other intellectual property\n * laws.\n *\n * DISCLAIMER\n * This disclaimer is not a license and does not grant any\n * rights to the materials distributed herewith. Except as\n * otherwise provided in a valid license issued to you by\n * Xilinx, and to the maximum extent permitted by applicable\n * law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n * (2) Xilinx shall not be liable (whether in contract or tort,\n * including negligence, or under any other theory of\n * liability) for any loss or damage of any kind or nature\n * related to, arising under or in connection with these\n * materials, including for any direct, or any indirect,\n * special, incidental, or consequential loss or damage\n * (including loss of data, profits, goodwill, or any type of\n * loss or damage suffered as a result of any action brought\n * by a third party) even if such damage or loss was\n * reasonably foreseeable or Xilinx had been advised of the\n * possibility of the same.\n *\n * CRITICAL APPLICATIONS\n * Xilinx products are not designed or intended to be fail-\n * safe, or for use in any application requiring fail-safe\n * performance, such as life-support or safety devices or\n * systems, Class III medical devices, nuclear facilities,\n * applications related to the deployment of airbags, or any\n * other applications that could lead to death, personal\n * injury, or severe property or environmental damage\n * (individually and collectively, \"Critical\n * Applications\"). Customer assumes the sole risk and\n * liability of any use of Xilinx products in Critical\n * Applications, subject only to applicable laws and\n * regulations governing limitations on product liability.\n *\n * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n * PART OF THIS FILE AT ALL TIMES.\n *\n *******************************************************************************\n *******************************************************************************\n *\n * Filename: fifo_generator_vlog_beh.v\n *\n * Author     : Xilinx\n *\n *******************************************************************************\n * Structure:\n * \n * fifo_generator_vlog_beh.v\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_as\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_ss\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_preload0\n * \n *******************************************************************************\n * Description:\n *\n * The Verilog behavioral model for the FIFO Generator.\n *\n *   The behavioral model has three parts:\n *      - The behavioral model for independent clocks FIFOs (_as)\n *      - The behavioral model for common clock FIFOs (_ss)\n *      - The \"preload logic\" block which implements First-word Fall-through\n * \n *******************************************************************************\n * Description:\n *  The verilog behavioral model for the FIFO generator core.\n *\n *******************************************************************************\n */\n\n`timescale 1ps/1ps\n`ifndef TCQ\n `define TCQ 100\n`endif\n\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_vlog_beh\n  #(\n    //-----------------------------------------------------------------------\n    // Generic Declarations\n    //-----------------------------------------------------------------------\n    parameter C_COMMON_CLOCK                 = 0,\n    parameter C_COUNT_TYPE                   = 0,\n    parameter C_DATA_COUNT_WIDTH             = 2,\n    parameter C_DEFAULT_VALUE                = \"\",\n    parameter C_DIN_WIDTH                    = 8,\n    parameter C_DOUT_RST_VAL                 = \"\",\n    parameter C_DOUT_WIDTH                   = 8,\n    parameter C_ENABLE_RLOCS                 = 0,\n    parameter C_FAMILY                       = \"\",\n    parameter C_FULL_FLAGS_RST_VAL           = 1,\n    parameter C_HAS_ALMOST_EMPTY             = 0,\n    parameter C_HAS_ALMOST_FULL              = 0,\n    parameter C_HAS_BACKUP                   = 0,\n    parameter C_HAS_DATA_COUNT               = 0,\n    parameter C_HAS_INT_CLK                  = 0,\n    parameter C_HAS_MEMINIT_FILE             = 0,\n    parameter C_HAS_OVERFLOW                 = 0,\n    parameter C_HAS_RD_DATA_COUNT            = 0,\n    parameter C_HAS_RD_RST                   = 0,\n    parameter C_HAS_RST                      = 1,\n    parameter C_HAS_SRST                     = 0,\n    parameter C_HAS_UNDERFLOW                = 0,\n    parameter C_HAS_VALID                    = 0,\n    parameter C_HAS_WR_ACK                   = 0,\n    parameter C_HAS_WR_DATA_COUNT            = 0,\n    parameter C_HAS_WR_RST                   = 0,\n    parameter C_IMPLEMENTATION_TYPE          = 0,\n    parameter C_INIT_WR_PNTR_VAL             = 0,\n    parameter C_MEMORY_TYPE                  = 1,\n    parameter C_MIF_FILE_NAME                = \"\",\n    parameter C_OPTIMIZATION_MODE            = 0,\n    parameter C_OVERFLOW_LOW                 = 0,\n    parameter C_EN_SAFETY_CKT                = 0,\n    parameter C_PRELOAD_LATENCY              = 1,\n    parameter C_PRELOAD_REGS                 = 0,\n    parameter C_PRIM_FIFO_TYPE               = \"4kx4\",\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter C_PROG_EMPTY_TYPE              = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter C_PROG_FULL_TYPE               = 0,\n    parameter C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter C_RD_DEPTH                     = 256,\n    parameter C_RD_FREQ                      = 1,\n    parameter C_RD_PNTR_WIDTH                = 8,\n    parameter C_UNDERFLOW_LOW                = 0,\n    parameter C_USE_DOUT_RST                 = 0,\n    parameter C_USE_ECC                      = 0,\n    parameter C_USE_EMBEDDED_REG             = 0,\n    parameter C_USE_PIPELINE_REG             = 0,\n    parameter C_POWER_SAVING_MODE            = 0,\n    parameter C_USE_FIFO16_FLAGS             = 0,\n    parameter C_USE_FWFT_DATA_COUNT          = 0,\n    parameter C_VALID_LOW                    = 0,\n    parameter C_WR_ACK_LOW                   = 0,\n    parameter C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter C_WR_DEPTH                     = 256,\n    parameter C_WR_FREQ                      = 1,\n    parameter C_WR_PNTR_WIDTH                = 8,\n    parameter C_WR_RESPONSE_LATENCY          = 1,\n    parameter C_MSGON_VAL                    = 1,\n    parameter C_ENABLE_RST_SYNC              = 1,\n    parameter C_ERROR_INJECTION_TYPE         = 0,\n    parameter C_SYNCHRONIZER_STAGE           = 2,\n\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE               = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3\n    parameter C_AXI_TYPE                     = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3\n    parameter C_HAS_AXI_WR_CHANNEL           = 0,\n    parameter C_HAS_AXI_RD_CHANNEL           = 0,\n    parameter C_HAS_SLAVE_CE                 = 0,\n    parameter C_HAS_MASTER_CE                = 0,\n    parameter C_ADD_NGC_CONSTRAINT           = 0,\n    parameter C_USE_COMMON_UNDERFLOW         = 0,\n    parameter C_USE_COMMON_OVERFLOW          = 0,\n    parameter C_USE_DEFAULT_SETTINGS         = 0,\n\n    // AXI Full/Lite\n    parameter C_AXI_ID_WIDTH                 = 0,\n    parameter C_AXI_ADDR_WIDTH               = 0,\n    parameter C_AXI_DATA_WIDTH               = 0,\n    parameter C_AXI_LEN_WIDTH                = 8,\n    parameter C_AXI_LOCK_WIDTH               = 2,\n    parameter C_HAS_AXI_ID                   = 0,\n    parameter C_HAS_AXI_AWUSER               = 0,\n    parameter C_HAS_AXI_WUSER                = 0,\n    parameter C_HAS_AXI_BUSER                = 0,\n    parameter C_HAS_AXI_ARUSER               = 0,\n    parameter C_HAS_AXI_RUSER                = 0,\n    parameter C_AXI_ARUSER_WIDTH             = 0,\n    parameter C_AXI_AWUSER_WIDTH             = 0,\n    parameter C_AXI_WUSER_WIDTH              = 0,\n    parameter C_AXI_BUSER_WIDTH              = 0,\n    parameter C_AXI_RUSER_WIDTH              = 0,\n\n    // AXI Streaming\n    parameter C_HAS_AXIS_TDATA               = 0,\n    parameter C_HAS_AXIS_TID                 = 0,\n    parameter C_HAS_AXIS_TDEST               = 0,\n    parameter C_HAS_AXIS_TUSER               = 0,\n    parameter C_HAS_AXIS_TREADY              = 0,\n    parameter C_HAS_AXIS_TLAST               = 0,\n    parameter C_HAS_AXIS_TSTRB               = 0,\n    parameter C_HAS_AXIS_TKEEP               = 0,\n    parameter C_AXIS_TDATA_WIDTH             = 1,\n    parameter C_AXIS_TID_WIDTH               = 1,\n    parameter C_AXIS_TDEST_WIDTH             = 1,\n    parameter C_AXIS_TUSER_WIDTH             = 1,\n    parameter C_AXIS_TSTRB_WIDTH             = 1,\n    parameter C_AXIS_TKEEP_WIDTH             = 1,\n\n    // AXI Channel Type\n    // WACH --> Write Address Channel\n    // WDCH --> Write Data Channel\n    // WRCH --> Write Response Channel\n    // RACH --> Read Address Channel\n    // RDCH --> Read Data Channel\n    // AXIS --> AXI Streaming\n    parameter C_WACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic\n    parameter C_WDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_WRCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_AXIS_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n\n    // AXI Implementation Type\n    // 1 = Common Clock Block RAM FIFO\n    // 2 = Common Clock Distributed RAM FIFO\n    // 11 = Independent Clock Block RAM FIFO\n    // 12 = Independent Clock Distributed RAM FIFO\n    parameter C_IMPLEMENTATION_TYPE_WACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WRCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_AXIS     = 0,\n\n    // AXI FIFO Type\n    // 0 = Data FIFO\n    // 1 = Packet FIFO\n    // 2 = Low Latency Sync FIFO\n    // 3 = Low Latency Async FIFO\n    parameter C_APPLICATION_TYPE_WACH        = 0,\n    parameter C_APPLICATION_TYPE_WDCH        = 0,\n    parameter C_APPLICATION_TYPE_WRCH        = 0,\n    parameter C_APPLICATION_TYPE_RACH        = 0,\n    parameter C_APPLICATION_TYPE_RDCH        = 0,\n    parameter C_APPLICATION_TYPE_AXIS        = 0,\n\n    // AXI Built-in FIFO Primitive Type\n    // 512x36, 1kx18, 2kx9, 4kx4, etc\n    parameter C_PRIM_FIFO_TYPE_WACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WRCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_AXIS          = \"512x36\",\n\n    // Enable ECC\n    // 0 = ECC disabled\n    // 1 = ECC enabled\n    parameter C_USE_ECC_WACH                 = 0,\n    parameter C_USE_ECC_WDCH                 = 0,\n    parameter C_USE_ECC_WRCH                 = 0,\n    parameter C_USE_ECC_RACH                 = 0,\n    parameter C_USE_ECC_RDCH                 = 0,\n    parameter C_USE_ECC_AXIS                 = 0,\n\n    // ECC Error Injection Type\n    // 0 = No Error Injection\n    // 1 = Single Bit Error Injection\n    // 2 = Double Bit Error Injection\n    // 3 = Single Bit and Double Bit Error Injection\n    parameter C_ERROR_INJECTION_TYPE_WACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WRCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_AXIS    = 0,\n\n    // Input Data Width\n    // Accumulation of all AXI input signal's width\n    parameter C_DIN_WIDTH_WACH               = 1,\n    parameter C_DIN_WIDTH_WDCH               = 1,\n    parameter C_DIN_WIDTH_WRCH               = 1,\n    parameter C_DIN_WIDTH_RACH               = 1,\n    parameter C_DIN_WIDTH_RDCH               = 1,\n    parameter C_DIN_WIDTH_AXIS               = 1,\n\n    parameter C_WR_DEPTH_WACH                = 16,\n    parameter C_WR_DEPTH_WDCH                = 16,\n    parameter C_WR_DEPTH_WRCH                = 16,\n    parameter C_WR_DEPTH_RACH                = 16,\n    parameter C_WR_DEPTH_RDCH                = 16,\n    parameter C_WR_DEPTH_AXIS                = 16,\n\n    parameter C_WR_PNTR_WIDTH_WACH           = 4,\n    parameter C_WR_PNTR_WIDTH_WDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_WRCH           = 4,\n    parameter C_WR_PNTR_WIDTH_RACH           = 4,\n    parameter C_WR_PNTR_WIDTH_RDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_AXIS           = 4,\n\n    parameter C_HAS_DATA_COUNTS_WACH         = 0,\n    parameter C_HAS_DATA_COUNTS_WDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_WRCH         = 0,\n    parameter C_HAS_DATA_COUNTS_RACH         = 0,\n    parameter C_HAS_DATA_COUNTS_RDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_AXIS         = 0,\n\n    parameter C_HAS_PROG_FLAGS_WACH          = 0,\n    parameter C_HAS_PROG_FLAGS_WDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_WRCH          = 0,\n    parameter C_HAS_PROG_FLAGS_RACH          = 0,\n    parameter C_HAS_PROG_FLAGS_RDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_AXIS          = 0,\n\n    parameter C_PROG_FULL_TYPE_WACH          = 0,\n    parameter C_PROG_FULL_TYPE_WDCH          = 0,\n    parameter C_PROG_FULL_TYPE_WRCH          = 0,\n    parameter C_PROG_FULL_TYPE_RACH          = 0,\n    parameter C_PROG_FULL_TYPE_RDCH          = 0,\n    parameter C_PROG_FULL_TYPE_AXIS          = 0,\n\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS      = 0,\n\n    parameter C_PROG_EMPTY_TYPE_WACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WRCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_AXIS         = 0,\n\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS     = 0,\n\n    parameter C_REG_SLICE_MODE_WACH          = 0,\n    parameter C_REG_SLICE_MODE_WDCH          = 0,\n    parameter C_REG_SLICE_MODE_WRCH          = 0,\n    parameter C_REG_SLICE_MODE_RACH          = 0,\n    parameter C_REG_SLICE_MODE_RDCH          = 0,\n    parameter C_REG_SLICE_MODE_AXIS          = 0\n\n    )\n\n   (\n    //------------------------------------------------------------------------------\n    // Input and Output Declarations\n    //------------------------------------------------------------------------------\n\n    // Conventional FIFO Interface Signals\n    input                               backup,\n    input                               backup_marker,\n    input                               clk,\n    input                               rst,\n    input                               srst,\n    input                               wr_clk,\n    input                               wr_rst,\n    input                               rd_clk,\n    input                               rd_rst,\n    input [C_DIN_WIDTH-1:0]             din,\n    input                               wr_en,\n    input                               rd_en,\n    // Optional inputs\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_assert,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_negate,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_assert,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_negate,\n    input                               int_clk,\n    input                               injectdbiterr,\n    input                               injectsbiterr,\n    input                               sleep,\n\n    output [C_DOUT_WIDTH-1:0]           dout,\n    output                              full,\n    output                              almost_full,\n    output                              wr_ack,\n    output                              overflow,\n    output                              empty,\n    output                              almost_empty,\n    output                              valid,\n    output                              underflow,\n    output [C_DATA_COUNT_WIDTH-1:0]     data_count,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]  rd_data_count,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count,\n    output                              prog_full,\n    output                              prog_empty,\n    output                              sbiterr,\n    output                              dbiterr,\n    output                              wr_rst_busy,\n    output                              rd_rst_busy,\n\n\n    // AXI Global Signal\n    input                               m_aclk,\n    input                               s_aclk,\n    input                               s_aresetn,\n    input                               s_aclk_en,\n    input                               m_aclk_en,\n    \n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_awid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_awaddr,\n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_awlen,\n    input [3-1:0]                       s_axi_awsize,\n    input [2-1:0]                       s_axi_awburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_awlock,\n    input [4-1:0]                       s_axi_awcache,\n    input [3-1:0]                       s_axi_awprot,\n    input [4-1:0]                       s_axi_awqos,\n    input [4-1:0]                       s_axi_awregion,\n    input [C_AXI_AWUSER_WIDTH-1:0]      s_axi_awuser,\n    input                               s_axi_awvalid,\n    output                              s_axi_awready,\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_wid,\n    input [C_AXI_DATA_WIDTH-1:0]        s_axi_wdata,\n    input [C_AXI_DATA_WIDTH/8-1:0]      s_axi_wstrb,\n    input                               s_axi_wlast,\n    input [C_AXI_WUSER_WIDTH-1:0]       s_axi_wuser,\n    input                               s_axi_wvalid,\n    output                              s_axi_wready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_bid,\n    output [2-1:0]                      s_axi_bresp,\n    output [C_AXI_BUSER_WIDTH-1:0]      s_axi_buser,\n    output                              s_axi_bvalid,\n    input                               s_axi_bready,\n    \n    // AXI Full/Lite Master Write Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_awid,\n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_awlen,\n    output [3-1:0]                      m_axi_awsize,\n    output [2-1:0]                      m_axi_awburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_awlock,\n    output [4-1:0]                      m_axi_awcache,\n    output [3-1:0]                      m_axi_awprot,\n    output [4-1:0]                      m_axi_awqos,\n    output [4-1:0]                      m_axi_awregion,\n    output [C_AXI_AWUSER_WIDTH-1:0]     m_axi_awuser,\n    output                              m_axi_awvalid,\n    input                               m_axi_awready,\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_wid,\n    output [C_AXI_DATA_WIDTH-1:0]       m_axi_wdata,\n    output [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb,\n    output                              m_axi_wlast,\n    output [C_AXI_WUSER_WIDTH-1:0]      m_axi_wuser,\n    output                              m_axi_wvalid,\n    input                               m_axi_wready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_bid,\n    input [2-1:0]                       m_axi_bresp,\n    input [C_AXI_BUSER_WIDTH-1:0]       m_axi_buser,\n    input                               m_axi_bvalid,\n    output                              m_axi_bready,\n    \n    \n    // AXI Full/Lite Slave Read Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_arid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_araddr, \n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_arlen,\n    input [3-1:0]                       s_axi_arsize,\n    input [2-1:0]                       s_axi_arburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_arlock,\n    input [4-1:0]                       s_axi_arcache,\n    input [3-1:0]                       s_axi_arprot,\n    input [4-1:0]                       s_axi_arqos,\n    input [4-1:0]                       s_axi_arregion,\n    input [C_AXI_ARUSER_WIDTH-1:0]      s_axi_aruser,\n    input                               s_axi_arvalid,\n    output                              s_axi_arready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_rid,       \n    output [C_AXI_DATA_WIDTH-1:0]       s_axi_rdata, \n    output [2-1:0]                      s_axi_rresp,\n    output                              s_axi_rlast,\n    output [C_AXI_RUSER_WIDTH-1:0]      s_axi_ruser,\n    output                              s_axi_rvalid,\n    input                               s_axi_rready,\n    \n    \n    \n    // AXI Full/Lite Master Read Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_arid,        \n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,  \n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_arlen,\n    output [3-1:0]                      m_axi_arsize,\n    output [2-1:0]                      m_axi_arburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_arlock,\n    output [4-1:0]                      m_axi_arcache,\n    output [3-1:0]                      m_axi_arprot,\n    output [4-1:0]                      m_axi_arqos,\n    output [4-1:0]                      m_axi_arregion,\n    output [C_AXI_ARUSER_WIDTH-1:0]     m_axi_aruser,\n    output                              m_axi_arvalid,\n    input                               m_axi_arready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_rid,        \n    input [C_AXI_DATA_WIDTH-1:0]        m_axi_rdata,  \n    input [2-1:0]                       m_axi_rresp,\n    input                               m_axi_rlast,\n    input [C_AXI_RUSER_WIDTH-1:0]       m_axi_ruser,\n    input                               m_axi_rvalid,\n    output                              m_axi_rready,\n    \n    \n    // AXI Streaming Slave Signals (Write side)\n    input                               s_axis_tvalid,\n    output                              s_axis_tready,\n    input [C_AXIS_TDATA_WIDTH-1:0]      s_axis_tdata,\n    input [C_AXIS_TSTRB_WIDTH-1:0]      s_axis_tstrb,\n    input [C_AXIS_TKEEP_WIDTH-1:0]      s_axis_tkeep,\n    input                               s_axis_tlast,\n    input [C_AXIS_TID_WIDTH-1:0]        s_axis_tid,\n    input [C_AXIS_TDEST_WIDTH-1:0]      s_axis_tdest,\n    input [C_AXIS_TUSER_WIDTH-1:0]      s_axis_tuser,\n    \n    // AXI Streaming Master Signals (Read side)\n    output                              m_axis_tvalid,\n    input                               m_axis_tready,\n    output [C_AXIS_TDATA_WIDTH-1:0]     m_axis_tdata,\n    output [C_AXIS_TSTRB_WIDTH-1:0]     m_axis_tstrb,\n    output [C_AXIS_TKEEP_WIDTH-1:0]     m_axis_tkeep,\n    output                              m_axis_tlast,\n    output [C_AXIS_TID_WIDTH-1:0]       m_axis_tid,\n    output [C_AXIS_TDEST_WIDTH-1:0]     m_axis_tdest,\n    output [C_AXIS_TUSER_WIDTH-1:0]     m_axis_tuser,\n    \n           \n    \n    \n    // AXI Full/Lite Write Address Channel signals\n    input                               axi_aw_injectsbiterr,\n    input                               axi_aw_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_rd_data_count,\n    output                              axi_aw_sbiterr,\n    output                              axi_aw_dbiterr,\n    output                              axi_aw_overflow,\n    output                              axi_aw_underflow,\n    output                              axi_aw_prog_full,\n    output                              axi_aw_prog_empty,\n    \n    \n    // AXI Full/Lite Write Data Channel signals\n    input                               axi_w_injectsbiterr,\n    input                               axi_w_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_rd_data_count,\n    output                              axi_w_sbiterr,\n    output                              axi_w_dbiterr,\n    output                              axi_w_overflow,\n    output                              axi_w_underflow,\n    output                              axi_w_prog_full,\n    output                              axi_w_prog_empty,\n    \n    \n    // AXI Full/Lite Write Response Channel signals\n    input                               axi_b_injectsbiterr,\n    input                               axi_b_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_rd_data_count,\n    output                              axi_b_sbiterr,\n    output                              axi_b_dbiterr,\n    output                              axi_b_overflow,\n    output                              axi_b_underflow,\n    output                              axi_b_prog_full,\n    output                              axi_b_prog_empty,\n    \n    \n    \n    // AXI Full/Lite Read Address Channel signals\n    input                               axi_ar_injectsbiterr,\n    input                               axi_ar_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_rd_data_count,\n    output                              axi_ar_sbiterr,\n    output                              axi_ar_dbiterr,\n    output                              axi_ar_overflow,\n    output                              axi_ar_underflow,\n    output                              axi_ar_prog_full,\n    output                              axi_ar_prog_empty,\n\n    \n    // AXI Full/Lite Read Data Channel Signals\n    input                               axi_r_injectsbiterr,\n    input                               axi_r_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_rd_data_count,\n    output                              axi_r_sbiterr,\n    output                              axi_r_dbiterr,\n    output                              axi_r_overflow,\n    output                              axi_r_underflow,\n    output                              axi_r_prog_full,\n    output                              axi_r_prog_empty,\n\n    \n    // AXI Streaming FIFO Related Signals\n    input                               axis_injectsbiterr,\n    input                               axis_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_wr_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_rd_data_count,\n    output                              axis_sbiterr,\n    output                              axis_dbiterr,\n    output                              axis_overflow,\n    output                              axis_underflow,\n    output                              axis_prog_full,\n    output                              axis_prog_empty\n\n    );\n\n    wire                              BACKUP;\n    wire                              BACKUP_MARKER;\n    wire                              CLK;\n    wire                              RST;\n    wire                              SRST;\n    wire                              WR_CLK;\n    wire                              WR_RST;\n    wire                              RD_CLK;\n    wire                              RD_RST;\n    wire [C_DIN_WIDTH-1:0]            DIN;\n    wire                              WR_EN;\n    wire                              RD_EN;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_ASSERT;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_NEGATE;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_ASSERT;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_NEGATE;\n    wire                              INT_CLK;\n    wire                              INJECTDBITERR;\n    wire                              INJECTSBITERR;\n    wire                              SLEEP;\n    wire [C_DOUT_WIDTH-1:0]           DOUT;\n    wire                              FULL;\n    wire                              ALMOST_FULL;\n    wire                              WR_ACK;\n    wire                              OVERFLOW;\n    wire                              EMPTY;\n    wire                              ALMOST_EMPTY;\n    wire                              VALID;\n    wire                              UNDERFLOW;\n    wire [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT;\n    wire [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT;\n    wire                              PROG_FULL;\n    wire                              PROG_EMPTY;\n    wire                              SBITERR;\n    wire                              DBITERR;\n    wire                              WR_RST_BUSY;\n    wire                              RD_RST_BUSY;\n    wire                              M_ACLK;\n    wire                              S_ACLK;\n    wire                              S_ARESETN;\n    wire                              S_ACLK_EN;\n    wire                              M_ACLK_EN;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_AWLEN;\n    wire [3-1:0]                      S_AXI_AWSIZE;\n    wire [2-1:0]                      S_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_AWLOCK;\n    wire [4-1:0]                      S_AXI_AWCACHE;\n    wire [3-1:0]                      S_AXI_AWPROT;\n    wire [4-1:0]                      S_AXI_AWQOS;\n    wire [4-1:0]                      S_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     S_AXI_AWUSER;\n    wire                              S_AXI_AWVALID;\n    wire                              S_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     S_AXI_WSTRB;\n    wire                              S_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      S_AXI_WUSER;\n    wire                              S_AXI_WVALID;\n    wire                              S_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_BID;\n    wire [2-1:0]                      S_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      S_AXI_BUSER;\n    wire                              S_AXI_BVALID;\n    wire                              S_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_AWLEN;\n    wire [3-1:0]                      M_AXI_AWSIZE;\n    wire [2-1:0]                      M_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_AWLOCK;\n    wire [4-1:0]                      M_AXI_AWCACHE;\n    wire [3-1:0]                      M_AXI_AWPROT;\n    wire [4-1:0]                      M_AXI_AWQOS;\n    wire [4-1:0]                      M_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     M_AXI_AWUSER;\n    wire                              M_AXI_AWVALID;\n    wire                              M_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     M_AXI_WSTRB;\n    wire                              M_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      M_AXI_WUSER;\n    wire                              M_AXI_WVALID;\n    wire                              M_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_BID;\n    wire [2-1:0]                      M_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      M_AXI_BUSER;\n    wire                              M_AXI_BVALID;\n    wire                              M_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_ARID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_ARADDR; \n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_ARLEN;\n    wire [3-1:0]                      S_AXI_ARSIZE;\n    wire [2-1:0]                      S_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_ARLOCK;\n    wire [4-1:0]                      S_AXI_ARCACHE;\n    wire [3-1:0]                      S_AXI_ARPROT;\n    wire [4-1:0]                      S_AXI_ARQOS;\n    wire [4-1:0]                      S_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     S_AXI_ARUSER;\n    wire                              S_AXI_ARVALID;\n    wire                              S_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_RID;       \n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_RDATA; \n    wire [2-1:0]                      S_AXI_RRESP;\n    wire                              S_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      S_AXI_RUSER;\n    wire                              S_AXI_RVALID;\n    wire                              S_AXI_RREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_ARID;        \n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_ARADDR;  \n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_ARLEN;\n    wire [3-1:0]                      M_AXI_ARSIZE;\n    wire [2-1:0]                      M_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_ARLOCK;\n    wire [4-1:0]                      M_AXI_ARCACHE;\n    wire [3-1:0]                      M_AXI_ARPROT;\n    wire [4-1:0]                      M_AXI_ARQOS;\n    wire [4-1:0]                      M_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     M_AXI_ARUSER;\n    wire                              M_AXI_ARVALID;\n    wire                              M_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_RID;        \n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_RDATA;  \n    wire [2-1:0]                      M_AXI_RRESP;\n    wire                              M_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      M_AXI_RUSER;\n    wire                              M_AXI_RVALID;\n    wire                              M_AXI_RREADY;\n    wire                              S_AXIS_TVALID;\n    wire                              S_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     S_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     S_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     S_AXIS_TKEEP;\n    wire                              S_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       S_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     S_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     S_AXIS_TUSER;\n    wire                              M_AXIS_TVALID;\n    wire                              M_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     M_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     M_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     M_AXIS_TKEEP;\n    wire                              M_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       M_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     M_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     M_AXIS_TUSER;\n    wire                              AXI_AW_INJECTSBITERR;\n    wire                              AXI_AW_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_RD_DATA_COUNT;\n    wire                              AXI_AW_SBITERR;\n    wire                              AXI_AW_DBITERR;\n    wire                              AXI_AW_OVERFLOW;\n    wire                              AXI_AW_UNDERFLOW;\n    wire                              AXI_AW_PROG_FULL;\n    wire                              AXI_AW_PROG_EMPTY;\n    wire                              AXI_W_INJECTSBITERR;\n    wire                              AXI_W_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_RD_DATA_COUNT;\n    wire                              AXI_W_SBITERR;\n    wire                              AXI_W_DBITERR;\n    wire                              AXI_W_OVERFLOW;\n    wire                              AXI_W_UNDERFLOW;\n    wire                              AXI_W_PROG_FULL;\n    wire                              AXI_W_PROG_EMPTY;\n    wire                              AXI_B_INJECTSBITERR;\n    wire                              AXI_B_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_RD_DATA_COUNT;\n    wire                              AXI_B_SBITERR;\n    wire                              AXI_B_DBITERR;\n    wire                              AXI_B_OVERFLOW;\n    wire                              AXI_B_UNDERFLOW;\n    wire                              AXI_B_PROG_FULL;\n    wire                              AXI_B_PROG_EMPTY;\n    wire                              AXI_AR_INJECTSBITERR;\n    wire                              AXI_AR_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_RD_DATA_COUNT;\n    wire                              AXI_AR_SBITERR;\n    wire                              AXI_AR_DBITERR;\n    wire                              AXI_AR_OVERFLOW;\n    wire                              AXI_AR_UNDERFLOW;\n    wire                              AXI_AR_PROG_FULL;\n    wire                              AXI_AR_PROG_EMPTY;\n    wire                              AXI_R_INJECTSBITERR;\n    wire                              AXI_R_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_RD_DATA_COUNT;\n    wire                              AXI_R_SBITERR;\n    wire                              AXI_R_DBITERR;\n    wire                              AXI_R_OVERFLOW;\n    wire                              AXI_R_UNDERFLOW;\n    wire                              AXI_R_PROG_FULL;\n    wire                              AXI_R_PROG_EMPTY;\n    wire                              AXIS_INJECTSBITERR;\n    wire                              AXIS_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_RD_DATA_COUNT;\n    wire                              AXIS_SBITERR;\n    wire                              AXIS_DBITERR;\n    wire                              AXIS_OVERFLOW;\n    wire                              AXIS_UNDERFLOW;\n    wire                              AXIS_PROG_FULL;\n    wire                              AXIS_PROG_EMPTY;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count_in;\n    wire                              wr_rst_int;\n    wire                              rd_rst_int;\n    wire                              wr_rst_busy_o;\n    wire                              wr_rst_busy_ntve;\n    wire                              wr_rst_busy_axis;\n    wire                              wr_rst_busy_wach;\n    wire                              wr_rst_busy_wdch;\n    wire                              wr_rst_busy_wrch;\n    wire                              wr_rst_busy_rach;\n    wire                              wr_rst_busy_rdch;\n\n\n\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n\n\n\n    // Conventional FIFO Interface Signals\n    assign BACKUP                 = backup;\n    assign BACKUP_MARKER          = backup_marker;\n    assign CLK                    = clk;\n    assign RST                    = rst;\n    assign SRST                   = srst;\n    assign WR_CLK                 = wr_clk;\n    assign WR_RST                 = wr_rst;\n    assign RD_CLK                 = rd_clk;\n    assign RD_RST                 = rd_rst;\n    assign WR_EN                  = wr_en;\n    assign RD_EN                  = rd_en;\n    assign INT_CLK                = int_clk;\n    assign INJECTDBITERR          = injectdbiterr;\n    assign INJECTSBITERR          = injectsbiterr;\n    assign SLEEP                  = sleep;\n    assign full                   = FULL;\n    assign almost_full            = ALMOST_FULL;\n    assign wr_ack                 = WR_ACK;\n    assign overflow               = OVERFLOW;\n    assign empty                  = EMPTY;\n    assign almost_empty           = ALMOST_EMPTY;\n    assign valid                  = VALID;\n    assign underflow              = UNDERFLOW;\n    assign prog_full              = PROG_FULL;\n    assign prog_empty             = PROG_EMPTY;\n    assign sbiterr                = SBITERR;\n    assign dbiterr                = DBITERR;\n//    assign wr_rst_busy            = WR_RST_BUSY | wr_rst_busy_o;\n    assign wr_rst_busy            = wr_rst_busy_o;\n    assign rd_rst_busy            = RD_RST_BUSY;\n    assign M_ACLK                 = m_aclk;\n    assign S_ACLK                 = s_aclk;\n    assign S_ARESETN              = s_aresetn;\n    assign S_ACLK_EN              = s_aclk_en;\n    assign M_ACLK_EN              = m_aclk_en;\n    assign S_AXI_AWVALID          = s_axi_awvalid;\n    assign s_axi_awready          = S_AXI_AWREADY;\n    assign S_AXI_WLAST            = s_axi_wlast;\n    assign S_AXI_WVALID           = s_axi_wvalid;\n    assign s_axi_wready           = S_AXI_WREADY;\n    assign s_axi_bvalid           = S_AXI_BVALID;\n    assign S_AXI_BREADY           = s_axi_bready;\n    assign m_axi_awvalid          = M_AXI_AWVALID;\n    assign M_AXI_AWREADY          = m_axi_awready;\n    assign m_axi_wlast            = M_AXI_WLAST;\n    assign m_axi_wvalid           = M_AXI_WVALID;\n    assign M_AXI_WREADY           = m_axi_wready;\n    assign M_AXI_BVALID           = m_axi_bvalid;\n    assign m_axi_bready           = M_AXI_BREADY;\n    assign S_AXI_ARVALID          = s_axi_arvalid;\n    assign s_axi_arready          = S_AXI_ARREADY;\n    assign s_axi_rlast            = S_AXI_RLAST;\n    assign s_axi_rvalid           = S_AXI_RVALID;\n    assign S_AXI_RREADY           = s_axi_rready;\n    assign m_axi_arvalid          = M_AXI_ARVALID;\n    assign M_AXI_ARREADY          = m_axi_arready;\n    assign M_AXI_RLAST            = m_axi_rlast;\n    assign M_AXI_RVALID           = m_axi_rvalid;\n    assign m_axi_rready           = M_AXI_RREADY;\n    assign S_AXIS_TVALID          = s_axis_tvalid;\n    assign s_axis_tready          = S_AXIS_TREADY;\n    assign S_AXIS_TLAST           = s_axis_tlast;\n    assign m_axis_tvalid          = M_AXIS_TVALID;\n    assign M_AXIS_TREADY          = m_axis_tready;\n    assign m_axis_tlast           = M_AXIS_TLAST;\n    assign AXI_AW_INJECTSBITERR   = axi_aw_injectsbiterr;\n    assign AXI_AW_INJECTDBITERR   = axi_aw_injectdbiterr;\n    assign axi_aw_sbiterr         = AXI_AW_SBITERR;\n    assign axi_aw_dbiterr         = AXI_AW_DBITERR;\n    assign axi_aw_overflow        = AXI_AW_OVERFLOW;\n    assign axi_aw_underflow       = AXI_AW_UNDERFLOW;\n    assign axi_aw_prog_full       = AXI_AW_PROG_FULL;\n    assign axi_aw_prog_empty      = AXI_AW_PROG_EMPTY;\n    assign AXI_W_INJECTSBITERR    = axi_w_injectsbiterr;\n    assign AXI_W_INJECTDBITERR    = axi_w_injectdbiterr;\n    assign axi_w_sbiterr          = AXI_W_SBITERR;\n    assign axi_w_dbiterr          = AXI_W_DBITERR;\n    assign axi_w_overflow         = AXI_W_OVERFLOW;\n    assign axi_w_underflow        = AXI_W_UNDERFLOW;\n    assign axi_w_prog_full        = AXI_W_PROG_FULL;\n    assign axi_w_prog_empty       = AXI_W_PROG_EMPTY;\n    assign AXI_B_INJECTSBITERR    = axi_b_injectsbiterr;\n    assign AXI_B_INJECTDBITERR    = axi_b_injectdbiterr;\n    assign axi_b_sbiterr          = AXI_B_SBITERR;\n    assign axi_b_dbiterr          = AXI_B_DBITERR;\n    assign axi_b_overflow         = AXI_B_OVERFLOW;\n    assign axi_b_underflow        = AXI_B_UNDERFLOW;\n    assign axi_b_prog_full        = AXI_B_PROG_FULL;\n    assign axi_b_prog_empty       = AXI_B_PROG_EMPTY;\n    assign AXI_AR_INJECTSBITERR   = axi_ar_injectsbiterr;\n    assign AXI_AR_INJECTDBITERR   = axi_ar_injectdbiterr;\n    assign axi_ar_sbiterr         = AXI_AR_SBITERR;\n    assign axi_ar_dbiterr         = AXI_AR_DBITERR;\n    assign axi_ar_overflow        = AXI_AR_OVERFLOW;\n    assign axi_ar_underflow       = AXI_AR_UNDERFLOW;\n    assign axi_ar_prog_full       = AXI_AR_PROG_FULL;\n    assign axi_ar_prog_empty      = AXI_AR_PROG_EMPTY;\n    assign AXI_R_INJECTSBITERR    = axi_r_injectsbiterr;\n    assign AXI_R_INJECTDBITERR    = axi_r_injectdbiterr;\n    assign axi_r_sbiterr          = AXI_R_SBITERR;\n    assign axi_r_dbiterr          = AXI_R_DBITERR;\n    assign axi_r_overflow         = AXI_R_OVERFLOW;\n    assign axi_r_underflow        = AXI_R_UNDERFLOW;\n    assign axi_r_prog_full        = AXI_R_PROG_FULL;\n    assign axi_r_prog_empty       = AXI_R_PROG_EMPTY;\n    assign AXIS_INJECTSBITERR     = axis_injectsbiterr;\n    assign AXIS_INJECTDBITERR     = axis_injectdbiterr;\n    assign axis_sbiterr           = AXIS_SBITERR;\n    assign axis_dbiterr           = AXIS_DBITERR;\n    assign axis_overflow          = AXIS_OVERFLOW;\n    assign axis_underflow         = AXIS_UNDERFLOW;\n    assign axis_prog_full         = AXIS_PROG_FULL;\n    assign axis_prog_empty        = AXIS_PROG_EMPTY;\n\n\n    assign DIN                       = din;\n    assign PROG_EMPTY_THRESH         = prog_empty_thresh;\n    assign PROG_EMPTY_THRESH_ASSERT  = prog_empty_thresh_assert;\n    assign PROG_EMPTY_THRESH_NEGATE  = prog_empty_thresh_negate;\n    assign PROG_FULL_THRESH          = prog_full_thresh;\n    assign PROG_FULL_THRESH_ASSERT   = prog_full_thresh_assert;\n    assign PROG_FULL_THRESH_NEGATE   = prog_full_thresh_negate;\n    assign dout                      = DOUT;\n    assign data_count                = DATA_COUNT;\n    assign rd_data_count             = RD_DATA_COUNT;\n    assign wr_data_count             = WR_DATA_COUNT;\n    assign S_AXI_AWID                = s_axi_awid;\n    assign S_AXI_AWADDR              = s_axi_awaddr;\n    assign S_AXI_AWLEN               = s_axi_awlen;\n    assign S_AXI_AWSIZE              = s_axi_awsize;\n    assign S_AXI_AWBURST             = s_axi_awburst;\n    assign S_AXI_AWLOCK              = s_axi_awlock;\n    assign S_AXI_AWCACHE             = s_axi_awcache;\n    assign S_AXI_AWPROT              = s_axi_awprot;\n    assign S_AXI_AWQOS               = s_axi_awqos;\n    assign S_AXI_AWREGION            = s_axi_awregion;\n    assign S_AXI_AWUSER              = s_axi_awuser;\n    assign S_AXI_WID                 = s_axi_wid;\n    assign S_AXI_WDATA               = s_axi_wdata;\n    assign S_AXI_WSTRB               = s_axi_wstrb;\n    assign S_AXI_WUSER               = s_axi_wuser;\n    assign s_axi_bid                 = S_AXI_BID;\n    assign s_axi_bresp               = S_AXI_BRESP;\n    assign s_axi_buser               = S_AXI_BUSER;\n    assign m_axi_awid                = M_AXI_AWID;\n    assign m_axi_awaddr              = M_AXI_AWADDR;\n    assign m_axi_awlen               = M_AXI_AWLEN;\n    assign m_axi_awsize              = M_AXI_AWSIZE;\n    assign m_axi_awburst             = M_AXI_AWBURST;\n    assign m_axi_awlock              = M_AXI_AWLOCK;\n    assign m_axi_awcache             = M_AXI_AWCACHE;\n    assign m_axi_awprot              = M_AXI_AWPROT;\n    assign m_axi_awqos               = M_AXI_AWQOS;\n    assign m_axi_awregion            = M_AXI_AWREGION;\n    assign m_axi_awuser              = M_AXI_AWUSER;\n    assign m_axi_wid                 = M_AXI_WID;\n    assign m_axi_wdata               = M_AXI_WDATA;\n    assign m_axi_wstrb               = M_AXI_WSTRB;\n    assign m_axi_wuser               = M_AXI_WUSER;\n    assign M_AXI_BID                 = m_axi_bid;\n    assign M_AXI_BRESP               = m_axi_bresp;\n    assign M_AXI_BUSER               = m_axi_buser;\n    assign S_AXI_ARID                = s_axi_arid;\n    assign S_AXI_ARADDR              = s_axi_araddr; \n    assign S_AXI_ARLEN               = s_axi_arlen;\n    assign S_AXI_ARSIZE              = s_axi_arsize;\n    assign S_AXI_ARBURST             = s_axi_arburst;\n    assign S_AXI_ARLOCK              = s_axi_arlock;\n    assign S_AXI_ARCACHE             = s_axi_arcache;\n    assign S_AXI_ARPROT              = s_axi_arprot;\n    assign S_AXI_ARQOS               = s_axi_arqos;\n    assign S_AXI_ARREGION            = s_axi_arregion;\n    assign S_AXI_ARUSER              = s_axi_aruser;\n    assign s_axi_rid                 = S_AXI_RID;\n    assign s_axi_rdata               = S_AXI_RDATA;\n    assign s_axi_rresp               = S_AXI_RRESP;\n    assign s_axi_ruser               = S_AXI_RUSER;\n    assign m_axi_arid                = M_AXI_ARID;        \n    assign m_axi_araddr              = M_AXI_ARADDR;  \n    assign m_axi_arlen               = M_AXI_ARLEN;\n    assign m_axi_arsize              = M_AXI_ARSIZE;\n    assign m_axi_arburst             = M_AXI_ARBURST;\n    assign m_axi_arlock              = M_AXI_ARLOCK;\n    assign m_axi_arcache             = M_AXI_ARCACHE;\n    assign m_axi_arprot              = M_AXI_ARPROT;\n    assign m_axi_arqos               = M_AXI_ARQOS;\n    assign m_axi_arregion            = M_AXI_ARREGION;\n    assign m_axi_aruser              = M_AXI_ARUSER;\n    assign M_AXI_RID                 = m_axi_rid;        \n    assign M_AXI_RDATA               = m_axi_rdata;  \n    assign M_AXI_RRESP               = m_axi_rresp;\n    assign M_AXI_RUSER               = m_axi_ruser;\n    assign S_AXIS_TDATA              = s_axis_tdata;\n    assign S_AXIS_TSTRB              = s_axis_tstrb;\n    assign S_AXIS_TKEEP              = s_axis_tkeep;\n    assign S_AXIS_TID                = s_axis_tid;\n    assign S_AXIS_TDEST              = s_axis_tdest;\n    assign S_AXIS_TUSER              = s_axis_tuser;\n    assign m_axis_tdata              = M_AXIS_TDATA;\n    assign m_axis_tstrb              = M_AXIS_TSTRB;\n    assign m_axis_tkeep              = M_AXIS_TKEEP;\n    assign m_axis_tid                = M_AXIS_TID;\n    assign m_axis_tdest              = M_AXIS_TDEST;\n    assign m_axis_tuser              = M_AXIS_TUSER;\n    assign AXI_AW_PROG_FULL_THRESH   = axi_aw_prog_full_thresh;\n    assign AXI_AW_PROG_EMPTY_THRESH  = axi_aw_prog_empty_thresh;\n    assign axi_aw_data_count         = AXI_AW_DATA_COUNT;\n    assign axi_aw_wr_data_count      = AXI_AW_WR_DATA_COUNT;\n    assign axi_aw_rd_data_count      = AXI_AW_RD_DATA_COUNT;\n    assign AXI_W_PROG_FULL_THRESH    = axi_w_prog_full_thresh;\n    assign AXI_W_PROG_EMPTY_THRESH   = axi_w_prog_empty_thresh;\n    assign axi_w_data_count          = AXI_W_DATA_COUNT;\n    assign axi_w_wr_data_count       = AXI_W_WR_DATA_COUNT;\n    assign axi_w_rd_data_count       = AXI_W_RD_DATA_COUNT;\n    assign AXI_B_PROG_FULL_THRESH    = axi_b_prog_full_thresh;\n    assign AXI_B_PROG_EMPTY_THRESH   = axi_b_prog_empty_thresh;\n    assign axi_b_data_count          = AXI_B_DATA_COUNT;\n    assign axi_b_wr_data_count       = AXI_B_WR_DATA_COUNT;\n    assign axi_b_rd_data_count       = AXI_B_RD_DATA_COUNT;\n    assign AXI_AR_PROG_FULL_THRESH   = axi_ar_prog_full_thresh;\n    assign AXI_AR_PROG_EMPTY_THRESH  = axi_ar_prog_empty_thresh;\n    assign axi_ar_data_count         = AXI_AR_DATA_COUNT;\n    assign axi_ar_wr_data_count      = AXI_AR_WR_DATA_COUNT;\n    assign axi_ar_rd_data_count      = AXI_AR_RD_DATA_COUNT;\n    assign AXI_R_PROG_FULL_THRESH    = axi_r_prog_full_thresh;\n    assign AXI_R_PROG_EMPTY_THRESH   = axi_r_prog_empty_thresh;\n    assign axi_r_data_count          = AXI_R_DATA_COUNT;\n    assign axi_r_wr_data_count       = AXI_R_WR_DATA_COUNT;\n    assign axi_r_rd_data_count       = AXI_R_RD_DATA_COUNT;\n    assign AXIS_PROG_FULL_THRESH     = axis_prog_full_thresh;\n    assign AXIS_PROG_EMPTY_THRESH    = axis_prog_empty_thresh;\n    assign axis_data_count           = AXIS_DATA_COUNT;\n    assign axis_wr_data_count        = AXIS_WR_DATA_COUNT;\n    assign axis_rd_data_count        = AXIS_RD_DATA_COUNT;\n\n\n  generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_COMMON_CLOCK \t\t(C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DATA_COUNT_WIDTH\t\t(C_DATA_COUNT_WIDTH),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH),\n        .C_DOUT_RST_VAL\t\t\t(C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),\n        .C_DOUT_WIDTH\t\t\t(C_DOUT_WIDTH),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n        .C_HAS_ALMOST_EMPTY\t\t(C_HAS_ALMOST_EMPTY),\n        .C_HAS_ALMOST_FULL\t\t(C_HAS_ALMOST_FULL),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_DATA_COUNT\t\t(C_HAS_DATA_COUNT),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_HAS_RD_DATA_COUNT\t\t(C_HAS_RD_DATA_COUNT),\n        .C_HAS_RD_RST\t\t\t(C_HAS_RD_RST),\n        .C_HAS_RST\t\t\t(C_HAS_RST),\n        .C_HAS_SRST\t\t\t(C_HAS_SRST),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_HAS_VALID\t\t\t(C_HAS_VALID),\n        .C_HAS_WR_ACK\t\t\t(C_HAS_WR_ACK),\n        .C_HAS_WR_DATA_COUNT\t\t(C_HAS_WR_DATA_COUNT),\n        .C_HAS_WR_RST\t\t\t(C_HAS_WR_RST),\n        .C_IMPLEMENTATION_TYPE\t\t(C_IMPLEMENTATION_TYPE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_MEMORY_TYPE\t\t\t(C_MEMORY_TYPE),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n        .C_PRELOAD_LATENCY\t\t(C_PRELOAD_LATENCY),\n        .C_PRELOAD_REGS\t\t\t(C_PRELOAD_REGS),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL),\n        .C_PROG_EMPTY_THRESH_NEGATE_VAL\t(C_PROG_EMPTY_THRESH_NEGATE_VAL),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL),\n        .C_PROG_FULL_THRESH_NEGATE_VAL\t(C_PROG_FULL_THRESH_NEGATE_VAL),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_RD_DATA_COUNT_WIDTH),\n        .C_RD_DEPTH\t\t\t(C_RD_DEPTH),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_RD_PNTR_WIDTH\t\t(C_RD_PNTR_WIDTH),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n        .C_USE_ECC                      (C_USE_ECC),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_EN_SAFETY_CKT\t\t(C_EN_SAFETY_CKT),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_USE_FWFT_DATA_COUNT\t\t(C_USE_FWFT_DATA_COUNT),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_DATA_COUNT_WIDTH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (C_ENABLE_RST_SYNC),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE),\n        .C_AXI_TYPE                     (C_AXI_TYPE),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE)\n      )\n    fifo_generator_v13_2_5_conv_dut\n      (\n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .CLK                      (CLK),\n        .RST                      (RST),\n        .SRST                     (SRST),\n        .WR_CLK                   (WR_CLK),\n        .WR_RST                   (WR_RST),\n        .RD_CLK                   (RD_CLK),\n        .RD_RST                   (RD_RST),\n        .DIN                      (DIN),\n        .WR_EN                    (WR_EN),\n        .RD_EN                    (RD_EN),\n        .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),\n        .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),\n        .PROG_FULL_THRESH         (PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),\n        .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),\n        .INT_CLK                  (INT_CLK),\n        .INJECTDBITERR            (INJECTDBITERR), \n        .INJECTSBITERR            (INJECTSBITERR),\n  \n        .DOUT                     (DOUT),\n        .FULL                     (FULL),\n        .ALMOST_FULL              (ALMOST_FULL),\n        .WR_ACK                   (WR_ACK),\n        .OVERFLOW                 (OVERFLOW),\n        .EMPTY                    (EMPTY),\n        .ALMOST_EMPTY             (ALMOST_EMPTY),\n        .VALID                    (VALID),\n        .UNDERFLOW                (UNDERFLOW),\n        .DATA_COUNT               (DATA_COUNT),\n        .RD_DATA_COUNT            (RD_DATA_COUNT),\n        .WR_DATA_COUNT            (wr_data_count_in),\n        .PROG_FULL                (PROG_FULL),\n        .PROG_EMPTY               (PROG_EMPTY),\n        .SBITERR                  (SBITERR),\n        .DBITERR                  (DBITERR),\n        .wr_rst_busy_o            (wr_rst_busy_o),\n        .wr_rst_busy              (wr_rst_busy_i),\n        .rd_rst_busy              (rd_rst_busy),\n        .wr_rst_i_out             (wr_rst_int),\n        .rd_rst_i_out             (rd_rst_int)\n       );\n  end endgenerate\n\n\n\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n  localparam C_AXI_SIZE_WIDTH   = 3;\n  localparam C_AXI_BURST_WIDTH  = 2;\n  localparam C_AXI_CACHE_WIDTH  = 4;\n  localparam C_AXI_PROT_WIDTH   = 3;\n  localparam C_AXI_QOS_WIDTH    = 4;\n  localparam C_AXI_REGION_WIDTH = 4;\n  localparam C_AXI_BRESP_WIDTH  = 2;\n  localparam C_AXI_RRESP_WIDTH  = 2;\n\n  localparam IS_AXI_STREAMING  = C_INTERFACE_TYPE == 1 ? 1 : 0;\n  localparam TDATA_OFFSET      = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;\n  localparam TSTRB_OFFSET      = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;\n  localparam TKEEP_OFFSET      = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;\n  localparam TID_OFFSET        = C_HAS_AXIS_TID   == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;\n  localparam TDEST_OFFSET      = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;\n  localparam TUSER_OFFSET      = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;\n  localparam LOG_DEPTH_AXIS    = find_log2(C_WR_DEPTH_AXIS); \n  localparam LOG_WR_DEPTH      = find_log2(C_WR_DEPTH); \n\n\n  function [LOG_DEPTH_AXIS-1:0] bin2gray;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      begin\n         bin2gray = x ^ (x>>1);\n      end\n   endfunction\n\n  function [LOG_DEPTH_AXIS-1:0] gray2bin;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      integer                i;\n      begin\n         gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];\n         for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin\n            gray2bin[i] =  gray2bin[i+1] ^ x[i];\n         end\n      end\n   endfunction\n\nwire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;\nwire  [LOG_WR_DEPTH-1 : 0]  w_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;\nreg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;\nwire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;\nwire [LOG_WR_DEPTH : 0] r_inv_pad;\nwire [LOG_WR_DEPTH-1 : 0] d_cnt;\nreg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;\nreg adj_w_cnt_rd_pad_0 = 0;\nreg r_inv_pad_0 = 0;\n\n\n   genvar l;\n\n   generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (LOG_WR_DEPTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_int), \n         .CLK      (RD_CLK), \n         .DIN      (w_q[l-1]), \n         .DOUT     (w_q[l])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter\n    assign wr_eop_ad = WR_EN & !(FULL);\n    assign rd_eop_ad = RD_EN & !(EMPTY);\n\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt    <= 1'b0;\n      else if (wr_eop_ad)\n        w_cnt    <= w_cnt + 1;\n    end\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt_gc    <= 1'b0;\n      else \n        w_cnt_gc    <= bin2gray(w_cnt);\n    end\n\n\n    assign  w_q[0]  = w_cnt_gc;\n    assign  w_cnt_gc_asreg_last       = w_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        w_cnt_rd    <= 1'b0;\n      else \n        w_cnt_rd    <= gray2bin(w_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        r_cnt    <= 1'b0;\n      else if (rd_eop_ad)\n        r_cnt    <= r_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;\n   assign r_inv_pad[LOG_WR_DEPTH : 1]        = ~r_cnt;\n   assign adj_w_cnt_rd_pad[0]                = adj_w_cnt_rd_pad_0;\n   assign r_inv_pad[0]                       = r_inv_pad_0;\n\n\n  always @ ( rd_eop_ad )\n    begin\n      if (!rd_eop_ad) begin\n        adj_w_cnt_rd_pad_0    <= 1'b1;\n        r_inv_pad_0           <= 1'b1;\n      end else begin \n        adj_w_cnt_rd_pad_0    <= 1'b0;\n        r_inv_pad_0           <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        d_cnt_pad    <= 1'b0;\n      else \n        d_cnt_pad    <= adj_w_cnt_rd_pad + r_inv_pad ;\n    end\n\n   assign  d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;\n   assign  WR_DATA_COUNT = d_cnt;\n\n  end endgenerate // fifo_ic_adapter\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter\n   assign  WR_DATA_COUNT = wr_data_count_in;\n\n  end endgenerate // fifo_icn_adapter\n\n\n\n  wire                          inverted_reset = ~S_ARESETN;\n  wire                          axi_rs_rst;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_din          ;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_dout         ;\n  wire                          axis_full         ;\n  wire                          axis_almost_full  ;\n  wire                          axis_empty        ;\n  wire                          axis_s_axis_tready;\n  wire                          axis_m_axis_tvalid;\n  wire                          axis_wr_en        ;\n  wire                          axis_rd_en        ;\n  wire                          axis_we           ;\n  wire                          axis_re           ;\n  wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;\n  reg                           axis_pkt_read = 1'b0;\n  wire                          axis_rd_rst;\n  wire                          axis_wr_rst;\n\n  generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||\n               C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst\n      reg                           rst_d1 = 0        ;\n      reg                           rst_d2 = 0        ;\n      reg [3:0]                    axi_rst = 4'h0     ;\n      always @ (posedge inverted_reset or posedge S_ACLK) begin\n        if (inverted_reset) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          axi_rst        <= 4'hf;\n        end else begin\n          rst_d1         <= #`TCQ 1'b0;\n          rst_d2         <= #`TCQ rst_d1;\n          axi_rst        <= #`TCQ {axi_rst[2:0],1'b0};\n        end\n      end\n\n      assign axi_rs_rst = axi_rst[3];//rst_d2;\n  end endgenerate // gaxi_rs_rst\n\n  generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming\n\n    // Write protection when almost full or prog_full is high\n    assign axis_we    = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : \n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign axis_re    = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :\n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? axis_we & S_ACLK_EN : axis_we;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE               (C_INTERFACE_TYPE),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 2  || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_AXIS),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_AXIS),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),\n        .C_USE_ECC                      (C_USE_ECC_AXIS),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_AXIS),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_axis_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (axis_wr_en),\n        .RD_EN                    (axis_rd_en),\n        .PROG_FULL_THRESH         (AXIS_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXIS_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .INJECTDBITERR            (AXIS_INJECTDBITERR), \n        .INJECTSBITERR            (AXIS_INJECTSBITERR),\n  \n        .DIN                      (axis_din),\n        .DOUT                     (axis_dout),\n        .FULL                     (axis_full),\n        .EMPTY                    (axis_empty),\n        .ALMOST_FULL              (axis_almost_full),\n        .PROG_FULL                (AXIS_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXIS_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (AXIS_OVERFLOW),\n        .VALID                    (),\n        .UNDERFLOW                (AXIS_UNDERFLOW),\n        .DATA_COUNT               (axis_dc),\n        .RD_DATA_COUNT            (AXIS_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXIS_WR_DATA_COUNT),\n        .SBITERR                  (AXIS_SBITERR),\n        .DBITERR                  (AXIS_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_axis),\n        .rd_rst_busy              (rd_rst_busy_axis),\n        .wr_rst_i_out             (axis_wr_rst),\n        .rd_rst_i_out             (axis_rd_rst),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign axis_s_axis_tready    = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;\n    assign axis_m_axis_tvalid    = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;\n    assign S_AXIS_TREADY         = axis_s_axis_tready;\n    assign M_AXIS_TVALID         = axis_m_axis_tvalid;\n\n  end endgenerate // axi_streaming\n\n  wire axis_wr_eop;\n  reg  axis_wr_eop_d1 = 1'b0;\n  wire axis_rd_eop;\n  integer  axis_pkt_cnt;\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)\n        axis_pkt_read    <= 1'b0;\n      else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_wr_eop_d1    <= 1'b0;\n      else\n        axis_wr_eop_d1   <= axis_wr_eop;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_cnt    <= 0;\n      else if (axis_wr_eop_d1 && ~axis_rd_eop)\n        axis_pkt_cnt    <= axis_pkt_cnt + 1;\n      else if (axis_rd_eop && ~axis_wr_eop_d1)\n        axis_pkt_cnt    <= axis_pkt_cnt - 1;\n    end\n  end endgenerate // gaxis_pkt_fifo_cc\n\n\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;\nwire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;\nwire axis_rd_has_rst;\nwire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;\nwire  [LOG_DEPTH_AXIS-1 : 0]  wpkt_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;\nwire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;\nwire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;\nwire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;\nwire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;\nreg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;\nreg adj_axis_wpkt_cnt_rd_pad_0 = 0;\nreg rpkt_inv_pad_0 = 0;\nwire axis_af_rd ;\n\ngenerate if (C_HAS_RST == 1) begin : rst_blk_has\n  assign axis_rd_has_rst = axis_rd_rst;\nend endgenerate //rst_blk_has\n\ngenerate if (C_HAS_RST == 0) begin :rst_blk_no\n  assign axis_rd_has_rst = 1'b0;\nend endgenerate //rst_blk_no\n\n   genvar i;\n\n   generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (LOG_DEPTH_AXIS)\n        )\n     rd_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (wpkt_q[i-1]), \n         .DOUT     (wpkt_q[i])\n        );\n \n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (1)\n        )\n     wr_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (axis_af_q[i-1]), \n         .DOUT     (axis_af_q[i])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (diff_pkt_cnt == 1))\n        axis_pkt_read    <= 1'b0;\n      else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt    <= 1'b0;\n      else if (axis_wr_eop)\n        axis_wpkt_cnt    <= axis_wpkt_cnt + 1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt_gc    <= 1'b0;\n      else \n        axis_wpkt_cnt_gc    <= bin2gray(axis_wpkt_cnt);\n    end\n\n\n    assign  wpkt_q[0]  = axis_wpkt_cnt_gc;\n    assign  axis_wpkt_cnt_gc_asreg_last       = wpkt_q[C_SYNCHRONIZER_STAGE];\n    assign  axis_af_q[0]                      = axis_almost_full;\n    //assign  axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];\n    assign  axis_af_rd                        = axis_af_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_wpkt_cnt_rd    <= 1'b0;\n      else \n        axis_wpkt_cnt_rd    <= gray2bin(axis_wpkt_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_rpkt_cnt    <= 1'b0;\n      else if (axis_rd_eop)\n        axis_rpkt_cnt    <= axis_rpkt_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;\n   assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1]             = ~axis_rpkt_cnt;\n   assign adj_axis_wpkt_cnt_rd_pad[0]                                = adj_axis_wpkt_cnt_rd_pad_0;\n   assign rpkt_inv_pad[0]                                            = rpkt_inv_pad_0;\n\n\n  always @ ( axis_rd_eop )\n    begin\n      if (!axis_rd_eop) begin\n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b1;\n        rpkt_inv_pad_0                <= 1'b1;\n      end else begin \n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b0;\n        rpkt_inv_pad_0                <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        diff_pkt_cnt_pad    <= 1'b0;\n      else \n        diff_pkt_cnt_pad    <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;\n    end\n\n   assign  diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;\n\n\n\n\n\n   end endgenerate // gaxis_pkt_fifo_ic\n\n\n\n\n  // Generate the accurate data count for axi stream packet fifo configuration\n  reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_dc_pkt_fifo <= 0;\n      else if (axis_wr_en && (~axis_rd_en))\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;\n      else if (~axis_wr_en && axis_rd_en)\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;\n    end\n    assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;\n  end endgenerate // gdc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt\n    assign AXIS_DATA_COUNT = 0;\n  end endgenerate // gndc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc\n    assign AXIS_DATA_COUNT = axis_dc;\n  end endgenerate // gdc\n\n  // Register Slice for Write Address Channel\n  generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_AXIS),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_AXIS)\n            )\n    axis_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (axis_din),\n          .S_VALID                   (axis_wr_en),\n          .S_READY                   (S_AXIS_TREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (axis_dout),\n          .M_VALID                   (M_AXIS_TVALID),\n          .M_READY                   (axis_rd_en)\n          );\n  end endgenerate // gaxis_reg_slice\n\n\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata\n    assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;\n    assign M_AXIS_TDATA   = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb\n    assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;\n    assign M_AXIS_TSTRB   = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep\n    assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;\n    assign M_AXIS_TKEEP   = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid\n    assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;\n    assign M_AXIS_TID     = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest\n    assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;\n    assign M_AXIS_TDEST   = axis_dout[TID_OFFSET-1:TDEST_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser\n    assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;\n    assign M_AXIS_TUSER   = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast\n    assign axis_din[0] = S_AXIS_TLAST;\n    assign M_AXIS_TLAST   = axis_dout[0];\n  end endgenerate\n\n  //###########################################################################\n  //  AXI FULL Write Channel (axi_write_channel)\n  //###########################################################################\n\n  localparam IS_AXI_FULL       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;\n  localparam IS_AXI_LITE       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;\n\n  localparam IS_AXI_FULL_WACH  = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WDCH  = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WRCH  = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RACH  = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RDCH  = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_AXI_LITE_WACH  = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WDCH  = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WRCH  = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RACH  = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RDCH  = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_WR_ADDR_CH     = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;\n  localparam IS_WR_DATA_CH     = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;\n  localparam IS_WR_RESP_CH     = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;\n  localparam IS_RD_ADDR_CH     = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;\n  localparam IS_RD_DATA_CH     = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;\n\n  localparam AWID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;\n  localparam AWADDR_OFFSET     = AWID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam AWLEN_OFFSET      = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;\n  localparam AWSIZE_OFFSET     = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;\n  localparam AWBURST_OFFSET    = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;\n  localparam AWLOCK_OFFSET     = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;\n  localparam AWCACHE_OFFSET    = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;\n  localparam AWPROT_OFFSET     = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam AWQOS_OFFSET      = AWPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam AWREGION_OFFSET   = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;\n  localparam AWUSER_OFFSET     = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;\n\n  localparam WID_OFFSET        = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;\n  localparam WDATA_OFFSET      = WID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam WSTRB_OFFSET      = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;\n  localparam WUSER_OFFSET      = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;\n\n  localparam BID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;\n  localparam BRESP_OFFSET      = BID_OFFSET - C_AXI_BRESP_WIDTH;\n  localparam BUSER_OFFSET      = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;\n\n\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_din          ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout         ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout_pkt     ;\n  wire                          wach_full         ;\n  wire                          wach_almost_full  ;\n  wire                          wach_prog_full    ;\n  wire                          wach_empty        ;\n  wire                          wach_almost_empty ;\n  wire                          wach_prog_empty   ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_din          ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_dout         ;\n  wire                          wdch_full         ;\n  wire                          wdch_almost_full  ;\n  wire                          wdch_prog_full    ;\n  wire                          wdch_empty        ;\n  wire                          wdch_almost_empty ;\n  wire                          wdch_prog_empty   ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_din          ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_dout         ;\n  wire                          wrch_full         ;\n  wire                          wrch_almost_full  ;\n  wire                          wrch_prog_full    ;\n  wire                          wrch_empty        ;\n  wire                          wrch_almost_empty ;\n  wire                          wrch_prog_empty   ;\n  wire                          axi_aw_underflow_i;\n  wire                          axi_w_underflow_i ;\n  wire                          axi_b_underflow_i ;\n  wire                          axi_aw_overflow_i ;\n  wire                          axi_w_overflow_i  ;\n  wire                          axi_b_overflow_i  ;\n  wire                          axi_wr_underflow_i;\n  wire                          axi_wr_overflow_i ;\n  wire                          wach_s_axi_awready;\n  wire                          wach_m_axi_awvalid;\n  wire                          wach_wr_en        ;\n  wire                          wach_rd_en        ;\n  wire                          wdch_s_axi_wready ;\n  wire                          wdch_m_axi_wvalid ;\n  wire                          wdch_wr_en        ;\n  wire                          wdch_rd_en        ;\n  wire                          wrch_s_axi_bvalid ;\n  wire                          wrch_m_axi_bready ;\n  wire                          wrch_wr_en        ;\n  wire                          wrch_rd_en        ;\n  wire                          txn_count_up      ;\n  wire                          txn_count_down    ;\n  wire                          awvalid_en        ;\n  wire                          awvalid_pkt       ;\n  wire                          awready_pkt       ;\n  integer                       wr_pkt_count      ;\n  wire                          wach_we           ;\n  wire                          wach_re           ;\n  wire                          wdch_we           ;\n  wire                          wdch_re           ;\n  wire                          wrch_we           ;\n  wire                          wrch_re           ;\n\n  generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel\n    // Write protection when almost full or prog_full is high\n    assign wach_we    = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wach_re    = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        wach_m_axi_awvalid & awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY && wach_m_axi_awvalid :\n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY : 1'b0;\n    assign wach_wr_en = (C_HAS_SLAVE_CE == 1)  ? wach_we & S_ACLK_EN : wach_we;\n    assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 2  || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),\n        .C_USE_ECC                      (C_USE_ECC_WACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wach_wr_en),\n        .RD_EN                    (wach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AW_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AW_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AW_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AW_INJECTSBITERR),\n  \n        .DIN                      (wach_din),\n        .DOUT                     (wach_dout_pkt),\n        .FULL                     (wach_full),\n        .EMPTY                    (wach_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_AW_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_AW_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_aw_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_aw_underflow_i),\n        .DATA_COUNT               (AXI_AW_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AW_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AW_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AW_SBITERR),\n        .DBITERR                  (AXI_AW_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wach),\n        .rd_rst_busy              (rd_rst_busy_wach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wach_s_axi_awready    = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;\n    assign wach_m_axi_awvalid   = ~wach_empty;\n    assign S_AXI_AWREADY        = wach_s_axi_awready;\n\n    assign AXI_AW_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;\n    assign AXI_AW_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_aw_overflow_i  : 0;\n\n  end endgenerate // axi_write_address_channel\n\n  // Register Slice for Write Address Channel\n  generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WACH)\n            )\n    wach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_din),\n          .S_VALID                   (S_AXI_AWVALID),\n          .S_READY                   (S_AXI_AWREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n  end endgenerate // gwach_reg_slice\n  \n  generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (1)\n            )\n    wach_pkt_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_dout_pkt),\n          .S_VALID                   (awvalid_pkt),\n          .S_READY                   (awready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n\n    assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;\n\n    assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; \n    assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset == 1) begin\n\twr_pkt_count <= 0;\n      end else begin\n\tif(txn_count_up == 1 && txn_count_down == 0) begin\n\t  wr_pkt_count <= wr_pkt_count + 1;\n\tend else if(txn_count_up == 0 && txn_count_down == 1) begin\n\t  wr_pkt_count <= wr_pkt_count - 1;\n\tend\n      end\n    end //Always end\n    assign awvalid_en = (wr_pkt_count > 0)?1:0;\n  end endgenerate\n  \n  generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr\n    assign awvalid_en    = 1;    \n    assign wach_dout     = wach_dout_pkt;\n    assign M_AXI_AWVALID = wach_m_axi_awvalid;\n  end\n  endgenerate\n\n\n\n  generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel\n    // Write protection when almost full or prog_full is high\n    assign wdch_we    = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wdch_re    = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;\n    assign wdch_wr_en = (C_HAS_SLAVE_CE == 1)  ? wdch_we & S_ACLK_EN : wdch_we;\n    assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;\n\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 2  || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),\n        .C_USE_ECC                      (C_USE_ECC_WDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wdch_wr_en),\n        .RD_EN                    (wdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_W_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_W_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_W_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_W_INJECTSBITERR),\n  \n        .DIN                      (wdch_din),\n        .DOUT                     (wdch_dout),\n        .FULL                     (wdch_full),\n        .EMPTY                    (wdch_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_W_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_W_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_w_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_w_underflow_i),\n        .DATA_COUNT               (AXI_W_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_W_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_W_WR_DATA_COUNT),\n        .SBITERR                  (AXI_W_SBITERR),\n        .DBITERR                  (AXI_W_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wdch),\n        .rd_rst_busy              (rd_rst_busy_wdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wdch_s_axi_wready     = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;\n    assign wdch_m_axi_wvalid = ~wdch_empty;\n    assign S_AXI_WREADY      = wdch_s_axi_wready;\n    assign M_AXI_WVALID      = wdch_m_axi_wvalid;\n\n    assign AXI_W_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i  : 0;\n    assign AXI_W_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_w_overflow_i   : 0;\n\n  end endgenerate // axi_write_data_channel\n\n  // Register Slice for Write Data Channel\n  generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WDCH)\n            )\n    wdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wdch_din),\n          .S_VALID                   (S_AXI_WVALID),\n          .S_READY                   (S_AXI_WREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wdch_dout),\n          .M_VALID                   (M_AXI_WVALID),\n          .M_READY                   (M_AXI_WREADY)\n          );\n  end endgenerate // gwdch_reg_slice\n\n  generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel\n    // Write protection when almost full or prog_full is high\n    assign wrch_we    = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wrch_re    = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;\n    assign wrch_wr_en = (C_HAS_MASTER_CE == 1)  ? wrch_we & M_ACLK_EN : wrch_we;\n    assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 2  || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WRCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WRCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),\n        .C_USE_ECC                      (C_USE_ECC_WRCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WRCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WRCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wrch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wrch_wr_en),\n        .RD_EN                    (wrch_rd_en),\n        .PROG_FULL_THRESH         (AXI_B_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_B_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .INJECTDBITERR            (AXI_B_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_B_INJECTSBITERR),\n  \n        .DIN                      (wrch_din),\n        .DOUT                     (wrch_dout),\n        .FULL                     (wrch_full),\n        .EMPTY                    (wrch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_B_PROG_FULL),\n        .PROG_EMPTY               (AXI_B_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_b_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_b_underflow_i),\n        .DATA_COUNT               (AXI_B_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_B_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_B_WR_DATA_COUNT),\n        .SBITERR                  (AXI_B_SBITERR),\n        .DBITERR                  (AXI_B_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wrch),\n        .rd_rst_busy              (rd_rst_busy_wrch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wrch_s_axi_bvalid = ~wrch_empty;\n    assign wrch_m_axi_bready     = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;\n    assign S_AXI_BVALID      = wrch_s_axi_bvalid;\n    assign M_AXI_BREADY      = wrch_m_axi_bready;\n\n    assign AXI_B_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i  : 0;\n    assign AXI_B_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_b_overflow_i   : 0;\n  end endgenerate // axi_write_resp_channel\n\n  // Register Slice for Write Response Channel\n  generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WRCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WRCH)\n            )\n    wrch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wrch_din),\n          .S_VALID                   (M_AXI_BVALID),\n          .S_READY                   (M_AXI_BREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wrch_dout),\n          .M_VALID                   (S_AXI_BVALID),\n          .M_READY                   (S_AXI_BREADY)\n          );\n  end endgenerate // gwrch_reg_slice\n\n\n    assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW  == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;\n    assign axi_wr_overflow_i  = C_USE_COMMON_OVERFLOW   == 1 ? (axi_aw_overflow_i  || axi_w_overflow_i  || axi_b_overflow_i)  : 0;\n\n  generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output\n    assign M_AXI_AWADDR    = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];    \n    assign M_AXI_AWLEN     = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];    \n    assign M_AXI_AWSIZE    = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];    \n    assign M_AXI_AWBURST   = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];    \n    assign M_AXI_AWLOCK    = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];    \n    assign M_AXI_AWCACHE   = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];    \n    assign M_AXI_AWQOS     = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];    \n    assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET]    = S_AXI_AWADDR;\n    assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET]   = S_AXI_AWLEN;\n    assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET]   = S_AXI_AWSIZE;\n    assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;\n    assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;\n    assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;\n    assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;\n    assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET]   = S_AXI_AWQOS;\n  end endgenerate // axi_wach_output\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion\n    assign M_AXI_AWREGION  = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];    \n  end endgenerate // axi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion\n    assign M_AXI_AWREGION  = 0;    \n  end endgenerate // naxi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser\n    assign M_AXI_AWUSER  = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];    \n  end endgenerate // axi_awuser\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser\n    assign M_AXI_AWUSER  = 0;    \n  end endgenerate // naxi_awuser\n\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid\n    assign M_AXI_AWID      = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];\n  end endgenerate //axi_awid\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid\n    assign M_AXI_AWID      = 0;\n  end endgenerate //naxi_awid\n\n  generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output\n    assign M_AXI_WDATA     = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n    assign M_AXI_WLAST     = wdch_dout[0];\n    assign wdch_din[WID_OFFSET-1:WDATA_OFFSET]   = S_AXI_WDATA;\n    assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;\n    assign wdch_din[0]   = S_AXI_WLAST;\n  end endgenerate // axi_wdch_output\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin\n    assign M_AXI_WID       = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];\n  end endgenerate\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin\n    assign M_AXI_WID       = 0;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin\n    assign M_AXI_WUSER     = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];    \n  end endgenerate\n  generate if (C_HAS_AXI_WUSER == 0) begin\n    assign M_AXI_WUSER       = 0;\n  end endgenerate\n\n  generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output\n    assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; \n    assign wrch_din[BID_OFFSET-1:BRESP_OFFSET]   = M_AXI_BRESP;\n  end endgenerate // axi_wrch_output\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser\n    assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];\n  end endgenerate // axi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser\n    assign S_AXI_BUSER = 0;\n  end endgenerate // naxi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid\n    assign S_AXI_BID   =  wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];\n  end endgenerate // axi_bid\n  \n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid\n    assign S_AXI_BID   =  0 ;\n  end endgenerate // naxi_bid  \n\n\n  generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1\n    assign wach_din        = {S_AXI_AWADDR, S_AXI_AWPROT};\n    assign M_AXI_AWADDR    = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];    \n  end endgenerate // axi_wach_output1\n\n  generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1\n    assign wdch_din        = {S_AXI_WDATA, S_AXI_WSTRB};\n    assign M_AXI_WDATA     = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n  end endgenerate // axi_wdch_output1\n\n  generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1\n    assign wrch_din        = M_AXI_BRESP;\n    assign S_AXI_BRESP     = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; \n  end endgenerate // axi_wrch_output1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1\n    assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET]     = S_AXI_AWUSER;\n  end endgenerate // gwach_din1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2\n    assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET]     = S_AXI_AWID;\n  end endgenerate // gwach_din2\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3\n    assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET]     = S_AXI_AWREGION;\n  end endgenerate // gwach_din3\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1\n    assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;\n  end endgenerate // gwdch_din1\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2\n    assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;\n  end endgenerate // gwdch_din2\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1\n    assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET]    = M_AXI_BUSER;\n  end endgenerate // gwrch_din1\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2\n    assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET]    = M_AXI_BID;\n  end endgenerate // gwrch_din2\n\n  //end of  axi_write_channel\n\n  //###########################################################################\n  //  AXI FULL Read Channel (axi_read_channel)\n  //###########################################################################\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_din            ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout           ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout_pkt       ;\n  wire                               rach_full           ;\n  wire                               rach_almost_full    ;\n  wire                               rach_prog_full      ;\n  wire                               rach_empty          ;\n  wire                               rach_almost_empty   ;\n  wire                               rach_prog_empty     ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_din            ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_dout           ;\n  wire                               rdch_full           ;\n  wire                               rdch_almost_full    ;\n  wire                               rdch_prog_full      ;\n  wire                               rdch_empty          ;\n  wire                               rdch_almost_empty   ;\n  wire                               rdch_prog_empty     ;\n  wire                               axi_ar_underflow_i  ;\n  wire                               axi_r_underflow_i   ;\n  wire                               axi_ar_overflow_i   ;\n  wire                               axi_r_overflow_i    ;\n  wire                               axi_rd_underflow_i  ;\n  wire                               axi_rd_overflow_i   ;\n  wire                               rach_s_axi_arready  ;\n  wire                               rach_m_axi_arvalid  ;\n  wire                               rach_wr_en          ;\n  wire                               rach_rd_en          ;\n  wire                               rdch_m_axi_rready   ;\n  wire                               rdch_s_axi_rvalid   ;\n  wire                               rdch_wr_en          ;\n  wire                               rdch_rd_en          ;\n  wire                               arvalid_pkt         ;\n  wire                               arready_pkt         ;\n  wire                               arvalid_en          ;\n  wire                               rdch_rd_ok          ;\n  wire                               accept_next_pkt     ;\n  integer                            rdch_free_space     ;\n  integer                            rdch_commited_space ;\n  wire                               rach_we             ;\n  wire                               rach_re             ;\n  wire                               rdch_we             ;\n  wire                               rdch_re             ;\n\n  localparam ARID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;\n  localparam ARADDR_OFFSET     = ARID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam ARLEN_OFFSET      = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;\n  localparam ARSIZE_OFFSET     = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;\n  localparam ARBURST_OFFSET    = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;\n  localparam ARLOCK_OFFSET     = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;\n  localparam ARCACHE_OFFSET    = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;\n  localparam ARPROT_OFFSET     = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam ARQOS_OFFSET      = ARPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam ARREGION_OFFSET   = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;\n  localparam ARUSER_OFFSET     = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;\n\n  localparam RID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;\n  localparam RDATA_OFFSET      = RID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam RRESP_OFFSET      = RDATA_OFFSET - C_AXI_RRESP_WIDTH;\n  localparam RUSER_OFFSET      = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;\n\n\n  generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rach_we    = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;\n\n    // Read protection when almost empty or prog_empty is high\n//    assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;\n    assign rach_re    = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        rach_m_axi_arvalid & arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY && rach_m_axi_arvalid :\n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY : 1'b0;\n    assign rach_wr_en = (C_HAS_SLAVE_CE == 1)  ? rach_we & S_ACLK_EN : rach_we;\n    assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;\n\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 2  || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),\n        .C_USE_ECC                      (C_USE_ECC_RACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_rach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rach_wr_en),\n        .RD_EN                    (rach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AR_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AR_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AR_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AR_INJECTSBITERR),\n  \n        .DIN                      (rach_din),\n        .DOUT                     (rach_dout_pkt),\n        .FULL                     (rach_full),\n        .EMPTY                    (rach_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_AR_PROG_FULL),\n        .PROG_EMPTY               (AXI_AR_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_ar_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_ar_underflow_i),\n        .DATA_COUNT               (AXI_AR_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AR_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AR_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AR_SBITERR),\n        .DBITERR                  (AXI_AR_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rach),\n        .rd_rst_busy              (rd_rst_busy_rach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rach_s_axi_arready    = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;\n    assign rach_m_axi_arvalid = ~rach_empty;\n    assign S_AXI_ARREADY      = rach_s_axi_arready;\n\n    assign AXI_AR_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;\n    assign AXI_AR_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_ar_overflow_i  : 0;\n\n  end endgenerate // axi_read_addr_channel\n\n  // Register Slice for Read Address Channel\n  generate if (C_RACH_TYPE == 1) begin : grach_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RACH)\n            )\n    rach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_din),\n          .S_VALID                   (S_AXI_ARVALID),\n          .S_READY                   (S_AXI_ARREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice\n\n  // Register Slice for Read Address Channel for MM Packet FIFO\n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (1)\n            )\n    reg_slice_mm_pkt_fifo_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_dout_pkt),\n          .S_VALID                   (arvalid_pkt),\n          .S_READY                   (arready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice_mm_pkt_fifo\n\n  \n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid\n    assign M_AXI_ARVALID      = rach_m_axi_arvalid;\n    assign rach_dout          = rach_dout_pkt;\n  end endgenerate // grach_m_axi_arvalid\n  \n  \n  generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd\n    assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;\n    assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;\n    assign accept_next_pkt  = rach_m_axi_arvalid && arready_pkt && arvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset) begin\n\trdch_commited_space <= 0;\n      end else begin\n\tif(rdch_rd_ok && !accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space-1;\n\tend else if(!rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);\n\tend else if(rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);\n\tend\n      end\n    end //Always end\n\n    always@(*) begin\n      rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));\n    end\n\n    assign arvalid_en = (rdch_free_space >= 0)?1:0;\n  end\n  endgenerate\n  \n  generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd\n    assign arvalid_en = 1;    \n  end\n  endgenerate\n\n  generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rdch_we    = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready  & M_AXI_RVALID : M_AXI_RVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign rdch_re    = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid  & S_AXI_RREADY : S_AXI_RREADY;\n    assign rdch_wr_en = (C_HAS_MASTER_CE == 1)  ? rdch_we & M_ACLK_EN : rdch_we;\n    assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 2  || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),\n        .C_USE_ECC                      (C_USE_ECC_RDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_RDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_rdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rdch_wr_en),\n        .RD_EN                    (rdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_R_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_R_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_R_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_R_INJECTSBITERR),\n  \n        .DIN                      (rdch_din),\n        .DOUT                     (rdch_dout),\n        .FULL                     (rdch_full),\n        .EMPTY                    (rdch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_R_PROG_FULL),\n        .PROG_EMPTY               (AXI_R_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_r_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_r_underflow_i),\n        .DATA_COUNT               (AXI_R_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_R_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_R_WR_DATA_COUNT),\n        .SBITERR                  (AXI_R_SBITERR),\n        .DBITERR                  (AXI_R_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rdch),\n        .rd_rst_busy              (rd_rst_busy_rdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rdch_s_axi_rvalid = ~rdch_empty;\n    assign rdch_m_axi_rready     = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;\n    assign S_AXI_RVALID      = rdch_s_axi_rvalid;\n    assign M_AXI_RREADY      = rdch_m_axi_rready;\n\n    assign AXI_R_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i  : 0;\n    assign AXI_R_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_r_overflow_i   : 0;\n\n  end endgenerate //axi_read_data_channel\n\n  // Register Slice for read Data Channel\n  generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RDCH)\n            )\n    rdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rdch_din),\n          .S_VALID                   (M_AXI_RVALID),\n          .S_READY                   (M_AXI_RREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rdch_dout),\n          .M_VALID                   (S_AXI_RVALID),\n          .M_READY                   (S_AXI_RREADY)\n          );\n  end endgenerate // grdch_reg_slice\n\n\n    assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;\n    assign axi_rd_overflow_i  = C_USE_COMMON_OVERFLOW  == 1 ? (axi_ar_overflow_i  || axi_r_overflow_i) : 0;\n\n\n  generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output\n    assign M_AXI_ARADDR    = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];    \n    assign M_AXI_ARLEN     = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];    \n    assign M_AXI_ARSIZE    = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];    \n    assign M_AXI_ARBURST   = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];    \n    assign M_AXI_ARLOCK    = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];    \n    assign M_AXI_ARCACHE   = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];    \n    assign M_AXI_ARPROT    = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];    \n    assign M_AXI_ARQOS     = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];    \n    assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET]    = S_AXI_ARADDR;\n    assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET]   = S_AXI_ARLEN;\n    assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET]   = S_AXI_ARSIZE;\n    assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;\n    assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;\n    assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;\n    assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;\n    assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET]   = S_AXI_ARQOS;\n  end endgenerate // axi_full_rach_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion\n    assign M_AXI_ARREGION  = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];    \n  end endgenerate // axi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion\n    assign M_AXI_ARREGION  = 0;    \n  end endgenerate // naxi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser\n    assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];    \n  end endgenerate // axi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser\n    assign M_AXI_ARUSER = 0;    \n  end endgenerate // naxi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid\n    assign M_AXI_ARID      = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];\n  end endgenerate // axi_arid\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid\n    assign M_AXI_ARID      = 0;\n  end endgenerate // naxi_arid\n\n  generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output\n    assign S_AXI_RDATA     = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];\n    assign S_AXI_RRESP     = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n    assign S_AXI_RLAST     = rdch_dout[0];\n    assign rdch_din[RID_OFFSET-1:RDATA_OFFSET]   = M_AXI_RDATA;\n    assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;\n    assign rdch_din[0] = M_AXI_RLAST;\n  end endgenerate // axi_full_rdch_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output\n    assign S_AXI_RUSER     = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];\n  end endgenerate // axi_full_ruser_output\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output\n    assign S_AXI_RUSER     =  0;\n  end endgenerate // axi_full_nruser_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid\n    assign S_AXI_RID       = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];\n  end endgenerate // axi_rid\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid\n    assign S_AXI_RID       = 0;\n  end endgenerate // naxi_rid\n\n  generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1\n    assign rach_din      = {S_AXI_ARADDR, S_AXI_ARPROT};\n    assign M_AXI_ARADDR  = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];\n    assign M_AXI_ARPROT  = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];\n  end endgenerate // axi_lite_rach_output\n\n  generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1\n    assign rdch_din      = {M_AXI_RDATA, M_AXI_RRESP};\n    assign S_AXI_RDATA   = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];\n    assign S_AXI_RRESP   = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n  end endgenerate // axi_lite_rdch_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1\n    assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET]     = S_AXI_ARUSER;\n  end endgenerate // grach_din1\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2\n    assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET]     = S_AXI_ARID;\n  end endgenerate // grach_din2\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin\n    assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1\n    assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET]     = M_AXI_RUSER;\n  end endgenerate // grdch_din1\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2\n    assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;\n  end endgenerate // grdch_din2\n\n  //end of axi_read_channel\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf\n    assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :\n                       (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :\n                       (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;\n  end endgenerate // gaxi_comm_uf\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of\n    assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :\n                      (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :\n                      (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;\n  end endgenerate // gaxi_comm_of\n  \n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  // Pass Through Logic or Wiring Logic\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  \n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Write Address Channel\n  generate if (C_WACH_TYPE == 2) begin : gwach_pass_through\n    assign M_AXI_AWID      = S_AXI_AWID;\n    assign M_AXI_AWADDR    = S_AXI_AWADDR;\n    assign M_AXI_AWLEN     = S_AXI_AWLEN;\n    assign M_AXI_AWSIZE    = S_AXI_AWSIZE;\n    assign M_AXI_AWBURST   = S_AXI_AWBURST;\n    assign M_AXI_AWLOCK    = S_AXI_AWLOCK;\n    assign M_AXI_AWCACHE   = S_AXI_AWCACHE;\n    assign M_AXI_AWPROT    = S_AXI_AWPROT;\n    assign M_AXI_AWQOS     = S_AXI_AWQOS;\n    assign M_AXI_AWREGION  = S_AXI_AWREGION;\n    assign M_AXI_AWUSER    = S_AXI_AWUSER;\n    assign S_AXI_AWREADY   = M_AXI_AWREADY;\n    assign M_AXI_AWVALID   = S_AXI_AWVALID;\n  end endgenerate // gwach_pass_through;\n\n  // Wiring logic for Write Data Channel\n  generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through\n    assign M_AXI_WID       = S_AXI_WID;\n    assign M_AXI_WDATA     = S_AXI_WDATA;\n    assign M_AXI_WSTRB     = S_AXI_WSTRB;\n    assign M_AXI_WLAST     = S_AXI_WLAST;\n    assign M_AXI_WUSER     = S_AXI_WUSER;\n    assign S_AXI_WREADY    = M_AXI_WREADY;\n    assign M_AXI_WVALID    = S_AXI_WVALID;\n  end endgenerate // gwdch_pass_through;\n\n  // Wiring logic for Write Response Channel\n  generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through\n    assign S_AXI_BID       = M_AXI_BID;\n    assign S_AXI_BRESP     = M_AXI_BRESP;\n    assign S_AXI_BUSER     = M_AXI_BUSER;\n    assign M_AXI_BREADY    = S_AXI_BREADY;\n    assign S_AXI_BVALID    = M_AXI_BVALID;\n  end endgenerate // gwrch_pass_through;\n\n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Read Address Channel\n  generate if (C_RACH_TYPE == 2) begin : grach_pass_through\n    assign M_AXI_ARID      = S_AXI_ARID;\n    assign M_AXI_ARADDR    = S_AXI_ARADDR;\n    assign M_AXI_ARLEN     = S_AXI_ARLEN;\n    assign M_AXI_ARSIZE    = S_AXI_ARSIZE;\n    assign M_AXI_ARBURST   = S_AXI_ARBURST;\n    assign M_AXI_ARLOCK    = S_AXI_ARLOCK;\n    assign M_AXI_ARCACHE   = S_AXI_ARCACHE;\n    assign M_AXI_ARPROT    = S_AXI_ARPROT;\n    assign M_AXI_ARQOS     = S_AXI_ARQOS;\n    assign M_AXI_ARREGION  = S_AXI_ARREGION;\n    assign M_AXI_ARUSER    = S_AXI_ARUSER;\n    assign S_AXI_ARREADY   = M_AXI_ARREADY;\n    assign M_AXI_ARVALID   = S_AXI_ARVALID;\n  end endgenerate // grach_pass_through;\n\n  // Wiring logic for Read Data Channel \n  generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through\n    assign S_AXI_RID      = M_AXI_RID;\n    assign S_AXI_RLAST    = M_AXI_RLAST;\n    assign S_AXI_RUSER    = M_AXI_RUSER;\n    assign S_AXI_RDATA    = M_AXI_RDATA;\n    assign S_AXI_RRESP    = M_AXI_RRESP;\n    assign S_AXI_RVALID   = M_AXI_RVALID;\n    assign M_AXI_RREADY   = S_AXI_RREADY;\n  end endgenerate // grdch_pass_through;\n\n  // Wiring logic for AXI Streaming\n  generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through\n    assign M_AXIS_TDATA   = S_AXIS_TDATA;\n    assign M_AXIS_TSTRB   = S_AXIS_TSTRB;\n    assign M_AXIS_TKEEP   = S_AXIS_TKEEP;\n    assign M_AXIS_TID     = S_AXIS_TID;\n    assign M_AXIS_TDEST   = S_AXIS_TDEST;\n    assign M_AXIS_TUSER   = S_AXIS_TUSER;\n    assign M_AXIS_TLAST   = S_AXIS_TLAST;\n    assign S_AXIS_TREADY  = M_AXIS_TREADY;\n    assign M_AXIS_TVALID  = S_AXIS_TVALID;\n  end endgenerate // gaxis_pass_through;\n\n\nendmodule //fifo_generator_v13_2_5\n\n\n\n/*******************************************************************************\n * Declaration of top-level module for Conventional FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_CONV_VER\n  #(\n    parameter  C_COMMON_CLOCK                 = 0,\n    parameter  C_INTERFACE_TYPE               = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_COUNT_TYPE                   = 0,\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DEFAULT_VALUE                = \"\",\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_ENABLE_RLOCS                 = 0,\n    parameter  C_FAMILY                       = \"virtex7\", //Not allowed in Verilog model\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_BACKUP                   = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_INT_CLK                  = 0,\n    parameter  C_HAS_MEMINIT_FILE             = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RD_RST                   = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_RST                   = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_INIT_WR_PNTR_VAL             = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_MIF_FILE_NAME                = \"\",\n    parameter  C_OPTIMIZATION_MODE            = 0,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PRIM_FIFO_TYPE               = \"\",\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_FREQ                      = 1,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_ECC                      = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_USE_FIFO16_FLAGS             = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_FREQ                      = 1,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_WR_RESPONSE_LATENCY          = 1,\n    parameter  C_MSGON_VAL                    = 1,\n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2,\n    parameter  C_AXI_TYPE                     = 0\n   )\n\n  (\n   input                               BACKUP,\n   input                               BACKUP_MARKER,\n   input                               CLK,\n   input                               RST,\n   input                               SRST,\n   input                               WR_CLK,\n   input                               WR_RST,\n   input                               RD_CLK,\n   input                               RD_RST,\n   input [C_DIN_WIDTH-1:0]             DIN,\n   input                               WR_EN,\n   input                               RD_EN,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_ASSERT,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_NEGATE,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_ASSERT,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_NEGATE,\n   input                               INT_CLK,\n   input                               INJECTDBITERR,\n   input                               INJECTSBITERR,\n  \n   output [C_DOUT_WIDTH-1:0]           DOUT,\n   output                              FULL,\n   output                              ALMOST_FULL,\n   output                              WR_ACK,\n   output                              OVERFLOW,\n   output                              EMPTY,\n   output                              ALMOST_EMPTY,\n   output                              VALID,\n   output                              UNDERFLOW,\n   output [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT,\n   output [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT,\n   output [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT,\n   output                              PROG_FULL,\n   output                              PROG_EMPTY,\n   output                              SBITERR,\n   output                              DBITERR,\n   output                              wr_rst_busy_o,\n   output                              wr_rst_busy,\n   output                              rd_rst_busy,\n   output                              wr_rst_i_out,\n   output                              rd_rst_i_out\n  );\n\n/*\n ******************************************************************************\n * Definition of Parameters\n ******************************************************************************\n *     C_COMMON_CLOCK                : Common Clock (1), Independent Clocks (0)\n *     C_COUNT_TYPE                  :    *not used\n *     C_DATA_COUNT_WIDTH            : Width of DATA_COUNT bus\n *     C_DEFAULT_VALUE               :    *not used\n *     C_DIN_WIDTH                   : Width of DIN bus\n *     C_DOUT_RST_VAL                : Reset value of DOUT\n *     C_DOUT_WIDTH                  : Width of DOUT bus\n *     C_ENABLE_RLOCS                :    *not used\n *     C_FAMILY                      : not used in bhv model\n *     C_FULL_FLAGS_RST_VAL          : Full flags rst val (0 or 1)\n *     C_HAS_ALMOST_EMPTY            : 1=Core has ALMOST_EMPTY flag\n *     C_HAS_ALMOST_FULL             : 1=Core has ALMOST_FULL flag\n *     C_HAS_BACKUP                  :    *not used\n *     C_HAS_DATA_COUNT              : 1=Core has DATA_COUNT bus\n *     C_HAS_INT_CLK                 : not used in bhv model\n *     C_HAS_MEMINIT_FILE            :    *not used\n *     C_HAS_OVERFLOW                : 1=Core has OVERFLOW flag\n *     C_HAS_RD_DATA_COUNT           : 1=Core has RD_DATA_COUNT bus\n *     C_HAS_RD_RST                  :    *not used\n *     C_HAS_RST                     : 1=Core has Async Rst\n *     C_HAS_SRST                    : 1=Core has Sync Rst\n *     C_HAS_UNDERFLOW               : 1=Core has UNDERFLOW flag\n *     C_HAS_VALID                   : 1=Core has VALID flag\n *     C_HAS_WR_ACK                  : 1=Core has WR_ACK flag\n *     C_HAS_WR_DATA_COUNT           : 1=Core has WR_DATA_COUNT bus\n *     C_HAS_WR_RST                  :    *not used\n *     C_IMPLEMENTATION_TYPE         : 0=Common-Clock Bram/Dram\n *                                     1=Common-Clock ShiftRam\n *                                     2=Indep. Clocks Bram/Dram\n *                                     3=Virtex-4 Built-in\n *                                     4=Virtex-5 Built-in\n *     C_INIT_WR_PNTR_VAL            :   *not used\n *     C_MEMORY_TYPE                 : 1=Block RAM\n *                                     2=Distributed RAM\n *                                     3=Shift RAM\n *                                     4=Built-in FIFO\n *     C_MIF_FILE_NAME               :   *not used\n *     C_OPTIMIZATION_MODE           :   *not used\n *     C_OVERFLOW_LOW                : 1=OVERFLOW active low\n *     C_PRELOAD_LATENCY             : Latency of read: 0, 1, 2\n *     C_PRELOAD_REGS                : 1=Use output registers\n *     C_PRIM_FIFO_TYPE              : not used in bhv model\n *     C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold\n *     C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold\n *     C_PROG_EMPTY_TYPE             : 0=No programmable empty\n *                                     1=Single prog empty thresh constant\n *                                     2=Multiple prog empty thresh constants\n *                                     3=Single prog empty thresh input\n *                                     4=Multiple prog empty thresh inputs\n *     C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold\n *     C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold\n *     C_PROG_FULL_TYPE              : 0=No prog full\n *                                     1=Single prog full thresh constant\n *                                     2=Multiple prog full thresh constants\n *                                     3=Single prog full thresh input\n *                                     4=Multiple prog full thresh inputs\n *     C_RD_DATA_COUNT_WIDTH         : Width of RD_DATA_COUNT bus\n *     C_RD_DEPTH                    : Depth of read interface (2^N)\n *     C_RD_FREQ                     : not used in bhv model\n *     C_RD_PNTR_WIDTH               : always log2(C_RD_DEPTH)\n *     C_UNDERFLOW_LOW               : 1=UNDERFLOW active low\n *     C_USE_DOUT_RST                : 1=Resets DOUT on RST\n *     C_USE_ECC                     : Used for error injection purpose\n *     C_USE_EMBEDDED_REG            : 1=Use BRAM embedded output register\n *     C_USE_FIFO16_FLAGS            : not used in bhv model\n *     C_USE_FWFT_DATA_COUNT         : 1=Use extra logic for FWFT data count\n *     C_VALID_LOW                   : 1=VALID active low\n *     C_WR_ACK_LOW                  : 1=WR_ACK active low\n *     C_WR_DATA_COUNT_WIDTH         : Width of WR_DATA_COUNT bus\n *     C_WR_DEPTH                    : Depth of write interface (2^N)\n *     C_WR_FREQ                     : not used in bhv model\n *     C_WR_PNTR_WIDTH               : always log2(C_WR_DEPTH)\n *     C_WR_RESPONSE_LATENCY         :    *not used\n *     C_MSGON_VAL                   :    *not used by bhv model\n *     C_ENABLE_RST_SYNC             : 0 = Use WR_RST & RD_RST\n *                                     1 = Use RST\n *     C_ERROR_INJECTION_TYPE        : 0 = No error injection\n *                                     1 = Single bit error injection only\n *                                     2 = Double bit error injection only\n *                                     3 = Single and double bit error injection\n ******************************************************************************\n * Definition of Ports\n ******************************************************************************\n *   BACKUP       : Not used\n *   BACKUP_MARKER: Not used\n *   CLK          : Clock\n *   DIN          : Input data bus\n *   PROG_EMPTY_THRESH       : Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag\n *   PROG_FULL_THRESH        : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag\n *   RD_CLK       : Read Domain Clock\n *   RD_EN        : Read enable\n *   RD_RST       : Read Reset\n *   RST          : Asynchronous Reset\n *   SRST         : Synchronous Reset\n *   WR_CLK       : Write Domain Clock\n *   WR_EN        : Write enable\n *   WR_RST       : Write Reset\n *   INT_CLK      : Internal Clock\n *   INJECTSBITERR: Inject Signle bit error\n *   INJECTDBITERR: Inject Double bit error\n *   ALMOST_EMPTY : One word remaining in FIFO\n *   ALMOST_FULL  : One empty space remaining in FIFO\n *   DATA_COUNT   : Number of data words in fifo( synchronous to CLK)\n *   DOUT         : Output data bus\n *   EMPTY        : Empty flag\n *   FULL         : Full flag\n *   OVERFLOW     : Last write rejected\n *   PROG_EMPTY   : Programmable Empty Flag\n *   PROG_FULL    : Programmable Full Flag\n *   RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)\n *   UNDERFLOW    : Last read rejected\n *   VALID        : Last read acknowledged, DOUT bus VALID\n *   WR_ACK       : Last write acknowledged\n *   WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)\n *   SBITERR      : Single Bit ECC Error Detected\n *   DBITERR      : Double Bit ECC Error Detected\n ******************************************************************************\n */\n\n  //----------------------------------------------------------------------------\n  //- Internal Signals for delayed input signals\n  //- All the input signals except Clock are delayed by 100 ps and then given to\n  //- the models.\n  //----------------------------------------------------------------------------\n \n  reg                         rst_delayed                       ;\n  reg                         empty_fb                       ;\n  reg                         srst_delayed                      ;\n  reg                         wr_rst_delayed                    ;\n  reg                         rd_rst_delayed                    ;\n  reg                         wr_en_delayed                     ;\n  reg                         rd_en_delayed                     ;\n  reg  [C_DIN_WIDTH-1:0]      din_delayed                       ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_delayed         ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_assert_delayed  ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_negate_delayed  ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_delayed          ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_assert_delayed   ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_negate_delayed   ;\n  reg                         injectdbiterr_delayed             ;\n  reg                         injectsbiterr_delayed             ;\n   wire                        empty_p0_out;\n\n  always @* rst_delayed                       <= #`TCQ RST                      ;\n  always @* empty_fb                       <= #`TCQ empty_p0_out                      ;\n  always @* srst_delayed                      <= #`TCQ SRST                     ; \n  always @* wr_rst_delayed                    <= #`TCQ WR_RST                   ; \n  always @* rd_rst_delayed                    <= #`TCQ RD_RST                   ; \n  always @* din_delayed                       <= #`TCQ DIN                      ; \n  always @* wr_en_delayed                     <= #`TCQ WR_EN                    ; \n  always @* rd_en_delayed                     <= #`TCQ RD_EN                    ; \n  always @* prog_empty_thresh_delayed         <= #`TCQ PROG_EMPTY_THRESH        ; \n  always @* prog_empty_thresh_assert_delayed  <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; \n  always @* prog_empty_thresh_negate_delayed  <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; \n  always @* prog_full_thresh_delayed          <= #`TCQ PROG_FULL_THRESH         ; \n  always @* prog_full_thresh_assert_delayed   <= #`TCQ PROG_FULL_THRESH_ASSERT  ; \n  always @* prog_full_thresh_negate_delayed   <= #`TCQ PROG_FULL_THRESH_NEGATE  ; \n  always @* injectdbiterr_delayed             <= #`TCQ INJECTDBITERR            ; \n  always @* injectsbiterr_delayed             <= #`TCQ INJECTSBITERR            ; \n\n  /*****************************************************************************\n   * Derived parameters\n   ****************************************************************************/\n  //There are 2 Verilog behavioral models\n  // 0 = Common-Clock FIFO/ShiftRam FIFO\n  // 1 = Independent Clocks FIFO\n  // 2 = Low Latency Synchronous FIFO\n  // 3 = Low Latency Asynchronous FIFO\n  localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :\n                              (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n\n  //Internal reset signals\n  reg                                rd_rst_asreg    = 1'b0;\n  reg                                rd_rst_asreg_d1 = 1'b0;\n  reg                                rd_rst_asreg_d2 = 1'b0;\n  reg                                rd_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_reg      = 1'b0;\n  reg                                rd_rst_comb     = 1'b1;\n  reg                                rd_rst_comb_d1  = 1'b0;\n  reg                                wr_rst_d0       = 1'b0;\n  reg                                wr_rst_d1       = 1'b0;\n  reg                                wr_rst_d2       = 1'b0;\n  reg                                rd_rst_d0       = 1'b0;\n  reg                                rd_rst_d1       = 1'b0;\n  reg                                rd_rst_d2       = 1'b0;\n  reg                                rd_rst_d3       = 1'b0;\n  reg                                wrrst_done      = 1'b0;\n  reg                                rdrst_done      = 1'b0;\n  reg                                wr_rst_asreg    = 1'b0;\n  reg                                wr_rst_asreg_d1 = 1'b0;\n  reg                                wr_rst_asreg_d2 = 1'b0;\n  reg                                wr_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_wr_d0    = 1'b0;\n  reg                                rd_rst_wr_d1    = 1'b0;\n  reg                                rd_rst_wr_d2    = 1'b0;\n  reg                                wr_rst_reg      = 1'b0;\n  reg                                rst_active_i    = 1'b1;\n  reg                                rst_delayed_d1  = 1'b1;\n  reg                                rst_delayed_d2  = 1'b1;\n  reg                                wr_rst_comb     = 1'b1;\n  reg                                wr_rst_comb_d1  = 1'b0;\n  wire                               wr_rst_i;\n  wire                               rd_rst_i;\n  wire                               rst_i;\n\n  //Internal reset signals\n  reg                                rst_asreg     = 1'b0;\n  reg                                srst_asreg    = 1'b0;\n  reg                                rst_asreg_d1  = 1'b0;\n  reg                                rst_asreg_d2  = 1'b0;\n  reg                                srst_asreg_d1 = 1'b0;\n  reg                                srst_asreg_d2 = 1'b0;\n  reg                                rst_reg       = 1'b0;\n  reg                                srst_reg      = 1'b0;\n  reg                                rst_comb      = 1'b1;\n  reg                                rst_comb_d1   = 1'b0;\n  wire                               srst_comb;\n  reg                                rst_full_gen_i = 0;\n  reg                                rst_full_ff_i = 0;\n  reg  [2:0]                         sckt_ff0_bsy_o_i = {3{1'b0}};\n                                     \n  wire                               RD_CLK_P0_IN;\n  wire                               RST_P0_IN;\n  wire                               RD_EN_FIFO_IN;\n  wire                               RD_EN_P0_IN;\n\n  wire                               ALMOST_EMPTY_FIFO_OUT;\n  wire                               ALMOST_FULL_FIFO_OUT;\n  wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT_FIFO_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DOUT_FIFO_OUT;\n  wire                               EMPTY_FIFO_OUT;\n  wire                               fifo_empty_fb;\n  wire                               FULL_FIFO_OUT;\n  wire                               OVERFLOW_FIFO_OUT;\n  wire                               PROG_EMPTY_FIFO_OUT;\n  wire                               PROG_FULL_FIFO_OUT;\n  wire                               VALID_FIFO_OUT;\n  wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT_FIFO_OUT;\n  wire                               UNDERFLOW_FIFO_OUT;\n  wire                               WR_ACK_FIFO_OUT;\n  wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT_FIFO_OUT;\n\n\n  //***************************************************************************\n  // Internal Signals\n  //   The core uses either the internal_ wires or the preload0_ wires depending\n  //     on whether the core uses Preload0 or not.\n  //   When using preload0, the internal signals connect the internal core to\n  //     the preload logic, and the external core's interfaces are tied to the\n  //     preload0 signals from the preload logic.\n  //***************************************************************************\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_OUT;\n  wire                               VALID_P0_OUT;\n  wire                               EMPTY_P0_OUT;\n  wire                               ALMOSTEMPTY_P0_OUT;\n  reg                                EMPTY_P0_OUT_Q;\n  reg                                ALMOSTEMPTY_P0_OUT_Q;\n  wire                               UNDERFLOW_P0_OUT;\n  wire                               RDEN_P0_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_IN;\n  wire                               EMPTY_P0_IN;\n  reg  [31:0]                        DATA_COUNT_FWFT;\n  reg                                SS_FWFT_WR  ;\n  reg                                SS_FWFT_RD ;\n\n  wire                               sbiterr_fifo_out;\n  wire                               dbiterr_fifo_out;\n  wire                               inject_sbit_err;\n  wire                               inject_dbit_err;\n  wire                               sckt_wr_rst_i;\n  wire                               sckt_rd_rst_i;\n  reg                                sckt_wr_rst_i_q = 1'b0;\n \n  wire                               w_fab_read_data_valid_i;\n  wire                               w_read_data_valid_i;\n  wire                               w_ram_valid_i;\n  // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.\n  assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectsbiterr_delayed : 0;\n  assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectdbiterr_delayed : 0;\n                           \n  assign wr_rst_i_out = wr_rst_i;\n  assign rd_rst_i_out = rd_rst_i;\n  assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];\n  generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o\n    wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;\n    always @ (posedge clk_i)\n      sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; \n  end endgenerate \n// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL\n// parameter (1=Independent Clocks, 0=Common Clock)\n\n  localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;\ngenerate\ncase (C_VERILOG_IMPL)\n0 : begin : block1_ss\n  //Common Clock Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_ss\n  #(\n    .C_FAMILY                            (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                  (C_DATA_COUNT_WIDTH),            \n    .C_DIN_WIDTH                         (C_DIN_WIDTH),                   \n    .C_DOUT_RST_VAL                      (C_DOUT_RST_VAL),                \n    .C_DOUT_WIDTH                        (C_DOUT_WIDTH),                  \n    .C_FULL_FLAGS_RST_VAL                (FULL_FLAGS_RST_VAL),            \n    .C_HAS_ALMOST_EMPTY                  (C_HAS_ALMOST_EMPTY),            \n    .C_HAS_ALMOST_FULL                   ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),             \n    .C_HAS_DATA_COUNT                    (C_HAS_DATA_COUNT),              \n    .C_HAS_OVERFLOW                      (C_HAS_OVERFLOW),                \n    .C_HAS_RD_DATA_COUNT                 (C_HAS_RD_DATA_COUNT),           \n    .C_HAS_RST                           (C_EN_SAFETY_CKT?0:C_HAS_RST),                     \n    .C_HAS_SRST                          (C_EN_SAFETY_CKT?1:C_HAS_SRST),                    \n    .C_HAS_UNDERFLOW                     (C_HAS_UNDERFLOW),               \n    .C_HAS_VALID                         (C_HAS_VALID),                   \n    .C_HAS_WR_ACK                        (C_HAS_WR_ACK),                  \n    .C_HAS_WR_DATA_COUNT                 (C_HAS_WR_DATA_COUNT),           \n    .C_IMPLEMENTATION_TYPE               (C_IMPLEMENTATION_TYPE),         \n    .C_MEMORY_TYPE                       (C_MEMORY_TYPE),                 \n    .C_OVERFLOW_LOW                      (C_OVERFLOW_LOW),                \n    .C_PRELOAD_LATENCY                   (C_PRELOAD_LATENCY),             \n    .C_PRELOAD_REGS                      (C_PRELOAD_REGS),                \n    .C_PROG_EMPTY_THRESH_ASSERT_VAL      (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL      (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                   (C_PROG_EMPTY_TYPE),             \n    .C_PROG_FULL_THRESH_ASSERT_VAL       (C_PROG_FULL_THRESH_ASSERT_VAL), \n    .C_PROG_FULL_THRESH_NEGATE_VAL       (C_PROG_FULL_THRESH_NEGATE_VAL), \n    .C_PROG_FULL_TYPE                    (C_PROG_FULL_TYPE),              \n    .C_RD_DATA_COUNT_WIDTH               (C_RD_DATA_COUNT_WIDTH),         \n    .C_RD_DEPTH                          (C_RD_DEPTH),                    \n    .C_RD_PNTR_WIDTH                     (C_RD_PNTR_WIDTH),               \n    .C_UNDERFLOW_LOW                     (C_UNDERFLOW_LOW),               \n    .C_USE_DOUT_RST                      (C_USE_DOUT_RST),                \n    .C_USE_EMBEDDED_REG                  (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                     (C_EN_SAFETY_CKT),            \n    .C_USE_FWFT_DATA_COUNT               (C_USE_FWFT_DATA_COUNT),         \n    .C_VALID_LOW                         (C_VALID_LOW),                   \n    .C_WR_ACK_LOW                        (C_WR_ACK_LOW),                  \n    .C_WR_DATA_COUNT_WIDTH               (C_WR_DATA_COUNT_WIDTH),         \n    .C_WR_DEPTH                          (C_WR_DEPTH),                    \n    .C_WR_PNTR_WIDTH                     (C_WR_PNTR_WIDTH),               \n    .C_USE_ECC                           (C_USE_ECC),                     \n    .C_ENABLE_RST_SYNC                   (C_ENABLE_RST_SYNC),             \n    .C_ERROR_INJECTION_TYPE              (C_ERROR_INJECTION_TYPE),\n    .C_FIFO_TYPE                         (C_FIFO_TYPE)                     \n  )\n  gen_ss\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .CLK                      (CLK),\n    .RST                      (C_EN_SAFETY_CKT?1'b0:rst_i),\n    .SRST                     (C_EN_SAFETY_CKT?sckt_wr_rst_i:srst_delayed),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .USER_EMPTY_FB            (empty_fb),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .DATA_COUNT               (DATA_COUNT_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .WR_RST_BUSY              (wr_rst_busy),\n    .RD_RST_BUSY              (rd_rst_busy),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n1 : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT), \n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .fab_read_data_valid_i    (w_fab_read_data_valid_i),\n    .read_data_valid_i        (w_read_data_valid_i),\n    .ram_valid_i              (w_ram_valid_i),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\n2 : begin : ll_afifo_inst\n  fifo_generator_v13_2_5_beh_ver_ll_afifo\n  #(\n    .C_DIN_WIDTH                    (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                 (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                   (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_RD_DATA_COUNT            (C_HAS_RD_DATA_COUNT),\n    .C_HAS_WR_DATA_COUNT            (C_HAS_WR_DATA_COUNT),\n    .C_RD_DEPTH                     (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                (C_RD_PNTR_WIDTH),\n    .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n    .C_WR_DATA_COUNT_WIDTH          (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                     (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                (C_WR_PNTR_WIDTH),\n    .C_FIFO_TYPE                    (C_FIFO_TYPE)\n   )\n  gen_ll_afifo\n  (\n    .DIN                        (din_delayed),\n    .RD_CLK                     (RD_CLK),\n    .RD_EN                      (rd_en_delayed),\n    .WR_RST                     (wr_rst_i),\n    .RD_RST                     (rd_rst_i),\n    .WR_CLK                     (WR_CLK),\n    .WR_EN                      (wr_en_delayed),\n    .DOUT                       (DOUT),\n    .EMPTY                      (EMPTY),\n    .FULL                       (FULL)\n  );\nend\ndefault : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT),\n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\nendcase\nendgenerate\n\n\n   //**************************************************************************\n   // Connect Internal Signals\n   //   (Signals labeled internal_*)\n   //  In the normal case, these signals tie directly to the FIFO's inputs and\n   //    outputs.\n   //  In the case of Preload Latency 0 or 1, there are intermediate\n   //    signals between the internal FIFO and the preload logic.\n   //**************************************************************************\n   \n   \n   //***********************************************\n   // If First-Word Fall-Through, instantiate\n   // the preload0 (FWFT) module\n   //***********************************************\n   wire                        rd_en_to_fwft_fifo;\n   wire                        sbiterr_fwft;\n   wire                        dbiterr_fwft;\n   wire [C_DOUT_WIDTH-1:0]     dout_fwft;\n   wire                        empty_fwft;\n   wire                        rd_en_fifo_in;\n   wire                        stage2_reg_en_i;\n   wire [1:0]                  valid_stages_i;\n   wire                        rst_fwft;\n   //wire                        empty_p0_out;\n   reg  [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n   localparam IS_PKT_FIFO      = (C_FIFO_TYPE == 1) ? 1 : 0;\n   localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;\n   assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2_fwft\n\n\n         fifo_generator_v13_2_5_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_EMBEDDED_REG  (C_USE_EMBEDDED_REG),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (C_FIFO_TYPE)\n             )\n             fgpl0\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (RST_P0_IN),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (RD_EN_P0_IN),\n                .FIFOEMPTY        (EMPTY_P0_IN),\n                .FIFODATA         (DATA_P0_IN),\n                .FIFOSBITERR      (sbiterr_fifo_out),\n                .FIFODBITERR      (dbiterr_fifo_out),\n                // Output\n                .USERDATA         (dout_fwft),\n                .USERVALID        (VALID_P0_OUT),\n                .USEREMPTY        (empty_fwft),\n                .USERALMOSTEMPTY  (ALMOSTEMPTY_P0_OUT),\n                .USERUNDERFLOW    (UNDERFLOW_P0_OUT),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_fifo_in),\n                .USERSBITERR      (sbiterr_fwft),\n                .USERDBITERR      (dbiterr_fwft),\n                .STAGE2_REG_EN    (stage2_reg_en_i),\n                .fab_read_data_valid_i_o    (w_fab_read_data_valid_i),\n                .read_data_valid_i_o        (w_read_data_valid_i),\n                .ram_valid_i_o              (w_ram_valid_i),\n                .VALID_STAGES                (valid_stages_i)\n                );\n\n         \n         //***********************************************\n         // Connect inputs to preload (FWFT) module\n         //***********************************************\n         //Connect the RD_CLK of the Preload (FWFT) module to CLK if we \n         // have a common-clock FIFO, or RD_CLK if we have an \n         // independent clock FIFO\n         assign RD_CLK_P0_IN       = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);\n         assign RST_P0_IN          = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;\n         assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n         assign EMPTY_P0_IN        = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;\n         assign DATA_P0_IN         = DOUT_FIFO_OUT;\n         \n         //***********************************************\n         // Connect outputs from preload (FWFT) module\n         //***********************************************\n         assign VALID              = VALID_P0_OUT ;\n         assign ALMOST_EMPTY       = ALMOSTEMPTY_P0_OUT;\n         assign UNDERFLOW          = UNDERFLOW_P0_OUT ;\n         \n         assign RD_EN_FIFO_IN      = rd_en_fifo_in;\n         \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:\n           (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : \n           DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];  \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               EMPTY_P0_OUT_Q       <= 1;\n               ALMOSTEMPTY_P0_OUT_Q <= 1;\n            end else begin\n               EMPTY_P0_OUT_Q       <= #`TCQ empty_p0_out;\n//               EMPTY_P0_OUT_Q       <= #`TCQ EMPTY_FIFO_OUT;\n               ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;\n            end\n         end //always\n         \n         \n         //***********************************************\n         // logic for common-clock data count when FWFT is selected\n         //***********************************************\n         initial begin\n            SS_FWFT_RD = 1'b0;\n            DATA_COUNT_FWFT = 0 ;\n            SS_FWFT_WR   = 1'b0 ;\n         end //initial\n         \n         \n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter. SS_FWFT_WR and SS_FWFT_RD\n         // are the up/down enables for the counter.\n         //***********************************************\n         always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin\n            if (C_VALID_LOW == 1) begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;\n            end else begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;\n            end\n            SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT))  ;\n         end \n\n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter for FWFT. This always block \n         // calculates the counter.\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               DATA_COUNT_FWFT      <= 0;\n            end else begin\n               //if (srst_delayed && (C_HAS_SRST == 1) ) begin\n               if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin\n                  DATA_COUNT_FWFT      <= #`TCQ 0;\n               end else begin\n                  case ( {SS_FWFT_WR, SS_FWFT_RD})\n                    2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                    2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;\n                    2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;\n                    2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                  endcase  \n               end //if SRST\n            end //IF RST\n         end //always\n\n      end endgenerate // : block2\n\n    // AXI Streaming Packet FIFO\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_plus1 = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_reg   = 0;\n    reg                         partial_packet     = 0;\n    reg                         stage1_eop_d1      = 0;\n    reg                         rd_en_fifo_in_d1   = 0;\n    reg                         eop_at_stage2      = 0;\n    reg                         ram_pkt_empty      = 0;\n    reg                         ram_pkt_empty_d1   = 0;\n\n    wire [C_DOUT_WIDTH-1:0]     dout_p0_out;\n    wire                        packet_empty_wr;\n    wire                        wr_rst_fwft_pkt_fifo;\n    wire                        dummy_wr_eop;\n    wire                        ram_wr_en_pkt_fifo;\n    wire                        wr_eop;\n    wire                        ram_rd_en_compare;\n    wire                        stage1_eop;\n    wire                        pkt_ready_to_read;\n    wire                        rd_en_2_stage2;\n\n    // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)\n    // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP\n    // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of\n    // write packet count\n    generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop\n       always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n          if (wr_rst_fwft_pkt_fifo)\n             partial_packet   <= 1'b0;\n          else begin\n             if (srst_delayed | wr_rst_busy | rd_rst_busy)\n                partial_packet <= #`TCQ 1'b0;\n             else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))\n                partial_packet <= #`TCQ 1'b1;\n             else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)\n                partial_packet <= #`TCQ 1'b0;\n          end\n        end\n    end endgenerate // gdummy_wr_eop\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin : gpkt_fifo_fwft\n      assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;\n      assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);\n      assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];\n  \n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft) begin\n          stage1_eop_d1    <= 1'b0;\n          rd_en_fifo_in_d1 <= 1'b0;\n        end else begin\n          if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            stage1_eop_d1    <= #`TCQ 1'b0;\n            rd_en_fifo_in_d1 <= #`TCQ 1'b0;\n          end else begin\n            stage1_eop_d1    <= #`TCQ stage1_eop;\n            rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;\n          end\n        end\n      end\n      assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;\n      assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);\n      assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);\n      assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;\n\n\n         fifo_generator_v13_2_5_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (2) // Enable low latency fwft logic\n             )\n         pkt_fifo_fwft\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (rst_fwft),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (rd_en_delayed),\n                .FIFOEMPTY        (pkt_ready_to_read),\n                .FIFODATA         (dout_fwft),\n                .FIFOSBITERR      (sbiterr_fwft),\n                .FIFODBITERR      (dbiterr_fwft),\n                // Output\n                .USERDATA         (dout_p0_out),\n                .USERVALID        (),\n                .USEREMPTY        (empty_p0_out),\n                .USERALMOSTEMPTY  (),\n                .USERUNDERFLOW    (),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_2_stage2),\n                .USERSBITERR      (SBITERR),\n                .USERDBITERR      (DBITERR),\n                .STAGE2_REG_EN    (),\n                .VALID_STAGES     ()\n                );\n\n      assign pkt_ready_to_read  = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));\n      assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft)\n          eop_at_stage2 <= 1'b0;\n        else if (stage2_reg_en_i)\n          eop_at_stage2 <= #`TCQ stage1_eop;\n      end\n\n      //---------------------------------------------------------------------------\n      // Write and Read Packet Count\n      //---------------------------------------------------------------------------\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count  <= 0;\n         else if (srst_delayed  | wr_rst_busy | rd_rst_busy)\n            wr_pkt_count  <= #`TCQ 0;\n         else if (wr_eop)\n            wr_pkt_count  <= #`TCQ wr_pkt_count + 1;\n      end\n    \n    end endgenerate //: gpkt_fifo_fwft\n\n    assign DOUT               = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;\n    assign EMPTY              = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            rd_pkt_count       <= 0;\n            rd_pkt_count_plus1 <= 1;\n         end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            rd_pkt_count       <= #`TCQ 0;\n            rd_pkt_count_plus1 <= #`TCQ 1;\n         end else if (stage2_reg_en_i && stage1_eop) begin\n            rd_pkt_count       <= #`TCQ rd_pkt_count + 1;\n            rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;\n         end\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (SRST | wr_rst_busy | rd_rst_busy) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n    end endgenerate //grss_pkt_cnt\n    \n    localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;\n    reg  [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_b2g = 0;\n    wire [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_rd;\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt\n      // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count_b2g  <= 0;\n         else\n            wr_pkt_count_b2g  <= #`TCQ wr_pkt_count;\n      end\n\n      // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            wr_pkt_count_q       <= 0;\n         else\n            wr_pkt_count_q       <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};\n      end\n\n      always @* begin\n        if (stage1_eop)\n           rd_pkt_count    <= rd_pkt_count_reg + 1;\n        else\n           rd_pkt_count    <= rd_pkt_count_reg;\n      end\n\n      assign wr_pkt_count_rd    = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            rd_pkt_count_reg       <= 0;\n         else if (rd_en_fifo_in)\n            rd_pkt_count_reg       <= #`TCQ rd_pkt_count;\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (rd_pkt_count != wr_pkt_count_rd) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n\n      // Synchronize the empty in write domain\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            pkt_empty_sync  <= 'b1;\n         else\n            pkt_empty_sync  <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};\n      end\n\n    end endgenerate //gras_pkt_cnt\n\n   generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO\n\n     //***********************************************\n     // If NOT First-Word Fall-Through, wire the outputs\n     // of the internal _ss or _as FIFO directly to the\n     // output, and do not instantiate the preload0\n     // module.\n     //***********************************************\n\n     assign RD_CLK_P0_IN       = 0;\n     assign RST_P0_IN          = 0;\n     assign RD_EN_P0_IN        = 0;\n\n     assign RD_EN_FIFO_IN      = rd_en_delayed;\n\n     assign DOUT               = DOUT_FIFO_OUT;\n     assign DATA_P0_IN         = 0;\n     assign VALID              = VALID_FIFO_OUT;\n     assign EMPTY              = EMPTY_FIFO_OUT;\n     assign ALMOST_EMPTY       = ALMOST_EMPTY_FIFO_OUT;\n     assign EMPTY_P0_IN        = 0;\n     assign UNDERFLOW          = UNDERFLOW_FIFO_OUT;\n     assign DATA_COUNT         = DATA_COUNT_FIFO_OUT;\n     assign SBITERR            = sbiterr_fifo_out;\n     assign DBITERR            = dbiterr_fifo_out;\n\n   end endgenerate // STD_FIFO\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO\n     assign empty_p0_out       = empty_fwft;\n     assign SBITERR            = sbiterr_fwft;\n     assign DBITERR            = dbiterr_fwft;\n     assign DOUT               = dout_fwft;\n     assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n\n   end endgenerate // NO_PKT_FIFO\n\n   //***********************************************\n   // Connect user flags to internal signals\n   //***********************************************\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3\n      if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);\n      end //block_ic\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3\n   endgenerate\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30\n       if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30\n   endgenerate\n\n\n    \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both\n       if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30_both\n   endgenerate\n\n generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both\n      if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));\n      end //block_ic_both\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3_both\n   endgenerate\n\n\n   //If we are not using extra logic for the FWFT data count,\n   //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the\n   //internal FIFO instance  \n   generate\n      if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n   //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal\n   //FIFO instance\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1) begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n      else begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n\n   //Connect other flags to the internal FIFO instance\n   assign       FULL        = FULL_FIFO_OUT;\n   assign       ALMOST_FULL = ALMOST_FULL_FIFO_OUT;\n   assign       WR_ACK      = WR_ACK_FIFO_OUT;\n   assign       OVERFLOW    = OVERFLOW_FIFO_OUT;\n   assign       PROG_FULL   = PROG_FULL_FIFO_OUT;\n   assign       PROG_EMPTY  = PROG_EMPTY_FIFO_OUT;\n\n\n  /**************************************************************************\n  * find_log2\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n   // if an asynchronous FIFO has been selected, display a message that the FIFO\n   //   will not be cycle-accurate in simulation\n   initial begin\n      if (C_IMPLEMENTATION_TYPE == 2) begin\n         $display(\"WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.\");\n      end else if (C_MEMORY_TYPE == 4) begin\n         $display(\"FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.\");\n         $finish;\n      end\n\n      if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin\n         $display(\"FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.\");\n         $finish;\n      end\n\n      if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin\n         $display(\"FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.\");\n         $finish;\n      end\n\n      if (C_USE_ECC == 1) begin\n         if (C_DIN_WIDTH != C_DOUT_WIDTH) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.\");\n            $finish;\n         end\n         if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.\");\n            $finish;\n         end\n      end\n\n   end //initial\n\n  /**************************************************************************\n  * Internal reset logic\n  **************************************************************************/\n  assign wr_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg|sckt_wr_rst_i : 0;\n  assign rd_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg|sckt_rd_rst_i : 0;\n  assign rst_i            = C_HAS_RST ? rst_reg|sckt_wr_rst_i : 0;\n\n  wire rst_2_sync;\n  wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;\n\n  localparam RST_SYNC_STAGES = C_EN_SAFETY_CKT == 0 ? C_COMMON_CLOCK ? C_SYNCHRONIZER_STAGE : C_SYNCHRONIZER_STAGE+2 : 5;\n  localparam RST_BUSY_LEN    = 4;\n  reg  wr_rst_busy_i = 0;\n  reg  rd_rst_busy_i = 0;\n  generate\n      if (C_ENABLE_RST_SYNC == 0 || (C_HAS_RST == 0 && C_HAS_SRST == 0)) begin : gnrst_sync\n        always @* begin\n          wr_rst_reg <= wr_rst_delayed;\n          rd_rst_reg <= rd_rst_delayed;\n          rst_reg    <= 1'b0;\n          srst_reg    <= 1'b0;\n        end\n        assign rst_2_sync = wr_rst_delayed;\n        assign wr_rst_busy = 1'b0;\n        assign wr_rst_busy_o = 1'b0;\n        assign rd_rst_busy = 1'b0;\n        assign sckt_wr_rst_i = 1'b0;\n        assign sckt_rd_rst_i = 1'b0;\n      end // gnrst_sync\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 0) begin : g7s_ic_rst_nsckt\n        reg [1:0]                 arst_sync_wr  = 2'b11;\n        reg [1:0]                 arst_sync_rd  = 2'b11;\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge WR_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge RD_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_rd    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_rd    <= #`TCQ {arst_sync_rd[0], rst_delayed};\n        end\n        always @(posedge WR_CLK) begin\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n\tend\n        always @(posedge WR_CLK or posedge arst_sync_wr[1]) begin\n\t  if (arst_sync_wr[1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n            rd_rst_wr_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            rd_rst_wr_ext  <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t    if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t      sckt_wr_rst_ic <= #`TCQ 1'b0;\n            else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t      wr_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n        always @(posedge RD_CLK) begin\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], sckt_wr_rst_ic};\n\tend\n        always @(posedge RD_CLK or posedge arst_sync_rd[1]) begin\n\t  if (arst_sync_rd[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n            wr_rst_rd_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            wr_rst_rd_ext  <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t    if (wr_rst_rd_ext[1]) begin\n\t      sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t      rd_rst_busy_i  <= #`TCQ 1'b0;\n\t    end\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic|arst_sync_wr[1];\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic|arst_sync_rd[1];\n      end // g7s_ic_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 1) begin : g7s_ic_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] arst_sync_rd  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        always @(posedge WR_CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n          rd_rst_wr_ext    <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_wr[RST_SYNC_STAGES-1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n          end else if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t    sckt_wr_rst_ic <= #`TCQ 1'b0;\n          else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t    wr_rst_busy_i  <= #`TCQ 1'b0;\n\tend\n        always @(posedge RD_CLK) begin\n\t  arst_sync_rd     <= #`TCQ {arst_sync_rd[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n          wr_rst_rd_ext    <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_rd[RST_SYNC_STAGES-1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n\t  end else if (wr_rst_rd_ext[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t    rd_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic;\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic;\n      end // g7s_ic_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 0) begin : g7s_cc_rst_nsckt\n        reg [1:0]              arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge CLK) begin\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0] | arst_sync_wr[1]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc | arst_sync_wr[1];\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 1) begin : g7s_cc_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n\n        always @(posedge CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc;\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst\n        assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;\n        assign rd_rst_busy = rst_reg;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = rst_reg;\n        always @* rst_full_ff_i  <= 1'b0;\n        always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;\n\n        always @(posedge CLK) begin\n          rst_delayed_d1 <= #`TCQ srst_delayed;\n          rst_delayed_d2 <= #`TCQ rst_delayed_d1;\n          if (rst_reg || rst_delayed_d2) begin\n            rst_active_i <= #`TCQ 1'b1;\n          end else begin\n            rst_active_i <= #`TCQ rst_reg;\n          end    \n        end   \n        always @(posedge CLK) begin\n          if (~rst_reg && srst_delayed) begin\n             rst_reg <= #`TCQ 1'b1;\n           end else if (rst_reg) begin\n             rst_reg <= #`TCQ 1'b0;\n           end else begin\n             rst_reg <= #`TCQ rst_reg;\n           end    \n        end   \n      end // g8s_cc_rst\n      else if (IS_8SERIES != 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_srst\n        assign wr_rst_busy = srst_delayed;\n        assign rd_rst_busy = srst_delayed;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = srst_delayed;\n        always @* rst_full_ff_i  <= 1'b0;\n      end // g7s_cc_srst\n  endgenerate \n\n  reg rst_d1 = 1'b0;\n  reg rst_d2 = 1'b0;\n  reg rst_d3 = 1'b0;\n  reg rst_d4 = 1'b0;\n  generate\n    if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1\n    // RST_FULL_GEN replaces the reset falling edge detection used to de-assert\n    // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.\n\n    // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &\n    // PROG_FULL\n\n      always @ (posedge rst_2_sync or posedge clk_2_sync) begin\n        if (rst_2_sync && C_EN_SAFETY_CKT == 0) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          rst_d3         <= 1'b1;\n          rst_d4         <= 1'b0;\n        end else begin\n          if (srst_delayed) begin\n            rst_d1         <= #`TCQ 1'b1;\n            rst_d2         <= #`TCQ 1'b1;\n            rst_d3         <= #`TCQ 1'b1;\n            rst_d4         <= #`TCQ 1'b0;\n          end else begin\n            rst_d1         <= #`TCQ wr_rst_busy;//1'b0;\n            rst_d2         <= #`TCQ rst_d1;\n            rst_d3         <= #`TCQ rst_d2 | sckt_wr_rst_i;\n            rst_d4         <= #`TCQ rst_d3;\n          end\n        end\n      end\n\n      always @* rst_full_ff_i  <= C_HAS_SRST ? 1'b0 : rst_d2 | sckt_wr_rst_i;\n      always @* rst_full_gen_i <= C_HAS_SRST ? rst_d4 : rst_d3;\n\n    end else if (C_EN_SAFETY_CKT == 1 && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full_sckt\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end\n  endgenerate // grstd1\n\nendmodule //fifo_generator_v13_2_5_CONV_VER\n\n\nmodule fifo_generator_v13_2_5_sync_stage\n  #(\n    parameter  C_WIDTH          = 10\n   )\n   (\n    input                     RST,\n    input                     CLK,\n    input       [C_WIDTH-1:0] DIN,\n    output reg  [C_WIDTH-1:0] DOUT = 0\n   );\n   always @ (posedge RST or posedge CLK) begin\n     if (RST)\n       DOUT <= 0;\n     else\n       DOUT <= #`TCQ DIN;\n   end\nendmodule // fifo_generator_v13_2_5_sync_stage\n\n/*******************************************************************************\n * Declaration of Independent-Clocks FIFO Module\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_as\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2 \n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input                                         SAFETY_CKT_WR_RST,\n   input                                         SAFETY_CKT_RD_RST,\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_ASSERT,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_NEGATE,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_ASSERT,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_NEGATE,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         RD_EN_USER,\n   input                                         RST,\n   input                                         RST_FULL_GEN,\n   input                                         RST_FULL_FF,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   input                                         INJECTDBITERR,\n   input                                         INJECTSBITERR,\n   input                                         USER_EMPTY_FB,\n   input                                         fab_read_data_valid_i,\n   input                                         read_data_valid_i,\n   input                                         ram_valid_i,\n   output reg                                    ALMOST_EMPTY = 1'b1,\n   output reg                                    ALMOST_FULL = C_FULL_FLAGS_RST_VAL,\n   output      [C_DOUT_WIDTH-1:0]                DOUT,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    EMPTY_FB = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL,\n   output                                        OVERFLOW,\n   output                                        PROG_EMPTY,\n   output                                        PROG_FULL,\n   output                                        VALID,\n   output      [C_RD_DATA_COUNT_WIDTH-1:0]       RD_DATA_COUNT,\n   output                                        UNDERFLOW,\n   output                                        WR_ACK,\n   output      [C_WR_DATA_COUNT_WIDTH-1:0]       WR_DATA_COUNT,\n   output                                        SBITERR,\n   output                                        DBITERR\n  );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   \n  \n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   \n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;\n   // Array that holds the error injection type (single/double bit error) on \n   // a specific write operation, which is returned on read to corrupt the\n   // output data.\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   //The amount of data stored in the FIFO at any time is given\n   // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK\n   // domain.\n   //num_wr_bits is calculated by considering the total words in the FIFO,\n   // and the state of the read pointer (which may not have yet crossed clock\n   // domains.)\n   //num_rd_bits is calculated by considering the total words in the FIFO,\n   // and the state of the write pointer (which may not have yet crossed clock\n   // domains.)\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   wire                        wr_rst_i = WR_RST;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n   wire                        rd_rst_i = RD_RST;\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n\n\n\n   // Delayed ram_rd_en is needed only for STD Embedded register option\n   generate\n     if (C_PRELOAD_LATENCY == 2) begin : grd_d\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n       end\n     end\n   endgenerate\n   \n    generate\n     if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n           fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n       end\n     end\n   endgenerate\n\n  \n\n   // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;\n     end else begin : rdl // Read depth lesser than or equal to write depth\n       assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n     end\n   endgenerate\n\n   // Generate Empty and Almost Empty\n  // ram_rd_en used to determine EMPTY should depend on the EMPTY.\n   assign ram_rd_en        = RD_EN & !EMPTY;\n   assign empty_int        = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));\n   assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));\n\n   // Register Empty and Almost Empty\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else begin\n         rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};\n\n         if (empty_int)\n           EMPTY           <= #`TCQ 1'b1;\n         else\n           EMPTY           <= #`TCQ 1'b0;\n\n         if (!EMPTY) begin\n           if (almost_empty_int)\n             ALMOST_EMPTY  <= #`TCQ 1'b1;\n           else\n             ALMOST_EMPTY  <= #`TCQ 1'b0;\n         end\n       end // rd_rst_i\n     end // always\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY_FB     <= 1'b1;\n       end else begin\n         if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else if (empty_int)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else\n           EMPTY_FB   <= #`TCQ 1'b0;\n       end // rd_rst_i\n     end // always\n\n   // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;\n     end else begin : wdl // Write depth lesser than or equal to read depth\n       assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n     end\n   endgenerate\n\n  // Generate FULL and ALMOST_FULL\n  // ram_wr_en used to determine FULL should depend on the FULL.\n  assign ram_wr_en       = WR_EN & !FULL;\n  assign full_int        = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));\n  assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));\n\n   // Register FULL and ALMOST_FULL Empty\n   always @ (posedge WR_CLK or posedge RST_FULL_FF)\n     begin\n       if (RST_FULL_FF & C_HAS_RST) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else begin\n         if (full_int) begin\n           FULL           <= #`TCQ 1'b1;\n         end else begin\n           FULL           <= #`TCQ 1'b0;\n         end\n\n         if (RST_FULL_GEN) begin\n           ALMOST_FULL    <= #`TCQ 1'b0;\n         end else if (!FULL) begin\n           if (almost_full_int)\n             ALMOST_FULL  <= #`TCQ 1'b1;\n           else\n             ALMOST_FULL  <= #`TCQ 1'b0;\n         end\n       end // wr_rst_i\n     end // always\n   always @ (posedge WR_CLK or posedge wr_rst_i)\n     begin\n       if (wr_rst_i) begin\n         wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};\n       end else begin\n         wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};\n       end // wr_rst_i\n     end // always\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i) begin\n           stage1_valid     <= 0;\n           stage2_valid     <= 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n   //Pointers passed into opposite clock domain\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_EMPTY.\n   wire [31:0] num_read_words_pe = \n     num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_FULL.\n   wire [31:0] num_write_words_pf =\n     num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n    \n    \n   /***************************************************************************\n    * Internal registers and wires\n    **************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire [C_DOUT_WIDTH-1:0] ideal_dout_out;      \n   wire valid_i;\n   wire valid_out1;\n   wire valid_out2;\n   wire valid_out;  \n   wire underflow_i;\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]               err_type                 = 0;\n   reg [1:0]               err_type_d1              = 0;\n   reg [1:0]               err_type_both              = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout               = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_d1            = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_both            = 0;\n   reg                     ideal_wr_ack             = 0;\n   reg                     ideal_valid              = 0;\n   reg                     ideal_overflow           = C_OVERFLOW_LOW;\n   reg                     ideal_underflow          = C_UNDERFLOW_LOW;\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   reg         valid_d1     = 0;\n   reg         valid_d2     = 0; \n   \n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n   \n\n  /****************************************************************************\n   * Function Declarations\n   ***************************************************************************/\n\n  /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n      if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n    end\n  endtask\n\n  /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n  /***********************************************************************\n  * hexstr_conv\n  *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n  ***********************************************************************/\n  function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_d2           = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n    end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the \n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n    wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;   \n   wire RD_CLK;\n   wire RD_EN;\n   wire RST;\n   wire WR_CLK;\n   wire WR_EN;\n    */\n\n   //***************************************************************************\n   // Dout may change behavior based on latency\n   //***************************************************************************\n   assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?\n                         ideal_dout_d1: ideal_dout;   \n   assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; \n\n   //***************************************************************************\n   // Assign SBITERR and DBITERR based on latency \n   //***************************************************************************\n   assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                    (C_PRELOAD_LATENCY == 2 &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?\n                    err_type_d1[0]: err_type[0]; \n   assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                    (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                    err_type_d1[1]: err_type[1]; \n  \n   //***************************************************************************\n   // Safety-ckt logic with embedded reg/fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n       //  if (C_HAS_VALID == 1) begin\n       //       assign valid_out = valid_d1;\n       //  end\n             \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)\n          begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else \n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n          end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                  @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n           end\n           else begin\n                   if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                   end\n             end \n           end  \n      end \n      endgenerate   \n\n//***************************************************************************\n   // Safety-ckt logic with embedded reg + fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else begin\n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n               fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n          end\n        end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   ideal_dout_both <= #`TCQ dout_reset_val;\n              end\n           end else begin\n             if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n              \n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n             end\n           end \n         end      \n      end \n      endgenerate    \n \n   //***************************************************************************\n   // Overflow may be active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_OVERFLOW==1) begin : blockOF1\n   assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n      end\n   endgenerate\n\n   assign PROG_EMPTY = ideal_prog_empty;\n   assign PROG_FULL  = ideal_prog_full;\n\n   //***************************************************************************\n   // Valid may change behavior based on latency or active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_VALID==1) begin : blockVL1\n   assign valid_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;\n   assign valid_out1 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?\n                       valid_d1: valid_i;  \n   assign valid_out2 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?\n                       valid_d2: valid_i; \n   assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;\n   assign VALID     = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Underflow may change behavior based on latency or active-low   \n   //***************************************************************************\n   generate\n      if (C_HAS_UNDERFLOW==1) begin : blockUF1\n   assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;\n   assign UNDERFLOW   = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n    end\n   endgenerate\n\n   //***************************************************************************\n   // Write acknowledge may be active low\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_ACK==1) begin : blockWK1\n   assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext\n\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_wr_pntr = 0;\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_rd_pntr = 0;\n      wire [C_PNTR_WIDTH-1:0]  diff_wr_rd_tmp;\n      wire [C_PNTR_WIDTH:0]    diff_wr_rd;\n      reg  [C_PNTR_WIDTH:0]    wr_data_count_i  = 0;\n        always @* begin\n          if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = 0;\n            adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n          end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin\n            adjusted_rd_pntr = rd_pntr_wr;\n            adjusted_wr_pntr = 0;\n            adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n          end else begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = rd_pntr_wr;\n          end\n        end // always @*\n\n        assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;\n        assign diff_wr_rd     = {1'b0,diff_wr_rd_tmp};\n\n        always @ (posedge wr_rst_i or posedge WR_CLK)\n        begin\n            if (wr_rst_i)\n              wr_data_count_i <= 0;\n            else\n              wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;\n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n\n        always @* begin\n          if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];\n          else\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n        end // always @*\n      end // wdc_fwft_ext\n   endgenerate\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   reg  [C_RD_PNTR_WIDTH:0]    rdc_fwft_ext_as  = 0;\n\n   generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n\n\n   always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= 0;\n            end else begin\n              if (!stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 0;\n              else if (!stage1_valid && stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 1;\n              else\n                rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;\n            end \n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n      end // rdc_fwft_ext\n end\n   endgenerate\n\n\n  generate if (C_USE_EMBEDDED_REG == 3) begin\n     if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n        wire [C_RD_PNTR_WIDTH:0]  diff_rd_wr_1;\n   //     assign diff_rd_wr_1 = diff_rd_wr +2'h2;\n\n       always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= #`TCQ 0;\n            end else begin\n          //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))\n          //    rdc_fwft_ext_as <= 1'b0;\n          //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) \n          //    rdc_fwft_ext_as <= 1'b1;\n          //else\n            rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;\n        end\n\n\n\nend\nend\nend\nendgenerate\n          \n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1) begin : grdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?\n          rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :\n          rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?\n          wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :\n          wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n\n  /**************************************************************************\n  * Assorted registers for delayed versions of signals\n  **************************************************************************/\n  //Capture delayed version of valid\n  generate\n      if (C_HAS_VALID==1) begin : blockVL2\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n      valid_d1 <= 1'b0;\n      valid_d2 <= 1'b0;\n    end else begin\n      valid_d1 <= #`TCQ valid_i;\n      valid_d2 <= #`TCQ valid_d1;\n    end \n//    if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin\n  //      valid_d2 <= #`TCQ valid_d1;\n      //  end \n  end \n      end\n endgenerate  \n   \n  //Capture delayed version of dout\n  /**************************************************************************\n    *embedded/fabric reg with no safety ckt\n    **************************************************************************/\n  generate \n       if (C_USE_EMBEDDED_REG < 3) begin\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n       if (C_USE_DOUT_RST == 1'b1) begin\n         @(posedge RD_CLK)\n           ideal_dout_d1   <= #`TCQ dout_reset_val;\n           ideal_dout   <= #`TCQ dout_reset_val;\n       end\n      // Reset err_type only if ECC is not selected\n      if (C_USE_ECC == 0)\n        err_type_d1     <= #`TCQ 0;\n     end else if (ram_rd_en_d1) begin\n      ideal_dout_d1   <= #`TCQ ideal_dout;\n      err_type_d1     <= #`TCQ err_type;\n           end    \n  end  \n   \nend  \nendgenerate \n/**************************************************************************\n    *embedded + fabric reg with no safety ckt\n    **************************************************************************/\n\ngenerate \n  if (C_USE_EMBEDDED_REG == 3) begin\n    always @(posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i == 1'b1) begin\n        if (C_USE_DOUT_RST == 1'b1) begin\n           @(posedge RD_CLK)\n             ideal_dout    <= #`TCQ dout_reset_val;\n             ideal_dout_d1   <= #`TCQ dout_reset_val;\n             ideal_dout_both   <= #`TCQ dout_reset_val;\n        end\n        // Reset err_type only if ECC is not selected\n        if (C_USE_ECC == 0) begin\n          err_type_d1     <= #`TCQ 0;\n          err_type_both   <= #`TCQ 0;\n        end\n      end else begin\n         if (ram_rd_en_d1) begin\n           ideal_dout_both   <= #`TCQ ideal_dout;\n           err_type_both     <= #`TCQ err_type;\n         end    \n         if (fab_rd_en_d1) begin\n           ideal_dout_d1   <= #`TCQ ideal_dout_both;\n           err_type_d1     <= #`TCQ err_type_both;\n         end\n      end\n    end  \n  end  \nendgenerate \n\n  \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate\n     if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n       always @(posedge WR_CLK) begin\n         ideal_overflow    <= #`TCQ WR_EN & FULL;\n       end\n     end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n       always @(posedge WR_CLK) begin\n         //ideal_overflow    <= #`TCQ WR_EN & (FULL | wr_rst_i);\n         ideal_overflow    <= #`TCQ WR_EN & (FULL );\n       end\n     end\n   endgenerate\n\n   generate\n     if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ EMPTY & RD_EN;\n       end\n     end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ (EMPTY) & RD_EN;\n         //ideal_underflow    <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;\n       end\n     end\n   endgenerate\n\n   /**************************************************************************\n   * Write/Read Pointer Synchronization\n   **************************************************************************/\n   localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;\n   wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   genvar gss;\n\n   generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (C_WR_PNTR_WIDTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_i), \n         .CLK      (RD_CLK), \n         .DIN      (wr_pntr_sync_stgs[gss-1]), \n         .DOUT     (wr_pntr_sync_stgs[gss])\n        );\n \n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (C_RD_PNTR_WIDTH)\n        )\n     wr_stg_inst\n        (\n         .RST      (wr_rst_i), \n         .CLK      (WR_CLK), \n         .DIN      (rd_pntr_sync_stgs[gss-1]), \n         .DOUT     (rd_pntr_sync_stgs[gss])\n        );\n   end endgenerate // Sync_stage_inst\n\n   assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;\n   assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;\n   always@* begin\n     wr_pntr_rd           <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n     rd_pntr_wr           <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n   end\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp\n     if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)\n       wr_pntr           <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)\n       wr_pntr           <= #`TCQ 0;\n   end\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (wr_rst_i == 1'b1) begin\n       num_wr_bits       <= 0;\n       next_num_wr_bits   = 0;\n       wr_ptr            <= C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= C_RD_DEPTH - 1;\n       ideal_wr_ack      <= 0;\n       ideal_wr_count    <= 0;\n       tmp_wr_listsize    = 0;\n       rd_ptr_wrclk_next <= 0;\n       wr_pntr_rd1       <= 0;\n\n     end else begin //wr_rst_i==0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       //If this is a write, handle the write by adding the value\n       // to the linked list, and updating all outputs appropriately\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD \n             >= C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full, but reporting full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //With DEPTH-1 words in the FIFO, it is almost_full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n\n           //If the FIFO is completely empty, but it is\n           // reporting FULL for some reason (like reset)\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=\n                C_FIFO_WR_DEPTH-2) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //FIFO is really not close to full, so change flag status.\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n           end //(tmp_wr_listsize == 0)\n\n         end else begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=\n              C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack       <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count     <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;\n\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //This write is CAUSING the FIFO to go full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is 2 from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == \n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits =  next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Still 2 from full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is not close to being full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <\n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //wr_rst_i==0\n   end // gen_fifo_w\n\n\n  /***************************************************************************\n   * Programmable FULL flags\n   ***************************************************************************/\n\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;\n\n   generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;\n   end else begin // STD\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;\n   end endgenerate\n\n   always @(posedge WR_CLK or posedge wr_rst_i) begin\n\n     if (wr_rst_i == 1'b1) begin\n       diff_pntr         <= 0;\n     end else begin\n       if (ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);\n       else if (!ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);\n    end\n  end\n\n\n   always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf\n\n     if (RST_FULL_FF & C_HAS_RST) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else begin\n\n       if (RST_FULL_GEN)\n         ideal_prog_full   <= #`TCQ 0;\n       //Single Programmable Full Constant Threshold\n       else if (C_PROG_FULL_TYPE == 1) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else\n             ideal_prog_full <= #`TCQ 0;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Constant Thresholds\n       end else if (C_PROG_FULL_TYPE == 2) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else if (diff_pntr < pf_thr_negate_val)\n             ideal_prog_full <= #`TCQ 0;\n           else\n             ideal_prog_full <= #`TCQ ideal_prog_full;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Single Programmable Full Threshold Input\n       end else if (C_PROG_FULL_TYPE == 3) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH)\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Threshold Inputs\n       end else if (C_PROG_FULL_TYPE == 4) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH_ASSERT)\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < PROG_FULL_THRESH_NEGATE)\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       end // C_PROG_FULL_TYPE\n\n     end //wr_rst_i==0\n   end //\n\n   \n   /**************************************************************************\n   * Read Domain Logic\n   **************************************************************************/\n\n\n   /*********************************************************\n    * Programmable EMPTY flags\n    *********************************************************/\n   //Determine the Assert and Negate thresholds for Programmable Empty\n\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd      = 0;\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe\n\n     if (rd_rst_i & C_HAS_RST) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else begin\n       if (ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;\n       else if (!ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr);\n       else\n         diff_pntr_rd       <=  #`TCQ diff_pntr_rd;\n  \n       if (C_PROG_EMPTY_TYPE == 1) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 2) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 3) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 4) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end  //C_PROG_EMPTY_TYPE\n     end\n   end // gen_pe\n\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;\n   end endgenerate // single_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;\n   end endgenerate // multiple_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;\n   end endgenerate // single_multiple_pe_thr_const\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp\n     if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n       rd_pntr            <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)\n       rd_pntr            <= #`TCQ 0;\n   end\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rd_rst_i & C_HAS_RST) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n     end else begin //rd_rst_i==0\n\n       rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 1\n       /*****************************************************************/\n       if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Reminder that FIFO is still empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end // if (tmp_rd_listsize <= 0)\n\n             //If the FIFO is one from empty, but it is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 1)\n\n             //If the FIFO is two from empty, and is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Fifo has two words, so is neither empty or almost empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 2)\n\n             //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid <= #`TCQ 1'b0;\n                 //Note that the FIFO is No Longer Empty or Almost Empty\n\n                 ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n               end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n             end // else: if(ideal_empty == 1'b1)\n\n           else //if (ideal_empty == 1'b0)\n             begin\n\n               //If the FIFO is completely full, and we are successfully reading from it\n               if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)\n\n               //If the FIFO is not close to being empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n               //If the FIFO is two from empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Fifo is not yet empty. It is going almost_empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n\n               //If the FIFO is one from empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Note that FIFO is GOING empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 1)\n\n\n               //If the FIFO is completely empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n                 begin\n                   //Do not change the contents of the FIFO\n\n                   //Do not acknowledge the read from empty FIFO\n                   ideal_valid        <= #`TCQ 1'b0;\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize <= 0)\n\n             end // if (ideal_empty == 1'b0)\n\n           end //(RD_EN == 1'b1)\n\n         else //if (RD_EN == 1'b0)\n           begin\n             //If user did not attempt a read, do not give an ack or err\n             ideal_valid          <= #`TCQ 1'b0;\n\n             ideal_rd_count       <= #`TCQ num_read_words_sized_i;\n\n           end // else: !if(RD_EN == 1'b1)\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 0\n       /*****************************************************************/\n       end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty, but it is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty, and is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Fifo has two words, so is neither empty or almost empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                         (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that the FIFO is No Longer Empty or Almost Empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n           end else begin\n\n             //If the FIFO is completely full, and we are successfully reading from it\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is not close to being empty\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                          (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Fifo is not yet empty. It is going almost_empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Note that FIFO is GOING empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is completely empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if (tmp_rd_listsize <= 0)\n\n           end // if (ideal_empty == 1'b0)\n\n         end else begin//(RD_EN == 1'b0)\n\n         \n           //If user did not attempt a read, do not give an ack or err\n           ideal_valid           <= #`TCQ 1'b0;\n           ideal_rd_count        <= #`TCQ num_read_words_sized_i;\n\n         end // else: !if(RD_EN == 1'b1)\n       end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //rd_rst_i==0\n   end //always gen_fifo_r_as\n\nendmodule // fifo_generator_v13_2_5_bhv_ver_as\n\n\n/*******************************************************************************\n * Declaration of Low Latency Asynchronous FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_beh_ver_ll_afifo\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_FIFO_TYPE                    = 0\n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   output reg  [C_DOUT_WIDTH-1:0]                DOUT = 0,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL\n  );\n\n  //-----------------------------------------------------------------------------\n  // Low Latency Asynchronous FIFO\n  //-----------------------------------------------------------------------------\n\n  // Memory which will be used to simulate a FIFO\n  reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n  integer i;\n  initial begin\n    for (i = 0; i < C_WR_DEPTH; i = i + 1)\n      memory[i] = 0;\n  end\n\n  reg  [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;\n  wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;\n  reg  [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;\n  reg                        ll_afifo_full    = 1'b0;\n  reg                        ll_afifo_empty   = 1'b1;\n  wire                       write_allow;\n  wire                       read_allow;\n\n  assign write_allow = WR_EN & ~ll_afifo_full;\n  assign read_allow  = RD_EN & ~ll_afifo_empty;\n\n  //-----------------------------------------------------------------------------\n  // Write Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      wr_pntr_ll_afifo   <= 0;\n    else if (write_allow)\n      wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Read Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      rd_pntr_ll_afifo_q   <= 0;\n    else\n      rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;\n  end\n  assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;\n  \n  //-----------------------------------------------------------------------------\n  // Fill the Memory\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK) begin\n    if (write_allow)\n      memory[wr_pntr_ll_afifo] <= #`TCQ DIN;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate DOUT\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK) begin\n      DOUT <= #`TCQ memory[rd_pntr_ll_afifo];\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate EMPTY\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      ll_afifo_empty   <= 1'b1;\n    else\n      ll_afifo_empty   <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | \n                           (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate FULL\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      ll_afifo_full   <= 1'b1;\n    else\n      ll_afifo_full   <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | \n                           (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));\n  end\n\n  always @* begin\n    FULL  <= ll_afifo_full;\n    EMPTY <= ll_afifo_empty;\n  end\n\nendmodule // fifo_generator_v13_2_5_beh_ver_ll_afifo\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_ss\n   \n  /**************************************************************************\n   * Declare user parameters and their defaults\n   *************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0 \n   )\n   \n  /**************************************************************************\n   * Declare Input and Output Ports\n   *************************************************************************/\n   (\n    //Inputs\n    input                                 SAFETY_CKT_WR_RST,\n    input                                 CLK,\n    input       [C_DIN_WIDTH-1:0]         DIN,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_ASSERT,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_NEGATE,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_ASSERT,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_NEGATE,\n    input                                 RD_EN,\n    input                                 RD_EN_USER,\n    input                                 USER_EMPTY_FB,\n    input                                 RST,\n    input                                 RST_FULL_GEN,\n    input                                 RST_FULL_FF,\n    input                                 SRST,\n    input                                 WR_EN,\n    input                                 INJECTDBITERR,\n    input                                 INJECTSBITERR,\n    input                                 WR_RST_BUSY,\n    input                                 RD_RST_BUSY,\n                                    \n    //Outputs                       \n    output                                ALMOST_EMPTY,\n    output                                ALMOST_FULL,\n    output reg   [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,\n    output       [C_DOUT_WIDTH-1:0]       DOUT,\n    output                                EMPTY,\n    output reg                            EMPTY_FB = 1'b1,\n    output                                FULL,\n    output                                OVERFLOW,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]    RD_DATA_COUNT,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]    WR_DATA_COUNT,\n    output                                PROG_EMPTY,\n    output                                PROG_FULL,\n    output                                VALID,\n    output                                UNDERFLOW,\n    output                                WR_ACK,\n    output                                SBITERR,\n    output                                DBITERR\n   );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;\n   wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n   localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; \n\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n   localparam  EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //localparam  EXTRA_WORDS_PE_PARAM  = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not \n   //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.\n   // Therefore, during SRST, all the FULL flags reset to 0.\n   localparam                      C_HAS_FAST_FIFO = 0;\n   localparam                      C_FIFO_WR_DEPTH = C_WR_DEPTH;\n   localparam                      C_FIFO_RD_DEPTH = C_RD_DEPTH;\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;\n   localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;\n   localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;\n   localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n  localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; \n  localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; \n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   \n   /**************************************************************************\n    * Internal Registers and wires\n    *************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire                           underflow_i;\n   wire                           valid_i;\n   wire                           valid_out;\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_reg = 1'b0;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n   wire                         srst_rrst_busy;\n\n\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]                      err_type           = 0;\n   reg [1:0]                      err_type_d1        = 0;\n   reg [1:0]                      err_type_both      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout         = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_d1      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_both      = 0;\n   wire [C_DOUT_WIDTH-1:0]        ideal_dout_out;\n   wire                           fwft_enabled;\n   reg                            ideal_wr_ack       = 0;\n   reg                            ideal_valid        = 0;\n   reg                            ideal_overflow     = C_OVERFLOW_LOW;\n   reg                            ideal_underflow    = C_UNDERFLOW_LOW;\n\n   reg                            full_i             = C_FULL_FLAGS_RST_VAL;\n   reg                            full_i_temp        = 0;\n   reg                            empty_i            = 1;\n   reg                            almost_full_i      = 0;\n   reg                            almost_empty_i     = 1;\n   reg                            prog_full_i        = 0;\n   reg                            prog_empty_i       = 1;\n   reg [C_WR_PNTR_WIDTH-1:0]      wr_pntr            = 0;\n   reg [C_RD_PNTR_WIDTH-1:0]      rd_pntr            = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg [C_RD_PNTR_WIDTH-1:0]      diff_count         = 0;\n\n   reg                            write_allow_q      = 0;\n   reg                            read_allow_q       = 0;\n   reg                            valid_d1           = 0;\n   reg                            valid_both           = 0;\n   reg                            valid_d2           = 0;\n   wire                           rst_i;\n   wire                           srst_i;\n\n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]         dout_reset_val = 0;\n\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n\n\n\n   /****************************************************************************\n    * Function Declarations\n    ***************************************************************************/\n\n   /****************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***************************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin\n        case (def_data[7:0])\n          8'b00000000 : begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default : begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1) begin\n          if ((index*4)+j < C_DOUT_WIDTH) begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   //reg         valid_d1     = 0;\n   \n   \n   //user specified value for reseting the size of the fifo\n   //reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n\n\n /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n     if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n\n     end\n  endtask\n\n\n   \n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_dout_both    = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_both         = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n\n   end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the\n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n   wire CLK;\n   wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;\n   wire RD_EN;\n   wire RST;\n   wire WR_EN;\n    */\n\n  // Assign ALMOST_EPMTY\n  generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae\n    assign ALMOST_EMPTY = almost_empty_i;\n  end else begin : gnae\n    assign ALMOST_EMPTY = 0;\n  end endgenerate // gae\n\n  // Assign ALMOST_FULL\n  generate if (C_HAS_ALMOST_FULL==1) begin : gaf\n    assign ALMOST_FULL  = almost_full_i;\n  end else begin : gnaf\n    assign ALMOST_FULL  = 0;\n  end endgenerate // gaf\n\n   // Dout may change behavior based on latency\n  localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?\n                         ideal_dout_d1: ideal_dout; \n  assign DOUT = ideal_dout_out;\n\n  // Assign SBITERR and DBITERR based on latency \n  assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[0]: err_type[0]; \n  assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[1]: err_type[1]; \n\n  assign EMPTY         = empty_i;\n  assign FULL          = full_i;\n  //saftey_ckt with one register\n\n  generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)\n          begin\n          if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n              valid_d1 <= #`TCQ 1'b0;\n          end\n          else begin\n               ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n               valid_d1 <= #`TCQ valid_i;\n          end\n          end\n          \n           always@(posedge rst_delayed_sft2 or posedge CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n              end\n           else if (srst_rrst_busy == 1'b1) begin\n                   if (C_USE_DOUT_RST == 1'b1) begin\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   end\n           end else if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                end\n           end   \n      end //if \n      endgenerate   \n\n//safety ckt with both registers\n\ngenerate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK) begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            valid_d1 <= #`TCQ 1'b0;\n          end else begin\n            ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n            fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n            valid_both <= #`TCQ valid_i;\n            valid_d1 <= #`TCQ valid_both;\n          end\n        end\n\n        always@(posedge rst_delayed_sft2 or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                  ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else if (srst_rrst_busy == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else begin \n            if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n            end\n          end\n        end\n      end //if \n      endgenerate    \n \n \n  //Overflow may be active-low\n  generate if (C_HAS_OVERFLOW==1) begin : gof\n    assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n  end else begin : gnof\n    assign OVERFLOW = 0;\n  end endgenerate // gof\n\n  assign PROG_EMPTY    = prog_empty_i;\n  assign PROG_FULL     = prog_full_i;\n\n   //Valid may change behavior based on latency or active-low\n  generate if (C_HAS_VALID==1) begin : gvalid\n    assign valid_i       = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;\n    assign valid_out     = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?\n                            valid_d1 : valid_i; \n    assign VALID         = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n  end else begin : gnvalid\n    assign VALID         = 0;\n  end endgenerate // gvalid\n\n  //Trim data count differently depending on set widths\n  generate if (C_HAS_DATA_COUNT == 1) begin : gdc\n    always @* begin\n      diff_count <= wr_pntr - rd_pntr;\n      if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin\n        DATA_COUNT[C_RD_PNTR_WIDTH-1:0]  <= diff_count;\n        DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; \n      end else begin\n        DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];\n      end\n    end\n//  end else begin : gndc\n//    always @* DATA_COUNT <= 0;\n  end endgenerate // gdc\n\n  //Underflow may change behavior based on latency or active-low\n  generate if (C_HAS_UNDERFLOW==1) begin : guf\n    assign underflow_i   = ideal_underflow;\n    assign UNDERFLOW     = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n  end else begin : gnuf\n    assign UNDERFLOW     = 0;\n  end endgenerate // guf\n \n\n  //Write acknowledge may be active low \n  generate if (C_HAS_WR_ACK==1) begin : gwr_ack\n    assign WR_ACK        = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n  end else begin : gnwr_ack\n    assign WR_ACK        = 0;\n  end endgenerate // gwr_ack\n\n\n  /*****************************************************************************\n   * Internal reset logic \n   ****************************************************************************/\n  assign srst_i        = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;\n  assign rst_i            = C_HAS_RST ? RST : 0;\n  assign srst_wrst_busy   = srst_i;\n  assign srst_rrst_busy   = srst_i;\n\n   /**************************************************************************\n    * Assorted registers for delayed versions of signals\n    **************************************************************************/\n   //Capture delayed version of valid\n   generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20\n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1 <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n           end else begin\n              valid_d1 <= #`TCQ valid_i;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n     end \n   endgenerate // blockVL20\n\n  generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin \n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1   <= 1'b0;\n           valid_both <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n              valid_both <= #`TCQ 1'b0;\n              \n           end else begin\n              valid_both <= #`TCQ valid_i;\n               valid_d1 <= #`TCQ valid_both;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n  end\n endgenerate // blockVL20\n\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge CLK or posedge rst_i) begin\n         if (rst_i) begin\n           stage1_valid     <= #`TCQ 0;\n           stage2_valid     <= #`TCQ 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n\n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc\n       assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc\n       assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n   \n   //reg ram_rd_en_d1 = 1'b0;\n   //Capture delayed version of dout\n   generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         ram_rd_en_d1 <= #`TCQ 1'b0;\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n        end\n      end else begin\n         ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n         if (srst_rrst_busy) begin\n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            // Reset err_type only if ECC is not selected\n            if (C_USE_ECC == 0) begin\n               err_type_d1   <= #`TCQ 0;\n               err_type_both <= #`TCQ 0;\n            end\n            // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n            if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n            end \n         if (C_USE_DOUT_RST == 1) begin\n           // @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         end else begin\n            if (ram_rd_en_d1 ) begin\n            ideal_dout_d1 <= #`TCQ ideal_dout;\n            err_type_d1   <= #`TCQ err_type;\n            end\n         end\n      end    \n   end   // always\nend\nendgenerate \n\n//no safety ckt with both registers\n generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n          ram_rd_en_d1 <= #`TCQ 1'b0;\n          fab_rd_en_d1 <= #`TCQ 1'b0;\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val; \n            \n      end\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val;\n       end\n      end else begin\n         if (srst_rrst_busy) begin \n           ram_rd_en_d1 <= #`TCQ 1'b0;\n           fab_rd_en_d1 <= #`TCQ 1'b0;\n           // Reset err_type only if ECC is not selected\n           if (C_USE_ECC == 0) begin\n              err_type_d1   <= #`TCQ 0;\n              err_type_both <= #`TCQ 0;\n           end\n           // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n           if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n              ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end \n           if (C_USE_DOUT_RST == 1) begin\n             ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end\n         end else begin\n           ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n           fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);\n           if (ram_rd_en_d1 ) begin\n             ideal_dout_both <= #`TCQ ideal_dout;\n             err_type_both   <= #`TCQ err_type;\n           end\n           if (fab_rd_en_d1 ) begin\n             ideal_dout_d1 <= #`TCQ ideal_dout_both;\n             err_type_d1   <= #`TCQ err_type_both;\n           end\n         end\n      end    \n   end   // always\nend\nendgenerate \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n     always @(posedge CLK) begin\n       ideal_overflow    <= #`TCQ WR_EN & full_i;\n     end\n   end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n     always @(posedge CLK) begin\n       //ideal_overflow    <= #`TCQ WR_EN & (rst_i | full_i);\n       ideal_overflow    <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);\n     end\n   end endgenerate // blockOF20\n \n   generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n     always @(posedge CLK) begin\n       ideal_underflow   <= #`TCQ empty_i & RD_EN;\n     end\n   end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n     always @(posedge CLK) begin\n       //ideal_underflow   <= #`TCQ (rst_i | empty_i) & RD_EN;\n       ideal_underflow   <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;\n     end\n   end endgenerate // blockUF20\n\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n\n  /*************************************************************************\n   * Write and Read Logic  \n   ************************************************************************/\n   wire              write_allow;\n   wire              read_allow;\n   wire              read_allow_dc;\n   wire              write_only;\n   wire              read_only;\n   //wire              write_only_q;\n   reg              write_only_q;\n   //wire              read_only_q;\n   reg              read_only_q;\n   reg              full_reg;\n   reg              rst_full_ff_reg1;\n   reg              rst_full_ff_reg2;\n   wire              ram_full_comb;\n   wire              carry;\n   \n   assign write_allow  = WR_EN & ~full_i;\n   assign read_allow   = RD_EN & ~empty_i;\n   assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;\n   //assign write_only   = write_allow & ~read_allow;\n   //assign write_only_q = write_allow_q;\n   //assign read_only    = read_allow    & ~write_allow;\n   //assign read_only_q  = read_allow_q ;\n   wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;\n   wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;\n   wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;\n\n   assign diff_pntr_pe_max = DIFF_MAX_RD;\n   assign diff_pntr_max = DIFF_MAX_WR;\n\n\n\n   generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym\n    assign write_only   = write_allow & ~read_allow;\n    assign read_only    = read_allow    & ~write_allow;\n    end endgenerate\n    generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd\n     assign read_only   = read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;\n     assign write_only    = write_allow    & ~(read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n    generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr\n     assign read_only   = read_allow & ~(write_allow  & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n     assign write_only    = write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;\n    end endgenerate\n\n\n   //-----------------------------------------------------------------------------\n   // Write and Read pointer generation\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       wr_pntr         <= 0;\n       rd_pntr         <= 0;\n     end else begin\n       if (srst_i) begin\n         wr_pntr       <= #`TCQ 0;\n         rd_pntr       <= #`TCQ 0;\n       end else begin\n         if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;\n         if (read_allow)  rd_pntr <= #`TCQ rd_pntr + 1;\n       end\n     end\n   end\n\n   generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout\n   always @(posedge CLK) begin\n     if (write_allow) begin\n       if (ENABLE_ERR_INJECTION == 1)\n         memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};\n       else\n         memory[wr_pntr] <= #`TCQ DIN;\n     end\n   end\n\n   reg  [C_DATA_WIDTH-1:0] dout_tmp_q;\n   reg [C_DATA_WIDTH-1:0] dout_tmp = 0;\n   reg  [C_DATA_WIDTH-1:0] dout_tmp1 = 0;\n   always @(posedge CLK) begin\n     dout_tmp_q <= #`TCQ ideal_dout;\n   end\n\n\n\n     always @* begin\n       if (read_allow)\n         ideal_dout <= memory[rd_pntr];\n       else\n         ideal_dout <= dout_tmp_q;\n     end\n   end endgenerate // gll_dm_dout\n\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   assign ram_rd_en        = RD_EN & !EMPTY;\n\n   //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   generate if (C_FIFO_TYPE != 2) begin : gnll_din\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i == 1'b1) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n\n     end else begin //rst_i==0\n     if (srst_wrst_busy) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n     end else begin//srst_i=0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n         end else begin\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error  \n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           //end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //srst_i==0\n     end //wr_rst_i==0\n   end // gen_fifo_w\n    end endgenerate\n\n   generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout\n     always @(posedge CLK) begin\n       if (rst_i || srst_rrst_busy) begin\n         if (C_USE_DOUT_RST == 1) begin\n           ideal_dout <= #`TCQ dout_reset_val;\n           ideal_dout_both <= #`TCQ dout_reset_val;\n         end\n       end\n     end\n    end endgenerate\n\n\n\n\n   generate if (C_FIFO_TYPE != 2) begin : gnll_dout\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_r\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n\n     end else begin //rd_rst_i==0\n     if (srst_rrst_busy) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets synchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= #`TCQ 0;\n         err_type_both    <= #`TCQ 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n      end //srst_i\n      else begin\n\n       //rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n         if (RD_EN == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end \n           else \n             begin\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n         end\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //s_rst_i==0\n     end //rd_rst_i==0\n   end //always\n  end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate diff_pntr for PROG_FULL generation\n   // Generate diff_pntr_pe for PROG_EMPTY generation\n   //-----------------------------------------------------------------------------\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         write_only_q   <= 1'b0;\n         read_only_q    <= 1'b0;\n         diff_pntr_reg1       <= 0;\n         diff_pntr_pe_reg1    <= 0;\n         diff_pntr_reg2       <= 0;\n         diff_pntr_pe_reg2    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_rrst_busy) begin\n           read_only_q  <= #`TCQ 1'b0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n           diff_pntr_pe_reg2  <= #`TCQ 0;\n          end\n          if (srst_wrst_busy) begin\n           write_only_q <= #`TCQ 1'b0;\n           diff_pntr_reg1     <= #`TCQ 0;\n           diff_pntr_reg2     <= #`TCQ 0;\n          end\n         end else begin\n           write_only_q <= #`TCQ write_only;\n           read_only_q  <= #`TCQ read_only;\n           diff_pntr_reg2  <= #`TCQ diff_pntr_reg1;\n           diff_pntr_pe_reg2  <= #`TCQ diff_pntr_pe_reg1;\n\n           // Add 1 to the difference pointer value when only write happens.\n           if (write_only)  \n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;\n           else\n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;\n\n           // Add 1 to the difference pointer value when write or both write & read or no write & read happen.\n           if (read_only)  \n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;\n           else\n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;\n         end\n       end\n     end\n   assign diff_pntr_pe = diff_pntr_pe_reg1;\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow\n\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym\n    assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};\n    assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         diff_pntr_pe_asym    <= 0;\n         diff_pntr_reg1       <= 0;\n         full_reg             <= 0;\n         rst_full_ff_reg1     <= 1;\n         rst_full_ff_reg2     <= 1;\n         diff_pntr_pe_reg1    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_wrst_busy)\n           diff_pntr_reg1     <= #`TCQ 0;\n          if (srst_rrst_busy)\n           full_reg             <=  #`TCQ 0;\n           rst_full_ff_reg1     <=  #`TCQ 1;\n           rst_full_ff_reg2     <=  #`TCQ 1;\n           diff_pntr_pe_asym    <=  #`TCQ 0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n         end else begin\n             diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;\n             full_reg          <= #`TCQ full_i;\n             rst_full_ff_reg1  <=  #`TCQ RST_FULL_FF;\n             rst_full_ff_reg2  <=  #`TCQ rst_full_ff_reg1;\n           if (~full_i) begin  \n             diff_pntr_reg1 <=  #`TCQ wr_pntr - adj_rd_pntr_wr;\n          end\n         end\n       end\n     end\n   assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));\n   assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow_asym\n\n\n   //-----------------------------------------------------------------------------\n   // Generate FULL flag\n   //-----------------------------------------------------------------------------\n   wire                 comp0;\n   wire                 comp1;\n   wire                 going_full;\n   wire                 leaving_full;\n \n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin :  gpad \t\n    assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;\n    assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin :  gtrim \n    assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n  end endgenerate\n\n   assign comp1         = (adj_rd_pntr_wr == (wr_pntr + 1'b1));\n   assign comp0         = (adj_rd_pntr_wr == wr_pntr);\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp\n     assign going_full    = (comp1 & write_allow & ~read_allow);\n     assign leaving_full  = (comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym\n      assign going_full = (comp1 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_full = (comp0 & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp \n      assign going_full = (comp1 & write_allow & ~read_allow);\n      assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n\n   assign ram_full_comb = going_full | (~leaving_full & full_i);\n\n   generate if (C_HAS_RST == 1) begin : grst_full\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF & C_HAS_RST)\n         full_i   <= C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_SRST == 1) begin : gsrst_full\n     always @(posedge CLK) begin\n       if (srst_wrst_busy)\n         full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_full\n     always @(posedge CLK) begin\n         full_i   <= #`TCQ ram_full_comb;\n     end\n   end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate EMPTY flag\n   //-----------------------------------------------------------------------------\n   wire                 ecomp0;\n   wire                 ecomp1;\n   wire                 going_empty;\n   wire                 leaving_empty;\n   wire                 ram_empty_comb;\n\n  \n generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin :  pad \t\n    assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n    assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin :  trim \n    assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n  end endgenerate\n\n   assign ecomp1         = (adj_wr_pntr_rd == (rd_pntr + 1'b1));\n   assign ecomp0         = (adj_wr_pntr_rd == rd_pntr);\n\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp\n     assign going_empty    = (ecomp1 & ~write_allow & read_allow);\n     assign leaving_empty  = (ecomp0 & write_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp\n      assign going_empty = (ecomp1 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_empty = (ecomp0 & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp \n      assign going_empty = (ecomp1 & ~write_allow & read_allow);\n      assign leaving_empty =(ecomp0 & write_allow);\n    end endgenerate\n\n\n\n    assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);\n\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       empty_i  <= 1'b1;\n     else if (srst_rrst_busy)\n       empty_i  <= #`TCQ 1'b1;\n     else\n       empty_i  <= #`TCQ ram_empty_comb;\n    end\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       EMPTY_FB     <= 1'b1;\n     end else begin\n       if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))\n         EMPTY_FB   <= #`TCQ 1'b1;\n       else\n         EMPTY_FB   <= #`TCQ ram_empty_comb;\n     end\n   end // always\n\n   //-----------------------------------------------------------------------------\n   // Generate Read and write data counts for asymmetic common clock\n   //-----------------------------------------------------------------------------\n\n    reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; \n    wire [C_GRTR_PNTR_WIDTH :0] ratio; \n    wire decr_by_one;\n    wire incr_by_ratio;\n    wire incr_by_one;\n    wire decr_by_ratio;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n\n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr \n      assign ratio         = C_DEPTH_RATIO_RD;\n      assign decr_by_one   = (IS_FWFT == 1)? read_allow_dc : read_allow;\n      assign incr_by_ratio = write_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (decr_by_one) begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc - 1;\n           else\n\t    count_dc <= #`TCQ count_dc - 1  + ratio ;\n\t end\n\t else begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc + ratio ;\n\tend\n       end\n       end\n\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n\n    end endgenerate\n\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd \n      assign ratio         = C_DEPTH_RATIO_WR;\n      assign incr_by_one   = write_allow;\n      assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (incr_by_one) begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc + 1;\n           else\n\t    count_dc <= #`TCQ count_dc + 1  - ratio ;\n\t end\n\t else begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc - ratio ;\n\tend\n       end\n       end\n\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n\n    end endgenerate\n\n\n\n\n\n\n   //-----------------------------------------------------------------------------\n   // Generate WR_ACK flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_wr_ack  <= 1'b0;\n     else if (srst_wrst_busy)\n       ideal_wr_ack  <= #`TCQ 1'b0;\n     else if (WR_EN & ~full_i)\n       ideal_wr_ack  <= #`TCQ 1'b1;\n     else\n       ideal_wr_ack  <= #`TCQ 1'b0;\n    end\n\n   //-----------------------------------------------------------------------------\n   // Generate VALID flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_valid  <= 1'b0;\n     else if (srst_rrst_busy)\n       ideal_valid  <= #`TCQ 1'b0;\n     else if (RD_EN & ~empty_i)\n       ideal_valid  <= #`TCQ 1'b1;\n     else\n       ideal_valid  <= #`TCQ 1'b0;\n    end\n\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_FULL flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss\n\n     wire                 fcomp2;\n     wire                 going_afull;\n     wire                 leaving_afull;\n     wire                 ram_afull_comb;\n\n\n   assign fcomp2         = (adj_rd_pntr_wr == (wr_pntr + 2'h2));\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp\n     assign going_afull    = (fcomp2 & write_allow & ~read_allow);\n     assign leaving_afull  = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym\n      assign going_afull = (fcomp2 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_afull = (comp1 & (~write_allow) & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp \n      assign going_afull = (fcomp2 & write_allow & ~read_allow);\n      assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n     assign ram_afull_comb  = going_afull | (~leaving_afull & almost_full_i);\n\n\n    generate if (C_HAS_RST == 1) begin : grst_afull\n      always @(posedge CLK or posedge RST_FULL_FF) begin\n        if (RST_FULL_FF & C_HAS_RST)\n          almost_full_i   <= C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_SRST == 1) begin : gsrst_afull\n      always @(posedge CLK) begin\n        if (srst_wrst_busy)\n          almost_full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_afull\n      always @(posedge CLK) begin\n          almost_full_i   <= #`TCQ ram_afull_comb;\n      end\n    end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_EMPTY flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss\n\n     wire                 ecomp2;\n     wire                 going_aempty;\n     wire                 leaving_aempty;\n     wire                 ram_aempty_comb;\n      \n     assign ecomp2          = (adj_wr_pntr_rd == (rd_pntr + 2'h2));\n   \n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp\n     assign going_aempty    = (ecomp2 & ~write_allow & read_allow);\n     assign leaving_aempty  = (ecomp1 & write_allow & ~read_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp\n      assign going_aempty = (ecomp2 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp \n      assign going_aempty = (ecomp2 & ~write_allow & read_allow);\n      assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);\n    end endgenerate\n\n\n     assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);\n\n     always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         almost_empty_i  <= 1'b1;\n       else if (srst_rrst_busy)\n         almost_empty_i  <= #`TCQ 1'b1;\n       else\n         almost_empty_i  <= #`TCQ ram_aempty_comb;\n      end\n  // end endgenerate // gae_ss\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL\n   //-----------------------------------------------------------------------------\n\n   localparam  C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT \n                                  C_PROG_FULL_THRESH_ASSERT_VAL; // STD\n   localparam  C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT\n                                  C_PROG_FULL_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;   \n   generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin \n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n          prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr>= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  ((diff_pntr) < C_PF_ASSERT_VAL )\n        prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate // single_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr >= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n       else if  (diff_pntr < C_PF_NEGATE_VAL)\n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate //multiple_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT\n                                               PROG_FULL_THRESH; // STD\n   generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input\n\n     always @(posedge CLK or posedge RST_FULL_FF) begin//0\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin //1\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin//2 \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin//3\n           if (diff_pntr > pf3_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if (diff_pntr == pf3_assert_val) begin//4\n             if (read_only_q)\n               prog_full_i <= #`TCQ 1'b0;\n             else\n               prog_full_i <= #`TCQ 1'b1;\n           end else//4\n             prog_full_i <= #`TCQ 1'b0;\n         end else//3\n           prog_full_i <= #`TCQ prog_full_i;\n       end //2\n       else begin//5\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin//6 \n        if (diff_pntr >= pf3_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  (diff_pntr < pf3_assert_val) begin//7\n         prog_full_i <= #`TCQ 1'b0;\n       end//7\n       end//6\n      else\n           prog_full_i <= #`TCQ prog_full_i;\n       end//5\n     end//1\n     end//0\n   end endgenerate //single_pf_input\n  \n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_ASSERT; // STD\n   wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_NEGATE; // STD\n\n   generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin\n           if (diff_pntr >= pf_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if ((diff_pntr == pf_negate_val && read_only_q) ||\n                  diff_pntr < pf_negate_val)\n             prog_full_i <= #`TCQ 1'b0;\n           else\n             prog_full_i <= #`TCQ prog_full_i;\n         end else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin \n        if (diff_pntr >= pf_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n       else if (diff_pntr < pf_negate_val) \n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n\n     end\n   end\n   end endgenerate //multiple_pf_inputs\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY\n   //-----------------------------------------------------------------------------\n   localparam  C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD\n   localparam  C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i) \n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy) \n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL)\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > C_PE_ASSERT_VAL)\n         prog_empty_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n     end\n     end\n   end endgenerate // single_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > C_PE_NEGATE_VAL) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n\n     end\n\n     end\n   end endgenerate //multiple_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH -2) : // FWFT\n                                                PROG_EMPTY_THRESH; // STD\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe < pe3_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (diff_pntr_pe == pe3_assert_val) begin\n             if (write_only_q)\n               prog_empty_i <= #`TCQ 1'b0;\n             else\n               prog_empty_i <= #`TCQ 1'b1;\n           end else\n             prog_empty_i <= #`TCQ 1'b0;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe3_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > pe3_assert_val)\n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n\n     end\n   end endgenerate // single_pe_input\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_ASSERT; // STD\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_NEGATE; // STD\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n      else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe <= pe4_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || \n                     (diff_pntr_pe > pe4_negate_val)) begin\n             prog_empty_i <= #`TCQ 1'b0;\n           end else\n             prog_empty_i <= #`TCQ prog_empty_i;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe4_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > pe4_negate_val) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n     end\n   end endgenerate // multiple_pe_inputs\n\nendmodule // fifo_generator_v13_2_5_bhv_ver_ss\n\n\n\n/**************************************************************************\n * First-Word Fall-Through module (preload 0)\n **************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_preload0\n  #(\n    parameter  C_DOUT_RST_VAL            = \"\",\n    parameter  C_DOUT_WIDTH              = 8,\n    parameter  C_HAS_RST                 = 0,\n    parameter  C_ENABLE_RST_SYNC         = 0,\n    parameter  C_HAS_SRST                = 0,\n    parameter  C_USE_EMBEDDED_REG        = 0,\n    parameter  C_EN_SAFETY_CKT           = 0, \n    parameter  C_USE_DOUT_RST            = 0,\n    parameter  C_USE_ECC                 = 0,\n    parameter  C_USERVALID_LOW           = 0,\n    parameter  C_USERUNDERFLOW_LOW       = 0,\n    parameter  C_MEMORY_TYPE             = 0,\n    parameter  C_FIFO_TYPE               = 0\n  )\n  (\n    //Inputs\n    input                          SAFETY_CKT_RD_RST,\n    input                          RD_CLK,\n    input                          RD_RST,\n    input                          SRST,\n    input                          WR_RST_BUSY,\n    input                          RD_RST_BUSY,\n    input                          RD_EN,\n    input                          FIFOEMPTY,\n    input       [C_DOUT_WIDTH-1:0] FIFODATA,\n    input                          FIFOSBITERR,\n    input                          FIFODBITERR,\n   \n    //Outputs\n    output reg  [C_DOUT_WIDTH-1:0] USERDATA,\n    output                         USERVALID,\n    output                         USERUNDERFLOW,\n    output                         USEREMPTY,\n    output                         USERALMOSTEMPTY,\n    output                         RAMVALID,\n    output                         FIFORDEN,\n    output reg                     USERSBITERR,\n    output reg                     USERDBITERR,\n    output reg                     STAGE2_REG_EN,\n    output                         fab_read_data_valid_i_o,\n    output                         read_data_valid_i_o,\n    output                         ram_valid_i_o,\n    output      [1:0]              VALID_STAGES \n  );\n //Internal signals\n wire                      preloadstage1;\n wire                      preloadstage2;\n reg                       ram_valid_i;\n reg                       fab_valid;\n reg                       read_data_valid_i;\n reg                       fab_read_data_valid_i;\n reg                       fab_read_data_valid_i_1;\n reg                       ram_valid_i_d;\n reg                       read_data_valid_i_d;\n reg                       fab_read_data_valid_i_d;\n wire                      ram_regout_en;\n reg                       ram_regout_en_d1;\n reg                       ram_regout_en_d2;\n wire                      fab_regout_en;\n wire                      ram_rd_en;\n reg                       empty_i        = 1'b1;\n reg                       empty_sckt     = 1'b1;\n reg                       sckt_rrst_q    = 1'b0;\n reg                       sckt_rrst_done = 1'b0;\n reg                       empty_q        = 1'b1;\n reg                       rd_en_q        = 1'b0;\n reg                       almost_empty_i = 1'b1;\n reg                       almost_empty_q = 1'b1;\n wire                      rd_rst_i;\n wire                      srst_i;\n reg  [C_DOUT_WIDTH-1:0]   userdata_both;\n wire                      uservalid_both;\n wire                      uservalid_one;\n reg                       user_sbiterr_both = 1'b0;\n reg                       user_dbiterr_both = 1'b0;\n  \nassign ram_valid_i_o = ram_valid_i;\nassign read_data_valid_i_o = read_data_valid_i;\nassign fab_read_data_valid_i_o = fab_read_data_valid_i; \n\n\n\n/*************************************************************************\n* FUNCTIONS\n*************************************************************************/\n\n   /*************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***********************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n   \n   //*************************************************************************\n   //  Set power-on states for regs\n   //*************************************************************************\n   initial begin\n      ram_valid_i       = 1'b0;\n      fab_valid         = 1'b0;\n      read_data_valid_i = 1'b0;\n      fab_read_data_valid_i = 1'b0;\n      fab_read_data_valid_i_1 = 1'b0;\n      USERDATA          = hexstr_conv(C_DOUT_RST_VAL);\n      userdata_both          = hexstr_conv(C_DOUT_RST_VAL);\n      USERSBITERR       = 1'b0;\n      USERDBITERR       = 1'b0;\n      user_sbiterr_both = 1'b0;\n      user_dbiterr_both = 1'b0;\n   end //initial\n\n   //***************************************************************************\n   //  connect up optional reset\n   //***************************************************************************\n   assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;\n   assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;\n\n   reg  sckt_rd_rst_fwft = 1'b0;\n   reg  fwft_rst_done_i  = 1'b0;\n   wire fwft_rst_done;\n   assign fwft_rst_done = 1'b1;//C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;\n   always @ (posedge RD_CLK) begin\n     sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;\n   end\n\n   always @ (posedge rd_rst_i or posedge RD_CLK) begin\n     if (rd_rst_i)\n       fwft_rst_done_i  <= 1'b0;\n     else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)\n       fwft_rst_done_i  <= #`TCQ 1'b1;\n   end\n\n   localparam INVALID             = 0;\n   localparam STAGE1_VALID        = 2;\n   localparam STAGE2_VALID        = 1;\n   localparam BOTH_STAGES_VALID   = 3;\n\n   reg  [1:0] curr_fwft_state = INVALID;\n   reg  [1:0] next_fwft_state = INVALID;\n\n\ngenerate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin\n         always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n \n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n     \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n    \n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = preloadstage2;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;\n   end\nendgenerate // gnll_fifo\n\n   reg curr_state         = 0;\n   reg next_state         = 0;\n   reg leaving_empty_fwft = 0;\n   reg going_empty_fwft   = 0;\n   reg empty_i_q          = 0;\n   reg ram_rd_en_fwft     = 0;\n   generate if (C_FIFO_TYPE == 2) begin : gll_fifo\n     always @* begin // FSM fo FWFT\n       case (curr_state)\n         1'b0: begin\n           if (~FIFOEMPTY)\n             next_state <= 1'b1;\n           else\n             next_state <= 1'b0;\n           end\n         1'b1: begin\n           if (FIFOEMPTY && RD_EN)\n             next_state <= 1'b0;\n           else\n             next_state <= 1'b1;\n           end\n         default: next_state <= 1'b0;\n       endcase\n     end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_i       <= 1'b1;\n           empty_i_q     <= 1'b1;\n           ram_valid_i   <= 1'b0;\n        end else if (srst_i) begin\n           empty_i       <= #`TCQ 1'b1;\n           empty_i_q     <= #`TCQ 1'b1;\n           ram_valid_i   <= #`TCQ 1'b0;\n        end else begin\n           empty_i       <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);\n           empty_i_q     <= #`TCQ FIFOEMPTY;\n           ram_valid_i   <= #`TCQ next_state;\n        end\n     end //always\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n           curr_state    <= 1'b0;\n        end else if (srst_i) begin\n           curr_state    <= #`TCQ 1'b0;\n        end else begin\n           curr_state    <= #`TCQ next_state;\n        end\n     end //always\n\n     wire                  fe_of_empty; \n     assign fe_of_empty   = empty_i_q & ~FIFOEMPTY;\n\n     always @* begin // Finding leaving empty\n       case (curr_state)\n         1'b0:    leaving_empty_fwft <= fe_of_empty;\n         1'b1:    leaving_empty_fwft <= 1'b1;\n         default: leaving_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Finding going empty\n       case (curr_state)\n         1'b1:    going_empty_fwft <= FIFOEMPTY & RD_EN;\n         default: going_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Generating FWFT rd_en\n       case (curr_state)\n         1'b0:    ram_rd_en_fwft <= ~FIFOEMPTY;\n         1'b1:    ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;\n         default: ram_rd_en_fwft <= 1'b0;\n       endcase\n     end\n\n     assign ram_regout_en = ram_rd_en_fwft;\n     //assign ram_regout_en_d1 = ram_rd_en_fwft;\n     //assign ram_regout_en_d2 = ram_rd_en_fwft;\n     assign ram_rd_en     = ram_rd_en_fwft;\n   end endgenerate // gll_fifo\n\n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false.\n   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n   generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           ram_valid_i     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              ram_valid_i     <= #`TCQ 1'b0;\n           end else begin\n              if (ram_rd_en == 1'b1) begin\n                 ram_valid_i   <= #`TCQ 1'b1;\n              end else begin\n                 if (ram_regout_en == 1'b1)\n                   ram_valid_i <= #`TCQ 1'b0;\n                 else\n                   ram_valid_i <= #`TCQ ram_valid_i;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_ram_valid\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n  \n generate if(C_USE_EMBEDDED_REG < 3) begin\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else\n        read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);\n   end //always\nend \nendgenerate\n\n   \n   \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n generate if ( C_USE_EMBEDDED_REG < 3) begin\n  always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin         // asynchronous reset (active high)\n             almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ FIFOEMPTY;\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n   \n   \n     \n  // BRAM resets synchronously\n generate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin\n   always @ ( posedge rd_rst_i)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n           @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n             USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end  else if (fwft_rst_done) begin\n            if (ram_regout_en) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end\n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n//safety ckt with one register\ngenerate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n            @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n        end\n     end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n          //@(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end \n       end\n        else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n            //  @(posedge RD_CLK)\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end else if (fwft_rst_done) begin\n            if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end          \n          end\n        end\n       end //always\n  end //if\nendgenerate\n\n\ngenerate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin\n         \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d1 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d1 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d1 <= #`TCQ ram_regout_en;\n                 end\n            end //always\n   //  assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));\n       assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d2 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d2 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;\n                 end\n            end //always\n\n    \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n     always @ (posedge RD_CLK) begin\n        ram_valid_i_d <= #`TCQ ram_valid_i;\n        read_data_valid_i_d <= #`TCQ read_data_valid_i;\n        fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;\n\n     end\n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n    \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;\n   end\n   endgenerate // gnll_fifo\n\n   \n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n     generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid\n\n     \n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           fab_valid     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              fab_valid    <= #`TCQ 1'b0;\n           end else begin\n              if (ram_regout_en == 1'b1) begin\n                 fab_valid  <= #`TCQ 1'b1;\n              end else begin\n                 if (fab_regout_en == 1'b1)\n                   fab_valid <= #`TCQ 1'b0;\n                 else\n                   fab_valid <= #`TCQ fab_valid;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_fab_valid\n\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n    generate if(C_USE_EMBEDDED_REG == 3) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else begin\n        if (ram_regout_en == 1'b1) begin\n          read_data_valid_i <= #`TCQ 1'b1;\n        end else begin\n         if (fab_regout_en == 1'b1)\n          read_data_valid_i <= #`TCQ 1'b0;\n        else\n          read_data_valid_i <= #`TCQ read_data_valid_i;\n        end \n      end \n   end //always\nend\nendgenerate\n\n//generate if(C_USE_EMBEDDED_REG == 3) begin\n//   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n//      if (rd_rst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//      else if (srst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//\n//      if (ram_regout_en == 1'b1) begin\n//        fab_read_data_valid_i <= #`TCQ 1'b0;\n//      end else begin\n//       if (fab_regout_en == 1'b1)\n//        fab_read_data_valid_i <= #`TCQ 1'b1;\n//      else\n//        fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;\n//      end \n//   end //always\n//end\n//endgenerate\n\n     generate if(C_USE_EMBEDDED_REG == 3 ) begin \n    always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid\n      if (rd_rst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else \n        fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);\n   end //always\nend\nendgenerate\n \nalways @ (posedge RD_CLK ) begin : proc_del1\n             begin\n                 fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;\n              end\n            end //always\n \n \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty_both\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n   reg FIFOEMPTY_1;\n   generate if (C_USE_EMBEDDED_REG == 3 ) begin\n    always @(posedge RD_CLK) begin\n            FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;\n           end\n    end\nendgenerate\n    generate if (C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n   begin\n      if (rd_rst_i) begin         // asynchronous reset (active high)\n           almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ (~ram_valid_i);\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_sckt <= #`TCQ 1'b1;\n           sckt_rrst_q <= #`TCQ 1'b0;\n           sckt_rrst_done <= #`TCQ 1'b0;\n        end else begin\n           sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;\n           if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin\n              sckt_rrst_done <= #`TCQ 1'b1;\n           end else if (sckt_rrst_done) begin\n              // rising clock edge\n              empty_sckt <= #`TCQ 1'b0;\n           end\n        end\n     end //always\n   \n   \n//   assign USEREMPTY       = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;\n   assign USEREMPTY       = empty_i;\n   assign USERALMOSTEMPTY = almost_empty_i;\n   assign FIFORDEN        = ram_rd_en;\n   assign RAMVALID        = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;\n   assign uservalid_both       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3)  ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);\n   assign uservalid_one       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3)  ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);\n   assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;\n   assign USERUNDERFLOW   = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;\n//no safety ckt with both reg\ngenerate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n            USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              userdata_both   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end else begin\n            if (fwft_rst_done) begin\n              if (ram_regout_en) begin\n                 userdata_both     <= #`TCQ FIFODATA; \n                 user_dbiterr_both <= #`TCQ FIFODBITERR;\n                 user_sbiterr_both <= #`TCQ FIFOSBITERR; \n              end\n              if (fab_regout_en) begin\n                 USERDATA     <= #`TCQ userdata_both;\n                 USERDBITERR  <= #`TCQ user_dbiterr_both;\n                 USERSBITERR  <= #`TCQ user_sbiterr_both; \n              end             \n            end             \n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n\n//safety_ckt with both registers\n generate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always @ (posedge RD_CLK) begin\n          if (rd_rst_i || srst_i) begin\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n              @(posedge RD_CLK)\n              USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n               userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end\n        end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n     if (rd_rst_i) begin //asynchronous reset (active high)\n       if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n         USERSBITERR       <= #`TCQ 0;\n         USERDBITERR       <= #`TCQ 0;\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end\n       // DRAM resets asynchronously\n       if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n         USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end \n     end else begin // rising clock edge\n       if (srst_i) begin\n         if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n           USERSBITERR       <= #`TCQ 0;\n           USERDBITERR       <= #`TCQ 0;\n           user_sbiterr_both <= #`TCQ 0;\n           user_dbiterr_both <= #`TCQ 0;\n         end\n         if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n           USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end\n       end else if (fwft_rst_done) begin\n         if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            userdata_both     <= #`TCQ FIFODATA;\n            user_dbiterr_both <= #`TCQ FIFODBITERR;\n            user_sbiterr_both <= #`TCQ FIFOSBITERR; \n         end\n         if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            USERDATA          <= #`TCQ userdata_both;\n            USERDBITERR       <= #`TCQ user_dbiterr_both;\n            USERSBITERR       <= #`TCQ user_sbiterr_both;\n         end\n       end\n     end\n   end //always\n  end //if\nendgenerate\n\nendmodule //fifo_generator_v13_2_5_bhv_ver_preload0\n\n\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Register one AXI channel on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   reg_slice\n//\n//--------------------------------------------------------------------------\n\nmodule fifo_generator_v13_2_5_axic_reg_slice #\n  (\n   parameter C_FAMILY     = \"virtex7\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   )\n  (\n   // System Signals\n   input  wire                      ACLK,\n   input  wire                      ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0]   S_PAYLOAD_DATA,\n   input  wire                      S_VALID,\n   output wire                      S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0]   M_PAYLOAD_DATA,\n   output wire                      M_VALID,\n   input  wire                      M_READY\n   );\n\n  localparam RST_SYNC_STAGES = 5;\n  localparam RST_BUSY_LEN    = 6;\n  reg [1:0] arst_sync_wr  = 2'b11;\n  reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n  wire sync_reset;\n  wire extnd_reset;\n\n\n  always @(posedge ARESET or posedge ACLK) begin\n    if (ARESET)\n      arst_sync_wr <= 2'b11;\n    else\n      arst_sync_wr <= #`TCQ {arst_sync_wr[0], 1'b0};\n  end\n\n  always @(posedge ACLK) begin\n    sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[1]};\n  end\n\n  assign sync_reset     = |sckt_wr_rst_cc[RST_BUSY_LEN-5:0] | arst_sync_wr[1]; \n  assign extnd_reset    = |sckt_wr_rst_cc | arst_sync_wr[1];\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000)\n    begin\n      reg [1:0] state;\n      localparam [1:0] \n        ZERO = 2'b10,\n        ONE  = 2'b11,\n        TWO  = 2'b01;\n      \n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg [C_DATA_WIDTH-1:0] storage_data2 = 0;\n      reg                    load_s1;\n      wire                   load_s2;\n      wire                   load_s1_from_s2;\n      reg                    s_ready_i; //local signal of output\n      wire                   m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with either slave side data or from storage2\n      always @(posedge ACLK) \n      begin\n        if (load_s1)\n          if (load_s1_from_s2)\n            storage_data1 <= storage_data2;\n          else\n            storage_data1 <= S_PAYLOAD_DATA;        \n      end\n\n      // Load storage2 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data1;\n\n      // Always load s2 on a valid transaction even if it's unnecessary\n      assign load_s2 = S_VALID & s_ready_i;\n\n      // Loading s1\n      always @ *\n      begin\n        if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction\n             // Load when ONE if we both have read and write at the same time\n             ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||\n             // Load when TWO and we have a transaction on Master side\n             ((state == TWO) && (M_READY == 1)))\n          load_s1 = 1'b1;\n        else\n          load_s1 = 1'b0;\n      end // always @ *\n\n      assign load_s1_from_s2 = (state == TWO);\n                       \n      // State Machine for handling output signals\n      always @(posedge ACLK) begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          state <= ZERO;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          case (state)\n            // No transaction stored locally\n            ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE\n\n            // One transaction stored locally\n            ONE: begin\n              if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO\n              if (~M_READY & S_VALID) begin\n                state <= TWO;  // Got another one so move to TWO\n                s_ready_i <= 1'b0;\n              end\n            end\n\n            // TWO transaction stored locally\n            TWO: if (M_READY) begin\n              state <= ONE; // Read out one so move to ONE\n              s_ready_i <= 1'b1;\n            end\n          endcase // case (state)\n        end\n      end // always @ (posedge ACLK)\n      \n      assign m_valid_i = state[0];\n\n    end // if (C_REG_CONFIG == 1)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000001)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg                    s_ready_i; //local signal of output\n      reg                    m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b0;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else if (m_valid_i & M_READY) begin\n          s_ready_i <= 1'b1;\n          m_valid_i <= 1'b0;\n        end else if (S_VALID & s_ready_i) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b1;\n        end\n        if (~m_valid_i) begin\n          storage_data1 <= S_PAYLOAD_DATA;        \n        end\n      end\n      assign M_PAYLOAD_DATA = storage_data1;\n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // reg_slice\n", "num_lines": 10520}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Generic single-channel AXI FIFO\n// Synchronous FIFO is implemented using either LUTs (SRL) or BRAM.\n// Transfers received on the AXI slave port are pushed onto the FIFO.\n// FIFO output, when available, is presented on the AXI master port and\n//   popped when the master port responds (M_READY).\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n// Structure:\n//   axic_fifo\n//     fifo_gen\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_21_axic_fifo #\n  (\n   parameter         C_FAMILY          = \"virtex6\",\n   parameter integer C_FIFO_DEPTH_LOG  = 5,      // FIFO depth = 2**C_FIFO_DEPTH_LOG\n                                                 // Range = [5:9] when TYPE=\"lut\",\n                                                 // Range = [5:12] when TYPE=\"bram\",\n   parameter integer C_FIFO_WIDTH      = 64,     // Width of payload [1:512]\n   parameter         C_FIFO_TYPE       = \"lut\"   // \"lut\" = LUT (SRL) based,\n                                                 // \"bram\" = BRAM based\n   )\n  (\n   // Global inputs\n   input  wire                        ACLK,    // Clock\n   input  wire                        ARESET,  // Reset\n   // Slave  Port\n   input  wire [C_FIFO_WIDTH-1:0]     S_MESG,  // Payload (may be any set of channel signals)\n   input  wire                        S_VALID, // FIFO push\n   output wire                        S_READY, // FIFO not full\n   // Master  Port\n   output wire [C_FIFO_WIDTH-1:0]     M_MESG,  // Payload\n   output wire                        M_VALID, // FIFO not empty\n   input  wire                        M_READY  // FIFO pop\n   );\n\n   axi_data_fifo_v2_1_21_fifo_gen #(\n     .C_FAMILY(C_FAMILY),\n     .C_COMMON_CLOCK(1),\n     .C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),\n     .C_FIFO_WIDTH(C_FIFO_WIDTH),\n     .C_FIFO_TYPE(C_FIFO_TYPE))\n   inst (\n     .clk(ACLK),\n     .rst(ARESET),\n     .wr_clk(1'b0),\n     .wr_en(S_VALID),\n     .wr_ready(S_READY),\n     .wr_data(S_MESG),\n     .rd_clk(1'b0),\n     .rd_en(M_READY),\n     .rd_valid(M_VALID),\n     .rd_data(M_MESG));\n\nendmodule\n\n\n// -- (c) Copyright 1995 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------\n\n// The synthesis directives \"translate_off/translate_on\" specified below are\n// supported by Xilinx, Mentor Graphics and Synplicity synthesis\n// tools. Ensure they are correct for your synthesis tool(s).\n\n// You must compile the fifo_generator wrapper file when simulating\n// the core. When compiling the wrapper file, be sure to\n// reference the XilinxCoreLib Verilog simulation library. For detailed\n// instructions, please refer to the \"CORE Generator Help\".\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_21_fifo_gen #(\nparameter C_FAMILY          = \"virtex7\",\nparameter integer C_COMMON_CLOCK    = 1,\nparameter integer C_SYNCHRONIZER_STAGE = 3,\nparameter integer C_FIFO_DEPTH_LOG  = 5,\nparameter integer C_FIFO_WIDTH      = 64,\nparameter C_FIFO_TYPE       = \"lut\"\n)(\n  clk,\n  rst,\n  wr_clk,\n  wr_en,\n  wr_ready,\n  wr_data,\n  rd_clk,\n  rd_en,\n  rd_valid,\n  rd_data);\n\ninput clk;\ninput wr_clk;\ninput rd_clk;\ninput rst;\ninput [C_FIFO_WIDTH-1 : 0] wr_data;\ninput wr_en;\ninput rd_en;\noutput [C_FIFO_WIDTH-1 : 0] rd_data;\noutput wr_ready;\noutput rd_valid;\n\nwire  full;\nwire  empty;\nwire  rd_valid = ~empty;\nwire  wr_ready = ~full;\n\nlocalparam C_MEMORY_TYPE =  (C_FIFO_TYPE == \"bram\")? 1 : 2;\n\nlocalparam C_IMPLEMENTATION_TYPE = (C_COMMON_CLOCK == 1)? 0 : 2;\n\n  fifo_generator_v13_2_5 #(\n    .C_COMMON_CLOCK(C_COMMON_CLOCK),\n    .C_DIN_WIDTH(C_FIFO_WIDTH),\n    .C_DOUT_WIDTH(C_FIFO_WIDTH),\n    .C_FAMILY(C_FAMILY),\n    .C_IMPLEMENTATION_TYPE(C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE(C_MEMORY_TYPE),\n    .C_RD_DEPTH(1<<C_FIFO_DEPTH_LOG),\n    .C_RD_PNTR_WIDTH(C_FIFO_DEPTH_LOG),\n    .C_WR_DEPTH(1<<C_FIFO_DEPTH_LOG),\n    .C_WR_PNTR_WIDTH(C_FIFO_DEPTH_LOG),\n    .C_ADD_NGC_CONSTRAINT(0),\n    .C_APPLICATION_TYPE_AXIS(0),\n    .C_APPLICATION_TYPE_RACH(0),\n    .C_APPLICATION_TYPE_RDCH(0),\n    .C_APPLICATION_TYPE_WACH(0),\n    .C_APPLICATION_TYPE_WDCH(0),\n    .C_APPLICATION_TYPE_WRCH(0),\n    .C_AXIS_TDATA_WIDTH(64),\n    .C_AXIS_TDEST_WIDTH(4),\n    .C_AXIS_TID_WIDTH(8),\n    .C_AXIS_TKEEP_WIDTH(4),\n    .C_AXIS_TSTRB_WIDTH(4),\n    .C_AXIS_TUSER_WIDTH(4),\n    .C_AXIS_TYPE(0),\n    .C_AXI_ADDR_WIDTH(32),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_AXI_DATA_WIDTH(64),\n    .C_AXI_ID_WIDTH(4),\n    .C_AXI_LEN_WIDTH(8),\n    .C_AXI_LOCK_WIDTH(2),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_TYPE(0),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_COUNT_TYPE(0),\n    .C_DATA_COUNT_WIDTH(6),\n    .C_DEFAULT_VALUE(\"BlankString\"),\n    .C_DIN_WIDTH_AXIS(1),\n    .C_DIN_WIDTH_RACH(32),\n    .C_DIN_WIDTH_RDCH(64),\n    .C_DIN_WIDTH_WACH(32),\n    .C_DIN_WIDTH_WDCH(64),\n    .C_DIN_WIDTH_WRCH(2),\n    .C_DOUT_RST_VAL(\"0\"),\n    .C_ENABLE_RLOCS(0),\n    .C_ENABLE_RST_SYNC(1),\n    .C_ERROR_INJECTION_TYPE(0),\n    .C_ERROR_INJECTION_TYPE_AXIS(0),\n    .C_ERROR_INJECTION_TYPE_RACH(0),\n    .C_ERROR_INJECTION_TYPE_RDCH(0),\n    .C_ERROR_INJECTION_TYPE_WACH(0),\n    .C_ERROR_INJECTION_TYPE_WDCH(0),\n    .C_ERROR_INJECTION_TYPE_WRCH(0),\n    .C_FULL_FLAGS_RST_VAL(0),\n    .C_HAS_ALMOST_EMPTY(0),\n    .C_HAS_ALMOST_FULL(0),\n    .C_HAS_AXIS_TDATA(0),\n    .C_HAS_AXIS_TDEST(0),\n    .C_HAS_AXIS_TID(0),\n    .C_HAS_AXIS_TKEEP(0),\n    .C_HAS_AXIS_TLAST(0),\n    .C_HAS_AXIS_TREADY(1),\n    .C_HAS_AXIS_TSTRB(0),\n    .C_HAS_AXIS_TUSER(0),\n    .C_HAS_AXI_ARUSER(0),\n    .C_HAS_AXI_AWUSER(0),\n    .C_HAS_AXI_BUSER(0),\n    .C_HAS_AXI_RD_CHANNEL(0),\n    .C_HAS_AXI_RUSER(0),\n    .C_HAS_AXI_WR_CHANNEL(0),\n    .C_HAS_AXI_WUSER(0),\n    .C_HAS_BACKUP(0),\n    .C_HAS_DATA_COUNT(0),\n    .C_HAS_DATA_COUNTS_AXIS(0),\n    .C_HAS_DATA_COUNTS_RACH(0),\n    .C_HAS_DATA_COUNTS_RDCH(0),\n    .C_HAS_DATA_COUNTS_WACH(0),\n    .C_HAS_DATA_COUNTS_WDCH(0),\n    .C_HAS_DATA_COUNTS_WRCH(0),\n    .C_HAS_INT_CLK(0),\n    .C_HAS_MASTER_CE(0),\n    .C_HAS_MEMINIT_FILE(0),\n    .C_HAS_OVERFLOW(0),\n    .C_HAS_PROG_FLAGS_AXIS(0),\n    .C_HAS_PROG_FLAGS_RACH(0),\n    .C_HAS_PROG_FLAGS_RDCH(0),\n    .C_HAS_PROG_FLAGS_WACH(0),\n    .C_HAS_PROG_FLAGS_WDCH(0),\n    .C_HAS_PROG_FLAGS_WRCH(0),\n    .C_HAS_RD_DATA_COUNT(0),\n    .C_HAS_RD_RST(0),\n    .C_HAS_RST(1),\n    .C_HAS_SLAVE_CE(0),\n    .C_HAS_SRST(0),\n    .C_HAS_UNDERFLOW(0),\n    .C_HAS_VALID(0),\n    .C_HAS_WR_ACK(0),\n    .C_HAS_WR_DATA_COUNT(0),\n    .C_HAS_WR_RST(0),\n    .C_IMPLEMENTATION_TYPE_AXIS(1),\n    .C_IMPLEMENTATION_TYPE_RACH(1),\n    .C_IMPLEMENTATION_TYPE_RDCH(1),\n    .C_IMPLEMENTATION_TYPE_WACH(1),\n    .C_IMPLEMENTATION_TYPE_WDCH(1),\n    .C_IMPLEMENTATION_TYPE_WRCH(1),\n    .C_INIT_WR_PNTR_VAL(0),\n    .C_INTERFACE_TYPE(0),\n    .C_MIF_FILE_NAME(\"BlankString\"),\n    .C_MSGON_VAL(1),\n    .C_OPTIMIZATION_MODE(0),\n    .C_OVERFLOW_LOW(0),\n    .C_PRELOAD_LATENCY(0),\n    .C_PRELOAD_REGS(1),\n    .C_PRIM_FIFO_TYPE(\"512x36\"),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),\n    .C_PROG_EMPTY_TYPE(0),\n    .C_PROG_EMPTY_TYPE_AXIS(0),\n    .C_PROG_EMPTY_TYPE_RACH(0),\n    .C_PROG_EMPTY_TYPE_RDCH(0),\n    .C_PROG_EMPTY_TYPE_WACH(0),\n    .C_PROG_EMPTY_TYPE_WDCH(0),\n    .C_PROG_EMPTY_TYPE_WRCH(0),\n    .C_PROG_FULL_THRESH_ASSERT_VAL(31),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),\n    .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),\n    .C_PROG_FULL_THRESH_NEGATE_VAL(30),\n    .C_PROG_FULL_TYPE(0),\n    .C_PROG_FULL_TYPE_AXIS(0),\n    .C_PROG_FULL_TYPE_RACH(0),\n    .C_PROG_FULL_TYPE_RDCH(0),\n    .C_PROG_FULL_TYPE_WACH(0),\n    .C_PROG_FULL_TYPE_WDCH(0),\n    .C_PROG_FULL_TYPE_WRCH(0),\n    .C_RACH_TYPE(0),\n    .C_RDCH_TYPE(0),\n    .C_RD_DATA_COUNT_WIDTH(6),\n    .C_RD_FREQ(1),\n    .C_REG_SLICE_MODE_AXIS(0),\n    .C_REG_SLICE_MODE_RACH(0),\n    .C_REG_SLICE_MODE_RDCH(0),\n    .C_REG_SLICE_MODE_WACH(0),\n    .C_REG_SLICE_MODE_WDCH(0),\n    .C_REG_SLICE_MODE_WRCH(0),\n    .C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),\n    .C_UNDERFLOW_LOW(0),\n    .C_USE_COMMON_OVERFLOW(0),\n    .C_USE_COMMON_UNDERFLOW(0),\n    .C_USE_DEFAULT_SETTINGS(0),\n    .C_USE_DOUT_RST(0),\n    .C_USE_ECC(0),\n    .C_USE_ECC_AXIS(0),\n    .C_USE_ECC_RACH(0),\n    .C_USE_ECC_RDCH(0),\n    .C_USE_ECC_WACH(0),\n    .C_USE_ECC_WDCH(0),\n    .C_USE_ECC_WRCH(0),\n    .C_USE_EMBEDDED_REG(0),\n    .C_USE_FIFO16_FLAGS(0),\n    .C_USE_FWFT_DATA_COUNT(1),\n    .C_VALID_LOW(0),\n    .C_WACH_TYPE(0),\n    .C_WDCH_TYPE(0),\n    .C_WRCH_TYPE(0),\n    .C_WR_ACK_LOW(0),\n    .C_WR_DATA_COUNT_WIDTH(6),\n    .C_WR_DEPTH_AXIS(1024),\n    .C_WR_DEPTH_RACH(16),\n    .C_WR_DEPTH_RDCH(1024),\n    .C_WR_DEPTH_WACH(16),\n    .C_WR_DEPTH_WDCH(1024),\n    .C_WR_DEPTH_WRCH(16),\n    .C_WR_FREQ(1),\n    .C_WR_PNTR_WIDTH_AXIS(10),\n    .C_WR_PNTR_WIDTH_RACH(4),\n    .C_WR_PNTR_WIDTH_RDCH(10),\n    .C_WR_PNTR_WIDTH_WACH(4),\n    .C_WR_PNTR_WIDTH_WDCH(10),\n    .C_WR_PNTR_WIDTH_WRCH(4),\n    .C_WR_RESPONSE_LATENCY(1)\n    )\n  fifo_gen_inst (\n    .clk(clk),\n    .din(wr_data),\n    .dout(rd_data),\n    .empty(empty),\n    .full(full),\n    .rd_clk(rd_clk),\n    .rd_en(rd_en),\n    .rst(rst),\n    .wr_clk(wr_clk),\n    .wr_en(wr_en),\n    .almost_empty(),\n    .almost_full(),\n    .axi_ar_data_count(),\n    .axi_ar_dbiterr(),\n    .axi_ar_injectdbiterr(1'b0),\n    .axi_ar_injectsbiterr(1'b0),\n    .axi_ar_overflow(),\n    .axi_ar_prog_empty(),\n    .axi_ar_prog_empty_thresh(4'b0),\n    .axi_ar_prog_full(),\n    .axi_ar_prog_full_thresh(4'b0),\n    .axi_ar_rd_data_count(),\n    .axi_ar_sbiterr(),\n    .axi_ar_underflow(),\n    .axi_ar_wr_data_count(),\n    .axi_aw_data_count(),\n    .axi_aw_dbiterr(),\n    .axi_aw_injectdbiterr(1'b0),\n    .axi_aw_injectsbiterr(1'b0),\n    .axi_aw_overflow(),\n    .axi_aw_prog_empty(),\n    .axi_aw_prog_empty_thresh(4'b0),\n    .axi_aw_prog_full(),\n    .axi_aw_prog_full_thresh(4'b0),\n    .axi_aw_rd_data_count(),\n    .axi_aw_sbiterr(),\n    .axi_aw_underflow(),\n    .axi_aw_wr_data_count(),\n    .axi_b_data_count(),\n    .axi_b_dbiterr(),\n    .axi_b_injectdbiterr(1'b0),\n    .axi_b_injectsbiterr(1'b0),\n    .axi_b_overflow(),\n    .axi_b_prog_empty(),\n    .axi_b_prog_empty_thresh(4'b0),\n    .axi_b_prog_full(),\n    .axi_b_prog_full_thresh(4'b0),\n    .axi_b_rd_data_count(),\n    .axi_b_sbiterr(),\n    .axi_b_underflow(),\n    .axi_b_wr_data_count(),\n    .axi_r_data_count(),\n    .axi_r_dbiterr(),\n    .axi_r_injectdbiterr(1'b0),\n    .axi_r_injectsbiterr(1'b0),\n    .axi_r_overflow(),\n    .axi_r_prog_empty(),\n    .axi_r_prog_empty_thresh(10'b0),\n    .axi_r_prog_full(),\n    .axi_r_prog_full_thresh(10'b0),\n    .axi_r_rd_data_count(),\n    .axi_r_sbiterr(),\n    .axi_r_underflow(),\n    .axi_r_wr_data_count(),\n    .axi_w_data_count(),\n    .axi_w_dbiterr(),\n    .axi_w_injectdbiterr(1'b0),\n    .axi_w_injectsbiterr(1'b0),\n    .axi_w_overflow(),\n    .axi_w_prog_empty(),\n    .axi_w_prog_empty_thresh(10'b0),\n    .axi_w_prog_full(),\n    .axi_w_prog_full_thresh(10'b0),\n    .axi_w_rd_data_count(),\n    .axi_w_sbiterr(),\n    .axi_w_underflow(),\n    .axi_w_wr_data_count(),\n    .axis_data_count(),\n    .axis_dbiterr(),\n    .axis_injectdbiterr(1'b0),\n    .axis_injectsbiterr(1'b0),\n    .axis_overflow(),\n    .axis_prog_empty(),\n    .axis_prog_empty_thresh(10'b0),\n    .axis_prog_full(),\n    .axis_prog_full_thresh(10'b0),\n    .axis_rd_data_count(),\n    .axis_sbiterr(),\n    .axis_underflow(),\n    .axis_wr_data_count(),\n    .backup(1'b0),\n    .backup_marker(1'b0),\n    .data_count(),\n    .dbiterr(),\n    .injectdbiterr(1'b0),\n    .injectsbiterr(1'b0),\n    .int_clk(1'b0),\n    .m_aclk(1'b0),\n    .m_aclk_en(1'b0),\n    .m_axi_araddr(),\n    .m_axi_arburst(),\n    .m_axi_arcache(),\n    .m_axi_arid(),\n    .m_axi_arlen(),\n    .m_axi_arlock(),\n    .m_axi_arprot(),\n    .m_axi_arqos(),\n    .m_axi_arready(1'b0),\n    .m_axi_arregion(),\n    .m_axi_arsize(),\n    .m_axi_aruser(),\n    .m_axi_arvalid(),\n    .m_axi_awaddr(),\n    .m_axi_awburst(),\n    .m_axi_awcache(),\n    .m_axi_awid(),\n    .m_axi_awlen(),\n    .m_axi_awlock(),\n    .m_axi_awprot(),\n    .m_axi_awqos(),\n    .m_axi_awready(1'b0),\n    .m_axi_awregion(),\n    .m_axi_awsize(),\n    .m_axi_awuser(),\n    .m_axi_awvalid(),\n    .m_axi_bid(4'b0),\n    .m_axi_bready(),\n    .m_axi_bresp(2'b0),\n    .m_axi_buser(1'b0),\n    .m_axi_bvalid(1'b0),\n    .m_axi_rdata(64'b0),\n    .m_axi_rid(4'b0),\n    .m_axi_rlast(1'b0),\n    .m_axi_rready(),\n    .m_axi_rresp(2'b0),\n    .m_axi_ruser(1'b0),\n    .m_axi_rvalid(1'b0),\n    .m_axi_wdata(),\n    .m_axi_wid(),\n    .m_axi_wlast(),\n    .m_axi_wready(1'b0),\n    .m_axi_wstrb(),\n    .m_axi_wuser(),\n    .m_axi_wvalid(),\n    .m_axis_tdata(),\n    .m_axis_tdest(),\n    .m_axis_tid(),\n    .m_axis_tkeep(),\n    .m_axis_tlast(),\n    .m_axis_tready(1'b0),\n    .m_axis_tstrb(),\n    .m_axis_tuser(),\n    .m_axis_tvalid(),\n    .overflow(),\n    .prog_empty(),\n    .prog_empty_thresh(5'b0),\n    .prog_empty_thresh_assert(5'b0),\n    .prog_empty_thresh_negate(5'b0),\n    .prog_full(),\n    .prog_full_thresh(5'b0),\n    .prog_full_thresh_assert(5'b0),\n    .prog_full_thresh_negate(5'b0),\n    .rd_data_count(),\n    .rd_rst(1'b0),\n    .s_aclk(1'b0),\n    .s_aclk_en(1'b0),\n    .s_aresetn(1'b0),\n    .s_axi_araddr(32'b0),\n    .s_axi_arburst(2'b0),\n    .s_axi_arcache(4'b0),\n    .s_axi_arid(4'b0),\n    .s_axi_arlen(8'b0),\n    .s_axi_arlock(2'b0),\n    .s_axi_arprot(3'b0),\n    .s_axi_arqos(4'b0),\n    .s_axi_arready(),\n    .s_axi_arregion(4'b0),\n    .s_axi_arsize(3'b0),\n    .s_axi_aruser(1'b0),\n    .s_axi_arvalid(1'b0),\n    .s_axi_awaddr(32'b0),\n    .s_axi_awburst(2'b0),\n    .s_axi_awcache(4'b0),\n    .s_axi_awid(4'b0),\n    .s_axi_awlen(8'b0),\n    .s_axi_awlock(2'b0),\n    .s_axi_awprot(3'b0),\n    .s_axi_awqos(4'b0),\n    .s_axi_awready(),\n    .s_axi_awregion(4'b0),\n    .s_axi_awsize(3'b0),\n    .s_axi_awuser(1'b0),\n    .s_axi_awvalid(1'b0),\n    .s_axi_bid(),\n    .s_axi_bready(1'b0),\n    .s_axi_bresp(),\n    .s_axi_buser(),\n    .s_axi_bvalid(),\n    .s_axi_rdata(),\n    .s_axi_rid(),\n    .s_axi_rlast(),\n    .s_axi_rready(1'b0),\n    .s_axi_rresp(),\n    .s_axi_ruser(),\n    .s_axi_rvalid(),\n    .s_axi_wdata(64'b0),\n    .s_axi_wid(4'b0),\n    .s_axi_wlast(1'b0),\n    .s_axi_wready(),\n    .s_axi_wstrb(8'b0),\n    .s_axi_wuser(1'b0),\n    .s_axi_wvalid(1'b0),\n    .s_axis_tdata(64'b0),\n    .s_axis_tdest(4'b0),\n    .s_axis_tid(8'b0),\n    .s_axis_tkeep(4'b0),\n    .s_axis_tlast(1'b0),\n    .s_axis_tready(),\n    .s_axis_tstrb(4'b0),\n    .s_axis_tuser(4'b0),\n    .s_axis_tvalid(1'b0),\n    .sbiterr(),\n    .srst(1'b0),\n    .underflow(),\n    .valid(),\n    .wr_ack(),\n    .wr_data_count(),\n    .wr_rst(1'b0),\n    .wr_rst_busy(),\n    .rd_rst_busy(),\n    .sleep(1'b0)\n  );\n\nendmodule\n\n\n\n// -- (c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n// Structure:\n//   axic_srl_fifo\n//     ndeep_srl\n//       nto1_mux\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_21_axic_srl_fifo #\n  (\n   parameter         C_FAMILY   = \"none\", // FPGA Family\n   parameter integer C_FIFO_WIDTH  = 1, // Width of S_MESG/M_MESG.\n   parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits\n                                             // the control logic can be used\n                                             // on before the control logic\n                                             // needs to be replicated.\n   parameter integer C_FIFO_DEPTH_LOG =  2,  // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.  \n                                             // The minimum size fifo generated is 4-deep.\n   parameter         C_USE_FULL =  1         // Prevent overwrite by throttling S_READY.                                              \n   )\n  (\n   input  wire                        ACLK,    // Clock\n   input  wire                        ARESET,  // Reset\n   input  wire [C_FIFO_WIDTH-1:0]     S_MESG,  // Input data\n   input  wire                        S_VALID, // Input data valid\n   output wire                        S_READY, // Input data ready\n   output wire [C_FIFO_WIDTH-1:0]     M_MESG,  // Output data\n   output wire                        M_VALID, // Output data valid\n   input  wire                        M_READY  // Output data ready\n   );\n  \n  localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;\n  localparam P_EMPTY       = {P_FIFO_DEPTH_LOG{1'b1}};\n  localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};\n  localparam P_ALMOSTFULL_TEMP  = {P_EMPTY, 1'b0};\n  localparam P_ALMOSTFULL  = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];\n  localparam P_NUM_REPS    = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?\n                             (C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :\n                             ((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;\n\n  (* syn_keep = \"1\" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0]  fifoaddr;\n  (* syn_keep = \"1\" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;\n\n  genvar i;\n  genvar j;\n\n  reg  M_VALID_i;\n  reg  S_READY_i;\n  wire push;     // FIFO push\n  wire pop;      // FIFO pop\n  reg  areset_d1; // Reset delay register\n  wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data\n\n  assign M_VALID = M_VALID_i;\n  assign S_READY = C_USE_FULL ? S_READY_i : 1'b1;\n  assign M_MESG = m_axi_mesg_i;\n  assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1'b1);\n  assign pop  = M_VALID_i & M_READY;\n  \n  always @(posedge ACLK) begin\n    areset_d1 <= ARESET;\n  end\n      \n  generate\n    //---------------------------------------------------------------------------\n    // Create count of number of elements in FIFOs\n    //---------------------------------------------------------------------------\n    for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep\n      assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] = \n         push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :\n                fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;\n      always @(posedge ACLK) begin\n        if (ARESET)\n          fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= \n                {P_FIFO_DEPTH_LOG{1'b1}};\n        else if (push ^ pop)\n          fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= \n                fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];\n      end\n    end\n\n    //---------------------------------------------------------------------------\n    // When FIFO is empty, reset master valid bit.  When not empty set valid bit.\n    // When FIFO is full,  reset slave  ready bit.  When not full  set ready bit.\n    //---------------------------------------------------------------------------\n    \n    always @(posedge ACLK) begin\n      if (ARESET) begin\n        M_VALID_i <= 1'b0;\n      end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == \n                               P_ALMOSTEMPTY) && pop && ~push) begin\n        M_VALID_i <= 1'b0;\n      end else if (push) begin\n        M_VALID_i <= 1'b1;\n      end\n    end\n      \n    always @(posedge ACLK) begin\n      if (ARESET) begin\n        S_READY_i <= 1'b0;\n      end else if (areset_d1) begin\n        S_READY_i <= 1'b1;\n      end else if (C_USE_FULL && \n        ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == \n         P_ALMOSTFULL) && push && ~pop)) begin\n        S_READY_i <= 1'b0;\n      end else if (C_USE_FULL && pop) begin\n        S_READY_i <= 1'b1;\n      end\n    end\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls\n      for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep\n        axi_data_fifo_v2_1_21_ndeep_srl #\n          (\n           .C_FAMILY  (C_FAMILY),\n           .C_A_WIDTH (P_FIFO_DEPTH_LOG)\n          )\n          srl_nx1\n          (\n           .CLK (ACLK),\n           .A   (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:\n                          P_FIFO_DEPTH_LOG*(i)]),\n           .CE  (push),\n           .D   (S_MESG[i*C_MAX_CTRL_FANOUT+j]),\n           .Q   (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j])\n          );\n      end\n    end      \n  endgenerate\n  \nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.\n//   Interface outputs are synchronized using ordinary flops for improved timing.\n//--------------------------------------------------------------------------\n// Structure:\n//   axic_reg_srl_fifo\n//     ndeep_srl\n//       nto1_mux\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_21_axic_reg_srl_fifo #\n  (\n   parameter         C_FAMILY   = \"none\", // FPGA Family\n   parameter integer C_FIFO_WIDTH  = 1, // Width of S_MESG/M_MESG.\n   parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits\n                                             // the control logic can be used\n                                             // on before the control logic\n                                             // needs to be replicated.\n   parameter integer C_FIFO_DEPTH_LOG =  2,  // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.  \n                                             // The minimum size fifo generated is 4-deep.\n   parameter         C_USE_FULL =  1         // Prevent overwrite by throttling S_READY.                                              \n   )\n  (\n   input  wire                        ACLK,    // Clock\n   input  wire                        ARESET,  // Reset\n   input  wire [C_FIFO_WIDTH-1:0]     S_MESG,  // Input data\n   input  wire                        S_VALID, // Input data valid\n   output wire                        S_READY, // Input data ready\n   output wire [C_FIFO_WIDTH-1:0]     M_MESG,  // Output data\n   output wire                        M_VALID, // Output data valid\n   input  wire                        M_READY  // Output data ready\n   );\n  \n  localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;\n  localparam P_EMPTY       = {P_FIFO_DEPTH_LOG{1'b1}};\n  localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};\n  localparam P_ALMOSTFULL_TEMP  = {P_EMPTY, 1'b0};\n  localparam P_ALMOSTFULL  = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];\n  localparam P_NUM_REPS    = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?\n                             (C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :\n                             ((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;\n\n  (* syn_keep = \"1\" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0]  fifoaddr;\n  (* syn_keep = \"1\" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;\n\n  genvar i;\n  genvar j;\n\n  \n  reg  m_valid_i = 1'b0;\n  reg  s_ready_i;\n  wire push;     // FIFO push\n  wire pop;      // FIFO pop\n  reg  areset_d1; // Reset delay register\n  reg  [C_FIFO_WIDTH-1:0] storage_data1;\n  wire [C_FIFO_WIDTH-1:0] storage_data2; // Intermediate SRL data\n  reg                    load_s1;\n  wire                   load_s1_from_s2;\n\n  reg [1:0] state;\n  localparam [1:0] \n    ZERO = 2'b10,\n    ONE  = 2'b11,\n    TWO  = 2'b01;\n      \n  assign M_VALID = m_valid_i;\n  assign S_READY = C_USE_FULL ? s_ready_i : 1'b1;\n  assign push = (S_VALID & (C_USE_FULL ? s_ready_i : 1'b1) & (state == TWO)) | (~M_READY & S_VALID & (state == ONE));\n  assign pop  = M_READY & (state == TWO);\n  assign M_MESG = storage_data1;\n  \n  always @(posedge ACLK) begin\n    areset_d1 <= ARESET;\n  end\n      \n  // Load storage1 with either slave side data or from storage2\n  always @(posedge ACLK) \n  begin\n    if (load_s1)\n      if (load_s1_from_s2)\n        storage_data1 <= storage_data2;\n      else\n        storage_data1 <= S_MESG;        \n  end\n\n  // Loading s1\n  always @ *\n  begin\n    if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction\n         // Load when ONE if we both have read and write at the same time\n         ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||\n         // Load when TWO and we have a transaction on Master side\n         ((state == TWO) && (M_READY == 1)))\n      load_s1 = 1'b1;\n    else\n      load_s1 = 1'b0;\n  end // always @ *\n\n  assign load_s1_from_s2 = (state == TWO);\n                   \n  // State Machine for handling output signals\n  always @(posedge ACLK) \n  begin\n    if (areset_d1) begin\n      state <= ZERO;\n      m_valid_i <= 1'b0;\n    end else begin\n      case (state)\n        // No transaction stored locally\n        ZERO: begin\n          if (S_VALID) begin\n            state <= ONE; // Got one so move to ONE\n            m_valid_i <= 1'b1;\n          end\n        end\n\n        // One transaction stored locally\n        ONE: begin\n          if (M_READY & ~S_VALID) begin\n            state <= ZERO; // Read out one so move to ZERO\n            m_valid_i <= 1'b0;\n          end else if (~M_READY & S_VALID) begin\n            state <= TWO;  // Got another one so move to TWO\n            m_valid_i <= 1'b1;\n          end\n        end\n\n        // TWO transaction stored locally\n        TWO: begin\n          if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == \n                 P_ALMOSTEMPTY) && pop && ~push) begin\n            state <= ONE; // Read out one so move to ONE\n            m_valid_i <= 1'b1;\n          end\n        end\n      endcase // case (state)\n    end\n  end // always @ (posedge ACLK)\n      \n  generate\n    //---------------------------------------------------------------------------\n    // Create count of number of elements in FIFOs\n    //---------------------------------------------------------------------------\n    for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep\n      assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] = \n         push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :\n                fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;\n      always @(posedge ACLK) begin\n        if (ARESET)\n          fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= \n                {P_FIFO_DEPTH_LOG{1'b1}};\n        else if (push ^ pop)\n          fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= \n                fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (ARESET) begin\n        s_ready_i <= 1'b0;\n      end else if (areset_d1) begin\n        s_ready_i <= 1'b1;\n      end else if (C_USE_FULL && \n        ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == \n         P_ALMOSTFULL) && push && ~pop)) begin\n        s_ready_i <= 1'b0;\n      end else if (C_USE_FULL && pop) begin\n        s_ready_i <= 1'b1;\n      end\n    end\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls\n      for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep\n        axi_data_fifo_v2_1_21_ndeep_srl #\n          (\n           .C_FAMILY  (C_FAMILY),\n           .C_A_WIDTH (P_FIFO_DEPTH_LOG)\n          )\n          srl_nx1\n          (\n           .CLK (ACLK),\n           .A   (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:\n                          P_FIFO_DEPTH_LOG*(i)]),\n           .CE  (push),\n           .D   (S_MESG[i*C_MAX_CTRL_FANOUT+j]),\n           .Q   (storage_data2[i*C_MAX_CTRL_FANOUT+j])\n          );\n      end\n    end      \n  endgenerate\n  \nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: This is a generic n-deep SRL instantiation\n// Verilog-standard:  Verilog 2001\n// $Revision: \n// $Date: \n//\n//-----------------------------------------------------------------------------\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_21_ndeep_srl #\n  (\n   parameter         C_FAMILY  = \"rtl\", // FPGA Family\n   parameter         C_A_WIDTH = 1          // Address Width (>= 1)\n   )\n  (\n   input  wire                 CLK, // Clock\n   input  wire [C_A_WIDTH-1:0] A,   // Address\n   input  wire                 CE,  // Clock Enable\n   input  wire                 D,   // Input Data\n   output wire                 Q    // Output Data\n   );\n\n  localparam integer P_SRLASIZE = 5;\n  localparam integer P_SRLDEPTH = 32;\n  localparam integer P_NUMSRLS  = (C_A_WIDTH>P_SRLASIZE) ? (2**(C_A_WIDTH-P_SRLASIZE)) : 1;\n  localparam integer P_SHIFT_DEPTH  = 2**C_A_WIDTH;\n  \n  wire [P_NUMSRLS:0]   d_i;\n  wire [P_NUMSRLS-1:0] q_i;\n  wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i;\n  \n  genvar i;\n  \n  // Instantiate SRLs in carry chain format\n  assign d_i[0] = D;\n  assign a_i = A;\n  \n  generate\n\t\t\t\t\t\n    if (C_FAMILY == \"rtl\") begin : gen_rtl_shifter\n      if (C_A_WIDTH <= P_SRLASIZE) begin : gen_inferred_srl\n        reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n        always @(posedge CLK)\n          if (CE)\n            shift_reg <= {shift_reg[P_SRLDEPTH-2:0], D};\n        assign Q = shift_reg[a_i];\n      end else begin : gen_logic_shifter  // Very wasteful\n        reg [P_SHIFT_DEPTH-1:0] shift_reg = {P_SHIFT_DEPTH{1'b0}};\n        always @(posedge CLK)\n          if (CE)\n            shift_reg <= {shift_reg[P_SHIFT_DEPTH-2:0], D};\n        assign Q = shift_reg[a_i];\n      end\n    end else begin : gen_primitive_shifter\n      for (i=0;i<P_NUMSRLS;i=i+1) begin : gen_srls\n        SRLC32E\n          srl_inst\n            (\n             .CLK (CLK),\n             .A   (a_i[P_SRLASIZE-1:0]),\n             .CE  (CE),\n             .D   (d_i[i]),\n             .Q   (q_i[i]),\n             .Q31 (d_i[i+1])\n             );\n      end\n      \n      if (C_A_WIDTH>P_SRLASIZE) begin : gen_srl_mux\n        generic_baseblocks_v2_1_0_nto1_mux #\n        (\n          .C_RATIO         (2**(C_A_WIDTH-P_SRLASIZE)),\n          .C_SEL_WIDTH     (C_A_WIDTH-P_SRLASIZE),\n          .C_DATAOUT_WIDTH (1),\n          .C_ONEHOT        (0)\n        )\n        srl_q_mux_inst\n        (\n          .SEL_ONEHOT ({2**(C_A_WIDTH-P_SRLASIZE){1'b0}}),\n          .SEL        (a_i[C_A_WIDTH-1:P_SRLASIZE]),\n          .IN         (q_i),\n          .OUT        (Q)\n        );\n      end else begin : gen_no_srl_mux\n        assign Q = q_i[0];\n      end\n    end\n  endgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// AXI data fifo module:    \n//   5-channel memory-mapped AXI4 interfaces.\n//   SRL or BRAM based FIFO on AXI W and/or R channels.\n//   FIFO to accommodate various data flow rates through the AXI interconnect\n//\n// Verilog-standard:  Verilog 2001\n//-----------------------------------------------------------------------------\n//\n// Structure:\n//   axi_data_fifo\n//     fifo_generator\n//\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_data_fifo_v2_1_21_axi_data_fifo #\n  (\n   parameter         C_FAMILY                    = \"virtex7\",\n   parameter integer C_AXI_PROTOCOL              = 0,\n   parameter integer C_AXI_ID_WIDTH              = 4,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   parameter integer C_AXI_WRITE_FIFO_DEPTH      = 0,      // Range: (0, 32, 512)\n   parameter         C_AXI_WRITE_FIFO_TYPE       = \"lut\",  // \"lut\" = LUT (SRL) based,\n                                                           // \"bram\" = BRAM based\n   parameter integer C_AXI_WRITE_FIFO_DELAY      = 0,      // 0 = No, 1 = Yes\n                       // Indicates whether AWVALID and WVALID assertion is delayed until:\n                       //   a. the corresponding WLAST is stored in the FIFO, or\n                       //   b. no WLAST is stored and the FIFO is full.\n                       // 0 means AW channel is pass-through and \n                       //   WVALID is asserted whenever FIFO is not empty.\n   parameter integer C_AXI_READ_FIFO_DEPTH       = 0,      // Range: (0, 32, 512)\n   parameter         C_AXI_READ_FIFO_TYPE        = \"lut\",  // \"lut\" = LUT (SRL) based,\n                                                           // \"bram\" = BRAM based\n   parameter integer C_AXI_READ_FIFO_DELAY       = 0)      // 0 = No, 1 = Yes\n                       // Indicates whether ARVALID assertion is delayed until the \n                       //   the remaining vacancy of the FIFO is at least the burst length\n                       //   as indicated by ARLEN.\n                       // 0 means AR channel is pass-through.\n   // System Signals\n  (input wire aclk,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     s_axi_bid,\n   output wire [2-1:0]                  s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0]  s_axi_buser,\n   output wire                          s_axi_bvalid,\n   input  wire                          s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   s_axi_rdata,\n   output wire [2-1:0]                  s_axi_rresp,\n   output wire                          s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0]  s_axi_ruser,\n   output wire                          s_axi_rvalid,\n   input  wire                          s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     m_axi_bid,\n   input  wire [2-1:0]                  m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0]  m_axi_buser,\n   input  wire                          m_axi_bvalid,\n   output wire                          m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   m_axi_rdata,\n   input  wire [2-1:0]                  m_axi_rresp,\n   input  wire                          m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0]  m_axi_ruser,\n   input  wire                          m_axi_rvalid,\n   output wire                          m_axi_rready);\n  \n  localparam integer P_WIDTH_RACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_ARUSER_WIDTH;\n  localparam integer P_WIDTH_WACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_AWUSER_WIDTH;\n  localparam integer P_WIDTH_RDCH = 1 + 2 + C_AXI_DATA_WIDTH + C_AXI_ID_WIDTH + C_AXI_RUSER_WIDTH;\n  localparam integer P_WIDTH_WDCH = 1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+((C_AXI_PROTOCOL==1)?C_AXI_ID_WIDTH:0)+C_AXI_WUSER_WIDTH;\n  localparam integer P_WIDTH_WRCH = 2 + C_AXI_ID_WIDTH + C_AXI_BUSER_WIDTH;\n  \n  localparam         P_PRIM_FIFO_TYPE = \"512x72\" ;\n  localparam integer P_AXI4 = 0;\n  localparam integer P_AXI3 = 1;\n  localparam integer P_AXILITE = 2;\n  localparam integer P_WRITE_FIFO_DEPTH_LOG = (C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1;\n  localparam integer P_READ_FIFO_DEPTH_LOG = (C_AXI_READ_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1;\n  \n  // Ceiling of log2(x)\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  generate\n    if (((C_AXI_WRITE_FIFO_DEPTH == 0) && (C_AXI_READ_FIFO_DEPTH == 0)) || (C_AXI_PROTOCOL == P_AXILITE)) begin : gen_bypass\n      assign m_axi_awid     = s_axi_awid;\n      assign m_axi_awaddr   = s_axi_awaddr;\n      assign m_axi_awlen    = s_axi_awlen;\n      assign m_axi_awsize   = s_axi_awsize;\n      assign m_axi_awburst  = s_axi_awburst;\n      assign m_axi_awlock   = s_axi_awlock;\n      assign m_axi_awcache  = s_axi_awcache;\n      assign m_axi_awprot   = s_axi_awprot;\n      assign m_axi_awregion = s_axi_awregion;\n      assign m_axi_awqos    = s_axi_awqos;\n      assign m_axi_awuser   = s_axi_awuser;\n      assign m_axi_awvalid  = s_axi_awvalid;\n      assign s_axi_awready  = m_axi_awready;\n      \n      assign m_axi_wid      = s_axi_wid;\n      assign m_axi_wdata    = s_axi_wdata;\n      assign m_axi_wstrb    = s_axi_wstrb;\n      assign m_axi_wlast    = s_axi_wlast;\n      assign m_axi_wuser    = s_axi_wuser;\n      assign m_axi_wvalid   = s_axi_wvalid;\n      assign s_axi_wready   = m_axi_wready;\n    \n      assign s_axi_bid      = m_axi_bid;\n      assign s_axi_bresp    = m_axi_bresp;\n      assign s_axi_buser    = m_axi_buser;\n      assign s_axi_bvalid   = m_axi_bvalid;\n      assign m_axi_bready   = s_axi_bready;\n    \n      assign m_axi_arid     = s_axi_arid;\n      assign m_axi_araddr   = s_axi_araddr;\n      assign m_axi_arlen    = s_axi_arlen;\n      assign m_axi_arsize   = s_axi_arsize;\n      assign m_axi_arburst  = s_axi_arburst;\n      assign m_axi_arlock   = s_axi_arlock;\n      assign m_axi_arcache  = s_axi_arcache;\n      assign m_axi_arprot   = s_axi_arprot;\n      assign m_axi_arregion = s_axi_arregion;\n      assign m_axi_arqos    = s_axi_arqos;\n      assign m_axi_aruser   = s_axi_aruser;\n      assign m_axi_arvalid  = s_axi_arvalid;\n      assign s_axi_arready  = m_axi_arready;\n  \n      assign s_axi_rid      = m_axi_rid;\n      assign s_axi_rdata    = m_axi_rdata;\n      assign s_axi_rresp    = m_axi_rresp;\n      assign s_axi_rlast    = m_axi_rlast;\n      assign s_axi_ruser    = m_axi_ruser;\n      assign s_axi_rvalid   = m_axi_rvalid;\n      assign m_axi_rready   = s_axi_rready;\n      \n    end else begin : gen_fifo\n      \n      wire [4-1:0]                  s_axi_awregion_i;\n      wire [4-1:0]                  s_axi_arregion_i;\n      wire [4-1:0]                  m_axi_awregion_i;\n      wire [4-1:0]                  m_axi_arregion_i;\n      wire [C_AXI_ID_WIDTH-1:0]     s_axi_wid_i;\n      wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid_i;\n      \n      assign s_axi_awregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : s_axi_awregion;\n      assign s_axi_arregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : s_axi_arregion;\n      assign m_axi_awregion = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : m_axi_awregion_i;\n      assign m_axi_arregion = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : m_axi_arregion_i;\n      assign s_axi_wid_i = (C_AXI_PROTOCOL == P_AXI3) ? s_axi_wid : {C_AXI_ID_WIDTH{1'b0}};\n      assign m_axi_wid = (C_AXI_PROTOCOL == P_AXI3) ? m_axi_wid_i : {C_AXI_ID_WIDTH{1'b0}};\n\n\n      fifo_generator_v13_2_5 #(\n          .C_EN_SAFETY_CKT(0),\n          .C_SELECT_XPM(0),\n          .C_INTERFACE_TYPE(2),\n          .C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : 3),\n          .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n          .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n          .C_HAS_AXI_ID(1),\n          .C_AXI_LEN_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 8 : 4),\n          .C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 1 : 2),\n          .C_HAS_AXI_ARUSER(1),\n          .C_HAS_AXI_AWUSER(1),\n          .C_HAS_AXI_BUSER(1),\n          .C_HAS_AXI_RUSER(1),\n          .C_HAS_AXI_WUSER(1),\n          .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n          .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n          .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n          .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),\n          .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n          .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n          .C_DIN_WIDTH_RACH(P_WIDTH_RACH),\n          .C_DIN_WIDTH_RDCH(P_WIDTH_RDCH),\n          .C_DIN_WIDTH_WACH(P_WIDTH_WACH),\n          .C_DIN_WIDTH_WDCH(P_WIDTH_WDCH),\n          .C_DIN_WIDTH_WRCH(P_WIDTH_WDCH),\n          .C_RACH_TYPE(((C_AXI_READ_FIFO_DEPTH != 0) && C_AXI_READ_FIFO_DELAY) ? 0 : 2),\n          .C_WACH_TYPE(((C_AXI_WRITE_FIFO_DEPTH != 0) && C_AXI_WRITE_FIFO_DELAY) ? 0 : 2),\n          .C_WDCH_TYPE((C_AXI_WRITE_FIFO_DEPTH != 0) ? 0 : 2),\n          .C_RDCH_TYPE((C_AXI_READ_FIFO_DEPTH != 0) ? 0 : 2),\n          .C_WRCH_TYPE(2),\n          .C_COMMON_CLOCK(1),\n          .C_ADD_NGC_CONSTRAINT(0),\n          .C_APPLICATION_TYPE_AXIS(0),\n          .C_APPLICATION_TYPE_RACH(C_AXI_READ_FIFO_DELAY ? 1 : 0),\n          .C_APPLICATION_TYPE_RDCH(0),\n          .C_APPLICATION_TYPE_WACH(C_AXI_WRITE_FIFO_DELAY ? 1 : 0),\n          .C_APPLICATION_TYPE_WDCH(0),\n          .C_APPLICATION_TYPE_WRCH(0),\n          .C_AXIS_TDATA_WIDTH(64),\n          .C_AXIS_TDEST_WIDTH(4),\n          .C_AXIS_TID_WIDTH(8),\n          .C_AXIS_TKEEP_WIDTH(4),\n          .C_AXIS_TSTRB_WIDTH(4),\n          .C_AXIS_TUSER_WIDTH(4),\n          .C_AXIS_TYPE(0),\n          .C_COUNT_TYPE(0),\n          .C_DATA_COUNT_WIDTH(10),\n          .C_DEFAULT_VALUE(\"BlankString\"),\n          .C_DIN_WIDTH(18),\n          .C_DIN_WIDTH_AXIS(1),\n          .C_DOUT_RST_VAL(\"0\"),\n          .C_DOUT_WIDTH(18),\n          .C_ENABLE_RLOCS(0),\n          .C_ENABLE_RST_SYNC(1),\n          .C_ERROR_INJECTION_TYPE(0),\n          .C_ERROR_INJECTION_TYPE_AXIS(0),\n          .C_ERROR_INJECTION_TYPE_RACH(0),\n          .C_ERROR_INJECTION_TYPE_RDCH(0),\n          .C_ERROR_INJECTION_TYPE_WACH(0),\n          .C_ERROR_INJECTION_TYPE_WDCH(0),\n          .C_ERROR_INJECTION_TYPE_WRCH(0),\n          .C_FAMILY(C_FAMILY),\n          .C_FULL_FLAGS_RST_VAL(1),\n          .C_HAS_ALMOST_EMPTY(0),\n          .C_HAS_ALMOST_FULL(0),\n          .C_HAS_AXI_RD_CHANNEL(1),\n          .C_HAS_AXI_WR_CHANNEL(1),\n          .C_HAS_AXIS_TDATA(0),\n          .C_HAS_AXIS_TDEST(0),\n          .C_HAS_AXIS_TID(0),\n          .C_HAS_AXIS_TKEEP(0),\n          .C_HAS_AXIS_TLAST(0),\n          .C_HAS_AXIS_TREADY(1),\n          .C_HAS_AXIS_TSTRB(0),\n          .C_HAS_AXIS_TUSER(0),\n          .C_HAS_BACKUP(0),\n          .C_HAS_DATA_COUNT(0),\n          .C_HAS_DATA_COUNTS_AXIS(0),\n          .C_HAS_DATA_COUNTS_RACH(0),\n          .C_HAS_DATA_COUNTS_RDCH(0),\n          .C_HAS_DATA_COUNTS_WACH(0),\n          .C_HAS_DATA_COUNTS_WDCH(0),\n          .C_HAS_DATA_COUNTS_WRCH(0),\n          .C_HAS_INT_CLK(0),\n          .C_HAS_MASTER_CE(0),\n          .C_HAS_MEMINIT_FILE(0),\n          .C_HAS_OVERFLOW(0),\n          .C_HAS_PROG_FLAGS_AXIS(0),\n          .C_HAS_PROG_FLAGS_RACH(0),\n          .C_HAS_PROG_FLAGS_RDCH(0),\n          .C_HAS_PROG_FLAGS_WACH(0),\n          .C_HAS_PROG_FLAGS_WDCH(0),\n          .C_HAS_PROG_FLAGS_WRCH(0),\n          .C_HAS_RD_DATA_COUNT(0),\n          .C_HAS_RD_RST(0),\n          .C_HAS_RST(1),\n          .C_HAS_SLAVE_CE(0),\n          .C_HAS_SRST(0),\n          .C_HAS_UNDERFLOW(0),\n          .C_HAS_VALID(0),\n          .C_HAS_WR_ACK(0),\n          .C_HAS_WR_DATA_COUNT(0),\n          .C_HAS_WR_RST(0),\n          .C_IMPLEMENTATION_TYPE(0),\n          .C_IMPLEMENTATION_TYPE_AXIS(1),\n          .C_IMPLEMENTATION_TYPE_RACH(2),\n          .C_IMPLEMENTATION_TYPE_RDCH((C_AXI_READ_FIFO_TYPE == \"bram\") ? 1 : 2),\n          .C_IMPLEMENTATION_TYPE_WACH(2),\n          .C_IMPLEMENTATION_TYPE_WDCH((C_AXI_WRITE_FIFO_TYPE == \"bram\") ? 1 : 2),\n          .C_IMPLEMENTATION_TYPE_WRCH(2),\n          .C_INIT_WR_PNTR_VAL(0),\n          .C_MEMORY_TYPE(1),\n          .C_MIF_FILE_NAME(\"BlankString\"),\n          .C_MSGON_VAL(1),\n          .C_OPTIMIZATION_MODE(0),\n          .C_OVERFLOW_LOW(0),\n          .C_PRELOAD_LATENCY(1),\n          .C_PRELOAD_REGS(0),\n          .C_PRIM_FIFO_TYPE(P_PRIM_FIFO_TYPE),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(30),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(510),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(30),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(510),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(14),\n          .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),\n          .C_PROG_EMPTY_TYPE(0),\n          .C_PROG_EMPTY_TYPE_AXIS(5),\n          .C_PROG_EMPTY_TYPE_RACH(5),\n          .C_PROG_EMPTY_TYPE_RDCH(5),\n          .C_PROG_EMPTY_TYPE_WACH(5),\n          .C_PROG_EMPTY_TYPE_WDCH(5),\n          .C_PROG_EMPTY_TYPE_WRCH(5),\n          .C_PROG_FULL_THRESH_ASSERT_VAL(1022),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(31),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(511),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(31),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(511),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),\n          .C_PROG_FULL_THRESH_NEGATE_VAL(1021),\n          .C_PROG_FULL_TYPE(0),\n          .C_PROG_FULL_TYPE_AXIS(5),\n          .C_PROG_FULL_TYPE_RACH(5),\n          .C_PROG_FULL_TYPE_RDCH(5),\n          .C_PROG_FULL_TYPE_WACH(5),\n          .C_PROG_FULL_TYPE_WDCH(5),\n          .C_PROG_FULL_TYPE_WRCH(5),\n          .C_RD_DATA_COUNT_WIDTH(10),\n          .C_RD_DEPTH(1024),\n          .C_RD_FREQ(1),\n          .C_RD_PNTR_WIDTH(10),\n          .C_REG_SLICE_MODE_AXIS(0),\n          .C_REG_SLICE_MODE_RACH(0),\n          .C_REG_SLICE_MODE_RDCH(0),\n          .C_REG_SLICE_MODE_WACH(0),\n          .C_REG_SLICE_MODE_WDCH(0),\n          .C_REG_SLICE_MODE_WRCH(0),\n          .C_UNDERFLOW_LOW(0),\n          .C_USE_COMMON_OVERFLOW(0),\n          .C_USE_COMMON_UNDERFLOW(0),\n          .C_USE_DEFAULT_SETTINGS(0),\n          .C_USE_DOUT_RST(1),\n          .C_USE_ECC(0),\n          .C_USE_ECC_AXIS(0),\n          .C_USE_ECC_RACH(0),\n          .C_USE_ECC_RDCH(0),\n          .C_USE_ECC_WACH(0),\n          .C_USE_ECC_WDCH(0),\n          .C_USE_ECC_WRCH(0),\n          .C_USE_EMBEDDED_REG(0),\n          .C_USE_FIFO16_FLAGS(0),\n          .C_USE_FWFT_DATA_COUNT(0),\n          .C_VALID_LOW(0),\n          .C_WR_ACK_LOW(0),\n          .C_WR_DATA_COUNT_WIDTH(10),\n          .C_WR_DEPTH(1024),\n          .C_WR_DEPTH_AXIS(1024),\n          .C_WR_DEPTH_RACH(32),\n          .C_WR_DEPTH_RDCH(C_AXI_READ_FIFO_DEPTH),\n          .C_WR_DEPTH_WACH(32),\n          .C_WR_DEPTH_WDCH(C_AXI_WRITE_FIFO_DEPTH),\n          .C_WR_DEPTH_WRCH(16),\n          .C_WR_FREQ(1),\n          .C_WR_PNTR_WIDTH(10),\n          .C_WR_PNTR_WIDTH_AXIS(10),\n          .C_WR_PNTR_WIDTH_RACH(5),\n          .C_WR_PNTR_WIDTH_RDCH((C_AXI_READ_FIFO_DEPTH> 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1),\n          .C_WR_PNTR_WIDTH_WACH(5),\n          .C_WR_PNTR_WIDTH_WDCH((C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1),\n          .C_WR_PNTR_WIDTH_WRCH(4),\n          .C_WR_RESPONSE_LATENCY(1)\n        )\n        fifo_gen_inst (\n          .s_aclk(aclk),\n          .s_aresetn(aresetn),\n          .s_axi_awid(s_axi_awid),\n          .s_axi_awaddr(s_axi_awaddr),\n          .s_axi_awlen(s_axi_awlen),\n          .s_axi_awsize(s_axi_awsize),\n          .s_axi_awburst(s_axi_awburst),\n          .s_axi_awlock(s_axi_awlock),\n          .s_axi_awcache(s_axi_awcache),\n          .s_axi_awprot(s_axi_awprot),\n          .s_axi_awqos(s_axi_awqos),\n          .s_axi_awregion(s_axi_awregion_i),\n          .s_axi_awuser(s_axi_awuser),\n          .s_axi_awvalid(s_axi_awvalid),\n          .s_axi_awready(s_axi_awready),\n          .s_axi_wid(s_axi_wid_i),\n          .s_axi_wdata(s_axi_wdata),\n          .s_axi_wstrb(s_axi_wstrb),\n          .s_axi_wlast(s_axi_wlast),\n          .s_axi_wvalid(s_axi_wvalid),\n          .s_axi_wready(s_axi_wready),\n          .s_axi_bid(s_axi_bid),\n          .s_axi_bresp(s_axi_bresp),\n          .s_axi_bvalid(s_axi_bvalid),\n          .s_axi_bready(s_axi_bready),\n          .m_axi_awid(m_axi_awid),\n          .m_axi_awaddr(m_axi_awaddr),\n          .m_axi_awlen(m_axi_awlen),\n          .m_axi_awsize(m_axi_awsize),\n          .m_axi_awburst(m_axi_awburst),\n          .m_axi_awlock(m_axi_awlock),\n          .m_axi_awcache(m_axi_awcache),\n          .m_axi_awprot(m_axi_awprot),\n          .m_axi_awqos(m_axi_awqos),\n          .m_axi_awregion(m_axi_awregion_i),\n          .m_axi_awuser(m_axi_awuser),\n          .m_axi_awvalid(m_axi_awvalid),\n          .m_axi_awready(m_axi_awready),\n          .m_axi_wid(m_axi_wid_i),\n          .m_axi_wdata(m_axi_wdata),\n          .m_axi_wstrb(m_axi_wstrb),\n          .m_axi_wlast(m_axi_wlast),\n          .m_axi_wvalid(m_axi_wvalid),\n          .m_axi_wready(m_axi_wready),\n          .m_axi_bid(m_axi_bid),\n          .m_axi_bresp(m_axi_bresp),\n          .m_axi_bvalid(m_axi_bvalid),\n          .m_axi_bready(m_axi_bready),\n          .s_axi_arid(s_axi_arid),\n          .s_axi_araddr(s_axi_araddr),\n          .s_axi_arlen(s_axi_arlen),\n          .s_axi_arsize(s_axi_arsize),\n          .s_axi_arburst(s_axi_arburst),\n          .s_axi_arlock(s_axi_arlock),\n          .s_axi_arcache(s_axi_arcache),\n          .s_axi_arprot(s_axi_arprot),\n          .s_axi_arqos(s_axi_arqos),\n          .s_axi_arregion(s_axi_arregion_i),\n          .s_axi_arvalid(s_axi_arvalid),\n          .s_axi_arready(s_axi_arready),\n          .s_axi_rid(s_axi_rid),\n          .s_axi_rdata(s_axi_rdata),\n          .s_axi_rresp(s_axi_rresp),\n          .s_axi_rlast(s_axi_rlast),\n          .s_axi_rvalid(s_axi_rvalid),\n          .s_axi_rready(s_axi_rready),\n          .m_axi_arid(m_axi_arid),\n          .m_axi_araddr(m_axi_araddr),\n          .m_axi_arlen(m_axi_arlen),\n          .m_axi_arsize(m_axi_arsize),\n          .m_axi_arburst(m_axi_arburst),\n          .m_axi_arlock(m_axi_arlock),\n          .m_axi_arcache(m_axi_arcache),\n          .m_axi_arprot(m_axi_arprot),\n          .m_axi_arqos(m_axi_arqos),\n          .m_axi_arregion(m_axi_arregion_i),\n          .m_axi_arvalid(m_axi_arvalid),\n          .m_axi_arready(m_axi_arready),\n          .m_axi_rid(m_axi_rid),\n          .m_axi_rdata(m_axi_rdata),\n          .m_axi_rresp(m_axi_rresp),\n          .m_axi_rlast(m_axi_rlast),\n          .m_axi_rvalid(m_axi_rvalid),\n          .m_axi_rready(m_axi_rready),\n          .m_aclk(aclk),\n          .m_aclk_en(1'b1),\n          .s_aclk_en(1'b1),\n          .s_axi_wuser(s_axi_wuser),\n          .s_axi_buser(s_axi_buser),\n          .m_axi_wuser(m_axi_wuser),\n          .m_axi_buser(m_axi_buser),\n          .s_axi_aruser(s_axi_aruser),\n          .s_axi_ruser(s_axi_ruser),\n          .m_axi_aruser(m_axi_aruser),\n          .m_axi_ruser(m_axi_ruser),\n          .almost_empty(),\n          .almost_full(),\n          .axis_data_count(),\n          .axis_dbiterr(),\n          .axis_injectdbiterr(1'b0),\n          .axis_injectsbiterr(1'b0),\n          .axis_overflow(),\n          .axis_prog_empty(),\n          .axis_prog_empty_thresh(10'b0),\n          .axis_prog_full(),\n          .axis_prog_full_thresh(10'b0),\n          .axis_rd_data_count(),\n          .axis_sbiterr(),\n          .axis_underflow(),\n          .axis_wr_data_count(),\n          .axi_ar_data_count(),\n          .axi_ar_dbiterr(),\n          .axi_ar_injectdbiterr(1'b0),\n          .axi_ar_injectsbiterr(1'b0),\n          .axi_ar_overflow(),\n          .axi_ar_prog_empty(),\n          .axi_ar_prog_empty_thresh(5'b0),\n          .axi_ar_prog_full(),\n          .axi_ar_prog_full_thresh(5'b0),\n          .axi_ar_rd_data_count(),\n          .axi_ar_sbiterr(),\n          .axi_ar_underflow(),\n          .axi_ar_wr_data_count(),\n          .axi_aw_data_count(),\n          .axi_aw_dbiterr(),\n          .axi_aw_injectdbiterr(1'b0),\n          .axi_aw_injectsbiterr(1'b0),\n          .axi_aw_overflow(),\n          .axi_aw_prog_empty(),\n          .axi_aw_prog_empty_thresh(5'b0),\n          .axi_aw_prog_full(),\n          .axi_aw_prog_full_thresh(5'b0),\n          .axi_aw_rd_data_count(),\n          .axi_aw_sbiterr(),\n          .axi_aw_underflow(),\n          .axi_aw_wr_data_count(),\n          .axi_b_data_count(),\n          .axi_b_dbiterr(),\n          .axi_b_injectdbiterr(1'b0),\n          .axi_b_injectsbiterr(1'b0),\n          .axi_b_overflow(),\n          .axi_b_prog_empty(),\n          .axi_b_prog_empty_thresh(4'b0),\n          .axi_b_prog_full(),\n          .axi_b_prog_full_thresh(4'b0),\n          .axi_b_rd_data_count(),\n          .axi_b_sbiterr(),\n          .axi_b_underflow(),\n          .axi_b_wr_data_count(),\n          .axi_r_data_count(),\n          .axi_r_dbiterr(),\n          .axi_r_injectdbiterr(1'b0),\n          .axi_r_injectsbiterr(1'b0),\n          .axi_r_overflow(),\n          .axi_r_prog_empty(),\n          .axi_r_prog_empty_thresh({P_READ_FIFO_DEPTH_LOG{1'b0}}),\n          .axi_r_prog_full(),\n          .axi_r_prog_full_thresh({P_READ_FIFO_DEPTH_LOG{1'b0}}),\n          .axi_r_rd_data_count(),\n          .axi_r_sbiterr(),\n          .axi_r_underflow(),\n          .axi_r_wr_data_count(),\n          .axi_w_data_count(),\n          .axi_w_dbiterr(),\n          .axi_w_injectdbiterr(1'b0),\n          .axi_w_injectsbiterr(1'b0),\n          .axi_w_overflow(),\n          .axi_w_prog_empty(),\n          .axi_w_prog_empty_thresh({P_WRITE_FIFO_DEPTH_LOG{1'b0}}),\n          .axi_w_prog_full(),\n          .axi_w_prog_full_thresh({P_WRITE_FIFO_DEPTH_LOG{1'b0}}),\n          .axi_w_rd_data_count(),\n          .axi_w_sbiterr(),\n          .axi_w_underflow(),\n          .axi_w_wr_data_count(),\n          .backup(1'b0),\n          .backup_marker(1'b0),\n          .clk(1'b0),\n          .data_count(),\n          .dbiterr(),\n          .din(18'b0),\n          .dout(),\n          .empty(),\n          .full(),\n          .injectdbiterr(1'b0),\n          .injectsbiterr(1'b0),\n          .int_clk(1'b0),\n          .m_axis_tdata(),\n          .m_axis_tdest(),\n          .m_axis_tid(),\n          .m_axis_tkeep(),\n          .m_axis_tlast(),\n          .m_axis_tready(1'b0),\n          .m_axis_tstrb(),\n          .m_axis_tuser(),\n          .m_axis_tvalid(),\n          .overflow(),\n          .prog_empty(),\n          .prog_empty_thresh(10'b0),\n          .prog_empty_thresh_assert(10'b0),\n          .prog_empty_thresh_negate(10'b0),\n          .prog_full(),\n          .prog_full_thresh(10'b0),\n          .prog_full_thresh_assert(10'b0),\n          .prog_full_thresh_negate(10'b0),\n          .rd_clk(1'b0),\n          .rd_data_count(),\n          .rd_en(1'b0),\n          .rd_rst(1'b0),\n          .rst(1'b0),\n          .sbiterr(),\n          .srst(1'b0),\n          .s_axis_tdata(64'b0),\n          .s_axis_tdest(4'b0),\n          .s_axis_tid(8'b0),\n          .s_axis_tkeep(4'b0),\n          .s_axis_tlast(1'b0),\n          .s_axis_tready(),\n          .s_axis_tstrb(4'b0),\n          .s_axis_tuser(4'b0),\n          .s_axis_tvalid(1'b0),\n          .underflow(),\n          .valid(),\n          .wr_ack(),\n          .wr_clk(1'b0),\n          .wr_data_count(),\n          .wr_en(1'b0),\n          .wr_rst(1'b0),\n          .wr_rst_busy(),\n          .rd_rst_busy(),\n          .sleep(1'b0)\n        );\n    end\n  endgenerate\nendmodule\n\n\n\n", "num_lines": 1957}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_master #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_SUPPORTS_NARROW = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1,\n   parameter [C_AXI_ADDR_WIDTH-1:0] C_AXI_ADDR = 0,  // Base address\n   parameter integer C_NUM_ADDR = 1,  // Number of address iterations; range 1..2**16 (fixed increment = 32'h10000\n   parameter integer C_NUM_ID = 1,  // Number of ID iterations; range 1..2**C_ID_WIDTH (base = 0; fixed increment = 1)\n   parameter integer C_NUM_LEN = 1,  // Number of LEN iterations; range 1..9 (base = 0; value = 2**i - 1)\n   parameter integer C_NUM_TRANS = 1  // Number of transactions; range >=1 (read and write)\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_awvalid,\n  input  wire                            m_axi_awready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_awburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_awlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_awlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_awid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]    m_axi_awuser = 'b0,\n  /**************** Write Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_wid,\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]      m_axi_wdata,\n  (* dont_touch=\"true\" *) output reg [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb = {(C_AXI_DATA_WIDTH/8){1'b1}},\n  (* dont_touch=\"true\" *) output wire                             m_axi_wvalid,\n  input  wire                            m_axi_wready,\n  (* dont_touch=\"true\" *) output wire                             m_axi_wlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]     m_axi_wuser = 'b0,\n  /**************** Write Response Channel Signals ****************/\n  input  wire [2-1:0]                    m_axi_bresp,\n  input  wire                            m_axi_bvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_bready,\n  input  wire [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]     m_axi_buser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_bid,\n  /**************** Read Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_arvalid,\n  input  wire                            m_axi_arready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_arburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_arlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_arlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_arid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]    m_axi_aruser = 'b0,\n  /**************** Read Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]      m_axi_rdata,\n  input  wire [2-1:0]                    m_axi_rresp,\n  input  wire                            m_axi_rvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_rready,\n  input  wire                            m_axi_rlast,\n  input  wire [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]     m_axi_ruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_rid,\n  /**************** System Signals ****************/\n  input  wire                            aclk,\n  input  wire                            aresetn\n  );\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n  localparam integer  P_NUM_ID_LOG = f_ceil_log2(C_NUM_ID);\n  localparam integer  P_NUM_ADDR_LOG = f_ceil_log2(C_NUM_ADDR);\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL==0 ? 8 : C_AXI_PROTOCOL==1 ? 4 : 1);\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer               P_M_AXI_DATA_BYTES = (C_AXI_DATA_WIDTH / 8);\n  localparam integer               P_M_AXI_DONE_WIDTH = f_ceil_log2(C_NUM_TRANS<2?2:C_NUM_TRANS);\n  localparam integer               P_M_AXI_SIZE = f_ceil_log2(C_AXI_DATA_WIDTH)-3;\n\n  /**************** Internal Wires/Regs - Global ****************/\n   wire                            done;\n    wire                            dummy ;\n  reg                         done_i;\n  reg                         done_sel;\n  wire                         done_cycle;\n  reg                          done_d1 = 1'b0;\n  reg                   areset = 1'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] arcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] rcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [3:0]                    acc_r_i = 4'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] awcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] wcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] bcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [2:0]                    acc_b_i = 3'b0;\n\n  // Register Reset\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    \n    /**************** Internal Wires/Regs - Read Channels ****************/\n    wire                         read_xaction_done_i;\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_arid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_ADDR_WIDTH:0]      araddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  arprot_i = 3'b0;\n    reg [3-1:0]                  arsize_i = 3'b0;\n    reg [2-1:0]                  arburst_i = 2'b0;\n    reg [4-1:0]                  arcache_i = 4'b0;\n    reg [2-1:0]                  arlock_i = 2'b0;\n    reg [P_LEN_WIDTH-1:0]     arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [4-1:0]                  arqos_i = 4'b0;\n    reg [P_ID_WIDTH-1:0]        arid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [2-1:0]                  rresp_i = 2'b00;\n    reg [C_AXI_RUSER_WIDTH:0]   ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      rid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_arvalid_i = 1'b0;\n    reg                        m_axi_rready_i = 1'b0;\n    reg [P_NUM_ADDR_LOG:0]    araddr_cnt = 0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign read_xaction_done_i = m_axi_rvalid && m_axi_rready_i && ((C_AXI_PROTOCOL==2)?1'b1:m_axi_rlast);\n    assign m_axi_arvalid = m_axi_arvalid_i;\n    assign m_axi_rready = m_axi_rready_i;\n    assign m_axi_araddr = m_axi_araddr_i;\n    assign m_axi_arlen = m_axi_arlen_i;\n    always @(posedge aclk) begin\n      m_axi_arprot <= dummy ? arprot_i : 3'b000;\n      m_axi_arsize <= dummy ? arsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_arburst <= dummy ? arburst_i : 2'b01;\n      m_axi_arlock <= dummy ? arlock_i : 1'b0;\n      m_axi_arcache <= dummy ? arcache_i : 4'h3;\n      m_axi_arqos <= dummy  ? arqos_i : 4'h0;\n      m_axi_aruser <= dummy ? aruser_i : 0;\n    end\n  \n    //**********************************************\n    // Read Channel: ARVALID, ARADDR, ARLEN, RREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_arvalid_i <= 1'b0;\n        arcnt_i <= C_NUM_TRANS;\n        m_axi_arlen_i <= 0;\n        m_axi_araddr_i <= C_AXI_ADDR;\n        m_axi_arid_i <= 1;\n        araddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_arready & m_axi_arvalid_i) begin\n          arcnt_i <= arcnt_i - 1;\n          if (araddr_cnt == 1) begin\n            m_axi_araddr_i <= dummy ? araddr_i : C_AXI_ADDR;\n            araddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_araddr_i <= m_axi_araddr_i + 32'h10000;\n            araddr_cnt <= araddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_arlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_arlen_i <= dummy ? arlen_i : 0;\n          end else begin\n            m_axi_arlen_i <= (m_axi_arlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_arid_i == C_NUM_ID)) begin\n            m_axi_arid <= dummy ? arid_i : 0;\n            m_axi_arid_i <= 1;\n          end else begin\n            m_axi_arid <= m_axi_arid_i;\n            m_axi_arid_i <= m_axi_arid_i + 1;\n          end\n          if (arcnt_i == 1) begin\n            m_axi_arvalid_i <= 1'b0;\n          end\n        end else if (arcnt_i != 0) begin\n          m_axi_arvalid_i <= 1'b1;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      araddr_i <= {araddr_i, ~araddr_i[C_AXI_ADDR_WIDTH]};\n      arprot_i <= {arprot_i, ~arprot_i[3-1]};\n      arlen_i <= {arlen_i, ~arlen_i[P_LEN_WIDTH-1]};\n      arsize_i <= {arsize_i, ~arsize_i[3-1]};\n      arburst_i <= {arburst_i, ~arburst_i[2-1]};\n      arlock_i <= {arlock_i, ~arlock_i[2-1]};\n      arcache_i <= {arcache_i, ~arcache_i[4-1]};\n      arqos_i <= {arqos_i, ~arqos_i[4-1]};\n      aruser_i <= {aruser_i, ~aruser_i[C_AXI_ARUSER_WIDTH]};\n      arid_i <= {arid_i, ~arid_i[P_ID_WIDTH-1]};\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        m_axi_rready_i <= 1'b0;\n        rcnt_i <= C_NUM_TRANS;\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        rresp_i <= {2{1'b0}};\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n        rid_i <= {P_ID_WIDTH{1'b0}};\n        acc_r_i <= 4'b0;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_rvalid & m_axi_rready_i) begin\n          m_axi_rready_i <= 1'b0;\n          rdata_i <= m_axi_rdata;\n            acc_r_i[0] <= rdata_i[0];\n          rresp_i <= m_axi_rresp;\n            acc_r_i[1] <= rresp_i[0];\n          ruser_i <= m_axi_ruser;\n            acc_r_i[2] <= ruser_i[0];\n          rid_i <= m_axi_rid;\n            acc_r_i[3] <= rid_i[0];\n          if (m_axi_rlast) begin\n            rcnt_i <= rcnt_i - 1;\n          end\n        end else begin\n          rdata_i <= rdata_i>>1;\n          rresp_i <= rresp_i>>1;\n          ruser_i <= ruser_i>>1;\n          rid_i <= rid_i>>1;\n          acc_r_i <= acc_r_i>>1;\n          if (m_axi_rvalid) begin\n            m_axi_rready_i <= 1'b1;\n          end\n        end\n      end\n    end\n    \n    assign dummy = rdata_i[0];\n    \n    \n\n    /**************** Internal Wires/Regs - Write Channels ****************/\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_awid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [8-1:0]                  xfer_w_i = 8'h00;\n    wire                         write_burst_done_i;\n    reg [C_AXI_ADDR_WIDTH:0]      awaddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  awprot_i = 3'b0;\n    reg [P_LEN_WIDTH-1:0]     awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [3-1:0]                  awsize_i = 3'b0;\n    reg [2-1:0]                  awburst_i = 2'b0;\n    reg [4-1:0]                  awcache_i = 4'b0;\n    reg [2-1:0]                  awlock_i = 2'b0;\n    reg [4-1:0]                  awqos_i = 4'b0;\n    reg [P_ID_WIDTH:0]        awid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_AWUSER_WIDTH:0]    awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg [P_M_AXI_DATA_BYTES-1:0] wstrb_i = {P_M_AXI_DATA_BYTES{1'b1}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]        wid_i = {P_ID_WIDTH{1'b0}};\n    reg [2-1:0]                  bresp_i = 2'b00;\n    reg [C_AXI_BUSER_WIDTH:0]   buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      bid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_awvalid_i = 1'b0;\n    reg                        m_axi_wvalid_i = 1'b0;\n    reg                        m_axi_bready_i = 1'b0;\n    reg                        m_axi_wlast_i = 1'b0;\n    reg                        m_axi_wid_i = {P_ID_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]     wlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [P_NUM_ADDR_LOG:0]    awaddr_cnt = 0;\n  \n    /**************** Assign Write Channel Outputs ****************/\n    assign m_axi_wdata = {wdata_i, done};\n    assign write_burst_done_i = m_axi_wready && m_axi_wvalid_i && ((C_AXI_PROTOCOL==2) || m_axi_wlast_i);\n    assign m_axi_awvalid = m_axi_awvalid_i;\n    assign m_axi_wvalid = m_axi_wvalid_i;\n    assign m_axi_bready = m_axi_bready_i;\n    assign m_axi_wlast = m_axi_wlast_i;\n    assign m_axi_awaddr = m_axi_awaddr_i;\n    assign m_axi_awlen = m_axi_awlen_i;\n    assign m_axi_wid = m_axi_wid_i;\n    always @(posedge aclk) begin\n      m_axi_awprot <= dummy ? awprot_i : 3'b000;\n      m_axi_awsize <= dummy ? awsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_awburst <= dummy ? awburst_i : 2'b01;\n      m_axi_awlock <= dummy ? awlock_i : 1'b0;\n      m_axi_awcache <= dummy ? awcache_i : 4'h3;\n      m_axi_awqos <= dummy ? awqos_i : 4'h0;\n      m_axi_wstrb <= dummy ? wstrb_i : {P_M_AXI_DATA_BYTES{1'b1}};\n      m_axi_awuser <= dummy ?  awuser_i : 0;\n      m_axi_wuser <= dummy ?  wuser_i : 0;\n    end\n  \n    //**********************************************\n    // Write Channel: AWVALID, AWADDR, AWLEN, WVALID, WLAST, BREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_awvalid_i <= 1'b0;\n        m_axi_wvalid_i <= 1'b0;\n        awcnt_i <= C_NUM_TRANS;\n        wcnt_i <= C_NUM_TRANS;\n        xfer_w_i <= 8'h00;\n        m_axi_awlen_i <= 0;\n        m_axi_awaddr_i <= C_AXI_ADDR;\n        m_axi_awid_i <= 1;\n        m_axi_wid_i <= 0;\n        m_axi_wlast_i <= 1'b0;\n        wlen_i <= 0;\n        wid_i <= 0;\n        awaddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_awvalid_i <= 1'b0;\n          awcnt_i <= awcnt_i - 1;\n          if (awaddr_cnt == 1) begin\n            m_axi_awaddr_i <= dummy ? awaddr_i : C_AXI_ADDR;\n            awaddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_awaddr_i <= m_axi_awaddr_i + 32'h10000;\n            awaddr_cnt <= awaddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_awlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_awlen_i <= dummy ? awlen_i : 0;\n          end else begin\n            m_axi_awlen_i <= (m_axi_awlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_awid_i == C_NUM_ID)) begin\n            m_axi_awid <= dummy ? awid_i : 0;\n            m_axi_awid_i <= 1;\n          end else begin\n            m_axi_awid <= m_axi_awid_i;\n            m_axi_awid_i <= m_axi_awid_i + 1;\n          end\n        end else if (~m_axi_wvalid_i) begin\n          if (awcnt_i != 0) begin\n            m_axi_awvalid_i <= 1'b1;\n          end\n        end\n  \n        /**************** Write Data Channel ****************/\n\n        if (m_axi_wready && m_axi_wvalid_i) begin\n          xfer_w_i <= xfer_w_i - 1'b1;\n          if (m_axi_wlast_i) begin\n            m_axi_wvalid_i <= 1'b0;\n            wcnt_i <= wcnt_i - 1'b1;\n          end else begin\n            m_axi_wlast_i <=  (xfer_w_i == 1);\n          end\n        end else if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_wvalid_i <= 1'b1;\n          xfer_w_i <= m_axi_awlen_i;\n          m_axi_wlast_i <= (m_axi_awlen_i==0);\n          m_axi_wid_i <= m_axi_awid_i;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: WDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        wdata_i <= (m_axi_wvalid_i && m_axi_wready) ? {wdata_i[C_AXI_DATA_WIDTH-2 : 0], ~wdata_i[C_AXI_DATA_WIDTH-1]} : wdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      awaddr_i <= {awaddr_i, ~awaddr_i[C_AXI_ADDR_WIDTH]};\n      awprot_i <= {awprot_i[3-2:0], ~awprot_i[3-1]};\n      wstrb_i <= {wstrb_i, ~wstrb_i[C_AXI_DATA_WIDTH/8-1]};\n      awlen_i <= {awlen_i, ~awlen_i[P_LEN_WIDTH-1]};\n      awsize_i <= {awsize_i, ~awsize_i[3-1]};\n      awburst_i <= {awburst_i, ~awburst_i[2-1]};\n      awlock_i <= {awlock_i, ~awlock_i[2-1]};\n      awcache_i <= {awcache_i, ~awcache_i[4-1]};\n      awqos_i <= {awqos_i, ~awqos_i[4-1]};\n      awid_i <= {awid_i, ~awid_i[P_ID_WIDTH-1]};\n      awuser_i <= {awuser_i, ~awuser_i[C_AXI_AWUSER_WIDTH]};\n      wuser_i <= {wuser_i, ~wuser_i[C_AXI_WUSER_WIDTH]};\n    end\n  \n    //**********************************************\n    // Write Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_bready_i <= 1'b0;\n        bcnt_i <= C_NUM_TRANS;\n        bresp_i <= {2{1'b0}};\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n        bid_i <= {P_ID_WIDTH{1'b0}};\n        acc_b_i <= 3'b0;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_bvalid & m_axi_bready_i) begin\n          m_axi_bready_i <= 1'b0;\n          bresp_i <= m_axi_bresp;\n            acc_b_i[0] <= bresp_i[0];\n          buser_i <= m_axi_buser;\n            acc_b_i[1] <= buser_i[0];\n          bid_i <= m_axi_bid;\n            acc_b_i[2] <= bid_i[0];\n          bcnt_i <= bcnt_i - 1;\n        end else begin\n          bresp_i <= bresp_i>>1;\n          buser_i <= buser_i>>1;\n          bid_i <= bid_i>>1;\n          acc_b_i <= acc_b_i>>1;\n          if (m_axi_bvalid) begin\n            m_axi_bready_i <= 1'b1;\n          end\n        end\n      end\n    end\n\n\n  //**********************************************\n  // Assert Done\n  //**********************************************\n  always @(posedge aclk) begin\n    if (~aresetn) begin\n      done_d1 <= 1'b0;\n    end else begin\n      done_d1 <= done_i;\n    end\n  end\n\n  assign done = done_sel ? done_i : done_d1;\n  assign done_cycle = done_i & ~done_d1;\n  \n  always @ * begin\n    if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_readonly_done\n       done_i = rcnt_i==0;\n       done_sel = acc_r_i[0];\n    end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_writeonly_done\n       done_i = bcnt_i==0;\n       done_sel = acc_b_i[0];\n    end else begin : gen_readwrite_done\n       done_i = (rcnt_i==0) && (bcnt_i==0);\n       done_sel = acc_r_i[0] ^ acc_b_i[0];\n    end\n  end\n  \nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n  input  wire [3-1:0]                   s_axi_awprot,\n  input  wire                           s_axi_awvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_awready,\n  input  wire [3-1:0]                   s_axi_awsize,\n  input  wire [2-1:0]                   s_axi_awburst,\n  input  wire [4-1:0]                   s_axi_awcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_awlen,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_awlock,\n  input  wire [4-1:0]                   s_axi_awqos,\n  input  wire [4-1:0]                   s_axi_awregion,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_awid,\n  input  wire [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]   s_axi_awuser,\n  /**************** Write Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n  input  wire                           s_axi_wvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_wready,\n  input  wire                           s_axi_wlast,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_wid,\n  input  wire [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]    s_axi_wuser,\n  /**************** Write Response Channel Signals ****************/\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_bresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_bvalid,\n  input  wire                           s_axi_bready,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]    s_axi_buser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_bid = 'b0,\n  /**************** Read Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n  input  wire [3-1:0]                   s_axi_arprot,\n  input  wire                           s_axi_arvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_arready,\n  input  wire [3-1:0]                   s_axi_arsize,\n  input  wire [2-1:0]                   s_axi_arburst,\n  input  wire [4-1:0]                   s_axi_arcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_arlock,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_arlen,\n  input  wire [4-1:0]                   s_axi_arqos,\n  input  wire [4-1:0]                   s_axi_arregion,\n  input  wire [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]   s_axi_aruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_arid,\n  /**************** Read Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_rresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rvalid,\n  input  wire                           s_axi_rready,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]    s_axi_ruser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_rid = 'b0,\n  /**************** System Signals ****************/\n  input  wire                           aclk,\n  input  wire                           aresetn\n   );\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL == 1) ? 4 : 8;\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer P_S_AXI_DATA_BYTES = 32/8;\n  localparam integer P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n\n  /**************** Internal Wires/Regs - Global ****************/\n  reg                   areset = 1'b0;\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    /**************** Internal Wires/Regs - Read Channels ****************/\n    reg [8-1:0]                   xfer_r_cnt = 8'h00;\n    reg [16-1:0]                  arcnt_i = 16'h0000;\n    wire                          read_xaction_done_i;\n    reg [C_AXI_DATA_WIDTH-1:0]     rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]      arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg                           arvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     araddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   arprot_i = 3'b000;\n    reg [3-1:0]                   arsize_i = 3'b000;\n    reg [2-1:0]                   arburst_i = 2'b00;\n    reg [4-1:0]                   arcache_i = 4'b0000;\n    reg [1-1:0]     arlock_i = 1'b0;\n    reg [4-1:0]                   arqos_i = 4'b0000;\n    reg [4-1:0]                   arregion_i = 4'b0000;\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_RUSER_WIDTH:0]     ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_ar_i = 9'b0;\n    reg                           s_axi_rvalid_i = 1'b0;\n    reg                           s_axi_arready_i = 1'b0;\n    reg                           s_axi_rlast_i = 1'b0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign s_axi_rdata = rdata_i;\n    assign read_xaction_done_i = (s_axi_rready && s_axi_rvalid_i && s_axi_rlast_i);\n    assign s_axi_rvalid = s_axi_rvalid_i;\n    assign s_axi_arready = s_axi_arready_i;\n    assign s_axi_rlast = s_axi_rlast_i;\n    //**********************************************\n    // Read Channel: ARREADY, RVALID, RLAST, RID\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        xfer_r_cnt <= 8'h00;\n        arcnt_i <= 16'h0000;\n        arlen_i <= {P_LEN_WIDTH{1'b0}};\n        s_axi_rlast_i <= 1'b0;\n      end else begin\n        /**************** Read Address Channel ****************/\n        // arready\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_arready_i <= 1'b0;\n          arcnt_i <= arcnt_i + 1'b1;\n        end else if (~s_axi_rvalid_i) begin\n          s_axi_arready_i <= 1'b1;\n        end\n  \n        /**************** Read Data Channel ****************/\n        // rvalid\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_rvalid_i <= 1'b1;\n          s_axi_rid <= s_axi_arid;\n          s_axi_ruser <= ruser_i;\n        end else if(read_xaction_done_i) begin\n          s_axi_rvalid_i <= 1'b0;\n        end\n  \n        // rlast\n        if(s_axi_rready && s_axi_rvalid_i) begin\n          xfer_r_cnt <= xfer_r_cnt - 1;\n          if(xfer_r_cnt == 1) begin\n            s_axi_rlast_i <= 1'b1;\n          end\n        end else if(s_axi_arready_i && s_axi_arvalid) begin\n          xfer_r_cnt <= s_axi_arlen;\n          s_axi_rlast_i <= (s_axi_arlen==0);\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Read Channel: RDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        rdata_i <= (s_axi_rready && s_axi_rvalid_i) ? {rdata_i[C_AXI_DATA_WIDTH-2 : 0], ~rdata_i[C_AXI_DATA_WIDTH-1]} : rdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_rresp <= {2{1'b0}};\n      end else if (~s_axi_rvalid_i) begin\n        s_axi_rresp <= {acc_ar_i[0], 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n      end else begin\n        ruser_i <= (s_axi_arready_i && s_axi_arvalid) ? {ruser_i, ~ruser_i[C_AXI_RUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        araddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        arprot_i <= {3{1'b0}};\n        arsize_i <= {3{1'b0}};\n        arburst_i <= {2{1'b0}};\n        arcache_i <= {4{1'b0}};\n        arlock_i <= {1{1'b0}};\n        arqos_i <= {4{1'b0}};\n        arregion_i <= {4{1'b0}};\n        aruser_i <= {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n        acc_ar_i <= 9'b0;\n      end else if (s_axi_arvalid) begin\n        // Register Inputs\n        araddr_i <= s_axi_araddr;\n          acc_ar_i[0] <= araddr_i[0];\n        arprot_i <= s_axi_arprot;\n          acc_ar_i[1] <= arprot_i[0];\n        arsize_i <= s_axi_arsize;\n          acc_ar_i[2] <= arsize_i[0];\n        arburst_i <= s_axi_arburst;\n          acc_ar_i[3] <= arburst_i[0];\n        arcache_i <= s_axi_arcache;\n          acc_ar_i[4] <= arcache_i[0];\n        arlock_i <= s_axi_arlock;\n          acc_ar_i[5] <= arlock_i[0];\n        arqos_i <= s_axi_arqos;\n          acc_ar_i[6] <= arqos_i[0];\n        arregion_i <= s_axi_arregion;\n          acc_ar_i[7] <= arregion_i[0];\n        aruser_i <= s_axi_aruser;\n          acc_ar_i[8] <= aruser_i[0];\n      end else begin\n        araddr_i <= araddr_i>>1;\n        arprot_i <= arprot_i>>1;\n        arsize_i <= arsize_i>>1;\n        arburst_i <= arburst_i>>1;\n        arcache_i <= arcache_i>>1;\n        arlock_i <= arlock_i>>1;\n        arqos_i <= arqos_i>>1;\n        arregion_i <= arregion_i>>1;\n        aruser_i <= aruser_i>>1;\n        acc_ar_i <= acc_ar_i>>1;\n      end\n    end\n  \n  \n    /**************** Internal Wires/Regs - Write Channels ****************/\n    wire                          write_burst_done_i;\n    reg [16-1:0]                  awcnt_i = 16'h0000;\n    reg                           awvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     awaddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   awprot_i = 3'b000;\n    reg [3-1:0]                   awsize_i = 3'b000;\n    reg [2-1:0]                   awburst_i = 2'b00;\n    reg [4-1:0]                   awcache_i = 4'b0000;\n    reg [P_LEN_WIDTH-1:0]      awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [1-1:0]     awlock_i = 1'b0;\n    reg [4-1:0]                   awqos_i = 4'b0000;\n    reg [4-1:0]                   awregion_i = 4'b0000;\n    reg [C_AXI_AWUSER_WIDTH:0]     awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg                           wvalid_i = 1'b0;\n    reg [C_AXI_DATA_WIDTH-1:0]     wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH/8-1:0]   wstrb_i = {(C_AXI_DATA_WIDTH/8){1'b0}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_BUSER_WIDTH:0]     buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_aw_i = 9'b0;\n    reg [3:0]                     acc_w_i = 4'b0;\n    reg                           s_axi_bvalid_i = 1'b0;\n    reg                           s_axi_awready_i = 1'b0;\n    reg                           s_axi_wready_i = 1'b0;\n    /**************** Assign Write Channel Outputs ****************/\n    assign write_burst_done_i =s_axi_wready_i && s_axi_wvalid && ((C_AXI_PROTOCOL == 2) ? 1'b1 : s_axi_wlast);\n    assign s_axi_bvalid = s_axi_bvalid_i;\n    assign s_axi_awready = s_axi_awready_i;\n    assign s_axi_wready = s_axi_wready_i;\n  \n    //**********************************************\n    // Write Channel: AWREADY, WREADY, BVALID, BID\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awcnt_i <= 16'h0000;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        /**************** Write Address Channel ****************/\n        // awready\n        if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_awready_i <= 1'b0;\n          awcnt_i <= awcnt_i + 1'b1;\n          s_axi_bid <= s_axi_awid;\n          s_axi_buser <= buser_i;\n        end else if(~s_axi_wready_i & ~s_axi_bvalid_i) begin\n          s_axi_awready_i <= 1'b1;\n        end\n  \n        /**************** Write Data Channel ****************/\n        // wready\n        if(write_burst_done_i) begin\n          s_axi_wready_i <= 1'b0;\n        end else if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_wready_i <= 1'b1;\n        end\n  \n        /**************** Write Response Channel ****************/\n        // bvalid\n        if(write_burst_done_i) begin\n          s_axi_bvalid_i <= 1'b1;\n        end else if(s_axi_bready && s_axi_bvalid_i) begin\n          s_axi_bvalid_i <= 1'b0;\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Write Channel: BRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_bresp <= {2{1'b0}};\n      end else if (~s_axi_bvalid_i) begin\n        s_axi_bresp <= {(acc_aw_i[0] ^ acc_w_i[0]), 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: BUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (aresetn) begin\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n      end else begin\n        buser_i <= (s_axi_awready_i && s_axi_awvalid) ? {buser_i, ~buser_i[C_AXI_BUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Write Address Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awaddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        awprot_i <= {3{1'b0}};\n        awsize_i <= {3{1'b0}};\n        awburst_i <= {2{1'b0}};\n        awcache_i <= {4{1'b0}};\n        awlen_i <= {P_LEN_WIDTH{1'b0}};\n        awlock_i <= {1{1'b0}};\n        awqos_i <= {4{1'b0}};\n        awregion_i <= {4{1'b0}};\n        awuser_i <= {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n        acc_aw_i <= 9'b0;\n      end else if (s_axi_awvalid) begin\n        // Register Inputs\n        awaddr_i <= s_axi_awaddr;\n          acc_aw_i[0] <= awaddr_i[0];\n        awprot_i <= s_axi_awprot;\n          acc_aw_i[1] <= awprot_i[0];\n        awsize_i <= s_axi_awsize;\n          acc_aw_i[2] <= awsize_i[0];\n        awburst_i <= s_axi_awburst;\n          acc_aw_i[3] <= awburst_i[0];\n        awcache_i <= s_axi_awcache;\n          acc_aw_i[4] <= awcache_i[0];\n        awlock_i <= s_axi_awlock;\n          acc_aw_i[5] <= awlock_i[0];\n        awqos_i <= s_axi_awqos;\n          acc_aw_i[6] <= awqos_i[0];\n        awregion_i <= s_axi_awregion;\n          acc_aw_i[7] <= awregion_i[0];\n        awuser_i <= s_axi_awuser;\n          acc_aw_i[8] <= awuser_i[0];\n      end else begin\n        awaddr_i <= awaddr_i>>1;\n        awprot_i <= awprot_i>>1;\n        awsize_i <= awsize_i>>1;\n        awburst_i <= awburst_i>>1;\n        awcache_i <= awcache_i>>1;\n        awlock_i <= awlock_i>>1;\n        awqos_i <= awqos_i>>1;\n        awregion_i <= awregion_i>>1;\n        awuser_i <= awuser_i>>1;\n        acc_aw_i <= acc_aw_i>>1;\n      end\n    end\n  \n    //**********************************************\n    // Write Data Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        wstrb_i <= {(C_AXI_DATA_WIDTH/8){1'b0}};\n        wuser_i <= {(C_AXI_WUSER_WIDTH+1){1'b0}};\n        acc_w_i <= 4'b0;\n      end else if (s_axi_wvalid) begin\n        // Register Inputs\n        wdata_i <= s_axi_wdata;\n          acc_w_i[0] <= wdata_i[0];\n        wstrb_i <= s_axi_wstrb;\n          acc_w_i[1] <= wstrb_i[0];\n        wuser_i <= s_axi_wuser;\n          acc_w_i[2] <= wuser_i[0];\n      end else begin\n        wdata_i <= wdata_i>>1;\n        wstrb_i <= wstrb_i>>1;\n        wuser_i <= wuser_i>>1;\n        acc_w_i <= acc_w_i>>1;\n      end\n    end\n  \nendmodule\n\n\n\n//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_22_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \n(* autopipeline_module=\"yes\" *)\nmodule axi_register_slice_v2_1_22_auto_slr #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n    wire                    handshake_pipe;\n    wire                    ready_pipe;\n    wire [C_DATA_WIDTH-1:0] payload_pipe;\n    (* keep=\"true\" *)                                                                reg  s_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  s_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  s_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  s_areset_resp2 = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  m_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  m_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_areset_resp2 = 1'b0;\n    \n  // Global Reset pipelining\n  \n    always @(posedge ACLK) begin\n      s_aclear       <= ~ARESETN;\n      s_areset_fwd   <= ~ARESETN; \n      s_areset_resp  <= s_areset_fwd;  // Auto-pipeline\n      s_areset_resp2 <= s_areset_resp; // Auto-pipeline\n    end\n    \n    always @(posedge ACLK) begin\n      m_aclear       <= ~ARESETN;\n      m_areset_fwd   <= ~ARESETN; \n      m_areset_resp  <= m_areset_fwd;  // Auto-pipeline\n      m_areset_resp2 <= m_areset_resp; // Auto-pipeline\n    end\n    \n  // Source-side submodule\n    \n    axi_register_slice_v2_1_22_auto_src #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_src\n      (\n       .ACLK             (ACLK),    \n       .s_aclear         (s_aclear),\n       .s_areset_resp2   (s_areset_resp2),  \n       .S_VALID          (S_VALID),  \n       .S_READY          (S_READY), \n       .S_PAYLOAD_DATA   (S_PAYLOAD_DATA),\n       .ready_pipe        (ready_pipe), \n       .handshake_pipe    (handshake_pipe),\n       .payload_pipe      (payload_pipe)  \n      );\n    \n  // Destination-side submodule\n    \n    axi_register_slice_v2_1_22_auto_dest #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_dest\n      (\n       .ACLK           (ACLK),    \n       .m_aclear       (m_aclear),\n       .m_areset_resp2 (m_areset_resp2),  \n       .M_READY        (M_READY), \n       .M_VALID        (M_VALID),  \n       .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n       .handshake_pipe  (handshake_pipe),\n       .ready_pipe      (ready_pipe),  \n       .payload_pipe    (payload_pipe)  \n      );\n    \nendmodule  // auto_slr\n\nmodule axi_register_slice_v2_1_22_auto_src #\n  (\n   parameter integer C_DATA_WIDTH = 32\n  )\n  (\n   input  wire ACLK,\n   input  wire s_aclear,\n   input  wire s_areset_resp2,\n   input  wire S_VALID,\n   input  wire ready_pipe,\n   output wire S_READY,\n   output wire handshake_pipe,\n   output wire  [C_DATA_WIDTH-1:0] payload_pipe,\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA\n   );\n    \n   (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  [C_DATA_WIDTH-1:0] payload_pipe_r;\n    (* keep=\"true\" *) reg [2:0] s_aresetn_resp4 = 3'b000;\n    wire s_aresetn_resp3;\n    wire s_aresetn_d;\n    wire s_aresetn_q;\n    wire s_handshake_d;\n    wire s_ready_i;\n    \n    assign S_READY = s_ready_i & s_aresetn_q;\n    assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;\n    assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;\n    assign payload_pipe = payload_pipe_r;\n    \n    always @(posedge ACLK or posedge s_aclear) begin\n      if (s_aclear) begin\n        s_aresetn_resp4 <= 3'b000;\n      end else begin\n        s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      payload_pipe_r <= S_PAYLOAD_DATA;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) s_aresetn_resp3_inst (\n        .Q   (s_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~s_areset_resp2)\n     );\n    \n    // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (s_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_aresetn_d)\n     );\n    \n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (handshake_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_handshake_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (s_ready_i),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (ready_pipe)\n     );\n    \nendmodule  // auto_src\n\nmodule axi_register_slice_v2_1_22_auto_dest #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   input  wire ACLK,\n   input  wire m_aclear,\n   input  wire m_areset_resp2,\n   input  wire M_READY,\n   input  wire handshake_pipe,\n   output wire ready_pipe,\n   output wire M_VALID,\n   input  wire [C_DATA_WIDTH-1:0] payload_pipe,\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n   );\n    \n    (* keep=\"true\" *) reg [2:0] m_aresetn_resp4 = 3'b000;\n    wire m_aresetn_resp3;\n    wire m_aresetn_d;\n    wire m_aresetn_q;\n    wire m_valid_i;\n    wire pop;\n    wire m_ready_d;\n    wire m_handshake_q;\n    reg  [C_DATA_WIDTH-1:0] m_payload_q;\n    \n    assign M_VALID = m_valid_i;\n    assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;\n    assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;\n    assign pop     = M_READY & m_valid_i;\n    \n    always @(posedge ACLK or posedge m_aclear) begin\n      if (m_aclear) begin\n        m_aresetn_resp4 <= 3'b000;\n      end else begin\n        m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      m_payload_q <= payload_pipe;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) m_aresetn_resp3_inst (\n        .Q   (m_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~m_areset_resp2)\n     );\n    \n    // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (m_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_aresetn_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (m_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (handshake_pipe)\n     );\n    \n    (* autopipeline_group=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (ready_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_ready_d)\n     );\n    \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  (5)  \n      )\n      srl_fifo\n      (\n       .aclk    (ACLK),    \n       .areset  (~m_aresetn_q),\n       .aclear  (m_aclear),  \n       .s_mesg  (m_payload_q),  \n       .s_valid (m_handshake_q), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      );\n    \nendmodule  // auto_dest\n\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      reg s_valid_d;\n      reg s_ready_d = 1'b0;\n      reg s_ready_reg = 1'b0;\n      reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_22_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_RESP_MIDDLE2_LATENCY = C_PIPELINES_SLAVE + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_22_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      .ACLK           (ACLK),\n      .ARESETN         (ARESETN),\n      .S_PAYLOAD_DATA (S_PAYLOAD_DATA),\n      .S_VALID        (S_VALID),\n      .S_READY        (S_READY),\n      .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n      .M_VALID        (M_VALID),\n      .M_READY        (M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_reset;\n    wire src_ready;\n    wire dummy_reset;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  ( C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( dummy_reset   ) ,\n        .laguna_s_reset_in  ( src_reset   ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset   ) ,\n        .laguna_m_reset_in  ( src_reset  ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset2   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n      \n  end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] mid_payload;\n    wire mid_handshake;\n    wire mid_ready;\n    wire mid_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n    wire dummy_reset3;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( mid_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( mid_reset    ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset3   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset3   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out (  dummy_reset2  ) ,\n        .laguna_m_reset_in  ( mid_reset   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE2_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( mid_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2   ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset3   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset3    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n   \n  generate\n\n  (* keep=\"true\" *) reg s_reset_dd = 1'b0;\n  (* keep=\"true\" *) reg m_reset_dd = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n  \n  assign laguna_s_reset_out = laguna_s_reset_out_i;\n  assign laguna_m_reset_out = laguna_m_reset_out_i;\n  \n  always @(posedge ACLK) begin\n    laguna_s_reset_in_d <= laguna_s_reset_in;\n    laguna_m_reset_in_d <= laguna_m_reset_in;\n    s_reset_dd <= laguna_s_reset_in_d;\n    m_reset_dd <= laguna_m_reset_in_d;\n    laguna_s_reset_out_i <= C_PIPELINES==0 ? laguna_m_reset_in_d : m_reset_dd;\n    laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;\n  end\n  \n  wire ACLEAR;\n  assign ACLEAR = ~ARESETN;\n  \n  if (1) begin : common\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire laguna_s_handshake_q;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, laguna_m_ready_d}; \n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else if (p==C_PIPELINES+1) begin\n          laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n\n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = handshake_i[C_PIPELINES];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_m_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* keep=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_22_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_m_reset_out = laguna_m_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_m_reset_in_d <= laguna_m_reset_in;\n      aresetn_d <= C_CHANNEL==P_FORWARD ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? areset_dly[15]  : laguna_m_reset_in_d;\n      laguna_m_reset_out_i <= areset_d;  // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n  \n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* keep=\"true\" *)  reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      ready_d <= {ready_d, laguna_m_ready_d}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid_q;\n      assign payload_valid_d = (p==0) ? (S_VALID & s_ready_i) : handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==C_PIPELINES) begin\n          laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else if (p==0) begin\n          payload_data <= S_PAYLOAD_DATA;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n      \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_s_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* keep=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_s_reset_out = laguna_s_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_s_reset_in_d <= laguna_s_reset_in;\n      aresetn_d <= C_CHANNEL==P_RESPONSE ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? laguna_s_reset_in_d : areset_dly[15];\n      laguna_s_reset_out_i <= areset_d;  // For forward channels, reflect laguna_s_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n\n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    wire laguna_s_handshake_q;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      laguna_s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n        \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n        \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)  \n      )\n      srl_fifo_0\n      (\n       .aclk    (ACLK),    \n       .areset  (areset_d),  \n       .aclear  (ACLEAR),\n       .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n       .s_valid (push), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      ); \n  \n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  reg areset_d = 1'b0;\n  reg [3:0] areset_dly = 4'b0;\n  always @(posedge ACLK) begin\n    areset_dly <= {4{~ARESETN}} | (areset_dly<<1);\n    areset_d <= areset_dly[3];\n  end\n  \n  if (1) begin : common\n    reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID & s_ready_i;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* keep=\"true\" *)  reg payload_valid = 1'b0;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          payload_data <= S_PAYLOAD_DATA;\n          payload_valid <= S_VALID & s_ready_i & ~areset_d;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n          payload_valid <= handshake_i[((p>0)?(p-1):0)];\n        end\n      end\n    end\n    \n    if (C_PIPELINES==0) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),\n         .aclear  (1'b0),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire                        aclear,  // Async clear\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    wire [1:0] state;  // State vector register\n    reg  [1:0] next;           // Next state value\n    wire [1:0] next_qual;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    reg  m_valid_d;\n    wire m_valid_q;\n    \n    assign m_valid = m_valid_q;\n    assign next_qual = areset ? K_EMPTY : next;\n    assign m_mesg  = mesg_reg;\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_mvalid_inst (\n        .Q   (m_valid_q),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (m_valid_d)\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state0_inst (\n        .Q   (state[0]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[0])\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state1_inst (\n        .Q   (state[1]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[1])\n     );\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      m_valid_d = m_valid_q & ~areset;\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid & ~areset) begin\n            next = K_HAS1;\n            m_valid_d = 1'b0;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              m_valid_d = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n              m_valid_d = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          m_valid_d = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      (* keep_hierarchy = \"yes\" *) axi_register_slice_v2_1_22_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule  // axic_reg_srl_fifo\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   //   16 -> Auto-pipelining\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_RESERVE_MODE = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n  \n  if (C_RESERVE_MODE==1) begin : gen_reserve_si\n  \n    axi_register_slice_v2_1_22_test_slave #(\n      .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n      .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n      .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n      .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n      .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n      .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n      .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n      .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n      .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .s_axi_awaddr(s_axi_awaddr),\n      .s_axi_awprot(s_axi_awprot),\n      .s_axi_awvalid(s_axi_awvalid),\n      .s_axi_awready(s_axi_awready),\n      .s_axi_awsize(s_axi_awsize),\n      .s_axi_awburst(s_axi_awburst),\n      .s_axi_awcache(s_axi_awcache),\n      .s_axi_awlen(s_axi_awlen),\n      .s_axi_awlock(s_axi_awlock),\n      .s_axi_awqos(s_axi_awqos),\n      .s_axi_awregion(s_axi_awregion),\n      .s_axi_awid(s_axi_awid),\n      .s_axi_awuser(s_axi_awuser),\n      .s_axi_wdata(s_axi_wdata),\n      .s_axi_wstrb(s_axi_wstrb),\n      .s_axi_wvalid(s_axi_wvalid),\n      .s_axi_wready(s_axi_wready),\n      .s_axi_wlast(s_axi_wlast),\n      .s_axi_wid(s_axi_wid),\n      .s_axi_wuser(s_axi_wuser),\n      .s_axi_bresp(s_axi_bresp),\n      .s_axi_bvalid(s_axi_bvalid),\n      .s_axi_bready(s_axi_bready),\n      .s_axi_buser(s_axi_buser),\n      .s_axi_bid(s_axi_bid),\n      .s_axi_araddr(s_axi_araddr),\n      .s_axi_arprot(s_axi_arprot),\n      .s_axi_arvalid(s_axi_arvalid),\n      .s_axi_arready(s_axi_arready),\n      .s_axi_arsize(s_axi_arsize),\n      .s_axi_arburst(s_axi_arburst),\n      .s_axi_arcache(s_axi_arcache),\n      .s_axi_arlock(s_axi_arlock),\n      .s_axi_arlen(s_axi_arlen),\n      .s_axi_arqos(s_axi_arqos),\n      .s_axi_arregion(s_axi_arregion),\n      .s_axi_aruser(s_axi_aruser),\n      .s_axi_arid(s_axi_arid),\n      .s_axi_rdata(s_axi_rdata),\n      .s_axi_rresp(s_axi_rresp),\n      .s_axi_rvalid(s_axi_rvalid),\n      .s_axi_rready(s_axi_rready),\n      .s_axi_rlast(s_axi_rlast),\n      .s_axi_ruser(s_axi_ruser),\n      .s_axi_rid(s_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign m_axi_awid     = 0;\n     assign m_axi_awaddr   = 0;\n     assign m_axi_awlen    = 0;\n     assign m_axi_awsize   = 0;\n     assign m_axi_awburst  = 0;\n     assign m_axi_awlock   = 0;\n     assign m_axi_awcache  = 0;\n     assign m_axi_awprot   = 0;\n     assign m_axi_awregion = 0;\n     assign m_axi_awqos    = 0;\n     assign m_axi_awuser   = 0;\n     assign m_axi_awvalid  = 0;\n     assign m_axi_wid      = 0;\n     assign m_axi_wdata    = 0;\n     assign m_axi_wstrb    = 0;\n     assign m_axi_wlast    = 0;\n     assign m_axi_wuser    = 0;\n     assign m_axi_wvalid   = 0;\n     assign m_axi_bready   = 0;\n     assign m_axi_arid     = 0;\n     assign m_axi_araddr   = 0;\n     assign m_axi_arlen    = 0;\n     assign m_axi_arsize   = 0;\n     assign m_axi_arburst  = 0;\n     assign m_axi_arlock   = 0;\n     assign m_axi_arcache  = 0;\n     assign m_axi_arprot   = 0;\n     assign m_axi_arregion = 0;\n     assign m_axi_arqos    = 0;\n     assign m_axi_aruser   = 0;\n     assign m_axi_arvalid  = 0;\n     assign m_axi_rready   = 0;\n      \n  end else if (C_RESERVE_MODE==2) begin : gen_reserve_mi\n    \n    axi_register_slice_v2_1_22_test_master #(\n    .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n    .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .m_axi_awaddr(m_axi_awaddr),\n      .m_axi_awprot(m_axi_awprot),\n      .m_axi_awvalid(m_axi_awvalid),\n      .m_axi_awready(m_axi_awready),\n      .m_axi_awsize(m_axi_awsize),\n      .m_axi_awburst(m_axi_awburst),\n      .m_axi_awcache(m_axi_awcache),\n      .m_axi_awlen(m_axi_awlen),\n      .m_axi_awlock(m_axi_awlock),\n      .m_axi_awqos(m_axi_awqos),\n      .m_axi_awid(m_axi_awid),\n      .m_axi_awuser(m_axi_awuser),\n      .m_axi_wid(m_axi_wid),\n      .m_axi_wdata(m_axi_wdata),\n      .m_axi_wstrb(m_axi_wstrb),\n      .m_axi_wvalid(m_axi_wvalid),\n      .m_axi_wready(m_axi_wready),\n      .m_axi_wlast(m_axi_wlast),\n      .m_axi_wuser(m_axi_wuser),\n      .m_axi_bresp(m_axi_bresp),\n      .m_axi_bvalid(m_axi_bvalid),\n      .m_axi_bready(m_axi_bready),\n      .m_axi_buser(m_axi_buser),\n      .m_axi_bid(m_axi_bid),\n      .m_axi_araddr(m_axi_araddr),\n      .m_axi_arprot(m_axi_arprot),\n      .m_axi_arvalid(m_axi_arvalid),\n      .m_axi_arready(m_axi_arready),\n      .m_axi_arsize(m_axi_arsize),\n      .m_axi_arburst(m_axi_arburst),\n      .m_axi_arcache(m_axi_arcache),\n      .m_axi_arlen(m_axi_arlen),\n      .m_axi_arlock(m_axi_arlock),\n      .m_axi_arqos(m_axi_arqos),\n      .m_axi_arid(m_axi_arid),\n      .m_axi_aruser(m_axi_aruser),\n      .m_axi_rdata(m_axi_rdata),\n      .m_axi_rresp(m_axi_rresp),\n      .m_axi_rvalid(m_axi_rvalid),\n      .m_axi_rready(m_axi_rready),\n      .m_axi_rlast(m_axi_rlast),\n      .m_axi_ruser(m_axi_ruser),\n      .m_axi_rid(m_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign s_axi_awready = 0;\n     assign s_axi_wready  = 0;\n     assign s_axi_bid     = 0;\n     assign s_axi_bresp   = 0;\n     assign s_axi_buser   = 0;\n     assign s_axi_bvalid  = 0;\n     assign s_axi_arready = 0;\n     assign s_axi_rid     = 0;\n     assign s_axi_rdata   = 0;\n     assign s_axi_rresp   = 0;\n     assign s_axi_rlast   = 0;\n     assign s_axi_ruser   = 0;\n     assign s_axi_rvalid  = 0;\n\n  end else begin : gen_reg_slice  // Any normal reg-slice mode\n\n    axi_infrastructure_v1_1_0_axi2vector #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    axi2vector_0 ( \n      .s_axi_awid      ( s_axi_awid      ) ,\n      .s_axi_awaddr    ( s_axi_awaddr    ) ,\n      .s_axi_awlen     ( s_axi_awlen     ) ,\n      .s_axi_awsize    ( s_axi_awsize    ) ,\n      .s_axi_awburst   ( s_axi_awburst   ) ,\n      .s_axi_awlock    ( s_axi_awlock    ) ,\n      .s_axi_awcache   ( s_axi_awcache   ) ,\n      .s_axi_awprot    ( s_axi_awprot    ) ,\n      .s_axi_awqos     ( s_axi_awqos     ) ,\n      .s_axi_awuser    ( s_axi_awuser    ) ,\n      .s_axi_awregion  ( s_axi_awregion  ) ,\n      .s_axi_wid       ( s_axi_wid       ) ,\n      .s_axi_wdata     ( s_axi_wdata     ) ,\n      .s_axi_wstrb     ( s_axi_wstrb     ) ,\n      .s_axi_wlast     ( s_axi_wlast     ) ,\n      .s_axi_wuser     ( s_axi_wuser     ) ,\n      .s_axi_bid       ( s_axi_bid       ) ,\n      .s_axi_bresp     ( s_axi_bresp     ) ,\n      .s_axi_buser     ( s_axi_buser     ) ,\n      .s_axi_arid      ( s_axi_arid      ) ,\n      .s_axi_araddr    ( s_axi_araddr    ) ,\n      .s_axi_arlen     ( s_axi_arlen     ) ,\n      .s_axi_arsize    ( s_axi_arsize    ) ,\n      .s_axi_arburst   ( s_axi_arburst   ) ,\n      .s_axi_arlock    ( s_axi_arlock    ) ,\n      .s_axi_arcache   ( s_axi_arcache   ) ,\n      .s_axi_arprot    ( s_axi_arprot    ) ,\n      .s_axi_arqos     ( s_axi_arqos     ) ,\n      .s_axi_aruser    ( s_axi_aruser    ) ,\n      .s_axi_arregion  ( s_axi_arregion  ) ,\n      .s_axi_rid       ( s_axi_rid       ) ,\n      .s_axi_rdata     ( s_axi_rdata     ) ,\n      .s_axi_rresp     ( s_axi_rresp     ) ,\n      .s_axi_rlast     ( s_axi_rlast     ) ,\n      .s_axi_ruser     ( s_axi_ruser     ) ,\n      .s_awpayload ( s_awpayload ) ,\n      .s_wpayload  ( s_wpayload  ) ,\n      .s_bpayload  ( s_bpayload  ) ,\n      .s_arpayload ( s_arpayload ) ,\n      .s_rpayload  ( s_rpayload  ) \n    );\n    \n    axi_infrastructure_v1_1_0_vector2axi #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    vector2axi_0 ( \n      .m_awpayload    ( m_awpayload    ) ,\n      .m_wpayload     ( m_wpayload     ) ,\n      .m_bpayload     ( m_bpayload     ) ,\n      .m_arpayload    ( m_arpayload    ) ,\n      .m_rpayload     ( m_rpayload     ) ,\n      .m_axi_awid     ( m_axi_awid     ) ,\n      .m_axi_awaddr   ( m_axi_awaddr   ) ,\n      .m_axi_awlen    ( m_axi_awlen    ) ,\n      .m_axi_awsize   ( m_axi_awsize   ) ,\n      .m_axi_awburst  ( m_axi_awburst  ) ,\n      .m_axi_awlock   ( m_axi_awlock   ) ,\n      .m_axi_awcache  ( m_axi_awcache  ) ,\n      .m_axi_awprot   ( m_axi_awprot   ) ,\n      .m_axi_awqos    ( m_axi_awqos    ) ,\n      .m_axi_awuser   ( m_axi_awuser   ) ,\n      .m_axi_awregion ( m_axi_awregion ) ,\n      .m_axi_wid      ( m_axi_wid      ) ,\n      .m_axi_wdata    ( m_axi_wdata    ) ,\n      .m_axi_wstrb    ( m_axi_wstrb    ) ,\n      .m_axi_wlast    ( m_axi_wlast    ) ,\n      .m_axi_wuser    ( m_axi_wuser    ) ,\n      .m_axi_bid      ( m_axi_bid      ) ,\n      .m_axi_bresp    ( m_axi_bresp    ) ,\n      .m_axi_buser    ( m_axi_buser    ) ,\n      .m_axi_arid     ( m_axi_arid     ) ,\n      .m_axi_araddr   ( m_axi_araddr   ) ,\n      .m_axi_arlen    ( m_axi_arlen    ) ,\n      .m_axi_arsize   ( m_axi_arsize   ) ,\n      .m_axi_arburst  ( m_axi_arburst  ) ,\n      .m_axi_arlock   ( m_axi_arlock   ) ,\n      .m_axi_arcache  ( m_axi_arcache  ) ,\n      .m_axi_arprot   ( m_axi_arprot   ) ,\n      .m_axi_arqos    ( m_axi_arqos    ) ,\n      .m_axi_aruser   ( m_axi_aruser   ) ,\n      .m_axi_arregion ( m_axi_arregion ) ,\n      .m_axi_rid      ( m_axi_rid      ) ,\n      .m_axi_rdata    ( m_axi_rdata    ) ,\n      .m_axi_rresp    ( m_axi_rresp    ) ,\n      .m_axi_rlast    ( m_axi_rlast    ) ,\n      .m_axi_ruser    ( m_axi_ruser    ) \n    );\n    \n  end  // Reserve SI/MI branch\n\n  if ((C_REG_CONFIG_AW <= 9) && (C_RESERVE_MODE==0)) begin : aw\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 15) && (C_RESERVE_MODE==0)) begin : aw15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 16) && (C_RESERVE_MODE==0)) begin : aw16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) \n    )\n    aw_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if ((C_REG_CONFIG_W <= 9) && (C_RESERVE_MODE==0)) begin : w\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 15) && (C_RESERVE_MODE==0)) begin : w15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 16) && (C_RESERVE_MODE==0)) begin : w16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) \n    )\n    w_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if ((C_REG_CONFIG_B <= 9) && (C_RESERVE_MODE==0)) begin : b\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if ((C_REG_CONFIG_B == 15) && (C_RESERVE_MODE==0)) begin : b15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if ((C_REG_CONFIG_B == 16) && (C_RESERVE_MODE==0)) begin : b16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) \n    )\n    b_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if ((C_REG_CONFIG_AR <= 9) && (C_RESERVE_MODE==0)) begin : ar\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 15) && (C_RESERVE_MODE==0)) begin : ar15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 16) && (C_RESERVE_MODE==0)) begin : ar16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) \n    )\n    ar_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if ((C_REG_CONFIG_R <= 9) && (C_RESERVE_MODE==0)) begin : r\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 15) && (C_RESERVE_MODE==0)) begin : r15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 16) && (C_RESERVE_MODE==0)) begin : r16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) \n    )\n    r_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 4844}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized AND with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_carry_and #\n  (\n   parameter         C_FAMILY                         = \"virtex6\"\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   )\n  (\n   input  wire        CIN,\n   input  wire        S,\n   output wire        COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n\n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n      assign COUT = CIN & S;\n      \n    end else begin : USE_FPGA\n      MUXCY and_inst \n      (\n       .O (COUT), \n       .CI (CIN), \n       .DI (1'b0), \n       .S (S)\n      ); \n      \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized AND with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_carry_latch_and #\n  (\n   parameter          C_FAMILY                         = \"virtex6\"\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   )\n  (\n   input  wire        CIN,\n   input  wire        I,\n   output wire        O\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n\n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n      assign O = CIN & ~I;\n      \n    end else begin : USE_FPGA\n      wire I_n;\n      \n      assign I_n = ~I;\n    \n      AND2B1L and2b1l_inst \n        (\n         .O(O),\n         .DI(CIN),\n         .SRI(I_n)\n        );\n      \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized OR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_carry_latch_or #\n  (\n   parameter          C_FAMILY                         = \"virtex6\"\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   )\n  (\n   input  wire        CIN,\n   input  wire        I,\n   output wire        O\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n      assign O = CIN | I;\n      \n    end else begin : USE_FPGA\n      OR2L or2l_inst1\n        (\n         .O(O),\n         .DI(CIN),\n         .SRI(I)\n        );\n      \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized OR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_carry_or #\n  (\n   parameter         C_FAMILY                         = \"virtex6\"\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   )\n  (\n   input  wire        CIN,\n   input  wire        S,\n   output wire        COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n      assign COUT = CIN | S;\n      \n    end else begin : USE_FPGA\n      wire S_n;\n      \n      assign S_n = ~S;\n    \n      MUXCY and_inst \n      (\n       .O (COUT), \n       .CI (CIN), \n       .DI (1'b1), \n       .S (S_n)\n      ); \n      \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_carry #\n  (\n   parameter         C_FAMILY                         = \"virtex6\"\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   )\n  (\n   input  wire        CIN,\n   input  wire        S,\n   input  wire        DI,\n   output wire        COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n      assign COUT = (CIN & S) | (DI & ~S);\n      \n    end else begin : USE_FPGA\n    \n      MUXCY and_inst \n      (\n       .O (COUT), \n       .CI (CIN), \n       .DI (DI), \n       .S (S)\n      ); \n      \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized 16/32 word deep FIFO.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_command_fifo #\n  (\n   parameter         C_FAMILY                        = \"virtex6\",\n   parameter integer C_ENABLE_S_VALID_CARRY          = 0,\n   parameter integer C_ENABLE_REGISTERED_OUTPUT      = 0,\n   parameter integer C_FIFO_DEPTH_LOG                = 5,      // FIFO depth = 2**C_FIFO_DEPTH_LOG\n                                                               // Range = [4:5].\n   parameter integer C_FIFO_WIDTH                    = 64      // Width of payload [1:512]\n   )\n  (\n   // Global inputs\n   input  wire                        ACLK,    // Clock\n   input  wire                        ARESET,  // Reset\n   // Information\n   output wire                        EMPTY,   // FIFO empty (all stages)\n   // Slave  Port\n   input  wire [C_FIFO_WIDTH-1:0]     S_MESG,  // Payload (may be any set of channel signals)\n   input  wire                        S_VALID, // FIFO push\n   output wire                        S_READY, // FIFO not full\n   // Master  Port\n   output wire [C_FIFO_WIDTH-1:0]     M_MESG,  // Payload\n   output wire                        M_VALID, // FIFO not empty\n   input  wire                        M_READY  // FIFO pop\n   );\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for data vector.\n  genvar addr_cnt;\n  genvar bit_cnt;\n  integer index;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIFO_DEPTH_LOG-1:0] addr;\n  wire                        buffer_Full;\n  wire                        buffer_Empty;\n  \n  wire                        next_Data_Exists;\n  reg                         data_Exists_I = 1'b0;\n  \n  wire                        valid_Write;\n  wire                        new_write;\n  \n  wire [C_FIFO_DEPTH_LOG-1:0] hsum_A;\n  wire [C_FIFO_DEPTH_LOG-1:0] sum_A;\n  wire [C_FIFO_DEPTH_LOG-1:0] addr_cy;\n\n  wire                        buffer_full_early;\n  \n  wire [C_FIFO_WIDTH-1:0]     M_MESG_I;   // Payload\n  wire                        M_VALID_I;  // FIFO not empty\n  wire                        M_READY_I;  // FIFO pop\n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Create Flags \n  /////////////////////////////////////////////////////////////////////////////\n  \n  assign buffer_full_early  = ( (addr == {{C_FIFO_DEPTH_LOG-1{1'b1}}, 1'b0}) & valid_Write & ~M_READY_I ) |\n                              ( buffer_Full & ~M_READY_I );\n\n  assign S_READY            = ~buffer_Full;\n\n  assign buffer_Empty       = (addr == {C_FIFO_DEPTH_LOG{1'b0}});\n\n  assign next_Data_Exists   = (data_Exists_I & ~buffer_Empty) |\n                              (buffer_Empty & S_VALID) |\n                              (data_Exists_I & ~(M_READY_I & data_Exists_I));\n\n  always @ (posedge ACLK) begin\n    if (ARESET) begin\n      data_Exists_I <= 1'b0;\n    end else begin\n      data_Exists_I <= next_Data_Exists;\n    end\n  end\n\n  assign M_VALID_I = data_Exists_I;\n  \n  // Select RTL or FPGA optimized instatiations for critical parts.\n  generate\n    if ( C_FAMILY == \"rtl\" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE\n      reg                         buffer_Full_q = 1'b0;\n      \n      assign valid_Write = S_VALID & ~buffer_Full;\n      \n      assign new_write = (S_VALID | ~buffer_Empty);\n     \n      assign addr_cy[0] = valid_Write;\n      \n      always @ (posedge ACLK) begin\n        if (ARESET) begin\n          buffer_Full_q <= 1'b0;\n        end else if ( data_Exists_I ) begin\n          buffer_Full_q <= buffer_full_early;\n        end\n      end\n      assign buffer_Full = buffer_Full_q;\n      \n    end else begin : USE_FPGA_VALID_WRITE\n      wire s_valid_dummy1;\n      wire s_valid_dummy2;\n      wire sel_s_valid;\n      wire sel_new_write;\n      wire valid_Write_dummy1;\n      wire valid_Write_dummy2;\n      \n      assign sel_s_valid = ~buffer_Full;\n      \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) s_valid_dummy_inst1\n        (\n         .CIN(S_VALID),\n         .S(1'b1),\n         .COUT(s_valid_dummy1)\n         );\n      \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) s_valid_dummy_inst2\n        (\n         .CIN(s_valid_dummy1),\n         .S(1'b1),\n         .COUT(s_valid_dummy2)\n         );\n      \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) valid_write_inst\n        (\n         .CIN(s_valid_dummy2),\n         .S(sel_s_valid),\n         .COUT(valid_Write)\n         );\n      \n      assign sel_new_write = ~buffer_Empty;\n       \n      generic_baseblocks_v2_1_0_carry_latch_or #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) new_write_inst\n        (\n         .CIN(valid_Write),\n         .I(sel_new_write),\n         .O(new_write)\n         );\n         \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) valid_write_dummy_inst1\n        (\n         .CIN(valid_Write),\n         .S(1'b1),\n         .COUT(valid_Write_dummy1)\n         );\n      \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) valid_write_dummy_inst2\n        (\n         .CIN(valid_Write_dummy1),\n         .S(1'b1),\n         .COUT(valid_Write_dummy2)\n         );\n      \n      generic_baseblocks_v2_1_0_carry_and #\n        (\n         .C_FAMILY(C_FAMILY)\n         ) valid_write_dummy_inst3\n        (\n         .CIN(valid_Write_dummy2),\n         .S(1'b1),\n         .COUT(addr_cy[0])\n         );\n      \n      FDRE #(\n       .INIT(1'b0)              // Initial value of register (1'b0 or 1'b1)\n       ) FDRE_I1 (\n       .Q(buffer_Full),         // Data output\n       .C(ACLK),                // Clock input\n       .CE(data_Exists_I),      // Clock enable input\n       .R(ARESET),              // Synchronous reset input\n       .D(buffer_full_early)    // Data input\n       );\n       \n    end\n  endgenerate\n      \n    \n  /////////////////////////////////////////////////////////////////////////////\n  // Create address pointer\n  /////////////////////////////////////////////////////////////////////////////\n\n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_ADDR\n    \n      reg  [C_FIFO_DEPTH_LOG-1:0] addr_q = {C_FIFO_DEPTH_LOG{1'b0}};\n      \n      always @ (posedge ACLK) begin\n        if (ARESET) begin\n          addr_q <= {C_FIFO_DEPTH_LOG{1'b0}};\n        end else if ( data_Exists_I ) begin\n          if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin\n            addr_q <= addr_q + 1'b1;\n          end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin\n            addr_q <= addr_q - 1'b1;\n          end\n          else begin\n            addr_q <= addr_q;\n          end\n        end\n        else begin\n          addr_q <= addr_q;\n        end\n      end\n      \n      assign addr = addr_q;\n      \n    end else begin : USE_FPGA_ADDR\n      for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN\n        assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write;\n        \n        // Don't need the last muxcy, addr_cy(last) is not used anywhere\n        if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY\n          MUXCY MUXCY_inst (\n           .DI(addr[addr_cnt]),\n           .CI(addr_cy[addr_cnt]),\n           .S(hsum_A[addr_cnt]),\n           .O(addr_cy[addr_cnt+1])\n           );\n           \n        end\n        else begin : NO_MUXCY\n        end\n        \n        XORCY XORCY_inst (\n         .LI(hsum_A[addr_cnt]),\n         .CI(addr_cy[addr_cnt]),\n         .O(sum_A[addr_cnt])\n         );\n        \n        FDRE #(\n         .INIT(1'b0)             // Initial value of register (1'b0 or 1'b1)\n         ) FDRE_inst (\n         .Q(addr[addr_cnt]),     // Data output\n         .C(ACLK),               // Clock input\n         .CE(data_Exists_I),     // Clock enable input\n         .R(ARESET),             // Synchronous reset input\n         .D(sum_A[addr_cnt])     // Data input\n         );\n        \n      end // end for bit_cnt\n    end // C_FAMILY\n  endgenerate\n      \n      \n  /////////////////////////////////////////////////////////////////////////////\n  // Data storage\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_FIFO\n      reg  [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0];\n      \n      always @ (posedge ACLK) begin\n        if ( valid_Write ) begin\n          for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin\n            data_srl[index+1] <= data_srl[index];\n          end\n          data_srl[0]   <= S_MESG;\n        end\n      end\n      \n      assign M_MESG_I = data_srl[addr];\n      \n    end else begin : USE_FPGA_FIFO\n      for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN\n        \n        if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32\n            SRLC32E # (\n             .INIT(32'h00000000)    // Initial Value of Shift Register\n            ) SRLC32E_inst (\n             .Q(M_MESG_I[bit_cnt]), // SRL data output\n             .Q31(),                // SRL cascade output pin\n             .A(addr),              // 5-bit shift depth select input\n             .CE(valid_Write),      // Clock enable input\n             .CLK(ACLK),            // Clock input\n             .D(S_MESG[bit_cnt])    // SRL data input\n            );\n        end else begin : USE_16\n            SRLC16E # (\n             .INIT(32'h00000000)    // Initial Value of Shift Register\n            ) SRLC16E_inst (\n             .Q(M_MESG_I[bit_cnt]), // SRL data output\n             .Q15(),                // SRL cascade output pin\n             .A0(addr[0]),          // 4-bit shift depth select input 0\n             .A1(addr[1]),          // 4-bit shift depth select input 1\n             .A2(addr[2]),          // 4-bit shift depth select input 2\n             .A3(addr[3]),          // 4-bit shift depth select input 3\n             .CE(valid_Write),      // Clock enable input\n             .CLK(ACLK),            // Clock input\n             .D(S_MESG[bit_cnt])    // SRL data input\n            );\n        end // C_FIFO_DEPTH_LOG\n      \n      end // end for bit_cnt\n    end // C_FAMILY\n  endgenerate\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Pipeline stage\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT\n      \n      wire [C_FIFO_WIDTH-1:0]     M_MESG_FF;    // Payload\n      wire                        M_VALID_FF;   // FIFO not empty\n      \n      // Select RTL or FPGA optimized instatiations for critical parts.\n      if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_OUTPUT_PIPELINE\n      \n        reg  [C_FIFO_WIDTH-1:0]     M_MESG_Q;   // Payload\n        reg                         M_VALID_Q = 1'b0;  // FIFO not empty\n        \n        always @ (posedge ACLK) begin\n          if (ARESET) begin\n            M_MESG_Q    <= {C_FIFO_WIDTH{1'b0}};\n            M_VALID_Q   <= 1'b0;\n          end else begin\n            if ( M_READY_I ) begin\n              M_MESG_Q    <= M_MESG_I;\n              M_VALID_Q   <= M_VALID_I;\n            end\n          end\n        end\n      \n        assign M_MESG_FF     = M_MESG_Q;\n        assign M_VALID_FF    = M_VALID_Q;\n        \n      end else begin : USE_FPGA_OUTPUT_PIPELINE\n      \n        reg  [C_FIFO_WIDTH-1:0]     M_MESG_CMB;   // Payload\n        reg                         M_VALID_CMB;  // FIFO not empty\n        \n        always @ *\n        begin\n          if ( M_READY_I ) begin\n            M_MESG_CMB  <= M_MESG_I;\n            M_VALID_CMB <= M_VALID_I;\n          end else begin\n            M_MESG_CMB  <= M_MESG_FF;\n            M_VALID_CMB <= M_VALID_FF;\n          end\n        end\n        \n        for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN\n              \n          FDRE #(\n           .INIT(1'b0)                    // Initial value of register (1'b0 or 1'b1)\n           ) FDRE_inst (\n           .Q(M_MESG_FF[bit_cnt]),        // Data output\n           .C(ACLK),                      // Clock input\n           .CE(1'b1),                     // Clock enable input\n           .R(ARESET),                    // Synchronous reset input\n           .D(M_MESG_CMB[bit_cnt])        // Data input\n           );\n        end // end for bit_cnt\n            \n        FDRE #(\n         .INIT(1'b0)                    // Initial value of register (1'b0 or 1'b1)\n         ) FDRE_inst (\n         .Q(M_VALID_FF),                // Data output\n         .C(ACLK),                      // Clock input\n         .CE(1'b1),                     // Clock enable input\n         .R(ARESET),                    // Synchronous reset input\n         .D(M_VALID_CMB)                // Data input\n         );\n      \n      end\n      \n      assign EMPTY      = ~M_VALID_I & ~M_VALID_FF;\n      assign M_MESG     = M_MESG_FF;\n      assign M_VALID    = M_VALID_FF;\n      assign M_READY_I  = ( M_READY & M_VALID_FF ) | ~M_VALID_FF;\n      \n    end else begin : NO_FF_OUT\n      \n      assign EMPTY      = ~M_VALID_I;\n      assign M_MESG     = M_MESG_I;\n      assign M_VALID    = M_VALID_I;\n      assign M_READY_I  = M_READY;\n      \n    end\n  endgenerate\n\nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_mask_static #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter         C_VALUE                          = 4'b0,\n                       // Static value to compare against.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] M,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar lut_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 3;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] m_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign m_local        = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = C_VALUE;\n      assign m_local        = M;\n    end\n    \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == \n                              ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[lut_cnt+1]),\n       .CIN   (carry_local[lut_cnt]),\n       .S     (sel[lut_cnt])\n      ); \n      \n    end // end for lut_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_mask #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   input  wire [C_DATA_WIDTH-1:0] M,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar lut_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 2;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] m_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign m_local        = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n      assign m_local        = M;\n    end\n  \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == \n                              ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[lut_cnt+1]),\n       .CIN   (carry_local[lut_cnt]),\n       .S     (sel[lut_cnt])\n      ); \n      \n    end // end for lut_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_sel_mask_static #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter         C_VALUE                          = 4'b0,\n                       // Static value to compare against.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire                    S,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   input  wire [C_DATA_WIDTH-1:0] M,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar lut_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 1;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] m_local;\n  wire [C_FIX_DATA_WIDTH-1:0] v_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign m_local        = {M,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign v_local        = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n      assign m_local        = M;\n      assign v_local        = C_VALUE;\n    end\n    \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==\n                                ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |\n                            ( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==\n                                ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[lut_cnt+1]),\n       .CIN   (carry_local[lut_cnt]),\n       .S     (sel[lut_cnt])\n      ); \n      \n    end // end for lut_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_sel_mask #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire                    S,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   input  wire [C_DATA_WIDTH-1:0] M,\n   input  wire [C_DATA_WIDTH-1:0] V,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar lut_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 1;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] m_local;\n  wire [C_FIX_DATA_WIDTH-1:0] v_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign m_local        = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign v_local        = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n      assign m_local        = M;\n      assign v_local        = V;\n    end\n    \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==\n                                ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |\n                            ( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==\n                                ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &\n                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[lut_cnt+1]),\n       .CIN   (carry_local[lut_cnt]),\n       .S     (sel[lut_cnt])\n      ); \n      \n    end // end for lut_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_sel_static #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter         C_VALUE                          = 4'b0,\n                       // Static value to compare against.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire                    S,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar bit_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 2;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] v_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign v_local        = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n      assign v_local        = C_VALUE;\n    end\n    \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                                v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |\n                            ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                                v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[bit_cnt+1]),\n       .CIN   (carry_local[bit_cnt]),\n       .S     (sel[bit_cnt])\n      ); \n      \n    end // end for bit_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_sel #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire                    S,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   input  wire [C_DATA_WIDTH-1:0] V,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar bit_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 1;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_FIX_DATA_WIDTH-1:0] v_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign v_local        = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n      assign v_local        = V;\n    end\n  \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                                v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |\n                            ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                                v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[bit_cnt+1]),\n       .CIN   (carry_local[bit_cnt]),\n       .S     (sel[bit_cnt])\n      ); \n      \n    end // end for bit_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator_static #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter         C_VALUE                          = 4'b0,\n                       // Static value to compare against.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar bit_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 6;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = C_VALUE;\n    end\n    \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                              b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[bit_cnt+1]),\n       .CIN   (carry_local[bit_cnt]),\n       .S     (sel[bit_cnt])\n      ); \n      \n    end // end for bit_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_comparator #\n  (\n   parameter         C_FAMILY                         = \"virtex6\", \n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_DATA_WIDTH                     = 4\n                       // Data width for comparator.\n   )\n  (\n   input  wire                    CIN,\n   input  wire [C_DATA_WIDTH-1:0] A,\n   input  wire [C_DATA_WIDTH-1:0] B,\n   output wire                    COUT\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar bit_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Bits per LUT for this architecture.\n  localparam integer C_BITS_PER_LUT   = 3;\n  \n  // Constants for packing levels.\n  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n  \n  // \n  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n                                        C_DATA_WIDTH;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  wire [C_FIX_DATA_WIDTH-1:0] a_local;\n  wire [C_FIX_DATA_WIDTH-1:0] b_local;\n  wire [C_NUM_LUT-1:0]        sel;\n  wire [C_NUM_LUT:0]          carry_local;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // \n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    // Assign input to local vectors.\n    assign carry_local[0] = CIN;\n    \n    // Extend input data to fit.\n    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n      assign a_local        = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n      assign b_local        = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n    end else begin : NO_EXTENDED_DATA\n      assign a_local        = A;\n      assign b_local        = B;\n    end\n  \n    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.\n    for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL\n      // Create the local select signal\n      assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n                              b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );\n    \n      // Instantiate each LUT level.\n      generic_baseblocks_v2_1_0_carry_and # \n      (\n       .C_FAMILY(C_FAMILY)\n      ) compare_inst \n      (\n       .COUT  (carry_local[bit_cnt+1]),\n       .CIN   (carry_local[bit_cnt]),\n       .S     (sel[bit_cnt])\n      ); \n      \n    end // end for bit_cnt\n    \n    // Assign output from local vector.\n    assign COUT = carry_local[C_NUM_LUT];\n    \n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized Mux using MUXF7/8.\n//  Any generic_baseblocks_v2_1_0_mux ratio.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   mux_enc\n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_mux_enc #\n  (\n   parameter         C_FAMILY                       = \"rtl\",\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_RATIO                        = 4,\n                       // Mux select ratio. Can be any binary value (>= 1)\n   parameter integer C_SEL_WIDTH                    = 2,\n                       // Log2-ceiling of C_RATIO (>= 1)\n   parameter integer C_DATA_WIDTH                   = 1\n                       // Data width for generic_baseblocks_v2_1_0_comparator (>= 1)\n   )\n  (\n   input  wire [C_SEL_WIDTH-1:0]                    S,\n   input  wire [C_RATIO*C_DATA_WIDTH-1:0]           A,\n   output wire [C_DATA_WIDTH-1:0]                   O,\n   input  wire                                      OE\n   );\n  \n  wire [C_DATA_WIDTH-1:0] o_i;\n  genvar bit_cnt;\n  \n  function [C_DATA_WIDTH-1:0] f_mux\n    (\n     input [C_SEL_WIDTH-1:0] s,\n     input [C_RATIO*C_DATA_WIDTH-1:0] a\n     );\n    integer i;\n    reg [C_RATIO*C_DATA_WIDTH-1:0] carry;\n    begin\n      carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];\n      for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc\n        carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] = \n          carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |\n          ({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);\n      end\n      f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)];\n    end\n  endfunction\n  \n  function [C_DATA_WIDTH-1:0] f_mux4\n    (\n     input [1:0] s,\n     input [4*C_DATA_WIDTH-1:0] a\n     );\n    integer i;\n    reg [4*C_DATA_WIDTH-1:0] carry;\n    begin\n      carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];\n      for (i=1;i<4;i=i+1) begin : gen_carrychain_enc\n        carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] = \n          carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |\n          ({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);\n      end\n      f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3];\n    end\n  endfunction\n  \n  assign O = o_i & {C_DATA_WIDTH{OE}};  // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic)\n  \n  generate\n    if ( C_RATIO < 2 ) begin : gen_bypass\n      assign o_i = A;\n    end else if ( C_FAMILY == \"rtl\" || C_RATIO < 5 ) begin : gen_rtl\n      assign o_i = f_mux(S, A);\n      \n    end else begin : gen_fpga\n      wire [C_DATA_WIDTH-1:0] l;\n      wire [C_DATA_WIDTH-1:0] h;\n      wire [C_DATA_WIDTH-1:0] ll;\n      wire [C_DATA_WIDTH-1:0] lh;\n      wire [C_DATA_WIDTH-1:0] hl;\n      wire [C_DATA_WIDTH-1:0] hh;\n      \n      case (C_RATIO)\n        1, 5, 9, 13: \n          assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        2, 6, 10, 14:\n          assign hh = S[0] ? \n            A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :\n            A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ;\n        3, 7, 11, 15:\n          assign hh = S[1] ? \n            A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :\n            (S[0] ? \n              A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] :\n              A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] );\n        4, 8, 12, 16:\n          assign hh = S[1] ? \n            (S[0] ? \n              A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :\n              A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) :\n            (S[0] ? \n              A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] :\n              A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] );\n        17:\n          assign hh = S[1] ? \n            (S[0] ? \n              A[15*C_DATA_WIDTH +: C_DATA_WIDTH] :\n              A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) :\n            (S[0] ? \n              A[13*C_DATA_WIDTH +: C_DATA_WIDTH] :\n              A[12*C_DATA_WIDTH +: C_DATA_WIDTH] );\n        default:\n          assign hh = 0; \n      endcase\n\n      case (C_RATIO)\n        5, 6, 7, 8: begin\n          assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);\n          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8\n            MUXF7 mux_s2_inst \n            (\n             .I0  (l[bit_cnt]),\n             .I1  (hh[bit_cnt]),\n             .S   (S[2]),\n             .O   (o_i[bit_cnt])\n            ); \n          end\n        end\n          \n        9, 10, 11, 12: begin\n          assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);\n          assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);\n          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12\n            MUXF7 muxf_s2_low_inst \n            (\n             .I0  (ll[bit_cnt]),\n             .I1  (lh[bit_cnt]),\n             .S   (S[2]),\n             .O   (l[bit_cnt])\n            ); \n            MUXF8 muxf_s3_inst \n            (\n             .I0  (l[bit_cnt]),\n             .I1  (hh[bit_cnt]),\n             .S   (S[3]),\n             .O   (o_i[bit_cnt])\n            ); \n          end\n        end\n          \n        13,14,15,16: begin\n          assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);\n          assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);\n          assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);\n          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16\n            MUXF7 muxf_s2_low_inst \n            (\n             .I0  (ll[bit_cnt]),\n             .I1  (lh[bit_cnt]),\n             .S   (S[2]),\n             .O   (l[bit_cnt])\n            ); \n            MUXF7 muxf_s2_hi_inst \n            (\n             .I0  (hl[bit_cnt]),\n             .I1  (hh[bit_cnt]),\n             .S   (S[2]),\n             .O   (h[bit_cnt])\n            );\n          \n            MUXF8 muxf_s3_inst \n            (\n             .I0  (l[bit_cnt]),\n             .I1  (h[bit_cnt]),\n             .S   (S[3]),\n             .O   (o_i[bit_cnt])\n            ); \n          end\n        end\n          \n        17: begin\n          assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);  // 5-input mux\n          assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);\n          assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);\n          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17\n            MUXF7 muxf_s2_low_inst \n            (\n             .I0  (ll[bit_cnt]),\n             .I1  (lh[bit_cnt]),\n             .S   (S[2]),\n             .O   (l[bit_cnt])\n            ); \n            MUXF7 muxf_s2_hi_inst \n            (\n             .I0  (hl[bit_cnt]),\n             .I1  (hh[bit_cnt]),\n             .S   (S[2]),\n             .O   (h[bit_cnt])\n            ); \n            MUXF8 muxf_s3_inst \n            (\n             .I0  (l[bit_cnt]),\n             .I1  (h[bit_cnt]),\n             .S   (S[3]),\n             .O   (o_i[bit_cnt])\n            ); \n          end\n        end\n          \n        default:  // If RATIO > 17, use RTL\n          assign o_i = f_mux(S, A);\n      endcase\n    end  // gen_fpga\n  endgenerate\nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n//  Optimized Mux from 2:1 upto 16:1.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_mux #\n  (\n   parameter         C_FAMILY                         = \"rtl\",\n                       // FPGA Family. Current version: virtex6 or spartan6.\n   parameter integer C_SEL_WIDTH                      = 4,\n                       // Data width for comparator.\n   parameter integer C_DATA_WIDTH                     = 2\n                       // Data width for comparator.\n   )\n  (\n   input  wire [C_SEL_WIDTH-1:0]                    S,\n   input  wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0]  A,\n   output wire [C_DATA_WIDTH-1:0]                   O\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Generate variable for bit vector.\n  genvar bit_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiate or use RTL code\n  /////////////////////////////////////////////////////////////////////////////\n  \n  generate\n    if ( C_FAMILY == \"rtl\" || C_SEL_WIDTH < 3 ) begin : USE_RTL\n      assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH];\n      \n    end else begin : USE_FPGA\n      \n      wire [C_DATA_WIDTH-1:0] C;\n      wire [C_DATA_WIDTH-1:0] D;\n      \n      // Lower half recursively.\n      generic_baseblocks_v2_1_0_mux # \n      (\n       .C_FAMILY      (C_FAMILY),\n       .C_SEL_WIDTH   (C_SEL_WIDTH-1),\n       .C_DATA_WIDTH  (C_DATA_WIDTH)\n      ) mux_c_inst \n      (\n       .S   (S[C_SEL_WIDTH-2:0]),\n       .A   (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]),\n       .O   (C)\n      ); \n      \n      // Upper half recursively.\n      generic_baseblocks_v2_1_0_mux # \n      (\n       .C_FAMILY      (C_FAMILY),\n       .C_SEL_WIDTH   (C_SEL_WIDTH-1),\n       .C_DATA_WIDTH  (C_DATA_WIDTH)\n      ) mux_d_inst \n      (\n       .S   (S[C_SEL_WIDTH-2:0]),\n       .A   (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]),\n       .O   (D)\n      ); \n      \n      // Generate instantiated generic_baseblocks_v2_1_0_mux components as required.\n      for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM\n        if ( C_SEL_WIDTH == 4 ) begin : USE_F8\n        \n          MUXF8 muxf8_inst \n          (\n           .I0  (C[bit_cnt]),\n           .I1  (D[bit_cnt]),\n           .S   (S[C_SEL_WIDTH-1]),\n           .O   (O[bit_cnt])\n          ); \n          \n        end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7\n      \n          MUXF7 muxf7_inst \n          (\n           .I0  (C[bit_cnt]),\n           .I1  (D[bit_cnt]),\n           .S   (S[C_SEL_WIDTH-1]),\n           .O   (O[bit_cnt])\n          ); \n          \n        end // C_SEL_WIDTH\n      end // end for bit_cnt\n    \n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: nto1_mux.v\n//\n// Description: N:1 MUX based on either binary-encoded or one-hot select input\n//   One-hot mode does not protect against multiple active SEL_ONEHOT inputs.\n//   Note: All port signals changed to all-upper-case (w.r.t. prior version).\n//\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule generic_baseblocks_v2_1_0_nto1_mux #\n  (\n   parameter integer C_RATIO         =  1,  // Range: >=1\n   parameter integer C_SEL_WIDTH     =  1,  // Range: >=1; recommended: ceil_log2(C_RATIO)\n   parameter integer C_DATAOUT_WIDTH =  1,  // Range: >=1\n   parameter integer C_ONEHOT        =  0   // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)\n   )\n  (\n   input  wire [C_RATIO-1:0]                 SEL_ONEHOT,  // One-hot generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=1)\n   input  wire [C_SEL_WIDTH-1:0]             SEL,         // Binary-encoded generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=0)\n   input  wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN,          // Data input array (num_selections x data_width)\n   output wire [C_DATAOUT_WIDTH-1:0]         OUT          // Data output vector\n   );\n\n  wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;\n  genvar i;\n  \n  generate\n    if (C_ONEHOT == 0) begin : gen_encoded\n      assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1'b1:1'b0}} & IN[C_DATAOUT_WIDTH-1:0];\n      for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc\n        assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] = \n               carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |\n               {C_DATAOUT_WIDTH{(SEL==i)?1'b1:1'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];\n      end\n    end else begin : gen_onehot\n      assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];\n      for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot\n        assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] = \n               carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |\n               {C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];\n      end\n    end\n  endgenerate\n  assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:\n                     C_DATAOUT_WIDTH*(C_RATIO-1)];\nendmodule\n\n`default_nettype wire\n\n\n", "num_lines": 2931}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: addr_arbiter_sasd.v\n//\n// Description: \n//   Hybrid priority + round-robin arbiter.\n//   Read & write requests combined (read preferred) at each slot\n//   Muxes AR and AW channel payload inputs based on arbitration results.\n//-----------------------------------------------------------------------------\n//\n// Structure:\n//    addr_arbiter_sasd\n//      mux_enc\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_addr_arbiter_sasd #\n  (\n   parameter         C_FAMILY                         = \"none\", \n   parameter integer C_NUM_S                = 1, \n   parameter integer C_NUM_S_LOG                = 1, \n   parameter integer C_AMESG_WIDTH                 = 1, \n   parameter         C_GRANT_ENC        = 0,\n   parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY             = {C_NUM_S{32'h00000000}}\n                       // Arbitration priority among each SI slot. \n                       // Higher values indicate higher priority.\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 'h0-'hF.\n   )\n  (\n   // Global Signals\n   input  wire                                      ACLK,\n   input  wire                                      ARESET,\n   // Slave Ports\n   input  wire [C_NUM_S*C_AMESG_WIDTH-1:0]  S_AWMESG,\n   input  wire [C_NUM_S*C_AMESG_WIDTH-1:0]  S_ARMESG,\n   input  wire [C_NUM_S-1:0]                S_AWVALID,\n   output wire [C_NUM_S-1:0]                S_AWREADY,\n   input  wire [C_NUM_S-1:0]                S_ARVALID,\n   output wire [C_NUM_S-1:0]                S_ARREADY,\n   // Master Ports\n   output wire [C_AMESG_WIDTH-1:0]          M_AMESG,\n   output wire [C_NUM_S_LOG-1:0]            M_GRANT_ENC,\n   output wire [C_NUM_S-1:0]                M_GRANT_HOT,\n   output wire                              M_GRANT_RNW,\n   output wire                              M_GRANT_ANY,\n   output wire                              M_AWVALID,\n   input  wire                              M_AWREADY,\n   output wire                              M_ARVALID,\n   input  wire                              M_ARREADY\n   );\n   \n  // Generates a mask for all input slots that are priority based\n  function [C_NUM_S-1:0] f_prio_mask\n    (\n      input integer null_arg\n    );\n    reg   [C_NUM_S-1:0]            mask;\n    integer                        i;    \n    begin\n      mask = 0;    \n      for (i=0; i < C_NUM_S; i=i+1) begin\n        mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0);\n      end \n      f_prio_mask = mask;\n    end   \n  endfunction\n  \n  // Convert 16-bit one-hot to 4-bit binary\n  function [3:0] f_hot2enc\n    (\n      input [15:0]  one_hot\n    );\n    begin\n      f_hot2enc[0] = |(one_hot & 16'b1010101010101010);\n      f_hot2enc[1] = |(one_hot & 16'b1100110011001100);\n      f_hot2enc[2] = |(one_hot & 16'b1111000011110000);\n      f_hot2enc[3] = |(one_hot & 16'b1111111100000000);\n    end\n  endfunction\n\n  localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0);\n\n  reg                     m_valid_i = 1'b0;\n  reg [C_NUM_S-1:0]       s_ready_i = 0;\n  reg [C_NUM_S-1:0]       s_awvalid_reg = 0;\n  reg [C_NUM_S-1:0]       s_arvalid_reg = 0;\n  wire [15:0]             s_avalid;\n  wire                    m_aready;\n  wire [C_NUM_S-1:0]      rnw;\n  reg                     grant_rnw;\n  reg [C_NUM_S_LOG-1:0]   m_grant_enc_i;\n  reg [C_NUM_S-1:0]       m_grant_hot_i; \n  reg [C_NUM_S-1:0]       last_rr_hot;\n  reg                     any_grant;\n  reg                     any_prio;\n  reg [C_NUM_S-1:0]       which_prio_hot;\n  reg [C_NUM_S_LOG-1:0]   which_prio_enc;          \n  reg [4:0]               current_highest;\n  reg [15:0]              next_prio_hot;\n  reg [C_NUM_S_LOG-1:0]   next_prio_enc;    \n  reg                     found_prio;\n  wire [C_NUM_S-1:0]      valid_rr;\n  reg [15:0]              next_rr_hot;\n  reg [C_NUM_S_LOG-1:0]   next_rr_enc;    \n  reg [C_NUM_S*C_NUM_S-1:0] carry_rr;\n  reg [C_NUM_S*C_NUM_S-1:0] mask_rr;\n  reg                     found_rr;\n  wire [C_NUM_S-1:0]      next_hot;\n  wire [C_NUM_S_LOG-1:0]  next_enc;    \n  integer                 i;\n  wire  [C_AMESG_WIDTH-1:0] amesg_mux;\n  reg   [C_AMESG_WIDTH-1:0] m_amesg_i;\n  wire [C_NUM_S*C_AMESG_WIDTH-1:0] s_amesg;\n  genvar                  gen_si;\n\n  always @(posedge ACLK) begin\n    if (ARESET) begin\n      s_awvalid_reg <= 0;\n      s_arvalid_reg <= 0;\n    end else if (|s_ready_i) begin\n      s_awvalid_reg <= 0;\n      s_arvalid_reg <= 0;\n    end else begin\n      s_arvalid_reg <= S_ARVALID & ~s_awvalid_reg;\n      s_awvalid_reg <= S_AWVALID & ~s_arvalid_reg & (~S_ARVALID | s_awvalid_reg);\n    end\n  end\n  \n  assign s_avalid = S_AWVALID | S_ARVALID;\n  assign M_AWVALID = m_valid_i & ~grant_rnw;\n  assign M_ARVALID = m_valid_i & grant_rnw;\n  assign S_AWREADY = s_ready_i & {C_NUM_S{~grant_rnw}};\n  assign S_ARREADY = s_ready_i & {C_NUM_S{grant_rnw}};\n  assign M_GRANT_ENC = C_GRANT_ENC ? m_grant_enc_i : 0;\n  assign M_GRANT_HOT = m_grant_hot_i;\n  assign M_GRANT_RNW = grant_rnw;\n  assign rnw = S_ARVALID & ~s_awvalid_reg;\n  assign M_AMESG = m_amesg_i;\n  assign m_aready = grant_rnw ? M_ARREADY : M_AWREADY;\n  \n  generate\n    for (gen_si=0; gen_si<C_NUM_S; gen_si=gen_si+1) begin : gen_mesg_mux\n      assign s_amesg[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] = rnw[gen_si] ? S_ARMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] : S_AWMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH];\n    end  // gen_mesg_mux\n         \n    if (C_NUM_S>1) begin : gen_arbiter\n    \n      /////////////////////////////////////////////////////////////////////////////\n      // Grant a new request when there is none still pending.\n      // If no qualified requests found, de-assert M_VALID.\n      /////////////////////////////////////////////////////////////////////////////\n      \n      assign M_GRANT_ANY = any_grant;\n      assign next_hot = found_prio ? next_prio_hot : next_rr_hot;\n      assign next_enc = found_prio ? next_prio_enc : next_rr_enc;\n      \n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          m_valid_i <= 0;\n          s_ready_i <= 0;\n          m_grant_hot_i <= 0;\n          m_grant_enc_i <= 0;\n          any_grant <= 1'b0;\n          last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};\n          grant_rnw <= 1'b0;\n        end else begin\n          s_ready_i <= 0;\n          if (m_valid_i) begin\n            // Stall 1 cycle after each master-side completion.\n            if (m_aready) begin  // Master-side completion\n              m_valid_i <= 1'b0;\n              m_grant_hot_i <= 0;\n              any_grant <= 1'b0;\n            end\n          end else if (any_grant) begin\n            m_valid_i <= 1'b1;\n            s_ready_i <= m_grant_hot_i;  // Assert S_AW/READY for 1 cycle to complete SI address transfer\n          end else begin\n            if (found_prio | found_rr) begin\n              m_grant_hot_i <= next_hot;\n              m_grant_enc_i <= next_enc;\n              any_grant <= 1'b1;\n              grant_rnw <= |(rnw & next_hot);\n              if (~found_prio) begin\n                last_rr_hot <= next_rr_hot;\n              end\n            end\n          end\n        end\n      end\n    \n      /////////////////////////////////////////////////////////////////////////////\n      // Fixed Priority arbiter\n      // Selects next request to grant from among inputs with PRIO > 0, if any.\n      /////////////////////////////////////////////////////////////////////////////\n      \n      always @ * begin : ALG_PRIO\n        integer ip;\n        any_prio = 1'b0;\n        which_prio_hot = 0;        \n        which_prio_enc = 0;    \n        current_highest = 0;    \n        for (ip=0; ip < C_NUM_S; ip=ip+1) begin\n          if (P_PRIO_MASK[ip] & ({1'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest)) begin\n            if (s_avalid[ip]) begin\n              current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4];\n              any_prio = 1'b1;\n              which_prio_hot = 1'b1 << ip;\n              which_prio_enc = ip;\n            end\n          end   \n        end\n        found_prio = any_prio;\n        next_prio_hot = which_prio_hot;\n        next_prio_enc = which_prio_enc;\n      end\n     \n      /////////////////////////////////////////////////////////////////////////////\n      // Round-robin arbiter\n      // Selects next request to grant from among inputs with PRIO = 0, if any.\n      /////////////////////////////////////////////////////////////////////////////\n      \n      assign valid_rr = ~P_PRIO_MASK & s_avalid;\n      \n      always @ * begin : ALG_RR\n        integer ir, jr, nr;\n        next_rr_hot = 0;\n        for (ir=0;ir<C_NUM_S;ir=ir+1) begin\n          nr = (ir>0) ? (ir-1) : (C_NUM_S-1);\n          carry_rr[ir*C_NUM_S] = last_rr_hot[nr];\n          mask_rr[ir*C_NUM_S] = ~valid_rr[nr];\n          for (jr=1;jr<C_NUM_S;jr=jr+1) begin\n            nr = (ir-jr > 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1);\n            carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]);\n            if (jr < C_NUM_S-1) begin\n              mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr];\n            end\n          end   \n          next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1];\n        end\n        next_rr_enc = f_hot2enc(next_rr_hot);\n        found_rr = |(next_rr_hot);\n      end\n  \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_S),\n         .C_SEL_WIDTH   (C_NUM_S_LOG),\n         .C_DATA_WIDTH  (C_AMESG_WIDTH)\n        ) si_amesg_mux_inst \n        (\n         .S   (next_enc),\n         .A   (s_amesg),\n         .O   (amesg_mux),\n         .OE  (1'b1)\n        ); \n        \n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          m_amesg_i <= 0;\n        end else if (~any_grant) begin\n          m_amesg_i <= amesg_mux;\n        end\n      end\n    \n    end else begin : gen_no_arbiter\n      \n      assign M_GRANT_ANY = m_grant_hot_i;\n\n      always @ (posedge ACLK) begin\n        if (ARESET) begin\n          m_valid_i <= 1'b0;\n          s_ready_i <= 1'b0;\n          m_grant_enc_i <= 0;\n          m_grant_hot_i <= 1'b0;\n          grant_rnw <= 1'b0;\n        end else begin\n          s_ready_i <= 1'b0;\n          if (m_valid_i) begin\n            if (m_aready) begin\n              m_valid_i <= 1'b0;\n              m_grant_hot_i <= 1'b0;\n            end\n          end else if (m_grant_hot_i) begin\n            m_valid_i <= 1'b1;\n            s_ready_i[0] <= 1'b1;  // Assert S_AW/READY for 1 cycle to complete SI address transfer\n          end else if (s_avalid[0]) begin\n            m_grant_hot_i <= 1'b1;\n            grant_rnw <= rnw[0];\n          end\n        end\n      end\n      \n      always @ (posedge ACLK) begin\n        if (ARESET) begin\n          m_amesg_i <= 0;\n        end else if (~m_grant_hot_i) begin\n          m_amesg_i <= s_amesg;\n        end\n      end\n    \n    end  // gen_arbiter\n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: addr_arbiter.v\n//\n// Description: \n//   Instantiates generic priority encoder.\n//   Each request is qualified if its target has not reached its issuing limit.\n//   Muxes mesg and target inputs based on arbitration results.\n//-----------------------------------------------------------------------------\n//\n// Structure:\n//    addr_arbiter\n//      mux_enc\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_addr_arbiter #\n  (\n   parameter         C_FAMILY                         = \"none\", \n   parameter integer C_NUM_S                = 1, \n   parameter integer C_NUM_S_LOG                = 1, \n   parameter integer C_NUM_M               = 1, \n   parameter integer C_MESG_WIDTH                 = 1, \n   parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY             = {C_NUM_S{32'h00000000}}\n                       // Arbitration priority among each SI slot. \n                       // Higher values indicate higher priority.\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 'h0-'hF.\n   )\n  (\n   // Global Signals\n   input  wire                                      ACLK,\n   input  wire                                      ARESET,\n   // Slave Ports\n   input  wire [C_NUM_S*C_MESG_WIDTH-1:0]  S_MESG,\n   input  wire [C_NUM_S*C_NUM_M-1:0]                S_TARGET_HOT,\n   input  wire [C_NUM_S-1:0]                S_VALID,\n   input  wire [C_NUM_S-1:0]                S_VALID_QUAL,\n   output wire [C_NUM_S-1:0]                S_READY,\n   // Master Ports\n   output wire [C_MESG_WIDTH-1:0]                    M_MESG,\n   output wire [C_NUM_M-1:0]                           M_TARGET_HOT,\n   output wire [C_NUM_S_LOG-1:0]                      M_GRANT_ENC,\n   output wire                                        M_VALID,\n   input  wire                                        M_READY,\n   // Sideband input\n   input  wire [C_NUM_M-1:0]                ISSUING_LIMIT\n   );\n   \n  // Generates a mask for all input slots that are priority based\n  function [C_NUM_S-1:0] f_prio_mask\n    (\n      input integer null_arg\n    );\n    reg   [C_NUM_S-1:0]            mask;\n    integer                        i;    \n    begin\n      mask = 0;    \n      for (i=0; i < C_NUM_S; i=i+1) begin\n        mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0);\n      end \n      f_prio_mask = mask;\n    end   \n  endfunction\n  \n  // Convert 16-bit one-hot to 4-bit binary\n  function [3:0] f_hot2enc\n    (\n      input [15:0]  one_hot\n    );\n    begin\n      f_hot2enc[0] = |(one_hot & 16'b1010101010101010);\n      f_hot2enc[1] = |(one_hot & 16'b1100110011001100);\n      f_hot2enc[2] = |(one_hot & 16'b1111000011110000);\n      f_hot2enc[3] = |(one_hot & 16'b1111111100000000);\n    end\n  endfunction\n\n  localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0);\n\n  reg                     m_valid_i = 1'b0;\n  reg [C_NUM_S-1:0]       s_ready_i = 0;\n  reg [C_NUM_S-1:0]       qual_reg;\n  reg [C_NUM_S-1:0]       grant_hot; \n  reg [C_NUM_S-1:0]       last_rr_hot;\n  reg                     any_grant;\n  reg                     any_prio;\n  reg                     found_prio;\n  reg [C_NUM_S-1:0]       which_prio_hot;\n  reg [C_NUM_S-1:0]       next_prio_hot;\n  reg [C_NUM_S_LOG-1:0]   which_prio_enc;          \n  reg [C_NUM_S_LOG-1:0]   next_prio_enc;    \n  reg [4:0]               current_highest;\n  wire [C_NUM_S-1:0]      valid_rr;\n  reg [15:0]              next_rr_hot;\n  reg [C_NUM_S_LOG-1:0]   next_rr_enc;    \n  reg [C_NUM_S*C_NUM_S-1:0] carry_rr;\n  reg [C_NUM_S*C_NUM_S-1:0] mask_rr;\n  reg                     found_rr;\n  wire [C_NUM_S-1:0]      next_hot;\n  wire [C_NUM_S_LOG-1:0]  next_enc;    \n  reg                     prio_stall;\n  integer                 i;\n  wire [C_NUM_S-1:0]      valid_qual_i;\n  reg  [C_NUM_S_LOG-1:0]  m_grant_enc_i;\n  reg  [C_NUM_M-1:0]      m_target_hot_i;\n  wire [C_NUM_M-1:0]      m_target_hot_mux;\n  reg  [C_MESG_WIDTH-1:0] m_mesg_i;\n  wire [C_MESG_WIDTH-1:0] m_mesg_mux;\n  genvar                  gen_si;\n\n  assign M_VALID = m_valid_i;\n  assign S_READY = s_ready_i;\n  assign M_GRANT_ENC = m_grant_enc_i;\n  assign M_MESG = m_mesg_i;\n  assign M_TARGET_HOT = m_target_hot_i;\n  \n  generate\n    if (C_NUM_S>1) begin : gen_arbiter\n      \n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          qual_reg <= 0;\n        end else begin \n          qual_reg <= valid_qual_i | ~S_VALID; // Don't disqualify when bus not VALID (valid_qual_i would be garbage)\n        end\n      end\n    \n      for (gen_si=0; gen_si<C_NUM_S; gen_si=gen_si+1) begin : gen_req_qual\n        assign valid_qual_i[gen_si] = S_VALID_QUAL[gen_si] & (|(S_TARGET_HOT[gen_si*C_NUM_M+:C_NUM_M] & ~ISSUING_LIMIT));\n      end\n    \n      /////////////////////////////////////////////////////////////////////////////\n      // Grant a new request when there is none still pending.\n      // If no qualified requests found, de-assert M_VALID.\n      /////////////////////////////////////////////////////////////////////////////\n      \n      assign next_hot = found_prio ? next_prio_hot : next_rr_hot;\n      assign next_enc = found_prio ? next_prio_enc : next_rr_enc;\n      \n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          m_valid_i <= 0;\n          s_ready_i <= 0;\n          grant_hot <= 0;\n          any_grant <= 1'b0;\n          m_grant_enc_i <= 0;\n          last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};\n          m_target_hot_i <= 0;\n        end else begin\n          s_ready_i <= 0;\n          if (m_valid_i) begin\n            // Stall 1 cycle after each master-side completion.\n            if (M_READY) begin  // Master-side completion\n              m_valid_i <= 1'b0;\n              grant_hot <= 0;\n              any_grant <= 1'b0;\n            end\n          end else if (any_grant) begin\n            m_valid_i <= 1'b1;\n            s_ready_i <= grant_hot;  // Assert S_AW/READY for 1 cycle to complete SI address transfer (regardless of M_AREADY)\n          end else begin\n            if ((found_prio | found_rr) & ~prio_stall) begin\n              // Waste 1 cycle and re-arbitrate if target of highest prio hit issuing limit in previous cycle (valid_qual_i).\n              if (|(next_hot & valid_qual_i)) begin  \n                grant_hot <= next_hot;\n                m_grant_enc_i <= next_enc;\n                any_grant <= 1'b1;\n                if (~found_prio) begin\n                  last_rr_hot <= next_rr_hot;\n                end\n                m_target_hot_i <= m_target_hot_mux;\n              end\n            end\n          end\n        end\n      end\n    \n      /////////////////////////////////////////////////////////////////////////////\n      // Fixed Priority arbiter\n      // Selects next request to grant from among inputs with PRIO > 0, if any.\n      /////////////////////////////////////////////////////////////////////////////\n          \n      always @ * begin : ALG_PRIO\n        integer ip;\n        any_prio = 1'b0;\n        prio_stall = 1'b0;\n        which_prio_hot = 0;        \n        which_prio_enc = 0;    \n        current_highest = 0;    \n        for (ip=0; ip < C_NUM_S; ip=ip+1) begin\n          // Disqualify slot if target hit issuing limit (pass to lower prio slot).\n          if (P_PRIO_MASK[ip] & S_VALID[ip] & qual_reg[ip]) begin\n            if ({1'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest) begin\n              current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4];\n              // Stall 1 cycle when highest prio is recovering from SI-side handshake.\n              // (Do not allow lower-prio slot to win arbitration.)\n              if (s_ready_i[ip]) begin\n                any_prio = 1'b0;\n                prio_stall = 1'b1;\n                which_prio_hot = 0;\n                which_prio_enc = 0;\n              end else begin\n                any_prio = 1'b1;\n                which_prio_hot = 1'b1 << ip;\n                which_prio_enc = ip;\n              end\n            end\n          end   \n        end\n        found_prio = any_prio;\n        next_prio_hot = which_prio_hot;\n        next_prio_enc = which_prio_enc;\n      end\n     \n      /////////////////////////////////////////////////////////////////////////////\n      // Round-robin arbiter\n      // Selects next request to grant from among inputs with PRIO = 0, if any.\n      /////////////////////////////////////////////////////////////////////////////\n      \n      // Disqualify slot if target hit issuing limit 2 or more cycles earlier (pass to next RR slot).\n      // Disqualify for 1 cycle a slot that is recovering from SI-side handshake (s_ready_i),\n      //   and allow arbitration to pass to any other RR requester.\n      assign valid_rr = ~P_PRIO_MASK & S_VALID & ~s_ready_i & qual_reg;\n      \n      always @ * begin : ALG_RR\n        integer ir, jr, nr;\n        next_rr_hot = 0;\n        for (ir=0;ir<C_NUM_S;ir=ir+1) begin\n          nr = (ir>0) ? (ir-1) : (C_NUM_S-1);\n          carry_rr[ir*C_NUM_S] = last_rr_hot[nr];\n          mask_rr[ir*C_NUM_S] = ~valid_rr[nr];\n          for (jr=1;jr<C_NUM_S;jr=jr+1) begin\n            nr = (ir-jr > 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1);\n            carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]);\n            if (jr < C_NUM_S-1) begin\n              mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr];\n            end\n          end   \n          next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1];\n        end\n        next_rr_enc = f_hot2enc(next_rr_hot);\n        found_rr = |(next_rr_hot);\n      end\n  \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_S),\n         .C_SEL_WIDTH   (C_NUM_S_LOG),\n         .C_DATA_WIDTH  (C_MESG_WIDTH)\n        ) mux_mesg \n        (\n         .S   (m_grant_enc_i),\n         .A   (S_MESG),\n         .O   (m_mesg_mux),\n         .OE  (1'b1)\n        ); \n        \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_S),\n         .C_SEL_WIDTH   (C_NUM_S_LOG),\n         .C_DATA_WIDTH  (C_NUM_M)\n        ) si_amesg_mux_inst \n        (\n         .S   (next_enc),\n         .A   (S_TARGET_HOT),\n         .O   (m_target_hot_mux),\n         .OE  (1'b1)\n        ); \n        \n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          m_mesg_i <= 0;\n        end else if (~m_valid_i) begin\n          m_mesg_i <= m_mesg_mux;\n        end\n      end\n    \n    end else begin : gen_no_arbiter\n      \n      assign valid_qual_i = S_VALID_QUAL & |(S_TARGET_HOT & ~ISSUING_LIMIT);\n      \n      always @ (posedge ACLK) begin\n        if (ARESET) begin\n          m_valid_i <= 1'b0;\n          s_ready_i <= 1'b0;\n          m_grant_enc_i <= 0;\n        end else begin\n          s_ready_i <= 1'b0;\n          if (m_valid_i) begin\n            if (M_READY) begin\n              m_valid_i <= 1'b0;\n            end\n          end else if (S_VALID[0] & valid_qual_i[0] & ~s_ready_i) begin\n            m_valid_i <= 1'b1;\n            s_ready_i <= 1'b1;\n            m_target_hot_i <= S_TARGET_HOT;\n          end\n        end\n      end\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          m_mesg_i <= 0;\n        end else if (~m_valid_i) begin\n          m_mesg_i <= S_MESG;\n        end\n      end\n      \n      \n    end  // gen_arbiter\n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: Addr Decoder\n// Each received address is compared to base and high address pairs for each \n//   of a set of decode targets. \n// The matching target's index (if any) is output combinatorially.\n// If the decode is successful (matches any target), the MATCH output is asserted.\n// For each target, a set of alternative address ranges may be specified.\n// The base and high address pairs are formatted as a pair of 2-dimensional arrays,\n//   alternative address ranges iterate within each target.\n// The alternative range which matches the address is also output as REGION.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   addr_decoder\n//      comparator_static\n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_addr_decoder #\n  (\n   parameter         C_FAMILY          = \"none\",\n   parameter integer C_NUM_TARGETS     = 2,  // Number of decode targets = [1:16]\n   parameter integer C_NUM_TARGETS_LOG = 1,  // Log2(C_NUM_TARGETS)\n   parameter integer C_NUM_RANGES      = 1, // Number of alternative ranges that\n                                             //    can match each target [1:16]\n   parameter integer C_ADDR_WIDTH      = 32, // Width of decoder operand and of\n                                             //   each base and high address [2:64]\n   parameter integer C_TARGET_ENC      = 0,  // Enable encoded target output\n   parameter integer C_TARGET_HOT      = 1,  // Enable 1-hot target output\n   parameter integer C_REGION_ENC      = 0,   // Enable REGION output\n   parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}}, \n   parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}}, \n   parameter [C_NUM_TARGETS:0]    C_TARGET_QUAL                 = {C_NUM_TARGETS{1'b1}},\n                       // Indicates whether each target has connectivity.\n                       // Format: C_NUM_TARGETS{Bit1}.\n   parameter integer   C_RESOLUTION                 = 0,\n                       // Number of low-order ADDR bits that can be ignored when decoding.\n   parameter integer   C_COMPARATOR_THRESHOLD       = 6\n                       // Number of decoded ADDR bits above which will implement comparator_static.\n   )\n  (\n   input  wire [C_ADDR_WIDTH-1:0]      ADDR,        // Decoder input operand\n   output wire [C_NUM_TARGETS-1:0]     TARGET_HOT,  // Target matching address (1-hot)\n   output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC,  // Target matching address (encoded)\n   output wire                         MATCH,       // Decode successful\n   output wire [3:0]                   REGION      // Range within target matching address (encoded)\n   );\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Variables for generating parameter controlled instances.\n  genvar target_cnt;\n  genvar region_cnt;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Function to detect addrs is in the addressable range.\n  // Only compare 4KB page address (ignore low-order 12 bits)\n  function  decode_address;\n    input [C_ADDR_WIDTH-1:0] base, high, addr;\n    reg   [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask;\n    reg   [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page;\n    reg   [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page;\n    reg   [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page;\n  begin\n    addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];\n    base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];\n    high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];\n    if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin\n      decode_address = 1'b0;\n    end else begin\n      mask  = base_page ^ high_page;\n      if ( (base_page & ~mask) == (addr_page & ~mask) ) begin\n        decode_address = 1'b1;\n      end else begin\n        decode_address = 1'b0;\n      end\n    end\n  end\n  endfunction\n  \n  // Generates a binary coded from onehotone encoded\n  function [3:0] f_hot2enc\n    (\n      input [15:0]  one_hot\n    );\n    begin\n      f_hot2enc[0] = |(one_hot & 16'b1010101010101010);\n      f_hot2enc[1] = |(one_hot & 16'b1100110011001100);\n      f_hot2enc[2] = |(one_hot & 16'b1111000011110000);\n      f_hot2enc[3] = |(one_hot & 16'b1111111100000000);\n    end\n  endfunction\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  wire [C_NUM_TARGETS-1:0]              TARGET_HOT_I;     // Target matching address (1-hot).\n  wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT;      // For address hit (1-hot).\n  wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG;  // For address hit (1-hot).\n  wire [C_NUM_RANGES-1:0]               REGION_HOT;       // Reginon matching address (1-hot).\n  wire [3:0]                            TARGET_ENC_I;     // Internal version of encoded hit. \n  /////////////////////////////////////////////////////////////////////////////\n  // Generate detection per region per target.\n  generate\n    for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target\n      for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region\n        // Detect if this is an address hit (including used region decoding).\n        if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static\n          if (C_TARGET_QUAL[target_cnt] &&\n              ((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) ||\n               (C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range\n            generic_baseblocks_v2_1_0_comparator_static #\n            (\n            .C_FAMILY(\"rtl\"),\n            .C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]),\n            .C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION)\n            ) addr_decode_comparator\n            (\n            .CIN(1'b1),\n            .A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] &\n              ~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^\n                C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])),\n            .COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt])\n            );\n          end else begin : gen_null_range\n            assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0;\n          end\n        end else begin : gen_no_comparator_static\n          assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ? \n                                    decode_address(\n                                      C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],\n                                      C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],\n                                      ADDR)\n                                    : 1'b0;\n        end  // gen_comparator_static\n        assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt];\n      end  // gen_region\n      \n      // All regions are non-overlapping\n      // => Or all the region detections for this target to determine if it is a hit.\n      assign TARGET_HOT_I[target_cnt]  = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES];\n    end  // gen_target\n    \n    for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region_or\n      assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS];\n    end  // gen_region_or\n  endgenerate\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // All regions are non-overlapping\n  // => Or all the target hit detections if it is a match.\n  assign MATCH = | TARGET_HOT_I;\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Assign conditional onehot target output signal.\n  generate\n    if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT\n      assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1;\n    end else begin : NO_TARGET_ONEHOT\n      assign TARGET_HOT = {C_NUM_TARGETS{1'b0}};\n    end\n  endgenerate\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Assign conditional encoded target output signal.\n  generate\n    if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED\n      assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I);\n      assign TARGET_ENC   = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0];\n    end else begin : NO_TARGET_ENCODED\n      assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}};\n    end\n  endgenerate\n  \n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Assign conditional encoded region output signal.\n  generate\n    if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED\n      assign REGION = f_hot2enc(REGION_HOT);\n    end else begin : NO_REGION_ENCODED\n      assign REGION = 4'b0;\n    end\n  endgenerate\n  \n  \nendmodule\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Round-Robin Arbiter for R and B channel responses\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    arbiter_resp\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_arbiter_resp #\n  (\n   parameter         C_FAMILY       = \"none\",\n   parameter integer C_NUM_S        = 4,      // Number of requesting Slave ports = [2:16]\n   parameter integer C_NUM_S_LOG    = 2,      // Log2(C_NUM_S)\n   parameter integer C_GRANT_ENC    = 0,      // Enable encoded grant output\n   parameter integer C_GRANT_HOT    = 1       // Enable 1-hot grant output\n   )\n  (\n   // Global Inputs\n   input  wire                     ACLK,\n   input  wire                     ARESET,\n   // Slave  Ports\n   input  wire [C_NUM_S-1:0]       S_VALID,      // Request from each slave\n   output wire [C_NUM_S-1:0]       S_READY,      // Grant response to each slave\n   // Master Ports\n   output wire [C_NUM_S_LOG-1:0]   M_GRANT_ENC,  // Granted slave index (encoded)\n   output wire [C_NUM_S-1:0]       M_GRANT_HOT,  // Granted slave index (1-hot)\n   output wire                     M_VALID,      // Grant event\n   input  wire                     M_READY\n   );\n\n  // Generates a binary coded from onehotone encoded\n  function [4:0] f_hot2enc\n    (\n      input [16:0]  one_hot\n    );\n    begin\n      f_hot2enc[0] = |(one_hot & 17'b01010101010101010);\n      f_hot2enc[1] = |(one_hot & 17'b01100110011001100);\n      f_hot2enc[2] = |(one_hot & 17'b01111000011110000);\n      f_hot2enc[3] = |(one_hot & 17'b01111111100000000);\n      f_hot2enc[4] = |(one_hot & 17'b10000000000000000);\n    end\n  endfunction\n\n  (* use_clock_enable = \"yes\" *)\n  reg [C_NUM_S-1:0]      chosen = 0;\n  \n  wire [C_NUM_S-1:0]     grant_hot; \n  wire                   master_selected; \n  wire                   active_master;\n  wire                   need_arbitration;\n  wire                   m_valid_i;\n  wire [C_NUM_S-1:0]     s_ready_i;\n  wire                   access_done;\n  reg [C_NUM_S-1:0]      last_rr_hot;\n  wire [C_NUM_S-1:0]     valid_rr;\n  reg [C_NUM_S-1:0]      next_rr_hot;\n  reg [C_NUM_S*C_NUM_S-1:0] carry_rr;\n  reg [C_NUM_S*C_NUM_S-1:0] mask_rr;\n  integer                 i;\n  integer                 j;\n  integer                 n;\n  \n  /////////////////////////////////////////////////////////////////////////////\n  //   \n  // Implementation of the arbiter outputs independant of arbitration\n  //\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Mask the current requests with the chosen master\n  assign grant_hot        = chosen & S_VALID;\n\n  // See if we have a selected master\n  assign master_selected  = |grant_hot[0+:C_NUM_S];\n\n  // See if we have current requests\n  assign active_master    = |S_VALID;\n\n  // Access is completed\n  assign access_done = m_valid_i & M_READY;\n  \n  // Need to handle if we drive S_ready combinatorial and without an IDLE state\n\n  // Drive S_READY on the master who has been chosen when we get a M_READY\n  assign s_ready_i = {C_NUM_S{M_READY}} & grant_hot[0+:C_NUM_S];\n\n  // Drive M_VALID if we have a selected master\n  assign m_valid_i = master_selected;\n                \n  // If we have request and not a selected master, we need to arbitrate a new chosen \n  assign need_arbitration = (active_master & ~master_selected) | access_done;\n\n  // need internal signals of the output signals\n  assign M_VALID = m_valid_i;\n  assign S_READY = s_ready_i;\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Assign conditional onehot target output signal.\n  assign M_GRANT_HOT = (C_GRANT_HOT == 1) ? grant_hot[0+:C_NUM_S] : {C_NUM_S{1'b0}};\n  /////////////////////////////////////////////////////////////////////////////\n  // Assign conditional encoded target output signal.\n  assign M_GRANT_ENC = (C_GRANT_ENC == 1) ? f_hot2enc(grant_hot) : {C_NUM_S_LOG{1'b0}};\n  \n  /////////////////////////////////////////////////////////////////////////////\n  // Select a new chosen when we need to arbitrate\n  // If we don't have a new chosen, keep the old one since it's a good chance\n  // that it will do another request\n  always @(posedge ACLK)\n    begin\n      if (ARESET) begin\n        chosen <= {C_NUM_S{1'b0}};\n        last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};\n      end else if (need_arbitration) begin\n        chosen <= next_rr_hot;   \n        if (|next_rr_hot) last_rr_hot <= next_rr_hot;\n      end\n    end\n\n  assign valid_rr =  S_VALID;\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Round-robin arbiter\n  // Selects next request to grant from among inputs with PRIO = 0, if any.\n  /////////////////////////////////////////////////////////////////////////////\n  \n  always @ * begin\n    next_rr_hot = 0;\n    for (i=0;i<C_NUM_S;i=i+1) begin\n      n = (i>0) ? (i-1) : (C_NUM_S-1);\n      carry_rr[i*C_NUM_S] = last_rr_hot[n];\n      mask_rr[i*C_NUM_S] = ~valid_rr[n];\n      for (j=1;j<C_NUM_S;j=j+1) begin\n        n = (i-j > 0) ? (i-j-1) : (C_NUM_S+i-j-1);\n        carry_rr[i*C_NUM_S+j] = carry_rr[i*C_NUM_S+j-1] | (last_rr_hot[n] & mask_rr[i*C_NUM_S+j-1]);\n        if (j < C_NUM_S-1) begin\n          mask_rr[i*C_NUM_S+j] = mask_rr[i*C_NUM_S+j-1] & ~valid_rr[n];\n        end\n      end   \n      next_rr_hot[i] = valid_rr[i] & carry_rr[(i+1)*C_NUM_S-1];\n    end\n  end\n  \nendmodule\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: crossbar_sasd.v\n//\n// Description: \n//   This module is a M-master to N-slave AXI axi_crossbar_v2_1_23_crossbar switch.\n//   Single transaction issuing, single arbiter (both W&R), single data pathways.\n//   The interface of this module consists of a vectored slave and master interface\n//     in which all slots are sized and synchronized to the native width and clock \n//     of the interconnect, and are all AXI4 protocol.\n//   All width, clock and protocol conversions are done outside this block, as are\n//     any pipeline registers or data FIFOs.\n//   This module contains all arbitration, decoders and channel multiplexing logic.\n//     It also contains the diagnostic registers and control interface.\n//\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    crossbar_sasd\n//      addr_arbiter_sasd\n//        mux_enc\n//      addr_decoder\n//        comparator_static\n//      splitter\n//      mux_enc\n//      axic_register_slice\n//      decerr_slave\n//      \n//-----------------------------------------------------------------------------\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_crossbar_sasd #\n  (\n   parameter         C_FAMILY                       = \"none\", \n   parameter integer C_NUM_SLAVE_SLOTS              =   1, \n   parameter integer C_NUM_MASTER_SLOTS             =   1, \n   parameter integer C_NUM_ADDR_RANGES              = 1,\n   parameter integer C_AXI_ID_WIDTH                   = 1, \n   parameter integer C_AXI_ADDR_WIDTH                 = 32, \n   parameter integer C_AXI_DATA_WIDTH = 32, \n   parameter integer C_AXI_PROTOCOL                 = 0, \n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}}, \n   parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},\n   parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS      = 0,\n   parameter integer C_AXI_AWUSER_WIDTH               = 1,\n   parameter integer C_AXI_ARUSER_WIDTH               = 1,\n   parameter integer C_AXI_WUSER_WIDTH                = 1,\n   parameter integer C_AXI_RUSER_WIDTH                = 1,\n   parameter integer C_AXI_BUSER_WIDTH                = 1,\n   parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE           = {C_NUM_SLAVE_SLOTS{1'b1}}, \n   parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ            = {C_NUM_SLAVE_SLOTS{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE           = {C_NUM_MASTER_SLOTS{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ            = {C_NUM_MASTER_SLOTS{1'b1}}, \n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY             = {C_NUM_SLAVE_SLOTS{32'h00000000}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE                   = {C_NUM_MASTER_SLOTS{32'h00000000}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE            = {C_NUM_MASTER_SLOTS{32'h00000000}},\n   parameter integer C_R_REGISTER               = 0,\n   parameter integer C_RANGE_CHECK                    = 0,\n   parameter integer C_ADDR_DECODE                    = 0,\n   parameter integer C_DEBUG              = 1\n   )\n  (\n   // Global Signals\n   input  wire                                                    ACLK,\n   input  wire                                                    ARESETN,\n   // Slave Interface Write Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_AWID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           S_AXI_AWADDR,\n   input  wire [C_NUM_SLAVE_SLOTS*8-1:0]                          S_AXI_AWLEN,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_AWSIZE,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_AWBURST,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_AWLOCK,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWCACHE,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_AWPROT,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWREGION,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWQOS,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0]         S_AXI_AWUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_AWVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_AWREADY,\n   // Slave Interface Write Data Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_WID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]     S_AXI_WDATA,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0]   S_AXI_WSTRB,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WLAST,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0]          S_AXI_WUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WREADY,\n   // Slave Interface Write Response Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_BID,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_BRESP,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_BVALID,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_BREADY,\n   // Slave Interface Read Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_ARID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           S_AXI_ARADDR,\n   input  wire [C_NUM_SLAVE_SLOTS*8-1:0]                          S_AXI_ARLEN,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_ARSIZE,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_ARBURST,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_ARLOCK,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARCACHE,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_ARPROT,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARREGION,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARQOS,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0]         S_AXI_ARUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_ARVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_ARREADY,\n   // Slave Interface Read Data Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_RID,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]     S_AXI_RDATA,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_RRESP,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RLAST,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0]          S_AXI_RUSER,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RVALID,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RREADY,\n   // Master Interface Write Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_AWID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          M_AXI_AWADDR,\n   output wire [C_NUM_MASTER_SLOTS*8-1:0]                         M_AXI_AWLEN,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_AWSIZE,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_AWBURST,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_AWLOCK,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWCACHE,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_AWPROT,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWREGION,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWQOS,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0]        M_AXI_AWUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_AWVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_AWREADY,\n   // Master Interface Write Data Ports\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_WID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]    M_AXI_WDATA,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0]  M_AXI_WSTRB,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WLAST,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0]         M_AXI_WUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WREADY,\n   // Master Interface Write Response Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_BID,  // Unused\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_BRESP,\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0]         M_AXI_BUSER,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_BVALID,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_BREADY,\n   // Master Interface Read Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_ARID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          M_AXI_ARADDR,\n   output wire [C_NUM_MASTER_SLOTS*8-1:0]                         M_AXI_ARLEN,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_ARSIZE,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_ARBURST,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_ARLOCK,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARCACHE,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_ARPROT,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARREGION,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARQOS,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0]        M_AXI_ARUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_ARVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_ARREADY,\n   // Master Interface Read Data Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_RID,  // Unused\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]    M_AXI_RDATA,\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_RRESP,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RLAST,\n   input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0]         M_AXI_RUSER,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RVALID,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RREADY\n   );\n   \n  localparam integer  P_AXI4 = 0;\n  localparam integer  P_AXI3 = 1;\n  localparam integer  P_AXILITE = 2;\n  localparam integer P_NUM_MASTER_SLOTS_DE = C_RANGE_CHECK ? C_NUM_MASTER_SLOTS+1 : C_NUM_MASTER_SLOTS;\n  localparam integer P_NUM_MASTER_SLOTS_LOG = (C_NUM_MASTER_SLOTS>1) ? f_ceil_log2(C_NUM_MASTER_SLOTS) : 1;\n  localparam integer P_NUM_MASTER_SLOTS_DE_LOG = (P_NUM_MASTER_SLOTS_DE>1) ? f_ceil_log2(P_NUM_MASTER_SLOTS_DE) : 1;\n  localparam integer P_NUM_SLAVE_SLOTS_LOG = (C_NUM_SLAVE_SLOTS>1) ? f_ceil_log2(C_NUM_SLAVE_SLOTS) : 1;\n  localparam integer P_AXI_AUSER_WIDTH = (C_AXI_AWUSER_WIDTH > C_AXI_ARUSER_WIDTH) ? C_AXI_AWUSER_WIDTH : C_AXI_ARUSER_WIDTH;\n  localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1;\n  localparam integer P_AMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+2+4+4 + P_AXI_AUSER_WIDTH + 4;\n  localparam integer P_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH;\n  localparam integer P_RMESG_WIDTH = 1+2 + C_AXI_DATA_WIDTH + C_AXI_RUSER_WIDTH;\n  localparam integer P_WMESG_WIDTH = 1 + C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH;\n  localparam [31:0]   P_AXILITE_ERRMODE = 32'h00000001;\n  localparam integer P_NONSECURE_BIT = 1; \n  localparam [C_NUM_MASTER_SLOTS-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE);  // Mask of secure MI-slots\n  localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXILITE_MASK = f_m_axilite(0);  // Mask of axilite rule-check MI-slots\n  localparam [1:0]   P_FIXED = 2'b00;\n  localparam integer P_BYPASS = 0;\n  localparam integer P_LIGHTWT = 7;\n  localparam integer P_FULLY_REG = 1;\n  localparam integer P_R_REG_CONFIG = C_R_REGISTER == 8 ?  // \"Automatic\" reg-slice\n        (C_RANGE_CHECK ? ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHTWT : P_FULLY_REG) : P_BYPASS) :  // Bypass if no R-channel mux\n        C_R_REGISTER;\n  localparam P_DECERR = 2'b11;\n\n  //---------------------------------------------------------------------------\n  // Functions\n  //---------------------------------------------------------------------------\n  // Ceiling of log2(x)\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  // Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value\n  //   only for end-point SI-slots\n  function [C_AXI_ID_WIDTH-1:0] f_extend_ID\n    (\n     input [C_AXI_ID_WIDTH-1:0] s_id,\n     input integer slot\n     );\n    begin\n      f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH]));\n    end\n  endfunction\n\n  // Convert Bit32 vector of range [0,1] to Bit1 vector on MI\n  function [C_NUM_MASTER_SLOTS-1:0] f_bit32to1_mi\n    (input [C_NUM_MASTER_SLOTS*32-1:0] vec32);\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        f_bit32to1_mi[mi] = vec32[mi*32];\n      end\n    end\n  endfunction\n\n  // AxiLite error-checking mask (on MI)      \n  function [C_NUM_MASTER_SLOTS-1:0] f_m_axilite\n    (\n      input integer null_arg\n    );\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        f_m_axilite[mi] = (C_M_AXI_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);\n      end\n    end\n  endfunction\n\n  genvar gen_si_slot;\n  genvar gen_mi_slot;\n  wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0]                      si_awmesg          ;\n  wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0]                      si_armesg          ;\n  wire [P_AMESG_WIDTH-1:0]                                        aa_amesg         ;\n  wire [C_AXI_ID_WIDTH-1:0]                                       mi_aid            ;\n  wire [C_AXI_ADDR_WIDTH-1:0]                                     mi_aaddr          ;\n  wire [8-1:0]                                                    mi_alen           ;\n  wire [3-1:0]                                                    mi_asize          ;\n  wire [2-1:0]                                                    mi_alock          ;\n  wire [3-1:0]                                                    mi_aprot          ;\n  wire [2-1:0]                                                    mi_aburst        ;\n  wire [4-1:0]                                                    mi_acache        ;\n  wire [4-1:0]                                                    mi_aregion        ;\n  wire [4-1:0]                                                    mi_aqos        ;\n  wire [P_AXI_AUSER_WIDTH-1:0]                                    mi_auser        ;\n  wire [4-1:0]                                                    target_region        ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  aa_grant_hot     ;\n  wire [P_NUM_SLAVE_SLOTS_LOG-1:0]                                  aa_grant_enc     ;\n  wire                                                            aa_grant_rnw ;\n  wire                                                            aa_grant_any ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                                   target_mi_hot    ;\n  wire [P_NUM_MASTER_SLOTS_LOG-1:0]                                   target_mi_enc    ;\n  reg  [P_NUM_MASTER_SLOTS_DE-1:0]                               m_atarget_hot = 0    ;\n  reg  [P_NUM_MASTER_SLOTS_DE_LOG-1:0]                               m_atarget_enc = 0    ;\n  wire [P_NUM_MASTER_SLOTS_DE_LOG-1:0]                               m_atarget_enc_comb    ;\n  wire                                                            match;\n  wire                                                            any_error         ;\n  wire [7:0]                                                      m_aerror_i         ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_awvalid            ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_awready            ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_arvalid            ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_arready            ;\n  wire                                                            aa_awvalid         ;\n  wire                                                            aa_awready         ;\n  wire                                                            aa_arvalid         ;\n  wire                                                            aa_arready         ;\n  wire                                                            mi_awvalid_en;\n  wire                                                            mi_awready_mux;\n  wire                                                            mi_arvalid_en;\n  wire                                                            mi_arready_mux;\n  wire                                                            w_transfer_en;\n  wire                                                            w_complete_mux;\n  wire                                                            b_transfer_en;\n  wire                                                            b_complete_mux;\n  wire                                                            r_transfer_en;\n  wire                                                            r_complete_mux;\n  wire                                                            target_secure;\n  wire                                                            target_write;\n  wire                                                            target_read;\n  wire                                                            target_axilite;\n  \n  wire [P_BMESG_WIDTH-1:0]                                        si_bmesg           ;\n  wire [P_NUM_MASTER_SLOTS_DE*P_BMESG_WIDTH-1:0]                 mi_bmesg           ;\n  wire [P_NUM_MASTER_SLOTS_DE*2-1:0]                             mi_bresp           ;\n  wire [P_NUM_MASTER_SLOTS_DE*C_AXI_BUSER_WIDTH-1:0]             mi_buser           ;\n  wire [2-1:0]                                                    si_bresp           ;\n  wire [C_AXI_BUSER_WIDTH-1:0]                                    si_buser           ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_bvalid          ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_bready          ;\n  wire                                                            aa_bvalid          ;\n  wire                                                            aa_bready         ;\n  wire                                                            si_bready         ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                                    si_bvalid;\n  \n  wire [P_RMESG_WIDTH-1:0]                                        aa_rmesg           ;\n  wire [P_RMESG_WIDTH-1:0]                                        sr_rmesg           ;\n  wire [P_NUM_MASTER_SLOTS_DE*P_RMESG_WIDTH-1:0]                 mi_rmesg           ;\n  wire [P_NUM_MASTER_SLOTS_DE*2-1:0]                             mi_rresp           ;\n  wire [P_NUM_MASTER_SLOTS_DE*C_AXI_RUSER_WIDTH-1:0]             mi_ruser           ;\n  wire [P_NUM_MASTER_SLOTS_DE*C_AXI_DATA_WIDTH-1:0]          mi_rdata              ;\n  wire [P_NUM_MASTER_SLOTS_DE*1-1:0]                             mi_rlast              ;\n  wire [2-1:0]                                                    si_rresp           ;\n  wire [C_AXI_RUSER_WIDTH-1:0]                                    si_ruser           ;\n  wire [C_AXI_DATA_WIDTH-1:0]                                 si_rdata              ;\n  wire                                                            si_rlast              ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_rvalid          ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_rready          ;\n  wire                                                            aa_rvalid          ;\n  wire                                                            aa_rready         ;\n  wire                                                            sr_rvalid          ;\n  wire                                                            si_rready         ;\n  wire                                                            sr_rready         ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                                    si_rvalid;\n  \n  wire [C_NUM_SLAVE_SLOTS*P_WMESG_WIDTH-1:0]                      si_wmesg           ;\n  wire [P_WMESG_WIDTH-1:0]                                        mi_wmesg           ;\n  wire [C_AXI_ID_WIDTH-1:0]                                    mi_wid              ;\n  wire [C_AXI_DATA_WIDTH-1:0]                            mi_wdata              ;\n  wire [C_AXI_DATA_WIDTH/8-1:0]                          mi_wstrb              ;\n  wire [C_AXI_WUSER_WIDTH-1:0]                                    mi_wuser              ;\n  wire [1-1:0]                                                    mi_wlast              ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_wvalid          ;\n  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_wready          ;\n  wire                                                            aa_wvalid          ;\n  wire                                                            aa_wready         ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                                    si_wready;\n  \n  reg  [7:0]                                                      debug_r_beat_cnt_i;\n  reg  [7:0]                                                      debug_w_beat_cnt_i;\n  reg  [7:0]                                                      debug_aw_trans_seq_i;\n  reg  [7:0]                                                      debug_ar_trans_seq_i;\n\n  reg aresetn_d = 1'b0; // Reset delay register\n  always @(posedge ACLK) begin\n    if (~ARESETN) begin\n      aresetn_d <= 1'b0;\n    end else begin\n      aresetn_d <= ARESETN;\n    end\n  end\n  wire reset;\n  assign reset = ~aresetn_d;\n\n  generate\n    axi_crossbar_v2_1_23_addr_arbiter_sasd #\n      (\n       .C_FAMILY                (C_FAMILY),\n       .C_NUM_S                 (C_NUM_SLAVE_SLOTS),\n       .C_NUM_S_LOG             (P_NUM_SLAVE_SLOTS_LOG),\n       .C_AMESG_WIDTH            (P_AMESG_WIDTH),\n       .C_GRANT_ENC             (1),\n       .C_ARB_PRIORITY          (C_S_AXI_ARB_PRIORITY)\n       )\n      addr_arbiter_inst\n        (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         // Vector of SI-side AW command request inputs\n         .S_AWMESG                (si_awmesg),\n         .S_ARMESG                (si_armesg),\n         .S_AWVALID               (S_AXI_AWVALID),\n         .S_AWREADY               (S_AXI_AWREADY),\n         .S_ARVALID               (S_AXI_ARVALID),\n         .S_ARREADY               (S_AXI_ARREADY),\n         .M_GRANT_ENC           (aa_grant_enc),\n         .M_GRANT_HOT           (aa_grant_hot),  // SI-slot 1-hot mask of granted command\n         .M_GRANT_ANY             (aa_grant_any),\n         .M_GRANT_RNW             (aa_grant_rnw),\n         .M_AMESG                (aa_amesg),  // Either S_AWMESG or S_ARMESG, as indicated by M_AWVALID and M_ARVALID.\n         .M_AWVALID               (aa_awvalid),\n         .M_AWREADY               (aa_awready),\n         .M_ARVALID               (aa_arvalid),\n         .M_ARREADY               (aa_arready)\n         );\n\n    if (C_ADDR_DECODE) begin : gen_addr_decoder\n      axi_crossbar_v2_1_23_addr_decoder #\n        (\n          .C_FAMILY          (C_FAMILY),\n          .C_NUM_TARGETS     (C_NUM_MASTER_SLOTS),\n          .C_NUM_TARGETS_LOG (P_NUM_MASTER_SLOTS_LOG),\n          .C_NUM_RANGES      (C_NUM_ADDR_RANGES),\n          .C_ADDR_WIDTH      (C_AXI_ADDR_WIDTH),\n          .C_TARGET_ENC      (1),\n          .C_TARGET_HOT      (1),\n          .C_REGION_ENC      (1),\n          .C_BASE_ADDR      (C_M_AXI_BASE_ADDR),\n          .C_HIGH_ADDR      (C_M_AXI_HIGH_ADDR),\n          .C_TARGET_QUAL     ({C_NUM_MASTER_SLOTS{1'b1}}),\n          .C_RESOLUTION      (2)\n        ) \n        addr_decoder_inst \n        (\n          .ADDR             (mi_aaddr),        \n          .TARGET_HOT       (target_mi_hot),  \n          .TARGET_ENC       (target_mi_enc),  \n          .MATCH            (match),       \n          .REGION           (target_region)      \n        );\n    end else begin : gen_no_addr_decoder\n      assign target_mi_hot = 1;\n      assign match = 1'b1;\n      assign target_region = 4'b0000;\n    end  // gen_addr_decoder\n    \n    // AW-channel arbiter command transfer completes upon completion of both M-side AW-channel transfer and B channel completion.\n    axi_crossbar_v2_1_23_splitter #  \n      (\n        .C_NUM_M                (3)\n      )\n      splitter_aw\n      (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         .S_VALID              (aa_awvalid),\n         .S_READY              (aa_awready),\n         .M_VALID              ({mi_awvalid_en, w_transfer_en, b_transfer_en}),\n         .M_READY              ({mi_awready_mux, w_complete_mux, b_complete_mux})\n      );\n    \n    // AR-channel arbiter command transfer completes upon completion of both M-side AR-channel transfer and R channel completion.\n    axi_crossbar_v2_1_23_splitter #  \n      (\n        .C_NUM_M                (2)\n      )\n      splitter_ar\n      (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         .S_VALID              (aa_arvalid),\n         .S_READY              (aa_arready),\n         .M_VALID              ({mi_arvalid_en, r_transfer_en}),\n         .M_READY              ({mi_arready_mux, r_complete_mux})\n      );\n    \n    assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);\n    assign target_write = |(target_mi_hot & C_M_AXI_SUPPORTS_WRITE);\n    assign target_read = |(target_mi_hot & C_M_AXI_SUPPORTS_READ);\n    assign target_axilite = |(target_mi_hot & P_M_AXILITE_MASK);\n    \n    assign any_error = C_RANGE_CHECK && (m_aerror_i != 0);             // DECERR if error-detection enabled and any error condition.\n    assign m_aerror_i[0] = ~match;                                     // Invalid target address\n    assign m_aerror_i[1] = target_secure && mi_aprot[P_NONSECURE_BIT]; // TrustZone violation\n    assign m_aerror_i[2] = target_axilite && ((mi_alen != 0) || \n      (mi_asize[1:0] == 2'b11) || (mi_asize[2] == 1'b1));              // AxiLite access violation\n    assign m_aerror_i[3] = (~aa_grant_rnw && ~target_write) ||\n      (aa_grant_rnw && ~target_read);                                  // R/W direction unsupported by target\n    assign m_aerror_i[7:4] = 4'b0000;                                     // Reserved\n    assign m_atarget_enc_comb = any_error ? (P_NUM_MASTER_SLOTS_DE-1) : target_mi_enc;  // Select MI slot or decerr_slave\n      \n    always @(posedge ACLK) begin\n      if (reset) begin\n        m_atarget_hot <= 0;\n        m_atarget_enc <= 0;\n      end else begin\n        m_atarget_hot <= {P_NUM_MASTER_SLOTS_DE{aa_grant_any}} & (any_error ? {1'b1, {C_NUM_MASTER_SLOTS{1'b0}}} : {1'b0, target_mi_hot});  // Select MI slot or decerr_slave\n        m_atarget_enc <= m_atarget_enc_comb;\n      end\n    end\n    \n    // Receive AWREADY from targeted MI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (1)\n      ) mi_awready_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_awready),\n       .O   (mi_awready_mux),\n       .OE  (mi_awvalid_en)\n      ); \n      \n    // Receive ARREADY from targeted MI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (1)\n      ) mi_arready_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_arready),\n       .O   (mi_arready_mux),\n       .OE  (mi_arvalid_en)\n      ); \n      \n    assign mi_awvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_awvalid_en}};  // Assert AWVALID on targeted MI.\n    assign mi_arvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_arvalid_en}};  // Assert ARVALID on targeted MI.\n    assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS];  // Propagate to MI slots.\n    assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS];  // Propagate to MI slots.\n    assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY;  // Copy from MI slots.\n    assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY;  // Copy from MI slots.\n    \n    // Receive WREADY from targeted MI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (1)\n      ) mi_wready_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_wready),\n       .O   (aa_wready),\n       .OE  (w_transfer_en)\n      ); \n      \n    assign mi_wvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_wvalid}};  // Assert WVALID on targeted MI.\n    assign si_wready = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_wready}};  // Assert WREADY on granted SI.\n    assign S_AXI_WREADY = si_wready;\n    assign w_complete_mux = aa_wready & aa_wvalid & mi_wlast;  // W burst complete on on designated SI/MI.\n    \n    // Receive RREADY from granted SI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (C_NUM_SLAVE_SLOTS),\n       .C_SEL_WIDTH   (P_NUM_SLAVE_SLOTS_LOG),\n       .C_DATA_WIDTH  (1)\n      ) si_rready_mux_inst \n      (\n       .S   (aa_grant_enc),\n       .A   (S_AXI_RREADY),\n       .O   (si_rready),\n       .OE  (r_transfer_en)\n      ); \n      \n    assign sr_rready = si_rready & r_transfer_en;\n    assign mi_rready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_rready}};  // Assert RREADY on targeted MI.\n    assign si_rvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{sr_rvalid}};  // Assert RVALID on granted SI.\n    assign S_AXI_RVALID = si_rvalid;\n    assign r_complete_mux = sr_rready & sr_rvalid & si_rlast;  // R burst complete on on designated SI/MI.\n    \n    // Receive BREADY from granted SI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (C_NUM_SLAVE_SLOTS),\n       .C_SEL_WIDTH   (P_NUM_SLAVE_SLOTS_LOG),\n       .C_DATA_WIDTH  (1)\n      ) si_bready_mux_inst \n      (\n       .S   (aa_grant_enc),\n       .A   (S_AXI_BREADY),\n       .O   (si_bready),\n       .OE  (b_transfer_en)\n      ); \n      \n    assign aa_bready = si_bready & b_transfer_en;\n    assign mi_bready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_bready}};  // Assert BREADY on targeted MI.\n    assign si_bvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_bvalid}};  // Assert BVALID on granted SI.\n    assign S_AXI_BVALID = si_bvalid;\n    assign b_complete_mux = aa_bready & aa_bvalid;  // B transfer complete on on designated SI/MI.\n    \n    for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_si_amesg\n      assign si_armesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = {  // Concatenate from MSB to LSB\n        4'b0000,\n//        S_AXI_ARREGION[gen_si_slot*4+:4],\n        S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH +: C_AXI_ARUSER_WIDTH],\n        S_AXI_ARQOS[gen_si_slot*4+:4],\n        S_AXI_ARCACHE[gen_si_slot*4+:4],\n        S_AXI_ARBURST[gen_si_slot*2+:2],\n        S_AXI_ARPROT[gen_si_slot*3+:3],\n        S_AXI_ARLOCK[gen_si_slot*2+:2],\n        S_AXI_ARSIZE[gen_si_slot*3+:3],\n        S_AXI_ARLEN[gen_si_slot*8+:8],\n        S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH],\n        f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH +: C_AXI_ID_WIDTH], gen_si_slot)\n        };\n      assign si_awmesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = {  // Concatenate from MSB to LSB\n        4'b0000,\n//        S_AXI_AWREGION[gen_si_slot*4+:4],\n        S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH +: C_AXI_AWUSER_WIDTH],\n        S_AXI_AWQOS[gen_si_slot*4+:4],\n        S_AXI_AWCACHE[gen_si_slot*4+:4],\n        S_AXI_AWBURST[gen_si_slot*2+:2],\n        S_AXI_AWPROT[gen_si_slot*3+:3],\n        S_AXI_AWLOCK[gen_si_slot*2+:2],\n        S_AXI_AWSIZE[gen_si_slot*3+:3],\n        S_AXI_AWLEN[gen_si_slot*8+:8],\n        S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH],\n        f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)\n        };\n    end  // gen_si_amesg\n    \n    assign mi_aid        = aa_amesg[0 +: C_AXI_ID_WIDTH];\n    assign mi_aaddr      = aa_amesg[C_AXI_ID_WIDTH +: C_AXI_ADDR_WIDTH];\n    assign mi_alen       = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +: 8];\n    assign mi_asize      = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +: 3];\n    assign mi_alock      = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +: 2];\n    assign mi_aprot      = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +: 3];\n    assign mi_aburst     = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +: 2];\n    assign mi_acache     = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2 +: 4];\n    assign mi_aqos       = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4 +: 4];\n    assign mi_auser      = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4 +: P_AXI_AUSER_WIDTH];\n    assign mi_aregion    = (C_ADDR_DECODE != 0) ? target_region : aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4+P_AXI_AUSER_WIDTH +: 4];\n      \n    // Broadcast AW transfer payload to all MI-slots\n    assign M_AXI_AWID        = {C_NUM_MASTER_SLOTS{mi_aid}};\n    assign M_AXI_AWADDR      = {C_NUM_MASTER_SLOTS{mi_aaddr}};\n    assign M_AXI_AWLEN       = {C_NUM_MASTER_SLOTS{mi_alen }};\n    assign M_AXI_AWSIZE      = {C_NUM_MASTER_SLOTS{mi_asize}};\n    assign M_AXI_AWLOCK      = {C_NUM_MASTER_SLOTS{mi_alock}};\n    assign M_AXI_AWPROT      = {C_NUM_MASTER_SLOTS{mi_aprot}};\n    assign M_AXI_AWREGION    = {C_NUM_MASTER_SLOTS{mi_aregion}};\n    assign M_AXI_AWBURST     = {C_NUM_MASTER_SLOTS{mi_aburst}};\n    assign M_AXI_AWCACHE     = {C_NUM_MASTER_SLOTS{mi_acache}};\n    assign M_AXI_AWQOS       = {C_NUM_MASTER_SLOTS{mi_aqos  }};\n    assign M_AXI_AWUSER      = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_AWUSER_WIDTH] }};\n    \n    // Broadcast AR transfer payload to all MI-slots\n    assign M_AXI_ARID        = {C_NUM_MASTER_SLOTS{mi_aid}};\n    assign M_AXI_ARADDR      = {C_NUM_MASTER_SLOTS{mi_aaddr}};                        \n    assign M_AXI_ARLEN       = {C_NUM_MASTER_SLOTS{mi_alen }};                        \n    assign M_AXI_ARSIZE      = {C_NUM_MASTER_SLOTS{mi_asize}};                        \n    assign M_AXI_ARLOCK      = {C_NUM_MASTER_SLOTS{mi_alock}};                        \n    assign M_AXI_ARPROT      = {C_NUM_MASTER_SLOTS{mi_aprot}};                        \n    assign M_AXI_ARREGION    = {C_NUM_MASTER_SLOTS{mi_aregion}};                          \n    assign M_AXI_ARBURST     = {C_NUM_MASTER_SLOTS{mi_aburst}};                       \n    assign M_AXI_ARCACHE     = {C_NUM_MASTER_SLOTS{mi_acache}};                       \n    assign M_AXI_ARQOS       = {C_NUM_MASTER_SLOTS{mi_aqos  }};                       \n    assign M_AXI_ARUSER      = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_ARUSER_WIDTH] }};\n    \n    // W-channel MI handshakes\n    assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS];\n    assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY;\n    // Broadcast W transfer payload to all MI-slots\n    assign M_AXI_WLAST = {C_NUM_MASTER_SLOTS{mi_wlast}};\n    assign M_AXI_WUSER = {C_NUM_MASTER_SLOTS{mi_wuser}};\n    assign M_AXI_WDATA = {C_NUM_MASTER_SLOTS{mi_wdata}};\n    assign M_AXI_WSTRB = {C_NUM_MASTER_SLOTS{mi_wstrb}};\n    assign M_AXI_WID =   {C_NUM_MASTER_SLOTS{mi_wid}};\n    \n    // Broadcast R transfer payload to all SI-slots\n    assign S_AXI_RLAST = {C_NUM_SLAVE_SLOTS{si_rlast}};\n    assign S_AXI_RRESP = {C_NUM_SLAVE_SLOTS{si_rresp}};\n    assign S_AXI_RUSER = {C_NUM_SLAVE_SLOTS{si_ruser}};\n    assign S_AXI_RDATA = {C_NUM_SLAVE_SLOTS{si_rdata}};\n    assign S_AXI_RID =   {C_NUM_SLAVE_SLOTS{mi_aid}};\n    \n    // Broadcast B transfer payload to all SI-slots\n    assign S_AXI_BRESP = {C_NUM_SLAVE_SLOTS{si_bresp}};\n    assign S_AXI_BUSER = {C_NUM_SLAVE_SLOTS{si_buser}};\n    assign S_AXI_BID =   {C_NUM_SLAVE_SLOTS{mi_aid}};\n    \n    if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux\n      // SI WVALID mux.\n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_SLAVE_SLOTS),\n         .C_SEL_WIDTH   (P_NUM_SLAVE_SLOTS_LOG),\n         .C_DATA_WIDTH  (1)\n        ) si_w_valid_mux_inst \n        (\n         .S   (aa_grant_enc),\n         .A   (S_AXI_WVALID),\n         .O   (aa_wvalid),\n         .OE  (w_transfer_en)\n        ); \n      \n      // SI W-channel payload mux\n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_SLAVE_SLOTS),\n         .C_SEL_WIDTH   (P_NUM_SLAVE_SLOTS_LOG),\n         .C_DATA_WIDTH  (P_WMESG_WIDTH)\n        ) si_w_payload_mux_inst \n        (\n         .S   (aa_grant_enc),\n         .A   (si_wmesg),\n         .O   (mi_wmesg),\n         .OE  (1'b1)\n        ); \n        \n      for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_wmesg\n        assign si_wmesg[gen_si_slot*P_WMESG_WIDTH+:P_WMESG_WIDTH] = {  // Concatenate from MSB to LSB\n          ((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1'b0),\n          S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH],\n          S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8],\n          S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],\n          S_AXI_WLAST[gen_si_slot*1+:1]\n        };\n      end  // gen_wmesg\n      \n      assign mi_wlast = mi_wmesg[0];\n      assign mi_wdata = mi_wmesg[1 +: C_AXI_DATA_WIDTH];\n      assign mi_wstrb = mi_wmesg[1+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8];\n      assign mi_wuser = mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH];\n      assign mi_wid =   mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH];\n    end else begin : gen_no_wmux\n      assign aa_wvalid = w_transfer_en & S_AXI_WVALID;\n      assign mi_wlast  = S_AXI_WLAST;\n      assign mi_wdata  = S_AXI_WDATA;\n      assign mi_wstrb  = S_AXI_WSTRB;\n      assign mi_wuser  = S_AXI_WUSER;\n      assign mi_wid =    S_AXI_WID;\n    end  // gen_wmux\n    \n    // Receive RVALID from targeted MI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (1)\n      ) mi_rvalid_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_rvalid),\n       .O   (aa_rvalid),\n       .OE  (r_transfer_en)\n      ); \n      \n    // MI R-channel payload mux\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (P_RMESG_WIDTH)\n      ) mi_rmesg_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_rmesg),\n       .O   (aa_rmesg),\n       .OE  (1'b1)\n      ); \n      \n    axi_register_slice_v2_1_22_axic_register_slice #\n      (\n       .C_FAMILY (C_FAMILY),\n       .C_DATA_WIDTH (P_RMESG_WIDTH),\n       .C_REG_CONFIG (P_R_REG_CONFIG)\n       )\n      reg_slice_r\n      (\n       // System Signals\n       .ACLK(ACLK),\n       .ARESET(reset),\n\n       // Slave side\n       .S_PAYLOAD_DATA(aa_rmesg),\n       .S_VALID(aa_rvalid),\n       .S_READY(aa_rready),\n\n       // Master side\n       .M_PAYLOAD_DATA(sr_rmesg),\n       .M_VALID(sr_rvalid),\n       .M_READY(sr_rready)\n       );\n\n    assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID; \n    assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST; \n    assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP;\n    assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER;\n    assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA;\n    assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS];\n    \n    for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_rmesg\n      assign mi_rmesg[gen_mi_slot*P_RMESG_WIDTH+:P_RMESG_WIDTH] = {  // Concatenate from MSB to LSB\n        mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH],\n        mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],\n        mi_rresp[gen_mi_slot*2+:2],\n        mi_rlast[gen_mi_slot*1+:1]\n      };\n    end  // gen_rmesg\n    \n    assign si_rlast = sr_rmesg[0];\n    assign si_rresp = sr_rmesg[1 +: 2];\n    assign si_rdata = sr_rmesg[1+2 +: C_AXI_DATA_WIDTH];\n    assign si_ruser = sr_rmesg[1+2+C_AXI_DATA_WIDTH +: C_AXI_RUSER_WIDTH];\n      \n    // Receive BVALID from targeted MI.\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (1)\n      ) mi_bvalid_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_bvalid),\n       .O   (aa_bvalid),\n       .OE  (b_transfer_en)\n      ); \n      \n    // MI B-channel payload mux\n    generic_baseblocks_v2_1_0_mux_enc # \n      (\n       .C_FAMILY      (\"rtl\"),\n       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),\n       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),\n       .C_DATA_WIDTH  (P_BMESG_WIDTH)\n      ) mi_bmesg_mux_inst \n      (\n       .S   (m_atarget_enc),\n       .A   (mi_bmesg),\n       .O   (si_bmesg),\n       .OE  (1'b1)\n      ); \n      \n    assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID; \n    assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP;\n    assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER;\n    assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS];\n    \n    for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_bmesg\n      assign mi_bmesg[gen_mi_slot*P_BMESG_WIDTH+:P_BMESG_WIDTH] = {  // Concatenate from MSB to LSB\n        mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH],\n        mi_bresp[gen_mi_slot*2+:2]\n      };\n    end  // gen_bmesg\n    \n    assign si_bresp = si_bmesg[0 +: 2];\n    assign si_buser = si_bmesg[2 +: C_AXI_BUSER_WIDTH];\n    \n    if (C_DEBUG) begin : gen_debug_trans_seq\n      // DEBUG WRITE TRANSACTION SEQUENCE COUNTER\n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_aw_trans_seq_i <= 1;\n        end else begin\n          if (aa_awvalid && aa_awready) begin\n            debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1;\n          end\n        end\n      end\n  \n      // DEBUG READ TRANSACTION SEQUENCE COUNTER\n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_ar_trans_seq_i <= 1;\n        end else begin\n          if (aa_arvalid && aa_arready) begin\n            debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1;\n          end\n        end\n      end\n      \n      // DEBUG WRITE BEAT COUNTER \n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_w_beat_cnt_i <= 0;\n        end else if (aa_wready & aa_wvalid) begin\n          if (mi_wlast) begin\n            debug_w_beat_cnt_i <= 0;\n          end else begin\n            debug_w_beat_cnt_i <= debug_w_beat_cnt_i + 1;\n          end\n        end\n      end  // Clocked process\n    \n      // DEBUG READ BEAT COUNTER \n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_r_beat_cnt_i <= 0;\n        end else if (sr_rready & sr_rvalid) begin\n          if (si_rlast) begin\n            debug_r_beat_cnt_i <= 0;\n          end else begin\n            debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;\n          end\n        end\n      end  // Clocked process\n    \n    end  // gen_debug_trans_seq\n\n    if (C_RANGE_CHECK) begin : gen_decerr\n      // Highest MI-slot (index C_NUM_MASTER_SLOTS) is the error handler\n      axi_crossbar_v2_1_23_decerr_slave #\n        (\n         .C_AXI_ID_WIDTH                 (1),\n         .C_AXI_DATA_WIDTH               (C_AXI_DATA_WIDTH),\n         .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),\n         .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),\n         .C_AXI_PROTOCOL                 (C_AXI_PROTOCOL),\n         .C_RESP                         (P_DECERR) \n        )\n        decerr_slave_inst\n          (\n           .S_AXI_ACLK (ACLK),\n           .S_AXI_ARESET (reset),\n           .S_AXI_AWID (1'b0),\n           .S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_WLAST (mi_wlast),\n           .S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_BID (),\n           .S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]),\n           .S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]),\n           .S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_ARID (1'b0),\n           .S_AXI_ARLEN (mi_alen),\n           .S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RID (),\n           .S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),\n           .S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]),\n           .S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]),\n           .S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS])\n         );\n    end  // gen_decerr\n\n  endgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: crossbar.v\n//\n// Description: \n//   This module is a M-master to N-slave AXI axi_crossbar_v2_1_23_crossbar switch.\n//   The interface of this module consists of a vectored slave and master interface\n//     in which all slots are sized and synchronized to the native width and clock \n//     of the interconnect.\n//   The SAMD axi_crossbar_v2_1_23_crossbar supports only AXI4 and AXI3 protocols.\n//   All width, clock and protocol conversions are done outside this block, as are\n//     any pipeline registers or data FIFOs.\n//   This module contains all arbitration, decoders and channel multiplexing logic.\n//     It also contains the diagnostic registers and control interface.\n//\n//-----------------------------------------------------------------------------\n//\n// Structure:\n//    crossbar\n//      si_transactor\n//        addr_decoder\n//          comparator_static\n//        mux_enc\n//        axic_srl_fifo\n//        arbiter_resp\n//      splitter\n//      wdata_router\n//        axic_reg_srl_fifo\n//      wdata_mux\n//        axic_reg_srl_fifo\n//        mux_enc\n//      addr_decoder\n//        comparator_static\n//      axic_srl_fifo\n//      axi_register_slice\n//      addr_arbiter\n//        mux_enc\n//      decerr_slave\n//      \n//-----------------------------------------------------------------------------\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_crossbar #\n  (\n   parameter         C_FAMILY                       = \"none\", \n   parameter integer C_NUM_SLAVE_SLOTS              =   1, \n   parameter integer C_NUM_MASTER_SLOTS             =   1, \n   parameter integer C_NUM_ADDR_RANGES              = 1,\n   parameter integer C_AXI_ID_WIDTH                   = 1, \n   parameter integer C_AXI_ADDR_WIDTH                 = 32, \n   parameter integer C_AXI_DATA_WIDTH = 32, \n   parameter integer C_AXI_PROTOCOL           = 0, \n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}}, \n   parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},\n   parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}}, \n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 1,\n   parameter integer C_AXI_ARUSER_WIDTH = 1,\n   parameter integer C_AXI_WUSER_WIDTH = 1,\n   parameter integer C_AXI_RUSER_WIDTH = 1,\n   parameter integer C_AXI_BUSER_WIDTH = 1,\n   parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE           = {C_NUM_SLAVE_SLOTS{1'b1}}, \n   parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ            = {C_NUM_SLAVE_SLOTS{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE           = {C_NUM_MASTER_SLOTS{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ            = {C_NUM_MASTER_SLOTS{1'b1}}, \n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1'b1}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1'b1}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD                 = {C_NUM_SLAVE_SLOTS{32'h00000000}}, \n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE         = {C_NUM_SLAVE_SLOTS{32'h00000001}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE          = {C_NUM_SLAVE_SLOTS{32'h00000001}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING            = {C_NUM_MASTER_SLOTS{32'h00000001}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING            = {C_NUM_MASTER_SLOTS{32'h00000001}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY             = {C_NUM_SLAVE_SLOTS{32'h00000000}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE                   = {C_NUM_MASTER_SLOTS{32'h00000000}},\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE            = {C_NUM_MASTER_SLOTS{32'h00000000}},\n   parameter integer C_RANGE_CHECK                    = 0,\n   parameter integer C_ADDR_DECODE                    = 0,\n   parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_W_ISSUE_WIDTH  = {C_NUM_MASTER_SLOTS+1{32'h00000000}},\n   parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_R_ISSUE_WIDTH  = {C_NUM_MASTER_SLOTS+1{32'h00000000}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_W_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}},\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_R_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}},\n   parameter integer C_DEBUG              = 1\n   )\n  (\n   // Global Signals\n   input  wire                                                    ACLK,\n   input  wire                                                    ARESETN,\n   // Slave Interface Write Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_AWID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           S_AXI_AWADDR,\n   input  wire [C_NUM_SLAVE_SLOTS*8-1:0]                          S_AXI_AWLEN,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_AWSIZE,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_AWBURST,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_AWLOCK,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWCACHE,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_AWPROT,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWREGION,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWQOS,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0]         S_AXI_AWUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_AWVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_AWREADY,\n   // Slave Interface Write Data Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_WID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]     S_AXI_WDATA,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0]   S_AXI_WSTRB,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WLAST,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0]          S_AXI_WUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WREADY,\n   // Slave Interface Write Response Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_BID,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_BRESP,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_BVALID,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_BREADY,\n   // Slave Interface Read Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_ARID,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           S_AXI_ARADDR,\n   input  wire [C_NUM_SLAVE_SLOTS*8-1:0]                          S_AXI_ARLEN,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_ARSIZE,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_ARBURST,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_ARLOCK,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARCACHE,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_ARPROT,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARREGION,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARQOS,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0]         S_AXI_ARUSER,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_ARVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_ARREADY,\n   // Slave Interface Read Data Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_RID,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]     S_AXI_RDATA,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_RRESP,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RLAST,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0]          S_AXI_RUSER,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RVALID,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RREADY,\n   // Master Interface Write Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_AWID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          M_AXI_AWADDR,\n   output wire [C_NUM_MASTER_SLOTS*8-1:0]                         M_AXI_AWLEN,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_AWSIZE,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_AWBURST,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_AWLOCK,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWCACHE,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_AWPROT,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWREGION,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWQOS,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0]        M_AXI_AWUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_AWVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_AWREADY,\n   // Master Interface Write Data Ports\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_WID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]    M_AXI_WDATA,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0]  M_AXI_WSTRB,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WLAST,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0]         M_AXI_WUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WREADY,\n   // Master Interface Write Response Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_BID,\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_BRESP,\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0]         M_AXI_BUSER,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_BVALID,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_BREADY,\n   // Master Interface Read Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_ARID,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          M_AXI_ARADDR,\n   output wire [C_NUM_MASTER_SLOTS*8-1:0]                         M_AXI_ARLEN,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_ARSIZE,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_ARBURST,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_ARLOCK,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARCACHE,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_ARPROT,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARREGION,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARQOS,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0]        M_AXI_ARUSER,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_ARVALID,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_ARREADY,\n   // Master Interface Read Data Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_RID,\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]    M_AXI_RDATA,\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_RRESP,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RLAST,\n   input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0]         M_AXI_RUSER,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RVALID,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RREADY\n   );\n   \n  localparam integer  P_AXI4 = 0;\n  localparam integer  P_AXI3 = 1;\n  localparam integer  P_AXILITE = 2;\n  localparam integer P_WRITE = 0;\n  localparam integer P_READ = 1;\n  localparam integer P_NUM_MASTER_SLOTS_LOG = f_ceil_log2(C_NUM_MASTER_SLOTS);\n  localparam integer P_NUM_SLAVE_SLOTS_LOG = f_ceil_log2((C_NUM_SLAVE_SLOTS>1) ? C_NUM_SLAVE_SLOTS : 2);\n  localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1;\n  localparam integer P_ST_AWMESG_WIDTH = 2+4+4 + C_AXI_AWUSER_WIDTH;\n  localparam integer P_AA_AWMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_AWMESG_WIDTH;\n  localparam integer P_ST_ARMESG_WIDTH = 2+4+4 + C_AXI_ARUSER_WIDTH;\n  localparam integer P_AA_ARMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_ARMESG_WIDTH;\n  localparam integer P_ST_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH;\n  localparam integer P_ST_RMESG_WIDTH = 2 + C_AXI_RUSER_WIDTH + C_AXI_DATA_WIDTH;\n  localparam integer P_WR_WMESG_WIDTH = C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH;\n  localparam [31:0] P_BYPASS  = 32'h00000000;\n  localparam [31:0] P_FWD_REV = 32'h00000001;\n  localparam [31:0] P_SIMPLE  = 32'h00000007;\n  localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_READ = {1'b1, C_M_AXI_SUPPORTS_READ[0+:C_NUM_MASTER_SLOTS]};\n  localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_WRITE = {1'b1, C_M_AXI_SUPPORTS_WRITE[0+:C_NUM_MASTER_SLOTS]};\n  localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_WRITE_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]};\n  localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_READ_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]};\n  localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_WRITE_CONNECTIVITY = f_si_write_connectivity(0);\n  localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_READ_CONNECTIVITY = f_si_read_connectivity(0);\n  localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_ISSUING = {32'h00000001, C_M_AXI_READ_ISSUING[0+:C_NUM_MASTER_SLOTS*32]};\n  localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_ISSUING = {32'h00000001, C_M_AXI_WRITE_ISSUING[0+:C_NUM_MASTER_SLOTS*32]};\n  localparam P_DECERR = 2'b11;\n\n  //---------------------------------------------------------------------------\n  // Functions\n  //---------------------------------------------------------------------------\n  // Ceiling of log2(x)\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  // Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value\n  //   only for end-point SI-slots\n  function [C_AXI_ID_WIDTH-1:0] f_extend_ID\n    (\n     input [C_AXI_ID_WIDTH-1:0] s_id,\n     input integer slot\n     );\n    begin\n      f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH]));\n    end\n  endfunction\n\n  // Write connectivity array transposed\n  function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_write_connectivity\n    (\n      input integer null_arg\n     );\n    integer si_slot;\n    integer mi_slot;\n    reg  [C_NUM_SLAVE_SLOTS*32-1:0]  result;\n    begin\n      result = {C_NUM_SLAVE_SLOTS*32{1'b1}};\n      for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin\n        for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin\n          result[si_slot*32+mi_slot] = C_M_AXI_WRITE_CONNECTIVITY[mi_slot*32+si_slot];\n        end\n      end\n    f_si_write_connectivity = result;\n    end\n  endfunction\n\n  // Read connectivity array transposed\n  function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_read_connectivity\n    (\n      input integer null_arg\n     );\n    integer si_slot;\n    integer mi_slot;\n    reg  [C_NUM_SLAVE_SLOTS*32-1:0]  result;\n    begin\n      result = {C_NUM_SLAVE_SLOTS*32{1'b1}};\n      for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin\n        for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin\n          result[si_slot*32+mi_slot] = C_M_AXI_READ_CONNECTIVITY[mi_slot*32+si_slot];\n        end\n      end\n    f_si_read_connectivity = result;\n    end\n  endfunction\n\n  genvar gen_si_slot;\n  genvar gen_mi_slot;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0]                  si_st_awmesg          ;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0]                  st_tmp_awmesg         ;\n  wire [C_NUM_SLAVE_SLOTS*P_AA_AWMESG_WIDTH-1:0]                  tmp_aa_awmesg         ;\n  wire [P_AA_AWMESG_WIDTH-1:0]                                    aa_mi_awmesg          ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]                     st_aa_awid            ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]                   st_aa_awaddr          ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                                  st_aa_awlen           ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                                  st_aa_awsize          ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                                  st_aa_awlock          ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                                  st_aa_awprot          ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                                  st_aa_awregion        ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                                  st_aa_awerror         ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_aa_awtarget_hot    ;\n  wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0]         st_aa_awtarget_enc    ;\n  wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0]                              aa_wm_awgrant_enc     ;\n  wire [(C_NUM_MASTER_SLOTS+1)-1:0]                               aa_mi_awtarget_hot    ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_aa_awvalid_qual    ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_ss_awvalid         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_ss_awready         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  ss_wr_awvalid         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  ss_wr_awready         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  ss_aa_awvalid         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  ss_aa_awready         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             sa_wm_awvalid         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             sa_wm_awready         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_awvalid            ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_awready            ;\n  wire                                                            aa_sa_awvalid         ;\n  wire                                                            aa_sa_awready         ;\n  wire                                                            aa_mi_arready         ;\n  wire                                                            mi_awvalid_en         ;\n  wire                                                            sa_wm_awvalid_en      ;\n  wire                                                            sa_wm_awready_mux     ;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0]                  si_st_armesg          ;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0]                  st_tmp_armesg         ;\n  wire [C_NUM_SLAVE_SLOTS*P_AA_ARMESG_WIDTH-1:0]                  tmp_aa_armesg         ;\n  wire [P_AA_ARMESG_WIDTH-1:0]                                    aa_mi_armesg          ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]                     st_aa_arid            ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]                   st_aa_araddr          ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                                  st_aa_arlen           ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                                  st_aa_arsize          ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                                  st_aa_arlock          ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                                  st_aa_arprot          ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                                  st_aa_arregion        ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                                  st_aa_arerror         ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_aa_artarget_hot    ;\n  wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0]         st_aa_artarget_enc    ;\n  wire [(C_NUM_MASTER_SLOTS+1)-1:0]                               aa_mi_artarget_hot    ;\n  wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0]                              aa_mi_argrant_enc     ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_aa_arvalid_qual    ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_aa_arvalid         ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_aa_arready         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_arvalid            ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_arready            ;\n  wire                                                            aa_mi_arvalid         ;\n  wire                                                            mi_awready_mux        ;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_BMESG_WIDTH-1:0]                   st_si_bmesg           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*P_ST_BMESG_WIDTH-1:0]              st_mr_bmesg           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                st_mr_bid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*2-1:0]                             st_mr_bresp           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0]             st_mr_buser           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_bvalid          ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_bready          ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_tmp_bready         ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_tmp_bid_target     ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0]             tmp_mr_bid_target     ;\n  wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0]         debug_bid_target_i    ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             bid_match             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                mi_bid                ;\n  wire [(C_NUM_MASTER_SLOTS+1)*2-1:0]                             mi_bresp              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0]             mi_buser              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_bvalid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_bready             ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             bready_carry          ;\n  wire [C_NUM_SLAVE_SLOTS*P_ST_RMESG_WIDTH-1:0]                   st_si_rmesg           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*P_ST_RMESG_WIDTH-1:0]              st_mr_rmesg           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                st_mr_rid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0]     st_mr_rdata           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0]             st_mr_ruser           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_rlast           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*2-1:0]                             st_mr_rresp           ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_rvalid          ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_rready          ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_tmp_rready         ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_tmp_rid_target     ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0]             tmp_mr_rid_target     ;\n  wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0]         debug_rid_target_i    ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             rid_match             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                mi_rid                ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0]          mi_rdata              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0]             mi_ruser              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_rlast              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*2-1:0]                             mi_rresp              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_rvalid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_rready             ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             rready_carry          ;\n  wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0]                   si_wr_wmesg           ;\n  wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0]                   wr_wm_wmesg           ;\n  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  wr_wm_wlast           ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             wr_tmp_wvalid         ;\n  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             wr_tmp_wready         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0]             tmp_wm_wvalid         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0]             tmp_wm_wready         ;\n  wire [(C_NUM_MASTER_SLOTS+1)*P_WR_WMESG_WIDTH-1:0]              wm_mr_wmesg              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0]          wm_mr_wdata              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0]        wm_mr_wstrb              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                wm_mr_wid              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0]             wm_mr_wuser              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             wm_mr_wlast              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             wm_mr_wvalid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             wm_mr_wready             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0]          mi_wdata              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0]        mi_wstrb              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0]             mi_wuser              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                mi_wid              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_wlast              ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_wvalid             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_wready             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             w_cmd_push            ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             w_cmd_pop             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             r_cmd_push            ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             r_cmd_pop             ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_awmaxissuing      ;\n  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_armaxissuing      ;\n  reg  [(C_NUM_MASTER_SLOTS+1)*8-1:0]                             w_issuing_cnt        ;\n  reg  [(C_NUM_MASTER_SLOTS+1)*8-1:0]                             r_issuing_cnt        ;\n  reg  [8-1:0]                                                    debug_aw_trans_seq_i    ;\n  reg  [8-1:0]                                                    debug_ar_trans_seq_i    ;\n  wire [(C_NUM_MASTER_SLOTS+1)*8-1:0]                             debug_w_trans_seq_i     ;\n  reg  [(C_NUM_MASTER_SLOTS+1)*8-1:0]                             debug_w_beat_cnt_i      ;\n\n  reg aresetn_d = 1'b0; // Reset delay register\n  always @(posedge ACLK) begin\n    if (~ARESETN) begin\n      aresetn_d <= 1'b0;\n    end else begin\n      aresetn_d <= ARESETN;\n    end\n  end\n  wire reset;\n  assign reset = ~aresetn_d;\n\n  generate\n    for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_slave_slots\n      if (C_S_AXI_SUPPORTS_READ[gen_si_slot]) begin : gen_si_read\n        axi_crossbar_v2_1_23_si_transactor #  // \"ST\": SI Transactor (read channel)\n          (\n           .C_FAMILY                (C_FAMILY),\n           .C_SI                    (gen_si_slot),\n           .C_DIR                   (P_READ),\n           .C_NUM_ADDR_RANGES       (C_NUM_ADDR_RANGES),\n           .C_NUM_M                 (C_NUM_MASTER_SLOTS),\n           .C_NUM_M_LOG             (P_NUM_MASTER_SLOTS_LOG),\n           .C_ACCEPTANCE            (C_S_AXI_READ_ACCEPTANCE[gen_si_slot*32+:32]),\n           .C_ACCEPTANCE_LOG        (C_R_ACCEPT_WIDTH[gen_si_slot*32+:32]),\n           .C_ID_WIDTH              (C_AXI_ID_WIDTH),\n           .C_THREAD_ID_WIDTH       (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]),\n           .C_ADDR_WIDTH            (C_AXI_ADDR_WIDTH),\n           .C_AMESG_WIDTH           (P_ST_ARMESG_WIDTH),\n           .C_RMESG_WIDTH           (P_ST_RMESG_WIDTH),\n           .C_BASE_ID               (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),\n           .C_HIGH_ID               (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),\n           .C_SINGLE_THREAD         (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]),\n           .C_BASE_ADDR             (C_M_AXI_BASE_ADDR),\n           .C_HIGH_ADDR             (C_M_AXI_HIGH_ADDR),\n           .C_TARGET_QUAL           (P_S_AXI_READ_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]),\n           .C_M_AXI_SECURE          (C_M_AXI_SECURE),\n           .C_RANGE_CHECK           (C_RANGE_CHECK),\n           .C_ADDR_DECODE           (C_ADDR_DECODE),\n           .C_ERR_MODE              (C_M_AXI_ERR_MODE),\n           .C_DEBUG                 (C_DEBUG)\n           )\n          si_transactor_ar\n            (\n             .ACLK                  (ACLK),\n             .ARESET                (reset),\n             .S_AID                 (f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)),\n             .S_AADDR               (S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),\n             .S_ALEN                (S_AXI_ARLEN[gen_si_slot*8+:8]),\n             .S_ASIZE               (S_AXI_ARSIZE[gen_si_slot*3+:3]),\n             .S_ABURST              (S_AXI_ARBURST[gen_si_slot*2+:2]),\n             .S_ALOCK               (S_AXI_ARLOCK[gen_si_slot*2+:2]),\n             .S_APROT               (S_AXI_ARPROT[gen_si_slot*3+:3]),\n//             .S_AREGION             (S_AXI_ARREGION[gen_si_slot*4+:4]),\n             .S_AMESG               (si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]),\n             .S_AVALID              (S_AXI_ARVALID[gen_si_slot]),\n             .S_AREADY              (S_AXI_ARREADY[gen_si_slot]),\n             .M_AID                 (st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n             .M_AADDR               (st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),\n             .M_ALEN                (st_aa_arlen[gen_si_slot*8+:8]),\n             .M_ASIZE               (st_aa_arsize[gen_si_slot*3+:3]),\n             .M_ALOCK               (st_aa_arlock[gen_si_slot*2+:2]),\n             .M_APROT               (st_aa_arprot[gen_si_slot*3+:3]),\n             .M_AREGION             (st_aa_arregion[gen_si_slot*4+:4]),\n             .M_AMESG               (st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]),\n             .M_ATARGET_HOT         (st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .M_ATARGET_ENC         (st_aa_artarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),\n             .M_AERROR              (st_aa_arerror[gen_si_slot*8+:8]),\n             .M_AVALID_QUAL         (st_aa_arvalid_qual[gen_si_slot]),\n             .M_AVALID              (st_aa_arvalid[gen_si_slot]),\n             .M_AREADY              (st_aa_arready[gen_si_slot]),\n             .S_RID                 (S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n             .S_RMESG               (st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH]),\n             .S_RLAST               (S_AXI_RLAST[gen_si_slot]),\n             .S_RVALID              (S_AXI_RVALID[gen_si_slot]),\n             .S_RREADY              (S_AXI_RREADY[gen_si_slot]),\n             .M_RID                 (st_mr_rid),\n             .M_RLAST               (st_mr_rlast),\n             .M_RMESG               (st_mr_rmesg),\n             .M_RVALID              (st_mr_rvalid),\n             .M_RREADY              (st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .M_RTARGET             (st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .DEBUG_A_TRANS_SEQ     (C_DEBUG ? debug_ar_trans_seq_i : 8'h0)\n             );\n        \n        assign si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH] = {\n          S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH],\n          S_AXI_ARQOS[gen_si_slot*4+:4],\n          S_AXI_ARCACHE[gen_si_slot*4+:4],\n          S_AXI_ARBURST[gen_si_slot*2+:2]\n          };\n        assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = {\n          st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH],\n          st_aa_arregion[gen_si_slot*4+:4],\n          st_aa_arprot[gen_si_slot*3+:3],\n          st_aa_arlock[gen_si_slot*2+:2],\n          st_aa_arsize[gen_si_slot*3+:3],\n          st_aa_arlen[gen_si_slot*8+:8],\n          st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH],\n          st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]\n          };\n        assign S_AXI_RRESP[gen_si_slot*2+:2] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:2];\n        assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2 +: C_AXI_RUSER_WIDTH];\n        assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2+C_AXI_RUSER_WIDTH +: C_AXI_DATA_WIDTH];\n      end else begin : gen_no_si_read\n        assign S_AXI_ARREADY[gen_si_slot] = 1'b0;\n        assign st_aa_arvalid[gen_si_slot] = 1'b0;\n        assign st_aa_arvalid_qual[gen_si_slot] = 1'b1;\n        assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = 0;\n        assign S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;\n        assign S_AXI_RRESP[gen_si_slot*2+:2] = 0;\n        assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = 0;\n        //assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0;\n        assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = {C_AXI_DATA_WIDTH/32{32'hDEC0_DE1C}};\n        assign S_AXI_RVALID[gen_si_slot] = 1'b0;\n        assign S_AXI_RLAST[gen_si_slot] = 1'b0;\n        assign st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;\n        assign st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;\n      end  // gen_si_read\n        \n      if (C_S_AXI_SUPPORTS_WRITE[gen_si_slot]) begin : gen_si_write\n        axi_crossbar_v2_1_23_si_transactor #  // \"ST\": SI Transactor (write channel)\n          (\n           .C_FAMILY                (C_FAMILY),\n           .C_SI                    (gen_si_slot),\n           .C_DIR                   (P_WRITE),\n           .C_NUM_ADDR_RANGES       (C_NUM_ADDR_RANGES),\n           .C_NUM_M                 (C_NUM_MASTER_SLOTS),\n           .C_NUM_M_LOG             (P_NUM_MASTER_SLOTS_LOG),\n           .C_ACCEPTANCE            (C_S_AXI_WRITE_ACCEPTANCE[gen_si_slot*32+:32]),\n           .C_ACCEPTANCE_LOG        (C_W_ACCEPT_WIDTH[gen_si_slot*32+:32]),\n           .C_ID_WIDTH              (C_AXI_ID_WIDTH),\n           .C_THREAD_ID_WIDTH       (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]),\n           .C_ADDR_WIDTH            (C_AXI_ADDR_WIDTH),\n           .C_AMESG_WIDTH           (P_ST_AWMESG_WIDTH),\n           .C_RMESG_WIDTH           (P_ST_BMESG_WIDTH),\n           .C_BASE_ID               (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),\n           .C_HIGH_ID               (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),\n           .C_SINGLE_THREAD         (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]),\n           .C_BASE_ADDR             (C_M_AXI_BASE_ADDR),\n           .C_HIGH_ADDR             (C_M_AXI_HIGH_ADDR),\n           .C_TARGET_QUAL           (P_S_AXI_WRITE_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]),\n           .C_M_AXI_SECURE          (C_M_AXI_SECURE),\n           .C_RANGE_CHECK           (C_RANGE_CHECK),\n           .C_ADDR_DECODE           (C_ADDR_DECODE),\n           .C_ERR_MODE              (C_M_AXI_ERR_MODE),\n           .C_DEBUG                 (C_DEBUG)\n           )\n          si_transactor_aw\n            (\n             .ACLK                  (ACLK),\n             .ARESET                (reset),\n             .S_AID                 (f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)),\n             .S_AADDR               (S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),\n             .S_ALEN                (S_AXI_AWLEN[gen_si_slot*8+:8]),\n             .S_ASIZE               (S_AXI_AWSIZE[gen_si_slot*3+:3]),\n             .S_ABURST              (S_AXI_AWBURST[gen_si_slot*2+:2]),\n             .S_ALOCK               (S_AXI_AWLOCK[gen_si_slot*2+:2]),\n             .S_APROT               (S_AXI_AWPROT[gen_si_slot*3+:3]),\n//             .S_AREGION             (S_AXI_AWREGION[gen_si_slot*4+:4]),\n             .S_AMESG               (si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]),\n             .S_AVALID              (S_AXI_AWVALID[gen_si_slot]),\n             .S_AREADY              (S_AXI_AWREADY[gen_si_slot]),\n             .M_AID                 (st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n             .M_AADDR               (st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),\n             .M_ALEN                (st_aa_awlen[gen_si_slot*8+:8]),\n             .M_ASIZE               (st_aa_awsize[gen_si_slot*3+:3]),\n             .M_ALOCK               (st_aa_awlock[gen_si_slot*2+:2]),\n             .M_APROT               (st_aa_awprot[gen_si_slot*3+:3]),\n             .M_AREGION             (st_aa_awregion[gen_si_slot*4+:4]),\n             .M_AMESG               (st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]),\n             .M_ATARGET_HOT         (st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .M_ATARGET_ENC         (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),\n             .M_AERROR              (st_aa_awerror[gen_si_slot*8+:8]),\n             .M_AVALID_QUAL         (st_aa_awvalid_qual[gen_si_slot]),\n             .M_AVALID              (st_ss_awvalid[gen_si_slot]),\n             .M_AREADY              (st_ss_awready[gen_si_slot]),\n             .S_RID                 (S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n             .S_RMESG               (st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH]),\n             .S_RLAST               (),\n             .S_RVALID              (S_AXI_BVALID[gen_si_slot]),\n             .S_RREADY              (S_AXI_BREADY[gen_si_slot]),\n             .M_RID                 (st_mr_bid),\n             .M_RLAST               ({(C_NUM_MASTER_SLOTS+1){1'b1}}),\n             .M_RMESG               (st_mr_bmesg),\n             .M_RVALID              (st_mr_bvalid),\n             .M_RREADY              (st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .M_RTARGET             (st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .DEBUG_A_TRANS_SEQ     (C_DEBUG ? debug_aw_trans_seq_i : 8'h0)\n             );\n        \n        // Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.\n        assign si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH] = {\n          S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH],\n          S_AXI_AWQOS[gen_si_slot*4+:4],\n          S_AXI_AWCACHE[gen_si_slot*4+:4],\n          S_AXI_AWBURST[gen_si_slot*2+:2]\n          };\n        assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = {\n          st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH],\n          st_aa_awregion[gen_si_slot*4+:4],\n          st_aa_awprot[gen_si_slot*3+:3],\n          st_aa_awlock[gen_si_slot*2+:2],\n          st_aa_awsize[gen_si_slot*3+:3],\n          st_aa_awlen[gen_si_slot*8+:8],\n          st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH],\n          st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]\n          };\n        assign S_AXI_BRESP[gen_si_slot*2+:2] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:2];\n        assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+2 +: C_AXI_BUSER_WIDTH];\n                       \n        // AW SI-transactor transfer completes upon completion of both W-router address acceptance (command push) and AW arbitration\n        axi_crossbar_v2_1_23_splitter #  // \"SS\": Splitter from SI-Transactor (write channel)\n          (\n            .C_NUM_M                (2)\n          )\n          splitter_aw_si\n          (\n             .ACLK                  (ACLK),\n             .ARESET                (reset),\n             .S_VALID              (st_ss_awvalid[gen_si_slot]),\n             .S_READY              (st_ss_awready[gen_si_slot]),\n             .M_VALID              ({ss_wr_awvalid[gen_si_slot], ss_aa_awvalid[gen_si_slot]}),\n             .M_READY              ({ss_wr_awready[gen_si_slot], ss_aa_awready[gen_si_slot]})\n          );\n      \n        axi_crossbar_v2_1_23_wdata_router #  // \"WR\": Write data Router\n          (\n           .C_FAMILY                   (C_FAMILY),\n           .C_NUM_MASTER_SLOTS         (C_NUM_MASTER_SLOTS+1),\n           .C_SELECT_WIDTH             (P_NUM_MASTER_SLOTS_LOG+1),\n           .C_WMESG_WIDTH               (P_WR_WMESG_WIDTH),\n           .C_FIFO_DEPTH_LOG           (C_W_ACCEPT_WIDTH[gen_si_slot*32+:6])\n           )\n          wdata_router_w\n            (\n             .ACLK    (ACLK),\n             .ARESET  (reset),\n             // Write transfer input from the current SI-slot\n             .S_WMESG  (si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]),\n             .S_WLAST  (S_AXI_WLAST[gen_si_slot]),\n             .S_WVALID (S_AXI_WVALID[gen_si_slot]),\n             .S_WREADY (S_AXI_WREADY[gen_si_slot]),\n             // Vector of write transfer outputs to each MI-slot's W-mux\n             .M_WMESG  (wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH]),\n             .M_WLAST  (wr_wm_wlast[gen_si_slot]),\n             .M_WVALID (wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             .M_WREADY (wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),\n             // AW command push from local SI-slot\n             .S_ASELECT (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),  // Target MI-slot\n             .S_AVALID  (ss_wr_awvalid[gen_si_slot]),\n             .S_AREADY  (ss_wr_awready[gen_si_slot])\n             );\n             \n        assign si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH] = {\n          ((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1'b0),\n          S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH],\n          S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8],\n          S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]\n        };        \n      end else begin : gen_no_si_write\n        assign S_AXI_AWREADY[gen_si_slot] = 1'b0;\n        assign ss_aa_awvalid[gen_si_slot] = 1'b0;\n        assign st_aa_awvalid_qual[gen_si_slot] = 1'b1;\n        assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = 0;\n        assign S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;\n        assign S_AXI_BRESP[gen_si_slot*2+:2] = 0;\n        assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = 0;\n        assign S_AXI_BVALID[gen_si_slot] = 1'b0;\n        assign st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;\n        assign S_AXI_WREADY[gen_si_slot] = 1'b0;\n        assign wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH] = 0;\n        assign wr_wm_wlast[gen_si_slot] = 1'b0;\n        assign wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;\n        assign st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;\n      end  // gen_si_write\n    end  // gen_slave_slots\n    \n    for (gen_mi_slot=0; gen_mi_slot<C_NUM_MASTER_SLOTS+1; gen_mi_slot=gen_mi_slot+1) begin : gen_master_slots\n      if (P_M_AXI_SUPPORTS_READ[gen_mi_slot]) begin : gen_mi_read\n        if (C_NUM_SLAVE_SLOTS>1) begin : gen_rid_decoder\n          axi_crossbar_v2_1_23_addr_decoder #\n            (\n              .C_FAMILY          (C_FAMILY),\n              .C_NUM_TARGETS     (C_NUM_SLAVE_SLOTS),\n              .C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG),\n              .C_NUM_RANGES      (1),\n              .C_ADDR_WIDTH      (C_AXI_ID_WIDTH),\n              .C_TARGET_ENC      (C_DEBUG),\n              .C_TARGET_HOT      (1),\n              .C_REGION_ENC      (0),\n              .C_BASE_ADDR       (C_S_AXI_BASE_ID),\n              .C_HIGH_ADDR       (C_S_AXI_HIGH_ID),\n              .C_TARGET_QUAL     (P_M_AXI_READ_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]),\n              .C_RESOLUTION      (0)\n            ) \n            rid_decoder_inst \n            (\n              .ADDR             (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),        \n              .TARGET_HOT       (tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),  \n              .TARGET_ENC       (debug_rid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]),  \n              .MATCH            (rid_match[gen_mi_slot]),       \n              .REGION           ()      \n            );\n        end else begin : gen_no_rid_decoder\n          assign tmp_mr_rid_target[gen_mi_slot] = 1'b1;  // All response transfers route to solo SI-slot.\n          assign rid_match[gen_mi_slot] = 1'b1;\n        end\n        \n        assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = {\n          st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],\n          st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH], \n          st_mr_rresp[gen_mi_slot*2+:2]\n          }; \n      end else begin : gen_no_mi_read\n        assign tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;\n        assign rid_match[gen_mi_slot] = 1'b0;\n        assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = 0;\n      end  // gen_mi_read\n      \n      if (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot]) begin : gen_mi_write\n        if (C_NUM_SLAVE_SLOTS>1) begin : gen_bid_decoder\n          axi_crossbar_v2_1_23_addr_decoder #\n            (\n              .C_FAMILY          (C_FAMILY),\n              .C_NUM_TARGETS     (C_NUM_SLAVE_SLOTS),\n              .C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG),\n              .C_NUM_RANGES      (1),\n              .C_ADDR_WIDTH      (C_AXI_ID_WIDTH),\n              .C_TARGET_ENC      (C_DEBUG),\n              .C_TARGET_HOT      (1),\n              .C_REGION_ENC      (0),\n              .C_BASE_ADDR       (C_S_AXI_BASE_ID),\n              .C_HIGH_ADDR       (C_S_AXI_HIGH_ID),\n              .C_TARGET_QUAL     (P_M_AXI_WRITE_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]),\n              .C_RESOLUTION      (0)\n            ) \n            bid_decoder_inst \n            (\n              .ADDR             (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),        \n              .TARGET_HOT       (tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),  \n              .TARGET_ENC       (debug_bid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]),  \n              .MATCH            (bid_match[gen_mi_slot]),       \n              .REGION           ()      \n            );\n        end else begin : gen_no_bid_decoder\n          assign tmp_mr_bid_target[gen_mi_slot] = 1'b1;  // All response transfers route to solo SI-slot.\n          assign bid_match[gen_mi_slot] = 1'b1;\n        end\n      \n        axi_crossbar_v2_1_23_wdata_mux #  // \"WM\": Write data Mux, per MI-slot (incl error-handler)\n          (\n           .C_FAMILY                   (C_FAMILY),\n           .C_NUM_SLAVE_SLOTS         (C_NUM_SLAVE_SLOTS),\n           .C_SELECT_WIDTH     (P_NUM_SLAVE_SLOTS_LOG),\n           .C_WMESG_WIDTH               (P_WR_WMESG_WIDTH),\n           .C_FIFO_DEPTH_LOG           (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6])\n           )\n          wdata_mux_w\n            (\n             .ACLK    (ACLK),\n             .ARESET  (reset),\n             // Vector of write transfer inputs from each SI-slot's W-router\n             .S_WMESG  (wr_wm_wmesg),\n             .S_WLAST  (wr_wm_wlast),\n             .S_WVALID (tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),\n             .S_WREADY (tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),\n             // Write transfer output to the current MI-slot\n             .M_WMESG  (wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]),\n             .M_WLAST  (wm_mr_wlast[gen_mi_slot]),\n             .M_WVALID (wm_mr_wvalid[gen_mi_slot]),\n             .M_WREADY (wm_mr_wready[gen_mi_slot]),\n             // AW command push from AW arbiter output\n             .S_ASELECT (aa_wm_awgrant_enc),  // SI-slot selected by arbiter\n             .S_AVALID  (sa_wm_awvalid[gen_mi_slot]),\n             .S_AREADY  (sa_wm_awready[gen_mi_slot])\n             );\n             \n        if (C_DEBUG) begin : gen_debug_w\n          // DEBUG WRITE BEAT COUNTER\n          always @(posedge ACLK) begin\n            if (reset) begin\n              debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0;\n            end else begin\n              if (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot]) begin\n                if (mi_wlast[gen_mi_slot]) begin\n                  debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0;\n                end else begin\n                  debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= debug_w_beat_cnt_i[gen_mi_slot*8+:8] + 1;\n                end\n              end\n            end\n          end  // clocked process\n  \n          // DEBUG W-CHANNEL TRANSACTION SEQUENCE QUEUE\n          axi_data_fifo_v2_1_21_axic_srl_fifo #\n            (\n             .C_FAMILY          (C_FAMILY),\n             .C_FIFO_WIDTH      (8),\n             .C_FIFO_DEPTH_LOG  (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]),\n             .C_USE_FULL        (0)\n             )\n            debug_w_seq_fifo\n              (\n               .ACLK    (ACLK),\n               .ARESET  (reset),\n               .S_MESG  (debug_aw_trans_seq_i),\n               .S_VALID (sa_wm_awvalid[gen_mi_slot]),\n               .S_READY (),\n               .M_MESG  (debug_w_trans_seq_i[gen_mi_slot*8+:8]),\n               .M_VALID (),\n               .M_READY (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot] & mi_wlast[gen_mi_slot])\n              );\n        end  // gen_debug_w\n             \n        assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH +: C_AXI_DATA_WIDTH];\n        assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8];\n        assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH];\n        assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+(C_AXI_DATA_WIDTH/8)+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH];\n        assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = {\n          st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH],\n          st_mr_bresp[gen_mi_slot*2+:2]\n          }; \n      end else begin : gen_no_mi_write\n        assign tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;\n        assign bid_match[gen_mi_slot] = 1'b0;\n        assign wm_mr_wvalid[gen_mi_slot] = 0;\n        assign wm_mr_wlast[gen_mi_slot] = 0;\n        assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0;\n        assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = 0;\n        assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = 0;\n        assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;\n        assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = 0;\n        assign tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;\n        assign sa_wm_awready[gen_mi_slot] = 0;\n      end  // gen_mi_write\n      \n      for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_trans_si\n        // Transpose handshakes from W-router (SxM) to W-mux (MxS).\n        assign tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot] = wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot];\n        assign wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];\n        // Transpose response enables from ID decoders (MxS) to si_transactors (SxM).\n        assign st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];\n        assign st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];\n      end  // gen_trans_si\n      \n      assign bready_carry[gen_mi_slot] =  st_tmp_bready[gen_mi_slot];\n      assign rready_carry[gen_mi_slot] =  st_tmp_rready[gen_mi_slot];\n      for (gen_si_slot=1; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_resp_carry_si\n        assign bready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] =  // Generate M_BREADY if ...\n          bready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] |  // For any SI-slot (OR carry-chain across all SI-slots), ...\n          st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot];  // The write SI transactor indicates BREADY for that MI-slot.\n        assign rready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] =  // Generate M_RREADY if ...\n          rready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] |  // For any SI-slot (OR carry-chain across all SI-slots), ...\n          st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot];  // The write SI transactor indicates RREADY for that MI-slot.\n      end  // gen_resp_carry_si\n           \n      assign w_cmd_push[gen_mi_slot] = mi_awvalid[gen_mi_slot] && mi_awready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot];\n      assign r_cmd_push[gen_mi_slot] = mi_arvalid[gen_mi_slot] && mi_arready[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot];\n      assign w_cmd_pop[gen_mi_slot] = st_mr_bvalid[gen_mi_slot] && st_mr_bready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot];\n      assign r_cmd_pop[gen_mi_slot] = st_mr_rvalid[gen_mi_slot] && st_mr_rready[gen_mi_slot] && st_mr_rlast[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot];\n      // Disqualify arbitration of SI-slot if targeted MI-slot has reached its issuing limit.\n      assign mi_awmaxissuing[gen_mi_slot] = (w_issuing_cnt[gen_mi_slot*8 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] == \n          P_M_AXI_WRITE_ISSUING[gen_mi_slot*32 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~w_cmd_pop[gen_mi_slot];\n      assign mi_armaxissuing[gen_mi_slot] = (r_issuing_cnt[gen_mi_slot*8 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] == \n          P_M_AXI_READ_ISSUING[gen_mi_slot*32 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~r_cmd_pop[gen_mi_slot];\n      \n      always @(posedge ACLK) begin\n        if (reset) begin\n          w_issuing_cnt[gen_mi_slot*8+:8] <= 0;  // Some high-order bits remain constant 0\n          r_issuing_cnt[gen_mi_slot*8+:8] <= 0;  // Some high-order bits remain constant 0\n        end else begin\n          if (w_cmd_push[gen_mi_slot] && ~w_cmd_pop[gen_mi_slot]) begin\n            w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1;\n          end else if (w_cmd_pop[gen_mi_slot] && ~w_cmd_push[gen_mi_slot] && (|w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin\n            w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1;\n          end\n          if (r_cmd_push[gen_mi_slot] && ~r_cmd_pop[gen_mi_slot]) begin\n            r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1;\n          end else if (r_cmd_pop[gen_mi_slot] && ~r_cmd_push[gen_mi_slot] && (|r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin\n            r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1;\n          end\n        end\n      end  // Clocked process\n      \n      // Reg-slice must break combinatorial path from M_BID and M_RID inputs to M_BREADY and M_RREADY outputs.\n      //   (See m_rready_i and m_resp_en combinatorial assignments in si_transactor.)\n      //   Reg-slice incurs +1 latency, but no bubble-cycles.\n      axi_register_slice_v2_1_22_axi_register_slice #  // \"MR\": MI-side R/B-channel Reg-slice, per MI-slot (pass-through if only 1 SI-slot configured)\n        (\n          .C_FAMILY                         (C_FAMILY),\n          .C_AXI_PROTOCOL                   ((C_AXI_PROTOCOL == P_AXI3) ? P_AXI3 : P_AXI4),\n          .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),\n          .C_AXI_ADDR_WIDTH                 (1),\n          .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),\n          .C_AXI_SUPPORTS_USER_SIGNALS      (C_AXI_SUPPORTS_USER_SIGNALS),\n          .C_AXI_AWUSER_WIDTH               (1),\n          .C_AXI_ARUSER_WIDTH               (1),\n          .C_AXI_WUSER_WIDTH                (C_AXI_WUSER_WIDTH),\n          .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),\n          .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),\n          .C_REG_CONFIG_AW                  (P_BYPASS),\n          .C_REG_CONFIG_AR                  (P_BYPASS),\n          .C_REG_CONFIG_W                   (P_BYPASS),\n          .C_REG_CONFIG_R                   (P_M_AXI_SUPPORTS_READ[gen_mi_slot] ? P_FWD_REV : P_BYPASS),\n          .C_REG_CONFIG_B                   (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot] ? P_SIMPLE : P_BYPASS)\n        )\n        reg_slice_mi \n        (\n          .aresetn                          (ARESETN),\n          .aclk                             (ACLK),\n          .s_axi_awid                       ({C_AXI_ID_WIDTH{1'b0}}),\n          .s_axi_awaddr                     ({1{1'b0}}),\n          .s_axi_awlen                      ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1'b0}}),\n          .s_axi_awsize                     ({3{1'b0}}),\n          .s_axi_awburst                    ({2{1'b0}}),\n          .s_axi_awlock                     ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1'b0}}),\n          .s_axi_awcache                    ({4{1'b0}}),\n          .s_axi_awprot                     ({3{1'b0}}),\n          .s_axi_awregion                   ({4{1'b0}}),\n          .s_axi_awqos                      ({4{1'b0}}),\n          .s_axi_awuser                     ({1{1'b0}}),\n          .s_axi_awvalid                    ({1{1'b0}}),\n          .s_axi_awready                    (),\n          .s_axi_wid                        (wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n          .s_axi_wdata                      (wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),\n          .s_axi_wstrb                      (wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]),\n          .s_axi_wlast                      (wm_mr_wlast[gen_mi_slot]),\n          .s_axi_wuser                      (wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]),\n          .s_axi_wvalid                     (wm_mr_wvalid[gen_mi_slot]),\n          .s_axi_wready                     (wm_mr_wready[gen_mi_slot]),\n          .s_axi_bid                        (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]         ),\n          .s_axi_bresp                      (st_mr_bresp[gen_mi_slot*2+:2]                                 ),\n          .s_axi_buser                      (st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] ),\n          .s_axi_bvalid                     (st_mr_bvalid[gen_mi_slot*1+:1]                                ),\n          .s_axi_bready                     (st_mr_bready[gen_mi_slot*1+:1]                                ),\n          .s_axi_arid                       ({C_AXI_ID_WIDTH{1'b0}}),\n          .s_axi_araddr                     ({1{1'b0}}),\n          .s_axi_arlen                      ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1'b0}}),\n          .s_axi_arsize                     ({3{1'b0}}),\n          .s_axi_arburst                    ({2{1'b0}}),\n          .s_axi_arlock                     ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1'b0}}),\n          .s_axi_arcache                    ({4{1'b0}}),\n          .s_axi_arprot                     ({3{1'b0}}),\n          .s_axi_arregion                   ({4{1'b0}}),\n          .s_axi_arqos                      ({4{1'b0}}),\n          .s_axi_aruser                     ({1{1'b0}}),\n          .s_axi_arvalid                    ({1{1'b0}}),\n          .s_axi_arready                    (),\n          .s_axi_rid                        (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                          ),\n          .s_axi_rdata                      (st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]  ),\n          .s_axi_rresp                      (st_mr_rresp[gen_mi_slot*2+:2]                                                  ),\n          .s_axi_rlast                      (st_mr_rlast[gen_mi_slot*1+:1]                                                  ),\n          .s_axi_ruser                      (st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                  ),\n          .s_axi_rvalid                     (st_mr_rvalid[gen_mi_slot*1+:1]                                                 ),\n          .s_axi_rready                     (st_mr_rready[gen_mi_slot*1+:1]                                                 ),\n          .m_axi_awid                       (),\n          .m_axi_awaddr                     (),\n          .m_axi_awlen                      (),\n          .m_axi_awsize                     (),\n          .m_axi_awburst                    (),\n          .m_axi_awlock                     (),\n          .m_axi_awcache                    (),\n          .m_axi_awprot                     (),\n          .m_axi_awregion                   (),\n          .m_axi_awqos                      (),\n          .m_axi_awuser                     (),\n          .m_axi_awvalid                    (),\n          .m_axi_awready                    ({1{1'b0}}),\n          .m_axi_wid                        (mi_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n          .m_axi_wdata                      (mi_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),\n          .m_axi_wstrb                      (mi_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]),\n          .m_axi_wlast                      (mi_wlast[gen_mi_slot]),\n          .m_axi_wuser                      (mi_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]),\n          .m_axi_wvalid                     (mi_wvalid[gen_mi_slot]),\n          .m_axi_wready                     (mi_wready[gen_mi_slot]),\n          .m_axi_bid                        (mi_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                          ),\n          .m_axi_bresp                      (mi_bresp[gen_mi_slot*2+:2]                                                  ),\n          .m_axi_buser                      (mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                  ),\n          .m_axi_bvalid                     (mi_bvalid[gen_mi_slot*1+:1]                                                 ),\n          .m_axi_bready                     (mi_bready[gen_mi_slot*1+:1]                                                 ),\n          .m_axi_arid                       (),\n          .m_axi_araddr                     (),\n          .m_axi_arlen                      (),\n          .m_axi_arsize                     (),\n          .m_axi_arburst                    (),\n          .m_axi_arlock                     (),\n          .m_axi_arcache                    (),\n          .m_axi_arprot                     (),\n          .m_axi_arregion                   (),\n          .m_axi_arqos                      (),\n          .m_axi_aruser                     (),\n          .m_axi_arvalid                    (),\n          .m_axi_arready                    ({1{1'b0}}),\n          .m_axi_rid                        (mi_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                          ),\n          .m_axi_rdata                      (mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]  ),\n          .m_axi_rresp                      (mi_rresp[gen_mi_slot*2+:2]                                                  ),\n          .m_axi_rlast                      (mi_rlast[gen_mi_slot*1+:1]                                                  ),\n          .m_axi_ruser                      (mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                  ),\n          .m_axi_rvalid                     (mi_rvalid[gen_mi_slot*1+:1]                                                 ),\n          .m_axi_rready                     (mi_rready[gen_mi_slot*1+:1]                                                 )\n        );\n    end  // gen_master_slots (Next gen_mi_slot)\n  \n    // Highest row of *ready_carry contains accumulated OR across all SI-slots, for each MI-slot.\n    assign st_mr_bready = bready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1]; \n    assign st_mr_rready = rready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1]; \n    // Assign MI-side B, R and W channel ports (exclude error handler signals).\n    assign mi_bid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_BID;\n    assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID; \n    assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP;\n    assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER;\n    assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS];\n    assign mi_rid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_RID;\n    assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST; \n    assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID; \n    assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP;\n    assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER;\n    assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA;\n    assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS];\n    assign M_AXI_WLAST = mi_wlast[0+:C_NUM_MASTER_SLOTS];\n    assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS];\n    assign M_AXI_WUSER = mi_wuser[0+:C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH];\n    assign M_AXI_WID = (C_AXI_PROTOCOL == P_AXI3) ? mi_wid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] : 0;\n    assign M_AXI_WDATA = mi_wdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH];\n    assign M_AXI_WSTRB = mi_wstrb[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8];\n    assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY;\n\n    axi_crossbar_v2_1_23_addr_arbiter #  // \"AA\": Addr Arbiter (AW channel)\n      (\n       .C_FAMILY                (C_FAMILY),\n       .C_NUM_M                 (C_NUM_MASTER_SLOTS+1),\n       .C_NUM_S                 (C_NUM_SLAVE_SLOTS),\n       .C_NUM_S_LOG             (P_NUM_SLAVE_SLOTS_LOG),\n       .C_MESG_WIDTH            (P_AA_AWMESG_WIDTH),\n       .C_ARB_PRIORITY          (C_S_AXI_ARB_PRIORITY)\n       )\n      addr_arbiter_aw\n        (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         // Vector of SI-side AW command request inputs\n         .S_MESG                (tmp_aa_awmesg),\n         .S_TARGET_HOT          (st_aa_awtarget_hot),\n         .S_VALID               (ss_aa_awvalid),\n         .S_VALID_QUAL          (st_aa_awvalid_qual),\n         .S_READY               (ss_aa_awready),\n         // Granted AW command output\n         .M_MESG                (aa_mi_awmesg),\n         .M_TARGET_HOT          (aa_mi_awtarget_hot),  // MI-slot targeted by granted command\n         .M_GRANT_ENC           (aa_wm_awgrant_enc),  // SI-slot index of granted command\n         .M_VALID               (aa_sa_awvalid),\n         .M_READY               (aa_sa_awready),\n         .ISSUING_LIMIT        (mi_awmaxissuing)\n        );\n         \n    // Broadcast AW transfer payload to all MI-slots\n    assign M_AXI_AWID        = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[0+:C_AXI_ID_WIDTH]}};\n    assign M_AXI_AWADDR      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}};\n    assign M_AXI_AWLEN       = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}};\n    assign M_AXI_AWSIZE      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}};\n    assign M_AXI_AWLOCK      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}};\n    assign M_AXI_AWPROT      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}};\n    assign M_AXI_AWREGION    = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}};\n    assign M_AXI_AWBURST     = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}};\n    assign M_AXI_AWCACHE     = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}};\n    assign M_AXI_AWQOS       = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}};\n    assign M_AXI_AWUSER      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_AWUSER_WIDTH]}};\n         \n    axi_crossbar_v2_1_23_addr_arbiter #  // \"AA\": Addr Arbiter (AR channel)\n      (\n       .C_FAMILY                (C_FAMILY),\n       .C_NUM_M                 (C_NUM_MASTER_SLOTS+1),\n       .C_NUM_S                 (C_NUM_SLAVE_SLOTS),\n       .C_NUM_S_LOG             (P_NUM_SLAVE_SLOTS_LOG),\n       .C_MESG_WIDTH            (P_AA_ARMESG_WIDTH),\n       .C_ARB_PRIORITY          (C_S_AXI_ARB_PRIORITY)\n       )\n      addr_arbiter_ar\n        (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         // Vector of SI-side AR command request inputs\n         .S_MESG                (tmp_aa_armesg),\n         .S_TARGET_HOT          (st_aa_artarget_hot),\n         .S_VALID_QUAL          (st_aa_arvalid_qual),\n         .S_VALID               (st_aa_arvalid),\n         .S_READY               (st_aa_arready),\n         // Granted AR command output\n         .M_MESG                (aa_mi_armesg),\n         .M_TARGET_HOT          (aa_mi_artarget_hot),  // MI-slot targeted by granted command\n         .M_GRANT_ENC           (aa_mi_argrant_enc),\n         .M_VALID               (aa_mi_arvalid),  // SI-slot index of granted command\n         .M_READY               (aa_mi_arready),\n         .ISSUING_LIMIT        (mi_armaxissuing)\n        );\n    \n    if (C_DEBUG) begin : gen_debug_trans_seq\n      // DEBUG WRITE TRANSACTION SEQUENCE COUNTER\n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_aw_trans_seq_i <= 1;\n        end else begin\n          if (aa_sa_awvalid && aa_sa_awready) begin\n            debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1;\n          end\n        end\n      end\n  \n      // DEBUG READ TRANSACTION SEQUENCE COUNTER\n      always @(posedge ACLK) begin\n        if (reset) begin\n          debug_ar_trans_seq_i <= 1;\n        end else begin\n          if (aa_mi_arvalid && aa_mi_arready) begin\n            debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1;\n          end\n        end\n      end\n    end  // gen_debug_trans_seq\n\n    // Broadcast AR transfer payload to all MI-slots\n    assign M_AXI_ARID        = {C_NUM_MASTER_SLOTS{aa_mi_armesg[0+:C_AXI_ID_WIDTH]}};\n    assign M_AXI_ARADDR      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}};\n    assign M_AXI_ARLEN       = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}};\n    assign M_AXI_ARSIZE      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}};\n    assign M_AXI_ARLOCK      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}};\n    assign M_AXI_ARPROT      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}};\n    assign M_AXI_ARREGION    = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}};\n    assign M_AXI_ARBURST     = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}};\n    assign M_AXI_ARCACHE     = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}};\n    assign M_AXI_ARQOS       = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}};\n    assign M_AXI_ARUSER      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_ARUSER_WIDTH]}};\n         \n    // AW arbiter command transfer completes upon completion of both M-side AW-channel transfer and W-mux address acceptance (command push).\n    axi_crossbar_v2_1_23_splitter #  // \"SA\": Splitter for Write Addr Arbiter\n      (\n        .C_NUM_M                (2)\n      )\n      splitter_aw_mi\n      (\n         .ACLK                  (ACLK),\n         .ARESET                (reset),\n         .S_VALID              (aa_sa_awvalid),\n         .S_READY              (aa_sa_awready),\n         .M_VALID              ({mi_awvalid_en, sa_wm_awvalid_en}),\n         .M_READY              ({mi_awready_mux, sa_wm_awready_mux})\n      );\n      \n    assign mi_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{mi_awvalid_en}};\n    assign mi_awready_mux = |(aa_mi_awtarget_hot & mi_awready);\n    assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS];  // Slot C_NUM_MASTER_SLOTS+1 is the error handler\n    assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY;\n    assign sa_wm_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{sa_wm_awvalid_en}};\n    assign sa_wm_awready_mux = |(aa_mi_awtarget_hot & sa_wm_awready);\n    \n    assign mi_arvalid = aa_mi_artarget_hot & {C_NUM_MASTER_SLOTS+1{aa_mi_arvalid}};\n    assign aa_mi_arready = |(aa_mi_artarget_hot & mi_arready);\n    assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS];  // Slot C_NUM_MASTER_SLOTS+1 is the error handler\n    assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY;\n    \n    // MI-slot # C_NUM_MASTER_SLOTS is the error handler\n    if (C_RANGE_CHECK) begin : gen_decerr_slave\n      axi_crossbar_v2_1_23_decerr_slave #\n        (\n         .C_AXI_ID_WIDTH                 (C_AXI_ID_WIDTH),\n         .C_AXI_DATA_WIDTH               (C_AXI_DATA_WIDTH),\n         .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),\n         .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),\n         .C_AXI_PROTOCOL                 (C_AXI_PROTOCOL),\n         .C_RESP                         (P_DECERR) \n        )\n        decerr_slave_inst\n          (\n           .S_AXI_ACLK (ACLK),\n           .S_AXI_ARESET (reset),\n           .S_AXI_AWID (aa_mi_awmesg[0+:C_AXI_ID_WIDTH]),\n           .S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_WLAST (mi_wlast[C_NUM_MASTER_SLOTS]),\n           .S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_BID (mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n           .S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]),\n           .S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]),\n           .S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_ARID (aa_mi_armesg[0+:C_AXI_ID_WIDTH]),\n           .S_AXI_ARLEN (aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]),\n           .S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RID (mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),\n           .S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),\n           .S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]),\n           .S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]),\n           .S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]),\n           .S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS])\n         );\n    end else begin : gen_no_decerr_slave\n      assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;\n      assign mi_wready[C_NUM_MASTER_SLOTS] = 1'b0;\n      assign mi_arready[C_NUM_MASTER_SLOTS] = 1'b0;\n      assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;\n      assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;\n      assign mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                    = 0;\n      assign mi_bresp[C_NUM_MASTER_SLOTS*2+:2]                                            = 0;\n      assign mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]            = 0;\n      assign mi_bvalid[C_NUM_MASTER_SLOTS]                                                = 1'b0;\n      assign mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                    = 0;\n      assign mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0; \n      assign mi_rresp[C_NUM_MASTER_SLOTS*2+:2]                                            = 0; \n      assign mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]            = 0; \n      assign mi_rlast[C_NUM_MASTER_SLOTS]                                                  = 1'b0;\n      assign mi_rvalid[C_NUM_MASTER_SLOTS]                                                 = 1'b0;\n    end  // gen_decerr_slave\n  endgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: decerr_slave.v\n//\n// Description: \n//   Phantom slave interface used to complete W, R and B channel transfers when an\n//   erroneous transaction is trapped in the crossbar.\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    decerr_slave\n//    \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_decerr_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH           = 1,\n   parameter integer C_AXI_DATA_WIDTH         = 32,\n   parameter integer C_AXI_BUSER_WIDTH        = 1,\n   parameter integer C_AXI_RUSER_WIDTH        = 1,\n   parameter integer C_AXI_PROTOCOL           = 0,\n   parameter integer C_RESP                   = 2'b11   \n   )\n  (\n   input wire S_AXI_ACLK,\n   input wire S_AXI_ARESET,\n   input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,\n   input wire S_AXI_AWVALID,\n   output wire S_AXI_AWREADY,\n   input wire S_AXI_WLAST,\n   input wire S_AXI_WVALID,\n   output wire S_AXI_WREADY,\n   output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,\n   output wire [1:0] S_AXI_BRESP,\n   output wire [C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,\n   output wire S_AXI_BVALID,\n   input wire S_AXI_BREADY,\n   input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,\n   input wire [7:0] S_AXI_ARLEN,\n   input wire S_AXI_ARVALID,\n   output wire S_AXI_ARREADY,\n   output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,\n   output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,\n   output wire [1:0] S_AXI_RRESP,\n   output wire [C_AXI_RUSER_WIDTH-1:0]          S_AXI_RUSER,\n   output wire S_AXI_RLAST,\n   output wire S_AXI_RVALID,\n   input wire S_AXI_RREADY\n   );\n   \n  reg s_axi_awready_i = 1'b0;\n  reg s_axi_wready_i = 1'b0;\n  reg s_axi_bvalid_i = 1'b0;\n  reg s_axi_arready_i = 1'b0;\n  reg s_axi_rvalid_i = 1'b0;\n  \n  localparam P_WRITE_IDLE = 2'b00;\n  localparam P_WRITE_DATA = 2'b01;\n  localparam P_WRITE_RESP = 2'b10;\n  localparam P_READ_IDLE = 1'b0;\n  localparam P_READ_DATA = 1'b1;\n  localparam integer  P_AXI4 = 0;\n  localparam integer  P_AXI3 = 1;\n  localparam integer  P_AXILITE = 2;\n   \n  assign S_AXI_BRESP = C_RESP;\n  assign S_AXI_RRESP = C_RESP;\n  //assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};\n  assign S_AXI_RDATA = {C_AXI_DATA_WIDTH/32{32'hDEC0_DE1C}};\n  assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};\n  assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};\n  assign S_AXI_AWREADY = s_axi_awready_i;\n  assign S_AXI_WREADY = s_axi_wready_i;\n  assign S_AXI_BVALID = s_axi_bvalid_i;\n  assign S_AXI_ARREADY = s_axi_arready_i;\n  assign S_AXI_RVALID = s_axi_rvalid_i;\n  \n  generate\n  if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite\n    \n    assign S_AXI_RLAST = 1'b1;\n    assign S_AXI_BID = 0;\n    assign S_AXI_RID = 0;\n    \n    always @(posedge S_AXI_ACLK) begin\n      if (S_AXI_ARESET) begin\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        if (s_axi_bvalid_i) begin\n          if (S_AXI_BREADY) begin\n            s_axi_bvalid_i <= 1'b0;\n          end\n        end else if (S_AXI_AWVALID & S_AXI_WVALID) begin\n          if (s_axi_awready_i) begin\n            s_axi_awready_i <= 1'b0;\n            s_axi_wready_i <= 1'b0;\n            s_axi_bvalid_i <= 1'b1;\n          end else begin\n            s_axi_awready_i <= 1'b1;\n            s_axi_wready_i <= 1'b1;\n          end\n        end\n      end\n    end\n           \n    always @(posedge S_AXI_ACLK) begin\n      if (S_AXI_ARESET) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n      end else begin\n        if (s_axi_rvalid_i) begin\n          if (S_AXI_RREADY) begin\n            s_axi_rvalid_i <= 1'b0;\n          end\n        end else if (S_AXI_ARVALID & s_axi_arready_i) begin\n          s_axi_arready_i <= 1'b0;\n          s_axi_rvalid_i <= 1'b1;\n        end else begin\n          s_axi_arready_i <= 1'b1;\n        end\n      end\n    end\n        \n  end else begin : gen_axi\n  \n    reg s_axi_rlast_i;\n    reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;\n    reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;\n    reg [7:0] read_cnt;\n    reg [1:0] write_cs;\n    reg [0:0] read_cs;\n  \n    assign S_AXI_RLAST = s_axi_rlast_i;\n    assign S_AXI_BID = s_axi_bid_i;\n    assign S_AXI_RID = s_axi_rid_i;\n  \n    always @(posedge S_AXI_ACLK) begin\n      if (S_AXI_ARESET) begin\n        write_cs <= P_WRITE_IDLE;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n        s_axi_bid_i <= 0;\n      end else begin\n        case (write_cs) \n          P_WRITE_IDLE: \n            begin\n              if (S_AXI_AWVALID & s_axi_awready_i) begin\n                s_axi_awready_i <= 1'b0;\n                s_axi_bid_i <= S_AXI_AWID;\n                s_axi_wready_i <= 1'b1;\n                write_cs <= P_WRITE_DATA;\n              end else begin\n                s_axi_awready_i <= 1'b1;\n              end\n            end\n          P_WRITE_DATA:\n            begin\n              if (S_AXI_WVALID & S_AXI_WLAST) begin\n                s_axi_wready_i <= 1'b0;\n                s_axi_bvalid_i <= 1'b1;\n                write_cs <= P_WRITE_RESP;\n              end\n            end\n          P_WRITE_RESP:\n            begin\n              if (S_AXI_BREADY) begin\n                s_axi_bvalid_i <= 1'b0;\n                s_axi_awready_i <= 1'b1;\n                write_cs <= P_WRITE_IDLE;\n              end\n            end\n        endcase\n      end\n    end\n  \n    always @(posedge S_AXI_ACLK) begin\n      if (S_AXI_ARESET) begin\n        read_cs <= P_READ_IDLE;\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        s_axi_rlast_i <= 1'b0;\n        s_axi_rid_i <= 0;\n        read_cnt <= 0;\n      end else begin\n        case (read_cs) \n          P_READ_IDLE: \n            begin\n              if (S_AXI_ARVALID & s_axi_arready_i) begin\n                s_axi_arready_i <= 1'b0;\n                s_axi_rid_i <= S_AXI_ARID;\n                read_cnt <= S_AXI_ARLEN;\n                s_axi_rvalid_i <= 1'b1;\n                if (S_AXI_ARLEN == 0) begin\n                  s_axi_rlast_i <= 1'b1;\n                end else begin\n                  s_axi_rlast_i <= 1'b0;\n                end\n                read_cs <= P_READ_DATA;\n              end else begin\n                s_axi_arready_i <= 1'b1;\n              end\n            end\n          P_READ_DATA:\n            begin\n              if (S_AXI_RREADY) begin\n                if (read_cnt == 0) begin\n                  s_axi_rvalid_i <= 1'b0;\n                  s_axi_rlast_i <= 1'b0;\n                  s_axi_arready_i <= 1'b1;\n                  read_cs <= P_READ_IDLE;\n                end else begin\n                  if (read_cnt == 1) begin\n                    s_axi_rlast_i <= 1'b1;\n                  end\n                  read_cnt <= read_cnt - 1;\n                end\n              end\n            end\n        endcase\n      end\n    end\n  \n  end  \n  endgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: si_transactor.v\n//\n// Description: \n//   This module manages multi-threaded transactions for one SI-slot.\n//   The module interface consists of a 1-slave to 1-master address channel, plus a\n//     (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel.\n//   The module maintains transaction thread control registers that count the\n//     number of outstanding transations for each thread and the target MI-slot.\n//   On the address channel, the module decodes addresses to select among MI-slots \n//     accessible to the SI-slot where it is instantiated.\n//     It then qualifies whether each received transaction\n//     should be propagated as a request to the address channel arbiter.\n//     Transactions are blocked while there is any outstanding transaction to a \n//     different slave (MI-slot) for the requested ID thread (for deadlock avoidance).\n//   On the response channel, the module mulitplexes transfers from each of the \n//     MI-slots whenever a transfer targets the ID of an active thread,\n//     arbitrating between MI-slots if multiple threads respond concurrently.\n//\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    si_transactor\n//      addr_decoder\n//        comparator_static\n//      mux_enc\n//      axic_srl_fifo\n//      arbiter_resp\n//      \n//-----------------------------------------------------------------------------\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_si_transactor #\n  (\n   parameter         C_FAMILY                       = \"none\", \n   parameter integer C_SI             =   0, // SI-slot number of current instance.\n   parameter integer C_DIR             =   0, // Direction: 0 = Write; 1 = Read.\n   parameter integer C_NUM_ADDR_RANGES = 1,\n   parameter integer C_NUM_M             =   2, \n   parameter integer C_NUM_M_LOG             =   1, \n   parameter integer C_ACCEPTANCE             =   1,  // Acceptance limit of this SI-slot.\n   parameter integer C_ACCEPTANCE_LOG             =   0,  // Width of acceptance counter for this SI-slot.\n   parameter integer C_ID_WIDTH                   = 1, \n   parameter integer C_THREAD_ID_WIDTH                  = 0,\n   parameter integer C_ADDR_WIDTH                 = 32, \n   parameter integer C_AMESG_WIDTH = 1,  // Used for AW or AR channel payload, depending on instantiation.\n   parameter integer C_RMESG_WIDTH = 1,  // Used for B or R channel payload, depending on instantiation.\n   parameter [C_ID_WIDTH-1:0]  C_BASE_ID                  = {C_ID_WIDTH{1'b0}},\n   parameter [C_ID_WIDTH-1:0]  C_HIGH_ID                  = {C_ID_WIDTH{1'b0}},\n   parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b1}}, \n   parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b0}}, \n   parameter integer C_SINGLE_THREAD             =   0,\n   parameter [C_NUM_M-1:0]    C_TARGET_QUAL                 = {C_NUM_M{1'b1}},\n   parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE                   = {C_NUM_M{32'h00000000}},\n   parameter integer C_RANGE_CHECK                    = 0,\n   parameter integer C_ADDR_DECODE           =0,\n   parameter [C_NUM_M*32-1:0] C_ERR_MODE            = {C_NUM_M{32'h00000000}},\n   parameter integer C_DEBUG                = 1\n   )\n  (\n   // Global Signals\n   input  wire                                                    ACLK,\n   input  wire                                                    ARESET,\n   // Slave Address Channel Interface Ports\n   input  wire [C_ID_WIDTH-1:0]           S_AID,\n   input  wire [C_ADDR_WIDTH-1:0]          S_AADDR,\n   input  wire [8-1:0]                    S_ALEN,\n   input  wire [3-1:0]                    S_ASIZE,\n   input  wire [2-1:0]                    S_ABURST,\n   input  wire [2-1:0]                    S_ALOCK,\n   input  wire [3-1:0]                    S_APROT,\n//   input  wire [4-1:0]                    S_AREGION,\n   input  wire [C_AMESG_WIDTH-1:0]         S_AMESG,\n   input  wire                             S_AVALID,\n   output wire                             S_AREADY,\n   // Master Address Channel Interface Ports\n   output wire [C_ID_WIDTH-1:0]          M_AID,\n   output wire [C_ADDR_WIDTH-1:0]          M_AADDR,\n   output  wire [8-1:0]                    M_ALEN,\n   output  wire [3-1:0]                    M_ASIZE,\n   output  wire [2-1:0]                    M_ALOCK,\n   output  wire [3-1:0]                    M_APROT,\n   output wire [4-1:0]                         M_AREGION,\n   output wire [C_AMESG_WIDTH-1:0]                         M_AMESG,\n   output wire [(C_NUM_M+1)-1:0]                         M_ATARGET_HOT,\n   output wire [(C_NUM_M_LOG+1)-1:0]                         M_ATARGET_ENC,\n   output wire [7:0]                         M_AERROR,\n   output wire                            M_AVALID_QUAL,\n   output wire                            M_AVALID,\n   input  wire                            M_AREADY,\n   // Slave Response Channel Interface Ports\n   output  wire [C_ID_WIDTH-1:0]           S_RID,\n   output  wire [C_RMESG_WIDTH-1:0]         S_RMESG,\n   output  wire                             S_RLAST,\n   output  wire                             S_RVALID,\n   input wire                             S_RREADY,\n   // Master Response Channel Interface Ports\n   input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0]          M_RID,\n   input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0]             M_RMESG,\n   input wire [(C_NUM_M+1)-1:0]                           M_RLAST,\n   input wire [(C_NUM_M+1)-1:0]                           M_RVALID,\n   output  wire [(C_NUM_M+1)-1:0]                           M_RREADY,\n   input wire [(C_NUM_M+1)-1:0]           M_RTARGET,  // Does response ID from each MI-slot target this SI slot?\n   input wire [8-1:0]                        DEBUG_A_TRANS_SEQ\n   );\n\n  localparam integer P_WRITE = 0;\n  localparam integer P_READ = 1;\n  localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1;\n  localparam [31:0]   P_AXILITE_ERRMODE = 32'h00000001;\n  localparam integer P_NONSECURE_BIT = 1; \n  localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1;\n  localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0);  // Mask of AxiLite MI-slots\n  localparam [1:0]   P_FIXED = 2'b00;\n  localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1);\n  localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1; \n  localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH;\n  localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE;\n  localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE);  // Mask of secure MI-slots\n  \n  // Ceiling of log2(x)\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  // AxiLite protocol flag vector      \n  function [C_NUM_M-1:0] f_m_axilite\n    (\n      input integer null_arg\n    );\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_M; mi=mi+1) begin\n        f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);\n      end\n    end\n  endfunction\n\n  // Convert Bit32 vector of range [0,1] to Bit1 vector on MI\n  function [C_NUM_M-1:0] f_bit32to1_mi\n    (input [C_NUM_M*32-1:0] vec32);\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_M; mi=mi+1) begin\n        f_bit32to1_mi[mi] = vec32[mi*32];\n      end\n    end\n  endfunction\n  \n  wire [C_NUM_M-1:0] target_mi_hot;\n  wire [P_NUM_M_LOG_M1-1:0] target_mi_enc;\n  wire [(C_NUM_M+1)-1:0] m_atarget_hot_i;\n  wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i;\n  wire match;\n  wire [3:0] target_region;\n  wire [3:0] m_aregion_i;\n  wire m_avalid_i;\n  wire s_aready_i;\n  wire any_error;\n  wire s_rvalid_i;\n  wire [C_ID_WIDTH-1:0] s_rid_i;\n  wire s_rlast_i;\n  wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg;\n  wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg;\n  wire [(C_NUM_M+1)-1:0] m_rvalid_qual;\n  wire [(C_NUM_M+1)-1:0] m_rready_arb;\n  wire [(C_NUM_M+1)-1:0] m_rready_i;\n  wire target_secure;\n  wire target_axilite;\n  wire m_avalid_qual_i;\n  wire [7:0] m_aerror_i;\n  \n  genvar gen_mi;\n  genvar gen_thread;\n    \n  generate\n    if (C_ADDR_DECODE) begin : gen_addr_decoder\n      axi_crossbar_v2_1_23_addr_decoder #\n        (\n          .C_FAMILY          (C_FAMILY),\n          .C_NUM_TARGETS     (C_NUM_M),\n          .C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1),\n          .C_NUM_RANGES      (C_NUM_ADDR_RANGES),\n          .C_ADDR_WIDTH      (C_ADDR_WIDTH),\n          .C_TARGET_ENC      (1),\n          .C_TARGET_HOT      (1),\n          .C_REGION_ENC      (1),\n          .C_BASE_ADDR      (C_BASE_ADDR),\n          .C_HIGH_ADDR      (C_HIGH_ADDR),\n          .C_TARGET_QUAL     (C_TARGET_QUAL),\n          .C_RESOLUTION      (2)\n        ) \n        addr_decoder_inst \n        (\n          .ADDR             (S_AADDR),        \n          .TARGET_HOT       (target_mi_hot),  \n          .TARGET_ENC       (target_mi_enc),  \n          .MATCH            (match),       \n          .REGION           (target_region)      \n        );\n    end else begin : gen_no_addr_decoder\n      assign target_mi_hot = 1;\n      assign target_mi_enc = 0;\n      assign match = 1'b1;\n      assign target_region = 4'b0000;\n    end\n  endgenerate\n  \n  assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);\n  assign target_axilite = |(target_mi_hot & P_M_AXILITE);\n\n  assign any_error = C_RANGE_CHECK && (m_aerror_i != 0);            // DECERR if error-detection enabled and any error condition.\n  assign m_aerror_i[0] = ~match;                                    // Invalid target address\n  assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation\n  assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) || \n    (S_ASIZE[1:0] == 2'b11) || (S_ASIZE[2] == 1'b1));               // AxiLite access violation\n  assign m_aerror_i[7:3] = 5'b00000;                                    // Reserved\n  assign M_ATARGET_HOT = m_atarget_hot_i;\n  assign m_atarget_hot_i = (any_error ? {1'b1, {C_NUM_M{1'b0}}} : {1'b0, target_mi_hot});\n  assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc);\n    \n  assign M_AVALID = m_avalid_i;\n  assign m_avalid_i = S_AVALID;\n  assign M_AVALID_QUAL = m_avalid_qual_i; \n  assign S_AREADY = s_aready_i;\n  assign s_aready_i = M_AREADY;\n  assign M_AERROR = m_aerror_i;\n  assign M_ATARGET_ENC = m_atarget_enc_i;\n  assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4'b0000;\n//  assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION;\n  assign M_AREGION = m_aregion_i;\n  assign M_AID = S_AID;\n  assign M_AADDR = S_AADDR;\n  assign M_ALEN = S_ALEN;\n  assign M_ASIZE = S_ASIZE;\n  assign M_ALOCK = S_ALOCK;\n  assign M_APROT = S_APROT;\n  assign M_AMESG = S_AMESG;\n  \n  assign S_RVALID = s_rvalid_i;\n  assign M_RREADY = m_rready_i;\n  assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH];\n  assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH];\n  assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1];\n  assign S_RID = s_rid_i;\n  assign S_RLAST = s_rlast_i;\n  assign m_rvalid_qual = M_RVALID & M_RTARGET;\n  assign m_rready_i = m_rready_arb & M_RTARGET;\n\n  generate\n    for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi\n      // Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.\n      assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = {\n               M_RLAST[gen_mi],\n               M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH],\n               M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH]\n               };\n    end  // gen_rmesg_mi\n\n    if (C_ACCEPTANCE == 1) begin : gen_single_issue\n      wire  cmd_push;\n      wire  cmd_pop;\n      reg  [(C_NUM_M+1)-1:0] active_target_hot = 0;\n      reg  [P_NUM_M_DE_LOG-1:0] active_target_enc = 0;\n      reg  accept_cnt = 1'b0;\n      reg  [8-1:0] debug_r_beat_cnt_i;\n      wire [8-1:0] debug_r_trans_seq_i;\n\n      assign cmd_push = M_AREADY;\n      assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i;  // Pop command queue if end of read burst\n      assign m_avalid_qual_i = ~accept_cnt | cmd_pop;  // Ready for arbitration if no outstanding transaction or transaction being completed\n\n      always @(posedge ACLK) begin \n        if (ARESET) begin\n          accept_cnt <= 1'b0;\n          active_target_enc <= 0;\n          active_target_hot <= 0;\n        end else begin\n          if (cmd_push) begin\n            active_target_enc <= m_atarget_enc_i;\n            active_target_hot <= m_atarget_hot_i;\n            accept_cnt <= 1'b1;\n          end else if (cmd_pop) begin\n            accept_cnt <= 1'b0;\n          end\n        end \n      end  // Clocked process\n        \n      assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};\n      assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);\n                 \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (C_FAMILY),\n         .C_RATIO       (C_NUM_M+1),\n         .C_SEL_WIDTH   (P_NUM_M_DE_LOG),\n         .C_DATA_WIDTH  (P_RMUX_MESG_WIDTH)\n        ) mux_resp_single_issue\n        (\n         .S   (active_target_enc),\n         .A   (mi_rmux_mesg),\n         .O   (si_rmux_mesg),\n         .OE  (1'b1)\n        ); \n        \n      if (C_DEBUG) begin : gen_debug_r_single_issue\n        // DEBUG READ BEAT COUNTER (only meaningful for R-channel)\n        always @(posedge ACLK) begin\n          if (ARESET) begin\n            debug_r_beat_cnt_i <= 0;\n          end else if (C_DIR == P_READ) begin\n            if (s_rvalid_i && S_RREADY) begin\n              if (s_rlast_i) begin\n                debug_r_beat_cnt_i <= 0;\n              end else begin\n                debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;\n              end\n            end\n          end else begin\n            debug_r_beat_cnt_i <= 0;            \n          end\n        end  // Clocked process\n        \n        // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO\n        axi_data_fifo_v2_1_21_axic_srl_fifo #\n          (\n           .C_FAMILY          (C_FAMILY),\n           .C_FIFO_WIDTH      (8),\n           .C_FIFO_DEPTH_LOG  (C_ACCEPTANCE_LOG+1),\n           .C_USE_FULL        (0)\n           )\n          debug_r_seq_fifo_single_issue\n            (\n             .ACLK    (ACLK),\n             .ARESET  (ARESET),\n             .S_MESG  (DEBUG_A_TRANS_SEQ),\n             .S_VALID (cmd_push),\n             .S_READY (),\n             .M_MESG  (debug_r_trans_seq_i),\n             .M_VALID (),\n             .M_READY (cmd_pop)\n            );\n            \n      end  // gen_debug_r\n      \n    end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread\n      wire  s_avalid_en;\n      wire  cmd_push;\n      wire  cmd_pop;\n      reg  [C_ID_WIDTH-1:0] active_id;\n      reg  [(C_NUM_M+1)-1:0] active_target_hot = 0;\n      reg  [P_NUM_M_DE_LOG-1:0] active_target_enc = 0;\n      reg  [4-1:0] active_region;\n      reg  [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt = 0;\n      reg  [8-1:0] debug_r_beat_cnt_i;\n      wire [8-1:0] debug_r_trans_seq_i;\n      wire accept_limit ;\n\n      // Implement single-region-per-ID cyclic dependency avoidance method.\n      assign s_avalid_en =  // This transaction is qualified to request arbitration if ...\n        (accept_cnt == 0) ||  // Either there are no outstanding transactions, or ...\n        (((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) &&  // the current transaction ID matches the previous, and ...\n        (active_target_enc == m_atarget_enc_i) &&  // all outstanding transactions are to the same target MI ...\n        (active_region == m_aregion_i));  // and to the same REGION.\n      \n      assign cmd_push = M_AREADY;\n      assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i;  // Pop command queue if end of read burst\n      assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop;  // Allow next push if a transaction is currently being completed\n      assign m_avalid_qual_i = s_avalid_en & ~accept_limit; \n      \n      always @(posedge ACLK) begin \n        if (ARESET) begin\n          accept_cnt <= 0;\n          active_id <= 0;\n          active_target_enc <= 0;\n          active_target_hot <= 0;\n          active_region <= 0;\n        end else begin\n          if (cmd_push) begin\n            active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];\n            active_target_enc <= m_atarget_enc_i;\n            active_target_hot <= m_atarget_hot_i;\n            active_region <= m_aregion_i;\n            if (~cmd_pop) begin\n              accept_cnt <= accept_cnt + 1;\n            end\n          end else begin\n            if (cmd_pop & (accept_cnt != 0)) begin\n              accept_cnt <= accept_cnt - 1;\n            end\n          end\n        end \n      end  // Clocked process\n        \n      assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};\n      assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);\n                 \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (C_FAMILY),\n         .C_RATIO       (C_NUM_M+1),\n         .C_SEL_WIDTH   (P_NUM_M_DE_LOG),\n         .C_DATA_WIDTH  (P_RMUX_MESG_WIDTH)\n        ) mux_resp_single_thread\n        (\n         .S   (active_target_enc),\n         .A   (mi_rmux_mesg),\n         .O   (si_rmux_mesg),\n         .OE  (1'b1)\n        ); \n        \n      if (C_DEBUG) begin : gen_debug_r_single_thread\n        // DEBUG READ BEAT COUNTER (only meaningful for R-channel)\n        always @(posedge ACLK) begin\n          if (ARESET) begin\n            debug_r_beat_cnt_i <= 0;\n          end else if (C_DIR == P_READ) begin\n            if (s_rvalid_i && S_RREADY) begin\n              if (s_rlast_i) begin\n                debug_r_beat_cnt_i <= 0;\n              end else begin\n                debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;\n              end\n            end\n          end else begin\n            debug_r_beat_cnt_i <= 0;            \n          end\n        end  // Clocked process\n        \n        // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO\n        axi_data_fifo_v2_1_21_axic_srl_fifo #\n          (\n           .C_FAMILY          (C_FAMILY),\n           .C_FIFO_WIDTH      (8),\n           .C_FIFO_DEPTH_LOG  (C_ACCEPTANCE_LOG+1),\n           .C_USE_FULL        (0)\n           )\n          debug_r_seq_fifo_single_thread\n            (\n             .ACLK    (ACLK),\n             .ARESET  (ARESET),\n             .S_MESG  (DEBUG_A_TRANS_SEQ),\n             .S_VALID (cmd_push),\n             .S_READY (),\n             .M_MESG  (debug_r_trans_seq_i),\n             .M_VALID (),\n             .M_READY (cmd_pop)\n            );\n            \n      end  // gen_debug_r\n      \n    end else begin : gen_multi_thread\n      wire [(P_NUM_M_DE_LOG)-1:0] resp_select;\n      reg  [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt = 0;\n      wire [P_NUM_THREADS-1:0] s_avalid_en;\n      wire [P_NUM_THREADS-1:0] thread_valid;\n      wire [P_NUM_THREADS-1:0] aid_match;\n      wire [P_NUM_THREADS-1:0] rid_match;\n      wire [P_NUM_THREADS-1:0] cmd_push;\n      wire [P_NUM_THREADS-1:0] cmd_pop;\n      wire [P_NUM_THREADS:0]   accum_push;\n      reg  [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id;\n      reg  [P_NUM_THREADS*8-1:0] active_target;\n      reg  [P_NUM_THREADS*8-1:0] active_region;\n      reg  [P_NUM_THREADS*8-1:0] active_cnt = 0;\n      reg  [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i;\n      wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i;\n      wire any_aid_match;\n      wire any_rid_match;\n      wire accept_limit;\n      wire any_push;\n      wire any_pop;\n        \n      axi_crossbar_v2_1_23_arbiter_resp #  // Multi-thread response arbiter\n        (\n         .C_FAMILY                (C_FAMILY),\n         .C_NUM_S                 (C_NUM_M+1),\n         .C_NUM_S_LOG             (P_NUM_M_DE_LOG),\n         .C_GRANT_ENC            (1),\n         .C_GRANT_HOT            (0)\n         )\n        arbiter_resp_inst\n          (\n           .ACLK                  (ACLK),\n           .ARESET                (ARESET),\n           .S_VALID               (m_rvalid_qual),\n           .S_READY               (m_rready_arb),\n           .M_GRANT_HOT           (),\n           .M_GRANT_ENC           (resp_select),\n           .M_VALID               (s_rvalid_i),\n           .M_READY               (S_RREADY)\n           );\n                 \n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (C_FAMILY),\n         .C_RATIO       (C_NUM_M+1),\n         .C_SEL_WIDTH   (P_NUM_M_DE_LOG),\n         .C_DATA_WIDTH  (P_RMUX_MESG_WIDTH)\n        ) mux_resp_multi_thread\n        (\n         .S   (resp_select),\n         .A   (mi_rmux_mesg),\n         .O   (si_rmux_mesg),\n         .OE  (1'b1)\n        ); \n        \n      assign any_push = M_AREADY;\n      assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i;\n      assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop;  // Allow next push if a transaction is currently being completed\n        assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit;  // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads.\n        assign any_aid_match = |aid_match;\n        assign any_rid_match = |rid_match;\n        assign accum_push[0] = 1'b0;\n        \n        always @(posedge ACLK) begin\n          if (ARESET) begin\n            accept_cnt <= 0; \n          end else begin\n            if (any_push & ~any_pop) begin\n              accept_cnt <= accept_cnt + 1;\n          end else if (any_pop & ~any_push & (accept_cnt != 0)) begin\n              accept_cnt <= accept_cnt - 1;\n            end\n          end \n        end  // Clocked process\n          \n        for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop\n          assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0);\n          assign aid_match[gen_thread] =  // The currect thread is active for the requested transaction if\n            thread_valid[gen_thread] &&  // this thread slot is not vacant, and\n          ((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]);  // the requested ID matches the active ID for this thread.\n          assign s_avalid_en[gen_thread] =  // The current request is qualified against this thread slot if\n            (~aid_match[gen_thread]) ||  // This thread slot is not active for the requested ID, or\n            ((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) &&  // this outstanding transaction was to the same target and\n            (m_aregion_i == active_region[gen_thread*8+:4]));  // to the same region.\n          \n          // cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot.\n          assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread];\n          assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread]));\n          \n          // cmd_pop points to the position of the active thread that matches the current RID.\n        assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]);\n          assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread];\n        \n          always @(posedge ACLK) begin\n            if (ARESET) begin\n              active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0;\n              active_target[gen_thread*8+:8] <= 0;\n              active_region[gen_thread*8+:8] <= 0;\n              active_cnt[gen_thread*8+:8] <= 0; \n            end else begin\n              if (cmd_push[gen_thread]) begin\n              active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];\n                active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i;\n                active_region[gen_thread*8+:4] <= m_aregion_i;\n                if (~cmd_pop[gen_thread]) begin\n                  active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1;\n                end\n              end else if (cmd_pop[gen_thread]) begin\n                  active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1;\n              end\n            end \n          end  // Clocked process\n            \n        if (C_DEBUG) begin : gen_debug_r_multi_thread\n            // DEBUG READ BEAT COUNTER (only meaningful for R-channel)\n            always @(posedge ACLK) begin\n              if (ARESET) begin\n                debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;\n              end else if (C_DIR == P_READ) begin\n                if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin\n                  if (s_rlast_i) begin\n                    debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;\n                  end else begin\n                    debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1;\n                  end\n                end\n              end else begin\n                debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;            \n              end\n            end  // Clocked process\n            \n            // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO\n            axi_data_fifo_v2_1_21_axic_srl_fifo #\n              (\n               .C_FAMILY          (C_FAMILY),\n               .C_FIFO_WIDTH      (8),\n               .C_FIFO_DEPTH_LOG  (C_ACCEPTANCE_LOG+1),\n               .C_USE_FULL        (0)\n               )\n            debug_r_seq_fifo_multi_thread\n                (\n                 .ACLK    (ACLK),\n                 .ARESET  (ARESET),\n                 .S_MESG  (DEBUG_A_TRANS_SEQ),\n                 .S_VALID (cmd_push[gen_thread]),\n                 .S_READY (),\n                 .M_MESG  (debug_r_trans_seq_i[gen_thread*8+:8]),\n                 .M_VALID (),\n                 .M_READY (cmd_pop[gen_thread])\n                );\n        end  // gen_debug_r_multi_thread\n      end  // Next gen_thread_loop\n            \n    end  // thread control\n        \n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: AXI Splitter\n// Each transfer received on the AXI handshake slave port is replicated onto \n//   each of the master ports, and is completed back to the slave (S_READY) \n//   once all master ports have completed.\n//   \n// M_VALID is asserted combinatorially from S_VALID assertion.\n// Each M_VALID is masked off beginning the cycle after each M_READY is\n//   received (if S_READY remains low) until the cycle after both S_VALID\n//   and S_READY are asserted.\n// S_READY is asserted combinatorially when the last (or all) of the M_READY\n//   inputs have been received.\n// If all M_READYs are asserted when S_VALID is asserted, back-to-back\n//   handshakes can occur without bubble cycles.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   splitter\n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_splitter #\n  (\n   parameter integer C_NUM_M = 2  // Number of master ports = [2:16]\n   )\n  (\n   // Global Signals\n   input  wire                             ACLK,\n   input  wire                             ARESET,\n   // Slave  Port\n   input  wire                             S_VALID,\n   output wire                             S_READY,\n   // Master Ports\n   output wire [C_NUM_M-1:0]               M_VALID,\n   input  wire [C_NUM_M-1:0]               M_READY\n   );\n\n   reg  [C_NUM_M-1:0] m_ready_d = 0;\n   wire               s_ready_i;\n   wire [C_NUM_M-1:0] m_valid_i;\n\n   always @(posedge ACLK) begin\n      if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1'b0}};\n      else                    m_ready_d <= m_ready_d | (m_valid_i & M_READY);\n   end\n\n   assign s_ready_i = &(m_ready_d | M_READY);\n   assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d;\n   assign M_VALID = m_valid_i;\n   assign S_READY = s_ready_i;\n\nendmodule\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: wdata_mux.v\n//\n// Description: \n//   Contains MI-side write command queue.\n//   SI-slot index selected by AW arbiter is pushed onto queue when S_AVALID transfer is received.\n//   Queue is popped when WLAST data beat is transferred.\n//   W-channel input from SI-slot selected by queue output is transferred to MI-side output .\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    wdata_mux\n//      axic_reg_srl_fifo\n//      mux_enc\n//      \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_wdata_mux #\n  (\n   parameter         C_FAMILY       = \"none\", // FPGA Family.\n   parameter integer C_WMESG_WIDTH            =  1, // Width of W-channel payload.\n   parameter integer C_NUM_SLAVE_SLOTS     =  1, // Number of S_* ports.\n   parameter integer C_SELECT_WIDTH      =  1, // Width of ASELECT.\n   parameter integer C_FIFO_DEPTH_LOG     =  0 // Queue depth = 2**C_FIFO_DEPTH_LOG.\n   )\n  (\n   // System Signals\n   input  wire                                        ACLK,\n   input  wire                                        ARESET,\n   // Slave Data Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_WMESG_WIDTH-1:0]     S_WMESG,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                S_WLAST,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                S_WVALID,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                S_WREADY,\n   // Master Data Ports\n   output wire [C_WMESG_WIDTH-1:0]                       M_WMESG,\n   output wire                                        M_WLAST,\n   output wire                                        M_WVALID,\n   input  wire                                        M_WREADY,\n   // Write Command Ports\n   input  wire [C_SELECT_WIDTH-1:0]                 S_ASELECT,  // SI-slot index from AW arbiter\n   input  wire                                        S_AVALID,\n   output wire                                        S_AREADY\n   );\n\n  localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5;  // Max depth = 32\n  \n  // Decode select input to 1-hot\n  function [C_NUM_SLAVE_SLOTS-1:0] f_decoder (\n      input [C_SELECT_WIDTH-1:0] sel\n    );\n    integer i;\n    begin\n      for (i=0; i<C_NUM_SLAVE_SLOTS; i=i+1) begin\n        f_decoder[i] = (sel == i);\n      end\n    end\n  endfunction\n\n  wire                                          m_valid_i;\n  wire                                          m_last_i;\n  wire [C_NUM_SLAVE_SLOTS-1:0]             m_select_hot;\n  wire [C_SELECT_WIDTH-1:0]                 m_select_enc;\n  wire                                          m_avalid;\n  wire                                          m_aready;\n  \n  generate\n    if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux\n      // SI-side write command queue\n      axi_data_fifo_v2_1_21_axic_reg_srl_fifo #\n        (\n         .C_FAMILY          (C_FAMILY),\n         .C_FIFO_WIDTH      (C_SELECT_WIDTH),\n         .C_FIFO_DEPTH_LOG  (P_FIFO_DEPTH_LOG),\n         .C_USE_FULL        (0)\n         )\n        wmux_aw_fifo\n          (\n           .ACLK    (ACLK),\n           .ARESET  (ARESET),\n           .S_MESG  (S_ASELECT),\n           .S_VALID (S_AVALID),\n           .S_READY (S_AREADY),\n           .M_MESG  (m_select_enc),\n           .M_VALID (m_avalid),\n           .M_READY (m_aready)\n           );\n    \n      assign m_select_hot = f_decoder(m_select_enc);\n      \n      // Instantiate MUX\n      generic_baseblocks_v2_1_0_mux_enc # \n        (\n         .C_FAMILY      (\"rtl\"),\n         .C_RATIO       (C_NUM_SLAVE_SLOTS),\n         .C_SEL_WIDTH   (C_SELECT_WIDTH),\n         .C_DATA_WIDTH  (C_WMESG_WIDTH)\n        ) mux_w \n        (\n         .S   (m_select_enc),\n         .A   (S_WMESG),\n         .O   (M_WMESG),\n         .OE  (1'b1)\n        ); \n        \n      assign m_last_i  = |(S_WLAST & m_select_hot);\n      assign m_valid_i = |(S_WVALID & m_select_hot);\n      \n      assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY;\n      assign M_WLAST = m_last_i;\n      assign M_WVALID = m_valid_i & m_avalid;\n      assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}};\n    end else begin : gen_no_wmux\n      assign S_AREADY = 1'b1;\n      assign M_WVALID = S_WVALID;\n      assign S_WREADY = M_WREADY;\n      assign M_WLAST = S_WLAST;\n      assign M_WMESG = S_WMESG;\n    end\n  endgenerate\n  \nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: wdata_router.v\n//\n// Description: \n//   Contains SI-side write command queue.\n//   Target MI-slot index is pushed onto queue when S_AVALID transfer is received.\n//   Queue is popped when WLAST data beat is transferred.\n//   W-channel input is transferred to MI-slot output selected by queue output.\n//--------------------------------------------------------------------------\n//\n// Structure:\n//    wdata_router\n//      axic_reg_srl_fifo\n//      \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_wdata_router #\n  (\n   parameter         C_FAMILY       = \"none\", // FPGA Family.\n   parameter integer C_WMESG_WIDTH          = 1, // Width of all data signals\n   parameter integer C_NUM_MASTER_SLOTS     = 1, // Number of M_* ports.\n   parameter integer C_SELECT_WIDTH     =  1, // Width of S_ASELECT.\n   parameter integer C_FIFO_DEPTH_LOG     =  0 // Queue depth = 2**C_FIFO_DEPTH_LOG.\n   )\n  (\n   // System Signals\n   input  wire                                        ACLK,\n   input  wire                                        ARESET,\n   // Slave Data Ports\n   input  wire [C_WMESG_WIDTH-1:0]                    S_WMESG,\n   input  wire                                        S_WLAST,\n   input  wire                                        S_WVALID,\n   output wire                                        S_WREADY,\n   // Master Data Ports\n   output wire [C_WMESG_WIDTH-1:0]                    M_WMESG,  // Broadcast to all MI-slots\n   output wire                                        M_WLAST,  // Broadcast to all MI-slots\n   output wire [C_NUM_MASTER_SLOTS-1:0]               M_WVALID,  // Per MI-slot\n   input  wire [C_NUM_MASTER_SLOTS-1:0]               M_WREADY,  // Per MI-slot\n   // Address Arbiter Ports\n   input  wire [C_SELECT_WIDTH-1:0]                   S_ASELECT,  // Target MI-slot index from SI-side AW command\n   input  wire                                        S_AVALID,\n   output wire                                        S_AREADY\n   );\n\n  localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5;  // Max depth = 32\n\n  // Decode select input to 1-hot\n  function [C_NUM_MASTER_SLOTS-1:0] f_decoder (\n      input [C_SELECT_WIDTH-1:0] sel\n    );\n    integer i;\n    begin\n      for (i=0; i<C_NUM_MASTER_SLOTS; i=i+1) begin\n        f_decoder[i] = (sel == i);\n      end\n    end\n  endfunction\n\n  //---------------------------------------------------------------------------\n  // Internal signal declarations\n  //---------------------------------------------------------------------------\n  wire [C_NUM_MASTER_SLOTS-1:0]             m_select_hot;\n  wire [C_SELECT_WIDTH-1:0]                 m_select_enc;\n  wire                                          m_avalid;\n  wire                                          m_aready;\n  \n  //---------------------------------------------------------------------------\n  // Router\n  //---------------------------------------------------------------------------\n\n  // SI-side write command queue\n  axi_data_fifo_v2_1_21_axic_reg_srl_fifo #\n    (\n     .C_FAMILY          (C_FAMILY),\n     .C_FIFO_WIDTH      (C_SELECT_WIDTH),\n     .C_FIFO_DEPTH_LOG  (P_FIFO_DEPTH_LOG),\n     .C_USE_FULL        (1)\n     )\n    wrouter_aw_fifo\n      (\n       .ACLK    (ACLK),\n       .ARESET  (ARESET),\n       .S_MESG  (S_ASELECT),\n       .S_VALID (S_AVALID),\n       .S_READY (S_AREADY),\n       .M_MESG  (m_select_enc),\n       .M_VALID (m_avalid),\n       .M_READY (m_aready)\n       );\n\n  assign m_select_hot = f_decoder(m_select_enc);\n  \n  // W-channel payload and LAST are broadcast to all MI-slot's W-mux\n  assign M_WMESG   = S_WMESG;\n  assign M_WLAST =   S_WLAST;\n  \n  // Assert m_aready when last beat acknowledged by slave\n  assign m_aready = m_avalid & S_WVALID & S_WLAST & (|(M_WREADY & m_select_hot));\n\n  // M_WVALID is generated per MI-slot (including error handler at slot C_NUM_MASTER_SLOTS).\n  // The slot selected by the head of the queue (m_select_enc) is enabled.\n  assign M_WVALID = {C_NUM_MASTER_SLOTS{S_WVALID & m_avalid}} & m_select_hot;\n\n  // S_WREADY is muxed from the MI slot selected by the head of the queue (m_select_enc).\n  assign S_WREADY = m_avalid & (|(M_WREADY & m_select_hot));\n  \nendmodule\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2011-2014 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// File name: axi_crossbar.v\n//-----------------------------------------------------------------------------\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_crossbar_v2_1_23_axi_crossbar # (\n   parameter         C_FAMILY                         = \"rtl\", \n                       // FPGA Base Family. Current version: virtex6 or spartan6.\n   parameter integer C_NUM_SLAVE_SLOTS                = 1, \n                       // Number of Slave Interface (SI) slots for connecting \n                       // to master IP. Range: 1-16.\n   parameter integer C_NUM_MASTER_SLOTS               = 2, \n                       // Number of Master Interface (MI) slots for connecting \n                       // to slave IP. Range: 1-16.                       \n   parameter integer C_AXI_ID_WIDTH                   = 1, \n                       // Width of ID signals propagated by the Interconnect.\n                       // Width of ID signals produced on all MI slots.\n                       // Range: 1-32.\n   parameter integer C_AXI_ADDR_WIDTH                 = 32, \n                       // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and \n                       // m_axi_araddr for all SI/MI slots.\n                       // Range: 1-64.\n   parameter integer C_AXI_DATA_WIDTH        = 32, \n                       // Data width of the internal interconnect write and read \n                       // data paths.\n                       // Range: 32, 64, 128, 256, 512, 1024.\n   parameter integer C_AXI_PROTOCOL                 = 0, \n                       // 0 = \"AXI4\",\n                       // 1 = \"AXI3\", \n                       // 2 = \"AXI4LITE\"\n                       //   Propagate WID only when C_AXI_PROTOCOL = 1.\n   parameter integer C_NUM_ADDR_RANGES = 1,\n                       // Number of BASE/HIGH_ADDR pairs per MI slot.\n                       // Range: 1-16.\n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = 128'h00000000001000000000000000000000,\n                       // Base address of each range of each MI slot. \n                       // For unused ranges, set C_M_AXI_BASE_ADDR[mm*aa*64 +: C_AXI_ADDR_WIDTH] = {C_AXI_ADDR_WIDTH{1'b1}}. \n                       //   (Bit positions above C_AXI_ADDR_WIDTH are ignored.)\n                       // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit64}}.\n   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*32-1:0] C_M_AXI_ADDR_WIDTH = 64'H0000000c0000000c, \n                       // Number of low-order address bits that are used to select locations within each address range of each MI slot.\n                       // The High address of each range is derived as BASE_ADDR + 2**C_M_AXI_ADDR_WIDTH -1.\n                       // For used address ranges, C_M_AXI_ADDR_WIDTH must be > 0.\n                       // For unused ranges, set C_M_AXI_ADDR_WIDTH to 32'h00000000.\n                       // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit32}}.\n                       // Range: 0 - C_AXI_ADDR_WIDTH.\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_BASE_ID = 32'h00000000,\n                       // Base ID of each SI slot. \n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 0 to 2**C_AXI_ID_WIDTH-1.\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = 32'h00000000,\n                       // Number of low-order ID bits a connected master may vary to select a transaction thread.\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 0 - C_AXI_ID_WIDTH.\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS      = 0,\n                       // 1 = Propagate all USER signals, 0 = Dont propagate.\n   parameter integer C_AXI_AWUSER_WIDTH               = 1,\n                       // Width of AWUSER signals for all SI slots and MI slots. \n                       // Range: 1-1024.\n   parameter integer C_AXI_ARUSER_WIDTH               = 1,\n                       // Width of ARUSER signals for all SI slots and MI slots. \n                       // Range: 1-1024.\n   parameter integer C_AXI_WUSER_WIDTH                = 1,\n                       // Width of WUSER signals for all SI slots and MI slots. \n                       // Range: 1-1024.\n   parameter integer C_AXI_RUSER_WIDTH                = 1,\n                       // Width of RUSER signals for all SI slots and MI slots. \n                       // Range: 1-1024.\n   parameter integer C_AXI_BUSER_WIDTH                = 1,\n                       // Width of BUSER signals for all SI slots and MI slots. \n                       // Range: 1-1024.\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,\n                       // Multi-pathway write connectivity from each SI slot (N) to each \n                       // MI slot (M):\n                       // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)\n                       // Format: C_NUM_MASTER_SLOTS{Bit32}; \n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,\n                       // Multi-pathway read connectivity from each SI slot (N) to each \n                       // MI slot (M):\n                       // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)\n                       // Format: C_NUM_MASTER_SLOTS{Bit32}; \n   parameter integer C_R_REGISTER               = 0,\n                       // Insert register slice on R channel in the crossbar. (Valid only for SASD)\n                       // Range: Reg-slice type (0-8).\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD                 = 32'h00000000, \n                       // 0 = Implement separate command queues per ID thread.\n                       // 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD)\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32}; \n                       // Range: 0, 1\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE         = 32'H00000002,\n                       // Maximum number of active write transactions that each SI \n                       // slot can accept. (Valid only for SAMD)\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32}; \n                       // Range: 1-32.\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE          = 32'H00000002,\n                       // Maximum number of active read transactions that each SI \n                       // slot can accept. (Valid only for SAMD)\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 1-32.\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING            = 64'H0000000400000004,\n                       // Maximum number of data-active write transactions that \n                       // each MI slot can generate at any one time. (Valid only for SAMD)\n                       // Format: C_NUM_MASTER_SLOTS{Bit32};\n                       // Range: 1-32.\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING            = 64'H0000000400000004,\n                       // Maximum number of active read transactions that \n                       // each MI slot can generate at any one time. (Valid only for SAMD)\n                       // Format: C_NUM_MASTER_SLOTS{Bit32};\n                       // Range: 1-32.\n   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY             = 32'h00000000,\n                       // Arbitration priority among each SI slot. \n                       // Higher values indicate higher priority.\n                       // Format: C_NUM_SLAVE_SLOTS{Bit32};\n                       // Range: 0-15.\n   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE                   = 32'h00000000,\n                       // Indicates whether each MI slot connects to a secure slave \n                       // (allows only TrustZone secure access).\n                       // Format: C_NUM_MASTER_SLOTS{Bit32}.\n                       // Range: 0, 1\n   parameter integer C_CONNECTIVITY_MODE = 1\n                       // 0 = Shared-Address Shared-Data (SASD).\n                       // 1 = Shared-Address Multi-Data (SAMD).\n                       // Default 1 (on) for simulation; default 0 (off) for implementation.\n)\n(\n   // Global Signals\n   input  wire                                                    aclk,\n   input  wire                                                    aresetn,\n   // Slave Interface Write Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_awid,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           s_axi_awaddr,\n   input  wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          s_axi_awsize,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          s_axi_awburst,\n   input  wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_awcache,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          s_axi_awprot,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_awregion,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_awqos,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0]         s_axi_awuser,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_awvalid,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_awready,\n   // Slave Interface Write Data Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_wid,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]           s_axi_wdata,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0]         s_axi_wstrb,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_wlast,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0]          s_axi_wuser,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_wvalid,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_wready,\n   // Slave Interface Write Response Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_bid,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          s_axi_bresp,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0]          s_axi_buser,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_bvalid,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_bready,\n   // Slave Interface Read Address Ports\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_arid,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           s_axi_araddr,\n   input  wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          s_axi_arsize,\n   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          s_axi_arburst,\n   input  wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_arcache,\n   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          s_axi_arprot,\n//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_arregion,\n   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_arqos,\n   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0]         s_axi_aruser,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_arvalid,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_arready,\n   // Slave Interface Read Data Ports\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_rid,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]           s_axi_rdata,\n   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          s_axi_rresp,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_rlast,\n   output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0]          s_axi_ruser,\n   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_rvalid,\n   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_rready,\n   // Master Interface Write Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_awid,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          m_axi_awaddr,\n   output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         m_axi_awsize,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         m_axi_awburst,\n   output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_awcache,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         m_axi_awprot,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_awregion,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_awqos,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0]        m_axi_awuser,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_awvalid,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_awready,\n   // Master Interface Write Data Ports\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_wid,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]          m_axi_wdata,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0]        m_axi_wstrb,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_wlast,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0]         m_axi_wuser,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_wvalid,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_wready,\n   // Master Interface Write Response Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_bid,\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         m_axi_bresp,\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0]         m_axi_buser,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_bvalid,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_bready,\n   // Master Interface Read Address Port\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_arid,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          m_axi_araddr,\n   output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         m_axi_arsize,\n   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         m_axi_arburst,\n   output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_arcache,\n   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         m_axi_arprot,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_arregion,\n   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_arqos,\n   output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0]        m_axi_aruser,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_arvalid,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_arready,\n   // Master Interface Read Data Ports\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_rid,\n   input  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]          m_axi_rdata,\n   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         m_axi_rresp,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_rlast,\n   input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0]          m_axi_ruser,\n   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_rvalid,\n   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_rready\n);\n\n  localparam [64:0] P_ONES = {65{1'b1}};\n  localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_BASE_ID = f_base_id(0);\n  localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_HIGH_ID = f_high_id(0);\n  localparam integer  P_AXI4 = 0;\n  localparam integer  P_AXI3 = 1;\n  localparam integer  P_AXILITE = 2;\n  localparam [2:0]   P_AXILITE_SIZE = 3'b010;\n  localparam [1:0]   P_INCR = 2'b01;\n  localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_WRITE = f_m_supports_write(0);\n  localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_READ = f_m_supports_read(0);\n  localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_WRITE = f_s_supports_write(0);\n  localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_READ = f_s_supports_read(0);\n  localparam integer C_DEBUG              = 1;\n  localparam integer P_RANGE_CHECK                    = 1;\n                       // 1 (non-zero) = Detect and issue DECERR on the following conditions:\n                       //   a. address range mismatch (no valid MI slot)\n                       //   b. Burst or >32-bit transfer to AxiLite slave\n                       //   c. TrustZone access violation\n                       //   d. R/W direction unsupported by target\n                       // 0 = Pass all transactions (no DECERR):\n                       //   a. Omit DECERR detection and response logic\n                       //   b. Omit address decoder and propagate s_axi_a*REGION to m_axi_a*REGION\n                       //      when C_NUM_MASTER_SLOTS=1 and C_NUM_ADDR_RANGES=1.\n                       //   c. Unpredictable target MI-slot if address mismatch and >1 MI-slot\n                       //   d. Transaction corruption if any burst or >32-bit transfer to AxiLite slave\n                       // Illegal combination: P_RANGE_CHECK = 0 && C_M_AXI_SECURE != 0.\n  localparam integer P_ADDR_DECODE = ((P_RANGE_CHECK == 1) || (C_NUM_MASTER_SLOTS > 1) || (C_NUM_ADDR_RANGES > 1)) ? 1 : 0;  // Always 1\n  localparam [C_NUM_MASTER_SLOTS*32-1:0] P_M_AXI_ERR_MODE            = {C_NUM_MASTER_SLOTS{32'h00000000}};\n                       // Transaction error detection (per MI-slot)\n                       // 0 = None; 1 = AXI4Lite burst violation\n                       // Format: C_NUM_MASTER_SLOTS{Bit32};\n  localparam integer P_LEN = (C_AXI_PROTOCOL == P_AXI3) ? 4 : 8;\n  localparam integer P_LOCK = (C_AXI_PROTOCOL == P_AXI3) ? 2 : 1;\n  localparam P_FAMILY = ((C_FAMILY == \"virtex7\") || (C_FAMILY == \"kintex7\") || (C_FAMILY == \"artix7\") || (C_FAMILY == \"zynq\")) ? C_FAMILY : \"rtl\";\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  // Widths of all write issuance counters implemented in axi_crossbar_v2_1_23_crossbar (before counter carry-out bit)\n  function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_write_issue_width_vec\n    (input null_arg);\n    integer mi;\n    reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;\n    begin\n      result = 0;\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_WRITE_ISSUING[mi*32+:32]);\n      end\n      result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;\n      f_write_issue_width_vec = result;\n    end\n  endfunction\n\n  // Widths of all read issuance counters implemented in axi_crossbar_v2_1_23_crossbar (before counter carry-out bit)\n  function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_read_issue_width_vec\n    (input null_arg);\n    integer mi;\n    reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;\n    begin\n      result = 0;\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_READ_ISSUING[mi*32+:32]);\n      end\n      result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;\n      f_read_issue_width_vec = result;\n    end\n  endfunction\n\n  // Widths of all write acceptance counters implemented in axi_crossbar_v2_1_23_crossbar (before counter carry-out bit)\n  function [C_NUM_SLAVE_SLOTS*32-1:0] f_write_accept_width_vec\n    (input null_arg);\n    integer si;\n    reg [C_NUM_SLAVE_SLOTS*32-1:0] result;\n    begin\n      result = 0;\n      for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin\n        result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_WRITE_ACCEPTANCE[si*32+:32]);\n      end\n      f_write_accept_width_vec = result;\n    end\n  endfunction\n\n  // Widths of all read acceptance counters implemented in axi_crossbar_v2_1_23_crossbar (before counter carry-out bit)\n  function [C_NUM_SLAVE_SLOTS*32-1:0] f_read_accept_width_vec\n    (input null_arg);\n    integer si;\n    reg [C_NUM_SLAVE_SLOTS*32-1:0] result;\n    begin\n      result = 0;\n      for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin\n        result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_READ_ACCEPTANCE[si*32+:32]);\n      end\n      f_read_accept_width_vec = result;\n    end\n  endfunction\n\n  // Convert C_S_AXI_BASE_ID vector from Bit32 to Bit64 format\n  function [C_NUM_SLAVE_SLOTS*64-1:0] f_base_id\n    (input null_arg);\n    integer si;\n    reg [C_NUM_SLAVE_SLOTS*64-1:0] result;\n    begin\n      result = 0;\n      for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin\n        result[si*64+:C_AXI_ID_WIDTH] = C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH];\n      end\n      f_base_id = result;\n    end\n  endfunction\n\n  // Construct P_S_HIGH_ID vector\n  function [C_NUM_SLAVE_SLOTS*64-1:0] f_high_id\n    (input null_arg);\n    integer si;\n    reg [C_NUM_SLAVE_SLOTS*64-1:0] result;\n    begin\n      result = 0;\n      for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin\n        result[si*64+:C_AXI_ID_WIDTH] = (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :\n          ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :\n          (C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));\n      end\n      f_high_id = result;\n    end\n  endfunction\n\n  // Construct P_M_HIGH_ADDR vector\n  function [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] f_high_addr\n    (input null_arg);\n    integer ar;\n    reg [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] result;\n    begin\n      result = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}};\n      for (ar=0; ar<C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES; ar=ar+1) begin\n        result[ar*64+:C_AXI_ADDR_WIDTH] = (C_M_AXI_ADDR_WIDTH[ar*32+:32] == 0) ? 64'h00000000_00000000 : \n          ({1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:31]} >= C_AXI_ADDR_WIDTH) ? {C_AXI_ADDR_WIDTH{1'b1}} :\n          (C_M_AXI_BASE_ADDR[ar*64+:C_AXI_ADDR_WIDTH] | ~(P_ONES << {1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:7]}));\n      end\n      f_high_addr = result;\n    end\n  endfunction\n\n  // Generate a mask of valid ID bits for a given SI slot.\n  function [C_AXI_ID_WIDTH-1:0] f_thread_id_mask\n    (input integer si);\n    begin\n      f_thread_id_mask = \n        (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? {C_AXI_ID_WIDTH{1'b0}} : \n        ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :\n        ({C_AXI_ID_WIDTH{1'b0}} | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));\n      end\n  endfunction\n\n  // Isolate thread bits of input S_ID and add to BASE_ID to form MI-side ID value\n  //   only for end-point SI-slots\n  function [C_AXI_ID_WIDTH-1:0] f_extend_ID (\n    input [C_AXI_ID_WIDTH-1:0] s_id,\n    input integer si\n    );\n    begin\n      f_extend_ID = \n        (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] : \n        ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? s_id :\n        (C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | (s_id &  ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]})));\n    end\n  endfunction\n\n  // Bit vector of SI slots with at least one write connection.\n  function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_write\n    (input null_arg);\n    integer mi;\n    reg [C_NUM_SLAVE_SLOTS-1:0] result;\n    begin\n      result = {C_NUM_SLAVE_SLOTS{1'b0}};\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        result = result | C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];\n      end\n      f_s_supports_write = result;\n    end\n  endfunction\n\n  // Bit vector of SI slots with at least one read connection.\n  function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_read\n    (input null_arg);\n    integer mi;\n    reg [C_NUM_SLAVE_SLOTS-1:0] result;\n    begin\n      result = {C_NUM_SLAVE_SLOTS{1'b0}};\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        result = result | C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];\n      end\n      f_s_supports_read = result;\n    end\n  endfunction\n\n  // Bit vector of MI slots with at least one write connection.\n  function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_write\n    (input null_arg);\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        f_m_supports_write[mi] = (|C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);\n      end\n    end\n  endfunction\n\n  // Bit vector of MI slots with at least one read connection.\n  function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_read\n    (input null_arg);\n    integer mi;\n    begin\n      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin\n        f_m_supports_read[mi] = (|C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);\n      end\n    end\n  endfunction\n\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_awid            ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]        si_cb_awaddr          ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                       si_cb_awlen           ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                       si_cb_awsize          ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_awburst         ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_awlock          ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_awcache         ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                       si_cb_awprot          ;\n//  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_awregion        ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_awqos           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0]      si_cb_awuser          ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_awvalid         ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_awready         ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_wid            ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]        si_cb_wdata           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0]      si_cb_wstrb           ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_wlast           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0]       si_cb_wuser           ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_wvalid          ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_wready          ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_bid             ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_bresp           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0]       si_cb_buser           ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_bvalid          ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_bready          ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_arid            ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]        si_cb_araddr          ;\n  wire [C_NUM_SLAVE_SLOTS*8-1:0]                       si_cb_arlen           ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                       si_cb_arsize          ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_arburst         ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_arlock          ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_arcache         ;\n  wire [C_NUM_SLAVE_SLOTS*3-1:0]                       si_cb_arprot          ;\n//  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_arregion        ;\n  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_arqos           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0]      si_cb_aruser          ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_arvalid         ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_arready         ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_rid             ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]        si_cb_rdata           ;\n  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_rresp           ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_rlast           ;\n  wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0]       si_cb_ruser           ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_rvalid          ;\n  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_rready          ;\n\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_awid            ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]       cb_mi_awaddr          ;\n  wire [C_NUM_MASTER_SLOTS*8-1:0]                      cb_mi_awlen           ;\n  wire [C_NUM_MASTER_SLOTS*3-1:0]                      cb_mi_awsize          ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_awburst         ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_awlock          ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_awcache         ;\n  wire [C_NUM_MASTER_SLOTS*3-1:0]                      cb_mi_awprot          ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_awregion        ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_awqos           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0]     cb_mi_awuser          ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_awvalid         ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_awready         ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_wid             ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]       cb_mi_wdata           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0]     cb_mi_wstrb           ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_wlast           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0]      cb_mi_wuser           ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_wvalid          ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_wready          ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_bid             ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_bresp           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0]      cb_mi_buser           ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_bvalid          ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_bready          ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_arid            ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]       cb_mi_araddr          ;\n  wire [C_NUM_MASTER_SLOTS*8-1:0]                      cb_mi_arlen           ;\n  wire [C_NUM_MASTER_SLOTS*3-1:0]                      cb_mi_arsize          ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_arburst         ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_arlock          ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_arcache         ;\n  wire [C_NUM_MASTER_SLOTS*3-1:0]                      cb_mi_arprot          ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_arregion        ;\n  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_arqos           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0]     cb_mi_aruser          ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_arvalid         ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_arready         ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_rid             ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]       cb_mi_rdata           ;\n  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_rresp           ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_rlast           ;\n  wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0]      cb_mi_ruser           ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_rvalid          ;\n  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_rready          ;\n  \n  genvar slot;\n\ngenerate\n    for (slot=0;slot<C_NUM_SLAVE_SLOTS;slot=slot+1) begin : gen_si_tieoff\n      assign si_cb_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? (s_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))              : 0 ;\n      assign si_cb_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       : 0 ;\n      assign si_cb_awlen[slot*8+:8]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awlen[slot*P_LEN+:P_LEN] : 0 ;\n      assign si_cb_awsize[slot*3+:3]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awsize[slot*3+:3]                                                     : P_AXILITE_SIZE ;\n      assign si_cb_awburst[slot*2+:2]                                                    = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awburst[slot*2+:2]                                                    : P_INCR ;\n      assign si_cb_awlock[slot*2+:2]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? {1'b0, s_axi_awlock[slot*P_LOCK+:1]}                                             : 0 ;\n      assign si_cb_awcache[slot*4+:4]                                                    = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awcache[slot*4+:4]                                                    : 0 ;\n      assign si_cb_awprot[slot*3+:3]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_awprot[slot*3+:3]                                                     : 0 ;\n      assign si_cb_awqos[slot*4+:4]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awqos[slot*4+:4]                                                      : 0 ;\n//      assign si_cb_awregion[slot*4+:4]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4)                                ) ? s_axi_awregion[slot*4+:4]                                                      : 0 ;\n      assign si_cb_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH]                   = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH]                   : 0 ;\n      assign si_cb_awvalid[slot*1+:1]                                                    = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_awvalid[slot*1+:1]                                                    : 0 ;\n      assign si_cb_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI3)                                   ) ? (s_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))   : 0 ;\n      assign si_cb_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]                        = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]     : 0 ;\n      assign si_cb_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]                    = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;\n      assign si_cb_wlast[slot*1+:1]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_wlast[slot*1+:1]                                                      : 1'b1 ;\n      assign si_cb_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]                      : 0 ;\n      assign si_cb_wvalid[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_wvalid[slot*1+:1]                                                     : 0 ;\n      assign si_cb_bready[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_bready[slot*1+:1]                                                     : 0 ;\n      assign si_cb_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? (s_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))              : 0 ;\n      assign si_cb_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? s_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       : 0 ;\n      assign si_cb_arlen[slot*8+:8]                                                      = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_arlen[slot*P_LEN+:P_LEN] : 0 ;\n      assign si_cb_arsize[slot*3+:3]                                                     = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_arsize[slot*3+:3]                                                     : P_AXILITE_SIZE ;\n      assign si_cb_arburst[slot*2+:2]                                                    = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_arburst[slot*2+:2]                                                    : P_INCR ;\n      assign si_cb_arlock[slot*2+:2]                                                     = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? {1'b0, s_axi_arlock[slot*P_LOCK+:1]}                                             : 0 ;\n      assign si_cb_arcache[slot*4+:4]                                                    = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                  ) ? s_axi_arcache[slot*4+:4]                                                    : 0 ;\n      assign si_cb_arprot[slot*3+:3]                                                     = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? s_axi_arprot[slot*3+:3]                                                     : 0 ;\n      assign si_cb_arqos[slot*4+:4]                                                      = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_arqos[slot*4+:4]                                                      : 0 ;\n//      assign si_cb_arregion[slot*4+:4]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4)                                ) ? s_axi_arregion[slot*4+:4]                                                      : 0 ;\n      assign si_cb_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH]                   = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH]                   : 0 ;\n      assign si_cb_arvalid[slot*1+:1]                                                    = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? s_axi_arvalid[slot*1+:1]                                                    : 0 ;\n      assign si_cb_rready[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? s_axi_rready[slot*1+:1]                                                     : 0 ;                                       \n\n      assign s_axi_awready[slot*1+:1]                                                    = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? si_cb_awready[slot*1+:1]                                                    : 0 ;\n      assign s_axi_wready[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? si_cb_wready[slot*1+:1]                                                     : 0 ;\n      assign s_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? (si_cb_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))               : 0 ;\n      assign s_axi_bresp[slot*2+:2]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? si_cb_bresp[slot*2+:2]                                                      : 0 ;\n      assign s_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                      : 0 ;\n      assign s_axi_bvalid[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? si_cb_bvalid[slot*1+:1]                                                     : 0 ;\n      assign s_axi_arready[slot*1+:1]                                                    = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? si_cb_arready[slot*1+:1]                                                    : 0 ;\n      assign s_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? (si_cb_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))               : 0 ;\n      assign s_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]                        = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? si_cb_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]     : 0 ;\n      assign s_axi_rresp[slot*2+:2]                                                      = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? si_cb_rresp[slot*2+:2]                                                      : 0 ;\n      assign s_axi_rlast[slot*1+:1]                                                      = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? si_cb_rlast[slot*1+:1]                                                      : 0 ;\n      assign s_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                      = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                      : 0 ;\n      assign s_axi_rvalid[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? si_cb_rvalid[slot*1+:1]                                                     : 0 ;\n    end  // gen_si_tieoff\n\n    for (slot=0;slot<C_NUM_MASTER_SLOTS;slot=slot+1) begin : gen_mi_tieoff\n      assign m_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             : 0 ;\n      assign m_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       : 0 ;\n      assign m_axi_awlen[slot*P_LEN+:P_LEN]                                              = (~P_M_AXI_SUPPORTS_WRITE[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4                             ) ? cb_mi_awlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_awlen[slot*8+:4] : 0 ;\n      assign m_axi_awsize[slot*3+:3]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awsize[slot*3+:3]                                                     : 0 ;\n      assign m_axi_awburst[slot*2+:2]                                                    = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awburst[slot*2+:2]                                                    : 0 ;\n      assign m_axi_awlock[slot*P_LOCK+:P_LOCK]                                           = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awlock[slot*2+:1]                                                     : 0 ;\n      assign m_axi_awcache[slot*4+:4]                                                    = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awcache[slot*4+:4]                                                    : 0 ;\n      assign m_axi_awprot[slot*3+:3]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_awprot[slot*3+:3]                                                     : 0 ;\n      assign m_axi_awregion[slot*4+:4]                                                   = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL==P_AXI4)                                 ) ? cb_mi_awregion[slot*4+:4]                                                   : 0 ;\n      assign m_axi_awqos[slot*4+:4]                                                      = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awqos[slot*4+:4]                                                      : 0 ;\n      assign m_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH]                   = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH]                   : 0 ;\n      assign m_axi_awvalid[slot*1+:1]                                                    = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_awvalid[slot*1+:1]                                                    : 0 ;\n      assign m_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              : 0 ;\n      assign m_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]                        = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]     : 0 ;\n      assign m_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]                    = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;\n      assign m_axi_wlast[slot*1+:1]                                                      = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_wlast[slot*1+:1]                                                      : 0 ;\n      assign m_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]                      = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]                      : 0 ;\n      assign m_axi_wvalid[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_wvalid[slot*1+:1]                                                     : 0 ;\n      assign m_axi_bready[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_bready[slot*1+:1]                                                     : 0 ;\n      assign m_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                            : 0 ;\n      assign m_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? cb_mi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       : 0 ;\n      assign m_axi_arlen[slot*P_LEN+:P_LEN]                                              = (~P_M_AXI_SUPPORTS_READ[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4                             ) ? cb_mi_arlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_arlen[slot*8+:4] : 0 ;\n      assign m_axi_arsize[slot*3+:3]                                                     = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arsize[slot*3+:3]                                                     : 0 ;\n      assign m_axi_arburst[slot*2+:2]                                                    = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arburst[slot*2+:2]                                                    : 0 ;\n      assign m_axi_arlock[slot*P_LOCK+:P_LOCK]                                           = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arlock[slot*2+:1]                                                     : 0 ;\n      assign m_axi_arcache[slot*4+:4]                                                    = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arcache[slot*4+:4]                                                    : 0 ;\n      assign m_axi_arprot[slot*3+:3]                                                     = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? cb_mi_arprot[slot*3+:3]                                                     : 0 ;\n      assign m_axi_arregion[slot*4+:4]                                                   = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL==P_AXI4)                                 ) ? cb_mi_arregion[slot*4+:4]                                                   : 0 ;\n      assign m_axi_arqos[slot*4+:4]                                                      = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arqos[slot*4+:4]                                                      : 0 ;\n      assign m_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH]                   = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH]                   : 0 ;\n      assign m_axi_arvalid[slot*1+:1]                                                    = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? cb_mi_arvalid[slot*1+:1]                                                    : 0 ;\n      assign m_axi_rready[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? cb_mi_rready[slot*1+:1]                                                     : 0 ;\n\n      assign cb_mi_awready[slot*1+:1]                                                    = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? m_axi_awready[slot*1+:1]                                                    : 0 ;\n      assign cb_mi_wready[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? m_axi_wready[slot*1+:1]                                                     : 0 ;\n      assign cb_mi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? m_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              : 0 ;\n      assign cb_mi_bresp[slot*2+:2]                                                      = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? m_axi_bresp[slot*2+:2]                                                      : 0 ;\n      assign cb_mi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                      = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                      : 0 ;\n      assign cb_mi_bvalid[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? m_axi_bvalid[slot*1+:1]                                                     : 0 ;\n      assign cb_mi_arready[slot*1+:1]                                                    = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? m_axi_arready[slot*1+:1]                                                    : 0 ;\n      assign cb_mi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? m_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              : 0 ;\n      assign cb_mi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]                        = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? m_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]     : 0 ;\n      assign cb_mi_rresp[slot*2+:2]                                                      = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? m_axi_rresp[slot*2+:2]                                                      : 0 ;\n      assign cb_mi_rlast[slot*1+:1]                                                      = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? m_axi_rlast[slot*1+:1]                                                      : 1'b1 ;\n      assign cb_mi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                      = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                      : 0 ;\n      assign cb_mi_rvalid[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? m_axi_rvalid[slot*1+:1]                                                     : 0 ;\n    end  // gen_mi_tieoff\n\n    if ((C_CONNECTIVITY_MODE==0) || (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_sasd\n      axi_crossbar_v2_1_23_crossbar_sasd #\n      (\n        .C_FAMILY                         (P_FAMILY),\n        .C_NUM_SLAVE_SLOTS                (C_NUM_SLAVE_SLOTS),\n        .C_NUM_MASTER_SLOTS               (C_NUM_MASTER_SLOTS),\n        .C_NUM_ADDR_RANGES                (C_NUM_ADDR_RANGES),\n        .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),\n        .C_AXI_ADDR_WIDTH                 (C_AXI_ADDR_WIDTH),\n        .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),\n        .C_AXI_PROTOCOL                   (C_AXI_PROTOCOL),\n        .C_M_AXI_BASE_ADDR                (C_M_AXI_BASE_ADDR),\n        .C_M_AXI_HIGH_ADDR                (f_high_addr(0)),\n        .C_S_AXI_BASE_ID                  (P_S_AXI_BASE_ID),\n        .C_S_AXI_HIGH_ID                  (P_S_AXI_HIGH_ID),\n        .C_AXI_SUPPORTS_USER_SIGNALS      (C_AXI_SUPPORTS_USER_SIGNALS),\n        .C_AXI_AWUSER_WIDTH               (C_AXI_AWUSER_WIDTH),\n        .C_AXI_ARUSER_WIDTH               (C_AXI_ARUSER_WIDTH),\n        .C_AXI_WUSER_WIDTH                (C_AXI_WUSER_WIDTH),\n        .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),\n        .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),\n        .C_S_AXI_SUPPORTS_WRITE           (P_S_AXI_SUPPORTS_WRITE),\n        .C_S_AXI_SUPPORTS_READ            (P_S_AXI_SUPPORTS_READ),\n        .C_M_AXI_SUPPORTS_WRITE           (P_M_AXI_SUPPORTS_WRITE),\n        .C_M_AXI_SUPPORTS_READ            (P_M_AXI_SUPPORTS_READ),\n        .C_S_AXI_ARB_PRIORITY             (C_S_AXI_ARB_PRIORITY),\n        .C_M_AXI_SECURE                   (C_M_AXI_SECURE),\n        .C_R_REGISTER                     (C_R_REGISTER),\n        .C_RANGE_CHECK                    (P_RANGE_CHECK),\n        .C_ADDR_DECODE                    (P_ADDR_DECODE),\n        .C_M_AXI_ERR_MODE                 (P_M_AXI_ERR_MODE),\n        .C_DEBUG                          (C_DEBUG)\n      )\n        crossbar_sasd_0\n      (\n          .ACLK                             (aclk),\n          .ARESETN                          (aresetn),\n          .S_AXI_AWID                       (si_cb_awid           ),\n          .S_AXI_AWADDR                     (si_cb_awaddr         ),\n          .S_AXI_AWLEN                      (si_cb_awlen          ),\n          .S_AXI_AWSIZE                     (si_cb_awsize         ),\n          .S_AXI_AWBURST                    (si_cb_awburst        ),\n          .S_AXI_AWLOCK                     (si_cb_awlock         ),\n          .S_AXI_AWCACHE                    (si_cb_awcache        ),\n          .S_AXI_AWPROT                     (si_cb_awprot         ),\n//          .S_AXI_AWREGION                   (si_cb_awregion       ),\n          .S_AXI_AWQOS                      (si_cb_awqos          ),\n          .S_AXI_AWUSER                     (si_cb_awuser         ),\n          .S_AXI_AWVALID                    (si_cb_awvalid        ),\n          .S_AXI_AWREADY                    (si_cb_awready        ),\n          .S_AXI_WID                        (si_cb_wid             ),\n          .S_AXI_WDATA                      (si_cb_wdata          ),\n          .S_AXI_WSTRB                      (si_cb_wstrb          ),\n          .S_AXI_WLAST                      (si_cb_wlast          ),\n          .S_AXI_WUSER                      (si_cb_wuser          ),\n          .S_AXI_WVALID                     (si_cb_wvalid         ),\n          .S_AXI_WREADY                     (si_cb_wready         ),\n          .S_AXI_BID                        (si_cb_bid            ),\n          .S_AXI_BRESP                      (si_cb_bresp          ),\n          .S_AXI_BUSER                      (si_cb_buser          ),\n          .S_AXI_BVALID                     (si_cb_bvalid         ),\n          .S_AXI_BREADY                     (si_cb_bready         ),\n          .S_AXI_ARID                       (si_cb_arid           ),\n          .S_AXI_ARADDR                     (si_cb_araddr         ),\n          .S_AXI_ARLEN                      (si_cb_arlen          ),\n          .S_AXI_ARSIZE                     (si_cb_arsize         ),\n          .S_AXI_ARBURST                    (si_cb_arburst        ),\n          .S_AXI_ARLOCK                     (si_cb_arlock         ),\n          .S_AXI_ARCACHE                    (si_cb_arcache        ),\n          .S_AXI_ARPROT                     (si_cb_arprot         ),\n//          .S_AXI_ARREGION                   (si_cb_arregion       ),\n          .S_AXI_ARQOS                      (si_cb_arqos          ),\n          .S_AXI_ARUSER                     (si_cb_aruser         ),\n          .S_AXI_ARVALID                    (si_cb_arvalid        ),\n          .S_AXI_ARREADY                    (si_cb_arready        ),\n          .S_AXI_RID                        (si_cb_rid            ),\n          .S_AXI_RDATA                      (si_cb_rdata          ),\n          .S_AXI_RRESP                      (si_cb_rresp          ),\n          .S_AXI_RLAST                      (si_cb_rlast          ),\n          .S_AXI_RUSER                      (si_cb_ruser          ),\n          .S_AXI_RVALID                     (si_cb_rvalid         ),\n          .S_AXI_RREADY                     (si_cb_rready         ),\n          .M_AXI_AWID                       (cb_mi_awid           ),\n          .M_AXI_AWADDR                     (cb_mi_awaddr         ),\n          .M_AXI_AWLEN                      (cb_mi_awlen          ),\n          .M_AXI_AWSIZE                     (cb_mi_awsize         ),\n          .M_AXI_AWBURST                    (cb_mi_awburst        ),\n          .M_AXI_AWLOCK                     (cb_mi_awlock         ),\n          .M_AXI_AWCACHE                    (cb_mi_awcache        ),\n          .M_AXI_AWPROT                     (cb_mi_awprot         ),\n          .M_AXI_AWREGION                   (cb_mi_awregion       ),\n          .M_AXI_AWQOS                      (cb_mi_awqos          ),\n          .M_AXI_AWUSER                     (cb_mi_awuser         ),\n          .M_AXI_AWVALID                    (cb_mi_awvalid        ),\n          .M_AXI_AWREADY                    (cb_mi_awready        ),\n          .M_AXI_WID                        (cb_mi_wid             ),\n          .M_AXI_WDATA                      (cb_mi_wdata          ),\n          .M_AXI_WSTRB                      (cb_mi_wstrb          ),\n          .M_AXI_WLAST                      (cb_mi_wlast          ),\n          .M_AXI_WUSER                      (cb_mi_wuser          ),\n          .M_AXI_WVALID                     (cb_mi_wvalid         ),\n          .M_AXI_WREADY                     (cb_mi_wready         ),\n          .M_AXI_BID                        (cb_mi_bid            ),\n          .M_AXI_BRESP                      (cb_mi_bresp          ),\n          .M_AXI_BUSER                      (cb_mi_buser          ),\n          .M_AXI_BVALID                     (cb_mi_bvalid         ),\n          .M_AXI_BREADY                     (cb_mi_bready         ),\n          .M_AXI_ARID                       (cb_mi_arid           ),\n          .M_AXI_ARADDR                     (cb_mi_araddr         ),\n          .M_AXI_ARLEN                      (cb_mi_arlen          ),\n          .M_AXI_ARSIZE                     (cb_mi_arsize         ),\n          .M_AXI_ARBURST                    (cb_mi_arburst        ),\n          .M_AXI_ARLOCK                     (cb_mi_arlock         ),\n          .M_AXI_ARCACHE                    (cb_mi_arcache        ),\n          .M_AXI_ARPROT                     (cb_mi_arprot         ),\n          .M_AXI_ARREGION                   (cb_mi_arregion       ),\n          .M_AXI_ARQOS                      (cb_mi_arqos          ),\n          .M_AXI_ARUSER                     (cb_mi_aruser         ),\n          .M_AXI_ARVALID                    (cb_mi_arvalid        ),\n          .M_AXI_ARREADY                    (cb_mi_arready        ),\n          .M_AXI_RID                        (cb_mi_rid            ),\n          .M_AXI_RDATA                      (cb_mi_rdata          ),\n          .M_AXI_RRESP                      (cb_mi_rresp          ),\n          .M_AXI_RLAST                      (cb_mi_rlast          ),\n          .M_AXI_RUSER                      (cb_mi_ruser          ),\n          .M_AXI_RVALID                     (cb_mi_rvalid         ),\n          .M_AXI_RREADY                     (cb_mi_rready         )\n      );\n    end else begin : gen_samd\n      axi_crossbar_v2_1_23_crossbar #\n      (\n        .C_FAMILY                         (P_FAMILY),\n        .C_NUM_SLAVE_SLOTS                (C_NUM_SLAVE_SLOTS),\n        .C_NUM_MASTER_SLOTS               (C_NUM_MASTER_SLOTS),\n        .C_NUM_ADDR_RANGES                (C_NUM_ADDR_RANGES),\n        .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),\n        .C_S_AXI_THREAD_ID_WIDTH          (C_S_AXI_THREAD_ID_WIDTH),\n        .C_AXI_ADDR_WIDTH                 (C_AXI_ADDR_WIDTH),\n        .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),\n        .C_AXI_PROTOCOL                   (C_AXI_PROTOCOL),\n        .C_M_AXI_BASE_ADDR                (C_M_AXI_BASE_ADDR),\n        .C_M_AXI_HIGH_ADDR                (f_high_addr(0)),\n        .C_S_AXI_BASE_ID                  (P_S_AXI_BASE_ID),\n        .C_S_AXI_HIGH_ID                  (P_S_AXI_HIGH_ID),\n        .C_AXI_SUPPORTS_USER_SIGNALS      (C_AXI_SUPPORTS_USER_SIGNALS),\n        .C_AXI_AWUSER_WIDTH               (C_AXI_AWUSER_WIDTH),\n        .C_AXI_ARUSER_WIDTH               (C_AXI_ARUSER_WIDTH),\n        .C_AXI_WUSER_WIDTH                (C_AXI_WUSER_WIDTH),\n        .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),\n        .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),\n        .C_S_AXI_SUPPORTS_WRITE           (P_S_AXI_SUPPORTS_WRITE),\n        .C_S_AXI_SUPPORTS_READ            (P_S_AXI_SUPPORTS_READ),\n        .C_M_AXI_SUPPORTS_WRITE           (P_M_AXI_SUPPORTS_WRITE),\n        .C_M_AXI_SUPPORTS_READ            (P_M_AXI_SUPPORTS_READ),\n        .C_M_AXI_WRITE_CONNECTIVITY       (C_M_AXI_WRITE_CONNECTIVITY),\n        .C_M_AXI_READ_CONNECTIVITY        (C_M_AXI_READ_CONNECTIVITY),\n        .C_S_AXI_SINGLE_THREAD            (C_S_AXI_SINGLE_THREAD),\n        .C_S_AXI_WRITE_ACCEPTANCE         (C_S_AXI_WRITE_ACCEPTANCE),\n        .C_S_AXI_READ_ACCEPTANCE          (C_S_AXI_READ_ACCEPTANCE),\n        .C_M_AXI_WRITE_ISSUING            (C_M_AXI_WRITE_ISSUING),\n        .C_M_AXI_READ_ISSUING             (C_M_AXI_READ_ISSUING),\n        .C_S_AXI_ARB_PRIORITY             (C_S_AXI_ARB_PRIORITY),\n        .C_M_AXI_SECURE                   (C_M_AXI_SECURE),\n        .C_RANGE_CHECK                    (P_RANGE_CHECK),\n        .C_ADDR_DECODE                    (P_ADDR_DECODE),\n        .C_W_ISSUE_WIDTH                  (f_write_issue_width_vec(0) ),\n        .C_R_ISSUE_WIDTH                  (f_read_issue_width_vec(0) ),\n        .C_W_ACCEPT_WIDTH                 (f_write_accept_width_vec(0)),\n        .C_R_ACCEPT_WIDTH                 (f_read_accept_width_vec(0)),\n        .C_M_AXI_ERR_MODE                 (P_M_AXI_ERR_MODE),\n        .C_DEBUG                          (C_DEBUG)\n      )\n        crossbar_samd \n      (\n          .ACLK                             (aclk),\n          .ARESETN                          (aresetn),\n          .S_AXI_AWID                       (si_cb_awid             ),\n          .S_AXI_AWADDR                     (si_cb_awaddr           ),\n          .S_AXI_AWLEN                      (si_cb_awlen            ),\n          .S_AXI_AWSIZE                     (si_cb_awsize           ),\n          .S_AXI_AWBURST                    (si_cb_awburst          ),\n          .S_AXI_AWLOCK                     (si_cb_awlock           ),\n          .S_AXI_AWCACHE                    (si_cb_awcache          ),\n          .S_AXI_AWPROT                     (si_cb_awprot           ),\n//          .S_AXI_AWREGION                   (si_cb_awregion       ),\n          .S_AXI_AWQOS                      (si_cb_awqos            ),\n          .S_AXI_AWUSER                     (si_cb_awuser           ),\n          .S_AXI_AWVALID                    (si_cb_awvalid          ),\n          .S_AXI_AWREADY                    (si_cb_awready          ),\n          .S_AXI_WID                        (si_cb_wid             ),\n          .S_AXI_WDATA                      (si_cb_wdata            ),\n          .S_AXI_WSTRB                      (si_cb_wstrb            ),\n          .S_AXI_WLAST                      (si_cb_wlast            ),\n          .S_AXI_WUSER                      (si_cb_wuser            ),\n          .S_AXI_WVALID                     (si_cb_wvalid           ),\n          .S_AXI_WREADY                     (si_cb_wready           ),\n          .S_AXI_BID                        (si_cb_bid              ),\n          .S_AXI_BRESP                      (si_cb_bresp            ),\n          .S_AXI_BUSER                      (si_cb_buser            ),\n          .S_AXI_BVALID                     (si_cb_bvalid           ),\n          .S_AXI_BREADY                     (si_cb_bready           ),\n          .S_AXI_ARID                       (si_cb_arid             ),\n          .S_AXI_ARADDR                     (si_cb_araddr           ),\n          .S_AXI_ARLEN                      (si_cb_arlen            ),\n          .S_AXI_ARSIZE                     (si_cb_arsize           ),\n          .S_AXI_ARBURST                    (si_cb_arburst          ),\n          .S_AXI_ARLOCK                     (si_cb_arlock           ),\n          .S_AXI_ARCACHE                    (si_cb_arcache          ),\n          .S_AXI_ARPROT                     (si_cb_arprot           ),\n//          .S_AXI_ARREGION                   (si_cb_arregion       ),\n          .S_AXI_ARQOS                      (si_cb_arqos            ),\n          .S_AXI_ARUSER                     (si_cb_aruser           ),\n          .S_AXI_ARVALID                    (si_cb_arvalid          ),\n          .S_AXI_ARREADY                    (si_cb_arready          ),\n          .S_AXI_RID                        (si_cb_rid              ),\n          .S_AXI_RDATA                      (si_cb_rdata            ),\n          .S_AXI_RRESP                      (si_cb_rresp            ),\n          .S_AXI_RLAST                      (si_cb_rlast            ),\n          .S_AXI_RUSER                      (si_cb_ruser            ),\n          .S_AXI_RVALID                     (si_cb_rvalid           ),\n          .S_AXI_RREADY                     (si_cb_rready           ),\n          .M_AXI_AWID                       (cb_mi_awid             ),\n          .M_AXI_AWADDR                     (cb_mi_awaddr           ),\n          .M_AXI_AWLEN                      (cb_mi_awlen            ),\n          .M_AXI_AWSIZE                     (cb_mi_awsize           ),\n          .M_AXI_AWBURST                    (cb_mi_awburst          ),\n          .M_AXI_AWLOCK                     (cb_mi_awlock           ),\n          .M_AXI_AWCACHE                    (cb_mi_awcache          ),\n          .M_AXI_AWPROT                     (cb_mi_awprot           ),\n          .M_AXI_AWREGION                   (cb_mi_awregion         ),\n          .M_AXI_AWQOS                      (cb_mi_awqos            ),\n          .M_AXI_AWUSER                     (cb_mi_awuser           ),\n          .M_AXI_AWVALID                    (cb_mi_awvalid          ),\n          .M_AXI_AWREADY                    (cb_mi_awready          ),\n          .M_AXI_WID                        (cb_mi_wid             ),\n          .M_AXI_WDATA                      (cb_mi_wdata            ),\n          .M_AXI_WSTRB                      (cb_mi_wstrb            ),\n          .M_AXI_WLAST                      (cb_mi_wlast            ),\n          .M_AXI_WUSER                      (cb_mi_wuser            ),\n          .M_AXI_WVALID                     (cb_mi_wvalid           ),\n          .M_AXI_WREADY                     (cb_mi_wready           ),\n          .M_AXI_BID                        (cb_mi_bid              ),\n          .M_AXI_BRESP                      (cb_mi_bresp            ),\n          .M_AXI_BUSER                      (cb_mi_buser            ),\n          .M_AXI_BVALID                     (cb_mi_bvalid           ),\n          .M_AXI_BREADY                     (cb_mi_bready           ),\n          .M_AXI_ARID                       (cb_mi_arid             ),\n          .M_AXI_ARADDR                     (cb_mi_araddr           ),\n          .M_AXI_ARLEN                      (cb_mi_arlen            ),\n          .M_AXI_ARSIZE                     (cb_mi_arsize           ),\n          .M_AXI_ARBURST                    (cb_mi_arburst          ),\n          .M_AXI_ARLOCK                     (cb_mi_arlock           ),\n          .M_AXI_ARCACHE                    (cb_mi_arcache          ),\n          .M_AXI_ARPROT                     (cb_mi_arprot           ),\n          .M_AXI_ARREGION                   (cb_mi_arregion         ),\n          .M_AXI_ARQOS                      (cb_mi_arqos            ),\n          .M_AXI_ARUSER                     (cb_mi_aruser           ),\n          .M_AXI_ARVALID                    (cb_mi_arvalid          ),\n          .M_AXI_ARREADY                    (cb_mi_arready          ),\n          .M_AXI_RID                        (cb_mi_rid              ),\n          .M_AXI_RDATA                      (cb_mi_rdata            ),\n          .M_AXI_RRESP                      (cb_mi_rresp            ),\n          .M_AXI_RLAST                      (cb_mi_rlast            ),\n          .M_AXI_RUSER                      (cb_mi_ruser            ),\n          .M_AXI_RVALID                     (cb_mi_rvalid           ),\n          .M_AXI_RREADY                     (cb_mi_rready           )\n      );\n    end  // gen_samd\n//  end  // gen_crossbar\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n", "num_lines": 5805}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020\n//Date        : Wed Dec 15 00:42:21 2021\n//Host        : a-21awsprq4sria running 64-bit Amazon Linux release 2 (Karoo)\n//Command     : generate_target cl_axi_interconnect.bd\n//Design      : cl_axi_interconnect\n//Purpose     : IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=cl_axi_interconnect,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=14,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}\" *) (* HW_HANDOFF = \"cl_axi_interconnect.hwdef\" *) \nmodule cl_axi_interconnect\n   (ACLK,\n    ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.ACLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF S00_AXI:M00_AXI:M01_AXI:M02_AXI:M03_AXI:S01_AXI, ASSOCIATED_RESET ARESETN, CLK_DOMAIN cl_axi_interconnect_ACLK, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input ACLK;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.ARESETN RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW\" *) input ARESETN;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M00_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M00_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARBURST\" *) output [1:0]M00_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE\" *) output [3:0]M00_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARID\" *) output [6:0]M00_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLEN\" *) output [7:0]M00_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK\" *) output [0:0]M00_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARPROT\" *) output [2:0]M00_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARQOS\" *) output [3:0]M00_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREADY\" *) input M00_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREGION\" *) output [3:0]M00_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE\" *) output [2:0]M00_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARVALID\" *) output M00_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWADDR\" *) output [63:0]M00_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWBURST\" *) output [1:0]M00_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE\" *) output [3:0]M00_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWID\" *) output [6:0]M00_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLEN\" *) output [7:0]M00_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK\" *) output [0:0]M00_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWPROT\" *) output [2:0]M00_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWQOS\" *) output [3:0]M00_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREADY\" *) input M00_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREGION\" *) output [3:0]M00_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE\" *) output [2:0]M00_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWVALID\" *) output M00_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BID\" *) input [6:0]M00_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BREADY\" *) output M00_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BRESP\" *) input [1:0]M00_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BVALID\" *) input M00_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RDATA\" *) input [511:0]M00_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RID\" *) input [6:0]M00_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RLAST\" *) input M00_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RREADY\" *) output M00_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RRESP\" *) input [1:0]M00_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RVALID\" *) input M00_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WDATA\" *) output [511:0]M00_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WLAST\" *) output M00_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WREADY\" *) input M00_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WSTRB\" *) output [63:0]M00_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WVALID\" *) output M00_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M01_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M01_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARBURST\" *) output [1:0]M01_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE\" *) output [3:0]M01_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARID\" *) output [6:0]M01_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARLEN\" *) output [7:0]M01_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK\" *) output [0:0]M01_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARPROT\" *) output [2:0]M01_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARQOS\" *) output [3:0]M01_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARREADY\" *) input M01_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARREGION\" *) output [3:0]M01_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE\" *) output [2:0]M01_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARVALID\" *) output M01_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWADDR\" *) output [63:0]M01_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWBURST\" *) output [1:0]M01_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE\" *) output [3:0]M01_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWID\" *) output [6:0]M01_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWLEN\" *) output [7:0]M01_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK\" *) output [0:0]M01_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWPROT\" *) output [2:0]M01_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWQOS\" *) output [3:0]M01_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWREADY\" *) input M01_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWREGION\" *) output [3:0]M01_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE\" *) output [2:0]M01_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWVALID\" *) output M01_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BID\" *) input [6:0]M01_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BREADY\" *) output M01_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BRESP\" *) input [1:0]M01_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BVALID\" *) input M01_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RDATA\" *) input [511:0]M01_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RID\" *) input [6:0]M01_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RLAST\" *) input M01_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RREADY\" *) output M01_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RRESP\" *) input [1:0]M01_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RVALID\" *) input M01_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WDATA\" *) output [511:0]M01_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WLAST\" *) output M01_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WREADY\" *) input M01_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WSTRB\" *) output [63:0]M01_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WVALID\" *) output M01_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M02_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M02_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARBURST\" *) output [1:0]M02_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE\" *) output [3:0]M02_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARID\" *) output [6:0]M02_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARLEN\" *) output [7:0]M02_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK\" *) output [0:0]M02_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARPROT\" *) output [2:0]M02_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARQOS\" *) output [3:0]M02_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARREADY\" *) input M02_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARREGION\" *) output [3:0]M02_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE\" *) output [2:0]M02_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARVALID\" *) output M02_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWADDR\" *) output [63:0]M02_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWBURST\" *) output [1:0]M02_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE\" *) output [3:0]M02_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWID\" *) output [6:0]M02_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWLEN\" *) output [7:0]M02_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK\" *) output [0:0]M02_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWPROT\" *) output [2:0]M02_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWQOS\" *) output [3:0]M02_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWREADY\" *) input M02_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWREGION\" *) output [3:0]M02_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE\" *) output [2:0]M02_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWVALID\" *) output M02_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BID\" *) input [6:0]M02_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BREADY\" *) output M02_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BRESP\" *) input [1:0]M02_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BVALID\" *) input M02_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RDATA\" *) input [511:0]M02_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RID\" *) input [6:0]M02_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RLAST\" *) input M02_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RREADY\" *) output M02_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RRESP\" *) input [1:0]M02_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RVALID\" *) input M02_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WDATA\" *) output [511:0]M02_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WLAST\" *) output M02_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WREADY\" *) input M02_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WSTRB\" *) output [63:0]M02_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WVALID\" *) output M02_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M03_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M03_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARBURST\" *) output [1:0]M03_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE\" *) output [3:0]M03_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARID\" *) output [6:0]M03_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARLEN\" *) output [7:0]M03_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK\" *) output [0:0]M03_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARPROT\" *) output [2:0]M03_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARQOS\" *) output [3:0]M03_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARREADY\" *) input M03_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARREGION\" *) output [3:0]M03_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE\" *) output [2:0]M03_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARVALID\" *) output M03_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWADDR\" *) output [63:0]M03_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWBURST\" *) output [1:0]M03_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE\" *) output [3:0]M03_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWID\" *) output [6:0]M03_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWLEN\" *) output [7:0]M03_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK\" *) output [0:0]M03_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWPROT\" *) output [2:0]M03_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWQOS\" *) output [3:0]M03_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWREADY\" *) input M03_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWREGION\" *) output [3:0]M03_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE\" *) output [2:0]M03_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWVALID\" *) output M03_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BID\" *) input [6:0]M03_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BREADY\" *) output M03_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BRESP\" *) input [1:0]M03_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BVALID\" *) input M03_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RDATA\" *) input [511:0]M03_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RID\" *) input [6:0]M03_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RLAST\" *) input M03_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RREADY\" *) output M03_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RRESP\" *) input [1:0]M03_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RVALID\" *) input M03_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WDATA\" *) output [511:0]M03_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WLAST\" *) output M03_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WREADY\" *) input M03_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WSTRB\" *) output [63:0]M03_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WVALID\" *) output M03_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S00_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 6, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 32, NUM_READ_THREADS 16, NUM_WRITE_OUTSTANDING 32, NUM_WRITE_THREADS 16, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) input [63:0]S00_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARBURST\" *) input [1:0]S00_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE\" *) input [3:0]S00_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARID\" *) input [5:0]S00_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLEN\" *) input [7:0]S00_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK\" *) input [0:0]S00_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARPROT\" *) input [2:0]S00_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARQOS\" *) input [3:0]S00_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREADY\" *) output S00_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREGION\" *) input [3:0]S00_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE\" *) input [2:0]S00_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARVALID\" *) input S00_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWADDR\" *) input [63:0]S00_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWBURST\" *) input [1:0]S00_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE\" *) input [3:0]S00_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWID\" *) input [5:0]S00_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLEN\" *) input [7:0]S00_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK\" *) input [0:0]S00_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWPROT\" *) input [2:0]S00_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWQOS\" *) input [3:0]S00_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREADY\" *) output S00_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREGION\" *) input [3:0]S00_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE\" *) input [2:0]S00_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWVALID\" *) input S00_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BID\" *) output [5:0]S00_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BREADY\" *) input S00_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BRESP\" *) output [1:0]S00_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BVALID\" *) output S00_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RDATA\" *) output [511:0]S00_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RID\" *) output [5:0]S00_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RLAST\" *) output S00_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RREADY\" *) input S00_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RRESP\" *) output [1:0]S00_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RVALID\" *) output S00_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WDATA\" *) input [511:0]S00_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WLAST\" *) input S00_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WREADY\" *) output S00_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WSTRB\" *) input [63:0]S00_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WVALID\" *) input S00_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S01_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 6, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 32, NUM_READ_THREADS 16, NUM_WRITE_OUTSTANDING 32, NUM_WRITE_THREADS 16, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) input [63:0]S01_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARBURST\" *) input [1:0]S01_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE\" *) input [3:0]S01_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARID\" *) input [5:0]S01_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARLEN\" *) input [7:0]S01_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK\" *) input [0:0]S01_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARPROT\" *) input [2:0]S01_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARQOS\" *) input [3:0]S01_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARREADY\" *) output S01_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARREGION\" *) input [3:0]S01_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE\" *) input [2:0]S01_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARVALID\" *) input S01_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWADDR\" *) input [63:0]S01_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWBURST\" *) input [1:0]S01_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE\" *) input [3:0]S01_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWID\" *) input [5:0]S01_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWLEN\" *) input [7:0]S01_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK\" *) input [0:0]S01_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWPROT\" *) input [2:0]S01_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWQOS\" *) input [3:0]S01_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWREADY\" *) output S01_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWREGION\" *) input [3:0]S01_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE\" *) input [2:0]S01_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWVALID\" *) input S01_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BID\" *) output [5:0]S01_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BREADY\" *) input S01_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BRESP\" *) output [1:0]S01_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BVALID\" *) output S01_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RDATA\" *) output [511:0]S01_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RID\" *) output [5:0]S01_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RLAST\" *) output S01_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RREADY\" *) input S01_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RRESP\" *) output [1:0]S01_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RVALID\" *) output S01_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WDATA\" *) input [511:0]S01_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WLAST\" *) input S01_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WREADY\" *) output S01_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WSTRB\" *) input [63:0]S01_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WVALID\" *) input S01_AXI_wvalid;\n\n  wire ACLK_1;\n  wire ARESETN_1;\n  wire [63:0]S00_AXI_1_ARADDR;\n  wire [1:0]S00_AXI_1_ARBURST;\n  wire [3:0]S00_AXI_1_ARCACHE;\n  wire [5:0]S00_AXI_1_ARID;\n  wire [7:0]S00_AXI_1_ARLEN;\n  wire [0:0]S00_AXI_1_ARLOCK;\n  wire [2:0]S00_AXI_1_ARPROT;\n  wire [3:0]S00_AXI_1_ARQOS;\n  wire S00_AXI_1_ARREADY;\n  wire [3:0]S00_AXI_1_ARREGION;\n  wire [2:0]S00_AXI_1_ARSIZE;\n  wire S00_AXI_1_ARVALID;\n  wire [63:0]S00_AXI_1_AWADDR;\n  wire [1:0]S00_AXI_1_AWBURST;\n  wire [3:0]S00_AXI_1_AWCACHE;\n  wire [5:0]S00_AXI_1_AWID;\n  wire [7:0]S00_AXI_1_AWLEN;\n  wire [0:0]S00_AXI_1_AWLOCK;\n  wire [2:0]S00_AXI_1_AWPROT;\n  wire [3:0]S00_AXI_1_AWQOS;\n  wire S00_AXI_1_AWREADY;\n  wire [3:0]S00_AXI_1_AWREGION;\n  wire [2:0]S00_AXI_1_AWSIZE;\n  wire S00_AXI_1_AWVALID;\n  wire [5:0]S00_AXI_1_BID;\n  wire S00_AXI_1_BREADY;\n  wire [1:0]S00_AXI_1_BRESP;\n  wire S00_AXI_1_BVALID;\n  wire [511:0]S00_AXI_1_RDATA;\n  wire [5:0]S00_AXI_1_RID;\n  wire S00_AXI_1_RLAST;\n  wire S00_AXI_1_RREADY;\n  wire [1:0]S00_AXI_1_RRESP;\n  wire S00_AXI_1_RVALID;\n  wire [511:0]S00_AXI_1_WDATA;\n  wire S00_AXI_1_WLAST;\n  wire S00_AXI_1_WREADY;\n  wire [63:0]S00_AXI_1_WSTRB;\n  wire S00_AXI_1_WVALID;\n  wire [63:0]S01_AXI_1_ARADDR;\n  wire [1:0]S01_AXI_1_ARBURST;\n  wire [3:0]S01_AXI_1_ARCACHE;\n  wire [5:0]S01_AXI_1_ARID;\n  wire [7:0]S01_AXI_1_ARLEN;\n  wire [0:0]S01_AXI_1_ARLOCK;\n  wire [2:0]S01_AXI_1_ARPROT;\n  wire [3:0]S01_AXI_1_ARQOS;\n  wire S01_AXI_1_ARREADY;\n  wire [3:0]S01_AXI_1_ARREGION;\n  wire [2:0]S01_AXI_1_ARSIZE;\n  wire S01_AXI_1_ARVALID;\n  wire [63:0]S01_AXI_1_AWADDR;\n  wire [1:0]S01_AXI_1_AWBURST;\n  wire [3:0]S01_AXI_1_AWCACHE;\n  wire [5:0]S01_AXI_1_AWID;\n  wire [7:0]S01_AXI_1_AWLEN;\n  wire [0:0]S01_AXI_1_AWLOCK;\n  wire [2:0]S01_AXI_1_AWPROT;\n  wire [3:0]S01_AXI_1_AWQOS;\n  wire S01_AXI_1_AWREADY;\n  wire [3:0]S01_AXI_1_AWREGION;\n  wire [2:0]S01_AXI_1_AWSIZE;\n  wire S01_AXI_1_AWVALID;\n  wire [5:0]S01_AXI_1_BID;\n  wire S01_AXI_1_BREADY;\n  wire [1:0]S01_AXI_1_BRESP;\n  wire S01_AXI_1_BVALID;\n  wire [511:0]S01_AXI_1_RDATA;\n  wire [5:0]S01_AXI_1_RID;\n  wire S01_AXI_1_RLAST;\n  wire S01_AXI_1_RREADY;\n  wire [1:0]S01_AXI_1_RRESP;\n  wire S01_AXI_1_RVALID;\n  wire [511:0]S01_AXI_1_WDATA;\n  wire S01_AXI_1_WLAST;\n  wire S01_AXI_1_WREADY;\n  wire [63:0]S01_AXI_1_WSTRB;\n  wire S01_AXI_1_WVALID;\n  wire [63:0]axi_interconnect_0_M00_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M00_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M00_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M00_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M00_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M00_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARQOS;\n  wire axi_interconnect_0_M00_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M00_AXI_ARSIZE;\n  wire axi_interconnect_0_M00_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M00_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M00_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M00_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M00_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M00_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M00_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWQOS;\n  wire axi_interconnect_0_M00_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M00_AXI_AWSIZE;\n  wire axi_interconnect_0_M00_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M00_AXI_BID;\n  wire axi_interconnect_0_M00_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M00_AXI_BRESP;\n  wire axi_interconnect_0_M00_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M00_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M00_AXI_RID;\n  wire axi_interconnect_0_M00_AXI_RLAST;\n  wire axi_interconnect_0_M00_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M00_AXI_RRESP;\n  wire axi_interconnect_0_M00_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M00_AXI_WDATA;\n  wire axi_interconnect_0_M00_AXI_WLAST;\n  wire axi_interconnect_0_M00_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M00_AXI_WSTRB;\n  wire axi_interconnect_0_M00_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M01_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M01_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M01_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M01_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M01_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M01_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARQOS;\n  wire axi_interconnect_0_M01_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M01_AXI_ARSIZE;\n  wire axi_interconnect_0_M01_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M01_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M01_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M01_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M01_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M01_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M01_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWQOS;\n  wire axi_interconnect_0_M01_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M01_AXI_AWSIZE;\n  wire axi_interconnect_0_M01_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M01_AXI_BID;\n  wire axi_interconnect_0_M01_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M01_AXI_BRESP;\n  wire axi_interconnect_0_M01_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M01_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M01_AXI_RID;\n  wire axi_interconnect_0_M01_AXI_RLAST;\n  wire axi_interconnect_0_M01_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M01_AXI_RRESP;\n  wire axi_interconnect_0_M01_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M01_AXI_WDATA;\n  wire axi_interconnect_0_M01_AXI_WLAST;\n  wire axi_interconnect_0_M01_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M01_AXI_WSTRB;\n  wire axi_interconnect_0_M01_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M02_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M02_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M02_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M02_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M02_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M02_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARQOS;\n  wire axi_interconnect_0_M02_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M02_AXI_ARSIZE;\n  wire axi_interconnect_0_M02_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M02_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M02_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M02_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M02_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M02_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M02_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWQOS;\n  wire axi_interconnect_0_M02_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M02_AXI_AWSIZE;\n  wire axi_interconnect_0_M02_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M02_AXI_BID;\n  wire axi_interconnect_0_M02_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M02_AXI_BRESP;\n  wire axi_interconnect_0_M02_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M02_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M02_AXI_RID;\n  wire axi_interconnect_0_M02_AXI_RLAST;\n  wire axi_interconnect_0_M02_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M02_AXI_RRESP;\n  wire axi_interconnect_0_M02_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M02_AXI_WDATA;\n  wire axi_interconnect_0_M02_AXI_WLAST;\n  wire axi_interconnect_0_M02_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M02_AXI_WSTRB;\n  wire axi_interconnect_0_M02_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M03_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M03_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M03_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M03_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M03_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M03_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARQOS;\n  wire axi_interconnect_0_M03_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M03_AXI_ARSIZE;\n  wire axi_interconnect_0_M03_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M03_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M03_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M03_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M03_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M03_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M03_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWQOS;\n  wire axi_interconnect_0_M03_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M03_AXI_AWSIZE;\n  wire axi_interconnect_0_M03_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M03_AXI_BID;\n  wire axi_interconnect_0_M03_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M03_AXI_BRESP;\n  wire axi_interconnect_0_M03_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M03_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M03_AXI_RID;\n  wire axi_interconnect_0_M03_AXI_RLAST;\n  wire axi_interconnect_0_M03_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M03_AXI_RRESP;\n  wire axi_interconnect_0_M03_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M03_AXI_WDATA;\n  wire axi_interconnect_0_M03_AXI_WLAST;\n  wire axi_interconnect_0_M03_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M03_AXI_WSTRB;\n  wire axi_interconnect_0_M03_AXI_WVALID;\n\n  assign ACLK_1 = ACLK;\n  assign ARESETN_1 = ARESETN;\n  assign M00_AXI_araddr[63:0] = axi_interconnect_0_M00_AXI_ARADDR;\n  assign M00_AXI_arburst[1:0] = axi_interconnect_0_M00_AXI_ARBURST;\n  assign M00_AXI_arcache[3:0] = axi_interconnect_0_M00_AXI_ARCACHE;\n  assign M00_AXI_arid[6:0] = axi_interconnect_0_M00_AXI_ARID;\n  assign M00_AXI_arlen[7:0] = axi_interconnect_0_M00_AXI_ARLEN;\n  assign M00_AXI_arlock[0] = axi_interconnect_0_M00_AXI_ARLOCK;\n  assign M00_AXI_arprot[2:0] = axi_interconnect_0_M00_AXI_ARPROT;\n  assign M00_AXI_arqos[3:0] = axi_interconnect_0_M00_AXI_ARQOS;\n  assign M00_AXI_arregion[3:0] = axi_interconnect_0_M00_AXI_ARREGION;\n  assign M00_AXI_arsize[2:0] = axi_interconnect_0_M00_AXI_ARSIZE;\n  assign M00_AXI_arvalid = axi_interconnect_0_M00_AXI_ARVALID;\n  assign M00_AXI_awaddr[63:0] = axi_interconnect_0_M00_AXI_AWADDR;\n  assign M00_AXI_awburst[1:0] = axi_interconnect_0_M00_AXI_AWBURST;\n  assign M00_AXI_awcache[3:0] = axi_interconnect_0_M00_AXI_AWCACHE;\n  assign M00_AXI_awid[6:0] = axi_interconnect_0_M00_AXI_AWID;\n  assign M00_AXI_awlen[7:0] = axi_interconnect_0_M00_AXI_AWLEN;\n  assign M00_AXI_awlock[0] = axi_interconnect_0_M00_AXI_AWLOCK;\n  assign M00_AXI_awprot[2:0] = axi_interconnect_0_M00_AXI_AWPROT;\n  assign M00_AXI_awqos[3:0] = axi_interconnect_0_M00_AXI_AWQOS;\n  assign M00_AXI_awregion[3:0] = axi_interconnect_0_M00_AXI_AWREGION;\n  assign M00_AXI_awsize[2:0] = axi_interconnect_0_M00_AXI_AWSIZE;\n  assign M00_AXI_awvalid = axi_interconnect_0_M00_AXI_AWVALID;\n  assign M00_AXI_bready = axi_interconnect_0_M00_AXI_BREADY;\n  assign M00_AXI_rready = axi_interconnect_0_M00_AXI_RREADY;\n  assign M00_AXI_wdata[511:0] = axi_interconnect_0_M00_AXI_WDATA;\n  assign M00_AXI_wlast = axi_interconnect_0_M00_AXI_WLAST;\n  assign M00_AXI_wstrb[63:0] = axi_interconnect_0_M00_AXI_WSTRB;\n  assign M00_AXI_wvalid = axi_interconnect_0_M00_AXI_WVALID;\n  assign M01_AXI_araddr[63:0] = axi_interconnect_0_M01_AXI_ARADDR;\n  assign M01_AXI_arburst[1:0] = axi_interconnect_0_M01_AXI_ARBURST;\n  assign M01_AXI_arcache[3:0] = axi_interconnect_0_M01_AXI_ARCACHE;\n  assign M01_AXI_arid[6:0] = axi_interconnect_0_M01_AXI_ARID;\n  assign M01_AXI_arlen[7:0] = axi_interconnect_0_M01_AXI_ARLEN;\n  assign M01_AXI_arlock[0] = axi_interconnect_0_M01_AXI_ARLOCK;\n  assign M01_AXI_arprot[2:0] = axi_interconnect_0_M01_AXI_ARPROT;\n  assign M01_AXI_arqos[3:0] = axi_interconnect_0_M01_AXI_ARQOS;\n  assign M01_AXI_arregion[3:0] = axi_interconnect_0_M01_AXI_ARREGION;\n  assign M01_AXI_arsize[2:0] = axi_interconnect_0_M01_AXI_ARSIZE;\n  assign M01_AXI_arvalid = axi_interconnect_0_M01_AXI_ARVALID;\n  assign M01_AXI_awaddr[63:0] = axi_interconnect_0_M01_AXI_AWADDR;\n  assign M01_AXI_awburst[1:0] = axi_interconnect_0_M01_AXI_AWBURST;\n  assign M01_AXI_awcache[3:0] = axi_interconnect_0_M01_AXI_AWCACHE;\n  assign M01_AXI_awid[6:0] = axi_interconnect_0_M01_AXI_AWID;\n  assign M01_AXI_awlen[7:0] = axi_interconnect_0_M01_AXI_AWLEN;\n  assign M01_AXI_awlock[0] = axi_interconnect_0_M01_AXI_AWLOCK;\n  assign M01_AXI_awprot[2:0] = axi_interconnect_0_M01_AXI_AWPROT;\n  assign M01_AXI_awqos[3:0] = axi_interconnect_0_M01_AXI_AWQOS;\n  assign M01_AXI_awregion[3:0] = axi_interconnect_0_M01_AXI_AWREGION;\n  assign M01_AXI_awsize[2:0] = axi_interconnect_0_M01_AXI_AWSIZE;\n  assign M01_AXI_awvalid = axi_interconnect_0_M01_AXI_AWVALID;\n  assign M01_AXI_bready = axi_interconnect_0_M01_AXI_BREADY;\n  assign M01_AXI_rready = axi_interconnect_0_M01_AXI_RREADY;\n  assign M01_AXI_wdata[511:0] = axi_interconnect_0_M01_AXI_WDATA;\n  assign M01_AXI_wlast = axi_interconnect_0_M01_AXI_WLAST;\n  assign M01_AXI_wstrb[63:0] = axi_interconnect_0_M01_AXI_WSTRB;\n  assign M01_AXI_wvalid = axi_interconnect_0_M01_AXI_WVALID;\n  assign M02_AXI_araddr[63:0] = axi_interconnect_0_M02_AXI_ARADDR;\n  assign M02_AXI_arburst[1:0] = axi_interconnect_0_M02_AXI_ARBURST;\n  assign M02_AXI_arcache[3:0] = axi_interconnect_0_M02_AXI_ARCACHE;\n  assign M02_AXI_arid[6:0] = axi_interconnect_0_M02_AXI_ARID;\n  assign M02_AXI_arlen[7:0] = axi_interconnect_0_M02_AXI_ARLEN;\n  assign M02_AXI_arlock[0] = axi_interconnect_0_M02_AXI_ARLOCK;\n  assign M02_AXI_arprot[2:0] = axi_interconnect_0_M02_AXI_ARPROT;\n  assign M02_AXI_arqos[3:0] = axi_interconnect_0_M02_AXI_ARQOS;\n  assign M02_AXI_arregion[3:0] = axi_interconnect_0_M02_AXI_ARREGION;\n  assign M02_AXI_arsize[2:0] = axi_interconnect_0_M02_AXI_ARSIZE;\n  assign M02_AXI_arvalid = axi_interconnect_0_M02_AXI_ARVALID;\n  assign M02_AXI_awaddr[63:0] = axi_interconnect_0_M02_AXI_AWADDR;\n  assign M02_AXI_awburst[1:0] = axi_interconnect_0_M02_AXI_AWBURST;\n  assign M02_AXI_awcache[3:0] = axi_interconnect_0_M02_AXI_AWCACHE;\n  assign M02_AXI_awid[6:0] = axi_interconnect_0_M02_AXI_AWID;\n  assign M02_AXI_awlen[7:0] = axi_interconnect_0_M02_AXI_AWLEN;\n  assign M02_AXI_awlock[0] = axi_interconnect_0_M02_AXI_AWLOCK;\n  assign M02_AXI_awprot[2:0] = axi_interconnect_0_M02_AXI_AWPROT;\n  assign M02_AXI_awqos[3:0] = axi_interconnect_0_M02_AXI_AWQOS;\n  assign M02_AXI_awregion[3:0] = axi_interconnect_0_M02_AXI_AWREGION;\n  assign M02_AXI_awsize[2:0] = axi_interconnect_0_M02_AXI_AWSIZE;\n  assign M02_AXI_awvalid = axi_interconnect_0_M02_AXI_AWVALID;\n  assign M02_AXI_bready = axi_interconnect_0_M02_AXI_BREADY;\n  assign M02_AXI_rready = axi_interconnect_0_M02_AXI_RREADY;\n  assign M02_AXI_wdata[511:0] = axi_interconnect_0_M02_AXI_WDATA;\n  assign M02_AXI_wlast = axi_interconnect_0_M02_AXI_WLAST;\n  assign M02_AXI_wstrb[63:0] = axi_interconnect_0_M02_AXI_WSTRB;\n  assign M02_AXI_wvalid = axi_interconnect_0_M02_AXI_WVALID;\n  assign M03_AXI_araddr[63:0] = axi_interconnect_0_M03_AXI_ARADDR;\n  assign M03_AXI_arburst[1:0] = axi_interconnect_0_M03_AXI_ARBURST;\n  assign M03_AXI_arcache[3:0] = axi_interconnect_0_M03_AXI_ARCACHE;\n  assign M03_AXI_arid[6:0] = axi_interconnect_0_M03_AXI_ARID;\n  assign M03_AXI_arlen[7:0] = axi_interconnect_0_M03_AXI_ARLEN;\n  assign M03_AXI_arlock[0] = axi_interconnect_0_M03_AXI_ARLOCK;\n  assign M03_AXI_arprot[2:0] = axi_interconnect_0_M03_AXI_ARPROT;\n  assign M03_AXI_arqos[3:0] = axi_interconnect_0_M03_AXI_ARQOS;\n  assign M03_AXI_arregion[3:0] = axi_interconnect_0_M03_AXI_ARREGION;\n  assign M03_AXI_arsize[2:0] = axi_interconnect_0_M03_AXI_ARSIZE;\n  assign M03_AXI_arvalid = axi_interconnect_0_M03_AXI_ARVALID;\n  assign M03_AXI_awaddr[63:0] = axi_interconnect_0_M03_AXI_AWADDR;\n  assign M03_AXI_awburst[1:0] = axi_interconnect_0_M03_AXI_AWBURST;\n  assign M03_AXI_awcache[3:0] = axi_interconnect_0_M03_AXI_AWCACHE;\n  assign M03_AXI_awid[6:0] = axi_interconnect_0_M03_AXI_AWID;\n  assign M03_AXI_awlen[7:0] = axi_interconnect_0_M03_AXI_AWLEN;\n  assign M03_AXI_awlock[0] = axi_interconnect_0_M03_AXI_AWLOCK;\n  assign M03_AXI_awprot[2:0] = axi_interconnect_0_M03_AXI_AWPROT;\n  assign M03_AXI_awqos[3:0] = axi_interconnect_0_M03_AXI_AWQOS;\n  assign M03_AXI_awregion[3:0] = axi_interconnect_0_M03_AXI_AWREGION;\n  assign M03_AXI_awsize[2:0] = axi_interconnect_0_M03_AXI_AWSIZE;\n  assign M03_AXI_awvalid = axi_interconnect_0_M03_AXI_AWVALID;\n  assign M03_AXI_bready = axi_interconnect_0_M03_AXI_BREADY;\n  assign M03_AXI_rready = axi_interconnect_0_M03_AXI_RREADY;\n  assign M03_AXI_wdata[511:0] = axi_interconnect_0_M03_AXI_WDATA;\n  assign M03_AXI_wlast = axi_interconnect_0_M03_AXI_WLAST;\n  assign M03_AXI_wstrb[63:0] = axi_interconnect_0_M03_AXI_WSTRB;\n  assign M03_AXI_wvalid = axi_interconnect_0_M03_AXI_WVALID;\n  assign S00_AXI_1_ARADDR = S00_AXI_araddr[63:0];\n  assign S00_AXI_1_ARBURST = S00_AXI_arburst[1:0];\n  assign S00_AXI_1_ARCACHE = S00_AXI_arcache[3:0];\n  assign S00_AXI_1_ARID = S00_AXI_arid[5:0];\n  assign S00_AXI_1_ARLEN = S00_AXI_arlen[7:0];\n  assign S00_AXI_1_ARLOCK = S00_AXI_arlock[0];\n  assign S00_AXI_1_ARPROT = S00_AXI_arprot[2:0];\n  assign S00_AXI_1_ARQOS = S00_AXI_arqos[3:0];\n  assign S00_AXI_1_ARREGION = S00_AXI_arregion[3:0];\n  assign S00_AXI_1_ARSIZE = S00_AXI_arsize[2:0];\n  assign S00_AXI_1_ARVALID = S00_AXI_arvalid;\n  assign S00_AXI_1_AWADDR = S00_AXI_awaddr[63:0];\n  assign S00_AXI_1_AWBURST = S00_AXI_awburst[1:0];\n  assign S00_AXI_1_AWCACHE = S00_AXI_awcache[3:0];\n  assign S00_AXI_1_AWID = S00_AXI_awid[5:0];\n  assign S00_AXI_1_AWLEN = S00_AXI_awlen[7:0];\n  assign S00_AXI_1_AWLOCK = S00_AXI_awlock[0];\n  assign S00_AXI_1_AWPROT = S00_AXI_awprot[2:0];\n  assign S00_AXI_1_AWQOS = S00_AXI_awqos[3:0];\n  assign S00_AXI_1_AWREGION = S00_AXI_awregion[3:0];\n  assign S00_AXI_1_AWSIZE = S00_AXI_awsize[2:0];\n  assign S00_AXI_1_AWVALID = S00_AXI_awvalid;\n  assign S00_AXI_1_BREADY = S00_AXI_bready;\n  assign S00_AXI_1_RREADY = S00_AXI_rready;\n  assign S00_AXI_1_WDATA = S00_AXI_wdata[511:0];\n  assign S00_AXI_1_WLAST = S00_AXI_wlast;\n  assign S00_AXI_1_WSTRB = S00_AXI_wstrb[63:0];\n  assign S00_AXI_1_WVALID = S00_AXI_wvalid;\n  assign S00_AXI_arready = S00_AXI_1_ARREADY;\n  assign S00_AXI_awready = S00_AXI_1_AWREADY;\n  assign S00_AXI_bid[5:0] = S00_AXI_1_BID;\n  assign S00_AXI_bresp[1:0] = S00_AXI_1_BRESP;\n  assign S00_AXI_bvalid = S00_AXI_1_BVALID;\n  assign S00_AXI_rdata[511:0] = S00_AXI_1_RDATA;\n  assign S00_AXI_rid[5:0] = S00_AXI_1_RID;\n  assign S00_AXI_rlast = S00_AXI_1_RLAST;\n  assign S00_AXI_rresp[1:0] = S00_AXI_1_RRESP;\n  assign S00_AXI_rvalid = S00_AXI_1_RVALID;\n  assign S00_AXI_wready = S00_AXI_1_WREADY;\n  assign S01_AXI_1_ARADDR = S01_AXI_araddr[63:0];\n  assign S01_AXI_1_ARBURST = S01_AXI_arburst[1:0];\n  assign S01_AXI_1_ARCACHE = S01_AXI_arcache[3:0];\n  assign S01_AXI_1_ARID = S01_AXI_arid[5:0];\n  assign S01_AXI_1_ARLEN = S01_AXI_arlen[7:0];\n  assign S01_AXI_1_ARLOCK = S01_AXI_arlock[0];\n  assign S01_AXI_1_ARPROT = S01_AXI_arprot[2:0];\n  assign S01_AXI_1_ARQOS = S01_AXI_arqos[3:0];\n  assign S01_AXI_1_ARREGION = S01_AXI_arregion[3:0];\n  assign S01_AXI_1_ARSIZE = S01_AXI_arsize[2:0];\n  assign S01_AXI_1_ARVALID = S01_AXI_arvalid;\n  assign S01_AXI_1_AWADDR = S01_AXI_awaddr[63:0];\n  assign S01_AXI_1_AWBURST = S01_AXI_awburst[1:0];\n  assign S01_AXI_1_AWCACHE = S01_AXI_awcache[3:0];\n  assign S01_AXI_1_AWID = S01_AXI_awid[5:0];\n  assign S01_AXI_1_AWLEN = S01_AXI_awlen[7:0];\n  assign S01_AXI_1_AWLOCK = S01_AXI_awlock[0];\n  assign S01_AXI_1_AWPROT = S01_AXI_awprot[2:0];\n  assign S01_AXI_1_AWQOS = S01_AXI_awqos[3:0];\n  assign S01_AXI_1_AWREGION = S01_AXI_awregion[3:0];\n  assign S01_AXI_1_AWSIZE = S01_AXI_awsize[2:0];\n  assign S01_AXI_1_AWVALID = S01_AXI_awvalid;\n  assign S01_AXI_1_BREADY = S01_AXI_bready;\n  assign S01_AXI_1_RREADY = S01_AXI_rready;\n  assign S01_AXI_1_WDATA = S01_AXI_wdata[511:0];\n  assign S01_AXI_1_WLAST = S01_AXI_wlast;\n  assign S01_AXI_1_WSTRB = S01_AXI_wstrb[63:0];\n  assign S01_AXI_1_WVALID = S01_AXI_wvalid;\n  assign S01_AXI_arready = S01_AXI_1_ARREADY;\n  assign S01_AXI_awready = S01_AXI_1_AWREADY;\n  assign S01_AXI_bid[5:0] = S01_AXI_1_BID;\n  assign S01_AXI_bresp[1:0] = S01_AXI_1_BRESP;\n  assign S01_AXI_bvalid = S01_AXI_1_BVALID;\n  assign S01_AXI_rdata[511:0] = S01_AXI_1_RDATA;\n  assign S01_AXI_rid[5:0] = S01_AXI_1_RID;\n  assign S01_AXI_rlast = S01_AXI_1_RLAST;\n  assign S01_AXI_rresp[1:0] = S01_AXI_1_RRESP;\n  assign S01_AXI_rvalid = S01_AXI_1_RVALID;\n  assign S01_AXI_wready = S01_AXI_1_WREADY;\n  assign axi_interconnect_0_M00_AXI_ARREADY = M00_AXI_arready;\n  assign axi_interconnect_0_M00_AXI_AWREADY = M00_AXI_awready;\n  assign axi_interconnect_0_M00_AXI_BID = M00_AXI_bid[6:0];\n  assign axi_interconnect_0_M00_AXI_BRESP = M00_AXI_bresp[1:0];\n  assign axi_interconnect_0_M00_AXI_BVALID = M00_AXI_bvalid;\n  assign axi_interconnect_0_M00_AXI_RDATA = M00_AXI_rdata[511:0];\n  assign axi_interconnect_0_M00_AXI_RID = M00_AXI_rid[6:0];\n  assign axi_interconnect_0_M00_AXI_RLAST = M00_AXI_rlast;\n  assign axi_interconnect_0_M00_AXI_RRESP = M00_AXI_rresp[1:0];\n  assign axi_interconnect_0_M00_AXI_RVALID = M00_AXI_rvalid;\n  assign axi_interconnect_0_M00_AXI_WREADY = M00_AXI_wready;\n  assign axi_interconnect_0_M01_AXI_ARREADY = M01_AXI_arready;\n  assign axi_interconnect_0_M01_AXI_AWREADY = M01_AXI_awready;\n  assign axi_interconnect_0_M01_AXI_BID = M01_AXI_bid[6:0];\n  assign axi_interconnect_0_M01_AXI_BRESP = M01_AXI_bresp[1:0];\n  assign axi_interconnect_0_M01_AXI_BVALID = M01_AXI_bvalid;\n  assign axi_interconnect_0_M01_AXI_RDATA = M01_AXI_rdata[511:0];\n  assign axi_interconnect_0_M01_AXI_RID = M01_AXI_rid[6:0];\n  assign axi_interconnect_0_M01_AXI_RLAST = M01_AXI_rlast;\n  assign axi_interconnect_0_M01_AXI_RRESP = M01_AXI_rresp[1:0];\n  assign axi_interconnect_0_M01_AXI_RVALID = M01_AXI_rvalid;\n  assign axi_interconnect_0_M01_AXI_WREADY = M01_AXI_wready;\n  assign axi_interconnect_0_M02_AXI_ARREADY = M02_AXI_arready;\n  assign axi_interconnect_0_M02_AXI_AWREADY = M02_AXI_awready;\n  assign axi_interconnect_0_M02_AXI_BID = M02_AXI_bid[6:0];\n  assign axi_interconnect_0_M02_AXI_BRESP = M02_AXI_bresp[1:0];\n  assign axi_interconnect_0_M02_AXI_BVALID = M02_AXI_bvalid;\n  assign axi_interconnect_0_M02_AXI_RDATA = M02_AXI_rdata[511:0];\n  assign axi_interconnect_0_M02_AXI_RID = M02_AXI_rid[6:0];\n  assign axi_interconnect_0_M02_AXI_RLAST = M02_AXI_rlast;\n  assign axi_interconnect_0_M02_AXI_RRESP = M02_AXI_rresp[1:0];\n  assign axi_interconnect_0_M02_AXI_RVALID = M02_AXI_rvalid;\n  assign axi_interconnect_0_M02_AXI_WREADY = M02_AXI_wready;\n  assign axi_interconnect_0_M03_AXI_ARREADY = M03_AXI_arready;\n  assign axi_interconnect_0_M03_AXI_AWREADY = M03_AXI_awready;\n  assign axi_interconnect_0_M03_AXI_BID = M03_AXI_bid[6:0];\n  assign axi_interconnect_0_M03_AXI_BRESP = M03_AXI_bresp[1:0];\n  assign axi_interconnect_0_M03_AXI_BVALID = M03_AXI_bvalid;\n  assign axi_interconnect_0_M03_AXI_RDATA = M03_AXI_rdata[511:0];\n  assign axi_interconnect_0_M03_AXI_RID = M03_AXI_rid[6:0];\n  assign axi_interconnect_0_M03_AXI_RLAST = M03_AXI_rlast;\n  assign axi_interconnect_0_M03_AXI_RRESP = M03_AXI_rresp[1:0];\n  assign axi_interconnect_0_M03_AXI_RVALID = M03_AXI_rvalid;\n  assign axi_interconnect_0_M03_AXI_WREADY = M03_AXI_wready;\n  cl_axi_interconnect_axi_interconnect_0_0 axi_interconnect_0\n       (.ACLK(ACLK_1),\n        .ARESETN(ARESETN_1),\n        .M00_ACLK(ACLK_1),\n        .M00_ARESETN(ARESETN_1),\n        .M00_AXI_araddr(axi_interconnect_0_M00_AXI_ARADDR),\n        .M00_AXI_arburst(axi_interconnect_0_M00_AXI_ARBURST),\n        .M00_AXI_arcache(axi_interconnect_0_M00_AXI_ARCACHE),\n        .M00_AXI_arid(axi_interconnect_0_M00_AXI_ARID),\n        .M00_AXI_arlen(axi_interconnect_0_M00_AXI_ARLEN),\n        .M00_AXI_arlock(axi_interconnect_0_M00_AXI_ARLOCK),\n        .M00_AXI_arprot(axi_interconnect_0_M00_AXI_ARPROT),\n        .M00_AXI_arqos(axi_interconnect_0_M00_AXI_ARQOS),\n        .M00_AXI_arready(axi_interconnect_0_M00_AXI_ARREADY),\n        .M00_AXI_arregion(axi_interconnect_0_M00_AXI_ARREGION),\n        .M00_AXI_arsize(axi_interconnect_0_M00_AXI_ARSIZE),\n        .M00_AXI_arvalid(axi_interconnect_0_M00_AXI_ARVALID),\n        .M00_AXI_awaddr(axi_interconnect_0_M00_AXI_AWADDR),\n        .M00_AXI_awburst(axi_interconnect_0_M00_AXI_AWBURST),\n        .M00_AXI_awcache(axi_interconnect_0_M00_AXI_AWCACHE),\n        .M00_AXI_awid(axi_interconnect_0_M00_AXI_AWID),\n        .M00_AXI_awlen(axi_interconnect_0_M00_AXI_AWLEN),\n        .M00_AXI_awlock(axi_interconnect_0_M00_AXI_AWLOCK),\n        .M00_AXI_awprot(axi_interconnect_0_M00_AXI_AWPROT),\n        .M00_AXI_awqos(axi_interconnect_0_M00_AXI_AWQOS),\n        .M00_AXI_awready(axi_interconnect_0_M00_AXI_AWREADY),\n        .M00_AXI_awregion(axi_interconnect_0_M00_AXI_AWREGION),\n        .M00_AXI_awsize(axi_interconnect_0_M00_AXI_AWSIZE),\n        .M00_AXI_awvalid(axi_interconnect_0_M00_AXI_AWVALID),\n        .M00_AXI_bid(axi_interconnect_0_M00_AXI_BID),\n        .M00_AXI_bready(axi_interconnect_0_M00_AXI_BREADY),\n        .M00_AXI_bresp(axi_interconnect_0_M00_AXI_BRESP),\n        .M00_AXI_bvalid(axi_interconnect_0_M00_AXI_BVALID),\n        .M00_AXI_rdata(axi_interconnect_0_M00_AXI_RDATA),\n        .M00_AXI_rid(axi_interconnect_0_M00_AXI_RID),\n        .M00_AXI_rlast(axi_interconnect_0_M00_AXI_RLAST),\n        .M00_AXI_rready(axi_interconnect_0_M00_AXI_RREADY),\n        .M00_AXI_rresp(axi_interconnect_0_M00_AXI_RRESP),\n        .M00_AXI_rvalid(axi_interconnect_0_M00_AXI_RVALID),\n        .M00_AXI_wdata(axi_interconnect_0_M00_AXI_WDATA),\n        .M00_AXI_wlast(axi_interconnect_0_M00_AXI_WLAST),\n        .M00_AXI_wready(axi_interconnect_0_M00_AXI_WREADY),\n        .M00_AXI_wstrb(axi_interconnect_0_M00_AXI_WSTRB),\n        .M00_AXI_wvalid(axi_interconnect_0_M00_AXI_WVALID),\n        .M01_ACLK(ACLK_1),\n        .M01_ARESETN(ARESETN_1),\n        .M01_AXI_araddr(axi_interconnect_0_M01_AXI_ARADDR),\n        .M01_AXI_arburst(axi_interconnect_0_M01_AXI_ARBURST),\n        .M01_AXI_arcache(axi_interconnect_0_M01_AXI_ARCACHE),\n        .M01_AXI_arid(axi_interconnect_0_M01_AXI_ARID),\n        .M01_AXI_arlen(axi_interconnect_0_M01_AXI_ARLEN),\n        .M01_AXI_arlock(axi_interconnect_0_M01_AXI_ARLOCK),\n        .M01_AXI_arprot(axi_interconnect_0_M01_AXI_ARPROT),\n        .M01_AXI_arqos(axi_interconnect_0_M01_AXI_ARQOS),\n        .M01_AXI_arready(axi_interconnect_0_M01_AXI_ARREADY),\n        .M01_AXI_arregion(axi_interconnect_0_M01_AXI_ARREGION),\n        .M01_AXI_arsize(axi_interconnect_0_M01_AXI_ARSIZE),\n        .M01_AXI_arvalid(axi_interconnect_0_M01_AXI_ARVALID),\n        .M01_AXI_awaddr(axi_interconnect_0_M01_AXI_AWADDR),\n        .M01_AXI_awburst(axi_interconnect_0_M01_AXI_AWBURST),\n        .M01_AXI_awcache(axi_interconnect_0_M01_AXI_AWCACHE),\n        .M01_AXI_awid(axi_interconnect_0_M01_AXI_AWID),\n        .M01_AXI_awlen(axi_interconnect_0_M01_AXI_AWLEN),\n        .M01_AXI_awlock(axi_interconnect_0_M01_AXI_AWLOCK),\n        .M01_AXI_awprot(axi_interconnect_0_M01_AXI_AWPROT),\n        .M01_AXI_awqos(axi_interconnect_0_M01_AXI_AWQOS),\n        .M01_AXI_awready(axi_interconnect_0_M01_AXI_AWREADY),\n        .M01_AXI_awregion(axi_interconnect_0_M01_AXI_AWREGION),\n        .M01_AXI_awsize(axi_interconnect_0_M01_AXI_AWSIZE),\n        .M01_AXI_awvalid(axi_interconnect_0_M01_AXI_AWVALID),\n        .M01_AXI_bid(axi_interconnect_0_M01_AXI_BID),\n        .M01_AXI_bready(axi_interconnect_0_M01_AXI_BREADY),\n        .M01_AXI_bresp(axi_interconnect_0_M01_AXI_BRESP),\n        .M01_AXI_bvalid(axi_interconnect_0_M01_AXI_BVALID),\n        .M01_AXI_rdata(axi_interconnect_0_M01_AXI_RDATA),\n        .M01_AXI_rid(axi_interconnect_0_M01_AXI_RID),\n        .M01_AXI_rlast(axi_interconnect_0_M01_AXI_RLAST),\n        .M01_AXI_rready(axi_interconnect_0_M01_AXI_RREADY),\n        .M01_AXI_rresp(axi_interconnect_0_M01_AXI_RRESP),\n        .M01_AXI_rvalid(axi_interconnect_0_M01_AXI_RVALID),\n        .M01_AXI_wdata(axi_interconnect_0_M01_AXI_WDATA),\n        .M01_AXI_wlast(axi_interconnect_0_M01_AXI_WLAST),\n        .M01_AXI_wready(axi_interconnect_0_M01_AXI_WREADY),\n        .M01_AXI_wstrb(axi_interconnect_0_M01_AXI_WSTRB),\n        .M01_AXI_wvalid(axi_interconnect_0_M01_AXI_WVALID),\n        .M02_ACLK(ACLK_1),\n        .M02_ARESETN(ARESETN_1),\n        .M02_AXI_araddr(axi_interconnect_0_M02_AXI_ARADDR),\n        .M02_AXI_arburst(axi_interconnect_0_M02_AXI_ARBURST),\n        .M02_AXI_arcache(axi_interconnect_0_M02_AXI_ARCACHE),\n        .M02_AXI_arid(axi_interconnect_0_M02_AXI_ARID),\n        .M02_AXI_arlen(axi_interconnect_0_M02_AXI_ARLEN),\n        .M02_AXI_arlock(axi_interconnect_0_M02_AXI_ARLOCK),\n        .M02_AXI_arprot(axi_interconnect_0_M02_AXI_ARPROT),\n        .M02_AXI_arqos(axi_interconnect_0_M02_AXI_ARQOS),\n        .M02_AXI_arready(axi_interconnect_0_M02_AXI_ARREADY),\n        .M02_AXI_arregion(axi_interconnect_0_M02_AXI_ARREGION),\n        .M02_AXI_arsize(axi_interconnect_0_M02_AXI_ARSIZE),\n        .M02_AXI_arvalid(axi_interconnect_0_M02_AXI_ARVALID),\n        .M02_AXI_awaddr(axi_interconnect_0_M02_AXI_AWADDR),\n        .M02_AXI_awburst(axi_interconnect_0_M02_AXI_AWBURST),\n        .M02_AXI_awcache(axi_interconnect_0_M02_AXI_AWCACHE),\n        .M02_AXI_awid(axi_interconnect_0_M02_AXI_AWID),\n        .M02_AXI_awlen(axi_interconnect_0_M02_AXI_AWLEN),\n        .M02_AXI_awlock(axi_interconnect_0_M02_AXI_AWLOCK),\n        .M02_AXI_awprot(axi_interconnect_0_M02_AXI_AWPROT),\n        .M02_AXI_awqos(axi_interconnect_0_M02_AXI_AWQOS),\n        .M02_AXI_awready(axi_interconnect_0_M02_AXI_AWREADY),\n        .M02_AXI_awregion(axi_interconnect_0_M02_AXI_AWREGION),\n        .M02_AXI_awsize(axi_interconnect_0_M02_AXI_AWSIZE),\n        .M02_AXI_awvalid(axi_interconnect_0_M02_AXI_AWVALID),\n        .M02_AXI_bid(axi_interconnect_0_M02_AXI_BID),\n        .M02_AXI_bready(axi_interconnect_0_M02_AXI_BREADY),\n        .M02_AXI_bresp(axi_interconnect_0_M02_AXI_BRESP),\n        .M02_AXI_bvalid(axi_interconnect_0_M02_AXI_BVALID),\n        .M02_AXI_rdata(axi_interconnect_0_M02_AXI_RDATA),\n        .M02_AXI_rid(axi_interconnect_0_M02_AXI_RID),\n        .M02_AXI_rlast(axi_interconnect_0_M02_AXI_RLAST),\n        .M02_AXI_rready(axi_interconnect_0_M02_AXI_RREADY),\n        .M02_AXI_rresp(axi_interconnect_0_M02_AXI_RRESP),\n        .M02_AXI_rvalid(axi_interconnect_0_M02_AXI_RVALID),\n        .M02_AXI_wdata(axi_interconnect_0_M02_AXI_WDATA),\n        .M02_AXI_wlast(axi_interconnect_0_M02_AXI_WLAST),\n        .M02_AXI_wready(axi_interconnect_0_M02_AXI_WREADY),\n        .M02_AXI_wstrb(axi_interconnect_0_M02_AXI_WSTRB),\n        .M02_AXI_wvalid(axi_interconnect_0_M02_AXI_WVALID),\n        .M03_ACLK(ACLK_1),\n        .M03_ARESETN(ARESETN_1),\n        .M03_AXI_araddr(axi_interconnect_0_M03_AXI_ARADDR),\n        .M03_AXI_arburst(axi_interconnect_0_M03_AXI_ARBURST),\n        .M03_AXI_arcache(axi_interconnect_0_M03_AXI_ARCACHE),\n        .M03_AXI_arid(axi_interconnect_0_M03_AXI_ARID),\n        .M03_AXI_arlen(axi_interconnect_0_M03_AXI_ARLEN),\n        .M03_AXI_arlock(axi_interconnect_0_M03_AXI_ARLOCK),\n        .M03_AXI_arprot(axi_interconnect_0_M03_AXI_ARPROT),\n        .M03_AXI_arqos(axi_interconnect_0_M03_AXI_ARQOS),\n        .M03_AXI_arready(axi_interconnect_0_M03_AXI_ARREADY),\n        .M03_AXI_arregion(axi_interconnect_0_M03_AXI_ARREGION),\n        .M03_AXI_arsize(axi_interconnect_0_M03_AXI_ARSIZE),\n        .M03_AXI_arvalid(axi_interconnect_0_M03_AXI_ARVALID),\n        .M03_AXI_awaddr(axi_interconnect_0_M03_AXI_AWADDR),\n        .M03_AXI_awburst(axi_interconnect_0_M03_AXI_AWBURST),\n        .M03_AXI_awcache(axi_interconnect_0_M03_AXI_AWCACHE),\n        .M03_AXI_awid(axi_interconnect_0_M03_AXI_AWID),\n        .M03_AXI_awlen(axi_interconnect_0_M03_AXI_AWLEN),\n        .M03_AXI_awlock(axi_interconnect_0_M03_AXI_AWLOCK),\n        .M03_AXI_awprot(axi_interconnect_0_M03_AXI_AWPROT),\n        .M03_AXI_awqos(axi_interconnect_0_M03_AXI_AWQOS),\n        .M03_AXI_awready(axi_interconnect_0_M03_AXI_AWREADY),\n        .M03_AXI_awregion(axi_interconnect_0_M03_AXI_AWREGION),\n        .M03_AXI_awsize(axi_interconnect_0_M03_AXI_AWSIZE),\n        .M03_AXI_awvalid(axi_interconnect_0_M03_AXI_AWVALID),\n        .M03_AXI_bid(axi_interconnect_0_M03_AXI_BID),\n        .M03_AXI_bready(axi_interconnect_0_M03_AXI_BREADY),\n        .M03_AXI_bresp(axi_interconnect_0_M03_AXI_BRESP),\n        .M03_AXI_bvalid(axi_interconnect_0_M03_AXI_BVALID),\n        .M03_AXI_rdata(axi_interconnect_0_M03_AXI_RDATA),\n        .M03_AXI_rid(axi_interconnect_0_M03_AXI_RID),\n        .M03_AXI_rlast(axi_interconnect_0_M03_AXI_RLAST),\n        .M03_AXI_rready(axi_interconnect_0_M03_AXI_RREADY),\n        .M03_AXI_rresp(axi_interconnect_0_M03_AXI_RRESP),\n        .M03_AXI_rvalid(axi_interconnect_0_M03_AXI_RVALID),\n        .M03_AXI_wdata(axi_interconnect_0_M03_AXI_WDATA),\n        .M03_AXI_wlast(axi_interconnect_0_M03_AXI_WLAST),\n        .M03_AXI_wready(axi_interconnect_0_M03_AXI_WREADY),\n        .M03_AXI_wstrb(axi_interconnect_0_M03_AXI_WSTRB),\n        .M03_AXI_wvalid(axi_interconnect_0_M03_AXI_WVALID),\n        .S00_ACLK(ACLK_1),\n        .S00_ARESETN(ARESETN_1),\n        .S00_AXI_araddr(S00_AXI_1_ARADDR),\n        .S00_AXI_arburst(S00_AXI_1_ARBURST),\n        .S00_AXI_arcache(S00_AXI_1_ARCACHE),\n        .S00_AXI_arid(S00_AXI_1_ARID),\n        .S00_AXI_arlen(S00_AXI_1_ARLEN),\n        .S00_AXI_arlock(S00_AXI_1_ARLOCK),\n        .S00_AXI_arprot(S00_AXI_1_ARPROT),\n        .S00_AXI_arqos(S00_AXI_1_ARQOS),\n        .S00_AXI_arready(S00_AXI_1_ARREADY),\n        .S00_AXI_arregion(S00_AXI_1_ARREGION),\n        .S00_AXI_arsize(S00_AXI_1_ARSIZE),\n        .S00_AXI_arvalid(S00_AXI_1_ARVALID),\n        .S00_AXI_awaddr(S00_AXI_1_AWADDR),\n        .S00_AXI_awburst(S00_AXI_1_AWBURST),\n        .S00_AXI_awcache(S00_AXI_1_AWCACHE),\n        .S00_AXI_awid(S00_AXI_1_AWID),\n        .S00_AXI_awlen(S00_AXI_1_AWLEN),\n        .S00_AXI_awlock(S00_AXI_1_AWLOCK),\n        .S00_AXI_awprot(S00_AXI_1_AWPROT),\n        .S00_AXI_awqos(S00_AXI_1_AWQOS),\n        .S00_AXI_awready(S00_AXI_1_AWREADY),\n        .S00_AXI_awregion(S00_AXI_1_AWREGION),\n        .S00_AXI_awsize(S00_AXI_1_AWSIZE),\n        .S00_AXI_awvalid(S00_AXI_1_AWVALID),\n        .S00_AXI_bid(S00_AXI_1_BID),\n        .S00_AXI_bready(S00_AXI_1_BREADY),\n        .S00_AXI_bresp(S00_AXI_1_BRESP),\n        .S00_AXI_bvalid(S00_AXI_1_BVALID),\n        .S00_AXI_rdata(S00_AXI_1_RDATA),\n        .S00_AXI_rid(S00_AXI_1_RID),\n        .S00_AXI_rlast(S00_AXI_1_RLAST),\n        .S00_AXI_rready(S00_AXI_1_RREADY),\n        .S00_AXI_rresp(S00_AXI_1_RRESP),\n        .S00_AXI_rvalid(S00_AXI_1_RVALID),\n        .S00_AXI_wdata(S00_AXI_1_WDATA),\n        .S00_AXI_wlast(S00_AXI_1_WLAST),\n        .S00_AXI_wready(S00_AXI_1_WREADY),\n        .S00_AXI_wstrb(S00_AXI_1_WSTRB),\n        .S00_AXI_wvalid(S00_AXI_1_WVALID),\n        .S01_ACLK(ACLK_1),\n        .S01_ARESETN(ARESETN_1),\n        .S01_AXI_araddr(S01_AXI_1_ARADDR),\n        .S01_AXI_arburst(S01_AXI_1_ARBURST),\n        .S01_AXI_arcache(S01_AXI_1_ARCACHE),\n        .S01_AXI_arid(S01_AXI_1_ARID),\n        .S01_AXI_arlen(S01_AXI_1_ARLEN),\n        .S01_AXI_arlock(S01_AXI_1_ARLOCK),\n        .S01_AXI_arprot(S01_AXI_1_ARPROT),\n        .S01_AXI_arqos(S01_AXI_1_ARQOS),\n        .S01_AXI_arready(S01_AXI_1_ARREADY),\n        .S01_AXI_arregion(S01_AXI_1_ARREGION),\n        .S01_AXI_arsize(S01_AXI_1_ARSIZE),\n        .S01_AXI_arvalid(S01_AXI_1_ARVALID),\n        .S01_AXI_awaddr(S01_AXI_1_AWADDR),\n        .S01_AXI_awburst(S01_AXI_1_AWBURST),\n        .S01_AXI_awcache(S01_AXI_1_AWCACHE),\n        .S01_AXI_awid(S01_AXI_1_AWID),\n        .S01_AXI_awlen(S01_AXI_1_AWLEN),\n        .S01_AXI_awlock(S01_AXI_1_AWLOCK),\n        .S01_AXI_awprot(S01_AXI_1_AWPROT),\n        .S01_AXI_awqos(S01_AXI_1_AWQOS),\n        .S01_AXI_awready(S01_AXI_1_AWREADY),\n        .S01_AXI_awregion(S01_AXI_1_AWREGION),\n        .S01_AXI_awsize(S01_AXI_1_AWSIZE),\n        .S01_AXI_awvalid(S01_AXI_1_AWVALID),\n        .S01_AXI_bid(S01_AXI_1_BID),\n        .S01_AXI_bready(S01_AXI_1_BREADY),\n        .S01_AXI_bresp(S01_AXI_1_BRESP),\n        .S01_AXI_bvalid(S01_AXI_1_BVALID),\n        .S01_AXI_rdata(S01_AXI_1_RDATA),\n        .S01_AXI_rid(S01_AXI_1_RID),\n        .S01_AXI_rlast(S01_AXI_1_RLAST),\n        .S01_AXI_rready(S01_AXI_1_RREADY),\n        .S01_AXI_rresp(S01_AXI_1_RRESP),\n        .S01_AXI_rvalid(S01_AXI_1_RVALID),\n        .S01_AXI_wdata(S01_AXI_1_WDATA),\n        .S01_AXI_wlast(S01_AXI_1_WLAST),\n        .S01_AXI_wready(S01_AXI_1_WREADY),\n        .S01_AXI_wstrb(S01_AXI_1_WSTRB),\n        .S01_AXI_wvalid(S01_AXI_1_WVALID));\nendmodule\n\nmodule cl_axi_interconnect_axi_interconnect_0_0\n   (ACLK,\n    ARESETN,\n    M00_ACLK,\n    M00_ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_ACLK,\n    M01_ARESETN,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_ACLK,\n    M02_ARESETN,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_ACLK,\n    M03_ARESETN,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_ACLK,\n    S00_ARESETN,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_ACLK,\n    S01_ARESETN,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  input ACLK;\n  input ARESETN;\n  input M00_ACLK;\n  input M00_ARESETN;\n  output [63:0]M00_AXI_araddr;\n  output [1:0]M00_AXI_arburst;\n  output [3:0]M00_AXI_arcache;\n  output [6:0]M00_AXI_arid;\n  output [7:0]M00_AXI_arlen;\n  output [0:0]M00_AXI_arlock;\n  output [2:0]M00_AXI_arprot;\n  output [3:0]M00_AXI_arqos;\n  input M00_AXI_arready;\n  output [3:0]M00_AXI_arregion;\n  output [2:0]M00_AXI_arsize;\n  output M00_AXI_arvalid;\n  output [63:0]M00_AXI_awaddr;\n  output [1:0]M00_AXI_awburst;\n  output [3:0]M00_AXI_awcache;\n  output [6:0]M00_AXI_awid;\n  output [7:0]M00_AXI_awlen;\n  output [0:0]M00_AXI_awlock;\n  output [2:0]M00_AXI_awprot;\n  output [3:0]M00_AXI_awqos;\n  input M00_AXI_awready;\n  output [3:0]M00_AXI_awregion;\n  output [2:0]M00_AXI_awsize;\n  output M00_AXI_awvalid;\n  input [6:0]M00_AXI_bid;\n  output M00_AXI_bready;\n  input [1:0]M00_AXI_bresp;\n  input M00_AXI_bvalid;\n  input [511:0]M00_AXI_rdata;\n  input [6:0]M00_AXI_rid;\n  input M00_AXI_rlast;\n  output M00_AXI_rready;\n  input [1:0]M00_AXI_rresp;\n  input M00_AXI_rvalid;\n  output [511:0]M00_AXI_wdata;\n  output M00_AXI_wlast;\n  input M00_AXI_wready;\n  output [63:0]M00_AXI_wstrb;\n  output M00_AXI_wvalid;\n  input M01_ACLK;\n  input M01_ARESETN;\n  output [63:0]M01_AXI_araddr;\n  output [1:0]M01_AXI_arburst;\n  output [3:0]M01_AXI_arcache;\n  output [6:0]M01_AXI_arid;\n  output [7:0]M01_AXI_arlen;\n  output [0:0]M01_AXI_arlock;\n  output [2:0]M01_AXI_arprot;\n  output [3:0]M01_AXI_arqos;\n  input M01_AXI_arready;\n  output [3:0]M01_AXI_arregion;\n  output [2:0]M01_AXI_arsize;\n  output M01_AXI_arvalid;\n  output [63:0]M01_AXI_awaddr;\n  output [1:0]M01_AXI_awburst;\n  output [3:0]M01_AXI_awcache;\n  output [6:0]M01_AXI_awid;\n  output [7:0]M01_AXI_awlen;\n  output [0:0]M01_AXI_awlock;\n  output [2:0]M01_AXI_awprot;\n  output [3:0]M01_AXI_awqos;\n  input M01_AXI_awready;\n  output [3:0]M01_AXI_awregion;\n  output [2:0]M01_AXI_awsize;\n  output M01_AXI_awvalid;\n  input [6:0]M01_AXI_bid;\n  output M01_AXI_bready;\n  input [1:0]M01_AXI_bresp;\n  input M01_AXI_bvalid;\n  input [511:0]M01_AXI_rdata;\n  input [6:0]M01_AXI_rid;\n  input M01_AXI_rlast;\n  output M01_AXI_rready;\n  input [1:0]M01_AXI_rresp;\n  input M01_AXI_rvalid;\n  output [511:0]M01_AXI_wdata;\n  output M01_AXI_wlast;\n  input M01_AXI_wready;\n  output [63:0]M01_AXI_wstrb;\n  output M01_AXI_wvalid;\n  input M02_ACLK;\n  input M02_ARESETN;\n  output [63:0]M02_AXI_araddr;\n  output [1:0]M02_AXI_arburst;\n  output [3:0]M02_AXI_arcache;\n  output [6:0]M02_AXI_arid;\n  output [7:0]M02_AXI_arlen;\n  output [0:0]M02_AXI_arlock;\n  output [2:0]M02_AXI_arprot;\n  output [3:0]M02_AXI_arqos;\n  input M02_AXI_arready;\n  output [3:0]M02_AXI_arregion;\n  output [2:0]M02_AXI_arsize;\n  output M02_AXI_arvalid;\n  output [63:0]M02_AXI_awaddr;\n  output [1:0]M02_AXI_awburst;\n  output [3:0]M02_AXI_awcache;\n  output [6:0]M02_AXI_awid;\n  output [7:0]M02_AXI_awlen;\n  output [0:0]M02_AXI_awlock;\n  output [2:0]M02_AXI_awprot;\n  output [3:0]M02_AXI_awqos;\n  input M02_AXI_awready;\n  output [3:0]M02_AXI_awregion;\n  output [2:0]M02_AXI_awsize;\n  output M02_AXI_awvalid;\n  input [6:0]M02_AXI_bid;\n  output M02_AXI_bready;\n  input [1:0]M02_AXI_bresp;\n  input M02_AXI_bvalid;\n  input [511:0]M02_AXI_rdata;\n  input [6:0]M02_AXI_rid;\n  input M02_AXI_rlast;\n  output M02_AXI_rready;\n  input [1:0]M02_AXI_rresp;\n  input M02_AXI_rvalid;\n  output [511:0]M02_AXI_wdata;\n  output M02_AXI_wlast;\n  input M02_AXI_wready;\n  output [63:0]M02_AXI_wstrb;\n  output M02_AXI_wvalid;\n  input M03_ACLK;\n  input M03_ARESETN;\n  output [63:0]M03_AXI_araddr;\n  output [1:0]M03_AXI_arburst;\n  output [3:0]M03_AXI_arcache;\n  output [6:0]M03_AXI_arid;\n  output [7:0]M03_AXI_arlen;\n  output [0:0]M03_AXI_arlock;\n  output [2:0]M03_AXI_arprot;\n  output [3:0]M03_AXI_arqos;\n  input M03_AXI_arready;\n  output [3:0]M03_AXI_arregion;\n  output [2:0]M03_AXI_arsize;\n  output M03_AXI_arvalid;\n  output [63:0]M03_AXI_awaddr;\n  output [1:0]M03_AXI_awburst;\n  output [3:0]M03_AXI_awcache;\n  output [6:0]M03_AXI_awid;\n  output [7:0]M03_AXI_awlen;\n  output [0:0]M03_AXI_awlock;\n  output [2:0]M03_AXI_awprot;\n  output [3:0]M03_AXI_awqos;\n  input M03_AXI_awready;\n  output [3:0]M03_AXI_awregion;\n  output [2:0]M03_AXI_awsize;\n  output M03_AXI_awvalid;\n  input [6:0]M03_AXI_bid;\n  output M03_AXI_bready;\n  input [1:0]M03_AXI_bresp;\n  input M03_AXI_bvalid;\n  input [511:0]M03_AXI_rdata;\n  input [6:0]M03_AXI_rid;\n  input M03_AXI_rlast;\n  output M03_AXI_rready;\n  input [1:0]M03_AXI_rresp;\n  input M03_AXI_rvalid;\n  output [511:0]M03_AXI_wdata;\n  output M03_AXI_wlast;\n  input M03_AXI_wready;\n  output [63:0]M03_AXI_wstrb;\n  output M03_AXI_wvalid;\n  input S00_ACLK;\n  input S00_ARESETN;\n  input [63:0]S00_AXI_araddr;\n  input [1:0]S00_AXI_arburst;\n  input [3:0]S00_AXI_arcache;\n  input [5:0]S00_AXI_arid;\n  input [7:0]S00_AXI_arlen;\n  input [0:0]S00_AXI_arlock;\n  input [2:0]S00_AXI_arprot;\n  input [3:0]S00_AXI_arqos;\n  output S00_AXI_arready;\n  input [3:0]S00_AXI_arregion;\n  input [2:0]S00_AXI_arsize;\n  input S00_AXI_arvalid;\n  input [63:0]S00_AXI_awaddr;\n  input [1:0]S00_AXI_awburst;\n  input [3:0]S00_AXI_awcache;\n  input [5:0]S00_AXI_awid;\n  input [7:0]S00_AXI_awlen;\n  input [0:0]S00_AXI_awlock;\n  input [2:0]S00_AXI_awprot;\n  input [3:0]S00_AXI_awqos;\n  output S00_AXI_awready;\n  input [3:0]S00_AXI_awregion;\n  input [2:0]S00_AXI_awsize;\n  input S00_AXI_awvalid;\n  output [5:0]S00_AXI_bid;\n  input S00_AXI_bready;\n  output [1:0]S00_AXI_bresp;\n  output S00_AXI_bvalid;\n  output [511:0]S00_AXI_rdata;\n  output [5:0]S00_AXI_rid;\n  output S00_AXI_rlast;\n  input S00_AXI_rready;\n  output [1:0]S00_AXI_rresp;\n  output S00_AXI_rvalid;\n  input [511:0]S00_AXI_wdata;\n  input S00_AXI_wlast;\n  output S00_AXI_wready;\n  input [63:0]S00_AXI_wstrb;\n  input S00_AXI_wvalid;\n  input S01_ACLK;\n  input S01_ARESETN;\n  input [63:0]S01_AXI_araddr;\n  input [1:0]S01_AXI_arburst;\n  input [3:0]S01_AXI_arcache;\n  input [5:0]S01_AXI_arid;\n  input [7:0]S01_AXI_arlen;\n  input [0:0]S01_AXI_arlock;\n  input [2:0]S01_AXI_arprot;\n  input [3:0]S01_AXI_arqos;\n  output S01_AXI_arready;\n  input [3:0]S01_AXI_arregion;\n  input [2:0]S01_AXI_arsize;\n  input S01_AXI_arvalid;\n  input [63:0]S01_AXI_awaddr;\n  input [1:0]S01_AXI_awburst;\n  input [3:0]S01_AXI_awcache;\n  input [5:0]S01_AXI_awid;\n  input [7:0]S01_AXI_awlen;\n  input [0:0]S01_AXI_awlock;\n  input [2:0]S01_AXI_awprot;\n  input [3:0]S01_AXI_awqos;\n  output S01_AXI_awready;\n  input [3:0]S01_AXI_awregion;\n  input [2:0]S01_AXI_awsize;\n  input S01_AXI_awvalid;\n  output [5:0]S01_AXI_bid;\n  input S01_AXI_bready;\n  output [1:0]S01_AXI_bresp;\n  output S01_AXI_bvalid;\n  output [511:0]S01_AXI_rdata;\n  output [5:0]S01_AXI_rid;\n  output S01_AXI_rlast;\n  input S01_AXI_rready;\n  output [1:0]S01_AXI_rresp;\n  output S01_AXI_rvalid;\n  input [511:0]S01_AXI_wdata;\n  input S01_AXI_wlast;\n  output S01_AXI_wready;\n  input [63:0]S01_AXI_wstrb;\n  input S01_AXI_wvalid;\n\n  wire axi_interconnect_0_ACLK_net;\n  wire axi_interconnect_0_ARESETN_net;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_ARADDR;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_ARBURST;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARCACHE;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_ARID;\n  wire [7:0]axi_interconnect_0_to_s00_couplers_ARLEN;\n  wire [0:0]axi_interconnect_0_to_s00_couplers_ARLOCK;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_ARPROT;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARQOS;\n  wire axi_interconnect_0_to_s00_couplers_ARREADY;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARREGION;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_ARSIZE;\n  wire axi_interconnect_0_to_s00_couplers_ARVALID;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_AWADDR;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_AWBURST;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWCACHE;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_AWID;\n  wire [7:0]axi_interconnect_0_to_s00_couplers_AWLEN;\n  wire [0:0]axi_interconnect_0_to_s00_couplers_AWLOCK;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_AWPROT;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWQOS;\n  wire axi_interconnect_0_to_s00_couplers_AWREADY;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWREGION;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_AWSIZE;\n  wire axi_interconnect_0_to_s00_couplers_AWVALID;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_BID;\n  wire axi_interconnect_0_to_s00_couplers_BREADY;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_BRESP;\n  wire axi_interconnect_0_to_s00_couplers_BVALID;\n  wire [511:0]axi_interconnect_0_to_s00_couplers_RDATA;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_RID;\n  wire axi_interconnect_0_to_s00_couplers_RLAST;\n  wire axi_interconnect_0_to_s00_couplers_RREADY;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_RRESP;\n  wire axi_interconnect_0_to_s00_couplers_RVALID;\n  wire [511:0]axi_interconnect_0_to_s00_couplers_WDATA;\n  wire axi_interconnect_0_to_s00_couplers_WLAST;\n  wire axi_interconnect_0_to_s00_couplers_WREADY;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_WSTRB;\n  wire axi_interconnect_0_to_s00_couplers_WVALID;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_ARADDR;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_ARBURST;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARCACHE;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_ARID;\n  wire [7:0]axi_interconnect_0_to_s01_couplers_ARLEN;\n  wire [0:0]axi_interconnect_0_to_s01_couplers_ARLOCK;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_ARPROT;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARQOS;\n  wire axi_interconnect_0_to_s01_couplers_ARREADY;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARREGION;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_ARSIZE;\n  wire axi_interconnect_0_to_s01_couplers_ARVALID;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_AWADDR;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_AWBURST;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWCACHE;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_AWID;\n  wire [7:0]axi_interconnect_0_to_s01_couplers_AWLEN;\n  wire [0:0]axi_interconnect_0_to_s01_couplers_AWLOCK;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_AWPROT;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWQOS;\n  wire axi_interconnect_0_to_s01_couplers_AWREADY;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWREGION;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_AWSIZE;\n  wire axi_interconnect_0_to_s01_couplers_AWVALID;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_BID;\n  wire axi_interconnect_0_to_s01_couplers_BREADY;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_BRESP;\n  wire axi_interconnect_0_to_s01_couplers_BVALID;\n  wire [511:0]axi_interconnect_0_to_s01_couplers_RDATA;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_RID;\n  wire axi_interconnect_0_to_s01_couplers_RLAST;\n  wire axi_interconnect_0_to_s01_couplers_RREADY;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_RRESP;\n  wire axi_interconnect_0_to_s01_couplers_RVALID;\n  wire [511:0]axi_interconnect_0_to_s01_couplers_WDATA;\n  wire axi_interconnect_0_to_s01_couplers_WLAST;\n  wire axi_interconnect_0_to_s01_couplers_WREADY;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_WSTRB;\n  wire axi_interconnect_0_to_s01_couplers_WVALID;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m00_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m00_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARQOS;\n  wire m00_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m00_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m00_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m00_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWQOS;\n  wire m00_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m00_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_BID;\n  wire m00_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_BRESP;\n  wire m00_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m00_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_RID;\n  wire m00_couplers_to_axi_interconnect_0_RLAST;\n  wire m00_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_RRESP;\n  wire m00_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m00_couplers_to_axi_interconnect_0_WDATA;\n  wire m00_couplers_to_axi_interconnect_0_WLAST;\n  wire m00_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_WSTRB;\n  wire m00_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m01_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m01_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARQOS;\n  wire m01_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m01_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m01_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m01_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWQOS;\n  wire m01_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m01_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_BID;\n  wire m01_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_BRESP;\n  wire m01_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m01_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_RID;\n  wire m01_couplers_to_axi_interconnect_0_RLAST;\n  wire m01_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_RRESP;\n  wire m01_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m01_couplers_to_axi_interconnect_0_WDATA;\n  wire m01_couplers_to_axi_interconnect_0_WLAST;\n  wire m01_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_WSTRB;\n  wire m01_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m02_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m02_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARQOS;\n  wire m02_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m02_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m02_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m02_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWQOS;\n  wire m02_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m02_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_BID;\n  wire m02_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_BRESP;\n  wire m02_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m02_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_RID;\n  wire m02_couplers_to_axi_interconnect_0_RLAST;\n  wire m02_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_RRESP;\n  wire m02_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m02_couplers_to_axi_interconnect_0_WDATA;\n  wire m02_couplers_to_axi_interconnect_0_WLAST;\n  wire m02_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_WSTRB;\n  wire m02_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m03_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m03_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARQOS;\n  wire m03_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m03_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m03_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m03_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWQOS;\n  wire m03_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m03_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_BID;\n  wire m03_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_BRESP;\n  wire m03_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m03_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_RID;\n  wire m03_couplers_to_axi_interconnect_0_RLAST;\n  wire m03_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_RRESP;\n  wire m03_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m03_couplers_to_axi_interconnect_0_WDATA;\n  wire m03_couplers_to_axi_interconnect_0_WLAST;\n  wire m03_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_WSTRB;\n  wire m03_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]s00_couplers_to_xbar_ARADDR;\n  wire [1:0]s00_couplers_to_xbar_ARBURST;\n  wire [3:0]s00_couplers_to_xbar_ARCACHE;\n  wire [5:0]s00_couplers_to_xbar_ARID;\n  wire [7:0]s00_couplers_to_xbar_ARLEN;\n  wire [0:0]s00_couplers_to_xbar_ARLOCK;\n  wire [2:0]s00_couplers_to_xbar_ARPROT;\n  wire [3:0]s00_couplers_to_xbar_ARQOS;\n  wire [0:0]s00_couplers_to_xbar_ARREADY;\n  wire [2:0]s00_couplers_to_xbar_ARSIZE;\n  wire s00_couplers_to_xbar_ARVALID;\n  wire [63:0]s00_couplers_to_xbar_AWADDR;\n  wire [1:0]s00_couplers_to_xbar_AWBURST;\n  wire [3:0]s00_couplers_to_xbar_AWCACHE;\n  wire [5:0]s00_couplers_to_xbar_AWID;\n  wire [7:0]s00_couplers_to_xbar_AWLEN;\n  wire [0:0]s00_couplers_to_xbar_AWLOCK;\n  wire [2:0]s00_couplers_to_xbar_AWPROT;\n  wire [3:0]s00_couplers_to_xbar_AWQOS;\n  wire [0:0]s00_couplers_to_xbar_AWREADY;\n  wire [2:0]s00_couplers_to_xbar_AWSIZE;\n  wire s00_couplers_to_xbar_AWVALID;\n  wire [6:0]s00_couplers_to_xbar_BID;\n  wire s00_couplers_to_xbar_BREADY;\n  wire [1:0]s00_couplers_to_xbar_BRESP;\n  wire [0:0]s00_couplers_to_xbar_BVALID;\n  wire [511:0]s00_couplers_to_xbar_RDATA;\n  wire [6:0]s00_couplers_to_xbar_RID;\n  wire [0:0]s00_couplers_to_xbar_RLAST;\n  wire s00_couplers_to_xbar_RREADY;\n  wire [1:0]s00_couplers_to_xbar_RRESP;\n  wire [0:0]s00_couplers_to_xbar_RVALID;\n  wire [511:0]s00_couplers_to_xbar_WDATA;\n  wire s00_couplers_to_xbar_WLAST;\n  wire [0:0]s00_couplers_to_xbar_WREADY;\n  wire [63:0]s00_couplers_to_xbar_WSTRB;\n  wire s00_couplers_to_xbar_WVALID;\n  wire [63:0]s01_couplers_to_xbar_ARADDR;\n  wire [1:0]s01_couplers_to_xbar_ARBURST;\n  wire [3:0]s01_couplers_to_xbar_ARCACHE;\n  wire [5:0]s01_couplers_to_xbar_ARID;\n  wire [7:0]s01_couplers_to_xbar_ARLEN;\n  wire [0:0]s01_couplers_to_xbar_ARLOCK;\n  wire [2:0]s01_couplers_to_xbar_ARPROT;\n  wire [3:0]s01_couplers_to_xbar_ARQOS;\n  wire [1:1]s01_couplers_to_xbar_ARREADY;\n  wire [2:0]s01_couplers_to_xbar_ARSIZE;\n  wire s01_couplers_to_xbar_ARVALID;\n  wire [63:0]s01_couplers_to_xbar_AWADDR;\n  wire [1:0]s01_couplers_to_xbar_AWBURST;\n  wire [3:0]s01_couplers_to_xbar_AWCACHE;\n  wire [5:0]s01_couplers_to_xbar_AWID;\n  wire [7:0]s01_couplers_to_xbar_AWLEN;\n  wire [0:0]s01_couplers_to_xbar_AWLOCK;\n  wire [2:0]s01_couplers_to_xbar_AWPROT;\n  wire [3:0]s01_couplers_to_xbar_AWQOS;\n  wire [1:1]s01_couplers_to_xbar_AWREADY;\n  wire [2:0]s01_couplers_to_xbar_AWSIZE;\n  wire s01_couplers_to_xbar_AWVALID;\n  wire [13:7]s01_couplers_to_xbar_BID;\n  wire s01_couplers_to_xbar_BREADY;\n  wire [3:2]s01_couplers_to_xbar_BRESP;\n  wire [1:1]s01_couplers_to_xbar_BVALID;\n  wire [1023:512]s01_couplers_to_xbar_RDATA;\n  wire [13:7]s01_couplers_to_xbar_RID;\n  wire [1:1]s01_couplers_to_xbar_RLAST;\n  wire s01_couplers_to_xbar_RREADY;\n  wire [3:2]s01_couplers_to_xbar_RRESP;\n  wire [1:1]s01_couplers_to_xbar_RVALID;\n  wire [511:0]s01_couplers_to_xbar_WDATA;\n  wire s01_couplers_to_xbar_WLAST;\n  wire [1:1]s01_couplers_to_xbar_WREADY;\n  wire [63:0]s01_couplers_to_xbar_WSTRB;\n  wire s01_couplers_to_xbar_WVALID;\n  wire [63:0]xbar_to_m00_couplers_ARADDR;\n  wire [1:0]xbar_to_m00_couplers_ARBURST;\n  wire [3:0]xbar_to_m00_couplers_ARCACHE;\n  wire [6:0]xbar_to_m00_couplers_ARID;\n  wire [7:0]xbar_to_m00_couplers_ARLEN;\n  wire [0:0]xbar_to_m00_couplers_ARLOCK;\n  wire [2:0]xbar_to_m00_couplers_ARPROT;\n  wire [3:0]xbar_to_m00_couplers_ARQOS;\n  wire xbar_to_m00_couplers_ARREADY;\n  wire [3:0]xbar_to_m00_couplers_ARREGION;\n  wire [2:0]xbar_to_m00_couplers_ARSIZE;\n  wire [0:0]xbar_to_m00_couplers_ARVALID;\n  wire [63:0]xbar_to_m00_couplers_AWADDR;\n  wire [1:0]xbar_to_m00_couplers_AWBURST;\n  wire [3:0]xbar_to_m00_couplers_AWCACHE;\n  wire [6:0]xbar_to_m00_couplers_AWID;\n  wire [7:0]xbar_to_m00_couplers_AWLEN;\n  wire [0:0]xbar_to_m00_couplers_AWLOCK;\n  wire [2:0]xbar_to_m00_couplers_AWPROT;\n  wire [3:0]xbar_to_m00_couplers_AWQOS;\n  wire xbar_to_m00_couplers_AWREADY;\n  wire [3:0]xbar_to_m00_couplers_AWREGION;\n  wire [2:0]xbar_to_m00_couplers_AWSIZE;\n  wire [0:0]xbar_to_m00_couplers_AWVALID;\n  wire [6:0]xbar_to_m00_couplers_BID;\n  wire [0:0]xbar_to_m00_couplers_BREADY;\n  wire [1:0]xbar_to_m00_couplers_BRESP;\n  wire xbar_to_m00_couplers_BVALID;\n  wire [511:0]xbar_to_m00_couplers_RDATA;\n  wire [6:0]xbar_to_m00_couplers_RID;\n  wire xbar_to_m00_couplers_RLAST;\n  wire [0:0]xbar_to_m00_couplers_RREADY;\n  wire [1:0]xbar_to_m00_couplers_RRESP;\n  wire xbar_to_m00_couplers_RVALID;\n  wire [511:0]xbar_to_m00_couplers_WDATA;\n  wire [0:0]xbar_to_m00_couplers_WLAST;\n  wire xbar_to_m00_couplers_WREADY;\n  wire [63:0]xbar_to_m00_couplers_WSTRB;\n  wire [0:0]xbar_to_m00_couplers_WVALID;\n  wire [127:64]xbar_to_m01_couplers_ARADDR;\n  wire [3:2]xbar_to_m01_couplers_ARBURST;\n  wire [7:4]xbar_to_m01_couplers_ARCACHE;\n  wire [13:7]xbar_to_m01_couplers_ARID;\n  wire [15:8]xbar_to_m01_couplers_ARLEN;\n  wire [1:1]xbar_to_m01_couplers_ARLOCK;\n  wire [5:3]xbar_to_m01_couplers_ARPROT;\n  wire [7:4]xbar_to_m01_couplers_ARQOS;\n  wire xbar_to_m01_couplers_ARREADY;\n  wire [7:4]xbar_to_m01_couplers_ARREGION;\n  wire [5:3]xbar_to_m01_couplers_ARSIZE;\n  wire [1:1]xbar_to_m01_couplers_ARVALID;\n  wire [127:64]xbar_to_m01_couplers_AWADDR;\n  wire [3:2]xbar_to_m01_couplers_AWBURST;\n  wire [7:4]xbar_to_m01_couplers_AWCACHE;\n  wire [13:7]xbar_to_m01_couplers_AWID;\n  wire [15:8]xbar_to_m01_couplers_AWLEN;\n  wire [1:1]xbar_to_m01_couplers_AWLOCK;\n  wire [5:3]xbar_to_m01_couplers_AWPROT;\n  wire [7:4]xbar_to_m01_couplers_AWQOS;\n  wire xbar_to_m01_couplers_AWREADY;\n  wire [7:4]xbar_to_m01_couplers_AWREGION;\n  wire [5:3]xbar_to_m01_couplers_AWSIZE;\n  wire [1:1]xbar_to_m01_couplers_AWVALID;\n  wire [6:0]xbar_to_m01_couplers_BID;\n  wire [1:1]xbar_to_m01_couplers_BREADY;\n  wire [1:0]xbar_to_m01_couplers_BRESP;\n  wire xbar_to_m01_couplers_BVALID;\n  wire [511:0]xbar_to_m01_couplers_RDATA;\n  wire [6:0]xbar_to_m01_couplers_RID;\n  wire xbar_to_m01_couplers_RLAST;\n  wire [1:1]xbar_to_m01_couplers_RREADY;\n  wire [1:0]xbar_to_m01_couplers_RRESP;\n  wire xbar_to_m01_couplers_RVALID;\n  wire [1023:512]xbar_to_m01_couplers_WDATA;\n  wire [1:1]xbar_to_m01_couplers_WLAST;\n  wire xbar_to_m01_couplers_WREADY;\n  wire [127:64]xbar_to_m01_couplers_WSTRB;\n  wire [1:1]xbar_to_m01_couplers_WVALID;\n  wire [191:128]xbar_to_m02_couplers_ARADDR;\n  wire [5:4]xbar_to_m02_couplers_ARBURST;\n  wire [11:8]xbar_to_m02_couplers_ARCACHE;\n  wire [20:14]xbar_to_m02_couplers_ARID;\n  wire [23:16]xbar_to_m02_couplers_ARLEN;\n  wire [2:2]xbar_to_m02_couplers_ARLOCK;\n  wire [8:6]xbar_to_m02_couplers_ARPROT;\n  wire [11:8]xbar_to_m02_couplers_ARQOS;\n  wire xbar_to_m02_couplers_ARREADY;\n  wire [11:8]xbar_to_m02_couplers_ARREGION;\n  wire [8:6]xbar_to_m02_couplers_ARSIZE;\n  wire [2:2]xbar_to_m02_couplers_ARVALID;\n  wire [191:128]xbar_to_m02_couplers_AWADDR;\n  wire [5:4]xbar_to_m02_couplers_AWBURST;\n  wire [11:8]xbar_to_m02_couplers_AWCACHE;\n  wire [20:14]xbar_to_m02_couplers_AWID;\n  wire [23:16]xbar_to_m02_couplers_AWLEN;\n  wire [2:2]xbar_to_m02_couplers_AWLOCK;\n  wire [8:6]xbar_to_m02_couplers_AWPROT;\n  wire [11:8]xbar_to_m02_couplers_AWQOS;\n  wire xbar_to_m02_couplers_AWREADY;\n  wire [11:8]xbar_to_m02_couplers_AWREGION;\n  wire [8:6]xbar_to_m02_couplers_AWSIZE;\n  wire [2:2]xbar_to_m02_couplers_AWVALID;\n  wire [6:0]xbar_to_m02_couplers_BID;\n  wire [2:2]xbar_to_m02_couplers_BREADY;\n  wire [1:0]xbar_to_m02_couplers_BRESP;\n  wire xbar_to_m02_couplers_BVALID;\n  wire [511:0]xbar_to_m02_couplers_RDATA;\n  wire [6:0]xbar_to_m02_couplers_RID;\n  wire xbar_to_m02_couplers_RLAST;\n  wire [2:2]xbar_to_m02_couplers_RREADY;\n  wire [1:0]xbar_to_m02_couplers_RRESP;\n  wire xbar_to_m02_couplers_RVALID;\n  wire [1535:1024]xbar_to_m02_couplers_WDATA;\n  wire [2:2]xbar_to_m02_couplers_WLAST;\n  wire xbar_to_m02_couplers_WREADY;\n  wire [191:128]xbar_to_m02_couplers_WSTRB;\n  wire [2:2]xbar_to_m02_couplers_WVALID;\n  wire [255:192]xbar_to_m03_couplers_ARADDR;\n  wire [7:6]xbar_to_m03_couplers_ARBURST;\n  wire [15:12]xbar_to_m03_couplers_ARCACHE;\n  wire [27:21]xbar_to_m03_couplers_ARID;\n  wire [31:24]xbar_to_m03_couplers_ARLEN;\n  wire [3:3]xbar_to_m03_couplers_ARLOCK;\n  wire [11:9]xbar_to_m03_couplers_ARPROT;\n  wire [15:12]xbar_to_m03_couplers_ARQOS;\n  wire xbar_to_m03_couplers_ARREADY;\n  wire [15:12]xbar_to_m03_couplers_ARREGION;\n  wire [11:9]xbar_to_m03_couplers_ARSIZE;\n  wire [3:3]xbar_to_m03_couplers_ARVALID;\n  wire [255:192]xbar_to_m03_couplers_AWADDR;\n  wire [7:6]xbar_to_m03_couplers_AWBURST;\n  wire [15:12]xbar_to_m03_couplers_AWCACHE;\n  wire [27:21]xbar_to_m03_couplers_AWID;\n  wire [31:24]xbar_to_m03_couplers_AWLEN;\n  wire [3:3]xbar_to_m03_couplers_AWLOCK;\n  wire [11:9]xbar_to_m03_couplers_AWPROT;\n  wire [15:12]xbar_to_m03_couplers_AWQOS;\n  wire xbar_to_m03_couplers_AWREADY;\n  wire [15:12]xbar_to_m03_couplers_AWREGION;\n  wire [11:9]xbar_to_m03_couplers_AWSIZE;\n  wire [3:3]xbar_to_m03_couplers_AWVALID;\n  wire [6:0]xbar_to_m03_couplers_BID;\n  wire [3:3]xbar_to_m03_couplers_BREADY;\n  wire [1:0]xbar_to_m03_couplers_BRESP;\n  wire xbar_to_m03_couplers_BVALID;\n  wire [511:0]xbar_to_m03_couplers_RDATA;\n  wire [6:0]xbar_to_m03_couplers_RID;\n  wire xbar_to_m03_couplers_RLAST;\n  wire [3:3]xbar_to_m03_couplers_RREADY;\n  wire [1:0]xbar_to_m03_couplers_RRESP;\n  wire xbar_to_m03_couplers_RVALID;\n  wire [2047:1536]xbar_to_m03_couplers_WDATA;\n  wire [3:3]xbar_to_m03_couplers_WLAST;\n  wire xbar_to_m03_couplers_WREADY;\n  wire [255:192]xbar_to_m03_couplers_WSTRB;\n  wire [3:3]xbar_to_m03_couplers_WVALID;\n\n  assign M00_AXI_araddr[63:0] = m00_couplers_to_axi_interconnect_0_ARADDR;\n  assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_interconnect_0_ARBURST;\n  assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M00_AXI_arid[6:0] = m00_couplers_to_axi_interconnect_0_ARID;\n  assign M00_AXI_arlen[7:0] = m00_couplers_to_axi_interconnect_0_ARLEN;\n  assign M00_AXI_arlock[0] = m00_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_interconnect_0_ARPROT;\n  assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_interconnect_0_ARQOS;\n  assign M00_AXI_arregion[3:0] = m00_couplers_to_axi_interconnect_0_ARREGION;\n  assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M00_AXI_arvalid = m00_couplers_to_axi_interconnect_0_ARVALID;\n  assign M00_AXI_awaddr[63:0] = m00_couplers_to_axi_interconnect_0_AWADDR;\n  assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_interconnect_0_AWBURST;\n  assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M00_AXI_awid[6:0] = m00_couplers_to_axi_interconnect_0_AWID;\n  assign M00_AXI_awlen[7:0] = m00_couplers_to_axi_interconnect_0_AWLEN;\n  assign M00_AXI_awlock[0] = m00_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_interconnect_0_AWPROT;\n  assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_interconnect_0_AWQOS;\n  assign M00_AXI_awregion[3:0] = m00_couplers_to_axi_interconnect_0_AWREGION;\n  assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M00_AXI_awvalid = m00_couplers_to_axi_interconnect_0_AWVALID;\n  assign M00_AXI_bready = m00_couplers_to_axi_interconnect_0_BREADY;\n  assign M00_AXI_rready = m00_couplers_to_axi_interconnect_0_RREADY;\n  assign M00_AXI_wdata[511:0] = m00_couplers_to_axi_interconnect_0_WDATA;\n  assign M00_AXI_wlast = m00_couplers_to_axi_interconnect_0_WLAST;\n  assign M00_AXI_wstrb[63:0] = m00_couplers_to_axi_interconnect_0_WSTRB;\n  assign M00_AXI_wvalid = m00_couplers_to_axi_interconnect_0_WVALID;\n  assign M01_AXI_araddr[63:0] = m01_couplers_to_axi_interconnect_0_ARADDR;\n  assign M01_AXI_arburst[1:0] = m01_couplers_to_axi_interconnect_0_ARBURST;\n  assign M01_AXI_arcache[3:0] = m01_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M01_AXI_arid[6:0] = m01_couplers_to_axi_interconnect_0_ARID;\n  assign M01_AXI_arlen[7:0] = m01_couplers_to_axi_interconnect_0_ARLEN;\n  assign M01_AXI_arlock[0] = m01_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M01_AXI_arprot[2:0] = m01_couplers_to_axi_interconnect_0_ARPROT;\n  assign M01_AXI_arqos[3:0] = m01_couplers_to_axi_interconnect_0_ARQOS;\n  assign M01_AXI_arregion[3:0] = m01_couplers_to_axi_interconnect_0_ARREGION;\n  assign M01_AXI_arsize[2:0] = m01_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M01_AXI_arvalid = m01_couplers_to_axi_interconnect_0_ARVALID;\n  assign M01_AXI_awaddr[63:0] = m01_couplers_to_axi_interconnect_0_AWADDR;\n  assign M01_AXI_awburst[1:0] = m01_couplers_to_axi_interconnect_0_AWBURST;\n  assign M01_AXI_awcache[3:0] = m01_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M01_AXI_awid[6:0] = m01_couplers_to_axi_interconnect_0_AWID;\n  assign M01_AXI_awlen[7:0] = m01_couplers_to_axi_interconnect_0_AWLEN;\n  assign M01_AXI_awlock[0] = m01_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M01_AXI_awprot[2:0] = m01_couplers_to_axi_interconnect_0_AWPROT;\n  assign M01_AXI_awqos[3:0] = m01_couplers_to_axi_interconnect_0_AWQOS;\n  assign M01_AXI_awregion[3:0] = m01_couplers_to_axi_interconnect_0_AWREGION;\n  assign M01_AXI_awsize[2:0] = m01_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M01_AXI_awvalid = m01_couplers_to_axi_interconnect_0_AWVALID;\n  assign M01_AXI_bready = m01_couplers_to_axi_interconnect_0_BREADY;\n  assign M01_AXI_rready = m01_couplers_to_axi_interconnect_0_RREADY;\n  assign M01_AXI_wdata[511:0] = m01_couplers_to_axi_interconnect_0_WDATA;\n  assign M01_AXI_wlast = m01_couplers_to_axi_interconnect_0_WLAST;\n  assign M01_AXI_wstrb[63:0] = m01_couplers_to_axi_interconnect_0_WSTRB;\n  assign M01_AXI_wvalid = m01_couplers_to_axi_interconnect_0_WVALID;\n  assign M02_AXI_araddr[63:0] = m02_couplers_to_axi_interconnect_0_ARADDR;\n  assign M02_AXI_arburst[1:0] = m02_couplers_to_axi_interconnect_0_ARBURST;\n  assign M02_AXI_arcache[3:0] = m02_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M02_AXI_arid[6:0] = m02_couplers_to_axi_interconnect_0_ARID;\n  assign M02_AXI_arlen[7:0] = m02_couplers_to_axi_interconnect_0_ARLEN;\n  assign M02_AXI_arlock[0] = m02_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M02_AXI_arprot[2:0] = m02_couplers_to_axi_interconnect_0_ARPROT;\n  assign M02_AXI_arqos[3:0] = m02_couplers_to_axi_interconnect_0_ARQOS;\n  assign M02_AXI_arregion[3:0] = m02_couplers_to_axi_interconnect_0_ARREGION;\n  assign M02_AXI_arsize[2:0] = m02_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M02_AXI_arvalid = m02_couplers_to_axi_interconnect_0_ARVALID;\n  assign M02_AXI_awaddr[63:0] = m02_couplers_to_axi_interconnect_0_AWADDR;\n  assign M02_AXI_awburst[1:0] = m02_couplers_to_axi_interconnect_0_AWBURST;\n  assign M02_AXI_awcache[3:0] = m02_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M02_AXI_awid[6:0] = m02_couplers_to_axi_interconnect_0_AWID;\n  assign M02_AXI_awlen[7:0] = m02_couplers_to_axi_interconnect_0_AWLEN;\n  assign M02_AXI_awlock[0] = m02_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M02_AXI_awprot[2:0] = m02_couplers_to_axi_interconnect_0_AWPROT;\n  assign M02_AXI_awqos[3:0] = m02_couplers_to_axi_interconnect_0_AWQOS;\n  assign M02_AXI_awregion[3:0] = m02_couplers_to_axi_interconnect_0_AWREGION;\n  assign M02_AXI_awsize[2:0] = m02_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M02_AXI_awvalid = m02_couplers_to_axi_interconnect_0_AWVALID;\n  assign M02_AXI_bready = m02_couplers_to_axi_interconnect_0_BREADY;\n  assign M02_AXI_rready = m02_couplers_to_axi_interconnect_0_RREADY;\n  assign M02_AXI_wdata[511:0] = m02_couplers_to_axi_interconnect_0_WDATA;\n  assign M02_AXI_wlast = m02_couplers_to_axi_interconnect_0_WLAST;\n  assign M02_AXI_wstrb[63:0] = m02_couplers_to_axi_interconnect_0_WSTRB;\n  assign M02_AXI_wvalid = m02_couplers_to_axi_interconnect_0_WVALID;\n  assign M03_AXI_araddr[63:0] = m03_couplers_to_axi_interconnect_0_ARADDR;\n  assign M03_AXI_arburst[1:0] = m03_couplers_to_axi_interconnect_0_ARBURST;\n  assign M03_AXI_arcache[3:0] = m03_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M03_AXI_arid[6:0] = m03_couplers_to_axi_interconnect_0_ARID;\n  assign M03_AXI_arlen[7:0] = m03_couplers_to_axi_interconnect_0_ARLEN;\n  assign M03_AXI_arlock[0] = m03_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M03_AXI_arprot[2:0] = m03_couplers_to_axi_interconnect_0_ARPROT;\n  assign M03_AXI_arqos[3:0] = m03_couplers_to_axi_interconnect_0_ARQOS;\n  assign M03_AXI_arregion[3:0] = m03_couplers_to_axi_interconnect_0_ARREGION;\n  assign M03_AXI_arsize[2:0] = m03_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M03_AXI_arvalid = m03_couplers_to_axi_interconnect_0_ARVALID;\n  assign M03_AXI_awaddr[63:0] = m03_couplers_to_axi_interconnect_0_AWADDR;\n  assign M03_AXI_awburst[1:0] = m03_couplers_to_axi_interconnect_0_AWBURST;\n  assign M03_AXI_awcache[3:0] = m03_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M03_AXI_awid[6:0] = m03_couplers_to_axi_interconnect_0_AWID;\n  assign M03_AXI_awlen[7:0] = m03_couplers_to_axi_interconnect_0_AWLEN;\n  assign M03_AXI_awlock[0] = m03_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M03_AXI_awprot[2:0] = m03_couplers_to_axi_interconnect_0_AWPROT;\n  assign M03_AXI_awqos[3:0] = m03_couplers_to_axi_interconnect_0_AWQOS;\n  assign M03_AXI_awregion[3:0] = m03_couplers_to_axi_interconnect_0_AWREGION;\n  assign M03_AXI_awsize[2:0] = m03_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M03_AXI_awvalid = m03_couplers_to_axi_interconnect_0_AWVALID;\n  assign M03_AXI_bready = m03_couplers_to_axi_interconnect_0_BREADY;\n  assign M03_AXI_rready = m03_couplers_to_axi_interconnect_0_RREADY;\n  assign M03_AXI_wdata[511:0] = m03_couplers_to_axi_interconnect_0_WDATA;\n  assign M03_AXI_wlast = m03_couplers_to_axi_interconnect_0_WLAST;\n  assign M03_AXI_wstrb[63:0] = m03_couplers_to_axi_interconnect_0_WSTRB;\n  assign M03_AXI_wvalid = m03_couplers_to_axi_interconnect_0_WVALID;\n  assign S00_AXI_arready = axi_interconnect_0_to_s00_couplers_ARREADY;\n  assign S00_AXI_awready = axi_interconnect_0_to_s00_couplers_AWREADY;\n  assign S00_AXI_bid[5:0] = axi_interconnect_0_to_s00_couplers_BID;\n  assign S00_AXI_bresp[1:0] = axi_interconnect_0_to_s00_couplers_BRESP;\n  assign S00_AXI_bvalid = axi_interconnect_0_to_s00_couplers_BVALID;\n  assign S00_AXI_rdata[511:0] = axi_interconnect_0_to_s00_couplers_RDATA;\n  assign S00_AXI_rid[5:0] = axi_interconnect_0_to_s00_couplers_RID;\n  assign S00_AXI_rlast = axi_interconnect_0_to_s00_couplers_RLAST;\n  assign S00_AXI_rresp[1:0] = axi_interconnect_0_to_s00_couplers_RRESP;\n  assign S00_AXI_rvalid = axi_interconnect_0_to_s00_couplers_RVALID;\n  assign S00_AXI_wready = axi_interconnect_0_to_s00_couplers_WREADY;\n  assign S01_AXI_arready = axi_interconnect_0_to_s01_couplers_ARREADY;\n  assign S01_AXI_awready = axi_interconnect_0_to_s01_couplers_AWREADY;\n  assign S01_AXI_bid[5:0] = axi_interconnect_0_to_s01_couplers_BID;\n  assign S01_AXI_bresp[1:0] = axi_interconnect_0_to_s01_couplers_BRESP;\n  assign S01_AXI_bvalid = axi_interconnect_0_to_s01_couplers_BVALID;\n  assign S01_AXI_rdata[511:0] = axi_interconnect_0_to_s01_couplers_RDATA;\n  assign S01_AXI_rid[5:0] = axi_interconnect_0_to_s01_couplers_RID;\n  assign S01_AXI_rlast = axi_interconnect_0_to_s01_couplers_RLAST;\n  assign S01_AXI_rresp[1:0] = axi_interconnect_0_to_s01_couplers_RRESP;\n  assign S01_AXI_rvalid = axi_interconnect_0_to_s01_couplers_RVALID;\n  assign S01_AXI_wready = axi_interconnect_0_to_s01_couplers_WREADY;\n  assign axi_interconnect_0_ACLK_net = ACLK;\n  assign axi_interconnect_0_ARESETN_net = ARESETN;\n  assign axi_interconnect_0_to_s00_couplers_ARADDR = S00_AXI_araddr[63:0];\n  assign axi_interconnect_0_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];\n  assign axi_interconnect_0_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARID = S00_AXI_arid[5:0];\n  assign axi_interconnect_0_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0];\n  assign axi_interconnect_0_to_s00_couplers_ARLOCK = S00_AXI_arlock[0];\n  assign axi_interconnect_0_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];\n  assign axi_interconnect_0_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARREGION = S00_AXI_arregion[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];\n  assign axi_interconnect_0_to_s00_couplers_ARVALID = S00_AXI_arvalid;\n  assign axi_interconnect_0_to_s00_couplers_AWADDR = S00_AXI_awaddr[63:0];\n  assign axi_interconnect_0_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];\n  assign axi_interconnect_0_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWID = S00_AXI_awid[5:0];\n  assign axi_interconnect_0_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0];\n  assign axi_interconnect_0_to_s00_couplers_AWLOCK = S00_AXI_awlock[0];\n  assign axi_interconnect_0_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];\n  assign axi_interconnect_0_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWREGION = S00_AXI_awregion[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];\n  assign axi_interconnect_0_to_s00_couplers_AWVALID = S00_AXI_awvalid;\n  assign axi_interconnect_0_to_s00_couplers_BREADY = S00_AXI_bready;\n  assign axi_interconnect_0_to_s00_couplers_RREADY = S00_AXI_rready;\n  assign axi_interconnect_0_to_s00_couplers_WDATA = S00_AXI_wdata[511:0];\n  assign axi_interconnect_0_to_s00_couplers_WLAST = S00_AXI_wlast;\n  assign axi_interconnect_0_to_s00_couplers_WSTRB = S00_AXI_wstrb[63:0];\n  assign axi_interconnect_0_to_s00_couplers_WVALID = S00_AXI_wvalid;\n  assign axi_interconnect_0_to_s01_couplers_ARADDR = S01_AXI_araddr[63:0];\n  assign axi_interconnect_0_to_s01_couplers_ARBURST = S01_AXI_arburst[1:0];\n  assign axi_interconnect_0_to_s01_couplers_ARCACHE = S01_AXI_arcache[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARID = S01_AXI_arid[5:0];\n  assign axi_interconnect_0_to_s01_couplers_ARLEN = S01_AXI_arlen[7:0];\n  assign axi_interconnect_0_to_s01_couplers_ARLOCK = S01_AXI_arlock[0];\n  assign axi_interconnect_0_to_s01_couplers_ARPROT = S01_AXI_arprot[2:0];\n  assign axi_interconnect_0_to_s01_couplers_ARQOS = S01_AXI_arqos[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARREGION = S01_AXI_arregion[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARSIZE = S01_AXI_arsize[2:0];\n  assign axi_interconnect_0_to_s01_couplers_ARVALID = S01_AXI_arvalid;\n  assign axi_interconnect_0_to_s01_couplers_AWADDR = S01_AXI_awaddr[63:0];\n  assign axi_interconnect_0_to_s01_couplers_AWBURST = S01_AXI_awburst[1:0];\n  assign axi_interconnect_0_to_s01_couplers_AWCACHE = S01_AXI_awcache[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWID = S01_AXI_awid[5:0];\n  assign axi_interconnect_0_to_s01_couplers_AWLEN = S01_AXI_awlen[7:0];\n  assign axi_interconnect_0_to_s01_couplers_AWLOCK = S01_AXI_awlock[0];\n  assign axi_interconnect_0_to_s01_couplers_AWPROT = S01_AXI_awprot[2:0];\n  assign axi_interconnect_0_to_s01_couplers_AWQOS = S01_AXI_awqos[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWREGION = S01_AXI_awregion[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWSIZE = S01_AXI_awsize[2:0];\n  assign axi_interconnect_0_to_s01_couplers_AWVALID = S01_AXI_awvalid;\n  assign axi_interconnect_0_to_s01_couplers_BREADY = S01_AXI_bready;\n  assign axi_interconnect_0_to_s01_couplers_RREADY = S01_AXI_rready;\n  assign axi_interconnect_0_to_s01_couplers_WDATA = S01_AXI_wdata[511:0];\n  assign axi_interconnect_0_to_s01_couplers_WLAST = S01_AXI_wlast;\n  assign axi_interconnect_0_to_s01_couplers_WSTRB = S01_AXI_wstrb[63:0];\n  assign axi_interconnect_0_to_s01_couplers_WVALID = S01_AXI_wvalid;\n  assign m00_couplers_to_axi_interconnect_0_ARREADY = M00_AXI_arready;\n  assign m00_couplers_to_axi_interconnect_0_AWREADY = M00_AXI_awready;\n  assign m00_couplers_to_axi_interconnect_0_BID = M00_AXI_bid[6:0];\n  assign m00_couplers_to_axi_interconnect_0_BRESP = M00_AXI_bresp[1:0];\n  assign m00_couplers_to_axi_interconnect_0_BVALID = M00_AXI_bvalid;\n  assign m00_couplers_to_axi_interconnect_0_RDATA = M00_AXI_rdata[511:0];\n  assign m00_couplers_to_axi_interconnect_0_RID = M00_AXI_rid[6:0];\n  assign m00_couplers_to_axi_interconnect_0_RLAST = M00_AXI_rlast;\n  assign m00_couplers_to_axi_interconnect_0_RRESP = M00_AXI_rresp[1:0];\n  assign m00_couplers_to_axi_interconnect_0_RVALID = M00_AXI_rvalid;\n  assign m00_couplers_to_axi_interconnect_0_WREADY = M00_AXI_wready;\n  assign m01_couplers_to_axi_interconnect_0_ARREADY = M01_AXI_arready;\n  assign m01_couplers_to_axi_interconnect_0_AWREADY = M01_AXI_awready;\n  assign m01_couplers_to_axi_interconnect_0_BID = M01_AXI_bid[6:0];\n  assign m01_couplers_to_axi_interconnect_0_BRESP = M01_AXI_bresp[1:0];\n  assign m01_couplers_to_axi_interconnect_0_BVALID = M01_AXI_bvalid;\n  assign m01_couplers_to_axi_interconnect_0_RDATA = M01_AXI_rdata[511:0];\n  assign m01_couplers_to_axi_interconnect_0_RID = M01_AXI_rid[6:0];\n  assign m01_couplers_to_axi_interconnect_0_RLAST = M01_AXI_rlast;\n  assign m01_couplers_to_axi_interconnect_0_RRESP = M01_AXI_rresp[1:0];\n  assign m01_couplers_to_axi_interconnect_0_RVALID = M01_AXI_rvalid;\n  assign m01_couplers_to_axi_interconnect_0_WREADY = M01_AXI_wready;\n  assign m02_couplers_to_axi_interconnect_0_ARREADY = M02_AXI_arready;\n  assign m02_couplers_to_axi_interconnect_0_AWREADY = M02_AXI_awready;\n  assign m02_couplers_to_axi_interconnect_0_BID = M02_AXI_bid[6:0];\n  assign m02_couplers_to_axi_interconnect_0_BRESP = M02_AXI_bresp[1:0];\n  assign m02_couplers_to_axi_interconnect_0_BVALID = M02_AXI_bvalid;\n  assign m02_couplers_to_axi_interconnect_0_RDATA = M02_AXI_rdata[511:0];\n  assign m02_couplers_to_axi_interconnect_0_RID = M02_AXI_rid[6:0];\n  assign m02_couplers_to_axi_interconnect_0_RLAST = M02_AXI_rlast;\n  assign m02_couplers_to_axi_interconnect_0_RRESP = M02_AXI_rresp[1:0];\n  assign m02_couplers_to_axi_interconnect_0_RVALID = M02_AXI_rvalid;\n  assign m02_couplers_to_axi_interconnect_0_WREADY = M02_AXI_wready;\n  assign m03_couplers_to_axi_interconnect_0_ARREADY = M03_AXI_arready;\n  assign m03_couplers_to_axi_interconnect_0_AWREADY = M03_AXI_awready;\n  assign m03_couplers_to_axi_interconnect_0_BID = M03_AXI_bid[6:0];\n  assign m03_couplers_to_axi_interconnect_0_BRESP = M03_AXI_bresp[1:0];\n  assign m03_couplers_to_axi_interconnect_0_BVALID = M03_AXI_bvalid;\n  assign m03_couplers_to_axi_interconnect_0_RDATA = M03_AXI_rdata[511:0];\n  assign m03_couplers_to_axi_interconnect_0_RID = M03_AXI_rid[6:0];\n  assign m03_couplers_to_axi_interconnect_0_RLAST = M03_AXI_rlast;\n  assign m03_couplers_to_axi_interconnect_0_RRESP = M03_AXI_rresp[1:0];\n  assign m03_couplers_to_axi_interconnect_0_RVALID = M03_AXI_rvalid;\n  assign m03_couplers_to_axi_interconnect_0_WREADY = M03_AXI_wready;\n  m00_couplers_imp_1QBJ6U2 m00_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m00_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m00_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m00_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m00_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m00_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m00_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m00_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m00_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m00_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m00_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m00_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m00_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m00_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m00_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m00_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m00_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m00_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m00_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m00_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m00_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m00_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m00_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m00_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m00_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m00_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m00_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m00_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m00_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m00_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m00_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m00_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m00_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m00_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m00_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m00_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m00_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m00_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m00_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m00_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m00_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m00_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m00_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m00_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m00_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m00_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m00_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m00_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m00_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m00_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m00_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m00_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m00_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m00_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m00_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m00_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m00_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m00_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m00_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m00_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m00_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m00_couplers_BID),\n        .S_AXI_bready(xbar_to_m00_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m00_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m00_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m00_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m00_couplers_RID),\n        .S_AXI_rlast(xbar_to_m00_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m00_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m00_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m00_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m00_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m00_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m00_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m00_couplers_WVALID));\n  m01_couplers_imp_10IMR9A m01_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m01_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m01_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m01_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m01_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m01_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m01_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m01_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m01_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m01_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m01_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m01_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m01_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m01_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m01_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m01_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m01_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m01_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m01_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m01_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m01_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m01_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m01_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m01_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m01_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m01_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m01_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m01_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m01_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m01_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m01_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m01_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m01_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m01_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m01_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m01_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m01_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m01_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m01_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m01_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m01_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m01_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m01_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m01_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m01_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m01_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m01_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m01_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m01_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m01_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m01_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m01_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m01_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m01_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m01_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m01_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m01_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m01_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m01_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m01_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m01_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m01_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m01_couplers_BID),\n        .S_AXI_bready(xbar_to_m01_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m01_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m01_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m01_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m01_couplers_RID),\n        .S_AXI_rlast(xbar_to_m01_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m01_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m01_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m01_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m01_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m01_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m01_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m01_couplers_WVALID));\n  m02_couplers_imp_APDUS2 m02_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m02_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m02_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m02_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m02_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m02_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m02_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m02_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m02_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m02_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m02_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m02_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m02_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m02_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m02_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m02_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m02_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m02_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m02_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m02_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m02_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m02_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m02_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m02_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m02_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m02_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m02_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m02_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m02_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m02_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m02_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m02_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m02_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m02_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m02_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m02_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m02_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m02_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m02_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m02_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m02_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m02_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m02_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m02_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m02_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m02_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m02_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m02_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m02_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m02_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m02_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m02_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m02_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m02_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m02_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m02_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m02_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m02_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m02_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m02_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m02_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m02_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m02_couplers_BID),\n        .S_AXI_bready(xbar_to_m02_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m02_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m02_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m02_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m02_couplers_RID),\n        .S_AXI_rlast(xbar_to_m02_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m02_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m02_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m02_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m02_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m02_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m02_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m02_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m02_couplers_WVALID));\n  m03_couplers_imp_JAYOMU m03_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m03_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m03_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m03_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m03_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m03_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m03_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m03_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m03_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m03_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m03_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m03_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m03_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m03_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m03_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m03_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m03_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m03_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m03_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m03_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m03_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m03_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m03_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m03_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m03_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m03_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m03_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m03_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m03_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m03_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m03_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m03_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m03_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m03_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m03_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m03_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m03_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m03_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m03_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m03_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m03_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m03_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m03_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m03_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m03_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m03_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m03_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m03_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m03_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m03_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m03_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m03_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m03_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m03_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m03_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m03_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m03_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m03_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m03_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m03_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m03_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m03_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m03_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m03_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m03_couplers_BID),\n        .S_AXI_bready(xbar_to_m03_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m03_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m03_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m03_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m03_couplers_RID),\n        .S_AXI_rlast(xbar_to_m03_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m03_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m03_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m03_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m03_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m03_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m03_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m03_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m03_couplers_WVALID));\n  s00_couplers_imp_QICM5G s00_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(s00_couplers_to_xbar_ARADDR),\n        .M_AXI_arburst(s00_couplers_to_xbar_ARBURST),\n        .M_AXI_arcache(s00_couplers_to_xbar_ARCACHE),\n        .M_AXI_arid(s00_couplers_to_xbar_ARID),\n        .M_AXI_arlen(s00_couplers_to_xbar_ARLEN),\n        .M_AXI_arlock(s00_couplers_to_xbar_ARLOCK),\n        .M_AXI_arprot(s00_couplers_to_xbar_ARPROT),\n        .M_AXI_arqos(s00_couplers_to_xbar_ARQOS),\n        .M_AXI_arready(s00_couplers_to_xbar_ARREADY),\n        .M_AXI_arsize(s00_couplers_to_xbar_ARSIZE),\n        .M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),\n        .M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),\n        .M_AXI_awburst(s00_couplers_to_xbar_AWBURST),\n        .M_AXI_awcache(s00_couplers_to_xbar_AWCACHE),\n        .M_AXI_awid(s00_couplers_to_xbar_AWID),\n        .M_AXI_awlen(s00_couplers_to_xbar_AWLEN),\n        .M_AXI_awlock(s00_couplers_to_xbar_AWLOCK),\n        .M_AXI_awprot(s00_couplers_to_xbar_AWPROT),\n        .M_AXI_awqos(s00_couplers_to_xbar_AWQOS),\n        .M_AXI_awready(s00_couplers_to_xbar_AWREADY),\n        .M_AXI_awsize(s00_couplers_to_xbar_AWSIZE),\n        .M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),\n        .M_AXI_bid(s00_couplers_to_xbar_BID),\n        .M_AXI_bready(s00_couplers_to_xbar_BREADY),\n        .M_AXI_bresp(s00_couplers_to_xbar_BRESP),\n        .M_AXI_bvalid(s00_couplers_to_xbar_BVALID),\n        .M_AXI_rdata(s00_couplers_to_xbar_RDATA),\n        .M_AXI_rid(s00_couplers_to_xbar_RID),\n        .M_AXI_rlast(s00_couplers_to_xbar_RLAST),\n        .M_AXI_rready(s00_couplers_to_xbar_RREADY),\n        .M_AXI_rresp(s00_couplers_to_xbar_RRESP),\n        .M_AXI_rvalid(s00_couplers_to_xbar_RVALID),\n        .M_AXI_wdata(s00_couplers_to_xbar_WDATA),\n        .M_AXI_wlast(s00_couplers_to_xbar_WLAST),\n        .M_AXI_wready(s00_couplers_to_xbar_WREADY),\n        .M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),\n        .M_AXI_wvalid(s00_couplers_to_xbar_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(axi_interconnect_0_to_s00_couplers_ARADDR),\n        .S_AXI_arburst(axi_interconnect_0_to_s00_couplers_ARBURST),\n        .S_AXI_arcache(axi_interconnect_0_to_s00_couplers_ARCACHE),\n        .S_AXI_arid(axi_interconnect_0_to_s00_couplers_ARID),\n        .S_AXI_arlen(axi_interconnect_0_to_s00_couplers_ARLEN),\n        .S_AXI_arlock(axi_interconnect_0_to_s00_couplers_ARLOCK),\n        .S_AXI_arprot(axi_interconnect_0_to_s00_couplers_ARPROT),\n        .S_AXI_arqos(axi_interconnect_0_to_s00_couplers_ARQOS),\n        .S_AXI_arready(axi_interconnect_0_to_s00_couplers_ARREADY),\n        .S_AXI_arregion(axi_interconnect_0_to_s00_couplers_ARREGION),\n        .S_AXI_arsize(axi_interconnect_0_to_s00_couplers_ARSIZE),\n        .S_AXI_arvalid(axi_interconnect_0_to_s00_couplers_ARVALID),\n        .S_AXI_awaddr(axi_interconnect_0_to_s00_couplers_AWADDR),\n        .S_AXI_awburst(axi_interconnect_0_to_s00_couplers_AWBURST),\n        .S_AXI_awcache(axi_interconnect_0_to_s00_couplers_AWCACHE),\n        .S_AXI_awid(axi_interconnect_0_to_s00_couplers_AWID),\n        .S_AXI_awlen(axi_interconnect_0_to_s00_couplers_AWLEN),\n        .S_AXI_awlock(axi_interconnect_0_to_s00_couplers_AWLOCK),\n        .S_AXI_awprot(axi_interconnect_0_to_s00_couplers_AWPROT),\n        .S_AXI_awqos(axi_interconnect_0_to_s00_couplers_AWQOS),\n        .S_AXI_awready(axi_interconnect_0_to_s00_couplers_AWREADY),\n        .S_AXI_awregion(axi_interconnect_0_to_s00_couplers_AWREGION),\n        .S_AXI_awsize(axi_interconnect_0_to_s00_couplers_AWSIZE),\n        .S_AXI_awvalid(axi_interconnect_0_to_s00_couplers_AWVALID),\n        .S_AXI_bid(axi_interconnect_0_to_s00_couplers_BID),\n        .S_AXI_bready(axi_interconnect_0_to_s00_couplers_BREADY),\n        .S_AXI_bresp(axi_interconnect_0_to_s00_couplers_BRESP),\n        .S_AXI_bvalid(axi_interconnect_0_to_s00_couplers_BVALID),\n        .S_AXI_rdata(axi_interconnect_0_to_s00_couplers_RDATA),\n        .S_AXI_rid(axi_interconnect_0_to_s00_couplers_RID),\n        .S_AXI_rlast(axi_interconnect_0_to_s00_couplers_RLAST),\n        .S_AXI_rready(axi_interconnect_0_to_s00_couplers_RREADY),\n        .S_AXI_rresp(axi_interconnect_0_to_s00_couplers_RRESP),\n        .S_AXI_rvalid(axi_interconnect_0_to_s00_couplers_RVALID),\n        .S_AXI_wdata(axi_interconnect_0_to_s00_couplers_WDATA),\n        .S_AXI_wlast(axi_interconnect_0_to_s00_couplers_WLAST),\n        .S_AXI_wready(axi_interconnect_0_to_s00_couplers_WREADY),\n        .S_AXI_wstrb(axi_interconnect_0_to_s00_couplers_WSTRB),\n        .S_AXI_wvalid(axi_interconnect_0_to_s00_couplers_WVALID));\n  s01_couplers_imp_GSTXQ8 s01_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(s01_couplers_to_xbar_ARADDR),\n        .M_AXI_arburst(s01_couplers_to_xbar_ARBURST),\n        .M_AXI_arcache(s01_couplers_to_xbar_ARCACHE),\n        .M_AXI_arid(s01_couplers_to_xbar_ARID),\n        .M_AXI_arlen(s01_couplers_to_xbar_ARLEN),\n        .M_AXI_arlock(s01_couplers_to_xbar_ARLOCK),\n        .M_AXI_arprot(s01_couplers_to_xbar_ARPROT),\n        .M_AXI_arqos(s01_couplers_to_xbar_ARQOS),\n        .M_AXI_arready(s01_couplers_to_xbar_ARREADY),\n        .M_AXI_arsize(s01_couplers_to_xbar_ARSIZE),\n        .M_AXI_arvalid(s01_couplers_to_xbar_ARVALID),\n        .M_AXI_awaddr(s01_couplers_to_xbar_AWADDR),\n        .M_AXI_awburst(s01_couplers_to_xbar_AWBURST),\n        .M_AXI_awcache(s01_couplers_to_xbar_AWCACHE),\n        .M_AXI_awid(s01_couplers_to_xbar_AWID),\n        .M_AXI_awlen(s01_couplers_to_xbar_AWLEN),\n        .M_AXI_awlock(s01_couplers_to_xbar_AWLOCK),\n        .M_AXI_awprot(s01_couplers_to_xbar_AWPROT),\n        .M_AXI_awqos(s01_couplers_to_xbar_AWQOS),\n        .M_AXI_awready(s01_couplers_to_xbar_AWREADY),\n        .M_AXI_awsize(s01_couplers_to_xbar_AWSIZE),\n        .M_AXI_awvalid(s01_couplers_to_xbar_AWVALID),\n        .M_AXI_bid(s01_couplers_to_xbar_BID),\n        .M_AXI_bready(s01_couplers_to_xbar_BREADY),\n        .M_AXI_bresp(s01_couplers_to_xbar_BRESP),\n        .M_AXI_bvalid(s01_couplers_to_xbar_BVALID),\n        .M_AXI_rdata(s01_couplers_to_xbar_RDATA),\n        .M_AXI_rid(s01_couplers_to_xbar_RID),\n        .M_AXI_rlast(s01_couplers_to_xbar_RLAST),\n        .M_AXI_rready(s01_couplers_to_xbar_RREADY),\n        .M_AXI_rresp(s01_couplers_to_xbar_RRESP),\n        .M_AXI_rvalid(s01_couplers_to_xbar_RVALID),\n        .M_AXI_wdata(s01_couplers_to_xbar_WDATA),\n        .M_AXI_wlast(s01_couplers_to_xbar_WLAST),\n        .M_AXI_wready(s01_couplers_to_xbar_WREADY),\n        .M_AXI_wstrb(s01_couplers_to_xbar_WSTRB),\n        .M_AXI_wvalid(s01_couplers_to_xbar_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(axi_interconnect_0_to_s01_couplers_ARADDR),\n        .S_AXI_arburst(axi_interconnect_0_to_s01_couplers_ARBURST),\n        .S_AXI_arcache(axi_interconnect_0_to_s01_couplers_ARCACHE),\n        .S_AXI_arid(axi_interconnect_0_to_s01_couplers_ARID),\n        .S_AXI_arlen(axi_interconnect_0_to_s01_couplers_ARLEN),\n        .S_AXI_arlock(axi_interconnect_0_to_s01_couplers_ARLOCK),\n        .S_AXI_arprot(axi_interconnect_0_to_s01_couplers_ARPROT),\n        .S_AXI_arqos(axi_interconnect_0_to_s01_couplers_ARQOS),\n        .S_AXI_arready(axi_interconnect_0_to_s01_couplers_ARREADY),\n        .S_AXI_arregion(axi_interconnect_0_to_s01_couplers_ARREGION),\n        .S_AXI_arsize(axi_interconnect_0_to_s01_couplers_ARSIZE),\n        .S_AXI_arvalid(axi_interconnect_0_to_s01_couplers_ARVALID),\n        .S_AXI_awaddr(axi_interconnect_0_to_s01_couplers_AWADDR),\n        .S_AXI_awburst(axi_interconnect_0_to_s01_couplers_AWBURST),\n        .S_AXI_awcache(axi_interconnect_0_to_s01_couplers_AWCACHE),\n        .S_AXI_awid(axi_interconnect_0_to_s01_couplers_AWID),\n        .S_AXI_awlen(axi_interconnect_0_to_s01_couplers_AWLEN),\n        .S_AXI_awlock(axi_interconnect_0_to_s01_couplers_AWLOCK),\n        .S_AXI_awprot(axi_interconnect_0_to_s01_couplers_AWPROT),\n        .S_AXI_awqos(axi_interconnect_0_to_s01_couplers_AWQOS),\n        .S_AXI_awready(axi_interconnect_0_to_s01_couplers_AWREADY),\n        .S_AXI_awregion(axi_interconnect_0_to_s01_couplers_AWREGION),\n        .S_AXI_awsize(axi_interconnect_0_to_s01_couplers_AWSIZE),\n        .S_AXI_awvalid(axi_interconnect_0_to_s01_couplers_AWVALID),\n        .S_AXI_bid(axi_interconnect_0_to_s01_couplers_BID),\n        .S_AXI_bready(axi_interconnect_0_to_s01_couplers_BREADY),\n        .S_AXI_bresp(axi_interconnect_0_to_s01_couplers_BRESP),\n        .S_AXI_bvalid(axi_interconnect_0_to_s01_couplers_BVALID),\n        .S_AXI_rdata(axi_interconnect_0_to_s01_couplers_RDATA),\n        .S_AXI_rid(axi_interconnect_0_to_s01_couplers_RID),\n        .S_AXI_rlast(axi_interconnect_0_to_s01_couplers_RLAST),\n        .S_AXI_rready(axi_interconnect_0_to_s01_couplers_RREADY),\n        .S_AXI_rresp(axi_interconnect_0_to_s01_couplers_RRESP),\n        .S_AXI_rvalid(axi_interconnect_0_to_s01_couplers_RVALID),\n        .S_AXI_wdata(axi_interconnect_0_to_s01_couplers_WDATA),\n        .S_AXI_wlast(axi_interconnect_0_to_s01_couplers_WLAST),\n        .S_AXI_wready(axi_interconnect_0_to_s01_couplers_WREADY),\n        .S_AXI_wstrb(axi_interconnect_0_to_s01_couplers_WSTRB),\n        .S_AXI_wvalid(axi_interconnect_0_to_s01_couplers_WVALID));\n  cl_axi_interconnect_xbar_0 xbar\n       (.aclk(axi_interconnect_0_ACLK_net),\n        .aresetn(axi_interconnect_0_ARESETN_net),\n        .m_axi_araddr({xbar_to_m03_couplers_ARADDR,xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),\n        .m_axi_arburst({xbar_to_m03_couplers_ARBURST,xbar_to_m02_couplers_ARBURST,xbar_to_m01_couplers_ARBURST,xbar_to_m00_couplers_ARBURST}),\n        .m_axi_arcache({xbar_to_m03_couplers_ARCACHE,xbar_to_m02_couplers_ARCACHE,xbar_to_m01_couplers_ARCACHE,xbar_to_m00_couplers_ARCACHE}),\n        .m_axi_arid({xbar_to_m03_couplers_ARID,xbar_to_m02_couplers_ARID,xbar_to_m01_couplers_ARID,xbar_to_m00_couplers_ARID}),\n        .m_axi_arlen({xbar_to_m03_couplers_ARLEN,xbar_to_m02_couplers_ARLEN,xbar_to_m01_couplers_ARLEN,xbar_to_m00_couplers_ARLEN}),\n        .m_axi_arlock({xbar_to_m03_couplers_ARLOCK,xbar_to_m02_couplers_ARLOCK,xbar_to_m01_couplers_ARLOCK,xbar_to_m00_couplers_ARLOCK}),\n        .m_axi_arprot({xbar_to_m03_couplers_ARPROT,xbar_to_m02_couplers_ARPROT,xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}),\n        .m_axi_arqos({xbar_to_m03_couplers_ARQOS,xbar_to_m02_couplers_ARQOS,xbar_to_m01_couplers_ARQOS,xbar_to_m00_couplers_ARQOS}),\n        .m_axi_arready({xbar_to_m03_couplers_ARREADY,xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),\n        .m_axi_arregion({xbar_to_m03_couplers_ARREGION,xbar_to_m02_couplers_ARREGION,xbar_to_m01_couplers_ARREGION,xbar_to_m00_couplers_ARREGION}),\n        .m_axi_arsize({xbar_to_m03_couplers_ARSIZE,xbar_to_m02_couplers_ARSIZE,xbar_to_m01_couplers_ARSIZE,xbar_to_m00_couplers_ARSIZE}),\n        .m_axi_arvalid({xbar_to_m03_couplers_ARVALID,xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),\n        .m_axi_awaddr({xbar_to_m03_couplers_AWADDR,xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),\n        .m_axi_awburst({xbar_to_m03_couplers_AWBURST,xbar_to_m02_couplers_AWBURST,xbar_to_m01_couplers_AWBURST,xbar_to_m00_couplers_AWBURST}),\n        .m_axi_awcache({xbar_to_m03_couplers_AWCACHE,xbar_to_m02_couplers_AWCACHE,xbar_to_m01_couplers_AWCACHE,xbar_to_m00_couplers_AWCACHE}),\n        .m_axi_awid({xbar_to_m03_couplers_AWID,xbar_to_m02_couplers_AWID,xbar_to_m01_couplers_AWID,xbar_to_m00_couplers_AWID}),\n        .m_axi_awlen({xbar_to_m03_couplers_AWLEN,xbar_to_m02_couplers_AWLEN,xbar_to_m01_couplers_AWLEN,xbar_to_m00_couplers_AWLEN}),\n        .m_axi_awlock({xbar_to_m03_couplers_AWLOCK,xbar_to_m02_couplers_AWLOCK,xbar_to_m01_couplers_AWLOCK,xbar_to_m00_couplers_AWLOCK}),\n        .m_axi_awprot({xbar_to_m03_couplers_AWPROT,xbar_to_m02_couplers_AWPROT,xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}),\n        .m_axi_awqos({xbar_to_m03_couplers_AWQOS,xbar_to_m02_couplers_AWQOS,xbar_to_m01_couplers_AWQOS,xbar_to_m00_couplers_AWQOS}),\n        .m_axi_awready({xbar_to_m03_couplers_AWREADY,xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),\n        .m_axi_awregion({xbar_to_m03_couplers_AWREGION,xbar_to_m02_couplers_AWREGION,xbar_to_m01_couplers_AWREGION,xbar_to_m00_couplers_AWREGION}),\n        .m_axi_awsize({xbar_to_m03_couplers_AWSIZE,xbar_to_m02_couplers_AWSIZE,xbar_to_m01_couplers_AWSIZE,xbar_to_m00_couplers_AWSIZE}),\n        .m_axi_awvalid({xbar_to_m03_couplers_AWVALID,xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),\n        .m_axi_bid({xbar_to_m03_couplers_BID,xbar_to_m02_couplers_BID,xbar_to_m01_couplers_BID,xbar_to_m00_couplers_BID}),\n        .m_axi_bready({xbar_to_m03_couplers_BREADY,xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),\n        .m_axi_bresp({xbar_to_m03_couplers_BRESP,xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),\n        .m_axi_bvalid({xbar_to_m03_couplers_BVALID,xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),\n        .m_axi_rdata({xbar_to_m03_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),\n        .m_axi_rid({xbar_to_m03_couplers_RID,xbar_to_m02_couplers_RID,xbar_to_m01_couplers_RID,xbar_to_m00_couplers_RID}),\n        .m_axi_rlast({xbar_to_m03_couplers_RLAST,xbar_to_m02_couplers_RLAST,xbar_to_m01_couplers_RLAST,xbar_to_m00_couplers_RLAST}),\n        .m_axi_rready({xbar_to_m03_couplers_RREADY,xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),\n        .m_axi_rresp({xbar_to_m03_couplers_RRESP,xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),\n        .m_axi_rvalid({xbar_to_m03_couplers_RVALID,xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),\n        .m_axi_wdata({xbar_to_m03_couplers_WDATA,xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),\n        .m_axi_wlast({xbar_to_m03_couplers_WLAST,xbar_to_m02_couplers_WLAST,xbar_to_m01_couplers_WLAST,xbar_to_m00_couplers_WLAST}),\n        .m_axi_wready({xbar_to_m03_couplers_WREADY,xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),\n        .m_axi_wstrb({xbar_to_m03_couplers_WSTRB,xbar_to_m02_couplers_WSTRB,xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),\n        .m_axi_wvalid({xbar_to_m03_couplers_WVALID,xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),\n        .s_axi_araddr({s01_couplers_to_xbar_ARADDR,s00_couplers_to_xbar_ARADDR}),\n        .s_axi_arburst({s01_couplers_to_xbar_ARBURST,s00_couplers_to_xbar_ARBURST}),\n        .s_axi_arcache({s01_couplers_to_xbar_ARCACHE,s00_couplers_to_xbar_ARCACHE}),\n        .s_axi_arid({1'b0,s01_couplers_to_xbar_ARID,1'b0,s00_couplers_to_xbar_ARID}),\n        .s_axi_arlen({s01_couplers_to_xbar_ARLEN,s00_couplers_to_xbar_ARLEN}),\n        .s_axi_arlock({s01_couplers_to_xbar_ARLOCK,s00_couplers_to_xbar_ARLOCK}),\n        .s_axi_arprot({s01_couplers_to_xbar_ARPROT,s00_couplers_to_xbar_ARPROT}),\n        .s_axi_arqos({s01_couplers_to_xbar_ARQOS,s00_couplers_to_xbar_ARQOS}),\n        .s_axi_arready({s01_couplers_to_xbar_ARREADY,s00_couplers_to_xbar_ARREADY}),\n        .s_axi_arsize({s01_couplers_to_xbar_ARSIZE,s00_couplers_to_xbar_ARSIZE}),\n        .s_axi_arvalid({s01_couplers_to_xbar_ARVALID,s00_couplers_to_xbar_ARVALID}),\n        .s_axi_awaddr({s01_couplers_to_xbar_AWADDR,s00_couplers_to_xbar_AWADDR}),\n        .s_axi_awburst({s01_couplers_to_xbar_AWBURST,s00_couplers_to_xbar_AWBURST}),\n        .s_axi_awcache({s01_couplers_to_xbar_AWCACHE,s00_couplers_to_xbar_AWCACHE}),\n        .s_axi_awid({1'b0,s01_couplers_to_xbar_AWID,1'b0,s00_couplers_to_xbar_AWID}),\n        .s_axi_awlen({s01_couplers_to_xbar_AWLEN,s00_couplers_to_xbar_AWLEN}),\n        .s_axi_awlock({s01_couplers_to_xbar_AWLOCK,s00_couplers_to_xbar_AWLOCK}),\n        .s_axi_awprot({s01_couplers_to_xbar_AWPROT,s00_couplers_to_xbar_AWPROT}),\n        .s_axi_awqos({s01_couplers_to_xbar_AWQOS,s00_couplers_to_xbar_AWQOS}),\n        .s_axi_awready({s01_couplers_to_xbar_AWREADY,s00_couplers_to_xbar_AWREADY}),\n        .s_axi_awsize({s01_couplers_to_xbar_AWSIZE,s00_couplers_to_xbar_AWSIZE}),\n        .s_axi_awvalid({s01_couplers_to_xbar_AWVALID,s00_couplers_to_xbar_AWVALID}),\n        .s_axi_bid({s01_couplers_to_xbar_BID,s00_couplers_to_xbar_BID}),\n        .s_axi_bready({s01_couplers_to_xbar_BREADY,s00_couplers_to_xbar_BREADY}),\n        .s_axi_bresp({s01_couplers_to_xbar_BRESP,s00_couplers_to_xbar_BRESP}),\n        .s_axi_bvalid({s01_couplers_to_xbar_BVALID,s00_couplers_to_xbar_BVALID}),\n        .s_axi_rdata({s01_couplers_to_xbar_RDATA,s00_couplers_to_xbar_RDATA}),\n        .s_axi_rid({s01_couplers_to_xbar_RID,s00_couplers_to_xbar_RID}),\n        .s_axi_rlast({s01_couplers_to_xbar_RLAST,s00_couplers_to_xbar_RLAST}),\n        .s_axi_rready({s01_couplers_to_xbar_RREADY,s00_couplers_to_xbar_RREADY}),\n        .s_axi_rresp({s01_couplers_to_xbar_RRESP,s00_couplers_to_xbar_RRESP}),\n        .s_axi_rvalid({s01_couplers_to_xbar_RVALID,s00_couplers_to_xbar_RVALID}),\n        .s_axi_wdata({s01_couplers_to_xbar_WDATA,s00_couplers_to_xbar_WDATA}),\n        .s_axi_wlast({s01_couplers_to_xbar_WLAST,s00_couplers_to_xbar_WLAST}),\n        .s_axi_wready({s01_couplers_to_xbar_WREADY,s00_couplers_to_xbar_WREADY}),\n        .s_axi_wstrb({s01_couplers_to_xbar_WSTRB,s00_couplers_to_xbar_WSTRB}),\n        .s_axi_wvalid({s01_couplers_to_xbar_WVALID,s00_couplers_to_xbar_WVALID}));\nendmodule\n\nmodule m00_couplers_imp_1QBJ6U2\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m00_couplers_to_m00_regslice_ARADDR;\n  wire [1:0]m00_couplers_to_m00_regslice_ARBURST;\n  wire [3:0]m00_couplers_to_m00_regslice_ARCACHE;\n  wire [6:0]m00_couplers_to_m00_regslice_ARID;\n  wire [7:0]m00_couplers_to_m00_regslice_ARLEN;\n  wire [0:0]m00_couplers_to_m00_regslice_ARLOCK;\n  wire [2:0]m00_couplers_to_m00_regslice_ARPROT;\n  wire [3:0]m00_couplers_to_m00_regslice_ARQOS;\n  wire m00_couplers_to_m00_regslice_ARREADY;\n  wire [3:0]m00_couplers_to_m00_regslice_ARREGION;\n  wire [2:0]m00_couplers_to_m00_regslice_ARSIZE;\n  wire m00_couplers_to_m00_regslice_ARVALID;\n  wire [63:0]m00_couplers_to_m00_regslice_AWADDR;\n  wire [1:0]m00_couplers_to_m00_regslice_AWBURST;\n  wire [3:0]m00_couplers_to_m00_regslice_AWCACHE;\n  wire [6:0]m00_couplers_to_m00_regslice_AWID;\n  wire [7:0]m00_couplers_to_m00_regslice_AWLEN;\n  wire [0:0]m00_couplers_to_m00_regslice_AWLOCK;\n  wire [2:0]m00_couplers_to_m00_regslice_AWPROT;\n  wire [3:0]m00_couplers_to_m00_regslice_AWQOS;\n  wire m00_couplers_to_m00_regslice_AWREADY;\n  wire [3:0]m00_couplers_to_m00_regslice_AWREGION;\n  wire [2:0]m00_couplers_to_m00_regslice_AWSIZE;\n  wire m00_couplers_to_m00_regslice_AWVALID;\n  wire [6:0]m00_couplers_to_m00_regslice_BID;\n  wire m00_couplers_to_m00_regslice_BREADY;\n  wire [1:0]m00_couplers_to_m00_regslice_BRESP;\n  wire m00_couplers_to_m00_regslice_BVALID;\n  wire [511:0]m00_couplers_to_m00_regslice_RDATA;\n  wire [6:0]m00_couplers_to_m00_regslice_RID;\n  wire m00_couplers_to_m00_regslice_RLAST;\n  wire m00_couplers_to_m00_regslice_RREADY;\n  wire [1:0]m00_couplers_to_m00_regslice_RRESP;\n  wire m00_couplers_to_m00_regslice_RVALID;\n  wire [511:0]m00_couplers_to_m00_regslice_WDATA;\n  wire m00_couplers_to_m00_regslice_WLAST;\n  wire m00_couplers_to_m00_regslice_WREADY;\n  wire [63:0]m00_couplers_to_m00_regslice_WSTRB;\n  wire m00_couplers_to_m00_regslice_WVALID;\n  wire [63:0]m00_regslice_to_m00_couplers_ARADDR;\n  wire [1:0]m00_regslice_to_m00_couplers_ARBURST;\n  wire [3:0]m00_regslice_to_m00_couplers_ARCACHE;\n  wire [6:0]m00_regslice_to_m00_couplers_ARID;\n  wire [7:0]m00_regslice_to_m00_couplers_ARLEN;\n  wire [0:0]m00_regslice_to_m00_couplers_ARLOCK;\n  wire [2:0]m00_regslice_to_m00_couplers_ARPROT;\n  wire [3:0]m00_regslice_to_m00_couplers_ARQOS;\n  wire m00_regslice_to_m00_couplers_ARREADY;\n  wire [3:0]m00_regslice_to_m00_couplers_ARREGION;\n  wire [2:0]m00_regslice_to_m00_couplers_ARSIZE;\n  wire m00_regslice_to_m00_couplers_ARVALID;\n  wire [63:0]m00_regslice_to_m00_couplers_AWADDR;\n  wire [1:0]m00_regslice_to_m00_couplers_AWBURST;\n  wire [3:0]m00_regslice_to_m00_couplers_AWCACHE;\n  wire [6:0]m00_regslice_to_m00_couplers_AWID;\n  wire [7:0]m00_regslice_to_m00_couplers_AWLEN;\n  wire [0:0]m00_regslice_to_m00_couplers_AWLOCK;\n  wire [2:0]m00_regslice_to_m00_couplers_AWPROT;\n  wire [3:0]m00_regslice_to_m00_couplers_AWQOS;\n  wire m00_regslice_to_m00_couplers_AWREADY;\n  wire [3:0]m00_regslice_to_m00_couplers_AWREGION;\n  wire [2:0]m00_regslice_to_m00_couplers_AWSIZE;\n  wire m00_regslice_to_m00_couplers_AWVALID;\n  wire [6:0]m00_regslice_to_m00_couplers_BID;\n  wire m00_regslice_to_m00_couplers_BREADY;\n  wire [1:0]m00_regslice_to_m00_couplers_BRESP;\n  wire m00_regslice_to_m00_couplers_BVALID;\n  wire [511:0]m00_regslice_to_m00_couplers_RDATA;\n  wire [6:0]m00_regslice_to_m00_couplers_RID;\n  wire m00_regslice_to_m00_couplers_RLAST;\n  wire m00_regslice_to_m00_couplers_RREADY;\n  wire [1:0]m00_regslice_to_m00_couplers_RRESP;\n  wire m00_regslice_to_m00_couplers_RVALID;\n  wire [511:0]m00_regslice_to_m00_couplers_WDATA;\n  wire m00_regslice_to_m00_couplers_WLAST;\n  wire m00_regslice_to_m00_couplers_WREADY;\n  wire [63:0]m00_regslice_to_m00_couplers_WSTRB;\n  wire m00_regslice_to_m00_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m00_regslice_to_m00_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m00_regslice_to_m00_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m00_regslice_to_m00_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m00_regslice_to_m00_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m00_regslice_to_m00_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m00_regslice_to_m00_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m00_regslice_to_m00_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m00_regslice_to_m00_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m00_regslice_to_m00_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m00_regslice_to_m00_couplers_ARSIZE;\n  assign M_AXI_arvalid = m00_regslice_to_m00_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m00_regslice_to_m00_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m00_regslice_to_m00_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m00_regslice_to_m00_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m00_regslice_to_m00_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m00_regslice_to_m00_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m00_regslice_to_m00_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m00_regslice_to_m00_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m00_regslice_to_m00_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m00_regslice_to_m00_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m00_regslice_to_m00_couplers_AWSIZE;\n  assign M_AXI_awvalid = m00_regslice_to_m00_couplers_AWVALID;\n  assign M_AXI_bready = m00_regslice_to_m00_couplers_BREADY;\n  assign M_AXI_rready = m00_regslice_to_m00_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m00_regslice_to_m00_couplers_WDATA;\n  assign M_AXI_wlast = m00_regslice_to_m00_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m00_regslice_to_m00_couplers_WSTRB;\n  assign M_AXI_wvalid = m00_regslice_to_m00_couplers_WVALID;\n  assign S_AXI_arready = m00_couplers_to_m00_regslice_ARREADY;\n  assign S_AXI_awready = m00_couplers_to_m00_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m00_couplers_to_m00_regslice_BID;\n  assign S_AXI_bresp[1:0] = m00_couplers_to_m00_regslice_BRESP;\n  assign S_AXI_bvalid = m00_couplers_to_m00_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m00_couplers_to_m00_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m00_couplers_to_m00_regslice_RID;\n  assign S_AXI_rlast = m00_couplers_to_m00_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m00_couplers_to_m00_regslice_RRESP;\n  assign S_AXI_rvalid = m00_couplers_to_m00_regslice_RVALID;\n  assign S_AXI_wready = m00_couplers_to_m00_regslice_WREADY;\n  assign m00_couplers_to_m00_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m00_couplers_to_m00_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m00_couplers_to_m00_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m00_couplers_to_m00_regslice_ARID = S_AXI_arid[6:0];\n  assign m00_couplers_to_m00_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m00_couplers_to_m00_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m00_couplers_to_m00_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m00_couplers_to_m00_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m00_couplers_to_m00_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m00_couplers_to_m00_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m00_couplers_to_m00_regslice_ARVALID = S_AXI_arvalid;\n  assign m00_couplers_to_m00_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m00_couplers_to_m00_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m00_couplers_to_m00_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m00_couplers_to_m00_regslice_AWID = S_AXI_awid[6:0];\n  assign m00_couplers_to_m00_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m00_couplers_to_m00_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m00_couplers_to_m00_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m00_couplers_to_m00_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m00_couplers_to_m00_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m00_couplers_to_m00_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m00_couplers_to_m00_regslice_AWVALID = S_AXI_awvalid;\n  assign m00_couplers_to_m00_regslice_BREADY = S_AXI_bready;\n  assign m00_couplers_to_m00_regslice_RREADY = S_AXI_rready;\n  assign m00_couplers_to_m00_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m00_couplers_to_m00_regslice_WLAST = S_AXI_wlast;\n  assign m00_couplers_to_m00_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m00_couplers_to_m00_regslice_WVALID = S_AXI_wvalid;\n  assign m00_regslice_to_m00_couplers_ARREADY = M_AXI_arready;\n  assign m00_regslice_to_m00_couplers_AWREADY = M_AXI_awready;\n  assign m00_regslice_to_m00_couplers_BID = M_AXI_bid[6:0];\n  assign m00_regslice_to_m00_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m00_regslice_to_m00_couplers_BVALID = M_AXI_bvalid;\n  assign m00_regslice_to_m00_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m00_regslice_to_m00_couplers_RID = M_AXI_rid[6:0];\n  assign m00_regslice_to_m00_couplers_RLAST = M_AXI_rlast;\n  assign m00_regslice_to_m00_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m00_regslice_to_m00_couplers_RVALID = M_AXI_rvalid;\n  assign m00_regslice_to_m00_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m00_regslice_0 m00_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m00_regslice_to_m00_couplers_ARADDR),\n        .m_axi_arburst(m00_regslice_to_m00_couplers_ARBURST),\n        .m_axi_arcache(m00_regslice_to_m00_couplers_ARCACHE),\n        .m_axi_arid(m00_regslice_to_m00_couplers_ARID),\n        .m_axi_arlen(m00_regslice_to_m00_couplers_ARLEN),\n        .m_axi_arlock(m00_regslice_to_m00_couplers_ARLOCK),\n        .m_axi_arprot(m00_regslice_to_m00_couplers_ARPROT),\n        .m_axi_arqos(m00_regslice_to_m00_couplers_ARQOS),\n        .m_axi_arready(m00_regslice_to_m00_couplers_ARREADY),\n        .m_axi_arregion(m00_regslice_to_m00_couplers_ARREGION),\n        .m_axi_arsize(m00_regslice_to_m00_couplers_ARSIZE),\n        .m_axi_arvalid(m00_regslice_to_m00_couplers_ARVALID),\n        .m_axi_awaddr(m00_regslice_to_m00_couplers_AWADDR),\n        .m_axi_awburst(m00_regslice_to_m00_couplers_AWBURST),\n        .m_axi_awcache(m00_regslice_to_m00_couplers_AWCACHE),\n        .m_axi_awid(m00_regslice_to_m00_couplers_AWID),\n        .m_axi_awlen(m00_regslice_to_m00_couplers_AWLEN),\n        .m_axi_awlock(m00_regslice_to_m00_couplers_AWLOCK),\n        .m_axi_awprot(m00_regslice_to_m00_couplers_AWPROT),\n        .m_axi_awqos(m00_regslice_to_m00_couplers_AWQOS),\n        .m_axi_awready(m00_regslice_to_m00_couplers_AWREADY),\n        .m_axi_awregion(m00_regslice_to_m00_couplers_AWREGION),\n        .m_axi_awsize(m00_regslice_to_m00_couplers_AWSIZE),\n        .m_axi_awvalid(m00_regslice_to_m00_couplers_AWVALID),\n        .m_axi_bid(m00_regslice_to_m00_couplers_BID),\n        .m_axi_bready(m00_regslice_to_m00_couplers_BREADY),\n        .m_axi_bresp(m00_regslice_to_m00_couplers_BRESP),\n        .m_axi_bvalid(m00_regslice_to_m00_couplers_BVALID),\n        .m_axi_rdata(m00_regslice_to_m00_couplers_RDATA),\n        .m_axi_rid(m00_regslice_to_m00_couplers_RID),\n        .m_axi_rlast(m00_regslice_to_m00_couplers_RLAST),\n        .m_axi_rready(m00_regslice_to_m00_couplers_RREADY),\n        .m_axi_rresp(m00_regslice_to_m00_couplers_RRESP),\n        .m_axi_rvalid(m00_regslice_to_m00_couplers_RVALID),\n        .m_axi_wdata(m00_regslice_to_m00_couplers_WDATA),\n        .m_axi_wlast(m00_regslice_to_m00_couplers_WLAST),\n        .m_axi_wready(m00_regslice_to_m00_couplers_WREADY),\n        .m_axi_wstrb(m00_regslice_to_m00_couplers_WSTRB),\n        .m_axi_wvalid(m00_regslice_to_m00_couplers_WVALID),\n        .s_axi_araddr(m00_couplers_to_m00_regslice_ARADDR),\n        .s_axi_arburst(m00_couplers_to_m00_regslice_ARBURST),\n        .s_axi_arcache(m00_couplers_to_m00_regslice_ARCACHE),\n        .s_axi_arid(m00_couplers_to_m00_regslice_ARID),\n        .s_axi_arlen(m00_couplers_to_m00_regslice_ARLEN),\n        .s_axi_arlock(m00_couplers_to_m00_regslice_ARLOCK),\n        .s_axi_arprot(m00_couplers_to_m00_regslice_ARPROT),\n        .s_axi_arqos(m00_couplers_to_m00_regslice_ARQOS),\n        .s_axi_arready(m00_couplers_to_m00_regslice_ARREADY),\n        .s_axi_arregion(m00_couplers_to_m00_regslice_ARREGION),\n        .s_axi_arsize(m00_couplers_to_m00_regslice_ARSIZE),\n        .s_axi_arvalid(m00_couplers_to_m00_regslice_ARVALID),\n        .s_axi_awaddr(m00_couplers_to_m00_regslice_AWADDR),\n        .s_axi_awburst(m00_couplers_to_m00_regslice_AWBURST),\n        .s_axi_awcache(m00_couplers_to_m00_regslice_AWCACHE),\n        .s_axi_awid(m00_couplers_to_m00_regslice_AWID),\n        .s_axi_awlen(m00_couplers_to_m00_regslice_AWLEN),\n        .s_axi_awlock(m00_couplers_to_m00_regslice_AWLOCK),\n        .s_axi_awprot(m00_couplers_to_m00_regslice_AWPROT),\n        .s_axi_awqos(m00_couplers_to_m00_regslice_AWQOS),\n        .s_axi_awready(m00_couplers_to_m00_regslice_AWREADY),\n        .s_axi_awregion(m00_couplers_to_m00_regslice_AWREGION),\n        .s_axi_awsize(m00_couplers_to_m00_regslice_AWSIZE),\n        .s_axi_awvalid(m00_couplers_to_m00_regslice_AWVALID),\n        .s_axi_bid(m00_couplers_to_m00_regslice_BID),\n        .s_axi_bready(m00_couplers_to_m00_regslice_BREADY),\n        .s_axi_bresp(m00_couplers_to_m00_regslice_BRESP),\n        .s_axi_bvalid(m00_couplers_to_m00_regslice_BVALID),\n        .s_axi_rdata(m00_couplers_to_m00_regslice_RDATA),\n        .s_axi_rid(m00_couplers_to_m00_regslice_RID),\n        .s_axi_rlast(m00_couplers_to_m00_regslice_RLAST),\n        .s_axi_rready(m00_couplers_to_m00_regslice_RREADY),\n        .s_axi_rresp(m00_couplers_to_m00_regslice_RRESP),\n        .s_axi_rvalid(m00_couplers_to_m00_regslice_RVALID),\n        .s_axi_wdata(m00_couplers_to_m00_regslice_WDATA),\n        .s_axi_wlast(m00_couplers_to_m00_regslice_WLAST),\n        .s_axi_wready(m00_couplers_to_m00_regslice_WREADY),\n        .s_axi_wstrb(m00_couplers_to_m00_regslice_WSTRB),\n        .s_axi_wvalid(m00_couplers_to_m00_regslice_WVALID));\nendmodule\n\nmodule m01_couplers_imp_10IMR9A\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m01_couplers_to_m01_regslice_ARADDR;\n  wire [1:0]m01_couplers_to_m01_regslice_ARBURST;\n  wire [3:0]m01_couplers_to_m01_regslice_ARCACHE;\n  wire [6:0]m01_couplers_to_m01_regslice_ARID;\n  wire [7:0]m01_couplers_to_m01_regslice_ARLEN;\n  wire [0:0]m01_couplers_to_m01_regslice_ARLOCK;\n  wire [2:0]m01_couplers_to_m01_regslice_ARPROT;\n  wire [3:0]m01_couplers_to_m01_regslice_ARQOS;\n  wire m01_couplers_to_m01_regslice_ARREADY;\n  wire [3:0]m01_couplers_to_m01_regslice_ARREGION;\n  wire [2:0]m01_couplers_to_m01_regslice_ARSIZE;\n  wire m01_couplers_to_m01_regslice_ARVALID;\n  wire [63:0]m01_couplers_to_m01_regslice_AWADDR;\n  wire [1:0]m01_couplers_to_m01_regslice_AWBURST;\n  wire [3:0]m01_couplers_to_m01_regslice_AWCACHE;\n  wire [6:0]m01_couplers_to_m01_regslice_AWID;\n  wire [7:0]m01_couplers_to_m01_regslice_AWLEN;\n  wire [0:0]m01_couplers_to_m01_regslice_AWLOCK;\n  wire [2:0]m01_couplers_to_m01_regslice_AWPROT;\n  wire [3:0]m01_couplers_to_m01_regslice_AWQOS;\n  wire m01_couplers_to_m01_regslice_AWREADY;\n  wire [3:0]m01_couplers_to_m01_regslice_AWREGION;\n  wire [2:0]m01_couplers_to_m01_regslice_AWSIZE;\n  wire m01_couplers_to_m01_regslice_AWVALID;\n  wire [6:0]m01_couplers_to_m01_regslice_BID;\n  wire m01_couplers_to_m01_regslice_BREADY;\n  wire [1:0]m01_couplers_to_m01_regslice_BRESP;\n  wire m01_couplers_to_m01_regslice_BVALID;\n  wire [511:0]m01_couplers_to_m01_regslice_RDATA;\n  wire [6:0]m01_couplers_to_m01_regslice_RID;\n  wire m01_couplers_to_m01_regslice_RLAST;\n  wire m01_couplers_to_m01_regslice_RREADY;\n  wire [1:0]m01_couplers_to_m01_regslice_RRESP;\n  wire m01_couplers_to_m01_regslice_RVALID;\n  wire [511:0]m01_couplers_to_m01_regslice_WDATA;\n  wire m01_couplers_to_m01_regslice_WLAST;\n  wire m01_couplers_to_m01_regslice_WREADY;\n  wire [63:0]m01_couplers_to_m01_regslice_WSTRB;\n  wire m01_couplers_to_m01_regslice_WVALID;\n  wire [63:0]m01_regslice_to_m01_couplers_ARADDR;\n  wire [1:0]m01_regslice_to_m01_couplers_ARBURST;\n  wire [3:0]m01_regslice_to_m01_couplers_ARCACHE;\n  wire [6:0]m01_regslice_to_m01_couplers_ARID;\n  wire [7:0]m01_regslice_to_m01_couplers_ARLEN;\n  wire [0:0]m01_regslice_to_m01_couplers_ARLOCK;\n  wire [2:0]m01_regslice_to_m01_couplers_ARPROT;\n  wire [3:0]m01_regslice_to_m01_couplers_ARQOS;\n  wire m01_regslice_to_m01_couplers_ARREADY;\n  wire [3:0]m01_regslice_to_m01_couplers_ARREGION;\n  wire [2:0]m01_regslice_to_m01_couplers_ARSIZE;\n  wire m01_regslice_to_m01_couplers_ARVALID;\n  wire [63:0]m01_regslice_to_m01_couplers_AWADDR;\n  wire [1:0]m01_regslice_to_m01_couplers_AWBURST;\n  wire [3:0]m01_regslice_to_m01_couplers_AWCACHE;\n  wire [6:0]m01_regslice_to_m01_couplers_AWID;\n  wire [7:0]m01_regslice_to_m01_couplers_AWLEN;\n  wire [0:0]m01_regslice_to_m01_couplers_AWLOCK;\n  wire [2:0]m01_regslice_to_m01_couplers_AWPROT;\n  wire [3:0]m01_regslice_to_m01_couplers_AWQOS;\n  wire m01_regslice_to_m01_couplers_AWREADY;\n  wire [3:0]m01_regslice_to_m01_couplers_AWREGION;\n  wire [2:0]m01_regslice_to_m01_couplers_AWSIZE;\n  wire m01_regslice_to_m01_couplers_AWVALID;\n  wire [6:0]m01_regslice_to_m01_couplers_BID;\n  wire m01_regslice_to_m01_couplers_BREADY;\n  wire [1:0]m01_regslice_to_m01_couplers_BRESP;\n  wire m01_regslice_to_m01_couplers_BVALID;\n  wire [511:0]m01_regslice_to_m01_couplers_RDATA;\n  wire [6:0]m01_regslice_to_m01_couplers_RID;\n  wire m01_regslice_to_m01_couplers_RLAST;\n  wire m01_regslice_to_m01_couplers_RREADY;\n  wire [1:0]m01_regslice_to_m01_couplers_RRESP;\n  wire m01_regslice_to_m01_couplers_RVALID;\n  wire [511:0]m01_regslice_to_m01_couplers_WDATA;\n  wire m01_regslice_to_m01_couplers_WLAST;\n  wire m01_regslice_to_m01_couplers_WREADY;\n  wire [63:0]m01_regslice_to_m01_couplers_WSTRB;\n  wire m01_regslice_to_m01_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m01_regslice_to_m01_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m01_regslice_to_m01_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m01_regslice_to_m01_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m01_regslice_to_m01_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m01_regslice_to_m01_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m01_regslice_to_m01_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m01_regslice_to_m01_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m01_regslice_to_m01_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m01_regslice_to_m01_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m01_regslice_to_m01_couplers_ARSIZE;\n  assign M_AXI_arvalid = m01_regslice_to_m01_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m01_regslice_to_m01_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m01_regslice_to_m01_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m01_regslice_to_m01_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m01_regslice_to_m01_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m01_regslice_to_m01_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m01_regslice_to_m01_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m01_regslice_to_m01_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m01_regslice_to_m01_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m01_regslice_to_m01_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m01_regslice_to_m01_couplers_AWSIZE;\n  assign M_AXI_awvalid = m01_regslice_to_m01_couplers_AWVALID;\n  assign M_AXI_bready = m01_regslice_to_m01_couplers_BREADY;\n  assign M_AXI_rready = m01_regslice_to_m01_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m01_regslice_to_m01_couplers_WDATA;\n  assign M_AXI_wlast = m01_regslice_to_m01_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m01_regslice_to_m01_couplers_WSTRB;\n  assign M_AXI_wvalid = m01_regslice_to_m01_couplers_WVALID;\n  assign S_AXI_arready = m01_couplers_to_m01_regslice_ARREADY;\n  assign S_AXI_awready = m01_couplers_to_m01_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m01_couplers_to_m01_regslice_BID;\n  assign S_AXI_bresp[1:0] = m01_couplers_to_m01_regslice_BRESP;\n  assign S_AXI_bvalid = m01_couplers_to_m01_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m01_couplers_to_m01_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m01_couplers_to_m01_regslice_RID;\n  assign S_AXI_rlast = m01_couplers_to_m01_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m01_couplers_to_m01_regslice_RRESP;\n  assign S_AXI_rvalid = m01_couplers_to_m01_regslice_RVALID;\n  assign S_AXI_wready = m01_couplers_to_m01_regslice_WREADY;\n  assign m01_couplers_to_m01_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m01_couplers_to_m01_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m01_couplers_to_m01_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m01_couplers_to_m01_regslice_ARID = S_AXI_arid[6:0];\n  assign m01_couplers_to_m01_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m01_couplers_to_m01_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m01_couplers_to_m01_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m01_couplers_to_m01_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m01_couplers_to_m01_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m01_couplers_to_m01_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m01_couplers_to_m01_regslice_ARVALID = S_AXI_arvalid;\n  assign m01_couplers_to_m01_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m01_couplers_to_m01_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m01_couplers_to_m01_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m01_couplers_to_m01_regslice_AWID = S_AXI_awid[6:0];\n  assign m01_couplers_to_m01_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m01_couplers_to_m01_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m01_couplers_to_m01_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m01_couplers_to_m01_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m01_couplers_to_m01_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m01_couplers_to_m01_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m01_couplers_to_m01_regslice_AWVALID = S_AXI_awvalid;\n  assign m01_couplers_to_m01_regslice_BREADY = S_AXI_bready;\n  assign m01_couplers_to_m01_regslice_RREADY = S_AXI_rready;\n  assign m01_couplers_to_m01_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m01_couplers_to_m01_regslice_WLAST = S_AXI_wlast;\n  assign m01_couplers_to_m01_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m01_couplers_to_m01_regslice_WVALID = S_AXI_wvalid;\n  assign m01_regslice_to_m01_couplers_ARREADY = M_AXI_arready;\n  assign m01_regslice_to_m01_couplers_AWREADY = M_AXI_awready;\n  assign m01_regslice_to_m01_couplers_BID = M_AXI_bid[6:0];\n  assign m01_regslice_to_m01_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m01_regslice_to_m01_couplers_BVALID = M_AXI_bvalid;\n  assign m01_regslice_to_m01_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m01_regslice_to_m01_couplers_RID = M_AXI_rid[6:0];\n  assign m01_regslice_to_m01_couplers_RLAST = M_AXI_rlast;\n  assign m01_regslice_to_m01_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m01_regslice_to_m01_couplers_RVALID = M_AXI_rvalid;\n  assign m01_regslice_to_m01_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m01_regslice_0 m01_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m01_regslice_to_m01_couplers_ARADDR),\n        .m_axi_arburst(m01_regslice_to_m01_couplers_ARBURST),\n        .m_axi_arcache(m01_regslice_to_m01_couplers_ARCACHE),\n        .m_axi_arid(m01_regslice_to_m01_couplers_ARID),\n        .m_axi_arlen(m01_regslice_to_m01_couplers_ARLEN),\n        .m_axi_arlock(m01_regslice_to_m01_couplers_ARLOCK),\n        .m_axi_arprot(m01_regslice_to_m01_couplers_ARPROT),\n        .m_axi_arqos(m01_regslice_to_m01_couplers_ARQOS),\n        .m_axi_arready(m01_regslice_to_m01_couplers_ARREADY),\n        .m_axi_arregion(m01_regslice_to_m01_couplers_ARREGION),\n        .m_axi_arsize(m01_regslice_to_m01_couplers_ARSIZE),\n        .m_axi_arvalid(m01_regslice_to_m01_couplers_ARVALID),\n        .m_axi_awaddr(m01_regslice_to_m01_couplers_AWADDR),\n        .m_axi_awburst(m01_regslice_to_m01_couplers_AWBURST),\n        .m_axi_awcache(m01_regslice_to_m01_couplers_AWCACHE),\n        .m_axi_awid(m01_regslice_to_m01_couplers_AWID),\n        .m_axi_awlen(m01_regslice_to_m01_couplers_AWLEN),\n        .m_axi_awlock(m01_regslice_to_m01_couplers_AWLOCK),\n        .m_axi_awprot(m01_regslice_to_m01_couplers_AWPROT),\n        .m_axi_awqos(m01_regslice_to_m01_couplers_AWQOS),\n        .m_axi_awready(m01_regslice_to_m01_couplers_AWREADY),\n        .m_axi_awregion(m01_regslice_to_m01_couplers_AWREGION),\n        .m_axi_awsize(m01_regslice_to_m01_couplers_AWSIZE),\n        .m_axi_awvalid(m01_regslice_to_m01_couplers_AWVALID),\n        .m_axi_bid(m01_regslice_to_m01_couplers_BID),\n        .m_axi_bready(m01_regslice_to_m01_couplers_BREADY),\n        .m_axi_bresp(m01_regslice_to_m01_couplers_BRESP),\n        .m_axi_bvalid(m01_regslice_to_m01_couplers_BVALID),\n        .m_axi_rdata(m01_regslice_to_m01_couplers_RDATA),\n        .m_axi_rid(m01_regslice_to_m01_couplers_RID),\n        .m_axi_rlast(m01_regslice_to_m01_couplers_RLAST),\n        .m_axi_rready(m01_regslice_to_m01_couplers_RREADY),\n        .m_axi_rresp(m01_regslice_to_m01_couplers_RRESP),\n        .m_axi_rvalid(m01_regslice_to_m01_couplers_RVALID),\n        .m_axi_wdata(m01_regslice_to_m01_couplers_WDATA),\n        .m_axi_wlast(m01_regslice_to_m01_couplers_WLAST),\n        .m_axi_wready(m01_regslice_to_m01_couplers_WREADY),\n        .m_axi_wstrb(m01_regslice_to_m01_couplers_WSTRB),\n        .m_axi_wvalid(m01_regslice_to_m01_couplers_WVALID),\n        .s_axi_araddr(m01_couplers_to_m01_regslice_ARADDR),\n        .s_axi_arburst(m01_couplers_to_m01_regslice_ARBURST),\n        .s_axi_arcache(m01_couplers_to_m01_regslice_ARCACHE),\n        .s_axi_arid(m01_couplers_to_m01_regslice_ARID),\n        .s_axi_arlen(m01_couplers_to_m01_regslice_ARLEN),\n        .s_axi_arlock(m01_couplers_to_m01_regslice_ARLOCK),\n        .s_axi_arprot(m01_couplers_to_m01_regslice_ARPROT),\n        .s_axi_arqos(m01_couplers_to_m01_regslice_ARQOS),\n        .s_axi_arready(m01_couplers_to_m01_regslice_ARREADY),\n        .s_axi_arregion(m01_couplers_to_m01_regslice_ARREGION),\n        .s_axi_arsize(m01_couplers_to_m01_regslice_ARSIZE),\n        .s_axi_arvalid(m01_couplers_to_m01_regslice_ARVALID),\n        .s_axi_awaddr(m01_couplers_to_m01_regslice_AWADDR),\n        .s_axi_awburst(m01_couplers_to_m01_regslice_AWBURST),\n        .s_axi_awcache(m01_couplers_to_m01_regslice_AWCACHE),\n        .s_axi_awid(m01_couplers_to_m01_regslice_AWID),\n        .s_axi_awlen(m01_couplers_to_m01_regslice_AWLEN),\n        .s_axi_awlock(m01_couplers_to_m01_regslice_AWLOCK),\n        .s_axi_awprot(m01_couplers_to_m01_regslice_AWPROT),\n        .s_axi_awqos(m01_couplers_to_m01_regslice_AWQOS),\n        .s_axi_awready(m01_couplers_to_m01_regslice_AWREADY),\n        .s_axi_awregion(m01_couplers_to_m01_regslice_AWREGION),\n        .s_axi_awsize(m01_couplers_to_m01_regslice_AWSIZE),\n        .s_axi_awvalid(m01_couplers_to_m01_regslice_AWVALID),\n        .s_axi_bid(m01_couplers_to_m01_regslice_BID),\n        .s_axi_bready(m01_couplers_to_m01_regslice_BREADY),\n        .s_axi_bresp(m01_couplers_to_m01_regslice_BRESP),\n        .s_axi_bvalid(m01_couplers_to_m01_regslice_BVALID),\n        .s_axi_rdata(m01_couplers_to_m01_regslice_RDATA),\n        .s_axi_rid(m01_couplers_to_m01_regslice_RID),\n        .s_axi_rlast(m01_couplers_to_m01_regslice_RLAST),\n        .s_axi_rready(m01_couplers_to_m01_regslice_RREADY),\n        .s_axi_rresp(m01_couplers_to_m01_regslice_RRESP),\n        .s_axi_rvalid(m01_couplers_to_m01_regslice_RVALID),\n        .s_axi_wdata(m01_couplers_to_m01_regslice_WDATA),\n        .s_axi_wlast(m01_couplers_to_m01_regslice_WLAST),\n        .s_axi_wready(m01_couplers_to_m01_regslice_WREADY),\n        .s_axi_wstrb(m01_couplers_to_m01_regslice_WSTRB),\n        .s_axi_wvalid(m01_couplers_to_m01_regslice_WVALID));\nendmodule\n\nmodule m02_couplers_imp_APDUS2\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m02_couplers_to_m02_regslice_ARADDR;\n  wire [1:0]m02_couplers_to_m02_regslice_ARBURST;\n  wire [3:0]m02_couplers_to_m02_regslice_ARCACHE;\n  wire [6:0]m02_couplers_to_m02_regslice_ARID;\n  wire [7:0]m02_couplers_to_m02_regslice_ARLEN;\n  wire [0:0]m02_couplers_to_m02_regslice_ARLOCK;\n  wire [2:0]m02_couplers_to_m02_regslice_ARPROT;\n  wire [3:0]m02_couplers_to_m02_regslice_ARQOS;\n  wire m02_couplers_to_m02_regslice_ARREADY;\n  wire [3:0]m02_couplers_to_m02_regslice_ARREGION;\n  wire [2:0]m02_couplers_to_m02_regslice_ARSIZE;\n  wire m02_couplers_to_m02_regslice_ARVALID;\n  wire [63:0]m02_couplers_to_m02_regslice_AWADDR;\n  wire [1:0]m02_couplers_to_m02_regslice_AWBURST;\n  wire [3:0]m02_couplers_to_m02_regslice_AWCACHE;\n  wire [6:0]m02_couplers_to_m02_regslice_AWID;\n  wire [7:0]m02_couplers_to_m02_regslice_AWLEN;\n  wire [0:0]m02_couplers_to_m02_regslice_AWLOCK;\n  wire [2:0]m02_couplers_to_m02_regslice_AWPROT;\n  wire [3:0]m02_couplers_to_m02_regslice_AWQOS;\n  wire m02_couplers_to_m02_regslice_AWREADY;\n  wire [3:0]m02_couplers_to_m02_regslice_AWREGION;\n  wire [2:0]m02_couplers_to_m02_regslice_AWSIZE;\n  wire m02_couplers_to_m02_regslice_AWVALID;\n  wire [6:0]m02_couplers_to_m02_regslice_BID;\n  wire m02_couplers_to_m02_regslice_BREADY;\n  wire [1:0]m02_couplers_to_m02_regslice_BRESP;\n  wire m02_couplers_to_m02_regslice_BVALID;\n  wire [511:0]m02_couplers_to_m02_regslice_RDATA;\n  wire [6:0]m02_couplers_to_m02_regslice_RID;\n  wire m02_couplers_to_m02_regslice_RLAST;\n  wire m02_couplers_to_m02_regslice_RREADY;\n  wire [1:0]m02_couplers_to_m02_regslice_RRESP;\n  wire m02_couplers_to_m02_regslice_RVALID;\n  wire [511:0]m02_couplers_to_m02_regslice_WDATA;\n  wire m02_couplers_to_m02_regslice_WLAST;\n  wire m02_couplers_to_m02_regslice_WREADY;\n  wire [63:0]m02_couplers_to_m02_regslice_WSTRB;\n  wire m02_couplers_to_m02_regslice_WVALID;\n  wire [63:0]m02_regslice_to_m02_couplers_ARADDR;\n  wire [1:0]m02_regslice_to_m02_couplers_ARBURST;\n  wire [3:0]m02_regslice_to_m02_couplers_ARCACHE;\n  wire [6:0]m02_regslice_to_m02_couplers_ARID;\n  wire [7:0]m02_regslice_to_m02_couplers_ARLEN;\n  wire [0:0]m02_regslice_to_m02_couplers_ARLOCK;\n  wire [2:0]m02_regslice_to_m02_couplers_ARPROT;\n  wire [3:0]m02_regslice_to_m02_couplers_ARQOS;\n  wire m02_regslice_to_m02_couplers_ARREADY;\n  wire [3:0]m02_regslice_to_m02_couplers_ARREGION;\n  wire [2:0]m02_regslice_to_m02_couplers_ARSIZE;\n  wire m02_regslice_to_m02_couplers_ARVALID;\n  wire [63:0]m02_regslice_to_m02_couplers_AWADDR;\n  wire [1:0]m02_regslice_to_m02_couplers_AWBURST;\n  wire [3:0]m02_regslice_to_m02_couplers_AWCACHE;\n  wire [6:0]m02_regslice_to_m02_couplers_AWID;\n  wire [7:0]m02_regslice_to_m02_couplers_AWLEN;\n  wire [0:0]m02_regslice_to_m02_couplers_AWLOCK;\n  wire [2:0]m02_regslice_to_m02_couplers_AWPROT;\n  wire [3:0]m02_regslice_to_m02_couplers_AWQOS;\n  wire m02_regslice_to_m02_couplers_AWREADY;\n  wire [3:0]m02_regslice_to_m02_couplers_AWREGION;\n  wire [2:0]m02_regslice_to_m02_couplers_AWSIZE;\n  wire m02_regslice_to_m02_couplers_AWVALID;\n  wire [6:0]m02_regslice_to_m02_couplers_BID;\n  wire m02_regslice_to_m02_couplers_BREADY;\n  wire [1:0]m02_regslice_to_m02_couplers_BRESP;\n  wire m02_regslice_to_m02_couplers_BVALID;\n  wire [511:0]m02_regslice_to_m02_couplers_RDATA;\n  wire [6:0]m02_regslice_to_m02_couplers_RID;\n  wire m02_regslice_to_m02_couplers_RLAST;\n  wire m02_regslice_to_m02_couplers_RREADY;\n  wire [1:0]m02_regslice_to_m02_couplers_RRESP;\n  wire m02_regslice_to_m02_couplers_RVALID;\n  wire [511:0]m02_regslice_to_m02_couplers_WDATA;\n  wire m02_regslice_to_m02_couplers_WLAST;\n  wire m02_regslice_to_m02_couplers_WREADY;\n  wire [63:0]m02_regslice_to_m02_couplers_WSTRB;\n  wire m02_regslice_to_m02_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m02_regslice_to_m02_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m02_regslice_to_m02_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m02_regslice_to_m02_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m02_regslice_to_m02_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m02_regslice_to_m02_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m02_regslice_to_m02_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m02_regslice_to_m02_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m02_regslice_to_m02_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m02_regslice_to_m02_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m02_regslice_to_m02_couplers_ARSIZE;\n  assign M_AXI_arvalid = m02_regslice_to_m02_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m02_regslice_to_m02_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m02_regslice_to_m02_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m02_regslice_to_m02_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m02_regslice_to_m02_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m02_regslice_to_m02_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m02_regslice_to_m02_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m02_regslice_to_m02_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m02_regslice_to_m02_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m02_regslice_to_m02_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m02_regslice_to_m02_couplers_AWSIZE;\n  assign M_AXI_awvalid = m02_regslice_to_m02_couplers_AWVALID;\n  assign M_AXI_bready = m02_regslice_to_m02_couplers_BREADY;\n  assign M_AXI_rready = m02_regslice_to_m02_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m02_regslice_to_m02_couplers_WDATA;\n  assign M_AXI_wlast = m02_regslice_to_m02_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m02_regslice_to_m02_couplers_WSTRB;\n  assign M_AXI_wvalid = m02_regslice_to_m02_couplers_WVALID;\n  assign S_AXI_arready = m02_couplers_to_m02_regslice_ARREADY;\n  assign S_AXI_awready = m02_couplers_to_m02_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m02_couplers_to_m02_regslice_BID;\n  assign S_AXI_bresp[1:0] = m02_couplers_to_m02_regslice_BRESP;\n  assign S_AXI_bvalid = m02_couplers_to_m02_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m02_couplers_to_m02_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m02_couplers_to_m02_regslice_RID;\n  assign S_AXI_rlast = m02_couplers_to_m02_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m02_couplers_to_m02_regslice_RRESP;\n  assign S_AXI_rvalid = m02_couplers_to_m02_regslice_RVALID;\n  assign S_AXI_wready = m02_couplers_to_m02_regslice_WREADY;\n  assign m02_couplers_to_m02_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m02_couplers_to_m02_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m02_couplers_to_m02_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m02_couplers_to_m02_regslice_ARID = S_AXI_arid[6:0];\n  assign m02_couplers_to_m02_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m02_couplers_to_m02_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m02_couplers_to_m02_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m02_couplers_to_m02_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m02_couplers_to_m02_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m02_couplers_to_m02_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m02_couplers_to_m02_regslice_ARVALID = S_AXI_arvalid;\n  assign m02_couplers_to_m02_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m02_couplers_to_m02_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m02_couplers_to_m02_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m02_couplers_to_m02_regslice_AWID = S_AXI_awid[6:0];\n  assign m02_couplers_to_m02_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m02_couplers_to_m02_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m02_couplers_to_m02_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m02_couplers_to_m02_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m02_couplers_to_m02_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m02_couplers_to_m02_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m02_couplers_to_m02_regslice_AWVALID = S_AXI_awvalid;\n  assign m02_couplers_to_m02_regslice_BREADY = S_AXI_bready;\n  assign m02_couplers_to_m02_regslice_RREADY = S_AXI_rready;\n  assign m02_couplers_to_m02_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m02_couplers_to_m02_regslice_WLAST = S_AXI_wlast;\n  assign m02_couplers_to_m02_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m02_couplers_to_m02_regslice_WVALID = S_AXI_wvalid;\n  assign m02_regslice_to_m02_couplers_ARREADY = M_AXI_arready;\n  assign m02_regslice_to_m02_couplers_AWREADY = M_AXI_awready;\n  assign m02_regslice_to_m02_couplers_BID = M_AXI_bid[6:0];\n  assign m02_regslice_to_m02_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m02_regslice_to_m02_couplers_BVALID = M_AXI_bvalid;\n  assign m02_regslice_to_m02_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m02_regslice_to_m02_couplers_RID = M_AXI_rid[6:0];\n  assign m02_regslice_to_m02_couplers_RLAST = M_AXI_rlast;\n  assign m02_regslice_to_m02_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m02_regslice_to_m02_couplers_RVALID = M_AXI_rvalid;\n  assign m02_regslice_to_m02_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m02_regslice_0 m02_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m02_regslice_to_m02_couplers_ARADDR),\n        .m_axi_arburst(m02_regslice_to_m02_couplers_ARBURST),\n        .m_axi_arcache(m02_regslice_to_m02_couplers_ARCACHE),\n        .m_axi_arid(m02_regslice_to_m02_couplers_ARID),\n        .m_axi_arlen(m02_regslice_to_m02_couplers_ARLEN),\n        .m_axi_arlock(m02_regslice_to_m02_couplers_ARLOCK),\n        .m_axi_arprot(m02_regslice_to_m02_couplers_ARPROT),\n        .m_axi_arqos(m02_regslice_to_m02_couplers_ARQOS),\n        .m_axi_arready(m02_regslice_to_m02_couplers_ARREADY),\n        .m_axi_arregion(m02_regslice_to_m02_couplers_ARREGION),\n        .m_axi_arsize(m02_regslice_to_m02_couplers_ARSIZE),\n        .m_axi_arvalid(m02_regslice_to_m02_couplers_ARVALID),\n        .m_axi_awaddr(m02_regslice_to_m02_couplers_AWADDR),\n        .m_axi_awburst(m02_regslice_to_m02_couplers_AWBURST),\n        .m_axi_awcache(m02_regslice_to_m02_couplers_AWCACHE),\n        .m_axi_awid(m02_regslice_to_m02_couplers_AWID),\n        .m_axi_awlen(m02_regslice_to_m02_couplers_AWLEN),\n        .m_axi_awlock(m02_regslice_to_m02_couplers_AWLOCK),\n        .m_axi_awprot(m02_regslice_to_m02_couplers_AWPROT),\n        .m_axi_awqos(m02_regslice_to_m02_couplers_AWQOS),\n        .m_axi_awready(m02_regslice_to_m02_couplers_AWREADY),\n        .m_axi_awregion(m02_regslice_to_m02_couplers_AWREGION),\n        .m_axi_awsize(m02_regslice_to_m02_couplers_AWSIZE),\n        .m_axi_awvalid(m02_regslice_to_m02_couplers_AWVALID),\n        .m_axi_bid(m02_regslice_to_m02_couplers_BID),\n        .m_axi_bready(m02_regslice_to_m02_couplers_BREADY),\n        .m_axi_bresp(m02_regslice_to_m02_couplers_BRESP),\n        .m_axi_bvalid(m02_regslice_to_m02_couplers_BVALID),\n        .m_axi_rdata(m02_regslice_to_m02_couplers_RDATA),\n        .m_axi_rid(m02_regslice_to_m02_couplers_RID),\n        .m_axi_rlast(m02_regslice_to_m02_couplers_RLAST),\n        .m_axi_rready(m02_regslice_to_m02_couplers_RREADY),\n        .m_axi_rresp(m02_regslice_to_m02_couplers_RRESP),\n        .m_axi_rvalid(m02_regslice_to_m02_couplers_RVALID),\n        .m_axi_wdata(m02_regslice_to_m02_couplers_WDATA),\n        .m_axi_wlast(m02_regslice_to_m02_couplers_WLAST),\n        .m_axi_wready(m02_regslice_to_m02_couplers_WREADY),\n        .m_axi_wstrb(m02_regslice_to_m02_couplers_WSTRB),\n        .m_axi_wvalid(m02_regslice_to_m02_couplers_WVALID),\n        .s_axi_araddr(m02_couplers_to_m02_regslice_ARADDR),\n        .s_axi_arburst(m02_couplers_to_m02_regslice_ARBURST),\n        .s_axi_arcache(m02_couplers_to_m02_regslice_ARCACHE),\n        .s_axi_arid(m02_couplers_to_m02_regslice_ARID),\n        .s_axi_arlen(m02_couplers_to_m02_regslice_ARLEN),\n        .s_axi_arlock(m02_couplers_to_m02_regslice_ARLOCK),\n        .s_axi_arprot(m02_couplers_to_m02_regslice_ARPROT),\n        .s_axi_arqos(m02_couplers_to_m02_regslice_ARQOS),\n        .s_axi_arready(m02_couplers_to_m02_regslice_ARREADY),\n        .s_axi_arregion(m02_couplers_to_m02_regslice_ARREGION),\n        .s_axi_arsize(m02_couplers_to_m02_regslice_ARSIZE),\n        .s_axi_arvalid(m02_couplers_to_m02_regslice_ARVALID),\n        .s_axi_awaddr(m02_couplers_to_m02_regslice_AWADDR),\n        .s_axi_awburst(m02_couplers_to_m02_regslice_AWBURST),\n        .s_axi_awcache(m02_couplers_to_m02_regslice_AWCACHE),\n        .s_axi_awid(m02_couplers_to_m02_regslice_AWID),\n        .s_axi_awlen(m02_couplers_to_m02_regslice_AWLEN),\n        .s_axi_awlock(m02_couplers_to_m02_regslice_AWLOCK),\n        .s_axi_awprot(m02_couplers_to_m02_regslice_AWPROT),\n        .s_axi_awqos(m02_couplers_to_m02_regslice_AWQOS),\n        .s_axi_awready(m02_couplers_to_m02_regslice_AWREADY),\n        .s_axi_awregion(m02_couplers_to_m02_regslice_AWREGION),\n        .s_axi_awsize(m02_couplers_to_m02_regslice_AWSIZE),\n        .s_axi_awvalid(m02_couplers_to_m02_regslice_AWVALID),\n        .s_axi_bid(m02_couplers_to_m02_regslice_BID),\n        .s_axi_bready(m02_couplers_to_m02_regslice_BREADY),\n        .s_axi_bresp(m02_couplers_to_m02_regslice_BRESP),\n        .s_axi_bvalid(m02_couplers_to_m02_regslice_BVALID),\n        .s_axi_rdata(m02_couplers_to_m02_regslice_RDATA),\n        .s_axi_rid(m02_couplers_to_m02_regslice_RID),\n        .s_axi_rlast(m02_couplers_to_m02_regslice_RLAST),\n        .s_axi_rready(m02_couplers_to_m02_regslice_RREADY),\n        .s_axi_rresp(m02_couplers_to_m02_regslice_RRESP),\n        .s_axi_rvalid(m02_couplers_to_m02_regslice_RVALID),\n        .s_axi_wdata(m02_couplers_to_m02_regslice_WDATA),\n        .s_axi_wlast(m02_couplers_to_m02_regslice_WLAST),\n        .s_axi_wready(m02_couplers_to_m02_regslice_WREADY),\n        .s_axi_wstrb(m02_couplers_to_m02_regslice_WSTRB),\n        .s_axi_wvalid(m02_couplers_to_m02_regslice_WVALID));\nendmodule\n\nmodule m03_couplers_imp_JAYOMU\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m03_couplers_to_m03_regslice_ARADDR;\n  wire [1:0]m03_couplers_to_m03_regslice_ARBURST;\n  wire [3:0]m03_couplers_to_m03_regslice_ARCACHE;\n  wire [6:0]m03_couplers_to_m03_regslice_ARID;\n  wire [7:0]m03_couplers_to_m03_regslice_ARLEN;\n  wire [0:0]m03_couplers_to_m03_regslice_ARLOCK;\n  wire [2:0]m03_couplers_to_m03_regslice_ARPROT;\n  wire [3:0]m03_couplers_to_m03_regslice_ARQOS;\n  wire m03_couplers_to_m03_regslice_ARREADY;\n  wire [3:0]m03_couplers_to_m03_regslice_ARREGION;\n  wire [2:0]m03_couplers_to_m03_regslice_ARSIZE;\n  wire m03_couplers_to_m03_regslice_ARVALID;\n  wire [63:0]m03_couplers_to_m03_regslice_AWADDR;\n  wire [1:0]m03_couplers_to_m03_regslice_AWBURST;\n  wire [3:0]m03_couplers_to_m03_regslice_AWCACHE;\n  wire [6:0]m03_couplers_to_m03_regslice_AWID;\n  wire [7:0]m03_couplers_to_m03_regslice_AWLEN;\n  wire [0:0]m03_couplers_to_m03_regslice_AWLOCK;\n  wire [2:0]m03_couplers_to_m03_regslice_AWPROT;\n  wire [3:0]m03_couplers_to_m03_regslice_AWQOS;\n  wire m03_couplers_to_m03_regslice_AWREADY;\n  wire [3:0]m03_couplers_to_m03_regslice_AWREGION;\n  wire [2:0]m03_couplers_to_m03_regslice_AWSIZE;\n  wire m03_couplers_to_m03_regslice_AWVALID;\n  wire [6:0]m03_couplers_to_m03_regslice_BID;\n  wire m03_couplers_to_m03_regslice_BREADY;\n  wire [1:0]m03_couplers_to_m03_regslice_BRESP;\n  wire m03_couplers_to_m03_regslice_BVALID;\n  wire [511:0]m03_couplers_to_m03_regslice_RDATA;\n  wire [6:0]m03_couplers_to_m03_regslice_RID;\n  wire m03_couplers_to_m03_regslice_RLAST;\n  wire m03_couplers_to_m03_regslice_RREADY;\n  wire [1:0]m03_couplers_to_m03_regslice_RRESP;\n  wire m03_couplers_to_m03_regslice_RVALID;\n  wire [511:0]m03_couplers_to_m03_regslice_WDATA;\n  wire m03_couplers_to_m03_regslice_WLAST;\n  wire m03_couplers_to_m03_regslice_WREADY;\n  wire [63:0]m03_couplers_to_m03_regslice_WSTRB;\n  wire m03_couplers_to_m03_regslice_WVALID;\n  wire [63:0]m03_regslice_to_m03_couplers_ARADDR;\n  wire [1:0]m03_regslice_to_m03_couplers_ARBURST;\n  wire [3:0]m03_regslice_to_m03_couplers_ARCACHE;\n  wire [6:0]m03_regslice_to_m03_couplers_ARID;\n  wire [7:0]m03_regslice_to_m03_couplers_ARLEN;\n  wire [0:0]m03_regslice_to_m03_couplers_ARLOCK;\n  wire [2:0]m03_regslice_to_m03_couplers_ARPROT;\n  wire [3:0]m03_regslice_to_m03_couplers_ARQOS;\n  wire m03_regslice_to_m03_couplers_ARREADY;\n  wire [3:0]m03_regslice_to_m03_couplers_ARREGION;\n  wire [2:0]m03_regslice_to_m03_couplers_ARSIZE;\n  wire m03_regslice_to_m03_couplers_ARVALID;\n  wire [63:0]m03_regslice_to_m03_couplers_AWADDR;\n  wire [1:0]m03_regslice_to_m03_couplers_AWBURST;\n  wire [3:0]m03_regslice_to_m03_couplers_AWCACHE;\n  wire [6:0]m03_regslice_to_m03_couplers_AWID;\n  wire [7:0]m03_regslice_to_m03_couplers_AWLEN;\n  wire [0:0]m03_regslice_to_m03_couplers_AWLOCK;\n  wire [2:0]m03_regslice_to_m03_couplers_AWPROT;\n  wire [3:0]m03_regslice_to_m03_couplers_AWQOS;\n  wire m03_regslice_to_m03_couplers_AWREADY;\n  wire [3:0]m03_regslice_to_m03_couplers_AWREGION;\n  wire [2:0]m03_regslice_to_m03_couplers_AWSIZE;\n  wire m03_regslice_to_m03_couplers_AWVALID;\n  wire [6:0]m03_regslice_to_m03_couplers_BID;\n  wire m03_regslice_to_m03_couplers_BREADY;\n  wire [1:0]m03_regslice_to_m03_couplers_BRESP;\n  wire m03_regslice_to_m03_couplers_BVALID;\n  wire [511:0]m03_regslice_to_m03_couplers_RDATA;\n  wire [6:0]m03_regslice_to_m03_couplers_RID;\n  wire m03_regslice_to_m03_couplers_RLAST;\n  wire m03_regslice_to_m03_couplers_RREADY;\n  wire [1:0]m03_regslice_to_m03_couplers_RRESP;\n  wire m03_regslice_to_m03_couplers_RVALID;\n  wire [511:0]m03_regslice_to_m03_couplers_WDATA;\n  wire m03_regslice_to_m03_couplers_WLAST;\n  wire m03_regslice_to_m03_couplers_WREADY;\n  wire [63:0]m03_regslice_to_m03_couplers_WSTRB;\n  wire m03_regslice_to_m03_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m03_regslice_to_m03_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m03_regslice_to_m03_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m03_regslice_to_m03_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m03_regslice_to_m03_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m03_regslice_to_m03_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m03_regslice_to_m03_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m03_regslice_to_m03_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m03_regslice_to_m03_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m03_regslice_to_m03_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m03_regslice_to_m03_couplers_ARSIZE;\n  assign M_AXI_arvalid = m03_regslice_to_m03_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m03_regslice_to_m03_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m03_regslice_to_m03_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m03_regslice_to_m03_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m03_regslice_to_m03_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m03_regslice_to_m03_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m03_regslice_to_m03_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m03_regslice_to_m03_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m03_regslice_to_m03_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m03_regslice_to_m03_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m03_regslice_to_m03_couplers_AWSIZE;\n  assign M_AXI_awvalid = m03_regslice_to_m03_couplers_AWVALID;\n  assign M_AXI_bready = m03_regslice_to_m03_couplers_BREADY;\n  assign M_AXI_rready = m03_regslice_to_m03_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m03_regslice_to_m03_couplers_WDATA;\n  assign M_AXI_wlast = m03_regslice_to_m03_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m03_regslice_to_m03_couplers_WSTRB;\n  assign M_AXI_wvalid = m03_regslice_to_m03_couplers_WVALID;\n  assign S_AXI_arready = m03_couplers_to_m03_regslice_ARREADY;\n  assign S_AXI_awready = m03_couplers_to_m03_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m03_couplers_to_m03_regslice_BID;\n  assign S_AXI_bresp[1:0] = m03_couplers_to_m03_regslice_BRESP;\n  assign S_AXI_bvalid = m03_couplers_to_m03_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m03_couplers_to_m03_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m03_couplers_to_m03_regslice_RID;\n  assign S_AXI_rlast = m03_couplers_to_m03_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m03_couplers_to_m03_regslice_RRESP;\n  assign S_AXI_rvalid = m03_couplers_to_m03_regslice_RVALID;\n  assign S_AXI_wready = m03_couplers_to_m03_regslice_WREADY;\n  assign m03_couplers_to_m03_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m03_couplers_to_m03_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m03_couplers_to_m03_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m03_couplers_to_m03_regslice_ARID = S_AXI_arid[6:0];\n  assign m03_couplers_to_m03_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m03_couplers_to_m03_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m03_couplers_to_m03_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m03_couplers_to_m03_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m03_couplers_to_m03_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m03_couplers_to_m03_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m03_couplers_to_m03_regslice_ARVALID = S_AXI_arvalid;\n  assign m03_couplers_to_m03_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m03_couplers_to_m03_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m03_couplers_to_m03_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m03_couplers_to_m03_regslice_AWID = S_AXI_awid[6:0];\n  assign m03_couplers_to_m03_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m03_couplers_to_m03_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m03_couplers_to_m03_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m03_couplers_to_m03_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m03_couplers_to_m03_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m03_couplers_to_m03_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m03_couplers_to_m03_regslice_AWVALID = S_AXI_awvalid;\n  assign m03_couplers_to_m03_regslice_BREADY = S_AXI_bready;\n  assign m03_couplers_to_m03_regslice_RREADY = S_AXI_rready;\n  assign m03_couplers_to_m03_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m03_couplers_to_m03_regslice_WLAST = S_AXI_wlast;\n  assign m03_couplers_to_m03_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m03_couplers_to_m03_regslice_WVALID = S_AXI_wvalid;\n  assign m03_regslice_to_m03_couplers_ARREADY = M_AXI_arready;\n  assign m03_regslice_to_m03_couplers_AWREADY = M_AXI_awready;\n  assign m03_regslice_to_m03_couplers_BID = M_AXI_bid[6:0];\n  assign m03_regslice_to_m03_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m03_regslice_to_m03_couplers_BVALID = M_AXI_bvalid;\n  assign m03_regslice_to_m03_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m03_regslice_to_m03_couplers_RID = M_AXI_rid[6:0];\n  assign m03_regslice_to_m03_couplers_RLAST = M_AXI_rlast;\n  assign m03_regslice_to_m03_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m03_regslice_to_m03_couplers_RVALID = M_AXI_rvalid;\n  assign m03_regslice_to_m03_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m03_regslice_0 m03_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m03_regslice_to_m03_couplers_ARADDR),\n        .m_axi_arburst(m03_regslice_to_m03_couplers_ARBURST),\n        .m_axi_arcache(m03_regslice_to_m03_couplers_ARCACHE),\n        .m_axi_arid(m03_regslice_to_m03_couplers_ARID),\n        .m_axi_arlen(m03_regslice_to_m03_couplers_ARLEN),\n        .m_axi_arlock(m03_regslice_to_m03_couplers_ARLOCK),\n        .m_axi_arprot(m03_regslice_to_m03_couplers_ARPROT),\n        .m_axi_arqos(m03_regslice_to_m03_couplers_ARQOS),\n        .m_axi_arready(m03_regslice_to_m03_couplers_ARREADY),\n        .m_axi_arregion(m03_regslice_to_m03_couplers_ARREGION),\n        .m_axi_arsize(m03_regslice_to_m03_couplers_ARSIZE),\n        .m_axi_arvalid(m03_regslice_to_m03_couplers_ARVALID),\n        .m_axi_awaddr(m03_regslice_to_m03_couplers_AWADDR),\n        .m_axi_awburst(m03_regslice_to_m03_couplers_AWBURST),\n        .m_axi_awcache(m03_regslice_to_m03_couplers_AWCACHE),\n        .m_axi_awid(m03_regslice_to_m03_couplers_AWID),\n        .m_axi_awlen(m03_regslice_to_m03_couplers_AWLEN),\n        .m_axi_awlock(m03_regslice_to_m03_couplers_AWLOCK),\n        .m_axi_awprot(m03_regslice_to_m03_couplers_AWPROT),\n        .m_axi_awqos(m03_regslice_to_m03_couplers_AWQOS),\n        .m_axi_awready(m03_regslice_to_m03_couplers_AWREADY),\n        .m_axi_awregion(m03_regslice_to_m03_couplers_AWREGION),\n        .m_axi_awsize(m03_regslice_to_m03_couplers_AWSIZE),\n        .m_axi_awvalid(m03_regslice_to_m03_couplers_AWVALID),\n        .m_axi_bid(m03_regslice_to_m03_couplers_BID),\n        .m_axi_bready(m03_regslice_to_m03_couplers_BREADY),\n        .m_axi_bresp(m03_regslice_to_m03_couplers_BRESP),\n        .m_axi_bvalid(m03_regslice_to_m03_couplers_BVALID),\n        .m_axi_rdata(m03_regslice_to_m03_couplers_RDATA),\n        .m_axi_rid(m03_regslice_to_m03_couplers_RID),\n        .m_axi_rlast(m03_regslice_to_m03_couplers_RLAST),\n        .m_axi_rready(m03_regslice_to_m03_couplers_RREADY),\n        .m_axi_rresp(m03_regslice_to_m03_couplers_RRESP),\n        .m_axi_rvalid(m03_regslice_to_m03_couplers_RVALID),\n        .m_axi_wdata(m03_regslice_to_m03_couplers_WDATA),\n        .m_axi_wlast(m03_regslice_to_m03_couplers_WLAST),\n        .m_axi_wready(m03_regslice_to_m03_couplers_WREADY),\n        .m_axi_wstrb(m03_regslice_to_m03_couplers_WSTRB),\n        .m_axi_wvalid(m03_regslice_to_m03_couplers_WVALID),\n        .s_axi_araddr(m03_couplers_to_m03_regslice_ARADDR),\n        .s_axi_arburst(m03_couplers_to_m03_regslice_ARBURST),\n        .s_axi_arcache(m03_couplers_to_m03_regslice_ARCACHE),\n        .s_axi_arid(m03_couplers_to_m03_regslice_ARID),\n        .s_axi_arlen(m03_couplers_to_m03_regslice_ARLEN),\n        .s_axi_arlock(m03_couplers_to_m03_regslice_ARLOCK),\n        .s_axi_arprot(m03_couplers_to_m03_regslice_ARPROT),\n        .s_axi_arqos(m03_couplers_to_m03_regslice_ARQOS),\n        .s_axi_arready(m03_couplers_to_m03_regslice_ARREADY),\n        .s_axi_arregion(m03_couplers_to_m03_regslice_ARREGION),\n        .s_axi_arsize(m03_couplers_to_m03_regslice_ARSIZE),\n        .s_axi_arvalid(m03_couplers_to_m03_regslice_ARVALID),\n        .s_axi_awaddr(m03_couplers_to_m03_regslice_AWADDR),\n        .s_axi_awburst(m03_couplers_to_m03_regslice_AWBURST),\n        .s_axi_awcache(m03_couplers_to_m03_regslice_AWCACHE),\n        .s_axi_awid(m03_couplers_to_m03_regslice_AWID),\n        .s_axi_awlen(m03_couplers_to_m03_regslice_AWLEN),\n        .s_axi_awlock(m03_couplers_to_m03_regslice_AWLOCK),\n        .s_axi_awprot(m03_couplers_to_m03_regslice_AWPROT),\n        .s_axi_awqos(m03_couplers_to_m03_regslice_AWQOS),\n        .s_axi_awready(m03_couplers_to_m03_regslice_AWREADY),\n        .s_axi_awregion(m03_couplers_to_m03_regslice_AWREGION),\n        .s_axi_awsize(m03_couplers_to_m03_regslice_AWSIZE),\n        .s_axi_awvalid(m03_couplers_to_m03_regslice_AWVALID),\n        .s_axi_bid(m03_couplers_to_m03_regslice_BID),\n        .s_axi_bready(m03_couplers_to_m03_regslice_BREADY),\n        .s_axi_bresp(m03_couplers_to_m03_regslice_BRESP),\n        .s_axi_bvalid(m03_couplers_to_m03_regslice_BVALID),\n        .s_axi_rdata(m03_couplers_to_m03_regslice_RDATA),\n        .s_axi_rid(m03_couplers_to_m03_regslice_RID),\n        .s_axi_rlast(m03_couplers_to_m03_regslice_RLAST),\n        .s_axi_rready(m03_couplers_to_m03_regslice_RREADY),\n        .s_axi_rresp(m03_couplers_to_m03_regslice_RRESP),\n        .s_axi_rvalid(m03_couplers_to_m03_regslice_RVALID),\n        .s_axi_wdata(m03_couplers_to_m03_regslice_WDATA),\n        .s_axi_wlast(m03_couplers_to_m03_regslice_WLAST),\n        .s_axi_wready(m03_couplers_to_m03_regslice_WREADY),\n        .s_axi_wstrb(m03_couplers_to_m03_regslice_WSTRB),\n        .s_axi_wvalid(m03_couplers_to_m03_regslice_WVALID));\nendmodule\n\nmodule s00_couplers_imp_QICM5G\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [5:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [5:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [5:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [5:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [5:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [5:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire S_ACLK_1;\n  wire S_ARESETN_1;\n  wire [63:0]s00_couplers_to_s00_regslice_ARADDR;\n  wire [1:0]s00_couplers_to_s00_regslice_ARBURST;\n  wire [3:0]s00_couplers_to_s00_regslice_ARCACHE;\n  wire [5:0]s00_couplers_to_s00_regslice_ARID;\n  wire [7:0]s00_couplers_to_s00_regslice_ARLEN;\n  wire [0:0]s00_couplers_to_s00_regslice_ARLOCK;\n  wire [2:0]s00_couplers_to_s00_regslice_ARPROT;\n  wire [3:0]s00_couplers_to_s00_regslice_ARQOS;\n  wire s00_couplers_to_s00_regslice_ARREADY;\n  wire [3:0]s00_couplers_to_s00_regslice_ARREGION;\n  wire [2:0]s00_couplers_to_s00_regslice_ARSIZE;\n  wire s00_couplers_to_s00_regslice_ARVALID;\n  wire [63:0]s00_couplers_to_s00_regslice_AWADDR;\n  wire [1:0]s00_couplers_to_s00_regslice_AWBURST;\n  wire [3:0]s00_couplers_to_s00_regslice_AWCACHE;\n  wire [5:0]s00_couplers_to_s00_regslice_AWID;\n  wire [7:0]s00_couplers_to_s00_regslice_AWLEN;\n  wire [0:0]s00_couplers_to_s00_regslice_AWLOCK;\n  wire [2:0]s00_couplers_to_s00_regslice_AWPROT;\n  wire [3:0]s00_couplers_to_s00_regslice_AWQOS;\n  wire s00_couplers_to_s00_regslice_AWREADY;\n  wire [3:0]s00_couplers_to_s00_regslice_AWREGION;\n  wire [2:0]s00_couplers_to_s00_regslice_AWSIZE;\n  wire s00_couplers_to_s00_regslice_AWVALID;\n  wire [5:0]s00_couplers_to_s00_regslice_BID;\n  wire s00_couplers_to_s00_regslice_BREADY;\n  wire [1:0]s00_couplers_to_s00_regslice_BRESP;\n  wire s00_couplers_to_s00_regslice_BVALID;\n  wire [511:0]s00_couplers_to_s00_regslice_RDATA;\n  wire [5:0]s00_couplers_to_s00_regslice_RID;\n  wire s00_couplers_to_s00_regslice_RLAST;\n  wire s00_couplers_to_s00_regslice_RREADY;\n  wire [1:0]s00_couplers_to_s00_regslice_RRESP;\n  wire s00_couplers_to_s00_regslice_RVALID;\n  wire [511:0]s00_couplers_to_s00_regslice_WDATA;\n  wire s00_couplers_to_s00_regslice_WLAST;\n  wire s00_couplers_to_s00_regslice_WREADY;\n  wire [63:0]s00_couplers_to_s00_regslice_WSTRB;\n  wire s00_couplers_to_s00_regslice_WVALID;\n  wire [63:0]s00_regslice_to_s00_couplers_ARADDR;\n  wire [1:0]s00_regslice_to_s00_couplers_ARBURST;\n  wire [3:0]s00_regslice_to_s00_couplers_ARCACHE;\n  wire [5:0]s00_regslice_to_s00_couplers_ARID;\n  wire [7:0]s00_regslice_to_s00_couplers_ARLEN;\n  wire [0:0]s00_regslice_to_s00_couplers_ARLOCK;\n  wire [2:0]s00_regslice_to_s00_couplers_ARPROT;\n  wire [3:0]s00_regslice_to_s00_couplers_ARQOS;\n  wire s00_regslice_to_s00_couplers_ARREADY;\n  wire [2:0]s00_regslice_to_s00_couplers_ARSIZE;\n  wire s00_regslice_to_s00_couplers_ARVALID;\n  wire [63:0]s00_regslice_to_s00_couplers_AWADDR;\n  wire [1:0]s00_regslice_to_s00_couplers_AWBURST;\n  wire [3:0]s00_regslice_to_s00_couplers_AWCACHE;\n  wire [5:0]s00_regslice_to_s00_couplers_AWID;\n  wire [7:0]s00_regslice_to_s00_couplers_AWLEN;\n  wire [0:0]s00_regslice_to_s00_couplers_AWLOCK;\n  wire [2:0]s00_regslice_to_s00_couplers_AWPROT;\n  wire [3:0]s00_regslice_to_s00_couplers_AWQOS;\n  wire s00_regslice_to_s00_couplers_AWREADY;\n  wire [2:0]s00_regslice_to_s00_couplers_AWSIZE;\n  wire s00_regslice_to_s00_couplers_AWVALID;\n  wire [6:0]s00_regslice_to_s00_couplers_BID;\n  wire s00_regslice_to_s00_couplers_BREADY;\n  wire [1:0]s00_regslice_to_s00_couplers_BRESP;\n  wire s00_regslice_to_s00_couplers_BVALID;\n  wire [511:0]s00_regslice_to_s00_couplers_RDATA;\n  wire [6:0]s00_regslice_to_s00_couplers_RID;\n  wire s00_regslice_to_s00_couplers_RLAST;\n  wire s00_regslice_to_s00_couplers_RREADY;\n  wire [1:0]s00_regslice_to_s00_couplers_RRESP;\n  wire s00_regslice_to_s00_couplers_RVALID;\n  wire [511:0]s00_regslice_to_s00_couplers_WDATA;\n  wire s00_regslice_to_s00_couplers_WLAST;\n  wire s00_regslice_to_s00_couplers_WREADY;\n  wire [63:0]s00_regslice_to_s00_couplers_WSTRB;\n  wire s00_regslice_to_s00_couplers_WVALID;\n\n  assign M_AXI_araddr[63:0] = s00_regslice_to_s00_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = s00_regslice_to_s00_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = s00_regslice_to_s00_couplers_ARCACHE;\n  assign M_AXI_arid[5:0] = s00_regslice_to_s00_couplers_ARID;\n  assign M_AXI_arlen[7:0] = s00_regslice_to_s00_couplers_ARLEN;\n  assign M_AXI_arlock[0] = s00_regslice_to_s00_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = s00_regslice_to_s00_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = s00_regslice_to_s00_couplers_ARQOS;\n  assign M_AXI_arsize[2:0] = s00_regslice_to_s00_couplers_ARSIZE;\n  assign M_AXI_arvalid = s00_regslice_to_s00_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = s00_regslice_to_s00_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = s00_regslice_to_s00_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = s00_regslice_to_s00_couplers_AWCACHE;\n  assign M_AXI_awid[5:0] = s00_regslice_to_s00_couplers_AWID;\n  assign M_AXI_awlen[7:0] = s00_regslice_to_s00_couplers_AWLEN;\n  assign M_AXI_awlock[0] = s00_regslice_to_s00_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = s00_regslice_to_s00_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = s00_regslice_to_s00_couplers_AWQOS;\n  assign M_AXI_awsize[2:0] = s00_regslice_to_s00_couplers_AWSIZE;\n  assign M_AXI_awvalid = s00_regslice_to_s00_couplers_AWVALID;\n  assign M_AXI_bready = s00_regslice_to_s00_couplers_BREADY;\n  assign M_AXI_rready = s00_regslice_to_s00_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = s00_regslice_to_s00_couplers_WDATA;\n  assign M_AXI_wlast = s00_regslice_to_s00_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = s00_regslice_to_s00_couplers_WSTRB;\n  assign M_AXI_wvalid = s00_regslice_to_s00_couplers_WVALID;\n  assign S_ACLK_1 = S_ACLK;\n  assign S_ARESETN_1 = S_ARESETN;\n  assign S_AXI_arready = s00_couplers_to_s00_regslice_ARREADY;\n  assign S_AXI_awready = s00_couplers_to_s00_regslice_AWREADY;\n  assign S_AXI_bid[5:0] = s00_couplers_to_s00_regslice_BID;\n  assign S_AXI_bresp[1:0] = s00_couplers_to_s00_regslice_BRESP;\n  assign S_AXI_bvalid = s00_couplers_to_s00_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = s00_couplers_to_s00_regslice_RDATA;\n  assign S_AXI_rid[5:0] = s00_couplers_to_s00_regslice_RID;\n  assign S_AXI_rlast = s00_couplers_to_s00_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = s00_couplers_to_s00_regslice_RRESP;\n  assign S_AXI_rvalid = s00_couplers_to_s00_regslice_RVALID;\n  assign S_AXI_wready = s00_couplers_to_s00_regslice_WREADY;\n  assign s00_couplers_to_s00_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign s00_couplers_to_s00_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign s00_couplers_to_s00_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign s00_couplers_to_s00_regslice_ARID = S_AXI_arid[5:0];\n  assign s00_couplers_to_s00_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign s00_couplers_to_s00_regslice_ARLOCK = S_AXI_arlock[0];\n  assign s00_couplers_to_s00_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign s00_couplers_to_s00_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign s00_couplers_to_s00_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign s00_couplers_to_s00_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign s00_couplers_to_s00_regslice_ARVALID = S_AXI_arvalid;\n  assign s00_couplers_to_s00_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign s00_couplers_to_s00_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign s00_couplers_to_s00_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign s00_couplers_to_s00_regslice_AWID = S_AXI_awid[5:0];\n  assign s00_couplers_to_s00_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign s00_couplers_to_s00_regslice_AWLOCK = S_AXI_awlock[0];\n  assign s00_couplers_to_s00_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign s00_couplers_to_s00_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign s00_couplers_to_s00_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign s00_couplers_to_s00_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign s00_couplers_to_s00_regslice_AWVALID = S_AXI_awvalid;\n  assign s00_couplers_to_s00_regslice_BREADY = S_AXI_bready;\n  assign s00_couplers_to_s00_regslice_RREADY = S_AXI_rready;\n  assign s00_couplers_to_s00_regslice_WDATA = S_AXI_wdata[511:0];\n  assign s00_couplers_to_s00_regslice_WLAST = S_AXI_wlast;\n  assign s00_couplers_to_s00_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign s00_couplers_to_s00_regslice_WVALID = S_AXI_wvalid;\n  assign s00_regslice_to_s00_couplers_ARREADY = M_AXI_arready;\n  assign s00_regslice_to_s00_couplers_AWREADY = M_AXI_awready;\n  assign s00_regslice_to_s00_couplers_BID = M_AXI_bid[6:0];\n  assign s00_regslice_to_s00_couplers_BRESP = M_AXI_bresp[1:0];\n  assign s00_regslice_to_s00_couplers_BVALID = M_AXI_bvalid;\n  assign s00_regslice_to_s00_couplers_RDATA = M_AXI_rdata[511:0];\n  assign s00_regslice_to_s00_couplers_RID = M_AXI_rid[6:0];\n  assign s00_regslice_to_s00_couplers_RLAST = M_AXI_rlast;\n  assign s00_regslice_to_s00_couplers_RRESP = M_AXI_rresp[1:0];\n  assign s00_regslice_to_s00_couplers_RVALID = M_AXI_rvalid;\n  assign s00_regslice_to_s00_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_s00_regslice_0 s00_regslice\n       (.aclk(S_ACLK_1),\n        .aresetn(S_ARESETN_1),\n        .m_axi_araddr(s00_regslice_to_s00_couplers_ARADDR),\n        .m_axi_arburst(s00_regslice_to_s00_couplers_ARBURST),\n        .m_axi_arcache(s00_regslice_to_s00_couplers_ARCACHE),\n        .m_axi_arid(s00_regslice_to_s00_couplers_ARID),\n        .m_axi_arlen(s00_regslice_to_s00_couplers_ARLEN),\n        .m_axi_arlock(s00_regslice_to_s00_couplers_ARLOCK),\n        .m_axi_arprot(s00_regslice_to_s00_couplers_ARPROT),\n        .m_axi_arqos(s00_regslice_to_s00_couplers_ARQOS),\n        .m_axi_arready(s00_regslice_to_s00_couplers_ARREADY),\n        .m_axi_arsize(s00_regslice_to_s00_couplers_ARSIZE),\n        .m_axi_arvalid(s00_regslice_to_s00_couplers_ARVALID),\n        .m_axi_awaddr(s00_regslice_to_s00_couplers_AWADDR),\n        .m_axi_awburst(s00_regslice_to_s00_couplers_AWBURST),\n        .m_axi_awcache(s00_regslice_to_s00_couplers_AWCACHE),\n        .m_axi_awid(s00_regslice_to_s00_couplers_AWID),\n        .m_axi_awlen(s00_regslice_to_s00_couplers_AWLEN),\n        .m_axi_awlock(s00_regslice_to_s00_couplers_AWLOCK),\n        .m_axi_awprot(s00_regslice_to_s00_couplers_AWPROT),\n        .m_axi_awqos(s00_regslice_to_s00_couplers_AWQOS),\n        .m_axi_awready(s00_regslice_to_s00_couplers_AWREADY),\n        .m_axi_awsize(s00_regslice_to_s00_couplers_AWSIZE),\n        .m_axi_awvalid(s00_regslice_to_s00_couplers_AWVALID),\n        .m_axi_bid(s00_regslice_to_s00_couplers_BID[5:0]),\n        .m_axi_bready(s00_regslice_to_s00_couplers_BREADY),\n        .m_axi_bresp(s00_regslice_to_s00_couplers_BRESP),\n        .m_axi_bvalid(s00_regslice_to_s00_couplers_BVALID),\n        .m_axi_rdata(s00_regslice_to_s00_couplers_RDATA),\n        .m_axi_rid(s00_regslice_to_s00_couplers_RID[5:0]),\n        .m_axi_rlast(s00_regslice_to_s00_couplers_RLAST),\n        .m_axi_rready(s00_regslice_to_s00_couplers_RREADY),\n        .m_axi_rresp(s00_regslice_to_s00_couplers_RRESP),\n        .m_axi_rvalid(s00_regslice_to_s00_couplers_RVALID),\n        .m_axi_wdata(s00_regslice_to_s00_couplers_WDATA),\n        .m_axi_wlast(s00_regslice_to_s00_couplers_WLAST),\n        .m_axi_wready(s00_regslice_to_s00_couplers_WREADY),\n        .m_axi_wstrb(s00_regslice_to_s00_couplers_WSTRB),\n        .m_axi_wvalid(s00_regslice_to_s00_couplers_WVALID),\n        .s_axi_araddr(s00_couplers_to_s00_regslice_ARADDR),\n        .s_axi_arburst(s00_couplers_to_s00_regslice_ARBURST),\n        .s_axi_arcache(s00_couplers_to_s00_regslice_ARCACHE),\n        .s_axi_arid(s00_couplers_to_s00_regslice_ARID),\n        .s_axi_arlen(s00_couplers_to_s00_regslice_ARLEN),\n        .s_axi_arlock(s00_couplers_to_s00_regslice_ARLOCK),\n        .s_axi_arprot(s00_couplers_to_s00_regslice_ARPROT),\n        .s_axi_arqos(s00_couplers_to_s00_regslice_ARQOS),\n        .s_axi_arready(s00_couplers_to_s00_regslice_ARREADY),\n        .s_axi_arregion(s00_couplers_to_s00_regslice_ARREGION),\n        .s_axi_arsize(s00_couplers_to_s00_regslice_ARSIZE),\n        .s_axi_arvalid(s00_couplers_to_s00_regslice_ARVALID),\n        .s_axi_awaddr(s00_couplers_to_s00_regslice_AWADDR),\n        .s_axi_awburst(s00_couplers_to_s00_regslice_AWBURST),\n        .s_axi_awcache(s00_couplers_to_s00_regslice_AWCACHE),\n        .s_axi_awid(s00_couplers_to_s00_regslice_AWID),\n        .s_axi_awlen(s00_couplers_to_s00_regslice_AWLEN),\n        .s_axi_awlock(s00_couplers_to_s00_regslice_AWLOCK),\n        .s_axi_awprot(s00_couplers_to_s00_regslice_AWPROT),\n        .s_axi_awqos(s00_couplers_to_s00_regslice_AWQOS),\n        .s_axi_awready(s00_couplers_to_s00_regslice_AWREADY),\n        .s_axi_awregion(s00_couplers_to_s00_regslice_AWREGION),\n        .s_axi_awsize(s00_couplers_to_s00_regslice_AWSIZE),\n        .s_axi_awvalid(s00_couplers_to_s00_regslice_AWVALID),\n        .s_axi_bid(s00_couplers_to_s00_regslice_BID),\n        .s_axi_bready(s00_couplers_to_s00_regslice_BREADY),\n        .s_axi_bresp(s00_couplers_to_s00_regslice_BRESP),\n        .s_axi_bvalid(s00_couplers_to_s00_regslice_BVALID),\n        .s_axi_rdata(s00_couplers_to_s00_regslice_RDATA),\n        .s_axi_rid(s00_couplers_to_s00_regslice_RID),\n        .s_axi_rlast(s00_couplers_to_s00_regslice_RLAST),\n        .s_axi_rready(s00_couplers_to_s00_regslice_RREADY),\n        .s_axi_rresp(s00_couplers_to_s00_regslice_RRESP),\n        .s_axi_rvalid(s00_couplers_to_s00_regslice_RVALID),\n        .s_axi_wdata(s00_couplers_to_s00_regslice_WDATA),\n        .s_axi_wlast(s00_couplers_to_s00_regslice_WLAST),\n        .s_axi_wready(s00_couplers_to_s00_regslice_WREADY),\n        .s_axi_wstrb(s00_couplers_to_s00_regslice_WSTRB),\n        .s_axi_wvalid(s00_couplers_to_s00_regslice_WVALID));\nendmodule\n\nmodule s01_couplers_imp_GSTXQ8\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [5:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [5:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [5:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [5:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [5:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [5:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire S_ACLK_1;\n  wire S_ARESETN_1;\n  wire [63:0]s01_couplers_to_s01_regslice_ARADDR;\n  wire [1:0]s01_couplers_to_s01_regslice_ARBURST;\n  wire [3:0]s01_couplers_to_s01_regslice_ARCACHE;\n  wire [5:0]s01_couplers_to_s01_regslice_ARID;\n  wire [7:0]s01_couplers_to_s01_regslice_ARLEN;\n  wire [0:0]s01_couplers_to_s01_regslice_ARLOCK;\n  wire [2:0]s01_couplers_to_s01_regslice_ARPROT;\n  wire [3:0]s01_couplers_to_s01_regslice_ARQOS;\n  wire s01_couplers_to_s01_regslice_ARREADY;\n  wire [3:0]s01_couplers_to_s01_regslice_ARREGION;\n  wire [2:0]s01_couplers_to_s01_regslice_ARSIZE;\n  wire s01_couplers_to_s01_regslice_ARVALID;\n  wire [63:0]s01_couplers_to_s01_regslice_AWADDR;\n  wire [1:0]s01_couplers_to_s01_regslice_AWBURST;\n  wire [3:0]s01_couplers_to_s01_regslice_AWCACHE;\n  wire [5:0]s01_couplers_to_s01_regslice_AWID;\n  wire [7:0]s01_couplers_to_s01_regslice_AWLEN;\n  wire [0:0]s01_couplers_to_s01_regslice_AWLOCK;\n  wire [2:0]s01_couplers_to_s01_regslice_AWPROT;\n  wire [3:0]s01_couplers_to_s01_regslice_AWQOS;\n  wire s01_couplers_to_s01_regslice_AWREADY;\n  wire [3:0]s01_couplers_to_s01_regslice_AWREGION;\n  wire [2:0]s01_couplers_to_s01_regslice_AWSIZE;\n  wire s01_couplers_to_s01_regslice_AWVALID;\n  wire [5:0]s01_couplers_to_s01_regslice_BID;\n  wire s01_couplers_to_s01_regslice_BREADY;\n  wire [1:0]s01_couplers_to_s01_regslice_BRESP;\n  wire s01_couplers_to_s01_regslice_BVALID;\n  wire [511:0]s01_couplers_to_s01_regslice_RDATA;\n  wire [5:0]s01_couplers_to_s01_regslice_RID;\n  wire s01_couplers_to_s01_regslice_RLAST;\n  wire s01_couplers_to_s01_regslice_RREADY;\n  wire [1:0]s01_couplers_to_s01_regslice_RRESP;\n  wire s01_couplers_to_s01_regslice_RVALID;\n  wire [511:0]s01_couplers_to_s01_regslice_WDATA;\n  wire s01_couplers_to_s01_regslice_WLAST;\n  wire s01_couplers_to_s01_regslice_WREADY;\n  wire [63:0]s01_couplers_to_s01_regslice_WSTRB;\n  wire s01_couplers_to_s01_regslice_WVALID;\n  wire [63:0]s01_regslice_to_s01_couplers_ARADDR;\n  wire [1:0]s01_regslice_to_s01_couplers_ARBURST;\n  wire [3:0]s01_regslice_to_s01_couplers_ARCACHE;\n  wire [5:0]s01_regslice_to_s01_couplers_ARID;\n  wire [7:0]s01_regslice_to_s01_couplers_ARLEN;\n  wire [0:0]s01_regslice_to_s01_couplers_ARLOCK;\n  wire [2:0]s01_regslice_to_s01_couplers_ARPROT;\n  wire [3:0]s01_regslice_to_s01_couplers_ARQOS;\n  wire s01_regslice_to_s01_couplers_ARREADY;\n  wire [2:0]s01_regslice_to_s01_couplers_ARSIZE;\n  wire s01_regslice_to_s01_couplers_ARVALID;\n  wire [63:0]s01_regslice_to_s01_couplers_AWADDR;\n  wire [1:0]s01_regslice_to_s01_couplers_AWBURST;\n  wire [3:0]s01_regslice_to_s01_couplers_AWCACHE;\n  wire [5:0]s01_regslice_to_s01_couplers_AWID;\n  wire [7:0]s01_regslice_to_s01_couplers_AWLEN;\n  wire [0:0]s01_regslice_to_s01_couplers_AWLOCK;\n  wire [2:0]s01_regslice_to_s01_couplers_AWPROT;\n  wire [3:0]s01_regslice_to_s01_couplers_AWQOS;\n  wire s01_regslice_to_s01_couplers_AWREADY;\n  wire [2:0]s01_regslice_to_s01_couplers_AWSIZE;\n  wire s01_regslice_to_s01_couplers_AWVALID;\n  wire [6:0]s01_regslice_to_s01_couplers_BID;\n  wire s01_regslice_to_s01_couplers_BREADY;\n  wire [1:0]s01_regslice_to_s01_couplers_BRESP;\n  wire s01_regslice_to_s01_couplers_BVALID;\n  wire [511:0]s01_regslice_to_s01_couplers_RDATA;\n  wire [6:0]s01_regslice_to_s01_couplers_RID;\n  wire s01_regslice_to_s01_couplers_RLAST;\n  wire s01_regslice_to_s01_couplers_RREADY;\n  wire [1:0]s01_regslice_to_s01_couplers_RRESP;\n  wire s01_regslice_to_s01_couplers_RVALID;\n  wire [511:0]s01_regslice_to_s01_couplers_WDATA;\n  wire s01_regslice_to_s01_couplers_WLAST;\n  wire s01_regslice_to_s01_couplers_WREADY;\n  wire [63:0]s01_regslice_to_s01_couplers_WSTRB;\n  wire s01_regslice_to_s01_couplers_WVALID;\n\n  assign M_AXI_araddr[63:0] = s01_regslice_to_s01_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = s01_regslice_to_s01_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = s01_regslice_to_s01_couplers_ARCACHE;\n  assign M_AXI_arid[5:0] = s01_regslice_to_s01_couplers_ARID;\n  assign M_AXI_arlen[7:0] = s01_regslice_to_s01_couplers_ARLEN;\n  assign M_AXI_arlock[0] = s01_regslice_to_s01_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = s01_regslice_to_s01_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = s01_regslice_to_s01_couplers_ARQOS;\n  assign M_AXI_arsize[2:0] = s01_regslice_to_s01_couplers_ARSIZE;\n  assign M_AXI_arvalid = s01_regslice_to_s01_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = s01_regslice_to_s01_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = s01_regslice_to_s01_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = s01_regslice_to_s01_couplers_AWCACHE;\n  assign M_AXI_awid[5:0] = s01_regslice_to_s01_couplers_AWID;\n  assign M_AXI_awlen[7:0] = s01_regslice_to_s01_couplers_AWLEN;\n  assign M_AXI_awlock[0] = s01_regslice_to_s01_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = s01_regslice_to_s01_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = s01_regslice_to_s01_couplers_AWQOS;\n  assign M_AXI_awsize[2:0] = s01_regslice_to_s01_couplers_AWSIZE;\n  assign M_AXI_awvalid = s01_regslice_to_s01_couplers_AWVALID;\n  assign M_AXI_bready = s01_regslice_to_s01_couplers_BREADY;\n  assign M_AXI_rready = s01_regslice_to_s01_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = s01_regslice_to_s01_couplers_WDATA;\n  assign M_AXI_wlast = s01_regslice_to_s01_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = s01_regslice_to_s01_couplers_WSTRB;\n  assign M_AXI_wvalid = s01_regslice_to_s01_couplers_WVALID;\n  assign S_ACLK_1 = S_ACLK;\n  assign S_ARESETN_1 = S_ARESETN;\n  assign S_AXI_arready = s01_couplers_to_s01_regslice_ARREADY;\n  assign S_AXI_awready = s01_couplers_to_s01_regslice_AWREADY;\n  assign S_AXI_bid[5:0] = s01_couplers_to_s01_regslice_BID;\n  assign S_AXI_bresp[1:0] = s01_couplers_to_s01_regslice_BRESP;\n  assign S_AXI_bvalid = s01_couplers_to_s01_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = s01_couplers_to_s01_regslice_RDATA;\n  assign S_AXI_rid[5:0] = s01_couplers_to_s01_regslice_RID;\n  assign S_AXI_rlast = s01_couplers_to_s01_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = s01_couplers_to_s01_regslice_RRESP;\n  assign S_AXI_rvalid = s01_couplers_to_s01_regslice_RVALID;\n  assign S_AXI_wready = s01_couplers_to_s01_regslice_WREADY;\n  assign s01_couplers_to_s01_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign s01_couplers_to_s01_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign s01_couplers_to_s01_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign s01_couplers_to_s01_regslice_ARID = S_AXI_arid[5:0];\n  assign s01_couplers_to_s01_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign s01_couplers_to_s01_regslice_ARLOCK = S_AXI_arlock[0];\n  assign s01_couplers_to_s01_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign s01_couplers_to_s01_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign s01_couplers_to_s01_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign s01_couplers_to_s01_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign s01_couplers_to_s01_regslice_ARVALID = S_AXI_arvalid;\n  assign s01_couplers_to_s01_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign s01_couplers_to_s01_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign s01_couplers_to_s01_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign s01_couplers_to_s01_regslice_AWID = S_AXI_awid[5:0];\n  assign s01_couplers_to_s01_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign s01_couplers_to_s01_regslice_AWLOCK = S_AXI_awlock[0];\n  assign s01_couplers_to_s01_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign s01_couplers_to_s01_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign s01_couplers_to_s01_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign s01_couplers_to_s01_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign s01_couplers_to_s01_regslice_AWVALID = S_AXI_awvalid;\n  assign s01_couplers_to_s01_regslice_BREADY = S_AXI_bready;\n  assign s01_couplers_to_s01_regslice_RREADY = S_AXI_rready;\n  assign s01_couplers_to_s01_regslice_WDATA = S_AXI_wdata[511:0];\n  assign s01_couplers_to_s01_regslice_WLAST = S_AXI_wlast;\n  assign s01_couplers_to_s01_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign s01_couplers_to_s01_regslice_WVALID = S_AXI_wvalid;\n  assign s01_regslice_to_s01_couplers_ARREADY = M_AXI_arready;\n  assign s01_regslice_to_s01_couplers_AWREADY = M_AXI_awready;\n  assign s01_regslice_to_s01_couplers_BID = M_AXI_bid[6:0];\n  assign s01_regslice_to_s01_couplers_BRESP = M_AXI_bresp[1:0];\n  assign s01_regslice_to_s01_couplers_BVALID = M_AXI_bvalid;\n  assign s01_regslice_to_s01_couplers_RDATA = M_AXI_rdata[511:0];\n  assign s01_regslice_to_s01_couplers_RID = M_AXI_rid[6:0];\n  assign s01_regslice_to_s01_couplers_RLAST = M_AXI_rlast;\n  assign s01_regslice_to_s01_couplers_RRESP = M_AXI_rresp[1:0];\n  assign s01_regslice_to_s01_couplers_RVALID = M_AXI_rvalid;\n  assign s01_regslice_to_s01_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_s01_regslice_0 s01_regslice\n       (.aclk(S_ACLK_1),\n        .aresetn(S_ARESETN_1),\n        .m_axi_araddr(s01_regslice_to_s01_couplers_ARADDR),\n        .m_axi_arburst(s01_regslice_to_s01_couplers_ARBURST),\n        .m_axi_arcache(s01_regslice_to_s01_couplers_ARCACHE),\n        .m_axi_arid(s01_regslice_to_s01_couplers_ARID),\n        .m_axi_arlen(s01_regslice_to_s01_couplers_ARLEN),\n        .m_axi_arlock(s01_regslice_to_s01_couplers_ARLOCK),\n        .m_axi_arprot(s01_regslice_to_s01_couplers_ARPROT),\n        .m_axi_arqos(s01_regslice_to_s01_couplers_ARQOS),\n        .m_axi_arready(s01_regslice_to_s01_couplers_ARREADY),\n        .m_axi_arsize(s01_regslice_to_s01_couplers_ARSIZE),\n        .m_axi_arvalid(s01_regslice_to_s01_couplers_ARVALID),\n        .m_axi_awaddr(s01_regslice_to_s01_couplers_AWADDR),\n        .m_axi_awburst(s01_regslice_to_s01_couplers_AWBURST),\n        .m_axi_awcache(s01_regslice_to_s01_couplers_AWCACHE),\n        .m_axi_awid(s01_regslice_to_s01_couplers_AWID),\n        .m_axi_awlen(s01_regslice_to_s01_couplers_AWLEN),\n        .m_axi_awlock(s01_regslice_to_s01_couplers_AWLOCK),\n        .m_axi_awprot(s01_regslice_to_s01_couplers_AWPROT),\n        .m_axi_awqos(s01_regslice_to_s01_couplers_AWQOS),\n        .m_axi_awready(s01_regslice_to_s01_couplers_AWREADY),\n        .m_axi_awsize(s01_regslice_to_s01_couplers_AWSIZE),\n        .m_axi_awvalid(s01_regslice_to_s01_couplers_AWVALID),\n        .m_axi_bid(s01_regslice_to_s01_couplers_BID[5:0]),\n        .m_axi_bready(s01_regslice_to_s01_couplers_BREADY),\n        .m_axi_bresp(s01_regslice_to_s01_couplers_BRESP),\n        .m_axi_bvalid(s01_regslice_to_s01_couplers_BVALID),\n        .m_axi_rdata(s01_regslice_to_s01_couplers_RDATA),\n        .m_axi_rid(s01_regslice_to_s01_couplers_RID[5:0]),\n        .m_axi_rlast(s01_regslice_to_s01_couplers_RLAST),\n        .m_axi_rready(s01_regslice_to_s01_couplers_RREADY),\n        .m_axi_rresp(s01_regslice_to_s01_couplers_RRESP),\n        .m_axi_rvalid(s01_regslice_to_s01_couplers_RVALID),\n        .m_axi_wdata(s01_regslice_to_s01_couplers_WDATA),\n        .m_axi_wlast(s01_regslice_to_s01_couplers_WLAST),\n        .m_axi_wready(s01_regslice_to_s01_couplers_WREADY),\n        .m_axi_wstrb(s01_regslice_to_s01_couplers_WSTRB),\n        .m_axi_wvalid(s01_regslice_to_s01_couplers_WVALID),\n        .s_axi_araddr(s01_couplers_to_s01_regslice_ARADDR),\n        .s_axi_arburst(s01_couplers_to_s01_regslice_ARBURST),\n        .s_axi_arcache(s01_couplers_to_s01_regslice_ARCACHE),\n        .s_axi_arid(s01_couplers_to_s01_regslice_ARID),\n        .s_axi_arlen(s01_couplers_to_s01_regslice_ARLEN),\n        .s_axi_arlock(s01_couplers_to_s01_regslice_ARLOCK),\n        .s_axi_arprot(s01_couplers_to_s01_regslice_ARPROT),\n        .s_axi_arqos(s01_couplers_to_s01_regslice_ARQOS),\n        .s_axi_arready(s01_couplers_to_s01_regslice_ARREADY),\n        .s_axi_arregion(s01_couplers_to_s01_regslice_ARREGION),\n        .s_axi_arsize(s01_couplers_to_s01_regslice_ARSIZE),\n        .s_axi_arvalid(s01_couplers_to_s01_regslice_ARVALID),\n        .s_axi_awaddr(s01_couplers_to_s01_regslice_AWADDR),\n        .s_axi_awburst(s01_couplers_to_s01_regslice_AWBURST),\n        .s_axi_awcache(s01_couplers_to_s01_regslice_AWCACHE),\n        .s_axi_awid(s01_couplers_to_s01_regslice_AWID),\n        .s_axi_awlen(s01_couplers_to_s01_regslice_AWLEN),\n        .s_axi_awlock(s01_couplers_to_s01_regslice_AWLOCK),\n        .s_axi_awprot(s01_couplers_to_s01_regslice_AWPROT),\n        .s_axi_awqos(s01_couplers_to_s01_regslice_AWQOS),\n        .s_axi_awready(s01_couplers_to_s01_regslice_AWREADY),\n        .s_axi_awregion(s01_couplers_to_s01_regslice_AWREGION),\n        .s_axi_awsize(s01_couplers_to_s01_regslice_AWSIZE),\n        .s_axi_awvalid(s01_couplers_to_s01_regslice_AWVALID),\n        .s_axi_bid(s01_couplers_to_s01_regslice_BID),\n        .s_axi_bready(s01_couplers_to_s01_regslice_BREADY),\n        .s_axi_bresp(s01_couplers_to_s01_regslice_BRESP),\n        .s_axi_bvalid(s01_couplers_to_s01_regslice_BVALID),\n        .s_axi_rdata(s01_couplers_to_s01_regslice_RDATA),\n        .s_axi_rid(s01_couplers_to_s01_regslice_RID),\n        .s_axi_rlast(s01_couplers_to_s01_regslice_RLAST),\n        .s_axi_rready(s01_couplers_to_s01_regslice_RREADY),\n        .s_axi_rresp(s01_couplers_to_s01_regslice_RRESP),\n        .s_axi_rvalid(s01_couplers_to_s01_regslice_RVALID),\n        .s_axi_wdata(s01_couplers_to_s01_regslice_WDATA),\n        .s_axi_wlast(s01_couplers_to_s01_regslice_WLAST),\n        .s_axi_wready(s01_couplers_to_s01_regslice_WREADY),\n        .s_axi_wstrb(s01_couplers_to_s01_regslice_WSTRB),\n        .s_axi_wvalid(s01_couplers_to_s01_regslice_WVALID));\nendmodule\n", "num_lines": 5426}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020\n//Date        : Wed Dec 15 00:42:18 2021\n//Host        : a-21awsprq4sria running 64-bit Amazon Linux release 2 (Karoo)\n//Command     : generate_target cl_axi_interconnect.bd\n//Design      : cl_axi_interconnect\n//Purpose     : IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=cl_axi_interconnect,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=14,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}\" *) (* HW_HANDOFF = \"cl_axi_interconnect.hwdef\" *) \nmodule cl_axi_interconnect\n   (ACLK,\n    ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.ACLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF S00_AXI:M00_AXI:M01_AXI:M02_AXI:M03_AXI:S01_AXI, ASSOCIATED_RESET ARESETN, CLK_DOMAIN cl_axi_interconnect_ACLK, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input ACLK;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.ARESETN RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW\" *) input ARESETN;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M00_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M00_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARBURST\" *) output [1:0]M00_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE\" *) output [3:0]M00_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARID\" *) output [6:0]M00_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLEN\" *) output [7:0]M00_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK\" *) output [0:0]M00_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARPROT\" *) output [2:0]M00_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARQOS\" *) output [3:0]M00_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREADY\" *) input M00_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREGION\" *) output [3:0]M00_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE\" *) output [2:0]M00_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARVALID\" *) output M00_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWADDR\" *) output [63:0]M00_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWBURST\" *) output [1:0]M00_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE\" *) output [3:0]M00_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWID\" *) output [6:0]M00_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLEN\" *) output [7:0]M00_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK\" *) output [0:0]M00_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWPROT\" *) output [2:0]M00_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWQOS\" *) output [3:0]M00_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREADY\" *) input M00_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREGION\" *) output [3:0]M00_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE\" *) output [2:0]M00_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWVALID\" *) output M00_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BID\" *) input [6:0]M00_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BREADY\" *) output M00_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BRESP\" *) input [1:0]M00_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BVALID\" *) input M00_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RDATA\" *) input [511:0]M00_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RID\" *) input [6:0]M00_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RLAST\" *) input M00_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RREADY\" *) output M00_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RRESP\" *) input [1:0]M00_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RVALID\" *) input M00_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WDATA\" *) output [511:0]M00_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WLAST\" *) output M00_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WREADY\" *) input M00_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WSTRB\" *) output [63:0]M00_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WVALID\" *) output M00_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M01_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M01_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARBURST\" *) output [1:0]M01_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE\" *) output [3:0]M01_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARID\" *) output [6:0]M01_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARLEN\" *) output [7:0]M01_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK\" *) output [0:0]M01_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARPROT\" *) output [2:0]M01_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARQOS\" *) output [3:0]M01_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARREADY\" *) input M01_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARREGION\" *) output [3:0]M01_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE\" *) output [2:0]M01_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARVALID\" *) output M01_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWADDR\" *) output [63:0]M01_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWBURST\" *) output [1:0]M01_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE\" *) output [3:0]M01_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWID\" *) output [6:0]M01_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWLEN\" *) output [7:0]M01_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK\" *) output [0:0]M01_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWPROT\" *) output [2:0]M01_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWQOS\" *) output [3:0]M01_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWREADY\" *) input M01_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWREGION\" *) output [3:0]M01_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE\" *) output [2:0]M01_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWVALID\" *) output M01_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BID\" *) input [6:0]M01_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BREADY\" *) output M01_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BRESP\" *) input [1:0]M01_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BVALID\" *) input M01_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RDATA\" *) input [511:0]M01_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RID\" *) input [6:0]M01_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RLAST\" *) input M01_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RREADY\" *) output M01_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RRESP\" *) input [1:0]M01_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RVALID\" *) input M01_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WDATA\" *) output [511:0]M01_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WLAST\" *) output M01_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WREADY\" *) input M01_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WSTRB\" *) output [63:0]M01_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WVALID\" *) output M01_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M02_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M02_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARBURST\" *) output [1:0]M02_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE\" *) output [3:0]M02_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARID\" *) output [6:0]M02_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARLEN\" *) output [7:0]M02_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK\" *) output [0:0]M02_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARPROT\" *) output [2:0]M02_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARQOS\" *) output [3:0]M02_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARREADY\" *) input M02_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARREGION\" *) output [3:0]M02_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE\" *) output [2:0]M02_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARVALID\" *) output M02_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWADDR\" *) output [63:0]M02_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWBURST\" *) output [1:0]M02_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE\" *) output [3:0]M02_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWID\" *) output [6:0]M02_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWLEN\" *) output [7:0]M02_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK\" *) output [0:0]M02_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWPROT\" *) output [2:0]M02_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWQOS\" *) output [3:0]M02_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWREADY\" *) input M02_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWREGION\" *) output [3:0]M02_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE\" *) output [2:0]M02_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWVALID\" *) output M02_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BID\" *) input [6:0]M02_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BREADY\" *) output M02_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BRESP\" *) input [1:0]M02_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BVALID\" *) input M02_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RDATA\" *) input [511:0]M02_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RID\" *) input [6:0]M02_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RLAST\" *) input M02_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RREADY\" *) output M02_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RRESP\" *) input [1:0]M02_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RVALID\" *) input M02_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WDATA\" *) output [511:0]M02_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WLAST\" *) output M02_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WREADY\" *) input M02_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WSTRB\" *) output [63:0]M02_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WVALID\" *) output M02_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M03_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M03_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARBURST\" *) output [1:0]M03_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE\" *) output [3:0]M03_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARID\" *) output [6:0]M03_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARLEN\" *) output [7:0]M03_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK\" *) output [0:0]M03_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARPROT\" *) output [2:0]M03_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARQOS\" *) output [3:0]M03_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARREADY\" *) input M03_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARREGION\" *) output [3:0]M03_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE\" *) output [2:0]M03_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARVALID\" *) output M03_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWADDR\" *) output [63:0]M03_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWBURST\" *) output [1:0]M03_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE\" *) output [3:0]M03_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWID\" *) output [6:0]M03_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWLEN\" *) output [7:0]M03_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK\" *) output [0:0]M03_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWPROT\" *) output [2:0]M03_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWQOS\" *) output [3:0]M03_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWREADY\" *) input M03_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWREGION\" *) output [3:0]M03_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE\" *) output [2:0]M03_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWVALID\" *) output M03_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BID\" *) input [6:0]M03_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BREADY\" *) output M03_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BRESP\" *) input [1:0]M03_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BVALID\" *) input M03_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RDATA\" *) input [511:0]M03_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RID\" *) input [6:0]M03_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RLAST\" *) input M03_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RREADY\" *) output M03_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RRESP\" *) input [1:0]M03_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RVALID\" *) input M03_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WDATA\" *) output [511:0]M03_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WLAST\" *) output M03_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WREADY\" *) input M03_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WSTRB\" *) output [63:0]M03_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WVALID\" *) output M03_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S00_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 6, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 32, NUM_READ_THREADS 16, NUM_WRITE_OUTSTANDING 32, NUM_WRITE_THREADS 16, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) input [63:0]S00_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARBURST\" *) input [1:0]S00_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE\" *) input [3:0]S00_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARID\" *) input [5:0]S00_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLEN\" *) input [7:0]S00_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK\" *) input [0:0]S00_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARPROT\" *) input [2:0]S00_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARQOS\" *) input [3:0]S00_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREADY\" *) output S00_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREGION\" *) input [3:0]S00_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE\" *) input [2:0]S00_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARVALID\" *) input S00_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWADDR\" *) input [63:0]S00_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWBURST\" *) input [1:0]S00_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE\" *) input [3:0]S00_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWID\" *) input [5:0]S00_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLEN\" *) input [7:0]S00_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK\" *) input [0:0]S00_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWPROT\" *) input [2:0]S00_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWQOS\" *) input [3:0]S00_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREADY\" *) output S00_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREGION\" *) input [3:0]S00_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE\" *) input [2:0]S00_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWVALID\" *) input S00_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BID\" *) output [5:0]S00_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BREADY\" *) input S00_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BRESP\" *) output [1:0]S00_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BVALID\" *) output S00_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RDATA\" *) output [511:0]S00_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RID\" *) output [5:0]S00_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RLAST\" *) output S00_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RREADY\" *) input S00_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RRESP\" *) output [1:0]S00_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RVALID\" *) output S00_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WDATA\" *) input [511:0]S00_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WLAST\" *) input S00_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WREADY\" *) output S00_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WSTRB\" *) input [63:0]S00_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WVALID\" *) input S00_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S01_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 6, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 32, NUM_READ_THREADS 16, NUM_WRITE_OUTSTANDING 32, NUM_WRITE_THREADS 16, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) input [63:0]S01_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARBURST\" *) input [1:0]S01_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE\" *) input [3:0]S01_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARID\" *) input [5:0]S01_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARLEN\" *) input [7:0]S01_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK\" *) input [0:0]S01_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARPROT\" *) input [2:0]S01_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARQOS\" *) input [3:0]S01_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARREADY\" *) output S01_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARREGION\" *) input [3:0]S01_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE\" *) input [2:0]S01_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARVALID\" *) input S01_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWADDR\" *) input [63:0]S01_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWBURST\" *) input [1:0]S01_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE\" *) input [3:0]S01_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWID\" *) input [5:0]S01_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWLEN\" *) input [7:0]S01_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK\" *) input [0:0]S01_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWPROT\" *) input [2:0]S01_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWQOS\" *) input [3:0]S01_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWREADY\" *) output S01_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWREGION\" *) input [3:0]S01_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE\" *) input [2:0]S01_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWVALID\" *) input S01_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BID\" *) output [5:0]S01_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BREADY\" *) input S01_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BRESP\" *) output [1:0]S01_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BVALID\" *) output S01_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RDATA\" *) output [511:0]S01_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RID\" *) output [5:0]S01_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RLAST\" *) output S01_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RREADY\" *) input S01_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RRESP\" *) output [1:0]S01_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RVALID\" *) output S01_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WDATA\" *) input [511:0]S01_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WLAST\" *) input S01_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WREADY\" *) output S01_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WSTRB\" *) input [63:0]S01_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WVALID\" *) input S01_AXI_wvalid;\n\n  wire ACLK_1;\n  wire ARESETN_1;\n  wire [63:0]S00_AXI_1_ARADDR;\n  wire [1:0]S00_AXI_1_ARBURST;\n  wire [3:0]S00_AXI_1_ARCACHE;\n  wire [5:0]S00_AXI_1_ARID;\n  wire [7:0]S00_AXI_1_ARLEN;\n  wire [0:0]S00_AXI_1_ARLOCK;\n  wire [2:0]S00_AXI_1_ARPROT;\n  wire [3:0]S00_AXI_1_ARQOS;\n  wire S00_AXI_1_ARREADY;\n  wire [3:0]S00_AXI_1_ARREGION;\n  wire [2:0]S00_AXI_1_ARSIZE;\n  wire S00_AXI_1_ARVALID;\n  wire [63:0]S00_AXI_1_AWADDR;\n  wire [1:0]S00_AXI_1_AWBURST;\n  wire [3:0]S00_AXI_1_AWCACHE;\n  wire [5:0]S00_AXI_1_AWID;\n  wire [7:0]S00_AXI_1_AWLEN;\n  wire [0:0]S00_AXI_1_AWLOCK;\n  wire [2:0]S00_AXI_1_AWPROT;\n  wire [3:0]S00_AXI_1_AWQOS;\n  wire S00_AXI_1_AWREADY;\n  wire [3:0]S00_AXI_1_AWREGION;\n  wire [2:0]S00_AXI_1_AWSIZE;\n  wire S00_AXI_1_AWVALID;\n  wire [5:0]S00_AXI_1_BID;\n  wire S00_AXI_1_BREADY;\n  wire [1:0]S00_AXI_1_BRESP;\n  wire S00_AXI_1_BVALID;\n  wire [511:0]S00_AXI_1_RDATA;\n  wire [5:0]S00_AXI_1_RID;\n  wire S00_AXI_1_RLAST;\n  wire S00_AXI_1_RREADY;\n  wire [1:0]S00_AXI_1_RRESP;\n  wire S00_AXI_1_RVALID;\n  wire [511:0]S00_AXI_1_WDATA;\n  wire S00_AXI_1_WLAST;\n  wire S00_AXI_1_WREADY;\n  wire [63:0]S00_AXI_1_WSTRB;\n  wire S00_AXI_1_WVALID;\n  wire [63:0]S01_AXI_1_ARADDR;\n  wire [1:0]S01_AXI_1_ARBURST;\n  wire [3:0]S01_AXI_1_ARCACHE;\n  wire [5:0]S01_AXI_1_ARID;\n  wire [7:0]S01_AXI_1_ARLEN;\n  wire [0:0]S01_AXI_1_ARLOCK;\n  wire [2:0]S01_AXI_1_ARPROT;\n  wire [3:0]S01_AXI_1_ARQOS;\n  wire S01_AXI_1_ARREADY;\n  wire [3:0]S01_AXI_1_ARREGION;\n  wire [2:0]S01_AXI_1_ARSIZE;\n  wire S01_AXI_1_ARVALID;\n  wire [63:0]S01_AXI_1_AWADDR;\n  wire [1:0]S01_AXI_1_AWBURST;\n  wire [3:0]S01_AXI_1_AWCACHE;\n  wire [5:0]S01_AXI_1_AWID;\n  wire [7:0]S01_AXI_1_AWLEN;\n  wire [0:0]S01_AXI_1_AWLOCK;\n  wire [2:0]S01_AXI_1_AWPROT;\n  wire [3:0]S01_AXI_1_AWQOS;\n  wire S01_AXI_1_AWREADY;\n  wire [3:0]S01_AXI_1_AWREGION;\n  wire [2:0]S01_AXI_1_AWSIZE;\n  wire S01_AXI_1_AWVALID;\n  wire [5:0]S01_AXI_1_BID;\n  wire S01_AXI_1_BREADY;\n  wire [1:0]S01_AXI_1_BRESP;\n  wire S01_AXI_1_BVALID;\n  wire [511:0]S01_AXI_1_RDATA;\n  wire [5:0]S01_AXI_1_RID;\n  wire S01_AXI_1_RLAST;\n  wire S01_AXI_1_RREADY;\n  wire [1:0]S01_AXI_1_RRESP;\n  wire S01_AXI_1_RVALID;\n  wire [511:0]S01_AXI_1_WDATA;\n  wire S01_AXI_1_WLAST;\n  wire S01_AXI_1_WREADY;\n  wire [63:0]S01_AXI_1_WSTRB;\n  wire S01_AXI_1_WVALID;\n  wire [63:0]axi_interconnect_0_M00_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M00_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M00_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M00_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M00_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M00_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARQOS;\n  wire axi_interconnect_0_M00_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M00_AXI_ARSIZE;\n  wire axi_interconnect_0_M00_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M00_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M00_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M00_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M00_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M00_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M00_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWQOS;\n  wire axi_interconnect_0_M00_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M00_AXI_AWSIZE;\n  wire axi_interconnect_0_M00_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M00_AXI_BID;\n  wire axi_interconnect_0_M00_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M00_AXI_BRESP;\n  wire axi_interconnect_0_M00_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M00_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M00_AXI_RID;\n  wire axi_interconnect_0_M00_AXI_RLAST;\n  wire axi_interconnect_0_M00_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M00_AXI_RRESP;\n  wire axi_interconnect_0_M00_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M00_AXI_WDATA;\n  wire axi_interconnect_0_M00_AXI_WLAST;\n  wire axi_interconnect_0_M00_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M00_AXI_WSTRB;\n  wire axi_interconnect_0_M00_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M01_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M01_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M01_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M01_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M01_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M01_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARQOS;\n  wire axi_interconnect_0_M01_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M01_AXI_ARSIZE;\n  wire axi_interconnect_0_M01_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M01_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M01_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M01_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M01_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M01_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M01_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWQOS;\n  wire axi_interconnect_0_M01_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M01_AXI_AWSIZE;\n  wire axi_interconnect_0_M01_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M01_AXI_BID;\n  wire axi_interconnect_0_M01_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M01_AXI_BRESP;\n  wire axi_interconnect_0_M01_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M01_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M01_AXI_RID;\n  wire axi_interconnect_0_M01_AXI_RLAST;\n  wire axi_interconnect_0_M01_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M01_AXI_RRESP;\n  wire axi_interconnect_0_M01_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M01_AXI_WDATA;\n  wire axi_interconnect_0_M01_AXI_WLAST;\n  wire axi_interconnect_0_M01_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M01_AXI_WSTRB;\n  wire axi_interconnect_0_M01_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M02_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M02_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M02_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M02_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M02_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M02_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARQOS;\n  wire axi_interconnect_0_M02_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M02_AXI_ARSIZE;\n  wire axi_interconnect_0_M02_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M02_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M02_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M02_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M02_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M02_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M02_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWQOS;\n  wire axi_interconnect_0_M02_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M02_AXI_AWSIZE;\n  wire axi_interconnect_0_M02_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M02_AXI_BID;\n  wire axi_interconnect_0_M02_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M02_AXI_BRESP;\n  wire axi_interconnect_0_M02_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M02_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M02_AXI_RID;\n  wire axi_interconnect_0_M02_AXI_RLAST;\n  wire axi_interconnect_0_M02_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M02_AXI_RRESP;\n  wire axi_interconnect_0_M02_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M02_AXI_WDATA;\n  wire axi_interconnect_0_M02_AXI_WLAST;\n  wire axi_interconnect_0_M02_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M02_AXI_WSTRB;\n  wire axi_interconnect_0_M02_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M03_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M03_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M03_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M03_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M03_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M03_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARQOS;\n  wire axi_interconnect_0_M03_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M03_AXI_ARSIZE;\n  wire axi_interconnect_0_M03_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M03_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M03_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M03_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M03_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M03_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M03_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWQOS;\n  wire axi_interconnect_0_M03_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M03_AXI_AWSIZE;\n  wire axi_interconnect_0_M03_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M03_AXI_BID;\n  wire axi_interconnect_0_M03_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M03_AXI_BRESP;\n  wire axi_interconnect_0_M03_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M03_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M03_AXI_RID;\n  wire axi_interconnect_0_M03_AXI_RLAST;\n  wire axi_interconnect_0_M03_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M03_AXI_RRESP;\n  wire axi_interconnect_0_M03_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M03_AXI_WDATA;\n  wire axi_interconnect_0_M03_AXI_WLAST;\n  wire axi_interconnect_0_M03_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M03_AXI_WSTRB;\n  wire axi_interconnect_0_M03_AXI_WVALID;\n\n  assign ACLK_1 = ACLK;\n  assign ARESETN_1 = ARESETN;\n  assign M00_AXI_araddr[63:0] = axi_interconnect_0_M00_AXI_ARADDR;\n  assign M00_AXI_arburst[1:0] = axi_interconnect_0_M00_AXI_ARBURST;\n  assign M00_AXI_arcache[3:0] = axi_interconnect_0_M00_AXI_ARCACHE;\n  assign M00_AXI_arid[6:0] = axi_interconnect_0_M00_AXI_ARID;\n  assign M00_AXI_arlen[7:0] = axi_interconnect_0_M00_AXI_ARLEN;\n  assign M00_AXI_arlock[0] = axi_interconnect_0_M00_AXI_ARLOCK;\n  assign M00_AXI_arprot[2:0] = axi_interconnect_0_M00_AXI_ARPROT;\n  assign M00_AXI_arqos[3:0] = axi_interconnect_0_M00_AXI_ARQOS;\n  assign M00_AXI_arregion[3:0] = axi_interconnect_0_M00_AXI_ARREGION;\n  assign M00_AXI_arsize[2:0] = axi_interconnect_0_M00_AXI_ARSIZE;\n  assign M00_AXI_arvalid = axi_interconnect_0_M00_AXI_ARVALID;\n  assign M00_AXI_awaddr[63:0] = axi_interconnect_0_M00_AXI_AWADDR;\n  assign M00_AXI_awburst[1:0] = axi_interconnect_0_M00_AXI_AWBURST;\n  assign M00_AXI_awcache[3:0] = axi_interconnect_0_M00_AXI_AWCACHE;\n  assign M00_AXI_awid[6:0] = axi_interconnect_0_M00_AXI_AWID;\n  assign M00_AXI_awlen[7:0] = axi_interconnect_0_M00_AXI_AWLEN;\n  assign M00_AXI_awlock[0] = axi_interconnect_0_M00_AXI_AWLOCK;\n  assign M00_AXI_awprot[2:0] = axi_interconnect_0_M00_AXI_AWPROT;\n  assign M00_AXI_awqos[3:0] = axi_interconnect_0_M00_AXI_AWQOS;\n  assign M00_AXI_awregion[3:0] = axi_interconnect_0_M00_AXI_AWREGION;\n  assign M00_AXI_awsize[2:0] = axi_interconnect_0_M00_AXI_AWSIZE;\n  assign M00_AXI_awvalid = axi_interconnect_0_M00_AXI_AWVALID;\n  assign M00_AXI_bready = axi_interconnect_0_M00_AXI_BREADY;\n  assign M00_AXI_rready = axi_interconnect_0_M00_AXI_RREADY;\n  assign M00_AXI_wdata[511:0] = axi_interconnect_0_M00_AXI_WDATA;\n  assign M00_AXI_wlast = axi_interconnect_0_M00_AXI_WLAST;\n  assign M00_AXI_wstrb[63:0] = axi_interconnect_0_M00_AXI_WSTRB;\n  assign M00_AXI_wvalid = axi_interconnect_0_M00_AXI_WVALID;\n  assign M01_AXI_araddr[63:0] = axi_interconnect_0_M01_AXI_ARADDR;\n  assign M01_AXI_arburst[1:0] = axi_interconnect_0_M01_AXI_ARBURST;\n  assign M01_AXI_arcache[3:0] = axi_interconnect_0_M01_AXI_ARCACHE;\n  assign M01_AXI_arid[6:0] = axi_interconnect_0_M01_AXI_ARID;\n  assign M01_AXI_arlen[7:0] = axi_interconnect_0_M01_AXI_ARLEN;\n  assign M01_AXI_arlock[0] = axi_interconnect_0_M01_AXI_ARLOCK;\n  assign M01_AXI_arprot[2:0] = axi_interconnect_0_M01_AXI_ARPROT;\n  assign M01_AXI_arqos[3:0] = axi_interconnect_0_M01_AXI_ARQOS;\n  assign M01_AXI_arregion[3:0] = axi_interconnect_0_M01_AXI_ARREGION;\n  assign M01_AXI_arsize[2:0] = axi_interconnect_0_M01_AXI_ARSIZE;\n  assign M01_AXI_arvalid = axi_interconnect_0_M01_AXI_ARVALID;\n  assign M01_AXI_awaddr[63:0] = axi_interconnect_0_M01_AXI_AWADDR;\n  assign M01_AXI_awburst[1:0] = axi_interconnect_0_M01_AXI_AWBURST;\n  assign M01_AXI_awcache[3:0] = axi_interconnect_0_M01_AXI_AWCACHE;\n  assign M01_AXI_awid[6:0] = axi_interconnect_0_M01_AXI_AWID;\n  assign M01_AXI_awlen[7:0] = axi_interconnect_0_M01_AXI_AWLEN;\n  assign M01_AXI_awlock[0] = axi_interconnect_0_M01_AXI_AWLOCK;\n  assign M01_AXI_awprot[2:0] = axi_interconnect_0_M01_AXI_AWPROT;\n  assign M01_AXI_awqos[3:0] = axi_interconnect_0_M01_AXI_AWQOS;\n  assign M01_AXI_awregion[3:0] = axi_interconnect_0_M01_AXI_AWREGION;\n  assign M01_AXI_awsize[2:0] = axi_interconnect_0_M01_AXI_AWSIZE;\n  assign M01_AXI_awvalid = axi_interconnect_0_M01_AXI_AWVALID;\n  assign M01_AXI_bready = axi_interconnect_0_M01_AXI_BREADY;\n  assign M01_AXI_rready = axi_interconnect_0_M01_AXI_RREADY;\n  assign M01_AXI_wdata[511:0] = axi_interconnect_0_M01_AXI_WDATA;\n  assign M01_AXI_wlast = axi_interconnect_0_M01_AXI_WLAST;\n  assign M01_AXI_wstrb[63:0] = axi_interconnect_0_M01_AXI_WSTRB;\n  assign M01_AXI_wvalid = axi_interconnect_0_M01_AXI_WVALID;\n  assign M02_AXI_araddr[63:0] = axi_interconnect_0_M02_AXI_ARADDR;\n  assign M02_AXI_arburst[1:0] = axi_interconnect_0_M02_AXI_ARBURST;\n  assign M02_AXI_arcache[3:0] = axi_interconnect_0_M02_AXI_ARCACHE;\n  assign M02_AXI_arid[6:0] = axi_interconnect_0_M02_AXI_ARID;\n  assign M02_AXI_arlen[7:0] = axi_interconnect_0_M02_AXI_ARLEN;\n  assign M02_AXI_arlock[0] = axi_interconnect_0_M02_AXI_ARLOCK;\n  assign M02_AXI_arprot[2:0] = axi_interconnect_0_M02_AXI_ARPROT;\n  assign M02_AXI_arqos[3:0] = axi_interconnect_0_M02_AXI_ARQOS;\n  assign M02_AXI_arregion[3:0] = axi_interconnect_0_M02_AXI_ARREGION;\n  assign M02_AXI_arsize[2:0] = axi_interconnect_0_M02_AXI_ARSIZE;\n  assign M02_AXI_arvalid = axi_interconnect_0_M02_AXI_ARVALID;\n  assign M02_AXI_awaddr[63:0] = axi_interconnect_0_M02_AXI_AWADDR;\n  assign M02_AXI_awburst[1:0] = axi_interconnect_0_M02_AXI_AWBURST;\n  assign M02_AXI_awcache[3:0] = axi_interconnect_0_M02_AXI_AWCACHE;\n  assign M02_AXI_awid[6:0] = axi_interconnect_0_M02_AXI_AWID;\n  assign M02_AXI_awlen[7:0] = axi_interconnect_0_M02_AXI_AWLEN;\n  assign M02_AXI_awlock[0] = axi_interconnect_0_M02_AXI_AWLOCK;\n  assign M02_AXI_awprot[2:0] = axi_interconnect_0_M02_AXI_AWPROT;\n  assign M02_AXI_awqos[3:0] = axi_interconnect_0_M02_AXI_AWQOS;\n  assign M02_AXI_awregion[3:0] = axi_interconnect_0_M02_AXI_AWREGION;\n  assign M02_AXI_awsize[2:0] = axi_interconnect_0_M02_AXI_AWSIZE;\n  assign M02_AXI_awvalid = axi_interconnect_0_M02_AXI_AWVALID;\n  assign M02_AXI_bready = axi_interconnect_0_M02_AXI_BREADY;\n  assign M02_AXI_rready = axi_interconnect_0_M02_AXI_RREADY;\n  assign M02_AXI_wdata[511:0] = axi_interconnect_0_M02_AXI_WDATA;\n  assign M02_AXI_wlast = axi_interconnect_0_M02_AXI_WLAST;\n  assign M02_AXI_wstrb[63:0] = axi_interconnect_0_M02_AXI_WSTRB;\n  assign M02_AXI_wvalid = axi_interconnect_0_M02_AXI_WVALID;\n  assign M03_AXI_araddr[63:0] = axi_interconnect_0_M03_AXI_ARADDR;\n  assign M03_AXI_arburst[1:0] = axi_interconnect_0_M03_AXI_ARBURST;\n  assign M03_AXI_arcache[3:0] = axi_interconnect_0_M03_AXI_ARCACHE;\n  assign M03_AXI_arid[6:0] = axi_interconnect_0_M03_AXI_ARID;\n  assign M03_AXI_arlen[7:0] = axi_interconnect_0_M03_AXI_ARLEN;\n  assign M03_AXI_arlock[0] = axi_interconnect_0_M03_AXI_ARLOCK;\n  assign M03_AXI_arprot[2:0] = axi_interconnect_0_M03_AXI_ARPROT;\n  assign M03_AXI_arqos[3:0] = axi_interconnect_0_M03_AXI_ARQOS;\n  assign M03_AXI_arregion[3:0] = axi_interconnect_0_M03_AXI_ARREGION;\n  assign M03_AXI_arsize[2:0] = axi_interconnect_0_M03_AXI_ARSIZE;\n  assign M03_AXI_arvalid = axi_interconnect_0_M03_AXI_ARVALID;\n  assign M03_AXI_awaddr[63:0] = axi_interconnect_0_M03_AXI_AWADDR;\n  assign M03_AXI_awburst[1:0] = axi_interconnect_0_M03_AXI_AWBURST;\n  assign M03_AXI_awcache[3:0] = axi_interconnect_0_M03_AXI_AWCACHE;\n  assign M03_AXI_awid[6:0] = axi_interconnect_0_M03_AXI_AWID;\n  assign M03_AXI_awlen[7:0] = axi_interconnect_0_M03_AXI_AWLEN;\n  assign M03_AXI_awlock[0] = axi_interconnect_0_M03_AXI_AWLOCK;\n  assign M03_AXI_awprot[2:0] = axi_interconnect_0_M03_AXI_AWPROT;\n  assign M03_AXI_awqos[3:0] = axi_interconnect_0_M03_AXI_AWQOS;\n  assign M03_AXI_awregion[3:0] = axi_interconnect_0_M03_AXI_AWREGION;\n  assign M03_AXI_awsize[2:0] = axi_interconnect_0_M03_AXI_AWSIZE;\n  assign M03_AXI_awvalid = axi_interconnect_0_M03_AXI_AWVALID;\n  assign M03_AXI_bready = axi_interconnect_0_M03_AXI_BREADY;\n  assign M03_AXI_rready = axi_interconnect_0_M03_AXI_RREADY;\n  assign M03_AXI_wdata[511:0] = axi_interconnect_0_M03_AXI_WDATA;\n  assign M03_AXI_wlast = axi_interconnect_0_M03_AXI_WLAST;\n  assign M03_AXI_wstrb[63:0] = axi_interconnect_0_M03_AXI_WSTRB;\n  assign M03_AXI_wvalid = axi_interconnect_0_M03_AXI_WVALID;\n  assign S00_AXI_1_ARADDR = S00_AXI_araddr[63:0];\n  assign S00_AXI_1_ARBURST = S00_AXI_arburst[1:0];\n  assign S00_AXI_1_ARCACHE = S00_AXI_arcache[3:0];\n  assign S00_AXI_1_ARID = S00_AXI_arid[5:0];\n  assign S00_AXI_1_ARLEN = S00_AXI_arlen[7:0];\n  assign S00_AXI_1_ARLOCK = S00_AXI_arlock[0];\n  assign S00_AXI_1_ARPROT = S00_AXI_arprot[2:0];\n  assign S00_AXI_1_ARQOS = S00_AXI_arqos[3:0];\n  assign S00_AXI_1_ARREGION = S00_AXI_arregion[3:0];\n  assign S00_AXI_1_ARSIZE = S00_AXI_arsize[2:0];\n  assign S00_AXI_1_ARVALID = S00_AXI_arvalid;\n  assign S00_AXI_1_AWADDR = S00_AXI_awaddr[63:0];\n  assign S00_AXI_1_AWBURST = S00_AXI_awburst[1:0];\n  assign S00_AXI_1_AWCACHE = S00_AXI_awcache[3:0];\n  assign S00_AXI_1_AWID = S00_AXI_awid[5:0];\n  assign S00_AXI_1_AWLEN = S00_AXI_awlen[7:0];\n  assign S00_AXI_1_AWLOCK = S00_AXI_awlock[0];\n  assign S00_AXI_1_AWPROT = S00_AXI_awprot[2:0];\n  assign S00_AXI_1_AWQOS = S00_AXI_awqos[3:0];\n  assign S00_AXI_1_AWREGION = S00_AXI_awregion[3:0];\n  assign S00_AXI_1_AWSIZE = S00_AXI_awsize[2:0];\n  assign S00_AXI_1_AWVALID = S00_AXI_awvalid;\n  assign S00_AXI_1_BREADY = S00_AXI_bready;\n  assign S00_AXI_1_RREADY = S00_AXI_rready;\n  assign S00_AXI_1_WDATA = S00_AXI_wdata[511:0];\n  assign S00_AXI_1_WLAST = S00_AXI_wlast;\n  assign S00_AXI_1_WSTRB = S00_AXI_wstrb[63:0];\n  assign S00_AXI_1_WVALID = S00_AXI_wvalid;\n  assign S00_AXI_arready = S00_AXI_1_ARREADY;\n  assign S00_AXI_awready = S00_AXI_1_AWREADY;\n  assign S00_AXI_bid[5:0] = S00_AXI_1_BID;\n  assign S00_AXI_bresp[1:0] = S00_AXI_1_BRESP;\n  assign S00_AXI_bvalid = S00_AXI_1_BVALID;\n  assign S00_AXI_rdata[511:0] = S00_AXI_1_RDATA;\n  assign S00_AXI_rid[5:0] = S00_AXI_1_RID;\n  assign S00_AXI_rlast = S00_AXI_1_RLAST;\n  assign S00_AXI_rresp[1:0] = S00_AXI_1_RRESP;\n  assign S00_AXI_rvalid = S00_AXI_1_RVALID;\n  assign S00_AXI_wready = S00_AXI_1_WREADY;\n  assign S01_AXI_1_ARADDR = S01_AXI_araddr[63:0];\n  assign S01_AXI_1_ARBURST = S01_AXI_arburst[1:0];\n  assign S01_AXI_1_ARCACHE = S01_AXI_arcache[3:0];\n  assign S01_AXI_1_ARID = S01_AXI_arid[5:0];\n  assign S01_AXI_1_ARLEN = S01_AXI_arlen[7:0];\n  assign S01_AXI_1_ARLOCK = S01_AXI_arlock[0];\n  assign S01_AXI_1_ARPROT = S01_AXI_arprot[2:0];\n  assign S01_AXI_1_ARQOS = S01_AXI_arqos[3:0];\n  assign S01_AXI_1_ARREGION = S01_AXI_arregion[3:0];\n  assign S01_AXI_1_ARSIZE = S01_AXI_arsize[2:0];\n  assign S01_AXI_1_ARVALID = S01_AXI_arvalid;\n  assign S01_AXI_1_AWADDR = S01_AXI_awaddr[63:0];\n  assign S01_AXI_1_AWBURST = S01_AXI_awburst[1:0];\n  assign S01_AXI_1_AWCACHE = S01_AXI_awcache[3:0];\n  assign S01_AXI_1_AWID = S01_AXI_awid[5:0];\n  assign S01_AXI_1_AWLEN = S01_AXI_awlen[7:0];\n  assign S01_AXI_1_AWLOCK = S01_AXI_awlock[0];\n  assign S01_AXI_1_AWPROT = S01_AXI_awprot[2:0];\n  assign S01_AXI_1_AWQOS = S01_AXI_awqos[3:0];\n  assign S01_AXI_1_AWREGION = S01_AXI_awregion[3:0];\n  assign S01_AXI_1_AWSIZE = S01_AXI_awsize[2:0];\n  assign S01_AXI_1_AWVALID = S01_AXI_awvalid;\n  assign S01_AXI_1_BREADY = S01_AXI_bready;\n  assign S01_AXI_1_RREADY = S01_AXI_rready;\n  assign S01_AXI_1_WDATA = S01_AXI_wdata[511:0];\n  assign S01_AXI_1_WLAST = S01_AXI_wlast;\n  assign S01_AXI_1_WSTRB = S01_AXI_wstrb[63:0];\n  assign S01_AXI_1_WVALID = S01_AXI_wvalid;\n  assign S01_AXI_arready = S01_AXI_1_ARREADY;\n  assign S01_AXI_awready = S01_AXI_1_AWREADY;\n  assign S01_AXI_bid[5:0] = S01_AXI_1_BID;\n  assign S01_AXI_bresp[1:0] = S01_AXI_1_BRESP;\n  assign S01_AXI_bvalid = S01_AXI_1_BVALID;\n  assign S01_AXI_rdata[511:0] = S01_AXI_1_RDATA;\n  assign S01_AXI_rid[5:0] = S01_AXI_1_RID;\n  assign S01_AXI_rlast = S01_AXI_1_RLAST;\n  assign S01_AXI_rresp[1:0] = S01_AXI_1_RRESP;\n  assign S01_AXI_rvalid = S01_AXI_1_RVALID;\n  assign S01_AXI_wready = S01_AXI_1_WREADY;\n  assign axi_interconnect_0_M00_AXI_ARREADY = M00_AXI_arready;\n  assign axi_interconnect_0_M00_AXI_AWREADY = M00_AXI_awready;\n  assign axi_interconnect_0_M00_AXI_BID = M00_AXI_bid[6:0];\n  assign axi_interconnect_0_M00_AXI_BRESP = M00_AXI_bresp[1:0];\n  assign axi_interconnect_0_M00_AXI_BVALID = M00_AXI_bvalid;\n  assign axi_interconnect_0_M00_AXI_RDATA = M00_AXI_rdata[511:0];\n  assign axi_interconnect_0_M00_AXI_RID = M00_AXI_rid[6:0];\n  assign axi_interconnect_0_M00_AXI_RLAST = M00_AXI_rlast;\n  assign axi_interconnect_0_M00_AXI_RRESP = M00_AXI_rresp[1:0];\n  assign axi_interconnect_0_M00_AXI_RVALID = M00_AXI_rvalid;\n  assign axi_interconnect_0_M00_AXI_WREADY = M00_AXI_wready;\n  assign axi_interconnect_0_M01_AXI_ARREADY = M01_AXI_arready;\n  assign axi_interconnect_0_M01_AXI_AWREADY = M01_AXI_awready;\n  assign axi_interconnect_0_M01_AXI_BID = M01_AXI_bid[6:0];\n  assign axi_interconnect_0_M01_AXI_BRESP = M01_AXI_bresp[1:0];\n  assign axi_interconnect_0_M01_AXI_BVALID = M01_AXI_bvalid;\n  assign axi_interconnect_0_M01_AXI_RDATA = M01_AXI_rdata[511:0];\n  assign axi_interconnect_0_M01_AXI_RID = M01_AXI_rid[6:0];\n  assign axi_interconnect_0_M01_AXI_RLAST = M01_AXI_rlast;\n  assign axi_interconnect_0_M01_AXI_RRESP = M01_AXI_rresp[1:0];\n  assign axi_interconnect_0_M01_AXI_RVALID = M01_AXI_rvalid;\n  assign axi_interconnect_0_M01_AXI_WREADY = M01_AXI_wready;\n  assign axi_interconnect_0_M02_AXI_ARREADY = M02_AXI_arready;\n  assign axi_interconnect_0_M02_AXI_AWREADY = M02_AXI_awready;\n  assign axi_interconnect_0_M02_AXI_BID = M02_AXI_bid[6:0];\n  assign axi_interconnect_0_M02_AXI_BRESP = M02_AXI_bresp[1:0];\n  assign axi_interconnect_0_M02_AXI_BVALID = M02_AXI_bvalid;\n  assign axi_interconnect_0_M02_AXI_RDATA = M02_AXI_rdata[511:0];\n  assign axi_interconnect_0_M02_AXI_RID = M02_AXI_rid[6:0];\n  assign axi_interconnect_0_M02_AXI_RLAST = M02_AXI_rlast;\n  assign axi_interconnect_0_M02_AXI_RRESP = M02_AXI_rresp[1:0];\n  assign axi_interconnect_0_M02_AXI_RVALID = M02_AXI_rvalid;\n  assign axi_interconnect_0_M02_AXI_WREADY = M02_AXI_wready;\n  assign axi_interconnect_0_M03_AXI_ARREADY = M03_AXI_arready;\n  assign axi_interconnect_0_M03_AXI_AWREADY = M03_AXI_awready;\n  assign axi_interconnect_0_M03_AXI_BID = M03_AXI_bid[6:0];\n  assign axi_interconnect_0_M03_AXI_BRESP = M03_AXI_bresp[1:0];\n  assign axi_interconnect_0_M03_AXI_BVALID = M03_AXI_bvalid;\n  assign axi_interconnect_0_M03_AXI_RDATA = M03_AXI_rdata[511:0];\n  assign axi_interconnect_0_M03_AXI_RID = M03_AXI_rid[6:0];\n  assign axi_interconnect_0_M03_AXI_RLAST = M03_AXI_rlast;\n  assign axi_interconnect_0_M03_AXI_RRESP = M03_AXI_rresp[1:0];\n  assign axi_interconnect_0_M03_AXI_RVALID = M03_AXI_rvalid;\n  assign axi_interconnect_0_M03_AXI_WREADY = M03_AXI_wready;\n  cl_axi_interconnect_axi_interconnect_0_0 axi_interconnect_0\n       (.ACLK(ACLK_1),\n        .ARESETN(ARESETN_1),\n        .M00_ACLK(ACLK_1),\n        .M00_ARESETN(ARESETN_1),\n        .M00_AXI_araddr(axi_interconnect_0_M00_AXI_ARADDR),\n        .M00_AXI_arburst(axi_interconnect_0_M00_AXI_ARBURST),\n        .M00_AXI_arcache(axi_interconnect_0_M00_AXI_ARCACHE),\n        .M00_AXI_arid(axi_interconnect_0_M00_AXI_ARID),\n        .M00_AXI_arlen(axi_interconnect_0_M00_AXI_ARLEN),\n        .M00_AXI_arlock(axi_interconnect_0_M00_AXI_ARLOCK),\n        .M00_AXI_arprot(axi_interconnect_0_M00_AXI_ARPROT),\n        .M00_AXI_arqos(axi_interconnect_0_M00_AXI_ARQOS),\n        .M00_AXI_arready(axi_interconnect_0_M00_AXI_ARREADY),\n        .M00_AXI_arregion(axi_interconnect_0_M00_AXI_ARREGION),\n        .M00_AXI_arsize(axi_interconnect_0_M00_AXI_ARSIZE),\n        .M00_AXI_arvalid(axi_interconnect_0_M00_AXI_ARVALID),\n        .M00_AXI_awaddr(axi_interconnect_0_M00_AXI_AWADDR),\n        .M00_AXI_awburst(axi_interconnect_0_M00_AXI_AWBURST),\n        .M00_AXI_awcache(axi_interconnect_0_M00_AXI_AWCACHE),\n        .M00_AXI_awid(axi_interconnect_0_M00_AXI_AWID),\n        .M00_AXI_awlen(axi_interconnect_0_M00_AXI_AWLEN),\n        .M00_AXI_awlock(axi_interconnect_0_M00_AXI_AWLOCK),\n        .M00_AXI_awprot(axi_interconnect_0_M00_AXI_AWPROT),\n        .M00_AXI_awqos(axi_interconnect_0_M00_AXI_AWQOS),\n        .M00_AXI_awready(axi_interconnect_0_M00_AXI_AWREADY),\n        .M00_AXI_awregion(axi_interconnect_0_M00_AXI_AWREGION),\n        .M00_AXI_awsize(axi_interconnect_0_M00_AXI_AWSIZE),\n        .M00_AXI_awvalid(axi_interconnect_0_M00_AXI_AWVALID),\n        .M00_AXI_bid(axi_interconnect_0_M00_AXI_BID),\n        .M00_AXI_bready(axi_interconnect_0_M00_AXI_BREADY),\n        .M00_AXI_bresp(axi_interconnect_0_M00_AXI_BRESP),\n        .M00_AXI_bvalid(axi_interconnect_0_M00_AXI_BVALID),\n        .M00_AXI_rdata(axi_interconnect_0_M00_AXI_RDATA),\n        .M00_AXI_rid(axi_interconnect_0_M00_AXI_RID),\n        .M00_AXI_rlast(axi_interconnect_0_M00_AXI_RLAST),\n        .M00_AXI_rready(axi_interconnect_0_M00_AXI_RREADY),\n        .M00_AXI_rresp(axi_interconnect_0_M00_AXI_RRESP),\n        .M00_AXI_rvalid(axi_interconnect_0_M00_AXI_RVALID),\n        .M00_AXI_wdata(axi_interconnect_0_M00_AXI_WDATA),\n        .M00_AXI_wlast(axi_interconnect_0_M00_AXI_WLAST),\n        .M00_AXI_wready(axi_interconnect_0_M00_AXI_WREADY),\n        .M00_AXI_wstrb(axi_interconnect_0_M00_AXI_WSTRB),\n        .M00_AXI_wvalid(axi_interconnect_0_M00_AXI_WVALID),\n        .M01_ACLK(ACLK_1),\n        .M01_ARESETN(ARESETN_1),\n        .M01_AXI_araddr(axi_interconnect_0_M01_AXI_ARADDR),\n        .M01_AXI_arburst(axi_interconnect_0_M01_AXI_ARBURST),\n        .M01_AXI_arcache(axi_interconnect_0_M01_AXI_ARCACHE),\n        .M01_AXI_arid(axi_interconnect_0_M01_AXI_ARID),\n        .M01_AXI_arlen(axi_interconnect_0_M01_AXI_ARLEN),\n        .M01_AXI_arlock(axi_interconnect_0_M01_AXI_ARLOCK),\n        .M01_AXI_arprot(axi_interconnect_0_M01_AXI_ARPROT),\n        .M01_AXI_arqos(axi_interconnect_0_M01_AXI_ARQOS),\n        .M01_AXI_arready(axi_interconnect_0_M01_AXI_ARREADY),\n        .M01_AXI_arregion(axi_interconnect_0_M01_AXI_ARREGION),\n        .M01_AXI_arsize(axi_interconnect_0_M01_AXI_ARSIZE),\n        .M01_AXI_arvalid(axi_interconnect_0_M01_AXI_ARVALID),\n        .M01_AXI_awaddr(axi_interconnect_0_M01_AXI_AWADDR),\n        .M01_AXI_awburst(axi_interconnect_0_M01_AXI_AWBURST),\n        .M01_AXI_awcache(axi_interconnect_0_M01_AXI_AWCACHE),\n        .M01_AXI_awid(axi_interconnect_0_M01_AXI_AWID),\n        .M01_AXI_awlen(axi_interconnect_0_M01_AXI_AWLEN),\n        .M01_AXI_awlock(axi_interconnect_0_M01_AXI_AWLOCK),\n        .M01_AXI_awprot(axi_interconnect_0_M01_AXI_AWPROT),\n        .M01_AXI_awqos(axi_interconnect_0_M01_AXI_AWQOS),\n        .M01_AXI_awready(axi_interconnect_0_M01_AXI_AWREADY),\n        .M01_AXI_awregion(axi_interconnect_0_M01_AXI_AWREGION),\n        .M01_AXI_awsize(axi_interconnect_0_M01_AXI_AWSIZE),\n        .M01_AXI_awvalid(axi_interconnect_0_M01_AXI_AWVALID),\n        .M01_AXI_bid(axi_interconnect_0_M01_AXI_BID),\n        .M01_AXI_bready(axi_interconnect_0_M01_AXI_BREADY),\n        .M01_AXI_bresp(axi_interconnect_0_M01_AXI_BRESP),\n        .M01_AXI_bvalid(axi_interconnect_0_M01_AXI_BVALID),\n        .M01_AXI_rdata(axi_interconnect_0_M01_AXI_RDATA),\n        .M01_AXI_rid(axi_interconnect_0_M01_AXI_RID),\n        .M01_AXI_rlast(axi_interconnect_0_M01_AXI_RLAST),\n        .M01_AXI_rready(axi_interconnect_0_M01_AXI_RREADY),\n        .M01_AXI_rresp(axi_interconnect_0_M01_AXI_RRESP),\n        .M01_AXI_rvalid(axi_interconnect_0_M01_AXI_RVALID),\n        .M01_AXI_wdata(axi_interconnect_0_M01_AXI_WDATA),\n        .M01_AXI_wlast(axi_interconnect_0_M01_AXI_WLAST),\n        .M01_AXI_wready(axi_interconnect_0_M01_AXI_WREADY),\n        .M01_AXI_wstrb(axi_interconnect_0_M01_AXI_WSTRB),\n        .M01_AXI_wvalid(axi_interconnect_0_M01_AXI_WVALID),\n        .M02_ACLK(ACLK_1),\n        .M02_ARESETN(ARESETN_1),\n        .M02_AXI_araddr(axi_interconnect_0_M02_AXI_ARADDR),\n        .M02_AXI_arburst(axi_interconnect_0_M02_AXI_ARBURST),\n        .M02_AXI_arcache(axi_interconnect_0_M02_AXI_ARCACHE),\n        .M02_AXI_arid(axi_interconnect_0_M02_AXI_ARID),\n        .M02_AXI_arlen(axi_interconnect_0_M02_AXI_ARLEN),\n        .M02_AXI_arlock(axi_interconnect_0_M02_AXI_ARLOCK),\n        .M02_AXI_arprot(axi_interconnect_0_M02_AXI_ARPROT),\n        .M02_AXI_arqos(axi_interconnect_0_M02_AXI_ARQOS),\n        .M02_AXI_arready(axi_interconnect_0_M02_AXI_ARREADY),\n        .M02_AXI_arregion(axi_interconnect_0_M02_AXI_ARREGION),\n        .M02_AXI_arsize(axi_interconnect_0_M02_AXI_ARSIZE),\n        .M02_AXI_arvalid(axi_interconnect_0_M02_AXI_ARVALID),\n        .M02_AXI_awaddr(axi_interconnect_0_M02_AXI_AWADDR),\n        .M02_AXI_awburst(axi_interconnect_0_M02_AXI_AWBURST),\n        .M02_AXI_awcache(axi_interconnect_0_M02_AXI_AWCACHE),\n        .M02_AXI_awid(axi_interconnect_0_M02_AXI_AWID),\n        .M02_AXI_awlen(axi_interconnect_0_M02_AXI_AWLEN),\n        .M02_AXI_awlock(axi_interconnect_0_M02_AXI_AWLOCK),\n        .M02_AXI_awprot(axi_interconnect_0_M02_AXI_AWPROT),\n        .M02_AXI_awqos(axi_interconnect_0_M02_AXI_AWQOS),\n        .M02_AXI_awready(axi_interconnect_0_M02_AXI_AWREADY),\n        .M02_AXI_awregion(axi_interconnect_0_M02_AXI_AWREGION),\n        .M02_AXI_awsize(axi_interconnect_0_M02_AXI_AWSIZE),\n        .M02_AXI_awvalid(axi_interconnect_0_M02_AXI_AWVALID),\n        .M02_AXI_bid(axi_interconnect_0_M02_AXI_BID),\n        .M02_AXI_bready(axi_interconnect_0_M02_AXI_BREADY),\n        .M02_AXI_bresp(axi_interconnect_0_M02_AXI_BRESP),\n        .M02_AXI_bvalid(axi_interconnect_0_M02_AXI_BVALID),\n        .M02_AXI_rdata(axi_interconnect_0_M02_AXI_RDATA),\n        .M02_AXI_rid(axi_interconnect_0_M02_AXI_RID),\n        .M02_AXI_rlast(axi_interconnect_0_M02_AXI_RLAST),\n        .M02_AXI_rready(axi_interconnect_0_M02_AXI_RREADY),\n        .M02_AXI_rresp(axi_interconnect_0_M02_AXI_RRESP),\n        .M02_AXI_rvalid(axi_interconnect_0_M02_AXI_RVALID),\n        .M02_AXI_wdata(axi_interconnect_0_M02_AXI_WDATA),\n        .M02_AXI_wlast(axi_interconnect_0_M02_AXI_WLAST),\n        .M02_AXI_wready(axi_interconnect_0_M02_AXI_WREADY),\n        .M02_AXI_wstrb(axi_interconnect_0_M02_AXI_WSTRB),\n        .M02_AXI_wvalid(axi_interconnect_0_M02_AXI_WVALID),\n        .M03_ACLK(ACLK_1),\n        .M03_ARESETN(ARESETN_1),\n        .M03_AXI_araddr(axi_interconnect_0_M03_AXI_ARADDR),\n        .M03_AXI_arburst(axi_interconnect_0_M03_AXI_ARBURST),\n        .M03_AXI_arcache(axi_interconnect_0_M03_AXI_ARCACHE),\n        .M03_AXI_arid(axi_interconnect_0_M03_AXI_ARID),\n        .M03_AXI_arlen(axi_interconnect_0_M03_AXI_ARLEN),\n        .M03_AXI_arlock(axi_interconnect_0_M03_AXI_ARLOCK),\n        .M03_AXI_arprot(axi_interconnect_0_M03_AXI_ARPROT),\n        .M03_AXI_arqos(axi_interconnect_0_M03_AXI_ARQOS),\n        .M03_AXI_arready(axi_interconnect_0_M03_AXI_ARREADY),\n        .M03_AXI_arregion(axi_interconnect_0_M03_AXI_ARREGION),\n        .M03_AXI_arsize(axi_interconnect_0_M03_AXI_ARSIZE),\n        .M03_AXI_arvalid(axi_interconnect_0_M03_AXI_ARVALID),\n        .M03_AXI_awaddr(axi_interconnect_0_M03_AXI_AWADDR),\n        .M03_AXI_awburst(axi_interconnect_0_M03_AXI_AWBURST),\n        .M03_AXI_awcache(axi_interconnect_0_M03_AXI_AWCACHE),\n        .M03_AXI_awid(axi_interconnect_0_M03_AXI_AWID),\n        .M03_AXI_awlen(axi_interconnect_0_M03_AXI_AWLEN),\n        .M03_AXI_awlock(axi_interconnect_0_M03_AXI_AWLOCK),\n        .M03_AXI_awprot(axi_interconnect_0_M03_AXI_AWPROT),\n        .M03_AXI_awqos(axi_interconnect_0_M03_AXI_AWQOS),\n        .M03_AXI_awready(axi_interconnect_0_M03_AXI_AWREADY),\n        .M03_AXI_awregion(axi_interconnect_0_M03_AXI_AWREGION),\n        .M03_AXI_awsize(axi_interconnect_0_M03_AXI_AWSIZE),\n        .M03_AXI_awvalid(axi_interconnect_0_M03_AXI_AWVALID),\n        .M03_AXI_bid(axi_interconnect_0_M03_AXI_BID),\n        .M03_AXI_bready(axi_interconnect_0_M03_AXI_BREADY),\n        .M03_AXI_bresp(axi_interconnect_0_M03_AXI_BRESP),\n        .M03_AXI_bvalid(axi_interconnect_0_M03_AXI_BVALID),\n        .M03_AXI_rdata(axi_interconnect_0_M03_AXI_RDATA),\n        .M03_AXI_rid(axi_interconnect_0_M03_AXI_RID),\n        .M03_AXI_rlast(axi_interconnect_0_M03_AXI_RLAST),\n        .M03_AXI_rready(axi_interconnect_0_M03_AXI_RREADY),\n        .M03_AXI_rresp(axi_interconnect_0_M03_AXI_RRESP),\n        .M03_AXI_rvalid(axi_interconnect_0_M03_AXI_RVALID),\n        .M03_AXI_wdata(axi_interconnect_0_M03_AXI_WDATA),\n        .M03_AXI_wlast(axi_interconnect_0_M03_AXI_WLAST),\n        .M03_AXI_wready(axi_interconnect_0_M03_AXI_WREADY),\n        .M03_AXI_wstrb(axi_interconnect_0_M03_AXI_WSTRB),\n        .M03_AXI_wvalid(axi_interconnect_0_M03_AXI_WVALID),\n        .S00_ACLK(ACLK_1),\n        .S00_ARESETN(ARESETN_1),\n        .S00_AXI_araddr(S00_AXI_1_ARADDR),\n        .S00_AXI_arburst(S00_AXI_1_ARBURST),\n        .S00_AXI_arcache(S00_AXI_1_ARCACHE),\n        .S00_AXI_arid(S00_AXI_1_ARID),\n        .S00_AXI_arlen(S00_AXI_1_ARLEN),\n        .S00_AXI_arlock(S00_AXI_1_ARLOCK),\n        .S00_AXI_arprot(S00_AXI_1_ARPROT),\n        .S00_AXI_arqos(S00_AXI_1_ARQOS),\n        .S00_AXI_arready(S00_AXI_1_ARREADY),\n        .S00_AXI_arregion(S00_AXI_1_ARREGION),\n        .S00_AXI_arsize(S00_AXI_1_ARSIZE),\n        .S00_AXI_arvalid(S00_AXI_1_ARVALID),\n        .S00_AXI_awaddr(S00_AXI_1_AWADDR),\n        .S00_AXI_awburst(S00_AXI_1_AWBURST),\n        .S00_AXI_awcache(S00_AXI_1_AWCACHE),\n        .S00_AXI_awid(S00_AXI_1_AWID),\n        .S00_AXI_awlen(S00_AXI_1_AWLEN),\n        .S00_AXI_awlock(S00_AXI_1_AWLOCK),\n        .S00_AXI_awprot(S00_AXI_1_AWPROT),\n        .S00_AXI_awqos(S00_AXI_1_AWQOS),\n        .S00_AXI_awready(S00_AXI_1_AWREADY),\n        .S00_AXI_awregion(S00_AXI_1_AWREGION),\n        .S00_AXI_awsize(S00_AXI_1_AWSIZE),\n        .S00_AXI_awvalid(S00_AXI_1_AWVALID),\n        .S00_AXI_bid(S00_AXI_1_BID),\n        .S00_AXI_bready(S00_AXI_1_BREADY),\n        .S00_AXI_bresp(S00_AXI_1_BRESP),\n        .S00_AXI_bvalid(S00_AXI_1_BVALID),\n        .S00_AXI_rdata(S00_AXI_1_RDATA),\n        .S00_AXI_rid(S00_AXI_1_RID),\n        .S00_AXI_rlast(S00_AXI_1_RLAST),\n        .S00_AXI_rready(S00_AXI_1_RREADY),\n        .S00_AXI_rresp(S00_AXI_1_RRESP),\n        .S00_AXI_rvalid(S00_AXI_1_RVALID),\n        .S00_AXI_wdata(S00_AXI_1_WDATA),\n        .S00_AXI_wlast(S00_AXI_1_WLAST),\n        .S00_AXI_wready(S00_AXI_1_WREADY),\n        .S00_AXI_wstrb(S00_AXI_1_WSTRB),\n        .S00_AXI_wvalid(S00_AXI_1_WVALID),\n        .S01_ACLK(ACLK_1),\n        .S01_ARESETN(ARESETN_1),\n        .S01_AXI_araddr(S01_AXI_1_ARADDR),\n        .S01_AXI_arburst(S01_AXI_1_ARBURST),\n        .S01_AXI_arcache(S01_AXI_1_ARCACHE),\n        .S01_AXI_arid(S01_AXI_1_ARID),\n        .S01_AXI_arlen(S01_AXI_1_ARLEN),\n        .S01_AXI_arlock(S01_AXI_1_ARLOCK),\n        .S01_AXI_arprot(S01_AXI_1_ARPROT),\n        .S01_AXI_arqos(S01_AXI_1_ARQOS),\n        .S01_AXI_arready(S01_AXI_1_ARREADY),\n        .S01_AXI_arregion(S01_AXI_1_ARREGION),\n        .S01_AXI_arsize(S01_AXI_1_ARSIZE),\n        .S01_AXI_arvalid(S01_AXI_1_ARVALID),\n        .S01_AXI_awaddr(S01_AXI_1_AWADDR),\n        .S01_AXI_awburst(S01_AXI_1_AWBURST),\n        .S01_AXI_awcache(S01_AXI_1_AWCACHE),\n        .S01_AXI_awid(S01_AXI_1_AWID),\n        .S01_AXI_awlen(S01_AXI_1_AWLEN),\n        .S01_AXI_awlock(S01_AXI_1_AWLOCK),\n        .S01_AXI_awprot(S01_AXI_1_AWPROT),\n        .S01_AXI_awqos(S01_AXI_1_AWQOS),\n        .S01_AXI_awready(S01_AXI_1_AWREADY),\n        .S01_AXI_awregion(S01_AXI_1_AWREGION),\n        .S01_AXI_awsize(S01_AXI_1_AWSIZE),\n        .S01_AXI_awvalid(S01_AXI_1_AWVALID),\n        .S01_AXI_bid(S01_AXI_1_BID),\n        .S01_AXI_bready(S01_AXI_1_BREADY),\n        .S01_AXI_bresp(S01_AXI_1_BRESP),\n        .S01_AXI_bvalid(S01_AXI_1_BVALID),\n        .S01_AXI_rdata(S01_AXI_1_RDATA),\n        .S01_AXI_rid(S01_AXI_1_RID),\n        .S01_AXI_rlast(S01_AXI_1_RLAST),\n        .S01_AXI_rready(S01_AXI_1_RREADY),\n        .S01_AXI_rresp(S01_AXI_1_RRESP),\n        .S01_AXI_rvalid(S01_AXI_1_RVALID),\n        .S01_AXI_wdata(S01_AXI_1_WDATA),\n        .S01_AXI_wlast(S01_AXI_1_WLAST),\n        .S01_AXI_wready(S01_AXI_1_WREADY),\n        .S01_AXI_wstrb(S01_AXI_1_WSTRB),\n        .S01_AXI_wvalid(S01_AXI_1_WVALID));\nendmodule\n\nmodule cl_axi_interconnect_axi_interconnect_0_0\n   (ACLK,\n    ARESETN,\n    M00_ACLK,\n    M00_ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_ACLK,\n    M01_ARESETN,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_ACLK,\n    M02_ARESETN,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_ACLK,\n    M03_ARESETN,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_ACLK,\n    S00_ARESETN,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_ACLK,\n    S01_ARESETN,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  input ACLK;\n  input ARESETN;\n  input M00_ACLK;\n  input M00_ARESETN;\n  output [63:0]M00_AXI_araddr;\n  output [1:0]M00_AXI_arburst;\n  output [3:0]M00_AXI_arcache;\n  output [6:0]M00_AXI_arid;\n  output [7:0]M00_AXI_arlen;\n  output [0:0]M00_AXI_arlock;\n  output [2:0]M00_AXI_arprot;\n  output [3:0]M00_AXI_arqos;\n  input M00_AXI_arready;\n  output [3:0]M00_AXI_arregion;\n  output [2:0]M00_AXI_arsize;\n  output M00_AXI_arvalid;\n  output [63:0]M00_AXI_awaddr;\n  output [1:0]M00_AXI_awburst;\n  output [3:0]M00_AXI_awcache;\n  output [6:0]M00_AXI_awid;\n  output [7:0]M00_AXI_awlen;\n  output [0:0]M00_AXI_awlock;\n  output [2:0]M00_AXI_awprot;\n  output [3:0]M00_AXI_awqos;\n  input M00_AXI_awready;\n  output [3:0]M00_AXI_awregion;\n  output [2:0]M00_AXI_awsize;\n  output M00_AXI_awvalid;\n  input [6:0]M00_AXI_bid;\n  output M00_AXI_bready;\n  input [1:0]M00_AXI_bresp;\n  input M00_AXI_bvalid;\n  input [511:0]M00_AXI_rdata;\n  input [6:0]M00_AXI_rid;\n  input M00_AXI_rlast;\n  output M00_AXI_rready;\n  input [1:0]M00_AXI_rresp;\n  input M00_AXI_rvalid;\n  output [511:0]M00_AXI_wdata;\n  output M00_AXI_wlast;\n  input M00_AXI_wready;\n  output [63:0]M00_AXI_wstrb;\n  output M00_AXI_wvalid;\n  input M01_ACLK;\n  input M01_ARESETN;\n  output [63:0]M01_AXI_araddr;\n  output [1:0]M01_AXI_arburst;\n  output [3:0]M01_AXI_arcache;\n  output [6:0]M01_AXI_arid;\n  output [7:0]M01_AXI_arlen;\n  output [0:0]M01_AXI_arlock;\n  output [2:0]M01_AXI_arprot;\n  output [3:0]M01_AXI_arqos;\n  input M01_AXI_arready;\n  output [3:0]M01_AXI_arregion;\n  output [2:0]M01_AXI_arsize;\n  output M01_AXI_arvalid;\n  output [63:0]M01_AXI_awaddr;\n  output [1:0]M01_AXI_awburst;\n  output [3:0]M01_AXI_awcache;\n  output [6:0]M01_AXI_awid;\n  output [7:0]M01_AXI_awlen;\n  output [0:0]M01_AXI_awlock;\n  output [2:0]M01_AXI_awprot;\n  output [3:0]M01_AXI_awqos;\n  input M01_AXI_awready;\n  output [3:0]M01_AXI_awregion;\n  output [2:0]M01_AXI_awsize;\n  output M01_AXI_awvalid;\n  input [6:0]M01_AXI_bid;\n  output M01_AXI_bready;\n  input [1:0]M01_AXI_bresp;\n  input M01_AXI_bvalid;\n  input [511:0]M01_AXI_rdata;\n  input [6:0]M01_AXI_rid;\n  input M01_AXI_rlast;\n  output M01_AXI_rready;\n  input [1:0]M01_AXI_rresp;\n  input M01_AXI_rvalid;\n  output [511:0]M01_AXI_wdata;\n  output M01_AXI_wlast;\n  input M01_AXI_wready;\n  output [63:0]M01_AXI_wstrb;\n  output M01_AXI_wvalid;\n  input M02_ACLK;\n  input M02_ARESETN;\n  output [63:0]M02_AXI_araddr;\n  output [1:0]M02_AXI_arburst;\n  output [3:0]M02_AXI_arcache;\n  output [6:0]M02_AXI_arid;\n  output [7:0]M02_AXI_arlen;\n  output [0:0]M02_AXI_arlock;\n  output [2:0]M02_AXI_arprot;\n  output [3:0]M02_AXI_arqos;\n  input M02_AXI_arready;\n  output [3:0]M02_AXI_arregion;\n  output [2:0]M02_AXI_arsize;\n  output M02_AXI_arvalid;\n  output [63:0]M02_AXI_awaddr;\n  output [1:0]M02_AXI_awburst;\n  output [3:0]M02_AXI_awcache;\n  output [6:0]M02_AXI_awid;\n  output [7:0]M02_AXI_awlen;\n  output [0:0]M02_AXI_awlock;\n  output [2:0]M02_AXI_awprot;\n  output [3:0]M02_AXI_awqos;\n  input M02_AXI_awready;\n  output [3:0]M02_AXI_awregion;\n  output [2:0]M02_AXI_awsize;\n  output M02_AXI_awvalid;\n  input [6:0]M02_AXI_bid;\n  output M02_AXI_bready;\n  input [1:0]M02_AXI_bresp;\n  input M02_AXI_bvalid;\n  input [511:0]M02_AXI_rdata;\n  input [6:0]M02_AXI_rid;\n  input M02_AXI_rlast;\n  output M02_AXI_rready;\n  input [1:0]M02_AXI_rresp;\n  input M02_AXI_rvalid;\n  output [511:0]M02_AXI_wdata;\n  output M02_AXI_wlast;\n  input M02_AXI_wready;\n  output [63:0]M02_AXI_wstrb;\n  output M02_AXI_wvalid;\n  input M03_ACLK;\n  input M03_ARESETN;\n  output [63:0]M03_AXI_araddr;\n  output [1:0]M03_AXI_arburst;\n  output [3:0]M03_AXI_arcache;\n  output [6:0]M03_AXI_arid;\n  output [7:0]M03_AXI_arlen;\n  output [0:0]M03_AXI_arlock;\n  output [2:0]M03_AXI_arprot;\n  output [3:0]M03_AXI_arqos;\n  input M03_AXI_arready;\n  output [3:0]M03_AXI_arregion;\n  output [2:0]M03_AXI_arsize;\n  output M03_AXI_arvalid;\n  output [63:0]M03_AXI_awaddr;\n  output [1:0]M03_AXI_awburst;\n  output [3:0]M03_AXI_awcache;\n  output [6:0]M03_AXI_awid;\n  output [7:0]M03_AXI_awlen;\n  output [0:0]M03_AXI_awlock;\n  output [2:0]M03_AXI_awprot;\n  output [3:0]M03_AXI_awqos;\n  input M03_AXI_awready;\n  output [3:0]M03_AXI_awregion;\n  output [2:0]M03_AXI_awsize;\n  output M03_AXI_awvalid;\n  input [6:0]M03_AXI_bid;\n  output M03_AXI_bready;\n  input [1:0]M03_AXI_bresp;\n  input M03_AXI_bvalid;\n  input [511:0]M03_AXI_rdata;\n  input [6:0]M03_AXI_rid;\n  input M03_AXI_rlast;\n  output M03_AXI_rready;\n  input [1:0]M03_AXI_rresp;\n  input M03_AXI_rvalid;\n  output [511:0]M03_AXI_wdata;\n  output M03_AXI_wlast;\n  input M03_AXI_wready;\n  output [63:0]M03_AXI_wstrb;\n  output M03_AXI_wvalid;\n  input S00_ACLK;\n  input S00_ARESETN;\n  input [63:0]S00_AXI_araddr;\n  input [1:0]S00_AXI_arburst;\n  input [3:0]S00_AXI_arcache;\n  input [5:0]S00_AXI_arid;\n  input [7:0]S00_AXI_arlen;\n  input [0:0]S00_AXI_arlock;\n  input [2:0]S00_AXI_arprot;\n  input [3:0]S00_AXI_arqos;\n  output S00_AXI_arready;\n  input [3:0]S00_AXI_arregion;\n  input [2:0]S00_AXI_arsize;\n  input S00_AXI_arvalid;\n  input [63:0]S00_AXI_awaddr;\n  input [1:0]S00_AXI_awburst;\n  input [3:0]S00_AXI_awcache;\n  input [5:0]S00_AXI_awid;\n  input [7:0]S00_AXI_awlen;\n  input [0:0]S00_AXI_awlock;\n  input [2:0]S00_AXI_awprot;\n  input [3:0]S00_AXI_awqos;\n  output S00_AXI_awready;\n  input [3:0]S00_AXI_awregion;\n  input [2:0]S00_AXI_awsize;\n  input S00_AXI_awvalid;\n  output [5:0]S00_AXI_bid;\n  input S00_AXI_bready;\n  output [1:0]S00_AXI_bresp;\n  output S00_AXI_bvalid;\n  output [511:0]S00_AXI_rdata;\n  output [5:0]S00_AXI_rid;\n  output S00_AXI_rlast;\n  input S00_AXI_rready;\n  output [1:0]S00_AXI_rresp;\n  output S00_AXI_rvalid;\n  input [511:0]S00_AXI_wdata;\n  input S00_AXI_wlast;\n  output S00_AXI_wready;\n  input [63:0]S00_AXI_wstrb;\n  input S00_AXI_wvalid;\n  input S01_ACLK;\n  input S01_ARESETN;\n  input [63:0]S01_AXI_araddr;\n  input [1:0]S01_AXI_arburst;\n  input [3:0]S01_AXI_arcache;\n  input [5:0]S01_AXI_arid;\n  input [7:0]S01_AXI_arlen;\n  input [0:0]S01_AXI_arlock;\n  input [2:0]S01_AXI_arprot;\n  input [3:0]S01_AXI_arqos;\n  output S01_AXI_arready;\n  input [3:0]S01_AXI_arregion;\n  input [2:0]S01_AXI_arsize;\n  input S01_AXI_arvalid;\n  input [63:0]S01_AXI_awaddr;\n  input [1:0]S01_AXI_awburst;\n  input [3:0]S01_AXI_awcache;\n  input [5:0]S01_AXI_awid;\n  input [7:0]S01_AXI_awlen;\n  input [0:0]S01_AXI_awlock;\n  input [2:0]S01_AXI_awprot;\n  input [3:0]S01_AXI_awqos;\n  output S01_AXI_awready;\n  input [3:0]S01_AXI_awregion;\n  input [2:0]S01_AXI_awsize;\n  input S01_AXI_awvalid;\n  output [5:0]S01_AXI_bid;\n  input S01_AXI_bready;\n  output [1:0]S01_AXI_bresp;\n  output S01_AXI_bvalid;\n  output [511:0]S01_AXI_rdata;\n  output [5:0]S01_AXI_rid;\n  output S01_AXI_rlast;\n  input S01_AXI_rready;\n  output [1:0]S01_AXI_rresp;\n  output S01_AXI_rvalid;\n  input [511:0]S01_AXI_wdata;\n  input S01_AXI_wlast;\n  output S01_AXI_wready;\n  input [63:0]S01_AXI_wstrb;\n  input S01_AXI_wvalid;\n\n  wire axi_interconnect_0_ACLK_net;\n  wire axi_interconnect_0_ARESETN_net;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_ARADDR;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_ARBURST;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARCACHE;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_ARID;\n  wire [7:0]axi_interconnect_0_to_s00_couplers_ARLEN;\n  wire [0:0]axi_interconnect_0_to_s00_couplers_ARLOCK;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_ARPROT;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARQOS;\n  wire axi_interconnect_0_to_s00_couplers_ARREADY;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARREGION;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_ARSIZE;\n  wire axi_interconnect_0_to_s00_couplers_ARVALID;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_AWADDR;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_AWBURST;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWCACHE;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_AWID;\n  wire [7:0]axi_interconnect_0_to_s00_couplers_AWLEN;\n  wire [0:0]axi_interconnect_0_to_s00_couplers_AWLOCK;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_AWPROT;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWQOS;\n  wire axi_interconnect_0_to_s00_couplers_AWREADY;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWREGION;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_AWSIZE;\n  wire axi_interconnect_0_to_s00_couplers_AWVALID;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_BID;\n  wire axi_interconnect_0_to_s00_couplers_BREADY;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_BRESP;\n  wire axi_interconnect_0_to_s00_couplers_BVALID;\n  wire [511:0]axi_interconnect_0_to_s00_couplers_RDATA;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_RID;\n  wire axi_interconnect_0_to_s00_couplers_RLAST;\n  wire axi_interconnect_0_to_s00_couplers_RREADY;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_RRESP;\n  wire axi_interconnect_0_to_s00_couplers_RVALID;\n  wire [511:0]axi_interconnect_0_to_s00_couplers_WDATA;\n  wire axi_interconnect_0_to_s00_couplers_WLAST;\n  wire axi_interconnect_0_to_s00_couplers_WREADY;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_WSTRB;\n  wire axi_interconnect_0_to_s00_couplers_WVALID;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_ARADDR;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_ARBURST;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARCACHE;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_ARID;\n  wire [7:0]axi_interconnect_0_to_s01_couplers_ARLEN;\n  wire [0:0]axi_interconnect_0_to_s01_couplers_ARLOCK;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_ARPROT;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARQOS;\n  wire axi_interconnect_0_to_s01_couplers_ARREADY;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARREGION;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_ARSIZE;\n  wire axi_interconnect_0_to_s01_couplers_ARVALID;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_AWADDR;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_AWBURST;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWCACHE;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_AWID;\n  wire [7:0]axi_interconnect_0_to_s01_couplers_AWLEN;\n  wire [0:0]axi_interconnect_0_to_s01_couplers_AWLOCK;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_AWPROT;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWQOS;\n  wire axi_interconnect_0_to_s01_couplers_AWREADY;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWREGION;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_AWSIZE;\n  wire axi_interconnect_0_to_s01_couplers_AWVALID;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_BID;\n  wire axi_interconnect_0_to_s01_couplers_BREADY;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_BRESP;\n  wire axi_interconnect_0_to_s01_couplers_BVALID;\n  wire [511:0]axi_interconnect_0_to_s01_couplers_RDATA;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_RID;\n  wire axi_interconnect_0_to_s01_couplers_RLAST;\n  wire axi_interconnect_0_to_s01_couplers_RREADY;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_RRESP;\n  wire axi_interconnect_0_to_s01_couplers_RVALID;\n  wire [511:0]axi_interconnect_0_to_s01_couplers_WDATA;\n  wire axi_interconnect_0_to_s01_couplers_WLAST;\n  wire axi_interconnect_0_to_s01_couplers_WREADY;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_WSTRB;\n  wire axi_interconnect_0_to_s01_couplers_WVALID;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m00_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m00_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARQOS;\n  wire m00_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m00_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m00_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m00_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWQOS;\n  wire m00_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m00_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_BID;\n  wire m00_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_BRESP;\n  wire m00_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m00_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_RID;\n  wire m00_couplers_to_axi_interconnect_0_RLAST;\n  wire m00_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_RRESP;\n  wire m00_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m00_couplers_to_axi_interconnect_0_WDATA;\n  wire m00_couplers_to_axi_interconnect_0_WLAST;\n  wire m00_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_WSTRB;\n  wire m00_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m01_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m01_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARQOS;\n  wire m01_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m01_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m01_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m01_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWQOS;\n  wire m01_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m01_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_BID;\n  wire m01_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_BRESP;\n  wire m01_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m01_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_RID;\n  wire m01_couplers_to_axi_interconnect_0_RLAST;\n  wire m01_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_RRESP;\n  wire m01_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m01_couplers_to_axi_interconnect_0_WDATA;\n  wire m01_couplers_to_axi_interconnect_0_WLAST;\n  wire m01_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_WSTRB;\n  wire m01_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m02_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m02_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARQOS;\n  wire m02_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m02_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m02_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m02_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWQOS;\n  wire m02_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m02_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_BID;\n  wire m02_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_BRESP;\n  wire m02_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m02_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_RID;\n  wire m02_couplers_to_axi_interconnect_0_RLAST;\n  wire m02_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_RRESP;\n  wire m02_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m02_couplers_to_axi_interconnect_0_WDATA;\n  wire m02_couplers_to_axi_interconnect_0_WLAST;\n  wire m02_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_WSTRB;\n  wire m02_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m03_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m03_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARQOS;\n  wire m03_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m03_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m03_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m03_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWQOS;\n  wire m03_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m03_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_BID;\n  wire m03_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_BRESP;\n  wire m03_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m03_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_RID;\n  wire m03_couplers_to_axi_interconnect_0_RLAST;\n  wire m03_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_RRESP;\n  wire m03_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m03_couplers_to_axi_interconnect_0_WDATA;\n  wire m03_couplers_to_axi_interconnect_0_WLAST;\n  wire m03_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_WSTRB;\n  wire m03_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]s00_couplers_to_xbar_ARADDR;\n  wire [1:0]s00_couplers_to_xbar_ARBURST;\n  wire [3:0]s00_couplers_to_xbar_ARCACHE;\n  wire [5:0]s00_couplers_to_xbar_ARID;\n  wire [7:0]s00_couplers_to_xbar_ARLEN;\n  wire [0:0]s00_couplers_to_xbar_ARLOCK;\n  wire [2:0]s00_couplers_to_xbar_ARPROT;\n  wire [3:0]s00_couplers_to_xbar_ARQOS;\n  wire [0:0]s00_couplers_to_xbar_ARREADY;\n  wire [2:0]s00_couplers_to_xbar_ARSIZE;\n  wire s00_couplers_to_xbar_ARVALID;\n  wire [63:0]s00_couplers_to_xbar_AWADDR;\n  wire [1:0]s00_couplers_to_xbar_AWBURST;\n  wire [3:0]s00_couplers_to_xbar_AWCACHE;\n  wire [5:0]s00_couplers_to_xbar_AWID;\n  wire [7:0]s00_couplers_to_xbar_AWLEN;\n  wire [0:0]s00_couplers_to_xbar_AWLOCK;\n  wire [2:0]s00_couplers_to_xbar_AWPROT;\n  wire [3:0]s00_couplers_to_xbar_AWQOS;\n  wire [0:0]s00_couplers_to_xbar_AWREADY;\n  wire [2:0]s00_couplers_to_xbar_AWSIZE;\n  wire s00_couplers_to_xbar_AWVALID;\n  wire [6:0]s00_couplers_to_xbar_BID;\n  wire s00_couplers_to_xbar_BREADY;\n  wire [1:0]s00_couplers_to_xbar_BRESP;\n  wire [0:0]s00_couplers_to_xbar_BVALID;\n  wire [511:0]s00_couplers_to_xbar_RDATA;\n  wire [6:0]s00_couplers_to_xbar_RID;\n  wire [0:0]s00_couplers_to_xbar_RLAST;\n  wire s00_couplers_to_xbar_RREADY;\n  wire [1:0]s00_couplers_to_xbar_RRESP;\n  wire [0:0]s00_couplers_to_xbar_RVALID;\n  wire [511:0]s00_couplers_to_xbar_WDATA;\n  wire s00_couplers_to_xbar_WLAST;\n  wire [0:0]s00_couplers_to_xbar_WREADY;\n  wire [63:0]s00_couplers_to_xbar_WSTRB;\n  wire s00_couplers_to_xbar_WVALID;\n  wire [63:0]s01_couplers_to_xbar_ARADDR;\n  wire [1:0]s01_couplers_to_xbar_ARBURST;\n  wire [3:0]s01_couplers_to_xbar_ARCACHE;\n  wire [5:0]s01_couplers_to_xbar_ARID;\n  wire [7:0]s01_couplers_to_xbar_ARLEN;\n  wire [0:0]s01_couplers_to_xbar_ARLOCK;\n  wire [2:0]s01_couplers_to_xbar_ARPROT;\n  wire [3:0]s01_couplers_to_xbar_ARQOS;\n  wire [1:1]s01_couplers_to_xbar_ARREADY;\n  wire [2:0]s01_couplers_to_xbar_ARSIZE;\n  wire s01_couplers_to_xbar_ARVALID;\n  wire [63:0]s01_couplers_to_xbar_AWADDR;\n  wire [1:0]s01_couplers_to_xbar_AWBURST;\n  wire [3:0]s01_couplers_to_xbar_AWCACHE;\n  wire [5:0]s01_couplers_to_xbar_AWID;\n  wire [7:0]s01_couplers_to_xbar_AWLEN;\n  wire [0:0]s01_couplers_to_xbar_AWLOCK;\n  wire [2:0]s01_couplers_to_xbar_AWPROT;\n  wire [3:0]s01_couplers_to_xbar_AWQOS;\n  wire [1:1]s01_couplers_to_xbar_AWREADY;\n  wire [2:0]s01_couplers_to_xbar_AWSIZE;\n  wire s01_couplers_to_xbar_AWVALID;\n  wire [13:7]s01_couplers_to_xbar_BID;\n  wire s01_couplers_to_xbar_BREADY;\n  wire [3:2]s01_couplers_to_xbar_BRESP;\n  wire [1:1]s01_couplers_to_xbar_BVALID;\n  wire [1023:512]s01_couplers_to_xbar_RDATA;\n  wire [13:7]s01_couplers_to_xbar_RID;\n  wire [1:1]s01_couplers_to_xbar_RLAST;\n  wire s01_couplers_to_xbar_RREADY;\n  wire [3:2]s01_couplers_to_xbar_RRESP;\n  wire [1:1]s01_couplers_to_xbar_RVALID;\n  wire [511:0]s01_couplers_to_xbar_WDATA;\n  wire s01_couplers_to_xbar_WLAST;\n  wire [1:1]s01_couplers_to_xbar_WREADY;\n  wire [63:0]s01_couplers_to_xbar_WSTRB;\n  wire s01_couplers_to_xbar_WVALID;\n  wire [63:0]xbar_to_m00_couplers_ARADDR;\n  wire [1:0]xbar_to_m00_couplers_ARBURST;\n  wire [3:0]xbar_to_m00_couplers_ARCACHE;\n  wire [6:0]xbar_to_m00_couplers_ARID;\n  wire [7:0]xbar_to_m00_couplers_ARLEN;\n  wire [0:0]xbar_to_m00_couplers_ARLOCK;\n  wire [2:0]xbar_to_m00_couplers_ARPROT;\n  wire [3:0]xbar_to_m00_couplers_ARQOS;\n  wire xbar_to_m00_couplers_ARREADY;\n  wire [3:0]xbar_to_m00_couplers_ARREGION;\n  wire [2:0]xbar_to_m00_couplers_ARSIZE;\n  wire [0:0]xbar_to_m00_couplers_ARVALID;\n  wire [63:0]xbar_to_m00_couplers_AWADDR;\n  wire [1:0]xbar_to_m00_couplers_AWBURST;\n  wire [3:0]xbar_to_m00_couplers_AWCACHE;\n  wire [6:0]xbar_to_m00_couplers_AWID;\n  wire [7:0]xbar_to_m00_couplers_AWLEN;\n  wire [0:0]xbar_to_m00_couplers_AWLOCK;\n  wire [2:0]xbar_to_m00_couplers_AWPROT;\n  wire [3:0]xbar_to_m00_couplers_AWQOS;\n  wire xbar_to_m00_couplers_AWREADY;\n  wire [3:0]xbar_to_m00_couplers_AWREGION;\n  wire [2:0]xbar_to_m00_couplers_AWSIZE;\n  wire [0:0]xbar_to_m00_couplers_AWVALID;\n  wire [6:0]xbar_to_m00_couplers_BID;\n  wire [0:0]xbar_to_m00_couplers_BREADY;\n  wire [1:0]xbar_to_m00_couplers_BRESP;\n  wire xbar_to_m00_couplers_BVALID;\n  wire [511:0]xbar_to_m00_couplers_RDATA;\n  wire [6:0]xbar_to_m00_couplers_RID;\n  wire xbar_to_m00_couplers_RLAST;\n  wire [0:0]xbar_to_m00_couplers_RREADY;\n  wire [1:0]xbar_to_m00_couplers_RRESP;\n  wire xbar_to_m00_couplers_RVALID;\n  wire [511:0]xbar_to_m00_couplers_WDATA;\n  wire [0:0]xbar_to_m00_couplers_WLAST;\n  wire xbar_to_m00_couplers_WREADY;\n  wire [63:0]xbar_to_m00_couplers_WSTRB;\n  wire [0:0]xbar_to_m00_couplers_WVALID;\n  wire [127:64]xbar_to_m01_couplers_ARADDR;\n  wire [3:2]xbar_to_m01_couplers_ARBURST;\n  wire [7:4]xbar_to_m01_couplers_ARCACHE;\n  wire [13:7]xbar_to_m01_couplers_ARID;\n  wire [15:8]xbar_to_m01_couplers_ARLEN;\n  wire [1:1]xbar_to_m01_couplers_ARLOCK;\n  wire [5:3]xbar_to_m01_couplers_ARPROT;\n  wire [7:4]xbar_to_m01_couplers_ARQOS;\n  wire xbar_to_m01_couplers_ARREADY;\n  wire [7:4]xbar_to_m01_couplers_ARREGION;\n  wire [5:3]xbar_to_m01_couplers_ARSIZE;\n  wire [1:1]xbar_to_m01_couplers_ARVALID;\n  wire [127:64]xbar_to_m01_couplers_AWADDR;\n  wire [3:2]xbar_to_m01_couplers_AWBURST;\n  wire [7:4]xbar_to_m01_couplers_AWCACHE;\n  wire [13:7]xbar_to_m01_couplers_AWID;\n  wire [15:8]xbar_to_m01_couplers_AWLEN;\n  wire [1:1]xbar_to_m01_couplers_AWLOCK;\n  wire [5:3]xbar_to_m01_couplers_AWPROT;\n  wire [7:4]xbar_to_m01_couplers_AWQOS;\n  wire xbar_to_m01_couplers_AWREADY;\n  wire [7:4]xbar_to_m01_couplers_AWREGION;\n  wire [5:3]xbar_to_m01_couplers_AWSIZE;\n  wire [1:1]xbar_to_m01_couplers_AWVALID;\n  wire [6:0]xbar_to_m01_couplers_BID;\n  wire [1:1]xbar_to_m01_couplers_BREADY;\n  wire [1:0]xbar_to_m01_couplers_BRESP;\n  wire xbar_to_m01_couplers_BVALID;\n  wire [511:0]xbar_to_m01_couplers_RDATA;\n  wire [6:0]xbar_to_m01_couplers_RID;\n  wire xbar_to_m01_couplers_RLAST;\n  wire [1:1]xbar_to_m01_couplers_RREADY;\n  wire [1:0]xbar_to_m01_couplers_RRESP;\n  wire xbar_to_m01_couplers_RVALID;\n  wire [1023:512]xbar_to_m01_couplers_WDATA;\n  wire [1:1]xbar_to_m01_couplers_WLAST;\n  wire xbar_to_m01_couplers_WREADY;\n  wire [127:64]xbar_to_m01_couplers_WSTRB;\n  wire [1:1]xbar_to_m01_couplers_WVALID;\n  wire [191:128]xbar_to_m02_couplers_ARADDR;\n  wire [5:4]xbar_to_m02_couplers_ARBURST;\n  wire [11:8]xbar_to_m02_couplers_ARCACHE;\n  wire [20:14]xbar_to_m02_couplers_ARID;\n  wire [23:16]xbar_to_m02_couplers_ARLEN;\n  wire [2:2]xbar_to_m02_couplers_ARLOCK;\n  wire [8:6]xbar_to_m02_couplers_ARPROT;\n  wire [11:8]xbar_to_m02_couplers_ARQOS;\n  wire xbar_to_m02_couplers_ARREADY;\n  wire [11:8]xbar_to_m02_couplers_ARREGION;\n  wire [8:6]xbar_to_m02_couplers_ARSIZE;\n  wire [2:2]xbar_to_m02_couplers_ARVALID;\n  wire [191:128]xbar_to_m02_couplers_AWADDR;\n  wire [5:4]xbar_to_m02_couplers_AWBURST;\n  wire [11:8]xbar_to_m02_couplers_AWCACHE;\n  wire [20:14]xbar_to_m02_couplers_AWID;\n  wire [23:16]xbar_to_m02_couplers_AWLEN;\n  wire [2:2]xbar_to_m02_couplers_AWLOCK;\n  wire [8:6]xbar_to_m02_couplers_AWPROT;\n  wire [11:8]xbar_to_m02_couplers_AWQOS;\n  wire xbar_to_m02_couplers_AWREADY;\n  wire [11:8]xbar_to_m02_couplers_AWREGION;\n  wire [8:6]xbar_to_m02_couplers_AWSIZE;\n  wire [2:2]xbar_to_m02_couplers_AWVALID;\n  wire [6:0]xbar_to_m02_couplers_BID;\n  wire [2:2]xbar_to_m02_couplers_BREADY;\n  wire [1:0]xbar_to_m02_couplers_BRESP;\n  wire xbar_to_m02_couplers_BVALID;\n  wire [511:0]xbar_to_m02_couplers_RDATA;\n  wire [6:0]xbar_to_m02_couplers_RID;\n  wire xbar_to_m02_couplers_RLAST;\n  wire [2:2]xbar_to_m02_couplers_RREADY;\n  wire [1:0]xbar_to_m02_couplers_RRESP;\n  wire xbar_to_m02_couplers_RVALID;\n  wire [1535:1024]xbar_to_m02_couplers_WDATA;\n  wire [2:2]xbar_to_m02_couplers_WLAST;\n  wire xbar_to_m02_couplers_WREADY;\n  wire [191:128]xbar_to_m02_couplers_WSTRB;\n  wire [2:2]xbar_to_m02_couplers_WVALID;\n  wire [255:192]xbar_to_m03_couplers_ARADDR;\n  wire [7:6]xbar_to_m03_couplers_ARBURST;\n  wire [15:12]xbar_to_m03_couplers_ARCACHE;\n  wire [27:21]xbar_to_m03_couplers_ARID;\n  wire [31:24]xbar_to_m03_couplers_ARLEN;\n  wire [3:3]xbar_to_m03_couplers_ARLOCK;\n  wire [11:9]xbar_to_m03_couplers_ARPROT;\n  wire [15:12]xbar_to_m03_couplers_ARQOS;\n  wire xbar_to_m03_couplers_ARREADY;\n  wire [15:12]xbar_to_m03_couplers_ARREGION;\n  wire [11:9]xbar_to_m03_couplers_ARSIZE;\n  wire [3:3]xbar_to_m03_couplers_ARVALID;\n  wire [255:192]xbar_to_m03_couplers_AWADDR;\n  wire [7:6]xbar_to_m03_couplers_AWBURST;\n  wire [15:12]xbar_to_m03_couplers_AWCACHE;\n  wire [27:21]xbar_to_m03_couplers_AWID;\n  wire [31:24]xbar_to_m03_couplers_AWLEN;\n  wire [3:3]xbar_to_m03_couplers_AWLOCK;\n  wire [11:9]xbar_to_m03_couplers_AWPROT;\n  wire [15:12]xbar_to_m03_couplers_AWQOS;\n  wire xbar_to_m03_couplers_AWREADY;\n  wire [15:12]xbar_to_m03_couplers_AWREGION;\n  wire [11:9]xbar_to_m03_couplers_AWSIZE;\n  wire [3:3]xbar_to_m03_couplers_AWVALID;\n  wire [6:0]xbar_to_m03_couplers_BID;\n  wire [3:3]xbar_to_m03_couplers_BREADY;\n  wire [1:0]xbar_to_m03_couplers_BRESP;\n  wire xbar_to_m03_couplers_BVALID;\n  wire [511:0]xbar_to_m03_couplers_RDATA;\n  wire [6:0]xbar_to_m03_couplers_RID;\n  wire xbar_to_m03_couplers_RLAST;\n  wire [3:3]xbar_to_m03_couplers_RREADY;\n  wire [1:0]xbar_to_m03_couplers_RRESP;\n  wire xbar_to_m03_couplers_RVALID;\n  wire [2047:1536]xbar_to_m03_couplers_WDATA;\n  wire [3:3]xbar_to_m03_couplers_WLAST;\n  wire xbar_to_m03_couplers_WREADY;\n  wire [255:192]xbar_to_m03_couplers_WSTRB;\n  wire [3:3]xbar_to_m03_couplers_WVALID;\n\n  assign M00_AXI_araddr[63:0] = m00_couplers_to_axi_interconnect_0_ARADDR;\n  assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_interconnect_0_ARBURST;\n  assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M00_AXI_arid[6:0] = m00_couplers_to_axi_interconnect_0_ARID;\n  assign M00_AXI_arlen[7:0] = m00_couplers_to_axi_interconnect_0_ARLEN;\n  assign M00_AXI_arlock[0] = m00_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_interconnect_0_ARPROT;\n  assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_interconnect_0_ARQOS;\n  assign M00_AXI_arregion[3:0] = m00_couplers_to_axi_interconnect_0_ARREGION;\n  assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M00_AXI_arvalid = m00_couplers_to_axi_interconnect_0_ARVALID;\n  assign M00_AXI_awaddr[63:0] = m00_couplers_to_axi_interconnect_0_AWADDR;\n  assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_interconnect_0_AWBURST;\n  assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M00_AXI_awid[6:0] = m00_couplers_to_axi_interconnect_0_AWID;\n  assign M00_AXI_awlen[7:0] = m00_couplers_to_axi_interconnect_0_AWLEN;\n  assign M00_AXI_awlock[0] = m00_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_interconnect_0_AWPROT;\n  assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_interconnect_0_AWQOS;\n  assign M00_AXI_awregion[3:0] = m00_couplers_to_axi_interconnect_0_AWREGION;\n  assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M00_AXI_awvalid = m00_couplers_to_axi_interconnect_0_AWVALID;\n  assign M00_AXI_bready = m00_couplers_to_axi_interconnect_0_BREADY;\n  assign M00_AXI_rready = m00_couplers_to_axi_interconnect_0_RREADY;\n  assign M00_AXI_wdata[511:0] = m00_couplers_to_axi_interconnect_0_WDATA;\n  assign M00_AXI_wlast = m00_couplers_to_axi_interconnect_0_WLAST;\n  assign M00_AXI_wstrb[63:0] = m00_couplers_to_axi_interconnect_0_WSTRB;\n  assign M00_AXI_wvalid = m00_couplers_to_axi_interconnect_0_WVALID;\n  assign M01_AXI_araddr[63:0] = m01_couplers_to_axi_interconnect_0_ARADDR;\n  assign M01_AXI_arburst[1:0] = m01_couplers_to_axi_interconnect_0_ARBURST;\n  assign M01_AXI_arcache[3:0] = m01_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M01_AXI_arid[6:0] = m01_couplers_to_axi_interconnect_0_ARID;\n  assign M01_AXI_arlen[7:0] = m01_couplers_to_axi_interconnect_0_ARLEN;\n  assign M01_AXI_arlock[0] = m01_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M01_AXI_arprot[2:0] = m01_couplers_to_axi_interconnect_0_ARPROT;\n  assign M01_AXI_arqos[3:0] = m01_couplers_to_axi_interconnect_0_ARQOS;\n  assign M01_AXI_arregion[3:0] = m01_couplers_to_axi_interconnect_0_ARREGION;\n  assign M01_AXI_arsize[2:0] = m01_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M01_AXI_arvalid = m01_couplers_to_axi_interconnect_0_ARVALID;\n  assign M01_AXI_awaddr[63:0] = m01_couplers_to_axi_interconnect_0_AWADDR;\n  assign M01_AXI_awburst[1:0] = m01_couplers_to_axi_interconnect_0_AWBURST;\n  assign M01_AXI_awcache[3:0] = m01_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M01_AXI_awid[6:0] = m01_couplers_to_axi_interconnect_0_AWID;\n  assign M01_AXI_awlen[7:0] = m01_couplers_to_axi_interconnect_0_AWLEN;\n  assign M01_AXI_awlock[0] = m01_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M01_AXI_awprot[2:0] = m01_couplers_to_axi_interconnect_0_AWPROT;\n  assign M01_AXI_awqos[3:0] = m01_couplers_to_axi_interconnect_0_AWQOS;\n  assign M01_AXI_awregion[3:0] = m01_couplers_to_axi_interconnect_0_AWREGION;\n  assign M01_AXI_awsize[2:0] = m01_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M01_AXI_awvalid = m01_couplers_to_axi_interconnect_0_AWVALID;\n  assign M01_AXI_bready = m01_couplers_to_axi_interconnect_0_BREADY;\n  assign M01_AXI_rready = m01_couplers_to_axi_interconnect_0_RREADY;\n  assign M01_AXI_wdata[511:0] = m01_couplers_to_axi_interconnect_0_WDATA;\n  assign M01_AXI_wlast = m01_couplers_to_axi_interconnect_0_WLAST;\n  assign M01_AXI_wstrb[63:0] = m01_couplers_to_axi_interconnect_0_WSTRB;\n  assign M01_AXI_wvalid = m01_couplers_to_axi_interconnect_0_WVALID;\n  assign M02_AXI_araddr[63:0] = m02_couplers_to_axi_interconnect_0_ARADDR;\n  assign M02_AXI_arburst[1:0] = m02_couplers_to_axi_interconnect_0_ARBURST;\n  assign M02_AXI_arcache[3:0] = m02_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M02_AXI_arid[6:0] = m02_couplers_to_axi_interconnect_0_ARID;\n  assign M02_AXI_arlen[7:0] = m02_couplers_to_axi_interconnect_0_ARLEN;\n  assign M02_AXI_arlock[0] = m02_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M02_AXI_arprot[2:0] = m02_couplers_to_axi_interconnect_0_ARPROT;\n  assign M02_AXI_arqos[3:0] = m02_couplers_to_axi_interconnect_0_ARQOS;\n  assign M02_AXI_arregion[3:0] = m02_couplers_to_axi_interconnect_0_ARREGION;\n  assign M02_AXI_arsize[2:0] = m02_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M02_AXI_arvalid = m02_couplers_to_axi_interconnect_0_ARVALID;\n  assign M02_AXI_awaddr[63:0] = m02_couplers_to_axi_interconnect_0_AWADDR;\n  assign M02_AXI_awburst[1:0] = m02_couplers_to_axi_interconnect_0_AWBURST;\n  assign M02_AXI_awcache[3:0] = m02_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M02_AXI_awid[6:0] = m02_couplers_to_axi_interconnect_0_AWID;\n  assign M02_AXI_awlen[7:0] = m02_couplers_to_axi_interconnect_0_AWLEN;\n  assign M02_AXI_awlock[0] = m02_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M02_AXI_awprot[2:0] = m02_couplers_to_axi_interconnect_0_AWPROT;\n  assign M02_AXI_awqos[3:0] = m02_couplers_to_axi_interconnect_0_AWQOS;\n  assign M02_AXI_awregion[3:0] = m02_couplers_to_axi_interconnect_0_AWREGION;\n  assign M02_AXI_awsize[2:0] = m02_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M02_AXI_awvalid = m02_couplers_to_axi_interconnect_0_AWVALID;\n  assign M02_AXI_bready = m02_couplers_to_axi_interconnect_0_BREADY;\n  assign M02_AXI_rready = m02_couplers_to_axi_interconnect_0_RREADY;\n  assign M02_AXI_wdata[511:0] = m02_couplers_to_axi_interconnect_0_WDATA;\n  assign M02_AXI_wlast = m02_couplers_to_axi_interconnect_0_WLAST;\n  assign M02_AXI_wstrb[63:0] = m02_couplers_to_axi_interconnect_0_WSTRB;\n  assign M02_AXI_wvalid = m02_couplers_to_axi_interconnect_0_WVALID;\n  assign M03_AXI_araddr[63:0] = m03_couplers_to_axi_interconnect_0_ARADDR;\n  assign M03_AXI_arburst[1:0] = m03_couplers_to_axi_interconnect_0_ARBURST;\n  assign M03_AXI_arcache[3:0] = m03_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M03_AXI_arid[6:0] = m03_couplers_to_axi_interconnect_0_ARID;\n  assign M03_AXI_arlen[7:0] = m03_couplers_to_axi_interconnect_0_ARLEN;\n  assign M03_AXI_arlock[0] = m03_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M03_AXI_arprot[2:0] = m03_couplers_to_axi_interconnect_0_ARPROT;\n  assign M03_AXI_arqos[3:0] = m03_couplers_to_axi_interconnect_0_ARQOS;\n  assign M03_AXI_arregion[3:0] = m03_couplers_to_axi_interconnect_0_ARREGION;\n  assign M03_AXI_arsize[2:0] = m03_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M03_AXI_arvalid = m03_couplers_to_axi_interconnect_0_ARVALID;\n  assign M03_AXI_awaddr[63:0] = m03_couplers_to_axi_interconnect_0_AWADDR;\n  assign M03_AXI_awburst[1:0] = m03_couplers_to_axi_interconnect_0_AWBURST;\n  assign M03_AXI_awcache[3:0] = m03_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M03_AXI_awid[6:0] = m03_couplers_to_axi_interconnect_0_AWID;\n  assign M03_AXI_awlen[7:0] = m03_couplers_to_axi_interconnect_0_AWLEN;\n  assign M03_AXI_awlock[0] = m03_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M03_AXI_awprot[2:0] = m03_couplers_to_axi_interconnect_0_AWPROT;\n  assign M03_AXI_awqos[3:0] = m03_couplers_to_axi_interconnect_0_AWQOS;\n  assign M03_AXI_awregion[3:0] = m03_couplers_to_axi_interconnect_0_AWREGION;\n  assign M03_AXI_awsize[2:0] = m03_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M03_AXI_awvalid = m03_couplers_to_axi_interconnect_0_AWVALID;\n  assign M03_AXI_bready = m03_couplers_to_axi_interconnect_0_BREADY;\n  assign M03_AXI_rready = m03_couplers_to_axi_interconnect_0_RREADY;\n  assign M03_AXI_wdata[511:0] = m03_couplers_to_axi_interconnect_0_WDATA;\n  assign M03_AXI_wlast = m03_couplers_to_axi_interconnect_0_WLAST;\n  assign M03_AXI_wstrb[63:0] = m03_couplers_to_axi_interconnect_0_WSTRB;\n  assign M03_AXI_wvalid = m03_couplers_to_axi_interconnect_0_WVALID;\n  assign S00_AXI_arready = axi_interconnect_0_to_s00_couplers_ARREADY;\n  assign S00_AXI_awready = axi_interconnect_0_to_s00_couplers_AWREADY;\n  assign S00_AXI_bid[5:0] = axi_interconnect_0_to_s00_couplers_BID;\n  assign S00_AXI_bresp[1:0] = axi_interconnect_0_to_s00_couplers_BRESP;\n  assign S00_AXI_bvalid = axi_interconnect_0_to_s00_couplers_BVALID;\n  assign S00_AXI_rdata[511:0] = axi_interconnect_0_to_s00_couplers_RDATA;\n  assign S00_AXI_rid[5:0] = axi_interconnect_0_to_s00_couplers_RID;\n  assign S00_AXI_rlast = axi_interconnect_0_to_s00_couplers_RLAST;\n  assign S00_AXI_rresp[1:0] = axi_interconnect_0_to_s00_couplers_RRESP;\n  assign S00_AXI_rvalid = axi_interconnect_0_to_s00_couplers_RVALID;\n  assign S00_AXI_wready = axi_interconnect_0_to_s00_couplers_WREADY;\n  assign S01_AXI_arready = axi_interconnect_0_to_s01_couplers_ARREADY;\n  assign S01_AXI_awready = axi_interconnect_0_to_s01_couplers_AWREADY;\n  assign S01_AXI_bid[5:0] = axi_interconnect_0_to_s01_couplers_BID;\n  assign S01_AXI_bresp[1:0] = axi_interconnect_0_to_s01_couplers_BRESP;\n  assign S01_AXI_bvalid = axi_interconnect_0_to_s01_couplers_BVALID;\n  assign S01_AXI_rdata[511:0] = axi_interconnect_0_to_s01_couplers_RDATA;\n  assign S01_AXI_rid[5:0] = axi_interconnect_0_to_s01_couplers_RID;\n  assign S01_AXI_rlast = axi_interconnect_0_to_s01_couplers_RLAST;\n  assign S01_AXI_rresp[1:0] = axi_interconnect_0_to_s01_couplers_RRESP;\n  assign S01_AXI_rvalid = axi_interconnect_0_to_s01_couplers_RVALID;\n  assign S01_AXI_wready = axi_interconnect_0_to_s01_couplers_WREADY;\n  assign axi_interconnect_0_ACLK_net = ACLK;\n  assign axi_interconnect_0_ARESETN_net = ARESETN;\n  assign axi_interconnect_0_to_s00_couplers_ARADDR = S00_AXI_araddr[63:0];\n  assign axi_interconnect_0_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];\n  assign axi_interconnect_0_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARID = S00_AXI_arid[5:0];\n  assign axi_interconnect_0_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0];\n  assign axi_interconnect_0_to_s00_couplers_ARLOCK = S00_AXI_arlock[0];\n  assign axi_interconnect_0_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];\n  assign axi_interconnect_0_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARREGION = S00_AXI_arregion[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];\n  assign axi_interconnect_0_to_s00_couplers_ARVALID = S00_AXI_arvalid;\n  assign axi_interconnect_0_to_s00_couplers_AWADDR = S00_AXI_awaddr[63:0];\n  assign axi_interconnect_0_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];\n  assign axi_interconnect_0_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWID = S00_AXI_awid[5:0];\n  assign axi_interconnect_0_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0];\n  assign axi_interconnect_0_to_s00_couplers_AWLOCK = S00_AXI_awlock[0];\n  assign axi_interconnect_0_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];\n  assign axi_interconnect_0_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWREGION = S00_AXI_awregion[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];\n  assign axi_interconnect_0_to_s00_couplers_AWVALID = S00_AXI_awvalid;\n  assign axi_interconnect_0_to_s00_couplers_BREADY = S00_AXI_bready;\n  assign axi_interconnect_0_to_s00_couplers_RREADY = S00_AXI_rready;\n  assign axi_interconnect_0_to_s00_couplers_WDATA = S00_AXI_wdata[511:0];\n  assign axi_interconnect_0_to_s00_couplers_WLAST = S00_AXI_wlast;\n  assign axi_interconnect_0_to_s00_couplers_WSTRB = S00_AXI_wstrb[63:0];\n  assign axi_interconnect_0_to_s00_couplers_WVALID = S00_AXI_wvalid;\n  assign axi_interconnect_0_to_s01_couplers_ARADDR = S01_AXI_araddr[63:0];\n  assign axi_interconnect_0_to_s01_couplers_ARBURST = S01_AXI_arburst[1:0];\n  assign axi_interconnect_0_to_s01_couplers_ARCACHE = S01_AXI_arcache[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARID = S01_AXI_arid[5:0];\n  assign axi_interconnect_0_to_s01_couplers_ARLEN = S01_AXI_arlen[7:0];\n  assign axi_interconnect_0_to_s01_couplers_ARLOCK = S01_AXI_arlock[0];\n  assign axi_interconnect_0_to_s01_couplers_ARPROT = S01_AXI_arprot[2:0];\n  assign axi_interconnect_0_to_s01_couplers_ARQOS = S01_AXI_arqos[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARREGION = S01_AXI_arregion[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARSIZE = S01_AXI_arsize[2:0];\n  assign axi_interconnect_0_to_s01_couplers_ARVALID = S01_AXI_arvalid;\n  assign axi_interconnect_0_to_s01_couplers_AWADDR = S01_AXI_awaddr[63:0];\n  assign axi_interconnect_0_to_s01_couplers_AWBURST = S01_AXI_awburst[1:0];\n  assign axi_interconnect_0_to_s01_couplers_AWCACHE = S01_AXI_awcache[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWID = S01_AXI_awid[5:0];\n  assign axi_interconnect_0_to_s01_couplers_AWLEN = S01_AXI_awlen[7:0];\n  assign axi_interconnect_0_to_s01_couplers_AWLOCK = S01_AXI_awlock[0];\n  assign axi_interconnect_0_to_s01_couplers_AWPROT = S01_AXI_awprot[2:0];\n  assign axi_interconnect_0_to_s01_couplers_AWQOS = S01_AXI_awqos[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWREGION = S01_AXI_awregion[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWSIZE = S01_AXI_awsize[2:0];\n  assign axi_interconnect_0_to_s01_couplers_AWVALID = S01_AXI_awvalid;\n  assign axi_interconnect_0_to_s01_couplers_BREADY = S01_AXI_bready;\n  assign axi_interconnect_0_to_s01_couplers_RREADY = S01_AXI_rready;\n  assign axi_interconnect_0_to_s01_couplers_WDATA = S01_AXI_wdata[511:0];\n  assign axi_interconnect_0_to_s01_couplers_WLAST = S01_AXI_wlast;\n  assign axi_interconnect_0_to_s01_couplers_WSTRB = S01_AXI_wstrb[63:0];\n  assign axi_interconnect_0_to_s01_couplers_WVALID = S01_AXI_wvalid;\n  assign m00_couplers_to_axi_interconnect_0_ARREADY = M00_AXI_arready;\n  assign m00_couplers_to_axi_interconnect_0_AWREADY = M00_AXI_awready;\n  assign m00_couplers_to_axi_interconnect_0_BID = M00_AXI_bid[6:0];\n  assign m00_couplers_to_axi_interconnect_0_BRESP = M00_AXI_bresp[1:0];\n  assign m00_couplers_to_axi_interconnect_0_BVALID = M00_AXI_bvalid;\n  assign m00_couplers_to_axi_interconnect_0_RDATA = M00_AXI_rdata[511:0];\n  assign m00_couplers_to_axi_interconnect_0_RID = M00_AXI_rid[6:0];\n  assign m00_couplers_to_axi_interconnect_0_RLAST = M00_AXI_rlast;\n  assign m00_couplers_to_axi_interconnect_0_RRESP = M00_AXI_rresp[1:0];\n  assign m00_couplers_to_axi_interconnect_0_RVALID = M00_AXI_rvalid;\n  assign m00_couplers_to_axi_interconnect_0_WREADY = M00_AXI_wready;\n  assign m01_couplers_to_axi_interconnect_0_ARREADY = M01_AXI_arready;\n  assign m01_couplers_to_axi_interconnect_0_AWREADY = M01_AXI_awready;\n  assign m01_couplers_to_axi_interconnect_0_BID = M01_AXI_bid[6:0];\n  assign m01_couplers_to_axi_interconnect_0_BRESP = M01_AXI_bresp[1:0];\n  assign m01_couplers_to_axi_interconnect_0_BVALID = M01_AXI_bvalid;\n  assign m01_couplers_to_axi_interconnect_0_RDATA = M01_AXI_rdata[511:0];\n  assign m01_couplers_to_axi_interconnect_0_RID = M01_AXI_rid[6:0];\n  assign m01_couplers_to_axi_interconnect_0_RLAST = M01_AXI_rlast;\n  assign m01_couplers_to_axi_interconnect_0_RRESP = M01_AXI_rresp[1:0];\n  assign m01_couplers_to_axi_interconnect_0_RVALID = M01_AXI_rvalid;\n  assign m01_couplers_to_axi_interconnect_0_WREADY = M01_AXI_wready;\n  assign m02_couplers_to_axi_interconnect_0_ARREADY = M02_AXI_arready;\n  assign m02_couplers_to_axi_interconnect_0_AWREADY = M02_AXI_awready;\n  assign m02_couplers_to_axi_interconnect_0_BID = M02_AXI_bid[6:0];\n  assign m02_couplers_to_axi_interconnect_0_BRESP = M02_AXI_bresp[1:0];\n  assign m02_couplers_to_axi_interconnect_0_BVALID = M02_AXI_bvalid;\n  assign m02_couplers_to_axi_interconnect_0_RDATA = M02_AXI_rdata[511:0];\n  assign m02_couplers_to_axi_interconnect_0_RID = M02_AXI_rid[6:0];\n  assign m02_couplers_to_axi_interconnect_0_RLAST = M02_AXI_rlast;\n  assign m02_couplers_to_axi_interconnect_0_RRESP = M02_AXI_rresp[1:0];\n  assign m02_couplers_to_axi_interconnect_0_RVALID = M02_AXI_rvalid;\n  assign m02_couplers_to_axi_interconnect_0_WREADY = M02_AXI_wready;\n  assign m03_couplers_to_axi_interconnect_0_ARREADY = M03_AXI_arready;\n  assign m03_couplers_to_axi_interconnect_0_AWREADY = M03_AXI_awready;\n  assign m03_couplers_to_axi_interconnect_0_BID = M03_AXI_bid[6:0];\n  assign m03_couplers_to_axi_interconnect_0_BRESP = M03_AXI_bresp[1:0];\n  assign m03_couplers_to_axi_interconnect_0_BVALID = M03_AXI_bvalid;\n  assign m03_couplers_to_axi_interconnect_0_RDATA = M03_AXI_rdata[511:0];\n  assign m03_couplers_to_axi_interconnect_0_RID = M03_AXI_rid[6:0];\n  assign m03_couplers_to_axi_interconnect_0_RLAST = M03_AXI_rlast;\n  assign m03_couplers_to_axi_interconnect_0_RRESP = M03_AXI_rresp[1:0];\n  assign m03_couplers_to_axi_interconnect_0_RVALID = M03_AXI_rvalid;\n  assign m03_couplers_to_axi_interconnect_0_WREADY = M03_AXI_wready;\n  m00_couplers_imp_1QBJ6U2 m00_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m00_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m00_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m00_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m00_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m00_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m00_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m00_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m00_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m00_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m00_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m00_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m00_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m00_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m00_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m00_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m00_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m00_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m00_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m00_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m00_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m00_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m00_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m00_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m00_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m00_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m00_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m00_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m00_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m00_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m00_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m00_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m00_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m00_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m00_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m00_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m00_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m00_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m00_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m00_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m00_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m00_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m00_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m00_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m00_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m00_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m00_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m00_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m00_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m00_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m00_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m00_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m00_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m00_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m00_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m00_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m00_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m00_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m00_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m00_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m00_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m00_couplers_BID),\n        .S_AXI_bready(xbar_to_m00_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m00_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m00_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m00_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m00_couplers_RID),\n        .S_AXI_rlast(xbar_to_m00_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m00_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m00_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m00_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m00_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m00_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m00_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m00_couplers_WVALID));\n  m01_couplers_imp_10IMR9A m01_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m01_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m01_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m01_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m01_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m01_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m01_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m01_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m01_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m01_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m01_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m01_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m01_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m01_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m01_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m01_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m01_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m01_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m01_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m01_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m01_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m01_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m01_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m01_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m01_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m01_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m01_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m01_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m01_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m01_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m01_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m01_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m01_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m01_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m01_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m01_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m01_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m01_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m01_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m01_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m01_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m01_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m01_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m01_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m01_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m01_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m01_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m01_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m01_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m01_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m01_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m01_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m01_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m01_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m01_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m01_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m01_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m01_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m01_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m01_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m01_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m01_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m01_couplers_BID),\n        .S_AXI_bready(xbar_to_m01_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m01_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m01_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m01_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m01_couplers_RID),\n        .S_AXI_rlast(xbar_to_m01_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m01_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m01_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m01_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m01_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m01_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m01_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m01_couplers_WVALID));\n  m02_couplers_imp_APDUS2 m02_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m02_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m02_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m02_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m02_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m02_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m02_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m02_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m02_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m02_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m02_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m02_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m02_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m02_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m02_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m02_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m02_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m02_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m02_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m02_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m02_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m02_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m02_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m02_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m02_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m02_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m02_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m02_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m02_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m02_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m02_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m02_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m02_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m02_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m02_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m02_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m02_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m02_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m02_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m02_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m02_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m02_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m02_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m02_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m02_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m02_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m02_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m02_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m02_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m02_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m02_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m02_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m02_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m02_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m02_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m02_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m02_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m02_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m02_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m02_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m02_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m02_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m02_couplers_BID),\n        .S_AXI_bready(xbar_to_m02_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m02_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m02_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m02_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m02_couplers_RID),\n        .S_AXI_rlast(xbar_to_m02_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m02_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m02_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m02_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m02_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m02_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m02_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m02_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m02_couplers_WVALID));\n  m03_couplers_imp_JAYOMU m03_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m03_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m03_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m03_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m03_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m03_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m03_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m03_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m03_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m03_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m03_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m03_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m03_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m03_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m03_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m03_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m03_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m03_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m03_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m03_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m03_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m03_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m03_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m03_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m03_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m03_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m03_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m03_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m03_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m03_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m03_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m03_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m03_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m03_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m03_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m03_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m03_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m03_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m03_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m03_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m03_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m03_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m03_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m03_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m03_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m03_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m03_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m03_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m03_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m03_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m03_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m03_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m03_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m03_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m03_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m03_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m03_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m03_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m03_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m03_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m03_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m03_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m03_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m03_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m03_couplers_BID),\n        .S_AXI_bready(xbar_to_m03_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m03_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m03_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m03_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m03_couplers_RID),\n        .S_AXI_rlast(xbar_to_m03_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m03_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m03_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m03_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m03_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m03_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m03_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m03_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m03_couplers_WVALID));\n  s00_couplers_imp_QICM5G s00_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(s00_couplers_to_xbar_ARADDR),\n        .M_AXI_arburst(s00_couplers_to_xbar_ARBURST),\n        .M_AXI_arcache(s00_couplers_to_xbar_ARCACHE),\n        .M_AXI_arid(s00_couplers_to_xbar_ARID),\n        .M_AXI_arlen(s00_couplers_to_xbar_ARLEN),\n        .M_AXI_arlock(s00_couplers_to_xbar_ARLOCK),\n        .M_AXI_arprot(s00_couplers_to_xbar_ARPROT),\n        .M_AXI_arqos(s00_couplers_to_xbar_ARQOS),\n        .M_AXI_arready(s00_couplers_to_xbar_ARREADY),\n        .M_AXI_arsize(s00_couplers_to_xbar_ARSIZE),\n        .M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),\n        .M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),\n        .M_AXI_awburst(s00_couplers_to_xbar_AWBURST),\n        .M_AXI_awcache(s00_couplers_to_xbar_AWCACHE),\n        .M_AXI_awid(s00_couplers_to_xbar_AWID),\n        .M_AXI_awlen(s00_couplers_to_xbar_AWLEN),\n        .M_AXI_awlock(s00_couplers_to_xbar_AWLOCK),\n        .M_AXI_awprot(s00_couplers_to_xbar_AWPROT),\n        .M_AXI_awqos(s00_couplers_to_xbar_AWQOS),\n        .M_AXI_awready(s00_couplers_to_xbar_AWREADY),\n        .M_AXI_awsize(s00_couplers_to_xbar_AWSIZE),\n        .M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),\n        .M_AXI_bid(s00_couplers_to_xbar_BID),\n        .M_AXI_bready(s00_couplers_to_xbar_BREADY),\n        .M_AXI_bresp(s00_couplers_to_xbar_BRESP),\n        .M_AXI_bvalid(s00_couplers_to_xbar_BVALID),\n        .M_AXI_rdata(s00_couplers_to_xbar_RDATA),\n        .M_AXI_rid(s00_couplers_to_xbar_RID),\n        .M_AXI_rlast(s00_couplers_to_xbar_RLAST),\n        .M_AXI_rready(s00_couplers_to_xbar_RREADY),\n        .M_AXI_rresp(s00_couplers_to_xbar_RRESP),\n        .M_AXI_rvalid(s00_couplers_to_xbar_RVALID),\n        .M_AXI_wdata(s00_couplers_to_xbar_WDATA),\n        .M_AXI_wlast(s00_couplers_to_xbar_WLAST),\n        .M_AXI_wready(s00_couplers_to_xbar_WREADY),\n        .M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),\n        .M_AXI_wvalid(s00_couplers_to_xbar_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(axi_interconnect_0_to_s00_couplers_ARADDR),\n        .S_AXI_arburst(axi_interconnect_0_to_s00_couplers_ARBURST),\n        .S_AXI_arcache(axi_interconnect_0_to_s00_couplers_ARCACHE),\n        .S_AXI_arid(axi_interconnect_0_to_s00_couplers_ARID),\n        .S_AXI_arlen(axi_interconnect_0_to_s00_couplers_ARLEN),\n        .S_AXI_arlock(axi_interconnect_0_to_s00_couplers_ARLOCK),\n        .S_AXI_arprot(axi_interconnect_0_to_s00_couplers_ARPROT),\n        .S_AXI_arqos(axi_interconnect_0_to_s00_couplers_ARQOS),\n        .S_AXI_arready(axi_interconnect_0_to_s00_couplers_ARREADY),\n        .S_AXI_arregion(axi_interconnect_0_to_s00_couplers_ARREGION),\n        .S_AXI_arsize(axi_interconnect_0_to_s00_couplers_ARSIZE),\n        .S_AXI_arvalid(axi_interconnect_0_to_s00_couplers_ARVALID),\n        .S_AXI_awaddr(axi_interconnect_0_to_s00_couplers_AWADDR),\n        .S_AXI_awburst(axi_interconnect_0_to_s00_couplers_AWBURST),\n        .S_AXI_awcache(axi_interconnect_0_to_s00_couplers_AWCACHE),\n        .S_AXI_awid(axi_interconnect_0_to_s00_couplers_AWID),\n        .S_AXI_awlen(axi_interconnect_0_to_s00_couplers_AWLEN),\n        .S_AXI_awlock(axi_interconnect_0_to_s00_couplers_AWLOCK),\n        .S_AXI_awprot(axi_interconnect_0_to_s00_couplers_AWPROT),\n        .S_AXI_awqos(axi_interconnect_0_to_s00_couplers_AWQOS),\n        .S_AXI_awready(axi_interconnect_0_to_s00_couplers_AWREADY),\n        .S_AXI_awregion(axi_interconnect_0_to_s00_couplers_AWREGION),\n        .S_AXI_awsize(axi_interconnect_0_to_s00_couplers_AWSIZE),\n        .S_AXI_awvalid(axi_interconnect_0_to_s00_couplers_AWVALID),\n        .S_AXI_bid(axi_interconnect_0_to_s00_couplers_BID),\n        .S_AXI_bready(axi_interconnect_0_to_s00_couplers_BREADY),\n        .S_AXI_bresp(axi_interconnect_0_to_s00_couplers_BRESP),\n        .S_AXI_bvalid(axi_interconnect_0_to_s00_couplers_BVALID),\n        .S_AXI_rdata(axi_interconnect_0_to_s00_couplers_RDATA),\n        .S_AXI_rid(axi_interconnect_0_to_s00_couplers_RID),\n        .S_AXI_rlast(axi_interconnect_0_to_s00_couplers_RLAST),\n        .S_AXI_rready(axi_interconnect_0_to_s00_couplers_RREADY),\n        .S_AXI_rresp(axi_interconnect_0_to_s00_couplers_RRESP),\n        .S_AXI_rvalid(axi_interconnect_0_to_s00_couplers_RVALID),\n        .S_AXI_wdata(axi_interconnect_0_to_s00_couplers_WDATA),\n        .S_AXI_wlast(axi_interconnect_0_to_s00_couplers_WLAST),\n        .S_AXI_wready(axi_interconnect_0_to_s00_couplers_WREADY),\n        .S_AXI_wstrb(axi_interconnect_0_to_s00_couplers_WSTRB),\n        .S_AXI_wvalid(axi_interconnect_0_to_s00_couplers_WVALID));\n  s01_couplers_imp_GSTXQ8 s01_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(s01_couplers_to_xbar_ARADDR),\n        .M_AXI_arburst(s01_couplers_to_xbar_ARBURST),\n        .M_AXI_arcache(s01_couplers_to_xbar_ARCACHE),\n        .M_AXI_arid(s01_couplers_to_xbar_ARID),\n        .M_AXI_arlen(s01_couplers_to_xbar_ARLEN),\n        .M_AXI_arlock(s01_couplers_to_xbar_ARLOCK),\n        .M_AXI_arprot(s01_couplers_to_xbar_ARPROT),\n        .M_AXI_arqos(s01_couplers_to_xbar_ARQOS),\n        .M_AXI_arready(s01_couplers_to_xbar_ARREADY),\n        .M_AXI_arsize(s01_couplers_to_xbar_ARSIZE),\n        .M_AXI_arvalid(s01_couplers_to_xbar_ARVALID),\n        .M_AXI_awaddr(s01_couplers_to_xbar_AWADDR),\n        .M_AXI_awburst(s01_couplers_to_xbar_AWBURST),\n        .M_AXI_awcache(s01_couplers_to_xbar_AWCACHE),\n        .M_AXI_awid(s01_couplers_to_xbar_AWID),\n        .M_AXI_awlen(s01_couplers_to_xbar_AWLEN),\n        .M_AXI_awlock(s01_couplers_to_xbar_AWLOCK),\n        .M_AXI_awprot(s01_couplers_to_xbar_AWPROT),\n        .M_AXI_awqos(s01_couplers_to_xbar_AWQOS),\n        .M_AXI_awready(s01_couplers_to_xbar_AWREADY),\n        .M_AXI_awsize(s01_couplers_to_xbar_AWSIZE),\n        .M_AXI_awvalid(s01_couplers_to_xbar_AWVALID),\n        .M_AXI_bid(s01_couplers_to_xbar_BID),\n        .M_AXI_bready(s01_couplers_to_xbar_BREADY),\n        .M_AXI_bresp(s01_couplers_to_xbar_BRESP),\n        .M_AXI_bvalid(s01_couplers_to_xbar_BVALID),\n        .M_AXI_rdata(s01_couplers_to_xbar_RDATA),\n        .M_AXI_rid(s01_couplers_to_xbar_RID),\n        .M_AXI_rlast(s01_couplers_to_xbar_RLAST),\n        .M_AXI_rready(s01_couplers_to_xbar_RREADY),\n        .M_AXI_rresp(s01_couplers_to_xbar_RRESP),\n        .M_AXI_rvalid(s01_couplers_to_xbar_RVALID),\n        .M_AXI_wdata(s01_couplers_to_xbar_WDATA),\n        .M_AXI_wlast(s01_couplers_to_xbar_WLAST),\n        .M_AXI_wready(s01_couplers_to_xbar_WREADY),\n        .M_AXI_wstrb(s01_couplers_to_xbar_WSTRB),\n        .M_AXI_wvalid(s01_couplers_to_xbar_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(axi_interconnect_0_to_s01_couplers_ARADDR),\n        .S_AXI_arburst(axi_interconnect_0_to_s01_couplers_ARBURST),\n        .S_AXI_arcache(axi_interconnect_0_to_s01_couplers_ARCACHE),\n        .S_AXI_arid(axi_interconnect_0_to_s01_couplers_ARID),\n        .S_AXI_arlen(axi_interconnect_0_to_s01_couplers_ARLEN),\n        .S_AXI_arlock(axi_interconnect_0_to_s01_couplers_ARLOCK),\n        .S_AXI_arprot(axi_interconnect_0_to_s01_couplers_ARPROT),\n        .S_AXI_arqos(axi_interconnect_0_to_s01_couplers_ARQOS),\n        .S_AXI_arready(axi_interconnect_0_to_s01_couplers_ARREADY),\n        .S_AXI_arregion(axi_interconnect_0_to_s01_couplers_ARREGION),\n        .S_AXI_arsize(axi_interconnect_0_to_s01_couplers_ARSIZE),\n        .S_AXI_arvalid(axi_interconnect_0_to_s01_couplers_ARVALID),\n        .S_AXI_awaddr(axi_interconnect_0_to_s01_couplers_AWADDR),\n        .S_AXI_awburst(axi_interconnect_0_to_s01_couplers_AWBURST),\n        .S_AXI_awcache(axi_interconnect_0_to_s01_couplers_AWCACHE),\n        .S_AXI_awid(axi_interconnect_0_to_s01_couplers_AWID),\n        .S_AXI_awlen(axi_interconnect_0_to_s01_couplers_AWLEN),\n        .S_AXI_awlock(axi_interconnect_0_to_s01_couplers_AWLOCK),\n        .S_AXI_awprot(axi_interconnect_0_to_s01_couplers_AWPROT),\n        .S_AXI_awqos(axi_interconnect_0_to_s01_couplers_AWQOS),\n        .S_AXI_awready(axi_interconnect_0_to_s01_couplers_AWREADY),\n        .S_AXI_awregion(axi_interconnect_0_to_s01_couplers_AWREGION),\n        .S_AXI_awsize(axi_interconnect_0_to_s01_couplers_AWSIZE),\n        .S_AXI_awvalid(axi_interconnect_0_to_s01_couplers_AWVALID),\n        .S_AXI_bid(axi_interconnect_0_to_s01_couplers_BID),\n        .S_AXI_bready(axi_interconnect_0_to_s01_couplers_BREADY),\n        .S_AXI_bresp(axi_interconnect_0_to_s01_couplers_BRESP),\n        .S_AXI_bvalid(axi_interconnect_0_to_s01_couplers_BVALID),\n        .S_AXI_rdata(axi_interconnect_0_to_s01_couplers_RDATA),\n        .S_AXI_rid(axi_interconnect_0_to_s01_couplers_RID),\n        .S_AXI_rlast(axi_interconnect_0_to_s01_couplers_RLAST),\n        .S_AXI_rready(axi_interconnect_0_to_s01_couplers_RREADY),\n        .S_AXI_rresp(axi_interconnect_0_to_s01_couplers_RRESP),\n        .S_AXI_rvalid(axi_interconnect_0_to_s01_couplers_RVALID),\n        .S_AXI_wdata(axi_interconnect_0_to_s01_couplers_WDATA),\n        .S_AXI_wlast(axi_interconnect_0_to_s01_couplers_WLAST),\n        .S_AXI_wready(axi_interconnect_0_to_s01_couplers_WREADY),\n        .S_AXI_wstrb(axi_interconnect_0_to_s01_couplers_WSTRB),\n        .S_AXI_wvalid(axi_interconnect_0_to_s01_couplers_WVALID));\n  cl_axi_interconnect_xbar_0 xbar\n       (.aclk(axi_interconnect_0_ACLK_net),\n        .aresetn(axi_interconnect_0_ARESETN_net),\n        .m_axi_araddr({xbar_to_m03_couplers_ARADDR,xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),\n        .m_axi_arburst({xbar_to_m03_couplers_ARBURST,xbar_to_m02_couplers_ARBURST,xbar_to_m01_couplers_ARBURST,xbar_to_m00_couplers_ARBURST}),\n        .m_axi_arcache({xbar_to_m03_couplers_ARCACHE,xbar_to_m02_couplers_ARCACHE,xbar_to_m01_couplers_ARCACHE,xbar_to_m00_couplers_ARCACHE}),\n        .m_axi_arid({xbar_to_m03_couplers_ARID,xbar_to_m02_couplers_ARID,xbar_to_m01_couplers_ARID,xbar_to_m00_couplers_ARID}),\n        .m_axi_arlen({xbar_to_m03_couplers_ARLEN,xbar_to_m02_couplers_ARLEN,xbar_to_m01_couplers_ARLEN,xbar_to_m00_couplers_ARLEN}),\n        .m_axi_arlock({xbar_to_m03_couplers_ARLOCK,xbar_to_m02_couplers_ARLOCK,xbar_to_m01_couplers_ARLOCK,xbar_to_m00_couplers_ARLOCK}),\n        .m_axi_arprot({xbar_to_m03_couplers_ARPROT,xbar_to_m02_couplers_ARPROT,xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}),\n        .m_axi_arqos({xbar_to_m03_couplers_ARQOS,xbar_to_m02_couplers_ARQOS,xbar_to_m01_couplers_ARQOS,xbar_to_m00_couplers_ARQOS}),\n        .m_axi_arready({xbar_to_m03_couplers_ARREADY,xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),\n        .m_axi_arregion({xbar_to_m03_couplers_ARREGION,xbar_to_m02_couplers_ARREGION,xbar_to_m01_couplers_ARREGION,xbar_to_m00_couplers_ARREGION}),\n        .m_axi_arsize({xbar_to_m03_couplers_ARSIZE,xbar_to_m02_couplers_ARSIZE,xbar_to_m01_couplers_ARSIZE,xbar_to_m00_couplers_ARSIZE}),\n        .m_axi_arvalid({xbar_to_m03_couplers_ARVALID,xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),\n        .m_axi_awaddr({xbar_to_m03_couplers_AWADDR,xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),\n        .m_axi_awburst({xbar_to_m03_couplers_AWBURST,xbar_to_m02_couplers_AWBURST,xbar_to_m01_couplers_AWBURST,xbar_to_m00_couplers_AWBURST}),\n        .m_axi_awcache({xbar_to_m03_couplers_AWCACHE,xbar_to_m02_couplers_AWCACHE,xbar_to_m01_couplers_AWCACHE,xbar_to_m00_couplers_AWCACHE}),\n        .m_axi_awid({xbar_to_m03_couplers_AWID,xbar_to_m02_couplers_AWID,xbar_to_m01_couplers_AWID,xbar_to_m00_couplers_AWID}),\n        .m_axi_awlen({xbar_to_m03_couplers_AWLEN,xbar_to_m02_couplers_AWLEN,xbar_to_m01_couplers_AWLEN,xbar_to_m00_couplers_AWLEN}),\n        .m_axi_awlock({xbar_to_m03_couplers_AWLOCK,xbar_to_m02_couplers_AWLOCK,xbar_to_m01_couplers_AWLOCK,xbar_to_m00_couplers_AWLOCK}),\n        .m_axi_awprot({xbar_to_m03_couplers_AWPROT,xbar_to_m02_couplers_AWPROT,xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}),\n        .m_axi_awqos({xbar_to_m03_couplers_AWQOS,xbar_to_m02_couplers_AWQOS,xbar_to_m01_couplers_AWQOS,xbar_to_m00_couplers_AWQOS}),\n        .m_axi_awready({xbar_to_m03_couplers_AWREADY,xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),\n        .m_axi_awregion({xbar_to_m03_couplers_AWREGION,xbar_to_m02_couplers_AWREGION,xbar_to_m01_couplers_AWREGION,xbar_to_m00_couplers_AWREGION}),\n        .m_axi_awsize({xbar_to_m03_couplers_AWSIZE,xbar_to_m02_couplers_AWSIZE,xbar_to_m01_couplers_AWSIZE,xbar_to_m00_couplers_AWSIZE}),\n        .m_axi_awvalid({xbar_to_m03_couplers_AWVALID,xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),\n        .m_axi_bid({xbar_to_m03_couplers_BID,xbar_to_m02_couplers_BID,xbar_to_m01_couplers_BID,xbar_to_m00_couplers_BID}),\n        .m_axi_bready({xbar_to_m03_couplers_BREADY,xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),\n        .m_axi_bresp({xbar_to_m03_couplers_BRESP,xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),\n        .m_axi_bvalid({xbar_to_m03_couplers_BVALID,xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),\n        .m_axi_rdata({xbar_to_m03_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),\n        .m_axi_rid({xbar_to_m03_couplers_RID,xbar_to_m02_couplers_RID,xbar_to_m01_couplers_RID,xbar_to_m00_couplers_RID}),\n        .m_axi_rlast({xbar_to_m03_couplers_RLAST,xbar_to_m02_couplers_RLAST,xbar_to_m01_couplers_RLAST,xbar_to_m00_couplers_RLAST}),\n        .m_axi_rready({xbar_to_m03_couplers_RREADY,xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),\n        .m_axi_rresp({xbar_to_m03_couplers_RRESP,xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),\n        .m_axi_rvalid({xbar_to_m03_couplers_RVALID,xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),\n        .m_axi_wdata({xbar_to_m03_couplers_WDATA,xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),\n        .m_axi_wlast({xbar_to_m03_couplers_WLAST,xbar_to_m02_couplers_WLAST,xbar_to_m01_couplers_WLAST,xbar_to_m00_couplers_WLAST}),\n        .m_axi_wready({xbar_to_m03_couplers_WREADY,xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),\n        .m_axi_wstrb({xbar_to_m03_couplers_WSTRB,xbar_to_m02_couplers_WSTRB,xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),\n        .m_axi_wvalid({xbar_to_m03_couplers_WVALID,xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),\n        .s_axi_araddr({s01_couplers_to_xbar_ARADDR,s00_couplers_to_xbar_ARADDR}),\n        .s_axi_arburst({s01_couplers_to_xbar_ARBURST,s00_couplers_to_xbar_ARBURST}),\n        .s_axi_arcache({s01_couplers_to_xbar_ARCACHE,s00_couplers_to_xbar_ARCACHE}),\n        .s_axi_arid({1'b0,s01_couplers_to_xbar_ARID,1'b0,s00_couplers_to_xbar_ARID}),\n        .s_axi_arlen({s01_couplers_to_xbar_ARLEN,s00_couplers_to_xbar_ARLEN}),\n        .s_axi_arlock({s01_couplers_to_xbar_ARLOCK,s00_couplers_to_xbar_ARLOCK}),\n        .s_axi_arprot({s01_couplers_to_xbar_ARPROT,s00_couplers_to_xbar_ARPROT}),\n        .s_axi_arqos({s01_couplers_to_xbar_ARQOS,s00_couplers_to_xbar_ARQOS}),\n        .s_axi_arready({s01_couplers_to_xbar_ARREADY,s00_couplers_to_xbar_ARREADY}),\n        .s_axi_arsize({s01_couplers_to_xbar_ARSIZE,s00_couplers_to_xbar_ARSIZE}),\n        .s_axi_arvalid({s01_couplers_to_xbar_ARVALID,s00_couplers_to_xbar_ARVALID}),\n        .s_axi_awaddr({s01_couplers_to_xbar_AWADDR,s00_couplers_to_xbar_AWADDR}),\n        .s_axi_awburst({s01_couplers_to_xbar_AWBURST,s00_couplers_to_xbar_AWBURST}),\n        .s_axi_awcache({s01_couplers_to_xbar_AWCACHE,s00_couplers_to_xbar_AWCACHE}),\n        .s_axi_awid({1'b0,s01_couplers_to_xbar_AWID,1'b0,s00_couplers_to_xbar_AWID}),\n        .s_axi_awlen({s01_couplers_to_xbar_AWLEN,s00_couplers_to_xbar_AWLEN}),\n        .s_axi_awlock({s01_couplers_to_xbar_AWLOCK,s00_couplers_to_xbar_AWLOCK}),\n        .s_axi_awprot({s01_couplers_to_xbar_AWPROT,s00_couplers_to_xbar_AWPROT}),\n        .s_axi_awqos({s01_couplers_to_xbar_AWQOS,s00_couplers_to_xbar_AWQOS}),\n        .s_axi_awready({s01_couplers_to_xbar_AWREADY,s00_couplers_to_xbar_AWREADY}),\n        .s_axi_awsize({s01_couplers_to_xbar_AWSIZE,s00_couplers_to_xbar_AWSIZE}),\n        .s_axi_awvalid({s01_couplers_to_xbar_AWVALID,s00_couplers_to_xbar_AWVALID}),\n        .s_axi_bid({s01_couplers_to_xbar_BID,s00_couplers_to_xbar_BID}),\n        .s_axi_bready({s01_couplers_to_xbar_BREADY,s00_couplers_to_xbar_BREADY}),\n        .s_axi_bresp({s01_couplers_to_xbar_BRESP,s00_couplers_to_xbar_BRESP}),\n        .s_axi_bvalid({s01_couplers_to_xbar_BVALID,s00_couplers_to_xbar_BVALID}),\n        .s_axi_rdata({s01_couplers_to_xbar_RDATA,s00_couplers_to_xbar_RDATA}),\n        .s_axi_rid({s01_couplers_to_xbar_RID,s00_couplers_to_xbar_RID}),\n        .s_axi_rlast({s01_couplers_to_xbar_RLAST,s00_couplers_to_xbar_RLAST}),\n        .s_axi_rready({s01_couplers_to_xbar_RREADY,s00_couplers_to_xbar_RREADY}),\n        .s_axi_rresp({s01_couplers_to_xbar_RRESP,s00_couplers_to_xbar_RRESP}),\n        .s_axi_rvalid({s01_couplers_to_xbar_RVALID,s00_couplers_to_xbar_RVALID}),\n        .s_axi_wdata({s01_couplers_to_xbar_WDATA,s00_couplers_to_xbar_WDATA}),\n        .s_axi_wlast({s01_couplers_to_xbar_WLAST,s00_couplers_to_xbar_WLAST}),\n        .s_axi_wready({s01_couplers_to_xbar_WREADY,s00_couplers_to_xbar_WREADY}),\n        .s_axi_wstrb({s01_couplers_to_xbar_WSTRB,s00_couplers_to_xbar_WSTRB}),\n        .s_axi_wvalid({s01_couplers_to_xbar_WVALID,s00_couplers_to_xbar_WVALID}));\nendmodule\n\nmodule m00_couplers_imp_1QBJ6U2\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m00_couplers_to_m00_regslice_ARADDR;\n  wire [1:0]m00_couplers_to_m00_regslice_ARBURST;\n  wire [3:0]m00_couplers_to_m00_regslice_ARCACHE;\n  wire [6:0]m00_couplers_to_m00_regslice_ARID;\n  wire [7:0]m00_couplers_to_m00_regslice_ARLEN;\n  wire [0:0]m00_couplers_to_m00_regslice_ARLOCK;\n  wire [2:0]m00_couplers_to_m00_regslice_ARPROT;\n  wire [3:0]m00_couplers_to_m00_regslice_ARQOS;\n  wire m00_couplers_to_m00_regslice_ARREADY;\n  wire [3:0]m00_couplers_to_m00_regslice_ARREGION;\n  wire [2:0]m00_couplers_to_m00_regslice_ARSIZE;\n  wire m00_couplers_to_m00_regslice_ARVALID;\n  wire [63:0]m00_couplers_to_m00_regslice_AWADDR;\n  wire [1:0]m00_couplers_to_m00_regslice_AWBURST;\n  wire [3:0]m00_couplers_to_m00_regslice_AWCACHE;\n  wire [6:0]m00_couplers_to_m00_regslice_AWID;\n  wire [7:0]m00_couplers_to_m00_regslice_AWLEN;\n  wire [0:0]m00_couplers_to_m00_regslice_AWLOCK;\n  wire [2:0]m00_couplers_to_m00_regslice_AWPROT;\n  wire [3:0]m00_couplers_to_m00_regslice_AWQOS;\n  wire m00_couplers_to_m00_regslice_AWREADY;\n  wire [3:0]m00_couplers_to_m00_regslice_AWREGION;\n  wire [2:0]m00_couplers_to_m00_regslice_AWSIZE;\n  wire m00_couplers_to_m00_regslice_AWVALID;\n  wire [6:0]m00_couplers_to_m00_regslice_BID;\n  wire m00_couplers_to_m00_regslice_BREADY;\n  wire [1:0]m00_couplers_to_m00_regslice_BRESP;\n  wire m00_couplers_to_m00_regslice_BVALID;\n  wire [511:0]m00_couplers_to_m00_regslice_RDATA;\n  wire [6:0]m00_couplers_to_m00_regslice_RID;\n  wire m00_couplers_to_m00_regslice_RLAST;\n  wire m00_couplers_to_m00_regslice_RREADY;\n  wire [1:0]m00_couplers_to_m00_regslice_RRESP;\n  wire m00_couplers_to_m00_regslice_RVALID;\n  wire [511:0]m00_couplers_to_m00_regslice_WDATA;\n  wire m00_couplers_to_m00_regslice_WLAST;\n  wire m00_couplers_to_m00_regslice_WREADY;\n  wire [63:0]m00_couplers_to_m00_regslice_WSTRB;\n  wire m00_couplers_to_m00_regslice_WVALID;\n  wire [63:0]m00_regslice_to_m00_couplers_ARADDR;\n  wire [1:0]m00_regslice_to_m00_couplers_ARBURST;\n  wire [3:0]m00_regslice_to_m00_couplers_ARCACHE;\n  wire [6:0]m00_regslice_to_m00_couplers_ARID;\n  wire [7:0]m00_regslice_to_m00_couplers_ARLEN;\n  wire [0:0]m00_regslice_to_m00_couplers_ARLOCK;\n  wire [2:0]m00_regslice_to_m00_couplers_ARPROT;\n  wire [3:0]m00_regslice_to_m00_couplers_ARQOS;\n  wire m00_regslice_to_m00_couplers_ARREADY;\n  wire [3:0]m00_regslice_to_m00_couplers_ARREGION;\n  wire [2:0]m00_regslice_to_m00_couplers_ARSIZE;\n  wire m00_regslice_to_m00_couplers_ARVALID;\n  wire [63:0]m00_regslice_to_m00_couplers_AWADDR;\n  wire [1:0]m00_regslice_to_m00_couplers_AWBURST;\n  wire [3:0]m00_regslice_to_m00_couplers_AWCACHE;\n  wire [6:0]m00_regslice_to_m00_couplers_AWID;\n  wire [7:0]m00_regslice_to_m00_couplers_AWLEN;\n  wire [0:0]m00_regslice_to_m00_couplers_AWLOCK;\n  wire [2:0]m00_regslice_to_m00_couplers_AWPROT;\n  wire [3:0]m00_regslice_to_m00_couplers_AWQOS;\n  wire m00_regslice_to_m00_couplers_AWREADY;\n  wire [3:0]m00_regslice_to_m00_couplers_AWREGION;\n  wire [2:0]m00_regslice_to_m00_couplers_AWSIZE;\n  wire m00_regslice_to_m00_couplers_AWVALID;\n  wire [6:0]m00_regslice_to_m00_couplers_BID;\n  wire m00_regslice_to_m00_couplers_BREADY;\n  wire [1:0]m00_regslice_to_m00_couplers_BRESP;\n  wire m00_regslice_to_m00_couplers_BVALID;\n  wire [511:0]m00_regslice_to_m00_couplers_RDATA;\n  wire [6:0]m00_regslice_to_m00_couplers_RID;\n  wire m00_regslice_to_m00_couplers_RLAST;\n  wire m00_regslice_to_m00_couplers_RREADY;\n  wire [1:0]m00_regslice_to_m00_couplers_RRESP;\n  wire m00_regslice_to_m00_couplers_RVALID;\n  wire [511:0]m00_regslice_to_m00_couplers_WDATA;\n  wire m00_regslice_to_m00_couplers_WLAST;\n  wire m00_regslice_to_m00_couplers_WREADY;\n  wire [63:0]m00_regslice_to_m00_couplers_WSTRB;\n  wire m00_regslice_to_m00_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m00_regslice_to_m00_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m00_regslice_to_m00_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m00_regslice_to_m00_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m00_regslice_to_m00_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m00_regslice_to_m00_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m00_regslice_to_m00_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m00_regslice_to_m00_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m00_regslice_to_m00_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m00_regslice_to_m00_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m00_regslice_to_m00_couplers_ARSIZE;\n  assign M_AXI_arvalid = m00_regslice_to_m00_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m00_regslice_to_m00_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m00_regslice_to_m00_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m00_regslice_to_m00_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m00_regslice_to_m00_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m00_regslice_to_m00_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m00_regslice_to_m00_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m00_regslice_to_m00_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m00_regslice_to_m00_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m00_regslice_to_m00_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m00_regslice_to_m00_couplers_AWSIZE;\n  assign M_AXI_awvalid = m00_regslice_to_m00_couplers_AWVALID;\n  assign M_AXI_bready = m00_regslice_to_m00_couplers_BREADY;\n  assign M_AXI_rready = m00_regslice_to_m00_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m00_regslice_to_m00_couplers_WDATA;\n  assign M_AXI_wlast = m00_regslice_to_m00_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m00_regslice_to_m00_couplers_WSTRB;\n  assign M_AXI_wvalid = m00_regslice_to_m00_couplers_WVALID;\n  assign S_AXI_arready = m00_couplers_to_m00_regslice_ARREADY;\n  assign S_AXI_awready = m00_couplers_to_m00_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m00_couplers_to_m00_regslice_BID;\n  assign S_AXI_bresp[1:0] = m00_couplers_to_m00_regslice_BRESP;\n  assign S_AXI_bvalid = m00_couplers_to_m00_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m00_couplers_to_m00_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m00_couplers_to_m00_regslice_RID;\n  assign S_AXI_rlast = m00_couplers_to_m00_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m00_couplers_to_m00_regslice_RRESP;\n  assign S_AXI_rvalid = m00_couplers_to_m00_regslice_RVALID;\n  assign S_AXI_wready = m00_couplers_to_m00_regslice_WREADY;\n  assign m00_couplers_to_m00_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m00_couplers_to_m00_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m00_couplers_to_m00_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m00_couplers_to_m00_regslice_ARID = S_AXI_arid[6:0];\n  assign m00_couplers_to_m00_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m00_couplers_to_m00_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m00_couplers_to_m00_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m00_couplers_to_m00_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m00_couplers_to_m00_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m00_couplers_to_m00_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m00_couplers_to_m00_regslice_ARVALID = S_AXI_arvalid;\n  assign m00_couplers_to_m00_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m00_couplers_to_m00_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m00_couplers_to_m00_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m00_couplers_to_m00_regslice_AWID = S_AXI_awid[6:0];\n  assign m00_couplers_to_m00_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m00_couplers_to_m00_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m00_couplers_to_m00_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m00_couplers_to_m00_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m00_couplers_to_m00_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m00_couplers_to_m00_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m00_couplers_to_m00_regslice_AWVALID = S_AXI_awvalid;\n  assign m00_couplers_to_m00_regslice_BREADY = S_AXI_bready;\n  assign m00_couplers_to_m00_regslice_RREADY = S_AXI_rready;\n  assign m00_couplers_to_m00_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m00_couplers_to_m00_regslice_WLAST = S_AXI_wlast;\n  assign m00_couplers_to_m00_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m00_couplers_to_m00_regslice_WVALID = S_AXI_wvalid;\n  assign m00_regslice_to_m00_couplers_ARREADY = M_AXI_arready;\n  assign m00_regslice_to_m00_couplers_AWREADY = M_AXI_awready;\n  assign m00_regslice_to_m00_couplers_BID = M_AXI_bid[6:0];\n  assign m00_regslice_to_m00_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m00_regslice_to_m00_couplers_BVALID = M_AXI_bvalid;\n  assign m00_regslice_to_m00_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m00_regslice_to_m00_couplers_RID = M_AXI_rid[6:0];\n  assign m00_regslice_to_m00_couplers_RLAST = M_AXI_rlast;\n  assign m00_regslice_to_m00_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m00_regslice_to_m00_couplers_RVALID = M_AXI_rvalid;\n  assign m00_regslice_to_m00_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m00_regslice_0 m00_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m00_regslice_to_m00_couplers_ARADDR),\n        .m_axi_arburst(m00_regslice_to_m00_couplers_ARBURST),\n        .m_axi_arcache(m00_regslice_to_m00_couplers_ARCACHE),\n        .m_axi_arid(m00_regslice_to_m00_couplers_ARID),\n        .m_axi_arlen(m00_regslice_to_m00_couplers_ARLEN),\n        .m_axi_arlock(m00_regslice_to_m00_couplers_ARLOCK),\n        .m_axi_arprot(m00_regslice_to_m00_couplers_ARPROT),\n        .m_axi_arqos(m00_regslice_to_m00_couplers_ARQOS),\n        .m_axi_arready(m00_regslice_to_m00_couplers_ARREADY),\n        .m_axi_arregion(m00_regslice_to_m00_couplers_ARREGION),\n        .m_axi_arsize(m00_regslice_to_m00_couplers_ARSIZE),\n        .m_axi_arvalid(m00_regslice_to_m00_couplers_ARVALID),\n        .m_axi_awaddr(m00_regslice_to_m00_couplers_AWADDR),\n        .m_axi_awburst(m00_regslice_to_m00_couplers_AWBURST),\n        .m_axi_awcache(m00_regslice_to_m00_couplers_AWCACHE),\n        .m_axi_awid(m00_regslice_to_m00_couplers_AWID),\n        .m_axi_awlen(m00_regslice_to_m00_couplers_AWLEN),\n        .m_axi_awlock(m00_regslice_to_m00_couplers_AWLOCK),\n        .m_axi_awprot(m00_regslice_to_m00_couplers_AWPROT),\n        .m_axi_awqos(m00_regslice_to_m00_couplers_AWQOS),\n        .m_axi_awready(m00_regslice_to_m00_couplers_AWREADY),\n        .m_axi_awregion(m00_regslice_to_m00_couplers_AWREGION),\n        .m_axi_awsize(m00_regslice_to_m00_couplers_AWSIZE),\n        .m_axi_awvalid(m00_regslice_to_m00_couplers_AWVALID),\n        .m_axi_bid(m00_regslice_to_m00_couplers_BID),\n        .m_axi_bready(m00_regslice_to_m00_couplers_BREADY),\n        .m_axi_bresp(m00_regslice_to_m00_couplers_BRESP),\n        .m_axi_bvalid(m00_regslice_to_m00_couplers_BVALID),\n        .m_axi_rdata(m00_regslice_to_m00_couplers_RDATA),\n        .m_axi_rid(m00_regslice_to_m00_couplers_RID),\n        .m_axi_rlast(m00_regslice_to_m00_couplers_RLAST),\n        .m_axi_rready(m00_regslice_to_m00_couplers_RREADY),\n        .m_axi_rresp(m00_regslice_to_m00_couplers_RRESP),\n        .m_axi_rvalid(m00_regslice_to_m00_couplers_RVALID),\n        .m_axi_wdata(m00_regslice_to_m00_couplers_WDATA),\n        .m_axi_wlast(m00_regslice_to_m00_couplers_WLAST),\n        .m_axi_wready(m00_regslice_to_m00_couplers_WREADY),\n        .m_axi_wstrb(m00_regslice_to_m00_couplers_WSTRB),\n        .m_axi_wvalid(m00_regslice_to_m00_couplers_WVALID),\n        .s_axi_araddr(m00_couplers_to_m00_regslice_ARADDR),\n        .s_axi_arburst(m00_couplers_to_m00_regslice_ARBURST),\n        .s_axi_arcache(m00_couplers_to_m00_regslice_ARCACHE),\n        .s_axi_arid(m00_couplers_to_m00_regslice_ARID),\n        .s_axi_arlen(m00_couplers_to_m00_regslice_ARLEN),\n        .s_axi_arlock(m00_couplers_to_m00_regslice_ARLOCK),\n        .s_axi_arprot(m00_couplers_to_m00_regslice_ARPROT),\n        .s_axi_arqos(m00_couplers_to_m00_regslice_ARQOS),\n        .s_axi_arready(m00_couplers_to_m00_regslice_ARREADY),\n        .s_axi_arregion(m00_couplers_to_m00_regslice_ARREGION),\n        .s_axi_arsize(m00_couplers_to_m00_regslice_ARSIZE),\n        .s_axi_arvalid(m00_couplers_to_m00_regslice_ARVALID),\n        .s_axi_awaddr(m00_couplers_to_m00_regslice_AWADDR),\n        .s_axi_awburst(m00_couplers_to_m00_regslice_AWBURST),\n        .s_axi_awcache(m00_couplers_to_m00_regslice_AWCACHE),\n        .s_axi_awid(m00_couplers_to_m00_regslice_AWID),\n        .s_axi_awlen(m00_couplers_to_m00_regslice_AWLEN),\n        .s_axi_awlock(m00_couplers_to_m00_regslice_AWLOCK),\n        .s_axi_awprot(m00_couplers_to_m00_regslice_AWPROT),\n        .s_axi_awqos(m00_couplers_to_m00_regslice_AWQOS),\n        .s_axi_awready(m00_couplers_to_m00_regslice_AWREADY),\n        .s_axi_awregion(m00_couplers_to_m00_regslice_AWREGION),\n        .s_axi_awsize(m00_couplers_to_m00_regslice_AWSIZE),\n        .s_axi_awvalid(m00_couplers_to_m00_regslice_AWVALID),\n        .s_axi_bid(m00_couplers_to_m00_regslice_BID),\n        .s_axi_bready(m00_couplers_to_m00_regslice_BREADY),\n        .s_axi_bresp(m00_couplers_to_m00_regslice_BRESP),\n        .s_axi_bvalid(m00_couplers_to_m00_regslice_BVALID),\n        .s_axi_rdata(m00_couplers_to_m00_regslice_RDATA),\n        .s_axi_rid(m00_couplers_to_m00_regslice_RID),\n        .s_axi_rlast(m00_couplers_to_m00_regslice_RLAST),\n        .s_axi_rready(m00_couplers_to_m00_regslice_RREADY),\n        .s_axi_rresp(m00_couplers_to_m00_regslice_RRESP),\n        .s_axi_rvalid(m00_couplers_to_m00_regslice_RVALID),\n        .s_axi_wdata(m00_couplers_to_m00_regslice_WDATA),\n        .s_axi_wlast(m00_couplers_to_m00_regslice_WLAST),\n        .s_axi_wready(m00_couplers_to_m00_regslice_WREADY),\n        .s_axi_wstrb(m00_couplers_to_m00_regslice_WSTRB),\n        .s_axi_wvalid(m00_couplers_to_m00_regslice_WVALID));\nendmodule\n\nmodule m01_couplers_imp_10IMR9A\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m01_couplers_to_m01_regslice_ARADDR;\n  wire [1:0]m01_couplers_to_m01_regslice_ARBURST;\n  wire [3:0]m01_couplers_to_m01_regslice_ARCACHE;\n  wire [6:0]m01_couplers_to_m01_regslice_ARID;\n  wire [7:0]m01_couplers_to_m01_regslice_ARLEN;\n  wire [0:0]m01_couplers_to_m01_regslice_ARLOCK;\n  wire [2:0]m01_couplers_to_m01_regslice_ARPROT;\n  wire [3:0]m01_couplers_to_m01_regslice_ARQOS;\n  wire m01_couplers_to_m01_regslice_ARREADY;\n  wire [3:0]m01_couplers_to_m01_regslice_ARREGION;\n  wire [2:0]m01_couplers_to_m01_regslice_ARSIZE;\n  wire m01_couplers_to_m01_regslice_ARVALID;\n  wire [63:0]m01_couplers_to_m01_regslice_AWADDR;\n  wire [1:0]m01_couplers_to_m01_regslice_AWBURST;\n  wire [3:0]m01_couplers_to_m01_regslice_AWCACHE;\n  wire [6:0]m01_couplers_to_m01_regslice_AWID;\n  wire [7:0]m01_couplers_to_m01_regslice_AWLEN;\n  wire [0:0]m01_couplers_to_m01_regslice_AWLOCK;\n  wire [2:0]m01_couplers_to_m01_regslice_AWPROT;\n  wire [3:0]m01_couplers_to_m01_regslice_AWQOS;\n  wire m01_couplers_to_m01_regslice_AWREADY;\n  wire [3:0]m01_couplers_to_m01_regslice_AWREGION;\n  wire [2:0]m01_couplers_to_m01_regslice_AWSIZE;\n  wire m01_couplers_to_m01_regslice_AWVALID;\n  wire [6:0]m01_couplers_to_m01_regslice_BID;\n  wire m01_couplers_to_m01_regslice_BREADY;\n  wire [1:0]m01_couplers_to_m01_regslice_BRESP;\n  wire m01_couplers_to_m01_regslice_BVALID;\n  wire [511:0]m01_couplers_to_m01_regslice_RDATA;\n  wire [6:0]m01_couplers_to_m01_regslice_RID;\n  wire m01_couplers_to_m01_regslice_RLAST;\n  wire m01_couplers_to_m01_regslice_RREADY;\n  wire [1:0]m01_couplers_to_m01_regslice_RRESP;\n  wire m01_couplers_to_m01_regslice_RVALID;\n  wire [511:0]m01_couplers_to_m01_regslice_WDATA;\n  wire m01_couplers_to_m01_regslice_WLAST;\n  wire m01_couplers_to_m01_regslice_WREADY;\n  wire [63:0]m01_couplers_to_m01_regslice_WSTRB;\n  wire m01_couplers_to_m01_regslice_WVALID;\n  wire [63:0]m01_regslice_to_m01_couplers_ARADDR;\n  wire [1:0]m01_regslice_to_m01_couplers_ARBURST;\n  wire [3:0]m01_regslice_to_m01_couplers_ARCACHE;\n  wire [6:0]m01_regslice_to_m01_couplers_ARID;\n  wire [7:0]m01_regslice_to_m01_couplers_ARLEN;\n  wire [0:0]m01_regslice_to_m01_couplers_ARLOCK;\n  wire [2:0]m01_regslice_to_m01_couplers_ARPROT;\n  wire [3:0]m01_regslice_to_m01_couplers_ARQOS;\n  wire m01_regslice_to_m01_couplers_ARREADY;\n  wire [3:0]m01_regslice_to_m01_couplers_ARREGION;\n  wire [2:0]m01_regslice_to_m01_couplers_ARSIZE;\n  wire m01_regslice_to_m01_couplers_ARVALID;\n  wire [63:0]m01_regslice_to_m01_couplers_AWADDR;\n  wire [1:0]m01_regslice_to_m01_couplers_AWBURST;\n  wire [3:0]m01_regslice_to_m01_couplers_AWCACHE;\n  wire [6:0]m01_regslice_to_m01_couplers_AWID;\n  wire [7:0]m01_regslice_to_m01_couplers_AWLEN;\n  wire [0:0]m01_regslice_to_m01_couplers_AWLOCK;\n  wire [2:0]m01_regslice_to_m01_couplers_AWPROT;\n  wire [3:0]m01_regslice_to_m01_couplers_AWQOS;\n  wire m01_regslice_to_m01_couplers_AWREADY;\n  wire [3:0]m01_regslice_to_m01_couplers_AWREGION;\n  wire [2:0]m01_regslice_to_m01_couplers_AWSIZE;\n  wire m01_regslice_to_m01_couplers_AWVALID;\n  wire [6:0]m01_regslice_to_m01_couplers_BID;\n  wire m01_regslice_to_m01_couplers_BREADY;\n  wire [1:0]m01_regslice_to_m01_couplers_BRESP;\n  wire m01_regslice_to_m01_couplers_BVALID;\n  wire [511:0]m01_regslice_to_m01_couplers_RDATA;\n  wire [6:0]m01_regslice_to_m01_couplers_RID;\n  wire m01_regslice_to_m01_couplers_RLAST;\n  wire m01_regslice_to_m01_couplers_RREADY;\n  wire [1:0]m01_regslice_to_m01_couplers_RRESP;\n  wire m01_regslice_to_m01_couplers_RVALID;\n  wire [511:0]m01_regslice_to_m01_couplers_WDATA;\n  wire m01_regslice_to_m01_couplers_WLAST;\n  wire m01_regslice_to_m01_couplers_WREADY;\n  wire [63:0]m01_regslice_to_m01_couplers_WSTRB;\n  wire m01_regslice_to_m01_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m01_regslice_to_m01_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m01_regslice_to_m01_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m01_regslice_to_m01_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m01_regslice_to_m01_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m01_regslice_to_m01_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m01_regslice_to_m01_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m01_regslice_to_m01_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m01_regslice_to_m01_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m01_regslice_to_m01_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m01_regslice_to_m01_couplers_ARSIZE;\n  assign M_AXI_arvalid = m01_regslice_to_m01_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m01_regslice_to_m01_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m01_regslice_to_m01_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m01_regslice_to_m01_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m01_regslice_to_m01_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m01_regslice_to_m01_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m01_regslice_to_m01_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m01_regslice_to_m01_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m01_regslice_to_m01_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m01_regslice_to_m01_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m01_regslice_to_m01_couplers_AWSIZE;\n  assign M_AXI_awvalid = m01_regslice_to_m01_couplers_AWVALID;\n  assign M_AXI_bready = m01_regslice_to_m01_couplers_BREADY;\n  assign M_AXI_rready = m01_regslice_to_m01_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m01_regslice_to_m01_couplers_WDATA;\n  assign M_AXI_wlast = m01_regslice_to_m01_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m01_regslice_to_m01_couplers_WSTRB;\n  assign M_AXI_wvalid = m01_regslice_to_m01_couplers_WVALID;\n  assign S_AXI_arready = m01_couplers_to_m01_regslice_ARREADY;\n  assign S_AXI_awready = m01_couplers_to_m01_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m01_couplers_to_m01_regslice_BID;\n  assign S_AXI_bresp[1:0] = m01_couplers_to_m01_regslice_BRESP;\n  assign S_AXI_bvalid = m01_couplers_to_m01_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m01_couplers_to_m01_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m01_couplers_to_m01_regslice_RID;\n  assign S_AXI_rlast = m01_couplers_to_m01_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m01_couplers_to_m01_regslice_RRESP;\n  assign S_AXI_rvalid = m01_couplers_to_m01_regslice_RVALID;\n  assign S_AXI_wready = m01_couplers_to_m01_regslice_WREADY;\n  assign m01_couplers_to_m01_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m01_couplers_to_m01_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m01_couplers_to_m01_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m01_couplers_to_m01_regslice_ARID = S_AXI_arid[6:0];\n  assign m01_couplers_to_m01_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m01_couplers_to_m01_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m01_couplers_to_m01_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m01_couplers_to_m01_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m01_couplers_to_m01_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m01_couplers_to_m01_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m01_couplers_to_m01_regslice_ARVALID = S_AXI_arvalid;\n  assign m01_couplers_to_m01_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m01_couplers_to_m01_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m01_couplers_to_m01_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m01_couplers_to_m01_regslice_AWID = S_AXI_awid[6:0];\n  assign m01_couplers_to_m01_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m01_couplers_to_m01_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m01_couplers_to_m01_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m01_couplers_to_m01_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m01_couplers_to_m01_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m01_couplers_to_m01_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m01_couplers_to_m01_regslice_AWVALID = S_AXI_awvalid;\n  assign m01_couplers_to_m01_regslice_BREADY = S_AXI_bready;\n  assign m01_couplers_to_m01_regslice_RREADY = S_AXI_rready;\n  assign m01_couplers_to_m01_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m01_couplers_to_m01_regslice_WLAST = S_AXI_wlast;\n  assign m01_couplers_to_m01_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m01_couplers_to_m01_regslice_WVALID = S_AXI_wvalid;\n  assign m01_regslice_to_m01_couplers_ARREADY = M_AXI_arready;\n  assign m01_regslice_to_m01_couplers_AWREADY = M_AXI_awready;\n  assign m01_regslice_to_m01_couplers_BID = M_AXI_bid[6:0];\n  assign m01_regslice_to_m01_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m01_regslice_to_m01_couplers_BVALID = M_AXI_bvalid;\n  assign m01_regslice_to_m01_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m01_regslice_to_m01_couplers_RID = M_AXI_rid[6:0];\n  assign m01_regslice_to_m01_couplers_RLAST = M_AXI_rlast;\n  assign m01_regslice_to_m01_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m01_regslice_to_m01_couplers_RVALID = M_AXI_rvalid;\n  assign m01_regslice_to_m01_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m01_regslice_0 m01_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m01_regslice_to_m01_couplers_ARADDR),\n        .m_axi_arburst(m01_regslice_to_m01_couplers_ARBURST),\n        .m_axi_arcache(m01_regslice_to_m01_couplers_ARCACHE),\n        .m_axi_arid(m01_regslice_to_m01_couplers_ARID),\n        .m_axi_arlen(m01_regslice_to_m01_couplers_ARLEN),\n        .m_axi_arlock(m01_regslice_to_m01_couplers_ARLOCK),\n        .m_axi_arprot(m01_regslice_to_m01_couplers_ARPROT),\n        .m_axi_arqos(m01_regslice_to_m01_couplers_ARQOS),\n        .m_axi_arready(m01_regslice_to_m01_couplers_ARREADY),\n        .m_axi_arregion(m01_regslice_to_m01_couplers_ARREGION),\n        .m_axi_arsize(m01_regslice_to_m01_couplers_ARSIZE),\n        .m_axi_arvalid(m01_regslice_to_m01_couplers_ARVALID),\n        .m_axi_awaddr(m01_regslice_to_m01_couplers_AWADDR),\n        .m_axi_awburst(m01_regslice_to_m01_couplers_AWBURST),\n        .m_axi_awcache(m01_regslice_to_m01_couplers_AWCACHE),\n        .m_axi_awid(m01_regslice_to_m01_couplers_AWID),\n        .m_axi_awlen(m01_regslice_to_m01_couplers_AWLEN),\n        .m_axi_awlock(m01_regslice_to_m01_couplers_AWLOCK),\n        .m_axi_awprot(m01_regslice_to_m01_couplers_AWPROT),\n        .m_axi_awqos(m01_regslice_to_m01_couplers_AWQOS),\n        .m_axi_awready(m01_regslice_to_m01_couplers_AWREADY),\n        .m_axi_awregion(m01_regslice_to_m01_couplers_AWREGION),\n        .m_axi_awsize(m01_regslice_to_m01_couplers_AWSIZE),\n        .m_axi_awvalid(m01_regslice_to_m01_couplers_AWVALID),\n        .m_axi_bid(m01_regslice_to_m01_couplers_BID),\n        .m_axi_bready(m01_regslice_to_m01_couplers_BREADY),\n        .m_axi_bresp(m01_regslice_to_m01_couplers_BRESP),\n        .m_axi_bvalid(m01_regslice_to_m01_couplers_BVALID),\n        .m_axi_rdata(m01_regslice_to_m01_couplers_RDATA),\n        .m_axi_rid(m01_regslice_to_m01_couplers_RID),\n        .m_axi_rlast(m01_regslice_to_m01_couplers_RLAST),\n        .m_axi_rready(m01_regslice_to_m01_couplers_RREADY),\n        .m_axi_rresp(m01_regslice_to_m01_couplers_RRESP),\n        .m_axi_rvalid(m01_regslice_to_m01_couplers_RVALID),\n        .m_axi_wdata(m01_regslice_to_m01_couplers_WDATA),\n        .m_axi_wlast(m01_regslice_to_m01_couplers_WLAST),\n        .m_axi_wready(m01_regslice_to_m01_couplers_WREADY),\n        .m_axi_wstrb(m01_regslice_to_m01_couplers_WSTRB),\n        .m_axi_wvalid(m01_regslice_to_m01_couplers_WVALID),\n        .s_axi_araddr(m01_couplers_to_m01_regslice_ARADDR),\n        .s_axi_arburst(m01_couplers_to_m01_regslice_ARBURST),\n        .s_axi_arcache(m01_couplers_to_m01_regslice_ARCACHE),\n        .s_axi_arid(m01_couplers_to_m01_regslice_ARID),\n        .s_axi_arlen(m01_couplers_to_m01_regslice_ARLEN),\n        .s_axi_arlock(m01_couplers_to_m01_regslice_ARLOCK),\n        .s_axi_arprot(m01_couplers_to_m01_regslice_ARPROT),\n        .s_axi_arqos(m01_couplers_to_m01_regslice_ARQOS),\n        .s_axi_arready(m01_couplers_to_m01_regslice_ARREADY),\n        .s_axi_arregion(m01_couplers_to_m01_regslice_ARREGION),\n        .s_axi_arsize(m01_couplers_to_m01_regslice_ARSIZE),\n        .s_axi_arvalid(m01_couplers_to_m01_regslice_ARVALID),\n        .s_axi_awaddr(m01_couplers_to_m01_regslice_AWADDR),\n        .s_axi_awburst(m01_couplers_to_m01_regslice_AWBURST),\n        .s_axi_awcache(m01_couplers_to_m01_regslice_AWCACHE),\n        .s_axi_awid(m01_couplers_to_m01_regslice_AWID),\n        .s_axi_awlen(m01_couplers_to_m01_regslice_AWLEN),\n        .s_axi_awlock(m01_couplers_to_m01_regslice_AWLOCK),\n        .s_axi_awprot(m01_couplers_to_m01_regslice_AWPROT),\n        .s_axi_awqos(m01_couplers_to_m01_regslice_AWQOS),\n        .s_axi_awready(m01_couplers_to_m01_regslice_AWREADY),\n        .s_axi_awregion(m01_couplers_to_m01_regslice_AWREGION),\n        .s_axi_awsize(m01_couplers_to_m01_regslice_AWSIZE),\n        .s_axi_awvalid(m01_couplers_to_m01_regslice_AWVALID),\n        .s_axi_bid(m01_couplers_to_m01_regslice_BID),\n        .s_axi_bready(m01_couplers_to_m01_regslice_BREADY),\n        .s_axi_bresp(m01_couplers_to_m01_regslice_BRESP),\n        .s_axi_bvalid(m01_couplers_to_m01_regslice_BVALID),\n        .s_axi_rdata(m01_couplers_to_m01_regslice_RDATA),\n        .s_axi_rid(m01_couplers_to_m01_regslice_RID),\n        .s_axi_rlast(m01_couplers_to_m01_regslice_RLAST),\n        .s_axi_rready(m01_couplers_to_m01_regslice_RREADY),\n        .s_axi_rresp(m01_couplers_to_m01_regslice_RRESP),\n        .s_axi_rvalid(m01_couplers_to_m01_regslice_RVALID),\n        .s_axi_wdata(m01_couplers_to_m01_regslice_WDATA),\n        .s_axi_wlast(m01_couplers_to_m01_regslice_WLAST),\n        .s_axi_wready(m01_couplers_to_m01_regslice_WREADY),\n        .s_axi_wstrb(m01_couplers_to_m01_regslice_WSTRB),\n        .s_axi_wvalid(m01_couplers_to_m01_regslice_WVALID));\nendmodule\n\nmodule m02_couplers_imp_APDUS2\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m02_couplers_to_m02_regslice_ARADDR;\n  wire [1:0]m02_couplers_to_m02_regslice_ARBURST;\n  wire [3:0]m02_couplers_to_m02_regslice_ARCACHE;\n  wire [6:0]m02_couplers_to_m02_regslice_ARID;\n  wire [7:0]m02_couplers_to_m02_regslice_ARLEN;\n  wire [0:0]m02_couplers_to_m02_regslice_ARLOCK;\n  wire [2:0]m02_couplers_to_m02_regslice_ARPROT;\n  wire [3:0]m02_couplers_to_m02_regslice_ARQOS;\n  wire m02_couplers_to_m02_regslice_ARREADY;\n  wire [3:0]m02_couplers_to_m02_regslice_ARREGION;\n  wire [2:0]m02_couplers_to_m02_regslice_ARSIZE;\n  wire m02_couplers_to_m02_regslice_ARVALID;\n  wire [63:0]m02_couplers_to_m02_regslice_AWADDR;\n  wire [1:0]m02_couplers_to_m02_regslice_AWBURST;\n  wire [3:0]m02_couplers_to_m02_regslice_AWCACHE;\n  wire [6:0]m02_couplers_to_m02_regslice_AWID;\n  wire [7:0]m02_couplers_to_m02_regslice_AWLEN;\n  wire [0:0]m02_couplers_to_m02_regslice_AWLOCK;\n  wire [2:0]m02_couplers_to_m02_regslice_AWPROT;\n  wire [3:0]m02_couplers_to_m02_regslice_AWQOS;\n  wire m02_couplers_to_m02_regslice_AWREADY;\n  wire [3:0]m02_couplers_to_m02_regslice_AWREGION;\n  wire [2:0]m02_couplers_to_m02_regslice_AWSIZE;\n  wire m02_couplers_to_m02_regslice_AWVALID;\n  wire [6:0]m02_couplers_to_m02_regslice_BID;\n  wire m02_couplers_to_m02_regslice_BREADY;\n  wire [1:0]m02_couplers_to_m02_regslice_BRESP;\n  wire m02_couplers_to_m02_regslice_BVALID;\n  wire [511:0]m02_couplers_to_m02_regslice_RDATA;\n  wire [6:0]m02_couplers_to_m02_regslice_RID;\n  wire m02_couplers_to_m02_regslice_RLAST;\n  wire m02_couplers_to_m02_regslice_RREADY;\n  wire [1:0]m02_couplers_to_m02_regslice_RRESP;\n  wire m02_couplers_to_m02_regslice_RVALID;\n  wire [511:0]m02_couplers_to_m02_regslice_WDATA;\n  wire m02_couplers_to_m02_regslice_WLAST;\n  wire m02_couplers_to_m02_regslice_WREADY;\n  wire [63:0]m02_couplers_to_m02_regslice_WSTRB;\n  wire m02_couplers_to_m02_regslice_WVALID;\n  wire [63:0]m02_regslice_to_m02_couplers_ARADDR;\n  wire [1:0]m02_regslice_to_m02_couplers_ARBURST;\n  wire [3:0]m02_regslice_to_m02_couplers_ARCACHE;\n  wire [6:0]m02_regslice_to_m02_couplers_ARID;\n  wire [7:0]m02_regslice_to_m02_couplers_ARLEN;\n  wire [0:0]m02_regslice_to_m02_couplers_ARLOCK;\n  wire [2:0]m02_regslice_to_m02_couplers_ARPROT;\n  wire [3:0]m02_regslice_to_m02_couplers_ARQOS;\n  wire m02_regslice_to_m02_couplers_ARREADY;\n  wire [3:0]m02_regslice_to_m02_couplers_ARREGION;\n  wire [2:0]m02_regslice_to_m02_couplers_ARSIZE;\n  wire m02_regslice_to_m02_couplers_ARVALID;\n  wire [63:0]m02_regslice_to_m02_couplers_AWADDR;\n  wire [1:0]m02_regslice_to_m02_couplers_AWBURST;\n  wire [3:0]m02_regslice_to_m02_couplers_AWCACHE;\n  wire [6:0]m02_regslice_to_m02_couplers_AWID;\n  wire [7:0]m02_regslice_to_m02_couplers_AWLEN;\n  wire [0:0]m02_regslice_to_m02_couplers_AWLOCK;\n  wire [2:0]m02_regslice_to_m02_couplers_AWPROT;\n  wire [3:0]m02_regslice_to_m02_couplers_AWQOS;\n  wire m02_regslice_to_m02_couplers_AWREADY;\n  wire [3:0]m02_regslice_to_m02_couplers_AWREGION;\n  wire [2:0]m02_regslice_to_m02_couplers_AWSIZE;\n  wire m02_regslice_to_m02_couplers_AWVALID;\n  wire [6:0]m02_regslice_to_m02_couplers_BID;\n  wire m02_regslice_to_m02_couplers_BREADY;\n  wire [1:0]m02_regslice_to_m02_couplers_BRESP;\n  wire m02_regslice_to_m02_couplers_BVALID;\n  wire [511:0]m02_regslice_to_m02_couplers_RDATA;\n  wire [6:0]m02_regslice_to_m02_couplers_RID;\n  wire m02_regslice_to_m02_couplers_RLAST;\n  wire m02_regslice_to_m02_couplers_RREADY;\n  wire [1:0]m02_regslice_to_m02_couplers_RRESP;\n  wire m02_regslice_to_m02_couplers_RVALID;\n  wire [511:0]m02_regslice_to_m02_couplers_WDATA;\n  wire m02_regslice_to_m02_couplers_WLAST;\n  wire m02_regslice_to_m02_couplers_WREADY;\n  wire [63:0]m02_regslice_to_m02_couplers_WSTRB;\n  wire m02_regslice_to_m02_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m02_regslice_to_m02_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m02_regslice_to_m02_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m02_regslice_to_m02_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m02_regslice_to_m02_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m02_regslice_to_m02_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m02_regslice_to_m02_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m02_regslice_to_m02_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m02_regslice_to_m02_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m02_regslice_to_m02_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m02_regslice_to_m02_couplers_ARSIZE;\n  assign M_AXI_arvalid = m02_regslice_to_m02_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m02_regslice_to_m02_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m02_regslice_to_m02_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m02_regslice_to_m02_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m02_regslice_to_m02_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m02_regslice_to_m02_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m02_regslice_to_m02_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m02_regslice_to_m02_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m02_regslice_to_m02_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m02_regslice_to_m02_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m02_regslice_to_m02_couplers_AWSIZE;\n  assign M_AXI_awvalid = m02_regslice_to_m02_couplers_AWVALID;\n  assign M_AXI_bready = m02_regslice_to_m02_couplers_BREADY;\n  assign M_AXI_rready = m02_regslice_to_m02_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m02_regslice_to_m02_couplers_WDATA;\n  assign M_AXI_wlast = m02_regslice_to_m02_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m02_regslice_to_m02_couplers_WSTRB;\n  assign M_AXI_wvalid = m02_regslice_to_m02_couplers_WVALID;\n  assign S_AXI_arready = m02_couplers_to_m02_regslice_ARREADY;\n  assign S_AXI_awready = m02_couplers_to_m02_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m02_couplers_to_m02_regslice_BID;\n  assign S_AXI_bresp[1:0] = m02_couplers_to_m02_regslice_BRESP;\n  assign S_AXI_bvalid = m02_couplers_to_m02_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m02_couplers_to_m02_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m02_couplers_to_m02_regslice_RID;\n  assign S_AXI_rlast = m02_couplers_to_m02_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m02_couplers_to_m02_regslice_RRESP;\n  assign S_AXI_rvalid = m02_couplers_to_m02_regslice_RVALID;\n  assign S_AXI_wready = m02_couplers_to_m02_regslice_WREADY;\n  assign m02_couplers_to_m02_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m02_couplers_to_m02_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m02_couplers_to_m02_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m02_couplers_to_m02_regslice_ARID = S_AXI_arid[6:0];\n  assign m02_couplers_to_m02_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m02_couplers_to_m02_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m02_couplers_to_m02_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m02_couplers_to_m02_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m02_couplers_to_m02_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m02_couplers_to_m02_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m02_couplers_to_m02_regslice_ARVALID = S_AXI_arvalid;\n  assign m02_couplers_to_m02_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m02_couplers_to_m02_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m02_couplers_to_m02_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m02_couplers_to_m02_regslice_AWID = S_AXI_awid[6:0];\n  assign m02_couplers_to_m02_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m02_couplers_to_m02_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m02_couplers_to_m02_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m02_couplers_to_m02_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m02_couplers_to_m02_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m02_couplers_to_m02_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m02_couplers_to_m02_regslice_AWVALID = S_AXI_awvalid;\n  assign m02_couplers_to_m02_regslice_BREADY = S_AXI_bready;\n  assign m02_couplers_to_m02_regslice_RREADY = S_AXI_rready;\n  assign m02_couplers_to_m02_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m02_couplers_to_m02_regslice_WLAST = S_AXI_wlast;\n  assign m02_couplers_to_m02_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m02_couplers_to_m02_regslice_WVALID = S_AXI_wvalid;\n  assign m02_regslice_to_m02_couplers_ARREADY = M_AXI_arready;\n  assign m02_regslice_to_m02_couplers_AWREADY = M_AXI_awready;\n  assign m02_regslice_to_m02_couplers_BID = M_AXI_bid[6:0];\n  assign m02_regslice_to_m02_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m02_regslice_to_m02_couplers_BVALID = M_AXI_bvalid;\n  assign m02_regslice_to_m02_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m02_regslice_to_m02_couplers_RID = M_AXI_rid[6:0];\n  assign m02_regslice_to_m02_couplers_RLAST = M_AXI_rlast;\n  assign m02_regslice_to_m02_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m02_regslice_to_m02_couplers_RVALID = M_AXI_rvalid;\n  assign m02_regslice_to_m02_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m02_regslice_0 m02_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m02_regslice_to_m02_couplers_ARADDR),\n        .m_axi_arburst(m02_regslice_to_m02_couplers_ARBURST),\n        .m_axi_arcache(m02_regslice_to_m02_couplers_ARCACHE),\n        .m_axi_arid(m02_regslice_to_m02_couplers_ARID),\n        .m_axi_arlen(m02_regslice_to_m02_couplers_ARLEN),\n        .m_axi_arlock(m02_regslice_to_m02_couplers_ARLOCK),\n        .m_axi_arprot(m02_regslice_to_m02_couplers_ARPROT),\n        .m_axi_arqos(m02_regslice_to_m02_couplers_ARQOS),\n        .m_axi_arready(m02_regslice_to_m02_couplers_ARREADY),\n        .m_axi_arregion(m02_regslice_to_m02_couplers_ARREGION),\n        .m_axi_arsize(m02_regslice_to_m02_couplers_ARSIZE),\n        .m_axi_arvalid(m02_regslice_to_m02_couplers_ARVALID),\n        .m_axi_awaddr(m02_regslice_to_m02_couplers_AWADDR),\n        .m_axi_awburst(m02_regslice_to_m02_couplers_AWBURST),\n        .m_axi_awcache(m02_regslice_to_m02_couplers_AWCACHE),\n        .m_axi_awid(m02_regslice_to_m02_couplers_AWID),\n        .m_axi_awlen(m02_regslice_to_m02_couplers_AWLEN),\n        .m_axi_awlock(m02_regslice_to_m02_couplers_AWLOCK),\n        .m_axi_awprot(m02_regslice_to_m02_couplers_AWPROT),\n        .m_axi_awqos(m02_regslice_to_m02_couplers_AWQOS),\n        .m_axi_awready(m02_regslice_to_m02_couplers_AWREADY),\n        .m_axi_awregion(m02_regslice_to_m02_couplers_AWREGION),\n        .m_axi_awsize(m02_regslice_to_m02_couplers_AWSIZE),\n        .m_axi_awvalid(m02_regslice_to_m02_couplers_AWVALID),\n        .m_axi_bid(m02_regslice_to_m02_couplers_BID),\n        .m_axi_bready(m02_regslice_to_m02_couplers_BREADY),\n        .m_axi_bresp(m02_regslice_to_m02_couplers_BRESP),\n        .m_axi_bvalid(m02_regslice_to_m02_couplers_BVALID),\n        .m_axi_rdata(m02_regslice_to_m02_couplers_RDATA),\n        .m_axi_rid(m02_regslice_to_m02_couplers_RID),\n        .m_axi_rlast(m02_regslice_to_m02_couplers_RLAST),\n        .m_axi_rready(m02_regslice_to_m02_couplers_RREADY),\n        .m_axi_rresp(m02_regslice_to_m02_couplers_RRESP),\n        .m_axi_rvalid(m02_regslice_to_m02_couplers_RVALID),\n        .m_axi_wdata(m02_regslice_to_m02_couplers_WDATA),\n        .m_axi_wlast(m02_regslice_to_m02_couplers_WLAST),\n        .m_axi_wready(m02_regslice_to_m02_couplers_WREADY),\n        .m_axi_wstrb(m02_regslice_to_m02_couplers_WSTRB),\n        .m_axi_wvalid(m02_regslice_to_m02_couplers_WVALID),\n        .s_axi_araddr(m02_couplers_to_m02_regslice_ARADDR),\n        .s_axi_arburst(m02_couplers_to_m02_regslice_ARBURST),\n        .s_axi_arcache(m02_couplers_to_m02_regslice_ARCACHE),\n        .s_axi_arid(m02_couplers_to_m02_regslice_ARID),\n        .s_axi_arlen(m02_couplers_to_m02_regslice_ARLEN),\n        .s_axi_arlock(m02_couplers_to_m02_regslice_ARLOCK),\n        .s_axi_arprot(m02_couplers_to_m02_regslice_ARPROT),\n        .s_axi_arqos(m02_couplers_to_m02_regslice_ARQOS),\n        .s_axi_arready(m02_couplers_to_m02_regslice_ARREADY),\n        .s_axi_arregion(m02_couplers_to_m02_regslice_ARREGION),\n        .s_axi_arsize(m02_couplers_to_m02_regslice_ARSIZE),\n        .s_axi_arvalid(m02_couplers_to_m02_regslice_ARVALID),\n        .s_axi_awaddr(m02_couplers_to_m02_regslice_AWADDR),\n        .s_axi_awburst(m02_couplers_to_m02_regslice_AWBURST),\n        .s_axi_awcache(m02_couplers_to_m02_regslice_AWCACHE),\n        .s_axi_awid(m02_couplers_to_m02_regslice_AWID),\n        .s_axi_awlen(m02_couplers_to_m02_regslice_AWLEN),\n        .s_axi_awlock(m02_couplers_to_m02_regslice_AWLOCK),\n        .s_axi_awprot(m02_couplers_to_m02_regslice_AWPROT),\n        .s_axi_awqos(m02_couplers_to_m02_regslice_AWQOS),\n        .s_axi_awready(m02_couplers_to_m02_regslice_AWREADY),\n        .s_axi_awregion(m02_couplers_to_m02_regslice_AWREGION),\n        .s_axi_awsize(m02_couplers_to_m02_regslice_AWSIZE),\n        .s_axi_awvalid(m02_couplers_to_m02_regslice_AWVALID),\n        .s_axi_bid(m02_couplers_to_m02_regslice_BID),\n        .s_axi_bready(m02_couplers_to_m02_regslice_BREADY),\n        .s_axi_bresp(m02_couplers_to_m02_regslice_BRESP),\n        .s_axi_bvalid(m02_couplers_to_m02_regslice_BVALID),\n        .s_axi_rdata(m02_couplers_to_m02_regslice_RDATA),\n        .s_axi_rid(m02_couplers_to_m02_regslice_RID),\n        .s_axi_rlast(m02_couplers_to_m02_regslice_RLAST),\n        .s_axi_rready(m02_couplers_to_m02_regslice_RREADY),\n        .s_axi_rresp(m02_couplers_to_m02_regslice_RRESP),\n        .s_axi_rvalid(m02_couplers_to_m02_regslice_RVALID),\n        .s_axi_wdata(m02_couplers_to_m02_regslice_WDATA),\n        .s_axi_wlast(m02_couplers_to_m02_regslice_WLAST),\n        .s_axi_wready(m02_couplers_to_m02_regslice_WREADY),\n        .s_axi_wstrb(m02_couplers_to_m02_regslice_WSTRB),\n        .s_axi_wvalid(m02_couplers_to_m02_regslice_WVALID));\nendmodule\n\nmodule m03_couplers_imp_JAYOMU\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m03_couplers_to_m03_regslice_ARADDR;\n  wire [1:0]m03_couplers_to_m03_regslice_ARBURST;\n  wire [3:0]m03_couplers_to_m03_regslice_ARCACHE;\n  wire [6:0]m03_couplers_to_m03_regslice_ARID;\n  wire [7:0]m03_couplers_to_m03_regslice_ARLEN;\n  wire [0:0]m03_couplers_to_m03_regslice_ARLOCK;\n  wire [2:0]m03_couplers_to_m03_regslice_ARPROT;\n  wire [3:0]m03_couplers_to_m03_regslice_ARQOS;\n  wire m03_couplers_to_m03_regslice_ARREADY;\n  wire [3:0]m03_couplers_to_m03_regslice_ARREGION;\n  wire [2:0]m03_couplers_to_m03_regslice_ARSIZE;\n  wire m03_couplers_to_m03_regslice_ARVALID;\n  wire [63:0]m03_couplers_to_m03_regslice_AWADDR;\n  wire [1:0]m03_couplers_to_m03_regslice_AWBURST;\n  wire [3:0]m03_couplers_to_m03_regslice_AWCACHE;\n  wire [6:0]m03_couplers_to_m03_regslice_AWID;\n  wire [7:0]m03_couplers_to_m03_regslice_AWLEN;\n  wire [0:0]m03_couplers_to_m03_regslice_AWLOCK;\n  wire [2:0]m03_couplers_to_m03_regslice_AWPROT;\n  wire [3:0]m03_couplers_to_m03_regslice_AWQOS;\n  wire m03_couplers_to_m03_regslice_AWREADY;\n  wire [3:0]m03_couplers_to_m03_regslice_AWREGION;\n  wire [2:0]m03_couplers_to_m03_regslice_AWSIZE;\n  wire m03_couplers_to_m03_regslice_AWVALID;\n  wire [6:0]m03_couplers_to_m03_regslice_BID;\n  wire m03_couplers_to_m03_regslice_BREADY;\n  wire [1:0]m03_couplers_to_m03_regslice_BRESP;\n  wire m03_couplers_to_m03_regslice_BVALID;\n  wire [511:0]m03_couplers_to_m03_regslice_RDATA;\n  wire [6:0]m03_couplers_to_m03_regslice_RID;\n  wire m03_couplers_to_m03_regslice_RLAST;\n  wire m03_couplers_to_m03_regslice_RREADY;\n  wire [1:0]m03_couplers_to_m03_regslice_RRESP;\n  wire m03_couplers_to_m03_regslice_RVALID;\n  wire [511:0]m03_couplers_to_m03_regslice_WDATA;\n  wire m03_couplers_to_m03_regslice_WLAST;\n  wire m03_couplers_to_m03_regslice_WREADY;\n  wire [63:0]m03_couplers_to_m03_regslice_WSTRB;\n  wire m03_couplers_to_m03_regslice_WVALID;\n  wire [63:0]m03_regslice_to_m03_couplers_ARADDR;\n  wire [1:0]m03_regslice_to_m03_couplers_ARBURST;\n  wire [3:0]m03_regslice_to_m03_couplers_ARCACHE;\n  wire [6:0]m03_regslice_to_m03_couplers_ARID;\n  wire [7:0]m03_regslice_to_m03_couplers_ARLEN;\n  wire [0:0]m03_regslice_to_m03_couplers_ARLOCK;\n  wire [2:0]m03_regslice_to_m03_couplers_ARPROT;\n  wire [3:0]m03_regslice_to_m03_couplers_ARQOS;\n  wire m03_regslice_to_m03_couplers_ARREADY;\n  wire [3:0]m03_regslice_to_m03_couplers_ARREGION;\n  wire [2:0]m03_regslice_to_m03_couplers_ARSIZE;\n  wire m03_regslice_to_m03_couplers_ARVALID;\n  wire [63:0]m03_regslice_to_m03_couplers_AWADDR;\n  wire [1:0]m03_regslice_to_m03_couplers_AWBURST;\n  wire [3:0]m03_regslice_to_m03_couplers_AWCACHE;\n  wire [6:0]m03_regslice_to_m03_couplers_AWID;\n  wire [7:0]m03_regslice_to_m03_couplers_AWLEN;\n  wire [0:0]m03_regslice_to_m03_couplers_AWLOCK;\n  wire [2:0]m03_regslice_to_m03_couplers_AWPROT;\n  wire [3:0]m03_regslice_to_m03_couplers_AWQOS;\n  wire m03_regslice_to_m03_couplers_AWREADY;\n  wire [3:0]m03_regslice_to_m03_couplers_AWREGION;\n  wire [2:0]m03_regslice_to_m03_couplers_AWSIZE;\n  wire m03_regslice_to_m03_couplers_AWVALID;\n  wire [6:0]m03_regslice_to_m03_couplers_BID;\n  wire m03_regslice_to_m03_couplers_BREADY;\n  wire [1:0]m03_regslice_to_m03_couplers_BRESP;\n  wire m03_regslice_to_m03_couplers_BVALID;\n  wire [511:0]m03_regslice_to_m03_couplers_RDATA;\n  wire [6:0]m03_regslice_to_m03_couplers_RID;\n  wire m03_regslice_to_m03_couplers_RLAST;\n  wire m03_regslice_to_m03_couplers_RREADY;\n  wire [1:0]m03_regslice_to_m03_couplers_RRESP;\n  wire m03_regslice_to_m03_couplers_RVALID;\n  wire [511:0]m03_regslice_to_m03_couplers_WDATA;\n  wire m03_regslice_to_m03_couplers_WLAST;\n  wire m03_regslice_to_m03_couplers_WREADY;\n  wire [63:0]m03_regslice_to_m03_couplers_WSTRB;\n  wire m03_regslice_to_m03_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m03_regslice_to_m03_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m03_regslice_to_m03_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m03_regslice_to_m03_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m03_regslice_to_m03_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m03_regslice_to_m03_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m03_regslice_to_m03_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m03_regslice_to_m03_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m03_regslice_to_m03_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m03_regslice_to_m03_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m03_regslice_to_m03_couplers_ARSIZE;\n  assign M_AXI_arvalid = m03_regslice_to_m03_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m03_regslice_to_m03_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m03_regslice_to_m03_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m03_regslice_to_m03_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m03_regslice_to_m03_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m03_regslice_to_m03_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m03_regslice_to_m03_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m03_regslice_to_m03_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m03_regslice_to_m03_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m03_regslice_to_m03_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m03_regslice_to_m03_couplers_AWSIZE;\n  assign M_AXI_awvalid = m03_regslice_to_m03_couplers_AWVALID;\n  assign M_AXI_bready = m03_regslice_to_m03_couplers_BREADY;\n  assign M_AXI_rready = m03_regslice_to_m03_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m03_regslice_to_m03_couplers_WDATA;\n  assign M_AXI_wlast = m03_regslice_to_m03_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m03_regslice_to_m03_couplers_WSTRB;\n  assign M_AXI_wvalid = m03_regslice_to_m03_couplers_WVALID;\n  assign S_AXI_arready = m03_couplers_to_m03_regslice_ARREADY;\n  assign S_AXI_awready = m03_couplers_to_m03_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m03_couplers_to_m03_regslice_BID;\n  assign S_AXI_bresp[1:0] = m03_couplers_to_m03_regslice_BRESP;\n  assign S_AXI_bvalid = m03_couplers_to_m03_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m03_couplers_to_m03_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m03_couplers_to_m03_regslice_RID;\n  assign S_AXI_rlast = m03_couplers_to_m03_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m03_couplers_to_m03_regslice_RRESP;\n  assign S_AXI_rvalid = m03_couplers_to_m03_regslice_RVALID;\n  assign S_AXI_wready = m03_couplers_to_m03_regslice_WREADY;\n  assign m03_couplers_to_m03_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m03_couplers_to_m03_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m03_couplers_to_m03_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m03_couplers_to_m03_regslice_ARID = S_AXI_arid[6:0];\n  assign m03_couplers_to_m03_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m03_couplers_to_m03_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m03_couplers_to_m03_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m03_couplers_to_m03_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m03_couplers_to_m03_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m03_couplers_to_m03_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m03_couplers_to_m03_regslice_ARVALID = S_AXI_arvalid;\n  assign m03_couplers_to_m03_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m03_couplers_to_m03_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m03_couplers_to_m03_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m03_couplers_to_m03_regslice_AWID = S_AXI_awid[6:0];\n  assign m03_couplers_to_m03_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m03_couplers_to_m03_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m03_couplers_to_m03_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m03_couplers_to_m03_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m03_couplers_to_m03_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m03_couplers_to_m03_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m03_couplers_to_m03_regslice_AWVALID = S_AXI_awvalid;\n  assign m03_couplers_to_m03_regslice_BREADY = S_AXI_bready;\n  assign m03_couplers_to_m03_regslice_RREADY = S_AXI_rready;\n  assign m03_couplers_to_m03_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m03_couplers_to_m03_regslice_WLAST = S_AXI_wlast;\n  assign m03_couplers_to_m03_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m03_couplers_to_m03_regslice_WVALID = S_AXI_wvalid;\n  assign m03_regslice_to_m03_couplers_ARREADY = M_AXI_arready;\n  assign m03_regslice_to_m03_couplers_AWREADY = M_AXI_awready;\n  assign m03_regslice_to_m03_couplers_BID = M_AXI_bid[6:0];\n  assign m03_regslice_to_m03_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m03_regslice_to_m03_couplers_BVALID = M_AXI_bvalid;\n  assign m03_regslice_to_m03_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m03_regslice_to_m03_couplers_RID = M_AXI_rid[6:0];\n  assign m03_regslice_to_m03_couplers_RLAST = M_AXI_rlast;\n  assign m03_regslice_to_m03_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m03_regslice_to_m03_couplers_RVALID = M_AXI_rvalid;\n  assign m03_regslice_to_m03_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m03_regslice_0 m03_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m03_regslice_to_m03_couplers_ARADDR),\n        .m_axi_arburst(m03_regslice_to_m03_couplers_ARBURST),\n        .m_axi_arcache(m03_regslice_to_m03_couplers_ARCACHE),\n        .m_axi_arid(m03_regslice_to_m03_couplers_ARID),\n        .m_axi_arlen(m03_regslice_to_m03_couplers_ARLEN),\n        .m_axi_arlock(m03_regslice_to_m03_couplers_ARLOCK),\n        .m_axi_arprot(m03_regslice_to_m03_couplers_ARPROT),\n        .m_axi_arqos(m03_regslice_to_m03_couplers_ARQOS),\n        .m_axi_arready(m03_regslice_to_m03_couplers_ARREADY),\n        .m_axi_arregion(m03_regslice_to_m03_couplers_ARREGION),\n        .m_axi_arsize(m03_regslice_to_m03_couplers_ARSIZE),\n        .m_axi_arvalid(m03_regslice_to_m03_couplers_ARVALID),\n        .m_axi_awaddr(m03_regslice_to_m03_couplers_AWADDR),\n        .m_axi_awburst(m03_regslice_to_m03_couplers_AWBURST),\n        .m_axi_awcache(m03_regslice_to_m03_couplers_AWCACHE),\n        .m_axi_awid(m03_regslice_to_m03_couplers_AWID),\n        .m_axi_awlen(m03_regslice_to_m03_couplers_AWLEN),\n        .m_axi_awlock(m03_regslice_to_m03_couplers_AWLOCK),\n        .m_axi_awprot(m03_regslice_to_m03_couplers_AWPROT),\n        .m_axi_awqos(m03_regslice_to_m03_couplers_AWQOS),\n        .m_axi_awready(m03_regslice_to_m03_couplers_AWREADY),\n        .m_axi_awregion(m03_regslice_to_m03_couplers_AWREGION),\n        .m_axi_awsize(m03_regslice_to_m03_couplers_AWSIZE),\n        .m_axi_awvalid(m03_regslice_to_m03_couplers_AWVALID),\n        .m_axi_bid(m03_regslice_to_m03_couplers_BID),\n        .m_axi_bready(m03_regslice_to_m03_couplers_BREADY),\n        .m_axi_bresp(m03_regslice_to_m03_couplers_BRESP),\n        .m_axi_bvalid(m03_regslice_to_m03_couplers_BVALID),\n        .m_axi_rdata(m03_regslice_to_m03_couplers_RDATA),\n        .m_axi_rid(m03_regslice_to_m03_couplers_RID),\n        .m_axi_rlast(m03_regslice_to_m03_couplers_RLAST),\n        .m_axi_rready(m03_regslice_to_m03_couplers_RREADY),\n        .m_axi_rresp(m03_regslice_to_m03_couplers_RRESP),\n        .m_axi_rvalid(m03_regslice_to_m03_couplers_RVALID),\n        .m_axi_wdata(m03_regslice_to_m03_couplers_WDATA),\n        .m_axi_wlast(m03_regslice_to_m03_couplers_WLAST),\n        .m_axi_wready(m03_regslice_to_m03_couplers_WREADY),\n        .m_axi_wstrb(m03_regslice_to_m03_couplers_WSTRB),\n        .m_axi_wvalid(m03_regslice_to_m03_couplers_WVALID),\n        .s_axi_araddr(m03_couplers_to_m03_regslice_ARADDR),\n        .s_axi_arburst(m03_couplers_to_m03_regslice_ARBURST),\n        .s_axi_arcache(m03_couplers_to_m03_regslice_ARCACHE),\n        .s_axi_arid(m03_couplers_to_m03_regslice_ARID),\n        .s_axi_arlen(m03_couplers_to_m03_regslice_ARLEN),\n        .s_axi_arlock(m03_couplers_to_m03_regslice_ARLOCK),\n        .s_axi_arprot(m03_couplers_to_m03_regslice_ARPROT),\n        .s_axi_arqos(m03_couplers_to_m03_regslice_ARQOS),\n        .s_axi_arready(m03_couplers_to_m03_regslice_ARREADY),\n        .s_axi_arregion(m03_couplers_to_m03_regslice_ARREGION),\n        .s_axi_arsize(m03_couplers_to_m03_regslice_ARSIZE),\n        .s_axi_arvalid(m03_couplers_to_m03_regslice_ARVALID),\n        .s_axi_awaddr(m03_couplers_to_m03_regslice_AWADDR),\n        .s_axi_awburst(m03_couplers_to_m03_regslice_AWBURST),\n        .s_axi_awcache(m03_couplers_to_m03_regslice_AWCACHE),\n        .s_axi_awid(m03_couplers_to_m03_regslice_AWID),\n        .s_axi_awlen(m03_couplers_to_m03_regslice_AWLEN),\n        .s_axi_awlock(m03_couplers_to_m03_regslice_AWLOCK),\n        .s_axi_awprot(m03_couplers_to_m03_regslice_AWPROT),\n        .s_axi_awqos(m03_couplers_to_m03_regslice_AWQOS),\n        .s_axi_awready(m03_couplers_to_m03_regslice_AWREADY),\n        .s_axi_awregion(m03_couplers_to_m03_regslice_AWREGION),\n        .s_axi_awsize(m03_couplers_to_m03_regslice_AWSIZE),\n        .s_axi_awvalid(m03_couplers_to_m03_regslice_AWVALID),\n        .s_axi_bid(m03_couplers_to_m03_regslice_BID),\n        .s_axi_bready(m03_couplers_to_m03_regslice_BREADY),\n        .s_axi_bresp(m03_couplers_to_m03_regslice_BRESP),\n        .s_axi_bvalid(m03_couplers_to_m03_regslice_BVALID),\n        .s_axi_rdata(m03_couplers_to_m03_regslice_RDATA),\n        .s_axi_rid(m03_couplers_to_m03_regslice_RID),\n        .s_axi_rlast(m03_couplers_to_m03_regslice_RLAST),\n        .s_axi_rready(m03_couplers_to_m03_regslice_RREADY),\n        .s_axi_rresp(m03_couplers_to_m03_regslice_RRESP),\n        .s_axi_rvalid(m03_couplers_to_m03_regslice_RVALID),\n        .s_axi_wdata(m03_couplers_to_m03_regslice_WDATA),\n        .s_axi_wlast(m03_couplers_to_m03_regslice_WLAST),\n        .s_axi_wready(m03_couplers_to_m03_regslice_WREADY),\n        .s_axi_wstrb(m03_couplers_to_m03_regslice_WSTRB),\n        .s_axi_wvalid(m03_couplers_to_m03_regslice_WVALID));\nendmodule\n\nmodule s00_couplers_imp_QICM5G\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [5:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [5:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [5:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [5:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [5:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [5:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire S_ACLK_1;\n  wire S_ARESETN_1;\n  wire [63:0]s00_couplers_to_s00_regslice_ARADDR;\n  wire [1:0]s00_couplers_to_s00_regslice_ARBURST;\n  wire [3:0]s00_couplers_to_s00_regslice_ARCACHE;\n  wire [5:0]s00_couplers_to_s00_regslice_ARID;\n  wire [7:0]s00_couplers_to_s00_regslice_ARLEN;\n  wire [0:0]s00_couplers_to_s00_regslice_ARLOCK;\n  wire [2:0]s00_couplers_to_s00_regslice_ARPROT;\n  wire [3:0]s00_couplers_to_s00_regslice_ARQOS;\n  wire s00_couplers_to_s00_regslice_ARREADY;\n  wire [3:0]s00_couplers_to_s00_regslice_ARREGION;\n  wire [2:0]s00_couplers_to_s00_regslice_ARSIZE;\n  wire s00_couplers_to_s00_regslice_ARVALID;\n  wire [63:0]s00_couplers_to_s00_regslice_AWADDR;\n  wire [1:0]s00_couplers_to_s00_regslice_AWBURST;\n  wire [3:0]s00_couplers_to_s00_regslice_AWCACHE;\n  wire [5:0]s00_couplers_to_s00_regslice_AWID;\n  wire [7:0]s00_couplers_to_s00_regslice_AWLEN;\n  wire [0:0]s00_couplers_to_s00_regslice_AWLOCK;\n  wire [2:0]s00_couplers_to_s00_regslice_AWPROT;\n  wire [3:0]s00_couplers_to_s00_regslice_AWQOS;\n  wire s00_couplers_to_s00_regslice_AWREADY;\n  wire [3:0]s00_couplers_to_s00_regslice_AWREGION;\n  wire [2:0]s00_couplers_to_s00_regslice_AWSIZE;\n  wire s00_couplers_to_s00_regslice_AWVALID;\n  wire [5:0]s00_couplers_to_s00_regslice_BID;\n  wire s00_couplers_to_s00_regslice_BREADY;\n  wire [1:0]s00_couplers_to_s00_regslice_BRESP;\n  wire s00_couplers_to_s00_regslice_BVALID;\n  wire [511:0]s00_couplers_to_s00_regslice_RDATA;\n  wire [5:0]s00_couplers_to_s00_regslice_RID;\n  wire s00_couplers_to_s00_regslice_RLAST;\n  wire s00_couplers_to_s00_regslice_RREADY;\n  wire [1:0]s00_couplers_to_s00_regslice_RRESP;\n  wire s00_couplers_to_s00_regslice_RVALID;\n  wire [511:0]s00_couplers_to_s00_regslice_WDATA;\n  wire s00_couplers_to_s00_regslice_WLAST;\n  wire s00_couplers_to_s00_regslice_WREADY;\n  wire [63:0]s00_couplers_to_s00_regslice_WSTRB;\n  wire s00_couplers_to_s00_regslice_WVALID;\n  wire [63:0]s00_regslice_to_s00_couplers_ARADDR;\n  wire [1:0]s00_regslice_to_s00_couplers_ARBURST;\n  wire [3:0]s00_regslice_to_s00_couplers_ARCACHE;\n  wire [5:0]s00_regslice_to_s00_couplers_ARID;\n  wire [7:0]s00_regslice_to_s00_couplers_ARLEN;\n  wire [0:0]s00_regslice_to_s00_couplers_ARLOCK;\n  wire [2:0]s00_regslice_to_s00_couplers_ARPROT;\n  wire [3:0]s00_regslice_to_s00_couplers_ARQOS;\n  wire s00_regslice_to_s00_couplers_ARREADY;\n  wire [2:0]s00_regslice_to_s00_couplers_ARSIZE;\n  wire s00_regslice_to_s00_couplers_ARVALID;\n  wire [63:0]s00_regslice_to_s00_couplers_AWADDR;\n  wire [1:0]s00_regslice_to_s00_couplers_AWBURST;\n  wire [3:0]s00_regslice_to_s00_couplers_AWCACHE;\n  wire [5:0]s00_regslice_to_s00_couplers_AWID;\n  wire [7:0]s00_regslice_to_s00_couplers_AWLEN;\n  wire [0:0]s00_regslice_to_s00_couplers_AWLOCK;\n  wire [2:0]s00_regslice_to_s00_couplers_AWPROT;\n  wire [3:0]s00_regslice_to_s00_couplers_AWQOS;\n  wire s00_regslice_to_s00_couplers_AWREADY;\n  wire [2:0]s00_regslice_to_s00_couplers_AWSIZE;\n  wire s00_regslice_to_s00_couplers_AWVALID;\n  wire [6:0]s00_regslice_to_s00_couplers_BID;\n  wire s00_regslice_to_s00_couplers_BREADY;\n  wire [1:0]s00_regslice_to_s00_couplers_BRESP;\n  wire s00_regslice_to_s00_couplers_BVALID;\n  wire [511:0]s00_regslice_to_s00_couplers_RDATA;\n  wire [6:0]s00_regslice_to_s00_couplers_RID;\n  wire s00_regslice_to_s00_couplers_RLAST;\n  wire s00_regslice_to_s00_couplers_RREADY;\n  wire [1:0]s00_regslice_to_s00_couplers_RRESP;\n  wire s00_regslice_to_s00_couplers_RVALID;\n  wire [511:0]s00_regslice_to_s00_couplers_WDATA;\n  wire s00_regslice_to_s00_couplers_WLAST;\n  wire s00_regslice_to_s00_couplers_WREADY;\n  wire [63:0]s00_regslice_to_s00_couplers_WSTRB;\n  wire s00_regslice_to_s00_couplers_WVALID;\n\n  assign M_AXI_araddr[63:0] = s00_regslice_to_s00_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = s00_regslice_to_s00_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = s00_regslice_to_s00_couplers_ARCACHE;\n  assign M_AXI_arid[5:0] = s00_regslice_to_s00_couplers_ARID;\n  assign M_AXI_arlen[7:0] = s00_regslice_to_s00_couplers_ARLEN;\n  assign M_AXI_arlock[0] = s00_regslice_to_s00_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = s00_regslice_to_s00_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = s00_regslice_to_s00_couplers_ARQOS;\n  assign M_AXI_arsize[2:0] = s00_regslice_to_s00_couplers_ARSIZE;\n  assign M_AXI_arvalid = s00_regslice_to_s00_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = s00_regslice_to_s00_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = s00_regslice_to_s00_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = s00_regslice_to_s00_couplers_AWCACHE;\n  assign M_AXI_awid[5:0] = s00_regslice_to_s00_couplers_AWID;\n  assign M_AXI_awlen[7:0] = s00_regslice_to_s00_couplers_AWLEN;\n  assign M_AXI_awlock[0] = s00_regslice_to_s00_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = s00_regslice_to_s00_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = s00_regslice_to_s00_couplers_AWQOS;\n  assign M_AXI_awsize[2:0] = s00_regslice_to_s00_couplers_AWSIZE;\n  assign M_AXI_awvalid = s00_regslice_to_s00_couplers_AWVALID;\n  assign M_AXI_bready = s00_regslice_to_s00_couplers_BREADY;\n  assign M_AXI_rready = s00_regslice_to_s00_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = s00_regslice_to_s00_couplers_WDATA;\n  assign M_AXI_wlast = s00_regslice_to_s00_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = s00_regslice_to_s00_couplers_WSTRB;\n  assign M_AXI_wvalid = s00_regslice_to_s00_couplers_WVALID;\n  assign S_ACLK_1 = S_ACLK;\n  assign S_ARESETN_1 = S_ARESETN;\n  assign S_AXI_arready = s00_couplers_to_s00_regslice_ARREADY;\n  assign S_AXI_awready = s00_couplers_to_s00_regslice_AWREADY;\n  assign S_AXI_bid[5:0] = s00_couplers_to_s00_regslice_BID;\n  assign S_AXI_bresp[1:0] = s00_couplers_to_s00_regslice_BRESP;\n  assign S_AXI_bvalid = s00_couplers_to_s00_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = s00_couplers_to_s00_regslice_RDATA;\n  assign S_AXI_rid[5:0] = s00_couplers_to_s00_regslice_RID;\n  assign S_AXI_rlast = s00_couplers_to_s00_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = s00_couplers_to_s00_regslice_RRESP;\n  assign S_AXI_rvalid = s00_couplers_to_s00_regslice_RVALID;\n  assign S_AXI_wready = s00_couplers_to_s00_regslice_WREADY;\n  assign s00_couplers_to_s00_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign s00_couplers_to_s00_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign s00_couplers_to_s00_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign s00_couplers_to_s00_regslice_ARID = S_AXI_arid[5:0];\n  assign s00_couplers_to_s00_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign s00_couplers_to_s00_regslice_ARLOCK = S_AXI_arlock[0];\n  assign s00_couplers_to_s00_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign s00_couplers_to_s00_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign s00_couplers_to_s00_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign s00_couplers_to_s00_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign s00_couplers_to_s00_regslice_ARVALID = S_AXI_arvalid;\n  assign s00_couplers_to_s00_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign s00_couplers_to_s00_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign s00_couplers_to_s00_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign s00_couplers_to_s00_regslice_AWID = S_AXI_awid[5:0];\n  assign s00_couplers_to_s00_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign s00_couplers_to_s00_regslice_AWLOCK = S_AXI_awlock[0];\n  assign s00_couplers_to_s00_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign s00_couplers_to_s00_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign s00_couplers_to_s00_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign s00_couplers_to_s00_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign s00_couplers_to_s00_regslice_AWVALID = S_AXI_awvalid;\n  assign s00_couplers_to_s00_regslice_BREADY = S_AXI_bready;\n  assign s00_couplers_to_s00_regslice_RREADY = S_AXI_rready;\n  assign s00_couplers_to_s00_regslice_WDATA = S_AXI_wdata[511:0];\n  assign s00_couplers_to_s00_regslice_WLAST = S_AXI_wlast;\n  assign s00_couplers_to_s00_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign s00_couplers_to_s00_regslice_WVALID = S_AXI_wvalid;\n  assign s00_regslice_to_s00_couplers_ARREADY = M_AXI_arready;\n  assign s00_regslice_to_s00_couplers_AWREADY = M_AXI_awready;\n  assign s00_regslice_to_s00_couplers_BID = M_AXI_bid[6:0];\n  assign s00_regslice_to_s00_couplers_BRESP = M_AXI_bresp[1:0];\n  assign s00_regslice_to_s00_couplers_BVALID = M_AXI_bvalid;\n  assign s00_regslice_to_s00_couplers_RDATA = M_AXI_rdata[511:0];\n  assign s00_regslice_to_s00_couplers_RID = M_AXI_rid[6:0];\n  assign s00_regslice_to_s00_couplers_RLAST = M_AXI_rlast;\n  assign s00_regslice_to_s00_couplers_RRESP = M_AXI_rresp[1:0];\n  assign s00_regslice_to_s00_couplers_RVALID = M_AXI_rvalid;\n  assign s00_regslice_to_s00_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_s00_regslice_0 s00_regslice\n       (.aclk(S_ACLK_1),\n        .aresetn(S_ARESETN_1),\n        .m_axi_araddr(s00_regslice_to_s00_couplers_ARADDR),\n        .m_axi_arburst(s00_regslice_to_s00_couplers_ARBURST),\n        .m_axi_arcache(s00_regslice_to_s00_couplers_ARCACHE),\n        .m_axi_arid(s00_regslice_to_s00_couplers_ARID),\n        .m_axi_arlen(s00_regslice_to_s00_couplers_ARLEN),\n        .m_axi_arlock(s00_regslice_to_s00_couplers_ARLOCK),\n        .m_axi_arprot(s00_regslice_to_s00_couplers_ARPROT),\n        .m_axi_arqos(s00_regslice_to_s00_couplers_ARQOS),\n        .m_axi_arready(s00_regslice_to_s00_couplers_ARREADY),\n        .m_axi_arsize(s00_regslice_to_s00_couplers_ARSIZE),\n        .m_axi_arvalid(s00_regslice_to_s00_couplers_ARVALID),\n        .m_axi_awaddr(s00_regslice_to_s00_couplers_AWADDR),\n        .m_axi_awburst(s00_regslice_to_s00_couplers_AWBURST),\n        .m_axi_awcache(s00_regslice_to_s00_couplers_AWCACHE),\n        .m_axi_awid(s00_regslice_to_s00_couplers_AWID),\n        .m_axi_awlen(s00_regslice_to_s00_couplers_AWLEN),\n        .m_axi_awlock(s00_regslice_to_s00_couplers_AWLOCK),\n        .m_axi_awprot(s00_regslice_to_s00_couplers_AWPROT),\n        .m_axi_awqos(s00_regslice_to_s00_couplers_AWQOS),\n        .m_axi_awready(s00_regslice_to_s00_couplers_AWREADY),\n        .m_axi_awsize(s00_regslice_to_s00_couplers_AWSIZE),\n        .m_axi_awvalid(s00_regslice_to_s00_couplers_AWVALID),\n        .m_axi_bid(s00_regslice_to_s00_couplers_BID[5:0]),\n        .m_axi_bready(s00_regslice_to_s00_couplers_BREADY),\n        .m_axi_bresp(s00_regslice_to_s00_couplers_BRESP),\n        .m_axi_bvalid(s00_regslice_to_s00_couplers_BVALID),\n        .m_axi_rdata(s00_regslice_to_s00_couplers_RDATA),\n        .m_axi_rid(s00_regslice_to_s00_couplers_RID[5:0]),\n        .m_axi_rlast(s00_regslice_to_s00_couplers_RLAST),\n        .m_axi_rready(s00_regslice_to_s00_couplers_RREADY),\n        .m_axi_rresp(s00_regslice_to_s00_couplers_RRESP),\n        .m_axi_rvalid(s00_regslice_to_s00_couplers_RVALID),\n        .m_axi_wdata(s00_regslice_to_s00_couplers_WDATA),\n        .m_axi_wlast(s00_regslice_to_s00_couplers_WLAST),\n        .m_axi_wready(s00_regslice_to_s00_couplers_WREADY),\n        .m_axi_wstrb(s00_regslice_to_s00_couplers_WSTRB),\n        .m_axi_wvalid(s00_regslice_to_s00_couplers_WVALID),\n        .s_axi_araddr(s00_couplers_to_s00_regslice_ARADDR),\n        .s_axi_arburst(s00_couplers_to_s00_regslice_ARBURST),\n        .s_axi_arcache(s00_couplers_to_s00_regslice_ARCACHE),\n        .s_axi_arid(s00_couplers_to_s00_regslice_ARID),\n        .s_axi_arlen(s00_couplers_to_s00_regslice_ARLEN),\n        .s_axi_arlock(s00_couplers_to_s00_regslice_ARLOCK),\n        .s_axi_arprot(s00_couplers_to_s00_regslice_ARPROT),\n        .s_axi_arqos(s00_couplers_to_s00_regslice_ARQOS),\n        .s_axi_arready(s00_couplers_to_s00_regslice_ARREADY),\n        .s_axi_arregion(s00_couplers_to_s00_regslice_ARREGION),\n        .s_axi_arsize(s00_couplers_to_s00_regslice_ARSIZE),\n        .s_axi_arvalid(s00_couplers_to_s00_regslice_ARVALID),\n        .s_axi_awaddr(s00_couplers_to_s00_regslice_AWADDR),\n        .s_axi_awburst(s00_couplers_to_s00_regslice_AWBURST),\n        .s_axi_awcache(s00_couplers_to_s00_regslice_AWCACHE),\n        .s_axi_awid(s00_couplers_to_s00_regslice_AWID),\n        .s_axi_awlen(s00_couplers_to_s00_regslice_AWLEN),\n        .s_axi_awlock(s00_couplers_to_s00_regslice_AWLOCK),\n        .s_axi_awprot(s00_couplers_to_s00_regslice_AWPROT),\n        .s_axi_awqos(s00_couplers_to_s00_regslice_AWQOS),\n        .s_axi_awready(s00_couplers_to_s00_regslice_AWREADY),\n        .s_axi_awregion(s00_couplers_to_s00_regslice_AWREGION),\n        .s_axi_awsize(s00_couplers_to_s00_regslice_AWSIZE),\n        .s_axi_awvalid(s00_couplers_to_s00_regslice_AWVALID),\n        .s_axi_bid(s00_couplers_to_s00_regslice_BID),\n        .s_axi_bready(s00_couplers_to_s00_regslice_BREADY),\n        .s_axi_bresp(s00_couplers_to_s00_regslice_BRESP),\n        .s_axi_bvalid(s00_couplers_to_s00_regslice_BVALID),\n        .s_axi_rdata(s00_couplers_to_s00_regslice_RDATA),\n        .s_axi_rid(s00_couplers_to_s00_regslice_RID),\n        .s_axi_rlast(s00_couplers_to_s00_regslice_RLAST),\n        .s_axi_rready(s00_couplers_to_s00_regslice_RREADY),\n        .s_axi_rresp(s00_couplers_to_s00_regslice_RRESP),\n        .s_axi_rvalid(s00_couplers_to_s00_regslice_RVALID),\n        .s_axi_wdata(s00_couplers_to_s00_regslice_WDATA),\n        .s_axi_wlast(s00_couplers_to_s00_regslice_WLAST),\n        .s_axi_wready(s00_couplers_to_s00_regslice_WREADY),\n        .s_axi_wstrb(s00_couplers_to_s00_regslice_WSTRB),\n        .s_axi_wvalid(s00_couplers_to_s00_regslice_WVALID));\nendmodule\n\nmodule s01_couplers_imp_GSTXQ8\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [5:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [5:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [5:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [5:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [5:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [5:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire S_ACLK_1;\n  wire S_ARESETN_1;\n  wire [63:0]s01_couplers_to_s01_regslice_ARADDR;\n  wire [1:0]s01_couplers_to_s01_regslice_ARBURST;\n  wire [3:0]s01_couplers_to_s01_regslice_ARCACHE;\n  wire [5:0]s01_couplers_to_s01_regslice_ARID;\n  wire [7:0]s01_couplers_to_s01_regslice_ARLEN;\n  wire [0:0]s01_couplers_to_s01_regslice_ARLOCK;\n  wire [2:0]s01_couplers_to_s01_regslice_ARPROT;\n  wire [3:0]s01_couplers_to_s01_regslice_ARQOS;\n  wire s01_couplers_to_s01_regslice_ARREADY;\n  wire [3:0]s01_couplers_to_s01_regslice_ARREGION;\n  wire [2:0]s01_couplers_to_s01_regslice_ARSIZE;\n  wire s01_couplers_to_s01_regslice_ARVALID;\n  wire [63:0]s01_couplers_to_s01_regslice_AWADDR;\n  wire [1:0]s01_couplers_to_s01_regslice_AWBURST;\n  wire [3:0]s01_couplers_to_s01_regslice_AWCACHE;\n  wire [5:0]s01_couplers_to_s01_regslice_AWID;\n  wire [7:0]s01_couplers_to_s01_regslice_AWLEN;\n  wire [0:0]s01_couplers_to_s01_regslice_AWLOCK;\n  wire [2:0]s01_couplers_to_s01_regslice_AWPROT;\n  wire [3:0]s01_couplers_to_s01_regslice_AWQOS;\n  wire s01_couplers_to_s01_regslice_AWREADY;\n  wire [3:0]s01_couplers_to_s01_regslice_AWREGION;\n  wire [2:0]s01_couplers_to_s01_regslice_AWSIZE;\n  wire s01_couplers_to_s01_regslice_AWVALID;\n  wire [5:0]s01_couplers_to_s01_regslice_BID;\n  wire s01_couplers_to_s01_regslice_BREADY;\n  wire [1:0]s01_couplers_to_s01_regslice_BRESP;\n  wire s01_couplers_to_s01_regslice_BVALID;\n  wire [511:0]s01_couplers_to_s01_regslice_RDATA;\n  wire [5:0]s01_couplers_to_s01_regslice_RID;\n  wire s01_couplers_to_s01_regslice_RLAST;\n  wire s01_couplers_to_s01_regslice_RREADY;\n  wire [1:0]s01_couplers_to_s01_regslice_RRESP;\n  wire s01_couplers_to_s01_regslice_RVALID;\n  wire [511:0]s01_couplers_to_s01_regslice_WDATA;\n  wire s01_couplers_to_s01_regslice_WLAST;\n  wire s01_couplers_to_s01_regslice_WREADY;\n  wire [63:0]s01_couplers_to_s01_regslice_WSTRB;\n  wire s01_couplers_to_s01_regslice_WVALID;\n  wire [63:0]s01_regslice_to_s01_couplers_ARADDR;\n  wire [1:0]s01_regslice_to_s01_couplers_ARBURST;\n  wire [3:0]s01_regslice_to_s01_couplers_ARCACHE;\n  wire [5:0]s01_regslice_to_s01_couplers_ARID;\n  wire [7:0]s01_regslice_to_s01_couplers_ARLEN;\n  wire [0:0]s01_regslice_to_s01_couplers_ARLOCK;\n  wire [2:0]s01_regslice_to_s01_couplers_ARPROT;\n  wire [3:0]s01_regslice_to_s01_couplers_ARQOS;\n  wire s01_regslice_to_s01_couplers_ARREADY;\n  wire [2:0]s01_regslice_to_s01_couplers_ARSIZE;\n  wire s01_regslice_to_s01_couplers_ARVALID;\n  wire [63:0]s01_regslice_to_s01_couplers_AWADDR;\n  wire [1:0]s01_regslice_to_s01_couplers_AWBURST;\n  wire [3:0]s01_regslice_to_s01_couplers_AWCACHE;\n  wire [5:0]s01_regslice_to_s01_couplers_AWID;\n  wire [7:0]s01_regslice_to_s01_couplers_AWLEN;\n  wire [0:0]s01_regslice_to_s01_couplers_AWLOCK;\n  wire [2:0]s01_regslice_to_s01_couplers_AWPROT;\n  wire [3:0]s01_regslice_to_s01_couplers_AWQOS;\n  wire s01_regslice_to_s01_couplers_AWREADY;\n  wire [2:0]s01_regslice_to_s01_couplers_AWSIZE;\n  wire s01_regslice_to_s01_couplers_AWVALID;\n  wire [6:0]s01_regslice_to_s01_couplers_BID;\n  wire s01_regslice_to_s01_couplers_BREADY;\n  wire [1:0]s01_regslice_to_s01_couplers_BRESP;\n  wire s01_regslice_to_s01_couplers_BVALID;\n  wire [511:0]s01_regslice_to_s01_couplers_RDATA;\n  wire [6:0]s01_regslice_to_s01_couplers_RID;\n  wire s01_regslice_to_s01_couplers_RLAST;\n  wire s01_regslice_to_s01_couplers_RREADY;\n  wire [1:0]s01_regslice_to_s01_couplers_RRESP;\n  wire s01_regslice_to_s01_couplers_RVALID;\n  wire [511:0]s01_regslice_to_s01_couplers_WDATA;\n  wire s01_regslice_to_s01_couplers_WLAST;\n  wire s01_regslice_to_s01_couplers_WREADY;\n  wire [63:0]s01_regslice_to_s01_couplers_WSTRB;\n  wire s01_regslice_to_s01_couplers_WVALID;\n\n  assign M_AXI_araddr[63:0] = s01_regslice_to_s01_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = s01_regslice_to_s01_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = s01_regslice_to_s01_couplers_ARCACHE;\n  assign M_AXI_arid[5:0] = s01_regslice_to_s01_couplers_ARID;\n  assign M_AXI_arlen[7:0] = s01_regslice_to_s01_couplers_ARLEN;\n  assign M_AXI_arlock[0] = s01_regslice_to_s01_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = s01_regslice_to_s01_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = s01_regslice_to_s01_couplers_ARQOS;\n  assign M_AXI_arsize[2:0] = s01_regslice_to_s01_couplers_ARSIZE;\n  assign M_AXI_arvalid = s01_regslice_to_s01_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = s01_regslice_to_s01_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = s01_regslice_to_s01_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = s01_regslice_to_s01_couplers_AWCACHE;\n  assign M_AXI_awid[5:0] = s01_regslice_to_s01_couplers_AWID;\n  assign M_AXI_awlen[7:0] = s01_regslice_to_s01_couplers_AWLEN;\n  assign M_AXI_awlock[0] = s01_regslice_to_s01_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = s01_regslice_to_s01_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = s01_regslice_to_s01_couplers_AWQOS;\n  assign M_AXI_awsize[2:0] = s01_regslice_to_s01_couplers_AWSIZE;\n  assign M_AXI_awvalid = s01_regslice_to_s01_couplers_AWVALID;\n  assign M_AXI_bready = s01_regslice_to_s01_couplers_BREADY;\n  assign M_AXI_rready = s01_regslice_to_s01_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = s01_regslice_to_s01_couplers_WDATA;\n  assign M_AXI_wlast = s01_regslice_to_s01_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = s01_regslice_to_s01_couplers_WSTRB;\n  assign M_AXI_wvalid = s01_regslice_to_s01_couplers_WVALID;\n  assign S_ACLK_1 = S_ACLK;\n  assign S_ARESETN_1 = S_ARESETN;\n  assign S_AXI_arready = s01_couplers_to_s01_regslice_ARREADY;\n  assign S_AXI_awready = s01_couplers_to_s01_regslice_AWREADY;\n  assign S_AXI_bid[5:0] = s01_couplers_to_s01_regslice_BID;\n  assign S_AXI_bresp[1:0] = s01_couplers_to_s01_regslice_BRESP;\n  assign S_AXI_bvalid = s01_couplers_to_s01_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = s01_couplers_to_s01_regslice_RDATA;\n  assign S_AXI_rid[5:0] = s01_couplers_to_s01_regslice_RID;\n  assign S_AXI_rlast = s01_couplers_to_s01_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = s01_couplers_to_s01_regslice_RRESP;\n  assign S_AXI_rvalid = s01_couplers_to_s01_regslice_RVALID;\n  assign S_AXI_wready = s01_couplers_to_s01_regslice_WREADY;\n  assign s01_couplers_to_s01_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign s01_couplers_to_s01_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign s01_couplers_to_s01_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign s01_couplers_to_s01_regslice_ARID = S_AXI_arid[5:0];\n  assign s01_couplers_to_s01_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign s01_couplers_to_s01_regslice_ARLOCK = S_AXI_arlock[0];\n  assign s01_couplers_to_s01_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign s01_couplers_to_s01_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign s01_couplers_to_s01_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign s01_couplers_to_s01_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign s01_couplers_to_s01_regslice_ARVALID = S_AXI_arvalid;\n  assign s01_couplers_to_s01_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign s01_couplers_to_s01_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign s01_couplers_to_s01_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign s01_couplers_to_s01_regslice_AWID = S_AXI_awid[5:0];\n  assign s01_couplers_to_s01_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign s01_couplers_to_s01_regslice_AWLOCK = S_AXI_awlock[0];\n  assign s01_couplers_to_s01_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign s01_couplers_to_s01_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign s01_couplers_to_s01_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign s01_couplers_to_s01_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign s01_couplers_to_s01_regslice_AWVALID = S_AXI_awvalid;\n  assign s01_couplers_to_s01_regslice_BREADY = S_AXI_bready;\n  assign s01_couplers_to_s01_regslice_RREADY = S_AXI_rready;\n  assign s01_couplers_to_s01_regslice_WDATA = S_AXI_wdata[511:0];\n  assign s01_couplers_to_s01_regslice_WLAST = S_AXI_wlast;\n  assign s01_couplers_to_s01_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign s01_couplers_to_s01_regslice_WVALID = S_AXI_wvalid;\n  assign s01_regslice_to_s01_couplers_ARREADY = M_AXI_arready;\n  assign s01_regslice_to_s01_couplers_AWREADY = M_AXI_awready;\n  assign s01_regslice_to_s01_couplers_BID = M_AXI_bid[6:0];\n  assign s01_regslice_to_s01_couplers_BRESP = M_AXI_bresp[1:0];\n  assign s01_regslice_to_s01_couplers_BVALID = M_AXI_bvalid;\n  assign s01_regslice_to_s01_couplers_RDATA = M_AXI_rdata[511:0];\n  assign s01_regslice_to_s01_couplers_RID = M_AXI_rid[6:0];\n  assign s01_regslice_to_s01_couplers_RLAST = M_AXI_rlast;\n  assign s01_regslice_to_s01_couplers_RRESP = M_AXI_rresp[1:0];\n  assign s01_regslice_to_s01_couplers_RVALID = M_AXI_rvalid;\n  assign s01_regslice_to_s01_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_s01_regslice_0 s01_regslice\n       (.aclk(S_ACLK_1),\n        .aresetn(S_ARESETN_1),\n        .m_axi_araddr(s01_regslice_to_s01_couplers_ARADDR),\n        .m_axi_arburst(s01_regslice_to_s01_couplers_ARBURST),\n        .m_axi_arcache(s01_regslice_to_s01_couplers_ARCACHE),\n        .m_axi_arid(s01_regslice_to_s01_couplers_ARID),\n        .m_axi_arlen(s01_regslice_to_s01_couplers_ARLEN),\n        .m_axi_arlock(s01_regslice_to_s01_couplers_ARLOCK),\n        .m_axi_arprot(s01_regslice_to_s01_couplers_ARPROT),\n        .m_axi_arqos(s01_regslice_to_s01_couplers_ARQOS),\n        .m_axi_arready(s01_regslice_to_s01_couplers_ARREADY),\n        .m_axi_arsize(s01_regslice_to_s01_couplers_ARSIZE),\n        .m_axi_arvalid(s01_regslice_to_s01_couplers_ARVALID),\n        .m_axi_awaddr(s01_regslice_to_s01_couplers_AWADDR),\n        .m_axi_awburst(s01_regslice_to_s01_couplers_AWBURST),\n        .m_axi_awcache(s01_regslice_to_s01_couplers_AWCACHE),\n        .m_axi_awid(s01_regslice_to_s01_couplers_AWID),\n        .m_axi_awlen(s01_regslice_to_s01_couplers_AWLEN),\n        .m_axi_awlock(s01_regslice_to_s01_couplers_AWLOCK),\n        .m_axi_awprot(s01_regslice_to_s01_couplers_AWPROT),\n        .m_axi_awqos(s01_regslice_to_s01_couplers_AWQOS),\n        .m_axi_awready(s01_regslice_to_s01_couplers_AWREADY),\n        .m_axi_awsize(s01_regslice_to_s01_couplers_AWSIZE),\n        .m_axi_awvalid(s01_regslice_to_s01_couplers_AWVALID),\n        .m_axi_bid(s01_regslice_to_s01_couplers_BID[5:0]),\n        .m_axi_bready(s01_regslice_to_s01_couplers_BREADY),\n        .m_axi_bresp(s01_regslice_to_s01_couplers_BRESP),\n        .m_axi_bvalid(s01_regslice_to_s01_couplers_BVALID),\n        .m_axi_rdata(s01_regslice_to_s01_couplers_RDATA),\n        .m_axi_rid(s01_regslice_to_s01_couplers_RID[5:0]),\n        .m_axi_rlast(s01_regslice_to_s01_couplers_RLAST),\n        .m_axi_rready(s01_regslice_to_s01_couplers_RREADY),\n        .m_axi_rresp(s01_regslice_to_s01_couplers_RRESP),\n        .m_axi_rvalid(s01_regslice_to_s01_couplers_RVALID),\n        .m_axi_wdata(s01_regslice_to_s01_couplers_WDATA),\n        .m_axi_wlast(s01_regslice_to_s01_couplers_WLAST),\n        .m_axi_wready(s01_regslice_to_s01_couplers_WREADY),\n        .m_axi_wstrb(s01_regslice_to_s01_couplers_WSTRB),\n        .m_axi_wvalid(s01_regslice_to_s01_couplers_WVALID),\n        .s_axi_araddr(s01_couplers_to_s01_regslice_ARADDR),\n        .s_axi_arburst(s01_couplers_to_s01_regslice_ARBURST),\n        .s_axi_arcache(s01_couplers_to_s01_regslice_ARCACHE),\n        .s_axi_arid(s01_couplers_to_s01_regslice_ARID),\n        .s_axi_arlen(s01_couplers_to_s01_regslice_ARLEN),\n        .s_axi_arlock(s01_couplers_to_s01_regslice_ARLOCK),\n        .s_axi_arprot(s01_couplers_to_s01_regslice_ARPROT),\n        .s_axi_arqos(s01_couplers_to_s01_regslice_ARQOS),\n        .s_axi_arready(s01_couplers_to_s01_regslice_ARREADY),\n        .s_axi_arregion(s01_couplers_to_s01_regslice_ARREGION),\n        .s_axi_arsize(s01_couplers_to_s01_regslice_ARSIZE),\n        .s_axi_arvalid(s01_couplers_to_s01_regslice_ARVALID),\n        .s_axi_awaddr(s01_couplers_to_s01_regslice_AWADDR),\n        .s_axi_awburst(s01_couplers_to_s01_regslice_AWBURST),\n        .s_axi_awcache(s01_couplers_to_s01_regslice_AWCACHE),\n        .s_axi_awid(s01_couplers_to_s01_regslice_AWID),\n        .s_axi_awlen(s01_couplers_to_s01_regslice_AWLEN),\n        .s_axi_awlock(s01_couplers_to_s01_regslice_AWLOCK),\n        .s_axi_awprot(s01_couplers_to_s01_regslice_AWPROT),\n        .s_axi_awqos(s01_couplers_to_s01_regslice_AWQOS),\n        .s_axi_awready(s01_couplers_to_s01_regslice_AWREADY),\n        .s_axi_awregion(s01_couplers_to_s01_regslice_AWREGION),\n        .s_axi_awsize(s01_couplers_to_s01_regslice_AWSIZE),\n        .s_axi_awvalid(s01_couplers_to_s01_regslice_AWVALID),\n        .s_axi_bid(s01_couplers_to_s01_regslice_BID),\n        .s_axi_bready(s01_couplers_to_s01_regslice_BREADY),\n        .s_axi_bresp(s01_couplers_to_s01_regslice_BRESP),\n        .s_axi_bvalid(s01_couplers_to_s01_regslice_BVALID),\n        .s_axi_rdata(s01_couplers_to_s01_regslice_RDATA),\n        .s_axi_rid(s01_couplers_to_s01_regslice_RID),\n        .s_axi_rlast(s01_couplers_to_s01_regslice_RLAST),\n        .s_axi_rready(s01_couplers_to_s01_regslice_RREADY),\n        .s_axi_rresp(s01_couplers_to_s01_regslice_RRESP),\n        .s_axi_rvalid(s01_couplers_to_s01_regslice_RVALID),\n        .s_axi_wdata(s01_couplers_to_s01_regslice_WDATA),\n        .s_axi_wlast(s01_couplers_to_s01_regslice_WLAST),\n        .s_axi_wready(s01_couplers_to_s01_regslice_WREADY),\n        .s_axi_wstrb(s01_couplers_to_s01_regslice_WSTRB),\n        .s_axi_wvalid(s01_couplers_to_s01_regslice_WVALID));\nendmodule\n", "num_lines": 5426}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sync_clock_converter\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axic_sync_clock_converter # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_FAMILY     = \"virtex6\",\n  parameter integer C_PAYLOAD_WIDTH = 32,\n  parameter integer C_S_ACLK_RATIO = 1,\n  parameter integer C_M_ACLK_RATIO = 1 ,\n  parameter integer C_MODE = 0  // 0 = light-weight (1-deep); 1 = fully-pipelined (2-deep)\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input wire                    SAMPLE_CYCLE_EARLY,\n  input wire                    SAMPLE_CYCLE,\n  // Slave side\n  input  wire                        S_ACLK,\n  input  wire                        S_ARESETN,\n  input  wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD,\n  input  wire                        S_VALID,\n  output wire                        S_READY,\n\n  // Master side\n  input  wire                        M_ACLK,\n  input  wire                        M_ARESETN,\n  output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD,\n  output wire                        M_VALID,\n  input  wire                        M_READY\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam [1:0] ZERO = 2'b10;\nlocalparam [1:0] ONE  = 2'b11;\nlocalparam [1:0] TWO  = 2'b01;\nlocalparam [1:0] INIT = 2'b00;\nlocalparam integer P_LIGHT_WT = 0;\nlocalparam integer P_FULLY_REG = 1;\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\ngenerate\n  if (C_S_ACLK_RATIO == C_M_ACLK_RATIO) begin : gen_passthru\n    assign M_PAYLOAD = S_PAYLOAD;\n    assign M_VALID   = S_VALID;\n    assign S_READY   = M_READY;      \n  end else begin : gen_sync_clock_converter\n    wire s_sample_cycle;\n    wire s_sample_cycle_early;\n    wire m_sample_cycle;\n    wire m_sample_cycle_early;\n\n    wire slow_aclk;\n    wire slow_areset;\n    wire s_areset_r;\n    wire m_areset_r;\n   \n    reg  s_tready_r = 1'b0; \n    wire s_tready_ns; \n    reg  m_tvalid_r = 1'b0; \n    wire m_tvalid_ns; \n    reg  [C_PAYLOAD_WIDTH-1:0] m_tpayload_r;\n    reg  [C_PAYLOAD_WIDTH-1:0] m_tstorage_r;\n    wire [C_PAYLOAD_WIDTH-1:0] m_tpayload_ns; \n    wire [C_PAYLOAD_WIDTH-1:0] m_tstorage_ns; \n    reg  m_tready_hold = 1'b0;\n    wire m_tready_sample;\n    wire load_tpayload;\n    wire load_tstorage;\n    wire load_tpayload_from_tstorage;\n    reg [1:0] state = INIT;\n    reg [1:0] next_state;\n    \n    reg s_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge S_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        s_aresetn_r <= 1'b0;\n      end else begin\n        s_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign s_areset_r = ~s_aresetn_r;\n\n    reg m_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge M_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        m_aresetn_r <= 1'b0;\n      end else begin\n        m_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign m_areset_r = ~m_aresetn_r;\n\n    if (C_S_ACLK_RATIO > C_M_ACLK_RATIO) begin : gen_slowclk_mi\n      assign slow_aclk = M_ACLK;\n    end else begin : gen_slowclk_si\n      assign slow_aclk = S_ACLK;\n    end\n  \n    assign slow_areset = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? m_areset_r : s_areset_r;\n    assign s_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE_EARLY : 1'b1;\n    assign s_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE : 1'b1;\n    assign m_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE_EARLY;\n    assign m_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE;\n\n    // Output flop for S_READY, value is encoded into state machine.\n    assign s_tready_ns = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? state[1] & (state != INIT) : next_state[1];\n\n    always @(posedge S_ACLK) begin \n      if (s_areset_r) begin\n        s_tready_r <= 1'b0;\n      end\n      else begin\n        s_tready_r <= s_sample_cycle_early ? s_tready_ns : 1'b0;\n      end\n    end\n\n    assign S_READY = s_tready_r;\n\n    // Output flop for M_VALID\n    assign m_tvalid_ns = next_state[0];\n\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tvalid_r <= 1'b0;\n      end\n      else begin\n        m_tvalid_r <= m_sample_cycle ? m_tvalid_ns : m_tvalid_r & ~M_READY;\n      end\n    end\n\n    assign M_VALID = m_tvalid_r;\n\n    // Hold register for M_READY when M_ACLK is fast.\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tready_hold <= 1'b0;\n      end\n      else begin\n        m_tready_hold <= m_sample_cycle ? 1'b0 : m_tready_sample;\n      end\n    end\n\n    assign m_tready_sample = (M_READY ) | m_tready_hold;\n    // Output/storage flops for PAYLOAD\n    assign m_tpayload_ns = ~load_tpayload ? m_tpayload_r :\n                           load_tpayload_from_tstorage ? m_tstorage_r : \n                           S_PAYLOAD;\n\n    assign m_tstorage_ns = C_MODE ? (load_tstorage ? S_PAYLOAD : m_tstorage_r) : 0;\n\n    always @(posedge slow_aclk) begin \n      m_tpayload_r <= m_tpayload_ns;\n      m_tstorage_r <= C_MODE ? m_tstorage_ns : 0;\n    end\n\n    assign M_PAYLOAD = m_tpayload_r;\n\n    // load logic\n    assign load_tstorage = C_MODE && (state != TWO);\n    assign load_tpayload = m_tready_sample || (state == ZERO);\n    assign load_tpayload_from_tstorage = C_MODE && (state == TWO) && m_tready_sample;\n    \n    // State machine\n    always @(posedge slow_aclk) begin \n      state <= next_state;\n    end\n\n    always @* begin \n      if (slow_areset) begin \n        next_state = INIT;\n      end else begin\n        case (state)\n          INIT: begin\n            next_state = ZERO;\n          end\n          // No transaction stored locally\n          ZERO: begin\n            if (S_VALID) begin\n              next_state = C_MODE ? ONE : TWO; // Push from empty\n            end\n            else begin\n              next_state = ZERO;\n            end\n          end\n\n          // One transaction stored locally\n          ONE: begin\n            if (C_MODE == 0) begin\n              next_state = TWO;  // State ONE is inaccessible when C_MODE=0\n            end \n            else if (m_tready_sample & ~S_VALID) begin \n              next_state = ZERO; // Read out one so move to ZERO\n            end\n            else if (~m_tready_sample & S_VALID) begin\n              next_state = TWO;  // Got another one so move to TWO\n            end\n            else begin\n              next_state = ONE;\n            end\n          end\n\n          // Storage registers full\n          TWO: begin \n            if (m_tready_sample) begin\n              next_state = C_MODE ? ONE : ZERO; // Pop from full\n            end\n            else begin\n              next_state = TWO;\n            end\n          end\n        endcase // case (state)\n      end\n    end\n  end // gen_sync_clock_converter\n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sample_cycle_ratio\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axic_sample_cycle_ratio # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_RATIO = 2 // Must be > 0\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    SLOW_ACLK,\n  input  wire                    FAST_ACLK,\n\n  output wire                    SAMPLE_CYCLE_EARLY,\n  output wire                    SAMPLE_CYCLE\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam P_DELAY = C_RATIO > 2 ? C_RATIO-1 : C_RATIO-1; \n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_aclk_div2 = 1'b0;\nreg                posedge_finder_first = 1'b0;\nreg                posedge_finder_second = 1'b0;\nwire               first_edge;\nwire               second_edge;\nwire               any_edge;\nreg  [P_DELAY-1:0] sample_cycle_d = {P_DELAY{1'b0}};\n(* shreg_extract = \"no\" *) reg                sample_cycle_r = 1'b0;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\ngenerate\n  if (C_RATIO == 1) begin : gen_always_sample\n    assign SAMPLE_CYCLE_EARLY = 1'b1;\n    assign SAMPLE_CYCLE = 1'b1;\n  end\n  else begin : gen_sample_cycle\n    genvar i;\n    always @(posedge SLOW_ACLK) begin \n      slow_aclk_div2 <= ~slow_aclk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_aclk_div2 onto faster clock\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_first <= slow_aclk_div2;\n    end\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_second <= ~slow_aclk_div2;\n    end\n\n    assign first_edge = slow_aclk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;\n    assign any_edge = first_edge | second_edge;\n   \n    // delay the posedge alignment by C_RATIO - 1 to set the sample cycle as\n    // the clock one cycle before the posedge.\n    for (i = P_DELAY-1; i > 0; i = i - 1) begin : gen_delay\n      always @(posedge FAST_ACLK) begin\n        if (i == P_DELAY-1) begin\n          sample_cycle_d[i-1] <= any_edge;\n        end else begin\n          sample_cycle_d[i-1] <= sample_cycle_d[i];\n        end\n      end\n    end\n\n    always @(posedge FAST_ACLK) begin \n      sample_cycle_r <= (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    end\n    assign SAMPLE_CYCLE_EARLY = (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    assign SAMPLE_CYCLE = sample_cycle_r;\n  end\nendgenerate\n\nendmodule // axisc_sample_cycle_ratio\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2010 - 2016 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and\n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Clock converter module\n//   Asynchronous clock converter when asynchronous M:N conversion\n//   Bypass when synchronous and ratio between S and M clock is 1:1\n//   Synchronous clock converter (S:M or M:S must be integer ratio)\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_clock_conv\n//     fifo_generator\n//     axic_sync_clock_converter\n//       axic_sample_cycle_ratio\n//\n// PROTECTED NAMES:\n//   Instance names \"asyncfifo_*\" are pattern-matched in core-level UCF.\n//   Signal names \"*_resync\" are pattern-matched in core-level UCF.\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_lite_async #(\n  parameter integer C_DEST_SYNC_FF = 3,\n  parameter integer C_SRC_SYNC_FF  = 3,\n  parameter integer C_WIDTH        = 1\n) (\n  input wire                s_aclk,\n  input wire                m_aclk,\n  input wire                s_aresetn,\n  input wire                m_aresetn,\n  input wire                s_valid,\n  output wire                s_ready,\n  input wire [C_WIDTH-1:0]  s_payld,\n  output wire                m_valid,\n  input wire                m_ready,\n  output wire [C_WIDTH-1:0] m_payld\n);\n\nreg [C_SRC_SYNC_FF:0] s_areset_dly = {C_SRC_SYNC_FF+1{1'b0}};\nreg [C_DEST_SYNC_FF:0] m_areset_dly = {C_DEST_SYNC_FF+1{1'b0}};\nreg                s_ready_i = 1'b0;\nreg                m_valid_i = 1'b0;\nreg   src_send = 1'b0;\nreg   dest_ack = 1'b0;\nwire  src_rcv;\nwire  dest_req;\n\nassign s_ready = s_ready_i;\nassign m_valid = m_valid_i;\n\nlocalparam SRC_IDLE           = 2'b00;\nlocalparam SRC_DRV_SEND       = 2'b01;\nlocalparam SRC_WAIT_RCV_DONE  = 2'b10;\nreg [1:0] src_state = SRC_IDLE;\n\nalways @(posedge s_aclk) begin\n  s_areset_dly <= {C_SRC_SYNC_FF+1{~s_aresetn}} | (s_areset_dly<<1);\n  if (s_areset_dly[C_SRC_SYNC_FF]) begin\n    s_ready_i <= 1'b0;\n    src_send <= 1'b0;\n    src_state <= SRC_IDLE;\n  end else begin\n    case (src_state)\n      SRC_IDLE: begin\n        if (s_valid) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end\n      end\n      SRC_DRV_SEND: begin\n        if (src_rcv) begin\n          s_ready_i <= 1'b1;\n          src_send <= 1'b0;\n          src_state <= SRC_WAIT_RCV_DONE;\n        end\n      end\n      SRC_WAIT_RCV_DONE: begin\n        s_ready_i <= 1'b0;\n        if (s_valid & !src_rcv) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end else if (!src_rcv) begin\n          src_state <= SRC_IDLE;\n        end\n      end\n      default: begin\n        s_ready_i <= 1'b0;\n        src_send <= 1'b0;\n        src_state <= SRC_IDLE;\n      end\n    endcase\n  end\nend\n\nlocalparam DEST_IDLE           = 2'b00;\nlocalparam DEST_DRV_VALID      = 2'b01;\nlocalparam DEST_DRV_ACK        = 2'b10;\nreg [1:0] dest_state = DEST_IDLE;\n\nalways @(posedge m_aclk) begin\n  m_areset_dly <= {C_DEST_SYNC_FF+1{~m_aresetn}} | (m_areset_dly<<1);\n  if (m_areset_dly[C_DEST_SYNC_FF]) begin\n    m_valid_i <= 1'b0;\n    dest_ack <= 1'b0;\n    dest_state <= DEST_IDLE;\n  end else begin\n    case (dest_state)\n      DEST_IDLE: begin\n        if (dest_req) begin\n          dest_state <= DEST_DRV_VALID;\n          m_valid_i <= 1'b1;\n        end else begin\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b0;\n        end\n      end\n      DEST_DRV_VALID: begin\n        if (m_ready & m_valid_i) begin\n          dest_state <= DEST_DRV_ACK;\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b1;\n        end\n      end\n      DEST_DRV_ACK: begin\n        if (!dest_req) begin\n          dest_state <= DEST_IDLE;\n          dest_ack <= 1'b0;\n        end\n      end\n      default: begin\n        m_valid_i <= 1'b0;\n        dest_ack <= 1'b0;\n        dest_state <= DEST_IDLE;\n      end\n    endcase\n  end\nend\n\nxpm_cdc_handshake #(\n  .DEST_SYNC_FF   (C_DEST_SYNC_FF),\n  .SRC_SYNC_FF    (C_SRC_SYNC_FF),\n  .WIDTH          (C_WIDTH)\n) handshake (\n  .src_clk  (s_aclk),\n  .src_in   (s_payld),\n  .src_send (src_send),\n  .src_rcv  (src_rcv),\n  .dest_clk (m_aclk),\n  .dest_out (m_payld),\n  .dest_req (dest_req),\n  .dest_ack (dest_ack)\n);\n\nendmodule\n\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axi_clock_converter #\n  (parameter         C_FAMILY = \"virtex7\",\n   parameter integer C_AXI_ID_WIDTH = 5,                    // Width of all ID signals on SI and MI side.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ADDR_WIDTH = 32,                 // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and\n                                                            // m_axi_araddr.\n                                                            // Range: 32.\n   parameter integer C_AXI_DATA_WIDTH = 32,       // Width of WDATA and RDATA (either side).\n                                                            // Format: Bit32;\n                                                            // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.\n   parameter integer C_S_AXI_ACLK_RATIO = 1,     // Clock frequency ratio of SI w.r.t. MI.\n   parameter integer C_M_AXI_ACLK_RATIO = 1,     // (Slowest of all clock inputs should have ratio=1.)\n                                                            // S:M or M:S must be integer ratio.\n                                                            // Format: Bit32; Range: >='h00000001.\n   parameter integer C_AXI_IS_ACLK_ASYNC = 1,            // Indicates whether S and M clocks are asynchronous.\n                                                            // FUTURE FEATURE\n                                                            // Format: Bit1. Range = 1'b0.\n   parameter integer C_AXI_PROTOCOL = 0,         // Protocol of this SI/MI slot.\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS  = 1,      // 1 = Propagate all USER signals, 0 = Do not propagate.\n   parameter integer C_AXI_AWUSER_WIDTH = 1,                // Width of AWUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ARUSER_WIDTH = 1,                // Width of ARUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_WUSER_WIDTH = 1,                 // Width of WUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_RUSER_WIDTH = 1,                 // Width of RUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_BUSER_WIDTH = 1,                 // Width of BUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,              // Implement AXI write channels\n   parameter integer C_AXI_SUPPORTS_READ = 1,               // Implement AXI read channels\n   parameter integer C_SYNCHRONIZER_STAGE = 3\n  )\n\n  (\n   // Slave Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n   input  wire [4-1:0]                    s_axi_awcache,\n   input  wire [3-1:0]                    s_axi_awprot,\n   input  wire [4-1:0]                    s_axi_awregion,\n   input  wire [4-1:0]                    s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0]   s_axi_awuser,\n   input  wire                            s_axi_awvalid,\n   output wire                            s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n   input  wire                            s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]    s_axi_wuser,\n   input  wire                            s_axi_wvalid,\n   output wire                            s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_bid,\n   output wire [2-1:0]                    s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0]    s_axi_buser,\n   output wire                            s_axi_bvalid,\n   input  wire                            s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n   input  wire [3-1:0]                    s_axi_arsize,\n   input  wire [2-1:0]                    s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n   input  wire [4-1:0]                    s_axi_arcache,\n   input  wire [3-1:0]                    s_axi_arprot,\n   input  wire [4-1:0]                    s_axi_arregion,\n   input  wire [4-1:0]                    s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0]   s_axi_aruser,\n   input  wire                            s_axi_arvalid,\n   output wire                            s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n   output wire [2-1:0]                    s_axi_rresp,\n   output wire                            s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0]    s_axi_ruser,\n   output wire                            s_axi_rvalid,\n   input  wire                            s_axi_rready,\n\n   // Master Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aresetn,\n\n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n   output wire [3-1:0]                    m_axi_awsize,\n   output wire [2-1:0]                    m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n   output wire [4-1:0]                    m_axi_awcache,\n   output wire [3-1:0]                    m_axi_awprot,\n   output wire [4-1:0]                    m_axi_awregion,\n   output wire [4-1:0]                    m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0]   m_axi_awuser,\n   output wire                            m_axi_awvalid,\n   input  wire                            m_axi_awready,\n\n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0]   m_axi_wstrb,\n   output wire                            m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]    m_axi_wuser,\n   output wire                            m_axi_wvalid,\n   input  wire                            m_axi_wready,\n\n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_bid,\n   input  wire [2-1:0]                    m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0]    m_axi_buser,\n   input  wire                            m_axi_bvalid,\n   output wire                            m_axi_bready,\n\n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n   output wire [3-1:0]                    m_axi_arsize,\n   output wire [2-1:0]                    m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n   output wire [4-1:0]                    m_axi_arcache,\n   output wire [3-1:0]                    m_axi_arprot,\n   output wire [4-1:0]                    m_axi_arregion,\n   output wire [4-1:0]                    m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0]   m_axi_aruser,\n   output wire                            m_axi_arvalid,\n   input  wire                            m_axi_arready,\n\n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     m_axi_rdata,\n   input  wire [2-1:0]                    m_axi_rresp,\n   input  wire                            m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0]    m_axi_ruser,\n   input  wire                            m_axi_rvalid,\n   output wire                            m_axi_rready);\n\n  localparam integer P_AXI4 = 0;\n  localparam integer P_AXI3 = 1;\n  localparam integer P_AXILITE = 2;\n  localparam integer P_LIGHT_WT = 0;\n  localparam integer P_FULLY_REG = 1;\n  localparam integer P_LUTRAM_ASYNC = 12;\n\n  // Sample cycle ratio\n  localparam  P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);\n  localparam integer P_ROUNDING_OFFSET = P_SI_LT_MI ? (C_S_AXI_ACLK_RATIO/2) : (C_M_AXI_ACLK_RATIO/2);\n  localparam integer P_ACLK_RATIO = P_SI_LT_MI ?\n    ((C_M_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_S_AXI_ACLK_RATIO) :\n    ((C_S_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_M_AXI_ACLK_RATIO);\n\n  // Write Address Port bit positions\n  localparam integer C_AWUSER_RIGHT   = 0;\n  localparam integer C_AWUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_AWUSER_WIDTH : 0;\n  localparam integer C_AWQOS_RIGHT    = C_AWUSER_RIGHT + C_AWUSER_WIDTH;\n  localparam integer C_AWQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWREGION_RIGHT = C_AWQOS_RIGHT + C_AWQOS_WIDTH;\n  localparam integer C_AWREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_AWPROT_RIGHT   = C_AWREGION_RIGHT + C_AWREGION_WIDTH;\n  localparam integer C_AWPROT_WIDTH     = 3;\n  localparam integer C_AWCACHE_RIGHT  = C_AWPROT_RIGHT + C_AWPROT_WIDTH;\n  localparam integer C_AWCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWLOCK_RIGHT   = C_AWCACHE_RIGHT + C_AWCACHE_WIDTH;\n  localparam integer C_AWLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_AWBURST_RIGHT  = C_AWLOCK_RIGHT + C_AWLOCK_WIDTH;\n  localparam integer C_AWBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_AWSIZE_RIGHT   = C_AWBURST_RIGHT + C_AWBURST_WIDTH;\n  localparam integer C_AWSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_AWLEN_RIGHT    = C_AWSIZE_RIGHT + C_AWSIZE_WIDTH;\n  localparam integer C_AWLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_AWADDR_RIGHT   = C_AWLEN_RIGHT + C_AWLEN_WIDTH;\n  localparam integer C_AWADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_AWID_RIGHT     = C_AWADDR_RIGHT + C_AWADDR_WIDTH;\n  localparam integer C_AWID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AW_WIDTH        = C_AWID_RIGHT + C_AWID_WIDTH;\n  localparam integer C_FIFO_AW_WIDTH   = C_AWUSER_WIDTH+C_AWQOS_WIDTH+C_AWQOS_WIDTH+3+C_AWCACHE_WIDTH+C_AWLOCK_WIDTH+C_AWBURST_WIDTH+C_AWSIZE_WIDTH+C_AWLEN_WIDTH+C_AXI_ADDR_WIDTH+C_AWID_WIDTH;\n\n  // Write Data Port bit positions\n  localparam integer C_WUSER_RIGHT   = 0;\n  localparam integer C_WUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_WUSER_WIDTH : 0;\n  localparam integer C_WLAST_RIGHT   = C_WUSER_RIGHT + C_WUSER_WIDTH;\n  localparam integer C_WLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_WSTRB_RIGHT   = C_WLAST_RIGHT + C_WLAST_WIDTH;\n  localparam integer C_WSTRB_WIDTH     = C_AXI_DATA_WIDTH/8;\n  localparam integer C_WDATA_RIGHT   = C_WSTRB_RIGHT + C_WSTRB_WIDTH;\n  localparam integer C_WDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_WID_RIGHT     = C_WDATA_RIGHT + C_WDATA_WIDTH;\n  localparam integer C_WID_WIDTH       = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_W_WIDTH        = C_WID_RIGHT + C_WID_WIDTH;\n  localparam integer C_FIFO_W_WIDTH   = C_WUSER_WIDTH + C_WLAST_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_DATA_WIDTH + C_WID_WIDTH;\n\n  // Write Response Port bit positions\n  localparam integer C_BUSER_RIGHT   = 0;\n  localparam integer C_BUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_BUSER_WIDTH : 0;\n  localparam integer C_BRESP_RIGHT   = C_BUSER_RIGHT + C_BUSER_WIDTH;\n  localparam integer C_BRESP_WIDTH     = 2;\n  localparam integer C_BID_RIGHT     = C_BRESP_RIGHT + C_BRESP_WIDTH;\n  localparam integer C_BID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_B_WIDTH        = C_BID_RIGHT + C_BID_WIDTH;\n  localparam integer C_FIFO_B_WIDTH    = C_BUSER_WIDTH + 2 + C_BID_WIDTH;\n\n  // Read Address Port bit positions\n  localparam integer C_ARUSER_RIGHT   = 0;\n  localparam integer C_ARUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_ARUSER_WIDTH : 0;\n  localparam integer C_ARQOS_RIGHT    = C_ARUSER_RIGHT + C_ARUSER_WIDTH;\n  localparam integer C_ARQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARREGION_RIGHT = C_ARQOS_RIGHT + C_ARQOS_WIDTH;\n  localparam integer C_ARREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_ARPROT_RIGHT   = C_ARREGION_RIGHT + C_ARREGION_WIDTH;\n  localparam integer C_ARPROT_WIDTH     = 3;\n  localparam integer C_ARCACHE_RIGHT  = C_ARPROT_RIGHT + C_ARPROT_WIDTH;\n  localparam integer C_ARCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARLOCK_RIGHT   = C_ARCACHE_RIGHT + C_ARCACHE_WIDTH;\n  localparam integer C_ARLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_ARBURST_RIGHT  = C_ARLOCK_RIGHT + C_ARLOCK_WIDTH;\n  localparam integer C_ARBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_ARSIZE_RIGHT   = C_ARBURST_RIGHT + C_ARBURST_WIDTH;\n  localparam integer C_ARSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_ARLEN_RIGHT    = C_ARSIZE_RIGHT + C_ARSIZE_WIDTH;\n  localparam integer C_ARLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_ARADDR_RIGHT   = C_ARLEN_RIGHT + C_ARLEN_WIDTH;\n  localparam integer C_ARADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_ARID_RIGHT     = C_ARADDR_RIGHT + C_ARADDR_WIDTH;\n  localparam integer C_ARID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AR_WIDTH        = C_ARID_RIGHT + C_ARID_WIDTH;\n  localparam integer C_FIFO_AR_WIDTH   = C_ARUSER_WIDTH+C_ARQOS_WIDTH+C_ARQOS_WIDTH+3+C_ARCACHE_WIDTH+C_ARLOCK_WIDTH+C_ARBURST_WIDTH+C_ARSIZE_WIDTH+C_ARLEN_WIDTH+C_AXI_ADDR_WIDTH+C_ARID_WIDTH;\n\n  // Read Data Ports bit positions\n  localparam integer C_RUSER_RIGHT   = 0;\n  localparam integer C_RUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_RUSER_WIDTH : 0;\n  localparam integer C_RLAST_RIGHT   = C_RUSER_RIGHT + C_RUSER_WIDTH;\n  localparam integer C_RLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_RRESP_RIGHT   = C_RLAST_RIGHT + C_RLAST_WIDTH;\n  localparam integer C_RRESP_WIDTH     = 2;\n  localparam integer C_RDATA_RIGHT   = C_RRESP_RIGHT + C_RRESP_WIDTH;\n  localparam integer C_RDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_RID_RIGHT     = C_RDATA_RIGHT + C_RDATA_WIDTH;\n  localparam integer C_RID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_R_WIDTH        = C_RID_RIGHT + C_RID_WIDTH;\n  localparam integer C_FIFO_R_WIDTH   = C_RUSER_WIDTH + C_RLAST_WIDTH + 2 + C_AXI_DATA_WIDTH + C_RID_WIDTH;\n\n  generate\n    if ((C_AXI_IS_ACLK_ASYNC == 0) && (P_ACLK_RATIO == 1)) begin : gen_bypass\n      \n      // Write address port\n      assign m_axi_awid     = s_axi_awid;\n      assign m_axi_awaddr   = s_axi_awaddr;\n      assign m_axi_awlen    = s_axi_awlen;\n      assign m_axi_awsize   = s_axi_awsize;\n      assign m_axi_awburst  = s_axi_awburst;\n      assign m_axi_awlock   = s_axi_awlock;\n      assign m_axi_awcache  = s_axi_awcache;\n      assign m_axi_awprot   = s_axi_awprot;\n      assign m_axi_awregion = s_axi_awregion;\n      assign m_axi_awqos    = s_axi_awqos;\n      assign m_axi_awuser   = s_axi_awuser;\n      assign m_axi_awvalid  = s_axi_awvalid;\n      assign s_axi_awready  = m_axi_awready;\n\n      // Write Data Port\n      assign m_axi_wid      = s_axi_wid;\n      assign m_axi_wdata    = s_axi_wdata;\n      assign m_axi_wstrb    = s_axi_wstrb;\n      assign m_axi_wlast    = s_axi_wlast;\n      assign m_axi_wuser    = s_axi_wuser;\n      assign m_axi_wvalid   = s_axi_wvalid;\n      assign s_axi_wready   = m_axi_wready;\n\n      // Write Response Port\n      assign s_axi_bid      = m_axi_bid;\n      assign s_axi_bresp    = m_axi_bresp;\n      assign s_axi_buser    = m_axi_buser;\n      assign s_axi_bvalid   = m_axi_bvalid;\n      assign m_axi_bready   = s_axi_bready;\n\n      // Read Address Port\n      assign m_axi_arid     = s_axi_arid;\n      assign m_axi_araddr   = s_axi_araddr;\n      assign m_axi_arlen    = s_axi_arlen;\n      assign m_axi_arsize   = s_axi_arsize;\n      assign m_axi_arburst  = s_axi_arburst;\n      assign m_axi_arlock   = s_axi_arlock;\n      assign m_axi_arcache  = s_axi_arcache;\n      assign m_axi_arprot   = s_axi_arprot;\n      assign m_axi_arregion = s_axi_arregion;\n      assign m_axi_arqos    = s_axi_arqos;\n      assign m_axi_aruser   = s_axi_aruser;\n      assign m_axi_arvalid  = s_axi_arvalid;\n      assign s_axi_arready  = m_axi_arready;\n\n      // Read Data Port\n      assign s_axi_rid      = m_axi_rid;\n      assign s_axi_rdata    = m_axi_rdata;\n      assign s_axi_rresp    = m_axi_rresp;\n      assign s_axi_rlast    = m_axi_rlast;\n      assign s_axi_ruser    = m_axi_ruser;\n      assign s_axi_rvalid   = m_axi_rvalid;\n      assign m_axi_rready   = s_axi_rready;\n      \n    end else begin : gen_clock_conv\n      \n      wire fast_aclk;\n      wire slow_aclk;\n      wire sample_cycle;\n      wire sample_cycle_early;\n    \n      // Write Address Port FIFO data read and write\n      wire [C_AW_WIDTH-1:0] s_aw_mesg ;\n      wire [C_AW_WIDTH-1:0] m_aw_mesg ;\n    \n      // Write Data Port FIFO data read and write\n      wire [C_W_WIDTH-1:0] s_w_mesg;\n      wire [C_W_WIDTH-1:0] m_w_mesg;\n    \n      // Write Response Port FIFO data read and write\n      wire [C_B_WIDTH-1:0] s_b_mesg;\n      wire [C_B_WIDTH-1:0] m_b_mesg;\n    \n      // Read Address Port FIFO data read and write\n      wire [C_AR_WIDTH-1:0] s_ar_mesg;\n      wire [C_AR_WIDTH-1:0] m_ar_mesg;\n    \n      // Read Data Ports FIFO data read and write\n      wire [C_R_WIDTH-1:0] s_r_mesg;\n      wire [C_R_WIDTH-1:0] m_r_mesg;\n    \n      wire async_conv_reset_n;\n      assign async_conv_reset_n = ~(~s_axi_aresetn | ~m_axi_aresetn);\n      \n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_awlen           ;\n      wire [3-1:0]                       si_cc_awsize          ;\n      wire [2-1:0]                       si_cc_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_awlock          ;\n      wire [4-1:0]                       si_cc_awcache         ;\n      wire [3-1:0]                       si_cc_awprot          ;\n      wire [4-1:0]                       si_cc_awregion        ;\n      wire [4-1:0]                       si_cc_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]      si_cc_awuser          ;\n      wire                               si_cc_awvalid         ;\n      wire                               si_cc_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_wid            ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]      si_cc_wstrb           ;\n      wire                               si_cc_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]       si_cc_wuser           ;\n      wire                               si_cc_wvalid          ;\n      wire                               si_cc_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_bid             ;\n      wire [2-1:0]                       si_cc_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]       si_cc_buser           ;\n      wire                               si_cc_bvalid          ;\n      wire                               si_cc_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_arlen           ;\n      wire [3-1:0]                       si_cc_arsize          ;\n      wire [2-1:0]                       si_cc_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_arlock          ;\n      wire [4-1:0]                       si_cc_arcache         ;\n      wire [3-1:0]                       si_cc_arprot          ;\n      wire [4-1:0]                       si_cc_arregion        ;\n      wire [4-1:0]                       si_cc_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]      si_cc_aruser          ;\n      wire                               si_cc_arvalid         ;\n      wire                               si_cc_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_rdata           ;\n      wire [2-1:0]                       si_cc_rresp           ;\n      wire                               si_cc_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]       si_cc_ruser           ;\n      wire                               si_cc_rvalid          ;\n      wire                               si_cc_rready          ;\n      \n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_awlen           ;\n      wire [3-1:0]                      cc_mi_awsize          ;\n      wire [2-1:0]                      cc_mi_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_awlock          ;\n      wire [4-1:0]                      cc_mi_awcache         ;\n      wire [3-1:0]                      cc_mi_awprot          ;\n      wire [4-1:0]                      cc_mi_awregion        ;\n      wire [4-1:0]                      cc_mi_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]     cc_mi_awuser          ;\n      wire                              cc_mi_awvalid         ;\n      wire                              cc_mi_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_wid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]     cc_mi_wstrb           ;\n      wire                              cc_mi_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]      cc_mi_wuser           ;\n      wire                              cc_mi_wvalid          ;\n      wire                              cc_mi_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_bid             ;\n      wire [2-1:0]                      cc_mi_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]      cc_mi_buser           ;\n      wire                              cc_mi_bvalid          ;\n      wire                              cc_mi_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_arlen           ;\n      wire [3-1:0]                      cc_mi_arsize          ;\n      wire [2-1:0]                      cc_mi_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_arlock          ;\n      wire [4-1:0]                      cc_mi_arcache         ;\n      wire [3-1:0]                      cc_mi_arprot          ;\n      wire [4-1:0]                      cc_mi_arregion        ;\n      wire [4-1:0]                      cc_mi_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]     cc_mi_aruser          ;\n      wire                              cc_mi_arvalid         ;\n      wire                              cc_mi_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_rdata           ;\n      wire [2-1:0]                      cc_mi_rresp           ;\n      wire                              cc_mi_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]      cc_mi_ruser           ;\n      wire                              cc_mi_rvalid          ;\n      wire                              cc_mi_rready          ;\n      \n    // Tie-offs\n      assign si_cc_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awid : 0 ;\n      assign si_cc_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awaddr : 0 ;\n      assign si_cc_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_awlen : {4'b0000, s_axi_awlen[3:0]}) : 0 ;\n      assign si_cc_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize : 0 ;\n      assign si_cc_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst : 0 ;\n      assign si_cc_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_awlock : {1'b0, s_axi_awlock[0]}) : 0 ;\n      assign si_cc_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache : 0 ;\n      assign si_cc_awprot    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awprot : 0 ;\n      assign si_cc_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos : 0 ;\n      assign si_cc_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion : 0 ;\n      assign si_cc_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser : 0 ;\n      assign si_cc_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awvalid : 0 ;\n      assign si_cc_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? s_axi_wid : 0 ;\n      assign si_cc_wdata     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wdata : 0 ;\n      assign si_cc_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wstrb : 0 ;\n      assign si_cc_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast : 1'b0 ;\n      assign si_cc_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser : 0 ;\n      assign si_cc_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wvalid : 0 ;\n      assign si_cc_bready    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_bready : 0 ;\n      assign si_cc_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arid : 0 ;\n      assign si_cc_araddr    = (C_AXI_SUPPORTS_READ ) ? s_axi_araddr : 0 ;\n      assign si_cc_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_arlen : {4'b0000, s_axi_arlen[3:0]}) : 0 ;\n      assign si_cc_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize : 0 ;\n      assign si_cc_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst : 0 ;\n      assign si_cc_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_arlock : {1'b0, s_axi_arlock[0]}) : 0 ;\n      assign si_cc_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache : 0 ;\n      assign si_cc_arprot    = (C_AXI_SUPPORTS_READ ) ? s_axi_arprot : 0 ;\n      assign si_cc_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos : 0 ;\n      assign si_cc_arregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion : 0 ;\n      assign si_cc_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser : 0 ;\n      assign si_cc_arvalid   = (C_AXI_SUPPORTS_READ ) ? s_axi_arvalid : 0 ;\n      assign si_cc_rready    = (C_AXI_SUPPORTS_READ ) ? s_axi_rready : 0 ;                                       \n                                                                                               \n      assign s_axi_awready   = (C_AXI_SUPPORTS_WRITE ) ? si_cc_awready : 0 ;\n      assign s_axi_wready    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_wready : 0 ;\n      assign s_axi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_bid : 0 ;\n      assign s_axi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bresp : 0 ;\n      assign s_axi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_buser : 0 ;\n      assign s_axi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bvalid : 0 ;\n      assign s_axi_arready   = (C_AXI_SUPPORTS_READ ) ? si_cc_arready : 0 ;\n      assign s_axi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rid : 0 ;\n      assign s_axi_rdata     = (C_AXI_SUPPORTS_READ ) ? si_cc_rdata : 0 ;\n      assign s_axi_rresp     = (C_AXI_SUPPORTS_READ ) ? si_cc_rresp : 0 ;\n      assign s_axi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rlast : 0 ;\n      assign s_axi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_ruser : 0 ;\n      assign s_axi_rvalid    = (C_AXI_SUPPORTS_READ ) ? si_cc_rvalid : 0 ;\n\n      assign m_axi_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awid : 0 ;\n      assign m_axi_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awaddr : 0 ;\n      assign m_axi_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_awlen : cc_mi_awlen[3:0]) : 0 ;\n      assign m_axi_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awsize : 0 ;\n      assign m_axi_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awburst : 0 ;\n      assign m_axi_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_awlock : cc_mi_awlock[0]) : 0 ;\n      assign m_axi_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awcache : 0 ;\n      assign m_axi_awprot    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awprot : 0 ;\n      assign m_axi_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_awregion : 0 ;\n      assign m_axi_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awqos : 0 ;\n      assign m_axi_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_awuser : 0 ;\n      assign m_axi_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awvalid : 0 ;\n      assign m_axi_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? cc_mi_wid : 0 ;\n      assign m_axi_wdata     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wdata : 0 ;\n      assign m_axi_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wstrb : 0 ;\n      assign m_axi_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_wlast : 0 ;\n      assign m_axi_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_wuser : 0 ;\n      assign m_axi_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wvalid : 0 ;\n      assign m_axi_bready    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_bready : 0 ;\n      assign m_axi_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arid : 0 ;\n      assign m_axi_araddr    = (C_AXI_SUPPORTS_READ ) ? cc_mi_araddr : 0 ;\n      assign m_axi_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_arlen : cc_mi_arlen[3:0]) : 0 ;\n      assign m_axi_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arsize : 0 ;\n      assign m_axi_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arburst : 0 ;\n      assign m_axi_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_arlock : cc_mi_arlock[0]) : 0 ;\n      assign m_axi_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arcache : 0 ;\n      assign m_axi_arprot    = (C_AXI_SUPPORTS_READ ) ? cc_mi_arprot : 0 ;\n      assign m_axi_arregion  = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_arregion : 0 ;\n      assign m_axi_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arqos : 0 ;\n      assign m_axi_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_aruser : 0 ;\n      assign m_axi_arvalid   = (C_AXI_SUPPORTS_READ ) ? cc_mi_arvalid : 0 ;\n      assign m_axi_rready    = (C_AXI_SUPPORTS_READ ) ? cc_mi_rready : 0 ;\n                                                                                                                                                                                                                                                                                        \n      assign cc_mi_awready   = (C_AXI_SUPPORTS_WRITE ) ? m_axi_awready : 0 ;\n      assign cc_mi_wready    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_wready : 0 ;\n      assign cc_mi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid : 0 ;\n      assign cc_mi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bresp : 0 ;\n      assign cc_mi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser : 0 ;\n      assign cc_mi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bvalid : 0 ;\n      assign cc_mi_arready   = (C_AXI_SUPPORTS_READ ) ? m_axi_arready : 0 ;\n      assign cc_mi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid : 0 ;\n      assign cc_mi_rdata     = (C_AXI_SUPPORTS_READ ) ? m_axi_rdata : 0 ;\n      assign cc_mi_rresp     = (C_AXI_SUPPORTS_READ ) ? m_axi_rresp : 0 ;\n      assign cc_mi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast : 1'b0 ;\n      assign cc_mi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser : 0 ;\n      assign cc_mi_rvalid    = (C_AXI_SUPPORTS_READ ) ? m_axi_rvalid : 0 ;\n      \n      if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL!=P_AXILITE)) begin : gen_async_conv\n        \n        fifo_generator_v13_2_5 #(\n          .C_EN_SAFETY_CKT(0),\n          .C_SELECT_XPM(0),\n          .C_INTERFACE_TYPE(2),\n          .C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ? 3 : 2),\n          .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n          .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n          .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n          .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n          .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n          .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),\n          .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n          .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n          .C_HAS_AXI_ID((C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0),\n          .C_AXI_LEN_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 8 : 4),\n          .C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 1 : 2),\n          .C_HAS_AXI_ARUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_AWUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_BUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_RUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_WUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_DIN_WIDTH_RACH(C_FIFO_AR_WIDTH),\n          .C_DIN_WIDTH_RDCH(C_FIFO_R_WIDTH),\n          .C_DIN_WIDTH_WACH(C_FIFO_AW_WIDTH),\n          .C_DIN_WIDTH_WDCH(C_FIFO_W_WIDTH),\n          .C_DIN_WIDTH_WRCH(C_FIFO_B_WIDTH),\n          .C_HAS_AXI_RD_CHANNEL(C_AXI_SUPPORTS_READ),\n          .C_HAS_AXI_WR_CHANNEL(C_AXI_SUPPORTS_WRITE),\n          .C_RACH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_RDCH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_WACH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WDCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WRCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),\n          .C_COMMON_CLOCK(0),\n          .C_COUNT_TYPE(0),\n          .C_DATA_COUNT_WIDTH(10),\n          .C_DEFAULT_VALUE(\"BlankString\"),\n          .C_DIN_WIDTH(18),\n          .C_DOUT_RST_VAL(\"0\"),\n          .C_DOUT_WIDTH(18),\n          .C_ENABLE_RLOCS(0),\n          .C_FAMILY(C_FAMILY),\n          .C_FULL_FLAGS_RST_VAL(1),\n          .C_HAS_ALMOST_EMPTY(0),\n          .C_HAS_ALMOST_FULL(0),\n          .C_HAS_BACKUP(0),\n          .C_HAS_DATA_COUNT(0),\n          .C_HAS_INT_CLK(0),\n          .C_HAS_MEMINIT_FILE(0),\n          .C_HAS_OVERFLOW(0),\n          .C_HAS_RD_DATA_COUNT(0),\n          .C_HAS_RD_RST(0),\n          .C_HAS_RST(1),\n          .C_HAS_SRST(0),\n          .C_HAS_UNDERFLOW(0),\n          .C_HAS_VALID(0),\n          .C_HAS_WR_ACK(0),\n          .C_HAS_WR_DATA_COUNT(0),\n          .C_HAS_WR_RST(0),\n          .C_IMPLEMENTATION_TYPE(0),\n          .C_INIT_WR_PNTR_VAL(0),\n          .C_MEMORY_TYPE(1),\n          .C_MIF_FILE_NAME(\"BlankString\"),\n          .C_OPTIMIZATION_MODE(0),\n          .C_OVERFLOW_LOW(0),\n          .C_PRELOAD_LATENCY(1),\n          .C_PRELOAD_REGS(0),\n          .C_PRIM_FIFO_TYPE(\"4kx4\"),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),\n          .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),\n          .C_PROG_EMPTY_TYPE(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL(1022),\n          .C_PROG_FULL_THRESH_NEGATE_VAL(1021),\n          .C_PROG_FULL_TYPE(0),\n          .C_RD_DATA_COUNT_WIDTH(10),\n          .C_RD_DEPTH(1024),\n          .C_RD_FREQ(1),\n          .C_RD_PNTR_WIDTH(10),\n          .C_UNDERFLOW_LOW(0),\n          .C_USE_DOUT_RST(1),\n          .C_USE_ECC(0),\n          .C_USE_EMBEDDED_REG(0),\n          .C_USE_FIFO16_FLAGS(0),\n          .C_USE_FWFT_DATA_COUNT(0),\n          .C_VALID_LOW(0),\n          .C_WR_ACK_LOW(0),\n          .C_WR_DATA_COUNT_WIDTH(10),\n          .C_WR_DEPTH(1024),\n          .C_WR_FREQ(1),\n          .C_WR_PNTR_WIDTH(10),\n          .C_WR_RESPONSE_LATENCY(1),\n          .C_MSGON_VAL(1),\n          .C_ENABLE_RST_SYNC(1),\n          .C_ERROR_INJECTION_TYPE(0),\n          .C_HAS_SLAVE_CE(0),\n          .C_HAS_MASTER_CE(0),\n          .C_ADD_NGC_CONSTRAINT(0),\n          .C_USE_COMMON_OVERFLOW(0),\n          .C_USE_COMMON_UNDERFLOW(0),\n          .C_USE_DEFAULT_SETTINGS(0),\n          .C_HAS_AXIS_TDATA(1),\n          .C_HAS_AXIS_TID(0),\n          .C_HAS_AXIS_TDEST(0),\n          .C_HAS_AXIS_TUSER(1),\n          .C_HAS_AXIS_TREADY(1),\n          .C_HAS_AXIS_TLAST(0),\n          .C_HAS_AXIS_TSTRB(0),\n          .C_HAS_AXIS_TKEEP(0),\n          .C_AXIS_TDATA_WIDTH(8),\n          .C_AXIS_TID_WIDTH(1),\n          .C_AXIS_TDEST_WIDTH(1),\n          .C_AXIS_TUSER_WIDTH(4),\n          .C_AXIS_TSTRB_WIDTH(1),\n          .C_AXIS_TKEEP_WIDTH(1),\n          .C_AXIS_TYPE(0),\n          .C_IMPLEMENTATION_TYPE_WACH(12),\n          .C_IMPLEMENTATION_TYPE_WDCH(12),\n          .C_IMPLEMENTATION_TYPE_WRCH(12),\n          .C_IMPLEMENTATION_TYPE_RACH(12),\n          .C_IMPLEMENTATION_TYPE_RDCH(12),\n          .C_IMPLEMENTATION_TYPE_AXIS(11),\n          .C_APPLICATION_TYPE_WACH(0),\n          .C_APPLICATION_TYPE_WDCH(0),\n          .C_APPLICATION_TYPE_WRCH(0),\n          .C_APPLICATION_TYPE_RACH(0),\n          .C_APPLICATION_TYPE_RDCH(0),\n          .C_APPLICATION_TYPE_AXIS(0),\n          .C_USE_ECC_WACH(0),\n          .C_USE_ECC_WDCH(0),\n          .C_USE_ECC_WRCH(0),\n          .C_USE_ECC_RACH(0),\n          .C_USE_ECC_RDCH(0),\n          .C_USE_ECC_AXIS(0),\n          .C_ERROR_INJECTION_TYPE_WACH(0),\n          .C_ERROR_INJECTION_TYPE_WDCH(0),\n          .C_ERROR_INJECTION_TYPE_WRCH(0),\n          .C_ERROR_INJECTION_TYPE_RACH(0),\n          .C_ERROR_INJECTION_TYPE_RDCH(0),\n          .C_ERROR_INJECTION_TYPE_AXIS(0),\n          .C_DIN_WIDTH_AXIS(1),\n          .C_WR_DEPTH_WACH(16),\n          .C_WR_DEPTH_WDCH(16),\n          .C_WR_DEPTH_WRCH(16),\n          .C_WR_DEPTH_RACH(16),\n          .C_WR_DEPTH_RDCH(16),\n          .C_WR_DEPTH_AXIS(1024),\n          .C_WR_PNTR_WIDTH_WACH(4),\n          .C_WR_PNTR_WIDTH_WDCH(4),\n          .C_WR_PNTR_WIDTH_WRCH(4),\n          .C_WR_PNTR_WIDTH_RACH(4),\n          .C_WR_PNTR_WIDTH_RDCH(4),\n          .C_WR_PNTR_WIDTH_AXIS(10),\n          .C_HAS_DATA_COUNTS_WACH(0),\n          .C_HAS_DATA_COUNTS_WDCH(0),\n          .C_HAS_DATA_COUNTS_WRCH(0),\n          .C_HAS_DATA_COUNTS_RACH(0),\n          .C_HAS_DATA_COUNTS_RDCH(0),\n          .C_HAS_DATA_COUNTS_AXIS(0),\n          .C_HAS_PROG_FLAGS_WACH(0),\n          .C_HAS_PROG_FLAGS_WDCH(0),\n          .C_HAS_PROG_FLAGS_WRCH(0),\n          .C_HAS_PROG_FLAGS_RACH(0),\n          .C_HAS_PROG_FLAGS_RDCH(0),\n          .C_HAS_PROG_FLAGS_AXIS(0),\n          .C_PROG_FULL_TYPE_WACH(0),\n          .C_PROG_FULL_TYPE_WDCH(0),\n          .C_PROG_FULL_TYPE_WRCH(0),\n          .C_PROG_FULL_TYPE_RACH(0),\n          .C_PROG_FULL_TYPE_RDCH(0),\n          .C_PROG_FULL_TYPE_AXIS(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),\n          .C_PROG_EMPTY_TYPE_WACH(0),\n          .C_PROG_EMPTY_TYPE_WDCH(0),\n          .C_PROG_EMPTY_TYPE_WRCH(0),\n          .C_PROG_EMPTY_TYPE_RACH(0),\n          .C_PROG_EMPTY_TYPE_RDCH(0),\n          .C_PROG_EMPTY_TYPE_AXIS(0),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1021),\n          .C_REG_SLICE_MODE_WACH(0),\n          .C_REG_SLICE_MODE_WDCH(0),\n          .C_REG_SLICE_MODE_WRCH(0),\n          .C_REG_SLICE_MODE_RACH(0),\n          .C_REG_SLICE_MODE_RDCH(0),\n          .C_REG_SLICE_MODE_AXIS(0)\n          )\n          asyncfifo_axi (\n            .s_aclk(s_axi_aclk),\n            .m_aclk(m_axi_aclk),\n            .s_aresetn(async_conv_reset_n),\n            .s_axi_awid           (si_cc_awid),\n            .s_axi_awaddr         (si_cc_awaddr),\n            .s_axi_awlen          (si_cc_awlen),\n            .s_axi_awsize         (si_cc_awsize),\n            .s_axi_awburst        (si_cc_awburst),\n            .s_axi_awlock         (si_cc_awlock),\n            .s_axi_awcache        (si_cc_awcache),\n            .s_axi_awprot         (si_cc_awprot),\n            .s_axi_awqos          (si_cc_awqos),\n            .s_axi_awregion       (si_cc_awregion),\n            .s_axi_awuser         (si_cc_awuser),\n            .s_axi_awvalid        (si_cc_awvalid),\n            .s_axi_awready        (si_cc_awready),\n            .s_axi_wid            (si_cc_wid),\n            .s_axi_wdata          (si_cc_wdata),\n            .s_axi_wstrb          (si_cc_wstrb),\n            .s_axi_wlast          (si_cc_wlast),\n            .s_axi_wuser          (si_cc_wuser),\n            .s_axi_wvalid         (si_cc_wvalid),\n            .s_axi_wready         (si_cc_wready),\n            .s_axi_bid            (si_cc_bid),\n            .s_axi_bresp          (si_cc_bresp),\n            .s_axi_buser          (si_cc_buser),\n            .s_axi_bvalid         (si_cc_bvalid),\n            .s_axi_bready         (si_cc_bready),\n            .m_axi_awid           (cc_mi_awid),\n            .m_axi_awaddr         (cc_mi_awaddr),\n            .m_axi_awlen          (cc_mi_awlen),\n            .m_axi_awsize         (cc_mi_awsize),\n            .m_axi_awburst        (cc_mi_awburst),\n            .m_axi_awlock         (cc_mi_awlock),\n            .m_axi_awcache        (cc_mi_awcache),\n            .m_axi_awprot         (cc_mi_awprot),\n            .m_axi_awqos          (cc_mi_awqos),\n            .m_axi_awregion       (cc_mi_awregion),\n            .m_axi_awuser         (cc_mi_awuser),\n            .m_axi_awvalid        (cc_mi_awvalid),\n            .m_axi_awready        (cc_mi_awready),\n            .m_axi_wid            (cc_mi_wid),\n            .m_axi_wdata          (cc_mi_wdata),\n            .m_axi_wstrb          (cc_mi_wstrb),\n            .m_axi_wlast          (cc_mi_wlast),\n            .m_axi_wuser          (cc_mi_wuser),\n            .m_axi_wvalid         (cc_mi_wvalid),\n            .m_axi_wready         (cc_mi_wready),\n            .m_axi_bid            (cc_mi_bid),\n            .m_axi_bresp          (cc_mi_bresp),\n            .m_axi_buser          (cc_mi_buser),\n            .m_axi_bvalid         (cc_mi_bvalid),\n            .m_axi_bready         (cc_mi_bready),\n            .s_axi_arid           (si_cc_arid),\n            .s_axi_araddr         (si_cc_araddr),\n            .s_axi_arlen          (si_cc_arlen),\n            .s_axi_arsize         (si_cc_arsize),\n            .s_axi_arburst        (si_cc_arburst),\n            .s_axi_arlock         (si_cc_arlock),\n            .s_axi_arcache        (si_cc_arcache),\n            .s_axi_arprot         (si_cc_arprot),\n            .s_axi_arqos          (si_cc_arqos),\n            .s_axi_arregion       (si_cc_arregion),\n            .s_axi_aruser         (si_cc_aruser),\n            .s_axi_arvalid        (si_cc_arvalid),\n            .s_axi_arready        (si_cc_arready),\n            .s_axi_rid            (si_cc_rid),\n            .s_axi_rdata          (si_cc_rdata),\n            .s_axi_rresp          (si_cc_rresp),\n            .s_axi_rlast          (si_cc_rlast),\n            .s_axi_ruser          (si_cc_ruser),\n            .s_axi_rvalid         (si_cc_rvalid),\n            .s_axi_rready         (si_cc_rready),\n            .m_axi_arid           (cc_mi_arid),\n            .m_axi_araddr         (cc_mi_araddr),\n            .m_axi_arlen          (cc_mi_arlen),\n            .m_axi_arsize         (cc_mi_arsize),\n            .m_axi_arburst        (cc_mi_arburst),\n            .m_axi_arlock         (cc_mi_arlock),\n            .m_axi_arcache        (cc_mi_arcache),\n            .m_axi_arprot         (cc_mi_arprot),\n            .m_axi_arqos          (cc_mi_arqos),\n            .m_axi_arregion       (cc_mi_arregion),\n            .m_axi_aruser         (cc_mi_aruser),\n            .m_axi_arvalid        (cc_mi_arvalid),\n            .m_axi_arready        (cc_mi_arready),\n            .m_axi_rid            (cc_mi_rid),\n            .m_axi_rdata          (cc_mi_rdata),\n            .m_axi_rresp          (cc_mi_rresp),\n            .m_axi_rlast          (cc_mi_rlast),\n            .m_axi_ruser          (cc_mi_ruser),\n            .m_axi_rvalid         (cc_mi_rvalid),\n            .m_axi_rready         (cc_mi_rready),\n            .m_aclk_en(1'b1),\n            .s_aclk_en(1'b1),\n            .almost_empty(),\n            .almost_full(),\n            .axis_data_count(),\n            .axis_dbiterr(),\n            .axis_injectdbiterr(1'b0),\n            .axis_injectsbiterr(1'b0),\n            .axis_overflow(),\n            .axis_prog_empty(),\n            .axis_prog_empty_thresh(10'b0),\n            .axis_prog_full(),\n            .axis_prog_full_thresh(10'b0),\n            .axis_rd_data_count(),\n            .axis_sbiterr(),\n            .axis_underflow(),\n            .axis_wr_data_count(),\n            .axi_ar_data_count(),\n            .axi_ar_dbiterr(),\n            .axi_ar_injectdbiterr(1'b0),\n            .axi_ar_injectsbiterr(1'b0),\n            .axi_ar_overflow(),\n            .axi_ar_prog_empty(),\n            .axi_ar_prog_empty_thresh(4'b0),\n            .axi_ar_prog_full(),\n            .axi_ar_prog_full_thresh(4'b0),\n            .axi_ar_rd_data_count(),\n            .axi_ar_sbiterr(),\n            .axi_ar_underflow(),\n            .axi_ar_wr_data_count(),\n            .axi_aw_data_count(),\n            .axi_aw_dbiterr(),\n            .axi_aw_injectdbiterr(1'b0),\n            .axi_aw_injectsbiterr(1'b0),\n            .axi_aw_overflow(),\n            .axi_aw_prog_empty(),\n            .axi_aw_prog_empty_thresh(4'b0),\n            .axi_aw_prog_full(),\n            .axi_aw_prog_full_thresh(4'b0),\n            .axi_aw_rd_data_count(),\n            .axi_aw_sbiterr(),\n            .axi_aw_underflow(),\n            .axi_aw_wr_data_count(),\n            .axi_b_data_count(),\n            .axi_b_dbiterr(),\n            .axi_b_injectdbiterr(1'b0),\n            .axi_b_injectsbiterr(1'b0),\n            .axi_b_overflow(),\n            .axi_b_prog_empty(),\n            .axi_b_prog_empty_thresh(4'b0),\n            .axi_b_prog_full(),\n            .axi_b_prog_full_thresh(4'b0),\n            .axi_b_rd_data_count(),\n            .axi_b_sbiterr(),\n            .axi_b_underflow(),\n            .axi_b_wr_data_count(),\n            .axi_r_data_count(),\n            .axi_r_dbiterr(),\n            .axi_r_injectdbiterr(1'b0),\n            .axi_r_injectsbiterr(1'b0),\n            .axi_r_overflow(),\n            .axi_r_prog_empty(),\n            .axi_r_prog_empty_thresh(4'b0),\n            .axi_r_prog_full(),\n            .axi_r_prog_full_thresh(4'b0),\n            .axi_r_rd_data_count(),\n            .axi_r_sbiterr(),\n            .axi_r_underflow(),\n            .axi_r_wr_data_count(),\n            .axi_w_data_count(),\n            .axi_w_dbiterr(),\n            .axi_w_injectdbiterr(1'b0),\n            .axi_w_injectsbiterr(1'b0),\n            .axi_w_overflow(),\n            .axi_w_prog_empty(),\n            .axi_w_prog_empty_thresh(4'b0),\n            .axi_w_prog_full(),\n            .axi_w_prog_full_thresh(4'b0),\n            .axi_w_rd_data_count(),\n            .axi_w_sbiterr(),\n            .axi_w_underflow(),\n            .axi_w_wr_data_count(),\n            .backup(1'b0),\n            .backup_marker(1'b0),\n            .clk(1'b0),\n            .data_count(),\n            .dbiterr(),\n            .din(18'b0),\n            .dout(),\n            .empty(),\n            .full(),\n            .injectdbiterr(1'b0),\n            .injectsbiterr(1'b0),\n            .int_clk(1'b0),\n            .m_axis_tdata(),\n            .m_axis_tdest(),\n            .m_axis_tid(),\n            .m_axis_tkeep(),\n            .m_axis_tlast(),\n            .m_axis_tready(1'b0),\n            .m_axis_tstrb(),\n            .m_axis_tuser(),\n            .m_axis_tvalid(),\n            .overflow(),\n            .prog_empty(),\n            .prog_empty_thresh(10'b0),\n            .prog_empty_thresh_assert(10'b0),\n            .prog_empty_thresh_negate(10'b0),\n            .prog_full(),\n            .prog_full_thresh(10'b0),\n            .prog_full_thresh_assert(10'b0),\n            .prog_full_thresh_negate(10'b0),\n            .rd_clk(1'b0),\n            .rd_data_count(),\n            .rd_en(1'b0),\n            .rd_rst(1'b0),\n            .rst(1'b0),\n            .sbiterr(),\n            .srst(1'b0),\n            .s_axis_tdata(8'b0),\n            .s_axis_tdest(1'b0),\n            .s_axis_tid(1'b0),\n            .s_axis_tkeep(1'b0),\n            .s_axis_tlast(1'b0),\n            .s_axis_tready(),\n            .s_axis_tstrb(1'b0),\n            .s_axis_tuser(4'b0),\n            .s_axis_tvalid(1'b0),\n            .underflow(),\n            .valid(),\n            .wr_ack(),\n            .wr_clk(1'b0),\n            .wr_data_count(),\n            .wr_en(1'b0),\n            .wr_rst(1'b0),\n            .wr_rst_busy(),\n            .rd_rst_busy(),\n            .sleep(1'b0)\n        );\n      end else if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_async_lite_conv\n        localparam C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n        `include \"axi_infrastructure_v1_1_0.vh\"\n\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n        axi_infrastructure_v1_1_0_axi2vector #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        axi2vec ( \n          .s_axi_awid      ( si_cc_awid      ) ,\n          .s_axi_awaddr    ( si_cc_awaddr    ) ,\n          .s_axi_awlen     ( s_axi_awlen     ) ,\n          .s_axi_awsize    ( si_cc_awsize    ) ,\n          .s_axi_awburst   ( si_cc_awburst   ) ,\n          .s_axi_awlock    ( s_axi_awlock    ) ,\n          .s_axi_awcache   ( si_cc_awcache   ) ,\n          .s_axi_awprot    ( si_cc_awprot    ) ,\n          .s_axi_awqos     ( si_cc_awqos     ) ,\n          .s_axi_awuser    ( si_cc_awuser    ) ,\n          .s_axi_awregion  ( si_cc_awregion  ) ,\n          .s_axi_wid       ( si_cc_wid       ) ,\n          .s_axi_wdata     ( si_cc_wdata     ) ,\n          .s_axi_wstrb     ( si_cc_wstrb     ) ,\n          .s_axi_wlast     ( si_cc_wlast     ) ,\n          .s_axi_wuser     ( si_cc_wuser     ) ,\n          .s_axi_bid       ( si_cc_bid       ) ,\n          .s_axi_bresp     ( si_cc_bresp     ) ,\n          .s_axi_buser     ( si_cc_buser     ) ,\n          .s_axi_arid      ( si_cc_arid      ) ,\n          .s_axi_araddr    ( si_cc_araddr    ) ,\n          .s_axi_arlen     ( s_axi_arlen     ) ,\n          .s_axi_arsize    ( si_cc_arsize    ) ,\n          .s_axi_arburst   ( si_cc_arburst   ) ,\n          .s_axi_arlock    ( s_axi_arlock    ) ,\n          .s_axi_arcache   ( si_cc_arcache   ) ,\n          .s_axi_arprot    ( si_cc_arprot    ) ,\n          .s_axi_arqos     ( si_cc_arqos     ) ,\n          .s_axi_aruser    ( si_cc_aruser    ) ,\n          .s_axi_arregion  ( si_cc_arregion  ) ,\n          .s_axi_rid       ( si_cc_rid       ) ,\n          .s_axi_rdata     ( si_cc_rdata     ) ,\n          .s_axi_rresp     ( si_cc_rresp     ) ,\n          .s_axi_rlast     ( si_cc_rlast     ) ,\n          .s_axi_ruser     ( si_cc_ruser     ) ,\n          .s_awpayload     ( s_awpayload ) ,\n          .s_wpayload      ( s_wpayload  ) ,\n          .s_bpayload      ( s_bpayload  ) ,\n          .s_arpayload     ( s_arpayload ) ,\n          .s_rpayload      ( s_rpayload  ) \n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_AWPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_aw (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_awvalid),\n          .s_ready  (si_cc_awready),\n          .s_payld  (s_awpayload),\n          .m_valid  (cc_mi_awvalid),\n          .m_ready  (cc_mi_awready),\n          .m_payld  (m_awpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_ARPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_ar (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_arvalid),\n          .s_ready  (si_cc_arready),\n          .s_payld  (s_arpayload),\n          .m_valid  (cc_mi_arvalid),\n          .m_ready  (cc_mi_arready),\n          .m_payld  (m_arpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_WPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_w (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_wvalid),\n          .s_ready  (si_cc_wready),\n          .s_payld  (s_wpayload),\n          .m_valid  (cc_mi_wvalid),\n          .m_ready  (cc_mi_wready),\n          .m_payld  (m_wpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_BPAYLOAD_WIDTH)\n        ) clock_conv_lite_resp_b (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_bvalid),\n          .s_ready  (cc_mi_bready),\n          .s_payld  (m_bpayload),\n          .m_valid  (si_cc_bvalid),\n          .m_ready  (si_cc_bready),\n          .m_payld  (s_bpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_RPAYLOAD_WIDTH)\n        ) clock_conv_lite_resp_r (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_rvalid),\n          .s_ready  (cc_mi_rready),\n          .s_payld  (m_rpayload),\n          .m_valid  (si_cc_rvalid),\n          .m_ready  (si_cc_rready),\n          .m_payld  (s_rpayload)\n        );\n\n        axi_infrastructure_v1_1_0_vector2axi #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        vec2axi ( \n          .m_awpayload    ( m_awpayload    ) ,\n          .m_wpayload     ( m_wpayload     ) ,\n          .m_bpayload     ( m_bpayload     ) ,\n          .m_arpayload    ( m_arpayload    ) ,\n          .m_rpayload     ( m_rpayload     ) ,\n          .m_axi_awid     ( cc_mi_awid     ) ,\n          .m_axi_awaddr   ( cc_mi_awaddr   ) ,\n          .m_axi_awlen    ( cc_mi_awlen    ) ,\n          .m_axi_awsize   ( cc_mi_awsize   ) ,\n          .m_axi_awburst  ( cc_mi_awburst  ) ,\n          .m_axi_awlock   ( cc_mi_awlock   ) ,\n          .m_axi_awcache  ( cc_mi_awcache  ) ,\n          .m_axi_awprot   ( cc_mi_awprot   ) ,\n          .m_axi_awqos    ( cc_mi_awqos    ) ,\n          .m_axi_awuser   ( cc_mi_awuser   ) ,\n          .m_axi_awregion ( cc_mi_awregion ) ,\n          .m_axi_wid      ( cc_mi_wid      ) ,\n          .m_axi_wdata    ( cc_mi_wdata    ) ,\n          .m_axi_wstrb    ( cc_mi_wstrb    ) ,\n          .m_axi_wlast    ( cc_mi_wlast    ) ,\n          .m_axi_wuser    ( cc_mi_wuser    ) ,\n          .m_axi_bid      ( cc_mi_bid      ) ,\n          .m_axi_bresp    ( cc_mi_bresp    ) ,\n          .m_axi_buser    ( cc_mi_buser    ) ,\n          .m_axi_arid     ( cc_mi_arid     ) ,\n          .m_axi_araddr   ( cc_mi_araddr   ) ,\n          .m_axi_arlen    ( cc_mi_arlen    ) ,\n          .m_axi_arsize   ( cc_mi_arsize   ) ,\n          .m_axi_arburst  ( cc_mi_arburst  ) ,\n          .m_axi_arlock   ( cc_mi_arlock   ) ,\n          .m_axi_arcache  ( cc_mi_arcache  ) ,\n          .m_axi_arprot   ( cc_mi_arprot   ) ,\n          .m_axi_arqos    ( cc_mi_arqos    ) ,\n          .m_axi_aruser   ( cc_mi_aruser   ) ,\n          .m_axi_arregion ( cc_mi_arregion ) ,\n          .m_axi_rid      ( cc_mi_rid      ) ,\n          .m_axi_rdata    ( cc_mi_rdata    ) ,\n          .m_axi_rresp    ( cc_mi_rresp    ) ,\n          .m_axi_rlast    ( cc_mi_rlast    ) ,\n          .m_axi_ruser    ( cc_mi_ruser    ) \n        );\n\n      end else begin : gen_sync_conv\n        \n        assign {fast_aclk, slow_aclk} = P_SI_LT_MI ? {m_axi_aclk, s_axi_aclk} : {s_axi_aclk, m_axi_aclk};\n    \n        // Sample cycle used to determine when to assert a signal on a fast clock\n        // to be flopped onto a slow clock.\n        axi_clock_converter_v2_1_21_axic_sample_cycle_ratio #(\n          .C_RATIO ( P_ACLK_RATIO )\n        )\n        axic_sample_cycle_inst (\n          .SLOW_ACLK          ( slow_aclk               ) ,\n          .FAST_ACLK          ( fast_aclk               ) ,\n          .SAMPLE_CYCLE_EARLY ( sample_cycle_early ) ,\n          .SAMPLE_CYCLE       ( sample_cycle       )\n        );\n    \n      ////////////////////////////////////////////////////////////////////////////////\n      // AXI write channels\n      ////////////////////////////////////////////////////////////////////////////////\n        if (C_AXI_SUPPORTS_WRITE) begin : gen_conv_write_ch\n    \n          // Write Address Port\n          assign s_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH]     = si_cc_awaddr   ;\n          assign s_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH]     = si_cc_awprot   ;\n          assign cc_mi_awaddr   = m_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH];\n          assign cc_mi_awprot   = m_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_aw_axi4\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen    ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock[0] ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH] = si_cc_awregion ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awregion = m_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_aw_axi3\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen[3:0] ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock   ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_aw_user\n            assign s_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH]  = si_cc_awuser;\n            assign cc_mi_awuser = m_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AW_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          aw_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_aw_mesg ) ,\n            .S_VALID   ( si_cc_awvalid   ) ,\n            .S_READY   ( si_cc_awready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_aw_mesg ) ,\n            .M_VALID   ( cc_mi_awvalid   ) ,\n            .M_READY   ( cc_mi_awready   )\n          );\n    \n          // Write Data Port\n          assign s_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH] = si_cc_wdata; \n          assign s_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH] = si_cc_wstrb; \n          assign cc_mi_wdata    = m_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH];\n          assign cc_mi_wstrb    = m_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_w_axi4\n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_w_axi3\n            assign s_w_mesg[C_WID_RIGHT+:C_WID_WIDTH]     = si_cc_wid; \n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wid      = m_w_mesg[C_WID_RIGHT+:C_WID_WIDTH];\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_w_user\n            assign s_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH]  = si_cc_wuser;\n            assign cc_mi_wuser = m_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH  ( C_W_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE           ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          w_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_w_mesg ) ,\n            .S_VALID   ( si_cc_wvalid   ) ,\n            .S_READY   ( si_cc_wready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_w_mesg ) ,\n            .M_VALID   ( cc_mi_wvalid   ) ,\n            .M_READY   ( cc_mi_wready   )\n          );\n    \n          // Write Response Port\n          assign m_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH] = cc_mi_bresp;\n          assign si_cc_bresp    = s_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_b_axi\n            assign m_b_mesg[C_BID_RIGHT+:C_BID_WIDTH]     = cc_mi_bid;\n            assign si_cc_bid      = s_b_mesg[C_BID_RIGHT+:C_BID_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_b_user\n            assign m_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH] = cc_mi_buser;\n            assign si_cc_buser  = s_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_B_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          b_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_b_mesg ) ,\n            .S_VALID   ( cc_mi_bvalid   ) ,\n            .S_READY   ( cc_mi_bready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_b_mesg ) ,\n            .M_VALID   ( si_cc_bvalid   ) ,\n            .M_READY   ( si_cc_bready   )\n          );\n    \n        end else begin : gen_tieoff_write_ch\n    \n          // Write address port\n          assign cc_mi_awid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_awaddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_awlen    = {8{1'b0}};\n          assign cc_mi_awsize   = {3{1'b0}};\n          assign cc_mi_awburst  = {2{1'b0}};\n          assign cc_mi_awlock   = {2{1'b0}};\n          assign cc_mi_awcache  = {4{1'b0}};\n          assign cc_mi_awprot   = {3{1'b0}};\n          assign cc_mi_awregion = {4{1'b0}};\n          assign cc_mi_awqos    = {4{1'b0}};\n          assign cc_mi_awuser   = {C_AXI_AWUSER_WIDTH{1'b0}};\n          assign cc_mi_awvalid  = 1'b0;\n          assign si_cc_awready  = 1'b0;\n    \n          // Write data port\n          assign cc_mi_wid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_wdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign cc_mi_wstrb    = {C_AXI_DATA_WIDTH/8{1'b0}};\n          assign cc_mi_wlast    = 1'b0;\n          assign cc_mi_wuser    = {C_AXI_WUSER_WIDTH{1'b0}};\n          assign cc_mi_wvalid   = 1'b0;\n          assign si_cc_wready   = 1'b0;\n    \n          // Write response port\n          assign si_cc_bid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_bresp    = {2{1'b0}};\n          assign si_cc_buser    = {C_AXI_BUSER_WIDTH{1'b0}};\n          assign si_cc_bvalid   = 1'b0;\n          assign cc_mi_bready   = 1'b0;\n        end\n    \n        ////////////////////////////////////////////////////////////////////////////////\n        // AXI read channels\n        ////////////////////////////////////////////////////////////////////////////////\n    \n        if (C_AXI_SUPPORTS_READ) begin : gen_conv_read_ch\n    \n          // Read Address Port\n          assign s_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH]     = si_cc_araddr   ;\n          assign s_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH]     = si_cc_arprot   ;\n          assign cc_mi_araddr   = m_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH];\n          assign cc_mi_arprot   = m_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_ar_axi4\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen    ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock[0] ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH] = si_cc_arregion ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arregion = m_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_ar_axi3\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen[3:0] ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock   ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_ar_user\n            assign s_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH]  = si_cc_aruser;\n            assign cc_mi_aruser = m_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AR_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          ar_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_ar_mesg ) ,\n            .S_VALID   ( si_cc_arvalid   ) ,\n            .S_READY   ( si_cc_arready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN  ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_ar_mesg ) ,\n            .M_VALID   ( cc_mi_arvalid   ) ,\n            .M_READY   ( cc_mi_arready   )\n          );\n    \n          // Read Data Port\n          assign m_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH] = cc_mi_rdata; \n          assign m_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH] = cc_mi_rresp; \n          assign si_cc_rdata    = s_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH];\n          assign si_cc_rresp    = s_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_r_axi\n            assign m_r_mesg[C_RID_RIGHT+:C_RID_WIDTH]     = cc_mi_rid;   \n            assign m_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH] = cc_mi_rlast;\n            assign si_cc_rid      = s_r_mesg[C_RID_RIGHT+:C_RID_WIDTH];\n            assign si_cc_rlast    = s_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_r_user\n            assign m_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH] = cc_mi_ruser;\n            assign si_cc_ruser  = s_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_R_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          r_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_r_mesg ) ,\n            .S_VALID   ( cc_mi_rvalid   ) ,\n            .S_READY   ( cc_mi_rready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_r_mesg ) ,\n            .M_VALID   ( si_cc_rvalid   ) ,\n            .M_READY   ( si_cc_rready   )\n          );\n    \n        end else begin : gen_tieoff_read_ch\n    \n          // Read Address Port\n          assign cc_mi_arid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_araddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_arlen    = {8{1'b0}};\n          assign cc_mi_arsize   = {3{1'b0}};\n          assign cc_mi_arburst  = {2{1'b0}};\n          assign cc_mi_arlock   = {2{1'b0}};\n          assign cc_mi_arcache  = {4{1'b0}};\n          assign cc_mi_arprot   = {3{1'b0}};\n          assign cc_mi_arregion = {4{1'b0}};\n          assign cc_mi_arqos    = {4{1'b0}};\n          assign cc_mi_aruser   = {C_AXI_ARUSER_WIDTH{1'b0}};\n          assign cc_mi_arvalid  = 1'b0;\n          assign si_cc_arready  = 1'b0;\n    \n          // Read data port\n          assign si_cc_rid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_rdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign si_cc_rresp    = {2{1'b0}};\n          assign si_cc_rlast    = 1'b0;\n          assign si_cc_ruser    = {C_AXI_RUSER_WIDTH{1'b0}};\n          assign si_cc_rvalid   = 1'b0;\n          assign cc_mi_rready   = 1'b0;\n        end\n      end\n    end\n\n  endgenerate\n\nendmodule\n\n\n\n", "num_lines": 2178}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1\n// IP Revision: 21\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_clock_converter_0 (\n  s_axi_aclk,\n  s_axi_aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awuser,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_aruser,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_aclk,\n  m_axi_aresetn,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awuser,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_aruser,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_CLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 SI_CLK CLK\" *)\ninput wire s_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 SI_RST RST\" *)\ninput wire s_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWUSER\" *)\ninput wire [18 : 0] s_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARUSER\" *)\ninput wire [18 : 0] s_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 19, ARUSER_WIDTH 19, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUS\\\nER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_CLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 MI_CLK CLK\" *)\ninput wire m_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 MI_RST RST\" *)\ninput wire m_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWUSER\" *)\noutput wire [18 : 0] m_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARUSER\" *)\noutput wire [18 : 0] m_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 19, ARUSER_WIDTH 19, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUS\\\nER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_clock_converter_v2_1_21_axi_clock_converter #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_S_AXI_ACLK_RATIO(1),\n    .C_M_AXI_ACLK_RATIO(2),\n    .C_AXI_IS_ACLK_ASYNC(1),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_SUPPORTS_USER_SIGNALS(1),\n    .C_AXI_AWUSER_WIDTH(19),\n    .C_AXI_ARUSER_WIDTH(19),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_AXI_SUPPORTS_WRITE(1),\n    .C_AXI_SUPPORTS_READ(1),\n    .C_SYNCHRONIZER_STAGE(2)\n  ) inst (\n    .s_axi_aclk(s_axi_aclk),\n    .s_axi_aresetn(s_axi_aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(s_axi_awuser),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(s_axi_aruser),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_aclk(m_axi_aclk),\n    .m_axi_aresetn(m_axi_aresetn),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(m_axi_awuser),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(m_axi_aruser),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 441}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/*\n *******************************************************************************\n *\n * FIFO Generator - Verilog Behavioral Model\n *\n *******************************************************************************\n *\n * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.\n *\n * This file contains confidential and proprietary information\n * of Xilinx, Inc. and is protected under U.S. and\n * international copyright and other intellectual property\n * laws.\n *\n * DISCLAIMER\n * This disclaimer is not a license and does not grant any\n * rights to the materials distributed herewith. Except as\n * otherwise provided in a valid license issued to you by\n * Xilinx, and to the maximum extent permitted by applicable\n * law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n * (2) Xilinx shall not be liable (whether in contract or tort,\n * including negligence, or under any other theory of\n * liability) for any loss or damage of any kind or nature\n * related to, arising under or in connection with these\n * materials, including for any direct, or any indirect,\n * special, incidental, or consequential loss or damage\n * (including loss of data, profits, goodwill, or any type of\n * loss or damage suffered as a result of any action brought\n * by a third party) even if such damage or loss was\n * reasonably foreseeable or Xilinx had been advised of the\n * possibility of the same.\n *\n * CRITICAL APPLICATIONS\n * Xilinx products are not designed or intended to be fail-\n * safe, or for use in any application requiring fail-safe\n * performance, such as life-support or safety devices or\n * systems, Class III medical devices, nuclear facilities,\n * applications related to the deployment of airbags, or any\n * other applications that could lead to death, personal\n * injury, or severe property or environmental damage\n * (individually and collectively, \"Critical\n * Applications\"). Customer assumes the sole risk and\n * liability of any use of Xilinx products in Critical\n * Applications, subject only to applicable laws and\n * regulations governing limitations on product liability.\n *\n * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n * PART OF THIS FILE AT ALL TIMES.\n *\n *******************************************************************************\n *******************************************************************************\n *\n * Filename: fifo_generator_vlog_beh.v\n *\n * Author     : Xilinx\n *\n *******************************************************************************\n * Structure:\n * \n * fifo_generator_vlog_beh.v\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_as\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_ss\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_preload0\n * \n *******************************************************************************\n * Description:\n *\n * The Verilog behavioral model for the FIFO Generator.\n *\n *   The behavioral model has three parts:\n *      - The behavioral model for independent clocks FIFOs (_as)\n *      - The behavioral model for common clock FIFOs (_ss)\n *      - The \"preload logic\" block which implements First-word Fall-through\n * \n *******************************************************************************\n * Description:\n *  The verilog behavioral model for the FIFO generator core.\n *\n *******************************************************************************\n */\n\n`timescale 1ps/1ps\n`ifndef TCQ\n `define TCQ 100\n`endif\n\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_vlog_beh\n  #(\n    //-----------------------------------------------------------------------\n    // Generic Declarations\n    //-----------------------------------------------------------------------\n    parameter C_COMMON_CLOCK                 = 0,\n    parameter C_COUNT_TYPE                   = 0,\n    parameter C_DATA_COUNT_WIDTH             = 2,\n    parameter C_DEFAULT_VALUE                = \"\",\n    parameter C_DIN_WIDTH                    = 8,\n    parameter C_DOUT_RST_VAL                 = \"\",\n    parameter C_DOUT_WIDTH                   = 8,\n    parameter C_ENABLE_RLOCS                 = 0,\n    parameter C_FAMILY                       = \"\",\n    parameter C_FULL_FLAGS_RST_VAL           = 1,\n    parameter C_HAS_ALMOST_EMPTY             = 0,\n    parameter C_HAS_ALMOST_FULL              = 0,\n    parameter C_HAS_BACKUP                   = 0,\n    parameter C_HAS_DATA_COUNT               = 0,\n    parameter C_HAS_INT_CLK                  = 0,\n    parameter C_HAS_MEMINIT_FILE             = 0,\n    parameter C_HAS_OVERFLOW                 = 0,\n    parameter C_HAS_RD_DATA_COUNT            = 0,\n    parameter C_HAS_RD_RST                   = 0,\n    parameter C_HAS_RST                      = 1,\n    parameter C_HAS_SRST                     = 0,\n    parameter C_HAS_UNDERFLOW                = 0,\n    parameter C_HAS_VALID                    = 0,\n    parameter C_HAS_WR_ACK                   = 0,\n    parameter C_HAS_WR_DATA_COUNT            = 0,\n    parameter C_HAS_WR_RST                   = 0,\n    parameter C_IMPLEMENTATION_TYPE          = 0,\n    parameter C_INIT_WR_PNTR_VAL             = 0,\n    parameter C_MEMORY_TYPE                  = 1,\n    parameter C_MIF_FILE_NAME                = \"\",\n    parameter C_OPTIMIZATION_MODE            = 0,\n    parameter C_OVERFLOW_LOW                 = 0,\n    parameter C_EN_SAFETY_CKT                = 0,\n    parameter C_PRELOAD_LATENCY              = 1,\n    parameter C_PRELOAD_REGS                 = 0,\n    parameter C_PRIM_FIFO_TYPE               = \"4kx4\",\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter C_PROG_EMPTY_TYPE              = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter C_PROG_FULL_TYPE               = 0,\n    parameter C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter C_RD_DEPTH                     = 256,\n    parameter C_RD_FREQ                      = 1,\n    parameter C_RD_PNTR_WIDTH                = 8,\n    parameter C_UNDERFLOW_LOW                = 0,\n    parameter C_USE_DOUT_RST                 = 0,\n    parameter C_USE_ECC                      = 0,\n    parameter C_USE_EMBEDDED_REG             = 0,\n    parameter C_USE_PIPELINE_REG             = 0,\n    parameter C_POWER_SAVING_MODE            = 0,\n    parameter C_USE_FIFO16_FLAGS             = 0,\n    parameter C_USE_FWFT_DATA_COUNT          = 0,\n    parameter C_VALID_LOW                    = 0,\n    parameter C_WR_ACK_LOW                   = 0,\n    parameter C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter C_WR_DEPTH                     = 256,\n    parameter C_WR_FREQ                      = 1,\n    parameter C_WR_PNTR_WIDTH                = 8,\n    parameter C_WR_RESPONSE_LATENCY          = 1,\n    parameter C_MSGON_VAL                    = 1,\n    parameter C_ENABLE_RST_SYNC              = 1,\n    parameter C_ERROR_INJECTION_TYPE         = 0,\n    parameter C_SYNCHRONIZER_STAGE           = 2,\n\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE               = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3\n    parameter C_AXI_TYPE                     = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3\n    parameter C_HAS_AXI_WR_CHANNEL           = 0,\n    parameter C_HAS_AXI_RD_CHANNEL           = 0,\n    parameter C_HAS_SLAVE_CE                 = 0,\n    parameter C_HAS_MASTER_CE                = 0,\n    parameter C_ADD_NGC_CONSTRAINT           = 0,\n    parameter C_USE_COMMON_UNDERFLOW         = 0,\n    parameter C_USE_COMMON_OVERFLOW          = 0,\n    parameter C_USE_DEFAULT_SETTINGS         = 0,\n\n    // AXI Full/Lite\n    parameter C_AXI_ID_WIDTH                 = 0,\n    parameter C_AXI_ADDR_WIDTH               = 0,\n    parameter C_AXI_DATA_WIDTH               = 0,\n    parameter C_AXI_LEN_WIDTH                = 8,\n    parameter C_AXI_LOCK_WIDTH               = 2,\n    parameter C_HAS_AXI_ID                   = 0,\n    parameter C_HAS_AXI_AWUSER               = 0,\n    parameter C_HAS_AXI_WUSER                = 0,\n    parameter C_HAS_AXI_BUSER                = 0,\n    parameter C_HAS_AXI_ARUSER               = 0,\n    parameter C_HAS_AXI_RUSER                = 0,\n    parameter C_AXI_ARUSER_WIDTH             = 0,\n    parameter C_AXI_AWUSER_WIDTH             = 0,\n    parameter C_AXI_WUSER_WIDTH              = 0,\n    parameter C_AXI_BUSER_WIDTH              = 0,\n    parameter C_AXI_RUSER_WIDTH              = 0,\n\n    // AXI Streaming\n    parameter C_HAS_AXIS_TDATA               = 0,\n    parameter C_HAS_AXIS_TID                 = 0,\n    parameter C_HAS_AXIS_TDEST               = 0,\n    parameter C_HAS_AXIS_TUSER               = 0,\n    parameter C_HAS_AXIS_TREADY              = 0,\n    parameter C_HAS_AXIS_TLAST               = 0,\n    parameter C_HAS_AXIS_TSTRB               = 0,\n    parameter C_HAS_AXIS_TKEEP               = 0,\n    parameter C_AXIS_TDATA_WIDTH             = 1,\n    parameter C_AXIS_TID_WIDTH               = 1,\n    parameter C_AXIS_TDEST_WIDTH             = 1,\n    parameter C_AXIS_TUSER_WIDTH             = 1,\n    parameter C_AXIS_TSTRB_WIDTH             = 1,\n    parameter C_AXIS_TKEEP_WIDTH             = 1,\n\n    // AXI Channel Type\n    // WACH --> Write Address Channel\n    // WDCH --> Write Data Channel\n    // WRCH --> Write Response Channel\n    // RACH --> Read Address Channel\n    // RDCH --> Read Data Channel\n    // AXIS --> AXI Streaming\n    parameter C_WACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic\n    parameter C_WDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_WRCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_AXIS_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n\n    // AXI Implementation Type\n    // 1 = Common Clock Block RAM FIFO\n    // 2 = Common Clock Distributed RAM FIFO\n    // 11 = Independent Clock Block RAM FIFO\n    // 12 = Independent Clock Distributed RAM FIFO\n    parameter C_IMPLEMENTATION_TYPE_WACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WRCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_AXIS     = 0,\n\n    // AXI FIFO Type\n    // 0 = Data FIFO\n    // 1 = Packet FIFO\n    // 2 = Low Latency Sync FIFO\n    // 3 = Low Latency Async FIFO\n    parameter C_APPLICATION_TYPE_WACH        = 0,\n    parameter C_APPLICATION_TYPE_WDCH        = 0,\n    parameter C_APPLICATION_TYPE_WRCH        = 0,\n    parameter C_APPLICATION_TYPE_RACH        = 0,\n    parameter C_APPLICATION_TYPE_RDCH        = 0,\n    parameter C_APPLICATION_TYPE_AXIS        = 0,\n\n    // AXI Built-in FIFO Primitive Type\n    // 512x36, 1kx18, 2kx9, 4kx4, etc\n    parameter C_PRIM_FIFO_TYPE_WACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WRCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_AXIS          = \"512x36\",\n\n    // Enable ECC\n    // 0 = ECC disabled\n    // 1 = ECC enabled\n    parameter C_USE_ECC_WACH                 = 0,\n    parameter C_USE_ECC_WDCH                 = 0,\n    parameter C_USE_ECC_WRCH                 = 0,\n    parameter C_USE_ECC_RACH                 = 0,\n    parameter C_USE_ECC_RDCH                 = 0,\n    parameter C_USE_ECC_AXIS                 = 0,\n\n    // ECC Error Injection Type\n    // 0 = No Error Injection\n    // 1 = Single Bit Error Injection\n    // 2 = Double Bit Error Injection\n    // 3 = Single Bit and Double Bit Error Injection\n    parameter C_ERROR_INJECTION_TYPE_WACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WRCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_AXIS    = 0,\n\n    // Input Data Width\n    // Accumulation of all AXI input signal's width\n    parameter C_DIN_WIDTH_WACH               = 1,\n    parameter C_DIN_WIDTH_WDCH               = 1,\n    parameter C_DIN_WIDTH_WRCH               = 1,\n    parameter C_DIN_WIDTH_RACH               = 1,\n    parameter C_DIN_WIDTH_RDCH               = 1,\n    parameter C_DIN_WIDTH_AXIS               = 1,\n\n    parameter C_WR_DEPTH_WACH                = 16,\n    parameter C_WR_DEPTH_WDCH                = 16,\n    parameter C_WR_DEPTH_WRCH                = 16,\n    parameter C_WR_DEPTH_RACH                = 16,\n    parameter C_WR_DEPTH_RDCH                = 16,\n    parameter C_WR_DEPTH_AXIS                = 16,\n\n    parameter C_WR_PNTR_WIDTH_WACH           = 4,\n    parameter C_WR_PNTR_WIDTH_WDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_WRCH           = 4,\n    parameter C_WR_PNTR_WIDTH_RACH           = 4,\n    parameter C_WR_PNTR_WIDTH_RDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_AXIS           = 4,\n\n    parameter C_HAS_DATA_COUNTS_WACH         = 0,\n    parameter C_HAS_DATA_COUNTS_WDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_WRCH         = 0,\n    parameter C_HAS_DATA_COUNTS_RACH         = 0,\n    parameter C_HAS_DATA_COUNTS_RDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_AXIS         = 0,\n\n    parameter C_HAS_PROG_FLAGS_WACH          = 0,\n    parameter C_HAS_PROG_FLAGS_WDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_WRCH          = 0,\n    parameter C_HAS_PROG_FLAGS_RACH          = 0,\n    parameter C_HAS_PROG_FLAGS_RDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_AXIS          = 0,\n\n    parameter C_PROG_FULL_TYPE_WACH          = 0,\n    parameter C_PROG_FULL_TYPE_WDCH          = 0,\n    parameter C_PROG_FULL_TYPE_WRCH          = 0,\n    parameter C_PROG_FULL_TYPE_RACH          = 0,\n    parameter C_PROG_FULL_TYPE_RDCH          = 0,\n    parameter C_PROG_FULL_TYPE_AXIS          = 0,\n\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS      = 0,\n\n    parameter C_PROG_EMPTY_TYPE_WACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WRCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_AXIS         = 0,\n\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS     = 0,\n\n    parameter C_REG_SLICE_MODE_WACH          = 0,\n    parameter C_REG_SLICE_MODE_WDCH          = 0,\n    parameter C_REG_SLICE_MODE_WRCH          = 0,\n    parameter C_REG_SLICE_MODE_RACH          = 0,\n    parameter C_REG_SLICE_MODE_RDCH          = 0,\n    parameter C_REG_SLICE_MODE_AXIS          = 0\n\n    )\n\n   (\n    //------------------------------------------------------------------------------\n    // Input and Output Declarations\n    //------------------------------------------------------------------------------\n\n    // Conventional FIFO Interface Signals\n    input                               backup,\n    input                               backup_marker,\n    input                               clk,\n    input                               rst,\n    input                               srst,\n    input                               wr_clk,\n    input                               wr_rst,\n    input                               rd_clk,\n    input                               rd_rst,\n    input [C_DIN_WIDTH-1:0]             din,\n    input                               wr_en,\n    input                               rd_en,\n    // Optional inputs\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_assert,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_negate,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_assert,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_negate,\n    input                               int_clk,\n    input                               injectdbiterr,\n    input                               injectsbiterr,\n    input                               sleep,\n\n    output [C_DOUT_WIDTH-1:0]           dout,\n    output                              full,\n    output                              almost_full,\n    output                              wr_ack,\n    output                              overflow,\n    output                              empty,\n    output                              almost_empty,\n    output                              valid,\n    output                              underflow,\n    output [C_DATA_COUNT_WIDTH-1:0]     data_count,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]  rd_data_count,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count,\n    output                              prog_full,\n    output                              prog_empty,\n    output                              sbiterr,\n    output                              dbiterr,\n    output                              wr_rst_busy,\n    output                              rd_rst_busy,\n\n\n    // AXI Global Signal\n    input                               m_aclk,\n    input                               s_aclk,\n    input                               s_aresetn,\n    input                               s_aclk_en,\n    input                               m_aclk_en,\n    \n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_awid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_awaddr,\n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_awlen,\n    input [3-1:0]                       s_axi_awsize,\n    input [2-1:0]                       s_axi_awburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_awlock,\n    input [4-1:0]                       s_axi_awcache,\n    input [3-1:0]                       s_axi_awprot,\n    input [4-1:0]                       s_axi_awqos,\n    input [4-1:0]                       s_axi_awregion,\n    input [C_AXI_AWUSER_WIDTH-1:0]      s_axi_awuser,\n    input                               s_axi_awvalid,\n    output                              s_axi_awready,\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_wid,\n    input [C_AXI_DATA_WIDTH-1:0]        s_axi_wdata,\n    input [C_AXI_DATA_WIDTH/8-1:0]      s_axi_wstrb,\n    input                               s_axi_wlast,\n    input [C_AXI_WUSER_WIDTH-1:0]       s_axi_wuser,\n    input                               s_axi_wvalid,\n    output                              s_axi_wready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_bid,\n    output [2-1:0]                      s_axi_bresp,\n    output [C_AXI_BUSER_WIDTH-1:0]      s_axi_buser,\n    output                              s_axi_bvalid,\n    input                               s_axi_bready,\n    \n    // AXI Full/Lite Master Write Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_awid,\n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_awlen,\n    output [3-1:0]                      m_axi_awsize,\n    output [2-1:0]                      m_axi_awburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_awlock,\n    output [4-1:0]                      m_axi_awcache,\n    output [3-1:0]                      m_axi_awprot,\n    output [4-1:0]                      m_axi_awqos,\n    output [4-1:0]                      m_axi_awregion,\n    output [C_AXI_AWUSER_WIDTH-1:0]     m_axi_awuser,\n    output                              m_axi_awvalid,\n    input                               m_axi_awready,\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_wid,\n    output [C_AXI_DATA_WIDTH-1:0]       m_axi_wdata,\n    output [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb,\n    output                              m_axi_wlast,\n    output [C_AXI_WUSER_WIDTH-1:0]      m_axi_wuser,\n    output                              m_axi_wvalid,\n    input                               m_axi_wready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_bid,\n    input [2-1:0]                       m_axi_bresp,\n    input [C_AXI_BUSER_WIDTH-1:0]       m_axi_buser,\n    input                               m_axi_bvalid,\n    output                              m_axi_bready,\n    \n    \n    // AXI Full/Lite Slave Read Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_arid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_araddr, \n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_arlen,\n    input [3-1:0]                       s_axi_arsize,\n    input [2-1:0]                       s_axi_arburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_arlock,\n    input [4-1:0]                       s_axi_arcache,\n    input [3-1:0]                       s_axi_arprot,\n    input [4-1:0]                       s_axi_arqos,\n    input [4-1:0]                       s_axi_arregion,\n    input [C_AXI_ARUSER_WIDTH-1:0]      s_axi_aruser,\n    input                               s_axi_arvalid,\n    output                              s_axi_arready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_rid,       \n    output [C_AXI_DATA_WIDTH-1:0]       s_axi_rdata, \n    output [2-1:0]                      s_axi_rresp,\n    output                              s_axi_rlast,\n    output [C_AXI_RUSER_WIDTH-1:0]      s_axi_ruser,\n    output                              s_axi_rvalid,\n    input                               s_axi_rready,\n    \n    \n    \n    // AXI Full/Lite Master Read Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_arid,        \n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,  \n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_arlen,\n    output [3-1:0]                      m_axi_arsize,\n    output [2-1:0]                      m_axi_arburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_arlock,\n    output [4-1:0]                      m_axi_arcache,\n    output [3-1:0]                      m_axi_arprot,\n    output [4-1:0]                      m_axi_arqos,\n    output [4-1:0]                      m_axi_arregion,\n    output [C_AXI_ARUSER_WIDTH-1:0]     m_axi_aruser,\n    output                              m_axi_arvalid,\n    input                               m_axi_arready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_rid,        \n    input [C_AXI_DATA_WIDTH-1:0]        m_axi_rdata,  \n    input [2-1:0]                       m_axi_rresp,\n    input                               m_axi_rlast,\n    input [C_AXI_RUSER_WIDTH-1:0]       m_axi_ruser,\n    input                               m_axi_rvalid,\n    output                              m_axi_rready,\n    \n    \n    // AXI Streaming Slave Signals (Write side)\n    input                               s_axis_tvalid,\n    output                              s_axis_tready,\n    input [C_AXIS_TDATA_WIDTH-1:0]      s_axis_tdata,\n    input [C_AXIS_TSTRB_WIDTH-1:0]      s_axis_tstrb,\n    input [C_AXIS_TKEEP_WIDTH-1:0]      s_axis_tkeep,\n    input                               s_axis_tlast,\n    input [C_AXIS_TID_WIDTH-1:0]        s_axis_tid,\n    input [C_AXIS_TDEST_WIDTH-1:0]      s_axis_tdest,\n    input [C_AXIS_TUSER_WIDTH-1:0]      s_axis_tuser,\n    \n    // AXI Streaming Master Signals (Read side)\n    output                              m_axis_tvalid,\n    input                               m_axis_tready,\n    output [C_AXIS_TDATA_WIDTH-1:0]     m_axis_tdata,\n    output [C_AXIS_TSTRB_WIDTH-1:0]     m_axis_tstrb,\n    output [C_AXIS_TKEEP_WIDTH-1:0]     m_axis_tkeep,\n    output                              m_axis_tlast,\n    output [C_AXIS_TID_WIDTH-1:0]       m_axis_tid,\n    output [C_AXIS_TDEST_WIDTH-1:0]     m_axis_tdest,\n    output [C_AXIS_TUSER_WIDTH-1:0]     m_axis_tuser,\n    \n           \n    \n    \n    // AXI Full/Lite Write Address Channel signals\n    input                               axi_aw_injectsbiterr,\n    input                               axi_aw_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_rd_data_count,\n    output                              axi_aw_sbiterr,\n    output                              axi_aw_dbiterr,\n    output                              axi_aw_overflow,\n    output                              axi_aw_underflow,\n    output                              axi_aw_prog_full,\n    output                              axi_aw_prog_empty,\n    \n    \n    // AXI Full/Lite Write Data Channel signals\n    input                               axi_w_injectsbiterr,\n    input                               axi_w_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_rd_data_count,\n    output                              axi_w_sbiterr,\n    output                              axi_w_dbiterr,\n    output                              axi_w_overflow,\n    output                              axi_w_underflow,\n    output                              axi_w_prog_full,\n    output                              axi_w_prog_empty,\n    \n    \n    // AXI Full/Lite Write Response Channel signals\n    input                               axi_b_injectsbiterr,\n    input                               axi_b_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_rd_data_count,\n    output                              axi_b_sbiterr,\n    output                              axi_b_dbiterr,\n    output                              axi_b_overflow,\n    output                              axi_b_underflow,\n    output                              axi_b_prog_full,\n    output                              axi_b_prog_empty,\n    \n    \n    \n    // AXI Full/Lite Read Address Channel signals\n    input                               axi_ar_injectsbiterr,\n    input                               axi_ar_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_rd_data_count,\n    output                              axi_ar_sbiterr,\n    output                              axi_ar_dbiterr,\n    output                              axi_ar_overflow,\n    output                              axi_ar_underflow,\n    output                              axi_ar_prog_full,\n    output                              axi_ar_prog_empty,\n\n    \n    // AXI Full/Lite Read Data Channel Signals\n    input                               axi_r_injectsbiterr,\n    input                               axi_r_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_rd_data_count,\n    output                              axi_r_sbiterr,\n    output                              axi_r_dbiterr,\n    output                              axi_r_overflow,\n    output                              axi_r_underflow,\n    output                              axi_r_prog_full,\n    output                              axi_r_prog_empty,\n\n    \n    // AXI Streaming FIFO Related Signals\n    input                               axis_injectsbiterr,\n    input                               axis_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_wr_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_rd_data_count,\n    output                              axis_sbiterr,\n    output                              axis_dbiterr,\n    output                              axis_overflow,\n    output                              axis_underflow,\n    output                              axis_prog_full,\n    output                              axis_prog_empty\n\n    );\n\n    wire                              BACKUP;\n    wire                              BACKUP_MARKER;\n    wire                              CLK;\n    wire                              RST;\n    wire                              SRST;\n    wire                              WR_CLK;\n    wire                              WR_RST;\n    wire                              RD_CLK;\n    wire                              RD_RST;\n    wire [C_DIN_WIDTH-1:0]            DIN;\n    wire                              WR_EN;\n    wire                              RD_EN;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_ASSERT;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_NEGATE;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_ASSERT;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_NEGATE;\n    wire                              INT_CLK;\n    wire                              INJECTDBITERR;\n    wire                              INJECTSBITERR;\n    wire                              SLEEP;\n    wire [C_DOUT_WIDTH-1:0]           DOUT;\n    wire                              FULL;\n    wire                              ALMOST_FULL;\n    wire                              WR_ACK;\n    wire                              OVERFLOW;\n    wire                              EMPTY;\n    wire                              ALMOST_EMPTY;\n    wire                              VALID;\n    wire                              UNDERFLOW;\n    wire [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT;\n    wire [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT;\n    wire                              PROG_FULL;\n    wire                              PROG_EMPTY;\n    wire                              SBITERR;\n    wire                              DBITERR;\n    wire                              WR_RST_BUSY;\n    wire                              RD_RST_BUSY;\n    wire                              M_ACLK;\n    wire                              S_ACLK;\n    wire                              S_ARESETN;\n    wire                              S_ACLK_EN;\n    wire                              M_ACLK_EN;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_AWLEN;\n    wire [3-1:0]                      S_AXI_AWSIZE;\n    wire [2-1:0]                      S_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_AWLOCK;\n    wire [4-1:0]                      S_AXI_AWCACHE;\n    wire [3-1:0]                      S_AXI_AWPROT;\n    wire [4-1:0]                      S_AXI_AWQOS;\n    wire [4-1:0]                      S_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     S_AXI_AWUSER;\n    wire                              S_AXI_AWVALID;\n    wire                              S_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     S_AXI_WSTRB;\n    wire                              S_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      S_AXI_WUSER;\n    wire                              S_AXI_WVALID;\n    wire                              S_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_BID;\n    wire [2-1:0]                      S_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      S_AXI_BUSER;\n    wire                              S_AXI_BVALID;\n    wire                              S_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_AWLEN;\n    wire [3-1:0]                      M_AXI_AWSIZE;\n    wire [2-1:0]                      M_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_AWLOCK;\n    wire [4-1:0]                      M_AXI_AWCACHE;\n    wire [3-1:0]                      M_AXI_AWPROT;\n    wire [4-1:0]                      M_AXI_AWQOS;\n    wire [4-1:0]                      M_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     M_AXI_AWUSER;\n    wire                              M_AXI_AWVALID;\n    wire                              M_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     M_AXI_WSTRB;\n    wire                              M_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      M_AXI_WUSER;\n    wire                              M_AXI_WVALID;\n    wire                              M_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_BID;\n    wire [2-1:0]                      M_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      M_AXI_BUSER;\n    wire                              M_AXI_BVALID;\n    wire                              M_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_ARID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_ARADDR; \n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_ARLEN;\n    wire [3-1:0]                      S_AXI_ARSIZE;\n    wire [2-1:0]                      S_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_ARLOCK;\n    wire [4-1:0]                      S_AXI_ARCACHE;\n    wire [3-1:0]                      S_AXI_ARPROT;\n    wire [4-1:0]                      S_AXI_ARQOS;\n    wire [4-1:0]                      S_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     S_AXI_ARUSER;\n    wire                              S_AXI_ARVALID;\n    wire                              S_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_RID;       \n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_RDATA; \n    wire [2-1:0]                      S_AXI_RRESP;\n    wire                              S_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      S_AXI_RUSER;\n    wire                              S_AXI_RVALID;\n    wire                              S_AXI_RREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_ARID;        \n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_ARADDR;  \n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_ARLEN;\n    wire [3-1:0]                      M_AXI_ARSIZE;\n    wire [2-1:0]                      M_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_ARLOCK;\n    wire [4-1:0]                      M_AXI_ARCACHE;\n    wire [3-1:0]                      M_AXI_ARPROT;\n    wire [4-1:0]                      M_AXI_ARQOS;\n    wire [4-1:0]                      M_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     M_AXI_ARUSER;\n    wire                              M_AXI_ARVALID;\n    wire                              M_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_RID;        \n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_RDATA;  \n    wire [2-1:0]                      M_AXI_RRESP;\n    wire                              M_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      M_AXI_RUSER;\n    wire                              M_AXI_RVALID;\n    wire                              M_AXI_RREADY;\n    wire                              S_AXIS_TVALID;\n    wire                              S_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     S_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     S_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     S_AXIS_TKEEP;\n    wire                              S_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       S_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     S_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     S_AXIS_TUSER;\n    wire                              M_AXIS_TVALID;\n    wire                              M_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     M_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     M_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     M_AXIS_TKEEP;\n    wire                              M_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       M_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     M_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     M_AXIS_TUSER;\n    wire                              AXI_AW_INJECTSBITERR;\n    wire                              AXI_AW_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_RD_DATA_COUNT;\n    wire                              AXI_AW_SBITERR;\n    wire                              AXI_AW_DBITERR;\n    wire                              AXI_AW_OVERFLOW;\n    wire                              AXI_AW_UNDERFLOW;\n    wire                              AXI_AW_PROG_FULL;\n    wire                              AXI_AW_PROG_EMPTY;\n    wire                              AXI_W_INJECTSBITERR;\n    wire                              AXI_W_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_RD_DATA_COUNT;\n    wire                              AXI_W_SBITERR;\n    wire                              AXI_W_DBITERR;\n    wire                              AXI_W_OVERFLOW;\n    wire                              AXI_W_UNDERFLOW;\n    wire                              AXI_W_PROG_FULL;\n    wire                              AXI_W_PROG_EMPTY;\n    wire                              AXI_B_INJECTSBITERR;\n    wire                              AXI_B_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_RD_DATA_COUNT;\n    wire                              AXI_B_SBITERR;\n    wire                              AXI_B_DBITERR;\n    wire                              AXI_B_OVERFLOW;\n    wire                              AXI_B_UNDERFLOW;\n    wire                              AXI_B_PROG_FULL;\n    wire                              AXI_B_PROG_EMPTY;\n    wire                              AXI_AR_INJECTSBITERR;\n    wire                              AXI_AR_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_RD_DATA_COUNT;\n    wire                              AXI_AR_SBITERR;\n    wire                              AXI_AR_DBITERR;\n    wire                              AXI_AR_OVERFLOW;\n    wire                              AXI_AR_UNDERFLOW;\n    wire                              AXI_AR_PROG_FULL;\n    wire                              AXI_AR_PROG_EMPTY;\n    wire                              AXI_R_INJECTSBITERR;\n    wire                              AXI_R_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_RD_DATA_COUNT;\n    wire                              AXI_R_SBITERR;\n    wire                              AXI_R_DBITERR;\n    wire                              AXI_R_OVERFLOW;\n    wire                              AXI_R_UNDERFLOW;\n    wire                              AXI_R_PROG_FULL;\n    wire                              AXI_R_PROG_EMPTY;\n    wire                              AXIS_INJECTSBITERR;\n    wire                              AXIS_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_RD_DATA_COUNT;\n    wire                              AXIS_SBITERR;\n    wire                              AXIS_DBITERR;\n    wire                              AXIS_OVERFLOW;\n    wire                              AXIS_UNDERFLOW;\n    wire                              AXIS_PROG_FULL;\n    wire                              AXIS_PROG_EMPTY;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count_in;\n    wire                              wr_rst_int;\n    wire                              rd_rst_int;\n    wire                              wr_rst_busy_o;\n    wire                              wr_rst_busy_ntve;\n    wire                              wr_rst_busy_axis;\n    wire                              wr_rst_busy_wach;\n    wire                              wr_rst_busy_wdch;\n    wire                              wr_rst_busy_wrch;\n    wire                              wr_rst_busy_rach;\n    wire                              wr_rst_busy_rdch;\n\n\n\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n\n\n\n    // Conventional FIFO Interface Signals\n    assign BACKUP                 = backup;\n    assign BACKUP_MARKER          = backup_marker;\n    assign CLK                    = clk;\n    assign RST                    = rst;\n    assign SRST                   = srst;\n    assign WR_CLK                 = wr_clk;\n    assign WR_RST                 = wr_rst;\n    assign RD_CLK                 = rd_clk;\n    assign RD_RST                 = rd_rst;\n    assign WR_EN                  = wr_en;\n    assign RD_EN                  = rd_en;\n    assign INT_CLK                = int_clk;\n    assign INJECTDBITERR          = injectdbiterr;\n    assign INJECTSBITERR          = injectsbiterr;\n    assign SLEEP                  = sleep;\n    assign full                   = FULL;\n    assign almost_full            = ALMOST_FULL;\n    assign wr_ack                 = WR_ACK;\n    assign overflow               = OVERFLOW;\n    assign empty                  = EMPTY;\n    assign almost_empty           = ALMOST_EMPTY;\n    assign valid                  = VALID;\n    assign underflow              = UNDERFLOW;\n    assign prog_full              = PROG_FULL;\n    assign prog_empty             = PROG_EMPTY;\n    assign sbiterr                = SBITERR;\n    assign dbiterr                = DBITERR;\n//    assign wr_rst_busy            = WR_RST_BUSY | wr_rst_busy_o;\n    assign wr_rst_busy            = wr_rst_busy_o;\n    assign rd_rst_busy            = RD_RST_BUSY;\n    assign M_ACLK                 = m_aclk;\n    assign S_ACLK                 = s_aclk;\n    assign S_ARESETN              = s_aresetn;\n    assign S_ACLK_EN              = s_aclk_en;\n    assign M_ACLK_EN              = m_aclk_en;\n    assign S_AXI_AWVALID          = s_axi_awvalid;\n    assign s_axi_awready          = S_AXI_AWREADY;\n    assign S_AXI_WLAST            = s_axi_wlast;\n    assign S_AXI_WVALID           = s_axi_wvalid;\n    assign s_axi_wready           = S_AXI_WREADY;\n    assign s_axi_bvalid           = S_AXI_BVALID;\n    assign S_AXI_BREADY           = s_axi_bready;\n    assign m_axi_awvalid          = M_AXI_AWVALID;\n    assign M_AXI_AWREADY          = m_axi_awready;\n    assign m_axi_wlast            = M_AXI_WLAST;\n    assign m_axi_wvalid           = M_AXI_WVALID;\n    assign M_AXI_WREADY           = m_axi_wready;\n    assign M_AXI_BVALID           = m_axi_bvalid;\n    assign m_axi_bready           = M_AXI_BREADY;\n    assign S_AXI_ARVALID          = s_axi_arvalid;\n    assign s_axi_arready          = S_AXI_ARREADY;\n    assign s_axi_rlast            = S_AXI_RLAST;\n    assign s_axi_rvalid           = S_AXI_RVALID;\n    assign S_AXI_RREADY           = s_axi_rready;\n    assign m_axi_arvalid          = M_AXI_ARVALID;\n    assign M_AXI_ARREADY          = m_axi_arready;\n    assign M_AXI_RLAST            = m_axi_rlast;\n    assign M_AXI_RVALID           = m_axi_rvalid;\n    assign m_axi_rready           = M_AXI_RREADY;\n    assign S_AXIS_TVALID          = s_axis_tvalid;\n    assign s_axis_tready          = S_AXIS_TREADY;\n    assign S_AXIS_TLAST           = s_axis_tlast;\n    assign m_axis_tvalid          = M_AXIS_TVALID;\n    assign M_AXIS_TREADY          = m_axis_tready;\n    assign m_axis_tlast           = M_AXIS_TLAST;\n    assign AXI_AW_INJECTSBITERR   = axi_aw_injectsbiterr;\n    assign AXI_AW_INJECTDBITERR   = axi_aw_injectdbiterr;\n    assign axi_aw_sbiterr         = AXI_AW_SBITERR;\n    assign axi_aw_dbiterr         = AXI_AW_DBITERR;\n    assign axi_aw_overflow        = AXI_AW_OVERFLOW;\n    assign axi_aw_underflow       = AXI_AW_UNDERFLOW;\n    assign axi_aw_prog_full       = AXI_AW_PROG_FULL;\n    assign axi_aw_prog_empty      = AXI_AW_PROG_EMPTY;\n    assign AXI_W_INJECTSBITERR    = axi_w_injectsbiterr;\n    assign AXI_W_INJECTDBITERR    = axi_w_injectdbiterr;\n    assign axi_w_sbiterr          = AXI_W_SBITERR;\n    assign axi_w_dbiterr          = AXI_W_DBITERR;\n    assign axi_w_overflow         = AXI_W_OVERFLOW;\n    assign axi_w_underflow        = AXI_W_UNDERFLOW;\n    assign axi_w_prog_full        = AXI_W_PROG_FULL;\n    assign axi_w_prog_empty       = AXI_W_PROG_EMPTY;\n    assign AXI_B_INJECTSBITERR    = axi_b_injectsbiterr;\n    assign AXI_B_INJECTDBITERR    = axi_b_injectdbiterr;\n    assign axi_b_sbiterr          = AXI_B_SBITERR;\n    assign axi_b_dbiterr          = AXI_B_DBITERR;\n    assign axi_b_overflow         = AXI_B_OVERFLOW;\n    assign axi_b_underflow        = AXI_B_UNDERFLOW;\n    assign axi_b_prog_full        = AXI_B_PROG_FULL;\n    assign axi_b_prog_empty       = AXI_B_PROG_EMPTY;\n    assign AXI_AR_INJECTSBITERR   = axi_ar_injectsbiterr;\n    assign AXI_AR_INJECTDBITERR   = axi_ar_injectdbiterr;\n    assign axi_ar_sbiterr         = AXI_AR_SBITERR;\n    assign axi_ar_dbiterr         = AXI_AR_DBITERR;\n    assign axi_ar_overflow        = AXI_AR_OVERFLOW;\n    assign axi_ar_underflow       = AXI_AR_UNDERFLOW;\n    assign axi_ar_prog_full       = AXI_AR_PROG_FULL;\n    assign axi_ar_prog_empty      = AXI_AR_PROG_EMPTY;\n    assign AXI_R_INJECTSBITERR    = axi_r_injectsbiterr;\n    assign AXI_R_INJECTDBITERR    = axi_r_injectdbiterr;\n    assign axi_r_sbiterr          = AXI_R_SBITERR;\n    assign axi_r_dbiterr          = AXI_R_DBITERR;\n    assign axi_r_overflow         = AXI_R_OVERFLOW;\n    assign axi_r_underflow        = AXI_R_UNDERFLOW;\n    assign axi_r_prog_full        = AXI_R_PROG_FULL;\n    assign axi_r_prog_empty       = AXI_R_PROG_EMPTY;\n    assign AXIS_INJECTSBITERR     = axis_injectsbiterr;\n    assign AXIS_INJECTDBITERR     = axis_injectdbiterr;\n    assign axis_sbiterr           = AXIS_SBITERR;\n    assign axis_dbiterr           = AXIS_DBITERR;\n    assign axis_overflow          = AXIS_OVERFLOW;\n    assign axis_underflow         = AXIS_UNDERFLOW;\n    assign axis_prog_full         = AXIS_PROG_FULL;\n    assign axis_prog_empty        = AXIS_PROG_EMPTY;\n\n\n    assign DIN                       = din;\n    assign PROG_EMPTY_THRESH         = prog_empty_thresh;\n    assign PROG_EMPTY_THRESH_ASSERT  = prog_empty_thresh_assert;\n    assign PROG_EMPTY_THRESH_NEGATE  = prog_empty_thresh_negate;\n    assign PROG_FULL_THRESH          = prog_full_thresh;\n    assign PROG_FULL_THRESH_ASSERT   = prog_full_thresh_assert;\n    assign PROG_FULL_THRESH_NEGATE   = prog_full_thresh_negate;\n    assign dout                      = DOUT;\n    assign data_count                = DATA_COUNT;\n    assign rd_data_count             = RD_DATA_COUNT;\n    assign wr_data_count             = WR_DATA_COUNT;\n    assign S_AXI_AWID                = s_axi_awid;\n    assign S_AXI_AWADDR              = s_axi_awaddr;\n    assign S_AXI_AWLEN               = s_axi_awlen;\n    assign S_AXI_AWSIZE              = s_axi_awsize;\n    assign S_AXI_AWBURST             = s_axi_awburst;\n    assign S_AXI_AWLOCK              = s_axi_awlock;\n    assign S_AXI_AWCACHE             = s_axi_awcache;\n    assign S_AXI_AWPROT              = s_axi_awprot;\n    assign S_AXI_AWQOS               = s_axi_awqos;\n    assign S_AXI_AWREGION            = s_axi_awregion;\n    assign S_AXI_AWUSER              = s_axi_awuser;\n    assign S_AXI_WID                 = s_axi_wid;\n    assign S_AXI_WDATA               = s_axi_wdata;\n    assign S_AXI_WSTRB               = s_axi_wstrb;\n    assign S_AXI_WUSER               = s_axi_wuser;\n    assign s_axi_bid                 = S_AXI_BID;\n    assign s_axi_bresp               = S_AXI_BRESP;\n    assign s_axi_buser               = S_AXI_BUSER;\n    assign m_axi_awid                = M_AXI_AWID;\n    assign m_axi_awaddr              = M_AXI_AWADDR;\n    assign m_axi_awlen               = M_AXI_AWLEN;\n    assign m_axi_awsize              = M_AXI_AWSIZE;\n    assign m_axi_awburst             = M_AXI_AWBURST;\n    assign m_axi_awlock              = M_AXI_AWLOCK;\n    assign m_axi_awcache             = M_AXI_AWCACHE;\n    assign m_axi_awprot              = M_AXI_AWPROT;\n    assign m_axi_awqos               = M_AXI_AWQOS;\n    assign m_axi_awregion            = M_AXI_AWREGION;\n    assign m_axi_awuser              = M_AXI_AWUSER;\n    assign m_axi_wid                 = M_AXI_WID;\n    assign m_axi_wdata               = M_AXI_WDATA;\n    assign m_axi_wstrb               = M_AXI_WSTRB;\n    assign m_axi_wuser               = M_AXI_WUSER;\n    assign M_AXI_BID                 = m_axi_bid;\n    assign M_AXI_BRESP               = m_axi_bresp;\n    assign M_AXI_BUSER               = m_axi_buser;\n    assign S_AXI_ARID                = s_axi_arid;\n    assign S_AXI_ARADDR              = s_axi_araddr; \n    assign S_AXI_ARLEN               = s_axi_arlen;\n    assign S_AXI_ARSIZE              = s_axi_arsize;\n    assign S_AXI_ARBURST             = s_axi_arburst;\n    assign S_AXI_ARLOCK              = s_axi_arlock;\n    assign S_AXI_ARCACHE             = s_axi_arcache;\n    assign S_AXI_ARPROT              = s_axi_arprot;\n    assign S_AXI_ARQOS               = s_axi_arqos;\n    assign S_AXI_ARREGION            = s_axi_arregion;\n    assign S_AXI_ARUSER              = s_axi_aruser;\n    assign s_axi_rid                 = S_AXI_RID;\n    assign s_axi_rdata               = S_AXI_RDATA;\n    assign s_axi_rresp               = S_AXI_RRESP;\n    assign s_axi_ruser               = S_AXI_RUSER;\n    assign m_axi_arid                = M_AXI_ARID;        \n    assign m_axi_araddr              = M_AXI_ARADDR;  \n    assign m_axi_arlen               = M_AXI_ARLEN;\n    assign m_axi_arsize              = M_AXI_ARSIZE;\n    assign m_axi_arburst             = M_AXI_ARBURST;\n    assign m_axi_arlock              = M_AXI_ARLOCK;\n    assign m_axi_arcache             = M_AXI_ARCACHE;\n    assign m_axi_arprot              = M_AXI_ARPROT;\n    assign m_axi_arqos               = M_AXI_ARQOS;\n    assign m_axi_arregion            = M_AXI_ARREGION;\n    assign m_axi_aruser              = M_AXI_ARUSER;\n    assign M_AXI_RID                 = m_axi_rid;        \n    assign M_AXI_RDATA               = m_axi_rdata;  \n    assign M_AXI_RRESP               = m_axi_rresp;\n    assign M_AXI_RUSER               = m_axi_ruser;\n    assign S_AXIS_TDATA              = s_axis_tdata;\n    assign S_AXIS_TSTRB              = s_axis_tstrb;\n    assign S_AXIS_TKEEP              = s_axis_tkeep;\n    assign S_AXIS_TID                = s_axis_tid;\n    assign S_AXIS_TDEST              = s_axis_tdest;\n    assign S_AXIS_TUSER              = s_axis_tuser;\n    assign m_axis_tdata              = M_AXIS_TDATA;\n    assign m_axis_tstrb              = M_AXIS_TSTRB;\n    assign m_axis_tkeep              = M_AXIS_TKEEP;\n    assign m_axis_tid                = M_AXIS_TID;\n    assign m_axis_tdest              = M_AXIS_TDEST;\n    assign m_axis_tuser              = M_AXIS_TUSER;\n    assign AXI_AW_PROG_FULL_THRESH   = axi_aw_prog_full_thresh;\n    assign AXI_AW_PROG_EMPTY_THRESH  = axi_aw_prog_empty_thresh;\n    assign axi_aw_data_count         = AXI_AW_DATA_COUNT;\n    assign axi_aw_wr_data_count      = AXI_AW_WR_DATA_COUNT;\n    assign axi_aw_rd_data_count      = AXI_AW_RD_DATA_COUNT;\n    assign AXI_W_PROG_FULL_THRESH    = axi_w_prog_full_thresh;\n    assign AXI_W_PROG_EMPTY_THRESH   = axi_w_prog_empty_thresh;\n    assign axi_w_data_count          = AXI_W_DATA_COUNT;\n    assign axi_w_wr_data_count       = AXI_W_WR_DATA_COUNT;\n    assign axi_w_rd_data_count       = AXI_W_RD_DATA_COUNT;\n    assign AXI_B_PROG_FULL_THRESH    = axi_b_prog_full_thresh;\n    assign AXI_B_PROG_EMPTY_THRESH   = axi_b_prog_empty_thresh;\n    assign axi_b_data_count          = AXI_B_DATA_COUNT;\n    assign axi_b_wr_data_count       = AXI_B_WR_DATA_COUNT;\n    assign axi_b_rd_data_count       = AXI_B_RD_DATA_COUNT;\n    assign AXI_AR_PROG_FULL_THRESH   = axi_ar_prog_full_thresh;\n    assign AXI_AR_PROG_EMPTY_THRESH  = axi_ar_prog_empty_thresh;\n    assign axi_ar_data_count         = AXI_AR_DATA_COUNT;\n    assign axi_ar_wr_data_count      = AXI_AR_WR_DATA_COUNT;\n    assign axi_ar_rd_data_count      = AXI_AR_RD_DATA_COUNT;\n    assign AXI_R_PROG_FULL_THRESH    = axi_r_prog_full_thresh;\n    assign AXI_R_PROG_EMPTY_THRESH   = axi_r_prog_empty_thresh;\n    assign axi_r_data_count          = AXI_R_DATA_COUNT;\n    assign axi_r_wr_data_count       = AXI_R_WR_DATA_COUNT;\n    assign axi_r_rd_data_count       = AXI_R_RD_DATA_COUNT;\n    assign AXIS_PROG_FULL_THRESH     = axis_prog_full_thresh;\n    assign AXIS_PROG_EMPTY_THRESH    = axis_prog_empty_thresh;\n    assign axis_data_count           = AXIS_DATA_COUNT;\n    assign axis_wr_data_count        = AXIS_WR_DATA_COUNT;\n    assign axis_rd_data_count        = AXIS_RD_DATA_COUNT;\n\n\n  generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_COMMON_CLOCK \t\t(C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DATA_COUNT_WIDTH\t\t(C_DATA_COUNT_WIDTH),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH),\n        .C_DOUT_RST_VAL\t\t\t(C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),\n        .C_DOUT_WIDTH\t\t\t(C_DOUT_WIDTH),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n        .C_HAS_ALMOST_EMPTY\t\t(C_HAS_ALMOST_EMPTY),\n        .C_HAS_ALMOST_FULL\t\t(C_HAS_ALMOST_FULL),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_DATA_COUNT\t\t(C_HAS_DATA_COUNT),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_HAS_RD_DATA_COUNT\t\t(C_HAS_RD_DATA_COUNT),\n        .C_HAS_RD_RST\t\t\t(C_HAS_RD_RST),\n        .C_HAS_RST\t\t\t(C_HAS_RST),\n        .C_HAS_SRST\t\t\t(C_HAS_SRST),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_HAS_VALID\t\t\t(C_HAS_VALID),\n        .C_HAS_WR_ACK\t\t\t(C_HAS_WR_ACK),\n        .C_HAS_WR_DATA_COUNT\t\t(C_HAS_WR_DATA_COUNT),\n        .C_HAS_WR_RST\t\t\t(C_HAS_WR_RST),\n        .C_IMPLEMENTATION_TYPE\t\t(C_IMPLEMENTATION_TYPE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_MEMORY_TYPE\t\t\t(C_MEMORY_TYPE),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n        .C_PRELOAD_LATENCY\t\t(C_PRELOAD_LATENCY),\n        .C_PRELOAD_REGS\t\t\t(C_PRELOAD_REGS),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL),\n        .C_PROG_EMPTY_THRESH_NEGATE_VAL\t(C_PROG_EMPTY_THRESH_NEGATE_VAL),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL),\n        .C_PROG_FULL_THRESH_NEGATE_VAL\t(C_PROG_FULL_THRESH_NEGATE_VAL),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_RD_DATA_COUNT_WIDTH),\n        .C_RD_DEPTH\t\t\t(C_RD_DEPTH),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_RD_PNTR_WIDTH\t\t(C_RD_PNTR_WIDTH),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n        .C_USE_ECC                      (C_USE_ECC),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_EN_SAFETY_CKT\t\t(C_EN_SAFETY_CKT),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_USE_FWFT_DATA_COUNT\t\t(C_USE_FWFT_DATA_COUNT),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_DATA_COUNT_WIDTH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (C_ENABLE_RST_SYNC),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE),\n        .C_AXI_TYPE                     (C_AXI_TYPE),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE)\n      )\n    fifo_generator_v13_2_5_conv_dut\n      (\n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .CLK                      (CLK),\n        .RST                      (RST),\n        .SRST                     (SRST),\n        .WR_CLK                   (WR_CLK),\n        .WR_RST                   (WR_RST),\n        .RD_CLK                   (RD_CLK),\n        .RD_RST                   (RD_RST),\n        .DIN                      (DIN),\n        .WR_EN                    (WR_EN),\n        .RD_EN                    (RD_EN),\n        .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),\n        .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),\n        .PROG_FULL_THRESH         (PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),\n        .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),\n        .INT_CLK                  (INT_CLK),\n        .INJECTDBITERR            (INJECTDBITERR), \n        .INJECTSBITERR            (INJECTSBITERR),\n  \n        .DOUT                     (DOUT),\n        .FULL                     (FULL),\n        .ALMOST_FULL              (ALMOST_FULL),\n        .WR_ACK                   (WR_ACK),\n        .OVERFLOW                 (OVERFLOW),\n        .EMPTY                    (EMPTY),\n        .ALMOST_EMPTY             (ALMOST_EMPTY),\n        .VALID                    (VALID),\n        .UNDERFLOW                (UNDERFLOW),\n        .DATA_COUNT               (DATA_COUNT),\n        .RD_DATA_COUNT            (RD_DATA_COUNT),\n        .WR_DATA_COUNT            (wr_data_count_in),\n        .PROG_FULL                (PROG_FULL),\n        .PROG_EMPTY               (PROG_EMPTY),\n        .SBITERR                  (SBITERR),\n        .DBITERR                  (DBITERR),\n        .wr_rst_busy_o            (wr_rst_busy_o),\n        .wr_rst_busy              (wr_rst_busy_i),\n        .rd_rst_busy              (rd_rst_busy),\n        .wr_rst_i_out             (wr_rst_int),\n        .rd_rst_i_out             (rd_rst_int)\n       );\n  end endgenerate\n\n\n\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n  localparam C_AXI_SIZE_WIDTH   = 3;\n  localparam C_AXI_BURST_WIDTH  = 2;\n  localparam C_AXI_CACHE_WIDTH  = 4;\n  localparam C_AXI_PROT_WIDTH   = 3;\n  localparam C_AXI_QOS_WIDTH    = 4;\n  localparam C_AXI_REGION_WIDTH = 4;\n  localparam C_AXI_BRESP_WIDTH  = 2;\n  localparam C_AXI_RRESP_WIDTH  = 2;\n\n  localparam IS_AXI_STREAMING  = C_INTERFACE_TYPE == 1 ? 1 : 0;\n  localparam TDATA_OFFSET      = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;\n  localparam TSTRB_OFFSET      = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;\n  localparam TKEEP_OFFSET      = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;\n  localparam TID_OFFSET        = C_HAS_AXIS_TID   == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;\n  localparam TDEST_OFFSET      = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;\n  localparam TUSER_OFFSET      = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;\n  localparam LOG_DEPTH_AXIS    = find_log2(C_WR_DEPTH_AXIS); \n  localparam LOG_WR_DEPTH      = find_log2(C_WR_DEPTH); \n\n\n  function [LOG_DEPTH_AXIS-1:0] bin2gray;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      begin\n         bin2gray = x ^ (x>>1);\n      end\n   endfunction\n\n  function [LOG_DEPTH_AXIS-1:0] gray2bin;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      integer                i;\n      begin\n         gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];\n         for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin\n            gray2bin[i] =  gray2bin[i+1] ^ x[i];\n         end\n      end\n   endfunction\n\nwire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;\nwire  [LOG_WR_DEPTH-1 : 0]  w_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;\nreg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;\nwire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;\nwire [LOG_WR_DEPTH : 0] r_inv_pad;\nwire [LOG_WR_DEPTH-1 : 0] d_cnt;\nreg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;\nreg adj_w_cnt_rd_pad_0 = 0;\nreg r_inv_pad_0 = 0;\n\n\n   genvar l;\n\n   generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (LOG_WR_DEPTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_int), \n         .CLK      (RD_CLK), \n         .DIN      (w_q[l-1]), \n         .DOUT     (w_q[l])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter\n    assign wr_eop_ad = WR_EN & !(FULL);\n    assign rd_eop_ad = RD_EN & !(EMPTY);\n\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt    <= 1'b0;\n      else if (wr_eop_ad)\n        w_cnt    <= w_cnt + 1;\n    end\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt_gc    <= 1'b0;\n      else \n        w_cnt_gc    <= bin2gray(w_cnt);\n    end\n\n\n    assign  w_q[0]  = w_cnt_gc;\n    assign  w_cnt_gc_asreg_last       = w_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        w_cnt_rd    <= 1'b0;\n      else \n        w_cnt_rd    <= gray2bin(w_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        r_cnt    <= 1'b0;\n      else if (rd_eop_ad)\n        r_cnt    <= r_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;\n   assign r_inv_pad[LOG_WR_DEPTH : 1]        = ~r_cnt;\n   assign adj_w_cnt_rd_pad[0]                = adj_w_cnt_rd_pad_0;\n   assign r_inv_pad[0]                       = r_inv_pad_0;\n\n\n  always @ ( rd_eop_ad )\n    begin\n      if (!rd_eop_ad) begin\n        adj_w_cnt_rd_pad_0    <= 1'b1;\n        r_inv_pad_0           <= 1'b1;\n      end else begin \n        adj_w_cnt_rd_pad_0    <= 1'b0;\n        r_inv_pad_0           <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        d_cnt_pad    <= 1'b0;\n      else \n        d_cnt_pad    <= adj_w_cnt_rd_pad + r_inv_pad ;\n    end\n\n   assign  d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;\n   assign  WR_DATA_COUNT = d_cnt;\n\n  end endgenerate // fifo_ic_adapter\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter\n   assign  WR_DATA_COUNT = wr_data_count_in;\n\n  end endgenerate // fifo_icn_adapter\n\n\n\n  wire                          inverted_reset = ~S_ARESETN;\n  wire                          axi_rs_rst;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_din          ;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_dout         ;\n  wire                          axis_full         ;\n  wire                          axis_almost_full  ;\n  wire                          axis_empty        ;\n  wire                          axis_s_axis_tready;\n  wire                          axis_m_axis_tvalid;\n  wire                          axis_wr_en        ;\n  wire                          axis_rd_en        ;\n  wire                          axis_we           ;\n  wire                          axis_re           ;\n  wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;\n  reg                           axis_pkt_read = 1'b0;\n  wire                          axis_rd_rst;\n  wire                          axis_wr_rst;\n\n  generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||\n               C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst\n      reg                           rst_d1 = 0        ;\n      reg                           rst_d2 = 0        ;\n      reg [3:0]                    axi_rst = 4'h0     ;\n      always @ (posedge inverted_reset or posedge S_ACLK) begin\n        if (inverted_reset) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          axi_rst        <= 4'hf;\n        end else begin\n          rst_d1         <= #`TCQ 1'b0;\n          rst_d2         <= #`TCQ rst_d1;\n          axi_rst        <= #`TCQ {axi_rst[2:0],1'b0};\n        end\n      end\n\n      assign axi_rs_rst = axi_rst[3];//rst_d2;\n  end endgenerate // gaxi_rs_rst\n\n  generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming\n\n    // Write protection when almost full or prog_full is high\n    assign axis_we    = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : \n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign axis_re    = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :\n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? axis_we & S_ACLK_EN : axis_we;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE               (C_INTERFACE_TYPE),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 2  || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_AXIS),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_AXIS),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),\n        .C_USE_ECC                      (C_USE_ECC_AXIS),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_AXIS),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_axis_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (axis_wr_en),\n        .RD_EN                    (axis_rd_en),\n        .PROG_FULL_THRESH         (AXIS_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXIS_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .INJECTDBITERR            (AXIS_INJECTDBITERR), \n        .INJECTSBITERR            (AXIS_INJECTSBITERR),\n  \n        .DIN                      (axis_din),\n        .DOUT                     (axis_dout),\n        .FULL                     (axis_full),\n        .EMPTY                    (axis_empty),\n        .ALMOST_FULL              (axis_almost_full),\n        .PROG_FULL                (AXIS_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXIS_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (AXIS_OVERFLOW),\n        .VALID                    (),\n        .UNDERFLOW                (AXIS_UNDERFLOW),\n        .DATA_COUNT               (axis_dc),\n        .RD_DATA_COUNT            (AXIS_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXIS_WR_DATA_COUNT),\n        .SBITERR                  (AXIS_SBITERR),\n        .DBITERR                  (AXIS_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_axis),\n        .rd_rst_busy              (rd_rst_busy_axis),\n        .wr_rst_i_out             (axis_wr_rst),\n        .rd_rst_i_out             (axis_rd_rst),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign axis_s_axis_tready    = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;\n    assign axis_m_axis_tvalid    = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;\n    assign S_AXIS_TREADY         = axis_s_axis_tready;\n    assign M_AXIS_TVALID         = axis_m_axis_tvalid;\n\n  end endgenerate // axi_streaming\n\n  wire axis_wr_eop;\n  reg  axis_wr_eop_d1 = 1'b0;\n  wire axis_rd_eop;\n  integer  axis_pkt_cnt;\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)\n        axis_pkt_read    <= 1'b0;\n      else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_wr_eop_d1    <= 1'b0;\n      else\n        axis_wr_eop_d1   <= axis_wr_eop;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_cnt    <= 0;\n      else if (axis_wr_eop_d1 && ~axis_rd_eop)\n        axis_pkt_cnt    <= axis_pkt_cnt + 1;\n      else if (axis_rd_eop && ~axis_wr_eop_d1)\n        axis_pkt_cnt    <= axis_pkt_cnt - 1;\n    end\n  end endgenerate // gaxis_pkt_fifo_cc\n\n\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;\nwire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;\nwire axis_rd_has_rst;\nwire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;\nwire  [LOG_DEPTH_AXIS-1 : 0]  wpkt_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;\nwire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;\nwire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;\nwire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;\nwire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;\nreg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;\nreg adj_axis_wpkt_cnt_rd_pad_0 = 0;\nreg rpkt_inv_pad_0 = 0;\nwire axis_af_rd ;\n\ngenerate if (C_HAS_RST == 1) begin : rst_blk_has\n  assign axis_rd_has_rst = axis_rd_rst;\nend endgenerate //rst_blk_has\n\ngenerate if (C_HAS_RST == 0) begin :rst_blk_no\n  assign axis_rd_has_rst = 1'b0;\nend endgenerate //rst_blk_no\n\n   genvar i;\n\n   generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (LOG_DEPTH_AXIS)\n        )\n     rd_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (wpkt_q[i-1]), \n         .DOUT     (wpkt_q[i])\n        );\n \n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (1)\n        )\n     wr_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (axis_af_q[i-1]), \n         .DOUT     (axis_af_q[i])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (diff_pkt_cnt == 1))\n        axis_pkt_read    <= 1'b0;\n      else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt    <= 1'b0;\n      else if (axis_wr_eop)\n        axis_wpkt_cnt    <= axis_wpkt_cnt + 1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt_gc    <= 1'b0;\n      else \n        axis_wpkt_cnt_gc    <= bin2gray(axis_wpkt_cnt);\n    end\n\n\n    assign  wpkt_q[0]  = axis_wpkt_cnt_gc;\n    assign  axis_wpkt_cnt_gc_asreg_last       = wpkt_q[C_SYNCHRONIZER_STAGE];\n    assign  axis_af_q[0]                      = axis_almost_full;\n    //assign  axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];\n    assign  axis_af_rd                        = axis_af_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_wpkt_cnt_rd    <= 1'b0;\n      else \n        axis_wpkt_cnt_rd    <= gray2bin(axis_wpkt_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_rpkt_cnt    <= 1'b0;\n      else if (axis_rd_eop)\n        axis_rpkt_cnt    <= axis_rpkt_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;\n   assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1]             = ~axis_rpkt_cnt;\n   assign adj_axis_wpkt_cnt_rd_pad[0]                                = adj_axis_wpkt_cnt_rd_pad_0;\n   assign rpkt_inv_pad[0]                                            = rpkt_inv_pad_0;\n\n\n  always @ ( axis_rd_eop )\n    begin\n      if (!axis_rd_eop) begin\n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b1;\n        rpkt_inv_pad_0                <= 1'b1;\n      end else begin \n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b0;\n        rpkt_inv_pad_0                <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        diff_pkt_cnt_pad    <= 1'b0;\n      else \n        diff_pkt_cnt_pad    <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;\n    end\n\n   assign  diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;\n\n\n\n\n\n   end endgenerate // gaxis_pkt_fifo_ic\n\n\n\n\n  // Generate the accurate data count for axi stream packet fifo configuration\n  reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_dc_pkt_fifo <= 0;\n      else if (axis_wr_en && (~axis_rd_en))\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;\n      else if (~axis_wr_en && axis_rd_en)\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;\n    end\n    assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;\n  end endgenerate // gdc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt\n    assign AXIS_DATA_COUNT = 0;\n  end endgenerate // gndc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc\n    assign AXIS_DATA_COUNT = axis_dc;\n  end endgenerate // gdc\n\n  // Register Slice for Write Address Channel\n  generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_AXIS),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_AXIS)\n            )\n    axis_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (axis_din),\n          .S_VALID                   (axis_wr_en),\n          .S_READY                   (S_AXIS_TREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (axis_dout),\n          .M_VALID                   (M_AXIS_TVALID),\n          .M_READY                   (axis_rd_en)\n          );\n  end endgenerate // gaxis_reg_slice\n\n\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata\n    assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;\n    assign M_AXIS_TDATA   = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb\n    assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;\n    assign M_AXIS_TSTRB   = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep\n    assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;\n    assign M_AXIS_TKEEP   = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid\n    assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;\n    assign M_AXIS_TID     = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest\n    assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;\n    assign M_AXIS_TDEST   = axis_dout[TID_OFFSET-1:TDEST_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser\n    assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;\n    assign M_AXIS_TUSER   = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast\n    assign axis_din[0] = S_AXIS_TLAST;\n    assign M_AXIS_TLAST   = axis_dout[0];\n  end endgenerate\n\n  //###########################################################################\n  //  AXI FULL Write Channel (axi_write_channel)\n  //###########################################################################\n\n  localparam IS_AXI_FULL       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;\n  localparam IS_AXI_LITE       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;\n\n  localparam IS_AXI_FULL_WACH  = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WDCH  = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WRCH  = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RACH  = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RDCH  = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_AXI_LITE_WACH  = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WDCH  = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WRCH  = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RACH  = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RDCH  = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_WR_ADDR_CH     = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;\n  localparam IS_WR_DATA_CH     = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;\n  localparam IS_WR_RESP_CH     = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;\n  localparam IS_RD_ADDR_CH     = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;\n  localparam IS_RD_DATA_CH     = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;\n\n  localparam AWID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;\n  localparam AWADDR_OFFSET     = AWID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam AWLEN_OFFSET      = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;\n  localparam AWSIZE_OFFSET     = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;\n  localparam AWBURST_OFFSET    = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;\n  localparam AWLOCK_OFFSET     = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;\n  localparam AWCACHE_OFFSET    = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;\n  localparam AWPROT_OFFSET     = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam AWQOS_OFFSET      = AWPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam AWREGION_OFFSET   = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;\n  localparam AWUSER_OFFSET     = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;\n\n  localparam WID_OFFSET        = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;\n  localparam WDATA_OFFSET      = WID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam WSTRB_OFFSET      = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;\n  localparam WUSER_OFFSET      = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;\n\n  localparam BID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;\n  localparam BRESP_OFFSET      = BID_OFFSET - C_AXI_BRESP_WIDTH;\n  localparam BUSER_OFFSET      = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;\n\n\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_din          ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout         ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout_pkt     ;\n  wire                          wach_full         ;\n  wire                          wach_almost_full  ;\n  wire                          wach_prog_full    ;\n  wire                          wach_empty        ;\n  wire                          wach_almost_empty ;\n  wire                          wach_prog_empty   ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_din          ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_dout         ;\n  wire                          wdch_full         ;\n  wire                          wdch_almost_full  ;\n  wire                          wdch_prog_full    ;\n  wire                          wdch_empty        ;\n  wire                          wdch_almost_empty ;\n  wire                          wdch_prog_empty   ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_din          ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_dout         ;\n  wire                          wrch_full         ;\n  wire                          wrch_almost_full  ;\n  wire                          wrch_prog_full    ;\n  wire                          wrch_empty        ;\n  wire                          wrch_almost_empty ;\n  wire                          wrch_prog_empty   ;\n  wire                          axi_aw_underflow_i;\n  wire                          axi_w_underflow_i ;\n  wire                          axi_b_underflow_i ;\n  wire                          axi_aw_overflow_i ;\n  wire                          axi_w_overflow_i  ;\n  wire                          axi_b_overflow_i  ;\n  wire                          axi_wr_underflow_i;\n  wire                          axi_wr_overflow_i ;\n  wire                          wach_s_axi_awready;\n  wire                          wach_m_axi_awvalid;\n  wire                          wach_wr_en        ;\n  wire                          wach_rd_en        ;\n  wire                          wdch_s_axi_wready ;\n  wire                          wdch_m_axi_wvalid ;\n  wire                          wdch_wr_en        ;\n  wire                          wdch_rd_en        ;\n  wire                          wrch_s_axi_bvalid ;\n  wire                          wrch_m_axi_bready ;\n  wire                          wrch_wr_en        ;\n  wire                          wrch_rd_en        ;\n  wire                          txn_count_up      ;\n  wire                          txn_count_down    ;\n  wire                          awvalid_en        ;\n  wire                          awvalid_pkt       ;\n  wire                          awready_pkt       ;\n  integer                       wr_pkt_count      ;\n  wire                          wach_we           ;\n  wire                          wach_re           ;\n  wire                          wdch_we           ;\n  wire                          wdch_re           ;\n  wire                          wrch_we           ;\n  wire                          wrch_re           ;\n\n  generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel\n    // Write protection when almost full or prog_full is high\n    assign wach_we    = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wach_re    = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        wach_m_axi_awvalid & awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY && wach_m_axi_awvalid :\n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY : 1'b0;\n    assign wach_wr_en = (C_HAS_SLAVE_CE == 1)  ? wach_we & S_ACLK_EN : wach_we;\n    assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 2  || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),\n        .C_USE_ECC                      (C_USE_ECC_WACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wach_wr_en),\n        .RD_EN                    (wach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AW_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AW_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AW_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AW_INJECTSBITERR),\n  \n        .DIN                      (wach_din),\n        .DOUT                     (wach_dout_pkt),\n        .FULL                     (wach_full),\n        .EMPTY                    (wach_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_AW_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_AW_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_aw_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_aw_underflow_i),\n        .DATA_COUNT               (AXI_AW_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AW_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AW_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AW_SBITERR),\n        .DBITERR                  (AXI_AW_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wach),\n        .rd_rst_busy              (rd_rst_busy_wach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wach_s_axi_awready    = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;\n    assign wach_m_axi_awvalid   = ~wach_empty;\n    assign S_AXI_AWREADY        = wach_s_axi_awready;\n\n    assign AXI_AW_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;\n    assign AXI_AW_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_aw_overflow_i  : 0;\n\n  end endgenerate // axi_write_address_channel\n\n  // Register Slice for Write Address Channel\n  generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WACH)\n            )\n    wach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_din),\n          .S_VALID                   (S_AXI_AWVALID),\n          .S_READY                   (S_AXI_AWREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n  end endgenerate // gwach_reg_slice\n  \n  generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (1)\n            )\n    wach_pkt_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_dout_pkt),\n          .S_VALID                   (awvalid_pkt),\n          .S_READY                   (awready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n\n    assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;\n\n    assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; \n    assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset == 1) begin\n\twr_pkt_count <= 0;\n      end else begin\n\tif(txn_count_up == 1 && txn_count_down == 0) begin\n\t  wr_pkt_count <= wr_pkt_count + 1;\n\tend else if(txn_count_up == 0 && txn_count_down == 1) begin\n\t  wr_pkt_count <= wr_pkt_count - 1;\n\tend\n      end\n    end //Always end\n    assign awvalid_en = (wr_pkt_count > 0)?1:0;\n  end endgenerate\n  \n  generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr\n    assign awvalid_en    = 1;    \n    assign wach_dout     = wach_dout_pkt;\n    assign M_AXI_AWVALID = wach_m_axi_awvalid;\n  end\n  endgenerate\n\n\n\n  generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel\n    // Write protection when almost full or prog_full is high\n    assign wdch_we    = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wdch_re    = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;\n    assign wdch_wr_en = (C_HAS_SLAVE_CE == 1)  ? wdch_we & S_ACLK_EN : wdch_we;\n    assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;\n\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 2  || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),\n        .C_USE_ECC                      (C_USE_ECC_WDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wdch_wr_en),\n        .RD_EN                    (wdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_W_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_W_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_W_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_W_INJECTSBITERR),\n  \n        .DIN                      (wdch_din),\n        .DOUT                     (wdch_dout),\n        .FULL                     (wdch_full),\n        .EMPTY                    (wdch_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_W_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_W_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_w_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_w_underflow_i),\n        .DATA_COUNT               (AXI_W_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_W_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_W_WR_DATA_COUNT),\n        .SBITERR                  (AXI_W_SBITERR),\n        .DBITERR                  (AXI_W_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wdch),\n        .rd_rst_busy              (rd_rst_busy_wdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wdch_s_axi_wready     = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;\n    assign wdch_m_axi_wvalid = ~wdch_empty;\n    assign S_AXI_WREADY      = wdch_s_axi_wready;\n    assign M_AXI_WVALID      = wdch_m_axi_wvalid;\n\n    assign AXI_W_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i  : 0;\n    assign AXI_W_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_w_overflow_i   : 0;\n\n  end endgenerate // axi_write_data_channel\n\n  // Register Slice for Write Data Channel\n  generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WDCH)\n            )\n    wdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wdch_din),\n          .S_VALID                   (S_AXI_WVALID),\n          .S_READY                   (S_AXI_WREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wdch_dout),\n          .M_VALID                   (M_AXI_WVALID),\n          .M_READY                   (M_AXI_WREADY)\n          );\n  end endgenerate // gwdch_reg_slice\n\n  generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel\n    // Write protection when almost full or prog_full is high\n    assign wrch_we    = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wrch_re    = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;\n    assign wrch_wr_en = (C_HAS_MASTER_CE == 1)  ? wrch_we & M_ACLK_EN : wrch_we;\n    assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 2  || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WRCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WRCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),\n        .C_USE_ECC                      (C_USE_ECC_WRCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WRCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WRCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wrch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wrch_wr_en),\n        .RD_EN                    (wrch_rd_en),\n        .PROG_FULL_THRESH         (AXI_B_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_B_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .INJECTDBITERR            (AXI_B_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_B_INJECTSBITERR),\n  \n        .DIN                      (wrch_din),\n        .DOUT                     (wrch_dout),\n        .FULL                     (wrch_full),\n        .EMPTY                    (wrch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_B_PROG_FULL),\n        .PROG_EMPTY               (AXI_B_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_b_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_b_underflow_i),\n        .DATA_COUNT               (AXI_B_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_B_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_B_WR_DATA_COUNT),\n        .SBITERR                  (AXI_B_SBITERR),\n        .DBITERR                  (AXI_B_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wrch),\n        .rd_rst_busy              (rd_rst_busy_wrch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wrch_s_axi_bvalid = ~wrch_empty;\n    assign wrch_m_axi_bready     = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;\n    assign S_AXI_BVALID      = wrch_s_axi_bvalid;\n    assign M_AXI_BREADY      = wrch_m_axi_bready;\n\n    assign AXI_B_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i  : 0;\n    assign AXI_B_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_b_overflow_i   : 0;\n  end endgenerate // axi_write_resp_channel\n\n  // Register Slice for Write Response Channel\n  generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WRCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WRCH)\n            )\n    wrch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wrch_din),\n          .S_VALID                   (M_AXI_BVALID),\n          .S_READY                   (M_AXI_BREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wrch_dout),\n          .M_VALID                   (S_AXI_BVALID),\n          .M_READY                   (S_AXI_BREADY)\n          );\n  end endgenerate // gwrch_reg_slice\n\n\n    assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW  == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;\n    assign axi_wr_overflow_i  = C_USE_COMMON_OVERFLOW   == 1 ? (axi_aw_overflow_i  || axi_w_overflow_i  || axi_b_overflow_i)  : 0;\n\n  generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output\n    assign M_AXI_AWADDR    = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];    \n    assign M_AXI_AWLEN     = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];    \n    assign M_AXI_AWSIZE    = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];    \n    assign M_AXI_AWBURST   = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];    \n    assign M_AXI_AWLOCK    = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];    \n    assign M_AXI_AWCACHE   = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];    \n    assign M_AXI_AWQOS     = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];    \n    assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET]    = S_AXI_AWADDR;\n    assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET]   = S_AXI_AWLEN;\n    assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET]   = S_AXI_AWSIZE;\n    assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;\n    assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;\n    assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;\n    assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;\n    assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET]   = S_AXI_AWQOS;\n  end endgenerate // axi_wach_output\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion\n    assign M_AXI_AWREGION  = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];    \n  end endgenerate // axi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion\n    assign M_AXI_AWREGION  = 0;    \n  end endgenerate // naxi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser\n    assign M_AXI_AWUSER  = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];    \n  end endgenerate // axi_awuser\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser\n    assign M_AXI_AWUSER  = 0;    \n  end endgenerate // naxi_awuser\n\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid\n    assign M_AXI_AWID      = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];\n  end endgenerate //axi_awid\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid\n    assign M_AXI_AWID      = 0;\n  end endgenerate //naxi_awid\n\n  generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output\n    assign M_AXI_WDATA     = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n    assign M_AXI_WLAST     = wdch_dout[0];\n    assign wdch_din[WID_OFFSET-1:WDATA_OFFSET]   = S_AXI_WDATA;\n    assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;\n    assign wdch_din[0]   = S_AXI_WLAST;\n  end endgenerate // axi_wdch_output\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin\n    assign M_AXI_WID       = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];\n  end endgenerate\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin\n    assign M_AXI_WID       = 0;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin\n    assign M_AXI_WUSER     = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];    \n  end endgenerate\n  generate if (C_HAS_AXI_WUSER == 0) begin\n    assign M_AXI_WUSER       = 0;\n  end endgenerate\n\n  generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output\n    assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; \n    assign wrch_din[BID_OFFSET-1:BRESP_OFFSET]   = M_AXI_BRESP;\n  end endgenerate // axi_wrch_output\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser\n    assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];\n  end endgenerate // axi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser\n    assign S_AXI_BUSER = 0;\n  end endgenerate // naxi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid\n    assign S_AXI_BID   =  wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];\n  end endgenerate // axi_bid\n  \n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid\n    assign S_AXI_BID   =  0 ;\n  end endgenerate // naxi_bid  \n\n\n  generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1\n    assign wach_din        = {S_AXI_AWADDR, S_AXI_AWPROT};\n    assign M_AXI_AWADDR    = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];    \n  end endgenerate // axi_wach_output1\n\n  generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1\n    assign wdch_din        = {S_AXI_WDATA, S_AXI_WSTRB};\n    assign M_AXI_WDATA     = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n  end endgenerate // axi_wdch_output1\n\n  generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1\n    assign wrch_din        = M_AXI_BRESP;\n    assign S_AXI_BRESP     = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; \n  end endgenerate // axi_wrch_output1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1\n    assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET]     = S_AXI_AWUSER;\n  end endgenerate // gwach_din1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2\n    assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET]     = S_AXI_AWID;\n  end endgenerate // gwach_din2\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3\n    assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET]     = S_AXI_AWREGION;\n  end endgenerate // gwach_din3\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1\n    assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;\n  end endgenerate // gwdch_din1\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2\n    assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;\n  end endgenerate // gwdch_din2\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1\n    assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET]    = M_AXI_BUSER;\n  end endgenerate // gwrch_din1\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2\n    assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET]    = M_AXI_BID;\n  end endgenerate // gwrch_din2\n\n  //end of  axi_write_channel\n\n  //###########################################################################\n  //  AXI FULL Read Channel (axi_read_channel)\n  //###########################################################################\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_din            ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout           ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout_pkt       ;\n  wire                               rach_full           ;\n  wire                               rach_almost_full    ;\n  wire                               rach_prog_full      ;\n  wire                               rach_empty          ;\n  wire                               rach_almost_empty   ;\n  wire                               rach_prog_empty     ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_din            ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_dout           ;\n  wire                               rdch_full           ;\n  wire                               rdch_almost_full    ;\n  wire                               rdch_prog_full      ;\n  wire                               rdch_empty          ;\n  wire                               rdch_almost_empty   ;\n  wire                               rdch_prog_empty     ;\n  wire                               axi_ar_underflow_i  ;\n  wire                               axi_r_underflow_i   ;\n  wire                               axi_ar_overflow_i   ;\n  wire                               axi_r_overflow_i    ;\n  wire                               axi_rd_underflow_i  ;\n  wire                               axi_rd_overflow_i   ;\n  wire                               rach_s_axi_arready  ;\n  wire                               rach_m_axi_arvalid  ;\n  wire                               rach_wr_en          ;\n  wire                               rach_rd_en          ;\n  wire                               rdch_m_axi_rready   ;\n  wire                               rdch_s_axi_rvalid   ;\n  wire                               rdch_wr_en          ;\n  wire                               rdch_rd_en          ;\n  wire                               arvalid_pkt         ;\n  wire                               arready_pkt         ;\n  wire                               arvalid_en          ;\n  wire                               rdch_rd_ok          ;\n  wire                               accept_next_pkt     ;\n  integer                            rdch_free_space     ;\n  integer                            rdch_commited_space ;\n  wire                               rach_we             ;\n  wire                               rach_re             ;\n  wire                               rdch_we             ;\n  wire                               rdch_re             ;\n\n  localparam ARID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;\n  localparam ARADDR_OFFSET     = ARID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam ARLEN_OFFSET      = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;\n  localparam ARSIZE_OFFSET     = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;\n  localparam ARBURST_OFFSET    = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;\n  localparam ARLOCK_OFFSET     = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;\n  localparam ARCACHE_OFFSET    = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;\n  localparam ARPROT_OFFSET     = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam ARQOS_OFFSET      = ARPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam ARREGION_OFFSET   = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;\n  localparam ARUSER_OFFSET     = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;\n\n  localparam RID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;\n  localparam RDATA_OFFSET      = RID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam RRESP_OFFSET      = RDATA_OFFSET - C_AXI_RRESP_WIDTH;\n  localparam RUSER_OFFSET      = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;\n\n\n  generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rach_we    = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;\n\n    // Read protection when almost empty or prog_empty is high\n//    assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;\n    assign rach_re    = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        rach_m_axi_arvalid & arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY && rach_m_axi_arvalid :\n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY : 1'b0;\n    assign rach_wr_en = (C_HAS_SLAVE_CE == 1)  ? rach_we & S_ACLK_EN : rach_we;\n    assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;\n\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 2  || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),\n        .C_USE_ECC                      (C_USE_ECC_RACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_rach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rach_wr_en),\n        .RD_EN                    (rach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AR_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AR_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AR_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AR_INJECTSBITERR),\n  \n        .DIN                      (rach_din),\n        .DOUT                     (rach_dout_pkt),\n        .FULL                     (rach_full),\n        .EMPTY                    (rach_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_AR_PROG_FULL),\n        .PROG_EMPTY               (AXI_AR_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_ar_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_ar_underflow_i),\n        .DATA_COUNT               (AXI_AR_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AR_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AR_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AR_SBITERR),\n        .DBITERR                  (AXI_AR_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rach),\n        .rd_rst_busy              (rd_rst_busy_rach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rach_s_axi_arready    = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;\n    assign rach_m_axi_arvalid = ~rach_empty;\n    assign S_AXI_ARREADY      = rach_s_axi_arready;\n\n    assign AXI_AR_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;\n    assign AXI_AR_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_ar_overflow_i  : 0;\n\n  end endgenerate // axi_read_addr_channel\n\n  // Register Slice for Read Address Channel\n  generate if (C_RACH_TYPE == 1) begin : grach_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RACH)\n            )\n    rach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_din),\n          .S_VALID                   (S_AXI_ARVALID),\n          .S_READY                   (S_AXI_ARREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice\n\n  // Register Slice for Read Address Channel for MM Packet FIFO\n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (1)\n            )\n    reg_slice_mm_pkt_fifo_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_dout_pkt),\n          .S_VALID                   (arvalid_pkt),\n          .S_READY                   (arready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice_mm_pkt_fifo\n\n  \n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid\n    assign M_AXI_ARVALID      = rach_m_axi_arvalid;\n    assign rach_dout          = rach_dout_pkt;\n  end endgenerate // grach_m_axi_arvalid\n  \n  \n  generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd\n    assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;\n    assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;\n    assign accept_next_pkt  = rach_m_axi_arvalid && arready_pkt && arvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset) begin\n\trdch_commited_space <= 0;\n      end else begin\n\tif(rdch_rd_ok && !accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space-1;\n\tend else if(!rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);\n\tend else if(rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);\n\tend\n      end\n    end //Always end\n\n    always@(*) begin\n      rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));\n    end\n\n    assign arvalid_en = (rdch_free_space >= 0)?1:0;\n  end\n  endgenerate\n  \n  generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd\n    assign arvalid_en = 1;    \n  end\n  endgenerate\n\n  generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rdch_we    = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready  & M_AXI_RVALID : M_AXI_RVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign rdch_re    = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid  & S_AXI_RREADY : S_AXI_RREADY;\n    assign rdch_wr_en = (C_HAS_MASTER_CE == 1)  ? rdch_we & M_ACLK_EN : rdch_we;\n    assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 2  || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),\n        .C_USE_ECC                      (C_USE_ECC_RDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_RDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_rdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rdch_wr_en),\n        .RD_EN                    (rdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_R_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_R_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_R_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_R_INJECTSBITERR),\n  \n        .DIN                      (rdch_din),\n        .DOUT                     (rdch_dout),\n        .FULL                     (rdch_full),\n        .EMPTY                    (rdch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_R_PROG_FULL),\n        .PROG_EMPTY               (AXI_R_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_r_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_r_underflow_i),\n        .DATA_COUNT               (AXI_R_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_R_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_R_WR_DATA_COUNT),\n        .SBITERR                  (AXI_R_SBITERR),\n        .DBITERR                  (AXI_R_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rdch),\n        .rd_rst_busy              (rd_rst_busy_rdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rdch_s_axi_rvalid = ~rdch_empty;\n    assign rdch_m_axi_rready     = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;\n    assign S_AXI_RVALID      = rdch_s_axi_rvalid;\n    assign M_AXI_RREADY      = rdch_m_axi_rready;\n\n    assign AXI_R_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i  : 0;\n    assign AXI_R_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_r_overflow_i   : 0;\n\n  end endgenerate //axi_read_data_channel\n\n  // Register Slice for read Data Channel\n  generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RDCH)\n            )\n    rdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rdch_din),\n          .S_VALID                   (M_AXI_RVALID),\n          .S_READY                   (M_AXI_RREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rdch_dout),\n          .M_VALID                   (S_AXI_RVALID),\n          .M_READY                   (S_AXI_RREADY)\n          );\n  end endgenerate // grdch_reg_slice\n\n\n    assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;\n    assign axi_rd_overflow_i  = C_USE_COMMON_OVERFLOW  == 1 ? (axi_ar_overflow_i  || axi_r_overflow_i) : 0;\n\n\n  generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output\n    assign M_AXI_ARADDR    = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];    \n    assign M_AXI_ARLEN     = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];    \n    assign M_AXI_ARSIZE    = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];    \n    assign M_AXI_ARBURST   = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];    \n    assign M_AXI_ARLOCK    = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];    \n    assign M_AXI_ARCACHE   = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];    \n    assign M_AXI_ARPROT    = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];    \n    assign M_AXI_ARQOS     = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];    \n    assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET]    = S_AXI_ARADDR;\n    assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET]   = S_AXI_ARLEN;\n    assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET]   = S_AXI_ARSIZE;\n    assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;\n    assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;\n    assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;\n    assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;\n    assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET]   = S_AXI_ARQOS;\n  end endgenerate // axi_full_rach_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion\n    assign M_AXI_ARREGION  = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];    \n  end endgenerate // axi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion\n    assign M_AXI_ARREGION  = 0;    \n  end endgenerate // naxi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser\n    assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];    \n  end endgenerate // axi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser\n    assign M_AXI_ARUSER = 0;    \n  end endgenerate // naxi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid\n    assign M_AXI_ARID      = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];\n  end endgenerate // axi_arid\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid\n    assign M_AXI_ARID      = 0;\n  end endgenerate // naxi_arid\n\n  generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output\n    assign S_AXI_RDATA     = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];\n    assign S_AXI_RRESP     = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n    assign S_AXI_RLAST     = rdch_dout[0];\n    assign rdch_din[RID_OFFSET-1:RDATA_OFFSET]   = M_AXI_RDATA;\n    assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;\n    assign rdch_din[0] = M_AXI_RLAST;\n  end endgenerate // axi_full_rdch_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output\n    assign S_AXI_RUSER     = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];\n  end endgenerate // axi_full_ruser_output\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output\n    assign S_AXI_RUSER     =  0;\n  end endgenerate // axi_full_nruser_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid\n    assign S_AXI_RID       = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];\n  end endgenerate // axi_rid\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid\n    assign S_AXI_RID       = 0;\n  end endgenerate // naxi_rid\n\n  generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1\n    assign rach_din      = {S_AXI_ARADDR, S_AXI_ARPROT};\n    assign M_AXI_ARADDR  = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];\n    assign M_AXI_ARPROT  = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];\n  end endgenerate // axi_lite_rach_output\n\n  generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1\n    assign rdch_din      = {M_AXI_RDATA, M_AXI_RRESP};\n    assign S_AXI_RDATA   = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];\n    assign S_AXI_RRESP   = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n  end endgenerate // axi_lite_rdch_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1\n    assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET]     = S_AXI_ARUSER;\n  end endgenerate // grach_din1\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2\n    assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET]     = S_AXI_ARID;\n  end endgenerate // grach_din2\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin\n    assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1\n    assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET]     = M_AXI_RUSER;\n  end endgenerate // grdch_din1\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2\n    assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;\n  end endgenerate // grdch_din2\n\n  //end of axi_read_channel\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf\n    assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :\n                       (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :\n                       (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;\n  end endgenerate // gaxi_comm_uf\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of\n    assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :\n                      (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :\n                      (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;\n  end endgenerate // gaxi_comm_of\n  \n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  // Pass Through Logic or Wiring Logic\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  \n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Write Address Channel\n  generate if (C_WACH_TYPE == 2) begin : gwach_pass_through\n    assign M_AXI_AWID      = S_AXI_AWID;\n    assign M_AXI_AWADDR    = S_AXI_AWADDR;\n    assign M_AXI_AWLEN     = S_AXI_AWLEN;\n    assign M_AXI_AWSIZE    = S_AXI_AWSIZE;\n    assign M_AXI_AWBURST   = S_AXI_AWBURST;\n    assign M_AXI_AWLOCK    = S_AXI_AWLOCK;\n    assign M_AXI_AWCACHE   = S_AXI_AWCACHE;\n    assign M_AXI_AWPROT    = S_AXI_AWPROT;\n    assign M_AXI_AWQOS     = S_AXI_AWQOS;\n    assign M_AXI_AWREGION  = S_AXI_AWREGION;\n    assign M_AXI_AWUSER    = S_AXI_AWUSER;\n    assign S_AXI_AWREADY   = M_AXI_AWREADY;\n    assign M_AXI_AWVALID   = S_AXI_AWVALID;\n  end endgenerate // gwach_pass_through;\n\n  // Wiring logic for Write Data Channel\n  generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through\n    assign M_AXI_WID       = S_AXI_WID;\n    assign M_AXI_WDATA     = S_AXI_WDATA;\n    assign M_AXI_WSTRB     = S_AXI_WSTRB;\n    assign M_AXI_WLAST     = S_AXI_WLAST;\n    assign M_AXI_WUSER     = S_AXI_WUSER;\n    assign S_AXI_WREADY    = M_AXI_WREADY;\n    assign M_AXI_WVALID    = S_AXI_WVALID;\n  end endgenerate // gwdch_pass_through;\n\n  // Wiring logic for Write Response Channel\n  generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through\n    assign S_AXI_BID       = M_AXI_BID;\n    assign S_AXI_BRESP     = M_AXI_BRESP;\n    assign S_AXI_BUSER     = M_AXI_BUSER;\n    assign M_AXI_BREADY    = S_AXI_BREADY;\n    assign S_AXI_BVALID    = M_AXI_BVALID;\n  end endgenerate // gwrch_pass_through;\n\n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Read Address Channel\n  generate if (C_RACH_TYPE == 2) begin : grach_pass_through\n    assign M_AXI_ARID      = S_AXI_ARID;\n    assign M_AXI_ARADDR    = S_AXI_ARADDR;\n    assign M_AXI_ARLEN     = S_AXI_ARLEN;\n    assign M_AXI_ARSIZE    = S_AXI_ARSIZE;\n    assign M_AXI_ARBURST   = S_AXI_ARBURST;\n    assign M_AXI_ARLOCK    = S_AXI_ARLOCK;\n    assign M_AXI_ARCACHE   = S_AXI_ARCACHE;\n    assign M_AXI_ARPROT    = S_AXI_ARPROT;\n    assign M_AXI_ARQOS     = S_AXI_ARQOS;\n    assign M_AXI_ARREGION  = S_AXI_ARREGION;\n    assign M_AXI_ARUSER    = S_AXI_ARUSER;\n    assign S_AXI_ARREADY   = M_AXI_ARREADY;\n    assign M_AXI_ARVALID   = S_AXI_ARVALID;\n  end endgenerate // grach_pass_through;\n\n  // Wiring logic for Read Data Channel \n  generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through\n    assign S_AXI_RID      = M_AXI_RID;\n    assign S_AXI_RLAST    = M_AXI_RLAST;\n    assign S_AXI_RUSER    = M_AXI_RUSER;\n    assign S_AXI_RDATA    = M_AXI_RDATA;\n    assign S_AXI_RRESP    = M_AXI_RRESP;\n    assign S_AXI_RVALID   = M_AXI_RVALID;\n    assign M_AXI_RREADY   = S_AXI_RREADY;\n  end endgenerate // grdch_pass_through;\n\n  // Wiring logic for AXI Streaming\n  generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through\n    assign M_AXIS_TDATA   = S_AXIS_TDATA;\n    assign M_AXIS_TSTRB   = S_AXIS_TSTRB;\n    assign M_AXIS_TKEEP   = S_AXIS_TKEEP;\n    assign M_AXIS_TID     = S_AXIS_TID;\n    assign M_AXIS_TDEST   = S_AXIS_TDEST;\n    assign M_AXIS_TUSER   = S_AXIS_TUSER;\n    assign M_AXIS_TLAST   = S_AXIS_TLAST;\n    assign S_AXIS_TREADY  = M_AXIS_TREADY;\n    assign M_AXIS_TVALID  = S_AXIS_TVALID;\n  end endgenerate // gaxis_pass_through;\n\n\nendmodule //fifo_generator_v13_2_5\n\n\n\n/*******************************************************************************\n * Declaration of top-level module for Conventional FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_CONV_VER\n  #(\n    parameter  C_COMMON_CLOCK                 = 0,\n    parameter  C_INTERFACE_TYPE               = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_COUNT_TYPE                   = 0,\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DEFAULT_VALUE                = \"\",\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_ENABLE_RLOCS                 = 0,\n    parameter  C_FAMILY                       = \"virtex7\", //Not allowed in Verilog model\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_BACKUP                   = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_INT_CLK                  = 0,\n    parameter  C_HAS_MEMINIT_FILE             = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RD_RST                   = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_RST                   = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_INIT_WR_PNTR_VAL             = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_MIF_FILE_NAME                = \"\",\n    parameter  C_OPTIMIZATION_MODE            = 0,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PRIM_FIFO_TYPE               = \"\",\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_FREQ                      = 1,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_ECC                      = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_USE_FIFO16_FLAGS             = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_FREQ                      = 1,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_WR_RESPONSE_LATENCY          = 1,\n    parameter  C_MSGON_VAL                    = 1,\n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2,\n    parameter  C_AXI_TYPE                     = 0\n   )\n\n  (\n   input                               BACKUP,\n   input                               BACKUP_MARKER,\n   input                               CLK,\n   input                               RST,\n   input                               SRST,\n   input                               WR_CLK,\n   input                               WR_RST,\n   input                               RD_CLK,\n   input                               RD_RST,\n   input [C_DIN_WIDTH-1:0]             DIN,\n   input                               WR_EN,\n   input                               RD_EN,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_ASSERT,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_NEGATE,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_ASSERT,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_NEGATE,\n   input                               INT_CLK,\n   input                               INJECTDBITERR,\n   input                               INJECTSBITERR,\n  \n   output [C_DOUT_WIDTH-1:0]           DOUT,\n   output                              FULL,\n   output                              ALMOST_FULL,\n   output                              WR_ACK,\n   output                              OVERFLOW,\n   output                              EMPTY,\n   output                              ALMOST_EMPTY,\n   output                              VALID,\n   output                              UNDERFLOW,\n   output [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT,\n   output [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT,\n   output [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT,\n   output                              PROG_FULL,\n   output                              PROG_EMPTY,\n   output                              SBITERR,\n   output                              DBITERR,\n   output                              wr_rst_busy_o,\n   output                              wr_rst_busy,\n   output                              rd_rst_busy,\n   output                              wr_rst_i_out,\n   output                              rd_rst_i_out\n  );\n\n/*\n ******************************************************************************\n * Definition of Parameters\n ******************************************************************************\n *     C_COMMON_CLOCK                : Common Clock (1), Independent Clocks (0)\n *     C_COUNT_TYPE                  :    *not used\n *     C_DATA_COUNT_WIDTH            : Width of DATA_COUNT bus\n *     C_DEFAULT_VALUE               :    *not used\n *     C_DIN_WIDTH                   : Width of DIN bus\n *     C_DOUT_RST_VAL                : Reset value of DOUT\n *     C_DOUT_WIDTH                  : Width of DOUT bus\n *     C_ENABLE_RLOCS                :    *not used\n *     C_FAMILY                      : not used in bhv model\n *     C_FULL_FLAGS_RST_VAL          : Full flags rst val (0 or 1)\n *     C_HAS_ALMOST_EMPTY            : 1=Core has ALMOST_EMPTY flag\n *     C_HAS_ALMOST_FULL             : 1=Core has ALMOST_FULL flag\n *     C_HAS_BACKUP                  :    *not used\n *     C_HAS_DATA_COUNT              : 1=Core has DATA_COUNT bus\n *     C_HAS_INT_CLK                 : not used in bhv model\n *     C_HAS_MEMINIT_FILE            :    *not used\n *     C_HAS_OVERFLOW                : 1=Core has OVERFLOW flag\n *     C_HAS_RD_DATA_COUNT           : 1=Core has RD_DATA_COUNT bus\n *     C_HAS_RD_RST                  :    *not used\n *     C_HAS_RST                     : 1=Core has Async Rst\n *     C_HAS_SRST                    : 1=Core has Sync Rst\n *     C_HAS_UNDERFLOW               : 1=Core has UNDERFLOW flag\n *     C_HAS_VALID                   : 1=Core has VALID flag\n *     C_HAS_WR_ACK                  : 1=Core has WR_ACK flag\n *     C_HAS_WR_DATA_COUNT           : 1=Core has WR_DATA_COUNT bus\n *     C_HAS_WR_RST                  :    *not used\n *     C_IMPLEMENTATION_TYPE         : 0=Common-Clock Bram/Dram\n *                                     1=Common-Clock ShiftRam\n *                                     2=Indep. Clocks Bram/Dram\n *                                     3=Virtex-4 Built-in\n *                                     4=Virtex-5 Built-in\n *     C_INIT_WR_PNTR_VAL            :   *not used\n *     C_MEMORY_TYPE                 : 1=Block RAM\n *                                     2=Distributed RAM\n *                                     3=Shift RAM\n *                                     4=Built-in FIFO\n *     C_MIF_FILE_NAME               :   *not used\n *     C_OPTIMIZATION_MODE           :   *not used\n *     C_OVERFLOW_LOW                : 1=OVERFLOW active low\n *     C_PRELOAD_LATENCY             : Latency of read: 0, 1, 2\n *     C_PRELOAD_REGS                : 1=Use output registers\n *     C_PRIM_FIFO_TYPE              : not used in bhv model\n *     C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold\n *     C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold\n *     C_PROG_EMPTY_TYPE             : 0=No programmable empty\n *                                     1=Single prog empty thresh constant\n *                                     2=Multiple prog empty thresh constants\n *                                     3=Single prog empty thresh input\n *                                     4=Multiple prog empty thresh inputs\n *     C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold\n *     C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold\n *     C_PROG_FULL_TYPE              : 0=No prog full\n *                                     1=Single prog full thresh constant\n *                                     2=Multiple prog full thresh constants\n *                                     3=Single prog full thresh input\n *                                     4=Multiple prog full thresh inputs\n *     C_RD_DATA_COUNT_WIDTH         : Width of RD_DATA_COUNT bus\n *     C_RD_DEPTH                    : Depth of read interface (2^N)\n *     C_RD_FREQ                     : not used in bhv model\n *     C_RD_PNTR_WIDTH               : always log2(C_RD_DEPTH)\n *     C_UNDERFLOW_LOW               : 1=UNDERFLOW active low\n *     C_USE_DOUT_RST                : 1=Resets DOUT on RST\n *     C_USE_ECC                     : Used for error injection purpose\n *     C_USE_EMBEDDED_REG            : 1=Use BRAM embedded output register\n *     C_USE_FIFO16_FLAGS            : not used in bhv model\n *     C_USE_FWFT_DATA_COUNT         : 1=Use extra logic for FWFT data count\n *     C_VALID_LOW                   : 1=VALID active low\n *     C_WR_ACK_LOW                  : 1=WR_ACK active low\n *     C_WR_DATA_COUNT_WIDTH         : Width of WR_DATA_COUNT bus\n *     C_WR_DEPTH                    : Depth of write interface (2^N)\n *     C_WR_FREQ                     : not used in bhv model\n *     C_WR_PNTR_WIDTH               : always log2(C_WR_DEPTH)\n *     C_WR_RESPONSE_LATENCY         :    *not used\n *     C_MSGON_VAL                   :    *not used by bhv model\n *     C_ENABLE_RST_SYNC             : 0 = Use WR_RST & RD_RST\n *                                     1 = Use RST\n *     C_ERROR_INJECTION_TYPE        : 0 = No error injection\n *                                     1 = Single bit error injection only\n *                                     2 = Double bit error injection only\n *                                     3 = Single and double bit error injection\n ******************************************************************************\n * Definition of Ports\n ******************************************************************************\n *   BACKUP       : Not used\n *   BACKUP_MARKER: Not used\n *   CLK          : Clock\n *   DIN          : Input data bus\n *   PROG_EMPTY_THRESH       : Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag\n *   PROG_FULL_THRESH        : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag\n *   RD_CLK       : Read Domain Clock\n *   RD_EN        : Read enable\n *   RD_RST       : Read Reset\n *   RST          : Asynchronous Reset\n *   SRST         : Synchronous Reset\n *   WR_CLK       : Write Domain Clock\n *   WR_EN        : Write enable\n *   WR_RST       : Write Reset\n *   INT_CLK      : Internal Clock\n *   INJECTSBITERR: Inject Signle bit error\n *   INJECTDBITERR: Inject Double bit error\n *   ALMOST_EMPTY : One word remaining in FIFO\n *   ALMOST_FULL  : One empty space remaining in FIFO\n *   DATA_COUNT   : Number of data words in fifo( synchronous to CLK)\n *   DOUT         : Output data bus\n *   EMPTY        : Empty flag\n *   FULL         : Full flag\n *   OVERFLOW     : Last write rejected\n *   PROG_EMPTY   : Programmable Empty Flag\n *   PROG_FULL    : Programmable Full Flag\n *   RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)\n *   UNDERFLOW    : Last read rejected\n *   VALID        : Last read acknowledged, DOUT bus VALID\n *   WR_ACK       : Last write acknowledged\n *   WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)\n *   SBITERR      : Single Bit ECC Error Detected\n *   DBITERR      : Double Bit ECC Error Detected\n ******************************************************************************\n */\n\n  //----------------------------------------------------------------------------\n  //- Internal Signals for delayed input signals\n  //- All the input signals except Clock are delayed by 100 ps and then given to\n  //- the models.\n  //----------------------------------------------------------------------------\n \n  reg                         rst_delayed                       ;\n  reg                         empty_fb                       ;\n  reg                         srst_delayed                      ;\n  reg                         wr_rst_delayed                    ;\n  reg                         rd_rst_delayed                    ;\n  reg                         wr_en_delayed                     ;\n  reg                         rd_en_delayed                     ;\n  reg  [C_DIN_WIDTH-1:0]      din_delayed                       ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_delayed         ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_assert_delayed  ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_negate_delayed  ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_delayed          ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_assert_delayed   ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_negate_delayed   ;\n  reg                         injectdbiterr_delayed             ;\n  reg                         injectsbiterr_delayed             ;\n   wire                        empty_p0_out;\n\n  always @* rst_delayed                       <= #`TCQ RST                      ;\n  always @* empty_fb                       <= #`TCQ empty_p0_out                      ;\n  always @* srst_delayed                      <= #`TCQ SRST                     ; \n  always @* wr_rst_delayed                    <= #`TCQ WR_RST                   ; \n  always @* rd_rst_delayed                    <= #`TCQ RD_RST                   ; \n  always @* din_delayed                       <= #`TCQ DIN                      ; \n  always @* wr_en_delayed                     <= #`TCQ WR_EN                    ; \n  always @* rd_en_delayed                     <= #`TCQ RD_EN                    ; \n  always @* prog_empty_thresh_delayed         <= #`TCQ PROG_EMPTY_THRESH        ; \n  always @* prog_empty_thresh_assert_delayed  <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; \n  always @* prog_empty_thresh_negate_delayed  <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; \n  always @* prog_full_thresh_delayed          <= #`TCQ PROG_FULL_THRESH         ; \n  always @* prog_full_thresh_assert_delayed   <= #`TCQ PROG_FULL_THRESH_ASSERT  ; \n  always @* prog_full_thresh_negate_delayed   <= #`TCQ PROG_FULL_THRESH_NEGATE  ; \n  always @* injectdbiterr_delayed             <= #`TCQ INJECTDBITERR            ; \n  always @* injectsbiterr_delayed             <= #`TCQ INJECTSBITERR            ; \n\n  /*****************************************************************************\n   * Derived parameters\n   ****************************************************************************/\n  //There are 2 Verilog behavioral models\n  // 0 = Common-Clock FIFO/ShiftRam FIFO\n  // 1 = Independent Clocks FIFO\n  // 2 = Low Latency Synchronous FIFO\n  // 3 = Low Latency Asynchronous FIFO\n  localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :\n                              (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n\n  //Internal reset signals\n  reg                                rd_rst_asreg    = 1'b0;\n  reg                                rd_rst_asreg_d1 = 1'b0;\n  reg                                rd_rst_asreg_d2 = 1'b0;\n  reg                                rd_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_reg      = 1'b0;\n  reg                                rd_rst_comb     = 1'b1;\n  reg                                rd_rst_comb_d1  = 1'b0;\n  reg                                wr_rst_d0       = 1'b0;\n  reg                                wr_rst_d1       = 1'b0;\n  reg                                wr_rst_d2       = 1'b0;\n  reg                                rd_rst_d0       = 1'b0;\n  reg                                rd_rst_d1       = 1'b0;\n  reg                                rd_rst_d2       = 1'b0;\n  reg                                rd_rst_d3       = 1'b0;\n  reg                                wrrst_done      = 1'b0;\n  reg                                rdrst_done      = 1'b0;\n  reg                                wr_rst_asreg    = 1'b0;\n  reg                                wr_rst_asreg_d1 = 1'b0;\n  reg                                wr_rst_asreg_d2 = 1'b0;\n  reg                                wr_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_wr_d0    = 1'b0;\n  reg                                rd_rst_wr_d1    = 1'b0;\n  reg                                rd_rst_wr_d2    = 1'b0;\n  reg                                wr_rst_reg      = 1'b0;\n  reg                                rst_active_i    = 1'b1;\n  reg                                rst_delayed_d1  = 1'b1;\n  reg                                rst_delayed_d2  = 1'b1;\n  reg                                wr_rst_comb     = 1'b1;\n  reg                                wr_rst_comb_d1  = 1'b0;\n  wire                               wr_rst_i;\n  wire                               rd_rst_i;\n  wire                               rst_i;\n\n  //Internal reset signals\n  reg                                rst_asreg     = 1'b0;\n  reg                                srst_asreg    = 1'b0;\n  reg                                rst_asreg_d1  = 1'b0;\n  reg                                rst_asreg_d2  = 1'b0;\n  reg                                srst_asreg_d1 = 1'b0;\n  reg                                srst_asreg_d2 = 1'b0;\n  reg                                rst_reg       = 1'b0;\n  reg                                srst_reg      = 1'b0;\n  reg                                rst_comb      = 1'b1;\n  reg                                rst_comb_d1   = 1'b0;\n  wire                               srst_comb;\n  reg                                rst_full_gen_i = 0;\n  reg                                rst_full_ff_i = 0;\n  reg  [2:0]                         sckt_ff0_bsy_o_i = {3{1'b0}};\n                                     \n  wire                               RD_CLK_P0_IN;\n  wire                               RST_P0_IN;\n  wire                               RD_EN_FIFO_IN;\n  wire                               RD_EN_P0_IN;\n\n  wire                               ALMOST_EMPTY_FIFO_OUT;\n  wire                               ALMOST_FULL_FIFO_OUT;\n  wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT_FIFO_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DOUT_FIFO_OUT;\n  wire                               EMPTY_FIFO_OUT;\n  wire                               fifo_empty_fb;\n  wire                               FULL_FIFO_OUT;\n  wire                               OVERFLOW_FIFO_OUT;\n  wire                               PROG_EMPTY_FIFO_OUT;\n  wire                               PROG_FULL_FIFO_OUT;\n  wire                               VALID_FIFO_OUT;\n  wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT_FIFO_OUT;\n  wire                               UNDERFLOW_FIFO_OUT;\n  wire                               WR_ACK_FIFO_OUT;\n  wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT_FIFO_OUT;\n\n\n  //***************************************************************************\n  // Internal Signals\n  //   The core uses either the internal_ wires or the preload0_ wires depending\n  //     on whether the core uses Preload0 or not.\n  //   When using preload0, the internal signals connect the internal core to\n  //     the preload logic, and the external core's interfaces are tied to the\n  //     preload0 signals from the preload logic.\n  //***************************************************************************\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_OUT;\n  wire                               VALID_P0_OUT;\n  wire                               EMPTY_P0_OUT;\n  wire                               ALMOSTEMPTY_P0_OUT;\n  reg                                EMPTY_P0_OUT_Q;\n  reg                                ALMOSTEMPTY_P0_OUT_Q;\n  wire                               UNDERFLOW_P0_OUT;\n  wire                               RDEN_P0_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_IN;\n  wire                               EMPTY_P0_IN;\n  reg  [31:0]                        DATA_COUNT_FWFT;\n  reg                                SS_FWFT_WR  ;\n  reg                                SS_FWFT_RD ;\n\n  wire                               sbiterr_fifo_out;\n  wire                               dbiterr_fifo_out;\n  wire                               inject_sbit_err;\n  wire                               inject_dbit_err;\n  wire                               sckt_wr_rst_i;\n  wire                               sckt_rd_rst_i;\n  reg                                sckt_wr_rst_i_q = 1'b0;\n \n  wire                               w_fab_read_data_valid_i;\n  wire                               w_read_data_valid_i;\n  wire                               w_ram_valid_i;\n  // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.\n  assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectsbiterr_delayed : 0;\n  assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectdbiterr_delayed : 0;\n                           \n  assign wr_rst_i_out = wr_rst_i;\n  assign rd_rst_i_out = rd_rst_i;\n  assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];\n  generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o\n    wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;\n    always @ (posedge clk_i)\n      sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; \n  end endgenerate \n// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL\n// parameter (1=Independent Clocks, 0=Common Clock)\n\n  localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;\ngenerate\ncase (C_VERILOG_IMPL)\n0 : begin : block1_ss\n  //Common Clock Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_ss\n  #(\n    .C_FAMILY                            (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                  (C_DATA_COUNT_WIDTH),            \n    .C_DIN_WIDTH                         (C_DIN_WIDTH),                   \n    .C_DOUT_RST_VAL                      (C_DOUT_RST_VAL),                \n    .C_DOUT_WIDTH                        (C_DOUT_WIDTH),                  \n    .C_FULL_FLAGS_RST_VAL                (FULL_FLAGS_RST_VAL),            \n    .C_HAS_ALMOST_EMPTY                  (C_HAS_ALMOST_EMPTY),            \n    .C_HAS_ALMOST_FULL                   ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),             \n    .C_HAS_DATA_COUNT                    (C_HAS_DATA_COUNT),              \n    .C_HAS_OVERFLOW                      (C_HAS_OVERFLOW),                \n    .C_HAS_RD_DATA_COUNT                 (C_HAS_RD_DATA_COUNT),           \n    .C_HAS_RST                           (C_EN_SAFETY_CKT?0:C_HAS_RST),                     \n    .C_HAS_SRST                          (C_EN_SAFETY_CKT?1:C_HAS_SRST),                    \n    .C_HAS_UNDERFLOW                     (C_HAS_UNDERFLOW),               \n    .C_HAS_VALID                         (C_HAS_VALID),                   \n    .C_HAS_WR_ACK                        (C_HAS_WR_ACK),                  \n    .C_HAS_WR_DATA_COUNT                 (C_HAS_WR_DATA_COUNT),           \n    .C_IMPLEMENTATION_TYPE               (C_IMPLEMENTATION_TYPE),         \n    .C_MEMORY_TYPE                       (C_MEMORY_TYPE),                 \n    .C_OVERFLOW_LOW                      (C_OVERFLOW_LOW),                \n    .C_PRELOAD_LATENCY                   (C_PRELOAD_LATENCY),             \n    .C_PRELOAD_REGS                      (C_PRELOAD_REGS),                \n    .C_PROG_EMPTY_THRESH_ASSERT_VAL      (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL      (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                   (C_PROG_EMPTY_TYPE),             \n    .C_PROG_FULL_THRESH_ASSERT_VAL       (C_PROG_FULL_THRESH_ASSERT_VAL), \n    .C_PROG_FULL_THRESH_NEGATE_VAL       (C_PROG_FULL_THRESH_NEGATE_VAL), \n    .C_PROG_FULL_TYPE                    (C_PROG_FULL_TYPE),              \n    .C_RD_DATA_COUNT_WIDTH               (C_RD_DATA_COUNT_WIDTH),         \n    .C_RD_DEPTH                          (C_RD_DEPTH),                    \n    .C_RD_PNTR_WIDTH                     (C_RD_PNTR_WIDTH),               \n    .C_UNDERFLOW_LOW                     (C_UNDERFLOW_LOW),               \n    .C_USE_DOUT_RST                      (C_USE_DOUT_RST),                \n    .C_USE_EMBEDDED_REG                  (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                     (C_EN_SAFETY_CKT),            \n    .C_USE_FWFT_DATA_COUNT               (C_USE_FWFT_DATA_COUNT),         \n    .C_VALID_LOW                         (C_VALID_LOW),                   \n    .C_WR_ACK_LOW                        (C_WR_ACK_LOW),                  \n    .C_WR_DATA_COUNT_WIDTH               (C_WR_DATA_COUNT_WIDTH),         \n    .C_WR_DEPTH                          (C_WR_DEPTH),                    \n    .C_WR_PNTR_WIDTH                     (C_WR_PNTR_WIDTH),               \n    .C_USE_ECC                           (C_USE_ECC),                     \n    .C_ENABLE_RST_SYNC                   (C_ENABLE_RST_SYNC),             \n    .C_ERROR_INJECTION_TYPE              (C_ERROR_INJECTION_TYPE),\n    .C_FIFO_TYPE                         (C_FIFO_TYPE)                     \n  )\n  gen_ss\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .CLK                      (CLK),\n    .RST                      (C_EN_SAFETY_CKT?1'b0:rst_i),\n    .SRST                     (C_EN_SAFETY_CKT?sckt_wr_rst_i:srst_delayed),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .USER_EMPTY_FB            (empty_fb),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .DATA_COUNT               (DATA_COUNT_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .WR_RST_BUSY              (wr_rst_busy),\n    .RD_RST_BUSY              (rd_rst_busy),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n1 : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT), \n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .fab_read_data_valid_i    (w_fab_read_data_valid_i),\n    .read_data_valid_i        (w_read_data_valid_i),\n    .ram_valid_i              (w_ram_valid_i),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\n2 : begin : ll_afifo_inst\n  fifo_generator_v13_2_5_beh_ver_ll_afifo\n  #(\n    .C_DIN_WIDTH                    (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                 (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                   (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_RD_DATA_COUNT            (C_HAS_RD_DATA_COUNT),\n    .C_HAS_WR_DATA_COUNT            (C_HAS_WR_DATA_COUNT),\n    .C_RD_DEPTH                     (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                (C_RD_PNTR_WIDTH),\n    .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n    .C_WR_DATA_COUNT_WIDTH          (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                     (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                (C_WR_PNTR_WIDTH),\n    .C_FIFO_TYPE                    (C_FIFO_TYPE)\n   )\n  gen_ll_afifo\n  (\n    .DIN                        (din_delayed),\n    .RD_CLK                     (RD_CLK),\n    .RD_EN                      (rd_en_delayed),\n    .WR_RST                     (wr_rst_i),\n    .RD_RST                     (rd_rst_i),\n    .WR_CLK                     (WR_CLK),\n    .WR_EN                      (wr_en_delayed),\n    .DOUT                       (DOUT),\n    .EMPTY                      (EMPTY),\n    .FULL                       (FULL)\n  );\nend\ndefault : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT),\n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\nendcase\nendgenerate\n\n\n   //**************************************************************************\n   // Connect Internal Signals\n   //   (Signals labeled internal_*)\n   //  In the normal case, these signals tie directly to the FIFO's inputs and\n   //    outputs.\n   //  In the case of Preload Latency 0 or 1, there are intermediate\n   //    signals between the internal FIFO and the preload logic.\n   //**************************************************************************\n   \n   \n   //***********************************************\n   // If First-Word Fall-Through, instantiate\n   // the preload0 (FWFT) module\n   //***********************************************\n   wire                        rd_en_to_fwft_fifo;\n   wire                        sbiterr_fwft;\n   wire                        dbiterr_fwft;\n   wire [C_DOUT_WIDTH-1:0]     dout_fwft;\n   wire                        empty_fwft;\n   wire                        rd_en_fifo_in;\n   wire                        stage2_reg_en_i;\n   wire [1:0]                  valid_stages_i;\n   wire                        rst_fwft;\n   //wire                        empty_p0_out;\n   reg  [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n   localparam IS_PKT_FIFO      = (C_FIFO_TYPE == 1) ? 1 : 0;\n   localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;\n   assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2_fwft\n\n\n         fifo_generator_v13_2_5_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_EMBEDDED_REG  (C_USE_EMBEDDED_REG),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (C_FIFO_TYPE)\n             )\n             fgpl0\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (RST_P0_IN),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (RD_EN_P0_IN),\n                .FIFOEMPTY        (EMPTY_P0_IN),\n                .FIFODATA         (DATA_P0_IN),\n                .FIFOSBITERR      (sbiterr_fifo_out),\n                .FIFODBITERR      (dbiterr_fifo_out),\n                // Output\n                .USERDATA         (dout_fwft),\n                .USERVALID        (VALID_P0_OUT),\n                .USEREMPTY        (empty_fwft),\n                .USERALMOSTEMPTY  (ALMOSTEMPTY_P0_OUT),\n                .USERUNDERFLOW    (UNDERFLOW_P0_OUT),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_fifo_in),\n                .USERSBITERR      (sbiterr_fwft),\n                .USERDBITERR      (dbiterr_fwft),\n                .STAGE2_REG_EN    (stage2_reg_en_i),\n                .fab_read_data_valid_i_o    (w_fab_read_data_valid_i),\n                .read_data_valid_i_o        (w_read_data_valid_i),\n                .ram_valid_i_o              (w_ram_valid_i),\n                .VALID_STAGES                (valid_stages_i)\n                );\n\n         \n         //***********************************************\n         // Connect inputs to preload (FWFT) module\n         //***********************************************\n         //Connect the RD_CLK of the Preload (FWFT) module to CLK if we \n         // have a common-clock FIFO, or RD_CLK if we have an \n         // independent clock FIFO\n         assign RD_CLK_P0_IN       = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);\n         assign RST_P0_IN          = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;\n         assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n         assign EMPTY_P0_IN        = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;\n         assign DATA_P0_IN         = DOUT_FIFO_OUT;\n         \n         //***********************************************\n         // Connect outputs from preload (FWFT) module\n         //***********************************************\n         assign VALID              = VALID_P0_OUT ;\n         assign ALMOST_EMPTY       = ALMOSTEMPTY_P0_OUT;\n         assign UNDERFLOW          = UNDERFLOW_P0_OUT ;\n         \n         assign RD_EN_FIFO_IN      = rd_en_fifo_in;\n         \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:\n           (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : \n           DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];  \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               EMPTY_P0_OUT_Q       <= 1;\n               ALMOSTEMPTY_P0_OUT_Q <= 1;\n            end else begin\n               EMPTY_P0_OUT_Q       <= #`TCQ empty_p0_out;\n//               EMPTY_P0_OUT_Q       <= #`TCQ EMPTY_FIFO_OUT;\n               ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;\n            end\n         end //always\n         \n         \n         //***********************************************\n         // logic for common-clock data count when FWFT is selected\n         //***********************************************\n         initial begin\n            SS_FWFT_RD = 1'b0;\n            DATA_COUNT_FWFT = 0 ;\n            SS_FWFT_WR   = 1'b0 ;\n         end //initial\n         \n         \n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter. SS_FWFT_WR and SS_FWFT_RD\n         // are the up/down enables for the counter.\n         //***********************************************\n         always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin\n            if (C_VALID_LOW == 1) begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;\n            end else begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;\n            end\n            SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT))  ;\n         end \n\n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter for FWFT. This always block \n         // calculates the counter.\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               DATA_COUNT_FWFT      <= 0;\n            end else begin\n               //if (srst_delayed && (C_HAS_SRST == 1) ) begin\n               if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin\n                  DATA_COUNT_FWFT      <= #`TCQ 0;\n               end else begin\n                  case ( {SS_FWFT_WR, SS_FWFT_RD})\n                    2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                    2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;\n                    2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;\n                    2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                  endcase  \n               end //if SRST\n            end //IF RST\n         end //always\n\n      end endgenerate // : block2\n\n    // AXI Streaming Packet FIFO\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_plus1 = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_reg   = 0;\n    reg                         partial_packet     = 0;\n    reg                         stage1_eop_d1      = 0;\n    reg                         rd_en_fifo_in_d1   = 0;\n    reg                         eop_at_stage2      = 0;\n    reg                         ram_pkt_empty      = 0;\n    reg                         ram_pkt_empty_d1   = 0;\n\n    wire [C_DOUT_WIDTH-1:0]     dout_p0_out;\n    wire                        packet_empty_wr;\n    wire                        wr_rst_fwft_pkt_fifo;\n    wire                        dummy_wr_eop;\n    wire                        ram_wr_en_pkt_fifo;\n    wire                        wr_eop;\n    wire                        ram_rd_en_compare;\n    wire                        stage1_eop;\n    wire                        pkt_ready_to_read;\n    wire                        rd_en_2_stage2;\n\n    // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)\n    // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP\n    // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of\n    // write packet count\n    generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop\n       always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n          if (wr_rst_fwft_pkt_fifo)\n             partial_packet   <= 1'b0;\n          else begin\n             if (srst_delayed | wr_rst_busy | rd_rst_busy)\n                partial_packet <= #`TCQ 1'b0;\n             else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))\n                partial_packet <= #`TCQ 1'b1;\n             else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)\n                partial_packet <= #`TCQ 1'b0;\n          end\n        end\n    end endgenerate // gdummy_wr_eop\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin : gpkt_fifo_fwft\n      assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;\n      assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);\n      assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];\n  \n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft) begin\n          stage1_eop_d1    <= 1'b0;\n          rd_en_fifo_in_d1 <= 1'b0;\n        end else begin\n          if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            stage1_eop_d1    <= #`TCQ 1'b0;\n            rd_en_fifo_in_d1 <= #`TCQ 1'b0;\n          end else begin\n            stage1_eop_d1    <= #`TCQ stage1_eop;\n            rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;\n          end\n        end\n      end\n      assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;\n      assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);\n      assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);\n      assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;\n\n\n         fifo_generator_v13_2_5_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (2) // Enable low latency fwft logic\n             )\n         pkt_fifo_fwft\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (rst_fwft),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (rd_en_delayed),\n                .FIFOEMPTY        (pkt_ready_to_read),\n                .FIFODATA         (dout_fwft),\n                .FIFOSBITERR      (sbiterr_fwft),\n                .FIFODBITERR      (dbiterr_fwft),\n                // Output\n                .USERDATA         (dout_p0_out),\n                .USERVALID        (),\n                .USEREMPTY        (empty_p0_out),\n                .USERALMOSTEMPTY  (),\n                .USERUNDERFLOW    (),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_2_stage2),\n                .USERSBITERR      (SBITERR),\n                .USERDBITERR      (DBITERR),\n                .STAGE2_REG_EN    (),\n                .VALID_STAGES     ()\n                );\n\n      assign pkt_ready_to_read  = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));\n      assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft)\n          eop_at_stage2 <= 1'b0;\n        else if (stage2_reg_en_i)\n          eop_at_stage2 <= #`TCQ stage1_eop;\n      end\n\n      //---------------------------------------------------------------------------\n      // Write and Read Packet Count\n      //---------------------------------------------------------------------------\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count  <= 0;\n         else if (srst_delayed  | wr_rst_busy | rd_rst_busy)\n            wr_pkt_count  <= #`TCQ 0;\n         else if (wr_eop)\n            wr_pkt_count  <= #`TCQ wr_pkt_count + 1;\n      end\n    \n    end endgenerate //: gpkt_fifo_fwft\n\n    assign DOUT               = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;\n    assign EMPTY              = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            rd_pkt_count       <= 0;\n            rd_pkt_count_plus1 <= 1;\n         end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            rd_pkt_count       <= #`TCQ 0;\n            rd_pkt_count_plus1 <= #`TCQ 1;\n         end else if (stage2_reg_en_i && stage1_eop) begin\n            rd_pkt_count       <= #`TCQ rd_pkt_count + 1;\n            rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;\n         end\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (SRST | wr_rst_busy | rd_rst_busy) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n    end endgenerate //grss_pkt_cnt\n    \n    localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;\n    reg  [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_b2g = 0;\n    wire [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_rd;\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt\n      // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count_b2g  <= 0;\n         else\n            wr_pkt_count_b2g  <= #`TCQ wr_pkt_count;\n      end\n\n      // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            wr_pkt_count_q       <= 0;\n         else\n            wr_pkt_count_q       <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};\n      end\n\n      always @* begin\n        if (stage1_eop)\n           rd_pkt_count    <= rd_pkt_count_reg + 1;\n        else\n           rd_pkt_count    <= rd_pkt_count_reg;\n      end\n\n      assign wr_pkt_count_rd    = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            rd_pkt_count_reg       <= 0;\n         else if (rd_en_fifo_in)\n            rd_pkt_count_reg       <= #`TCQ rd_pkt_count;\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (rd_pkt_count != wr_pkt_count_rd) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n\n      // Synchronize the empty in write domain\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            pkt_empty_sync  <= 'b1;\n         else\n            pkt_empty_sync  <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};\n      end\n\n    end endgenerate //gras_pkt_cnt\n\n   generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO\n\n     //***********************************************\n     // If NOT First-Word Fall-Through, wire the outputs\n     // of the internal _ss or _as FIFO directly to the\n     // output, and do not instantiate the preload0\n     // module.\n     //***********************************************\n\n     assign RD_CLK_P0_IN       = 0;\n     assign RST_P0_IN          = 0;\n     assign RD_EN_P0_IN        = 0;\n\n     assign RD_EN_FIFO_IN      = rd_en_delayed;\n\n     assign DOUT               = DOUT_FIFO_OUT;\n     assign DATA_P0_IN         = 0;\n     assign VALID              = VALID_FIFO_OUT;\n     assign EMPTY              = EMPTY_FIFO_OUT;\n     assign ALMOST_EMPTY       = ALMOST_EMPTY_FIFO_OUT;\n     assign EMPTY_P0_IN        = 0;\n     assign UNDERFLOW          = UNDERFLOW_FIFO_OUT;\n     assign DATA_COUNT         = DATA_COUNT_FIFO_OUT;\n     assign SBITERR            = sbiterr_fifo_out;\n     assign DBITERR            = dbiterr_fifo_out;\n\n   end endgenerate // STD_FIFO\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO\n     assign empty_p0_out       = empty_fwft;\n     assign SBITERR            = sbiterr_fwft;\n     assign DBITERR            = dbiterr_fwft;\n     assign DOUT               = dout_fwft;\n     assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n\n   end endgenerate // NO_PKT_FIFO\n\n   //***********************************************\n   // Connect user flags to internal signals\n   //***********************************************\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3\n      if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);\n      end //block_ic\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3\n   endgenerate\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30\n       if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30\n   endgenerate\n\n\n    \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both\n       if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30_both\n   endgenerate\n\n generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both\n      if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));\n      end //block_ic_both\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3_both\n   endgenerate\n\n\n   //If we are not using extra logic for the FWFT data count,\n   //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the\n   //internal FIFO instance  \n   generate\n      if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n   //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal\n   //FIFO instance\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1) begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n      else begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n\n   //Connect other flags to the internal FIFO instance\n   assign       FULL        = FULL_FIFO_OUT;\n   assign       ALMOST_FULL = ALMOST_FULL_FIFO_OUT;\n   assign       WR_ACK      = WR_ACK_FIFO_OUT;\n   assign       OVERFLOW    = OVERFLOW_FIFO_OUT;\n   assign       PROG_FULL   = PROG_FULL_FIFO_OUT;\n   assign       PROG_EMPTY  = PROG_EMPTY_FIFO_OUT;\n\n\n  /**************************************************************************\n  * find_log2\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n   // if an asynchronous FIFO has been selected, display a message that the FIFO\n   //   will not be cycle-accurate in simulation\n   initial begin\n      if (C_IMPLEMENTATION_TYPE == 2) begin\n         $display(\"WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.\");\n      end else if (C_MEMORY_TYPE == 4) begin\n         $display(\"FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.\");\n         $finish;\n      end\n\n      if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin\n         $display(\"FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.\");\n         $finish;\n      end\n\n      if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin\n         $display(\"FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.\");\n         $finish;\n      end\n\n      if (C_USE_ECC == 1) begin\n         if (C_DIN_WIDTH != C_DOUT_WIDTH) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.\");\n            $finish;\n         end\n         if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.\");\n            $finish;\n         end\n      end\n\n   end //initial\n\n  /**************************************************************************\n  * Internal reset logic\n  **************************************************************************/\n  assign wr_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg|sckt_wr_rst_i : 0;\n  assign rd_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg|sckt_rd_rst_i : 0;\n  assign rst_i            = C_HAS_RST ? rst_reg|sckt_wr_rst_i : 0;\n\n  wire rst_2_sync;\n  wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;\n\n  localparam RST_SYNC_STAGES = C_EN_SAFETY_CKT == 0 ? C_COMMON_CLOCK ? C_SYNCHRONIZER_STAGE : C_SYNCHRONIZER_STAGE+2 : 5;\n  localparam RST_BUSY_LEN    = 4;\n  reg  wr_rst_busy_i = 0;\n  reg  rd_rst_busy_i = 0;\n  generate\n      if (C_ENABLE_RST_SYNC == 0 || (C_HAS_RST == 0 && C_HAS_SRST == 0)) begin : gnrst_sync\n        always @* begin\n          wr_rst_reg <= wr_rst_delayed;\n          rd_rst_reg <= rd_rst_delayed;\n          rst_reg    <= 1'b0;\n          srst_reg    <= 1'b0;\n        end\n        assign rst_2_sync = wr_rst_delayed;\n        assign wr_rst_busy = 1'b0;\n        assign wr_rst_busy_o = 1'b0;\n        assign rd_rst_busy = 1'b0;\n        assign sckt_wr_rst_i = 1'b0;\n        assign sckt_rd_rst_i = 1'b0;\n      end // gnrst_sync\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 0) begin : g7s_ic_rst_nsckt\n        reg [1:0]                 arst_sync_wr  = 2'b11;\n        reg [1:0]                 arst_sync_rd  = 2'b11;\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge WR_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge RD_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_rd    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_rd    <= #`TCQ {arst_sync_rd[0], rst_delayed};\n        end\n        always @(posedge WR_CLK) begin\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n\tend\n        always @(posedge WR_CLK or posedge arst_sync_wr[1]) begin\n\t  if (arst_sync_wr[1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n            rd_rst_wr_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            rd_rst_wr_ext  <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t    if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t      sckt_wr_rst_ic <= #`TCQ 1'b0;\n            else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t      wr_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n        always @(posedge RD_CLK) begin\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], sckt_wr_rst_ic};\n\tend\n        always @(posedge RD_CLK or posedge arst_sync_rd[1]) begin\n\t  if (arst_sync_rd[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n            wr_rst_rd_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            wr_rst_rd_ext  <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t    if (wr_rst_rd_ext[1]) begin\n\t      sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t      rd_rst_busy_i  <= #`TCQ 1'b0;\n\t    end\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic|arst_sync_wr[1];\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic|arst_sync_rd[1];\n      end // g7s_ic_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 1) begin : g7s_ic_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] arst_sync_rd  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        always @(posedge WR_CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n          rd_rst_wr_ext    <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_wr[RST_SYNC_STAGES-1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n          end else if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t    sckt_wr_rst_ic <= #`TCQ 1'b0;\n          else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t    wr_rst_busy_i  <= #`TCQ 1'b0;\n\tend\n        always @(posedge RD_CLK) begin\n\t  arst_sync_rd     <= #`TCQ {arst_sync_rd[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n          wr_rst_rd_ext    <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_rd[RST_SYNC_STAGES-1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n\t  end else if (wr_rst_rd_ext[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t    rd_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic;\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic;\n      end // g7s_ic_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 0) begin : g7s_cc_rst_nsckt\n        reg [1:0]              arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge CLK) begin\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0] | arst_sync_wr[1]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc | arst_sync_wr[1];\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 1) begin : g7s_cc_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n\n        always @(posedge CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc;\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst\n        assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;\n        assign rd_rst_busy = rst_reg;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = rst_reg;\n        always @* rst_full_ff_i  <= 1'b0;\n        always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;\n\n        always @(posedge CLK) begin\n          rst_delayed_d1 <= #`TCQ srst_delayed;\n          rst_delayed_d2 <= #`TCQ rst_delayed_d1;\n          if (rst_reg || rst_delayed_d2) begin\n            rst_active_i <= #`TCQ 1'b1;\n          end else begin\n            rst_active_i <= #`TCQ rst_reg;\n          end    \n        end   \n        always @(posedge CLK) begin\n          if (~rst_reg && srst_delayed) begin\n             rst_reg <= #`TCQ 1'b1;\n           end else if (rst_reg) begin\n             rst_reg <= #`TCQ 1'b0;\n           end else begin\n             rst_reg <= #`TCQ rst_reg;\n           end    \n        end   \n      end // g8s_cc_rst\n      else if (IS_8SERIES != 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_srst\n        assign wr_rst_busy = srst_delayed;\n        assign rd_rst_busy = srst_delayed;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = srst_delayed;\n        always @* rst_full_ff_i  <= 1'b0;\n      end // g7s_cc_srst\n  endgenerate \n\n  reg rst_d1 = 1'b0;\n  reg rst_d2 = 1'b0;\n  reg rst_d3 = 1'b0;\n  reg rst_d4 = 1'b0;\n  generate\n    if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1\n    // RST_FULL_GEN replaces the reset falling edge detection used to de-assert\n    // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.\n\n    // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &\n    // PROG_FULL\n\n      always @ (posedge rst_2_sync or posedge clk_2_sync) begin\n        if (rst_2_sync && C_EN_SAFETY_CKT == 0) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          rst_d3         <= 1'b1;\n          rst_d4         <= 1'b0;\n        end else begin\n          if (srst_delayed) begin\n            rst_d1         <= #`TCQ 1'b1;\n            rst_d2         <= #`TCQ 1'b1;\n            rst_d3         <= #`TCQ 1'b1;\n            rst_d4         <= #`TCQ 1'b0;\n          end else begin\n            rst_d1         <= #`TCQ wr_rst_busy;//1'b0;\n            rst_d2         <= #`TCQ rst_d1;\n            rst_d3         <= #`TCQ rst_d2 | sckt_wr_rst_i;\n            rst_d4         <= #`TCQ rst_d3;\n          end\n        end\n      end\n\n      always @* rst_full_ff_i  <= C_HAS_SRST ? 1'b0 : rst_d2 | sckt_wr_rst_i;\n      always @* rst_full_gen_i <= C_HAS_SRST ? rst_d4 : rst_d3;\n\n    end else if (C_EN_SAFETY_CKT == 1 && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full_sckt\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end\n  endgenerate // grstd1\n\nendmodule //fifo_generator_v13_2_5_CONV_VER\n\n\nmodule fifo_generator_v13_2_5_sync_stage\n  #(\n    parameter  C_WIDTH          = 10\n   )\n   (\n    input                     RST,\n    input                     CLK,\n    input       [C_WIDTH-1:0] DIN,\n    output reg  [C_WIDTH-1:0] DOUT = 0\n   );\n   always @ (posedge RST or posedge CLK) begin\n     if (RST)\n       DOUT <= 0;\n     else\n       DOUT <= #`TCQ DIN;\n   end\nendmodule // fifo_generator_v13_2_5_sync_stage\n\n/*******************************************************************************\n * Declaration of Independent-Clocks FIFO Module\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_as\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2 \n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input                                         SAFETY_CKT_WR_RST,\n   input                                         SAFETY_CKT_RD_RST,\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_ASSERT,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_NEGATE,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_ASSERT,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_NEGATE,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         RD_EN_USER,\n   input                                         RST,\n   input                                         RST_FULL_GEN,\n   input                                         RST_FULL_FF,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   input                                         INJECTDBITERR,\n   input                                         INJECTSBITERR,\n   input                                         USER_EMPTY_FB,\n   input                                         fab_read_data_valid_i,\n   input                                         read_data_valid_i,\n   input                                         ram_valid_i,\n   output reg                                    ALMOST_EMPTY = 1'b1,\n   output reg                                    ALMOST_FULL = C_FULL_FLAGS_RST_VAL,\n   output      [C_DOUT_WIDTH-1:0]                DOUT,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    EMPTY_FB = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL,\n   output                                        OVERFLOW,\n   output                                        PROG_EMPTY,\n   output                                        PROG_FULL,\n   output                                        VALID,\n   output      [C_RD_DATA_COUNT_WIDTH-1:0]       RD_DATA_COUNT,\n   output                                        UNDERFLOW,\n   output                                        WR_ACK,\n   output      [C_WR_DATA_COUNT_WIDTH-1:0]       WR_DATA_COUNT,\n   output                                        SBITERR,\n   output                                        DBITERR\n  );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   \n  \n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   \n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;\n   // Array that holds the error injection type (single/double bit error) on \n   // a specific write operation, which is returned on read to corrupt the\n   // output data.\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   //The amount of data stored in the FIFO at any time is given\n   // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK\n   // domain.\n   //num_wr_bits is calculated by considering the total words in the FIFO,\n   // and the state of the read pointer (which may not have yet crossed clock\n   // domains.)\n   //num_rd_bits is calculated by considering the total words in the FIFO,\n   // and the state of the write pointer (which may not have yet crossed clock\n   // domains.)\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   wire                        wr_rst_i = WR_RST;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n   wire                        rd_rst_i = RD_RST;\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n\n\n\n   // Delayed ram_rd_en is needed only for STD Embedded register option\n   generate\n     if (C_PRELOAD_LATENCY == 2) begin : grd_d\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n       end\n     end\n   endgenerate\n   \n    generate\n     if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n           fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n       end\n     end\n   endgenerate\n\n  \n\n   // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;\n     end else begin : rdl // Read depth lesser than or equal to write depth\n       assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n     end\n   endgenerate\n\n   // Generate Empty and Almost Empty\n  // ram_rd_en used to determine EMPTY should depend on the EMPTY.\n   assign ram_rd_en        = RD_EN & !EMPTY;\n   assign empty_int        = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));\n   assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));\n\n   // Register Empty and Almost Empty\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else begin\n         rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};\n\n         if (empty_int)\n           EMPTY           <= #`TCQ 1'b1;\n         else\n           EMPTY           <= #`TCQ 1'b0;\n\n         if (!EMPTY) begin\n           if (almost_empty_int)\n             ALMOST_EMPTY  <= #`TCQ 1'b1;\n           else\n             ALMOST_EMPTY  <= #`TCQ 1'b0;\n         end\n       end // rd_rst_i\n     end // always\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY_FB     <= 1'b1;\n       end else begin\n         if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else if (empty_int)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else\n           EMPTY_FB   <= #`TCQ 1'b0;\n       end // rd_rst_i\n     end // always\n\n   // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;\n     end else begin : wdl // Write depth lesser than or equal to read depth\n       assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n     end\n   endgenerate\n\n  // Generate FULL and ALMOST_FULL\n  // ram_wr_en used to determine FULL should depend on the FULL.\n  assign ram_wr_en       = WR_EN & !FULL;\n  assign full_int        = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));\n  assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));\n\n   // Register FULL and ALMOST_FULL Empty\n   always @ (posedge WR_CLK or posedge RST_FULL_FF)\n     begin\n       if (RST_FULL_FF & C_HAS_RST) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else begin\n         if (full_int) begin\n           FULL           <= #`TCQ 1'b1;\n         end else begin\n           FULL           <= #`TCQ 1'b0;\n         end\n\n         if (RST_FULL_GEN) begin\n           ALMOST_FULL    <= #`TCQ 1'b0;\n         end else if (!FULL) begin\n           if (almost_full_int)\n             ALMOST_FULL  <= #`TCQ 1'b1;\n           else\n             ALMOST_FULL  <= #`TCQ 1'b0;\n         end\n       end // wr_rst_i\n     end // always\n   always @ (posedge WR_CLK or posedge wr_rst_i)\n     begin\n       if (wr_rst_i) begin\n         wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};\n       end else begin\n         wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};\n       end // wr_rst_i\n     end // always\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i) begin\n           stage1_valid     <= 0;\n           stage2_valid     <= 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n   //Pointers passed into opposite clock domain\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_EMPTY.\n   wire [31:0] num_read_words_pe = \n     num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_FULL.\n   wire [31:0] num_write_words_pf =\n     num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n    \n    \n   /***************************************************************************\n    * Internal registers and wires\n    **************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire [C_DOUT_WIDTH-1:0] ideal_dout_out;      \n   wire valid_i;\n   wire valid_out1;\n   wire valid_out2;\n   wire valid_out;  \n   wire underflow_i;\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]               err_type                 = 0;\n   reg [1:0]               err_type_d1              = 0;\n   reg [1:0]               err_type_both              = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout               = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_d1            = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_both            = 0;\n   reg                     ideal_wr_ack             = 0;\n   reg                     ideal_valid              = 0;\n   reg                     ideal_overflow           = C_OVERFLOW_LOW;\n   reg                     ideal_underflow          = C_UNDERFLOW_LOW;\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   reg         valid_d1     = 0;\n   reg         valid_d2     = 0; \n   \n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n   \n\n  /****************************************************************************\n   * Function Declarations\n   ***************************************************************************/\n\n  /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n      if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n    end\n  endtask\n\n  /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n  /***********************************************************************\n  * hexstr_conv\n  *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n  ***********************************************************************/\n  function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_d2           = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n    end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the \n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n    wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;   \n   wire RD_CLK;\n   wire RD_EN;\n   wire RST;\n   wire WR_CLK;\n   wire WR_EN;\n    */\n\n   //***************************************************************************\n   // Dout may change behavior based on latency\n   //***************************************************************************\n   assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?\n                         ideal_dout_d1: ideal_dout;   \n   assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; \n\n   //***************************************************************************\n   // Assign SBITERR and DBITERR based on latency \n   //***************************************************************************\n   assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                    (C_PRELOAD_LATENCY == 2 &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?\n                    err_type_d1[0]: err_type[0]; \n   assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                    (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                    err_type_d1[1]: err_type[1]; \n  \n   //***************************************************************************\n   // Safety-ckt logic with embedded reg/fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n       //  if (C_HAS_VALID == 1) begin\n       //       assign valid_out = valid_d1;\n       //  end\n             \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)\n          begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else \n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n          end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                  @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n           end\n           else begin\n                   if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                   end\n             end \n           end  \n      end \n      endgenerate   \n\n//***************************************************************************\n   // Safety-ckt logic with embedded reg + fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else begin\n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n               fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n          end\n        end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   ideal_dout_both <= #`TCQ dout_reset_val;\n              end\n           end else begin\n             if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n              \n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n             end\n           end \n         end      \n      end \n      endgenerate    \n \n   //***************************************************************************\n   // Overflow may be active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_OVERFLOW==1) begin : blockOF1\n   assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n      end\n   endgenerate\n\n   assign PROG_EMPTY = ideal_prog_empty;\n   assign PROG_FULL  = ideal_prog_full;\n\n   //***************************************************************************\n   // Valid may change behavior based on latency or active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_VALID==1) begin : blockVL1\n   assign valid_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;\n   assign valid_out1 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?\n                       valid_d1: valid_i;  \n   assign valid_out2 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?\n                       valid_d2: valid_i; \n   assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;\n   assign VALID     = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Underflow may change behavior based on latency or active-low   \n   //***************************************************************************\n   generate\n      if (C_HAS_UNDERFLOW==1) begin : blockUF1\n   assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;\n   assign UNDERFLOW   = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n    end\n   endgenerate\n\n   //***************************************************************************\n   // Write acknowledge may be active low\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_ACK==1) begin : blockWK1\n   assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext\n\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_wr_pntr = 0;\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_rd_pntr = 0;\n      wire [C_PNTR_WIDTH-1:0]  diff_wr_rd_tmp;\n      wire [C_PNTR_WIDTH:0]    diff_wr_rd;\n      reg  [C_PNTR_WIDTH:0]    wr_data_count_i  = 0;\n        always @* begin\n          if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = 0;\n            adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n          end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin\n            adjusted_rd_pntr = rd_pntr_wr;\n            adjusted_wr_pntr = 0;\n            adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n          end else begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = rd_pntr_wr;\n          end\n        end // always @*\n\n        assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;\n        assign diff_wr_rd     = {1'b0,diff_wr_rd_tmp};\n\n        always @ (posedge wr_rst_i or posedge WR_CLK)\n        begin\n            if (wr_rst_i)\n              wr_data_count_i <= 0;\n            else\n              wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;\n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n\n        always @* begin\n          if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];\n          else\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n        end // always @*\n      end // wdc_fwft_ext\n   endgenerate\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   reg  [C_RD_PNTR_WIDTH:0]    rdc_fwft_ext_as  = 0;\n\n   generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n\n\n   always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= 0;\n            end else begin\n              if (!stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 0;\n              else if (!stage1_valid && stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 1;\n              else\n                rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;\n            end \n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n      end // rdc_fwft_ext\n end\n   endgenerate\n\n\n  generate if (C_USE_EMBEDDED_REG == 3) begin\n     if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n        wire [C_RD_PNTR_WIDTH:0]  diff_rd_wr_1;\n   //     assign diff_rd_wr_1 = diff_rd_wr +2'h2;\n\n       always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= #`TCQ 0;\n            end else begin\n          //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))\n          //    rdc_fwft_ext_as <= 1'b0;\n          //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) \n          //    rdc_fwft_ext_as <= 1'b1;\n          //else\n            rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;\n        end\n\n\n\nend\nend\nend\nendgenerate\n          \n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1) begin : grdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?\n          rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :\n          rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?\n          wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :\n          wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n\n  /**************************************************************************\n  * Assorted registers for delayed versions of signals\n  **************************************************************************/\n  //Capture delayed version of valid\n  generate\n      if (C_HAS_VALID==1) begin : blockVL2\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n      valid_d1 <= 1'b0;\n      valid_d2 <= 1'b0;\n    end else begin\n      valid_d1 <= #`TCQ valid_i;\n      valid_d2 <= #`TCQ valid_d1;\n    end \n//    if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin\n  //      valid_d2 <= #`TCQ valid_d1;\n      //  end \n  end \n      end\n endgenerate  \n   \n  //Capture delayed version of dout\n  /**************************************************************************\n    *embedded/fabric reg with no safety ckt\n    **************************************************************************/\n  generate \n       if (C_USE_EMBEDDED_REG < 3) begin\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n       if (C_USE_DOUT_RST == 1'b1) begin\n         @(posedge RD_CLK)\n           ideal_dout_d1   <= #`TCQ dout_reset_val;\n           ideal_dout   <= #`TCQ dout_reset_val;\n       end\n      // Reset err_type only if ECC is not selected\n      if (C_USE_ECC == 0)\n        err_type_d1     <= #`TCQ 0;\n     end else if (ram_rd_en_d1) begin\n      ideal_dout_d1   <= #`TCQ ideal_dout;\n      err_type_d1     <= #`TCQ err_type;\n           end    \n  end  \n   \nend  \nendgenerate \n/**************************************************************************\n    *embedded + fabric reg with no safety ckt\n    **************************************************************************/\n\ngenerate \n  if (C_USE_EMBEDDED_REG == 3) begin\n    always @(posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i == 1'b1) begin\n        if (C_USE_DOUT_RST == 1'b1) begin\n           @(posedge RD_CLK)\n             ideal_dout    <= #`TCQ dout_reset_val;\n             ideal_dout_d1   <= #`TCQ dout_reset_val;\n             ideal_dout_both   <= #`TCQ dout_reset_val;\n        end\n        // Reset err_type only if ECC is not selected\n        if (C_USE_ECC == 0) begin\n          err_type_d1     <= #`TCQ 0;\n          err_type_both   <= #`TCQ 0;\n        end\n      end else begin\n         if (ram_rd_en_d1) begin\n           ideal_dout_both   <= #`TCQ ideal_dout;\n           err_type_both     <= #`TCQ err_type;\n         end    \n         if (fab_rd_en_d1) begin\n           ideal_dout_d1   <= #`TCQ ideal_dout_both;\n           err_type_d1     <= #`TCQ err_type_both;\n         end\n      end\n    end  \n  end  \nendgenerate \n\n  \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate\n     if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n       always @(posedge WR_CLK) begin\n         ideal_overflow    <= #`TCQ WR_EN & FULL;\n       end\n     end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n       always @(posedge WR_CLK) begin\n         //ideal_overflow    <= #`TCQ WR_EN & (FULL | wr_rst_i);\n         ideal_overflow    <= #`TCQ WR_EN & (FULL );\n       end\n     end\n   endgenerate\n\n   generate\n     if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ EMPTY & RD_EN;\n       end\n     end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ (EMPTY) & RD_EN;\n         //ideal_underflow    <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;\n       end\n     end\n   endgenerate\n\n   /**************************************************************************\n   * Write/Read Pointer Synchronization\n   **************************************************************************/\n   localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;\n   wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   genvar gss;\n\n   generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (C_WR_PNTR_WIDTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_i), \n         .CLK      (RD_CLK), \n         .DIN      (wr_pntr_sync_stgs[gss-1]), \n         .DOUT     (wr_pntr_sync_stgs[gss])\n        );\n \n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (C_RD_PNTR_WIDTH)\n        )\n     wr_stg_inst\n        (\n         .RST      (wr_rst_i), \n         .CLK      (WR_CLK), \n         .DIN      (rd_pntr_sync_stgs[gss-1]), \n         .DOUT     (rd_pntr_sync_stgs[gss])\n        );\n   end endgenerate // Sync_stage_inst\n\n   assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;\n   assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;\n   always@* begin\n     wr_pntr_rd           <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n     rd_pntr_wr           <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n   end\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp\n     if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)\n       wr_pntr           <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)\n       wr_pntr           <= #`TCQ 0;\n   end\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (wr_rst_i == 1'b1) begin\n       num_wr_bits       <= 0;\n       next_num_wr_bits   = 0;\n       wr_ptr            <= C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= C_RD_DEPTH - 1;\n       ideal_wr_ack      <= 0;\n       ideal_wr_count    <= 0;\n       tmp_wr_listsize    = 0;\n       rd_ptr_wrclk_next <= 0;\n       wr_pntr_rd1       <= 0;\n\n     end else begin //wr_rst_i==0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       //If this is a write, handle the write by adding the value\n       // to the linked list, and updating all outputs appropriately\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD \n             >= C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full, but reporting full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //With DEPTH-1 words in the FIFO, it is almost_full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n\n           //If the FIFO is completely empty, but it is\n           // reporting FULL for some reason (like reset)\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=\n                C_FIFO_WR_DEPTH-2) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //FIFO is really not close to full, so change flag status.\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n           end //(tmp_wr_listsize == 0)\n\n         end else begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=\n              C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack       <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count     <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;\n\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //This write is CAUSING the FIFO to go full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is 2 from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == \n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits =  next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Still 2 from full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is not close to being full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <\n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //wr_rst_i==0\n   end // gen_fifo_w\n\n\n  /***************************************************************************\n   * Programmable FULL flags\n   ***************************************************************************/\n\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;\n\n   generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;\n   end else begin // STD\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;\n   end endgenerate\n\n   always @(posedge WR_CLK or posedge wr_rst_i) begin\n\n     if (wr_rst_i == 1'b1) begin\n       diff_pntr         <= 0;\n     end else begin\n       if (ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);\n       else if (!ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);\n    end\n  end\n\n\n   always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf\n\n     if (RST_FULL_FF & C_HAS_RST) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else begin\n\n       if (RST_FULL_GEN)\n         ideal_prog_full   <= #`TCQ 0;\n       //Single Programmable Full Constant Threshold\n       else if (C_PROG_FULL_TYPE == 1) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else\n             ideal_prog_full <= #`TCQ 0;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Constant Thresholds\n       end else if (C_PROG_FULL_TYPE == 2) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else if (diff_pntr < pf_thr_negate_val)\n             ideal_prog_full <= #`TCQ 0;\n           else\n             ideal_prog_full <= #`TCQ ideal_prog_full;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Single Programmable Full Threshold Input\n       end else if (C_PROG_FULL_TYPE == 3) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH)\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Threshold Inputs\n       end else if (C_PROG_FULL_TYPE == 4) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH_ASSERT)\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < PROG_FULL_THRESH_NEGATE)\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       end // C_PROG_FULL_TYPE\n\n     end //wr_rst_i==0\n   end //\n\n   \n   /**************************************************************************\n   * Read Domain Logic\n   **************************************************************************/\n\n\n   /*********************************************************\n    * Programmable EMPTY flags\n    *********************************************************/\n   //Determine the Assert and Negate thresholds for Programmable Empty\n\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd      = 0;\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe\n\n     if (rd_rst_i & C_HAS_RST) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else begin\n       if (ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;\n       else if (!ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr);\n       else\n         diff_pntr_rd       <=  #`TCQ diff_pntr_rd;\n  \n       if (C_PROG_EMPTY_TYPE == 1) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 2) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 3) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 4) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end  //C_PROG_EMPTY_TYPE\n     end\n   end // gen_pe\n\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;\n   end endgenerate // single_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;\n   end endgenerate // multiple_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;\n   end endgenerate // single_multiple_pe_thr_const\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp\n     if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n       rd_pntr            <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)\n       rd_pntr            <= #`TCQ 0;\n   end\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rd_rst_i & C_HAS_RST) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n     end else begin //rd_rst_i==0\n\n       rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 1\n       /*****************************************************************/\n       if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Reminder that FIFO is still empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end // if (tmp_rd_listsize <= 0)\n\n             //If the FIFO is one from empty, but it is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 1)\n\n             //If the FIFO is two from empty, and is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Fifo has two words, so is neither empty or almost empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 2)\n\n             //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid <= #`TCQ 1'b0;\n                 //Note that the FIFO is No Longer Empty or Almost Empty\n\n                 ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n               end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n             end // else: if(ideal_empty == 1'b1)\n\n           else //if (ideal_empty == 1'b0)\n             begin\n\n               //If the FIFO is completely full, and we are successfully reading from it\n               if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)\n\n               //If the FIFO is not close to being empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n               //If the FIFO is two from empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Fifo is not yet empty. It is going almost_empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n\n               //If the FIFO is one from empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Note that FIFO is GOING empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 1)\n\n\n               //If the FIFO is completely empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n                 begin\n                   //Do not change the contents of the FIFO\n\n                   //Do not acknowledge the read from empty FIFO\n                   ideal_valid        <= #`TCQ 1'b0;\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize <= 0)\n\n             end // if (ideal_empty == 1'b0)\n\n           end //(RD_EN == 1'b1)\n\n         else //if (RD_EN == 1'b0)\n           begin\n             //If user did not attempt a read, do not give an ack or err\n             ideal_valid          <= #`TCQ 1'b0;\n\n             ideal_rd_count       <= #`TCQ num_read_words_sized_i;\n\n           end // else: !if(RD_EN == 1'b1)\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 0\n       /*****************************************************************/\n       end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty, but it is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty, and is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Fifo has two words, so is neither empty or almost empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                         (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that the FIFO is No Longer Empty or Almost Empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n           end else begin\n\n             //If the FIFO is completely full, and we are successfully reading from it\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is not close to being empty\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                          (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Fifo is not yet empty. It is going almost_empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Note that FIFO is GOING empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is completely empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if (tmp_rd_listsize <= 0)\n\n           end // if (ideal_empty == 1'b0)\n\n         end else begin//(RD_EN == 1'b0)\n\n         \n           //If user did not attempt a read, do not give an ack or err\n           ideal_valid           <= #`TCQ 1'b0;\n           ideal_rd_count        <= #`TCQ num_read_words_sized_i;\n\n         end // else: !if(RD_EN == 1'b1)\n       end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //rd_rst_i==0\n   end //always gen_fifo_r_as\n\nendmodule // fifo_generator_v13_2_5_bhv_ver_as\n\n\n/*******************************************************************************\n * Declaration of Low Latency Asynchronous FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_beh_ver_ll_afifo\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_FIFO_TYPE                    = 0\n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   output reg  [C_DOUT_WIDTH-1:0]                DOUT = 0,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL\n  );\n\n  //-----------------------------------------------------------------------------\n  // Low Latency Asynchronous FIFO\n  //-----------------------------------------------------------------------------\n\n  // Memory which will be used to simulate a FIFO\n  reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n  integer i;\n  initial begin\n    for (i = 0; i < C_WR_DEPTH; i = i + 1)\n      memory[i] = 0;\n  end\n\n  reg  [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;\n  wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;\n  reg  [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;\n  reg                        ll_afifo_full    = 1'b0;\n  reg                        ll_afifo_empty   = 1'b1;\n  wire                       write_allow;\n  wire                       read_allow;\n\n  assign write_allow = WR_EN & ~ll_afifo_full;\n  assign read_allow  = RD_EN & ~ll_afifo_empty;\n\n  //-----------------------------------------------------------------------------\n  // Write Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      wr_pntr_ll_afifo   <= 0;\n    else if (write_allow)\n      wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Read Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      rd_pntr_ll_afifo_q   <= 0;\n    else\n      rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;\n  end\n  assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;\n  \n  //-----------------------------------------------------------------------------\n  // Fill the Memory\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK) begin\n    if (write_allow)\n      memory[wr_pntr_ll_afifo] <= #`TCQ DIN;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate DOUT\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK) begin\n      DOUT <= #`TCQ memory[rd_pntr_ll_afifo];\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate EMPTY\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      ll_afifo_empty   <= 1'b1;\n    else\n      ll_afifo_empty   <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | \n                           (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate FULL\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      ll_afifo_full   <= 1'b1;\n    else\n      ll_afifo_full   <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | \n                           (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));\n  end\n\n  always @* begin\n    FULL  <= ll_afifo_full;\n    EMPTY <= ll_afifo_empty;\n  end\n\nendmodule // fifo_generator_v13_2_5_beh_ver_ll_afifo\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_ss\n   \n  /**************************************************************************\n   * Declare user parameters and their defaults\n   *************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0 \n   )\n   \n  /**************************************************************************\n   * Declare Input and Output Ports\n   *************************************************************************/\n   (\n    //Inputs\n    input                                 SAFETY_CKT_WR_RST,\n    input                                 CLK,\n    input       [C_DIN_WIDTH-1:0]         DIN,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_ASSERT,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_NEGATE,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_ASSERT,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_NEGATE,\n    input                                 RD_EN,\n    input                                 RD_EN_USER,\n    input                                 USER_EMPTY_FB,\n    input                                 RST,\n    input                                 RST_FULL_GEN,\n    input                                 RST_FULL_FF,\n    input                                 SRST,\n    input                                 WR_EN,\n    input                                 INJECTDBITERR,\n    input                                 INJECTSBITERR,\n    input                                 WR_RST_BUSY,\n    input                                 RD_RST_BUSY,\n                                    \n    //Outputs                       \n    output                                ALMOST_EMPTY,\n    output                                ALMOST_FULL,\n    output reg   [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,\n    output       [C_DOUT_WIDTH-1:0]       DOUT,\n    output                                EMPTY,\n    output reg                            EMPTY_FB = 1'b1,\n    output                                FULL,\n    output                                OVERFLOW,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]    RD_DATA_COUNT,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]    WR_DATA_COUNT,\n    output                                PROG_EMPTY,\n    output                                PROG_FULL,\n    output                                VALID,\n    output                                UNDERFLOW,\n    output                                WR_ACK,\n    output                                SBITERR,\n    output                                DBITERR\n   );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;\n   wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n   localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; \n\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n   localparam  EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //localparam  EXTRA_WORDS_PE_PARAM  = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not \n   //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.\n   // Therefore, during SRST, all the FULL flags reset to 0.\n   localparam                      C_HAS_FAST_FIFO = 0;\n   localparam                      C_FIFO_WR_DEPTH = C_WR_DEPTH;\n   localparam                      C_FIFO_RD_DEPTH = C_RD_DEPTH;\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;\n   localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;\n   localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;\n   localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n  localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; \n  localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; \n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   \n   /**************************************************************************\n    * Internal Registers and wires\n    *************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire                           underflow_i;\n   wire                           valid_i;\n   wire                           valid_out;\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_reg = 1'b0;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n   wire                         srst_rrst_busy;\n\n\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]                      err_type           = 0;\n   reg [1:0]                      err_type_d1        = 0;\n   reg [1:0]                      err_type_both      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout         = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_d1      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_both      = 0;\n   wire [C_DOUT_WIDTH-1:0]        ideal_dout_out;\n   wire                           fwft_enabled;\n   reg                            ideal_wr_ack       = 0;\n   reg                            ideal_valid        = 0;\n   reg                            ideal_overflow     = C_OVERFLOW_LOW;\n   reg                            ideal_underflow    = C_UNDERFLOW_LOW;\n\n   reg                            full_i             = C_FULL_FLAGS_RST_VAL;\n   reg                            full_i_temp        = 0;\n   reg                            empty_i            = 1;\n   reg                            almost_full_i      = 0;\n   reg                            almost_empty_i     = 1;\n   reg                            prog_full_i        = 0;\n   reg                            prog_empty_i       = 1;\n   reg [C_WR_PNTR_WIDTH-1:0]      wr_pntr            = 0;\n   reg [C_RD_PNTR_WIDTH-1:0]      rd_pntr            = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg [C_RD_PNTR_WIDTH-1:0]      diff_count         = 0;\n\n   reg                            write_allow_q      = 0;\n   reg                            read_allow_q       = 0;\n   reg                            valid_d1           = 0;\n   reg                            valid_both           = 0;\n   reg                            valid_d2           = 0;\n   wire                           rst_i;\n   wire                           srst_i;\n\n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]         dout_reset_val = 0;\n\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n\n\n\n   /****************************************************************************\n    * Function Declarations\n    ***************************************************************************/\n\n   /****************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***************************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin\n        case (def_data[7:0])\n          8'b00000000 : begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default : begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1) begin\n          if ((index*4)+j < C_DOUT_WIDTH) begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   //reg         valid_d1     = 0;\n   \n   \n   //user specified value for reseting the size of the fifo\n   //reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n\n\n /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n     if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n\n     end\n  endtask\n\n\n   \n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_dout_both    = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_both         = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n\n   end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the\n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n   wire CLK;\n   wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;\n   wire RD_EN;\n   wire RST;\n   wire WR_EN;\n    */\n\n  // Assign ALMOST_EPMTY\n  generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae\n    assign ALMOST_EMPTY = almost_empty_i;\n  end else begin : gnae\n    assign ALMOST_EMPTY = 0;\n  end endgenerate // gae\n\n  // Assign ALMOST_FULL\n  generate if (C_HAS_ALMOST_FULL==1) begin : gaf\n    assign ALMOST_FULL  = almost_full_i;\n  end else begin : gnaf\n    assign ALMOST_FULL  = 0;\n  end endgenerate // gaf\n\n   // Dout may change behavior based on latency\n  localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?\n                         ideal_dout_d1: ideal_dout; \n  assign DOUT = ideal_dout_out;\n\n  // Assign SBITERR and DBITERR based on latency \n  assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[0]: err_type[0]; \n  assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[1]: err_type[1]; \n\n  assign EMPTY         = empty_i;\n  assign FULL          = full_i;\n  //saftey_ckt with one register\n\n  generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)\n          begin\n          if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n              valid_d1 <= #`TCQ 1'b0;\n          end\n          else begin\n               ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n               valid_d1 <= #`TCQ valid_i;\n          end\n          end\n          \n           always@(posedge rst_delayed_sft2 or posedge CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n              end\n           else if (srst_rrst_busy == 1'b1) begin\n                   if (C_USE_DOUT_RST == 1'b1) begin\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   end\n           end else if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                end\n           end   \n      end //if \n      endgenerate   \n\n//safety ckt with both registers\n\ngenerate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK) begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            valid_d1 <= #`TCQ 1'b0;\n          end else begin\n            ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n            fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n            valid_both <= #`TCQ valid_i;\n            valid_d1 <= #`TCQ valid_both;\n          end\n        end\n\n        always@(posedge rst_delayed_sft2 or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                  ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else if (srst_rrst_busy == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else begin \n            if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n            end\n          end\n        end\n      end //if \n      endgenerate    \n \n \n  //Overflow may be active-low\n  generate if (C_HAS_OVERFLOW==1) begin : gof\n    assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n  end else begin : gnof\n    assign OVERFLOW = 0;\n  end endgenerate // gof\n\n  assign PROG_EMPTY    = prog_empty_i;\n  assign PROG_FULL     = prog_full_i;\n\n   //Valid may change behavior based on latency or active-low\n  generate if (C_HAS_VALID==1) begin : gvalid\n    assign valid_i       = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;\n    assign valid_out     = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?\n                            valid_d1 : valid_i; \n    assign VALID         = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n  end else begin : gnvalid\n    assign VALID         = 0;\n  end endgenerate // gvalid\n\n  //Trim data count differently depending on set widths\n  generate if (C_HAS_DATA_COUNT == 1) begin : gdc\n    always @* begin\n      diff_count <= wr_pntr - rd_pntr;\n      if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin\n        DATA_COUNT[C_RD_PNTR_WIDTH-1:0]  <= diff_count;\n        DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; \n      end else begin\n        DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];\n      end\n    end\n//  end else begin : gndc\n//    always @* DATA_COUNT <= 0;\n  end endgenerate // gdc\n\n  //Underflow may change behavior based on latency or active-low\n  generate if (C_HAS_UNDERFLOW==1) begin : guf\n    assign underflow_i   = ideal_underflow;\n    assign UNDERFLOW     = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n  end else begin : gnuf\n    assign UNDERFLOW     = 0;\n  end endgenerate // guf\n \n\n  //Write acknowledge may be active low \n  generate if (C_HAS_WR_ACK==1) begin : gwr_ack\n    assign WR_ACK        = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n  end else begin : gnwr_ack\n    assign WR_ACK        = 0;\n  end endgenerate // gwr_ack\n\n\n  /*****************************************************************************\n   * Internal reset logic \n   ****************************************************************************/\n  assign srst_i        = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;\n  assign rst_i            = C_HAS_RST ? RST : 0;\n  assign srst_wrst_busy   = srst_i;\n  assign srst_rrst_busy   = srst_i;\n\n   /**************************************************************************\n    * Assorted registers for delayed versions of signals\n    **************************************************************************/\n   //Capture delayed version of valid\n   generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20\n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1 <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n           end else begin\n              valid_d1 <= #`TCQ valid_i;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n     end \n   endgenerate // blockVL20\n\n  generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin \n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1   <= 1'b0;\n           valid_both <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n              valid_both <= #`TCQ 1'b0;\n              \n           end else begin\n              valid_both <= #`TCQ valid_i;\n               valid_d1 <= #`TCQ valid_both;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n  end\n endgenerate // blockVL20\n\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge CLK or posedge rst_i) begin\n         if (rst_i) begin\n           stage1_valid     <= #`TCQ 0;\n           stage2_valid     <= #`TCQ 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n\n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc\n       assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc\n       assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n   \n   //reg ram_rd_en_d1 = 1'b0;\n   //Capture delayed version of dout\n   generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         ram_rd_en_d1 <= #`TCQ 1'b0;\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n        end\n      end else begin\n         ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n         if (srst_rrst_busy) begin\n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            // Reset err_type only if ECC is not selected\n            if (C_USE_ECC == 0) begin\n               err_type_d1   <= #`TCQ 0;\n               err_type_both <= #`TCQ 0;\n            end\n            // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n            if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n            end \n         if (C_USE_DOUT_RST == 1) begin\n           // @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         end else begin\n            if (ram_rd_en_d1 ) begin\n            ideal_dout_d1 <= #`TCQ ideal_dout;\n            err_type_d1   <= #`TCQ err_type;\n            end\n         end\n      end    \n   end   // always\nend\nendgenerate \n\n//no safety ckt with both registers\n generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n          ram_rd_en_d1 <= #`TCQ 1'b0;\n          fab_rd_en_d1 <= #`TCQ 1'b0;\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val; \n            \n      end\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val;\n       end\n      end else begin\n         if (srst_rrst_busy) begin \n           ram_rd_en_d1 <= #`TCQ 1'b0;\n           fab_rd_en_d1 <= #`TCQ 1'b0;\n           // Reset err_type only if ECC is not selected\n           if (C_USE_ECC == 0) begin\n              err_type_d1   <= #`TCQ 0;\n              err_type_both <= #`TCQ 0;\n           end\n           // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n           if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n              ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end \n           if (C_USE_DOUT_RST == 1) begin\n             ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end\n         end else begin\n           ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n           fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);\n           if (ram_rd_en_d1 ) begin\n             ideal_dout_both <= #`TCQ ideal_dout;\n             err_type_both   <= #`TCQ err_type;\n           end\n           if (fab_rd_en_d1 ) begin\n             ideal_dout_d1 <= #`TCQ ideal_dout_both;\n             err_type_d1   <= #`TCQ err_type_both;\n           end\n         end\n      end    \n   end   // always\nend\nendgenerate \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n     always @(posedge CLK) begin\n       ideal_overflow    <= #`TCQ WR_EN & full_i;\n     end\n   end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n     always @(posedge CLK) begin\n       //ideal_overflow    <= #`TCQ WR_EN & (rst_i | full_i);\n       ideal_overflow    <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);\n     end\n   end endgenerate // blockOF20\n \n   generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n     always @(posedge CLK) begin\n       ideal_underflow   <= #`TCQ empty_i & RD_EN;\n     end\n   end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n     always @(posedge CLK) begin\n       //ideal_underflow   <= #`TCQ (rst_i | empty_i) & RD_EN;\n       ideal_underflow   <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;\n     end\n   end endgenerate // blockUF20\n\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n\n  /*************************************************************************\n   * Write and Read Logic  \n   ************************************************************************/\n   wire              write_allow;\n   wire              read_allow;\n   wire              read_allow_dc;\n   wire              write_only;\n   wire              read_only;\n   //wire              write_only_q;\n   reg              write_only_q;\n   //wire              read_only_q;\n   reg              read_only_q;\n   reg              full_reg;\n   reg              rst_full_ff_reg1;\n   reg              rst_full_ff_reg2;\n   wire              ram_full_comb;\n   wire              carry;\n   \n   assign write_allow  = WR_EN & ~full_i;\n   assign read_allow   = RD_EN & ~empty_i;\n   assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;\n   //assign write_only   = write_allow & ~read_allow;\n   //assign write_only_q = write_allow_q;\n   //assign read_only    = read_allow    & ~write_allow;\n   //assign read_only_q  = read_allow_q ;\n   wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;\n   wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;\n   wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;\n\n   assign diff_pntr_pe_max = DIFF_MAX_RD;\n   assign diff_pntr_max = DIFF_MAX_WR;\n\n\n\n   generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym\n    assign write_only   = write_allow & ~read_allow;\n    assign read_only    = read_allow    & ~write_allow;\n    end endgenerate\n    generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd\n     assign read_only   = read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;\n     assign write_only    = write_allow    & ~(read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n    generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr\n     assign read_only   = read_allow & ~(write_allow  & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n     assign write_only    = write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;\n    end endgenerate\n\n\n   //-----------------------------------------------------------------------------\n   // Write and Read pointer generation\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       wr_pntr         <= 0;\n       rd_pntr         <= 0;\n     end else begin\n       if (srst_i) begin\n         wr_pntr       <= #`TCQ 0;\n         rd_pntr       <= #`TCQ 0;\n       end else begin\n         if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;\n         if (read_allow)  rd_pntr <= #`TCQ rd_pntr + 1;\n       end\n     end\n   end\n\n   generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout\n   always @(posedge CLK) begin\n     if (write_allow) begin\n       if (ENABLE_ERR_INJECTION == 1)\n         memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};\n       else\n         memory[wr_pntr] <= #`TCQ DIN;\n     end\n   end\n\n   reg  [C_DATA_WIDTH-1:0] dout_tmp_q;\n   reg [C_DATA_WIDTH-1:0] dout_tmp = 0;\n   reg  [C_DATA_WIDTH-1:0] dout_tmp1 = 0;\n   always @(posedge CLK) begin\n     dout_tmp_q <= #`TCQ ideal_dout;\n   end\n\n\n\n     always @* begin\n       if (read_allow)\n         ideal_dout <= memory[rd_pntr];\n       else\n         ideal_dout <= dout_tmp_q;\n     end\n   end endgenerate // gll_dm_dout\n\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   assign ram_rd_en        = RD_EN & !EMPTY;\n\n   //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   generate if (C_FIFO_TYPE != 2) begin : gnll_din\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i == 1'b1) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n\n     end else begin //rst_i==0\n     if (srst_wrst_busy) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n     end else begin//srst_i=0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n         end else begin\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error  \n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           //end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //srst_i==0\n     end //wr_rst_i==0\n   end // gen_fifo_w\n    end endgenerate\n\n   generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout\n     always @(posedge CLK) begin\n       if (rst_i || srst_rrst_busy) begin\n         if (C_USE_DOUT_RST == 1) begin\n           ideal_dout <= #`TCQ dout_reset_val;\n           ideal_dout_both <= #`TCQ dout_reset_val;\n         end\n       end\n     end\n    end endgenerate\n\n\n\n\n   generate if (C_FIFO_TYPE != 2) begin : gnll_dout\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_r\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n\n     end else begin //rd_rst_i==0\n     if (srst_rrst_busy) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets synchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= #`TCQ 0;\n         err_type_both    <= #`TCQ 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n      end //srst_i\n      else begin\n\n       //rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n         if (RD_EN == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end \n           else \n             begin\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n         end\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //s_rst_i==0\n     end //rd_rst_i==0\n   end //always\n  end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate diff_pntr for PROG_FULL generation\n   // Generate diff_pntr_pe for PROG_EMPTY generation\n   //-----------------------------------------------------------------------------\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         write_only_q   <= 1'b0;\n         read_only_q    <= 1'b0;\n         diff_pntr_reg1       <= 0;\n         diff_pntr_pe_reg1    <= 0;\n         diff_pntr_reg2       <= 0;\n         diff_pntr_pe_reg2    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_rrst_busy) begin\n           read_only_q  <= #`TCQ 1'b0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n           diff_pntr_pe_reg2  <= #`TCQ 0;\n          end\n          if (srst_wrst_busy) begin\n           write_only_q <= #`TCQ 1'b0;\n           diff_pntr_reg1     <= #`TCQ 0;\n           diff_pntr_reg2     <= #`TCQ 0;\n          end\n         end else begin\n           write_only_q <= #`TCQ write_only;\n           read_only_q  <= #`TCQ read_only;\n           diff_pntr_reg2  <= #`TCQ diff_pntr_reg1;\n           diff_pntr_pe_reg2  <= #`TCQ diff_pntr_pe_reg1;\n\n           // Add 1 to the difference pointer value when only write happens.\n           if (write_only)  \n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;\n           else\n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;\n\n           // Add 1 to the difference pointer value when write or both write & read or no write & read happen.\n           if (read_only)  \n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;\n           else\n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;\n         end\n       end\n     end\n   assign diff_pntr_pe = diff_pntr_pe_reg1;\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow\n\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym\n    assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};\n    assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         diff_pntr_pe_asym    <= 0;\n         diff_pntr_reg1       <= 0;\n         full_reg             <= 0;\n         rst_full_ff_reg1     <= 1;\n         rst_full_ff_reg2     <= 1;\n         diff_pntr_pe_reg1    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_wrst_busy)\n           diff_pntr_reg1     <= #`TCQ 0;\n          if (srst_rrst_busy)\n           full_reg             <=  #`TCQ 0;\n           rst_full_ff_reg1     <=  #`TCQ 1;\n           rst_full_ff_reg2     <=  #`TCQ 1;\n           diff_pntr_pe_asym    <=  #`TCQ 0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n         end else begin\n             diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;\n             full_reg          <= #`TCQ full_i;\n             rst_full_ff_reg1  <=  #`TCQ RST_FULL_FF;\n             rst_full_ff_reg2  <=  #`TCQ rst_full_ff_reg1;\n           if (~full_i) begin  \n             diff_pntr_reg1 <=  #`TCQ wr_pntr - adj_rd_pntr_wr;\n          end\n         end\n       end\n     end\n   assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));\n   assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow_asym\n\n\n   //-----------------------------------------------------------------------------\n   // Generate FULL flag\n   //-----------------------------------------------------------------------------\n   wire                 comp0;\n   wire                 comp1;\n   wire                 going_full;\n   wire                 leaving_full;\n \n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin :  gpad \t\n    assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;\n    assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin :  gtrim \n    assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n  end endgenerate\n\n   assign comp1         = (adj_rd_pntr_wr == (wr_pntr + 1'b1));\n   assign comp0         = (adj_rd_pntr_wr == wr_pntr);\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp\n     assign going_full    = (comp1 & write_allow & ~read_allow);\n     assign leaving_full  = (comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym\n      assign going_full = (comp1 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_full = (comp0 & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp \n      assign going_full = (comp1 & write_allow & ~read_allow);\n      assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n\n   assign ram_full_comb = going_full | (~leaving_full & full_i);\n\n   generate if (C_HAS_RST == 1) begin : grst_full\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF & C_HAS_RST)\n         full_i   <= C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_SRST == 1) begin : gsrst_full\n     always @(posedge CLK) begin\n       if (srst_wrst_busy)\n         full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_full\n     always @(posedge CLK) begin\n         full_i   <= #`TCQ ram_full_comb;\n     end\n   end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate EMPTY flag\n   //-----------------------------------------------------------------------------\n   wire                 ecomp0;\n   wire                 ecomp1;\n   wire                 going_empty;\n   wire                 leaving_empty;\n   wire                 ram_empty_comb;\n\n  \n generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin :  pad \t\n    assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n    assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin :  trim \n    assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n  end endgenerate\n\n   assign ecomp1         = (adj_wr_pntr_rd == (rd_pntr + 1'b1));\n   assign ecomp0         = (adj_wr_pntr_rd == rd_pntr);\n\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp\n     assign going_empty    = (ecomp1 & ~write_allow & read_allow);\n     assign leaving_empty  = (ecomp0 & write_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp\n      assign going_empty = (ecomp1 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_empty = (ecomp0 & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp \n      assign going_empty = (ecomp1 & ~write_allow & read_allow);\n      assign leaving_empty =(ecomp0 & write_allow);\n    end endgenerate\n\n\n\n    assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);\n\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       empty_i  <= 1'b1;\n     else if (srst_rrst_busy)\n       empty_i  <= #`TCQ 1'b1;\n     else\n       empty_i  <= #`TCQ ram_empty_comb;\n    end\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       EMPTY_FB     <= 1'b1;\n     end else begin\n       if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))\n         EMPTY_FB   <= #`TCQ 1'b1;\n       else\n         EMPTY_FB   <= #`TCQ ram_empty_comb;\n     end\n   end // always\n\n   //-----------------------------------------------------------------------------\n   // Generate Read and write data counts for asymmetic common clock\n   //-----------------------------------------------------------------------------\n\n    reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; \n    wire [C_GRTR_PNTR_WIDTH :0] ratio; \n    wire decr_by_one;\n    wire incr_by_ratio;\n    wire incr_by_one;\n    wire decr_by_ratio;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n\n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr \n      assign ratio         = C_DEPTH_RATIO_RD;\n      assign decr_by_one   = (IS_FWFT == 1)? read_allow_dc : read_allow;\n      assign incr_by_ratio = write_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (decr_by_one) begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc - 1;\n           else\n\t    count_dc <= #`TCQ count_dc - 1  + ratio ;\n\t end\n\t else begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc + ratio ;\n\tend\n       end\n       end\n\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n\n    end endgenerate\n\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd \n      assign ratio         = C_DEPTH_RATIO_WR;\n      assign incr_by_one   = write_allow;\n      assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (incr_by_one) begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc + 1;\n           else\n\t    count_dc <= #`TCQ count_dc + 1  - ratio ;\n\t end\n\t else begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc - ratio ;\n\tend\n       end\n       end\n\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n\n    end endgenerate\n\n\n\n\n\n\n   //-----------------------------------------------------------------------------\n   // Generate WR_ACK flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_wr_ack  <= 1'b0;\n     else if (srst_wrst_busy)\n       ideal_wr_ack  <= #`TCQ 1'b0;\n     else if (WR_EN & ~full_i)\n       ideal_wr_ack  <= #`TCQ 1'b1;\n     else\n       ideal_wr_ack  <= #`TCQ 1'b0;\n    end\n\n   //-----------------------------------------------------------------------------\n   // Generate VALID flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_valid  <= 1'b0;\n     else if (srst_rrst_busy)\n       ideal_valid  <= #`TCQ 1'b0;\n     else if (RD_EN & ~empty_i)\n       ideal_valid  <= #`TCQ 1'b1;\n     else\n       ideal_valid  <= #`TCQ 1'b0;\n    end\n\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_FULL flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss\n\n     wire                 fcomp2;\n     wire                 going_afull;\n     wire                 leaving_afull;\n     wire                 ram_afull_comb;\n\n\n   assign fcomp2         = (adj_rd_pntr_wr == (wr_pntr + 2'h2));\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp\n     assign going_afull    = (fcomp2 & write_allow & ~read_allow);\n     assign leaving_afull  = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym\n      assign going_afull = (fcomp2 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_afull = (comp1 & (~write_allow) & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp \n      assign going_afull = (fcomp2 & write_allow & ~read_allow);\n      assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n     assign ram_afull_comb  = going_afull | (~leaving_afull & almost_full_i);\n\n\n    generate if (C_HAS_RST == 1) begin : grst_afull\n      always @(posedge CLK or posedge RST_FULL_FF) begin\n        if (RST_FULL_FF & C_HAS_RST)\n          almost_full_i   <= C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_SRST == 1) begin : gsrst_afull\n      always @(posedge CLK) begin\n        if (srst_wrst_busy)\n          almost_full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_afull\n      always @(posedge CLK) begin\n          almost_full_i   <= #`TCQ ram_afull_comb;\n      end\n    end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_EMPTY flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss\n\n     wire                 ecomp2;\n     wire                 going_aempty;\n     wire                 leaving_aempty;\n     wire                 ram_aempty_comb;\n      \n     assign ecomp2          = (adj_wr_pntr_rd == (rd_pntr + 2'h2));\n   \n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp\n     assign going_aempty    = (ecomp2 & ~write_allow & read_allow);\n     assign leaving_aempty  = (ecomp1 & write_allow & ~read_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp\n      assign going_aempty = (ecomp2 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp \n      assign going_aempty = (ecomp2 & ~write_allow & read_allow);\n      assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);\n    end endgenerate\n\n\n     assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);\n\n     always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         almost_empty_i  <= 1'b1;\n       else if (srst_rrst_busy)\n         almost_empty_i  <= #`TCQ 1'b1;\n       else\n         almost_empty_i  <= #`TCQ ram_aempty_comb;\n      end\n  // end endgenerate // gae_ss\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL\n   //-----------------------------------------------------------------------------\n\n   localparam  C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT \n                                  C_PROG_FULL_THRESH_ASSERT_VAL; // STD\n   localparam  C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT\n                                  C_PROG_FULL_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;   \n   generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin \n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n          prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr>= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  ((diff_pntr) < C_PF_ASSERT_VAL )\n        prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate // single_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr >= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n       else if  (diff_pntr < C_PF_NEGATE_VAL)\n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate //multiple_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT\n                                               PROG_FULL_THRESH; // STD\n   generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input\n\n     always @(posedge CLK or posedge RST_FULL_FF) begin//0\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin //1\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin//2 \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin//3\n           if (diff_pntr > pf3_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if (diff_pntr == pf3_assert_val) begin//4\n             if (read_only_q)\n               prog_full_i <= #`TCQ 1'b0;\n             else\n               prog_full_i <= #`TCQ 1'b1;\n           end else//4\n             prog_full_i <= #`TCQ 1'b0;\n         end else//3\n           prog_full_i <= #`TCQ prog_full_i;\n       end //2\n       else begin//5\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin//6 \n        if (diff_pntr >= pf3_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  (diff_pntr < pf3_assert_val) begin//7\n         prog_full_i <= #`TCQ 1'b0;\n       end//7\n       end//6\n      else\n           prog_full_i <= #`TCQ prog_full_i;\n       end//5\n     end//1\n     end//0\n   end endgenerate //single_pf_input\n  \n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_ASSERT; // STD\n   wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_NEGATE; // STD\n\n   generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin\n           if (diff_pntr >= pf_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if ((diff_pntr == pf_negate_val && read_only_q) ||\n                  diff_pntr < pf_negate_val)\n             prog_full_i <= #`TCQ 1'b0;\n           else\n             prog_full_i <= #`TCQ prog_full_i;\n         end else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin \n        if (diff_pntr >= pf_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n       else if (diff_pntr < pf_negate_val) \n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n\n     end\n   end\n   end endgenerate //multiple_pf_inputs\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY\n   //-----------------------------------------------------------------------------\n   localparam  C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD\n   localparam  C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i) \n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy) \n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL)\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > C_PE_ASSERT_VAL)\n         prog_empty_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n     end\n     end\n   end endgenerate // single_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > C_PE_NEGATE_VAL) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n\n     end\n\n     end\n   end endgenerate //multiple_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH -2) : // FWFT\n                                                PROG_EMPTY_THRESH; // STD\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe < pe3_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (diff_pntr_pe == pe3_assert_val) begin\n             if (write_only_q)\n               prog_empty_i <= #`TCQ 1'b0;\n             else\n               prog_empty_i <= #`TCQ 1'b1;\n           end else\n             prog_empty_i <= #`TCQ 1'b0;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe3_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > pe3_assert_val)\n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n\n     end\n   end endgenerate // single_pe_input\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_ASSERT; // STD\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_NEGATE; // STD\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n      else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe <= pe4_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || \n                     (diff_pntr_pe > pe4_negate_val)) begin\n             prog_empty_i <= #`TCQ 1'b0;\n           end else\n             prog_empty_i <= #`TCQ prog_empty_i;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe4_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > pe4_negate_val) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n     end\n   end endgenerate // multiple_pe_inputs\n\nendmodule // fifo_generator_v13_2_5_bhv_ver_ss\n\n\n\n/**************************************************************************\n * First-Word Fall-Through module (preload 0)\n **************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_preload0\n  #(\n    parameter  C_DOUT_RST_VAL            = \"\",\n    parameter  C_DOUT_WIDTH              = 8,\n    parameter  C_HAS_RST                 = 0,\n    parameter  C_ENABLE_RST_SYNC         = 0,\n    parameter  C_HAS_SRST                = 0,\n    parameter  C_USE_EMBEDDED_REG        = 0,\n    parameter  C_EN_SAFETY_CKT           = 0, \n    parameter  C_USE_DOUT_RST            = 0,\n    parameter  C_USE_ECC                 = 0,\n    parameter  C_USERVALID_LOW           = 0,\n    parameter  C_USERUNDERFLOW_LOW       = 0,\n    parameter  C_MEMORY_TYPE             = 0,\n    parameter  C_FIFO_TYPE               = 0\n  )\n  (\n    //Inputs\n    input                          SAFETY_CKT_RD_RST,\n    input                          RD_CLK,\n    input                          RD_RST,\n    input                          SRST,\n    input                          WR_RST_BUSY,\n    input                          RD_RST_BUSY,\n    input                          RD_EN,\n    input                          FIFOEMPTY,\n    input       [C_DOUT_WIDTH-1:0] FIFODATA,\n    input                          FIFOSBITERR,\n    input                          FIFODBITERR,\n   \n    //Outputs\n    output reg  [C_DOUT_WIDTH-1:0] USERDATA,\n    output                         USERVALID,\n    output                         USERUNDERFLOW,\n    output                         USEREMPTY,\n    output                         USERALMOSTEMPTY,\n    output                         RAMVALID,\n    output                         FIFORDEN,\n    output reg                     USERSBITERR,\n    output reg                     USERDBITERR,\n    output reg                     STAGE2_REG_EN,\n    output                         fab_read_data_valid_i_o,\n    output                         read_data_valid_i_o,\n    output                         ram_valid_i_o,\n    output      [1:0]              VALID_STAGES \n  );\n //Internal signals\n wire                      preloadstage1;\n wire                      preloadstage2;\n reg                       ram_valid_i;\n reg                       fab_valid;\n reg                       read_data_valid_i;\n reg                       fab_read_data_valid_i;\n reg                       fab_read_data_valid_i_1;\n reg                       ram_valid_i_d;\n reg                       read_data_valid_i_d;\n reg                       fab_read_data_valid_i_d;\n wire                      ram_regout_en;\n reg                       ram_regout_en_d1;\n reg                       ram_regout_en_d2;\n wire                      fab_regout_en;\n wire                      ram_rd_en;\n reg                       empty_i        = 1'b1;\n reg                       empty_sckt     = 1'b1;\n reg                       sckt_rrst_q    = 1'b0;\n reg                       sckt_rrst_done = 1'b0;\n reg                       empty_q        = 1'b1;\n reg                       rd_en_q        = 1'b0;\n reg                       almost_empty_i = 1'b1;\n reg                       almost_empty_q = 1'b1;\n wire                      rd_rst_i;\n wire                      srst_i;\n reg  [C_DOUT_WIDTH-1:0]   userdata_both;\n wire                      uservalid_both;\n wire                      uservalid_one;\n reg                       user_sbiterr_both = 1'b0;\n reg                       user_dbiterr_both = 1'b0;\n  \nassign ram_valid_i_o = ram_valid_i;\nassign read_data_valid_i_o = read_data_valid_i;\nassign fab_read_data_valid_i_o = fab_read_data_valid_i; \n\n\n\n/*************************************************************************\n* FUNCTIONS\n*************************************************************************/\n\n   /*************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***********************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n   \n   //*************************************************************************\n   //  Set power-on states for regs\n   //*************************************************************************\n   initial begin\n      ram_valid_i       = 1'b0;\n      fab_valid         = 1'b0;\n      read_data_valid_i = 1'b0;\n      fab_read_data_valid_i = 1'b0;\n      fab_read_data_valid_i_1 = 1'b0;\n      USERDATA          = hexstr_conv(C_DOUT_RST_VAL);\n      userdata_both          = hexstr_conv(C_DOUT_RST_VAL);\n      USERSBITERR       = 1'b0;\n      USERDBITERR       = 1'b0;\n      user_sbiterr_both = 1'b0;\n      user_dbiterr_both = 1'b0;\n   end //initial\n\n   //***************************************************************************\n   //  connect up optional reset\n   //***************************************************************************\n   assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;\n   assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;\n\n   reg  sckt_rd_rst_fwft = 1'b0;\n   reg  fwft_rst_done_i  = 1'b0;\n   wire fwft_rst_done;\n   assign fwft_rst_done = 1'b1;//C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;\n   always @ (posedge RD_CLK) begin\n     sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;\n   end\n\n   always @ (posedge rd_rst_i or posedge RD_CLK) begin\n     if (rd_rst_i)\n       fwft_rst_done_i  <= 1'b0;\n     else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)\n       fwft_rst_done_i  <= #`TCQ 1'b1;\n   end\n\n   localparam INVALID             = 0;\n   localparam STAGE1_VALID        = 2;\n   localparam STAGE2_VALID        = 1;\n   localparam BOTH_STAGES_VALID   = 3;\n\n   reg  [1:0] curr_fwft_state = INVALID;\n   reg  [1:0] next_fwft_state = INVALID;\n\n\ngenerate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin\n         always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n \n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n     \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n    \n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = preloadstage2;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;\n   end\nendgenerate // gnll_fifo\n\n   reg curr_state         = 0;\n   reg next_state         = 0;\n   reg leaving_empty_fwft = 0;\n   reg going_empty_fwft   = 0;\n   reg empty_i_q          = 0;\n   reg ram_rd_en_fwft     = 0;\n   generate if (C_FIFO_TYPE == 2) begin : gll_fifo\n     always @* begin // FSM fo FWFT\n       case (curr_state)\n         1'b0: begin\n           if (~FIFOEMPTY)\n             next_state <= 1'b1;\n           else\n             next_state <= 1'b0;\n           end\n         1'b1: begin\n           if (FIFOEMPTY && RD_EN)\n             next_state <= 1'b0;\n           else\n             next_state <= 1'b1;\n           end\n         default: next_state <= 1'b0;\n       endcase\n     end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_i       <= 1'b1;\n           empty_i_q     <= 1'b1;\n           ram_valid_i   <= 1'b0;\n        end else if (srst_i) begin\n           empty_i       <= #`TCQ 1'b1;\n           empty_i_q     <= #`TCQ 1'b1;\n           ram_valid_i   <= #`TCQ 1'b0;\n        end else begin\n           empty_i       <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);\n           empty_i_q     <= #`TCQ FIFOEMPTY;\n           ram_valid_i   <= #`TCQ next_state;\n        end\n     end //always\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n           curr_state    <= 1'b0;\n        end else if (srst_i) begin\n           curr_state    <= #`TCQ 1'b0;\n        end else begin\n           curr_state    <= #`TCQ next_state;\n        end\n     end //always\n\n     wire                  fe_of_empty; \n     assign fe_of_empty   = empty_i_q & ~FIFOEMPTY;\n\n     always @* begin // Finding leaving empty\n       case (curr_state)\n         1'b0:    leaving_empty_fwft <= fe_of_empty;\n         1'b1:    leaving_empty_fwft <= 1'b1;\n         default: leaving_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Finding going empty\n       case (curr_state)\n         1'b1:    going_empty_fwft <= FIFOEMPTY & RD_EN;\n         default: going_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Generating FWFT rd_en\n       case (curr_state)\n         1'b0:    ram_rd_en_fwft <= ~FIFOEMPTY;\n         1'b1:    ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;\n         default: ram_rd_en_fwft <= 1'b0;\n       endcase\n     end\n\n     assign ram_regout_en = ram_rd_en_fwft;\n     //assign ram_regout_en_d1 = ram_rd_en_fwft;\n     //assign ram_regout_en_d2 = ram_rd_en_fwft;\n     assign ram_rd_en     = ram_rd_en_fwft;\n   end endgenerate // gll_fifo\n\n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false.\n   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n   generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           ram_valid_i     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              ram_valid_i     <= #`TCQ 1'b0;\n           end else begin\n              if (ram_rd_en == 1'b1) begin\n                 ram_valid_i   <= #`TCQ 1'b1;\n              end else begin\n                 if (ram_regout_en == 1'b1)\n                   ram_valid_i <= #`TCQ 1'b0;\n                 else\n                   ram_valid_i <= #`TCQ ram_valid_i;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_ram_valid\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n  \n generate if(C_USE_EMBEDDED_REG < 3) begin\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else\n        read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);\n   end //always\nend \nendgenerate\n\n   \n   \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n generate if ( C_USE_EMBEDDED_REG < 3) begin\n  always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin         // asynchronous reset (active high)\n             almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ FIFOEMPTY;\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n   \n   \n     \n  // BRAM resets synchronously\n generate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin\n   always @ ( posedge rd_rst_i)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n           @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n             USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end  else if (fwft_rst_done) begin\n            if (ram_regout_en) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end\n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n//safety ckt with one register\ngenerate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n            @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n        end\n     end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n          //@(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end \n       end\n        else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n            //  @(posedge RD_CLK)\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end else if (fwft_rst_done) begin\n            if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end          \n          end\n        end\n       end //always\n  end //if\nendgenerate\n\n\ngenerate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin\n         \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d1 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d1 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d1 <= #`TCQ ram_regout_en;\n                 end\n            end //always\n   //  assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));\n       assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d2 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d2 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;\n                 end\n            end //always\n\n    \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n     always @ (posedge RD_CLK) begin\n        ram_valid_i_d <= #`TCQ ram_valid_i;\n        read_data_valid_i_d <= #`TCQ read_data_valid_i;\n        fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;\n\n     end\n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n    \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;\n   end\n   endgenerate // gnll_fifo\n\n   \n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n     generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid\n\n     \n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           fab_valid     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              fab_valid    <= #`TCQ 1'b0;\n           end else begin\n              if (ram_regout_en == 1'b1) begin\n                 fab_valid  <= #`TCQ 1'b1;\n              end else begin\n                 if (fab_regout_en == 1'b1)\n                   fab_valid <= #`TCQ 1'b0;\n                 else\n                   fab_valid <= #`TCQ fab_valid;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_fab_valid\n\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n    generate if(C_USE_EMBEDDED_REG == 3) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else begin\n        if (ram_regout_en == 1'b1) begin\n          read_data_valid_i <= #`TCQ 1'b1;\n        end else begin\n         if (fab_regout_en == 1'b1)\n          read_data_valid_i <= #`TCQ 1'b0;\n        else\n          read_data_valid_i <= #`TCQ read_data_valid_i;\n        end \n      end \n   end //always\nend\nendgenerate\n\n//generate if(C_USE_EMBEDDED_REG == 3) begin\n//   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n//      if (rd_rst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//      else if (srst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//\n//      if (ram_regout_en == 1'b1) begin\n//        fab_read_data_valid_i <= #`TCQ 1'b0;\n//      end else begin\n//       if (fab_regout_en == 1'b1)\n//        fab_read_data_valid_i <= #`TCQ 1'b1;\n//      else\n//        fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;\n//      end \n//   end //always\n//end\n//endgenerate\n\n     generate if(C_USE_EMBEDDED_REG == 3 ) begin \n    always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid\n      if (rd_rst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else \n        fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);\n   end //always\nend\nendgenerate\n \nalways @ (posedge RD_CLK ) begin : proc_del1\n             begin\n                 fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;\n              end\n            end //always\n \n \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty_both\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n   reg FIFOEMPTY_1;\n   generate if (C_USE_EMBEDDED_REG == 3 ) begin\n    always @(posedge RD_CLK) begin\n            FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;\n           end\n    end\nendgenerate\n    generate if (C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n   begin\n      if (rd_rst_i) begin         // asynchronous reset (active high)\n           almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ (~ram_valid_i);\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_sckt <= #`TCQ 1'b1;\n           sckt_rrst_q <= #`TCQ 1'b0;\n           sckt_rrst_done <= #`TCQ 1'b0;\n        end else begin\n           sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;\n           if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin\n              sckt_rrst_done <= #`TCQ 1'b1;\n           end else if (sckt_rrst_done) begin\n              // rising clock edge\n              empty_sckt <= #`TCQ 1'b0;\n           end\n        end\n     end //always\n   \n   \n//   assign USEREMPTY       = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;\n   assign USEREMPTY       = empty_i;\n   assign USERALMOSTEMPTY = almost_empty_i;\n   assign FIFORDEN        = ram_rd_en;\n   assign RAMVALID        = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;\n   assign uservalid_both       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3)  ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);\n   assign uservalid_one       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3)  ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);\n   assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;\n   assign USERUNDERFLOW   = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;\n//no safety ckt with both reg\ngenerate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n            USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              userdata_both   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end else begin\n            if (fwft_rst_done) begin\n              if (ram_regout_en) begin\n                 userdata_both     <= #`TCQ FIFODATA; \n                 user_dbiterr_both <= #`TCQ FIFODBITERR;\n                 user_sbiterr_both <= #`TCQ FIFOSBITERR; \n              end\n              if (fab_regout_en) begin\n                 USERDATA     <= #`TCQ userdata_both;\n                 USERDBITERR  <= #`TCQ user_dbiterr_both;\n                 USERSBITERR  <= #`TCQ user_sbiterr_both; \n              end             \n            end             \n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n\n//safety_ckt with both registers\n generate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always @ (posedge RD_CLK) begin\n          if (rd_rst_i || srst_i) begin\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n              @(posedge RD_CLK)\n              USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n               userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end\n        end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n     if (rd_rst_i) begin //asynchronous reset (active high)\n       if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n         USERSBITERR       <= #`TCQ 0;\n         USERDBITERR       <= #`TCQ 0;\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end\n       // DRAM resets asynchronously\n       if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n         USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end \n     end else begin // rising clock edge\n       if (srst_i) begin\n         if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n           USERSBITERR       <= #`TCQ 0;\n           USERDBITERR       <= #`TCQ 0;\n           user_sbiterr_both <= #`TCQ 0;\n           user_dbiterr_both <= #`TCQ 0;\n         end\n         if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n           USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end\n       end else if (fwft_rst_done) begin\n         if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            userdata_both     <= #`TCQ FIFODATA;\n            user_dbiterr_both <= #`TCQ FIFODBITERR;\n            user_sbiterr_both <= #`TCQ FIFOSBITERR; \n         end\n         if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            USERDATA          <= #`TCQ userdata_both;\n            USERDBITERR       <= #`TCQ user_dbiterr_both;\n            USERSBITERR       <= #`TCQ user_sbiterr_both;\n         end\n       end\n     end\n   end //always\n  end //if\nendgenerate\n\nendmodule //fifo_generator_v13_2_5_bhv_ver_preload0\n\n\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Register one AXI channel on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   reg_slice\n//\n//--------------------------------------------------------------------------\n\nmodule fifo_generator_v13_2_5_axic_reg_slice #\n  (\n   parameter C_FAMILY     = \"virtex7\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   )\n  (\n   // System Signals\n   input  wire                      ACLK,\n   input  wire                      ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0]   S_PAYLOAD_DATA,\n   input  wire                      S_VALID,\n   output wire                      S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0]   M_PAYLOAD_DATA,\n   output wire                      M_VALID,\n   input  wire                      M_READY\n   );\n\n  localparam RST_SYNC_STAGES = 5;\n  localparam RST_BUSY_LEN    = 6;\n  reg [1:0] arst_sync_wr  = 2'b11;\n  reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n  wire sync_reset;\n  wire extnd_reset;\n\n\n  always @(posedge ARESET or posedge ACLK) begin\n    if (ARESET)\n      arst_sync_wr <= 2'b11;\n    else\n      arst_sync_wr <= #`TCQ {arst_sync_wr[0], 1'b0};\n  end\n\n  always @(posedge ACLK) begin\n    sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[1]};\n  end\n\n  assign sync_reset     = |sckt_wr_rst_cc[RST_BUSY_LEN-5:0] | arst_sync_wr[1]; \n  assign extnd_reset    = |sckt_wr_rst_cc | arst_sync_wr[1];\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000)\n    begin\n      reg [1:0] state;\n      localparam [1:0] \n        ZERO = 2'b10,\n        ONE  = 2'b11,\n        TWO  = 2'b01;\n      \n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg [C_DATA_WIDTH-1:0] storage_data2 = 0;\n      reg                    load_s1;\n      wire                   load_s2;\n      wire                   load_s1_from_s2;\n      reg                    s_ready_i; //local signal of output\n      wire                   m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with either slave side data or from storage2\n      always @(posedge ACLK) \n      begin\n        if (load_s1)\n          if (load_s1_from_s2)\n            storage_data1 <= storage_data2;\n          else\n            storage_data1 <= S_PAYLOAD_DATA;        \n      end\n\n      // Load storage2 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data1;\n\n      // Always load s2 on a valid transaction even if it's unnecessary\n      assign load_s2 = S_VALID & s_ready_i;\n\n      // Loading s1\n      always @ *\n      begin\n        if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction\n             // Load when ONE if we both have read and write at the same time\n             ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||\n             // Load when TWO and we have a transaction on Master side\n             ((state == TWO) && (M_READY == 1)))\n          load_s1 = 1'b1;\n        else\n          load_s1 = 1'b0;\n      end // always @ *\n\n      assign load_s1_from_s2 = (state == TWO);\n                       \n      // State Machine for handling output signals\n      always @(posedge ACLK) begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          state <= ZERO;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          case (state)\n            // No transaction stored locally\n            ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE\n\n            // One transaction stored locally\n            ONE: begin\n              if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO\n              if (~M_READY & S_VALID) begin\n                state <= TWO;  // Got another one so move to TWO\n                s_ready_i <= 1'b0;\n              end\n            end\n\n            // TWO transaction stored locally\n            TWO: if (M_READY) begin\n              state <= ONE; // Read out one so move to ONE\n              s_ready_i <= 1'b1;\n            end\n          endcase // case (state)\n        end\n      end // always @ (posedge ACLK)\n      \n      assign m_valid_i = state[0];\n\n    end // if (C_REG_CONFIG == 1)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000001)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg                    s_ready_i; //local signal of output\n      reg                    m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b0;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else if (m_valid_i & M_READY) begin\n          s_ready_i <= 1'b1;\n          m_valid_i <= 1'b0;\n        end else if (S_VALID & s_ready_i) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b1;\n        end\n        if (~m_valid_i) begin\n          storage_data1 <= S_PAYLOAD_DATA;        \n        end\n      end\n      assign M_PAYLOAD_DATA = storage_data1;\n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // reg_slice\n", "num_lines": 10520}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1\n// IP Revision: 21\n\n(* X_CORE_INFO = \"axi_clock_converter_v2_1_21_axi_clock_converter,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"axi_clock_converter_0,axi_clock_converter_v2_1_21_axi_clock_converter,{}\" *)\n(* CORE_GENERATION_INFO = \"axi_clock_converter_0,axi_clock_converter_v2_1_21_axi_clock_converter,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_clock_converter,x_ipVersion=2.1,x_ipCoreRevision=21,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_ID_WIDTH=16,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=1,C_AXI_PROTOCOL=0,C_AXI_SUPPORTS_USER_SIGNALS=1,C_AXI_AWUSER_WIDTH=19,C_AXI_ARUSER_WIDTH=19,C_AXI_WUSER_WIDTH=1,C_A\\\nXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_SYNCHRONIZER_STAGE=2}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_clock_converter_0 (\n  s_axi_aclk,\n  s_axi_aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awuser,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_aruser,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_aclk,\n  m_axi_aresetn,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awuser,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_aruser,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_CLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 SI_CLK CLK\" *)\ninput wire s_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 SI_RST RST\" *)\ninput wire s_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWUSER\" *)\ninput wire [18 : 0] s_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARUSER\" *)\ninput wire [18 : 0] s_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 19, ARUSER_WIDTH 19, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUS\\\nER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_CLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 MI_CLK CLK\" *)\ninput wire m_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 MI_RST RST\" *)\ninput wire m_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWUSER\" *)\noutput wire [18 : 0] m_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARUSER\" *)\noutput wire [18 : 0] m_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 19, ARUSER_WIDTH 19, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUS\\\nER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_clock_converter_v2_1_21_axi_clock_converter #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_S_AXI_ACLK_RATIO(1),\n    .C_M_AXI_ACLK_RATIO(2),\n    .C_AXI_IS_ACLK_ASYNC(1),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_SUPPORTS_USER_SIGNALS(1),\n    .C_AXI_AWUSER_WIDTH(19),\n    .C_AXI_ARUSER_WIDTH(19),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_AXI_SUPPORTS_WRITE(1),\n    .C_AXI_SUPPORTS_READ(1),\n    .C_SYNCHRONIZER_STAGE(2)\n  ) inst (\n    .s_axi_aclk(s_axi_aclk),\n    .s_axi_aresetn(s_axi_aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(s_axi_awuser),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(s_axi_aruser),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_aclk(m_axi_aclk),\n    .m_axi_aresetn(m_axi_aresetn),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(m_axi_awuser),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(m_axi_aruser),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 443}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sync_clock_converter\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axic_sync_clock_converter # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_FAMILY     = \"virtex6\",\n  parameter integer C_PAYLOAD_WIDTH = 32,\n  parameter integer C_S_ACLK_RATIO = 1,\n  parameter integer C_M_ACLK_RATIO = 1 ,\n  parameter integer C_MODE = 0  // 0 = light-weight (1-deep); 1 = fully-pipelined (2-deep)\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input wire                    SAMPLE_CYCLE_EARLY,\n  input wire                    SAMPLE_CYCLE,\n  // Slave side\n  input  wire                        S_ACLK,\n  input  wire                        S_ARESETN,\n  input  wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD,\n  input  wire                        S_VALID,\n  output wire                        S_READY,\n\n  // Master side\n  input  wire                        M_ACLK,\n  input  wire                        M_ARESETN,\n  output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD,\n  output wire                        M_VALID,\n  input  wire                        M_READY\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam [1:0] ZERO = 2'b10;\nlocalparam [1:0] ONE  = 2'b11;\nlocalparam [1:0] TWO  = 2'b01;\nlocalparam [1:0] INIT = 2'b00;\nlocalparam integer P_LIGHT_WT = 0;\nlocalparam integer P_FULLY_REG = 1;\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\ngenerate\n  if (C_S_ACLK_RATIO == C_M_ACLK_RATIO) begin : gen_passthru\n    assign M_PAYLOAD = S_PAYLOAD;\n    assign M_VALID   = S_VALID;\n    assign S_READY   = M_READY;      \n  end else begin : gen_sync_clock_converter\n    wire s_sample_cycle;\n    wire s_sample_cycle_early;\n    wire m_sample_cycle;\n    wire m_sample_cycle_early;\n\n    wire slow_aclk;\n    wire slow_areset;\n    wire s_areset_r;\n    wire m_areset_r;\n   \n    reg  s_tready_r = 1'b0; \n    wire s_tready_ns; \n    reg  m_tvalid_r = 1'b0; \n    wire m_tvalid_ns; \n    reg  [C_PAYLOAD_WIDTH-1:0] m_tpayload_r;\n    reg  [C_PAYLOAD_WIDTH-1:0] m_tstorage_r;\n    wire [C_PAYLOAD_WIDTH-1:0] m_tpayload_ns; \n    wire [C_PAYLOAD_WIDTH-1:0] m_tstorage_ns; \n    reg  m_tready_hold = 1'b0;\n    wire m_tready_sample;\n    wire load_tpayload;\n    wire load_tstorage;\n    wire load_tpayload_from_tstorage;\n    reg [1:0] state = INIT;\n    reg [1:0] next_state;\n    \n    reg s_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge S_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        s_aresetn_r <= 1'b0;\n      end else begin\n        s_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign s_areset_r = ~s_aresetn_r;\n\n    reg m_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge M_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        m_aresetn_r <= 1'b0;\n      end else begin\n        m_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign m_areset_r = ~m_aresetn_r;\n\n    if (C_S_ACLK_RATIO > C_M_ACLK_RATIO) begin : gen_slowclk_mi\n      assign slow_aclk = M_ACLK;\n    end else begin : gen_slowclk_si\n      assign slow_aclk = S_ACLK;\n    end\n  \n    assign slow_areset = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? m_areset_r : s_areset_r;\n    assign s_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE_EARLY : 1'b1;\n    assign s_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE : 1'b1;\n    assign m_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE_EARLY;\n    assign m_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE;\n\n    // Output flop for S_READY, value is encoded into state machine.\n    assign s_tready_ns = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? state[1] & (state != INIT) : next_state[1];\n\n    always @(posedge S_ACLK) begin \n      if (s_areset_r) begin\n        s_tready_r <= 1'b0;\n      end\n      else begin\n        s_tready_r <= s_sample_cycle_early ? s_tready_ns : 1'b0;\n      end\n    end\n\n    assign S_READY = s_tready_r;\n\n    // Output flop for M_VALID\n    assign m_tvalid_ns = next_state[0];\n\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tvalid_r <= 1'b0;\n      end\n      else begin\n        m_tvalid_r <= m_sample_cycle ? m_tvalid_ns : m_tvalid_r & ~M_READY;\n      end\n    end\n\n    assign M_VALID = m_tvalid_r;\n\n    // Hold register for M_READY when M_ACLK is fast.\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tready_hold <= 1'b0;\n      end\n      else begin\n        m_tready_hold <= m_sample_cycle ? 1'b0 : m_tready_sample;\n      end\n    end\n\n    assign m_tready_sample = (M_READY ) | m_tready_hold;\n    // Output/storage flops for PAYLOAD\n    assign m_tpayload_ns = ~load_tpayload ? m_tpayload_r :\n                           load_tpayload_from_tstorage ? m_tstorage_r : \n                           S_PAYLOAD;\n\n    assign m_tstorage_ns = C_MODE ? (load_tstorage ? S_PAYLOAD : m_tstorage_r) : 0;\n\n    always @(posedge slow_aclk) begin \n      m_tpayload_r <= m_tpayload_ns;\n      m_tstorage_r <= C_MODE ? m_tstorage_ns : 0;\n    end\n\n    assign M_PAYLOAD = m_tpayload_r;\n\n    // load logic\n    assign load_tstorage = C_MODE && (state != TWO);\n    assign load_tpayload = m_tready_sample || (state == ZERO);\n    assign load_tpayload_from_tstorage = C_MODE && (state == TWO) && m_tready_sample;\n    \n    // State machine\n    always @(posedge slow_aclk) begin \n      state <= next_state;\n    end\n\n    always @* begin \n      if (slow_areset) begin \n        next_state = INIT;\n      end else begin\n        case (state)\n          INIT: begin\n            next_state = ZERO;\n          end\n          // No transaction stored locally\n          ZERO: begin\n            if (S_VALID) begin\n              next_state = C_MODE ? ONE : TWO; // Push from empty\n            end\n            else begin\n              next_state = ZERO;\n            end\n          end\n\n          // One transaction stored locally\n          ONE: begin\n            if (C_MODE == 0) begin\n              next_state = TWO;  // State ONE is inaccessible when C_MODE=0\n            end \n            else if (m_tready_sample & ~S_VALID) begin \n              next_state = ZERO; // Read out one so move to ZERO\n            end\n            else if (~m_tready_sample & S_VALID) begin\n              next_state = TWO;  // Got another one so move to TWO\n            end\n            else begin\n              next_state = ONE;\n            end\n          end\n\n          // Storage registers full\n          TWO: begin \n            if (m_tready_sample) begin\n              next_state = C_MODE ? ONE : ZERO; // Pop from full\n            end\n            else begin\n              next_state = TWO;\n            end\n          end\n        endcase // case (state)\n      end\n    end\n  end // gen_sync_clock_converter\n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sample_cycle_ratio\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axic_sample_cycle_ratio # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_RATIO = 2 // Must be > 0\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    SLOW_ACLK,\n  input  wire                    FAST_ACLK,\n\n  output wire                    SAMPLE_CYCLE_EARLY,\n  output wire                    SAMPLE_CYCLE\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam P_DELAY = C_RATIO > 2 ? C_RATIO-1 : C_RATIO-1; \n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_aclk_div2 = 1'b0;\nreg                posedge_finder_first = 1'b0;\nreg                posedge_finder_second = 1'b0;\nwire               first_edge;\nwire               second_edge;\nwire               any_edge;\nreg  [P_DELAY-1:0] sample_cycle_d = {P_DELAY{1'b0}};\n(* shreg_extract = \"no\" *) reg                sample_cycle_r = 1'b0;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\ngenerate\n  if (C_RATIO == 1) begin : gen_always_sample\n    assign SAMPLE_CYCLE_EARLY = 1'b1;\n    assign SAMPLE_CYCLE = 1'b1;\n  end\n  else begin : gen_sample_cycle\n    genvar i;\n    always @(posedge SLOW_ACLK) begin \n      slow_aclk_div2 <= ~slow_aclk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_aclk_div2 onto faster clock\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_first <= slow_aclk_div2;\n    end\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_second <= ~slow_aclk_div2;\n    end\n\n    assign first_edge = slow_aclk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;\n    assign any_edge = first_edge | second_edge;\n   \n    // delay the posedge alignment by C_RATIO - 1 to set the sample cycle as\n    // the clock one cycle before the posedge.\n    for (i = P_DELAY-1; i > 0; i = i - 1) begin : gen_delay\n      always @(posedge FAST_ACLK) begin\n        if (i == P_DELAY-1) begin\n          sample_cycle_d[i-1] <= any_edge;\n        end else begin\n          sample_cycle_d[i-1] <= sample_cycle_d[i];\n        end\n      end\n    end\n\n    always @(posedge FAST_ACLK) begin \n      sample_cycle_r <= (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    end\n    assign SAMPLE_CYCLE_EARLY = (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    assign SAMPLE_CYCLE = sample_cycle_r;\n  end\nendgenerate\n\nendmodule // axisc_sample_cycle_ratio\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2010 - 2016 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and\n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Clock converter module\n//   Asynchronous clock converter when asynchronous M:N conversion\n//   Bypass when synchronous and ratio between S and M clock is 1:1\n//   Synchronous clock converter (S:M or M:S must be integer ratio)\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_clock_conv\n//     fifo_generator\n//     axic_sync_clock_converter\n//       axic_sample_cycle_ratio\n//\n// PROTECTED NAMES:\n//   Instance names \"asyncfifo_*\" are pattern-matched in core-level UCF.\n//   Signal names \"*_resync\" are pattern-matched in core-level UCF.\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_lite_async #(\n  parameter integer C_DEST_SYNC_FF = 3,\n  parameter integer C_SRC_SYNC_FF  = 3,\n  parameter integer C_WIDTH        = 1\n) (\n  input wire                s_aclk,\n  input wire                m_aclk,\n  input wire                s_aresetn,\n  input wire                m_aresetn,\n  input wire                s_valid,\n  output wire                s_ready,\n  input wire [C_WIDTH-1:0]  s_payld,\n  output wire                m_valid,\n  input wire                m_ready,\n  output wire [C_WIDTH-1:0] m_payld\n);\n\nreg [C_SRC_SYNC_FF:0] s_areset_dly = {C_SRC_SYNC_FF+1{1'b0}};\nreg [C_DEST_SYNC_FF:0] m_areset_dly = {C_DEST_SYNC_FF+1{1'b0}};\nreg                s_ready_i = 1'b0;\nreg                m_valid_i = 1'b0;\nreg   src_send = 1'b0;\nreg   dest_ack = 1'b0;\nwire  src_rcv;\nwire  dest_req;\n\nassign s_ready = s_ready_i;\nassign m_valid = m_valid_i;\n\nlocalparam SRC_IDLE           = 2'b00;\nlocalparam SRC_DRV_SEND       = 2'b01;\nlocalparam SRC_WAIT_RCV_DONE  = 2'b10;\nreg [1:0] src_state = SRC_IDLE;\n\nalways @(posedge s_aclk) begin\n  s_areset_dly <= {C_SRC_SYNC_FF+1{~s_aresetn}} | (s_areset_dly<<1);\n  if (s_areset_dly[C_SRC_SYNC_FF]) begin\n    s_ready_i <= 1'b0;\n    src_send <= 1'b0;\n    src_state <= SRC_IDLE;\n  end else begin\n    case (src_state)\n      SRC_IDLE: begin\n        if (s_valid) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end\n      end\n      SRC_DRV_SEND: begin\n        if (src_rcv) begin\n          s_ready_i <= 1'b1;\n          src_send <= 1'b0;\n          src_state <= SRC_WAIT_RCV_DONE;\n        end\n      end\n      SRC_WAIT_RCV_DONE: begin\n        s_ready_i <= 1'b0;\n        if (s_valid & !src_rcv) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end else if (!src_rcv) begin\n          src_state <= SRC_IDLE;\n        end\n      end\n      default: begin\n        s_ready_i <= 1'b0;\n        src_send <= 1'b0;\n        src_state <= SRC_IDLE;\n      end\n    endcase\n  end\nend\n\nlocalparam DEST_IDLE           = 2'b00;\nlocalparam DEST_DRV_VALID      = 2'b01;\nlocalparam DEST_DRV_ACK        = 2'b10;\nreg [1:0] dest_state = DEST_IDLE;\n\nalways @(posedge m_aclk) begin\n  m_areset_dly <= {C_DEST_SYNC_FF+1{~m_aresetn}} | (m_areset_dly<<1);\n  if (m_areset_dly[C_DEST_SYNC_FF]) begin\n    m_valid_i <= 1'b0;\n    dest_ack <= 1'b0;\n    dest_state <= DEST_IDLE;\n  end else begin\n    case (dest_state)\n      DEST_IDLE: begin\n        if (dest_req) begin\n          dest_state <= DEST_DRV_VALID;\n          m_valid_i <= 1'b1;\n        end else begin\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b0;\n        end\n      end\n      DEST_DRV_VALID: begin\n        if (m_ready & m_valid_i) begin\n          dest_state <= DEST_DRV_ACK;\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b1;\n        end\n      end\n      DEST_DRV_ACK: begin\n        if (!dest_req) begin\n          dest_state <= DEST_IDLE;\n          dest_ack <= 1'b0;\n        end\n      end\n      default: begin\n        m_valid_i <= 1'b0;\n        dest_ack <= 1'b0;\n        dest_state <= DEST_IDLE;\n      end\n    endcase\n  end\nend\n\nxpm_cdc_handshake #(\n  .DEST_SYNC_FF   (C_DEST_SYNC_FF),\n  .SRC_SYNC_FF    (C_SRC_SYNC_FF),\n  .WIDTH          (C_WIDTH)\n) handshake (\n  .src_clk  (s_aclk),\n  .src_in   (s_payld),\n  .src_send (src_send),\n  .src_rcv  (src_rcv),\n  .dest_clk (m_aclk),\n  .dest_out (m_payld),\n  .dest_req (dest_req),\n  .dest_ack (dest_ack)\n);\n\nendmodule\n\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axi_clock_converter #\n  (parameter         C_FAMILY = \"virtex7\",\n   parameter integer C_AXI_ID_WIDTH = 5,                    // Width of all ID signals on SI and MI side.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ADDR_WIDTH = 32,                 // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and\n                                                            // m_axi_araddr.\n                                                            // Range: 32.\n   parameter integer C_AXI_DATA_WIDTH = 32,       // Width of WDATA and RDATA (either side).\n                                                            // Format: Bit32;\n                                                            // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.\n   parameter integer C_S_AXI_ACLK_RATIO = 1,     // Clock frequency ratio of SI w.r.t. MI.\n   parameter integer C_M_AXI_ACLK_RATIO = 1,     // (Slowest of all clock inputs should have ratio=1.)\n                                                            // S:M or M:S must be integer ratio.\n                                                            // Format: Bit32; Range: >='h00000001.\n   parameter integer C_AXI_IS_ACLK_ASYNC = 1,            // Indicates whether S and M clocks are asynchronous.\n                                                            // FUTURE FEATURE\n                                                            // Format: Bit1. Range = 1'b0.\n   parameter integer C_AXI_PROTOCOL = 0,         // Protocol of this SI/MI slot.\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS  = 1,      // 1 = Propagate all USER signals, 0 = Do not propagate.\n   parameter integer C_AXI_AWUSER_WIDTH = 1,                // Width of AWUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ARUSER_WIDTH = 1,                // Width of ARUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_WUSER_WIDTH = 1,                 // Width of WUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_RUSER_WIDTH = 1,                 // Width of RUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_BUSER_WIDTH = 1,                 // Width of BUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,              // Implement AXI write channels\n   parameter integer C_AXI_SUPPORTS_READ = 1,               // Implement AXI read channels\n   parameter integer C_SYNCHRONIZER_STAGE = 3\n  )\n\n  (\n   // Slave Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n   input  wire [4-1:0]                    s_axi_awcache,\n   input  wire [3-1:0]                    s_axi_awprot,\n   input  wire [4-1:0]                    s_axi_awregion,\n   input  wire [4-1:0]                    s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0]   s_axi_awuser,\n   input  wire                            s_axi_awvalid,\n   output wire                            s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n   input  wire                            s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]    s_axi_wuser,\n   input  wire                            s_axi_wvalid,\n   output wire                            s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_bid,\n   output wire [2-1:0]                    s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0]    s_axi_buser,\n   output wire                            s_axi_bvalid,\n   input  wire                            s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n   input  wire [3-1:0]                    s_axi_arsize,\n   input  wire [2-1:0]                    s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n   input  wire [4-1:0]                    s_axi_arcache,\n   input  wire [3-1:0]                    s_axi_arprot,\n   input  wire [4-1:0]                    s_axi_arregion,\n   input  wire [4-1:0]                    s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0]   s_axi_aruser,\n   input  wire                            s_axi_arvalid,\n   output wire                            s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n   output wire [2-1:0]                    s_axi_rresp,\n   output wire                            s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0]    s_axi_ruser,\n   output wire                            s_axi_rvalid,\n   input  wire                            s_axi_rready,\n\n   // Master Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aresetn,\n\n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n   output wire [3-1:0]                    m_axi_awsize,\n   output wire [2-1:0]                    m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n   output wire [4-1:0]                    m_axi_awcache,\n   output wire [3-1:0]                    m_axi_awprot,\n   output wire [4-1:0]                    m_axi_awregion,\n   output wire [4-1:0]                    m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0]   m_axi_awuser,\n   output wire                            m_axi_awvalid,\n   input  wire                            m_axi_awready,\n\n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0]   m_axi_wstrb,\n   output wire                            m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]    m_axi_wuser,\n   output wire                            m_axi_wvalid,\n   input  wire                            m_axi_wready,\n\n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_bid,\n   input  wire [2-1:0]                    m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0]    m_axi_buser,\n   input  wire                            m_axi_bvalid,\n   output wire                            m_axi_bready,\n\n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n   output wire [3-1:0]                    m_axi_arsize,\n   output wire [2-1:0]                    m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n   output wire [4-1:0]                    m_axi_arcache,\n   output wire [3-1:0]                    m_axi_arprot,\n   output wire [4-1:0]                    m_axi_arregion,\n   output wire [4-1:0]                    m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0]   m_axi_aruser,\n   output wire                            m_axi_arvalid,\n   input  wire                            m_axi_arready,\n\n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     m_axi_rdata,\n   input  wire [2-1:0]                    m_axi_rresp,\n   input  wire                            m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0]    m_axi_ruser,\n   input  wire                            m_axi_rvalid,\n   output wire                            m_axi_rready);\n\n  localparam integer P_AXI4 = 0;\n  localparam integer P_AXI3 = 1;\n  localparam integer P_AXILITE = 2;\n  localparam integer P_LIGHT_WT = 0;\n  localparam integer P_FULLY_REG = 1;\n  localparam integer P_LUTRAM_ASYNC = 12;\n\n  // Sample cycle ratio\n  localparam  P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);\n  localparam integer P_ROUNDING_OFFSET = P_SI_LT_MI ? (C_S_AXI_ACLK_RATIO/2) : (C_M_AXI_ACLK_RATIO/2);\n  localparam integer P_ACLK_RATIO = P_SI_LT_MI ?\n    ((C_M_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_S_AXI_ACLK_RATIO) :\n    ((C_S_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_M_AXI_ACLK_RATIO);\n\n  // Write Address Port bit positions\n  localparam integer C_AWUSER_RIGHT   = 0;\n  localparam integer C_AWUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_AWUSER_WIDTH : 0;\n  localparam integer C_AWQOS_RIGHT    = C_AWUSER_RIGHT + C_AWUSER_WIDTH;\n  localparam integer C_AWQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWREGION_RIGHT = C_AWQOS_RIGHT + C_AWQOS_WIDTH;\n  localparam integer C_AWREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_AWPROT_RIGHT   = C_AWREGION_RIGHT + C_AWREGION_WIDTH;\n  localparam integer C_AWPROT_WIDTH     = 3;\n  localparam integer C_AWCACHE_RIGHT  = C_AWPROT_RIGHT + C_AWPROT_WIDTH;\n  localparam integer C_AWCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWLOCK_RIGHT   = C_AWCACHE_RIGHT + C_AWCACHE_WIDTH;\n  localparam integer C_AWLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_AWBURST_RIGHT  = C_AWLOCK_RIGHT + C_AWLOCK_WIDTH;\n  localparam integer C_AWBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_AWSIZE_RIGHT   = C_AWBURST_RIGHT + C_AWBURST_WIDTH;\n  localparam integer C_AWSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_AWLEN_RIGHT    = C_AWSIZE_RIGHT + C_AWSIZE_WIDTH;\n  localparam integer C_AWLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_AWADDR_RIGHT   = C_AWLEN_RIGHT + C_AWLEN_WIDTH;\n  localparam integer C_AWADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_AWID_RIGHT     = C_AWADDR_RIGHT + C_AWADDR_WIDTH;\n  localparam integer C_AWID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AW_WIDTH        = C_AWID_RIGHT + C_AWID_WIDTH;\n  localparam integer C_FIFO_AW_WIDTH   = C_AWUSER_WIDTH+C_AWQOS_WIDTH+C_AWQOS_WIDTH+3+C_AWCACHE_WIDTH+C_AWLOCK_WIDTH+C_AWBURST_WIDTH+C_AWSIZE_WIDTH+C_AWLEN_WIDTH+C_AXI_ADDR_WIDTH+C_AWID_WIDTH;\n\n  // Write Data Port bit positions\n  localparam integer C_WUSER_RIGHT   = 0;\n  localparam integer C_WUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_WUSER_WIDTH : 0;\n  localparam integer C_WLAST_RIGHT   = C_WUSER_RIGHT + C_WUSER_WIDTH;\n  localparam integer C_WLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_WSTRB_RIGHT   = C_WLAST_RIGHT + C_WLAST_WIDTH;\n  localparam integer C_WSTRB_WIDTH     = C_AXI_DATA_WIDTH/8;\n  localparam integer C_WDATA_RIGHT   = C_WSTRB_RIGHT + C_WSTRB_WIDTH;\n  localparam integer C_WDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_WID_RIGHT     = C_WDATA_RIGHT + C_WDATA_WIDTH;\n  localparam integer C_WID_WIDTH       = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_W_WIDTH        = C_WID_RIGHT + C_WID_WIDTH;\n  localparam integer C_FIFO_W_WIDTH   = C_WUSER_WIDTH + C_WLAST_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_DATA_WIDTH + C_WID_WIDTH;\n\n  // Write Response Port bit positions\n  localparam integer C_BUSER_RIGHT   = 0;\n  localparam integer C_BUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_BUSER_WIDTH : 0;\n  localparam integer C_BRESP_RIGHT   = C_BUSER_RIGHT + C_BUSER_WIDTH;\n  localparam integer C_BRESP_WIDTH     = 2;\n  localparam integer C_BID_RIGHT     = C_BRESP_RIGHT + C_BRESP_WIDTH;\n  localparam integer C_BID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_B_WIDTH        = C_BID_RIGHT + C_BID_WIDTH;\n  localparam integer C_FIFO_B_WIDTH    = C_BUSER_WIDTH + 2 + C_BID_WIDTH;\n\n  // Read Address Port bit positions\n  localparam integer C_ARUSER_RIGHT   = 0;\n  localparam integer C_ARUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_ARUSER_WIDTH : 0;\n  localparam integer C_ARQOS_RIGHT    = C_ARUSER_RIGHT + C_ARUSER_WIDTH;\n  localparam integer C_ARQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARREGION_RIGHT = C_ARQOS_RIGHT + C_ARQOS_WIDTH;\n  localparam integer C_ARREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_ARPROT_RIGHT   = C_ARREGION_RIGHT + C_ARREGION_WIDTH;\n  localparam integer C_ARPROT_WIDTH     = 3;\n  localparam integer C_ARCACHE_RIGHT  = C_ARPROT_RIGHT + C_ARPROT_WIDTH;\n  localparam integer C_ARCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARLOCK_RIGHT   = C_ARCACHE_RIGHT + C_ARCACHE_WIDTH;\n  localparam integer C_ARLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_ARBURST_RIGHT  = C_ARLOCK_RIGHT + C_ARLOCK_WIDTH;\n  localparam integer C_ARBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_ARSIZE_RIGHT   = C_ARBURST_RIGHT + C_ARBURST_WIDTH;\n  localparam integer C_ARSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_ARLEN_RIGHT    = C_ARSIZE_RIGHT + C_ARSIZE_WIDTH;\n  localparam integer C_ARLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_ARADDR_RIGHT   = C_ARLEN_RIGHT + C_ARLEN_WIDTH;\n  localparam integer C_ARADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_ARID_RIGHT     = C_ARADDR_RIGHT + C_ARADDR_WIDTH;\n  localparam integer C_ARID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AR_WIDTH        = C_ARID_RIGHT + C_ARID_WIDTH;\n  localparam integer C_FIFO_AR_WIDTH   = C_ARUSER_WIDTH+C_ARQOS_WIDTH+C_ARQOS_WIDTH+3+C_ARCACHE_WIDTH+C_ARLOCK_WIDTH+C_ARBURST_WIDTH+C_ARSIZE_WIDTH+C_ARLEN_WIDTH+C_AXI_ADDR_WIDTH+C_ARID_WIDTH;\n\n  // Read Data Ports bit positions\n  localparam integer C_RUSER_RIGHT   = 0;\n  localparam integer C_RUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_RUSER_WIDTH : 0;\n  localparam integer C_RLAST_RIGHT   = C_RUSER_RIGHT + C_RUSER_WIDTH;\n  localparam integer C_RLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_RRESP_RIGHT   = C_RLAST_RIGHT + C_RLAST_WIDTH;\n  localparam integer C_RRESP_WIDTH     = 2;\n  localparam integer C_RDATA_RIGHT   = C_RRESP_RIGHT + C_RRESP_WIDTH;\n  localparam integer C_RDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_RID_RIGHT     = C_RDATA_RIGHT + C_RDATA_WIDTH;\n  localparam integer C_RID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_R_WIDTH        = C_RID_RIGHT + C_RID_WIDTH;\n  localparam integer C_FIFO_R_WIDTH   = C_RUSER_WIDTH + C_RLAST_WIDTH + 2 + C_AXI_DATA_WIDTH + C_RID_WIDTH;\n\n  generate\n    if ((C_AXI_IS_ACLK_ASYNC == 0) && (P_ACLK_RATIO == 1)) begin : gen_bypass\n      \n      // Write address port\n      assign m_axi_awid     = s_axi_awid;\n      assign m_axi_awaddr   = s_axi_awaddr;\n      assign m_axi_awlen    = s_axi_awlen;\n      assign m_axi_awsize   = s_axi_awsize;\n      assign m_axi_awburst  = s_axi_awburst;\n      assign m_axi_awlock   = s_axi_awlock;\n      assign m_axi_awcache  = s_axi_awcache;\n      assign m_axi_awprot   = s_axi_awprot;\n      assign m_axi_awregion = s_axi_awregion;\n      assign m_axi_awqos    = s_axi_awqos;\n      assign m_axi_awuser   = s_axi_awuser;\n      assign m_axi_awvalid  = s_axi_awvalid;\n      assign s_axi_awready  = m_axi_awready;\n\n      // Write Data Port\n      assign m_axi_wid      = s_axi_wid;\n      assign m_axi_wdata    = s_axi_wdata;\n      assign m_axi_wstrb    = s_axi_wstrb;\n      assign m_axi_wlast    = s_axi_wlast;\n      assign m_axi_wuser    = s_axi_wuser;\n      assign m_axi_wvalid   = s_axi_wvalid;\n      assign s_axi_wready   = m_axi_wready;\n\n      // Write Response Port\n      assign s_axi_bid      = m_axi_bid;\n      assign s_axi_bresp    = m_axi_bresp;\n      assign s_axi_buser    = m_axi_buser;\n      assign s_axi_bvalid   = m_axi_bvalid;\n      assign m_axi_bready   = s_axi_bready;\n\n      // Read Address Port\n      assign m_axi_arid     = s_axi_arid;\n      assign m_axi_araddr   = s_axi_araddr;\n      assign m_axi_arlen    = s_axi_arlen;\n      assign m_axi_arsize   = s_axi_arsize;\n      assign m_axi_arburst  = s_axi_arburst;\n      assign m_axi_arlock   = s_axi_arlock;\n      assign m_axi_arcache  = s_axi_arcache;\n      assign m_axi_arprot   = s_axi_arprot;\n      assign m_axi_arregion = s_axi_arregion;\n      assign m_axi_arqos    = s_axi_arqos;\n      assign m_axi_aruser   = s_axi_aruser;\n      assign m_axi_arvalid  = s_axi_arvalid;\n      assign s_axi_arready  = m_axi_arready;\n\n      // Read Data Port\n      assign s_axi_rid      = m_axi_rid;\n      assign s_axi_rdata    = m_axi_rdata;\n      assign s_axi_rresp    = m_axi_rresp;\n      assign s_axi_rlast    = m_axi_rlast;\n      assign s_axi_ruser    = m_axi_ruser;\n      assign s_axi_rvalid   = m_axi_rvalid;\n      assign m_axi_rready   = s_axi_rready;\n      \n    end else begin : gen_clock_conv\n      \n      wire fast_aclk;\n      wire slow_aclk;\n      wire sample_cycle;\n      wire sample_cycle_early;\n    \n      // Write Address Port FIFO data read and write\n      wire [C_AW_WIDTH-1:0] s_aw_mesg ;\n      wire [C_AW_WIDTH-1:0] m_aw_mesg ;\n    \n      // Write Data Port FIFO data read and write\n      wire [C_W_WIDTH-1:0] s_w_mesg;\n      wire [C_W_WIDTH-1:0] m_w_mesg;\n    \n      // Write Response Port FIFO data read and write\n      wire [C_B_WIDTH-1:0] s_b_mesg;\n      wire [C_B_WIDTH-1:0] m_b_mesg;\n    \n      // Read Address Port FIFO data read and write\n      wire [C_AR_WIDTH-1:0] s_ar_mesg;\n      wire [C_AR_WIDTH-1:0] m_ar_mesg;\n    \n      // Read Data Ports FIFO data read and write\n      wire [C_R_WIDTH-1:0] s_r_mesg;\n      wire [C_R_WIDTH-1:0] m_r_mesg;\n    \n      wire async_conv_reset_n;\n      assign async_conv_reset_n = ~(~s_axi_aresetn | ~m_axi_aresetn);\n      \n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_awlen           ;\n      wire [3-1:0]                       si_cc_awsize          ;\n      wire [2-1:0]                       si_cc_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_awlock          ;\n      wire [4-1:0]                       si_cc_awcache         ;\n      wire [3-1:0]                       si_cc_awprot          ;\n      wire [4-1:0]                       si_cc_awregion        ;\n      wire [4-1:0]                       si_cc_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]      si_cc_awuser          ;\n      wire                               si_cc_awvalid         ;\n      wire                               si_cc_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_wid            ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]      si_cc_wstrb           ;\n      wire                               si_cc_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]       si_cc_wuser           ;\n      wire                               si_cc_wvalid          ;\n      wire                               si_cc_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_bid             ;\n      wire [2-1:0]                       si_cc_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]       si_cc_buser           ;\n      wire                               si_cc_bvalid          ;\n      wire                               si_cc_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_arlen           ;\n      wire [3-1:0]                       si_cc_arsize          ;\n      wire [2-1:0]                       si_cc_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_arlock          ;\n      wire [4-1:0]                       si_cc_arcache         ;\n      wire [3-1:0]                       si_cc_arprot          ;\n      wire [4-1:0]                       si_cc_arregion        ;\n      wire [4-1:0]                       si_cc_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]      si_cc_aruser          ;\n      wire                               si_cc_arvalid         ;\n      wire                               si_cc_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_rdata           ;\n      wire [2-1:0]                       si_cc_rresp           ;\n      wire                               si_cc_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]       si_cc_ruser           ;\n      wire                               si_cc_rvalid          ;\n      wire                               si_cc_rready          ;\n      \n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_awlen           ;\n      wire [3-1:0]                      cc_mi_awsize          ;\n      wire [2-1:0]                      cc_mi_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_awlock          ;\n      wire [4-1:0]                      cc_mi_awcache         ;\n      wire [3-1:0]                      cc_mi_awprot          ;\n      wire [4-1:0]                      cc_mi_awregion        ;\n      wire [4-1:0]                      cc_mi_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]     cc_mi_awuser          ;\n      wire                              cc_mi_awvalid         ;\n      wire                              cc_mi_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_wid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]     cc_mi_wstrb           ;\n      wire                              cc_mi_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]      cc_mi_wuser           ;\n      wire                              cc_mi_wvalid          ;\n      wire                              cc_mi_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_bid             ;\n      wire [2-1:0]                      cc_mi_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]      cc_mi_buser           ;\n      wire                              cc_mi_bvalid          ;\n      wire                              cc_mi_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_arlen           ;\n      wire [3-1:0]                      cc_mi_arsize          ;\n      wire [2-1:0]                      cc_mi_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_arlock          ;\n      wire [4-1:0]                      cc_mi_arcache         ;\n      wire [3-1:0]                      cc_mi_arprot          ;\n      wire [4-1:0]                      cc_mi_arregion        ;\n      wire [4-1:0]                      cc_mi_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]     cc_mi_aruser          ;\n      wire                              cc_mi_arvalid         ;\n      wire                              cc_mi_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_rdata           ;\n      wire [2-1:0]                      cc_mi_rresp           ;\n      wire                              cc_mi_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]      cc_mi_ruser           ;\n      wire                              cc_mi_rvalid          ;\n      wire                              cc_mi_rready          ;\n      \n    // Tie-offs\n      assign si_cc_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awid : 0 ;\n      assign si_cc_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awaddr : 0 ;\n      assign si_cc_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_awlen : {4'b0000, s_axi_awlen[3:0]}) : 0 ;\n      assign si_cc_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize : 0 ;\n      assign si_cc_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst : 0 ;\n      assign si_cc_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_awlock : {1'b0, s_axi_awlock[0]}) : 0 ;\n      assign si_cc_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache : 0 ;\n      assign si_cc_awprot    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awprot : 0 ;\n      assign si_cc_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos : 0 ;\n      assign si_cc_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion : 0 ;\n      assign si_cc_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser : 0 ;\n      assign si_cc_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awvalid : 0 ;\n      assign si_cc_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? s_axi_wid : 0 ;\n      assign si_cc_wdata     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wdata : 0 ;\n      assign si_cc_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wstrb : 0 ;\n      assign si_cc_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast : 1'b0 ;\n      assign si_cc_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser : 0 ;\n      assign si_cc_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wvalid : 0 ;\n      assign si_cc_bready    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_bready : 0 ;\n      assign si_cc_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arid : 0 ;\n      assign si_cc_araddr    = (C_AXI_SUPPORTS_READ ) ? s_axi_araddr : 0 ;\n      assign si_cc_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_arlen : {4'b0000, s_axi_arlen[3:0]}) : 0 ;\n      assign si_cc_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize : 0 ;\n      assign si_cc_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst : 0 ;\n      assign si_cc_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_arlock : {1'b0, s_axi_arlock[0]}) : 0 ;\n      assign si_cc_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache : 0 ;\n      assign si_cc_arprot    = (C_AXI_SUPPORTS_READ ) ? s_axi_arprot : 0 ;\n      assign si_cc_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos : 0 ;\n      assign si_cc_arregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion : 0 ;\n      assign si_cc_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser : 0 ;\n      assign si_cc_arvalid   = (C_AXI_SUPPORTS_READ ) ? s_axi_arvalid : 0 ;\n      assign si_cc_rready    = (C_AXI_SUPPORTS_READ ) ? s_axi_rready : 0 ;                                       \n                                                                                               \n      assign s_axi_awready   = (C_AXI_SUPPORTS_WRITE ) ? si_cc_awready : 0 ;\n      assign s_axi_wready    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_wready : 0 ;\n      assign s_axi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_bid : 0 ;\n      assign s_axi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bresp : 0 ;\n      assign s_axi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_buser : 0 ;\n      assign s_axi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bvalid : 0 ;\n      assign s_axi_arready   = (C_AXI_SUPPORTS_READ ) ? si_cc_arready : 0 ;\n      assign s_axi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rid : 0 ;\n      assign s_axi_rdata     = (C_AXI_SUPPORTS_READ ) ? si_cc_rdata : 0 ;\n      assign s_axi_rresp     = (C_AXI_SUPPORTS_READ ) ? si_cc_rresp : 0 ;\n      assign s_axi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rlast : 0 ;\n      assign s_axi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_ruser : 0 ;\n      assign s_axi_rvalid    = (C_AXI_SUPPORTS_READ ) ? si_cc_rvalid : 0 ;\n\n      assign m_axi_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awid : 0 ;\n      assign m_axi_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awaddr : 0 ;\n      assign m_axi_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_awlen : cc_mi_awlen[3:0]) : 0 ;\n      assign m_axi_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awsize : 0 ;\n      assign m_axi_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awburst : 0 ;\n      assign m_axi_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_awlock : cc_mi_awlock[0]) : 0 ;\n      assign m_axi_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awcache : 0 ;\n      assign m_axi_awprot    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awprot : 0 ;\n      assign m_axi_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_awregion : 0 ;\n      assign m_axi_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awqos : 0 ;\n      assign m_axi_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_awuser : 0 ;\n      assign m_axi_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awvalid : 0 ;\n      assign m_axi_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? cc_mi_wid : 0 ;\n      assign m_axi_wdata     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wdata : 0 ;\n      assign m_axi_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wstrb : 0 ;\n      assign m_axi_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_wlast : 0 ;\n      assign m_axi_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_wuser : 0 ;\n      assign m_axi_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wvalid : 0 ;\n      assign m_axi_bready    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_bready : 0 ;\n      assign m_axi_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arid : 0 ;\n      assign m_axi_araddr    = (C_AXI_SUPPORTS_READ ) ? cc_mi_araddr : 0 ;\n      assign m_axi_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_arlen : cc_mi_arlen[3:0]) : 0 ;\n      assign m_axi_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arsize : 0 ;\n      assign m_axi_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arburst : 0 ;\n      assign m_axi_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_arlock : cc_mi_arlock[0]) : 0 ;\n      assign m_axi_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arcache : 0 ;\n      assign m_axi_arprot    = (C_AXI_SUPPORTS_READ ) ? cc_mi_arprot : 0 ;\n      assign m_axi_arregion  = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_arregion : 0 ;\n      assign m_axi_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arqos : 0 ;\n      assign m_axi_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_aruser : 0 ;\n      assign m_axi_arvalid   = (C_AXI_SUPPORTS_READ ) ? cc_mi_arvalid : 0 ;\n      assign m_axi_rready    = (C_AXI_SUPPORTS_READ ) ? cc_mi_rready : 0 ;\n                                                                                                                                                                                                                                                                                        \n      assign cc_mi_awready   = (C_AXI_SUPPORTS_WRITE ) ? m_axi_awready : 0 ;\n      assign cc_mi_wready    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_wready : 0 ;\n      assign cc_mi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid : 0 ;\n      assign cc_mi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bresp : 0 ;\n      assign cc_mi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser : 0 ;\n      assign cc_mi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bvalid : 0 ;\n      assign cc_mi_arready   = (C_AXI_SUPPORTS_READ ) ? m_axi_arready : 0 ;\n      assign cc_mi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid : 0 ;\n      assign cc_mi_rdata     = (C_AXI_SUPPORTS_READ ) ? m_axi_rdata : 0 ;\n      assign cc_mi_rresp     = (C_AXI_SUPPORTS_READ ) ? m_axi_rresp : 0 ;\n      assign cc_mi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast : 1'b0 ;\n      assign cc_mi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser : 0 ;\n      assign cc_mi_rvalid    = (C_AXI_SUPPORTS_READ ) ? m_axi_rvalid : 0 ;\n      \n      if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL!=P_AXILITE)) begin : gen_async_conv\n        \n        fifo_generator_v13_2_5 #(\n          .C_EN_SAFETY_CKT(0),\n          .C_SELECT_XPM(0),\n          .C_INTERFACE_TYPE(2),\n          .C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ? 3 : 2),\n          .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n          .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n          .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n          .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n          .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n          .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),\n          .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n          .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n          .C_HAS_AXI_ID((C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0),\n          .C_AXI_LEN_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 8 : 4),\n          .C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 1 : 2),\n          .C_HAS_AXI_ARUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_AWUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_BUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_RUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_WUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_DIN_WIDTH_RACH(C_FIFO_AR_WIDTH),\n          .C_DIN_WIDTH_RDCH(C_FIFO_R_WIDTH),\n          .C_DIN_WIDTH_WACH(C_FIFO_AW_WIDTH),\n          .C_DIN_WIDTH_WDCH(C_FIFO_W_WIDTH),\n          .C_DIN_WIDTH_WRCH(C_FIFO_B_WIDTH),\n          .C_HAS_AXI_RD_CHANNEL(C_AXI_SUPPORTS_READ),\n          .C_HAS_AXI_WR_CHANNEL(C_AXI_SUPPORTS_WRITE),\n          .C_RACH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_RDCH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_WACH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WDCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WRCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),\n          .C_COMMON_CLOCK(0),\n          .C_COUNT_TYPE(0),\n          .C_DATA_COUNT_WIDTH(10),\n          .C_DEFAULT_VALUE(\"BlankString\"),\n          .C_DIN_WIDTH(18),\n          .C_DOUT_RST_VAL(\"0\"),\n          .C_DOUT_WIDTH(18),\n          .C_ENABLE_RLOCS(0),\n          .C_FAMILY(C_FAMILY),\n          .C_FULL_FLAGS_RST_VAL(1),\n          .C_HAS_ALMOST_EMPTY(0),\n          .C_HAS_ALMOST_FULL(0),\n          .C_HAS_BACKUP(0),\n          .C_HAS_DATA_COUNT(0),\n          .C_HAS_INT_CLK(0),\n          .C_HAS_MEMINIT_FILE(0),\n          .C_HAS_OVERFLOW(0),\n          .C_HAS_RD_DATA_COUNT(0),\n          .C_HAS_RD_RST(0),\n          .C_HAS_RST(1),\n          .C_HAS_SRST(0),\n          .C_HAS_UNDERFLOW(0),\n          .C_HAS_VALID(0),\n          .C_HAS_WR_ACK(0),\n          .C_HAS_WR_DATA_COUNT(0),\n          .C_HAS_WR_RST(0),\n          .C_IMPLEMENTATION_TYPE(0),\n          .C_INIT_WR_PNTR_VAL(0),\n          .C_MEMORY_TYPE(1),\n          .C_MIF_FILE_NAME(\"BlankString\"),\n          .C_OPTIMIZATION_MODE(0),\n          .C_OVERFLOW_LOW(0),\n          .C_PRELOAD_LATENCY(1),\n          .C_PRELOAD_REGS(0),\n          .C_PRIM_FIFO_TYPE(\"4kx4\"),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),\n          .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),\n          .C_PROG_EMPTY_TYPE(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL(1022),\n          .C_PROG_FULL_THRESH_NEGATE_VAL(1021),\n          .C_PROG_FULL_TYPE(0),\n          .C_RD_DATA_COUNT_WIDTH(10),\n          .C_RD_DEPTH(1024),\n          .C_RD_FREQ(1),\n          .C_RD_PNTR_WIDTH(10),\n          .C_UNDERFLOW_LOW(0),\n          .C_USE_DOUT_RST(1),\n          .C_USE_ECC(0),\n          .C_USE_EMBEDDED_REG(0),\n          .C_USE_FIFO16_FLAGS(0),\n          .C_USE_FWFT_DATA_COUNT(0),\n          .C_VALID_LOW(0),\n          .C_WR_ACK_LOW(0),\n          .C_WR_DATA_COUNT_WIDTH(10),\n          .C_WR_DEPTH(1024),\n          .C_WR_FREQ(1),\n          .C_WR_PNTR_WIDTH(10),\n          .C_WR_RESPONSE_LATENCY(1),\n          .C_MSGON_VAL(1),\n          .C_ENABLE_RST_SYNC(1),\n          .C_ERROR_INJECTION_TYPE(0),\n          .C_HAS_SLAVE_CE(0),\n          .C_HAS_MASTER_CE(0),\n          .C_ADD_NGC_CONSTRAINT(0),\n          .C_USE_COMMON_OVERFLOW(0),\n          .C_USE_COMMON_UNDERFLOW(0),\n          .C_USE_DEFAULT_SETTINGS(0),\n          .C_HAS_AXIS_TDATA(1),\n          .C_HAS_AXIS_TID(0),\n          .C_HAS_AXIS_TDEST(0),\n          .C_HAS_AXIS_TUSER(1),\n          .C_HAS_AXIS_TREADY(1),\n          .C_HAS_AXIS_TLAST(0),\n          .C_HAS_AXIS_TSTRB(0),\n          .C_HAS_AXIS_TKEEP(0),\n          .C_AXIS_TDATA_WIDTH(8),\n          .C_AXIS_TID_WIDTH(1),\n          .C_AXIS_TDEST_WIDTH(1),\n          .C_AXIS_TUSER_WIDTH(4),\n          .C_AXIS_TSTRB_WIDTH(1),\n          .C_AXIS_TKEEP_WIDTH(1),\n          .C_AXIS_TYPE(0),\n          .C_IMPLEMENTATION_TYPE_WACH(12),\n          .C_IMPLEMENTATION_TYPE_WDCH(12),\n          .C_IMPLEMENTATION_TYPE_WRCH(12),\n          .C_IMPLEMENTATION_TYPE_RACH(12),\n          .C_IMPLEMENTATION_TYPE_RDCH(12),\n          .C_IMPLEMENTATION_TYPE_AXIS(11),\n          .C_APPLICATION_TYPE_WACH(0),\n          .C_APPLICATION_TYPE_WDCH(0),\n          .C_APPLICATION_TYPE_WRCH(0),\n          .C_APPLICATION_TYPE_RACH(0),\n          .C_APPLICATION_TYPE_RDCH(0),\n          .C_APPLICATION_TYPE_AXIS(0),\n          .C_USE_ECC_WACH(0),\n          .C_USE_ECC_WDCH(0),\n          .C_USE_ECC_WRCH(0),\n          .C_USE_ECC_RACH(0),\n          .C_USE_ECC_RDCH(0),\n          .C_USE_ECC_AXIS(0),\n          .C_ERROR_INJECTION_TYPE_WACH(0),\n          .C_ERROR_INJECTION_TYPE_WDCH(0),\n          .C_ERROR_INJECTION_TYPE_WRCH(0),\n          .C_ERROR_INJECTION_TYPE_RACH(0),\n          .C_ERROR_INJECTION_TYPE_RDCH(0),\n          .C_ERROR_INJECTION_TYPE_AXIS(0),\n          .C_DIN_WIDTH_AXIS(1),\n          .C_WR_DEPTH_WACH(16),\n          .C_WR_DEPTH_WDCH(16),\n          .C_WR_DEPTH_WRCH(16),\n          .C_WR_DEPTH_RACH(16),\n          .C_WR_DEPTH_RDCH(16),\n          .C_WR_DEPTH_AXIS(1024),\n          .C_WR_PNTR_WIDTH_WACH(4),\n          .C_WR_PNTR_WIDTH_WDCH(4),\n          .C_WR_PNTR_WIDTH_WRCH(4),\n          .C_WR_PNTR_WIDTH_RACH(4),\n          .C_WR_PNTR_WIDTH_RDCH(4),\n          .C_WR_PNTR_WIDTH_AXIS(10),\n          .C_HAS_DATA_COUNTS_WACH(0),\n          .C_HAS_DATA_COUNTS_WDCH(0),\n          .C_HAS_DATA_COUNTS_WRCH(0),\n          .C_HAS_DATA_COUNTS_RACH(0),\n          .C_HAS_DATA_COUNTS_RDCH(0),\n          .C_HAS_DATA_COUNTS_AXIS(0),\n          .C_HAS_PROG_FLAGS_WACH(0),\n          .C_HAS_PROG_FLAGS_WDCH(0),\n          .C_HAS_PROG_FLAGS_WRCH(0),\n          .C_HAS_PROG_FLAGS_RACH(0),\n          .C_HAS_PROG_FLAGS_RDCH(0),\n          .C_HAS_PROG_FLAGS_AXIS(0),\n          .C_PROG_FULL_TYPE_WACH(0),\n          .C_PROG_FULL_TYPE_WDCH(0),\n          .C_PROG_FULL_TYPE_WRCH(0),\n          .C_PROG_FULL_TYPE_RACH(0),\n          .C_PROG_FULL_TYPE_RDCH(0),\n          .C_PROG_FULL_TYPE_AXIS(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),\n          .C_PROG_EMPTY_TYPE_WACH(0),\n          .C_PROG_EMPTY_TYPE_WDCH(0),\n          .C_PROG_EMPTY_TYPE_WRCH(0),\n          .C_PROG_EMPTY_TYPE_RACH(0),\n          .C_PROG_EMPTY_TYPE_RDCH(0),\n          .C_PROG_EMPTY_TYPE_AXIS(0),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1021),\n          .C_REG_SLICE_MODE_WACH(0),\n          .C_REG_SLICE_MODE_WDCH(0),\n          .C_REG_SLICE_MODE_WRCH(0),\n          .C_REG_SLICE_MODE_RACH(0),\n          .C_REG_SLICE_MODE_RDCH(0),\n          .C_REG_SLICE_MODE_AXIS(0)\n          )\n          asyncfifo_axi (\n            .s_aclk(s_axi_aclk),\n            .m_aclk(m_axi_aclk),\n            .s_aresetn(async_conv_reset_n),\n            .s_axi_awid           (si_cc_awid),\n            .s_axi_awaddr         (si_cc_awaddr),\n            .s_axi_awlen          (si_cc_awlen),\n            .s_axi_awsize         (si_cc_awsize),\n            .s_axi_awburst        (si_cc_awburst),\n            .s_axi_awlock         (si_cc_awlock),\n            .s_axi_awcache        (si_cc_awcache),\n            .s_axi_awprot         (si_cc_awprot),\n            .s_axi_awqos          (si_cc_awqos),\n            .s_axi_awregion       (si_cc_awregion),\n            .s_axi_awuser         (si_cc_awuser),\n            .s_axi_awvalid        (si_cc_awvalid),\n            .s_axi_awready        (si_cc_awready),\n            .s_axi_wid            (si_cc_wid),\n            .s_axi_wdata          (si_cc_wdata),\n            .s_axi_wstrb          (si_cc_wstrb),\n            .s_axi_wlast          (si_cc_wlast),\n            .s_axi_wuser          (si_cc_wuser),\n            .s_axi_wvalid         (si_cc_wvalid),\n            .s_axi_wready         (si_cc_wready),\n            .s_axi_bid            (si_cc_bid),\n            .s_axi_bresp          (si_cc_bresp),\n            .s_axi_buser          (si_cc_buser),\n            .s_axi_bvalid         (si_cc_bvalid),\n            .s_axi_bready         (si_cc_bready),\n            .m_axi_awid           (cc_mi_awid),\n            .m_axi_awaddr         (cc_mi_awaddr),\n            .m_axi_awlen          (cc_mi_awlen),\n            .m_axi_awsize         (cc_mi_awsize),\n            .m_axi_awburst        (cc_mi_awburst),\n            .m_axi_awlock         (cc_mi_awlock),\n            .m_axi_awcache        (cc_mi_awcache),\n            .m_axi_awprot         (cc_mi_awprot),\n            .m_axi_awqos          (cc_mi_awqos),\n            .m_axi_awregion       (cc_mi_awregion),\n            .m_axi_awuser         (cc_mi_awuser),\n            .m_axi_awvalid        (cc_mi_awvalid),\n            .m_axi_awready        (cc_mi_awready),\n            .m_axi_wid            (cc_mi_wid),\n            .m_axi_wdata          (cc_mi_wdata),\n            .m_axi_wstrb          (cc_mi_wstrb),\n            .m_axi_wlast          (cc_mi_wlast),\n            .m_axi_wuser          (cc_mi_wuser),\n            .m_axi_wvalid         (cc_mi_wvalid),\n            .m_axi_wready         (cc_mi_wready),\n            .m_axi_bid            (cc_mi_bid),\n            .m_axi_bresp          (cc_mi_bresp),\n            .m_axi_buser          (cc_mi_buser),\n            .m_axi_bvalid         (cc_mi_bvalid),\n            .m_axi_bready         (cc_mi_bready),\n            .s_axi_arid           (si_cc_arid),\n            .s_axi_araddr         (si_cc_araddr),\n            .s_axi_arlen          (si_cc_arlen),\n            .s_axi_arsize         (si_cc_arsize),\n            .s_axi_arburst        (si_cc_arburst),\n            .s_axi_arlock         (si_cc_arlock),\n            .s_axi_arcache        (si_cc_arcache),\n            .s_axi_arprot         (si_cc_arprot),\n            .s_axi_arqos          (si_cc_arqos),\n            .s_axi_arregion       (si_cc_arregion),\n            .s_axi_aruser         (si_cc_aruser),\n            .s_axi_arvalid        (si_cc_arvalid),\n            .s_axi_arready        (si_cc_arready),\n            .s_axi_rid            (si_cc_rid),\n            .s_axi_rdata          (si_cc_rdata),\n            .s_axi_rresp          (si_cc_rresp),\n            .s_axi_rlast          (si_cc_rlast),\n            .s_axi_ruser          (si_cc_ruser),\n            .s_axi_rvalid         (si_cc_rvalid),\n            .s_axi_rready         (si_cc_rready),\n            .m_axi_arid           (cc_mi_arid),\n            .m_axi_araddr         (cc_mi_araddr),\n            .m_axi_arlen          (cc_mi_arlen),\n            .m_axi_arsize         (cc_mi_arsize),\n            .m_axi_arburst        (cc_mi_arburst),\n            .m_axi_arlock         (cc_mi_arlock),\n            .m_axi_arcache        (cc_mi_arcache),\n            .m_axi_arprot         (cc_mi_arprot),\n            .m_axi_arqos          (cc_mi_arqos),\n            .m_axi_arregion       (cc_mi_arregion),\n            .m_axi_aruser         (cc_mi_aruser),\n            .m_axi_arvalid        (cc_mi_arvalid),\n            .m_axi_arready        (cc_mi_arready),\n            .m_axi_rid            (cc_mi_rid),\n            .m_axi_rdata          (cc_mi_rdata),\n            .m_axi_rresp          (cc_mi_rresp),\n            .m_axi_rlast          (cc_mi_rlast),\n            .m_axi_ruser          (cc_mi_ruser),\n            .m_axi_rvalid         (cc_mi_rvalid),\n            .m_axi_rready         (cc_mi_rready),\n            .m_aclk_en(1'b1),\n            .s_aclk_en(1'b1),\n            .almost_empty(),\n            .almost_full(),\n            .axis_data_count(),\n            .axis_dbiterr(),\n            .axis_injectdbiterr(1'b0),\n            .axis_injectsbiterr(1'b0),\n            .axis_overflow(),\n            .axis_prog_empty(),\n            .axis_prog_empty_thresh(10'b0),\n            .axis_prog_full(),\n            .axis_prog_full_thresh(10'b0),\n            .axis_rd_data_count(),\n            .axis_sbiterr(),\n            .axis_underflow(),\n            .axis_wr_data_count(),\n            .axi_ar_data_count(),\n            .axi_ar_dbiterr(),\n            .axi_ar_injectdbiterr(1'b0),\n            .axi_ar_injectsbiterr(1'b0),\n            .axi_ar_overflow(),\n            .axi_ar_prog_empty(),\n            .axi_ar_prog_empty_thresh(4'b0),\n            .axi_ar_prog_full(),\n            .axi_ar_prog_full_thresh(4'b0),\n            .axi_ar_rd_data_count(),\n            .axi_ar_sbiterr(),\n            .axi_ar_underflow(),\n            .axi_ar_wr_data_count(),\n            .axi_aw_data_count(),\n            .axi_aw_dbiterr(),\n            .axi_aw_injectdbiterr(1'b0),\n            .axi_aw_injectsbiterr(1'b0),\n            .axi_aw_overflow(),\n            .axi_aw_prog_empty(),\n            .axi_aw_prog_empty_thresh(4'b0),\n            .axi_aw_prog_full(),\n            .axi_aw_prog_full_thresh(4'b0),\n            .axi_aw_rd_data_count(),\n            .axi_aw_sbiterr(),\n            .axi_aw_underflow(),\n            .axi_aw_wr_data_count(),\n            .axi_b_data_count(),\n            .axi_b_dbiterr(),\n            .axi_b_injectdbiterr(1'b0),\n            .axi_b_injectsbiterr(1'b0),\n            .axi_b_overflow(),\n            .axi_b_prog_empty(),\n            .axi_b_prog_empty_thresh(4'b0),\n            .axi_b_prog_full(),\n            .axi_b_prog_full_thresh(4'b0),\n            .axi_b_rd_data_count(),\n            .axi_b_sbiterr(),\n            .axi_b_underflow(),\n            .axi_b_wr_data_count(),\n            .axi_r_data_count(),\n            .axi_r_dbiterr(),\n            .axi_r_injectdbiterr(1'b0),\n            .axi_r_injectsbiterr(1'b0),\n            .axi_r_overflow(),\n            .axi_r_prog_empty(),\n            .axi_r_prog_empty_thresh(4'b0),\n            .axi_r_prog_full(),\n            .axi_r_prog_full_thresh(4'b0),\n            .axi_r_rd_data_count(),\n            .axi_r_sbiterr(),\n            .axi_r_underflow(),\n            .axi_r_wr_data_count(),\n            .axi_w_data_count(),\n            .axi_w_dbiterr(),\n            .axi_w_injectdbiterr(1'b0),\n            .axi_w_injectsbiterr(1'b0),\n            .axi_w_overflow(),\n            .axi_w_prog_empty(),\n            .axi_w_prog_empty_thresh(4'b0),\n            .axi_w_prog_full(),\n            .axi_w_prog_full_thresh(4'b0),\n            .axi_w_rd_data_count(),\n            .axi_w_sbiterr(),\n            .axi_w_underflow(),\n            .axi_w_wr_data_count(),\n            .backup(1'b0),\n            .backup_marker(1'b0),\n            .clk(1'b0),\n            .data_count(),\n            .dbiterr(),\n            .din(18'b0),\n            .dout(),\n            .empty(),\n            .full(),\n            .injectdbiterr(1'b0),\n            .injectsbiterr(1'b0),\n            .int_clk(1'b0),\n            .m_axis_tdata(),\n            .m_axis_tdest(),\n            .m_axis_tid(),\n            .m_axis_tkeep(),\n            .m_axis_tlast(),\n            .m_axis_tready(1'b0),\n            .m_axis_tstrb(),\n            .m_axis_tuser(),\n            .m_axis_tvalid(),\n            .overflow(),\n            .prog_empty(),\n            .prog_empty_thresh(10'b0),\n            .prog_empty_thresh_assert(10'b0),\n            .prog_empty_thresh_negate(10'b0),\n            .prog_full(),\n            .prog_full_thresh(10'b0),\n            .prog_full_thresh_assert(10'b0),\n            .prog_full_thresh_negate(10'b0),\n            .rd_clk(1'b0),\n            .rd_data_count(),\n            .rd_en(1'b0),\n            .rd_rst(1'b0),\n            .rst(1'b0),\n            .sbiterr(),\n            .srst(1'b0),\n            .s_axis_tdata(8'b0),\n            .s_axis_tdest(1'b0),\n            .s_axis_tid(1'b0),\n            .s_axis_tkeep(1'b0),\n            .s_axis_tlast(1'b0),\n            .s_axis_tready(),\n            .s_axis_tstrb(1'b0),\n            .s_axis_tuser(4'b0),\n            .s_axis_tvalid(1'b0),\n            .underflow(),\n            .valid(),\n            .wr_ack(),\n            .wr_clk(1'b0),\n            .wr_data_count(),\n            .wr_en(1'b0),\n            .wr_rst(1'b0),\n            .wr_rst_busy(),\n            .rd_rst_busy(),\n            .sleep(1'b0)\n        );\n      end else if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_async_lite_conv\n        localparam C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n        `include \"axi_infrastructure_v1_1_0.vh\"\n\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n        axi_infrastructure_v1_1_0_axi2vector #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        axi2vec ( \n          .s_axi_awid      ( si_cc_awid      ) ,\n          .s_axi_awaddr    ( si_cc_awaddr    ) ,\n          .s_axi_awlen     ( s_axi_awlen     ) ,\n          .s_axi_awsize    ( si_cc_awsize    ) ,\n          .s_axi_awburst   ( si_cc_awburst   ) ,\n          .s_axi_awlock    ( s_axi_awlock    ) ,\n          .s_axi_awcache   ( si_cc_awcache   ) ,\n          .s_axi_awprot    ( si_cc_awprot    ) ,\n          .s_axi_awqos     ( si_cc_awqos     ) ,\n          .s_axi_awuser    ( si_cc_awuser    ) ,\n          .s_axi_awregion  ( si_cc_awregion  ) ,\n          .s_axi_wid       ( si_cc_wid       ) ,\n          .s_axi_wdata     ( si_cc_wdata     ) ,\n          .s_axi_wstrb     ( si_cc_wstrb     ) ,\n          .s_axi_wlast     ( si_cc_wlast     ) ,\n          .s_axi_wuser     ( si_cc_wuser     ) ,\n          .s_axi_bid       ( si_cc_bid       ) ,\n          .s_axi_bresp     ( si_cc_bresp     ) ,\n          .s_axi_buser     ( si_cc_buser     ) ,\n          .s_axi_arid      ( si_cc_arid      ) ,\n          .s_axi_araddr    ( si_cc_araddr    ) ,\n          .s_axi_arlen     ( s_axi_arlen     ) ,\n          .s_axi_arsize    ( si_cc_arsize    ) ,\n          .s_axi_arburst   ( si_cc_arburst   ) ,\n          .s_axi_arlock    ( s_axi_arlock    ) ,\n          .s_axi_arcache   ( si_cc_arcache   ) ,\n          .s_axi_arprot    ( si_cc_arprot    ) ,\n          .s_axi_arqos     ( si_cc_arqos     ) ,\n          .s_axi_aruser    ( si_cc_aruser    ) ,\n          .s_axi_arregion  ( si_cc_arregion  ) ,\n          .s_axi_rid       ( si_cc_rid       ) ,\n          .s_axi_rdata     ( si_cc_rdata     ) ,\n          .s_axi_rresp     ( si_cc_rresp     ) ,\n          .s_axi_rlast     ( si_cc_rlast     ) ,\n          .s_axi_ruser     ( si_cc_ruser     ) ,\n          .s_awpayload     ( s_awpayload ) ,\n          .s_wpayload      ( s_wpayload  ) ,\n          .s_bpayload      ( s_bpayload  ) ,\n          .s_arpayload     ( s_arpayload ) ,\n          .s_rpayload      ( s_rpayload  ) \n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_AWPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_aw (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_awvalid),\n          .s_ready  (si_cc_awready),\n          .s_payld  (s_awpayload),\n          .m_valid  (cc_mi_awvalid),\n          .m_ready  (cc_mi_awready),\n          .m_payld  (m_awpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_ARPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_ar (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_arvalid),\n          .s_ready  (si_cc_arready),\n          .s_payld  (s_arpayload),\n          .m_valid  (cc_mi_arvalid),\n          .m_ready  (cc_mi_arready),\n          .m_payld  (m_arpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_WPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_w (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_wvalid),\n          .s_ready  (si_cc_wready),\n          .s_payld  (s_wpayload),\n          .m_valid  (cc_mi_wvalid),\n          .m_ready  (cc_mi_wready),\n          .m_payld  (m_wpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_BPAYLOAD_WIDTH)\n        ) clock_conv_lite_resp_b (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_bvalid),\n          .s_ready  (cc_mi_bready),\n          .s_payld  (m_bpayload),\n          .m_valid  (si_cc_bvalid),\n          .m_ready  (si_cc_bready),\n          .m_payld  (s_bpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_RPAYLOAD_WIDTH)\n        ) clock_conv_lite_resp_r (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_rvalid),\n          .s_ready  (cc_mi_rready),\n          .s_payld  (m_rpayload),\n          .m_valid  (si_cc_rvalid),\n          .m_ready  (si_cc_rready),\n          .m_payld  (s_rpayload)\n        );\n\n        axi_infrastructure_v1_1_0_vector2axi #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        vec2axi ( \n          .m_awpayload    ( m_awpayload    ) ,\n          .m_wpayload     ( m_wpayload     ) ,\n          .m_bpayload     ( m_bpayload     ) ,\n          .m_arpayload    ( m_arpayload    ) ,\n          .m_rpayload     ( m_rpayload     ) ,\n          .m_axi_awid     ( cc_mi_awid     ) ,\n          .m_axi_awaddr   ( cc_mi_awaddr   ) ,\n          .m_axi_awlen    ( cc_mi_awlen    ) ,\n          .m_axi_awsize   ( cc_mi_awsize   ) ,\n          .m_axi_awburst  ( cc_mi_awburst  ) ,\n          .m_axi_awlock   ( cc_mi_awlock   ) ,\n          .m_axi_awcache  ( cc_mi_awcache  ) ,\n          .m_axi_awprot   ( cc_mi_awprot   ) ,\n          .m_axi_awqos    ( cc_mi_awqos    ) ,\n          .m_axi_awuser   ( cc_mi_awuser   ) ,\n          .m_axi_awregion ( cc_mi_awregion ) ,\n          .m_axi_wid      ( cc_mi_wid      ) ,\n          .m_axi_wdata    ( cc_mi_wdata    ) ,\n          .m_axi_wstrb    ( cc_mi_wstrb    ) ,\n          .m_axi_wlast    ( cc_mi_wlast    ) ,\n          .m_axi_wuser    ( cc_mi_wuser    ) ,\n          .m_axi_bid      ( cc_mi_bid      ) ,\n          .m_axi_bresp    ( cc_mi_bresp    ) ,\n          .m_axi_buser    ( cc_mi_buser    ) ,\n          .m_axi_arid     ( cc_mi_arid     ) ,\n          .m_axi_araddr   ( cc_mi_araddr   ) ,\n          .m_axi_arlen    ( cc_mi_arlen    ) ,\n          .m_axi_arsize   ( cc_mi_arsize   ) ,\n          .m_axi_arburst  ( cc_mi_arburst  ) ,\n          .m_axi_arlock   ( cc_mi_arlock   ) ,\n          .m_axi_arcache  ( cc_mi_arcache  ) ,\n          .m_axi_arprot   ( cc_mi_arprot   ) ,\n          .m_axi_arqos    ( cc_mi_arqos    ) ,\n          .m_axi_aruser   ( cc_mi_aruser   ) ,\n          .m_axi_arregion ( cc_mi_arregion ) ,\n          .m_axi_rid      ( cc_mi_rid      ) ,\n          .m_axi_rdata    ( cc_mi_rdata    ) ,\n          .m_axi_rresp    ( cc_mi_rresp    ) ,\n          .m_axi_rlast    ( cc_mi_rlast    ) ,\n          .m_axi_ruser    ( cc_mi_ruser    ) \n        );\n\n      end else begin : gen_sync_conv\n        \n        assign {fast_aclk, slow_aclk} = P_SI_LT_MI ? {m_axi_aclk, s_axi_aclk} : {s_axi_aclk, m_axi_aclk};\n    \n        // Sample cycle used to determine when to assert a signal on a fast clock\n        // to be flopped onto a slow clock.\n        axi_clock_converter_v2_1_21_axic_sample_cycle_ratio #(\n          .C_RATIO ( P_ACLK_RATIO )\n        )\n        axic_sample_cycle_inst (\n          .SLOW_ACLK          ( slow_aclk               ) ,\n          .FAST_ACLK          ( fast_aclk               ) ,\n          .SAMPLE_CYCLE_EARLY ( sample_cycle_early ) ,\n          .SAMPLE_CYCLE       ( sample_cycle       )\n        );\n    \n      ////////////////////////////////////////////////////////////////////////////////\n      // AXI write channels\n      ////////////////////////////////////////////////////////////////////////////////\n        if (C_AXI_SUPPORTS_WRITE) begin : gen_conv_write_ch\n    \n          // Write Address Port\n          assign s_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH]     = si_cc_awaddr   ;\n          assign s_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH]     = si_cc_awprot   ;\n          assign cc_mi_awaddr   = m_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH];\n          assign cc_mi_awprot   = m_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_aw_axi4\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen    ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock[0] ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH] = si_cc_awregion ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awregion = m_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_aw_axi3\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen[3:0] ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock   ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_aw_user\n            assign s_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH]  = si_cc_awuser;\n            assign cc_mi_awuser = m_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AW_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          aw_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_aw_mesg ) ,\n            .S_VALID   ( si_cc_awvalid   ) ,\n            .S_READY   ( si_cc_awready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_aw_mesg ) ,\n            .M_VALID   ( cc_mi_awvalid   ) ,\n            .M_READY   ( cc_mi_awready   )\n          );\n    \n          // Write Data Port\n          assign s_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH] = si_cc_wdata; \n          assign s_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH] = si_cc_wstrb; \n          assign cc_mi_wdata    = m_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH];\n          assign cc_mi_wstrb    = m_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_w_axi4\n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_w_axi3\n            assign s_w_mesg[C_WID_RIGHT+:C_WID_WIDTH]     = si_cc_wid; \n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wid      = m_w_mesg[C_WID_RIGHT+:C_WID_WIDTH];\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_w_user\n            assign s_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH]  = si_cc_wuser;\n            assign cc_mi_wuser = m_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH  ( C_W_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE           ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          w_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_w_mesg ) ,\n            .S_VALID   ( si_cc_wvalid   ) ,\n            .S_READY   ( si_cc_wready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_w_mesg ) ,\n            .M_VALID   ( cc_mi_wvalid   ) ,\n            .M_READY   ( cc_mi_wready   )\n          );\n    \n          // Write Response Port\n          assign m_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH] = cc_mi_bresp;\n          assign si_cc_bresp    = s_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_b_axi\n            assign m_b_mesg[C_BID_RIGHT+:C_BID_WIDTH]     = cc_mi_bid;\n            assign si_cc_bid      = s_b_mesg[C_BID_RIGHT+:C_BID_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_b_user\n            assign m_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH] = cc_mi_buser;\n            assign si_cc_buser  = s_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_B_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          b_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_b_mesg ) ,\n            .S_VALID   ( cc_mi_bvalid   ) ,\n            .S_READY   ( cc_mi_bready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_b_mesg ) ,\n            .M_VALID   ( si_cc_bvalid   ) ,\n            .M_READY   ( si_cc_bready   )\n          );\n    \n        end else begin : gen_tieoff_write_ch\n    \n          // Write address port\n          assign cc_mi_awid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_awaddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_awlen    = {8{1'b0}};\n          assign cc_mi_awsize   = {3{1'b0}};\n          assign cc_mi_awburst  = {2{1'b0}};\n          assign cc_mi_awlock   = {2{1'b0}};\n          assign cc_mi_awcache  = {4{1'b0}};\n          assign cc_mi_awprot   = {3{1'b0}};\n          assign cc_mi_awregion = {4{1'b0}};\n          assign cc_mi_awqos    = {4{1'b0}};\n          assign cc_mi_awuser   = {C_AXI_AWUSER_WIDTH{1'b0}};\n          assign cc_mi_awvalid  = 1'b0;\n          assign si_cc_awready  = 1'b0;\n    \n          // Write data port\n          assign cc_mi_wid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_wdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign cc_mi_wstrb    = {C_AXI_DATA_WIDTH/8{1'b0}};\n          assign cc_mi_wlast    = 1'b0;\n          assign cc_mi_wuser    = {C_AXI_WUSER_WIDTH{1'b0}};\n          assign cc_mi_wvalid   = 1'b0;\n          assign si_cc_wready   = 1'b0;\n    \n          // Write response port\n          assign si_cc_bid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_bresp    = {2{1'b0}};\n          assign si_cc_buser    = {C_AXI_BUSER_WIDTH{1'b0}};\n          assign si_cc_bvalid   = 1'b0;\n          assign cc_mi_bready   = 1'b0;\n        end\n    \n        ////////////////////////////////////////////////////////////////////////////////\n        // AXI read channels\n        ////////////////////////////////////////////////////////////////////////////////\n    \n        if (C_AXI_SUPPORTS_READ) begin : gen_conv_read_ch\n    \n          // Read Address Port\n          assign s_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH]     = si_cc_araddr   ;\n          assign s_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH]     = si_cc_arprot   ;\n          assign cc_mi_araddr   = m_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH];\n          assign cc_mi_arprot   = m_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_ar_axi4\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen    ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock[0] ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH] = si_cc_arregion ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arregion = m_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_ar_axi3\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen[3:0] ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock   ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_ar_user\n            assign s_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH]  = si_cc_aruser;\n            assign cc_mi_aruser = m_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AR_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          ar_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_ar_mesg ) ,\n            .S_VALID   ( si_cc_arvalid   ) ,\n            .S_READY   ( si_cc_arready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN  ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_ar_mesg ) ,\n            .M_VALID   ( cc_mi_arvalid   ) ,\n            .M_READY   ( cc_mi_arready   )\n          );\n    \n          // Read Data Port\n          assign m_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH] = cc_mi_rdata; \n          assign m_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH] = cc_mi_rresp; \n          assign si_cc_rdata    = s_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH];\n          assign si_cc_rresp    = s_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_r_axi\n            assign m_r_mesg[C_RID_RIGHT+:C_RID_WIDTH]     = cc_mi_rid;   \n            assign m_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH] = cc_mi_rlast;\n            assign si_cc_rid      = s_r_mesg[C_RID_RIGHT+:C_RID_WIDTH];\n            assign si_cc_rlast    = s_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_r_user\n            assign m_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH] = cc_mi_ruser;\n            assign si_cc_ruser  = s_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_R_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          r_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_r_mesg ) ,\n            .S_VALID   ( cc_mi_rvalid   ) ,\n            .S_READY   ( cc_mi_rready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_r_mesg ) ,\n            .M_VALID   ( si_cc_rvalid   ) ,\n            .M_READY   ( si_cc_rready   )\n          );\n    \n        end else begin : gen_tieoff_read_ch\n    \n          // Read Address Port\n          assign cc_mi_arid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_araddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_arlen    = {8{1'b0}};\n          assign cc_mi_arsize   = {3{1'b0}};\n          assign cc_mi_arburst  = {2{1'b0}};\n          assign cc_mi_arlock   = {2{1'b0}};\n          assign cc_mi_arcache  = {4{1'b0}};\n          assign cc_mi_arprot   = {3{1'b0}};\n          assign cc_mi_arregion = {4{1'b0}};\n          assign cc_mi_arqos    = {4{1'b0}};\n          assign cc_mi_aruser   = {C_AXI_ARUSER_WIDTH{1'b0}};\n          assign cc_mi_arvalid  = 1'b0;\n          assign si_cc_arready  = 1'b0;\n    \n          // Read data port\n          assign si_cc_rid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_rdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign si_cc_rresp    = {2{1'b0}};\n          assign si_cc_rlast    = 1'b0;\n          assign si_cc_ruser    = {C_AXI_RUSER_WIDTH{1'b0}};\n          assign si_cc_rvalid   = 1'b0;\n          assign cc_mi_rready   = 1'b0;\n        end\n      end\n    end\n\n  endgenerate\n\nendmodule\n\n\n\n", "num_lines": 2178}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1\n// IP Revision: 21\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_clock_converter_512 (\n  s_axi_aclk,\n  s_axi_aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awuser,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_aruser,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_aclk,\n  m_axi_aresetn,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awuser,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_aruser,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_CLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 SI_CLK CLK\" *)\ninput wire s_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 SI_RST RST\" *)\ninput wire s_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWUSER\" *)\ninput wire [7 : 0] s_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARUSER\" *)\ninput wire [7 : 0] s_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 8, ARUSER_WIDTH 8, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_CLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 MI_CLK CLK\" *)\ninput wire m_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 MI_RST RST\" *)\ninput wire m_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWUSER\" *)\noutput wire [7 : 0] m_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARUSER\" *)\noutput wire [7 : 0] m_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 8, ARUSER_WIDTH 8, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_clock_converter_v2_1_21_axi_clock_converter #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_S_AXI_ACLK_RATIO(1),\n    .C_M_AXI_ACLK_RATIO(2),\n    .C_AXI_IS_ACLK_ASYNC(1),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_SUPPORTS_USER_SIGNALS(1),\n    .C_AXI_AWUSER_WIDTH(8),\n    .C_AXI_ARUSER_WIDTH(8),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_AXI_SUPPORTS_WRITE(1),\n    .C_AXI_SUPPORTS_READ(1),\n    .C_SYNCHRONIZER_STAGE(2)\n  ) inst (\n    .s_axi_aclk(s_axi_aclk),\n    .s_axi_aresetn(s_axi_aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(s_axi_awuser),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(s_axi_aruser),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_aclk(m_axi_aclk),\n    .m_axi_aresetn(m_axi_aresetn),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(m_axi_awuser),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(m_axi_aruser),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 441}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/*\n *******************************************************************************\n *\n * FIFO Generator - Verilog Behavioral Model\n *\n *******************************************************************************\n *\n * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.\n *\n * This file contains confidential and proprietary information\n * of Xilinx, Inc. and is protected under U.S. and\n * international copyright and other intellectual property\n * laws.\n *\n * DISCLAIMER\n * This disclaimer is not a license and does not grant any\n * rights to the materials distributed herewith. Except as\n * otherwise provided in a valid license issued to you by\n * Xilinx, and to the maximum extent permitted by applicable\n * law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n * (2) Xilinx shall not be liable (whether in contract or tort,\n * including negligence, or under any other theory of\n * liability) for any loss or damage of any kind or nature\n * related to, arising under or in connection with these\n * materials, including for any direct, or any indirect,\n * special, incidental, or consequential loss or damage\n * (including loss of data, profits, goodwill, or any type of\n * loss or damage suffered as a result of any action brought\n * by a third party) even if such damage or loss was\n * reasonably foreseeable or Xilinx had been advised of the\n * possibility of the same.\n *\n * CRITICAL APPLICATIONS\n * Xilinx products are not designed or intended to be fail-\n * safe, or for use in any application requiring fail-safe\n * performance, such as life-support or safety devices or\n * systems, Class III medical devices, nuclear facilities,\n * applications related to the deployment of airbags, or any\n * other applications that could lead to death, personal\n * injury, or severe property or environmental damage\n * (individually and collectively, \"Critical\n * Applications\"). Customer assumes the sole risk and\n * liability of any use of Xilinx products in Critical\n * Applications, subject only to applicable laws and\n * regulations governing limitations on product liability.\n *\n * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n * PART OF THIS FILE AT ALL TIMES.\n *\n *******************************************************************************\n *******************************************************************************\n *\n * Filename: fifo_generator_vlog_beh.v\n *\n * Author     : Xilinx\n *\n *******************************************************************************\n * Structure:\n * \n * fifo_generator_vlog_beh.v\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_as\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_ss\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_preload0\n * \n *******************************************************************************\n * Description:\n *\n * The Verilog behavioral model for the FIFO Generator.\n *\n *   The behavioral model has three parts:\n *      - The behavioral model for independent clocks FIFOs (_as)\n *      - The behavioral model for common clock FIFOs (_ss)\n *      - The \"preload logic\" block which implements First-word Fall-through\n * \n *******************************************************************************\n * Description:\n *  The verilog behavioral model for the FIFO generator core.\n *\n *******************************************************************************\n */\n\n`timescale 1ps/1ps\n`ifndef TCQ\n `define TCQ 100\n`endif\n\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_vlog_beh\n  #(\n    //-----------------------------------------------------------------------\n    // Generic Declarations\n    //-----------------------------------------------------------------------\n    parameter C_COMMON_CLOCK                 = 0,\n    parameter C_COUNT_TYPE                   = 0,\n    parameter C_DATA_COUNT_WIDTH             = 2,\n    parameter C_DEFAULT_VALUE                = \"\",\n    parameter C_DIN_WIDTH                    = 8,\n    parameter C_DOUT_RST_VAL                 = \"\",\n    parameter C_DOUT_WIDTH                   = 8,\n    parameter C_ENABLE_RLOCS                 = 0,\n    parameter C_FAMILY                       = \"\",\n    parameter C_FULL_FLAGS_RST_VAL           = 1,\n    parameter C_HAS_ALMOST_EMPTY             = 0,\n    parameter C_HAS_ALMOST_FULL              = 0,\n    parameter C_HAS_BACKUP                   = 0,\n    parameter C_HAS_DATA_COUNT               = 0,\n    parameter C_HAS_INT_CLK                  = 0,\n    parameter C_HAS_MEMINIT_FILE             = 0,\n    parameter C_HAS_OVERFLOW                 = 0,\n    parameter C_HAS_RD_DATA_COUNT            = 0,\n    parameter C_HAS_RD_RST                   = 0,\n    parameter C_HAS_RST                      = 1,\n    parameter C_HAS_SRST                     = 0,\n    parameter C_HAS_UNDERFLOW                = 0,\n    parameter C_HAS_VALID                    = 0,\n    parameter C_HAS_WR_ACK                   = 0,\n    parameter C_HAS_WR_DATA_COUNT            = 0,\n    parameter C_HAS_WR_RST                   = 0,\n    parameter C_IMPLEMENTATION_TYPE          = 0,\n    parameter C_INIT_WR_PNTR_VAL             = 0,\n    parameter C_MEMORY_TYPE                  = 1,\n    parameter C_MIF_FILE_NAME                = \"\",\n    parameter C_OPTIMIZATION_MODE            = 0,\n    parameter C_OVERFLOW_LOW                 = 0,\n    parameter C_EN_SAFETY_CKT                = 0,\n    parameter C_PRELOAD_LATENCY              = 1,\n    parameter C_PRELOAD_REGS                 = 0,\n    parameter C_PRIM_FIFO_TYPE               = \"4kx4\",\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter C_PROG_EMPTY_TYPE              = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter C_PROG_FULL_TYPE               = 0,\n    parameter C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter C_RD_DEPTH                     = 256,\n    parameter C_RD_FREQ                      = 1,\n    parameter C_RD_PNTR_WIDTH                = 8,\n    parameter C_UNDERFLOW_LOW                = 0,\n    parameter C_USE_DOUT_RST                 = 0,\n    parameter C_USE_ECC                      = 0,\n    parameter C_USE_EMBEDDED_REG             = 0,\n    parameter C_USE_PIPELINE_REG             = 0,\n    parameter C_POWER_SAVING_MODE            = 0,\n    parameter C_USE_FIFO16_FLAGS             = 0,\n    parameter C_USE_FWFT_DATA_COUNT          = 0,\n    parameter C_VALID_LOW                    = 0,\n    parameter C_WR_ACK_LOW                   = 0,\n    parameter C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter C_WR_DEPTH                     = 256,\n    parameter C_WR_FREQ                      = 1,\n    parameter C_WR_PNTR_WIDTH                = 8,\n    parameter C_WR_RESPONSE_LATENCY          = 1,\n    parameter C_MSGON_VAL                    = 1,\n    parameter C_ENABLE_RST_SYNC              = 1,\n    parameter C_ERROR_INJECTION_TYPE         = 0,\n    parameter C_SYNCHRONIZER_STAGE           = 2,\n\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE               = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3\n    parameter C_AXI_TYPE                     = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3\n    parameter C_HAS_AXI_WR_CHANNEL           = 0,\n    parameter C_HAS_AXI_RD_CHANNEL           = 0,\n    parameter C_HAS_SLAVE_CE                 = 0,\n    parameter C_HAS_MASTER_CE                = 0,\n    parameter C_ADD_NGC_CONSTRAINT           = 0,\n    parameter C_USE_COMMON_UNDERFLOW         = 0,\n    parameter C_USE_COMMON_OVERFLOW          = 0,\n    parameter C_USE_DEFAULT_SETTINGS         = 0,\n\n    // AXI Full/Lite\n    parameter C_AXI_ID_WIDTH                 = 0,\n    parameter C_AXI_ADDR_WIDTH               = 0,\n    parameter C_AXI_DATA_WIDTH               = 0,\n    parameter C_AXI_LEN_WIDTH                = 8,\n    parameter C_AXI_LOCK_WIDTH               = 2,\n    parameter C_HAS_AXI_ID                   = 0,\n    parameter C_HAS_AXI_AWUSER               = 0,\n    parameter C_HAS_AXI_WUSER                = 0,\n    parameter C_HAS_AXI_BUSER                = 0,\n    parameter C_HAS_AXI_ARUSER               = 0,\n    parameter C_HAS_AXI_RUSER                = 0,\n    parameter C_AXI_ARUSER_WIDTH             = 0,\n    parameter C_AXI_AWUSER_WIDTH             = 0,\n    parameter C_AXI_WUSER_WIDTH              = 0,\n    parameter C_AXI_BUSER_WIDTH              = 0,\n    parameter C_AXI_RUSER_WIDTH              = 0,\n\n    // AXI Streaming\n    parameter C_HAS_AXIS_TDATA               = 0,\n    parameter C_HAS_AXIS_TID                 = 0,\n    parameter C_HAS_AXIS_TDEST               = 0,\n    parameter C_HAS_AXIS_TUSER               = 0,\n    parameter C_HAS_AXIS_TREADY              = 0,\n    parameter C_HAS_AXIS_TLAST               = 0,\n    parameter C_HAS_AXIS_TSTRB               = 0,\n    parameter C_HAS_AXIS_TKEEP               = 0,\n    parameter C_AXIS_TDATA_WIDTH             = 1,\n    parameter C_AXIS_TID_WIDTH               = 1,\n    parameter C_AXIS_TDEST_WIDTH             = 1,\n    parameter C_AXIS_TUSER_WIDTH             = 1,\n    parameter C_AXIS_TSTRB_WIDTH             = 1,\n    parameter C_AXIS_TKEEP_WIDTH             = 1,\n\n    // AXI Channel Type\n    // WACH --> Write Address Channel\n    // WDCH --> Write Data Channel\n    // WRCH --> Write Response Channel\n    // RACH --> Read Address Channel\n    // RDCH --> Read Data Channel\n    // AXIS --> AXI Streaming\n    parameter C_WACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic\n    parameter C_WDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_WRCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_AXIS_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n\n    // AXI Implementation Type\n    // 1 = Common Clock Block RAM FIFO\n    // 2 = Common Clock Distributed RAM FIFO\n    // 11 = Independent Clock Block RAM FIFO\n    // 12 = Independent Clock Distributed RAM FIFO\n    parameter C_IMPLEMENTATION_TYPE_WACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WRCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_AXIS     = 0,\n\n    // AXI FIFO Type\n    // 0 = Data FIFO\n    // 1 = Packet FIFO\n    // 2 = Low Latency Sync FIFO\n    // 3 = Low Latency Async FIFO\n    parameter C_APPLICATION_TYPE_WACH        = 0,\n    parameter C_APPLICATION_TYPE_WDCH        = 0,\n    parameter C_APPLICATION_TYPE_WRCH        = 0,\n    parameter C_APPLICATION_TYPE_RACH        = 0,\n    parameter C_APPLICATION_TYPE_RDCH        = 0,\n    parameter C_APPLICATION_TYPE_AXIS        = 0,\n\n    // AXI Built-in FIFO Primitive Type\n    // 512x36, 1kx18, 2kx9, 4kx4, etc\n    parameter C_PRIM_FIFO_TYPE_WACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WRCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_AXIS          = \"512x36\",\n\n    // Enable ECC\n    // 0 = ECC disabled\n    // 1 = ECC enabled\n    parameter C_USE_ECC_WACH                 = 0,\n    parameter C_USE_ECC_WDCH                 = 0,\n    parameter C_USE_ECC_WRCH                 = 0,\n    parameter C_USE_ECC_RACH                 = 0,\n    parameter C_USE_ECC_RDCH                 = 0,\n    parameter C_USE_ECC_AXIS                 = 0,\n\n    // ECC Error Injection Type\n    // 0 = No Error Injection\n    // 1 = Single Bit Error Injection\n    // 2 = Double Bit Error Injection\n    // 3 = Single Bit and Double Bit Error Injection\n    parameter C_ERROR_INJECTION_TYPE_WACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WRCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_AXIS    = 0,\n\n    // Input Data Width\n    // Accumulation of all AXI input signal's width\n    parameter C_DIN_WIDTH_WACH               = 1,\n    parameter C_DIN_WIDTH_WDCH               = 1,\n    parameter C_DIN_WIDTH_WRCH               = 1,\n    parameter C_DIN_WIDTH_RACH               = 1,\n    parameter C_DIN_WIDTH_RDCH               = 1,\n    parameter C_DIN_WIDTH_AXIS               = 1,\n\n    parameter C_WR_DEPTH_WACH                = 16,\n    parameter C_WR_DEPTH_WDCH                = 16,\n    parameter C_WR_DEPTH_WRCH                = 16,\n    parameter C_WR_DEPTH_RACH                = 16,\n    parameter C_WR_DEPTH_RDCH                = 16,\n    parameter C_WR_DEPTH_AXIS                = 16,\n\n    parameter C_WR_PNTR_WIDTH_WACH           = 4,\n    parameter C_WR_PNTR_WIDTH_WDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_WRCH           = 4,\n    parameter C_WR_PNTR_WIDTH_RACH           = 4,\n    parameter C_WR_PNTR_WIDTH_RDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_AXIS           = 4,\n\n    parameter C_HAS_DATA_COUNTS_WACH         = 0,\n    parameter C_HAS_DATA_COUNTS_WDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_WRCH         = 0,\n    parameter C_HAS_DATA_COUNTS_RACH         = 0,\n    parameter C_HAS_DATA_COUNTS_RDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_AXIS         = 0,\n\n    parameter C_HAS_PROG_FLAGS_WACH          = 0,\n    parameter C_HAS_PROG_FLAGS_WDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_WRCH          = 0,\n    parameter C_HAS_PROG_FLAGS_RACH          = 0,\n    parameter C_HAS_PROG_FLAGS_RDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_AXIS          = 0,\n\n    parameter C_PROG_FULL_TYPE_WACH          = 0,\n    parameter C_PROG_FULL_TYPE_WDCH          = 0,\n    parameter C_PROG_FULL_TYPE_WRCH          = 0,\n    parameter C_PROG_FULL_TYPE_RACH          = 0,\n    parameter C_PROG_FULL_TYPE_RDCH          = 0,\n    parameter C_PROG_FULL_TYPE_AXIS          = 0,\n\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS      = 0,\n\n    parameter C_PROG_EMPTY_TYPE_WACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WRCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_AXIS         = 0,\n\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS     = 0,\n\n    parameter C_REG_SLICE_MODE_WACH          = 0,\n    parameter C_REG_SLICE_MODE_WDCH          = 0,\n    parameter C_REG_SLICE_MODE_WRCH          = 0,\n    parameter C_REG_SLICE_MODE_RACH          = 0,\n    parameter C_REG_SLICE_MODE_RDCH          = 0,\n    parameter C_REG_SLICE_MODE_AXIS          = 0\n\n    )\n\n   (\n    //------------------------------------------------------------------------------\n    // Input and Output Declarations\n    //------------------------------------------------------------------------------\n\n    // Conventional FIFO Interface Signals\n    input                               backup,\n    input                               backup_marker,\n    input                               clk,\n    input                               rst,\n    input                               srst,\n    input                               wr_clk,\n    input                               wr_rst,\n    input                               rd_clk,\n    input                               rd_rst,\n    input [C_DIN_WIDTH-1:0]             din,\n    input                               wr_en,\n    input                               rd_en,\n    // Optional inputs\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_assert,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_negate,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_assert,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_negate,\n    input                               int_clk,\n    input                               injectdbiterr,\n    input                               injectsbiterr,\n    input                               sleep,\n\n    output [C_DOUT_WIDTH-1:0]           dout,\n    output                              full,\n    output                              almost_full,\n    output                              wr_ack,\n    output                              overflow,\n    output                              empty,\n    output                              almost_empty,\n    output                              valid,\n    output                              underflow,\n    output [C_DATA_COUNT_WIDTH-1:0]     data_count,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]  rd_data_count,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count,\n    output                              prog_full,\n    output                              prog_empty,\n    output                              sbiterr,\n    output                              dbiterr,\n    output                              wr_rst_busy,\n    output                              rd_rst_busy,\n\n\n    // AXI Global Signal\n    input                               m_aclk,\n    input                               s_aclk,\n    input                               s_aresetn,\n    input                               s_aclk_en,\n    input                               m_aclk_en,\n    \n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_awid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_awaddr,\n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_awlen,\n    input [3-1:0]                       s_axi_awsize,\n    input [2-1:0]                       s_axi_awburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_awlock,\n    input [4-1:0]                       s_axi_awcache,\n    input [3-1:0]                       s_axi_awprot,\n    input [4-1:0]                       s_axi_awqos,\n    input [4-1:0]                       s_axi_awregion,\n    input [C_AXI_AWUSER_WIDTH-1:0]      s_axi_awuser,\n    input                               s_axi_awvalid,\n    output                              s_axi_awready,\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_wid,\n    input [C_AXI_DATA_WIDTH-1:0]        s_axi_wdata,\n    input [C_AXI_DATA_WIDTH/8-1:0]      s_axi_wstrb,\n    input                               s_axi_wlast,\n    input [C_AXI_WUSER_WIDTH-1:0]       s_axi_wuser,\n    input                               s_axi_wvalid,\n    output                              s_axi_wready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_bid,\n    output [2-1:0]                      s_axi_bresp,\n    output [C_AXI_BUSER_WIDTH-1:0]      s_axi_buser,\n    output                              s_axi_bvalid,\n    input                               s_axi_bready,\n    \n    // AXI Full/Lite Master Write Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_awid,\n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_awlen,\n    output [3-1:0]                      m_axi_awsize,\n    output [2-1:0]                      m_axi_awburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_awlock,\n    output [4-1:0]                      m_axi_awcache,\n    output [3-1:0]                      m_axi_awprot,\n    output [4-1:0]                      m_axi_awqos,\n    output [4-1:0]                      m_axi_awregion,\n    output [C_AXI_AWUSER_WIDTH-1:0]     m_axi_awuser,\n    output                              m_axi_awvalid,\n    input                               m_axi_awready,\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_wid,\n    output [C_AXI_DATA_WIDTH-1:0]       m_axi_wdata,\n    output [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb,\n    output                              m_axi_wlast,\n    output [C_AXI_WUSER_WIDTH-1:0]      m_axi_wuser,\n    output                              m_axi_wvalid,\n    input                               m_axi_wready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_bid,\n    input [2-1:0]                       m_axi_bresp,\n    input [C_AXI_BUSER_WIDTH-1:0]       m_axi_buser,\n    input                               m_axi_bvalid,\n    output                              m_axi_bready,\n    \n    \n    // AXI Full/Lite Slave Read Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_arid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_araddr, \n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_arlen,\n    input [3-1:0]                       s_axi_arsize,\n    input [2-1:0]                       s_axi_arburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_arlock,\n    input [4-1:0]                       s_axi_arcache,\n    input [3-1:0]                       s_axi_arprot,\n    input [4-1:0]                       s_axi_arqos,\n    input [4-1:0]                       s_axi_arregion,\n    input [C_AXI_ARUSER_WIDTH-1:0]      s_axi_aruser,\n    input                               s_axi_arvalid,\n    output                              s_axi_arready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_rid,       \n    output [C_AXI_DATA_WIDTH-1:0]       s_axi_rdata, \n    output [2-1:0]                      s_axi_rresp,\n    output                              s_axi_rlast,\n    output [C_AXI_RUSER_WIDTH-1:0]      s_axi_ruser,\n    output                              s_axi_rvalid,\n    input                               s_axi_rready,\n    \n    \n    \n    // AXI Full/Lite Master Read Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_arid,        \n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,  \n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_arlen,\n    output [3-1:0]                      m_axi_arsize,\n    output [2-1:0]                      m_axi_arburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_arlock,\n    output [4-1:0]                      m_axi_arcache,\n    output [3-1:0]                      m_axi_arprot,\n    output [4-1:0]                      m_axi_arqos,\n    output [4-1:0]                      m_axi_arregion,\n    output [C_AXI_ARUSER_WIDTH-1:0]     m_axi_aruser,\n    output                              m_axi_arvalid,\n    input                               m_axi_arready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_rid,        \n    input [C_AXI_DATA_WIDTH-1:0]        m_axi_rdata,  \n    input [2-1:0]                       m_axi_rresp,\n    input                               m_axi_rlast,\n    input [C_AXI_RUSER_WIDTH-1:0]       m_axi_ruser,\n    input                               m_axi_rvalid,\n    output                              m_axi_rready,\n    \n    \n    // AXI Streaming Slave Signals (Write side)\n    input                               s_axis_tvalid,\n    output                              s_axis_tready,\n    input [C_AXIS_TDATA_WIDTH-1:0]      s_axis_tdata,\n    input [C_AXIS_TSTRB_WIDTH-1:0]      s_axis_tstrb,\n    input [C_AXIS_TKEEP_WIDTH-1:0]      s_axis_tkeep,\n    input                               s_axis_tlast,\n    input [C_AXIS_TID_WIDTH-1:0]        s_axis_tid,\n    input [C_AXIS_TDEST_WIDTH-1:0]      s_axis_tdest,\n    input [C_AXIS_TUSER_WIDTH-1:0]      s_axis_tuser,\n    \n    // AXI Streaming Master Signals (Read side)\n    output                              m_axis_tvalid,\n    input                               m_axis_tready,\n    output [C_AXIS_TDATA_WIDTH-1:0]     m_axis_tdata,\n    output [C_AXIS_TSTRB_WIDTH-1:0]     m_axis_tstrb,\n    output [C_AXIS_TKEEP_WIDTH-1:0]     m_axis_tkeep,\n    output                              m_axis_tlast,\n    output [C_AXIS_TID_WIDTH-1:0]       m_axis_tid,\n    output [C_AXIS_TDEST_WIDTH-1:0]     m_axis_tdest,\n    output [C_AXIS_TUSER_WIDTH-1:0]     m_axis_tuser,\n    \n           \n    \n    \n    // AXI Full/Lite Write Address Channel signals\n    input                               axi_aw_injectsbiterr,\n    input                               axi_aw_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_rd_data_count,\n    output                              axi_aw_sbiterr,\n    output                              axi_aw_dbiterr,\n    output                              axi_aw_overflow,\n    output                              axi_aw_underflow,\n    output                              axi_aw_prog_full,\n    output                              axi_aw_prog_empty,\n    \n    \n    // AXI Full/Lite Write Data Channel signals\n    input                               axi_w_injectsbiterr,\n    input                               axi_w_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_rd_data_count,\n    output                              axi_w_sbiterr,\n    output                              axi_w_dbiterr,\n    output                              axi_w_overflow,\n    output                              axi_w_underflow,\n    output                              axi_w_prog_full,\n    output                              axi_w_prog_empty,\n    \n    \n    // AXI Full/Lite Write Response Channel signals\n    input                               axi_b_injectsbiterr,\n    input                               axi_b_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_rd_data_count,\n    output                              axi_b_sbiterr,\n    output                              axi_b_dbiterr,\n    output                              axi_b_overflow,\n    output                              axi_b_underflow,\n    output                              axi_b_prog_full,\n    output                              axi_b_prog_empty,\n    \n    \n    \n    // AXI Full/Lite Read Address Channel signals\n    input                               axi_ar_injectsbiterr,\n    input                               axi_ar_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_rd_data_count,\n    output                              axi_ar_sbiterr,\n    output                              axi_ar_dbiterr,\n    output                              axi_ar_overflow,\n    output                              axi_ar_underflow,\n    output                              axi_ar_prog_full,\n    output                              axi_ar_prog_empty,\n\n    \n    // AXI Full/Lite Read Data Channel Signals\n    input                               axi_r_injectsbiterr,\n    input                               axi_r_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_rd_data_count,\n    output                              axi_r_sbiterr,\n    output                              axi_r_dbiterr,\n    output                              axi_r_overflow,\n    output                              axi_r_underflow,\n    output                              axi_r_prog_full,\n    output                              axi_r_prog_empty,\n\n    \n    // AXI Streaming FIFO Related Signals\n    input                               axis_injectsbiterr,\n    input                               axis_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_wr_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_rd_data_count,\n    output                              axis_sbiterr,\n    output                              axis_dbiterr,\n    output                              axis_overflow,\n    output                              axis_underflow,\n    output                              axis_prog_full,\n    output                              axis_prog_empty\n\n    );\n\n    wire                              BACKUP;\n    wire                              BACKUP_MARKER;\n    wire                              CLK;\n    wire                              RST;\n    wire                              SRST;\n    wire                              WR_CLK;\n    wire                              WR_RST;\n    wire                              RD_CLK;\n    wire                              RD_RST;\n    wire [C_DIN_WIDTH-1:0]            DIN;\n    wire                              WR_EN;\n    wire                              RD_EN;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_ASSERT;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_NEGATE;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_ASSERT;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_NEGATE;\n    wire                              INT_CLK;\n    wire                              INJECTDBITERR;\n    wire                              INJECTSBITERR;\n    wire                              SLEEP;\n    wire [C_DOUT_WIDTH-1:0]           DOUT;\n    wire                              FULL;\n    wire                              ALMOST_FULL;\n    wire                              WR_ACK;\n    wire                              OVERFLOW;\n    wire                              EMPTY;\n    wire                              ALMOST_EMPTY;\n    wire                              VALID;\n    wire                              UNDERFLOW;\n    wire [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT;\n    wire [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT;\n    wire                              PROG_FULL;\n    wire                              PROG_EMPTY;\n    wire                              SBITERR;\n    wire                              DBITERR;\n    wire                              WR_RST_BUSY;\n    wire                              RD_RST_BUSY;\n    wire                              M_ACLK;\n    wire                              S_ACLK;\n    wire                              S_ARESETN;\n    wire                              S_ACLK_EN;\n    wire                              M_ACLK_EN;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_AWLEN;\n    wire [3-1:0]                      S_AXI_AWSIZE;\n    wire [2-1:0]                      S_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_AWLOCK;\n    wire [4-1:0]                      S_AXI_AWCACHE;\n    wire [3-1:0]                      S_AXI_AWPROT;\n    wire [4-1:0]                      S_AXI_AWQOS;\n    wire [4-1:0]                      S_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     S_AXI_AWUSER;\n    wire                              S_AXI_AWVALID;\n    wire                              S_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     S_AXI_WSTRB;\n    wire                              S_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      S_AXI_WUSER;\n    wire                              S_AXI_WVALID;\n    wire                              S_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_BID;\n    wire [2-1:0]                      S_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      S_AXI_BUSER;\n    wire                              S_AXI_BVALID;\n    wire                              S_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_AWLEN;\n    wire [3-1:0]                      M_AXI_AWSIZE;\n    wire [2-1:0]                      M_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_AWLOCK;\n    wire [4-1:0]                      M_AXI_AWCACHE;\n    wire [3-1:0]                      M_AXI_AWPROT;\n    wire [4-1:0]                      M_AXI_AWQOS;\n    wire [4-1:0]                      M_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     M_AXI_AWUSER;\n    wire                              M_AXI_AWVALID;\n    wire                              M_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     M_AXI_WSTRB;\n    wire                              M_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      M_AXI_WUSER;\n    wire                              M_AXI_WVALID;\n    wire                              M_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_BID;\n    wire [2-1:0]                      M_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      M_AXI_BUSER;\n    wire                              M_AXI_BVALID;\n    wire                              M_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_ARID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_ARADDR; \n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_ARLEN;\n    wire [3-1:0]                      S_AXI_ARSIZE;\n    wire [2-1:0]                      S_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_ARLOCK;\n    wire [4-1:0]                      S_AXI_ARCACHE;\n    wire [3-1:0]                      S_AXI_ARPROT;\n    wire [4-1:0]                      S_AXI_ARQOS;\n    wire [4-1:0]                      S_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     S_AXI_ARUSER;\n    wire                              S_AXI_ARVALID;\n    wire                              S_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_RID;       \n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_RDATA; \n    wire [2-1:0]                      S_AXI_RRESP;\n    wire                              S_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      S_AXI_RUSER;\n    wire                              S_AXI_RVALID;\n    wire                              S_AXI_RREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_ARID;        \n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_ARADDR;  \n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_ARLEN;\n    wire [3-1:0]                      M_AXI_ARSIZE;\n    wire [2-1:0]                      M_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_ARLOCK;\n    wire [4-1:0]                      M_AXI_ARCACHE;\n    wire [3-1:0]                      M_AXI_ARPROT;\n    wire [4-1:0]                      M_AXI_ARQOS;\n    wire [4-1:0]                      M_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     M_AXI_ARUSER;\n    wire                              M_AXI_ARVALID;\n    wire                              M_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_RID;        \n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_RDATA;  \n    wire [2-1:0]                      M_AXI_RRESP;\n    wire                              M_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      M_AXI_RUSER;\n    wire                              M_AXI_RVALID;\n    wire                              M_AXI_RREADY;\n    wire                              S_AXIS_TVALID;\n    wire                              S_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     S_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     S_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     S_AXIS_TKEEP;\n    wire                              S_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       S_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     S_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     S_AXIS_TUSER;\n    wire                              M_AXIS_TVALID;\n    wire                              M_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     M_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     M_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     M_AXIS_TKEEP;\n    wire                              M_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       M_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     M_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     M_AXIS_TUSER;\n    wire                              AXI_AW_INJECTSBITERR;\n    wire                              AXI_AW_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_RD_DATA_COUNT;\n    wire                              AXI_AW_SBITERR;\n    wire                              AXI_AW_DBITERR;\n    wire                              AXI_AW_OVERFLOW;\n    wire                              AXI_AW_UNDERFLOW;\n    wire                              AXI_AW_PROG_FULL;\n    wire                              AXI_AW_PROG_EMPTY;\n    wire                              AXI_W_INJECTSBITERR;\n    wire                              AXI_W_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_RD_DATA_COUNT;\n    wire                              AXI_W_SBITERR;\n    wire                              AXI_W_DBITERR;\n    wire                              AXI_W_OVERFLOW;\n    wire                              AXI_W_UNDERFLOW;\n    wire                              AXI_W_PROG_FULL;\n    wire                              AXI_W_PROG_EMPTY;\n    wire                              AXI_B_INJECTSBITERR;\n    wire                              AXI_B_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_RD_DATA_COUNT;\n    wire                              AXI_B_SBITERR;\n    wire                              AXI_B_DBITERR;\n    wire                              AXI_B_OVERFLOW;\n    wire                              AXI_B_UNDERFLOW;\n    wire                              AXI_B_PROG_FULL;\n    wire                              AXI_B_PROG_EMPTY;\n    wire                              AXI_AR_INJECTSBITERR;\n    wire                              AXI_AR_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_RD_DATA_COUNT;\n    wire                              AXI_AR_SBITERR;\n    wire                              AXI_AR_DBITERR;\n    wire                              AXI_AR_OVERFLOW;\n    wire                              AXI_AR_UNDERFLOW;\n    wire                              AXI_AR_PROG_FULL;\n    wire                              AXI_AR_PROG_EMPTY;\n    wire                              AXI_R_INJECTSBITERR;\n    wire                              AXI_R_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_RD_DATA_COUNT;\n    wire                              AXI_R_SBITERR;\n    wire                              AXI_R_DBITERR;\n    wire                              AXI_R_OVERFLOW;\n    wire                              AXI_R_UNDERFLOW;\n    wire                              AXI_R_PROG_FULL;\n    wire                              AXI_R_PROG_EMPTY;\n    wire                              AXIS_INJECTSBITERR;\n    wire                              AXIS_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_RD_DATA_COUNT;\n    wire                              AXIS_SBITERR;\n    wire                              AXIS_DBITERR;\n    wire                              AXIS_OVERFLOW;\n    wire                              AXIS_UNDERFLOW;\n    wire                              AXIS_PROG_FULL;\n    wire                              AXIS_PROG_EMPTY;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count_in;\n    wire                              wr_rst_int;\n    wire                              rd_rst_int;\n    wire                              wr_rst_busy_o;\n    wire                              wr_rst_busy_ntve;\n    wire                              wr_rst_busy_axis;\n    wire                              wr_rst_busy_wach;\n    wire                              wr_rst_busy_wdch;\n    wire                              wr_rst_busy_wrch;\n    wire                              wr_rst_busy_rach;\n    wire                              wr_rst_busy_rdch;\n\n\n\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n\n\n\n    // Conventional FIFO Interface Signals\n    assign BACKUP                 = backup;\n    assign BACKUP_MARKER          = backup_marker;\n    assign CLK                    = clk;\n    assign RST                    = rst;\n    assign SRST                   = srst;\n    assign WR_CLK                 = wr_clk;\n    assign WR_RST                 = wr_rst;\n    assign RD_CLK                 = rd_clk;\n    assign RD_RST                 = rd_rst;\n    assign WR_EN                  = wr_en;\n    assign RD_EN                  = rd_en;\n    assign INT_CLK                = int_clk;\n    assign INJECTDBITERR          = injectdbiterr;\n    assign INJECTSBITERR          = injectsbiterr;\n    assign SLEEP                  = sleep;\n    assign full                   = FULL;\n    assign almost_full            = ALMOST_FULL;\n    assign wr_ack                 = WR_ACK;\n    assign overflow               = OVERFLOW;\n    assign empty                  = EMPTY;\n    assign almost_empty           = ALMOST_EMPTY;\n    assign valid                  = VALID;\n    assign underflow              = UNDERFLOW;\n    assign prog_full              = PROG_FULL;\n    assign prog_empty             = PROG_EMPTY;\n    assign sbiterr                = SBITERR;\n    assign dbiterr                = DBITERR;\n//    assign wr_rst_busy            = WR_RST_BUSY | wr_rst_busy_o;\n    assign wr_rst_busy            = wr_rst_busy_o;\n    assign rd_rst_busy            = RD_RST_BUSY;\n    assign M_ACLK                 = m_aclk;\n    assign S_ACLK                 = s_aclk;\n    assign S_ARESETN              = s_aresetn;\n    assign S_ACLK_EN              = s_aclk_en;\n    assign M_ACLK_EN              = m_aclk_en;\n    assign S_AXI_AWVALID          = s_axi_awvalid;\n    assign s_axi_awready          = S_AXI_AWREADY;\n    assign S_AXI_WLAST            = s_axi_wlast;\n    assign S_AXI_WVALID           = s_axi_wvalid;\n    assign s_axi_wready           = S_AXI_WREADY;\n    assign s_axi_bvalid           = S_AXI_BVALID;\n    assign S_AXI_BREADY           = s_axi_bready;\n    assign m_axi_awvalid          = M_AXI_AWVALID;\n    assign M_AXI_AWREADY          = m_axi_awready;\n    assign m_axi_wlast            = M_AXI_WLAST;\n    assign m_axi_wvalid           = M_AXI_WVALID;\n    assign M_AXI_WREADY           = m_axi_wready;\n    assign M_AXI_BVALID           = m_axi_bvalid;\n    assign m_axi_bready           = M_AXI_BREADY;\n    assign S_AXI_ARVALID          = s_axi_arvalid;\n    assign s_axi_arready          = S_AXI_ARREADY;\n    assign s_axi_rlast            = S_AXI_RLAST;\n    assign s_axi_rvalid           = S_AXI_RVALID;\n    assign S_AXI_RREADY           = s_axi_rready;\n    assign m_axi_arvalid          = M_AXI_ARVALID;\n    assign M_AXI_ARREADY          = m_axi_arready;\n    assign M_AXI_RLAST            = m_axi_rlast;\n    assign M_AXI_RVALID           = m_axi_rvalid;\n    assign m_axi_rready           = M_AXI_RREADY;\n    assign S_AXIS_TVALID          = s_axis_tvalid;\n    assign s_axis_tready          = S_AXIS_TREADY;\n    assign S_AXIS_TLAST           = s_axis_tlast;\n    assign m_axis_tvalid          = M_AXIS_TVALID;\n    assign M_AXIS_TREADY          = m_axis_tready;\n    assign m_axis_tlast           = M_AXIS_TLAST;\n    assign AXI_AW_INJECTSBITERR   = axi_aw_injectsbiterr;\n    assign AXI_AW_INJECTDBITERR   = axi_aw_injectdbiterr;\n    assign axi_aw_sbiterr         = AXI_AW_SBITERR;\n    assign axi_aw_dbiterr         = AXI_AW_DBITERR;\n    assign axi_aw_overflow        = AXI_AW_OVERFLOW;\n    assign axi_aw_underflow       = AXI_AW_UNDERFLOW;\n    assign axi_aw_prog_full       = AXI_AW_PROG_FULL;\n    assign axi_aw_prog_empty      = AXI_AW_PROG_EMPTY;\n    assign AXI_W_INJECTSBITERR    = axi_w_injectsbiterr;\n    assign AXI_W_INJECTDBITERR    = axi_w_injectdbiterr;\n    assign axi_w_sbiterr          = AXI_W_SBITERR;\n    assign axi_w_dbiterr          = AXI_W_DBITERR;\n    assign axi_w_overflow         = AXI_W_OVERFLOW;\n    assign axi_w_underflow        = AXI_W_UNDERFLOW;\n    assign axi_w_prog_full        = AXI_W_PROG_FULL;\n    assign axi_w_prog_empty       = AXI_W_PROG_EMPTY;\n    assign AXI_B_INJECTSBITERR    = axi_b_injectsbiterr;\n    assign AXI_B_INJECTDBITERR    = axi_b_injectdbiterr;\n    assign axi_b_sbiterr          = AXI_B_SBITERR;\n    assign axi_b_dbiterr          = AXI_B_DBITERR;\n    assign axi_b_overflow         = AXI_B_OVERFLOW;\n    assign axi_b_underflow        = AXI_B_UNDERFLOW;\n    assign axi_b_prog_full        = AXI_B_PROG_FULL;\n    assign axi_b_prog_empty       = AXI_B_PROG_EMPTY;\n    assign AXI_AR_INJECTSBITERR   = axi_ar_injectsbiterr;\n    assign AXI_AR_INJECTDBITERR   = axi_ar_injectdbiterr;\n    assign axi_ar_sbiterr         = AXI_AR_SBITERR;\n    assign axi_ar_dbiterr         = AXI_AR_DBITERR;\n    assign axi_ar_overflow        = AXI_AR_OVERFLOW;\n    assign axi_ar_underflow       = AXI_AR_UNDERFLOW;\n    assign axi_ar_prog_full       = AXI_AR_PROG_FULL;\n    assign axi_ar_prog_empty      = AXI_AR_PROG_EMPTY;\n    assign AXI_R_INJECTSBITERR    = axi_r_injectsbiterr;\n    assign AXI_R_INJECTDBITERR    = axi_r_injectdbiterr;\n    assign axi_r_sbiterr          = AXI_R_SBITERR;\n    assign axi_r_dbiterr          = AXI_R_DBITERR;\n    assign axi_r_overflow         = AXI_R_OVERFLOW;\n    assign axi_r_underflow        = AXI_R_UNDERFLOW;\n    assign axi_r_prog_full        = AXI_R_PROG_FULL;\n    assign axi_r_prog_empty       = AXI_R_PROG_EMPTY;\n    assign AXIS_INJECTSBITERR     = axis_injectsbiterr;\n    assign AXIS_INJECTDBITERR     = axis_injectdbiterr;\n    assign axis_sbiterr           = AXIS_SBITERR;\n    assign axis_dbiterr           = AXIS_DBITERR;\n    assign axis_overflow          = AXIS_OVERFLOW;\n    assign axis_underflow         = AXIS_UNDERFLOW;\n    assign axis_prog_full         = AXIS_PROG_FULL;\n    assign axis_prog_empty        = AXIS_PROG_EMPTY;\n\n\n    assign DIN                       = din;\n    assign PROG_EMPTY_THRESH         = prog_empty_thresh;\n    assign PROG_EMPTY_THRESH_ASSERT  = prog_empty_thresh_assert;\n    assign PROG_EMPTY_THRESH_NEGATE  = prog_empty_thresh_negate;\n    assign PROG_FULL_THRESH          = prog_full_thresh;\n    assign PROG_FULL_THRESH_ASSERT   = prog_full_thresh_assert;\n    assign PROG_FULL_THRESH_NEGATE   = prog_full_thresh_negate;\n    assign dout                      = DOUT;\n    assign data_count                = DATA_COUNT;\n    assign rd_data_count             = RD_DATA_COUNT;\n    assign wr_data_count             = WR_DATA_COUNT;\n    assign S_AXI_AWID                = s_axi_awid;\n    assign S_AXI_AWADDR              = s_axi_awaddr;\n    assign S_AXI_AWLEN               = s_axi_awlen;\n    assign S_AXI_AWSIZE              = s_axi_awsize;\n    assign S_AXI_AWBURST             = s_axi_awburst;\n    assign S_AXI_AWLOCK              = s_axi_awlock;\n    assign S_AXI_AWCACHE             = s_axi_awcache;\n    assign S_AXI_AWPROT              = s_axi_awprot;\n    assign S_AXI_AWQOS               = s_axi_awqos;\n    assign S_AXI_AWREGION            = s_axi_awregion;\n    assign S_AXI_AWUSER              = s_axi_awuser;\n    assign S_AXI_WID                 = s_axi_wid;\n    assign S_AXI_WDATA               = s_axi_wdata;\n    assign S_AXI_WSTRB               = s_axi_wstrb;\n    assign S_AXI_WUSER               = s_axi_wuser;\n    assign s_axi_bid                 = S_AXI_BID;\n    assign s_axi_bresp               = S_AXI_BRESP;\n    assign s_axi_buser               = S_AXI_BUSER;\n    assign m_axi_awid                = M_AXI_AWID;\n    assign m_axi_awaddr              = M_AXI_AWADDR;\n    assign m_axi_awlen               = M_AXI_AWLEN;\n    assign m_axi_awsize              = M_AXI_AWSIZE;\n    assign m_axi_awburst             = M_AXI_AWBURST;\n    assign m_axi_awlock              = M_AXI_AWLOCK;\n    assign m_axi_awcache             = M_AXI_AWCACHE;\n    assign m_axi_awprot              = M_AXI_AWPROT;\n    assign m_axi_awqos               = M_AXI_AWQOS;\n    assign m_axi_awregion            = M_AXI_AWREGION;\n    assign m_axi_awuser              = M_AXI_AWUSER;\n    assign m_axi_wid                 = M_AXI_WID;\n    assign m_axi_wdata               = M_AXI_WDATA;\n    assign m_axi_wstrb               = M_AXI_WSTRB;\n    assign m_axi_wuser               = M_AXI_WUSER;\n    assign M_AXI_BID                 = m_axi_bid;\n    assign M_AXI_BRESP               = m_axi_bresp;\n    assign M_AXI_BUSER               = m_axi_buser;\n    assign S_AXI_ARID                = s_axi_arid;\n    assign S_AXI_ARADDR              = s_axi_araddr; \n    assign S_AXI_ARLEN               = s_axi_arlen;\n    assign S_AXI_ARSIZE              = s_axi_arsize;\n    assign S_AXI_ARBURST             = s_axi_arburst;\n    assign S_AXI_ARLOCK              = s_axi_arlock;\n    assign S_AXI_ARCACHE             = s_axi_arcache;\n    assign S_AXI_ARPROT              = s_axi_arprot;\n    assign S_AXI_ARQOS               = s_axi_arqos;\n    assign S_AXI_ARREGION            = s_axi_arregion;\n    assign S_AXI_ARUSER              = s_axi_aruser;\n    assign s_axi_rid                 = S_AXI_RID;\n    assign s_axi_rdata               = S_AXI_RDATA;\n    assign s_axi_rresp               = S_AXI_RRESP;\n    assign s_axi_ruser               = S_AXI_RUSER;\n    assign m_axi_arid                = M_AXI_ARID;        \n    assign m_axi_araddr              = M_AXI_ARADDR;  \n    assign m_axi_arlen               = M_AXI_ARLEN;\n    assign m_axi_arsize              = M_AXI_ARSIZE;\n    assign m_axi_arburst             = M_AXI_ARBURST;\n    assign m_axi_arlock              = M_AXI_ARLOCK;\n    assign m_axi_arcache             = M_AXI_ARCACHE;\n    assign m_axi_arprot              = M_AXI_ARPROT;\n    assign m_axi_arqos               = M_AXI_ARQOS;\n    assign m_axi_arregion            = M_AXI_ARREGION;\n    assign m_axi_aruser              = M_AXI_ARUSER;\n    assign M_AXI_RID                 = m_axi_rid;        \n    assign M_AXI_RDATA               = m_axi_rdata;  \n    assign M_AXI_RRESP               = m_axi_rresp;\n    assign M_AXI_RUSER               = m_axi_ruser;\n    assign S_AXIS_TDATA              = s_axis_tdata;\n    assign S_AXIS_TSTRB              = s_axis_tstrb;\n    assign S_AXIS_TKEEP              = s_axis_tkeep;\n    assign S_AXIS_TID                = s_axis_tid;\n    assign S_AXIS_TDEST              = s_axis_tdest;\n    assign S_AXIS_TUSER              = s_axis_tuser;\n    assign m_axis_tdata              = M_AXIS_TDATA;\n    assign m_axis_tstrb              = M_AXIS_TSTRB;\n    assign m_axis_tkeep              = M_AXIS_TKEEP;\n    assign m_axis_tid                = M_AXIS_TID;\n    assign m_axis_tdest              = M_AXIS_TDEST;\n    assign m_axis_tuser              = M_AXIS_TUSER;\n    assign AXI_AW_PROG_FULL_THRESH   = axi_aw_prog_full_thresh;\n    assign AXI_AW_PROG_EMPTY_THRESH  = axi_aw_prog_empty_thresh;\n    assign axi_aw_data_count         = AXI_AW_DATA_COUNT;\n    assign axi_aw_wr_data_count      = AXI_AW_WR_DATA_COUNT;\n    assign axi_aw_rd_data_count      = AXI_AW_RD_DATA_COUNT;\n    assign AXI_W_PROG_FULL_THRESH    = axi_w_prog_full_thresh;\n    assign AXI_W_PROG_EMPTY_THRESH   = axi_w_prog_empty_thresh;\n    assign axi_w_data_count          = AXI_W_DATA_COUNT;\n    assign axi_w_wr_data_count       = AXI_W_WR_DATA_COUNT;\n    assign axi_w_rd_data_count       = AXI_W_RD_DATA_COUNT;\n    assign AXI_B_PROG_FULL_THRESH    = axi_b_prog_full_thresh;\n    assign AXI_B_PROG_EMPTY_THRESH   = axi_b_prog_empty_thresh;\n    assign axi_b_data_count          = AXI_B_DATA_COUNT;\n    assign axi_b_wr_data_count       = AXI_B_WR_DATA_COUNT;\n    assign axi_b_rd_data_count       = AXI_B_RD_DATA_COUNT;\n    assign AXI_AR_PROG_FULL_THRESH   = axi_ar_prog_full_thresh;\n    assign AXI_AR_PROG_EMPTY_THRESH  = axi_ar_prog_empty_thresh;\n    assign axi_ar_data_count         = AXI_AR_DATA_COUNT;\n    assign axi_ar_wr_data_count      = AXI_AR_WR_DATA_COUNT;\n    assign axi_ar_rd_data_count      = AXI_AR_RD_DATA_COUNT;\n    assign AXI_R_PROG_FULL_THRESH    = axi_r_prog_full_thresh;\n    assign AXI_R_PROG_EMPTY_THRESH   = axi_r_prog_empty_thresh;\n    assign axi_r_data_count          = AXI_R_DATA_COUNT;\n    assign axi_r_wr_data_count       = AXI_R_WR_DATA_COUNT;\n    assign axi_r_rd_data_count       = AXI_R_RD_DATA_COUNT;\n    assign AXIS_PROG_FULL_THRESH     = axis_prog_full_thresh;\n    assign AXIS_PROG_EMPTY_THRESH    = axis_prog_empty_thresh;\n    assign axis_data_count           = AXIS_DATA_COUNT;\n    assign axis_wr_data_count        = AXIS_WR_DATA_COUNT;\n    assign axis_rd_data_count        = AXIS_RD_DATA_COUNT;\n\n\n  generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_COMMON_CLOCK \t\t(C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DATA_COUNT_WIDTH\t\t(C_DATA_COUNT_WIDTH),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH),\n        .C_DOUT_RST_VAL\t\t\t(C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),\n        .C_DOUT_WIDTH\t\t\t(C_DOUT_WIDTH),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n        .C_HAS_ALMOST_EMPTY\t\t(C_HAS_ALMOST_EMPTY),\n        .C_HAS_ALMOST_FULL\t\t(C_HAS_ALMOST_FULL),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_DATA_COUNT\t\t(C_HAS_DATA_COUNT),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_HAS_RD_DATA_COUNT\t\t(C_HAS_RD_DATA_COUNT),\n        .C_HAS_RD_RST\t\t\t(C_HAS_RD_RST),\n        .C_HAS_RST\t\t\t(C_HAS_RST),\n        .C_HAS_SRST\t\t\t(C_HAS_SRST),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_HAS_VALID\t\t\t(C_HAS_VALID),\n        .C_HAS_WR_ACK\t\t\t(C_HAS_WR_ACK),\n        .C_HAS_WR_DATA_COUNT\t\t(C_HAS_WR_DATA_COUNT),\n        .C_HAS_WR_RST\t\t\t(C_HAS_WR_RST),\n        .C_IMPLEMENTATION_TYPE\t\t(C_IMPLEMENTATION_TYPE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_MEMORY_TYPE\t\t\t(C_MEMORY_TYPE),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n        .C_PRELOAD_LATENCY\t\t(C_PRELOAD_LATENCY),\n        .C_PRELOAD_REGS\t\t\t(C_PRELOAD_REGS),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL),\n        .C_PROG_EMPTY_THRESH_NEGATE_VAL\t(C_PROG_EMPTY_THRESH_NEGATE_VAL),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL),\n        .C_PROG_FULL_THRESH_NEGATE_VAL\t(C_PROG_FULL_THRESH_NEGATE_VAL),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_RD_DATA_COUNT_WIDTH),\n        .C_RD_DEPTH\t\t\t(C_RD_DEPTH),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_RD_PNTR_WIDTH\t\t(C_RD_PNTR_WIDTH),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n        .C_USE_ECC                      (C_USE_ECC),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_EN_SAFETY_CKT\t\t(C_EN_SAFETY_CKT),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_USE_FWFT_DATA_COUNT\t\t(C_USE_FWFT_DATA_COUNT),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_DATA_COUNT_WIDTH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (C_ENABLE_RST_SYNC),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE),\n        .C_AXI_TYPE                     (C_AXI_TYPE),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE)\n      )\n    fifo_generator_v13_2_5_conv_dut\n      (\n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .CLK                      (CLK),\n        .RST                      (RST),\n        .SRST                     (SRST),\n        .WR_CLK                   (WR_CLK),\n        .WR_RST                   (WR_RST),\n        .RD_CLK                   (RD_CLK),\n        .RD_RST                   (RD_RST),\n        .DIN                      (DIN),\n        .WR_EN                    (WR_EN),\n        .RD_EN                    (RD_EN),\n        .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),\n        .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),\n        .PROG_FULL_THRESH         (PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),\n        .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),\n        .INT_CLK                  (INT_CLK),\n        .INJECTDBITERR            (INJECTDBITERR), \n        .INJECTSBITERR            (INJECTSBITERR),\n  \n        .DOUT                     (DOUT),\n        .FULL                     (FULL),\n        .ALMOST_FULL              (ALMOST_FULL),\n        .WR_ACK                   (WR_ACK),\n        .OVERFLOW                 (OVERFLOW),\n        .EMPTY                    (EMPTY),\n        .ALMOST_EMPTY             (ALMOST_EMPTY),\n        .VALID                    (VALID),\n        .UNDERFLOW                (UNDERFLOW),\n        .DATA_COUNT               (DATA_COUNT),\n        .RD_DATA_COUNT            (RD_DATA_COUNT),\n        .WR_DATA_COUNT            (wr_data_count_in),\n        .PROG_FULL                (PROG_FULL),\n        .PROG_EMPTY               (PROG_EMPTY),\n        .SBITERR                  (SBITERR),\n        .DBITERR                  (DBITERR),\n        .wr_rst_busy_o            (wr_rst_busy_o),\n        .wr_rst_busy              (wr_rst_busy_i),\n        .rd_rst_busy              (rd_rst_busy),\n        .wr_rst_i_out             (wr_rst_int),\n        .rd_rst_i_out             (rd_rst_int)\n       );\n  end endgenerate\n\n\n\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n  localparam C_AXI_SIZE_WIDTH   = 3;\n  localparam C_AXI_BURST_WIDTH  = 2;\n  localparam C_AXI_CACHE_WIDTH  = 4;\n  localparam C_AXI_PROT_WIDTH   = 3;\n  localparam C_AXI_QOS_WIDTH    = 4;\n  localparam C_AXI_REGION_WIDTH = 4;\n  localparam C_AXI_BRESP_WIDTH  = 2;\n  localparam C_AXI_RRESP_WIDTH  = 2;\n\n  localparam IS_AXI_STREAMING  = C_INTERFACE_TYPE == 1 ? 1 : 0;\n  localparam TDATA_OFFSET      = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;\n  localparam TSTRB_OFFSET      = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;\n  localparam TKEEP_OFFSET      = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;\n  localparam TID_OFFSET        = C_HAS_AXIS_TID   == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;\n  localparam TDEST_OFFSET      = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;\n  localparam TUSER_OFFSET      = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;\n  localparam LOG_DEPTH_AXIS    = find_log2(C_WR_DEPTH_AXIS); \n  localparam LOG_WR_DEPTH      = find_log2(C_WR_DEPTH); \n\n\n  function [LOG_DEPTH_AXIS-1:0] bin2gray;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      begin\n         bin2gray = x ^ (x>>1);\n      end\n   endfunction\n\n  function [LOG_DEPTH_AXIS-1:0] gray2bin;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      integer                i;\n      begin\n         gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];\n         for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin\n            gray2bin[i] =  gray2bin[i+1] ^ x[i];\n         end\n      end\n   endfunction\n\nwire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;\nwire  [LOG_WR_DEPTH-1 : 0]  w_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;\nreg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;\nwire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;\nwire [LOG_WR_DEPTH : 0] r_inv_pad;\nwire [LOG_WR_DEPTH-1 : 0] d_cnt;\nreg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;\nreg adj_w_cnt_rd_pad_0 = 0;\nreg r_inv_pad_0 = 0;\n\n\n   genvar l;\n\n   generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (LOG_WR_DEPTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_int), \n         .CLK      (RD_CLK), \n         .DIN      (w_q[l-1]), \n         .DOUT     (w_q[l])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter\n    assign wr_eop_ad = WR_EN & !(FULL);\n    assign rd_eop_ad = RD_EN & !(EMPTY);\n\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt    <= 1'b0;\n      else if (wr_eop_ad)\n        w_cnt    <= w_cnt + 1;\n    end\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt_gc    <= 1'b0;\n      else \n        w_cnt_gc    <= bin2gray(w_cnt);\n    end\n\n\n    assign  w_q[0]  = w_cnt_gc;\n    assign  w_cnt_gc_asreg_last       = w_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        w_cnt_rd    <= 1'b0;\n      else \n        w_cnt_rd    <= gray2bin(w_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        r_cnt    <= 1'b0;\n      else if (rd_eop_ad)\n        r_cnt    <= r_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;\n   assign r_inv_pad[LOG_WR_DEPTH : 1]        = ~r_cnt;\n   assign adj_w_cnt_rd_pad[0]                = adj_w_cnt_rd_pad_0;\n   assign r_inv_pad[0]                       = r_inv_pad_0;\n\n\n  always @ ( rd_eop_ad )\n    begin\n      if (!rd_eop_ad) begin\n        adj_w_cnt_rd_pad_0    <= 1'b1;\n        r_inv_pad_0           <= 1'b1;\n      end else begin \n        adj_w_cnt_rd_pad_0    <= 1'b0;\n        r_inv_pad_0           <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        d_cnt_pad    <= 1'b0;\n      else \n        d_cnt_pad    <= adj_w_cnt_rd_pad + r_inv_pad ;\n    end\n\n   assign  d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;\n   assign  WR_DATA_COUNT = d_cnt;\n\n  end endgenerate // fifo_ic_adapter\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter\n   assign  WR_DATA_COUNT = wr_data_count_in;\n\n  end endgenerate // fifo_icn_adapter\n\n\n\n  wire                          inverted_reset = ~S_ARESETN;\n  wire                          axi_rs_rst;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_din          ;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_dout         ;\n  wire                          axis_full         ;\n  wire                          axis_almost_full  ;\n  wire                          axis_empty        ;\n  wire                          axis_s_axis_tready;\n  wire                          axis_m_axis_tvalid;\n  wire                          axis_wr_en        ;\n  wire                          axis_rd_en        ;\n  wire                          axis_we           ;\n  wire                          axis_re           ;\n  wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;\n  reg                           axis_pkt_read = 1'b0;\n  wire                          axis_rd_rst;\n  wire                          axis_wr_rst;\n\n  generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||\n               C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst\n      reg                           rst_d1 = 0        ;\n      reg                           rst_d2 = 0        ;\n      reg [3:0]                    axi_rst = 4'h0     ;\n      always @ (posedge inverted_reset or posedge S_ACLK) begin\n        if (inverted_reset) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          axi_rst        <= 4'hf;\n        end else begin\n          rst_d1         <= #`TCQ 1'b0;\n          rst_d2         <= #`TCQ rst_d1;\n          axi_rst        <= #`TCQ {axi_rst[2:0],1'b0};\n        end\n      end\n\n      assign axi_rs_rst = axi_rst[3];//rst_d2;\n  end endgenerate // gaxi_rs_rst\n\n  generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming\n\n    // Write protection when almost full or prog_full is high\n    assign axis_we    = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : \n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign axis_re    = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :\n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? axis_we & S_ACLK_EN : axis_we;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE               (C_INTERFACE_TYPE),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 2  || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_AXIS),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_AXIS),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),\n        .C_USE_ECC                      (C_USE_ECC_AXIS),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_AXIS),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_axis_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (axis_wr_en),\n        .RD_EN                    (axis_rd_en),\n        .PROG_FULL_THRESH         (AXIS_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXIS_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .INJECTDBITERR            (AXIS_INJECTDBITERR), \n        .INJECTSBITERR            (AXIS_INJECTSBITERR),\n  \n        .DIN                      (axis_din),\n        .DOUT                     (axis_dout),\n        .FULL                     (axis_full),\n        .EMPTY                    (axis_empty),\n        .ALMOST_FULL              (axis_almost_full),\n        .PROG_FULL                (AXIS_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXIS_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (AXIS_OVERFLOW),\n        .VALID                    (),\n        .UNDERFLOW                (AXIS_UNDERFLOW),\n        .DATA_COUNT               (axis_dc),\n        .RD_DATA_COUNT            (AXIS_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXIS_WR_DATA_COUNT),\n        .SBITERR                  (AXIS_SBITERR),\n        .DBITERR                  (AXIS_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_axis),\n        .rd_rst_busy              (rd_rst_busy_axis),\n        .wr_rst_i_out             (axis_wr_rst),\n        .rd_rst_i_out             (axis_rd_rst),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign axis_s_axis_tready    = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;\n    assign axis_m_axis_tvalid    = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;\n    assign S_AXIS_TREADY         = axis_s_axis_tready;\n    assign M_AXIS_TVALID         = axis_m_axis_tvalid;\n\n  end endgenerate // axi_streaming\n\n  wire axis_wr_eop;\n  reg  axis_wr_eop_d1 = 1'b0;\n  wire axis_rd_eop;\n  integer  axis_pkt_cnt;\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)\n        axis_pkt_read    <= 1'b0;\n      else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_wr_eop_d1    <= 1'b0;\n      else\n        axis_wr_eop_d1   <= axis_wr_eop;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_cnt    <= 0;\n      else if (axis_wr_eop_d1 && ~axis_rd_eop)\n        axis_pkt_cnt    <= axis_pkt_cnt + 1;\n      else if (axis_rd_eop && ~axis_wr_eop_d1)\n        axis_pkt_cnt    <= axis_pkt_cnt - 1;\n    end\n  end endgenerate // gaxis_pkt_fifo_cc\n\n\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;\nwire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;\nwire axis_rd_has_rst;\nwire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;\nwire  [LOG_DEPTH_AXIS-1 : 0]  wpkt_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;\nwire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;\nwire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;\nwire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;\nwire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;\nreg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;\nreg adj_axis_wpkt_cnt_rd_pad_0 = 0;\nreg rpkt_inv_pad_0 = 0;\nwire axis_af_rd ;\n\ngenerate if (C_HAS_RST == 1) begin : rst_blk_has\n  assign axis_rd_has_rst = axis_rd_rst;\nend endgenerate //rst_blk_has\n\ngenerate if (C_HAS_RST == 0) begin :rst_blk_no\n  assign axis_rd_has_rst = 1'b0;\nend endgenerate //rst_blk_no\n\n   genvar i;\n\n   generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (LOG_DEPTH_AXIS)\n        )\n     rd_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (wpkt_q[i-1]), \n         .DOUT     (wpkt_q[i])\n        );\n \n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (1)\n        )\n     wr_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (axis_af_q[i-1]), \n         .DOUT     (axis_af_q[i])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (diff_pkt_cnt == 1))\n        axis_pkt_read    <= 1'b0;\n      else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt    <= 1'b0;\n      else if (axis_wr_eop)\n        axis_wpkt_cnt    <= axis_wpkt_cnt + 1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt_gc    <= 1'b0;\n      else \n        axis_wpkt_cnt_gc    <= bin2gray(axis_wpkt_cnt);\n    end\n\n\n    assign  wpkt_q[0]  = axis_wpkt_cnt_gc;\n    assign  axis_wpkt_cnt_gc_asreg_last       = wpkt_q[C_SYNCHRONIZER_STAGE];\n    assign  axis_af_q[0]                      = axis_almost_full;\n    //assign  axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];\n    assign  axis_af_rd                        = axis_af_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_wpkt_cnt_rd    <= 1'b0;\n      else \n        axis_wpkt_cnt_rd    <= gray2bin(axis_wpkt_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_rpkt_cnt    <= 1'b0;\n      else if (axis_rd_eop)\n        axis_rpkt_cnt    <= axis_rpkt_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;\n   assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1]             = ~axis_rpkt_cnt;\n   assign adj_axis_wpkt_cnt_rd_pad[0]                                = adj_axis_wpkt_cnt_rd_pad_0;\n   assign rpkt_inv_pad[0]                                            = rpkt_inv_pad_0;\n\n\n  always @ ( axis_rd_eop )\n    begin\n      if (!axis_rd_eop) begin\n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b1;\n        rpkt_inv_pad_0                <= 1'b1;\n      end else begin \n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b0;\n        rpkt_inv_pad_0                <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        diff_pkt_cnt_pad    <= 1'b0;\n      else \n        diff_pkt_cnt_pad    <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;\n    end\n\n   assign  diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;\n\n\n\n\n\n   end endgenerate // gaxis_pkt_fifo_ic\n\n\n\n\n  // Generate the accurate data count for axi stream packet fifo configuration\n  reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_dc_pkt_fifo <= 0;\n      else if (axis_wr_en && (~axis_rd_en))\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;\n      else if (~axis_wr_en && axis_rd_en)\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;\n    end\n    assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;\n  end endgenerate // gdc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt\n    assign AXIS_DATA_COUNT = 0;\n  end endgenerate // gndc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc\n    assign AXIS_DATA_COUNT = axis_dc;\n  end endgenerate // gdc\n\n  // Register Slice for Write Address Channel\n  generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_AXIS),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_AXIS)\n            )\n    axis_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (axis_din),\n          .S_VALID                   (axis_wr_en),\n          .S_READY                   (S_AXIS_TREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (axis_dout),\n          .M_VALID                   (M_AXIS_TVALID),\n          .M_READY                   (axis_rd_en)\n          );\n  end endgenerate // gaxis_reg_slice\n\n\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata\n    assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;\n    assign M_AXIS_TDATA   = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb\n    assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;\n    assign M_AXIS_TSTRB   = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep\n    assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;\n    assign M_AXIS_TKEEP   = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid\n    assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;\n    assign M_AXIS_TID     = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest\n    assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;\n    assign M_AXIS_TDEST   = axis_dout[TID_OFFSET-1:TDEST_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser\n    assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;\n    assign M_AXIS_TUSER   = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast\n    assign axis_din[0] = S_AXIS_TLAST;\n    assign M_AXIS_TLAST   = axis_dout[0];\n  end endgenerate\n\n  //###########################################################################\n  //  AXI FULL Write Channel (axi_write_channel)\n  //###########################################################################\n\n  localparam IS_AXI_FULL       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;\n  localparam IS_AXI_LITE       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;\n\n  localparam IS_AXI_FULL_WACH  = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WDCH  = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WRCH  = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RACH  = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RDCH  = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_AXI_LITE_WACH  = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WDCH  = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WRCH  = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RACH  = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RDCH  = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_WR_ADDR_CH     = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;\n  localparam IS_WR_DATA_CH     = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;\n  localparam IS_WR_RESP_CH     = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;\n  localparam IS_RD_ADDR_CH     = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;\n  localparam IS_RD_DATA_CH     = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;\n\n  localparam AWID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;\n  localparam AWADDR_OFFSET     = AWID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam AWLEN_OFFSET      = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;\n  localparam AWSIZE_OFFSET     = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;\n  localparam AWBURST_OFFSET    = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;\n  localparam AWLOCK_OFFSET     = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;\n  localparam AWCACHE_OFFSET    = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;\n  localparam AWPROT_OFFSET     = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam AWQOS_OFFSET      = AWPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam AWREGION_OFFSET   = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;\n  localparam AWUSER_OFFSET     = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;\n\n  localparam WID_OFFSET        = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;\n  localparam WDATA_OFFSET      = WID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam WSTRB_OFFSET      = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;\n  localparam WUSER_OFFSET      = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;\n\n  localparam BID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;\n  localparam BRESP_OFFSET      = BID_OFFSET - C_AXI_BRESP_WIDTH;\n  localparam BUSER_OFFSET      = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;\n\n\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_din          ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout         ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout_pkt     ;\n  wire                          wach_full         ;\n  wire                          wach_almost_full  ;\n  wire                          wach_prog_full    ;\n  wire                          wach_empty        ;\n  wire                          wach_almost_empty ;\n  wire                          wach_prog_empty   ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_din          ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_dout         ;\n  wire                          wdch_full         ;\n  wire                          wdch_almost_full  ;\n  wire                          wdch_prog_full    ;\n  wire                          wdch_empty        ;\n  wire                          wdch_almost_empty ;\n  wire                          wdch_prog_empty   ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_din          ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_dout         ;\n  wire                          wrch_full         ;\n  wire                          wrch_almost_full  ;\n  wire                          wrch_prog_full    ;\n  wire                          wrch_empty        ;\n  wire                          wrch_almost_empty ;\n  wire                          wrch_prog_empty   ;\n  wire                          axi_aw_underflow_i;\n  wire                          axi_w_underflow_i ;\n  wire                          axi_b_underflow_i ;\n  wire                          axi_aw_overflow_i ;\n  wire                          axi_w_overflow_i  ;\n  wire                          axi_b_overflow_i  ;\n  wire                          axi_wr_underflow_i;\n  wire                          axi_wr_overflow_i ;\n  wire                          wach_s_axi_awready;\n  wire                          wach_m_axi_awvalid;\n  wire                          wach_wr_en        ;\n  wire                          wach_rd_en        ;\n  wire                          wdch_s_axi_wready ;\n  wire                          wdch_m_axi_wvalid ;\n  wire                          wdch_wr_en        ;\n  wire                          wdch_rd_en        ;\n  wire                          wrch_s_axi_bvalid ;\n  wire                          wrch_m_axi_bready ;\n  wire                          wrch_wr_en        ;\n  wire                          wrch_rd_en        ;\n  wire                          txn_count_up      ;\n  wire                          txn_count_down    ;\n  wire                          awvalid_en        ;\n  wire                          awvalid_pkt       ;\n  wire                          awready_pkt       ;\n  integer                       wr_pkt_count      ;\n  wire                          wach_we           ;\n  wire                          wach_re           ;\n  wire                          wdch_we           ;\n  wire                          wdch_re           ;\n  wire                          wrch_we           ;\n  wire                          wrch_re           ;\n\n  generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel\n    // Write protection when almost full or prog_full is high\n    assign wach_we    = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wach_re    = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        wach_m_axi_awvalid & awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY && wach_m_axi_awvalid :\n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY : 1'b0;\n    assign wach_wr_en = (C_HAS_SLAVE_CE == 1)  ? wach_we & S_ACLK_EN : wach_we;\n    assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 2  || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),\n        .C_USE_ECC                      (C_USE_ECC_WACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wach_wr_en),\n        .RD_EN                    (wach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AW_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AW_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AW_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AW_INJECTSBITERR),\n  \n        .DIN                      (wach_din),\n        .DOUT                     (wach_dout_pkt),\n        .FULL                     (wach_full),\n        .EMPTY                    (wach_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_AW_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_AW_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_aw_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_aw_underflow_i),\n        .DATA_COUNT               (AXI_AW_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AW_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AW_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AW_SBITERR),\n        .DBITERR                  (AXI_AW_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wach),\n        .rd_rst_busy              (rd_rst_busy_wach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wach_s_axi_awready    = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;\n    assign wach_m_axi_awvalid   = ~wach_empty;\n    assign S_AXI_AWREADY        = wach_s_axi_awready;\n\n    assign AXI_AW_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;\n    assign AXI_AW_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_aw_overflow_i  : 0;\n\n  end endgenerate // axi_write_address_channel\n\n  // Register Slice for Write Address Channel\n  generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WACH)\n            )\n    wach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_din),\n          .S_VALID                   (S_AXI_AWVALID),\n          .S_READY                   (S_AXI_AWREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n  end endgenerate // gwach_reg_slice\n  \n  generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (1)\n            )\n    wach_pkt_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_dout_pkt),\n          .S_VALID                   (awvalid_pkt),\n          .S_READY                   (awready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n\n    assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;\n\n    assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; \n    assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset == 1) begin\n\twr_pkt_count <= 0;\n      end else begin\n\tif(txn_count_up == 1 && txn_count_down == 0) begin\n\t  wr_pkt_count <= wr_pkt_count + 1;\n\tend else if(txn_count_up == 0 && txn_count_down == 1) begin\n\t  wr_pkt_count <= wr_pkt_count - 1;\n\tend\n      end\n    end //Always end\n    assign awvalid_en = (wr_pkt_count > 0)?1:0;\n  end endgenerate\n  \n  generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr\n    assign awvalid_en    = 1;    \n    assign wach_dout     = wach_dout_pkt;\n    assign M_AXI_AWVALID = wach_m_axi_awvalid;\n  end\n  endgenerate\n\n\n\n  generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel\n    // Write protection when almost full or prog_full is high\n    assign wdch_we    = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wdch_re    = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;\n    assign wdch_wr_en = (C_HAS_SLAVE_CE == 1)  ? wdch_we & S_ACLK_EN : wdch_we;\n    assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;\n\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 2  || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),\n        .C_USE_ECC                      (C_USE_ECC_WDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wdch_wr_en),\n        .RD_EN                    (wdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_W_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_W_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_W_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_W_INJECTSBITERR),\n  \n        .DIN                      (wdch_din),\n        .DOUT                     (wdch_dout),\n        .FULL                     (wdch_full),\n        .EMPTY                    (wdch_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_W_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_W_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_w_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_w_underflow_i),\n        .DATA_COUNT               (AXI_W_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_W_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_W_WR_DATA_COUNT),\n        .SBITERR                  (AXI_W_SBITERR),\n        .DBITERR                  (AXI_W_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wdch),\n        .rd_rst_busy              (rd_rst_busy_wdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wdch_s_axi_wready     = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;\n    assign wdch_m_axi_wvalid = ~wdch_empty;\n    assign S_AXI_WREADY      = wdch_s_axi_wready;\n    assign M_AXI_WVALID      = wdch_m_axi_wvalid;\n\n    assign AXI_W_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i  : 0;\n    assign AXI_W_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_w_overflow_i   : 0;\n\n  end endgenerate // axi_write_data_channel\n\n  // Register Slice for Write Data Channel\n  generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WDCH)\n            )\n    wdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wdch_din),\n          .S_VALID                   (S_AXI_WVALID),\n          .S_READY                   (S_AXI_WREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wdch_dout),\n          .M_VALID                   (M_AXI_WVALID),\n          .M_READY                   (M_AXI_WREADY)\n          );\n  end endgenerate // gwdch_reg_slice\n\n  generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel\n    // Write protection when almost full or prog_full is high\n    assign wrch_we    = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wrch_re    = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;\n    assign wrch_wr_en = (C_HAS_MASTER_CE == 1)  ? wrch_we & M_ACLK_EN : wrch_we;\n    assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 2  || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WRCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WRCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),\n        .C_USE_ECC                      (C_USE_ECC_WRCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WRCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WRCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wrch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wrch_wr_en),\n        .RD_EN                    (wrch_rd_en),\n        .PROG_FULL_THRESH         (AXI_B_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_B_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .INJECTDBITERR            (AXI_B_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_B_INJECTSBITERR),\n  \n        .DIN                      (wrch_din),\n        .DOUT                     (wrch_dout),\n        .FULL                     (wrch_full),\n        .EMPTY                    (wrch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_B_PROG_FULL),\n        .PROG_EMPTY               (AXI_B_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_b_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_b_underflow_i),\n        .DATA_COUNT               (AXI_B_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_B_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_B_WR_DATA_COUNT),\n        .SBITERR                  (AXI_B_SBITERR),\n        .DBITERR                  (AXI_B_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wrch),\n        .rd_rst_busy              (rd_rst_busy_wrch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wrch_s_axi_bvalid = ~wrch_empty;\n    assign wrch_m_axi_bready     = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;\n    assign S_AXI_BVALID      = wrch_s_axi_bvalid;\n    assign M_AXI_BREADY      = wrch_m_axi_bready;\n\n    assign AXI_B_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i  : 0;\n    assign AXI_B_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_b_overflow_i   : 0;\n  end endgenerate // axi_write_resp_channel\n\n  // Register Slice for Write Response Channel\n  generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WRCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WRCH)\n            )\n    wrch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wrch_din),\n          .S_VALID                   (M_AXI_BVALID),\n          .S_READY                   (M_AXI_BREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wrch_dout),\n          .M_VALID                   (S_AXI_BVALID),\n          .M_READY                   (S_AXI_BREADY)\n          );\n  end endgenerate // gwrch_reg_slice\n\n\n    assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW  == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;\n    assign axi_wr_overflow_i  = C_USE_COMMON_OVERFLOW   == 1 ? (axi_aw_overflow_i  || axi_w_overflow_i  || axi_b_overflow_i)  : 0;\n\n  generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output\n    assign M_AXI_AWADDR    = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];    \n    assign M_AXI_AWLEN     = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];    \n    assign M_AXI_AWSIZE    = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];    \n    assign M_AXI_AWBURST   = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];    \n    assign M_AXI_AWLOCK    = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];    \n    assign M_AXI_AWCACHE   = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];    \n    assign M_AXI_AWQOS     = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];    \n    assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET]    = S_AXI_AWADDR;\n    assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET]   = S_AXI_AWLEN;\n    assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET]   = S_AXI_AWSIZE;\n    assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;\n    assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;\n    assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;\n    assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;\n    assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET]   = S_AXI_AWQOS;\n  end endgenerate // axi_wach_output\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion\n    assign M_AXI_AWREGION  = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];    \n  end endgenerate // axi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion\n    assign M_AXI_AWREGION  = 0;    \n  end endgenerate // naxi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser\n    assign M_AXI_AWUSER  = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];    \n  end endgenerate // axi_awuser\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser\n    assign M_AXI_AWUSER  = 0;    \n  end endgenerate // naxi_awuser\n\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid\n    assign M_AXI_AWID      = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];\n  end endgenerate //axi_awid\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid\n    assign M_AXI_AWID      = 0;\n  end endgenerate //naxi_awid\n\n  generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output\n    assign M_AXI_WDATA     = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n    assign M_AXI_WLAST     = wdch_dout[0];\n    assign wdch_din[WID_OFFSET-1:WDATA_OFFSET]   = S_AXI_WDATA;\n    assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;\n    assign wdch_din[0]   = S_AXI_WLAST;\n  end endgenerate // axi_wdch_output\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin\n    assign M_AXI_WID       = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];\n  end endgenerate\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin\n    assign M_AXI_WID       = 0;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin\n    assign M_AXI_WUSER     = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];    \n  end endgenerate\n  generate if (C_HAS_AXI_WUSER == 0) begin\n    assign M_AXI_WUSER       = 0;\n  end endgenerate\n\n  generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output\n    assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; \n    assign wrch_din[BID_OFFSET-1:BRESP_OFFSET]   = M_AXI_BRESP;\n  end endgenerate // axi_wrch_output\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser\n    assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];\n  end endgenerate // axi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser\n    assign S_AXI_BUSER = 0;\n  end endgenerate // naxi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid\n    assign S_AXI_BID   =  wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];\n  end endgenerate // axi_bid\n  \n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid\n    assign S_AXI_BID   =  0 ;\n  end endgenerate // naxi_bid  \n\n\n  generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1\n    assign wach_din        = {S_AXI_AWADDR, S_AXI_AWPROT};\n    assign M_AXI_AWADDR    = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];    \n  end endgenerate // axi_wach_output1\n\n  generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1\n    assign wdch_din        = {S_AXI_WDATA, S_AXI_WSTRB};\n    assign M_AXI_WDATA     = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n  end endgenerate // axi_wdch_output1\n\n  generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1\n    assign wrch_din        = M_AXI_BRESP;\n    assign S_AXI_BRESP     = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; \n  end endgenerate // axi_wrch_output1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1\n    assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET]     = S_AXI_AWUSER;\n  end endgenerate // gwach_din1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2\n    assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET]     = S_AXI_AWID;\n  end endgenerate // gwach_din2\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3\n    assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET]     = S_AXI_AWREGION;\n  end endgenerate // gwach_din3\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1\n    assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;\n  end endgenerate // gwdch_din1\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2\n    assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;\n  end endgenerate // gwdch_din2\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1\n    assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET]    = M_AXI_BUSER;\n  end endgenerate // gwrch_din1\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2\n    assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET]    = M_AXI_BID;\n  end endgenerate // gwrch_din2\n\n  //end of  axi_write_channel\n\n  //###########################################################################\n  //  AXI FULL Read Channel (axi_read_channel)\n  //###########################################################################\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_din            ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout           ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout_pkt       ;\n  wire                               rach_full           ;\n  wire                               rach_almost_full    ;\n  wire                               rach_prog_full      ;\n  wire                               rach_empty          ;\n  wire                               rach_almost_empty   ;\n  wire                               rach_prog_empty     ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_din            ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_dout           ;\n  wire                               rdch_full           ;\n  wire                               rdch_almost_full    ;\n  wire                               rdch_prog_full      ;\n  wire                               rdch_empty          ;\n  wire                               rdch_almost_empty   ;\n  wire                               rdch_prog_empty     ;\n  wire                               axi_ar_underflow_i  ;\n  wire                               axi_r_underflow_i   ;\n  wire                               axi_ar_overflow_i   ;\n  wire                               axi_r_overflow_i    ;\n  wire                               axi_rd_underflow_i  ;\n  wire                               axi_rd_overflow_i   ;\n  wire                               rach_s_axi_arready  ;\n  wire                               rach_m_axi_arvalid  ;\n  wire                               rach_wr_en          ;\n  wire                               rach_rd_en          ;\n  wire                               rdch_m_axi_rready   ;\n  wire                               rdch_s_axi_rvalid   ;\n  wire                               rdch_wr_en          ;\n  wire                               rdch_rd_en          ;\n  wire                               arvalid_pkt         ;\n  wire                               arready_pkt         ;\n  wire                               arvalid_en          ;\n  wire                               rdch_rd_ok          ;\n  wire                               accept_next_pkt     ;\n  integer                            rdch_free_space     ;\n  integer                            rdch_commited_space ;\n  wire                               rach_we             ;\n  wire                               rach_re             ;\n  wire                               rdch_we             ;\n  wire                               rdch_re             ;\n\n  localparam ARID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;\n  localparam ARADDR_OFFSET     = ARID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam ARLEN_OFFSET      = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;\n  localparam ARSIZE_OFFSET     = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;\n  localparam ARBURST_OFFSET    = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;\n  localparam ARLOCK_OFFSET     = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;\n  localparam ARCACHE_OFFSET    = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;\n  localparam ARPROT_OFFSET     = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam ARQOS_OFFSET      = ARPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam ARREGION_OFFSET   = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;\n  localparam ARUSER_OFFSET     = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;\n\n  localparam RID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;\n  localparam RDATA_OFFSET      = RID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam RRESP_OFFSET      = RDATA_OFFSET - C_AXI_RRESP_WIDTH;\n  localparam RUSER_OFFSET      = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;\n\n\n  generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rach_we    = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;\n\n    // Read protection when almost empty or prog_empty is high\n//    assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;\n    assign rach_re    = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        rach_m_axi_arvalid & arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY && rach_m_axi_arvalid :\n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY : 1'b0;\n    assign rach_wr_en = (C_HAS_SLAVE_CE == 1)  ? rach_we & S_ACLK_EN : rach_we;\n    assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;\n\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 2  || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),\n        .C_USE_ECC                      (C_USE_ECC_RACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_rach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rach_wr_en),\n        .RD_EN                    (rach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AR_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AR_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AR_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AR_INJECTSBITERR),\n  \n        .DIN                      (rach_din),\n        .DOUT                     (rach_dout_pkt),\n        .FULL                     (rach_full),\n        .EMPTY                    (rach_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_AR_PROG_FULL),\n        .PROG_EMPTY               (AXI_AR_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_ar_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_ar_underflow_i),\n        .DATA_COUNT               (AXI_AR_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AR_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AR_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AR_SBITERR),\n        .DBITERR                  (AXI_AR_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rach),\n        .rd_rst_busy              (rd_rst_busy_rach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rach_s_axi_arready    = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;\n    assign rach_m_axi_arvalid = ~rach_empty;\n    assign S_AXI_ARREADY      = rach_s_axi_arready;\n\n    assign AXI_AR_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;\n    assign AXI_AR_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_ar_overflow_i  : 0;\n\n  end endgenerate // axi_read_addr_channel\n\n  // Register Slice for Read Address Channel\n  generate if (C_RACH_TYPE == 1) begin : grach_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RACH)\n            )\n    rach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_din),\n          .S_VALID                   (S_AXI_ARVALID),\n          .S_READY                   (S_AXI_ARREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice\n\n  // Register Slice for Read Address Channel for MM Packet FIFO\n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (1)\n            )\n    reg_slice_mm_pkt_fifo_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_dout_pkt),\n          .S_VALID                   (arvalid_pkt),\n          .S_READY                   (arready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice_mm_pkt_fifo\n\n  \n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid\n    assign M_AXI_ARVALID      = rach_m_axi_arvalid;\n    assign rach_dout          = rach_dout_pkt;\n  end endgenerate // grach_m_axi_arvalid\n  \n  \n  generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd\n    assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;\n    assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;\n    assign accept_next_pkt  = rach_m_axi_arvalid && arready_pkt && arvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset) begin\n\trdch_commited_space <= 0;\n      end else begin\n\tif(rdch_rd_ok && !accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space-1;\n\tend else if(!rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);\n\tend else if(rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);\n\tend\n      end\n    end //Always end\n\n    always@(*) begin\n      rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));\n    end\n\n    assign arvalid_en = (rdch_free_space >= 0)?1:0;\n  end\n  endgenerate\n  \n  generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd\n    assign arvalid_en = 1;    \n  end\n  endgenerate\n\n  generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rdch_we    = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready  & M_AXI_RVALID : M_AXI_RVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign rdch_re    = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid  & S_AXI_RREADY : S_AXI_RREADY;\n    assign rdch_wr_en = (C_HAS_MASTER_CE == 1)  ? rdch_we & M_ACLK_EN : rdch_we;\n    assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 2  || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),\n        .C_USE_ECC                      (C_USE_ECC_RDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_RDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_rdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rdch_wr_en),\n        .RD_EN                    (rdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_R_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_R_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_R_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_R_INJECTSBITERR),\n  \n        .DIN                      (rdch_din),\n        .DOUT                     (rdch_dout),\n        .FULL                     (rdch_full),\n        .EMPTY                    (rdch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_R_PROG_FULL),\n        .PROG_EMPTY               (AXI_R_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_r_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_r_underflow_i),\n        .DATA_COUNT               (AXI_R_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_R_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_R_WR_DATA_COUNT),\n        .SBITERR                  (AXI_R_SBITERR),\n        .DBITERR                  (AXI_R_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rdch),\n        .rd_rst_busy              (rd_rst_busy_rdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rdch_s_axi_rvalid = ~rdch_empty;\n    assign rdch_m_axi_rready     = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;\n    assign S_AXI_RVALID      = rdch_s_axi_rvalid;\n    assign M_AXI_RREADY      = rdch_m_axi_rready;\n\n    assign AXI_R_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i  : 0;\n    assign AXI_R_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_r_overflow_i   : 0;\n\n  end endgenerate //axi_read_data_channel\n\n  // Register Slice for read Data Channel\n  generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RDCH)\n            )\n    rdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rdch_din),\n          .S_VALID                   (M_AXI_RVALID),\n          .S_READY                   (M_AXI_RREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rdch_dout),\n          .M_VALID                   (S_AXI_RVALID),\n          .M_READY                   (S_AXI_RREADY)\n          );\n  end endgenerate // grdch_reg_slice\n\n\n    assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;\n    assign axi_rd_overflow_i  = C_USE_COMMON_OVERFLOW  == 1 ? (axi_ar_overflow_i  || axi_r_overflow_i) : 0;\n\n\n  generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output\n    assign M_AXI_ARADDR    = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];    \n    assign M_AXI_ARLEN     = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];    \n    assign M_AXI_ARSIZE    = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];    \n    assign M_AXI_ARBURST   = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];    \n    assign M_AXI_ARLOCK    = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];    \n    assign M_AXI_ARCACHE   = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];    \n    assign M_AXI_ARPROT    = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];    \n    assign M_AXI_ARQOS     = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];    \n    assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET]    = S_AXI_ARADDR;\n    assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET]   = S_AXI_ARLEN;\n    assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET]   = S_AXI_ARSIZE;\n    assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;\n    assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;\n    assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;\n    assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;\n    assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET]   = S_AXI_ARQOS;\n  end endgenerate // axi_full_rach_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion\n    assign M_AXI_ARREGION  = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];    \n  end endgenerate // axi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion\n    assign M_AXI_ARREGION  = 0;    \n  end endgenerate // naxi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser\n    assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];    \n  end endgenerate // axi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser\n    assign M_AXI_ARUSER = 0;    \n  end endgenerate // naxi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid\n    assign M_AXI_ARID      = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];\n  end endgenerate // axi_arid\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid\n    assign M_AXI_ARID      = 0;\n  end endgenerate // naxi_arid\n\n  generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output\n    assign S_AXI_RDATA     = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];\n    assign S_AXI_RRESP     = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n    assign S_AXI_RLAST     = rdch_dout[0];\n    assign rdch_din[RID_OFFSET-1:RDATA_OFFSET]   = M_AXI_RDATA;\n    assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;\n    assign rdch_din[0] = M_AXI_RLAST;\n  end endgenerate // axi_full_rdch_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output\n    assign S_AXI_RUSER     = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];\n  end endgenerate // axi_full_ruser_output\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output\n    assign S_AXI_RUSER     =  0;\n  end endgenerate // axi_full_nruser_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid\n    assign S_AXI_RID       = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];\n  end endgenerate // axi_rid\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid\n    assign S_AXI_RID       = 0;\n  end endgenerate // naxi_rid\n\n  generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1\n    assign rach_din      = {S_AXI_ARADDR, S_AXI_ARPROT};\n    assign M_AXI_ARADDR  = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];\n    assign M_AXI_ARPROT  = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];\n  end endgenerate // axi_lite_rach_output\n\n  generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1\n    assign rdch_din      = {M_AXI_RDATA, M_AXI_RRESP};\n    assign S_AXI_RDATA   = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];\n    assign S_AXI_RRESP   = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n  end endgenerate // axi_lite_rdch_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1\n    assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET]     = S_AXI_ARUSER;\n  end endgenerate // grach_din1\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2\n    assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET]     = S_AXI_ARID;\n  end endgenerate // grach_din2\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin\n    assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1\n    assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET]     = M_AXI_RUSER;\n  end endgenerate // grdch_din1\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2\n    assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;\n  end endgenerate // grdch_din2\n\n  //end of axi_read_channel\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf\n    assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :\n                       (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :\n                       (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;\n  end endgenerate // gaxi_comm_uf\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of\n    assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :\n                      (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :\n                      (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;\n  end endgenerate // gaxi_comm_of\n  \n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  // Pass Through Logic or Wiring Logic\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  \n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Write Address Channel\n  generate if (C_WACH_TYPE == 2) begin : gwach_pass_through\n    assign M_AXI_AWID      = S_AXI_AWID;\n    assign M_AXI_AWADDR    = S_AXI_AWADDR;\n    assign M_AXI_AWLEN     = S_AXI_AWLEN;\n    assign M_AXI_AWSIZE    = S_AXI_AWSIZE;\n    assign M_AXI_AWBURST   = S_AXI_AWBURST;\n    assign M_AXI_AWLOCK    = S_AXI_AWLOCK;\n    assign M_AXI_AWCACHE   = S_AXI_AWCACHE;\n    assign M_AXI_AWPROT    = S_AXI_AWPROT;\n    assign M_AXI_AWQOS     = S_AXI_AWQOS;\n    assign M_AXI_AWREGION  = S_AXI_AWREGION;\n    assign M_AXI_AWUSER    = S_AXI_AWUSER;\n    assign S_AXI_AWREADY   = M_AXI_AWREADY;\n    assign M_AXI_AWVALID   = S_AXI_AWVALID;\n  end endgenerate // gwach_pass_through;\n\n  // Wiring logic for Write Data Channel\n  generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through\n    assign M_AXI_WID       = S_AXI_WID;\n    assign M_AXI_WDATA     = S_AXI_WDATA;\n    assign M_AXI_WSTRB     = S_AXI_WSTRB;\n    assign M_AXI_WLAST     = S_AXI_WLAST;\n    assign M_AXI_WUSER     = S_AXI_WUSER;\n    assign S_AXI_WREADY    = M_AXI_WREADY;\n    assign M_AXI_WVALID    = S_AXI_WVALID;\n  end endgenerate // gwdch_pass_through;\n\n  // Wiring logic for Write Response Channel\n  generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through\n    assign S_AXI_BID       = M_AXI_BID;\n    assign S_AXI_BRESP     = M_AXI_BRESP;\n    assign S_AXI_BUSER     = M_AXI_BUSER;\n    assign M_AXI_BREADY    = S_AXI_BREADY;\n    assign S_AXI_BVALID    = M_AXI_BVALID;\n  end endgenerate // gwrch_pass_through;\n\n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Read Address Channel\n  generate if (C_RACH_TYPE == 2) begin : grach_pass_through\n    assign M_AXI_ARID      = S_AXI_ARID;\n    assign M_AXI_ARADDR    = S_AXI_ARADDR;\n    assign M_AXI_ARLEN     = S_AXI_ARLEN;\n    assign M_AXI_ARSIZE    = S_AXI_ARSIZE;\n    assign M_AXI_ARBURST   = S_AXI_ARBURST;\n    assign M_AXI_ARLOCK    = S_AXI_ARLOCK;\n    assign M_AXI_ARCACHE   = S_AXI_ARCACHE;\n    assign M_AXI_ARPROT    = S_AXI_ARPROT;\n    assign M_AXI_ARQOS     = S_AXI_ARQOS;\n    assign M_AXI_ARREGION  = S_AXI_ARREGION;\n    assign M_AXI_ARUSER    = S_AXI_ARUSER;\n    assign S_AXI_ARREADY   = M_AXI_ARREADY;\n    assign M_AXI_ARVALID   = S_AXI_ARVALID;\n  end endgenerate // grach_pass_through;\n\n  // Wiring logic for Read Data Channel \n  generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through\n    assign S_AXI_RID      = M_AXI_RID;\n    assign S_AXI_RLAST    = M_AXI_RLAST;\n    assign S_AXI_RUSER    = M_AXI_RUSER;\n    assign S_AXI_RDATA    = M_AXI_RDATA;\n    assign S_AXI_RRESP    = M_AXI_RRESP;\n    assign S_AXI_RVALID   = M_AXI_RVALID;\n    assign M_AXI_RREADY   = S_AXI_RREADY;\n  end endgenerate // grdch_pass_through;\n\n  // Wiring logic for AXI Streaming\n  generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through\n    assign M_AXIS_TDATA   = S_AXIS_TDATA;\n    assign M_AXIS_TSTRB   = S_AXIS_TSTRB;\n    assign M_AXIS_TKEEP   = S_AXIS_TKEEP;\n    assign M_AXIS_TID     = S_AXIS_TID;\n    assign M_AXIS_TDEST   = S_AXIS_TDEST;\n    assign M_AXIS_TUSER   = S_AXIS_TUSER;\n    assign M_AXIS_TLAST   = S_AXIS_TLAST;\n    assign S_AXIS_TREADY  = M_AXIS_TREADY;\n    assign M_AXIS_TVALID  = S_AXIS_TVALID;\n  end endgenerate // gaxis_pass_through;\n\n\nendmodule //fifo_generator_v13_2_5\n\n\n\n/*******************************************************************************\n * Declaration of top-level module for Conventional FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_CONV_VER\n  #(\n    parameter  C_COMMON_CLOCK                 = 0,\n    parameter  C_INTERFACE_TYPE               = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_COUNT_TYPE                   = 0,\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DEFAULT_VALUE                = \"\",\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_ENABLE_RLOCS                 = 0,\n    parameter  C_FAMILY                       = \"virtex7\", //Not allowed in Verilog model\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_BACKUP                   = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_INT_CLK                  = 0,\n    parameter  C_HAS_MEMINIT_FILE             = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RD_RST                   = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_RST                   = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_INIT_WR_PNTR_VAL             = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_MIF_FILE_NAME                = \"\",\n    parameter  C_OPTIMIZATION_MODE            = 0,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PRIM_FIFO_TYPE               = \"\",\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_FREQ                      = 1,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_ECC                      = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_USE_FIFO16_FLAGS             = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_FREQ                      = 1,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_WR_RESPONSE_LATENCY          = 1,\n    parameter  C_MSGON_VAL                    = 1,\n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2,\n    parameter  C_AXI_TYPE                     = 0\n   )\n\n  (\n   input                               BACKUP,\n   input                               BACKUP_MARKER,\n   input                               CLK,\n   input                               RST,\n   input                               SRST,\n   input                               WR_CLK,\n   input                               WR_RST,\n   input                               RD_CLK,\n   input                               RD_RST,\n   input [C_DIN_WIDTH-1:0]             DIN,\n   input                               WR_EN,\n   input                               RD_EN,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_ASSERT,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_NEGATE,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_ASSERT,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_NEGATE,\n   input                               INT_CLK,\n   input                               INJECTDBITERR,\n   input                               INJECTSBITERR,\n  \n   output [C_DOUT_WIDTH-1:0]           DOUT,\n   output                              FULL,\n   output                              ALMOST_FULL,\n   output                              WR_ACK,\n   output                              OVERFLOW,\n   output                              EMPTY,\n   output                              ALMOST_EMPTY,\n   output                              VALID,\n   output                              UNDERFLOW,\n   output [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT,\n   output [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT,\n   output [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT,\n   output                              PROG_FULL,\n   output                              PROG_EMPTY,\n   output                              SBITERR,\n   output                              DBITERR,\n   output                              wr_rst_busy_o,\n   output                              wr_rst_busy,\n   output                              rd_rst_busy,\n   output                              wr_rst_i_out,\n   output                              rd_rst_i_out\n  );\n\n/*\n ******************************************************************************\n * Definition of Parameters\n ******************************************************************************\n *     C_COMMON_CLOCK                : Common Clock (1), Independent Clocks (0)\n *     C_COUNT_TYPE                  :    *not used\n *     C_DATA_COUNT_WIDTH            : Width of DATA_COUNT bus\n *     C_DEFAULT_VALUE               :    *not used\n *     C_DIN_WIDTH                   : Width of DIN bus\n *     C_DOUT_RST_VAL                : Reset value of DOUT\n *     C_DOUT_WIDTH                  : Width of DOUT bus\n *     C_ENABLE_RLOCS                :    *not used\n *     C_FAMILY                      : not used in bhv model\n *     C_FULL_FLAGS_RST_VAL          : Full flags rst val (0 or 1)\n *     C_HAS_ALMOST_EMPTY            : 1=Core has ALMOST_EMPTY flag\n *     C_HAS_ALMOST_FULL             : 1=Core has ALMOST_FULL flag\n *     C_HAS_BACKUP                  :    *not used\n *     C_HAS_DATA_COUNT              : 1=Core has DATA_COUNT bus\n *     C_HAS_INT_CLK                 : not used in bhv model\n *     C_HAS_MEMINIT_FILE            :    *not used\n *     C_HAS_OVERFLOW                : 1=Core has OVERFLOW flag\n *     C_HAS_RD_DATA_COUNT           : 1=Core has RD_DATA_COUNT bus\n *     C_HAS_RD_RST                  :    *not used\n *     C_HAS_RST                     : 1=Core has Async Rst\n *     C_HAS_SRST                    : 1=Core has Sync Rst\n *     C_HAS_UNDERFLOW               : 1=Core has UNDERFLOW flag\n *     C_HAS_VALID                   : 1=Core has VALID flag\n *     C_HAS_WR_ACK                  : 1=Core has WR_ACK flag\n *     C_HAS_WR_DATA_COUNT           : 1=Core has WR_DATA_COUNT bus\n *     C_HAS_WR_RST                  :    *not used\n *     C_IMPLEMENTATION_TYPE         : 0=Common-Clock Bram/Dram\n *                                     1=Common-Clock ShiftRam\n *                                     2=Indep. Clocks Bram/Dram\n *                                     3=Virtex-4 Built-in\n *                                     4=Virtex-5 Built-in\n *     C_INIT_WR_PNTR_VAL            :   *not used\n *     C_MEMORY_TYPE                 : 1=Block RAM\n *                                     2=Distributed RAM\n *                                     3=Shift RAM\n *                                     4=Built-in FIFO\n *     C_MIF_FILE_NAME               :   *not used\n *     C_OPTIMIZATION_MODE           :   *not used\n *     C_OVERFLOW_LOW                : 1=OVERFLOW active low\n *     C_PRELOAD_LATENCY             : Latency of read: 0, 1, 2\n *     C_PRELOAD_REGS                : 1=Use output registers\n *     C_PRIM_FIFO_TYPE              : not used in bhv model\n *     C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold\n *     C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold\n *     C_PROG_EMPTY_TYPE             : 0=No programmable empty\n *                                     1=Single prog empty thresh constant\n *                                     2=Multiple prog empty thresh constants\n *                                     3=Single prog empty thresh input\n *                                     4=Multiple prog empty thresh inputs\n *     C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold\n *     C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold\n *     C_PROG_FULL_TYPE              : 0=No prog full\n *                                     1=Single prog full thresh constant\n *                                     2=Multiple prog full thresh constants\n *                                     3=Single prog full thresh input\n *                                     4=Multiple prog full thresh inputs\n *     C_RD_DATA_COUNT_WIDTH         : Width of RD_DATA_COUNT bus\n *     C_RD_DEPTH                    : Depth of read interface (2^N)\n *     C_RD_FREQ                     : not used in bhv model\n *     C_RD_PNTR_WIDTH               : always log2(C_RD_DEPTH)\n *     C_UNDERFLOW_LOW               : 1=UNDERFLOW active low\n *     C_USE_DOUT_RST                : 1=Resets DOUT on RST\n *     C_USE_ECC                     : Used for error injection purpose\n *     C_USE_EMBEDDED_REG            : 1=Use BRAM embedded output register\n *     C_USE_FIFO16_FLAGS            : not used in bhv model\n *     C_USE_FWFT_DATA_COUNT         : 1=Use extra logic for FWFT data count\n *     C_VALID_LOW                   : 1=VALID active low\n *     C_WR_ACK_LOW                  : 1=WR_ACK active low\n *     C_WR_DATA_COUNT_WIDTH         : Width of WR_DATA_COUNT bus\n *     C_WR_DEPTH                    : Depth of write interface (2^N)\n *     C_WR_FREQ                     : not used in bhv model\n *     C_WR_PNTR_WIDTH               : always log2(C_WR_DEPTH)\n *     C_WR_RESPONSE_LATENCY         :    *not used\n *     C_MSGON_VAL                   :    *not used by bhv model\n *     C_ENABLE_RST_SYNC             : 0 = Use WR_RST & RD_RST\n *                                     1 = Use RST\n *     C_ERROR_INJECTION_TYPE        : 0 = No error injection\n *                                     1 = Single bit error injection only\n *                                     2 = Double bit error injection only\n *                                     3 = Single and double bit error injection\n ******************************************************************************\n * Definition of Ports\n ******************************************************************************\n *   BACKUP       : Not used\n *   BACKUP_MARKER: Not used\n *   CLK          : Clock\n *   DIN          : Input data bus\n *   PROG_EMPTY_THRESH       : Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag\n *   PROG_FULL_THRESH        : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag\n *   RD_CLK       : Read Domain Clock\n *   RD_EN        : Read enable\n *   RD_RST       : Read Reset\n *   RST          : Asynchronous Reset\n *   SRST         : Synchronous Reset\n *   WR_CLK       : Write Domain Clock\n *   WR_EN        : Write enable\n *   WR_RST       : Write Reset\n *   INT_CLK      : Internal Clock\n *   INJECTSBITERR: Inject Signle bit error\n *   INJECTDBITERR: Inject Double bit error\n *   ALMOST_EMPTY : One word remaining in FIFO\n *   ALMOST_FULL  : One empty space remaining in FIFO\n *   DATA_COUNT   : Number of data words in fifo( synchronous to CLK)\n *   DOUT         : Output data bus\n *   EMPTY        : Empty flag\n *   FULL         : Full flag\n *   OVERFLOW     : Last write rejected\n *   PROG_EMPTY   : Programmable Empty Flag\n *   PROG_FULL    : Programmable Full Flag\n *   RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)\n *   UNDERFLOW    : Last read rejected\n *   VALID        : Last read acknowledged, DOUT bus VALID\n *   WR_ACK       : Last write acknowledged\n *   WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)\n *   SBITERR      : Single Bit ECC Error Detected\n *   DBITERR      : Double Bit ECC Error Detected\n ******************************************************************************\n */\n\n  //----------------------------------------------------------------------------\n  //- Internal Signals for delayed input signals\n  //- All the input signals except Clock are delayed by 100 ps and then given to\n  //- the models.\n  //----------------------------------------------------------------------------\n \n  reg                         rst_delayed                       ;\n  reg                         empty_fb                       ;\n  reg                         srst_delayed                      ;\n  reg                         wr_rst_delayed                    ;\n  reg                         rd_rst_delayed                    ;\n  reg                         wr_en_delayed                     ;\n  reg                         rd_en_delayed                     ;\n  reg  [C_DIN_WIDTH-1:0]      din_delayed                       ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_delayed         ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_assert_delayed  ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_negate_delayed  ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_delayed          ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_assert_delayed   ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_negate_delayed   ;\n  reg                         injectdbiterr_delayed             ;\n  reg                         injectsbiterr_delayed             ;\n   wire                        empty_p0_out;\n\n  always @* rst_delayed                       <= #`TCQ RST                      ;\n  always @* empty_fb                       <= #`TCQ empty_p0_out                      ;\n  always @* srst_delayed                      <= #`TCQ SRST                     ; \n  always @* wr_rst_delayed                    <= #`TCQ WR_RST                   ; \n  always @* rd_rst_delayed                    <= #`TCQ RD_RST                   ; \n  always @* din_delayed                       <= #`TCQ DIN                      ; \n  always @* wr_en_delayed                     <= #`TCQ WR_EN                    ; \n  always @* rd_en_delayed                     <= #`TCQ RD_EN                    ; \n  always @* prog_empty_thresh_delayed         <= #`TCQ PROG_EMPTY_THRESH        ; \n  always @* prog_empty_thresh_assert_delayed  <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; \n  always @* prog_empty_thresh_negate_delayed  <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; \n  always @* prog_full_thresh_delayed          <= #`TCQ PROG_FULL_THRESH         ; \n  always @* prog_full_thresh_assert_delayed   <= #`TCQ PROG_FULL_THRESH_ASSERT  ; \n  always @* prog_full_thresh_negate_delayed   <= #`TCQ PROG_FULL_THRESH_NEGATE  ; \n  always @* injectdbiterr_delayed             <= #`TCQ INJECTDBITERR            ; \n  always @* injectsbiterr_delayed             <= #`TCQ INJECTSBITERR            ; \n\n  /*****************************************************************************\n   * Derived parameters\n   ****************************************************************************/\n  //There are 2 Verilog behavioral models\n  // 0 = Common-Clock FIFO/ShiftRam FIFO\n  // 1 = Independent Clocks FIFO\n  // 2 = Low Latency Synchronous FIFO\n  // 3 = Low Latency Asynchronous FIFO\n  localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :\n                              (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n\n  //Internal reset signals\n  reg                                rd_rst_asreg    = 1'b0;\n  reg                                rd_rst_asreg_d1 = 1'b0;\n  reg                                rd_rst_asreg_d2 = 1'b0;\n  reg                                rd_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_reg      = 1'b0;\n  reg                                rd_rst_comb     = 1'b1;\n  reg                                rd_rst_comb_d1  = 1'b0;\n  reg                                wr_rst_d0       = 1'b0;\n  reg                                wr_rst_d1       = 1'b0;\n  reg                                wr_rst_d2       = 1'b0;\n  reg                                rd_rst_d0       = 1'b0;\n  reg                                rd_rst_d1       = 1'b0;\n  reg                                rd_rst_d2       = 1'b0;\n  reg                                rd_rst_d3       = 1'b0;\n  reg                                wrrst_done      = 1'b0;\n  reg                                rdrst_done      = 1'b0;\n  reg                                wr_rst_asreg    = 1'b0;\n  reg                                wr_rst_asreg_d1 = 1'b0;\n  reg                                wr_rst_asreg_d2 = 1'b0;\n  reg                                wr_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_wr_d0    = 1'b0;\n  reg                                rd_rst_wr_d1    = 1'b0;\n  reg                                rd_rst_wr_d2    = 1'b0;\n  reg                                wr_rst_reg      = 1'b0;\n  reg                                rst_active_i    = 1'b1;\n  reg                                rst_delayed_d1  = 1'b1;\n  reg                                rst_delayed_d2  = 1'b1;\n  reg                                wr_rst_comb     = 1'b1;\n  reg                                wr_rst_comb_d1  = 1'b0;\n  wire                               wr_rst_i;\n  wire                               rd_rst_i;\n  wire                               rst_i;\n\n  //Internal reset signals\n  reg                                rst_asreg     = 1'b0;\n  reg                                srst_asreg    = 1'b0;\n  reg                                rst_asreg_d1  = 1'b0;\n  reg                                rst_asreg_d2  = 1'b0;\n  reg                                srst_asreg_d1 = 1'b0;\n  reg                                srst_asreg_d2 = 1'b0;\n  reg                                rst_reg       = 1'b0;\n  reg                                srst_reg      = 1'b0;\n  reg                                rst_comb      = 1'b1;\n  reg                                rst_comb_d1   = 1'b0;\n  wire                               srst_comb;\n  reg                                rst_full_gen_i = 0;\n  reg                                rst_full_ff_i = 0;\n  reg  [2:0]                         sckt_ff0_bsy_o_i = {3{1'b0}};\n                                     \n  wire                               RD_CLK_P0_IN;\n  wire                               RST_P0_IN;\n  wire                               RD_EN_FIFO_IN;\n  wire                               RD_EN_P0_IN;\n\n  wire                               ALMOST_EMPTY_FIFO_OUT;\n  wire                               ALMOST_FULL_FIFO_OUT;\n  wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT_FIFO_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DOUT_FIFO_OUT;\n  wire                               EMPTY_FIFO_OUT;\n  wire                               fifo_empty_fb;\n  wire                               FULL_FIFO_OUT;\n  wire                               OVERFLOW_FIFO_OUT;\n  wire                               PROG_EMPTY_FIFO_OUT;\n  wire                               PROG_FULL_FIFO_OUT;\n  wire                               VALID_FIFO_OUT;\n  wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT_FIFO_OUT;\n  wire                               UNDERFLOW_FIFO_OUT;\n  wire                               WR_ACK_FIFO_OUT;\n  wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT_FIFO_OUT;\n\n\n  //***************************************************************************\n  // Internal Signals\n  //   The core uses either the internal_ wires or the preload0_ wires depending\n  //     on whether the core uses Preload0 or not.\n  //   When using preload0, the internal signals connect the internal core to\n  //     the preload logic, and the external core's interfaces are tied to the\n  //     preload0 signals from the preload logic.\n  //***************************************************************************\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_OUT;\n  wire                               VALID_P0_OUT;\n  wire                               EMPTY_P0_OUT;\n  wire                               ALMOSTEMPTY_P0_OUT;\n  reg                                EMPTY_P0_OUT_Q;\n  reg                                ALMOSTEMPTY_P0_OUT_Q;\n  wire                               UNDERFLOW_P0_OUT;\n  wire                               RDEN_P0_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_IN;\n  wire                               EMPTY_P0_IN;\n  reg  [31:0]                        DATA_COUNT_FWFT;\n  reg                                SS_FWFT_WR  ;\n  reg                                SS_FWFT_RD ;\n\n  wire                               sbiterr_fifo_out;\n  wire                               dbiterr_fifo_out;\n  wire                               inject_sbit_err;\n  wire                               inject_dbit_err;\n  wire                               sckt_wr_rst_i;\n  wire                               sckt_rd_rst_i;\n  reg                                sckt_wr_rst_i_q = 1'b0;\n \n  wire                               w_fab_read_data_valid_i;\n  wire                               w_read_data_valid_i;\n  wire                               w_ram_valid_i;\n  // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.\n  assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectsbiterr_delayed : 0;\n  assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectdbiterr_delayed : 0;\n                           \n  assign wr_rst_i_out = wr_rst_i;\n  assign rd_rst_i_out = rd_rst_i;\n  assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];\n  generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o\n    wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;\n    always @ (posedge clk_i)\n      sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; \n  end endgenerate \n// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL\n// parameter (1=Independent Clocks, 0=Common Clock)\n\n  localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;\ngenerate\ncase (C_VERILOG_IMPL)\n0 : begin : block1_ss\n  //Common Clock Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_ss\n  #(\n    .C_FAMILY                            (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                  (C_DATA_COUNT_WIDTH),            \n    .C_DIN_WIDTH                         (C_DIN_WIDTH),                   \n    .C_DOUT_RST_VAL                      (C_DOUT_RST_VAL),                \n    .C_DOUT_WIDTH                        (C_DOUT_WIDTH),                  \n    .C_FULL_FLAGS_RST_VAL                (FULL_FLAGS_RST_VAL),            \n    .C_HAS_ALMOST_EMPTY                  (C_HAS_ALMOST_EMPTY),            \n    .C_HAS_ALMOST_FULL                   ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),             \n    .C_HAS_DATA_COUNT                    (C_HAS_DATA_COUNT),              \n    .C_HAS_OVERFLOW                      (C_HAS_OVERFLOW),                \n    .C_HAS_RD_DATA_COUNT                 (C_HAS_RD_DATA_COUNT),           \n    .C_HAS_RST                           (C_EN_SAFETY_CKT?0:C_HAS_RST),                     \n    .C_HAS_SRST                          (C_EN_SAFETY_CKT?1:C_HAS_SRST),                    \n    .C_HAS_UNDERFLOW                     (C_HAS_UNDERFLOW),               \n    .C_HAS_VALID                         (C_HAS_VALID),                   \n    .C_HAS_WR_ACK                        (C_HAS_WR_ACK),                  \n    .C_HAS_WR_DATA_COUNT                 (C_HAS_WR_DATA_COUNT),           \n    .C_IMPLEMENTATION_TYPE               (C_IMPLEMENTATION_TYPE),         \n    .C_MEMORY_TYPE                       (C_MEMORY_TYPE),                 \n    .C_OVERFLOW_LOW                      (C_OVERFLOW_LOW),                \n    .C_PRELOAD_LATENCY                   (C_PRELOAD_LATENCY),             \n    .C_PRELOAD_REGS                      (C_PRELOAD_REGS),                \n    .C_PROG_EMPTY_THRESH_ASSERT_VAL      (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL      (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                   (C_PROG_EMPTY_TYPE),             \n    .C_PROG_FULL_THRESH_ASSERT_VAL       (C_PROG_FULL_THRESH_ASSERT_VAL), \n    .C_PROG_FULL_THRESH_NEGATE_VAL       (C_PROG_FULL_THRESH_NEGATE_VAL), \n    .C_PROG_FULL_TYPE                    (C_PROG_FULL_TYPE),              \n    .C_RD_DATA_COUNT_WIDTH               (C_RD_DATA_COUNT_WIDTH),         \n    .C_RD_DEPTH                          (C_RD_DEPTH),                    \n    .C_RD_PNTR_WIDTH                     (C_RD_PNTR_WIDTH),               \n    .C_UNDERFLOW_LOW                     (C_UNDERFLOW_LOW),               \n    .C_USE_DOUT_RST                      (C_USE_DOUT_RST),                \n    .C_USE_EMBEDDED_REG                  (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                     (C_EN_SAFETY_CKT),            \n    .C_USE_FWFT_DATA_COUNT               (C_USE_FWFT_DATA_COUNT),         \n    .C_VALID_LOW                         (C_VALID_LOW),                   \n    .C_WR_ACK_LOW                        (C_WR_ACK_LOW),                  \n    .C_WR_DATA_COUNT_WIDTH               (C_WR_DATA_COUNT_WIDTH),         \n    .C_WR_DEPTH                          (C_WR_DEPTH),                    \n    .C_WR_PNTR_WIDTH                     (C_WR_PNTR_WIDTH),               \n    .C_USE_ECC                           (C_USE_ECC),                     \n    .C_ENABLE_RST_SYNC                   (C_ENABLE_RST_SYNC),             \n    .C_ERROR_INJECTION_TYPE              (C_ERROR_INJECTION_TYPE),\n    .C_FIFO_TYPE                         (C_FIFO_TYPE)                     \n  )\n  gen_ss\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .CLK                      (CLK),\n    .RST                      (C_EN_SAFETY_CKT?1'b0:rst_i),\n    .SRST                     (C_EN_SAFETY_CKT?sckt_wr_rst_i:srst_delayed),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .USER_EMPTY_FB            (empty_fb),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .DATA_COUNT               (DATA_COUNT_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .WR_RST_BUSY              (wr_rst_busy),\n    .RD_RST_BUSY              (rd_rst_busy),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n1 : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT), \n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .fab_read_data_valid_i    (w_fab_read_data_valid_i),\n    .read_data_valid_i        (w_read_data_valid_i),\n    .ram_valid_i              (w_ram_valid_i),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\n2 : begin : ll_afifo_inst\n  fifo_generator_v13_2_5_beh_ver_ll_afifo\n  #(\n    .C_DIN_WIDTH                    (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                 (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                   (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_RD_DATA_COUNT            (C_HAS_RD_DATA_COUNT),\n    .C_HAS_WR_DATA_COUNT            (C_HAS_WR_DATA_COUNT),\n    .C_RD_DEPTH                     (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                (C_RD_PNTR_WIDTH),\n    .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n    .C_WR_DATA_COUNT_WIDTH          (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                     (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                (C_WR_PNTR_WIDTH),\n    .C_FIFO_TYPE                    (C_FIFO_TYPE)\n   )\n  gen_ll_afifo\n  (\n    .DIN                        (din_delayed),\n    .RD_CLK                     (RD_CLK),\n    .RD_EN                      (rd_en_delayed),\n    .WR_RST                     (wr_rst_i),\n    .RD_RST                     (rd_rst_i),\n    .WR_CLK                     (WR_CLK),\n    .WR_EN                      (wr_en_delayed),\n    .DOUT                       (DOUT),\n    .EMPTY                      (EMPTY),\n    .FULL                       (FULL)\n  );\nend\ndefault : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT),\n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\nendcase\nendgenerate\n\n\n   //**************************************************************************\n   // Connect Internal Signals\n   //   (Signals labeled internal_*)\n   //  In the normal case, these signals tie directly to the FIFO's inputs and\n   //    outputs.\n   //  In the case of Preload Latency 0 or 1, there are intermediate\n   //    signals between the internal FIFO and the preload logic.\n   //**************************************************************************\n   \n   \n   //***********************************************\n   // If First-Word Fall-Through, instantiate\n   // the preload0 (FWFT) module\n   //***********************************************\n   wire                        rd_en_to_fwft_fifo;\n   wire                        sbiterr_fwft;\n   wire                        dbiterr_fwft;\n   wire [C_DOUT_WIDTH-1:0]     dout_fwft;\n   wire                        empty_fwft;\n   wire                        rd_en_fifo_in;\n   wire                        stage2_reg_en_i;\n   wire [1:0]                  valid_stages_i;\n   wire                        rst_fwft;\n   //wire                        empty_p0_out;\n   reg  [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n   localparam IS_PKT_FIFO      = (C_FIFO_TYPE == 1) ? 1 : 0;\n   localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;\n   assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2_fwft\n\n\n         fifo_generator_v13_2_5_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_EMBEDDED_REG  (C_USE_EMBEDDED_REG),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (C_FIFO_TYPE)\n             )\n             fgpl0\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (RST_P0_IN),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (RD_EN_P0_IN),\n                .FIFOEMPTY        (EMPTY_P0_IN),\n                .FIFODATA         (DATA_P0_IN),\n                .FIFOSBITERR      (sbiterr_fifo_out),\n                .FIFODBITERR      (dbiterr_fifo_out),\n                // Output\n                .USERDATA         (dout_fwft),\n                .USERVALID        (VALID_P0_OUT),\n                .USEREMPTY        (empty_fwft),\n                .USERALMOSTEMPTY  (ALMOSTEMPTY_P0_OUT),\n                .USERUNDERFLOW    (UNDERFLOW_P0_OUT),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_fifo_in),\n                .USERSBITERR      (sbiterr_fwft),\n                .USERDBITERR      (dbiterr_fwft),\n                .STAGE2_REG_EN    (stage2_reg_en_i),\n                .fab_read_data_valid_i_o    (w_fab_read_data_valid_i),\n                .read_data_valid_i_o        (w_read_data_valid_i),\n                .ram_valid_i_o              (w_ram_valid_i),\n                .VALID_STAGES                (valid_stages_i)\n                );\n\n         \n         //***********************************************\n         // Connect inputs to preload (FWFT) module\n         //***********************************************\n         //Connect the RD_CLK of the Preload (FWFT) module to CLK if we \n         // have a common-clock FIFO, or RD_CLK if we have an \n         // independent clock FIFO\n         assign RD_CLK_P0_IN       = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);\n         assign RST_P0_IN          = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;\n         assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n         assign EMPTY_P0_IN        = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;\n         assign DATA_P0_IN         = DOUT_FIFO_OUT;\n         \n         //***********************************************\n         // Connect outputs from preload (FWFT) module\n         //***********************************************\n         assign VALID              = VALID_P0_OUT ;\n         assign ALMOST_EMPTY       = ALMOSTEMPTY_P0_OUT;\n         assign UNDERFLOW          = UNDERFLOW_P0_OUT ;\n         \n         assign RD_EN_FIFO_IN      = rd_en_fifo_in;\n         \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:\n           (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : \n           DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];  \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               EMPTY_P0_OUT_Q       <= 1;\n               ALMOSTEMPTY_P0_OUT_Q <= 1;\n            end else begin\n               EMPTY_P0_OUT_Q       <= #`TCQ empty_p0_out;\n//               EMPTY_P0_OUT_Q       <= #`TCQ EMPTY_FIFO_OUT;\n               ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;\n            end\n         end //always\n         \n         \n         //***********************************************\n         // logic for common-clock data count when FWFT is selected\n         //***********************************************\n         initial begin\n            SS_FWFT_RD = 1'b0;\n            DATA_COUNT_FWFT = 0 ;\n            SS_FWFT_WR   = 1'b0 ;\n         end //initial\n         \n         \n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter. SS_FWFT_WR and SS_FWFT_RD\n         // are the up/down enables for the counter.\n         //***********************************************\n         always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin\n            if (C_VALID_LOW == 1) begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;\n            end else begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;\n            end\n            SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT))  ;\n         end \n\n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter for FWFT. This always block \n         // calculates the counter.\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               DATA_COUNT_FWFT      <= 0;\n            end else begin\n               //if (srst_delayed && (C_HAS_SRST == 1) ) begin\n               if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin\n                  DATA_COUNT_FWFT      <= #`TCQ 0;\n               end else begin\n                  case ( {SS_FWFT_WR, SS_FWFT_RD})\n                    2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                    2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;\n                    2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;\n                    2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                  endcase  \n               end //if SRST\n            end //IF RST\n         end //always\n\n      end endgenerate // : block2\n\n    // AXI Streaming Packet FIFO\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_plus1 = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_reg   = 0;\n    reg                         partial_packet     = 0;\n    reg                         stage1_eop_d1      = 0;\n    reg                         rd_en_fifo_in_d1   = 0;\n    reg                         eop_at_stage2      = 0;\n    reg                         ram_pkt_empty      = 0;\n    reg                         ram_pkt_empty_d1   = 0;\n\n    wire [C_DOUT_WIDTH-1:0]     dout_p0_out;\n    wire                        packet_empty_wr;\n    wire                        wr_rst_fwft_pkt_fifo;\n    wire                        dummy_wr_eop;\n    wire                        ram_wr_en_pkt_fifo;\n    wire                        wr_eop;\n    wire                        ram_rd_en_compare;\n    wire                        stage1_eop;\n    wire                        pkt_ready_to_read;\n    wire                        rd_en_2_stage2;\n\n    // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)\n    // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP\n    // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of\n    // write packet count\n    generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop\n       always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n          if (wr_rst_fwft_pkt_fifo)\n             partial_packet   <= 1'b0;\n          else begin\n             if (srst_delayed | wr_rst_busy | rd_rst_busy)\n                partial_packet <= #`TCQ 1'b0;\n             else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))\n                partial_packet <= #`TCQ 1'b1;\n             else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)\n                partial_packet <= #`TCQ 1'b0;\n          end\n        end\n    end endgenerate // gdummy_wr_eop\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin : gpkt_fifo_fwft\n      assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;\n      assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);\n      assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];\n  \n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft) begin\n          stage1_eop_d1    <= 1'b0;\n          rd_en_fifo_in_d1 <= 1'b0;\n        end else begin\n          if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            stage1_eop_d1    <= #`TCQ 1'b0;\n            rd_en_fifo_in_d1 <= #`TCQ 1'b0;\n          end else begin\n            stage1_eop_d1    <= #`TCQ stage1_eop;\n            rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;\n          end\n        end\n      end\n      assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;\n      assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);\n      assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);\n      assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;\n\n\n         fifo_generator_v13_2_5_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (2) // Enable low latency fwft logic\n             )\n         pkt_fifo_fwft\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (rst_fwft),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (rd_en_delayed),\n                .FIFOEMPTY        (pkt_ready_to_read),\n                .FIFODATA         (dout_fwft),\n                .FIFOSBITERR      (sbiterr_fwft),\n                .FIFODBITERR      (dbiterr_fwft),\n                // Output\n                .USERDATA         (dout_p0_out),\n                .USERVALID        (),\n                .USEREMPTY        (empty_p0_out),\n                .USERALMOSTEMPTY  (),\n                .USERUNDERFLOW    (),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_2_stage2),\n                .USERSBITERR      (SBITERR),\n                .USERDBITERR      (DBITERR),\n                .STAGE2_REG_EN    (),\n                .VALID_STAGES     ()\n                );\n\n      assign pkt_ready_to_read  = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));\n      assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft)\n          eop_at_stage2 <= 1'b0;\n        else if (stage2_reg_en_i)\n          eop_at_stage2 <= #`TCQ stage1_eop;\n      end\n\n      //---------------------------------------------------------------------------\n      // Write and Read Packet Count\n      //---------------------------------------------------------------------------\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count  <= 0;\n         else if (srst_delayed  | wr_rst_busy | rd_rst_busy)\n            wr_pkt_count  <= #`TCQ 0;\n         else if (wr_eop)\n            wr_pkt_count  <= #`TCQ wr_pkt_count + 1;\n      end\n    \n    end endgenerate //: gpkt_fifo_fwft\n\n    assign DOUT               = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;\n    assign EMPTY              = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            rd_pkt_count       <= 0;\n            rd_pkt_count_plus1 <= 1;\n         end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            rd_pkt_count       <= #`TCQ 0;\n            rd_pkt_count_plus1 <= #`TCQ 1;\n         end else if (stage2_reg_en_i && stage1_eop) begin\n            rd_pkt_count       <= #`TCQ rd_pkt_count + 1;\n            rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;\n         end\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (SRST | wr_rst_busy | rd_rst_busy) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n    end endgenerate //grss_pkt_cnt\n    \n    localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;\n    reg  [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_b2g = 0;\n    wire [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_rd;\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt\n      // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count_b2g  <= 0;\n         else\n            wr_pkt_count_b2g  <= #`TCQ wr_pkt_count;\n      end\n\n      // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            wr_pkt_count_q       <= 0;\n         else\n            wr_pkt_count_q       <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};\n      end\n\n      always @* begin\n        if (stage1_eop)\n           rd_pkt_count    <= rd_pkt_count_reg + 1;\n        else\n           rd_pkt_count    <= rd_pkt_count_reg;\n      end\n\n      assign wr_pkt_count_rd    = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            rd_pkt_count_reg       <= 0;\n         else if (rd_en_fifo_in)\n            rd_pkt_count_reg       <= #`TCQ rd_pkt_count;\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (rd_pkt_count != wr_pkt_count_rd) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n\n      // Synchronize the empty in write domain\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            pkt_empty_sync  <= 'b1;\n         else\n            pkt_empty_sync  <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};\n      end\n\n    end endgenerate //gras_pkt_cnt\n\n   generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO\n\n     //***********************************************\n     // If NOT First-Word Fall-Through, wire the outputs\n     // of the internal _ss or _as FIFO directly to the\n     // output, and do not instantiate the preload0\n     // module.\n     //***********************************************\n\n     assign RD_CLK_P0_IN       = 0;\n     assign RST_P0_IN          = 0;\n     assign RD_EN_P0_IN        = 0;\n\n     assign RD_EN_FIFO_IN      = rd_en_delayed;\n\n     assign DOUT               = DOUT_FIFO_OUT;\n     assign DATA_P0_IN         = 0;\n     assign VALID              = VALID_FIFO_OUT;\n     assign EMPTY              = EMPTY_FIFO_OUT;\n     assign ALMOST_EMPTY       = ALMOST_EMPTY_FIFO_OUT;\n     assign EMPTY_P0_IN        = 0;\n     assign UNDERFLOW          = UNDERFLOW_FIFO_OUT;\n     assign DATA_COUNT         = DATA_COUNT_FIFO_OUT;\n     assign SBITERR            = sbiterr_fifo_out;\n     assign DBITERR            = dbiterr_fifo_out;\n\n   end endgenerate // STD_FIFO\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO\n     assign empty_p0_out       = empty_fwft;\n     assign SBITERR            = sbiterr_fwft;\n     assign DBITERR            = dbiterr_fwft;\n     assign DOUT               = dout_fwft;\n     assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n\n   end endgenerate // NO_PKT_FIFO\n\n   //***********************************************\n   // Connect user flags to internal signals\n   //***********************************************\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3\n      if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);\n      end //block_ic\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3\n   endgenerate\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30\n       if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30\n   endgenerate\n\n\n    \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both\n       if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30_both\n   endgenerate\n\n generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both\n      if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));\n      end //block_ic_both\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3_both\n   endgenerate\n\n\n   //If we are not using extra logic for the FWFT data count,\n   //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the\n   //internal FIFO instance  \n   generate\n      if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n   //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal\n   //FIFO instance\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1) begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n      else begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n\n   //Connect other flags to the internal FIFO instance\n   assign       FULL        = FULL_FIFO_OUT;\n   assign       ALMOST_FULL = ALMOST_FULL_FIFO_OUT;\n   assign       WR_ACK      = WR_ACK_FIFO_OUT;\n   assign       OVERFLOW    = OVERFLOW_FIFO_OUT;\n   assign       PROG_FULL   = PROG_FULL_FIFO_OUT;\n   assign       PROG_EMPTY  = PROG_EMPTY_FIFO_OUT;\n\n\n  /**************************************************************************\n  * find_log2\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n   // if an asynchronous FIFO has been selected, display a message that the FIFO\n   //   will not be cycle-accurate in simulation\n   initial begin\n      if (C_IMPLEMENTATION_TYPE == 2) begin\n         $display(\"WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.\");\n      end else if (C_MEMORY_TYPE == 4) begin\n         $display(\"FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.\");\n         $finish;\n      end\n\n      if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin\n         $display(\"FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.\");\n         $finish;\n      end\n\n      if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin\n         $display(\"FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.\");\n         $finish;\n      end\n\n      if (C_USE_ECC == 1) begin\n         if (C_DIN_WIDTH != C_DOUT_WIDTH) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.\");\n            $finish;\n         end\n         if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.\");\n            $finish;\n         end\n      end\n\n   end //initial\n\n  /**************************************************************************\n  * Internal reset logic\n  **************************************************************************/\n  assign wr_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg|sckt_wr_rst_i : 0;\n  assign rd_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg|sckt_rd_rst_i : 0;\n  assign rst_i            = C_HAS_RST ? rst_reg|sckt_wr_rst_i : 0;\n\n  wire rst_2_sync;\n  wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;\n\n  localparam RST_SYNC_STAGES = C_EN_SAFETY_CKT == 0 ? C_COMMON_CLOCK ? C_SYNCHRONIZER_STAGE : C_SYNCHRONIZER_STAGE+2 : 5;\n  localparam RST_BUSY_LEN    = 4;\n  reg  wr_rst_busy_i = 0;\n  reg  rd_rst_busy_i = 0;\n  generate\n      if (C_ENABLE_RST_SYNC == 0 || (C_HAS_RST == 0 && C_HAS_SRST == 0)) begin : gnrst_sync\n        always @* begin\n          wr_rst_reg <= wr_rst_delayed;\n          rd_rst_reg <= rd_rst_delayed;\n          rst_reg    <= 1'b0;\n          srst_reg    <= 1'b0;\n        end\n        assign rst_2_sync = wr_rst_delayed;\n        assign wr_rst_busy = 1'b0;\n        assign wr_rst_busy_o = 1'b0;\n        assign rd_rst_busy = 1'b0;\n        assign sckt_wr_rst_i = 1'b0;\n        assign sckt_rd_rst_i = 1'b0;\n      end // gnrst_sync\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 0) begin : g7s_ic_rst_nsckt\n        reg [1:0]                 arst_sync_wr  = 2'b11;\n        reg [1:0]                 arst_sync_rd  = 2'b11;\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge WR_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge RD_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_rd    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_rd    <= #`TCQ {arst_sync_rd[0], rst_delayed};\n        end\n        always @(posedge WR_CLK) begin\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n\tend\n        always @(posedge WR_CLK or posedge arst_sync_wr[1]) begin\n\t  if (arst_sync_wr[1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n            rd_rst_wr_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            rd_rst_wr_ext  <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t    if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t      sckt_wr_rst_ic <= #`TCQ 1'b0;\n            else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t      wr_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n        always @(posedge RD_CLK) begin\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], sckt_wr_rst_ic};\n\tend\n        always @(posedge RD_CLK or posedge arst_sync_rd[1]) begin\n\t  if (arst_sync_rd[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n            wr_rst_rd_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            wr_rst_rd_ext  <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t    if (wr_rst_rd_ext[1]) begin\n\t      sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t      rd_rst_busy_i  <= #`TCQ 1'b0;\n\t    end\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic|arst_sync_wr[1];\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic|arst_sync_rd[1];\n      end // g7s_ic_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 1) begin : g7s_ic_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] arst_sync_rd  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        always @(posedge WR_CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n          rd_rst_wr_ext    <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_wr[RST_SYNC_STAGES-1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n          end else if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t    sckt_wr_rst_ic <= #`TCQ 1'b0;\n          else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t    wr_rst_busy_i  <= #`TCQ 1'b0;\n\tend\n        always @(posedge RD_CLK) begin\n\t  arst_sync_rd     <= #`TCQ {arst_sync_rd[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n          wr_rst_rd_ext    <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_rd[RST_SYNC_STAGES-1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n\t  end else if (wr_rst_rd_ext[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t    rd_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic;\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic;\n      end // g7s_ic_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 0) begin : g7s_cc_rst_nsckt\n        reg [1:0]              arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge CLK) begin\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0] | arst_sync_wr[1]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc | arst_sync_wr[1];\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 1) begin : g7s_cc_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n\n        always @(posedge CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc;\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst\n        assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;\n        assign rd_rst_busy = rst_reg;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = rst_reg;\n        always @* rst_full_ff_i  <= 1'b0;\n        always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;\n\n        always @(posedge CLK) begin\n          rst_delayed_d1 <= #`TCQ srst_delayed;\n          rst_delayed_d2 <= #`TCQ rst_delayed_d1;\n          if (rst_reg || rst_delayed_d2) begin\n            rst_active_i <= #`TCQ 1'b1;\n          end else begin\n            rst_active_i <= #`TCQ rst_reg;\n          end    \n        end   \n        always @(posedge CLK) begin\n          if (~rst_reg && srst_delayed) begin\n             rst_reg <= #`TCQ 1'b1;\n           end else if (rst_reg) begin\n             rst_reg <= #`TCQ 1'b0;\n           end else begin\n             rst_reg <= #`TCQ rst_reg;\n           end    \n        end   \n      end // g8s_cc_rst\n      else if (IS_8SERIES != 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_srst\n        assign wr_rst_busy = srst_delayed;\n        assign rd_rst_busy = srst_delayed;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = srst_delayed;\n        always @* rst_full_ff_i  <= 1'b0;\n      end // g7s_cc_srst\n  endgenerate \n\n  reg rst_d1 = 1'b0;\n  reg rst_d2 = 1'b0;\n  reg rst_d3 = 1'b0;\n  reg rst_d4 = 1'b0;\n  generate\n    if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1\n    // RST_FULL_GEN replaces the reset falling edge detection used to de-assert\n    // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.\n\n    // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &\n    // PROG_FULL\n\n      always @ (posedge rst_2_sync or posedge clk_2_sync) begin\n        if (rst_2_sync && C_EN_SAFETY_CKT == 0) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          rst_d3         <= 1'b1;\n          rst_d4         <= 1'b0;\n        end else begin\n          if (srst_delayed) begin\n            rst_d1         <= #`TCQ 1'b1;\n            rst_d2         <= #`TCQ 1'b1;\n            rst_d3         <= #`TCQ 1'b1;\n            rst_d4         <= #`TCQ 1'b0;\n          end else begin\n            rst_d1         <= #`TCQ wr_rst_busy;//1'b0;\n            rst_d2         <= #`TCQ rst_d1;\n            rst_d3         <= #`TCQ rst_d2 | sckt_wr_rst_i;\n            rst_d4         <= #`TCQ rst_d3;\n          end\n        end\n      end\n\n      always @* rst_full_ff_i  <= C_HAS_SRST ? 1'b0 : rst_d2 | sckt_wr_rst_i;\n      always @* rst_full_gen_i <= C_HAS_SRST ? rst_d4 : rst_d3;\n\n    end else if (C_EN_SAFETY_CKT == 1 && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full_sckt\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end\n  endgenerate // grstd1\n\nendmodule //fifo_generator_v13_2_5_CONV_VER\n\n\nmodule fifo_generator_v13_2_5_sync_stage\n  #(\n    parameter  C_WIDTH          = 10\n   )\n   (\n    input                     RST,\n    input                     CLK,\n    input       [C_WIDTH-1:0] DIN,\n    output reg  [C_WIDTH-1:0] DOUT = 0\n   );\n   always @ (posedge RST or posedge CLK) begin\n     if (RST)\n       DOUT <= 0;\n     else\n       DOUT <= #`TCQ DIN;\n   end\nendmodule // fifo_generator_v13_2_5_sync_stage\n\n/*******************************************************************************\n * Declaration of Independent-Clocks FIFO Module\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_as\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2 \n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input                                         SAFETY_CKT_WR_RST,\n   input                                         SAFETY_CKT_RD_RST,\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_ASSERT,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_NEGATE,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_ASSERT,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_NEGATE,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         RD_EN_USER,\n   input                                         RST,\n   input                                         RST_FULL_GEN,\n   input                                         RST_FULL_FF,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   input                                         INJECTDBITERR,\n   input                                         INJECTSBITERR,\n   input                                         USER_EMPTY_FB,\n   input                                         fab_read_data_valid_i,\n   input                                         read_data_valid_i,\n   input                                         ram_valid_i,\n   output reg                                    ALMOST_EMPTY = 1'b1,\n   output reg                                    ALMOST_FULL = C_FULL_FLAGS_RST_VAL,\n   output      [C_DOUT_WIDTH-1:0]                DOUT,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    EMPTY_FB = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL,\n   output                                        OVERFLOW,\n   output                                        PROG_EMPTY,\n   output                                        PROG_FULL,\n   output                                        VALID,\n   output      [C_RD_DATA_COUNT_WIDTH-1:0]       RD_DATA_COUNT,\n   output                                        UNDERFLOW,\n   output                                        WR_ACK,\n   output      [C_WR_DATA_COUNT_WIDTH-1:0]       WR_DATA_COUNT,\n   output                                        SBITERR,\n   output                                        DBITERR\n  );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   \n  \n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   \n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;\n   // Array that holds the error injection type (single/double bit error) on \n   // a specific write operation, which is returned on read to corrupt the\n   // output data.\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   //The amount of data stored in the FIFO at any time is given\n   // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK\n   // domain.\n   //num_wr_bits is calculated by considering the total words in the FIFO,\n   // and the state of the read pointer (which may not have yet crossed clock\n   // domains.)\n   //num_rd_bits is calculated by considering the total words in the FIFO,\n   // and the state of the write pointer (which may not have yet crossed clock\n   // domains.)\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   wire                        wr_rst_i = WR_RST;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n   wire                        rd_rst_i = RD_RST;\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n\n\n\n   // Delayed ram_rd_en is needed only for STD Embedded register option\n   generate\n     if (C_PRELOAD_LATENCY == 2) begin : grd_d\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n       end\n     end\n   endgenerate\n   \n    generate\n     if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n           fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n       end\n     end\n   endgenerate\n\n  \n\n   // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;\n     end else begin : rdl // Read depth lesser than or equal to write depth\n       assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n     end\n   endgenerate\n\n   // Generate Empty and Almost Empty\n  // ram_rd_en used to determine EMPTY should depend on the EMPTY.\n   assign ram_rd_en        = RD_EN & !EMPTY;\n   assign empty_int        = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));\n   assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));\n\n   // Register Empty and Almost Empty\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else begin\n         rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};\n\n         if (empty_int)\n           EMPTY           <= #`TCQ 1'b1;\n         else\n           EMPTY           <= #`TCQ 1'b0;\n\n         if (!EMPTY) begin\n           if (almost_empty_int)\n             ALMOST_EMPTY  <= #`TCQ 1'b1;\n           else\n             ALMOST_EMPTY  <= #`TCQ 1'b0;\n         end\n       end // rd_rst_i\n     end // always\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY_FB     <= 1'b1;\n       end else begin\n         if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else if (empty_int)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else\n           EMPTY_FB   <= #`TCQ 1'b0;\n       end // rd_rst_i\n     end // always\n\n   // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;\n     end else begin : wdl // Write depth lesser than or equal to read depth\n       assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n     end\n   endgenerate\n\n  // Generate FULL and ALMOST_FULL\n  // ram_wr_en used to determine FULL should depend on the FULL.\n  assign ram_wr_en       = WR_EN & !FULL;\n  assign full_int        = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));\n  assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));\n\n   // Register FULL and ALMOST_FULL Empty\n   always @ (posedge WR_CLK or posedge RST_FULL_FF)\n     begin\n       if (RST_FULL_FF & C_HAS_RST) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else begin\n         if (full_int) begin\n           FULL           <= #`TCQ 1'b1;\n         end else begin\n           FULL           <= #`TCQ 1'b0;\n         end\n\n         if (RST_FULL_GEN) begin\n           ALMOST_FULL    <= #`TCQ 1'b0;\n         end else if (!FULL) begin\n           if (almost_full_int)\n             ALMOST_FULL  <= #`TCQ 1'b1;\n           else\n             ALMOST_FULL  <= #`TCQ 1'b0;\n         end\n       end // wr_rst_i\n     end // always\n   always @ (posedge WR_CLK or posedge wr_rst_i)\n     begin\n       if (wr_rst_i) begin\n         wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};\n       end else begin\n         wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};\n       end // wr_rst_i\n     end // always\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i) begin\n           stage1_valid     <= 0;\n           stage2_valid     <= 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n   //Pointers passed into opposite clock domain\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_EMPTY.\n   wire [31:0] num_read_words_pe = \n     num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_FULL.\n   wire [31:0] num_write_words_pf =\n     num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n    \n    \n   /***************************************************************************\n    * Internal registers and wires\n    **************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire [C_DOUT_WIDTH-1:0] ideal_dout_out;      \n   wire valid_i;\n   wire valid_out1;\n   wire valid_out2;\n   wire valid_out;  \n   wire underflow_i;\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]               err_type                 = 0;\n   reg [1:0]               err_type_d1              = 0;\n   reg [1:0]               err_type_both              = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout               = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_d1            = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_both            = 0;\n   reg                     ideal_wr_ack             = 0;\n   reg                     ideal_valid              = 0;\n   reg                     ideal_overflow           = C_OVERFLOW_LOW;\n   reg                     ideal_underflow          = C_UNDERFLOW_LOW;\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   reg         valid_d1     = 0;\n   reg         valid_d2     = 0; \n   \n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n   \n\n  /****************************************************************************\n   * Function Declarations\n   ***************************************************************************/\n\n  /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n      if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n    end\n  endtask\n\n  /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n  /***********************************************************************\n  * hexstr_conv\n  *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n  ***********************************************************************/\n  function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_d2           = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n    end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the \n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n    wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;   \n   wire RD_CLK;\n   wire RD_EN;\n   wire RST;\n   wire WR_CLK;\n   wire WR_EN;\n    */\n\n   //***************************************************************************\n   // Dout may change behavior based on latency\n   //***************************************************************************\n   assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?\n                         ideal_dout_d1: ideal_dout;   \n   assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; \n\n   //***************************************************************************\n   // Assign SBITERR and DBITERR based on latency \n   //***************************************************************************\n   assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                    (C_PRELOAD_LATENCY == 2 &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?\n                    err_type_d1[0]: err_type[0]; \n   assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                    (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                    err_type_d1[1]: err_type[1]; \n  \n   //***************************************************************************\n   // Safety-ckt logic with embedded reg/fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n       //  if (C_HAS_VALID == 1) begin\n       //       assign valid_out = valid_d1;\n       //  end\n             \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)\n          begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else \n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n          end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                  @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n           end\n           else begin\n                   if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                   end\n             end \n           end  \n      end \n      endgenerate   \n\n//***************************************************************************\n   // Safety-ckt logic with embedded reg + fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else begin\n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n               fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n          end\n        end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   ideal_dout_both <= #`TCQ dout_reset_val;\n              end\n           end else begin\n             if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n              \n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n             end\n           end \n         end      \n      end \n      endgenerate    \n \n   //***************************************************************************\n   // Overflow may be active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_OVERFLOW==1) begin : blockOF1\n   assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n      end\n   endgenerate\n\n   assign PROG_EMPTY = ideal_prog_empty;\n   assign PROG_FULL  = ideal_prog_full;\n\n   //***************************************************************************\n   // Valid may change behavior based on latency or active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_VALID==1) begin : blockVL1\n   assign valid_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;\n   assign valid_out1 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?\n                       valid_d1: valid_i;  \n   assign valid_out2 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?\n                       valid_d2: valid_i; \n   assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;\n   assign VALID     = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Underflow may change behavior based on latency or active-low   \n   //***************************************************************************\n   generate\n      if (C_HAS_UNDERFLOW==1) begin : blockUF1\n   assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;\n   assign UNDERFLOW   = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n    end\n   endgenerate\n\n   //***************************************************************************\n   // Write acknowledge may be active low\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_ACK==1) begin : blockWK1\n   assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext\n\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_wr_pntr = 0;\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_rd_pntr = 0;\n      wire [C_PNTR_WIDTH-1:0]  diff_wr_rd_tmp;\n      wire [C_PNTR_WIDTH:0]    diff_wr_rd;\n      reg  [C_PNTR_WIDTH:0]    wr_data_count_i  = 0;\n        always @* begin\n          if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = 0;\n            adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n          end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin\n            adjusted_rd_pntr = rd_pntr_wr;\n            adjusted_wr_pntr = 0;\n            adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n          end else begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = rd_pntr_wr;\n          end\n        end // always @*\n\n        assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;\n        assign diff_wr_rd     = {1'b0,diff_wr_rd_tmp};\n\n        always @ (posedge wr_rst_i or posedge WR_CLK)\n        begin\n            if (wr_rst_i)\n              wr_data_count_i <= 0;\n            else\n              wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;\n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n\n        always @* begin\n          if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];\n          else\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n        end // always @*\n      end // wdc_fwft_ext\n   endgenerate\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   reg  [C_RD_PNTR_WIDTH:0]    rdc_fwft_ext_as  = 0;\n\n   generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n\n\n   always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= 0;\n            end else begin\n              if (!stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 0;\n              else if (!stage1_valid && stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 1;\n              else\n                rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;\n            end \n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n      end // rdc_fwft_ext\n end\n   endgenerate\n\n\n  generate if (C_USE_EMBEDDED_REG == 3) begin\n     if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n        wire [C_RD_PNTR_WIDTH:0]  diff_rd_wr_1;\n   //     assign diff_rd_wr_1 = diff_rd_wr +2'h2;\n\n       always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= #`TCQ 0;\n            end else begin\n          //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))\n          //    rdc_fwft_ext_as <= 1'b0;\n          //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) \n          //    rdc_fwft_ext_as <= 1'b1;\n          //else\n            rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;\n        end\n\n\n\nend\nend\nend\nendgenerate\n          \n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1) begin : grdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?\n          rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :\n          rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?\n          wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :\n          wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n\n  /**************************************************************************\n  * Assorted registers for delayed versions of signals\n  **************************************************************************/\n  //Capture delayed version of valid\n  generate\n      if (C_HAS_VALID==1) begin : blockVL2\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n      valid_d1 <= 1'b0;\n      valid_d2 <= 1'b0;\n    end else begin\n      valid_d1 <= #`TCQ valid_i;\n      valid_d2 <= #`TCQ valid_d1;\n    end \n//    if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin\n  //      valid_d2 <= #`TCQ valid_d1;\n      //  end \n  end \n      end\n endgenerate  \n   \n  //Capture delayed version of dout\n  /**************************************************************************\n    *embedded/fabric reg with no safety ckt\n    **************************************************************************/\n  generate \n       if (C_USE_EMBEDDED_REG < 3) begin\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n       if (C_USE_DOUT_RST == 1'b1) begin\n         @(posedge RD_CLK)\n           ideal_dout_d1   <= #`TCQ dout_reset_val;\n           ideal_dout   <= #`TCQ dout_reset_val;\n       end\n      // Reset err_type only if ECC is not selected\n      if (C_USE_ECC == 0)\n        err_type_d1     <= #`TCQ 0;\n     end else if (ram_rd_en_d1) begin\n      ideal_dout_d1   <= #`TCQ ideal_dout;\n      err_type_d1     <= #`TCQ err_type;\n           end    \n  end  \n   \nend  \nendgenerate \n/**************************************************************************\n    *embedded + fabric reg with no safety ckt\n    **************************************************************************/\n\ngenerate \n  if (C_USE_EMBEDDED_REG == 3) begin\n    always @(posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i == 1'b1) begin\n        if (C_USE_DOUT_RST == 1'b1) begin\n           @(posedge RD_CLK)\n             ideal_dout    <= #`TCQ dout_reset_val;\n             ideal_dout_d1   <= #`TCQ dout_reset_val;\n             ideal_dout_both   <= #`TCQ dout_reset_val;\n        end\n        // Reset err_type only if ECC is not selected\n        if (C_USE_ECC == 0) begin\n          err_type_d1     <= #`TCQ 0;\n          err_type_both   <= #`TCQ 0;\n        end\n      end else begin\n         if (ram_rd_en_d1) begin\n           ideal_dout_both   <= #`TCQ ideal_dout;\n           err_type_both     <= #`TCQ err_type;\n         end    \n         if (fab_rd_en_d1) begin\n           ideal_dout_d1   <= #`TCQ ideal_dout_both;\n           err_type_d1     <= #`TCQ err_type_both;\n         end\n      end\n    end  \n  end  \nendgenerate \n\n  \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate\n     if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n       always @(posedge WR_CLK) begin\n         ideal_overflow    <= #`TCQ WR_EN & FULL;\n       end\n     end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n       always @(posedge WR_CLK) begin\n         //ideal_overflow    <= #`TCQ WR_EN & (FULL | wr_rst_i);\n         ideal_overflow    <= #`TCQ WR_EN & (FULL );\n       end\n     end\n   endgenerate\n\n   generate\n     if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ EMPTY & RD_EN;\n       end\n     end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ (EMPTY) & RD_EN;\n         //ideal_underflow    <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;\n       end\n     end\n   endgenerate\n\n   /**************************************************************************\n   * Write/Read Pointer Synchronization\n   **************************************************************************/\n   localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;\n   wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   genvar gss;\n\n   generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (C_WR_PNTR_WIDTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_i), \n         .CLK      (RD_CLK), \n         .DIN      (wr_pntr_sync_stgs[gss-1]), \n         .DOUT     (wr_pntr_sync_stgs[gss])\n        );\n \n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (C_RD_PNTR_WIDTH)\n        )\n     wr_stg_inst\n        (\n         .RST      (wr_rst_i), \n         .CLK      (WR_CLK), \n         .DIN      (rd_pntr_sync_stgs[gss-1]), \n         .DOUT     (rd_pntr_sync_stgs[gss])\n        );\n   end endgenerate // Sync_stage_inst\n\n   assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;\n   assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;\n   always@* begin\n     wr_pntr_rd           <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n     rd_pntr_wr           <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n   end\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp\n     if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)\n       wr_pntr           <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)\n       wr_pntr           <= #`TCQ 0;\n   end\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (wr_rst_i == 1'b1) begin\n       num_wr_bits       <= 0;\n       next_num_wr_bits   = 0;\n       wr_ptr            <= C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= C_RD_DEPTH - 1;\n       ideal_wr_ack      <= 0;\n       ideal_wr_count    <= 0;\n       tmp_wr_listsize    = 0;\n       rd_ptr_wrclk_next <= 0;\n       wr_pntr_rd1       <= 0;\n\n     end else begin //wr_rst_i==0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       //If this is a write, handle the write by adding the value\n       // to the linked list, and updating all outputs appropriately\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD \n             >= C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full, but reporting full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //With DEPTH-1 words in the FIFO, it is almost_full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n\n           //If the FIFO is completely empty, but it is\n           // reporting FULL for some reason (like reset)\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=\n                C_FIFO_WR_DEPTH-2) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //FIFO is really not close to full, so change flag status.\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n           end //(tmp_wr_listsize == 0)\n\n         end else begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=\n              C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack       <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count     <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;\n\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //This write is CAUSING the FIFO to go full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is 2 from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == \n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits =  next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Still 2 from full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is not close to being full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <\n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //wr_rst_i==0\n   end // gen_fifo_w\n\n\n  /***************************************************************************\n   * Programmable FULL flags\n   ***************************************************************************/\n\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;\n\n   generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;\n   end else begin // STD\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;\n   end endgenerate\n\n   always @(posedge WR_CLK or posedge wr_rst_i) begin\n\n     if (wr_rst_i == 1'b1) begin\n       diff_pntr         <= 0;\n     end else begin\n       if (ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);\n       else if (!ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);\n    end\n  end\n\n\n   always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf\n\n     if (RST_FULL_FF & C_HAS_RST) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else begin\n\n       if (RST_FULL_GEN)\n         ideal_prog_full   <= #`TCQ 0;\n       //Single Programmable Full Constant Threshold\n       else if (C_PROG_FULL_TYPE == 1) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else\n             ideal_prog_full <= #`TCQ 0;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Constant Thresholds\n       end else if (C_PROG_FULL_TYPE == 2) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else if (diff_pntr < pf_thr_negate_val)\n             ideal_prog_full <= #`TCQ 0;\n           else\n             ideal_prog_full <= #`TCQ ideal_prog_full;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Single Programmable Full Threshold Input\n       end else if (C_PROG_FULL_TYPE == 3) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH)\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Threshold Inputs\n       end else if (C_PROG_FULL_TYPE == 4) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH_ASSERT)\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < PROG_FULL_THRESH_NEGATE)\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       end // C_PROG_FULL_TYPE\n\n     end //wr_rst_i==0\n   end //\n\n   \n   /**************************************************************************\n   * Read Domain Logic\n   **************************************************************************/\n\n\n   /*********************************************************\n    * Programmable EMPTY flags\n    *********************************************************/\n   //Determine the Assert and Negate thresholds for Programmable Empty\n\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd      = 0;\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe\n\n     if (rd_rst_i & C_HAS_RST) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else begin\n       if (ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;\n       else if (!ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr);\n       else\n         diff_pntr_rd       <=  #`TCQ diff_pntr_rd;\n  \n       if (C_PROG_EMPTY_TYPE == 1) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 2) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 3) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 4) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end  //C_PROG_EMPTY_TYPE\n     end\n   end // gen_pe\n\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;\n   end endgenerate // single_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;\n   end endgenerate // multiple_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;\n   end endgenerate // single_multiple_pe_thr_const\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp\n     if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n       rd_pntr            <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)\n       rd_pntr            <= #`TCQ 0;\n   end\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rd_rst_i & C_HAS_RST) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n     end else begin //rd_rst_i==0\n\n       rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 1\n       /*****************************************************************/\n       if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Reminder that FIFO is still empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end // if (tmp_rd_listsize <= 0)\n\n             //If the FIFO is one from empty, but it is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 1)\n\n             //If the FIFO is two from empty, and is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Fifo has two words, so is neither empty or almost empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 2)\n\n             //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid <= #`TCQ 1'b0;\n                 //Note that the FIFO is No Longer Empty or Almost Empty\n\n                 ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n               end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n             end // else: if(ideal_empty == 1'b1)\n\n           else //if (ideal_empty == 1'b0)\n             begin\n\n               //If the FIFO is completely full, and we are successfully reading from it\n               if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)\n\n               //If the FIFO is not close to being empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n               //If the FIFO is two from empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Fifo is not yet empty. It is going almost_empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n\n               //If the FIFO is one from empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Note that FIFO is GOING empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 1)\n\n\n               //If the FIFO is completely empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n                 begin\n                   //Do not change the contents of the FIFO\n\n                   //Do not acknowledge the read from empty FIFO\n                   ideal_valid        <= #`TCQ 1'b0;\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize <= 0)\n\n             end // if (ideal_empty == 1'b0)\n\n           end //(RD_EN == 1'b1)\n\n         else //if (RD_EN == 1'b0)\n           begin\n             //If user did not attempt a read, do not give an ack or err\n             ideal_valid          <= #`TCQ 1'b0;\n\n             ideal_rd_count       <= #`TCQ num_read_words_sized_i;\n\n           end // else: !if(RD_EN == 1'b1)\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 0\n       /*****************************************************************/\n       end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty, but it is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty, and is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Fifo has two words, so is neither empty or almost empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                         (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that the FIFO is No Longer Empty or Almost Empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n           end else begin\n\n             //If the FIFO is completely full, and we are successfully reading from it\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is not close to being empty\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                          (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Fifo is not yet empty. It is going almost_empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Note that FIFO is GOING empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is completely empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if (tmp_rd_listsize <= 0)\n\n           end // if (ideal_empty == 1'b0)\n\n         end else begin//(RD_EN == 1'b0)\n\n         \n           //If user did not attempt a read, do not give an ack or err\n           ideal_valid           <= #`TCQ 1'b0;\n           ideal_rd_count        <= #`TCQ num_read_words_sized_i;\n\n         end // else: !if(RD_EN == 1'b1)\n       end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //rd_rst_i==0\n   end //always gen_fifo_r_as\n\nendmodule // fifo_generator_v13_2_5_bhv_ver_as\n\n\n/*******************************************************************************\n * Declaration of Low Latency Asynchronous FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_beh_ver_ll_afifo\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_FIFO_TYPE                    = 0\n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   output reg  [C_DOUT_WIDTH-1:0]                DOUT = 0,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL\n  );\n\n  //-----------------------------------------------------------------------------\n  // Low Latency Asynchronous FIFO\n  //-----------------------------------------------------------------------------\n\n  // Memory which will be used to simulate a FIFO\n  reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n  integer i;\n  initial begin\n    for (i = 0; i < C_WR_DEPTH; i = i + 1)\n      memory[i] = 0;\n  end\n\n  reg  [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;\n  wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;\n  reg  [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;\n  reg                        ll_afifo_full    = 1'b0;\n  reg                        ll_afifo_empty   = 1'b1;\n  wire                       write_allow;\n  wire                       read_allow;\n\n  assign write_allow = WR_EN & ~ll_afifo_full;\n  assign read_allow  = RD_EN & ~ll_afifo_empty;\n\n  //-----------------------------------------------------------------------------\n  // Write Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      wr_pntr_ll_afifo   <= 0;\n    else if (write_allow)\n      wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Read Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      rd_pntr_ll_afifo_q   <= 0;\n    else\n      rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;\n  end\n  assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;\n  \n  //-----------------------------------------------------------------------------\n  // Fill the Memory\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK) begin\n    if (write_allow)\n      memory[wr_pntr_ll_afifo] <= #`TCQ DIN;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate DOUT\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK) begin\n      DOUT <= #`TCQ memory[rd_pntr_ll_afifo];\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate EMPTY\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      ll_afifo_empty   <= 1'b1;\n    else\n      ll_afifo_empty   <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | \n                           (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate FULL\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      ll_afifo_full   <= 1'b1;\n    else\n      ll_afifo_full   <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | \n                           (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));\n  end\n\n  always @* begin\n    FULL  <= ll_afifo_full;\n    EMPTY <= ll_afifo_empty;\n  end\n\nendmodule // fifo_generator_v13_2_5_beh_ver_ll_afifo\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_ss\n   \n  /**************************************************************************\n   * Declare user parameters and their defaults\n   *************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0 \n   )\n   \n  /**************************************************************************\n   * Declare Input and Output Ports\n   *************************************************************************/\n   (\n    //Inputs\n    input                                 SAFETY_CKT_WR_RST,\n    input                                 CLK,\n    input       [C_DIN_WIDTH-1:0]         DIN,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_ASSERT,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_NEGATE,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_ASSERT,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_NEGATE,\n    input                                 RD_EN,\n    input                                 RD_EN_USER,\n    input                                 USER_EMPTY_FB,\n    input                                 RST,\n    input                                 RST_FULL_GEN,\n    input                                 RST_FULL_FF,\n    input                                 SRST,\n    input                                 WR_EN,\n    input                                 INJECTDBITERR,\n    input                                 INJECTSBITERR,\n    input                                 WR_RST_BUSY,\n    input                                 RD_RST_BUSY,\n                                    \n    //Outputs                       \n    output                                ALMOST_EMPTY,\n    output                                ALMOST_FULL,\n    output reg   [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,\n    output       [C_DOUT_WIDTH-1:0]       DOUT,\n    output                                EMPTY,\n    output reg                            EMPTY_FB = 1'b1,\n    output                                FULL,\n    output                                OVERFLOW,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]    RD_DATA_COUNT,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]    WR_DATA_COUNT,\n    output                                PROG_EMPTY,\n    output                                PROG_FULL,\n    output                                VALID,\n    output                                UNDERFLOW,\n    output                                WR_ACK,\n    output                                SBITERR,\n    output                                DBITERR\n   );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;\n   wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n   localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; \n\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n   localparam  EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //localparam  EXTRA_WORDS_PE_PARAM  = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not \n   //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.\n   // Therefore, during SRST, all the FULL flags reset to 0.\n   localparam                      C_HAS_FAST_FIFO = 0;\n   localparam                      C_FIFO_WR_DEPTH = C_WR_DEPTH;\n   localparam                      C_FIFO_RD_DEPTH = C_RD_DEPTH;\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;\n   localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;\n   localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;\n   localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n  localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; \n  localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; \n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   \n   /**************************************************************************\n    * Internal Registers and wires\n    *************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire                           underflow_i;\n   wire                           valid_i;\n   wire                           valid_out;\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_reg = 1'b0;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n   wire                         srst_rrst_busy;\n\n\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]                      err_type           = 0;\n   reg [1:0]                      err_type_d1        = 0;\n   reg [1:0]                      err_type_both      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout         = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_d1      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_both      = 0;\n   wire [C_DOUT_WIDTH-1:0]        ideal_dout_out;\n   wire                           fwft_enabled;\n   reg                            ideal_wr_ack       = 0;\n   reg                            ideal_valid        = 0;\n   reg                            ideal_overflow     = C_OVERFLOW_LOW;\n   reg                            ideal_underflow    = C_UNDERFLOW_LOW;\n\n   reg                            full_i             = C_FULL_FLAGS_RST_VAL;\n   reg                            full_i_temp        = 0;\n   reg                            empty_i            = 1;\n   reg                            almost_full_i      = 0;\n   reg                            almost_empty_i     = 1;\n   reg                            prog_full_i        = 0;\n   reg                            prog_empty_i       = 1;\n   reg [C_WR_PNTR_WIDTH-1:0]      wr_pntr            = 0;\n   reg [C_RD_PNTR_WIDTH-1:0]      rd_pntr            = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg [C_RD_PNTR_WIDTH-1:0]      diff_count         = 0;\n\n   reg                            write_allow_q      = 0;\n   reg                            read_allow_q       = 0;\n   reg                            valid_d1           = 0;\n   reg                            valid_both           = 0;\n   reg                            valid_d2           = 0;\n   wire                           rst_i;\n   wire                           srst_i;\n\n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]         dout_reset_val = 0;\n\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n\n\n\n   /****************************************************************************\n    * Function Declarations\n    ***************************************************************************/\n\n   /****************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***************************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin\n        case (def_data[7:0])\n          8'b00000000 : begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default : begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1) begin\n          if ((index*4)+j < C_DOUT_WIDTH) begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   //reg         valid_d1     = 0;\n   \n   \n   //user specified value for reseting the size of the fifo\n   //reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n\n\n /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n     if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n\n     end\n  endtask\n\n\n   \n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_dout_both    = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_both         = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n\n   end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the\n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n   wire CLK;\n   wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;\n   wire RD_EN;\n   wire RST;\n   wire WR_EN;\n    */\n\n  // Assign ALMOST_EPMTY\n  generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae\n    assign ALMOST_EMPTY = almost_empty_i;\n  end else begin : gnae\n    assign ALMOST_EMPTY = 0;\n  end endgenerate // gae\n\n  // Assign ALMOST_FULL\n  generate if (C_HAS_ALMOST_FULL==1) begin : gaf\n    assign ALMOST_FULL  = almost_full_i;\n  end else begin : gnaf\n    assign ALMOST_FULL  = 0;\n  end endgenerate // gaf\n\n   // Dout may change behavior based on latency\n  localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?\n                         ideal_dout_d1: ideal_dout; \n  assign DOUT = ideal_dout_out;\n\n  // Assign SBITERR and DBITERR based on latency \n  assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[0]: err_type[0]; \n  assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[1]: err_type[1]; \n\n  assign EMPTY         = empty_i;\n  assign FULL          = full_i;\n  //saftey_ckt with one register\n\n  generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)\n          begin\n          if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n              valid_d1 <= #`TCQ 1'b0;\n          end\n          else begin\n               ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n               valid_d1 <= #`TCQ valid_i;\n          end\n          end\n          \n           always@(posedge rst_delayed_sft2 or posedge CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n              end\n           else if (srst_rrst_busy == 1'b1) begin\n                   if (C_USE_DOUT_RST == 1'b1) begin\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   end\n           end else if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                end\n           end   \n      end //if \n      endgenerate   \n\n//safety ckt with both registers\n\ngenerate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK) begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            valid_d1 <= #`TCQ 1'b0;\n          end else begin\n            ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n            fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n            valid_both <= #`TCQ valid_i;\n            valid_d1 <= #`TCQ valid_both;\n          end\n        end\n\n        always@(posedge rst_delayed_sft2 or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                  ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else if (srst_rrst_busy == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else begin \n            if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n            end\n          end\n        end\n      end //if \n      endgenerate    \n \n \n  //Overflow may be active-low\n  generate if (C_HAS_OVERFLOW==1) begin : gof\n    assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n  end else begin : gnof\n    assign OVERFLOW = 0;\n  end endgenerate // gof\n\n  assign PROG_EMPTY    = prog_empty_i;\n  assign PROG_FULL     = prog_full_i;\n\n   //Valid may change behavior based on latency or active-low\n  generate if (C_HAS_VALID==1) begin : gvalid\n    assign valid_i       = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;\n    assign valid_out     = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?\n                            valid_d1 : valid_i; \n    assign VALID         = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n  end else begin : gnvalid\n    assign VALID         = 0;\n  end endgenerate // gvalid\n\n  //Trim data count differently depending on set widths\n  generate if (C_HAS_DATA_COUNT == 1) begin : gdc\n    always @* begin\n      diff_count <= wr_pntr - rd_pntr;\n      if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin\n        DATA_COUNT[C_RD_PNTR_WIDTH-1:0]  <= diff_count;\n        DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; \n      end else begin\n        DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];\n      end\n    end\n//  end else begin : gndc\n//    always @* DATA_COUNT <= 0;\n  end endgenerate // gdc\n\n  //Underflow may change behavior based on latency or active-low\n  generate if (C_HAS_UNDERFLOW==1) begin : guf\n    assign underflow_i   = ideal_underflow;\n    assign UNDERFLOW     = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n  end else begin : gnuf\n    assign UNDERFLOW     = 0;\n  end endgenerate // guf\n \n\n  //Write acknowledge may be active low \n  generate if (C_HAS_WR_ACK==1) begin : gwr_ack\n    assign WR_ACK        = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n  end else begin : gnwr_ack\n    assign WR_ACK        = 0;\n  end endgenerate // gwr_ack\n\n\n  /*****************************************************************************\n   * Internal reset logic \n   ****************************************************************************/\n  assign srst_i        = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;\n  assign rst_i            = C_HAS_RST ? RST : 0;\n  assign srst_wrst_busy   = srst_i;\n  assign srst_rrst_busy   = srst_i;\n\n   /**************************************************************************\n    * Assorted registers for delayed versions of signals\n    **************************************************************************/\n   //Capture delayed version of valid\n   generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20\n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1 <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n           end else begin\n              valid_d1 <= #`TCQ valid_i;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n     end \n   endgenerate // blockVL20\n\n  generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin \n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1   <= 1'b0;\n           valid_both <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n              valid_both <= #`TCQ 1'b0;\n              \n           end else begin\n              valid_both <= #`TCQ valid_i;\n               valid_d1 <= #`TCQ valid_both;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n  end\n endgenerate // blockVL20\n\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge CLK or posedge rst_i) begin\n         if (rst_i) begin\n           stage1_valid     <= #`TCQ 0;\n           stage2_valid     <= #`TCQ 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n\n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc\n       assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc\n       assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n   \n   //reg ram_rd_en_d1 = 1'b0;\n   //Capture delayed version of dout\n   generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         ram_rd_en_d1 <= #`TCQ 1'b0;\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n        end\n      end else begin\n         ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n         if (srst_rrst_busy) begin\n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            // Reset err_type only if ECC is not selected\n            if (C_USE_ECC == 0) begin\n               err_type_d1   <= #`TCQ 0;\n               err_type_both <= #`TCQ 0;\n            end\n            // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n            if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n            end \n         if (C_USE_DOUT_RST == 1) begin\n           // @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         end else begin\n            if (ram_rd_en_d1 ) begin\n            ideal_dout_d1 <= #`TCQ ideal_dout;\n            err_type_d1   <= #`TCQ err_type;\n            end\n         end\n      end    \n   end   // always\nend\nendgenerate \n\n//no safety ckt with both registers\n generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n          ram_rd_en_d1 <= #`TCQ 1'b0;\n          fab_rd_en_d1 <= #`TCQ 1'b0;\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val; \n            \n      end\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val;\n       end\n      end else begin\n         if (srst_rrst_busy) begin \n           ram_rd_en_d1 <= #`TCQ 1'b0;\n           fab_rd_en_d1 <= #`TCQ 1'b0;\n           // Reset err_type only if ECC is not selected\n           if (C_USE_ECC == 0) begin\n              err_type_d1   <= #`TCQ 0;\n              err_type_both <= #`TCQ 0;\n           end\n           // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n           if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n              ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end \n           if (C_USE_DOUT_RST == 1) begin\n             ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end\n         end else begin\n           ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n           fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);\n           if (ram_rd_en_d1 ) begin\n             ideal_dout_both <= #`TCQ ideal_dout;\n             err_type_both   <= #`TCQ err_type;\n           end\n           if (fab_rd_en_d1 ) begin\n             ideal_dout_d1 <= #`TCQ ideal_dout_both;\n             err_type_d1   <= #`TCQ err_type_both;\n           end\n         end\n      end    \n   end   // always\nend\nendgenerate \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n     always @(posedge CLK) begin\n       ideal_overflow    <= #`TCQ WR_EN & full_i;\n     end\n   end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n     always @(posedge CLK) begin\n       //ideal_overflow    <= #`TCQ WR_EN & (rst_i | full_i);\n       ideal_overflow    <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);\n     end\n   end endgenerate // blockOF20\n \n   generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n     always @(posedge CLK) begin\n       ideal_underflow   <= #`TCQ empty_i & RD_EN;\n     end\n   end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n     always @(posedge CLK) begin\n       //ideal_underflow   <= #`TCQ (rst_i | empty_i) & RD_EN;\n       ideal_underflow   <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;\n     end\n   end endgenerate // blockUF20\n\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n\n  /*************************************************************************\n   * Write and Read Logic  \n   ************************************************************************/\n   wire              write_allow;\n   wire              read_allow;\n   wire              read_allow_dc;\n   wire              write_only;\n   wire              read_only;\n   //wire              write_only_q;\n   reg              write_only_q;\n   //wire              read_only_q;\n   reg              read_only_q;\n   reg              full_reg;\n   reg              rst_full_ff_reg1;\n   reg              rst_full_ff_reg2;\n   wire              ram_full_comb;\n   wire              carry;\n   \n   assign write_allow  = WR_EN & ~full_i;\n   assign read_allow   = RD_EN & ~empty_i;\n   assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;\n   //assign write_only   = write_allow & ~read_allow;\n   //assign write_only_q = write_allow_q;\n   //assign read_only    = read_allow    & ~write_allow;\n   //assign read_only_q  = read_allow_q ;\n   wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;\n   wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;\n   wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;\n\n   assign diff_pntr_pe_max = DIFF_MAX_RD;\n   assign diff_pntr_max = DIFF_MAX_WR;\n\n\n\n   generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym\n    assign write_only   = write_allow & ~read_allow;\n    assign read_only    = read_allow    & ~write_allow;\n    end endgenerate\n    generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd\n     assign read_only   = read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;\n     assign write_only    = write_allow    & ~(read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n    generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr\n     assign read_only   = read_allow & ~(write_allow  & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n     assign write_only    = write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;\n    end endgenerate\n\n\n   //-----------------------------------------------------------------------------\n   // Write and Read pointer generation\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       wr_pntr         <= 0;\n       rd_pntr         <= 0;\n     end else begin\n       if (srst_i) begin\n         wr_pntr       <= #`TCQ 0;\n         rd_pntr       <= #`TCQ 0;\n       end else begin\n         if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;\n         if (read_allow)  rd_pntr <= #`TCQ rd_pntr + 1;\n       end\n     end\n   end\n\n   generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout\n   always @(posedge CLK) begin\n     if (write_allow) begin\n       if (ENABLE_ERR_INJECTION == 1)\n         memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};\n       else\n         memory[wr_pntr] <= #`TCQ DIN;\n     end\n   end\n\n   reg  [C_DATA_WIDTH-1:0] dout_tmp_q;\n   reg [C_DATA_WIDTH-1:0] dout_tmp = 0;\n   reg  [C_DATA_WIDTH-1:0] dout_tmp1 = 0;\n   always @(posedge CLK) begin\n     dout_tmp_q <= #`TCQ ideal_dout;\n   end\n\n\n\n     always @* begin\n       if (read_allow)\n         ideal_dout <= memory[rd_pntr];\n       else\n         ideal_dout <= dout_tmp_q;\n     end\n   end endgenerate // gll_dm_dout\n\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   assign ram_rd_en        = RD_EN & !EMPTY;\n\n   //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   generate if (C_FIFO_TYPE != 2) begin : gnll_din\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i == 1'b1) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n\n     end else begin //rst_i==0\n     if (srst_wrst_busy) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n     end else begin//srst_i=0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n         end else begin\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error  \n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           //end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //srst_i==0\n     end //wr_rst_i==0\n   end // gen_fifo_w\n    end endgenerate\n\n   generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout\n     always @(posedge CLK) begin\n       if (rst_i || srst_rrst_busy) begin\n         if (C_USE_DOUT_RST == 1) begin\n           ideal_dout <= #`TCQ dout_reset_val;\n           ideal_dout_both <= #`TCQ dout_reset_val;\n         end\n       end\n     end\n    end endgenerate\n\n\n\n\n   generate if (C_FIFO_TYPE != 2) begin : gnll_dout\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_r\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n\n     end else begin //rd_rst_i==0\n     if (srst_rrst_busy) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets synchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= #`TCQ 0;\n         err_type_both    <= #`TCQ 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n      end //srst_i\n      else begin\n\n       //rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n         if (RD_EN == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end \n           else \n             begin\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n         end\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //s_rst_i==0\n     end //rd_rst_i==0\n   end //always\n  end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate diff_pntr for PROG_FULL generation\n   // Generate diff_pntr_pe for PROG_EMPTY generation\n   //-----------------------------------------------------------------------------\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         write_only_q   <= 1'b0;\n         read_only_q    <= 1'b0;\n         diff_pntr_reg1       <= 0;\n         diff_pntr_pe_reg1    <= 0;\n         diff_pntr_reg2       <= 0;\n         diff_pntr_pe_reg2    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_rrst_busy) begin\n           read_only_q  <= #`TCQ 1'b0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n           diff_pntr_pe_reg2  <= #`TCQ 0;\n          end\n          if (srst_wrst_busy) begin\n           write_only_q <= #`TCQ 1'b0;\n           diff_pntr_reg1     <= #`TCQ 0;\n           diff_pntr_reg2     <= #`TCQ 0;\n          end\n         end else begin\n           write_only_q <= #`TCQ write_only;\n           read_only_q  <= #`TCQ read_only;\n           diff_pntr_reg2  <= #`TCQ diff_pntr_reg1;\n           diff_pntr_pe_reg2  <= #`TCQ diff_pntr_pe_reg1;\n\n           // Add 1 to the difference pointer value when only write happens.\n           if (write_only)  \n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;\n           else\n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;\n\n           // Add 1 to the difference pointer value when write or both write & read or no write & read happen.\n           if (read_only)  \n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;\n           else\n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;\n         end\n       end\n     end\n   assign diff_pntr_pe = diff_pntr_pe_reg1;\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow\n\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym\n    assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};\n    assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         diff_pntr_pe_asym    <= 0;\n         diff_pntr_reg1       <= 0;\n         full_reg             <= 0;\n         rst_full_ff_reg1     <= 1;\n         rst_full_ff_reg2     <= 1;\n         diff_pntr_pe_reg1    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_wrst_busy)\n           diff_pntr_reg1     <= #`TCQ 0;\n          if (srst_rrst_busy)\n           full_reg             <=  #`TCQ 0;\n           rst_full_ff_reg1     <=  #`TCQ 1;\n           rst_full_ff_reg2     <=  #`TCQ 1;\n           diff_pntr_pe_asym    <=  #`TCQ 0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n         end else begin\n             diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;\n             full_reg          <= #`TCQ full_i;\n             rst_full_ff_reg1  <=  #`TCQ RST_FULL_FF;\n             rst_full_ff_reg2  <=  #`TCQ rst_full_ff_reg1;\n           if (~full_i) begin  \n             diff_pntr_reg1 <=  #`TCQ wr_pntr - adj_rd_pntr_wr;\n          end\n         end\n       end\n     end\n   assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));\n   assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow_asym\n\n\n   //-----------------------------------------------------------------------------\n   // Generate FULL flag\n   //-----------------------------------------------------------------------------\n   wire                 comp0;\n   wire                 comp1;\n   wire                 going_full;\n   wire                 leaving_full;\n \n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin :  gpad \t\n    assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;\n    assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin :  gtrim \n    assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n  end endgenerate\n\n   assign comp1         = (adj_rd_pntr_wr == (wr_pntr + 1'b1));\n   assign comp0         = (adj_rd_pntr_wr == wr_pntr);\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp\n     assign going_full    = (comp1 & write_allow & ~read_allow);\n     assign leaving_full  = (comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym\n      assign going_full = (comp1 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_full = (comp0 & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp \n      assign going_full = (comp1 & write_allow & ~read_allow);\n      assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n\n   assign ram_full_comb = going_full | (~leaving_full & full_i);\n\n   generate if (C_HAS_RST == 1) begin : grst_full\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF & C_HAS_RST)\n         full_i   <= C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_SRST == 1) begin : gsrst_full\n     always @(posedge CLK) begin\n       if (srst_wrst_busy)\n         full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_full\n     always @(posedge CLK) begin\n         full_i   <= #`TCQ ram_full_comb;\n     end\n   end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate EMPTY flag\n   //-----------------------------------------------------------------------------\n   wire                 ecomp0;\n   wire                 ecomp1;\n   wire                 going_empty;\n   wire                 leaving_empty;\n   wire                 ram_empty_comb;\n\n  \n generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin :  pad \t\n    assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n    assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin :  trim \n    assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n  end endgenerate\n\n   assign ecomp1         = (adj_wr_pntr_rd == (rd_pntr + 1'b1));\n   assign ecomp0         = (adj_wr_pntr_rd == rd_pntr);\n\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp\n     assign going_empty    = (ecomp1 & ~write_allow & read_allow);\n     assign leaving_empty  = (ecomp0 & write_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp\n      assign going_empty = (ecomp1 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_empty = (ecomp0 & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp \n      assign going_empty = (ecomp1 & ~write_allow & read_allow);\n      assign leaving_empty =(ecomp0 & write_allow);\n    end endgenerate\n\n\n\n    assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);\n\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       empty_i  <= 1'b1;\n     else if (srst_rrst_busy)\n       empty_i  <= #`TCQ 1'b1;\n     else\n       empty_i  <= #`TCQ ram_empty_comb;\n    end\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       EMPTY_FB     <= 1'b1;\n     end else begin\n       if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))\n         EMPTY_FB   <= #`TCQ 1'b1;\n       else\n         EMPTY_FB   <= #`TCQ ram_empty_comb;\n     end\n   end // always\n\n   //-----------------------------------------------------------------------------\n   // Generate Read and write data counts for asymmetic common clock\n   //-----------------------------------------------------------------------------\n\n    reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; \n    wire [C_GRTR_PNTR_WIDTH :0] ratio; \n    wire decr_by_one;\n    wire incr_by_ratio;\n    wire incr_by_one;\n    wire decr_by_ratio;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n\n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr \n      assign ratio         = C_DEPTH_RATIO_RD;\n      assign decr_by_one   = (IS_FWFT == 1)? read_allow_dc : read_allow;\n      assign incr_by_ratio = write_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (decr_by_one) begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc - 1;\n           else\n\t    count_dc <= #`TCQ count_dc - 1  + ratio ;\n\t end\n\t else begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc + ratio ;\n\tend\n       end\n       end\n\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n\n    end endgenerate\n\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd \n      assign ratio         = C_DEPTH_RATIO_WR;\n      assign incr_by_one   = write_allow;\n      assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (incr_by_one) begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc + 1;\n           else\n\t    count_dc <= #`TCQ count_dc + 1  - ratio ;\n\t end\n\t else begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc - ratio ;\n\tend\n       end\n       end\n\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n\n    end endgenerate\n\n\n\n\n\n\n   //-----------------------------------------------------------------------------\n   // Generate WR_ACK flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_wr_ack  <= 1'b0;\n     else if (srst_wrst_busy)\n       ideal_wr_ack  <= #`TCQ 1'b0;\n     else if (WR_EN & ~full_i)\n       ideal_wr_ack  <= #`TCQ 1'b1;\n     else\n       ideal_wr_ack  <= #`TCQ 1'b0;\n    end\n\n   //-----------------------------------------------------------------------------\n   // Generate VALID flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_valid  <= 1'b0;\n     else if (srst_rrst_busy)\n       ideal_valid  <= #`TCQ 1'b0;\n     else if (RD_EN & ~empty_i)\n       ideal_valid  <= #`TCQ 1'b1;\n     else\n       ideal_valid  <= #`TCQ 1'b0;\n    end\n\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_FULL flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss\n\n     wire                 fcomp2;\n     wire                 going_afull;\n     wire                 leaving_afull;\n     wire                 ram_afull_comb;\n\n\n   assign fcomp2         = (adj_rd_pntr_wr == (wr_pntr + 2'h2));\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp\n     assign going_afull    = (fcomp2 & write_allow & ~read_allow);\n     assign leaving_afull  = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym\n      assign going_afull = (fcomp2 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_afull = (comp1 & (~write_allow) & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp \n      assign going_afull = (fcomp2 & write_allow & ~read_allow);\n      assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n     assign ram_afull_comb  = going_afull | (~leaving_afull & almost_full_i);\n\n\n    generate if (C_HAS_RST == 1) begin : grst_afull\n      always @(posedge CLK or posedge RST_FULL_FF) begin\n        if (RST_FULL_FF & C_HAS_RST)\n          almost_full_i   <= C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_SRST == 1) begin : gsrst_afull\n      always @(posedge CLK) begin\n        if (srst_wrst_busy)\n          almost_full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_afull\n      always @(posedge CLK) begin\n          almost_full_i   <= #`TCQ ram_afull_comb;\n      end\n    end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_EMPTY flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss\n\n     wire                 ecomp2;\n     wire                 going_aempty;\n     wire                 leaving_aempty;\n     wire                 ram_aempty_comb;\n      \n     assign ecomp2          = (adj_wr_pntr_rd == (rd_pntr + 2'h2));\n   \n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp\n     assign going_aempty    = (ecomp2 & ~write_allow & read_allow);\n     assign leaving_aempty  = (ecomp1 & write_allow & ~read_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp\n      assign going_aempty = (ecomp2 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp \n      assign going_aempty = (ecomp2 & ~write_allow & read_allow);\n      assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);\n    end endgenerate\n\n\n     assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);\n\n     always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         almost_empty_i  <= 1'b1;\n       else if (srst_rrst_busy)\n         almost_empty_i  <= #`TCQ 1'b1;\n       else\n         almost_empty_i  <= #`TCQ ram_aempty_comb;\n      end\n  // end endgenerate // gae_ss\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL\n   //-----------------------------------------------------------------------------\n\n   localparam  C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT \n                                  C_PROG_FULL_THRESH_ASSERT_VAL; // STD\n   localparam  C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT\n                                  C_PROG_FULL_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;   \n   generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin \n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n          prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr>= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  ((diff_pntr) < C_PF_ASSERT_VAL )\n        prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate // single_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr >= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n       else if  (diff_pntr < C_PF_NEGATE_VAL)\n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate //multiple_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT\n                                               PROG_FULL_THRESH; // STD\n   generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input\n\n     always @(posedge CLK or posedge RST_FULL_FF) begin//0\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin //1\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin//2 \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin//3\n           if (diff_pntr > pf3_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if (diff_pntr == pf3_assert_val) begin//4\n             if (read_only_q)\n               prog_full_i <= #`TCQ 1'b0;\n             else\n               prog_full_i <= #`TCQ 1'b1;\n           end else//4\n             prog_full_i <= #`TCQ 1'b0;\n         end else//3\n           prog_full_i <= #`TCQ prog_full_i;\n       end //2\n       else begin//5\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin//6 \n        if (diff_pntr >= pf3_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  (diff_pntr < pf3_assert_val) begin//7\n         prog_full_i <= #`TCQ 1'b0;\n       end//7\n       end//6\n      else\n           prog_full_i <= #`TCQ prog_full_i;\n       end//5\n     end//1\n     end//0\n   end endgenerate //single_pf_input\n  \n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_ASSERT; // STD\n   wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_NEGATE; // STD\n\n   generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin\n           if (diff_pntr >= pf_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if ((diff_pntr == pf_negate_val && read_only_q) ||\n                  diff_pntr < pf_negate_val)\n             prog_full_i <= #`TCQ 1'b0;\n           else\n             prog_full_i <= #`TCQ prog_full_i;\n         end else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin \n        if (diff_pntr >= pf_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n       else if (diff_pntr < pf_negate_val) \n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n\n     end\n   end\n   end endgenerate //multiple_pf_inputs\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY\n   //-----------------------------------------------------------------------------\n   localparam  C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD\n   localparam  C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i) \n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy) \n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL)\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > C_PE_ASSERT_VAL)\n         prog_empty_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n     end\n     end\n   end endgenerate // single_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > C_PE_NEGATE_VAL) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n\n     end\n\n     end\n   end endgenerate //multiple_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH -2) : // FWFT\n                                                PROG_EMPTY_THRESH; // STD\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe < pe3_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (diff_pntr_pe == pe3_assert_val) begin\n             if (write_only_q)\n               prog_empty_i <= #`TCQ 1'b0;\n             else\n               prog_empty_i <= #`TCQ 1'b1;\n           end else\n             prog_empty_i <= #`TCQ 1'b0;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe3_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > pe3_assert_val)\n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n\n     end\n   end endgenerate // single_pe_input\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_ASSERT; // STD\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_NEGATE; // STD\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n      else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe <= pe4_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || \n                     (diff_pntr_pe > pe4_negate_val)) begin\n             prog_empty_i <= #`TCQ 1'b0;\n           end else\n             prog_empty_i <= #`TCQ prog_empty_i;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe4_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > pe4_negate_val) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n     end\n   end endgenerate // multiple_pe_inputs\n\nendmodule // fifo_generator_v13_2_5_bhv_ver_ss\n\n\n\n/**************************************************************************\n * First-Word Fall-Through module (preload 0)\n **************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_preload0\n  #(\n    parameter  C_DOUT_RST_VAL            = \"\",\n    parameter  C_DOUT_WIDTH              = 8,\n    parameter  C_HAS_RST                 = 0,\n    parameter  C_ENABLE_RST_SYNC         = 0,\n    parameter  C_HAS_SRST                = 0,\n    parameter  C_USE_EMBEDDED_REG        = 0,\n    parameter  C_EN_SAFETY_CKT           = 0, \n    parameter  C_USE_DOUT_RST            = 0,\n    parameter  C_USE_ECC                 = 0,\n    parameter  C_USERVALID_LOW           = 0,\n    parameter  C_USERUNDERFLOW_LOW       = 0,\n    parameter  C_MEMORY_TYPE             = 0,\n    parameter  C_FIFO_TYPE               = 0\n  )\n  (\n    //Inputs\n    input                          SAFETY_CKT_RD_RST,\n    input                          RD_CLK,\n    input                          RD_RST,\n    input                          SRST,\n    input                          WR_RST_BUSY,\n    input                          RD_RST_BUSY,\n    input                          RD_EN,\n    input                          FIFOEMPTY,\n    input       [C_DOUT_WIDTH-1:0] FIFODATA,\n    input                          FIFOSBITERR,\n    input                          FIFODBITERR,\n   \n    //Outputs\n    output reg  [C_DOUT_WIDTH-1:0] USERDATA,\n    output                         USERVALID,\n    output                         USERUNDERFLOW,\n    output                         USEREMPTY,\n    output                         USERALMOSTEMPTY,\n    output                         RAMVALID,\n    output                         FIFORDEN,\n    output reg                     USERSBITERR,\n    output reg                     USERDBITERR,\n    output reg                     STAGE2_REG_EN,\n    output                         fab_read_data_valid_i_o,\n    output                         read_data_valid_i_o,\n    output                         ram_valid_i_o,\n    output      [1:0]              VALID_STAGES \n  );\n //Internal signals\n wire                      preloadstage1;\n wire                      preloadstage2;\n reg                       ram_valid_i;\n reg                       fab_valid;\n reg                       read_data_valid_i;\n reg                       fab_read_data_valid_i;\n reg                       fab_read_data_valid_i_1;\n reg                       ram_valid_i_d;\n reg                       read_data_valid_i_d;\n reg                       fab_read_data_valid_i_d;\n wire                      ram_regout_en;\n reg                       ram_regout_en_d1;\n reg                       ram_regout_en_d2;\n wire                      fab_regout_en;\n wire                      ram_rd_en;\n reg                       empty_i        = 1'b1;\n reg                       empty_sckt     = 1'b1;\n reg                       sckt_rrst_q    = 1'b0;\n reg                       sckt_rrst_done = 1'b0;\n reg                       empty_q        = 1'b1;\n reg                       rd_en_q        = 1'b0;\n reg                       almost_empty_i = 1'b1;\n reg                       almost_empty_q = 1'b1;\n wire                      rd_rst_i;\n wire                      srst_i;\n reg  [C_DOUT_WIDTH-1:0]   userdata_both;\n wire                      uservalid_both;\n wire                      uservalid_one;\n reg                       user_sbiterr_both = 1'b0;\n reg                       user_dbiterr_both = 1'b0;\n  \nassign ram_valid_i_o = ram_valid_i;\nassign read_data_valid_i_o = read_data_valid_i;\nassign fab_read_data_valid_i_o = fab_read_data_valid_i; \n\n\n\n/*************************************************************************\n* FUNCTIONS\n*************************************************************************/\n\n   /*************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***********************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n   \n   //*************************************************************************\n   //  Set power-on states for regs\n   //*************************************************************************\n   initial begin\n      ram_valid_i       = 1'b0;\n      fab_valid         = 1'b0;\n      read_data_valid_i = 1'b0;\n      fab_read_data_valid_i = 1'b0;\n      fab_read_data_valid_i_1 = 1'b0;\n      USERDATA          = hexstr_conv(C_DOUT_RST_VAL);\n      userdata_both          = hexstr_conv(C_DOUT_RST_VAL);\n      USERSBITERR       = 1'b0;\n      USERDBITERR       = 1'b0;\n      user_sbiterr_both = 1'b0;\n      user_dbiterr_both = 1'b0;\n   end //initial\n\n   //***************************************************************************\n   //  connect up optional reset\n   //***************************************************************************\n   assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;\n   assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;\n\n   reg  sckt_rd_rst_fwft = 1'b0;\n   reg  fwft_rst_done_i  = 1'b0;\n   wire fwft_rst_done;\n   assign fwft_rst_done = 1'b1;//C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;\n   always @ (posedge RD_CLK) begin\n     sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;\n   end\n\n   always @ (posedge rd_rst_i or posedge RD_CLK) begin\n     if (rd_rst_i)\n       fwft_rst_done_i  <= 1'b0;\n     else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)\n       fwft_rst_done_i  <= #`TCQ 1'b1;\n   end\n\n   localparam INVALID             = 0;\n   localparam STAGE1_VALID        = 2;\n   localparam STAGE2_VALID        = 1;\n   localparam BOTH_STAGES_VALID   = 3;\n\n   reg  [1:0] curr_fwft_state = INVALID;\n   reg  [1:0] next_fwft_state = INVALID;\n\n\ngenerate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin\n         always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n \n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n     \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n    \n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = preloadstage2;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;\n   end\nendgenerate // gnll_fifo\n\n   reg curr_state         = 0;\n   reg next_state         = 0;\n   reg leaving_empty_fwft = 0;\n   reg going_empty_fwft   = 0;\n   reg empty_i_q          = 0;\n   reg ram_rd_en_fwft     = 0;\n   generate if (C_FIFO_TYPE == 2) begin : gll_fifo\n     always @* begin // FSM fo FWFT\n       case (curr_state)\n         1'b0: begin\n           if (~FIFOEMPTY)\n             next_state <= 1'b1;\n           else\n             next_state <= 1'b0;\n           end\n         1'b1: begin\n           if (FIFOEMPTY && RD_EN)\n             next_state <= 1'b0;\n           else\n             next_state <= 1'b1;\n           end\n         default: next_state <= 1'b0;\n       endcase\n     end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_i       <= 1'b1;\n           empty_i_q     <= 1'b1;\n           ram_valid_i   <= 1'b0;\n        end else if (srst_i) begin\n           empty_i       <= #`TCQ 1'b1;\n           empty_i_q     <= #`TCQ 1'b1;\n           ram_valid_i   <= #`TCQ 1'b0;\n        end else begin\n           empty_i       <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);\n           empty_i_q     <= #`TCQ FIFOEMPTY;\n           ram_valid_i   <= #`TCQ next_state;\n        end\n     end //always\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n           curr_state    <= 1'b0;\n        end else if (srst_i) begin\n           curr_state    <= #`TCQ 1'b0;\n        end else begin\n           curr_state    <= #`TCQ next_state;\n        end\n     end //always\n\n     wire                  fe_of_empty; \n     assign fe_of_empty   = empty_i_q & ~FIFOEMPTY;\n\n     always @* begin // Finding leaving empty\n       case (curr_state)\n         1'b0:    leaving_empty_fwft <= fe_of_empty;\n         1'b1:    leaving_empty_fwft <= 1'b1;\n         default: leaving_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Finding going empty\n       case (curr_state)\n         1'b1:    going_empty_fwft <= FIFOEMPTY & RD_EN;\n         default: going_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Generating FWFT rd_en\n       case (curr_state)\n         1'b0:    ram_rd_en_fwft <= ~FIFOEMPTY;\n         1'b1:    ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;\n         default: ram_rd_en_fwft <= 1'b0;\n       endcase\n     end\n\n     assign ram_regout_en = ram_rd_en_fwft;\n     //assign ram_regout_en_d1 = ram_rd_en_fwft;\n     //assign ram_regout_en_d2 = ram_rd_en_fwft;\n     assign ram_rd_en     = ram_rd_en_fwft;\n   end endgenerate // gll_fifo\n\n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false.\n   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n   generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           ram_valid_i     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              ram_valid_i     <= #`TCQ 1'b0;\n           end else begin\n              if (ram_rd_en == 1'b1) begin\n                 ram_valid_i   <= #`TCQ 1'b1;\n              end else begin\n                 if (ram_regout_en == 1'b1)\n                   ram_valid_i <= #`TCQ 1'b0;\n                 else\n                   ram_valid_i <= #`TCQ ram_valid_i;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_ram_valid\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n  \n generate if(C_USE_EMBEDDED_REG < 3) begin\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else\n        read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);\n   end //always\nend \nendgenerate\n\n   \n   \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n generate if ( C_USE_EMBEDDED_REG < 3) begin\n  always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin         // asynchronous reset (active high)\n             almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ FIFOEMPTY;\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n   \n   \n     \n  // BRAM resets synchronously\n generate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin\n   always @ ( posedge rd_rst_i)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n           @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n             USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end  else if (fwft_rst_done) begin\n            if (ram_regout_en) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end\n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n//safety ckt with one register\ngenerate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n            @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n        end\n     end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n          //@(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end \n       end\n        else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n            //  @(posedge RD_CLK)\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end else if (fwft_rst_done) begin\n            if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end          \n          end\n        end\n       end //always\n  end //if\nendgenerate\n\n\ngenerate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin\n         \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d1 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d1 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d1 <= #`TCQ ram_regout_en;\n                 end\n            end //always\n   //  assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));\n       assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d2 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d2 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;\n                 end\n            end //always\n\n    \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n     always @ (posedge RD_CLK) begin\n        ram_valid_i_d <= #`TCQ ram_valid_i;\n        read_data_valid_i_d <= #`TCQ read_data_valid_i;\n        fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;\n\n     end\n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n    \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;\n   end\n   endgenerate // gnll_fifo\n\n   \n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n     generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid\n\n     \n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           fab_valid     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              fab_valid    <= #`TCQ 1'b0;\n           end else begin\n              if (ram_regout_en == 1'b1) begin\n                 fab_valid  <= #`TCQ 1'b1;\n              end else begin\n                 if (fab_regout_en == 1'b1)\n                   fab_valid <= #`TCQ 1'b0;\n                 else\n                   fab_valid <= #`TCQ fab_valid;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_fab_valid\n\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n    generate if(C_USE_EMBEDDED_REG == 3) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else begin\n        if (ram_regout_en == 1'b1) begin\n          read_data_valid_i <= #`TCQ 1'b1;\n        end else begin\n         if (fab_regout_en == 1'b1)\n          read_data_valid_i <= #`TCQ 1'b0;\n        else\n          read_data_valid_i <= #`TCQ read_data_valid_i;\n        end \n      end \n   end //always\nend\nendgenerate\n\n//generate if(C_USE_EMBEDDED_REG == 3) begin\n//   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n//      if (rd_rst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//      else if (srst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//\n//      if (ram_regout_en == 1'b1) begin\n//        fab_read_data_valid_i <= #`TCQ 1'b0;\n//      end else begin\n//       if (fab_regout_en == 1'b1)\n//        fab_read_data_valid_i <= #`TCQ 1'b1;\n//      else\n//        fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;\n//      end \n//   end //always\n//end\n//endgenerate\n\n     generate if(C_USE_EMBEDDED_REG == 3 ) begin \n    always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid\n      if (rd_rst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else \n        fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);\n   end //always\nend\nendgenerate\n \nalways @ (posedge RD_CLK ) begin : proc_del1\n             begin\n                 fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;\n              end\n            end //always\n \n \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty_both\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n   reg FIFOEMPTY_1;\n   generate if (C_USE_EMBEDDED_REG == 3 ) begin\n    always @(posedge RD_CLK) begin\n            FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;\n           end\n    end\nendgenerate\n    generate if (C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n   begin\n      if (rd_rst_i) begin         // asynchronous reset (active high)\n           almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ (~ram_valid_i);\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_sckt <= #`TCQ 1'b1;\n           sckt_rrst_q <= #`TCQ 1'b0;\n           sckt_rrst_done <= #`TCQ 1'b0;\n        end else begin\n           sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;\n           if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin\n              sckt_rrst_done <= #`TCQ 1'b1;\n           end else if (sckt_rrst_done) begin\n              // rising clock edge\n              empty_sckt <= #`TCQ 1'b0;\n           end\n        end\n     end //always\n   \n   \n//   assign USEREMPTY       = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;\n   assign USEREMPTY       = empty_i;\n   assign USERALMOSTEMPTY = almost_empty_i;\n   assign FIFORDEN        = ram_rd_en;\n   assign RAMVALID        = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;\n   assign uservalid_both       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3)  ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);\n   assign uservalid_one       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3)  ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);\n   assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;\n   assign USERUNDERFLOW   = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;\n//no safety ckt with both reg\ngenerate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n            USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              userdata_both   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end else begin\n            if (fwft_rst_done) begin\n              if (ram_regout_en) begin\n                 userdata_both     <= #`TCQ FIFODATA; \n                 user_dbiterr_both <= #`TCQ FIFODBITERR;\n                 user_sbiterr_both <= #`TCQ FIFOSBITERR; \n              end\n              if (fab_regout_en) begin\n                 USERDATA     <= #`TCQ userdata_both;\n                 USERDBITERR  <= #`TCQ user_dbiterr_both;\n                 USERSBITERR  <= #`TCQ user_sbiterr_both; \n              end             \n            end             \n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n\n//safety_ckt with both registers\n generate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always @ (posedge RD_CLK) begin\n          if (rd_rst_i || srst_i) begin\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n              @(posedge RD_CLK)\n              USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n               userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end\n        end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n     if (rd_rst_i) begin //asynchronous reset (active high)\n       if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n         USERSBITERR       <= #`TCQ 0;\n         USERDBITERR       <= #`TCQ 0;\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end\n       // DRAM resets asynchronously\n       if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n         USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end \n     end else begin // rising clock edge\n       if (srst_i) begin\n         if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n           USERSBITERR       <= #`TCQ 0;\n           USERDBITERR       <= #`TCQ 0;\n           user_sbiterr_both <= #`TCQ 0;\n           user_dbiterr_both <= #`TCQ 0;\n         end\n         if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n           USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end\n       end else if (fwft_rst_done) begin\n         if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            userdata_both     <= #`TCQ FIFODATA;\n            user_dbiterr_both <= #`TCQ FIFODBITERR;\n            user_sbiterr_both <= #`TCQ FIFOSBITERR; \n         end\n         if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            USERDATA          <= #`TCQ userdata_both;\n            USERDBITERR       <= #`TCQ user_dbiterr_both;\n            USERSBITERR       <= #`TCQ user_sbiterr_both;\n         end\n       end\n     end\n   end //always\n  end //if\nendgenerate\n\nendmodule //fifo_generator_v13_2_5_bhv_ver_preload0\n\n\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Register one AXI channel on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   reg_slice\n//\n//--------------------------------------------------------------------------\n\nmodule fifo_generator_v13_2_5_axic_reg_slice #\n  (\n   parameter C_FAMILY     = \"virtex7\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   )\n  (\n   // System Signals\n   input  wire                      ACLK,\n   input  wire                      ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0]   S_PAYLOAD_DATA,\n   input  wire                      S_VALID,\n   output wire                      S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0]   M_PAYLOAD_DATA,\n   output wire                      M_VALID,\n   input  wire                      M_READY\n   );\n\n  localparam RST_SYNC_STAGES = 5;\n  localparam RST_BUSY_LEN    = 6;\n  reg [1:0] arst_sync_wr  = 2'b11;\n  reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n  wire sync_reset;\n  wire extnd_reset;\n\n\n  always @(posedge ARESET or posedge ACLK) begin\n    if (ARESET)\n      arst_sync_wr <= 2'b11;\n    else\n      arst_sync_wr <= #`TCQ {arst_sync_wr[0], 1'b0};\n  end\n\n  always @(posedge ACLK) begin\n    sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[1]};\n  end\n\n  assign sync_reset     = |sckt_wr_rst_cc[RST_BUSY_LEN-5:0] | arst_sync_wr[1]; \n  assign extnd_reset    = |sckt_wr_rst_cc | arst_sync_wr[1];\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000)\n    begin\n      reg [1:0] state;\n      localparam [1:0] \n        ZERO = 2'b10,\n        ONE  = 2'b11,\n        TWO  = 2'b01;\n      \n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg [C_DATA_WIDTH-1:0] storage_data2 = 0;\n      reg                    load_s1;\n      wire                   load_s2;\n      wire                   load_s1_from_s2;\n      reg                    s_ready_i; //local signal of output\n      wire                   m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with either slave side data or from storage2\n      always @(posedge ACLK) \n      begin\n        if (load_s1)\n          if (load_s1_from_s2)\n            storage_data1 <= storage_data2;\n          else\n            storage_data1 <= S_PAYLOAD_DATA;        \n      end\n\n      // Load storage2 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data1;\n\n      // Always load s2 on a valid transaction even if it's unnecessary\n      assign load_s2 = S_VALID & s_ready_i;\n\n      // Loading s1\n      always @ *\n      begin\n        if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction\n             // Load when ONE if we both have read and write at the same time\n             ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||\n             // Load when TWO and we have a transaction on Master side\n             ((state == TWO) && (M_READY == 1)))\n          load_s1 = 1'b1;\n        else\n          load_s1 = 1'b0;\n      end // always @ *\n\n      assign load_s1_from_s2 = (state == TWO);\n                       \n      // State Machine for handling output signals\n      always @(posedge ACLK) begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          state <= ZERO;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          case (state)\n            // No transaction stored locally\n            ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE\n\n            // One transaction stored locally\n            ONE: begin\n              if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO\n              if (~M_READY & S_VALID) begin\n                state <= TWO;  // Got another one so move to TWO\n                s_ready_i <= 1'b0;\n              end\n            end\n\n            // TWO transaction stored locally\n            TWO: if (M_READY) begin\n              state <= ONE; // Read out one so move to ONE\n              s_ready_i <= 1'b1;\n            end\n          endcase // case (state)\n        end\n      end // always @ (posedge ACLK)\n      \n      assign m_valid_i = state[0];\n\n    end // if (C_REG_CONFIG == 1)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000001)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg                    s_ready_i; //local signal of output\n      reg                    m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b0;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else if (m_valid_i & M_READY) begin\n          s_ready_i <= 1'b1;\n          m_valid_i <= 1'b0;\n        end else if (S_VALID & s_ready_i) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b1;\n        end\n        if (~m_valid_i) begin\n          storage_data1 <= S_PAYLOAD_DATA;        \n        end\n      end\n      assign M_PAYLOAD_DATA = storage_data1;\n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // reg_slice\n", "num_lines": 10520}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1\n// IP Revision: 21\n\n(* X_CORE_INFO = \"axi_clock_converter_v2_1_21_axi_clock_converter,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"axi_clock_converter_512,axi_clock_converter_v2_1_21_axi_clock_converter,{}\" *)\n(* CORE_GENERATION_INFO = \"axi_clock_converter_512,axi_clock_converter_v2_1_21_axi_clock_converter,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_clock_converter,x_ipVersion=2.1,x_ipCoreRevision=21,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_ID_WIDTH=16,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=1,C_AXI_PROTOCOL=0,C_AXI_SUPPORTS_USER_SIGNALS=1,C_AXI_AWUSER_WIDTH=8,C_AXI_ARUSER_WIDTH=8,C_AXI_WUSER_WIDTH=1,C_A\\\nXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_SYNCHRONIZER_STAGE=2}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_clock_converter_512 (\n  s_axi_aclk,\n  s_axi_aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awuser,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_aruser,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_aclk,\n  m_axi_aresetn,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awuser,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_aruser,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_CLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 SI_CLK CLK\" *)\ninput wire s_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 SI_RST RST\" *)\ninput wire s_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWUSER\" *)\ninput wire [7 : 0] s_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARUSER\" *)\ninput wire [7 : 0] s_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 8, ARUSER_WIDTH 8, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_CLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 MI_CLK CLK\" *)\ninput wire m_axi_aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 MI_RST RST\" *)\ninput wire m_axi_aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWUSER\" *)\noutput wire [7 : 0] m_axi_awuser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARUSER\" *)\noutput wire [7 : 0] m_axi_aruser;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 8, ARUSER_WIDTH 8, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_clock_converter_v2_1_21_axi_clock_converter #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_S_AXI_ACLK_RATIO(1),\n    .C_M_AXI_ACLK_RATIO(2),\n    .C_AXI_IS_ACLK_ASYNC(1),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_SUPPORTS_USER_SIGNALS(1),\n    .C_AXI_AWUSER_WIDTH(8),\n    .C_AXI_ARUSER_WIDTH(8),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_AXI_SUPPORTS_WRITE(1),\n    .C_AXI_SUPPORTS_READ(1),\n    .C_SYNCHRONIZER_STAGE(2)\n  ) inst (\n    .s_axi_aclk(s_axi_aclk),\n    .s_axi_aresetn(s_axi_aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(s_axi_awuser),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(s_axi_aruser),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_aclk(m_axi_aclk),\n    .m_axi_aresetn(m_axi_aresetn),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(m_axi_awuser),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(m_axi_aruser),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 443}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_master #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_SUPPORTS_NARROW = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1,\n   parameter [C_AXI_ADDR_WIDTH-1:0] C_AXI_ADDR = 0,  // Base address\n   parameter integer C_NUM_ADDR = 1,  // Number of address iterations; range 1..2**16 (fixed increment = 32'h10000\n   parameter integer C_NUM_ID = 1,  // Number of ID iterations; range 1..2**C_ID_WIDTH (base = 0; fixed increment = 1)\n   parameter integer C_NUM_LEN = 1,  // Number of LEN iterations; range 1..9 (base = 0; value = 2**i - 1)\n   parameter integer C_NUM_TRANS = 1  // Number of transactions; range >=1 (read and write)\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_awvalid,\n  input  wire                            m_axi_awready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_awburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_awlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_awlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_awid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]    m_axi_awuser = 'b0,\n  /**************** Write Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_wid,\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]      m_axi_wdata,\n  (* dont_touch=\"true\" *) output reg [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb = {(C_AXI_DATA_WIDTH/8){1'b1}},\n  (* dont_touch=\"true\" *) output wire                             m_axi_wvalid,\n  input  wire                            m_axi_wready,\n  (* dont_touch=\"true\" *) output wire                             m_axi_wlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]     m_axi_wuser = 'b0,\n  /**************** Write Response Channel Signals ****************/\n  input  wire [2-1:0]                    m_axi_bresp,\n  input  wire                            m_axi_bvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_bready,\n  input  wire [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]     m_axi_buser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_bid,\n  /**************** Read Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_arvalid,\n  input  wire                            m_axi_arready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_arburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_arlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_arlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_arid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]    m_axi_aruser = 'b0,\n  /**************** Read Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]      m_axi_rdata,\n  input  wire [2-1:0]                    m_axi_rresp,\n  input  wire                            m_axi_rvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_rready,\n  input  wire                            m_axi_rlast,\n  input  wire [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]     m_axi_ruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_rid,\n  /**************** System Signals ****************/\n  input  wire                            aclk,\n  input  wire                            aresetn\n  );\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n  localparam integer  P_NUM_ID_LOG = f_ceil_log2(C_NUM_ID);\n  localparam integer  P_NUM_ADDR_LOG = f_ceil_log2(C_NUM_ADDR);\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL==0 ? 8 : C_AXI_PROTOCOL==1 ? 4 : 1);\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer               P_M_AXI_DATA_BYTES = (C_AXI_DATA_WIDTH / 8);\n  localparam integer               P_M_AXI_DONE_WIDTH = f_ceil_log2(C_NUM_TRANS<2?2:C_NUM_TRANS);\n  localparam integer               P_M_AXI_SIZE = f_ceil_log2(C_AXI_DATA_WIDTH)-3;\n\n  /**************** Internal Wires/Regs - Global ****************/\n   wire                            done;\n    wire                            dummy ;\n  reg                         done_i;\n  reg                         done_sel;\n  wire                         done_cycle;\n  reg                          done_d1 = 1'b0;\n  reg                   areset = 1'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] arcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] rcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [3:0]                    acc_r_i = 4'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] awcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] wcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] bcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [2:0]                    acc_b_i = 3'b0;\n\n  // Register Reset\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    \n    /**************** Internal Wires/Regs - Read Channels ****************/\n    wire                         read_xaction_done_i;\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_arid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_ADDR_WIDTH:0]      araddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  arprot_i = 3'b0;\n    reg [3-1:0]                  arsize_i = 3'b0;\n    reg [2-1:0]                  arburst_i = 2'b0;\n    reg [4-1:0]                  arcache_i = 4'b0;\n    reg [2-1:0]                  arlock_i = 2'b0;\n    reg [P_LEN_WIDTH-1:0]     arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [4-1:0]                  arqos_i = 4'b0;\n    reg [P_ID_WIDTH-1:0]        arid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [2-1:0]                  rresp_i = 2'b00;\n    reg [C_AXI_RUSER_WIDTH:0]   ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      rid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_arvalid_i = 1'b0;\n    reg                        m_axi_rready_i = 1'b0;\n    reg [P_NUM_ADDR_LOG:0]    araddr_cnt = 0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign read_xaction_done_i = m_axi_rvalid && m_axi_rready_i && ((C_AXI_PROTOCOL==2)?1'b1:m_axi_rlast);\n    assign m_axi_arvalid = m_axi_arvalid_i;\n    assign m_axi_rready = m_axi_rready_i;\n    assign m_axi_araddr = m_axi_araddr_i;\n    assign m_axi_arlen = m_axi_arlen_i;\n    always @(posedge aclk) begin\n      m_axi_arprot <= dummy ? arprot_i : 3'b000;\n      m_axi_arsize <= dummy ? arsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_arburst <= dummy ? arburst_i : 2'b01;\n      m_axi_arlock <= dummy ? arlock_i : 1'b0;\n      m_axi_arcache <= dummy ? arcache_i : 4'h3;\n      m_axi_arqos <= dummy  ? arqos_i : 4'h0;\n      m_axi_aruser <= dummy ? aruser_i : 0;\n    end\n  \n    //**********************************************\n    // Read Channel: ARVALID, ARADDR, ARLEN, RREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_arvalid_i <= 1'b0;\n        arcnt_i <= C_NUM_TRANS;\n        m_axi_arlen_i <= 0;\n        m_axi_araddr_i <= C_AXI_ADDR;\n        m_axi_arid_i <= 1;\n        araddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_arready & m_axi_arvalid_i) begin\n          arcnt_i <= arcnt_i - 1;\n          if (araddr_cnt == 1) begin\n            m_axi_araddr_i <= dummy ? araddr_i : C_AXI_ADDR;\n            araddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_araddr_i <= m_axi_araddr_i + 32'h10000;\n            araddr_cnt <= araddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_arlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_arlen_i <= dummy ? arlen_i : 0;\n          end else begin\n            m_axi_arlen_i <= (m_axi_arlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_arid_i == C_NUM_ID)) begin\n            m_axi_arid <= dummy ? arid_i : 0;\n            m_axi_arid_i <= 1;\n          end else begin\n            m_axi_arid <= m_axi_arid_i;\n            m_axi_arid_i <= m_axi_arid_i + 1;\n          end\n          if (arcnt_i == 1) begin\n            m_axi_arvalid_i <= 1'b0;\n          end\n        end else if (arcnt_i != 0) begin\n          m_axi_arvalid_i <= 1'b1;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      araddr_i <= {araddr_i, ~araddr_i[C_AXI_ADDR_WIDTH]};\n      arprot_i <= {arprot_i, ~arprot_i[3-1]};\n      arlen_i <= {arlen_i, ~arlen_i[P_LEN_WIDTH-1]};\n      arsize_i <= {arsize_i, ~arsize_i[3-1]};\n      arburst_i <= {arburst_i, ~arburst_i[2-1]};\n      arlock_i <= {arlock_i, ~arlock_i[2-1]};\n      arcache_i <= {arcache_i, ~arcache_i[4-1]};\n      arqos_i <= {arqos_i, ~arqos_i[4-1]};\n      aruser_i <= {aruser_i, ~aruser_i[C_AXI_ARUSER_WIDTH]};\n      arid_i <= {arid_i, ~arid_i[P_ID_WIDTH-1]};\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        m_axi_rready_i <= 1'b0;\n        rcnt_i <= C_NUM_TRANS;\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        rresp_i <= {2{1'b0}};\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n        rid_i <= {P_ID_WIDTH{1'b0}};\n        acc_r_i <= 4'b0;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_rvalid & m_axi_rready_i) begin\n          m_axi_rready_i <= 1'b0;\n          rdata_i <= m_axi_rdata;\n            acc_r_i[0] <= rdata_i[0];\n          rresp_i <= m_axi_rresp;\n            acc_r_i[1] <= rresp_i[0];\n          ruser_i <= m_axi_ruser;\n            acc_r_i[2] <= ruser_i[0];\n          rid_i <= m_axi_rid;\n            acc_r_i[3] <= rid_i[0];\n          if (m_axi_rlast) begin\n            rcnt_i <= rcnt_i - 1;\n          end\n        end else begin\n          rdata_i <= rdata_i>>1;\n          rresp_i <= rresp_i>>1;\n          ruser_i <= ruser_i>>1;\n          rid_i <= rid_i>>1;\n          acc_r_i <= acc_r_i>>1;\n          if (m_axi_rvalid) begin\n            m_axi_rready_i <= 1'b1;\n          end\n        end\n      end\n    end\n    \n    assign dummy = rdata_i[0];\n    \n    \n\n    /**************** Internal Wires/Regs - Write Channels ****************/\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_awid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [8-1:0]                  xfer_w_i = 8'h00;\n    wire                         write_burst_done_i;\n    reg [C_AXI_ADDR_WIDTH:0]      awaddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  awprot_i = 3'b0;\n    reg [P_LEN_WIDTH-1:0]     awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [3-1:0]                  awsize_i = 3'b0;\n    reg [2-1:0]                  awburst_i = 2'b0;\n    reg [4-1:0]                  awcache_i = 4'b0;\n    reg [2-1:0]                  awlock_i = 2'b0;\n    reg [4-1:0]                  awqos_i = 4'b0;\n    reg [P_ID_WIDTH:0]        awid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_AWUSER_WIDTH:0]    awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg [P_M_AXI_DATA_BYTES-1:0] wstrb_i = {P_M_AXI_DATA_BYTES{1'b1}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]        wid_i = {P_ID_WIDTH{1'b0}};\n    reg [2-1:0]                  bresp_i = 2'b00;\n    reg [C_AXI_BUSER_WIDTH:0]   buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      bid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_awvalid_i = 1'b0;\n    reg                        m_axi_wvalid_i = 1'b0;\n    reg                        m_axi_bready_i = 1'b0;\n    reg                        m_axi_wlast_i = 1'b0;\n    reg                        m_axi_wid_i = {P_ID_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]     wlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [P_NUM_ADDR_LOG:0]    awaddr_cnt = 0;\n  \n    /**************** Assign Write Channel Outputs ****************/\n    assign m_axi_wdata = {wdata_i, done};\n    assign write_burst_done_i = m_axi_wready && m_axi_wvalid_i && ((C_AXI_PROTOCOL==2) || m_axi_wlast_i);\n    assign m_axi_awvalid = m_axi_awvalid_i;\n    assign m_axi_wvalid = m_axi_wvalid_i;\n    assign m_axi_bready = m_axi_bready_i;\n    assign m_axi_wlast = m_axi_wlast_i;\n    assign m_axi_awaddr = m_axi_awaddr_i;\n    assign m_axi_awlen = m_axi_awlen_i;\n    assign m_axi_wid = m_axi_wid_i;\n    always @(posedge aclk) begin\n      m_axi_awprot <= dummy ? awprot_i : 3'b000;\n      m_axi_awsize <= dummy ? awsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_awburst <= dummy ? awburst_i : 2'b01;\n      m_axi_awlock <= dummy ? awlock_i : 1'b0;\n      m_axi_awcache <= dummy ? awcache_i : 4'h3;\n      m_axi_awqos <= dummy ? awqos_i : 4'h0;\n      m_axi_wstrb <= dummy ? wstrb_i : {P_M_AXI_DATA_BYTES{1'b1}};\n      m_axi_awuser <= dummy ?  awuser_i : 0;\n      m_axi_wuser <= dummy ?  wuser_i : 0;\n    end\n  \n    //**********************************************\n    // Write Channel: AWVALID, AWADDR, AWLEN, WVALID, WLAST, BREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_awvalid_i <= 1'b0;\n        m_axi_wvalid_i <= 1'b0;\n        awcnt_i <= C_NUM_TRANS;\n        wcnt_i <= C_NUM_TRANS;\n        xfer_w_i <= 8'h00;\n        m_axi_awlen_i <= 0;\n        m_axi_awaddr_i <= C_AXI_ADDR;\n        m_axi_awid_i <= 1;\n        m_axi_wid_i <= 0;\n        m_axi_wlast_i <= 1'b0;\n        wlen_i <= 0;\n        wid_i <= 0;\n        awaddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_awvalid_i <= 1'b0;\n          awcnt_i <= awcnt_i - 1;\n          if (awaddr_cnt == 1) begin\n            m_axi_awaddr_i <= dummy ? awaddr_i : C_AXI_ADDR;\n            awaddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_awaddr_i <= m_axi_awaddr_i + 32'h10000;\n            awaddr_cnt <= awaddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_awlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_awlen_i <= dummy ? awlen_i : 0;\n          end else begin\n            m_axi_awlen_i <= (m_axi_awlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_awid_i == C_NUM_ID)) begin\n            m_axi_awid <= dummy ? awid_i : 0;\n            m_axi_awid_i <= 1;\n          end else begin\n            m_axi_awid <= m_axi_awid_i;\n            m_axi_awid_i <= m_axi_awid_i + 1;\n          end\n        end else if (~m_axi_wvalid_i) begin\n          if (awcnt_i != 0) begin\n            m_axi_awvalid_i <= 1'b1;\n          end\n        end\n  \n        /**************** Write Data Channel ****************/\n\n        if (m_axi_wready && m_axi_wvalid_i) begin\n          xfer_w_i <= xfer_w_i - 1'b1;\n          if (m_axi_wlast_i) begin\n            m_axi_wvalid_i <= 1'b0;\n            wcnt_i <= wcnt_i - 1'b1;\n          end else begin\n            m_axi_wlast_i <=  (xfer_w_i == 1);\n          end\n        end else if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_wvalid_i <= 1'b1;\n          xfer_w_i <= m_axi_awlen_i;\n          m_axi_wlast_i <= (m_axi_awlen_i==0);\n          m_axi_wid_i <= m_axi_awid_i;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: WDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        wdata_i <= (m_axi_wvalid_i && m_axi_wready) ? {wdata_i[C_AXI_DATA_WIDTH-2 : 0], ~wdata_i[C_AXI_DATA_WIDTH-1]} : wdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      awaddr_i <= {awaddr_i, ~awaddr_i[C_AXI_ADDR_WIDTH]};\n      awprot_i <= {awprot_i[3-2:0], ~awprot_i[3-1]};\n      wstrb_i <= {wstrb_i, ~wstrb_i[C_AXI_DATA_WIDTH/8-1]};\n      awlen_i <= {awlen_i, ~awlen_i[P_LEN_WIDTH-1]};\n      awsize_i <= {awsize_i, ~awsize_i[3-1]};\n      awburst_i <= {awburst_i, ~awburst_i[2-1]};\n      awlock_i <= {awlock_i, ~awlock_i[2-1]};\n      awcache_i <= {awcache_i, ~awcache_i[4-1]};\n      awqos_i <= {awqos_i, ~awqos_i[4-1]};\n      awid_i <= {awid_i, ~awid_i[P_ID_WIDTH-1]};\n      awuser_i <= {awuser_i, ~awuser_i[C_AXI_AWUSER_WIDTH]};\n      wuser_i <= {wuser_i, ~wuser_i[C_AXI_WUSER_WIDTH]};\n    end\n  \n    //**********************************************\n    // Write Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_bready_i <= 1'b0;\n        bcnt_i <= C_NUM_TRANS;\n        bresp_i <= {2{1'b0}};\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n        bid_i <= {P_ID_WIDTH{1'b0}};\n        acc_b_i <= 3'b0;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_bvalid & m_axi_bready_i) begin\n          m_axi_bready_i <= 1'b0;\n          bresp_i <= m_axi_bresp;\n            acc_b_i[0] <= bresp_i[0];\n          buser_i <= m_axi_buser;\n            acc_b_i[1] <= buser_i[0];\n          bid_i <= m_axi_bid;\n            acc_b_i[2] <= bid_i[0];\n          bcnt_i <= bcnt_i - 1;\n        end else begin\n          bresp_i <= bresp_i>>1;\n          buser_i <= buser_i>>1;\n          bid_i <= bid_i>>1;\n          acc_b_i <= acc_b_i>>1;\n          if (m_axi_bvalid) begin\n            m_axi_bready_i <= 1'b1;\n          end\n        end\n      end\n    end\n\n\n  //**********************************************\n  // Assert Done\n  //**********************************************\n  always @(posedge aclk) begin\n    if (~aresetn) begin\n      done_d1 <= 1'b0;\n    end else begin\n      done_d1 <= done_i;\n    end\n  end\n\n  assign done = done_sel ? done_i : done_d1;\n  assign done_cycle = done_i & ~done_d1;\n  \n  always @ * begin\n    if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_readonly_done\n       done_i = rcnt_i==0;\n       done_sel = acc_r_i[0];\n    end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_writeonly_done\n       done_i = bcnt_i==0;\n       done_sel = acc_b_i[0];\n    end else begin : gen_readwrite_done\n       done_i = (rcnt_i==0) && (bcnt_i==0);\n       done_sel = acc_r_i[0] ^ acc_b_i[0];\n    end\n  end\n  \nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n  input  wire [3-1:0]                   s_axi_awprot,\n  input  wire                           s_axi_awvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_awready,\n  input  wire [3-1:0]                   s_axi_awsize,\n  input  wire [2-1:0]                   s_axi_awburst,\n  input  wire [4-1:0]                   s_axi_awcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_awlen,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_awlock,\n  input  wire [4-1:0]                   s_axi_awqos,\n  input  wire [4-1:0]                   s_axi_awregion,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_awid,\n  input  wire [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]   s_axi_awuser,\n  /**************** Write Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n  input  wire                           s_axi_wvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_wready,\n  input  wire                           s_axi_wlast,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_wid,\n  input  wire [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]    s_axi_wuser,\n  /**************** Write Response Channel Signals ****************/\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_bresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_bvalid,\n  input  wire                           s_axi_bready,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]    s_axi_buser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_bid = 'b0,\n  /**************** Read Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n  input  wire [3-1:0]                   s_axi_arprot,\n  input  wire                           s_axi_arvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_arready,\n  input  wire [3-1:0]                   s_axi_arsize,\n  input  wire [2-1:0]                   s_axi_arburst,\n  input  wire [4-1:0]                   s_axi_arcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_arlock,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_arlen,\n  input  wire [4-1:0]                   s_axi_arqos,\n  input  wire [4-1:0]                   s_axi_arregion,\n  input  wire [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]   s_axi_aruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_arid,\n  /**************** Read Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_rresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rvalid,\n  input  wire                           s_axi_rready,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]    s_axi_ruser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_rid = 'b0,\n  /**************** System Signals ****************/\n  input  wire                           aclk,\n  input  wire                           aresetn\n   );\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL == 1) ? 4 : 8;\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer P_S_AXI_DATA_BYTES = 32/8;\n  localparam integer P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n\n  /**************** Internal Wires/Regs - Global ****************/\n  reg                   areset = 1'b0;\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    /**************** Internal Wires/Regs - Read Channels ****************/\n    reg [8-1:0]                   xfer_r_cnt = 8'h00;\n    reg [16-1:0]                  arcnt_i = 16'h0000;\n    wire                          read_xaction_done_i;\n    reg [C_AXI_DATA_WIDTH-1:0]     rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]      arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg                           arvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     araddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   arprot_i = 3'b000;\n    reg [3-1:0]                   arsize_i = 3'b000;\n    reg [2-1:0]                   arburst_i = 2'b00;\n    reg [4-1:0]                   arcache_i = 4'b0000;\n    reg [1-1:0]     arlock_i = 1'b0;\n    reg [4-1:0]                   arqos_i = 4'b0000;\n    reg [4-1:0]                   arregion_i = 4'b0000;\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_RUSER_WIDTH:0]     ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_ar_i = 9'b0;\n    reg                           s_axi_rvalid_i = 1'b0;\n    reg                           s_axi_arready_i = 1'b0;\n    reg                           s_axi_rlast_i = 1'b0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign s_axi_rdata = rdata_i;\n    assign read_xaction_done_i = (s_axi_rready && s_axi_rvalid_i && s_axi_rlast_i);\n    assign s_axi_rvalid = s_axi_rvalid_i;\n    assign s_axi_arready = s_axi_arready_i;\n    assign s_axi_rlast = s_axi_rlast_i;\n    //**********************************************\n    // Read Channel: ARREADY, RVALID, RLAST, RID\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        xfer_r_cnt <= 8'h00;\n        arcnt_i <= 16'h0000;\n        arlen_i <= {P_LEN_WIDTH{1'b0}};\n        s_axi_rlast_i <= 1'b0;\n      end else begin\n        /**************** Read Address Channel ****************/\n        // arready\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_arready_i <= 1'b0;\n          arcnt_i <= arcnt_i + 1'b1;\n        end else if (~s_axi_rvalid_i) begin\n          s_axi_arready_i <= 1'b1;\n        end\n  \n        /**************** Read Data Channel ****************/\n        // rvalid\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_rvalid_i <= 1'b1;\n          s_axi_rid <= s_axi_arid;\n          s_axi_ruser <= ruser_i;\n        end else if(read_xaction_done_i) begin\n          s_axi_rvalid_i <= 1'b0;\n        end\n  \n        // rlast\n        if(s_axi_rready && s_axi_rvalid_i) begin\n          xfer_r_cnt <= xfer_r_cnt - 1;\n          if(xfer_r_cnt == 1) begin\n            s_axi_rlast_i <= 1'b1;\n          end\n        end else if(s_axi_arready_i && s_axi_arvalid) begin\n          xfer_r_cnt <= s_axi_arlen;\n          s_axi_rlast_i <= (s_axi_arlen==0);\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Read Channel: RDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        rdata_i <= (s_axi_rready && s_axi_rvalid_i) ? {rdata_i[C_AXI_DATA_WIDTH-2 : 0], ~rdata_i[C_AXI_DATA_WIDTH-1]} : rdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_rresp <= {2{1'b0}};\n      end else if (~s_axi_rvalid_i) begin\n        s_axi_rresp <= {acc_ar_i[0], 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n      end else begin\n        ruser_i <= (s_axi_arready_i && s_axi_arvalid) ? {ruser_i, ~ruser_i[C_AXI_RUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        araddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        arprot_i <= {3{1'b0}};\n        arsize_i <= {3{1'b0}};\n        arburst_i <= {2{1'b0}};\n        arcache_i <= {4{1'b0}};\n        arlock_i <= {1{1'b0}};\n        arqos_i <= {4{1'b0}};\n        arregion_i <= {4{1'b0}};\n        aruser_i <= {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n        acc_ar_i <= 9'b0;\n      end else if (s_axi_arvalid) begin\n        // Register Inputs\n        araddr_i <= s_axi_araddr;\n          acc_ar_i[0] <= araddr_i[0];\n        arprot_i <= s_axi_arprot;\n          acc_ar_i[1] <= arprot_i[0];\n        arsize_i <= s_axi_arsize;\n          acc_ar_i[2] <= arsize_i[0];\n        arburst_i <= s_axi_arburst;\n          acc_ar_i[3] <= arburst_i[0];\n        arcache_i <= s_axi_arcache;\n          acc_ar_i[4] <= arcache_i[0];\n        arlock_i <= s_axi_arlock;\n          acc_ar_i[5] <= arlock_i[0];\n        arqos_i <= s_axi_arqos;\n          acc_ar_i[6] <= arqos_i[0];\n        arregion_i <= s_axi_arregion;\n          acc_ar_i[7] <= arregion_i[0];\n        aruser_i <= s_axi_aruser;\n          acc_ar_i[8] <= aruser_i[0];\n      end else begin\n        araddr_i <= araddr_i>>1;\n        arprot_i <= arprot_i>>1;\n        arsize_i <= arsize_i>>1;\n        arburst_i <= arburst_i>>1;\n        arcache_i <= arcache_i>>1;\n        arlock_i <= arlock_i>>1;\n        arqos_i <= arqos_i>>1;\n        arregion_i <= arregion_i>>1;\n        aruser_i <= aruser_i>>1;\n        acc_ar_i <= acc_ar_i>>1;\n      end\n    end\n  \n  \n    /**************** Internal Wires/Regs - Write Channels ****************/\n    wire                          write_burst_done_i;\n    reg [16-1:0]                  awcnt_i = 16'h0000;\n    reg                           awvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     awaddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   awprot_i = 3'b000;\n    reg [3-1:0]                   awsize_i = 3'b000;\n    reg [2-1:0]                   awburst_i = 2'b00;\n    reg [4-1:0]                   awcache_i = 4'b0000;\n    reg [P_LEN_WIDTH-1:0]      awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [1-1:0]     awlock_i = 1'b0;\n    reg [4-1:0]                   awqos_i = 4'b0000;\n    reg [4-1:0]                   awregion_i = 4'b0000;\n    reg [C_AXI_AWUSER_WIDTH:0]     awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg                           wvalid_i = 1'b0;\n    reg [C_AXI_DATA_WIDTH-1:0]     wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH/8-1:0]   wstrb_i = {(C_AXI_DATA_WIDTH/8){1'b0}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_BUSER_WIDTH:0]     buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_aw_i = 9'b0;\n    reg [3:0]                     acc_w_i = 4'b0;\n    reg                           s_axi_bvalid_i = 1'b0;\n    reg                           s_axi_awready_i = 1'b0;\n    reg                           s_axi_wready_i = 1'b0;\n    /**************** Assign Write Channel Outputs ****************/\n    assign write_burst_done_i =s_axi_wready_i && s_axi_wvalid && ((C_AXI_PROTOCOL == 2) ? 1'b1 : s_axi_wlast);\n    assign s_axi_bvalid = s_axi_bvalid_i;\n    assign s_axi_awready = s_axi_awready_i;\n    assign s_axi_wready = s_axi_wready_i;\n  \n    //**********************************************\n    // Write Channel: AWREADY, WREADY, BVALID, BID\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awcnt_i <= 16'h0000;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        /**************** Write Address Channel ****************/\n        // awready\n        if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_awready_i <= 1'b0;\n          awcnt_i <= awcnt_i + 1'b1;\n          s_axi_bid <= s_axi_awid;\n          s_axi_buser <= buser_i;\n        end else if(~s_axi_wready_i & ~s_axi_bvalid_i) begin\n          s_axi_awready_i <= 1'b1;\n        end\n  \n        /**************** Write Data Channel ****************/\n        // wready\n        if(write_burst_done_i) begin\n          s_axi_wready_i <= 1'b0;\n        end else if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_wready_i <= 1'b1;\n        end\n  \n        /**************** Write Response Channel ****************/\n        // bvalid\n        if(write_burst_done_i) begin\n          s_axi_bvalid_i <= 1'b1;\n        end else if(s_axi_bready && s_axi_bvalid_i) begin\n          s_axi_bvalid_i <= 1'b0;\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Write Channel: BRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_bresp <= {2{1'b0}};\n      end else if (~s_axi_bvalid_i) begin\n        s_axi_bresp <= {(acc_aw_i[0] ^ acc_w_i[0]), 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: BUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (aresetn) begin\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n      end else begin\n        buser_i <= (s_axi_awready_i && s_axi_awvalid) ? {buser_i, ~buser_i[C_AXI_BUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Write Address Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awaddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        awprot_i <= {3{1'b0}};\n        awsize_i <= {3{1'b0}};\n        awburst_i <= {2{1'b0}};\n        awcache_i <= {4{1'b0}};\n        awlen_i <= {P_LEN_WIDTH{1'b0}};\n        awlock_i <= {1{1'b0}};\n        awqos_i <= {4{1'b0}};\n        awregion_i <= {4{1'b0}};\n        awuser_i <= {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n        acc_aw_i <= 9'b0;\n      end else if (s_axi_awvalid) begin\n        // Register Inputs\n        awaddr_i <= s_axi_awaddr;\n          acc_aw_i[0] <= awaddr_i[0];\n        awprot_i <= s_axi_awprot;\n          acc_aw_i[1] <= awprot_i[0];\n        awsize_i <= s_axi_awsize;\n          acc_aw_i[2] <= awsize_i[0];\n        awburst_i <= s_axi_awburst;\n          acc_aw_i[3] <= awburst_i[0];\n        awcache_i <= s_axi_awcache;\n          acc_aw_i[4] <= awcache_i[0];\n        awlock_i <= s_axi_awlock;\n          acc_aw_i[5] <= awlock_i[0];\n        awqos_i <= s_axi_awqos;\n          acc_aw_i[6] <= awqos_i[0];\n        awregion_i <= s_axi_awregion;\n          acc_aw_i[7] <= awregion_i[0];\n        awuser_i <= s_axi_awuser;\n          acc_aw_i[8] <= awuser_i[0];\n      end else begin\n        awaddr_i <= awaddr_i>>1;\n        awprot_i <= awprot_i>>1;\n        awsize_i <= awsize_i>>1;\n        awburst_i <= awburst_i>>1;\n        awcache_i <= awcache_i>>1;\n        awlock_i <= awlock_i>>1;\n        awqos_i <= awqos_i>>1;\n        awregion_i <= awregion_i>>1;\n        awuser_i <= awuser_i>>1;\n        acc_aw_i <= acc_aw_i>>1;\n      end\n    end\n  \n    //**********************************************\n    // Write Data Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        wstrb_i <= {(C_AXI_DATA_WIDTH/8){1'b0}};\n        wuser_i <= {(C_AXI_WUSER_WIDTH+1){1'b0}};\n        acc_w_i <= 4'b0;\n      end else if (s_axi_wvalid) begin\n        // Register Inputs\n        wdata_i <= s_axi_wdata;\n          acc_w_i[0] <= wdata_i[0];\n        wstrb_i <= s_axi_wstrb;\n          acc_w_i[1] <= wstrb_i[0];\n        wuser_i <= s_axi_wuser;\n          acc_w_i[2] <= wuser_i[0];\n      end else begin\n        wdata_i <= wdata_i>>1;\n        wstrb_i <= wstrb_i>>1;\n        wuser_i <= wuser_i>>1;\n        acc_w_i <= acc_w_i>>1;\n      end\n    end\n  \nendmodule\n\n\n\n//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_22_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \n(* autopipeline_module=\"yes\" *)\nmodule axi_register_slice_v2_1_22_auto_slr #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n    wire                    handshake_pipe;\n    wire                    ready_pipe;\n    wire [C_DATA_WIDTH-1:0] payload_pipe;\n    (* keep=\"true\" *)                                                                reg  s_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  s_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  s_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  s_areset_resp2 = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  m_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  m_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_areset_resp2 = 1'b0;\n    \n  // Global Reset pipelining\n  \n    always @(posedge ACLK) begin\n      s_aclear       <= ~ARESETN;\n      s_areset_fwd   <= ~ARESETN; \n      s_areset_resp  <= s_areset_fwd;  // Auto-pipeline\n      s_areset_resp2 <= s_areset_resp; // Auto-pipeline\n    end\n    \n    always @(posedge ACLK) begin\n      m_aclear       <= ~ARESETN;\n      m_areset_fwd   <= ~ARESETN; \n      m_areset_resp  <= m_areset_fwd;  // Auto-pipeline\n      m_areset_resp2 <= m_areset_resp; // Auto-pipeline\n    end\n    \n  // Source-side submodule\n    \n    axi_register_slice_v2_1_22_auto_src #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_src\n      (\n       .ACLK             (ACLK),    \n       .s_aclear         (s_aclear),\n       .s_areset_resp2   (s_areset_resp2),  \n       .S_VALID          (S_VALID),  \n       .S_READY          (S_READY), \n       .S_PAYLOAD_DATA   (S_PAYLOAD_DATA),\n       .ready_pipe        (ready_pipe), \n       .handshake_pipe    (handshake_pipe),\n       .payload_pipe      (payload_pipe)  \n      );\n    \n  // Destination-side submodule\n    \n    axi_register_slice_v2_1_22_auto_dest #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_dest\n      (\n       .ACLK           (ACLK),    \n       .m_aclear       (m_aclear),\n       .m_areset_resp2 (m_areset_resp2),  \n       .M_READY        (M_READY), \n       .M_VALID        (M_VALID),  \n       .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n       .handshake_pipe  (handshake_pipe),\n       .ready_pipe      (ready_pipe),  \n       .payload_pipe    (payload_pipe)  \n      );\n    \nendmodule  // auto_slr\n\nmodule axi_register_slice_v2_1_22_auto_src #\n  (\n   parameter integer C_DATA_WIDTH = 32\n  )\n  (\n   input  wire ACLK,\n   input  wire s_aclear,\n   input  wire s_areset_resp2,\n   input  wire S_VALID,\n   input  wire ready_pipe,\n   output wire S_READY,\n   output wire handshake_pipe,\n   output wire  [C_DATA_WIDTH-1:0] payload_pipe,\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA\n   );\n    \n   (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  [C_DATA_WIDTH-1:0] payload_pipe_r;\n    (* keep=\"true\" *) reg [2:0] s_aresetn_resp4 = 3'b000;\n    wire s_aresetn_resp3;\n    wire s_aresetn_d;\n    wire s_aresetn_q;\n    wire s_handshake_d;\n    wire s_ready_i;\n    \n    assign S_READY = s_ready_i & s_aresetn_q;\n    assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;\n    assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;\n    assign payload_pipe = payload_pipe_r;\n    \n    always @(posedge ACLK or posedge s_aclear) begin\n      if (s_aclear) begin\n        s_aresetn_resp4 <= 3'b000;\n      end else begin\n        s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      payload_pipe_r <= S_PAYLOAD_DATA;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) s_aresetn_resp3_inst (\n        .Q   (s_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~s_areset_resp2)\n     );\n    \n    // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (s_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_aresetn_d)\n     );\n    \n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (handshake_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_handshake_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (s_ready_i),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (ready_pipe)\n     );\n    \nendmodule  // auto_src\n\nmodule axi_register_slice_v2_1_22_auto_dest #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   input  wire ACLK,\n   input  wire m_aclear,\n   input  wire m_areset_resp2,\n   input  wire M_READY,\n   input  wire handshake_pipe,\n   output wire ready_pipe,\n   output wire M_VALID,\n   input  wire [C_DATA_WIDTH-1:0] payload_pipe,\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n   );\n    \n    (* keep=\"true\" *) reg [2:0] m_aresetn_resp4 = 3'b000;\n    wire m_aresetn_resp3;\n    wire m_aresetn_d;\n    wire m_aresetn_q;\n    wire m_valid_i;\n    wire pop;\n    wire m_ready_d;\n    wire m_handshake_q;\n    reg  [C_DATA_WIDTH-1:0] m_payload_q;\n    \n    assign M_VALID = m_valid_i;\n    assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;\n    assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;\n    assign pop     = M_READY & m_valid_i;\n    \n    always @(posedge ACLK or posedge m_aclear) begin\n      if (m_aclear) begin\n        m_aresetn_resp4 <= 3'b000;\n      end else begin\n        m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      m_payload_q <= payload_pipe;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) m_aresetn_resp3_inst (\n        .Q   (m_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~m_areset_resp2)\n     );\n    \n    // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (m_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_aresetn_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (m_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (handshake_pipe)\n     );\n    \n    (* autopipeline_group=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (ready_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_ready_d)\n     );\n    \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  (5)  \n      )\n      srl_fifo\n      (\n       .aclk    (ACLK),    \n       .areset  (~m_aresetn_q),\n       .aclear  (m_aclear),  \n       .s_mesg  (m_payload_q),  \n       .s_valid (m_handshake_q), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      );\n    \nendmodule  // auto_dest\n\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      reg s_valid_d;\n      reg s_ready_d = 1'b0;\n      reg s_ready_reg = 1'b0;\n      reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_22_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_RESP_MIDDLE2_LATENCY = C_PIPELINES_SLAVE + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_22_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      .ACLK           (ACLK),\n      .ARESETN         (ARESETN),\n      .S_PAYLOAD_DATA (S_PAYLOAD_DATA),\n      .S_VALID        (S_VALID),\n      .S_READY        (S_READY),\n      .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n      .M_VALID        (M_VALID),\n      .M_READY        (M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_reset;\n    wire src_ready;\n    wire dummy_reset;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  ( C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( dummy_reset   ) ,\n        .laguna_s_reset_in  ( src_reset   ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset   ) ,\n        .laguna_m_reset_in  ( src_reset  ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset2   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n      \n  end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] mid_payload;\n    wire mid_handshake;\n    wire mid_ready;\n    wire mid_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n    wire dummy_reset3;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( mid_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( mid_reset    ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset3   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset3   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out (  dummy_reset2  ) ,\n        .laguna_m_reset_in  ( mid_reset   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE2_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( mid_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2   ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset3   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset3    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n   \n  generate\n\n  (* keep=\"true\" *) reg s_reset_dd = 1'b0;\n  (* keep=\"true\" *) reg m_reset_dd = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n  \n  assign laguna_s_reset_out = laguna_s_reset_out_i;\n  assign laguna_m_reset_out = laguna_m_reset_out_i;\n  \n  always @(posedge ACLK) begin\n    laguna_s_reset_in_d <= laguna_s_reset_in;\n    laguna_m_reset_in_d <= laguna_m_reset_in;\n    s_reset_dd <= laguna_s_reset_in_d;\n    m_reset_dd <= laguna_m_reset_in_d;\n    laguna_s_reset_out_i <= C_PIPELINES==0 ? laguna_m_reset_in_d : m_reset_dd;\n    laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;\n  end\n  \n  wire ACLEAR;\n  assign ACLEAR = ~ARESETN;\n  \n  if (1) begin : common\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire laguna_s_handshake_q;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, laguna_m_ready_d}; \n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else if (p==C_PIPELINES+1) begin\n          laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n\n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = handshake_i[C_PIPELINES];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_m_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* keep=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_22_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_m_reset_out = laguna_m_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_m_reset_in_d <= laguna_m_reset_in;\n      aresetn_d <= C_CHANNEL==P_FORWARD ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? areset_dly[15]  : laguna_m_reset_in_d;\n      laguna_m_reset_out_i <= areset_d;  // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n  \n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* keep=\"true\" *)  reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      ready_d <= {ready_d, laguna_m_ready_d}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid_q;\n      assign payload_valid_d = (p==0) ? (S_VALID & s_ready_i) : handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==C_PIPELINES) begin\n          laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else if (p==0) begin\n          payload_data <= S_PAYLOAD_DATA;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n      \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_s_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* keep=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_s_reset_out = laguna_s_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_s_reset_in_d <= laguna_s_reset_in;\n      aresetn_d <= C_CHANNEL==P_RESPONSE ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? laguna_s_reset_in_d : areset_dly[15];\n      laguna_s_reset_out_i <= areset_d;  // For forward channels, reflect laguna_s_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n\n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    wire laguna_s_handshake_q;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      laguna_s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n        \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n        \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)  \n      )\n      srl_fifo_0\n      (\n       .aclk    (ACLK),    \n       .areset  (areset_d),  \n       .aclear  (ACLEAR),\n       .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n       .s_valid (push), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      ); \n  \n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  reg areset_d = 1'b0;\n  reg [3:0] areset_dly = 4'b0;\n  always @(posedge ACLK) begin\n    areset_dly <= {4{~ARESETN}} | (areset_dly<<1);\n    areset_d <= areset_dly[3];\n  end\n  \n  if (1) begin : common\n    reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID & s_ready_i;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* keep=\"true\" *)  reg payload_valid = 1'b0;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          payload_data <= S_PAYLOAD_DATA;\n          payload_valid <= S_VALID & s_ready_i & ~areset_d;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n          payload_valid <= handshake_i[((p>0)?(p-1):0)];\n        end\n      end\n    end\n    \n    if (C_PIPELINES==0) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),\n         .aclear  (1'b0),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire                        aclear,  // Async clear\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    wire [1:0] state;  // State vector register\n    reg  [1:0] next;           // Next state value\n    wire [1:0] next_qual;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    reg  m_valid_d;\n    wire m_valid_q;\n    \n    assign m_valid = m_valid_q;\n    assign next_qual = areset ? K_EMPTY : next;\n    assign m_mesg  = mesg_reg;\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_mvalid_inst (\n        .Q   (m_valid_q),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (m_valid_d)\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state0_inst (\n        .Q   (state[0]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[0])\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state1_inst (\n        .Q   (state[1]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[1])\n     );\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      m_valid_d = m_valid_q & ~areset;\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid & ~areset) begin\n            next = K_HAS1;\n            m_valid_d = 1'b0;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              m_valid_d = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n              m_valid_d = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          m_valid_d = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      (* keep_hierarchy = \"yes\" *) axi_register_slice_v2_1_22_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule  // axic_reg_srl_fifo\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   //   16 -> Auto-pipelining\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_RESERVE_MODE = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n  \n  if (C_RESERVE_MODE==1) begin : gen_reserve_si\n  \n    axi_register_slice_v2_1_22_test_slave #(\n      .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n      .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n      .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n      .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n      .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n      .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n      .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n      .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n      .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .s_axi_awaddr(s_axi_awaddr),\n      .s_axi_awprot(s_axi_awprot),\n      .s_axi_awvalid(s_axi_awvalid),\n      .s_axi_awready(s_axi_awready),\n      .s_axi_awsize(s_axi_awsize),\n      .s_axi_awburst(s_axi_awburst),\n      .s_axi_awcache(s_axi_awcache),\n      .s_axi_awlen(s_axi_awlen),\n      .s_axi_awlock(s_axi_awlock),\n      .s_axi_awqos(s_axi_awqos),\n      .s_axi_awregion(s_axi_awregion),\n      .s_axi_awid(s_axi_awid),\n      .s_axi_awuser(s_axi_awuser),\n      .s_axi_wdata(s_axi_wdata),\n      .s_axi_wstrb(s_axi_wstrb),\n      .s_axi_wvalid(s_axi_wvalid),\n      .s_axi_wready(s_axi_wready),\n      .s_axi_wlast(s_axi_wlast),\n      .s_axi_wid(s_axi_wid),\n      .s_axi_wuser(s_axi_wuser),\n      .s_axi_bresp(s_axi_bresp),\n      .s_axi_bvalid(s_axi_bvalid),\n      .s_axi_bready(s_axi_bready),\n      .s_axi_buser(s_axi_buser),\n      .s_axi_bid(s_axi_bid),\n      .s_axi_araddr(s_axi_araddr),\n      .s_axi_arprot(s_axi_arprot),\n      .s_axi_arvalid(s_axi_arvalid),\n      .s_axi_arready(s_axi_arready),\n      .s_axi_arsize(s_axi_arsize),\n      .s_axi_arburst(s_axi_arburst),\n      .s_axi_arcache(s_axi_arcache),\n      .s_axi_arlock(s_axi_arlock),\n      .s_axi_arlen(s_axi_arlen),\n      .s_axi_arqos(s_axi_arqos),\n      .s_axi_arregion(s_axi_arregion),\n      .s_axi_aruser(s_axi_aruser),\n      .s_axi_arid(s_axi_arid),\n      .s_axi_rdata(s_axi_rdata),\n      .s_axi_rresp(s_axi_rresp),\n      .s_axi_rvalid(s_axi_rvalid),\n      .s_axi_rready(s_axi_rready),\n      .s_axi_rlast(s_axi_rlast),\n      .s_axi_ruser(s_axi_ruser),\n      .s_axi_rid(s_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign m_axi_awid     = 0;\n     assign m_axi_awaddr   = 0;\n     assign m_axi_awlen    = 0;\n     assign m_axi_awsize   = 0;\n     assign m_axi_awburst  = 0;\n     assign m_axi_awlock   = 0;\n     assign m_axi_awcache  = 0;\n     assign m_axi_awprot   = 0;\n     assign m_axi_awregion = 0;\n     assign m_axi_awqos    = 0;\n     assign m_axi_awuser   = 0;\n     assign m_axi_awvalid  = 0;\n     assign m_axi_wid      = 0;\n     assign m_axi_wdata    = 0;\n     assign m_axi_wstrb    = 0;\n     assign m_axi_wlast    = 0;\n     assign m_axi_wuser    = 0;\n     assign m_axi_wvalid   = 0;\n     assign m_axi_bready   = 0;\n     assign m_axi_arid     = 0;\n     assign m_axi_araddr   = 0;\n     assign m_axi_arlen    = 0;\n     assign m_axi_arsize   = 0;\n     assign m_axi_arburst  = 0;\n     assign m_axi_arlock   = 0;\n     assign m_axi_arcache  = 0;\n     assign m_axi_arprot   = 0;\n     assign m_axi_arregion = 0;\n     assign m_axi_arqos    = 0;\n     assign m_axi_aruser   = 0;\n     assign m_axi_arvalid  = 0;\n     assign m_axi_rready   = 0;\n      \n  end else if (C_RESERVE_MODE==2) begin : gen_reserve_mi\n    \n    axi_register_slice_v2_1_22_test_master #(\n    .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n    .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .m_axi_awaddr(m_axi_awaddr),\n      .m_axi_awprot(m_axi_awprot),\n      .m_axi_awvalid(m_axi_awvalid),\n      .m_axi_awready(m_axi_awready),\n      .m_axi_awsize(m_axi_awsize),\n      .m_axi_awburst(m_axi_awburst),\n      .m_axi_awcache(m_axi_awcache),\n      .m_axi_awlen(m_axi_awlen),\n      .m_axi_awlock(m_axi_awlock),\n      .m_axi_awqos(m_axi_awqos),\n      .m_axi_awid(m_axi_awid),\n      .m_axi_awuser(m_axi_awuser),\n      .m_axi_wid(m_axi_wid),\n      .m_axi_wdata(m_axi_wdata),\n      .m_axi_wstrb(m_axi_wstrb),\n      .m_axi_wvalid(m_axi_wvalid),\n      .m_axi_wready(m_axi_wready),\n      .m_axi_wlast(m_axi_wlast),\n      .m_axi_wuser(m_axi_wuser),\n      .m_axi_bresp(m_axi_bresp),\n      .m_axi_bvalid(m_axi_bvalid),\n      .m_axi_bready(m_axi_bready),\n      .m_axi_buser(m_axi_buser),\n      .m_axi_bid(m_axi_bid),\n      .m_axi_araddr(m_axi_araddr),\n      .m_axi_arprot(m_axi_arprot),\n      .m_axi_arvalid(m_axi_arvalid),\n      .m_axi_arready(m_axi_arready),\n      .m_axi_arsize(m_axi_arsize),\n      .m_axi_arburst(m_axi_arburst),\n      .m_axi_arcache(m_axi_arcache),\n      .m_axi_arlen(m_axi_arlen),\n      .m_axi_arlock(m_axi_arlock),\n      .m_axi_arqos(m_axi_arqos),\n      .m_axi_arid(m_axi_arid),\n      .m_axi_aruser(m_axi_aruser),\n      .m_axi_rdata(m_axi_rdata),\n      .m_axi_rresp(m_axi_rresp),\n      .m_axi_rvalid(m_axi_rvalid),\n      .m_axi_rready(m_axi_rready),\n      .m_axi_rlast(m_axi_rlast),\n      .m_axi_ruser(m_axi_ruser),\n      .m_axi_rid(m_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign s_axi_awready = 0;\n     assign s_axi_wready  = 0;\n     assign s_axi_bid     = 0;\n     assign s_axi_bresp   = 0;\n     assign s_axi_buser   = 0;\n     assign s_axi_bvalid  = 0;\n     assign s_axi_arready = 0;\n     assign s_axi_rid     = 0;\n     assign s_axi_rdata   = 0;\n     assign s_axi_rresp   = 0;\n     assign s_axi_rlast   = 0;\n     assign s_axi_ruser   = 0;\n     assign s_axi_rvalid  = 0;\n\n  end else begin : gen_reg_slice  // Any normal reg-slice mode\n\n    axi_infrastructure_v1_1_0_axi2vector #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    axi2vector_0 ( \n      .s_axi_awid      ( s_axi_awid      ) ,\n      .s_axi_awaddr    ( s_axi_awaddr    ) ,\n      .s_axi_awlen     ( s_axi_awlen     ) ,\n      .s_axi_awsize    ( s_axi_awsize    ) ,\n      .s_axi_awburst   ( s_axi_awburst   ) ,\n      .s_axi_awlock    ( s_axi_awlock    ) ,\n      .s_axi_awcache   ( s_axi_awcache   ) ,\n      .s_axi_awprot    ( s_axi_awprot    ) ,\n      .s_axi_awqos     ( s_axi_awqos     ) ,\n      .s_axi_awuser    ( s_axi_awuser    ) ,\n      .s_axi_awregion  ( s_axi_awregion  ) ,\n      .s_axi_wid       ( s_axi_wid       ) ,\n      .s_axi_wdata     ( s_axi_wdata     ) ,\n      .s_axi_wstrb     ( s_axi_wstrb     ) ,\n      .s_axi_wlast     ( s_axi_wlast     ) ,\n      .s_axi_wuser     ( s_axi_wuser     ) ,\n      .s_axi_bid       ( s_axi_bid       ) ,\n      .s_axi_bresp     ( s_axi_bresp     ) ,\n      .s_axi_buser     ( s_axi_buser     ) ,\n      .s_axi_arid      ( s_axi_arid      ) ,\n      .s_axi_araddr    ( s_axi_araddr    ) ,\n      .s_axi_arlen     ( s_axi_arlen     ) ,\n      .s_axi_arsize    ( s_axi_arsize    ) ,\n      .s_axi_arburst   ( s_axi_arburst   ) ,\n      .s_axi_arlock    ( s_axi_arlock    ) ,\n      .s_axi_arcache   ( s_axi_arcache   ) ,\n      .s_axi_arprot    ( s_axi_arprot    ) ,\n      .s_axi_arqos     ( s_axi_arqos     ) ,\n      .s_axi_aruser    ( s_axi_aruser    ) ,\n      .s_axi_arregion  ( s_axi_arregion  ) ,\n      .s_axi_rid       ( s_axi_rid       ) ,\n      .s_axi_rdata     ( s_axi_rdata     ) ,\n      .s_axi_rresp     ( s_axi_rresp     ) ,\n      .s_axi_rlast     ( s_axi_rlast     ) ,\n      .s_axi_ruser     ( s_axi_ruser     ) ,\n      .s_awpayload ( s_awpayload ) ,\n      .s_wpayload  ( s_wpayload  ) ,\n      .s_bpayload  ( s_bpayload  ) ,\n      .s_arpayload ( s_arpayload ) ,\n      .s_rpayload  ( s_rpayload  ) \n    );\n    \n    axi_infrastructure_v1_1_0_vector2axi #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    vector2axi_0 ( \n      .m_awpayload    ( m_awpayload    ) ,\n      .m_wpayload     ( m_wpayload     ) ,\n      .m_bpayload     ( m_bpayload     ) ,\n      .m_arpayload    ( m_arpayload    ) ,\n      .m_rpayload     ( m_rpayload     ) ,\n      .m_axi_awid     ( m_axi_awid     ) ,\n      .m_axi_awaddr   ( m_axi_awaddr   ) ,\n      .m_axi_awlen    ( m_axi_awlen    ) ,\n      .m_axi_awsize   ( m_axi_awsize   ) ,\n      .m_axi_awburst  ( m_axi_awburst  ) ,\n      .m_axi_awlock   ( m_axi_awlock   ) ,\n      .m_axi_awcache  ( m_axi_awcache  ) ,\n      .m_axi_awprot   ( m_axi_awprot   ) ,\n      .m_axi_awqos    ( m_axi_awqos    ) ,\n      .m_axi_awuser   ( m_axi_awuser   ) ,\n      .m_axi_awregion ( m_axi_awregion ) ,\n      .m_axi_wid      ( m_axi_wid      ) ,\n      .m_axi_wdata    ( m_axi_wdata    ) ,\n      .m_axi_wstrb    ( m_axi_wstrb    ) ,\n      .m_axi_wlast    ( m_axi_wlast    ) ,\n      .m_axi_wuser    ( m_axi_wuser    ) ,\n      .m_axi_bid      ( m_axi_bid      ) ,\n      .m_axi_bresp    ( m_axi_bresp    ) ,\n      .m_axi_buser    ( m_axi_buser    ) ,\n      .m_axi_arid     ( m_axi_arid     ) ,\n      .m_axi_araddr   ( m_axi_araddr   ) ,\n      .m_axi_arlen    ( m_axi_arlen    ) ,\n      .m_axi_arsize   ( m_axi_arsize   ) ,\n      .m_axi_arburst  ( m_axi_arburst  ) ,\n      .m_axi_arlock   ( m_axi_arlock   ) ,\n      .m_axi_arcache  ( m_axi_arcache  ) ,\n      .m_axi_arprot   ( m_axi_arprot   ) ,\n      .m_axi_arqos    ( m_axi_arqos    ) ,\n      .m_axi_aruser   ( m_axi_aruser   ) ,\n      .m_axi_arregion ( m_axi_arregion ) ,\n      .m_axi_rid      ( m_axi_rid      ) ,\n      .m_axi_rdata    ( m_axi_rdata    ) ,\n      .m_axi_rresp    ( m_axi_rresp    ) ,\n      .m_axi_rlast    ( m_axi_rlast    ) ,\n      .m_axi_ruser    ( m_axi_ruser    ) \n    );\n    \n  end  // Reserve SI/MI branch\n\n  if ((C_REG_CONFIG_AW <= 9) && (C_RESERVE_MODE==0)) begin : aw\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 15) && (C_RESERVE_MODE==0)) begin : aw15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 16) && (C_RESERVE_MODE==0)) begin : aw16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) \n    )\n    aw_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if ((C_REG_CONFIG_W <= 9) && (C_RESERVE_MODE==0)) begin : w\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 15) && (C_RESERVE_MODE==0)) begin : w15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 16) && (C_RESERVE_MODE==0)) begin : w16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) \n    )\n    w_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if ((C_REG_CONFIG_B <= 9) && (C_RESERVE_MODE==0)) begin : b\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if ((C_REG_CONFIG_B == 15) && (C_RESERVE_MODE==0)) begin : b15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if ((C_REG_CONFIG_B == 16) && (C_RESERVE_MODE==0)) begin : b16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) \n    )\n    b_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if ((C_REG_CONFIG_AR <= 9) && (C_RESERVE_MODE==0)) begin : ar\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 15) && (C_RESERVE_MODE==0)) begin : ar15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 16) && (C_RESERVE_MODE==0)) begin : ar16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) \n    )\n    ar_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if ((C_REG_CONFIG_R <= 9) && (C_RESERVE_MODE==0)) begin : r\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 15) && (C_RESERVE_MODE==0)) begin : r15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 16) && (C_RESERVE_MODE==0)) begin : r16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) \n    )\n    r_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 4844}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(1),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(1),\n    .C_REG_CONFIG_AR(1),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"axi_register_slice,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"axi_register_slice,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=16,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=1,C_REG_CONFIG_W=1,\\\nC_REG_CONFIG_B=1,C_REG_CONFIG_AR=1,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(1),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(1),\n    .C_REG_CONFIG_AR(1),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_master #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_SUPPORTS_NARROW = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1,\n   parameter [C_AXI_ADDR_WIDTH-1:0] C_AXI_ADDR = 0,  // Base address\n   parameter integer C_NUM_ADDR = 1,  // Number of address iterations; range 1..2**16 (fixed increment = 32'h10000\n   parameter integer C_NUM_ID = 1,  // Number of ID iterations; range 1..2**C_ID_WIDTH (base = 0; fixed increment = 1)\n   parameter integer C_NUM_LEN = 1,  // Number of LEN iterations; range 1..9 (base = 0; value = 2**i - 1)\n   parameter integer C_NUM_TRANS = 1  // Number of transactions; range >=1 (read and write)\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_awvalid,\n  input  wire                            m_axi_awready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_awburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_awlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_awlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_awid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]    m_axi_awuser = 'b0,\n  /**************** Write Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_wid,\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]      m_axi_wdata,\n  (* dont_touch=\"true\" *) output reg [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb = {(C_AXI_DATA_WIDTH/8){1'b1}},\n  (* dont_touch=\"true\" *) output wire                             m_axi_wvalid,\n  input  wire                            m_axi_wready,\n  (* dont_touch=\"true\" *) output wire                             m_axi_wlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]     m_axi_wuser = 'b0,\n  /**************** Write Response Channel Signals ****************/\n  input  wire [2-1:0]                    m_axi_bresp,\n  input  wire                            m_axi_bvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_bready,\n  input  wire [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]     m_axi_buser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_bid,\n  /**************** Read Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_arvalid,\n  input  wire                            m_axi_arready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_arburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_arlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_arlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_arid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]    m_axi_aruser = 'b0,\n  /**************** Read Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]      m_axi_rdata,\n  input  wire [2-1:0]                    m_axi_rresp,\n  input  wire                            m_axi_rvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_rready,\n  input  wire                            m_axi_rlast,\n  input  wire [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]     m_axi_ruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_rid,\n  /**************** System Signals ****************/\n  input  wire                            aclk,\n  input  wire                            aresetn\n  );\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n  localparam integer  P_NUM_ID_LOG = f_ceil_log2(C_NUM_ID);\n  localparam integer  P_NUM_ADDR_LOG = f_ceil_log2(C_NUM_ADDR);\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL==0 ? 8 : C_AXI_PROTOCOL==1 ? 4 : 1);\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer               P_M_AXI_DATA_BYTES = (C_AXI_DATA_WIDTH / 8);\n  localparam integer               P_M_AXI_DONE_WIDTH = f_ceil_log2(C_NUM_TRANS<2?2:C_NUM_TRANS);\n  localparam integer               P_M_AXI_SIZE = f_ceil_log2(C_AXI_DATA_WIDTH)-3;\n\n  /**************** Internal Wires/Regs - Global ****************/\n   wire                            done;\n    wire                            dummy ;\n  reg                         done_i;\n  reg                         done_sel;\n  wire                         done_cycle;\n  reg                          done_d1 = 1'b0;\n  reg                   areset = 1'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] arcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] rcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [3:0]                    acc_r_i = 4'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] awcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] wcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] bcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [2:0]                    acc_b_i = 3'b0;\n\n  // Register Reset\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    \n    /**************** Internal Wires/Regs - Read Channels ****************/\n    wire                         read_xaction_done_i;\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_arid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_ADDR_WIDTH:0]      araddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  arprot_i = 3'b0;\n    reg [3-1:0]                  arsize_i = 3'b0;\n    reg [2-1:0]                  arburst_i = 2'b0;\n    reg [4-1:0]                  arcache_i = 4'b0;\n    reg [2-1:0]                  arlock_i = 2'b0;\n    reg [P_LEN_WIDTH-1:0]     arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [4-1:0]                  arqos_i = 4'b0;\n    reg [P_ID_WIDTH-1:0]        arid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [2-1:0]                  rresp_i = 2'b00;\n    reg [C_AXI_RUSER_WIDTH:0]   ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      rid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_arvalid_i = 1'b0;\n    reg                        m_axi_rready_i = 1'b0;\n    reg [P_NUM_ADDR_LOG:0]    araddr_cnt = 0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign read_xaction_done_i = m_axi_rvalid && m_axi_rready_i && ((C_AXI_PROTOCOL==2)?1'b1:m_axi_rlast);\n    assign m_axi_arvalid = m_axi_arvalid_i;\n    assign m_axi_rready = m_axi_rready_i;\n    assign m_axi_araddr = m_axi_araddr_i;\n    assign m_axi_arlen = m_axi_arlen_i;\n    always @(posedge aclk) begin\n      m_axi_arprot <= dummy ? arprot_i : 3'b000;\n      m_axi_arsize <= dummy ? arsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_arburst <= dummy ? arburst_i : 2'b01;\n      m_axi_arlock <= dummy ? arlock_i : 1'b0;\n      m_axi_arcache <= dummy ? arcache_i : 4'h3;\n      m_axi_arqos <= dummy  ? arqos_i : 4'h0;\n      m_axi_aruser <= dummy ? aruser_i : 0;\n    end\n  \n    //**********************************************\n    // Read Channel: ARVALID, ARADDR, ARLEN, RREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_arvalid_i <= 1'b0;\n        arcnt_i <= C_NUM_TRANS;\n        m_axi_arlen_i <= 0;\n        m_axi_araddr_i <= C_AXI_ADDR;\n        m_axi_arid_i <= 1;\n        araddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_arready & m_axi_arvalid_i) begin\n          arcnt_i <= arcnt_i - 1;\n          if (araddr_cnt == 1) begin\n            m_axi_araddr_i <= dummy ? araddr_i : C_AXI_ADDR;\n            araddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_araddr_i <= m_axi_araddr_i + 32'h10000;\n            araddr_cnt <= araddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_arlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_arlen_i <= dummy ? arlen_i : 0;\n          end else begin\n            m_axi_arlen_i <= (m_axi_arlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_arid_i == C_NUM_ID)) begin\n            m_axi_arid <= dummy ? arid_i : 0;\n            m_axi_arid_i <= 1;\n          end else begin\n            m_axi_arid <= m_axi_arid_i;\n            m_axi_arid_i <= m_axi_arid_i + 1;\n          end\n          if (arcnt_i == 1) begin\n            m_axi_arvalid_i <= 1'b0;\n          end\n        end else if (arcnt_i != 0) begin\n          m_axi_arvalid_i <= 1'b1;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      araddr_i <= {araddr_i, ~araddr_i[C_AXI_ADDR_WIDTH]};\n      arprot_i <= {arprot_i, ~arprot_i[3-1]};\n      arlen_i <= {arlen_i, ~arlen_i[P_LEN_WIDTH-1]};\n      arsize_i <= {arsize_i, ~arsize_i[3-1]};\n      arburst_i <= {arburst_i, ~arburst_i[2-1]};\n      arlock_i <= {arlock_i, ~arlock_i[2-1]};\n      arcache_i <= {arcache_i, ~arcache_i[4-1]};\n      arqos_i <= {arqos_i, ~arqos_i[4-1]};\n      aruser_i <= {aruser_i, ~aruser_i[C_AXI_ARUSER_WIDTH]};\n      arid_i <= {arid_i, ~arid_i[P_ID_WIDTH-1]};\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        m_axi_rready_i <= 1'b0;\n        rcnt_i <= C_NUM_TRANS;\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        rresp_i <= {2{1'b0}};\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n        rid_i <= {P_ID_WIDTH{1'b0}};\n        acc_r_i <= 4'b0;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_rvalid & m_axi_rready_i) begin\n          m_axi_rready_i <= 1'b0;\n          rdata_i <= m_axi_rdata;\n            acc_r_i[0] <= rdata_i[0];\n          rresp_i <= m_axi_rresp;\n            acc_r_i[1] <= rresp_i[0];\n          ruser_i <= m_axi_ruser;\n            acc_r_i[2] <= ruser_i[0];\n          rid_i <= m_axi_rid;\n            acc_r_i[3] <= rid_i[0];\n          if (m_axi_rlast) begin\n            rcnt_i <= rcnt_i - 1;\n          end\n        end else begin\n          rdata_i <= rdata_i>>1;\n          rresp_i <= rresp_i>>1;\n          ruser_i <= ruser_i>>1;\n          rid_i <= rid_i>>1;\n          acc_r_i <= acc_r_i>>1;\n          if (m_axi_rvalid) begin\n            m_axi_rready_i <= 1'b1;\n          end\n        end\n      end\n    end\n    \n    assign dummy = rdata_i[0];\n    \n    \n\n    /**************** Internal Wires/Regs - Write Channels ****************/\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_awid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [8-1:0]                  xfer_w_i = 8'h00;\n    wire                         write_burst_done_i;\n    reg [C_AXI_ADDR_WIDTH:0]      awaddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  awprot_i = 3'b0;\n    reg [P_LEN_WIDTH-1:0]     awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [3-1:0]                  awsize_i = 3'b0;\n    reg [2-1:0]                  awburst_i = 2'b0;\n    reg [4-1:0]                  awcache_i = 4'b0;\n    reg [2-1:0]                  awlock_i = 2'b0;\n    reg [4-1:0]                  awqos_i = 4'b0;\n    reg [P_ID_WIDTH:0]        awid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_AWUSER_WIDTH:0]    awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg [P_M_AXI_DATA_BYTES-1:0] wstrb_i = {P_M_AXI_DATA_BYTES{1'b1}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]        wid_i = {P_ID_WIDTH{1'b0}};\n    reg [2-1:0]                  bresp_i = 2'b00;\n    reg [C_AXI_BUSER_WIDTH:0]   buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      bid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_awvalid_i = 1'b0;\n    reg                        m_axi_wvalid_i = 1'b0;\n    reg                        m_axi_bready_i = 1'b0;\n    reg                        m_axi_wlast_i = 1'b0;\n    reg                        m_axi_wid_i = {P_ID_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]     wlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [P_NUM_ADDR_LOG:0]    awaddr_cnt = 0;\n  \n    /**************** Assign Write Channel Outputs ****************/\n    assign m_axi_wdata = {wdata_i, done};\n    assign write_burst_done_i = m_axi_wready && m_axi_wvalid_i && ((C_AXI_PROTOCOL==2) || m_axi_wlast_i);\n    assign m_axi_awvalid = m_axi_awvalid_i;\n    assign m_axi_wvalid = m_axi_wvalid_i;\n    assign m_axi_bready = m_axi_bready_i;\n    assign m_axi_wlast = m_axi_wlast_i;\n    assign m_axi_awaddr = m_axi_awaddr_i;\n    assign m_axi_awlen = m_axi_awlen_i;\n    assign m_axi_wid = m_axi_wid_i;\n    always @(posedge aclk) begin\n      m_axi_awprot <= dummy ? awprot_i : 3'b000;\n      m_axi_awsize <= dummy ? awsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_awburst <= dummy ? awburst_i : 2'b01;\n      m_axi_awlock <= dummy ? awlock_i : 1'b0;\n      m_axi_awcache <= dummy ? awcache_i : 4'h3;\n      m_axi_awqos <= dummy ? awqos_i : 4'h0;\n      m_axi_wstrb <= dummy ? wstrb_i : {P_M_AXI_DATA_BYTES{1'b1}};\n      m_axi_awuser <= dummy ?  awuser_i : 0;\n      m_axi_wuser <= dummy ?  wuser_i : 0;\n    end\n  \n    //**********************************************\n    // Write Channel: AWVALID, AWADDR, AWLEN, WVALID, WLAST, BREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_awvalid_i <= 1'b0;\n        m_axi_wvalid_i <= 1'b0;\n        awcnt_i <= C_NUM_TRANS;\n        wcnt_i <= C_NUM_TRANS;\n        xfer_w_i <= 8'h00;\n        m_axi_awlen_i <= 0;\n        m_axi_awaddr_i <= C_AXI_ADDR;\n        m_axi_awid_i <= 1;\n        m_axi_wid_i <= 0;\n        m_axi_wlast_i <= 1'b0;\n        wlen_i <= 0;\n        wid_i <= 0;\n        awaddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_awvalid_i <= 1'b0;\n          awcnt_i <= awcnt_i - 1;\n          if (awaddr_cnt == 1) begin\n            m_axi_awaddr_i <= dummy ? awaddr_i : C_AXI_ADDR;\n            awaddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_awaddr_i <= m_axi_awaddr_i + 32'h10000;\n            awaddr_cnt <= awaddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_awlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_awlen_i <= dummy ? awlen_i : 0;\n          end else begin\n            m_axi_awlen_i <= (m_axi_awlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_awid_i == C_NUM_ID)) begin\n            m_axi_awid <= dummy ? awid_i : 0;\n            m_axi_awid_i <= 1;\n          end else begin\n            m_axi_awid <= m_axi_awid_i;\n            m_axi_awid_i <= m_axi_awid_i + 1;\n          end\n        end else if (~m_axi_wvalid_i) begin\n          if (awcnt_i != 0) begin\n            m_axi_awvalid_i <= 1'b1;\n          end\n        end\n  \n        /**************** Write Data Channel ****************/\n\n        if (m_axi_wready && m_axi_wvalid_i) begin\n          xfer_w_i <= xfer_w_i - 1'b1;\n          if (m_axi_wlast_i) begin\n            m_axi_wvalid_i <= 1'b0;\n            wcnt_i <= wcnt_i - 1'b1;\n          end else begin\n            m_axi_wlast_i <=  (xfer_w_i == 1);\n          end\n        end else if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_wvalid_i <= 1'b1;\n          xfer_w_i <= m_axi_awlen_i;\n          m_axi_wlast_i <= (m_axi_awlen_i==0);\n          m_axi_wid_i <= m_axi_awid_i;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: WDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        wdata_i <= (m_axi_wvalid_i && m_axi_wready) ? {wdata_i[C_AXI_DATA_WIDTH-2 : 0], ~wdata_i[C_AXI_DATA_WIDTH-1]} : wdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      awaddr_i <= {awaddr_i, ~awaddr_i[C_AXI_ADDR_WIDTH]};\n      awprot_i <= {awprot_i[3-2:0], ~awprot_i[3-1]};\n      wstrb_i <= {wstrb_i, ~wstrb_i[C_AXI_DATA_WIDTH/8-1]};\n      awlen_i <= {awlen_i, ~awlen_i[P_LEN_WIDTH-1]};\n      awsize_i <= {awsize_i, ~awsize_i[3-1]};\n      awburst_i <= {awburst_i, ~awburst_i[2-1]};\n      awlock_i <= {awlock_i, ~awlock_i[2-1]};\n      awcache_i <= {awcache_i, ~awcache_i[4-1]};\n      awqos_i <= {awqos_i, ~awqos_i[4-1]};\n      awid_i <= {awid_i, ~awid_i[P_ID_WIDTH-1]};\n      awuser_i <= {awuser_i, ~awuser_i[C_AXI_AWUSER_WIDTH]};\n      wuser_i <= {wuser_i, ~wuser_i[C_AXI_WUSER_WIDTH]};\n    end\n  \n    //**********************************************\n    // Write Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_bready_i <= 1'b0;\n        bcnt_i <= C_NUM_TRANS;\n        bresp_i <= {2{1'b0}};\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n        bid_i <= {P_ID_WIDTH{1'b0}};\n        acc_b_i <= 3'b0;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_bvalid & m_axi_bready_i) begin\n          m_axi_bready_i <= 1'b0;\n          bresp_i <= m_axi_bresp;\n            acc_b_i[0] <= bresp_i[0];\n          buser_i <= m_axi_buser;\n            acc_b_i[1] <= buser_i[0];\n          bid_i <= m_axi_bid;\n            acc_b_i[2] <= bid_i[0];\n          bcnt_i <= bcnt_i - 1;\n        end else begin\n          bresp_i <= bresp_i>>1;\n          buser_i <= buser_i>>1;\n          bid_i <= bid_i>>1;\n          acc_b_i <= acc_b_i>>1;\n          if (m_axi_bvalid) begin\n            m_axi_bready_i <= 1'b1;\n          end\n        end\n      end\n    end\n\n\n  //**********************************************\n  // Assert Done\n  //**********************************************\n  always @(posedge aclk) begin\n    if (~aresetn) begin\n      done_d1 <= 1'b0;\n    end else begin\n      done_d1 <= done_i;\n    end\n  end\n\n  assign done = done_sel ? done_i : done_d1;\n  assign done_cycle = done_i & ~done_d1;\n  \n  always @ * begin\n    if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_readonly_done\n       done_i = rcnt_i==0;\n       done_sel = acc_r_i[0];\n    end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_writeonly_done\n       done_i = bcnt_i==0;\n       done_sel = acc_b_i[0];\n    end else begin : gen_readwrite_done\n       done_i = (rcnt_i==0) && (bcnt_i==0);\n       done_sel = acc_r_i[0] ^ acc_b_i[0];\n    end\n  end\n  \nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n  input  wire [3-1:0]                   s_axi_awprot,\n  input  wire                           s_axi_awvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_awready,\n  input  wire [3-1:0]                   s_axi_awsize,\n  input  wire [2-1:0]                   s_axi_awburst,\n  input  wire [4-1:0]                   s_axi_awcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_awlen,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_awlock,\n  input  wire [4-1:0]                   s_axi_awqos,\n  input  wire [4-1:0]                   s_axi_awregion,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_awid,\n  input  wire [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]   s_axi_awuser,\n  /**************** Write Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n  input  wire                           s_axi_wvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_wready,\n  input  wire                           s_axi_wlast,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_wid,\n  input  wire [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]    s_axi_wuser,\n  /**************** Write Response Channel Signals ****************/\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_bresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_bvalid,\n  input  wire                           s_axi_bready,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]    s_axi_buser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_bid = 'b0,\n  /**************** Read Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n  input  wire [3-1:0]                   s_axi_arprot,\n  input  wire                           s_axi_arvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_arready,\n  input  wire [3-1:0]                   s_axi_arsize,\n  input  wire [2-1:0]                   s_axi_arburst,\n  input  wire [4-1:0]                   s_axi_arcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_arlock,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_arlen,\n  input  wire [4-1:0]                   s_axi_arqos,\n  input  wire [4-1:0]                   s_axi_arregion,\n  input  wire [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]   s_axi_aruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_arid,\n  /**************** Read Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_rresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rvalid,\n  input  wire                           s_axi_rready,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]    s_axi_ruser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_rid = 'b0,\n  /**************** System Signals ****************/\n  input  wire                           aclk,\n  input  wire                           aresetn\n   );\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL == 1) ? 4 : 8;\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer P_S_AXI_DATA_BYTES = 32/8;\n  localparam integer P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n\n  /**************** Internal Wires/Regs - Global ****************/\n  reg                   areset = 1'b0;\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    /**************** Internal Wires/Regs - Read Channels ****************/\n    reg [8-1:0]                   xfer_r_cnt = 8'h00;\n    reg [16-1:0]                  arcnt_i = 16'h0000;\n    wire                          read_xaction_done_i;\n    reg [C_AXI_DATA_WIDTH-1:0]     rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]      arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg                           arvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     araddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   arprot_i = 3'b000;\n    reg [3-1:0]                   arsize_i = 3'b000;\n    reg [2-1:0]                   arburst_i = 2'b00;\n    reg [4-1:0]                   arcache_i = 4'b0000;\n    reg [1-1:0]     arlock_i = 1'b0;\n    reg [4-1:0]                   arqos_i = 4'b0000;\n    reg [4-1:0]                   arregion_i = 4'b0000;\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_RUSER_WIDTH:0]     ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_ar_i = 9'b0;\n    reg                           s_axi_rvalid_i = 1'b0;\n    reg                           s_axi_arready_i = 1'b0;\n    reg                           s_axi_rlast_i = 1'b0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign s_axi_rdata = rdata_i;\n    assign read_xaction_done_i = (s_axi_rready && s_axi_rvalid_i && s_axi_rlast_i);\n    assign s_axi_rvalid = s_axi_rvalid_i;\n    assign s_axi_arready = s_axi_arready_i;\n    assign s_axi_rlast = s_axi_rlast_i;\n    //**********************************************\n    // Read Channel: ARREADY, RVALID, RLAST, RID\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        xfer_r_cnt <= 8'h00;\n        arcnt_i <= 16'h0000;\n        arlen_i <= {P_LEN_WIDTH{1'b0}};\n        s_axi_rlast_i <= 1'b0;\n      end else begin\n        /**************** Read Address Channel ****************/\n        // arready\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_arready_i <= 1'b0;\n          arcnt_i <= arcnt_i + 1'b1;\n        end else if (~s_axi_rvalid_i) begin\n          s_axi_arready_i <= 1'b1;\n        end\n  \n        /**************** Read Data Channel ****************/\n        // rvalid\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_rvalid_i <= 1'b1;\n          s_axi_rid <= s_axi_arid;\n          s_axi_ruser <= ruser_i;\n        end else if(read_xaction_done_i) begin\n          s_axi_rvalid_i <= 1'b0;\n        end\n  \n        // rlast\n        if(s_axi_rready && s_axi_rvalid_i) begin\n          xfer_r_cnt <= xfer_r_cnt - 1;\n          if(xfer_r_cnt == 1) begin\n            s_axi_rlast_i <= 1'b1;\n          end\n        end else if(s_axi_arready_i && s_axi_arvalid) begin\n          xfer_r_cnt <= s_axi_arlen;\n          s_axi_rlast_i <= (s_axi_arlen==0);\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Read Channel: RDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        rdata_i <= (s_axi_rready && s_axi_rvalid_i) ? {rdata_i[C_AXI_DATA_WIDTH-2 : 0], ~rdata_i[C_AXI_DATA_WIDTH-1]} : rdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_rresp <= {2{1'b0}};\n      end else if (~s_axi_rvalid_i) begin\n        s_axi_rresp <= {acc_ar_i[0], 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n      end else begin\n        ruser_i <= (s_axi_arready_i && s_axi_arvalid) ? {ruser_i, ~ruser_i[C_AXI_RUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        araddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        arprot_i <= {3{1'b0}};\n        arsize_i <= {3{1'b0}};\n        arburst_i <= {2{1'b0}};\n        arcache_i <= {4{1'b0}};\n        arlock_i <= {1{1'b0}};\n        arqos_i <= {4{1'b0}};\n        arregion_i <= {4{1'b0}};\n        aruser_i <= {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n        acc_ar_i <= 9'b0;\n      end else if (s_axi_arvalid) begin\n        // Register Inputs\n        araddr_i <= s_axi_araddr;\n          acc_ar_i[0] <= araddr_i[0];\n        arprot_i <= s_axi_arprot;\n          acc_ar_i[1] <= arprot_i[0];\n        arsize_i <= s_axi_arsize;\n          acc_ar_i[2] <= arsize_i[0];\n        arburst_i <= s_axi_arburst;\n          acc_ar_i[3] <= arburst_i[0];\n        arcache_i <= s_axi_arcache;\n          acc_ar_i[4] <= arcache_i[0];\n        arlock_i <= s_axi_arlock;\n          acc_ar_i[5] <= arlock_i[0];\n        arqos_i <= s_axi_arqos;\n          acc_ar_i[6] <= arqos_i[0];\n        arregion_i <= s_axi_arregion;\n          acc_ar_i[7] <= arregion_i[0];\n        aruser_i <= s_axi_aruser;\n          acc_ar_i[8] <= aruser_i[0];\n      end else begin\n        araddr_i <= araddr_i>>1;\n        arprot_i <= arprot_i>>1;\n        arsize_i <= arsize_i>>1;\n        arburst_i <= arburst_i>>1;\n        arcache_i <= arcache_i>>1;\n        arlock_i <= arlock_i>>1;\n        arqos_i <= arqos_i>>1;\n        arregion_i <= arregion_i>>1;\n        aruser_i <= aruser_i>>1;\n        acc_ar_i <= acc_ar_i>>1;\n      end\n    end\n  \n  \n    /**************** Internal Wires/Regs - Write Channels ****************/\n    wire                          write_burst_done_i;\n    reg [16-1:0]                  awcnt_i = 16'h0000;\n    reg                           awvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     awaddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   awprot_i = 3'b000;\n    reg [3-1:0]                   awsize_i = 3'b000;\n    reg [2-1:0]                   awburst_i = 2'b00;\n    reg [4-1:0]                   awcache_i = 4'b0000;\n    reg [P_LEN_WIDTH-1:0]      awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [1-1:0]     awlock_i = 1'b0;\n    reg [4-1:0]                   awqos_i = 4'b0000;\n    reg [4-1:0]                   awregion_i = 4'b0000;\n    reg [C_AXI_AWUSER_WIDTH:0]     awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg                           wvalid_i = 1'b0;\n    reg [C_AXI_DATA_WIDTH-1:0]     wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH/8-1:0]   wstrb_i = {(C_AXI_DATA_WIDTH/8){1'b0}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_BUSER_WIDTH:0]     buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_aw_i = 9'b0;\n    reg [3:0]                     acc_w_i = 4'b0;\n    reg                           s_axi_bvalid_i = 1'b0;\n    reg                           s_axi_awready_i = 1'b0;\n    reg                           s_axi_wready_i = 1'b0;\n    /**************** Assign Write Channel Outputs ****************/\n    assign write_burst_done_i =s_axi_wready_i && s_axi_wvalid && ((C_AXI_PROTOCOL == 2) ? 1'b1 : s_axi_wlast);\n    assign s_axi_bvalid = s_axi_bvalid_i;\n    assign s_axi_awready = s_axi_awready_i;\n    assign s_axi_wready = s_axi_wready_i;\n  \n    //**********************************************\n    // Write Channel: AWREADY, WREADY, BVALID, BID\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awcnt_i <= 16'h0000;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        /**************** Write Address Channel ****************/\n        // awready\n        if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_awready_i <= 1'b0;\n          awcnt_i <= awcnt_i + 1'b1;\n          s_axi_bid <= s_axi_awid;\n          s_axi_buser <= buser_i;\n        end else if(~s_axi_wready_i & ~s_axi_bvalid_i) begin\n          s_axi_awready_i <= 1'b1;\n        end\n  \n        /**************** Write Data Channel ****************/\n        // wready\n        if(write_burst_done_i) begin\n          s_axi_wready_i <= 1'b0;\n        end else if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_wready_i <= 1'b1;\n        end\n  \n        /**************** Write Response Channel ****************/\n        // bvalid\n        if(write_burst_done_i) begin\n          s_axi_bvalid_i <= 1'b1;\n        end else if(s_axi_bready && s_axi_bvalid_i) begin\n          s_axi_bvalid_i <= 1'b0;\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Write Channel: BRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_bresp <= {2{1'b0}};\n      end else if (~s_axi_bvalid_i) begin\n        s_axi_bresp <= {(acc_aw_i[0] ^ acc_w_i[0]), 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: BUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (aresetn) begin\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n      end else begin\n        buser_i <= (s_axi_awready_i && s_axi_awvalid) ? {buser_i, ~buser_i[C_AXI_BUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Write Address Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awaddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        awprot_i <= {3{1'b0}};\n        awsize_i <= {3{1'b0}};\n        awburst_i <= {2{1'b0}};\n        awcache_i <= {4{1'b0}};\n        awlen_i <= {P_LEN_WIDTH{1'b0}};\n        awlock_i <= {1{1'b0}};\n        awqos_i <= {4{1'b0}};\n        awregion_i <= {4{1'b0}};\n        awuser_i <= {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n        acc_aw_i <= 9'b0;\n      end else if (s_axi_awvalid) begin\n        // Register Inputs\n        awaddr_i <= s_axi_awaddr;\n          acc_aw_i[0] <= awaddr_i[0];\n        awprot_i <= s_axi_awprot;\n          acc_aw_i[1] <= awprot_i[0];\n        awsize_i <= s_axi_awsize;\n          acc_aw_i[2] <= awsize_i[0];\n        awburst_i <= s_axi_awburst;\n          acc_aw_i[3] <= awburst_i[0];\n        awcache_i <= s_axi_awcache;\n          acc_aw_i[4] <= awcache_i[0];\n        awlock_i <= s_axi_awlock;\n          acc_aw_i[5] <= awlock_i[0];\n        awqos_i <= s_axi_awqos;\n          acc_aw_i[6] <= awqos_i[0];\n        awregion_i <= s_axi_awregion;\n          acc_aw_i[7] <= awregion_i[0];\n        awuser_i <= s_axi_awuser;\n          acc_aw_i[8] <= awuser_i[0];\n      end else begin\n        awaddr_i <= awaddr_i>>1;\n        awprot_i <= awprot_i>>1;\n        awsize_i <= awsize_i>>1;\n        awburst_i <= awburst_i>>1;\n        awcache_i <= awcache_i>>1;\n        awlock_i <= awlock_i>>1;\n        awqos_i <= awqos_i>>1;\n        awregion_i <= awregion_i>>1;\n        awuser_i <= awuser_i>>1;\n        acc_aw_i <= acc_aw_i>>1;\n      end\n    end\n  \n    //**********************************************\n    // Write Data Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        wstrb_i <= {(C_AXI_DATA_WIDTH/8){1'b0}};\n        wuser_i <= {(C_AXI_WUSER_WIDTH+1){1'b0}};\n        acc_w_i <= 4'b0;\n      end else if (s_axi_wvalid) begin\n        // Register Inputs\n        wdata_i <= s_axi_wdata;\n          acc_w_i[0] <= wdata_i[0];\n        wstrb_i <= s_axi_wstrb;\n          acc_w_i[1] <= wstrb_i[0];\n        wuser_i <= s_axi_wuser;\n          acc_w_i[2] <= wuser_i[0];\n      end else begin\n        wdata_i <= wdata_i>>1;\n        wstrb_i <= wstrb_i>>1;\n        wuser_i <= wuser_i>>1;\n        acc_w_i <= acc_w_i>>1;\n      end\n    end\n  \nendmodule\n\n\n\n//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_22_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \n(* autopipeline_module=\"yes\" *)\nmodule axi_register_slice_v2_1_22_auto_slr #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n    wire                    handshake_pipe;\n    wire                    ready_pipe;\n    wire [C_DATA_WIDTH-1:0] payload_pipe;\n    (* keep=\"true\" *)                                                                reg  s_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  s_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  s_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  s_areset_resp2 = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  m_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  m_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_areset_resp2 = 1'b0;\n    \n  // Global Reset pipelining\n  \n    always @(posedge ACLK) begin\n      s_aclear       <= ~ARESETN;\n      s_areset_fwd   <= ~ARESETN; \n      s_areset_resp  <= s_areset_fwd;  // Auto-pipeline\n      s_areset_resp2 <= s_areset_resp; // Auto-pipeline\n    end\n    \n    always @(posedge ACLK) begin\n      m_aclear       <= ~ARESETN;\n      m_areset_fwd   <= ~ARESETN; \n      m_areset_resp  <= m_areset_fwd;  // Auto-pipeline\n      m_areset_resp2 <= m_areset_resp; // Auto-pipeline\n    end\n    \n  // Source-side submodule\n    \n    axi_register_slice_v2_1_22_auto_src #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_src\n      (\n       .ACLK             (ACLK),    \n       .s_aclear         (s_aclear),\n       .s_areset_resp2   (s_areset_resp2),  \n       .S_VALID          (S_VALID),  \n       .S_READY          (S_READY), \n       .S_PAYLOAD_DATA   (S_PAYLOAD_DATA),\n       .ready_pipe        (ready_pipe), \n       .handshake_pipe    (handshake_pipe),\n       .payload_pipe      (payload_pipe)  \n      );\n    \n  // Destination-side submodule\n    \n    axi_register_slice_v2_1_22_auto_dest #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_dest\n      (\n       .ACLK           (ACLK),    \n       .m_aclear       (m_aclear),\n       .m_areset_resp2 (m_areset_resp2),  \n       .M_READY        (M_READY), \n       .M_VALID        (M_VALID),  \n       .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n       .handshake_pipe  (handshake_pipe),\n       .ready_pipe      (ready_pipe),  \n       .payload_pipe    (payload_pipe)  \n      );\n    \nendmodule  // auto_slr\n\nmodule axi_register_slice_v2_1_22_auto_src #\n  (\n   parameter integer C_DATA_WIDTH = 32\n  )\n  (\n   input  wire ACLK,\n   input  wire s_aclear,\n   input  wire s_areset_resp2,\n   input  wire S_VALID,\n   input  wire ready_pipe,\n   output wire S_READY,\n   output wire handshake_pipe,\n   output wire  [C_DATA_WIDTH-1:0] payload_pipe,\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA\n   );\n    \n   (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  [C_DATA_WIDTH-1:0] payload_pipe_r;\n    (* keep=\"true\" *) reg [2:0] s_aresetn_resp4 = 3'b000;\n    wire s_aresetn_resp3;\n    wire s_aresetn_d;\n    wire s_aresetn_q;\n    wire s_handshake_d;\n    wire s_ready_i;\n    \n    assign S_READY = s_ready_i & s_aresetn_q;\n    assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;\n    assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;\n    assign payload_pipe = payload_pipe_r;\n    \n    always @(posedge ACLK or posedge s_aclear) begin\n      if (s_aclear) begin\n        s_aresetn_resp4 <= 3'b000;\n      end else begin\n        s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      payload_pipe_r <= S_PAYLOAD_DATA;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) s_aresetn_resp3_inst (\n        .Q   (s_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~s_areset_resp2)\n     );\n    \n    // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (s_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_aresetn_d)\n     );\n    \n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (handshake_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_handshake_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (s_ready_i),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (ready_pipe)\n     );\n    \nendmodule  // auto_src\n\nmodule axi_register_slice_v2_1_22_auto_dest #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   input  wire ACLK,\n   input  wire m_aclear,\n   input  wire m_areset_resp2,\n   input  wire M_READY,\n   input  wire handshake_pipe,\n   output wire ready_pipe,\n   output wire M_VALID,\n   input  wire [C_DATA_WIDTH-1:0] payload_pipe,\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n   );\n    \n    (* keep=\"true\" *) reg [2:0] m_aresetn_resp4 = 3'b000;\n    wire m_aresetn_resp3;\n    wire m_aresetn_d;\n    wire m_aresetn_q;\n    wire m_valid_i;\n    wire pop;\n    wire m_ready_d;\n    wire m_handshake_q;\n    reg  [C_DATA_WIDTH-1:0] m_payload_q;\n    \n    assign M_VALID = m_valid_i;\n    assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;\n    assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;\n    assign pop     = M_READY & m_valid_i;\n    \n    always @(posedge ACLK or posedge m_aclear) begin\n      if (m_aclear) begin\n        m_aresetn_resp4 <= 3'b000;\n      end else begin\n        m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      m_payload_q <= payload_pipe;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) m_aresetn_resp3_inst (\n        .Q   (m_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~m_areset_resp2)\n     );\n    \n    // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (m_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_aresetn_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (m_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (handshake_pipe)\n     );\n    \n    (* autopipeline_group=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (ready_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_ready_d)\n     );\n    \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  (5)  \n      )\n      srl_fifo\n      (\n       .aclk    (ACLK),    \n       .areset  (~m_aresetn_q),\n       .aclear  (m_aclear),  \n       .s_mesg  (m_payload_q),  \n       .s_valid (m_handshake_q), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      );\n    \nendmodule  // auto_dest\n\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      reg s_valid_d;\n      reg s_ready_d = 1'b0;\n      reg s_ready_reg = 1'b0;\n      reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_22_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_RESP_MIDDLE2_LATENCY = C_PIPELINES_SLAVE + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_22_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      .ACLK           (ACLK),\n      .ARESETN         (ARESETN),\n      .S_PAYLOAD_DATA (S_PAYLOAD_DATA),\n      .S_VALID        (S_VALID),\n      .S_READY        (S_READY),\n      .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n      .M_VALID        (M_VALID),\n      .M_READY        (M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_reset;\n    wire src_ready;\n    wire dummy_reset;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  ( C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( dummy_reset   ) ,\n        .laguna_s_reset_in  ( src_reset   ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset   ) ,\n        .laguna_m_reset_in  ( src_reset  ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset2   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n      \n  end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] mid_payload;\n    wire mid_handshake;\n    wire mid_ready;\n    wire mid_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n    wire dummy_reset3;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( mid_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( mid_reset    ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset3   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset3   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out (  dummy_reset2  ) ,\n        .laguna_m_reset_in  ( mid_reset   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE2_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( mid_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2   ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset3   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset3    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n   \n  generate\n\n  (* keep=\"true\" *) reg s_reset_dd = 1'b0;\n  (* keep=\"true\" *) reg m_reset_dd = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n  \n  assign laguna_s_reset_out = laguna_s_reset_out_i;\n  assign laguna_m_reset_out = laguna_m_reset_out_i;\n  \n  always @(posedge ACLK) begin\n    laguna_s_reset_in_d <= laguna_s_reset_in;\n    laguna_m_reset_in_d <= laguna_m_reset_in;\n    s_reset_dd <= laguna_s_reset_in_d;\n    m_reset_dd <= laguna_m_reset_in_d;\n    laguna_s_reset_out_i <= C_PIPELINES==0 ? laguna_m_reset_in_d : m_reset_dd;\n    laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;\n  end\n  \n  wire ACLEAR;\n  assign ACLEAR = ~ARESETN;\n  \n  if (1) begin : common\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire laguna_s_handshake_q;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, laguna_m_ready_d}; \n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else if (p==C_PIPELINES+1) begin\n          laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n\n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = handshake_i[C_PIPELINES];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_m_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* keep=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_22_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_m_reset_out = laguna_m_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_m_reset_in_d <= laguna_m_reset_in;\n      aresetn_d <= C_CHANNEL==P_FORWARD ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? areset_dly[15]  : laguna_m_reset_in_d;\n      laguna_m_reset_out_i <= areset_d;  // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n  \n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* keep=\"true\" *)  reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      ready_d <= {ready_d, laguna_m_ready_d}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid_q;\n      assign payload_valid_d = (p==0) ? (S_VALID & s_ready_i) : handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==C_PIPELINES) begin\n          laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else if (p==0) begin\n          payload_data <= S_PAYLOAD_DATA;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n      \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_s_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* keep=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_s_reset_out = laguna_s_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_s_reset_in_d <= laguna_s_reset_in;\n      aresetn_d <= C_CHANNEL==P_RESPONSE ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? laguna_s_reset_in_d : areset_dly[15];\n      laguna_s_reset_out_i <= areset_d;  // For forward channels, reflect laguna_s_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n\n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    wire laguna_s_handshake_q;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      laguna_s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n        \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n        \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)  \n      )\n      srl_fifo_0\n      (\n       .aclk    (ACLK),    \n       .areset  (areset_d),  \n       .aclear  (ACLEAR),\n       .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n       .s_valid (push), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      ); \n  \n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  reg areset_d = 1'b0;\n  reg [3:0] areset_dly = 4'b0;\n  always @(posedge ACLK) begin\n    areset_dly <= {4{~ARESETN}} | (areset_dly<<1);\n    areset_d <= areset_dly[3];\n  end\n  \n  if (1) begin : common\n    reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID & s_ready_i;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* keep=\"true\" *)  reg payload_valid = 1'b0;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          payload_data <= S_PAYLOAD_DATA;\n          payload_valid <= S_VALID & s_ready_i & ~areset_d;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n          payload_valid <= handshake_i[((p>0)?(p-1):0)];\n        end\n      end\n    end\n    \n    if (C_PIPELINES==0) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),\n         .aclear  (1'b0),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire                        aclear,  // Async clear\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    wire [1:0] state;  // State vector register\n    reg  [1:0] next;           // Next state value\n    wire [1:0] next_qual;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    reg  m_valid_d;\n    wire m_valid_q;\n    \n    assign m_valid = m_valid_q;\n    assign next_qual = areset ? K_EMPTY : next;\n    assign m_mesg  = mesg_reg;\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_mvalid_inst (\n        .Q   (m_valid_q),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (m_valid_d)\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state0_inst (\n        .Q   (state[0]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[0])\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state1_inst (\n        .Q   (state[1]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[1])\n     );\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      m_valid_d = m_valid_q & ~areset;\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid & ~areset) begin\n            next = K_HAS1;\n            m_valid_d = 1'b0;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              m_valid_d = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n              m_valid_d = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          m_valid_d = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      (* keep_hierarchy = \"yes\" *) axi_register_slice_v2_1_22_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule  // axic_reg_srl_fifo\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   //   16 -> Auto-pipelining\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_RESERVE_MODE = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n  \n  if (C_RESERVE_MODE==1) begin : gen_reserve_si\n  \n    axi_register_slice_v2_1_22_test_slave #(\n      .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n      .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n      .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n      .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n      .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n      .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n      .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n      .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n      .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .s_axi_awaddr(s_axi_awaddr),\n      .s_axi_awprot(s_axi_awprot),\n      .s_axi_awvalid(s_axi_awvalid),\n      .s_axi_awready(s_axi_awready),\n      .s_axi_awsize(s_axi_awsize),\n      .s_axi_awburst(s_axi_awburst),\n      .s_axi_awcache(s_axi_awcache),\n      .s_axi_awlen(s_axi_awlen),\n      .s_axi_awlock(s_axi_awlock),\n      .s_axi_awqos(s_axi_awqos),\n      .s_axi_awregion(s_axi_awregion),\n      .s_axi_awid(s_axi_awid),\n      .s_axi_awuser(s_axi_awuser),\n      .s_axi_wdata(s_axi_wdata),\n      .s_axi_wstrb(s_axi_wstrb),\n      .s_axi_wvalid(s_axi_wvalid),\n      .s_axi_wready(s_axi_wready),\n      .s_axi_wlast(s_axi_wlast),\n      .s_axi_wid(s_axi_wid),\n      .s_axi_wuser(s_axi_wuser),\n      .s_axi_bresp(s_axi_bresp),\n      .s_axi_bvalid(s_axi_bvalid),\n      .s_axi_bready(s_axi_bready),\n      .s_axi_buser(s_axi_buser),\n      .s_axi_bid(s_axi_bid),\n      .s_axi_araddr(s_axi_araddr),\n      .s_axi_arprot(s_axi_arprot),\n      .s_axi_arvalid(s_axi_arvalid),\n      .s_axi_arready(s_axi_arready),\n      .s_axi_arsize(s_axi_arsize),\n      .s_axi_arburst(s_axi_arburst),\n      .s_axi_arcache(s_axi_arcache),\n      .s_axi_arlock(s_axi_arlock),\n      .s_axi_arlen(s_axi_arlen),\n      .s_axi_arqos(s_axi_arqos),\n      .s_axi_arregion(s_axi_arregion),\n      .s_axi_aruser(s_axi_aruser),\n      .s_axi_arid(s_axi_arid),\n      .s_axi_rdata(s_axi_rdata),\n      .s_axi_rresp(s_axi_rresp),\n      .s_axi_rvalid(s_axi_rvalid),\n      .s_axi_rready(s_axi_rready),\n      .s_axi_rlast(s_axi_rlast),\n      .s_axi_ruser(s_axi_ruser),\n      .s_axi_rid(s_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign m_axi_awid     = 0;\n     assign m_axi_awaddr   = 0;\n     assign m_axi_awlen    = 0;\n     assign m_axi_awsize   = 0;\n     assign m_axi_awburst  = 0;\n     assign m_axi_awlock   = 0;\n     assign m_axi_awcache  = 0;\n     assign m_axi_awprot   = 0;\n     assign m_axi_awregion = 0;\n     assign m_axi_awqos    = 0;\n     assign m_axi_awuser   = 0;\n     assign m_axi_awvalid  = 0;\n     assign m_axi_wid      = 0;\n     assign m_axi_wdata    = 0;\n     assign m_axi_wstrb    = 0;\n     assign m_axi_wlast    = 0;\n     assign m_axi_wuser    = 0;\n     assign m_axi_wvalid   = 0;\n     assign m_axi_bready   = 0;\n     assign m_axi_arid     = 0;\n     assign m_axi_araddr   = 0;\n     assign m_axi_arlen    = 0;\n     assign m_axi_arsize   = 0;\n     assign m_axi_arburst  = 0;\n     assign m_axi_arlock   = 0;\n     assign m_axi_arcache  = 0;\n     assign m_axi_arprot   = 0;\n     assign m_axi_arregion = 0;\n     assign m_axi_arqos    = 0;\n     assign m_axi_aruser   = 0;\n     assign m_axi_arvalid  = 0;\n     assign m_axi_rready   = 0;\n      \n  end else if (C_RESERVE_MODE==2) begin : gen_reserve_mi\n    \n    axi_register_slice_v2_1_22_test_master #(\n    .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n    .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .m_axi_awaddr(m_axi_awaddr),\n      .m_axi_awprot(m_axi_awprot),\n      .m_axi_awvalid(m_axi_awvalid),\n      .m_axi_awready(m_axi_awready),\n      .m_axi_awsize(m_axi_awsize),\n      .m_axi_awburst(m_axi_awburst),\n      .m_axi_awcache(m_axi_awcache),\n      .m_axi_awlen(m_axi_awlen),\n      .m_axi_awlock(m_axi_awlock),\n      .m_axi_awqos(m_axi_awqos),\n      .m_axi_awid(m_axi_awid),\n      .m_axi_awuser(m_axi_awuser),\n      .m_axi_wid(m_axi_wid),\n      .m_axi_wdata(m_axi_wdata),\n      .m_axi_wstrb(m_axi_wstrb),\n      .m_axi_wvalid(m_axi_wvalid),\n      .m_axi_wready(m_axi_wready),\n      .m_axi_wlast(m_axi_wlast),\n      .m_axi_wuser(m_axi_wuser),\n      .m_axi_bresp(m_axi_bresp),\n      .m_axi_bvalid(m_axi_bvalid),\n      .m_axi_bready(m_axi_bready),\n      .m_axi_buser(m_axi_buser),\n      .m_axi_bid(m_axi_bid),\n      .m_axi_araddr(m_axi_araddr),\n      .m_axi_arprot(m_axi_arprot),\n      .m_axi_arvalid(m_axi_arvalid),\n      .m_axi_arready(m_axi_arready),\n      .m_axi_arsize(m_axi_arsize),\n      .m_axi_arburst(m_axi_arburst),\n      .m_axi_arcache(m_axi_arcache),\n      .m_axi_arlen(m_axi_arlen),\n      .m_axi_arlock(m_axi_arlock),\n      .m_axi_arqos(m_axi_arqos),\n      .m_axi_arid(m_axi_arid),\n      .m_axi_aruser(m_axi_aruser),\n      .m_axi_rdata(m_axi_rdata),\n      .m_axi_rresp(m_axi_rresp),\n      .m_axi_rvalid(m_axi_rvalid),\n      .m_axi_rready(m_axi_rready),\n      .m_axi_rlast(m_axi_rlast),\n      .m_axi_ruser(m_axi_ruser),\n      .m_axi_rid(m_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign s_axi_awready = 0;\n     assign s_axi_wready  = 0;\n     assign s_axi_bid     = 0;\n     assign s_axi_bresp   = 0;\n     assign s_axi_buser   = 0;\n     assign s_axi_bvalid  = 0;\n     assign s_axi_arready = 0;\n     assign s_axi_rid     = 0;\n     assign s_axi_rdata   = 0;\n     assign s_axi_rresp   = 0;\n     assign s_axi_rlast   = 0;\n     assign s_axi_ruser   = 0;\n     assign s_axi_rvalid  = 0;\n\n  end else begin : gen_reg_slice  // Any normal reg-slice mode\n\n    axi_infrastructure_v1_1_0_axi2vector #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    axi2vector_0 ( \n      .s_axi_awid      ( s_axi_awid      ) ,\n      .s_axi_awaddr    ( s_axi_awaddr    ) ,\n      .s_axi_awlen     ( s_axi_awlen     ) ,\n      .s_axi_awsize    ( s_axi_awsize    ) ,\n      .s_axi_awburst   ( s_axi_awburst   ) ,\n      .s_axi_awlock    ( s_axi_awlock    ) ,\n      .s_axi_awcache   ( s_axi_awcache   ) ,\n      .s_axi_awprot    ( s_axi_awprot    ) ,\n      .s_axi_awqos     ( s_axi_awqos     ) ,\n      .s_axi_awuser    ( s_axi_awuser    ) ,\n      .s_axi_awregion  ( s_axi_awregion  ) ,\n      .s_axi_wid       ( s_axi_wid       ) ,\n      .s_axi_wdata     ( s_axi_wdata     ) ,\n      .s_axi_wstrb     ( s_axi_wstrb     ) ,\n      .s_axi_wlast     ( s_axi_wlast     ) ,\n      .s_axi_wuser     ( s_axi_wuser     ) ,\n      .s_axi_bid       ( s_axi_bid       ) ,\n      .s_axi_bresp     ( s_axi_bresp     ) ,\n      .s_axi_buser     ( s_axi_buser     ) ,\n      .s_axi_arid      ( s_axi_arid      ) ,\n      .s_axi_araddr    ( s_axi_araddr    ) ,\n      .s_axi_arlen     ( s_axi_arlen     ) ,\n      .s_axi_arsize    ( s_axi_arsize    ) ,\n      .s_axi_arburst   ( s_axi_arburst   ) ,\n      .s_axi_arlock    ( s_axi_arlock    ) ,\n      .s_axi_arcache   ( s_axi_arcache   ) ,\n      .s_axi_arprot    ( s_axi_arprot    ) ,\n      .s_axi_arqos     ( s_axi_arqos     ) ,\n      .s_axi_aruser    ( s_axi_aruser    ) ,\n      .s_axi_arregion  ( s_axi_arregion  ) ,\n      .s_axi_rid       ( s_axi_rid       ) ,\n      .s_axi_rdata     ( s_axi_rdata     ) ,\n      .s_axi_rresp     ( s_axi_rresp     ) ,\n      .s_axi_rlast     ( s_axi_rlast     ) ,\n      .s_axi_ruser     ( s_axi_ruser     ) ,\n      .s_awpayload ( s_awpayload ) ,\n      .s_wpayload  ( s_wpayload  ) ,\n      .s_bpayload  ( s_bpayload  ) ,\n      .s_arpayload ( s_arpayload ) ,\n      .s_rpayload  ( s_rpayload  ) \n    );\n    \n    axi_infrastructure_v1_1_0_vector2axi #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    vector2axi_0 ( \n      .m_awpayload    ( m_awpayload    ) ,\n      .m_wpayload     ( m_wpayload     ) ,\n      .m_bpayload     ( m_bpayload     ) ,\n      .m_arpayload    ( m_arpayload    ) ,\n      .m_rpayload     ( m_rpayload     ) ,\n      .m_axi_awid     ( m_axi_awid     ) ,\n      .m_axi_awaddr   ( m_axi_awaddr   ) ,\n      .m_axi_awlen    ( m_axi_awlen    ) ,\n      .m_axi_awsize   ( m_axi_awsize   ) ,\n      .m_axi_awburst  ( m_axi_awburst  ) ,\n      .m_axi_awlock   ( m_axi_awlock   ) ,\n      .m_axi_awcache  ( m_axi_awcache  ) ,\n      .m_axi_awprot   ( m_axi_awprot   ) ,\n      .m_axi_awqos    ( m_axi_awqos    ) ,\n      .m_axi_awuser   ( m_axi_awuser   ) ,\n      .m_axi_awregion ( m_axi_awregion ) ,\n      .m_axi_wid      ( m_axi_wid      ) ,\n      .m_axi_wdata    ( m_axi_wdata    ) ,\n      .m_axi_wstrb    ( m_axi_wstrb    ) ,\n      .m_axi_wlast    ( m_axi_wlast    ) ,\n      .m_axi_wuser    ( m_axi_wuser    ) ,\n      .m_axi_bid      ( m_axi_bid      ) ,\n      .m_axi_bresp    ( m_axi_bresp    ) ,\n      .m_axi_buser    ( m_axi_buser    ) ,\n      .m_axi_arid     ( m_axi_arid     ) ,\n      .m_axi_araddr   ( m_axi_araddr   ) ,\n      .m_axi_arlen    ( m_axi_arlen    ) ,\n      .m_axi_arsize   ( m_axi_arsize   ) ,\n      .m_axi_arburst  ( m_axi_arburst  ) ,\n      .m_axi_arlock   ( m_axi_arlock   ) ,\n      .m_axi_arcache  ( m_axi_arcache  ) ,\n      .m_axi_arprot   ( m_axi_arprot   ) ,\n      .m_axi_arqos    ( m_axi_arqos    ) ,\n      .m_axi_aruser   ( m_axi_aruser   ) ,\n      .m_axi_arregion ( m_axi_arregion ) ,\n      .m_axi_rid      ( m_axi_rid      ) ,\n      .m_axi_rdata    ( m_axi_rdata    ) ,\n      .m_axi_rresp    ( m_axi_rresp    ) ,\n      .m_axi_rlast    ( m_axi_rlast    ) ,\n      .m_axi_ruser    ( m_axi_ruser    ) \n    );\n    \n  end  // Reserve SI/MI branch\n\n  if ((C_REG_CONFIG_AW <= 9) && (C_RESERVE_MODE==0)) begin : aw\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 15) && (C_RESERVE_MODE==0)) begin : aw15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 16) && (C_RESERVE_MODE==0)) begin : aw16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) \n    )\n    aw_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if ((C_REG_CONFIG_W <= 9) && (C_RESERVE_MODE==0)) begin : w\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 15) && (C_RESERVE_MODE==0)) begin : w15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 16) && (C_RESERVE_MODE==0)) begin : w16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) \n    )\n    w_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if ((C_REG_CONFIG_B <= 9) && (C_RESERVE_MODE==0)) begin : b\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if ((C_REG_CONFIG_B == 15) && (C_RESERVE_MODE==0)) begin : b15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if ((C_REG_CONFIG_B == 16) && (C_RESERVE_MODE==0)) begin : b16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) \n    )\n    b_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if ((C_REG_CONFIG_AR <= 9) && (C_RESERVE_MODE==0)) begin : ar\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 15) && (C_RESERVE_MODE==0)) begin : ar15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 16) && (C_RESERVE_MODE==0)) begin : ar16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) \n    )\n    ar_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if ((C_REG_CONFIG_R <= 9) && (C_RESERVE_MODE==0)) begin : r\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 15) && (C_RESERVE_MODE==0)) begin : r15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 16) && (C_RESERVE_MODE==0)) begin : r16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) \n    )\n    r_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 4844}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_register_slice_light (\n  aclk,\n  aresetn,\n  s_axi_awaddr,\n  s_axi_awprot,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_araddr,\n  s_axi_arprot,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awaddr,\n  m_axi_awprot,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_araddr,\n  m_axi_arprot,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [31 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [31 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [3 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [31 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [31 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [31 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [31 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [3 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [31 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [31 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(2),\n    .C_AXI_ID_WIDTH(1),\n    .C_AXI_ADDR_WIDTH(32),\n    .C_AXI_DATA_WIDTH(32),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(7),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(7),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(1'B0),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'H00000002),\n    .s_axi_awburst(2'B1),\n    .s_axi_awlock(1'B0),\n    .s_axi_awcache(4'B0),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(4'B0),\n    .s_axi_awqos(4'B0),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(1'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(1'B0),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(1'B0),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'H00000002),\n    .s_axi_arburst(2'B1),\n    .s_axi_arlock(1'B0),\n    .s_axi_arcache(4'B0),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(4'B0),\n    .s_axi_arqos(4'B0),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(),\n    .m_axi_awsize(),\n    .m_axi_awburst(),\n    .m_axi_awlock(),\n    .m_axi_awcache(),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(),\n    .m_axi_awqos(),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(1'B0),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(),\n    .m_axi_arsize(),\n    .m_axi_arburst(),\n    .m_axi_arlock(),\n    .m_axi_arcache(),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(),\n    .m_axi_arqos(),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(1'B0),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(1'B0),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 316}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"axi_register_slice_light,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"axi_register_slice_light,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=2,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_REG_CONFIG_\\\nW=7,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=7,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule axi_register_slice_light (\n  aclk,\n  aresetn,\n  s_axi_awaddr,\n  s_axi_awprot,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_araddr,\n  s_axi_arprot,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awaddr,\n  m_axi_awprot,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_araddr,\n  m_axi_arprot,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [31 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [31 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [3 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [31 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [31 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [31 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [31 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [3 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [31 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [31 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(2),\n    .C_AXI_ID_WIDTH(1),\n    .C_AXI_ADDR_WIDTH(32),\n    .C_AXI_DATA_WIDTH(32),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(7),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(7),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(1'B0),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'H00000002),\n    .s_axi_awburst(2'B1),\n    .s_axi_awlock(1'B0),\n    .s_axi_awcache(4'B0),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(4'B0),\n    .s_axi_awqos(4'B0),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(1'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(1'B0),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(1'B0),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'H00000002),\n    .s_axi_arburst(2'B1),\n    .s_axi_arlock(1'B0),\n    .s_axi_arcache(4'B0),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(4'B0),\n    .s_axi_arqos(4'B0),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(),\n    .m_axi_awsize(),\n    .m_axi_awburst(),\n    .m_axi_awlock(),\n    .m_axi_awcache(),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(),\n    .m_axi_awqos(),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(1'B0),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(),\n    .m_axi_arsize(),\n    .m_axi_arburst(),\n    .m_axi_arlock(),\n    .m_axi_arcache(),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(),\n    .m_axi_arqos(),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(1'B0),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(1'B0),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 318}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_\\\nBITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_\\\nBITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_axi_interconnect_m00_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect_m00_regslice_0,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=6,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_\\\nREG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_\\\nBITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_\\\nBITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_a493_wrapper.bd\n//Design : bd_a493_wrapper\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule bd_a493_wrapper\n   (S_BSCAN_bscanid_en,\n    S_BSCAN_capture,\n    S_BSCAN_drck,\n    S_BSCAN_reset,\n    S_BSCAN_runtest,\n    S_BSCAN_sel,\n    S_BSCAN_shift,\n    S_BSCAN_tck,\n    S_BSCAN_tdi,\n    S_BSCAN_tdo,\n    S_BSCAN_tms,\n    S_BSCAN_update,\n    clk);\n  input S_BSCAN_bscanid_en;\n  input S_BSCAN_capture;\n  input S_BSCAN_drck;\n  input S_BSCAN_reset;\n  input S_BSCAN_runtest;\n  input S_BSCAN_sel;\n  input S_BSCAN_shift;\n  input S_BSCAN_tck;\n  input S_BSCAN_tdi;\n  output S_BSCAN_tdo;\n  input S_BSCAN_tms;\n  input S_BSCAN_update;\n  input clk;\n\n  wire S_BSCAN_bscanid_en;\n  wire S_BSCAN_capture;\n  wire S_BSCAN_drck;\n  wire S_BSCAN_reset;\n  wire S_BSCAN_runtest;\n  wire S_BSCAN_sel;\n  wire S_BSCAN_shift;\n  wire S_BSCAN_tck;\n  wire S_BSCAN_tdi;\n  wire S_BSCAN_tdo;\n  wire S_BSCAN_tms;\n  wire S_BSCAN_update;\n  wire clk;\n\n  bd_a493 bd_a493_i\n       (.S_BSCAN_bscanid_en(S_BSCAN_bscanid_en),\n        .S_BSCAN_capture(S_BSCAN_capture),\n        .S_BSCAN_drck(S_BSCAN_drck),\n        .S_BSCAN_reset(S_BSCAN_reset),\n        .S_BSCAN_runtest(S_BSCAN_runtest),\n        .S_BSCAN_sel(S_BSCAN_sel),\n        .S_BSCAN_shift(S_BSCAN_shift),\n        .S_BSCAN_tck(S_BSCAN_tck),\n        .S_BSCAN_tdi(S_BSCAN_tdi),\n        .S_BSCAN_tdo(S_BSCAN_tdo),\n        .S_BSCAN_tms(S_BSCAN_tms),\n        .S_BSCAN_update(S_BSCAN_update),\n        .clk(clk));\nendmodule\n", "num_lines": 66}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nXvoWuyjysN5V55U4xsjyWg2bXI++8I1KAZgJ0eiQkY3L8ns1PfNti9fujmr8wvFQA6ycwh4K6mSp\nINQjc8TyLQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nbD05I2IKef08FLVG4C2ftkJOY+/UsvagxY6ta+A0N1USwLQivKTmRt7LJlQ+5UJqrfPvhHMyYrLN\nrjoJbClg85XfNTYCnalRVvg3mmCcjtJkCLf6S5E9Q6UF92b6bwgtMTsr0BndJhdItlJtr0dYZtoP\nAEskMBthh6RdNMkZ3CA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nvLo4Yp/zX6HvZ92VMA2Xr4EIhMWPNGq2EvSBkjiZd5sCSFAX+37MKx4gdbrsGvhUMl1njqvSaoP7\nKrAa29/cm3QWjPgpaCsR/MhnaG5+7aUvxA5iCqVHXdriMlgx9kzxkB9SD+mOC8XR5LtYA0bPhbZ9\njQzWpWxdaOGYFF25DU0O9M7LMc7SLfKunYH/cQ91D37m0LjgZh1/uZv8chFzvCBbkHqUU0qi17/k\nZTWIIzqb1oycbuhZZrWLl95xQ/aaTxZ30sONWd/axZtO3Cd57huCbCxLuOH51qq6erD9AVszmxL8\noEoM+KW88P1S3LJ/EcIQN4LU0/nyN/f7xEmy2w==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nj99ihkoCqIO9DhRZEJdEqlRF2P+IwS2wuYmoh3hWFCDXbmGTwTqc+3EMjxY8Z4uDixuazjlTMiEH\nCk4MdTkVZ55pPhFb4druHTap3Twn20B3SWvOy2nf84OpTkdBnbK4qagABgZXs9/mAtQxbF++/F6Y\n+OOE3yUNTWvHiVGvpTJavfADkB2CL5wEIlBSnYRwtLp71JokDsMvjq2l3o3hxAjvtdg9ej7NKx4I\nkAZfrpZH7Ebv2hfXrTVI2kDTAl5Etr+4oSqxIhABJut2WaeWJrsSbL+dz9s2ZmYDMb1BCQdRexck\nbMMvUaS+P7sSGuR9BTVynHOY5GdQelHO1aazQw==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nHuzbd0U90PuPKn40554Cnki98HuQSq7dg6ZyXufEWFHsji6rteNupAY3HQsuLpXjFVxsNlS4bcHj\nAAOnDcL0hCCVbSkU011mqhhlkFmWqeBBECGfP+T7/+l9KBu+9ynszhlhaVhmZMffsEuohDl5x084\nFnzFCdxrFyvqrOyWDac=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\neoQKmSsNWNEOJcUApe0UhUNGRDkxOLedPbjyDILgUJWMG+WVCpL9MC2MXZeZ6/oVwAYRlZTZsF1h\nUsVo6BO7IAuHuJAHeIQgEs2oIMj/I2qZxm9wUsOzWoK5/Jz4SS4sTE3TgOJXaX1GNAJlbUrCBtnM\nqIiavU164vZjX5BFoPGuHp4kICN8A4Wr9y2w2Lh0/IdiHjr/Ruk5PpVNyl7tW9EaSFY1AL4aoQpd\nRFDdUFRk4tMBtmFxi/B+pLVFE0hAUZnlVCsSaf4B0lN/m4CME7lgy7oXElp7ov4fMnD9VI8HLGMX\nWBSQjD8F6BB0Wblgm9lJNc0h0VqxxD4DbRleKA==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nyrn0K+G4SU1wuMdE7DJlKWErX/N5nCqD3+dP+4ONmo8yuM983VHfjLhCoeQMbM26e49U4PPdXcDR\ny0rRemqJACoi5H5NvzXohhKZI9q+WKME4TkhFzfKvIwyta1m/uNSe/A0+52Dzbg5uAxYihw0IdZR\nZMywfa3deZ8IUMz3kWSlMs1P4wESz2pKpdYGs0FpvovucuNn4OhZKH7RGX8z8Zy4E9juZRgnSQnX\nmvRtisgVB9uL2J0vl9XjW/1990VYZi0nrZJ8gQL38HLTz62vDuMuYjiFbbnDCujJNKOCHh/xJTdt\n73nsz+dY3We4tQdnxuESibzLQLGF1l8+d9FPDA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nJPIGH1v6BG8bvo+3pHrWlum+XEDtFDlKP+4Toq88+g/eeinS/p8A0zMVVYj4wfjGDhx3kGvJ9XAx\ngxYpezvlgnz+IEGWQzepCMSp4iHz9TEdGkc5LTQj50VJj4+HGz2Qhrw96Hw0c+5RDrv238ILy3p7\nuzIPIzxKEl8D7gK6b8ZPrzx95KMPuGZyju4JUHBWdjDx0hhhIl+L3Ju/bVyWaWd7w1xI0mreJtAN\noOdcObOESJpTuj0KqFtfA3UY7v9n9Lj/I/vMaPX7LnSIZuS+tHyiD8D+t+Kf6XiIl3sYDL9erP7t\nSpHvPfG9bOfGRxM7dmsvKj+XqHeXg23wyS1Nfg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nrxmK0sxFw5opGoAsi+RHBRwE0wYNls8LL+oURMgLNuoRDOPNH7up4F86jASnrdlvXLShGHMZnaJ6\ny1orZ0uAZ6xxM2PeKAxvxBI02HOu0aXd/SMNxr16dADlCYK6R1DVdq3DC+T8bQTLWyyHr9r4m4En\nW5DcJ2hEs5b31PUg/DoCNTpHm2swT7sLG9qRkSfTddaSyGTADcvRXYjnHKHin6TQlOCZufWMm54P\nPJeCQmj1MjyycQGpsvFNX7VMxW49ashO7EGmRdy7lMGRoHDqLWBxcIlwAS4L28iuln/NdC/QV538\nQei7EbcqeUmfs07XP8FKxdA3hi3Aq2Upg9DkOw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64736)\n`pragma protect data_block\npJdOORWQloxSGvgvy0l4tBp1HqnYdonsYgNOe99SLH3qi9BP+2tNlaoelqmLJLSHNsBn3TJxXlZa\nnIZxc0/l2jA1h9Jz15QEEgUR0MqZaESeIPQdEbADnul6xUXY0J6g//n8Vnzph99nb1v9j4yp0I8W\nmF2Bvdz/qHJcUcV5zedPk5PkPVS8cmwYFQWer3rOMl6Or1E/YoHi9T9wfbgxxTs6yzqYqVGUBlz5\nAlhSoRF+xXB1Z4h2Ny4v4u05pGtbpnnDj+JhauZ7AfT+uRL3JZ7hNdSiI3coyNU077RtI/1VAmYO\npJoj/3tO2z4y9phvRShE/Otch4qxfx53IywqoRQmUF57yV4NjbkGPW8j7U6iQ8Ls1911ZAOgZIga\nmynl1jCs8ajbsNdraT0wfsPf1kWJOCuUGyItYv2eEwfh7iEYRrpT0V6YT5gENAgDuriQCZuFtnJE\ndhvImjwTXy3d76buWun43bM5pyUNSUzm90uucXHtbfsv8HZTM/chDluZJ4cMeW8D9Pwjtvo6lXLx\nYJM6v2cUpOTIMOcKDxrRTFomRQ1DwRsa4wQGal4q2dhrokLR6YNhu1ED6+AbEAN+FWui25yRPN2c\nRifAbYj3+oa+z6kUON22gegvkiRIe3iVn5MeyImok+P+5dmykiOW6L7J+GDFd4UZtYwJkwUH4ijt\ny9tlvkg7bhgKKY/VRht7EZFg6U4GjUBwLTEWIsD/6R8LgyENKTNO1FVyOJge9+hJYOxJpk93nMac\n0dR2cl0TLESIEfZQ8wSlqKcnzibNa/Mwa+gyj8uNmBtlGMv9GLnh914fnVrJPaJYjkLNLesy5uKF\nWOOHFhlsuqMHkybog57X/W2y+bzzdtaWoQ8/DU/QWGyTt3Vhlmu4YBKvv/DBB51RUj7naprx+CNR\nK7/l3uoheqcD/zy4ipVqZ/mSOTxjqNwJ88tpKUTD7UHuLf8rEeiu80iR1raYJGMHzUS7FcK/APPf\nbBCJIKpjoq1C63MJYurbOeqWcRL3DDPi/z3C66E9WG/nFKs7vMkhbVhClFUAjy+DwMCS7VjbvUvn\nCbr4m+kTXY7ipbBxU7YIDWHssBAAjeM1Rdxx9VvDqABN+rFZAA7C08PNPUeOiVYCFO3gmbAqYK8f\nEPeBaPUk6eskVX2sXw5/qrh1a5mqGk/sYCFZItuYZ6SMz1BFuaZz+ac8Feq8+d7gH2f1DuK4EG20\nOgLh0liUdRk5TCUZsSZTlhRd1FA4SqglWHYk+GIL1WEcVBskAEiY2YIK1TGXzUQaG00TT5TRBNmv\nsPnVI8z6bWwqXomyqcYSelXrfl2izqtjadlA+3+0O2A1XhL9tmMhT3v0nQIlobxn4nFE376czv08\n2+xLHI/chXlg2WvKMK3NCBbWGw7tnHSdJc47JRdiCkb0tIr9wocUbWPbM7W5G3Ku+bQZQXPM0lNy\nstFAjwukEDL4vbC72EJbEwf+6kzkzLjBrc0JDEzvjqnYQYiwloQ0qi9k/yE3bXcnEHvgw8ig5Y/S\nt9SttzL9mNMXwbouRg1seAZ89RrLrTNZiBk2TlhzdIfvWsbvdBYdIhaMqKRGJFpWxZgPm+JbW+09\nfF1z2nf/18EW+WziUuICezISE4+2HDfqFOEltKV6AdesQWDrloYiby+MezSSORPfWkx+nVGv8JEs\nI01podsuoWFRpVmbt/Dua5qZk9EOHGFBRgvYNnlH47YVREn5j8l2T/0bBlGUrv4r0tmSTvb5Rk62\nTtYvXt/3/jJe7TX05O4Uz8CDBe02LhhwyNkyyNYPm6hcqislaGMW5IrlUBR19xoKivY5xsi9WHEp\nOscK7GlXBFf+1ZdqPUIFBzo8CoanS+vY6N5dX/zhH9ka7wSGlru7qjqAyYG3VOzYi+lIUT1D0l0A\nhIuLJhQlgGIPioPMX5r9G+nJX9J1xhmQmslUobJCrtsIfoshA1m3sO8FVq/uKShEPK85uU48DmE1\nBM73G3APR/Pn3q4udJagFjB+ngJWARXqQX1U/fZdrs1d4U8E/KLlkVQywLtM4ImADW15ZRE2zwbt\n93vD21KzRF0gTEp32+Y94DZJmilvEITUz6i6Uf3GIhk/8VlW2sgoZBxyIXdlfZU0hAeWoF6z0y8i\nsz3YJBSL59bOXPeovsUY+1K4JWkThiLh9WlHMd3YfANHBPnf+imIQZm0bk8SniIn386MI5OOzHz4\nE4NRinoFBZ2QveSs8W7mDkgRcm6PoFPVY3QRUGVKM/cdavafi55CMHzsrvtIU+GTn9VIn3xNt55T\nvun82PwGiZ2FiwhlNlG8Wy4O+LFNA76IijNkkamPOoINY3NpvBlYJ4sMSw1dZ/S+Qd509gN+YqK/\njuugLi10dq5ezC717GDkCW4fL6XMF1BLctfTjFHbDnQePKJIiB57aUuvbzah60QCKQnwYsO2mNs3\nlX8Tl9YL68F88dwoxH0JclrQ/K+4uYuofKZNpcUqyesWLZ7Ajkjo1V/LWCNdqLb7jaE2Z0v+PGsJ\nbQ2zY2rbw1xVbkOFkWnJb00IZlS5AfKLW2JwtTjSc9R5cytj7Kj8rVyPRdWixjwHVXwb9oIhCtsZ\nr9zdlcsnNvnrEk8HWDJmg9t+Ss3qdeobuZBvC1qVhW9OeCSeLWFmmlBTM7zlf4bIM7BPobwINrOH\na+x81+t4Xk/8bAWK5b1pfO/q6usi0t9Z1NTJb3ix47MRkhAbStRfFBfBwzDQr/YBXixPzFiRd7RK\nKHM5pI4NGo4x/1eUa3I9iGFb0JwOlvTvmyLF4CY35sdztuKueaGq0YUi4X3SbBVUihPbcPvhcn3q\nULcb1JlytkOdtyHtyrm7/EOiSLmMn3uCPXQDioYj1f6NsIRA8BV+t4V5VK8a2hNJ+Ci6U9tBmG7R\n2AfVDNWXakk0eYIUYcZuIPVd4sH7Be8PANt6YH+bxeZtBfUel13RoATsMc/l+Vz7BvaZ9ZhPoxu0\nMpG5BKJTAuGZ3OqNXDuuvsvuBv8s5hC8JKvLoL76k+rFk8PlyNwEnYoc7nFhCrqDHeOr/8E3maxP\nPv/AiEhEzjU5PQBF457AHnjeQ3eTwpDPSnYJ6nuR0WhnaxbVcRDXmfQc5Pm+RgJOQXySVRlfAtO/\nJmM8oWf9Wd57qYf2P95KvohDPW6vlFW5UOuYJRNedw/Vofmtj6gUXmSUtZzX9x+pGUbZK1L7qaRH\n4Bl+RKLFFF3ULv72pe+uhZoyumhCUE9nTUfh/0bbyfQ0/7E4OjNceJy3IuQXZAelpm4/lyIClM6a\nbcA7XaiUNtUxRgOk+Gm4bXDK/lbpfHAo3ZLrOeIIrJSFdGgfIjMAMcPO2agXDXysM9w0LXX4XzKa\nAk5Ctu+YxqwaE3xbxVfqa3Xiwxzu9RezCh2I21Ysg1ckJugmX+s7525qUeaUizKlxcu5ef5xX40W\nh5pW3QA7UPCugDISw+aX406IO2drov2E5eUNDLRRG/nY7aG606JFGCFgUNVLl22BloATVP6ZeMDr\nmifoHBORyaJvgAndCrygYyJGcy9labne+Cqn0A1qtn323sFNB43FEMX42WIgtgc4oPab1AYsEQum\ns46nWTCUaZAyRO+53Dzben+MOJEy1iKP7o1PMZDKjaQ4Atrpot1Ix9OivbbWL8nNOjFG3rRgc8Tf\nLOVtiwqq/r+IiSB/HQOV/ZHmkDTL9dtw3UFvBE6wRo6XaWDbKDi/T7PaYAC3GGNaQZw3CTXVFb6P\nSvTMYdICAhD7YCZDr6aVLiD1Mgc225aXecHZoluSWOck9HO5ezjlCFCPDSTSj5OnC9v9zUcFbNOa\nri/TT7JdgqdBMKQjvpVrljLeuPPWvSxLMEar6iv8iFwj9w4fIGsSX5D1h0fx53Dosj7c99OjPOKJ\n43ciuUlKmUrl8zGTv1bTsvgQBspvbQjDlKlZcFGKkJ5y+h+FKT7sLG0T7X0OsNyJhlkV8Oh1B7s0\nnzc4JG92kvRVvDmVljLF5q7kSbo4pOg+r9MMh209JANj1imzsRTwNlFhL4KQmOy32YKv975WzfpE\n5gOHTY5gj/9beHVy72SphX1PvZ/GvMrFHu0Q1SdMOxiDJO/8Vv+UogST5Z+pm6YS50RKp917SJLr\npQGNrqMBt2q0TjdKoF10330Oq2OQnGbPQBcF5wAOKor3lUhuKlgi4yfTsE7g0RlphaWiUi0kfQnJ\nxJaR/v3zWkal8YKuqBUOk2zAI58JgLOCGfkeP4lLDigas6lR86dIFm2ehEwWiuUxA0rMWk7MxUFq\nIvlNP2JTSuRX5d7mSS5TdZoich5Z28tzuAxtmfX/HVgsAiDJsXeq2lNJnPI4t7OJcjw+/LTBFn4u\nGkaeVQKsrDg0XjypHHAcx3Htai3F8S3SrSZThLhmNA0UuPAVwrWM/YxdRJdPCFxRV9DIfFLc78ED\nrxRf+2hm2iIX0v9lJubvukxj3RKg3bWedHf9X7fBwzCzmT3xpSVT/orUQHTM7BJi1uX619EAPHfH\nEslFnO9xBhBE/NfxEOIr6puKJWQy0vcdu3KHp/98gdYKgnVg5mCXI4uGSJL+j3Mo34LyWj6jofG1\nRpvUjZOY2WsTY2U7akBl0Uyiv66vuAVFTYtHxbLeKihdYSSxteod2tWquqRvLeBirXL2qi69vijg\n+WXGPNEs1ioW+W6cjl9Kt1V92qIp1LbqTEC9jDdj5VHq36eM3zGGY1FX+VH47w4FoxWcrGaGXkXO\nhGXHGyLwe6ssZ273qYR1N0RhvtgHnAdUHIPdsqqRbjeld0f7uZDVEUjGCA5HvEPmaA4qaz1HEmEX\nMSbcEbGOwM4/lsTSso35cqWlqf9VepPPahniUNw1bY7j79iM/o0F8kJkfL5NumCR5VM7RsWuHT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C99kqfj/UVOTB5eheZdHy7EcqBeNR/+6GsibmPncbobTk24qcaqVJt3wgZyWp0s45X+9wMv8\naq7nxbvk+JD5cuPi785YB4Is1gg85t6bvpA9Qfzb3O9Wk32ecemuYY7hfv+wXPcCciMC61K8t1VJ\nDxofEz9Nxh0L6M2gdZhrIeECMYqp9YunMryNLeqc7YQLvKIjonC1l4sbrYWZ+Vr/tRAksYUVxldM\nWs7rdbIReyHwkW9Q3eVk5tGNZYwsTJZ3LLHqX4k4QW4fN5SrXF7tpu0Nh6B20X5kbA57dL9bI0Mg\ngdCKLlB0s2kqOmSFFGQ2qiGM4gLCtJKTcJvH0QXyq3PoTYgnvqWXAi7962ulHUUvjiqAbTLGRYQR\ngd6pRfridQ9QkVVZ3q8/Wwg9RSEsbZuIJ9bsY3KxRk+Bv/QJmfbw9otM2ufRS79SLoJDUzayREpA\nzPDRjhDoGxRqrI6rV3uPDIkmG/IgiRjrOM3CMltuf+l5zCRv72lm/BooJKYufHaSMAUyCUXJp/Uc\nFu0s9YVH+QVUDZtdn/t+XoUZ1zviEEgoAEoY2VYry4fCJ8DYaSDlP46tShiJjQrOJdERGgL/xQBx\nO6uzJrNrt7Cf6kh0YFyp6QRAfTkuf7kwETESQMUFV2MR8wr0hZHmd/UBOQiPTPb8DscsuSAYh8Zc\nrknuK0zKex9YiHkZeDo7D/PSeuh+WG2d2zJdkM3Td3eMS6WVDFMFl2b5W8/jYjNABrnjK1XwThFh\nYLnSLJi/Op7SthgN17FwYwSwj+AcsR63hVzcnfiVu3ZUXHEZJEyz2HWtWt0RLaZ7MNZccAta93yH\ngOMoJdpfeYUKCCFDGcTyJlFegiSY/R9BWXq/NR5ouF0kpaoEUa+kWjoHoOiSEaQs4XEhSuNjRynD\nrVhVZzcmzBTJAU/E9/o/Hq/uvAStcm39QbP3OeAuNYGNe3sCFCFik9NxiyTW3OEmJSjBcrOnO+Qw\nx7FcS9UJ/wQfURM4P12Z7osL0N6s5Am8NipjMtQyeAtwOcmnJoNC+0+NUiyPWlCuXP/3Z4arSgFa\nZR7xsOv//tsF4wlUna5iH3TC56YNk8nUsFEw6Ge6ZSuhEVsfIeY4wG2IxxjFm7GLEm+Qi2fnWvFp\nirwOxF+K+U92WcMWV9jGmnuJKdDgr9f0rTsSnyJoE6abD5qCwAUSiMOFTLyqf0omOu5SrdwPvxDF\ndftrQ5R+oqkHgkZje/QojcIA5MmPjkCLRdKv8Qe8et8c4lmY6vRi/j86jriaKSwx4Y+Mw85SnPR2\n2j1hg4L1bm3Y95mODLr49QGkDVB7kvY4Qy33Bsp2CTuOWo05KgZSEEXL/7U+fWGzRHjASwfcbgCg\niVFHnASo+4H+F8SItbh9vW9aZB7dvzb/sp41V3sOiSQ/lvFv36hNky3d5TPRgeWxk7ahEnAeBvcU\nN36JNzslIJ0QcFbUJcrGjbreKWGwtRudHbvZZiy3VBuJefbL+K/nA5GKYex5vaF8VvW2JtNaz6nG\nO2mf0K1OaIC26ble9NY9pYrqytCcdTpOisFBK/sWMwJTDavyPDcaK3b2r0z6l8yWe/+kZORkwM1n\n+vS+mBxXx0tf6GtBwKVn9Wq5PBEpboQb7z+jnDgqEVQGEQk44+zDxF6mTiYHaVCLhGP1x2L8Qxtw\nPkf1ixuZGNM5w3J6JjwoYA1WqjGzNXQ/2I4IFQ7+zOL2BVVm8a+5aGNvBOtcu4B12kHIJpqjtEJq\n3tU1eussVADMAsGVV8uDeYtJPvulbF/idSwsgG8crk6BAOKJo99VQxAzmHr6hzse35prsun1dsY+\ntbANM8RyL4weuRCRdH+gaMfEFjRTXyRtKzs19VCSRxpLGUewvAFPajZ9ighUQ2DOA7Kr/rcMTxxd\nrh6hpvfsAFBAQjLiKMsH8ZMXPqNGDBjA8s7TGxd1KmM66Kj1RfzFBtlBuz9LglC/dRn/arEJkYKW\ngOxCUP9SwP1tqpMfyCFKkHci/RYZqmjbNlLH12cl5zMhmsQpiIcZXYfQL8enrVutyHkc8Oplycxn\njTecEx2W4yyRww+b9SpNrQwNcQAZHfUmu5afg1rtbUHZmBW//Afpurxew4MlsTVbE/q+GW4sYS08\n5hT4/ITaA2T979WNydM1h2SItDPecKYro2NCBuNGPCj2smuGGwIqTTedt7kY0lTXqc1QprlIXDOv\n7A/WEW6Ks/DyDbzo5ebBQ9k/Or/ERzVfh5qWgkq8yG0qonueIlbVexyJM/7sKO/BjOR3x/FKDD5A\nPOch29mk1tOqyzjUVo2fdU4B2P5yIWUu4LyA1+iW0TzGEcAlb+9A3LJHWtdxf5XRYSDst39xRNq/\njlN38Ihbn61REmPKmA+LoB8LUMaREXZsyBT2mkJjbCqOmNANgzEAOIj9ceuS25Y2KtrSdejGBdIE\nvCBEfvsJHNzt4EujHKaeJh7o4NDjqLcdEp7ed4Ep3cSOHMCOA874EICbE2zaW5mDE8TG62+kJMaF\nV28mlwI5fMFxipXSTKgVDY4Vj5EWSGuC9St7IfruwsQ039cqwvbAOIuBDwEDSJc6lCmXs/qZhmZt\nnFv7j6yW+vhyh9F/M49mYXMIrZDI2IQn1meVK5DQbu4ISFnSDGJl+UGx+F0w292X7x/NZlrDFxjU\n8F8hH3SoFUjtp3cdqR6J0qgyyvNuJIK0pC2nq9IzjvH1k+PjKgFH3e23kG7suulbVb/rfU+4p0A0\nUw/8qfFdt9ZBcVINnpEPSUJScU20uwWwAzXtPblYceO4Nbetd/Rru6gMmzl4QBV6dHDFv9Llj35m\nrcJlg8L6gZdUkbc5dWUef9LywyJ3ifFwzOukFPVGj0p1G9hRSiNUqdgpYFlexuLPL30vERjJltwu\nf4LrTIZ2VSuuoDz3yvK7YYnre2MTp1IvJIRPF0FnWr5WUuDhARBzNlManehpegpS4ik+5bBOARnk\n2ikf25Ea+euX4IRwUJwiPzAGTUbPzL3cODFaJ4mHcPv972AeFd1T3djc/nkOpMRfzLbUHz1h++GZ\nfguK3eWFxgEnwvmTBOSV/2pqlydJB+j2kzDoBOhHJ7yMYPINzLTm+GvY8+PE6TGpMumpLB79DVsR\nwtH293Qaqs60uwABd29zk+xMrOUEivDU8FIBU3QFpa33/+/A4nI1MVfVSHknip/yEcpuNY2qPJsT\nYuN68cBSWDFeSQJE5yXwjpRVFkSAHd8nML/bKhBZiplgzijzI6AXJOmkqclzuE3gbvl06XzNvh5g\niwbchkuC2q85hHpT3w63G6WwlR9OlnKpzSBsWJI5MiFvl09L3irrYtbw529xtermE/blvOxQYxuJ\nA3+cCbwrhbuASE/lxx/+CQSXsAGEFsG+rJZf02gTem+flBUQWxgYw7USLAXlR/yGYO6KKUiU5mYp\nMcLp5SF0ptsnO4GjOAmsRzhq+nFaThfDeXAXowTEeuWN+d56AInospMZc/eW0bFPTbgOjid6z1Vd\n+9+s7tiYNg6b6j0iAwEiBa8LX50Gz1E8B8Xk0bA4iCfVG+pXzxngp/ZgDAxA6x4B4xS8JSzvBqG9\n3fF/tpaS1x0ZYZNKrC0vl9eX2oeN5I3CbgEuLOUU1xIlzEYHqt8Ta5ZEnYRUtbhiunpXdVyqirCN\n2dgXkldd9U31gMhMY7qFkzBGBtdUApeaRyAGLxKnyg+nwnmirKX9Y3rBKSd6L+R5qhO6n0UbbSzD\n+4en4Cmiy/ti0HItxFAe4vWNWKSwEzlKaZ2HLEPHIUlwN4xiAAyIeXLQP3SyqcvdMzkhMFVdQYhH\nM2F1yAOo3G/JqR2EjrPkiLCy80ya2Cey9fh2IrTFABUwl8LswS7gb3noQTWyDJTWhVsMOvXawU6k\n9W4Jitv0d/+g4QNb1K05p1NtcnLpsIbcTsGei35vIairYz2Wpukkc+QIjcnbRoRYwr386Jd+y7da\n3/zxTz0ylTc2RMTh2TEZRm4kwoCvMb5bRjiCs5p4VDLdB5NKcfMPq/J+LOvbN9BdKd2e8etvM1x9\nZ83qLpzhi7vatfxsU6M1tYzeP0N1fDEQPFerPkzA/sJJfcYa5H+94+uMTRANw63xIlLDhmnCm9fB\nvFsT1znWi0KNE5YxMVAP5Nj3aNk30viM/aEGcXN1+348mdh8cJXP6Se0n9M2ShPtIh6uOzHcNN4F\nXvgZxyI06BOFPCh6pPn8pM/4wkj6M+5Q3d37NGdAT8T8ei4zfuLUhoasw2cJjrdrZ3LNelT1XVzr\ngtfkU+onSthCPR4WS6Xrw7Ok/kkEQoYmkdI7UB9unluvVVQ764ldp5OlFSL6uGJlq53fikq1mMPd\nHtYt08ogxQnb+cC85LdLrpUdkov30YC0DE++eB3VOpsBoGUdgSzOw4L/wn+VuAsCWq5ABwRe4fqT\no7SyMEpq1RX0wDx7yvM1IrLxDdnN/w9pE9XQ1ww/ANlsQf3806Yc1bxBlnH0iwF7F5dr6ExWX02C\nm4GMD+POG+syw7glXgXQ0OUc8vp22qMR4sD57/Oul0voKncx2id8UccXB9vsMZIBhX8NK9iQyJK7\nYG53Y6spKPwBaJ+D6oCzIRdMrl47suvOHOFMlq9EgcKZSM8cW1EeM34Q9wneG+hmi1jxmgRg05WA\nNvs9ns0cBAUoExbeKaTDf+UdQg8kQpTj787x73pVcySGZAe6vE/iMHRuSiZo8GQ7v7UaVF9ntzDG\nTtrPWvFHyuV/SDdzax+LPSONzmqYuZtNNGc7rSFNjipVg81YgVclfSx1PGAIfydo7Z24e3Gz6NIU\nMwj2TtlQKBbeM3mx05abZdGgKr2KZg/G7mtpHcWqPBAwGoOynrpV4ZdlOI7jP3SkujjjiUQJ8FdQ\n9dU1KADRL9hr5MOS92p0+2CDZXdgK1l4EzeYC6fuN9IyAXHsqWhfswpOubjlkJfdxHP/GX3hjyHO\nUvlaWBcZDw7BAWM+AX28BwSssw+yc8sPIxzjHKVjNVz51Vpi6eQgVAZfgVeW/CVd4po9zDauDBPe\nLW3Ffrt6P9FU45qwQ7MWE7oZ3zsTc0evg2krhbb9dLqiCoz6VuCkphBd+BhX2nSPTl+BrGC3EtT8\naS6sDKIiJlBJL+8+GJ5RSEQoTGfqIs6ND98n26dELJI8S0uXSltTPxBhra5yloAd2F4/mmmPjyWr\nTQxaz9QC3JZaY5ciYNddoc6aIflLXGP2kZlT/V1zu+CW+BExE9WpMnVToGI8RRt4jv0a874Y0An6\nHhiPkeDYN6VUowNBrQ5rQnTkFaMpJk4oWUQE3v6avp7Y5alYEE4wCED+ItD2AgaKwC/nFgLMfAnZ\nktUhijy2X1yEewInb5S1xc28GWJeUEjeegaSJijHmFVUCwrnggKTZlbyJ2a2ezSse3QS7DNzMLsw\ns3lvV7VDvQazHXN8RAgvOB0B/CgfYjwZQnyysjBMCOEXr9ltmJw3ogG/vxGHBu667EeL5qOCFKZS\nK2yY/1setEN3lBeyWFiOt84crc97yyhIN9WLadvrh/f0YfzTa8/jZpqi6C6YM8s4vbQgQayL34x2\n47QkQV/JCgk47e027m4LJl2YsaOwIdm0CLnMgOgEGQPFdyZktwDaQcho9eG3wdeeDVrkyzQormhu\n9aXm2HxMwA7LFBoLoLMTe/h9G0EmWJjSZJbpYBym7mGdw7mGASxg/8DfPNQ061R+2X3xcnmG+cIO\nvl0+UTTis+WrgnTXMMvcqbanhkRzuTaNKehiSLRg6bGYM0soIp56mfxn+lCOLxRvrFVCb4SESUTQ\nh41pLzHt1noaHrzs6Gg5F6h/f/xdaHC5qixpm+GAiRp0dMj0xX0roGySULb0Pg5Ik9k6Txub6XiO\nZgO5zmj4Zg5w8I0AnXTXRWRQrHzuRzUxeqeeMsb/JspTSY5oZj06H3vlmxUcBhypLvXrMLcXh/Ls\nc3bNxQvpWzLBqqdhy2tGJ8fAWkun0YPhNwlUU8lBB4Gk06kgUQm222XRVdAheeWAjR8NbiAop06S\n8Wy+XiAj+daeCKkiouMukARqbllP0jcynVe076LG+ZgkcNqoPU37HDyH9n2pGf6ZkAQuwFeIbkSF\nPg4iQ36vkP+KaDnRItQq5Ii+DKzEOXGkFXjeyB2kGs1noDV9eD6DHXsQa0azeB+0c9fKSA7nV4Mx\n1BtiwRMnJT7JPQOciedKCuaoP0Aq+hvnG6MBlo+nAOOlQfvZ8qQxlg0laf4f6XLVWOpAeGt6y0pr\nAw0YlMDiAyvjsrh3t8P4eyWaZSoFPRIJLol9+5QCyrLlm2aVeoMUtwJ1/53pTKnTEHcZIZfi1n7e\npjP+HdzVIccamu4mef1McNibQT4nUfu60LdH+ZQICzwZKDu6slLfWc1KaTXs71UCJzmFmBNREiS2\nXy7c04shnL9MVkGQUM4rVvlqeU7hjpj2FNlt0nq2A7NHDHkEArM25UeIzO+An0jC3tn+qfMDBZmx\npl24RVKkzC2NhWcwhhc3TGrk1gzXt5aE3zkSTGv9pEL/s8V0XrlWQBLq2XFeBXgLpSAzseg2st1r\n71IH25LcYi65u03YZ8TaQSNK5ZQxrVBVO+JVdqF5H+UcYmJxyBsmvTOso+y/z+nGXXnu6Wxeb2K3\nPMCSNT7G7TIbSFmkl2cSMzEeMwmt7AyMdckkJzv6cvcC0j0fLIcJ+ygBucF6mrNY7OMFKMatX0PI\n4UdpryZPtTB7sdMGLH8FqHkw0PoHM+53+V3rRDIo+ImSU7g97SHk4uMmW9/lU3+h4QEVhf1SsCoH\nD9SCjVbJmWSx+5ck3SWahLdUTGE0c66fdQ50VOj3xxA9nvsgL6x8+drW1LZr6SHG4Ma07PvqbId/\ncOHrnVi5FevEja28niNJV/635eMPcCA8uWcnSyTm1J3Fe+CyROmWWUPs1QOJLqlM/Ai2tsSCIaui\nrBVtakmXqv0aMhA33NdtZu3vrog0aJfleoLXQUuDYIGcGc8kfavMyQBG72eZnrVz6/tupr3lLY4Q\nxVGFP4Jxgxq1oFD+d8nf2DrnUh9AyNvtyyOCKi7z+ReLuwDg4jFzd3U9eZQ7WTDxuOYKmerT5+UO\nG4qs6dNLomx30eVvW25a2Z2qtWBywQq/MaVipSr2RmdVavfkdvSb4lRU8c/OXc2j2EjLF9uwD9ij\nR+SremaAbHZZKoNbBX79rPCGwHPTuu2e/3veCG7t4yv5s3WUvVkFPocYD2rO92YBt3DE5NjJ8kgM\nBCj48v+cPe2x069u+Nco6d7scSnHpPHHPSM+6Py5/LgYVagzcTfjK8PlJARVcAMsLJiBvfzpO+zb\na4Rs26CnEdvlCgaKBV1YLeJ2dXWhGAXTQg7SIPEe+qxZanakqfbbb2xT8QLylB2wpP6fAVc2MhM7\n8GAoec89XNo9PAPakTkcl0WxeigJFRkS527gXqWbZigV+8fVkzfLL8ARih7A5Y8faOuGrHTI1D3/\nzLMHy7/g+ESSQUAfGIeRgrKCYK7EMouPFRuxC5uxAYpm5W/pKsdIPrBHWTqvC0PZClvqzFXBi97p\n9keo4Q8i5+/jCqoMSKdh43uf/t7GW8Dcg5wWxhGnjWC7PMUgwEzMeruqNa0zB76K0zeUaOmh69WT\nQE+NgpCq0rrPFoR4W/hxQ5lqPWMYVQs08oixXrdi4qxOlpMbrxoLJ9dbreMCg21g+h8idnl0Tl1L\ntZ5uVIyA0sfNcXr37h71rInz9wjZ2D+cn1MJf9A+S9uhwm3BGTz/4NlrrXLFirxI7VfKkYEQ5kS9\nUmJtizU6dQ6Ehg6JDdHxuh5l52FvU7VuMVMozDJdJMvbkeQHAh3I0RSRxjaUk9t20AqO38NUWado\ngkUnSoEZCLnKpWk0YPx/LgMwFeFUGPMwCcZ+o4LM/G/XVGe5eO/pecve0eHmEnfeVBoIeGUVNgM+\np5FXp1hflAYwWYzb3FqUrZM6TMi1jBAtwoA8RkCsrYN61H3rOO2e29xzDffAshtKB1dXBUfI0Zxp\nVN8o0s2S0sIOL0Z6Y2+38Wn6hSTm9pUH+2vQjPt5mmWo7cg22+s7MbGkZISOJNCM1mCrD3s08ZAJ\nwSe0IXxQ9GoXKl71fWfyxDOEN80E97kYHfLwT/anINNK4DYOqinZPKwL6lPcmfztT/jkkYeC47vc\n2LKundEqdpIO8cT/NlrAVtDH6t3Fm9VABN/HIsAxIiNvOpHUSrLSF1keYvjZzNPJ5FRQgPns+eTv\nGP8JvC15MCNYsPYO03i0V8tim0p2g1ZGaidN0DRZ+8QURKlhGPX747Npc+Sns6GK2hOpqQs5xmC/\nkg05svfxeKyBc+mnkDT3BuW6tl06gkPpjvfgTxknS3UtGnjHnLRzXmIjQMl2IQ0m0gzzccVzi/72\niZtemsxeuumi+UP3MrCWaN+wN9xfBDV49pifJbqDeSGoznX/Zcb2XT9kvtBFWMmlBG27ZlbXviyw\nPnR21Qdpe9Ga3f0oQjJGGlKrEtk8kpZXg8bTyYQAlP0cxQpKZU2EjD5JPPrHfj1jG8shz+Fu/9Ho\nMoczpTM2n3rQNUp7R8v0cHO6ikm9/A1cUv3WjysTiu7SuCs4gBkotSNY2Xk68SXZWzYgFxmK8HXy\ntx9sdKEH13yEbULEXA+4COwl/PywoPj/Nl+Ew4Pwcm3TnoqS0GSPt7HJPOo2hoOxxqB08tPM+X0t\nB9E3nmeN6WGtdPk5mkipZRl6B32i/Zgg+ya/eRdCQdf9fg9Wyl1aioGzWlZgA8sH0At8Y7gl7NYv\nGsBJKYY9eIu3oVdG89uBhlUj0AOPcTOGIyt2OwESMxURJPXjak9Yh0eSBLOasPf3rxt91kWGROIx\njBiT8eMt0OnS2yu5HO2Eg40cmIqsC2vwtJoj9wOdu3zeceXfhMsdMoEsk85U9XUNedzDXBDY+d/K\ni529zO4iKsBwTRgnL3+Qq6lgmFdlFvr4PT7x/PusFTxAe30moNx7vtlthoDXjY69raOtJEVg3oac\nlEa+QrsLiy6szONetja8Xwm35OWq22kBLLd/fhaSvhSgxFNpHlINTa+dJ4OHbZshSM479f3oy6Gw\n36CHvvAUHpTmQiWWOqNmmUHHHnMRxvyySNkV7J8hlPk547mUpXPDCAheNrbQCq7Zg9QcaiQWd9qJ\ngnrFkLP+BjGxkvJwrV+1jUS4ymZ8io4U0EOc64Tuk3B2OXy4e8bHbNs90VoNbogNJ2JBBrluJx1L\nQ4+/oI2p1bd9BrWyi9lb2v+KL4o85RzAFnSU5vGSjrIx3lm/ZH/QN8/90o4qJsXwnwzwywuIEieB\nDYWlvqUtcnk46xKGSj9rr/PSTZBd7gFkW0W3nLbd5MKKjVDxtdiKjSV30e6iwgDQZ5rKvLaEPVul\npiJd8wgHGnnZRT6oMODzea5SMDG1Mx/Uu8SQZWcFTOb11D7MmcZD74Dh6kGsUS+qfY/P6LK5ZyoN\nHNMkZtEiQINbI3DG2LexnjcnXgKqZm2ZXGavRz/1f3A+4d4Rw6KoWfXIZOVUdNn/l4FxU3xw44SI\noKl1tT8NUagrB/gafvUWFBenLnxPxW0TaqMp+/lnAdDvwHLTwf2p56K21HxTlxXAb2QmgQlZB6bU\nDuYRjWtw96PcNIcEhaffTdNRFC37g/+Rw8qIWX4+euwL7s7q0kxKR4/TG/OfLrnBR/5+jgJGxj+u\ndtyDwjwrtChjTru6KPXODLvAm97PhZ8NRtb2Yzn5a9LjbWYSBpxjf4eyfAdYjEw9yPbjJpi9AJAW\nmwhWv/9b5rkxkeCEr4yQ7tXZTLx9l9hQktow08Zlh6pE4/8M86ah/0BFrTA8TwV1MQM9W2oncjGH\n+9q2b04TNO3wbncrECEi4DtBvtfYup7Ewyn3GlaO5eYLTg2/jiNmLP8fy893XZvRFmwsQRwnyXCo\n2nYZv3H6iAokmm54kiA8wDeKeZH5bMVRb8coUhzn+OdVrFqyf8myg0lyTJzy+bzzY4Pah1/xh3/L\nbI1bdfdg2OoVS3n1aXMOJQSoBQzk8F4lkSgV14x0kEgcg+6I2cD6IG6bQHCLflY17NMmKnX7MQeQ\n9ARoZL9Ftb6h6jt+Yj9TqigvDbbli6iYyt/3iLvMaE7nKbkI+BcyGR8FeD5rz5Sukk8W6WTDkgsD\nYzu0DTmAkRvyAwCKiwy6bzCh4dzKWJOK4GMV+psXZepr0io43Re5pRIkbdTsNzCzimW21WR9ePZ8\noWGZGUVoCCHkoM+VhFyZgrFBCuEGtlTrL1OhJnn8G/vmj6GzP7ppzjqtQOJdd1NT3mIJtM2MU2jK\nSJ1bL9b1YgSVmGnENvIHBs2oDoiFeYB/AdsDKbam8Ofe08wTbM09FVlDEjl4Kvym/+mlqBqdjB8W\nBTlVuLz1Npwe2Rqin9pAfmf2mro+7Q+P1t2MkMMBq7+mNXk6t7f1EZ9CP//mfVK5vfUlm1bJwc7h\n7zjymmmA2J7MYyTiTZCFm7zKpr2m0yARdirGbh5+XEerjM0JG1JFcunC/BfW4EJW+aPNSQhpCcmS\ntpvSqc1TiSkWDACL+Kld4mtOaUOVAjJ4IPoOKrJtnDz5EYLStpqmXsohKLCt+sy9YZ7t7NEdk0SI\n+i8nrAQsijEAoguMLC2r4fcfepagdfAzf18AS3Z8t8vItfUFlgvlByAWPD0pAxEeL6gRPo34mHvp\nqtb02SaAbEWUaCCZNhoIT+MAPCCwxxu6OEN9VW7YQw/hmrD4e4GyB19xhrNtuyh4zHoN+FX72opr\nxOkXzzghtXGGsQ2q3/6cNaNiE7P1xigeetIkjYaEOogeiEI0BuF1fbJDaLfReX9e6jXiLvhJ5AQe\ngiPAl3g0FjDUcmDqjRteAhE/PNHfoJUSgu55pPfO0NY2t2Z2Ye8DF9v/uGaVuFA1bhi9O6ZJfE0V\ndCrNoO9JVtPWadZbKqRoRYR64EhOYf8QMWXpQea8J6pNasP5XG62E3mNJmZhsEhO8da14ofQAFnr\nuw1npXWWvVGW2OGong7N2Kwh7SRpeKL+2tVeUM5oyRkkegprU8oY6yDTmkgW4gzR3iUD9r2yEQQR\nEUrnBqjowX6/a2UbkSvengDsfeYrIn57XZhpweU0dH5uBYP5FkquBKbngRzDWRIhRjpZOeNBuquj\nX6fJiQEmJedr3pyKIPHyXEepzbIAgL5Wuhzk/LNljrsUkTz1/vK9wk75QbxTXjCCi0MlhBUnf0Rn\nT9gWptFSKOOspcWHZzz1bR3qAF6yX2iGIpC7CBqaPPjOSnOIr1Qhts3FByUz2W7IrG7VFIApG2Qr\nZEpY3450S8oEjLqImCdG2XYabHF3KyViSlBMveVAn1qZGku+UFjoqKXKLREhng3hLqooi6ugvH3F\nhLD0lteBKSVsoGT5MDZ10f0FHDYuDu8pt7Yx+avdWuF0XQUqscn1y0GeYS5kr86t+F4ToSMW3ovR\nH9BqBMW/e94nritukUh+pUU2ENfgPglvuqcA55FabulEONPo2iV/4CdTcW3iZD/sNsGF1UHqf12a\nGB0N+vCYNuUpx9LspYpJWTeHOQslPRs7vWN8S54MBEJuS2EKLe8/vgESL+G2BnW7yrnXdPGpYRi7\nantqD/KGvHSTv4C2mNcnINFPsx4e4JPlmwJwsIHL8ez4LDfzGkbQo3znuwcl1FgqMpr/rZfAbjGd\nJnMlIYAo47jNmAfLXWB+SdpPEJgdYuuRi2GQKLWkI8JUR+/CMdKDssgcEyaJyvWOzURvv1hQUUs8\nPkMdKt81i7zFYQjiItlszd2C8zczwlH0eWE2I/wYLwBYMkRn868QftUBc7WCXFXvjBndT65IzaLk\ntS+XJHy1Fk4Cnnkwhr5UiOJVKXMm45H5EKxjwXZ8si08tIgWT/TPY7OcTvYc4EdO5sqbIrOIlxcJ\nA9IOjMcJqGbEoWMAtk2ASak4RNiXlg1zb+mt4fLZDqvemjQOEytIdpDjsKXex4b1kwug4wZmGlki\n8NSMfJNHvGf+G1NZ/qm5S3ZV2kDMvsq1CbBFSw/PxZ+mi7bChotalY0y4uMUAOBSP9kunqJAUrMn\nS2uohKVUiU917LWN5sndUR/DPUfV8pwKaCkdxF5wwUhxZriym4suG9nSYCjgTo7RtHPM8zJ6jadr\nTOy4MQeh/41kZsJ/XYpc5ElRTokVajxpABDhLz+d8fs3DQLWhTQ7dAQFzaxKEHPQYD5+qYLkSURA\n9WeBKvZqJTRRibHc4nbOfxRMxaQc+EAAjELMdOKS89L0XejFvCUujsz2fzQBJkpDyfKoXWLRko92\npzHpWTlhRDA9s5b8PX/AR77wA5ArUGNjqLmVzA1pp9zbxZdgpjqCLi9BNmyv/dg2HOuQs4tgw0Wa\nhIkwx7jfZ3N+FEnXqMihEhWujWBIpFVWJJg9UJ8Cj597k6j613fhjn+fQC3KCwnC2yGWi5ohm/8M\nSpdCBPF0n3F7iEKeRYOe9LRZGXKsa7cPF1dK3NOLqS9L8s/I5RGmzzYpuJX9J3AdnFkFX+eNJqg0\nKMrTPSxtaHUEe+by0YZm0zlcR9t+oiatQXde6yVVzmFWgcmsoz/fDx/AOOCTGxthX7cLvkDnRut2\nzdGY+x0SPOUVq9Up20+HVCHHJVdvlDHnRcwiopLP9EVVJJ3+8+zXcRwdR/W0qU3e3tjHMQeLcQKh\nJEXrK+Byiw8OmW0QMfzy1sWD0q0/sbMxlvt4eq0rHv2LvmpDayo5mQXKasNBMKdsSCFzmjkeVXkL\nx6lrIBNQrnRK3F9WHeo1St/Vlx7gKX61STdUZx3s6I2o9Fu5kQ/n87oY5kGnfIYy/Sqe7poccG8s\nnwtvT0W1l8YAgjLp+y4ttwVZN1u2Tib7vNpCGWTeUR4N4HZlfTWLkfxHA9E6qHgLyLhFdQxD5MjF\nzFCW5kFcsPysIWupF6wd+bHTvxMd9+e6km+LqJvwX9TJm0/Tuhv5smOEetrL85LZL4hoOD3gkOD9\nux8mkIV156Zn5qAXgRhGCBzTAoc3gdEEAZuM9CMnvGFt7nYQqUWozJbVNIu84YUuW9UaohW0MdBq\n9OmTNAp1jaYXjqH+ZcW4yCPJEkJKLw97SJqnlj0ts5ypvSx0AsRbwVqIUkBHIRTEuqdwXy7ffZPz\nSuwzY87QGmpoKvLB/NF/8a/XOC/8ekWrTlyNU7kOVZdUUan4xgg+rmtb5dxRQOg2+Cg5yB2KYpFZ\nGLIJEaN5ePx6OuNsKyGAnoL8VB4CVbYL2YhLksaWv9aVH0MSEQBH+d+Hhh/hyb08on14QDQ3IPn5\nPOfH37BX1Kt4ZT9FhH9AqYK9+IYyvlY1QZqMYqku6WF19aB5M1k1mnxoD9qP2OCDsvW0PulTcPwe\nbZWzXBB+yCTURvqwPmCCGg7Botgo7UemIA/YDo6uZQhRsrlLBqrNEpQRRJvwcCZadPmql+bxVLoB\nHRd0slNjme8ocHNUYblDKhFKIO4zGW4vkVS2xu86jFCJP+AUtWtEoBbRuFb6se1EPWSEZccg/tdG\n3S+yZwJXmSQIKiocBNNsoQl0ZuYObaHJFh/ghdUlIm9QpTkoUQwAdD6P2fVXHsUxXitYILj9Eao4\nnl7koAUxv+egJe38T+XzWu3qJvZlze2xvOmAAXEjVQQfE0DmYJfZVFKcDVdg5jYqF8G8FxSmQcxC\ntIn4gkrqg6EV87gisbn7qspi0sacZ6Q/1gQAURtDxooDDK5gsV0NEhI7EyoinLXjZJ9SY84+Bzcw\n+VD19FvREqBGtziYVyJ2+YAO9kUgWbuDuEy3aFnNOeTv9ze33bOAoAhBDtbJ4BJZt+eGcbWYWlP0\npMcWI4mKtcX18daNTCZR+LgCAw6J/bR3KiArm9ML52M7oEzMMSX7skvxyTaIj1zojGgXeZXvki/H\ntGHQauTSObrzhFf+YE5t50078XpPzdQQVhn63OgOKp+6Rie0Q2OZJJP1G9PXiAViKajwJ0U6IoUK\nVG0LJhSYwAOF+ditODWEnyYQJx6u4HFg1/OYPbRRf5SL0HEyB2SOhxzRc+QylENCwbGWxkJ/MjpF\nucxP9yehbXSUmmAXr6u8e0PlT+0MEcL5+hML6XanaR4sMnepTVUB5OQKCOhz5bVdYkfJf/AZhI5u\n1tj4AjxaqRwn5RhHqqcjspa9oAXyD6fTTd6VkJtf79obE2Vn0/CkZx5Gc/vEV6Y/UUsQa0+HNWxC\n0KxJ/LqbD+0Xo9hk30nIOWumBfNHVFNABhSH0FO6hXe1h7DRvhESnhSo7kGWpv0N7/A4SIRMybQt\nC3MeWIdBm09lya/sOlRRHwnjh6BgZeBEtPqYX++mSFDadrZ5912qAYsGsdIFlk7+p6xospuH+IyQ\n1PP4r9wg6I1iF+wSIukIJgfswFgAGBtqgDHhfMaea99tCTbBODCxTlvVOkbfZwEcdfqDQJioj+nY\nkY//DSMVhLeq/3yvLCdiembO06ynPh1byTgwmALsU/RT7uf5DrZBontbQhHqEaFGqtf8irH9r7Cg\nJC23F1/SWnAd16dLnUjiqbXwbIoLMHbD3pnqvbyyqy7FNroWPX4qTHJMm5LbSMWNMGR/l4ucWMxV\nky/QnNMEU4wvxoK1RI+mCtU7cdIjq7I9Jx8vXkCdnLnAXFb9QNHosk8LwZfmibS/xe8bBW7lTtzc\ndbpZwB90QL9ATHHTbwX997qQwU6f8Q6ZjTVx8VzS23VGBt3KmFvGycKB6dmPyzvkFWiQW+Cs8bpN\nvwr1sTQF8HierHVZSIDcGGnQ2RcE9sHY9ywA2gug29YJOrasaChUvfzGHMkvgAeWBLoNN45Ptoq1\nHNYIOiNBDDt8b2NxtHOlftvoV+KQTNTItY8HuSuvucGLRFZ/ijxZMp7Gka8hw0omBjJ3K/Canqk0\np/nI+kfZ/ww8PnWSkJCV3iTei8yb9akSyGPtimN3DRXg+nm9F1vhe6ZjwvfxYdXsR9RM2YFddDJj\nPJ/7sbG2ySqr5AI3utiP/mJsP9zsIUtciEXpzIiY17AGEzEf9WZc01mBXJheccBxjLpk2hOmp7DW\n/bolFGQo1u0HwOCjvUQEN/VnOXBf9dUC8dHNpljvbvcpY97VkVLl1hhLXJ1B6CZ5pcmV49ukA2yP\nHUvkv0kKuJDG2kjj4LUJ5YXaAGBdch2MCw/ET+X9R1Lbz7Tm0oYfP/vj2oQjxfHEux6lD/Urc2oI\n1tAqwKd6r/F2M/RmthYfXTEpVDUbiw91v8Sh4I0wwtXOQr1qrn4qwtP90lOT+tlF2M8TKR+rerOz\n/5Xgv0CCYjY7xCg4tuF//w6fpvgs0Xp8n+/+RRHW9SZuYLcjNkECku4X/bNTWgMoAfJIJLIPFZEg\nKFFHSa7PwlQqsQtO7f3M30QtV+S6oPKAnAqXuAd8gNhhlzMJ4O71NOrGSrsYdqyKFMu1pulAegSk\nQZ+uiKAj5kh/P0Ce6xKJQVPByIdBLuUdKWrNSvLdkjayB5YrzBXr2uR8Z3qtXmVTRrfhblbKcmVx\nbSlQCkpVPIWCxkOIc1vH7QfvkHgkz0Vh1O4Br6JIiEDbSD3WhYk8pT3YrbNfBhL9XWekVTilmC+E\ncoRGgWwOOnLGcaI7bxVfNZzqrCajMQSnYQUipkO9bAkBHiMkdegZfmnOCpQgUhIRZAmdKCA5IYZs\nhcQolXWCTRNRgfH7AkKeeObiP8KDY1vJ1LZx2YPiRrfGHoQeAVKnpo5Q+XF4nsb5FDWlbSF9WK4x\n3r2tGTKoamdzjbn2uks7TO7uFcTC1hsh2iFiECPnECYbt25QcuA6GhkCaQDMVCRlC72dzdy8cM0X\nNLgdEMCfAuh/pfO5Soab4eZFkdYi0lUKw2JYfFUm0MsvAYUhYEY0Hv6jh5aRNCEz+5cuDw7ufd7P\nmvD82HTyuLstpgQVz9MqL2IrFX7zOwsr4Iki/sE9jhAIqK6UNb2lrwHuhRS6OETJDguQycwqveDU\ni5P15/S9l0xzS0bAffASHIiHDS/nna1mXJMzNA92v5SHt6iND+4NgaspRFj5McYl13C+pzciz3D4\nX0zSkKlDQTpJZAjzqyduOgXcU5sROz6raPi+V12shPmKE5aTU+nt5baf0/qBBo47q2UjQMY75tMF\nRVal05IPRf/HOpHBowN7F02gfVE7H44F4ERDK/Hq1xEtrOFK7H2U3ec851+lya2zTCJR/Xcf3VBe\nlxb4RN1NWaePQkEcv/YWnNpQx+wtJntRzhd2+4ZsxawcWl10ffFyNr4ZHupqLvX7v4I/hqx48thY\niV2fchI4tKi54R4OpsCf7NZMQeEvUspEGjrcQxpHVgtMx1vXC3/lApBlX1jOD1aTwr7ThB9FbEPp\nc37PFCi99PpLZuExy4twaIUSOK+4IOfnhrNzP4+bb4TObcMe1gbmAED5+fDlwoMUWWRMMzWsyN/A\n1xIrOrM7zcDWgLZLcIOfS0spfbW4l41PKSCbIcNrB3jFSBrcwm0pQbneAUYkURTiw0Js/NskmPQ1\nqg+UnXhDdicyH0Wfn4tVGjaPXG+qMWBP4Fx3Z4tA7m0jIrR68Ao8aX+cbhBeS0kMS/j246amm0/s\nCXDiO60Fcdr+vOQpO10O+LjBwZ5qsiJnpnjeaJqXT+Et9/jkV5Fjp1xJ3EnlachHDM//79eNvK8/\n/JKOSm4wMLqBigZLP0jzbtnwgaUT77pjjr7T1mI5GQzeY3nuBOxgyscRlg6qA+96hZ+yXXtVArTR\nnf8MO1ycpLPgEkAEsRETTvNnDrfQAd3EFl4I5oisHtpNwuZC9DBflnl5hDZaZW8INJHxcaYffeOA\nI4SZqRyHEDisnaRsUSDIwcwj+tUhOyJyOMFqPYPu3W8unFFJc5VDswkGf2v1azZ9sqH/+QC2r1+q\nvmU/p4fmXXsNumWv6mJCHSInANf3xj65XGYYVUADHApABy4FLykn1IX80gOG/DkB8tArpTRIvOnL\nymsyFKe7bYMu0tUnlo2TPt/h8MeCWZiDdodmrMWa35AxrWLyT0U3n0ZtHC6/Vdt/e3T6oziJ/eVg\nlSZVzkrl/F5IvDwa6bvb6U0s/exSaMcTOHYms2e8B986/g+KZ9CjNQx8CSaf/8NGvuVEXtnONlx3\nLAWQZyLkf9AlRhWJk8otSYNkhQ30sHgRnkTwxaL/hxEClk6MEI+Z5UJt9ycXKODHuULHepLOcPZ6\n14Qufb3ZpVjOTbYmikm1m0IX3bCoKrUhj9oXXboV9woaTYxH8fx08ABGoDz1wA4F8VMn3QUY+F4A\nsb8WtvEmh+XEuRlB1edUNrN8WEkKjj3TwLKejJhrheVTvDZR3LGzRN5p/Fiz3f35bZUALgirF+Xu\npJhpoFYB7CAMH8og/F+Jlma38Ms96J/JN2SLV6bxpjWe5s/aAFb/m5T2WMr6f/Fi+hR3bYw2ANUU\nuDrYb3BZizZl8oAm3Y8N/HtMXtiLLPo1FuXhV/I/dqimr5RkGNYv2vmFyIRzlTWvf1OoQdCpp/8e\njsVRC2nOL5aja1Gbrsb6xLI7v7zOy3OXXnL3A+5G/aRzJIi6OYRIU9iBmF4cPrBOeljwsiThjyIo\nKFFxbCwY3TLsY5DzxbRnwXg5/kBxZOaES7X3X+zHI5eyla9CnQbfH3EUEvY3EV/37+8QTasY1tOI\ny905e4+8SABe51gkubKLjrhy29UKH7O2fYpuytamltn64Cdq4NhqTcnJzHCqZsFlQR2d3NCt85uw\nAMhm34FtpsIt7/67XzcvPhzNtotKCiLKN/Cgm6WqDNXxXQdqWBpk2t0ruAhp3IlUhukD3Wg+LyXf\n/ZO143HqZM09ejrB30WW0BvJbccuf5qb0GgBxnj7M/eDXJJPxea5jNDgIz5AJ0m2xwLDSCHWb2Wv\n2gTrQlIYnhFqNF51eS9oTQcHL1NUd8J5WhoKC/tnFnYhqZPSXTiC1F8H3rMUITUwIwR4Eq5f/SMy\n9vvjUuHFbAre0sYO884yH76/735dC/HbyF81vbM7uEaXpOBXKXUyFJwP5E5GfEcWXmllf5c8aS/0\nX1aavdNjFTbB38PKSNPR7vE4GYr8QZDsjsYzycp5vB/F1X1R55r1oHlKyB4lyggTZMjolN7L0+/K\nh0SaDpL1hBSp0datucCgpkHAK1ECDvvnZz/EYs4aUJdU/3zroy9RYIfB24/4jNs5h5aCBTMkmeiR\nAMIDLVnyEReJ7oVzZ6u1b6EZKmUGyoE/NAWcRmSPjTUJgrzF4ERtajmDO5hzZdyTOkti/h4tFdJl\nsaYMNAKg0w+186Fz7c25LLBkit7BG/wjrAPz2cW6JI3S4ru5pGGi85VQsoeLOW80nnosEnFDip+V\nJ7aDxGq9BSwM50DlrWdIxbvLObiVnLR8Ar9HAyYTzspjd0FPpeLqQVnWy9kn6nIT5CqukkpCwcLo\nSlct2bLxTcQhrwQucx5/LHBYpKkrp7rrzkHZ6P+cTUcLHJNyJPZkZK3heV/f0OcEsM4EKLZpD0g1\nJv8wATCKBeecm7/VqyQllTUUWvP69Owt0G4XzttdIBz8DTPtaI6ts0hlmbOkcDTTvBf5mZ3rNmnw\nlg1mysjyO/US6Fuiq9t9+3Xofstc4bHEm4YBjGCH1IHTDzvQccKfnM/cqleRvo7H5eXiFsZtPp1G\n6GOcsXHa95RzZj79MoKZNjnpEY+t8YauJ+ETl9KG2HPb5yLpP6Q6cV2HTp5GNHhvtcCoWQBAiqHO\nbxr7/HrkWj51SqQJe0KV/R6u46GvpDHfkVkDlouZTZy9uiFGVIo58fKeM3Te6Crcktg/2o5vSjkO\na7Z8yu/uzD4/L9K5yC9W0SCtqS8uulGQZpEHMWNlzCWY+pOvRSTSp73IL0EUO6DI/7fF2UjEWTyP\nl7qk/O9HvnOrrWAV5MLHT2Axk1W7H5akhnhcPAA7Lx/Q/Q5iLoPNHVWxjlvlwLlwWq9OaQICR4jq\nGDNMi14HM8VyANmSUU50AAoSn5ABDzSXJ9eUaJT/oU+O6OyAckpg07u/yYW4BkTMw8xIioyNOSqn\nvyJ7cBAB7X6KOj/KjRLLt2J94Qj6UBECe8x1PJ+/oKc1U5SNGmaDsiJPYE42OuvkHxD9CXzez4zx\nMiigISEAWNHfQrcy73vctjtz9y0ieOjN163Or2pLp5RE+4EnBTO68tZ7DiFsYAvgyApEJfTwTzS/\nH+NfjaRftQPoB23DSbd4otwB9wqCTcgyKeHfwrA2tWNoBnRRDh43MiB/X3InWXASYwMqfd2bTAXB\nO2ZNmuvDjFCqHdc6XOPqtha0OlB3JmvtCjQqmRjfwBDEg9nRrUo5OrhjinJ1ZZwsA6X9Oc2M1jUP\nlgQgjlV0P/hsZqt/GDjLt30k3e6DvQg5Ye+Kvn8MkqXne8Omnj4K3lzvEKXPYgWrAr6+t3IuGKRO\nr/774W4XqSnQXDXYSsPlm5VAGXmAqncVo5ekdQw9di1hmya76/G8VcN4QK0J/Q5c7xhsRvZUhBbD\naoZnX74rF3GIzaxID8PujDrYDMP2QkRZijphPCywc/l0jsldhR2NB4RW/kYPN3uUqK75cVesEaL5\n5v/AR9/c4p8tdoJRCWfRRBN5m9RRDQl3XFMUCUPifDExugkQfos7EIKRGrXely/Hf1bqQd84KBHw\nQgmROHDt2QlItAPE/wtivVzftCklyirO4+OmfkftzxGbX1/QGxAlJyR0gmm6RvKa1YoKUrKgK5S7\nXscl6MYwHWn1FJriTwerIP4mWdDdbOdCyCWKVqrv72q1sgu9Oofps4WpH4Id8HnAUAeoyYdHVdyf\nJnSE8viWhzvF+yf1tjrLZZySiZWT+ad44uIZkAqC4GRPwpOiYMPcB2Wa+1jl9Sjtp6expmx+u/5h\nAqCBE5nVYwwbNJ5/97wkl/T0DZm9KVtrlWoLxqYBUhTAfQ/Vdd5kx3Es/xK0tvL1c62UXivN7/I9\nVqga2Z9NvKTT8owc+ZOI0CANprFE4IK8JbXKrTc2NMiULmEnCU8OGYBYIMnkxGLerH12+A3ChuLx\nHIhcg1avfqvOounj2H362C2fJYDtmMVv5i0y8x0+v2FBjrTzdrisolTypKmUZ2MHXga5ZGY7mXqn\ndgkFBZOS64qYD1nIn48V5Vlsi7LF5aLMCOZWlXOw8WmIF6glbehcEFsPSnmyeQWeFK9duIjIEiYC\n2S0COsdbabYyYPGGFpz+iI9h675DoLj4BC552U1qA3tp95Z5GrD+9NcJQeNA3QjGp8mHde/skpX4\nYkex6WxEDA5ppcdy4YJO/pIrDUz4Y+KJm2AHQ8G/1UYNLy3QQm2xvEdP165sZy/GgTk/MxGtmTrE\nUumAVGVSTzDM3pMWOXMbHsDiCoY+LxKBmOofdTajcbPQor9UnJOOh3bk79plZvZkj/kjgc1ipavu\njT6UFxbm9ghBi9L6eUME4BbN+EiorSLlyWruDKS6fq83mX+4iaCshfP6nQnuTU1728nJ1U7J8h9l\nq+nruftauizB/m2VnGlEUGvC5d/olcqk6pWiMeuemTJM5+/BeAZ82XblX62hnpwo2kJhh0byu56B\npAUGKnLdamBw437+UlRRmPWEp2UG5OrqjLR0JMf02lGeO+AXXllC0ji5T+qUuITeYpHEadr7rg4V\n4vCNuTSmTymv06ja7bmoQR69HQxh8GWBKzTOLLC0knyElBbtUMaLTK8ocsuJxklx/fiJ6dcTfyay\n17QKT9aSN/+h/kzJsmdd/rSI6eJuQzg5lq1pM9nNggWdnDkZteF0Zg9YFqHbGfJMRqZuHxiWWHYf\nhs6BYwa1Si9yITAbky6OYkMYRRXLKB11R+pmRoUoiwr0xLh07t5UF7xEWYTqv+9KueNxtSOeV/+f\nEdo7uzq0Dii7Z8WTX2z7Aga6oO50BUYS7Zu9EQqXr8lj66On35fDlpEVb6h0feMPSn8Z7CCYxZxv\nrrgpc+B2PXhRlSumar1I9au3GrGSzbXaP9tYa1pWTWneUxksfdk/VkDLBuWlUN3jc5hvC0URlDsn\nV9FN14sxPOVWYbJt04oVou/R5XA4BNMUei+KMqaZ9LsMWy3qKESHAs0vomXA0Q1xxXac/zDN7LsB\nRTS+2gszGrNQQd961iFcXZUTQQaittUszpL3Z1wklSTLGQ3Do9eYkpQ4MXTmKjEcUcTkDd/8NA7M\nahK/cQ2y1mYEyJRkYFICvafpDj2h3+Vrzbg9cJ/+E1y9pNY2lS19jiEtaCisx04TRLUodD8TP7UQ\n4/ijc61VHaWa3tTgXuk6D9hD0oCiJOSUItz8iavDq1u7eDRCMKfEuHf2v8Ddhmkd04t2N/NQRTRb\nIoNNHHHBrQ/dszA1gWrgEV1xZ0dKWps4R/gk47Ow72agtIRoPMhVUyWaBgxaaEF9NAB/0Knc79/h\npDrIRM3UDEfbvOJJfBhGpmEXa5waa5PjxFrms+lsyTs58QeBBGPyfXH1r00fkBCCrhrlsM1QQTrU\n048xf/oyN0tUcjE/B1ZIBe410V5kNJfAtxAh2VPfvVbgbecLqGm3bRUljE8ozf1n6ARxD6GASLmc\n3GOh/dMJqp5oJn2sOFwv+B+AYOeGsnY8Qc0sa1DnEwTVUhDCZ2M775dMR3zZGEM/kk1pALwGQ6Im\nCnigap8WJ3+AQ+x5TZJsjWnnsZFbKiAITDP4+5gG9BpBQwVL7bSQYfWAYV+HsZNkpN9DYVKoz2u/\nbNnXohT5+gKpBQYKTg+h6XWaT/lwjspKXQkftnXwIgZC2EoA3j1BVjXTu6ePnVHr0azUwa7rhzUe\nSNoCfmOWeqnZSvRbVB+fRNZRI4hAVPpgptKPpCgL7DekF+8a8+X+Rca6jH9KFM6Vat3qvo4j81hW\nxg4glHb86eHWcUlzAW4wQR/D6gOuwjzvEi1jMpNNzZda2vtnd6b2QWQHKGtf2V3gPQNE7qp0z6tn\n8zMGcmW/WdC4n3Sc9GSGmsVAzNkoJmkCpBSMUwSbM1Tu1dX8eqXtI53zosOPO/buxyAkhN9sXDC/\nt5lVZdFQB3QqqT4xDjY+CwXxguwKeogUHQlcmu2PyndG1/ZlougRvZrmb/Lkw6bwLFHnuYLBZbov\nvAFBpbSKNKvQkZfTSwYiDNvc8BMFjMmjcFamwmizpssKFLlKIIbAUGDo7/9giFPRr+jOsQsmEYM4\nvL/nKadZokw3N0FCPbZNG7oP3I1wFyii7Klje6QNyIu/MqYQmb/XY51Tt3uPm7Xfc3/tNrmlri9s\nqzbMC9eeiwC2HkXHim2p0c4EKVWinPJkmzzHhHD5XqOMojAJPhX+ZblrNiwdx7yZ9FDd+udt11t5\nKBAtGk+DkDqFAWmcK77O05i4wt2nbfCYpoKyN224bqN/dwJBUcvQDeGU7zCkK9cY/M1RyGyOrSBv\nuZdwpqjj52VMyhC4eSw0VKnH/dkjXE6ob2Bu4okt1VlwfosxgTLiKv30Nxqa6xsSgUBdLW76YgRM\nSSxCp+DlI4KsYaCpTLqAkTsNbWs/XXcz+KkpZwGT3Ak7gUk9gWYDThPEGhAMifMZoNiuB/frOteo\nErLJDy9+/CBi+mwbqwhlM1mSLtEL+QjKXQtFXnAoKwlV0A0S3Y1F3eZVIt6N7EGpp+GqKm6pbvJi\n19Uv96Xgojy6KuRIp/r7ylJhgsaZmktjQVHgyTwbhlwc443FUjShzjYUNu1v/lv/ma3v07n/Nu1v\n5Ygxneefjd/BazNEjUTdLMV+xI/8Z5v2ZgRVVM/EjyzoDUtDR+/Fc3MUuqiQt7vYIQ3vJshwAQ7H\nq6dkx314RtY4hRvZUCGU+rnX/qCmenpVXFV2xn6Cc/5OF4EXbr6RN/qhCuiD81yAQd/NbjNEOtMW\nVmqXqTPsOOPY+FHam5EW4IxjWPRsAIX3P6My6Rer1kJd1F5zhDJbArwUbEm54c9GQkVXxhTWYIqF\nvH+Qp0Yy9tyMUnRlASj5jMvgwe3cUuHPxlyPUuZK+rK5ayJVxweBf8s8NsE58TFti+6DGNH+GMoj\niJrcHMl7JIRez9U7WoBdNSTa6Wu4FsIQskSZAPRnqG1YIhSSsLnEaonRZ5jHn6PxFIsGHWLkRRTM\nPYYKNKVMipW3WnaHIgiN57KTb5pXBGnXQxTZWgNJ4Oc1Hb/CLPxx+jpJFEHcrEa1chVQZd0SORaJ\nC0zRLJ3K6naY4bpkuEtRGvqnEiC69i7rkR5IYJVZn4T0L/IaF+HxfL2jZBzUqPiEpBIkGRIoRoal\nnAnVsez+Tf1g3sKGGb8Jc7Bvv9mbKP5r+ciY4SkeEHFCjRtXAHTU2sIxj+cVDrOGcwgj04QZg1CG\nf9j+AucjM1EmfmYfM6GMwlJ+jju7bvRNsowv0BBNlF7J8l98+ikv4vmUYM4WSkRV/jc+XOLWD2y5\nyNpM1OjVk1/KAG/In+VQAh+vgz1+4/xoyotLH/qRGT+bFxn9tomW0+Yzn/gahFC7LGrb3bI0eQTp\nQSejapmUj3nSlxVQ7dpQNZ0NrLwA+G/GycUyauRzRBxKtZMNHDmjfuBZX7Tcy7YiatzCZ6M2eST9\n05E4HperTb/cfGMm16ME0VdyxSZXAmb+OckEFGyGvWLoIVi1AdQUkJAh5rbT1QIkSS95m6iNjS13\ntFc+QIFe0S9X0DKXeRy730ZfGzxDHl3mt004W60VSMKldSaBLcHxxkrXUno6fZskEcRQEFd8weJj\neZkjtL6rtwkKjYV6x+cAqIRIH2CIcwgvi1MM+SbuB7Ej2OHbWGsH+ae6kDWlG5RxNhyL9DD4xcf0\nDdxElbdQ8rphwwoJvoNEe02bsY8iwtjuSyD6Y6clNaL27fwyCzjLujIWDUy4CHvK7Vl7a2PLD+dw\ny3uIbO9kn1IMMIKHSlomNpPap52CEIksHGtfk+4XSYfSkQKKp/kNqVVR1RPQGFToDqSveiV0bWAu\nSEee8c2awA4VDSIte3mzaYqUYDEfpBfjlJ1kfUOttH4qAi0IgL4BL+9FkiKjuwGeHVs7r+v2X30a\ngWOPSwAX10NabuD1IZjK3kIAgJJXnmco2ziHkW63XC2rKj3imToI3yyPwL11wtrAgJETZGrJTxO+\nMfLO+/2U61Knhu2slj+hYdaJqoIn0DCviHnI7DIQ2fAgjjaBl5/Er7USC8yzu0STnipb7cjZiTZP\naakr4i4vGo4b9Bd1itUaJzJtsdWrkVcFA2gSmBCHTYdro1jelehFneB/aDR7mxtnjz4PoHdES47A\nOuvVgKpCzNoMR43wGwKzG0B32o2W4cyo5fewsH6eHMn+T4EedcuHmgurYiN62uO0nz+M7aIaaBjS\nbPAJW3sIHIEEdl1P1Qtj5bpN+FoHJO1S7NGnxpS9OU7QMPd0thdPovlaO1Whwj23a2G2ry9SoW1z\nY5olooVHpgXYzMH7/aKVZy7EIaC6Pq6ILrl+N6Ql3+UuOAhOVuIGmgA3U234T48fYm736NjR5Gul\nrSbC9/WbAzLVLiCWKyxHmQqbSEsaOrjhz+ddTL3rcvzVLwFzhjTqRWQsPbtItebs41tdPf8MvInt\nkHYDIMP1RHhTu/5dAS9h/X3tQYAQgRhCHOAE/4uMtfdvIjgAe8fs2gC8QK99+EappIfJfUkvZKML\nn7JtFbyd4wN7CU5dpNIk8/RsvM3z2u7jtDa1yIZZIHNQfTaJ8WmsrUrjGpbjbT5lPZoMiQt/jblL\nk5uJo5y4kpVNE9Mg+OlMSMqekZyUeFSHuGOBn2smMqko+UVNaCFxXInWjz4TYpqXp288S605F7cL\nLmqsI1yHvV6yXa/8DztLhmbusW0vtxUKU3I2h/KupFTrxLHKOWOrxyix7kJ4L/g8/PutXuU1kAoI\nAu9OkaBF9G4qAHp30Eb2fxolsyRqSg7tDREIfyA6rPwj7+gY9z+2g65bC2+O5XyzC979ETBl5EmI\nPjuXiDRlRRDNtKsOLoz98L/9GAnV0AudrPU+sgVjxwcNfKaRqib2icBzWMIIsL3QLhhQxLI6bZwp\neya26npYMw+VI6+huptBzOaBV//Yonn62HLD3MBmDEsZRbSRiedUiuv7FO2kTlQi66FK9h02Uf30\nzrbGSKr4sRI666hzuzBE11QBkJqOosb4dDlHX01MQSKIc2w5pKvfi1MECCATgZMZ7ilhizyPHPhM\nqYR6erClv/4mrKlfdy/eRyaWBenWkK0J9aQB62+fNvXWRJ3F5SQA4xtCLxOlSKoqQVV+311DUvax\nEm5l0r5y8XMpy8Ig9W/TOidKG2ruNkmtRHwn7fomGNnG+YRWvlHPYkKcrMXXVZYEHhVwrwv0FRdw\nqqilhFaMowQStCU6A/Mch+SK8shJHK11OJnt4E6n7GSS0VWWIoddIm5+RK6+DVbhGIGMWvq2c+/r\nUMAozYzqqMD/iC/ZUuMEFaGnsRaf7fDLta1A7VFGGX1JrfJ84/D89+TUzIoiJt2a+mlOv47F/nIt\nDAgtzOSYGKb1NhXlkc5js+oaoygWm3Nl2B3F52XQd7P+eJfDpWK2TjB4F1BX9GMnOlI5S3kWAp+y\n8m67tK5JQgHqpN0CZ6yLbololzSu4PX3gW8kafdkgnx/s11MMaGgmdlGj2EpOY3RmzfYb0zUcv6x\nrDj6PCQU7tjBx85GxXzUZpzyoW0vswvtkLufpFueFe13Lj/xkjdwrV9ztjg3RmEWpqEDhb/ewj9w\nMDgzH1m5Waee3zV6RsdM8OywzwGB7r3QEi4+TJUT7n93NRH2bl++VBegv12aakTzLHKbSb6HyWdE\nUctb0DJhxi6aBKuzwBDJ8IXilBnK5vb0oGMpyvR0+SIG/WehKC+lUhfpwyKzZ/x+BMz/AakXAFHB\ngprixyoHCJS+IyJRNTufZoRpXGD/NdpZEyuZEAOBoY4iuamF/oaWgXBZgaa0NGa7axmq8VyYXhhS\nXRaEXo0XFlyt34x/Hs3t5P2AwUqFOhBalvgxSFuIdt8s1SfXHA48jwEBSY2mRa/LrKm9DL7CVsfd\nW7AcoaS+xAkMd1ZA7zGD1+xV5kFBSJ+oUm+BHq35pBGjxdwPM4IYx5qL8t5y6LkBzYVXQeXrYz3n\nAPikEn834V2RN3BXwNBi++a9RQG/9kyZFKAgjy/EIEDqsZ2Fz1a5AD+kRnZMq4Gy8FqfvtzaDX51\n/24gW4s+KdESku5GMoJiIdxYoPSC5yYdU6maW2zfvhU7j/VxHIVkEAuL1jggslz7UvWmLvDQSvyg\nAOiGhRngYu4hcVry1NbfF4Y9YOxx5VSFvbZcdVav2L76PYXQvfZa6b5zAj8nMtYby/auDzpCGggX\nIFig1IHnalQgAmlg++abElpqAE9+F7wlpvxSuMr9qjsXMJFa1NLhTAuYn6KSATMLJtmc5ZgFjtV/\nqZI83QMNaqgB/sFXO/zdaW6lc3DKYv0khan0DLyxC9ZYoU56KxHnwcsy316h2kq+KlFI9JUD4R5K\nk+NKgW87SF7e2IsYnl9F4WoeUQ9uu1TrYwvbBQikWhMo5zGJ+jDNnZE0hXYvD7zLnrpjNxk8u1jB\nVI3+wFkgF3y9dft9r//mAputCiFpTIwLsQE06NCVgTlG73PCHAGOQBkEBW1i6c/u8at890aDr9FL\nJulPXrkRHnyQlGS6bml0RA8vNJpoVwFRl2QRt2qUo3qTbXDEV9aj3xXdfeEseUR6MQCshhixhNj0\nKU4YYyNjpsnXLYyHerXk3ioDeukDGLEyA51ZK07Szu2UDcIFqZ+ab2ZHiovr68NcLfw6YE1qkg9c\nYLT5Dk89XCyGIdn3pgnES+Sd0tcg+T5Pp7nx1EigHx3ZihMi8Oxe/D6guDWy5TSL1G0ZaC8BvFYa\nh1C5Pfr43DjEoojJFMUyz4w/w5lCEUBEh6E8gXjAMVjzFAsA7vDjdWz08GsKz+CFWPXVVrVAaIRy\n19k1gGQ1MRtI7CUf1wWh7f416K2hwjHgzz6cmETCt7TexIThgarGxn+VSXO5pr5O1/Fs179fijJE\nLmwfZInZ5GW/PJnyfU80Z3xD7Jf8tA9KEhVmkiNE+SX7QVCho8sBVQhT5B26NKZrKHXkuFWKcBsM\nBhB6mZkvndJIuBm6ALke5fJITcrvcci6rA987B6eGw2NVJK11fP8ugBJBkmiSCxH3U6uXThxgqMz\nPujL2p61OUB/0gPUXs/sr7qt6X9/kYDGwejPI9ievkME+XteHvCyDtPlq/mjoWYawo1wDIP2NnLV\n+0QatxMMZBMlG6naoEf4pifcaMe3CAyIAlbYCkFgKoMf0qVgdHd05KcNusDkLqz+bNqx0PyHucx6\ntQNR+G/WKS4eXcAdwTudTPLXuqY4T5dXr3EU/fhG2oKFgHJRrAIllJQn5it+B1ljBrm8BMXVZC50\nkm/y/Dv2k1RZg83xH6UoGk0OEw29nx+XrBNqjLBViBHSdzLAg7XUs4irDXyfhxGycqBdvG0a98Nk\nxNU46vJazVxZWSL6U6mAe6Sv3Sr9jGmNIgA/VdbNk/SIP/AhthEjNhk/19pheo85ryTp4KL24Vhw\nrSotkbHebmTArYBspDLozvV51DeBkxnLdq1AwEdI+kiwzBbiud1p9rJEfRCLlqRYOI2rNY48L9Lz\nVwjSLp1+SKY7ERb2h+5bygkAImLrivJNuv0yj8p03GAPfu6DwfwlYjr/ZSn5C713pe6Imf5odEyk\n2g27gNss5gKol+0fnIRlZrAdBphbK+HDGns5LVFnXt6nhEEzzrhmhY5q8YS8OBSR09NzveOjphSo\nMFsa7DV6Mx6FidSa3xeL8Kiq98kSg/JzKmT917YSdmFImgN839ZxMPonkiRYfizHC0bcdFfVJC9P\ney50x1ZvNhADKvxaQoVppfhgjgY4RAL3yo8CNeL+8diNOvxxv7VXL6VmkVHb0OPSK9T7jM0UNC7g\nx2kdywCP5JyEAE1ZYgyfhp0cZseW8D3oJ03+f6aWUefyoDW+U7lhbahfjP9EC67VrkOC0aA2r1qb\n0EGdy+Wgbo8LwZqlv+i0kT6JJVzJAs9m9mIkVRdSau7A6EtZ++Gui0K56HTnHxdBZpKPLfaMY/Vq\ncO5ShwiXPBEzE8G5dKmjHC+z12W1EDxgsCLar9+YOAjxKhgHkBGfg69+NmO0ydwiFZtkb9kQn2n2\ncakas/WtmPRcBrFKxTJv7hrqsa0tATeeQxEfLYe4qtlUzpbtLY2FdoNRQlSxUGJ4pGgiCSx+x5ri\n5dbUwJzYin9/1AkNrajyQ1igqFH63Oe5iA05U0OBHL1TZbqVJu91v+1hHGccThB7kV/xn+sWCL0Q\nmMULWQqEWLR9aFsTO9vP+2fvOf6Zwuefn0MzofCFTwq/kYuMgyppHBeqD0San0S3+DlRWFbvQxtd\n/2tSB+nGWbiKevmP/K3gE8oRdXigzg7xbPH+gh2lCC0wJmKwTgQwHIC31x50ZJkg8cci6fVAAw/C\nVHXrDrjZSiroK8utPInMK9UgiLiJZaxnv6VMTQfV26pYRuUPBEPpZ4PLypuOIcDs1tS4X6nUNDU2\nfNyzzsyS7Fs6nTKsfTb13JGw+dOOt4lMUIBEU84U5RQKL+jrymEyKK/sSA4kuQYjQXLCHUIIG8G5\nHUgZ9GKsNo3ugw6mpQdnfJ5cW5I10H8JLWrMiCExw/s1EXPyeM59eTd7T9tDoN1rAZKPHG/JN8dV\nh0oYFXVBv9sIAGpOy1+yMXyrapdwkmnq9M75xOw+4tdRAWNlhGUgeer4qaGwM1AiZOh9ICdC5zLx\nBQ6+b4pwzgxHxvbCVYSY3J/6A1H2OWZ/DJsHbkCJzKyyIJI6c9Sj+iL7IWOEz3kPoTdwojbxnFjE\nFHyzNYqDISswQg6KXYsPWTEGpB/obQREvd+ABflTfjzhr3Tjftzcg8LURNmOgUQANWT1DWQSbC19\nmfeCmEA3Y+mKQXkzlCARoH1uXMPPUpVC1ipWTPqeH7TcwHjaNCNhXgDS/uk2Z5GBD8YiHzSvAuVf\nKZvULyg1j21LI/bSkfQ7+lk8ROtqWPv7/JtmfKo4EJbyI7aQPWjlTqdH9mV0ELtfD7EbTPEhwZZQ\nHGWfHrL778ObaVgVlJ+4cur5V5ysxaYVfZvWa3RzOCv0QqOo2lYVW6b1BV6cZPLYruo7o4VgOq4K\nzMz6Tv5RTu1X/Q0sXm1kmGF9b7w0Pc5x3QBxIGCO+NzcC9HZekrjxRIqqqG9SREDtovJy40tvW9B\nVLyL0e4LS6wq+BG21T5Tm3wStOhCHnyJAneG91iZNFnrTY57YkATwIja/JJiSnDtzisBcdOXsnE+\njF+WIPe/OXaP7EXFwWnvQcMy3CEeH0v9WQ8R0k7m5/5LJUSKZegVF2vImSnXZte3+N1jLmIspK2X\nLSW00mKB9e7X0tmoffFcNa5K91v5qCKZP+jH9FlXfo6FyNfnHZeBtYWE1rFrWkkNoyffdTydMxU3\nHsE7+QvtoAiGifQOxWPvyL6jtcKpDsPkZKwWMaDS6t6CrUW2+7FIzIySi4GPD+UtldMfOgfX/xY4\nRwOLpHM0qz77Vk7F8r5igDm3YdRUclJRj/9p3PhuaGURCCOfvYY/1YtGyn4pRScUV0eI5mWn2HkY\nPB1KwhTPUTGwVWu7Y3fD26njzSehEGb15soneI8/j2u57nBdio7e76zBGd1Ae28DCxlw6eheUL+t\nVfbb+l1BrerQeAHVxnm+duuLE+rNrPfp+17NGTOlB2Qf1rcFqQWYCmgEI+VzyOhWARntifEQ91cL\neG3JS8IW02lPLDfwgGnw1jdsBDrP490+YoZQxAo1kmK8lSjgUXuTchXZtHz6I8/mHaTDsZ3ZJQA3\nNXIjfP4KlMMnUOG5LiaeDZ03uItPx33c7XIlhC8wCHIeOQHEnRoS7Ah4f7M3FP3oommN4YQxreJR\n/uAHpkr0sCdoRVU3J+7N2vwSP685CNjrqyl78reB2aX7Ty3g0hVKTHlyPzRgA62N3Gfb9vMrk+W0\nY78yHpQHiYOQTwAsjZvyYBwT9f/ldXZVwC1YIvI20GQ7kL8uvhV/+zbXVzv6kyjHg6HZIY+D/+rY\n9JnqgDOXkANYZNab/6uv2j1ojjDqBOeZShxkJkbTwoWc1yT8OmnQVIXLmeGTpGuabFKI9Zi6Q/06\n+HPwkG5LawIar0MHYUs4lb8X9uKIVauJZHO3fCfDJpfE7p0weI+DMayYvriGCPSu2+0cO66waMD8\nkoQKpOmFxHOrio+PflCURVPrWAdtiOVWfTKpPdCUgyjcX/0SNGNc+GsKLpPgnseR5baF4rxbWWCj\nkZQJhVLuPemR09jsCHluA70+mz9AXQAg/pa7bfPbMldU69lewVO7xbwqdUDy4hdTZYJCwX9TNp1P\nNpCzdGsgoswj/88Cy3icvq+rPBdxfqogbUZXI0ZcBQuBSscM9RPagLxJRYfOWbvPYakgaarvMURQ\nUKkmvS7oHX3jyOH166f1V6kX7iU1FtSODnMP0RTIiVB1jMY8PPv20LD5653dtu8nhpW/yxdeaulB\n6HrUOModOutJHPogWpEpYquKf+DCjyztBIiWtsXp0rIdpdackzsWc3l3gZdiLtsV1BhLCsj0FJw2\nU26qRLCKKxk0axjYCW1xbCcNn2Ui03uJuYtzjrQJU/ng+M40qPAoIOoonXkN2va+Z/XjAlJvXRLl\npvwhi82zybVUV7GX+GBE0mShC/h7yvkzFiRrRDA/RwRQur+2okCdE6dK8hr1zzFE10JBP0d9TUS0\npK2XqZN2VJ/BQSHEd38SApjeg4BZNbFB4+Qm5v2hy9XGHVWFBr86STemwiPK/HTKyvHbsTG8gt94\n4Y361rCNBFPqISw38qIcz8ooUjFi622Y/CWCjDz21lLX3iFDIFf/ZxxqVSlJM1NoqsTHOTYaVwF7\nhlfj1vG0b3l+cGCZNArEGD9fxGx3Z8OwL7Bzs63ULFNDz9lM2zFr4UU6eL3vuRH3yJfuI3H4I77P\nffLuBWlPBg9kdeOw+bZrrzSRIRmKmYS6kOz3Uyn/i0ejd+TPM5dR+qHmiFt7OZjjSaf6pYIDxuFA\nDZ6PvZDVBcTDMavNkIcSkwsm+B0NwELE2BV7pbI7jpTpkuTQpZAIcuURtrHRXOohYiktQX0f2DId\nGDX2juPGYqAkqHn2O6TuzV+PKfUMTryW3TwkT2rIqBqzrGBtN1hU0JVrCaZAM1J928FQGECowe4C\nYw3phOU/wxWfcpsDd+JjsNmQP1GrNaLeCvX9iiM91ya+u8I0UPBSSpBhbDExnHRQ8x8L+Nxrv2P0\njVZpcPraT1DfqxmICYoVm6AY7rdTgJrjclMbYmafOsUk5wRRTQVAYPBpGcA93u8qLRqEvvDHhnS2\n9RKzGmNUV0hKqNIF4f426z0tJi0IkRW0znccZmt2d8TXKzYkCOfKAliSBqpZS7bodKplqMqc4voE\njaPXEf1vKkbUQOV5HqmvUiJPI5Y7jQrosCCg5VL2/oqN5DodmIqCCTd3vdAm/tt/b0IuI5mRfpP6\nV2Y/cRCrmE+MumRavYpcem+l50tCbeSbglB4grrAtBooNSiWou5vd+6WISoDxewgOeJQGew6HhaX\nO3eGe6KfJ6TaL3fiJuZF3hZ9XXqyDuGrb8nQoAt6dqqzzDpGo1JaPScwI3EIpud4EhFE1Qti5v5a\nV3Vl1+6/UJSBa8V/BrByhZyt7xmrFz+1Bgy6E+Z8DAH3rQXV6mKOieQAoUPkW2mh9tx9xnFpbSsZ\nTPYhbec2cj4bGLI5crXAxEScCC7qH6wD4Zgnd+qNl2NdDJqKJO+4hUlTbuc5wXXvarGBBhgjMHLs\nXGdXVwHOm+Cc8rKXJvr7+5PUUtnwD8gWKxJXPimyS72D9CW6d7dkhkbP7lFlaWAatkkLR5ARwFbx\nMZAF9W53PRE329iWi8zBjf2WDZBSN2Q0TcA10dOE5nbnbfeT01IkqmqARAkQh+nTwL9T3bR2A8Pf\ngmwCqBj1+5rRlYslJ8CZOrLDQgDuLDJ0EbX+JSDcQd6jEyne6hgAaoZs41ByP/8g/PE2alqR1kRZ\nTYhiSUk5FbaPSLijYoL5o1w7Zy0qqdH/p9GBtm4JO9CVzc6hI09H8Uk2lQbJPzvt9YSlv3v92sQz\n2TKxXXtBQ+mUlziFQ/8BYitiRqoE2cdR+mE5f1X1YvM49qIirMbEuumBGiHJqvkqNUZBHU0ZgVKg\nvobG6mF+vwwH28e3no4tQ7zOa/fDVprzZjLGnvdPUjym+XCgbrKyypqUWKJ4/T/4PjaanyzPvvXt\nRlcGp/nhqI4n2u93okHPDK6jV/5phIyTYsLiXu3CKgu+8IRYdXYOiIo/e1Y5WDTKYgQhmBVshF3g\np1hGuj0SPHrrAaGaEG0egjAyMEWxwFicIsMjvHDzms9wj7SGPo6CFt4YMfar870S3Mr4rqPPTLEl\nKaX83QSEnw2lHk1wIWIFRH/7JbyQRSmJQSWe1dyCNY3CJc9ckpBwv+ZE3JjOz/eE9hu5cxojJXoW\nlr5td8y7IAWzChiI0YLBwLJRGcSEKYwgbLcICqV6JillP9J4X92YlMW6BHoBsMhB1DOl6TyZgMNQ\nVlZGWfNoYelupoRkIT8M7MzXISDSzqoDIKM5mr9eoSAo8ib6YK3ODFN1Ipi0Hm+qUVh97Qb3LCXy\nJ6TLZ7yBPe3PyN9tI0DKKMQaEf7MIeR/pJVXBGsWw1J8lMeUKMZGj/PNQ8jCoeKR8IQWRQA+u08l\nvi2HhJO/OOKzrT7wWfTqQ8JQJWoego0wyxREKsmJVph5puuURbW1rqMZ59X/1NWVNk/LbJ1gpEhD\nRDB7m4Z37EdY60O5sOgWAgfgocCGN+qw4b+xKacYxMN4HjXO+wJq18wCTE6+j/Riq53L1N8BhQ8Y\nGzmRansnzeytnsaTfsvP369sjt22XF5RMpCRvIpwnBzhVtSbsoEOecovV9J60ihS9Fe3klm6gBY7\nO27ky2+Nqy6V5sFI8PXp8SBwkwq5pNi/BqYrHGV+KbX8d32v1RUYbRrV4F6ptibJnNz0aU+HQQBw\ns4RzTcJUIJhlCEM+J8xX7HwyaUGYXM4Vblpw6Pdu9uJT0tjyon29wMG41c5BLhYFL9bVxSB0rylA\no9dhCoNanyu2VfmWH0K1eh+YJaNXtEb0ysEmWhCOAN/BB005lvi/w2S97ehdtGEWfujIFXRsvCgY\n+RCIDAxVVZqHL8q746Y3NWuLClwgx1vHx1NcQUcDBNsRytgo9Gb0DigkKNt+dAAIGmfD2l8RTA00\ni2rxwGF3erRv9z6mzledqzEO17RKC31VFamUnhcuZiDRaRRCBnE8GuE5BHaK8rw79pL1YSIawfMd\nLK7hHkbaDI3kT4s0uTl+t99PyWMS/B/0yfBkHsKDGfriLreKrAncpEeUpJVFKdFGrPl1HIHS5ZEX\ns1gVTXjNJJrMestKVYaEs4nViCstGD9zSan6JhEmfaifIkJ7GLKw+NimA9uOzyKvxUxfRCCFUSvF\nMprZGCfJ4ltS0NYsdjAs1KQSH/5sn/PQ6OIeDHlZ/n3Of315bRk57pzLC1/aVqAi8XLsSRefF/uG\ng/x4R0AMUW0mo2mdnHH/TY/0iT8LYCmwQO5G/dkxHjhJRFJDZ3qUZid99q56MwmCVIj6WDNBu+KO\nQN6QM5N82dHzc1QI4OMalKCyGwtF1fJoK6eNGi3dVQTES3YoHYpJwy9mkxPa0rvrWLS6/4KyUv+I\nEDZZY6lbAg/ozYCu+01v8P5fYavZmOXKq7EICFKOmUroiCAKQb7RAGvnYqGcYPcJRAsDYdAoIFDU\nroKp2Ovcei4dqjC/IMmPpx2utomxn1moEPZkeviZ/h4Jw8M+YkT9VrkRWpAoADxDnDqVJm9CyRZ3\nZYi06cQ7Xi+nISoqnuU0wG4niseJcLPhRyK/eN25gKr33zC0KA1F90dGy8K2XjjGkAy166Fm+3nU\nL2M0OoqaJrHkmiE5GOorVEOvOcgQPi5mcLYVduX9edasttXX1GWuqS6e+TdcltrvITA2mCaGW9W3\nuLXjKkSpq982wMXZ6Lezt5GVq0xxPV/hocBpYZGNk1GnQrKh6TZ2oDCwL3BfXTqGPrO2BfEl6Gt4\n/y3kZDSf1MYEfz0iQOKOy+lWAlsnuPolMTRzT1cOGY/Xo5ZfvbKryDcTb6bhVTvO6/ytROqjAUmQ\nTHPlyl8CeG7hdq6DGm/TlWk+DtDGTXDeiF5IwFeBRsJPlaQ//IAkaAdtGnFztK5xLzNvyFs87v/9\njkbEu4pvPLRGn8alKJB8ZZ/E12VD5owB7dVz3WdKnfFS+ewUVFFKFM/LqRQIoLDfau36JyDEBIoK\nCc9QhI4knWpjgd3rc0Ror6hYufUfdIhZvbYz3935zgckWWECuvAIgdz5z2ckO8J2UHAmrLdWFxtz\n7NFYheF0uQVqIWu7hRMmfPVEgJNVslEfrtSENg19NvNy3vkke892kD/uoMfkVuyjAkS8PzGBrXJ7\nSQqI6VjMifzTsYMS/WQ+kXXwPhjx09QEncMmZSp0thPdg5CZk8eEvrZGprWuaWpDs9S3lN+NV/qh\nEaMcIGIuEMxbxMgD5WtZb20rxjLc674wYAzoVZKd1k0L9/5C0iSgJUwYBe49dyDOKYUMctmkESxi\nVd7eT/IqusXB5Q/PLFKKSpIjnafKrHv8yGyfnTaBC+kzTlVpb2G++mJNfwSbkDuqAvAoKjPAVHv+\nqzQVAKQ0+UOmw3T+29c4atCHzi2+uB2N0pr3kiOHQ8yooLRMdkn24q9cxynSkIZo1/dARHNNdxa3\nCJv1zraDIX2a9McxBdYXYYPeFRe//3X0Icj+fafoR1L6ZnzJ8pkqjZSGr7s9acLQGxabvRMGFAlH\nVSEB3Y7eWvxapneBKniIGGujM8MXaz15lv9RmTiEqxfRsxRhgthrhqNWOlGWfz21p8uZT/iV0h9Y\nfzfelebsnPN2uqnYGEKFTYTm43VLTKdViucgm0FyCsC5i7j0MIw20+J+3xPhA7x4++Bg0WIc2oa6\nyZWBWrw09oorWa4VXS9O4jd/qCs1lXQO9qyI4RaWmg1w/2nMaDgx3InEckVMCboMIeiaxntF0Oan\nPBiBdb1PPzTtsMmzVNpv4Fjv/cOEPRIRFPibNg3qhLCCRI7H9mgzfUzv90GEsJjMVTCAhWsuuHo9\nwGzpvadtd3ZPmPsOFa01NwPTRw0Ka+zQf07NZ5o1vtUsD8QeGQdLQQ/Q5OKw2HbA/bmpERHgtPaO\nU2pjfnadcng5L589GtL1Yn1o8CLSPo3GBOJXJ+EEsGHxmSytk2TceD72Fzn1at8SRZcjtsb4Puy5\nD6IOS7UeaGPeKQA6l11RgJHgfZbUgaJmK6tPYXZqXja2NBHNAlJGUGSUdtTyFwrSw1v9Kvbta3nm\n9dSQggcFLN0jfOh4Wx4PkZqrNAn4aYXAl1hVDrYSJYeIi/g9UWvt4lKEKzII7sSP+/Smvc+DQI7c\nKrUPoBrCwwSIULOWIvTrmc/9H9lyRuvvalVYoO1UJ4h1QZ8l8Awyua3XBfn+LhsE5y8En3VMKVBK\nHDDhGXOo1ly3kQ8NfiYxpwcHcNdNtrv6maO8YQ5GRGqef7AdwOaB88p4d8Lo4SDu62Dzf2fkdySN\nvx+zps0lGn2ew4IFCknQaUtUaHVrSDUG/NZZQabVDl4WAdblcpbCOW8uTiNoFIKFX8dP4RYXgq+N\n0wODhInglAFqObFfIC84RBfDlEA6t/45rPMvS12+uDunWBSZHyVY1Uwvwu/pnI48lV9m61OsJCLO\nOIgrpGewilIwhStXkjxdI/PB+Vez075WfTee96epvw8Gy7kPD7RFvqrDDIrSGm93FKnRHplTj8O5\n5uu+yfmzGBWYcqCbo4mJK6V0M/SJnB1HCGbgLiRxGy/WnHWjaYx9bBqMbBHImuGlpEzPmfDKvgV7\nAlHvpdpzcBlf2iAEr4jhpXqh/KwnRQ4vJL1P84YbChWf4s+IKE0AZ6f0vl7phKgUVq+P+ULvZdoT\nqnWO0Ig8FCSr/a6sZumTd2V59t1HdZTvc9V7LHv7XW1ar8fwPredD5AYEDMepb6AgFxec1FiOc3D\nykbfBhIXJE6n+Yn+BkBfyPaHQtr6CygbQYqPxrWvwqNaGqiR4M1+SnXc1ZPUCuO3jpsqErNCpGur\n86gev9iN95nwRZl1czxWVa9z2Vups+DUDYNl6OGsA3VaU6eY+zfjdw22WdfBTQW1yLZbKdfPdglM\nk0W3fK6xVQmWd7Q0MFJx12rohylS2M3jRt6ymRYDuj9G2x7e5COQAH4HvGSj1xQao0Oqt1esrJ4a\nYIqOffOvsSJq932yvAK//wpl7jU/meranK6kL+SFodAzXhE5O9i3yUroUaSX5y59xIfZoFg4NHP0\nM7zEBF6QB2GW8onP2jBMjRx1c2YyjCZC9I2gxLVNFMuAynr8b5R66ZPqvrh/8y6Mqr83orbrcV1X\njrDazLR6yHEOtNQ4bi8mN7w1RxzLuL2h058RZGlSsTBsO8xP6HAr5Kp2wBfbvI57lK6CxqUspCj8\neO92O5CNgGOfYdotXRnXfVffA4XKFtgvw2Me/hq6OXRjQJn4ru2BJA8kDP43xdNfLhkeKIZM3AoG\nTcMCW6giOWLiADsnkr2ofGgeUFbW+ngIOyctXvMwRFMD+1K5RpwKmd9uVYsHK5u+PLBnvBGoyoS7\n8/m4+m5zQh1ucW8F1QfRwl/sKSrRq0ciF10lQ6zYZB4lLAem6FOmUFaoyuBVPiQdDA1ZsbW/Oy9h\nCVMHPZwPrJ3UnrPvs6YOfXs2Jlfc4nyTMV9gez2SwA0MbPHMnpIcvsBYMqVf1NbZumEG5UI4mVji\nsP+Lo3Q+cV56vHImYilS916X7mZ0gHna6WTTGV9UyJ+Du3k0Tl5TlYLHL/ob4uKWbj822Gt7tv23\nAJnMLGCkgZQbYYRLwv5C7jFKxzPsaYrdBbnhN8Hzj8uWglOv5NmXOcg2pNyIv6Xp7o3P4/taZy/s\nbavizNn1qFu+wczAKyYeOCD1GOD150qXMwDfJGIaD722D5IfvLbBJkBz14/nzS42fO+i/NSflxqQ\nIh8W1dHgXZR1+1xGFhfpNgJ73eVqPltXA5/xNtE6EWKAK2h01+j9T0mPP+TCq80DejbANcjNu+ug\nQ7qp1/IN1oZBnRQf0DNejhOdZ3Ik88Xhwy2Bn0jLmvR81NTNbmVEoZf6/LBhkmC++d5tWUODaE3V\nMmjV73rV8eAB0kRkj3yGu5GLwWEtbau6TqRGb0BcVzUlzqvF5MPetFqKTBQY6sJENoTXq1XQjWm6\n9wH63KFczwcmFRWNgBpkvjQZUGWcCIlioS4fuoQg+RfiCszpQm6etlOglZq6tbo35s7iHLifH2fJ\nXgBvGhw1Mzh5WLkhF0SZtXs1flSvmLCyJM6MwWBe9Vg1rncHvsaqt33+9kknBEsl8yJuvLzpWHIq\nIOyjgBz9NEl5RNUhBXzOzvIRK9F3Z+fejM0uOy+z5JQfMyUHKAEhEtGivvnuKn5Iv1yGYQbKcWzf\nrLxAQP1WA+5zJeTLRbU+kco9GYRaVaIvruvNy1wYXHcRnwEui9exP//Ej02tNULykhUHv7P7iTnf\nYCwad9m+QexSnt0Sf+x7TTYZGucEUC7Y4EDC2m9MsTtXFuhHgin2e9eHMTm7cMiFUf3O8h8Qszop\nwzWvIQZOkkv91HzJT8h4L2b0+s0LMTK978OOGCGHEcqUPGyAWN7nOu16o2UjvQGFPn79rD1sub3W\nU+zCmNvAttFgu659SJhYDXnvhUoNWhfY6acclg3KD38v/SOAfl/eq+85NRYWvJtweiJRYYtk0vVs\nu6EitsHfSy055na+HIelCMTPbv3+3OwB8KNeJGveU0qxSv4okxF8YWWxztNlTRVWwx6fC7LrHTJS\nXhjvKRWBJrdBkAn903FdNO406+gwfbMP6VAaTCMo2gsunicIpS8xTA9jcMdcnCyP4GXLvQi4UckD\nQNgqbWYvw5fxTLOWyf1Qu4u6Ul1cRBRNRqZ3sZG1iD58EIMSS69VEvYM1w5CWdFFkYZesNsF2ZAC\n4RTSQLixyOWbPHcCckgl3/E4FZCkIi1A0xsbsyirad4r4OdBa4ELnPi0ASWPuCJZp8QxIx9ohBTU\ncXKA+rgTrCgCLzavqrmNtp3Gr4WW1sfls95t68GeO6SScz+13sR+D3gkP998Q+3+9ENk5i7fJ9/i\nQcLd8GqnDZaJ/h36F7+cUQZg67jcA5APE29UEhwTU72sbZWGcGykxoFo6Wu8gG9xLNC2pPVSdS6a\nF55fpU0b9k7eoRIM9wJyDoF5jVRrL+wNULRlvZpfiLOpSwjUKnZ6ljjKtTt6qfsye31ZSpQbTEDi\nei67gpANY9oE+l8zI+oIf8eBQod4TXK0aotrRsx0T048+WvCuIiR+iczHejTE8Pdi8+enWorNp6u\nCcR1yfG23NU1xEPqbMjQdnMIw2T7xx8WBpnaS+nBJ1gNENmT+JS56BNxD6xy5OvTLAQXjtm+KiG5\ncnsBBCY/Am/rByb+pNGepykPoma6lXmXc5FMpKsySFKxXx7y5zorfRE9gSbCmTG5Ltvw4142R91i\n812qH7JQQPaumVCKm33BGCVGuitsJfOfv/98p8oQPsV6SftmQusOjQSyn5Qm+dlpy2+VymZDEnTc\neJlGz99qQGTvq8/CnYHNoTodEyCv3uGGGoA0TqUo53dr7ssSRbAFgdsyRHMDxepGAcjkw7T6laTd\nqtTg6VF8hWTkI7MN6+pMfl4m1JUI3jCTvL3r/vgV6Kz3ppGiAoXiSzxy4keXJ6PAPwFmbGMVtZay\nWyEhiliGvUyzaYlZPptWWhQOtNFU7fxXPiYE32GVZIx+SiWJLnWydxbRC/WlhwgNYcGsyqSZMFit\nsNGCmXGtYx50tvzGxQwzehYg0nZ2T3/PJDCx29bJ47EO9lmaIUUPuHUmene0vI1Pu3WArggyDcZm\nv2T2/rnn/OkCTuK9/cnfLCkG9PZvw+b6Q8iqL81fUCaMHPspDM/w/iL0pGUM68CLdUwOhsuz9jrD\nADfcq+EHTkeSm1tRfg+5QtFa4PgsUd1tA9j3+oO8OS4wuERtXT8tItcS8PjZuyin4U0+G5ec8xRq\nNXig33Ho45rUFp/dzkeNN1A0r9jrBnzIxzHAQZgfdTuGWuttmgbHPe/8AhXQ1iFepoTAzqrCqBln\ndNdMPtSzeK2ZoMaHjCWqZs+s8/+1seQjregjKaPbNxtmkplWus0EExT+udkoO7IXvlQq7BgPYo4r\nRpjeAfQC8Li0QA1OIq++poHELmQg9Sv753ldrgUe7HlrntwA8pnVfa3P2xWCC5ti+tEdtMl2Z3R5\nahgZisYsB8c1LNpju99Cd5thHlHl4q8bD77qMmBldsN89OKNqPHdYrbQUxFuR0cSUly501EUip2r\nJwNftGERUEMKhO82u2cZQzDhz17Ttkor/7NeO+Z+DrmO2e4BlNdtNXxiWIprq5n7njgKw0+Y31Z9\no5bBl4zCMvNHlQ/IuBUEEIcDEP1SH8hlHzzCrOoA3/6P17v4Px9APMiiv33ExsXH8T1i0iteJS07\nzLASBPvauUC9xNjitpan8V2eHxBVPDkLlNHX8+hobBnp5vRMSQcBO0JFm33M2lSRBE9ZNcgYf+g3\nkB2CVDaFyDLLvhVdXW034NGCc2deKjNDfZrSkVEFJH0aDJoEYzxeEnMh9d5rIKx3VYmcYHgw6JGg\nJBhUkNHmCjfh0vCo+hjMCPwH95m3vUFe1wKhOoXsIWyk1QJ+QTR9t+hZTowkYlQprcv5t2gWHJYG\nys6npKLa+KanvsrGVrXB32uysIZliELY0rvCu1lnLfOVG5o6VxHS66qJPHimhiy6XX4IgXd6zZiW\nYO7BOZluVxA1fF+ajFTsjY32A70kD/tRSPQpYwH9EMaoF76kkDLhsIobb2kYNomgtk7M503onnCd\nu64Y7Grs+FvIkcG6rJ/SZUqfoPbCZmvMJtxhS3d9eDphfgzSyg0uEcbc30Scvx3MW/Ka45FcPqWU\nTTJuaFa5sYSLgrtp0/xa2z1ZrvplfUMOfs1Ir4WbJ9S9rWOTG+MOlyxRJVANozxhNnL+p0UxBvIK\nFUnFSYxOeTffvL/9AiuwYKEGlG8TP4W0kgfeL3hMAL5gpcXggAW/2zDLba/syJhMD6Tp62ZpzZTH\nz/IPQv4NIEnBLbQy6BH4d0wGaSLfPyXvaUjY7YQ+ntuC31nihw1bQwaZ+MUWyZRcmiX5r9u7+XdL\nI1L1yZBLfdvFM+nIfXra/bYYxC99jIKFf7pNPlxoLNMW5ArXRg/FY+4oEjkoCU5VQUgZUNAuJNxU\nkjCdWYT/MrC1tV8BTjT8vgZqsUVG+9Q9BiJFhhAhyxYKch4SAtURNyGrLtp0SSnIYJ3B/ZVjzn7I\nxuxZZ2v2AflGdJfcDL+Rr6aLQdbjGj/+0zoSVfLZv4JbXBQwhr85A0tkeg6cGcxR9Vza/zc7+M6g\nJ5ccWZqPWubJGmJvKwm8cnMa+pcVTxa27WsCDyvS0Y68jalHosyqevLvcB3xDPTsn2uHlV+VpQcj\nV0VFxSXFpQmg8i91a+zS4L7xHHbrjcRUly+muThjtgw6ig/wF5IxtSpj5x7igdPnhA36Go4s6ycI\nIiK57NlcBNfiebdpAbi/w5sM+taV1uXqviHauEuFjtQA33Ok8ch86BdmtrhnfMrEJ8rHapBXrVht\nIdcFv0tQUfg2nx+8xWmAW0dbKjOV9EeqQp0I4g9LeZD5GoAP9n3P9uxbxza4GAUXxvg8YQn638cD\npJ08vWFIXQz+R7QyyTo9sX+L/8OhlUe57VaGzoGGHeg2RfhPUXKQ5g4vkHkUQq05nbCCuLIsc/NF\nA9VSgYsetAZd8ab3oI/3nSeVQn9BqI6eeK76MN9q/uGinlJrJwDKg2lAwE4Sx1NtxZUDL5Qng1z2\n+lwVJzNItzXwfBtFu0TCpNDRouYbIY10OgzqrgN8p1Iw4yC4fdfmvvoeJBaWzueEUdTT0lR9CbXg\nnCIcYnStmgLfad7bKNKuZF0N2BdtTyt02DP4LzxwMUX9zaxXo2s/7FBfFcU3FJuvYBvJNxclo8rd\nK99uOpDhoAF68Cp8f3U1xGQs9hcQFsIiZxeJK3ILBP5gp+CyPPneqHwgN07Z3h+9wvOFgwV7PuNs\nihcq9INZE5hivSIUv1J4uqxZxw2YOvj+4XtgILMDsLBUh2/CeiJHDnRXHHXa8xyHN/VEZlvP995w\nphboRlruPD5mR/ocPYK7UdxRiSWJM3aJzUcLRi955umxUm0bw6N0pSJ7JahT+I2XC34PwpktoFJK\ncnszLXBWbxz29fPMUkVIgrJLImaca+mZQRabAzDdtkZVBJfpiL95/WLyAlyEFqHx6pOn9YdqK/x8\nls+aAzMGETkfnoOlM6je/dTzj3l6Qegyttg6hacm7+dwNcr5RLP10+lmLI47KpEZMRH0JtDps/ey\nRtCY/uN6O1UaJdOhdtyZCpou6ZZrao39nAAK3hsYPS++aZgjVAM+j0HZPfDxzqTE4Wp2AHE0vEVb\nsbWOC5JkhFUEsNgxf3CZZek4tylhZBFe2qAPmca7Nr8cX+/fGwJa4zsstW1RSHzzXp+ga7T04RRj\nqKwX8lhMp83DKrFARIncMkCPhC9OchoFv6Gq/qOjB5ENUspxDy4S/IOsNdRpKsjsoA/E6+aiSeQp\n3DWa071ADqC3V/jEDFQxKj++OP+/pINq6Y1craLIugETiEcpuMZtIfeNmTtUQ9bQlnnIHSMgiiLk\nEYO/fwfSTz7trn+YBvKL5vAPEgd8EXnJTQmYglGi3iPtfYZCecyOfq3JykNYoLGzlc8l+lgHht6D\njBryf+zujUdATobQ6vmyUQSCtmPgv044olqWdpLhzoc9ASuMzv1Tf60b+vX3nQLZbSJuYh7SHxUc\nGxaQJbaAUNbtxB873Z2xQaexfwD0XIgmIrV4nTsGA8CKeZGD44WmVGfF2zAEj0Suw90pvxZ6ak52\npnNXRoiYA1GbUbaAPifn9es5nNMox1WMhiiFqkfTt6QT/LPDaI6pctEEKbhZABvzuC+AFV6ApkFQ\n9sEbC67oJqc2L/F5+EIi5bC2E4TuVw5PGllkgLBAmBS9ZJXLt8W/7AZzh2zXOiztarPYrGxcQWQi\n1NqD9kbqMfjq4GgxdfOh6GXp+/8hzguNrB0XOLT57jqu3ukdyPI/38f/tdSR8rVLm9ctklpFxIp1\natcGe6ZzLhkmrAWaEgXu+rkvalDeJJzYMCdssUggP9sbyIBqNm+bu0hs27axwtzO0aLTdEmRy7BX\n02mW+0eM4axPDPBXp7Km1zDETT9OuwhMcrmk9IDiDrbaUj5u9Is6RN5ZNoT9chv4XZJKvLR2ut3e\nQGCvbdUAVHxPLCOslYfGfXiNFdwL9ygx5Xv94ULNBynBX65Yc0v5uokgRUlQFr4KxsdMcxhnJrjd\n5mKOOdcKDyXcYKKk1YrFmxp2Mqa1iRK0gm7BoGrH6dy8ZY4obArr8X7BYzzkf4oUx8I+5e2BLyig\nSCmP33zMkZFpk/Auh1rgfxz/PbMciaPSHZvrsiCsT3mIopE+JgltnrrCcjK7GAdB5hrTS3w3SR1y\nGBavVYxjiEqnr8WlVGP5HbH08fIsOBlMX7LO5sciII0cGlRpn364mCbdp91BslmVrQoxcPaj+TC9\nO0MZi9C8aOZsUVk7GGBEye2EQ6zuEpA0PE6X2sUd4HqfaTrtQg1EivraNouAMLztKnLgN7pU/ETf\nK4iMYGGJzip/SjpXL4XIr62c0IMMYJzIXHBaTyrZ4idSxkM6S6Q/VUPOjO00HKdaRqOIH4Fl7siD\nQGdPpuIRj0b31W/7wIswcFZmCuzoZQGgj7b7P4nLZ1ugw4MHnHQ0p0zWM+A+R01iDJDTBdfEPSsz\ntVdGAoTuJ+O5nYpHMc+IAOA29tvUF0hLHKvwz719ElO2436olcY+xVc88CWad1ptcp6aodqcFyUM\nOlHeSnAgLnQRB4lEfJKprHEnN1TrjL67oHO/cABupwcFGBhTJebJn1u/nizRAVf+CKSUryUX1plf\nq1Wg9A52pO4nv4UPs5j2/i4PgDiSZY8dZu2YgE043PYJ5dEjNrmyvjaWkjFwtziqqKJ/zAwzxSfY\nFx5VOVen0XsXcoLpFHKH06Nbml4lnpDAxCdCAQlBhJagIUqVZUEIMzzBgaOUj7Y0E/Sx/MU06AAm\nb+hjKhJ4ht+9FDe3q31ngEpHms3C2CB73sGjLP85VrkgocaNNOGwWb85+dtp6SbR1oOXKGSgDIuW\nWa9nFDdb80zA/9MYuiTLZB0pGf2ysznBH4gVaJ86M27pJbE/oidnAlTQUPvFB38TOYQNTSnCNbmC\nBY/7Vz2hDC+A4DHGgWSJ/wWGblIidbsZpgHg1Xo8ekbgWacICP4eJRnFY0h99QUPrb9rr7nSKoVD\n4fgt/CUrqX9nvnFnEEI8eiWD+oHVrQKGRK6TnOP/839TpPTKpwfa5Qlp8j3ABCliKMAkPP6HOX+K\ndwjGgNzWtsIMFH+5fIx94smDLYyUxaUiQLsy44s+y54eVCf5XtKV7oMkEfvPoBAXlmhHKys2EraD\nKquLZQqsoRYc87pUW7KZ+/FGw76fQKeccRJfucdYfj2hHBcIaBuJUIPKrC592N7/WwEBhSd8nLa1\nLZKRMwzDGxXGYlmDMwf56Zf6OgqrCqSI/SnvV5mzligO5Au0AT5y8UGRR9x2hTLAohR3HhVudEXO\nowk0UJg8YDcoxxu0VpwoNbMLIcaEY1pemBsAdLqJhGMTRnneNxKrTtSgUwFN30HpP1fHg8FLhkHd\nFEhXXm6zT2mMHNhNgq8nbsHlIZj6lPdOCqJht4xkSQhmq+b4kwFjsVIOsR+y6Mo+C1vtZM89MyCi\n6SWt8fabXIQhJg+XGRqdh6vVWl5/YYso5T332zDvVQTlJAIu30bYPbZTre/xqhs/eG5/01Gy6nQd\nsONvdiK5TjgFj1gAUliaaUHi3VsgkrNExifz+rXAoecbj8lpEh36t3rEyvXjjGsAl6nV1UgQiCOU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mjmT3stzC/Xv3U+2KUtVN3IyoZysXfApjzYPxRGoY14wxVxml3cjWkid8wTZt/\nqKiZ8+DNGhOWsKqtYFfzvK3ApRuFrMQI4nmfP0ioaEsTGAw0TGjMc/edUC/KrxwpP9WbWlpcR1Mn\nyRmHmO1G980fLf1P/q5GKog5mVjHFI3YGEOry1qcHAJR2dzO40KJ0/5N3/Pxa7i6wNIJh/mHzFZ+\n31kRMiX98q/i5AnwSm6CIHRH2WptfuJJu8bOdHyEc2X/ZykVW5x17fso5tTlUjx5p+HR96FFUaBH\nlCZQUHaHREVDgLoo37xNLUuVkMHZqp9r/Bd63iatA1vtI53HEnJpU6AsMLIsCdkY+Lf82Feavy1/\nXEAxqjo7H1QoA9YuFHqbS5WP7hI7NfNQMDjoqprgcz9/UB7xC5WYr8rq2d5mgeAbnstt5tE7sQm6\nQgLlHockY4CJK8Xvmv4d4SblYXDAds1reKTgyhuI4ZtI4IEsIdiA6/FCJ2Vtw+GFFB0zIWutZ9Qg\nvRS3DxbGOPG7mDhBr7DndSkrx0aocMGbybimWSBSg54OO8poGqinGYfYKzIcnpmV8De9rNUYTd70\nICpozYFwIfHD6uW/tcf8vX5K9TD61i5pXIBimaenR5BI2PMYIhZxYqmWN5m2C4lpq7eUVSFU6cJU\nDopA56H0YzS1Yghkaz6ccapw4+IWSfmbW+U+xxGGT3wNd/C0LkyFKJzdCEZLxeZWC2Om6YAKNHn+\niFQ0gxa5wWQPwuJ8ZhYyqSk/q1Ta/GqqRzNbWLlZC4xztgz3JY1yx0g4gGXDKlO705YMD2H1sVzh\ny8FE+koC6h6l4i41cL/DFsmJm5Jqj52bd3iigktOLK6QtleXtA6WLojTYOnJOguFYPtthxaSvmGm\nqQTuLmCdlOWgPxQizNJRMRBTiuN87BktKycizvXRwigxNRv5V2btiXkJPtyPyqkLA4WN6rCMZBko\niXN3m7e9ovTge7aNZ42IWrAY75oe3jrfzduFMjJB7BHwVaV1dNpZqNe+ZP4gzGhO6yKU6gUhhLjo\nhuML+408orbEV4f3IS8O1PfQ+c9afO72/Ivqt12Iq1YNG3EKdwt+NulV+j6oevJWc1U/vV8MrQa0\nbeVkn5LMWMAilgmbX61R6wISQo0NfBGdFL7yL76BwJ5wauMZ3beZYu5smvlVxpEwVhQ8fFxH5Xpo\noihRZCSnp0L/BG8e+f6/sZJ3g939OWCjOd7v+b1g7lOXhRH12gLTb/5yvbYNu6R73tarKDzA+EDC\nV6Cjc0uuB1aWJB/N+OrNOcVXKhZcotiTMF4vDqfRNuqt4Lr8gjOQdRbrQEveoS5Z3dGPAUi07lqg\nqVZaKQNTSVTGNdFooKDV6jxrbpDI7VfHYQeRlcfaGQ1FG1NFjzlHBtwZAFGM65hXUyuLRvTsfmyJ\nKoaS6UFC1MuuQS/l45/VFm1tfQmlNWunhV0kpPrB8jg4HzKBk9f2BfqoHchtOGcUKTenprkzbPfn\nw4lemz9G4I8Lj5ly28uFVHheaCmKS4+8HGNam+xtZvyfd5dpBY8AcoNMtHr6i4UmfWaURIdijXdH\n4Bmll6uW4Pbk+DGTBh4mPSh2on/JXHVKOI+tXmcYauiEje985N91S+0Na3tbw+coqe0WLnAcRjrm\nq0HRhBFaPvHkoNwuQKN20uBjwavtz72na95RG+VD89klPSBmoG9U09U91P6sJ18GtlDxXCP0UAvS\nYwS5AWhwvu1ZBenlPuvRWL5SCxKd60mnVbKgePL10ztCgNJWKHL/tYG5erl6R7VpWRMeuAsivG4L\nvlZh1VMUk7WcEFtlQ8ewoghZgp/iUiIGdB8UYFsMC2n0jF2KlbD0qxkuacheyV42MhjTNrWOGJpP\nb8cLqovTnWaUaEQR4ox7qhg+i7lW7pFMSIP9k6dZSVrywanuiKxyZEM8txnRmifM5BWdVlFe7o4Q\n6LDdZw4TPzfPC/79pncGr4kcfXBeItIkCz2Kb37YPXMbPvCbBJ3buirX4xlN4U9Fzi5U0OI8rI/m\nxEaubhXYIo1C1wVEbMmhjjAYqm9mdtqwtK34nKt6UA8yzfBAKUcRS9C7ComgLKAnsqqYmQ6+d9du\nQEqBOA+dGyP5ei6S8XQuTmoeHBEzJtkaDcSReujBlwUYKT5jEDk0nET2T3W05RN8O+I1iuCL2zEk\nCBa9XojaCW7WnyD9fHIfIlVP3k5fyrMDshYPSJRoF+L3za8tcsFxoTB29Q6BjKAxZ/R2U7piuOIo\n3MRAXcIwBS55HqoJGM2SsAP+FtMEdbi9rvWNynjnYLT3VWrn9y4dpa1PzuBknAAIADZ1iJy8w45l\nKMoZndthreWqtx5WJ/NDeCbjKlRUXo+VcTOw5wfPGjtROIJrk+a0pBEvk9IgkLPXS67zcTg3SmX6\nqQGKLp8Q4wEM9wWWnL2h6O0wifvd8KNCNPziDdUS1b31LePR/mZo4s8QhVTskrjHFAb4QUbPl7a6\nHLudISZ7yV3Gmp6lxCIVCJYIiPkLiVfwQRSQViwIUWt6BCc960d/MqoOz0fwpsTkdjYr+EqA4FGJ\nwxJLPlTgl2lMVKdWumgkU6nREoX2fmCnx53Jl2LcDzdxTiKv4g72G/QzytkzP/3csANiNniXJKyb\nyPEYM+lewTjlwyBrvA1Hseq0rwEyuZIohPauQrtMD/CqgPghUCPc1zEUWqtbD7Cs6Wa9Q6i9cZe6\noygam6u4DqOHve4zENyA4vn6BeFcxUULrbhaf00LyIK8JhVfO3PgfxROzcPGkUTDn9lNMcgSYFw1\nF5h0O+k4KTZAuh5WmzhA07pUadrHIEWS84zpb597LkMmlP/Ir2b5DSd3a9WrRzXtffoW6wj+dqC7\npakKeVaDaFLsKew4NQn/5Gv2SSsl4XFUnLgN38g3e2L47gMZVmWlB+Y2pxNwsAyXV5zrfZ66+6NO\n/atnQFy39BdJa/QlM1kXvILZzqUOXKGZVYZLaTWJEug9PUV3sxznlaY+cyInU/Zyp4GnlbQ0XVJM\njjTgTXNLU2xwchHYZ2fBegrJgvIFGdryBZ0iiPdHvP0oKTrobiiLLzbV6OGhFV17NAM1UtiiGvmX\nCecPeJZhMWSNd1sR0zXBMsmK0TzQz9wCoe+6xVsyVVjA7V2FOPwHS/UUbVQY48xEuz3BqvoRTDza\n/Upe/JHbXSk9IhwLJhuQT51Ra6cPMWmXfgxXBAUVwMzzMx5nf38uLxEbI8HuxHJNoAr5GGRdDbDM\nvIaZdGD58IBnjKY6oHp0HRYu4WKaLDRblLUdGdvRRYTa8gDWhSNjXPohCsckVTdJP+6e2e4QOj4j\nERJFaK63X5h0QsmZOgpBr0rJwPTHnVY6GB3YKBw354eubQ9K7LofK66j6q3zT4Guf8RJUbdEAwPX\nO76Nk2K/YZetp9kO7l+c5cAIr8TwXPfl9w6+CZ8CwysJcd4GCwCkfBAE6qXqEVKayXnkzL+/gi9q\nYhodZUcg9N6TE/MQblA4jb3J2ttB1IdT6RQqaipYfiglppdRbRW1Qij7hpryOT2LWAgda1QDnOCw\nN/aRmOHe3cYkOP7spl87Ts3hk7E2Ax/UCeVxagIHpfy+FrsHZ4qiX+k649T/cfEl5rBbvmxA/xiL\nCwG9iyKqxglcf46ESxutKiDbBbgTxm51oe53JUdUJ80WTQ9/VQIlCKHVZPeWam1by0CZhhQ+FHPz\niRM7iAkCLl0ad6jbmsTBDB4Yo3j9GzlRn4OwfvkX+1X6Br/jpb7Ods5R9sYdCU8iirwHrrDeyl4P\n5Oa3TjRfEeRc/j9P7DyMx3ksTLodItG9x/vZWgOy4iFOa215lI7+X25rZS1Ummp/5i+Xpg/2bqL1\nYc6h7fbQjdpHUXjn4QUz0LYvmc+BNdDxx7TgSkeXOeHhdOTNPZBaDLDk2cy+lw8H7HLME+RVBt1k\nsXgcUBHjvvnpcteXo3EY/4mNbR/ZqLeXimXlWhSbjhCGYDzmqa5rgtz3n/CYymQhxCskPAQGw+sz\nezc1Bd1Gs8eiRp5AYUfgRpr4jbtwjt6z++6Vu8p97biVpBs1ExN2/VFrFqgpOJw9uA6QDmVZnx8t\ntsVnG09ksxL5q7LXryPT74zfhepy7+7aTH5YUpDpb2waeTIFvBdg8gmxXZB2ZJNSvEFEPglZ4KhP\ns5Wo15NcuLVfQySWiiEeFOZVqadoOuNZDghUEifrUf+33tFg6SeVx+zBDJbH89YDSGPONwYA8KZ1\nllfpAVGLBseobFKvocGgdqQf5YsUQQL2aNanPQqWDHJHr30u4IJBVKuluk8tjx90eD5z0fjoCqq3\nJds3DQnYjrQ7BU2xCixiaN26VICrnw47sIinfFcVXPidugt7ZC/KdJ/aQIVQbkrgDLjDxprUS7W1\nFffseESv5PsMOXQPCsFvlKPUCAAM4JKznpl/d5fx73jhcyMXizSXCoL3+8p/2BFB2u1ZYbisTH6V\nHLzAnIYsfS7eDvpwedtN7UZnmo/srjqJdMDTnCXrvGjHEr7252l6Ipuygr6C+WLPMQU9rrfvIwyN\n7t6vCh04Uqaszzc5CY9Aglhmwt/2Y5fx9JkGZumJynrdGXP33p2621iPJ4AevXZ3fdpNsCsmXnzc\n03cELWhMybwOw1YYoFbfYaz0s7PGleQIeLnk/884jAZTBzjHWSoLCwehSZqGTEAap+F/qiwHr9if\nuKfdQfIf1sOFlHlFnmEytGa24c0rloKQYqZPkuEVY7dS+SDs3W/Bcfs8x0goY2jaXFj4ZMP5UuTc\nyYDHI66HFcvlFknDksj2QlDgRfqZvhK4nKn/ov1YLKpHRhjo71lyHjJm2VbSQ+0OKQv8nqczLIpC\n2mynrP+VJILPijymLq5vCPGo6QllgLdqvuNKBIsJJrlMhIMyMmnRNJvVS+sTiwwsxinybxQicOf4\n34R6e7oY72ItEWWzrwJMtmMMcQrNBoRVgZsDnDu3B/iLN9B445+Ia/2xI8tg4h4bWVtfUrPF/GHF\nCCMcBaai/7iqersKU25P9YqCrW5gzK4yd6hHRVmP/GReTSC8etOcS/dQ+iH7YAw6g+VqwGCE9NNq\nrDHzSFNHzcuTFPuPTnjdDyBuk8tgZ2P8L+upWmAB8WRT08N0FYWxRVHTgdWwIb++kpR4oah3SMVh\ncMdDNeDMRXWOPYx+eoBFG4TdDky/+Rpt3Y3t+kXs5rBtuM3mN6lO/N62N0YIWBy9PPROt6ABLhjn\nkTSPxHFYPlq+2tW7Yq6PpB3gOJgIpw6Jd2FVY/nnHFVGLeti1SuPxoqA/zB+RqAZ1ugF1/HuD/no\nlOzP6btVSLptufMfKGXQlqJurAbPNswzU1SgOzKKgJWsBc8A1dZhUmmODZr7QJWHHjXRe7yJioTB\nSe+1t1P79UExlkY2Av53wBpm/Qf4fP4wQc1SW3DW0IMbQtjt9uv9/X9fGV6/G4GCcNq3idyucymc\n5DsqZ30iU7nUPo5TDk2xTfYTo5J6KDFbWg68PBTUjc9YU+xUqFwxcpfCVXhHxosuzfUSnP6d8DrK\n3sQNP4khBnas9LtuKIEewVH1iv2IiKUdT79XbsL/vFcNBq0+Sqvvg8Mk/IozOebCZTqLA+pRh8j1\nPO0dg1EYBx38k9kKMWWaaucDeaXpyGKEurCt+rNNj6O3iZ4CRZX9o1/noytgel7upuLBzZqGwGps\n73AtMGLpnD77WEcHmk7vCb/9ZIQ/1JqILIS7tWQrpz13TnS0vYnHyN54RndRSVrH3tV5/OmRT8Vr\n86wb6pLSlRI3+LytODQtXr5Pjm9zRxy6ohZ3KULiJ++p02B77O1XtFtNs3jRNxHwmT1DpOf+e3YF\n7zwucJ1nuZyIc7dAzGodikj09oxWDfGZLpGvUv8slbHALDP09Q1sZYzbZb1WMxARlYmMMbOMv6bp\nqXEGb6OxN9Z+GzBYi3Txjse2FDv2HMAimBoCXDRXlk+yVpwUiCn5LTOOrLgekPXApsjOz7wN1iAF\nuPCOno030qg47WpIfuuAkwTBNanyjM9t9kGvHBUbYvNGJkbeRm8WiEhVGVnfSDbFg1e8sBlL0Lu3\naMpK5PBpegs+vk8K2IkOGYvR5Aow1ZeA5q1rcMpEdIMR3mvYVfmtKdsviHZ0E9byAXZKlxdLV500\nemm5GQ0btI6qUDeat0/afCtAal+KQNfrpHPt/BKEshvW65onuKtkGdVhgINJh2YjRt6jDRwNZQy0\nt2/zk33lRdcQQQ8LBhOyDN4ulcQycDTY8OirqCVBDoNZ+9yHallJ2KKSJ36/U8NF0hahr7y5qtSM\nA/CkX1Sq/WW9AUQghL6/flbo6xyPz6Bk2CrrAkVR1m8WMsMYMTJzDzfobDkq/uOLuUcYSHS8GNM6\nIdJqSHQHu56KgPK0O/DnWxNXJkyeBTmFrEEAeToW3FoLlXfLwtvWmC06ciSqRnbm4gQimtKLA186\n3MaT356eSiGNv5qN+OQ8jv9hOKg17JmP9W2QWQxotOSiN3CpHK96mnBgBkpBqeksHSwkZ0Ym0Qlr\nWv4lGLAVFUI/rN/rGeRGjup/z4iwy542LcR9kEYZOCDY7F+46FcaQVcgrEM3BbZM1pZ7vMLZbBAB\nNIp2+fxvCHdPb2MYCkQJEi/lNoxzKSXQtUF/XliVdGDd/gJwms8Xkb0HYbyyJaWmfe/7DA0SWmmI\n5fHk2ePB/BvngIkwjKN6KMMHlozyCxLMBeUviR479mhHY3qV5gjKRE18cK3t6WtqD1l/r8fKmf2w\nmzxkLYc44rJqGUZqz2o47L0QXKUl4KpIGJ/PgoMPvA1kf0RdRqeBduHyjVFsKxHnVpN5TcWOPpEw\nsnzFSf8uh2B3xmR8tN3FtBy76kvQdN+6jOgMRDMtqYF7sGVg9vWPkeNNYzWk3rNC82l1Zzzx1ztQ\nJPblX9T7Eopb8dQclIpQtlVlyIvKm//abXhCgGVhBiQO4HX0Mien3FDZ990Z+ACbN0ccUL4Q1a8i\nxBtv+PWgZCeEA7utiTzOAPee3+34gAm6naicmXjXFCr2YvuZ5nD8J4hTINSaASRF8YaSrvYywwTy\n0iiBeMiahZnjX6Ra2SrDx7v34srF6/hoMCA8DyH1mFmdEUrCRgE4t6Hi1YVAINEphDeCGVVAVZ2N\nPykajTZihGf35IIRqjlR4U376Y0tBRNDAGp0Q6kPtvejvKlrZKN4G7r1lJAyP09bE7KDPRmbs/fs\nNyVC8RFydYUivRE6veitQTKDOMDm6JNj7qAaWp77cujnVGbn64Bd4xm7WZeKIKIm4aYSnUwJl5hL\nD+LcQnpAu6AAfc5YHgN5y5HYw1yEUhRnMl/L5Bjz/LberH5kV5CAMGc35Dn5CCsgW62MH0Klur3t\nqvDQ3OvhGmDL4Y2xOoW4kBC/Rjs4GjGtRYrXT4e2tlpknnpaKlAKV1YKawJ0W5ajt598+Y5C55Xi\nFrK/U1x+yGGVlKNimaW2agOl9VuEcCh6glCflnLynYngd4XXKA2JKIVNlRW01Xgdtfi10B5ipXZS\nZVEoJ/hncNBjVQcHqAeGhnptqMCqfg7CcyShKr61kfcsAc5VLbEphtId0rpP5V0qOrtNJAKxoEaN\n0ppVGEAI9TOF73jTYNy5e79+kav+WYHx6AgbaL192QJxAqG6252UlyKD+TN3wBZoObX12Adr3vX0\nj8zGgO0he4Dx9Cc1zYRKQf+J+yMSyWdmVEp+MKCbgyK6LEYoIp17fcKhZNmAg+ZS36UfkshviFTK\n+POKT3AT1fvcHL8OYw/QdRPMaLWPsOWPzcq4yVgeUMUgiaSnDUCDUB2yCO1vrkhPMwKhlhn0LwuZ\nwfM3h+czZAHuZRighzjAJUXwkEsN1Pgt9F4Ga9v4FpSBRve37ucHHuEn5jrX7b93oBywaPyG4za/\nsKerqFfobeFqou+l5uZHAWu9PB7G/36xCuN+gmjhdwI/5TjKnJGVa/Y4mrJHsK6xloq5ez4C0iUi\nDmzKDqJoGdws5uiPusdI5CZWqgii+tJ8UWOIJHe9wGCyFsM8DcbrnffJ/viThaJpSCiPR0zFv6En\nui3LW356UdHeYjk/6ZLmILb75WrZlIL0kBuk74qo9+iFxkDdId6A9FExjyh5C0dP0BDu7B53lknF\nihlFcZBGxzYFi0FbzdfCEM2K3tcVp8899GthOJgGu1N/qgTjg7ZC/hyW+NBVWOcsA/YI7H3p0zgC\nXErEvovgf4PesV8V5YrcnbNOLDkF2F+Hf+2W32/JFOuPVvcNZ0gw633lx0jeGk6zfpU4S+UqC6Z5\nlv2D7EYFebe8OBLKCmRA2kE6MXcrMBmFn7B6+0q/HxIcCLbSLBhEYooIbwK4lBvBHwt3ZNID9S46\nrlt9jHIYAJJLaDmqvniX1DClRh9zTvsHpSGG3mOKpwD1pbAsE/8AMN715F7VM9sLDloqgirm14c6\n6KaiDL34h1u3UPQcAYa/iUBBFD/omsncOZqodQoWJn1t78iJvCBlDiE/KRD+shi7MBiWR2qJzUV6\nvszTfqHmcpXqEKqJvAXBiNAYngR+GmMYIbTgB1YEwXQCZD0LToUOiwp5anTrAhDmS/ZUfyPA3O6e\nTeDJzu+g6CkNKGT6qnI9zSYRkn59rzdWimTbmd31+E9sE3oldZ7yukJKGm9HcrjmEn5iIHN2ksfy\n/bkuKAzgYebyoHDYTZZ4VZqRJkKaocRo0fbIi3zd65Gp3s5K7YmVN1cvTb30eNMvckNTr5tRJMXB\nQ1bruBwB0ntnrr5x/IGxj/XRZ7/oSwIkJdyNApk2te/birUbUR6UnGc4y4ttNTCDEuqggW3Cbfx9\n9tQdOjLwh43tPYA8H/M++ZwOf3HhfJjQQKysv0lOWY4S7ARJ3OrEoqKqyXAWdXniajcpDVbynsa8\nNsjwPf5WL5HPa+3iczXjARgydFiLFoxXOvEHjL7tJu91ngVLoHuKCc1sVCOdlfYThGi23uWH7vJ0\nYOLKmVWobVhcf5VpB8+yu1Am0dOHkBdHCr3rrgZdInlMue8oop0PLaPmJVMowyGjsverdCv6z6UE\nOqIUWtaPVpiBpHHD9Yw6XYxDCAiGibe+Gl6m/28e8Ym+QSzsogPaSQBf0SelV7KrqzHbId7aPJEq\ngRCDJzmPbD1Avv3QgG3iKsbrPI2KxWvxVP0dALSOEGlaW1luiCFhyVQZMjhvB2qkJbqeiTDhS7h7\n3EUa4i+fV/sjeR56deRJoqqk3M2q5B2q8M8jiW3dXI4Bxnmf1g7J8vrQ+iXPrLgC2JkSbeRZ/eFF\nCnM7HWHG7fLPw+dEcoxCvhyjiLG4nrEVGBWGXhUmx7lCGjGBUwRSXgUKYTNM+tVB/GGQSLqO1BXa\nqonr6lyJ9aQG7gc66GT96wZBQGclYbR4btuwY1dBNSMp+euELOd1xEiLYTm8oFfu+4GyZNtxGaNH\nQPGRCGjL34JDEnum18YLX1sqaLAaI4Vd3oohNrCZpQUGEPboSGGh1OhTL0TcjUaI1kzx5pnFFlQW\num+7966tMQzGB0widT/dnC203OehdRUxF3mVKO3vyZQS/QQL0LhvmTW6F2yZftZZwGor4BAllquC\n557VhXbkeLpl/vbtt0chG5IT/u9C7bdHihJPK9UT4R88nM21DYUK11SdT+pomG5JH2mJc3Io3YzG\nZcfbv8KIZsybNllnnP/EBy1sp1maLL9qN6kF8hDFHfB/Jr2elZJJ01JYHPOQCHNy+UA2Gl5QwPr8\nc9SHuUtr8rz+WAOCvege7emLx4Jt5ytymFbSfrvoRM+ZUxFmqe62SfHTEzg7ml6FYKGwZFzHxAVP\nqClbYQVma1hfPRcOQ2EPNB+IDQvSMtnMgfNCRvCXzR+Q+46QsNEdqQLttQrMkLWYUWQ/PxH/abKm\naMyBEKhbB0uA37pA7d7nNWme6VWCZ7Phlw4sTGZ9usfSAF2iks+dhfHFUczhnkRr5kLs2nN//1Hm\nujL9S2Xh+YR8mZbK/X/DNNxk5vMeM2BEVm1PZoxk2SRTp2R/vYNolwEbwelAj06fIHNm5MpYsL1E\n7ncTpnND/46Rp+9dC46VWjFitJhw6xYQBnAnAUgK5XKJoMd1ULWbXo9Obn6RduRPzN0a789FLdcx\n4OyYK3f61tQF3inIYC1r1HHOGDrI2xRZVZNZNDzADjAcygRu1Sw4WL8VBi/vYsKqVoNERt38KOEl\n9NyG3q3+6TPPg72wauvsj9vXnxr/ERZ9FdkR/nhOatd9PJBBtPaEAMYvPNJ01ByAr1H9v7EusrNo\ndtHZtpRoWhrKsTvw8ChWSzj4E7jptyFhnLEslaw4KGbKc0rKYK/kNZB6DrrEl2aCV7QHsdkX9Bj1\nPKcOWqa37YQlp97WsyhXrowmbd3CistDmVeRnzDx4swr7Q6boEig1BCH+1d5aIEO9ffvu2QbMvti\nAbcrVFpP6sBalPmiLjS15uhWV8KEGw781zQ4mqnoVw3oCKOuwjvvK/9OhNoout6ggrrMMfHFLop/\n7TagcwxVB59eehfgXDHC5RxEwiKlLkX4TdQk3bJgWiNKjaUI0iF5sXdRTcu76owM9bPDeFQ0zvcK\ndUkPtD7AXtk/vFhKjwLRLeB3UTz+YhoVaUH1daPHUMlMEH+eJQESKAxgCeuJAj8GZnyT7+cw0TT7\ncjpaqS0H1C0WUL6EFh9/Re8yGO0a8+1Wp5GoD3ceJ9EingExgibnx1rZ3dLJ8Hmf4F6c97FHtUGj\nWWra/KN5WoCJrdl6TSdm2vPt/3JFImXL3VxVhD1lHg5jk87q0UvPEFJbe56oPyUDYIHorFMXCtkB\nSp0+FG2szkowh6Po7B7p6lTueX4hCfE63q/RjQu0vNkacOGXYHvO/nT/7D6KtFG9OpRZwtuB5emu\nCGXEsehh9FDIFrOpVZN7q6ME4mkpcEBoVM5qdWoVt/3gUeGi7NoO+67+Xub8tmwmHzbP8nOXg3X9\nfNoTD1RXYZyvLZE4fAJJsmUmaxheX5QZ7wY+viDhcuVgAlnxxX0LLauJsgSdLdbbADd1bV5VS5Lr\n7B78FfM0LvFrQA5ay6ZN+k3078VR8KQ77wOOtuiXuls/asxNNLGEZe3j1Oqa8f4PJaCMlo6GC4Fw\nG3ADbVBwDp6yZwFL+jqVJcecF0yGso2WSscQ2vtmwXqV/rt1ntgPMcrqJSBUCsg3n8UAqSqyrJMP\nFl3aW/zxO8e34gRl8Gb+Av7qEDyqQnJbSeqv+bQRtgG85qT9oO8xyqlwpsHqHY98338C2Doe0qWE\nihq/+PAb/4nr9c5kJKMC6aqGRJYAD0fox21bybPmT4ZB2ZffeOrw36ME+hNkiBhNVDEW0j4LFPfC\nYTBRPHdDBONBGboUy+sX0hhLEFqDxD/pZ5nuulAJ1Gnpq5tYOdAVxsaLS4xVsiN6zvxKorSgpp8N\n6MetCHR0J1sVQSDbgLtEnrJ7/7F0wLUSS9jjxyJk3JHSRXyJQkLPrGjNvsgaaZ2+lUq84JavE4TW\n9WVMjvOBSoHbjCPnbFZC8a49DiHvK1W7MjjzSoFWxEqbJf55ZKbmbZgJvRBEMomcR2nX6WZLbKWd\noRt3xjhQXyyiLw7QmCKsylEF4+dhqgHIebhz0y70vdoOeqc0rMJsm2eLHLngRgytaRry7GtPEs5k\nEPzKLb4IzUud4aHQuqMS48KrQWjqCoEMqJC+/cyg0GMCPX8DoZ9NTjThi3KQ0Zm7ccl0zBlw3HJO\n4qeihfn5PUbsuXiimxdpDSOITExdNX2hgIYo6AHvcXqMa/5Srf1HuJLKLN77iqK19L2yGGkfG4cT\nPp+WIn1zd33WLqzGEEGFwucN4QrfZT0Mk0WseahDZbW80vLs1NuEfK2AfMYWc+gVKQjjNjUOEeA9\nEL0nVCajyreQL1X77MQ/Z3f7MKXlMZIKZ9st9Pqja1Wqt63i3HjrSEDh1cr7EQru3+zBo7gAIJNr\n9GzPVfhPzNmlRJyLd29w63i3/hPgjFiRB2yI01ijIow79xNLQev0WpGBJKnLZIkIGQdHfPjySCPp\nLNOOluCTX9RiV7C2yt65IAYwEE3Rmu0QeEMTSJr8M6cwP8mkQHG7TC26sVsjzhaVJ31m5gOTplWS\neyBIdXbYZgIWt1obgM5qbXkjN05FCv5jjW3R13d0x6cAu0lu1EIU8Otrn3d7K7abyyOqc6fFOCWC\nFarr8sTVDJSYHojX+adnx0hjaUrcMBbGBTKORHKWrTFaDAPouT+Wyu7oCi+Hh5VqU+mZe/qB7Kxj\nlgqWgjbbdcxQ8ViVvicBe5q/Ovu9OX/S/BryWWNVpNVVPrNNP7Ud6AruH/fVFpmbyTL55m/dllDf\nEsoSG4IV4Iq8y+AEYbXrUUN6PUiM0B/GGx4FWgf8LDcPntO8P7KQcTV6F6MLG/Me/gsMqJg9cTka\nGebbtdVE3YGk4XTN1vGthwkfPh1Bj6hbaXmcvd1KVqWndHf7ySukioyKHVdLKfaleKZQjgYrFC3+\nk9M5UF8iyFNdxOHcn2vCBKWVc1I2pd6ZMR0eYCpW3Bl+UUc551rT4YjvRrmtgQDJa6pyO3YU8u8d\n4WmETh5BlAaqkEDHrICLy8G5Yep8lSuyYflQRyJlV2xhgVqOUJTgtQij9t35ogixJNN+XdeAvnZN\nYp/xoGGboGv2dQbh1AB6/hISTyoeoxiUiY8Nc+wJ43jxi7Zof2SnRGiGZO+DEU5xvGRXl2Ws30bG\nF6+Am3Fvx6BC8+k+3uh9EM9dWQfSBMnHdb3idchTHaECxrWgQ6YbLbIwFuEO5ZH79Vq0tBc5et4I\nGX9TavQlby9lMDPpsiWQoFMzvCBc3iZ+lZJau9LWocl+f/9BM5rtOdI0HmACQiXtU54IhGtfHCn8\navgoEX6YeYOtrL13mkeqZNMTwp9lDG2/ChB8jfBoeD2759DTTH3o0cL9Sf5OTcuPA3V6/lQNTJTO\nF17UEFBwpnizy/n8XdzKpjU+gDcJsRcp/WGYombRXjSxfOEcYeRGaNBkgmqcV6xbHB9voCeSyNZQ\n3NYbjLsDuHnQ5i0saD+Yo1ryDiGFJoetyr6nXA1l8onA/40QGdAL14rfQV6HmaKHRVYCsF5tQoxH\nG29OdGuI0EVOUfIt+T29zFbaLde+rv8aqiogYctNjvILupJVMCrUy3eB1cYL1r4cE8vDpaIrVw3S\nlXsgoXh2LK7PC3REaCHJDLS9oq0Nxu43MiAuaSZ6DZp0U5rHH4DcUGKGK4LxiKC1fKZB2YXk8CXg\n4JmMulWsBZyVc1Hs2STEooc5NEZRynFPyNx6sPwUKpBlwvxgPIz8ashYeArr7pgtazIlQCV8RsbB\no3WNCfSTrHDscYbNhNGSN15ujTXyZIxf0xmw1NxhW4VE0LbVbU4Q9muynFksh/f+O3sz79eTs2Wk\ncj94qweFDzzDSKfo+fYFxr35zCg/FefHqD9FPNrkArUiafPmFRWLGkm6SWycHTHW2dmOUxqBLDnS\nKOU4i53LrnwJtNlnnNbR9vCnTV3HZkrvTaGD1GJiRzC/es+XDUFHEb7YDM8JUKlRbU33uV+CnXcq\nE5Afnqcfch6xTfp4W24eBeAxeKZEXYdjLxisOYvQ03BbLnt/ao+HyqjiaVos86B9Z8guiTv7Y7vm\nU0QBEPyFWR0ehm2yrjUy2ZOjpN+dN8ptlOpi+8jkgisg6gYT2U8e1S2pPCrAtZwj51rEayRg6gp+\nfZ1+HBHDLTW++YMQshPGSEXZMzn40VO97CNjgrh8ovSvROZzPoujNet0XF4Xl+0pRfUzN08GGTzc\nCDNZWKvs7QQNI0+Jzy3TOqD5OoFWQbRf3ETptGJEjsxTG4xPlNBT393qN4TMLuz9Lu1DCUKN/auR\nkZ2FO6X5bGfE7IJXmo05JK9M+NQ17wS6A/rJrHFTFQG3i3U1xyCqWFjTpJJamaXa8Ap24WYvz6dc\n098Zr90dPEFqCDwe6hxyVvY5RfffPzDqQb5DMiiFBA0+l1lXQ6msvQO0/PjN67FDr+p4RuZxhV6p\nTCZm4lrQ47Q5/Asnv2QX7XT23yACOPXvT5VII5iJx66cZDW8PqcokaLa+pAtVqbgZDPxZD1C4NXw\nAoObbkqulKoJobs7EjZSIpKQqr5GCZ3QjgDDwPruhevdnzONX5uBvI19+JYqusyuR333F376uyvK\nn6F+d/zNdvSAV3gIz9JaPPEhjbKgsUOFhdyDoaXdydwVHrAB1SkIhNzpfNl62QU0h9m1rX0tPNdt\nUnlnjJPMTjVt7hS8vJhfgtk+39dFB37FS3rVDWUD/97MlcR8z6MEGzbLsGSRtQgzQXSzXL4ruX2E\n7F8oaVsrywznJGiEc+2zzA1QekJQuy5dxS2hvHftZoajaCqWhhrACvQAE5HTIr8etonzlt70MhBX\nR4L2Kdszs+cuKe7YCn41vp6yn+jkXCpOzLOekgT30vVB2cScqwhXUnoA4eD5oeMK/VvSG8OomIto\nmaCJiv0wLgJ7kJsprJEeL16mqTkMwmvay2FtiWlIWbKIs9hgg5RqP5ftklAYWiA/4wg9CMMoH2hp\nuZ1nni2cWWGynf2ne0XC1qDqennT2JyNAQtk9Jw0eXHvjVLarN4YgyFvFTr0C5rV9472azo3UE8A\ndbhgNUf94/74joOWhz9K0BX6hu6u9am3nZfHjzT8iT3pq3MtSlLDx/+vqR09j1sBXhBoyiyASoio\nhAQyBIlf137OHYUONIvyzXe1M6PgVDfdvFr6g7VVEpVZDeSgkN1SXdnbZwYBVLOYe3JTzPfiCNmw\nPL+c0DJ8OwN91pieUcftyhX8/4nraUP0jfbmoqYneAn2aizdgj+uYZDayM1DDIqG7HkWgfoTyOux\nFto6L/LvFuzFDe+ipcLHg/txvv/oK16fIF31ETqIDIKRU1LBbQAbPUwEZxC+TEnpkcr6oVT0hwHN\nJuTLW8ZHgsVNC5YQaLbTIU0uVZ2AYfXpD5jXx2DHxpFmqpwAA10PEvjjBwEXurS92XYW6Vlh3vag\nh8071PI4Y8h0dlx5dPI/VyJA5MsaecCPh9Wc3Mu9ju7CmJzmdnouyGW49lVc7T+BFgn8vY84W4Jy\n0EOJqxtbldn/b0RL9qNfkmndlxOOYUGpkoTDXOeKNtd7HyleHoQUnqsrJltt7n1TUWyBkUSvmr2e\nhIco9V0pfGLnQmBrcS8ESf7JoDfid3dd9xhfTYd7x95o4BpLRW9VbAnUv/qzO2Ql4PsXD4elhlqQ\nIX/zvEAslyulqRlaIojF5lfyR5gs5T3XDgy9J3wvtzGMB2e/OdhArVKDlyiGKVBCwObJBltJLdrm\nqQtoqvfdCn+V9EPh8P1tILiKhp/pxpNcMLi4F54Ss1mMT6eOjdsUUk2NgxCMXJ9DCe3Vzm8uyZL7\ngcN4jfAg3E1rqk3m/i6KHng7yyFwHWIWhDG1pdVdgHnmaVWwnYivlzpB/S7eNw4unSB3dd2BlnzG\nRb5PE2fCqQmV6WZPnzyEbQbON8IXydg2GwqhVl7d+KhVvB9u2DtRSUwccaSTmzQitYkii0ktito/\nOZn5ZAWREOagH6xk2jSJtB+raBOlZD/StDmobLXWmpcaSlaEkDEyTAMr+crVbeg3vAGSoSOK9IbG\nhEMMVUnbYc1PtZV+vY21I6ppYt5T/zHwORuaK4UahSEs+tc11E84gYKfibx4zaxbrR6PIWoRhFpx\nfygJGI82fQqpK8rIAfb84Z6eXjnfx8vNe3ePHTI9pkZghZ1vx44M7VPJerWd7U5zd1C45avIo7bJ\n7u6tesU5+cplrvIG+231DuhICa8DH9UF72c/JWk3FiHDqhpde5ScS3IcWx1hhrKBvi5FXoH10veQ\nlHicTS5ZPF03XuljrC096UTByid0LNhm3MEYNMhJHDAg//PphATDzK9kPRVEqWJNnUXtQxCtfaGv\nDDm9ZwguZj9gqtu4FYLLYUIYBSERRP0P3uA20WOHJw+chMy+nL/5NJ5IbO3bDpRrULtw20tfYeXd\nMEZRrVydMWKNjYU3WDHTREgJjguTG/o0uckR8jUjDqND8/aBClo3a38CpFmPcWL6ws4xn7mPX0eQ\ndm04/XpCC8K8rCxBby0gOx53dNfuWePoTZANSnjGGiUI5BxmFdAWSo6va4tcRBNNZMPM97o0kVhv\nEPnfc3/sGE1x3k8/zSHbDc8HaQOXTo9W3rmPsM1cLrN9t27Iox3uo8H8MKqn1YcA0ilt5LAjrSV+\ntUKxL0hO5/r4sVSAigD8X48thLABHsoJPxsvEF8LqbeF6ar28+m3HKCwEkXmuDsb2D9EH9UPETzk\noU7Zlu+cBilAsNow3MhIVGRoQMJ90wjs5tMHHN0coijGoZTA0lcU/s6NGNC2TOBj1w5bSDX8FKiM\nS07TxyW3rw6YTaoFIbD66Rq/NSP/31Z3DELdKtPR9xDQKSDKf8jWDeUMJczhi6nWPBQbN7UQtmrO\nLkeWuAHdvStParHRMDHlyl76hJKPEZy48fg9N9UdnO+Pd1Ald+lem+PCsHHf+OqbXStJyJ7sNQPS\njKJNQgifRKxMJxi0ijJ0y77hsBxInqwKBywtcfVKlXs5gwB5+HzKqctr1bzPf+oUVROtD4s7C8n8\nPRAVBiiazwsrGoCKpXRTQdmcPIWk5o/ljibexkeIJdZGOflQLAG79TkQP4VR589A9TEHqrbDA8Ow\niEvue5OjEfXk8v35rM5k036b2nWDRQjwgH6Ww3B4Lm4ynLAYQGTB96U9XWkAnWLiLp5m8zvFZdDi\nE+meA0JkE6eMo9xpSCwtthR9qC/ZN+oxyhOIxOtsuOB79uBllrVRyxq5F8q9Jv+a7IKcvLMc3+Sk\nZmbgOAgVLYMQnsj7C+GgRoA181qNGBLLADnDESGgJ/3VlMRVMiOvVQ+AWmMuns4aRjO7TJj0T4gj\nOtQxN5mRSOWygf4wDNFbjjzdk9Wrb+YtBxxP67a1DBY73E4f8rq4GAGOc+uA+vYPxN2cpzQMxn67\ntST3yTFSN0HU+TLzADeDsR9fli+VCAO40pjEmfvnmz8uX4ieAh1/bmsrpCB4hddDi4K7Pm6hCPVZ\nlNMu2yUJ2Gv7pSfim/c6uDmTOvuyKRHsEtHBss9V0SHiF7zsCw9jC1Gw1Z3hAWIEE9MWxlQFYCc/\nOJl2e+2sT7p7D6B+NL5udUm7nX8gB74q1PUFWPsGYpD2pu3lCBVsQcSipoVTozPzXTMu9GhiBbtD\nKMVzVgZKLQb85zYLEfk9esGkaaAa/IMlXBYyZ3KgxHNEQVVYLd/28z6Bgq4z92uZ+nUjAQQNhNbd\nihUSeLisI8jS+p0o5SqzysX2BhJTA73Dl1qC80tYYxi+Dgt6Ix5T5JgkBeZt5XKSBj+tWhDWKCDx\n6uUFw/ci6OktwfqL5KZVOMkEwPLWW0W3S4EwFRv/nqulclXjxaiEmI1qy2g3i4xu4ozAzfvuY4PX\n4TNsbHRGXKHnbUq3OX7WWl0FoO0CnTw7uzXYj3goIj+2ppauZVSQt3oGFMco07p5c7AG791rM2wx\n+pZL5s5qBaL9pScdRgmtmuslKlqootc7gQJ5OxR6mvoMhOnphhgyojQnOr+SJEtDMMD5rHlXoSgW\nUJGwt8q/XT7s+tAVwEfFZwcio0IPbQNDOOsdHChnWoWh82tTu2wWSgR7Kg3fahsm6lpYDnkid7j5\nkTGihYKRKRkvpg2Ws63TmPYjpdul3WC+b4ZOhk6v3C1IdjpjOJ5UG4l9tMkYVfoW7y024BquSO5/\nMPPdTM2nWYdjbgO42K4Zxv4zLj2NSkWZm3pkgJP8LOnt+bV9C5AceuFe2YEcYfHP2NnzCbPkW3DX\n7OB2UfViC3Mm7S4KKuGfnRC4dEAlRwcrCwYneuiP6uS0A1MNUvCnPn8WEs3qpVOweX2aJkYS5ur/\nR1bloUhVQUshGkVfjwbVCpNKA1Z9uzEmBMAoQ7XvphL37Gw4A6IF6IP0hE2sLueqpM8yW6YP/n2m\nThOWH112SQ7B6Cl1xkrSYRy2fRhCPLiOb/AIOrOXBfO7Htq4hRh8mLjn9tsBdxQiCauhjPtftHqA\nbnkLa4np5WOkVect6L/DVTK0V5YtCK3SVmMRX5+n/iH5KjTBdbJDG5zE1+cZIZUf1jHOQT1zGeYb\nPcdKviHtuX/dxA/zR96YYgE+6kvpWexwOMkvDnMeZrFWV3YA2Q4yzl1IMz7mxXAYg+xr1XhyQAHh\nbvAoPX1ZX/f/hT0d5tm7H0+hzJGpOMNmOb9uWoxbURr1oTe7Aub9LGHM7MeHGjRy0eeNA4l9a3ZY\nWaNVI8NHq1/gTMRD2P454oSx+FPyBOny6Sx3+WAXKWV4raTpFUBs/OkARVapcvZtqOP0JQyWm7PT\nCLXQurpYYnK+M5sJwh9q8N5Ymi5B7RVWKXSw3bTt5UpCMFF8w3wqLBnB20ai9FBNCmCWLZmqK1BW\nOT5Z9SWGsFad4wD/ykn7EphW/XOoLWY4gWTRReb8kUiyK4uYq3GdyedGWQMQubbwsw4Yf9XLQOCA\nveyvPmR0nXWIDyie/P517DyAPPR3QSsQaXWL6OwedlZe9/pJZvpyVuCkMvohDO0OiZBnKhw8c6g7\nQDxVJpr+PzuscPWWNvWsRleF9CtP6o3lVCPYofb5eni3/gew6UuMOOPdq96vjfol+ipMOitig/EK\n5KSSJc4ignVV1rpPdS8jKt1uRzdiIG04lIgKV/iTrGxulwFTYWn0YXZ70j00M7akJBpgtHYtEwg7\ntuFwF87SDt98jOPD/WHKwoeleWTKwDzN8dUG6rIIjciM7ttKAupuKB8zcngy2+VEd8SJsoOuiVXv\nI1jEkJzWfyF9h+BgpXXoFGfSUjm4PqBwqBTsya3TbfnxMusFwVAmhcgkODyoaBE2aPevUBLTPEyg\noXiZdFn96TTFBTSKxfbvfoWmBfJLQG+IUMH6XUArLaDvPsOewnpCrh+xOPs2VUJvRJlbOoQA8hhc\nBYFw9C/vaE8JPImPCF8Mcml3atuzrH8J+M55leKZ+Ahyde17lDJYmLaTtLVQgqkyaZyHgYJabqrL\nfvxMvqW5F5ysEsk4uLDBFDd26mKkWfaYPU1SQDCVe5TX6ZCrMoOF7QT3xo/dGRKOrgxhF80rEBSA\npbHEX09kRVpK/s7dJePfIDBOH4wslJSyr+cpQWARs1LDsRdJqfBnbx5MEQ4E2qk0F1V6P0Uu3APK\nPs8KsBhcdUXgUqbGbsEQmLHNmMsW9PItMgYMqBKVjCWjmnu7XFM+2WPGuA22GFgbq/HHjTvb4+a/\nhNHFvP4EGDou4Pq063a7EtIFFh0VzxeE8It65f8GizD4Z/YaE5NBdVql7NOdDECr3l5vqCI3HnNC\nrd00HANISl5oyA2MuYTQR+GQaXrKUzZ0cDbvQZ7P2epot1a+MCmRzUKtgRQlP3GEAOvl/z6jyNGl\n0i9gClFCTubmketbUNA8oLzc5tOCpMdeyfZX7wq1Mj84m63g4WECc1S400lGBZhiUvaRIgsEnvQo\n0/oWeneHemIMitJgnp4Mf5PvMfKmyud8ED+o05VrGt2n1P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{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:xsdbm:3.0\n// IP Revision: 0\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_a493_xsdbm_0 (\n  update,\n  capture,\n  reset,\n  runtest,\n  tck,\n  tms,\n  tdi,\n  sel,\n  shift,\n  drck,\n  tdo,\n  bscanid_en,\n  clk\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan UPDATE\" *)\ninput wire update;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan CAPTURE\" *)\ninput wire capture;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RESET\" *)\ninput wire reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RUNTEST\" *)\ninput wire runtest;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TCK\" *)\ninput wire tck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TMS\" *)\ninput wire tms;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDI\" *)\ninput wire tdi;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SEL\" *)\ninput wire sel;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SHIFT\" *)\ninput wire shift;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan DRCK\" *)\ninput wire drck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDO\" *)\noutput wire tdo;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan BSCANID_EN\" *)\ninput wire bscanid_en;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME signal_clock, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_a493_clk, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 signal_clock CLK\" *)\ninput wire clk;\n\n  xsdbm_v3_0_0_xsdbm #(\n    .C_FIFO_STYLE(\"SUBCORE\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_MAJOR_VERSION(14),\n    .C_MINOR_VERSION(1),\n    .C_BUILD_REVISION(0),\n    .C_CORE_MAJOR_VER(1),\n    .C_CORE_MINOR_VER(0),\n    .C_CORE_MINOR_ALPHA_VER(97),\n    .C_XSDB_NUM_SLAVES(0),\n    .C_XSDB_PERIOD_INT(10),\n    .C_XSDB_PERIOD_FRC(0),\n    .C_USE_BUFR(0),\n    .C_DCLK_HAS_RESET(0),\n    .C_EN_INT_SIM(1),\n    .C_CORE_TYPE(1),\n    .C_USER_SCAN_CHAIN(1),\n    .C_CLKFBOUT_MULT_F(4.000),\n    .C_DIVCLK_DIVIDE(1),\n    .C_CLKOUT0_DIVIDE_F(12.000),\n    .C_CLK_INPUT_FREQ_HZ(300000000),\n    .C_ENABLE_CLK_DIVIDER(0),\n    .C_USE_EXT_BSCAN(1),\n    .C_USE_STARTUP_CLK(0),\n    .C_EN_BSCANID_VEC(0),\n    .C_TWO_PRIM_MODE(0),\n    .C_USER_SCAN_CHAIN1(1),\n    .C_BSCANID(76546592),\n    .C_BSCAN_MODE(0),\n    .C_BSCAN_MODE_WITH_CORE(0),\n    .C_NUM_BSCAN_MASTER_PORTS(0)\n  ) inst (\n    .sl_iport0_o(),\n    .sl_iport1_o(),\n    .sl_iport2_o(),\n    .sl_iport3_o(),\n    .sl_iport4_o(),\n    .sl_iport5_o(),\n    .sl_iport6_o(),\n    .sl_iport7_o(),\n    .sl_iport8_o(),\n    .sl_iport9_o(),\n    .sl_iport10_o(),\n    .sl_iport11_o(),\n    .sl_iport12_o(),\n    .sl_iport13_o(),\n    .sl_iport14_o(),\n    .sl_iport15_o(),\n    .sl_iport16_o(),\n    .sl_iport17_o(),\n    .sl_iport18_o(),\n    .sl_iport19_o(),\n    .sl_iport20_o(),\n    .sl_iport21_o(),\n    .sl_iport22_o(),\n    .sl_iport23_o(),\n    .sl_iport24_o(),\n    .sl_iport25_o(),\n    .sl_iport26_o(),\n    .sl_iport27_o(),\n    .sl_iport28_o(),\n    .sl_iport29_o(),\n    .sl_iport30_o(),\n    .sl_iport31_o(),\n    .sl_iport32_o(),\n    .sl_iport33_o(),\n    .sl_iport34_o(),\n    .sl_iport35_o(),\n    .sl_iport36_o(),\n    .sl_iport37_o(),\n    .sl_iport38_o(),\n    .sl_iport39_o(),\n    .sl_iport40_o(),\n    .sl_iport41_o(),\n    .sl_iport42_o(),\n    .sl_iport43_o(),\n    .sl_iport44_o(),\n    .sl_iport45_o(),\n    .sl_iport46_o(),\n    .sl_iport47_o(),\n    .sl_iport48_o(),\n    .sl_iport49_o(),\n    .sl_iport50_o(),\n    .sl_iport51_o(),\n    .sl_iport52_o(),\n    .sl_iport53_o(),\n    .sl_iport54_o(),\n    .sl_iport55_o(),\n    .sl_iport56_o(),\n    .sl_iport57_o(),\n    .sl_iport58_o(),\n    .sl_iport59_o(),\n    .sl_iport60_o(),\n    .sl_iport61_o(),\n    .sl_iport62_o(),\n    .sl_iport63_o(),\n    .sl_iport64_o(),\n    .sl_iport65_o(),\n    .sl_iport66_o(),\n    .sl_iport67_o(),\n    .sl_iport68_o(),\n    .sl_iport69_o(),\n    .sl_iport70_o(),\n    .sl_iport71_o(),\n    .sl_iport72_o(),\n    .sl_iport73_o(),\n    .sl_iport74_o(),\n    .sl_iport75_o(),\n    .sl_iport76_o(),\n    .sl_iport77_o(),\n    .sl_iport78_o(),\n    .sl_iport79_o(),\n    .sl_iport80_o(),\n    .sl_iport81_o(),\n    .sl_iport82_o(),\n    .sl_iport83_o(),\n    .sl_iport84_o(),\n    .sl_iport85_o(),\n    .sl_iport86_o(),\n    .sl_iport87_o(),\n    .sl_iport88_o(),\n    .sl_iport89_o(),\n    .sl_iport90_o(),\n    .sl_iport91_o(),\n    .sl_iport92_o(),\n    .sl_iport93_o(),\n    .sl_iport94_o(),\n    .sl_iport95_o(),\n    .sl_iport96_o(),\n    .sl_iport97_o(),\n    .sl_iport98_o(),\n    .sl_iport99_o(),\n    .sl_iport100_o(),\n    .sl_iport101_o(),\n    .sl_iport102_o(),\n    .sl_iport103_o(),\n    .sl_iport104_o(),\n    .sl_iport105_o(),\n    .sl_iport106_o(),\n    .sl_iport107_o(),\n    .sl_iport108_o(),\n    .sl_iport109_o(),\n    .sl_iport110_o(),\n    .sl_iport111_o(),\n    .sl_iport112_o(),\n    .sl_iport113_o(),\n    .sl_iport114_o(),\n    .sl_iport115_o(),\n    .sl_iport116_o(),\n    .sl_iport117_o(),\n    .sl_iport118_o(),\n    .sl_iport119_o(),\n    .sl_iport120_o(),\n    .sl_iport121_o(),\n    .sl_iport122_o(),\n    .sl_iport123_o(),\n    .sl_iport124_o(),\n    .sl_iport125_o(),\n    .sl_iport126_o(),\n    .sl_iport127_o(),\n    .sl_iport128_o(),\n    .sl_iport129_o(),\n    .sl_iport130_o(),\n    .sl_iport131_o(),\n    .sl_iport132_o(),\n    .sl_iport133_o(),\n    .sl_iport134_o(),\n    .sl_iport135_o(),\n    .sl_iport136_o(),\n    .sl_iport137_o(),\n    .sl_iport138_o(),\n    .sl_iport139_o(),\n    .sl_iport140_o(),\n    .sl_iport141_o(),\n    .sl_iport142_o(),\n    .sl_iport143_o(),\n    .sl_iport144_o(),\n    .sl_iport145_o(),\n    .sl_iport146_o(),\n    .sl_iport147_o(),\n    .sl_iport148_o(),\n    .sl_iport149_o(),\n    .sl_iport150_o(),\n    .sl_iport151_o(),\n    .sl_iport152_o(),\n    .sl_iport153_o(),\n    .sl_iport154_o(),\n    .sl_iport155_o(),\n    .sl_iport156_o(),\n    .sl_iport157_o(),\n    .sl_iport158_o(),\n    .sl_iport159_o(),\n    .sl_iport160_o(),\n    .sl_iport161_o(),\n    .sl_iport162_o(),\n    .sl_iport163_o(),\n    .sl_iport164_o(),\n    .sl_iport165_o(),\n    .sl_iport166_o(),\n    .sl_iport167_o(),\n    .sl_iport168_o(),\n    .sl_iport169_o(),\n    .sl_iport170_o(),\n    .sl_iport171_o(),\n    .sl_iport172_o(),\n    .sl_iport173_o(),\n    .sl_iport174_o(),\n    .sl_iport175_o(),\n    .sl_iport176_o(),\n    .sl_iport177_o(),\n    .sl_iport178_o(),\n    .sl_iport179_o(),\n    .sl_iport180_o(),\n    .sl_iport181_o(),\n    .sl_iport182_o(),\n    .sl_iport183_o(),\n    .sl_iport184_o(),\n    .sl_iport185_o(),\n    .sl_iport186_o(),\n    .sl_iport187_o(),\n    .sl_iport188_o(),\n    .sl_iport189_o(),\n    .sl_iport190_o(),\n    .sl_iport191_o(),\n    .sl_iport192_o(),\n    .sl_iport193_o(),\n    .sl_iport194_o(),\n    .sl_iport195_o(),\n    .sl_iport196_o(),\n    .sl_iport197_o(),\n    .sl_iport198_o(),\n    .sl_iport199_o(),\n    .sl_iport200_o(),\n    .sl_iport201_o(),\n    .sl_iport202_o(),\n    .sl_iport203_o(),\n    .sl_iport204_o(),\n    .sl_iport205_o(),\n    .sl_iport206_o(),\n    .sl_iport207_o(),\n    .sl_iport208_o(),\n    .sl_iport209_o(),\n    .sl_iport210_o(),\n    .sl_iport211_o(),\n    .sl_iport212_o(),\n    .sl_iport213_o(),\n    .sl_iport214_o(),\n    .sl_iport215_o(),\n    .sl_iport216_o(),\n    .sl_iport217_o(),\n    .sl_iport218_o(),\n    .sl_iport219_o(),\n    .sl_iport220_o(),\n    .sl_iport221_o(),\n    .sl_iport222_o(),\n    .sl_iport223_o(),\n    .sl_iport224_o(),\n    .sl_iport225_o(),\n    .sl_iport226_o(),\n    .sl_iport227_o(),\n    .sl_iport228_o(),\n    .sl_iport229_o(),\n    .sl_iport230_o(),\n    .sl_iport231_o(),\n    .sl_iport232_o(),\n    .sl_iport233_o(),\n    .sl_iport234_o(),\n    .sl_iport235_o(),\n    .sl_iport236_o(),\n    .sl_iport237_o(),\n    .sl_iport238_o(),\n    .sl_iport239_o(),\n    .sl_iport240_o(),\n    .sl_iport241_o(),\n    .sl_iport242_o(),\n    .sl_iport243_o(),\n    .sl_iport244_o(),\n    .sl_iport245_o(),\n    .sl_iport246_o(),\n    .sl_iport247_o(),\n    .sl_iport248_o(),\n    .sl_iport249_o(),\n    .sl_iport250_o(),\n    .sl_iport251_o(),\n    .sl_iport252_o(),\n    .sl_iport253_o(),\n    .sl_iport254_o(),\n    .sl_iport255_o(),\n    .sl_oport0_i(1'B0),\n    .sl_oport1_i(1'B0),\n    .sl_oport2_i(1'B0),\n    .sl_oport3_i(1'B0),\n    .sl_oport4_i(1'B0),\n    .sl_oport5_i(1'B0),\n    .sl_oport6_i(1'B0),\n    .sl_oport7_i(1'B0),\n    .sl_oport8_i(1'B0),\n    .sl_oport9_i(1'B0),\n    .sl_oport10_i(1'B0),\n    .sl_oport11_i(1'B0),\n    .sl_oport12_i(1'B0),\n    .sl_oport13_i(1'B0),\n    .sl_oport14_i(1'B0),\n    .sl_oport15_i(1'B0),\n    .sl_oport16_i(1'B0),\n    .sl_oport17_i(1'B0),\n    .sl_oport18_i(1'B0),\n    .sl_oport19_i(1'B0),\n    .sl_oport20_i(1'B0),\n    .sl_oport21_i(1'B0),\n    .sl_oport22_i(1'B0),\n    .sl_oport23_i(1'B0),\n    .sl_oport24_i(1'B0),\n    .sl_oport25_i(1'B0),\n    .sl_oport26_i(1'B0),\n    .sl_oport27_i(1'B0),\n    .sl_oport28_i(1'B0),\n    .sl_oport29_i(1'B0),\n    .sl_oport30_i(1'B0),\n    .sl_oport31_i(1'B0),\n    .sl_oport32_i(1'B0),\n    .sl_oport33_i(1'B0),\n    .sl_oport34_i(1'B0),\n    .sl_oport35_i(1'B0),\n    .sl_oport36_i(1'B0),\n    .sl_oport37_i(1'B0),\n    .sl_oport38_i(1'B0),\n    .sl_oport39_i(1'B0),\n    .sl_oport40_i(1'B0),\n    .sl_oport41_i(1'B0),\n    .sl_oport42_i(1'B0),\n    .sl_oport43_i(1'B0),\n    .sl_oport44_i(1'B0),\n    .sl_oport45_i(1'B0),\n    .sl_oport46_i(1'B0),\n    .sl_oport47_i(1'B0),\n    .sl_oport48_i(1'B0),\n    .sl_oport49_i(1'B0),\n    .sl_oport50_i(1'B0),\n    .sl_oport51_i(1'B0),\n    .sl_oport52_i(1'B0),\n    .sl_oport53_i(1'B0),\n    .sl_oport54_i(1'B0),\n    .sl_oport55_i(1'B0),\n    .sl_oport56_i(1'B0),\n    .sl_oport57_i(1'B0),\n    .sl_oport58_i(1'B0),\n    .sl_oport59_i(1'B0),\n    .sl_oport60_i(1'B0),\n    .sl_oport61_i(1'B0),\n    .sl_oport62_i(1'B0),\n    .sl_oport63_i(1'B0),\n    .sl_oport64_i(1'B0),\n    .sl_oport65_i(1'B0),\n    .sl_oport66_i(1'B0),\n    .sl_oport67_i(1'B0),\n    .sl_oport68_i(1'B0),\n    .sl_oport69_i(1'B0),\n    .sl_oport70_i(1'B0),\n    .sl_oport71_i(1'B0),\n    .sl_oport72_i(1'B0),\n    .sl_oport73_i(1'B0),\n    .sl_oport74_i(1'B0),\n    .sl_oport75_i(1'B0),\n    .sl_oport76_i(1'B0),\n    .sl_oport77_i(1'B0),\n    .sl_oport78_i(1'B0),\n    .sl_oport79_i(1'B0),\n    .sl_oport80_i(1'B0),\n    .sl_oport81_i(1'B0),\n    .sl_oport82_i(1'B0),\n    .sl_oport83_i(1'B0),\n    .sl_oport84_i(1'B0),\n    .sl_oport85_i(1'B0),\n    .sl_oport86_i(1'B0),\n    .sl_oport87_i(1'B0),\n    .sl_oport88_i(1'B0),\n    .sl_oport89_i(1'B0),\n    .sl_oport90_i(1'B0),\n    .sl_oport91_i(1'B0),\n    .sl_oport92_i(1'B0),\n    .sl_oport93_i(1'B0),\n    .sl_oport94_i(1'B0),\n    .sl_oport95_i(1'B0),\n    .sl_oport96_i(1'B0),\n    .sl_oport97_i(1'B0),\n    .sl_oport98_i(1'B0),\n    .sl_oport99_i(1'B0),\n    .sl_oport100_i(1'B0),\n    .sl_oport101_i(1'B0),\n    .sl_oport102_i(1'B0),\n    .sl_oport103_i(1'B0),\n    .sl_oport104_i(1'B0),\n    .sl_oport105_i(1'B0),\n    .sl_oport106_i(1'B0),\n    .sl_oport107_i(1'B0),\n    .sl_oport108_i(1'B0),\n    .sl_oport109_i(1'B0),\n    .sl_oport110_i(1'B0),\n    .sl_oport111_i(1'B0),\n    .sl_oport112_i(1'B0),\n    .sl_oport113_i(1'B0),\n    .sl_oport114_i(1'B0),\n    .sl_oport115_i(1'B0),\n    .sl_oport116_i(1'B0),\n    .sl_oport117_i(1'B0),\n    .sl_oport118_i(1'B0),\n    .sl_oport119_i(1'B0),\n    .sl_oport120_i(1'B0),\n    .sl_oport121_i(1'B0),\n    .sl_oport122_i(1'B0),\n    .sl_oport123_i(1'B0),\n    .sl_oport124_i(1'B0),\n    .sl_oport125_i(1'B0),\n    .sl_oport126_i(1'B0),\n    .sl_oport127_i(1'B0),\n    .sl_oport128_i(1'B0),\n    .sl_oport129_i(1'B0),\n    .sl_oport130_i(1'B0),\n    .sl_oport131_i(1'B0),\n    .sl_oport132_i(1'B0),\n    .sl_oport133_i(1'B0),\n    .sl_oport134_i(1'B0),\n    .sl_oport135_i(1'B0),\n    .sl_oport136_i(1'B0),\n    .sl_oport137_i(1'B0),\n    .sl_oport138_i(1'B0),\n    .sl_oport139_i(1'B0),\n    .sl_oport140_i(1'B0),\n    .sl_oport141_i(1'B0),\n    .sl_oport142_i(1'B0),\n    .sl_oport143_i(1'B0),\n    .sl_oport144_i(1'B0),\n    .sl_oport145_i(1'B0),\n    .sl_oport146_i(1'B0),\n    .sl_oport147_i(1'B0),\n    .sl_oport148_i(1'B0),\n    .sl_oport149_i(1'B0),\n    .sl_oport150_i(1'B0),\n    .sl_oport151_i(1'B0),\n    .sl_oport152_i(1'B0),\n    .sl_oport153_i(1'B0),\n    .sl_oport154_i(1'B0),\n    .sl_oport155_i(1'B0),\n    .sl_oport156_i(1'B0),\n    .sl_oport157_i(1'B0),\n    .sl_oport158_i(1'B0),\n    .sl_oport159_i(1'B0),\n    .sl_oport160_i(1'B0),\n    .sl_oport161_i(1'B0),\n    .sl_oport162_i(1'B0),\n    .sl_oport163_i(1'B0),\n    .sl_oport164_i(1'B0),\n    .sl_oport165_i(1'B0),\n    .sl_oport166_i(1'B0),\n    .sl_oport167_i(1'B0),\n    .sl_oport168_i(1'B0),\n    .sl_oport169_i(1'B0),\n    .sl_oport170_i(1'B0),\n    .sl_oport171_i(1'B0),\n    .sl_oport172_i(1'B0),\n    .sl_oport173_i(1'B0),\n    .sl_oport174_i(1'B0),\n    .sl_oport175_i(1'B0),\n    .sl_oport176_i(1'B0),\n    .sl_oport177_i(1'B0),\n    .sl_oport178_i(1'B0),\n    .sl_oport179_i(1'B0),\n    .sl_oport180_i(1'B0),\n    .sl_oport181_i(1'B0),\n    .sl_oport182_i(1'B0),\n    .sl_oport183_i(1'B0),\n    .sl_oport184_i(1'B0),\n    .sl_oport185_i(1'B0),\n    .sl_oport186_i(1'B0),\n    .sl_oport187_i(1'B0),\n    .sl_oport188_i(1'B0),\n    .sl_oport189_i(1'B0),\n    .sl_oport190_i(1'B0),\n    .sl_oport191_i(1'B0),\n    .sl_oport192_i(1'B0),\n    .sl_oport193_i(1'B0),\n    .sl_oport194_i(1'B0),\n    .sl_oport195_i(1'B0),\n    .sl_oport196_i(1'B0),\n    .sl_oport197_i(1'B0),\n    .sl_oport198_i(1'B0),\n    .sl_oport199_i(1'B0),\n    .sl_oport200_i(1'B0),\n    .sl_oport201_i(1'B0),\n    .sl_oport202_i(1'B0),\n    .sl_oport203_i(1'B0),\n    .sl_oport204_i(1'B0),\n    .sl_oport205_i(1'B0),\n    .sl_oport206_i(1'B0),\n    .sl_oport207_i(1'B0),\n    .sl_oport208_i(1'B0),\n    .sl_oport209_i(1'B0),\n    .sl_oport210_i(1'B0),\n    .sl_oport211_i(1'B0),\n    .sl_oport212_i(1'B0),\n    .sl_oport213_i(1'B0),\n    .sl_oport214_i(1'B0),\n    .sl_oport215_i(1'B0),\n    .sl_oport216_i(1'B0),\n    .sl_oport217_i(1'B0),\n    .sl_oport218_i(1'B0),\n    .sl_oport219_i(1'B0),\n    .sl_oport220_i(1'B0),\n    .sl_oport221_i(1'B0),\n    .sl_oport222_i(1'B0),\n    .sl_oport223_i(1'B0),\n    .sl_oport224_i(1'B0),\n    .sl_oport225_i(1'B0),\n    .sl_oport226_i(1'B0),\n    .sl_oport227_i(1'B0),\n    .sl_oport228_i(1'B0),\n    .sl_oport229_i(1'B0),\n    .sl_oport230_i(1'B0),\n    .sl_oport231_i(1'B0),\n    .sl_oport232_i(1'B0),\n    .sl_oport233_i(1'B0),\n    .sl_oport234_i(1'B0),\n    .sl_oport235_i(1'B0),\n    .sl_oport236_i(1'B0),\n    .sl_oport237_i(1'B0),\n    .sl_oport238_i(1'B0),\n    .sl_oport239_i(1'B0),\n    .sl_oport240_i(1'B0),\n    .sl_oport241_i(1'B0),\n    .sl_oport242_i(1'B0),\n    .sl_oport243_i(1'B0),\n    .sl_oport244_i(1'B0),\n    .sl_oport245_i(1'B0),\n    .sl_oport246_i(1'B0),\n    .sl_oport247_i(1'B0),\n    .sl_oport248_i(1'B0),\n    .sl_oport249_i(1'B0),\n    .sl_oport250_i(1'B0),\n    .sl_oport251_i(1'B0),\n    .sl_oport252_i(1'B0),\n    .sl_oport253_i(1'B0),\n    .sl_oport254_i(1'B0),\n    .sl_oport255_i(1'B0),\n    .update_0(),\n    .capture_0(),\n    .reset_0(),\n    .runtest_0(),\n    .tms_0(),\n    .tck_0(),\n    .tdi_0(),\n    .sel_0(),\n    .shift_0(),\n    .drck_0(),\n    .tdo_0(1'B0),\n    .update_1(),\n    .capture_1(),\n    .reset_1(),\n    .runtest_1(),\n    .tms_1(),\n    .tck_1(),\n    .tdi_1(),\n    .sel_1(),\n    .shift_1(),\n    .drck_1(),\n    .tdo_1(1'B0),\n    .update_2(),\n    .capture_2(),\n    .reset_2(),\n    .runtest_2(),\n    .tms_2(),\n    .tck_2(),\n    .tdi_2(),\n    .sel_2(),\n    .shift_2(),\n    .drck_2(),\n    .tdo_2(1'B0),\n    .update_3(),\n    .capture_3(),\n    .reset_3(),\n    .runtest_3(),\n    .tms_3(),\n    .tck_3(),\n    .tdi_3(),\n    .sel_3(),\n    .shift_3(),\n    .drck_3(),\n    .tdo_3(1'B0),\n    .update_4(),\n    .capture_4(),\n    .reset_4(),\n    .runtest_4(),\n    .tms_4(),\n    .tck_4(),\n    .tdi_4(),\n    .sel_4(),\n    .shift_4(),\n    .drck_4(),\n    .tdo_4(1'B0),\n    .update_5(),\n    .capture_5(),\n    .reset_5(),\n    .runtest_5(),\n    .tms_5(),\n    .tck_5(),\n    .tdi_5(),\n    .sel_5(),\n    .shift_5(),\n    .drck_5(),\n    .tdo_5(1'B0),\n    .update_6(),\n    .capture_6(),\n    .reset_6(),\n    .runtest_6(),\n    .tms_6(),\n    .tck_6(),\n    .tdi_6(),\n    .sel_6(),\n    .shift_6(),\n    .drck_6(),\n    .tdo_6(1'B0),\n    .update_7(),\n    .capture_7(),\n    .reset_7(),\n    .runtest_7(),\n    .tms_7(),\n    .tck_7(),\n    .tdi_7(),\n    .sel_7(),\n    .shift_7(),\n    .drck_7(),\n    .tdo_7(1'B0),\n    .update_8(),\n    .capture_8(),\n    .reset_8(),\n    .runtest_8(),\n    .tms_8(),\n    .tck_8(),\n    .tdi_8(),\n    .sel_8(),\n    .shift_8(),\n    .drck_8(),\n    .tdo_8(1'B0),\n    .update_9(),\n    .capture_9(),\n    .reset_9(),\n    .runtest_9(),\n    .tms_9(),\n    .tck_9(),\n    .tdi_9(),\n    .sel_9(),\n    .shift_9(),\n    .drck_9(),\n    .tdo_9(1'B0),\n    .update_10(),\n    .capture_10(),\n    .reset_10(),\n    .runtest_10(),\n    .tms_10(),\n    .tck_10(),\n    .tdi_10(),\n    .sel_10(),\n    .shift_10(),\n    .drck_10(),\n    .tdo_10(1'B0),\n    .update_11(),\n    .capture_11(),\n    .reset_11(),\n    .runtest_11(),\n    .tms_11(),\n    .tck_11(),\n    .tdi_11(),\n    .sel_11(),\n    .shift_11(),\n    .drck_11(),\n    .tdo_11(1'B0),\n    .update_12(),\n    .capture_12(),\n    .reset_12(),\n    .runtest_12(),\n    .tms_12(),\n    .tck_12(),\n    .tdi_12(),\n    .sel_12(),\n    .shift_12(),\n    .drck_12(),\n    .tdo_12(1'B0),\n    .update_13(),\n    .capture_13(),\n    .reset_13(),\n    .runtest_13(),\n    .tms_13(),\n    .tck_13(),\n    .tdi_13(),\n    .sel_13(),\n    .shift_13(),\n    .drck_13(),\n    .tdo_13(1'B0),\n    .update_14(),\n    .capture_14(),\n    .reset_14(),\n    .runtest_14(),\n    .tms_14(),\n    .tck_14(),\n    .tdi_14(),\n    .sel_14(),\n    .shift_14(),\n    .drck_14(),\n    .tdo_14(1'B0),\n    .update_15(),\n    .capture_15(),\n    .reset_15(),\n    .runtest_15(),\n    .tms_15(),\n    .tck_15(),\n    .tdi_15(),\n    .sel_15(),\n    .shift_15(),\n    .drck_15(),\n    .tdo_15(1'B0),\n    .bscanid_en_0(),\n    .bscanid_en_1(),\n    .bscanid_en_2(),\n    .bscanid_en_3(),\n    .bscanid_en_4(),\n    .bscanid_en_5(),\n    .bscanid_en_6(),\n    .bscanid_en_7(),\n    .bscanid_en_8(),\n    .bscanid_en_9(),\n    .bscanid_en_10(),\n    .bscanid_en_11(),\n    .bscanid_en_12(),\n    .bscanid_en_13(),\n    .bscanid_en_14(),\n    .bscanid_en_15(),\n    .bscanid_0(32'B0),\n    .bscanid_1(32'B0),\n    .bscanid_2(32'B0),\n    .bscanid_3(32'B0),\n    .bscanid_4(32'B0),\n    .bscanid_5(32'B0),\n    .bscanid_6(32'B0),\n    .bscanid_7(32'B0),\n    .bscanid_8(32'B0),\n    .bscanid_9(32'B0),\n    .bscanid_10(32'B0),\n    .bscanid_11(32'B0),\n    .bscanid_12(32'B0),\n    .bscanid_13(32'B0),\n    .bscanid_14(32'B0),\n    .bscanid_15(32'B0),\n    .update(update),\n    .capture(capture),\n    .reset(reset),\n    .runtest(runtest),\n    .tck(tck),\n    .tms(tms),\n    .tdi(tdi),\n    .sel(sel),\n    .shift(shift),\n    .drck(drck),\n    .tdo(tdo),\n    .bscanid_en(bscanid_en),\n    .bscanid(),\n    .clk(clk)\n  );\nendmodule\n", "num_lines": 868}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:xsdbm:3.0\n// IP Revision: 0\n\n(* X_CORE_INFO = \"xsdbm_v3_0_0_xsdbm,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"bd_a493_xsdbm_0,xsdbm_v3_0_0_xsdbm,{}\" *)\n(* CORE_GENERATION_INFO = \"bd_a493_xsdbm_0,xsdbm_v3_0_0_xsdbm,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xsdbm,x_ipVersion=3.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FIFO_STYLE=SUBCORE,C_XDEVICEFAMILY=virtexuplus,C_MAJOR_VERSION=14,C_MINOR_VERSION=1,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=1,C_CORE_MINOR_VER=0,C_CORE_MINOR_ALPHA_VER=97,C_XSDB_NUM_SLAVES=0,C_XSDB_PERIOD_INT=10,C_XSDB_PERIOD_FRC=0,C_USE_BUFR=0,C_DCLK_HAS_RESET=0,C_EN_INT_SIM=1,C_CORE_TYPE=1,C_USER_SCAN_CHAIN\\\n=1,C_CLKFBOUT_MULT_F=4.000,C_DIVCLK_DIVIDE=1,C_CLKOUT0_DIVIDE_F=12.000,C_CLK_INPUT_FREQ_HZ=300000000,C_ENABLE_CLK_DIVIDER=0,C_USE_EXT_BSCAN=1,C_USE_STARTUP_CLK=0,C_EN_BSCANID_VEC=0,C_TWO_PRIM_MODE=0,C_USER_SCAN_CHAIN1=1,C_BSCANID=76546592,C_BSCAN_MODE=0,C_BSCAN_MODE_WITH_CORE=0,C_NUM_BSCAN_MASTER_PORTS=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_a493_xsdbm_0 (\n  update,\n  capture,\n  reset,\n  runtest,\n  tck,\n  tms,\n  tdi,\n  sel,\n  shift,\n  drck,\n  tdo,\n  bscanid_en,\n  clk\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan UPDATE\" *)\ninput wire update;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan CAPTURE\" *)\ninput wire capture;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RESET\" *)\ninput wire reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RUNTEST\" *)\ninput wire runtest;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TCK\" *)\ninput wire tck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TMS\" *)\ninput wire tms;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDI\" *)\ninput wire tdi;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SEL\" *)\ninput wire sel;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SHIFT\" *)\ninput wire shift;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan DRCK\" *)\ninput wire drck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDO\" *)\noutput wire tdo;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan BSCANID_EN\" *)\ninput wire bscanid_en;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME signal_clock, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_a493_clk, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 signal_clock CLK\" *)\ninput wire clk;\n\n  xsdbm_v3_0_0_xsdbm #(\n    .C_FIFO_STYLE(\"SUBCORE\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_MAJOR_VERSION(14),\n    .C_MINOR_VERSION(1),\n    .C_BUILD_REVISION(0),\n    .C_CORE_MAJOR_VER(1),\n    .C_CORE_MINOR_VER(0),\n    .C_CORE_MINOR_ALPHA_VER(97),\n    .C_XSDB_NUM_SLAVES(0),\n    .C_XSDB_PERIOD_INT(10),\n    .C_XSDB_PERIOD_FRC(0),\n    .C_USE_BUFR(0),\n    .C_DCLK_HAS_RESET(0),\n    .C_EN_INT_SIM(1),\n    .C_CORE_TYPE(1),\n    .C_USER_SCAN_CHAIN(1),\n    .C_CLKFBOUT_MULT_F(4.000),\n    .C_DIVCLK_DIVIDE(1),\n    .C_CLKOUT0_DIVIDE_F(12.000),\n    .C_CLK_INPUT_FREQ_HZ(300000000),\n    .C_ENABLE_CLK_DIVIDER(0),\n    .C_USE_EXT_BSCAN(1),\n    .C_USE_STARTUP_CLK(0),\n    .C_EN_BSCANID_VEC(0),\n    .C_TWO_PRIM_MODE(0),\n    .C_USER_SCAN_CHAIN1(1),\n    .C_BSCANID(76546592),\n    .C_BSCAN_MODE(0),\n    .C_BSCAN_MODE_WITH_CORE(0),\n    .C_NUM_BSCAN_MASTER_PORTS(0)\n  ) inst (\n    .sl_iport0_o(),\n    .sl_iport1_o(),\n    .sl_iport2_o(),\n    .sl_iport3_o(),\n    .sl_iport4_o(),\n    .sl_iport5_o(),\n    .sl_iport6_o(),\n    .sl_iport7_o(),\n    .sl_iport8_o(),\n    .sl_iport9_o(),\n    .sl_iport10_o(),\n    .sl_iport11_o(),\n    .sl_iport12_o(),\n    .sl_iport13_o(),\n    .sl_iport14_o(),\n    .sl_iport15_o(),\n    .sl_iport16_o(),\n    .sl_iport17_o(),\n    .sl_iport18_o(),\n    .sl_iport19_o(),\n    .sl_iport20_o(),\n    .sl_iport21_o(),\n    .sl_iport22_o(),\n    .sl_iport23_o(),\n    .sl_iport24_o(),\n    .sl_iport25_o(),\n    .sl_iport26_o(),\n    .sl_iport27_o(),\n    .sl_iport28_o(),\n    .sl_iport29_o(),\n    .sl_iport30_o(),\n    .sl_iport31_o(),\n    .sl_iport32_o(),\n    .sl_iport33_o(),\n    .sl_iport34_o(),\n    .sl_iport35_o(),\n    .sl_iport36_o(),\n    .sl_iport37_o(),\n    .sl_iport38_o(),\n    .sl_iport39_o(),\n    .sl_iport40_o(),\n    .sl_iport41_o(),\n    .sl_iport42_o(),\n    .sl_iport43_o(),\n    .sl_iport44_o(),\n    .sl_iport45_o(),\n    .sl_iport46_o(),\n    .sl_iport47_o(),\n    .sl_iport48_o(),\n    .sl_iport49_o(),\n    .sl_iport50_o(),\n    .sl_iport51_o(),\n    .sl_iport52_o(),\n    .sl_iport53_o(),\n    .sl_iport54_o(),\n    .sl_iport55_o(),\n    .sl_iport56_o(),\n    .sl_iport57_o(),\n    .sl_iport58_o(),\n    .sl_iport59_o(),\n    .sl_iport60_o(),\n    .sl_iport61_o(),\n    .sl_iport62_o(),\n    .sl_iport63_o(),\n    .sl_iport64_o(),\n    .sl_iport65_o(),\n    .sl_iport66_o(),\n    .sl_iport67_o(),\n    .sl_iport68_o(),\n    .sl_iport69_o(),\n    .sl_iport70_o(),\n    .sl_iport71_o(),\n    .sl_iport72_o(),\n    .sl_iport73_o(),\n    .sl_iport74_o(),\n    .sl_iport75_o(),\n    .sl_iport76_o(),\n    .sl_iport77_o(),\n    .sl_iport78_o(),\n    .sl_iport79_o(),\n    .sl_iport80_o(),\n    .sl_iport81_o(),\n    .sl_iport82_o(),\n    .sl_iport83_o(),\n    .sl_iport84_o(),\n    .sl_iport85_o(),\n    .sl_iport86_o(),\n    .sl_iport87_o(),\n    .sl_iport88_o(),\n    .sl_iport89_o(),\n    .sl_iport90_o(),\n    .sl_iport91_o(),\n    .sl_iport92_o(),\n    .sl_iport93_o(),\n    .sl_iport94_o(),\n    .sl_iport95_o(),\n    .sl_iport96_o(),\n    .sl_iport97_o(),\n    .sl_iport98_o(),\n    .sl_iport99_o(),\n    .sl_iport100_o(),\n    .sl_iport101_o(),\n    .sl_iport102_o(),\n    .sl_iport103_o(),\n    .sl_iport104_o(),\n    .sl_iport105_o(),\n    .sl_iport106_o(),\n    .sl_iport107_o(),\n    .sl_iport108_o(),\n    .sl_iport109_o(),\n    .sl_iport110_o(),\n    .sl_iport111_o(),\n    .sl_iport112_o(),\n    .sl_iport113_o(),\n    .sl_iport114_o(),\n    .sl_iport115_o(),\n    .sl_iport116_o(),\n    .sl_iport117_o(),\n    .sl_iport118_o(),\n    .sl_iport119_o(),\n    .sl_iport120_o(),\n    .sl_iport121_o(),\n    .sl_iport122_o(),\n    .sl_iport123_o(),\n    .sl_iport124_o(),\n    .sl_iport125_o(),\n    .sl_iport126_o(),\n    .sl_iport127_o(),\n    .sl_iport128_o(),\n    .sl_iport129_o(),\n    .sl_iport130_o(),\n    .sl_iport131_o(),\n    .sl_iport132_o(),\n    .sl_iport133_o(),\n    .sl_iport134_o(),\n    .sl_iport135_o(),\n    .sl_iport136_o(),\n    .sl_iport137_o(),\n    .sl_iport138_o(),\n    .sl_iport139_o(),\n    .sl_iport140_o(),\n    .sl_iport141_o(),\n    .sl_iport142_o(),\n    .sl_iport143_o(),\n    .sl_iport144_o(),\n    .sl_iport145_o(),\n    .sl_iport146_o(),\n    .sl_iport147_o(),\n    .sl_iport148_o(),\n    .sl_iport149_o(),\n    .sl_iport150_o(),\n    .sl_iport151_o(),\n    .sl_iport152_o(),\n    .sl_iport153_o(),\n    .sl_iport154_o(),\n    .sl_iport155_o(),\n    .sl_iport156_o(),\n    .sl_iport157_o(),\n    .sl_iport158_o(),\n    .sl_iport159_o(),\n    .sl_iport160_o(),\n    .sl_iport161_o(),\n    .sl_iport162_o(),\n    .sl_iport163_o(),\n    .sl_iport164_o(),\n    .sl_iport165_o(),\n    .sl_iport166_o(),\n    .sl_iport167_o(),\n    .sl_iport168_o(),\n    .sl_iport169_o(),\n    .sl_iport170_o(),\n    .sl_iport171_o(),\n    .sl_iport172_o(),\n    .sl_iport173_o(),\n    .sl_iport174_o(),\n    .sl_iport175_o(),\n    .sl_iport176_o(),\n    .sl_iport177_o(),\n    .sl_iport178_o(),\n    .sl_iport179_o(),\n    .sl_iport180_o(),\n    .sl_iport181_o(),\n    .sl_iport182_o(),\n    .sl_iport183_o(),\n    .sl_iport184_o(),\n    .sl_iport185_o(),\n    .sl_iport186_o(),\n    .sl_iport187_o(),\n    .sl_iport188_o(),\n    .sl_iport189_o(),\n    .sl_iport190_o(),\n    .sl_iport191_o(),\n    .sl_iport192_o(),\n    .sl_iport193_o(),\n    .sl_iport194_o(),\n    .sl_iport195_o(),\n    .sl_iport196_o(),\n    .sl_iport197_o(),\n    .sl_iport198_o(),\n    .sl_iport199_o(),\n    .sl_iport200_o(),\n    .sl_iport201_o(),\n    .sl_iport202_o(),\n    .sl_iport203_o(),\n    .sl_iport204_o(),\n    .sl_iport205_o(),\n    .sl_iport206_o(),\n    .sl_iport207_o(),\n    .sl_iport208_o(),\n    .sl_iport209_o(),\n    .sl_iport210_o(),\n    .sl_iport211_o(),\n    .sl_iport212_o(),\n    .sl_iport213_o(),\n    .sl_iport214_o(),\n    .sl_iport215_o(),\n    .sl_iport216_o(),\n    .sl_iport217_o(),\n    .sl_iport218_o(),\n    .sl_iport219_o(),\n    .sl_iport220_o(),\n    .sl_iport221_o(),\n    .sl_iport222_o(),\n    .sl_iport223_o(),\n    .sl_iport224_o(),\n    .sl_iport225_o(),\n    .sl_iport226_o(),\n    .sl_iport227_o(),\n    .sl_iport228_o(),\n    .sl_iport229_o(),\n    .sl_iport230_o(),\n    .sl_iport231_o(),\n    .sl_iport232_o(),\n    .sl_iport233_o(),\n    .sl_iport234_o(),\n    .sl_iport235_o(),\n    .sl_iport236_o(),\n    .sl_iport237_o(),\n    .sl_iport238_o(),\n    .sl_iport239_o(),\n    .sl_iport240_o(),\n    .sl_iport241_o(),\n    .sl_iport242_o(),\n    .sl_iport243_o(),\n    .sl_iport244_o(),\n    .sl_iport245_o(),\n    .sl_iport246_o(),\n    .sl_iport247_o(),\n    .sl_iport248_o(),\n    .sl_iport249_o(),\n    .sl_iport250_o(),\n    .sl_iport251_o(),\n    .sl_iport252_o(),\n    .sl_iport253_o(),\n    .sl_iport254_o(),\n    .sl_iport255_o(),\n    .sl_oport0_i(1'B0),\n    .sl_oport1_i(1'B0),\n    .sl_oport2_i(1'B0),\n    .sl_oport3_i(1'B0),\n    .sl_oport4_i(1'B0),\n    .sl_oport5_i(1'B0),\n    .sl_oport6_i(1'B0),\n    .sl_oport7_i(1'B0),\n    .sl_oport8_i(1'B0),\n    .sl_oport9_i(1'B0),\n    .sl_oport10_i(1'B0),\n    .sl_oport11_i(1'B0),\n    .sl_oport12_i(1'B0),\n    .sl_oport13_i(1'B0),\n    .sl_oport14_i(1'B0),\n    .sl_oport15_i(1'B0),\n    .sl_oport16_i(1'B0),\n    .sl_oport17_i(1'B0),\n    .sl_oport18_i(1'B0),\n    .sl_oport19_i(1'B0),\n    .sl_oport20_i(1'B0),\n    .sl_oport21_i(1'B0),\n    .sl_oport22_i(1'B0),\n    .sl_oport23_i(1'B0),\n    .sl_oport24_i(1'B0),\n    .sl_oport25_i(1'B0),\n    .sl_oport26_i(1'B0),\n    .sl_oport27_i(1'B0),\n    .sl_oport28_i(1'B0),\n    .sl_oport29_i(1'B0),\n    .sl_oport30_i(1'B0),\n    .sl_oport31_i(1'B0),\n    .sl_oport32_i(1'B0),\n    .sl_oport33_i(1'B0),\n    .sl_oport34_i(1'B0),\n    .sl_oport35_i(1'B0),\n    .sl_oport36_i(1'B0),\n    .sl_oport37_i(1'B0),\n    .sl_oport38_i(1'B0),\n    .sl_oport39_i(1'B0),\n    .sl_oport40_i(1'B0),\n    .sl_oport41_i(1'B0),\n    .sl_oport42_i(1'B0),\n    .sl_oport43_i(1'B0),\n    .sl_oport44_i(1'B0),\n    .sl_oport45_i(1'B0),\n    .sl_oport46_i(1'B0),\n    .sl_oport47_i(1'B0),\n    .sl_oport48_i(1'B0),\n    .sl_oport49_i(1'B0),\n    .sl_oport50_i(1'B0),\n    .sl_oport51_i(1'B0),\n    .sl_oport52_i(1'B0),\n    .sl_oport53_i(1'B0),\n    .sl_oport54_i(1'B0),\n    .sl_oport55_i(1'B0),\n    .sl_oport56_i(1'B0),\n    .sl_oport57_i(1'B0),\n    .sl_oport58_i(1'B0),\n    .sl_oport59_i(1'B0),\n    .sl_oport60_i(1'B0),\n    .sl_oport61_i(1'B0),\n    .sl_oport62_i(1'B0),\n    .sl_oport63_i(1'B0),\n    .sl_oport64_i(1'B0),\n    .sl_oport65_i(1'B0),\n    .sl_oport66_i(1'B0),\n    .sl_oport67_i(1'B0),\n    .sl_oport68_i(1'B0),\n    .sl_oport69_i(1'B0),\n    .sl_oport70_i(1'B0),\n    .sl_oport71_i(1'B0),\n    .sl_oport72_i(1'B0),\n    .sl_oport73_i(1'B0),\n    .sl_oport74_i(1'B0),\n    .sl_oport75_i(1'B0),\n    .sl_oport76_i(1'B0),\n    .sl_oport77_i(1'B0),\n    .sl_oport78_i(1'B0),\n    .sl_oport79_i(1'B0),\n    .sl_oport80_i(1'B0),\n    .sl_oport81_i(1'B0),\n    .sl_oport82_i(1'B0),\n    .sl_oport83_i(1'B0),\n    .sl_oport84_i(1'B0),\n    .sl_oport85_i(1'B0),\n    .sl_oport86_i(1'B0),\n    .sl_oport87_i(1'B0),\n    .sl_oport88_i(1'B0),\n    .sl_oport89_i(1'B0),\n    .sl_oport90_i(1'B0),\n    .sl_oport91_i(1'B0),\n    .sl_oport92_i(1'B0),\n    .sl_oport93_i(1'B0),\n    .sl_oport94_i(1'B0),\n    .sl_oport95_i(1'B0),\n    .sl_oport96_i(1'B0),\n    .sl_oport97_i(1'B0),\n    .sl_oport98_i(1'B0),\n    .sl_oport99_i(1'B0),\n    .sl_oport100_i(1'B0),\n    .sl_oport101_i(1'B0),\n    .sl_oport102_i(1'B0),\n    .sl_oport103_i(1'B0),\n    .sl_oport104_i(1'B0),\n    .sl_oport105_i(1'B0),\n    .sl_oport106_i(1'B0),\n    .sl_oport107_i(1'B0),\n    .sl_oport108_i(1'B0),\n    .sl_oport109_i(1'B0),\n    .sl_oport110_i(1'B0),\n    .sl_oport111_i(1'B0),\n    .sl_oport112_i(1'B0),\n    .sl_oport113_i(1'B0),\n    .sl_oport114_i(1'B0),\n    .sl_oport115_i(1'B0),\n    .sl_oport116_i(1'B0),\n    .sl_oport117_i(1'B0),\n    .sl_oport118_i(1'B0),\n    .sl_oport119_i(1'B0),\n    .sl_oport120_i(1'B0),\n    .sl_oport121_i(1'B0),\n    .sl_oport122_i(1'B0),\n    .sl_oport123_i(1'B0),\n    .sl_oport124_i(1'B0),\n    .sl_oport125_i(1'B0),\n    .sl_oport126_i(1'B0),\n    .sl_oport127_i(1'B0),\n    .sl_oport128_i(1'B0),\n    .sl_oport129_i(1'B0),\n    .sl_oport130_i(1'B0),\n    .sl_oport131_i(1'B0),\n    .sl_oport132_i(1'B0),\n    .sl_oport133_i(1'B0),\n    .sl_oport134_i(1'B0),\n    .sl_oport135_i(1'B0),\n    .sl_oport136_i(1'B0),\n    .sl_oport137_i(1'B0),\n    .sl_oport138_i(1'B0),\n    .sl_oport139_i(1'B0),\n    .sl_oport140_i(1'B0),\n    .sl_oport141_i(1'B0),\n    .sl_oport142_i(1'B0),\n    .sl_oport143_i(1'B0),\n    .sl_oport144_i(1'B0),\n    .sl_oport145_i(1'B0),\n    .sl_oport146_i(1'B0),\n    .sl_oport147_i(1'B0),\n    .sl_oport148_i(1'B0),\n    .sl_oport149_i(1'B0),\n    .sl_oport150_i(1'B0),\n    .sl_oport151_i(1'B0),\n    .sl_oport152_i(1'B0),\n    .sl_oport153_i(1'B0),\n    .sl_oport154_i(1'B0),\n    .sl_oport155_i(1'B0),\n    .sl_oport156_i(1'B0),\n    .sl_oport157_i(1'B0),\n    .sl_oport158_i(1'B0),\n    .sl_oport159_i(1'B0),\n    .sl_oport160_i(1'B0),\n    .sl_oport161_i(1'B0),\n    .sl_oport162_i(1'B0),\n    .sl_oport163_i(1'B0),\n    .sl_oport164_i(1'B0),\n    .sl_oport165_i(1'B0),\n    .sl_oport166_i(1'B0),\n    .sl_oport167_i(1'B0),\n    .sl_oport168_i(1'B0),\n    .sl_oport169_i(1'B0),\n    .sl_oport170_i(1'B0),\n    .sl_oport171_i(1'B0),\n    .sl_oport172_i(1'B0),\n    .sl_oport173_i(1'B0),\n    .sl_oport174_i(1'B0),\n    .sl_oport175_i(1'B0),\n    .sl_oport176_i(1'B0),\n    .sl_oport177_i(1'B0),\n    .sl_oport178_i(1'B0),\n    .sl_oport179_i(1'B0),\n    .sl_oport180_i(1'B0),\n    .sl_oport181_i(1'B0),\n    .sl_oport182_i(1'B0),\n    .sl_oport183_i(1'B0),\n    .sl_oport184_i(1'B0),\n    .sl_oport185_i(1'B0),\n    .sl_oport186_i(1'B0),\n    .sl_oport187_i(1'B0),\n    .sl_oport188_i(1'B0),\n    .sl_oport189_i(1'B0),\n    .sl_oport190_i(1'B0),\n    .sl_oport191_i(1'B0),\n    .sl_oport192_i(1'B0),\n    .sl_oport193_i(1'B0),\n    .sl_oport194_i(1'B0),\n    .sl_oport195_i(1'B0),\n    .sl_oport196_i(1'B0),\n    .sl_oport197_i(1'B0),\n    .sl_oport198_i(1'B0),\n    .sl_oport199_i(1'B0),\n    .sl_oport200_i(1'B0),\n    .sl_oport201_i(1'B0),\n    .sl_oport202_i(1'B0),\n    .sl_oport203_i(1'B0),\n    .sl_oport204_i(1'B0),\n    .sl_oport205_i(1'B0),\n    .sl_oport206_i(1'B0),\n    .sl_oport207_i(1'B0),\n    .sl_oport208_i(1'B0),\n    .sl_oport209_i(1'B0),\n    .sl_oport210_i(1'B0),\n    .sl_oport211_i(1'B0),\n    .sl_oport212_i(1'B0),\n    .sl_oport213_i(1'B0),\n    .sl_oport214_i(1'B0),\n    .sl_oport215_i(1'B0),\n    .sl_oport216_i(1'B0),\n    .sl_oport217_i(1'B0),\n    .sl_oport218_i(1'B0),\n    .sl_oport219_i(1'B0),\n    .sl_oport220_i(1'B0),\n    .sl_oport221_i(1'B0),\n    .sl_oport222_i(1'B0),\n    .sl_oport223_i(1'B0),\n    .sl_oport224_i(1'B0),\n    .sl_oport225_i(1'B0),\n    .sl_oport226_i(1'B0),\n    .sl_oport227_i(1'B0),\n    .sl_oport228_i(1'B0),\n    .sl_oport229_i(1'B0),\n    .sl_oport230_i(1'B0),\n    .sl_oport231_i(1'B0),\n    .sl_oport232_i(1'B0),\n    .sl_oport233_i(1'B0),\n    .sl_oport234_i(1'B0),\n    .sl_oport235_i(1'B0),\n    .sl_oport236_i(1'B0),\n    .sl_oport237_i(1'B0),\n    .sl_oport238_i(1'B0),\n    .sl_oport239_i(1'B0),\n    .sl_oport240_i(1'B0),\n    .sl_oport241_i(1'B0),\n    .sl_oport242_i(1'B0),\n    .sl_oport243_i(1'B0),\n    .sl_oport244_i(1'B0),\n    .sl_oport245_i(1'B0),\n    .sl_oport246_i(1'B0),\n    .sl_oport247_i(1'B0),\n    .sl_oport248_i(1'B0),\n    .sl_oport249_i(1'B0),\n    .sl_oport250_i(1'B0),\n    .sl_oport251_i(1'B0),\n    .sl_oport252_i(1'B0),\n    .sl_oport253_i(1'B0),\n    .sl_oport254_i(1'B0),\n    .sl_oport255_i(1'B0),\n    .update_0(),\n    .capture_0(),\n    .reset_0(),\n    .runtest_0(),\n    .tms_0(),\n    .tck_0(),\n    .tdi_0(),\n    .sel_0(),\n    .shift_0(),\n    .drck_0(),\n    .tdo_0(1'B0),\n    .update_1(),\n    .capture_1(),\n    .reset_1(),\n    .runtest_1(),\n    .tms_1(),\n    .tck_1(),\n    .tdi_1(),\n    .sel_1(),\n    .shift_1(),\n    .drck_1(),\n    .tdo_1(1'B0),\n    .update_2(),\n    .capture_2(),\n    .reset_2(),\n    .runtest_2(),\n    .tms_2(),\n    .tck_2(),\n    .tdi_2(),\n    .sel_2(),\n    .shift_2(),\n    .drck_2(),\n    .tdo_2(1'B0),\n    .update_3(),\n    .capture_3(),\n    .reset_3(),\n    .runtest_3(),\n    .tms_3(),\n    .tck_3(),\n    .tdi_3(),\n    .sel_3(),\n    .shift_3(),\n    .drck_3(),\n    .tdo_3(1'B0),\n    .update_4(),\n    .capture_4(),\n    .reset_4(),\n    .runtest_4(),\n    .tms_4(),\n    .tck_4(),\n    .tdi_4(),\n    .sel_4(),\n    .shift_4(),\n    .drck_4(),\n    .tdo_4(1'B0),\n    .update_5(),\n    .capture_5(),\n    .reset_5(),\n    .runtest_5(),\n    .tms_5(),\n    .tck_5(),\n    .tdi_5(),\n    .sel_5(),\n    .shift_5(),\n    .drck_5(),\n    .tdo_5(1'B0),\n    .update_6(),\n    .capture_6(),\n    .reset_6(),\n    .runtest_6(),\n    .tms_6(),\n    .tck_6(),\n    .tdi_6(),\n    .sel_6(),\n    .shift_6(),\n    .drck_6(),\n    .tdo_6(1'B0),\n    .update_7(),\n    .capture_7(),\n    .reset_7(),\n    .runtest_7(),\n    .tms_7(),\n    .tck_7(),\n    .tdi_7(),\n    .sel_7(),\n    .shift_7(),\n    .drck_7(),\n    .tdo_7(1'B0),\n    .update_8(),\n    .capture_8(),\n    .reset_8(),\n    .runtest_8(),\n    .tms_8(),\n    .tck_8(),\n    .tdi_8(),\n    .sel_8(),\n    .shift_8(),\n    .drck_8(),\n    .tdo_8(1'B0),\n    .update_9(),\n    .capture_9(),\n    .reset_9(),\n    .runtest_9(),\n    .tms_9(),\n    .tck_9(),\n    .tdi_9(),\n    .sel_9(),\n    .shift_9(),\n    .drck_9(),\n    .tdo_9(1'B0),\n    .update_10(),\n    .capture_10(),\n    .reset_10(),\n    .runtest_10(),\n    .tms_10(),\n    .tck_10(),\n    .tdi_10(),\n    .sel_10(),\n    .shift_10(),\n    .drck_10(),\n    .tdo_10(1'B0),\n    .update_11(),\n    .capture_11(),\n    .reset_11(),\n    .runtest_11(),\n    .tms_11(),\n    .tck_11(),\n    .tdi_11(),\n    .sel_11(),\n    .shift_11(),\n    .drck_11(),\n    .tdo_11(1'B0),\n    .update_12(),\n    .capture_12(),\n    .reset_12(),\n    .runtest_12(),\n    .tms_12(),\n    .tck_12(),\n    .tdi_12(),\n    .sel_12(),\n    .shift_12(),\n    .drck_12(),\n    .tdo_12(1'B0),\n    .update_13(),\n    .capture_13(),\n    .reset_13(),\n    .runtest_13(),\n    .tms_13(),\n    .tck_13(),\n    .tdi_13(),\n    .sel_13(),\n    .shift_13(),\n    .drck_13(),\n    .tdo_13(1'B0),\n    .update_14(),\n    .capture_14(),\n    .reset_14(),\n    .runtest_14(),\n    .tms_14(),\n    .tck_14(),\n    .tdi_14(),\n    .sel_14(),\n    .shift_14(),\n    .drck_14(),\n    .tdo_14(1'B0),\n    .update_15(),\n    .capture_15(),\n    .reset_15(),\n    .runtest_15(),\n    .tms_15(),\n    .tck_15(),\n    .tdi_15(),\n    .sel_15(),\n    .shift_15(),\n    .drck_15(),\n    .tdo_15(1'B0),\n    .bscanid_en_0(),\n    .bscanid_en_1(),\n    .bscanid_en_2(),\n    .bscanid_en_3(),\n    .bscanid_en_4(),\n    .bscanid_en_5(),\n    .bscanid_en_6(),\n    .bscanid_en_7(),\n    .bscanid_en_8(),\n    .bscanid_en_9(),\n    .bscanid_en_10(),\n    .bscanid_en_11(),\n    .bscanid_en_12(),\n    .bscanid_en_13(),\n    .bscanid_en_14(),\n    .bscanid_en_15(),\n    .bscanid_0(32'B0),\n    .bscanid_1(32'B0),\n    .bscanid_2(32'B0),\n    .bscanid_3(32'B0),\n    .bscanid_4(32'B0),\n    .bscanid_5(32'B0),\n    .bscanid_6(32'B0),\n    .bscanid_7(32'B0),\n    .bscanid_8(32'B0),\n    .bscanid_9(32'B0),\n    .bscanid_10(32'B0),\n    .bscanid_11(32'B0),\n    .bscanid_12(32'B0),\n    .bscanid_13(32'B0),\n    .bscanid_14(32'B0),\n    .bscanid_15(32'B0),\n    .update(update),\n    .capture(capture),\n    .reset(reset),\n    .runtest(runtest),\n    .tck(tck),\n    .tms(tms),\n    .tdi(tdi),\n    .sel(sel),\n    .shift(shift),\n    .drck(drck),\n    .tdo(tdo),\n    .bscanid_en(bscanid_en),\n    .bscanid(),\n    .clk(clk)\n  );\nendmodule\n", "num_lines": 870}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\ngeSCzw9gYjFCv0Dn0YxOXxhH+GZFMePCQPK3AjT+zbjt1urPphGbRmSIP212qcXhU3u6qBayOOuP\nzGTUOznyYQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nOnCSRn8bnLy+eSxgkIEXKk5zY3JDppSX+6N3lQVX9PeSypgnQ/2z4GTpmoL+rdMoco6U9R4G1u4m\nE0xhKuM4ba9nEk7cLfAxOQqKqsWQrZaIEmzIr1ET+cp4jOMvYA/MsN4jh93kbuKcSDuJ8zN13DFX\nRemIkmekhFjPkyUS5qM=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nMSBAO7tnsBVh2XpVImbQvPkv1Ik+6Bw1D0e9n6H/Bw1mXnRXzm0RzPaEYAIFuluPbWglTrw4pQSr\nJI/DSdCg6087Xmb+Q5zKawFvuZahx4HgmrKxTL15lZwamiIpmu3LGyxaEH/VbYGM9Ky0jp5PyDKU\nJeskyx64XVUPlRklhMjIKCtYITsgROzqjs+d1jIc494zqnDADEz0msJP38WdzHgwLDQ0NamfpodX\nBUqMR71hgPx1Rvdt7HagUbkfyaG3/12LxFvpAblT7W0W6RKBFEFgFrxWRFaDw+jzj4jgl9g+sjY0\ncveJYAA4UpZJwPSDIWehjmS+mOinzlnl8UP7jw==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUtIiSU3lZ1iUKAuaJuT083jLC5QokBuxbJC/zVsWXf8ozOCIDAvtpSufF02lDCCaNNheB40dXQFS\nI8VBcTtdWzNr2vj/HmW17e10D6T6mqn/8t0HnWx9c3modRuXup0Too1mNTU5gTH+v3utogTO5ztm\nHbJZ/+5ov0tPkaeJufJl5L/RZAfLmRnRYybtx5bbc7XiGyWaVk6KunsaWtX5zJtVnMeUOkg0N8oL\nRBeyFp3tFqTN7ecNUp7zom6BjZ3fR6euRy36u1XviJsqBjcxzASI1k+bn2lDs3oEdXuMHoRvcuWL\nmmMddzjwWr43L7YoB/WBz/Tw7t6iYI5B6imPUA==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nAMZ17uwJyVzW4KyzjD/YjCrX2GlLIDwW9HSuEat97pn8ZQ7QpDPhFLNx09klp1fHQ8yb1KlxCqpm\nIjAljp4A5oQHWcBw/s+Xhtpin6GMDGjsmd5KmAD2J5DQmzqPazc0M8vNO+pGpCJogvWarX5XrP6U\n56l9vH5mfyPmbT/09Kw=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\noAGTk8IFmmwAT5eT+h5xMK7MsqYCJnsMll3rq17njNu6wbVX2TAoOlVC5DzNg9T5ce7gVnuLuFG/\nFgNSnTJx8TlbP73KxlDubmAVofR56G/yHzaJfJ0fwNhrfXm5AFgmFaKFPTKNkrG/qjdNuwUeA8p4\niHoj1zvPx50myVHXSpHLQ8n92DLWgMUX/57aPLbMHmYu/gsD0kHOuQ8Fr2Mi2DxufAvq1gzT0kc+\nlxSntoseL+X1HLSvmKpEkR/sjaz6P9omIzqKlmOhvLeTZVEZcUtukVN1HTrlol+4/pTFDztcz0tZ\nXqYZKVNB/igvn1iP/Fej8fpkaeJOrk1YgJZ6xw==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nHM0OWTHTT9qkiqicwldwQlaXCXhAavOkOLtzdsXybVEqcdGTuInS8Xvu2i7fjfGdnZjc+o4ZayFd\nadCXUGMQZ+7u79Rm71DMtV7WL4PMhXZmItLJgXQmNzajU211AuWse/CyD7Am9ZDJuQcIK0fcqZQI\nXVJU6sMESVWiSWdCuqkcQLSuSoBY7TVLmCDoTF9n7MlYfcxCkkK6d+2Xs/gjaWO59GZ3TbWhAQLc\n9hHL9YUJUTzZ8yPC8tX+DLS/YrniD3lBpquxXGcl1FxHKFTSpMG/6pTH+7Y5u1s29iqS/KYCCOfR\nPqg3ikxxR4ywBL+umX+Ijv+Hqgol6tBnCkWh/g==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nDQuK/YuairmUNmnTZFN/Tbbjjk202ciTMNZWiES7z/c8BYrmlnBses/x7XzAVxFxOTns+S6gcbxv\nlho3MoYQI3b1wxR93ymMpbFY2AAKqfTaYrt9nuBi+J66NUkNb4mO5Ysrmk/FyxUuVMw2JeKhCxVf\n1Lkw2weXEA2RSHrWxd8764IFSbBqKoKUTMuqLxHovRaQHDy/mOdyefGG7/6ywGbKjVTlE8lXVH8E\n8QodSYZ7p8uod81sVFzJL26a9Tqu+u2tOgD/WqMuxrio7zRkYYC5P+/FtxLC4GaIZ6LivaJuTLOF\nbkAMneaa5dlfamLnRyzDXUCJu/DFpJtH5s1eLQ==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nDL1JbuaDxIhP8ir0jAdx6nea42/rMQ2VXG8PZEGqMkgF/yLmK8+UcPNvmkEnUbVxq6WNxCUUYBOO\neroUXvKd3hB7aza+lE1PkczDRQpe4dZWQ8yHCUSbqj/KnUKU7sMHOSk5MiYcbBazdC+B/zdSxJsr\nsUmnOLgp/SqygmZW7/oDYMIYyOExEOrIPD4CH/xXZGlvuNs4OjdmaSus7kQp/iaUxQz03NGaMv3/\nEuIfORb3j+mQPwXwEBQhecy81p8ky3bmOS0LK+CPuz0LF3VVvrDnnXUSBCWa2WW6t7burmoHvgPV\noB2jrvwkS6dNjRJ7CoyGvV0N6d60kiD0LjZg6Q==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 2400)\n`pragma protect data_block\nNayj+Ml813fDniWORR2jtIBWLUnTKLU73quUTC0r5jwck/h8GoDq9XKw8BqI5v1J3nTgkNVm5atb\ncAw/VaO3NkhfBheJQbSR69Nrz/dOO5tggQHH5bhiVgkyJ10J0IJijCkqHTEM7eqAUpRB+C+swn77\n0UbAbjpA6iLxZtySLCkfu1IDmIuJVGQQu5gx5HhJOOS9sbBqYLpKFtMkq0ekmdT8uVsJas5Dn/rL\nFK6cI0u3hF6jx7C6EuRP9bts5JinWmopHabvdIuMWogq/jEOmvK/YWa2F6a22JfPI9md2SGv001Z\nNF3S+OFUqWLkWcQuQiK1EeStnUgfx0DKmP44Rh49vAuwvoCnEGtGPoJcuqCj8kkx2HperJBoPMXF\nbwOXyBsVw8smubJpJUklj/jkYQU7Mhn0+1DDK4kkK06W5VS0PwpcHI/NCpCrtst2FFbkesNH2SsO\n5KIGW+Cfb4QrEDe5XavyjtAdc7Kf/olEw1ZvNmIwyZXSdJcT54GFCi4KQPPRS9kiaadQLPQS/WUP\nwP3P3JdX9YvFC5Sp1yq2sPWuL1eMLRyNl339wIhus+/wM5aQSDi/pHmJmMEl1YLUa+mN6EenORTG\n5MU9xnSDDk5SD4ObbT9KWXjRTWogMOCapY1Tv1MWBzOTNzXGtVtAJBw4cxOHMG+OFF0yGvhE/AiV\nUJBEeJzP8L2Bj71c8RCxIViFz07rXhaFlBxMGxkdgTscOVxJtGiXqO970qc+E+YhnpZrgzpPog3A\nHIxK9BG2bcC2sSeQO+WCrtfMMdvVUNZHntYQpZozeGZF5OTZeeqs2I0PvZblmP7/srlzJ/JzetZ0\nCpTygxJF6W9HlXHv9qS2in1MDX5LvPjFtN0zKGyxUv4X8CFSqcYRW0lPxKh8dQ8KfIf1/+JRuMUW\nCO3I17UAoMQyc5PLA35Nis/x1CGOS2Zq5QgnlIBPpFv5JGoS0wKJ/bIyq0i0w+v4KWN5TrLYWJ84\nsMf45/+/nnmUoNq90k8SrWlnr9pxaqXZeklZOtEGejWc0oYa3+O2lYV0522Cm+XAuCiLIx1oRyxa\n+u6HnsKXvR9DGb1osgt9gANalMh//k8N88W7tvMLcXwdkFi3uvBg/oZZeRm+o8p5swkqfDh2gQuZ\nGJ1QE8KWN8hTZ9fEsScunk4GbuTk3dg05a1sMGm1gkRzTfiEVCzyn5Hi3pFpbikjAO7g/FLU6yiZ\npKzI2Crm4XPWRCfhwxycS8r2s63JspfJUZBW7tfCcbmQHYqHgxL3ZiEIV4N4tCF6rLQe8eu8xVI4\n/ReaCvAsFB9k7r6h7vh2b/kor3j4v+vAAZs3NBd5vlKFfHc3a2phzTdGn9/IodWpqPp66h+D0hMB\n8NQHJ3785F0Znfee4XxCQdXvwh03Pq+vWOHfhxdV+GL/oYI5/3eX0cZlwNXNhgrBE/jjCvh+/qf+\nEuYKKMASHjIYzBihs/pCIBjKCya9eF6CKxRfp3KTjZ2nu0k/P00aR1alNLtPJR6SD3wEBMa7yNgY\nByaV1EQovQeu24Klh9zavCXFUHc3h3j8MqHxZrNfI/eUyIDoEuURBHymJZ13GIYA+mWIFdrXIC84\nSlX5spcjNcB+mHif2EzCB6nJP3AE9aq8cpOJcQjhkcPZHkg2t9l5F5EupuAFUvvfcTXN/y6F3qIr\nThqLyFGwSiGzZX0AwRaNpyXuZKQsNz1WTzj1BjvDSTF1//OlAgzx0F1UZOuh9Hzv4+IBl0yGCHiR\noGXeQvMTSxI1D0BcFoc61ga1nbv3+QY2aYafMEJ+LKq2sz3mGk0Vpzo+swUVCYeveAb11ugkLVq9\nRa5FHeyN5v+RwxysgCDPo+jBUyzguryY6OBJBtBUXJV3Vrg8TEC1JNfIuiaQGmXiWvUj7VD3fgFP\nA/Pax3F+Unn9dJaEhfgG23dLGZyo/H32CTtiWZfkWBJV8/W3g040xdKdNl+Y7sBtjuGt0IdS8lWJ\nbomc8CybMXpVp9SQkhVlf4135WYYZuozj6Kt0dv581TbcnOPMEkTrRnU/XCQOVj9mHD8kDE8BGPs\nu1WPZBZQ1Tfgb5SDwQQf3XYTIQNAnDzjLrEPaxy7I36CFdPTpJXR+DrTmbYH416q/LusHMxfzhkE\nw+OkHqm6czWhunOkfPBoECoA9j609E2s6JDyqqdyNGGw3KsGIu3zyudgD+AeIlbr5wvld3VhQu+k\nGbD1GKPT9sOuQylU6aG0R75sAjP0/RSbLUhGUdAL1NeNa2Q5utBg4b7xY2znf8k43uQuH9gDftQK\nMoCj+4M/kY5vFOehA+mgPmocoo8+ta7JVcwiLjJPyYN/N7RIRvu0bpPfTeQM+6DijB5NSetCHZeW\nKLrP7l1+niGT/aEUEZej5w42fhW5sZHSiMRrLyLeDxPtaeUE82Q8OzcJqmXqsrFMkgyVYOS6vWRE\np8+5qxoxSzeQ36exOktW+E2/pJPFVJYv608U/e/KsJ18RpOpuwdPQeazasQl0zwh9u34LrhV6Hgs\nG8DKy0o62/rCo+JVEb1RdF37hXvTDGFF//rlcyBQgVtwCOJFFL5geugUbu5A/8AzBEN9Pzw0vxPV\nfUaRNNckCcVybD5F7BZ3ielbt42QOneOK6+07rP2GQq6wu4Kocbpi5WXkAwDwn9iEsJT6Vh3Xz9A\nGjEIelxMlGde1Ett9oxHhKcMYEnPyv4evAmG7EErwlTCQd+vp8tPPTmVvXbIJEpz4ViA5GiW8eTI\nk/BkHd7IGq64iYXdddJ63IxopIFrccFbADHVy2LXr73bfFWYkRzvShUlQXRs2nK8iLqkmlEeNa8u\nxaG3JQj0CYQCzTlqrKFs7AK8b8BwqaXmZ3FB9Xfj65H3mkW01gIq4i7sdVBBe4FgjsQAPdA+QPyP\nFymbOZEQQPblH3qHCFfiQ9DDi/zDZi26sar4BjLeoS6GuI2juEmSKZLMcHezPShGjMq7TDo25lD6\nlTlVWv5FmEIE4aI6UTNu4lJ3xl7a4lWJea95qzcitsplCEQA3mhp4zu9euRzSrneC01njKmDnrPH\nmqzSlSiWOcwitRn6BFaIcXktL6gU0l0wbOKHkv4u6Wd4kbpRfHuZGrrcUU9JHlIQn9e7Rhx3a8Le\nWewZ4FHJqc4gDvS+d8JPbCOb0K5VOINAjyn78G8320oCOfCyv3IKlkmyNHvqFcKzpNFcaza/1v/w\nwP46e8ZI\n`pragma protect end_protected\n", "num_lines": 126}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:lut_buffer:2.0\n// IP Revision: 0\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_a493_lut_buffer_0 (\n  tdi_i,\n  tms_i,\n  tck_i,\n  drck_i,\n  sel_i,\n  shift_i,\n  update_i,\n  capture_i,\n  runtest_i,\n  reset_i,\n  bscanid_en_i,\n  tdo_o,\n  tdi_o,\n  tms_o,\n  tck_o,\n  drck_o,\n  sel_o,\n  shift_o,\n  update_o,\n  capture_o,\n  runtest_o,\n  reset_o,\n  bscanid_en_o,\n  tdo_i\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDI\" *)\ninput wire tdi_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TMS\" *)\ninput wire tms_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TCK\" *)\ninput wire tck_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan DRCK\" *)\ninput wire drck_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SEL\" *)\ninput wire sel_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SHIFT\" *)\ninput wire shift_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan UPDATE\" *)\ninput wire update_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan CAPTURE\" *)\ninput wire capture_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RUNTEST\" *)\ninput wire runtest_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RESET\" *)\ninput wire reset_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan BSCANID_EN\" *)\ninput wire bscanid_en_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDO\" *)\noutput wire tdo_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TDI\" *)\noutput wire tdi_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TMS\" *)\noutput wire tms_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TCK\" *)\noutput wire tck_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan DRCK\" *)\noutput wire drck_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan SEL\" *)\noutput wire sel_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan SHIFT\" *)\noutput wire shift_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan UPDATE\" *)\noutput wire update_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan CAPTURE\" *)\noutput wire capture_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan RUNTEST\" *)\noutput wire runtest_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan RESET\" *)\noutput wire reset_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan BSCANID_EN\" *)\noutput wire bscanid_en_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TDO\" *)\ninput wire tdo_i;\n\n  lut_buffer_v2_0_0_lut_buffer #(\n    .C_EN_BSCANID_VEC(0)\n  ) inst (\n    .tdi_i(tdi_i),\n    .tms_i(tms_i),\n    .tck_i(tck_i),\n    .drck_i(drck_i),\n    .sel_i(sel_i),\n    .shift_i(shift_i),\n    .update_i(update_i),\n    .capture_i(capture_i),\n    .runtest_i(runtest_i),\n    .reset_i(reset_i),\n    .bscanid_en_i(bscanid_en_i),\n    .tdo_o(tdo_o),\n    .bscanid_o(),\n    .tdi_o(tdi_o),\n    .tms_o(tms_o),\n    .tck_o(tck_o),\n    .drck_o(drck_o),\n    .sel_o(sel_o),\n    .shift_o(shift_o),\n    .update_o(update_o),\n    .capture_o(capture_o),\n    .runtest_o(runtest_o),\n    .reset_o(reset_o),\n    .bscanid_en_o(bscanid_en_o),\n    .tdo_i(tdo_i),\n    .bscanid_i(32'B0)\n  );\nendmodule\n", "num_lines": 163}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:lut_buffer:2.0\n// IP Revision: 0\n\n(* X_CORE_INFO = \"lut_buffer_v2_0_0_lut_buffer,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"bd_a493_lut_buffer_0,lut_buffer_v2_0_0_lut_buffer,{}\" *)\n(* CORE_GENERATION_INFO = \"bd_a493_lut_buffer_0,lut_buffer_v2_0_0_lut_buffer,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lut_buffer,x_ipVersion=2.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_BSCANID_VEC=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_a493_lut_buffer_0 (\n  tdi_i,\n  tms_i,\n  tck_i,\n  drck_i,\n  sel_i,\n  shift_i,\n  update_i,\n  capture_i,\n  runtest_i,\n  reset_i,\n  bscanid_en_i,\n  tdo_o,\n  tdi_o,\n  tms_o,\n  tck_o,\n  drck_o,\n  sel_o,\n  shift_o,\n  update_o,\n  capture_o,\n  runtest_o,\n  reset_o,\n  bscanid_en_o,\n  tdo_i\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDI\" *)\ninput wire tdi_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TMS\" *)\ninput wire tms_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TCK\" *)\ninput wire tck_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan DRCK\" *)\ninput wire drck_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SEL\" *)\ninput wire sel_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan SHIFT\" *)\ninput wire shift_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan UPDATE\" *)\ninput wire update_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan CAPTURE\" *)\ninput wire capture_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RUNTEST\" *)\ninput wire runtest_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan RESET\" *)\ninput wire reset_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan BSCANID_EN\" *)\ninput wire bscanid_en_i;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 s_bscan TDO\" *)\noutput wire tdo_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TDI\" *)\noutput wire tdi_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TMS\" *)\noutput wire tms_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TCK\" *)\noutput wire tck_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan DRCK\" *)\noutput wire drck_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan SEL\" *)\noutput wire sel_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan SHIFT\" *)\noutput wire shift_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan UPDATE\" *)\noutput wire update_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan CAPTURE\" *)\noutput wire capture_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan RUNTEST\" *)\noutput wire runtest_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan RESET\" *)\noutput wire reset_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan BSCANID_EN\" *)\noutput wire bscanid_en_o;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 m_bscan TDO\" *)\ninput wire tdo_i;\n\n  lut_buffer_v2_0_0_lut_buffer #(\n    .C_EN_BSCANID_VEC(0)\n  ) inst (\n    .tdi_i(tdi_i),\n    .tms_i(tms_i),\n    .tck_i(tck_i),\n    .drck_i(drck_i),\n    .sel_i(sel_i),\n    .shift_i(shift_i),\n    .update_i(update_i),\n    .capture_i(capture_i),\n    .runtest_i(runtest_i),\n    .reset_i(reset_i),\n    .bscanid_en_i(bscanid_en_i),\n    .tdo_o(tdo_o),\n    .bscanid_o(),\n    .tdi_o(tdi_o),\n    .tms_o(tms_o),\n    .tck_o(tck_o),\n    .drck_o(drck_o),\n    .sel_o(sel_o),\n    .shift_o(shift_o),\n    .update_o(update_o),\n    .capture_o(capture_o),\n    .runtest_o(runtest_o),\n    .reset_o(reset_o),\n    .bscanid_en_o(bscanid_en_o),\n    .tdo_i(tdo_i),\n    .bscanid_i(32'B0)\n  );\nendmodule\n", "num_lines": 164}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_a493.bd\n//Design : bd_a493\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_a493,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_a493,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}\" *) (* HW_HANDOFF = \"cl_debug_bridge.hwdef\" *) \nmodule bd_a493\n   (S_BSCAN_bscanid_en,\n    S_BSCAN_capture,\n    S_BSCAN_drck,\n    S_BSCAN_reset,\n    S_BSCAN_runtest,\n    S_BSCAN_sel,\n    S_BSCAN_shift,\n    S_BSCAN_tck,\n    S_BSCAN_tdi,\n    S_BSCAN_tdo,\n    S_BSCAN_tms,\n    S_BSCAN_update,\n    clk);\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN BSCANID_EN\" *) input S_BSCAN_bscanid_en;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN CAPTURE\" *) input S_BSCAN_capture;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN DRCK\" *) input S_BSCAN_drck;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RESET\" *) input S_BSCAN_reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RUNTEST\" *) input S_BSCAN_runtest;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SEL\" *) input S_BSCAN_sel;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SHIFT\" *) input S_BSCAN_shift;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TCK\" *) input S_BSCAN_tck;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDI\" *) input S_BSCAN_tdi;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDO\" *) output S_BSCAN_tdo;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TMS\" *) input S_BSCAN_tms;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN UPDATE\" *) input S_BSCAN_update;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, CLK_DOMAIN bd_a493_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input clk;\n\n  wire S_BSCAN_1_BSCANID_EN;\n  wire S_BSCAN_1_CAPTURE;\n  wire S_BSCAN_1_DRCK;\n  wire S_BSCAN_1_RESET;\n  wire S_BSCAN_1_RUNTEST;\n  wire S_BSCAN_1_SEL;\n  wire S_BSCAN_1_SHIFT;\n  wire S_BSCAN_1_TCK;\n  wire S_BSCAN_1_TDI;\n  wire S_BSCAN_1_TDO;\n  wire S_BSCAN_1_TMS;\n  wire S_BSCAN_1_UPDATE;\n  wire clk_1;\n  wire lut_buffer_m_bscan_BSCANID_EN;\n  wire lut_buffer_m_bscan_CAPTURE;\n  wire lut_buffer_m_bscan_DRCK;\n  wire lut_buffer_m_bscan_RESET;\n  wire lut_buffer_m_bscan_RUNTEST;\n  wire lut_buffer_m_bscan_SEL;\n  wire lut_buffer_m_bscan_SHIFT;\n  wire lut_buffer_m_bscan_TCK;\n  wire lut_buffer_m_bscan_TDI;\n  wire lut_buffer_m_bscan_TDO;\n  wire lut_buffer_m_bscan_TMS;\n  wire lut_buffer_m_bscan_UPDATE;\n\n  assign S_BSCAN_1_BSCANID_EN = S_BSCAN_bscanid_en;\n  assign S_BSCAN_1_CAPTURE = S_BSCAN_capture;\n  assign S_BSCAN_1_DRCK = S_BSCAN_drck;\n  assign S_BSCAN_1_RESET = S_BSCAN_reset;\n  assign S_BSCAN_1_RUNTEST = S_BSCAN_runtest;\n  assign S_BSCAN_1_SEL = S_BSCAN_sel;\n  assign S_BSCAN_1_SHIFT = S_BSCAN_shift;\n  assign S_BSCAN_1_TCK = S_BSCAN_tck;\n  assign S_BSCAN_1_TDI = S_BSCAN_tdi;\n  assign S_BSCAN_1_TMS = S_BSCAN_tms;\n  assign S_BSCAN_1_UPDATE = S_BSCAN_update;\n  assign S_BSCAN_tdo = S_BSCAN_1_TDO;\n  assign clk_1 = clk;\n  bd_a493_lut_buffer_0 lut_buffer\n       (.bscanid_en_i(S_BSCAN_1_BSCANID_EN),\n        .bscanid_en_o(lut_buffer_m_bscan_BSCANID_EN),\n        .capture_i(S_BSCAN_1_CAPTURE),\n        .capture_o(lut_buffer_m_bscan_CAPTURE),\n        .drck_i(S_BSCAN_1_DRCK),\n        .drck_o(lut_buffer_m_bscan_DRCK),\n        .reset_i(S_BSCAN_1_RESET),\n        .reset_o(lut_buffer_m_bscan_RESET),\n        .runtest_i(S_BSCAN_1_RUNTEST),\n        .runtest_o(lut_buffer_m_bscan_RUNTEST),\n        .sel_i(S_BSCAN_1_SEL),\n        .sel_o(lut_buffer_m_bscan_SEL),\n        .shift_i(S_BSCAN_1_SHIFT),\n        .shift_o(lut_buffer_m_bscan_SHIFT),\n        .tck_i(S_BSCAN_1_TCK),\n        .tck_o(lut_buffer_m_bscan_TCK),\n        .tdi_i(S_BSCAN_1_TDI),\n        .tdi_o(lut_buffer_m_bscan_TDI),\n        .tdo_i(lut_buffer_m_bscan_TDO),\n        .tdo_o(S_BSCAN_1_TDO),\n        .tms_i(S_BSCAN_1_TMS),\n        .tms_o(lut_buffer_m_bscan_TMS),\n        .update_i(S_BSCAN_1_UPDATE),\n        .update_o(lut_buffer_m_bscan_UPDATE));\n  bd_a493_xsdbm_0 xsdbm\n       (.bscanid_en(lut_buffer_m_bscan_BSCANID_EN),\n        .capture(lut_buffer_m_bscan_CAPTURE),\n        .clk(clk_1),\n        .drck(lut_buffer_m_bscan_DRCK),\n        .reset(lut_buffer_m_bscan_RESET),\n        .runtest(lut_buffer_m_bscan_RUNTEST),\n        .sel(lut_buffer_m_bscan_SEL),\n        .shift(lut_buffer_m_bscan_SHIFT),\n        .tck(lut_buffer_m_bscan_TCK),\n        .tdi(lut_buffer_m_bscan_TDI),\n        .tdo(lut_buffer_m_bscan_TDO),\n        .tms(lut_buffer_m_bscan_TMS),\n        .update(lut_buffer_m_bscan_UPDATE));\nendmodule\n", "num_lines": 117}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_a493.bd\n//Design : bd_a493\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_a493,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_a493,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}\" *) (* HW_HANDOFF = \"cl_debug_bridge.hwdef\" *) \nmodule bd_a493\n   (S_BSCAN_bscanid_en,\n    S_BSCAN_capture,\n    S_BSCAN_drck,\n    S_BSCAN_reset,\n    S_BSCAN_runtest,\n    S_BSCAN_sel,\n    S_BSCAN_shift,\n    S_BSCAN_tck,\n    S_BSCAN_tdi,\n    S_BSCAN_tdo,\n    S_BSCAN_tms,\n    S_BSCAN_update,\n    clk);\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN BSCANID_EN\" *) input S_BSCAN_bscanid_en;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN CAPTURE\" *) input S_BSCAN_capture;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN DRCK\" *) input S_BSCAN_drck;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RESET\" *) input S_BSCAN_reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RUNTEST\" *) input S_BSCAN_runtest;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SEL\" *) input S_BSCAN_sel;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SHIFT\" *) input S_BSCAN_shift;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TCK\" *) input S_BSCAN_tck;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDI\" *) input S_BSCAN_tdi;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDO\" *) output S_BSCAN_tdo;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TMS\" *) input S_BSCAN_tms;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN UPDATE\" *) input S_BSCAN_update;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, CLK_DOMAIN bd_a493_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input clk;\n\n  wire S_BSCAN_1_BSCANID_EN;\n  wire S_BSCAN_1_CAPTURE;\n  wire S_BSCAN_1_DRCK;\n  wire S_BSCAN_1_RESET;\n  wire S_BSCAN_1_RUNTEST;\n  wire S_BSCAN_1_SEL;\n  wire S_BSCAN_1_SHIFT;\n  wire S_BSCAN_1_TCK;\n  wire S_BSCAN_1_TDI;\n  wire S_BSCAN_1_TDO;\n  wire S_BSCAN_1_TMS;\n  wire S_BSCAN_1_UPDATE;\n  wire clk_1;\n  wire lut_buffer_m_bscan_BSCANID_EN;\n  wire lut_buffer_m_bscan_CAPTURE;\n  wire lut_buffer_m_bscan_DRCK;\n  wire lut_buffer_m_bscan_RESET;\n  wire lut_buffer_m_bscan_RUNTEST;\n  wire lut_buffer_m_bscan_SEL;\n  wire lut_buffer_m_bscan_SHIFT;\n  wire lut_buffer_m_bscan_TCK;\n  wire lut_buffer_m_bscan_TDI;\n  wire lut_buffer_m_bscan_TDO;\n  wire lut_buffer_m_bscan_TMS;\n  wire lut_buffer_m_bscan_UPDATE;\n\n  assign S_BSCAN_1_BSCANID_EN = S_BSCAN_bscanid_en;\n  assign S_BSCAN_1_CAPTURE = S_BSCAN_capture;\n  assign S_BSCAN_1_DRCK = S_BSCAN_drck;\n  assign S_BSCAN_1_RESET = S_BSCAN_reset;\n  assign S_BSCAN_1_RUNTEST = S_BSCAN_runtest;\n  assign S_BSCAN_1_SEL = S_BSCAN_sel;\n  assign S_BSCAN_1_SHIFT = S_BSCAN_shift;\n  assign S_BSCAN_1_TCK = S_BSCAN_tck;\n  assign S_BSCAN_1_TDI = S_BSCAN_tdi;\n  assign S_BSCAN_1_TMS = S_BSCAN_tms;\n  assign S_BSCAN_1_UPDATE = S_BSCAN_update;\n  assign S_BSCAN_tdo = S_BSCAN_1_TDO;\n  assign clk_1 = clk;\n  bd_a493_lut_buffer_0 lut_buffer\n       (.bscanid_en_i(S_BSCAN_1_BSCANID_EN),\n        .bscanid_en_o(lut_buffer_m_bscan_BSCANID_EN),\n        .capture_i(S_BSCAN_1_CAPTURE),\n        .capture_o(lut_buffer_m_bscan_CAPTURE),\n        .drck_i(S_BSCAN_1_DRCK),\n        .drck_o(lut_buffer_m_bscan_DRCK),\n        .reset_i(S_BSCAN_1_RESET),\n        .reset_o(lut_buffer_m_bscan_RESET),\n        .runtest_i(S_BSCAN_1_RUNTEST),\n        .runtest_o(lut_buffer_m_bscan_RUNTEST),\n        .sel_i(S_BSCAN_1_SEL),\n        .sel_o(lut_buffer_m_bscan_SEL),\n        .shift_i(S_BSCAN_1_SHIFT),\n        .shift_o(lut_buffer_m_bscan_SHIFT),\n        .tck_i(S_BSCAN_1_TCK),\n        .tck_o(lut_buffer_m_bscan_TCK),\n        .tdi_i(S_BSCAN_1_TDI),\n        .tdi_o(lut_buffer_m_bscan_TDI),\n        .tdo_i(lut_buffer_m_bscan_TDO),\n        .tdo_o(S_BSCAN_1_TDO),\n        .tms_i(S_BSCAN_1_TMS),\n        .tms_o(lut_buffer_m_bscan_TMS),\n        .update_i(S_BSCAN_1_UPDATE),\n        .update_o(lut_buffer_m_bscan_UPDATE));\n  bd_a493_xsdbm_0 xsdbm\n       (.bscanid_en(lut_buffer_m_bscan_BSCANID_EN),\n        .capture(lut_buffer_m_bscan_CAPTURE),\n        .clk(clk_1),\n        .drck(lut_buffer_m_bscan_DRCK),\n        .reset(lut_buffer_m_bscan_RESET),\n        .runtest(lut_buffer_m_bscan_RUNTEST),\n        .sel(lut_buffer_m_bscan_SEL),\n        .shift(lut_buffer_m_bscan_SHIFT),\n        .tck(lut_buffer_m_bscan_TCK),\n        .tdi(lut_buffer_m_bscan_TDI),\n        .tdo(lut_buffer_m_bscan_TDO),\n        .tms(lut_buffer_m_bscan_TMS),\n        .update(lut_buffer_m_bscan_UPDATE));\nendmodule\n", "num_lines": 117}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:debug_bridge:3.0\n// IP Revision: 6\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_debug_bridge (\n  clk,\n  S_BSCAN_bscanid_en,\n  S_BSCAN_capture,\n  S_BSCAN_drck,\n  S_BSCAN_reset,\n  S_BSCAN_runtest,\n  S_BSCAN_sel,\n  S_BSCAN_shift,\n  S_BSCAN_tck,\n  S_BSCAN_tdi,\n  S_BSCAN_tdo,\n  S_BSCAN_tms,\n  S_BSCAN_update\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_a493_clk, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.clk CLK\" *)\ninput wire clk;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN BSCANID_EN\" *)\ninput wire S_BSCAN_bscanid_en;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN CAPTURE\" *)\ninput wire S_BSCAN_capture;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN DRCK\" *)\ninput wire S_BSCAN_drck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RESET\" *)\ninput wire S_BSCAN_reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RUNTEST\" *)\ninput wire S_BSCAN_runtest;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SEL\" *)\ninput wire S_BSCAN_sel;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SHIFT\" *)\ninput wire S_BSCAN_shift;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TCK\" *)\ninput wire S_BSCAN_tck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDI\" *)\ninput wire S_BSCAN_tdi;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDO\" *)\noutput wire S_BSCAN_tdo;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TMS\" *)\ninput wire S_BSCAN_tms;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN UPDATE\" *)\ninput wire S_BSCAN_update;\n\n  bd_a493 inst (\n    .clk(clk),\n    .S_BSCAN_bscanid_en(S_BSCAN_bscanid_en),\n    .S_BSCAN_capture(S_BSCAN_capture),\n    .S_BSCAN_drck(S_BSCAN_drck),\n    .S_BSCAN_reset(S_BSCAN_reset),\n    .S_BSCAN_runtest(S_BSCAN_runtest),\n    .S_BSCAN_sel(S_BSCAN_sel),\n    .S_BSCAN_shift(S_BSCAN_shift),\n    .S_BSCAN_tck(S_BSCAN_tck),\n    .S_BSCAN_tdi(S_BSCAN_tdi),\n    .S_BSCAN_tdo(S_BSCAN_tdo),\n    .S_BSCAN_tms(S_BSCAN_tms),\n    .S_BSCAN_update(S_BSCAN_update)\n  );\nendmodule\n", "num_lines": 116}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:debug_bridge:3.0\n// IP Revision: 6\n\n(* X_CORE_INFO = \"bd_a493,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"cl_debug_bridge,bd_a493,{}\" *)\n(* CORE_GENERATION_INFO = \"cl_debug_bridge,bd_a493,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=debug_bridge,x_ipVersion=3.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_DEBUG_MODE=1,C_NUM_BS_MASTER=0,C_BSCAN_MUX=1,C_EN_BSCANID_VEC=false,C_USE_EXT_BSCAN=true,C_USE_STARTUP_CLK=false,C_ENABLE_CLK_DIVIDER=false,C_TWO_PRIM_MODE=false,C_USER_SCAN_CHAIN=1,C_CORE_TYPE=1,C_EN_INT_SIM=1,C_DCLK_HAS_RESET=0,C_USE_BUFR=0,C_XSDB_NUM_SLAVES=0,C_CORE_MINOR_ALPHA_VER=97,C_CORE_MINOR_VER=0,C_\\\nCORE_MAJOR_VER=1,C_BUILD_REVISION=0,C_MINOR_VERSION=1,C_MAJOR_VERSION=14,C_FIFO_STYLE=SUBCORE,C_DESIGN_TYPE=0,C_MASTER_INTF_TYPE=1,C_EN_PASSTHROUGH=0,C_XVC_HW_ID=0x0001,C_XVC_SW_ID=0x0001,C_PCIE_EXT_CFG_BASE_ADDR=0x400,C_PCIE_EXT_CFG_VSEC_REV_ID=0x0,C_PCIE_EXT_CFG_VSEC_LENGTH=0x020,C_PCIE_EXT_CFG_NEXT_PTR=0x000,C_PCIE_EXT_CFG_VSEC_ID=0x0008,Component_Name=cl_debug_bridge,C_CLK_INPUT_FREQ_HZ=300000000,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ADDR_WIDTH=5,C_TCK_CLOCK_RATIO=8,C_USE_SOFTBSCAN=1,C_DEVICE_FAMILY\\\n=0,C_IR_WIDTH=0,C_CHIP_ID=0,C_IR_ID_INSTR=0,C_IR_USER1_INSTR=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_debug_bridge (\n  clk,\n  S_BSCAN_bscanid_en,\n  S_BSCAN_capture,\n  S_BSCAN_drck,\n  S_BSCAN_reset,\n  S_BSCAN_runtest,\n  S_BSCAN_sel,\n  S_BSCAN_shift,\n  S_BSCAN_tck,\n  S_BSCAN_tdi,\n  S_BSCAN_tdo,\n  S_BSCAN_tms,\n  S_BSCAN_update\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_a493_clk, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.clk CLK\" *)\ninput wire clk;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN BSCANID_EN\" *)\ninput wire S_BSCAN_bscanid_en;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN CAPTURE\" *)\ninput wire S_BSCAN_capture;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN DRCK\" *)\ninput wire S_BSCAN_drck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RESET\" *)\ninput wire S_BSCAN_reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN RUNTEST\" *)\ninput wire S_BSCAN_runtest;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SEL\" *)\ninput wire S_BSCAN_sel;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN SHIFT\" *)\ninput wire S_BSCAN_shift;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TCK\" *)\ninput wire S_BSCAN_tck;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDI\" *)\ninput wire S_BSCAN_tdi;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TDO\" *)\noutput wire S_BSCAN_tdo;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN TMS\" *)\ninput wire S_BSCAN_tms;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bscan:1.0 S_BSCAN UPDATE\" *)\ninput wire S_BSCAN_update;\n\n  bd_a493 inst (\n    .clk(clk),\n    .S_BSCAN_bscanid_en(S_BSCAN_bscanid_en),\n    .S_BSCAN_capture(S_BSCAN_capture),\n    .S_BSCAN_drck(S_BSCAN_drck),\n    .S_BSCAN_reset(S_BSCAN_reset),\n    .S_BSCAN_runtest(S_BSCAN_runtest),\n    .S_BSCAN_sel(S_BSCAN_sel),\n    .S_BSCAN_shift(S_BSCAN_shift),\n    .S_BSCAN_tck(S_BSCAN_tck),\n    .S_BSCAN_tdi(S_BSCAN_tdi),\n    .S_BSCAN_tdo(S_BSCAN_tdo),\n    .S_BSCAN_tms(S_BSCAN_tms),\n    .S_BSCAN_update(S_BSCAN_update)\n  );\nendmodule\n", "num_lines": 119}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_bf3f_wrapper.bd\n//Design : bd_bf3f_wrapper\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule bd_bf3f_wrapper\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  input Clk;\n  output IO_addr_strobe;\n  output [31:0]IO_address;\n  output [3:0]IO_byte_enable;\n  input [31:0]IO_read_data;\n  output IO_read_strobe;\n  input IO_ready;\n  output [31:0]IO_write_data;\n  output IO_write_strobe;\n  input Reset;\n  output TRACE_data_access;\n  output [0:31]TRACE_data_address;\n  output [0:3]TRACE_data_byte_enable;\n  output TRACE_data_read;\n  output TRACE_data_write;\n  output [0:31]TRACE_data_write_value;\n  output TRACE_dcache_hit;\n  output TRACE_dcache_rdy;\n  output TRACE_dcache_read;\n  output TRACE_dcache_req;\n  output TRACE_delay_slot;\n  output TRACE_ex_piperun;\n  output [0:4]TRACE_exception_kind;\n  output TRACE_exception_taken;\n  output TRACE_icache_hit;\n  output TRACE_icache_rdy;\n  output TRACE_icache_req;\n  output [0:31]TRACE_instruction;\n  output TRACE_jump_hit;\n  output TRACE_jump_taken;\n  output TRACE_mb_halted;\n  output TRACE_mem_piperun;\n  output [0:14]TRACE_msr_reg;\n  output [0:31]TRACE_new_reg_value;\n  output TRACE_of_piperun;\n  output [0:31]TRACE_pc;\n  output [0:7]TRACE_pid_reg;\n  output [0:4]TRACE_reg_addr;\n  output TRACE_reg_write;\n  output TRACE_valid_instr;\n\n  wire Clk;\n  wire IO_addr_strobe;\n  wire [31:0]IO_address;\n  wire [3:0]IO_byte_enable;\n  wire [31:0]IO_read_data;\n  wire IO_read_strobe;\n  wire IO_ready;\n  wire [31:0]IO_write_data;\n  wire IO_write_strobe;\n  wire Reset;\n  wire TRACE_data_access;\n  wire [0:31]TRACE_data_address;\n  wire [0:3]TRACE_data_byte_enable;\n  wire TRACE_data_read;\n  wire TRACE_data_write;\n  wire [0:31]TRACE_data_write_value;\n  wire TRACE_dcache_hit;\n  wire TRACE_dcache_rdy;\n  wire TRACE_dcache_read;\n  wire TRACE_dcache_req;\n  wire TRACE_delay_slot;\n  wire TRACE_ex_piperun;\n  wire [0:4]TRACE_exception_kind;\n  wire TRACE_exception_taken;\n  wire TRACE_icache_hit;\n  wire TRACE_icache_rdy;\n  wire TRACE_icache_req;\n  wire [0:31]TRACE_instruction;\n  wire TRACE_jump_hit;\n  wire TRACE_jump_taken;\n  wire TRACE_mb_halted;\n  wire TRACE_mem_piperun;\n  wire [0:14]TRACE_msr_reg;\n  wire [0:31]TRACE_new_reg_value;\n  wire TRACE_of_piperun;\n  wire [0:31]TRACE_pc;\n  wire [0:7]TRACE_pid_reg;\n  wire [0:4]TRACE_reg_addr;\n  wire TRACE_reg_write;\n  wire TRACE_valid_instr;\n\n  bd_bf3f bd_bf3f_i\n       (.Clk(Clk),\n        .IO_addr_strobe(IO_addr_strobe),\n        .IO_address(IO_address),\n        .IO_byte_enable(IO_byte_enable),\n        .IO_read_data(IO_read_data),\n        .IO_read_strobe(IO_read_strobe),\n        .IO_ready(IO_ready),\n        .IO_write_data(IO_write_data),\n        .IO_write_strobe(IO_write_strobe),\n        .Reset(Reset),\n        .TRACE_data_access(TRACE_data_access),\n        .TRACE_data_address(TRACE_data_address),\n        .TRACE_data_byte_enable(TRACE_data_byte_enable),\n        .TRACE_data_read(TRACE_data_read),\n        .TRACE_data_write(TRACE_data_write),\n        .TRACE_data_write_value(TRACE_data_write_value),\n        .TRACE_dcache_hit(TRACE_dcache_hit),\n        .TRACE_dcache_rdy(TRACE_dcache_rdy),\n        .TRACE_dcache_read(TRACE_dcache_read),\n        .TRACE_dcache_req(TRACE_dcache_req),\n        .TRACE_delay_slot(TRACE_delay_slot),\n        .TRACE_ex_piperun(TRACE_ex_piperun),\n        .TRACE_exception_kind(TRACE_exception_kind),\n        .TRACE_exception_taken(TRACE_exception_taken),\n        .TRACE_icache_hit(TRACE_icache_hit),\n        .TRACE_icache_rdy(TRACE_icache_rdy),\n        .TRACE_icache_req(TRACE_icache_req),\n        .TRACE_instruction(TRACE_instruction),\n        .TRACE_jump_hit(TRACE_jump_hit),\n        .TRACE_jump_taken(TRACE_jump_taken),\n        .TRACE_mb_halted(TRACE_mb_halted),\n        .TRACE_mem_piperun(TRACE_mem_piperun),\n        .TRACE_msr_reg(TRACE_msr_reg),\n        .TRACE_new_reg_value(TRACE_new_reg_value),\n        .TRACE_of_piperun(TRACE_of_piperun),\n        .TRACE_pc(TRACE_pc),\n        .TRACE_pid_reg(TRACE_pid_reg),\n        .TRACE_reg_addr(TRACE_reg_addr),\n        .TRACE_reg_write(TRACE_reg_write),\n        .TRACE_valid_instr(TRACE_valid_instr));\nendmodule\n", "num_lines": 174}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_bf3f_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_bf3f_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(16384),\n    .C_READ_DEPTH_A(16384),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(16384),\n    .C_READ_DEPTH_B(16384),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"16\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     19.660986 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_bf3f_second_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_bf3f_second_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(8192),\n    .C_READ_DEPTH_A(8192),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(8192),\n    .C_READ_DEPTH_B(8192),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"8\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     17.246228 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_bf3f.bd\n//Design : bd_bf3f\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_bf3f,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_bf3f,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_microblaze_mcs.hwdef\" *) \nmodule bd_bf3f\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_bf3f_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_bf3f_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_bf3f lmb_bram_I bd_bf3f second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_bf3f_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_bf3f_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_bf3f_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_bf3f_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_bf3f_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_bf3f dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_bf3f_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_bf3f_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_bf3f_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_bf3f_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_bf3f_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_bf3f.bd\n//Design : bd_bf3f\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_bf3f,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_bf3f,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_microblaze_mcs.hwdef\" *) \nmodule bd_bf3f\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_bf3f_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_bf3f_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_bf3f lmb_bram_I bd_bf3f second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_bf3f_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_bf3f_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_bf3f_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_bf3f_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_bf3f_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_bf3f dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_bf3f_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_bf3f_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_bf3f_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_bf3f_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_bf3f_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_bf3f_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_bf3f inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 225}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n(* X_CORE_INFO = \"bd_bf3f,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"ddr4_core_microblaze_mcs,bd_bf3f,{}\" *)\n(* CORE_GENERATION_INFO = \"ddr4_core_microblaze_mcs,bd_bf3f,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze_mcs,x_ipVersion=3.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,JTAG_CHAIN=2,MICROBLAZE_INSTANCE=microblaze_0,AVOID_PRIMITIVES=0,PATH=mcs_0,FREQ=100.0,OPTIMIZATION=1,DEBUG_ENABLED=0,USE_BSCAN=0,BSCANID=76547328,TRACE=1,ECC=0,MEMSIZE=98304,MEMTYPE=0,USE_IO_BUS=1,USE_UART_RX=0,USE_UART_TX=0,UART_BAUDRATE=9600,UART_PROG_BAUDRATE=0,UART_DATA_BITS=8,UART_USE_PARITY=0\\\n,UART_ODD_PARITY=0,UART_RX_INTERRUPT=0,UART_TX_INTERRUPT=0,UART_ERROR_INTERRUPT=0,USE_FIT1=0,FIT1_No_CLOCKS=6216,FIT1_INTERRUPT=0,USE_FIT2=0,FIT2_No_CLOCKS=6216,FIT2_INTERRUPT=0,USE_FIT3=0,FIT3_No_CLOCKS=6216,FIT3_INTERRUPT=0,USE_FIT4=0,FIT4_No_CLOCKS=6216,FIT4_INTERRUPT=0,USE_PIT1=0,PIT1_SIZE=32,PIT1_READABLE=1,PIT1_PRESCALER=0,PIT1_INTERRUPT=0,USE_PIT2=0,PIT2_SIZE=32,PIT2_READABLE=1,PIT2_PRESCALER=0,PIT2_INTERRUPT=0,USE_PIT3=0,PIT3_SIZE=32,PIT3_READABLE=1,PIT3_PRESCALER=0,PIT3_INTERRUPT=0,USE_\\\nPIT4=0,PIT4_SIZE=32,PIT4_READABLE=1,PIT4_PRESCALER=0,PIT4_INTERRUPT=0,USE_GPO1=0,GPO1_SIZE=32,GPO1_INIT=0x00000000,USE_GPO2=0,GPO2_SIZE=32,GPO2_INIT=0x00000000,USE_GPO3=0,GPO3_SIZE=32,GPO3_INIT=0x00000000,USE_GPO4=0,GPO4_SIZE=32,GPO4_INIT=0x00000000,USE_GPI1=0,GPI1_SIZE=32,GPI1_INTERRUPT=0,USE_GPI2=0,GPI2_SIZE=32,GPI2_INTERRUPT=0,USE_GPI3=0,GPI3_SIZE=32,GPI3_INTERRUPT=0,USE_GPI4=0,GPI4_SIZE=32,GPI4_INTERRUPT=0,INTC_USE_EXT_INTR=0,INTC_INTR_SIZE=1,INTC_LEVEL_EDGE=0x0000,INTC_POSITIVE=0xFFFF,INTC_\\\nASYNC_INTR=0xFFFF,INTC_NUM_SYNC_FF=2,Component_Name=ddr4_core_microblaze_mcs,USE_BOARD_FLOW=false,CLK_BOARD_INTERFACE=Custom,RESET_BOARD_INTERFACE=Custom,GPIO1_BOARD_INTERFACE=Custom,GPIO2_BOARD_INTERFACE=Custom,GPIO3_BOARD_INTERFACE=Custom,GPIO4_BOARD_INTERFACE=Custom,UART_BOARD_INTERFACE=Custom}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_bf3f_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_bf3f inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 229}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_8120_wrapper.bd\n//Design : bd_8120_wrapper\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule bd_8120_wrapper\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  input Clk;\n  output IO_addr_strobe;\n  output [31:0]IO_address;\n  output [3:0]IO_byte_enable;\n  input [31:0]IO_read_data;\n  output IO_read_strobe;\n  input IO_ready;\n  output [31:0]IO_write_data;\n  output IO_write_strobe;\n  input Reset;\n  output TRACE_data_access;\n  output [0:31]TRACE_data_address;\n  output [0:3]TRACE_data_byte_enable;\n  output TRACE_data_read;\n  output TRACE_data_write;\n  output [0:31]TRACE_data_write_value;\n  output TRACE_dcache_hit;\n  output TRACE_dcache_rdy;\n  output TRACE_dcache_read;\n  output TRACE_dcache_req;\n  output TRACE_delay_slot;\n  output TRACE_ex_piperun;\n  output [0:4]TRACE_exception_kind;\n  output TRACE_exception_taken;\n  output TRACE_icache_hit;\n  output TRACE_icache_rdy;\n  output TRACE_icache_req;\n  output [0:31]TRACE_instruction;\n  output TRACE_jump_hit;\n  output TRACE_jump_taken;\n  output TRACE_mb_halted;\n  output TRACE_mem_piperun;\n  output [0:14]TRACE_msr_reg;\n  output [0:31]TRACE_new_reg_value;\n  output TRACE_of_piperun;\n  output [0:31]TRACE_pc;\n  output [0:7]TRACE_pid_reg;\n  output [0:4]TRACE_reg_addr;\n  output TRACE_reg_write;\n  output TRACE_valid_instr;\n\n  wire Clk;\n  wire IO_addr_strobe;\n  wire [31:0]IO_address;\n  wire [3:0]IO_byte_enable;\n  wire [31:0]IO_read_data;\n  wire IO_read_strobe;\n  wire IO_ready;\n  wire [31:0]IO_write_data;\n  wire IO_write_strobe;\n  wire Reset;\n  wire TRACE_data_access;\n  wire [0:31]TRACE_data_address;\n  wire [0:3]TRACE_data_byte_enable;\n  wire TRACE_data_read;\n  wire TRACE_data_write;\n  wire [0:31]TRACE_data_write_value;\n  wire TRACE_dcache_hit;\n  wire TRACE_dcache_rdy;\n  wire TRACE_dcache_read;\n  wire TRACE_dcache_req;\n  wire TRACE_delay_slot;\n  wire TRACE_ex_piperun;\n  wire [0:4]TRACE_exception_kind;\n  wire TRACE_exception_taken;\n  wire TRACE_icache_hit;\n  wire TRACE_icache_rdy;\n  wire TRACE_icache_req;\n  wire [0:31]TRACE_instruction;\n  wire TRACE_jump_hit;\n  wire TRACE_jump_taken;\n  wire TRACE_mb_halted;\n  wire TRACE_mem_piperun;\n  wire [0:14]TRACE_msr_reg;\n  wire [0:31]TRACE_new_reg_value;\n  wire TRACE_of_piperun;\n  wire [0:31]TRACE_pc;\n  wire [0:7]TRACE_pid_reg;\n  wire [0:4]TRACE_reg_addr;\n  wire TRACE_reg_write;\n  wire TRACE_valid_instr;\n\n  bd_8120 bd_8120_i\n       (.Clk(Clk),\n        .IO_addr_strobe(IO_addr_strobe),\n        .IO_address(IO_address),\n        .IO_byte_enable(IO_byte_enable),\n        .IO_read_data(IO_read_data),\n        .IO_read_strobe(IO_read_strobe),\n        .IO_ready(IO_ready),\n        .IO_write_data(IO_write_data),\n        .IO_write_strobe(IO_write_strobe),\n        .Reset(Reset),\n        .TRACE_data_access(TRACE_data_access),\n        .TRACE_data_address(TRACE_data_address),\n        .TRACE_data_byte_enable(TRACE_data_byte_enable),\n        .TRACE_data_read(TRACE_data_read),\n        .TRACE_data_write(TRACE_data_write),\n        .TRACE_data_write_value(TRACE_data_write_value),\n        .TRACE_dcache_hit(TRACE_dcache_hit),\n        .TRACE_dcache_rdy(TRACE_dcache_rdy),\n        .TRACE_dcache_read(TRACE_dcache_read),\n        .TRACE_dcache_req(TRACE_dcache_req),\n        .TRACE_delay_slot(TRACE_delay_slot),\n        .TRACE_ex_piperun(TRACE_ex_piperun),\n        .TRACE_exception_kind(TRACE_exception_kind),\n        .TRACE_exception_taken(TRACE_exception_taken),\n        .TRACE_icache_hit(TRACE_icache_hit),\n        .TRACE_icache_rdy(TRACE_icache_rdy),\n        .TRACE_icache_req(TRACE_icache_req),\n        .TRACE_instruction(TRACE_instruction),\n        .TRACE_jump_hit(TRACE_jump_hit),\n        .TRACE_jump_taken(TRACE_jump_taken),\n        .TRACE_mb_halted(TRACE_mb_halted),\n        .TRACE_mem_piperun(TRACE_mem_piperun),\n        .TRACE_msr_reg(TRACE_msr_reg),\n        .TRACE_new_reg_value(TRACE_new_reg_value),\n        .TRACE_of_piperun(TRACE_of_piperun),\n        .TRACE_pc(TRACE_pc),\n        .TRACE_pid_reg(TRACE_pid_reg),\n        .TRACE_reg_addr(TRACE_reg_addr),\n        .TRACE_reg_write(TRACE_reg_write),\n        .TRACE_valid_instr(TRACE_valid_instr));\nendmodule\n", "num_lines": 174}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_8120_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_8120_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(16384),\n    .C_READ_DEPTH_A(16384),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(16384),\n    .C_READ_DEPTH_B(16384),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"16\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     19.660986 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_8120_second_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_8120_second_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(8192),\n    .C_READ_DEPTH_A(8192),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(8192),\n    .C_READ_DEPTH_B(8192),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"8\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     17.246228 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_8120.bd\n//Design : bd_8120\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_8120,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_8120,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_a_microblaze_mcs.hwdef\" *) \nmodule bd_8120\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_8120_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_8120_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_8120 lmb_bram_I bd_8120 second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_8120_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_8120_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_8120_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_8120_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_8120_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_8120 dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_8120_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_8120_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_8120_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_8120_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_8120_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_8120.bd\n//Design : bd_8120\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_8120,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_8120,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_a_microblaze_mcs.hwdef\" *) \nmodule bd_8120\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_8120_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_8120_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_8120 lmb_bram_I bd_8120 second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_8120_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_8120_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_8120_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_8120_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_8120_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_8120 dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_8120_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_8120_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_8120_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_8120_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_8120_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_a_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_8120_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_8120 inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 225}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n(* X_CORE_INFO = \"bd_8120,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"ddr4_core_a_microblaze_mcs,bd_8120,{}\" *)\n(* CORE_GENERATION_INFO = \"ddr4_core_a_microblaze_mcs,bd_8120,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze_mcs,x_ipVersion=3.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,JTAG_CHAIN=2,MICROBLAZE_INSTANCE=microblaze_0,AVOID_PRIMITIVES=0,PATH=mcs_0,FREQ=100.0,OPTIMIZATION=1,DEBUG_ENABLED=0,USE_BSCAN=0,BSCANID=76547328,TRACE=1,ECC=0,MEMSIZE=98304,MEMTYPE=0,USE_IO_BUS=1,USE_UART_RX=0,USE_UART_TX=0,UART_BAUDRATE=9600,UART_PROG_BAUDRATE=0,UART_DATA_BITS=8,UART_USE_PARITY\\\n=0,UART_ODD_PARITY=0,UART_RX_INTERRUPT=0,UART_TX_INTERRUPT=0,UART_ERROR_INTERRUPT=0,USE_FIT1=0,FIT1_No_CLOCKS=6216,FIT1_INTERRUPT=0,USE_FIT2=0,FIT2_No_CLOCKS=6216,FIT2_INTERRUPT=0,USE_FIT3=0,FIT3_No_CLOCKS=6216,FIT3_INTERRUPT=0,USE_FIT4=0,FIT4_No_CLOCKS=6216,FIT4_INTERRUPT=0,USE_PIT1=0,PIT1_SIZE=32,PIT1_READABLE=1,PIT1_PRESCALER=0,PIT1_INTERRUPT=0,USE_PIT2=0,PIT2_SIZE=32,PIT2_READABLE=1,PIT2_PRESCALER=0,PIT2_INTERRUPT=0,USE_PIT3=0,PIT3_SIZE=32,PIT3_READABLE=1,PIT3_PRESCALER=0,PIT3_INTERRUPT=0,US\\\nE_PIT4=0,PIT4_SIZE=32,PIT4_READABLE=1,PIT4_PRESCALER=0,PIT4_INTERRUPT=0,USE_GPO1=0,GPO1_SIZE=32,GPO1_INIT=0x00000000,USE_GPO2=0,GPO2_SIZE=32,GPO2_INIT=0x00000000,USE_GPO3=0,GPO3_SIZE=32,GPO3_INIT=0x00000000,USE_GPO4=0,GPO4_SIZE=32,GPO4_INIT=0x00000000,USE_GPI1=0,GPI1_SIZE=32,GPI1_INTERRUPT=0,USE_GPI2=0,GPI2_SIZE=32,GPI2_INTERRUPT=0,USE_GPI3=0,GPI3_SIZE=32,GPI3_INTERRUPT=0,USE_GPI4=0,GPI4_SIZE=32,GPI4_INTERRUPT=0,INTC_USE_EXT_INTR=0,INTC_INTR_SIZE=1,INTC_LEVEL_EDGE=0x0000,INTC_POSITIVE=0xFFFF,INT\\\nC_ASYNC_INTR=0xFFFF,INTC_NUM_SYNC_FF=2,Component_Name=ddr4_core_a_microblaze_mcs,USE_BOARD_FLOW=false,CLK_BOARD_INTERFACE=Custom,RESET_BOARD_INTERFACE=Custom,GPIO1_BOARD_INTERFACE=Custom,GPIO2_BOARD_INTERFACE=Custom,GPIO3_BOARD_INTERFACE=Custom,GPIO4_BOARD_INTERFACE=Custom,UART_BOARD_INTERFACE=Custom}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_a_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_8120_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_8120 inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 229}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_b066_wrapper.bd\n//Design : bd_b066_wrapper\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule bd_b066_wrapper\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  input Clk;\n  output IO_addr_strobe;\n  output [31:0]IO_address;\n  output [3:0]IO_byte_enable;\n  input [31:0]IO_read_data;\n  output IO_read_strobe;\n  input IO_ready;\n  output [31:0]IO_write_data;\n  output IO_write_strobe;\n  input Reset;\n  output TRACE_data_access;\n  output [0:31]TRACE_data_address;\n  output [0:3]TRACE_data_byte_enable;\n  output TRACE_data_read;\n  output TRACE_data_write;\n  output [0:31]TRACE_data_write_value;\n  output TRACE_dcache_hit;\n  output TRACE_dcache_rdy;\n  output TRACE_dcache_read;\n  output TRACE_dcache_req;\n  output TRACE_delay_slot;\n  output TRACE_ex_piperun;\n  output [0:4]TRACE_exception_kind;\n  output TRACE_exception_taken;\n  output TRACE_icache_hit;\n  output TRACE_icache_rdy;\n  output TRACE_icache_req;\n  output [0:31]TRACE_instruction;\n  output TRACE_jump_hit;\n  output TRACE_jump_taken;\n  output TRACE_mb_halted;\n  output TRACE_mem_piperun;\n  output [0:14]TRACE_msr_reg;\n  output [0:31]TRACE_new_reg_value;\n  output TRACE_of_piperun;\n  output [0:31]TRACE_pc;\n  output [0:7]TRACE_pid_reg;\n  output [0:4]TRACE_reg_addr;\n  output TRACE_reg_write;\n  output TRACE_valid_instr;\n\n  wire Clk;\n  wire IO_addr_strobe;\n  wire [31:0]IO_address;\n  wire [3:0]IO_byte_enable;\n  wire [31:0]IO_read_data;\n  wire IO_read_strobe;\n  wire IO_ready;\n  wire [31:0]IO_write_data;\n  wire IO_write_strobe;\n  wire Reset;\n  wire TRACE_data_access;\n  wire [0:31]TRACE_data_address;\n  wire [0:3]TRACE_data_byte_enable;\n  wire TRACE_data_read;\n  wire TRACE_data_write;\n  wire [0:31]TRACE_data_write_value;\n  wire TRACE_dcache_hit;\n  wire TRACE_dcache_rdy;\n  wire TRACE_dcache_read;\n  wire TRACE_dcache_req;\n  wire TRACE_delay_slot;\n  wire TRACE_ex_piperun;\n  wire [0:4]TRACE_exception_kind;\n  wire TRACE_exception_taken;\n  wire TRACE_icache_hit;\n  wire TRACE_icache_rdy;\n  wire TRACE_icache_req;\n  wire [0:31]TRACE_instruction;\n  wire TRACE_jump_hit;\n  wire TRACE_jump_taken;\n  wire TRACE_mb_halted;\n  wire TRACE_mem_piperun;\n  wire [0:14]TRACE_msr_reg;\n  wire [0:31]TRACE_new_reg_value;\n  wire TRACE_of_piperun;\n  wire [0:31]TRACE_pc;\n  wire [0:7]TRACE_pid_reg;\n  wire [0:4]TRACE_reg_addr;\n  wire TRACE_reg_write;\n  wire TRACE_valid_instr;\n\n  bd_b066 bd_b066_i\n       (.Clk(Clk),\n        .IO_addr_strobe(IO_addr_strobe),\n        .IO_address(IO_address),\n        .IO_byte_enable(IO_byte_enable),\n        .IO_read_data(IO_read_data),\n        .IO_read_strobe(IO_read_strobe),\n        .IO_ready(IO_ready),\n        .IO_write_data(IO_write_data),\n        .IO_write_strobe(IO_write_strobe),\n        .Reset(Reset),\n        .TRACE_data_access(TRACE_data_access),\n        .TRACE_data_address(TRACE_data_address),\n        .TRACE_data_byte_enable(TRACE_data_byte_enable),\n        .TRACE_data_read(TRACE_data_read),\n        .TRACE_data_write(TRACE_data_write),\n        .TRACE_data_write_value(TRACE_data_write_value),\n        .TRACE_dcache_hit(TRACE_dcache_hit),\n        .TRACE_dcache_rdy(TRACE_dcache_rdy),\n        .TRACE_dcache_read(TRACE_dcache_read),\n        .TRACE_dcache_req(TRACE_dcache_req),\n        .TRACE_delay_slot(TRACE_delay_slot),\n        .TRACE_ex_piperun(TRACE_ex_piperun),\n        .TRACE_exception_kind(TRACE_exception_kind),\n        .TRACE_exception_taken(TRACE_exception_taken),\n        .TRACE_icache_hit(TRACE_icache_hit),\n        .TRACE_icache_rdy(TRACE_icache_rdy),\n        .TRACE_icache_req(TRACE_icache_req),\n        .TRACE_instruction(TRACE_instruction),\n        .TRACE_jump_hit(TRACE_jump_hit),\n        .TRACE_jump_taken(TRACE_jump_taken),\n        .TRACE_mb_halted(TRACE_mb_halted),\n        .TRACE_mem_piperun(TRACE_mem_piperun),\n        .TRACE_msr_reg(TRACE_msr_reg),\n        .TRACE_new_reg_value(TRACE_new_reg_value),\n        .TRACE_of_piperun(TRACE_of_piperun),\n        .TRACE_pc(TRACE_pc),\n        .TRACE_pid_reg(TRACE_pid_reg),\n        .TRACE_reg_addr(TRACE_reg_addr),\n        .TRACE_reg_write(TRACE_reg_write),\n        .TRACE_valid_instr(TRACE_valid_instr));\nendmodule\n", "num_lines": 174}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_b066_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_b066_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(16384),\n    .C_READ_DEPTH_A(16384),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(16384),\n    .C_READ_DEPTH_B(16384),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"16\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     19.660986 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_b066_second_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_b066_second_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(8192),\n    .C_READ_DEPTH_A(8192),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(8192),\n    .C_READ_DEPTH_B(8192),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"8\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     17.246228 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_b066.bd\n//Design : bd_b066\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_b066,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_b066,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_b_microblaze_mcs.hwdef\" *) \nmodule bd_b066\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_b066_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_b066_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_b066 lmb_bram_I bd_b066 second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_b066_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_b066_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_b066_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_b066_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_b066_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_b066 dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_b066_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_b066_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_b066_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_b066_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_b066_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_b066.bd\n//Design : bd_b066\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_b066,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_b066,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_b_microblaze_mcs.hwdef\" *) \nmodule bd_b066\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_b066_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_b066_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_b066 lmb_bram_I bd_b066 second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_b066_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_b066_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_b066_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_b066_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_b066_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_b066 dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_b066_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_b066_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_b066_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_b066_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_b066_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_b_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_b066_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_b066 inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 225}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n(* X_CORE_INFO = \"bd_b066,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"ddr4_core_b_microblaze_mcs,bd_b066,{}\" *)\n(* CORE_GENERATION_INFO = \"ddr4_core_b_microblaze_mcs,bd_b066,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze_mcs,x_ipVersion=3.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,JTAG_CHAIN=2,MICROBLAZE_INSTANCE=microblaze_0,AVOID_PRIMITIVES=0,PATH=mcs_0,FREQ=100.0,OPTIMIZATION=1,DEBUG_ENABLED=0,USE_BSCAN=0,BSCANID=76547328,TRACE=1,ECC=0,MEMSIZE=98304,MEMTYPE=0,USE_IO_BUS=1,USE_UART_RX=0,USE_UART_TX=0,UART_BAUDRATE=9600,UART_PROG_BAUDRATE=0,UART_DATA_BITS=8,UART_USE_PARITY\\\n=0,UART_ODD_PARITY=0,UART_RX_INTERRUPT=0,UART_TX_INTERRUPT=0,UART_ERROR_INTERRUPT=0,USE_FIT1=0,FIT1_No_CLOCKS=6216,FIT1_INTERRUPT=0,USE_FIT2=0,FIT2_No_CLOCKS=6216,FIT2_INTERRUPT=0,USE_FIT3=0,FIT3_No_CLOCKS=6216,FIT3_INTERRUPT=0,USE_FIT4=0,FIT4_No_CLOCKS=6216,FIT4_INTERRUPT=0,USE_PIT1=0,PIT1_SIZE=32,PIT1_READABLE=1,PIT1_PRESCALER=0,PIT1_INTERRUPT=0,USE_PIT2=0,PIT2_SIZE=32,PIT2_READABLE=1,PIT2_PRESCALER=0,PIT2_INTERRUPT=0,USE_PIT3=0,PIT3_SIZE=32,PIT3_READABLE=1,PIT3_PRESCALER=0,PIT3_INTERRUPT=0,US\\\nE_PIT4=0,PIT4_SIZE=32,PIT4_READABLE=1,PIT4_PRESCALER=0,PIT4_INTERRUPT=0,USE_GPO1=0,GPO1_SIZE=32,GPO1_INIT=0x00000000,USE_GPO2=0,GPO2_SIZE=32,GPO2_INIT=0x00000000,USE_GPO3=0,GPO3_SIZE=32,GPO3_INIT=0x00000000,USE_GPO4=0,GPO4_SIZE=32,GPO4_INIT=0x00000000,USE_GPI1=0,GPI1_SIZE=32,GPI1_INTERRUPT=0,USE_GPI2=0,GPI2_SIZE=32,GPI2_INTERRUPT=0,USE_GPI3=0,GPI3_SIZE=32,GPI3_INTERRUPT=0,USE_GPI4=0,GPI4_SIZE=32,GPI4_INTERRUPT=0,INTC_USE_EXT_INTR=0,INTC_INTR_SIZE=1,INTC_LEVEL_EDGE=0x0000,INTC_POSITIVE=0xFFFF,INT\\\nC_ASYNC_INTR=0xFFFF,INTC_NUM_SYNC_FF=2,Component_Name=ddr4_core_b_microblaze_mcs,USE_BOARD_FLOW=false,CLK_BOARD_INTERFACE=Custom,RESET_BOARD_INTERFACE=Custom,GPIO1_BOARD_INTERFACE=Custom,GPIO2_BOARD_INTERFACE=Custom,GPIO3_BOARD_INTERFACE=Custom,GPIO4_BOARD_INTERFACE=Custom,UART_BOARD_INTERFACE=Custom}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_b_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_b066_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_b066 inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 229}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_a0a4_wrapper.bd\n//Design : bd_a0a4_wrapper\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule bd_a0a4_wrapper\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  input Clk;\n  output IO_addr_strobe;\n  output [31:0]IO_address;\n  output [3:0]IO_byte_enable;\n  input [31:0]IO_read_data;\n  output IO_read_strobe;\n  input IO_ready;\n  output [31:0]IO_write_data;\n  output IO_write_strobe;\n  input Reset;\n  output TRACE_data_access;\n  output [0:31]TRACE_data_address;\n  output [0:3]TRACE_data_byte_enable;\n  output TRACE_data_read;\n  output TRACE_data_write;\n  output [0:31]TRACE_data_write_value;\n  output TRACE_dcache_hit;\n  output TRACE_dcache_rdy;\n  output TRACE_dcache_read;\n  output TRACE_dcache_req;\n  output TRACE_delay_slot;\n  output TRACE_ex_piperun;\n  output [0:4]TRACE_exception_kind;\n  output TRACE_exception_taken;\n  output TRACE_icache_hit;\n  output TRACE_icache_rdy;\n  output TRACE_icache_req;\n  output [0:31]TRACE_instruction;\n  output TRACE_jump_hit;\n  output TRACE_jump_taken;\n  output TRACE_mb_halted;\n  output TRACE_mem_piperun;\n  output [0:14]TRACE_msr_reg;\n  output [0:31]TRACE_new_reg_value;\n  output TRACE_of_piperun;\n  output [0:31]TRACE_pc;\n  output [0:7]TRACE_pid_reg;\n  output [0:4]TRACE_reg_addr;\n  output TRACE_reg_write;\n  output TRACE_valid_instr;\n\n  wire Clk;\n  wire IO_addr_strobe;\n  wire [31:0]IO_address;\n  wire [3:0]IO_byte_enable;\n  wire [31:0]IO_read_data;\n  wire IO_read_strobe;\n  wire IO_ready;\n  wire [31:0]IO_write_data;\n  wire IO_write_strobe;\n  wire Reset;\n  wire TRACE_data_access;\n  wire [0:31]TRACE_data_address;\n  wire [0:3]TRACE_data_byte_enable;\n  wire TRACE_data_read;\n  wire TRACE_data_write;\n  wire [0:31]TRACE_data_write_value;\n  wire TRACE_dcache_hit;\n  wire TRACE_dcache_rdy;\n  wire TRACE_dcache_read;\n  wire TRACE_dcache_req;\n  wire TRACE_delay_slot;\n  wire TRACE_ex_piperun;\n  wire [0:4]TRACE_exception_kind;\n  wire TRACE_exception_taken;\n  wire TRACE_icache_hit;\n  wire TRACE_icache_rdy;\n  wire TRACE_icache_req;\n  wire [0:31]TRACE_instruction;\n  wire TRACE_jump_hit;\n  wire TRACE_jump_taken;\n  wire TRACE_mb_halted;\n  wire TRACE_mem_piperun;\n  wire [0:14]TRACE_msr_reg;\n  wire [0:31]TRACE_new_reg_value;\n  wire TRACE_of_piperun;\n  wire [0:31]TRACE_pc;\n  wire [0:7]TRACE_pid_reg;\n  wire [0:4]TRACE_reg_addr;\n  wire TRACE_reg_write;\n  wire TRACE_valid_instr;\n\n  bd_a0a4 bd_a0a4_i\n       (.Clk(Clk),\n        .IO_addr_strobe(IO_addr_strobe),\n        .IO_address(IO_address),\n        .IO_byte_enable(IO_byte_enable),\n        .IO_read_data(IO_read_data),\n        .IO_read_strobe(IO_read_strobe),\n        .IO_ready(IO_ready),\n        .IO_write_data(IO_write_data),\n        .IO_write_strobe(IO_write_strobe),\n        .Reset(Reset),\n        .TRACE_data_access(TRACE_data_access),\n        .TRACE_data_address(TRACE_data_address),\n        .TRACE_data_byte_enable(TRACE_data_byte_enable),\n        .TRACE_data_read(TRACE_data_read),\n        .TRACE_data_write(TRACE_data_write),\n        .TRACE_data_write_value(TRACE_data_write_value),\n        .TRACE_dcache_hit(TRACE_dcache_hit),\n        .TRACE_dcache_rdy(TRACE_dcache_rdy),\n        .TRACE_dcache_read(TRACE_dcache_read),\n        .TRACE_dcache_req(TRACE_dcache_req),\n        .TRACE_delay_slot(TRACE_delay_slot),\n        .TRACE_ex_piperun(TRACE_ex_piperun),\n        .TRACE_exception_kind(TRACE_exception_kind),\n        .TRACE_exception_taken(TRACE_exception_taken),\n        .TRACE_icache_hit(TRACE_icache_hit),\n        .TRACE_icache_rdy(TRACE_icache_rdy),\n        .TRACE_icache_req(TRACE_icache_req),\n        .TRACE_instruction(TRACE_instruction),\n        .TRACE_jump_hit(TRACE_jump_hit),\n        .TRACE_jump_taken(TRACE_jump_taken),\n        .TRACE_mb_halted(TRACE_mb_halted),\n        .TRACE_mem_piperun(TRACE_mem_piperun),\n        .TRACE_msr_reg(TRACE_msr_reg),\n        .TRACE_new_reg_value(TRACE_new_reg_value),\n        .TRACE_of_piperun(TRACE_of_piperun),\n        .TRACE_pc(TRACE_pc),\n        .TRACE_pid_reg(TRACE_pid_reg),\n        .TRACE_reg_addr(TRACE_reg_addr),\n        .TRACE_reg_write(TRACE_reg_write),\n        .TRACE_valid_instr(TRACE_valid_instr));\nendmodule\n", "num_lines": 174}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_a0a4_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_a0a4_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(16384),\n    .C_READ_DEPTH_A(16384),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(16384),\n    .C_READ_DEPTH_B(16384),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"16\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     19.660986 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_a0a4_second_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_a0a4_second_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(8192),\n    .C_READ_DEPTH_A(8192),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(8192),\n    .C_READ_DEPTH_B(8192),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"8\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     17.246228 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_a0a4.bd\n//Design : bd_a0a4\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_a0a4,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_a0a4,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_c_microblaze_mcs.hwdef\" *) \nmodule bd_a0a4\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_a0a4_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_a0a4_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_a0a4 lmb_bram_I bd_a0a4 second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_a0a4_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_a0a4_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_a0a4_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_a0a4_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_a0a4_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_a0a4 dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_a0a4_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_a0a4_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_a0a4_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_a0a4_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_a0a4_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_a0a4.bd\n//Design : bd_a0a4\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_a0a4,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_a0a4,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_c_microblaze_mcs.hwdef\" *) \nmodule bd_a0a4\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_a0a4_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_a0a4_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_a0a4 lmb_bram_I bd_a0a4 second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_a0a4_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_a0a4_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_a0a4_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_a0a4_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_a0a4_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_a0a4 dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_a0a4_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_a0a4_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_a0a4_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_a0a4_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_a0a4_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_c_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_a0a4_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_a0a4 inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 225}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n(* X_CORE_INFO = \"bd_a0a4,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"ddr4_core_c_microblaze_mcs,bd_a0a4,{}\" *)\n(* CORE_GENERATION_INFO = \"ddr4_core_c_microblaze_mcs,bd_a0a4,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze_mcs,x_ipVersion=3.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,JTAG_CHAIN=2,MICROBLAZE_INSTANCE=microblaze_0,AVOID_PRIMITIVES=0,PATH=mcs_0,FREQ=100.0,OPTIMIZATION=1,DEBUG_ENABLED=0,USE_BSCAN=0,BSCANID=76547328,TRACE=1,ECC=0,MEMSIZE=98304,MEMTYPE=0,USE_IO_BUS=1,USE_UART_RX=0,USE_UART_TX=0,UART_BAUDRATE=9600,UART_PROG_BAUDRATE=0,UART_DATA_BITS=8,UART_USE_PARITY\\\n=0,UART_ODD_PARITY=0,UART_RX_INTERRUPT=0,UART_TX_INTERRUPT=0,UART_ERROR_INTERRUPT=0,USE_FIT1=0,FIT1_No_CLOCKS=6216,FIT1_INTERRUPT=0,USE_FIT2=0,FIT2_No_CLOCKS=6216,FIT2_INTERRUPT=0,USE_FIT3=0,FIT3_No_CLOCKS=6216,FIT3_INTERRUPT=0,USE_FIT4=0,FIT4_No_CLOCKS=6216,FIT4_INTERRUPT=0,USE_PIT1=0,PIT1_SIZE=32,PIT1_READABLE=1,PIT1_PRESCALER=0,PIT1_INTERRUPT=0,USE_PIT2=0,PIT2_SIZE=32,PIT2_READABLE=1,PIT2_PRESCALER=0,PIT2_INTERRUPT=0,USE_PIT3=0,PIT3_SIZE=32,PIT3_READABLE=1,PIT3_PRESCALER=0,PIT3_INTERRUPT=0,US\\\nE_PIT4=0,PIT4_SIZE=32,PIT4_READABLE=1,PIT4_PRESCALER=0,PIT4_INTERRUPT=0,USE_GPO1=0,GPO1_SIZE=32,GPO1_INIT=0x00000000,USE_GPO2=0,GPO2_SIZE=32,GPO2_INIT=0x00000000,USE_GPO3=0,GPO3_SIZE=32,GPO3_INIT=0x00000000,USE_GPO4=0,GPO4_SIZE=32,GPO4_INIT=0x00000000,USE_GPI1=0,GPI1_SIZE=32,GPI1_INTERRUPT=0,USE_GPI2=0,GPI2_SIZE=32,GPI2_INTERRUPT=0,USE_GPI3=0,GPI3_SIZE=32,GPI3_INTERRUPT=0,USE_GPI4=0,GPI4_SIZE=32,GPI4_INTERRUPT=0,INTC_USE_EXT_INTR=0,INTC_INTR_SIZE=1,INTC_LEVEL_EDGE=0x0000,INTC_POSITIVE=0xFFFF,INT\\\nC_ASYNC_INTR=0xFFFF,INTC_NUM_SYNC_FF=2,Component_Name=ddr4_core_c_microblaze_mcs,USE_BOARD_FLOW=false,CLK_BOARD_INTERFACE=Custom,RESET_BOARD_INTERFACE=Custom,GPIO1_BOARD_INTERFACE=Custom,GPIO2_BOARD_INTERFACE=Custom,GPIO3_BOARD_INTERFACE=Custom,GPIO4_BOARD_INTERFACE=Custom,UART_BOARD_INTERFACE=Custom}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_c_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_a0a4_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_a0a4 inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 229}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_d2ea_wrapper.bd\n//Design : bd_d2ea_wrapper\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule bd_d2ea_wrapper\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  input Clk;\n  output IO_addr_strobe;\n  output [31:0]IO_address;\n  output [3:0]IO_byte_enable;\n  input [31:0]IO_read_data;\n  output IO_read_strobe;\n  input IO_ready;\n  output [31:0]IO_write_data;\n  output IO_write_strobe;\n  input Reset;\n  output TRACE_data_access;\n  output [0:31]TRACE_data_address;\n  output [0:3]TRACE_data_byte_enable;\n  output TRACE_data_read;\n  output TRACE_data_write;\n  output [0:31]TRACE_data_write_value;\n  output TRACE_dcache_hit;\n  output TRACE_dcache_rdy;\n  output TRACE_dcache_read;\n  output TRACE_dcache_req;\n  output TRACE_delay_slot;\n  output TRACE_ex_piperun;\n  output [0:4]TRACE_exception_kind;\n  output TRACE_exception_taken;\n  output TRACE_icache_hit;\n  output TRACE_icache_rdy;\n  output TRACE_icache_req;\n  output [0:31]TRACE_instruction;\n  output TRACE_jump_hit;\n  output TRACE_jump_taken;\n  output TRACE_mb_halted;\n  output TRACE_mem_piperun;\n  output [0:14]TRACE_msr_reg;\n  output [0:31]TRACE_new_reg_value;\n  output TRACE_of_piperun;\n  output [0:31]TRACE_pc;\n  output [0:7]TRACE_pid_reg;\n  output [0:4]TRACE_reg_addr;\n  output TRACE_reg_write;\n  output TRACE_valid_instr;\n\n  wire Clk;\n  wire IO_addr_strobe;\n  wire [31:0]IO_address;\n  wire [3:0]IO_byte_enable;\n  wire [31:0]IO_read_data;\n  wire IO_read_strobe;\n  wire IO_ready;\n  wire [31:0]IO_write_data;\n  wire IO_write_strobe;\n  wire Reset;\n  wire TRACE_data_access;\n  wire [0:31]TRACE_data_address;\n  wire [0:3]TRACE_data_byte_enable;\n  wire TRACE_data_read;\n  wire TRACE_data_write;\n  wire [0:31]TRACE_data_write_value;\n  wire TRACE_dcache_hit;\n  wire TRACE_dcache_rdy;\n  wire TRACE_dcache_read;\n  wire TRACE_dcache_req;\n  wire TRACE_delay_slot;\n  wire TRACE_ex_piperun;\n  wire [0:4]TRACE_exception_kind;\n  wire TRACE_exception_taken;\n  wire TRACE_icache_hit;\n  wire TRACE_icache_rdy;\n  wire TRACE_icache_req;\n  wire [0:31]TRACE_instruction;\n  wire TRACE_jump_hit;\n  wire TRACE_jump_taken;\n  wire TRACE_mb_halted;\n  wire TRACE_mem_piperun;\n  wire [0:14]TRACE_msr_reg;\n  wire [0:31]TRACE_new_reg_value;\n  wire TRACE_of_piperun;\n  wire [0:31]TRACE_pc;\n  wire [0:7]TRACE_pid_reg;\n  wire [0:4]TRACE_reg_addr;\n  wire TRACE_reg_write;\n  wire TRACE_valid_instr;\n\n  bd_d2ea bd_d2ea_i\n       (.Clk(Clk),\n        .IO_addr_strobe(IO_addr_strobe),\n        .IO_address(IO_address),\n        .IO_byte_enable(IO_byte_enable),\n        .IO_read_data(IO_read_data),\n        .IO_read_strobe(IO_read_strobe),\n        .IO_ready(IO_ready),\n        .IO_write_data(IO_write_data),\n        .IO_write_strobe(IO_write_strobe),\n        .Reset(Reset),\n        .TRACE_data_access(TRACE_data_access),\n        .TRACE_data_address(TRACE_data_address),\n        .TRACE_data_byte_enable(TRACE_data_byte_enable),\n        .TRACE_data_read(TRACE_data_read),\n        .TRACE_data_write(TRACE_data_write),\n        .TRACE_data_write_value(TRACE_data_write_value),\n        .TRACE_dcache_hit(TRACE_dcache_hit),\n        .TRACE_dcache_rdy(TRACE_dcache_rdy),\n        .TRACE_dcache_read(TRACE_dcache_read),\n        .TRACE_dcache_req(TRACE_dcache_req),\n        .TRACE_delay_slot(TRACE_delay_slot),\n        .TRACE_ex_piperun(TRACE_ex_piperun),\n        .TRACE_exception_kind(TRACE_exception_kind),\n        .TRACE_exception_taken(TRACE_exception_taken),\n        .TRACE_icache_hit(TRACE_icache_hit),\n        .TRACE_icache_rdy(TRACE_icache_rdy),\n        .TRACE_icache_req(TRACE_icache_req),\n        .TRACE_instruction(TRACE_instruction),\n        .TRACE_jump_hit(TRACE_jump_hit),\n        .TRACE_jump_taken(TRACE_jump_taken),\n        .TRACE_mb_halted(TRACE_mb_halted),\n        .TRACE_mem_piperun(TRACE_mem_piperun),\n        .TRACE_msr_reg(TRACE_msr_reg),\n        .TRACE_new_reg_value(TRACE_new_reg_value),\n        .TRACE_of_piperun(TRACE_of_piperun),\n        .TRACE_pc(TRACE_pc),\n        .TRACE_pid_reg(TRACE_pid_reg),\n        .TRACE_reg_addr(TRACE_reg_addr),\n        .TRACE_reg_write(TRACE_reg_write),\n        .TRACE_valid_instr(TRACE_valid_instr));\nendmodule\n", "num_lines": 174}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_d2ea_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_d2ea_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(16384),\n    .C_READ_DEPTH_A(16384),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(16384),\n    .C_READ_DEPTH_B(16384),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"16\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     19.660986 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule bd_d2ea_second_lmb_bram_I_0 (\n  clka,\n  rsta,\n  ena,\n  wea,\n  addra,\n  dina,\n  douta,\n  clkb,\n  rstb,\n  enb,\n  web,\n  addrb,\n  dinb,\n  doutb,\n  rsta_busy,\n  rstb_busy\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA RST\" *)\ninput wire rsta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [3 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [31 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [31 : 0] dina;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT\" *)\noutput wire [31 : 0] douta;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB RST\" *)\ninput wire rstb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB EN\" *)\ninput wire enb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB WE\" *)\ninput wire [3 : 0] web;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [31 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DIN\" *)\ninput wire [31 : 0] dinb;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [31 : 0] doutb;\noutput wire rsta_busy;\noutput wire rstb_busy;\n\n  blk_mem_gen_v8_4_4 #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_XDEVICEFAMILY(\"virtexuplus\"),\n    .C_ELABORATION_DIR(\"./\"),\n    .C_INTERFACE_TYPE(0),\n    .C_AXI_TYPE(1),\n    .C_AXI_SLAVE_TYPE(0),\n    .C_USE_BRAM_BLOCK(1),\n    .C_ENABLE_32BIT_ADDRESS(1),\n    .C_CTRL_ECC_ALGO(\"NONE\"),\n    .C_HAS_AXI_ID(0),\n    .C_AXI_ID_WIDTH(4),\n    .C_MEM_TYPE(2),\n    .C_BYTE_SIZE(8),\n    .C_ALGORITHM(1),\n    .C_PRIM_TYPE(1),\n    .C_LOAD_INIT_FILE(0),\n    .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n    .C_INIT_FILE(\"bd_d2ea_second_lmb_bram_I_0.mem\"),\n    .C_USE_DEFAULT_DATA(0),\n    .C_DEFAULT_DATA(\"0\"),\n    .C_HAS_RSTA(1),\n    .C_RST_PRIORITY_A(\"CE\"),\n    .C_RSTRAM_A(0),\n    .C_INITA_VAL(\"0\"),\n    .C_HAS_ENA(1),\n    .C_HAS_REGCEA(0),\n    .C_USE_BYTE_WEA(1),\n    .C_WEA_WIDTH(4),\n    .C_WRITE_MODE_A(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_A(32),\n    .C_READ_WIDTH_A(32),\n    .C_WRITE_DEPTH_A(8192),\n    .C_READ_DEPTH_A(8192),\n    .C_ADDRA_WIDTH(32),\n    .C_HAS_RSTB(1),\n    .C_RST_PRIORITY_B(\"CE\"),\n    .C_RSTRAM_B(0),\n    .C_INITB_VAL(\"0\"),\n    .C_HAS_ENB(1),\n    .C_HAS_REGCEB(0),\n    .C_USE_BYTE_WEB(1),\n    .C_WEB_WIDTH(4),\n    .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n    .C_WRITE_WIDTH_B(32),\n    .C_READ_WIDTH_B(32),\n    .C_WRITE_DEPTH_B(8192),\n    .C_READ_DEPTH_B(8192),\n    .C_ADDRB_WIDTH(32),\n    .C_HAS_MEM_OUTPUT_REGS_A(0),\n    .C_HAS_MEM_OUTPUT_REGS_B(0),\n    .C_HAS_MUX_OUTPUT_REGS_A(0),\n    .C_HAS_MUX_OUTPUT_REGS_B(0),\n    .C_MUX_PIPELINE_STAGES(0),\n    .C_HAS_SOFTECC_INPUT_REGS_A(0),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n    .C_USE_SOFTECC(0),\n    .C_USE_ECC(0),\n    .C_EN_ECC_PIPE(0),\n    .C_READ_LATENCY_A(1),\n    .C_READ_LATENCY_B(1),\n    .C_HAS_INJECTERR(0),\n    .C_SIM_COLLISION_CHECK(\"ALL\"),\n    .C_COMMON_CLK(0),\n    .C_DISABLE_WARN_BHV_COLL(0),\n    .C_EN_SLEEP_PIN(0),\n    .C_USE_URAM(0),\n    .C_EN_RDADDRA_CHG(0),\n    .C_EN_RDADDRB_CHG(0),\n    .C_EN_DEEPSLEEP_PIN(0),\n    .C_EN_SHUTDOWN_PIN(0),\n    .C_EN_SAFETY_CKT(1),\n    .C_DISABLE_WARN_BHV_RANGE(0),\n    .C_COUNT_36K_BRAM(\"8\"),\n    .C_COUNT_18K_BRAM(\"0\"),\n    .C_EST_POWER_SUMMARY(\"Estimated Power for IP     :     17.246228 mW\")\n  ) inst (\n    .clka(clka),\n    .rsta(rsta),\n    .ena(ena),\n    .regcea(1'D0),\n    .wea(wea),\n    .addra(addra),\n    .dina(dina),\n    .douta(douta),\n    .clkb(clkb),\n    .rstb(rstb),\n    .enb(enb),\n    .regceb(1'D0),\n    .web(web),\n    .addrb(addrb),\n    .dinb(dinb),\n    .doutb(doutb),\n    .injectsbiterr(1'D0),\n    .injectdbiterr(1'D0),\n    .eccpipece(1'D0),\n    .sbiterr(),\n    .dbiterr(),\n    .rdaddrecc(),\n    .sleep(1'D0),\n    .deepsleep(1'D0),\n    .shutdown(1'D0),\n    .rsta_busy(rsta_busy),\n    .rstb_busy(rstb_busy),\n    .s_aclk(1'H0),\n    .s_aresetn(1'D0),\n    .s_axi_awid(4'B0),\n    .s_axi_awaddr(32'B0),\n    .s_axi_awlen(8'B0),\n    .s_axi_awsize(3'B0),\n    .s_axi_awburst(2'B0),\n    .s_axi_awvalid(1'D0),\n    .s_axi_awready(),\n    .s_axi_wdata(32'B0),\n    .s_axi_wstrb(4'B0),\n    .s_axi_wlast(1'D0),\n    .s_axi_wvalid(1'D0),\n    .s_axi_wready(),\n    .s_axi_bid(),\n    .s_axi_bresp(),\n    .s_axi_bvalid(),\n    .s_axi_bready(1'D0),\n    .s_axi_arid(4'B0),\n    .s_axi_araddr(32'B0),\n    .s_axi_arlen(8'B0),\n    .s_axi_arsize(3'B0),\n    .s_axi_arburst(2'B0),\n    .s_axi_arvalid(1'D0),\n    .s_axi_arready(),\n    .s_axi_rid(),\n    .s_axi_rdata(),\n    .s_axi_rresp(),\n    .s_axi_rlast(),\n    .s_axi_rvalid(),\n    .s_axi_rready(1'D0),\n    .s_axi_injectsbiterr(1'D0),\n    .s_axi_injectdbiterr(1'D0),\n    .s_axi_sbiterr(),\n    .s_axi_dbiterr(),\n    .s_axi_rdaddrecc()\n  );\nendmodule\n", "num_lines": 250}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_d2ea.bd\n//Design : bd_d2ea\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_d2ea,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_d2ea,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_d_microblaze_mcs.hwdef\" *) \nmodule bd_d2ea\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_d2ea_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_d2ea_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_d2ea lmb_bram_I bd_d2ea second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_d2ea_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_d2ea_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_d2ea_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_d2ea_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_d2ea_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_d2ea dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_d2ea_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_d2ea_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_d2ea_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_d2ea_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_d2ea_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Command: generate_target bd_d2ea.bd\n//Design : bd_d2ea\n//Purpose: IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"bd_d2ea,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_d2ea,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}\" *) (* HW_HANDOFF = \"ddr4_core_d_microblaze_mcs.hwdef\" *) \nmodule bd_d2ea\n   (Clk,\n    IO_addr_strobe,\n    IO_address,\n    IO_byte_enable,\n    IO_read_data,\n    IO_read_strobe,\n    IO_ready,\n    IO_write_data,\n    IO_write_strobe,\n    Reset,\n    TRACE_data_access,\n    TRACE_data_address,\n    TRACE_data_byte_enable,\n    TRACE_data_read,\n    TRACE_data_write,\n    TRACE_data_write_value,\n    TRACE_dcache_hit,\n    TRACE_dcache_rdy,\n    TRACE_dcache_read,\n    TRACE_dcache_req,\n    TRACE_delay_slot,\n    TRACE_ex_piperun,\n    TRACE_exception_kind,\n    TRACE_exception_taken,\n    TRACE_icache_hit,\n    TRACE_icache_rdy,\n    TRACE_icache_req,\n    TRACE_instruction,\n    TRACE_jump_hit,\n    TRACE_jump_taken,\n    TRACE_mb_halted,\n    TRACE_mem_piperun,\n    TRACE_msr_reg,\n    TRACE_new_reg_value,\n    TRACE_of_piperun,\n    TRACE_pc,\n    TRACE_pid_reg,\n    TRACE_reg_addr,\n    TRACE_reg_write,\n    TRACE_valid_instr);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.CLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_d2ea_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input Clk;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *) output IO_addr_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *) output [31:0]IO_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *) output [3:0]IO_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *) input [31:0]IO_read_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *) output IO_read_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *) input IO_ready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *) output [31:0]IO_write_data;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *) output IO_write_strobe;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.RESET RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH\" *) input Reset;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *) output TRACE_data_access;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *) output [0:31]TRACE_data_address;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *) output [0:3]TRACE_data_byte_enable;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *) output TRACE_data_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *) output TRACE_data_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *) output [0:31]TRACE_data_write_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *) output TRACE_dcache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *) output TRACE_dcache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *) output TRACE_dcache_read;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *) output TRACE_dcache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *) output TRACE_delay_slot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *) output TRACE_ex_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *) output [0:4]TRACE_exception_kind;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *) output TRACE_exception_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *) output TRACE_icache_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *) output TRACE_icache_rdy;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *) output TRACE_icache_req;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *) output [0:31]TRACE_instruction;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *) output TRACE_jump_hit;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *) output TRACE_jump_taken;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *) output TRACE_mb_halted;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *) output TRACE_mem_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *) output [0:14]TRACE_msr_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *) output [0:31]TRACE_new_reg_value;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *) output TRACE_of_piperun;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *) output [0:31]TRACE_pc;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *) output [0:7]TRACE_pid_reg;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *) output [0:4]TRACE_reg_addr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *) output TRACE_reg_write;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *) output TRACE_valid_instr;\n\n  wire Clk2;\n  wire [0:0]IO_Rst;\n  wire [0:0]LMB_Rst2;\n  wire MB_Reset;\n  wire Reset;\n  wire [0:31]dlmb_ABUS;\n  wire dlmb_ADDRSTROBE;\n  wire [0:3]dlmb_BE;\n  wire dlmb_CE;\n  wire [0:31]dlmb_READDBUS;\n  wire dlmb_READSTROBE;\n  wire dlmb_READY;\n  wire dlmb_UE;\n  wire dlmb_WAIT;\n  wire [0:31]dlmb_WRITEDBUS;\n  wire dlmb_WRITESTROBE;\n  wire [0:31]dlmb_port_2_ADDR;\n  wire dlmb_port_2_CLK;\n  wire [0:31]dlmb_port_2_DIN;\n  wire [31:0]dlmb_port_2_DOUT;\n  wire dlmb_port_2_EN;\n  wire dlmb_port_2_RST;\n  wire [0:3]dlmb_port_2_WE;\n  wire [0:31]dlmb_port_ADDR;\n  wire dlmb_port_CLK;\n  wire [0:31]dlmb_port_DIN;\n  wire [31:0]dlmb_port_DOUT;\n  wire dlmb_port_EN;\n  wire dlmb_port_RST;\n  wire [0:3]dlmb_port_WE;\n  wire [0:31]dlmb_sl_0_ABUS;\n  wire dlmb_sl_0_ADDRSTROBE;\n  wire [0:3]dlmb_sl_0_BE;\n  wire dlmb_sl_0_CE;\n  wire [0:31]dlmb_sl_0_READDBUS;\n  wire dlmb_sl_0_READSTROBE;\n  wire dlmb_sl_0_READY;\n  wire dlmb_sl_0_UE;\n  wire dlmb_sl_0_WAIT;\n  wire [0:31]dlmb_sl_0_WRITEDBUS;\n  wire dlmb_sl_0_WRITESTROBE;\n  wire dlmb_sl_1_CE;\n  wire [0:31]dlmb_sl_1_READDBUS;\n  wire dlmb_sl_1_READY;\n  wire dlmb_sl_1_UE;\n  wire dlmb_sl_1_WAIT;\n  wire dlmb_sl_2_CE;\n  wire [0:31]dlmb_sl_2_READDBUS;\n  wire dlmb_sl_2_READY;\n  wire dlmb_sl_2_UE;\n  wire dlmb_sl_2_WAIT;\n  wire [0:31]ilmb_ABUS;\n  wire ilmb_ADDRSTROBE;\n  wire ilmb_CE;\n  wire [0:31]ilmb_READDBUS;\n  wire ilmb_READSTROBE;\n  wire ilmb_READY;\n  wire ilmb_UE;\n  wire ilmb_WAIT;\n  wire [0:31]ilmb_port_2_ADDR;\n  wire ilmb_port_2_CLK;\n  wire [0:31]ilmb_port_2_DIN;\n  wire [31:0]ilmb_port_2_DOUT;\n  wire ilmb_port_2_EN;\n  wire ilmb_port_2_RST;\n  wire [0:3]ilmb_port_2_WE;\n  wire [0:31]ilmb_port_ADDR;\n  wire ilmb_port_CLK;\n  wire [0:31]ilmb_port_DIN;\n  wire [31:0]ilmb_port_DOUT;\n  wire ilmb_port_EN;\n  wire ilmb_port_RST;\n  wire [0:3]ilmb_port_WE;\n  wire [0:31]ilmb_sl_0_ABUS;\n  wire ilmb_sl_0_ADDRSTROBE;\n  wire [0:3]ilmb_sl_0_BE;\n  wire ilmb_sl_0_CE;\n  wire [0:31]ilmb_sl_0_READDBUS;\n  wire ilmb_sl_0_READSTROBE;\n  wire ilmb_sl_0_READY;\n  wire ilmb_sl_0_UE;\n  wire ilmb_sl_0_WAIT;\n  wire [0:31]ilmb_sl_0_WRITEDBUS;\n  wire ilmb_sl_0_WRITESTROBE;\n  wire ilmb_sl_1_CE;\n  wire [0:31]ilmb_sl_1_READDBUS;\n  wire ilmb_sl_1_READY;\n  wire ilmb_sl_1_UE;\n  wire ilmb_sl_1_WAIT;\n  wire [31:0]iomodule_0_IO_ADDRESS;\n  wire iomodule_0_IO_ADDR_STROBE;\n  wire [3:0]iomodule_0_IO_BYTE_ENABLE;\n  wire iomodule_0_IO_READY;\n  wire [31:0]iomodule_0_IO_READ_DATA;\n  wire iomodule_0_IO_READ_STROBE;\n  wire [31:0]iomodule_0_IO_WRITE_DATA;\n  wire iomodule_0_IO_WRITE_STROBE;\n  wire microblaze_I_Trace_DATA_ACCESS;\n  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;\n  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;\n  wire microblaze_I_Trace_DATA_READ;\n  wire microblaze_I_Trace_DATA_WRITE;\n  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;\n  wire microblaze_I_Trace_DCACHE_HIT;\n  wire microblaze_I_Trace_DCACHE_RDY;\n  wire microblaze_I_Trace_DCACHE_READ;\n  wire microblaze_I_Trace_DCACHE_REQ;\n  wire microblaze_I_Trace_DELAY_SLOT;\n  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;\n  wire microblaze_I_Trace_EXCEPTION_TAKEN;\n  wire microblaze_I_Trace_EX_PIPERUN;\n  wire microblaze_I_Trace_ICACHE_HIT;\n  wire microblaze_I_Trace_ICACHE_RDY;\n  wire microblaze_I_Trace_ICACHE_REQ;\n  wire [0:31]microblaze_I_Trace_INSTRUCTION;\n  wire microblaze_I_Trace_JUMP_HIT;\n  wire microblaze_I_Trace_JUMP_TAKEN;\n  wire microblaze_I_Trace_MB_HALTED;\n  wire microblaze_I_Trace_MEM_PIPERUN;\n  wire [0:14]microblaze_I_Trace_MSR_REG;\n  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;\n  wire microblaze_I_Trace_OF_PIPERUN;\n  wire [0:31]microblaze_I_Trace_PC;\n  wire [0:7]microblaze_I_Trace_PID_REG;\n  wire [0:4]microblaze_I_Trace_REG_ADDR;\n  wire microblaze_I_Trace_REG_WRITE;\n  wire microblaze_I_Trace_VALID_INSTR;\n\n  assign Clk2 = Clk;\n  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;\n  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;\n  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;\n  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;\n  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;\n  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;\n  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;\n  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;\n  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;\n  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;\n  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;\n  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;\n  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;\n  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;\n  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;\n  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;\n  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;\n  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;\n  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;\n  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;\n  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;\n  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;\n  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;\n  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;\n  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;\n  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;\n  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;\n  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;\n  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;\n  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;\n  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;\n  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;\n  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;\n  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;\n  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;\n  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;\n  assign iomodule_0_IO_READY = IO_ready;\n  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];\n  bd_d2ea_dlmb_0 dlmb\n       (.LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_CE(dlmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(dlmb_READDBUS),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Ready(dlmb_READY),\n        .LMB_UE(dlmb_UE),\n        .LMB_Wait(dlmb_WAIT),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .M_ABus(dlmb_ABUS),\n        .M_AddrStrobe(dlmb_ADDRSTROBE),\n        .M_BE(dlmb_BE),\n        .M_DBus(dlmb_WRITEDBUS),\n        .M_ReadStrobe(dlmb_READSTROBE),\n        .M_WriteStrobe(dlmb_WRITESTROBE),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),\n        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),\n        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),\n        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),\n        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));\n  (* BMM_INFO_ADDRESS_SPACE = \"byte  0x00000000 32 >  bd_d2ea lmb_bram_I bd_d2ea second_lmb_bram_I\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_d2ea_dlmb_cntlr_0 dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_ADDR),\n        .BRAM_Clk_A(dlmb_port_CLK),\n        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_DIN),\n        .BRAM_EN_A(dlmb_port_EN),\n        .BRAM_Rst_A(dlmb_port_RST),\n        .BRAM_WEN_A(dlmb_port_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_0_CE),\n        .Sl_DBus(dlmb_sl_0_READDBUS),\n        .Sl_Ready(dlmb_sl_0_READY),\n        .Sl_UE(dlmb_sl_0_UE),\n        .Sl_Wait(dlmb_sl_0_WAIT));\n  bd_d2ea_ilmb_0 ilmb\n       (.LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_CE(ilmb_CE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadDBus(ilmb_READDBUS),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Ready(ilmb_READY),\n        .LMB_UE(ilmb_UE),\n        .LMB_Wait(ilmb_WAIT),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .M_ABus(ilmb_ABUS),\n        .M_AddrStrobe(ilmb_ADDRSTROBE),\n        .M_BE({1'b0,1'b0,1'b0,1'b0}),\n        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .M_ReadStrobe(ilmb_READSTROBE),\n        .M_WriteStrobe(1'b0),\n        .SYS_Rst(LMB_Rst2),\n        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),\n        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),\n        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),\n        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),\n        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));\n  bd_d2ea_ilmb_cntlr_0 ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_ADDR),\n        .BRAM_Clk_A(ilmb_port_CLK),\n        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_DIN),\n        .BRAM_EN_A(ilmb_port_EN),\n        .BRAM_Rst_A(ilmb_port_RST),\n        .BRAM_WEN_A(ilmb_port_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_0_CE),\n        .Sl_DBus(ilmb_sl_0_READDBUS),\n        .Sl_Ready(ilmb_sl_0_READY),\n        .Sl_UE(ilmb_sl_0_UE),\n        .Sl_Wait(ilmb_sl_0_WAIT));\n  bd_d2ea_iomodule_0_0 iomodule_0\n       (.Clk(Clk2),\n        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),\n        .IO_Address(iomodule_0_IO_ADDRESS),\n        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),\n        .IO_Read_Data(iomodule_0_IO_READ_DATA),\n        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),\n        .IO_Ready(iomodule_0_IO_READY),\n        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),\n        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Rst(IO_Rst),\n        .Sl_CE(dlmb_sl_1_CE),\n        .Sl_DBus(dlmb_sl_1_READDBUS),\n        .Sl_Ready(dlmb_sl_1_READY),\n        .Sl_UE(dlmb_sl_1_UE),\n        .Sl_Wait(dlmb_sl_1_WAIT));\n  bd_d2ea_lmb_bram_I_0 lmb_bram_I\n       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),\n        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),\n        .clka(dlmb_port_CLK),\n        .clkb(ilmb_port_CLK),\n        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),\n        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),\n        .douta(dlmb_port_DOUT),\n        .doutb(ilmb_port_DOUT),\n        .ena(dlmb_port_EN),\n        .enb(ilmb_port_EN),\n        .rsta(dlmb_port_RST),\n        .rstb(ilmb_port_RST),\n        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),\n        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));\n  (* BMM_INFO_PROCESSOR = \"microblaze-le > bd_d2ea dlmb_cntlr\" *) \n  (* KEEP_HIERARCHY = \"yes\" *) \n  bd_d2ea_microblaze_I_0 microblaze_I\n       (.Byte_Enable(dlmb_BE),\n        .Clk(Clk2),\n        .DCE(dlmb_CE),\n        .DReady(dlmb_READY),\n        .DUE(dlmb_UE),\n        .DWait(dlmb_WAIT),\n        .D_AS(dlmb_ADDRSTROBE),\n        .Data_Addr(dlmb_ABUS),\n        .Data_Read(dlmb_READDBUS),\n        .Data_Write(dlmb_WRITEDBUS),\n        .ICE(ilmb_CE),\n        .IFetch(ilmb_READSTROBE),\n        .IReady(ilmb_READY),\n        .IUE(ilmb_UE),\n        .IWAIT(ilmb_WAIT),\n        .I_AS(ilmb_ADDRSTROBE),\n        .Instr(ilmb_READDBUS),\n        .Instr_Addr(ilmb_ABUS),\n        .Interrupt(1'b0),\n        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n        .Read_Strobe(dlmb_READSTROBE),\n        .Reset(MB_Reset),\n        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),\n        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),\n        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),\n        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),\n        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),\n        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),\n        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),\n        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),\n        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),\n        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),\n        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),\n        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),\n        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),\n        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),\n        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),\n        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),\n        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),\n        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),\n        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),\n        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),\n        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),\n        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),\n        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),\n        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),\n        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),\n        .Trace_PC(microblaze_I_Trace_PC),\n        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),\n        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),\n        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),\n        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),\n        .Write_Strobe(dlmb_WRITESTROBE));\n  bd_d2ea_rst_0_0 rst_0\n       (.aux_reset_in(1'b1),\n        .bus_struct_reset(LMB_Rst2),\n        .dcm_locked(1'b1),\n        .ext_reset_in(Reset),\n        .mb_debug_sys_rst(1'b0),\n        .mb_reset(MB_Reset),\n        .peripheral_reset(IO_Rst),\n        .slowest_sync_clk(Clk2));\n  (* BMM_INFO_ADDRESS_RANGE = \" \" *) \n  bd_d2ea_second_dlmb_cntlr_0 second_dlmb_cntlr\n       (.BRAM_Addr_A(dlmb_port_2_ADDR),\n        .BRAM_Clk_A(dlmb_port_2_CLK),\n        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(dlmb_port_2_DIN),\n        .BRAM_EN_A(dlmb_port_2_EN),\n        .BRAM_Rst_A(dlmb_port_2_RST),\n        .BRAM_WEN_A(dlmb_port_2_WE),\n        .LMB_ABus(dlmb_sl_0_ABUS),\n        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),\n        .LMB_BE(dlmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),\n        .Sl_CE(dlmb_sl_2_CE),\n        .Sl_DBus(dlmb_sl_2_READDBUS),\n        .Sl_Ready(dlmb_sl_2_READY),\n        .Sl_UE(dlmb_sl_2_UE),\n        .Sl_Wait(dlmb_sl_2_WAIT));\n  bd_d2ea_second_ilmb_cntlr_0 second_ilmb_cntlr\n       (.BRAM_Addr_A(ilmb_port_2_ADDR),\n        .BRAM_Clk_A(ilmb_port_2_CLK),\n        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),\n        .BRAM_Dout_A(ilmb_port_2_DIN),\n        .BRAM_EN_A(ilmb_port_2_EN),\n        .BRAM_Rst_A(ilmb_port_2_RST),\n        .BRAM_WEN_A(ilmb_port_2_WE),\n        .LMB_ABus(ilmb_sl_0_ABUS),\n        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),\n        .LMB_BE(ilmb_sl_0_BE),\n        .LMB_Clk(Clk2),\n        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),\n        .LMB_Rst(LMB_Rst2),\n        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),\n        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),\n        .Sl_CE(ilmb_sl_1_CE),\n        .Sl_DBus(ilmb_sl_1_READDBUS),\n        .Sl_Ready(ilmb_sl_1_READY),\n        .Sl_UE(ilmb_sl_1_UE),\n        .Sl_Wait(ilmb_sl_1_WAIT));\n  bd_d2ea_second_lmb_bram_I_0 second_lmb_bram_I\n       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),\n        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),\n        .clka(dlmb_port_2_CLK),\n        .clkb(ilmb_port_2_CLK),\n        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),\n        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),\n        .douta(dlmb_port_2_DOUT),\n        .doutb(ilmb_port_2_DOUT),\n        .ena(dlmb_port_2_EN),\n        .enb(ilmb_port_2_EN),\n        .rsta(dlmb_port_2_RST),\n        .rstb(ilmb_port_2_RST),\n        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),\n        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));\nendmodule\n", "num_lines": 514}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_d_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_d2ea_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_d2ea inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 225}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0\n// IP Revision: 14\n\n(* X_CORE_INFO = \"bd_d2ea,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"ddr4_core_d_microblaze_mcs,bd_d2ea,{}\" *)\n(* CORE_GENERATION_INFO = \"ddr4_core_d_microblaze_mcs,bd_d2ea,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze_mcs,x_ipVersion=3.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,JTAG_CHAIN=2,MICROBLAZE_INSTANCE=microblaze_0,AVOID_PRIMITIVES=0,PATH=mcs_0,FREQ=100.0,OPTIMIZATION=1,DEBUG_ENABLED=0,USE_BSCAN=0,BSCANID=76547328,TRACE=1,ECC=0,MEMSIZE=98304,MEMTYPE=0,USE_IO_BUS=1,USE_UART_RX=0,USE_UART_TX=0,UART_BAUDRATE=9600,UART_PROG_BAUDRATE=0,UART_DATA_BITS=8,UART_USE_PARITY\\\n=0,UART_ODD_PARITY=0,UART_RX_INTERRUPT=0,UART_TX_INTERRUPT=0,UART_ERROR_INTERRUPT=0,USE_FIT1=0,FIT1_No_CLOCKS=6216,FIT1_INTERRUPT=0,USE_FIT2=0,FIT2_No_CLOCKS=6216,FIT2_INTERRUPT=0,USE_FIT3=0,FIT3_No_CLOCKS=6216,FIT3_INTERRUPT=0,USE_FIT4=0,FIT4_No_CLOCKS=6216,FIT4_INTERRUPT=0,USE_PIT1=0,PIT1_SIZE=32,PIT1_READABLE=1,PIT1_PRESCALER=0,PIT1_INTERRUPT=0,USE_PIT2=0,PIT2_SIZE=32,PIT2_READABLE=1,PIT2_PRESCALER=0,PIT2_INTERRUPT=0,USE_PIT3=0,PIT3_SIZE=32,PIT3_READABLE=1,PIT3_PRESCALER=0,PIT3_INTERRUPT=0,US\\\nE_PIT4=0,PIT4_SIZE=32,PIT4_READABLE=1,PIT4_PRESCALER=0,PIT4_INTERRUPT=0,USE_GPO1=0,GPO1_SIZE=32,GPO1_INIT=0x00000000,USE_GPO2=0,GPO2_SIZE=32,GPO2_INIT=0x00000000,USE_GPO3=0,GPO3_SIZE=32,GPO3_INIT=0x00000000,USE_GPO4=0,GPO4_SIZE=32,GPO4_INIT=0x00000000,USE_GPI1=0,GPI1_SIZE=32,GPI1_INTERRUPT=0,USE_GPI2=0,GPI2_SIZE=32,GPI2_INTERRUPT=0,USE_GPI3=0,GPI3_SIZE=32,GPI3_INTERRUPT=0,USE_GPI4=0,GPI4_SIZE=32,GPI4_INTERRUPT=0,INTC_USE_EXT_INTR=0,INTC_INTR_SIZE=1,INTC_LEVEL_EDGE=0x0000,INTC_POSITIVE=0xFFFF,INT\\\nC_ASYNC_INTR=0xFFFF,INTC_NUM_SYNC_FF=2,Component_Name=ddr4_core_d_microblaze_mcs,USE_BOARD_FLOW=false,CLK_BOARD_INTERFACE=Custom,RESET_BOARD_INTERFACE=Custom,GPIO1_BOARD_INTERFACE=Custom,GPIO2_BOARD_INTERFACE=Custom,GPIO3_BOARD_INTERFACE=Custom,GPIO4_BOARD_INTERFACE=Custom,UART_BOARD_INTERFACE=Custom}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule ddr4_core_d_microblaze_mcs (\n  Clk,\n  Reset,\n  TRACE_data_access,\n  TRACE_data_address,\n  TRACE_data_byte_enable,\n  TRACE_data_read,\n  TRACE_data_write,\n  TRACE_data_write_value,\n  TRACE_dcache_hit,\n  TRACE_dcache_rdy,\n  TRACE_dcache_read,\n  TRACE_dcache_req,\n  TRACE_delay_slot,\n  TRACE_ex_piperun,\n  TRACE_exception_kind,\n  TRACE_exception_taken,\n  TRACE_icache_hit,\n  TRACE_icache_rdy,\n  TRACE_icache_req,\n  TRACE_instruction,\n  TRACE_jump_hit,\n  TRACE_jump_taken,\n  TRACE_mb_halted,\n  TRACE_mem_piperun,\n  TRACE_msr_reg,\n  TRACE_new_reg_value,\n  TRACE_of_piperun,\n  TRACE_pc,\n  TRACE_pid_reg,\n  TRACE_reg_addr,\n  TRACE_reg_write,\n  TRACE_valid_instr,\n  IO_addr_strobe,\n  IO_address,\n  IO_byte_enable,\n  IO_read_data,\n  IO_read_strobe,\n  IO_ready,\n  IO_write_data,\n  IO_write_strobe\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_d2ea_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.Clk CLK\" *)\ninput wire Clk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.Reset RST\" *)\ninput wire Reset;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS\" *)\noutput wire TRACE_data_access;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS\" *)\noutput wire [0 : 31] TRACE_data_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE\" *)\noutput wire [0 : 3] TRACE_data_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ\" *)\noutput wire TRACE_data_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE\" *)\noutput wire TRACE_data_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE\" *)\noutput wire [0 : 31] TRACE_data_write_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT\" *)\noutput wire TRACE_dcache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY\" *)\noutput wire TRACE_dcache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ\" *)\noutput wire TRACE_dcache_read;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ\" *)\noutput wire TRACE_dcache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT\" *)\noutput wire TRACE_delay_slot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN\" *)\noutput wire TRACE_ex_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND\" *)\noutput wire [0 : 4] TRACE_exception_kind;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN\" *)\noutput wire TRACE_exception_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT\" *)\noutput wire TRACE_icache_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY\" *)\noutput wire TRACE_icache_rdy;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ\" *)\noutput wire TRACE_icache_req;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION\" *)\noutput wire [0 : 31] TRACE_instruction;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT\" *)\noutput wire TRACE_jump_hit;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN\" *)\noutput wire TRACE_jump_taken;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED\" *)\noutput wire TRACE_mb_halted;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN\" *)\noutput wire TRACE_mem_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG\" *)\noutput wire [0 : 14] TRACE_msr_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE\" *)\noutput wire [0 : 31] TRACE_new_reg_value;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN\" *)\noutput wire TRACE_of_piperun;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PC\" *)\noutput wire [0 : 31] TRACE_pc;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE PID_REG\" *)\noutput wire [0 : 7] TRACE_pid_reg;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR\" *)\noutput wire [0 : 4] TRACE_reg_addr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE\" *)\noutput wire TRACE_reg_write;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR\" *)\noutput wire TRACE_valid_instr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE\" *)\noutput wire IO_addr_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS\" *)\noutput wire [31 : 0] IO_address;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE\" *)\noutput wire [3 : 0] IO_byte_enable;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA\" *)\ninput wire [31 : 0] IO_read_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE\" *)\noutput wire IO_read_strobe;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO READY\" *)\ninput wire IO_ready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA\" *)\noutput wire [31 : 0] IO_write_data;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE\" *)\noutput wire IO_write_strobe;\n\n  bd_d2ea inst (\n    .Clk(Clk),\n    .Reset(Reset),\n    .TRACE_data_access(TRACE_data_access),\n    .TRACE_data_address(TRACE_data_address),\n    .TRACE_data_byte_enable(TRACE_data_byte_enable),\n    .TRACE_data_read(TRACE_data_read),\n    .TRACE_data_write(TRACE_data_write),\n    .TRACE_data_write_value(TRACE_data_write_value),\n    .TRACE_dcache_hit(TRACE_dcache_hit),\n    .TRACE_dcache_rdy(TRACE_dcache_rdy),\n    .TRACE_dcache_read(TRACE_dcache_read),\n    .TRACE_dcache_req(TRACE_dcache_req),\n    .TRACE_delay_slot(TRACE_delay_slot),\n    .TRACE_ex_piperun(TRACE_ex_piperun),\n    .TRACE_exception_kind(TRACE_exception_kind),\n    .TRACE_exception_taken(TRACE_exception_taken),\n    .TRACE_icache_hit(TRACE_icache_hit),\n    .TRACE_icache_rdy(TRACE_icache_rdy),\n    .TRACE_icache_req(TRACE_icache_req),\n    .TRACE_instruction(TRACE_instruction),\n    .TRACE_jump_hit(TRACE_jump_hit),\n    .TRACE_jump_taken(TRACE_jump_taken),\n    .TRACE_mb_halted(TRACE_mb_halted),\n    .TRACE_mem_piperun(TRACE_mem_piperun),\n    .TRACE_msr_reg(TRACE_msr_reg),\n    .TRACE_new_reg_value(TRACE_new_reg_value),\n    .TRACE_of_piperun(TRACE_of_piperun),\n    .TRACE_pc(TRACE_pc),\n    .TRACE_pid_reg(TRACE_pid_reg),\n    .TRACE_reg_addr(TRACE_reg_addr),\n    .TRACE_reg_write(TRACE_reg_write),\n    .TRACE_valid_instr(TRACE_valid_instr),\n    .IO_addr_strobe(IO_addr_strobe),\n    .IO_address(IO_address),\n    .IO_byte_enable(IO_byte_enable),\n    .IO_read_data(IO_read_data),\n    .IO_read_strobe(IO_read_strobe),\n    .IO_ready(IO_ready),\n    .IO_write_data(IO_write_data),\n    .IO_write_strobe(IO_write_strobe)\n  );\nendmodule\n", "num_lines": 229}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_master #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_SUPPORTS_NARROW = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1,\n   parameter [C_AXI_ADDR_WIDTH-1:0] C_AXI_ADDR = 0,  // Base address\n   parameter integer C_NUM_ADDR = 1,  // Number of address iterations; range 1..2**16 (fixed increment = 32'h10000\n   parameter integer C_NUM_ID = 1,  // Number of ID iterations; range 1..2**C_ID_WIDTH (base = 0; fixed increment = 1)\n   parameter integer C_NUM_LEN = 1,  // Number of LEN iterations; range 1..9 (base = 0; value = 2**i - 1)\n   parameter integer C_NUM_TRANS = 1  // Number of transactions; range >=1 (read and write)\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_awvalid,\n  input  wire                            m_axi_awready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_awburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_awlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_awlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_awid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]    m_axi_awuser = 'b0,\n  /**************** Write Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_wid,\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]      m_axi_wdata,\n  (* dont_touch=\"true\" *) output reg [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb = {(C_AXI_DATA_WIDTH/8){1'b1}},\n  (* dont_touch=\"true\" *) output wire                             m_axi_wvalid,\n  input  wire                            m_axi_wready,\n  (* dont_touch=\"true\" *) output wire                             m_axi_wlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]     m_axi_wuser = 'b0,\n  /**************** Write Response Channel Signals ****************/\n  input  wire [2-1:0]                    m_axi_bresp,\n  input  wire                            m_axi_bvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_bready,\n  input  wire [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]     m_axi_buser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_bid,\n  /**************** Read Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_arvalid,\n  input  wire                            m_axi_arready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_arburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_arlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_arlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_arid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]    m_axi_aruser = 'b0,\n  /**************** Read Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]      m_axi_rdata,\n  input  wire [2-1:0]                    m_axi_rresp,\n  input  wire                            m_axi_rvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_rready,\n  input  wire                            m_axi_rlast,\n  input  wire [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]     m_axi_ruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_rid,\n  /**************** System Signals ****************/\n  input  wire                            aclk,\n  input  wire                            aresetn\n  );\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n  localparam integer  P_NUM_ID_LOG = f_ceil_log2(C_NUM_ID);\n  localparam integer  P_NUM_ADDR_LOG = f_ceil_log2(C_NUM_ADDR);\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL==0 ? 8 : C_AXI_PROTOCOL==1 ? 4 : 1);\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer               P_M_AXI_DATA_BYTES = (C_AXI_DATA_WIDTH / 8);\n  localparam integer               P_M_AXI_DONE_WIDTH = f_ceil_log2(C_NUM_TRANS<2?2:C_NUM_TRANS);\n  localparam integer               P_M_AXI_SIZE = f_ceil_log2(C_AXI_DATA_WIDTH)-3;\n\n  /**************** Internal Wires/Regs - Global ****************/\n   wire                            done;\n    wire                            dummy ;\n  reg                         done_i;\n  reg                         done_sel;\n  wire                         done_cycle;\n  reg                          done_d1 = 1'b0;\n  reg                   areset = 1'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] arcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] rcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [3:0]                    acc_r_i = 4'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] awcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] wcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] bcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [2:0]                    acc_b_i = 3'b0;\n\n  // Register Reset\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    \n    /**************** Internal Wires/Regs - Read Channels ****************/\n    wire                         read_xaction_done_i;\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_arid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_ADDR_WIDTH:0]      araddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  arprot_i = 3'b0;\n    reg [3-1:0]                  arsize_i = 3'b0;\n    reg [2-1:0]                  arburst_i = 2'b0;\n    reg [4-1:0]                  arcache_i = 4'b0;\n    reg [2-1:0]                  arlock_i = 2'b0;\n    reg [P_LEN_WIDTH-1:0]     arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [4-1:0]                  arqos_i = 4'b0;\n    reg [P_ID_WIDTH-1:0]        arid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [2-1:0]                  rresp_i = 2'b00;\n    reg [C_AXI_RUSER_WIDTH:0]   ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      rid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_arvalid_i = 1'b0;\n    reg                        m_axi_rready_i = 1'b0;\n    reg [P_NUM_ADDR_LOG:0]    araddr_cnt = 0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign read_xaction_done_i = m_axi_rvalid && m_axi_rready_i && ((C_AXI_PROTOCOL==2)?1'b1:m_axi_rlast);\n    assign m_axi_arvalid = m_axi_arvalid_i;\n    assign m_axi_rready = m_axi_rready_i;\n    assign m_axi_araddr = m_axi_araddr_i;\n    assign m_axi_arlen = m_axi_arlen_i;\n    always @(posedge aclk) begin\n      m_axi_arprot <= dummy ? arprot_i : 3'b000;\n      m_axi_arsize <= dummy ? arsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_arburst <= dummy ? arburst_i : 2'b01;\n      m_axi_arlock <= dummy ? arlock_i : 1'b0;\n      m_axi_arcache <= dummy ? arcache_i : 4'h3;\n      m_axi_arqos <= dummy  ? arqos_i : 4'h0;\n      m_axi_aruser <= dummy ? aruser_i : 0;\n    end\n  \n    //**********************************************\n    // Read Channel: ARVALID, ARADDR, ARLEN, RREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_arvalid_i <= 1'b0;\n        arcnt_i <= C_NUM_TRANS;\n        m_axi_arlen_i <= 0;\n        m_axi_araddr_i <= C_AXI_ADDR;\n        m_axi_arid_i <= 1;\n        araddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_arready & m_axi_arvalid_i) begin\n          arcnt_i <= arcnt_i - 1;\n          if (araddr_cnt == 1) begin\n            m_axi_araddr_i <= dummy ? araddr_i : C_AXI_ADDR;\n            araddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_araddr_i <= m_axi_araddr_i + 32'h10000;\n            araddr_cnt <= araddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_arlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_arlen_i <= dummy ? arlen_i : 0;\n          end else begin\n            m_axi_arlen_i <= (m_axi_arlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_arid_i == C_NUM_ID)) begin\n            m_axi_arid <= dummy ? arid_i : 0;\n            m_axi_arid_i <= 1;\n          end else begin\n            m_axi_arid <= m_axi_arid_i;\n            m_axi_arid_i <= m_axi_arid_i + 1;\n          end\n          if (arcnt_i == 1) begin\n            m_axi_arvalid_i <= 1'b0;\n          end\n        end else if (arcnt_i != 0) begin\n          m_axi_arvalid_i <= 1'b1;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      araddr_i <= {araddr_i, ~araddr_i[C_AXI_ADDR_WIDTH]};\n      arprot_i <= {arprot_i, ~arprot_i[3-1]};\n      arlen_i <= {arlen_i, ~arlen_i[P_LEN_WIDTH-1]};\n      arsize_i <= {arsize_i, ~arsize_i[3-1]};\n      arburst_i <= {arburst_i, ~arburst_i[2-1]};\n      arlock_i <= {arlock_i, ~arlock_i[2-1]};\n      arcache_i <= {arcache_i, ~arcache_i[4-1]};\n      arqos_i <= {arqos_i, ~arqos_i[4-1]};\n      aruser_i <= {aruser_i, ~aruser_i[C_AXI_ARUSER_WIDTH]};\n      arid_i <= {arid_i, ~arid_i[P_ID_WIDTH-1]};\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        m_axi_rready_i <= 1'b0;\n        rcnt_i <= C_NUM_TRANS;\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        rresp_i <= {2{1'b0}};\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n        rid_i <= {P_ID_WIDTH{1'b0}};\n        acc_r_i <= 4'b0;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_rvalid & m_axi_rready_i) begin\n          m_axi_rready_i <= 1'b0;\n          rdata_i <= m_axi_rdata;\n            acc_r_i[0] <= rdata_i[0];\n          rresp_i <= m_axi_rresp;\n            acc_r_i[1] <= rresp_i[0];\n          ruser_i <= m_axi_ruser;\n            acc_r_i[2] <= ruser_i[0];\n          rid_i <= m_axi_rid;\n            acc_r_i[3] <= rid_i[0];\n          if (m_axi_rlast) begin\n            rcnt_i <= rcnt_i - 1;\n          end\n        end else begin\n          rdata_i <= rdata_i>>1;\n          rresp_i <= rresp_i>>1;\n          ruser_i <= ruser_i>>1;\n          rid_i <= rid_i>>1;\n          acc_r_i <= acc_r_i>>1;\n          if (m_axi_rvalid) begin\n            m_axi_rready_i <= 1'b1;\n          end\n        end\n      end\n    end\n    \n    assign dummy = rdata_i[0];\n    \n    \n\n    /**************** Internal Wires/Regs - Write Channels ****************/\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_awid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [8-1:0]                  xfer_w_i = 8'h00;\n    wire                         write_burst_done_i;\n    reg [C_AXI_ADDR_WIDTH:0]      awaddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  awprot_i = 3'b0;\n    reg [P_LEN_WIDTH-1:0]     awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [3-1:0]                  awsize_i = 3'b0;\n    reg [2-1:0]                  awburst_i = 2'b0;\n    reg [4-1:0]                  awcache_i = 4'b0;\n    reg [2-1:0]                  awlock_i = 2'b0;\n    reg [4-1:0]                  awqos_i = 4'b0;\n    reg [P_ID_WIDTH:0]        awid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_AWUSER_WIDTH:0]    awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg [P_M_AXI_DATA_BYTES-1:0] wstrb_i = {P_M_AXI_DATA_BYTES{1'b1}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]        wid_i = {P_ID_WIDTH{1'b0}};\n    reg [2-1:0]                  bresp_i = 2'b00;\n    reg [C_AXI_BUSER_WIDTH:0]   buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      bid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_awvalid_i = 1'b0;\n    reg                        m_axi_wvalid_i = 1'b0;\n    reg                        m_axi_bready_i = 1'b0;\n    reg                        m_axi_wlast_i = 1'b0;\n    reg                        m_axi_wid_i = {P_ID_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]     wlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [P_NUM_ADDR_LOG:0]    awaddr_cnt = 0;\n  \n    /**************** Assign Write Channel Outputs ****************/\n    assign m_axi_wdata = {wdata_i, done};\n    assign write_burst_done_i = m_axi_wready && m_axi_wvalid_i && ((C_AXI_PROTOCOL==2) || m_axi_wlast_i);\n    assign m_axi_awvalid = m_axi_awvalid_i;\n    assign m_axi_wvalid = m_axi_wvalid_i;\n    assign m_axi_bready = m_axi_bready_i;\n    assign m_axi_wlast = m_axi_wlast_i;\n    assign m_axi_awaddr = m_axi_awaddr_i;\n    assign m_axi_awlen = m_axi_awlen_i;\n    assign m_axi_wid = m_axi_wid_i;\n    always @(posedge aclk) begin\n      m_axi_awprot <= dummy ? awprot_i : 3'b000;\n      m_axi_awsize <= dummy ? awsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_awburst <= dummy ? awburst_i : 2'b01;\n      m_axi_awlock <= dummy ? awlock_i : 1'b0;\n      m_axi_awcache <= dummy ? awcache_i : 4'h3;\n      m_axi_awqos <= dummy ? awqos_i : 4'h0;\n      m_axi_wstrb <= dummy ? wstrb_i : {P_M_AXI_DATA_BYTES{1'b1}};\n      m_axi_awuser <= dummy ?  awuser_i : 0;\n      m_axi_wuser <= dummy ?  wuser_i : 0;\n    end\n  \n    //**********************************************\n    // Write Channel: AWVALID, AWADDR, AWLEN, WVALID, WLAST, BREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_awvalid_i <= 1'b0;\n        m_axi_wvalid_i <= 1'b0;\n        awcnt_i <= C_NUM_TRANS;\n        wcnt_i <= C_NUM_TRANS;\n        xfer_w_i <= 8'h00;\n        m_axi_awlen_i <= 0;\n        m_axi_awaddr_i <= C_AXI_ADDR;\n        m_axi_awid_i <= 1;\n        m_axi_wid_i <= 0;\n        m_axi_wlast_i <= 1'b0;\n        wlen_i <= 0;\n        wid_i <= 0;\n        awaddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_awvalid_i <= 1'b0;\n          awcnt_i <= awcnt_i - 1;\n          if (awaddr_cnt == 1) begin\n            m_axi_awaddr_i <= dummy ? awaddr_i : C_AXI_ADDR;\n            awaddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_awaddr_i <= m_axi_awaddr_i + 32'h10000;\n            awaddr_cnt <= awaddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_awlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_awlen_i <= dummy ? awlen_i : 0;\n          end else begin\n            m_axi_awlen_i <= (m_axi_awlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_awid_i == C_NUM_ID)) begin\n            m_axi_awid <= dummy ? awid_i : 0;\n            m_axi_awid_i <= 1;\n          end else begin\n            m_axi_awid <= m_axi_awid_i;\n            m_axi_awid_i <= m_axi_awid_i + 1;\n          end\n        end else if (~m_axi_wvalid_i) begin\n          if (awcnt_i != 0) begin\n            m_axi_awvalid_i <= 1'b1;\n          end\n        end\n  \n        /**************** Write Data Channel ****************/\n\n        if (m_axi_wready && m_axi_wvalid_i) begin\n          xfer_w_i <= xfer_w_i - 1'b1;\n          if (m_axi_wlast_i) begin\n            m_axi_wvalid_i <= 1'b0;\n            wcnt_i <= wcnt_i - 1'b1;\n          end else begin\n            m_axi_wlast_i <=  (xfer_w_i == 1);\n          end\n        end else if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_wvalid_i <= 1'b1;\n          xfer_w_i <= m_axi_awlen_i;\n          m_axi_wlast_i <= (m_axi_awlen_i==0);\n          m_axi_wid_i <= m_axi_awid_i;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: WDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        wdata_i <= (m_axi_wvalid_i && m_axi_wready) ? {wdata_i[C_AXI_DATA_WIDTH-2 : 0], ~wdata_i[C_AXI_DATA_WIDTH-1]} : wdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      awaddr_i <= {awaddr_i, ~awaddr_i[C_AXI_ADDR_WIDTH]};\n      awprot_i <= {awprot_i[3-2:0], ~awprot_i[3-1]};\n      wstrb_i <= {wstrb_i, ~wstrb_i[C_AXI_DATA_WIDTH/8-1]};\n      awlen_i <= {awlen_i, ~awlen_i[P_LEN_WIDTH-1]};\n      awsize_i <= {awsize_i, ~awsize_i[3-1]};\n      awburst_i <= {awburst_i, ~awburst_i[2-1]};\n      awlock_i <= {awlock_i, ~awlock_i[2-1]};\n      awcache_i <= {awcache_i, ~awcache_i[4-1]};\n      awqos_i <= {awqos_i, ~awqos_i[4-1]};\n      awid_i <= {awid_i, ~awid_i[P_ID_WIDTH-1]};\n      awuser_i <= {awuser_i, ~awuser_i[C_AXI_AWUSER_WIDTH]};\n      wuser_i <= {wuser_i, ~wuser_i[C_AXI_WUSER_WIDTH]};\n    end\n  \n    //**********************************************\n    // Write Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_bready_i <= 1'b0;\n        bcnt_i <= C_NUM_TRANS;\n        bresp_i <= {2{1'b0}};\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n        bid_i <= {P_ID_WIDTH{1'b0}};\n        acc_b_i <= 3'b0;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_bvalid & m_axi_bready_i) begin\n          m_axi_bready_i <= 1'b0;\n          bresp_i <= m_axi_bresp;\n            acc_b_i[0] <= bresp_i[0];\n          buser_i <= m_axi_buser;\n            acc_b_i[1] <= buser_i[0];\n          bid_i <= m_axi_bid;\n            acc_b_i[2] <= bid_i[0];\n          bcnt_i <= bcnt_i - 1;\n        end else begin\n          bresp_i <= bresp_i>>1;\n          buser_i <= buser_i>>1;\n          bid_i <= bid_i>>1;\n          acc_b_i <= acc_b_i>>1;\n          if (m_axi_bvalid) begin\n            m_axi_bready_i <= 1'b1;\n          end\n        end\n      end\n    end\n\n\n  //**********************************************\n  // Assert Done\n  //**********************************************\n  always @(posedge aclk) begin\n    if (~aresetn) begin\n      done_d1 <= 1'b0;\n    end else begin\n      done_d1 <= done_i;\n    end\n  end\n\n  assign done = done_sel ? done_i : done_d1;\n  assign done_cycle = done_i & ~done_d1;\n  \n  always @ * begin\n    if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_readonly_done\n       done_i = rcnt_i==0;\n       done_sel = acc_r_i[0];\n    end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_writeonly_done\n       done_i = bcnt_i==0;\n       done_sel = acc_b_i[0];\n    end else begin : gen_readwrite_done\n       done_i = (rcnt_i==0) && (bcnt_i==0);\n       done_sel = acc_r_i[0] ^ acc_b_i[0];\n    end\n  end\n  \nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n  input  wire [3-1:0]                   s_axi_awprot,\n  input  wire                           s_axi_awvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_awready,\n  input  wire [3-1:0]                   s_axi_awsize,\n  input  wire [2-1:0]                   s_axi_awburst,\n  input  wire [4-1:0]                   s_axi_awcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_awlen,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_awlock,\n  input  wire [4-1:0]                   s_axi_awqos,\n  input  wire [4-1:0]                   s_axi_awregion,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_awid,\n  input  wire [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]   s_axi_awuser,\n  /**************** Write Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n  input  wire                           s_axi_wvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_wready,\n  input  wire                           s_axi_wlast,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_wid,\n  input  wire [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]    s_axi_wuser,\n  /**************** Write Response Channel Signals ****************/\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_bresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_bvalid,\n  input  wire                           s_axi_bready,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]    s_axi_buser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_bid = 'b0,\n  /**************** Read Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n  input  wire [3-1:0]                   s_axi_arprot,\n  input  wire                           s_axi_arvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_arready,\n  input  wire [3-1:0]                   s_axi_arsize,\n  input  wire [2-1:0]                   s_axi_arburst,\n  input  wire [4-1:0]                   s_axi_arcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_arlock,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_arlen,\n  input  wire [4-1:0]                   s_axi_arqos,\n  input  wire [4-1:0]                   s_axi_arregion,\n  input  wire [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]   s_axi_aruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_arid,\n  /**************** Read Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_rresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rvalid,\n  input  wire                           s_axi_rready,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]    s_axi_ruser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_rid = 'b0,\n  /**************** System Signals ****************/\n  input  wire                           aclk,\n  input  wire                           aresetn\n   );\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL == 1) ? 4 : 8;\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer P_S_AXI_DATA_BYTES = 32/8;\n  localparam integer P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n\n  /**************** Internal Wires/Regs - Global ****************/\n  reg                   areset = 1'b0;\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    /**************** Internal Wires/Regs - Read Channels ****************/\n    reg [8-1:0]                   xfer_r_cnt = 8'h00;\n    reg [16-1:0]                  arcnt_i = 16'h0000;\n    wire                          read_xaction_done_i;\n    reg [C_AXI_DATA_WIDTH-1:0]     rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]      arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg                           arvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     araddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   arprot_i = 3'b000;\n    reg [3-1:0]                   arsize_i = 3'b000;\n    reg [2-1:0]                   arburst_i = 2'b00;\n    reg [4-1:0]                   arcache_i = 4'b0000;\n    reg [1-1:0]     arlock_i = 1'b0;\n    reg [4-1:0]                   arqos_i = 4'b0000;\n    reg [4-1:0]                   arregion_i = 4'b0000;\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_RUSER_WIDTH:0]     ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_ar_i = 9'b0;\n    reg                           s_axi_rvalid_i = 1'b0;\n    reg                           s_axi_arready_i = 1'b0;\n    reg                           s_axi_rlast_i = 1'b0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign s_axi_rdata = rdata_i;\n    assign read_xaction_done_i = (s_axi_rready && s_axi_rvalid_i && s_axi_rlast_i);\n    assign s_axi_rvalid = s_axi_rvalid_i;\n    assign s_axi_arready = s_axi_arready_i;\n    assign s_axi_rlast = s_axi_rlast_i;\n    //**********************************************\n    // Read Channel: ARREADY, RVALID, RLAST, RID\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        xfer_r_cnt <= 8'h00;\n        arcnt_i <= 16'h0000;\n        arlen_i <= {P_LEN_WIDTH{1'b0}};\n        s_axi_rlast_i <= 1'b0;\n      end else begin\n        /**************** Read Address Channel ****************/\n        // arready\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_arready_i <= 1'b0;\n          arcnt_i <= arcnt_i + 1'b1;\n        end else if (~s_axi_rvalid_i) begin\n          s_axi_arready_i <= 1'b1;\n        end\n  \n        /**************** Read Data Channel ****************/\n        // rvalid\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_rvalid_i <= 1'b1;\n          s_axi_rid <= s_axi_arid;\n          s_axi_ruser <= ruser_i;\n        end else if(read_xaction_done_i) begin\n          s_axi_rvalid_i <= 1'b0;\n        end\n  \n        // rlast\n        if(s_axi_rready && s_axi_rvalid_i) begin\n          xfer_r_cnt <= xfer_r_cnt - 1;\n          if(xfer_r_cnt == 1) begin\n            s_axi_rlast_i <= 1'b1;\n          end\n        end else if(s_axi_arready_i && s_axi_arvalid) begin\n          xfer_r_cnt <= s_axi_arlen;\n          s_axi_rlast_i <= (s_axi_arlen==0);\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Read Channel: RDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        rdata_i <= (s_axi_rready && s_axi_rvalid_i) ? {rdata_i[C_AXI_DATA_WIDTH-2 : 0], ~rdata_i[C_AXI_DATA_WIDTH-1]} : rdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_rresp <= {2{1'b0}};\n      end else if (~s_axi_rvalid_i) begin\n        s_axi_rresp <= {acc_ar_i[0], 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n      end else begin\n        ruser_i <= (s_axi_arready_i && s_axi_arvalid) ? {ruser_i, ~ruser_i[C_AXI_RUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        araddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        arprot_i <= {3{1'b0}};\n        arsize_i <= {3{1'b0}};\n        arburst_i <= {2{1'b0}};\n        arcache_i <= {4{1'b0}};\n        arlock_i <= {1{1'b0}};\n        arqos_i <= {4{1'b0}};\n        arregion_i <= {4{1'b0}};\n        aruser_i <= {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n        acc_ar_i <= 9'b0;\n      end else if (s_axi_arvalid) begin\n        // Register Inputs\n        araddr_i <= s_axi_araddr;\n          acc_ar_i[0] <= araddr_i[0];\n        arprot_i <= s_axi_arprot;\n          acc_ar_i[1] <= arprot_i[0];\n        arsize_i <= s_axi_arsize;\n          acc_ar_i[2] <= arsize_i[0];\n        arburst_i <= s_axi_arburst;\n          acc_ar_i[3] <= arburst_i[0];\n        arcache_i <= s_axi_arcache;\n          acc_ar_i[4] <= arcache_i[0];\n        arlock_i <= s_axi_arlock;\n          acc_ar_i[5] <= arlock_i[0];\n        arqos_i <= s_axi_arqos;\n          acc_ar_i[6] <= arqos_i[0];\n        arregion_i <= s_axi_arregion;\n          acc_ar_i[7] <= arregion_i[0];\n        aruser_i <= s_axi_aruser;\n          acc_ar_i[8] <= aruser_i[0];\n      end else begin\n        araddr_i <= araddr_i>>1;\n        arprot_i <= arprot_i>>1;\n        arsize_i <= arsize_i>>1;\n        arburst_i <= arburst_i>>1;\n        arcache_i <= arcache_i>>1;\n        arlock_i <= arlock_i>>1;\n        arqos_i <= arqos_i>>1;\n        arregion_i <= arregion_i>>1;\n        aruser_i <= aruser_i>>1;\n        acc_ar_i <= acc_ar_i>>1;\n      end\n    end\n  \n  \n    /**************** Internal Wires/Regs - Write Channels ****************/\n    wire                          write_burst_done_i;\n    reg [16-1:0]                  awcnt_i = 16'h0000;\n    reg                           awvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     awaddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   awprot_i = 3'b000;\n    reg [3-1:0]                   awsize_i = 3'b000;\n    reg [2-1:0]                   awburst_i = 2'b00;\n    reg [4-1:0]                   awcache_i = 4'b0000;\n    reg [P_LEN_WIDTH-1:0]      awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [1-1:0]     awlock_i = 1'b0;\n    reg [4-1:0]                   awqos_i = 4'b0000;\n    reg [4-1:0]                   awregion_i = 4'b0000;\n    reg [C_AXI_AWUSER_WIDTH:0]     awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg                           wvalid_i = 1'b0;\n    reg [C_AXI_DATA_WIDTH-1:0]     wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH/8-1:0]   wstrb_i = {(C_AXI_DATA_WIDTH/8){1'b0}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_BUSER_WIDTH:0]     buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_aw_i = 9'b0;\n    reg [3:0]                     acc_w_i = 4'b0;\n    reg                           s_axi_bvalid_i = 1'b0;\n    reg                           s_axi_awready_i = 1'b0;\n    reg                           s_axi_wready_i = 1'b0;\n    /**************** Assign Write Channel Outputs ****************/\n    assign write_burst_done_i =s_axi_wready_i && s_axi_wvalid && ((C_AXI_PROTOCOL == 2) ? 1'b1 : s_axi_wlast);\n    assign s_axi_bvalid = s_axi_bvalid_i;\n    assign s_axi_awready = s_axi_awready_i;\n    assign s_axi_wready = s_axi_wready_i;\n  \n    //**********************************************\n    // Write Channel: AWREADY, WREADY, BVALID, BID\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awcnt_i <= 16'h0000;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        /**************** Write Address Channel ****************/\n        // awready\n        if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_awready_i <= 1'b0;\n          awcnt_i <= awcnt_i + 1'b1;\n          s_axi_bid <= s_axi_awid;\n          s_axi_buser <= buser_i;\n        end else if(~s_axi_wready_i & ~s_axi_bvalid_i) begin\n          s_axi_awready_i <= 1'b1;\n        end\n  \n        /**************** Write Data Channel ****************/\n        // wready\n        if(write_burst_done_i) begin\n          s_axi_wready_i <= 1'b0;\n        end else if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_wready_i <= 1'b1;\n        end\n  \n        /**************** Write Response Channel ****************/\n        // bvalid\n        if(write_burst_done_i) begin\n          s_axi_bvalid_i <= 1'b1;\n        end else if(s_axi_bready && s_axi_bvalid_i) begin\n          s_axi_bvalid_i <= 1'b0;\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Write Channel: BRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_bresp <= {2{1'b0}};\n      end else if (~s_axi_bvalid_i) begin\n        s_axi_bresp <= {(acc_aw_i[0] ^ acc_w_i[0]), 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: BUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (aresetn) begin\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n      end else begin\n        buser_i <= (s_axi_awready_i && s_axi_awvalid) ? {buser_i, ~buser_i[C_AXI_BUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Write Address Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awaddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        awprot_i <= {3{1'b0}};\n        awsize_i <= {3{1'b0}};\n        awburst_i <= {2{1'b0}};\n        awcache_i <= {4{1'b0}};\n        awlen_i <= {P_LEN_WIDTH{1'b0}};\n        awlock_i <= {1{1'b0}};\n        awqos_i <= {4{1'b0}};\n        awregion_i <= {4{1'b0}};\n        awuser_i <= {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n        acc_aw_i <= 9'b0;\n      end else if (s_axi_awvalid) begin\n        // Register Inputs\n        awaddr_i <= s_axi_awaddr;\n          acc_aw_i[0] <= awaddr_i[0];\n        awprot_i <= s_axi_awprot;\n          acc_aw_i[1] <= awprot_i[0];\n        awsize_i <= s_axi_awsize;\n          acc_aw_i[2] <= awsize_i[0];\n        awburst_i <= s_axi_awburst;\n          acc_aw_i[3] <= awburst_i[0];\n        awcache_i <= s_axi_awcache;\n          acc_aw_i[4] <= awcache_i[0];\n        awlock_i <= s_axi_awlock;\n          acc_aw_i[5] <= awlock_i[0];\n        awqos_i <= s_axi_awqos;\n          acc_aw_i[6] <= awqos_i[0];\n        awregion_i <= s_axi_awregion;\n          acc_aw_i[7] <= awregion_i[0];\n        awuser_i <= s_axi_awuser;\n          acc_aw_i[8] <= awuser_i[0];\n      end else begin\n        awaddr_i <= awaddr_i>>1;\n        awprot_i <= awprot_i>>1;\n        awsize_i <= awsize_i>>1;\n        awburst_i <= awburst_i>>1;\n        awcache_i <= awcache_i>>1;\n        awlock_i <= awlock_i>>1;\n        awqos_i <= awqos_i>>1;\n        awregion_i <= awregion_i>>1;\n        awuser_i <= awuser_i>>1;\n        acc_aw_i <= acc_aw_i>>1;\n      end\n    end\n  \n    //**********************************************\n    // Write Data Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        wstrb_i <= {(C_AXI_DATA_WIDTH/8){1'b0}};\n        wuser_i <= {(C_AXI_WUSER_WIDTH+1){1'b0}};\n        acc_w_i <= 4'b0;\n      end else if (s_axi_wvalid) begin\n        // Register Inputs\n        wdata_i <= s_axi_wdata;\n          acc_w_i[0] <= wdata_i[0];\n        wstrb_i <= s_axi_wstrb;\n          acc_w_i[1] <= wstrb_i[0];\n        wuser_i <= s_axi_wuser;\n          acc_w_i[2] <= wuser_i[0];\n      end else begin\n        wdata_i <= wdata_i>>1;\n        wstrb_i <= wstrb_i>>1;\n        wuser_i <= wuser_i>>1;\n        acc_w_i <= acc_w_i>>1;\n      end\n    end\n  \nendmodule\n\n\n\n//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_22_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \n(* autopipeline_module=\"yes\" *)\nmodule axi_register_slice_v2_1_22_auto_slr #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n    wire                    handshake_pipe;\n    wire                    ready_pipe;\n    wire [C_DATA_WIDTH-1:0] payload_pipe;\n    (* keep=\"true\" *)                                                                reg  s_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  s_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  s_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  s_areset_resp2 = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  m_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  m_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_areset_resp2 = 1'b0;\n    \n  // Global Reset pipelining\n  \n    always @(posedge ACLK) begin\n      s_aclear       <= ~ARESETN;\n      s_areset_fwd   <= ~ARESETN; \n      s_areset_resp  <= s_areset_fwd;  // Auto-pipeline\n      s_areset_resp2 <= s_areset_resp; // Auto-pipeline\n    end\n    \n    always @(posedge ACLK) begin\n      m_aclear       <= ~ARESETN;\n      m_areset_fwd   <= ~ARESETN; \n      m_areset_resp  <= m_areset_fwd;  // Auto-pipeline\n      m_areset_resp2 <= m_areset_resp; // Auto-pipeline\n    end\n    \n  // Source-side submodule\n    \n    axi_register_slice_v2_1_22_auto_src #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_src\n      (\n       .ACLK             (ACLK),    \n       .s_aclear         (s_aclear),\n       .s_areset_resp2   (s_areset_resp2),  \n       .S_VALID          (S_VALID),  \n       .S_READY          (S_READY), \n       .S_PAYLOAD_DATA   (S_PAYLOAD_DATA),\n       .ready_pipe        (ready_pipe), \n       .handshake_pipe    (handshake_pipe),\n       .payload_pipe      (payload_pipe)  \n      );\n    \n  // Destination-side submodule\n    \n    axi_register_slice_v2_1_22_auto_dest #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_dest\n      (\n       .ACLK           (ACLK),    \n       .m_aclear       (m_aclear),\n       .m_areset_resp2 (m_areset_resp2),  \n       .M_READY        (M_READY), \n       .M_VALID        (M_VALID),  \n       .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n       .handshake_pipe  (handshake_pipe),\n       .ready_pipe      (ready_pipe),  \n       .payload_pipe    (payload_pipe)  \n      );\n    \nendmodule  // auto_slr\n\nmodule axi_register_slice_v2_1_22_auto_src #\n  (\n   parameter integer C_DATA_WIDTH = 32\n  )\n  (\n   input  wire ACLK,\n   input  wire s_aclear,\n   input  wire s_areset_resp2,\n   input  wire S_VALID,\n   input  wire ready_pipe,\n   output wire S_READY,\n   output wire handshake_pipe,\n   output wire  [C_DATA_WIDTH-1:0] payload_pipe,\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA\n   );\n    \n   (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  [C_DATA_WIDTH-1:0] payload_pipe_r;\n    (* keep=\"true\" *) reg [2:0] s_aresetn_resp4 = 3'b000;\n    wire s_aresetn_resp3;\n    wire s_aresetn_d;\n    wire s_aresetn_q;\n    wire s_handshake_d;\n    wire s_ready_i;\n    \n    assign S_READY = s_ready_i & s_aresetn_q;\n    assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;\n    assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;\n    assign payload_pipe = payload_pipe_r;\n    \n    always @(posedge ACLK or posedge s_aclear) begin\n      if (s_aclear) begin\n        s_aresetn_resp4 <= 3'b000;\n      end else begin\n        s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      payload_pipe_r <= S_PAYLOAD_DATA;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) s_aresetn_resp3_inst (\n        .Q   (s_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~s_areset_resp2)\n     );\n    \n    // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (s_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_aresetn_d)\n     );\n    \n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (handshake_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_handshake_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (s_ready_i),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (ready_pipe)\n     );\n    \nendmodule  // auto_src\n\nmodule axi_register_slice_v2_1_22_auto_dest #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   input  wire ACLK,\n   input  wire m_aclear,\n   input  wire m_areset_resp2,\n   input  wire M_READY,\n   input  wire handshake_pipe,\n   output wire ready_pipe,\n   output wire M_VALID,\n   input  wire [C_DATA_WIDTH-1:0] payload_pipe,\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n   );\n    \n    (* keep=\"true\" *) reg [2:0] m_aresetn_resp4 = 3'b000;\n    wire m_aresetn_resp3;\n    wire m_aresetn_d;\n    wire m_aresetn_q;\n    wire m_valid_i;\n    wire pop;\n    wire m_ready_d;\n    wire m_handshake_q;\n    reg  [C_DATA_WIDTH-1:0] m_payload_q;\n    \n    assign M_VALID = m_valid_i;\n    assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;\n    assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;\n    assign pop     = M_READY & m_valid_i;\n    \n    always @(posedge ACLK or posedge m_aclear) begin\n      if (m_aclear) begin\n        m_aresetn_resp4 <= 3'b000;\n      end else begin\n        m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      m_payload_q <= payload_pipe;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) m_aresetn_resp3_inst (\n        .Q   (m_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~m_areset_resp2)\n     );\n    \n    // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (m_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_aresetn_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (m_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (handshake_pipe)\n     );\n    \n    (* autopipeline_group=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (ready_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_ready_d)\n     );\n    \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  (5)  \n      )\n      srl_fifo\n      (\n       .aclk    (ACLK),    \n       .areset  (~m_aresetn_q),\n       .aclear  (m_aclear),  \n       .s_mesg  (m_payload_q),  \n       .s_valid (m_handshake_q), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      );\n    \nendmodule  // auto_dest\n\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      reg s_valid_d;\n      reg s_ready_d = 1'b0;\n      reg s_ready_reg = 1'b0;\n      reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_22_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_RESP_MIDDLE2_LATENCY = C_PIPELINES_SLAVE + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_22_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      .ACLK           (ACLK),\n      .ARESETN         (ARESETN),\n      .S_PAYLOAD_DATA (S_PAYLOAD_DATA),\n      .S_VALID        (S_VALID),\n      .S_READY        (S_READY),\n      .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n      .M_VALID        (M_VALID),\n      .M_READY        (M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_reset;\n    wire src_ready;\n    wire dummy_reset;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  ( C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( dummy_reset   ) ,\n        .laguna_s_reset_in  ( src_reset   ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset   ) ,\n        .laguna_m_reset_in  ( src_reset  ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset2   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n      \n  end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] mid_payload;\n    wire mid_handshake;\n    wire mid_ready;\n    wire mid_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n    wire dummy_reset3;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( mid_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( mid_reset    ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset3   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset3   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out (  dummy_reset2  ) ,\n        .laguna_m_reset_in  ( mid_reset   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE2_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( mid_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2   ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset3   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset3    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n   \n  generate\n\n  (* keep=\"true\" *) reg s_reset_dd = 1'b0;\n  (* keep=\"true\" *) reg m_reset_dd = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n  \n  assign laguna_s_reset_out = laguna_s_reset_out_i;\n  assign laguna_m_reset_out = laguna_m_reset_out_i;\n  \n  always @(posedge ACLK) begin\n    laguna_s_reset_in_d <= laguna_s_reset_in;\n    laguna_m_reset_in_d <= laguna_m_reset_in;\n    s_reset_dd <= laguna_s_reset_in_d;\n    m_reset_dd <= laguna_m_reset_in_d;\n    laguna_s_reset_out_i <= C_PIPELINES==0 ? laguna_m_reset_in_d : m_reset_dd;\n    laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;\n  end\n  \n  wire ACLEAR;\n  assign ACLEAR = ~ARESETN;\n  \n  if (1) begin : common\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire laguna_s_handshake_q;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, laguna_m_ready_d}; \n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else if (p==C_PIPELINES+1) begin\n          laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n\n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = handshake_i[C_PIPELINES];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_m_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* keep=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_22_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_m_reset_out = laguna_m_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_m_reset_in_d <= laguna_m_reset_in;\n      aresetn_d <= C_CHANNEL==P_FORWARD ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? areset_dly[15]  : laguna_m_reset_in_d;\n      laguna_m_reset_out_i <= areset_d;  // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n  \n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* keep=\"true\" *)  reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      ready_d <= {ready_d, laguna_m_ready_d}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid_q;\n      assign payload_valid_d = (p==0) ? (S_VALID & s_ready_i) : handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==C_PIPELINES) begin\n          laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else if (p==0) begin\n          payload_data <= S_PAYLOAD_DATA;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n      \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_s_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* keep=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_s_reset_out = laguna_s_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_s_reset_in_d <= laguna_s_reset_in;\n      aresetn_d <= C_CHANNEL==P_RESPONSE ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? laguna_s_reset_in_d : areset_dly[15];\n      laguna_s_reset_out_i <= areset_d;  // For forward channels, reflect laguna_s_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n\n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    wire laguna_s_handshake_q;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      laguna_s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n        \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n        \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)  \n      )\n      srl_fifo_0\n      (\n       .aclk    (ACLK),    \n       .areset  (areset_d),  \n       .aclear  (ACLEAR),\n       .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n       .s_valid (push), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      ); \n  \n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  reg areset_d = 1'b0;\n  reg [3:0] areset_dly = 4'b0;\n  always @(posedge ACLK) begin\n    areset_dly <= {4{~ARESETN}} | (areset_dly<<1);\n    areset_d <= areset_dly[3];\n  end\n  \n  if (1) begin : common\n    reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID & s_ready_i;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* keep=\"true\" *)  reg payload_valid = 1'b0;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          payload_data <= S_PAYLOAD_DATA;\n          payload_valid <= S_VALID & s_ready_i & ~areset_d;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n          payload_valid <= handshake_i[((p>0)?(p-1):0)];\n        end\n      end\n    end\n    \n    if (C_PIPELINES==0) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),\n         .aclear  (1'b0),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire                        aclear,  // Async clear\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    wire [1:0] state;  // State vector register\n    reg  [1:0] next;           // Next state value\n    wire [1:0] next_qual;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    reg  m_valid_d;\n    wire m_valid_q;\n    \n    assign m_valid = m_valid_q;\n    assign next_qual = areset ? K_EMPTY : next;\n    assign m_mesg  = mesg_reg;\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_mvalid_inst (\n        .Q   (m_valid_q),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (m_valid_d)\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state0_inst (\n        .Q   (state[0]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[0])\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state1_inst (\n        .Q   (state[1]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[1])\n     );\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      m_valid_d = m_valid_q & ~areset;\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid & ~areset) begin\n            next = K_HAS1;\n            m_valid_d = 1'b0;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              m_valid_d = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n              m_valid_d = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          m_valid_d = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      (* keep_hierarchy = \"yes\" *) axi_register_slice_v2_1_22_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule  // axic_reg_srl_fifo\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   //   16 -> Auto-pipelining\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_RESERVE_MODE = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n  \n  if (C_RESERVE_MODE==1) begin : gen_reserve_si\n  \n    axi_register_slice_v2_1_22_test_slave #(\n      .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n      .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n      .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n      .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n      .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n      .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n      .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n      .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n      .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .s_axi_awaddr(s_axi_awaddr),\n      .s_axi_awprot(s_axi_awprot),\n      .s_axi_awvalid(s_axi_awvalid),\n      .s_axi_awready(s_axi_awready),\n      .s_axi_awsize(s_axi_awsize),\n      .s_axi_awburst(s_axi_awburst),\n      .s_axi_awcache(s_axi_awcache),\n      .s_axi_awlen(s_axi_awlen),\n      .s_axi_awlock(s_axi_awlock),\n      .s_axi_awqos(s_axi_awqos),\n      .s_axi_awregion(s_axi_awregion),\n      .s_axi_awid(s_axi_awid),\n      .s_axi_awuser(s_axi_awuser),\n      .s_axi_wdata(s_axi_wdata),\n      .s_axi_wstrb(s_axi_wstrb),\n      .s_axi_wvalid(s_axi_wvalid),\n      .s_axi_wready(s_axi_wready),\n      .s_axi_wlast(s_axi_wlast),\n      .s_axi_wid(s_axi_wid),\n      .s_axi_wuser(s_axi_wuser),\n      .s_axi_bresp(s_axi_bresp),\n      .s_axi_bvalid(s_axi_bvalid),\n      .s_axi_bready(s_axi_bready),\n      .s_axi_buser(s_axi_buser),\n      .s_axi_bid(s_axi_bid),\n      .s_axi_araddr(s_axi_araddr),\n      .s_axi_arprot(s_axi_arprot),\n      .s_axi_arvalid(s_axi_arvalid),\n      .s_axi_arready(s_axi_arready),\n      .s_axi_arsize(s_axi_arsize),\n      .s_axi_arburst(s_axi_arburst),\n      .s_axi_arcache(s_axi_arcache),\n      .s_axi_arlock(s_axi_arlock),\n      .s_axi_arlen(s_axi_arlen),\n      .s_axi_arqos(s_axi_arqos),\n      .s_axi_arregion(s_axi_arregion),\n      .s_axi_aruser(s_axi_aruser),\n      .s_axi_arid(s_axi_arid),\n      .s_axi_rdata(s_axi_rdata),\n      .s_axi_rresp(s_axi_rresp),\n      .s_axi_rvalid(s_axi_rvalid),\n      .s_axi_rready(s_axi_rready),\n      .s_axi_rlast(s_axi_rlast),\n      .s_axi_ruser(s_axi_ruser),\n      .s_axi_rid(s_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign m_axi_awid     = 0;\n     assign m_axi_awaddr   = 0;\n     assign m_axi_awlen    = 0;\n     assign m_axi_awsize   = 0;\n     assign m_axi_awburst  = 0;\n     assign m_axi_awlock   = 0;\n     assign m_axi_awcache  = 0;\n     assign m_axi_awprot   = 0;\n     assign m_axi_awregion = 0;\n     assign m_axi_awqos    = 0;\n     assign m_axi_awuser   = 0;\n     assign m_axi_awvalid  = 0;\n     assign m_axi_wid      = 0;\n     assign m_axi_wdata    = 0;\n     assign m_axi_wstrb    = 0;\n     assign m_axi_wlast    = 0;\n     assign m_axi_wuser    = 0;\n     assign m_axi_wvalid   = 0;\n     assign m_axi_bready   = 0;\n     assign m_axi_arid     = 0;\n     assign m_axi_araddr   = 0;\n     assign m_axi_arlen    = 0;\n     assign m_axi_arsize   = 0;\n     assign m_axi_arburst  = 0;\n     assign m_axi_arlock   = 0;\n     assign m_axi_arcache  = 0;\n     assign m_axi_arprot   = 0;\n     assign m_axi_arregion = 0;\n     assign m_axi_arqos    = 0;\n     assign m_axi_aruser   = 0;\n     assign m_axi_arvalid  = 0;\n     assign m_axi_rready   = 0;\n      \n  end else if (C_RESERVE_MODE==2) begin : gen_reserve_mi\n    \n    axi_register_slice_v2_1_22_test_master #(\n    .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n    .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .m_axi_awaddr(m_axi_awaddr),\n      .m_axi_awprot(m_axi_awprot),\n      .m_axi_awvalid(m_axi_awvalid),\n      .m_axi_awready(m_axi_awready),\n      .m_axi_awsize(m_axi_awsize),\n      .m_axi_awburst(m_axi_awburst),\n      .m_axi_awcache(m_axi_awcache),\n      .m_axi_awlen(m_axi_awlen),\n      .m_axi_awlock(m_axi_awlock),\n      .m_axi_awqos(m_axi_awqos),\n      .m_axi_awid(m_axi_awid),\n      .m_axi_awuser(m_axi_awuser),\n      .m_axi_wid(m_axi_wid),\n      .m_axi_wdata(m_axi_wdata),\n      .m_axi_wstrb(m_axi_wstrb),\n      .m_axi_wvalid(m_axi_wvalid),\n      .m_axi_wready(m_axi_wready),\n      .m_axi_wlast(m_axi_wlast),\n      .m_axi_wuser(m_axi_wuser),\n      .m_axi_bresp(m_axi_bresp),\n      .m_axi_bvalid(m_axi_bvalid),\n      .m_axi_bready(m_axi_bready),\n      .m_axi_buser(m_axi_buser),\n      .m_axi_bid(m_axi_bid),\n      .m_axi_araddr(m_axi_araddr),\n      .m_axi_arprot(m_axi_arprot),\n      .m_axi_arvalid(m_axi_arvalid),\n      .m_axi_arready(m_axi_arready),\n      .m_axi_arsize(m_axi_arsize),\n      .m_axi_arburst(m_axi_arburst),\n      .m_axi_arcache(m_axi_arcache),\n      .m_axi_arlen(m_axi_arlen),\n      .m_axi_arlock(m_axi_arlock),\n      .m_axi_arqos(m_axi_arqos),\n      .m_axi_arid(m_axi_arid),\n      .m_axi_aruser(m_axi_aruser),\n      .m_axi_rdata(m_axi_rdata),\n      .m_axi_rresp(m_axi_rresp),\n      .m_axi_rvalid(m_axi_rvalid),\n      .m_axi_rready(m_axi_rready),\n      .m_axi_rlast(m_axi_rlast),\n      .m_axi_ruser(m_axi_ruser),\n      .m_axi_rid(m_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign s_axi_awready = 0;\n     assign s_axi_wready  = 0;\n     assign s_axi_bid     = 0;\n     assign s_axi_bresp   = 0;\n     assign s_axi_buser   = 0;\n     assign s_axi_bvalid  = 0;\n     assign s_axi_arready = 0;\n     assign s_axi_rid     = 0;\n     assign s_axi_rdata   = 0;\n     assign s_axi_rresp   = 0;\n     assign s_axi_rlast   = 0;\n     assign s_axi_ruser   = 0;\n     assign s_axi_rvalid  = 0;\n\n  end else begin : gen_reg_slice  // Any normal reg-slice mode\n\n    axi_infrastructure_v1_1_0_axi2vector #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    axi2vector_0 ( \n      .s_axi_awid      ( s_axi_awid      ) ,\n      .s_axi_awaddr    ( s_axi_awaddr    ) ,\n      .s_axi_awlen     ( s_axi_awlen     ) ,\n      .s_axi_awsize    ( s_axi_awsize    ) ,\n      .s_axi_awburst   ( s_axi_awburst   ) ,\n      .s_axi_awlock    ( s_axi_awlock    ) ,\n      .s_axi_awcache   ( s_axi_awcache   ) ,\n      .s_axi_awprot    ( s_axi_awprot    ) ,\n      .s_axi_awqos     ( s_axi_awqos     ) ,\n      .s_axi_awuser    ( s_axi_awuser    ) ,\n      .s_axi_awregion  ( s_axi_awregion  ) ,\n      .s_axi_wid       ( s_axi_wid       ) ,\n      .s_axi_wdata     ( s_axi_wdata     ) ,\n      .s_axi_wstrb     ( s_axi_wstrb     ) ,\n      .s_axi_wlast     ( s_axi_wlast     ) ,\n      .s_axi_wuser     ( s_axi_wuser     ) ,\n      .s_axi_bid       ( s_axi_bid       ) ,\n      .s_axi_bresp     ( s_axi_bresp     ) ,\n      .s_axi_buser     ( s_axi_buser     ) ,\n      .s_axi_arid      ( s_axi_arid      ) ,\n      .s_axi_araddr    ( s_axi_araddr    ) ,\n      .s_axi_arlen     ( s_axi_arlen     ) ,\n      .s_axi_arsize    ( s_axi_arsize    ) ,\n      .s_axi_arburst   ( s_axi_arburst   ) ,\n      .s_axi_arlock    ( s_axi_arlock    ) ,\n      .s_axi_arcache   ( s_axi_arcache   ) ,\n      .s_axi_arprot    ( s_axi_arprot    ) ,\n      .s_axi_arqos     ( s_axi_arqos     ) ,\n      .s_axi_aruser    ( s_axi_aruser    ) ,\n      .s_axi_arregion  ( s_axi_arregion  ) ,\n      .s_axi_rid       ( s_axi_rid       ) ,\n      .s_axi_rdata     ( s_axi_rdata     ) ,\n      .s_axi_rresp     ( s_axi_rresp     ) ,\n      .s_axi_rlast     ( s_axi_rlast     ) ,\n      .s_axi_ruser     ( s_axi_ruser     ) ,\n      .s_awpayload ( s_awpayload ) ,\n      .s_wpayload  ( s_wpayload  ) ,\n      .s_bpayload  ( s_bpayload  ) ,\n      .s_arpayload ( s_arpayload ) ,\n      .s_rpayload  ( s_rpayload  ) \n    );\n    \n    axi_infrastructure_v1_1_0_vector2axi #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    vector2axi_0 ( \n      .m_awpayload    ( m_awpayload    ) ,\n      .m_wpayload     ( m_wpayload     ) ,\n      .m_bpayload     ( m_bpayload     ) ,\n      .m_arpayload    ( m_arpayload    ) ,\n      .m_rpayload     ( m_rpayload     ) ,\n      .m_axi_awid     ( m_axi_awid     ) ,\n      .m_axi_awaddr   ( m_axi_awaddr   ) ,\n      .m_axi_awlen    ( m_axi_awlen    ) ,\n      .m_axi_awsize   ( m_axi_awsize   ) ,\n      .m_axi_awburst  ( m_axi_awburst  ) ,\n      .m_axi_awlock   ( m_axi_awlock   ) ,\n      .m_axi_awcache  ( m_axi_awcache  ) ,\n      .m_axi_awprot   ( m_axi_awprot   ) ,\n      .m_axi_awqos    ( m_axi_awqos    ) ,\n      .m_axi_awuser   ( m_axi_awuser   ) ,\n      .m_axi_awregion ( m_axi_awregion ) ,\n      .m_axi_wid      ( m_axi_wid      ) ,\n      .m_axi_wdata    ( m_axi_wdata    ) ,\n      .m_axi_wstrb    ( m_axi_wstrb    ) ,\n      .m_axi_wlast    ( m_axi_wlast    ) ,\n      .m_axi_wuser    ( m_axi_wuser    ) ,\n      .m_axi_bid      ( m_axi_bid      ) ,\n      .m_axi_bresp    ( m_axi_bresp    ) ,\n      .m_axi_buser    ( m_axi_buser    ) ,\n      .m_axi_arid     ( m_axi_arid     ) ,\n      .m_axi_araddr   ( m_axi_araddr   ) ,\n      .m_axi_arlen    ( m_axi_arlen    ) ,\n      .m_axi_arsize   ( m_axi_arsize   ) ,\n      .m_axi_arburst  ( m_axi_arburst  ) ,\n      .m_axi_arlock   ( m_axi_arlock   ) ,\n      .m_axi_arcache  ( m_axi_arcache  ) ,\n      .m_axi_arprot   ( m_axi_arprot   ) ,\n      .m_axi_arqos    ( m_axi_arqos    ) ,\n      .m_axi_aruser   ( m_axi_aruser   ) ,\n      .m_axi_arregion ( m_axi_arregion ) ,\n      .m_axi_rid      ( m_axi_rid      ) ,\n      .m_axi_rdata    ( m_axi_rdata    ) ,\n      .m_axi_rresp    ( m_axi_rresp    ) ,\n      .m_axi_rlast    ( m_axi_rlast    ) ,\n      .m_axi_ruser    ( m_axi_ruser    ) \n    );\n    \n  end  // Reserve SI/MI branch\n\n  if ((C_REG_CONFIG_AW <= 9) && (C_RESERVE_MODE==0)) begin : aw\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 15) && (C_RESERVE_MODE==0)) begin : aw15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 16) && (C_RESERVE_MODE==0)) begin : aw16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) \n    )\n    aw_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if ((C_REG_CONFIG_W <= 9) && (C_RESERVE_MODE==0)) begin : w\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 15) && (C_RESERVE_MODE==0)) begin : w15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 16) && (C_RESERVE_MODE==0)) begin : w16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) \n    )\n    w_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if ((C_REG_CONFIG_B <= 9) && (C_RESERVE_MODE==0)) begin : b\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if ((C_REG_CONFIG_B == 15) && (C_RESERVE_MODE==0)) begin : b15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if ((C_REG_CONFIG_B == 16) && (C_RESERVE_MODE==0)) begin : b16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) \n    )\n    b_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if ((C_REG_CONFIG_AR <= 9) && (C_RESERVE_MODE==0)) begin : ar\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 15) && (C_RESERVE_MODE==0)) begin : ar15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 16) && (C_RESERVE_MODE==0)) begin : ar16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) \n    )\n    ar_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if ((C_REG_CONFIG_R <= 9) && (C_RESERVE_MODE==0)) begin : r\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 15) && (C_RESERVE_MODE==0)) begin : r15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 16) && (C_RESERVE_MODE==0)) begin : r16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) \n    )\n    r_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 4844}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule dest_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(9),\n    .C_REG_CONFIG_W(9),\n    .C_REG_CONFIG_B(1),\n    .C_REG_CONFIG_AR(9),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"dest_register_slice,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"dest_register_slice,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=16,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=9,C_REG_CONFIG_W=9\\\n,C_REG_CONFIG_B=1,C_REG_CONFIG_AR=9,C_REG_CONFIG_R=1,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule dest_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(9),\n    .C_REG_CONFIG_W(9),\n    .C_REG_CONFIG_B(1),\n    .C_REG_CONFIG_AR(9),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nXvoWuyjysN5V55U4xsjyWg2bXI++8I1KAZgJ0eiQkY3L8ns1PfNti9fujmr8wvFQA6ycwh4K6mSp\nINQjc8TyLQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nbD05I2IKef08FLVG4C2ftkJOY+/UsvagxY6ta+A0N1USwLQivKTmRt7LJlQ+5UJqrfPvhHMyYrLN\nrjoJbClg85XfNTYCnalRVvg3mmCcjtJkCLf6S5E9Q6UF92b6bwgtMTsr0BndJhdItlJtr0dYZtoP\nAEskMBthh6RdNMkZ3CA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nvLo4Yp/zX6HvZ92VMA2Xr4EIhMWPNGq2EvSBkjiZd5sCSFAX+37MKx4gdbrsGvhUMl1njqvSaoP7\nKrAa29/cm3QWjPgpaCsR/MhnaG5+7aUvxA5iCqVHXdriMlgx9kzxkB9SD+mOC8XR5LtYA0bPhbZ9\njQzWpWxdaOGYFF25DU0O9M7LMc7SLfKunYH/cQ91D37m0LjgZh1/uZv8chFzvCBbkHqUU0qi17/k\nZTWIIzqb1oycbuhZZrWLl95xQ/aaTxZ30sONWd/axZtO3Cd57huCbCxLuOH51qq6erD9AVszmxL8\noEoM+KW88P1S3LJ/EcIQN4LU0/nyN/f7xEmy2w==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nj99ihkoCqIO9DhRZEJdEqlRF2P+IwS2wuYmoh3hWFCDXbmGTwTqc+3EMjxY8Z4uDixuazjlTMiEH\nCk4MdTkVZ55pPhFb4druHTap3Twn20B3SWvOy2nf84OpTkdBnbK4qagABgZXs9/mAtQxbF++/F6Y\n+OOE3yUNTWvHiVGvpTJavfADkB2CL5wEIlBSnYRwtLp71JokDsMvjq2l3o3hxAjvtdg9ej7NKx4I\nkAZfrpZH7Ebv2hfXrTVI2kDTAl5Etr+4oSqxIhABJut2WaeWJrsSbL+dz9s2ZmYDMb1BCQdRexck\nbMMvUaS+P7sSGuR9BTVynHOY5GdQelHO1aazQw==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nHuzbd0U90PuPKn40554Cnki98HuQSq7dg6ZyXufEWFHsji6rteNupAY3HQsuLpXjFVxsNlS4bcHj\nAAOnDcL0hCCVbSkU011mqhhlkFmWqeBBECGfP+T7/+l9KBu+9ynszhlhaVhmZMffsEuohDl5x084\nFnzFCdxrFyvqrOyWDac=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\neoQKmSsNWNEOJcUApe0UhUNGRDkxOLedPbjyDILgUJWMG+WVCpL9MC2MXZeZ6/oVwAYRlZTZsF1h\nUsVo6BO7IAuHuJAHeIQgEs2oIMj/I2qZxm9wUsOzWoK5/Jz4SS4sTE3TgOJXaX1GNAJlbUrCBtnM\nqIiavU164vZjX5BFoPGuHp4kICN8A4Wr9y2w2Lh0/IdiHjr/Ruk5PpVNyl7tW9EaSFY1AL4aoQpd\nRFDdUFRk4tMBtmFxi/B+pLVFE0hAUZnlVCsSaf4B0lN/m4CME7lgy7oXElp7ov4fMnD9VI8HLGMX\nWBSQjD8F6BB0Wblgm9lJNc0h0VqxxD4DbRleKA==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nyrn0K+G4SU1wuMdE7DJlKWErX/N5nCqD3+dP+4ONmo8yuM983VHfjLhCoeQMbM26e49U4PPdXcDR\ny0rRemqJACoi5H5NvzXohhKZI9q+WKME4TkhFzfKvIwyta1m/uNSe/A0+52Dzbg5uAxYihw0IdZR\nZMywfa3deZ8IUMz3kWSlMs1P4wESz2pKpdYGs0FpvovucuNn4OhZKH7RGX8z8Zy4E9juZRgnSQnX\nmvRtisgVB9uL2J0vl9XjW/1990VYZi0nrZJ8gQL38HLTz62vDuMuYjiFbbnDCujJNKOCHh/xJTdt\n73nsz+dY3We4tQdnxuESibzLQLGF1l8+d9FPDA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nJPIGH1v6BG8bvo+3pHrWlum+XEDtFDlKP+4Toq88+g/eeinS/p8A0zMVVYj4wfjGDhx3kGvJ9XAx\ngxYpezvlgnz+IEGWQzepCMSp4iHz9TEdGkc5LTQj50VJj4+HGz2Qhrw96Hw0c+5RDrv238ILy3p7\nuzIPIzxKEl8D7gK6b8ZPrzx95KMPuGZyju4JUHBWdjDx0hhhIl+L3Ju/bVyWaWd7w1xI0mreJtAN\noOdcObOESJpTuj0KqFtfA3UY7v9n9Lj/I/vMaPX7LnSIZuS+tHyiD8D+t+Kf6XiIl3sYDL9erP7t\nSpHvPfG9bOfGRxM7dmsvKj+XqHeXg23wyS1Nfg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nrxmK0sxFw5opGoAsi+RHBRwE0wYNls8LL+oURMgLNuoRDOPNH7up4F86jASnrdlvXLShGHMZnaJ6\ny1orZ0uAZ6xxM2PeKAxvxBI02HOu0aXd/SMNxr16dADlCYK6R1DVdq3DC+T8bQTLWyyHr9r4m4En\nW5DcJ2hEs5b31PUg/DoCNTpHm2swT7sLG9qRkSfTddaSyGTADcvRXYjnHKHin6TQlOCZufWMm54P\nPJeCQmj1MjyycQGpsvFNX7VMxW49ashO7EGmRdy7lMGRoHDqLWBxcIlwAS4L28iuln/NdC/QV538\nQei7EbcqeUmfs07XP8FKxdA3hi3Aq2Upg9DkOw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64736)\n`pragma protect data_block\npJdOORWQloxSGvgvy0l4tBp1HqnYdonsYgNOe99SLH3qi9BP+2tNlaoelqmLJLSHNsBn3TJxXlZa\nnIZxc0/l2jA1h9Jz15QEEgUR0MqZaESeIPQdEbADnul6xUXY0J6g//n8Vnzph99nb1v9j4yp0I8W\nmF2Bvdz/qHJcUcV5zedPk5PkPVS8cmwYFQWer3rOMl6Or1E/YoHi9T9wfbgxxTs6yzqYqVGUBlz5\nAlhSoRF+xXB1Z4h2Ny4v4u05pGtbpnnDj+JhauZ7AfT+uRL3JZ7hNdSiI3coyNU077RtI/1VAmYO\npJoj/3tO2z4y9phvRShE/Otch4qxfx53IywqoRQmUF57yV4NjbkGPW8j7U6iQ8Ls1911ZAOgZIga\nmynl1jCs8ajbsNdraT0wfsPf1kWJOCuUGyItYv2eEwfh7iEYRrpT0V6YT5gENAgDuriQCZuFtnJE\ndhvImjwTXy3d76buWun43bM5pyUNSUzm90uucXHtbfsv8HZTM/chDluZJ4cMeW8D9Pwjtvo6lXLx\nYJM6v2cUpOTIMOcKDxrRTFomRQ1DwRsa4wQGal4q2dhrokLR6YNhu1ED6+AbEAN+FWui25yRPN2c\nRifAbYj3+oa+z6kUON22gegvkiRIe3iVn5MeyImok+P+5dmykiOW6L7J+GDFd4UZtYwJkwUH4ijt\ny9tlvkg7bhgKKY/VRht7EZFg6U4GjUBwLTEWIsD/6R8LgyENKTNO1FVyOJge9+hJYOxJpk93nMac\n0dR2cl0TLESIEfZQ8wSlqKcnzibNa/Mwa+gyj8uNmBtlGMv9GLnh914fnVrJPaJYjkLNLesy5uKF\nWOOHFhlsuqMHkybog57X/W2y+bzzdtaWoQ8/DU/QWGyTt3Vhlmu4YBKvv/DBB51RUj7naprx+CNR\nK7/l3uoheqcD/zy4ipVqZ/mSOTxjqNwJ88tpKUTD7UHuLf8rEeiu80iR1raYJGMHzUS7FcK/APPf\nbBCJIKpjoq1C63MJYurbOeqWcRL3DDPi/z3C66E9WG/nFKs7vMkhbVhClFUAjy+DwMCS7VjbvUvn\nCbr4m+kTXY7ipbBxU7YIDWHssBAAjeM1Rdxx9VvDqABN+rFZAA7C08PNPUeOiVYCFO3gmbAqYK8f\nEPeBaPUk6eskVX2sXw5/qrh1a5mqGk/sYCFZItuYZ6SMz1BFuaZz+ac8Feq8+d7gH2f1DuK4EG20\nOgLh0liUdRk5TCUZsSZTlhRd1FA4SqglWHYk+GIL1WEcVBskAEiY2YIK1TGXzUQaG00TT5TRBNmv\nsPnVI8z6bWwqXomyqcYSelXrfl2izqtjadlA+3+0O2A1XhL9tmMhT3v0nQIlobxn4nFE376czv08\n2+xLHI/chXlg2WvKMK3NCBbWGw7tnHSdJc47JRdiCkb0tIr9wocUbWPbM7W5G3Ku+bQZQXPM0lNy\nstFAjwukEDL4vbC72EJbEwf+6kzkzLjBrc0JDEzvjqnYQYiwloQ0qi9k/yE3bXcnEHvgw8ig5Y/S\nt9SttzL9mNMXwbouRg1seAZ89RrLrTNZiBk2TlhzdIfvWsbvdBYdIhaMqKRGJFpWxZgPm+JbW+09\nfF1z2nf/18EW+WziUuICezISE4+2HDfqFOEltKV6AdesQWDrloYiby+MezSSORPfWkx+nVGv8JEs\nI01podsuoWFRpVmbt/Dua5qZk9EOHGFBRgvYNnlH47YVREn5j8l2T/0bBlGUrv4r0tmSTvb5Rk62\nTtYvXt/3/jJe7TX05O4Uz8CDBe02LhhwyNkyyNYPm6hcqislaGMW5IrlUBR19xoKivY5xsi9WHEp\nOscK7GlXBFf+1ZdqPUIFBzo8CoanS+vY6N5dX/zhH9ka7wSGlru7qjqAyYG3VOzYi+lIUT1D0l0A\nhIuLJhQlgGIPioPMX5r9G+nJX9J1xhmQmslUobJCrtsIfoshA1m3sO8FVq/uKShEPK85uU48DmE1\nBM73G3APR/Pn3q4udJagFjB+ngJWARXqQX1U/fZdrs1d4U8E/KLlkVQywLtM4ImADW15ZRE2zwbt\n93vD21KzRF0gTEp32+Y94DZJmilvEITUz6i6Uf3GIhk/8VlW2sgoZBxyIXdlfZU0hAeWoF6z0y8i\nsz3YJBSL59bOXPeovsUY+1K4JWkThiLh9WlHMd3YfANHBPnf+imIQZm0bk8SniIn386MI5OOzHz4\nE4NRinoFBZ2QveSs8W7mDkgRcm6PoFPVY3QRUGVKM/cdavafi55CMHzsrvtIU+GTn9VIn3xNt55T\nvun82PwGiZ2FiwhlNlG8Wy4O+LFNA76IijNkkamPOoINY3NpvBlYJ4sMSw1dZ/S+Qd509gN+YqK/\njuugLi10dq5ezC717GDkCW4fL6XMF1BLctfTjFHbDnQePKJIiB57aUuvbzah60QCKQnwYsO2mNs3\nlX8Tl9YL68F88dwoxH0JclrQ/K+4uYuofKZNpcUqyesWLZ7Ajkjo1V/LWCNdqLb7jaE2Z0v+PGsJ\nbQ2zY2rbw1xVbkOFkWnJb00IZlS5AfKLW2JwtTjSc9R5cytj7Kj8rVyPRdWixjwHVXwb9oIhCtsZ\nr9zdlcsnNvnrEk8HWDJmg9t+Ss3qdeobuZBvC1qVhW9OeCSeLWFmmlBTM7zlf4bIM7BPobwINrOH\na+x81+t4Xk/8bAWK5b1pfO/q6usi0t9Z1NTJb3ix47MRkhAbStRfFBfBwzDQr/YBXixPzFiRd7RK\nKHM5pI4NGo4x/1eUa3I9iGFb0JwOlvTvmyLF4CY35sdztuKueaGq0YUi4X3SbBVUihPbcPvhcn3q\nULcb1JlytkOdtyHtyrm7/EOiSLmMn3uCPXQDioYj1f6NsIRA8BV+t4V5VK8a2hNJ+Ci6U9tBmG7R\n2AfVDNWXakk0eYIUYcZuIPVd4sH7Be8PANt6YH+bxeZtBfUel13RoATsMc/l+Vz7BvaZ9ZhPoxu0\nMpG5BKJTAuGZ3OqNXDuuvsvuBv8s5hC8JKvLoL76k+rFk8PlyNwEnYoc7nFhCrqDHeOr/8E3maxP\nPv/AiEhEzjU5PQBF457AHnjeQ3eTwpDPSnYJ6nuR0WhnaxbVcRDXmfQc5Pm+RgJOQXySVRlfAtO/\nJmM8oWf9Wd57qYf2P95KvohDPW6vlFW5UOuYJRNedw/Vofmtj6gUXmSUtZzX9x+pGUbZK1L7qaRH\n4Bl+RKLFFF3ULv72pe+uhZoyumhCUE9nTUfh/0bbyfQ0/7E4OjNceJy3IuQXZAelpm4/lyIClM6a\nbcA7XaiUNtUxRgOk+Gm4bXDK/lbpfHAo3ZLrOeIIrJSFdGgfIjMAMcPO2agXDXysM9w0LXX4XzKa\nAk5Ctu+YxqwaE3xbxVfqa3Xiwxzu9RezCh2I21Ysg1ckJugmX+s7525qUeaUizKlxcu5ef5xX40W\nh5pW3QA7UPCugDISw+aX406IO2drov2E5eUNDLRRG/nY7aG606JFGCFgUNVLl22BloATVP6ZeMDr\nmifoHBORyaJvgAndCrygYyJGcy9labne+Cqn0A1qtn323sFNB43FEMX42WIgtgc4oPab1AYsEQum\ns46nWTCUaZAyRO+53Dzben+MOJEy1iKP7o1PMZDKjaQ4Atrpot1Ix9OivbbWL8nNOjFG3rRgc8Tf\nLOVtiwqq/r+IiSB/HQOV/ZHmkDTL9dtw3UFvBE6wRo6XaWDbKDi/T7PaYAC3GGNaQZw3CTXVFb6P\nSvTMYdICAhD7YCZDr6aVLiD1Mgc225aXecHZoluSWOck9HO5ezjlCFCPDSTSj5OnC9v9zUcFbNOa\nri/TT7JdgqdBMKQjvpVrljLeuPPWvSxLMEar6iv8iFwj9w4fIGsSX5D1h0fx53Dosj7c99OjPOKJ\n43ciuUlKmUrl8zGTv1bTsvgQBspvbQjDlKlZcFGKkJ5y+h+FKT7sLG0T7X0OsNyJhlkV8Oh1B7s0\nnzc4JG92kvRVvDmVljLF5q7kSbo4pOg+r9MMh209JANj1imzsRTwNlFhL4KQmOy32YKv975WzfpE\n5gOHTY5gj/9beHVy72SphX1PvZ/GvMrFHu0Q1SdMOxiDJO/8Vv+UogST5Z+pm6YS50RKp917SJLr\npQGNrqMBt2q0TjdKoF10330Oq2OQnGbPQBcF5wAOKor3lUhuKlgi4yfTsE7g0RlphaWiUi0kfQnJ\nxJaR/v3zWkal8YKuqBUOk2zAI58JgLOCGfkeP4lLDigas6lR86dIFm2ehEwWiuUxA0rMWk7MxUFq\nIvlNP2JTSuRX5d7mSS5TdZoich5Z28tzuAxtmfX/HVgsAiDJsXeq2lNJnPI4t7OJcjw+/LTBFn4u\nGkaeVQKsrDg0XjypHHAcx3Htai3F8S3SrSZThLhmNA0UuPAVwrWM/YxdRJdPCFxRV9DIfFLc78ED\nrxRf+2hm2iIX0v9lJubvukxj3RKg3bWedHf9X7fBwzCzmT3xpSVT/orUQHTM7BJi1uX619EAPHfH\nEslFnO9xBhBE/NfxEOIr6puKJWQy0vcdu3KHp/98gdYKgnVg5mCXI4uGSJL+j3Mo34LyWj6jofG1\nRpvUjZOY2WsTY2U7akBl0Uyiv66vuAVFTYtHxbLeKihdYSSxteod2tWquqRvLeBirXL2qi69vijg\n+WXGPNEs1ioW+W6cjl9Kt1V92qIp1LbqTEC9jDdj5VHq36eM3zGGY1FX+VH47w4FoxWcrGaGXkXO\nhGXHGyLwe6ssZ273qYR1N0RhvtgHnAdUHIPdsqqRbjeld0f7uZDVEUjGCA5HvEPmaA4qaz1HEmEX\nMSbcEbGOwM4/lsTSso35cqWlqf9VepPPahniUNw1bY7j79iM/o0F8kJkfL5NumCR5VM7RsWuHT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C99kqfj/UVOTB5eheZdHy7EcqBeNR/+6GsibmPncbobTk24qcaqVJt3wgZyWp0s45X+9wMv8\naq7nxbvk+JD5cuPi785YB4Is1gg85t6bvpA9Qfzb3O9Wk32ecemuYY7hfv+wXPcCciMC61K8t1VJ\nDxofEz9Nxh0L6M2gdZhrIeECMYqp9YunMryNLeqc7YQLvKIjonC1l4sbrYWZ+Vr/tRAksYUVxldM\nWs7rdbIReyHwkW9Q3eVk5tGNZYwsTJZ3LLHqX4k4QW4fN5SrXF7tpu0Nh6B20X5kbA57dL9bI0Mg\ngdCKLlB0s2kqOmSFFGQ2qiGM4gLCtJKTcJvH0QXyq3PoTYgnvqWXAi7962ulHUUvjiqAbTLGRYQR\ngd6pRfridQ9QkVVZ3q8/Wwg9RSEsbZuIJ9bsY3KxRk+Bv/QJmfbw9otM2ufRS79SLoJDUzayREpA\nzPDRjhDoGxRqrI6rV3uPDIkmG/IgiRjrOM3CMltuf+l5zCRv72lm/BooJKYufHaSMAUyCUXJp/Uc\nFu0s9YVH+QVUDZtdn/t+XoUZ1zviEEgoAEoY2VYry4fCJ8DYaSDlP46tShiJjQrOJdERGgL/xQBx\nO6uzJrNrt7Cf6kh0YFyp6QRAfTkuf7kwETESQMUFV2MR8wr0hZHmd/UBOQiPTPb8DscsuSAYh8Zc\nrknuK0zKex9YiHkZeDo7D/PSeuh+WG2d2zJdkM3Td3eMS6WVDFMFl2b5W8/jYjNABrnjK1XwThFh\nYLnSLJi/Op7SthgN17FwYwSwj+AcsR63hVzcnfiVu3ZUXHEZJEyz2HWtWt0RLaZ7MNZccAta93yH\ngOMoJdpfeYUKCCFDGcTyJlFegiSY/R9BWXq/NR5ouF0kpaoEUa+kWjoHoOiSEaQs4XEhSuNjRynD\nrVhVZzcmzBTJAU/E9/o/Hq/uvAStcm39QbP3OeAuNYGNe3sCFCFik9NxiyTW3OEmJSjBcrOnO+Qw\nx7FcS9UJ/wQfURM4P12Z7osL0N6s5Am8NipjMtQyeAtwOcmnJoNC+0+NUiyPWlCuXP/3Z4arSgFa\nZR7xsOv//tsF4wlUna5iH3TC56YNk8nUsFEw6Ge6ZSuhEVsfIeY4wG2IxxjFm7GLEm+Qi2fnWvFp\nirwOxF+K+U92WcMWV9jGmnuJKdDgr9f0rTsSnyJoE6abD5qCwAUSiMOFTLyqf0omOu5SrdwPvxDF\ndftrQ5R+oqkHgkZje/QojcIA5MmPjkCLRdKv8Qe8et8c4lmY6vRi/j86jriaKSwx4Y+Mw85SnPR2\n2j1hg4L1bm3Y95mODLr49QGkDVB7kvY4Qy33Bsp2CTuOWo05KgZSEEXL/7U+fWGzRHjASwfcbgCg\niVFHnASo+4H+F8SItbh9vW9aZB7dvzb/sp41V3sOiSQ/lvFv36hNky3d5TPRgeWxk7ahEnAeBvcU\nN36JNzslIJ0QcFbUJcrGjbreKWGwtRudHbvZZiy3VBuJefbL+K/nA5GKYex5vaF8VvW2JtNaz6nG\nO2mf0K1OaIC26ble9NY9pYrqytCcdTpOisFBK/sWMwJTDavyPDcaK3b2r0z6l8yWe/+kZORkwM1n\n+vS+mBxXx0tf6GtBwKVn9Wq5PBEpboQb7z+jnDgqEVQGEQk44+zDxF6mTiYHaVCLhGP1x2L8Qxtw\nPkf1ixuZGNM5w3J6JjwoYA1WqjGzNXQ/2I4IFQ7+zOL2BVVm8a+5aGNvBOtcu4B12kHIJpqjtEJq\n3tU1eussVADMAsGVV8uDeYtJPvulbF/idSwsgG8crk6BAOKJo99VQxAzmHr6hzse35prsun1dsY+\ntbANM8RyL4weuRCRdH+gaMfEFjRTXyRtKzs19VCSRxpLGUewvAFPajZ9ighUQ2DOA7Kr/rcMTxxd\nrh6hpvfsAFBAQjLiKMsH8ZMXPqNGDBjA8s7TGxd1KmM66Kj1RfzFBtlBuz9LglC/dRn/arEJkYKW\ngOxCUP9SwP1tqpMfyCFKkHci/RYZqmjbNlLH12cl5zMhmsQpiIcZXYfQL8enrVutyHkc8Oplycxn\njTecEx2W4yyRww+b9SpNrQwNcQAZHfUmu5afg1rtbUHZmBW//Afpurxew4MlsTVbE/q+GW4sYS08\n5hT4/ITaA2T979WNydM1h2SItDPecKYro2NCBuNGPCj2smuGGwIqTTedt7kY0lTXqc1QprlIXDOv\n7A/WEW6Ks/DyDbzo5ebBQ9k/Or/ERzVfh5qWgkq8yG0qonueIlbVexyJM/7sKO/BjOR3x/FKDD5A\nPOch29mk1tOqyzjUVo2fdU4B2P5yIWUu4LyA1+iW0TzGEcAlb+9A3LJHWtdxf5XRYSDst39xRNq/\njlN38Ihbn61REmPKmA+LoB8LUMaREXZsyBT2mkJjbCqOmNANgzEAOIj9ceuS25Y2KtrSdejGBdIE\nvCBEfvsJHNzt4EujHKaeJh7o4NDjqLcdEp7ed4Ep3cSOHMCOA874EICbE2zaW5mDE8TG62+kJMaF\nV28mlwI5fMFxipXSTKgVDY4Vj5EWSGuC9St7IfruwsQ039cqwvbAOIuBDwEDSJc6lCmXs/qZhmZt\nnFv7j6yW+vhyh9F/M49mYXMIrZDI2IQn1meVK5DQbu4ISFnSDGJl+UGx+F0w292X7x/NZlrDFxjU\n8F8hH3SoFUjtp3cdqR6J0qgyyvNuJIK0pC2nq9IzjvH1k+PjKgFH3e23kG7suulbVb/rfU+4p0A0\nUw/8qfFdt9ZBcVINnpEPSUJScU20uwWwAzXtPblYceO4Nbetd/Rru6gMmzl4QBV6dHDFv9Llj35m\nrcJlg8L6gZdUkbc5dWUef9LywyJ3ifFwzOukFPVGj0p1G9hRSiNUqdgpYFlexuLPL30vERjJltwu\nf4LrTIZ2VSuuoDz3yvK7YYnre2MTp1IvJIRPF0FnWr5WUuDhARBzNlManehpegpS4ik+5bBOARnk\n2ikf25Ea+euX4IRwUJwiPzAGTUbPzL3cODFaJ4mHcPv972AeFd1T3djc/nkOpMRfzLbUHz1h++GZ\nfguK3eWFxgEnwvmTBOSV/2pqlydJB+j2kzDoBOhHJ7yMYPINzLTm+GvY8+PE6TGpMumpLB79DVsR\nwtH293Qaqs60uwABd29zk+xMrOUEivDU8FIBU3QFpa33/+/A4nI1MVfVSHknip/yEcpuNY2qPJsT\nYuN68cBSWDFeSQJE5yXwjpRVFkSAHd8nML/bKhBZiplgzijzI6AXJOmkqclzuE3gbvl06XzNvh5g\niwbchkuC2q85hHpT3w63G6WwlR9OlnKpzSBsWJI5MiFvl09L3irrYtbw529xtermE/blvOxQYxuJ\nA3+cCbwrhbuASE/lxx/+CQSXsAGEFsG+rJZf02gTem+flBUQWxgYw7USLAXlR/yGYO6KKUiU5mYp\nMcLp5SF0ptsnO4GjOAmsRzhq+nFaThfDeXAXowTEeuWN+d56AInospMZc/eW0bFPTbgOjid6z1Vd\n+9+s7tiYNg6b6j0iAwEiBa8LX50Gz1E8B8Xk0bA4iCfVG+pXzxngp/ZgDAxA6x4B4xS8JSzvBqG9\n3fF/tpaS1x0ZYZNKrC0vl9eX2oeN5I3CbgEuLOUU1xIlzEYHqt8Ta5ZEnYRUtbhiunpXdVyqirCN\n2dgXkldd9U31gMhMY7qFkzBGBtdUApeaRyAGLxKnyg+nwnmirKX9Y3rBKSd6L+R5qhO6n0UbbSzD\n+4en4Cmiy/ti0HItxFAe4vWNWKSwEzlKaZ2HLEPHIUlwN4xiAAyIeXLQP3SyqcvdMzkhMFVdQYhH\nM2F1yAOo3G/JqR2EjrPkiLCy80ya2Cey9fh2IrTFABUwl8LswS7gb3noQTWyDJTWhVsMOvXawU6k\n9W4Jitv0d/+g4QNb1K05p1NtcnLpsIbcTsGei35vIairYz2Wpukkc+QIjcnbRoRYwr386Jd+y7da\n3/zxTz0ylTc2RMTh2TEZRm4kwoCvMb5bRjiCs5p4VDLdB5NKcfMPq/J+LOvbN9BdKd2e8etvM1x9\nZ83qLpzhi7vatfxsU6M1tYzeP0N1fDEQPFerPkzA/sJJfcYa5H+94+uMTRANw63xIlLDhmnCm9fB\nvFsT1znWi0KNE5YxMVAP5Nj3aNk30viM/aEGcXN1+348mdh8cJXP6Se0n9M2ShPtIh6uOzHcNN4F\nXvgZxyI06BOFPCh6pPn8pM/4wkj6M+5Q3d37NGdAT8T8ei4zfuLUhoasw2cJjrdrZ3LNelT1XVzr\ngtfkU+onSthCPR4WS6Xrw7Ok/kkEQoYmkdI7UB9unluvVVQ764ldp5OlFSL6uGJlq53fikq1mMPd\nHtYt08ogxQnb+cC85LdLrpUdkov30YC0DE++eB3VOpsBoGUdgSzOw4L/wn+VuAsCWq5ABwRe4fqT\no7SyMEpq1RX0wDx7yvM1IrLxDdnN/w9pE9XQ1ww/ANlsQf3806Yc1bxBlnH0iwF7F5dr6ExWX02C\nm4GMD+POG+syw7glXgXQ0OUc8vp22qMR4sD57/Oul0voKncx2id8UccXB9vsMZIBhX8NK9iQyJK7\nYG53Y6spKPwBaJ+D6oCzIRdMrl47suvOHOFMlq9EgcKZSM8cW1EeM34Q9wneG+hmi1jxmgRg05WA\nNvs9ns0cBAUoExbeKaTDf+UdQg8kQpTj787x73pVcySGZAe6vE/iMHRuSiZo8GQ7v7UaVF9ntzDG\nTtrPWvFHyuV/SDdzax+LPSONzmqYuZtNNGc7rSFNjipVg81YgVclfSx1PGAIfydo7Z24e3Gz6NIU\nMwj2TtlQKBbeM3mx05abZdGgKr2KZg/G7mtpHcWqPBAwGoOynrpV4ZdlOI7jP3SkujjjiUQJ8FdQ\n9dU1KADRL9hr5MOS92p0+2CDZXdgK1l4EzeYC6fuN9IyAXHsqWhfswpOubjlkJfdxHP/GX3hjyHO\nUvlaWBcZDw7BAWM+AX28BwSssw+yc8sPIxzjHKVjNVz51Vpi6eQgVAZfgVeW/CVd4po9zDauDBPe\nLW3Ffrt6P9FU45qwQ7MWE7oZ3zsTc0evg2krhbb9dLqiCoz6VuCkphBd+BhX2nSPTl+BrGC3EtT8\naS6sDKIiJlBJL+8+GJ5RSEQoTGfqIs6ND98n26dELJI8S0uXSltTPxBhra5yloAd2F4/mmmPjyWr\nTQxaz9QC3JZaY5ciYNddoc6aIflLXGP2kZlT/V1zu+CW+BExE9WpMnVToGI8RRt4jv0a874Y0An6\nHhiPkeDYN6VUowNBrQ5rQnTkFaMpJk4oWUQE3v6avp7Y5alYEE4wCED+ItD2AgaKwC/nFgLMfAnZ\nktUhijy2X1yEewInb5S1xc28GWJeUEjeegaSJijHmFVUCwrnggKTZlbyJ2a2ezSse3QS7DNzMLsw\ns3lvV7VDvQazHXN8RAgvOB0B/CgfYjwZQnyysjBMCOEXr9ltmJw3ogG/vxGHBu667EeL5qOCFKZS\nK2yY/1setEN3lBeyWFiOt84crc97yyhIN9WLadvrh/f0YfzTa8/jZpqi6C6YM8s4vbQgQayL34x2\n47QkQV/JCgk47e027m4LJl2YsaOwIdm0CLnMgOgEGQPFdyZktwDaQcho9eG3wdeeDVrkyzQormhu\n9aXm2HxMwA7LFBoLoLMTe/h9G0EmWJjSZJbpYBym7mGdw7mGASxg/8DfPNQ061R+2X3xcnmG+cIO\nvl0+UTTis+WrgnTXMMvcqbanhkRzuTaNKehiSLRg6bGYM0soIp56mfxn+lCOLxRvrFVCb4SESUTQ\nh41pLzHt1noaHrzs6Gg5F6h/f/xdaHC5qixpm+GAiRp0dMj0xX0roGySULb0Pg5Ik9k6Txub6XiO\nZgO5zmj4Zg5w8I0AnXTXRWRQrHzuRzUxeqeeMsb/JspTSY5oZj06H3vlmxUcBhypLvXrMLcXh/Ls\nc3bNxQvpWzLBqqdhy2tGJ8fAWkun0YPhNwlUU8lBB4Gk06kgUQm222XRVdAheeWAjR8NbiAop06S\n8Wy+XiAj+daeCKkiouMukARqbllP0jcynVe076LG+ZgkcNqoPU37HDyH9n2pGf6ZkAQuwFeIbkSF\nPg4iQ36vkP+KaDnRItQq5Ii+DKzEOXGkFXjeyB2kGs1noDV9eD6DHXsQa0azeB+0c9fKSA7nV4Mx\n1BtiwRMnJT7JPQOciedKCuaoP0Aq+hvnG6MBlo+nAOOlQfvZ8qQxlg0laf4f6XLVWOpAeGt6y0pr\nAw0YlMDiAyvjsrh3t8P4eyWaZSoFPRIJLol9+5QCyrLlm2aVeoMUtwJ1/53pTKnTEHcZIZfi1n7e\npjP+HdzVIccamu4mef1McNibQT4nUfu60LdH+ZQICzwZKDu6slLfWc1KaTXs71UCJzmFmBNREiS2\nXy7c04shnL9MVkGQUM4rVvlqeU7hjpj2FNlt0nq2A7NHDHkEArM25UeIzO+An0jC3tn+qfMDBZmx\npl24RVKkzC2NhWcwhhc3TGrk1gzXt5aE3zkSTGv9pEL/s8V0XrlWQBLq2XFeBXgLpSAzseg2st1r\n71IH25LcYi65u03YZ8TaQSNK5ZQxrVBVO+JVdqF5H+UcYmJxyBsmvTOso+y/z+nGXXnu6Wxeb2K3\nPMCSNT7G7TIbSFmkl2cSMzEeMwmt7AyMdckkJzv6cvcC0j0fLIcJ+ygBucF6mrNY7OMFKMatX0PI\n4UdpryZPtTB7sdMGLH8FqHkw0PoHM+53+V3rRDIo+ImSU7g97SHk4uMmW9/lU3+h4QEVhf1SsCoH\nD9SCjVbJmWSx+5ck3SWahLdUTGE0c66fdQ50VOj3xxA9nvsgL6x8+drW1LZr6SHG4Ma07PvqbId/\ncOHrnVi5FevEja28niNJV/635eMPcCA8uWcnSyTm1J3Fe+CyROmWWUPs1QOJLqlM/Ai2tsSCIaui\nrBVtakmXqv0aMhA33NdtZu3vrog0aJfleoLXQUuDYIGcGc8kfavMyQBG72eZnrVz6/tupr3lLY4Q\nxVGFP4Jxgxq1oFD+d8nf2DrnUh9AyNvtyyOCKi7z+ReLuwDg4jFzd3U9eZQ7WTDxuOYKmerT5+UO\nG4qs6dNLomx30eVvW25a2Z2qtWBywQq/MaVipSr2RmdVavfkdvSb4lRU8c/OXc2j2EjLF9uwD9ij\nR+SremaAbHZZKoNbBX79rPCGwHPTuu2e/3veCG7t4yv5s3WUvVkFPocYD2rO92YBt3DE5NjJ8kgM\nBCj48v+cPe2x069u+Nco6d7scSnHpPHHPSM+6Py5/LgYVagzcTfjK8PlJARVcAMsLJiBvfzpO+zb\na4Rs26CnEdvlCgaKBV1YLeJ2dXWhGAXTQg7SIPEe+qxZanakqfbbb2xT8QLylB2wpP6fAVc2MhM7\n8GAoec89XNo9PAPakTkcl0WxeigJFRkS527gXqWbZigV+8fVkzfLL8ARih7A5Y8faOuGrHTI1D3/\nzLMHy7/g+ESSQUAfGIeRgrKCYK7EMouPFRuxC5uxAYpm5W/pKsdIPrBHWTqvC0PZClvqzFXBi97p\n9keo4Q8i5+/jCqoMSKdh43uf/t7GW8Dcg5wWxhGnjWC7PMUgwEzMeruqNa0zB76K0zeUaOmh69WT\nQE+NgpCq0rrPFoR4W/hxQ5lqPWMYVQs08oixXrdi4qxOlpMbrxoLJ9dbreMCg21g+h8idnl0Tl1L\ntZ5uVIyA0sfNcXr37h71rInz9wjZ2D+cn1MJf9A+S9uhwm3BGTz/4NlrrXLFirxI7VfKkYEQ5kS9\nUmJtizU6dQ6Ehg6JDdHxuh5l52FvU7VuMVMozDJdJMvbkeQHAh3I0RSRxjaUk9t20AqO38NUWado\ngkUnSoEZCLnKpWk0YPx/LgMwFeFUGPMwCcZ+o4LM/G/XVGe5eO/pecve0eHmEnfeVBoIeGUVNgM+\np5FXp1hflAYwWYzb3FqUrZM6TMi1jBAtwoA8RkCsrYN61H3rOO2e29xzDffAshtKB1dXBUfI0Zxp\nVN8o0s2S0sIOL0Z6Y2+38Wn6hSTm9pUH+2vQjPt5mmWo7cg22+s7MbGkZISOJNCM1mCrD3s08ZAJ\nwSe0IXxQ9GoXKl71fWfyxDOEN80E97kYHfLwT/anINNK4DYOqinZPKwL6lPcmfztT/jkkYeC47vc\n2LKundEqdpIO8cT/NlrAVtDH6t3Fm9VABN/HIsAxIiNvOpHUSrLSF1keYvjZzNPJ5FRQgPns+eTv\nGP8JvC15MCNYsPYO03i0V8tim0p2g1ZGaidN0DRZ+8QURKlhGPX747Npc+Sns6GK2hOpqQs5xmC/\nkg05svfxeKyBc+mnkDT3BuW6tl06gkPpjvfgTxknS3UtGnjHnLRzXmIjQMl2IQ0m0gzzccVzi/72\niZtemsxeuumi+UP3MrCWaN+wN9xfBDV49pifJbqDeSGoznX/Zcb2XT9kvtBFWMmlBG27ZlbXviyw\nPnR21Qdpe9Ga3f0oQjJGGlKrEtk8kpZXg8bTyYQAlP0cxQpKZU2EjD5JPPrHfj1jG8shz+Fu/9Ho\nMoczpTM2n3rQNUp7R8v0cHO6ikm9/A1cUv3WjysTiu7SuCs4gBkotSNY2Xk68SXZWzYgFxmK8HXy\ntx9sdKEH13yEbULEXA+4COwl/PywoPj/Nl+Ew4Pwcm3TnoqS0GSPt7HJPOo2hoOxxqB08tPM+X0t\nB9E3nmeN6WGtdPk5mkipZRl6B32i/Zgg+ya/eRdCQdf9fg9Wyl1aioGzWlZgA8sH0At8Y7gl7NYv\nGsBJKYY9eIu3oVdG89uBhlUj0AOPcTOGIyt2OwESMxURJPXjak9Yh0eSBLOasPf3rxt91kWGROIx\njBiT8eMt0OnS2yu5HO2Eg40cmIqsC2vwtJoj9wOdu3zeceXfhMsdMoEsk85U9XUNedzDXBDY+d/K\ni529zO4iKsBwTRgnL3+Qq6lgmFdlFvr4PT7x/PusFTxAe30moNx7vtlthoDXjY69raOtJEVg3oac\nlEa+QrsLiy6szONetja8Xwm35OWq22kBLLd/fhaSvhSgxFNpHlINTa+dJ4OHbZshSM479f3oy6Gw\n36CHvvAUHpTmQiWWOqNmmUHHHnMRxvyySNkV7J8hlPk547mUpXPDCAheNrbQCq7Zg9QcaiQWd9qJ\ngnrFkLP+BjGxkvJwrV+1jUS4ymZ8io4U0EOc64Tuk3B2OXy4e8bHbNs90VoNbogNJ2JBBrluJx1L\nQ4+/oI2p1bd9BrWyi9lb2v+KL4o85RzAFnSU5vGSjrIx3lm/ZH/QN8/90o4qJsXwnwzwywuIEieB\nDYWlvqUtcnk46xKGSj9rr/PSTZBd7gFkW0W3nLbd5MKKjVDxtdiKjSV30e6iwgDQZ5rKvLaEPVul\npiJd8wgHGnnZRT6oMODzea5SMDG1Mx/Uu8SQZWcFTOb11D7MmcZD74Dh6kGsUS+qfY/P6LK5ZyoN\nHNMkZtEiQINbI3DG2LexnjcnXgKqZm2ZXGavRz/1f3A+4d4Rw6KoWfXIZOVUdNn/l4FxU3xw44SI\noKl1tT8NUagrB/gafvUWFBenLnxPxW0TaqMp+/lnAdDvwHLTwf2p56K21HxTlxXAb2QmgQlZB6bU\nDuYRjWtw96PcNIcEhaffTdNRFC37g/+Rw8qIWX4+euwL7s7q0kxKR4/TG/OfLrnBR/5+jgJGxj+u\ndtyDwjwrtChjTru6KPXODLvAm97PhZ8NRtb2Yzn5a9LjbWYSBpxjf4eyfAdYjEw9yPbjJpi9AJAW\nmwhWv/9b5rkxkeCEr4yQ7tXZTLx9l9hQktow08Zlh6pE4/8M86ah/0BFrTA8TwV1MQM9W2oncjGH\n+9q2b04TNO3wbncrECEi4DtBvtfYup7Ewyn3GlaO5eYLTg2/jiNmLP8fy893XZvRFmwsQRwnyXCo\n2nYZv3H6iAokmm54kiA8wDeKeZH5bMVRb8coUhzn+OdVrFqyf8myg0lyTJzy+bzzY4Pah1/xh3/L\nbI1bdfdg2OoVS3n1aXMOJQSoBQzk8F4lkSgV14x0kEgcg+6I2cD6IG6bQHCLflY17NMmKnX7MQeQ\n9ARoZL9Ftb6h6jt+Yj9TqigvDbbli6iYyt/3iLvMaE7nKbkI+BcyGR8FeD5rz5Sukk8W6WTDkgsD\nYzu0DTmAkRvyAwCKiwy6bzCh4dzKWJOK4GMV+psXZepr0io43Re5pRIkbdTsNzCzimW21WR9ePZ8\noWGZGUVoCCHkoM+VhFyZgrFBCuEGtlTrL1OhJnn8G/vmj6GzP7ppzjqtQOJdd1NT3mIJtM2MU2jK\nSJ1bL9b1YgSVmGnENvIHBs2oDoiFeYB/AdsDKbam8Ofe08wTbM09FVlDEjl4Kvym/+mlqBqdjB8W\nBTlVuLz1Npwe2Rqin9pAfmf2mro+7Q+P1t2MkMMBq7+mNXk6t7f1EZ9CP//mfVK5vfUlm1bJwc7h\n7zjymmmA2J7MYyTiTZCFm7zKpr2m0yARdirGbh5+XEerjM0JG1JFcunC/BfW4EJW+aPNSQhpCcmS\ntpvSqc1TiSkWDACL+Kld4mtOaUOVAjJ4IPoOKrJtnDz5EYLStpqmXsohKLCt+sy9YZ7t7NEdk0SI\n+i8nrAQsijEAoguMLC2r4fcfepagdfAzf18AS3Z8t8vItfUFlgvlByAWPD0pAxEeL6gRPo34mHvp\nqtb02SaAbEWUaCCZNhoIT+MAPCCwxxu6OEN9VW7YQw/hmrD4e4GyB19xhrNtuyh4zHoN+FX72opr\nxOkXzzghtXGGsQ2q3/6cNaNiE7P1xigeetIkjYaEOogeiEI0BuF1fbJDaLfReX9e6jXiLvhJ5AQe\ngiPAl3g0FjDUcmDqjRteAhE/PNHfoJUSgu55pPfO0NY2t2Z2Ye8DF9v/uGaVuFA1bhi9O6ZJfE0V\ndCrNoO9JVtPWadZbKqRoRYR64EhOYf8QMWXpQea8J6pNasP5XG62E3mNJmZhsEhO8da14ofQAFnr\nuw1npXWWvVGW2OGong7N2Kwh7SRpeKL+2tVeUM5oyRkkegprU8oY6yDTmkgW4gzR3iUD9r2yEQQR\nEUrnBqjowX6/a2UbkSvengDsfeYrIn57XZhpweU0dH5uBYP5FkquBKbngRzDWRIhRjpZOeNBuquj\nX6fJiQEmJedr3pyKIPHyXEepzbIAgL5Wuhzk/LNljrsUkTz1/vK9wk75QbxTXjCCi0MlhBUnf0Rn\nT9gWptFSKOOspcWHZzz1bR3qAF6yX2iGIpC7CBqaPPjOSnOIr1Qhts3FByUz2W7IrG7VFIApG2Qr\nZEpY3450S8oEjLqImCdG2XYabHF3KyViSlBMveVAn1qZGku+UFjoqKXKLREhng3hLqooi6ugvH3F\nhLD0lteBKSVsoGT5MDZ10f0FHDYuDu8pt7Yx+avdWuF0XQUqscn1y0GeYS5kr86t+F4ToSMW3ovR\nH9BqBMW/e94nritukUh+pUU2ENfgPglvuqcA55FabulEONPo2iV/4CdTcW3iZD/sNsGF1UHqf12a\nGB0N+vCYNuUpx9LspYpJWTeHOQslPRs7vWN8S54MBEJuS2EKLe8/vgESL+G2BnW7yrnXdPGpYRi7\nantqD/KGvHSTv4C2mNcnINFPsx4e4JPlmwJwsIHL8ez4LDfzGkbQo3znuwcl1FgqMpr/rZfAbjGd\nJnMlIYAo47jNmAfLXWB+SdpPEJgdYuuRi2GQKLWkI8JUR+/CMdKDssgcEyaJyvWOzURvv1hQUUs8\nPkMdKt81i7zFYQjiItlszd2C8zczwlH0eWE2I/wYLwBYMkRn868QftUBc7WCXFXvjBndT65IzaLk\ntS+XJHy1Fk4Cnnkwhr5UiOJVKXMm45H5EKxjwXZ8si08tIgWT/TPY7OcTvYc4EdO5sqbIrOIlxcJ\nA9IOjMcJqGbEoWMAtk2ASak4RNiXlg1zb+mt4fLZDqvemjQOEytIdpDjsKXex4b1kwug4wZmGlki\n8NSMfJNHvGf+G1NZ/qm5S3ZV2kDMvsq1CbBFSw/PxZ+mi7bChotalY0y4uMUAOBSP9kunqJAUrMn\nS2uohKVUiU917LWN5sndUR/DPUfV8pwKaCkdxF5wwUhxZriym4suG9nSYCjgTo7RtHPM8zJ6jadr\nTOy4MQeh/41kZsJ/XYpc5ElRTokVajxpABDhLz+d8fs3DQLWhTQ7dAQFzaxKEHPQYD5+qYLkSURA\n9WeBKvZqJTRRibHc4nbOfxRMxaQc+EAAjELMdOKS89L0XejFvCUujsz2fzQBJkpDyfKoXWLRko92\npzHpWTlhRDA9s5b8PX/AR77wA5ArUGNjqLmVzA1pp9zbxZdgpjqCLi9BNmyv/dg2HOuQs4tgw0Wa\nhIkwx7jfZ3N+FEnXqMihEhWujWBIpFVWJJg9UJ8Cj597k6j613fhjn+fQC3KCwnC2yGWi5ohm/8M\nSpdCBPF0n3F7iEKeRYOe9LRZGXKsa7cPF1dK3NOLqS9L8s/I5RGmzzYpuJX9J3AdnFkFX+eNJqg0\nKMrTPSxtaHUEe+by0YZm0zlcR9t+oiatQXde6yVVzmFWgcmsoz/fDx/AOOCTGxthX7cLvkDnRut2\nzdGY+x0SPOUVq9Up20+HVCHHJVdvlDHnRcwiopLP9EVVJJ3+8+zXcRwdR/W0qU3e3tjHMQeLcQKh\nJEXrK+Byiw8OmW0QMfzy1sWD0q0/sbMxlvt4eq0rHv2LvmpDayo5mQXKasNBMKdsSCFzmjkeVXkL\nx6lrIBNQrnRK3F9WHeo1St/Vlx7gKX61STdUZx3s6I2o9Fu5kQ/n87oY5kGnfIYy/Sqe7poccG8s\nnwtvT0W1l8YAgjLp+y4ttwVZN1u2Tib7vNpCGWTeUR4N4HZlfTWLkfxHA9E6qHgLyLhFdQxD5MjF\nzFCW5kFcsPysIWupF6wd+bHTvxMd9+e6km+LqJvwX9TJm0/Tuhv5smOEetrL85LZL4hoOD3gkOD9\nux8mkIV156Zn5qAXgRhGCBzTAoc3gdEEAZuM9CMnvGFt7nYQqUWozJbVNIu84YUuW9UaohW0MdBq\n9OmTNAp1jaYXjqH+ZcW4yCPJEkJKLw97SJqnlj0ts5ypvSx0AsRbwVqIUkBHIRTEuqdwXy7ffZPz\nSuwzY87QGmpoKvLB/NF/8a/XOC/8ekWrTlyNU7kOVZdUUan4xgg+rmtb5dxRQOg2+Cg5yB2KYpFZ\nGLIJEaN5ePx6OuNsKyGAnoL8VB4CVbYL2YhLksaWv9aVH0MSEQBH+d+Hhh/hyb08on14QDQ3IPn5\nPOfH37BX1Kt4ZT9FhH9AqYK9+IYyvlY1QZqMYqku6WF19aB5M1k1mnxoD9qP2OCDsvW0PulTcPwe\nbZWzXBB+yCTURvqwPmCCGg7Botgo7UemIA/YDo6uZQhRsrlLBqrNEpQRRJvwcCZadPmql+bxVLoB\nHRd0slNjme8ocHNUYblDKhFKIO4zGW4vkVS2xu86jFCJP+AUtWtEoBbRuFb6se1EPWSEZccg/tdG\n3S+yZwJXmSQIKiocBNNsoQl0ZuYObaHJFh/ghdUlIm9QpTkoUQwAdD6P2fVXHsUxXitYILj9Eao4\nnl7koAUxv+egJe38T+XzWu3qJvZlze2xvOmAAXEjVQQfE0DmYJfZVFKcDVdg5jYqF8G8FxSmQcxC\ntIn4gkrqg6EV87gisbn7qspi0sacZ6Q/1gQAURtDxooDDK5gsV0NEhI7EyoinLXjZJ9SY84+Bzcw\n+VD19FvREqBGtziYVyJ2+YAO9kUgWbuDuEy3aFnNOeTv9ze33bOAoAhBDtbJ4BJZt+eGcbWYWlP0\npMcWI4mKtcX18daNTCZR+LgCAw6J/bR3KiArm9ML52M7oEzMMSX7skvxyTaIj1zojGgXeZXvki/H\ntGHQauTSObrzhFf+YE5t50078XpPzdQQVhn63OgOKp+6Rie0Q2OZJJP1G9PXiAViKajwJ0U6IoUK\nVG0LJhSYwAOF+ditODWEnyYQJx6u4HFg1/OYPbRRf5SL0HEyB2SOhxzRc+QylENCwbGWxkJ/MjpF\nucxP9yehbXSUmmAXr6u8e0PlT+0MEcL5+hML6XanaR4sMnepTVUB5OQKCOhz5bVdYkfJf/AZhI5u\n1tj4AjxaqRwn5RhHqqcjspa9oAXyD6fTTd6VkJtf79obE2Vn0/CkZx5Gc/vEV6Y/UUsQa0+HNWxC\n0KxJ/LqbD+0Xo9hk30nIOWumBfNHVFNABhSH0FO6hXe1h7DRvhESnhSo7kGWpv0N7/A4SIRMybQt\nC3MeWIdBm09lya/sOlRRHwnjh6BgZeBEtPqYX++mSFDadrZ5912qAYsGsdIFlk7+p6xospuH+IyQ\n1PP4r9wg6I1iF+wSIukIJgfswFgAGBtqgDHhfMaea99tCTbBODCxTlvVOkbfZwEcdfqDQJioj+nY\nkY//DSMVhLeq/3yvLCdiembO06ynPh1byTgwmALsU/RT7uf5DrZBontbQhHqEaFGqtf8irH9r7Cg\nJC23F1/SWnAd16dLnUjiqbXwbIoLMHbD3pnqvbyyqy7FNroWPX4qTHJMm5LbSMWNMGR/l4ucWMxV\nky/QnNMEU4wvxoK1RI+mCtU7cdIjq7I9Jx8vXkCdnLnAXFb9QNHosk8LwZfmibS/xe8bBW7lTtzc\ndbpZwB90QL9ATHHTbwX997qQwU6f8Q6ZjTVx8VzS23VGBt3KmFvGycKB6dmPyzvkFWiQW+Cs8bpN\nvwr1sTQF8HierHVZSIDcGGnQ2RcE9sHY9ywA2gug29YJOrasaChUvfzGHMkvgAeWBLoNN45Ptoq1\nHNYIOiNBDDt8b2NxtHOlftvoV+KQTNTItY8HuSuvucGLRFZ/ijxZMp7Gka8hw0omBjJ3K/Canqk0\np/nI+kfZ/ww8PnWSkJCV3iTei8yb9akSyGPtimN3DRXg+nm9F1vhe6ZjwvfxYdXsR9RM2YFddDJj\nPJ/7sbG2ySqr5AI3utiP/mJsP9zsIUtciEXpzIiY17AGEzEf9WZc01mBXJheccBxjLpk2hOmp7DW\n/bolFGQo1u0HwOCjvUQEN/VnOXBf9dUC8dHNpljvbvcpY97VkVLl1hhLXJ1B6CZ5pcmV49ukA2yP\nHUvkv0kKuJDG2kjj4LUJ5YXaAGBdch2MCw/ET+X9R1Lbz7Tm0oYfP/vj2oQjxfHEux6lD/Urc2oI\n1tAqwKd6r/F2M/RmthYfXTEpVDUbiw91v8Sh4I0wwtXOQr1qrn4qwtP90lOT+tlF2M8TKR+rerOz\n/5Xgv0CCYjY7xCg4tuF//w6fpvgs0Xp8n+/+RRHW9SZuYLcjNkECku4X/bNTWgMoAfJIJLIPFZEg\nKFFHSa7PwlQqsQtO7f3M30QtV+S6oPKAnAqXuAd8gNhhlzMJ4O71NOrGSrsYdqyKFMu1pulAegSk\nQZ+uiKAj5kh/P0Ce6xKJQVPByIdBLuUdKWrNSvLdkjayB5YrzBXr2uR8Z3qtXmVTRrfhblbKcmVx\nbSlQCkpVPIWCxkOIc1vH7QfvkHgkz0Vh1O4Br6JIiEDbSD3WhYk8pT3YrbNfBhL9XWekVTilmC+E\ncoRGgWwOOnLGcaI7bxVfNZzqrCajMQSnYQUipkO9bAkBHiMkdegZfmnOCpQgUhIRZAmdKCA5IYZs\nhcQolXWCTRNRgfH7AkKeeObiP8KDY1vJ1LZx2YPiRrfGHoQeAVKnpo5Q+XF4nsb5FDWlbSF9WK4x\n3r2tGTKoamdzjbn2uks7TO7uFcTC1hsh2iFiECPnECYbt25QcuA6GhkCaQDMVCRlC72dzdy8cM0X\nNLgdEMCfAuh/pfO5Soab4eZFkdYi0lUKw2JYfFUm0MsvAYUhYEY0Hv6jh5aRNCEz+5cuDw7ufd7P\nmvD82HTyuLstpgQVz9MqL2IrFX7zOwsr4Iki/sE9jhAIqK6UNb2lrwHuhRS6OETJDguQycwqveDU\ni5P15/S9l0xzS0bAffASHIiHDS/nna1mXJMzNA92v5SHt6iND+4NgaspRFj5McYl13C+pzciz3D4\nX0zSkKlDQTpJZAjzqyduOgXcU5sROz6raPi+V12shPmKE5aTU+nt5baf0/qBBo47q2UjQMY75tMF\nRVal05IPRf/HOpHBowN7F02gfVE7H44F4ERDK/Hq1xEtrOFK7H2U3ec851+lya2zTCJR/Xcf3VBe\nlxb4RN1NWaePQkEcv/YWnNpQx+wtJntRzhd2+4ZsxawcWl10ffFyNr4ZHupqLvX7v4I/hqx48thY\niV2fchI4tKi54R4OpsCf7NZMQeEvUspEGjrcQxpHVgtMx1vXC3/lApBlX1jOD1aTwr7ThB9FbEPp\nc37PFCi99PpLZuExy4twaIUSOK+4IOfnhrNzP4+bb4TObcMe1gbmAED5+fDlwoMUWWRMMzWsyN/A\n1xIrOrM7zcDWgLZLcIOfS0spfbW4l41PKSCbIcNrB3jFSBrcwm0pQbneAUYkURTiw0Js/NskmPQ1\nqg+UnXhDdicyH0Wfn4tVGjaPXG+qMWBP4Fx3Z4tA7m0jIrR68Ao8aX+cbhBeS0kMS/j246amm0/s\nCXDiO60Fcdr+vOQpO10O+LjBwZ5qsiJnpnjeaJqXT+Et9/jkV5Fjp1xJ3EnlachHDM//79eNvK8/\n/JKOSm4wMLqBigZLP0jzbtnwgaUT77pjjr7T1mI5GQzeY3nuBOxgyscRlg6qA+96hZ+yXXtVArTR\nnf8MO1ycpLPgEkAEsRETTvNnDrfQAd3EFl4I5oisHtpNwuZC9DBflnl5hDZaZW8INJHxcaYffeOA\nI4SZqRyHEDisnaRsUSDIwcwj+tUhOyJyOMFqPYPu3W8unFFJc5VDswkGf2v1azZ9sqH/+QC2r1+q\nvmU/p4fmXXsNumWv6mJCHSInANf3xj65XGYYVUADHApABy4FLykn1IX80gOG/DkB8tArpTRIvOnL\nymsyFKe7bYMu0tUnlo2TPt/h8MeCWZiDdodmrMWa35AxrWLyT0U3n0ZtHC6/Vdt/e3T6oziJ/eVg\nlSZVzkrl/F5IvDwa6bvb6U0s/exSaMcTOHYms2e8B986/g+KZ9CjNQx8CSaf/8NGvuVEXtnONlx3\nLAWQZyLkf9AlRhWJk8otSYNkhQ30sHgRnkTwxaL/hxEClk6MEI+Z5UJt9ycXKODHuULHepLOcPZ6\n14Qufb3ZpVjOTbYmikm1m0IX3bCoKrUhj9oXXboV9woaTYxH8fx08ABGoDz1wA4F8VMn3QUY+F4A\nsb8WtvEmh+XEuRlB1edUNrN8WEkKjj3TwLKejJhrheVTvDZR3LGzRN5p/Fiz3f35bZUALgirF+Xu\npJhpoFYB7CAMH8og/F+Jlma38Ms96J/JN2SLV6bxpjWe5s/aAFb/m5T2WMr6f/Fi+hR3bYw2ANUU\nuDrYb3BZizZl8oAm3Y8N/HtMXtiLLPo1FuXhV/I/dqimr5RkGNYv2vmFyIRzlTWvf1OoQdCpp/8e\njsVRC2nOL5aja1Gbrsb6xLI7v7zOy3OXXnL3A+5G/aRzJIi6OYRIU9iBmF4cPrBOeljwsiThjyIo\nKFFxbCwY3TLsY5DzxbRnwXg5/kBxZOaES7X3X+zHI5eyla9CnQbfH3EUEvY3EV/37+8QTasY1tOI\ny905e4+8SABe51gkubKLjrhy29UKH7O2fYpuytamltn64Cdq4NhqTcnJzHCqZsFlQR2d3NCt85uw\nAMhm34FtpsIt7/67XzcvPhzNtotKCiLKN/Cgm6WqDNXxXQdqWBpk2t0ruAhp3IlUhukD3Wg+LyXf\n/ZO143HqZM09ejrB30WW0BvJbccuf5qb0GgBxnj7M/eDXJJPxea5jNDgIz5AJ0m2xwLDSCHWb2Wv\n2gTrQlIYnhFqNF51eS9oTQcHL1NUd8J5WhoKC/tnFnYhqZPSXTiC1F8H3rMUITUwIwR4Eq5f/SMy\n9vvjUuHFbAre0sYO884yH76/735dC/HbyF81vbM7uEaXpOBXKXUyFJwP5E5GfEcWXmllf5c8aS/0\nX1aavdNjFTbB38PKSNPR7vE4GYr8QZDsjsYzycp5vB/F1X1R55r1oHlKyB4lyggTZMjolN7L0+/K\nh0SaDpL1hBSp0datucCgpkHAK1ECDvvnZz/EYs4aUJdU/3zroy9RYIfB24/4jNs5h5aCBTMkmeiR\nAMIDLVnyEReJ7oVzZ6u1b6EZKmUGyoE/NAWcRmSPjTUJgrzF4ERtajmDO5hzZdyTOkti/h4tFdJl\nsaYMNAKg0w+186Fz7c25LLBkit7BG/wjrAPz2cW6JI3S4ru5pGGi85VQsoeLOW80nnosEnFDip+V\nJ7aDxGq9BSwM50DlrWdIxbvLObiVnLR8Ar9HAyYTzspjd0FPpeLqQVnWy9kn6nIT5CqukkpCwcLo\nSlct2bLxTcQhrwQucx5/LHBYpKkrp7rrzkHZ6P+cTUcLHJNyJPZkZK3heV/f0OcEsM4EKLZpD0g1\nJv8wATCKBeecm7/VqyQllTUUWvP69Owt0G4XzttdIBz8DTPtaI6ts0hlmbOkcDTTvBf5mZ3rNmnw\nlg1mysjyO/US6Fuiq9t9+3Xofstc4bHEm4YBjGCH1IHTDzvQccKfnM/cqleRvo7H5eXiFsZtPp1G\n6GOcsXHa95RzZj79MoKZNjnpEY+t8YauJ+ETl9KG2HPb5yLpP6Q6cV2HTp5GNHhvtcCoWQBAiqHO\nbxr7/HrkWj51SqQJe0KV/R6u46GvpDHfkVkDlouZTZy9uiFGVIo58fKeM3Te6Crcktg/2o5vSjkO\na7Z8yu/uzD4/L9K5yC9W0SCtqS8uulGQZpEHMWNlzCWY+pOvRSTSp73IL0EUO6DI/7fF2UjEWTyP\nl7qk/O9HvnOrrWAV5MLHT2Axk1W7H5akhnhcPAA7Lx/Q/Q5iLoPNHVWxjlvlwLlwWq9OaQICR4jq\nGDNMi14HM8VyANmSUU50AAoSn5ABDzSXJ9eUaJT/oU+O6OyAckpg07u/yYW4BkTMw8xIioyNOSqn\nvyJ7cBAB7X6KOj/KjRLLt2J94Qj6UBECe8x1PJ+/oKc1U5SNGmaDsiJPYE42OuvkHxD9CXzez4zx\nMiigISEAWNHfQrcy73vctjtz9y0ieOjN163Or2pLp5RE+4EnBTO68tZ7DiFsYAvgyApEJfTwTzS/\nH+NfjaRftQPoB23DSbd4otwB9wqCTcgyKeHfwrA2tWNoBnRRDh43MiB/X3InWXASYwMqfd2bTAXB\nO2ZNmuvDjFCqHdc6XOPqtha0OlB3JmvtCjQqmRjfwBDEg9nRrUo5OrhjinJ1ZZwsA6X9Oc2M1jUP\nlgQgjlV0P/hsZqt/GDjLt30k3e6DvQg5Ye+Kvn8MkqXne8Omnj4K3lzvEKXPYgWrAr6+t3IuGKRO\nr/774W4XqSnQXDXYSsPlm5VAGXmAqncVo5ekdQw9di1hmya76/G8VcN4QK0J/Q5c7xhsRvZUhBbD\naoZnX74rF3GIzaxID8PujDrYDMP2QkRZijphPCywc/l0jsldhR2NB4RW/kYPN3uUqK75cVesEaL5\n5v/AR9/c4p8tdoJRCWfRRBN5m9RRDQl3XFMUCUPifDExugkQfos7EIKRGrXely/Hf1bqQd84KBHw\nQgmROHDt2QlItAPE/wtivVzftCklyirO4+OmfkftzxGbX1/QGxAlJyR0gmm6RvKa1YoKUrKgK5S7\nXscl6MYwHWn1FJriTwerIP4mWdDdbOdCyCWKVqrv72q1sgu9Oofps4WpH4Id8HnAUAeoyYdHVdyf\nJnSE8viWhzvF+yf1tjrLZZySiZWT+ad44uIZkAqC4GRPwpOiYMPcB2Wa+1jl9Sjtp6expmx+u/5h\nAqCBE5nVYwwbNJ5/97wkl/T0DZm9KVtrlWoLxqYBUhTAfQ/Vdd5kx3Es/xK0tvL1c62UXivN7/I9\nVqga2Z9NvKTT8owc+ZOI0CANprFE4IK8JbXKrTc2NMiULmEnCU8OGYBYIMnkxGLerH12+A3ChuLx\nHIhcg1avfqvOounj2H362C2fJYDtmMVv5i0y8x0+v2FBjrTzdrisolTypKmUZ2MHXga5ZGY7mXqn\ndgkFBZOS64qYD1nIn48V5Vlsi7LF5aLMCOZWlXOw8WmIF6glbehcEFsPSnmyeQWeFK9duIjIEiYC\n2S0COsdbabYyYPGGFpz+iI9h675DoLj4BC552U1qA3tp95Z5GrD+9NcJQeNA3QjGp8mHde/skpX4\nYkex6WxEDA5ppcdy4YJO/pIrDUz4Y+KJm2AHQ8G/1UYNLy3QQm2xvEdP165sZy/GgTk/MxGtmTrE\nUumAVGVSTzDM3pMWOXMbHsDiCoY+LxKBmOofdTajcbPQor9UnJOOh3bk79plZvZkj/kjgc1ipavu\njT6UFxbm9ghBi9L6eUME4BbN+EiorSLlyWruDKS6fq83mX+4iaCshfP6nQnuTU1728nJ1U7J8h9l\nq+nruftauizB/m2VnGlEUGvC5d/olcqk6pWiMeuemTJM5+/BeAZ82XblX62hnpwo2kJhh0byu56B\npAUGKnLdamBw437+UlRRmPWEp2UG5OrqjLR0JMf02lGeO+AXXllC0ji5T+qUuITeYpHEadr7rg4V\n4vCNuTSmTymv06ja7bmoQR69HQxh8GWBKzTOLLC0knyElBbtUMaLTK8ocsuJxklx/fiJ6dcTfyay\n17QKT9aSN/+h/kzJsmdd/rSI6eJuQzg5lq1pM9nNggWdnDkZteF0Zg9YFqHbGfJMRqZuHxiWWHYf\nhs6BYwa1Si9yITAbky6OYkMYRRXLKB11R+pmRoUoiwr0xLh07t5UF7xEWYTqv+9KueNxtSOeV/+f\nEdo7uzq0Dii7Z8WTX2z7Aga6oO50BUYS7Zu9EQqXr8lj66On35fDlpEVb6h0feMPSn8Z7CCYxZxv\nrrgpc+B2PXhRlSumar1I9au3GrGSzbXaP9tYa1pWTWneUxksfdk/VkDLBuWlUN3jc5hvC0URlDsn\nV9FN14sxPOVWYbJt04oVou/R5XA4BNMUei+KMqaZ9LsMWy3qKESHAs0vomXA0Q1xxXac/zDN7LsB\nRTS+2gszGrNQQd961iFcXZUTQQaittUszpL3Z1wklSTLGQ3Do9eYkpQ4MXTmKjEcUcTkDd/8NA7M\nahK/cQ2y1mYEyJRkYFICvafpDj2h3+Vrzbg9cJ/+E1y9pNY2lS19jiEtaCisx04TRLUodD8TP7UQ\n4/ijc61VHaWa3tTgXuk6D9hD0oCiJOSUItz8iavDq1u7eDRCMKfEuHf2v8Ddhmkd04t2N/NQRTRb\nIoNNHHHBrQ/dszA1gWrgEV1xZ0dKWps4R/gk47Ow72agtIRoPMhVUyWaBgxaaEF9NAB/0Knc79/h\npDrIRM3UDEfbvOJJfBhGpmEXa5waa5PjxFrms+lsyTs58QeBBGPyfXH1r00fkBCCrhrlsM1QQTrU\n048xf/oyN0tUcjE/B1ZIBe410V5kNJfAtxAh2VPfvVbgbecLqGm3bRUljE8ozf1n6ARxD6GASLmc\n3GOh/dMJqp5oJn2sOFwv+B+AYOeGsnY8Qc0sa1DnEwTVUhDCZ2M775dMR3zZGEM/kk1pALwGQ6Im\nCnigap8WJ3+AQ+x5TZJsjWnnsZFbKiAITDP4+5gG9BpBQwVL7bSQYfWAYV+HsZNkpN9DYVKoz2u/\nbNnXohT5+gKpBQYKTg+h6XWaT/lwjspKXQkftnXwIgZC2EoA3j1BVjXTu6ePnVHr0azUwa7rhzUe\nSNoCfmOWeqnZSvRbVB+fRNZRI4hAVPpgptKPpCgL7DekF+8a8+X+Rca6jH9KFM6Vat3qvo4j81hW\nxg4glHb86eHWcUlzAW4wQR/D6gOuwjzvEi1jMpNNzZda2vtnd6b2QWQHKGtf2V3gPQNE7qp0z6tn\n8zMGcmW/WdC4n3Sc9GSGmsVAzNkoJmkCpBSMUwSbM1Tu1dX8eqXtI53zosOPO/buxyAkhN9sXDC/\nt5lVZdFQB3QqqT4xDjY+CwXxguwKeogUHQlcmu2PyndG1/ZlougRvZrmb/Lkw6bwLFHnuYLBZbov\nvAFBpbSKNKvQkZfTSwYiDNvc8BMFjMmjcFamwmizpssKFLlKIIbAUGDo7/9giFPRr+jOsQsmEYM4\nvL/nKadZokw3N0FCPbZNG7oP3I1wFyii7Klje6QNyIu/MqYQmb/XY51Tt3uPm7Xfc3/tNrmlri9s\nqzbMC9eeiwC2HkXHim2p0c4EKVWinPJkmzzHhHD5XqOMojAJPhX+ZblrNiwdx7yZ9FDd+udt11t5\nKBAtGk+DkDqFAWmcK77O05i4wt2nbfCYpoKyN224bqN/dwJBUcvQDeGU7zCkK9cY/M1RyGyOrSBv\nuZdwpqjj52VMyhC4eSw0VKnH/dkjXE6ob2Bu4okt1VlwfosxgTLiKv30Nxqa6xsSgUBdLW76YgRM\nSSxCp+DlI4KsYaCpTLqAkTsNbWs/XXcz+KkpZwGT3Ak7gUk9gWYDThPEGhAMifMZoNiuB/frOteo\nErLJDy9+/CBi+mwbqwhlM1mSLtEL+QjKXQtFXnAoKwlV0A0S3Y1F3eZVIt6N7EGpp+GqKm6pbvJi\n19Uv96Xgojy6KuRIp/r7ylJhgsaZmktjQVHgyTwbhlwc443FUjShzjYUNu1v/lv/ma3v07n/Nu1v\n5Ygxneefjd/BazNEjUTdLMV+xI/8Z5v2ZgRVVM/EjyzoDUtDR+/Fc3MUuqiQt7vYIQ3vJshwAQ7H\nq6dkx314RtY4hRvZUCGU+rnX/qCmenpVXFV2xn6Cc/5OF4EXbr6RN/qhCuiD81yAQd/NbjNEOtMW\nVmqXqTPsOOPY+FHam5EW4IxjWPRsAIX3P6My6Rer1kJd1F5zhDJbArwUbEm54c9GQkVXxhTWYIqF\nvH+Qp0Yy9tyMUnRlASj5jMvgwe3cUuHPxlyPUuZK+rK5ayJVxweBf8s8NsE58TFti+6DGNH+GMoj\niJrcHMl7JIRez9U7WoBdNSTa6Wu4FsIQskSZAPRnqG1YIhSSsLnEaonRZ5jHn6PxFIsGHWLkRRTM\nPYYKNKVMipW3WnaHIgiN57KTb5pXBGnXQxTZWgNJ4Oc1Hb/CLPxx+jpJFEHcrEa1chVQZd0SORaJ\nC0zRLJ3K6naY4bpkuEtRGvqnEiC69i7rkR5IYJVZn4T0L/IaF+HxfL2jZBzUqPiEpBIkGRIoRoal\nnAnVsez+Tf1g3sKGGb8Jc7Bvv9mbKP5r+ciY4SkeEHFCjRtXAHTU2sIxj+cVDrOGcwgj04QZg1CG\nf9j+AucjM1EmfmYfM6GMwlJ+jju7bvRNsowv0BBNlF7J8l98+ikv4vmUYM4WSkRV/jc+XOLWD2y5\nyNpM1OjVk1/KAG/In+VQAh+vgz1+4/xoyotLH/qRGT+bFxn9tomW0+Yzn/gahFC7LGrb3bI0eQTp\nQSejapmUj3nSlxVQ7dpQNZ0NrLwA+G/GycUyauRzRBxKtZMNHDmjfuBZX7Tcy7YiatzCZ6M2eST9\n05E4HperTb/cfGMm16ME0VdyxSZXAmb+OckEFGyGvWLoIVi1AdQUkJAh5rbT1QIkSS95m6iNjS13\ntFc+QIFe0S9X0DKXeRy730ZfGzxDHl3mt004W60VSMKldSaBLcHxxkrXUno6fZskEcRQEFd8weJj\neZkjtL6rtwkKjYV6x+cAqIRIH2CIcwgvi1MM+SbuB7Ej2OHbWGsH+ae6kDWlG5RxNhyL9DD4xcf0\nDdxElbdQ8rphwwoJvoNEe02bsY8iwtjuSyD6Y6clNaL27fwyCzjLujIWDUy4CHvK7Vl7a2PLD+dw\ny3uIbO9kn1IMMIKHSlomNpPap52CEIksHGtfk+4XSYfSkQKKp/kNqVVR1RPQGFToDqSveiV0bWAu\nSEee8c2awA4VDSIte3mzaYqUYDEfpBfjlJ1kfUOttH4qAi0IgL4BL+9FkiKjuwGeHVs7r+v2X30a\ngWOPSwAX10NabuD1IZjK3kIAgJJXnmco2ziHkW63XC2rKj3imToI3yyPwL11wtrAgJETZGrJTxO+\nMfLO+/2U61Knhu2slj+hYdaJqoIn0DCviHnI7DIQ2fAgjjaBl5/Er7USC8yzu0STnipb7cjZiTZP\naakr4i4vGo4b9Bd1itUaJzJtsdWrkVcFA2gSmBCHTYdro1jelehFneB/aDR7mxtnjz4PoHdES47A\nOuvVgKpCzNoMR43wGwKzG0B32o2W4cyo5fewsH6eHMn+T4EedcuHmgurYiN62uO0nz+M7aIaaBjS\nbPAJW3sIHIEEdl1P1Qtj5bpN+FoHJO1S7NGnxpS9OU7QMPd0thdPovlaO1Whwj23a2G2ry9SoW1z\nY5olooVHpgXYzMH7/aKVZy7EIaC6Pq6ILrl+N6Ql3+UuOAhOVuIGmgA3U234T48fYm736NjR5Gul\nrSbC9/WbAzLVLiCWKyxHmQqbSEsaOrjhz+ddTL3rcvzVLwFzhjTqRWQsPbtItebs41tdPf8MvInt\nkHYDIMP1RHhTu/5dAS9h/X3tQYAQgRhCHOAE/4uMtfdvIjgAe8fs2gC8QK99+EappIfJfUkvZKML\nn7JtFbyd4wN7CU5dpNIk8/RsvM3z2u7jtDa1yIZZIHNQfTaJ8WmsrUrjGpbjbT5lPZoMiQt/jblL\nk5uJo5y4kpVNE9Mg+OlMSMqekZyUeFSHuGOBn2smMqko+UVNaCFxXInWjz4TYpqXp288S605F7cL\nLmqsI1yHvV6yXa/8DztLhmbusW0vtxUKU3I2h/KupFTrxLHKOWOrxyix7kJ4L/g8/PutXuU1kAoI\nAu9OkaBF9G4qAHp30Eb2fxolsyRqSg7tDREIfyA6rPwj7+gY9z+2g65bC2+O5XyzC979ETBl5EmI\nPjuXiDRlRRDNtKsOLoz98L/9GAnV0AudrPU+sgVjxwcNfKaRqib2icBzWMIIsL3QLhhQxLI6bZwp\neya26npYMw+VI6+huptBzOaBV//Yonn62HLD3MBmDEsZRbSRiedUiuv7FO2kTlQi66FK9h02Uf30\nzrbGSKr4sRI666hzuzBE11QBkJqOosb4dDlHX01MQSKIc2w5pKvfi1MECCATgZMZ7ilhizyPHPhM\nqYR6erClv/4mrKlfdy/eRyaWBenWkK0J9aQB62+fNvXWRJ3F5SQA4xtCLxOlSKoqQVV+311DUvax\nEm5l0r5y8XMpy8Ig9W/TOidKG2ruNkmtRHwn7fomGNnG+YRWvlHPYkKcrMXXVZYEHhVwrwv0FRdw\nqqilhFaMowQStCU6A/Mch+SK8shJHK11OJnt4E6n7GSS0VWWIoddIm5+RK6+DVbhGIGMWvq2c+/r\nUMAozYzqqMD/iC/ZUuMEFaGnsRaf7fDLta1A7VFGGX1JrfJ84/D89+TUzIoiJt2a+mlOv47F/nIt\nDAgtzOSYGKb1NhXlkc5js+oaoygWm3Nl2B3F52XQd7P+eJfDpWK2TjB4F1BX9GMnOlI5S3kWAp+y\n8m67tK5JQgHqpN0CZ6yLbololzSu4PX3gW8kafdkgnx/s11MMaGgmdlGj2EpOY3RmzfYb0zUcv6x\nrDj6PCQU7tjBx85GxXzUZpzyoW0vswvtkLufpFueFe13Lj/xkjdwrV9ztjg3RmEWpqEDhb/ewj9w\nMDgzH1m5Waee3zV6RsdM8OywzwGB7r3QEi4+TJUT7n93NRH2bl++VBegv12aakTzLHKbSb6HyWdE\nUctb0DJhxi6aBKuzwBDJ8IXilBnK5vb0oGMpyvR0+SIG/WehKC+lUhfpwyKzZ/x+BMz/AakXAFHB\ngprixyoHCJS+IyJRNTufZoRpXGD/NdpZEyuZEAOBoY4iuamF/oaWgXBZgaa0NGa7axmq8VyYXhhS\nXRaEXo0XFlyt34x/Hs3t5P2AwUqFOhBalvgxSFuIdt8s1SfXHA48jwEBSY2mRa/LrKm9DL7CVsfd\nW7AcoaS+xAkMd1ZA7zGD1+xV5kFBSJ+oUm+BHq35pBGjxdwPM4IYx5qL8t5y6LkBzYVXQeXrYz3n\nAPikEn834V2RN3BXwNBi++a9RQG/9kyZFKAgjy/EIEDqsZ2Fz1a5AD+kRnZMq4Gy8FqfvtzaDX51\n/24gW4s+KdESku5GMoJiIdxYoPSC5yYdU6maW2zfvhU7j/VxHIVkEAuL1jggslz7UvWmLvDQSvyg\nAOiGhRngYu4hcVry1NbfF4Y9YOxx5VSFvbZcdVav2L76PYXQvfZa6b5zAj8nMtYby/auDzpCGggX\nIFig1IHnalQgAmlg++abElpqAE9+F7wlpvxSuMr9qjsXMJFa1NLhTAuYn6KSATMLJtmc5ZgFjtV/\nqZI83QMNaqgB/sFXO/zdaW6lc3DKYv0khan0DLyxC9ZYoU56KxHnwcsy316h2kq+KlFI9JUD4R5K\nk+NKgW87SF7e2IsYnl9F4WoeUQ9uu1TrYwvbBQikWhMo5zGJ+jDNnZE0hXYvD7zLnrpjNxk8u1jB\nVI3+wFkgF3y9dft9r//mAputCiFpTIwLsQE06NCVgTlG73PCHAGOQBkEBW1i6c/u8at890aDr9FL\nJulPXrkRHnyQlGS6bml0RA8vNJpoVwFRl2QRt2qUo3qTbXDEV9aj3xXdfeEseUR6MQCshhixhNj0\nKU4YYyNjpsnXLYyHerXk3ioDeukDGLEyA51ZK07Szu2UDcIFqZ+ab2ZHiovr68NcLfw6YE1qkg9c\nYLT5Dk89XCyGIdn3pgnES+Sd0tcg+T5Pp7nx1EigHx3ZihMi8Oxe/D6guDWy5TSL1G0ZaC8BvFYa\nh1C5Pfr43DjEoojJFMUyz4w/w5lCEUBEh6E8gXjAMVjzFAsA7vDjdWz08GsKz+CFWPXVVrVAaIRy\n19k1gGQ1MRtI7CUf1wWh7f416K2hwjHgzz6cmETCt7TexIThgarGxn+VSXO5pr5O1/Fs179fijJE\nLmwfZInZ5GW/PJnyfU80Z3xD7Jf8tA9KEhVmkiNE+SX7QVCho8sBVQhT5B26NKZrKHXkuFWKcBsM\nBhB6mZkvndJIuBm6ALke5fJITcrvcci6rA987B6eGw2NVJK11fP8ugBJBkmiSCxH3U6uXThxgqMz\nPujL2p61OUB/0gPUXs/sr7qt6X9/kYDGwejPI9ievkME+XteHvCyDtPlq/mjoWYawo1wDIP2NnLV\n+0QatxMMZBMlG6naoEf4pifcaMe3CAyIAlbYCkFgKoMf0qVgdHd05KcNusDkLqz+bNqx0PyHucx6\ntQNR+G/WKS4eXcAdwTudTPLXuqY4T5dXr3EU/fhG2oKFgHJRrAIllJQn5it+B1ljBrm8BMXVZC50\nkm/y/Dv2k1RZg83xH6UoGk0OEw29nx+XrBNqjLBViBHSdzLAg7XUs4irDXyfhxGycqBdvG0a98Nk\nxNU46vJazVxZWSL6U6mAe6Sv3Sr9jGmNIgA/VdbNk/SIP/AhthEjNhk/19pheo85ryTp4KL24Vhw\nrSotkbHebmTArYBspDLozvV51DeBkxnLdq1AwEdI+kiwzBbiud1p9rJEfRCLlqRYOI2rNY48L9Lz\nVwjSLp1+SKY7ERb2h+5bygkAImLrivJNuv0yj8p03GAPfu6DwfwlYjr/ZSn5C713pe6Imf5odEyk\n2g27gNss5gKol+0fnIRlZrAdBphbK+HDGns5LVFnXt6nhEEzzrhmhY5q8YS8OBSR09NzveOjphSo\nMFsa7DV6Mx6FidSa3xeL8Kiq98kSg/JzKmT917YSdmFImgN839ZxMPonkiRYfizHC0bcdFfVJC9P\ney50x1ZvNhADKvxaQoVppfhgjgY4RAL3yo8CNeL+8diNOvxxv7VXL6VmkVHb0OPSK9T7jM0UNC7g\nx2kdywCP5JyEAE1ZYgyfhp0cZseW8D3oJ03+f6aWUefyoDW+U7lhbahfjP9EC67VrkOC0aA2r1qb\n0EGdy+Wgbo8LwZqlv+i0kT6JJVzJAs9m9mIkVRdSau7A6EtZ++Gui0K56HTnHxdBZpKPLfaMY/Vq\ncO5ShwiXPBEzE8G5dKmjHC+z12W1EDxgsCLar9+YOAjxKhgHkBGfg69+NmO0ydwiFZtkb9kQn2n2\ncakas/WtmPRcBrFKxTJv7hrqsa0tATeeQxEfLYe4qtlUzpbtLY2FdoNRQlSxUGJ4pGgiCSx+x5ri\n5dbUwJzYin9/1AkNrajyQ1igqFH63Oe5iA05U0OBHL1TZbqVJu91v+1hHGccThB7kV/xn+sWCL0Q\nmMULWQqEWLR9aFsTO9vP+2fvOf6Zwuefn0MzofCFTwq/kYuMgyppHBeqD0San0S3+DlRWFbvQxtd\n/2tSB+nGWbiKevmP/K3gE8oRdXigzg7xbPH+gh2lCC0wJmKwTgQwHIC31x50ZJkg8cci6fVAAw/C\nVHXrDrjZSiroK8utPInMK9UgiLiJZaxnv6VMTQfV26pYRuUPBEPpZ4PLypuOIcDs1tS4X6nUNDU2\nfNyzzsyS7Fs6nTKsfTb13JGw+dOOt4lMUIBEU84U5RQKL+jrymEyKK/sSA4kuQYjQXLCHUIIG8G5\nHUgZ9GKsNo3ugw6mpQdnfJ5cW5I10H8JLWrMiCExw/s1EXPyeM59eTd7T9tDoN1rAZKPHG/JN8dV\nh0oYFXVBv9sIAGpOy1+yMXyrapdwkmnq9M75xOw+4tdRAWNlhGUgeer4qaGwM1AiZOh9ICdC5zLx\nBQ6+b4pwzgxHxvbCVYSY3J/6A1H2OWZ/DJsHbkCJzKyyIJI6c9Sj+iL7IWOEz3kPoTdwojbxnFjE\nFHyzNYqDISswQg6KXYsPWTEGpB/obQREvd+ABflTfjzhr3Tjftzcg8LURNmOgUQANWT1DWQSbC19\nmfeCmEA3Y+mKQXkzlCARoH1uXMPPUpVC1ipWTPqeH7TcwHjaNCNhXgDS/uk2Z5GBD8YiHzSvAuVf\nKZvULyg1j21LI/bSkfQ7+lk8ROtqWPv7/JtmfKo4EJbyI7aQPWjlTqdH9mV0ELtfD7EbTPEhwZZQ\nHGWfHrL778ObaVgVlJ+4cur5V5ysxaYVfZvWa3RzOCv0QqOo2lYVW6b1BV6cZPLYruo7o4VgOq4K\nzMz6Tv5RTu1X/Q0sXm1kmGF9b7w0Pc5x3QBxIGCO+NzcC9HZekrjxRIqqqG9SREDtovJy40tvW9B\nVLyL0e4LS6wq+BG21T5Tm3wStOhCHnyJAneG91iZNFnrTY57YkATwIja/JJiSnDtzisBcdOXsnE+\njF+WIPe/OXaP7EXFwWnvQcMy3CEeH0v9WQ8R0k7m5/5LJUSKZegVF2vImSnXZte3+N1jLmIspK2X\nLSW00mKB9e7X0tmoffFcNa5K91v5qCKZP+jH9FlXfo6FyNfnHZeBtYWE1rFrWkkNoyffdTydMxU3\nHsE7+QvtoAiGifQOxWPvyL6jtcKpDsPkZKwWMaDS6t6CrUW2+7FIzIySi4GPD+UtldMfOgfX/xY4\nRwOLpHM0qz77Vk7F8r5igDm3YdRUclJRj/9p3PhuaGURCCOfvYY/1YtGyn4pRScUV0eI5mWn2HkY\nPB1KwhTPUTGwVWu7Y3fD26njzSehEGb15soneI8/j2u57nBdio7e76zBGd1Ae28DCxlw6eheUL+t\nVfbb+l1BrerQeAHVxnm+duuLE+rNrPfp+17NGTOlB2Qf1rcFqQWYCmgEI+VzyOhWARntifEQ91cL\neG3JS8IW02lPLDfwgGnw1jdsBDrP490+YoZQxAo1kmK8lSjgUXuTchXZtHz6I8/mHaTDsZ3ZJQA3\nNXIjfP4KlMMnUOG5LiaeDZ03uItPx33c7XIlhC8wCHIeOQHEnRoS7Ah4f7M3FP3oommN4YQxreJR\n/uAHpkr0sCdoRVU3J+7N2vwSP685CNjrqyl78reB2aX7Ty3g0hVKTHlyPzRgA62N3Gfb9vMrk+W0\nY78yHpQHiYOQTwAsjZvyYBwT9f/ldXZVwC1YIvI20GQ7kL8uvhV/+zbXVzv6kyjHg6HZIY+D/+rY\n9JnqgDOXkANYZNab/6uv2j1ojjDqBOeZShxkJkbTwoWc1yT8OmnQVIXLmeGTpGuabFKI9Zi6Q/06\n+HPwkG5LawIar0MHYUs4lb8X9uKIVauJZHO3fCfDJpfE7p0weI+DMayYvriGCPSu2+0cO66waMD8\nkoQKpOmFxHOrio+PflCURVPrWAdtiOVWfTKpPdCUgyjcX/0SNGNc+GsKLpPgnseR5baF4rxbWWCj\nkZQJhVLuPemR09jsCHluA70+mz9AXQAg/pa7bfPbMldU69lewVO7xbwqdUDy4hdTZYJCwX9TNp1P\nNpCzdGsgoswj/88Cy3icvq+rPBdxfqogbUZXI0ZcBQuBSscM9RPagLxJRYfOWbvPYakgaarvMURQ\nUKkmvS7oHX3jyOH166f1V6kX7iU1FtSODnMP0RTIiVB1jMY8PPv20LD5653dtu8nhpW/yxdeaulB\n6HrUOModOutJHPogWpEpYquKf+DCjyztBIiWtsXp0rIdpdackzsWc3l3gZdiLtsV1BhLCsj0FJw2\nU26qRLCKKxk0axjYCW1xbCcNn2Ui03uJuYtzjrQJU/ng+M40qPAoIOoonXkN2va+Z/XjAlJvXRLl\npvwhi82zybVUV7GX+GBE0mShC/h7yvkzFiRrRDA/RwRQur+2okCdE6dK8hr1zzFE10JBP0d9TUS0\npK2XqZN2VJ/BQSHEd38SApjeg4BZNbFB4+Qm5v2hy9XGHVWFBr86STemwiPK/HTKyvHbsTG8gt94\n4Y361rCNBFPqISw38qIcz8ooUjFi622Y/CWCjDz21lLX3iFDIFf/ZxxqVSlJM1NoqsTHOTYaVwF7\nhlfj1vG0b3l+cGCZNArEGD9fxGx3Z8OwL7Bzs63ULFNDz9lM2zFr4UU6eL3vuRH3yJfuI3H4I77P\nffLuBWlPBg9kdeOw+bZrrzSRIRmKmYS6kOz3Uyn/i0ejd+TPM5dR+qHmiFt7OZjjSaf6pYIDxuFA\nDZ6PvZDVBcTDMavNkIcSkwsm+B0NwELE2BV7pbI7jpTpkuTQpZAIcuURtrHRXOohYiktQX0f2DId\nGDX2juPGYqAkqHn2O6TuzV+PKfUMTryW3TwkT2rIqBqzrGBtN1hU0JVrCaZAM1J928FQGECowe4C\nYw3phOU/wxWfcpsDd+JjsNmQP1GrNaLeCvX9iiM91ya+u8I0UPBSSpBhbDExnHRQ8x8L+Nxrv2P0\njVZpcPraT1DfqxmICYoVm6AY7rdTgJrjclMbYmafOsUk5wRRTQVAYPBpGcA93u8qLRqEvvDHhnS2\n9RKzGmNUV0hKqNIF4f426z0tJi0IkRW0znccZmt2d8TXKzYkCOfKAliSBqpZS7bodKplqMqc4voE\njaPXEf1vKkbUQOV5HqmvUiJPI5Y7jQrosCCg5VL2/oqN5DodmIqCCTd3vdAm/tt/b0IuI5mRfpP6\nV2Y/cRCrmE+MumRavYpcem+l50tCbeSbglB4grrAtBooNSiWou5vd+6WISoDxewgOeJQGew6HhaX\nO3eGe6KfJ6TaL3fiJuZF3hZ9XXqyDuGrb8nQoAt6dqqzzDpGo1JaPScwI3EIpud4EhFE1Qti5v5a\nV3Vl1+6/UJSBa8V/BrByhZyt7xmrFz+1Bgy6E+Z8DAH3rQXV6mKOieQAoUPkW2mh9tx9xnFpbSsZ\nTPYhbec2cj4bGLI5crXAxEScCC7qH6wD4Zgnd+qNl2NdDJqKJO+4hUlTbuc5wXXvarGBBhgjMHLs\nXGdXVwHOm+Cc8rKXJvr7+5PUUtnwD8gWKxJXPimyS72D9CW6d7dkhkbP7lFlaWAatkkLR5ARwFbx\nMZAF9W53PRE329iWi8zBjf2WDZBSN2Q0TcA10dOE5nbnbfeT01IkqmqARAkQh+nTwL9T3bR2A8Pf\ngmwCqBj1+5rRlYslJ8CZOrLDQgDuLDJ0EbX+JSDcQd6jEyne6hgAaoZs41ByP/8g/PE2alqR1kRZ\nTYhiSUk5FbaPSLijYoL5o1w7Zy0qqdH/p9GBtm4JO9CVzc6hI09H8Uk2lQbJPzvt9YSlv3v92sQz\n2TKxXXtBQ+mUlziFQ/8BYitiRqoE2cdR+mE5f1X1YvM49qIirMbEuumBGiHJqvkqNUZBHU0ZgVKg\nvobG6mF+vwwH28e3no4tQ7zOa/fDVprzZjLGnvdPUjym+XCgbrKyypqUWKJ4/T/4PjaanyzPvvXt\nRlcGp/nhqI4n2u93okHPDK6jV/5phIyTYsLiXu3CKgu+8IRYdXYOiIo/e1Y5WDTKYgQhmBVshF3g\np1hGuj0SPHrrAaGaEG0egjAyMEWxwFicIsMjvHDzms9wj7SGPo6CFt4YMfar870S3Mr4rqPPTLEl\nKaX83QSEnw2lHk1wIWIFRH/7JbyQRSmJQSWe1dyCNY3CJc9ckpBwv+ZE3JjOz/eE9hu5cxojJXoW\nlr5td8y7IAWzChiI0YLBwLJRGcSEKYwgbLcICqV6JillP9J4X92YlMW6BHoBsMhB1DOl6TyZgMNQ\nVlZGWfNoYelupoRkIT8M7MzXISDSzqoDIKM5mr9eoSAo8ib6YK3ODFN1Ipi0Hm+qUVh97Qb3LCXy\nJ6TLZ7yBPe3PyN9tI0DKKMQaEf7MIeR/pJVXBGsWw1J8lMeUKMZGj/PNQ8jCoeKR8IQWRQA+u08l\nvi2HhJO/OOKzrT7wWfTqQ8JQJWoego0wyxREKsmJVph5puuURbW1rqMZ59X/1NWVNk/LbJ1gpEhD\nRDB7m4Z37EdY60O5sOgWAgfgocCGN+qw4b+xKacYxMN4HjXO+wJq18wCTE6+j/Riq53L1N8BhQ8Y\nGzmRansnzeytnsaTfsvP369sjt22XF5RMpCRvIpwnBzhVtSbsoEOecovV9J60ihS9Fe3klm6gBY7\nO27ky2+Nqy6V5sFI8PXp8SBwkwq5pNi/BqYrHGV+KbX8d32v1RUYbRrV4F6ptibJnNz0aU+HQQBw\ns4RzTcJUIJhlCEM+J8xX7HwyaUGYXM4Vblpw6Pdu9uJT0tjyon29wMG41c5BLhYFL9bVxSB0rylA\no9dhCoNanyu2VfmWH0K1eh+YJaNXtEb0ysEmWhCOAN/BB005lvi/w2S97ehdtGEWfujIFXRsvCgY\n+RCIDAxVVZqHL8q746Y3NWuLClwgx1vHx1NcQUcDBNsRytgo9Gb0DigkKNt+dAAIGmfD2l8RTA00\ni2rxwGF3erRv9z6mzledqzEO17RKC31VFamUnhcuZiDRaRRCBnE8GuE5BHaK8rw79pL1YSIawfMd\nLK7hHkbaDI3kT4s0uTl+t99PyWMS/B/0yfBkHsKDGfriLreKrAncpEeUpJVFKdFGrPl1HIHS5ZEX\ns1gVTXjNJJrMestKVYaEs4nViCstGD9zSan6JhEmfaifIkJ7GLKw+NimA9uOzyKvxUxfRCCFUSvF\nMprZGCfJ4ltS0NYsdjAs1KQSH/5sn/PQ6OIeDHlZ/n3Of315bRk57pzLC1/aVqAi8XLsSRefF/uG\ng/x4R0AMUW0mo2mdnHH/TY/0iT8LYCmwQO5G/dkxHjhJRFJDZ3qUZid99q56MwmCVIj6WDNBu+KO\nQN6QM5N82dHzc1QI4OMalKCyGwtF1fJoK6eNGi3dVQTES3YoHYpJwy9mkxPa0rvrWLS6/4KyUv+I\nEDZZY6lbAg/ozYCu+01v8P5fYavZmOXKq7EICFKOmUroiCAKQb7RAGvnYqGcYPcJRAsDYdAoIFDU\nroKp2Ovcei4dqjC/IMmPpx2utomxn1moEPZkeviZ/h4Jw8M+YkT9VrkRWpAoADxDnDqVJm9CyRZ3\nZYi06cQ7Xi+nISoqnuU0wG4niseJcLPhRyK/eN25gKr33zC0KA1F90dGy8K2XjjGkAy166Fm+3nU\nL2M0OoqaJrHkmiE5GOorVEOvOcgQPi5mcLYVduX9edasttXX1GWuqS6e+TdcltrvITA2mCaGW9W3\nuLXjKkSpq982wMXZ6Lezt5GVq0xxPV/hocBpYZGNk1GnQrKh6TZ2oDCwL3BfXTqGPrO2BfEl6Gt4\n/y3kZDSf1MYEfz0iQOKOy+lWAlsnuPolMTRzT1cOGY/Xo5ZfvbKryDcTb6bhVTvO6/ytROqjAUmQ\nTHPlyl8CeG7hdq6DGm/TlWk+DtDGTXDeiF5IwFeBRsJPlaQ//IAkaAdtGnFztK5xLzNvyFs87v/9\njkbEu4pvPLRGn8alKJB8ZZ/E12VD5owB7dVz3WdKnfFS+ewUVFFKFM/LqRQIoLDfau36JyDEBIoK\nCc9QhI4knWpjgd3rc0Ror6hYufUfdIhZvbYz3935zgckWWECuvAIgdz5z2ckO8J2UHAmrLdWFxtz\n7NFYheF0uQVqIWu7hRMmfPVEgJNVslEfrtSENg19NvNy3vkke892kD/uoMfkVuyjAkS8PzGBrXJ7\nSQqI6VjMifzTsYMS/WQ+kXXwPhjx09QEncMmZSp0thPdg5CZk8eEvrZGprWuaWpDs9S3lN+NV/qh\nEaMcIGIuEMxbxMgD5WtZb20rxjLc674wYAzoVZKd1k0L9/5C0iSgJUwYBe49dyDOKYUMctmkESxi\nVd7eT/IqusXB5Q/PLFKKSpIjnafKrHv8yGyfnTaBC+kzTlVpb2G++mJNfwSbkDuqAvAoKjPAVHv+\nqzQVAKQ0+UOmw3T+29c4atCHzi2+uB2N0pr3kiOHQ8yooLRMdkn24q9cxynSkIZo1/dARHNNdxa3\nCJv1zraDIX2a9McxBdYXYYPeFRe//3X0Icj+fafoR1L6ZnzJ8pkqjZSGr7s9acLQGxabvRMGFAlH\nVSEB3Y7eWvxapneBKniIGGujM8MXaz15lv9RmTiEqxfRsxRhgthrhqNWOlGWfz21p8uZT/iV0h9Y\nfzfelebsnPN2uqnYGEKFTYTm43VLTKdViucgm0FyCsC5i7j0MIw20+J+3xPhA7x4++Bg0WIc2oa6\nyZWBWrw09oorWa4VXS9O4jd/qCs1lXQO9qyI4RaWmg1w/2nMaDgx3InEckVMCboMIeiaxntF0Oan\nPBiBdb1PPzTtsMmzVNpv4Fjv/cOEPRIRFPibNg3qhLCCRI7H9mgzfUzv90GEsJjMVTCAhWsuuHo9\nwGzpvadtd3ZPmPsOFa01NwPTRw0Ka+zQf07NZ5o1vtUsD8QeGQdLQQ/Q5OKw2HbA/bmpERHgtPaO\nU2pjfnadcng5L589GtL1Yn1o8CLSPo3GBOJXJ+EEsGHxmSytk2TceD72Fzn1at8SRZcjtsb4Puy5\nD6IOS7UeaGPeKQA6l11RgJHgfZbUgaJmK6tPYXZqXja2NBHNAlJGUGSUdtTyFwrSw1v9Kvbta3nm\n9dSQggcFLN0jfOh4Wx4PkZqrNAn4aYXAl1hVDrYSJYeIi/g9UWvt4lKEKzII7sSP+/Smvc+DQI7c\nKrUPoBrCwwSIULOWIvTrmc/9H9lyRuvvalVYoO1UJ4h1QZ8l8Awyua3XBfn+LhsE5y8En3VMKVBK\nHDDhGXOo1ly3kQ8NfiYxpwcHcNdNtrv6maO8YQ5GRGqef7AdwOaB88p4d8Lo4SDu62Dzf2fkdySN\nvx+zps0lGn2ew4IFCknQaUtUaHVrSDUG/NZZQabVDl4WAdblcpbCOW8uTiNoFIKFX8dP4RYXgq+N\n0wODhInglAFqObFfIC84RBfDlEA6t/45rPMvS12+uDunWBSZHyVY1Uwvwu/pnI48lV9m61OsJCLO\nOIgrpGewilIwhStXkjxdI/PB+Vez075WfTee96epvw8Gy7kPD7RFvqrDDIrSGm93FKnRHplTj8O5\n5uu+yfmzGBWYcqCbo4mJK6V0M/SJnB1HCGbgLiRxGy/WnHWjaYx9bBqMbBHImuGlpEzPmfDKvgV7\nAlHvpdpzcBlf2iAEr4jhpXqh/KwnRQ4vJL1P84YbChWf4s+IKE0AZ6f0vl7phKgUVq+P+ULvZdoT\nqnWO0Ig8FCSr/a6sZumTd2V59t1HdZTvc9V7LHv7XW1ar8fwPredD5AYEDMepb6AgFxec1FiOc3D\nykbfBhIXJE6n+Yn+BkBfyPaHQtr6CygbQYqPxrWvwqNaGqiR4M1+SnXc1ZPUCuO3jpsqErNCpGur\n86gev9iN95nwRZl1czxWVa9z2Vups+DUDYNl6OGsA3VaU6eY+zfjdw22WdfBTQW1yLZbKdfPdglM\nk0W3fK6xVQmWd7Q0MFJx12rohylS2M3jRt6ymRYDuj9G2x7e5COQAH4HvGSj1xQao0Oqt1esrJ4a\nYIqOffOvsSJq932yvAK//wpl7jU/meranK6kL+SFodAzXhE5O9i3yUroUaSX5y59xIfZoFg4NHP0\nM7zEBF6QB2GW8onP2jBMjRx1c2YyjCZC9I2gxLVNFMuAynr8b5R66ZPqvrh/8y6Mqr83orbrcV1X\njrDazLR6yHEOtNQ4bi8mN7w1RxzLuL2h058RZGlSsTBsO8xP6HAr5Kp2wBfbvI57lK6CxqUspCj8\neO92O5CNgGOfYdotXRnXfVffA4XKFtgvw2Me/hq6OXRjQJn4ru2BJA8kDP43xdNfLhkeKIZM3AoG\nTcMCW6giOWLiADsnkr2ofGgeUFbW+ngIOyctXvMwRFMD+1K5RpwKmd9uVYsHK5u+PLBnvBGoyoS7\n8/m4+m5zQh1ucW8F1QfRwl/sKSrRq0ciF10lQ6zYZB4lLAem6FOmUFaoyuBVPiQdDA1ZsbW/Oy9h\nCVMHPZwPrJ3UnrPvs6YOfXs2Jlfc4nyTMV9gez2SwA0MbPHMnpIcvsBYMqVf1NbZumEG5UI4mVji\nsP+Lo3Q+cV56vHImYilS916X7mZ0gHna6WTTGV9UyJ+Du3k0Tl5TlYLHL/ob4uKWbj822Gt7tv23\nAJnMLGCkgZQbYYRLwv5C7jFKxzPsaYrdBbnhN8Hzj8uWglOv5NmXOcg2pNyIv6Xp7o3P4/taZy/s\nbavizNn1qFu+wczAKyYeOCD1GOD150qXMwDfJGIaD722D5IfvLbBJkBz14/nzS42fO+i/NSflxqQ\nIh8W1dHgXZR1+1xGFhfpNgJ73eVqPltXA5/xNtE6EWKAK2h01+j9T0mPP+TCq80DejbANcjNu+ug\nQ7qp1/IN1oZBnRQf0DNejhOdZ3Ik88Xhwy2Bn0jLmvR81NTNbmVEoZf6/LBhkmC++d5tWUODaE3V\nMmjV73rV8eAB0kRkj3yGu5GLwWEtbau6TqRGb0BcVzUlzqvF5MPetFqKTBQY6sJENoTXq1XQjWm6\n9wH63KFczwcmFRWNgBpkvjQZUGWcCIlioS4fuoQg+RfiCszpQm6etlOglZq6tbo35s7iHLifH2fJ\nXgBvGhw1Mzh5WLkhF0SZtXs1flSvmLCyJM6MwWBe9Vg1rncHvsaqt33+9kknBEsl8yJuvLzpWHIq\nIOyjgBz9NEl5RNUhBXzOzvIRK9F3Z+fejM0uOy+z5JQfMyUHKAEhEtGivvnuKn5Iv1yGYQbKcWzf\nrLxAQP1WA+5zJeTLRbU+kco9GYRaVaIvruvNy1wYXHcRnwEui9exP//Ej02tNULykhUHv7P7iTnf\nYCwad9m+QexSnt0Sf+x7TTYZGucEUC7Y4EDC2m9MsTtXFuhHgin2e9eHMTm7cMiFUf3O8h8Qszop\nwzWvIQZOkkv91HzJT8h4L2b0+s0LMTK978OOGCGHEcqUPGyAWN7nOu16o2UjvQGFPn79rD1sub3W\nU+zCmNvAttFgu659SJhYDXnvhUoNWhfY6acclg3KD38v/SOAfl/eq+85NRYWvJtweiJRYYtk0vVs\nu6EitsHfSy055na+HIelCMTPbv3+3OwB8KNeJGveU0qxSv4okxF8YWWxztNlTRVWwx6fC7LrHTJS\nXhjvKRWBJrdBkAn903FdNO406+gwfbMP6VAaTCMo2gsunicIpS8xTA9jcMdcnCyP4GXLvQi4UckD\nQNgqbWYvw5fxTLOWyf1Qu4u6Ul1cRBRNRqZ3sZG1iD58EIMSS69VEvYM1w5CWdFFkYZesNsF2ZAC\n4RTSQLixyOWbPHcCckgl3/E4FZCkIi1A0xsbsyirad4r4OdBa4ELnPi0ASWPuCJZp8QxIx9ohBTU\ncXKA+rgTrCgCLzavqrmNtp3Gr4WW1sfls95t68GeO6SScz+13sR+D3gkP998Q+3+9ENk5i7fJ9/i\nQcLd8GqnDZaJ/h36F7+cUQZg67jcA5APE29UEhwTU72sbZWGcGykxoFo6Wu8gG9xLNC2pPVSdS6a\nF55fpU0b9k7eoRIM9wJyDoF5jVRrL+wNULRlvZpfiLOpSwjUKnZ6ljjKtTt6qfsye31ZSpQbTEDi\nei67gpANY9oE+l8zI+oIf8eBQod4TXK0aotrRsx0T048+WvCuIiR+iczHejTE8Pdi8+enWorNp6u\nCcR1yfG23NU1xEPqbMjQdnMIw2T7xx8WBpnaS+nBJ1gNENmT+JS56BNxD6xy5OvTLAQXjtm+KiG5\ncnsBBCY/Am/rByb+pNGepykPoma6lXmXc5FMpKsySFKxXx7y5zorfRE9gSbCmTG5Ltvw4142R91i\n812qH7JQQPaumVCKm33BGCVGuitsJfOfv/98p8oQPsV6SftmQusOjQSyn5Qm+dlpy2+VymZDEnTc\neJlGz99qQGTvq8/CnYHNoTodEyCv3uGGGoA0TqUo53dr7ssSRbAFgdsyRHMDxepGAcjkw7T6laTd\nqtTg6VF8hWTkI7MN6+pMfl4m1JUI3jCTvL3r/vgV6Kz3ppGiAoXiSzxy4keXJ6PAPwFmbGMVtZay\nWyEhiliGvUyzaYlZPptWWhQOtNFU7fxXPiYE32GVZIx+SiWJLnWydxbRC/WlhwgNYcGsyqSZMFit\nsNGCmXGtYx50tvzGxQwzehYg0nZ2T3/PJDCx29bJ47EO9lmaIUUPuHUmene0vI1Pu3WArggyDcZm\nv2T2/rnn/OkCTuK9/cnfLCkG9PZvw+b6Q8iqL81fUCaMHPspDM/w/iL0pGUM68CLdUwOhsuz9jrD\nADfcq+EHTkeSm1tRfg+5QtFa4PgsUd1tA9j3+oO8OS4wuERtXT8tItcS8PjZuyin4U0+G5ec8xRq\nNXig33Ho45rUFp/dzkeNN1A0r9jrBnzIxzHAQZgfdTuGWuttmgbHPe/8AhXQ1iFepoTAzqrCqBln\ndNdMPtSzeK2ZoMaHjCWqZs+s8/+1seQjregjKaPbNxtmkplWus0EExT+udkoO7IXvlQq7BgPYo4r\nRpjeAfQC8Li0QA1OIq++poHELmQg9Sv753ldrgUe7HlrntwA8pnVfa3P2xWCC5ti+tEdtMl2Z3R5\nahgZisYsB8c1LNpju99Cd5thHlHl4q8bD77qMmBldsN89OKNqPHdYrbQUxFuR0cSUly501EUip2r\nJwNftGERUEMKhO82u2cZQzDhz17Ttkor/7NeO+Z+DrmO2e4BlNdtNXxiWIprq5n7njgKw0+Y31Z9\no5bBl4zCMvNHlQ/IuBUEEIcDEP1SH8hlHzzCrOoA3/6P17v4Px9APMiiv33ExsXH8T1i0iteJS07\nzLASBPvauUC9xNjitpan8V2eHxBVPDkLlNHX8+hobBnp5vRMSQcBO0JFm33M2lSRBE9ZNcgYf+g3\nkB2CVDaFyDLLvhVdXW034NGCc2deKjNDfZrSkVEFJH0aDJoEYzxeEnMh9d5rIKx3VYmcYHgw6JGg\nJBhUkNHmCjfh0vCo+hjMCPwH95m3vUFe1wKhOoXsIWyk1QJ+QTR9t+hZTowkYlQprcv5t2gWHJYG\nys6npKLa+KanvsrGVrXB32uysIZliELY0rvCu1lnLfOVG5o6VxHS66qJPHimhiy6XX4IgXd6zZiW\nYO7BOZluVxA1fF+ajFTsjY32A70kD/tRSPQpYwH9EMaoF76kkDLhsIobb2kYNomgtk7M503onnCd\nu64Y7Grs+FvIkcG6rJ/SZUqfoPbCZmvMJtxhS3d9eDphfgzSyg0uEcbc30Scvx3MW/Ka45FcPqWU\nTTJuaFa5sYSLgrtp0/xa2z1ZrvplfUMOfs1Ir4WbJ9S9rWOTG+MOlyxRJVANozxhNnL+p0UxBvIK\nFUnFSYxOeTffvL/9AiuwYKEGlG8TP4W0kgfeL3hMAL5gpcXggAW/2zDLba/syJhMD6Tp62ZpzZTH\nz/IPQv4NIEnBLbQy6BH4d0wGaSLfPyXvaUjY7YQ+ntuC31nihw1bQwaZ+MUWyZRcmiX5r9u7+XdL\nI1L1yZBLfdvFM+nIfXra/bYYxC99jIKFf7pNPlxoLNMW5ArXRg/FY+4oEjkoCU5VQUgZUNAuJNxU\nkjCdWYT/MrC1tV8BTjT8vgZqsUVG+9Q9BiJFhhAhyxYKch4SAtURNyGrLtp0SSnIYJ3B/ZVjzn7I\nxuxZZ2v2AflGdJfcDL+Rr6aLQdbjGj/+0zoSVfLZv4JbXBQwhr85A0tkeg6cGcxR9Vza/zc7+M6g\nJ5ccWZqPWubJGmJvKwm8cnMa+pcVTxa27WsCDyvS0Y68jalHosyqevLvcB3xDPTsn2uHlV+VpQcj\nV0VFxSXFpQmg8i91a+zS4L7xHHbrjcRUly+muThjtgw6ig/wF5IxtSpj5x7igdPnhA36Go4s6ycI\nIiK57NlcBNfiebdpAbi/w5sM+taV1uXqviHauEuFjtQA33Ok8ch86BdmtrhnfMrEJ8rHapBXrVht\nIdcFv0tQUfg2nx+8xWmAW0dbKjOV9EeqQp0I4g9LeZD5GoAP9n3P9uxbxza4GAUXxvg8YQn638cD\npJ08vWFIXQz+R7QyyTo9sX+L/8OhlUe57VaGzoGGHeg2RfhPUXKQ5g4vkHkUQq05nbCCuLIsc/NF\nA9VSgYsetAZd8ab3oI/3nSeVQn9BqI6eeK76MN9q/uGinlJrJwDKg2lAwE4Sx1NtxZUDL5Qng1z2\n+lwVJzNItzXwfBtFu0TCpNDRouYbIY10OgzqrgN8p1Iw4yC4fdfmvvoeJBaWzueEUdTT0lR9CbXg\nnCIcYnStmgLfad7bKNKuZF0N2BdtTyt02DP4LzxwMUX9zaxXo2s/7FBfFcU3FJuvYBvJNxclo8rd\nK99uOpDhoAF68Cp8f3U1xGQs9hcQFsIiZxeJK3ILBP5gp+CyPPneqHwgN07Z3h+9wvOFgwV7PuNs\nihcq9INZE5hivSIUv1J4uqxZxw2YOvj+4XtgILMDsLBUh2/CeiJHDnRXHHXa8xyHN/VEZlvP995w\nphboRlruPD5mR/ocPYK7UdxRiSWJM3aJzUcLRi955umxUm0bw6N0pSJ7JahT+I2XC34PwpktoFJK\ncnszLXBWbxz29fPMUkVIgrJLImaca+mZQRabAzDdtkZVBJfpiL95/WLyAlyEFqHx6pOn9YdqK/x8\nls+aAzMGETkfnoOlM6je/dTzj3l6Qegyttg6hacm7+dwNcr5RLP10+lmLI47KpEZMRH0JtDps/ey\nRtCY/uN6O1UaJdOhdtyZCpou6ZZrao39nAAK3hsYPS++aZgjVAM+j0HZPfDxzqTE4Wp2AHE0vEVb\nsbWOC5JkhFUEsNgxf3CZZek4tylhZBFe2qAPmca7Nr8cX+/fGwJa4zsstW1RSHzzXp+ga7T04RRj\nqKwX8lhMp83DKrFARIncMkCPhC9OchoFv6Gq/qOjB5ENUspxDy4S/IOsNdRpKsjsoA/E6+aiSeQp\n3DWa071ADqC3V/jEDFQxKj++OP+/pINq6Y1craLIugETiEcpuMZtIfeNmTtUQ9bQlnnIHSMgiiLk\nEYO/fwfSTz7trn+YBvKL5vAPEgd8EXnJTQmYglGi3iPtfYZCecyOfq3JykNYoLGzlc8l+lgHht6D\njBryf+zujUdATobQ6vmyUQSCtmPgv044olqWdpLhzoc9ASuMzv1Tf60b+vX3nQLZbSJuYh7SHxUc\nGxaQJbaAUNbtxB873Z2xQaexfwD0XIgmIrV4nTsGA8CKeZGD44WmVGfF2zAEj0Suw90pvxZ6ak52\npnNXRoiYA1GbUbaAPifn9es5nNMox1WMhiiFqkfTt6QT/LPDaI6pctEEKbhZABvzuC+AFV6ApkFQ\n9sEbC67oJqc2L/F5+EIi5bC2E4TuVw5PGllkgLBAmBS9ZJXLt8W/7AZzh2zXOiztarPYrGxcQWQi\n1NqD9kbqMfjq4GgxdfOh6GXp+/8hzguNrB0XOLT57jqu3ukdyPI/38f/tdSR8rVLm9ctklpFxIp1\natcGe6ZzLhkmrAWaEgXu+rkvalDeJJzYMCdssUggP9sbyIBqNm+bu0hs27axwtzO0aLTdEmRy7BX\n02mW+0eM4axPDPBXp7Km1zDETT9OuwhMcrmk9IDiDrbaUj5u9Is6RN5ZNoT9chv4XZJKvLR2ut3e\nQGCvbdUAVHxPLCOslYfGfXiNFdwL9ygx5Xv94ULNBynBX65Yc0v5uokgRUlQFr4KxsdMcxhnJrjd\n5mKOOdcKDyXcYKKk1YrFmxp2Mqa1iRK0gm7BoGrH6dy8ZY4obArr8X7BYzzkf4oUx8I+5e2BLyig\nSCmP33zMkZFpk/Auh1rgfxz/PbMciaPSHZvrsiCsT3mIopE+JgltnrrCcjK7GAdB5hrTS3w3SR1y\nGBavVYxjiEqnr8WlVGP5HbH08fIsOBlMX7LO5sciII0cGlRpn364mCbdp91BslmVrQoxcPaj+TC9\nO0MZi9C8aOZsUVk7GGBEye2EQ6zuEpA0PE6X2sUd4HqfaTrtQg1EivraNouAMLztKnLgN7pU/ETf\nK4iMYGGJzip/SjpXL4XIr62c0IMMYJzIXHBaTyrZ4idSxkM6S6Q/VUPOjO00HKdaRqOIH4Fl7siD\nQGdPpuIRj0b31W/7wIswcFZmCuzoZQGgj7b7P4nLZ1ugw4MHnHQ0p0zWM+A+R01iDJDTBdfEPSsz\ntVdGAoTuJ+O5nYpHMc+IAOA29tvUF0hLHKvwz719ElO2436olcY+xVc88CWad1ptcp6aodqcFyUM\nOlHeSnAgLnQRB4lEfJKprHEnN1TrjL67oHO/cABupwcFGBhTJebJn1u/nizRAVf+CKSUryUX1plf\nq1Wg9A52pO4nv4UPs5j2/i4PgDiSZY8dZu2YgE043PYJ5dEjNrmyvjaWkjFwtziqqKJ/zAwzxSfY\nFx5VOVen0XsXcoLpFHKH06Nbml4lnpDAxCdCAQlBhJagIUqVZUEIMzzBgaOUj7Y0E/Sx/MU06AAm\nb+hjKhJ4ht+9FDe3q31ngEpHms3C2CB73sGjLP85VrkgocaNNOGwWb85+dtp6SbR1oOXKGSgDIuW\nWa9nFDdb80zA/9MYuiTLZB0pGf2ysznBH4gVaJ86M27pJbE/oidnAlTQUPvFB38TOYQNTSnCNbmC\nBY/7Vz2hDC+A4DHGgWSJ/wWGblIidbsZpgHg1Xo8ekbgWacICP4eJRnFY0h99QUPrb9rr7nSKoVD\n4fgt/CUrqX9nvnFnEEI8eiWD+oHVrQKGRK6TnOP/839TpPTKpwfa5Qlp8j3ABCliKMAkPP6HOX+K\ndwjGgNzWtsIMFH+5fIx94smDLYyUxaUiQLsy44s+y54eVCf5XtKV7oMkEfvPoBAXlmhHKys2EraD\nKquLZQqsoRYc87pUW7KZ+/FGw76fQKeccRJfucdYfj2hHBcIaBuJUIPKrC592N7/WwEBhSd8nLa1\nLZKRMwzDGxXGYlmDMwf56Zf6OgqrCqSI/SnvV5mzligO5Au0AT5y8UGRR9x2hTLAohR3HhVudEXO\nowk0UJg8YDcoxxu0VpwoNbMLIcaEY1pemBsAdLqJhGMTRnneNxKrTtSgUwFN30HpP1fHg8FLhkHd\nFEhXXm6zT2mMHNhNgq8nbsHlIZj6lPdOCqJht4xkSQhmq+b4kwFjsVIOsR+y6Mo+C1vtZM89MyCi\n6SWt8fabXIQhJg+XGRqdh6vVWl5/YYso5T332zDvVQTlJAIu30bYPbZTre/xqhs/eG5/01Gy6nQd\nsONvdiK5TjgFj1gAUliaaUHi3VsgkrNExifz+rXAoecbj8lpEh36t3rEyvXjjGsAl6nV1UgQiCOU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mjmT3stzC/Xv3U+2KUtVN3IyoZysXfApjzYPxRGoY14wxVxml3cjWkid8wTZt/\nqKiZ8+DNGhOWsKqtYFfzvK3ApRuFrMQI4nmfP0ioaEsTGAw0TGjMc/edUC/KrxwpP9WbWlpcR1Mn\nyRmHmO1G980fLf1P/q5GKog5mVjHFI3YGEOry1qcHAJR2dzO40KJ0/5N3/Pxa7i6wNIJh/mHzFZ+\n31kRMiX98q/i5AnwSm6CIHRH2WptfuJJu8bOdHyEc2X/ZykVW5x17fso5tTlUjx5p+HR96FFUaBH\nlCZQUHaHREVDgLoo37xNLUuVkMHZqp9r/Bd63iatA1vtI53HEnJpU6AsMLIsCdkY+Lf82Feavy1/\nXEAxqjo7H1QoA9YuFHqbS5WP7hI7NfNQMDjoqprgcz9/UB7xC5WYr8rq2d5mgeAbnstt5tE7sQm6\nQgLlHockY4CJK8Xvmv4d4SblYXDAds1reKTgyhuI4ZtI4IEsIdiA6/FCJ2Vtw+GFFB0zIWutZ9Qg\nvRS3DxbGOPG7mDhBr7DndSkrx0aocMGbybimWSBSg54OO8poGqinGYfYKzIcnpmV8De9rNUYTd70\nICpozYFwIfHD6uW/tcf8vX5K9TD61i5pXIBimaenR5BI2PMYIhZxYqmWN5m2C4lpq7eUVSFU6cJU\nDopA56H0YzS1Yghkaz6ccapw4+IWSfmbW+U+xxGGT3wNd/C0LkyFKJzdCEZLxeZWC2Om6YAKNHn+\niFQ0gxa5wWQPwuJ8ZhYyqSk/q1Ta/GqqRzNbWLlZC4xztgz3JY1yx0g4gGXDKlO705YMD2H1sVzh\ny8FE+koC6h6l4i41cL/DFsmJm5Jqj52bd3iigktOLK6QtleXtA6WLojTYOnJOguFYPtthxaSvmGm\nqQTuLmCdlOWgPxQizNJRMRBTiuN87BktKycizvXRwigxNRv5V2btiXkJPtyPyqkLA4WN6rCMZBko\niXN3m7e9ovTge7aNZ42IWrAY75oe3jrfzduFMjJB7BHwVaV1dNpZqNe+ZP4gzGhO6yKU6gUhhLjo\nhuML+408orbEV4f3IS8O1PfQ+c9afO72/Ivqt12Iq1YNG3EKdwt+NulV+j6oevJWc1U/vV8MrQa0\nbeVkn5LMWMAilgmbX61R6wISQo0NfBGdFL7yL76BwJ5wauMZ3beZYu5smvlVxpEwVhQ8fFxH5Xpo\noihRZCSnp0L/BG8e+f6/sZJ3g939OWCjOd7v+b1g7lOXhRH12gLTb/5yvbYNu6R73tarKDzA+EDC\nV6Cjc0uuB1aWJB/N+OrNOcVXKhZcotiTMF4vDqfRNuqt4Lr8gjOQdRbrQEveoS5Z3dGPAUi07lqg\nqVZaKQNTSVTGNdFooKDV6jxrbpDI7VfHYQeRlcfaGQ1FG1NFjzlHBtwZAFGM65hXUyuLRvTsfmyJ\nKoaS6UFC1MuuQS/l45/VFm1tfQmlNWunhV0kpPrB8jg4HzKBk9f2BfqoHchtOGcUKTenprkzbPfn\nw4lemz9G4I8Lj5ly28uFVHheaCmKS4+8HGNam+xtZvyfd5dpBY8AcoNMtHr6i4UmfWaURIdijXdH\n4Bmll6uW4Pbk+DGTBh4mPSh2on/JXHVKOI+tXmcYauiEje985N91S+0Na3tbw+coqe0WLnAcRjrm\nq0HRhBFaPvHkoNwuQKN20uBjwavtz72na95RG+VD89klPSBmoG9U09U91P6sJ18GtlDxXCP0UAvS\nYwS5AWhwvu1ZBenlPuvRWL5SCxKd60mnVbKgePL10ztCgNJWKHL/tYG5erl6R7VpWRMeuAsivG4L\nvlZh1VMUk7WcEFtlQ8ewoghZgp/iUiIGdB8UYFsMC2n0jF2KlbD0qxkuacheyV42MhjTNrWOGJpP\nb8cLqovTnWaUaEQR4ox7qhg+i7lW7pFMSIP9k6dZSVrywanuiKxyZEM8txnRmifM5BWdVlFe7o4Q\n6LDdZw4TPzfPC/79pncGr4kcfXBeItIkCz2Kb37YPXMbPvCbBJ3buirX4xlN4U9Fzi5U0OI8rI/m\nxEaubhXYIo1C1wVEbMmhjjAYqm9mdtqwtK34nKt6UA8yzfBAKUcRS9C7ComgLKAnsqqYmQ6+d9du\nQEqBOA+dGyP5ei6S8XQuTmoeHBEzJtkaDcSReujBlwUYKT5jEDk0nET2T3W05RN8O+I1iuCL2zEk\nCBa9XojaCW7WnyD9fHIfIlVP3k5fyrMDshYPSJRoF+L3za8tcsFxoTB29Q6BjKAxZ/R2U7piuOIo\n3MRAXcIwBS55HqoJGM2SsAP+FtMEdbi9rvWNynjnYLT3VWrn9y4dpa1PzuBknAAIADZ1iJy8w45l\nKMoZndthreWqtx5WJ/NDeCbjKlRUXo+VcTOw5wfPGjtROIJrk+a0pBEvk9IgkLPXS67zcTg3SmX6\nqQGKLp8Q4wEM9wWWnL2h6O0wifvd8KNCNPziDdUS1b31LePR/mZo4s8QhVTskrjHFAb4QUbPl7a6\nHLudISZ7yV3Gmp6lxCIVCJYIiPkLiVfwQRSQViwIUWt6BCc960d/MqoOz0fwpsTkdjYr+EqA4FGJ\nwxJLPlTgl2lMVKdWumgkU6nREoX2fmCnx53Jl2LcDzdxTiKv4g72G/QzytkzP/3csANiNniXJKyb\nyPEYM+lewTjlwyBrvA1Hseq0rwEyuZIohPauQrtMD/CqgPghUCPc1zEUWqtbD7Cs6Wa9Q6i9cZe6\noygam6u4DqOHve4zENyA4vn6BeFcxUULrbhaf00LyIK8JhVfO3PgfxROzcPGkUTDn9lNMcgSYFw1\nF5h0O+k4KTZAuh5WmzhA07pUadrHIEWS84zpb597LkMmlP/Ir2b5DSd3a9WrRzXtffoW6wj+dqC7\npakKeVaDaFLsKew4NQn/5Gv2SSsl4XFUnLgN38g3e2L47gMZVmWlB+Y2pxNwsAyXV5zrfZ66+6NO\n/atnQFy39BdJa/QlM1kXvILZzqUOXKGZVYZLaTWJEug9PUV3sxznlaY+cyInU/Zyp4GnlbQ0XVJM\njjTgTXNLU2xwchHYZ2fBegrJgvIFGdryBZ0iiPdHvP0oKTrobiiLLzbV6OGhFV17NAM1UtiiGvmX\nCecPeJZhMWSNd1sR0zXBMsmK0TzQz9wCoe+6xVsyVVjA7V2FOPwHS/UUbVQY48xEuz3BqvoRTDza\n/Upe/JHbXSk9IhwLJhuQT51Ra6cPMWmXfgxXBAUVwMzzMx5nf38uLxEbI8HuxHJNoAr5GGRdDbDM\nvIaZdGD58IBnjKY6oHp0HRYu4WKaLDRblLUdGdvRRYTa8gDWhSNjXPohCsckVTdJP+6e2e4QOj4j\nERJFaK63X5h0QsmZOgpBr0rJwPTHnVY6GB3YKBw354eubQ9K7LofK66j6q3zT4Guf8RJUbdEAwPX\nO76Nk2K/YZetp9kO7l+c5cAIr8TwXPfl9w6+CZ8CwysJcd4GCwCkfBAE6qXqEVKayXnkzL+/gi9q\nYhodZUcg9N6TE/MQblA4jb3J2ttB1IdT6RQqaipYfiglppdRbRW1Qij7hpryOT2LWAgda1QDnOCw\nN/aRmOHe3cYkOP7spl87Ts3hk7E2Ax/UCeVxagIHpfy+FrsHZ4qiX+k649T/cfEl5rBbvmxA/xiL\nCwG9iyKqxglcf46ESxutKiDbBbgTxm51oe53JUdUJ80WTQ9/VQIlCKHVZPeWam1by0CZhhQ+FHPz\niRM7iAkCLl0ad6jbmsTBDB4Yo3j9GzlRn4OwfvkX+1X6Br/jpb7Ods5R9sYdCU8iirwHrrDeyl4P\n5Oa3TjRfEeRc/j9P7DyMx3ksTLodItG9x/vZWgOy4iFOa215lI7+X25rZS1Ummp/5i+Xpg/2bqL1\nYc6h7fbQjdpHUXjn4QUz0LYvmc+BNdDxx7TgSkeXOeHhdOTNPZBaDLDk2cy+lw8H7HLME+RVBt1k\nsXgcUBHjvvnpcteXo3EY/4mNbR/ZqLeXimXlWhSbjhCGYDzmqa5rgtz3n/CYymQhxCskPAQGw+sz\nezc1Bd1Gs8eiRp5AYUfgRpr4jbtwjt6z++6Vu8p97biVpBs1ExN2/VFrFqgpOJw9uA6QDmVZnx8t\ntsVnG09ksxL5q7LXryPT74zfhepy7+7aTH5YUpDpb2waeTIFvBdg8gmxXZB2ZJNSvEFEPglZ4KhP\ns5Wo15NcuLVfQySWiiEeFOZVqadoOuNZDghUEifrUf+33tFg6SeVx+zBDJbH89YDSGPONwYA8KZ1\nllfpAVGLBseobFKvocGgdqQf5YsUQQL2aNanPQqWDHJHr30u4IJBVKuluk8tjx90eD5z0fjoCqq3\nJds3DQnYjrQ7BU2xCixiaN26VICrnw47sIinfFcVXPidugt7ZC/KdJ/aQIVQbkrgDLjDxprUS7W1\nFffseESv5PsMOXQPCsFvlKPUCAAM4JKznpl/d5fx73jhcyMXizSXCoL3+8p/2BFB2u1ZYbisTH6V\nHLzAnIYsfS7eDvpwedtN7UZnmo/srjqJdMDTnCXrvGjHEr7252l6Ipuygr6C+WLPMQU9rrfvIwyN\n7t6vCh04Uqaszzc5CY9Aglhmwt/2Y5fx9JkGZumJynrdGXP33p2621iPJ4AevXZ3fdpNsCsmXnzc\n03cELWhMybwOw1YYoFbfYaz0s7PGleQIeLnk/884jAZTBzjHWSoLCwehSZqGTEAap+F/qiwHr9if\nuKfdQfIf1sOFlHlFnmEytGa24c0rloKQYqZPkuEVY7dS+SDs3W/Bcfs8x0goY2jaXFj4ZMP5UuTc\nyYDHI66HFcvlFknDksj2QlDgRfqZvhK4nKn/ov1YLKpHRhjo71lyHjJm2VbSQ+0OKQv8nqczLIpC\n2mynrP+VJILPijymLq5vCPGo6QllgLdqvuNKBIsJJrlMhIMyMmnRNJvVS+sTiwwsxinybxQicOf4\n34R6e7oY72ItEWWzrwJMtmMMcQrNBoRVgZsDnDu3B/iLN9B445+Ia/2xI8tg4h4bWVtfUrPF/GHF\nCCMcBaai/7iqersKU25P9YqCrW5gzK4yd6hHRVmP/GReTSC8etOcS/dQ+iH7YAw6g+VqwGCE9NNq\nrDHzSFNHzcuTFPuPTnjdDyBuk8tgZ2P8L+upWmAB8WRT08N0FYWxRVHTgdWwIb++kpR4oah3SMVh\ncMdDNeDMRXWOPYx+eoBFG4TdDky/+Rpt3Y3t+kXs5rBtuM3mN6lO/N62N0YIWBy9PPROt6ABLhjn\nkTSPxHFYPlq+2tW7Yq6PpB3gOJgIpw6Jd2FVY/nnHFVGLeti1SuPxoqA/zB+RqAZ1ugF1/HuD/no\nlOzP6btVSLptufMfKGXQlqJurAbPNswzU1SgOzKKgJWsBc8A1dZhUmmODZr7QJWHHjXRe7yJioTB\nSe+1t1P79UExlkY2Av53wBpm/Qf4fP4wQc1SW3DW0IMbQtjt9uv9/X9fGV6/G4GCcNq3idyucymc\n5DsqZ30iU7nUPo5TDk2xTfYTo5J6KDFbWg68PBTUjc9YU+xUqFwxcpfCVXhHxosuzfUSnP6d8DrK\n3sQNP4khBnas9LtuKIEewVH1iv2IiKUdT79XbsL/vFcNBq0+Sqvvg8Mk/IozOebCZTqLA+pRh8j1\nPO0dg1EYBx38k9kKMWWaaucDeaXpyGKEurCt+rNNj6O3iZ4CRZX9o1/noytgel7upuLBzZqGwGps\n73AtMGLpnD77WEcHmk7vCb/9ZIQ/1JqILIS7tWQrpz13TnS0vYnHyN54RndRSVrH3tV5/OmRT8Vr\n86wb6pLSlRI3+LytODQtXr5Pjm9zRxy6ohZ3KULiJ++p02B77O1XtFtNs3jRNxHwmT1DpOf+e3YF\n7zwucJ1nuZyIc7dAzGodikj09oxWDfGZLpGvUv8slbHALDP09Q1sZYzbZb1WMxARlYmMMbOMv6bp\nqXEGb6OxN9Z+GzBYi3Txjse2FDv2HMAimBoCXDRXlk+yVpwUiCn5LTOOrLgekPXApsjOz7wN1iAF\nuPCOno030qg47WpIfuuAkwTBNanyjM9t9kGvHBUbYvNGJkbeRm8WiEhVGVnfSDbFg1e8sBlL0Lu3\naMpK5PBpegs+vk8K2IkOGYvR5Aow1ZeA5q1rcMpEdIMR3mvYVfmtKdsviHZ0E9byAXZKlxdLV500\nemm5GQ0btI6qUDeat0/afCtAal+KQNfrpHPt/BKEshvW65onuKtkGdVhgINJh2YjRt6jDRwNZQy0\nt2/zk33lRdcQQQ8LBhOyDN4ulcQycDTY8OirqCVBDoNZ+9yHallJ2KKSJ36/U8NF0hahr7y5qtSM\nA/CkX1Sq/WW9AUQghL6/flbo6xyPz6Bk2CrrAkVR1m8WMsMYMTJzDzfobDkq/uOLuUcYSHS8GNM6\nIdJqSHQHu56KgPK0O/DnWxNXJkyeBTmFrEEAeToW3FoLlXfLwtvWmC06ciSqRnbm4gQimtKLA186\n3MaT356eSiGNv5qN+OQ8jv9hOKg17JmP9W2QWQxotOSiN3CpHK96mnBgBkpBqeksHSwkZ0Ym0Qlr\nWv4lGLAVFUI/rN/rGeRGjup/z4iwy542LcR9kEYZOCDY7F+46FcaQVcgrEM3BbZM1pZ7vMLZbBAB\nNIp2+fxvCHdPb2MYCkQJEi/lNoxzKSXQtUF/XliVdGDd/gJwms8Xkb0HYbyyJaWmfe/7DA0SWmmI\n5fHk2ePB/BvngIkwjKN6KMMHlozyCxLMBeUviR479mhHY3qV5gjKRE18cK3t6WtqD1l/r8fKmf2w\nmzxkLYc44rJqGUZqz2o47L0QXKUl4KpIGJ/PgoMPvA1kf0RdRqeBduHyjVFsKxHnVpN5TcWOPpEw\nsnzFSf8uh2B3xmR8tN3FtBy76kvQdN+6jOgMRDMtqYF7sGVg9vWPkeNNYzWk3rNC82l1Zzzx1ztQ\nJPblX9T7Eopb8dQclIpQtlVlyIvKm//abXhCgGVhBiQO4HX0Mien3FDZ990Z+ACbN0ccUL4Q1a8i\nxBtv+PWgZCeEA7utiTzOAPee3+34gAm6naicmXjXFCr2YvuZ5nD8J4hTINSaASRF8YaSrvYywwTy\n0iiBeMiahZnjX6Ra2SrDx7v34srF6/hoMCA8DyH1mFmdEUrCRgE4t6Hi1YVAINEphDeCGVVAVZ2N\nPykajTZihGf35IIRqjlR4U376Y0tBRNDAGp0Q6kPtvejvKlrZKN4G7r1lJAyP09bE7KDPRmbs/fs\nNyVC8RFydYUivRE6veitQTKDOMDm6JNj7qAaWp77cujnVGbn64Bd4xm7WZeKIKIm4aYSnUwJl5hL\nD+LcQnpAu6AAfc5YHgN5y5HYw1yEUhRnMl/L5Bjz/LberH5kV5CAMGc35Dn5CCsgW62MH0Klur3t\nqvDQ3OvhGmDL4Y2xOoW4kBC/Rjs4GjGtRYrXT4e2tlpknnpaKlAKV1YKawJ0W5ajt598+Y5C55Xi\nFrK/U1x+yGGVlKNimaW2agOl9VuEcCh6glCflnLynYngd4XXKA2JKIVNlRW01Xgdtfi10B5ipXZS\nZVEoJ/hncNBjVQcHqAeGhnptqMCqfg7CcyShKr61kfcsAc5VLbEphtId0rpP5V0qOrtNJAKxoEaN\n0ppVGEAI9TOF73jTYNy5e79+kav+WYHx6AgbaL192QJxAqG6252UlyKD+TN3wBZoObX12Adr3vX0\nj8zGgO0he4Dx9Cc1zYRKQf+J+yMSyWdmVEp+MKCbgyK6LEYoIp17fcKhZNmAg+ZS36UfkshviFTK\n+POKT3AT1fvcHL8OYw/QdRPMaLWPsOWPzcq4yVgeUMUgiaSnDUCDUB2yCO1vrkhPMwKhlhn0LwuZ\nwfM3h+czZAHuZRighzjAJUXwkEsN1Pgt9F4Ga9v4FpSBRve37ucHHuEn5jrX7b93oBywaPyG4za/\nsKerqFfobeFqou+l5uZHAWu9PB7G/36xCuN+gmjhdwI/5TjKnJGVa/Y4mrJHsK6xloq5ez4C0iUi\nDmzKDqJoGdws5uiPusdI5CZWqgii+tJ8UWOIJHe9wGCyFsM8DcbrnffJ/viThaJpSCiPR0zFv6En\nui3LW356UdHeYjk/6ZLmILb75WrZlIL0kBuk74qo9+iFxkDdId6A9FExjyh5C0dP0BDu7B53lknF\nihlFcZBGxzYFi0FbzdfCEM2K3tcVp8899GthOJgGu1N/qgTjg7ZC/hyW+NBVWOcsA/YI7H3p0zgC\nXErEvovgf4PesV8V5YrcnbNOLDkF2F+Hf+2W32/JFOuPVvcNZ0gw633lx0jeGk6zfpU4S+UqC6Z5\nlv2D7EYFebe8OBLKCmRA2kE6MXcrMBmFn7B6+0q/HxIcCLbSLBhEYooIbwK4lBvBHwt3ZNID9S46\nrlt9jHIYAJJLaDmqvniX1DClRh9zTvsHpSGG3mOKpwD1pbAsE/8AMN715F7VM9sLDloqgirm14c6\n6KaiDL34h1u3UPQcAYa/iUBBFD/omsncOZqodQoWJn1t78iJvCBlDiE/KRD+shi7MBiWR2qJzUV6\nvszTfqHmcpXqEKqJvAXBiNAYngR+GmMYIbTgB1YEwXQCZD0LToUOiwp5anTrAhDmS/ZUfyPA3O6e\nTeDJzu+g6CkNKGT6qnI9zSYRkn59rzdWimTbmd31+E9sE3oldZ7yukJKGm9HcrjmEn5iIHN2ksfy\n/bkuKAzgYebyoHDYTZZ4VZqRJkKaocRo0fbIi3zd65Gp3s5K7YmVN1cvTb30eNMvckNTr5tRJMXB\nQ1bruBwB0ntnrr5x/IGxj/XRZ7/oSwIkJdyNApk2te/birUbUR6UnGc4y4ttNTCDEuqggW3Cbfx9\n9tQdOjLwh43tPYA8H/M++ZwOf3HhfJjQQKysv0lOWY4S7ARJ3OrEoqKqyXAWdXniajcpDVbynsa8\nNsjwPf5WL5HPa+3iczXjARgydFiLFoxXOvEHjL7tJu91ngVLoHuKCc1sVCOdlfYThGi23uWH7vJ0\nYOLKmVWobVhcf5VpB8+yu1Am0dOHkBdHCr3rrgZdInlMue8oop0PLaPmJVMowyGjsverdCv6z6UE\nOqIUWtaPVpiBpHHD9Yw6XYxDCAiGibe+Gl6m/28e8Ym+QSzsogPaSQBf0SelV7KrqzHbId7aPJEq\ngRCDJzmPbD1Avv3QgG3iKsbrPI2KxWvxVP0dALSOEGlaW1luiCFhyVQZMjhvB2qkJbqeiTDhS7h7\n3EUa4i+fV/sjeR56deRJoqqk3M2q5B2q8M8jiW3dXI4Bxnmf1g7J8vrQ+iXPrLgC2JkSbeRZ/eFF\nCnM7HWHG7fLPw+dEcoxCvhyjiLG4nrEVGBWGXhUmx7lCGjGBUwRSXgUKYTNM+tVB/GGQSLqO1BXa\nqonr6lyJ9aQG7gc66GT96wZBQGclYbR4btuwY1dBNSMp+euELOd1xEiLYTm8oFfu+4GyZNtxGaNH\nQPGRCGjL34JDEnum18YLX1sqaLAaI4Vd3oohNrCZpQUGEPboSGGh1OhTL0TcjUaI1kzx5pnFFlQW\num+7966tMQzGB0widT/dnC203OehdRUxF3mVKO3vyZQS/QQL0LhvmTW6F2yZftZZwGor4BAllquC\n557VhXbkeLpl/vbtt0chG5IT/u9C7bdHihJPK9UT4R88nM21DYUK11SdT+pomG5JH2mJc3Io3YzG\nZcfbv8KIZsybNllnnP/EBy1sp1maLL9qN6kF8hDFHfB/Jr2elZJJ01JYHPOQCHNy+UA2Gl5QwPr8\nc9SHuUtr8rz+WAOCvege7emLx4Jt5ytymFbSfrvoRM+ZUxFmqe62SfHTEzg7ml6FYKGwZFzHxAVP\nqClbYQVma1hfPRcOQ2EPNB+IDQvSMtnMgfNCRvCXzR+Q+46QsNEdqQLttQrMkLWYUWQ/PxH/abKm\naMyBEKhbB0uA37pA7d7nNWme6VWCZ7Phlw4sTGZ9usfSAF2iks+dhfHFUczhnkRr5kLs2nN//1Hm\nujL9S2Xh+YR8mZbK/X/DNNxk5vMeM2BEVm1PZoxk2SRTp2R/vYNolwEbwelAj06fIHNm5MpYsL1E\n7ncTpnND/46Rp+9dC46VWjFitJhw6xYQBnAnAUgK5XKJoMd1ULWbXo9Obn6RduRPzN0a789FLdcx\n4OyYK3f61tQF3inIYC1r1HHOGDrI2xRZVZNZNDzADjAcygRu1Sw4WL8VBi/vYsKqVoNERt38KOEl\n9NyG3q3+6TPPg72wauvsj9vXnxr/ERZ9FdkR/nhOatd9PJBBtPaEAMYvPNJ01ByAr1H9v7EusrNo\ndtHZtpRoWhrKsTvw8ChWSzj4E7jptyFhnLEslaw4KGbKc0rKYK/kNZB6DrrEl2aCV7QHsdkX9Bj1\nPKcOWqa37YQlp97WsyhXrowmbd3CistDmVeRnzDx4swr7Q6boEig1BCH+1d5aIEO9ffvu2QbMvti\nAbcrVFpP6sBalPmiLjS15uhWV8KEGw781zQ4mqnoVw3oCKOuwjvvK/9OhNoout6ggrrMMfHFLop/\n7TagcwxVB59eehfgXDHC5RxEwiKlLkX4TdQk3bJgWiNKjaUI0iF5sXdRTcu76owM9bPDeFQ0zvcK\ndUkPtD7AXtk/vFhKjwLRLeB3UTz+YhoVaUH1daPHUMlMEH+eJQESKAxgCeuJAj8GZnyT7+cw0TT7\ncjpaqS0H1C0WUL6EFh9/Re8yGO0a8+1Wp5GoD3ceJ9EingExgibnx1rZ3dLJ8Hmf4F6c97FHtUGj\nWWra/KN5WoCJrdl6TSdm2vPt/3JFImXL3VxVhD1lHg5jk87q0UvPEFJbe56oPyUDYIHorFMXCtkB\nSp0+FG2szkowh6Po7B7p6lTueX4hCfE63q/RjQu0vNkacOGXYHvO/nT/7D6KtFG9OpRZwtuB5emu\nCGXEsehh9FDIFrOpVZN7q6ME4mkpcEBoVM5qdWoVt/3gUeGi7NoO+67+Xub8tmwmHzbP8nOXg3X9\nfNoTD1RXYZyvLZE4fAJJsmUmaxheX5QZ7wY+viDhcuVgAlnxxX0LLauJsgSdLdbbADd1bV5VS5Lr\n7B78FfM0LvFrQA5ay6ZN+k3078VR8KQ77wOOtuiXuls/asxNNLGEZe3j1Oqa8f4PJaCMlo6GC4Fw\nG3ADbVBwDp6yZwFL+jqVJcecF0yGso2WSscQ2vtmwXqV/rt1ntgPMcrqJSBUCsg3n8UAqSqyrJMP\nFl3aW/zxO8e34gRl8Gb+Av7qEDyqQnJbSeqv+bQRtgG85qT9oO8xyqlwpsHqHY98338C2Doe0qWE\nihq/+PAb/4nr9c5kJKMC6aqGRJYAD0fox21bybPmT4ZB2ZffeOrw36ME+hNkiBhNVDEW0j4LFPfC\nYTBRPHdDBONBGboUy+sX0hhLEFqDxD/pZ5nuulAJ1Gnpq5tYOdAVxsaLS4xVsiN6zvxKorSgpp8N\n6MetCHR0J1sVQSDbgLtEnrJ7/7F0wLUSS9jjxyJk3JHSRXyJQkLPrGjNvsgaaZ2+lUq84JavE4TW\n9WVMjvOBSoHbjCPnbFZC8a49DiHvK1W7MjjzSoFWxEqbJf55ZKbmbZgJvRBEMomcR2nX6WZLbKWd\noRt3xjhQXyyiLw7QmCKsylEF4+dhqgHIebhz0y70vdoOeqc0rMJsm2eLHLngRgytaRry7GtPEs5k\nEPzKLb4IzUud4aHQuqMS48KrQWjqCoEMqJC+/cyg0GMCPX8DoZ9NTjThi3KQ0Zm7ccl0zBlw3HJO\n4qeihfn5PUbsuXiimxdpDSOITExdNX2hgIYo6AHvcXqMa/5Srf1HuJLKLN77iqK19L2yGGkfG4cT\nPp+WIn1zd33WLqzGEEGFwucN4QrfZT0Mk0WseahDZbW80vLs1NuEfK2AfMYWc+gVKQjjNjUOEeA9\nEL0nVCajyreQL1X77MQ/Z3f7MKXlMZIKZ9st9Pqja1Wqt63i3HjrSEDh1cr7EQru3+zBo7gAIJNr\n9GzPVfhPzNmlRJyLd29w63i3/hPgjFiRB2yI01ijIow79xNLQev0WpGBJKnLZIkIGQdHfPjySCPp\nLNOOluCTX9RiV7C2yt65IAYwEE3Rmu0QeEMTSJr8M6cwP8mkQHG7TC26sVsjzhaVJ31m5gOTplWS\neyBIdXbYZgIWt1obgM5qbXkjN05FCv5jjW3R13d0x6cAu0lu1EIU8Otrn3d7K7abyyOqc6fFOCWC\nFarr8sTVDJSYHojX+adnx0hjaUrcMBbGBTKORHKWrTFaDAPouT+Wyu7oCi+Hh5VqU+mZe/qB7Kxj\nlgqWgjbbdcxQ8ViVvicBe5q/Ovu9OX/S/BryWWNVpNVVPrNNP7Ud6AruH/fVFpmbyTL55m/dllDf\nEsoSG4IV4Iq8y+AEYbXrUUN6PUiM0B/GGx4FWgf8LDcPntO8P7KQcTV6F6MLG/Me/gsMqJg9cTka\nGebbtdVE3YGk4XTN1vGthwkfPh1Bj6hbaXmcvd1KVqWndHf7ySukioyKHVdLKfaleKZQjgYrFC3+\nk9M5UF8iyFNdxOHcn2vCBKWVc1I2pd6ZMR0eYCpW3Bl+UUc551rT4YjvRrmtgQDJa6pyO3YU8u8d\n4WmETh5BlAaqkEDHrICLy8G5Yep8lSuyYflQRyJlV2xhgVqOUJTgtQij9t35ogixJNN+XdeAvnZN\nYp/xoGGboGv2dQbh1AB6/hISTyoeoxiUiY8Nc+wJ43jxi7Zof2SnRGiGZO+DEU5xvGRXl2Ws30bG\nF6+Am3Fvx6BC8+k+3uh9EM9dWQfSBMnHdb3idchTHaECxrWgQ6YbLbIwFuEO5ZH79Vq0tBc5et4I\nGX9TavQlby9lMDPpsiWQoFMzvCBc3iZ+lZJau9LWocl+f/9BM5rtOdI0HmACQiXtU54IhGtfHCn8\navgoEX6YeYOtrL13mkeqZNMTwp9lDG2/ChB8jfBoeD2759DTTH3o0cL9Sf5OTcuPA3V6/lQNTJTO\nF17UEFBwpnizy/n8XdzKpjU+gDcJsRcp/WGYombRXjSxfOEcYeRGaNBkgmqcV6xbHB9voCeSyNZQ\n3NYbjLsDuHnQ5i0saD+Yo1ryDiGFJoetyr6nXA1l8onA/40QGdAL14rfQV6HmaKHRVYCsF5tQoxH\nG29OdGuI0EVOUfIt+T29zFbaLde+rv8aqiogYctNjvILupJVMCrUy3eB1cYL1r4cE8vDpaIrVw3S\nlXsgoXh2LK7PC3REaCHJDLS9oq0Nxu43MiAuaSZ6DZp0U5rHH4DcUGKGK4LxiKC1fKZB2YXk8CXg\n4JmMulWsBZyVc1Hs2STEooc5NEZRynFPyNx6sPwUKpBlwvxgPIz8ashYeArr7pgtazIlQCV8RsbB\no3WNCfSTrHDscYbNhNGSN15ujTXyZIxf0xmw1NxhW4VE0LbVbU4Q9muynFksh/f+O3sz79eTs2Wk\ncj94qweFDzzDSKfo+fYFxr35zCg/FefHqD9FPNrkArUiafPmFRWLGkm6SWycHTHW2dmOUxqBLDnS\nKOU4i53LrnwJtNlnnNbR9vCnTV3HZkrvTaGD1GJiRzC/es+XDUFHEb7YDM8JUKlRbU33uV+CnXcq\nE5Afnqcfch6xTfp4W24eBeAxeKZEXYdjLxisOYvQ03BbLnt/ao+HyqjiaVos86B9Z8guiTv7Y7vm\nU0QBEPyFWR0ehm2yrjUy2ZOjpN+dN8ptlOpi+8jkgisg6gYT2U8e1S2pPCrAtZwj51rEayRg6gp+\nfZ1+HBHDLTW++YMQshPGSEXZMzn40VO97CNjgrh8ovSvROZzPoujNet0XF4Xl+0pRfUzN08GGTzc\nCDNZWKvs7QQNI0+Jzy3TOqD5OoFWQbRf3ETptGJEjsxTG4xPlNBT393qN4TMLuz9Lu1DCUKN/auR\nkZ2FO6X5bGfE7IJXmo05JK9M+NQ17wS6A/rJrHFTFQG3i3U1xyCqWFjTpJJamaXa8Ap24WYvz6dc\n098Zr90dPEFqCDwe6hxyVvY5RfffPzDqQb5DMiiFBA0+l1lXQ6msvQO0/PjN67FDr+p4RuZxhV6p\nTCZm4lrQ47Q5/Asnv2QX7XT23yACOPXvT5VII5iJx66cZDW8PqcokaLa+pAtVqbgZDPxZD1C4NXw\nAoObbkqulKoJobs7EjZSIpKQqr5GCZ3QjgDDwPruhevdnzONX5uBvI19+JYqusyuR333F376uyvK\nn6F+d/zNdvSAV3gIz9JaPPEhjbKgsUOFhdyDoaXdydwVHrAB1SkIhNzpfNl62QU0h9m1rX0tPNdt\nUnlnjJPMTjVt7hS8vJhfgtk+39dFB37FS3rVDWUD/97MlcR8z6MEGzbLsGSRtQgzQXSzXL4ruX2E\n7F8oaVsrywznJGiEc+2zzA1QekJQuy5dxS2hvHftZoajaCqWhhrACvQAE5HTIr8etonzlt70MhBX\nR4L2Kdszs+cuKe7YCn41vp6yn+jkXCpOzLOekgT30vVB2cScqwhXUnoA4eD5oeMK/VvSG8OomIto\nmaCJiv0wLgJ7kJsprJEeL16mqTkMwmvay2FtiWlIWbKIs9hgg5RqP5ftklAYWiA/4wg9CMMoH2hp\nuZ1nni2cWWGynf2ne0XC1qDqennT2JyNAQtk9Jw0eXHvjVLarN4YgyFvFTr0C5rV9472azo3UE8A\ndbhgNUf94/74joOWhz9K0BX6hu6u9am3nZfHjzT8iT3pq3MtSlLDx/+vqR09j1sBXhBoyiyASoio\nhAQyBIlf137OHYUONIvyzXe1M6PgVDfdvFr6g7VVEpVZDeSgkN1SXdnbZwYBVLOYe3JTzPfiCNmw\nPL+c0DJ8OwN91pieUcftyhX8/4nraUP0jfbmoqYneAn2aizdgj+uYZDayM1DDIqG7HkWgfoTyOux\nFto6L/LvFuzFDe+ipcLHg/txvv/oK16fIF31ETqIDIKRU1LBbQAbPUwEZxC+TEnpkcr6oVT0hwHN\nJuTLW8ZHgsVNC5YQaLbTIU0uVZ2AYfXpD5jXx2DHxpFmqpwAA10PEvjjBwEXurS92XYW6Vlh3vag\nh8071PI4Y8h0dlx5dPI/VyJA5MsaecCPh9Wc3Mu9ju7CmJzmdnouyGW49lVc7T+BFgn8vY84W4Jy\n0EOJqxtbldn/b0RL9qNfkmndlxOOYUGpkoTDXOeKNtd7HyleHoQUnqsrJltt7n1TUWyBkUSvmr2e\nhIco9V0pfGLnQmBrcS8ESf7JoDfid3dd9xhfTYd7x95o4BpLRW9VbAnUv/qzO2Ql4PsXD4elhlqQ\nIX/zvEAslyulqRlaIojF5lfyR5gs5T3XDgy9J3wvtzGMB2e/OdhArVKDlyiGKVBCwObJBltJLdrm\nqQtoqvfdCn+V9EPh8P1tILiKhp/pxpNcMLi4F54Ss1mMT6eOjdsUUk2NgxCMXJ9DCe3Vzm8uyZL7\ngcN4jfAg3E1rqk3m/i6KHng7yyFwHWIWhDG1pdVdgHnmaVWwnYivlzpB/S7eNw4unSB3dd2BlnzG\nRb5PE2fCqQmV6WZPnzyEbQbON8IXydg2GwqhVl7d+KhVvB9u2DtRSUwccaSTmzQitYkii0ktito/\nOZn5ZAWREOagH6xk2jSJtB+raBOlZD/StDmobLXWmpcaSlaEkDEyTAMr+crVbeg3vAGSoSOK9IbG\nhEMMVUnbYc1PtZV+vY21I6ppYt5T/zHwORuaK4UahSEs+tc11E84gYKfibx4zaxbrR6PIWoRhFpx\nfygJGI82fQqpK8rIAfb84Z6eXjnfx8vNe3ePHTI9pkZghZ1vx44M7VPJerWd7U5zd1C45avIo7bJ\n7u6tesU5+cplrvIG+231DuhICa8DH9UF72c/JWk3FiHDqhpde5ScS3IcWx1hhrKBvi5FXoH10veQ\nlHicTS5ZPF03XuljrC096UTByid0LNhm3MEYNMhJHDAg//PphATDzK9kPRVEqWJNnUXtQxCtfaGv\nDDm9ZwguZj9gqtu4FYLLYUIYBSERRP0P3uA20WOHJw+chMy+nL/5NJ5IbO3bDpRrULtw20tfYeXd\nMEZRrVydMWKNjYU3WDHTREgJjguTG/o0uckR8jUjDqND8/aBClo3a38CpFmPcWL6ws4xn7mPX0eQ\ndm04/XpCC8K8rCxBby0gOx53dNfuWePoTZANSnjGGiUI5BxmFdAWSo6va4tcRBNNZMPM97o0kVhv\nEPnfc3/sGE1x3k8/zSHbDc8HaQOXTo9W3rmPsM1cLrN9t27Iox3uo8H8MKqn1YcA0ilt5LAjrSV+\ntUKxL0hO5/r4sVSAigD8X48thLABHsoJPxsvEF8LqbeF6ar28+m3HKCwEkXmuDsb2D9EH9UPETzk\noU7Zlu+cBilAsNow3MhIVGRoQMJ90wjs5tMHHN0coijGoZTA0lcU/s6NGNC2TOBj1w5bSDX8FKiM\nS07TxyW3rw6YTaoFIbD66Rq/NSP/31Z3DELdKtPR9xDQKSDKf8jWDeUMJczhi6nWPBQbN7UQtmrO\nLkeWuAHdvStParHRMDHlyl76hJKPEZy48fg9N9UdnO+Pd1Ald+lem+PCsHHf+OqbXStJyJ7sNQPS\njKJNQgifRKxMJxi0ijJ0y77hsBxInqwKBywtcfVKlXs5gwB5+HzKqctr1bzPf+oUVROtD4s7C8n8\nPRAVBiiazwsrGoCKpXRTQdmcPIWk5o/ljibexkeIJdZGOflQLAG79TkQP4VR589A9TEHqrbDA8Ow\niEvue5OjEfXk8v35rM5k036b2nWDRQjwgH6Ww3B4Lm4ynLAYQGTB96U9XWkAnWLiLp5m8zvFZdDi\nE+meA0JkE6eMo9xpSCwtthR9qC/ZN+oxyhOIxOtsuOB79uBllrVRyxq5F8q9Jv+a7IKcvLMc3+Sk\nZmbgOAgVLYMQnsj7C+GgRoA181qNGBLLADnDESGgJ/3VlMRVMiOvVQ+AWmMuns4aRjO7TJj0T4gj\nOtQxN5mRSOWygf4wDNFbjjzdk9Wrb+YtBxxP67a1DBY73E4f8rq4GAGOc+uA+vYPxN2cpzQMxn67\ntST3yTFSN0HU+TLzADeDsR9fli+VCAO40pjEmfvnmz8uX4ieAh1/bmsrpCB4hddDi4K7Pm6hCPVZ\nlNMu2yUJ2Gv7pSfim/c6uDmTOvuyKRHsEtHBss9V0SHiF7zsCw9jC1Gw1Z3hAWIEE9MWxlQFYCc/\nOJl2e+2sT7p7D6B+NL5udUm7nX8gB74q1PUFWPsGYpD2pu3lCBVsQcSipoVTozPzXTMu9GhiBbtD\nKMVzVgZKLQb85zYLEfk9esGkaaAa/IMlXBYyZ3KgxHNEQVVYLd/28z6Bgq4z92uZ+nUjAQQNhNbd\nihUSeLisI8jS+p0o5SqzysX2BhJTA73Dl1qC80tYYxi+Dgt6Ix5T5JgkBeZt5XKSBj+tWhDWKCDx\n6uUFw/ci6OktwfqL5KZVOMkEwPLWW0W3S4EwFRv/nqulclXjxaiEmI1qy2g3i4xu4ozAzfvuY4PX\n4TNsbHRGXKHnbUq3OX7WWl0FoO0CnTw7uzXYj3goIj+2ppauZVSQt3oGFMco07p5c7AG791rM2wx\n+pZL5s5qBaL9pScdRgmtmuslKlqootc7gQJ5OxR6mvoMhOnphhgyojQnOr+SJEtDMMD5rHlXoSgW\nUJGwt8q/XT7s+tAVwEfFZwcio0IPbQNDOOsdHChnWoWh82tTu2wWSgR7Kg3fahsm6lpYDnkid7j5\nkTGihYKRKRkvpg2Ws63TmPYjpdul3WC+b4ZOhk6v3C1IdjpjOJ5UG4l9tMkYVfoW7y024BquSO5/\nMPPdTM2nWYdjbgO42K4Zxv4zLj2NSkWZm3pkgJP8LOnt+bV9C5AceuFe2YEcYfHP2NnzCbPkW3DX\n7OB2UfViC3Mm7S4KKuGfnRC4dEAlRwcrCwYneuiP6uS0A1MNUvCnPn8WEs3qpVOweX2aJkYS5ur/\nR1bloUhVQUshGkVfjwbVCpNKA1Z9uzEmBMAoQ7XvphL37Gw4A6IF6IP0hE2sLueqpM8yW6YP/n2m\nThOWH112SQ7B6Cl1xkrSYRy2fRhCPLiOb/AIOrOXBfO7Htq4hRh8mLjn9tsBdxQiCauhjPtftHqA\nbnkLa4np5WOkVect6L/DVTK0V5YtCK3SVmMRX5+n/iH5KjTBdbJDG5zE1+cZIZUf1jHOQT1zGeYb\nPcdKviHtuX/dxA/zR96YYgE+6kvpWexwOMkvDnMeZrFWV3YA2Q4yzl1IMz7mxXAYg+xr1XhyQAHh\nbvAoPX1ZX/f/hT0d5tm7H0+hzJGpOMNmOb9uWoxbURr1oTe7Aub9LGHM7MeHGjRy0eeNA4l9a3ZY\nWaNVI8NHq1/gTMRD2P454oSx+FPyBOny6Sx3+WAXKWV4raTpFUBs/OkARVapcvZtqOP0JQyWm7PT\nCLXQurpYYnK+M5sJwh9q8N5Ymi5B7RVWKXSw3bTt5UpCMFF8w3wqLBnB20ai9FBNCmCWLZmqK1BW\nOT5Z9SWGsFad4wD/ykn7EphW/XOoLWY4gWTRReb8kUiyK4uYq3GdyedGWQMQubbwsw4Yf9XLQOCA\nveyvPmR0nXWIDyie/P517DyAPPR3QSsQaXWL6OwedlZe9/pJZvpyVuCkMvohDO0OiZBnKhw8c6g7\nQDxVJpr+PzuscPWWNvWsRleF9CtP6o3lVCPYofb5eni3/gew6UuMOOPdq96vjfol+ipMOitig/EK\n5KSSJc4ignVV1rpPdS8jKt1uRzdiIG04lIgKV/iTrGxulwFTYWn0YXZ70j00M7akJBpgtHYtEwg7\ntuFwF87SDt98jOPD/WHKwoeleWTKwDzN8dUG6rIIjciM7ttKAupuKB8zcngy2+VEd8SJsoOuiVXv\nI1jEkJzWfyF9h+BgpXXoFGfSUjm4PqBwqBTsya3TbfnxMusFwVAmhcgkODyoaBE2aPevUBLTPEyg\noXiZdFn96TTFBTSKxfbvfoWmBfJLQG+IUMH6XUArLaDvPsOewnpCrh+xOPs2VUJvRJlbOoQA8hhc\nBYFw9C/vaE8JPImPCF8Mcml3atuzrH8J+M55leKZ+Ahyde17lDJYmLaTtLVQgqkyaZyHgYJabqrL\nfvxMvqW5F5ysEsk4uLDBFDd26mKkWfaYPU1SQDCVe5TX6ZCrMoOF7QT3xo/dGRKOrgxhF80rEBSA\npbHEX09kRVpK/s7dJePfIDBOH4wslJSyr+cpQWARs1LDsRdJqfBnbx5MEQ4E2qk0F1V6P0Uu3APK\nPs8KsBhcdUXgUqbGbsEQmLHNmMsW9PItMgYMqBKVjCWjmnu7XFM+2WPGuA22GFgbq/HHjTvb4+a/\nhNHFvP4EGDou4Pq063a7EtIFFh0VzxeE8It65f8GizD4Z/YaE5NBdVql7NOdDECr3l5vqCI3HnNC\nrd00HANISl5oyA2MuYTQR+GQaXrKUzZ0cDbvQZ7P2epot1a+MCmRzUKtgRQlP3GEAOvl/z6jyNGl\n0i9gClFCTubmketbUNA8oLzc5tOCpMdeyfZX7wq1Mj84m63g4WECc1S400lGBZhiUvaRIgsEnvQo\n0/oWeneHemIMitJgnp4Mf5PvMfKmyud8ED+o05VrGt2n1P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protect end_protected\n", "num_lines": 1219}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\ngazeSTBrENHvbt5mZLx18dRtoyW+Km4t51uVxxH7ZGNnmTTcoKqZyFpOrZ3w8kS9aFoiQlh5unYf\nVMD36zgB+w==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nJaIcYFxN5pqUbzepnqrpmFHdFIYWDYoimv/QCWvvIMmet78lyyCu7OmAbUWaZA7w0zL3MGnfxCUN\nn3vQGmg/2D1qvx/q2zy23sfhZfE87aSbXcNL67XF+GYu6OLKGGPH8rnW6exQAoemSF54SZgfsVR+\nZQSjSgAEtaKfNJS48WA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfa+581mCG4lxTJxvsYAMI+Y0/3DEJVi5IASCLU/HkCRmXkai01uuifj6HPVqiueReLeiWI0bzNp5\nJVlbpO/kKqg9MkQMgg1uBw2FFsg7gfVjpDJV9TVBp9Tm4YsSrWm6yWxzb6uMaHsxRa5Y+E4WUKp7\nkFXmUM1qfaMPGyGNdQg20KAvKFwwN0302/mi6GDcLvLNvvne93tcew0yQIxg/gqJlcURIlak/g5o\ntVj030iWkuj/kKp5guYfq3gEFKVEr4SV1BC/f5KX961SkhTxXGKLNLPd//Gm7akdx9a4SnpGY1Jj\ndKETnZJbnXtrvqcZUh2N1o7nl+YTs0mjObgM4A==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nQPlIuDrSSApp/O5dvtKOql3r2+lVEipJtAA3M9T5a18Cd2E2LeOe6u54LQRqvqSgFUElg4Mk3hH/\nGPHlO6wLGkc68a2QHrQWBA8YylrYUj+OZbum9kUQm5R3TPU5Wchw/mhpqWpgPlWvyK/cO9FxrB5n\nHD5ZuDk7iJeShjEmKewIRdMZqkkvQahMZk1eJ8aT2jahULqIomSMODM8v16Cxv6S3q0ohUtT2DVH\nwOkY6nsqo58T1MDDOffgorFUWVqkQwGQ/maDu/KENCo/JCJZOAmODbmBfBAsXvg7bqGZKB9VPp6h\nTMfEboGK0PjL8yhECxqeqwtqHk+eixHOqSANVQ==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nb4dHNcYwRRv3ODYilIe7aZan8VP5sGFpEcM4Sk9B84EsHlTRadyHodV0BfhfsPQB7kezG88HW5h6\nWNkuMny+KpZj54uRmnCQmrVIyZTZC+1+fpR1i46q7pc1ZFH0ByfdNqY/66Ew72bJ3bqt98VUJ+b1\nKDNSnYmqrLKj6TtcYAc=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUFVtDvwzUgfeTJK5RQPCu5bEQXOVNdg/Ctt3LMq1WwNKEczcihJ2sl86P3NdRo0ERI8ueQtux6aa\neHgbxrha+qncx9ha9CjfRUqPzzsOn3Y7i1ixq84ynt9jVyhbj9UUv8UyPbi4K5iayWqESAXrtTyL\n4izB0qPIWl4//8zsVriy5QoAxHYuCOVTFT74KhP0GfBhGq8gl2pE4gyETTs/8CEabnJ3ERkaoy22\nqOEPUjVTsxS8vgRq8tS716SKeECQKpsy4XCSTfx1d1knluz73QztnOOUXoIisTy9nHoSAbC1cRDx\n3ja7kCl2MkDQsfmBWkq0ozzVuY4qo/oIb33DVw==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nYC06/kx9685ntAX7i3acgvLk/EwgC2VW4WVhE+P9S0QST/y6VSJ0oBWMmzsdOs5O1+nblcA3DkpX\niLfXgmvlzh61Du6yn0zIyDDTLrMYWINvRbXV5FG9pLM3G/U+6fTbBV97iUYMHPWk0A2DdkXIWMP3\nmcLuMBQc2y0dm038tnqa7fuMeTcvxPhQ4wTWwHXvp54ejwq4bTAhNgyJeExmEzOvR+zWXm2VgpLp\nqcMFWAA6nlUIG5ZF4M15/u9UyutQPOLlX5+QPwfoMVi/kyC+JK5AUrviJ1QU+rzwvU3tw3rXqAgE\nsMTi8fHZ/Nt42HIXty0cXb5zEQDuP6pPBNW6XA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nHg7KeQWoQfRjpmFIAWAFbtestpXMcHBDYTZuLUSbL+kKuRGBZWT+FXknqinVcx0pJ+q5acUTBtyX\n7dcJkS4qdpYpoaBETZeL/wcOfYFz/CcO2z0+LWoGRDW3DzXn1oRWWZyJwgJkigyMIHPH5qxsjDO6\nJPKj81fkKJMHi/vC0LbmZMiKSmWL7sQNeQyH9Dn6VLxtXovGL9yVh0SoMlG0/v81wA1TX/bXmqKJ\neUvzBU070O5AHkn3Z9WRSK5S2L7x/k+ltWDFho5jtXYcevcbA/14blQqT6/9PetAyFmzvbIS+6Sy\ncJ54zu+VswtKtSOWyzlOnfx1Jgt9q/yLpCG10A==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nn/U5obQaKe7e57D8Mwxo0WeDlQ4fxz4sWCrMViskbh2tk4bDpeUf1ENBUputMkID5xX5gqlPeFYH\n/lod/5hBiFEecXymoK17ADl/jmNo1MjfVQ/nqN6xaJWL8VqmPoJ2XUvVt/nh5gTeI6QOH0BkigMy\npLFieK53VJ/5XRJXmLUeyAKMuQYF3FZPQdvCn1NDG/xTrxv61UqQKbL35Q6DuG8ZqHIJKSJFVln1\nchCHgEOHDKo7nJ9MCjYRgwBWPGvr+w4IgHNPDhatfWTGz3wjSXmjYynT7/3ZWqR/d7FCLN+lZ/ht\nr87GH/juUmy47PmZd6QhKuuc19/j3eDrwcHg8g==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25472)\n`pragma protect data_block\nrVD/wL4DHCsEfzFEf1VoQTKecFocJw604Tk0NgO7M3ODm6t/6/biD0QPzz/Fzy1UxKBEqQ8Nxpt0\nkd5dp5nyCwOVRYlAXNcBHWyWuF3ImZ0fp1y2c4napTVULuw+XU5nSbEmfo3EFsLjHWHYarc33XNE\neccwGpgfFccdUa90fp+q6imfJMIuCWHWowLNMDGdb8ZqNKZUIE8ob6W2adzfUxW6BcwKDMhYtONy\nphGaaPcir/7ub5AXgPuxZ+H/dTq9wgn1aTqOJAp1ucnPzVq3IUtg1OC2yU2vi0qMrGvEVqZa5al3\nShGeBdw/lrrv+XpB0FfkT2KARuuSvzee9a4oDMMvB9rD6SluK40ECZ1+yy9NV8VPy1Z2E7wjjpHJ\nomuIJmTDG6P4NMgl9qjKSn4GSHvEJtg8Hs/pMVAdAds6SMK+O9p7rBsB9TJ+Jfe+EKBicHLzhqUf\nYcNZCfyCtkGAWU7HcdbTu9BHbBM7GuhixBjPG1gZBzSE0WtB6MGt0YXj5LC9B2B4gUc+LuNxNcc9\nUKE7AQ6OnNorwxgTIT1j4f2lTdDpN7naMjcc0dFrzhwLEt7EYhpH25Cb1lTtbt3ny3KVcWNrvcLk\nv09yJ3wThnjJnQl+GUiERUgWu8ROGl8TiZbUBs5yecOS/BsLolr6ykQh3uUot6ZrpLggo7e2zZy4\n3svfbA7sVv+IfBOnba21zodL6jR5Io/8RZ9dAtTSxEkwNKn6woPbXr0vzkNOcXmNshPgXMNfn7kP\nhh71P3gVjrM1Z4XR2k5FHBKIFP7xvG46B9zLPPSpe9cKzJ4DSqgt0aNr031h/E4RKIrUZmmfW0JP\nOP5eFKLhkwM5x+n5EaEHSfUgoGX++y4UkfnBJWjFbVIWdkTMzBCFia7/hFiP4k87QX08uk84BfEf\nsgKGgULddxVYXIDV7mrWaO9Cy6yLEYGh6+7ZOBVM7Zy6cqp9LP7Kc0FPdoy8x9BVG6p/reTiiw1v\nNn3v32uEnt3XP6T+LoaKu/6mrF1npJimdRr7SstYkFy0LoyzKWhUHUz/VQ3iwILTJ0JnGP770FqV\nmvyHmvHBk6MZTTlNhtcVSTTwbM0lw0LvHbExAUCD9Laa09kQXtQstGMFqjckEvN2jqCALunjsEkp\nBQy8rtux02oSB0O2baktMwI571Rh+4HmnparL2+x49hG7tthybchylTgZbFDHKBCvdQBZkzVuo3Q\nj7Y3oKUrm2bmuJSbom1St7TbGFQq8d0b0kTXHL3I2ohjaio0dcvYDfVg+yWz93shEUO3Jy4PUuCC\nxhV2WTmsBi64HHIJgemiKEoZqO3e18N4F8cdUteag8hQdvF+6ZlNnZ/ms6TH575Di4UiksGkL0FR\n3sJm4AQ9V6tp6J/S+c+1flwE89qo+Xsg1/cG+L8vSsQxqyAk/ovRsYwYHiS7Yy4/606czKjJjQLN\n/Od4Z/RzSCDTe9OkRgKnHt5zK3yQjI9keM6uYHLPJND8bpBNdWrqOdAkXjDHjM3I9U6L2JJqeXVK\njIP4ArCrIq1ZHjpvCnFaxB+/+BBdYcUPUm1A5us5vUT7+x9nSm5EoMOVcMVFqrdJ27v3WAGi6+E4\nKO2C+XigT9fiGzmzXlKKtsTeS9pPq+XJ+3ohj5rZIoPhbrKxWjCzmpLqwAJ0gNd1WFfrHgE2LOe/\nH0ryLItmrp8oOSGEdzqkIi3IjIWzEJsFuNK57sg85CLkLBrD/2GAE829x/TXqmIJN9TXeNtV2gKP\nzoR4NFQendQZY0s22N8NsE4Y00GMNZhaQdHbxhimdXjmLk0d7qaq06rLRbHcsoP5Sq1QJlF2K1qR\nCGKoiuDSQoQ4Ys7EOeerLV2n/FRB2yqoN8xeHjway1HTDoAPAet9wYutlxLTBUccGt+zU65u6OaV\ns1H2YlNFqtwE716Dp39IzGvOD4w6IjA/vBYiXj/dOVHbBBfQr0u5i5m07Mu8+ql9fOGoJP2wqBln\neGByChXLhb4uLoe6Bht9vwf98nzSbRmiaYLyALBXHgZKs5L5Udkanozr2NM301M2pzP8QIPa2aQb\n64OnBA4icxCxWwz320VkF/K5BM1ObCLOipn/07v1naPYJx/9aT/ZVupp+QL9cBnPp8LZtldMFsxi\nZojdTH/u0pOw8jx+SH84VqjOEloFoTxTXkAMHKRulU7yj7ZmWlEviMhxT+f63SOqtMW6bd8ndq86\nbFiDcjGNkZC4YUerGzbOM6M+me6Qe5RcwL5VJARilQoyPMlPtvzSwMzUJQyUmabaCEispxMMZ3QX\ndNb4c+W7FDY4fxsytOmuPwhCZS3ytA1vCB92ukP2KVeOien0DKc4mIwjdBllzW9+QN+GNSzRe5LN\n/YyvlmAWUmlNSB8smtrpmB84JVKlWaXOOrpOLxRHtFaYpnmpmXJcNveKAB4LMvGTHJdEDlR6LZ5n\nCgWcU34eHvwxJ0N7D9kxlxL15EDsPFjxeT/vykJmOvcwVPmia0M2nwFaolKZW5cm0pZvf3bzkkBt\nkxFF4vDu3VKJBPN1qqR6ngJ8w5cII2VcSG+TZBxeAg/XH5mW1JuetQkNdLK940Rk85qvx9Z5tYFu\nFKrDM/P9zlRri+ggEpi73JzEUnuwXVzjIe4bn+BCJz+SYBKbr3OlasPo2GXinaCm5ZjGwKSqBbnw\nJNQvpJstSIPLThwNEK3IT7qyWtVrGoCDNiYO4H+x3es6P4VqLqh4r/0++vkRSTM4Ov8V4lO1aK+/\na/Wba1G4sbX+xCKKd66y0Rr3rr77pOo7IC0W9booS++rNRLvt64SbPyun/PqLmZi9rwotRAJRA4k\n7TXOcgtq4Ki6pKRKU7oKP5pQXRmGEVr/qGRqcX/IFcGkvR76WQxcFoASm0Yj/3Xu7bvEHJDX02tK\n4cAJxbC+4JkeI2Yc4e6V27wCtFNv8VAnJEAIJxM8w8Y+uK3Wdth00+HnMr/teyh9PAFI23BCDQ8k\nP3/TGEk+2X9AelM3jnJ1cx55xK7Y/PsWkiPKyUozhHYOyR4SaETBIxAtZ3ttpyHm7JPgipayDsI8\n7gYw9SePFZFjYEZhCtfrBAzTmKhxEJ4BYA2Yq5/1Djk3dqr1Y7XDyyIaLjVim9C05XBvKk/3JjmK\no/4wBHIRPWEui8ORGTOUvziQUj+FDTHjthpKosRq4PYd0gugZGbbhdlEj9IDDCDNxkVM9Xyk3ytf\nEqvvgLtYOih3D2Pq4LqFEqHahfAKS8ugstEsKmEWOeBnP50FSppoksT7QdPuZ9PWlAatvnkJv763\n5BXALS8jMNlPIJvelWHd2qCx6OhCgLmUmRPNd7LCMMydqv2c9uA7voFh6jp9JGAvPu53dzjWz83r\ncFeBSw11OeeiKRsJaiHddsq8L7nMEeMcZshhvcS5y26j+2tp1zr6sVBFicGgokYH1CKTQFIpiTib\nXPL5vAVDlvFDdaC5VNkFNCs76Bou5yWCTAwG2DcN88BLMV7QS7M/iGZSbCw8JV01LKDRqeheVsxP\njaLYS5XkKHDpYtsCzcVvCn6u+nDFLOLhz20cYL4vxwmt1pMKikYG15ONmScVDm5/xQBKe7nWsOKz\nSN1w6zj36KQ/C80gFY0GXtFZkG2CqAMt0M3uDfWx3VKuW6ObJNUb3R0TpZri4OwLbrrUpL5UT8yt\nITdov+Beft7qZpxoMu9KLHhncLx4TJH0gBzyTVfAPg4ljeaBsL7cmVfDmZ1PxNBQWN2/Ms5XhA42\nF3BDbS8YdOU8JUxHPgD9tCaXHqmt/co4uhm7Qtmm+DeDE3O6ljX5zbblXhS0345LHi4MFfhCkb81\nJ5XdY0hze86Ye/grd4KM1+hLV49/08mXyM5oQSWFRPGDY5ivO4n9anEwslLWZ2OKFvXtW0ZjW0tT\nRXEjOIOyE8jyr36AQDMI1LnOl15xPMnKxb/u3VpCatxnNlgTk/jzmFAD36PDOdzIPJr58KDGvKFS\nG18BSpcfrx+8cPWzVMM9M9Xk88D3Mxb+hWAv6UC/efp1x3+Hvihd9zDuubo8/FLjegZC0fa3een9\ndOTgEIsRfcfWWWdtQEDcPKuUn7WhoHt0SvpvO5dTcLaAmCPwcROmaH0teqy1XjMnZYp+sKIWZe7h\naa/hTWP68T4UHeFB8IDD9md4MZDlB/L2ac5XlcVY7UmN/GXG3pc7Gbc6uN0CzGUQcYa/v04G+11h\nT8nRzZQJdZlq0lH1U8k7gR7YudvLKtUfLHu1xmyJshSEKbRWUUdGRnwfJUm+3jGXNSoyoDu4eVa0\nmvh2E9+h8tpc6Hdxbe0/dRAb6sSYseeMuPA07z/+SsPa5oJMBS4zBtxgDX7xBkPmnOmMnJAKzWdI\n2/zXRzhP8OaEODsQLJm6++pIgkkHCqOGr6GeXrHTdMP3idL7UslwV4Lad1r2Y9+61kW7fcGSJ1KP\nG39vh0sAfFWWeb9d5TVQgwz+KIoe74xDJPYPPSkVl5kx3YFKk6vty4CYAB+5DVSd9bLaBnJ4/6l1\nJ76KqFbRsqIPDPWm7OcGTLW7JIMmU/Ofpv4nidkb4LPNVbPMfVS+Z32QG6FXVhOpIqgiKe8BfVka\nxk1jg5/fA0RQ/P5VlZhWUzEHywD2+khTh9xwSLldzJ30El7YZ++yRrsgkGW93hRzZdx/r1YMGGS/\nQBmRuRM3FKMkS0svshNKaNg8DySBg+q2X6Ky9IjA3dznU49GnthwMKhx58ThDxQ+szVA0MrLc0o9\n+rEmk+wXvMx1gpwkFLsJocOcBtoyq3atxI33E/X4g0N1mdf0f7XCxqKCPRyQfjfDQQv222kEzPfK\no/j6pJzL/bq2QCtQD62ViO655dAFs1zzuPSuwrN0eWO5sKLw4bi9ekjxE61AGmPACWDjdfaFWJ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dNrJi4eDjTX7egADR1lPi7IHJnaNzULLyzuO3tY20xdNoS1WZ9Cd6zJ3177q62zFD9IqW5Lu\nqwbBMBn9Srz8L15/PmeO818lgnRA+Obqkway5NlS5ktpFQ+pamj3jyYU+gi61IJh4yOrdmG+0YNr\nYFfUfUywA+Vb0DyVlm6VO+PiHnezjyvHEOcYEa8umdPJ9zJG7DIv0F2B2RqLChYKcamD2eAeDTbH\nfV0/YaWwv1GhQ+Ao8z4mbGlH71ah+UI4VMNU5k94werdUcmCZDFEnscd9SO86QRSF05j+ffi1CCi\nv+ySBxYK9APjuLQjNVrNKkjo3sgO/wtZFTimlVD9eKKZO3oJ+8ImII4d0IrCjHSBC0BNLtUvbme9\nmUJX8cvZmqs02dF+ATX/gcguP3DCUJDAUSvbg94oU5zILWF5KshRjRmpg3/63m3Mqua565kXaXW0\nqSB075zLeZeUTxd874xUJdwhzrCH1TkgjtNBULzc+e1zgGneUDlKpF7+GM3E4g2yPDntlKDSV4tq\nZg/J9yLjn1WZ+g3OXJp3EuqNpixt4tWc7g4zpFD+6PkEQHyikmzegOPhSHkmz2B78XcqHnVlVRT6\nu+h8+OajG4S+2zUQ2+y9ii2QR22KHBEnoriSV0FkkgCt9aEB2YKRRKtPBMXtQpeLYxm70Z3gLSUA\nW29k0A/vnaVEOuEOlY/jqfFKbKb1K4q9aVjX+++COWTPhV5kly9w8ujzb69MbaQWfX7p+PvJCGyF\nTwCS/7D3fUAjuzGmkdfDhZccW80v40olYz+LXAUl7tUuByKyy15G+0BKB5YEi6hGFv6lEz3GSGxe\n8/uUmYAPkJ1u1STOydIjaaYXqD83ZO/ZOVEKqhVutfVl2hSHLzYw6/gUFpFcMwZWXX5eOGNLl2/T\nFF4MzK6u9+0KXGdOAvATi0btUYD6QYMM1f5b1kBWZjJcC1//GBYKhkVUuwduwTVT6aj/2wzH5gz7\nQ8qEmTw4zYRBtJXQgOs/voolLCe3EfZEyqm2uQ/r1PchYuV1+d7io3uQFszexWSuf/eYepqWnq/v\nz2Gz7GegP8v46bRpzZKV61eoGO59seLhOTjvp7L/gdDO8xjlrHxYtOpMrNrj06dtbzUUacmPBceR\nd/N3VW3ovm04JbtMLrbwXdgY4PIFgeC5ldjlU2bnibhXKkE2/MjYx8B5HonlmJU3YGnjfnMzuVhi\nsfVEj1uJaRWKiNw0ZAITwD1bMfhDZShTe0WQqn6LrI1/UH5oUhqovpbWw70bz+ENp+D4TDwsZS0s\nSpmlHT0fP8DbRP044UI6dumqUBh6K1XNWgERFQD7UXK8EUV+Idp/rnr1NbNDOlaD0+dhG+p4Id+F\niQe8It9F8OXKRtsV/b7VJ70PE+RuIgrdPemrpm67UkBWnBSKixKvX9kJd4ecWPpr0hHeiPZFRA8U\nD+ACqk7FL3Q4yr05PC//O0H2Vym+cbqKruXPHgWLbH9CI9zSMFo/j+Fq7Aq+EDCG58e6G9X+bmFP\nH/5XNkvZhbeggLK+WQr8H9GQIZLZMQCboRvhX9u+eUuhUUvRU9gwFbtDrSz8K8kJBMzb8blG5UwM\nC2N2y41I2+paR+I2m5hEXkKM9tXl7VclIQIsYF6NoNH3ncc1x4HOPwxgUUR36L2amu/bzBn8MXVJ\nftczkKFdZiYMB5xIcDLovipakJFSH/w2xu6WVXWMOiA5kvgUvu+hbbVi6sHkQNFHYKIAjobH3q+3\nDrc09phW+ROYO+aTcQbKrIjZd71OhsV5rzwZ2JQ7ki7NSzGWrG6x8vZodBDEMCl2MIjkqJ+PHIov\ngo1cRx+oS/5Dae9iXLZjx04CKFNUWUSPyHHrfbNDyOPrdvGCTFr/67j/rGj1J8vVNCxtLm1bEQpc\nSIhvaUaLDRXNEjLHerJ79+3XQHd7IqCcBLemBhPmU+/fiAWJozadBEb+HGZqlMPDNzwkut2l43PB\n24M9Sj7odg/0kwUb+nkDDFoZdwlMwRh+gKg8uvy1/fK1j0sJaMju2Livjx2dKdE1F0GLrtHWI04A\nauTXE9SM5DeEDogTpQeQZPSjlINIteGYpH+oQKh9ZNsv/7z+zVFuvjSsLxXZy0AmwKADhVa+Xh1q\nPOrIzFEtf3FEPdGmEyelpCcZbjgkSf1KggQSt4O4YkgNwswY8tEBLIDAXDQExIjCYv/AIeVtzzzl\n+gKWU0UQjKYMVQCWH9zUlHQz8rQcLCB8EgUlMKDsQVoRJbvQR365CNfAX3W8rMVy4nTztqh7zU8Y\npTMGjwCCnBVie6sRytRY79AmqVpgvBPcuQdAMszg+wqIOS/YOXfWuVWaAHwDpxw6UNFMhWcFKSOH\n05VPD72EbnrzamjHK7JEkayKLgR8VVQaXYvT1jVmwbJ6/f9Gfy8CZaZuJJhKPAbeo8mMHuGWa9HL\nA8hVOZll51JKNbAGr5wPKjPHhfBCcWJqs7VIW00Fms/7xNFGllj/SZtUXSzpO/+2FCnmtjO36lw7\nuBLmHLf7CfjRZYUEgQLNVQA07zta/IkjSnwAojzCOOGiriJKJh6Xxrq7QrpLKKMpwb75V+Bf7UIq\nXCrPo45BCxCLgZ/361L4yE1xbmngU707NlaRF24SuFTe7juhvITEAy3wY6U7A7XsGp1GhBBNaYzx\n63YNFYggmHPw2SyXoCLq+pVuz+tvr1PMqnV3zzb1XvR/5Y4Tsp3bIfi00nNB+tv7WU3mCiKl+KDn\nWulilfdt2qcMkdt7dtmcPpClSu9KfkwSQANc0ehkxDHMf0CT2X361QRvY1BiIqs5wfHnQurPZVvW\nIHViiyTAS3AZ/VOpqQJ9UeATGNz/qAOHlu4l0AAE6xdtAPmQ/ccoAbLOCtCJRlTP4bk+mK/UXsj4\nG5Fs43hzF3JxJ4LR9C2FvUvkNnM4hsoGeWg5/PI3h1hXU7vUZJWEgYReDK1L7mkquUjzkWOBvs/Z\ndZTkag4LuLtNIBkAuT8lMHzT6gfGfl8FX5+8nSILKBx072cjdYwUpvNqyRE2Z/RnolUwJalgqWFb\njwYgWT1LgrAf9zDNpkiBuskNgatldY/dyAyHZ8aoMboKqqPiZMkqJKavv+FSK4leOWqG8/2gaZke\nxNn4gg7BPj+xor4DbD81mH/cZ6YSEZbXxAo5ynx3BpP6mXWX3Q9BVYMbSPDKd5LP/sL+FLO4lhXe\nHGsXA3ZwJficyeFbwqcUF4WXXjftNC8xtQgoYUdMYTmtiO2Wko7wUYf5VzXvf3iAJh6h+ii7bnNk\nQD8LnpXLyWkBAxCxXLS439nKagcl9eGoV9S59YSrP18BCUxHteCTtVutmEwT40IhND3eY4xiK2gJ\n1mJGaWYTHkCq+0qg0+pobyEVhuMvAbp+hax+P5gFIK4xkXaUrJY/rnaXTMMpPlU/ew3xGKHRD6Rn\naz43KtCgy0a0LgYTDuQkkWgfEbeC3Qc3rv1tAYrQoiVSwPN1Ppmyb500ZaLxhfGyslQtV6Cj8IKf\ncHcbEG1SU/vgXR+I/iJitzfGYck2dBP6Hc9bkQiJgCaJyzVJKT2nLPrMra+TZpxLjAf8bfzTaIR7\nyBzAM1+ONLzI4NZwoabqZphQMBeLgkvRZ4iutHq9/65XXwPhJ9rawATImQizNXIWZ/Xc/dBdeYci\ncXlh4cNi9lXr86kv42EtzQO8wiXxvpJNllzagqcYzoDS/2+v9gDA81y/sHczLBSXich8fCL9sHnk\n5HEPy+MWeoxHTXzk4NVKhoDg310u7DNHN/iqdC9jowVF45NxlX5xEGTagsxET2kbWxiMiA+l/seJ\n6hm9WQ5oT/E2yZHcl+/+7WtuGZN65uRALxVa5/5f/aiPVjAc+nbCopYK6mlCZQ1fe6EPe8V6UAwu\nmK6Uxk5h9aHjCoxyl5jtUOUpA3Z2E0IY5HjWDUmo2bW13KxWLnEpTdxtgduawTSy7y1brrIDV9Ou\nthZNeteFd9ZEFakDiqLVxSlFcVeSaMOlBtkUpVqZgEIwE4RUExVbKFs+H5eWDhOO8OZe9cSg9acu\nYYhr68IKC7t9VpDYX5OOgNcj2vxcsNVFwYRGOiq0HeDo2RS36LOmkhoHKBwolhA0gBjZd70RygkT\ne+ujgmuAfYLnTYLZ2nHTE2bGOp0zk1L9xPoBXxIvdp+k5T53k9MUi7R5IRINuNmzr5bC5Qfp1foo\nokZfB1U6tHv1oEOoThzFFHi5MhTQsKEn/ks7GCTg2bAFKYJNuuE7GjA61F1+6Pfp7NPIjUwbK7bN\nTlw/pFPKgsPwRciluwLrUwG/LcAxhFFcg+lpOR6KrBVha2FXaGyrxGufH4oJo5wlwekT/MUb5pmW\nZJgQFHqzjiiXpwW275Qpn8xplJiwEhsVfRYaQIzC5HzBQtBD0Z5xnctY48i77DbgIyL0hIwb/9pW\nQhRC7/N0v7qdT27P0pl+jumTiuNVZta8YTC7G0xouZu+vXxOvE/NO0wbDODHNploJXlfweCV1oyP\nI1N1H5/jXLW0L2eiuCupnTrqSGPbGlL5ABfwLqaZsT5pSY34+77u60VZWbsIexLeWmMfjCRnwqdW\nlazA/KsFkNe9O1U2719btMuPKm+/4TvoYxbpn1POEQsMuuwf9Pu5ujFjLAJq7KtmxM83P+hUfwbr\nG2G0JYCgS4d2fxUgAQiic7SD6J+PBgVi9fHwO7v/rbC/r7wgRKqfvQmlWmB1raUV5e7qFyPgMl91\nDb8DOYHV7Rpd6qEz88xkcQTRT4wIs2PzJ7zBQmRJXb+XbWW88jQEJVpOwGMGWqG33QS7T/CszEl2\n8G/UzSnCH9i0fIkX5bB8hX1jdnr9OkaiXmXu43+ixOyLIbZDRN2aRFEU4bczxAuR5mDXA3WX1DWF\n1LMX3PBCA3DIdqjhKv1+o7MLR+9Hree79XghCuZgtetNgzE+BgpYsP/L+wq4AzZceo2gx/0A3Ad2\nJHE71pWJ/OStHuQFDk7oCr02NKijAhZT/5I73DLzWpVMrpPwG0706DOFl5+bko+2xhL+vKkL4s9G\n43sC21ZYXx40qplG+nB4fhtMI7Lx12xMc6QgJO/DJGJbPIp5sPUk5yZyzFSb6vxhQcGKzF0jRKk2\nblj8QeOpzwmj2vNpKnM80a3UxpPiqfN7qiNdQV/oGE4utr7yunmZfyhLjo/uE0vfzSjmvB87f5Xq\nlSz9CuGzxhmVUGtT60TctfVAGIWcvXELEXV9HRvbEvzJ/XxlarWtZBkumvhDxv+H3/qxTBYBB3VL\nEE7GwzXzsRqrfwK5sZNZBrnzd+XIfp91Cnc96mK+7oU/+LV+A6NtqwEEdxNXA9EK6BlqTOYrfmNU\nUAyIzodRgP4dyJKUwF0WnCNbwi+WgWfKxeD6J6U5fRGoUSwKaIxOmNvBMgeSQ2eA+671h0YMe4NP\nqggDfVx9cXGcpytVWFntnxs6aQPg4qSpVOZkJHP2/oUPTaeW/+Hvyja+m3VTiajRHS+lfWABSwkq\n7pRAbCjzIbKeOM6sY4W63453Ewo296f3xh5ZY65u0scQgUyXtB48n3211e4tIIKNN/AwXo08/bhL\n8gThWAG9WhH2kzkFX3M7AZm47XgemDZnxChGhAXlif7chETEzzJtM8Ytn6zgg/ph9GV3i/Z6aun0\nmrCG0LMtrg4CJo+4mHmQUG27Gtd/PIm9eqWdt4ywk02K4gGJ67YvXnm+EhJHkApngBbKhp+I52ee\nZtUw0Li4xW6bs49i2dOUAjx86jsKeU7uJiWkirUvQ+aK37MPYTPcfME8nYmJNlOwZWzbVKfm00HL\nk0qmK6iDSmL/DSdx9VnPtGsNRFDgI1hAkSsqoGO2mCxxCyfAc48cWKxErLRoVWoO8VSl834ogKht\noeVK58ezIAHphOWtGVwz6GZwBiIy//1koxIMb3oR/qvXYhyucGPrvWOoGAHfpFsQPqwrb+rEKn03\nScU9PlrRZFhZOONC3GwM8Pssp2AOJT6RI+RXmNsMX2QRDtwDnC4vmHwen9MePiN3F/jppJhwA8RW\n/Rm1C2FX8ODUUj/mJU2oyh2u1HV75vH1uvUNFzDmB27k9IBiPpU0jjvuSXAJRPkzve4rYPV9xTL8\nfvi3Vtkjj6ahvzGVcsAVgAX4iWHLuRCHlAmMaXvPjURqSCU6XRgDTx1ia0CoytuL3y2O+KSUqBEK\nUqmtax5Wn+VzUtROS462rJdrp3YARn//1bxpXyg/j1/juWv0yJPQgUYcU3d3JuYIp8Q8jjoVodhn\nP1QPd79DXNB/Pwd711DNxOb0sk8yEPXHXc1Xcnnuz7a1WrYqeU+Ww/PpVga/3biOfdSOi339aWgB\nfndekDI0qMl0s9pWT+9CPjkyL0nbVWARb/uVgNpjHNmro4Nbj0HpFXKX9fwsBDeBmD2lgBrmbKj6\nbdRKGMZutn+k3xVU2uNfdFPeVpbC5lod/2xvC8Ful+0xSpTdyyvsUgfPwPgPtL/SOrLFT0nutxzZ\nkz8gjdMQ4dFDPg5YoKfi+ICV/qlSloXDse3ooI5N1ZuDqcKdcXjzm46vsfHbCZCzGxIgo+W3tT29\nAKYT0/xSqJTbX1kkMmCMOiQqCfGf29k8J1SaP1lrOC5l1AA8nrKBjm3OvciG8hf+5r02GNnwBp8Z\nZDCjx/Atsr+9LAHvecc6HiHJPuNCINcP5TLiSfF0jgcdsQm3869+RWCQUX5yLZWiVCpuQxFzPLPm\n9mjy+MRdZRDrfpkdPkHapHE3kPmPVWQXDTnhLYOgE4vdcljB4tWrpeCNm+JgRQ03G+v+wSPN9TYb\nrwX2GUhJoR/ax47EWPbYauv7LNZ2bJGfOb9s/o8KYw68eXkgj+FDljZzzP0dKUQqYjNgIw2TGCxY\ngcJ7cxv8BTZJ/JTxk7ZL577zd1AInIq0wuKBFqp2t/9tMsxSXegD0PLlzMB2fDYVGmncDtT4PzlE\nozcuiUJRipjY6DoesJlfHKyxNqJNNxjDOW3SjMiKtI8JtSQNH0BSyrRIyGNGXzX/uQArTH65IiPY\nkbNFkh5LMdN5Wn42QqnWV583GGVqmNlGzHkdprd4C+xMN4kkWbjaJVSDHQGeVbUdqT7K6j1Sa/gY\nKGZmys+BhBpakUrOXa2ouadrpwLjtjwhGHVq+zFPcxNyMBIuT43rLb116BwmRtaHmmQRa1Y9fgPg\n7LWLlkhNqEKOAPWFDQUuPpJqYr94vCP0A9arjsxYSzLkGGUsYf0r35nsW4eRMZjFyywzOyktfHup\nchvurg5EDDibgz8QtOdlGNqjerLNTRx+XGEqla27/jSiw8H1kgGrPDAeYsfAVs5y2+3WJNAsw9hT\nZzFM8t/CCIgXX2pj4yrJxSskmH6QjRspvr+VxbpVgFbgSKw/l1lDbmJDDPgX89Wmo0Bog+C8R21R\nqseSnoWZu17XsTWPMkOBeLmus/g7Aw7CMHMIYuQ4A4cJu9j0Gc6RVLvud7iLe2FMoSn0HdrObS/v\nRUAkfW832KW7aEdntoOLUdjtzOQ5QKD8YnNfz4LAzm3OhInLz/DshGnUdxR3EAL159zxjVlLZKGK\nElxu0aK5Jr8coyzWWtm+4HX92C+Qb5vXEXsmqRgIZoQPp5RpRukTUGg4zq4uAWspaTKNzxxlIEYI\npM4B/sIKkQ7sHptRAgZ/K8sDCJolRdeda8ln2ywDEJkz2nu1Kw0jm/+XghX8j1SIOG0qWiz6/Ybc\nzdbJO4Plp4J+X39ZxONVdiGg1EbaJ8UYFl+7inGY0c+VUCclN6lhgWULVKgp0ZbB3yLpKvdDBKgD\n7ZPXHoHemwi+R5aEY7fxs2S9MQcCvo7n2z8hTeHWb+DA5zq8/x/8eWhaI77HZ3DTvtkC2mVsiImR\nwjAkfk0z5JHXQ10Dqdwey7NVkAHLKwgXQG7SZFqrdI2PQV9HHw8bn3m6P+f7/EAy4MkYv8OHlwCg\nAz44PcpP9zXgPo5kl094cZivvFVVOC9A14EHv5xaRJSbue3ckHwAaVgXMonasMWqzQXHHWB4pM/2\nzq4cgM+X11VuzcRfROlRKdmu9umzZJq3sAFpM5xM4oyWtBLLHCdk+kmOffwThUPQcFT6Cp9se2Wv\nBQ3DldAMEtZ/j40qXaVivpsdHisEwN5FZQdxBMQqzZaP4UxldJ4xWKA3n61Muv4KIfoUKajddLuS\nZ5bqFL3zAkvxOf3JPUroU3wJfi2PGRcFmrNSWgp7VEHsWiBw//1PEbEYYXNzlCG322IbiY2RL6iR\nA7vI7/83fM4uY75AhDlBhuQHcEG1mL/9OfaC8TOhJiCwn2ByChDEFZhloTgtP/ZWa3aVGajOfbb2\n9X2Q7O2fzO9lBbF49OOnRLGTGH3jggbIELpZYfUF2wHdMdRJa3vJce8DTqVv771jzqUjE+fnwOv1\n269F8crvbc0cn13uXMkAyw1nN0wpG1H9l1P6jnVhrYq74DkOPEjkiK4unQKlx0aZI/YIHcAfszVM\nY0VIC2djUXZXrZlW3Y4bUmtoO4kMwI/iMgrYuA2cnHULO79HXnYXhrsdAAv9xYSiCAVQv1w7trDt\nXOmMVGvsc7eY3BpFegOKEqPqYIb5cwa75vy47XFo1zUtjPohgZ/g+MCSwqRz13l5N9vQlFSUL857\nRIPEeotyNTAsdh3vFX/jYfsonxch698ZbFLAAZ2uagiQ4oDuMeZpgeUnzcsT64lJa8GhO9cVASuE\ny0F6GpshZvVOe791qrdIB+EJ+FSESXq7IBlZ7u8nKzT3vwJbAFCmo2FIPqzBzR6n3aAQnYVuJIKN\n5Sg85UzY90qoBTGnu7wz2Z8lnZ8kGtpDSDOGhDFHBOGL1+xytbC3IeWxpkSUppE4dMh3UBtUpQpc\nrznsPHtwQusNoU5UHNl+ro08V1FXkHUs3BGo7cjO1E5mEsXECd0Yh+x/PAAC2sove1R0oZM6sGqv\n+cCCB7Vc9Az/Ei+rKcaQ7/cztvAERpeXYbhXrHeIwzJOeo6SllZ6eWAU0t9Umj75FZpWqfPlVngg\nxspwNQyDQ+pzoelgqX6CDTSoJJVBX6ypQoRpbQK004AUM2ODfMQeGrXJroVW7Dn/UvFzPHrPglZC\nHQmAG7G0MAv1OywENidA/tXzqhJYQ8VCtT2y/tKc3sh+T2PofUFs/sXPkTtUY9ALHm3DeX3H4CQP\n3Rb+ibBMospJV/C4wY8lXWgxxVCfBnLgO5r4RdQZ9iG+D+jNnqOzIsmOWgzNE+mbRYtKgPjmCs5w\nkpDjZCTmayxeTJBGAHsyCqnJxUhm0lia66LtCTkMcuB6j6i35CZ97kDpwIOi7AutER7n7lPH++Gn\nm3D321MZdm8kTkBVzTPhrnCA4JFEy+muDff1jfJIYuipA9VLqGCgficM2pPxl5PAt10RYCFRIczP\nImS8vQ89vm3/mEJLxVdbhKLSSIOUe0SyhbZ2qI77n7Pds4qv2SY5jt+R+iIhRASw7/v/kNYUxdiU\nd2whz+3cp4AylBxKxxEOrtr+SEwv9Onfj3IHTQtGHr7vZ7YgYe0YTvUebilhEDptwX6Bk4wHVH18\nELtY4IKlOENXltTlk4Fmfj2DWrqzrYwE27mXmVsBkrge382vltAomA/zHyDmmVAR9fSNI8kJqPv9\nBf0kt+ri0IU1ZZg9Woj0aa6yJritF6/2sxQwnu7hDud4nxN6agLEuHlhB37LbdL4HSPtvvRyQBEA\neetF5eYD5jUT+9nAbGZ+gGiyc7is+4wBcp5djCDST+xp/aqAUweRDNoGPk9chJw7tOrYGAsiLigf\nXAdVxBdEHR7w35WoJZOKR/ohU4uVHNlLcsqfPX8Dvr6UBD0lPGmwIq2vqjVCbdb7t6yILuEq9Ufm\nMGfARBYUMcz0CLCaO6fMddLXYb3+7JNc6BfgeNNs4c+og1l/7cS5kyAZ7etGCS4NmxOe8lgxHUWw\n8IO0tvTl6ukkA/6HFwXkZ0AbJcHifOFomjCv7anv2hOfuO9oEeFpp3WDj12n2Td+ZsWkf1AmoukR\neHaSxklqdCPcEI+UKHxQLNyr8pAOYswoRRGZbIqYW/ta17ZpL5ObFe7L0dnkTerzaK6+7QuQcXN4\nPEGg/nZtybL619pmNPfMj7PZjzIQeW/8N19FXPNLpPAoVClkPHG4Jw2tWKC4w+NgfUpUZJV5/oLG\nE0Qzbcl2mu8ISb5O1UcRkK4QStBrSta2QNvkxAkqOMW/jbQTViSnlFGnQPa3JBnvZ5xx8kSZDoL4\nzRzW+5sj6EamucW1FGMHEcaRnfoI9HYpQXf/8IyKuWe1UyYuhDL/2GkuQjpJTaIy21kze3sprXk6\nwpt1QJZ0Edtv5/8ks9db7hw2IbtXZBpSZpvE9ugD0lLiq5rPGhEahktiI7dZ3qbKT0bTXgXhrq9q\nSUMqwZoXaG/OkXvzEGInn5k3AP8V71EZfoxn5fn/UOuomkWmITLVKtg7tWd1LyrVbmJiZZFDZ7qI\np/XN53yVoQSXwoT4AshECVSbN/qX2+Qwu9Li7N8ET6x0aZ5qsJoEZr2yW2YVjQfbzCQy2cyj06/R\nMr7wwHXXa9rwr8iPvJZqmheEb7Y0AT8RjFFkICCE3TaRpLpc5GXvlm30aMqecTG2WVjbcnNiR+4F\n/C2wlDxRVm2bYvBdaKYVpicEjIE4yUAuMM8LkISEeRh569nRfVlQvmBwU9/WwXT3Ti/9jnbnlYvr\n+Ahjwb2/qNZd5qdcZoIm53BHEPFH6Vq1H/Gh/kzAJKdFN/PoXZKFLX463Mi70+9jrOYA1OiCHndK\no3zf7txPRp00vR2xJpj4unJbmpT4ffdThfuCSmKXRBTTZrgzY9yS6ftKCkee51Ztt+U6nPNlUpAN\nllyRhHkTPq060dxFuYOAoh9z58j+mdFB8eni0jqIqTlySXsVysNMX8AEngW2l89h7oV7E6W3Cthj\nLMSiKmG2/uMLyVm+c2btxBH1BiQRhQ1Rv9q39KwMbuGrzU1o1P3FtPG5HSsyJGmJtp6rDaNiiwxb\npFvHTWhTiDlj/0drNkTzFhG1JwaNzt0kOuewsLPdSir3uklbO6ecYaPK8Z4jgXerghf6lEyknZLS\nAYkKYA3rNh+45AAi1hRUOi3cp/pEHV/rSRmAPuczKvBZi/XmAqj6LGPxNcENDgMujqSw+7+uJJ0U\nQ9Yc5CELdrqvZ7mpxDFUx8QeiSww/sXE6aExkV68LMQHbrd4YaV96mjBcBLcyVqzRhLPDyuNzEFw\np4qk0TDXF1ACMNds2+Dt/Uuq9fxkmO5/q/GV1TyqO2RLP/z8GSXYvfZqOpJDtkFNGW4YcUU9OabN\nad+Q/9AomAx6BhJN0djqPBEafbnO0Jt3UVlPRE+gFekn0MvN+Tvw8vtBYQDL9VjaXZ350tmEqM5n\n8r4nQDI2NKf2AqFC1h6yx1D80OPYltLCRgU0y2GMZwp5ffMxpciUQYx48wteQkIj1vSGxelD7w3D\nFp/RHW7VRDRDzGez/pb0ZUlkmUzN7U1Eo3XRciUGIqIIUNn/ONyb3yvpQQA8wPiq1mwZIKZxyItD\n0U/CJNypm/F4npGM0VnY7fDcgFt7D29oorNPtCf2GAGAwDgKQmSNPmHVa8jJsYiuDcpw9URnTY9V\ntlH1HgWU+Tvr/riLXwOUqSufAPwmdP3p7nNAJVhufvf+5dLe5d3hxHtLxI6kjQwypWq3UBSwzQs2\nLO1+IJ1O4ds3iOra8+5J6u94UI1YsUbGYPOJwvzJ6SjHcLu8x6cWFhaUV2G6xs1fpi+7XO3lbm0y\n5W27tdy11ymOBHal9SdMg+tCFS62wxb2pPE8ZYDSXcwFxnU2QoKifLjZMYzKxXJFwweri6WL3VCt\niqEVBjol27uPCleezJI93TjZrRwL5CETU1b0nUl7hB5tni/KeEvIgKJ04f3KhE3w8g2abb6a0kXC\nuIlTQIIPxUM1ALbGJ+4f5qlVpvJ7nwT2bZ394BwTsH2S8eP241Bq2eVSuOi3Ab6tapNU4YNxIpBL\nDzcIQ/Jq3ToPenfueZrnGr3xKjeXYHJFhki5fzQIs0UkV8rvZP5qWUrko6dILN62pdzGOFJ+y4W0\nXfyMB2uKuXJv6Utx9fFydtYUyEj8Zrn90goiFM+NQU0iFdZ4QEvl1Ts+dv8/rrQH3eJTZqvI/yE3\n12TofYflRc2uRuGlx0r+Q6/3+33yPzrfr6U/aRx1N2E+vcv/L2kGVucq16ibQzJGIZqfHdBints2\nnB/xvJob2flgExd0M73QfeiBCRHzrKKyzj9Xy/YqcQjnpVZHJ0z8Khrxyx3uHHEjnFnVbod7bFEU\nc9ZV++TR2/rvd4/6tgAzf4slQhJqLWCG50xvRj+FPZPCbvxvtFnpArHuGPLhQP58M+qu8J1r6I7s\nag7qtFsFsPbykd8JxRwlB3lt4K7cNC1bKu6iSfT4vsU6XRY/ascVBykqvZDfh/zsnUvrZgmKCCBr\np5h8nDwS5zWHjQ5jShlMEqUr1g8tXsoh0g0RCOAYfHMpevkuPO3hdOrwj6+xJKkkfvuUKAJ15Siq\nsfGhPHOKEye2SzkPITZCk6Epg3vCrRweshnptUBNLAAEgZFGjAcsUQpnC+ckfUoseyAmdGwL2gw7\njQTTYXUrHvMyk+sKl6YTqd1bkaKW4kkUvaZ/rhWQefXwi759KpCKAStFGqfBO0P0buiDMWT3NQZW\nSLbgrltCu/0xvuYiq4t2Dq4pEfgQhWDCTXNAaavjbEt3oNWVDk2/oLH9DhhaEGJ7cp8+e6N6+QOS\n0bspQnURwauJmMJ8yUNYyf9ta8c40Np3aJDOareux0hbEISmQSc4Ibt8NqJFXqF7N2NWS5A+gSsi\norAZxPtzThjQ23JkrwJ0ZPNmbmcrPw1mfTOehFBdqoWPx/V1eDm5NNyriTd6LoYLbfHomQ+8WALR\nvZEOzoN+xewA5Uyk1S3+MzmEKZ3CVhK3GHoxuIMA7jpKebjYySo4sCnlQMb6qqT/bEYEyIsnWvcy\n82f7UbQc9TnIkHDhaRJw2m92dRvylHLCW54hHu6QLRMVKvHYeJNzEdtEit7GocKKSTkPn4BPI/Yi\nDB78TGR7uT3b85v7IOyxHBzEe9as39kKuQRced8pqdr9rbXMTxKG9fjurivrGePnZUbfZnOrpVRL\nkKCb+IpI64a/68XG/DR/SKALmfHrlb33vpCSd0LPcJ9gJUYGctaIA7XC5VtBzhDIcR9PBU+tTm9W\nau9psrwiInRr05n+P2ka3juxmJUvRjj+VYdfHsFkpNtAyitihSAmtBzaFQ/GCY9qd7kXWuxltG51\nrFrtLeXwN+9Dnr+9ExBWRWkyD107BNXg7Q127EZxGeVB9VR/X1KLOqjRClcK7lJrRpdva5kHRJ54\nKhRZV1sepRiHDRVCJIhJ9U6FWd/rQgWMmmcGawdgO1OX8kC5EdLJpXpkSeH5Yjqv3zzjASPu7K1e\nwWPiAxuwVgjdGKJIbluw6G5pJQ2uXDR5Xa5xsfAdroYQ0IRUvAkeOY3tND4Lkw/XVvx8KeFAWTNp\nXenmRJ5/iBqiIfM/c/rIofFpZCA5QqrNEMfQtDBkAJrxtq1sol50O0rih87WaJ+mdtwngYU7HOXS\nRQ+QLH1ciUq6EcJ73P+0hPAOokjzgjhqaori7+/iLyN1C/AWI1S59VXo4s8Lrl4s1/kVBR4QHr5V\nNiVmq4cDDDzuL1SP1j/K7bkn0GyS/RY8DPXrsujE06j3tTvjvnMGY/HaviTzAHivPGFzfXWofpT/\nFOBIBBwbn4pUVoeGWQJXIoNTcyeIxLLEOiJ2zYAUEwEdsOn+f8+dtBaERYpwAhYE4NLbwH6ple55\nRwSPKczzLDMieRAXxc+iQjGV4j/5oqHAmcwgXN7zvk/aGpMYPyA2berXcmFw0LSY1sepZIKYaWuj\noYF9Y7ElShrguXYyk1lAuvOX8VPhIpudfS7dnJHZRceapQi/Xl8DlsQg5fPaQo7gvh+5Hxbe5/dt\nsNmxiidiIGAyoTi091EqBHlEwjR9IhtjBB9469BfzhnT6ccPVCINNxJpiUBJiEOtublFQ/M7KWIP\nfC2d0pCxn06H9bmLT9zfhWsyldmMeBU9AEB2Ck/kn+c75sFlRezkk8wmqlFM2NcAvQcSf8GR2hO/\ncFxi9ZzXFOJCgdfy/9zY0YFHKKnurAgHZlgOdBl8inDgvgC2RlDXnzIuz23kNA9RxHQ2/FXl0z61\nnYwe+SCMNDzoPcUZcUBhPZonJ+3irIWLUdjkbb7qTGymgjf5KR/XMuWA/VX/8uRtjWSOc95Nbt8a\nCaci43oMh2lwO79FoeUffZYmZV3fldqnDs1ze/aOGywPwqcT1jntje94qn3lvQoQ/BJ/k93rEy+2\n5x0vRK6gNlXO4KtnS9D9Ypwk0VbvxdQ8n1IGdI8B9XTjg6ENjqtUbomhDPSFQCjwicweZXrRfUOD\nh+cPfCp22/DQgxGK2DHVgSjAS7NgTpMzbMt2/jQdh7ewO5Ek07NBPGfI47RJujdhRIoS6lFB2L5i\nM2Ly8kjyyAQreVG7AMc6P3r5WOlcr9TujTmvWGh8TOwQ1LDhVNVKJ+JGG1AzuIFYfDJBzzcZd1A5\nteF80j/Z0cUfa1hdkR4d4OTqS5QotD9WNh4QCndwopopxD6G1h9s/s5UVf0blaIfjDBU0/Nx9WVK\n6t/6Ruyhta8hQ9IxRw2VqEEY6Evx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protect end_protected\n", "num_lines": 530}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_0 (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [63 : 0] probe1;\ninput [0 : 0] probe2;\ninput [0 : 0] probe3;\ninput [63 : 0] probe4;\ninput [0 : 0] probe5;\n\n\nendmodule\n", "num_lines": 73}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"ila_0,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_0,ila,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=6.2,x_ipLanguage=VERILOG,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=virtexu,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=6,C_DATA_DEPTH=1024,C_MAJOR_VERSION=2020,C_MINOR_VERSION=2,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=6,C_CORE_MINOR_VER=2,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=2,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=0,C_EN_DDR_ILA=0,C_DDR_CLK_GEN=0,C_CLK_FREQ=200,C_CLK_PERIOD=5.0,C_CLKFBOUT_MULT_F=10,C_DIVCLK_DIVIDE=3,C_CLKOUT0_DIVIDE_F=10,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=4,ALL_PROBE_SAME_MU=false,ALL_PROBE_SAME_MU_CNT=1,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_ILA_CLK_FREQ=2000000,C_PROBE0_WIDTH=1,C_PROBE1_WIDTH=64,C_PROBE2_WIDTH=1,C_PROBE3_WIDTH=1,C_PROBE4_WIDTH=64,C_PROBE5_WIDTH=1,C_PROBE6_WIDTH=1,C_PROBE7_WIDTH=1,C_PROBE8_WIDTH=1,C_PROBE9_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE12_WIDTH=1,C_PROBE13_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE18_WIDTH=1,C_PROBE19_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE22_WIDTH=1,C_PROBE23_WIDTH=1,C_PROBE24_WIDTH=1,C_PROBE25_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE52_WIDTH=1,C_PROBE53_WIDTH=1,\\\nC_PROBE54_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE70_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE80_WIDTH=1,C_PROBE81_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE108_WIDTH=1,C_PROBE109_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE131_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE134_WIDTH=1,C_PROBE135_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE153_WIDTH=1,\\\nC_PROBE154_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE156_WIDTH=1,C_PROBE157_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE160_WIDTH=1,C_PROBE161_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE184_WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE187_WIDTH=1,C_PROBE188_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE210_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE213_WIDTH=1,C_PROBE214_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE226_WIDTH=1,C_PR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BE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1,C_PROBE0_TYPE=0,C_PROBE1_TYPE=0,C_PROBE2_TYPE=0,C_PROBE3_TYPE=0,C_PROBE4_TYPE=0,C_PROBE5_TYPE=0,\\\nC_PROBE6_TYPE=1,C_PROBE7_TYPE=1,C_PROBE8_TYPE=1,C_PROBE9_TYPE=1,C_PROBE10_TYPE=1,C_PROBE11_TYPE=1,C_PROBE12_TYPE=1,C_PROBE13_TYPE=1,C_PROBE14_TYPE=1,C_PROBE15_TYPE=1,C_PROBE16_TYPE=1,C_PROBE17_TYPE=1,C_PROBE18_TYPE=1,C_PROBE19_TYPE=1,C_PROBE20_TYPE=1,C_PROBE21_TYPE=1,C_PROBE22_TYPE=1,C_PROBE23_TYPE=1,C_PROBE24_TYPE=1,C_PROBE25_TYPE=1,C_PROBE26_TYPE=1,C_PROBE27_TYPE=1,C_PROBE28_TYPE=1,C_PROBE29_TYPE=1,C_PROBE30_TYPE=1,C_PROBE31_TYPE=1,C_PROBE32_TYPE=1,C_PROBE33_TYPE=1,C_PROBE34_TYPE=1,C_PROBE35_TYPE=1,C_PROBE36_TYPE=1,C_PROBE37_TYPE=1,C_PROBE38_TYPE=1,C_PROBE39_TYPE=1,C_PROBE40_TYPE=1,C_PROBE41_TYPE=1,C_PROBE42_TYPE=1,C_PROBE43_TYPE=1,C_PROBE44_TYPE=1,C_PROBE45_TYPE=1,C_PROBE46_TYPE=1,C_PROBE47_TYPE=1,C_PROBE48_TYPE=1,C_PROBE49_TYPE=1,C_PROBE50_TYPE=1,C_PROBE51_TYPE=1,C_PROBE52_TYPE=1,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,\\\nC_PROBE106_TYPE=1,C_PROBE107_TYPE=1,C_PROBE108_TYPE=1,C_PROBE109_TYPE=1,C_PROBE110_TYPE=1,C_PROBE111_TYPE=1,C_PROBE112_TYPE=1,C_PROBE113_TYPE=1,C_PROBE114_TYPE=1,C_PROBE115_TYPE=1,C_PROBE116_TYPE=1,C_PROBE117_TYPE=1,C_PROBE118_TYPE=1,C_PROBE119_TYPE=1,C_PROBE120_TYPE=1,C_PROBE121_TYPE=1,C_PROBE122_TYPE=1,C_PROBE123_TYPE=1,C_PROBE124_TYPE=1,C_PROBE125_TYPE=1,C_PROBE126_TYPE=1,C_PROBE127_TYPE=1,C_PROBE128_TYPE=1,C_PROBE129_TYPE=1,C_PROBE130_TYPE=1,C_PROBE131_TYPE=1,C_PROBE132_TYPE=1,C_PROBE133_TYPE=1,C_PROBE134_TYPE=1,C_PROBE135_TYPE=1,C_PROBE136_TYPE=1,C_PROBE137_TYPE=1,C_PROBE138_TYPE=1,C_PROBE139_TYPE=1,C_PROBE140_TYPE=1,C_PROBE141_TYPE=1,C_PROBE142_TYPE=1,C_PROBE143_TYPE=1,C_PROBE144_TYPE=1,C_PROBE145_TYPE=1,C_PROBE146_TYPE=1,C_PROBE147_TYPE=1,C_PROBE148_TYPE=1,C_PROBE149_TYPE=1,C_PROBE150_TYPE=1,C_PROBE151_TYPE=1,C_PROBE152_TYPE=1,C_PROBE153_TYPE=1,C_PROBE154_TYPE=1,C_PROBE155_TYPE=1,C_PROBE156_TYPE=1,C_PROBE157_TYPE=1,C_PROBE158_TYPE=1,C_PROBE159_TYPE=1,C_PROBE160_TYPE=1,C_PROBE161_TYPE=1,C_PROBE162_TYPE=1,C_PROBE163_TYPE=1,C_PROBE164_TYPE=1,C_PROBE165_TYPE=1,C_PROBE166_TYPE=1,C_PROBE167_TYPE=1,C_PROBE168_TYPE=1,C_PROBE169_TYPE=1,C_PROBE170_TYPE=1,C_PROBE171_TYPE=1,C_PROBE172_TYPE=1,C_PROBE173_TYPE=1,C_PROBE174_TYPE=1,C_PROBE175_TYPE=1,C_PROBE176_TYPE=1,C_PROBE177_TYPE=1,C_PROBE178_TYPE=1,C_PROBE179_TYPE=1,C_PROBE180_TYPE=1,C_PROBE181_TYPE=1,C_PROBE182_TYPE=1,C_PROBE183_TYPE=1,C_PROBE184_TYPE=1,C_PROBE185_TYPE=1,C_PROBE186_TYPE=1,C_PROBE187_TYPE=1,C_PROBE188_TYPE=1,C_PROBE189_TYPE=1,C_PROBE190_TYPE=1,C_PROBE191_TYPE=1,C_PROBE192_TYPE=1,C_PROBE193_TYPE=1,C_PROBE194_TYPE=1,C_PROBE195_TYPE=1,C_PROBE196_TYPE=1,C_PROBE197_TYPE=1,C_PROBE198_TYPE=1,C_PROBE199_TYPE=1,C_PROBE200_TYPE=1,C_PROBE201_TYPE=1,C_PROBE202_TYPE=1,C_PROBE203_TYPE=1,C_PROBE204_TYPE=1,C_PROBE205_TYPE=1,\\\nC_PROBE206_TYPE=1,C_PROBE207_TYPE=1,C_PROBE208_TYPE=1,C_PROBE209_TYPE=1,C_PROBE210_TYPE=1,C_PROBE211_TYPE=1,C_PROBE212_TYPE=1,C_PROBE213_TYPE=1,C_PROBE214_TYPE=1,C_PROBE215_TYPE=1,C_PROBE216_TYPE=1,C_PROBE217_TYPE=1,C_PROBE218_TYPE=1,C_PROBE219_TYPE=1,C_PROBE220_TYPE=1,C_PROBE221_TYPE=1,C_PROBE222_TYPE=1,C_PROBE223_TYPE=1,C_PROBE224_TYPE=1,C_PROBE225_TYPE=1,C_PROBE226_TYPE=1,C_PROBE227_TYPE=1,C_PROBE228_TYPE=1,C_PROBE229_TYPE=1,C_PROBE230_TYPE=1,C_PROBE231_TYPE=1,C_PROBE232_TYPE=1,C_PROBE233_TYPE=1,C_PROBE234_TYPE=1,C_PROBE235_TYPE=1,C_PROBE236_TYPE=1,C_PROBE237_TYPE=1,C_PROBE238_TYPE=1,C_PROBE239_TYPE=1,C_PROBE240_TYPE=1,C_PROBE241_TYPE=1,C_PROBE242_TYPE=1,C_PROBE243_TYPE=1,C_PROBE244_TYPE=1,C_PROBE245_TYPE=1,C_PROBE246_TYPE=1,C_PROBE247_TYPE=1,C_PRO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525_TYPE=1,C_PROBE526_TYPE=1,C_PROBE527_TYPE=1,C_PROBE528_TYPE=1,C_PROBE529_TYPE=1,C_PROBE530_TYPE=1,C_PROBE531_TYPE=1,C_PROBE532_TYPE=1,C_PROBE533_TYPE=1,C_PROBE534_TYPE=1,C_PROBE535_TYPE=1,C_PROBE536_TYPE=1,C_PROBE537_TYPE=1,C_PROBE538_TYPE=1,C_PROBE539_TYPE=1,C_PROBE540_TYPE=1,C_PROBE541_TYPE=1,C_PROBE542_TYPE=1,C_PROBE543_TYPE=1,C_PROBE544_TYPE=1,C_PROBE545_TYPE=1,C_PROBE546_TYPE=1,C_PROBE547_TYPE=1,C_PROBE548_TYPE=1,C_PROBE549_TYPE=1,C_PROBE550_TYPE=1,C_PROBE551_TYPE=1,C_PROBE552_TYPE=1,C_PROBE553_TYPE=1,C_PROBE554_TYPE=1,C_PROBE555_TYPE=1,C_PROBE556_TYPE=1,C_PROBE557_TYPE=1,C_PROBE558_TYPE=1,C_PROBE559_TYPE=1,C_PROBE560_TYPE=1,C_PROBE561_TYPE=1,C_PROBE562_TYPE=1,C_PROBE563_TYPE=1,C_PROBE564_TYPE=1,C_PROBE565_TYPE=1,C_PROBE566_TYPE=1,C_PROBE567_TYPE=1,C_PROBE568_TYPE=1,C_PROBE569_TYPE=1,C_PROBE570_TYPE=1,C_PROBE571_TYPE=1,C_PROBE572_TYPE=1,C_PROBE573_TYPE=1,C_PROBE574_TYPE=1,C_PROBE575_TYPE=1,C_PROBE576_TYPE=1,C_PROBE577_TYPE=1,C_PROBE578_TYPE=1,C_PROBE579_TYPE=1,C_PROBE580_TYPE=1,C_PROBE581_TYPE=1,C_PROBE582_TYPE=1,C_PROBE583_TYPE=1,C_PROBE584_TYPE=1,C_PROBE585_TYPE=1,C_PROBE586_TYPE=1,C_PROBE587_TYPE=1,C_PROBE588_TYPE=1,C_PROBE589_TYPE=1,C_PROBE590_TYPE=1,C_PROBE591_TYPE=1,C_PROBE592_TYPE=1,C_PROBE593_TYPE=1,C_PROBE594_TYPE=1,C_PROBE595_TYPE=1,C_PROBE596_TYPE=1,C_PROBE597_TYPE=1,C_PROBE598_TYPE=1,C_PROBE599_TYPE=1,C_PROBE600_TYPE=1,C_PROBE601_TYPE=1,C_PROBE602_TYPE=1,C_PROBE603_TYPE=1,C_PROBE604_TYPE=1,C_PROBE605_TYPE=1,\\\nC_PROBE606_TYPE=1,C_PROBE607_TYPE=1,C_PROBE608_TYPE=1,C_PROBE609_TYPE=1,C_PROBE610_TYPE=1,C_PROBE611_TYPE=1,C_PROBE612_TYPE=1,C_PROBE613_TYPE=1,C_PROBE614_TYPE=1,C_PROBE615_TYPE=1,C_PROBE616_TYPE=1,C_PROBE617_TYPE=1,C_PROBE618_TYPE=1,C_PROBE619_TYPE=1,C_PROBE620_TYPE=1,C_PROBE621_TYPE=1,C_PROBE622_TYPE=1,C_PROBE623_TYPE=1,C_PROBE624_TYPE=1,C_PROBE625_TYPE=1,C_PROBE626_TYPE=1,C_PROBE627_TYPE=1,C_PROBE628_TYPE=1,C_PROBE629_TYPE=1,C_PROBE630_TYPE=1,C_PROBE631_TYPE=1,C_PROBE632_TYPE=1,C_PROBE633_TYPE=1,C_PROBE634_TYPE=1,C_PROBE635_TYPE=1,C_PROBE636_TYPE=1,C_PROBE637_TYPE=1,C_PROBE638_TYPE=1,C_PROBE639_TYPE=1,C_PROBE640_TYPE=1,C_PROBE641_TYPE=1,C_PROBE642_TYPE=1,C_PROBE643_TYPE=1,C_PROBE644_TYPE=1,C_PROBE645_TYPE=1,C_PROBE646_TYPE=1,C_PROBE647_TYPE=1,C_PROBE648_TYPE=1,C_PROBE649_TYPE=1,C_PROBE650_TYPE=1,C_PROBE651_TYPE=1,C_PROBE652_TYPE=1,C_PROBE653_TYPE=1,C_PROBE654_TYPE=1,C_PROBE655_TYPE=1,C_PROBE656_TYPE=1,C_PROBE657_TYPE=1,C_PROBE658_TYPE=1,C_PROBE659_TYPE=1,C_PROBE660_TYPE=1,C_PROBE661_TYPE=1,C_PROBE662_TYPE=1,C_PROBE663_TYPE=1,C_PROBE664_TYPE=1,C_PROBE665_TYPE=1,C_PROBE666_TYPE=1,C_PROBE667_TYPE=1,C_PROBE668_TYPE=1,C_PROBE669_TYPE=1,C_PROBE670_TYPE=1,C_PROBE671_TYPE=1,C_PROBE672_TYPE=1,C_PROBE673_TYPE=1,C_PROBE674_TYPE=1,C_PROBE675_TYPE=1,C_PROBE676_TYPE=1,C_PROBE677_TYPE=1,C_PROBE678_TYPE=1,C_PROBE679_TYPE=1,C_PROBE680_TYPE=1,C_PROBE681_TYPE=1,C_PROBE682_TYPE=1,C_PROBE683_TYPE=1,C_PROBE684_TYPE=1,C_PROBE685_TYPE=1,C_PROBE686_TYPE=1,C_PROBE687_TYPE=1,C_PROBE688_TYPE=1,C_PROBE689_TYPE=1,C_PROBE690_TYPE=1,C_PROBE691_TYPE=1,C_PROBE692_TYPE=1,C_PROBE693_TYPE=1,C_PROBE694_TYPE=1,C_PROBE695_TYPE=1,C_PROBE696_TYPE=1,C_PROBE697_TYPE=1,C_PROBE698_TYPE=1,C_PROBE699_TYPE=1,C_PROBE700_TYPE=1,C_PROBE701_TYPE=1,C_PROBE702_TYPE=1,C_PROBE703_TYPE=1,C_PROBE704_TYPE=1,C_PROBE705_TYPE=1,\\\nC_PROBE706_TYPE=1,C_PROBE707_TYPE=1,C_PROBE708_TYPE=1,C_PROBE709_TYPE=1,C_PROBE710_TYPE=1,C_PROBE711_TYPE=1,C_PROBE712_TYPE=1,C_PROBE713_TYPE=1,C_PROBE714_TYPE=1,C_PROBE715_TYPE=1,C_PROBE716_TYPE=1,C_PROBE717_TYPE=1,C_PROBE718_TYPE=1,C_PROBE719_TYPE=1,C_PROBE720_TYPE=1,C_PROBE721_TYPE=1,C_PROBE722_TYPE=1,C_PROBE723_TYPE=1,C_PROBE724_TYPE=1,C_PROBE725_TYPE=1,C_PROBE726_TYPE=1,C_PROBE727_TYPE=1,C_PROBE728_TYPE=1,C_PROBE729_TYPE=1,C_PROBE730_TYPE=1,C_PROBE731_TYPE=1,C_PROBE732_TYPE=1,C_PROBE733_TYPE=1,C_PROBE734_TYPE=1,C_PROBE735_TYPE=1,C_PROBE736_TYPE=1,C_PROBE737_TYPE=1,C_PROBE738_TYPE=1,C_PROBE739_TYPE=1,C_PROBE740_TYPE=1,C_PROBE741_TYPE=1,C_PROBE742_TYPE=1,C_PROBE743_TYPE=1,C_PROBE744_TYPE=1,C_PROBE745_TYPE=1,C_PROBE746_TYPE=1,C_PROBE747_TYPE=1,C_PROBE748_TYPE=1,C_PROBE749_TYPE=1,C_PROBE750_TYPE=1,C_PROBE751_TYPE=1,C_PROBE752_TYPE=1,C_PROBE753_TYPE=1,C_PROBE754_TYPE=1,C_PROBE755_TYPE=1,C_PROBE756_TYPE=1,C_PROBE757_TYPE=1,C_PROBE758_TYPE=1,C_PROBE759_TYPE=1,C_PROBE760_TYPE=1,C_PROBE761_TYPE=1,C_PROBE762_TYPE=1,C_PROBE763_TYPE=1,C_PROBE764_TYPE=1,C_PROBE765_TYPE=1,C_PROBE766_TYPE=1,C_PROBE767_TYPE=1,C_PROBE768_TYPE=1,C_PROBE769_TYPE=1,C_PROBE770_TYPE=1,C_PROBE771_TYPE=1,C_PROBE772_TYPE=1,C_PROBE773_TYPE=1,C_PROBE774_TYPE=1,C_PROBE775_TYPE=1,C_PROBE776_TYPE=1,C_PROBE777_TYPE=1,C_PROBE778_TYPE=1,C_PROBE779_TYPE=1,C_PROBE780_TYPE=1,C_PROBE781_TYPE=1,C_PROBE782_TYPE=1,C_PROBE783_TYPE=1,C_PROBE784_TYPE=1,C_PROBE785_TYPE=1,C_PROBE786_TYPE=1,C_PROBE787_TYPE=1,C_PROBE788_TYPE=1,C_PROBE789_TYPE=1,C_PROBE790_TYPE=1,C_PROBE791_TYPE=1,C_PROBE792_TYPE=1,C_PROBE793_TYPE=1,C_PROBE794_TYPE=1,C_PROBE795_TYPE=1,C_PROBE796_TYPE=1,C_PROBE797_TYPE=1,C_PROBE798_TYPE=1,C_PROBE799_TYPE=1,C_PROBE800_TYPE=1,C_PROBE801_TYPE=1,C_PROBE802_TYPE=1,C_PROBE803_TYPE=1,C_PROBE804_TYPE=1,C_PROBE805_TYPE=1,\\\nC_PROBE806_TYPE=1,C_PROBE807_TYPE=1,C_PROBE808_TYPE=1,C_PROBE809_TYPE=1,C_PROBE810_TYPE=1,C_PROBE811_TYPE=1,C_PROBE812_TYPE=1,C_PROBE813_TYPE=1,C_PROBE814_TYPE=1,C_PROBE815_TYPE=1,C_PROBE816_TYPE=1,C_PROBE817_TYPE=1,C_PROBE818_TYPE=1,C_PROBE819_TYPE=1,C_PROBE820_TYPE=1,C_PROBE821_TYPE=1,C_PROBE822_TYPE=1,C_PROBE823_TYPE=1,C_PROBE824_TYPE=1,C_PROBE825_TYPE=1,C_PROBE826_TYPE=1,C_PROBE827_TYPE=1,C_PROBE828_TYPE=1,C_PROBE829_TYPE=1,C_PROBE830_TYPE=1,C_PROBE831_TYPE=1,C_PROBE832_TYPE=1,C_PROBE833_TYPE=1,C_PROBE834_TYPE=1,C_PROBE835_TYPE=1,C_PROBE836_TYPE=1,C_PROBE837_TYPE=1,C_PROBE838_TYPE=1,C_PROBE839_TYPE=1,C_PROBE840_TYPE=1,C_PROBE841_TYPE=1,C_PROBE842_TYPE=1,C_PROBE843_TYPE=1,C_PROBE844_TYPE=1,C_PROBE845_TYPE=1,C_PROBE846_TYPE=1,C_PROBE847_TYPE=1,C_PROBE848_TYPE=1,C_PROBE849_TYPE=1,C_PROBE850_TYPE=1,C_PROBE851_TYPE=1,C_PROBE852_TYPE=1,C_PROBE853_TYPE=1,C_PROBE854_TYPE=1,C_PROBE855_TYPE=1,C_PROBE856_TYPE=1,C_PROBE857_TYPE=1,C_PROBE858_TYPE=1,C_PROBE859_TYPE=1,C_PROBE860_TYPE=1,C_PROBE861_TYPE=1,C_PROBE862_TYPE=1,C_PROBE863_TYPE=1,C_PROBE864_TYPE=1,C_PROBE865_TYPE=1,C_PROBE866_TYPE=1,C_PROBE867_TYPE=1,C_PROBE868_TYPE=1,C_PROBE869_TYPE=1,C_PROBE870_TYPE=1,C_PROBE871_TYPE=1,C_PROBE872_TYPE=1,C_PROBE873_TYPE=1,C_PROBE874_TYPE=1,C_PROBE875_TYPE=1,C_PROBE876_TYPE=1,C_PROBE877_TYPE=1,C_PROBE878_TYPE=1,C_PROBE879_TYPE=1,C_PROBE880_TYPE=1,C_PROBE881_TYPE=1,C_PROBE882_TYPE=1,C_PROBE883_TYPE=1,C_PROBE884_TYPE=1,C_PROBE885_TYPE=1,C_PROBE886_TYPE=1,C_PROBE887_TYPE=1,C_PROBE888_TYPE=1,C_PROBE889_TYPE=1,C_PROBE890_TYPE=1,C_PROBE891_TYPE=1,C_PROBE892_TYPE=1,C_PROBE893_TYPE=1,C_PROBE894_TYPE=1,C_PROBE895_TYPE=1,C_PROBE896_TYPE=1,C_PROBE897_TYPE=1,C_PROBE898_TYPE=1,C_PROBE899_TYPE=1,C_PROBE900_TYPE=1,C_PROBE901_TYPE=1,C_PROBE902_TYPE=1,C_PROBE903_TYPE=1,C_PROBE904_TYPE=1,C_PROBE905_TYPE=1,\\\nC_PROBE906_TYPE=1,C_PROBE907_TYPE=1,C_PROBE908_TYPE=1,C_PROBE909_TYPE=1,C_PROBE910_TYPE=1,C_PROBE911_TYPE=1,C_PROBE912_TYPE=1,C_PROBE913_TYPE=1,C_PROBE914_TYPE=1,C_PROBE915_TYPE=1,C_PROBE916_TYPE=1,C_PROBE917_TYPE=1,C_PROBE918_TYPE=1,C_PROBE919_TYPE=1,C_PROBE920_TYPE=1,C_PROBE921_TYPE=1,C_PROBE922_TYPE=1,C_PROBE923_TYPE=1,C_PROBE924_TYPE=1,C_PROBE925_TYPE=1,C_PROBE926_TYPE=1,C_PROBE927_TYPE=1,C_PROBE928_TYPE=1,C_PROBE929_TYPE=1,C_PROBE930_TYPE=1,C_PROBE931_TYPE=1,C_PROBE932_TYPE=1,C_PROBE933_TYPE=1,C_PROBE934_TYPE=1,C_PROBE935_TYPE=1,C_PROBE936_TYPE=1,C_PROBE937_TYPE=1,C_PROBE938_TYPE=1,C_PROBE939_TYPE=1,C_PROBE940_TYPE=1,C_PROBE941_TYPE=1,C_PROBE942_TYPE=1,C_PROBE943_TYPE=1,C_PROBE944_TYPE=1,C_PROBE945_TYPE=1,C_PROBE946_TYPE=1,C_PROBE947_TYPE=1,C_PROBE948_TYPE=1,C_PROBE949_TYPE=1,C_PROBE950_TYPE=1,C_PROBE951_TYPE=1,C_PROBE952_TYPE=1,C_PROBE953_TYPE=1,C_PROBE954_TYPE=1,C_PROBE955_TYPE=1,C_PROBE956_TYPE=1,C_PROBE957_TYPE=1,C_PROBE958_TYPE=1,C_PROBE959_TYPE=1,C_PROBE960_TYPE=1,C_PROBE961_TYPE=1,C_PROBE962_TYPE=1,C_PROBE963_TYPE=1,C_PROBE964_TYPE=1,C_PROBE965_TYPE=1,C_PROBE966_TYPE=1,C_PROBE967_TYPE=1,C_PROBE968_TYPE=1,C_PROBE969_TYPE=1,C_PROBE970_TYPE=1,C_PROBE971_TYPE=1,C_PROBE972_TYPE=1,C_PROBE973_TYPE=1,C_PROBE974_TYPE=1,C_PROBE975_TYPE=1,C_PROBE976_TYPE=1,C_PROBE977_TYPE=1,C_PROBE978_TYPE=1,C_PROBE979_TYPE=1,C_PROBE980_TYPE=1,C_PROBE981_TYPE=1,C_PROBE982_TYPE=1,C_PROBE983_TYPE=1,C_PROBE984_TYPE=1,C_PROBE985_TYPE=1,C_PROBE986_TYPE=1,C_PROBE987_TYPE=1,C_PROBE988_TYPE=1,C_PROBE989_TYPE=1,C_PROBE990_TYPE=1,C_PROBE991_TYPE=1,C_PROBE992_TYPE=1,C_PROBE993_TYPE=1,C_PROBE994_TYPE=1,C_PROBE995_TYPE=1,C_PROBE996_TYPE=1,C_PROBE997_TYPE=1,C_PROBE998_TYPE=1,C_PROBE999_TYPE=1,C_PROBE1000_TYPE=1,C_PROBE1001_TYPE=1,C_PROBE1002_TYPE=1,C_PROBE1003_TYPE=1,C_PROBE1004_TYPE=1,C_PROBE1005_TYPE=1,\\\nC_PROBE1006_TYPE=1,C_PROBE1007_TYPE=1,C_PROBE1008_TYPE=1,C_PROBE1009_TYPE=1,C_PROBE1010_TYPE=1,C_PROBE1011_TYPE=1,C_PROBE1012_TYPE=1,C_PROBE1013_TYPE=1,C_PROBE1014_TYPE=1,C_PROBE1015_TYPE=1,C_PROBE1016_TYPE=1,C_PROBE1017_TYPE=1,C_PROBE1018_TYPE=1,C_PROBE1019_TYPE=1,C_PROBE1020_TYPE=1,C_PROBE1021_TYPE=1,C_PROBE1022_TYPE=1,C_PROBE1023_TYPE=1}\" *)\n\nmodule ila_0 (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [63 : 0] probe1;\ninput [0 : 0] probe2;\ninput [0 : 0] probe3;\ninput [63 : 0] probe4;\ninput [0 : 0] probe5;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_11_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(6),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2020),\n.C_MINOR_VERSION(2),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(0),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(4),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH (32),\n.C_ILA_CLK_FREQ(2000000),\n.C_PROBE0_WIDTH(1),\n.C_PROBE1_WIDTH(64),\n.C_PROBE2_WIDTH(1),\n.C_PROBE3_WIDTH(1),\n.C_PROBE4_WIDTH(64),\n.C_PROBE5_WIDTH(1),\n.C_PROBE6_WIDTH(1),\n.C_PROBE7_WIDTH(1),\n.C_PROBE8_WIDTH(1),\n.C_PROBE9_WIDTH(1),\n.C_PROBE10_WIDTH(1),\n.C_PROBE11_WIDTH(1),\n.C_PROBE12_WIDTH(1),\n.C_PROBE13_WIDTH(1),\n.C_PROBE14_WIDTH(1),\n.C_PROBE15_WIDTH(1),\n.C_PROBE16_WIDTH(1),\n.C_PROBE17_WIDTH(1),\n.C_PROBE18_WIDTH(1),\n.C_PROBE19_WIDTH(1),\n.C_PROBE20_WIDTH(1),\n.C_PROBE21_WIDTH(1),\n.C_PROBE22_WIDTH(1),\n.C_PROBE23_WIDTH(1),\n.C_PROBE24_WIDTH(1),\n.C_PROBE25_WIDTH(1),\n.C_PROBE26_WIDTH(1),\n.C_PROBE27_WIDTH(1),\n.C_PROBE28_WIDTH(1),\n.C_PROBE29_WIDTH(1),\n.C_PROBE30_WIDTH(1),\n.C_PROBE31_WIDTH(1),\n.C_PROBE32_WIDTH(1),\n.C_PROBE33_WIDTH(1),\n.C_PROBE34_WIDTH(1),\n.C_PROBE35_WIDTH(1),\n.C_PROBE36_WIDTH(1),\n.C_PROBE37_WIDTH(1),\n.C_PROBE38_WIDTH(1),\n.C_PROBE39_WIDTH(1),\n.C_PROBE40_WIDTH(1),\n.C_PROBE41_WIDTH(1),\n.C_PROBE42_WIDTH(1),\n.C_PROBE43_WIDTH(1),\n.C_PROBE44_WIDTH(1),\n.C_PROBE45_WIDTH(1),\n.C_PROBE46_WIDTH(1),\n.C_PROBE47_WIDTH(1),\n.C_PROBE48_WIDTH(1),\n.C_PROBE49_WIDTH(1),\n.C_PROBE50_WIDTH(1),\n.C_PROBE51_WIDTH(1),\n.C_PROBE52_WIDTH(1),\n.C_PROBE53_WIDTH(1),\n.C_PROBE54_WIDTH(1),\n.C_PROBE55_WIDTH(1),\n.C_PROBE56_WIDTH(1),\n.C_PROBE57_WIDTH(1),\n.C_PROBE58_WIDTH(1),\n.C_PROBE59_WIDTH(1),\n.C_PROBE60_WIDTH(1),\n.C_PROBE61_WIDTH(1),\n.C_PROBE62_WIDTH(1),\n.C_PROBE63_WIDTH(1),\n.C_PROBE64_WIDTH(1),\n.C_PROBE65_WIDTH(1),\n.C_PROBE66_WIDTH(1),\n.C_PROBE67_WIDTH(1),\n.C_PROBE68_WIDTH(1),\n.C_PROBE69_WIDTH(1),\n.C_PROBE70_WIDTH(1),\n.C_PROBE71_WIDTH(1),\n.C_PROBE72_WIDTH(1),\n.C_PROBE73_WIDTH(1),\n.C_PROBE74_WIDTH(1),\n.C_PROBE75_WIDTH(1),\n.C_PROBE76_WIDTH(1),\n.C_PROBE77_WIDTH(1),\n.C_PROBE78_WIDTH(1),\n.C_PROBE79_WIDTH(1),\n.C_PROBE80_WIDTH(1),\n.C_PROBE81_WIDTH(1),\n.C_PROBE82_WIDTH(1),\n.C_PROBE83_WIDTH(1),\n.C_PROBE84_WIDTH(1),\n.C_PROBE85_WIDTH(1),\n.C_PROBE86_WIDTH(1),\n.C_PROBE87_WIDTH(1),\n.C_PROBE88_WIDTH(1),\n.C_PROBE89_WIDTH(1),\n.C_PROBE90_WIDTH(1),\n.C_PROBE91_WIDTH(1),\n.C_PROBE92_WIDTH(1),\n.C_PROBE93_WIDTH(1),\n.C_PROBE94_WIDTH(1),\n.C_PROBE95_WIDTH(1),\n.C_PROBE96_WIDTH(1),\n.C_PROBE97_WIDTH(1),\n.C_PROBE98_WIDTH(1),\n.C_PROBE99_WIDTH(1),\n.C_PROBE100_WIDTH(1),\n.C_PROBE101_WIDTH(1),\n.C_PROBE102_WIDTH(1),\n.C_PROBE103_WIDTH(1),\n.C_PROBE104_WIDTH(1),\n.C_PROBE105_WIDTH(1),\n.C_PROBE106_WIDTH(1),\n.C_PROBE107_WIDTH(1),\n.C_PROBE108_WIDTH(1),\n.C_PROBE109_WIDTH(1),\n.C_PROBE110_WIDTH(1),\n.C_PROBE111_WIDTH(1),\n.C_PROBE112_WIDTH(1),\n.C_PROBE113_WIDTH(1),\n.C_PROBE114_WIDTH(1),\n.C_PROBE115_WIDTH(1),\n.C_PROBE116_WIDTH(1),\n.C_PROBE117_WIDTH(1),\n.C_PROBE118_WIDTH(1),\n.C_PROBE119_WIDTH(1),\n.C_PROBE120_WIDTH(1),\n.C_PROBE121_WIDTH(1),\n.C_PROBE122_WIDTH(1),\n.C_PROBE123_WIDTH(1),\n.C_PROBE124_WIDTH(1),\n.C_PROBE125_WIDTH(1),\n.C_PROBE126_WIDTH(1),\n.C_PROBE127_WIDTH(1),\n.C_PROBE128_WIDTH(1),\n.C_PROBE129_WIDTH(1),\n.C_PROBE130_WIDTH(1),\n.C_PROBE131_WIDTH(1),\n.C_PROBE132_WIDTH(1),\n.C_PROBE133_WIDTH(1),\n.C_PROBE134_WIDTH(1),\n.C_PROBE135_WIDTH(1),\n.C_PROBE136_WIDTH(1),\n.C_PROBE137_WIDTH(1),\n.C_PROBE138_WIDTH(1),\n.C_PROBE139_WIDTH(1),\n.C_PROBE140_WIDTH(1),\n.C_PROBE141_WIDTH(1),\n.C_PROBE142_WIDTH(1),\n.C_PROBE143_WIDTH(1),\n.C_PROBE144_WIDTH(1),\n.C_PROBE145_WIDTH(1),\n.C_PROBE146_WIDTH(1),\n.C_PROBE147_WIDTH(1),\n.C_PROBE148_WIDTH(1),\n.C_PROBE149_WIDTH(1),\n.C_PROBE150_WIDTH(1),\n.C_PROBE151_WIDTH(1),\n.C_PROBE152_WIDTH(1),\n.C_PROBE153_WIDTH(1),\n.C_PROBE154_WIDTH(1),\n.C_PROBE155_WIDTH(1),\n.C_PROBE156_WIDTH(1),\n.C_PROBE157_WIDTH(1),\n.C_PROBE158_WIDTH(1),\n.C_PROBE159_WIDTH(1),\n.C_PROBE160_WIDTH(1),\n.C_PROBE161_WIDTH(1),\n.C_PROBE162_WIDTH(1),\n.C_PROBE163_WIDTH(1),\n.C_PROBE164_WIDTH(1),\n.C_PROBE165_WIDTH(1),\n.C_PROBE166_WIDTH(1),\n.C_PROBE167_WIDTH(1),\n.C_PROBE168_WIDTH(1),\n.C_PROBE169_WIDTH(1),\n.C_PROBE170_WIDTH(1),\n.C_PROBE171_WIDTH(1),\n.C_PROBE172_WIDTH(1),\n.C_PROBE173_WIDTH(1),\n.C_PROBE174_WIDTH(1),\n.C_PROBE175_WIDTH(1),\n.C_PROBE176_WIDTH(1),\n.C_PROBE177_WIDTH(1),\n.C_PROBE178_WIDTH(1),\n.C_PROBE179_WIDTH(1),\n.C_PROBE180_WIDTH(1),\n.C_PROBE181_WIDTH(1),\n.C_PROBE182_WIDTH(1),\n.C_PROBE183_WIDTH(1),\n.C_PROBE184_WIDTH(1),\n.C_PROBE185_WIDTH(1),\n.C_PROBE186_WIDTH(1),\n.C_PROBE187_WIDTH(1),\n.C_PROBE188_WIDTH(1),\n.C_PROBE189_WIDTH(1),\n.C_PROBE190_WIDTH(1),\n.C_PROBE191_WIDTH(1),\n.C_PROBE192_WIDTH(1),\n.C_PROBE193_WIDTH(1),\n.C_PROBE194_WIDTH(1),\n.C_PROBE195_WIDTH(1),\n.C_PROBE196_WIDTH(1),\n.C_PROBE197_WIDTH(1),\n.C_PROBE198_WIDTH(1),\n.C_PROBE199_WIDTH(1),\n.C_PROBE200_WIDTH(1),\n.C_PROBE201_WIDTH(1),\n.C_PROBE202_WIDTH(1),\n.C_PROBE203_WIDTH(1),\n.C_PROBE204_WIDTH(1),\n.C_PROBE205_WIDTH(1),\n.C_PROBE206_WIDTH(1),\n.C_PROBE207_WIDTH(1),\n.C_PROBE208_WIDTH(1),\n.C_PROBE209_WIDTH(1),\n.C_PROBE210_WIDTH(1),\n.C_PROBE211_WIDTH(1),\n.C_PROBE212_WIDTH(1),\n.C_PROBE213_WIDTH(1),\n.C_PROBE214_WIDTH(1),\n.C_PROBE215_WIDTH(1),\n.C_PROBE216_WIDTH(1),\n.C_PROBE217_WIDTH(1),\n.C_PROBE218_WIDTH(1),\n.C_PROBE219_WIDTH(1),\n.C_PROBE220_WI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_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT(1),\n.C_PROBE275_MU_CNT(1),\n.C_PROBE276_MU_CNT(1),\n.C_PROBE277_MU_CNT(1),\n.C_PROBE278_MU_CNT(1),\n.C_PROBE279_MU_CNT(1),\n.C_PROBE280_MU_CNT(1),\n.C_PROBE281_MU_CNT(1),\n.C_PROBE282_MU_CNT(1),\n.C_PROBE283_MU_CNT(1),\n.C_PROBE284_MU_CNT(1),\n.C_PROBE285_MU_CNT(1),\n.C_PROBE286_MU_CNT(1),\n.C_PROBE287_MU_CNT(1),\n.C_PROBE288_MU_CNT(1),\n.C_PROBE289_MU_CNT(1),\n.C_PROBE290_MU_CNT(1),\n.C_PROBE291_MU_CNT(1),\n.C_PROBE292_MU_CNT(1),\n.C_PROBE293_MU_CNT(1),\n.C_PROBE294_MU_CNT(1),\n.C_PROBE295_MU_CNT(1),\n.C_PROBE296_MU_CNT(1),\n.C_PROBE297_MU_CNT(1),\n.C_PROBE298_MU_CNT(1),\n.C_PROBE299_MU_CNT(1),\n.C_PROBE300_MU_CNT(1),\n.C_PROBE301_MU_CNT(1),\n.C_PROBE302_MU_CNT(1),\n.C_PROBE303_MU_CNT(1),\n.C_PROBE304_MU_CNT(1),\n.C_PROBE305_MU_CNT(1),\n.C_PROBE306_MU_CNT(1),\n.C_PROBE307_MU_CNT(1),\n.C_PROBE308_MU_CNT(1),\n.C_PROBE309_MU_CNT(1),\n.C_PROBE310_MU_CNT(1),\n.C_PROBE311_MU_CNT(1),\n.C_PROBE312_MU_CNT(1),\n.C_PROBE313_MU_CNT(1),\n.C_PROBE314_MU_CNT(1),\n.C_PROBE315_MU_CNT(1),\n.C_PROBE316_MU_CNT(1),\n.C_PROBE317_MU_CNT(1),\n.C_PROBE318_MU_CNT(1),\n.C_PROBE319_MU_CNT(1),\n.C_PROBE320_MU_CNT(1),\n.C_PROBE321_MU_CNT(1),\n.C_PROBE322_MU_CNT(1),\n.C_PROBE323_MU_CNT(1),\n.C_PROBE324_MU_CNT(1),\n.C_PROBE325_MU_CNT(1),\n.C_PROBE326_MU_CNT(1),\n.C_PROBE327_MU_CNT(1),\n.C_PROBE328_MU_CNT(1),\n.C_PROBE329_MU_CNT(1),\n.C_PROBE330_MU_CNT(1),\n.C_PROBE331_MU_CNT(1),\n.C_PROBE332_MU_CNT(1),\n.C_PROBE333_MU_CNT(1),\n.C_PROBE334_MU_CNT(1),\n.C_PROBE335_MU_CNT(1),\n.C_PROBE336_MU_CNT(1),\n.C_PROBE337_MU_CNT(1),\n.C_PROBE338_MU_CNT(1),\n.C_PROBE339_MU_CNT(1),\n.C_PROBE340_MU_CNT(1),\n.C_PROBE341_MU_CNT(1),\n.C_PROBE342_MU_CNT(1),\n.C_PROBE343_MU_CNT(1),\n.C_PROBE344_MU_CNT(1),\n.C_PROBE345_MU_CNT(1),\n.C_PROBE346_MU_CNT(1),\n.C_PROBE347_MU_CNT(1),\n.C_PROBE348_MU_CNT(1),\n.C_PROBE349_MU_CNT(1),\n.C_PROBE350_MU_CNT(1),\n.C_PROBE351_MU_CNT(1),\n.C_PROBE352_MU_CNT(1),\n.C_PROBE353_MU_CNT(1),\n.C_PROBE354_MU_CNT(1),\n.C_PROBE355_MU_CNT(1),\n.C_PROBE356_MU_CNT(1),\n.C_PROBE357_MU_CNT(1),\n.C_PROBE358_MU_CNT(1),\n.C_PROBE359_MU_CNT(1),\n.C_PROBE360_MU_CNT(1),\n.C_PROBE361_MU_CNT(1),\n.C_PROBE362_MU_CNT(1),\n.C_PROBE363_MU_CNT(1),\n.C_PROBE364_MU_CNT(1),\n.C_PROBE365_MU_CNT(1),\n.C_PROBE366_MU_CNT(1),\n.C_PROBE367_MU_CNT(1),\n.C_PROBE368_MU_CNT(1),\n.C_PROBE369_MU_CNT(1),\n.C_PROBE370_MU_CNT(1),\n.C_PROBE371_MU_CNT(1),\n.C_PROBE372_MU_CNT(1),\n.C_PROBE373_MU_CNT(1),\n.C_PROBE374_MU_CNT(1),\n.C_PROBE375_MU_CNT(1),\n.C_PROBE376_MU_CNT(1),\n.C_PROBE377_MU_CNT(1),\n.C_PROBE378_MU_CNT(1),\n.C_PROBE379_MU_CNT(1),\n.C_PROBE380_MU_CNT(1),\n.C_PROBE381_MU_CNT(1),\n.C_PROBE382_MU_CNT(1),\n.C_PROBE383_MU_CNT(1),\n.C_PROBE384_MU_CNT(1),\n.C_PROBE385_MU_CNT(1),\n.C_PROBE386_MU_CNT(1),\n.C_PROBE387_MU_CNT(1),\n.C_PROBE388_MU_CNT(1),\n.C_PROBE389_MU_CNT(1),\n.C_PROBE390_MU_CNT(1),\n.C_PROBE391_MU_CNT(1),\n.C_PROBE392_MU_CNT(1),\n.C_PROBE393_MU_CNT(1),\n.C_PROBE394_MU_CNT(1),\n.C_PROBE395_MU_CNT(1),\n.C_PROBE396_MU_CNT(1),\n.C_PROBE397_MU_CNT(1),\n.C_PROBE398_MU_CNT(1),\n.C_PROBE399_MU_CNT(1),\n.C_PROBE400_MU_CNT(1),\n.C_PROBE401_MU_CNT(1),\n.C_PROBE402_MU_CNT(1),\n.C_PROBE403_MU_CNT(1),\n.C_PROBE404_MU_CNT(1),\n.C_PROBE405_MU_CNT(1),\n.C_PROBE406_MU_CNT(1),\n.C_PROBE407_MU_CNT(1),\n.C_PROBE408_MU_CNT(1),\n.C_PROBE409_MU_CNT(1),\n.C_PROBE410_MU_CNT(1),\n.C_PROBE411_MU_CNT(1),\n.C_PROBE412_MU_CNT(1),\n.C_PROBE413_MU_CNT(1),\n.C_PROBE414_MU_CNT(1),\n.C_PROBE415_MU_CNT(1),\n.C_PROBE416_MU_CNT(1),\n.C_PROBE417_MU_CNT(1),\n.C_PROBE418_MU_CNT(1),\n.C_PROBE419_MU_CNT(1),\n.C_PROBE420_MU_CNT(1),\n.C_PROBE421_MU_CNT(1),\n.C_PROBE422_MU_CNT(1),\n.C_PROBE423_MU_CNT(1),\n.C_PROBE424_MU_CNT(1),\n.C_PROBE425_MU_CNT(1),\n.C_PROBE426_MU_CNT(1),\n.C_PROBE427_MU_CNT(1),\n.C_PROBE428_MU_CNT(1),\n.C_PROBE429_MU_CNT(1),\n.C_PROBE430_MU_CNT(1),\n.C_PROBE431_MU_CNT(1),\n.C_PROBE432_MU_CNT(1),\n.C_PROBE433_MU_CNT(1),\n.C_PROBE434_MU_CNT(1),\n.C_PROBE435_MU_CNT(1),\n.C_PROBE436_MU_CNT(1),\n.C_PROBE437_MU_CNT(1),\n.C_PROBE438_MU_CNT(1),\n.C_PROBE439_MU_CNT(1),\n.C_PROBE440_MU_CNT(1),\n.C_PROBE441_MU_CNT(1),\n.C_PROBE442_MU_CNT(1),\n.C_PROBE443_MU_CNT(1),\n.C_PROBE444_MU_CNT(1),\n.C_PROBE445_MU_CNT(1),\n.C_PROBE446_MU_CNT(1),\n.C_PROBE447_MU_CNT(1),\n.C_PROBE448_MU_CNT(1),\n.C_PROBE449_MU_CNT(1),\n.C_PROBE450_MU_CNT(1),\n.C_PROBE451_MU_CNT(1),\n.C_PROBE452_MU_CNT(1),\n.C_PROBE453_MU_CNT(1),\n.C_PROBE454_MU_CNT(1),\n.C_PROBE455_MU_CNT(1),\n.C_PROBE456_MU_CNT(1),\n.C_PROBE457_MU_CNT(1),\n.C_PROBE458_MU_CNT(1),\n.C_PROBE459_MU_CNT(1),\n.C_PROBE460_MU_CNT(1),\n.C_PROBE461_MU_CNT(1),\n.C_PROBE462_MU_CNT(1),\n.C_PROBE463_MU_CNT(1),\n.C_PROBE464_MU_CNT(1),\n.C_PROBE465_MU_CNT(1),\n.C_PROBE466_MU_CNT(1),\n.C_PROBE467_MU_CNT(1),\n.C_PROBE468_MU_CNT(1),\n.C_PROBE469_MU_CNT(1),\n.C_PROBE470_MU_CNT(1),\n.C_PROBE471_MU_CNT(1),\n.C_PROBE472_MU_CNT(1),\n.C_PROBE473_MU_CNT(1),\n.C_PROBE474_MU_CNT(1),\n.C_PROBE475_MU_CNT(1),\n.C_PROBE476_MU_CNT(1),\n.C_PROBE477_MU_CNT(1),\n.C_PROBE478_MU_CNT(1),\n.C_PROBE479_MU_CNT(1),\n.C_PROBE480_MU_CNT(1),\n.C_PROBE481_MU_CNT(1),\n.C_PROBE482_MU_CNT(1),\n.C_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1),\n.C_PROBE691_MU_CNT(1),\n.C_PROBE692_MU_CNT(1),\n.C_PROBE693_MU_CNT(1),\n.C_PROBE694_MU_CNT(1),\n.C_PROBE695_MU_CNT(1),\n.C_PROBE696_MU_CNT(1),\n.C_PROBE697_MU_CNT(1),\n.C_PROBE698_MU_CNT(1),\n.C_PROBE699_MU_CNT(1),\n.C_PROBE700_MU_CNT(1),\n.C_PROBE701_MU_CNT(1),\n.C_PROBE702_MU_CNT(1),\n.C_PROBE703_MU_CNT(1),\n.C_PROBE704_MU_CNT(1),\n.C_PROBE705_MU_CNT(1),\n.C_PROBE706_MU_CNT(1),\n.C_PROBE707_MU_CNT(1),\n.C_PROBE708_MU_CNT(1),\n.C_PROBE709_MU_CNT(1),\n.C_PROBE710_MU_CNT(1),\n.C_PROBE711_MU_CNT(1),\n.C_PROBE712_MU_CNT(1),\n.C_PROBE713_MU_CNT(1),\n.C_PROBE714_MU_CNT(1),\n.C_PROBE715_MU_CNT(1),\n.C_PROBE716_MU_CNT(1),\n.C_PROBE717_MU_CNT(1),\n.C_PROBE718_MU_CNT(1),\n.C_PROBE719_MU_CNT(1),\n.C_PROBE720_MU_CNT(1),\n.C_PROBE721_MU_CNT(1),\n.C_PROBE722_MU_CNT(1),\n.C_PROBE723_MU_CNT(1),\n.C_PROBE724_MU_CNT(1),\n.C_PROBE725_MU_CNT(1),\n.C_PROBE726_MU_CNT(1),\n.C_PROBE727_MU_CNT(1),\n.C_PROBE728_MU_CNT(1),\n.C_PROBE729_MU_CNT(1),\n.C_PROBE730_MU_CNT(1),\n.C_PROBE731_MU_CNT(1),\n.C_PROBE732_MU_CNT(1),\n.C_PROBE733_MU_CNT(1),\n.C_PROBE734_MU_CNT(1),\n.C_PROBE735_MU_CNT(1),\n.C_PROBE736_MU_CNT(1),\n.C_PROBE737_MU_CNT(1),\n.C_PROBE738_MU_CNT(1),\n.C_PROBE739_MU_CNT(1),\n.C_PROBE740_MU_CNT(1),\n.C_PROBE741_MU_CNT(1),\n.C_PROBE742_MU_CNT(1),\n.C_PROBE743_MU_CNT(1),\n.C_PROBE744_MU_CNT(1),\n.C_PROBE745_MU_CNT(1),\n.C_PROBE746_MU_CNT(1),\n.C_PROBE747_MU_CNT(1),\n.C_PROBE748_MU_CNT(1),\n.C_PROBE749_MU_CNT(1),\n.C_PROBE750_MU_CNT(1),\n.C_PROBE751_MU_CNT(1),\n.C_PROBE752_MU_CNT(1),\n.C_PROBE753_MU_CNT(1),\n.C_PROBE754_MU_CNT(1),\n.C_PROBE755_MU_CNT(1),\n.C_PROBE756_MU_CNT(1),\n.C_PROBE757_MU_CNT(1),\n.C_PROBE758_MU_CNT(1),\n.C_PROBE759_MU_CNT(1),\n.C_PROBE760_MU_CNT(1),\n.C_PROBE761_MU_CNT(1),\n.C_PROBE762_MU_CNT(1),\n.C_PROBE763_MU_CNT(1),\n.C_PROBE764_MU_CNT(1),\n.C_PROBE765_MU_CNT(1),\n.C_PROBE766_MU_CNT(1),\n.C_PROBE767_MU_CNT(1),\n.C_PROBE768_MU_CNT(1),\n.C_PROBE769_MU_CNT(1),\n.C_PROBE770_MU_CNT(1),\n.C_PROBE771_MU_CNT(1),\n.C_PROBE772_MU_CNT(1),\n.C_PROBE773_MU_CNT(1),\n.C_PROBE774_MU_CNT(1),\n.C_PROBE775_MU_CNT(1),\n.C_PROBE776_MU_CNT(1),\n.C_PROBE777_MU_CNT(1),\n.C_PROBE778_MU_CNT(1),\n.C_PROBE779_MU_CNT(1),\n.C_PROBE780_MU_CNT(1),\n.C_PROBE781_MU_CNT(1),\n.C_PROBE782_MU_CNT(1),\n.C_PROBE783_MU_CNT(1),\n.C_PROBE784_MU_CNT(1),\n.C_PROBE785_MU_CNT(1),\n.C_PROBE786_MU_CNT(1),\n.C_PROBE787_MU_CNT(1),\n.C_PROBE788_MU_CNT(1),\n.C_PROBE789_MU_CNT(1),\n.C_PROBE790_MU_CNT(1),\n.C_PROBE791_MU_CNT(1),\n.C_PROBE792_MU_CNT(1),\n.C_PROBE793_MU_CNT(1),\n.C_PROBE794_MU_CNT(1),\n.C_PROBE795_MU_CNT(1),\n.C_PROBE796_MU_CNT(1),\n.C_PROBE797_MU_CNT(1),\n.C_PROBE798_MU_CNT(1),\n.C_PROBE799_MU_CNT(1),\n.C_PROBE800_MU_CNT(1),\n.C_PROBE801_MU_CNT(1),\n.C_PROBE802_MU_CNT(1),\n.C_PROBE803_MU_CNT(1),\n.C_PROBE804_MU_CNT(1),\n.C_PROBE805_MU_CNT(1),\n.C_PROBE806_MU_CNT(1),\n.C_PROBE807_MU_CNT(1),\n.C_PROBE808_MU_CNT(1),\n.C_PROBE809_MU_CNT(1),\n.C_PROBE810_MU_CNT(1),\n.C_PROBE811_MU_CNT(1),\n.C_PROBE812_MU_CNT(1),\n.C_PROBE813_MU_CNT(1),\n.C_PROBE814_MU_CNT(1),\n.C_PROBE815_MU_CNT(1),\n.C_PROBE816_MU_CNT(1),\n.C_PROBE817_MU_CNT(1),\n.C_PROBE818_MU_CNT(1),\n.C_PROBE819_MU_CNT(1),\n.C_PROBE820_MU_CNT(1),\n.C_PROBE821_MU_CNT(1),\n.C_PROBE822_MU_CNT(1),\n.C_PROBE823_MU_CNT(1),\n.C_PROBE824_MU_CNT(1),\n.C_PROBE825_MU_CNT(1),\n.C_PROBE826_MU_CNT(1),\n.C_PROBE827_MU_CNT(1),\n.C_PROBE828_MU_CNT(1),\n.C_PROBE829_MU_CNT(1),\n.C_PROBE830_MU_CNT(1),\n.C_PROBE831_MU_CNT(1),\n.C_PROBE832_MU_CNT(1),\n.C_PROBE833_MU_CNT(1),\n.C_PROBE834_MU_CNT(1),\n.C_PROBE835_MU_CNT(1),\n.C_PROBE836_MU_CNT(1),\n.C_PROBE837_MU_CNT(1),\n.C_PROBE838_MU_CNT(1),\n.C_PROBE839_MU_CNT(1),\n.C_PROBE840_MU_CNT(1),\n.C_PROBE841_MU_CNT(1),\n.C_PROBE842_MU_CNT(1),\n.C_PROBE843_MU_CNT(1),\n.C_PROBE844_MU_CNT(1),\n.C_PROBE845_MU_CNT(1),\n.C_PROBE846_MU_CNT(1),\n.C_PROBE847_MU_CNT(1),\n.C_PROBE848_MU_CNT(1),\n.C_PROBE849_MU_CNT(1),\n.C_PROBE850_MU_CNT(1),\n.C_PROBE851_MU_CNT(1),\n.C_PROBE852_MU_CNT(1),\n.C_PROBE853_MU_CNT(1),\n.C_PROBE854_MU_CNT(1),\n.C_PROBE855_MU_CNT(1),\n.C_PROBE856_MU_CNT(1),\n.C_PROBE857_MU_CNT(1),\n.C_PROBE858_MU_CNT(1),\n.C_PROBE859_MU_CNT(1),\n.C_PROBE860_MU_CNT(1),\n.C_PROBE861_MU_CNT(1),\n.C_PROBE862_MU_CNT(1),\n.C_PROBE863_MU_CNT(1),\n.C_PROBE864_MU_CNT(1),\n.C_PROBE865_MU_CNT(1),\n.C_PROBE866_MU_CNT(1),\n.C_PROBE867_MU_CNT(1),\n.C_PROBE868_MU_CNT(1),\n.C_PROBE869_MU_CNT(1),\n.C_PROBE870_MU_CNT(1),\n.C_PROBE871_MU_CNT(1),\n.C_PROBE872_MU_CNT(1),\n.C_PROBE873_MU_CNT(1),\n.C_PROBE874_MU_CNT(1),\n.C_PROBE875_MU_CNT(1),\n.C_PROBE876_MU_CNT(1),\n.C_PROBE877_MU_CNT(1),\n.C_PROBE878_MU_CNT(1),\n.C_PROBE879_MU_CNT(1),\n.C_PROBE880_MU_CNT(1),\n.C_PROBE881_MU_CNT(1),\n.C_PROBE882_MU_CNT(1),\n.C_PROBE883_MU_CNT(1),\n.C_PROBE884_MU_CNT(1),\n.C_PROBE885_MU_CNT(1),\n.C_PROBE886_MU_CNT(1),\n.C_PROBE887_MU_CNT(1),\n.C_PROBE888_MU_CNT(1),\n.C_PROBE889_MU_CNT(1),\n.C_PROBE890_MU_CNT(1),\n.C_PROBE891_MU_CNT(1),\n.C_PROBE892_MU_CNT(1),\n.C_PROBE893_MU_CNT(1),\n.C_PROBE894_MU_CNT(1),\n.C_PROBE895_MU_CNT(1),\n.C_PROBE896_MU_CNT(1),\n.C_PROBE897_MU_CNT(1),\n.C_PROBE898_MU_CNT(1),\n.C_PROBE899_MU_CNT(1),\n.C_PROBE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synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4251}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nXvoWuyjysN5V55U4xsjyWg2bXI++8I1KAZgJ0eiQkY3L8ns1PfNti9fujmr8wvFQA6ycwh4K6mSp\nINQjc8TyLQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nbD05I2IKef08FLVG4C2ftkJOY+/UsvagxY6ta+A0N1USwLQivKTmRt7LJlQ+5UJqrfPvhHMyYrLN\nrjoJbClg85XfNTYCnalRVvg3mmCcjtJkCLf6S5E9Q6UF92b6bwgtMTsr0BndJhdItlJtr0dYZtoP\nAEskMBthh6RdNMkZ3CA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nvLo4Yp/zX6HvZ92VMA2Xr4EIhMWPNGq2EvSBkjiZd5sCSFAX+37MKx4gdbrsGvhUMl1njqvSaoP7\nKrAa29/cm3QWjPgpaCsR/MhnaG5+7aUvxA5iCqVHXdriMlgx9kzxkB9SD+mOC8XR5LtYA0bPhbZ9\njQzWpWxdaOGYFF25DU0O9M7LMc7SLfKunYH/cQ91D37m0LjgZh1/uZv8chFzvCBbkHqUU0qi17/k\nZTWIIzqb1oycbuhZZrWLl95xQ/aaTxZ30sONWd/axZtO3Cd57huCbCxLuOH51qq6erD9AVszmxL8\noEoM+KW88P1S3LJ/EcIQN4LU0/nyN/f7xEmy2w==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nj99ihkoCqIO9DhRZEJdEqlRF2P+IwS2wuYmoh3hWFCDXbmGTwTqc+3EMjxY8Z4uDixuazjlTMiEH\nCk4MdTkVZ55pPhFb4druHTap3Twn20B3SWvOy2nf84OpTkdBnbK4qagABgZXs9/mAtQxbF++/F6Y\n+OOE3yUNTWvHiVGvpTJavfADkB2CL5wEIlBSnYRwtLp71JokDsMvjq2l3o3hxAjvtdg9ej7NKx4I\nkAZfrpZH7Ebv2hfXrTVI2kDTAl5Etr+4oSqxIhABJut2WaeWJrsSbL+dz9s2ZmYDMb1BCQdRexck\nbMMvUaS+P7sSGuR9BTVynHOY5GdQelHO1aazQw==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nHuzbd0U90PuPKn40554Cnki98HuQSq7dg6ZyXufEWFHsji6rteNupAY3HQsuLpXjFVxsNlS4bcHj\nAAOnDcL0hCCVbSkU011mqhhlkFmWqeBBECGfP+T7/+l9KBu+9ynszhlhaVhmZMffsEuohDl5x084\nFnzFCdxrFyvqrOyWDac=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\neoQKmSsNWNEOJcUApe0UhUNGRDkxOLedPbjyDILgUJWMG+WVCpL9MC2MXZeZ6/oVwAYRlZTZsF1h\nUsVo6BO7IAuHuJAHeIQgEs2oIMj/I2qZxm9wUsOzWoK5/Jz4SS4sTE3TgOJXaX1GNAJlbUrCBtnM\nqIiavU164vZjX5BFoPGuHp4kICN8A4Wr9y2w2Lh0/IdiHjr/Ruk5PpVNyl7tW9EaSFY1AL4aoQpd\nRFDdUFRk4tMBtmFxi/B+pLVFE0hAUZnlVCsSaf4B0lN/m4CME7lgy7oXElp7ov4fMnD9VI8HLGMX\nWBSQjD8F6BB0Wblgm9lJNc0h0VqxxD4DbRleKA==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nyrn0K+G4SU1wuMdE7DJlKWErX/N5nCqD3+dP+4ONmo8yuM983VHfjLhCoeQMbM26e49U4PPdXcDR\ny0rRemqJACoi5H5NvzXohhKZI9q+WKME4TkhFzfKvIwyta1m/uNSe/A0+52Dzbg5uAxYihw0IdZR\nZMywfa3deZ8IUMz3kWSlMs1P4wESz2pKpdYGs0FpvovucuNn4OhZKH7RGX8z8Zy4E9juZRgnSQnX\nmvRtisgVB9uL2J0vl9XjW/1990VYZi0nrZJ8gQL38HLTz62vDuMuYjiFbbnDCujJNKOCHh/xJTdt\n73nsz+dY3We4tQdnxuESibzLQLGF1l8+d9FPDA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nJPIGH1v6BG8bvo+3pHrWlum+XEDtFDlKP+4Toq88+g/eeinS/p8A0zMVVYj4wfjGDhx3kGvJ9XAx\ngxYpezvlgnz+IEGWQzepCMSp4iHz9TEdGkc5LTQj50VJj4+HGz2Qhrw96Hw0c+5RDrv238ILy3p7\nuzIPIzxKEl8D7gK6b8ZPrzx95KMPuGZyju4JUHBWdjDx0hhhIl+L3Ju/bVyWaWd7w1xI0mreJtAN\noOdcObOESJpTuj0KqFtfA3UY7v9n9Lj/I/vMaPX7LnSIZuS+tHyiD8D+t+Kf6XiIl3sYDL9erP7t\nSpHvPfG9bOfGRxM7dmsvKj+XqHeXg23wyS1Nfg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nrxmK0sxFw5opGoAsi+RHBRwE0wYNls8LL+oURMgLNuoRDOPNH7up4F86jASnrdlvXLShGHMZnaJ6\ny1orZ0uAZ6xxM2PeKAxvxBI02HOu0aXd/SMNxr16dADlCYK6R1DVdq3DC+T8bQTLWyyHr9r4m4En\nW5DcJ2hEs5b31PUg/DoCNTpHm2swT7sLG9qRkSfTddaSyGTADcvRXYjnHKHin6TQlOCZufWMm54P\nPJeCQmj1MjyycQGpsvFNX7VMxW49ashO7EGmRdy7lMGRoHDqLWBxcIlwAS4L28iuln/NdC/QV538\nQei7EbcqeUmfs07XP8FKxdA3hi3Aq2Upg9DkOw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64736)\n`pragma protect data_block\npJdOORWQloxSGvgvy0l4tBp1HqnYdonsYgNOe99SLH3qi9BP+2tNlaoelqmLJLSHNsBn3TJxXlZa\nnIZxc0/l2jA1h9Jz15QEEgUR0MqZaESeIPQdEbADnul6xUXY0J6g//n8Vnzph99nb1v9j4yp0I8W\nmF2Bvdz/qHJcUcV5zedPk5PkPVS8cmwYFQWer3rOMl6Or1E/YoHi9T9wfbgxxTs6yzqYqVGUBlz5\nAlhSoRF+xXB1Z4h2Ny4v4u05pGtbpnnDj+JhauZ7AfT+uRL3JZ7hNdSiI3coyNU077RtI/1VAmYO\npJoj/3tO2z4y9phvRShE/Otch4qxfx53IywqoRQmUF57yV4NjbkGPW8j7U6iQ8Ls1911ZAOgZIga\nmynl1jCs8ajbsNdraT0wfsPf1kWJOCuUGyItYv2eEwfh7iEYRrpT0V6YT5gENAgDuriQCZuFtnJE\ndhvImjwTXy3d76buWun43bM5pyUNSUzm90uucXHtbfsv8HZTM/chDluZJ4cMeW8D9Pwjtvo6lXLx\nYJM6v2cUpOTIMOcKDxrRTFomRQ1DwRsa4wQGal4q2dhrokLR6YNhu1ED6+AbEAN+FWui25yRPN2c\nRifAbYj3+oa+z6kUON22gegvkiRIe3iVn5MeyImok+P+5dmykiOW6L7J+GDFd4UZtYwJkwUH4ijt\ny9tlvkg7bhgKKY/VRht7EZFg6U4GjUBwLTEWIsD/6R8LgyENKTNO1FVyOJge9+hJYOxJpk93nMac\n0dR2cl0TLESIEfZQ8wSlqKcnzibNa/Mwa+gyj8uNmBtlGMv9GLnh914fnVrJPaJYjkLNLesy5uKF\nWOOHFhlsuqMHkybog57X/W2y+bzzdtaWoQ8/DU/QWGyTt3Vhlmu4YBKvv/DBB51RUj7naprx+CNR\nK7/l3uoheqcD/zy4ipVqZ/mSOTxjqNwJ88tpKUTD7UHuLf8rEeiu80iR1raYJGMHzUS7FcK/APPf\nbBCJIKpjoq1C63MJYurbOeqWcRL3DDPi/z3C66E9WG/nFKs7vMkhbVhClFUAjy+DwMCS7VjbvUvn\nCbr4m+kTXY7ipbBxU7YIDWHssBAAjeM1Rdxx9VvDqABN+rFZAA7C08PNPUeOiVYCFO3gmbAqYK8f\nEPeBaPUk6eskVX2sXw5/qrh1a5mqGk/sYCFZItuYZ6SMz1BFuaZz+ac8Feq8+d7gH2f1DuK4EG20\nOgLh0liUdRk5TCUZsSZTlhRd1FA4SqglWHYk+GIL1WEcVBskAEiY2YIK1TGXzUQaG00TT5TRBNmv\nsPnVI8z6bWwqXomyqcYSelXrfl2izqtjadlA+3+0O2A1XhL9tmMhT3v0nQIlobxn4nFE376czv08\n2+xLHI/chXlg2WvKMK3NCBbWGw7tnHSdJc47JRdiCkb0tIr9wocUbWPbM7W5G3Ku+bQZQXPM0lNy\nstFAjwukEDL4vbC72EJbEwf+6kzkzLjBrc0JDEzvjqnYQYiwloQ0qi9k/yE3bXcnEHvgw8ig5Y/S\nt9SttzL9mNMXwbouRg1seAZ89RrLrTNZiBk2TlhzdIfvWsbvdBYdIhaMqKRGJFpWxZgPm+JbW+09\nfF1z2nf/18EW+WziUuICezISE4+2HDfqFOEltKV6AdesQWDrloYiby+MezSSORPfWkx+nVGv8JEs\nI01podsuoWFRpVmbt/Dua5qZk9EOHGFBRgvYNnlH47YVREn5j8l2T/0bBlGUrv4r0tmSTvb5Rk62\nTtYvXt/3/jJe7TX05O4Uz8CDBe02LhhwyNkyyNYPm6hcqislaGMW5IrlUBR19xoKivY5xsi9WHEp\nOscK7GlXBFf+1ZdqPUIFBzo8CoanS+vY6N5dX/zhH9ka7wSGlru7qjqAyYG3VOzYi+lIUT1D0l0A\nhIuLJhQlgGIPioPMX5r9G+nJX9J1xhmQmslUobJCrtsIfoshA1m3sO8FVq/uKShEPK85uU48DmE1\nBM73G3APR/Pn3q4udJagFjB+ngJWARXqQX1U/fZdrs1d4U8E/KLlkVQywLtM4ImADW15ZRE2zwbt\n93vD21KzRF0gTEp32+Y94DZJmilvEITUz6i6Uf3GIhk/8VlW2sgoZBxyIXdlfZU0hAeWoF6z0y8i\nsz3YJBSL59bOXPeovsUY+1K4JWkThiLh9WlHMd3YfANHBPnf+imIQZm0bk8SniIn386MI5OOzHz4\nE4NRinoFBZ2QveSs8W7mDkgRcm6PoFPVY3QRUGVKM/cdavafi55CMHzsrvtIU+GTn9VIn3xNt55T\nvun82PwGiZ2FiwhlNlG8Wy4O+LFNA76IijNkkamPOoINY3NpvBlYJ4sMSw1dZ/S+Qd509gN+YqK/\njuugLi10dq5ezC717GDkCW4fL6XMF1BLctfTjFHbDnQePKJIiB57aUuvbzah60QCKQnwYsO2mNs3\nlX8Tl9YL68F88dwoxH0JclrQ/K+4uYuofKZNpcUqyesWLZ7Ajkjo1V/LWCNdqLb7jaE2Z0v+PGsJ\nbQ2zY2rbw1xVbkOFkWnJb00IZlS5AfKLW2JwtTjSc9R5cytj7Kj8rVyPRdWixjwHVXwb9oIhCtsZ\nr9zdlcsnNvnrEk8HWDJmg9t+Ss3qdeobuZBvC1qVhW9OeCSeLWFmmlBTM7zlf4bIM7BPobwINrOH\na+x81+t4Xk/8bAWK5b1pfO/q6usi0t9Z1NTJb3ix47MRkhAbStRfFBfBwzDQr/YBXixPzFiRd7RK\nKHM5pI4NGo4x/1eUa3I9iGFb0JwOlvTvmyLF4CY35sdztuKueaGq0YUi4X3SbBVUihPbcPvhcn3q\nULcb1JlytkOdtyHtyrm7/EOiSLmMn3uCPXQDioYj1f6NsIRA8BV+t4V5VK8a2hNJ+Ci6U9tBmG7R\n2AfVDNWXakk0eYIUYcZuIPVd4sH7Be8PANt6YH+bxeZtBfUel13RoATsMc/l+Vz7BvaZ9ZhPoxu0\nMpG5BKJTAuGZ3OqNXDuuvsvuBv8s5hC8JKvLoL76k+rFk8PlyNwEnYoc7nFhCrqDHeOr/8E3maxP\nPv/AiEhEzjU5PQBF457AHnjeQ3eTwpDPSnYJ6nuR0WhnaxbVcRDXmfQc5Pm+RgJOQXySVRlfAtO/\nJmM8oWf9Wd57qYf2P95KvohDPW6vlFW5UOuYJRNedw/Vofmtj6gUXmSUtZzX9x+pGUbZK1L7qaRH\n4Bl+RKLFFF3ULv72pe+uhZoyumhCUE9nTUfh/0bbyfQ0/7E4OjNceJy3IuQXZAelpm4/lyIClM6a\nbcA7XaiUNtUxRgOk+Gm4bXDK/lbpfHAo3ZLrOeIIrJSFdGgfIjMAMcPO2agXDXysM9w0LXX4XzKa\nAk5Ctu+YxqwaE3xbxVfqa3Xiwxzu9RezCh2I21Ysg1ckJugmX+s7525qUeaUizKlxcu5ef5xX40W\nh5pW3QA7UPCugDISw+aX406IO2drov2E5eUNDLRRG/nY7aG606JFGCFgUNVLl22BloATVP6ZeMDr\nmifoHBORyaJvgAndCrygYyJGcy9labne+Cqn0A1qtn323sFNB43FEMX42WIgtgc4oPab1AYsEQum\ns46nWTCUaZAyRO+53Dzben+MOJEy1iKP7o1PMZDKjaQ4Atrpot1Ix9OivbbWL8nNOjFG3rRgc8Tf\nLOVtiwqq/r+IiSB/HQOV/ZHmkDTL9dtw3UFvBE6wRo6XaWDbKDi/T7PaYAC3GGNaQZw3CTXVFb6P\nSvTMYdICAhD7YCZDr6aVLiD1Mgc225aXecHZoluSWOck9HO5ezjlCFCPDSTSj5OnC9v9zUcFbNOa\nri/TT7JdgqdBMKQjvpVrljLeuPPWvSxLMEar6iv8iFwj9w4fIGsSX5D1h0fx53Dosj7c99OjPOKJ\n43ciuUlKmUrl8zGTv1bTsvgQBspvbQjDlKlZcFGKkJ5y+h+FKT7sLG0T7X0OsNyJhlkV8Oh1B7s0\nnzc4JG92kvRVvDmVljLF5q7kSbo4pOg+r9MMh209JANj1imzsRTwNlFhL4KQmOy32YKv975WzfpE\n5gOHTY5gj/9beHVy72SphX1PvZ/GvMrFHu0Q1SdMOxiDJO/8Vv+UogST5Z+pm6YS50RKp917SJLr\npQGNrqMBt2q0TjdKoF10330Oq2OQnGbPQBcF5wAOKor3lUhuKlgi4yfTsE7g0RlphaWiUi0kfQnJ\nxJaR/v3zWkal8YKuqBUOk2zAI58JgLOCGfkeP4lLDigas6lR86dIFm2ehEwWiuUxA0rMWk7MxUFq\nIvlNP2JTSuRX5d7mSS5TdZoich5Z28tzuAxtmfX/HVgsAiDJsXeq2lNJnPI4t7OJcjw+/LTBFn4u\nGkaeVQKsrDg0XjypHHAcx3Htai3F8S3SrSZThLhmNA0UuPAVwrWM/YxdRJdPCFxRV9DIfFLc78ED\nrxRf+2hm2iIX0v9lJubvukxj3RKg3bWedHf9X7fBwzCzmT3xpSVT/orUQHTM7BJi1uX619EAPHfH\nEslFnO9xBhBE/NfxEOIr6puKJWQy0vcdu3KHp/98gdYKgnVg5mCXI4uGSJL+j3Mo34LyWj6jofG1\nRpvUjZOY2WsTY2U7akBl0Uyiv66vuAVFTYtHxbLeKihdYSSxteod2tWquqRvLeBirXL2qi69vijg\n+WXGPNEs1ioW+W6cjl9Kt1V92qIp1LbqTEC9jDdj5VHq36eM3zGGY1FX+VH47w4FoxWcrGaGXkXO\nhGXHGyLwe6ssZ273qYR1N0RhvtgHnAdUHIPdsqqRbjeld0f7uZDVEUjGCA5HvEPmaA4qaz1HEmEX\nMSbcEbGOwM4/lsTSso35cqWlqf9VepPPahniUNw1bY7j79iM/o0F8kJkfL5NumCR5VM7RsWuHT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C99kqfj/UVOTB5eheZdHy7EcqBeNR/+6GsibmPncbobTk24qcaqVJt3wgZyWp0s45X+9wMv8\naq7nxbvk+JD5cuPi785YB4Is1gg85t6bvpA9Qfzb3O9Wk32ecemuYY7hfv+wXPcCciMC61K8t1VJ\nDxofEz9Nxh0L6M2gdZhrIeECMYqp9YunMryNLeqc7YQLvKIjonC1l4sbrYWZ+Vr/tRAksYUVxldM\nWs7rdbIReyHwkW9Q3eVk5tGNZYwsTJZ3LLHqX4k4QW4fN5SrXF7tpu0Nh6B20X5kbA57dL9bI0Mg\ngdCKLlB0s2kqOmSFFGQ2qiGM4gLCtJKTcJvH0QXyq3PoTYgnvqWXAi7962ulHUUvjiqAbTLGRYQR\ngd6pRfridQ9QkVVZ3q8/Wwg9RSEsbZuIJ9bsY3KxRk+Bv/QJmfbw9otM2ufRS79SLoJDUzayREpA\nzPDRjhDoGxRqrI6rV3uPDIkmG/IgiRjrOM3CMltuf+l5zCRv72lm/BooJKYufHaSMAUyCUXJp/Uc\nFu0s9YVH+QVUDZtdn/t+XoUZ1zviEEgoAEoY2VYry4fCJ8DYaSDlP46tShiJjQrOJdERGgL/xQBx\nO6uzJrNrt7Cf6kh0YFyp6QRAfTkuf7kwETESQMUFV2MR8wr0hZHmd/UBOQiPTPb8DscsuSAYh8Zc\nrknuK0zKex9YiHkZeDo7D/PSeuh+WG2d2zJdkM3Td3eMS6WVDFMFl2b5W8/jYjNABrnjK1XwThFh\nYLnSLJi/Op7SthgN17FwYwSwj+AcsR63hVzcnfiVu3ZUXHEZJEyz2HWtWt0RLaZ7MNZccAta93yH\ngOMoJdpfeYUKCCFDGcTyJlFegiSY/R9BWXq/NR5ouF0kpaoEUa+kWjoHoOiSEaQs4XEhSuNjRynD\nrVhVZzcmzBTJAU/E9/o/Hq/uvAStcm39QbP3OeAuNYGNe3sCFCFik9NxiyTW3OEmJSjBcrOnO+Qw\nx7FcS9UJ/wQfURM4P12Z7osL0N6s5Am8NipjMtQyeAtwOcmnJoNC+0+NUiyPWlCuXP/3Z4arSgFa\nZR7xsOv//tsF4wlUna5iH3TC56YNk8nUsFEw6Ge6ZSuhEVsfIeY4wG2IxxjFm7GLEm+Qi2fnWvFp\nirwOxF+K+U92WcMWV9jGmnuJKdDgr9f0rTsSnyJoE6abD5qCwAUSiMOFTLyqf0omOu5SrdwPvxDF\ndftrQ5R+oqkHgkZje/QojcIA5MmPjkCLRdKv8Qe8et8c4lmY6vRi/j86jriaKSwx4Y+Mw85SnPR2\n2j1hg4L1bm3Y95mODLr49QGkDVB7kvY4Qy33Bsp2CTuOWo05KgZSEEXL/7U+fWGzRHjASwfcbgCg\niVFHnASo+4H+F8SItbh9vW9aZB7dvzb/sp41V3sOiSQ/lvFv36hNky3d5TPRgeWxk7ahEnAeBvcU\nN36JNzslIJ0QcFbUJcrGjbreKWGwtRudHbvZZiy3VBuJefbL+K/nA5GKYex5vaF8VvW2JtNaz6nG\nO2mf0K1OaIC26ble9NY9pYrqytCcdTpOisFBK/sWMwJTDavyPDcaK3b2r0z6l8yWe/+kZORkwM1n\n+vS+mBxXx0tf6GtBwKVn9Wq5PBEpboQb7z+jnDgqEVQGEQk44+zDxF6mTiYHaVCLhGP1x2L8Qxtw\nPkf1ixuZGNM5w3J6JjwoYA1WqjGzNXQ/2I4IFQ7+zOL2BVVm8a+5aGNvBOtcu4B12kHIJpqjtEJq\n3tU1eussVADMAsGVV8uDeYtJPvulbF/idSwsgG8crk6BAOKJo99VQxAzmHr6hzse35prsun1dsY+\ntbANM8RyL4weuRCRdH+gaMfEFjRTXyRtKzs19VCSRxpLGUewvAFPajZ9ighUQ2DOA7Kr/rcMTxxd\nrh6hpvfsAFBAQjLiKMsH8ZMXPqNGDBjA8s7TGxd1KmM66Kj1RfzFBtlBuz9LglC/dRn/arEJkYKW\ngOxCUP9SwP1tqpMfyCFKkHci/RYZqmjbNlLH12cl5zMhmsQpiIcZXYfQL8enrVutyHkc8Oplycxn\njTecEx2W4yyRww+b9SpNrQwNcQAZHfUmu5afg1rtbUHZmBW//Afpurxew4MlsTVbE/q+GW4sYS08\n5hT4/ITaA2T979WNydM1h2SItDPecKYro2NCBuNGPCj2smuGGwIqTTedt7kY0lTXqc1QprlIXDOv\n7A/WEW6Ks/DyDbzo5ebBQ9k/Or/ERzVfh5qWgkq8yG0qonueIlbVexyJM/7sKO/BjOR3x/FKDD5A\nPOch29mk1tOqyzjUVo2fdU4B2P5yIWUu4LyA1+iW0TzGEcAlb+9A3LJHWtdxf5XRYSDst39xRNq/\njlN38Ihbn61REmPKmA+LoB8LUMaREXZsyBT2mkJjbCqOmNANgzEAOIj9ceuS25Y2KtrSdejGBdIE\nvCBEfvsJHNzt4EujHKaeJh7o4NDjqLcdEp7ed4Ep3cSOHMCOA874EICbE2zaW5mDE8TG62+kJMaF\nV28mlwI5fMFxipXSTKgVDY4Vj5EWSGuC9St7IfruwsQ039cqwvbAOIuBDwEDSJc6lCmXs/qZhmZt\nnFv7j6yW+vhyh9F/M49mYXMIrZDI2IQn1meVK5DQbu4ISFnSDGJl+UGx+F0w292X7x/NZlrDFxjU\n8F8hH3SoFUjtp3cdqR6J0qgyyvNuJIK0pC2nq9IzjvH1k+PjKgFH3e23kG7suulbVb/rfU+4p0A0\nUw/8qfFdt9ZBcVINnpEPSUJScU20uwWwAzXtPblYceO4Nbetd/Rru6gMmzl4QBV6dHDFv9Llj35m\nrcJlg8L6gZdUkbc5dWUef9LywyJ3ifFwzOukFPVGj0p1G9hRSiNUqdgpYFlexuLPL30vERjJltwu\nf4LrTIZ2VSuuoDz3yvK7YYnre2MTp1IvJIRPF0FnWr5WUuDhARBzNlManehpegpS4ik+5bBOARnk\n2ikf25Ea+euX4IRwUJwiPzAGTUbPzL3cODFaJ4mHcPv972AeFd1T3djc/nkOpMRfzLbUHz1h++GZ\nfguK3eWFxgEnwvmTBOSV/2pqlydJB+j2kzDoBOhHJ7yMYPINzLTm+GvY8+PE6TGpMumpLB79DVsR\nwtH293Qaqs60uwABd29zk+xMrOUEivDU8FIBU3QFpa33/+/A4nI1MVfVSHknip/yEcpuNY2qPJsT\nYuN68cBSWDFeSQJE5yXwjpRVFkSAHd8nML/bKhBZiplgzijzI6AXJOmkqclzuE3gbvl06XzNvh5g\niwbchkuC2q85hHpT3w63G6WwlR9OlnKpzSBsWJI5MiFvl09L3irrYtbw529xtermE/blvOxQYxuJ\nA3+cCbwrhbuASE/lxx/+CQSXsAGEFsG+rJZf02gTem+flBUQWxgYw7USLAXlR/yGYO6KKUiU5mYp\nMcLp5SF0ptsnO4GjOAmsRzhq+nFaThfDeXAXowTEeuWN+d56AInospMZc/eW0bFPTbgOjid6z1Vd\n+9+s7tiYNg6b6j0iAwEiBa8LX50Gz1E8B8Xk0bA4iCfVG+pXzxngp/ZgDAxA6x4B4xS8JSzvBqG9\n3fF/tpaS1x0ZYZNKrC0vl9eX2oeN5I3CbgEuLOUU1xIlzEYHqt8Ta5ZEnYRUtbhiunpXdVyqirCN\n2dgXkldd9U31gMhMY7qFkzBGBtdUApeaRyAGLxKnyg+nwnmirKX9Y3rBKSd6L+R5qhO6n0UbbSzD\n+4en4Cmiy/ti0HItxFAe4vWNWKSwEzlKaZ2HLEPHIUlwN4xiAAyIeXLQP3SyqcvdMzkhMFVdQYhH\nM2F1yAOo3G/JqR2EjrPkiLCy80ya2Cey9fh2IrTFABUwl8LswS7gb3noQTWyDJTWhVsMOvXawU6k\n9W4Jitv0d/+g4QNb1K05p1NtcnLpsIbcTsGei35vIairYz2Wpukkc+QIjcnbRoRYwr386Jd+y7da\n3/zxTz0ylTc2RMTh2TEZRm4kwoCvMb5bRjiCs5p4VDLdB5NKcfMPq/J+LOvbN9BdKd2e8etvM1x9\nZ83qLpzhi7vatfxsU6M1tYzeP0N1fDEQPFerPkzA/sJJfcYa5H+94+uMTRANw63xIlLDhmnCm9fB\nvFsT1znWi0KNE5YxMVAP5Nj3aNk30viM/aEGcXN1+348mdh8cJXP6Se0n9M2ShPtIh6uOzHcNN4F\nXvgZxyI06BOFPCh6pPn8pM/4wkj6M+5Q3d37NGdAT8T8ei4zfuLUhoasw2cJjrdrZ3LNelT1XVzr\ngtfkU+onSthCPR4WS6Xrw7Ok/kkEQoYmkdI7UB9unluvVVQ764ldp5OlFSL6uGJlq53fikq1mMPd\nHtYt08ogxQnb+cC85LdLrpUdkov30YC0DE++eB3VOpsBoGUdgSzOw4L/wn+VuAsCWq5ABwRe4fqT\no7SyMEpq1RX0wDx7yvM1IrLxDdnN/w9pE9XQ1ww/ANlsQf3806Yc1bxBlnH0iwF7F5dr6ExWX02C\nm4GMD+POG+syw7glXgXQ0OUc8vp22qMR4sD57/Oul0voKncx2id8UccXB9vsMZIBhX8NK9iQyJK7\nYG53Y6spKPwBaJ+D6oCzIRdMrl47suvOHOFMlq9EgcKZSM8cW1EeM34Q9wneG+hmi1jxmgRg05WA\nNvs9ns0cBAUoExbeKaTDf+UdQg8kQpTj787x73pVcySGZAe6vE/iMHRuSiZo8GQ7v7UaVF9ntzDG\nTtrPWvFHyuV/SDdzax+LPSONzmqYuZtNNGc7rSFNjipVg81YgVclfSx1PGAIfydo7Z24e3Gz6NIU\nMwj2TtlQKBbeM3mx05abZdGgKr2KZg/G7mtpHcWqPBAwGoOynrpV4ZdlOI7jP3SkujjjiUQJ8FdQ\n9dU1KADRL9hr5MOS92p0+2CDZXdgK1l4EzeYC6fuN9IyAXHsqWhfswpOubjlkJfdxHP/GX3hjyHO\nUvlaWBcZDw7BAWM+AX28BwSssw+yc8sPIxzjHKVjNVz51Vpi6eQgVAZfgVeW/CVd4po9zDauDBPe\nLW3Ffrt6P9FU45qwQ7MWE7oZ3zsTc0evg2krhbb9dLqiCoz6VuCkphBd+BhX2nSPTl+BrGC3EtT8\naS6sDKIiJlBJL+8+GJ5RSEQoTGfqIs6ND98n26dELJI8S0uXSltTPxBhra5yloAd2F4/mmmPjyWr\nTQxaz9QC3JZaY5ciYNddoc6aIflLXGP2kZlT/V1zu+CW+BExE9WpMnVToGI8RRt4jv0a874Y0An6\nHhiPkeDYN6VUowNBrQ5rQnTkFaMpJk4oWUQE3v6avp7Y5alYEE4wCED+ItD2AgaKwC/nFgLMfAnZ\nktUhijy2X1yEewInb5S1xc28GWJeUEjeegaSJijHmFVUCwrnggKTZlbyJ2a2ezSse3QS7DNzMLsw\ns3lvV7VDvQazHXN8RAgvOB0B/CgfYjwZQnyysjBMCOEXr9ltmJw3ogG/vxGHBu667EeL5qOCFKZS\nK2yY/1setEN3lBeyWFiOt84crc97yyhIN9WLadvrh/f0YfzTa8/jZpqi6C6YM8s4vbQgQayL34x2\n47QkQV/JCgk47e027m4LJl2YsaOwIdm0CLnMgOgEGQPFdyZktwDaQcho9eG3wdeeDVrkyzQormhu\n9aXm2HxMwA7LFBoLoLMTe/h9G0EmWJjSZJbpYBym7mGdw7mGASxg/8DfPNQ061R+2X3xcnmG+cIO\nvl0+UTTis+WrgnTXMMvcqbanhkRzuTaNKehiSLRg6bGYM0soIp56mfxn+lCOLxRvrFVCb4SESUTQ\nh41pLzHt1noaHrzs6Gg5F6h/f/xdaHC5qixpm+GAiRp0dMj0xX0roGySULb0Pg5Ik9k6Txub6XiO\nZgO5zmj4Zg5w8I0AnXTXRWRQrHzuRzUxeqeeMsb/JspTSY5oZj06H3vlmxUcBhypLvXrMLcXh/Ls\nc3bNxQvpWzLBqqdhy2tGJ8fAWkun0YPhNwlUU8lBB4Gk06kgUQm222XRVdAheeWAjR8NbiAop06S\n8Wy+XiAj+daeCKkiouMukARqbllP0jcynVe076LG+ZgkcNqoPU37HDyH9n2pGf6ZkAQuwFeIbkSF\nPg4iQ36vkP+KaDnRItQq5Ii+DKzEOXGkFXjeyB2kGs1noDV9eD6DHXsQa0azeB+0c9fKSA7nV4Mx\n1BtiwRMnJT7JPQOciedKCuaoP0Aq+hvnG6MBlo+nAOOlQfvZ8qQxlg0laf4f6XLVWOpAeGt6y0pr\nAw0YlMDiAyvjsrh3t8P4eyWaZSoFPRIJLol9+5QCyrLlm2aVeoMUtwJ1/53pTKnTEHcZIZfi1n7e\npjP+HdzVIccamu4mef1McNibQT4nUfu60LdH+ZQICzwZKDu6slLfWc1KaTXs71UCJzmFmBNREiS2\nXy7c04shnL9MVkGQUM4rVvlqeU7hjpj2FNlt0nq2A7NHDHkEArM25UeIzO+An0jC3tn+qfMDBZmx\npl24RVKkzC2NhWcwhhc3TGrk1gzXt5aE3zkSTGv9pEL/s8V0XrlWQBLq2XFeBXgLpSAzseg2st1r\n71IH25LcYi65u03YZ8TaQSNK5ZQxrVBVO+JVdqF5H+UcYmJxyBsmvTOso+y/z+nGXXnu6Wxeb2K3\nPMCSNT7G7TIbSFmkl2cSMzEeMwmt7AyMdckkJzv6cvcC0j0fLIcJ+ygBucF6mrNY7OMFKMatX0PI\n4UdpryZPtTB7sdMGLH8FqHkw0PoHM+53+V3rRDIo+ImSU7g97SHk4uMmW9/lU3+h4QEVhf1SsCoH\nD9SCjVbJmWSx+5ck3SWahLdUTGE0c66fdQ50VOj3xxA9nvsgL6x8+drW1LZr6SHG4Ma07PvqbId/\ncOHrnVi5FevEja28niNJV/635eMPcCA8uWcnSyTm1J3Fe+CyROmWWUPs1QOJLqlM/Ai2tsSCIaui\nrBVtakmXqv0aMhA33NdtZu3vrog0aJfleoLXQUuDYIGcGc8kfavMyQBG72eZnrVz6/tupr3lLY4Q\nxVGFP4Jxgxq1oFD+d8nf2DrnUh9AyNvtyyOCKi7z+ReLuwDg4jFzd3U9eZQ7WTDxuOYKmerT5+UO\nG4qs6dNLomx30eVvW25a2Z2qtWBywQq/MaVipSr2RmdVavfkdvSb4lRU8c/OXc2j2EjLF9uwD9ij\nR+SremaAbHZZKoNbBX79rPCGwHPTuu2e/3veCG7t4yv5s3WUvVkFPocYD2rO92YBt3DE5NjJ8kgM\nBCj48v+cPe2x069u+Nco6d7scSnHpPHHPSM+6Py5/LgYVagzcTfjK8PlJARVcAMsLJiBvfzpO+zb\na4Rs26CnEdvlCgaKBV1YLeJ2dXWhGAXTQg7SIPEe+qxZanakqfbbb2xT8QLylB2wpP6fAVc2MhM7\n8GAoec89XNo9PAPakTkcl0WxeigJFRkS527gXqWbZigV+8fVkzfLL8ARih7A5Y8faOuGrHTI1D3/\nzLMHy7/g+ESSQUAfGIeRgrKCYK7EMouPFRuxC5uxAYpm5W/pKsdIPrBHWTqvC0PZClvqzFXBi97p\n9keo4Q8i5+/jCqoMSKdh43uf/t7GW8Dcg5wWxhGnjWC7PMUgwEzMeruqNa0zB76K0zeUaOmh69WT\nQE+NgpCq0rrPFoR4W/hxQ5lqPWMYVQs08oixXrdi4qxOlpMbrxoLJ9dbreMCg21g+h8idnl0Tl1L\ntZ5uVIyA0sfNcXr37h71rInz9wjZ2D+cn1MJf9A+S9uhwm3BGTz/4NlrrXLFirxI7VfKkYEQ5kS9\nUmJtizU6dQ6Ehg6JDdHxuh5l52FvU7VuMVMozDJdJMvbkeQHAh3I0RSRxjaUk9t20AqO38NUWado\ngkUnSoEZCLnKpWk0YPx/LgMwFeFUGPMwCcZ+o4LM/G/XVGe5eO/pecve0eHmEnfeVBoIeGUVNgM+\np5FXp1hflAYwWYzb3FqUrZM6TMi1jBAtwoA8RkCsrYN61H3rOO2e29xzDffAshtKB1dXBUfI0Zxp\nVN8o0s2S0sIOL0Z6Y2+38Wn6hSTm9pUH+2vQjPt5mmWo7cg22+s7MbGkZISOJNCM1mCrD3s08ZAJ\nwSe0IXxQ9GoXKl71fWfyxDOEN80E97kYHfLwT/anINNK4DYOqinZPKwL6lPcmfztT/jkkYeC47vc\n2LKundEqdpIO8cT/NlrAVtDH6t3Fm9VABN/HIsAxIiNvOpHUSrLSF1keYvjZzNPJ5FRQgPns+eTv\nGP8JvC15MCNYsPYO03i0V8tim0p2g1ZGaidN0DRZ+8QURKlhGPX747Npc+Sns6GK2hOpqQs5xmC/\nkg05svfxeKyBc+mnkDT3BuW6tl06gkPpjvfgTxknS3UtGnjHnLRzXmIjQMl2IQ0m0gzzccVzi/72\niZtemsxeuumi+UP3MrCWaN+wN9xfBDV49pifJbqDeSGoznX/Zcb2XT9kvtBFWMmlBG27ZlbXviyw\nPnR21Qdpe9Ga3f0oQjJGGlKrEtk8kpZXg8bTyYQAlP0cxQpKZU2EjD5JPPrHfj1jG8shz+Fu/9Ho\nMoczpTM2n3rQNUp7R8v0cHO6ikm9/A1cUv3WjysTiu7SuCs4gBkotSNY2Xk68SXZWzYgFxmK8HXy\ntx9sdKEH13yEbULEXA+4COwl/PywoPj/Nl+Ew4Pwcm3TnoqS0GSPt7HJPOo2hoOxxqB08tPM+X0t\nB9E3nmeN6WGtdPk5mkipZRl6B32i/Zgg+ya/eRdCQdf9fg9Wyl1aioGzWlZgA8sH0At8Y7gl7NYv\nGsBJKYY9eIu3oVdG89uBhlUj0AOPcTOGIyt2OwESMxURJPXjak9Yh0eSBLOasPf3rxt91kWGROIx\njBiT8eMt0OnS2yu5HO2Eg40cmIqsC2vwtJoj9wOdu3zeceXfhMsdMoEsk85U9XUNedzDXBDY+d/K\ni529zO4iKsBwTRgnL3+Qq6lgmFdlFvr4PT7x/PusFTxAe30moNx7vtlthoDXjY69raOtJEVg3oac\nlEa+QrsLiy6szONetja8Xwm35OWq22kBLLd/fhaSvhSgxFNpHlINTa+dJ4OHbZshSM479f3oy6Gw\n36CHvvAUHpTmQiWWOqNmmUHHHnMRxvyySNkV7J8hlPk547mUpXPDCAheNrbQCq7Zg9QcaiQWd9qJ\ngnrFkLP+BjGxkvJwrV+1jUS4ymZ8io4U0EOc64Tuk3B2OXy4e8bHbNs90VoNbogNJ2JBBrluJx1L\nQ4+/oI2p1bd9BrWyi9lb2v+KL4o85RzAFnSU5vGSjrIx3lm/ZH/QN8/90o4qJsXwnwzwywuIEieB\nDYWlvqUtcnk46xKGSj9rr/PSTZBd7gFkW0W3nLbd5MKKjVDxtdiKjSV30e6iwgDQZ5rKvLaEPVul\npiJd8wgHGnnZRT6oMODzea5SMDG1Mx/Uu8SQZWcFTOb11D7MmcZD74Dh6kGsUS+qfY/P6LK5ZyoN\nHNMkZtEiQINbI3DG2LexnjcnXgKqZm2ZXGavRz/1f3A+4d4Rw6KoWfXIZOVUdNn/l4FxU3xw44SI\noKl1tT8NUagrB/gafvUWFBenLnxPxW0TaqMp+/lnAdDvwHLTwf2p56K21HxTlxXAb2QmgQlZB6bU\nDuYRjWtw96PcNIcEhaffTdNRFC37g/+Rw8qIWX4+euwL7s7q0kxKR4/TG/OfLrnBR/5+jgJGxj+u\ndtyDwjwrtChjTru6KPXODLvAm97PhZ8NRtb2Yzn5a9LjbWYSBpxjf4eyfAdYjEw9yPbjJpi9AJAW\nmwhWv/9b5rkxkeCEr4yQ7tXZTLx9l9hQktow08Zlh6pE4/8M86ah/0BFrTA8TwV1MQM9W2oncjGH\n+9q2b04TNO3wbncrECEi4DtBvtfYup7Ewyn3GlaO5eYLTg2/jiNmLP8fy893XZvRFmwsQRwnyXCo\n2nYZv3H6iAokmm54kiA8wDeKeZH5bMVRb8coUhzn+OdVrFqyf8myg0lyTJzy+bzzY4Pah1/xh3/L\nbI1bdfdg2OoVS3n1aXMOJQSoBQzk8F4lkSgV14x0kEgcg+6I2cD6IG6bQHCLflY17NMmKnX7MQeQ\n9ARoZL9Ftb6h6jt+Yj9TqigvDbbli6iYyt/3iLvMaE7nKbkI+BcyGR8FeD5rz5Sukk8W6WTDkgsD\nYzu0DTmAkRvyAwCKiwy6bzCh4dzKWJOK4GMV+psXZepr0io43Re5pRIkbdTsNzCzimW21WR9ePZ8\noWGZGUVoCCHkoM+VhFyZgrFBCuEGtlTrL1OhJnn8G/vmj6GzP7ppzjqtQOJdd1NT3mIJtM2MU2jK\nSJ1bL9b1YgSVmGnENvIHBs2oDoiFeYB/AdsDKbam8Ofe08wTbM09FVlDEjl4Kvym/+mlqBqdjB8W\nBTlVuLz1Npwe2Rqin9pAfmf2mro+7Q+P1t2MkMMBq7+mNXk6t7f1EZ9CP//mfVK5vfUlm1bJwc7h\n7zjymmmA2J7MYyTiTZCFm7zKpr2m0yARdirGbh5+XEerjM0JG1JFcunC/BfW4EJW+aPNSQhpCcmS\ntpvSqc1TiSkWDACL+Kld4mtOaUOVAjJ4IPoOKrJtnDz5EYLStpqmXsohKLCt+sy9YZ7t7NEdk0SI\n+i8nrAQsijEAoguMLC2r4fcfepagdfAzf18AS3Z8t8vItfUFlgvlByAWPD0pAxEeL6gRPo34mHvp\nqtb02SaAbEWUaCCZNhoIT+MAPCCwxxu6OEN9VW7YQw/hmrD4e4GyB19xhrNtuyh4zHoN+FX72opr\nxOkXzzghtXGGsQ2q3/6cNaNiE7P1xigeetIkjYaEOogeiEI0BuF1fbJDaLfReX9e6jXiLvhJ5AQe\ngiPAl3g0FjDUcmDqjRteAhE/PNHfoJUSgu55pPfO0NY2t2Z2Ye8DF9v/uGaVuFA1bhi9O6ZJfE0V\ndCrNoO9JVtPWadZbKqRoRYR64EhOYf8QMWXpQea8J6pNasP5XG62E3mNJmZhsEhO8da14ofQAFnr\nuw1npXWWvVGW2OGong7N2Kwh7SRpeKL+2tVeUM5oyRkkegprU8oY6yDTmkgW4gzR3iUD9r2yEQQR\nEUrnBqjowX6/a2UbkSvengDsfeYrIn57XZhpweU0dH5uBYP5FkquBKbngRzDWRIhRjpZOeNBuquj\nX6fJiQEmJedr3pyKIPHyXEepzbIAgL5Wuhzk/LNljrsUkTz1/vK9wk75QbxTXjCCi0MlhBUnf0Rn\nT9gWptFSKOOspcWHZzz1bR3qAF6yX2iGIpC7CBqaPPjOSnOIr1Qhts3FByUz2W7IrG7VFIApG2Qr\nZEpY3450S8oEjLqImCdG2XYabHF3KyViSlBMveVAn1qZGku+UFjoqKXKLREhng3hLqooi6ugvH3F\nhLD0lteBKSVsoGT5MDZ10f0FHDYuDu8pt7Yx+avdWuF0XQUqscn1y0GeYS5kr86t+F4ToSMW3ovR\nH9BqBMW/e94nritukUh+pUU2ENfgPglvuqcA55FabulEONPo2iV/4CdTcW3iZD/sNsGF1UHqf12a\nGB0N+vCYNuUpx9LspYpJWTeHOQslPRs7vWN8S54MBEJuS2EKLe8/vgESL+G2BnW7yrnXdPGpYRi7\nantqD/KGvHSTv4C2mNcnINFPsx4e4JPlmwJwsIHL8ez4LDfzGkbQo3znuwcl1FgqMpr/rZfAbjGd\nJnMlIYAo47jNmAfLXWB+SdpPEJgdYuuRi2GQKLWkI8JUR+/CMdKDssgcEyaJyvWOzURvv1hQUUs8\nPkMdKt81i7zFYQjiItlszd2C8zczwlH0eWE2I/wYLwBYMkRn868QftUBc7WCXFXvjBndT65IzaLk\ntS+XJHy1Fk4Cnnkwhr5UiOJVKXMm45H5EKxjwXZ8si08tIgWT/TPY7OcTvYc4EdO5sqbIrOIlxcJ\nA9IOjMcJqGbEoWMAtk2ASak4RNiXlg1zb+mt4fLZDqvemjQOEytIdpDjsKXex4b1kwug4wZmGlki\n8NSMfJNHvGf+G1NZ/qm5S3ZV2kDMvsq1CbBFSw/PxZ+mi7bChotalY0y4uMUAOBSP9kunqJAUrMn\nS2uohKVUiU917LWN5sndUR/DPUfV8pwKaCkdxF5wwUhxZriym4suG9nSYCjgTo7RtHPM8zJ6jadr\nTOy4MQeh/41kZsJ/XYpc5ElRTokVajxpABDhLz+d8fs3DQLWhTQ7dAQFzaxKEHPQYD5+qYLkSURA\n9WeBKvZqJTRRibHc4nbOfxRMxaQc+EAAjELMdOKS89L0XejFvCUujsz2fzQBJkpDyfKoXWLRko92\npzHpWTlhRDA9s5b8PX/AR77wA5ArUGNjqLmVzA1pp9zbxZdgpjqCLi9BNmyv/dg2HOuQs4tgw0Wa\nhIkwx7jfZ3N+FEnXqMihEhWujWBIpFVWJJg9UJ8Cj597k6j613fhjn+fQC3KCwnC2yGWi5ohm/8M\nSpdCBPF0n3F7iEKeRYOe9LRZGXKsa7cPF1dK3NOLqS9L8s/I5RGmzzYpuJX9J3AdnFkFX+eNJqg0\nKMrTPSxtaHUEe+by0YZm0zlcR9t+oiatQXde6yVVzmFWgcmsoz/fDx/AOOCTGxthX7cLvkDnRut2\nzdGY+x0SPOUVq9Up20+HVCHHJVdvlDHnRcwiopLP9EVVJJ3+8+zXcRwdR/W0qU3e3tjHMQeLcQKh\nJEXrK+Byiw8OmW0QMfzy1sWD0q0/sbMxlvt4eq0rHv2LvmpDayo5mQXKasNBMKdsSCFzmjkeVXkL\nx6lrIBNQrnRK3F9WHeo1St/Vlx7gKX61STdUZx3s6I2o9Fu5kQ/n87oY5kGnfIYy/Sqe7poccG8s\nnwtvT0W1l8YAgjLp+y4ttwVZN1u2Tib7vNpCGWTeUR4N4HZlfTWLkfxHA9E6qHgLyLhFdQxD5MjF\nzFCW5kFcsPysIWupF6wd+bHTvxMd9+e6km+LqJvwX9TJm0/Tuhv5smOEetrL85LZL4hoOD3gkOD9\nux8mkIV156Zn5qAXgRhGCBzTAoc3gdEEAZuM9CMnvGFt7nYQqUWozJbVNIu84YUuW9UaohW0MdBq\n9OmTNAp1jaYXjqH+ZcW4yCPJEkJKLw97SJqnlj0ts5ypvSx0AsRbwVqIUkBHIRTEuqdwXy7ffZPz\nSuwzY87QGmpoKvLB/NF/8a/XOC/8ekWrTlyNU7kOVZdUUan4xgg+rmtb5dxRQOg2+Cg5yB2KYpFZ\nGLIJEaN5ePx6OuNsKyGAnoL8VB4CVbYL2YhLksaWv9aVH0MSEQBH+d+Hhh/hyb08on14QDQ3IPn5\nPOfH37BX1Kt4ZT9FhH9AqYK9+IYyvlY1QZqMYqku6WF19aB5M1k1mnxoD9qP2OCDsvW0PulTcPwe\nbZWzXBB+yCTURvqwPmCCGg7Botgo7UemIA/YDo6uZQhRsrlLBqrNEpQRRJvwcCZadPmql+bxVLoB\nHRd0slNjme8ocHNUYblDKhFKIO4zGW4vkVS2xu86jFCJP+AUtWtEoBbRuFb6se1EPWSEZccg/tdG\n3S+yZwJXmSQIKiocBNNsoQl0ZuYObaHJFh/ghdUlIm9QpTkoUQwAdD6P2fVXHsUxXitYILj9Eao4\nnl7koAUxv+egJe38T+XzWu3qJvZlze2xvOmAAXEjVQQfE0DmYJfZVFKcDVdg5jYqF8G8FxSmQcxC\ntIn4gkrqg6EV87gisbn7qspi0sacZ6Q/1gQAURtDxooDDK5gsV0NEhI7EyoinLXjZJ9SY84+Bzcw\n+VD19FvREqBGtziYVyJ2+YAO9kUgWbuDuEy3aFnNOeTv9ze33bOAoAhBDtbJ4BJZt+eGcbWYWlP0\npMcWI4mKtcX18daNTCZR+LgCAw6J/bR3KiArm9ML52M7oEzMMSX7skvxyTaIj1zojGgXeZXvki/H\ntGHQauTSObrzhFf+YE5t50078XpPzdQQVhn63OgOKp+6Rie0Q2OZJJP1G9PXiAViKajwJ0U6IoUK\nVG0LJhSYwAOF+ditODWEnyYQJx6u4HFg1/OYPbRRf5SL0HEyB2SOhxzRc+QylENCwbGWxkJ/MjpF\nucxP9yehbXSUmmAXr6u8e0PlT+0MEcL5+hML6XanaR4sMnepTVUB5OQKCOhz5bVdYkfJf/AZhI5u\n1tj4AjxaqRwn5RhHqqcjspa9oAXyD6fTTd6VkJtf79obE2Vn0/CkZx5Gc/vEV6Y/UUsQa0+HNWxC\n0KxJ/LqbD+0Xo9hk30nIOWumBfNHVFNABhSH0FO6hXe1h7DRvhESnhSo7kGWpv0N7/A4SIRMybQt\nC3MeWIdBm09lya/sOlRRHwnjh6BgZeBEtPqYX++mSFDadrZ5912qAYsGsdIFlk7+p6xospuH+IyQ\n1PP4r9wg6I1iF+wSIukIJgfswFgAGBtqgDHhfMaea99tCTbBODCxTlvVOkbfZwEcdfqDQJioj+nY\nkY//DSMVhLeq/3yvLCdiembO06ynPh1byTgwmALsU/RT7uf5DrZBontbQhHqEaFGqtf8irH9r7Cg\nJC23F1/SWnAd16dLnUjiqbXwbIoLMHbD3pnqvbyyqy7FNroWPX4qTHJMm5LbSMWNMGR/l4ucWMxV\nky/QnNMEU4wvxoK1RI+mCtU7cdIjq7I9Jx8vXkCdnLnAXFb9QNHosk8LwZfmibS/xe8bBW7lTtzc\ndbpZwB90QL9ATHHTbwX997qQwU6f8Q6ZjTVx8VzS23VGBt3KmFvGycKB6dmPyzvkFWiQW+Cs8bpN\nvwr1sTQF8HierHVZSIDcGGnQ2RcE9sHY9ywA2gug29YJOrasaChUvfzGHMkvgAeWBLoNN45Ptoq1\nHNYIOiNBDDt8b2NxtHOlftvoV+KQTNTItY8HuSuvucGLRFZ/ijxZMp7Gka8hw0omBjJ3K/Canqk0\np/nI+kfZ/ww8PnWSkJCV3iTei8yb9akSyGPtimN3DRXg+nm9F1vhe6ZjwvfxYdXsR9RM2YFddDJj\nPJ/7sbG2ySqr5AI3utiP/mJsP9zsIUtciEXpzIiY17AGEzEf9WZc01mBXJheccBxjLpk2hOmp7DW\n/bolFGQo1u0HwOCjvUQEN/VnOXBf9dUC8dHNpljvbvcpY97VkVLl1hhLXJ1B6CZ5pcmV49ukA2yP\nHUvkv0kKuJDG2kjj4LUJ5YXaAGBdch2MCw/ET+X9R1Lbz7Tm0oYfP/vj2oQjxfHEux6lD/Urc2oI\n1tAqwKd6r/F2M/RmthYfXTEpVDUbiw91v8Sh4I0wwtXOQr1qrn4qwtP90lOT+tlF2M8TKR+rerOz\n/5Xgv0CCYjY7xCg4tuF//w6fpvgs0Xp8n+/+RRHW9SZuYLcjNkECku4X/bNTWgMoAfJIJLIPFZEg\nKFFHSa7PwlQqsQtO7f3M30QtV+S6oPKAnAqXuAd8gNhhlzMJ4O71NOrGSrsYdqyKFMu1pulAegSk\nQZ+uiKAj5kh/P0Ce6xKJQVPByIdBLuUdKWrNSvLdkjayB5YrzBXr2uR8Z3qtXmVTRrfhblbKcmVx\nbSlQCkpVPIWCxkOIc1vH7QfvkHgkz0Vh1O4Br6JIiEDbSD3WhYk8pT3YrbNfBhL9XWekVTilmC+E\ncoRGgWwOOnLGcaI7bxVfNZzqrCajMQSnYQUipkO9bAkBHiMkdegZfmnOCpQgUhIRZAmdKCA5IYZs\nhcQolXWCTRNRgfH7AkKeeObiP8KDY1vJ1LZx2YPiRrfGHoQeAVKnpo5Q+XF4nsb5FDWlbSF9WK4x\n3r2tGTKoamdzjbn2uks7TO7uFcTC1hsh2iFiECPnECYbt25QcuA6GhkCaQDMVCRlC72dzdy8cM0X\nNLgdEMCfAuh/pfO5Soab4eZFkdYi0lUKw2JYfFUm0MsvAYUhYEY0Hv6jh5aRNCEz+5cuDw7ufd7P\nmvD82HTyuLstpgQVz9MqL2IrFX7zOwsr4Iki/sE9jhAIqK6UNb2lrwHuhRS6OETJDguQycwqveDU\ni5P15/S9l0xzS0bAffASHIiHDS/nna1mXJMzNA92v5SHt6iND+4NgaspRFj5McYl13C+pzciz3D4\nX0zSkKlDQTpJZAjzqyduOgXcU5sROz6raPi+V12shPmKE5aTU+nt5baf0/qBBo47q2UjQMY75tMF\nRVal05IPRf/HOpHBowN7F02gfVE7H44F4ERDK/Hq1xEtrOFK7H2U3ec851+lya2zTCJR/Xcf3VBe\nlxb4RN1NWaePQkEcv/YWnNpQx+wtJntRzhd2+4ZsxawcWl10ffFyNr4ZHupqLvX7v4I/hqx48thY\niV2fchI4tKi54R4OpsCf7NZMQeEvUspEGjrcQxpHVgtMx1vXC3/lApBlX1jOD1aTwr7ThB9FbEPp\nc37PFCi99PpLZuExy4twaIUSOK+4IOfnhrNzP4+bb4TObcMe1gbmAED5+fDlwoMUWWRMMzWsyN/A\n1xIrOrM7zcDWgLZLcIOfS0spfbW4l41PKSCbIcNrB3jFSBrcwm0pQbneAUYkURTiw0Js/NskmPQ1\nqg+UnXhDdicyH0Wfn4tVGjaPXG+qMWBP4Fx3Z4tA7m0jIrR68Ao8aX+cbhBeS0kMS/j246amm0/s\nCXDiO60Fcdr+vOQpO10O+LjBwZ5qsiJnpnjeaJqXT+Et9/jkV5Fjp1xJ3EnlachHDM//79eNvK8/\n/JKOSm4wMLqBigZLP0jzbtnwgaUT77pjjr7T1mI5GQzeY3nuBOxgyscRlg6qA+96hZ+yXXtVArTR\nnf8MO1ycpLPgEkAEsRETTvNnDrfQAd3EFl4I5oisHtpNwuZC9DBflnl5hDZaZW8INJHxcaYffeOA\nI4SZqRyHEDisnaRsUSDIwcwj+tUhOyJyOMFqPYPu3W8unFFJc5VDswkGf2v1azZ9sqH/+QC2r1+q\nvmU/p4fmXXsNumWv6mJCHSInANf3xj65XGYYVUADHApABy4FLykn1IX80gOG/DkB8tArpTRIvOnL\nymsyFKe7bYMu0tUnlo2TPt/h8MeCWZiDdodmrMWa35AxrWLyT0U3n0ZtHC6/Vdt/e3T6oziJ/eVg\nlSZVzkrl/F5IvDwa6bvb6U0s/exSaMcTOHYms2e8B986/g+KZ9CjNQx8CSaf/8NGvuVEXtnONlx3\nLAWQZyLkf9AlRhWJk8otSYNkhQ30sHgRnkTwxaL/hxEClk6MEI+Z5UJt9ycXKODHuULHepLOcPZ6\n14Qufb3ZpVjOTbYmikm1m0IX3bCoKrUhj9oXXboV9woaTYxH8fx08ABGoDz1wA4F8VMn3QUY+F4A\nsb8WtvEmh+XEuRlB1edUNrN8WEkKjj3TwLKejJhrheVTvDZR3LGzRN5p/Fiz3f35bZUALgirF+Xu\npJhpoFYB7CAMH8og/F+Jlma38Ms96J/JN2SLV6bxpjWe5s/aAFb/m5T2WMr6f/Fi+hR3bYw2ANUU\nuDrYb3BZizZl8oAm3Y8N/HtMXtiLLPo1FuXhV/I/dqimr5RkGNYv2vmFyIRzlTWvf1OoQdCpp/8e\njsVRC2nOL5aja1Gbrsb6xLI7v7zOy3OXXnL3A+5G/aRzJIi6OYRIU9iBmF4cPrBOeljwsiThjyIo\nKFFxbCwY3TLsY5DzxbRnwXg5/kBxZOaES7X3X+zHI5eyla9CnQbfH3EUEvY3EV/37+8QTasY1tOI\ny905e4+8SABe51gkubKLjrhy29UKH7O2fYpuytamltn64Cdq4NhqTcnJzHCqZsFlQR2d3NCt85uw\nAMhm34FtpsIt7/67XzcvPhzNtotKCiLKN/Cgm6WqDNXxXQdqWBpk2t0ruAhp3IlUhukD3Wg+LyXf\n/ZO143HqZM09ejrB30WW0BvJbccuf5qb0GgBxnj7M/eDXJJPxea5jNDgIz5AJ0m2xwLDSCHWb2Wv\n2gTrQlIYnhFqNF51eS9oTQcHL1NUd8J5WhoKC/tnFnYhqZPSXTiC1F8H3rMUITUwIwR4Eq5f/SMy\n9vvjUuHFbAre0sYO884yH76/735dC/HbyF81vbM7uEaXpOBXKXUyFJwP5E5GfEcWXmllf5c8aS/0\nX1aavdNjFTbB38PKSNPR7vE4GYr8QZDsjsYzycp5vB/F1X1R55r1oHlKyB4lyggTZMjolN7L0+/K\nh0SaDpL1hBSp0datucCgpkHAK1ECDvvnZz/EYs4aUJdU/3zroy9RYIfB24/4jNs5h5aCBTMkmeiR\nAMIDLVnyEReJ7oVzZ6u1b6EZKmUGyoE/NAWcRmSPjTUJgrzF4ERtajmDO5hzZdyTOkti/h4tFdJl\nsaYMNAKg0w+186Fz7c25LLBkit7BG/wjrAPz2cW6JI3S4ru5pGGi85VQsoeLOW80nnosEnFDip+V\nJ7aDxGq9BSwM50DlrWdIxbvLObiVnLR8Ar9HAyYTzspjd0FPpeLqQVnWy9kn6nIT5CqukkpCwcLo\nSlct2bLxTcQhrwQucx5/LHBYpKkrp7rrzkHZ6P+cTUcLHJNyJPZkZK3heV/f0OcEsM4EKLZpD0g1\nJv8wATCKBeecm7/VqyQllTUUWvP69Owt0G4XzttdIBz8DTPtaI6ts0hlmbOkcDTTvBf5mZ3rNmnw\nlg1mysjyO/US6Fuiq9t9+3Xofstc4bHEm4YBjGCH1IHTDzvQccKfnM/cqleRvo7H5eXiFsZtPp1G\n6GOcsXHa95RzZj79MoKZNjnpEY+t8YauJ+ETl9KG2HPb5yLpP6Q6cV2HTp5GNHhvtcCoWQBAiqHO\nbxr7/HrkWj51SqQJe0KV/R6u46GvpDHfkVkDlouZTZy9uiFGVIo58fKeM3Te6Crcktg/2o5vSjkO\na7Z8yu/uzD4/L9K5yC9W0SCtqS8uulGQZpEHMWNlzCWY+pOvRSTSp73IL0EUO6DI/7fF2UjEWTyP\nl7qk/O9HvnOrrWAV5MLHT2Axk1W7H5akhnhcPAA7Lx/Q/Q5iLoPNHVWxjlvlwLlwWq9OaQICR4jq\nGDNMi14HM8VyANmSUU50AAoSn5ABDzSXJ9eUaJT/oU+O6OyAckpg07u/yYW4BkTMw8xIioyNOSqn\nvyJ7cBAB7X6KOj/KjRLLt2J94Qj6UBECe8x1PJ+/oKc1U5SNGmaDsiJPYE42OuvkHxD9CXzez4zx\nMiigISEAWNHfQrcy73vctjtz9y0ieOjN163Or2pLp5RE+4EnBTO68tZ7DiFsYAvgyApEJfTwTzS/\nH+NfjaRftQPoB23DSbd4otwB9wqCTcgyKeHfwrA2tWNoBnRRDh43MiB/X3InWXASYwMqfd2bTAXB\nO2ZNmuvDjFCqHdc6XOPqtha0OlB3JmvtCjQqmRjfwBDEg9nRrUo5OrhjinJ1ZZwsA6X9Oc2M1jUP\nlgQgjlV0P/hsZqt/GDjLt30k3e6DvQg5Ye+Kvn8MkqXne8Omnj4K3lzvEKXPYgWrAr6+t3IuGKRO\nr/774W4XqSnQXDXYSsPlm5VAGXmAqncVo5ekdQw9di1hmya76/G8VcN4QK0J/Q5c7xhsRvZUhBbD\naoZnX74rF3GIzaxID8PujDrYDMP2QkRZijphPCywc/l0jsldhR2NB4RW/kYPN3uUqK75cVesEaL5\n5v/AR9/c4p8tdoJRCWfRRBN5m9RRDQl3XFMUCUPifDExugkQfos7EIKRGrXely/Hf1bqQd84KBHw\nQgmROHDt2QlItAPE/wtivVzftCklyirO4+OmfkftzxGbX1/QGxAlJyR0gmm6RvKa1YoKUrKgK5S7\nXscl6MYwHWn1FJriTwerIP4mWdDdbOdCyCWKVqrv72q1sgu9Oofps4WpH4Id8HnAUAeoyYdHVdyf\nJnSE8viWhzvF+yf1tjrLZZySiZWT+ad44uIZkAqC4GRPwpOiYMPcB2Wa+1jl9Sjtp6expmx+u/5h\nAqCBE5nVYwwbNJ5/97wkl/T0DZm9KVtrlWoLxqYBUhTAfQ/Vdd5kx3Es/xK0tvL1c62UXivN7/I9\nVqga2Z9NvKTT8owc+ZOI0CANprFE4IK8JbXKrTc2NMiULmEnCU8OGYBYIMnkxGLerH12+A3ChuLx\nHIhcg1avfqvOounj2H362C2fJYDtmMVv5i0y8x0+v2FBjrTzdrisolTypKmUZ2MHXga5ZGY7mXqn\ndgkFBZOS64qYD1nIn48V5Vlsi7LF5aLMCOZWlXOw8WmIF6glbehcEFsPSnmyeQWeFK9duIjIEiYC\n2S0COsdbabYyYPGGFpz+iI9h675DoLj4BC552U1qA3tp95Z5GrD+9NcJQeNA3QjGp8mHde/skpX4\nYkex6WxEDA5ppcdy4YJO/pIrDUz4Y+KJm2AHQ8G/1UYNLy3QQm2xvEdP165sZy/GgTk/MxGtmTrE\nUumAVGVSTzDM3pMWOXMbHsDiCoY+LxKBmOofdTajcbPQor9UnJOOh3bk79plZvZkj/kjgc1ipavu\njT6UFxbm9ghBi9L6eUME4BbN+EiorSLlyWruDKS6fq83mX+4iaCshfP6nQnuTU1728nJ1U7J8h9l\nq+nruftauizB/m2VnGlEUGvC5d/olcqk6pWiMeuemTJM5+/BeAZ82XblX62hnpwo2kJhh0byu56B\npAUGKnLdamBw437+UlRRmPWEp2UG5OrqjLR0JMf02lGeO+AXXllC0ji5T+qUuITeYpHEadr7rg4V\n4vCNuTSmTymv06ja7bmoQR69HQxh8GWBKzTOLLC0knyElBbtUMaLTK8ocsuJxklx/fiJ6dcTfyay\n17QKT9aSN/+h/kzJsmdd/rSI6eJuQzg5lq1pM9nNggWdnDkZteF0Zg9YFqHbGfJMRqZuHxiWWHYf\nhs6BYwa1Si9yITAbky6OYkMYRRXLKB11R+pmRoUoiwr0xLh07t5UF7xEWYTqv+9KueNxtSOeV/+f\nEdo7uzq0Dii7Z8WTX2z7Aga6oO50BUYS7Zu9EQqXr8lj66On35fDlpEVb6h0feMPSn8Z7CCYxZxv\nrrgpc+B2PXhRlSumar1I9au3GrGSzbXaP9tYa1pWTWneUxksfdk/VkDLBuWlUN3jc5hvC0URlDsn\nV9FN14sxPOVWYbJt04oVou/R5XA4BNMUei+KMqaZ9LsMWy3qKESHAs0vomXA0Q1xxXac/zDN7LsB\nRTS+2gszGrNQQd961iFcXZUTQQaittUszpL3Z1wklSTLGQ3Do9eYkpQ4MXTmKjEcUcTkDd/8NA7M\nahK/cQ2y1mYEyJRkYFICvafpDj2h3+Vrzbg9cJ/+E1y9pNY2lS19jiEtaCisx04TRLUodD8TP7UQ\n4/ijc61VHaWa3tTgXuk6D9hD0oCiJOSUItz8iavDq1u7eDRCMKfEuHf2v8Ddhmkd04t2N/NQRTRb\nIoNNHHHBrQ/dszA1gWrgEV1xZ0dKWps4R/gk47Ow72agtIRoPMhVUyWaBgxaaEF9NAB/0Knc79/h\npDrIRM3UDEfbvOJJfBhGpmEXa5waa5PjxFrms+lsyTs58QeBBGPyfXH1r00fkBCCrhrlsM1QQTrU\n048xf/oyN0tUcjE/B1ZIBe410V5kNJfAtxAh2VPfvVbgbecLqGm3bRUljE8ozf1n6ARxD6GASLmc\n3GOh/dMJqp5oJn2sOFwv+B+AYOeGsnY8Qc0sa1DnEwTVUhDCZ2M775dMR3zZGEM/kk1pALwGQ6Im\nCnigap8WJ3+AQ+x5TZJsjWnnsZFbKiAITDP4+5gG9BpBQwVL7bSQYfWAYV+HsZNkpN9DYVKoz2u/\nbNnXohT5+gKpBQYKTg+h6XWaT/lwjspKXQkftnXwIgZC2EoA3j1BVjXTu6ePnVHr0azUwa7rhzUe\nSNoCfmOWeqnZSvRbVB+fRNZRI4hAVPpgptKPpCgL7DekF+8a8+X+Rca6jH9KFM6Vat3qvo4j81hW\nxg4glHb86eHWcUlzAW4wQR/D6gOuwjzvEi1jMpNNzZda2vtnd6b2QWQHKGtf2V3gPQNE7qp0z6tn\n8zMGcmW/WdC4n3Sc9GSGmsVAzNkoJmkCpBSMUwSbM1Tu1dX8eqXtI53zosOPO/buxyAkhN9sXDC/\nt5lVZdFQB3QqqT4xDjY+CwXxguwKeogUHQlcmu2PyndG1/ZlougRvZrmb/Lkw6bwLFHnuYLBZbov\nvAFBpbSKNKvQkZfTSwYiDNvc8BMFjMmjcFamwmizpssKFLlKIIbAUGDo7/9giFPRr+jOsQsmEYM4\nvL/nKadZokw3N0FCPbZNG7oP3I1wFyii7Klje6QNyIu/MqYQmb/XY51Tt3uPm7Xfc3/tNrmlri9s\nqzbMC9eeiwC2HkXHim2p0c4EKVWinPJkmzzHhHD5XqOMojAJPhX+ZblrNiwdx7yZ9FDd+udt11t5\nKBAtGk+DkDqFAWmcK77O05i4wt2nbfCYpoKyN224bqN/dwJBUcvQDeGU7zCkK9cY/M1RyGyOrSBv\nuZdwpqjj52VMyhC4eSw0VKnH/dkjXE6ob2Bu4okt1VlwfosxgTLiKv30Nxqa6xsSgUBdLW76YgRM\nSSxCp+DlI4KsYaCpTLqAkTsNbWs/XXcz+KkpZwGT3Ak7gUk9gWYDThPEGhAMifMZoNiuB/frOteo\nErLJDy9+/CBi+mwbqwhlM1mSLtEL+QjKXQtFXnAoKwlV0A0S3Y1F3eZVIt6N7EGpp+GqKm6pbvJi\n19Uv96Xgojy6KuRIp/r7ylJhgsaZmktjQVHgyTwbhlwc443FUjShzjYUNu1v/lv/ma3v07n/Nu1v\n5Ygxneefjd/BazNEjUTdLMV+xI/8Z5v2ZgRVVM/EjyzoDUtDR+/Fc3MUuqiQt7vYIQ3vJshwAQ7H\nq6dkx314RtY4hRvZUCGU+rnX/qCmenpVXFV2xn6Cc/5OF4EXbr6RN/qhCuiD81yAQd/NbjNEOtMW\nVmqXqTPsOOPY+FHam5EW4IxjWPRsAIX3P6My6Rer1kJd1F5zhDJbArwUbEm54c9GQkVXxhTWYIqF\nvH+Qp0Yy9tyMUnRlASj5jMvgwe3cUuHPxlyPUuZK+rK5ayJVxweBf8s8NsE58TFti+6DGNH+GMoj\niJrcHMl7JIRez9U7WoBdNSTa6Wu4FsIQskSZAPRnqG1YIhSSsLnEaonRZ5jHn6PxFIsGHWLkRRTM\nPYYKNKVMipW3WnaHIgiN57KTb5pXBGnXQxTZWgNJ4Oc1Hb/CLPxx+jpJFEHcrEa1chVQZd0SORaJ\nC0zRLJ3K6naY4bpkuEtRGvqnEiC69i7rkR5IYJVZn4T0L/IaF+HxfL2jZBzUqPiEpBIkGRIoRoal\nnAnVsez+Tf1g3sKGGb8Jc7Bvv9mbKP5r+ciY4SkeEHFCjRtXAHTU2sIxj+cVDrOGcwgj04QZg1CG\nf9j+AucjM1EmfmYfM6GMwlJ+jju7bvRNsowv0BBNlF7J8l98+ikv4vmUYM4WSkRV/jc+XOLWD2y5\nyNpM1OjVk1/KAG/In+VQAh+vgz1+4/xoyotLH/qRGT+bFxn9tomW0+Yzn/gahFC7LGrb3bI0eQTp\nQSejapmUj3nSlxVQ7dpQNZ0NrLwA+G/GycUyauRzRBxKtZMNHDmjfuBZX7Tcy7YiatzCZ6M2eST9\n05E4HperTb/cfGMm16ME0VdyxSZXAmb+OckEFGyGvWLoIVi1AdQUkJAh5rbT1QIkSS95m6iNjS13\ntFc+QIFe0S9X0DKXeRy730ZfGzxDHl3mt004W60VSMKldSaBLcHxxkrXUno6fZskEcRQEFd8weJj\neZkjtL6rtwkKjYV6x+cAqIRIH2CIcwgvi1MM+SbuB7Ej2OHbWGsH+ae6kDWlG5RxNhyL9DD4xcf0\nDdxElbdQ8rphwwoJvoNEe02bsY8iwtjuSyD6Y6clNaL27fwyCzjLujIWDUy4CHvK7Vl7a2PLD+dw\ny3uIbO9kn1IMMIKHSlomNpPap52CEIksHGtfk+4XSYfSkQKKp/kNqVVR1RPQGFToDqSveiV0bWAu\nSEee8c2awA4VDSIte3mzaYqUYDEfpBfjlJ1kfUOttH4qAi0IgL4BL+9FkiKjuwGeHVs7r+v2X30a\ngWOPSwAX10NabuD1IZjK3kIAgJJXnmco2ziHkW63XC2rKj3imToI3yyPwL11wtrAgJETZGrJTxO+\nMfLO+/2U61Knhu2slj+hYdaJqoIn0DCviHnI7DIQ2fAgjjaBl5/Er7USC8yzu0STnipb7cjZiTZP\naakr4i4vGo4b9Bd1itUaJzJtsdWrkVcFA2gSmBCHTYdro1jelehFneB/aDR7mxtnjz4PoHdES47A\nOuvVgKpCzNoMR43wGwKzG0B32o2W4cyo5fewsH6eHMn+T4EedcuHmgurYiN62uO0nz+M7aIaaBjS\nbPAJW3sIHIEEdl1P1Qtj5bpN+FoHJO1S7NGnxpS9OU7QMPd0thdPovlaO1Whwj23a2G2ry9SoW1z\nY5olooVHpgXYzMH7/aKVZy7EIaC6Pq6ILrl+N6Ql3+UuOAhOVuIGmgA3U234T48fYm736NjR5Gul\nrSbC9/WbAzLVLiCWKyxHmQqbSEsaOrjhz+ddTL3rcvzVLwFzhjTqRWQsPbtItebs41tdPf8MvInt\nkHYDIMP1RHhTu/5dAS9h/X3tQYAQgRhCHOAE/4uMtfdvIjgAe8fs2gC8QK99+EappIfJfUkvZKML\nn7JtFbyd4wN7CU5dpNIk8/RsvM3z2u7jtDa1yIZZIHNQfTaJ8WmsrUrjGpbjbT5lPZoMiQt/jblL\nk5uJo5y4kpVNE9Mg+OlMSMqekZyUeFSHuGOBn2smMqko+UVNaCFxXInWjz4TYpqXp288S605F7cL\nLmqsI1yHvV6yXa/8DztLhmbusW0vtxUKU3I2h/KupFTrxLHKOWOrxyix7kJ4L/g8/PutXuU1kAoI\nAu9OkaBF9G4qAHp30Eb2fxolsyRqSg7tDREIfyA6rPwj7+gY9z+2g65bC2+O5XyzC979ETBl5EmI\nPjuXiDRlRRDNtKsOLoz98L/9GAnV0AudrPU+sgVjxwcNfKaRqib2icBzWMIIsL3QLhhQxLI6bZwp\neya26npYMw+VI6+huptBzOaBV//Yonn62HLD3MBmDEsZRbSRiedUiuv7FO2kTlQi66FK9h02Uf30\nzrbGSKr4sRI666hzuzBE11QBkJqOosb4dDlHX01MQSKIc2w5pKvfi1MECCATgZMZ7ilhizyPHPhM\nqYR6erClv/4mrKlfdy/eRyaWBenWkK0J9aQB62+fNvXWRJ3F5SQA4xtCLxOlSKoqQVV+311DUvax\nEm5l0r5y8XMpy8Ig9W/TOidKG2ruNkmtRHwn7fomGNnG+YRWvlHPYkKcrMXXVZYEHhVwrwv0FRdw\nqqilhFaMowQStCU6A/Mch+SK8shJHK11OJnt4E6n7GSS0VWWIoddIm5+RK6+DVbhGIGMWvq2c+/r\nUMAozYzqqMD/iC/ZUuMEFaGnsRaf7fDLta1A7VFGGX1JrfJ84/D89+TUzIoiJt2a+mlOv47F/nIt\nDAgtzOSYGKb1NhXlkc5js+oaoygWm3Nl2B3F52XQd7P+eJfDpWK2TjB4F1BX9GMnOlI5S3kWAp+y\n8m67tK5JQgHqpN0CZ6yLbololzSu4PX3gW8kafdkgnx/s11MMaGgmdlGj2EpOY3RmzfYb0zUcv6x\nrDj6PCQU7tjBx85GxXzUZpzyoW0vswvtkLufpFueFe13Lj/xkjdwrV9ztjg3RmEWpqEDhb/ewj9w\nMDgzH1m5Waee3zV6RsdM8OywzwGB7r3QEi4+TJUT7n93NRH2bl++VBegv12aakTzLHKbSb6HyWdE\nUctb0DJhxi6aBKuzwBDJ8IXilBnK5vb0oGMpyvR0+SIG/WehKC+lUhfpwyKzZ/x+BMz/AakXAFHB\ngprixyoHCJS+IyJRNTufZoRpXGD/NdpZEyuZEAOBoY4iuamF/oaWgXBZgaa0NGa7axmq8VyYXhhS\nXRaEXo0XFlyt34x/Hs3t5P2AwUqFOhBalvgxSFuIdt8s1SfXHA48jwEBSY2mRa/LrKm9DL7CVsfd\nW7AcoaS+xAkMd1ZA7zGD1+xV5kFBSJ+oUm+BHq35pBGjxdwPM4IYx5qL8t5y6LkBzYVXQeXrYz3n\nAPikEn834V2RN3BXwNBi++a9RQG/9kyZFKAgjy/EIEDqsZ2Fz1a5AD+kRnZMq4Gy8FqfvtzaDX51\n/24gW4s+KdESku5GMoJiIdxYoPSC5yYdU6maW2zfvhU7j/VxHIVkEAuL1jggslz7UvWmLvDQSvyg\nAOiGhRngYu4hcVry1NbfF4Y9YOxx5VSFvbZcdVav2L76PYXQvfZa6b5zAj8nMtYby/auDzpCGggX\nIFig1IHnalQgAmlg++abElpqAE9+F7wlpvxSuMr9qjsXMJFa1NLhTAuYn6KSATMLJtmc5ZgFjtV/\nqZI83QMNaqgB/sFXO/zdaW6lc3DKYv0khan0DLyxC9ZYoU56KxHnwcsy316h2kq+KlFI9JUD4R5K\nk+NKgW87SF7e2IsYnl9F4WoeUQ9uu1TrYwvbBQikWhMo5zGJ+jDNnZE0hXYvD7zLnrpjNxk8u1jB\nVI3+wFkgF3y9dft9r//mAputCiFpTIwLsQE06NCVgTlG73PCHAGOQBkEBW1i6c/u8at890aDr9FL\nJulPXrkRHnyQlGS6bml0RA8vNJpoVwFRl2QRt2qUo3qTbXDEV9aj3xXdfeEseUR6MQCshhixhNj0\nKU4YYyNjpsnXLYyHerXk3ioDeukDGLEyA51ZK07Szu2UDcIFqZ+ab2ZHiovr68NcLfw6YE1qkg9c\nYLT5Dk89XCyGIdn3pgnES+Sd0tcg+T5Pp7nx1EigHx3ZihMi8Oxe/D6guDWy5TSL1G0ZaC8BvFYa\nh1C5Pfr43DjEoojJFMUyz4w/w5lCEUBEh6E8gXjAMVjzFAsA7vDjdWz08GsKz+CFWPXVVrVAaIRy\n19k1gGQ1MRtI7CUf1wWh7f416K2hwjHgzz6cmETCt7TexIThgarGxn+VSXO5pr5O1/Fs179fijJE\nLmwfZInZ5GW/PJnyfU80Z3xD7Jf8tA9KEhVmkiNE+SX7QVCho8sBVQhT5B26NKZrKHXkuFWKcBsM\nBhB6mZkvndJIuBm6ALke5fJITcrvcci6rA987B6eGw2NVJK11fP8ugBJBkmiSCxH3U6uXThxgqMz\nPujL2p61OUB/0gPUXs/sr7qt6X9/kYDGwejPI9ievkME+XteHvCyDtPlq/mjoWYawo1wDIP2NnLV\n+0QatxMMZBMlG6naoEf4pifcaMe3CAyIAlbYCkFgKoMf0qVgdHd05KcNusDkLqz+bNqx0PyHucx6\ntQNR+G/WKS4eXcAdwTudTPLXuqY4T5dXr3EU/fhG2oKFgHJRrAIllJQn5it+B1ljBrm8BMXVZC50\nkm/y/Dv2k1RZg83xH6UoGk0OEw29nx+XrBNqjLBViBHSdzLAg7XUs4irDXyfhxGycqBdvG0a98Nk\nxNU46vJazVxZWSL6U6mAe6Sv3Sr9jGmNIgA/VdbNk/SIP/AhthEjNhk/19pheo85ryTp4KL24Vhw\nrSotkbHebmTArYBspDLozvV51DeBkxnLdq1AwEdI+kiwzBbiud1p9rJEfRCLlqRYOI2rNY48L9Lz\nVwjSLp1+SKY7ERb2h+5bygkAImLrivJNuv0yj8p03GAPfu6DwfwlYjr/ZSn5C713pe6Imf5odEyk\n2g27gNss5gKol+0fnIRlZrAdBphbK+HDGns5LVFnXt6nhEEzzrhmhY5q8YS8OBSR09NzveOjphSo\nMFsa7DV6Mx6FidSa3xeL8Kiq98kSg/JzKmT917YSdmFImgN839ZxMPonkiRYfizHC0bcdFfVJC9P\ney50x1ZvNhADKvxaQoVppfhgjgY4RAL3yo8CNeL+8diNOvxxv7VXL6VmkVHb0OPSK9T7jM0UNC7g\nx2kdywCP5JyEAE1ZYgyfhp0cZseW8D3oJ03+f6aWUefyoDW+U7lhbahfjP9EC67VrkOC0aA2r1qb\n0EGdy+Wgbo8LwZqlv+i0kT6JJVzJAs9m9mIkVRdSau7A6EtZ++Gui0K56HTnHxdBZpKPLfaMY/Vq\ncO5ShwiXPBEzE8G5dKmjHC+z12W1EDxgsCLar9+YOAjxKhgHkBGfg69+NmO0ydwiFZtkb9kQn2n2\ncakas/WtmPRcBrFKxTJv7hrqsa0tATeeQxEfLYe4qtlUzpbtLY2FdoNRQlSxUGJ4pGgiCSx+x5ri\n5dbUwJzYin9/1AkNrajyQ1igqFH63Oe5iA05U0OBHL1TZbqVJu91v+1hHGccThB7kV/xn+sWCL0Q\nmMULWQqEWLR9aFsTO9vP+2fvOf6Zwuefn0MzofCFTwq/kYuMgyppHBeqD0San0S3+DlRWFbvQxtd\n/2tSB+nGWbiKevmP/K3gE8oRdXigzg7xbPH+gh2lCC0wJmKwTgQwHIC31x50ZJkg8cci6fVAAw/C\nVHXrDrjZSiroK8utPInMK9UgiLiJZaxnv6VMTQfV26pYRuUPBEPpZ4PLypuOIcDs1tS4X6nUNDU2\nfNyzzsyS7Fs6nTKsfTb13JGw+dOOt4lMUIBEU84U5RQKL+jrymEyKK/sSA4kuQYjQXLCHUIIG8G5\nHUgZ9GKsNo3ugw6mpQdnfJ5cW5I10H8JLWrMiCExw/s1EXPyeM59eTd7T9tDoN1rAZKPHG/JN8dV\nh0oYFXVBv9sIAGpOy1+yMXyrapdwkmnq9M75xOw+4tdRAWNlhGUgeer4qaGwM1AiZOh9ICdC5zLx\nBQ6+b4pwzgxHxvbCVYSY3J/6A1H2OWZ/DJsHbkCJzKyyIJI6c9Sj+iL7IWOEz3kPoTdwojbxnFjE\nFHyzNYqDISswQg6KXYsPWTEGpB/obQREvd+ABflTfjzhr3Tjftzcg8LURNmOgUQANWT1DWQSbC19\nmfeCmEA3Y+mKQXkzlCARoH1uXMPPUpVC1ipWTPqeH7TcwHjaNCNhXgDS/uk2Z5GBD8YiHzSvAuVf\nKZvULyg1j21LI/bSkfQ7+lk8ROtqWPv7/JtmfKo4EJbyI7aQPWjlTqdH9mV0ELtfD7EbTPEhwZZQ\nHGWfHrL778ObaVgVlJ+4cur5V5ysxaYVfZvWa3RzOCv0QqOo2lYVW6b1BV6cZPLYruo7o4VgOq4K\nzMz6Tv5RTu1X/Q0sXm1kmGF9b7w0Pc5x3QBxIGCO+NzcC9HZekrjxRIqqqG9SREDtovJy40tvW9B\nVLyL0e4LS6wq+BG21T5Tm3wStOhCHnyJAneG91iZNFnrTY57YkATwIja/JJiSnDtzisBcdOXsnE+\njF+WIPe/OXaP7EXFwWnvQcMy3CEeH0v9WQ8R0k7m5/5LJUSKZegVF2vImSnXZte3+N1jLmIspK2X\nLSW00mKB9e7X0tmoffFcNa5K91v5qCKZP+jH9FlXfo6FyNfnHZeBtYWE1rFrWkkNoyffdTydMxU3\nHsE7+QvtoAiGifQOxWPvyL6jtcKpDsPkZKwWMaDS6t6CrUW2+7FIzIySi4GPD+UtldMfOgfX/xY4\nRwOLpHM0qz77Vk7F8r5igDm3YdRUclJRj/9p3PhuaGURCCOfvYY/1YtGyn4pRScUV0eI5mWn2HkY\nPB1KwhTPUTGwVWu7Y3fD26njzSehEGb15soneI8/j2u57nBdio7e76zBGd1Ae28DCxlw6eheUL+t\nVfbb+l1BrerQeAHVxnm+duuLE+rNrPfp+17NGTOlB2Qf1rcFqQWYCmgEI+VzyOhWARntifEQ91cL\neG3JS8IW02lPLDfwgGnw1jdsBDrP490+YoZQxAo1kmK8lSjgUXuTchXZtHz6I8/mHaTDsZ3ZJQA3\nNXIjfP4KlMMnUOG5LiaeDZ03uItPx33c7XIlhC8wCHIeOQHEnRoS7Ah4f7M3FP3oommN4YQxreJR\n/uAHpkr0sCdoRVU3J+7N2vwSP685CNjrqyl78reB2aX7Ty3g0hVKTHlyPzRgA62N3Gfb9vMrk+W0\nY78yHpQHiYOQTwAsjZvyYBwT9f/ldXZVwC1YIvI20GQ7kL8uvhV/+zbXVzv6kyjHg6HZIY+D/+rY\n9JnqgDOXkANYZNab/6uv2j1ojjDqBOeZShxkJkbTwoWc1yT8OmnQVIXLmeGTpGuabFKI9Zi6Q/06\n+HPwkG5LawIar0MHYUs4lb8X9uKIVauJZHO3fCfDJpfE7p0weI+DMayYvriGCPSu2+0cO66waMD8\nkoQKpOmFxHOrio+PflCURVPrWAdtiOVWfTKpPdCUgyjcX/0SNGNc+GsKLpPgnseR5baF4rxbWWCj\nkZQJhVLuPemR09jsCHluA70+mz9AXQAg/pa7bfPbMldU69lewVO7xbwqdUDy4hdTZYJCwX9TNp1P\nNpCzdGsgoswj/88Cy3icvq+rPBdxfqogbUZXI0ZcBQuBSscM9RPagLxJRYfOWbvPYakgaarvMURQ\nUKkmvS7oHX3jyOH166f1V6kX7iU1FtSODnMP0RTIiVB1jMY8PPv20LD5653dtu8nhpW/yxdeaulB\n6HrUOModOutJHPogWpEpYquKf+DCjyztBIiWtsXp0rIdpdackzsWc3l3gZdiLtsV1BhLCsj0FJw2\nU26qRLCKKxk0axjYCW1xbCcNn2Ui03uJuYtzjrQJU/ng+M40qPAoIOoonXkN2va+Z/XjAlJvXRLl\npvwhi82zybVUV7GX+GBE0mShC/h7yvkzFiRrRDA/RwRQur+2okCdE6dK8hr1zzFE10JBP0d9TUS0\npK2XqZN2VJ/BQSHEd38SApjeg4BZNbFB4+Qm5v2hy9XGHVWFBr86STemwiPK/HTKyvHbsTG8gt94\n4Y361rCNBFPqISw38qIcz8ooUjFi622Y/CWCjDz21lLX3iFDIFf/ZxxqVSlJM1NoqsTHOTYaVwF7\nhlfj1vG0b3l+cGCZNArEGD9fxGx3Z8OwL7Bzs63ULFNDz9lM2zFr4UU6eL3vuRH3yJfuI3H4I77P\nffLuBWlPBg9kdeOw+bZrrzSRIRmKmYS6kOz3Uyn/i0ejd+TPM5dR+qHmiFt7OZjjSaf6pYIDxuFA\nDZ6PvZDVBcTDMavNkIcSkwsm+B0NwELE2BV7pbI7jpTpkuTQpZAIcuURtrHRXOohYiktQX0f2DId\nGDX2juPGYqAkqHn2O6TuzV+PKfUMTryW3TwkT2rIqBqzrGBtN1hU0JVrCaZAM1J928FQGECowe4C\nYw3phOU/wxWfcpsDd+JjsNmQP1GrNaLeCvX9iiM91ya+u8I0UPBSSpBhbDExnHRQ8x8L+Nxrv2P0\njVZpcPraT1DfqxmICYoVm6AY7rdTgJrjclMbYmafOsUk5wRRTQVAYPBpGcA93u8qLRqEvvDHhnS2\n9RKzGmNUV0hKqNIF4f426z0tJi0IkRW0znccZmt2d8TXKzYkCOfKAliSBqpZS7bodKplqMqc4voE\njaPXEf1vKkbUQOV5HqmvUiJPI5Y7jQrosCCg5VL2/oqN5DodmIqCCTd3vdAm/tt/b0IuI5mRfpP6\nV2Y/cRCrmE+MumRavYpcem+l50tCbeSbglB4grrAtBooNSiWou5vd+6WISoDxewgOeJQGew6HhaX\nO3eGe6KfJ6TaL3fiJuZF3hZ9XXqyDuGrb8nQoAt6dqqzzDpGo1JaPScwI3EIpud4EhFE1Qti5v5a\nV3Vl1+6/UJSBa8V/BrByhZyt7xmrFz+1Bgy6E+Z8DAH3rQXV6mKOieQAoUPkW2mh9tx9xnFpbSsZ\nTPYhbec2cj4bGLI5crXAxEScCC7qH6wD4Zgnd+qNl2NdDJqKJO+4hUlTbuc5wXXvarGBBhgjMHLs\nXGdXVwHOm+Cc8rKXJvr7+5PUUtnwD8gWKxJXPimyS72D9CW6d7dkhkbP7lFlaWAatkkLR5ARwFbx\nMZAF9W53PRE329iWi8zBjf2WDZBSN2Q0TcA10dOE5nbnbfeT01IkqmqARAkQh+nTwL9T3bR2A8Pf\ngmwCqBj1+5rRlYslJ8CZOrLDQgDuLDJ0EbX+JSDcQd6jEyne6hgAaoZs41ByP/8g/PE2alqR1kRZ\nTYhiSUk5FbaPSLijYoL5o1w7Zy0qqdH/p9GBtm4JO9CVzc6hI09H8Uk2lQbJPzvt9YSlv3v92sQz\n2TKxXXtBQ+mUlziFQ/8BYitiRqoE2cdR+mE5f1X1YvM49qIirMbEuumBGiHJqvkqNUZBHU0ZgVKg\nvobG6mF+vwwH28e3no4tQ7zOa/fDVprzZjLGnvdPUjym+XCgbrKyypqUWKJ4/T/4PjaanyzPvvXt\nRlcGp/nhqI4n2u93okHPDK6jV/5phIyTYsLiXu3CKgu+8IRYdXYOiIo/e1Y5WDTKYgQhmBVshF3g\np1hGuj0SPHrrAaGaEG0egjAyMEWxwFicIsMjvHDzms9wj7SGPo6CFt4YMfar870S3Mr4rqPPTLEl\nKaX83QSEnw2lHk1wIWIFRH/7JbyQRSmJQSWe1dyCNY3CJc9ckpBwv+ZE3JjOz/eE9hu5cxojJXoW\nlr5td8y7IAWzChiI0YLBwLJRGcSEKYwgbLcICqV6JillP9J4X92YlMW6BHoBsMhB1DOl6TyZgMNQ\nVlZGWfNoYelupoRkIT8M7MzXISDSzqoDIKM5mr9eoSAo8ib6YK3ODFN1Ipi0Hm+qUVh97Qb3LCXy\nJ6TLZ7yBPe3PyN9tI0DKKMQaEf7MIeR/pJVXBGsWw1J8lMeUKMZGj/PNQ8jCoeKR8IQWRQA+u08l\nvi2HhJO/OOKzrT7wWfTqQ8JQJWoego0wyxREKsmJVph5puuURbW1rqMZ59X/1NWVNk/LbJ1gpEhD\nRDB7m4Z37EdY60O5sOgWAgfgocCGN+qw4b+xKacYxMN4HjXO+wJq18wCTE6+j/Riq53L1N8BhQ8Y\nGzmRansnzeytnsaTfsvP369sjt22XF5RMpCRvIpwnBzhVtSbsoEOecovV9J60ihS9Fe3klm6gBY7\nO27ky2+Nqy6V5sFI8PXp8SBwkwq5pNi/BqYrHGV+KbX8d32v1RUYbRrV4F6ptibJnNz0aU+HQQBw\ns4RzTcJUIJhlCEM+J8xX7HwyaUGYXM4Vblpw6Pdu9uJT0tjyon29wMG41c5BLhYFL9bVxSB0rylA\no9dhCoNanyu2VfmWH0K1eh+YJaNXtEb0ysEmWhCOAN/BB005lvi/w2S97ehdtGEWfujIFXRsvCgY\n+RCIDAxVVZqHL8q746Y3NWuLClwgx1vHx1NcQUcDBNsRytgo9Gb0DigkKNt+dAAIGmfD2l8RTA00\ni2rxwGF3erRv9z6mzledqzEO17RKC31VFamUnhcuZiDRaRRCBnE8GuE5BHaK8rw79pL1YSIawfMd\nLK7hHkbaDI3kT4s0uTl+t99PyWMS/B/0yfBkHsKDGfriLreKrAncpEeUpJVFKdFGrPl1HIHS5ZEX\ns1gVTXjNJJrMestKVYaEs4nViCstGD9zSan6JhEmfaifIkJ7GLKw+NimA9uOzyKvxUxfRCCFUSvF\nMprZGCfJ4ltS0NYsdjAs1KQSH/5sn/PQ6OIeDHlZ/n3Of315bRk57pzLC1/aVqAi8XLsSRefF/uG\ng/x4R0AMUW0mo2mdnHH/TY/0iT8LYCmwQO5G/dkxHjhJRFJDZ3qUZid99q56MwmCVIj6WDNBu+KO\nQN6QM5N82dHzc1QI4OMalKCyGwtF1fJoK6eNGi3dVQTES3YoHYpJwy9mkxPa0rvrWLS6/4KyUv+I\nEDZZY6lbAg/ozYCu+01v8P5fYavZmOXKq7EICFKOmUroiCAKQb7RAGvnYqGcYPcJRAsDYdAoIFDU\nroKp2Ovcei4dqjC/IMmPpx2utomxn1moEPZkeviZ/h4Jw8M+YkT9VrkRWpAoADxDnDqVJm9CyRZ3\nZYi06cQ7Xi+nISoqnuU0wG4niseJcLPhRyK/eN25gKr33zC0KA1F90dGy8K2XjjGkAy166Fm+3nU\nL2M0OoqaJrHkmiE5GOorVEOvOcgQPi5mcLYVduX9edasttXX1GWuqS6e+TdcltrvITA2mCaGW9W3\nuLXjKkSpq982wMXZ6Lezt5GVq0xxPV/hocBpYZGNk1GnQrKh6TZ2oDCwL3BfXTqGPrO2BfEl6Gt4\n/y3kZDSf1MYEfz0iQOKOy+lWAlsnuPolMTRzT1cOGY/Xo5ZfvbKryDcTb6bhVTvO6/ytROqjAUmQ\nTHPlyl8CeG7hdq6DGm/TlWk+DtDGTXDeiF5IwFeBRsJPlaQ//IAkaAdtGnFztK5xLzNvyFs87v/9\njkbEu4pvPLRGn8alKJB8ZZ/E12VD5owB7dVz3WdKnfFS+ewUVFFKFM/LqRQIoLDfau36JyDEBIoK\nCc9QhI4knWpjgd3rc0Ror6hYufUfdIhZvbYz3935zgckWWECuvAIgdz5z2ckO8J2UHAmrLdWFxtz\n7NFYheF0uQVqIWu7hRMmfPVEgJNVslEfrtSENg19NvNy3vkke892kD/uoMfkVuyjAkS8PzGBrXJ7\nSQqI6VjMifzTsYMS/WQ+kXXwPhjx09QEncMmZSp0thPdg5CZk8eEvrZGprWuaWpDs9S3lN+NV/qh\nEaMcIGIuEMxbxMgD5WtZb20rxjLc674wYAzoVZKd1k0L9/5C0iSgJUwYBe49dyDOKYUMctmkESxi\nVd7eT/IqusXB5Q/PLFKKSpIjnafKrHv8yGyfnTaBC+kzTlVpb2G++mJNfwSbkDuqAvAoKjPAVHv+\nqzQVAKQ0+UOmw3T+29c4atCHzi2+uB2N0pr3kiOHQ8yooLRMdkn24q9cxynSkIZo1/dARHNNdxa3\nCJv1zraDIX2a9McxBdYXYYPeFRe//3X0Icj+fafoR1L6ZnzJ8pkqjZSGr7s9acLQGxabvRMGFAlH\nVSEB3Y7eWvxapneBKniIGGujM8MXaz15lv9RmTiEqxfRsxRhgthrhqNWOlGWfz21p8uZT/iV0h9Y\nfzfelebsnPN2uqnYGEKFTYTm43VLTKdViucgm0FyCsC5i7j0MIw20+J+3xPhA7x4++Bg0WIc2oa6\nyZWBWrw09oorWa4VXS9O4jd/qCs1lXQO9qyI4RaWmg1w/2nMaDgx3InEckVMCboMIeiaxntF0Oan\nPBiBdb1PPzTtsMmzVNpv4Fjv/cOEPRIRFPibNg3qhLCCRI7H9mgzfUzv90GEsJjMVTCAhWsuuHo9\nwGzpvadtd3ZPmPsOFa01NwPTRw0Ka+zQf07NZ5o1vtUsD8QeGQdLQQ/Q5OKw2HbA/bmpERHgtPaO\nU2pjfnadcng5L589GtL1Yn1o8CLSPo3GBOJXJ+EEsGHxmSytk2TceD72Fzn1at8SRZcjtsb4Puy5\nD6IOS7UeaGPeKQA6l11RgJHgfZbUgaJmK6tPYXZqXja2NBHNAlJGUGSUdtTyFwrSw1v9Kvbta3nm\n9dSQggcFLN0jfOh4Wx4PkZqrNAn4aYXAl1hVDrYSJYeIi/g9UWvt4lKEKzII7sSP+/Smvc+DQI7c\nKrUPoBrCwwSIULOWIvTrmc/9H9lyRuvvalVYoO1UJ4h1QZ8l8Awyua3XBfn+LhsE5y8En3VMKVBK\nHDDhGXOo1ly3kQ8NfiYxpwcHcNdNtrv6maO8YQ5GRGqef7AdwOaB88p4d8Lo4SDu62Dzf2fkdySN\nvx+zps0lGn2ew4IFCknQaUtUaHVrSDUG/NZZQabVDl4WAdblcpbCOW8uTiNoFIKFX8dP4RYXgq+N\n0wODhInglAFqObFfIC84RBfDlEA6t/45rPMvS12+uDunWBSZHyVY1Uwvwu/pnI48lV9m61OsJCLO\nOIgrpGewilIwhStXkjxdI/PB+Vez075WfTee96epvw8Gy7kPD7RFvqrDDIrSGm93FKnRHplTj8O5\n5uu+yfmzGBWYcqCbo4mJK6V0M/SJnB1HCGbgLiRxGy/WnHWjaYx9bBqMbBHImuGlpEzPmfDKvgV7\nAlHvpdpzcBlf2iAEr4jhpXqh/KwnRQ4vJL1P84YbChWf4s+IKE0AZ6f0vl7phKgUVq+P+ULvZdoT\nqnWO0Ig8FCSr/a6sZumTd2V59t1HdZTvc9V7LHv7XW1ar8fwPredD5AYEDMepb6AgFxec1FiOc3D\nykbfBhIXJE6n+Yn+BkBfyPaHQtr6CygbQYqPxrWvwqNaGqiR4M1+SnXc1ZPUCuO3jpsqErNCpGur\n86gev9iN95nwRZl1czxWVa9z2Vups+DUDYNl6OGsA3VaU6eY+zfjdw22WdfBTQW1yLZbKdfPdglM\nk0W3fK6xVQmWd7Q0MFJx12rohylS2M3jRt6ymRYDuj9G2x7e5COQAH4HvGSj1xQao0Oqt1esrJ4a\nYIqOffOvsSJq932yvAK//wpl7jU/meranK6kL+SFodAzXhE5O9i3yUroUaSX5y59xIfZoFg4NHP0\nM7zEBF6QB2GW8onP2jBMjRx1c2YyjCZC9I2gxLVNFMuAynr8b5R66ZPqvrh/8y6Mqr83orbrcV1X\njrDazLR6yHEOtNQ4bi8mN7w1RxzLuL2h058RZGlSsTBsO8xP6HAr5Kp2wBfbvI57lK6CxqUspCj8\neO92O5CNgGOfYdotXRnXfVffA4XKFtgvw2Me/hq6OXRjQJn4ru2BJA8kDP43xdNfLhkeKIZM3AoG\nTcMCW6giOWLiADsnkr2ofGgeUFbW+ngIOyctXvMwRFMD+1K5RpwKmd9uVYsHK5u+PLBnvBGoyoS7\n8/m4+m5zQh1ucW8F1QfRwl/sKSrRq0ciF10lQ6zYZB4lLAem6FOmUFaoyuBVPiQdDA1ZsbW/Oy9h\nCVMHPZwPrJ3UnrPvs6YOfXs2Jlfc4nyTMV9gez2SwA0MbPHMnpIcvsBYMqVf1NbZumEG5UI4mVji\nsP+Lo3Q+cV56vHImYilS916X7mZ0gHna6WTTGV9UyJ+Du3k0Tl5TlYLHL/ob4uKWbj822Gt7tv23\nAJnMLGCkgZQbYYRLwv5C7jFKxzPsaYrdBbnhN8Hzj8uWglOv5NmXOcg2pNyIv6Xp7o3P4/taZy/s\nbavizNn1qFu+wczAKyYeOCD1GOD150qXMwDfJGIaD722D5IfvLbBJkBz14/nzS42fO+i/NSflxqQ\nIh8W1dHgXZR1+1xGFhfpNgJ73eVqPltXA5/xNtE6EWKAK2h01+j9T0mPP+TCq80DejbANcjNu+ug\nQ7qp1/IN1oZBnRQf0DNejhOdZ3Ik88Xhwy2Bn0jLmvR81NTNbmVEoZf6/LBhkmC++d5tWUODaE3V\nMmjV73rV8eAB0kRkj3yGu5GLwWEtbau6TqRGb0BcVzUlzqvF5MPetFqKTBQY6sJENoTXq1XQjWm6\n9wH63KFczwcmFRWNgBpkvjQZUGWcCIlioS4fuoQg+RfiCszpQm6etlOglZq6tbo35s7iHLifH2fJ\nXgBvGhw1Mzh5WLkhF0SZtXs1flSvmLCyJM6MwWBe9Vg1rncHvsaqt33+9kknBEsl8yJuvLzpWHIq\nIOyjgBz9NEl5RNUhBXzOzvIRK9F3Z+fejM0uOy+z5JQfMyUHKAEhEtGivvnuKn5Iv1yGYQbKcWzf\nrLxAQP1WA+5zJeTLRbU+kco9GYRaVaIvruvNy1wYXHcRnwEui9exP//Ej02tNULykhUHv7P7iTnf\nYCwad9m+QexSnt0Sf+x7TTYZGucEUC7Y4EDC2m9MsTtXFuhHgin2e9eHMTm7cMiFUf3O8h8Qszop\nwzWvIQZOkkv91HzJT8h4L2b0+s0LMTK978OOGCGHEcqUPGyAWN7nOu16o2UjvQGFPn79rD1sub3W\nU+zCmNvAttFgu659SJhYDXnvhUoNWhfY6acclg3KD38v/SOAfl/eq+85NRYWvJtweiJRYYtk0vVs\nu6EitsHfSy055na+HIelCMTPbv3+3OwB8KNeJGveU0qxSv4okxF8YWWxztNlTRVWwx6fC7LrHTJS\nXhjvKRWBJrdBkAn903FdNO406+gwfbMP6VAaTCMo2gsunicIpS8xTA9jcMdcnCyP4GXLvQi4UckD\nQNgqbWYvw5fxTLOWyf1Qu4u6Ul1cRBRNRqZ3sZG1iD58EIMSS69VEvYM1w5CWdFFkYZesNsF2ZAC\n4RTSQLixyOWbPHcCckgl3/E4FZCkIi1A0xsbsyirad4r4OdBa4ELnPi0ASWPuCJZp8QxIx9ohBTU\ncXKA+rgTrCgCLzavqrmNtp3Gr4WW1sfls95t68GeO6SScz+13sR+D3gkP998Q+3+9ENk5i7fJ9/i\nQcLd8GqnDZaJ/h36F7+cUQZg67jcA5APE29UEhwTU72sbZWGcGykxoFo6Wu8gG9xLNC2pPVSdS6a\nF55fpU0b9k7eoRIM9wJyDoF5jVRrL+wNULRlvZpfiLOpSwjUKnZ6ljjKtTt6qfsye31ZSpQbTEDi\nei67gpANY9oE+l8zI+oIf8eBQod4TXK0aotrRsx0T048+WvCuIiR+iczHejTE8Pdi8+enWorNp6u\nCcR1yfG23NU1xEPqbMjQdnMIw2T7xx8WBpnaS+nBJ1gNENmT+JS56BNxD6xy5OvTLAQXjtm+KiG5\ncnsBBCY/Am/rByb+pNGepykPoma6lXmXc5FMpKsySFKxXx7y5zorfRE9gSbCmTG5Ltvw4142R91i\n812qH7JQQPaumVCKm33BGCVGuitsJfOfv/98p8oQPsV6SftmQusOjQSyn5Qm+dlpy2+VymZDEnTc\neJlGz99qQGTvq8/CnYHNoTodEyCv3uGGGoA0TqUo53dr7ssSRbAFgdsyRHMDxepGAcjkw7T6laTd\nqtTg6VF8hWTkI7MN6+pMfl4m1JUI3jCTvL3r/vgV6Kz3ppGiAoXiSzxy4keXJ6PAPwFmbGMVtZay\nWyEhiliGvUyzaYlZPptWWhQOtNFU7fxXPiYE32GVZIx+SiWJLnWydxbRC/WlhwgNYcGsyqSZMFit\nsNGCmXGtYx50tvzGxQwzehYg0nZ2T3/PJDCx29bJ47EO9lmaIUUPuHUmene0vI1Pu3WArggyDcZm\nv2T2/rnn/OkCTuK9/cnfLCkG9PZvw+b6Q8iqL81fUCaMHPspDM/w/iL0pGUM68CLdUwOhsuz9jrD\nADfcq+EHTkeSm1tRfg+5QtFa4PgsUd1tA9j3+oO8OS4wuERtXT8tItcS8PjZuyin4U0+G5ec8xRq\nNXig33Ho45rUFp/dzkeNN1A0r9jrBnzIxzHAQZgfdTuGWuttmgbHPe/8AhXQ1iFepoTAzqrCqBln\ndNdMPtSzeK2ZoMaHjCWqZs+s8/+1seQjregjKaPbNxtmkplWus0EExT+udkoO7IXvlQq7BgPYo4r\nRpjeAfQC8Li0QA1OIq++poHELmQg9Sv753ldrgUe7HlrntwA8pnVfa3P2xWCC5ti+tEdtMl2Z3R5\nahgZisYsB8c1LNpju99Cd5thHlHl4q8bD77qMmBldsN89OKNqPHdYrbQUxFuR0cSUly501EUip2r\nJwNftGERUEMKhO82u2cZQzDhz17Ttkor/7NeO+Z+DrmO2e4BlNdtNXxiWIprq5n7njgKw0+Y31Z9\no5bBl4zCMvNHlQ/IuBUEEIcDEP1SH8hlHzzCrOoA3/6P17v4Px9APMiiv33ExsXH8T1i0iteJS07\nzLASBPvauUC9xNjitpan8V2eHxBVPDkLlNHX8+hobBnp5vRMSQcBO0JFm33M2lSRBE9ZNcgYf+g3\nkB2CVDaFyDLLvhVdXW034NGCc2deKjNDfZrSkVEFJH0aDJoEYzxeEnMh9d5rIKx3VYmcYHgw6JGg\nJBhUkNHmCjfh0vCo+hjMCPwH95m3vUFe1wKhOoXsIWyk1QJ+QTR9t+hZTowkYlQprcv5t2gWHJYG\nys6npKLa+KanvsrGVrXB32uysIZliELY0rvCu1lnLfOVG5o6VxHS66qJPHimhiy6XX4IgXd6zZiW\nYO7BOZluVxA1fF+ajFTsjY32A70kD/tRSPQpYwH9EMaoF76kkDLhsIobb2kYNomgtk7M503onnCd\nu64Y7Grs+FvIkcG6rJ/SZUqfoPbCZmvMJtxhS3d9eDphfgzSyg0uEcbc30Scvx3MW/Ka45FcPqWU\nTTJuaFa5sYSLgrtp0/xa2z1ZrvplfUMOfs1Ir4WbJ9S9rWOTG+MOlyxRJVANozxhNnL+p0UxBvIK\nFUnFSYxOeTffvL/9AiuwYKEGlG8TP4W0kgfeL3hMAL5gpcXggAW/2zDLba/syJhMD6Tp62ZpzZTH\nz/IPQv4NIEnBLbQy6BH4d0wGaSLfPyXvaUjY7YQ+ntuC31nihw1bQwaZ+MUWyZRcmiX5r9u7+XdL\nI1L1yZBLfdvFM+nIfXra/bYYxC99jIKFf7pNPlxoLNMW5ArXRg/FY+4oEjkoCU5VQUgZUNAuJNxU\nkjCdWYT/MrC1tV8BTjT8vgZqsUVG+9Q9BiJFhhAhyxYKch4SAtURNyGrLtp0SSnIYJ3B/ZVjzn7I\nxuxZZ2v2AflGdJfcDL+Rr6aLQdbjGj/+0zoSVfLZv4JbXBQwhr85A0tkeg6cGcxR9Vza/zc7+M6g\nJ5ccWZqPWubJGmJvKwm8cnMa+pcVTxa27WsCDyvS0Y68jalHosyqevLvcB3xDPTsn2uHlV+VpQcj\nV0VFxSXFpQmg8i91a+zS4L7xHHbrjcRUly+muThjtgw6ig/wF5IxtSpj5x7igdPnhA36Go4s6ycI\nIiK57NlcBNfiebdpAbi/w5sM+taV1uXqviHauEuFjtQA33Ok8ch86BdmtrhnfMrEJ8rHapBXrVht\nIdcFv0tQUfg2nx+8xWmAW0dbKjOV9EeqQp0I4g9LeZD5GoAP9n3P9uxbxza4GAUXxvg8YQn638cD\npJ08vWFIXQz+R7QyyTo9sX+L/8OhlUe57VaGzoGGHeg2RfhPUXKQ5g4vkHkUQq05nbCCuLIsc/NF\nA9VSgYsetAZd8ab3oI/3nSeVQn9BqI6eeK76MN9q/uGinlJrJwDKg2lAwE4Sx1NtxZUDL5Qng1z2\n+lwVJzNItzXwfBtFu0TCpNDRouYbIY10OgzqrgN8p1Iw4yC4fdfmvvoeJBaWzueEUdTT0lR9CbXg\nnCIcYnStmgLfad7bKNKuZF0N2BdtTyt02DP4LzxwMUX9zaxXo2s/7FBfFcU3FJuvYBvJNxclo8rd\nK99uOpDhoAF68Cp8f3U1xGQs9hcQFsIiZxeJK3ILBP5gp+CyPPneqHwgN07Z3h+9wvOFgwV7PuNs\nihcq9INZE5hivSIUv1J4uqxZxw2YOvj+4XtgILMDsLBUh2/CeiJHDnRXHHXa8xyHN/VEZlvP995w\nphboRlruPD5mR/ocPYK7UdxRiSWJM3aJzUcLRi955umxUm0bw6N0pSJ7JahT+I2XC34PwpktoFJK\ncnszLXBWbxz29fPMUkVIgrJLImaca+mZQRabAzDdtkZVBJfpiL95/WLyAlyEFqHx6pOn9YdqK/x8\nls+aAzMGETkfnoOlM6je/dTzj3l6Qegyttg6hacm7+dwNcr5RLP10+lmLI47KpEZMRH0JtDps/ey\nRtCY/uN6O1UaJdOhdtyZCpou6ZZrao39nAAK3hsYPS++aZgjVAM+j0HZPfDxzqTE4Wp2AHE0vEVb\nsbWOC5JkhFUEsNgxf3CZZek4tylhZBFe2qAPmca7Nr8cX+/fGwJa4zsstW1RSHzzXp+ga7T04RRj\nqKwX8lhMp83DKrFARIncMkCPhC9OchoFv6Gq/qOjB5ENUspxDy4S/IOsNdRpKsjsoA/E6+aiSeQp\n3DWa071ADqC3V/jEDFQxKj++OP+/pINq6Y1craLIugETiEcpuMZtIfeNmTtUQ9bQlnnIHSMgiiLk\nEYO/fwfSTz7trn+YBvKL5vAPEgd8EXnJTQmYglGi3iPtfYZCecyOfq3JykNYoLGzlc8l+lgHht6D\njBryf+zujUdATobQ6vmyUQSCtmPgv044olqWdpLhzoc9ASuMzv1Tf60b+vX3nQLZbSJuYh7SHxUc\nGxaQJbaAUNbtxB873Z2xQaexfwD0XIgmIrV4nTsGA8CKeZGD44WmVGfF2zAEj0Suw90pvxZ6ak52\npnNXRoiYA1GbUbaAPifn9es5nNMox1WMhiiFqkfTt6QT/LPDaI6pctEEKbhZABvzuC+AFV6ApkFQ\n9sEbC67oJqc2L/F5+EIi5bC2E4TuVw5PGllkgLBAmBS9ZJXLt8W/7AZzh2zXOiztarPYrGxcQWQi\n1NqD9kbqMfjq4GgxdfOh6GXp+/8hzguNrB0XOLT57jqu3ukdyPI/38f/tdSR8rVLm9ctklpFxIp1\natcGe6ZzLhkmrAWaEgXu+rkvalDeJJzYMCdssUggP9sbyIBqNm+bu0hs27axwtzO0aLTdEmRy7BX\n02mW+0eM4axPDPBXp7Km1zDETT9OuwhMcrmk9IDiDrbaUj5u9Is6RN5ZNoT9chv4XZJKvLR2ut3e\nQGCvbdUAVHxPLCOslYfGfXiNFdwL9ygx5Xv94ULNBynBX65Yc0v5uokgRUlQFr4KxsdMcxhnJrjd\n5mKOOdcKDyXcYKKk1YrFmxp2Mqa1iRK0gm7BoGrH6dy8ZY4obArr8X7BYzzkf4oUx8I+5e2BLyig\nSCmP33zMkZFpk/Auh1rgfxz/PbMciaPSHZvrsiCsT3mIopE+JgltnrrCcjK7GAdB5hrTS3w3SR1y\nGBavVYxjiEqnr8WlVGP5HbH08fIsOBlMX7LO5sciII0cGlRpn364mCbdp91BslmVrQoxcPaj+TC9\nO0MZi9C8aOZsUVk7GGBEye2EQ6zuEpA0PE6X2sUd4HqfaTrtQg1EivraNouAMLztKnLgN7pU/ETf\nK4iMYGGJzip/SjpXL4XIr62c0IMMYJzIXHBaTyrZ4idSxkM6S6Q/VUPOjO00HKdaRqOIH4Fl7siD\nQGdPpuIRj0b31W/7wIswcFZmCuzoZQGgj7b7P4nLZ1ugw4MHnHQ0p0zWM+A+R01iDJDTBdfEPSsz\ntVdGAoTuJ+O5nYpHMc+IAOA29tvUF0hLHKvwz719ElO2436olcY+xVc88CWad1ptcp6aodqcFyUM\nOlHeSnAgLnQRB4lEfJKprHEnN1TrjL67oHO/cABupwcFGBhTJebJn1u/nizRAVf+CKSUryUX1plf\nq1Wg9A52pO4nv4UPs5j2/i4PgDiSZY8dZu2YgE043PYJ5dEjNrmyvjaWkjFwtziqqKJ/zAwzxSfY\nFx5VOVen0XsXcoLpFHKH06Nbml4lnpDAxCdCAQlBhJagIUqVZUEIMzzBgaOUj7Y0E/Sx/MU06AAm\nb+hjKhJ4ht+9FDe3q31ngEpHms3C2CB73sGjLP85VrkgocaNNOGwWb85+dtp6SbR1oOXKGSgDIuW\nWa9nFDdb80zA/9MYuiTLZB0pGf2ysznBH4gVaJ86M27pJbE/oidnAlTQUPvFB38TOYQNTSnCNbmC\nBY/7Vz2hDC+A4DHGgWSJ/wWGblIidbsZpgHg1Xo8ekbgWacICP4eJRnFY0h99QUPrb9rr7nSKoVD\n4fgt/CUrqX9nvnFnEEI8eiWD+oHVrQKGRK6TnOP/839TpPTKpwfa5Qlp8j3ABCliKMAkPP6HOX+K\ndwjGgNzWtsIMFH+5fIx94smDLYyUxaUiQLsy44s+y54eVCf5XtKV7oMkEfvPoBAXlmhHKys2EraD\nKquLZQqsoRYc87pUW7KZ+/FGw76fQKeccRJfucdYfj2hHBcIaBuJUIPKrC592N7/WwEBhSd8nLa1\nLZKRMwzDGxXGYlmDMwf56Zf6OgqrCqSI/SnvV5mzligO5Au0AT5y8UGRR9x2hTLAohR3HhVudEXO\nowk0UJg8YDcoxxu0VpwoNbMLIcaEY1pemBsAdLqJhGMTRnneNxKrTtSgUwFN30HpP1fHg8FLhkHd\nFEhXXm6zT2mMHNhNgq8nbsHlIZj6lPdOCqJht4xkSQhmq+b4kwFjsVIOsR+y6Mo+C1vtZM89MyCi\n6SWt8fabXIQhJg+XGRqdh6vVWl5/YYso5T332zDvVQTlJAIu30bYPbZTre/xqhs/eG5/01Gy6nQd\nsONvdiK5TjgFj1gAUliaaUHi3VsgkrNExifz+rXAoecbj8lpEh36t3rEyvXjjGsAl6nV1UgQiCOU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mjmT3stzC/Xv3U+2KUtVN3IyoZysXfApjzYPxRGoY14wxVxml3cjWkid8wTZt/\nqKiZ8+DNGhOWsKqtYFfzvK3ApRuFrMQI4nmfP0ioaEsTGAw0TGjMc/edUC/KrxwpP9WbWlpcR1Mn\nyRmHmO1G980fLf1P/q5GKog5mVjHFI3YGEOry1qcHAJR2dzO40KJ0/5N3/Pxa7i6wNIJh/mHzFZ+\n31kRMiX98q/i5AnwSm6CIHRH2WptfuJJu8bOdHyEc2X/ZykVW5x17fso5tTlUjx5p+HR96FFUaBH\nlCZQUHaHREVDgLoo37xNLUuVkMHZqp9r/Bd63iatA1vtI53HEnJpU6AsMLIsCdkY+Lf82Feavy1/\nXEAxqjo7H1QoA9YuFHqbS5WP7hI7NfNQMDjoqprgcz9/UB7xC5WYr8rq2d5mgeAbnstt5tE7sQm6\nQgLlHockY4CJK8Xvmv4d4SblYXDAds1reKTgyhuI4ZtI4IEsIdiA6/FCJ2Vtw+GFFB0zIWutZ9Qg\nvRS3DxbGOPG7mDhBr7DndSkrx0aocMGbybimWSBSg54OO8poGqinGYfYKzIcnpmV8De9rNUYTd70\nICpozYFwIfHD6uW/tcf8vX5K9TD61i5pXIBimaenR5BI2PMYIhZxYqmWN5m2C4lpq7eUVSFU6cJU\nDopA56H0YzS1Yghkaz6ccapw4+IWSfmbW+U+xxGGT3wNd/C0LkyFKJzdCEZLxeZWC2Om6YAKNHn+\niFQ0gxa5wWQPwuJ8ZhYyqSk/q1Ta/GqqRzNbWLlZC4xztgz3JY1yx0g4gGXDKlO705YMD2H1sVzh\ny8FE+koC6h6l4i41cL/DFsmJm5Jqj52bd3iigktOLK6QtleXtA6WLojTYOnJOguFYPtthxaSvmGm\nqQTuLmCdlOWgPxQizNJRMRBTiuN87BktKycizvXRwigxNRv5V2btiXkJPtyPyqkLA4WN6rCMZBko\niXN3m7e9ovTge7aNZ42IWrAY75oe3jrfzduFMjJB7BHwVaV1dNpZqNe+ZP4gzGhO6yKU6gUhhLjo\nhuML+408orbEV4f3IS8O1PfQ+c9afO72/Ivqt12Iq1YNG3EKdwt+NulV+j6oevJWc1U/vV8MrQa0\nbeVkn5LMWMAilgmbX61R6wISQo0NfBGdFL7yL76BwJ5wauMZ3beZYu5smvlVxpEwVhQ8fFxH5Xpo\noihRZCSnp0L/BG8e+f6/sZJ3g939OWCjOd7v+b1g7lOXhRH12gLTb/5yvbYNu6R73tarKDzA+EDC\nV6Cjc0uuB1aWJB/N+OrNOcVXKhZcotiTMF4vDqfRNuqt4Lr8gjOQdRbrQEveoS5Z3dGPAUi07lqg\nqVZaKQNTSVTGNdFooKDV6jxrbpDI7VfHYQeRlcfaGQ1FG1NFjzlHBtwZAFGM65hXUyuLRvTsfmyJ\nKoaS6UFC1MuuQS/l45/VFm1tfQmlNWunhV0kpPrB8jg4HzKBk9f2BfqoHchtOGcUKTenprkzbPfn\nw4lemz9G4I8Lj5ly28uFVHheaCmKS4+8HGNam+xtZvyfd5dpBY8AcoNMtHr6i4UmfWaURIdijXdH\n4Bmll6uW4Pbk+DGTBh4mPSh2on/JXHVKOI+tXmcYauiEje985N91S+0Na3tbw+coqe0WLnAcRjrm\nq0HRhBFaPvHkoNwuQKN20uBjwavtz72na95RG+VD89klPSBmoG9U09U91P6sJ18GtlDxXCP0UAvS\nYwS5AWhwvu1ZBenlPuvRWL5SCxKd60mnVbKgePL10ztCgNJWKHL/tYG5erl6R7VpWRMeuAsivG4L\nvlZh1VMUk7WcEFtlQ8ewoghZgp/iUiIGdB8UYFsMC2n0jF2KlbD0qxkuacheyV42MhjTNrWOGJpP\nb8cLqovTnWaUaEQR4ox7qhg+i7lW7pFMSIP9k6dZSVrywanuiKxyZEM8txnRmifM5BWdVlFe7o4Q\n6LDdZw4TPzfPC/79pncGr4kcfXBeItIkCz2Kb37YPXMbPvCbBJ3buirX4xlN4U9Fzi5U0OI8rI/m\nxEaubhXYIo1C1wVEbMmhjjAYqm9mdtqwtK34nKt6UA8yzfBAKUcRS9C7ComgLKAnsqqYmQ6+d9du\nQEqBOA+dGyP5ei6S8XQuTmoeHBEzJtkaDcSReujBlwUYKT5jEDk0nET2T3W05RN8O+I1iuCL2zEk\nCBa9XojaCW7WnyD9fHIfIlVP3k5fyrMDshYPSJRoF+L3za8tcsFxoTB29Q6BjKAxZ/R2U7piuOIo\n3MRAXcIwBS55HqoJGM2SsAP+FtMEdbi9rvWNynjnYLT3VWrn9y4dpa1PzuBknAAIADZ1iJy8w45l\nKMoZndthreWqtx5WJ/NDeCbjKlRUXo+VcTOw5wfPGjtROIJrk+a0pBEvk9IgkLPXS67zcTg3SmX6\nqQGKLp8Q4wEM9wWWnL2h6O0wifvd8KNCNPziDdUS1b31LePR/mZo4s8QhVTskrjHFAb4QUbPl7a6\nHLudISZ7yV3Gmp6lxCIVCJYIiPkLiVfwQRSQViwIUWt6BCc960d/MqoOz0fwpsTkdjYr+EqA4FGJ\nwxJLPlTgl2lMVKdWumgkU6nREoX2fmCnx53Jl2LcDzdxTiKv4g72G/QzytkzP/3csANiNniXJKyb\nyPEYM+lewTjlwyBrvA1Hseq0rwEyuZIohPauQrtMD/CqgPghUCPc1zEUWqtbD7Cs6Wa9Q6i9cZe6\noygam6u4DqOHve4zENyA4vn6BeFcxUULrbhaf00LyIK8JhVfO3PgfxROzcPGkUTDn9lNMcgSYFw1\nF5h0O+k4KTZAuh5WmzhA07pUadrHIEWS84zpb597LkMmlP/Ir2b5DSd3a9WrRzXtffoW6wj+dqC7\npakKeVaDaFLsKew4NQn/5Gv2SSsl4XFUnLgN38g3e2L47gMZVmWlB+Y2pxNwsAyXV5zrfZ66+6NO\n/atnQFy39BdJa/QlM1kXvILZzqUOXKGZVYZLaTWJEug9PUV3sxznlaY+cyInU/Zyp4GnlbQ0XVJM\njjTgTXNLU2xwchHYZ2fBegrJgvIFGdryBZ0iiPdHvP0oKTrobiiLLzbV6OGhFV17NAM1UtiiGvmX\nCecPeJZhMWSNd1sR0zXBMsmK0TzQz9wCoe+6xVsyVVjA7V2FOPwHS/UUbVQY48xEuz3BqvoRTDza\n/Upe/JHbXSk9IhwLJhuQT51Ra6cPMWmXfgxXBAUVwMzzMx5nf38uLxEbI8HuxHJNoAr5GGRdDbDM\nvIaZdGD58IBnjKY6oHp0HRYu4WKaLDRblLUdGdvRRYTa8gDWhSNjXPohCsckVTdJP+6e2e4QOj4j\nERJFaK63X5h0QsmZOgpBr0rJwPTHnVY6GB3YKBw354eubQ9K7LofK66j6q3zT4Guf8RJUbdEAwPX\nO76Nk2K/YZetp9kO7l+c5cAIr8TwXPfl9w6+CZ8CwysJcd4GCwCkfBAE6qXqEVKayXnkzL+/gi9q\nYhodZUcg9N6TE/MQblA4jb3J2ttB1IdT6RQqaipYfiglppdRbRW1Qij7hpryOT2LWAgda1QDnOCw\nN/aRmOHe3cYkOP7spl87Ts3hk7E2Ax/UCeVxagIHpfy+FrsHZ4qiX+k649T/cfEl5rBbvmxA/xiL\nCwG9iyKqxglcf46ESxutKiDbBbgTxm51oe53JUdUJ80WTQ9/VQIlCKHVZPeWam1by0CZhhQ+FHPz\niRM7iAkCLl0ad6jbmsTBDB4Yo3j9GzlRn4OwfvkX+1X6Br/jpb7Ods5R9sYdCU8iirwHrrDeyl4P\n5Oa3TjRfEeRc/j9P7DyMx3ksTLodItG9x/vZWgOy4iFOa215lI7+X25rZS1Ummp/5i+Xpg/2bqL1\nYc6h7fbQjdpHUXjn4QUz0LYvmc+BNdDxx7TgSkeXOeHhdOTNPZBaDLDk2cy+lw8H7HLME+RVBt1k\nsXgcUBHjvvnpcteXo3EY/4mNbR/ZqLeXimXlWhSbjhCGYDzmqa5rgtz3n/CYymQhxCskPAQGw+sz\nezc1Bd1Gs8eiRp5AYUfgRpr4jbtwjt6z++6Vu8p97biVpBs1ExN2/VFrFqgpOJw9uA6QDmVZnx8t\ntsVnG09ksxL5q7LXryPT74zfhepy7+7aTH5YUpDpb2waeTIFvBdg8gmxXZB2ZJNSvEFEPglZ4KhP\ns5Wo15NcuLVfQySWiiEeFOZVqadoOuNZDghUEifrUf+33tFg6SeVx+zBDJbH89YDSGPONwYA8KZ1\nllfpAVGLBseobFKvocGgdqQf5YsUQQL2aNanPQqWDHJHr30u4IJBVKuluk8tjx90eD5z0fjoCqq3\nJds3DQnYjrQ7BU2xCixiaN26VICrnw47sIinfFcVXPidugt7ZC/KdJ/aQIVQbkrgDLjDxprUS7W1\nFffseESv5PsMOXQPCsFvlKPUCAAM4JKznpl/d5fx73jhcyMXizSXCoL3+8p/2BFB2u1ZYbisTH6V\nHLzAnIYsfS7eDvpwedtN7UZnmo/srjqJdMDTnCXrvGjHEr7252l6Ipuygr6C+WLPMQU9rrfvIwyN\n7t6vCh04Uqaszzc5CY9Aglhmwt/2Y5fx9JkGZumJynrdGXP33p2621iPJ4AevXZ3fdpNsCsmXnzc\n03cELWhMybwOw1YYoFbfYaz0s7PGleQIeLnk/884jAZTBzjHWSoLCwehSZqGTEAap+F/qiwHr9if\nuKfdQfIf1sOFlHlFnmEytGa24c0rloKQYqZPkuEVY7dS+SDs3W/Bcfs8x0goY2jaXFj4ZMP5UuTc\nyYDHI66HFcvlFknDksj2QlDgRfqZvhK4nKn/ov1YLKpHRhjo71lyHjJm2VbSQ+0OKQv8nqczLIpC\n2mynrP+VJILPijymLq5vCPGo6QllgLdqvuNKBIsJJrlMhIMyMmnRNJvVS+sTiwwsxinybxQicOf4\n34R6e7oY72ItEWWzrwJMtmMMcQrNBoRVgZsDnDu3B/iLN9B445+Ia/2xI8tg4h4bWVtfUrPF/GHF\nCCMcBaai/7iqersKU25P9YqCrW5gzK4yd6hHRVmP/GReTSC8etOcS/dQ+iH7YAw6g+VqwGCE9NNq\nrDHzSFNHzcuTFPuPTnjdDyBuk8tgZ2P8L+upWmAB8WRT08N0FYWxRVHTgdWwIb++kpR4oah3SMVh\ncMdDNeDMRXWOPYx+eoBFG4TdDky/+Rpt3Y3t+kXs5rBtuM3mN6lO/N62N0YIWBy9PPROt6ABLhjn\nkTSPxHFYPlq+2tW7Yq6PpB3gOJgIpw6Jd2FVY/nnHFVGLeti1SuPxoqA/zB+RqAZ1ugF1/HuD/no\nlOzP6btVSLptufMfKGXQlqJurAbPNswzU1SgOzKKgJWsBc8A1dZhUmmODZr7QJWHHjXRe7yJioTB\nSe+1t1P79UExlkY2Av53wBpm/Qf4fP4wQc1SW3DW0IMbQtjt9uv9/X9fGV6/G4GCcNq3idyucymc\n5DsqZ30iU7nUPo5TDk2xTfYTo5J6KDFbWg68PBTUjc9YU+xUqFwxcpfCVXhHxosuzfUSnP6d8DrK\n3sQNP4khBnas9LtuKIEewVH1iv2IiKUdT79XbsL/vFcNBq0+Sqvvg8Mk/IozOebCZTqLA+pRh8j1\nPO0dg1EYBx38k9kKMWWaaucDeaXpyGKEurCt+rNNj6O3iZ4CRZX9o1/noytgel7upuLBzZqGwGps\n73AtMGLpnD77WEcHmk7vCb/9ZIQ/1JqILIS7tWQrpz13TnS0vYnHyN54RndRSVrH3tV5/OmRT8Vr\n86wb6pLSlRI3+LytODQtXr5Pjm9zRxy6ohZ3KULiJ++p02B77O1XtFtNs3jRNxHwmT1DpOf+e3YF\n7zwucJ1nuZyIc7dAzGodikj09oxWDfGZLpGvUv8slbHALDP09Q1sZYzbZb1WMxARlYmMMbOMv6bp\nqXEGb6OxN9Z+GzBYi3Txjse2FDv2HMAimBoCXDRXlk+yVpwUiCn5LTOOrLgekPXApsjOz7wN1iAF\nuPCOno030qg47WpIfuuAkwTBNanyjM9t9kGvHBUbYvNGJkbeRm8WiEhVGVnfSDbFg1e8sBlL0Lu3\naMpK5PBpegs+vk8K2IkOGYvR5Aow1ZeA5q1rcMpEdIMR3mvYVfmtKdsviHZ0E9byAXZKlxdLV500\nemm5GQ0btI6qUDeat0/afCtAal+KQNfrpHPt/BKEshvW65onuKtkGdVhgINJh2YjRt6jDRwNZQy0\nt2/zk33lRdcQQQ8LBhOyDN4ulcQycDTY8OirqCVBDoNZ+9yHallJ2KKSJ36/U8NF0hahr7y5qtSM\nA/CkX1Sq/WW9AUQghL6/flbo6xyPz6Bk2CrrAkVR1m8WMsMYMTJzDzfobDkq/uOLuUcYSHS8GNM6\nIdJqSHQHu56KgPK0O/DnWxNXJkyeBTmFrEEAeToW3FoLlXfLwtvWmC06ciSqRnbm4gQimtKLA186\n3MaT356eSiGNv5qN+OQ8jv9hOKg17JmP9W2QWQxotOSiN3CpHK96mnBgBkpBqeksHSwkZ0Ym0Qlr\nWv4lGLAVFUI/rN/rGeRGjup/z4iwy542LcR9kEYZOCDY7F+46FcaQVcgrEM3BbZM1pZ7vMLZbBAB\nNIp2+fxvCHdPb2MYCkQJEi/lNoxzKSXQtUF/XliVdGDd/gJwms8Xkb0HYbyyJaWmfe/7DA0SWmmI\n5fHk2ePB/BvngIkwjKN6KMMHlozyCxLMBeUviR479mhHY3qV5gjKRE18cK3t6WtqD1l/r8fKmf2w\nmzxkLYc44rJqGUZqz2o47L0QXKUl4KpIGJ/PgoMPvA1kf0RdRqeBduHyjVFsKxHnVpN5TcWOPpEw\nsnzFSf8uh2B3xmR8tN3FtBy76kvQdN+6jOgMRDMtqYF7sGVg9vWPkeNNYzWk3rNC82l1Zzzx1ztQ\nJPblX9T7Eopb8dQclIpQtlVlyIvKm//abXhCgGVhBiQO4HX0Mien3FDZ990Z+ACbN0ccUL4Q1a8i\nxBtv+PWgZCeEA7utiTzOAPee3+34gAm6naicmXjXFCr2YvuZ5nD8J4hTINSaASRF8YaSrvYywwTy\n0iiBeMiahZnjX6Ra2SrDx7v34srF6/hoMCA8DyH1mFmdEUrCRgE4t6Hi1YVAINEphDeCGVVAVZ2N\nPykajTZihGf35IIRqjlR4U376Y0tBRNDAGp0Q6kPtvejvKlrZKN4G7r1lJAyP09bE7KDPRmbs/fs\nNyVC8RFydYUivRE6veitQTKDOMDm6JNj7qAaWp77cujnVGbn64Bd4xm7WZeKIKIm4aYSnUwJl5hL\nD+LcQnpAu6AAfc5YHgN5y5HYw1yEUhRnMl/L5Bjz/LberH5kV5CAMGc35Dn5CCsgW62MH0Klur3t\nqvDQ3OvhGmDL4Y2xOoW4kBC/Rjs4GjGtRYrXT4e2tlpknnpaKlAKV1YKawJ0W5ajt598+Y5C55Xi\nFrK/U1x+yGGVlKNimaW2agOl9VuEcCh6glCflnLynYngd4XXKA2JKIVNlRW01Xgdtfi10B5ipXZS\nZVEoJ/hncNBjVQcHqAeGhnptqMCqfg7CcyShKr61kfcsAc5VLbEphtId0rpP5V0qOrtNJAKxoEaN\n0ppVGEAI9TOF73jTYNy5e79+kav+WYHx6AgbaL192QJxAqG6252UlyKD+TN3wBZoObX12Adr3vX0\nj8zGgO0he4Dx9Cc1zYRKQf+J+yMSyWdmVEp+MKCbgyK6LEYoIp17fcKhZNmAg+ZS36UfkshviFTK\n+POKT3AT1fvcHL8OYw/QdRPMaLWPsOWPzcq4yVgeUMUgiaSnDUCDUB2yCO1vrkhPMwKhlhn0LwuZ\nwfM3h+czZAHuZRighzjAJUXwkEsN1Pgt9F4Ga9v4FpSBRve37ucHHuEn5jrX7b93oBywaPyG4za/\nsKerqFfobeFqou+l5uZHAWu9PB7G/36xCuN+gmjhdwI/5TjKnJGVa/Y4mrJHsK6xloq5ez4C0iUi\nDmzKDqJoGdws5uiPusdI5CZWqgii+tJ8UWOIJHe9wGCyFsM8DcbrnffJ/viThaJpSCiPR0zFv6En\nui3LW356UdHeYjk/6ZLmILb75WrZlIL0kBuk74qo9+iFxkDdId6A9FExjyh5C0dP0BDu7B53lknF\nihlFcZBGxzYFi0FbzdfCEM2K3tcVp8899GthOJgGu1N/qgTjg7ZC/hyW+NBVWOcsA/YI7H3p0zgC\nXErEvovgf4PesV8V5YrcnbNOLDkF2F+Hf+2W32/JFOuPVvcNZ0gw633lx0jeGk6zfpU4S+UqC6Z5\nlv2D7EYFebe8OBLKCmRA2kE6MXcrMBmFn7B6+0q/HxIcCLbSLBhEYooIbwK4lBvBHwt3ZNID9S46\nrlt9jHIYAJJLaDmqvniX1DClRh9zTvsHpSGG3mOKpwD1pbAsE/8AMN715F7VM9sLDloqgirm14c6\n6KaiDL34h1u3UPQcAYa/iUBBFD/omsncOZqodQoWJn1t78iJvCBlDiE/KRD+shi7MBiWR2qJzUV6\nvszTfqHmcpXqEKqJvAXBiNAYngR+GmMYIbTgB1YEwXQCZD0LToUOiwp5anTrAhDmS/ZUfyPA3O6e\nTeDJzu+g6CkNKGT6qnI9zSYRkn59rzdWimTbmd31+E9sE3oldZ7yukJKGm9HcrjmEn5iIHN2ksfy\n/bkuKAzgYebyoHDYTZZ4VZqRJkKaocRo0fbIi3zd65Gp3s5K7YmVN1cvTb30eNMvckNTr5tRJMXB\nQ1bruBwB0ntnrr5x/IGxj/XRZ7/oSwIkJdyNApk2te/birUbUR6UnGc4y4ttNTCDEuqggW3Cbfx9\n9tQdOjLwh43tPYA8H/M++ZwOf3HhfJjQQKysv0lOWY4S7ARJ3OrEoqKqyXAWdXniajcpDVbynsa8\nNsjwPf5WL5HPa+3iczXjARgydFiLFoxXOvEHjL7tJu91ngVLoHuKCc1sVCOdlfYThGi23uWH7vJ0\nYOLKmVWobVhcf5VpB8+yu1Am0dOHkBdHCr3rrgZdInlMue8oop0PLaPmJVMowyGjsverdCv6z6UE\nOqIUWtaPVpiBpHHD9Yw6XYxDCAiGibe+Gl6m/28e8Ym+QSzsogPaSQBf0SelV7KrqzHbId7aPJEq\ngRCDJzmPbD1Avv3QgG3iKsbrPI2KxWvxVP0dALSOEGlaW1luiCFhyVQZMjhvB2qkJbqeiTDhS7h7\n3EUa4i+fV/sjeR56deRJoqqk3M2q5B2q8M8jiW3dXI4Bxnmf1g7J8vrQ+iXPrLgC2JkSbeRZ/eFF\nCnM7HWHG7fLPw+dEcoxCvhyjiLG4nrEVGBWGXhUmx7lCGjGBUwRSXgUKYTNM+tVB/GGQSLqO1BXa\nqonr6lyJ9aQG7gc66GT96wZBQGclYbR4btuwY1dBNSMp+euELOd1xEiLYTm8oFfu+4GyZNtxGaNH\nQPGRCGjL34JDEnum18YLX1sqaLAaI4Vd3oohNrCZpQUGEPboSGGh1OhTL0TcjUaI1kzx5pnFFlQW\num+7966tMQzGB0widT/dnC203OehdRUxF3mVKO3vyZQS/QQL0LhvmTW6F2yZftZZwGor4BAllquC\n557VhXbkeLpl/vbtt0chG5IT/u9C7bdHihJPK9UT4R88nM21DYUK11SdT+pomG5JH2mJc3Io3YzG\nZcfbv8KIZsybNllnnP/EBy1sp1maLL9qN6kF8hDFHfB/Jr2elZJJ01JYHPOQCHNy+UA2Gl5QwPr8\nc9SHuUtr8rz+WAOCvege7emLx4Jt5ytymFbSfrvoRM+ZUxFmqe62SfHTEzg7ml6FYKGwZFzHxAVP\nqClbYQVma1hfPRcOQ2EPNB+IDQvSMtnMgfNCRvCXzR+Q+46QsNEdqQLttQrMkLWYUWQ/PxH/abKm\naMyBEKhbB0uA37pA7d7nNWme6VWCZ7Phlw4sTGZ9usfSAF2iks+dhfHFUczhnkRr5kLs2nN//1Hm\nujL9S2Xh+YR8mZbK/X/DNNxk5vMeM2BEVm1PZoxk2SRTp2R/vYNolwEbwelAj06fIHNm5MpYsL1E\n7ncTpnND/46Rp+9dC46VWjFitJhw6xYQBnAnAUgK5XKJoMd1ULWbXo9Obn6RduRPzN0a789FLdcx\n4OyYK3f61tQF3inIYC1r1HHOGDrI2xRZVZNZNDzADjAcygRu1Sw4WL8VBi/vYsKqVoNERt38KOEl\n9NyG3q3+6TPPg72wauvsj9vXnxr/ERZ9FdkR/nhOatd9PJBBtPaEAMYvPNJ01ByAr1H9v7EusrNo\ndtHZtpRoWhrKsTvw8ChWSzj4E7jptyFhnLEslaw4KGbKc0rKYK/kNZB6DrrEl2aCV7QHsdkX9Bj1\nPKcOWqa37YQlp97WsyhXrowmbd3CistDmVeRnzDx4swr7Q6boEig1BCH+1d5aIEO9ffvu2QbMvti\nAbcrVFpP6sBalPmiLjS15uhWV8KEGw781zQ4mqnoVw3oCKOuwjvvK/9OhNoout6ggrrMMfHFLop/\n7TagcwxVB59eehfgXDHC5RxEwiKlLkX4TdQk3bJgWiNKjaUI0iF5sXdRTcu76owM9bPDeFQ0zvcK\ndUkPtD7AXtk/vFhKjwLRLeB3UTz+YhoVaUH1daPHUMlMEH+eJQESKAxgCeuJAj8GZnyT7+cw0TT7\ncjpaqS0H1C0WUL6EFh9/Re8yGO0a8+1Wp5GoD3ceJ9EingExgibnx1rZ3dLJ8Hmf4F6c97FHtUGj\nWWra/KN5WoCJrdl6TSdm2vPt/3JFImXL3VxVhD1lHg5jk87q0UvPEFJbe56oPyUDYIHorFMXCtkB\nSp0+FG2szkowh6Po7B7p6lTueX4hCfE63q/RjQu0vNkacOGXYHvO/nT/7D6KtFG9OpRZwtuB5emu\nCGXEsehh9FDIFrOpVZN7q6ME4mkpcEBoVM5qdWoVt/3gUeGi7NoO+67+Xub8tmwmHzbP8nOXg3X9\nfNoTD1RXYZyvLZE4fAJJsmUmaxheX5QZ7wY+viDhcuVgAlnxxX0LLauJsgSdLdbbADd1bV5VS5Lr\n7B78FfM0LvFrQA5ay6ZN+k3078VR8KQ77wOOtuiXuls/asxNNLGEZe3j1Oqa8f4PJaCMlo6GC4Fw\nG3ADbVBwDp6yZwFL+jqVJcecF0yGso2WSscQ2vtmwXqV/rt1ntgPMcrqJSBUCsg3n8UAqSqyrJMP\nFl3aW/zxO8e34gRl8Gb+Av7qEDyqQnJbSeqv+bQRtgG85qT9oO8xyqlwpsHqHY98338C2Doe0qWE\nihq/+PAb/4nr9c5kJKMC6aqGRJYAD0fox21bybPmT4ZB2ZffeOrw36ME+hNkiBhNVDEW0j4LFPfC\nYTBRPHdDBONBGboUy+sX0hhLEFqDxD/pZ5nuulAJ1Gnpq5tYOdAVxsaLS4xVsiN6zvxKorSgpp8N\n6MetCHR0J1sVQSDbgLtEnrJ7/7F0wLUSS9jjxyJk3JHSRXyJQkLPrGjNvsgaaZ2+lUq84JavE4TW\n9WVMjvOBSoHbjCPnbFZC8a49DiHvK1W7MjjzSoFWxEqbJf55ZKbmbZgJvRBEMomcR2nX6WZLbKWd\noRt3xjhQXyyiLw7QmCKsylEF4+dhqgHIebhz0y70vdoOeqc0rMJsm2eLHLngRgytaRry7GtPEs5k\nEPzKLb4IzUud4aHQuqMS48KrQWjqCoEMqJC+/cyg0GMCPX8DoZ9NTjThi3KQ0Zm7ccl0zBlw3HJO\n4qeihfn5PUbsuXiimxdpDSOITExdNX2hgIYo6AHvcXqMa/5Srf1HuJLKLN77iqK19L2yGGkfG4cT\nPp+WIn1zd33WLqzGEEGFwucN4QrfZT0Mk0WseahDZbW80vLs1NuEfK2AfMYWc+gVKQjjNjUOEeA9\nEL0nVCajyreQL1X77MQ/Z3f7MKXlMZIKZ9st9Pqja1Wqt63i3HjrSEDh1cr7EQru3+zBo7gAIJNr\n9GzPVfhPzNmlRJyLd29w63i3/hPgjFiRB2yI01ijIow79xNLQev0WpGBJKnLZIkIGQdHfPjySCPp\nLNOOluCTX9RiV7C2yt65IAYwEE3Rmu0QeEMTSJr8M6cwP8mkQHG7TC26sVsjzhaVJ31m5gOTplWS\neyBIdXbYZgIWt1obgM5qbXkjN05FCv5jjW3R13d0x6cAu0lu1EIU8Otrn3d7K7abyyOqc6fFOCWC\nFarr8sTVDJSYHojX+adnx0hjaUrcMBbGBTKORHKWrTFaDAPouT+Wyu7oCi+Hh5VqU+mZe/qB7Kxj\nlgqWgjbbdcxQ8ViVvicBe5q/Ovu9OX/S/BryWWNVpNVVPrNNP7Ud6AruH/fVFpmbyTL55m/dllDf\nEsoSG4IV4Iq8y+AEYbXrUUN6PUiM0B/GGx4FWgf8LDcPntO8P7KQcTV6F6MLG/Me/gsMqJg9cTka\nGebbtdVE3YGk4XTN1vGthwkfPh1Bj6hbaXmcvd1KVqWndHf7ySukioyKHVdLKfaleKZQjgYrFC3+\nk9M5UF8iyFNdxOHcn2vCBKWVc1I2pd6ZMR0eYCpW3Bl+UUc551rT4YjvRrmtgQDJa6pyO3YU8u8d\n4WmETh5BlAaqkEDHrICLy8G5Yep8lSuyYflQRyJlV2xhgVqOUJTgtQij9t35ogixJNN+XdeAvnZN\nYp/xoGGboGv2dQbh1AB6/hISTyoeoxiUiY8Nc+wJ43jxi7Zof2SnRGiGZO+DEU5xvGRXl2Ws30bG\nF6+Am3Fvx6BC8+k+3uh9EM9dWQfSBMnHdb3idchTHaECxrWgQ6YbLbIwFuEO5ZH79Vq0tBc5et4I\nGX9TavQlby9lMDPpsiWQoFMzvCBc3iZ+lZJau9LWocl+f/9BM5rtOdI0HmACQiXtU54IhGtfHCn8\navgoEX6YeYOtrL13mkeqZNMTwp9lDG2/ChB8jfBoeD2759DTTH3o0cL9Sf5OTcuPA3V6/lQNTJTO\nF17UEFBwpnizy/n8XdzKpjU+gDcJsRcp/WGYombRXjSxfOEcYeRGaNBkgmqcV6xbHB9voCeSyNZQ\n3NYbjLsDuHnQ5i0saD+Yo1ryDiGFJoetyr6nXA1l8onA/40QGdAL14rfQV6HmaKHRVYCsF5tQoxH\nG29OdGuI0EVOUfIt+T29zFbaLde+rv8aqiogYctNjvILupJVMCrUy3eB1cYL1r4cE8vDpaIrVw3S\nlXsgoXh2LK7PC3REaCHJDLS9oq0Nxu43MiAuaSZ6DZp0U5rHH4DcUGKGK4LxiKC1fKZB2YXk8CXg\n4JmMulWsBZyVc1Hs2STEooc5NEZRynFPyNx6sPwUKpBlwvxgPIz8ashYeArr7pgtazIlQCV8RsbB\no3WNCfSTrHDscYbNhNGSN15ujTXyZIxf0xmw1NxhW4VE0LbVbU4Q9muynFksh/f+O3sz79eTs2Wk\ncj94qweFDzzDSKfo+fYFxr35zCg/FefHqD9FPNrkArUiafPmFRWLGkm6SWycHTHW2dmOUxqBLDnS\nKOU4i53LrnwJtNlnnNbR9vCnTV3HZkrvTaGD1GJiRzC/es+XDUFHEb7YDM8JUKlRbU33uV+CnXcq\nE5Afnqcfch6xTfp4W24eBeAxeKZEXYdjLxisOYvQ03BbLnt/ao+HyqjiaVos86B9Z8guiTv7Y7vm\nU0QBEPyFWR0ehm2yrjUy2ZOjpN+dN8ptlOpi+8jkgisg6gYT2U8e1S2pPCrAtZwj51rEayRg6gp+\nfZ1+HBHDLTW++YMQshPGSEXZMzn40VO97CNjgrh8ovSvROZzPoujNet0XF4Xl+0pRfUzN08GGTzc\nCDNZWKvs7QQNI0+Jzy3TOqD5OoFWQbRf3ETptGJEjsxTG4xPlNBT393qN4TMLuz9Lu1DCUKN/auR\nkZ2FO6X5bGfE7IJXmo05JK9M+NQ17wS6A/rJrHFTFQG3i3U1xyCqWFjTpJJamaXa8Ap24WYvz6dc\n098Zr90dPEFqCDwe6hxyVvY5RfffPzDqQb5DMiiFBA0+l1lXQ6msvQO0/PjN67FDr+p4RuZxhV6p\nTCZm4lrQ47Q5/Asnv2QX7XT23yACOPXvT5VII5iJx66cZDW8PqcokaLa+pAtVqbgZDPxZD1C4NXw\nAoObbkqulKoJobs7EjZSIpKQqr5GCZ3QjgDDwPruhevdnzONX5uBvI19+JYqusyuR333F376uyvK\nn6F+d/zNdvSAV3gIz9JaPPEhjbKgsUOFhdyDoaXdydwVHrAB1SkIhNzpfNl62QU0h9m1rX0tPNdt\nUnlnjJPMTjVt7hS8vJhfgtk+39dFB37FS3rVDWUD/97MlcR8z6MEGzbLsGSRtQgzQXSzXL4ruX2E\n7F8oaVsrywznJGiEc+2zzA1QekJQuy5dxS2hvHftZoajaCqWhhrACvQAE5HTIr8etonzlt70MhBX\nR4L2Kdszs+cuKe7YCn41vp6yn+jkXCpOzLOekgT30vVB2cScqwhXUnoA4eD5oeMK/VvSG8OomIto\nmaCJiv0wLgJ7kJsprJEeL16mqTkMwmvay2FtiWlIWbKIs9hgg5RqP5ftklAYWiA/4wg9CMMoH2hp\nuZ1nni2cWWGynf2ne0XC1qDqennT2JyNAQtk9Jw0eXHvjVLarN4YgyFvFTr0C5rV9472azo3UE8A\ndbhgNUf94/74joOWhz9K0BX6hu6u9am3nZfHjzT8iT3pq3MtSlLDx/+vqR09j1sBXhBoyiyASoio\nhAQyBIlf137OHYUONIvyzXe1M6PgVDfdvFr6g7VVEpVZDeSgkN1SXdnbZwYBVLOYe3JTzPfiCNmw\nPL+c0DJ8OwN91pieUcftyhX8/4nraUP0jfbmoqYneAn2aizdgj+uYZDayM1DDIqG7HkWgfoTyOux\nFto6L/LvFuzFDe+ipcLHg/txvv/oK16fIF31ETqIDIKRU1LBbQAbPUwEZxC+TEnpkcr6oVT0hwHN\nJuTLW8ZHgsVNC5YQaLbTIU0uVZ2AYfXpD5jXx2DHxpFmqpwAA10PEvjjBwEXurS92XYW6Vlh3vag\nh8071PI4Y8h0dlx5dPI/VyJA5MsaecCPh9Wc3Mu9ju7CmJzmdnouyGW49lVc7T+BFgn8vY84W4Jy\n0EOJqxtbldn/b0RL9qNfkmndlxOOYUGpkoTDXOeKNtd7HyleHoQUnqsrJltt7n1TUWyBkUSvmr2e\nhIco9V0pfGLnQmBrcS8ESf7JoDfid3dd9xhfTYd7x95o4BpLRW9VbAnUv/qzO2Ql4PsXD4elhlqQ\nIX/zvEAslyulqRlaIojF5lfyR5gs5T3XDgy9J3wvtzGMB2e/OdhArVKDlyiGKVBCwObJBltJLdrm\nqQtoqvfdCn+V9EPh8P1tILiKhp/pxpNcMLi4F54Ss1mMT6eOjdsUUk2NgxCMXJ9DCe3Vzm8uyZL7\ngcN4jfAg3E1rqk3m/i6KHng7yyFwHWIWhDG1pdVdgHnmaVWwnYivlzpB/S7eNw4unSB3dd2BlnzG\nRb5PE2fCqQmV6WZPnzyEbQbON8IXydg2GwqhVl7d+KhVvB9u2DtRSUwccaSTmzQitYkii0ktito/\nOZn5ZAWREOagH6xk2jSJtB+raBOlZD/StDmobLXWmpcaSlaEkDEyTAMr+crVbeg3vAGSoSOK9IbG\nhEMMVUnbYc1PtZV+vY21I6ppYt5T/zHwORuaK4UahSEs+tc11E84gYKfibx4zaxbrR6PIWoRhFpx\nfygJGI82fQqpK8rIAfb84Z6eXjnfx8vNe3ePHTI9pkZghZ1vx44M7VPJerWd7U5zd1C45avIo7bJ\n7u6tesU5+cplrvIG+231DuhICa8DH9UF72c/JWk3FiHDqhpde5ScS3IcWx1hhrKBvi5FXoH10veQ\nlHicTS5ZPF03XuljrC096UTByid0LNhm3MEYNMhJHDAg//PphATDzK9kPRVEqWJNnUXtQxCtfaGv\nDDm9ZwguZj9gqtu4FYLLYUIYBSERRP0P3uA20WOHJw+chMy+nL/5NJ5IbO3bDpRrULtw20tfYeXd\nMEZRrVydMWKNjYU3WDHTREgJjguTG/o0uckR8jUjDqND8/aBClo3a38CpFmPcWL6ws4xn7mPX0eQ\ndm04/XpCC8K8rCxBby0gOx53dNfuWePoTZANSnjGGiUI5BxmFdAWSo6va4tcRBNNZMPM97o0kVhv\nEPnfc3/sGE1x3k8/zSHbDc8HaQOXTo9W3rmPsM1cLrN9t27Iox3uo8H8MKqn1YcA0ilt5LAjrSV+\ntUKxL0hO5/r4sVSAigD8X48thLABHsoJPxsvEF8LqbeF6ar28+m3HKCwEkXmuDsb2D9EH9UPETzk\noU7Zlu+cBilAsNow3MhIVGRoQMJ90wjs5tMHHN0coijGoZTA0lcU/s6NGNC2TOBj1w5bSDX8FKiM\nS07TxyW3rw6YTaoFIbD66Rq/NSP/31Z3DELdKtPR9xDQKSDKf8jWDeUMJczhi6nWPBQbN7UQtmrO\nLkeWuAHdvStParHRMDHlyl76hJKPEZy48fg9N9UdnO+Pd1Ald+lem+PCsHHf+OqbXStJyJ7sNQPS\njKJNQgifRKxMJxi0ijJ0y77hsBxInqwKBywtcfVKlXs5gwB5+HzKqctr1bzPf+oUVROtD4s7C8n8\nPRAVBiiazwsrGoCKpXRTQdmcPIWk5o/ljibexkeIJdZGOflQLAG79TkQP4VR589A9TEHqrbDA8Ow\niEvue5OjEfXk8v35rM5k036b2nWDRQjwgH6Ww3B4Lm4ynLAYQGTB96U9XWkAnWLiLp5m8zvFZdDi\nE+meA0JkE6eMo9xpSCwtthR9qC/ZN+oxyhOIxOtsuOB79uBllrVRyxq5F8q9Jv+a7IKcvLMc3+Sk\nZmbgOAgVLYMQnsj7C+GgRoA181qNGBLLADnDESGgJ/3VlMRVMiOvVQ+AWmMuns4aRjO7TJj0T4gj\nOtQxN5mRSOWygf4wDNFbjjzdk9Wrb+YtBxxP67a1DBY73E4f8rq4GAGOc+uA+vYPxN2cpzQMxn67\ntST3yTFSN0HU+TLzADeDsR9fli+VCAO40pjEmfvnmz8uX4ieAh1/bmsrpCB4hddDi4K7Pm6hCPVZ\nlNMu2yUJ2Gv7pSfim/c6uDmTOvuyKRHsEtHBss9V0SHiF7zsCw9jC1Gw1Z3hAWIEE9MWxlQFYCc/\nOJl2e+2sT7p7D6B+NL5udUm7nX8gB74q1PUFWPsGYpD2pu3lCBVsQcSipoVTozPzXTMu9GhiBbtD\nKMVzVgZKLQb85zYLEfk9esGkaaAa/IMlXBYyZ3KgxHNEQVVYLd/28z6Bgq4z92uZ+nUjAQQNhNbd\nihUSeLisI8jS+p0o5SqzysX2BhJTA73Dl1qC80tYYxi+Dgt6Ix5T5JgkBeZt5XKSBj+tWhDWKCDx\n6uUFw/ci6OktwfqL5KZVOMkEwPLWW0W3S4EwFRv/nqulclXjxaiEmI1qy2g3i4xu4ozAzfvuY4PX\n4TNsbHRGXKHnbUq3OX7WWl0FoO0CnTw7uzXYj3goIj+2ppauZVSQt3oGFMco07p5c7AG791rM2wx\n+pZL5s5qBaL9pScdRgmtmuslKlqootc7gQJ5OxR6mvoMhOnphhgyojQnOr+SJEtDMMD5rHlXoSgW\nUJGwt8q/XT7s+tAVwEfFZwcio0IPbQNDOOsdHChnWoWh82tTu2wWSgR7Kg3fahsm6lpYDnkid7j5\nkTGihYKRKRkvpg2Ws63TmPYjpdul3WC+b4ZOhk6v3C1IdjpjOJ5UG4l9tMkYVfoW7y024BquSO5/\nMPPdTM2nWYdjbgO42K4Zxv4zLj2NSkWZm3pkgJP8LOnt+bV9C5AceuFe2YEcYfHP2NnzCbPkW3DX\n7OB2UfViC3Mm7S4KKuGfnRC4dEAlRwcrCwYneuiP6uS0A1MNUvCnPn8WEs3qpVOweX2aJkYS5ur/\nR1bloUhVQUshGkVfjwbVCpNKA1Z9uzEmBMAoQ7XvphL37Gw4A6IF6IP0hE2sLueqpM8yW6YP/n2m\nThOWH112SQ7B6Cl1xkrSYRy2fRhCPLiOb/AIOrOXBfO7Htq4hRh8mLjn9tsBdxQiCauhjPtftHqA\nbnkLa4np5WOkVect6L/DVTK0V5YtCK3SVmMRX5+n/iH5KjTBdbJDG5zE1+cZIZUf1jHOQT1zGeYb\nPcdKviHtuX/dxA/zR96YYgE+6kvpWexwOMkvDnMeZrFWV3YA2Q4yzl1IMz7mxXAYg+xr1XhyQAHh\nbvAoPX1ZX/f/hT0d5tm7H0+hzJGpOMNmOb9uWoxbURr1oTe7Aub9LGHM7MeHGjRy0eeNA4l9a3ZY\nWaNVI8NHq1/gTMRD2P454oSx+FPyBOny6Sx3+WAXKWV4raTpFUBs/OkARVapcvZtqOP0JQyWm7PT\nCLXQurpYYnK+M5sJwh9q8N5Ymi5B7RVWKXSw3bTt5UpCMFF8w3wqLBnB20ai9FBNCmCWLZmqK1BW\nOT5Z9SWGsFad4wD/ykn7EphW/XOoLWY4gWTRReb8kUiyK4uYq3GdyedGWQMQubbwsw4Yf9XLQOCA\nveyvPmR0nXWIDyie/P517DyAPPR3QSsQaXWL6OwedlZe9/pJZvpyVuCkMvohDO0OiZBnKhw8c6g7\nQDxVJpr+PzuscPWWNvWsRleF9CtP6o3lVCPYofb5eni3/gew6UuMOOPdq96vjfol+ipMOitig/EK\n5KSSJc4ignVV1rpPdS8jKt1uRzdiIG04lIgKV/iTrGxulwFTYWn0YXZ70j00M7akJBpgtHYtEwg7\ntuFwF87SDt98jOPD/WHKwoeleWTKwDzN8dUG6rIIjciM7ttKAupuKB8zcngy2+VEd8SJsoOuiVXv\nI1jEkJzWfyF9h+BgpXXoFGfSUjm4PqBwqBTsya3TbfnxMusFwVAmhcgkODyoaBE2aPevUBLTPEyg\noXiZdFn96TTFBTSKxfbvfoWmBfJLQG+IUMH6XUArLaDvPsOewnpCrh+xOPs2VUJvRJlbOoQA8hhc\nBYFw9C/vaE8JPImPCF8Mcml3atuzrH8J+M55leKZ+Ahyde17lDJYmLaTtLVQgqkyaZyHgYJabqrL\nfvxMvqW5F5ysEsk4uLDBFDd26mKkWfaYPU1SQDCVe5TX6ZCrMoOF7QT3xo/dGRKOrgxhF80rEBSA\npbHEX09kRVpK/s7dJePfIDBOH4wslJSyr+cpQWARs1LDsRdJqfBnbx5MEQ4E2qk0F1V6P0Uu3APK\nPs8KsBhcdUXgUqbGbsEQmLHNmMsW9PItMgYMqBKVjCWjmnu7XFM+2WPGuA22GFgbq/HHjTvb4+a/\nhNHFvP4EGDou4Pq063a7EtIFFh0VzxeE8It65f8GizD4Z/YaE5NBdVql7NOdDECr3l5vqCI3HnNC\nrd00HANISl5oyA2MuYTQR+GQaXrKUzZ0cDbvQZ7P2epot1a+MCmRzUKtgRQlP3GEAOvl/z6jyNGl\n0i9gClFCTubmketbUNA8oLzc5tOCpMdeyfZX7wq1Mj84m63g4WECc1S400lGBZhiUvaRIgsEnvQo\n0/oWeneHemIMitJgnp4Mf5PvMfKmyud8ED+o05VrGt2n1P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protect end_protected\n", "num_lines": 1219}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\ngazeSTBrENHvbt5mZLx18dRtoyW+Km4t51uVxxH7ZGNnmTTcoKqZyFpOrZ3w8kS9aFoiQlh5unYf\nVMD36zgB+w==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nJaIcYFxN5pqUbzepnqrpmFHdFIYWDYoimv/QCWvvIMmet78lyyCu7OmAbUWaZA7w0zL3MGnfxCUN\nn3vQGmg/2D1qvx/q2zy23sfhZfE87aSbXcNL67XF+GYu6OLKGGPH8rnW6exQAoemSF54SZgfsVR+\nZQSjSgAEtaKfNJS48WA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfa+581mCG4lxTJxvsYAMI+Y0/3DEJVi5IASCLU/HkCRmXkai01uuifj6HPVqiueReLeiWI0bzNp5\nJVlbpO/kKqg9MkQMgg1uBw2FFsg7gfVjpDJV9TVBp9Tm4YsSrWm6yWxzb6uMaHsxRa5Y+E4WUKp7\nkFXmUM1qfaMPGyGNdQg20KAvKFwwN0302/mi6GDcLvLNvvne93tcew0yQIxg/gqJlcURIlak/g5o\ntVj030iWkuj/kKp5guYfq3gEFKVEr4SV1BC/f5KX961SkhTxXGKLNLPd//Gm7akdx9a4SnpGY1Jj\ndKETnZJbnXtrvqcZUh2N1o7nl+YTs0mjObgM4A==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nQPlIuDrSSApp/O5dvtKOql3r2+lVEipJtAA3M9T5a18Cd2E2LeOe6u54LQRqvqSgFUElg4Mk3hH/\nGPHlO6wLGkc68a2QHrQWBA8YylrYUj+OZbum9kUQm5R3TPU5Wchw/mhpqWpgPlWvyK/cO9FxrB5n\nHD5ZuDk7iJeShjEmKewIRdMZqkkvQahMZk1eJ8aT2jahULqIomSMODM8v16Cxv6S3q0ohUtT2DVH\nwOkY6nsqo58T1MDDOffgorFUWVqkQwGQ/maDu/KENCo/JCJZOAmODbmBfBAsXvg7bqGZKB9VPp6h\nTMfEboGK0PjL8yhECxqeqwtqHk+eixHOqSANVQ==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nb4dHNcYwRRv3ODYilIe7aZan8VP5sGFpEcM4Sk9B84EsHlTRadyHodV0BfhfsPQB7kezG88HW5h6\nWNkuMny+KpZj54uRmnCQmrVIyZTZC+1+fpR1i46q7pc1ZFH0ByfdNqY/66Ew72bJ3bqt98VUJ+b1\nKDNSnYmqrLKj6TtcYAc=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUFVtDvwzUgfeTJK5RQPCu5bEQXOVNdg/Ctt3LMq1WwNKEczcihJ2sl86P3NdRo0ERI8ueQtux6aa\neHgbxrha+qncx9ha9CjfRUqPzzsOn3Y7i1ixq84ynt9jVyhbj9UUv8UyPbi4K5iayWqESAXrtTyL\n4izB0qPIWl4//8zsVriy5QoAxHYuCOVTFT74KhP0GfBhGq8gl2pE4gyETTs/8CEabnJ3ERkaoy22\nqOEPUjVTsxS8vgRq8tS716SKeECQKpsy4XCSTfx1d1knluz73QztnOOUXoIisTy9nHoSAbC1cRDx\n3ja7kCl2MkDQsfmBWkq0ozzVuY4qo/oIb33DVw==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nYC06/kx9685ntAX7i3acgvLk/EwgC2VW4WVhE+P9S0QST/y6VSJ0oBWMmzsdOs5O1+nblcA3DkpX\niLfXgmvlzh61Du6yn0zIyDDTLrMYWINvRbXV5FG9pLM3G/U+6fTbBV97iUYMHPWk0A2DdkXIWMP3\nmcLuMBQc2y0dm038tnqa7fuMeTcvxPhQ4wTWwHXvp54ejwq4bTAhNgyJeExmEzOvR+zWXm2VgpLp\nqcMFWAA6nlUIG5ZF4M15/u9UyutQPOLlX5+QPwfoMVi/kyC+JK5AUrviJ1QU+rzwvU3tw3rXqAgE\nsMTi8fHZ/Nt42HIXty0cXb5zEQDuP6pPBNW6XA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nHg7KeQWoQfRjpmFIAWAFbtestpXMcHBDYTZuLUSbL+kKuRGBZWT+FXknqinVcx0pJ+q5acUTBtyX\n7dcJkS4qdpYpoaBETZeL/wcOfYFz/CcO2z0+LWoGRDW3DzXn1oRWWZyJwgJkigyMIHPH5qxsjDO6\nJPKj81fkKJMHi/vC0LbmZMiKSmWL7sQNeQyH9Dn6VLxtXovGL9yVh0SoMlG0/v81wA1TX/bXmqKJ\neUvzBU070O5AHkn3Z9WRSK5S2L7x/k+ltWDFho5jtXYcevcbA/14blQqT6/9PetAyFmzvbIS+6Sy\ncJ54zu+VswtKtSOWyzlOnfx1Jgt9q/yLpCG10A==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nn/U5obQaKe7e57D8Mwxo0WeDlQ4fxz4sWCrMViskbh2tk4bDpeUf1ENBUputMkID5xX5gqlPeFYH\n/lod/5hBiFEecXymoK17ADl/jmNo1MjfVQ/nqN6xaJWL8VqmPoJ2XUvVt/nh5gTeI6QOH0BkigMy\npLFieK53VJ/5XRJXmLUeyAKMuQYF3FZPQdvCn1NDG/xTrxv61UqQKbL35Q6DuG8ZqHIJKSJFVln1\nchCHgEOHDKo7nJ9MCjYRgwBWPGvr+w4IgHNPDhatfWTGz3wjSXmjYynT7/3ZWqR/d7FCLN+lZ/ht\nr87GH/juUmy47PmZd6QhKuuc19/j3eDrwcHg8g==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25472)\n`pragma protect data_block\nrVD/wL4DHCsEfzFEf1VoQTKecFocJw604Tk0NgO7M3ODm6t/6/biD0QPzz/Fzy1UxKBEqQ8Nxpt0\nkd5dp5nyCwOVRYlAXNcBHWyWuF3ImZ0fp1y2c4napTVULuw+XU5nSbEmfo3EFsLjHWHYarc33XNE\neccwGpgfFccdUa90fp+q6imfJMIuCWHWowLNMDGdb8ZqNKZUIE8ob6W2adzfUxW6BcwKDMhYtONy\nphGaaPcir/7ub5AXgPuxZ+H/dTq9wgn1aTqOJAp1ucnPzVq3IUtg1OC2yU2vi0qMrGvEVqZa5al3\nShGeBdw/lrrv+XpB0FfkT2KARuuSvzee9a4oDMMvB9rD6SluK40ECZ1+yy9NV8VPy1Z2E7wjjpHJ\nomuIJmTDG6P4NMgl9qjKSn4GSHvEJtg8Hs/pMVAdAds6SMK+O9p7rBsB9TJ+Jfe+EKBicHLzhqUf\nYcNZCfyCtkGAWU7HcdbTu9BHbBM7GuhixBjPG1gZBzSE0WtB6MGt0YXj5LC9B2B4gUc+LuNxNcc9\nUKE7AQ6OnNorwxgTIT1j4f2lTdDpN7naMjcc0dFrzhwLEt7EYhpH25Cb1lTtbt3ny3KVcWNrvcLk\nv09yJ3wThnjJnQl+GUiERUgWu8ROGl8TiZbUBs5yecOS/BsLolr6ykQh3uUot6ZrpLggo7e2zZy4\n3svfbA7sVv+IfBOnba21zodL6jR5Io/8RZ9dAtTSxEkwNKn6woPbXr0vzkNOcXmNshPgXMNfn7kP\nhh71P3gVjrM1Z4XR2k5FHBKIFP7xvG46B9zLPPSpe9cKzJ4DSqgt0aNr031h/E4RKIrUZmmfW0JP\nOP5eFKLhkwM5x+n5EaEHSfUgoGX++y4UkfnBJWjFbVIWdkTMzBCFia7/hFiP4k87QX08uk84BfEf\nsgKGgULddxVYXIDV7mrWaO9Cy6yLEYGh6+7ZOBVM7Zy6cqp9LP7Kc0FPdoy8x9BVG6p/reTiiw1v\nNn3v32uEnt3XP6T+LoaKu/6mrF1npJimdRr7SstYkFy0LoyzKWhUHUz/VQ3iwILTJ0JnGP770FqV\nmvyHmvHBk6MZTTlNhtcVSTTwbM0lw0LvHbExAUCD9Laa09kQXtQstGMFqjckEvN2jqCALunjsEkp\nBQy8rtux02oSB0O2baktMwI571Rh+4HmnparL2+x49hG7tthybchylTgZbFDHKBCvdQBZkzVuo3Q\nj7Y3oKUrm2bmuJSbom1St7TbGFQq8d0b0kTXHL3I2ohjaio0dcvYDfVg+yWz93shEUO3Jy4PUuCC\nxhV2WTmsBi64HHIJgemiKEoZqO3e18N4F8cdUteag8hQdvF+6ZlNnZ/ms6TH575Di4UiksGkL0FR\n3sJm4AQ9V6tp6J/S+c+1flwE89qo+Xsg1/cG+L8vSsQxqyAk/ovRsYwYHiS7Yy4/606czKjJjQLN\n/Od4Z/RzSCDTe9OkRgKnHt5zK3yQjI9keM6uYHLPJND8bpBNdWrqOdAkXjDHjM3I9U6L2JJqeXVK\njIP4ArCrIq1ZHjpvCnFaxB+/+BBdYcUPUm1A5us5vUT7+x9nSm5EoMOVcMVFqrdJ27v3WAGi6+E4\nKO2C+XigT9fiGzmzXlKKtsTeS9pPq+XJ+3ohj5rZIoPhbrKxWjCzmpLqwAJ0gNd1WFfrHgE2LOe/\nH0ryLItmrp8oOSGEdzqkIi3IjIWzEJsFuNK57sg85CLkLBrD/2GAE829x/TXqmIJN9TXeNtV2gKP\nzoR4NFQendQZY0s22N8NsE4Y00GMNZhaQdHbxhimdXjmLk0d7qaq06rLRbHcsoP5Sq1QJlF2K1qR\nCGKoiuDSQoQ4Ys7EOeerLV2n/FRB2yqoN8xeHjway1HTDoAPAet9wYutlxLTBUccGt+zU65u6OaV\ns1H2YlNFqtwE716Dp39IzGvOD4w6IjA/vBYiXj/dOVHbBBfQr0u5i5m07Mu8+ql9fOGoJP2wqBln\neGByChXLhb4uLoe6Bht9vwf98nzSbRmiaYLyALBXHgZKs5L5Udkanozr2NM301M2pzP8QIPa2aQb\n64OnBA4icxCxWwz320VkF/K5BM1ObCLOipn/07v1naPYJx/9aT/ZVupp+QL9cBnPp8LZtldMFsxi\nZojdTH/u0pOw8jx+SH84VqjOEloFoTxTXkAMHKRulU7yj7ZmWlEviMhxT+f63SOqtMW6bd8ndq86\nbFiDcjGNkZC4YUerGzbOM6M+me6Qe5RcwL5VJARilQoyPMlPtvzSwMzUJQyUmabaCEispxMMZ3QX\ndNb4c+W7FDY4fxsytOmuPwhCZS3ytA1vCB92ukP2KVeOien0DKc4mIwjdBllzW9+QN+GNSzRe5LN\n/YyvlmAWUmlNSB8smtrpmB84JVKlWaXOOrpOLxRHtFaYpnmpmXJcNveKAB4LMvGTHJdEDlR6LZ5n\nCgWcU34eHvwxJ0N7D9kxlxL15EDsPFjxeT/vykJmOvcwVPmia0M2nwFaolKZW5cm0pZvf3bzkkBt\nkxFF4vDu3VKJBPN1qqR6ngJ8w5cII2VcSG+TZBxeAg/XH5mW1JuetQkNdLK940Rk85qvx9Z5tYFu\nFKrDM/P9zlRri+ggEpi73JzEUnuwXVzjIe4bn+BCJz+SYBKbr3OlasPo2GXinaCm5ZjGwKSqBbnw\nJNQvpJstSIPLThwNEK3IT7qyWtVrGoCDNiYO4H+x3es6P4VqLqh4r/0++vkRSTM4Ov8V4lO1aK+/\na/Wba1G4sbX+xCKKd66y0Rr3rr77pOo7IC0W9booS++rNRLvt64SbPyun/PqLmZi9rwotRAJRA4k\n7TXOcgtq4Ki6pKRKU7oKP5pQXRmGEVr/qGRqcX/IFcGkvR76WQxcFoASm0Yj/3Xu7bvEHJDX02tK\n4cAJxbC+4JkeI2Yc4e6V27wCtFNv8VAnJEAIJxM8w8Y+uK3Wdth00+HnMr/teyh9PAFI23BCDQ8k\nP3/TGEk+2X9AelM3jnJ1cx55xK7Y/PsWkiPKyUozhHYOyR4SaETBIxAtZ3ttpyHm7JPgipayDsI8\n7gYw9SePFZFjYEZhCtfrBAzTmKhxEJ4BYA2Yq5/1Djk3dqr1Y7XDyyIaLjVim9C05XBvKk/3JjmK\no/4wBHIRPWEui8ORGTOUvziQUj+FDTHjthpKosRq4PYd0gugZGbbhdlEj9IDDCDNxkVM9Xyk3ytf\nEqvvgLtYOih3D2Pq4LqFEqHahfAKS8ugstEsKmEWOeBnP50FSppoksT7QdPuZ9PWlAatvnkJv763\n5BXALS8jMNlPIJvelWHd2qCx6OhCgLmUmRPNd7LCMMydqv2c9uA7voFh6jp9JGAvPu53dzjWz83r\ncFeBSw11OeeiKRsJaiHddsq8L7nMEeMcZshhvcS5y26j+2tp1zr6sVBFicGgokYH1CKTQFIpiTib\nXPL5vAVDlvFDdaC5VNkFNCs76Bou5yWCTAwG2DcN88BLMV7QS7M/iGZSbCw8JV01LKDRqeheVsxP\njaLYS5XkKHDpYtsCzcVvCn6u+nDFLOLhz20cYL4vxwmt1pMKikYG15ONmScVDm5/xQBKe7nWsOKz\nSN1w6zj36KQ/C80gFY0GXtFZkG2CqAMt0M3uDfWx3VKuW6ObJNUb3R0TpZri4OwLbrrUpL5UT8yt\nITdov+Beft7qZpxoMu9KLHhncLx4TJH0gBzyTVfAPg4ljeaBsL7cmVfDmZ1PxNBQWN2/Ms5XhA42\nF3BDbS8YdOU8JUxHPgD9tCaXHqmt/co4uhm7Qtmm+DeDE3O6ljX5zbblXhS0345LHi4MFfhCkb81\nJ5XdY0hze86Ye/grd4KM1+hLV49/08mXyM5oQSWFRPGDY5ivO4n9anEwslLWZ2OKFvXtW0ZjW0tT\nRXEjOIOyE8jyr36AQDMI1LnOl15xPMnKxb/u3VpCatxnNlgTk/jzmFAD36PDOdzIPJr58KDGvKFS\nG18BSpcfrx+8cPWzVMM9M9Xk88D3Mxb+hWAv6UC/efp1x3+Hvihd9zDuubo8/FLjegZC0fa3een9\ndOTgEIsRfcfWWWdtQEDcPKuUn7WhoHt0SvpvO5dTcLaAmCPwcROmaH0teqy1XjMnZYp+sKIWZe7h\naa/hTWP68T4UHeFB8IDD9md4MZDlB/L2ac5XlcVY7UmN/GXG3pc7Gbc6uN0CzGUQcYa/v04G+11h\nT8nRzZQJdZlq0lH1U8k7gR7YudvLKtUfLHu1xmyJshSEKbRWUUdGRnwfJUm+3jGXNSoyoDu4eVa0\nmvh2E9+h8tpc6Hdxbe0/dRAb6sSYseeMuPA07z/+SsPa5oJMBS4zBtxgDX7xBkPmnOmMnJAKzWdI\n2/zXRzhP8OaEODsQLJm6++pIgkkHCqOGr6GeXrHTdMP3idL7UslwV4Lad1r2Y9+61kW7fcGSJ1KP\nG39vh0sAfFWWeb9d5TVQgwz+KIoe74xDJPYPPSkVl5kx3YFKk6vty4CYAB+5DVSd9bLaBnJ4/6l1\nJ76KqFbRsqIPDPWm7OcGTLW7JIMmU/Ofpv4nidkb4LPNVbPMfVS+Z32QG6FXVhOpIqgiKe8BfVka\nxk1jg5/fA0RQ/P5VlZhWUzEHywD2+khTh9xwSLldzJ30El7YZ++yRrsgkGW93hRzZdx/r1YMGGS/\nQBmRuRM3FKMkS0svshNKaNg8DySBg+q2X6Ky9IjA3dznU49GnthwMKhx58ThDxQ+szVA0MrLc0o9\n+rEmk+wXvMx1gpwkFLsJocOcBtoyq3atxI33E/X4g0N1mdf0f7XCxqKCPRyQfjfDQQv222kEzPfK\no/j6pJzL/bq2QCtQD62ViO655dAFs1zzuPSuwrN0eWO5sKLw4bi9ekjxE61AGmPACWDjdfaFWJ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dNrJi4eDjTX7egADR1lPi7IHJnaNzULLyzuO3tY20xdNoS1WZ9Cd6zJ3177q62zFD9IqW5Lu\nqwbBMBn9Srz8L15/PmeO818lgnRA+Obqkway5NlS5ktpFQ+pamj3jyYU+gi61IJh4yOrdmG+0YNr\nYFfUfUywA+Vb0DyVlm6VO+PiHnezjyvHEOcYEa8umdPJ9zJG7DIv0F2B2RqLChYKcamD2eAeDTbH\nfV0/YaWwv1GhQ+Ao8z4mbGlH71ah+UI4VMNU5k94werdUcmCZDFEnscd9SO86QRSF05j+ffi1CCi\nv+ySBxYK9APjuLQjNVrNKkjo3sgO/wtZFTimlVD9eKKZO3oJ+8ImII4d0IrCjHSBC0BNLtUvbme9\nmUJX8cvZmqs02dF+ATX/gcguP3DCUJDAUSvbg94oU5zILWF5KshRjRmpg3/63m3Mqua565kXaXW0\nqSB075zLeZeUTxd874xUJdwhzrCH1TkgjtNBULzc+e1zgGneUDlKpF7+GM3E4g2yPDntlKDSV4tq\nZg/J9yLjn1WZ+g3OXJp3EuqNpixt4tWc7g4zpFD+6PkEQHyikmzegOPhSHkmz2B78XcqHnVlVRT6\nu+h8+OajG4S+2zUQ2+y9ii2QR22KHBEnoriSV0FkkgCt9aEB2YKRRKtPBMXtQpeLYxm70Z3gLSUA\nW29k0A/vnaVEOuEOlY/jqfFKbKb1K4q9aVjX+++COWTPhV5kly9w8ujzb69MbaQWfX7p+PvJCGyF\nTwCS/7D3fUAjuzGmkdfDhZccW80v40olYz+LXAUl7tUuByKyy15G+0BKB5YEi6hGFv6lEz3GSGxe\n8/uUmYAPkJ1u1STOydIjaaYXqD83ZO/ZOVEKqhVutfVl2hSHLzYw6/gUFpFcMwZWXX5eOGNLl2/T\nFF4MzK6u9+0KXGdOAvATi0btUYD6QYMM1f5b1kBWZjJcC1//GBYKhkVUuwduwTVT6aj/2wzH5gz7\nQ8qEmTw4zYRBtJXQgOs/voolLCe3EfZEyqm2uQ/r1PchYuV1+d7io3uQFszexWSuf/eYepqWnq/v\nz2Gz7GegP8v46bRpzZKV61eoGO59seLhOTjvp7L/gdDO8xjlrHxYtOpMrNrj06dtbzUUacmPBceR\nd/N3VW3ovm04JbtMLrbwXdgY4PIFgeC5ldjlU2bnibhXKkE2/MjYx8B5HonlmJU3YGnjfnMzuVhi\nsfVEj1uJaRWKiNw0ZAITwD1bMfhDZShTe0WQqn6LrI1/UH5oUhqovpbWw70bz+ENp+D4TDwsZS0s\nSpmlHT0fP8DbRP044UI6dumqUBh6K1XNWgERFQD7UXK8EUV+Idp/rnr1NbNDOlaD0+dhG+p4Id+F\niQe8It9F8OXKRtsV/b7VJ70PE+RuIgrdPemrpm67UkBWnBSKixKvX9kJd4ecWPpr0hHeiPZFRA8U\nD+ACqk7FL3Q4yr05PC//O0H2Vym+cbqKruXPHgWLbH9CI9zSMFo/j+Fq7Aq+EDCG58e6G9X+bmFP\nH/5XNkvZhbeggLK+WQr8H9GQIZLZMQCboRvhX9u+eUuhUUvRU9gwFbtDrSz8K8kJBMzb8blG5UwM\nC2N2y41I2+paR+I2m5hEXkKM9tXl7VclIQIsYF6NoNH3ncc1x4HOPwxgUUR36L2amu/bzBn8MXVJ\nftczkKFdZiYMB5xIcDLovipakJFSH/w2xu6WVXWMOiA5kvgUvu+hbbVi6sHkQNFHYKIAjobH3q+3\nDrc09phW+ROYO+aTcQbKrIjZd71OhsV5rzwZ2JQ7ki7NSzGWrG6x8vZodBDEMCl2MIjkqJ+PHIov\ngo1cRx+oS/5Dae9iXLZjx04CKFNUWUSPyHHrfbNDyOPrdvGCTFr/67j/rGj1J8vVNCxtLm1bEQpc\nSIhvaUaLDRXNEjLHerJ79+3XQHd7IqCcBLemBhPmU+/fiAWJozadBEb+HGZqlMPDNzwkut2l43PB\n24M9Sj7odg/0kwUb+nkDDFoZdwlMwRh+gKg8uvy1/fK1j0sJaMju2Livjx2dKdE1F0GLrtHWI04A\nauTXE9SM5DeEDogTpQeQZPSjlINIteGYpH+oQKh9ZNsv/7z+zVFuvjSsLxXZy0AmwKADhVa+Xh1q\nPOrIzFEtf3FEPdGmEyelpCcZbjgkSf1KggQSt4O4YkgNwswY8tEBLIDAXDQExIjCYv/AIeVtzzzl\n+gKWU0UQjKYMVQCWH9zUlHQz8rQcLCB8EgUlMKDsQVoRJbvQR365CNfAX3W8rMVy4nTztqh7zU8Y\npTMGjwCCnBVie6sRytRY79AmqVpgvBPcuQdAMszg+wqIOS/YOXfWuVWaAHwDpxw6UNFMhWcFKSOH\n05VPD72EbnrzamjHK7JEkayKLgR8VVQaXYvT1jVmwbJ6/f9Gfy8CZaZuJJhKPAbeo8mMHuGWa9HL\nA8hVOZll51JKNbAGr5wPKjPHhfBCcWJqs7VIW00Fms/7xNFGllj/SZtUXSzpO/+2FCnmtjO36lw7\nuBLmHLf7CfjRZYUEgQLNVQA07zta/IkjSnwAojzCOOGiriJKJh6Xxrq7QrpLKKMpwb75V+Bf7UIq\nXCrPo45BCxCLgZ/361L4yE1xbmngU707NlaRF24SuFTe7juhvITEAy3wY6U7A7XsGp1GhBBNaYzx\n63YNFYggmHPw2SyXoCLq+pVuz+tvr1PMqnV3zzb1XvR/5Y4Tsp3bIfi00nNB+tv7WU3mCiKl+KDn\nWulilfdt2qcMkdt7dtmcPpClSu9KfkwSQANc0ehkxDHMf0CT2X361QRvY1BiIqs5wfHnQurPZVvW\nIHViiyTAS3AZ/VOpqQJ9UeATGNz/qAOHlu4l0AAE6xdtAPmQ/ccoAbLOCtCJRlTP4bk+mK/UXsj4\nG5Fs43hzF3JxJ4LR9C2FvUvkNnM4hsoGeWg5/PI3h1hXU7vUZJWEgYReDK1L7mkquUjzkWOBvs/Z\ndZTkag4LuLtNIBkAuT8lMHzT6gfGfl8FX5+8nSILKBx072cjdYwUpvNqyRE2Z/RnolUwJalgqWFb\njwYgWT1LgrAf9zDNpkiBuskNgatldY/dyAyHZ8aoMboKqqPiZMkqJKavv+FSK4leOWqG8/2gaZke\nxNn4gg7BPj+xor4DbD81mH/cZ6YSEZbXxAo5ynx3BpP6mXWX3Q9BVYMbSPDKd5LP/sL+FLO4lhXe\nHGsXA3ZwJficyeFbwqcUF4WXXjftNC8xtQgoYUdMYTmtiO2Wko7wUYf5VzXvf3iAJh6h+ii7bnNk\nQD8LnpXLyWkBAxCxXLS439nKagcl9eGoV9S59YSrP18BCUxHteCTtVutmEwT40IhND3eY4xiK2gJ\n1mJGaWYTHkCq+0qg0+pobyEVhuMvAbp+hax+P5gFIK4xkXaUrJY/rnaXTMMpPlU/ew3xGKHRD6Rn\naz43KtCgy0a0LgYTDuQkkWgfEbeC3Qc3rv1tAYrQoiVSwPN1Ppmyb500ZaLxhfGyslQtV6Cj8IKf\ncHcbEG1SU/vgXR+I/iJitzfGYck2dBP6Hc9bkQiJgCaJyzVJKT2nLPrMra+TZpxLjAf8bfzTaIR7\nyBzAM1+ONLzI4NZwoabqZphQMBeLgkvRZ4iutHq9/65XXwPhJ9rawATImQizNXIWZ/Xc/dBdeYci\ncXlh4cNi9lXr86kv42EtzQO8wiXxvpJNllzagqcYzoDS/2+v9gDA81y/sHczLBSXich8fCL9sHnk\n5HEPy+MWeoxHTXzk4NVKhoDg310u7DNHN/iqdC9jowVF45NxlX5xEGTagsxET2kbWxiMiA+l/seJ\n6hm9WQ5oT/E2yZHcl+/+7WtuGZN65uRALxVa5/5f/aiPVjAc+nbCopYK6mlCZQ1fe6EPe8V6UAwu\nmK6Uxk5h9aHjCoxyl5jtUOUpA3Z2E0IY5HjWDUmo2bW13KxWLnEpTdxtgduawTSy7y1brrIDV9Ou\nthZNeteFd9ZEFakDiqLVxSlFcVeSaMOlBtkUpVqZgEIwE4RUExVbKFs+H5eWDhOO8OZe9cSg9acu\nYYhr68IKC7t9VpDYX5OOgNcj2vxcsNVFwYRGOiq0HeDo2RS36LOmkhoHKBwolhA0gBjZd70RygkT\ne+ujgmuAfYLnTYLZ2nHTE2bGOp0zk1L9xPoBXxIvdp+k5T53k9MUi7R5IRINuNmzr5bC5Qfp1foo\nokZfB1U6tHv1oEOoThzFFHi5MhTQsKEn/ks7GCTg2bAFKYJNuuE7GjA61F1+6Pfp7NPIjUwbK7bN\nTlw/pFPKgsPwRciluwLrUwG/LcAxhFFcg+lpOR6KrBVha2FXaGyrxGufH4oJo5wlwekT/MUb5pmW\nZJgQFHqzjiiXpwW275Qpn8xplJiwEhsVfRYaQIzC5HzBQtBD0Z5xnctY48i77DbgIyL0hIwb/9pW\nQhRC7/N0v7qdT27P0pl+jumTiuNVZta8YTC7G0xouZu+vXxOvE/NO0wbDODHNploJXlfweCV1oyP\nI1N1H5/jXLW0L2eiuCupnTrqSGPbGlL5ABfwLqaZsT5pSY34+77u60VZWbsIexLeWmMfjCRnwqdW\nlazA/KsFkNe9O1U2719btMuPKm+/4TvoYxbpn1POEQsMuuwf9Pu5ujFjLAJq7KtmxM83P+hUfwbr\nG2G0JYCgS4d2fxUgAQiic7SD6J+PBgVi9fHwO7v/rbC/r7wgRKqfvQmlWmB1raUV5e7qFyPgMl91\nDb8DOYHV7Rpd6qEz88xkcQTRT4wIs2PzJ7zBQmRJXb+XbWW88jQEJVpOwGMGWqG33QS7T/CszEl2\n8G/UzSnCH9i0fIkX5bB8hX1jdnr9OkaiXmXu43+ixOyLIbZDRN2aRFEU4bczxAuR5mDXA3WX1DWF\n1LMX3PBCA3DIdqjhKv1+o7MLR+9Hree79XghCuZgtetNgzE+BgpYsP/L+wq4AzZceo2gx/0A3Ad2\nJHE71pWJ/OStHuQFDk7oCr02NKijAhZT/5I73DLzWpVMrpPwG0706DOFl5+bko+2xhL+vKkL4s9G\n43sC21ZYXx40qplG+nB4fhtMI7Lx12xMc6QgJO/DJGJbPIp5sPUk5yZyzFSb6vxhQcGKzF0jRKk2\nblj8QeOpzwmj2vNpKnM80a3UxpPiqfN7qiNdQV/oGE4utr7yunmZfyhLjo/uE0vfzSjmvB87f5Xq\nlSz9CuGzxhmVUGtT60TctfVAGIWcvXELEXV9HRvbEvzJ/XxlarWtZBkumvhDxv+H3/qxTBYBB3VL\nEE7GwzXzsRqrfwK5sZNZBrnzd+XIfp91Cnc96mK+7oU/+LV+A6NtqwEEdxNXA9EK6BlqTOYrfmNU\nUAyIzodRgP4dyJKUwF0WnCNbwi+WgWfKxeD6J6U5fRGoUSwKaIxOmNvBMgeSQ2eA+671h0YMe4NP\nqggDfVx9cXGcpytVWFntnxs6aQPg4qSpVOZkJHP2/oUPTaeW/+Hvyja+m3VTiajRHS+lfWABSwkq\n7pRAbCjzIbKeOM6sY4W63453Ewo296f3xh5ZY65u0scQgUyXtB48n3211e4tIIKNN/AwXo08/bhL\n8gThWAG9WhH2kzkFX3M7AZm47XgemDZnxChGhAXlif7chETEzzJtM8Ytn6zgg/ph9GV3i/Z6aun0\nmrCG0LMtrg4CJo+4mHmQUG27Gtd/PIm9eqWdt4ywk02K4gGJ67YvXnm+EhJHkApngBbKhp+I52ee\nZtUw0Li4xW6bs49i2dOUAjx86jsKeU7uJiWkirUvQ+aK37MPYTPcfME8nYmJNlOwZWzbVKfm00HL\nk0qmK6iDSmL/DSdx9VnPtGsNRFDgI1hAkSsqoGO2mCxxCyfAc48cWKxErLRoVWoO8VSl834ogKht\noeVK58ezIAHphOWtGVwz6GZwBiIy//1koxIMb3oR/qvXYhyucGPrvWOoGAHfpFsQPqwrb+rEKn03\nScU9PlrRZFhZOONC3GwM8Pssp2AOJT6RI+RXmNsMX2QRDtwDnC4vmHwen9MePiN3F/jppJhwA8RW\n/Rm1C2FX8ODUUj/mJU2oyh2u1HV75vH1uvUNFzDmB27k9IBiPpU0jjvuSXAJRPkzve4rYPV9xTL8\nfvi3Vtkjj6ahvzGVcsAVgAX4iWHLuRCHlAmMaXvPjURqSCU6XRgDTx1ia0CoytuL3y2O+KSUqBEK\nUqmtax5Wn+VzUtROS462rJdrp3YARn//1bxpXyg/j1/juWv0yJPQgUYcU3d3JuYIp8Q8jjoVodhn\nP1QPd79DXNB/Pwd711DNxOb0sk8yEPXHXc1Xcnnuz7a1WrYqeU+Ww/PpVga/3biOfdSOi339aWgB\nfndekDI0qMl0s9pWT+9CPjkyL0nbVWARb/uVgNpjHNmro4Nbj0HpFXKX9fwsBDeBmD2lgBrmbKj6\nbdRKGMZutn+k3xVU2uNfdFPeVpbC5lod/2xvC8Ful+0xSpTdyyvsUgfPwPgPtL/SOrLFT0nutxzZ\nkz8gjdMQ4dFDPg5YoKfi+ICV/qlSloXDse3ooI5N1ZuDqcKdcXjzm46vsfHbCZCzGxIgo+W3tT29\nAKYT0/xSqJTbX1kkMmCMOiQqCfGf29k8J1SaP1lrOC5l1AA8nrKBjm3OvciG8hf+5r02GNnwBp8Z\nZDCjx/Atsr+9LAHvecc6HiHJPuNCINcP5TLiSfF0jgcdsQm3869+RWCQUX5yLZWiVCpuQxFzPLPm\n9mjy+MRdZRDrfpkdPkHapHE3kPmPVWQXDTnhLYOgE4vdcljB4tWrpeCNm+JgRQ03G+v+wSPN9TYb\nrwX2GUhJoR/ax47EWPbYauv7LNZ2bJGfOb9s/o8KYw68eXkgj+FDljZzzP0dKUQqYjNgIw2TGCxY\ngcJ7cxv8BTZJ/JTxk7ZL577zd1AInIq0wuKBFqp2t/9tMsxSXegD0PLlzMB2fDYVGmncDtT4PzlE\nozcuiUJRipjY6DoesJlfHKyxNqJNNxjDOW3SjMiKtI8JtSQNH0BSyrRIyGNGXzX/uQArTH65IiPY\nkbNFkh5LMdN5Wn42QqnWV583GGVqmNlGzHkdprd4C+xMN4kkWbjaJVSDHQGeVbUdqT7K6j1Sa/gY\nKGZmys+BhBpakUrOXa2ouadrpwLjtjwhGHVq+zFPcxNyMBIuT43rLb116BwmRtaHmmQRa1Y9fgPg\n7LWLlkhNqEKOAPWFDQUuPpJqYr94vCP0A9arjsxYSzLkGGUsYf0r35nsW4eRMZjFyywzOyktfHup\nchvurg5EDDibgz8QtOdlGNqjerLNTRx+XGEqla27/jSiw8H1kgGrPDAeYsfAVs5y2+3WJNAsw9hT\nZzFM8t/CCIgXX2pj4yrJxSskmH6QjRspvr+VxbpVgFbgSKw/l1lDbmJDDPgX89Wmo0Bog+C8R21R\nqseSnoWZu17XsTWPMkOBeLmus/g7Aw7CMHMIYuQ4A4cJu9j0Gc6RVLvud7iLe2FMoSn0HdrObS/v\nRUAkfW832KW7aEdntoOLUdjtzOQ5QKD8YnNfz4LAzm3OhInLz/DshGnUdxR3EAL159zxjVlLZKGK\nElxu0aK5Jr8coyzWWtm+4HX92C+Qb5vXEXsmqRgIZoQPp5RpRukTUGg4zq4uAWspaTKNzxxlIEYI\npM4B/sIKkQ7sHptRAgZ/K8sDCJolRdeda8ln2ywDEJkz2nu1Kw0jm/+XghX8j1SIOG0qWiz6/Ybc\nzdbJO4Plp4J+X39ZxONVdiGg1EbaJ8UYFl+7inGY0c+VUCclN6lhgWULVKgp0ZbB3yLpKvdDBKgD\n7ZPXHoHemwi+R5aEY7fxs2S9MQcCvo7n2z8hTeHWb+DA5zq8/x/8eWhaI77HZ3DTvtkC2mVsiImR\nwjAkfk0z5JHXQ10Dqdwey7NVkAHLKwgXQG7SZFqrdI2PQV9HHw8bn3m6P+f7/EAy4MkYv8OHlwCg\nAz44PcpP9zXgPo5kl094cZivvFVVOC9A14EHv5xaRJSbue3ckHwAaVgXMonasMWqzQXHHWB4pM/2\nzq4cgM+X11VuzcRfROlRKdmu9umzZJq3sAFpM5xM4oyWtBLLHCdk+kmOffwThUPQcFT6Cp9se2Wv\nBQ3DldAMEtZ/j40qXaVivpsdHisEwN5FZQdxBMQqzZaP4UxldJ4xWKA3n61Muv4KIfoUKajddLuS\nZ5bqFL3zAkvxOf3JPUroU3wJfi2PGRcFmrNSWgp7VEHsWiBw//1PEbEYYXNzlCG322IbiY2RL6iR\nA7vI7/83fM4uY75AhDlBhuQHcEG1mL/9OfaC8TOhJiCwn2ByChDEFZhloTgtP/ZWa3aVGajOfbb2\n9X2Q7O2fzO9lBbF49OOnRLGTGH3jggbIELpZYfUF2wHdMdRJa3vJce8DTqVv771jzqUjE+fnwOv1\n269F8crvbc0cn13uXMkAyw1nN0wpG1H9l1P6jnVhrYq74DkOPEjkiK4unQKlx0aZI/YIHcAfszVM\nY0VIC2djUXZXrZlW3Y4bUmtoO4kMwI/iMgrYuA2cnHULO79HXnYXhrsdAAv9xYSiCAVQv1w7trDt\nXOmMVGvsc7eY3BpFegOKEqPqYIb5cwa75vy47XFo1zUtjPohgZ/g+MCSwqRz13l5N9vQlFSUL857\nRIPEeotyNTAsdh3vFX/jYfsonxch698ZbFLAAZ2uagiQ4oDuMeZpgeUnzcsT64lJa8GhO9cVASuE\ny0F6GpshZvVOe791qrdIB+EJ+FSESXq7IBlZ7u8nKzT3vwJbAFCmo2FIPqzBzR6n3aAQnYVuJIKN\n5Sg85UzY90qoBTGnu7wz2Z8lnZ8kGtpDSDOGhDFHBOGL1+xytbC3IeWxpkSUppE4dMh3UBtUpQpc\nrznsPHtwQusNoU5UHNl+ro08V1FXkHUs3BGo7cjO1E5mEsXECd0Yh+x/PAAC2sove1R0oZM6sGqv\n+cCCB7Vc9Az/Ei+rKcaQ7/cztvAERpeXYbhXrHeIwzJOeo6SllZ6eWAU0t9Umj75FZpWqfPlVngg\nxspwNQyDQ+pzoelgqX6CDTSoJJVBX6ypQoRpbQK004AUM2ODfMQeGrXJroVW7Dn/UvFzPHrPglZC\nHQmAG7G0MAv1OywENidA/tXzqhJYQ8VCtT2y/tKc3sh+T2PofUFs/sXPkTtUY9ALHm3DeX3H4CQP\n3Rb+ibBMospJV/C4wY8lXWgxxVCfBnLgO5r4RdQZ9iG+D+jNnqOzIsmOWgzNE+mbRYtKgPjmCs5w\nkpDjZCTmayxeTJBGAHsyCqnJxUhm0lia66LtCTkMcuB6j6i35CZ97kDpwIOi7AutER7n7lPH++Gn\nm3D321MZdm8kTkBVzTPhrnCA4JFEy+muDff1jfJIYuipA9VLqGCgficM2pPxl5PAt10RYCFRIczP\nImS8vQ89vm3/mEJLxVdbhKLSSIOUe0SyhbZ2qI77n7Pds4qv2SY5jt+R+iIhRASw7/v/kNYUxdiU\nd2whz+3cp4AylBxKxxEOrtr+SEwv9Onfj3IHTQtGHr7vZ7YgYe0YTvUebilhEDptwX6Bk4wHVH18\nELtY4IKlOENXltTlk4Fmfj2DWrqzrYwE27mXmVsBkrge382vltAomA/zHyDmmVAR9fSNI8kJqPv9\nBf0kt+ri0IU1ZZg9Woj0aa6yJritF6/2sxQwnu7hDud4nxN6agLEuHlhB37LbdL4HSPtvvRyQBEA\neetF5eYD5jUT+9nAbGZ+gGiyc7is+4wBcp5djCDST+xp/aqAUweRDNoGPk9chJw7tOrYGAsiLigf\nXAdVxBdEHR7w35WoJZOKR/ohU4uVHNlLcsqfPX8Dvr6UBD0lPGmwIq2vqjVCbdb7t6yILuEq9Ufm\nMGfARBYUMcz0CLCaO6fMddLXYb3+7JNc6BfgeNNs4c+og1l/7cS5kyAZ7etGCS4NmxOe8lgxHUWw\n8IO0tvTl6ukkA/6HFwXkZ0AbJcHifOFomjCv7anv2hOfuO9oEeFpp3WDj12n2Td+ZsWkf1AmoukR\neHaSxklqdCPcEI+UKHxQLNyr8pAOYswoRRGZbIqYW/ta17ZpL5ObFe7L0dnkTerzaK6+7QuQcXN4\nPEGg/nZtybL619pmNPfMj7PZjzIQeW/8N19FXPNLpPAoVClkPHG4Jw2tWKC4w+NgfUpUZJV5/oLG\nE0Qzbcl2mu8ISb5O1UcRkK4QStBrSta2QNvkxAkqOMW/jbQTViSnlFGnQPa3JBnvZ5xx8kSZDoL4\nzRzW+5sj6EamucW1FGMHEcaRnfoI9HYpQXf/8IyKuWe1UyYuhDL/2GkuQjpJTaIy21kze3sprXk6\nwpt1QJZ0Edtv5/8ks9db7hw2IbtXZBpSZpvE9ugD0lLiq5rPGhEahktiI7dZ3qbKT0bTXgXhrq9q\nSUMqwZoXaG/OkXvzEGInn5k3AP8V71EZfoxn5fn/UOuomkWmITLVKtg7tWd1LyrVbmJiZZFDZ7qI\np/XN53yVoQSXwoT4AshECVSbN/qX2+Qwu9Li7N8ET6x0aZ5qsJoEZr2yW2YVjQfbzCQy2cyj06/R\nMr7wwHXXa9rwr8iPvJZqmheEb7Y0AT8RjFFkICCE3TaRpLpc5GXvlm30aMqecTG2WVjbcnNiR+4F\n/C2wlDxRVm2bYvBdaKYVpicEjIE4yUAuMM8LkISEeRh569nRfVlQvmBwU9/WwXT3Ti/9jnbnlYvr\n+Ahjwb2/qNZd5qdcZoIm53BHEPFH6Vq1H/Gh/kzAJKdFN/PoXZKFLX463Mi70+9jrOYA1OiCHndK\no3zf7txPRp00vR2xJpj4unJbmpT4ffdThfuCSmKXRBTTZrgzY9yS6ftKCkee51Ztt+U6nPNlUpAN\nllyRhHkTPq060dxFuYOAoh9z58j+mdFB8eni0jqIqTlySXsVysNMX8AEngW2l89h7oV7E6W3Cthj\nLMSiKmG2/uMLyVm+c2btxBH1BiQRhQ1Rv9q39KwMbuGrzU1o1P3FtPG5HSsyJGmJtp6rDaNiiwxb\npFvHTWhTiDlj/0drNkTzFhG1JwaNzt0kOuewsLPdSir3uklbO6ecYaPK8Z4jgXerghf6lEyknZLS\nAYkKYA3rNh+45AAi1hRUOi3cp/pEHV/rSRmAPuczKvBZi/XmAqj6LGPxNcENDgMujqSw+7+uJJ0U\nQ9Yc5CELdrqvZ7mpxDFUx8QeiSww/sXE6aExkV68LMQHbrd4YaV96mjBcBLcyVqzRhLPDyuNzEFw\np4qk0TDXF1ACMNds2+Dt/Uuq9fxkmO5/q/GV1TyqO2RLP/z8GSXYvfZqOpJDtkFNGW4YcUU9OabN\nad+Q/9AomAx6BhJN0djqPBEafbnO0Jt3UVlPRE+gFekn0MvN+Tvw8vtBYQDL9VjaXZ350tmEqM5n\n8r4nQDI2NKf2AqFC1h6yx1D80OPYltLCRgU0y2GMZwp5ffMxpciUQYx48wteQkIj1vSGxelD7w3D\nFp/RHW7VRDRDzGez/pb0ZUlkmUzN7U1Eo3XRciUGIqIIUNn/ONyb3yvpQQA8wPiq1mwZIKZxyItD\n0U/CJNypm/F4npGM0VnY7fDcgFt7D29oorNPtCf2GAGAwDgKQmSNPmHVa8jJsYiuDcpw9URnTY9V\ntlH1HgWU+Tvr/riLXwOUqSufAPwmdP3p7nNAJVhufvf+5dLe5d3hxHtLxI6kjQwypWq3UBSwzQs2\nLO1+IJ1O4ds3iOra8+5J6u94UI1YsUbGYPOJwvzJ6SjHcLu8x6cWFhaUV2G6xs1fpi+7XO3lbm0y\n5W27tdy11ymOBHal9SdMg+tCFS62wxb2pPE8ZYDSXcwFxnU2QoKifLjZMYzKxXJFwweri6WL3VCt\niqEVBjol27uPCleezJI93TjZrRwL5CETU1b0nUl7hB5tni/KeEvIgKJ04f3KhE3w8g2abb6a0kXC\nuIlTQIIPxUM1ALbGJ+4f5qlVpvJ7nwT2bZ394BwTsH2S8eP241Bq2eVSuOi3Ab6tapNU4YNxIpBL\nDzcIQ/Jq3ToPenfueZrnGr3xKjeXYHJFhki5fzQIs0UkV8rvZP5qWUrko6dILN62pdzGOFJ+y4W0\nXfyMB2uKuXJv6Utx9fFydtYUyEj8Zrn90goiFM+NQU0iFdZ4QEvl1Ts+dv8/rrQH3eJTZqvI/yE3\n12TofYflRc2uRuGlx0r+Q6/3+33yPzrfr6U/aRx1N2E+vcv/L2kGVucq16ibQzJGIZqfHdBints2\nnB/xvJob2flgExd0M73QfeiBCRHzrKKyzj9Xy/YqcQjnpVZHJ0z8Khrxyx3uHHEjnFnVbod7bFEU\nc9ZV++TR2/rvd4/6tgAzf4slQhJqLWCG50xvRj+FPZPCbvxvtFnpArHuGPLhQP58M+qu8J1r6I7s\nag7qtFsFsPbykd8JxRwlB3lt4K7cNC1bKu6iSfT4vsU6XRY/ascVBykqvZDfh/zsnUvrZgmKCCBr\np5h8nDwS5zWHjQ5jShlMEqUr1g8tXsoh0g0RCOAYfHMpevkuPO3hdOrwj6+xJKkkfvuUKAJ15Siq\nsfGhPHOKEye2SzkPITZCk6Epg3vCrRweshnptUBNLAAEgZFGjAcsUQpnC+ckfUoseyAmdGwL2gw7\njQTTYXUrHvMyk+sKl6YTqd1bkaKW4kkUvaZ/rhWQefXwi759KpCKAStFGqfBO0P0buiDMWT3NQZW\nSLbgrltCu/0xvuYiq4t2Dq4pEfgQhWDCTXNAaavjbEt3oNWVDk2/oLH9DhhaEGJ7cp8+e6N6+QOS\n0bspQnURwauJmMJ8yUNYyf9ta8c40Np3aJDOareux0hbEISmQSc4Ibt8NqJFXqF7N2NWS5A+gSsi\norAZxPtzThjQ23JkrwJ0ZPNmbmcrPw1mfTOehFBdqoWPx/V1eDm5NNyriTd6LoYLbfHomQ+8WALR\nvZEOzoN+xewA5Uyk1S3+MzmEKZ3CVhK3GHoxuIMA7jpKebjYySo4sCnlQMb6qqT/bEYEyIsnWvcy\n82f7UbQc9TnIkHDhaRJw2m92dRvylHLCW54hHu6QLRMVKvHYeJNzEdtEit7GocKKSTkPn4BPI/Yi\nDB78TGR7uT3b85v7IOyxHBzEe9as39kKuQRced8pqdr9rbXMTxKG9fjurivrGePnZUbfZnOrpVRL\nkKCb+IpI64a/68XG/DR/SKALmfHrlb33vpCSd0LPcJ9gJUYGctaIA7XC5VtBzhDIcR9PBU+tTm9W\nau9psrwiInRr05n+P2ka3juxmJUvRjj+VYdfHsFkpNtAyitihSAmtBzaFQ/GCY9qd7kXWuxltG51\nrFrtLeXwN+9Dnr+9ExBWRWkyD107BNXg7Q127EZxGeVB9VR/X1KLOqjRClcK7lJrRpdva5kHRJ54\nKhRZV1sepRiHDRVCJIhJ9U6FWd/rQgWMmmcGawdgO1OX8kC5EdLJpXpkSeH5Yjqv3zzjASPu7K1e\nwWPiAxuwVgjdGKJIbluw6G5pJQ2uXDR5Xa5xsfAdroYQ0IRUvAkeOY3tND4Lkw/XVvx8KeFAWTNp\nXenmRJ5/iBqiIfM/c/rIofFpZCA5QqrNEMfQtDBkAJrxtq1sol50O0rih87WaJ+mdtwngYU7HOXS\nRQ+QLH1ciUq6EcJ73P+0hPAOokjzgjhqaori7+/iLyN1C/AWI1S59VXo4s8Lrl4s1/kVBR4QHr5V\nNiVmq4cDDDzuL1SP1j/K7bkn0GyS/RY8DPXrsujE06j3tTvjvnMGY/HaviTzAHivPGFzfXWofpT/\nFOBIBBwbn4pUVoeGWQJXIoNTcyeIxLLEOiJ2zYAUEwEdsOn+f8+dtBaERYpwAhYE4NLbwH6ple55\nRwSPKczzLDMieRAXxc+iQjGV4j/5oqHAmcwgXN7zvk/aGpMYPyA2berXcmFw0LSY1sepZIKYaWuj\noYF9Y7ElShrguXYyk1lAuvOX8VPhIpudfS7dnJHZRceapQi/Xl8DlsQg5fPaQo7gvh+5Hxbe5/dt\nsNmxiidiIGAyoTi091EqBHlEwjR9IhtjBB9469BfzhnT6ccPVCINNxJpiUBJiEOtublFQ/M7KWIP\nfC2d0pCxn06H9bmLT9zfhWsyldmMeBU9AEB2Ck/kn+c75sFlRezkk8wmqlFM2NcAvQcSf8GR2hO/\ncFxi9ZzXFOJCgdfy/9zY0YFHKKnurAgHZlgOdBl8inDgvgC2RlDXnzIuz23kNA9RxHQ2/FXl0z61\nnYwe+SCMNDzoPcUZcUBhPZonJ+3irIWLUdjkbb7qTGymgjf5KR/XMuWA/VX/8uRtjWSOc95Nbt8a\nCaci43oMh2lwO79FoeUffZYmZV3fldqnDs1ze/aOGywPwqcT1jntje94qn3lvQoQ/BJ/k93rEy+2\n5x0vRK6gNlXO4KtnS9D9Ypwk0VbvxdQ8n1IGdI8B9XTjg6ENjqtUbomhDPSFQCjwicweZXrRfUOD\nh+cPfCp22/DQgxGK2DHVgSjAS7NgTpMzbMt2/jQdh7ewO5Ek07NBPGfI47RJujdhRIoS6lFB2L5i\nM2Ly8kjyyAQreVG7AMc6P3r5WOlcr9TujTmvWGh8TOwQ1LDhVNVKJ+JGG1AzuIFYfDJBzzcZd1A5\nteF80j/Z0cUfa1hdkR4d4OTqS5QotD9WNh4QCndwopopxD6G1h9s/s5UVf0blaIfjDBU0/Nx9WVK\n6t/6Ruyhta8hQ9IxRw2VqEEY6Evx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protect end_protected\n", "num_lines": 530}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_1 (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26,\nprobe27,\nprobe28,\nprobe29,\nprobe30,\nprobe31,\nprobe32,\nprobe33,\nprobe34,\nprobe35,\nprobe36,\nprobe37,\nprobe38,\nprobe39,\nprobe40,\nprobe41,\nprobe42,\nprobe43\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [63 : 0] probe1;\ninput [1 : 0] probe2;\ninput [0 : 0] probe3;\ninput [0 : 0] probe4;\ninput [63 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [0 : 0] probe8;\ninput [0 : 0] probe9;\ninput [511 : 0] probe10;\ninput [0 : 0] probe11;\ninput [0 : 0] probe12;\ninput [1 : 0] probe13;\ninput [511 : 0] probe14;\ninput [63 : 0] probe15;\ninput [0 : 0] probe16;\ninput [2 : 0] probe17;\ninput [2 : 0] probe18;\ninput [4 : 0] probe19;\ninput [4 : 0] probe20;\ninput [7 : 0] probe21;\ninput [0 : 0] probe22;\ninput [2 : 0] probe23;\ninput [1 : 0] probe24;\ninput [4 : 0] probe25;\ninput [0 : 0] probe26;\ninput [7 : 0] probe27;\ninput [2 : 0] probe28;\ninput [1 : 0] probe29;\ninput [0 : 0] probe30;\ninput [3 : 0] probe31;\ninput [3 : 0] probe32;\ninput [3 : 0] probe33;\ninput [3 : 0] probe34;\ninput [0 : 0] probe35;\ninput [3 : 0] probe36;\ninput [3 : 0] probe37;\ninput [4 : 0] probe38;\ninput [0 : 0] probe39;\ninput [0 : 0] probe40;\ninput [0 : 0] probe41;\ninput [0 : 0] probe42;\ninput [0 : 0] probe43;\n\n\nendmodule\n", "num_lines": 149}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"ila_1,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_1,ila,{x_ipProduct=Vivado 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C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993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*)\n\nmodule ila_1 (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10,\nprobe11,\nprobe12,\nprobe13,\nprobe14,\nprobe15,\nprobe16,\nprobe17,\nprobe18,\nprobe19,\nprobe20,\nprobe21,\nprobe22,\nprobe23,\nprobe24,\nprobe25,\nprobe26,\nprobe27,\nprobe28,\nprobe29,\nprobe30,\nprobe31,\nprobe32,\nprobe33,\nprobe34,\nprobe35,\nprobe36,\nprobe37,\nprobe38,\nprobe39,\nprobe40,\nprobe41,\nprobe42,\nprobe43\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [63 : 0] probe1;\ninput [1 : 0] probe2;\ninput [0 : 0] probe3;\ninput [0 : 0] probe4;\ninput [63 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [0 : 0] probe8;\ninput [0 : 0] probe9;\ninput [511 : 0] probe10;\ninput [0 : 0] probe11;\ninput [0 : 0] probe12;\ninput [1 : 0] probe13;\ninput [511 : 0] probe14;\ninput [63 : 0] probe15;\ninput [0 : 0] probe16;\ninput [2 : 0] probe17;\ninput [2 : 0] probe18;\ninput [4 : 0] probe19;\ninput [4 : 0] probe20;\ninput [7 : 0] probe21;\ninput [0 : 0] probe22;\ninput [2 : 0] probe23;\ninput [1 : 0] probe24;\ninput [4 : 0] probe25;\ninput [0 : 0] probe26;\ninput [7 : 0] probe27;\ninput [2 : 0] probe28;\ninput [1 : 0] probe29;\ninput [0 : 0] probe30;\ninput [3 : 0] probe31;\ninput [3 : 0] probe32;\ninput [3 : 0] probe33;\ninput [3 : 0] probe34;\ninput [0 : 0] probe35;\ninput [3 : 0] probe36;\ninput [3 : 0] probe37;\ninput [4 : 0] probe38;\ninput [0 : 0] probe39;\ninput [0 : 0] probe40;\ninput [0 : 0] probe41;\ninput [0 : 0] probe42;\ninput [0 : 0] probe43;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_11_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(44),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2020),\n.C_MINOR_VERSION(2),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(0),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(4),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH 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65_MU_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT(1),\n.C_PROBE275_MU_CNT(1),\n.C_PROBE276_MU_CNT(1),\n.C_PROBE277_MU_CNT(1),\n.C_PROBE278_MU_CNT(1),\n.C_PROBE279_MU_CNT(1),\n.C_PROBE280_MU_CNT(1),\n.C_PROBE281_MU_CNT(1),\n.C_PROBE282_MU_CNT(1),\n.C_PROBE283_MU_CNT(1),\n.C_PROBE284_MU_CNT(1),\n.C_PROBE285_MU_CNT(1),\n.C_PROBE286_MU_CNT(1),\n.C_PROBE287_MU_CNT(1),\n.C_PROBE288_MU_CNT(1),\n.C_PROBE289_MU_CNT(1),\n.C_PROBE290_MU_CNT(1),\n.C_PROBE291_MU_CNT(1),\n.C_PROBE292_MU_CNT(1),\n.C_PROBE293_MU_CNT(1),\n.C_PROBE294_MU_CNT(1),\n.C_PROBE295_MU_CNT(1),\n.C_PROBE296_MU_CNT(1),\n.C_PROBE297_MU_CNT(1),\n.C_PROBE298_MU_CNT(1),\n.C_PROBE299_MU_CNT(1),\n.C_PROBE300_MU_CNT(1),\n.C_PROBE301_MU_CNT(1),\n.C_PROBE302_MU_CNT(1),\n.C_PROBE303_MU_CNT(1),\n.C_PROBE304_MU_CNT(1),\n.C_PROBE305_MU_CNT(1),\n.C_PROBE306_MU_CNT(1),\n.C_PROBE307_MU_CNT(1),\n.C_PROBE308_MU_CNT(1),\n.C_PROBE309_MU_CNT(1),\n.C_PROBE310_MU_CNT(1),\n.C_PROBE311_MU_CNT(1),\n.C_PROBE312_MU_CNT(1),\n.C_PROBE313_MU_CNT(1),\n.C_PROBE314_MU_CNT(1),\n.C_PROBE315_MU_CNT(1),\n.C_PROBE316_MU_CNT(1),\n.C_PROBE317_MU_CNT(1),\n.C_PROBE318_MU_CNT(1),\n.C_PROBE319_MU_CNT(1),\n.C_PROBE320_MU_CNT(1),\n.C_PROBE321_MU_CNT(1),\n.C_PROBE322_MU_CNT(1),\n.C_PROBE323_MU_CNT(1),\n.C_PROBE324_MU_CNT(1),\n.C_PROBE325_MU_CNT(1),\n.C_PROBE326_MU_CNT(1),\n.C_PROBE327_MU_CNT(1),\n.C_PROBE328_MU_CNT(1),\n.C_PROBE329_MU_CNT(1),\n.C_PROBE330_MU_CNT(1),\n.C_PROBE331_MU_CNT(1),\n.C_PROBE332_MU_CNT(1),\n.C_PROBE333_MU_CNT(1),\n.C_PROBE334_MU_CNT(1),\n.C_PROBE335_MU_CNT(1),\n.C_PROBE336_MU_CNT(1),\n.C_PROBE337_MU_CNT(1),\n.C_PROBE338_MU_CNT(1),\n.C_PROBE339_MU_CNT(1),\n.C_PROBE340_MU_CNT(1),\n.C_PROBE341_MU_CNT(1),\n.C_PROBE342_MU_CNT(1),\n.C_PROBE343_MU_CNT(1),\n.C_PROBE344_MU_CNT(1),\n.C_PROBE345_MU_CNT(1),\n.C_PROBE346_MU_CNT(1),\n.C_PROBE347_MU_CNT(1),\n.C_PROBE348_MU_CNT(1),\n.C_PROBE349_MU_CNT(1),\n.C_PROBE350_MU_CNT(1),\n.C_PROBE351_MU_CNT(1),\n.C_PROBE352_MU_CNT(1),\n.C_PROBE353_MU_CNT(1),\n.C_PROBE354_MU_CNT(1),\n.C_PROBE355_MU_CNT(1),\n.C_PROBE356_MU_CNT(1),\n.C_PROBE357_MU_CNT(1),\n.C_PROBE358_MU_CNT(1),\n.C_PROBE359_MU_CNT(1),\n.C_PROBE360_MU_CNT(1),\n.C_PROBE361_MU_CNT(1),\n.C_PROBE362_MU_CNT(1),\n.C_PROBE363_MU_CNT(1),\n.C_PROBE364_MU_CNT(1),\n.C_PROBE365_MU_CNT(1),\n.C_PROBE366_MU_CNT(1),\n.C_PROBE367_MU_CNT(1),\n.C_PROBE368_MU_CNT(1),\n.C_PROBE369_MU_CNT(1),\n.C_PROBE370_MU_CNT(1),\n.C_PROBE371_MU_CNT(1),\n.C_PROBE372_MU_CNT(1),\n.C_PROBE373_MU_CNT(1),\n.C_PROBE374_MU_CNT(1),\n.C_PROBE375_MU_CNT(1),\n.C_PROBE376_MU_CNT(1),\n.C_PROBE377_MU_CNT(1),\n.C_PROBE378_MU_CNT(1),\n.C_PROBE379_MU_CNT(1),\n.C_PROBE380_MU_CNT(1),\n.C_PROBE381_MU_CNT(1),\n.C_PROBE382_MU_CNT(1),\n.C_PROBE383_MU_CNT(1),\n.C_PROBE384_MU_CNT(1),\n.C_PROBE385_MU_CNT(1),\n.C_PROBE386_MU_CNT(1),\n.C_PROBE387_MU_CNT(1),\n.C_PROBE388_MU_CNT(1),\n.C_PROBE389_MU_CNT(1),\n.C_PROBE390_MU_CNT(1),\n.C_PROBE391_MU_CNT(1),\n.C_PROBE392_MU_CNT(1),\n.C_PROBE393_MU_CNT(1),\n.C_PROBE394_MU_CNT(1),\n.C_PROBE395_MU_CNT(1),\n.C_PROBE396_MU_CNT(1),\n.C_PROBE397_MU_CNT(1),\n.C_PROBE398_MU_CNT(1),\n.C_PROBE399_MU_CNT(1),\n.C_PROBE400_MU_CNT(1),\n.C_PROBE401_MU_CNT(1),\n.C_PROBE402_MU_CNT(1),\n.C_PROBE403_MU_CNT(1),\n.C_PROBE404_MU_CNT(1),\n.C_PROBE405_MU_CNT(1),\n.C_PROBE406_MU_CNT(1),\n.C_PROBE407_MU_CNT(1),\n.C_PROBE408_MU_CNT(1),\n.C_PROBE409_MU_CNT(1),\n.C_PROBE410_MU_CNT(1),\n.C_PROBE411_MU_CNT(1),\n.C_PROBE412_MU_CNT(1),\n.C_PROBE413_MU_CNT(1),\n.C_PROBE414_MU_CNT(1),\n.C_PROBE415_MU_CNT(1),\n.C_PROBE416_MU_CNT(1),\n.C_PROBE417_MU_CNT(1),\n.C_PROBE418_MU_CNT(1),\n.C_PROBE419_MU_CNT(1),\n.C_PROBE420_MU_CNT(1),\n.C_PROBE421_MU_CNT(1),\n.C_PROBE422_MU_CNT(1),\n.C_PROBE423_MU_CNT(1),\n.C_PROBE424_MU_CNT(1),\n.C_PROBE425_MU_CNT(1),\n.C_PROBE426_MU_CNT(1),\n.C_PROBE427_MU_CNT(1),\n.C_PROBE428_MU_CNT(1),\n.C_PROBE429_MU_CNT(1),\n.C_PROBE430_MU_CNT(1),\n.C_PROBE431_MU_CNT(1),\n.C_PROBE432_MU_CNT(1),\n.C_PROBE433_MU_CNT(1),\n.C_PROBE434_MU_CNT(1),\n.C_PROBE435_MU_CNT(1),\n.C_PROBE436_MU_CNT(1),\n.C_PROBE437_MU_CNT(1),\n.C_PROBE438_MU_CNT(1),\n.C_PROBE439_MU_CNT(1),\n.C_PROBE440_MU_CNT(1),\n.C_PROBE441_MU_CNT(1),\n.C_PROBE442_MU_CNT(1),\n.C_PROBE443_MU_CNT(1),\n.C_PROBE444_MU_CNT(1),\n.C_PROBE445_MU_CNT(1),\n.C_PROBE446_MU_CNT(1),\n.C_PROBE447_MU_CNT(1),\n.C_PROBE448_MU_CNT(1),\n.C_PROBE449_MU_CNT(1),\n.C_PROBE450_MU_CNT(1),\n.C_PROBE451_MU_CNT(1),\n.C_PROBE452_MU_CNT(1),\n.C_PROBE453_MU_CNT(1),\n.C_PROBE454_MU_CNT(1),\n.C_PROBE455_MU_CNT(1),\n.C_PROBE456_MU_CNT(1),\n.C_PROBE457_MU_CNT(1),\n.C_PROBE458_MU_CNT(1),\n.C_PROBE459_MU_CNT(1),\n.C_PROBE460_MU_CNT(1),\n.C_PROBE461_MU_CNT(1),\n.C_PROBE462_MU_CNT(1),\n.C_PROBE463_MU_CNT(1),\n.C_PROBE464_MU_CNT(1),\n.C_PROBE465_MU_CNT(1),\n.C_PROBE466_MU_CNT(1),\n.C_PROBE467_MU_CNT(1),\n.C_PROBE468_MU_CNT(1),\n.C_PROBE469_MU_CNT(1),\n.C_PROBE470_MU_CNT(1),\n.C_PROBE471_MU_CNT(1),\n.C_PROBE472_MU_CNT(1),\n.C_PROBE473_MU_CNT(1),\n.C_PROBE474_MU_CNT(1),\n.C_PROBE475_MU_CNT(1),\n.C_PROBE476_MU_CNT(1),\n.C_PROBE477_MU_CNT(1),\n.C_PROBE478_MU_CNT(1),\n.C_PROBE479_MU_CNT(1),\n.C_PROBE480_MU_CNT(1),\n.C_PROBE481_MU_CNT(1),\n.C_PROBE482_MU_CNT(1),\n.C_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1),\n.C_PROBE691_MU_CNT(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synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4327}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nXvoWuyjysN5V55U4xsjyWg2bXI++8I1KAZgJ0eiQkY3L8ns1PfNti9fujmr8wvFQA6ycwh4K6mSp\nINQjc8TyLQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nbD05I2IKef08FLVG4C2ftkJOY+/UsvagxY6ta+A0N1USwLQivKTmRt7LJlQ+5UJqrfPvhHMyYrLN\nrjoJbClg85XfNTYCnalRVvg3mmCcjtJkCLf6S5E9Q6UF92b6bwgtMTsr0BndJhdItlJtr0dYZtoP\nAEskMBthh6RdNMkZ3CA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nvLo4Yp/zX6HvZ92VMA2Xr4EIhMWPNGq2EvSBkjiZd5sCSFAX+37MKx4gdbrsGvhUMl1njqvSaoP7\nKrAa29/cm3QWjPgpaCsR/MhnaG5+7aUvxA5iCqVHXdriMlgx9kzxkB9SD+mOC8XR5LtYA0bPhbZ9\njQzWpWxdaOGYFF25DU0O9M7LMc7SLfKunYH/cQ91D37m0LjgZh1/uZv8chFzvCBbkHqUU0qi17/k\nZTWIIzqb1oycbuhZZrWLl95xQ/aaTxZ30sONWd/axZtO3Cd57huCbCxLuOH51qq6erD9AVszmxL8\noEoM+KW88P1S3LJ/EcIQN4LU0/nyN/f7xEmy2w==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nj99ihkoCqIO9DhRZEJdEqlRF2P+IwS2wuYmoh3hWFCDXbmGTwTqc+3EMjxY8Z4uDixuazjlTMiEH\nCk4MdTkVZ55pPhFb4druHTap3Twn20B3SWvOy2nf84OpTkdBnbK4qagABgZXs9/mAtQxbF++/F6Y\n+OOE3yUNTWvHiVGvpTJavfADkB2CL5wEIlBSnYRwtLp71JokDsMvjq2l3o3hxAjvtdg9ej7NKx4I\nkAZfrpZH7Ebv2hfXrTVI2kDTAl5Etr+4oSqxIhABJut2WaeWJrsSbL+dz9s2ZmYDMb1BCQdRexck\nbMMvUaS+P7sSGuR9BTVynHOY5GdQelHO1aazQw==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nHuzbd0U90PuPKn40554Cnki98HuQSq7dg6ZyXufEWFHsji6rteNupAY3HQsuLpXjFVxsNlS4bcHj\nAAOnDcL0hCCVbSkU011mqhhlkFmWqeBBECGfP+T7/+l9KBu+9ynszhlhaVhmZMffsEuohDl5x084\nFnzFCdxrFyvqrOyWDac=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\neoQKmSsNWNEOJcUApe0UhUNGRDkxOLedPbjyDILgUJWMG+WVCpL9MC2MXZeZ6/oVwAYRlZTZsF1h\nUsVo6BO7IAuHuJAHeIQgEs2oIMj/I2qZxm9wUsOzWoK5/Jz4SS4sTE3TgOJXaX1GNAJlbUrCBtnM\nqIiavU164vZjX5BFoPGuHp4kICN8A4Wr9y2w2Lh0/IdiHjr/Ruk5PpVNyl7tW9EaSFY1AL4aoQpd\nRFDdUFRk4tMBtmFxi/B+pLVFE0hAUZnlVCsSaf4B0lN/m4CME7lgy7oXElp7ov4fMnD9VI8HLGMX\nWBSQjD8F6BB0Wblgm9lJNc0h0VqxxD4DbRleKA==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nyrn0K+G4SU1wuMdE7DJlKWErX/N5nCqD3+dP+4ONmo8yuM983VHfjLhCoeQMbM26e49U4PPdXcDR\ny0rRemqJACoi5H5NvzXohhKZI9q+WKME4TkhFzfKvIwyta1m/uNSe/A0+52Dzbg5uAxYihw0IdZR\nZMywfa3deZ8IUMz3kWSlMs1P4wESz2pKpdYGs0FpvovucuNn4OhZKH7RGX8z8Zy4E9juZRgnSQnX\nmvRtisgVB9uL2J0vl9XjW/1990VYZi0nrZJ8gQL38HLTz62vDuMuYjiFbbnDCujJNKOCHh/xJTdt\n73nsz+dY3We4tQdnxuESibzLQLGF1l8+d9FPDA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nJPIGH1v6BG8bvo+3pHrWlum+XEDtFDlKP+4Toq88+g/eeinS/p8A0zMVVYj4wfjGDhx3kGvJ9XAx\ngxYpezvlgnz+IEGWQzepCMSp4iHz9TEdGkc5LTQj50VJj4+HGz2Qhrw96Hw0c+5RDrv238ILy3p7\nuzIPIzxKEl8D7gK6b8ZPrzx95KMPuGZyju4JUHBWdjDx0hhhIl+L3Ju/bVyWaWd7w1xI0mreJtAN\noOdcObOESJpTuj0KqFtfA3UY7v9n9Lj/I/vMaPX7LnSIZuS+tHyiD8D+t+Kf6XiIl3sYDL9erP7t\nSpHvPfG9bOfGRxM7dmsvKj+XqHeXg23wyS1Nfg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nrxmK0sxFw5opGoAsi+RHBRwE0wYNls8LL+oURMgLNuoRDOPNH7up4F86jASnrdlvXLShGHMZnaJ6\ny1orZ0uAZ6xxM2PeKAxvxBI02HOu0aXd/SMNxr16dADlCYK6R1DVdq3DC+T8bQTLWyyHr9r4m4En\nW5DcJ2hEs5b31PUg/DoCNTpHm2swT7sLG9qRkSfTddaSyGTADcvRXYjnHKHin6TQlOCZufWMm54P\nPJeCQmj1MjyycQGpsvFNX7VMxW49ashO7EGmRdy7lMGRoHDqLWBxcIlwAS4L28iuln/NdC/QV538\nQei7EbcqeUmfs07XP8FKxdA3hi3Aq2Upg9DkOw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64736)\n`pragma protect data_block\npJdOORWQloxSGvgvy0l4tBp1HqnYdonsYgNOe99SLH3qi9BP+2tNlaoelqmLJLSHNsBn3TJxXlZa\nnIZxc0/l2jA1h9Jz15QEEgUR0MqZaESeIPQdEbADnul6xUXY0J6g//n8Vnzph99nb1v9j4yp0I8W\nmF2Bvdz/qHJcUcV5zedPk5PkPVS8cmwYFQWer3rOMl6Or1E/YoHi9T9wfbgxxTs6yzqYqVGUBlz5\nAlhSoRF+xXB1Z4h2Ny4v4u05pGtbpnnDj+JhauZ7AfT+uRL3JZ7hNdSiI3coyNU077RtI/1VAmYO\npJoj/3tO2z4y9phvRShE/Otch4qxfx53IywqoRQmUF57yV4NjbkGPW8j7U6iQ8Ls1911ZAOgZIga\nmynl1jCs8ajbsNdraT0wfsPf1kWJOCuUGyItYv2eEwfh7iEYRrpT0V6YT5gENAgDuriQCZuFtnJE\ndhvImjwTXy3d76buWun43bM5pyUNSUzm90uucXHtbfsv8HZTM/chDluZJ4cMeW8D9Pwjtvo6lXLx\nYJM6v2cUpOTIMOcKDxrRTFomRQ1DwRsa4wQGal4q2dhrokLR6YNhu1ED6+AbEAN+FWui25yRPN2c\nRifAbYj3+oa+z6kUON22gegvkiRIe3iVn5MeyImok+P+5dmykiOW6L7J+GDFd4UZtYwJkwUH4ijt\ny9tlvkg7bhgKKY/VRht7EZFg6U4GjUBwLTEWIsD/6R8LgyENKTNO1FVyOJge9+hJYOxJpk93nMac\n0dR2cl0TLESIEfZQ8wSlqKcnzibNa/Mwa+gyj8uNmBtlGMv9GLnh914fnVrJPaJYjkLNLesy5uKF\nWOOHFhlsuqMHkybog57X/W2y+bzzdtaWoQ8/DU/QWGyTt3Vhlmu4YBKvv/DBB51RUj7naprx+CNR\nK7/l3uoheqcD/zy4ipVqZ/mSOTxjqNwJ88tpKUTD7UHuLf8rEeiu80iR1raYJGMHzUS7FcK/APPf\nbBCJIKpjoq1C63MJYurbOeqWcRL3DDPi/z3C66E9WG/nFKs7vMkhbVhClFUAjy+DwMCS7VjbvUvn\nCbr4m+kTXY7ipbBxU7YIDWHssBAAjeM1Rdxx9VvDqABN+rFZAA7C08PNPUeOiVYCFO3gmbAqYK8f\nEPeBaPUk6eskVX2sXw5/qrh1a5mqGk/sYCFZItuYZ6SMz1BFuaZz+ac8Feq8+d7gH2f1DuK4EG20\nOgLh0liUdRk5TCUZsSZTlhRd1FA4SqglWHYk+GIL1WEcVBskAEiY2YIK1TGXzUQaG00TT5TRBNmv\nsPnVI8z6bWwqXomyqcYSelXrfl2izqtjadlA+3+0O2A1XhL9tmMhT3v0nQIlobxn4nFE376czv08\n2+xLHI/chXlg2WvKMK3NCBbWGw7tnHSdJc47JRdiCkb0tIr9wocUbWPbM7W5G3Ku+bQZQXPM0lNy\nstFAjwukEDL4vbC72EJbEwf+6kzkzLjBrc0JDEzvjqnYQYiwloQ0qi9k/yE3bXcnEHvgw8ig5Y/S\nt9SttzL9mNMXwbouRg1seAZ89RrLrTNZiBk2TlhzdIfvWsbvdBYdIhaMqKRGJFpWxZgPm+JbW+09\nfF1z2nf/18EW+WziUuICezISE4+2HDfqFOEltKV6AdesQWDrloYiby+MezSSORPfWkx+nVGv8JEs\nI01podsuoWFRpVmbt/Dua5qZk9EOHGFBRgvYNnlH47YVREn5j8l2T/0bBlGUrv4r0tmSTvb5Rk62\nTtYvXt/3/jJe7TX05O4Uz8CDBe02LhhwyNkyyNYPm6hcqislaGMW5IrlUBR19xoKivY5xsi9WHEp\nOscK7GlXBFf+1ZdqPUIFBzo8CoanS+vY6N5dX/zhH9ka7wSGlru7qjqAyYG3VOzYi+lIUT1D0l0A\nhIuLJhQlgGIPioPMX5r9G+nJX9J1xhmQmslUobJCrtsIfoshA1m3sO8FVq/uKShEPK85uU48DmE1\nBM73G3APR/Pn3q4udJagFjB+ngJWARXqQX1U/fZdrs1d4U8E/KLlkVQywLtM4ImADW15ZRE2zwbt\n93vD21KzRF0gTEp32+Y94DZJmilvEITUz6i6Uf3GIhk/8VlW2sgoZBxyIXdlfZU0hAeWoF6z0y8i\nsz3YJBSL59bOXPeovsUY+1K4JWkThiLh9WlHMd3YfANHBPnf+imIQZm0bk8SniIn386MI5OOzHz4\nE4NRinoFBZ2QveSs8W7mDkgRcm6PoFPVY3QRUGVKM/cdavafi55CMHzsrvtIU+GTn9VIn3xNt55T\nvun82PwGiZ2FiwhlNlG8Wy4O+LFNA76IijNkkamPOoINY3NpvBlYJ4sMSw1dZ/S+Qd509gN+YqK/\njuugLi10dq5ezC717GDkCW4fL6XMF1BLctfTjFHbDnQePKJIiB57aUuvbzah60QCKQnwYsO2mNs3\nlX8Tl9YL68F88dwoxH0JclrQ/K+4uYuofKZNpcUqyesWLZ7Ajkjo1V/LWCNdqLb7jaE2Z0v+PGsJ\nbQ2zY2rbw1xVbkOFkWnJb00IZlS5AfKLW2JwtTjSc9R5cytj7Kj8rVyPRdWixjwHVXwb9oIhCtsZ\nr9zdlcsnNvnrEk8HWDJmg9t+Ss3qdeobuZBvC1qVhW9OeCSeLWFmmlBTM7zlf4bIM7BPobwINrOH\na+x81+t4Xk/8bAWK5b1pfO/q6usi0t9Z1NTJb3ix47MRkhAbStRfFBfBwzDQr/YBXixPzFiRd7RK\nKHM5pI4NGo4x/1eUa3I9iGFb0JwOlvTvmyLF4CY35sdztuKueaGq0YUi4X3SbBVUihPbcPvhcn3q\nULcb1JlytkOdtyHtyrm7/EOiSLmMn3uCPXQDioYj1f6NsIRA8BV+t4V5VK8a2hNJ+Ci6U9tBmG7R\n2AfVDNWXakk0eYIUYcZuIPVd4sH7Be8PANt6YH+bxeZtBfUel13RoATsMc/l+Vz7BvaZ9ZhPoxu0\nMpG5BKJTAuGZ3OqNXDuuvsvuBv8s5hC8JKvLoL76k+rFk8PlyNwEnYoc7nFhCrqDHeOr/8E3maxP\nPv/AiEhEzjU5PQBF457AHnjeQ3eTwpDPSnYJ6nuR0WhnaxbVcRDXmfQc5Pm+RgJOQXySVRlfAtO/\nJmM8oWf9Wd57qYf2P95KvohDPW6vlFW5UOuYJRNedw/Vofmtj6gUXmSUtZzX9x+pGUbZK1L7qaRH\n4Bl+RKLFFF3ULv72pe+uhZoyumhCUE9nTUfh/0bbyfQ0/7E4OjNceJy3IuQXZAelpm4/lyIClM6a\nbcA7XaiUNtUxRgOk+Gm4bXDK/lbpfHAo3ZLrOeIIrJSFdGgfIjMAMcPO2agXDXysM9w0LXX4XzKa\nAk5Ctu+YxqwaE3xbxVfqa3Xiwxzu9RezCh2I21Ysg1ckJugmX+s7525qUeaUizKlxcu5ef5xX40W\nh5pW3QA7UPCugDISw+aX406IO2drov2E5eUNDLRRG/nY7aG606JFGCFgUNVLl22BloATVP6ZeMDr\nmifoHBORyaJvgAndCrygYyJGcy9labne+Cqn0A1qtn323sFNB43FEMX42WIgtgc4oPab1AYsEQum\ns46nWTCUaZAyRO+53Dzben+MOJEy1iKP7o1PMZDKjaQ4Atrpot1Ix9OivbbWL8nNOjFG3rRgc8Tf\nLOVtiwqq/r+IiSB/HQOV/ZHmkDTL9dtw3UFvBE6wRo6XaWDbKDi/T7PaYAC3GGNaQZw3CTXVFb6P\nSvTMYdICAhD7YCZDr6aVLiD1Mgc225aXecHZoluSWOck9HO5ezjlCFCPDSTSj5OnC9v9zUcFbNOa\nri/TT7JdgqdBMKQjvpVrljLeuPPWvSxLMEar6iv8iFwj9w4fIGsSX5D1h0fx53Dosj7c99OjPOKJ\n43ciuUlKmUrl8zGTv1bTsvgQBspvbQjDlKlZcFGKkJ5y+h+FKT7sLG0T7X0OsNyJhlkV8Oh1B7s0\nnzc4JG92kvRVvDmVljLF5q7kSbo4pOg+r9MMh209JANj1imzsRTwNlFhL4KQmOy32YKv975WzfpE\n5gOHTY5gj/9beHVy72SphX1PvZ/GvMrFHu0Q1SdMOxiDJO/8Vv+UogST5Z+pm6YS50RKp917SJLr\npQGNrqMBt2q0TjdKoF10330Oq2OQnGbPQBcF5wAOKor3lUhuKlgi4yfTsE7g0RlphaWiUi0kfQnJ\nxJaR/v3zWkal8YKuqBUOk2zAI58JgLOCGfkeP4lLDigas6lR86dIFm2ehEwWiuUxA0rMWk7MxUFq\nIvlNP2JTSuRX5d7mSS5TdZoich5Z28tzuAxtmfX/HVgsAiDJsXeq2lNJnPI4t7OJcjw+/LTBFn4u\nGkaeVQKsrDg0XjypHHAcx3Htai3F8S3SrSZThLhmNA0UuPAVwrWM/YxdRJdPCFxRV9DIfFLc78ED\nrxRf+2hm2iIX0v9lJubvukxj3RKg3bWedHf9X7fBwzCzmT3xpSVT/orUQHTM7BJi1uX619EAPHfH\nEslFnO9xBhBE/NfxEOIr6puKJWQy0vcdu3KHp/98gdYKgnVg5mCXI4uGSJL+j3Mo34LyWj6jofG1\nRpvUjZOY2WsTY2U7akBl0Uyiv66vuAVFTYtHxbLeKihdYSSxteod2tWquqRvLeBirXL2qi69vijg\n+WXGPNEs1ioW+W6cjl9Kt1V92qIp1LbqTEC9jDdj5VHq36eM3zGGY1FX+VH47w4FoxWcrGaGXkXO\nhGXHGyLwe6ssZ273qYR1N0RhvtgHnAdUHIPdsqqRbjeld0f7uZDVEUjGCA5HvEPmaA4qaz1HEmEX\nMSbcEbGOwM4/lsTSso35cqWlqf9VepPPahniUNw1bY7j79iM/o0F8kJkfL5NumCR5VM7RsWuHT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C99kqfj/UVOTB5eheZdHy7EcqBeNR/+6GsibmPncbobTk24qcaqVJt3wgZyWp0s45X+9wMv8\naq7nxbvk+JD5cuPi785YB4Is1gg85t6bvpA9Qfzb3O9Wk32ecemuYY7hfv+wXPcCciMC61K8t1VJ\nDxofEz9Nxh0L6M2gdZhrIeECMYqp9YunMryNLeqc7YQLvKIjonC1l4sbrYWZ+Vr/tRAksYUVxldM\nWs7rdbIReyHwkW9Q3eVk5tGNZYwsTJZ3LLHqX4k4QW4fN5SrXF7tpu0Nh6B20X5kbA57dL9bI0Mg\ngdCKLlB0s2kqOmSFFGQ2qiGM4gLCtJKTcJvH0QXyq3PoTYgnvqWXAi7962ulHUUvjiqAbTLGRYQR\ngd6pRfridQ9QkVVZ3q8/Wwg9RSEsbZuIJ9bsY3KxRk+Bv/QJmfbw9otM2ufRS79SLoJDUzayREpA\nzPDRjhDoGxRqrI6rV3uPDIkmG/IgiRjrOM3CMltuf+l5zCRv72lm/BooJKYufHaSMAUyCUXJp/Uc\nFu0s9YVH+QVUDZtdn/t+XoUZ1zviEEgoAEoY2VYry4fCJ8DYaSDlP46tShiJjQrOJdERGgL/xQBx\nO6uzJrNrt7Cf6kh0YFyp6QRAfTkuf7kwETESQMUFV2MR8wr0hZHmd/UBOQiPTPb8DscsuSAYh8Zc\nrknuK0zKex9YiHkZeDo7D/PSeuh+WG2d2zJdkM3Td3eMS6WVDFMFl2b5W8/jYjNABrnjK1XwThFh\nYLnSLJi/Op7SthgN17FwYwSwj+AcsR63hVzcnfiVu3ZUXHEZJEyz2HWtWt0RLaZ7MNZccAta93yH\ngOMoJdpfeYUKCCFDGcTyJlFegiSY/R9BWXq/NR5ouF0kpaoEUa+kWjoHoOiSEaQs4XEhSuNjRynD\nrVhVZzcmzBTJAU/E9/o/Hq/uvAStcm39QbP3OeAuNYGNe3sCFCFik9NxiyTW3OEmJSjBcrOnO+Qw\nx7FcS9UJ/wQfURM4P12Z7osL0N6s5Am8NipjMtQyeAtwOcmnJoNC+0+NUiyPWlCuXP/3Z4arSgFa\nZR7xsOv//tsF4wlUna5iH3TC56YNk8nUsFEw6Ge6ZSuhEVsfIeY4wG2IxxjFm7GLEm+Qi2fnWvFp\nirwOxF+K+U92WcMWV9jGmnuJKdDgr9f0rTsSnyJoE6abD5qCwAUSiMOFTLyqf0omOu5SrdwPvxDF\ndftrQ5R+oqkHgkZje/QojcIA5MmPjkCLRdKv8Qe8et8c4lmY6vRi/j86jriaKSwx4Y+Mw85SnPR2\n2j1hg4L1bm3Y95mODLr49QGkDVB7kvY4Qy33Bsp2CTuOWo05KgZSEEXL/7U+fWGzRHjASwfcbgCg\niVFHnASo+4H+F8SItbh9vW9aZB7dvzb/sp41V3sOiSQ/lvFv36hNky3d5TPRgeWxk7ahEnAeBvcU\nN36JNzslIJ0QcFbUJcrGjbreKWGwtRudHbvZZiy3VBuJefbL+K/nA5GKYex5vaF8VvW2JtNaz6nG\nO2mf0K1OaIC26ble9NY9pYrqytCcdTpOisFBK/sWMwJTDavyPDcaK3b2r0z6l8yWe/+kZORkwM1n\n+vS+mBxXx0tf6GtBwKVn9Wq5PBEpboQb7z+jnDgqEVQGEQk44+zDxF6mTiYHaVCLhGP1x2L8Qxtw\nPkf1ixuZGNM5w3J6JjwoYA1WqjGzNXQ/2I4IFQ7+zOL2BVVm8a+5aGNvBOtcu4B12kHIJpqjtEJq\n3tU1eussVADMAsGVV8uDeYtJPvulbF/idSwsgG8crk6BAOKJo99VQxAzmHr6hzse35prsun1dsY+\ntbANM8RyL4weuRCRdH+gaMfEFjRTXyRtKzs19VCSRxpLGUewvAFPajZ9ighUQ2DOA7Kr/rcMTxxd\nrh6hpvfsAFBAQjLiKMsH8ZMXPqNGDBjA8s7TGxd1KmM66Kj1RfzFBtlBuz9LglC/dRn/arEJkYKW\ngOxCUP9SwP1tqpMfyCFKkHci/RYZqmjbNlLH12cl5zMhmsQpiIcZXYfQL8enrVutyHkc8Oplycxn\njTecEx2W4yyRww+b9SpNrQwNcQAZHfUmu5afg1rtbUHZmBW//Afpurxew4MlsTVbE/q+GW4sYS08\n5hT4/ITaA2T979WNydM1h2SItDPecKYro2NCBuNGPCj2smuGGwIqTTedt7kY0lTXqc1QprlIXDOv\n7A/WEW6Ks/DyDbzo5ebBQ9k/Or/ERzVfh5qWgkq8yG0qonueIlbVexyJM/7sKO/BjOR3x/FKDD5A\nPOch29mk1tOqyzjUVo2fdU4B2P5yIWUu4LyA1+iW0TzGEcAlb+9A3LJHWtdxf5XRYSDst39xRNq/\njlN38Ihbn61REmPKmA+LoB8LUMaREXZsyBT2mkJjbCqOmNANgzEAOIj9ceuS25Y2KtrSdejGBdIE\nvCBEfvsJHNzt4EujHKaeJh7o4NDjqLcdEp7ed4Ep3cSOHMCOA874EICbE2zaW5mDE8TG62+kJMaF\nV28mlwI5fMFxipXSTKgVDY4Vj5EWSGuC9St7IfruwsQ039cqwvbAOIuBDwEDSJc6lCmXs/qZhmZt\nnFv7j6yW+vhyh9F/M49mYXMIrZDI2IQn1meVK5DQbu4ISFnSDGJl+UGx+F0w292X7x/NZlrDFxjU\n8F8hH3SoFUjtp3cdqR6J0qgyyvNuJIK0pC2nq9IzjvH1k+PjKgFH3e23kG7suulbVb/rfU+4p0A0\nUw/8qfFdt9ZBcVINnpEPSUJScU20uwWwAzXtPblYceO4Nbetd/Rru6gMmzl4QBV6dHDFv9Llj35m\nrcJlg8L6gZdUkbc5dWUef9LywyJ3ifFwzOukFPVGj0p1G9hRSiNUqdgpYFlexuLPL30vERjJltwu\nf4LrTIZ2VSuuoDz3yvK7YYnre2MTp1IvJIRPF0FnWr5WUuDhARBzNlManehpegpS4ik+5bBOARnk\n2ikf25Ea+euX4IRwUJwiPzAGTUbPzL3cODFaJ4mHcPv972AeFd1T3djc/nkOpMRfzLbUHz1h++GZ\nfguK3eWFxgEnwvmTBOSV/2pqlydJB+j2kzDoBOhHJ7yMYPINzLTm+GvY8+PE6TGpMumpLB79DVsR\nwtH293Qaqs60uwABd29zk+xMrOUEivDU8FIBU3QFpa33/+/A4nI1MVfVSHknip/yEcpuNY2qPJsT\nYuN68cBSWDFeSQJE5yXwjpRVFkSAHd8nML/bKhBZiplgzijzI6AXJOmkqclzuE3gbvl06XzNvh5g\niwbchkuC2q85hHpT3w63G6WwlR9OlnKpzSBsWJI5MiFvl09L3irrYtbw529xtermE/blvOxQYxuJ\nA3+cCbwrhbuASE/lxx/+CQSXsAGEFsG+rJZf02gTem+flBUQWxgYw7USLAXlR/yGYO6KKUiU5mYp\nMcLp5SF0ptsnO4GjOAmsRzhq+nFaThfDeXAXowTEeuWN+d56AInospMZc/eW0bFPTbgOjid6z1Vd\n+9+s7tiYNg6b6j0iAwEiBa8LX50Gz1E8B8Xk0bA4iCfVG+pXzxngp/ZgDAxA6x4B4xS8JSzvBqG9\n3fF/tpaS1x0ZYZNKrC0vl9eX2oeN5I3CbgEuLOUU1xIlzEYHqt8Ta5ZEnYRUtbhiunpXdVyqirCN\n2dgXkldd9U31gMhMY7qFkzBGBtdUApeaRyAGLxKnyg+nwnmirKX9Y3rBKSd6L+R5qhO6n0UbbSzD\n+4en4Cmiy/ti0HItxFAe4vWNWKSwEzlKaZ2HLEPHIUlwN4xiAAyIeXLQP3SyqcvdMzkhMFVdQYhH\nM2F1yAOo3G/JqR2EjrPkiLCy80ya2Cey9fh2IrTFABUwl8LswS7gb3noQTWyDJTWhVsMOvXawU6k\n9W4Jitv0d/+g4QNb1K05p1NtcnLpsIbcTsGei35vIairYz2Wpukkc+QIjcnbRoRYwr386Jd+y7da\n3/zxTz0ylTc2RMTh2TEZRm4kwoCvMb5bRjiCs5p4VDLdB5NKcfMPq/J+LOvbN9BdKd2e8etvM1x9\nZ83qLpzhi7vatfxsU6M1tYzeP0N1fDEQPFerPkzA/sJJfcYa5H+94+uMTRANw63xIlLDhmnCm9fB\nvFsT1znWi0KNE5YxMVAP5Nj3aNk30viM/aEGcXN1+348mdh8cJXP6Se0n9M2ShPtIh6uOzHcNN4F\nXvgZxyI06BOFPCh6pPn8pM/4wkj6M+5Q3d37NGdAT8T8ei4zfuLUhoasw2cJjrdrZ3LNelT1XVzr\ngtfkU+onSthCPR4WS6Xrw7Ok/kkEQoYmkdI7UB9unluvVVQ764ldp5OlFSL6uGJlq53fikq1mMPd\nHtYt08ogxQnb+cC85LdLrpUdkov30YC0DE++eB3VOpsBoGUdgSzOw4L/wn+VuAsCWq5ABwRe4fqT\no7SyMEpq1RX0wDx7yvM1IrLxDdnN/w9pE9XQ1ww/ANlsQf3806Yc1bxBlnH0iwF7F5dr6ExWX02C\nm4GMD+POG+syw7glXgXQ0OUc8vp22qMR4sD57/Oul0voKncx2id8UccXB9vsMZIBhX8NK9iQyJK7\nYG53Y6spKPwBaJ+D6oCzIRdMrl47suvOHOFMlq9EgcKZSM8cW1EeM34Q9wneG+hmi1jxmgRg05WA\nNvs9ns0cBAUoExbeKaTDf+UdQg8kQpTj787x73pVcySGZAe6vE/iMHRuSiZo8GQ7v7UaVF9ntzDG\nTtrPWvFHyuV/SDdzax+LPSONzmqYuZtNNGc7rSFNjipVg81YgVclfSx1PGAIfydo7Z24e3Gz6NIU\nMwj2TtlQKBbeM3mx05abZdGgKr2KZg/G7mtpHcWqPBAwGoOynrpV4ZdlOI7jP3SkujjjiUQJ8FdQ\n9dU1KADRL9hr5MOS92p0+2CDZXdgK1l4EzeYC6fuN9IyAXHsqWhfswpOubjlkJfdxHP/GX3hjyHO\nUvlaWBcZDw7BAWM+AX28BwSssw+yc8sPIxzjHKVjNVz51Vpi6eQgVAZfgVeW/CVd4po9zDauDBPe\nLW3Ffrt6P9FU45qwQ7MWE7oZ3zsTc0evg2krhbb9dLqiCoz6VuCkphBd+BhX2nSPTl+BrGC3EtT8\naS6sDKIiJlBJL+8+GJ5RSEQoTGfqIs6ND98n26dELJI8S0uXSltTPxBhra5yloAd2F4/mmmPjyWr\nTQxaz9QC3JZaY5ciYNddoc6aIflLXGP2kZlT/V1zu+CW+BExE9WpMnVToGI8RRt4jv0a874Y0An6\nHhiPkeDYN6VUowNBrQ5rQnTkFaMpJk4oWUQE3v6avp7Y5alYEE4wCED+ItD2AgaKwC/nFgLMfAnZ\nktUhijy2X1yEewInb5S1xc28GWJeUEjeegaSJijHmFVUCwrnggKTZlbyJ2a2ezSse3QS7DNzMLsw\ns3lvV7VDvQazHXN8RAgvOB0B/CgfYjwZQnyysjBMCOEXr9ltmJw3ogG/vxGHBu667EeL5qOCFKZS\nK2yY/1setEN3lBeyWFiOt84crc97yyhIN9WLadvrh/f0YfzTa8/jZpqi6C6YM8s4vbQgQayL34x2\n47QkQV/JCgk47e027m4LJl2YsaOwIdm0CLnMgOgEGQPFdyZktwDaQcho9eG3wdeeDVrkyzQormhu\n9aXm2HxMwA7LFBoLoLMTe/h9G0EmWJjSZJbpYBym7mGdw7mGASxg/8DfPNQ061R+2X3xcnmG+cIO\nvl0+UTTis+WrgnTXMMvcqbanhkRzuTaNKehiSLRg6bGYM0soIp56mfxn+lCOLxRvrFVCb4SESUTQ\nh41pLzHt1noaHrzs6Gg5F6h/f/xdaHC5qixpm+GAiRp0dMj0xX0roGySULb0Pg5Ik9k6Txub6XiO\nZgO5zmj4Zg5w8I0AnXTXRWRQrHzuRzUxeqeeMsb/JspTSY5oZj06H3vlmxUcBhypLvXrMLcXh/Ls\nc3bNxQvpWzLBqqdhy2tGJ8fAWkun0YPhNwlUU8lBB4Gk06kgUQm222XRVdAheeWAjR8NbiAop06S\n8Wy+XiAj+daeCKkiouMukARqbllP0jcynVe076LG+ZgkcNqoPU37HDyH9n2pGf6ZkAQuwFeIbkSF\nPg4iQ36vkP+KaDnRItQq5Ii+DKzEOXGkFXjeyB2kGs1noDV9eD6DHXsQa0azeB+0c9fKSA7nV4Mx\n1BtiwRMnJT7JPQOciedKCuaoP0Aq+hvnG6MBlo+nAOOlQfvZ8qQxlg0laf4f6XLVWOpAeGt6y0pr\nAw0YlMDiAyvjsrh3t8P4eyWaZSoFPRIJLol9+5QCyrLlm2aVeoMUtwJ1/53pTKnTEHcZIZfi1n7e\npjP+HdzVIccamu4mef1McNibQT4nUfu60LdH+ZQICzwZKDu6slLfWc1KaTXs71UCJzmFmBNREiS2\nXy7c04shnL9MVkGQUM4rVvlqeU7hjpj2FNlt0nq2A7NHDHkEArM25UeIzO+An0jC3tn+qfMDBZmx\npl24RVKkzC2NhWcwhhc3TGrk1gzXt5aE3zkSTGv9pEL/s8V0XrlWQBLq2XFeBXgLpSAzseg2st1r\n71IH25LcYi65u03YZ8TaQSNK5ZQxrVBVO+JVdqF5H+UcYmJxyBsmvTOso+y/z+nGXXnu6Wxeb2K3\nPMCSNT7G7TIbSFmkl2cSMzEeMwmt7AyMdckkJzv6cvcC0j0fLIcJ+ygBucF6mrNY7OMFKMatX0PI\n4UdpryZPtTB7sdMGLH8FqHkw0PoHM+53+V3rRDIo+ImSU7g97SHk4uMmW9/lU3+h4QEVhf1SsCoH\nD9SCjVbJmWSx+5ck3SWahLdUTGE0c66fdQ50VOj3xxA9nvsgL6x8+drW1LZr6SHG4Ma07PvqbId/\ncOHrnVi5FevEja28niNJV/635eMPcCA8uWcnSyTm1J3Fe+CyROmWWUPs1QOJLqlM/Ai2tsSCIaui\nrBVtakmXqv0aMhA33NdtZu3vrog0aJfleoLXQUuDYIGcGc8kfavMyQBG72eZnrVz6/tupr3lLY4Q\nxVGFP4Jxgxq1oFD+d8nf2DrnUh9AyNvtyyOCKi7z+ReLuwDg4jFzd3U9eZQ7WTDxuOYKmerT5+UO\nG4qs6dNLomx30eVvW25a2Z2qtWBywQq/MaVipSr2RmdVavfkdvSb4lRU8c/OXc2j2EjLF9uwD9ij\nR+SremaAbHZZKoNbBX79rPCGwHPTuu2e/3veCG7t4yv5s3WUvVkFPocYD2rO92YBt3DE5NjJ8kgM\nBCj48v+cPe2x069u+Nco6d7scSnHpPHHPSM+6Py5/LgYVagzcTfjK8PlJARVcAMsLJiBvfzpO+zb\na4Rs26CnEdvlCgaKBV1YLeJ2dXWhGAXTQg7SIPEe+qxZanakqfbbb2xT8QLylB2wpP6fAVc2MhM7\n8GAoec89XNo9PAPakTkcl0WxeigJFRkS527gXqWbZigV+8fVkzfLL8ARih7A5Y8faOuGrHTI1D3/\nzLMHy7/g+ESSQUAfGIeRgrKCYK7EMouPFRuxC5uxAYpm5W/pKsdIPrBHWTqvC0PZClvqzFXBi97p\n9keo4Q8i5+/jCqoMSKdh43uf/t7GW8Dcg5wWxhGnjWC7PMUgwEzMeruqNa0zB76K0zeUaOmh69WT\nQE+NgpCq0rrPFoR4W/hxQ5lqPWMYVQs08oixXrdi4qxOlpMbrxoLJ9dbreMCg21g+h8idnl0Tl1L\ntZ5uVIyA0sfNcXr37h71rInz9wjZ2D+cn1MJf9A+S9uhwm3BGTz/4NlrrXLFirxI7VfKkYEQ5kS9\nUmJtizU6dQ6Ehg6JDdHxuh5l52FvU7VuMVMozDJdJMvbkeQHAh3I0RSRxjaUk9t20AqO38NUWado\ngkUnSoEZCLnKpWk0YPx/LgMwFeFUGPMwCcZ+o4LM/G/XVGe5eO/pecve0eHmEnfeVBoIeGUVNgM+\np5FXp1hflAYwWYzb3FqUrZM6TMi1jBAtwoA8RkCsrYN61H3rOO2e29xzDffAshtKB1dXBUfI0Zxp\nVN8o0s2S0sIOL0Z6Y2+38Wn6hSTm9pUH+2vQjPt5mmWo7cg22+s7MbGkZISOJNCM1mCrD3s08ZAJ\nwSe0IXxQ9GoXKl71fWfyxDOEN80E97kYHfLwT/anINNK4DYOqinZPKwL6lPcmfztT/jkkYeC47vc\n2LKundEqdpIO8cT/NlrAVtDH6t3Fm9VABN/HIsAxIiNvOpHUSrLSF1keYvjZzNPJ5FRQgPns+eTv\nGP8JvC15MCNYsPYO03i0V8tim0p2g1ZGaidN0DRZ+8QURKlhGPX747Npc+Sns6GK2hOpqQs5xmC/\nkg05svfxeKyBc+mnkDT3BuW6tl06gkPpjvfgTxknS3UtGnjHnLRzXmIjQMl2IQ0m0gzzccVzi/72\niZtemsxeuumi+UP3MrCWaN+wN9xfBDV49pifJbqDeSGoznX/Zcb2XT9kvtBFWMmlBG27ZlbXviyw\nPnR21Qdpe9Ga3f0oQjJGGlKrEtk8kpZXg8bTyYQAlP0cxQpKZU2EjD5JPPrHfj1jG8shz+Fu/9Ho\nMoczpTM2n3rQNUp7R8v0cHO6ikm9/A1cUv3WjysTiu7SuCs4gBkotSNY2Xk68SXZWzYgFxmK8HXy\ntx9sdKEH13yEbULEXA+4COwl/PywoPj/Nl+Ew4Pwcm3TnoqS0GSPt7HJPOo2hoOxxqB08tPM+X0t\nB9E3nmeN6WGtdPk5mkipZRl6B32i/Zgg+ya/eRdCQdf9fg9Wyl1aioGzWlZgA8sH0At8Y7gl7NYv\nGsBJKYY9eIu3oVdG89uBhlUj0AOPcTOGIyt2OwESMxURJPXjak9Yh0eSBLOasPf3rxt91kWGROIx\njBiT8eMt0OnS2yu5HO2Eg40cmIqsC2vwtJoj9wOdu3zeceXfhMsdMoEsk85U9XUNedzDXBDY+d/K\ni529zO4iKsBwTRgnL3+Qq6lgmFdlFvr4PT7x/PusFTxAe30moNx7vtlthoDXjY69raOtJEVg3oac\nlEa+QrsLiy6szONetja8Xwm35OWq22kBLLd/fhaSvhSgxFNpHlINTa+dJ4OHbZshSM479f3oy6Gw\n36CHvvAUHpTmQiWWOqNmmUHHHnMRxvyySNkV7J8hlPk547mUpXPDCAheNrbQCq7Zg9QcaiQWd9qJ\ngnrFkLP+BjGxkvJwrV+1jUS4ymZ8io4U0EOc64Tuk3B2OXy4e8bHbNs90VoNbogNJ2JBBrluJx1L\nQ4+/oI2p1bd9BrWyi9lb2v+KL4o85RzAFnSU5vGSjrIx3lm/ZH/QN8/90o4qJsXwnwzwywuIEieB\nDYWlvqUtcnk46xKGSj9rr/PSTZBd7gFkW0W3nLbd5MKKjVDxtdiKjSV30e6iwgDQZ5rKvLaEPVul\npiJd8wgHGnnZRT6oMODzea5SMDG1Mx/Uu8SQZWcFTOb11D7MmcZD74Dh6kGsUS+qfY/P6LK5ZyoN\nHNMkZtEiQINbI3DG2LexnjcnXgKqZm2ZXGavRz/1f3A+4d4Rw6KoWfXIZOVUdNn/l4FxU3xw44SI\noKl1tT8NUagrB/gafvUWFBenLnxPxW0TaqMp+/lnAdDvwHLTwf2p56K21HxTlxXAb2QmgQlZB6bU\nDuYRjWtw96PcNIcEhaffTdNRFC37g/+Rw8qIWX4+euwL7s7q0kxKR4/TG/OfLrnBR/5+jgJGxj+u\ndtyDwjwrtChjTru6KPXODLvAm97PhZ8NRtb2Yzn5a9LjbWYSBpxjf4eyfAdYjEw9yPbjJpi9AJAW\nmwhWv/9b5rkxkeCEr4yQ7tXZTLx9l9hQktow08Zlh6pE4/8M86ah/0BFrTA8TwV1MQM9W2oncjGH\n+9q2b04TNO3wbncrECEi4DtBvtfYup7Ewyn3GlaO5eYLTg2/jiNmLP8fy893XZvRFmwsQRwnyXCo\n2nYZv3H6iAokmm54kiA8wDeKeZH5bMVRb8coUhzn+OdVrFqyf8myg0lyTJzy+bzzY4Pah1/xh3/L\nbI1bdfdg2OoVS3n1aXMOJQSoBQzk8F4lkSgV14x0kEgcg+6I2cD6IG6bQHCLflY17NMmKnX7MQeQ\n9ARoZL9Ftb6h6jt+Yj9TqigvDbbli6iYyt/3iLvMaE7nKbkI+BcyGR8FeD5rz5Sukk8W6WTDkgsD\nYzu0DTmAkRvyAwCKiwy6bzCh4dzKWJOK4GMV+psXZepr0io43Re5pRIkbdTsNzCzimW21WR9ePZ8\noWGZGUVoCCHkoM+VhFyZgrFBCuEGtlTrL1OhJnn8G/vmj6GzP7ppzjqtQOJdd1NT3mIJtM2MU2jK\nSJ1bL9b1YgSVmGnENvIHBs2oDoiFeYB/AdsDKbam8Ofe08wTbM09FVlDEjl4Kvym/+mlqBqdjB8W\nBTlVuLz1Npwe2Rqin9pAfmf2mro+7Q+P1t2MkMMBq7+mNXk6t7f1EZ9CP//mfVK5vfUlm1bJwc7h\n7zjymmmA2J7MYyTiTZCFm7zKpr2m0yARdirGbh5+XEerjM0JG1JFcunC/BfW4EJW+aPNSQhpCcmS\ntpvSqc1TiSkWDACL+Kld4mtOaUOVAjJ4IPoOKrJtnDz5EYLStpqmXsohKLCt+sy9YZ7t7NEdk0SI\n+i8nrAQsijEAoguMLC2r4fcfepagdfAzf18AS3Z8t8vItfUFlgvlByAWPD0pAxEeL6gRPo34mHvp\nqtb02SaAbEWUaCCZNhoIT+MAPCCwxxu6OEN9VW7YQw/hmrD4e4GyB19xhrNtuyh4zHoN+FX72opr\nxOkXzzghtXGGsQ2q3/6cNaNiE7P1xigeetIkjYaEOogeiEI0BuF1fbJDaLfReX9e6jXiLvhJ5AQe\ngiPAl3g0FjDUcmDqjRteAhE/PNHfoJUSgu55pPfO0NY2t2Z2Ye8DF9v/uGaVuFA1bhi9O6ZJfE0V\ndCrNoO9JVtPWadZbKqRoRYR64EhOYf8QMWXpQea8J6pNasP5XG62E3mNJmZhsEhO8da14ofQAFnr\nuw1npXWWvVGW2OGong7N2Kwh7SRpeKL+2tVeUM5oyRkkegprU8oY6yDTmkgW4gzR3iUD9r2yEQQR\nEUrnBqjowX6/a2UbkSvengDsfeYrIn57XZhpweU0dH5uBYP5FkquBKbngRzDWRIhRjpZOeNBuquj\nX6fJiQEmJedr3pyKIPHyXEepzbIAgL5Wuhzk/LNljrsUkTz1/vK9wk75QbxTXjCCi0MlhBUnf0Rn\nT9gWptFSKOOspcWHZzz1bR3qAF6yX2iGIpC7CBqaPPjOSnOIr1Qhts3FByUz2W7IrG7VFIApG2Qr\nZEpY3450S8oEjLqImCdG2XYabHF3KyViSlBMveVAn1qZGku+UFjoqKXKLREhng3hLqooi6ugvH3F\nhLD0lteBKSVsoGT5MDZ10f0FHDYuDu8pt7Yx+avdWuF0XQUqscn1y0GeYS5kr86t+F4ToSMW3ovR\nH9BqBMW/e94nritukUh+pUU2ENfgPglvuqcA55FabulEONPo2iV/4CdTcW3iZD/sNsGF1UHqf12a\nGB0N+vCYNuUpx9LspYpJWTeHOQslPRs7vWN8S54MBEJuS2EKLe8/vgESL+G2BnW7yrnXdPGpYRi7\nantqD/KGvHSTv4C2mNcnINFPsx4e4JPlmwJwsIHL8ez4LDfzGkbQo3znuwcl1FgqMpr/rZfAbjGd\nJnMlIYAo47jNmAfLXWB+SdpPEJgdYuuRi2GQKLWkI8JUR+/CMdKDssgcEyaJyvWOzURvv1hQUUs8\nPkMdKt81i7zFYQjiItlszd2C8zczwlH0eWE2I/wYLwBYMkRn868QftUBc7WCXFXvjBndT65IzaLk\ntS+XJHy1Fk4Cnnkwhr5UiOJVKXMm45H5EKxjwXZ8si08tIgWT/TPY7OcTvYc4EdO5sqbIrOIlxcJ\nA9IOjMcJqGbEoWMAtk2ASak4RNiXlg1zb+mt4fLZDqvemjQOEytIdpDjsKXex4b1kwug4wZmGlki\n8NSMfJNHvGf+G1NZ/qm5S3ZV2kDMvsq1CbBFSw/PxZ+mi7bChotalY0y4uMUAOBSP9kunqJAUrMn\nS2uohKVUiU917LWN5sndUR/DPUfV8pwKaCkdxF5wwUhxZriym4suG9nSYCjgTo7RtHPM8zJ6jadr\nTOy4MQeh/41kZsJ/XYpc5ElRTokVajxpABDhLz+d8fs3DQLWhTQ7dAQFzaxKEHPQYD5+qYLkSURA\n9WeBKvZqJTRRibHc4nbOfxRMxaQc+EAAjELMdOKS89L0XejFvCUujsz2fzQBJkpDyfKoXWLRko92\npzHpWTlhRDA9s5b8PX/AR77wA5ArUGNjqLmVzA1pp9zbxZdgpjqCLi9BNmyv/dg2HOuQs4tgw0Wa\nhIkwx7jfZ3N+FEnXqMihEhWujWBIpFVWJJg9UJ8Cj597k6j613fhjn+fQC3KCwnC2yGWi5ohm/8M\nSpdCBPF0n3F7iEKeRYOe9LRZGXKsa7cPF1dK3NOLqS9L8s/I5RGmzzYpuJX9J3AdnFkFX+eNJqg0\nKMrTPSxtaHUEe+by0YZm0zlcR9t+oiatQXde6yVVzmFWgcmsoz/fDx/AOOCTGxthX7cLvkDnRut2\nzdGY+x0SPOUVq9Up20+HVCHHJVdvlDHnRcwiopLP9EVVJJ3+8+zXcRwdR/W0qU3e3tjHMQeLcQKh\nJEXrK+Byiw8OmW0QMfzy1sWD0q0/sbMxlvt4eq0rHv2LvmpDayo5mQXKasNBMKdsSCFzmjkeVXkL\nx6lrIBNQrnRK3F9WHeo1St/Vlx7gKX61STdUZx3s6I2o9Fu5kQ/n87oY5kGnfIYy/Sqe7poccG8s\nnwtvT0W1l8YAgjLp+y4ttwVZN1u2Tib7vNpCGWTeUR4N4HZlfTWLkfxHA9E6qHgLyLhFdQxD5MjF\nzFCW5kFcsPysIWupF6wd+bHTvxMd9+e6km+LqJvwX9TJm0/Tuhv5smOEetrL85LZL4hoOD3gkOD9\nux8mkIV156Zn5qAXgRhGCBzTAoc3gdEEAZuM9CMnvGFt7nYQqUWozJbVNIu84YUuW9UaohW0MdBq\n9OmTNAp1jaYXjqH+ZcW4yCPJEkJKLw97SJqnlj0ts5ypvSx0AsRbwVqIUkBHIRTEuqdwXy7ffZPz\nSuwzY87QGmpoKvLB/NF/8a/XOC/8ekWrTlyNU7kOVZdUUan4xgg+rmtb5dxRQOg2+Cg5yB2KYpFZ\nGLIJEaN5ePx6OuNsKyGAnoL8VB4CVbYL2YhLksaWv9aVH0MSEQBH+d+Hhh/hyb08on14QDQ3IPn5\nPOfH37BX1Kt4ZT9FhH9AqYK9+IYyvlY1QZqMYqku6WF19aB5M1k1mnxoD9qP2OCDsvW0PulTcPwe\nbZWzXBB+yCTURvqwPmCCGg7Botgo7UemIA/YDo6uZQhRsrlLBqrNEpQRRJvwcCZadPmql+bxVLoB\nHRd0slNjme8ocHNUYblDKhFKIO4zGW4vkVS2xu86jFCJP+AUtWtEoBbRuFb6se1EPWSEZccg/tdG\n3S+yZwJXmSQIKiocBNNsoQl0ZuYObaHJFh/ghdUlIm9QpTkoUQwAdD6P2fVXHsUxXitYILj9Eao4\nnl7koAUxv+egJe38T+XzWu3qJvZlze2xvOmAAXEjVQQfE0DmYJfZVFKcDVdg5jYqF8G8FxSmQcxC\ntIn4gkrqg6EV87gisbn7qspi0sacZ6Q/1gQAURtDxooDDK5gsV0NEhI7EyoinLXjZJ9SY84+Bzcw\n+VD19FvREqBGtziYVyJ2+YAO9kUgWbuDuEy3aFnNOeTv9ze33bOAoAhBDtbJ4BJZt+eGcbWYWlP0\npMcWI4mKtcX18daNTCZR+LgCAw6J/bR3KiArm9ML52M7oEzMMSX7skvxyTaIj1zojGgXeZXvki/H\ntGHQauTSObrzhFf+YE5t50078XpPzdQQVhn63OgOKp+6Rie0Q2OZJJP1G9PXiAViKajwJ0U6IoUK\nVG0LJhSYwAOF+ditODWEnyYQJx6u4HFg1/OYPbRRf5SL0HEyB2SOhxzRc+QylENCwbGWxkJ/MjpF\nucxP9yehbXSUmmAXr6u8e0PlT+0MEcL5+hML6XanaR4sMnepTVUB5OQKCOhz5bVdYkfJf/AZhI5u\n1tj4AjxaqRwn5RhHqqcjspa9oAXyD6fTTd6VkJtf79obE2Vn0/CkZx5Gc/vEV6Y/UUsQa0+HNWxC\n0KxJ/LqbD+0Xo9hk30nIOWumBfNHVFNABhSH0FO6hXe1h7DRvhESnhSo7kGWpv0N7/A4SIRMybQt\nC3MeWIdBm09lya/sOlRRHwnjh6BgZeBEtPqYX++mSFDadrZ5912qAYsGsdIFlk7+p6xospuH+IyQ\n1PP4r9wg6I1iF+wSIukIJgfswFgAGBtqgDHhfMaea99tCTbBODCxTlvVOkbfZwEcdfqDQJioj+nY\nkY//DSMVhLeq/3yvLCdiembO06ynPh1byTgwmALsU/RT7uf5DrZBontbQhHqEaFGqtf8irH9r7Cg\nJC23F1/SWnAd16dLnUjiqbXwbIoLMHbD3pnqvbyyqy7FNroWPX4qTHJMm5LbSMWNMGR/l4ucWMxV\nky/QnNMEU4wvxoK1RI+mCtU7cdIjq7I9Jx8vXkCdnLnAXFb9QNHosk8LwZfmibS/xe8bBW7lTtzc\ndbpZwB90QL9ATHHTbwX997qQwU6f8Q6ZjTVx8VzS23VGBt3KmFvGycKB6dmPyzvkFWiQW+Cs8bpN\nvwr1sTQF8HierHVZSIDcGGnQ2RcE9sHY9ywA2gug29YJOrasaChUvfzGHMkvgAeWBLoNN45Ptoq1\nHNYIOiNBDDt8b2NxtHOlftvoV+KQTNTItY8HuSuvucGLRFZ/ijxZMp7Gka8hw0omBjJ3K/Canqk0\np/nI+kfZ/ww8PnWSkJCV3iTei8yb9akSyGPtimN3DRXg+nm9F1vhe6ZjwvfxYdXsR9RM2YFddDJj\nPJ/7sbG2ySqr5AI3utiP/mJsP9zsIUtciEXpzIiY17AGEzEf9WZc01mBXJheccBxjLpk2hOmp7DW\n/bolFGQo1u0HwOCjvUQEN/VnOXBf9dUC8dHNpljvbvcpY97VkVLl1hhLXJ1B6CZ5pcmV49ukA2yP\nHUvkv0kKuJDG2kjj4LUJ5YXaAGBdch2MCw/ET+X9R1Lbz7Tm0oYfP/vj2oQjxfHEux6lD/Urc2oI\n1tAqwKd6r/F2M/RmthYfXTEpVDUbiw91v8Sh4I0wwtXOQr1qrn4qwtP90lOT+tlF2M8TKR+rerOz\n/5Xgv0CCYjY7xCg4tuF//w6fpvgs0Xp8n+/+RRHW9SZuYLcjNkECku4X/bNTWgMoAfJIJLIPFZEg\nKFFHSa7PwlQqsQtO7f3M30QtV+S6oPKAnAqXuAd8gNhhlzMJ4O71NOrGSrsYdqyKFMu1pulAegSk\nQZ+uiKAj5kh/P0Ce6xKJQVPByIdBLuUdKWrNSvLdkjayB5YrzBXr2uR8Z3qtXmVTRrfhblbKcmVx\nbSlQCkpVPIWCxkOIc1vH7QfvkHgkz0Vh1O4Br6JIiEDbSD3WhYk8pT3YrbNfBhL9XWekVTilmC+E\ncoRGgWwOOnLGcaI7bxVfNZzqrCajMQSnYQUipkO9bAkBHiMkdegZfmnOCpQgUhIRZAmdKCA5IYZs\nhcQolXWCTRNRgfH7AkKeeObiP8KDY1vJ1LZx2YPiRrfGHoQeAVKnpo5Q+XF4nsb5FDWlbSF9WK4x\n3r2tGTKoamdzjbn2uks7TO7uFcTC1hsh2iFiECPnECYbt25QcuA6GhkCaQDMVCRlC72dzdy8cM0X\nNLgdEMCfAuh/pfO5Soab4eZFkdYi0lUKw2JYfFUm0MsvAYUhYEY0Hv6jh5aRNCEz+5cuDw7ufd7P\nmvD82HTyuLstpgQVz9MqL2IrFX7zOwsr4Iki/sE9jhAIqK6UNb2lrwHuhRS6OETJDguQycwqveDU\ni5P15/S9l0xzS0bAffASHIiHDS/nna1mXJMzNA92v5SHt6iND+4NgaspRFj5McYl13C+pzciz3D4\nX0zSkKlDQTpJZAjzqyduOgXcU5sROz6raPi+V12shPmKE5aTU+nt5baf0/qBBo47q2UjQMY75tMF\nRVal05IPRf/HOpHBowN7F02gfVE7H44F4ERDK/Hq1xEtrOFK7H2U3ec851+lya2zTCJR/Xcf3VBe\nlxb4RN1NWaePQkEcv/YWnNpQx+wtJntRzhd2+4ZsxawcWl10ffFyNr4ZHupqLvX7v4I/hqx48thY\niV2fchI4tKi54R4OpsCf7NZMQeEvUspEGjrcQxpHVgtMx1vXC3/lApBlX1jOD1aTwr7ThB9FbEPp\nc37PFCi99PpLZuExy4twaIUSOK+4IOfnhrNzP4+bb4TObcMe1gbmAED5+fDlwoMUWWRMMzWsyN/A\n1xIrOrM7zcDWgLZLcIOfS0spfbW4l41PKSCbIcNrB3jFSBrcwm0pQbneAUYkURTiw0Js/NskmPQ1\nqg+UnXhDdicyH0Wfn4tVGjaPXG+qMWBP4Fx3Z4tA7m0jIrR68Ao8aX+cbhBeS0kMS/j246amm0/s\nCXDiO60Fcdr+vOQpO10O+LjBwZ5qsiJnpnjeaJqXT+Et9/jkV5Fjp1xJ3EnlachHDM//79eNvK8/\n/JKOSm4wMLqBigZLP0jzbtnwgaUT77pjjr7T1mI5GQzeY3nuBOxgyscRlg6qA+96hZ+yXXtVArTR\nnf8MO1ycpLPgEkAEsRETTvNnDrfQAd3EFl4I5oisHtpNwuZC9DBflnl5hDZaZW8INJHxcaYffeOA\nI4SZqRyHEDisnaRsUSDIwcwj+tUhOyJyOMFqPYPu3W8unFFJc5VDswkGf2v1azZ9sqH/+QC2r1+q\nvmU/p4fmXXsNumWv6mJCHSInANf3xj65XGYYVUADHApABy4FLykn1IX80gOG/DkB8tArpTRIvOnL\nymsyFKe7bYMu0tUnlo2TPt/h8MeCWZiDdodmrMWa35AxrWLyT0U3n0ZtHC6/Vdt/e3T6oziJ/eVg\nlSZVzkrl/F5IvDwa6bvb6U0s/exSaMcTOHYms2e8B986/g+KZ9CjNQx8CSaf/8NGvuVEXtnONlx3\nLAWQZyLkf9AlRhWJk8otSYNkhQ30sHgRnkTwxaL/hxEClk6MEI+Z5UJt9ycXKODHuULHepLOcPZ6\n14Qufb3ZpVjOTbYmikm1m0IX3bCoKrUhj9oXXboV9woaTYxH8fx08ABGoDz1wA4F8VMn3QUY+F4A\nsb8WtvEmh+XEuRlB1edUNrN8WEkKjj3TwLKejJhrheVTvDZR3LGzRN5p/Fiz3f35bZUALgirF+Xu\npJhpoFYB7CAMH8og/F+Jlma38Ms96J/JN2SLV6bxpjWe5s/aAFb/m5T2WMr6f/Fi+hR3bYw2ANUU\nuDrYb3BZizZl8oAm3Y8N/HtMXtiLLPo1FuXhV/I/dqimr5RkGNYv2vmFyIRzlTWvf1OoQdCpp/8e\njsVRC2nOL5aja1Gbrsb6xLI7v7zOy3OXXnL3A+5G/aRzJIi6OYRIU9iBmF4cPrBOeljwsiThjyIo\nKFFxbCwY3TLsY5DzxbRnwXg5/kBxZOaES7X3X+zHI5eyla9CnQbfH3EUEvY3EV/37+8QTasY1tOI\ny905e4+8SABe51gkubKLjrhy29UKH7O2fYpuytamltn64Cdq4NhqTcnJzHCqZsFlQR2d3NCt85uw\nAMhm34FtpsIt7/67XzcvPhzNtotKCiLKN/Cgm6WqDNXxXQdqWBpk2t0ruAhp3IlUhukD3Wg+LyXf\n/ZO143HqZM09ejrB30WW0BvJbccuf5qb0GgBxnj7M/eDXJJPxea5jNDgIz5AJ0m2xwLDSCHWb2Wv\n2gTrQlIYnhFqNF51eS9oTQcHL1NUd8J5WhoKC/tnFnYhqZPSXTiC1F8H3rMUITUwIwR4Eq5f/SMy\n9vvjUuHFbAre0sYO884yH76/735dC/HbyF81vbM7uEaXpOBXKXUyFJwP5E5GfEcWXmllf5c8aS/0\nX1aavdNjFTbB38PKSNPR7vE4GYr8QZDsjsYzycp5vB/F1X1R55r1oHlKyB4lyggTZMjolN7L0+/K\nh0SaDpL1hBSp0datucCgpkHAK1ECDvvnZz/EYs4aUJdU/3zroy9RYIfB24/4jNs5h5aCBTMkmeiR\nAMIDLVnyEReJ7oVzZ6u1b6EZKmUGyoE/NAWcRmSPjTUJgrzF4ERtajmDO5hzZdyTOkti/h4tFdJl\nsaYMNAKg0w+186Fz7c25LLBkit7BG/wjrAPz2cW6JI3S4ru5pGGi85VQsoeLOW80nnosEnFDip+V\nJ7aDxGq9BSwM50DlrWdIxbvLObiVnLR8Ar9HAyYTzspjd0FPpeLqQVnWy9kn6nIT5CqukkpCwcLo\nSlct2bLxTcQhrwQucx5/LHBYpKkrp7rrzkHZ6P+cTUcLHJNyJPZkZK3heV/f0OcEsM4EKLZpD0g1\nJv8wATCKBeecm7/VqyQllTUUWvP69Owt0G4XzttdIBz8DTPtaI6ts0hlmbOkcDTTvBf5mZ3rNmnw\nlg1mysjyO/US6Fuiq9t9+3Xofstc4bHEm4YBjGCH1IHTDzvQccKfnM/cqleRvo7H5eXiFsZtPp1G\n6GOcsXHa95RzZj79MoKZNjnpEY+t8YauJ+ETl9KG2HPb5yLpP6Q6cV2HTp5GNHhvtcCoWQBAiqHO\nbxr7/HrkWj51SqQJe0KV/R6u46GvpDHfkVkDlouZTZy9uiFGVIo58fKeM3Te6Crcktg/2o5vSjkO\na7Z8yu/uzD4/L9K5yC9W0SCtqS8uulGQZpEHMWNlzCWY+pOvRSTSp73IL0EUO6DI/7fF2UjEWTyP\nl7qk/O9HvnOrrWAV5MLHT2Axk1W7H5akhnhcPAA7Lx/Q/Q5iLoPNHVWxjlvlwLlwWq9OaQICR4jq\nGDNMi14HM8VyANmSUU50AAoSn5ABDzSXJ9eUaJT/oU+O6OyAckpg07u/yYW4BkTMw8xIioyNOSqn\nvyJ7cBAB7X6KOj/KjRLLt2J94Qj6UBECe8x1PJ+/oKc1U5SNGmaDsiJPYE42OuvkHxD9CXzez4zx\nMiigISEAWNHfQrcy73vctjtz9y0ieOjN163Or2pLp5RE+4EnBTO68tZ7DiFsYAvgyApEJfTwTzS/\nH+NfjaRftQPoB23DSbd4otwB9wqCTcgyKeHfwrA2tWNoBnRRDh43MiB/X3InWXASYwMqfd2bTAXB\nO2ZNmuvDjFCqHdc6XOPqtha0OlB3JmvtCjQqmRjfwBDEg9nRrUo5OrhjinJ1ZZwsA6X9Oc2M1jUP\nlgQgjlV0P/hsZqt/GDjLt30k3e6DvQg5Ye+Kvn8MkqXne8Omnj4K3lzvEKXPYgWrAr6+t3IuGKRO\nr/774W4XqSnQXDXYSsPlm5VAGXmAqncVo5ekdQw9di1hmya76/G8VcN4QK0J/Q5c7xhsRvZUhBbD\naoZnX74rF3GIzaxID8PujDrYDMP2QkRZijphPCywc/l0jsldhR2NB4RW/kYPN3uUqK75cVesEaL5\n5v/AR9/c4p8tdoJRCWfRRBN5m9RRDQl3XFMUCUPifDExugkQfos7EIKRGrXely/Hf1bqQd84KBHw\nQgmROHDt2QlItAPE/wtivVzftCklyirO4+OmfkftzxGbX1/QGxAlJyR0gmm6RvKa1YoKUrKgK5S7\nXscl6MYwHWn1FJriTwerIP4mWdDdbOdCyCWKVqrv72q1sgu9Oofps4WpH4Id8HnAUAeoyYdHVdyf\nJnSE8viWhzvF+yf1tjrLZZySiZWT+ad44uIZkAqC4GRPwpOiYMPcB2Wa+1jl9Sjtp6expmx+u/5h\nAqCBE5nVYwwbNJ5/97wkl/T0DZm9KVtrlWoLxqYBUhTAfQ/Vdd5kx3Es/xK0tvL1c62UXivN7/I9\nVqga2Z9NvKTT8owc+ZOI0CANprFE4IK8JbXKrTc2NMiULmEnCU8OGYBYIMnkxGLerH12+A3ChuLx\nHIhcg1avfqvOounj2H362C2fJYDtmMVv5i0y8x0+v2FBjrTzdrisolTypKmUZ2MHXga5ZGY7mXqn\ndgkFBZOS64qYD1nIn48V5Vlsi7LF5aLMCOZWlXOw8WmIF6glbehcEFsPSnmyeQWeFK9duIjIEiYC\n2S0COsdbabYyYPGGFpz+iI9h675DoLj4BC552U1qA3tp95Z5GrD+9NcJQeNA3QjGp8mHde/skpX4\nYkex6WxEDA5ppcdy4YJO/pIrDUz4Y+KJm2AHQ8G/1UYNLy3QQm2xvEdP165sZy/GgTk/MxGtmTrE\nUumAVGVSTzDM3pMWOXMbHsDiCoY+LxKBmOofdTajcbPQor9UnJOOh3bk79plZvZkj/kjgc1ipavu\njT6UFxbm9ghBi9L6eUME4BbN+EiorSLlyWruDKS6fq83mX+4iaCshfP6nQnuTU1728nJ1U7J8h9l\nq+nruftauizB/m2VnGlEUGvC5d/olcqk6pWiMeuemTJM5+/BeAZ82XblX62hnpwo2kJhh0byu56B\npAUGKnLdamBw437+UlRRmPWEp2UG5OrqjLR0JMf02lGeO+AXXllC0ji5T+qUuITeYpHEadr7rg4V\n4vCNuTSmTymv06ja7bmoQR69HQxh8GWBKzTOLLC0knyElBbtUMaLTK8ocsuJxklx/fiJ6dcTfyay\n17QKT9aSN/+h/kzJsmdd/rSI6eJuQzg5lq1pM9nNggWdnDkZteF0Zg9YFqHbGfJMRqZuHxiWWHYf\nhs6BYwa1Si9yITAbky6OYkMYRRXLKB11R+pmRoUoiwr0xLh07t5UF7xEWYTqv+9KueNxtSOeV/+f\nEdo7uzq0Dii7Z8WTX2z7Aga6oO50BUYS7Zu9EQqXr8lj66On35fDlpEVb6h0feMPSn8Z7CCYxZxv\nrrgpc+B2PXhRlSumar1I9au3GrGSzbXaP9tYa1pWTWneUxksfdk/VkDLBuWlUN3jc5hvC0URlDsn\nV9FN14sxPOVWYbJt04oVou/R5XA4BNMUei+KMqaZ9LsMWy3qKESHAs0vomXA0Q1xxXac/zDN7LsB\nRTS+2gszGrNQQd961iFcXZUTQQaittUszpL3Z1wklSTLGQ3Do9eYkpQ4MXTmKjEcUcTkDd/8NA7M\nahK/cQ2y1mYEyJRkYFICvafpDj2h3+Vrzbg9cJ/+E1y9pNY2lS19jiEtaCisx04TRLUodD8TP7UQ\n4/ijc61VHaWa3tTgXuk6D9hD0oCiJOSUItz8iavDq1u7eDRCMKfEuHf2v8Ddhmkd04t2N/NQRTRb\nIoNNHHHBrQ/dszA1gWrgEV1xZ0dKWps4R/gk47Ow72agtIRoPMhVUyWaBgxaaEF9NAB/0Knc79/h\npDrIRM3UDEfbvOJJfBhGpmEXa5waa5PjxFrms+lsyTs58QeBBGPyfXH1r00fkBCCrhrlsM1QQTrU\n048xf/oyN0tUcjE/B1ZIBe410V5kNJfAtxAh2VPfvVbgbecLqGm3bRUljE8ozf1n6ARxD6GASLmc\n3GOh/dMJqp5oJn2sOFwv+B+AYOeGsnY8Qc0sa1DnEwTVUhDCZ2M775dMR3zZGEM/kk1pALwGQ6Im\nCnigap8WJ3+AQ+x5TZJsjWnnsZFbKiAITDP4+5gG9BpBQwVL7bSQYfWAYV+HsZNkpN9DYVKoz2u/\nbNnXohT5+gKpBQYKTg+h6XWaT/lwjspKXQkftnXwIgZC2EoA3j1BVjXTu6ePnVHr0azUwa7rhzUe\nSNoCfmOWeqnZSvRbVB+fRNZRI4hAVPpgptKPpCgL7DekF+8a8+X+Rca6jH9KFM6Vat3qvo4j81hW\nxg4glHb86eHWcUlzAW4wQR/D6gOuwjzvEi1jMpNNzZda2vtnd6b2QWQHKGtf2V3gPQNE7qp0z6tn\n8zMGcmW/WdC4n3Sc9GSGmsVAzNkoJmkCpBSMUwSbM1Tu1dX8eqXtI53zosOPO/buxyAkhN9sXDC/\nt5lVZdFQB3QqqT4xDjY+CwXxguwKeogUHQlcmu2PyndG1/ZlougRvZrmb/Lkw6bwLFHnuYLBZbov\nvAFBpbSKNKvQkZfTSwYiDNvc8BMFjMmjcFamwmizpssKFLlKIIbAUGDo7/9giFPRr+jOsQsmEYM4\nvL/nKadZokw3N0FCPbZNG7oP3I1wFyii7Klje6QNyIu/MqYQmb/XY51Tt3uPm7Xfc3/tNrmlri9s\nqzbMC9eeiwC2HkXHim2p0c4EKVWinPJkmzzHhHD5XqOMojAJPhX+ZblrNiwdx7yZ9FDd+udt11t5\nKBAtGk+DkDqFAWmcK77O05i4wt2nbfCYpoKyN224bqN/dwJBUcvQDeGU7zCkK9cY/M1RyGyOrSBv\nuZdwpqjj52VMyhC4eSw0VKnH/dkjXE6ob2Bu4okt1VlwfosxgTLiKv30Nxqa6xsSgUBdLW76YgRM\nSSxCp+DlI4KsYaCpTLqAkTsNbWs/XXcz+KkpZwGT3Ak7gUk9gWYDThPEGhAMifMZoNiuB/frOteo\nErLJDy9+/CBi+mwbqwhlM1mSLtEL+QjKXQtFXnAoKwlV0A0S3Y1F3eZVIt6N7EGpp+GqKm6pbvJi\n19Uv96Xgojy6KuRIp/r7ylJhgsaZmktjQVHgyTwbhlwc443FUjShzjYUNu1v/lv/ma3v07n/Nu1v\n5Ygxneefjd/BazNEjUTdLMV+xI/8Z5v2ZgRVVM/EjyzoDUtDR+/Fc3MUuqiQt7vYIQ3vJshwAQ7H\nq6dkx314RtY4hRvZUCGU+rnX/qCmenpVXFV2xn6Cc/5OF4EXbr6RN/qhCuiD81yAQd/NbjNEOtMW\nVmqXqTPsOOPY+FHam5EW4IxjWPRsAIX3P6My6Rer1kJd1F5zhDJbArwUbEm54c9GQkVXxhTWYIqF\nvH+Qp0Yy9tyMUnRlASj5jMvgwe3cUuHPxlyPUuZK+rK5ayJVxweBf8s8NsE58TFti+6DGNH+GMoj\niJrcHMl7JIRez9U7WoBdNSTa6Wu4FsIQskSZAPRnqG1YIhSSsLnEaonRZ5jHn6PxFIsGHWLkRRTM\nPYYKNKVMipW3WnaHIgiN57KTb5pXBGnXQxTZWgNJ4Oc1Hb/CLPxx+jpJFEHcrEa1chVQZd0SORaJ\nC0zRLJ3K6naY4bpkuEtRGvqnEiC69i7rkR5IYJVZn4T0L/IaF+HxfL2jZBzUqPiEpBIkGRIoRoal\nnAnVsez+Tf1g3sKGGb8Jc7Bvv9mbKP5r+ciY4SkeEHFCjRtXAHTU2sIxj+cVDrOGcwgj04QZg1CG\nf9j+AucjM1EmfmYfM6GMwlJ+jju7bvRNsowv0BBNlF7J8l98+ikv4vmUYM4WSkRV/jc+XOLWD2y5\nyNpM1OjVk1/KAG/In+VQAh+vgz1+4/xoyotLH/qRGT+bFxn9tomW0+Yzn/gahFC7LGrb3bI0eQTp\nQSejapmUj3nSlxVQ7dpQNZ0NrLwA+G/GycUyauRzRBxKtZMNHDmjfuBZX7Tcy7YiatzCZ6M2eST9\n05E4HperTb/cfGMm16ME0VdyxSZXAmb+OckEFGyGvWLoIVi1AdQUkJAh5rbT1QIkSS95m6iNjS13\ntFc+QIFe0S9X0DKXeRy730ZfGzxDHl3mt004W60VSMKldSaBLcHxxkrXUno6fZskEcRQEFd8weJj\neZkjtL6rtwkKjYV6x+cAqIRIH2CIcwgvi1MM+SbuB7Ej2OHbWGsH+ae6kDWlG5RxNhyL9DD4xcf0\nDdxElbdQ8rphwwoJvoNEe02bsY8iwtjuSyD6Y6clNaL27fwyCzjLujIWDUy4CHvK7Vl7a2PLD+dw\ny3uIbO9kn1IMMIKHSlomNpPap52CEIksHGtfk+4XSYfSkQKKp/kNqVVR1RPQGFToDqSveiV0bWAu\nSEee8c2awA4VDSIte3mzaYqUYDEfpBfjlJ1kfUOttH4qAi0IgL4BL+9FkiKjuwGeHVs7r+v2X30a\ngWOPSwAX10NabuD1IZjK3kIAgJJXnmco2ziHkW63XC2rKj3imToI3yyPwL11wtrAgJETZGrJTxO+\nMfLO+/2U61Knhu2slj+hYdaJqoIn0DCviHnI7DIQ2fAgjjaBl5/Er7USC8yzu0STnipb7cjZiTZP\naakr4i4vGo4b9Bd1itUaJzJtsdWrkVcFA2gSmBCHTYdro1jelehFneB/aDR7mxtnjz4PoHdES47A\nOuvVgKpCzNoMR43wGwKzG0B32o2W4cyo5fewsH6eHMn+T4EedcuHmgurYiN62uO0nz+M7aIaaBjS\nbPAJW3sIHIEEdl1P1Qtj5bpN+FoHJO1S7NGnxpS9OU7QMPd0thdPovlaO1Whwj23a2G2ry9SoW1z\nY5olooVHpgXYzMH7/aKVZy7EIaC6Pq6ILrl+N6Ql3+UuOAhOVuIGmgA3U234T48fYm736NjR5Gul\nrSbC9/WbAzLVLiCWKyxHmQqbSEsaOrjhz+ddTL3rcvzVLwFzhjTqRWQsPbtItebs41tdPf8MvInt\nkHYDIMP1RHhTu/5dAS9h/X3tQYAQgRhCHOAE/4uMtfdvIjgAe8fs2gC8QK99+EappIfJfUkvZKML\nn7JtFbyd4wN7CU5dpNIk8/RsvM3z2u7jtDa1yIZZIHNQfTaJ8WmsrUrjGpbjbT5lPZoMiQt/jblL\nk5uJo5y4kpVNE9Mg+OlMSMqekZyUeFSHuGOBn2smMqko+UVNaCFxXInWjz4TYpqXp288S605F7cL\nLmqsI1yHvV6yXa/8DztLhmbusW0vtxUKU3I2h/KupFTrxLHKOWOrxyix7kJ4L/g8/PutXuU1kAoI\nAu9OkaBF9G4qAHp30Eb2fxolsyRqSg7tDREIfyA6rPwj7+gY9z+2g65bC2+O5XyzC979ETBl5EmI\nPjuXiDRlRRDNtKsOLoz98L/9GAnV0AudrPU+sgVjxwcNfKaRqib2icBzWMIIsL3QLhhQxLI6bZwp\neya26npYMw+VI6+huptBzOaBV//Yonn62HLD3MBmDEsZRbSRiedUiuv7FO2kTlQi66FK9h02Uf30\nzrbGSKr4sRI666hzuzBE11QBkJqOosb4dDlHX01MQSKIc2w5pKvfi1MECCATgZMZ7ilhizyPHPhM\nqYR6erClv/4mrKlfdy/eRyaWBenWkK0J9aQB62+fNvXWRJ3F5SQA4xtCLxOlSKoqQVV+311DUvax\nEm5l0r5y8XMpy8Ig9W/TOidKG2ruNkmtRHwn7fomGNnG+YRWvlHPYkKcrMXXVZYEHhVwrwv0FRdw\nqqilhFaMowQStCU6A/Mch+SK8shJHK11OJnt4E6n7GSS0VWWIoddIm5+RK6+DVbhGIGMWvq2c+/r\nUMAozYzqqMD/iC/ZUuMEFaGnsRaf7fDLta1A7VFGGX1JrfJ84/D89+TUzIoiJt2a+mlOv47F/nIt\nDAgtzOSYGKb1NhXlkc5js+oaoygWm3Nl2B3F52XQd7P+eJfDpWK2TjB4F1BX9GMnOlI5S3kWAp+y\n8m67tK5JQgHqpN0CZ6yLbololzSu4PX3gW8kafdkgnx/s11MMaGgmdlGj2EpOY3RmzfYb0zUcv6x\nrDj6PCQU7tjBx85GxXzUZpzyoW0vswvtkLufpFueFe13Lj/xkjdwrV9ztjg3RmEWpqEDhb/ewj9w\nMDgzH1m5Waee3zV6RsdM8OywzwGB7r3QEi4+TJUT7n93NRH2bl++VBegv12aakTzLHKbSb6HyWdE\nUctb0DJhxi6aBKuzwBDJ8IXilBnK5vb0oGMpyvR0+SIG/WehKC+lUhfpwyKzZ/x+BMz/AakXAFHB\ngprixyoHCJS+IyJRNTufZoRpXGD/NdpZEyuZEAOBoY4iuamF/oaWgXBZgaa0NGa7axmq8VyYXhhS\nXRaEXo0XFlyt34x/Hs3t5P2AwUqFOhBalvgxSFuIdt8s1SfXHA48jwEBSY2mRa/LrKm9DL7CVsfd\nW7AcoaS+xAkMd1ZA7zGD1+xV5kFBSJ+oUm+BHq35pBGjxdwPM4IYx5qL8t5y6LkBzYVXQeXrYz3n\nAPikEn834V2RN3BXwNBi++a9RQG/9kyZFKAgjy/EIEDqsZ2Fz1a5AD+kRnZMq4Gy8FqfvtzaDX51\n/24gW4s+KdESku5GMoJiIdxYoPSC5yYdU6maW2zfvhU7j/VxHIVkEAuL1jggslz7UvWmLvDQSvyg\nAOiGhRngYu4hcVry1NbfF4Y9YOxx5VSFvbZcdVav2L76PYXQvfZa6b5zAj8nMtYby/auDzpCGggX\nIFig1IHnalQgAmlg++abElpqAE9+F7wlpvxSuMr9qjsXMJFa1NLhTAuYn6KSATMLJtmc5ZgFjtV/\nqZI83QMNaqgB/sFXO/zdaW6lc3DKYv0khan0DLyxC9ZYoU56KxHnwcsy316h2kq+KlFI9JUD4R5K\nk+NKgW87SF7e2IsYnl9F4WoeUQ9uu1TrYwvbBQikWhMo5zGJ+jDNnZE0hXYvD7zLnrpjNxk8u1jB\nVI3+wFkgF3y9dft9r//mAputCiFpTIwLsQE06NCVgTlG73PCHAGOQBkEBW1i6c/u8at890aDr9FL\nJulPXrkRHnyQlGS6bml0RA8vNJpoVwFRl2QRt2qUo3qTbXDEV9aj3xXdfeEseUR6MQCshhixhNj0\nKU4YYyNjpsnXLYyHerXk3ioDeukDGLEyA51ZK07Szu2UDcIFqZ+ab2ZHiovr68NcLfw6YE1qkg9c\nYLT5Dk89XCyGIdn3pgnES+Sd0tcg+T5Pp7nx1EigHx3ZihMi8Oxe/D6guDWy5TSL1G0ZaC8BvFYa\nh1C5Pfr43DjEoojJFMUyz4w/w5lCEUBEh6E8gXjAMVjzFAsA7vDjdWz08GsKz+CFWPXVVrVAaIRy\n19k1gGQ1MRtI7CUf1wWh7f416K2hwjHgzz6cmETCt7TexIThgarGxn+VSXO5pr5O1/Fs179fijJE\nLmwfZInZ5GW/PJnyfU80Z3xD7Jf8tA9KEhVmkiNE+SX7QVCho8sBVQhT5B26NKZrKHXkuFWKcBsM\nBhB6mZkvndJIuBm6ALke5fJITcrvcci6rA987B6eGw2NVJK11fP8ugBJBkmiSCxH3U6uXThxgqMz\nPujL2p61OUB/0gPUXs/sr7qt6X9/kYDGwejPI9ievkME+XteHvCyDtPlq/mjoWYawo1wDIP2NnLV\n+0QatxMMZBMlG6naoEf4pifcaMe3CAyIAlbYCkFgKoMf0qVgdHd05KcNusDkLqz+bNqx0PyHucx6\ntQNR+G/WKS4eXcAdwTudTPLXuqY4T5dXr3EU/fhG2oKFgHJRrAIllJQn5it+B1ljBrm8BMXVZC50\nkm/y/Dv2k1RZg83xH6UoGk0OEw29nx+XrBNqjLBViBHSdzLAg7XUs4irDXyfhxGycqBdvG0a98Nk\nxNU46vJazVxZWSL6U6mAe6Sv3Sr9jGmNIgA/VdbNk/SIP/AhthEjNhk/19pheo85ryTp4KL24Vhw\nrSotkbHebmTArYBspDLozvV51DeBkxnLdq1AwEdI+kiwzBbiud1p9rJEfRCLlqRYOI2rNY48L9Lz\nVwjSLp1+SKY7ERb2h+5bygkAImLrivJNuv0yj8p03GAPfu6DwfwlYjr/ZSn5C713pe6Imf5odEyk\n2g27gNss5gKol+0fnIRlZrAdBphbK+HDGns5LVFnXt6nhEEzzrhmhY5q8YS8OBSR09NzveOjphSo\nMFsa7DV6Mx6FidSa3xeL8Kiq98kSg/JzKmT917YSdmFImgN839ZxMPonkiRYfizHC0bcdFfVJC9P\ney50x1ZvNhADKvxaQoVppfhgjgY4RAL3yo8CNeL+8diNOvxxv7VXL6VmkVHb0OPSK9T7jM0UNC7g\nx2kdywCP5JyEAE1ZYgyfhp0cZseW8D3oJ03+f6aWUefyoDW+U7lhbahfjP9EC67VrkOC0aA2r1qb\n0EGdy+Wgbo8LwZqlv+i0kT6JJVzJAs9m9mIkVRdSau7A6EtZ++Gui0K56HTnHxdBZpKPLfaMY/Vq\ncO5ShwiXPBEzE8G5dKmjHC+z12W1EDxgsCLar9+YOAjxKhgHkBGfg69+NmO0ydwiFZtkb9kQn2n2\ncakas/WtmPRcBrFKxTJv7hrqsa0tATeeQxEfLYe4qtlUzpbtLY2FdoNRQlSxUGJ4pGgiCSx+x5ri\n5dbUwJzYin9/1AkNrajyQ1igqFH63Oe5iA05U0OBHL1TZbqVJu91v+1hHGccThB7kV/xn+sWCL0Q\nmMULWQqEWLR9aFsTO9vP+2fvOf6Zwuefn0MzofCFTwq/kYuMgyppHBeqD0San0S3+DlRWFbvQxtd\n/2tSB+nGWbiKevmP/K3gE8oRdXigzg7xbPH+gh2lCC0wJmKwTgQwHIC31x50ZJkg8cci6fVAAw/C\nVHXrDrjZSiroK8utPInMK9UgiLiJZaxnv6VMTQfV26pYRuUPBEPpZ4PLypuOIcDs1tS4X6nUNDU2\nfNyzzsyS7Fs6nTKsfTb13JGw+dOOt4lMUIBEU84U5RQKL+jrymEyKK/sSA4kuQYjQXLCHUIIG8G5\nHUgZ9GKsNo3ugw6mpQdnfJ5cW5I10H8JLWrMiCExw/s1EXPyeM59eTd7T9tDoN1rAZKPHG/JN8dV\nh0oYFXVBv9sIAGpOy1+yMXyrapdwkmnq9M75xOw+4tdRAWNlhGUgeer4qaGwM1AiZOh9ICdC5zLx\nBQ6+b4pwzgxHxvbCVYSY3J/6A1H2OWZ/DJsHbkCJzKyyIJI6c9Sj+iL7IWOEz3kPoTdwojbxnFjE\nFHyzNYqDISswQg6KXYsPWTEGpB/obQREvd+ABflTfjzhr3Tjftzcg8LURNmOgUQANWT1DWQSbC19\nmfeCmEA3Y+mKQXkzlCARoH1uXMPPUpVC1ipWTPqeH7TcwHjaNCNhXgDS/uk2Z5GBD8YiHzSvAuVf\nKZvULyg1j21LI/bSkfQ7+lk8ROtqWPv7/JtmfKo4EJbyI7aQPWjlTqdH9mV0ELtfD7EbTPEhwZZQ\nHGWfHrL778ObaVgVlJ+4cur5V5ysxaYVfZvWa3RzOCv0QqOo2lYVW6b1BV6cZPLYruo7o4VgOq4K\nzMz6Tv5RTu1X/Q0sXm1kmGF9b7w0Pc5x3QBxIGCO+NzcC9HZekrjxRIqqqG9SREDtovJy40tvW9B\nVLyL0e4LS6wq+BG21T5Tm3wStOhCHnyJAneG91iZNFnrTY57YkATwIja/JJiSnDtzisBcdOXsnE+\njF+WIPe/OXaP7EXFwWnvQcMy3CEeH0v9WQ8R0k7m5/5LJUSKZegVF2vImSnXZte3+N1jLmIspK2X\nLSW00mKB9e7X0tmoffFcNa5K91v5qCKZP+jH9FlXfo6FyNfnHZeBtYWE1rFrWkkNoyffdTydMxU3\nHsE7+QvtoAiGifQOxWPvyL6jtcKpDsPkZKwWMaDS6t6CrUW2+7FIzIySi4GPD+UtldMfOgfX/xY4\nRwOLpHM0qz77Vk7F8r5igDm3YdRUclJRj/9p3PhuaGURCCOfvYY/1YtGyn4pRScUV0eI5mWn2HkY\nPB1KwhTPUTGwVWu7Y3fD26njzSehEGb15soneI8/j2u57nBdio7e76zBGd1Ae28DCxlw6eheUL+t\nVfbb+l1BrerQeAHVxnm+duuLE+rNrPfp+17NGTOlB2Qf1rcFqQWYCmgEI+VzyOhWARntifEQ91cL\neG3JS8IW02lPLDfwgGnw1jdsBDrP490+YoZQxAo1kmK8lSjgUXuTchXZtHz6I8/mHaTDsZ3ZJQA3\nNXIjfP4KlMMnUOG5LiaeDZ03uItPx33c7XIlhC8wCHIeOQHEnRoS7Ah4f7M3FP3oommN4YQxreJR\n/uAHpkr0sCdoRVU3J+7N2vwSP685CNjrqyl78reB2aX7Ty3g0hVKTHlyPzRgA62N3Gfb9vMrk+W0\nY78yHpQHiYOQTwAsjZvyYBwT9f/ldXZVwC1YIvI20GQ7kL8uvhV/+zbXVzv6kyjHg6HZIY+D/+rY\n9JnqgDOXkANYZNab/6uv2j1ojjDqBOeZShxkJkbTwoWc1yT8OmnQVIXLmeGTpGuabFKI9Zi6Q/06\n+HPwkG5LawIar0MHYUs4lb8X9uKIVauJZHO3fCfDJpfE7p0weI+DMayYvriGCPSu2+0cO66waMD8\nkoQKpOmFxHOrio+PflCURVPrWAdtiOVWfTKpPdCUgyjcX/0SNGNc+GsKLpPgnseR5baF4rxbWWCj\nkZQJhVLuPemR09jsCHluA70+mz9AXQAg/pa7bfPbMldU69lewVO7xbwqdUDy4hdTZYJCwX9TNp1P\nNpCzdGsgoswj/88Cy3icvq+rPBdxfqogbUZXI0ZcBQuBSscM9RPagLxJRYfOWbvPYakgaarvMURQ\nUKkmvS7oHX3jyOH166f1V6kX7iU1FtSODnMP0RTIiVB1jMY8PPv20LD5653dtu8nhpW/yxdeaulB\n6HrUOModOutJHPogWpEpYquKf+DCjyztBIiWtsXp0rIdpdackzsWc3l3gZdiLtsV1BhLCsj0FJw2\nU26qRLCKKxk0axjYCW1xbCcNn2Ui03uJuYtzjrQJU/ng+M40qPAoIOoonXkN2va+Z/XjAlJvXRLl\npvwhi82zybVUV7GX+GBE0mShC/h7yvkzFiRrRDA/RwRQur+2okCdE6dK8hr1zzFE10JBP0d9TUS0\npK2XqZN2VJ/BQSHEd38SApjeg4BZNbFB4+Qm5v2hy9XGHVWFBr86STemwiPK/HTKyvHbsTG8gt94\n4Y361rCNBFPqISw38qIcz8ooUjFi622Y/CWCjDz21lLX3iFDIFf/ZxxqVSlJM1NoqsTHOTYaVwF7\nhlfj1vG0b3l+cGCZNArEGD9fxGx3Z8OwL7Bzs63ULFNDz9lM2zFr4UU6eL3vuRH3yJfuI3H4I77P\nffLuBWlPBg9kdeOw+bZrrzSRIRmKmYS6kOz3Uyn/i0ejd+TPM5dR+qHmiFt7OZjjSaf6pYIDxuFA\nDZ6PvZDVBcTDMavNkIcSkwsm+B0NwELE2BV7pbI7jpTpkuTQpZAIcuURtrHRXOohYiktQX0f2DId\nGDX2juPGYqAkqHn2O6TuzV+PKfUMTryW3TwkT2rIqBqzrGBtN1hU0JVrCaZAM1J928FQGECowe4C\nYw3phOU/wxWfcpsDd+JjsNmQP1GrNaLeCvX9iiM91ya+u8I0UPBSSpBhbDExnHRQ8x8L+Nxrv2P0\njVZpcPraT1DfqxmICYoVm6AY7rdTgJrjclMbYmafOsUk5wRRTQVAYPBpGcA93u8qLRqEvvDHhnS2\n9RKzGmNUV0hKqNIF4f426z0tJi0IkRW0znccZmt2d8TXKzYkCOfKAliSBqpZS7bodKplqMqc4voE\njaPXEf1vKkbUQOV5HqmvUiJPI5Y7jQrosCCg5VL2/oqN5DodmIqCCTd3vdAm/tt/b0IuI5mRfpP6\nV2Y/cRCrmE+MumRavYpcem+l50tCbeSbglB4grrAtBooNSiWou5vd+6WISoDxewgOeJQGew6HhaX\nO3eGe6KfJ6TaL3fiJuZF3hZ9XXqyDuGrb8nQoAt6dqqzzDpGo1JaPScwI3EIpud4EhFE1Qti5v5a\nV3Vl1+6/UJSBa8V/BrByhZyt7xmrFz+1Bgy6E+Z8DAH3rQXV6mKOieQAoUPkW2mh9tx9xnFpbSsZ\nTPYhbec2cj4bGLI5crXAxEScCC7qH6wD4Zgnd+qNl2NdDJqKJO+4hUlTbuc5wXXvarGBBhgjMHLs\nXGdXVwHOm+Cc8rKXJvr7+5PUUtnwD8gWKxJXPimyS72D9CW6d7dkhkbP7lFlaWAatkkLR5ARwFbx\nMZAF9W53PRE329iWi8zBjf2WDZBSN2Q0TcA10dOE5nbnbfeT01IkqmqARAkQh+nTwL9T3bR2A8Pf\ngmwCqBj1+5rRlYslJ8CZOrLDQgDuLDJ0EbX+JSDcQd6jEyne6hgAaoZs41ByP/8g/PE2alqR1kRZ\nTYhiSUk5FbaPSLijYoL5o1w7Zy0qqdH/p9GBtm4JO9CVzc6hI09H8Uk2lQbJPzvt9YSlv3v92sQz\n2TKxXXtBQ+mUlziFQ/8BYitiRqoE2cdR+mE5f1X1YvM49qIirMbEuumBGiHJqvkqNUZBHU0ZgVKg\nvobG6mF+vwwH28e3no4tQ7zOa/fDVprzZjLGnvdPUjym+XCgbrKyypqUWKJ4/T/4PjaanyzPvvXt\nRlcGp/nhqI4n2u93okHPDK6jV/5phIyTYsLiXu3CKgu+8IRYdXYOiIo/e1Y5WDTKYgQhmBVshF3g\np1hGuj0SPHrrAaGaEG0egjAyMEWxwFicIsMjvHDzms9wj7SGPo6CFt4YMfar870S3Mr4rqPPTLEl\nKaX83QSEnw2lHk1wIWIFRH/7JbyQRSmJQSWe1dyCNY3CJc9ckpBwv+ZE3JjOz/eE9hu5cxojJXoW\nlr5td8y7IAWzChiI0YLBwLJRGcSEKYwgbLcICqV6JillP9J4X92YlMW6BHoBsMhB1DOl6TyZgMNQ\nVlZGWfNoYelupoRkIT8M7MzXISDSzqoDIKM5mr9eoSAo8ib6YK3ODFN1Ipi0Hm+qUVh97Qb3LCXy\nJ6TLZ7yBPe3PyN9tI0DKKMQaEf7MIeR/pJVXBGsWw1J8lMeUKMZGj/PNQ8jCoeKR8IQWRQA+u08l\nvi2HhJO/OOKzrT7wWfTqQ8JQJWoego0wyxREKsmJVph5puuURbW1rqMZ59X/1NWVNk/LbJ1gpEhD\nRDB7m4Z37EdY60O5sOgWAgfgocCGN+qw4b+xKacYxMN4HjXO+wJq18wCTE6+j/Riq53L1N8BhQ8Y\nGzmRansnzeytnsaTfsvP369sjt22XF5RMpCRvIpwnBzhVtSbsoEOecovV9J60ihS9Fe3klm6gBY7\nO27ky2+Nqy6V5sFI8PXp8SBwkwq5pNi/BqYrHGV+KbX8d32v1RUYbRrV4F6ptibJnNz0aU+HQQBw\ns4RzTcJUIJhlCEM+J8xX7HwyaUGYXM4Vblpw6Pdu9uJT0tjyon29wMG41c5BLhYFL9bVxSB0rylA\no9dhCoNanyu2VfmWH0K1eh+YJaNXtEb0ysEmWhCOAN/BB005lvi/w2S97ehdtGEWfujIFXRsvCgY\n+RCIDAxVVZqHL8q746Y3NWuLClwgx1vHx1NcQUcDBNsRytgo9Gb0DigkKNt+dAAIGmfD2l8RTA00\ni2rxwGF3erRv9z6mzledqzEO17RKC31VFamUnhcuZiDRaRRCBnE8GuE5BHaK8rw79pL1YSIawfMd\nLK7hHkbaDI3kT4s0uTl+t99PyWMS/B/0yfBkHsKDGfriLreKrAncpEeUpJVFKdFGrPl1HIHS5ZEX\ns1gVTXjNJJrMestKVYaEs4nViCstGD9zSan6JhEmfaifIkJ7GLKw+NimA9uOzyKvxUxfRCCFUSvF\nMprZGCfJ4ltS0NYsdjAs1KQSH/5sn/PQ6OIeDHlZ/n3Of315bRk57pzLC1/aVqAi8XLsSRefF/uG\ng/x4R0AMUW0mo2mdnHH/TY/0iT8LYCmwQO5G/dkxHjhJRFJDZ3qUZid99q56MwmCVIj6WDNBu+KO\nQN6QM5N82dHzc1QI4OMalKCyGwtF1fJoK6eNGi3dVQTES3YoHYpJwy9mkxPa0rvrWLS6/4KyUv+I\nEDZZY6lbAg/ozYCu+01v8P5fYavZmOXKq7EICFKOmUroiCAKQb7RAGvnYqGcYPcJRAsDYdAoIFDU\nroKp2Ovcei4dqjC/IMmPpx2utomxn1moEPZkeviZ/h4Jw8M+YkT9VrkRWpAoADxDnDqVJm9CyRZ3\nZYi06cQ7Xi+nISoqnuU0wG4niseJcLPhRyK/eN25gKr33zC0KA1F90dGy8K2XjjGkAy166Fm+3nU\nL2M0OoqaJrHkmiE5GOorVEOvOcgQPi5mcLYVduX9edasttXX1GWuqS6e+TdcltrvITA2mCaGW9W3\nuLXjKkSpq982wMXZ6Lezt5GVq0xxPV/hocBpYZGNk1GnQrKh6TZ2oDCwL3BfXTqGPrO2BfEl6Gt4\n/y3kZDSf1MYEfz0iQOKOy+lWAlsnuPolMTRzT1cOGY/Xo5ZfvbKryDcTb6bhVTvO6/ytROqjAUmQ\nTHPlyl8CeG7hdq6DGm/TlWk+DtDGTXDeiF5IwFeBRsJPlaQ//IAkaAdtGnFztK5xLzNvyFs87v/9\njkbEu4pvPLRGn8alKJB8ZZ/E12VD5owB7dVz3WdKnfFS+ewUVFFKFM/LqRQIoLDfau36JyDEBIoK\nCc9QhI4knWpjgd3rc0Ror6hYufUfdIhZvbYz3935zgckWWECuvAIgdz5z2ckO8J2UHAmrLdWFxtz\n7NFYheF0uQVqIWu7hRMmfPVEgJNVslEfrtSENg19NvNy3vkke892kD/uoMfkVuyjAkS8PzGBrXJ7\nSQqI6VjMifzTsYMS/WQ+kXXwPhjx09QEncMmZSp0thPdg5CZk8eEvrZGprWuaWpDs9S3lN+NV/qh\nEaMcIGIuEMxbxMgD5WtZb20rxjLc674wYAzoVZKd1k0L9/5C0iSgJUwYBe49dyDOKYUMctmkESxi\nVd7eT/IqusXB5Q/PLFKKSpIjnafKrHv8yGyfnTaBC+kzTlVpb2G++mJNfwSbkDuqAvAoKjPAVHv+\nqzQVAKQ0+UOmw3T+29c4atCHzi2+uB2N0pr3kiOHQ8yooLRMdkn24q9cxynSkIZo1/dARHNNdxa3\nCJv1zraDIX2a9McxBdYXYYPeFRe//3X0Icj+fafoR1L6ZnzJ8pkqjZSGr7s9acLQGxabvRMGFAlH\nVSEB3Y7eWvxapneBKniIGGujM8MXaz15lv9RmTiEqxfRsxRhgthrhqNWOlGWfz21p8uZT/iV0h9Y\nfzfelebsnPN2uqnYGEKFTYTm43VLTKdViucgm0FyCsC5i7j0MIw20+J+3xPhA7x4++Bg0WIc2oa6\nyZWBWrw09oorWa4VXS9O4jd/qCs1lXQO9qyI4RaWmg1w/2nMaDgx3InEckVMCboMIeiaxntF0Oan\nPBiBdb1PPzTtsMmzVNpv4Fjv/cOEPRIRFPibNg3qhLCCRI7H9mgzfUzv90GEsJjMVTCAhWsuuHo9\nwGzpvadtd3ZPmPsOFa01NwPTRw0Ka+zQf07NZ5o1vtUsD8QeGQdLQQ/Q5OKw2HbA/bmpERHgtPaO\nU2pjfnadcng5L589GtL1Yn1o8CLSPo3GBOJXJ+EEsGHxmSytk2TceD72Fzn1at8SRZcjtsb4Puy5\nD6IOS7UeaGPeKQA6l11RgJHgfZbUgaJmK6tPYXZqXja2NBHNAlJGUGSUdtTyFwrSw1v9Kvbta3nm\n9dSQggcFLN0jfOh4Wx4PkZqrNAn4aYXAl1hVDrYSJYeIi/g9UWvt4lKEKzII7sSP+/Smvc+DQI7c\nKrUPoBrCwwSIULOWIvTrmc/9H9lyRuvvalVYoO1UJ4h1QZ8l8Awyua3XBfn+LhsE5y8En3VMKVBK\nHDDhGXOo1ly3kQ8NfiYxpwcHcNdNtrv6maO8YQ5GRGqef7AdwOaB88p4d8Lo4SDu62Dzf2fkdySN\nvx+zps0lGn2ew4IFCknQaUtUaHVrSDUG/NZZQabVDl4WAdblcpbCOW8uTiNoFIKFX8dP4RYXgq+N\n0wODhInglAFqObFfIC84RBfDlEA6t/45rPMvS12+uDunWBSZHyVY1Uwvwu/pnI48lV9m61OsJCLO\nOIgrpGewilIwhStXkjxdI/PB+Vez075WfTee96epvw8Gy7kPD7RFvqrDDIrSGm93FKnRHplTj8O5\n5uu+yfmzGBWYcqCbo4mJK6V0M/SJnB1HCGbgLiRxGy/WnHWjaYx9bBqMbBHImuGlpEzPmfDKvgV7\nAlHvpdpzcBlf2iAEr4jhpXqh/KwnRQ4vJL1P84YbChWf4s+IKE0AZ6f0vl7phKgUVq+P+ULvZdoT\nqnWO0Ig8FCSr/a6sZumTd2V59t1HdZTvc9V7LHv7XW1ar8fwPredD5AYEDMepb6AgFxec1FiOc3D\nykbfBhIXJE6n+Yn+BkBfyPaHQtr6CygbQYqPxrWvwqNaGqiR4M1+SnXc1ZPUCuO3jpsqErNCpGur\n86gev9iN95nwRZl1czxWVa9z2Vups+DUDYNl6OGsA3VaU6eY+zfjdw22WdfBTQW1yLZbKdfPdglM\nk0W3fK6xVQmWd7Q0MFJx12rohylS2M3jRt6ymRYDuj9G2x7e5COQAH4HvGSj1xQao0Oqt1esrJ4a\nYIqOffOvsSJq932yvAK//wpl7jU/meranK6kL+SFodAzXhE5O9i3yUroUaSX5y59xIfZoFg4NHP0\nM7zEBF6QB2GW8onP2jBMjRx1c2YyjCZC9I2gxLVNFMuAynr8b5R66ZPqvrh/8y6Mqr83orbrcV1X\njrDazLR6yHEOtNQ4bi8mN7w1RxzLuL2h058RZGlSsTBsO8xP6HAr5Kp2wBfbvI57lK6CxqUspCj8\neO92O5CNgGOfYdotXRnXfVffA4XKFtgvw2Me/hq6OXRjQJn4ru2BJA8kDP43xdNfLhkeKIZM3AoG\nTcMCW6giOWLiADsnkr2ofGgeUFbW+ngIOyctXvMwRFMD+1K5RpwKmd9uVYsHK5u+PLBnvBGoyoS7\n8/m4+m5zQh1ucW8F1QfRwl/sKSrRq0ciF10lQ6zYZB4lLAem6FOmUFaoyuBVPiQdDA1ZsbW/Oy9h\nCVMHPZwPrJ3UnrPvs6YOfXs2Jlfc4nyTMV9gez2SwA0MbPHMnpIcvsBYMqVf1NbZumEG5UI4mVji\nsP+Lo3Q+cV56vHImYilS916X7mZ0gHna6WTTGV9UyJ+Du3k0Tl5TlYLHL/ob4uKWbj822Gt7tv23\nAJnMLGCkgZQbYYRLwv5C7jFKxzPsaYrdBbnhN8Hzj8uWglOv5NmXOcg2pNyIv6Xp7o3P4/taZy/s\nbavizNn1qFu+wczAKyYeOCD1GOD150qXMwDfJGIaD722D5IfvLbBJkBz14/nzS42fO+i/NSflxqQ\nIh8W1dHgXZR1+1xGFhfpNgJ73eVqPltXA5/xNtE6EWKAK2h01+j9T0mPP+TCq80DejbANcjNu+ug\nQ7qp1/IN1oZBnRQf0DNejhOdZ3Ik88Xhwy2Bn0jLmvR81NTNbmVEoZf6/LBhkmC++d5tWUODaE3V\nMmjV73rV8eAB0kRkj3yGu5GLwWEtbau6TqRGb0BcVzUlzqvF5MPetFqKTBQY6sJENoTXq1XQjWm6\n9wH63KFczwcmFRWNgBpkvjQZUGWcCIlioS4fuoQg+RfiCszpQm6etlOglZq6tbo35s7iHLifH2fJ\nXgBvGhw1Mzh5WLkhF0SZtXs1flSvmLCyJM6MwWBe9Vg1rncHvsaqt33+9kknBEsl8yJuvLzpWHIq\nIOyjgBz9NEl5RNUhBXzOzvIRK9F3Z+fejM0uOy+z5JQfMyUHKAEhEtGivvnuKn5Iv1yGYQbKcWzf\nrLxAQP1WA+5zJeTLRbU+kco9GYRaVaIvruvNy1wYXHcRnwEui9exP//Ej02tNULykhUHv7P7iTnf\nYCwad9m+QexSnt0Sf+x7TTYZGucEUC7Y4EDC2m9MsTtXFuhHgin2e9eHMTm7cMiFUf3O8h8Qszop\nwzWvIQZOkkv91HzJT8h4L2b0+s0LMTK978OOGCGHEcqUPGyAWN7nOu16o2UjvQGFPn79rD1sub3W\nU+zCmNvAttFgu659SJhYDXnvhUoNWhfY6acclg3KD38v/SOAfl/eq+85NRYWvJtweiJRYYtk0vVs\nu6EitsHfSy055na+HIelCMTPbv3+3OwB8KNeJGveU0qxSv4okxF8YWWxztNlTRVWwx6fC7LrHTJS\nXhjvKRWBJrdBkAn903FdNO406+gwfbMP6VAaTCMo2gsunicIpS8xTA9jcMdcnCyP4GXLvQi4UckD\nQNgqbWYvw5fxTLOWyf1Qu4u6Ul1cRBRNRqZ3sZG1iD58EIMSS69VEvYM1w5CWdFFkYZesNsF2ZAC\n4RTSQLixyOWbPHcCckgl3/E4FZCkIi1A0xsbsyirad4r4OdBa4ELnPi0ASWPuCJZp8QxIx9ohBTU\ncXKA+rgTrCgCLzavqrmNtp3Gr4WW1sfls95t68GeO6SScz+13sR+D3gkP998Q+3+9ENk5i7fJ9/i\nQcLd8GqnDZaJ/h36F7+cUQZg67jcA5APE29UEhwTU72sbZWGcGykxoFo6Wu8gG9xLNC2pPVSdS6a\nF55fpU0b9k7eoRIM9wJyDoF5jVRrL+wNULRlvZpfiLOpSwjUKnZ6ljjKtTt6qfsye31ZSpQbTEDi\nei67gpANY9oE+l8zI+oIf8eBQod4TXK0aotrRsx0T048+WvCuIiR+iczHejTE8Pdi8+enWorNp6u\nCcR1yfG23NU1xEPqbMjQdnMIw2T7xx8WBpnaS+nBJ1gNENmT+JS56BNxD6xy5OvTLAQXjtm+KiG5\ncnsBBCY/Am/rByb+pNGepykPoma6lXmXc5FMpKsySFKxXx7y5zorfRE9gSbCmTG5Ltvw4142R91i\n812qH7JQQPaumVCKm33BGCVGuitsJfOfv/98p8oQPsV6SftmQusOjQSyn5Qm+dlpy2+VymZDEnTc\neJlGz99qQGTvq8/CnYHNoTodEyCv3uGGGoA0TqUo53dr7ssSRbAFgdsyRHMDxepGAcjkw7T6laTd\nqtTg6VF8hWTkI7MN6+pMfl4m1JUI3jCTvL3r/vgV6Kz3ppGiAoXiSzxy4keXJ6PAPwFmbGMVtZay\nWyEhiliGvUyzaYlZPptWWhQOtNFU7fxXPiYE32GVZIx+SiWJLnWydxbRC/WlhwgNYcGsyqSZMFit\nsNGCmXGtYx50tvzGxQwzehYg0nZ2T3/PJDCx29bJ47EO9lmaIUUPuHUmene0vI1Pu3WArggyDcZm\nv2T2/rnn/OkCTuK9/cnfLCkG9PZvw+b6Q8iqL81fUCaMHPspDM/w/iL0pGUM68CLdUwOhsuz9jrD\nADfcq+EHTkeSm1tRfg+5QtFa4PgsUd1tA9j3+oO8OS4wuERtXT8tItcS8PjZuyin4U0+G5ec8xRq\nNXig33Ho45rUFp/dzkeNN1A0r9jrBnzIxzHAQZgfdTuGWuttmgbHPe/8AhXQ1iFepoTAzqrCqBln\ndNdMPtSzeK2ZoMaHjCWqZs+s8/+1seQjregjKaPbNxtmkplWus0EExT+udkoO7IXvlQq7BgPYo4r\nRpjeAfQC8Li0QA1OIq++poHELmQg9Sv753ldrgUe7HlrntwA8pnVfa3P2xWCC5ti+tEdtMl2Z3R5\nahgZisYsB8c1LNpju99Cd5thHlHl4q8bD77qMmBldsN89OKNqPHdYrbQUxFuR0cSUly501EUip2r\nJwNftGERUEMKhO82u2cZQzDhz17Ttkor/7NeO+Z+DrmO2e4BlNdtNXxiWIprq5n7njgKw0+Y31Z9\no5bBl4zCMvNHlQ/IuBUEEIcDEP1SH8hlHzzCrOoA3/6P17v4Px9APMiiv33ExsXH8T1i0iteJS07\nzLASBPvauUC9xNjitpan8V2eHxBVPDkLlNHX8+hobBnp5vRMSQcBO0JFm33M2lSRBE9ZNcgYf+g3\nkB2CVDaFyDLLvhVdXW034NGCc2deKjNDfZrSkVEFJH0aDJoEYzxeEnMh9d5rIKx3VYmcYHgw6JGg\nJBhUkNHmCjfh0vCo+hjMCPwH95m3vUFe1wKhOoXsIWyk1QJ+QTR9t+hZTowkYlQprcv5t2gWHJYG\nys6npKLa+KanvsrGVrXB32uysIZliELY0rvCu1lnLfOVG5o6VxHS66qJPHimhiy6XX4IgXd6zZiW\nYO7BOZluVxA1fF+ajFTsjY32A70kD/tRSPQpYwH9EMaoF76kkDLhsIobb2kYNomgtk7M503onnCd\nu64Y7Grs+FvIkcG6rJ/SZUqfoPbCZmvMJtxhS3d9eDphfgzSyg0uEcbc30Scvx3MW/Ka45FcPqWU\nTTJuaFa5sYSLgrtp0/xa2z1ZrvplfUMOfs1Ir4WbJ9S9rWOTG+MOlyxRJVANozxhNnL+p0UxBvIK\nFUnFSYxOeTffvL/9AiuwYKEGlG8TP4W0kgfeL3hMAL5gpcXggAW/2zDLba/syJhMD6Tp62ZpzZTH\nz/IPQv4NIEnBLbQy6BH4d0wGaSLfPyXvaUjY7YQ+ntuC31nihw1bQwaZ+MUWyZRcmiX5r9u7+XdL\nI1L1yZBLfdvFM+nIfXra/bYYxC99jIKFf7pNPlxoLNMW5ArXRg/FY+4oEjkoCU5VQUgZUNAuJNxU\nkjCdWYT/MrC1tV8BTjT8vgZqsUVG+9Q9BiJFhhAhyxYKch4SAtURNyGrLtp0SSnIYJ3B/ZVjzn7I\nxuxZZ2v2AflGdJfcDL+Rr6aLQdbjGj/+0zoSVfLZv4JbXBQwhr85A0tkeg6cGcxR9Vza/zc7+M6g\nJ5ccWZqPWubJGmJvKwm8cnMa+pcVTxa27WsCDyvS0Y68jalHosyqevLvcB3xDPTsn2uHlV+VpQcj\nV0VFxSXFpQmg8i91a+zS4L7xHHbrjcRUly+muThjtgw6ig/wF5IxtSpj5x7igdPnhA36Go4s6ycI\nIiK57NlcBNfiebdpAbi/w5sM+taV1uXqviHauEuFjtQA33Ok8ch86BdmtrhnfMrEJ8rHapBXrVht\nIdcFv0tQUfg2nx+8xWmAW0dbKjOV9EeqQp0I4g9LeZD5GoAP9n3P9uxbxza4GAUXxvg8YQn638cD\npJ08vWFIXQz+R7QyyTo9sX+L/8OhlUe57VaGzoGGHeg2RfhPUXKQ5g4vkHkUQq05nbCCuLIsc/NF\nA9VSgYsetAZd8ab3oI/3nSeVQn9BqI6eeK76MN9q/uGinlJrJwDKg2lAwE4Sx1NtxZUDL5Qng1z2\n+lwVJzNItzXwfBtFu0TCpNDRouYbIY10OgzqrgN8p1Iw4yC4fdfmvvoeJBaWzueEUdTT0lR9CbXg\nnCIcYnStmgLfad7bKNKuZF0N2BdtTyt02DP4LzxwMUX9zaxXo2s/7FBfFcU3FJuvYBvJNxclo8rd\nK99uOpDhoAF68Cp8f3U1xGQs9hcQFsIiZxeJK3ILBP5gp+CyPPneqHwgN07Z3h+9wvOFgwV7PuNs\nihcq9INZE5hivSIUv1J4uqxZxw2YOvj+4XtgILMDsLBUh2/CeiJHDnRXHHXa8xyHN/VEZlvP995w\nphboRlruPD5mR/ocPYK7UdxRiSWJM3aJzUcLRi955umxUm0bw6N0pSJ7JahT+I2XC34PwpktoFJK\ncnszLXBWbxz29fPMUkVIgrJLImaca+mZQRabAzDdtkZVBJfpiL95/WLyAlyEFqHx6pOn9YdqK/x8\nls+aAzMGETkfnoOlM6je/dTzj3l6Qegyttg6hacm7+dwNcr5RLP10+lmLI47KpEZMRH0JtDps/ey\nRtCY/uN6O1UaJdOhdtyZCpou6ZZrao39nAAK3hsYPS++aZgjVAM+j0HZPfDxzqTE4Wp2AHE0vEVb\nsbWOC5JkhFUEsNgxf3CZZek4tylhZBFe2qAPmca7Nr8cX+/fGwJa4zsstW1RSHzzXp+ga7T04RRj\nqKwX8lhMp83DKrFARIncMkCPhC9OchoFv6Gq/qOjB5ENUspxDy4S/IOsNdRpKsjsoA/E6+aiSeQp\n3DWa071ADqC3V/jEDFQxKj++OP+/pINq6Y1craLIugETiEcpuMZtIfeNmTtUQ9bQlnnIHSMgiiLk\nEYO/fwfSTz7trn+YBvKL5vAPEgd8EXnJTQmYglGi3iPtfYZCecyOfq3JykNYoLGzlc8l+lgHht6D\njBryf+zujUdATobQ6vmyUQSCtmPgv044olqWdpLhzoc9ASuMzv1Tf60b+vX3nQLZbSJuYh7SHxUc\nGxaQJbaAUNbtxB873Z2xQaexfwD0XIgmIrV4nTsGA8CKeZGD44WmVGfF2zAEj0Suw90pvxZ6ak52\npnNXRoiYA1GbUbaAPifn9es5nNMox1WMhiiFqkfTt6QT/LPDaI6pctEEKbhZABvzuC+AFV6ApkFQ\n9sEbC67oJqc2L/F5+EIi5bC2E4TuVw5PGllkgLBAmBS9ZJXLt8W/7AZzh2zXOiztarPYrGxcQWQi\n1NqD9kbqMfjq4GgxdfOh6GXp+/8hzguNrB0XOLT57jqu3ukdyPI/38f/tdSR8rVLm9ctklpFxIp1\natcGe6ZzLhkmrAWaEgXu+rkvalDeJJzYMCdssUggP9sbyIBqNm+bu0hs27axwtzO0aLTdEmRy7BX\n02mW+0eM4axPDPBXp7Km1zDETT9OuwhMcrmk9IDiDrbaUj5u9Is6RN5ZNoT9chv4XZJKvLR2ut3e\nQGCvbdUAVHxPLCOslYfGfXiNFdwL9ygx5Xv94ULNBynBX65Yc0v5uokgRUlQFr4KxsdMcxhnJrjd\n5mKOOdcKDyXcYKKk1YrFmxp2Mqa1iRK0gm7BoGrH6dy8ZY4obArr8X7BYzzkf4oUx8I+5e2BLyig\nSCmP33zMkZFpk/Auh1rgfxz/PbMciaPSHZvrsiCsT3mIopE+JgltnrrCcjK7GAdB5hrTS3w3SR1y\nGBavVYxjiEqnr8WlVGP5HbH08fIsOBlMX7LO5sciII0cGlRpn364mCbdp91BslmVrQoxcPaj+TC9\nO0MZi9C8aOZsUVk7GGBEye2EQ6zuEpA0PE6X2sUd4HqfaTrtQg1EivraNouAMLztKnLgN7pU/ETf\nK4iMYGGJzip/SjpXL4XIr62c0IMMYJzIXHBaTyrZ4idSxkM6S6Q/VUPOjO00HKdaRqOIH4Fl7siD\nQGdPpuIRj0b31W/7wIswcFZmCuzoZQGgj7b7P4nLZ1ugw4MHnHQ0p0zWM+A+R01iDJDTBdfEPSsz\ntVdGAoTuJ+O5nYpHMc+IAOA29tvUF0hLHKvwz719ElO2436olcY+xVc88CWad1ptcp6aodqcFyUM\nOlHeSnAgLnQRB4lEfJKprHEnN1TrjL67oHO/cABupwcFGBhTJebJn1u/nizRAVf+CKSUryUX1plf\nq1Wg9A52pO4nv4UPs5j2/i4PgDiSZY8dZu2YgE043PYJ5dEjNrmyvjaWkjFwtziqqKJ/zAwzxSfY\nFx5VOVen0XsXcoLpFHKH06Nbml4lnpDAxCdCAQlBhJagIUqVZUEIMzzBgaOUj7Y0E/Sx/MU06AAm\nb+hjKhJ4ht+9FDe3q31ngEpHms3C2CB73sGjLP85VrkgocaNNOGwWb85+dtp6SbR1oOXKGSgDIuW\nWa9nFDdb80zA/9MYuiTLZB0pGf2ysznBH4gVaJ86M27pJbE/oidnAlTQUPvFB38TOYQNTSnCNbmC\nBY/7Vz2hDC+A4DHGgWSJ/wWGblIidbsZpgHg1Xo8ekbgWacICP4eJRnFY0h99QUPrb9rr7nSKoVD\n4fgt/CUrqX9nvnFnEEI8eiWD+oHVrQKGRK6TnOP/839TpPTKpwfa5Qlp8j3ABCliKMAkPP6HOX+K\ndwjGgNzWtsIMFH+5fIx94smDLYyUxaUiQLsy44s+y54eVCf5XtKV7oMkEfvPoBAXlmhHKys2EraD\nKquLZQqsoRYc87pUW7KZ+/FGw76fQKeccRJfucdYfj2hHBcIaBuJUIPKrC592N7/WwEBhSd8nLa1\nLZKRMwzDGxXGYlmDMwf56Zf6OgqrCqSI/SnvV5mzligO5Au0AT5y8UGRR9x2hTLAohR3HhVudEXO\nowk0UJg8YDcoxxu0VpwoNbMLIcaEY1pemBsAdLqJhGMTRnneNxKrTtSgUwFN30HpP1fHg8FLhkHd\nFEhXXm6zT2mMHNhNgq8nbsHlIZj6lPdOCqJht4xkSQhmq+b4kwFjsVIOsR+y6Mo+C1vtZM89MyCi\n6SWt8fabXIQhJg+XGRqdh6vVWl5/YYso5T332zDvVQTlJAIu30bYPbZTre/xqhs/eG5/01Gy6nQd\nsONvdiK5TjgFj1gAUliaaUHi3VsgkrNExifz+rXAoecbj8lpEh36t3rEyvXjjGsAl6nV1UgQiCOU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mjmT3stzC/Xv3U+2KUtVN3IyoZysXfApjzYPxRGoY14wxVxml3cjWkid8wTZt/\nqKiZ8+DNGhOWsKqtYFfzvK3ApRuFrMQI4nmfP0ioaEsTGAw0TGjMc/edUC/KrxwpP9WbWlpcR1Mn\nyRmHmO1G980fLf1P/q5GKog5mVjHFI3YGEOry1qcHAJR2dzO40KJ0/5N3/Pxa7i6wNIJh/mHzFZ+\n31kRMiX98q/i5AnwSm6CIHRH2WptfuJJu8bOdHyEc2X/ZykVW5x17fso5tTlUjx5p+HR96FFUaBH\nlCZQUHaHREVDgLoo37xNLUuVkMHZqp9r/Bd63iatA1vtI53HEnJpU6AsMLIsCdkY+Lf82Feavy1/\nXEAxqjo7H1QoA9YuFHqbS5WP7hI7NfNQMDjoqprgcz9/UB7xC5WYr8rq2d5mgeAbnstt5tE7sQm6\nQgLlHockY4CJK8Xvmv4d4SblYXDAds1reKTgyhuI4ZtI4IEsIdiA6/FCJ2Vtw+GFFB0zIWutZ9Qg\nvRS3DxbGOPG7mDhBr7DndSkrx0aocMGbybimWSBSg54OO8poGqinGYfYKzIcnpmV8De9rNUYTd70\nICpozYFwIfHD6uW/tcf8vX5K9TD61i5pXIBimaenR5BI2PMYIhZxYqmWN5m2C4lpq7eUVSFU6cJU\nDopA56H0YzS1Yghkaz6ccapw4+IWSfmbW+U+xxGGT3wNd/C0LkyFKJzdCEZLxeZWC2Om6YAKNHn+\niFQ0gxa5wWQPwuJ8ZhYyqSk/q1Ta/GqqRzNbWLlZC4xztgz3JY1yx0g4gGXDKlO705YMD2H1sVzh\ny8FE+koC6h6l4i41cL/DFsmJm5Jqj52bd3iigktOLK6QtleXtA6WLojTYOnJOguFYPtthxaSvmGm\nqQTuLmCdlOWgPxQizNJRMRBTiuN87BktKycizvXRwigxNRv5V2btiXkJPtyPyqkLA4WN6rCMZBko\niXN3m7e9ovTge7aNZ42IWrAY75oe3jrfzduFMjJB7BHwVaV1dNpZqNe+ZP4gzGhO6yKU6gUhhLjo\nhuML+408orbEV4f3IS8O1PfQ+c9afO72/Ivqt12Iq1YNG3EKdwt+NulV+j6oevJWc1U/vV8MrQa0\nbeVkn5LMWMAilgmbX61R6wISQo0NfBGdFL7yL76BwJ5wauMZ3beZYu5smvlVxpEwVhQ8fFxH5Xpo\noihRZCSnp0L/BG8e+f6/sZJ3g939OWCjOd7v+b1g7lOXhRH12gLTb/5yvbYNu6R73tarKDzA+EDC\nV6Cjc0uuB1aWJB/N+OrNOcVXKhZcotiTMF4vDqfRNuqt4Lr8gjOQdRbrQEveoS5Z3dGPAUi07lqg\nqVZaKQNTSVTGNdFooKDV6jxrbpDI7VfHYQeRlcfaGQ1FG1NFjzlHBtwZAFGM65hXUyuLRvTsfmyJ\nKoaS6UFC1MuuQS/l45/VFm1tfQmlNWunhV0kpPrB8jg4HzKBk9f2BfqoHchtOGcUKTenprkzbPfn\nw4lemz9G4I8Lj5ly28uFVHheaCmKS4+8HGNam+xtZvyfd5dpBY8AcoNMtHr6i4UmfWaURIdijXdH\n4Bmll6uW4Pbk+DGTBh4mPSh2on/JXHVKOI+tXmcYauiEje985N91S+0Na3tbw+coqe0WLnAcRjrm\nq0HRhBFaPvHkoNwuQKN20uBjwavtz72na95RG+VD89klPSBmoG9U09U91P6sJ18GtlDxXCP0UAvS\nYwS5AWhwvu1ZBenlPuvRWL5SCxKd60mnVbKgePL10ztCgNJWKHL/tYG5erl6R7VpWRMeuAsivG4L\nvlZh1VMUk7WcEFtlQ8ewoghZgp/iUiIGdB8UYFsMC2n0jF2KlbD0qxkuacheyV42MhjTNrWOGJpP\nb8cLqovTnWaUaEQR4ox7qhg+i7lW7pFMSIP9k6dZSVrywanuiKxyZEM8txnRmifM5BWdVlFe7o4Q\n6LDdZw4TPzfPC/79pncGr4kcfXBeItIkCz2Kb37YPXMbPvCbBJ3buirX4xlN4U9Fzi5U0OI8rI/m\nxEaubhXYIo1C1wVEbMmhjjAYqm9mdtqwtK34nKt6UA8yzfBAKUcRS9C7ComgLKAnsqqYmQ6+d9du\nQEqBOA+dGyP5ei6S8XQuTmoeHBEzJtkaDcSReujBlwUYKT5jEDk0nET2T3W05RN8O+I1iuCL2zEk\nCBa9XojaCW7WnyD9fHIfIlVP3k5fyrMDshYPSJRoF+L3za8tcsFxoTB29Q6BjKAxZ/R2U7piuOIo\n3MRAXcIwBS55HqoJGM2SsAP+FtMEdbi9rvWNynjnYLT3VWrn9y4dpa1PzuBknAAIADZ1iJy8w45l\nKMoZndthreWqtx5WJ/NDeCbjKlRUXo+VcTOw5wfPGjtROIJrk+a0pBEvk9IgkLPXS67zcTg3SmX6\nqQGKLp8Q4wEM9wWWnL2h6O0wifvd8KNCNPziDdUS1b31LePR/mZo4s8QhVTskrjHFAb4QUbPl7a6\nHLudISZ7yV3Gmp6lxCIVCJYIiPkLiVfwQRSQViwIUWt6BCc960d/MqoOz0fwpsTkdjYr+EqA4FGJ\nwxJLPlTgl2lMVKdWumgkU6nREoX2fmCnx53Jl2LcDzdxTiKv4g72G/QzytkzP/3csANiNniXJKyb\nyPEYM+lewTjlwyBrvA1Hseq0rwEyuZIohPauQrtMD/CqgPghUCPc1zEUWqtbD7Cs6Wa9Q6i9cZe6\noygam6u4DqOHve4zENyA4vn6BeFcxUULrbhaf00LyIK8JhVfO3PgfxROzcPGkUTDn9lNMcgSYFw1\nF5h0O+k4KTZAuh5WmzhA07pUadrHIEWS84zpb597LkMmlP/Ir2b5DSd3a9WrRzXtffoW6wj+dqC7\npakKeVaDaFLsKew4NQn/5Gv2SSsl4XFUnLgN38g3e2L47gMZVmWlB+Y2pxNwsAyXV5zrfZ66+6NO\n/atnQFy39BdJa/QlM1kXvILZzqUOXKGZVYZLaTWJEug9PUV3sxznlaY+cyInU/Zyp4GnlbQ0XVJM\njjTgTXNLU2xwchHYZ2fBegrJgvIFGdryBZ0iiPdHvP0oKTrobiiLLzbV6OGhFV17NAM1UtiiGvmX\nCecPeJZhMWSNd1sR0zXBMsmK0TzQz9wCoe+6xVsyVVjA7V2FOPwHS/UUbVQY48xEuz3BqvoRTDza\n/Upe/JHbXSk9IhwLJhuQT51Ra6cPMWmXfgxXBAUVwMzzMx5nf38uLxEbI8HuxHJNoAr5GGRdDbDM\nvIaZdGD58IBnjKY6oHp0HRYu4WKaLDRblLUdGdvRRYTa8gDWhSNjXPohCsckVTdJP+6e2e4QOj4j\nERJFaK63X5h0QsmZOgpBr0rJwPTHnVY6GB3YKBw354eubQ9K7LofK66j6q3zT4Guf8RJUbdEAwPX\nO76Nk2K/YZetp9kO7l+c5cAIr8TwXPfl9w6+CZ8CwysJcd4GCwCkfBAE6qXqEVKayXnkzL+/gi9q\nYhodZUcg9N6TE/MQblA4jb3J2ttB1IdT6RQqaipYfiglppdRbRW1Qij7hpryOT2LWAgda1QDnOCw\nN/aRmOHe3cYkOP7spl87Ts3hk7E2Ax/UCeVxagIHpfy+FrsHZ4qiX+k649T/cfEl5rBbvmxA/xiL\nCwG9iyKqxglcf46ESxutKiDbBbgTxm51oe53JUdUJ80WTQ9/VQIlCKHVZPeWam1by0CZhhQ+FHPz\niRM7iAkCLl0ad6jbmsTBDB4Yo3j9GzlRn4OwfvkX+1X6Br/jpb7Ods5R9sYdCU8iirwHrrDeyl4P\n5Oa3TjRfEeRc/j9P7DyMx3ksTLodItG9x/vZWgOy4iFOa215lI7+X25rZS1Ummp/5i+Xpg/2bqL1\nYc6h7fbQjdpHUXjn4QUz0LYvmc+BNdDxx7TgSkeXOeHhdOTNPZBaDLDk2cy+lw8H7HLME+RVBt1k\nsXgcUBHjvvnpcteXo3EY/4mNbR/ZqLeXimXlWhSbjhCGYDzmqa5rgtz3n/CYymQhxCskPAQGw+sz\nezc1Bd1Gs8eiRp5AYUfgRpr4jbtwjt6z++6Vu8p97biVpBs1ExN2/VFrFqgpOJw9uA6QDmVZnx8t\ntsVnG09ksxL5q7LXryPT74zfhepy7+7aTH5YUpDpb2waeTIFvBdg8gmxXZB2ZJNSvEFEPglZ4KhP\ns5Wo15NcuLVfQySWiiEeFOZVqadoOuNZDghUEifrUf+33tFg6SeVx+zBDJbH89YDSGPONwYA8KZ1\nllfpAVGLBseobFKvocGgdqQf5YsUQQL2aNanPQqWDHJHr30u4IJBVKuluk8tjx90eD5z0fjoCqq3\nJds3DQnYjrQ7BU2xCixiaN26VICrnw47sIinfFcVXPidugt7ZC/KdJ/aQIVQbkrgDLjDxprUS7W1\nFffseESv5PsMOXQPCsFvlKPUCAAM4JKznpl/d5fx73jhcyMXizSXCoL3+8p/2BFB2u1ZYbisTH6V\nHLzAnIYsfS7eDvpwedtN7UZnmo/srjqJdMDTnCXrvGjHEr7252l6Ipuygr6C+WLPMQU9rrfvIwyN\n7t6vCh04Uqaszzc5CY9Aglhmwt/2Y5fx9JkGZumJynrdGXP33p2621iPJ4AevXZ3fdpNsCsmXnzc\n03cELWhMybwOw1YYoFbfYaz0s7PGleQIeLnk/884jAZTBzjHWSoLCwehSZqGTEAap+F/qiwHr9if\nuKfdQfIf1sOFlHlFnmEytGa24c0rloKQYqZPkuEVY7dS+SDs3W/Bcfs8x0goY2jaXFj4ZMP5UuTc\nyYDHI66HFcvlFknDksj2QlDgRfqZvhK4nKn/ov1YLKpHRhjo71lyHjJm2VbSQ+0OKQv8nqczLIpC\n2mynrP+VJILPijymLq5vCPGo6QllgLdqvuNKBIsJJrlMhIMyMmnRNJvVS+sTiwwsxinybxQicOf4\n34R6e7oY72ItEWWzrwJMtmMMcQrNBoRVgZsDnDu3B/iLN9B445+Ia/2xI8tg4h4bWVtfUrPF/GHF\nCCMcBaai/7iqersKU25P9YqCrW5gzK4yd6hHRVmP/GReTSC8etOcS/dQ+iH7YAw6g+VqwGCE9NNq\nrDHzSFNHzcuTFPuPTnjdDyBuk8tgZ2P8L+upWmAB8WRT08N0FYWxRVHTgdWwIb++kpR4oah3SMVh\ncMdDNeDMRXWOPYx+eoBFG4TdDky/+Rpt3Y3t+kXs5rBtuM3mN6lO/N62N0YIWBy9PPROt6ABLhjn\nkTSPxHFYPlq+2tW7Yq6PpB3gOJgIpw6Jd2FVY/nnHFVGLeti1SuPxoqA/zB+RqAZ1ugF1/HuD/no\nlOzP6btVSLptufMfKGXQlqJurAbPNswzU1SgOzKKgJWsBc8A1dZhUmmODZr7QJWHHjXRe7yJioTB\nSe+1t1P79UExlkY2Av53wBpm/Qf4fP4wQc1SW3DW0IMbQtjt9uv9/X9fGV6/G4GCcNq3idyucymc\n5DsqZ30iU7nUPo5TDk2xTfYTo5J6KDFbWg68PBTUjc9YU+xUqFwxcpfCVXhHxosuzfUSnP6d8DrK\n3sQNP4khBnas9LtuKIEewVH1iv2IiKUdT79XbsL/vFcNBq0+Sqvvg8Mk/IozOebCZTqLA+pRh8j1\nPO0dg1EYBx38k9kKMWWaaucDeaXpyGKEurCt+rNNj6O3iZ4CRZX9o1/noytgel7upuLBzZqGwGps\n73AtMGLpnD77WEcHmk7vCb/9ZIQ/1JqILIS7tWQrpz13TnS0vYnHyN54RndRSVrH3tV5/OmRT8Vr\n86wb6pLSlRI3+LytODQtXr5Pjm9zRxy6ohZ3KULiJ++p02B77O1XtFtNs3jRNxHwmT1DpOf+e3YF\n7zwucJ1nuZyIc7dAzGodikj09oxWDfGZLpGvUv8slbHALDP09Q1sZYzbZb1WMxARlYmMMbOMv6bp\nqXEGb6OxN9Z+GzBYi3Txjse2FDv2HMAimBoCXDRXlk+yVpwUiCn5LTOOrLgekPXApsjOz7wN1iAF\nuPCOno030qg47WpIfuuAkwTBNanyjM9t9kGvHBUbYvNGJkbeRm8WiEhVGVnfSDbFg1e8sBlL0Lu3\naMpK5PBpegs+vk8K2IkOGYvR5Aow1ZeA5q1rcMpEdIMR3mvYVfmtKdsviHZ0E9byAXZKlxdLV500\nemm5GQ0btI6qUDeat0/afCtAal+KQNfrpHPt/BKEshvW65onuKtkGdVhgINJh2YjRt6jDRwNZQy0\nt2/zk33lRdcQQQ8LBhOyDN4ulcQycDTY8OirqCVBDoNZ+9yHallJ2KKSJ36/U8NF0hahr7y5qtSM\nA/CkX1Sq/WW9AUQghL6/flbo6xyPz6Bk2CrrAkVR1m8WMsMYMTJzDzfobDkq/uOLuUcYSHS8GNM6\nIdJqSHQHu56KgPK0O/DnWxNXJkyeBTmFrEEAeToW3FoLlXfLwtvWmC06ciSqRnbm4gQimtKLA186\n3MaT356eSiGNv5qN+OQ8jv9hOKg17JmP9W2QWQxotOSiN3CpHK96mnBgBkpBqeksHSwkZ0Ym0Qlr\nWv4lGLAVFUI/rN/rGeRGjup/z4iwy542LcR9kEYZOCDY7F+46FcaQVcgrEM3BbZM1pZ7vMLZbBAB\nNIp2+fxvCHdPb2MYCkQJEi/lNoxzKSXQtUF/XliVdGDd/gJwms8Xkb0HYbyyJaWmfe/7DA0SWmmI\n5fHk2ePB/BvngIkwjKN6KMMHlozyCxLMBeUviR479mhHY3qV5gjKRE18cK3t6WtqD1l/r8fKmf2w\nmzxkLYc44rJqGUZqz2o47L0QXKUl4KpIGJ/PgoMPvA1kf0RdRqeBduHyjVFsKxHnVpN5TcWOPpEw\nsnzFSf8uh2B3xmR8tN3FtBy76kvQdN+6jOgMRDMtqYF7sGVg9vWPkeNNYzWk3rNC82l1Zzzx1ztQ\nJPblX9T7Eopb8dQclIpQtlVlyIvKm//abXhCgGVhBiQO4HX0Mien3FDZ990Z+ACbN0ccUL4Q1a8i\nxBtv+PWgZCeEA7utiTzOAPee3+34gAm6naicmXjXFCr2YvuZ5nD8J4hTINSaASRF8YaSrvYywwTy\n0iiBeMiahZnjX6Ra2SrDx7v34srF6/hoMCA8DyH1mFmdEUrCRgE4t6Hi1YVAINEphDeCGVVAVZ2N\nPykajTZihGf35IIRqjlR4U376Y0tBRNDAGp0Q6kPtvejvKlrZKN4G7r1lJAyP09bE7KDPRmbs/fs\nNyVC8RFydYUivRE6veitQTKDOMDm6JNj7qAaWp77cujnVGbn64Bd4xm7WZeKIKIm4aYSnUwJl5hL\nD+LcQnpAu6AAfc5YHgN5y5HYw1yEUhRnMl/L5Bjz/LberH5kV5CAMGc35Dn5CCsgW62MH0Klur3t\nqvDQ3OvhGmDL4Y2xOoW4kBC/Rjs4GjGtRYrXT4e2tlpknnpaKlAKV1YKawJ0W5ajt598+Y5C55Xi\nFrK/U1x+yGGVlKNimaW2agOl9VuEcCh6glCflnLynYngd4XXKA2JKIVNlRW01Xgdtfi10B5ipXZS\nZVEoJ/hncNBjVQcHqAeGhnptqMCqfg7CcyShKr61kfcsAc5VLbEphtId0rpP5V0qOrtNJAKxoEaN\n0ppVGEAI9TOF73jTYNy5e79+kav+WYHx6AgbaL192QJxAqG6252UlyKD+TN3wBZoObX12Adr3vX0\nj8zGgO0he4Dx9Cc1zYRKQf+J+yMSyWdmVEp+MKCbgyK6LEYoIp17fcKhZNmAg+ZS36UfkshviFTK\n+POKT3AT1fvcHL8OYw/QdRPMaLWPsOWPzcq4yVgeUMUgiaSnDUCDUB2yCO1vrkhPMwKhlhn0LwuZ\nwfM3h+czZAHuZRighzjAJUXwkEsN1Pgt9F4Ga9v4FpSBRve37ucHHuEn5jrX7b93oBywaPyG4za/\nsKerqFfobeFqou+l5uZHAWu9PB7G/36xCuN+gmjhdwI/5TjKnJGVa/Y4mrJHsK6xloq5ez4C0iUi\nDmzKDqJoGdws5uiPusdI5CZWqgii+tJ8UWOIJHe9wGCyFsM8DcbrnffJ/viThaJpSCiPR0zFv6En\nui3LW356UdHeYjk/6ZLmILb75WrZlIL0kBuk74qo9+iFxkDdId6A9FExjyh5C0dP0BDu7B53lknF\nihlFcZBGxzYFi0FbzdfCEM2K3tcVp8899GthOJgGu1N/qgTjg7ZC/hyW+NBVWOcsA/YI7H3p0zgC\nXErEvovgf4PesV8V5YrcnbNOLDkF2F+Hf+2W32/JFOuPVvcNZ0gw633lx0jeGk6zfpU4S+UqC6Z5\nlv2D7EYFebe8OBLKCmRA2kE6MXcrMBmFn7B6+0q/HxIcCLbSLBhEYooIbwK4lBvBHwt3ZNID9S46\nrlt9jHIYAJJLaDmqvniX1DClRh9zTvsHpSGG3mOKpwD1pbAsE/8AMN715F7VM9sLDloqgirm14c6\n6KaiDL34h1u3UPQcAYa/iUBBFD/omsncOZqodQoWJn1t78iJvCBlDiE/KRD+shi7MBiWR2qJzUV6\nvszTfqHmcpXqEKqJvAXBiNAYngR+GmMYIbTgB1YEwXQCZD0LToUOiwp5anTrAhDmS/ZUfyPA3O6e\nTeDJzu+g6CkNKGT6qnI9zSYRkn59rzdWimTbmd31+E9sE3oldZ7yukJKGm9HcrjmEn5iIHN2ksfy\n/bkuKAzgYebyoHDYTZZ4VZqRJkKaocRo0fbIi3zd65Gp3s5K7YmVN1cvTb30eNMvckNTr5tRJMXB\nQ1bruBwB0ntnrr5x/IGxj/XRZ7/oSwIkJdyNApk2te/birUbUR6UnGc4y4ttNTCDEuqggW3Cbfx9\n9tQdOjLwh43tPYA8H/M++ZwOf3HhfJjQQKysv0lOWY4S7ARJ3OrEoqKqyXAWdXniajcpDVbynsa8\nNsjwPf5WL5HPa+3iczXjARgydFiLFoxXOvEHjL7tJu91ngVLoHuKCc1sVCOdlfYThGi23uWH7vJ0\nYOLKmVWobVhcf5VpB8+yu1Am0dOHkBdHCr3rrgZdInlMue8oop0PLaPmJVMowyGjsverdCv6z6UE\nOqIUWtaPVpiBpHHD9Yw6XYxDCAiGibe+Gl6m/28e8Ym+QSzsogPaSQBf0SelV7KrqzHbId7aPJEq\ngRCDJzmPbD1Avv3QgG3iKsbrPI2KxWvxVP0dALSOEGlaW1luiCFhyVQZMjhvB2qkJbqeiTDhS7h7\n3EUa4i+fV/sjeR56deRJoqqk3M2q5B2q8M8jiW3dXI4Bxnmf1g7J8vrQ+iXPrLgC2JkSbeRZ/eFF\nCnM7HWHG7fLPw+dEcoxCvhyjiLG4nrEVGBWGXhUmx7lCGjGBUwRSXgUKYTNM+tVB/GGQSLqO1BXa\nqonr6lyJ9aQG7gc66GT96wZBQGclYbR4btuwY1dBNSMp+euELOd1xEiLYTm8oFfu+4GyZNtxGaNH\nQPGRCGjL34JDEnum18YLX1sqaLAaI4Vd3oohNrCZpQUGEPboSGGh1OhTL0TcjUaI1kzx5pnFFlQW\num+7966tMQzGB0widT/dnC203OehdRUxF3mVKO3vyZQS/QQL0LhvmTW6F2yZftZZwGor4BAllquC\n557VhXbkeLpl/vbtt0chG5IT/u9C7bdHihJPK9UT4R88nM21DYUK11SdT+pomG5JH2mJc3Io3YzG\nZcfbv8KIZsybNllnnP/EBy1sp1maLL9qN6kF8hDFHfB/Jr2elZJJ01JYHPOQCHNy+UA2Gl5QwPr8\nc9SHuUtr8rz+WAOCvege7emLx4Jt5ytymFbSfrvoRM+ZUxFmqe62SfHTEzg7ml6FYKGwZFzHxAVP\nqClbYQVma1hfPRcOQ2EPNB+IDQvSMtnMgfNCRvCXzR+Q+46QsNEdqQLttQrMkLWYUWQ/PxH/abKm\naMyBEKhbB0uA37pA7d7nNWme6VWCZ7Phlw4sTGZ9usfSAF2iks+dhfHFUczhnkRr5kLs2nN//1Hm\nujL9S2Xh+YR8mZbK/X/DNNxk5vMeM2BEVm1PZoxk2SRTp2R/vYNolwEbwelAj06fIHNm5MpYsL1E\n7ncTpnND/46Rp+9dC46VWjFitJhw6xYQBnAnAUgK5XKJoMd1ULWbXo9Obn6RduRPzN0a789FLdcx\n4OyYK3f61tQF3inIYC1r1HHOGDrI2xRZVZNZNDzADjAcygRu1Sw4WL8VBi/vYsKqVoNERt38KOEl\n9NyG3q3+6TPPg72wauvsj9vXnxr/ERZ9FdkR/nhOatd9PJBBtPaEAMYvPNJ01ByAr1H9v7EusrNo\ndtHZtpRoWhrKsTvw8ChWSzj4E7jptyFhnLEslaw4KGbKc0rKYK/kNZB6DrrEl2aCV7QHsdkX9Bj1\nPKcOWqa37YQlp97WsyhXrowmbd3CistDmVeRnzDx4swr7Q6boEig1BCH+1d5aIEO9ffvu2QbMvti\nAbcrVFpP6sBalPmiLjS15uhWV8KEGw781zQ4mqnoVw3oCKOuwjvvK/9OhNoout6ggrrMMfHFLop/\n7TagcwxVB59eehfgXDHC5RxEwiKlLkX4TdQk3bJgWiNKjaUI0iF5sXdRTcu76owM9bPDeFQ0zvcK\ndUkPtD7AXtk/vFhKjwLRLeB3UTz+YhoVaUH1daPHUMlMEH+eJQESKAxgCeuJAj8GZnyT7+cw0TT7\ncjpaqS0H1C0WUL6EFh9/Re8yGO0a8+1Wp5GoD3ceJ9EingExgibnx1rZ3dLJ8Hmf4F6c97FHtUGj\nWWra/KN5WoCJrdl6TSdm2vPt/3JFImXL3VxVhD1lHg5jk87q0UvPEFJbe56oPyUDYIHorFMXCtkB\nSp0+FG2szkowh6Po7B7p6lTueX4hCfE63q/RjQu0vNkacOGXYHvO/nT/7D6KtFG9OpRZwtuB5emu\nCGXEsehh9FDIFrOpVZN7q6ME4mkpcEBoVM5qdWoVt/3gUeGi7NoO+67+Xub8tmwmHzbP8nOXg3X9\nfNoTD1RXYZyvLZE4fAJJsmUmaxheX5QZ7wY+viDhcuVgAlnxxX0LLauJsgSdLdbbADd1bV5VS5Lr\n7B78FfM0LvFrQA5ay6ZN+k3078VR8KQ77wOOtuiXuls/asxNNLGEZe3j1Oqa8f4PJaCMlo6GC4Fw\nG3ADbVBwDp6yZwFL+jqVJcecF0yGso2WSscQ2vtmwXqV/rt1ntgPMcrqJSBUCsg3n8UAqSqyrJMP\nFl3aW/zxO8e34gRl8Gb+Av7qEDyqQnJbSeqv+bQRtgG85qT9oO8xyqlwpsHqHY98338C2Doe0qWE\nihq/+PAb/4nr9c5kJKMC6aqGRJYAD0fox21bybPmT4ZB2ZffeOrw36ME+hNkiBhNVDEW0j4LFPfC\nYTBRPHdDBONBGboUy+sX0hhLEFqDxD/pZ5nuulAJ1Gnpq5tYOdAVxsaLS4xVsiN6zvxKorSgpp8N\n6MetCHR0J1sVQSDbgLtEnrJ7/7F0wLUSS9jjxyJk3JHSRXyJQkLPrGjNvsgaaZ2+lUq84JavE4TW\n9WVMjvOBSoHbjCPnbFZC8a49DiHvK1W7MjjzSoFWxEqbJf55ZKbmbZgJvRBEMomcR2nX6WZLbKWd\noRt3xjhQXyyiLw7QmCKsylEF4+dhqgHIebhz0y70vdoOeqc0rMJsm2eLHLngRgytaRry7GtPEs5k\nEPzKLb4IzUud4aHQuqMS48KrQWjqCoEMqJC+/cyg0GMCPX8DoZ9NTjThi3KQ0Zm7ccl0zBlw3HJO\n4qeihfn5PUbsuXiimxdpDSOITExdNX2hgIYo6AHvcXqMa/5Srf1HuJLKLN77iqK19L2yGGkfG4cT\nPp+WIn1zd33WLqzGEEGFwucN4QrfZT0Mk0WseahDZbW80vLs1NuEfK2AfMYWc+gVKQjjNjUOEeA9\nEL0nVCajyreQL1X77MQ/Z3f7MKXlMZIKZ9st9Pqja1Wqt63i3HjrSEDh1cr7EQru3+zBo7gAIJNr\n9GzPVfhPzNmlRJyLd29w63i3/hPgjFiRB2yI01ijIow79xNLQev0WpGBJKnLZIkIGQdHfPjySCPp\nLNOOluCTX9RiV7C2yt65IAYwEE3Rmu0QeEMTSJr8M6cwP8mkQHG7TC26sVsjzhaVJ31m5gOTplWS\neyBIdXbYZgIWt1obgM5qbXkjN05FCv5jjW3R13d0x6cAu0lu1EIU8Otrn3d7K7abyyOqc6fFOCWC\nFarr8sTVDJSYHojX+adnx0hjaUrcMBbGBTKORHKWrTFaDAPouT+Wyu7oCi+Hh5VqU+mZe/qB7Kxj\nlgqWgjbbdcxQ8ViVvicBe5q/Ovu9OX/S/BryWWNVpNVVPrNNP7Ud6AruH/fVFpmbyTL55m/dllDf\nEsoSG4IV4Iq8y+AEYbXrUUN6PUiM0B/GGx4FWgf8LDcPntO8P7KQcTV6F6MLG/Me/gsMqJg9cTka\nGebbtdVE3YGk4XTN1vGthwkfPh1Bj6hbaXmcvd1KVqWndHf7ySukioyKHVdLKfaleKZQjgYrFC3+\nk9M5UF8iyFNdxOHcn2vCBKWVc1I2pd6ZMR0eYCpW3Bl+UUc551rT4YjvRrmtgQDJa6pyO3YU8u8d\n4WmETh5BlAaqkEDHrICLy8G5Yep8lSuyYflQRyJlV2xhgVqOUJTgtQij9t35ogixJNN+XdeAvnZN\nYp/xoGGboGv2dQbh1AB6/hISTyoeoxiUiY8Nc+wJ43jxi7Zof2SnRGiGZO+DEU5xvGRXl2Ws30bG\nF6+Am3Fvx6BC8+k+3uh9EM9dWQfSBMnHdb3idchTHaECxrWgQ6YbLbIwFuEO5ZH79Vq0tBc5et4I\nGX9TavQlby9lMDPpsiWQoFMzvCBc3iZ+lZJau9LWocl+f/9BM5rtOdI0HmACQiXtU54IhGtfHCn8\navgoEX6YeYOtrL13mkeqZNMTwp9lDG2/ChB8jfBoeD2759DTTH3o0cL9Sf5OTcuPA3V6/lQNTJTO\nF17UEFBwpnizy/n8XdzKpjU+gDcJsRcp/WGYombRXjSxfOEcYeRGaNBkgmqcV6xbHB9voCeSyNZQ\n3NYbjLsDuHnQ5i0saD+Yo1ryDiGFJoetyr6nXA1l8onA/40QGdAL14rfQV6HmaKHRVYCsF5tQoxH\nG29OdGuI0EVOUfIt+T29zFbaLde+rv8aqiogYctNjvILupJVMCrUy3eB1cYL1r4cE8vDpaIrVw3S\nlXsgoXh2LK7PC3REaCHJDLS9oq0Nxu43MiAuaSZ6DZp0U5rHH4DcUGKGK4LxiKC1fKZB2YXk8CXg\n4JmMulWsBZyVc1Hs2STEooc5NEZRynFPyNx6sPwUKpBlwvxgPIz8ashYeArr7pgtazIlQCV8RsbB\no3WNCfSTrHDscYbNhNGSN15ujTXyZIxf0xmw1NxhW4VE0LbVbU4Q9muynFksh/f+O3sz79eTs2Wk\ncj94qweFDzzDSKfo+fYFxr35zCg/FefHqD9FPNrkArUiafPmFRWLGkm6SWycHTHW2dmOUxqBLDnS\nKOU4i53LrnwJtNlnnNbR9vCnTV3HZkrvTaGD1GJiRzC/es+XDUFHEb7YDM8JUKlRbU33uV+CnXcq\nE5Afnqcfch6xTfp4W24eBeAxeKZEXYdjLxisOYvQ03BbLnt/ao+HyqjiaVos86B9Z8guiTv7Y7vm\nU0QBEPyFWR0ehm2yrjUy2ZOjpN+dN8ptlOpi+8jkgisg6gYT2U8e1S2pPCrAtZwj51rEayRg6gp+\nfZ1+HBHDLTW++YMQshPGSEXZMzn40VO97CNjgrh8ovSvROZzPoujNet0XF4Xl+0pRfUzN08GGTzc\nCDNZWKvs7QQNI0+Jzy3TOqD5OoFWQbRf3ETptGJEjsxTG4xPlNBT393qN4TMLuz9Lu1DCUKN/auR\nkZ2FO6X5bGfE7IJXmo05JK9M+NQ17wS6A/rJrHFTFQG3i3U1xyCqWFjTpJJamaXa8Ap24WYvz6dc\n098Zr90dPEFqCDwe6hxyVvY5RfffPzDqQb5DMiiFBA0+l1lXQ6msvQO0/PjN67FDr+p4RuZxhV6p\nTCZm4lrQ47Q5/Asnv2QX7XT23yACOPXvT5VII5iJx66cZDW8PqcokaLa+pAtVqbgZDPxZD1C4NXw\nAoObbkqulKoJobs7EjZSIpKQqr5GCZ3QjgDDwPruhevdnzONX5uBvI19+JYqusyuR333F376uyvK\nn6F+d/zNdvSAV3gIz9JaPPEhjbKgsUOFhdyDoaXdydwVHrAB1SkIhNzpfNl62QU0h9m1rX0tPNdt\nUnlnjJPMTjVt7hS8vJhfgtk+39dFB37FS3rVDWUD/97MlcR8z6MEGzbLsGSRtQgzQXSzXL4ruX2E\n7F8oaVsrywznJGiEc+2zzA1QekJQuy5dxS2hvHftZoajaCqWhhrACvQAE5HTIr8etonzlt70MhBX\nR4L2Kdszs+cuKe7YCn41vp6yn+jkXCpOzLOekgT30vVB2cScqwhXUnoA4eD5oeMK/VvSG8OomIto\nmaCJiv0wLgJ7kJsprJEeL16mqTkMwmvay2FtiWlIWbKIs9hgg5RqP5ftklAYWiA/4wg9CMMoH2hp\nuZ1nni2cWWGynf2ne0XC1qDqennT2JyNAQtk9Jw0eXHvjVLarN4YgyFvFTr0C5rV9472azo3UE8A\ndbhgNUf94/74joOWhz9K0BX6hu6u9am3nZfHjzT8iT3pq3MtSlLDx/+vqR09j1sBXhBoyiyASoio\nhAQyBIlf137OHYUONIvyzXe1M6PgVDfdvFr6g7VVEpVZDeSgkN1SXdnbZwYBVLOYe3JTzPfiCNmw\nPL+c0DJ8OwN91pieUcftyhX8/4nraUP0jfbmoqYneAn2aizdgj+uYZDayM1DDIqG7HkWgfoTyOux\nFto6L/LvFuzFDe+ipcLHg/txvv/oK16fIF31ETqIDIKRU1LBbQAbPUwEZxC+TEnpkcr6oVT0hwHN\nJuTLW8ZHgsVNC5YQaLbTIU0uVZ2AYfXpD5jXx2DHxpFmqpwAA10PEvjjBwEXurS92XYW6Vlh3vag\nh8071PI4Y8h0dlx5dPI/VyJA5MsaecCPh9Wc3Mu9ju7CmJzmdnouyGW49lVc7T+BFgn8vY84W4Jy\n0EOJqxtbldn/b0RL9qNfkmndlxOOYUGpkoTDXOeKNtd7HyleHoQUnqsrJltt7n1TUWyBkUSvmr2e\nhIco9V0pfGLnQmBrcS8ESf7JoDfid3dd9xhfTYd7x95o4BpLRW9VbAnUv/qzO2Ql4PsXD4elhlqQ\nIX/zvEAslyulqRlaIojF5lfyR5gs5T3XDgy9J3wvtzGMB2e/OdhArVKDlyiGKVBCwObJBltJLdrm\nqQtoqvfdCn+V9EPh8P1tILiKhp/pxpNcMLi4F54Ss1mMT6eOjdsUUk2NgxCMXJ9DCe3Vzm8uyZL7\ngcN4jfAg3E1rqk3m/i6KHng7yyFwHWIWhDG1pdVdgHnmaVWwnYivlzpB/S7eNw4unSB3dd2BlnzG\nRb5PE2fCqQmV6WZPnzyEbQbON8IXydg2GwqhVl7d+KhVvB9u2DtRSUwccaSTmzQitYkii0ktito/\nOZn5ZAWREOagH6xk2jSJtB+raBOlZD/StDmobLXWmpcaSlaEkDEyTAMr+crVbeg3vAGSoSOK9IbG\nhEMMVUnbYc1PtZV+vY21I6ppYt5T/zHwORuaK4UahSEs+tc11E84gYKfibx4zaxbrR6PIWoRhFpx\nfygJGI82fQqpK8rIAfb84Z6eXjnfx8vNe3ePHTI9pkZghZ1vx44M7VPJerWd7U5zd1C45avIo7bJ\n7u6tesU5+cplrvIG+231DuhICa8DH9UF72c/JWk3FiHDqhpde5ScS3IcWx1hhrKBvi5FXoH10veQ\nlHicTS5ZPF03XuljrC096UTByid0LNhm3MEYNMhJHDAg//PphATDzK9kPRVEqWJNnUXtQxCtfaGv\nDDm9ZwguZj9gqtu4FYLLYUIYBSERRP0P3uA20WOHJw+chMy+nL/5NJ5IbO3bDpRrULtw20tfYeXd\nMEZRrVydMWKNjYU3WDHTREgJjguTG/o0uckR8jUjDqND8/aBClo3a38CpFmPcWL6ws4xn7mPX0eQ\ndm04/XpCC8K8rCxBby0gOx53dNfuWePoTZANSnjGGiUI5BxmFdAWSo6va4tcRBNNZMPM97o0kVhv\nEPnfc3/sGE1x3k8/zSHbDc8HaQOXTo9W3rmPsM1cLrN9t27Iox3uo8H8MKqn1YcA0ilt5LAjrSV+\ntUKxL0hO5/r4sVSAigD8X48thLABHsoJPxsvEF8LqbeF6ar28+m3HKCwEkXmuDsb2D9EH9UPETzk\noU7Zlu+cBilAsNow3MhIVGRoQMJ90wjs5tMHHN0coijGoZTA0lcU/s6NGNC2TOBj1w5bSDX8FKiM\nS07TxyW3rw6YTaoFIbD66Rq/NSP/31Z3DELdKtPR9xDQKSDKf8jWDeUMJczhi6nWPBQbN7UQtmrO\nLkeWuAHdvStParHRMDHlyl76hJKPEZy48fg9N9UdnO+Pd1Ald+lem+PCsHHf+OqbXStJyJ7sNQPS\njKJNQgifRKxMJxi0ijJ0y77hsBxInqwKBywtcfVKlXs5gwB5+HzKqctr1bzPf+oUVROtD4s7C8n8\nPRAVBiiazwsrGoCKpXRTQdmcPIWk5o/ljibexkeIJdZGOflQLAG79TkQP4VR589A9TEHqrbDA8Ow\niEvue5OjEfXk8v35rM5k036b2nWDRQjwgH6Ww3B4Lm4ynLAYQGTB96U9XWkAnWLiLp5m8zvFZdDi\nE+meA0JkE6eMo9xpSCwtthR9qC/ZN+oxyhOIxOtsuOB79uBllrVRyxq5F8q9Jv+a7IKcvLMc3+Sk\nZmbgOAgVLYMQnsj7C+GgRoA181qNGBLLADnDESGgJ/3VlMRVMiOvVQ+AWmMuns4aRjO7TJj0T4gj\nOtQxN5mRSOWygf4wDNFbjjzdk9Wrb+YtBxxP67a1DBY73E4f8rq4GAGOc+uA+vYPxN2cpzQMxn67\ntST3yTFSN0HU+TLzADeDsR9fli+VCAO40pjEmfvnmz8uX4ieAh1/bmsrpCB4hddDi4K7Pm6hCPVZ\nlNMu2yUJ2Gv7pSfim/c6uDmTOvuyKRHsEtHBss9V0SHiF7zsCw9jC1Gw1Z3hAWIEE9MWxlQFYCc/\nOJl2e+2sT7p7D6B+NL5udUm7nX8gB74q1PUFWPsGYpD2pu3lCBVsQcSipoVTozPzXTMu9GhiBbtD\nKMVzVgZKLQb85zYLEfk9esGkaaAa/IMlXBYyZ3KgxHNEQVVYLd/28z6Bgq4z92uZ+nUjAQQNhNbd\nihUSeLisI8jS+p0o5SqzysX2BhJTA73Dl1qC80tYYxi+Dgt6Ix5T5JgkBeZt5XKSBj+tWhDWKCDx\n6uUFw/ci6OktwfqL5KZVOMkEwPLWW0W3S4EwFRv/nqulclXjxaiEmI1qy2g3i4xu4ozAzfvuY4PX\n4TNsbHRGXKHnbUq3OX7WWl0FoO0CnTw7uzXYj3goIj+2ppauZVSQt3oGFMco07p5c7AG791rM2wx\n+pZL5s5qBaL9pScdRgmtmuslKlqootc7gQJ5OxR6mvoMhOnphhgyojQnOr+SJEtDMMD5rHlXoSgW\nUJGwt8q/XT7s+tAVwEfFZwcio0IPbQNDOOsdHChnWoWh82tTu2wWSgR7Kg3fahsm6lpYDnkid7j5\nkTGihYKRKRkvpg2Ws63TmPYjpdul3WC+b4ZOhk6v3C1IdjpjOJ5UG4l9tMkYVfoW7y024BquSO5/\nMPPdTM2nWYdjbgO42K4Zxv4zLj2NSkWZm3pkgJP8LOnt+bV9C5AceuFe2YEcYfHP2NnzCbPkW3DX\n7OB2UfViC3Mm7S4KKuGfnRC4dEAlRwcrCwYneuiP6uS0A1MNUvCnPn8WEs3qpVOweX2aJkYS5ur/\nR1bloUhVQUshGkVfjwbVCpNKA1Z9uzEmBMAoQ7XvphL37Gw4A6IF6IP0hE2sLueqpM8yW6YP/n2m\nThOWH112SQ7B6Cl1xkrSYRy2fRhCPLiOb/AIOrOXBfO7Htq4hRh8mLjn9tsBdxQiCauhjPtftHqA\nbnkLa4np5WOkVect6L/DVTK0V5YtCK3SVmMRX5+n/iH5KjTBdbJDG5zE1+cZIZUf1jHOQT1zGeYb\nPcdKviHtuX/dxA/zR96YYgE+6kvpWexwOMkvDnMeZrFWV3YA2Q4yzl1IMz7mxXAYg+xr1XhyQAHh\nbvAoPX1ZX/f/hT0d5tm7H0+hzJGpOMNmOb9uWoxbURr1oTe7Aub9LGHM7MeHGjRy0eeNA4l9a3ZY\nWaNVI8NHq1/gTMRD2P454oSx+FPyBOny6Sx3+WAXKWV4raTpFUBs/OkARVapcvZtqOP0JQyWm7PT\nCLXQurpYYnK+M5sJwh9q8N5Ymi5B7RVWKXSw3bTt5UpCMFF8w3wqLBnB20ai9FBNCmCWLZmqK1BW\nOT5Z9SWGsFad4wD/ykn7EphW/XOoLWY4gWTRReb8kUiyK4uYq3GdyedGWQMQubbwsw4Yf9XLQOCA\nveyvPmR0nXWIDyie/P517DyAPPR3QSsQaXWL6OwedlZe9/pJZvpyVuCkMvohDO0OiZBnKhw8c6g7\nQDxVJpr+PzuscPWWNvWsRleF9CtP6o3lVCPYofb5eni3/gew6UuMOOPdq96vjfol+ipMOitig/EK\n5KSSJc4ignVV1rpPdS8jKt1uRzdiIG04lIgKV/iTrGxulwFTYWn0YXZ70j00M7akJBpgtHYtEwg7\ntuFwF87SDt98jOPD/WHKwoeleWTKwDzN8dUG6rIIjciM7ttKAupuKB8zcngy2+VEd8SJsoOuiVXv\nI1jEkJzWfyF9h+BgpXXoFGfSUjm4PqBwqBTsya3TbfnxMusFwVAmhcgkODyoaBE2aPevUBLTPEyg\noXiZdFn96TTFBTSKxfbvfoWmBfJLQG+IUMH6XUArLaDvPsOewnpCrh+xOPs2VUJvRJlbOoQA8hhc\nBYFw9C/vaE8JPImPCF8Mcml3atuzrH8J+M55leKZ+Ahyde17lDJYmLaTtLVQgqkyaZyHgYJabqrL\nfvxMvqW5F5ysEsk4uLDBFDd26mKkWfaYPU1SQDCVe5TX6ZCrMoOF7QT3xo/dGRKOrgxhF80rEBSA\npbHEX09kRVpK/s7dJePfIDBOH4wslJSyr+cpQWARs1LDsRdJqfBnbx5MEQ4E2qk0F1V6P0Uu3APK\nPs8KsBhcdUXgUqbGbsEQmLHNmMsW9PItMgYMqBKVjCWjmnu7XFM+2WPGuA22GFgbq/HHjTvb4+a/\nhNHFvP4EGDou4Pq063a7EtIFFh0VzxeE8It65f8GizD4Z/YaE5NBdVql7NOdDECr3l5vqCI3HnNC\nrd00HANISl5oyA2MuYTQR+GQaXrKUzZ0cDbvQZ7P2epot1a+MCmRzUKtgRQlP3GEAOvl/z6jyNGl\n0i9gClFCTubmketbUNA8oLzc5tOCpMdeyfZX7wq1Mj84m63g4WECc1S400lGBZhiUvaRIgsEnvQo\n0/oWeneHemIMitJgnp4Mf5PvMfKmyud8ED+o05VrGt2n1P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protect end_protected\n", "num_lines": 1219}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\ngazeSTBrENHvbt5mZLx18dRtoyW+Km4t51uVxxH7ZGNnmTTcoKqZyFpOrZ3w8kS9aFoiQlh5unYf\nVMD36zgB+w==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nJaIcYFxN5pqUbzepnqrpmFHdFIYWDYoimv/QCWvvIMmet78lyyCu7OmAbUWaZA7w0zL3MGnfxCUN\nn3vQGmg/2D1qvx/q2zy23sfhZfE87aSbXcNL67XF+GYu6OLKGGPH8rnW6exQAoemSF54SZgfsVR+\nZQSjSgAEtaKfNJS48WA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfa+581mCG4lxTJxvsYAMI+Y0/3DEJVi5IASCLU/HkCRmXkai01uuifj6HPVqiueReLeiWI0bzNp5\nJVlbpO/kKqg9MkQMgg1uBw2FFsg7gfVjpDJV9TVBp9Tm4YsSrWm6yWxzb6uMaHsxRa5Y+E4WUKp7\nkFXmUM1qfaMPGyGNdQg20KAvKFwwN0302/mi6GDcLvLNvvne93tcew0yQIxg/gqJlcURIlak/g5o\ntVj030iWkuj/kKp5guYfq3gEFKVEr4SV1BC/f5KX961SkhTxXGKLNLPd//Gm7akdx9a4SnpGY1Jj\ndKETnZJbnXtrvqcZUh2N1o7nl+YTs0mjObgM4A==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nQPlIuDrSSApp/O5dvtKOql3r2+lVEipJtAA3M9T5a18Cd2E2LeOe6u54LQRqvqSgFUElg4Mk3hH/\nGPHlO6wLGkc68a2QHrQWBA8YylrYUj+OZbum9kUQm5R3TPU5Wchw/mhpqWpgPlWvyK/cO9FxrB5n\nHD5ZuDk7iJeShjEmKewIRdMZqkkvQahMZk1eJ8aT2jahULqIomSMODM8v16Cxv6S3q0ohUtT2DVH\nwOkY6nsqo58T1MDDOffgorFUWVqkQwGQ/maDu/KENCo/JCJZOAmODbmBfBAsXvg7bqGZKB9VPp6h\nTMfEboGK0PjL8yhECxqeqwtqHk+eixHOqSANVQ==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nb4dHNcYwRRv3ODYilIe7aZan8VP5sGFpEcM4Sk9B84EsHlTRadyHodV0BfhfsPQB7kezG88HW5h6\nWNkuMny+KpZj54uRmnCQmrVIyZTZC+1+fpR1i46q7pc1ZFH0ByfdNqY/66Ew72bJ3bqt98VUJ+b1\nKDNSnYmqrLKj6TtcYAc=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUFVtDvwzUgfeTJK5RQPCu5bEQXOVNdg/Ctt3LMq1WwNKEczcihJ2sl86P3NdRo0ERI8ueQtux6aa\neHgbxrha+qncx9ha9CjfRUqPzzsOn3Y7i1ixq84ynt9jVyhbj9UUv8UyPbi4K5iayWqESAXrtTyL\n4izB0qPIWl4//8zsVriy5QoAxHYuCOVTFT74KhP0GfBhGq8gl2pE4gyETTs/8CEabnJ3ERkaoy22\nqOEPUjVTsxS8vgRq8tS716SKeECQKpsy4XCSTfx1d1knluz73QztnOOUXoIisTy9nHoSAbC1cRDx\n3ja7kCl2MkDQsfmBWkq0ozzVuY4qo/oIb33DVw==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nYC06/kx9685ntAX7i3acgvLk/EwgC2VW4WVhE+P9S0QST/y6VSJ0oBWMmzsdOs5O1+nblcA3DkpX\niLfXgmvlzh61Du6yn0zIyDDTLrMYWINvRbXV5FG9pLM3G/U+6fTbBV97iUYMHPWk0A2DdkXIWMP3\nmcLuMBQc2y0dm038tnqa7fuMeTcvxPhQ4wTWwHXvp54ejwq4bTAhNgyJeExmEzOvR+zWXm2VgpLp\nqcMFWAA6nlUIG5ZF4M15/u9UyutQPOLlX5+QPwfoMVi/kyC+JK5AUrviJ1QU+rzwvU3tw3rXqAgE\nsMTi8fHZ/Nt42HIXty0cXb5zEQDuP6pPBNW6XA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nHg7KeQWoQfRjpmFIAWAFbtestpXMcHBDYTZuLUSbL+kKuRGBZWT+FXknqinVcx0pJ+q5acUTBtyX\n7dcJkS4qdpYpoaBETZeL/wcOfYFz/CcO2z0+LWoGRDW3DzXn1oRWWZyJwgJkigyMIHPH5qxsjDO6\nJPKj81fkKJMHi/vC0LbmZMiKSmWL7sQNeQyH9Dn6VLxtXovGL9yVh0SoMlG0/v81wA1TX/bXmqKJ\neUvzBU070O5AHkn3Z9WRSK5S2L7x/k+ltWDFho5jtXYcevcbA/14blQqT6/9PetAyFmzvbIS+6Sy\ncJ54zu+VswtKtSOWyzlOnfx1Jgt9q/yLpCG10A==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nn/U5obQaKe7e57D8Mwxo0WeDlQ4fxz4sWCrMViskbh2tk4bDpeUf1ENBUputMkID5xX5gqlPeFYH\n/lod/5hBiFEecXymoK17ADl/jmNo1MjfVQ/nqN6xaJWL8VqmPoJ2XUvVt/nh5gTeI6QOH0BkigMy\npLFieK53VJ/5XRJXmLUeyAKMuQYF3FZPQdvCn1NDG/xTrxv61UqQKbL35Q6DuG8ZqHIJKSJFVln1\nchCHgEOHDKo7nJ9MCjYRgwBWPGvr+w4IgHNPDhatfWTGz3wjSXmjYynT7/3ZWqR/d7FCLN+lZ/ht\nr87GH/juUmy47PmZd6QhKuuc19/j3eDrwcHg8g==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25472)\n`pragma protect data_block\nrVD/wL4DHCsEfzFEf1VoQTKecFocJw604Tk0NgO7M3ODm6t/6/biD0QPzz/Fzy1UxKBEqQ8Nxpt0\nkd5dp5nyCwOVRYlAXNcBHWyWuF3ImZ0fp1y2c4napTVULuw+XU5nSbEmfo3EFsLjHWHYarc33XNE\neccwGpgfFccdUa90fp+q6imfJMIuCWHWowLNMDGdb8ZqNKZUIE8ob6W2adzfUxW6BcwKDMhYtONy\nphGaaPcir/7ub5AXgPuxZ+H/dTq9wgn1aTqOJAp1ucnPzVq3IUtg1OC2yU2vi0qMrGvEVqZa5al3\nShGeBdw/lrrv+XpB0FfkT2KARuuSvzee9a4oDMMvB9rD6SluK40ECZ1+yy9NV8VPy1Z2E7wjjpHJ\nomuIJmTDG6P4NMgl9qjKSn4GSHvEJtg8Hs/pMVAdAds6SMK+O9p7rBsB9TJ+Jfe+EKBicHLzhqUf\nYcNZCfyCtkGAWU7HcdbTu9BHbBM7GuhixBjPG1gZBzSE0WtB6MGt0YXj5LC9B2B4gUc+LuNxNcc9\nUKE7AQ6OnNorwxgTIT1j4f2lTdDpN7naMjcc0dFrzhwLEt7EYhpH25Cb1lTtbt3ny3KVcWNrvcLk\nv09yJ3wThnjJnQl+GUiERUgWu8ROGl8TiZbUBs5yecOS/BsLolr6ykQh3uUot6ZrpLggo7e2zZy4\n3svfbA7sVv+IfBOnba21zodL6jR5Io/8RZ9dAtTSxEkwNKn6woPbXr0vzkNOcXmNshPgXMNfn7kP\nhh71P3gVjrM1Z4XR2k5FHBKIFP7xvG46B9zLPPSpe9cKzJ4DSqgt0aNr031h/E4RKIrUZmmfW0JP\nOP5eFKLhkwM5x+n5EaEHSfUgoGX++y4UkfnBJWjFbVIWdkTMzBCFia7/hFiP4k87QX08uk84BfEf\nsgKGgULddxVYXIDV7mrWaO9Cy6yLEYGh6+7ZOBVM7Zy6cqp9LP7Kc0FPdoy8x9BVG6p/reTiiw1v\nNn3v32uEnt3XP6T+LoaKu/6mrF1npJimdRr7SstYkFy0LoyzKWhUHUz/VQ3iwILTJ0JnGP770FqV\nmvyHmvHBk6MZTTlNhtcVSTTwbM0lw0LvHbExAUCD9Laa09kQXtQstGMFqjckEvN2jqCALunjsEkp\nBQy8rtux02oSB0O2baktMwI571Rh+4HmnparL2+x49hG7tthybchylTgZbFDHKBCvdQBZkzVuo3Q\nj7Y3oKUrm2bmuJSbom1St7TbGFQq8d0b0kTXHL3I2ohjaio0dcvYDfVg+yWz93shEUO3Jy4PUuCC\nxhV2WTmsBi64HHIJgemiKEoZqO3e18N4F8cdUteag8hQdvF+6ZlNnZ/ms6TH575Di4UiksGkL0FR\n3sJm4AQ9V6tp6J/S+c+1flwE89qo+Xsg1/cG+L8vSsQxqyAk/ovRsYwYHiS7Yy4/606czKjJjQLN\n/Od4Z/RzSCDTe9OkRgKnHt5zK3yQjI9keM6uYHLPJND8bpBNdWrqOdAkXjDHjM3I9U6L2JJqeXVK\njIP4ArCrIq1ZHjpvCnFaxB+/+BBdYcUPUm1A5us5vUT7+x9nSm5EoMOVcMVFqrdJ27v3WAGi6+E4\nKO2C+XigT9fiGzmzXlKKtsTeS9pPq+XJ+3ohj5rZIoPhbrKxWjCzmpLqwAJ0gNd1WFfrHgE2LOe/\nH0ryLItmrp8oOSGEdzqkIi3IjIWzEJsFuNK57sg85CLkLBrD/2GAE829x/TXqmIJN9TXeNtV2gKP\nzoR4NFQendQZY0s22N8NsE4Y00GMNZhaQdHbxhimdXjmLk0d7qaq06rLRbHcsoP5Sq1QJlF2K1qR\nCGKoiuDSQoQ4Ys7EOeerLV2n/FRB2yqoN8xeHjway1HTDoAPAet9wYutlxLTBUccGt+zU65u6OaV\ns1H2YlNFqtwE716Dp39IzGvOD4w6IjA/vBYiXj/dOVHbBBfQr0u5i5m07Mu8+ql9fOGoJP2wqBln\neGByChXLhb4uLoe6Bht9vwf98nzSbRmiaYLyALBXHgZKs5L5Udkanozr2NM301M2pzP8QIPa2aQb\n64OnBA4icxCxWwz320VkF/K5BM1ObCLOipn/07v1naPYJx/9aT/ZVupp+QL9cBnPp8LZtldMFsxi\nZojdTH/u0pOw8jx+SH84VqjOEloFoTxTXkAMHKRulU7yj7ZmWlEviMhxT+f63SOqtMW6bd8ndq86\nbFiDcjGNkZC4YUerGzbOM6M+me6Qe5RcwL5VJARilQoyPMlPtvzSwMzUJQyUmabaCEispxMMZ3QX\ndNb4c+W7FDY4fxsytOmuPwhCZS3ytA1vCB92ukP2KVeOien0DKc4mIwjdBllzW9+QN+GNSzRe5LN\n/YyvlmAWUmlNSB8smtrpmB84JVKlWaXOOrpOLxRHtFaYpnmpmXJcNveKAB4LMvGTHJdEDlR6LZ5n\nCgWcU34eHvwxJ0N7D9kxlxL15EDsPFjxeT/vykJmOvcwVPmia0M2nwFaolKZW5cm0pZvf3bzkkBt\nkxFF4vDu3VKJBPN1qqR6ngJ8w5cII2VcSG+TZBxeAg/XH5mW1JuetQkNdLK940Rk85qvx9Z5tYFu\nFKrDM/P9zlRri+ggEpi73JzEUnuwXVzjIe4bn+BCJz+SYBKbr3OlasPo2GXinaCm5ZjGwKSqBbnw\nJNQvpJstSIPLThwNEK3IT7qyWtVrGoCDNiYO4H+x3es6P4VqLqh4r/0++vkRSTM4Ov8V4lO1aK+/\na/Wba1G4sbX+xCKKd66y0Rr3rr77pOo7IC0W9booS++rNRLvt64SbPyun/PqLmZi9rwotRAJRA4k\n7TXOcgtq4Ki6pKRKU7oKP5pQXRmGEVr/qGRqcX/IFcGkvR76WQxcFoASm0Yj/3Xu7bvEHJDX02tK\n4cAJxbC+4JkeI2Yc4e6V27wCtFNv8VAnJEAIJxM8w8Y+uK3Wdth00+HnMr/teyh9PAFI23BCDQ8k\nP3/TGEk+2X9AelM3jnJ1cx55xK7Y/PsWkiPKyUozhHYOyR4SaETBIxAtZ3ttpyHm7JPgipayDsI8\n7gYw9SePFZFjYEZhCtfrBAzTmKhxEJ4BYA2Yq5/1Djk3dqr1Y7XDyyIaLjVim9C05XBvKk/3JjmK\no/4wBHIRPWEui8ORGTOUvziQUj+FDTHjthpKosRq4PYd0gugZGbbhdlEj9IDDCDNxkVM9Xyk3ytf\nEqvvgLtYOih3D2Pq4LqFEqHahfAKS8ugstEsKmEWOeBnP50FSppoksT7QdPuZ9PWlAatvnkJv763\n5BXALS8jMNlPIJvelWHd2qCx6OhCgLmUmRPNd7LCMMydqv2c9uA7voFh6jp9JGAvPu53dzjWz83r\ncFeBSw11OeeiKRsJaiHddsq8L7nMEeMcZshhvcS5y26j+2tp1zr6sVBFicGgokYH1CKTQFIpiTib\nXPL5vAVDlvFDdaC5VNkFNCs76Bou5yWCTAwG2DcN88BLMV7QS7M/iGZSbCw8JV01LKDRqeheVsxP\njaLYS5XkKHDpYtsCzcVvCn6u+nDFLOLhz20cYL4vxwmt1pMKikYG15ONmScVDm5/xQBKe7nWsOKz\nSN1w6zj36KQ/C80gFY0GXtFZkG2CqAMt0M3uDfWx3VKuW6ObJNUb3R0TpZri4OwLbrrUpL5UT8yt\nITdov+Beft7qZpxoMu9KLHhncLx4TJH0gBzyTVfAPg4ljeaBsL7cmVfDmZ1PxNBQWN2/Ms5XhA42\nF3BDbS8YdOU8JUxHPgD9tCaXHqmt/co4uhm7Qtmm+DeDE3O6ljX5zbblXhS0345LHi4MFfhCkb81\nJ5XdY0hze86Ye/grd4KM1+hLV49/08mXyM5oQSWFRPGDY5ivO4n9anEwslLWZ2OKFvXtW0ZjW0tT\nRXEjOIOyE8jyr36AQDMI1LnOl15xPMnKxb/u3VpCatxnNlgTk/jzmFAD36PDOdzIPJr58KDGvKFS\nG18BSpcfrx+8cPWzVMM9M9Xk88D3Mxb+hWAv6UC/efp1x3+Hvihd9zDuubo8/FLjegZC0fa3een9\ndOTgEIsRfcfWWWdtQEDcPKuUn7WhoHt0SvpvO5dTcLaAmCPwcROmaH0teqy1XjMnZYp+sKIWZe7h\naa/hTWP68T4UHeFB8IDD9md4MZDlB/L2ac5XlcVY7UmN/GXG3pc7Gbc6uN0CzGUQcYa/v04G+11h\nT8nRzZQJdZlq0lH1U8k7gR7YudvLKtUfLHu1xmyJshSEKbRWUUdGRnwfJUm+3jGXNSoyoDu4eVa0\nmvh2E9+h8tpc6Hdxbe0/dRAb6sSYseeMuPA07z/+SsPa5oJMBS4zBtxgDX7xBkPmnOmMnJAKzWdI\n2/zXRzhP8OaEODsQLJm6++pIgkkHCqOGr6GeXrHTdMP3idL7UslwV4Lad1r2Y9+61kW7fcGSJ1KP\nG39vh0sAfFWWeb9d5TVQgwz+KIoe74xDJPYPPSkVl5kx3YFKk6vty4CYAB+5DVSd9bLaBnJ4/6l1\nJ76KqFbRsqIPDPWm7OcGTLW7JIMmU/Ofpv4nidkb4LPNVbPMfVS+Z32QG6FXVhOpIqgiKe8BfVka\nxk1jg5/fA0RQ/P5VlZhWUzEHywD2+khTh9xwSLldzJ30El7YZ++yRrsgkGW93hRzZdx/r1YMGGS/\nQBmRuRM3FKMkS0svshNKaNg8DySBg+q2X6Ky9IjA3dznU49GnthwMKhx58ThDxQ+szVA0MrLc0o9\n+rEmk+wXvMx1gpwkFLsJocOcBtoyq3atxI33E/X4g0N1mdf0f7XCxqKCPRyQfjfDQQv222kEzPfK\no/j6pJzL/bq2QCtQD62ViO655dAFs1zzuPSuwrN0eWO5sKLw4bi9ekjxE61AGmPACWDjdfaFWJ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dNrJi4eDjTX7egADR1lPi7IHJnaNzULLyzuO3tY20xdNoS1WZ9Cd6zJ3177q62zFD9IqW5Lu\nqwbBMBn9Srz8L15/PmeO818lgnRA+Obqkway5NlS5ktpFQ+pamj3jyYU+gi61IJh4yOrdmG+0YNr\nYFfUfUywA+Vb0DyVlm6VO+PiHnezjyvHEOcYEa8umdPJ9zJG7DIv0F2B2RqLChYKcamD2eAeDTbH\nfV0/YaWwv1GhQ+Ao8z4mbGlH71ah+UI4VMNU5k94werdUcmCZDFEnscd9SO86QRSF05j+ffi1CCi\nv+ySBxYK9APjuLQjNVrNKkjo3sgO/wtZFTimlVD9eKKZO3oJ+8ImII4d0IrCjHSBC0BNLtUvbme9\nmUJX8cvZmqs02dF+ATX/gcguP3DCUJDAUSvbg94oU5zILWF5KshRjRmpg3/63m3Mqua565kXaXW0\nqSB075zLeZeUTxd874xUJdwhzrCH1TkgjtNBULzc+e1zgGneUDlKpF7+GM3E4g2yPDntlKDSV4tq\nZg/J9yLjn1WZ+g3OXJp3EuqNpixt4tWc7g4zpFD+6PkEQHyikmzegOPhSHkmz2B78XcqHnVlVRT6\nu+h8+OajG4S+2zUQ2+y9ii2QR22KHBEnoriSV0FkkgCt9aEB2YKRRKtPBMXtQpeLYxm70Z3gLSUA\nW29k0A/vnaVEOuEOlY/jqfFKbKb1K4q9aVjX+++COWTPhV5kly9w8ujzb69MbaQWfX7p+PvJCGyF\nTwCS/7D3fUAjuzGmkdfDhZccW80v40olYz+LXAUl7tUuByKyy15G+0BKB5YEi6hGFv6lEz3GSGxe\n8/uUmYAPkJ1u1STOydIjaaYXqD83ZO/ZOVEKqhVutfVl2hSHLzYw6/gUFpFcMwZWXX5eOGNLl2/T\nFF4MzK6u9+0KXGdOAvATi0btUYD6QYMM1f5b1kBWZjJcC1//GBYKhkVUuwduwTVT6aj/2wzH5gz7\nQ8qEmTw4zYRBtJXQgOs/voolLCe3EfZEyqm2uQ/r1PchYuV1+d7io3uQFszexWSuf/eYepqWnq/v\nz2Gz7GegP8v46bRpzZKV61eoGO59seLhOTjvp7L/gdDO8xjlrHxYtOpMrNrj06dtbzUUacmPBceR\nd/N3VW3ovm04JbtMLrbwXdgY4PIFgeC5ldjlU2bnibhXKkE2/MjYx8B5HonlmJU3YGnjfnMzuVhi\nsfVEj1uJaRWKiNw0ZAITwD1bMfhDZShTe0WQqn6LrI1/UH5oUhqovpbWw70bz+ENp+D4TDwsZS0s\nSpmlHT0fP8DbRP044UI6dumqUBh6K1XNWgERFQD7UXK8EUV+Idp/rnr1NbNDOlaD0+dhG+p4Id+F\niQe8It9F8OXKRtsV/b7VJ70PE+RuIgrdPemrpm67UkBWnBSKixKvX9kJd4ecWPpr0hHeiPZFRA8U\nD+ACqk7FL3Q4yr05PC//O0H2Vym+cbqKruXPHgWLbH9CI9zSMFo/j+Fq7Aq+EDCG58e6G9X+bmFP\nH/5XNkvZhbeggLK+WQr8H9GQIZLZMQCboRvhX9u+eUuhUUvRU9gwFbtDrSz8K8kJBMzb8blG5UwM\nC2N2y41I2+paR+I2m5hEXkKM9tXl7VclIQIsYF6NoNH3ncc1x4HOPwxgUUR36L2amu/bzBn8MXVJ\nftczkKFdZiYMB5xIcDLovipakJFSH/w2xu6WVXWMOiA5kvgUvu+hbbVi6sHkQNFHYKIAjobH3q+3\nDrc09phW+ROYO+aTcQbKrIjZd71OhsV5rzwZ2JQ7ki7NSzGWrG6x8vZodBDEMCl2MIjkqJ+PHIov\ngo1cRx+oS/5Dae9iXLZjx04CKFNUWUSPyHHrfbNDyOPrdvGCTFr/67j/rGj1J8vVNCxtLm1bEQpc\nSIhvaUaLDRXNEjLHerJ79+3XQHd7IqCcBLemBhPmU+/fiAWJozadBEb+HGZqlMPDNzwkut2l43PB\n24M9Sj7odg/0kwUb+nkDDFoZdwlMwRh+gKg8uvy1/fK1j0sJaMju2Livjx2dKdE1F0GLrtHWI04A\nauTXE9SM5DeEDogTpQeQZPSjlINIteGYpH+oQKh9ZNsv/7z+zVFuvjSsLxXZy0AmwKADhVa+Xh1q\nPOrIzFEtf3FEPdGmEyelpCcZbjgkSf1KggQSt4O4YkgNwswY8tEBLIDAXDQExIjCYv/AIeVtzzzl\n+gKWU0UQjKYMVQCWH9zUlHQz8rQcLCB8EgUlMKDsQVoRJbvQR365CNfAX3W8rMVy4nTztqh7zU8Y\npTMGjwCCnBVie6sRytRY79AmqVpgvBPcuQdAMszg+wqIOS/YOXfWuVWaAHwDpxw6UNFMhWcFKSOH\n05VPD72EbnrzamjHK7JEkayKLgR8VVQaXYvT1jVmwbJ6/f9Gfy8CZaZuJJhKPAbeo8mMHuGWa9HL\nA8hVOZll51JKNbAGr5wPKjPHhfBCcWJqs7VIW00Fms/7xNFGllj/SZtUXSzpO/+2FCnmtjO36lw7\nuBLmHLf7CfjRZYUEgQLNVQA07zta/IkjSnwAojzCOOGiriJKJh6Xxrq7QrpLKKMpwb75V+Bf7UIq\nXCrPo45BCxCLgZ/361L4yE1xbmngU707NlaRF24SuFTe7juhvITEAy3wY6U7A7XsGp1GhBBNaYzx\n63YNFYggmHPw2SyXoCLq+pVuz+tvr1PMqnV3zzb1XvR/5Y4Tsp3bIfi00nNB+tv7WU3mCiKl+KDn\nWulilfdt2qcMkdt7dtmcPpClSu9KfkwSQANc0ehkxDHMf0CT2X361QRvY1BiIqs5wfHnQurPZVvW\nIHViiyTAS3AZ/VOpqQJ9UeATGNz/qAOHlu4l0AAE6xdtAPmQ/ccoAbLOCtCJRlTP4bk+mK/UXsj4\nG5Fs43hzF3JxJ4LR9C2FvUvkNnM4hsoGeWg5/PI3h1hXU7vUZJWEgYReDK1L7mkquUjzkWOBvs/Z\ndZTkag4LuLtNIBkAuT8lMHzT6gfGfl8FX5+8nSILKBx072cjdYwUpvNqyRE2Z/RnolUwJalgqWFb\njwYgWT1LgrAf9zDNpkiBuskNgatldY/dyAyHZ8aoMboKqqPiZMkqJKavv+FSK4leOWqG8/2gaZke\nxNn4gg7BPj+xor4DbD81mH/cZ6YSEZbXxAo5ynx3BpP6mXWX3Q9BVYMbSPDKd5LP/sL+FLO4lhXe\nHGsXA3ZwJficyeFbwqcUF4WXXjftNC8xtQgoYUdMYTmtiO2Wko7wUYf5VzXvf3iAJh6h+ii7bnNk\nQD8LnpXLyWkBAxCxXLS439nKagcl9eGoV9S59YSrP18BCUxHteCTtVutmEwT40IhND3eY4xiK2gJ\n1mJGaWYTHkCq+0qg0+pobyEVhuMvAbp+hax+P5gFIK4xkXaUrJY/rnaXTMMpPlU/ew3xGKHRD6Rn\naz43KtCgy0a0LgYTDuQkkWgfEbeC3Qc3rv1tAYrQoiVSwPN1Ppmyb500ZaLxhfGyslQtV6Cj8IKf\ncHcbEG1SU/vgXR+I/iJitzfGYck2dBP6Hc9bkQiJgCaJyzVJKT2nLPrMra+TZpxLjAf8bfzTaIR7\nyBzAM1+ONLzI4NZwoabqZphQMBeLgkvRZ4iutHq9/65XXwPhJ9rawATImQizNXIWZ/Xc/dBdeYci\ncXlh4cNi9lXr86kv42EtzQO8wiXxvpJNllzagqcYzoDS/2+v9gDA81y/sHczLBSXich8fCL9sHnk\n5HEPy+MWeoxHTXzk4NVKhoDg310u7DNHN/iqdC9jowVF45NxlX5xEGTagsxET2kbWxiMiA+l/seJ\n6hm9WQ5oT/E2yZHcl+/+7WtuGZN65uRALxVa5/5f/aiPVjAc+nbCopYK6mlCZQ1fe6EPe8V6UAwu\nmK6Uxk5h9aHjCoxyl5jtUOUpA3Z2E0IY5HjWDUmo2bW13KxWLnEpTdxtgduawTSy7y1brrIDV9Ou\nthZNeteFd9ZEFakDiqLVxSlFcVeSaMOlBtkUpVqZgEIwE4RUExVbKFs+H5eWDhOO8OZe9cSg9acu\nYYhr68IKC7t9VpDYX5OOgNcj2vxcsNVFwYRGOiq0HeDo2RS36LOmkhoHKBwolhA0gBjZd70RygkT\ne+ujgmuAfYLnTYLZ2nHTE2bGOp0zk1L9xPoBXxIvdp+k5T53k9MUi7R5IRINuNmzr5bC5Qfp1foo\nokZfB1U6tHv1oEOoThzFFHi5MhTQsKEn/ks7GCTg2bAFKYJNuuE7GjA61F1+6Pfp7NPIjUwbK7bN\nTlw/pFPKgsPwRciluwLrUwG/LcAxhFFcg+lpOR6KrBVha2FXaGyrxGufH4oJo5wlwekT/MUb5pmW\nZJgQFHqzjiiXpwW275Qpn8xplJiwEhsVfRYaQIzC5HzBQtBD0Z5xnctY48i77DbgIyL0hIwb/9pW\nQhRC7/N0v7qdT27P0pl+jumTiuNVZta8YTC7G0xouZu+vXxOvE/NO0wbDODHNploJXlfweCV1oyP\nI1N1H5/jXLW0L2eiuCupnTrqSGPbGlL5ABfwLqaZsT5pSY34+77u60VZWbsIexLeWmMfjCRnwqdW\nlazA/KsFkNe9O1U2719btMuPKm+/4TvoYxbpn1POEQsMuuwf9Pu5ujFjLAJq7KtmxM83P+hUfwbr\nG2G0JYCgS4d2fxUgAQiic7SD6J+PBgVi9fHwO7v/rbC/r7wgRKqfvQmlWmB1raUV5e7qFyPgMl91\nDb8DOYHV7Rpd6qEz88xkcQTRT4wIs2PzJ7zBQmRJXb+XbWW88jQEJVpOwGMGWqG33QS7T/CszEl2\n8G/UzSnCH9i0fIkX5bB8hX1jdnr9OkaiXmXu43+ixOyLIbZDRN2aRFEU4bczxAuR5mDXA3WX1DWF\n1LMX3PBCA3DIdqjhKv1+o7MLR+9Hree79XghCuZgtetNgzE+BgpYsP/L+wq4AzZceo2gx/0A3Ad2\nJHE71pWJ/OStHuQFDk7oCr02NKijAhZT/5I73DLzWpVMrpPwG0706DOFl5+bko+2xhL+vKkL4s9G\n43sC21ZYXx40qplG+nB4fhtMI7Lx12xMc6QgJO/DJGJbPIp5sPUk5yZyzFSb6vxhQcGKzF0jRKk2\nblj8QeOpzwmj2vNpKnM80a3UxpPiqfN7qiNdQV/oGE4utr7yunmZfyhLjo/uE0vfzSjmvB87f5Xq\nlSz9CuGzxhmVUGtT60TctfVAGIWcvXELEXV9HRvbEvzJ/XxlarWtZBkumvhDxv+H3/qxTBYBB3VL\nEE7GwzXzsRqrfwK5sZNZBrnzd+XIfp91Cnc96mK+7oU/+LV+A6NtqwEEdxNXA9EK6BlqTOYrfmNU\nUAyIzodRgP4dyJKUwF0WnCNbwi+WgWfKxeD6J6U5fRGoUSwKaIxOmNvBMgeSQ2eA+671h0YMe4NP\nqggDfVx9cXGcpytVWFntnxs6aQPg4qSpVOZkJHP2/oUPTaeW/+Hvyja+m3VTiajRHS+lfWABSwkq\n7pRAbCjzIbKeOM6sY4W63453Ewo296f3xh5ZY65u0scQgUyXtB48n3211e4tIIKNN/AwXo08/bhL\n8gThWAG9WhH2kzkFX3M7AZm47XgemDZnxChGhAXlif7chETEzzJtM8Ytn6zgg/ph9GV3i/Z6aun0\nmrCG0LMtrg4CJo+4mHmQUG27Gtd/PIm9eqWdt4ywk02K4gGJ67YvXnm+EhJHkApngBbKhp+I52ee\nZtUw0Li4xW6bs49i2dOUAjx86jsKeU7uJiWkirUvQ+aK37MPYTPcfME8nYmJNlOwZWzbVKfm00HL\nk0qmK6iDSmL/DSdx9VnPtGsNRFDgI1hAkSsqoGO2mCxxCyfAc48cWKxErLRoVWoO8VSl834ogKht\noeVK58ezIAHphOWtGVwz6GZwBiIy//1koxIMb3oR/qvXYhyucGPrvWOoGAHfpFsQPqwrb+rEKn03\nScU9PlrRZFhZOONC3GwM8Pssp2AOJT6RI+RXmNsMX2QRDtwDnC4vmHwen9MePiN3F/jppJhwA8RW\n/Rm1C2FX8ODUUj/mJU2oyh2u1HV75vH1uvUNFzDmB27k9IBiPpU0jjvuSXAJRPkzve4rYPV9xTL8\nfvi3Vtkjj6ahvzGVcsAVgAX4iWHLuRCHlAmMaXvPjURqSCU6XRgDTx1ia0CoytuL3y2O+KSUqBEK\nUqmtax5Wn+VzUtROS462rJdrp3YARn//1bxpXyg/j1/juWv0yJPQgUYcU3d3JuYIp8Q8jjoVodhn\nP1QPd79DXNB/Pwd711DNxOb0sk8yEPXHXc1Xcnnuz7a1WrYqeU+Ww/PpVga/3biOfdSOi339aWgB\nfndekDI0qMl0s9pWT+9CPjkyL0nbVWARb/uVgNpjHNmro4Nbj0HpFXKX9fwsBDeBmD2lgBrmbKj6\nbdRKGMZutn+k3xVU2uNfdFPeVpbC5lod/2xvC8Ful+0xSpTdyyvsUgfPwPgPtL/SOrLFT0nutxzZ\nkz8gjdMQ4dFDPg5YoKfi+ICV/qlSloXDse3ooI5N1ZuDqcKdcXjzm46vsfHbCZCzGxIgo+W3tT29\nAKYT0/xSqJTbX1kkMmCMOiQqCfGf29k8J1SaP1lrOC5l1AA8nrKBjm3OvciG8hf+5r02GNnwBp8Z\nZDCjx/Atsr+9LAHvecc6HiHJPuNCINcP5TLiSfF0jgcdsQm3869+RWCQUX5yLZWiVCpuQxFzPLPm\n9mjy+MRdZRDrfpkdPkHapHE3kPmPVWQXDTnhLYOgE4vdcljB4tWrpeCNm+JgRQ03G+v+wSPN9TYb\nrwX2GUhJoR/ax47EWPbYauv7LNZ2bJGfOb9s/o8KYw68eXkgj+FDljZzzP0dKUQqYjNgIw2TGCxY\ngcJ7cxv8BTZJ/JTxk7ZL577zd1AInIq0wuKBFqp2t/9tMsxSXegD0PLlzMB2fDYVGmncDtT4PzlE\nozcuiUJRipjY6DoesJlfHKyxNqJNNxjDOW3SjMiKtI8JtSQNH0BSyrRIyGNGXzX/uQArTH65IiPY\nkbNFkh5LMdN5Wn42QqnWV583GGVqmNlGzHkdprd4C+xMN4kkWbjaJVSDHQGeVbUdqT7K6j1Sa/gY\nKGZmys+BhBpakUrOXa2ouadrpwLjtjwhGHVq+zFPcxNyMBIuT43rLb116BwmRtaHmmQRa1Y9fgPg\n7LWLlkhNqEKOAPWFDQUuPpJqYr94vCP0A9arjsxYSzLkGGUsYf0r35nsW4eRMZjFyywzOyktfHup\nchvurg5EDDibgz8QtOdlGNqjerLNTRx+XGEqla27/jSiw8H1kgGrPDAeYsfAVs5y2+3WJNAsw9hT\nZzFM8t/CCIgXX2pj4yrJxSskmH6QjRspvr+VxbpVgFbgSKw/l1lDbmJDDPgX89Wmo0Bog+C8R21R\nqseSnoWZu17XsTWPMkOBeLmus/g7Aw7CMHMIYuQ4A4cJu9j0Gc6RVLvud7iLe2FMoSn0HdrObS/v\nRUAkfW832KW7aEdntoOLUdjtzOQ5QKD8YnNfz4LAzm3OhInLz/DshGnUdxR3EAL159zxjVlLZKGK\nElxu0aK5Jr8coyzWWtm+4HX92C+Qb5vXEXsmqRgIZoQPp5RpRukTUGg4zq4uAWspaTKNzxxlIEYI\npM4B/sIKkQ7sHptRAgZ/K8sDCJolRdeda8ln2ywDEJkz2nu1Kw0jm/+XghX8j1SIOG0qWiz6/Ybc\nzdbJO4Plp4J+X39ZxONVdiGg1EbaJ8UYFl+7inGY0c+VUCclN6lhgWULVKgp0ZbB3yLpKvdDBKgD\n7ZPXHoHemwi+R5aEY7fxs2S9MQcCvo7n2z8hTeHWb+DA5zq8/x/8eWhaI77HZ3DTvtkC2mVsiImR\nwjAkfk0z5JHXQ10Dqdwey7NVkAHLKwgXQG7SZFqrdI2PQV9HHw8bn3m6P+f7/EAy4MkYv8OHlwCg\nAz44PcpP9zXgPo5kl094cZivvFVVOC9A14EHv5xaRJSbue3ckHwAaVgXMonasMWqzQXHHWB4pM/2\nzq4cgM+X11VuzcRfROlRKdmu9umzZJq3sAFpM5xM4oyWtBLLHCdk+kmOffwThUPQcFT6Cp9se2Wv\nBQ3DldAMEtZ/j40qXaVivpsdHisEwN5FZQdxBMQqzZaP4UxldJ4xWKA3n61Muv4KIfoUKajddLuS\nZ5bqFL3zAkvxOf3JPUroU3wJfi2PGRcFmrNSWgp7VEHsWiBw//1PEbEYYXNzlCG322IbiY2RL6iR\nA7vI7/83fM4uY75AhDlBhuQHcEG1mL/9OfaC8TOhJiCwn2ByChDEFZhloTgtP/ZWa3aVGajOfbb2\n9X2Q7O2fzO9lBbF49OOnRLGTGH3jggbIELpZYfUF2wHdMdRJa3vJce8DTqVv771jzqUjE+fnwOv1\n269F8crvbc0cn13uXMkAyw1nN0wpG1H9l1P6jnVhrYq74DkOPEjkiK4unQKlx0aZI/YIHcAfszVM\nY0VIC2djUXZXrZlW3Y4bUmtoO4kMwI/iMgrYuA2cnHULO79HXnYXhrsdAAv9xYSiCAVQv1w7trDt\nXOmMVGvsc7eY3BpFegOKEqPqYIb5cwa75vy47XFo1zUtjPohgZ/g+MCSwqRz13l5N9vQlFSUL857\nRIPEeotyNTAsdh3vFX/jYfsonxch698ZbFLAAZ2uagiQ4oDuMeZpgeUnzcsT64lJa8GhO9cVASuE\ny0F6GpshZvVOe791qrdIB+EJ+FSESXq7IBlZ7u8nKzT3vwJbAFCmo2FIPqzBzR6n3aAQnYVuJIKN\n5Sg85UzY90qoBTGnu7wz2Z8lnZ8kGtpDSDOGhDFHBOGL1+xytbC3IeWxpkSUppE4dMh3UBtUpQpc\nrznsPHtwQusNoU5UHNl+ro08V1FXkHUs3BGo7cjO1E5mEsXECd0Yh+x/PAAC2sove1R0oZM6sGqv\n+cCCB7Vc9Az/Ei+rKcaQ7/cztvAERpeXYbhXrHeIwzJOeo6SllZ6eWAU0t9Umj75FZpWqfPlVngg\nxspwNQyDQ+pzoelgqX6CDTSoJJVBX6ypQoRpbQK004AUM2ODfMQeGrXJroVW7Dn/UvFzPHrPglZC\nHQmAG7G0MAv1OywENidA/tXzqhJYQ8VCtT2y/tKc3sh+T2PofUFs/sXPkTtUY9ALHm3DeX3H4CQP\n3Rb+ibBMospJV/C4wY8lXWgxxVCfBnLgO5r4RdQZ9iG+D+jNnqOzIsmOWgzNE+mbRYtKgPjmCs5w\nkpDjZCTmayxeTJBGAHsyCqnJxUhm0lia66LtCTkMcuB6j6i35CZ97kDpwIOi7AutER7n7lPH++Gn\nm3D321MZdm8kTkBVzTPhrnCA4JFEy+muDff1jfJIYuipA9VLqGCgficM2pPxl5PAt10RYCFRIczP\nImS8vQ89vm3/mEJLxVdbhKLSSIOUe0SyhbZ2qI77n7Pds4qv2SY5jt+R+iIhRASw7/v/kNYUxdiU\nd2whz+3cp4AylBxKxxEOrtr+SEwv9Onfj3IHTQtGHr7vZ7YgYe0YTvUebilhEDptwX6Bk4wHVH18\nELtY4IKlOENXltTlk4Fmfj2DWrqzrYwE27mXmVsBkrge382vltAomA/zHyDmmVAR9fSNI8kJqPv9\nBf0kt+ri0IU1ZZg9Woj0aa6yJritF6/2sxQwnu7hDud4nxN6agLEuHlhB37LbdL4HSPtvvRyQBEA\neetF5eYD5jUT+9nAbGZ+gGiyc7is+4wBcp5djCDST+xp/aqAUweRDNoGPk9chJw7tOrYGAsiLigf\nXAdVxBdEHR7w35WoJZOKR/ohU4uVHNlLcsqfPX8Dvr6UBD0lPGmwIq2vqjVCbdb7t6yILuEq9Ufm\nMGfARBYUMcz0CLCaO6fMddLXYb3+7JNc6BfgeNNs4c+og1l/7cS5kyAZ7etGCS4NmxOe8lgxHUWw\n8IO0tvTl6ukkA/6HFwXkZ0AbJcHifOFomjCv7anv2hOfuO9oEeFpp3WDj12n2Td+ZsWkf1AmoukR\neHaSxklqdCPcEI+UKHxQLNyr8pAOYswoRRGZbIqYW/ta17ZpL5ObFe7L0dnkTerzaK6+7QuQcXN4\nPEGg/nZtybL619pmNPfMj7PZjzIQeW/8N19FXPNLpPAoVClkPHG4Jw2tWKC4w+NgfUpUZJV5/oLG\nE0Qzbcl2mu8ISb5O1UcRkK4QStBrSta2QNvkxAkqOMW/jbQTViSnlFGnQPa3JBnvZ5xx8kSZDoL4\nzRzW+5sj6EamucW1FGMHEcaRnfoI9HYpQXf/8IyKuWe1UyYuhDL/2GkuQjpJTaIy21kze3sprXk6\nwpt1QJZ0Edtv5/8ks9db7hw2IbtXZBpSZpvE9ugD0lLiq5rPGhEahktiI7dZ3qbKT0bTXgXhrq9q\nSUMqwZoXaG/OkXvzEGInn5k3AP8V71EZfoxn5fn/UOuomkWmITLVKtg7tWd1LyrVbmJiZZFDZ7qI\np/XN53yVoQSXwoT4AshECVSbN/qX2+Qwu9Li7N8ET6x0aZ5qsJoEZr2yW2YVjQfbzCQy2cyj06/R\nMr7wwHXXa9rwr8iPvJZqmheEb7Y0AT8RjFFkICCE3TaRpLpc5GXvlm30aMqecTG2WVjbcnNiR+4F\n/C2wlDxRVm2bYvBdaKYVpicEjIE4yUAuMM8LkISEeRh569nRfVlQvmBwU9/WwXT3Ti/9jnbnlYvr\n+Ahjwb2/qNZd5qdcZoIm53BHEPFH6Vq1H/Gh/kzAJKdFN/PoXZKFLX463Mi70+9jrOYA1OiCHndK\no3zf7txPRp00vR2xJpj4unJbmpT4ffdThfuCSmKXRBTTZrgzY9yS6ftKCkee51Ztt+U6nPNlUpAN\nllyRhHkTPq060dxFuYOAoh9z58j+mdFB8eni0jqIqTlySXsVysNMX8AEngW2l89h7oV7E6W3Cthj\nLMSiKmG2/uMLyVm+c2btxBH1BiQRhQ1Rv9q39KwMbuGrzU1o1P3FtPG5HSsyJGmJtp6rDaNiiwxb\npFvHTWhTiDlj/0drNkTzFhG1JwaNzt0kOuewsLPdSir3uklbO6ecYaPK8Z4jgXerghf6lEyknZLS\nAYkKYA3rNh+45AAi1hRUOi3cp/pEHV/rSRmAPuczKvBZi/XmAqj6LGPxNcENDgMujqSw+7+uJJ0U\nQ9Yc5CELdrqvZ7mpxDFUx8QeiSww/sXE6aExkV68LMQHbrd4YaV96mjBcBLcyVqzRhLPDyuNzEFw\np4qk0TDXF1ACMNds2+Dt/Uuq9fxkmO5/q/GV1TyqO2RLP/z8GSXYvfZqOpJDtkFNGW4YcUU9OabN\nad+Q/9AomAx6BhJN0djqPBEafbnO0Jt3UVlPRE+gFekn0MvN+Tvw8vtBYQDL9VjaXZ350tmEqM5n\n8r4nQDI2NKf2AqFC1h6yx1D80OPYltLCRgU0y2GMZwp5ffMxpciUQYx48wteQkIj1vSGxelD7w3D\nFp/RHW7VRDRDzGez/pb0ZUlkmUzN7U1Eo3XRciUGIqIIUNn/ONyb3yvpQQA8wPiq1mwZIKZxyItD\n0U/CJNypm/F4npGM0VnY7fDcgFt7D29oorNPtCf2GAGAwDgKQmSNPmHVa8jJsYiuDcpw9URnTY9V\ntlH1HgWU+Tvr/riLXwOUqSufAPwmdP3p7nNAJVhufvf+5dLe5d3hxHtLxI6kjQwypWq3UBSwzQs2\nLO1+IJ1O4ds3iOra8+5J6u94UI1YsUbGYPOJwvzJ6SjHcLu8x6cWFhaUV2G6xs1fpi+7XO3lbm0y\n5W27tdy11ymOBHal9SdMg+tCFS62wxb2pPE8ZYDSXcwFxnU2QoKifLjZMYzKxXJFwweri6WL3VCt\niqEVBjol27uPCleezJI93TjZrRwL5CETU1b0nUl7hB5tni/KeEvIgKJ04f3KhE3w8g2abb6a0kXC\nuIlTQIIPxUM1ALbGJ+4f5qlVpvJ7nwT2bZ394BwTsH2S8eP241Bq2eVSuOi3Ab6tapNU4YNxIpBL\nDzcIQ/Jq3ToPenfueZrnGr3xKjeXYHJFhki5fzQIs0UkV8rvZP5qWUrko6dILN62pdzGOFJ+y4W0\nXfyMB2uKuXJv6Utx9fFydtYUyEj8Zrn90goiFM+NQU0iFdZ4QEvl1Ts+dv8/rrQH3eJTZqvI/yE3\n12TofYflRc2uRuGlx0r+Q6/3+33yPzrfr6U/aRx1N2E+vcv/L2kGVucq16ibQzJGIZqfHdBints2\nnB/xvJob2flgExd0M73QfeiBCRHzrKKyzj9Xy/YqcQjnpVZHJ0z8Khrxyx3uHHEjnFnVbod7bFEU\nc9ZV++TR2/rvd4/6tgAzf4slQhJqLWCG50xvRj+FPZPCbvxvtFnpArHuGPLhQP58M+qu8J1r6I7s\nag7qtFsFsPbykd8JxRwlB3lt4K7cNC1bKu6iSfT4vsU6XRY/ascVBykqvZDfh/zsnUvrZgmKCCBr\np5h8nDwS5zWHjQ5jShlMEqUr1g8tXsoh0g0RCOAYfHMpevkuPO3hdOrwj6+xJKkkfvuUKAJ15Siq\nsfGhPHOKEye2SzkPITZCk6Epg3vCrRweshnptUBNLAAEgZFGjAcsUQpnC+ckfUoseyAmdGwL2gw7\njQTTYXUrHvMyk+sKl6YTqd1bkaKW4kkUvaZ/rhWQefXwi759KpCKAStFGqfBO0P0buiDMWT3NQZW\nSLbgrltCu/0xvuYiq4t2Dq4pEfgQhWDCTXNAaavjbEt3oNWVDk2/oLH9DhhaEGJ7cp8+e6N6+QOS\n0bspQnURwauJmMJ8yUNYyf9ta8c40Np3aJDOareux0hbEISmQSc4Ibt8NqJFXqF7N2NWS5A+gSsi\norAZxPtzThjQ23JkrwJ0ZPNmbmcrPw1mfTOehFBdqoWPx/V1eDm5NNyriTd6LoYLbfHomQ+8WALR\nvZEOzoN+xewA5Uyk1S3+MzmEKZ3CVhK3GHoxuIMA7jpKebjYySo4sCnlQMb6qqT/bEYEyIsnWvcy\n82f7UbQc9TnIkHDhaRJw2m92dRvylHLCW54hHu6QLRMVKvHYeJNzEdtEit7GocKKSTkPn4BPI/Yi\nDB78TGR7uT3b85v7IOyxHBzEe9as39kKuQRced8pqdr9rbXMTxKG9fjurivrGePnZUbfZnOrpVRL\nkKCb+IpI64a/68XG/DR/SKALmfHrlb33vpCSd0LPcJ9gJUYGctaIA7XC5VtBzhDIcR9PBU+tTm9W\nau9psrwiInRr05n+P2ka3juxmJUvRjj+VYdfHsFkpNtAyitihSAmtBzaFQ/GCY9qd7kXWuxltG51\nrFrtLeXwN+9Dnr+9ExBWRWkyD107BNXg7Q127EZxGeVB9VR/X1KLOqjRClcK7lJrRpdva5kHRJ54\nKhRZV1sepRiHDRVCJIhJ9U6FWd/rQgWMmmcGawdgO1OX8kC5EdLJpXpkSeH5Yjqv3zzjASPu7K1e\nwWPiAxuwVgjdGKJIbluw6G5pJQ2uXDR5Xa5xsfAdroYQ0IRUvAkeOY3tND4Lkw/XVvx8KeFAWTNp\nXenmRJ5/iBqiIfM/c/rIofFpZCA5QqrNEMfQtDBkAJrxtq1sol50O0rih87WaJ+mdtwngYU7HOXS\nRQ+QLH1ciUq6EcJ73P+0hPAOokjzgjhqaori7+/iLyN1C/AWI1S59VXo4s8Lrl4s1/kVBR4QHr5V\nNiVmq4cDDDzuL1SP1j/K7bkn0GyS/RY8DPXrsujE06j3tTvjvnMGY/HaviTzAHivPGFzfXWofpT/\nFOBIBBwbn4pUVoeGWQJXIoNTcyeIxLLEOiJ2zYAUEwEdsOn+f8+dtBaERYpwAhYE4NLbwH6ple55\nRwSPKczzLDMieRAXxc+iQjGV4j/5oqHAmcwgXN7zvk/aGpMYPyA2berXcmFw0LSY1sepZIKYaWuj\noYF9Y7ElShrguXYyk1lAuvOX8VPhIpudfS7dnJHZRceapQi/Xl8DlsQg5fPaQo7gvh+5Hxbe5/dt\nsNmxiidiIGAyoTi091EqBHlEwjR9IhtjBB9469BfzhnT6ccPVCINNxJpiUBJiEOtublFQ/M7KWIP\nfC2d0pCxn06H9bmLT9zfhWsyldmMeBU9AEB2Ck/kn+c75sFlRezkk8wmqlFM2NcAvQcSf8GR2hO/\ncFxi9ZzXFOJCgdfy/9zY0YFHKKnurAgHZlgOdBl8inDgvgC2RlDXnzIuz23kNA9RxHQ2/FXl0z61\nnYwe+SCMNDzoPcUZcUBhPZonJ+3irIWLUdjkbb7qTGymgjf5KR/XMuWA/VX/8uRtjWSOc95Nbt8a\nCaci43oMh2lwO79FoeUffZYmZV3fldqnDs1ze/aOGywPwqcT1jntje94qn3lvQoQ/BJ/k93rEy+2\n5x0vRK6gNlXO4KtnS9D9Ypwk0VbvxdQ8n1IGdI8B9XTjg6ENjqtUbomhDPSFQCjwicweZXrRfUOD\nh+cPfCp22/DQgxGK2DHVgSjAS7NgTpMzbMt2/jQdh7ewO5Ek07NBPGfI47RJujdhRIoS6lFB2L5i\nM2Ly8kjyyAQreVG7AMc6P3r5WOlcr9TujTmvWGh8TOwQ1LDhVNVKJ+JGG1AzuIFYfDJBzzcZd1A5\nteF80j/Z0cUfa1hdkR4d4OTqS5QotD9WNh4QCndwopopxD6G1h9s/s5UVf0blaIfjDBU0/Nx9WVK\n6t/6Ruyhta8hQ9IxRw2VqEEY6Evx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{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule ila_vio_counter (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [0 : 0] probe1;\ninput [7 : 0] probe2;\ninput [15 : 0] probe3;\ninput [0 : 0] probe4;\ninput [0 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [7 : 0] probe8;\ninput [15 : 0] probe9;\ninput [15 : 0] probe10;\n\n\nendmodule\n", "num_lines": 83}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n(* X_CORE_INFO = \"ila,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"ila_vio_counter,ila,{}\" *)\n(* CORE_GENERATION_INFO = \"ila_vio_counter,ila,{x_ipProduct=Vivado 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OBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\\\nC_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\\\nC_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\\\nC_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\\\nC_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\\\nC_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\\\nC_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\\\nC_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\\\nC_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\\\nC_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\\\nC_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1,C_PROBE0_TYPE=0,C_PROBE1_TYPE=0,C_PROBE2_TYPE=0,C_PROBE3_TYPE=0,C_PROBE4_TYPE=0,C_PROBE5_TYPE=0,\\\nC_PROBE6_TYPE=0,C_PROBE7_TYPE=0,C_PROBE8_TYPE=0,C_PROBE9_TYPE=0,C_PROBE10_TYPE=0,C_PROBE11_TYPE=1,C_PROBE12_TYPE=1,C_PROBE13_TYPE=1,C_PROBE14_TYPE=1,C_PROBE15_TYPE=1,C_PROBE16_TYPE=1,C_PROBE17_TYPE=1,C_PROBE18_TYPE=1,C_PROBE19_TYPE=1,C_PROBE20_TYPE=1,C_PROBE21_TYPE=1,C_PROBE22_TYPE=1,C_PROBE23_TYPE=1,C_PROBE24_TYPE=1,C_PROBE25_TYPE=1,C_PROBE26_TYPE=1,C_PROBE27_TYPE=1,C_PROBE28_TYPE=1,C_PROBE29_TYPE=1,C_PROBE30_TYPE=1,C_PROBE31_TYPE=1,C_PROBE32_TYPE=1,C_PROBE33_TYPE=1,C_PROBE34_TYPE=1,C_PROBE35_TYPE=1,C_PROBE36_TYPE=1,C_PROBE37_TYPE=1,C_PROBE38_TYPE=1,C_PROBE39_TYPE=1,C_PROBE40_TYPE=1,C_PROBE41_TYPE=1,C_PROBE42_TYPE=1,C_PROBE43_TYPE=1,C_PROBE44_TYPE=1,C_PROBE45_TYPE=1,C_PROBE46_TYPE=1,C_PROBE47_TYPE=1,C_PROBE48_TYPE=1,C_PROBE49_TYPE=1,C_PROBE50_TYPE=1,C_PROBE51_TYPE=1,C_PROBE52_TYPE=1,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,\\\nC_PROBE106_TYPE=1,C_PROBE107_TYPE=1,C_PROBE108_TYPE=1,C_PROBE109_TYPE=1,C_PROBE110_TYPE=1,C_PROBE111_TYPE=1,C_PROBE112_TYPE=1,C_PROBE113_TYPE=1,C_PROBE114_TYPE=1,C_PROBE115_TYPE=1,C_PROBE116_TYPE=1,C_PROBE117_TYPE=1,C_PROBE118_TYPE=1,C_PROBE119_TYPE=1,C_PROBE120_TYPE=1,C_PROBE121_TYPE=1,C_PROBE122_TYPE=1,C_PROBE123_TYPE=1,C_PROBE124_TYPE=1,C_PROBE125_TYPE=1,C_PROBE126_TYPE=1,C_PROBE127_TYPE=1,C_PROBE128_TYPE=1,C_PROBE129_TYPE=1,C_PROBE130_TYPE=1,C_PROBE131_TYPE=1,C_PROBE132_TYPE=1,C_PROBE133_TYPE=1,C_PROBE134_TYPE=1,C_PROBE135_TYPE=1,C_PROBE136_TYPE=1,C_PROBE137_TYPE=1,C_PROBE138_TYPE=1,C_PROBE139_TYPE=1,C_PROBE140_TYPE=1,C_PROBE141_TYPE=1,C_PROBE142_TYPE=1,C_PROBE143_TYPE=1,C_PROBE144_TYPE=1,C_PROBE145_TYPE=1,C_PROBE146_TYPE=1,C_PROBE147_TYPE=1,C_PROBE148_TYPE=1,C_PROBE149_TYPE=1,C_PROBE150_TYPE=1,C_PROBE151_TYPE=1,C_PROBE152_TYPE=1,C_PROBE153_TYPE=1,C_PROBE154_TYPE=1,C_PROBE155_TYPE=1,C_PROBE156_TYPE=1,C_PROBE157_TYPE=1,C_PROBE158_TYPE=1,C_PROBE159_TYPE=1,C_PROBE160_TYPE=1,C_PROBE161_TYPE=1,C_PROBE162_TYPE=1,C_PROBE163_TYPE=1,C_PROBE164_TYPE=1,C_PROBE165_TYPE=1,C_PROBE166_TYPE=1,C_PROBE167_TYPE=1,C_PROBE168_TYPE=1,C_PROBE169_TYPE=1,C_PROBE170_TYPE=1,C_PROBE171_TYPE=1,C_PROBE172_TYPE=1,C_PROBE173_TYPE=1,C_PROBE174_TYPE=1,C_PROBE175_TYPE=1,C_PROBE176_TYPE=1,C_PROBE177_TYPE=1,C_PROBE178_TYPE=1,C_PROBE179_TYPE=1,C_PROBE180_TYPE=1,C_PROBE181_TYPE=1,C_PROBE182_TYPE=1,C_PROBE183_TYPE=1,C_PROBE184_TYPE=1,C_PROBE185_TYPE=1,C_PROBE186_TYPE=1,C_PROBE187_TYPE=1,C_PROBE188_TYPE=1,C_PROBE189_TYPE=1,C_PROBE190_TYPE=1,C_PROBE191_TYPE=1,C_PROBE192_TYPE=1,C_PROBE193_TYPE=1,C_PROBE194_TYPE=1,C_PROBE195_TYPE=1,C_PROBE196_TYPE=1,C_PROBE197_TYPE=1,C_PROBE198_TYPE=1,C_PROBE199_TYPE=1,C_PROBE200_TYPE=1,C_PROBE201_TYPE=1,C_PROBE202_TYPE=1,C_PROBE203_TYPE=1,C_PROBE204_TYPE=1,C_PROBE205_TYPE=1,\\\nC_PROBE206_TYPE=1,C_PROBE207_TYPE=1,C_PROBE208_TYPE=1,C_PROBE209_TYPE=1,C_PROBE210_TYPE=1,C_PROBE211_TYPE=1,C_PROBE212_TYPE=1,C_PROBE213_TYPE=1,C_PROBE214_TYPE=1,C_PROBE215_TYPE=1,C_PROBE216_TYPE=1,C_PROBE217_TYPE=1,C_PROBE218_TYPE=1,C_PROBE219_TYPE=1,C_PROBE220_TYPE=1,C_PROBE221_TYPE=1,C_PROBE222_TYPE=1,C_PROBE223_TYPE=1,C_PROBE224_TYPE=1,C_PROBE225_TYPE=1,C_PROBE226_TYPE=1,C_PROBE227_TYPE=1,C_PROBE228_TYPE=1,C_PROBE229_TYPE=1,C_PROBE230_TYPE=1,C_PROBE231_TYPE=1,C_PROBE232_TYPE=1,C_PROBE233_TYPE=1,C_PROBE234_TYPE=1,C_PROBE235_TYPE=1,C_PROBE236_TYPE=1,C_PROBE237_TYPE=1,C_PROBE238_TYPE=1,C_PROBE239_TYPE=1,C_PROBE240_TYPE=1,C_PROBE241_TYPE=1,C_PROBE242_TYPE=1,C_PROBE243_TYPE=1,C_PROBE244_TYPE=1,C_PROBE245_TYPE=1,C_PROBE246_TYPE=1,C_PROBE247_TYPE=1,C_PR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E525_TYPE=1,C_PROBE526_TYPE=1,C_PROBE527_TYPE=1,C_PROBE528_TYPE=1,C_PROBE529_TYPE=1,C_PROBE530_TYPE=1,C_PROBE531_TYPE=1,C_PROBE532_TYPE=1,C_PROBE533_TYPE=1,C_PROBE534_TYPE=1,C_PROBE535_TYPE=1,C_PROBE536_TYPE=1,C_PROBE537_TYPE=1,C_PROBE538_TYPE=1,C_PROBE539_TYPE=1,C_PROBE540_TYPE=1,C_PROBE541_TYPE=1,C_PROBE542_TYPE=1,C_PROBE543_TYPE=1,C_PROBE544_TYPE=1,C_PROBE545_TYPE=1,C_PROBE546_TYPE=1,C_PROBE547_TYPE=1,C_PROBE548_TYPE=1,C_PROBE549_TYPE=1,C_PROBE550_TYPE=1,C_PROBE551_TYPE=1,C_PROBE552_TYPE=1,C_PROBE553_TYPE=1,C_PROBE554_TYPE=1,C_PROBE555_TYPE=1,C_PROBE556_TYPE=1,C_PROBE557_TYPE=1,C_PROBE558_TYPE=1,C_PROBE559_TYPE=1,C_PROBE560_TYPE=1,C_PROBE561_TYPE=1,C_PROBE562_TYPE=1,C_PROBE563_TYPE=1,C_PROBE564_TYPE=1,C_PROBE565_TYPE=1,C_PROBE566_TYPE=1,C_PROBE567_TYPE=1,C_PROBE568_TYPE=1,C_PROBE569_TYPE=1,C_PROBE570_TYPE=1,C_PROBE571_TYPE=1,C_PROBE572_TYPE=1,C_PROBE573_TYPE=1,C_PROBE574_TYPE=1,C_PROBE575_TYPE=1,C_PROBE576_TYPE=1,C_PROBE577_TYPE=1,C_PROBE578_TYPE=1,C_PROBE579_TYPE=1,C_PROBE580_TYPE=1,C_PROBE581_TYPE=1,C_PROBE582_TYPE=1,C_PROBE583_TYPE=1,C_PROBE584_TYPE=1,C_PROBE585_TYPE=1,C_PROBE586_TYPE=1,C_PROBE587_TYPE=1,C_PROBE588_TYPE=1,C_PROBE589_TYPE=1,C_PROBE590_TYPE=1,C_PROBE591_TYPE=1,C_PROBE592_TYPE=1,C_PROBE593_TYPE=1,C_PROBE594_TYPE=1,C_PROBE595_TYPE=1,C_PROBE596_TYPE=1,C_PROBE597_TYPE=1,C_PROBE598_TYPE=1,C_PROBE599_TYPE=1,C_PROBE600_TYPE=1,C_PROBE601_TYPE=1,C_PROBE602_TYPE=1,C_PROBE603_TYPE=1,C_PROBE604_TYPE=1,C_PROBE605_TYPE=1,\\\nC_PROBE606_TYPE=1,C_PROBE607_TYPE=1,C_PROBE608_TYPE=1,C_PROBE609_TYPE=1,C_PROBE610_TYPE=1,C_PROBE611_TYPE=1,C_PROBE612_TYPE=1,C_PROBE613_TYPE=1,C_PROBE614_TYPE=1,C_PROBE615_TYPE=1,C_PROBE616_TYPE=1,C_PROBE617_TYPE=1,C_PROBE618_TYPE=1,C_PROBE619_TYPE=1,C_PROBE620_TYPE=1,C_PROBE621_TYPE=1,C_PROBE622_TYPE=1,C_PROBE623_TYPE=1,C_PROBE624_TYPE=1,C_PROBE625_TYPE=1,C_PROBE626_TYPE=1,C_PROBE627_TYPE=1,C_PROBE628_TYPE=1,C_PROBE629_TYPE=1,C_PROBE630_TYPE=1,C_PROBE631_TYPE=1,C_PROBE632_TYPE=1,C_PROBE633_TYPE=1,C_PROBE634_TYPE=1,C_PROBE635_TYPE=1,C_PROBE636_TYPE=1,C_PROBE637_TYPE=1,C_PROBE638_TYPE=1,C_PROBE639_TYPE=1,C_PROBE640_TYPE=1,C_PROBE641_TYPE=1,C_PROBE642_TYPE=1,C_PROBE643_TYPE=1,C_PROBE644_TYPE=1,C_PROBE645_TYPE=1,C_PROBE646_TYPE=1,C_PROBE647_TYPE=1,C_PROBE648_TYPE=1,C_PROBE649_TYPE=1,C_PROBE650_TYPE=1,C_PROBE651_TYPE=1,C_PROBE652_TYPE=1,C_PROBE653_TYPE=1,C_PROBE654_TYPE=1,C_PROBE655_TYPE=1,C_PROBE656_TYPE=1,C_PROBE657_TYPE=1,C_PROBE658_TYPE=1,C_PROBE659_TYPE=1,C_PROBE660_TYPE=1,C_PROBE661_TYPE=1,C_PROBE662_TYPE=1,C_PROBE663_TYPE=1,C_PROBE664_TYPE=1,C_PROBE665_TYPE=1,C_PROBE666_TYPE=1,C_PROBE667_TYPE=1,C_PROBE668_TYPE=1,C_PROBE669_TYPE=1,C_PROBE670_TYPE=1,C_PROBE671_TYPE=1,C_PROBE672_TYPE=1,C_PROBE673_TYPE=1,C_PROBE674_TYPE=1,C_PROBE675_TYPE=1,C_PROBE676_TYPE=1,C_PROBE677_TYPE=1,C_PROBE678_TYPE=1,C_PROBE679_TYPE=1,C_PROBE680_TYPE=1,C_PROBE681_TYPE=1,C_PROBE682_TYPE=1,C_PROBE683_TYPE=1,C_PROBE684_TYPE=1,C_PROBE685_TYPE=1,C_PROBE686_TYPE=1,C_PROBE687_TYPE=1,C_PROBE688_TYPE=1,C_PROBE689_TYPE=1,C_PROBE690_TYPE=1,C_PROBE691_TYPE=1,C_PROBE692_TYPE=1,C_PROBE693_TYPE=1,C_PROBE694_TYPE=1,C_PROBE695_TYPE=1,C_PROBE696_TYPE=1,C_PROBE697_TYPE=1,C_PROBE698_TYPE=1,C_PROBE699_TYPE=1,C_PROBE700_TYPE=1,C_PROBE701_TYPE=1,C_PROBE702_TYPE=1,C_PROBE703_TYPE=1,C_PROBE704_TYPE=1,C_PROBE705_TYPE=1,\\\nC_PROBE706_TYPE=1,C_PROBE707_TYPE=1,C_PROBE708_TYPE=1,C_PROBE709_TYPE=1,C_PROBE710_TYPE=1,C_PROBE711_TYPE=1,C_PROBE712_TYPE=1,C_PROBE713_TYPE=1,C_PROBE714_TYPE=1,C_PROBE715_TYPE=1,C_PROBE716_TYPE=1,C_PROBE717_TYPE=1,C_PROBE718_TYPE=1,C_PROBE719_TYPE=1,C_PROBE720_TYPE=1,C_PROBE721_TYPE=1,C_PROBE722_TYPE=1,C_PROBE723_TYPE=1,C_PROBE724_TYPE=1,C_PROBE725_TYPE=1,C_PROBE726_TYPE=1,C_PROBE727_TYPE=1,C_PROBE728_TYPE=1,C_PROBE729_TYPE=1,C_PROBE730_TYPE=1,C_PROBE731_TYPE=1,C_PROBE732_TYPE=1,C_PROBE733_TYPE=1,C_PROBE734_TYPE=1,C_PROBE735_TYPE=1,C_PROBE736_TYPE=1,C_PROBE737_TYPE=1,C_PROBE738_TYPE=1,C_PROBE739_TYPE=1,C_PROBE740_TYPE=1,C_PROBE741_TYPE=1,C_PROBE742_TYPE=1,C_PROBE743_TYPE=1,C_PROBE744_TYPE=1,C_PROBE745_TYPE=1,C_PROBE746_TYPE=1,C_PROBE747_TYPE=1,C_PROBE748_TYPE=1,C_PROBE749_TYPE=1,C_PROBE750_TYPE=1,C_PROBE751_TYPE=1,C_PROBE752_TYPE=1,C_PROBE753_TYPE=1,C_PROBE754_TYPE=1,C_PROBE755_TYPE=1,C_PROBE756_TYPE=1,C_PROBE757_TYPE=1,C_PROBE758_TYPE=1,C_PROBE759_TYPE=1,C_PROBE760_TYPE=1,C_PROBE761_TYPE=1,C_PROBE762_TYPE=1,C_PROBE763_TYPE=1,C_PROBE764_TYPE=1,C_PROBE765_TYPE=1,C_PROBE766_TYPE=1,C_PROBE767_TYPE=1,C_PROBE768_TYPE=1,C_PROBE769_TYPE=1,C_PROBE770_TYPE=1,C_PROBE771_TYPE=1,C_PROBE772_TYPE=1,C_PROBE773_TYPE=1,C_PROBE774_TYPE=1,C_PROBE775_TYPE=1,C_PROBE776_TYPE=1,C_PROBE777_TYPE=1,C_PROBE778_TYPE=1,C_PROBE779_TYPE=1,C_PROBE780_TYPE=1,C_PROBE781_TYPE=1,C_PROBE782_TYPE=1,C_PROBE783_TYPE=1,C_PROBE784_TYPE=1,C_PROBE785_TYPE=1,C_PROBE786_TYPE=1,C_PROBE787_TYPE=1,C_PROBE788_TYPE=1,C_PROBE789_TYPE=1,C_PROBE790_TYPE=1,C_PROBE791_TYPE=1,C_PROBE792_TYPE=1,C_PROBE793_TYPE=1,C_PROBE794_TYPE=1,C_PROBE795_TYPE=1,C_PROBE796_TYPE=1,C_PROBE797_TYPE=1,C_PROBE798_TYPE=1,C_PROBE799_TYPE=1,C_PROBE800_TYPE=1,C_PROBE801_TYPE=1,C_PROBE802_TYPE=1,C_PROBE803_TYPE=1,C_PROBE804_TYPE=1,C_PROBE805_TYPE=1,\\\nC_PROBE806_TYPE=1,C_PROBE807_TYPE=1,C_PROBE808_TYPE=1,C_PROBE809_TYPE=1,C_PROBE810_TYPE=1,C_PROBE811_TYPE=1,C_PROBE812_TYPE=1,C_PROBE813_TYPE=1,C_PROBE814_TYPE=1,C_PROBE815_TYPE=1,C_PROBE816_TYPE=1,C_PROBE817_TYPE=1,C_PROBE818_TYPE=1,C_PROBE819_TYPE=1,C_PROBE820_TYPE=1,C_PROBE821_TYPE=1,C_PROBE822_TYPE=1,C_PROBE823_TYPE=1,C_PROBE824_TYPE=1,C_PROBE825_TYPE=1,C_PROBE826_TYPE=1,C_PROBE827_TYPE=1,C_PROBE828_TYPE=1,C_PROBE829_TYPE=1,C_PROBE830_TYPE=1,C_PROBE831_TYPE=1,C_PROBE832_TYPE=1,C_PROBE833_TYPE=1,C_PROBE834_TYPE=1,C_PROBE835_TYPE=1,C_PROBE836_TYPE=1,C_PROBE837_TYPE=1,C_PROBE838_TYPE=1,C_PROBE839_TYPE=1,C_PROBE840_TYPE=1,C_PROBE841_TYPE=1,C_PROBE842_TYPE=1,C_PROBE843_TYPE=1,C_PROBE844_TYPE=1,C_PROBE845_TYPE=1,C_PROBE846_TYPE=1,C_PROBE847_TYPE=1,C_PROBE848_TYPE=1,C_PROBE849_TYPE=1,C_PROBE850_TYPE=1,C_PROBE851_TYPE=1,C_PROBE852_TYPE=1,C_PROBE853_TYPE=1,C_PROBE854_TYPE=1,C_PROBE855_TYPE=1,C_PROBE856_TYPE=1,C_PROBE857_TYPE=1,C_PROBE858_TYPE=1,C_PROBE859_TYPE=1,C_PROBE860_TYPE=1,C_PROBE861_TYPE=1,C_PROBE862_TYPE=1,C_PROBE863_TYPE=1,C_PROBE864_TYPE=1,C_PROBE865_TYPE=1,C_PROBE866_TYPE=1,C_PROBE867_TYPE=1,C_PROBE868_TYPE=1,C_PROBE869_TYPE=1,C_PROBE870_TYPE=1,C_PROBE871_TYPE=1,C_PROBE872_TYPE=1,C_PROBE873_TYPE=1,C_PROBE874_TYPE=1,C_PROBE875_TYPE=1,C_PROBE876_TYPE=1,C_PROBE877_TYPE=1,C_PROBE878_TYPE=1,C_PROBE879_TYPE=1,C_PROBE880_TYPE=1,C_PROBE881_TYPE=1,C_PROBE882_TYPE=1,C_PROBE883_TYPE=1,C_PROBE884_TYPE=1,C_PROBE885_TYPE=1,C_PROBE886_TYPE=1,C_PROBE887_TYPE=1,C_PROBE888_TYPE=1,C_PROBE889_TYPE=1,C_PROBE890_TYPE=1,C_PROBE891_TYPE=1,C_PROBE892_TYPE=1,C_PROBE893_TYPE=1,C_PROBE894_TYPE=1,C_PROBE895_TYPE=1,C_PROBE896_TYPE=1,C_PROBE897_TYPE=1,C_PROBE898_TYPE=1,C_PROBE899_TYPE=1,C_PROBE900_TYPE=1,C_PROBE901_TYPE=1,C_PROBE902_TYPE=1,C_PROBE903_TYPE=1,C_PROBE904_TYPE=1,C_PROBE905_TYPE=1,\\\nC_PROBE906_TYPE=1,C_PROBE907_TYPE=1,C_PROBE908_TYPE=1,C_PROBE909_TYPE=1,C_PROBE910_TYPE=1,C_PROBE911_TYPE=1,C_PROBE912_TYPE=1,C_PROBE913_TYPE=1,C_PROBE914_TYPE=1,C_PROBE915_TYPE=1,C_PROBE916_TYPE=1,C_PROBE917_TYPE=1,C_PROBE918_TYPE=1,C_PROBE919_TYPE=1,C_PROBE920_TYPE=1,C_PROBE921_TYPE=1,C_PROBE922_TYPE=1,C_PROBE923_TYPE=1,C_PROBE924_TYPE=1,C_PROBE925_TYPE=1,C_PROBE926_TYPE=1,C_PROBE927_TYPE=1,C_PROBE928_TYPE=1,C_PROBE929_TYPE=1,C_PROBE930_TYPE=1,C_PROBE931_TYPE=1,C_PROBE932_TYPE=1,C_PROBE933_TYPE=1,C_PROBE934_TYPE=1,C_PROBE935_TYPE=1,C_PROBE936_TYPE=1,C_PROBE937_TYPE=1,C_PROBE938_TYPE=1,C_PROBE939_TYPE=1,C_PROBE940_TYPE=1,C_PROBE941_TYPE=1,C_PROBE942_TYPE=1,C_PROBE943_TYPE=1,C_PROBE944_TYPE=1,C_PROBE945_TYPE=1,C_PROBE946_TYPE=1,C_PROBE947_TYPE=1,C_PROBE948_TYPE=1,C_PROBE949_TYPE=1,C_PROBE950_TYPE=1,C_PROBE951_TYPE=1,C_PROBE952_TYPE=1,C_PROBE953_TYPE=1,C_PROBE954_TYPE=1,C_PROBE955_TYPE=1,C_PROBE956_TYPE=1,C_PROBE957_TYPE=1,C_PROBE958_TYPE=1,C_PROBE959_TYPE=1,C_PROBE960_TYPE=1,C_PROBE961_TYPE=1,C_PROBE962_TYPE=1,C_PROBE963_TYPE=1,C_PROBE964_TYPE=1,C_PROBE965_TYPE=1,C_PROBE966_TYPE=1,C_PROBE967_TYPE=1,C_PROBE968_TYPE=1,C_PROBE969_TYPE=1,C_PROBE970_TYPE=1,C_PROBE971_TYPE=1,C_PROBE972_TYPE=1,C_PROBE973_TYPE=1,C_PROBE974_TYPE=1,C_PROBE975_TYPE=1,C_PROBE976_TYPE=1,C_PROBE977_TYPE=1,C_PROBE978_TYPE=1,C_PROBE979_TYPE=1,C_PROBE980_TYPE=1,C_PROBE981_TYPE=1,C_PROBE982_TYPE=1,C_PROBE983_TYPE=1,C_PROBE984_TYPE=1,C_PROBE985_TYPE=1,C_PROBE986_TYPE=1,C_PROBE987_TYPE=1,C_PROBE988_TYPE=1,C_PROBE989_TYPE=1,C_PROBE990_TYPE=1,C_PROBE991_TYPE=1,C_PROBE992_TYPE=1,C_PROBE993_TYPE=1,C_PROBE994_TYPE=1,C_PROBE995_TYPE=1,C_PROBE996_TYPE=1,C_PROBE997_TYPE=1,C_PROBE998_TYPE=1,C_PROBE999_TYPE=1,C_PROBE1000_TYPE=1,C_PROBE1001_TYPE=1,C_PROBE1002_TYPE=1,C_PROBE1003_TYPE=1,C_PROBE1004_TYPE=1,C_PROBE1005_TYPE=1,\\\nC_PROBE1006_TYPE=1,C_PROBE1007_TYPE=1,C_PROBE1008_TYPE=1,C_PROBE1009_TYPE=1,C_PROBE1010_TYPE=1,C_PROBE1011_TYPE=1,C_PROBE1012_TYPE=1,C_PROBE1013_TYPE=1,C_PROBE1014_TYPE=1,C_PROBE1015_TYPE=1,C_PROBE1016_TYPE=1,C_PROBE1017_TYPE=1,C_PROBE1018_TYPE=1,C_PROBE1019_TYPE=1,C_PROBE1020_TYPE=1,C_PROBE1021_TYPE=1,C_PROBE1022_TYPE=1,C_PROBE1023_TYPE=1}\" *)\n\nmodule ila_vio_counter (\nclk,\n\n\nprobe0,\nprobe1,\nprobe2,\nprobe3,\nprobe4,\nprobe5,\nprobe6,\nprobe7,\nprobe8,\nprobe9,\nprobe10\n);\n\ninput clk;\n\n\ninput [0 : 0] probe0;\ninput [0 : 0] probe1;\ninput [7 : 0] probe2;\ninput [15 : 0] probe3;\ninput [0 : 0] probe4;\ninput [0 : 0] probe5;\ninput [0 : 0] probe6;\ninput [0 : 0] probe7;\ninput [7 : 0] probe8;\ninput [15 : 0] probe9;\ninput [15 : 0] probe10;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nila_v6_2_11_ila #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexu\"),\n.C_CORE_TYPE(1),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_CAPTURE_TYPE(0),\n.C_MU_TYPE(0),\n.C_TC_TYPE(0),\n.C_NUM_OF_PROBES(11),\n.C_DATA_DEPTH(1024),\n.C_MAJOR_VERSION(2020),\n.C_MINOR_VERSION(2),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(6),\n.C_CORE_MINOR_VER(2),\n.C_XSDB_SLAVE_TYPE(17),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(2),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(1),\n.C_RAM_STYLE(\"SUBCORE\"),\n.C_TRIGOUT_EN(0),\n.C_TRIGIN_EN(0),\n.C_ADV_TRIGGER(0),\n.C_EN_DDR_ILA(0),\n.C_DDR_CLK_GEN(0),\n.C_CLK_FREQ(200),\n.C_CLK_PERIOD(5.0),\n.C_CLKFBOUT_MULT_F(10),\n.C_DIVCLK_DIVIDE(3),\n.C_CLKOUT0_DIVIDE_F(10),\n.C_EN_STRG_QUAL(0),\n.C_INPUT_PIPE_STAGES(4),\n.C_EN_TIME_TAG (0),\n.C_TIME_TAG_WIDTH (32),\n.C_ILA_CLK_FREQ(2000000),\n.C_PROBE0_WIDTH(1),\n.C_PROBE1_WIDTH(1),\n.C_PROBE2_WIDTH(8),\n.C_PROBE3_WIDTH(16),\n.C_PROBE4_WIDTH(1),\n.C_PROBE5_WIDTH(1),\n.C_PROBE6_WIDTH(1),\n.C_PROBE7_WIDTH(1),\n.C_PROBE8_WIDTH(8),\n.C_PROBE9_WIDTH(16),\n.C_PROBE10_WIDTH(16),\n.C_PROBE11_WIDTH(1),\n.C_PROBE12_WIDTH(1),\n.C_PROBE13_WIDTH(1),\n.C_PROBE14_WIDTH(1),\n.C_PROBE15_WIDTH(1),\n.C_PROBE16_WIDTH(1),\n.C_PROBE17_WIDTH(1),\n.C_PROBE18_WIDTH(1),\n.C_PROBE19_WIDTH(1),\n.C_PROBE20_WIDTH(1),\n.C_PROBE21_WIDTH(1),\n.C_PROBE22_WIDTH(1),\n.C_PROBE23_WIDTH(1),\n.C_PROBE24_WIDTH(1),\n.C_PROBE25_WIDTH(1),\n.C_PROBE26_WIDTH(1),\n.C_PROBE27_WIDTH(1),\n.C_PROBE28_WIDTH(1),\n.C_PROBE29_WIDTH(1),\n.C_PROBE30_WIDTH(1),\n.C_PROBE31_WIDTH(1),\n.C_PROBE32_WIDTH(1),\n.C_PROBE33_WIDTH(1),\n.C_PROBE34_WIDTH(1),\n.C_PROBE35_WIDTH(1),\n.C_PROBE36_WIDTH(1),\n.C_PROBE37_WIDTH(1),\n.C_PROBE38_WIDTH(1),\n.C_PROBE39_WIDTH(1),\n.C_PROBE40_WIDTH(1),\n.C_PROBE41_WIDTH(1),\n.C_PROBE42_WIDTH(1),\n.C_PROBE43_WIDTH(1),\n.C_PROBE44_WIDTH(1),\n.C_PROBE45_WIDTH(1),\n.C_PROBE46_WIDTH(1),\n.C_PROBE47_WIDTH(1),\n.C_PROBE48_WIDTH(1),\n.C_PROBE49_WIDTH(1),\n.C_PROBE50_WIDTH(1),\n.C_PROBE51_WIDTH(1),\n.C_PROBE52_WIDTH(1),\n.C_PROBE53_WIDTH(1),\n.C_PROBE54_WIDTH(1),\n.C_PROBE55_WIDTH(1),\n.C_PROBE56_WIDTH(1),\n.C_PROBE57_WIDTH(1),\n.C_PROBE58_WIDTH(1),\n.C_PROBE59_WIDTH(1),\n.C_PROBE60_WIDTH(1),\n.C_PROBE61_WIDTH(1),\n.C_PROBE62_WIDTH(1),\n.C_PROBE63_WIDTH(1),\n.C_PROBE64_WIDTH(1),\n.C_PROBE65_WIDTH(1),\n.C_PROBE66_WIDTH(1),\n.C_PROBE67_WIDTH(1),\n.C_PROBE68_WIDTH(1),\n.C_PROBE69_WIDTH(1),\n.C_PROBE70_WIDTH(1),\n.C_PROBE71_WIDTH(1),\n.C_PROBE72_WIDTH(1),\n.C_PROBE73_WIDTH(1),\n.C_PROBE74_WIDTH(1),\n.C_PROBE75_WIDTH(1),\n.C_PROBE76_WIDTH(1),\n.C_PROBE77_WIDTH(1),\n.C_PROBE78_WIDTH(1),\n.C_PROBE79_WIDTH(1),\n.C_PROBE80_WIDTH(1),\n.C_PROBE81_WIDTH(1),\n.C_PROBE82_WIDTH(1),\n.C_PROBE83_WIDTH(1),\n.C_PROBE84_WIDTH(1),\n.C_PROBE85_WIDTH(1),\n.C_PROBE86_WIDTH(1),\n.C_PROBE87_WIDTH(1),\n.C_PROBE88_WIDTH(1),\n.C_PROBE89_WIDTH(1),\n.C_PROBE90_WIDTH(1),\n.C_PROBE91_WIDTH(1),\n.C_PROBE92_WIDTH(1),\n.C_PROBE93_WIDTH(1),\n.C_PROBE94_WIDTH(1),\n.C_PROBE95_WIDTH(1),\n.C_PROBE96_WIDTH(1),\n.C_PROBE97_WIDTH(1),\n.C_PROBE98_WIDTH(1),\n.C_PROBE99_WIDTH(1),\n.C_PROBE100_WIDTH(1),\n.C_PROBE101_WIDTH(1),\n.C_PROBE102_WIDTH(1),\n.C_PROBE103_WIDTH(1),\n.C_PROBE104_WIDTH(1),\n.C_PROBE105_WIDTH(1),\n.C_PROBE106_WIDTH(1),\n.C_PROBE107_WIDTH(1),\n.C_PROBE108_WIDTH(1),\n.C_PROBE109_WIDTH(1),\n.C_PROBE110_WIDTH(1),\n.C_PROBE111_WIDTH(1),\n.C_PROBE112_WIDTH(1),\n.C_PROBE113_WIDTH(1),\n.C_PROBE114_WIDTH(1),\n.C_PROBE115_WIDTH(1),\n.C_PROBE116_WIDTH(1),\n.C_PROBE117_WIDTH(1),\n.C_PROBE118_WIDTH(1),\n.C_PROBE119_WIDTH(1),\n.C_PROBE120_WIDTH(1),\n.C_PROBE121_WIDTH(1),\n.C_PROBE122_WIDTH(1),\n.C_PROBE123_WIDTH(1),\n.C_PROBE124_WIDTH(1),\n.C_PROBE125_WIDTH(1),\n.C_PROBE126_WIDTH(1),\n.C_PROBE127_WIDTH(1),\n.C_PROBE128_WIDTH(1),\n.C_PROBE129_WIDTH(1),\n.C_PROBE130_WIDTH(1),\n.C_PROBE131_WIDTH(1),\n.C_PROBE132_WIDTH(1),\n.C_PROBE133_WIDTH(1),\n.C_PROBE134_WIDTH(1),\n.C_PROBE135_WIDTH(1),\n.C_PROBE136_WIDTH(1),\n.C_PROBE137_WIDTH(1),\n.C_PROBE138_WIDTH(1),\n.C_PROBE139_WIDTH(1),\n.C_PROBE140_WIDTH(1),\n.C_PROBE141_WIDTH(1),\n.C_PROBE142_WIDTH(1),\n.C_PROBE143_WIDTH(1),\n.C_PROBE144_WIDTH(1),\n.C_PROBE145_WIDTH(1),\n.C_PROBE146_WIDTH(1),\n.C_PROBE147_WIDTH(1),\n.C_PROBE148_WIDTH(1),\n.C_PROBE149_WIDTH(1),\n.C_PROBE150_WIDTH(1),\n.C_PROBE151_WIDTH(1),\n.C_PROBE152_WIDTH(1),\n.C_PROBE153_WIDTH(1),\n.C_PROBE154_WIDTH(1),\n.C_PROBE155_WIDTH(1),\n.C_PROBE156_WIDTH(1),\n.C_PROBE157_WIDTH(1),\n.C_PROBE158_WIDTH(1),\n.C_PROBE159_WIDTH(1),\n.C_PROBE160_WIDTH(1),\n.C_PROBE161_WIDTH(1),\n.C_PROBE162_WIDTH(1),\n.C_PROBE163_WIDTH(1),\n.C_PROBE164_WIDTH(1),\n.C_PROBE165_WIDTH(1),\n.C_PROBE166_WIDTH(1),\n.C_PROBE167_WIDTH(1),\n.C_PROBE168_WIDTH(1),\n.C_PROBE169_WIDTH(1),\n.C_PROBE170_WIDTH(1),\n.C_PROBE171_WIDTH(1),\n.C_PROBE172_WIDTH(1),\n.C_PROBE173_WIDTH(1),\n.C_PROBE174_WIDTH(1),\n.C_PROBE175_WIDTH(1),\n.C_PROBE176_WIDTH(1),\n.C_PROBE177_WIDTH(1),\n.C_PROBE178_WIDTH(1),\n.C_PROBE179_WIDTH(1),\n.C_PROBE180_WIDTH(1),\n.C_PROBE181_WIDTH(1),\n.C_PROBE182_WIDTH(1),\n.C_PROBE183_WIDTH(1),\n.C_PROBE184_WIDTH(1),\n.C_PROBE185_WIDTH(1),\n.C_PROBE186_WIDTH(1),\n.C_PROBE187_WIDTH(1),\n.C_PROBE188_WIDTH(1),\n.C_PROBE189_WIDTH(1),\n.C_PROBE190_WIDTH(1),\n.C_PROBE191_WIDTH(1),\n.C_PROBE192_WIDTH(1),\n.C_PROBE193_WIDTH(1),\n.C_PROBE194_WIDTH(1),\n.C_PROBE195_WIDTH(1),\n.C_PROBE196_WIDTH(1),\n.C_PROBE197_WIDTH(1),\n.C_PROBE198_WIDTH(1),\n.C_PROBE199_WIDTH(1),\n.C_PROBE200_WIDTH(1),\n.C_PROBE201_WIDTH(1),\n.C_PROBE202_WIDTH(1),\n.C_PROBE203_WIDTH(1),\n.C_PROBE204_WIDTH(1),\n.C_PROBE205_WIDTH(1),\n.C_PROBE206_WIDTH(1),\n.C_PROBE207_WIDTH(1),\n.C_PROBE208_WIDTH(1),\n.C_PROBE209_WIDTH(1),\n.C_PROBE210_WIDTH(1),\n.C_PROBE211_WIDTH(1),\n.C_PROBE212_WIDTH(1),\n.C_PROBE213_WIDTH(1),\n.C_PROBE214_WIDTH(1),\n.C_PROBE215_WIDTH(1),\n.C_PROBE216_WIDTH(1),\n.C_PROBE217_WIDTH(1),\n.C_PROBE218_WIDTH(1),\n.C_PROBE219_WIDTH(1),\n.C_PROBE220_W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U_CNT(1),\n.C_PROBE66_MU_CNT(1),\n.C_PROBE67_MU_CNT(1),\n.C_PROBE68_MU_CNT(1),\n.C_PROBE69_MU_CNT(1),\n.C_PROBE70_MU_CNT(1),\n.C_PROBE71_MU_CNT(1),\n.C_PROBE72_MU_CNT(1),\n.C_PROBE73_MU_CNT(1),\n.C_PROBE74_MU_CNT(1),\n.C_PROBE75_MU_CNT(1),\n.C_PROBE76_MU_CNT(1),\n.C_PROBE77_MU_CNT(1),\n.C_PROBE78_MU_CNT(1),\n.C_PROBE79_MU_CNT(1),\n.C_PROBE80_MU_CNT(1),\n.C_PROBE81_MU_CNT(1),\n.C_PROBE82_MU_CNT(1),\n.C_PROBE83_MU_CNT(1),\n.C_PROBE84_MU_CNT(1),\n.C_PROBE85_MU_CNT(1),\n.C_PROBE86_MU_CNT(1),\n.C_PROBE87_MU_CNT(1),\n.C_PROBE88_MU_CNT(1),\n.C_PROBE89_MU_CNT(1),\n.C_PROBE90_MU_CNT(1),\n.C_PROBE91_MU_CNT(1),\n.C_PROBE92_MU_CNT(1),\n.C_PROBE93_MU_CNT(1),\n.C_PROBE94_MU_CNT(1),\n.C_PROBE95_MU_CNT(1),\n.C_PROBE96_MU_CNT(1),\n.C_PROBE97_MU_CNT(1),\n.C_PROBE98_MU_CNT(1),\n.C_PROBE99_MU_CNT(1),\n.C_PROBE100_MU_CNT(1),\n.C_PROBE101_MU_CNT(1),\n.C_PROBE102_MU_CNT(1),\n.C_PROBE103_MU_CNT(1),\n.C_PROBE104_MU_CNT(1),\n.C_PROBE105_MU_CNT(1),\n.C_PROBE106_MU_CNT(1),\n.C_PROBE107_MU_CNT(1),\n.C_PROBE108_MU_CNT(1),\n.C_PROBE109_MU_CNT(1),\n.C_PROBE110_MU_CNT(1),\n.C_PROBE111_MU_CNT(1),\n.C_PROBE112_MU_CNT(1),\n.C_PROBE113_MU_CNT(1),\n.C_PROBE114_MU_CNT(1),\n.C_PROBE115_MU_CNT(1),\n.C_PROBE116_MU_CNT(1),\n.C_PROBE117_MU_CNT(1),\n.C_PROBE118_MU_CNT(1),\n.C_PROBE119_MU_CNT(1),\n.C_PROBE120_MU_CNT(1),\n.C_PROBE121_MU_CNT(1),\n.C_PROBE122_MU_CNT(1),\n.C_PROBE123_MU_CNT(1),\n.C_PROBE124_MU_CNT(1),\n.C_PROBE125_MU_CNT(1),\n.C_PROBE126_MU_CNT(1),\n.C_PROBE127_MU_CNT(1),\n.C_PROBE128_MU_CNT(1),\n.C_PROBE129_MU_CNT(1),\n.C_PROBE130_MU_CNT(1),\n.C_PROBE131_MU_CNT(1),\n.C_PROBE132_MU_CNT(1),\n.C_PROBE133_MU_CNT(1),\n.C_PROBE134_MU_CNT(1),\n.C_PROBE135_MU_CNT(1),\n.C_PROBE136_MU_CNT(1),\n.C_PROBE137_MU_CNT(1),\n.C_PROBE138_MU_CNT(1),\n.C_PROBE139_MU_CNT(1),\n.C_PROBE140_MU_CNT(1),\n.C_PROBE141_MU_CNT(1),\n.C_PROBE142_MU_CNT(1),\n.C_PROBE143_MU_CNT(1),\n.C_PROBE144_MU_CNT(1),\n.C_PROBE145_MU_CNT(1),\n.C_PROBE146_MU_CNT(1),\n.C_PROBE147_MU_CNT(1),\n.C_PROBE148_MU_CNT(1),\n.C_PROBE149_MU_CNT(1),\n.C_PROBE150_MU_CNT(1),\n.C_PROBE151_MU_CNT(1),\n.C_PROBE152_MU_CNT(1),\n.C_PROBE153_MU_CNT(1),\n.C_PROBE154_MU_CNT(1),\n.C_PROBE155_MU_CNT(1),\n.C_PROBE156_MU_CNT(1),\n.C_PROBE157_MU_CNT(1),\n.C_PROBE158_MU_CNT(1),\n.C_PROBE159_MU_CNT(1),\n.C_PROBE160_MU_CNT(1),\n.C_PROBE161_MU_CNT(1),\n.C_PROBE162_MU_CNT(1),\n.C_PROBE163_MU_CNT(1),\n.C_PROBE164_MU_CNT(1),\n.C_PROBE165_MU_CNT(1),\n.C_PROBE166_MU_CNT(1),\n.C_PROBE167_MU_CNT(1),\n.C_PROBE168_MU_CNT(1),\n.C_PROBE169_MU_CNT(1),\n.C_PROBE170_MU_CNT(1),\n.C_PROBE171_MU_CNT(1),\n.C_PROBE172_MU_CNT(1),\n.C_PROBE173_MU_CNT(1),\n.C_PROBE174_MU_CNT(1),\n.C_PROBE175_MU_CNT(1),\n.C_PROBE176_MU_CNT(1),\n.C_PROBE177_MU_CNT(1),\n.C_PROBE178_MU_CNT(1),\n.C_PROBE179_MU_CNT(1),\n.C_PROBE180_MU_CNT(1),\n.C_PROBE181_MU_CNT(1),\n.C_PROBE182_MU_CNT(1),\n.C_PROBE183_MU_CNT(1),\n.C_PROBE184_MU_CNT(1),\n.C_PROBE185_MU_CNT(1),\n.C_PROBE186_MU_CNT(1),\n.C_PROBE187_MU_CNT(1),\n.C_PROBE188_MU_CNT(1),\n.C_PROBE189_MU_CNT(1),\n.C_PROBE190_MU_CNT(1),\n.C_PROBE191_MU_CNT(1),\n.C_PROBE192_MU_CNT(1),\n.C_PROBE193_MU_CNT(1),\n.C_PROBE194_MU_CNT(1),\n.C_PROBE195_MU_CNT(1),\n.C_PROBE196_MU_CNT(1),\n.C_PROBE197_MU_CNT(1),\n.C_PROBE198_MU_CNT(1),\n.C_PROBE199_MU_CNT(1),\n.C_PROBE200_MU_CNT(1),\n.C_PROBE201_MU_CNT(1),\n.C_PROBE202_MU_CNT(1),\n.C_PROBE203_MU_CNT(1),\n.C_PROBE204_MU_CNT(1),\n.C_PROBE205_MU_CNT(1),\n.C_PROBE206_MU_CNT(1),\n.C_PROBE207_MU_CNT(1),\n.C_PROBE208_MU_CNT(1),\n.C_PROBE209_MU_CNT(1),\n.C_PROBE210_MU_CNT(1),\n.C_PROBE211_MU_CNT(1),\n.C_PROBE212_MU_CNT(1),\n.C_PROBE213_MU_CNT(1),\n.C_PROBE214_MU_CNT(1),\n.C_PROBE215_MU_CNT(1),\n.C_PROBE216_MU_CNT(1),\n.C_PROBE217_MU_CNT(1),\n.C_PROBE218_MU_CNT(1),\n.C_PROBE219_MU_CNT(1),\n.C_PROBE220_MU_CNT(1),\n.C_PROBE221_MU_CNT(1),\n.C_PROBE222_MU_CNT(1),\n.C_PROBE223_MU_CNT(1),\n.C_PROBE224_MU_CNT(1),\n.C_PROBE225_MU_CNT(1),\n.C_PROBE226_MU_CNT(1),\n.C_PROBE227_MU_CNT(1),\n.C_PROBE228_MU_CNT(1),\n.C_PROBE229_MU_CNT(1),\n.C_PROBE230_MU_CNT(1),\n.C_PROBE231_MU_CNT(1),\n.C_PROBE232_MU_CNT(1),\n.C_PROBE233_MU_CNT(1),\n.C_PROBE234_MU_CNT(1),\n.C_PROBE235_MU_CNT(1),\n.C_PROBE236_MU_CNT(1),\n.C_PROBE237_MU_CNT(1),\n.C_PROBE238_MU_CNT(1),\n.C_PROBE239_MU_CNT(1),\n.C_PROBE240_MU_CNT(1),\n.C_PROBE241_MU_CNT(1),\n.C_PROBE242_MU_CNT(1),\n.C_PROBE243_MU_CNT(1),\n.C_PROBE244_MU_CNT(1),\n.C_PROBE245_MU_CNT(1),\n.C_PROBE246_MU_CNT(1),\n.C_PROBE247_MU_CNT(1),\n.C_PROBE248_MU_CNT(1),\n.C_PROBE249_MU_CNT(1),\n.C_PROBE250_MU_CNT(1),\n.C_PROBE251_MU_CNT(1),\n.C_PROBE252_MU_CNT(1),\n.C_PROBE253_MU_CNT(1),\n.C_PROBE254_MU_CNT(1),\n.C_PROBE255_MU_CNT(1),\n.C_PROBE256_MU_CNT(1),\n.C_PROBE257_MU_CNT(1),\n.C_PROBE258_MU_CNT(1),\n.C_PROBE259_MU_CNT(1),\n.C_PROBE260_MU_CNT(1),\n.C_PROBE261_MU_CNT(1),\n.C_PROBE262_MU_CNT(1),\n.C_PROBE263_MU_CNT(1),\n.C_PROBE264_MU_CNT(1),\n.C_PROBE265_MU_CNT(1),\n.C_PROBE266_MU_CNT(1),\n.C_PROBE267_MU_CNT(1),\n.C_PROBE268_MU_CNT(1),\n.C_PROBE269_MU_CNT(1),\n.C_PROBE270_MU_CNT(1),\n.C_PROBE271_MU_CNT(1),\n.C_PROBE272_MU_CNT(1),\n.C_PROBE273_MU_CNT(1),\n.C_PROBE274_MU_CNT(1),\n.C_PROBE275_MU_CNT(1),\n.C_PROBE276_MU_CNT(1),\n.C_PROBE277_MU_CNT(1),\n.C_PROBE278_MU_CNT(1),\n.C_PROBE279_MU_CNT(1),\n.C_PROBE280_MU_CNT(1),\n.C_PROBE281_MU_CNT(1),\n.C_PROBE282_MU_CNT(1),\n.C_PROBE283_MU_CNT(1),\n.C_PROBE284_MU_CNT(1),\n.C_PROBE285_MU_CNT(1),\n.C_PROBE286_MU_CNT(1),\n.C_PROBE287_MU_CNT(1),\n.C_PROBE288_MU_CNT(1),\n.C_PROBE289_MU_CNT(1),\n.C_PROBE290_MU_CNT(1),\n.C_PROBE291_MU_CNT(1),\n.C_PROBE292_MU_CNT(1),\n.C_PROBE293_MU_CNT(1),\n.C_PROBE294_MU_CNT(1),\n.C_PROBE295_MU_CNT(1),\n.C_PROBE296_MU_CNT(1),\n.C_PROBE297_MU_CNT(1),\n.C_PROBE298_MU_CNT(1),\n.C_PROBE299_MU_CNT(1),\n.C_PROBE300_MU_CNT(1),\n.C_PROBE301_MU_CNT(1),\n.C_PROBE302_MU_CNT(1),\n.C_PROBE303_MU_CNT(1),\n.C_PROBE304_MU_CNT(1),\n.C_PROBE305_MU_CNT(1),\n.C_PROBE306_MU_CNT(1),\n.C_PROBE307_MU_CNT(1),\n.C_PROBE308_MU_CNT(1),\n.C_PROBE309_MU_CNT(1),\n.C_PROBE310_MU_CNT(1),\n.C_PROBE311_MU_CNT(1),\n.C_PROBE312_MU_CNT(1),\n.C_PROBE313_MU_CNT(1),\n.C_PROBE314_MU_CNT(1),\n.C_PROBE315_MU_CNT(1),\n.C_PROBE316_MU_CNT(1),\n.C_PROBE317_MU_CNT(1),\n.C_PROBE318_MU_CNT(1),\n.C_PROBE319_MU_CNT(1),\n.C_PROBE320_MU_CNT(1),\n.C_PROBE321_MU_CNT(1),\n.C_PROBE322_MU_CNT(1),\n.C_PROBE323_MU_CNT(1),\n.C_PROBE324_MU_CNT(1),\n.C_PROBE325_MU_CNT(1),\n.C_PROBE326_MU_CNT(1),\n.C_PROBE327_MU_CNT(1),\n.C_PROBE328_MU_CNT(1),\n.C_PROBE329_MU_CNT(1),\n.C_PROBE330_MU_CNT(1),\n.C_PROBE331_MU_CNT(1),\n.C_PROBE332_MU_CNT(1),\n.C_PROBE333_MU_CNT(1),\n.C_PROBE334_MU_CNT(1),\n.C_PROBE335_MU_CNT(1),\n.C_PROBE336_MU_CNT(1),\n.C_PROBE337_MU_CNT(1),\n.C_PROBE338_MU_CNT(1),\n.C_PROBE339_MU_CNT(1),\n.C_PROBE340_MU_CNT(1),\n.C_PROBE341_MU_CNT(1),\n.C_PROBE342_MU_CNT(1),\n.C_PROBE343_MU_CNT(1),\n.C_PROBE344_MU_CNT(1),\n.C_PROBE345_MU_CNT(1),\n.C_PROBE346_MU_CNT(1),\n.C_PROBE347_MU_CNT(1),\n.C_PROBE348_MU_CNT(1),\n.C_PROBE349_MU_CNT(1),\n.C_PROBE350_MU_CNT(1),\n.C_PROBE351_MU_CNT(1),\n.C_PROBE352_MU_CNT(1),\n.C_PROBE353_MU_CNT(1),\n.C_PROBE354_MU_CNT(1),\n.C_PROBE355_MU_CNT(1),\n.C_PROBE356_MU_CNT(1),\n.C_PROBE357_MU_CNT(1),\n.C_PROBE358_MU_CNT(1),\n.C_PROBE359_MU_CNT(1),\n.C_PROBE360_MU_CNT(1),\n.C_PROBE361_MU_CNT(1),\n.C_PROBE362_MU_CNT(1),\n.C_PROBE363_MU_CNT(1),\n.C_PROBE364_MU_CNT(1),\n.C_PROBE365_MU_CNT(1),\n.C_PROBE366_MU_CNT(1),\n.C_PROBE367_MU_CNT(1),\n.C_PROBE368_MU_CNT(1),\n.C_PROBE369_MU_CNT(1),\n.C_PROBE370_MU_CNT(1),\n.C_PROBE371_MU_CNT(1),\n.C_PROBE372_MU_CNT(1),\n.C_PROBE373_MU_CNT(1),\n.C_PROBE374_MU_CNT(1),\n.C_PROBE375_MU_CNT(1),\n.C_PROBE376_MU_CNT(1),\n.C_PROBE377_MU_CNT(1),\n.C_PROBE378_MU_CNT(1),\n.C_PROBE379_MU_CNT(1),\n.C_PROBE380_MU_CNT(1),\n.C_PROBE381_MU_CNT(1),\n.C_PROBE382_MU_CNT(1),\n.C_PROBE383_MU_CNT(1),\n.C_PROBE384_MU_CNT(1),\n.C_PROBE385_MU_CNT(1),\n.C_PROBE386_MU_CNT(1),\n.C_PROBE387_MU_CNT(1),\n.C_PROBE388_MU_CNT(1),\n.C_PROBE389_MU_CNT(1),\n.C_PROBE390_MU_CNT(1),\n.C_PROBE391_MU_CNT(1),\n.C_PROBE392_MU_CNT(1),\n.C_PROBE393_MU_CNT(1),\n.C_PROBE394_MU_CNT(1),\n.C_PROBE395_MU_CNT(1),\n.C_PROBE396_MU_CNT(1),\n.C_PROBE397_MU_CNT(1),\n.C_PROBE398_MU_CNT(1),\n.C_PROBE399_MU_CNT(1),\n.C_PROBE400_MU_CNT(1),\n.C_PROBE401_MU_CNT(1),\n.C_PROBE402_MU_CNT(1),\n.C_PROBE403_MU_CNT(1),\n.C_PROBE404_MU_CNT(1),\n.C_PROBE405_MU_CNT(1),\n.C_PROBE406_MU_CNT(1),\n.C_PROBE407_MU_CNT(1),\n.C_PROBE408_MU_CNT(1),\n.C_PROBE409_MU_CNT(1),\n.C_PROBE410_MU_CNT(1),\n.C_PROBE411_MU_CNT(1),\n.C_PROBE412_MU_CNT(1),\n.C_PROBE413_MU_CNT(1),\n.C_PROBE414_MU_CNT(1),\n.C_PROBE415_MU_CNT(1),\n.C_PROBE416_MU_CNT(1),\n.C_PROBE417_MU_CNT(1),\n.C_PROBE418_MU_CNT(1),\n.C_PROBE419_MU_CNT(1),\n.C_PROBE420_MU_CNT(1),\n.C_PROBE421_MU_CNT(1),\n.C_PROBE422_MU_CNT(1),\n.C_PROBE423_MU_CNT(1),\n.C_PROBE424_MU_CNT(1),\n.C_PROBE425_MU_CNT(1),\n.C_PROBE426_MU_CNT(1),\n.C_PROBE427_MU_CNT(1),\n.C_PROBE428_MU_CNT(1),\n.C_PROBE429_MU_CNT(1),\n.C_PROBE430_MU_CNT(1),\n.C_PROBE431_MU_CNT(1),\n.C_PROBE432_MU_CNT(1),\n.C_PROBE433_MU_CNT(1),\n.C_PROBE434_MU_CNT(1),\n.C_PROBE435_MU_CNT(1),\n.C_PROBE436_MU_CNT(1),\n.C_PROBE437_MU_CNT(1),\n.C_PROBE438_MU_CNT(1),\n.C_PROBE439_MU_CNT(1),\n.C_PROBE440_MU_CNT(1),\n.C_PROBE441_MU_CNT(1),\n.C_PROBE442_MU_CNT(1),\n.C_PROBE443_MU_CNT(1),\n.C_PROBE444_MU_CNT(1),\n.C_PROBE445_MU_CNT(1),\n.C_PROBE446_MU_CNT(1),\n.C_PROBE447_MU_CNT(1),\n.C_PROBE448_MU_CNT(1),\n.C_PROBE449_MU_CNT(1),\n.C_PROBE450_MU_CNT(1),\n.C_PROBE451_MU_CNT(1),\n.C_PROBE452_MU_CNT(1),\n.C_PROBE453_MU_CNT(1),\n.C_PROBE454_MU_CNT(1),\n.C_PROBE455_MU_CNT(1),\n.C_PROBE456_MU_CNT(1),\n.C_PROBE457_MU_CNT(1),\n.C_PROBE458_MU_CNT(1),\n.C_PROBE459_MU_CNT(1),\n.C_PROBE460_MU_CNT(1),\n.C_PROBE461_MU_CNT(1),\n.C_PROBE462_MU_CNT(1),\n.C_PROBE463_MU_CNT(1),\n.C_PROBE464_MU_CNT(1),\n.C_PROBE465_MU_CNT(1),\n.C_PROBE466_MU_CNT(1),\n.C_PROBE467_MU_CNT(1),\n.C_PROBE468_MU_CNT(1),\n.C_PROBE469_MU_CNT(1),\n.C_PROBE470_MU_CNT(1),\n.C_PROBE471_MU_CNT(1),\n.C_PROBE472_MU_CNT(1),\n.C_PROBE473_MU_CNT(1),\n.C_PROBE474_MU_CNT(1),\n.C_PROBE475_MU_CNT(1),\n.C_PROBE476_MU_CNT(1),\n.C_PROBE477_MU_CNT(1),\n.C_PROBE478_MU_CNT(1),\n.C_PROBE479_MU_CNT(1),\n.C_PROBE480_MU_CNT(1),\n.C_PROBE481_MU_CNT(1),\n.C_PROBE482_MU_CNT(1),\n.C_PROBE483_MU_CNT(1),\n.C_PROBE484_MU_CNT(1),\n.C_PROBE485_MU_CNT(1),\n.C_PROBE486_MU_CNT(1),\n.C_PROBE487_MU_CNT(1),\n.C_PROBE488_MU_CNT(1),\n.C_PROBE489_MU_CNT(1),\n.C_PROBE490_MU_CNT(1),\n.C_PROBE491_MU_CNT(1),\n.C_PROBE492_MU_CNT(1),\n.C_PROBE493_MU_CNT(1),\n.C_PROBE494_MU_CNT(1),\n.C_PROBE495_MU_CNT(1),\n.C_PROBE496_MU_CNT(1),\n.C_PROBE497_MU_CNT(1),\n.C_PROBE498_MU_CNT(1),\n.C_PROBE499_MU_CNT(1),\n.C_PROBE500_MU_CNT(1),\n.C_PROBE501_MU_CNT(1),\n.C_PROBE502_MU_CNT(1),\n.C_PROBE503_MU_CNT(1),\n.C_PROBE504_MU_CNT(1),\n.C_PROBE505_MU_CNT(1),\n.C_PROBE506_MU_CNT(1),\n.C_PROBE507_MU_CNT(1),\n.C_PROBE508_MU_CNT(1),\n.C_PROBE509_MU_CNT(1),\n.C_PROBE510_MU_CNT(1),\n.C_PROBE511_MU_CNT(1),\n.C_PROBE512_MU_CNT(1),\n.C_PROBE513_MU_CNT(1),\n.C_PROBE514_MU_CNT(1),\n.C_PROBE515_MU_CNT(1),\n.C_PROBE516_MU_CNT(1),\n.C_PROBE517_MU_CNT(1),\n.C_PROBE518_MU_CNT(1),\n.C_PROBE519_MU_CNT(1),\n.C_PROBE520_MU_CNT(1),\n.C_PROBE521_MU_CNT(1),\n.C_PROBE522_MU_CNT(1),\n.C_PROBE523_MU_CNT(1),\n.C_PROBE524_MU_CNT(1),\n.C_PROBE525_MU_CNT(1),\n.C_PROBE526_MU_CNT(1),\n.C_PROBE527_MU_CNT(1),\n.C_PROBE528_MU_CNT(1),\n.C_PROBE529_MU_CNT(1),\n.C_PROBE530_MU_CNT(1),\n.C_PROBE531_MU_CNT(1),\n.C_PROBE532_MU_CNT(1),\n.C_PROBE533_MU_CNT(1),\n.C_PROBE534_MU_CNT(1),\n.C_PROBE535_MU_CNT(1),\n.C_PROBE536_MU_CNT(1),\n.C_PROBE537_MU_CNT(1),\n.C_PROBE538_MU_CNT(1),\n.C_PROBE539_MU_CNT(1),\n.C_PROBE540_MU_CNT(1),\n.C_PROBE541_MU_CNT(1),\n.C_PROBE542_MU_CNT(1),\n.C_PROBE543_MU_CNT(1),\n.C_PROBE544_MU_CNT(1),\n.C_PROBE545_MU_CNT(1),\n.C_PROBE546_MU_CNT(1),\n.C_PROBE547_MU_CNT(1),\n.C_PROBE548_MU_CNT(1),\n.C_PROBE549_MU_CNT(1),\n.C_PROBE550_MU_CNT(1),\n.C_PROBE551_MU_CNT(1),\n.C_PROBE552_MU_CNT(1),\n.C_PROBE553_MU_CNT(1),\n.C_PROBE554_MU_CNT(1),\n.C_PROBE555_MU_CNT(1),\n.C_PROBE556_MU_CNT(1),\n.C_PROBE557_MU_CNT(1),\n.C_PROBE558_MU_CNT(1),\n.C_PROBE559_MU_CNT(1),\n.C_PROBE560_MU_CNT(1),\n.C_PROBE561_MU_CNT(1),\n.C_PROBE562_MU_CNT(1),\n.C_PROBE563_MU_CNT(1),\n.C_PROBE564_MU_CNT(1),\n.C_PROBE565_MU_CNT(1),\n.C_PROBE566_MU_CNT(1),\n.C_PROBE567_MU_CNT(1),\n.C_PROBE568_MU_CNT(1),\n.C_PROBE569_MU_CNT(1),\n.C_PROBE570_MU_CNT(1),\n.C_PROBE571_MU_CNT(1),\n.C_PROBE572_MU_CNT(1),\n.C_PROBE573_MU_CNT(1),\n.C_PROBE574_MU_CNT(1),\n.C_PROBE575_MU_CNT(1),\n.C_PROBE576_MU_CNT(1),\n.C_PROBE577_MU_CNT(1),\n.C_PROBE578_MU_CNT(1),\n.C_PROBE579_MU_CNT(1),\n.C_PROBE580_MU_CNT(1),\n.C_PROBE581_MU_CNT(1),\n.C_PROBE582_MU_CNT(1),\n.C_PROBE583_MU_CNT(1),\n.C_PROBE584_MU_CNT(1),\n.C_PROBE585_MU_CNT(1),\n.C_PROBE586_MU_CNT(1),\n.C_PROBE587_MU_CNT(1),\n.C_PROBE588_MU_CNT(1),\n.C_PROBE589_MU_CNT(1),\n.C_PROBE590_MU_CNT(1),\n.C_PROBE591_MU_CNT(1),\n.C_PROBE592_MU_CNT(1),\n.C_PROBE593_MU_CNT(1),\n.C_PROBE594_MU_CNT(1),\n.C_PROBE595_MU_CNT(1),\n.C_PROBE596_MU_CNT(1),\n.C_PROBE597_MU_CNT(1),\n.C_PROBE598_MU_CNT(1),\n.C_PROBE599_MU_CNT(1),\n.C_PROBE600_MU_CNT(1),\n.C_PROBE601_MU_CNT(1),\n.C_PROBE602_MU_CNT(1),\n.C_PROBE603_MU_CNT(1),\n.C_PROBE604_MU_CNT(1),\n.C_PROBE605_MU_CNT(1),\n.C_PROBE606_MU_CNT(1),\n.C_PROBE607_MU_CNT(1),\n.C_PROBE608_MU_CNT(1),\n.C_PROBE609_MU_CNT(1),\n.C_PROBE610_MU_CNT(1),\n.C_PROBE611_MU_CNT(1),\n.C_PROBE612_MU_CNT(1),\n.C_PROBE613_MU_CNT(1),\n.C_PROBE614_MU_CNT(1),\n.C_PROBE615_MU_CNT(1),\n.C_PROBE616_MU_CNT(1),\n.C_PROBE617_MU_CNT(1),\n.C_PROBE618_MU_CNT(1),\n.C_PROBE619_MU_CNT(1),\n.C_PROBE620_MU_CNT(1),\n.C_PROBE621_MU_CNT(1),\n.C_PROBE622_MU_CNT(1),\n.C_PROBE623_MU_CNT(1),\n.C_PROBE624_MU_CNT(1),\n.C_PROBE625_MU_CNT(1),\n.C_PROBE626_MU_CNT(1),\n.C_PROBE627_MU_CNT(1),\n.C_PROBE628_MU_CNT(1),\n.C_PROBE629_MU_CNT(1),\n.C_PROBE630_MU_CNT(1),\n.C_PROBE631_MU_CNT(1),\n.C_PROBE632_MU_CNT(1),\n.C_PROBE633_MU_CNT(1),\n.C_PROBE634_MU_CNT(1),\n.C_PROBE635_MU_CNT(1),\n.C_PROBE636_MU_CNT(1),\n.C_PROBE637_MU_CNT(1),\n.C_PROBE638_MU_CNT(1),\n.C_PROBE639_MU_CNT(1),\n.C_PROBE640_MU_CNT(1),\n.C_PROBE641_MU_CNT(1),\n.C_PROBE642_MU_CNT(1),\n.C_PROBE643_MU_CNT(1),\n.C_PROBE644_MU_CNT(1),\n.C_PROBE645_MU_CNT(1),\n.C_PROBE646_MU_CNT(1),\n.C_PROBE647_MU_CNT(1),\n.C_PROBE648_MU_CNT(1),\n.C_PROBE649_MU_CNT(1),\n.C_PROBE650_MU_CNT(1),\n.C_PROBE651_MU_CNT(1),\n.C_PROBE652_MU_CNT(1),\n.C_PROBE653_MU_CNT(1),\n.C_PROBE654_MU_CNT(1),\n.C_PROBE655_MU_CNT(1),\n.C_PROBE656_MU_CNT(1),\n.C_PROBE657_MU_CNT(1),\n.C_PROBE658_MU_CNT(1),\n.C_PROBE659_MU_CNT(1),\n.C_PROBE660_MU_CNT(1),\n.C_PROBE661_MU_CNT(1),\n.C_PROBE662_MU_CNT(1),\n.C_PROBE663_MU_CNT(1),\n.C_PROBE664_MU_CNT(1),\n.C_PROBE665_MU_CNT(1),\n.C_PROBE666_MU_CNT(1),\n.C_PROBE667_MU_CNT(1),\n.C_PROBE668_MU_CNT(1),\n.C_PROBE669_MU_CNT(1),\n.C_PROBE670_MU_CNT(1),\n.C_PROBE671_MU_CNT(1),\n.C_PROBE672_MU_CNT(1),\n.C_PROBE673_MU_CNT(1),\n.C_PROBE674_MU_CNT(1),\n.C_PROBE675_MU_CNT(1),\n.C_PROBE676_MU_CNT(1),\n.C_PROBE677_MU_CNT(1),\n.C_PROBE678_MU_CNT(1),\n.C_PROBE679_MU_CNT(1),\n.C_PROBE680_MU_CNT(1),\n.C_PROBE681_MU_CNT(1),\n.C_PROBE682_MU_CNT(1),\n.C_PROBE683_MU_CNT(1),\n.C_PROBE684_MU_CNT(1),\n.C_PROBE685_MU_CNT(1),\n.C_PROBE686_MU_CNT(1),\n.C_PROBE687_MU_CNT(1),\n.C_PROBE688_MU_CNT(1),\n.C_PROBE689_MU_CNT(1),\n.C_PROBE690_MU_CNT(1),\n.C_PROBE691_MU_CNT(1),\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synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 4261}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_master #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_SUPPORTS_NARROW = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1,\n   parameter [C_AXI_ADDR_WIDTH-1:0] C_AXI_ADDR = 0,  // Base address\n   parameter integer C_NUM_ADDR = 1,  // Number of address iterations; range 1..2**16 (fixed increment = 32'h10000\n   parameter integer C_NUM_ID = 1,  // Number of ID iterations; range 1..2**C_ID_WIDTH (base = 0; fixed increment = 1)\n   parameter integer C_NUM_LEN = 1,  // Number of LEN iterations; range 1..9 (base = 0; value = 2**i - 1)\n   parameter integer C_NUM_TRANS = 1  // Number of transactions; range >=1 (read and write)\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_awvalid,\n  input  wire                            m_axi_awready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_awburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_awlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_awlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_awid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]    m_axi_awuser = 'b0,\n  /**************** Write Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_wid,\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]      m_axi_wdata,\n  (* dont_touch=\"true\" *) output reg [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb = {(C_AXI_DATA_WIDTH/8){1'b1}},\n  (* dont_touch=\"true\" *) output wire                             m_axi_wvalid,\n  input  wire                            m_axi_wready,\n  (* dont_touch=\"true\" *) output wire                             m_axi_wlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]     m_axi_wuser = 'b0,\n  /**************** Write Response Channel Signals ****************/\n  input  wire [2-1:0]                    m_axi_bresp,\n  input  wire                            m_axi_bvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_bready,\n  input  wire [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]     m_axi_buser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_bid,\n  /**************** Read Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_arvalid,\n  input  wire                            m_axi_arready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_arburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_arlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_arlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_arid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]    m_axi_aruser = 'b0,\n  /**************** Read Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]      m_axi_rdata,\n  input  wire [2-1:0]                    m_axi_rresp,\n  input  wire                            m_axi_rvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_rready,\n  input  wire                            m_axi_rlast,\n  input  wire [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]     m_axi_ruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_rid,\n  /**************** System Signals ****************/\n  input  wire                            aclk,\n  input  wire                            aresetn\n  );\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n  localparam integer  P_NUM_ID_LOG = f_ceil_log2(C_NUM_ID);\n  localparam integer  P_NUM_ADDR_LOG = f_ceil_log2(C_NUM_ADDR);\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL==0 ? 8 : C_AXI_PROTOCOL==1 ? 4 : 1);\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer               P_M_AXI_DATA_BYTES = (C_AXI_DATA_WIDTH / 8);\n  localparam integer               P_M_AXI_DONE_WIDTH = f_ceil_log2(C_NUM_TRANS<2?2:C_NUM_TRANS);\n  localparam integer               P_M_AXI_SIZE = f_ceil_log2(C_AXI_DATA_WIDTH)-3;\n\n  /**************** Internal Wires/Regs - Global ****************/\n   wire                            done;\n    wire                            dummy ;\n  reg                         done_i;\n  reg                         done_sel;\n  wire                         done_cycle;\n  reg                          done_d1 = 1'b0;\n  reg                   areset = 1'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] arcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] rcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [3:0]                    acc_r_i = 4'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] awcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] wcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] bcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [2:0]                    acc_b_i = 3'b0;\n\n  // Register Reset\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    \n    /**************** Internal Wires/Regs - Read Channels ****************/\n    wire                         read_xaction_done_i;\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_arid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_ADDR_WIDTH:0]      araddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  arprot_i = 3'b0;\n    reg [3-1:0]                  arsize_i = 3'b0;\n    reg [2-1:0]                  arburst_i = 2'b0;\n    reg [4-1:0]                  arcache_i = 4'b0;\n    reg [2-1:0]                  arlock_i = 2'b0;\n    reg [P_LEN_WIDTH-1:0]     arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [4-1:0]                  arqos_i = 4'b0;\n    reg [P_ID_WIDTH-1:0]        arid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [2-1:0]                  rresp_i = 2'b00;\n    reg [C_AXI_RUSER_WIDTH:0]   ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      rid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_arvalid_i = 1'b0;\n    reg                        m_axi_rready_i = 1'b0;\n    reg [P_NUM_ADDR_LOG:0]    araddr_cnt = 0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign read_xaction_done_i = m_axi_rvalid && m_axi_rready_i && ((C_AXI_PROTOCOL==2)?1'b1:m_axi_rlast);\n    assign m_axi_arvalid = m_axi_arvalid_i;\n    assign m_axi_rready = m_axi_rready_i;\n    assign m_axi_araddr = m_axi_araddr_i;\n    assign m_axi_arlen = m_axi_arlen_i;\n    always @(posedge aclk) begin\n      m_axi_arprot <= dummy ? arprot_i : 3'b000;\n      m_axi_arsize <= dummy ? arsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_arburst <= dummy ? arburst_i : 2'b01;\n      m_axi_arlock <= dummy ? arlock_i : 1'b0;\n      m_axi_arcache <= dummy ? arcache_i : 4'h3;\n      m_axi_arqos <= dummy  ? arqos_i : 4'h0;\n      m_axi_aruser <= dummy ? aruser_i : 0;\n    end\n  \n    //**********************************************\n    // Read Channel: ARVALID, ARADDR, ARLEN, RREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_arvalid_i <= 1'b0;\n        arcnt_i <= C_NUM_TRANS;\n        m_axi_arlen_i <= 0;\n        m_axi_araddr_i <= C_AXI_ADDR;\n        m_axi_arid_i <= 1;\n        araddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_arready & m_axi_arvalid_i) begin\n          arcnt_i <= arcnt_i - 1;\n          if (araddr_cnt == 1) begin\n            m_axi_araddr_i <= dummy ? araddr_i : C_AXI_ADDR;\n            araddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_araddr_i <= m_axi_araddr_i + 32'h10000;\n            araddr_cnt <= araddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_arlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_arlen_i <= dummy ? arlen_i : 0;\n          end else begin\n            m_axi_arlen_i <= (m_axi_arlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_arid_i == C_NUM_ID)) begin\n            m_axi_arid <= dummy ? arid_i : 0;\n            m_axi_arid_i <= 1;\n          end else begin\n            m_axi_arid <= m_axi_arid_i;\n            m_axi_arid_i <= m_axi_arid_i + 1;\n          end\n          if (arcnt_i == 1) begin\n            m_axi_arvalid_i <= 1'b0;\n          end\n        end else if (arcnt_i != 0) begin\n          m_axi_arvalid_i <= 1'b1;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      araddr_i <= {araddr_i, ~araddr_i[C_AXI_ADDR_WIDTH]};\n      arprot_i <= {arprot_i, ~arprot_i[3-1]};\n      arlen_i <= {arlen_i, ~arlen_i[P_LEN_WIDTH-1]};\n      arsize_i <= {arsize_i, ~arsize_i[3-1]};\n      arburst_i <= {arburst_i, ~arburst_i[2-1]};\n      arlock_i <= {arlock_i, ~arlock_i[2-1]};\n      arcache_i <= {arcache_i, ~arcache_i[4-1]};\n      arqos_i <= {arqos_i, ~arqos_i[4-1]};\n      aruser_i <= {aruser_i, ~aruser_i[C_AXI_ARUSER_WIDTH]};\n      arid_i <= {arid_i, ~arid_i[P_ID_WIDTH-1]};\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        m_axi_rready_i <= 1'b0;\n        rcnt_i <= C_NUM_TRANS;\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        rresp_i <= {2{1'b0}};\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n        rid_i <= {P_ID_WIDTH{1'b0}};\n        acc_r_i <= 4'b0;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_rvalid & m_axi_rready_i) begin\n          m_axi_rready_i <= 1'b0;\n          rdata_i <= m_axi_rdata;\n            acc_r_i[0] <= rdata_i[0];\n          rresp_i <= m_axi_rresp;\n            acc_r_i[1] <= rresp_i[0];\n          ruser_i <= m_axi_ruser;\n            acc_r_i[2] <= ruser_i[0];\n          rid_i <= m_axi_rid;\n            acc_r_i[3] <= rid_i[0];\n          if (m_axi_rlast) begin\n            rcnt_i <= rcnt_i - 1;\n          end\n        end else begin\n          rdata_i <= rdata_i>>1;\n          rresp_i <= rresp_i>>1;\n          ruser_i <= ruser_i>>1;\n          rid_i <= rid_i>>1;\n          acc_r_i <= acc_r_i>>1;\n          if (m_axi_rvalid) begin\n            m_axi_rready_i <= 1'b1;\n          end\n        end\n      end\n    end\n    \n    assign dummy = rdata_i[0];\n    \n    \n\n    /**************** Internal Wires/Regs - Write Channels ****************/\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_awid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [8-1:0]                  xfer_w_i = 8'h00;\n    wire                         write_burst_done_i;\n    reg [C_AXI_ADDR_WIDTH:0]      awaddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  awprot_i = 3'b0;\n    reg [P_LEN_WIDTH-1:0]     awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [3-1:0]                  awsize_i = 3'b0;\n    reg [2-1:0]                  awburst_i = 2'b0;\n    reg [4-1:0]                  awcache_i = 4'b0;\n    reg [2-1:0]                  awlock_i = 2'b0;\n    reg [4-1:0]                  awqos_i = 4'b0;\n    reg [P_ID_WIDTH:0]        awid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_AWUSER_WIDTH:0]    awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg [P_M_AXI_DATA_BYTES-1:0] wstrb_i = {P_M_AXI_DATA_BYTES{1'b1}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]        wid_i = {P_ID_WIDTH{1'b0}};\n    reg [2-1:0]                  bresp_i = 2'b00;\n    reg [C_AXI_BUSER_WIDTH:0]   buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      bid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_awvalid_i = 1'b0;\n    reg                        m_axi_wvalid_i = 1'b0;\n    reg                        m_axi_bready_i = 1'b0;\n    reg                        m_axi_wlast_i = 1'b0;\n    reg                        m_axi_wid_i = {P_ID_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]     wlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [P_NUM_ADDR_LOG:0]    awaddr_cnt = 0;\n  \n    /**************** Assign Write Channel Outputs ****************/\n    assign m_axi_wdata = {wdata_i, done};\n    assign write_burst_done_i = m_axi_wready && m_axi_wvalid_i && ((C_AXI_PROTOCOL==2) || m_axi_wlast_i);\n    assign m_axi_awvalid = m_axi_awvalid_i;\n    assign m_axi_wvalid = m_axi_wvalid_i;\n    assign m_axi_bready = m_axi_bready_i;\n    assign m_axi_wlast = m_axi_wlast_i;\n    assign m_axi_awaddr = m_axi_awaddr_i;\n    assign m_axi_awlen = m_axi_awlen_i;\n    assign m_axi_wid = m_axi_wid_i;\n    always @(posedge aclk) begin\n      m_axi_awprot <= dummy ? awprot_i : 3'b000;\n      m_axi_awsize <= dummy ? awsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_awburst <= dummy ? awburst_i : 2'b01;\n      m_axi_awlock <= dummy ? awlock_i : 1'b0;\n      m_axi_awcache <= dummy ? awcache_i : 4'h3;\n      m_axi_awqos <= dummy ? awqos_i : 4'h0;\n      m_axi_wstrb <= dummy ? wstrb_i : {P_M_AXI_DATA_BYTES{1'b1}};\n      m_axi_awuser <= dummy ?  awuser_i : 0;\n      m_axi_wuser <= dummy ?  wuser_i : 0;\n    end\n  \n    //**********************************************\n    // Write Channel: AWVALID, AWADDR, AWLEN, WVALID, WLAST, BREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_awvalid_i <= 1'b0;\n        m_axi_wvalid_i <= 1'b0;\n        awcnt_i <= C_NUM_TRANS;\n        wcnt_i <= C_NUM_TRANS;\n        xfer_w_i <= 8'h00;\n        m_axi_awlen_i <= 0;\n        m_axi_awaddr_i <= C_AXI_ADDR;\n        m_axi_awid_i <= 1;\n        m_axi_wid_i <= 0;\n        m_axi_wlast_i <= 1'b0;\n        wlen_i <= 0;\n        wid_i <= 0;\n        awaddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_awvalid_i <= 1'b0;\n          awcnt_i <= awcnt_i - 1;\n          if (awaddr_cnt == 1) begin\n            m_axi_awaddr_i <= dummy ? awaddr_i : C_AXI_ADDR;\n            awaddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_awaddr_i <= m_axi_awaddr_i + 32'h10000;\n            awaddr_cnt <= awaddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_awlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_awlen_i <= dummy ? awlen_i : 0;\n          end else begin\n            m_axi_awlen_i <= (m_axi_awlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_awid_i == C_NUM_ID)) begin\n            m_axi_awid <= dummy ? awid_i : 0;\n            m_axi_awid_i <= 1;\n          end else begin\n            m_axi_awid <= m_axi_awid_i;\n            m_axi_awid_i <= m_axi_awid_i + 1;\n          end\n        end else if (~m_axi_wvalid_i) begin\n          if (awcnt_i != 0) begin\n            m_axi_awvalid_i <= 1'b1;\n          end\n        end\n  \n        /**************** Write Data Channel ****************/\n\n        if (m_axi_wready && m_axi_wvalid_i) begin\n          xfer_w_i <= xfer_w_i - 1'b1;\n          if (m_axi_wlast_i) begin\n            m_axi_wvalid_i <= 1'b0;\n            wcnt_i <= wcnt_i - 1'b1;\n          end else begin\n            m_axi_wlast_i <=  (xfer_w_i == 1);\n          end\n        end else if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_wvalid_i <= 1'b1;\n          xfer_w_i <= m_axi_awlen_i;\n          m_axi_wlast_i <= (m_axi_awlen_i==0);\n          m_axi_wid_i <= m_axi_awid_i;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: WDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        wdata_i <= (m_axi_wvalid_i && m_axi_wready) ? {wdata_i[C_AXI_DATA_WIDTH-2 : 0], ~wdata_i[C_AXI_DATA_WIDTH-1]} : wdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      awaddr_i <= {awaddr_i, ~awaddr_i[C_AXI_ADDR_WIDTH]};\n      awprot_i <= {awprot_i[3-2:0], ~awprot_i[3-1]};\n      wstrb_i <= {wstrb_i, ~wstrb_i[C_AXI_DATA_WIDTH/8-1]};\n      awlen_i <= {awlen_i, ~awlen_i[P_LEN_WIDTH-1]};\n      awsize_i <= {awsize_i, ~awsize_i[3-1]};\n      awburst_i <= {awburst_i, ~awburst_i[2-1]};\n      awlock_i <= {awlock_i, ~awlock_i[2-1]};\n      awcache_i <= {awcache_i, ~awcache_i[4-1]};\n      awqos_i <= {awqos_i, ~awqos_i[4-1]};\n      awid_i <= {awid_i, ~awid_i[P_ID_WIDTH-1]};\n      awuser_i <= {awuser_i, ~awuser_i[C_AXI_AWUSER_WIDTH]};\n      wuser_i <= {wuser_i, ~wuser_i[C_AXI_WUSER_WIDTH]};\n    end\n  \n    //**********************************************\n    // Write Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_bready_i <= 1'b0;\n        bcnt_i <= C_NUM_TRANS;\n        bresp_i <= {2{1'b0}};\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n        bid_i <= {P_ID_WIDTH{1'b0}};\n        acc_b_i <= 3'b0;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_bvalid & m_axi_bready_i) begin\n          m_axi_bready_i <= 1'b0;\n          bresp_i <= m_axi_bresp;\n            acc_b_i[0] <= bresp_i[0];\n          buser_i <= m_axi_buser;\n            acc_b_i[1] <= buser_i[0];\n          bid_i <= m_axi_bid;\n            acc_b_i[2] <= bid_i[0];\n          bcnt_i <= bcnt_i - 1;\n        end else begin\n          bresp_i <= bresp_i>>1;\n          buser_i <= buser_i>>1;\n          bid_i <= bid_i>>1;\n          acc_b_i <= acc_b_i>>1;\n          if (m_axi_bvalid) begin\n            m_axi_bready_i <= 1'b1;\n          end\n        end\n      end\n    end\n\n\n  //**********************************************\n  // Assert Done\n  //**********************************************\n  always @(posedge aclk) begin\n    if (~aresetn) begin\n      done_d1 <= 1'b0;\n    end else begin\n      done_d1 <= done_i;\n    end\n  end\n\n  assign done = done_sel ? done_i : done_d1;\n  assign done_cycle = done_i & ~done_d1;\n  \n  always @ * begin\n    if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_readonly_done\n       done_i = rcnt_i==0;\n       done_sel = acc_r_i[0];\n    end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_writeonly_done\n       done_i = bcnt_i==0;\n       done_sel = acc_b_i[0];\n    end else begin : gen_readwrite_done\n       done_i = (rcnt_i==0) && (bcnt_i==0);\n       done_sel = acc_r_i[0] ^ acc_b_i[0];\n    end\n  end\n  \nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n  input  wire [3-1:0]                   s_axi_awprot,\n  input  wire                           s_axi_awvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_awready,\n  input  wire [3-1:0]                   s_axi_awsize,\n  input  wire [2-1:0]                   s_axi_awburst,\n  input  wire [4-1:0]                   s_axi_awcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_awlen,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_awlock,\n  input  wire [4-1:0]                   s_axi_awqos,\n  input  wire [4-1:0]                   s_axi_awregion,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_awid,\n  input  wire [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]   s_axi_awuser,\n  /**************** Write Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n  input  wire                           s_axi_wvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_wready,\n  input  wire                           s_axi_wlast,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_wid,\n  input  wire [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]    s_axi_wuser,\n  /**************** Write Response Channel Signals ****************/\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_bresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_bvalid,\n  input  wire                           s_axi_bready,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]    s_axi_buser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_bid = 'b0,\n  /**************** Read Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n  input  wire [3-1:0]                   s_axi_arprot,\n  input  wire                           s_axi_arvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_arready,\n  input  wire [3-1:0]                   s_axi_arsize,\n  input  wire [2-1:0]                   s_axi_arburst,\n  input  wire [4-1:0]                   s_axi_arcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_arlock,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_arlen,\n  input  wire [4-1:0]                   s_axi_arqos,\n  input  wire [4-1:0]                   s_axi_arregion,\n  input  wire [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]   s_axi_aruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_arid,\n  /**************** Read Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_rresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rvalid,\n  input  wire                           s_axi_rready,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]    s_axi_ruser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_rid = 'b0,\n  /**************** System Signals ****************/\n  input  wire                           aclk,\n  input  wire                           aresetn\n   );\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL == 1) ? 4 : 8;\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer P_S_AXI_DATA_BYTES = 32/8;\n  localparam integer P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n\n  /**************** Internal Wires/Regs - Global ****************/\n  reg                   areset = 1'b0;\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    /**************** Internal Wires/Regs - Read Channels ****************/\n    reg [8-1:0]                   xfer_r_cnt = 8'h00;\n    reg [16-1:0]                  arcnt_i = 16'h0000;\n    wire                          read_xaction_done_i;\n    reg [C_AXI_DATA_WIDTH-1:0]     rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]      arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg                           arvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     araddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   arprot_i = 3'b000;\n    reg [3-1:0]                   arsize_i = 3'b000;\n    reg [2-1:0]                   arburst_i = 2'b00;\n    reg [4-1:0]                   arcache_i = 4'b0000;\n    reg [1-1:0]     arlock_i = 1'b0;\n    reg [4-1:0]                   arqos_i = 4'b0000;\n    reg [4-1:0]                   arregion_i = 4'b0000;\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_RUSER_WIDTH:0]     ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_ar_i = 9'b0;\n    reg                           s_axi_rvalid_i = 1'b0;\n    reg                           s_axi_arready_i = 1'b0;\n    reg                           s_axi_rlast_i = 1'b0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign s_axi_rdata = rdata_i;\n    assign read_xaction_done_i = (s_axi_rready && s_axi_rvalid_i && s_axi_rlast_i);\n    assign s_axi_rvalid = s_axi_rvalid_i;\n    assign s_axi_arready = s_axi_arready_i;\n    assign s_axi_rlast = s_axi_rlast_i;\n    //**********************************************\n    // Read Channel: ARREADY, RVALID, RLAST, RID\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        xfer_r_cnt <= 8'h00;\n        arcnt_i <= 16'h0000;\n        arlen_i <= {P_LEN_WIDTH{1'b0}};\n        s_axi_rlast_i <= 1'b0;\n      end else begin\n        /**************** Read Address Channel ****************/\n        // arready\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_arready_i <= 1'b0;\n          arcnt_i <= arcnt_i + 1'b1;\n        end else if (~s_axi_rvalid_i) begin\n          s_axi_arready_i <= 1'b1;\n        end\n  \n        /**************** Read Data Channel ****************/\n        // rvalid\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_rvalid_i <= 1'b1;\n          s_axi_rid <= s_axi_arid;\n          s_axi_ruser <= ruser_i;\n        end else if(read_xaction_done_i) begin\n          s_axi_rvalid_i <= 1'b0;\n        end\n  \n        // rlast\n        if(s_axi_rready && s_axi_rvalid_i) begin\n          xfer_r_cnt <= xfer_r_cnt - 1;\n          if(xfer_r_cnt == 1) begin\n            s_axi_rlast_i <= 1'b1;\n          end\n        end else if(s_axi_arready_i && s_axi_arvalid) begin\n          xfer_r_cnt <= s_axi_arlen;\n          s_axi_rlast_i <= (s_axi_arlen==0);\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Read Channel: RDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        rdata_i <= (s_axi_rready && s_axi_rvalid_i) ? {rdata_i[C_AXI_DATA_WIDTH-2 : 0], ~rdata_i[C_AXI_DATA_WIDTH-1]} : rdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_rresp <= {2{1'b0}};\n      end else if (~s_axi_rvalid_i) begin\n        s_axi_rresp <= {acc_ar_i[0], 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n      end else begin\n        ruser_i <= (s_axi_arready_i && s_axi_arvalid) ? {ruser_i, ~ruser_i[C_AXI_RUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        araddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        arprot_i <= {3{1'b0}};\n        arsize_i <= {3{1'b0}};\n        arburst_i <= {2{1'b0}};\n        arcache_i <= {4{1'b0}};\n        arlock_i <= {1{1'b0}};\n        arqos_i <= {4{1'b0}};\n        arregion_i <= {4{1'b0}};\n        aruser_i <= {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n        acc_ar_i <= 9'b0;\n      end else if (s_axi_arvalid) begin\n        // Register Inputs\n        araddr_i <= s_axi_araddr;\n          acc_ar_i[0] <= araddr_i[0];\n        arprot_i <= s_axi_arprot;\n          acc_ar_i[1] <= arprot_i[0];\n        arsize_i <= s_axi_arsize;\n          acc_ar_i[2] <= arsize_i[0];\n        arburst_i <= s_axi_arburst;\n          acc_ar_i[3] <= arburst_i[0];\n        arcache_i <= s_axi_arcache;\n          acc_ar_i[4] <= arcache_i[0];\n        arlock_i <= s_axi_arlock;\n          acc_ar_i[5] <= arlock_i[0];\n        arqos_i <= s_axi_arqos;\n          acc_ar_i[6] <= arqos_i[0];\n        arregion_i <= s_axi_arregion;\n          acc_ar_i[7] <= arregion_i[0];\n        aruser_i <= s_axi_aruser;\n          acc_ar_i[8] <= aruser_i[0];\n      end else begin\n        araddr_i <= araddr_i>>1;\n        arprot_i <= arprot_i>>1;\n        arsize_i <= arsize_i>>1;\n        arburst_i <= arburst_i>>1;\n        arcache_i <= arcache_i>>1;\n        arlock_i <= arlock_i>>1;\n        arqos_i <= arqos_i>>1;\n        arregion_i <= arregion_i>>1;\n        aruser_i <= aruser_i>>1;\n        acc_ar_i <= acc_ar_i>>1;\n      end\n    end\n  \n  \n    /**************** Internal Wires/Regs - Write Channels ****************/\n    wire                          write_burst_done_i;\n    reg [16-1:0]                  awcnt_i = 16'h0000;\n    reg                           awvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     awaddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   awprot_i = 3'b000;\n    reg [3-1:0]                   awsize_i = 3'b000;\n    reg [2-1:0]                   awburst_i = 2'b00;\n    reg [4-1:0]                   awcache_i = 4'b0000;\n    reg [P_LEN_WIDTH-1:0]      awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [1-1:0]     awlock_i = 1'b0;\n    reg [4-1:0]                   awqos_i = 4'b0000;\n    reg [4-1:0]                   awregion_i = 4'b0000;\n    reg [C_AXI_AWUSER_WIDTH:0]     awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg                           wvalid_i = 1'b0;\n    reg [C_AXI_DATA_WIDTH-1:0]     wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH/8-1:0]   wstrb_i = {(C_AXI_DATA_WIDTH/8){1'b0}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_BUSER_WIDTH:0]     buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_aw_i = 9'b0;\n    reg [3:0]                     acc_w_i = 4'b0;\n    reg                           s_axi_bvalid_i = 1'b0;\n    reg                           s_axi_awready_i = 1'b0;\n    reg                           s_axi_wready_i = 1'b0;\n    /**************** Assign Write Channel Outputs ****************/\n    assign write_burst_done_i =s_axi_wready_i && s_axi_wvalid && ((C_AXI_PROTOCOL == 2) ? 1'b1 : s_axi_wlast);\n    assign s_axi_bvalid = s_axi_bvalid_i;\n    assign s_axi_awready = s_axi_awready_i;\n    assign s_axi_wready = s_axi_wready_i;\n  \n    //**********************************************\n    // Write Channel: AWREADY, WREADY, BVALID, BID\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awcnt_i <= 16'h0000;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        /**************** Write Address Channel ****************/\n        // awready\n        if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_awready_i <= 1'b0;\n          awcnt_i <= awcnt_i + 1'b1;\n          s_axi_bid <= s_axi_awid;\n          s_axi_buser <= buser_i;\n        end else if(~s_axi_wready_i & ~s_axi_bvalid_i) begin\n          s_axi_awready_i <= 1'b1;\n        end\n  \n        /**************** Write Data Channel ****************/\n        // wready\n        if(write_burst_done_i) begin\n          s_axi_wready_i <= 1'b0;\n        end else if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_wready_i <= 1'b1;\n        end\n  \n        /**************** Write Response Channel ****************/\n        // bvalid\n        if(write_burst_done_i) begin\n          s_axi_bvalid_i <= 1'b1;\n        end else if(s_axi_bready && s_axi_bvalid_i) begin\n          s_axi_bvalid_i <= 1'b0;\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Write Channel: BRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_bresp <= {2{1'b0}};\n      end else if (~s_axi_bvalid_i) begin\n        s_axi_bresp <= {(acc_aw_i[0] ^ acc_w_i[0]), 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: BUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (aresetn) begin\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n      end else begin\n        buser_i <= (s_axi_awready_i && s_axi_awvalid) ? {buser_i, ~buser_i[C_AXI_BUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Write Address Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awaddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        awprot_i <= {3{1'b0}};\n        awsize_i <= {3{1'b0}};\n        awburst_i <= {2{1'b0}};\n        awcache_i <= {4{1'b0}};\n        awlen_i <= {P_LEN_WIDTH{1'b0}};\n        awlock_i <= {1{1'b0}};\n        awqos_i <= {4{1'b0}};\n        awregion_i <= {4{1'b0}};\n        awuser_i <= {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n        acc_aw_i <= 9'b0;\n      end else if (s_axi_awvalid) begin\n        // Register Inputs\n        awaddr_i <= s_axi_awaddr;\n          acc_aw_i[0] <= awaddr_i[0];\n        awprot_i <= s_axi_awprot;\n          acc_aw_i[1] <= awprot_i[0];\n        awsize_i <= s_axi_awsize;\n          acc_aw_i[2] <= awsize_i[0];\n        awburst_i <= s_axi_awburst;\n          acc_aw_i[3] <= awburst_i[0];\n        awcache_i <= s_axi_awcache;\n          acc_aw_i[4] <= awcache_i[0];\n        awlock_i <= s_axi_awlock;\n          acc_aw_i[5] <= awlock_i[0];\n        awqos_i <= s_axi_awqos;\n          acc_aw_i[6] <= awqos_i[0];\n        awregion_i <= s_axi_awregion;\n          acc_aw_i[7] <= awregion_i[0];\n        awuser_i <= s_axi_awuser;\n          acc_aw_i[8] <= awuser_i[0];\n      end else begin\n        awaddr_i <= awaddr_i>>1;\n        awprot_i <= awprot_i>>1;\n        awsize_i <= awsize_i>>1;\n        awburst_i <= awburst_i>>1;\n        awcache_i <= awcache_i>>1;\n        awlock_i <= awlock_i>>1;\n        awqos_i <= awqos_i>>1;\n        awregion_i <= awregion_i>>1;\n        awuser_i <= awuser_i>>1;\n        acc_aw_i <= acc_aw_i>>1;\n      end\n    end\n  \n    //**********************************************\n    // Write Data Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        wstrb_i <= {(C_AXI_DATA_WIDTH/8){1'b0}};\n        wuser_i <= {(C_AXI_WUSER_WIDTH+1){1'b0}};\n        acc_w_i <= 4'b0;\n      end else if (s_axi_wvalid) begin\n        // Register Inputs\n        wdata_i <= s_axi_wdata;\n          acc_w_i[0] <= wdata_i[0];\n        wstrb_i <= s_axi_wstrb;\n          acc_w_i[1] <= wstrb_i[0];\n        wuser_i <= s_axi_wuser;\n          acc_w_i[2] <= wuser_i[0];\n      end else begin\n        wdata_i <= wdata_i>>1;\n        wstrb_i <= wstrb_i>>1;\n        wuser_i <= wuser_i>>1;\n        acc_w_i <= acc_w_i>>1;\n      end\n    end\n  \nendmodule\n\n\n\n//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_22_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \n(* autopipeline_module=\"yes\" *)\nmodule axi_register_slice_v2_1_22_auto_slr #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n    wire                    handshake_pipe;\n    wire                    ready_pipe;\n    wire [C_DATA_WIDTH-1:0] payload_pipe;\n    (* keep=\"true\" *)                                                                reg  s_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  s_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  s_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  s_areset_resp2 = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  m_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  m_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_areset_resp2 = 1'b0;\n    \n  // Global Reset pipelining\n  \n    always @(posedge ACLK) begin\n      s_aclear       <= ~ARESETN;\n      s_areset_fwd   <= ~ARESETN; \n      s_areset_resp  <= s_areset_fwd;  // Auto-pipeline\n      s_areset_resp2 <= s_areset_resp; // Auto-pipeline\n    end\n    \n    always @(posedge ACLK) begin\n      m_aclear       <= ~ARESETN;\n      m_areset_fwd   <= ~ARESETN; \n      m_areset_resp  <= m_areset_fwd;  // Auto-pipeline\n      m_areset_resp2 <= m_areset_resp; // Auto-pipeline\n    end\n    \n  // Source-side submodule\n    \n    axi_register_slice_v2_1_22_auto_src #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_src\n      (\n       .ACLK             (ACLK),    \n       .s_aclear         (s_aclear),\n       .s_areset_resp2   (s_areset_resp2),  \n       .S_VALID          (S_VALID),  \n       .S_READY          (S_READY), \n       .S_PAYLOAD_DATA   (S_PAYLOAD_DATA),\n       .ready_pipe        (ready_pipe), \n       .handshake_pipe    (handshake_pipe),\n       .payload_pipe      (payload_pipe)  \n      );\n    \n  // Destination-side submodule\n    \n    axi_register_slice_v2_1_22_auto_dest #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_dest\n      (\n       .ACLK           (ACLK),    \n       .m_aclear       (m_aclear),\n       .m_areset_resp2 (m_areset_resp2),  \n       .M_READY        (M_READY), \n       .M_VALID        (M_VALID),  \n       .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n       .handshake_pipe  (handshake_pipe),\n       .ready_pipe      (ready_pipe),  \n       .payload_pipe    (payload_pipe)  \n      );\n    \nendmodule  // auto_slr\n\nmodule axi_register_slice_v2_1_22_auto_src #\n  (\n   parameter integer C_DATA_WIDTH = 32\n  )\n  (\n   input  wire ACLK,\n   input  wire s_aclear,\n   input  wire s_areset_resp2,\n   input  wire S_VALID,\n   input  wire ready_pipe,\n   output wire S_READY,\n   output wire handshake_pipe,\n   output wire  [C_DATA_WIDTH-1:0] payload_pipe,\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA\n   );\n    \n   (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  [C_DATA_WIDTH-1:0] payload_pipe_r;\n    (* keep=\"true\" *) reg [2:0] s_aresetn_resp4 = 3'b000;\n    wire s_aresetn_resp3;\n    wire s_aresetn_d;\n    wire s_aresetn_q;\n    wire s_handshake_d;\n    wire s_ready_i;\n    \n    assign S_READY = s_ready_i & s_aresetn_q;\n    assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;\n    assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;\n    assign payload_pipe = payload_pipe_r;\n    \n    always @(posedge ACLK or posedge s_aclear) begin\n      if (s_aclear) begin\n        s_aresetn_resp4 <= 3'b000;\n      end else begin\n        s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      payload_pipe_r <= S_PAYLOAD_DATA;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) s_aresetn_resp3_inst (\n        .Q   (s_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~s_areset_resp2)\n     );\n    \n    // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (s_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_aresetn_d)\n     );\n    \n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (handshake_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_handshake_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (s_ready_i),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (ready_pipe)\n     );\n    \nendmodule  // auto_src\n\nmodule axi_register_slice_v2_1_22_auto_dest #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   input  wire ACLK,\n   input  wire m_aclear,\n   input  wire m_areset_resp2,\n   input  wire M_READY,\n   input  wire handshake_pipe,\n   output wire ready_pipe,\n   output wire M_VALID,\n   input  wire [C_DATA_WIDTH-1:0] payload_pipe,\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n   );\n    \n    (* keep=\"true\" *) reg [2:0] m_aresetn_resp4 = 3'b000;\n    wire m_aresetn_resp3;\n    wire m_aresetn_d;\n    wire m_aresetn_q;\n    wire m_valid_i;\n    wire pop;\n    wire m_ready_d;\n    wire m_handshake_q;\n    reg  [C_DATA_WIDTH-1:0] m_payload_q;\n    \n    assign M_VALID = m_valid_i;\n    assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;\n    assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;\n    assign pop     = M_READY & m_valid_i;\n    \n    always @(posedge ACLK or posedge m_aclear) begin\n      if (m_aclear) begin\n        m_aresetn_resp4 <= 3'b000;\n      end else begin\n        m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      m_payload_q <= payload_pipe;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) m_aresetn_resp3_inst (\n        .Q   (m_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~m_areset_resp2)\n     );\n    \n    // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (m_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_aresetn_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (m_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (handshake_pipe)\n     );\n    \n    (* autopipeline_group=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (ready_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_ready_d)\n     );\n    \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  (5)  \n      )\n      srl_fifo\n      (\n       .aclk    (ACLK),    \n       .areset  (~m_aresetn_q),\n       .aclear  (m_aclear),  \n       .s_mesg  (m_payload_q),  \n       .s_valid (m_handshake_q), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      );\n    \nendmodule  // auto_dest\n\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      reg s_valid_d;\n      reg s_ready_d = 1'b0;\n      reg s_ready_reg = 1'b0;\n      reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_22_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_RESP_MIDDLE2_LATENCY = C_PIPELINES_SLAVE + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_22_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      .ACLK           (ACLK),\n      .ARESETN         (ARESETN),\n      .S_PAYLOAD_DATA (S_PAYLOAD_DATA),\n      .S_VALID        (S_VALID),\n      .S_READY        (S_READY),\n      .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n      .M_VALID        (M_VALID),\n      .M_READY        (M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_reset;\n    wire src_ready;\n    wire dummy_reset;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  ( C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( dummy_reset   ) ,\n        .laguna_s_reset_in  ( src_reset   ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset   ) ,\n        .laguna_m_reset_in  ( src_reset  ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset2   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n      \n  end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] mid_payload;\n    wire mid_handshake;\n    wire mid_ready;\n    wire mid_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n    wire dummy_reset3;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( mid_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( mid_reset    ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset3   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset3   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out (  dummy_reset2  ) ,\n        .laguna_m_reset_in  ( mid_reset   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE2_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( mid_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2   ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset3   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset3    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n   \n  generate\n\n  (* keep=\"true\" *) reg s_reset_dd = 1'b0;\n  (* keep=\"true\" *) reg m_reset_dd = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n  \n  assign laguna_s_reset_out = laguna_s_reset_out_i;\n  assign laguna_m_reset_out = laguna_m_reset_out_i;\n  \n  always @(posedge ACLK) begin\n    laguna_s_reset_in_d <= laguna_s_reset_in;\n    laguna_m_reset_in_d <= laguna_m_reset_in;\n    s_reset_dd <= laguna_s_reset_in_d;\n    m_reset_dd <= laguna_m_reset_in_d;\n    laguna_s_reset_out_i <= C_PIPELINES==0 ? laguna_m_reset_in_d : m_reset_dd;\n    laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;\n  end\n  \n  wire ACLEAR;\n  assign ACLEAR = ~ARESETN;\n  \n  if (1) begin : common\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire laguna_s_handshake_q;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, laguna_m_ready_d}; \n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else if (p==C_PIPELINES+1) begin\n          laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n\n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = handshake_i[C_PIPELINES];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_m_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* keep=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_22_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_m_reset_out = laguna_m_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_m_reset_in_d <= laguna_m_reset_in;\n      aresetn_d <= C_CHANNEL==P_FORWARD ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? areset_dly[15]  : laguna_m_reset_in_d;\n      laguna_m_reset_out_i <= areset_d;  // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n  \n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* keep=\"true\" *)  reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      ready_d <= {ready_d, laguna_m_ready_d}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid_q;\n      assign payload_valid_d = (p==0) ? (S_VALID & s_ready_i) : handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==C_PIPELINES) begin\n          laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else if (p==0) begin\n          payload_data <= S_PAYLOAD_DATA;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n      \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_s_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* keep=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_s_reset_out = laguna_s_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_s_reset_in_d <= laguna_s_reset_in;\n      aresetn_d <= C_CHANNEL==P_RESPONSE ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? laguna_s_reset_in_d : areset_dly[15];\n      laguna_s_reset_out_i <= areset_d;  // For forward channels, reflect laguna_s_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n\n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    wire laguna_s_handshake_q;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      laguna_s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n        \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n        \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)  \n      )\n      srl_fifo_0\n      (\n       .aclk    (ACLK),    \n       .areset  (areset_d),  \n       .aclear  (ACLEAR),\n       .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n       .s_valid (push), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      ); \n  \n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  reg areset_d = 1'b0;\n  reg [3:0] areset_dly = 4'b0;\n  always @(posedge ACLK) begin\n    areset_dly <= {4{~ARESETN}} | (areset_dly<<1);\n    areset_d <= areset_dly[3];\n  end\n  \n  if (1) begin : common\n    reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID & s_ready_i;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* keep=\"true\" *)  reg payload_valid = 1'b0;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          payload_data <= S_PAYLOAD_DATA;\n          payload_valid <= S_VALID & s_ready_i & ~areset_d;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n          payload_valid <= handshake_i[((p>0)?(p-1):0)];\n        end\n      end\n    end\n    \n    if (C_PIPELINES==0) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),\n         .aclear  (1'b0),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire                        aclear,  // Async clear\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    wire [1:0] state;  // State vector register\n    reg  [1:0] next;           // Next state value\n    wire [1:0] next_qual;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    reg  m_valid_d;\n    wire m_valid_q;\n    \n    assign m_valid = m_valid_q;\n    assign next_qual = areset ? K_EMPTY : next;\n    assign m_mesg  = mesg_reg;\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_mvalid_inst (\n        .Q   (m_valid_q),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (m_valid_d)\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state0_inst (\n        .Q   (state[0]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[0])\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state1_inst (\n        .Q   (state[1]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[1])\n     );\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      m_valid_d = m_valid_q & ~areset;\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid & ~areset) begin\n            next = K_HAS1;\n            m_valid_d = 1'b0;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              m_valid_d = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n              m_valid_d = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          m_valid_d = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      (* keep_hierarchy = \"yes\" *) axi_register_slice_v2_1_22_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule  // axic_reg_srl_fifo\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   //   16 -> Auto-pipelining\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_RESERVE_MODE = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n  \n  if (C_RESERVE_MODE==1) begin : gen_reserve_si\n  \n    axi_register_slice_v2_1_22_test_slave #(\n      .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n      .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n      .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n      .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n      .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n      .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n      .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n      .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n      .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .s_axi_awaddr(s_axi_awaddr),\n      .s_axi_awprot(s_axi_awprot),\n      .s_axi_awvalid(s_axi_awvalid),\n      .s_axi_awready(s_axi_awready),\n      .s_axi_awsize(s_axi_awsize),\n      .s_axi_awburst(s_axi_awburst),\n      .s_axi_awcache(s_axi_awcache),\n      .s_axi_awlen(s_axi_awlen),\n      .s_axi_awlock(s_axi_awlock),\n      .s_axi_awqos(s_axi_awqos),\n      .s_axi_awregion(s_axi_awregion),\n      .s_axi_awid(s_axi_awid),\n      .s_axi_awuser(s_axi_awuser),\n      .s_axi_wdata(s_axi_wdata),\n      .s_axi_wstrb(s_axi_wstrb),\n      .s_axi_wvalid(s_axi_wvalid),\n      .s_axi_wready(s_axi_wready),\n      .s_axi_wlast(s_axi_wlast),\n      .s_axi_wid(s_axi_wid),\n      .s_axi_wuser(s_axi_wuser),\n      .s_axi_bresp(s_axi_bresp),\n      .s_axi_bvalid(s_axi_bvalid),\n      .s_axi_bready(s_axi_bready),\n      .s_axi_buser(s_axi_buser),\n      .s_axi_bid(s_axi_bid),\n      .s_axi_araddr(s_axi_araddr),\n      .s_axi_arprot(s_axi_arprot),\n      .s_axi_arvalid(s_axi_arvalid),\n      .s_axi_arready(s_axi_arready),\n      .s_axi_arsize(s_axi_arsize),\n      .s_axi_arburst(s_axi_arburst),\n      .s_axi_arcache(s_axi_arcache),\n      .s_axi_arlock(s_axi_arlock),\n      .s_axi_arlen(s_axi_arlen),\n      .s_axi_arqos(s_axi_arqos),\n      .s_axi_arregion(s_axi_arregion),\n      .s_axi_aruser(s_axi_aruser),\n      .s_axi_arid(s_axi_arid),\n      .s_axi_rdata(s_axi_rdata),\n      .s_axi_rresp(s_axi_rresp),\n      .s_axi_rvalid(s_axi_rvalid),\n      .s_axi_rready(s_axi_rready),\n      .s_axi_rlast(s_axi_rlast),\n      .s_axi_ruser(s_axi_ruser),\n      .s_axi_rid(s_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign m_axi_awid     = 0;\n     assign m_axi_awaddr   = 0;\n     assign m_axi_awlen    = 0;\n     assign m_axi_awsize   = 0;\n     assign m_axi_awburst  = 0;\n     assign m_axi_awlock   = 0;\n     assign m_axi_awcache  = 0;\n     assign m_axi_awprot   = 0;\n     assign m_axi_awregion = 0;\n     assign m_axi_awqos    = 0;\n     assign m_axi_awuser   = 0;\n     assign m_axi_awvalid  = 0;\n     assign m_axi_wid      = 0;\n     assign m_axi_wdata    = 0;\n     assign m_axi_wstrb    = 0;\n     assign m_axi_wlast    = 0;\n     assign m_axi_wuser    = 0;\n     assign m_axi_wvalid   = 0;\n     assign m_axi_bready   = 0;\n     assign m_axi_arid     = 0;\n     assign m_axi_araddr   = 0;\n     assign m_axi_arlen    = 0;\n     assign m_axi_arsize   = 0;\n     assign m_axi_arburst  = 0;\n     assign m_axi_arlock   = 0;\n     assign m_axi_arcache  = 0;\n     assign m_axi_arprot   = 0;\n     assign m_axi_arregion = 0;\n     assign m_axi_arqos    = 0;\n     assign m_axi_aruser   = 0;\n     assign m_axi_arvalid  = 0;\n     assign m_axi_rready   = 0;\n      \n  end else if (C_RESERVE_MODE==2) begin : gen_reserve_mi\n    \n    axi_register_slice_v2_1_22_test_master #(\n    .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n    .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .m_axi_awaddr(m_axi_awaddr),\n      .m_axi_awprot(m_axi_awprot),\n      .m_axi_awvalid(m_axi_awvalid),\n      .m_axi_awready(m_axi_awready),\n      .m_axi_awsize(m_axi_awsize),\n      .m_axi_awburst(m_axi_awburst),\n      .m_axi_awcache(m_axi_awcache),\n      .m_axi_awlen(m_axi_awlen),\n      .m_axi_awlock(m_axi_awlock),\n      .m_axi_awqos(m_axi_awqos),\n      .m_axi_awid(m_axi_awid),\n      .m_axi_awuser(m_axi_awuser),\n      .m_axi_wid(m_axi_wid),\n      .m_axi_wdata(m_axi_wdata),\n      .m_axi_wstrb(m_axi_wstrb),\n      .m_axi_wvalid(m_axi_wvalid),\n      .m_axi_wready(m_axi_wready),\n      .m_axi_wlast(m_axi_wlast),\n      .m_axi_wuser(m_axi_wuser),\n      .m_axi_bresp(m_axi_bresp),\n      .m_axi_bvalid(m_axi_bvalid),\n      .m_axi_bready(m_axi_bready),\n      .m_axi_buser(m_axi_buser),\n      .m_axi_bid(m_axi_bid),\n      .m_axi_araddr(m_axi_araddr),\n      .m_axi_arprot(m_axi_arprot),\n      .m_axi_arvalid(m_axi_arvalid),\n      .m_axi_arready(m_axi_arready),\n      .m_axi_arsize(m_axi_arsize),\n      .m_axi_arburst(m_axi_arburst),\n      .m_axi_arcache(m_axi_arcache),\n      .m_axi_arlen(m_axi_arlen),\n      .m_axi_arlock(m_axi_arlock),\n      .m_axi_arqos(m_axi_arqos),\n      .m_axi_arid(m_axi_arid),\n      .m_axi_aruser(m_axi_aruser),\n      .m_axi_rdata(m_axi_rdata),\n      .m_axi_rresp(m_axi_rresp),\n      .m_axi_rvalid(m_axi_rvalid),\n      .m_axi_rready(m_axi_rready),\n      .m_axi_rlast(m_axi_rlast),\n      .m_axi_ruser(m_axi_ruser),\n      .m_axi_rid(m_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign s_axi_awready = 0;\n     assign s_axi_wready  = 0;\n     assign s_axi_bid     = 0;\n     assign s_axi_bresp   = 0;\n     assign s_axi_buser   = 0;\n     assign s_axi_bvalid  = 0;\n     assign s_axi_arready = 0;\n     assign s_axi_rid     = 0;\n     assign s_axi_rdata   = 0;\n     assign s_axi_rresp   = 0;\n     assign s_axi_rlast   = 0;\n     assign s_axi_ruser   = 0;\n     assign s_axi_rvalid  = 0;\n\n  end else begin : gen_reg_slice  // Any normal reg-slice mode\n\n    axi_infrastructure_v1_1_0_axi2vector #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    axi2vector_0 ( \n      .s_axi_awid      ( s_axi_awid      ) ,\n      .s_axi_awaddr    ( s_axi_awaddr    ) ,\n      .s_axi_awlen     ( s_axi_awlen     ) ,\n      .s_axi_awsize    ( s_axi_awsize    ) ,\n      .s_axi_awburst   ( s_axi_awburst   ) ,\n      .s_axi_awlock    ( s_axi_awlock    ) ,\n      .s_axi_awcache   ( s_axi_awcache   ) ,\n      .s_axi_awprot    ( s_axi_awprot    ) ,\n      .s_axi_awqos     ( s_axi_awqos     ) ,\n      .s_axi_awuser    ( s_axi_awuser    ) ,\n      .s_axi_awregion  ( s_axi_awregion  ) ,\n      .s_axi_wid       ( s_axi_wid       ) ,\n      .s_axi_wdata     ( s_axi_wdata     ) ,\n      .s_axi_wstrb     ( s_axi_wstrb     ) ,\n      .s_axi_wlast     ( s_axi_wlast     ) ,\n      .s_axi_wuser     ( s_axi_wuser     ) ,\n      .s_axi_bid       ( s_axi_bid       ) ,\n      .s_axi_bresp     ( s_axi_bresp     ) ,\n      .s_axi_buser     ( s_axi_buser     ) ,\n      .s_axi_arid      ( s_axi_arid      ) ,\n      .s_axi_araddr    ( s_axi_araddr    ) ,\n      .s_axi_arlen     ( s_axi_arlen     ) ,\n      .s_axi_arsize    ( s_axi_arsize    ) ,\n      .s_axi_arburst   ( s_axi_arburst   ) ,\n      .s_axi_arlock    ( s_axi_arlock    ) ,\n      .s_axi_arcache   ( s_axi_arcache   ) ,\n      .s_axi_arprot    ( s_axi_arprot    ) ,\n      .s_axi_arqos     ( s_axi_arqos     ) ,\n      .s_axi_aruser    ( s_axi_aruser    ) ,\n      .s_axi_arregion  ( s_axi_arregion  ) ,\n      .s_axi_rid       ( s_axi_rid       ) ,\n      .s_axi_rdata     ( s_axi_rdata     ) ,\n      .s_axi_rresp     ( s_axi_rresp     ) ,\n      .s_axi_rlast     ( s_axi_rlast     ) ,\n      .s_axi_ruser     ( s_axi_ruser     ) ,\n      .s_awpayload ( s_awpayload ) ,\n      .s_wpayload  ( s_wpayload  ) ,\n      .s_bpayload  ( s_bpayload  ) ,\n      .s_arpayload ( s_arpayload ) ,\n      .s_rpayload  ( s_rpayload  ) \n    );\n    \n    axi_infrastructure_v1_1_0_vector2axi #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    vector2axi_0 ( \n      .m_awpayload    ( m_awpayload    ) ,\n      .m_wpayload     ( m_wpayload     ) ,\n      .m_bpayload     ( m_bpayload     ) ,\n      .m_arpayload    ( m_arpayload    ) ,\n      .m_rpayload     ( m_rpayload     ) ,\n      .m_axi_awid     ( m_axi_awid     ) ,\n      .m_axi_awaddr   ( m_axi_awaddr   ) ,\n      .m_axi_awlen    ( m_axi_awlen    ) ,\n      .m_axi_awsize   ( m_axi_awsize   ) ,\n      .m_axi_awburst  ( m_axi_awburst  ) ,\n      .m_axi_awlock   ( m_axi_awlock   ) ,\n      .m_axi_awcache  ( m_axi_awcache  ) ,\n      .m_axi_awprot   ( m_axi_awprot   ) ,\n      .m_axi_awqos    ( m_axi_awqos    ) ,\n      .m_axi_awuser   ( m_axi_awuser   ) ,\n      .m_axi_awregion ( m_axi_awregion ) ,\n      .m_axi_wid      ( m_axi_wid      ) ,\n      .m_axi_wdata    ( m_axi_wdata    ) ,\n      .m_axi_wstrb    ( m_axi_wstrb    ) ,\n      .m_axi_wlast    ( m_axi_wlast    ) ,\n      .m_axi_wuser    ( m_axi_wuser    ) ,\n      .m_axi_bid      ( m_axi_bid      ) ,\n      .m_axi_bresp    ( m_axi_bresp    ) ,\n      .m_axi_buser    ( m_axi_buser    ) ,\n      .m_axi_arid     ( m_axi_arid     ) ,\n      .m_axi_araddr   ( m_axi_araddr   ) ,\n      .m_axi_arlen    ( m_axi_arlen    ) ,\n      .m_axi_arsize   ( m_axi_arsize   ) ,\n      .m_axi_arburst  ( m_axi_arburst  ) ,\n      .m_axi_arlock   ( m_axi_arlock   ) ,\n      .m_axi_arcache  ( m_axi_arcache  ) ,\n      .m_axi_arprot   ( m_axi_arprot   ) ,\n      .m_axi_arqos    ( m_axi_arqos    ) ,\n      .m_axi_aruser   ( m_axi_aruser   ) ,\n      .m_axi_arregion ( m_axi_arregion ) ,\n      .m_axi_rid      ( m_axi_rid      ) ,\n      .m_axi_rdata    ( m_axi_rdata    ) ,\n      .m_axi_rresp    ( m_axi_rresp    ) ,\n      .m_axi_rlast    ( m_axi_rlast    ) ,\n      .m_axi_ruser    ( m_axi_ruser    ) \n    );\n    \n  end  // Reserve SI/MI branch\n\n  if ((C_REG_CONFIG_AW <= 9) && (C_RESERVE_MODE==0)) begin : aw\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 15) && (C_RESERVE_MODE==0)) begin : aw15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 16) && (C_RESERVE_MODE==0)) begin : aw16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) \n    )\n    aw_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if ((C_REG_CONFIG_W <= 9) && (C_RESERVE_MODE==0)) begin : w\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 15) && (C_RESERVE_MODE==0)) begin : w15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 16) && (C_RESERVE_MODE==0)) begin : w16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) \n    )\n    w_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if ((C_REG_CONFIG_B <= 9) && (C_RESERVE_MODE==0)) begin : b\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if ((C_REG_CONFIG_B == 15) && (C_RESERVE_MODE==0)) begin : b15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if ((C_REG_CONFIG_B == 16) && (C_RESERVE_MODE==0)) begin : b16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) \n    )\n    b_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if ((C_REG_CONFIG_AR <= 9) && (C_RESERVE_MODE==0)) begin : ar\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 15) && (C_RESERVE_MODE==0)) begin : ar15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 16) && (C_RESERVE_MODE==0)) begin : ar16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) \n    )\n    ar_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if ((C_REG_CONFIG_R <= 9) && (C_RESERVE_MODE==0)) begin : r\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 15) && (C_RESERVE_MODE==0)) begin : r15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 16) && (C_RESERVE_MODE==0)) begin : r16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) \n    )\n    r_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 4844}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule src_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(1),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(9),\n    .C_REG_CONFIG_AR(1),\n    .C_REG_CONFIG_R(9),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n(* X_CORE_INFO = \"axi_register_slice_v2_1_22_axi_register_slice,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"src_register_slice,axi_register_slice_v2_1_22_axi_register_slice,{}\" *)\n(* CORE_GENERATION_INFO = \"src_register_slice,axi_register_slice_v2_1_22_axi_register_slice,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=virtexuplus,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=16,C_AXI_ADDR_WIDTH=64,C_AXI_DATA_WIDTH=512,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=1,C_REG_CONFIG_W=1,\\\nC_REG_CONFIG_B=9,C_REG_CONFIG_AR=1,C_REG_CONFIG_R=9,C_RESERVE_MODE=0,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER_AW=0,C_PIPELINES_MASTER_W=0,C_PIPELINES_MASTER_B=0,C_PIPELINES_MASTER_AR=0,C_PIPELINES_MASTER_R=0,C_PIPELINES_SLAVE_AW=0,C_PIPELINES_SLAVE_W=0,C_PIPELINES_SLAVE_B=0,C_PIPELINES_SLAVE_AR=0,C_PIPELINES_SLAVE_R=0,C_PIPELINES_MIDDLE_AW=0,C_PIPELINES_MIDDLE_W=0,C_PIPELINES_MIDDLE_B=0,C_PIPELINES_MIDDLE_AR=0,C_PIPELINES_MIDDLE_R=0}\" *)\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule src_register_slice (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [15 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [15 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [15 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [15 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [15 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [15 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [15 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [15 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER\\\n_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(16),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(1),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(9),\n    .C_REG_CONFIG_AR(1),\n    .C_REG_CONFIG_R(9),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(16'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 438}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nXvoWuyjysN5V55U4xsjyWg2bXI++8I1KAZgJ0eiQkY3L8ns1PfNti9fujmr8wvFQA6ycwh4K6mSp\nINQjc8TyLQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nbD05I2IKef08FLVG4C2ftkJOY+/UsvagxY6ta+A0N1USwLQivKTmRt7LJlQ+5UJqrfPvhHMyYrLN\nrjoJbClg85XfNTYCnalRVvg3mmCcjtJkCLf6S5E9Q6UF92b6bwgtMTsr0BndJhdItlJtr0dYZtoP\nAEskMBthh6RdNMkZ3CA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nvLo4Yp/zX6HvZ92VMA2Xr4EIhMWPNGq2EvSBkjiZd5sCSFAX+37MKx4gdbrsGvhUMl1njqvSaoP7\nKrAa29/cm3QWjPgpaCsR/MhnaG5+7aUvxA5iCqVHXdriMlgx9kzxkB9SD+mOC8XR5LtYA0bPhbZ9\njQzWpWxdaOGYFF25DU0O9M7LMc7SLfKunYH/cQ91D37m0LjgZh1/uZv8chFzvCBbkHqUU0qi17/k\nZTWIIzqb1oycbuhZZrWLl95xQ/aaTxZ30sONWd/axZtO3Cd57huCbCxLuOH51qq6erD9AVszmxL8\noEoM+KW88P1S3LJ/EcIQN4LU0/nyN/f7xEmy2w==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nj99ihkoCqIO9DhRZEJdEqlRF2P+IwS2wuYmoh3hWFCDXbmGTwTqc+3EMjxY8Z4uDixuazjlTMiEH\nCk4MdTkVZ55pPhFb4druHTap3Twn20B3SWvOy2nf84OpTkdBnbK4qagABgZXs9/mAtQxbF++/F6Y\n+OOE3yUNTWvHiVGvpTJavfADkB2CL5wEIlBSnYRwtLp71JokDsMvjq2l3o3hxAjvtdg9ej7NKx4I\nkAZfrpZH7Ebv2hfXrTVI2kDTAl5Etr+4oSqxIhABJut2WaeWJrsSbL+dz9s2ZmYDMb1BCQdRexck\nbMMvUaS+P7sSGuR9BTVynHOY5GdQelHO1aazQw==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nHuzbd0U90PuPKn40554Cnki98HuQSq7dg6ZyXufEWFHsji6rteNupAY3HQsuLpXjFVxsNlS4bcHj\nAAOnDcL0hCCVbSkU011mqhhlkFmWqeBBECGfP+T7/+l9KBu+9ynszhlhaVhmZMffsEuohDl5x084\nFnzFCdxrFyvqrOyWDac=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\neoQKmSsNWNEOJcUApe0UhUNGRDkxOLedPbjyDILgUJWMG+WVCpL9MC2MXZeZ6/oVwAYRlZTZsF1h\nUsVo6BO7IAuHuJAHeIQgEs2oIMj/I2qZxm9wUsOzWoK5/Jz4SS4sTE3TgOJXaX1GNAJlbUrCBtnM\nqIiavU164vZjX5BFoPGuHp4kICN8A4Wr9y2w2Lh0/IdiHjr/Ruk5PpVNyl7tW9EaSFY1AL4aoQpd\nRFDdUFRk4tMBtmFxi/B+pLVFE0hAUZnlVCsSaf4B0lN/m4CME7lgy7oXElp7ov4fMnD9VI8HLGMX\nWBSQjD8F6BB0Wblgm9lJNc0h0VqxxD4DbRleKA==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nyrn0K+G4SU1wuMdE7DJlKWErX/N5nCqD3+dP+4ONmo8yuM983VHfjLhCoeQMbM26e49U4PPdXcDR\ny0rRemqJACoi5H5NvzXohhKZI9q+WKME4TkhFzfKvIwyta1m/uNSe/A0+52Dzbg5uAxYihw0IdZR\nZMywfa3deZ8IUMz3kWSlMs1P4wESz2pKpdYGs0FpvovucuNn4OhZKH7RGX8z8Zy4E9juZRgnSQnX\nmvRtisgVB9uL2J0vl9XjW/1990VYZi0nrZJ8gQL38HLTz62vDuMuYjiFbbnDCujJNKOCHh/xJTdt\n73nsz+dY3We4tQdnxuESibzLQLGF1l8+d9FPDA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nJPIGH1v6BG8bvo+3pHrWlum+XEDtFDlKP+4Toq88+g/eeinS/p8A0zMVVYj4wfjGDhx3kGvJ9XAx\ngxYpezvlgnz+IEGWQzepCMSp4iHz9TEdGkc5LTQj50VJj4+HGz2Qhrw96Hw0c+5RDrv238ILy3p7\nuzIPIzxKEl8D7gK6b8ZPrzx95KMPuGZyju4JUHBWdjDx0hhhIl+L3Ju/bVyWaWd7w1xI0mreJtAN\noOdcObOESJpTuj0KqFtfA3UY7v9n9Lj/I/vMaPX7LnSIZuS+tHyiD8D+t+Kf6XiIl3sYDL9erP7t\nSpHvPfG9bOfGRxM7dmsvKj+XqHeXg23wyS1Nfg==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nrxmK0sxFw5opGoAsi+RHBRwE0wYNls8LL+oURMgLNuoRDOPNH7up4F86jASnrdlvXLShGHMZnaJ6\ny1orZ0uAZ6xxM2PeKAxvxBI02HOu0aXd/SMNxr16dADlCYK6R1DVdq3DC+T8bQTLWyyHr9r4m4En\nW5DcJ2hEs5b31PUg/DoCNTpHm2swT7sLG9qRkSfTddaSyGTADcvRXYjnHKHin6TQlOCZufWMm54P\nPJeCQmj1MjyycQGpsvFNX7VMxW49ashO7EGmRdy7lMGRoHDqLWBxcIlwAS4L28iuln/NdC/QV538\nQei7EbcqeUmfs07XP8FKxdA3hi3Aq2Upg9DkOw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64736)\n`pragma protect data_block\npJdOORWQloxSGvgvy0l4tBp1HqnYdonsYgNOe99SLH3qi9BP+2tNlaoelqmLJLSHNsBn3TJxXlZa\nnIZxc0/l2jA1h9Jz15QEEgUR0MqZaESeIPQdEbADnul6xUXY0J6g//n8Vnzph99nb1v9j4yp0I8W\nmF2Bvdz/qHJcUcV5zedPk5PkPVS8cmwYFQWer3rOMl6Or1E/YoHi9T9wfbgxxTs6yzqYqVGUBlz5\nAlhSoRF+xXB1Z4h2Ny4v4u05pGtbpnnDj+JhauZ7AfT+uRL3JZ7hNdSiI3coyNU077RtI/1VAmYO\npJoj/3tO2z4y9phvRShE/Otch4qxfx53IywqoRQmUF57yV4NjbkGPW8j7U6iQ8Ls1911ZAOgZIga\nmynl1jCs8ajbsNdraT0wfsPf1kWJOCuUGyItYv2eEwfh7iEYRrpT0V6YT5gENAgDuriQCZuFtnJE\ndhvImjwTXy3d76buWun43bM5pyUNSUzm90uucXHtbfsv8HZTM/chDluZJ4cMeW8D9Pwjtvo6lXLx\nYJM6v2cUpOTIMOcKDxrRTFomRQ1DwRsa4wQGal4q2dhrokLR6YNhu1ED6+AbEAN+FWui25yRPN2c\nRifAbYj3+oa+z6kUON22gegvkiRIe3iVn5MeyImok+P+5dmykiOW6L7J+GDFd4UZtYwJkwUH4ijt\ny9tlvkg7bhgKKY/VRht7EZFg6U4GjUBwLTEWIsD/6R8LgyENKTNO1FVyOJge9+hJYOxJpk93nMac\n0dR2cl0TLESIEfZQ8wSlqKcnzibNa/Mwa+gyj8uNmBtlGMv9GLnh914fnVrJPaJYjkLNLesy5uKF\nWOOHFhlsuqMHkybog57X/W2y+bzzdtaWoQ8/DU/QWGyTt3Vhlmu4YBKvv/DBB51RUj7naprx+CNR\nK7/l3uoheqcD/zy4ipVqZ/mSOTxjqNwJ88tpKUTD7UHuLf8rEeiu80iR1raYJGMHzUS7FcK/APPf\nbBCJIKpjoq1C63MJYurbOeqWcRL3DDPi/z3C66E9WG/nFKs7vMkhbVhClFUAjy+DwMCS7VjbvUvn\nCbr4m+kTXY7ipbBxU7YIDWHssBAAjeM1Rdxx9VvDqABN+rFZAA7C08PNPUeOiVYCFO3gmbAqYK8f\nEPeBaPUk6eskVX2sXw5/qrh1a5mqGk/sYCFZItuYZ6SMz1BFuaZz+ac8Feq8+d7gH2f1DuK4EG20\nOgLh0liUdRk5TCUZsSZTlhRd1FA4SqglWHYk+GIL1WEcVBskAEiY2YIK1TGXzUQaG00TT5TRBNmv\nsPnVI8z6bWwqXomyqcYSelXrfl2izqtjadlA+3+0O2A1XhL9tmMhT3v0nQIlobxn4nFE376czv08\n2+xLHI/chXlg2WvKMK3NCBbWGw7tnHSdJc47JRdiCkb0tIr9wocUbWPbM7W5G3Ku+bQZQXPM0lNy\nstFAjwukEDL4vbC72EJbEwf+6kzkzLjBrc0JDEzvjqnYQYiwloQ0qi9k/yE3bXcnEHvgw8ig5Y/S\nt9SttzL9mNMXwbouRg1seAZ89RrLrTNZiBk2TlhzdIfvWsbvdBYdIhaMqKRGJFpWxZgPm+JbW+09\nfF1z2nf/18EW+WziUuICezISE4+2HDfqFOEltKV6AdesQWDrloYiby+MezSSORPfWkx+nVGv8JEs\nI01podsuoWFRpVmbt/Dua5qZk9EOHGFBRgvYNnlH47YVREn5j8l2T/0bBlGUrv4r0tmSTvb5Rk62\nTtYvXt/3/jJe7TX05O4Uz8CDBe02LhhwyNkyyNYPm6hcqislaGMW5IrlUBR19xoKivY5xsi9WHEp\nOscK7GlXBFf+1ZdqPUIFBzo8CoanS+vY6N5dX/zhH9ka7wSGlru7qjqAyYG3VOzYi+lIUT1D0l0A\nhIuLJhQlgGIPioPMX5r9G+nJX9J1xhmQmslUobJCrtsIfoshA1m3sO8FVq/uKShEPK85uU48DmE1\nBM73G3APR/Pn3q4udJagFjB+ngJWARXqQX1U/fZdrs1d4U8E/KLlkVQywLtM4ImADW15ZRE2zwbt\n93vD21KzRF0gTEp32+Y94DZJmilvEITUz6i6Uf3GIhk/8VlW2sgoZBxyIXdlfZU0hAeWoF6z0y8i\nsz3YJBSL59bOXPeovsUY+1K4JWkThiLh9WlHMd3YfANHBPnf+imIQZm0bk8SniIn386MI5OOzHz4\nE4NRinoFBZ2QveSs8W7mDkgRcm6PoFPVY3QRUGVKM/cdavafi55CMHzsrvtIU+GTn9VIn3xNt55T\nvun82PwGiZ2FiwhlNlG8Wy4O+LFNA76IijNkkamPOoINY3NpvBlYJ4sMSw1dZ/S+Qd509gN+YqK/\njuugLi10dq5ezC717GDkCW4fL6XMF1BLctfTjFHbDnQePKJIiB57aUuvbzah60QCKQnwYsO2mNs3\nlX8Tl9YL68F88dwoxH0JclrQ/K+4uYuofKZNpcUqyesWLZ7Ajkjo1V/LWCNdqLb7jaE2Z0v+PGsJ\nbQ2zY2rbw1xVbkOFkWnJb00IZlS5AfKLW2JwtTjSc9R5cytj7Kj8rVyPRdWixjwHVXwb9oIhCtsZ\nr9zdlcsnNvnrEk8HWDJmg9t+Ss3qdeobuZBvC1qVhW9OeCSeLWFmmlBTM7zlf4bIM7BPobwINrOH\na+x81+t4Xk/8bAWK5b1pfO/q6usi0t9Z1NTJb3ix47MRkhAbStRfFBfBwzDQr/YBXixPzFiRd7RK\nKHM5pI4NGo4x/1eUa3I9iGFb0JwOlvTvmyLF4CY35sdztuKueaGq0YUi4X3SbBVUihPbcPvhcn3q\nULcb1JlytkOdtyHtyrm7/EOiSLmMn3uCPXQDioYj1f6NsIRA8BV+t4V5VK8a2hNJ+Ci6U9tBmG7R\n2AfVDNWXakk0eYIUYcZuIPVd4sH7Be8PANt6YH+bxeZtBfUel13RoATsMc/l+Vz7BvaZ9ZhPoxu0\nMpG5BKJTAuGZ3OqNXDuuvsvuBv8s5hC8JKvLoL76k+rFk8PlyNwEnYoc7nFhCrqDHeOr/8E3maxP\nPv/AiEhEzjU5PQBF457AHnjeQ3eTwpDPSnYJ6nuR0WhnaxbVcRDXmfQc5Pm+RgJOQXySVRlfAtO/\nJmM8oWf9Wd57qYf2P95KvohDPW6vlFW5UOuYJRNedw/Vofmtj6gUXmSUtZzX9x+pGUbZK1L7qaRH\n4Bl+RKLFFF3ULv72pe+uhZoyumhCUE9nTUfh/0bbyfQ0/7E4OjNceJy3IuQXZAelpm4/lyIClM6a\nbcA7XaiUNtUxRgOk+Gm4bXDK/lbpfHAo3ZLrOeIIrJSFdGgfIjMAMcPO2agXDXysM9w0LXX4XzKa\nAk5Ctu+YxqwaE3xbxVfqa3Xiwxzu9RezCh2I21Ysg1ckJugmX+s7525qUeaUizKlxcu5ef5xX40W\nh5pW3QA7UPCugDISw+aX406IO2drov2E5eUNDLRRG/nY7aG606JFGCFgUNVLl22BloATVP6ZeMDr\nmifoHBORyaJvgAndCrygYyJGcy9labne+Cqn0A1qtn323sFNB43FEMX42WIgtgc4oPab1AYsEQum\ns46nWTCUaZAyRO+53Dzben+MOJEy1iKP7o1PMZDKjaQ4Atrpot1Ix9OivbbWL8nNOjFG3rRgc8Tf\nLOVtiwqq/r+IiSB/HQOV/ZHmkDTL9dtw3UFvBE6wRo6XaWDbKDi/T7PaYAC3GGNaQZw3CTXVFb6P\nSvTMYdICAhD7YCZDr6aVLiD1Mgc225aXecHZoluSWOck9HO5ezjlCFCPDSTSj5OnC9v9zUcFbNOa\nri/TT7JdgqdBMKQjvpVrljLeuPPWvSxLMEar6iv8iFwj9w4fIGsSX5D1h0fx53Dosj7c99OjPOKJ\n43ciuUlKmUrl8zGTv1bTsvgQBspvbQjDlKlZcFGKkJ5y+h+FKT7sLG0T7X0OsNyJhlkV8Oh1B7s0\nnzc4JG92kvRVvDmVljLF5q7kSbo4pOg+r9MMh209JANj1imzsRTwNlFhL4KQmOy32YKv975WzfpE\n5gOHTY5gj/9beHVy72SphX1PvZ/GvMrFHu0Q1SdMOxiDJO/8Vv+UogST5Z+pm6YS50RKp917SJLr\npQGNrqMBt2q0TjdKoF10330Oq2OQnGbPQBcF5wAOKor3lUhuKlgi4yfTsE7g0RlphaWiUi0kfQnJ\nxJaR/v3zWkal8YKuqBUOk2zAI58JgLOCGfkeP4lLDigas6lR86dIFm2ehEwWiuUxA0rMWk7MxUFq\nIvlNP2JTSuRX5d7mSS5TdZoich5Z28tzuAxtmfX/HVgsAiDJsXeq2lNJnPI4t7OJcjw+/LTBFn4u\nGkaeVQKsrDg0XjypHHAcx3Htai3F8S3SrSZThLhmNA0UuPAVwrWM/YxdRJdPCFxRV9DIfFLc78ED\nrxRf+2hm2iIX0v9lJubvukxj3RKg3bWedHf9X7fBwzCzmT3xpSVT/orUQHTM7BJi1uX619EAPHfH\nEslFnO9xBhBE/NfxEOIr6puKJWQy0vcdu3KHp/98gdYKgnVg5mCXI4uGSJL+j3Mo34LyWj6jofG1\nRpvUjZOY2WsTY2U7akBl0Uyiv66vuAVFTYtHxbLeKihdYSSxteod2tWquqRvLeBirXL2qi69vijg\n+WXGPNEs1ioW+W6cjl9Kt1V92qIp1LbqTEC9jDdj5VHq36eM3zGGY1FX+VH47w4FoxWcrGaGXkXO\nhGXHGyLwe6ssZ273qYR1N0RhvtgHnAdUHIPdsqqRbjeld0f7uZDVEUjGCA5HvEPmaA4qaz1HEmEX\nMSbcEbGOwM4/lsTSso35cqWlqf9VepPPahniUNw1bY7j79iM/o0F8kJkfL5NumCR5VM7RsWuHT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C99kqfj/UVOTB5eheZdHy7EcqBeNR/+6GsibmPncbobTk24qcaqVJt3wgZyWp0s45X+9wMv8\naq7nxbvk+JD5cuPi785YB4Is1gg85t6bvpA9Qfzb3O9Wk32ecemuYY7hfv+wXPcCciMC61K8t1VJ\nDxofEz9Nxh0L6M2gdZhrIeECMYqp9YunMryNLeqc7YQLvKIjonC1l4sbrYWZ+Vr/tRAksYUVxldM\nWs7rdbIReyHwkW9Q3eVk5tGNZYwsTJZ3LLHqX4k4QW4fN5SrXF7tpu0Nh6B20X5kbA57dL9bI0Mg\ngdCKLlB0s2kqOmSFFGQ2qiGM4gLCtJKTcJvH0QXyq3PoTYgnvqWXAi7962ulHUUvjiqAbTLGRYQR\ngd6pRfridQ9QkVVZ3q8/Wwg9RSEsbZuIJ9bsY3KxRk+Bv/QJmfbw9otM2ufRS79SLoJDUzayREpA\nzPDRjhDoGxRqrI6rV3uPDIkmG/IgiRjrOM3CMltuf+l5zCRv72lm/BooJKYufHaSMAUyCUXJp/Uc\nFu0s9YVH+QVUDZtdn/t+XoUZ1zviEEgoAEoY2VYry4fCJ8DYaSDlP46tShiJjQrOJdERGgL/xQBx\nO6uzJrNrt7Cf6kh0YFyp6QRAfTkuf7kwETESQMUFV2MR8wr0hZHmd/UBOQiPTPb8DscsuSAYh8Zc\nrknuK0zKex9YiHkZeDo7D/PSeuh+WG2d2zJdkM3Td3eMS6WVDFMFl2b5W8/jYjNABrnjK1XwThFh\nYLnSLJi/Op7SthgN17FwYwSwj+AcsR63hVzcnfiVu3ZUXHEZJEyz2HWtWt0RLaZ7MNZccAta93yH\ngOMoJdpfeYUKCCFDGcTyJlFegiSY/R9BWXq/NR5ouF0kpaoEUa+kWjoHoOiSEaQs4XEhSuNjRynD\nrVhVZzcmzBTJAU/E9/o/Hq/uvAStcm39QbP3OeAuNYGNe3sCFCFik9NxiyTW3OEmJSjBcrOnO+Qw\nx7FcS9UJ/wQfURM4P12Z7osL0N6s5Am8NipjMtQyeAtwOcmnJoNC+0+NUiyPWlCuXP/3Z4arSgFa\nZR7xsOv//tsF4wlUna5iH3TC56YNk8nUsFEw6Ge6ZSuhEVsfIeY4wG2IxxjFm7GLEm+Qi2fnWvFp\nirwOxF+K+U92WcMWV9jGmnuJKdDgr9f0rTsSnyJoE6abD5qCwAUSiMOFTLyqf0omOu5SrdwPvxDF\ndftrQ5R+oqkHgkZje/QojcIA5MmPjkCLRdKv8Qe8et8c4lmY6vRi/j86jriaKSwx4Y+Mw85SnPR2\n2j1hg4L1bm3Y95mODLr49QGkDVB7kvY4Qy33Bsp2CTuOWo05KgZSEEXL/7U+fWGzRHjASwfcbgCg\niVFHnASo+4H+F8SItbh9vW9aZB7dvzb/sp41V3sOiSQ/lvFv36hNky3d5TPRgeWxk7ahEnAeBvcU\nN36JNzslIJ0QcFbUJcrGjbreKWGwtRudHbvZZiy3VBuJefbL+K/nA5GKYex5vaF8VvW2JtNaz6nG\nO2mf0K1OaIC26ble9NY9pYrqytCcdTpOisFBK/sWMwJTDavyPDcaK3b2r0z6l8yWe/+kZORkwM1n\n+vS+mBxXx0tf6GtBwKVn9Wq5PBEpboQb7z+jnDgqEVQGEQk44+zDxF6mTiYHaVCLhGP1x2L8Qxtw\nPkf1ixuZGNM5w3J6JjwoYA1WqjGzNXQ/2I4IFQ7+zOL2BVVm8a+5aGNvBOtcu4B12kHIJpqjtEJq\n3tU1eussVADMAsGVV8uDeYtJPvulbF/idSwsgG8crk6BAOKJo99VQxAzmHr6hzse35prsun1dsY+\ntbANM8RyL4weuRCRdH+gaMfEFjRTXyRtKzs19VCSRxpLGUewvAFPajZ9ighUQ2DOA7Kr/rcMTxxd\nrh6hpvfsAFBAQjLiKMsH8ZMXPqNGDBjA8s7TGxd1KmM66Kj1RfzFBtlBuz9LglC/dRn/arEJkYKW\ngOxCUP9SwP1tqpMfyCFKkHci/RYZqmjbNlLH12cl5zMhmsQpiIcZXYfQL8enrVutyHkc8Oplycxn\njTecEx2W4yyRww+b9SpNrQwNcQAZHfUmu5afg1rtbUHZmBW//Afpurxew4MlsTVbE/q+GW4sYS08\n5hT4/ITaA2T979WNydM1h2SItDPecKYro2NCBuNGPCj2smuGGwIqTTedt7kY0lTXqc1QprlIXDOv\n7A/WEW6Ks/DyDbzo5ebBQ9k/Or/ERzVfh5qWgkq8yG0qonueIlbVexyJM/7sKO/BjOR3x/FKDD5A\nPOch29mk1tOqyzjUVo2fdU4B2P5yIWUu4LyA1+iW0TzGEcAlb+9A3LJHWtdxf5XRYSDst39xRNq/\njlN38Ihbn61REmPKmA+LoB8LUMaREXZsyBT2mkJjbCqOmNANgzEAOIj9ceuS25Y2KtrSdejGBdIE\nvCBEfvsJHNzt4EujHKaeJh7o4NDjqLcdEp7ed4Ep3cSOHMCOA874EICbE2zaW5mDE8TG62+kJMaF\nV28mlwI5fMFxipXSTKgVDY4Vj5EWSGuC9St7IfruwsQ039cqwvbAOIuBDwEDSJc6lCmXs/qZhmZt\nnFv7j6yW+vhyh9F/M49mYXMIrZDI2IQn1meVK5DQbu4ISFnSDGJl+UGx+F0w292X7x/NZlrDFxjU\n8F8hH3SoFUjtp3cdqR6J0qgyyvNuJIK0pC2nq9IzjvH1k+PjKgFH3e23kG7suulbVb/rfU+4p0A0\nUw/8qfFdt9ZBcVINnpEPSUJScU20uwWwAzXtPblYceO4Nbetd/Rru6gMmzl4QBV6dHDFv9Llj35m\nrcJlg8L6gZdUkbc5dWUef9LywyJ3ifFwzOukFPVGj0p1G9hRSiNUqdgpYFlexuLPL30vERjJltwu\nf4LrTIZ2VSuuoDz3yvK7YYnre2MTp1IvJIRPF0FnWr5WUuDhARBzNlManehpegpS4ik+5bBOARnk\n2ikf25Ea+euX4IRwUJwiPzAGTUbPzL3cODFaJ4mHcPv972AeFd1T3djc/nkOpMRfzLbUHz1h++GZ\nfguK3eWFxgEnwvmTBOSV/2pqlydJB+j2kzDoBOhHJ7yMYPINzLTm+GvY8+PE6TGpMumpLB79DVsR\nwtH293Qaqs60uwABd29zk+xMrOUEivDU8FIBU3QFpa33/+/A4nI1MVfVSHknip/yEcpuNY2qPJsT\nYuN68cBSWDFeSQJE5yXwjpRVFkSAHd8nML/bKhBZiplgzijzI6AXJOmkqclzuE3gbvl06XzNvh5g\niwbchkuC2q85hHpT3w63G6WwlR9OlnKpzSBsWJI5MiFvl09L3irrYtbw529xtermE/blvOxQYxuJ\nA3+cCbwrhbuASE/lxx/+CQSXsAGEFsG+rJZf02gTem+flBUQWxgYw7USLAXlR/yGYO6KKUiU5mYp\nMcLp5SF0ptsnO4GjOAmsRzhq+nFaThfDeXAXowTEeuWN+d56AInospMZc/eW0bFPTbgOjid6z1Vd\n+9+s7tiYNg6b6j0iAwEiBa8LX50Gz1E8B8Xk0bA4iCfVG+pXzxngp/ZgDAxA6x4B4xS8JSzvBqG9\n3fF/tpaS1x0ZYZNKrC0vl9eX2oeN5I3CbgEuLOUU1xIlzEYHqt8Ta5ZEnYRUtbhiunpXdVyqirCN\n2dgXkldd9U31gMhMY7qFkzBGBtdUApeaRyAGLxKnyg+nwnmirKX9Y3rBKSd6L+R5qhO6n0UbbSzD\n+4en4Cmiy/ti0HItxFAe4vWNWKSwEzlKaZ2HLEPHIUlwN4xiAAyIeXLQP3SyqcvdMzkhMFVdQYhH\nM2F1yAOo3G/JqR2EjrPkiLCy80ya2Cey9fh2IrTFABUwl8LswS7gb3noQTWyDJTWhVsMOvXawU6k\n9W4Jitv0d/+g4QNb1K05p1NtcnLpsIbcTsGei35vIairYz2Wpukkc+QIjcnbRoRYwr386Jd+y7da\n3/zxTz0ylTc2RMTh2TEZRm4kwoCvMb5bRjiCs5p4VDLdB5NKcfMPq/J+LOvbN9BdKd2e8etvM1x9\nZ83qLpzhi7vatfxsU6M1tYzeP0N1fDEQPFerPkzA/sJJfcYa5H+94+uMTRANw63xIlLDhmnCm9fB\nvFsT1znWi0KNE5YxMVAP5Nj3aNk30viM/aEGcXN1+348mdh8cJXP6Se0n9M2ShPtIh6uOzHcNN4F\nXvgZxyI06BOFPCh6pPn8pM/4wkj6M+5Q3d37NGdAT8T8ei4zfuLUhoasw2cJjrdrZ3LNelT1XVzr\ngtfkU+onSthCPR4WS6Xrw7Ok/kkEQoYmkdI7UB9unluvVVQ764ldp5OlFSL6uGJlq53fikq1mMPd\nHtYt08ogxQnb+cC85LdLrpUdkov30YC0DE++eB3VOpsBoGUdgSzOw4L/wn+VuAsCWq5ABwRe4fqT\no7SyMEpq1RX0wDx7yvM1IrLxDdnN/w9pE9XQ1ww/ANlsQf3806Yc1bxBlnH0iwF7F5dr6ExWX02C\nm4GMD+POG+syw7glXgXQ0OUc8vp22qMR4sD57/Oul0voKncx2id8UccXB9vsMZIBhX8NK9iQyJK7\nYG53Y6spKPwBaJ+D6oCzIRdMrl47suvOHOFMlq9EgcKZSM8cW1EeM34Q9wneG+hmi1jxmgRg05WA\nNvs9ns0cBAUoExbeKaTDf+UdQg8kQpTj787x73pVcySGZAe6vE/iMHRuSiZo8GQ7v7UaVF9ntzDG\nTtrPWvFHyuV/SDdzax+LPSONzmqYuZtNNGc7rSFNjipVg81YgVclfSx1PGAIfydo7Z24e3Gz6NIU\nMwj2TtlQKBbeM3mx05abZdGgKr2KZg/G7mtpHcWqPBAwGoOynrpV4ZdlOI7jP3SkujjjiUQJ8FdQ\n9dU1KADRL9hr5MOS92p0+2CDZXdgK1l4EzeYC6fuN9IyAXHsqWhfswpOubjlkJfdxHP/GX3hjyHO\nUvlaWBcZDw7BAWM+AX28BwSssw+yc8sPIxzjHKVjNVz51Vpi6eQgVAZfgVeW/CVd4po9zDauDBPe\nLW3Ffrt6P9FU45qwQ7MWE7oZ3zsTc0evg2krhbb9dLqiCoz6VuCkphBd+BhX2nSPTl+BrGC3EtT8\naS6sDKIiJlBJL+8+GJ5RSEQoTGfqIs6ND98n26dELJI8S0uXSltTPxBhra5yloAd2F4/mmmPjyWr\nTQxaz9QC3JZaY5ciYNddoc6aIflLXGP2kZlT/V1zu+CW+BExE9WpMnVToGI8RRt4jv0a874Y0An6\nHhiPkeDYN6VUowNBrQ5rQnTkFaMpJk4oWUQE3v6avp7Y5alYEE4wCED+ItD2AgaKwC/nFgLMfAnZ\nktUhijy2X1yEewInb5S1xc28GWJeUEjeegaSJijHmFVUCwrnggKTZlbyJ2a2ezSse3QS7DNzMLsw\ns3lvV7VDvQazHXN8RAgvOB0B/CgfYjwZQnyysjBMCOEXr9ltmJw3ogG/vxGHBu667EeL5qOCFKZS\nK2yY/1setEN3lBeyWFiOt84crc97yyhIN9WLadvrh/f0YfzTa8/jZpqi6C6YM8s4vbQgQayL34x2\n47QkQV/JCgk47e027m4LJl2YsaOwIdm0CLnMgOgEGQPFdyZktwDaQcho9eG3wdeeDVrkyzQormhu\n9aXm2HxMwA7LFBoLoLMTe/h9G0EmWJjSZJbpYBym7mGdw7mGASxg/8DfPNQ061R+2X3xcnmG+cIO\nvl0+UTTis+WrgnTXMMvcqbanhkRzuTaNKehiSLRg6bGYM0soIp56mfxn+lCOLxRvrFVCb4SESUTQ\nh41pLzHt1noaHrzs6Gg5F6h/f/xdaHC5qixpm+GAiRp0dMj0xX0roGySULb0Pg5Ik9k6Txub6XiO\nZgO5zmj4Zg5w8I0AnXTXRWRQrHzuRzUxeqeeMsb/JspTSY5oZj06H3vlmxUcBhypLvXrMLcXh/Ls\nc3bNxQvpWzLBqqdhy2tGJ8fAWkun0YPhNwlUU8lBB4Gk06kgUQm222XRVdAheeWAjR8NbiAop06S\n8Wy+XiAj+daeCKkiouMukARqbllP0jcynVe076LG+ZgkcNqoPU37HDyH9n2pGf6ZkAQuwFeIbkSF\nPg4iQ36vkP+KaDnRItQq5Ii+DKzEOXGkFXjeyB2kGs1noDV9eD6DHXsQa0azeB+0c9fKSA7nV4Mx\n1BtiwRMnJT7JPQOciedKCuaoP0Aq+hvnG6MBlo+nAOOlQfvZ8qQxlg0laf4f6XLVWOpAeGt6y0pr\nAw0YlMDiAyvjsrh3t8P4eyWaZSoFPRIJLol9+5QCyrLlm2aVeoMUtwJ1/53pTKnTEHcZIZfi1n7e\npjP+HdzVIccamu4mef1McNibQT4nUfu60LdH+ZQICzwZKDu6slLfWc1KaTXs71UCJzmFmBNREiS2\nXy7c04shnL9MVkGQUM4rVvlqeU7hjpj2FNlt0nq2A7NHDHkEArM25UeIzO+An0jC3tn+qfMDBZmx\npl24RVKkzC2NhWcwhhc3TGrk1gzXt5aE3zkSTGv9pEL/s8V0XrlWQBLq2XFeBXgLpSAzseg2st1r\n71IH25LcYi65u03YZ8TaQSNK5ZQxrVBVO+JVdqF5H+UcYmJxyBsmvTOso+y/z+nGXXnu6Wxeb2K3\nPMCSNT7G7TIbSFmkl2cSMzEeMwmt7AyMdckkJzv6cvcC0j0fLIcJ+ygBucF6mrNY7OMFKMatX0PI\n4UdpryZPtTB7sdMGLH8FqHkw0PoHM+53+V3rRDIo+ImSU7g97SHk4uMmW9/lU3+h4QEVhf1SsCoH\nD9SCjVbJmWSx+5ck3SWahLdUTGE0c66fdQ50VOj3xxA9nvsgL6x8+drW1LZr6SHG4Ma07PvqbId/\ncOHrnVi5FevEja28niNJV/635eMPcCA8uWcnSyTm1J3Fe+CyROmWWUPs1QOJLqlM/Ai2tsSCIaui\nrBVtakmXqv0aMhA33NdtZu3vrog0aJfleoLXQUuDYIGcGc8kfavMyQBG72eZnrVz6/tupr3lLY4Q\nxVGFP4Jxgxq1oFD+d8nf2DrnUh9AyNvtyyOCKi7z+ReLuwDg4jFzd3U9eZQ7WTDxuOYKmerT5+UO\nG4qs6dNLomx30eVvW25a2Z2qtWBywQq/MaVipSr2RmdVavfkdvSb4lRU8c/OXc2j2EjLF9uwD9ij\nR+SremaAbHZZKoNbBX79rPCGwHPTuu2e/3veCG7t4yv5s3WUvVkFPocYD2rO92YBt3DE5NjJ8kgM\nBCj48v+cPe2x069u+Nco6d7scSnHpPHHPSM+6Py5/LgYVagzcTfjK8PlJARVcAMsLJiBvfzpO+zb\na4Rs26CnEdvlCgaKBV1YLeJ2dXWhGAXTQg7SIPEe+qxZanakqfbbb2xT8QLylB2wpP6fAVc2MhM7\n8GAoec89XNo9PAPakTkcl0WxeigJFRkS527gXqWbZigV+8fVkzfLL8ARih7A5Y8faOuGrHTI1D3/\nzLMHy7/g+ESSQUAfGIeRgrKCYK7EMouPFRuxC5uxAYpm5W/pKsdIPrBHWTqvC0PZClvqzFXBi97p\n9keo4Q8i5+/jCqoMSKdh43uf/t7GW8Dcg5wWxhGnjWC7PMUgwEzMeruqNa0zB76K0zeUaOmh69WT\nQE+NgpCq0rrPFoR4W/hxQ5lqPWMYVQs08oixXrdi4qxOlpMbrxoLJ9dbreMCg21g+h8idnl0Tl1L\ntZ5uVIyA0sfNcXr37h71rInz9wjZ2D+cn1MJf9A+S9uhwm3BGTz/4NlrrXLFirxI7VfKkYEQ5kS9\nUmJtizU6dQ6Ehg6JDdHxuh5l52FvU7VuMVMozDJdJMvbkeQHAh3I0RSRxjaUk9t20AqO38NUWado\ngkUnSoEZCLnKpWk0YPx/LgMwFeFUGPMwCcZ+o4LM/G/XVGe5eO/pecve0eHmEnfeVBoIeGUVNgM+\np5FXp1hflAYwWYzb3FqUrZM6TMi1jBAtwoA8RkCsrYN61H3rOO2e29xzDffAshtKB1dXBUfI0Zxp\nVN8o0s2S0sIOL0Z6Y2+38Wn6hSTm9pUH+2vQjPt5mmWo7cg22+s7MbGkZISOJNCM1mCrD3s08ZAJ\nwSe0IXxQ9GoXKl71fWfyxDOEN80E97kYHfLwT/anINNK4DYOqinZPKwL6lPcmfztT/jkkYeC47vc\n2LKundEqdpIO8cT/NlrAVtDH6t3Fm9VABN/HIsAxIiNvOpHUSrLSF1keYvjZzNPJ5FRQgPns+eTv\nGP8JvC15MCNYsPYO03i0V8tim0p2g1ZGaidN0DRZ+8QURKlhGPX747Npc+Sns6GK2hOpqQs5xmC/\nkg05svfxeKyBc+mnkDT3BuW6tl06gkPpjvfgTxknS3UtGnjHnLRzXmIjQMl2IQ0m0gzzccVzi/72\niZtemsxeuumi+UP3MrCWaN+wN9xfBDV49pifJbqDeSGoznX/Zcb2XT9kvtBFWMmlBG27ZlbXviyw\nPnR21Qdpe9Ga3f0oQjJGGlKrEtk8kpZXg8bTyYQAlP0cxQpKZU2EjD5JPPrHfj1jG8shz+Fu/9Ho\nMoczpTM2n3rQNUp7R8v0cHO6ikm9/A1cUv3WjysTiu7SuCs4gBkotSNY2Xk68SXZWzYgFxmK8HXy\ntx9sdKEH13yEbULEXA+4COwl/PywoPj/Nl+Ew4Pwcm3TnoqS0GSPt7HJPOo2hoOxxqB08tPM+X0t\nB9E3nmeN6WGtdPk5mkipZRl6B32i/Zgg+ya/eRdCQdf9fg9Wyl1aioGzWlZgA8sH0At8Y7gl7NYv\nGsBJKYY9eIu3oVdG89uBhlUj0AOPcTOGIyt2OwESMxURJPXjak9Yh0eSBLOasPf3rxt91kWGROIx\njBiT8eMt0OnS2yu5HO2Eg40cmIqsC2vwtJoj9wOdu3zeceXfhMsdMoEsk85U9XUNedzDXBDY+d/K\ni529zO4iKsBwTRgnL3+Qq6lgmFdlFvr4PT7x/PusFTxAe30moNx7vtlthoDXjY69raOtJEVg3oac\nlEa+QrsLiy6szONetja8Xwm35OWq22kBLLd/fhaSvhSgxFNpHlINTa+dJ4OHbZshSM479f3oy6Gw\n36CHvvAUHpTmQiWWOqNmmUHHHnMRxvyySNkV7J8hlPk547mUpXPDCAheNrbQCq7Zg9QcaiQWd9qJ\ngnrFkLP+BjGxkvJwrV+1jUS4ymZ8io4U0EOc64Tuk3B2OXy4e8bHbNs90VoNbogNJ2JBBrluJx1L\nQ4+/oI2p1bd9BrWyi9lb2v+KL4o85RzAFnSU5vGSjrIx3lm/ZH/QN8/90o4qJsXwnwzwywuIEieB\nDYWlvqUtcnk46xKGSj9rr/PSTZBd7gFkW0W3nLbd5MKKjVDxtdiKjSV30e6iwgDQZ5rKvLaEPVul\npiJd8wgHGnnZRT6oMODzea5SMDG1Mx/Uu8SQZWcFTOb11D7MmcZD74Dh6kGsUS+qfY/P6LK5ZyoN\nHNMkZtEiQINbI3DG2LexnjcnXgKqZm2ZXGavRz/1f3A+4d4Rw6KoWfXIZOVUdNn/l4FxU3xw44SI\noKl1tT8NUagrB/gafvUWFBenLnxPxW0TaqMp+/lnAdDvwHLTwf2p56K21HxTlxXAb2QmgQlZB6bU\nDuYRjWtw96PcNIcEhaffTdNRFC37g/+Rw8qIWX4+euwL7s7q0kxKR4/TG/OfLrnBR/5+jgJGxj+u\ndtyDwjwrtChjTru6KPXODLvAm97PhZ8NRtb2Yzn5a9LjbWYSBpxjf4eyfAdYjEw9yPbjJpi9AJAW\nmwhWv/9b5rkxkeCEr4yQ7tXZTLx9l9hQktow08Zlh6pE4/8M86ah/0BFrTA8TwV1MQM9W2oncjGH\n+9q2b04TNO3wbncrECEi4DtBvtfYup7Ewyn3GlaO5eYLTg2/jiNmLP8fy893XZvRFmwsQRwnyXCo\n2nYZv3H6iAokmm54kiA8wDeKeZH5bMVRb8coUhzn+OdVrFqyf8myg0lyTJzy+bzzY4Pah1/xh3/L\nbI1bdfdg2OoVS3n1aXMOJQSoBQzk8F4lkSgV14x0kEgcg+6I2cD6IG6bQHCLflY17NMmKnX7MQeQ\n9ARoZL9Ftb6h6jt+Yj9TqigvDbbli6iYyt/3iLvMaE7nKbkI+BcyGR8FeD5rz5Sukk8W6WTDkgsD\nYzu0DTmAkRvyAwCKiwy6bzCh4dzKWJOK4GMV+psXZepr0io43Re5pRIkbdTsNzCzimW21WR9ePZ8\noWGZGUVoCCHkoM+VhFyZgrFBCuEGtlTrL1OhJnn8G/vmj6GzP7ppzjqtQOJdd1NT3mIJtM2MU2jK\nSJ1bL9b1YgSVmGnENvIHBs2oDoiFeYB/AdsDKbam8Ofe08wTbM09FVlDEjl4Kvym/+mlqBqdjB8W\nBTlVuLz1Npwe2Rqin9pAfmf2mro+7Q+P1t2MkMMBq7+mNXk6t7f1EZ9CP//mfVK5vfUlm1bJwc7h\n7zjymmmA2J7MYyTiTZCFm7zKpr2m0yARdirGbh5+XEerjM0JG1JFcunC/BfW4EJW+aPNSQhpCcmS\ntpvSqc1TiSkWDACL+Kld4mtOaUOVAjJ4IPoOKrJtnDz5EYLStpqmXsohKLCt+sy9YZ7t7NEdk0SI\n+i8nrAQsijEAoguMLC2r4fcfepagdfAzf18AS3Z8t8vItfUFlgvlByAWPD0pAxEeL6gRPo34mHvp\nqtb02SaAbEWUaCCZNhoIT+MAPCCwxxu6OEN9VW7YQw/hmrD4e4GyB19xhrNtuyh4zHoN+FX72opr\nxOkXzzghtXGGsQ2q3/6cNaNiE7P1xigeetIkjYaEOogeiEI0BuF1fbJDaLfReX9e6jXiLvhJ5AQe\ngiPAl3g0FjDUcmDqjRteAhE/PNHfoJUSgu55pPfO0NY2t2Z2Ye8DF9v/uGaVuFA1bhi9O6ZJfE0V\ndCrNoO9JVtPWadZbKqRoRYR64EhOYf8QMWXpQea8J6pNasP5XG62E3mNJmZhsEhO8da14ofQAFnr\nuw1npXWWvVGW2OGong7N2Kwh7SRpeKL+2tVeUM5oyRkkegprU8oY6yDTmkgW4gzR3iUD9r2yEQQR\nEUrnBqjowX6/a2UbkSvengDsfeYrIn57XZhpweU0dH5uBYP5FkquBKbngRzDWRIhRjpZOeNBuquj\nX6fJiQEmJedr3pyKIPHyXEepzbIAgL5Wuhzk/LNljrsUkTz1/vK9wk75QbxTXjCCi0MlhBUnf0Rn\nT9gWptFSKOOspcWHZzz1bR3qAF6yX2iGIpC7CBqaPPjOSnOIr1Qhts3FByUz2W7IrG7VFIApG2Qr\nZEpY3450S8oEjLqImCdG2XYabHF3KyViSlBMveVAn1qZGku+UFjoqKXKLREhng3hLqooi6ugvH3F\nhLD0lteBKSVsoGT5MDZ10f0FHDYuDu8pt7Yx+avdWuF0XQUqscn1y0GeYS5kr86t+F4ToSMW3ovR\nH9BqBMW/e94nritukUh+pUU2ENfgPglvuqcA55FabulEONPo2iV/4CdTcW3iZD/sNsGF1UHqf12a\nGB0N+vCYNuUpx9LspYpJWTeHOQslPRs7vWN8S54MBEJuS2EKLe8/vgESL+G2BnW7yrnXdPGpYRi7\nantqD/KGvHSTv4C2mNcnINFPsx4e4JPlmwJwsIHL8ez4LDfzGkbQo3znuwcl1FgqMpr/rZfAbjGd\nJnMlIYAo47jNmAfLXWB+SdpPEJgdYuuRi2GQKLWkI8JUR+/CMdKDssgcEyaJyvWOzURvv1hQUUs8\nPkMdKt81i7zFYQjiItlszd2C8zczwlH0eWE2I/wYLwBYMkRn868QftUBc7WCXFXvjBndT65IzaLk\ntS+XJHy1Fk4Cnnkwhr5UiOJVKXMm45H5EKxjwXZ8si08tIgWT/TPY7OcTvYc4EdO5sqbIrOIlxcJ\nA9IOjMcJqGbEoWMAtk2ASak4RNiXlg1zb+mt4fLZDqvemjQOEytIdpDjsKXex4b1kwug4wZmGlki\n8NSMfJNHvGf+G1NZ/qm5S3ZV2kDMvsq1CbBFSw/PxZ+mi7bChotalY0y4uMUAOBSP9kunqJAUrMn\nS2uohKVUiU917LWN5sndUR/DPUfV8pwKaCkdxF5wwUhxZriym4suG9nSYCjgTo7RtHPM8zJ6jadr\nTOy4MQeh/41kZsJ/XYpc5ElRTokVajxpABDhLz+d8fs3DQLWhTQ7dAQFzaxKEHPQYD5+qYLkSURA\n9WeBKvZqJTRRibHc4nbOfxRMxaQc+EAAjELMdOKS89L0XejFvCUujsz2fzQBJkpDyfKoXWLRko92\npzHpWTlhRDA9s5b8PX/AR77wA5ArUGNjqLmVzA1pp9zbxZdgpjqCLi9BNmyv/dg2HOuQs4tgw0Wa\nhIkwx7jfZ3N+FEnXqMihEhWujWBIpFVWJJg9UJ8Cj597k6j613fhjn+fQC3KCwnC2yGWi5ohm/8M\nSpdCBPF0n3F7iEKeRYOe9LRZGXKsa7cPF1dK3NOLqS9L8s/I5RGmzzYpuJX9J3AdnFkFX+eNJqg0\nKMrTPSxtaHUEe+by0YZm0zlcR9t+oiatQXde6yVVzmFWgcmsoz/fDx/AOOCTGxthX7cLvkDnRut2\nzdGY+x0SPOUVq9Up20+HVCHHJVdvlDHnRcwiopLP9EVVJJ3+8+zXcRwdR/W0qU3e3tjHMQeLcQKh\nJEXrK+Byiw8OmW0QMfzy1sWD0q0/sbMxlvt4eq0rHv2LvmpDayo5mQXKasNBMKdsSCFzmjkeVXkL\nx6lrIBNQrnRK3F9WHeo1St/Vlx7gKX61STdUZx3s6I2o9Fu5kQ/n87oY5kGnfIYy/Sqe7poccG8s\nnwtvT0W1l8YAgjLp+y4ttwVZN1u2Tib7vNpCGWTeUR4N4HZlfTWLkfxHA9E6qHgLyLhFdQxD5MjF\nzFCW5kFcsPysIWupF6wd+bHTvxMd9+e6km+LqJvwX9TJm0/Tuhv5smOEetrL85LZL4hoOD3gkOD9\nux8mkIV156Zn5qAXgRhGCBzTAoc3gdEEAZuM9CMnvGFt7nYQqUWozJbVNIu84YUuW9UaohW0MdBq\n9OmTNAp1jaYXjqH+ZcW4yCPJEkJKLw97SJqnlj0ts5ypvSx0AsRbwVqIUkBHIRTEuqdwXy7ffZPz\nSuwzY87QGmpoKvLB/NF/8a/XOC/8ekWrTlyNU7kOVZdUUan4xgg+rmtb5dxRQOg2+Cg5yB2KYpFZ\nGLIJEaN5ePx6OuNsKyGAnoL8VB4CVbYL2YhLksaWv9aVH0MSEQBH+d+Hhh/hyb08on14QDQ3IPn5\nPOfH37BX1Kt4ZT9FhH9AqYK9+IYyvlY1QZqMYqku6WF19aB5M1k1mnxoD9qP2OCDsvW0PulTcPwe\nbZWzXBB+yCTURvqwPmCCGg7Botgo7UemIA/YDo6uZQhRsrlLBqrNEpQRRJvwcCZadPmql+bxVLoB\nHRd0slNjme8ocHNUYblDKhFKIO4zGW4vkVS2xu86jFCJP+AUtWtEoBbRuFb6se1EPWSEZccg/tdG\n3S+yZwJXmSQIKiocBNNsoQl0ZuYObaHJFh/ghdUlIm9QpTkoUQwAdD6P2fVXHsUxXitYILj9Eao4\nnl7koAUxv+egJe38T+XzWu3qJvZlze2xvOmAAXEjVQQfE0DmYJfZVFKcDVdg5jYqF8G8FxSmQcxC\ntIn4gkrqg6EV87gisbn7qspi0sacZ6Q/1gQAURtDxooDDK5gsV0NEhI7EyoinLXjZJ9SY84+Bzcw\n+VD19FvREqBGtziYVyJ2+YAO9kUgWbuDuEy3aFnNOeTv9ze33bOAoAhBDtbJ4BJZt+eGcbWYWlP0\npMcWI4mKtcX18daNTCZR+LgCAw6J/bR3KiArm9ML52M7oEzMMSX7skvxyTaIj1zojGgXeZXvki/H\ntGHQauTSObrzhFf+YE5t50078XpPzdQQVhn63OgOKp+6Rie0Q2OZJJP1G9PXiAViKajwJ0U6IoUK\nVG0LJhSYwAOF+ditODWEnyYQJx6u4HFg1/OYPbRRf5SL0HEyB2SOhxzRc+QylENCwbGWxkJ/MjpF\nucxP9yehbXSUmmAXr6u8e0PlT+0MEcL5+hML6XanaR4sMnepTVUB5OQKCOhz5bVdYkfJf/AZhI5u\n1tj4AjxaqRwn5RhHqqcjspa9oAXyD6fTTd6VkJtf79obE2Vn0/CkZx5Gc/vEV6Y/UUsQa0+HNWxC\n0KxJ/LqbD+0Xo9hk30nIOWumBfNHVFNABhSH0FO6hXe1h7DRvhESnhSo7kGWpv0N7/A4SIRMybQt\nC3MeWIdBm09lya/sOlRRHwnjh6BgZeBEtPqYX++mSFDadrZ5912qAYsGsdIFlk7+p6xospuH+IyQ\n1PP4r9wg6I1iF+wSIukIJgfswFgAGBtqgDHhfMaea99tCTbBODCxTlvVOkbfZwEcdfqDQJioj+nY\nkY//DSMVhLeq/3yvLCdiembO06ynPh1byTgwmALsU/RT7uf5DrZBontbQhHqEaFGqtf8irH9r7Cg\nJC23F1/SWnAd16dLnUjiqbXwbIoLMHbD3pnqvbyyqy7FNroWPX4qTHJMm5LbSMWNMGR/l4ucWMxV\nky/QnNMEU4wvxoK1RI+mCtU7cdIjq7I9Jx8vXkCdnLnAXFb9QNHosk8LwZfmibS/xe8bBW7lTtzc\ndbpZwB90QL9ATHHTbwX997qQwU6f8Q6ZjTVx8VzS23VGBt3KmFvGycKB6dmPyzvkFWiQW+Cs8bpN\nvwr1sTQF8HierHVZSIDcGGnQ2RcE9sHY9ywA2gug29YJOrasaChUvfzGHMkvgAeWBLoNN45Ptoq1\nHNYIOiNBDDt8b2NxtHOlftvoV+KQTNTItY8HuSuvucGLRFZ/ijxZMp7Gka8hw0omBjJ3K/Canqk0\np/nI+kfZ/ww8PnWSkJCV3iTei8yb9akSyGPtimN3DRXg+nm9F1vhe6ZjwvfxYdXsR9RM2YFddDJj\nPJ/7sbG2ySqr5AI3utiP/mJsP9zsIUtciEXpzIiY17AGEzEf9WZc01mBXJheccBxjLpk2hOmp7DW\n/bolFGQo1u0HwOCjvUQEN/VnOXBf9dUC8dHNpljvbvcpY97VkVLl1hhLXJ1B6CZ5pcmV49ukA2yP\nHUvkv0kKuJDG2kjj4LUJ5YXaAGBdch2MCw/ET+X9R1Lbz7Tm0oYfP/vj2oQjxfHEux6lD/Urc2oI\n1tAqwKd6r/F2M/RmthYfXTEpVDUbiw91v8Sh4I0wwtXOQr1qrn4qwtP90lOT+tlF2M8TKR+rerOz\n/5Xgv0CCYjY7xCg4tuF//w6fpvgs0Xp8n+/+RRHW9SZuYLcjNkECku4X/bNTWgMoAfJIJLIPFZEg\nKFFHSa7PwlQqsQtO7f3M30QtV+S6oPKAnAqXuAd8gNhhlzMJ4O71NOrGSrsYdqyKFMu1pulAegSk\nQZ+uiKAj5kh/P0Ce6xKJQVPByIdBLuUdKWrNSvLdkjayB5YrzBXr2uR8Z3qtXmVTRrfhblbKcmVx\nbSlQCkpVPIWCxkOIc1vH7QfvkHgkz0Vh1O4Br6JIiEDbSD3WhYk8pT3YrbNfBhL9XWekVTilmC+E\ncoRGgWwOOnLGcaI7bxVfNZzqrCajMQSnYQUipkO9bAkBHiMkdegZfmnOCpQgUhIRZAmdKCA5IYZs\nhcQolXWCTRNRgfH7AkKeeObiP8KDY1vJ1LZx2YPiRrfGHoQeAVKnpo5Q+XF4nsb5FDWlbSF9WK4x\n3r2tGTKoamdzjbn2uks7TO7uFcTC1hsh2iFiECPnECYbt25QcuA6GhkCaQDMVCRlC72dzdy8cM0X\nNLgdEMCfAuh/pfO5Soab4eZFkdYi0lUKw2JYfFUm0MsvAYUhYEY0Hv6jh5aRNCEz+5cuDw7ufd7P\nmvD82HTyuLstpgQVz9MqL2IrFX7zOwsr4Iki/sE9jhAIqK6UNb2lrwHuhRS6OETJDguQycwqveDU\ni5P15/S9l0xzS0bAffASHIiHDS/nna1mXJMzNA92v5SHt6iND+4NgaspRFj5McYl13C+pzciz3D4\nX0zSkKlDQTpJZAjzqyduOgXcU5sROz6raPi+V12shPmKE5aTU+nt5baf0/qBBo47q2UjQMY75tMF\nRVal05IPRf/HOpHBowN7F02gfVE7H44F4ERDK/Hq1xEtrOFK7H2U3ec851+lya2zTCJR/Xcf3VBe\nlxb4RN1NWaePQkEcv/YWnNpQx+wtJntRzhd2+4ZsxawcWl10ffFyNr4ZHupqLvX7v4I/hqx48thY\niV2fchI4tKi54R4OpsCf7NZMQeEvUspEGjrcQxpHVgtMx1vXC3/lApBlX1jOD1aTwr7ThB9FbEPp\nc37PFCi99PpLZuExy4twaIUSOK+4IOfnhrNzP4+bb4TObcMe1gbmAED5+fDlwoMUWWRMMzWsyN/A\n1xIrOrM7zcDWgLZLcIOfS0spfbW4l41PKSCbIcNrB3jFSBrcwm0pQbneAUYkURTiw0Js/NskmPQ1\nqg+UnXhDdicyH0Wfn4tVGjaPXG+qMWBP4Fx3Z4tA7m0jIrR68Ao8aX+cbhBeS0kMS/j246amm0/s\nCXDiO60Fcdr+vOQpO10O+LjBwZ5qsiJnpnjeaJqXT+Et9/jkV5Fjp1xJ3EnlachHDM//79eNvK8/\n/JKOSm4wMLqBigZLP0jzbtnwgaUT77pjjr7T1mI5GQzeY3nuBOxgyscRlg6qA+96hZ+yXXtVArTR\nnf8MO1ycpLPgEkAEsRETTvNnDrfQAd3EFl4I5oisHtpNwuZC9DBflnl5hDZaZW8INJHxcaYffeOA\nI4SZqRyHEDisnaRsUSDIwcwj+tUhOyJyOMFqPYPu3W8unFFJc5VDswkGf2v1azZ9sqH/+QC2r1+q\nvmU/p4fmXXsNumWv6mJCHSInANf3xj65XGYYVUADHApABy4FLykn1IX80gOG/DkB8tArpTRIvOnL\nymsyFKe7bYMu0tUnlo2TPt/h8MeCWZiDdodmrMWa35AxrWLyT0U3n0ZtHC6/Vdt/e3T6oziJ/eVg\nlSZVzkrl/F5IvDwa6bvb6U0s/exSaMcTOHYms2e8B986/g+KZ9CjNQx8CSaf/8NGvuVEXtnONlx3\nLAWQZyLkf9AlRhWJk8otSYNkhQ30sHgRnkTwxaL/hxEClk6MEI+Z5UJt9ycXKODHuULHepLOcPZ6\n14Qufb3ZpVjOTbYmikm1m0IX3bCoKrUhj9oXXboV9woaTYxH8fx08ABGoDz1wA4F8VMn3QUY+F4A\nsb8WtvEmh+XEuRlB1edUNrN8WEkKjj3TwLKejJhrheVTvDZR3LGzRN5p/Fiz3f35bZUALgirF+Xu\npJhpoFYB7CAMH8og/F+Jlma38Ms96J/JN2SLV6bxpjWe5s/aAFb/m5T2WMr6f/Fi+hR3bYw2ANUU\nuDrYb3BZizZl8oAm3Y8N/HtMXtiLLPo1FuXhV/I/dqimr5RkGNYv2vmFyIRzlTWvf1OoQdCpp/8e\njsVRC2nOL5aja1Gbrsb6xLI7v7zOy3OXXnL3A+5G/aRzJIi6OYRIU9iBmF4cPrBOeljwsiThjyIo\nKFFxbCwY3TLsY5DzxbRnwXg5/kBxZOaES7X3X+zHI5eyla9CnQbfH3EUEvY3EV/37+8QTasY1tOI\ny905e4+8SABe51gkubKLjrhy29UKH7O2fYpuytamltn64Cdq4NhqTcnJzHCqZsFlQR2d3NCt85uw\nAMhm34FtpsIt7/67XzcvPhzNtotKCiLKN/Cgm6WqDNXxXQdqWBpk2t0ruAhp3IlUhukD3Wg+LyXf\n/ZO143HqZM09ejrB30WW0BvJbccuf5qb0GgBxnj7M/eDXJJPxea5jNDgIz5AJ0m2xwLDSCHWb2Wv\n2gTrQlIYnhFqNF51eS9oTQcHL1NUd8J5WhoKC/tnFnYhqZPSXTiC1F8H3rMUITUwIwR4Eq5f/SMy\n9vvjUuHFbAre0sYO884yH76/735dC/HbyF81vbM7uEaXpOBXKXUyFJwP5E5GfEcWXmllf5c8aS/0\nX1aavdNjFTbB38PKSNPR7vE4GYr8QZDsjsYzycp5vB/F1X1R55r1oHlKyB4lyggTZMjolN7L0+/K\nh0SaDpL1hBSp0datucCgpkHAK1ECDvvnZz/EYs4aUJdU/3zroy9RYIfB24/4jNs5h5aCBTMkmeiR\nAMIDLVnyEReJ7oVzZ6u1b6EZKmUGyoE/NAWcRmSPjTUJgrzF4ERtajmDO5hzZdyTOkti/h4tFdJl\nsaYMNAKg0w+186Fz7c25LLBkit7BG/wjrAPz2cW6JI3S4ru5pGGi85VQsoeLOW80nnosEnFDip+V\nJ7aDxGq9BSwM50DlrWdIxbvLObiVnLR8Ar9HAyYTzspjd0FPpeLqQVnWy9kn6nIT5CqukkpCwcLo\nSlct2bLxTcQhrwQucx5/LHBYpKkrp7rrzkHZ6P+cTUcLHJNyJPZkZK3heV/f0OcEsM4EKLZpD0g1\nJv8wATCKBeecm7/VqyQllTUUWvP69Owt0G4XzttdIBz8DTPtaI6ts0hlmbOkcDTTvBf5mZ3rNmnw\nlg1mysjyO/US6Fuiq9t9+3Xofstc4bHEm4YBjGCH1IHTDzvQccKfnM/cqleRvo7H5eXiFsZtPp1G\n6GOcsXHa95RzZj79MoKZNjnpEY+t8YauJ+ETl9KG2HPb5yLpP6Q6cV2HTp5GNHhvtcCoWQBAiqHO\nbxr7/HrkWj51SqQJe0KV/R6u46GvpDHfkVkDlouZTZy9uiFGVIo58fKeM3Te6Crcktg/2o5vSjkO\na7Z8yu/uzD4/L9K5yC9W0SCtqS8uulGQZpEHMWNlzCWY+pOvRSTSp73IL0EUO6DI/7fF2UjEWTyP\nl7qk/O9HvnOrrWAV5MLHT2Axk1W7H5akhnhcPAA7Lx/Q/Q5iLoPNHVWxjlvlwLlwWq9OaQICR4jq\nGDNMi14HM8VyANmSUU50AAoSn5ABDzSXJ9eUaJT/oU+O6OyAckpg07u/yYW4BkTMw8xIioyNOSqn\nvyJ7cBAB7X6KOj/KjRLLt2J94Qj6UBECe8x1PJ+/oKc1U5SNGmaDsiJPYE42OuvkHxD9CXzez4zx\nMiigISEAWNHfQrcy73vctjtz9y0ieOjN163Or2pLp5RE+4EnBTO68tZ7DiFsYAvgyApEJfTwTzS/\nH+NfjaRftQPoB23DSbd4otwB9wqCTcgyKeHfwrA2tWNoBnRRDh43MiB/X3InWXASYwMqfd2bTAXB\nO2ZNmuvDjFCqHdc6XOPqtha0OlB3JmvtCjQqmRjfwBDEg9nRrUo5OrhjinJ1ZZwsA6X9Oc2M1jUP\nlgQgjlV0P/hsZqt/GDjLt30k3e6DvQg5Ye+Kvn8MkqXne8Omnj4K3lzvEKXPYgWrAr6+t3IuGKRO\nr/774W4XqSnQXDXYSsPlm5VAGXmAqncVo5ekdQw9di1hmya76/G8VcN4QK0J/Q5c7xhsRvZUhBbD\naoZnX74rF3GIzaxID8PujDrYDMP2QkRZijphPCywc/l0jsldhR2NB4RW/kYPN3uUqK75cVesEaL5\n5v/AR9/c4p8tdoJRCWfRRBN5m9RRDQl3XFMUCUPifDExugkQfos7EIKRGrXely/Hf1bqQd84KBHw\nQgmROHDt2QlItAPE/wtivVzftCklyirO4+OmfkftzxGbX1/QGxAlJyR0gmm6RvKa1YoKUrKgK5S7\nXscl6MYwHWn1FJriTwerIP4mWdDdbOdCyCWKVqrv72q1sgu9Oofps4WpH4Id8HnAUAeoyYdHVdyf\nJnSE8viWhzvF+yf1tjrLZZySiZWT+ad44uIZkAqC4GRPwpOiYMPcB2Wa+1jl9Sjtp6expmx+u/5h\nAqCBE5nVYwwbNJ5/97wkl/T0DZm9KVtrlWoLxqYBUhTAfQ/Vdd5kx3Es/xK0tvL1c62UXivN7/I9\nVqga2Z9NvKTT8owc+ZOI0CANprFE4IK8JbXKrTc2NMiULmEnCU8OGYBYIMnkxGLerH12+A3ChuLx\nHIhcg1avfqvOounj2H362C2fJYDtmMVv5i0y8x0+v2FBjrTzdrisolTypKmUZ2MHXga5ZGY7mXqn\ndgkFBZOS64qYD1nIn48V5Vlsi7LF5aLMCOZWlXOw8WmIF6glbehcEFsPSnmyeQWeFK9duIjIEiYC\n2S0COsdbabYyYPGGFpz+iI9h675DoLj4BC552U1qA3tp95Z5GrD+9NcJQeNA3QjGp8mHde/skpX4\nYkex6WxEDA5ppcdy4YJO/pIrDUz4Y+KJm2AHQ8G/1UYNLy3QQm2xvEdP165sZy/GgTk/MxGtmTrE\nUumAVGVSTzDM3pMWOXMbHsDiCoY+LxKBmOofdTajcbPQor9UnJOOh3bk79plZvZkj/kjgc1ipavu\njT6UFxbm9ghBi9L6eUME4BbN+EiorSLlyWruDKS6fq83mX+4iaCshfP6nQnuTU1728nJ1U7J8h9l\nq+nruftauizB/m2VnGlEUGvC5d/olcqk6pWiMeuemTJM5+/BeAZ82XblX62hnpwo2kJhh0byu56B\npAUGKnLdamBw437+UlRRmPWEp2UG5OrqjLR0JMf02lGeO+AXXllC0ji5T+qUuITeYpHEadr7rg4V\n4vCNuTSmTymv06ja7bmoQR69HQxh8GWBKzTOLLC0knyElBbtUMaLTK8ocsuJxklx/fiJ6dcTfyay\n17QKT9aSN/+h/kzJsmdd/rSI6eJuQzg5lq1pM9nNggWdnDkZteF0Zg9YFqHbGfJMRqZuHxiWWHYf\nhs6BYwa1Si9yITAbky6OYkMYRRXLKB11R+pmRoUoiwr0xLh07t5UF7xEWYTqv+9KueNxtSOeV/+f\nEdo7uzq0Dii7Z8WTX2z7Aga6oO50BUYS7Zu9EQqXr8lj66On35fDlpEVb6h0feMPSn8Z7CCYxZxv\nrrgpc+B2PXhRlSumar1I9au3GrGSzbXaP9tYa1pWTWneUxksfdk/VkDLBuWlUN3jc5hvC0URlDsn\nV9FN14sxPOVWYbJt04oVou/R5XA4BNMUei+KMqaZ9LsMWy3qKESHAs0vomXA0Q1xxXac/zDN7LsB\nRTS+2gszGrNQQd961iFcXZUTQQaittUszpL3Z1wklSTLGQ3Do9eYkpQ4MXTmKjEcUcTkDd/8NA7M\nahK/cQ2y1mYEyJRkYFICvafpDj2h3+Vrzbg9cJ/+E1y9pNY2lS19jiEtaCisx04TRLUodD8TP7UQ\n4/ijc61VHaWa3tTgXuk6D9hD0oCiJOSUItz8iavDq1u7eDRCMKfEuHf2v8Ddhmkd04t2N/NQRTRb\nIoNNHHHBrQ/dszA1gWrgEV1xZ0dKWps4R/gk47Ow72agtIRoPMhVUyWaBgxaaEF9NAB/0Knc79/h\npDrIRM3UDEfbvOJJfBhGpmEXa5waa5PjxFrms+lsyTs58QeBBGPyfXH1r00fkBCCrhrlsM1QQTrU\n048xf/oyN0tUcjE/B1ZIBe410V5kNJfAtxAh2VPfvVbgbecLqGm3bRUljE8ozf1n6ARxD6GASLmc\n3GOh/dMJqp5oJn2sOFwv+B+AYOeGsnY8Qc0sa1DnEwTVUhDCZ2M775dMR3zZGEM/kk1pALwGQ6Im\nCnigap8WJ3+AQ+x5TZJsjWnnsZFbKiAITDP4+5gG9BpBQwVL7bSQYfWAYV+HsZNkpN9DYVKoz2u/\nbNnXohT5+gKpBQYKTg+h6XWaT/lwjspKXQkftnXwIgZC2EoA3j1BVjXTu6ePnVHr0azUwa7rhzUe\nSNoCfmOWeqnZSvRbVB+fRNZRI4hAVPpgptKPpCgL7DekF+8a8+X+Rca6jH9KFM6Vat3qvo4j81hW\nxg4glHb86eHWcUlzAW4wQR/D6gOuwjzvEi1jMpNNzZda2vtnd6b2QWQHKGtf2V3gPQNE7qp0z6tn\n8zMGcmW/WdC4n3Sc9GSGmsVAzNkoJmkCpBSMUwSbM1Tu1dX8eqXtI53zosOPO/buxyAkhN9sXDC/\nt5lVZdFQB3QqqT4xDjY+CwXxguwKeogUHQlcmu2PyndG1/ZlougRvZrmb/Lkw6bwLFHnuYLBZbov\nvAFBpbSKNKvQkZfTSwYiDNvc8BMFjMmjcFamwmizpssKFLlKIIbAUGDo7/9giFPRr+jOsQsmEYM4\nvL/nKadZokw3N0FCPbZNG7oP3I1wFyii7Klje6QNyIu/MqYQmb/XY51Tt3uPm7Xfc3/tNrmlri9s\nqzbMC9eeiwC2HkXHim2p0c4EKVWinPJkmzzHhHD5XqOMojAJPhX+ZblrNiwdx7yZ9FDd+udt11t5\nKBAtGk+DkDqFAWmcK77O05i4wt2nbfCYpoKyN224bqN/dwJBUcvQDeGU7zCkK9cY/M1RyGyOrSBv\nuZdwpqjj52VMyhC4eSw0VKnH/dkjXE6ob2Bu4okt1VlwfosxgTLiKv30Nxqa6xsSgUBdLW76YgRM\nSSxCp+DlI4KsYaCpTLqAkTsNbWs/XXcz+KkpZwGT3Ak7gUk9gWYDThPEGhAMifMZoNiuB/frOteo\nErLJDy9+/CBi+mwbqwhlM1mSLtEL+QjKXQtFXnAoKwlV0A0S3Y1F3eZVIt6N7EGpp+GqKm6pbvJi\n19Uv96Xgojy6KuRIp/r7ylJhgsaZmktjQVHgyTwbhlwc443FUjShzjYUNu1v/lv/ma3v07n/Nu1v\n5Ygxneefjd/BazNEjUTdLMV+xI/8Z5v2ZgRVVM/EjyzoDUtDR+/Fc3MUuqiQt7vYIQ3vJshwAQ7H\nq6dkx314RtY4hRvZUCGU+rnX/qCmenpVXFV2xn6Cc/5OF4EXbr6RN/qhCuiD81yAQd/NbjNEOtMW\nVmqXqTPsOOPY+FHam5EW4IxjWPRsAIX3P6My6Rer1kJd1F5zhDJbArwUbEm54c9GQkVXxhTWYIqF\nvH+Qp0Yy9tyMUnRlASj5jMvgwe3cUuHPxlyPUuZK+rK5ayJVxweBf8s8NsE58TFti+6DGNH+GMoj\niJrcHMl7JIRez9U7WoBdNSTa6Wu4FsIQskSZAPRnqG1YIhSSsLnEaonRZ5jHn6PxFIsGHWLkRRTM\nPYYKNKVMipW3WnaHIgiN57KTb5pXBGnXQxTZWgNJ4Oc1Hb/CLPxx+jpJFEHcrEa1chVQZd0SORaJ\nC0zRLJ3K6naY4bpkuEtRGvqnEiC69i7rkR5IYJVZn4T0L/IaF+HxfL2jZBzUqPiEpBIkGRIoRoal\nnAnVsez+Tf1g3sKGGb8Jc7Bvv9mbKP5r+ciY4SkeEHFCjRtXAHTU2sIxj+cVDrOGcwgj04QZg1CG\nf9j+AucjM1EmfmYfM6GMwlJ+jju7bvRNsowv0BBNlF7J8l98+ikv4vmUYM4WSkRV/jc+XOLWD2y5\nyNpM1OjVk1/KAG/In+VQAh+vgz1+4/xoyotLH/qRGT+bFxn9tomW0+Yzn/gahFC7LGrb3bI0eQTp\nQSejapmUj3nSlxVQ7dpQNZ0NrLwA+G/GycUyauRzRBxKtZMNHDmjfuBZX7Tcy7YiatzCZ6M2eST9\n05E4HperTb/cfGMm16ME0VdyxSZXAmb+OckEFGyGvWLoIVi1AdQUkJAh5rbT1QIkSS95m6iNjS13\ntFc+QIFe0S9X0DKXeRy730ZfGzxDHl3mt004W60VSMKldSaBLcHxxkrXUno6fZskEcRQEFd8weJj\neZkjtL6rtwkKjYV6x+cAqIRIH2CIcwgvi1MM+SbuB7Ej2OHbWGsH+ae6kDWlG5RxNhyL9DD4xcf0\nDdxElbdQ8rphwwoJvoNEe02bsY8iwtjuSyD6Y6clNaL27fwyCzjLujIWDUy4CHvK7Vl7a2PLD+dw\ny3uIbO9kn1IMMIKHSlomNpPap52CEIksHGtfk+4XSYfSkQKKp/kNqVVR1RPQGFToDqSveiV0bWAu\nSEee8c2awA4VDSIte3mzaYqUYDEfpBfjlJ1kfUOttH4qAi0IgL4BL+9FkiKjuwGeHVs7r+v2X30a\ngWOPSwAX10NabuD1IZjK3kIAgJJXnmco2ziHkW63XC2rKj3imToI3yyPwL11wtrAgJETZGrJTxO+\nMfLO+/2U61Knhu2slj+hYdaJqoIn0DCviHnI7DIQ2fAgjjaBl5/Er7USC8yzu0STnipb7cjZiTZP\naakr4i4vGo4b9Bd1itUaJzJtsdWrkVcFA2gSmBCHTYdro1jelehFneB/aDR7mxtnjz4PoHdES47A\nOuvVgKpCzNoMR43wGwKzG0B32o2W4cyo5fewsH6eHMn+T4EedcuHmgurYiN62uO0nz+M7aIaaBjS\nbPAJW3sIHIEEdl1P1Qtj5bpN+FoHJO1S7NGnxpS9OU7QMPd0thdPovlaO1Whwj23a2G2ry9SoW1z\nY5olooVHpgXYzMH7/aKVZy7EIaC6Pq6ILrl+N6Ql3+UuOAhOVuIGmgA3U234T48fYm736NjR5Gul\nrSbC9/WbAzLVLiCWKyxHmQqbSEsaOrjhz+ddTL3rcvzVLwFzhjTqRWQsPbtItebs41tdPf8MvInt\nkHYDIMP1RHhTu/5dAS9h/X3tQYAQgRhCHOAE/4uMtfdvIjgAe8fs2gC8QK99+EappIfJfUkvZKML\nn7JtFbyd4wN7CU5dpNIk8/RsvM3z2u7jtDa1yIZZIHNQfTaJ8WmsrUrjGpbjbT5lPZoMiQt/jblL\nk5uJo5y4kpVNE9Mg+OlMSMqekZyUeFSHuGOBn2smMqko+UVNaCFxXInWjz4TYpqXp288S605F7cL\nLmqsI1yHvV6yXa/8DztLhmbusW0vtxUKU3I2h/KupFTrxLHKOWOrxyix7kJ4L/g8/PutXuU1kAoI\nAu9OkaBF9G4qAHp30Eb2fxolsyRqSg7tDREIfyA6rPwj7+gY9z+2g65bC2+O5XyzC979ETBl5EmI\nPjuXiDRlRRDNtKsOLoz98L/9GAnV0AudrPU+sgVjxwcNfKaRqib2icBzWMIIsL3QLhhQxLI6bZwp\neya26npYMw+VI6+huptBzOaBV//Yonn62HLD3MBmDEsZRbSRiedUiuv7FO2kTlQi66FK9h02Uf30\nzrbGSKr4sRI666hzuzBE11QBkJqOosb4dDlHX01MQSKIc2w5pKvfi1MECCATgZMZ7ilhizyPHPhM\nqYR6erClv/4mrKlfdy/eRyaWBenWkK0J9aQB62+fNvXWRJ3F5SQA4xtCLxOlSKoqQVV+311DUvax\nEm5l0r5y8XMpy8Ig9W/TOidKG2ruNkmtRHwn7fomGNnG+YRWvlHPYkKcrMXXVZYEHhVwrwv0FRdw\nqqilhFaMowQStCU6A/Mch+SK8shJHK11OJnt4E6n7GSS0VWWIoddIm5+RK6+DVbhGIGMWvq2c+/r\nUMAozYzqqMD/iC/ZUuMEFaGnsRaf7fDLta1A7VFGGX1JrfJ84/D89+TUzIoiJt2a+mlOv47F/nIt\nDAgtzOSYGKb1NhXlkc5js+oaoygWm3Nl2B3F52XQd7P+eJfDpWK2TjB4F1BX9GMnOlI5S3kWAp+y\n8m67tK5JQgHqpN0CZ6yLbololzSu4PX3gW8kafdkgnx/s11MMaGgmdlGj2EpOY3RmzfYb0zUcv6x\nrDj6PCQU7tjBx85GxXzUZpzyoW0vswvtkLufpFueFe13Lj/xkjdwrV9ztjg3RmEWpqEDhb/ewj9w\nMDgzH1m5Waee3zV6RsdM8OywzwGB7r3QEi4+TJUT7n93NRH2bl++VBegv12aakTzLHKbSb6HyWdE\nUctb0DJhxi6aBKuzwBDJ8IXilBnK5vb0oGMpyvR0+SIG/WehKC+lUhfpwyKzZ/x+BMz/AakXAFHB\ngprixyoHCJS+IyJRNTufZoRpXGD/NdpZEyuZEAOBoY4iuamF/oaWgXBZgaa0NGa7axmq8VyYXhhS\nXRaEXo0XFlyt34x/Hs3t5P2AwUqFOhBalvgxSFuIdt8s1SfXHA48jwEBSY2mRa/LrKm9DL7CVsfd\nW7AcoaS+xAkMd1ZA7zGD1+xV5kFBSJ+oUm+BHq35pBGjxdwPM4IYx5qL8t5y6LkBzYVXQeXrYz3n\nAPikEn834V2RN3BXwNBi++a9RQG/9kyZFKAgjy/EIEDqsZ2Fz1a5AD+kRnZMq4Gy8FqfvtzaDX51\n/24gW4s+KdESku5GMoJiIdxYoPSC5yYdU6maW2zfvhU7j/VxHIVkEAuL1jggslz7UvWmLvDQSvyg\nAOiGhRngYu4hcVry1NbfF4Y9YOxx5VSFvbZcdVav2L76PYXQvfZa6b5zAj8nMtYby/auDzpCGggX\nIFig1IHnalQgAmlg++abElpqAE9+F7wlpvxSuMr9qjsXMJFa1NLhTAuYn6KSATMLJtmc5ZgFjtV/\nqZI83QMNaqgB/sFXO/zdaW6lc3DKYv0khan0DLyxC9ZYoU56KxHnwcsy316h2kq+KlFI9JUD4R5K\nk+NKgW87SF7e2IsYnl9F4WoeUQ9uu1TrYwvbBQikWhMo5zGJ+jDNnZE0hXYvD7zLnrpjNxk8u1jB\nVI3+wFkgF3y9dft9r//mAputCiFpTIwLsQE06NCVgTlG73PCHAGOQBkEBW1i6c/u8at890aDr9FL\nJulPXrkRHnyQlGS6bml0RA8vNJpoVwFRl2QRt2qUo3qTbXDEV9aj3xXdfeEseUR6MQCshhixhNj0\nKU4YYyNjpsnXLYyHerXk3ioDeukDGLEyA51ZK07Szu2UDcIFqZ+ab2ZHiovr68NcLfw6YE1qkg9c\nYLT5Dk89XCyGIdn3pgnES+Sd0tcg+T5Pp7nx1EigHx3ZihMi8Oxe/D6guDWy5TSL1G0ZaC8BvFYa\nh1C5Pfr43DjEoojJFMUyz4w/w5lCEUBEh6E8gXjAMVjzFAsA7vDjdWz08GsKz+CFWPXVVrVAaIRy\n19k1gGQ1MRtI7CUf1wWh7f416K2hwjHgzz6cmETCt7TexIThgarGxn+VSXO5pr5O1/Fs179fijJE\nLmwfZInZ5GW/PJnyfU80Z3xD7Jf8tA9KEhVmkiNE+SX7QVCho8sBVQhT5B26NKZrKHXkuFWKcBsM\nBhB6mZkvndJIuBm6ALke5fJITcrvcci6rA987B6eGw2NVJK11fP8ugBJBkmiSCxH3U6uXThxgqMz\nPujL2p61OUB/0gPUXs/sr7qt6X9/kYDGwejPI9ievkME+XteHvCyDtPlq/mjoWYawo1wDIP2NnLV\n+0QatxMMZBMlG6naoEf4pifcaMe3CAyIAlbYCkFgKoMf0qVgdHd05KcNusDkLqz+bNqx0PyHucx6\ntQNR+G/WKS4eXcAdwTudTPLXuqY4T5dXr3EU/fhG2oKFgHJRrAIllJQn5it+B1ljBrm8BMXVZC50\nkm/y/Dv2k1RZg83xH6UoGk0OEw29nx+XrBNqjLBViBHSdzLAg7XUs4irDXyfhxGycqBdvG0a98Nk\nxNU46vJazVxZWSL6U6mAe6Sv3Sr9jGmNIgA/VdbNk/SIP/AhthEjNhk/19pheo85ryTp4KL24Vhw\nrSotkbHebmTArYBspDLozvV51DeBkxnLdq1AwEdI+kiwzBbiud1p9rJEfRCLlqRYOI2rNY48L9Lz\nVwjSLp1+SKY7ERb2h+5bygkAImLrivJNuv0yj8p03GAPfu6DwfwlYjr/ZSn5C713pe6Imf5odEyk\n2g27gNss5gKol+0fnIRlZrAdBphbK+HDGns5LVFnXt6nhEEzzrhmhY5q8YS8OBSR09NzveOjphSo\nMFsa7DV6Mx6FidSa3xeL8Kiq98kSg/JzKmT917YSdmFImgN839ZxMPonkiRYfizHC0bcdFfVJC9P\ney50x1ZvNhADKvxaQoVppfhgjgY4RAL3yo8CNeL+8diNOvxxv7VXL6VmkVHb0OPSK9T7jM0UNC7g\nx2kdywCP5JyEAE1ZYgyfhp0cZseW8D3oJ03+f6aWUefyoDW+U7lhbahfjP9EC67VrkOC0aA2r1qb\n0EGdy+Wgbo8LwZqlv+i0kT6JJVzJAs9m9mIkVRdSau7A6EtZ++Gui0K56HTnHxdBZpKPLfaMY/Vq\ncO5ShwiXPBEzE8G5dKmjHC+z12W1EDxgsCLar9+YOAjxKhgHkBGfg69+NmO0ydwiFZtkb9kQn2n2\ncakas/WtmPRcBrFKxTJv7hrqsa0tATeeQxEfLYe4qtlUzpbtLY2FdoNRQlSxUGJ4pGgiCSx+x5ri\n5dbUwJzYin9/1AkNrajyQ1igqFH63Oe5iA05U0OBHL1TZbqVJu91v+1hHGccThB7kV/xn+sWCL0Q\nmMULWQqEWLR9aFsTO9vP+2fvOf6Zwuefn0MzofCFTwq/kYuMgyppHBeqD0San0S3+DlRWFbvQxtd\n/2tSB+nGWbiKevmP/K3gE8oRdXigzg7xbPH+gh2lCC0wJmKwTgQwHIC31x50ZJkg8cci6fVAAw/C\nVHXrDrjZSiroK8utPInMK9UgiLiJZaxnv6VMTQfV26pYRuUPBEPpZ4PLypuOIcDs1tS4X6nUNDU2\nfNyzzsyS7Fs6nTKsfTb13JGw+dOOt4lMUIBEU84U5RQKL+jrymEyKK/sSA4kuQYjQXLCHUIIG8G5\nHUgZ9GKsNo3ugw6mpQdnfJ5cW5I10H8JLWrMiCExw/s1EXPyeM59eTd7T9tDoN1rAZKPHG/JN8dV\nh0oYFXVBv9sIAGpOy1+yMXyrapdwkmnq9M75xOw+4tdRAWNlhGUgeer4qaGwM1AiZOh9ICdC5zLx\nBQ6+b4pwzgxHxvbCVYSY3J/6A1H2OWZ/DJsHbkCJzKyyIJI6c9Sj+iL7IWOEz3kPoTdwojbxnFjE\nFHyzNYqDISswQg6KXYsPWTEGpB/obQREvd+ABflTfjzhr3Tjftzcg8LURNmOgUQANWT1DWQSbC19\nmfeCmEA3Y+mKQXkzlCARoH1uXMPPUpVC1ipWTPqeH7TcwHjaNCNhXgDS/uk2Z5GBD8YiHzSvAuVf\nKZvULyg1j21LI/bSkfQ7+lk8ROtqWPv7/JtmfKo4EJbyI7aQPWjlTqdH9mV0ELtfD7EbTPEhwZZQ\nHGWfHrL778ObaVgVlJ+4cur5V5ysxaYVfZvWa3RzOCv0QqOo2lYVW6b1BV6cZPLYruo7o4VgOq4K\nzMz6Tv5RTu1X/Q0sXm1kmGF9b7w0Pc5x3QBxIGCO+NzcC9HZekrjxRIqqqG9SREDtovJy40tvW9B\nVLyL0e4LS6wq+BG21T5Tm3wStOhCHnyJAneG91iZNFnrTY57YkATwIja/JJiSnDtzisBcdOXsnE+\njF+WIPe/OXaP7EXFwWnvQcMy3CEeH0v9WQ8R0k7m5/5LJUSKZegVF2vImSnXZte3+N1jLmIspK2X\nLSW00mKB9e7X0tmoffFcNa5K91v5qCKZP+jH9FlXfo6FyNfnHZeBtYWE1rFrWkkNoyffdTydMxU3\nHsE7+QvtoAiGifQOxWPvyL6jtcKpDsPkZKwWMaDS6t6CrUW2+7FIzIySi4GPD+UtldMfOgfX/xY4\nRwOLpHM0qz77Vk7F8r5igDm3YdRUclJRj/9p3PhuaGURCCOfvYY/1YtGyn4pRScUV0eI5mWn2HkY\nPB1KwhTPUTGwVWu7Y3fD26njzSehEGb15soneI8/j2u57nBdio7e76zBGd1Ae28DCxlw6eheUL+t\nVfbb+l1BrerQeAHVxnm+duuLE+rNrPfp+17NGTOlB2Qf1rcFqQWYCmgEI+VzyOhWARntifEQ91cL\neG3JS8IW02lPLDfwgGnw1jdsBDrP490+YoZQxAo1kmK8lSjgUXuTchXZtHz6I8/mHaTDsZ3ZJQA3\nNXIjfP4KlMMnUOG5LiaeDZ03uItPx33c7XIlhC8wCHIeOQHEnRoS7Ah4f7M3FP3oommN4YQxreJR\n/uAHpkr0sCdoRVU3J+7N2vwSP685CNjrqyl78reB2aX7Ty3g0hVKTHlyPzRgA62N3Gfb9vMrk+W0\nY78yHpQHiYOQTwAsjZvyYBwT9f/ldXZVwC1YIvI20GQ7kL8uvhV/+zbXVzv6kyjHg6HZIY+D/+rY\n9JnqgDOXkANYZNab/6uv2j1ojjDqBOeZShxkJkbTwoWc1yT8OmnQVIXLmeGTpGuabFKI9Zi6Q/06\n+HPwkG5LawIar0MHYUs4lb8X9uKIVauJZHO3fCfDJpfE7p0weI+DMayYvriGCPSu2+0cO66waMD8\nkoQKpOmFxHOrio+PflCURVPrWAdtiOVWfTKpPdCUgyjcX/0SNGNc+GsKLpPgnseR5baF4rxbWWCj\nkZQJhVLuPemR09jsCHluA70+mz9AXQAg/pa7bfPbMldU69lewVO7xbwqdUDy4hdTZYJCwX9TNp1P\nNpCzdGsgoswj/88Cy3icvq+rPBdxfqogbUZXI0ZcBQuBSscM9RPagLxJRYfOWbvPYakgaarvMURQ\nUKkmvS7oHX3jyOH166f1V6kX7iU1FtSODnMP0RTIiVB1jMY8PPv20LD5653dtu8nhpW/yxdeaulB\n6HrUOModOutJHPogWpEpYquKf+DCjyztBIiWtsXp0rIdpdackzsWc3l3gZdiLtsV1BhLCsj0FJw2\nU26qRLCKKxk0axjYCW1xbCcNn2Ui03uJuYtzjrQJU/ng+M40qPAoIOoonXkN2va+Z/XjAlJvXRLl\npvwhi82zybVUV7GX+GBE0mShC/h7yvkzFiRrRDA/RwRQur+2okCdE6dK8hr1zzFE10JBP0d9TUS0\npK2XqZN2VJ/BQSHEd38SApjeg4BZNbFB4+Qm5v2hy9XGHVWFBr86STemwiPK/HTKyvHbsTG8gt94\n4Y361rCNBFPqISw38qIcz8ooUjFi622Y/CWCjDz21lLX3iFDIFf/ZxxqVSlJM1NoqsTHOTYaVwF7\nhlfj1vG0b3l+cGCZNArEGD9fxGx3Z8OwL7Bzs63ULFNDz9lM2zFr4UU6eL3vuRH3yJfuI3H4I77P\nffLuBWlPBg9kdeOw+bZrrzSRIRmKmYS6kOz3Uyn/i0ejd+TPM5dR+qHmiFt7OZjjSaf6pYIDxuFA\nDZ6PvZDVBcTDMavNkIcSkwsm+B0NwELE2BV7pbI7jpTpkuTQpZAIcuURtrHRXOohYiktQX0f2DId\nGDX2juPGYqAkqHn2O6TuzV+PKfUMTryW3TwkT2rIqBqzrGBtN1hU0JVrCaZAM1J928FQGECowe4C\nYw3phOU/wxWfcpsDd+JjsNmQP1GrNaLeCvX9iiM91ya+u8I0UPBSSpBhbDExnHRQ8x8L+Nxrv2P0\njVZpcPraT1DfqxmICYoVm6AY7rdTgJrjclMbYmafOsUk5wRRTQVAYPBpGcA93u8qLRqEvvDHhnS2\n9RKzGmNUV0hKqNIF4f426z0tJi0IkRW0znccZmt2d8TXKzYkCOfKAliSBqpZS7bodKplqMqc4voE\njaPXEf1vKkbUQOV5HqmvUiJPI5Y7jQrosCCg5VL2/oqN5DodmIqCCTd3vdAm/tt/b0IuI5mRfpP6\nV2Y/cRCrmE+MumRavYpcem+l50tCbeSbglB4grrAtBooNSiWou5vd+6WISoDxewgOeJQGew6HhaX\nO3eGe6KfJ6TaL3fiJuZF3hZ9XXqyDuGrb8nQoAt6dqqzzDpGo1JaPScwI3EIpud4EhFE1Qti5v5a\nV3Vl1+6/UJSBa8V/BrByhZyt7xmrFz+1Bgy6E+Z8DAH3rQXV6mKOieQAoUPkW2mh9tx9xnFpbSsZ\nTPYhbec2cj4bGLI5crXAxEScCC7qH6wD4Zgnd+qNl2NdDJqKJO+4hUlTbuc5wXXvarGBBhgjMHLs\nXGdXVwHOm+Cc8rKXJvr7+5PUUtnwD8gWKxJXPimyS72D9CW6d7dkhkbP7lFlaWAatkkLR5ARwFbx\nMZAF9W53PRE329iWi8zBjf2WDZBSN2Q0TcA10dOE5nbnbfeT01IkqmqARAkQh+nTwL9T3bR2A8Pf\ngmwCqBj1+5rRlYslJ8CZOrLDQgDuLDJ0EbX+JSDcQd6jEyne6hgAaoZs41ByP/8g/PE2alqR1kRZ\nTYhiSUk5FbaPSLijYoL5o1w7Zy0qqdH/p9GBtm4JO9CVzc6hI09H8Uk2lQbJPzvt9YSlv3v92sQz\n2TKxXXtBQ+mUlziFQ/8BYitiRqoE2cdR+mE5f1X1YvM49qIirMbEuumBGiHJqvkqNUZBHU0ZgVKg\nvobG6mF+vwwH28e3no4tQ7zOa/fDVprzZjLGnvdPUjym+XCgbrKyypqUWKJ4/T/4PjaanyzPvvXt\nRlcGp/nhqI4n2u93okHPDK6jV/5phIyTYsLiXu3CKgu+8IRYdXYOiIo/e1Y5WDTKYgQhmBVshF3g\np1hGuj0SPHrrAaGaEG0egjAyMEWxwFicIsMjvHDzms9wj7SGPo6CFt4YMfar870S3Mr4rqPPTLEl\nKaX83QSEnw2lHk1wIWIFRH/7JbyQRSmJQSWe1dyCNY3CJc9ckpBwv+ZE3JjOz/eE9hu5cxojJXoW\nlr5td8y7IAWzChiI0YLBwLJRGcSEKYwgbLcICqV6JillP9J4X92YlMW6BHoBsMhB1DOl6TyZgMNQ\nVlZGWfNoYelupoRkIT8M7MzXISDSzqoDIKM5mr9eoSAo8ib6YK3ODFN1Ipi0Hm+qUVh97Qb3LCXy\nJ6TLZ7yBPe3PyN9tI0DKKMQaEf7MIeR/pJVXBGsWw1J8lMeUKMZGj/PNQ8jCoeKR8IQWRQA+u08l\nvi2HhJO/OOKzrT7wWfTqQ8JQJWoego0wyxREKsmJVph5puuURbW1rqMZ59X/1NWVNk/LbJ1gpEhD\nRDB7m4Z37EdY60O5sOgWAgfgocCGN+qw4b+xKacYxMN4HjXO+wJq18wCTE6+j/Riq53L1N8BhQ8Y\nGzmRansnzeytnsaTfsvP369sjt22XF5RMpCRvIpwnBzhVtSbsoEOecovV9J60ihS9Fe3klm6gBY7\nO27ky2+Nqy6V5sFI8PXp8SBwkwq5pNi/BqYrHGV+KbX8d32v1RUYbRrV4F6ptibJnNz0aU+HQQBw\ns4RzTcJUIJhlCEM+J8xX7HwyaUGYXM4Vblpw6Pdu9uJT0tjyon29wMG41c5BLhYFL9bVxSB0rylA\no9dhCoNanyu2VfmWH0K1eh+YJaNXtEb0ysEmWhCOAN/BB005lvi/w2S97ehdtGEWfujIFXRsvCgY\n+RCIDAxVVZqHL8q746Y3NWuLClwgx1vHx1NcQUcDBNsRytgo9Gb0DigkKNt+dAAIGmfD2l8RTA00\ni2rxwGF3erRv9z6mzledqzEO17RKC31VFamUnhcuZiDRaRRCBnE8GuE5BHaK8rw79pL1YSIawfMd\nLK7hHkbaDI3kT4s0uTl+t99PyWMS/B/0yfBkHsKDGfriLreKrAncpEeUpJVFKdFGrPl1HIHS5ZEX\ns1gVTXjNJJrMestKVYaEs4nViCstGD9zSan6JhEmfaifIkJ7GLKw+NimA9uOzyKvxUxfRCCFUSvF\nMprZGCfJ4ltS0NYsdjAs1KQSH/5sn/PQ6OIeDHlZ/n3Of315bRk57pzLC1/aVqAi8XLsSRefF/uG\ng/x4R0AMUW0mo2mdnHH/TY/0iT8LYCmwQO5G/dkxHjhJRFJDZ3qUZid99q56MwmCVIj6WDNBu+KO\nQN6QM5N82dHzc1QI4OMalKCyGwtF1fJoK6eNGi3dVQTES3YoHYpJwy9mkxPa0rvrWLS6/4KyUv+I\nEDZZY6lbAg/ozYCu+01v8P5fYavZmOXKq7EICFKOmUroiCAKQb7RAGvnYqGcYPcJRAsDYdAoIFDU\nroKp2Ovcei4dqjC/IMmPpx2utomxn1moEPZkeviZ/h4Jw8M+YkT9VrkRWpAoADxDnDqVJm9CyRZ3\nZYi06cQ7Xi+nISoqnuU0wG4niseJcLPhRyK/eN25gKr33zC0KA1F90dGy8K2XjjGkAy166Fm+3nU\nL2M0OoqaJrHkmiE5GOorVEOvOcgQPi5mcLYVduX9edasttXX1GWuqS6e+TdcltrvITA2mCaGW9W3\nuLXjKkSpq982wMXZ6Lezt5GVq0xxPV/hocBpYZGNk1GnQrKh6TZ2oDCwL3BfXTqGPrO2BfEl6Gt4\n/y3kZDSf1MYEfz0iQOKOy+lWAlsnuPolMTRzT1cOGY/Xo5ZfvbKryDcTb6bhVTvO6/ytROqjAUmQ\nTHPlyl8CeG7hdq6DGm/TlWk+DtDGTXDeiF5IwFeBRsJPlaQ//IAkaAdtGnFztK5xLzNvyFs87v/9\njkbEu4pvPLRGn8alKJB8ZZ/E12VD5owB7dVz3WdKnfFS+ewUVFFKFM/LqRQIoLDfau36JyDEBIoK\nCc9QhI4knWpjgd3rc0Ror6hYufUfdIhZvbYz3935zgckWWECuvAIgdz5z2ckO8J2UHAmrLdWFxtz\n7NFYheF0uQVqIWu7hRMmfPVEgJNVslEfrtSENg19NvNy3vkke892kD/uoMfkVuyjAkS8PzGBrXJ7\nSQqI6VjMifzTsYMS/WQ+kXXwPhjx09QEncMmZSp0thPdg5CZk8eEvrZGprWuaWpDs9S3lN+NV/qh\nEaMcIGIuEMxbxMgD5WtZb20rxjLc674wYAzoVZKd1k0L9/5C0iSgJUwYBe49dyDOKYUMctmkESxi\nVd7eT/IqusXB5Q/PLFKKSpIjnafKrHv8yGyfnTaBC+kzTlVpb2G++mJNfwSbkDuqAvAoKjPAVHv+\nqzQVAKQ0+UOmw3T+29c4atCHzi2+uB2N0pr3kiOHQ8yooLRMdkn24q9cxynSkIZo1/dARHNNdxa3\nCJv1zraDIX2a9McxBdYXYYPeFRe//3X0Icj+fafoR1L6ZnzJ8pkqjZSGr7s9acLQGxabvRMGFAlH\nVSEB3Y7eWvxapneBKniIGGujM8MXaz15lv9RmTiEqxfRsxRhgthrhqNWOlGWfz21p8uZT/iV0h9Y\nfzfelebsnPN2uqnYGEKFTYTm43VLTKdViucgm0FyCsC5i7j0MIw20+J+3xPhA7x4++Bg0WIc2oa6\nyZWBWrw09oorWa4VXS9O4jd/qCs1lXQO9qyI4RaWmg1w/2nMaDgx3InEckVMCboMIeiaxntF0Oan\nPBiBdb1PPzTtsMmzVNpv4Fjv/cOEPRIRFPibNg3qhLCCRI7H9mgzfUzv90GEsJjMVTCAhWsuuHo9\nwGzpvadtd3ZPmPsOFa01NwPTRw0Ka+zQf07NZ5o1vtUsD8QeGQdLQQ/Q5OKw2HbA/bmpERHgtPaO\nU2pjfnadcng5L589GtL1Yn1o8CLSPo3GBOJXJ+EEsGHxmSytk2TceD72Fzn1at8SRZcjtsb4Puy5\nD6IOS7UeaGPeKQA6l11RgJHgfZbUgaJmK6tPYXZqXja2NBHNAlJGUGSUdtTyFwrSw1v9Kvbta3nm\n9dSQggcFLN0jfOh4Wx4PkZqrNAn4aYXAl1hVDrYSJYeIi/g9UWvt4lKEKzII7sSP+/Smvc+DQI7c\nKrUPoBrCwwSIULOWIvTrmc/9H9lyRuvvalVYoO1UJ4h1QZ8l8Awyua3XBfn+LhsE5y8En3VMKVBK\nHDDhGXOo1ly3kQ8NfiYxpwcHcNdNtrv6maO8YQ5GRGqef7AdwOaB88p4d8Lo4SDu62Dzf2fkdySN\nvx+zps0lGn2ew4IFCknQaUtUaHVrSDUG/NZZQabVDl4WAdblcpbCOW8uTiNoFIKFX8dP4RYXgq+N\n0wODhInglAFqObFfIC84RBfDlEA6t/45rPMvS12+uDunWBSZHyVY1Uwvwu/pnI48lV9m61OsJCLO\nOIgrpGewilIwhStXkjxdI/PB+Vez075WfTee96epvw8Gy7kPD7RFvqrDDIrSGm93FKnRHplTj8O5\n5uu+yfmzGBWYcqCbo4mJK6V0M/SJnB1HCGbgLiRxGy/WnHWjaYx9bBqMbBHImuGlpEzPmfDKvgV7\nAlHvpdpzcBlf2iAEr4jhpXqh/KwnRQ4vJL1P84YbChWf4s+IKE0AZ6f0vl7phKgUVq+P+ULvZdoT\nqnWO0Ig8FCSr/a6sZumTd2V59t1HdZTvc9V7LHv7XW1ar8fwPredD5AYEDMepb6AgFxec1FiOc3D\nykbfBhIXJE6n+Yn+BkBfyPaHQtr6CygbQYqPxrWvwqNaGqiR4M1+SnXc1ZPUCuO3jpsqErNCpGur\n86gev9iN95nwRZl1czxWVa9z2Vups+DUDYNl6OGsA3VaU6eY+zfjdw22WdfBTQW1yLZbKdfPdglM\nk0W3fK6xVQmWd7Q0MFJx12rohylS2M3jRt6ymRYDuj9G2x7e5COQAH4HvGSj1xQao0Oqt1esrJ4a\nYIqOffOvsSJq932yvAK//wpl7jU/meranK6kL+SFodAzXhE5O9i3yUroUaSX5y59xIfZoFg4NHP0\nM7zEBF6QB2GW8onP2jBMjRx1c2YyjCZC9I2gxLVNFMuAynr8b5R66ZPqvrh/8y6Mqr83orbrcV1X\njrDazLR6yHEOtNQ4bi8mN7w1RxzLuL2h058RZGlSsTBsO8xP6HAr5Kp2wBfbvI57lK6CxqUspCj8\neO92O5CNgGOfYdotXRnXfVffA4XKFtgvw2Me/hq6OXRjQJn4ru2BJA8kDP43xdNfLhkeKIZM3AoG\nTcMCW6giOWLiADsnkr2ofGgeUFbW+ngIOyctXvMwRFMD+1K5RpwKmd9uVYsHK5u+PLBnvBGoyoS7\n8/m4+m5zQh1ucW8F1QfRwl/sKSrRq0ciF10lQ6zYZB4lLAem6FOmUFaoyuBVPiQdDA1ZsbW/Oy9h\nCVMHPZwPrJ3UnrPvs6YOfXs2Jlfc4nyTMV9gez2SwA0MbPHMnpIcvsBYMqVf1NbZumEG5UI4mVji\nsP+Lo3Q+cV56vHImYilS916X7mZ0gHna6WTTGV9UyJ+Du3k0Tl5TlYLHL/ob4uKWbj822Gt7tv23\nAJnMLGCkgZQbYYRLwv5C7jFKxzPsaYrdBbnhN8Hzj8uWglOv5NmXOcg2pNyIv6Xp7o3P4/taZy/s\nbavizNn1qFu+wczAKyYeOCD1GOD150qXMwDfJGIaD722D5IfvLbBJkBz14/nzS42fO+i/NSflxqQ\nIh8W1dHgXZR1+1xGFhfpNgJ73eVqPltXA5/xNtE6EWKAK2h01+j9T0mPP+TCq80DejbANcjNu+ug\nQ7qp1/IN1oZBnRQf0DNejhOdZ3Ik88Xhwy2Bn0jLmvR81NTNbmVEoZf6/LBhkmC++d5tWUODaE3V\nMmjV73rV8eAB0kRkj3yGu5GLwWEtbau6TqRGb0BcVzUlzqvF5MPetFqKTBQY6sJENoTXq1XQjWm6\n9wH63KFczwcmFRWNgBpkvjQZUGWcCIlioS4fuoQg+RfiCszpQm6etlOglZq6tbo35s7iHLifH2fJ\nXgBvGhw1Mzh5WLkhF0SZtXs1flSvmLCyJM6MwWBe9Vg1rncHvsaqt33+9kknBEsl8yJuvLzpWHIq\nIOyjgBz9NEl5RNUhBXzOzvIRK9F3Z+fejM0uOy+z5JQfMyUHKAEhEtGivvnuKn5Iv1yGYQbKcWzf\nrLxAQP1WA+5zJeTLRbU+kco9GYRaVaIvruvNy1wYXHcRnwEui9exP//Ej02tNULykhUHv7P7iTnf\nYCwad9m+QexSnt0Sf+x7TTYZGucEUC7Y4EDC2m9MsTtXFuhHgin2e9eHMTm7cMiFUf3O8h8Qszop\nwzWvIQZOkkv91HzJT8h4L2b0+s0LMTK978OOGCGHEcqUPGyAWN7nOu16o2UjvQGFPn79rD1sub3W\nU+zCmNvAttFgu659SJhYDXnvhUoNWhfY6acclg3KD38v/SOAfl/eq+85NRYWvJtweiJRYYtk0vVs\nu6EitsHfSy055na+HIelCMTPbv3+3OwB8KNeJGveU0qxSv4okxF8YWWxztNlTRVWwx6fC7LrHTJS\nXhjvKRWBJrdBkAn903FdNO406+gwfbMP6VAaTCMo2gsunicIpS8xTA9jcMdcnCyP4GXLvQi4UckD\nQNgqbWYvw5fxTLOWyf1Qu4u6Ul1cRBRNRqZ3sZG1iD58EIMSS69VEvYM1w5CWdFFkYZesNsF2ZAC\n4RTSQLixyOWbPHcCckgl3/E4FZCkIi1A0xsbsyirad4r4OdBa4ELnPi0ASWPuCJZp8QxIx9ohBTU\ncXKA+rgTrCgCLzavqrmNtp3Gr4WW1sfls95t68GeO6SScz+13sR+D3gkP998Q+3+9ENk5i7fJ9/i\nQcLd8GqnDZaJ/h36F7+cUQZg67jcA5APE29UEhwTU72sbZWGcGykxoFo6Wu8gG9xLNC2pPVSdS6a\nF55fpU0b9k7eoRIM9wJyDoF5jVRrL+wNULRlvZpfiLOpSwjUKnZ6ljjKtTt6qfsye31ZSpQbTEDi\nei67gpANY9oE+l8zI+oIf8eBQod4TXK0aotrRsx0T048+WvCuIiR+iczHejTE8Pdi8+enWorNp6u\nCcR1yfG23NU1xEPqbMjQdnMIw2T7xx8WBpnaS+nBJ1gNENmT+JS56BNxD6xy5OvTLAQXjtm+KiG5\ncnsBBCY/Am/rByb+pNGepykPoma6lXmXc5FMpKsySFKxXx7y5zorfRE9gSbCmTG5Ltvw4142R91i\n812qH7JQQPaumVCKm33BGCVGuitsJfOfv/98p8oQPsV6SftmQusOjQSyn5Qm+dlpy2+VymZDEnTc\neJlGz99qQGTvq8/CnYHNoTodEyCv3uGGGoA0TqUo53dr7ssSRbAFgdsyRHMDxepGAcjkw7T6laTd\nqtTg6VF8hWTkI7MN6+pMfl4m1JUI3jCTvL3r/vgV6Kz3ppGiAoXiSzxy4keXJ6PAPwFmbGMVtZay\nWyEhiliGvUyzaYlZPptWWhQOtNFU7fxXPiYE32GVZIx+SiWJLnWydxbRC/WlhwgNYcGsyqSZMFit\nsNGCmXGtYx50tvzGxQwzehYg0nZ2T3/PJDCx29bJ47EO9lmaIUUPuHUmene0vI1Pu3WArggyDcZm\nv2T2/rnn/OkCTuK9/cnfLCkG9PZvw+b6Q8iqL81fUCaMHPspDM/w/iL0pGUM68CLdUwOhsuz9jrD\nADfcq+EHTkeSm1tRfg+5QtFa4PgsUd1tA9j3+oO8OS4wuERtXT8tItcS8PjZuyin4U0+G5ec8xRq\nNXig33Ho45rUFp/dzkeNN1A0r9jrBnzIxzHAQZgfdTuGWuttmgbHPe/8AhXQ1iFepoTAzqrCqBln\ndNdMPtSzeK2ZoMaHjCWqZs+s8/+1seQjregjKaPbNxtmkplWus0EExT+udkoO7IXvlQq7BgPYo4r\nRpjeAfQC8Li0QA1OIq++poHELmQg9Sv753ldrgUe7HlrntwA8pnVfa3P2xWCC5ti+tEdtMl2Z3R5\nahgZisYsB8c1LNpju99Cd5thHlHl4q8bD77qMmBldsN89OKNqPHdYrbQUxFuR0cSUly501EUip2r\nJwNftGERUEMKhO82u2cZQzDhz17Ttkor/7NeO+Z+DrmO2e4BlNdtNXxiWIprq5n7njgKw0+Y31Z9\no5bBl4zCMvNHlQ/IuBUEEIcDEP1SH8hlHzzCrOoA3/6P17v4Px9APMiiv33ExsXH8T1i0iteJS07\nzLASBPvauUC9xNjitpan8V2eHxBVPDkLlNHX8+hobBnp5vRMSQcBO0JFm33M2lSRBE9ZNcgYf+g3\nkB2CVDaFyDLLvhVdXW034NGCc2deKjNDfZrSkVEFJH0aDJoEYzxeEnMh9d5rIKx3VYmcYHgw6JGg\nJBhUkNHmCjfh0vCo+hjMCPwH95m3vUFe1wKhOoXsIWyk1QJ+QTR9t+hZTowkYlQprcv5t2gWHJYG\nys6npKLa+KanvsrGVrXB32uysIZliELY0rvCu1lnLfOVG5o6VxHS66qJPHimhiy6XX4IgXd6zZiW\nYO7BOZluVxA1fF+ajFTsjY32A70kD/tRSPQpYwH9EMaoF76kkDLhsIobb2kYNomgtk7M503onnCd\nu64Y7Grs+FvIkcG6rJ/SZUqfoPbCZmvMJtxhS3d9eDphfgzSyg0uEcbc30Scvx3MW/Ka45FcPqWU\nTTJuaFa5sYSLgrtp0/xa2z1ZrvplfUMOfs1Ir4WbJ9S9rWOTG+MOlyxRJVANozxhNnL+p0UxBvIK\nFUnFSYxOeTffvL/9AiuwYKEGlG8TP4W0kgfeL3hMAL5gpcXggAW/2zDLba/syJhMD6Tp62ZpzZTH\nz/IPQv4NIEnBLbQy6BH4d0wGaSLfPyXvaUjY7YQ+ntuC31nihw1bQwaZ+MUWyZRcmiX5r9u7+XdL\nI1L1yZBLfdvFM+nIfXra/bYYxC99jIKFf7pNPlxoLNMW5ArXRg/FY+4oEjkoCU5VQUgZUNAuJNxU\nkjCdWYT/MrC1tV8BTjT8vgZqsUVG+9Q9BiJFhhAhyxYKch4SAtURNyGrLtp0SSnIYJ3B/ZVjzn7I\nxuxZZ2v2AflGdJfcDL+Rr6aLQdbjGj/+0zoSVfLZv4JbXBQwhr85A0tkeg6cGcxR9Vza/zc7+M6g\nJ5ccWZqPWubJGmJvKwm8cnMa+pcVTxa27WsCDyvS0Y68jalHosyqevLvcB3xDPTsn2uHlV+VpQcj\nV0VFxSXFpQmg8i91a+zS4L7xHHbrjcRUly+muThjtgw6ig/wF5IxtSpj5x7igdPnhA36Go4s6ycI\nIiK57NlcBNfiebdpAbi/w5sM+taV1uXqviHauEuFjtQA33Ok8ch86BdmtrhnfMrEJ8rHapBXrVht\nIdcFv0tQUfg2nx+8xWmAW0dbKjOV9EeqQp0I4g9LeZD5GoAP9n3P9uxbxza4GAUXxvg8YQn638cD\npJ08vWFIXQz+R7QyyTo9sX+L/8OhlUe57VaGzoGGHeg2RfhPUXKQ5g4vkHkUQq05nbCCuLIsc/NF\nA9VSgYsetAZd8ab3oI/3nSeVQn9BqI6eeK76MN9q/uGinlJrJwDKg2lAwE4Sx1NtxZUDL5Qng1z2\n+lwVJzNItzXwfBtFu0TCpNDRouYbIY10OgzqrgN8p1Iw4yC4fdfmvvoeJBaWzueEUdTT0lR9CbXg\nnCIcYnStmgLfad7bKNKuZF0N2BdtTyt02DP4LzxwMUX9zaxXo2s/7FBfFcU3FJuvYBvJNxclo8rd\nK99uOpDhoAF68Cp8f3U1xGQs9hcQFsIiZxeJK3ILBP5gp+CyPPneqHwgN07Z3h+9wvOFgwV7PuNs\nihcq9INZE5hivSIUv1J4uqxZxw2YOvj+4XtgILMDsLBUh2/CeiJHDnRXHHXa8xyHN/VEZlvP995w\nphboRlruPD5mR/ocPYK7UdxRiSWJM3aJzUcLRi955umxUm0bw6N0pSJ7JahT+I2XC34PwpktoFJK\ncnszLXBWbxz29fPMUkVIgrJLImaca+mZQRabAzDdtkZVBJfpiL95/WLyAlyEFqHx6pOn9YdqK/x8\nls+aAzMGETkfnoOlM6je/dTzj3l6Qegyttg6hacm7+dwNcr5RLP10+lmLI47KpEZMRH0JtDps/ey\nRtCY/uN6O1UaJdOhdtyZCpou6ZZrao39nAAK3hsYPS++aZgjVAM+j0HZPfDxzqTE4Wp2AHE0vEVb\nsbWOC5JkhFUEsNgxf3CZZek4tylhZBFe2qAPmca7Nr8cX+/fGwJa4zsstW1RSHzzXp+ga7T04RRj\nqKwX8lhMp83DKrFARIncMkCPhC9OchoFv6Gq/qOjB5ENUspxDy4S/IOsNdRpKsjsoA/E6+aiSeQp\n3DWa071ADqC3V/jEDFQxKj++OP+/pINq6Y1craLIugETiEcpuMZtIfeNmTtUQ9bQlnnIHSMgiiLk\nEYO/fwfSTz7trn+YBvKL5vAPEgd8EXnJTQmYglGi3iPtfYZCecyOfq3JykNYoLGzlc8l+lgHht6D\njBryf+zujUdATobQ6vmyUQSCtmPgv044olqWdpLhzoc9ASuMzv1Tf60b+vX3nQLZbSJuYh7SHxUc\nGxaQJbaAUNbtxB873Z2xQaexfwD0XIgmIrV4nTsGA8CKeZGD44WmVGfF2zAEj0Suw90pvxZ6ak52\npnNXRoiYA1GbUbaAPifn9es5nNMox1WMhiiFqkfTt6QT/LPDaI6pctEEKbhZABvzuC+AFV6ApkFQ\n9sEbC67oJqc2L/F5+EIi5bC2E4TuVw5PGllkgLBAmBS9ZJXLt8W/7AZzh2zXOiztarPYrGxcQWQi\n1NqD9kbqMfjq4GgxdfOh6GXp+/8hzguNrB0XOLT57jqu3ukdyPI/38f/tdSR8rVLm9ctklpFxIp1\natcGe6ZzLhkmrAWaEgXu+rkvalDeJJzYMCdssUggP9sbyIBqNm+bu0hs27axwtzO0aLTdEmRy7BX\n02mW+0eM4axPDPBXp7Km1zDETT9OuwhMcrmk9IDiDrbaUj5u9Is6RN5ZNoT9chv4XZJKvLR2ut3e\nQGCvbdUAVHxPLCOslYfGfXiNFdwL9ygx5Xv94ULNBynBX65Yc0v5uokgRUlQFr4KxsdMcxhnJrjd\n5mKOOdcKDyXcYKKk1YrFmxp2Mqa1iRK0gm7BoGrH6dy8ZY4obArr8X7BYzzkf4oUx8I+5e2BLyig\nSCmP33zMkZFpk/Auh1rgfxz/PbMciaPSHZvrsiCsT3mIopE+JgltnrrCcjK7GAdB5hrTS3w3SR1y\nGBavVYxjiEqnr8WlVGP5HbH08fIsOBlMX7LO5sciII0cGlRpn364mCbdp91BslmVrQoxcPaj+TC9\nO0MZi9C8aOZsUVk7GGBEye2EQ6zuEpA0PE6X2sUd4HqfaTrtQg1EivraNouAMLztKnLgN7pU/ETf\nK4iMYGGJzip/SjpXL4XIr62c0IMMYJzIXHBaTyrZ4idSxkM6S6Q/VUPOjO00HKdaRqOIH4Fl7siD\nQGdPpuIRj0b31W/7wIswcFZmCuzoZQGgj7b7P4nLZ1ugw4MHnHQ0p0zWM+A+R01iDJDTBdfEPSsz\ntVdGAoTuJ+O5nYpHMc+IAOA29tvUF0hLHKvwz719ElO2436olcY+xVc88CWad1ptcp6aodqcFyUM\nOlHeSnAgLnQRB4lEfJKprHEnN1TrjL67oHO/cABupwcFGBhTJebJn1u/nizRAVf+CKSUryUX1plf\nq1Wg9A52pO4nv4UPs5j2/i4PgDiSZY8dZu2YgE043PYJ5dEjNrmyvjaWkjFwtziqqKJ/zAwzxSfY\nFx5VOVen0XsXcoLpFHKH06Nbml4lnpDAxCdCAQlBhJagIUqVZUEIMzzBgaOUj7Y0E/Sx/MU06AAm\nb+hjKhJ4ht+9FDe3q31ngEpHms3C2CB73sGjLP85VrkgocaNNOGwWb85+dtp6SbR1oOXKGSgDIuW\nWa9nFDdb80zA/9MYuiTLZB0pGf2ysznBH4gVaJ86M27pJbE/oidnAlTQUPvFB38TOYQNTSnCNbmC\nBY/7Vz2hDC+A4DHGgWSJ/wWGblIidbsZpgHg1Xo8ekbgWacICP4eJRnFY0h99QUPrb9rr7nSKoVD\n4fgt/CUrqX9nvnFnEEI8eiWD+oHVrQKGRK6TnOP/839TpPTKpwfa5Qlp8j3ABCliKMAkPP6HOX+K\ndwjGgNzWtsIMFH+5fIx94smDLYyUxaUiQLsy44s+y54eVCf5XtKV7oMkEfvPoBAXlmhHKys2EraD\nKquLZQqsoRYc87pUW7KZ+/FGw76fQKeccRJfucdYfj2hHBcIaBuJUIPKrC592N7/WwEBhSd8nLa1\nLZKRMwzDGxXGYlmDMwf56Zf6OgqrCqSI/SnvV5mzligO5Au0AT5y8UGRR9x2hTLAohR3HhVudEXO\nowk0UJg8YDcoxxu0VpwoNbMLIcaEY1pemBsAdLqJhGMTRnneNxKrTtSgUwFN30HpP1fHg8FLhkHd\nFEhXXm6zT2mMHNhNgq8nbsHlIZj6lPdOCqJht4xkSQhmq+b4kwFjsVIOsR+y6Mo+C1vtZM89MyCi\n6SWt8fabXIQhJg+XGRqdh6vVWl5/YYso5T332zDvVQTlJAIu30bYPbZTre/xqhs/eG5/01Gy6nQd\nsONvdiK5TjgFj1gAUliaaUHi3VsgkrNExifz+rXAoecbj8lpEh36t3rEyvXjjGsAl6nV1UgQiCOU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mjmT3stzC/Xv3U+2KUtVN3IyoZysXfApjzYPxRGoY14wxVxml3cjWkid8wTZt/\nqKiZ8+DNGhOWsKqtYFfzvK3ApRuFrMQI4nmfP0ioaEsTGAw0TGjMc/edUC/KrxwpP9WbWlpcR1Mn\nyRmHmO1G980fLf1P/q5GKog5mVjHFI3YGEOry1qcHAJR2dzO40KJ0/5N3/Pxa7i6wNIJh/mHzFZ+\n31kRMiX98q/i5AnwSm6CIHRH2WptfuJJu8bOdHyEc2X/ZykVW5x17fso5tTlUjx5p+HR96FFUaBH\nlCZQUHaHREVDgLoo37xNLUuVkMHZqp9r/Bd63iatA1vtI53HEnJpU6AsMLIsCdkY+Lf82Feavy1/\nXEAxqjo7H1QoA9YuFHqbS5WP7hI7NfNQMDjoqprgcz9/UB7xC5WYr8rq2d5mgeAbnstt5tE7sQm6\nQgLlHockY4CJK8Xvmv4d4SblYXDAds1reKTgyhuI4ZtI4IEsIdiA6/FCJ2Vtw+GFFB0zIWutZ9Qg\nvRS3DxbGOPG7mDhBr7DndSkrx0aocMGbybimWSBSg54OO8poGqinGYfYKzIcnpmV8De9rNUYTd70\nICpozYFwIfHD6uW/tcf8vX5K9TD61i5pXIBimaenR5BI2PMYIhZxYqmWN5m2C4lpq7eUVSFU6cJU\nDopA56H0YzS1Yghkaz6ccapw4+IWSfmbW+U+xxGGT3wNd/C0LkyFKJzdCEZLxeZWC2Om6YAKNHn+\niFQ0gxa5wWQPwuJ8ZhYyqSk/q1Ta/GqqRzNbWLlZC4xztgz3JY1yx0g4gGXDKlO705YMD2H1sVzh\ny8FE+koC6h6l4i41cL/DFsmJm5Jqj52bd3iigktOLK6QtleXtA6WLojTYOnJOguFYPtthxaSvmGm\nqQTuLmCdlOWgPxQizNJRMRBTiuN87BktKycizvXRwigxNRv5V2btiXkJPtyPyqkLA4WN6rCMZBko\niXN3m7e9ovTge7aNZ42IWrAY75oe3jrfzduFMjJB7BHwVaV1dNpZqNe+ZP4gzGhO6yKU6gUhhLjo\nhuML+408orbEV4f3IS8O1PfQ+c9afO72/Ivqt12Iq1YNG3EKdwt+NulV+j6oevJWc1U/vV8MrQa0\nbeVkn5LMWMAilgmbX61R6wISQo0NfBGdFL7yL76BwJ5wauMZ3beZYu5smvlVxpEwVhQ8fFxH5Xpo\noihRZCSnp0L/BG8e+f6/sZJ3g939OWCjOd7v+b1g7lOXhRH12gLTb/5yvbYNu6R73tarKDzA+EDC\nV6Cjc0uuB1aWJB/N+OrNOcVXKhZcotiTMF4vDqfRNuqt4Lr8gjOQdRbrQEveoS5Z3dGPAUi07lqg\nqVZaKQNTSVTGNdFooKDV6jxrbpDI7VfHYQeRlcfaGQ1FG1NFjzlHBtwZAFGM65hXUyuLRvTsfmyJ\nKoaS6UFC1MuuQS/l45/VFm1tfQmlNWunhV0kpPrB8jg4HzKBk9f2BfqoHchtOGcUKTenprkzbPfn\nw4lemz9G4I8Lj5ly28uFVHheaCmKS4+8HGNam+xtZvyfd5dpBY8AcoNMtHr6i4UmfWaURIdijXdH\n4Bmll6uW4Pbk+DGTBh4mPSh2on/JXHVKOI+tXmcYauiEje985N91S+0Na3tbw+coqe0WLnAcRjrm\nq0HRhBFaPvHkoNwuQKN20uBjwavtz72na95RG+VD89klPSBmoG9U09U91P6sJ18GtlDxXCP0UAvS\nYwS5AWhwvu1ZBenlPuvRWL5SCxKd60mnVbKgePL10ztCgNJWKHL/tYG5erl6R7VpWRMeuAsivG4L\nvlZh1VMUk7WcEFtlQ8ewoghZgp/iUiIGdB8UYFsMC2n0jF2KlbD0qxkuacheyV42MhjTNrWOGJpP\nb8cLqovTnWaUaEQR4ox7qhg+i7lW7pFMSIP9k6dZSVrywanuiKxyZEM8txnRmifM5BWdVlFe7o4Q\n6LDdZw4TPzfPC/79pncGr4kcfXBeItIkCz2Kb37YPXMbPvCbBJ3buirX4xlN4U9Fzi5U0OI8rI/m\nxEaubhXYIo1C1wVEbMmhjjAYqm9mdtqwtK34nKt6UA8yzfBAKUcRS9C7ComgLKAnsqqYmQ6+d9du\nQEqBOA+dGyP5ei6S8XQuTmoeHBEzJtkaDcSReujBlwUYKT5jEDk0nET2T3W05RN8O+I1iuCL2zEk\nCBa9XojaCW7WnyD9fHIfIlVP3k5fyrMDshYPSJRoF+L3za8tcsFxoTB29Q6BjKAxZ/R2U7piuOIo\n3MRAXcIwBS55HqoJGM2SsAP+FtMEdbi9rvWNynjnYLT3VWrn9y4dpa1PzuBknAAIADZ1iJy8w45l\nKMoZndthreWqtx5WJ/NDeCbjKlRUXo+VcTOw5wfPGjtROIJrk+a0pBEvk9IgkLPXS67zcTg3SmX6\nqQGKLp8Q4wEM9wWWnL2h6O0wifvd8KNCNPziDdUS1b31LePR/mZo4s8QhVTskrjHFAb4QUbPl7a6\nHLudISZ7yV3Gmp6lxCIVCJYIiPkLiVfwQRSQViwIUWt6BCc960d/MqoOz0fwpsTkdjYr+EqA4FGJ\nwxJLPlTgl2lMVKdWumgkU6nREoX2fmCnx53Jl2LcDzdxTiKv4g72G/QzytkzP/3csANiNniXJKyb\nyPEYM+lewTjlwyBrvA1Hseq0rwEyuZIohPauQrtMD/CqgPghUCPc1zEUWqtbD7Cs6Wa9Q6i9cZe6\noygam6u4DqOHve4zENyA4vn6BeFcxUULrbhaf00LyIK8JhVfO3PgfxROzcPGkUTDn9lNMcgSYFw1\nF5h0O+k4KTZAuh5WmzhA07pUadrHIEWS84zpb597LkMmlP/Ir2b5DSd3a9WrRzXtffoW6wj+dqC7\npakKeVaDaFLsKew4NQn/5Gv2SSsl4XFUnLgN38g3e2L47gMZVmWlB+Y2pxNwsAyXV5zrfZ66+6NO\n/atnQFy39BdJa/QlM1kXvILZzqUOXKGZVYZLaTWJEug9PUV3sxznlaY+cyInU/Zyp4GnlbQ0XVJM\njjTgTXNLU2xwchHYZ2fBegrJgvIFGdryBZ0iiPdHvP0oKTrobiiLLzbV6OGhFV17NAM1UtiiGvmX\nCecPeJZhMWSNd1sR0zXBMsmK0TzQz9wCoe+6xVsyVVjA7V2FOPwHS/UUbVQY48xEuz3BqvoRTDza\n/Upe/JHbXSk9IhwLJhuQT51Ra6cPMWmXfgxXBAUVwMzzMx5nf38uLxEbI8HuxHJNoAr5GGRdDbDM\nvIaZdGD58IBnjKY6oHp0HRYu4WKaLDRblLUdGdvRRYTa8gDWhSNjXPohCsckVTdJP+6e2e4QOj4j\nERJFaK63X5h0QsmZOgpBr0rJwPTHnVY6GB3YKBw354eubQ9K7LofK66j6q3zT4Guf8RJUbdEAwPX\nO76Nk2K/YZetp9kO7l+c5cAIr8TwXPfl9w6+CZ8CwysJcd4GCwCkfBAE6qXqEVKayXnkzL+/gi9q\nYhodZUcg9N6TE/MQblA4jb3J2ttB1IdT6RQqaipYfiglppdRbRW1Qij7hpryOT2LWAgda1QDnOCw\nN/aRmOHe3cYkOP7spl87Ts3hk7E2Ax/UCeVxagIHpfy+FrsHZ4qiX+k649T/cfEl5rBbvmxA/xiL\nCwG9iyKqxglcf46ESxutKiDbBbgTxm51oe53JUdUJ80WTQ9/VQIlCKHVZPeWam1by0CZhhQ+FHPz\niRM7iAkCLl0ad6jbmsTBDB4Yo3j9GzlRn4OwfvkX+1X6Br/jpb7Ods5R9sYdCU8iirwHrrDeyl4P\n5Oa3TjRfEeRc/j9P7DyMx3ksTLodItG9x/vZWgOy4iFOa215lI7+X25rZS1Ummp/5i+Xpg/2bqL1\nYc6h7fbQjdpHUXjn4QUz0LYvmc+BNdDxx7TgSkeXOeHhdOTNPZBaDLDk2cy+lw8H7HLME+RVBt1k\nsXgcUBHjvvnpcteXo3EY/4mNbR/ZqLeXimXlWhSbjhCGYDzmqa5rgtz3n/CYymQhxCskPAQGw+sz\nezc1Bd1Gs8eiRp5AYUfgRpr4jbtwjt6z++6Vu8p97biVpBs1ExN2/VFrFqgpOJw9uA6QDmVZnx8t\ntsVnG09ksxL5q7LXryPT74zfhepy7+7aTH5YUpDpb2waeTIFvBdg8gmxXZB2ZJNSvEFEPglZ4KhP\ns5Wo15NcuLVfQySWiiEeFOZVqadoOuNZDghUEifrUf+33tFg6SeVx+zBDJbH89YDSGPONwYA8KZ1\nllfpAVGLBseobFKvocGgdqQf5YsUQQL2aNanPQqWDHJHr30u4IJBVKuluk8tjx90eD5z0fjoCqq3\nJds3DQnYjrQ7BU2xCixiaN26VICrnw47sIinfFcVXPidugt7ZC/KdJ/aQIVQbkrgDLjDxprUS7W1\nFffseESv5PsMOXQPCsFvlKPUCAAM4JKznpl/d5fx73jhcyMXizSXCoL3+8p/2BFB2u1ZYbisTH6V\nHLzAnIYsfS7eDvpwedtN7UZnmo/srjqJdMDTnCXrvGjHEr7252l6Ipuygr6C+WLPMQU9rrfvIwyN\n7t6vCh04Uqaszzc5CY9Aglhmwt/2Y5fx9JkGZumJynrdGXP33p2621iPJ4AevXZ3fdpNsCsmXnzc\n03cELWhMybwOw1YYoFbfYaz0s7PGleQIeLnk/884jAZTBzjHWSoLCwehSZqGTEAap+F/qiwHr9if\nuKfdQfIf1sOFlHlFnmEytGa24c0rloKQYqZPkuEVY7dS+SDs3W/Bcfs8x0goY2jaXFj4ZMP5UuTc\nyYDHI66HFcvlFknDksj2QlDgRfqZvhK4nKn/ov1YLKpHRhjo71lyHjJm2VbSQ+0OKQv8nqczLIpC\n2mynrP+VJILPijymLq5vCPGo6QllgLdqvuNKBIsJJrlMhIMyMmnRNJvVS+sTiwwsxinybxQicOf4\n34R6e7oY72ItEWWzrwJMtmMMcQrNBoRVgZsDnDu3B/iLN9B445+Ia/2xI8tg4h4bWVtfUrPF/GHF\nCCMcBaai/7iqersKU25P9YqCrW5gzK4yd6hHRVmP/GReTSC8etOcS/dQ+iH7YAw6g+VqwGCE9NNq\nrDHzSFNHzcuTFPuPTnjdDyBuk8tgZ2P8L+upWmAB8WRT08N0FYWxRVHTgdWwIb++kpR4oah3SMVh\ncMdDNeDMRXWOPYx+eoBFG4TdDky/+Rpt3Y3t+kXs5rBtuM3mN6lO/N62N0YIWBy9PPROt6ABLhjn\nkTSPxHFYPlq+2tW7Yq6PpB3gOJgIpw6Jd2FVY/nnHFVGLeti1SuPxoqA/zB+RqAZ1ugF1/HuD/no\nlOzP6btVSLptufMfKGXQlqJurAbPNswzU1SgOzKKgJWsBc8A1dZhUmmODZr7QJWHHjXRe7yJioTB\nSe+1t1P79UExlkY2Av53wBpm/Qf4fP4wQc1SW3DW0IMbQtjt9uv9/X9fGV6/G4GCcNq3idyucymc\n5DsqZ30iU7nUPo5TDk2xTfYTo5J6KDFbWg68PBTUjc9YU+xUqFwxcpfCVXhHxosuzfUSnP6d8DrK\n3sQNP4khBnas9LtuKIEewVH1iv2IiKUdT79XbsL/vFcNBq0+Sqvvg8Mk/IozOebCZTqLA+pRh8j1\nPO0dg1EYBx38k9kKMWWaaucDeaXpyGKEurCt+rNNj6O3iZ4CRZX9o1/noytgel7upuLBzZqGwGps\n73AtMGLpnD77WEcHmk7vCb/9ZIQ/1JqILIS7tWQrpz13TnS0vYnHyN54RndRSVrH3tV5/OmRT8Vr\n86wb6pLSlRI3+LytODQtXr5Pjm9zRxy6ohZ3KULiJ++p02B77O1XtFtNs3jRNxHwmT1DpOf+e3YF\n7zwucJ1nuZyIc7dAzGodikj09oxWDfGZLpGvUv8slbHALDP09Q1sZYzbZb1WMxARlYmMMbOMv6bp\nqXEGb6OxN9Z+GzBYi3Txjse2FDv2HMAimBoCXDRXlk+yVpwUiCn5LTOOrLgekPXApsjOz7wN1iAF\nuPCOno030qg47WpIfuuAkwTBNanyjM9t9kGvHBUbYvNGJkbeRm8WiEhVGVnfSDbFg1e8sBlL0Lu3\naMpK5PBpegs+vk8K2IkOGYvR5Aow1ZeA5q1rcMpEdIMR3mvYVfmtKdsviHZ0E9byAXZKlxdLV500\nemm5GQ0btI6qUDeat0/afCtAal+KQNfrpHPt/BKEshvW65onuKtkGdVhgINJh2YjRt6jDRwNZQy0\nt2/zk33lRdcQQQ8LBhOyDN4ulcQycDTY8OirqCVBDoNZ+9yHallJ2KKSJ36/U8NF0hahr7y5qtSM\nA/CkX1Sq/WW9AUQghL6/flbo6xyPz6Bk2CrrAkVR1m8WMsMYMTJzDzfobDkq/uOLuUcYSHS8GNM6\nIdJqSHQHu56KgPK0O/DnWxNXJkyeBTmFrEEAeToW3FoLlXfLwtvWmC06ciSqRnbm4gQimtKLA186\n3MaT356eSiGNv5qN+OQ8jv9hOKg17JmP9W2QWQxotOSiN3CpHK96mnBgBkpBqeksHSwkZ0Ym0Qlr\nWv4lGLAVFUI/rN/rGeRGjup/z4iwy542LcR9kEYZOCDY7F+46FcaQVcgrEM3BbZM1pZ7vMLZbBAB\nNIp2+fxvCHdPb2MYCkQJEi/lNoxzKSXQtUF/XliVdGDd/gJwms8Xkb0HYbyyJaWmfe/7DA0SWmmI\n5fHk2ePB/BvngIkwjKN6KMMHlozyCxLMBeUviR479mhHY3qV5gjKRE18cK3t6WtqD1l/r8fKmf2w\nmzxkLYc44rJqGUZqz2o47L0QXKUl4KpIGJ/PgoMPvA1kf0RdRqeBduHyjVFsKxHnVpN5TcWOPpEw\nsnzFSf8uh2B3xmR8tN3FtBy76kvQdN+6jOgMRDMtqYF7sGVg9vWPkeNNYzWk3rNC82l1Zzzx1ztQ\nJPblX9T7Eopb8dQclIpQtlVlyIvKm//abXhCgGVhBiQO4HX0Mien3FDZ990Z+ACbN0ccUL4Q1a8i\nxBtv+PWgZCeEA7utiTzOAPee3+34gAm6naicmXjXFCr2YvuZ5nD8J4hTINSaASRF8YaSrvYywwTy\n0iiBeMiahZnjX6Ra2SrDx7v34srF6/hoMCA8DyH1mFmdEUrCRgE4t6Hi1YVAINEphDeCGVVAVZ2N\nPykajTZihGf35IIRqjlR4U376Y0tBRNDAGp0Q6kPtvejvKlrZKN4G7r1lJAyP09bE7KDPRmbs/fs\nNyVC8RFydYUivRE6veitQTKDOMDm6JNj7qAaWp77cujnVGbn64Bd4xm7WZeKIKIm4aYSnUwJl5hL\nD+LcQnpAu6AAfc5YHgN5y5HYw1yEUhRnMl/L5Bjz/LberH5kV5CAMGc35Dn5CCsgW62MH0Klur3t\nqvDQ3OvhGmDL4Y2xOoW4kBC/Rjs4GjGtRYrXT4e2tlpknnpaKlAKV1YKawJ0W5ajt598+Y5C55Xi\nFrK/U1x+yGGVlKNimaW2agOl9VuEcCh6glCflnLynYngd4XXKA2JKIVNlRW01Xgdtfi10B5ipXZS\nZVEoJ/hncNBjVQcHqAeGhnptqMCqfg7CcyShKr61kfcsAc5VLbEphtId0rpP5V0qOrtNJAKxoEaN\n0ppVGEAI9TOF73jTYNy5e79+kav+WYHx6AgbaL192QJxAqG6252UlyKD+TN3wBZoObX12Adr3vX0\nj8zGgO0he4Dx9Cc1zYRKQf+J+yMSyWdmVEp+MKCbgyK6LEYoIp17fcKhZNmAg+ZS36UfkshviFTK\n+POKT3AT1fvcHL8OYw/QdRPMaLWPsOWPzcq4yVgeUMUgiaSnDUCDUB2yCO1vrkhPMwKhlhn0LwuZ\nwfM3h+czZAHuZRighzjAJUXwkEsN1Pgt9F4Ga9v4FpSBRve37ucHHuEn5jrX7b93oBywaPyG4za/\nsKerqFfobeFqou+l5uZHAWu9PB7G/36xCuN+gmjhdwI/5TjKnJGVa/Y4mrJHsK6xloq5ez4C0iUi\nDmzKDqJoGdws5uiPusdI5CZWqgii+tJ8UWOIJHe9wGCyFsM8DcbrnffJ/viThaJpSCiPR0zFv6En\nui3LW356UdHeYjk/6ZLmILb75WrZlIL0kBuk74qo9+iFxkDdId6A9FExjyh5C0dP0BDu7B53lknF\nihlFcZBGxzYFi0FbzdfCEM2K3tcVp8899GthOJgGu1N/qgTjg7ZC/hyW+NBVWOcsA/YI7H3p0zgC\nXErEvovgf4PesV8V5YrcnbNOLDkF2F+Hf+2W32/JFOuPVvcNZ0gw633lx0jeGk6zfpU4S+UqC6Z5\nlv2D7EYFebe8OBLKCmRA2kE6MXcrMBmFn7B6+0q/HxIcCLbSLBhEYooIbwK4lBvBHwt3ZNID9S46\nrlt9jHIYAJJLaDmqvniX1DClRh9zTvsHpSGG3mOKpwD1pbAsE/8AMN715F7VM9sLDloqgirm14c6\n6KaiDL34h1u3UPQcAYa/iUBBFD/omsncOZqodQoWJn1t78iJvCBlDiE/KRD+shi7MBiWR2qJzUV6\nvszTfqHmcpXqEKqJvAXBiNAYngR+GmMYIbTgB1YEwXQCZD0LToUOiwp5anTrAhDmS/ZUfyPA3O6e\nTeDJzu+g6CkNKGT6qnI9zSYRkn59rzdWimTbmd31+E9sE3oldZ7yukJKGm9HcrjmEn5iIHN2ksfy\n/bkuKAzgYebyoHDYTZZ4VZqRJkKaocRo0fbIi3zd65Gp3s5K7YmVN1cvTb30eNMvckNTr5tRJMXB\nQ1bruBwB0ntnrr5x/IGxj/XRZ7/oSwIkJdyNApk2te/birUbUR6UnGc4y4ttNTCDEuqggW3Cbfx9\n9tQdOjLwh43tPYA8H/M++ZwOf3HhfJjQQKysv0lOWY4S7ARJ3OrEoqKqyXAWdXniajcpDVbynsa8\nNsjwPf5WL5HPa+3iczXjARgydFiLFoxXOvEHjL7tJu91ngVLoHuKCc1sVCOdlfYThGi23uWH7vJ0\nYOLKmVWobVhcf5VpB8+yu1Am0dOHkBdHCr3rrgZdInlMue8oop0PLaPmJVMowyGjsverdCv6z6UE\nOqIUWtaPVpiBpHHD9Yw6XYxDCAiGibe+Gl6m/28e8Ym+QSzsogPaSQBf0SelV7KrqzHbId7aPJEq\ngRCDJzmPbD1Avv3QgG3iKsbrPI2KxWvxVP0dALSOEGlaW1luiCFhyVQZMjhvB2qkJbqeiTDhS7h7\n3EUa4i+fV/sjeR56deRJoqqk3M2q5B2q8M8jiW3dXI4Bxnmf1g7J8vrQ+iXPrLgC2JkSbeRZ/eFF\nCnM7HWHG7fLPw+dEcoxCvhyjiLG4nrEVGBWGXhUmx7lCGjGBUwRSXgUKYTNM+tVB/GGQSLqO1BXa\nqonr6lyJ9aQG7gc66GT96wZBQGclYbR4btuwY1dBNSMp+euELOd1xEiLYTm8oFfu+4GyZNtxGaNH\nQPGRCGjL34JDEnum18YLX1sqaLAaI4Vd3oohNrCZpQUGEPboSGGh1OhTL0TcjUaI1kzx5pnFFlQW\num+7966tMQzGB0widT/dnC203OehdRUxF3mVKO3vyZQS/QQL0LhvmTW6F2yZftZZwGor4BAllquC\n557VhXbkeLpl/vbtt0chG5IT/u9C7bdHihJPK9UT4R88nM21DYUK11SdT+pomG5JH2mJc3Io3YzG\nZcfbv8KIZsybNllnnP/EBy1sp1maLL9qN6kF8hDFHfB/Jr2elZJJ01JYHPOQCHNy+UA2Gl5QwPr8\nc9SHuUtr8rz+WAOCvege7emLx4Jt5ytymFbSfrvoRM+ZUxFmqe62SfHTEzg7ml6FYKGwZFzHxAVP\nqClbYQVma1hfPRcOQ2EPNB+IDQvSMtnMgfNCRvCXzR+Q+46QsNEdqQLttQrMkLWYUWQ/PxH/abKm\naMyBEKhbB0uA37pA7d7nNWme6VWCZ7Phlw4sTGZ9usfSAF2iks+dhfHFUczhnkRr5kLs2nN//1Hm\nujL9S2Xh+YR8mZbK/X/DNNxk5vMeM2BEVm1PZoxk2SRTp2R/vYNolwEbwelAj06fIHNm5MpYsL1E\n7ncTpnND/46Rp+9dC46VWjFitJhw6xYQBnAnAUgK5XKJoMd1ULWbXo9Obn6RduRPzN0a789FLdcx\n4OyYK3f61tQF3inIYC1r1HHOGDrI2xRZVZNZNDzADjAcygRu1Sw4WL8VBi/vYsKqVoNERt38KOEl\n9NyG3q3+6TPPg72wauvsj9vXnxr/ERZ9FdkR/nhOatd9PJBBtPaEAMYvPNJ01ByAr1H9v7EusrNo\ndtHZtpRoWhrKsTvw8ChWSzj4E7jptyFhnLEslaw4KGbKc0rKYK/kNZB6DrrEl2aCV7QHsdkX9Bj1\nPKcOWqa37YQlp97WsyhXrowmbd3CistDmVeRnzDx4swr7Q6boEig1BCH+1d5aIEO9ffvu2QbMvti\nAbcrVFpP6sBalPmiLjS15uhWV8KEGw781zQ4mqnoVw3oCKOuwjvvK/9OhNoout6ggrrMMfHFLop/\n7TagcwxVB59eehfgXDHC5RxEwiKlLkX4TdQk3bJgWiNKjaUI0iF5sXdRTcu76owM9bPDeFQ0zvcK\ndUkPtD7AXtk/vFhKjwLRLeB3UTz+YhoVaUH1daPHUMlMEH+eJQESKAxgCeuJAj8GZnyT7+cw0TT7\ncjpaqS0H1C0WUL6EFh9/Re8yGO0a8+1Wp5GoD3ceJ9EingExgibnx1rZ3dLJ8Hmf4F6c97FHtUGj\nWWra/KN5WoCJrdl6TSdm2vPt/3JFImXL3VxVhD1lHg5jk87q0UvPEFJbe56oPyUDYIHorFMXCtkB\nSp0+FG2szkowh6Po7B7p6lTueX4hCfE63q/RjQu0vNkacOGXYHvO/nT/7D6KtFG9OpRZwtuB5emu\nCGXEsehh9FDIFrOpVZN7q6ME4mkpcEBoVM5qdWoVt/3gUeGi7NoO+67+Xub8tmwmHzbP8nOXg3X9\nfNoTD1RXYZyvLZE4fAJJsmUmaxheX5QZ7wY+viDhcuVgAlnxxX0LLauJsgSdLdbbADd1bV5VS5Lr\n7B78FfM0LvFrQA5ay6ZN+k3078VR8KQ77wOOtuiXuls/asxNNLGEZe3j1Oqa8f4PJaCMlo6GC4Fw\nG3ADbVBwDp6yZwFL+jqVJcecF0yGso2WSscQ2vtmwXqV/rt1ntgPMcrqJSBUCsg3n8UAqSqyrJMP\nFl3aW/zxO8e34gRl8Gb+Av7qEDyqQnJbSeqv+bQRtgG85qT9oO8xyqlwpsHqHY98338C2Doe0qWE\nihq/+PAb/4nr9c5kJKMC6aqGRJYAD0fox21bybPmT4ZB2ZffeOrw36ME+hNkiBhNVDEW0j4LFPfC\nYTBRPHdDBONBGboUy+sX0hhLEFqDxD/pZ5nuulAJ1Gnpq5tYOdAVxsaLS4xVsiN6zvxKorSgpp8N\n6MetCHR0J1sVQSDbgLtEnrJ7/7F0wLUSS9jjxyJk3JHSRXyJQkLPrGjNvsgaaZ2+lUq84JavE4TW\n9WVMjvOBSoHbjCPnbFZC8a49DiHvK1W7MjjzSoFWxEqbJf55ZKbmbZgJvRBEMomcR2nX6WZLbKWd\noRt3xjhQXyyiLw7QmCKsylEF4+dhqgHIebhz0y70vdoOeqc0rMJsm2eLHLngRgytaRry7GtPEs5k\nEPzKLb4IzUud4aHQuqMS48KrQWjqCoEMqJC+/cyg0GMCPX8DoZ9NTjThi3KQ0Zm7ccl0zBlw3HJO\n4qeihfn5PUbsuXiimxdpDSOITExdNX2hgIYo6AHvcXqMa/5Srf1HuJLKLN77iqK19L2yGGkfG4cT\nPp+WIn1zd33WLqzGEEGFwucN4QrfZT0Mk0WseahDZbW80vLs1NuEfK2AfMYWc+gVKQjjNjUOEeA9\nEL0nVCajyreQL1X77MQ/Z3f7MKXlMZIKZ9st9Pqja1Wqt63i3HjrSEDh1cr7EQru3+zBo7gAIJNr\n9GzPVfhPzNmlRJyLd29w63i3/hPgjFiRB2yI01ijIow79xNLQev0WpGBJKnLZIkIGQdHfPjySCPp\nLNOOluCTX9RiV7C2yt65IAYwEE3Rmu0QeEMTSJr8M6cwP8mkQHG7TC26sVsjzhaVJ31m5gOTplWS\neyBIdXbYZgIWt1obgM5qbXkjN05FCv5jjW3R13d0x6cAu0lu1EIU8Otrn3d7K7abyyOqc6fFOCWC\nFarr8sTVDJSYHojX+adnx0hjaUrcMBbGBTKORHKWrTFaDAPouT+Wyu7oCi+Hh5VqU+mZe/qB7Kxj\nlgqWgjbbdcxQ8ViVvicBe5q/Ovu9OX/S/BryWWNVpNVVPrNNP7Ud6AruH/fVFpmbyTL55m/dllDf\nEsoSG4IV4Iq8y+AEYbXrUUN6PUiM0B/GGx4FWgf8LDcPntO8P7KQcTV6F6MLG/Me/gsMqJg9cTka\nGebbtdVE3YGk4XTN1vGthwkfPh1Bj6hbaXmcvd1KVqWndHf7ySukioyKHVdLKfaleKZQjgYrFC3+\nk9M5UF8iyFNdxOHcn2vCBKWVc1I2pd6ZMR0eYCpW3Bl+UUc551rT4YjvRrmtgQDJa6pyO3YU8u8d\n4WmETh5BlAaqkEDHrICLy8G5Yep8lSuyYflQRyJlV2xhgVqOUJTgtQij9t35ogixJNN+XdeAvnZN\nYp/xoGGboGv2dQbh1AB6/hISTyoeoxiUiY8Nc+wJ43jxi7Zof2SnRGiGZO+DEU5xvGRXl2Ws30bG\nF6+Am3Fvx6BC8+k+3uh9EM9dWQfSBMnHdb3idchTHaECxrWgQ6YbLbIwFuEO5ZH79Vq0tBc5et4I\nGX9TavQlby9lMDPpsiWQoFMzvCBc3iZ+lZJau9LWocl+f/9BM5rtOdI0HmACQiXtU54IhGtfHCn8\navgoEX6YeYOtrL13mkeqZNMTwp9lDG2/ChB8jfBoeD2759DTTH3o0cL9Sf5OTcuPA3V6/lQNTJTO\nF17UEFBwpnizy/n8XdzKpjU+gDcJsRcp/WGYombRXjSxfOEcYeRGaNBkgmqcV6xbHB9voCeSyNZQ\n3NYbjLsDuHnQ5i0saD+Yo1ryDiGFJoetyr6nXA1l8onA/40QGdAL14rfQV6HmaKHRVYCsF5tQoxH\nG29OdGuI0EVOUfIt+T29zFbaLde+rv8aqiogYctNjvILupJVMCrUy3eB1cYL1r4cE8vDpaIrVw3S\nlXsgoXh2LK7PC3REaCHJDLS9oq0Nxu43MiAuaSZ6DZp0U5rHH4DcUGKGK4LxiKC1fKZB2YXk8CXg\n4JmMulWsBZyVc1Hs2STEooc5NEZRynFPyNx6sPwUKpBlwvxgPIz8ashYeArr7pgtazIlQCV8RsbB\no3WNCfSTrHDscYbNhNGSN15ujTXyZIxf0xmw1NxhW4VE0LbVbU4Q9muynFksh/f+O3sz79eTs2Wk\ncj94qweFDzzDSKfo+fYFxr35zCg/FefHqD9FPNrkArUiafPmFRWLGkm6SWycHTHW2dmOUxqBLDnS\nKOU4i53LrnwJtNlnnNbR9vCnTV3HZkrvTaGD1GJiRzC/es+XDUFHEb7YDM8JUKlRbU33uV+CnXcq\nE5Afnqcfch6xTfp4W24eBeAxeKZEXYdjLxisOYvQ03BbLnt/ao+HyqjiaVos86B9Z8guiTv7Y7vm\nU0QBEPyFWR0ehm2yrjUy2ZOjpN+dN8ptlOpi+8jkgisg6gYT2U8e1S2pPCrAtZwj51rEayRg6gp+\nfZ1+HBHDLTW++YMQshPGSEXZMzn40VO97CNjgrh8ovSvROZzPoujNet0XF4Xl+0pRfUzN08GGTzc\nCDNZWKvs7QQNI0+Jzy3TOqD5OoFWQbRf3ETptGJEjsxTG4xPlNBT393qN4TMLuz9Lu1DCUKN/auR\nkZ2FO6X5bGfE7IJXmo05JK9M+NQ17wS6A/rJrHFTFQG3i3U1xyCqWFjTpJJamaXa8Ap24WYvz6dc\n098Zr90dPEFqCDwe6hxyVvY5RfffPzDqQb5DMiiFBA0+l1lXQ6msvQO0/PjN67FDr+p4RuZxhV6p\nTCZm4lrQ47Q5/Asnv2QX7XT23yACOPXvT5VII5iJx66cZDW8PqcokaLa+pAtVqbgZDPxZD1C4NXw\nAoObbkqulKoJobs7EjZSIpKQqr5GCZ3QjgDDwPruhevdnzONX5uBvI19+JYqusyuR333F376uyvK\nn6F+d/zNdvSAV3gIz9JaPPEhjbKgsUOFhdyDoaXdydwVHrAB1SkIhNzpfNl62QU0h9m1rX0tPNdt\nUnlnjJPMTjVt7hS8vJhfgtk+39dFB37FS3rVDWUD/97MlcR8z6MEGzbLsGSRtQgzQXSzXL4ruX2E\n7F8oaVsrywznJGiEc+2zzA1QekJQuy5dxS2hvHftZoajaCqWhhrACvQAE5HTIr8etonzlt70MhBX\nR4L2Kdszs+cuKe7YCn41vp6yn+jkXCpOzLOekgT30vVB2cScqwhXUnoA4eD5oeMK/VvSG8OomIto\nmaCJiv0wLgJ7kJsprJEeL16mqTkMwmvay2FtiWlIWbKIs9hgg5RqP5ftklAYWiA/4wg9CMMoH2hp\nuZ1nni2cWWGynf2ne0XC1qDqennT2JyNAQtk9Jw0eXHvjVLarN4YgyFvFTr0C5rV9472azo3UE8A\ndbhgNUf94/74joOWhz9K0BX6hu6u9am3nZfHjzT8iT3pq3MtSlLDx/+vqR09j1sBXhBoyiyASoio\nhAQyBIlf137OHYUONIvyzXe1M6PgVDfdvFr6g7VVEpVZDeSgkN1SXdnbZwYBVLOYe3JTzPfiCNmw\nPL+c0DJ8OwN91pieUcftyhX8/4nraUP0jfbmoqYneAn2aizdgj+uYZDayM1DDIqG7HkWgfoTyOux\nFto6L/LvFuzFDe+ipcLHg/txvv/oK16fIF31ETqIDIKRU1LBbQAbPUwEZxC+TEnpkcr6oVT0hwHN\nJuTLW8ZHgsVNC5YQaLbTIU0uVZ2AYfXpD5jXx2DHxpFmqpwAA10PEvjjBwEXurS92XYW6Vlh3vag\nh8071PI4Y8h0dlx5dPI/VyJA5MsaecCPh9Wc3Mu9ju7CmJzmdnouyGW49lVc7T+BFgn8vY84W4Jy\n0EOJqxtbldn/b0RL9qNfkmndlxOOYUGpkoTDXOeKNtd7HyleHoQUnqsrJltt7n1TUWyBkUSvmr2e\nhIco9V0pfGLnQmBrcS8ESf7JoDfid3dd9xhfTYd7x95o4BpLRW9VbAnUv/qzO2Ql4PsXD4elhlqQ\nIX/zvEAslyulqRlaIojF5lfyR5gs5T3XDgy9J3wvtzGMB2e/OdhArVKDlyiGKVBCwObJBltJLdrm\nqQtoqvfdCn+V9EPh8P1tILiKhp/pxpNcMLi4F54Ss1mMT6eOjdsUUk2NgxCMXJ9DCe3Vzm8uyZL7\ngcN4jfAg3E1rqk3m/i6KHng7yyFwHWIWhDG1pdVdgHnmaVWwnYivlzpB/S7eNw4unSB3dd2BlnzG\nRb5PE2fCqQmV6WZPnzyEbQbON8IXydg2GwqhVl7d+KhVvB9u2DtRSUwccaSTmzQitYkii0ktito/\nOZn5ZAWREOagH6xk2jSJtB+raBOlZD/StDmobLXWmpcaSlaEkDEyTAMr+crVbeg3vAGSoSOK9IbG\nhEMMVUnbYc1PtZV+vY21I6ppYt5T/zHwORuaK4UahSEs+tc11E84gYKfibx4zaxbrR6PIWoRhFpx\nfygJGI82fQqpK8rIAfb84Z6eXjnfx8vNe3ePHTI9pkZghZ1vx44M7VPJerWd7U5zd1C45avIo7bJ\n7u6tesU5+cplrvIG+231DuhICa8DH9UF72c/JWk3FiHDqhpde5ScS3IcWx1hhrKBvi5FXoH10veQ\nlHicTS5ZPF03XuljrC096UTByid0LNhm3MEYNMhJHDAg//PphATDzK9kPRVEqWJNnUXtQxCtfaGv\nDDm9ZwguZj9gqtu4FYLLYUIYBSERRP0P3uA20WOHJw+chMy+nL/5NJ5IbO3bDpRrULtw20tfYeXd\nMEZRrVydMWKNjYU3WDHTREgJjguTG/o0uckR8jUjDqND8/aBClo3a38CpFmPcWL6ws4xn7mPX0eQ\ndm04/XpCC8K8rCxBby0gOx53dNfuWePoTZANSnjGGiUI5BxmFdAWSo6va4tcRBNNZMPM97o0kVhv\nEPnfc3/sGE1x3k8/zSHbDc8HaQOXTo9W3rmPsM1cLrN9t27Iox3uo8H8MKqn1YcA0ilt5LAjrSV+\ntUKxL0hO5/r4sVSAigD8X48thLABHsoJPxsvEF8LqbeF6ar28+m3HKCwEkXmuDsb2D9EH9UPETzk\noU7Zlu+cBilAsNow3MhIVGRoQMJ90wjs5tMHHN0coijGoZTA0lcU/s6NGNC2TOBj1w5bSDX8FKiM\nS07TxyW3rw6YTaoFIbD66Rq/NSP/31Z3DELdKtPR9xDQKSDKf8jWDeUMJczhi6nWPBQbN7UQtmrO\nLkeWuAHdvStParHRMDHlyl76hJKPEZy48fg9N9UdnO+Pd1Ald+lem+PCsHHf+OqbXStJyJ7sNQPS\njKJNQgifRKxMJxi0ijJ0y77hsBxInqwKBywtcfVKlXs5gwB5+HzKqctr1bzPf+oUVROtD4s7C8n8\nPRAVBiiazwsrGoCKpXRTQdmcPIWk5o/ljibexkeIJdZGOflQLAG79TkQP4VR589A9TEHqrbDA8Ow\niEvue5OjEfXk8v35rM5k036b2nWDRQjwgH6Ww3B4Lm4ynLAYQGTB96U9XWkAnWLiLp5m8zvFZdDi\nE+meA0JkE6eMo9xpSCwtthR9qC/ZN+oxyhOIxOtsuOB79uBllrVRyxq5F8q9Jv+a7IKcvLMc3+Sk\nZmbgOAgVLYMQnsj7C+GgRoA181qNGBLLADnDESGgJ/3VlMRVMiOvVQ+AWmMuns4aRjO7TJj0T4gj\nOtQxN5mRSOWygf4wDNFbjjzdk9Wrb+YtBxxP67a1DBY73E4f8rq4GAGOc+uA+vYPxN2cpzQMxn67\ntST3yTFSN0HU+TLzADeDsR9fli+VCAO40pjEmfvnmz8uX4ieAh1/bmsrpCB4hddDi4K7Pm6hCPVZ\nlNMu2yUJ2Gv7pSfim/c6uDmTOvuyKRHsEtHBss9V0SHiF7zsCw9jC1Gw1Z3hAWIEE9MWxlQFYCc/\nOJl2e+2sT7p7D6B+NL5udUm7nX8gB74q1PUFWPsGYpD2pu3lCBVsQcSipoVTozPzXTMu9GhiBbtD\nKMVzVgZKLQb85zYLEfk9esGkaaAa/IMlXBYyZ3KgxHNEQVVYLd/28z6Bgq4z92uZ+nUjAQQNhNbd\nihUSeLisI8jS+p0o5SqzysX2BhJTA73Dl1qC80tYYxi+Dgt6Ix5T5JgkBeZt5XKSBj+tWhDWKCDx\n6uUFw/ci6OktwfqL5KZVOMkEwPLWW0W3S4EwFRv/nqulclXjxaiEmI1qy2g3i4xu4ozAzfvuY4PX\n4TNsbHRGXKHnbUq3OX7WWl0FoO0CnTw7uzXYj3goIj+2ppauZVSQt3oGFMco07p5c7AG791rM2wx\n+pZL5s5qBaL9pScdRgmtmuslKlqootc7gQJ5OxR6mvoMhOnphhgyojQnOr+SJEtDMMD5rHlXoSgW\nUJGwt8q/XT7s+tAVwEfFZwcio0IPbQNDOOsdHChnWoWh82tTu2wWSgR7Kg3fahsm6lpYDnkid7j5\nkTGihYKRKRkvpg2Ws63TmPYjpdul3WC+b4ZOhk6v3C1IdjpjOJ5UG4l9tMkYVfoW7y024BquSO5/\nMPPdTM2nWYdjbgO42K4Zxv4zLj2NSkWZm3pkgJP8LOnt+bV9C5AceuFe2YEcYfHP2NnzCbPkW3DX\n7OB2UfViC3Mm7S4KKuGfnRC4dEAlRwcrCwYneuiP6uS0A1MNUvCnPn8WEs3qpVOweX2aJkYS5ur/\nR1bloUhVQUshGkVfjwbVCpNKA1Z9uzEmBMAoQ7XvphL37Gw4A6IF6IP0hE2sLueqpM8yW6YP/n2m\nThOWH112SQ7B6Cl1xkrSYRy2fRhCPLiOb/AIOrOXBfO7Htq4hRh8mLjn9tsBdxQiCauhjPtftHqA\nbnkLa4np5WOkVect6L/DVTK0V5YtCK3SVmMRX5+n/iH5KjTBdbJDG5zE1+cZIZUf1jHOQT1zGeYb\nPcdKviHtuX/dxA/zR96YYgE+6kvpWexwOMkvDnMeZrFWV3YA2Q4yzl1IMz7mxXAYg+xr1XhyQAHh\nbvAoPX1ZX/f/hT0d5tm7H0+hzJGpOMNmOb9uWoxbURr1oTe7Aub9LGHM7MeHGjRy0eeNA4l9a3ZY\nWaNVI8NHq1/gTMRD2P454oSx+FPyBOny6Sx3+WAXKWV4raTpFUBs/OkARVapcvZtqOP0JQyWm7PT\nCLXQurpYYnK+M5sJwh9q8N5Ymi5B7RVWKXSw3bTt5UpCMFF8w3wqLBnB20ai9FBNCmCWLZmqK1BW\nOT5Z9SWGsFad4wD/ykn7EphW/XOoLWY4gWTRReb8kUiyK4uYq3GdyedGWQMQubbwsw4Yf9XLQOCA\nveyvPmR0nXWIDyie/P517DyAPPR3QSsQaXWL6OwedlZe9/pJZvpyVuCkMvohDO0OiZBnKhw8c6g7\nQDxVJpr+PzuscPWWNvWsRleF9CtP6o3lVCPYofb5eni3/gew6UuMOOPdq96vjfol+ipMOitig/EK\n5KSSJc4ignVV1rpPdS8jKt1uRzdiIG04lIgKV/iTrGxulwFTYWn0YXZ70j00M7akJBpgtHYtEwg7\ntuFwF87SDt98jOPD/WHKwoeleWTKwDzN8dUG6rIIjciM7ttKAupuKB8zcngy2+VEd8SJsoOuiVXv\nI1jEkJzWfyF9h+BgpXXoFGfSUjm4PqBwqBTsya3TbfnxMusFwVAmhcgkODyoaBE2aPevUBLTPEyg\noXiZdFn96TTFBTSKxfbvfoWmBfJLQG+IUMH6XUArLaDvPsOewnpCrh+xOPs2VUJvRJlbOoQA8hhc\nBYFw9C/vaE8JPImPCF8Mcml3atuzrH8J+M55leKZ+Ahyde17lDJYmLaTtLVQgqkyaZyHgYJabqrL\nfvxMvqW5F5ysEsk4uLDBFDd26mKkWfaYPU1SQDCVe5TX6ZCrMoOF7QT3xo/dGRKOrgxhF80rEBSA\npbHEX09kRVpK/s7dJePfIDBOH4wslJSyr+cpQWARs1LDsRdJqfBnbx5MEQ4E2qk0F1V6P0Uu3APK\nPs8KsBhcdUXgUqbGbsEQmLHNmMsW9PItMgYMqBKVjCWjmnu7XFM+2WPGuA22GFgbq/HHjTvb4+a/\nhNHFvP4EGDou4Pq063a7EtIFFh0VzxeE8It65f8GizD4Z/YaE5NBdVql7NOdDECr3l5vqCI3HnNC\nrd00HANISl5oyA2MuYTQR+GQaXrKUzZ0cDbvQZ7P2epot1a+MCmRzUKtgRQlP3GEAOvl/z6jyNGl\n0i9gClFCTubmketbUNA8oLzc5tOCpMdeyfZX7wq1Mj84m63g4WECc1S400lGBZhiUvaRIgsEnvQo\n0/oWeneHemIMitJgnp4Mf5PvMfKmyud8ED+o05VrGt2n1P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protect end_protected\n", "num_lines": 1219}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nReplC5Ahoe/ekHadJrZrmcxktMbPXmgewEOVkFltxDCtp7tjIROEjR2J0SX8SJSOj28503HOqCPD\n5HwauVkxEw==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\ndq0jjzDFNxyZLuCz/pQfvevO7zrYA9e/RXFtC0zs9vJkavN7vpFs4dWp1T45tmALQCanKasqmhhA\nbRrgjw4a32LZXERx90Sp9x8VBmLXOfw9Xg/LRBctRS+xLJvPuQPnD61fU2yD+DHHuAh4V7z97iBY\nW3qQSUzTTNMN1JprB7Q=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfslYTuc1ifY4iZRomp+98coaTdM+sERsLRzARKGgfhdyl4ejm0X1439hhlJZ7d7tGRtc9wOwzpsg\n/BjAHfhI0GN98FPbTMXmwIVZ4xb8F6OfUvJz71o+5oFDkZBQA5t9GaBxUno9++/GrhnRLkDhBhE6\nqqZtEGogfxjP7u3D1TCkD57v8OrsqHuuLKBzwJzuoxeo8w98GmBS0W1HbRoWI1ihFZb8bi6u07hw\n6G/59mB0i1MeTrA/nlfp4ZqwFcMwUkVv7BNdFPdniOghdGRFQwXzx6glpgnvSkzxIUcz9YddAzDR\nz9lTjMsWZaJg/1VTBaZLzzRjVS4NidlGCWcAtQ==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nNuhRHq63Nn7DJ7N9KmLTkmFO/pzyN322hkWuLK9DFqmNH1Sh/KUkgVIzA4YEJIlgTsfdGyxmXhIz\nye2BkQBEOyNZ9V8Yy0f0wvu/732rGkqabthdyRagbuLIY+po+fNOV3Mh+L2sobV0cCL9+FkFM9WG\nudMRIHdqJoU5F1Uyivp9XQ5p1DqVBUEeKGqb4oI5hyk7rgBR/wdsMmZaySBunPsOQOM+GCZmCwia\nOxj7Y7YMR/AuildHo/MG6rH7+TPk72luhTUoxeUU4RFZ+OBOXVV8A746tcjYIW954lHFuz1lOjyX\n6s/E2ZGSB1daVYsVGbXZCDGXztOubhxgABsydw==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nQ+3bSvkzpWqHz+Js8pO2JND+aLH8PVPx7Ga566/XW/zU52UJgqgvgfPO06Rxm0MrzgGVOeqcgfjk\nl8f8T74yQPJFxYE97dwn6Ek9c/4P015WcEt3HbSC2NgCSmyf6Fk4N4oPC6TDJ0KdzaunhIg/uT+M\nVNWRiEQq4BZ2NwoyIQg=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nKA+Enx0zxUaNQLmFOIuxV6NZpy5a6Hxgt6WW0NNg9/X6V6LK2SDqokbj3Y94Ev+d+qhLiOhG46Pt\nYdBx1YsEGgnXq9yoAf5eTiIZ0pbsxXvuh+v7YNLrVKsfNOTds0cDPcKfUIP8DTK2xNkgnlDRwXRZ\nbKquTuXNS5VL7rAeehT5VDDQmEkchpOsvfMZJh64nsWjV0Jw9Pd9l7GLuLK6FpAX8UFdoIV6Aq7J\nLzWlDwrKxbpeRz+KN3PyqsAAMIJ7xGaNHyPcGgYdeGqw6Y1OGYPhl+r0a7Rw5wZV+TAdgvDlqs0k\nHsWo+wgX0B9Jelrlwtkvf2GAQqWbLnOHJBSnag==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\naey/uF+AZUbOHsLVgq2yoW++LygRP1Vg+GXLrXqJeFzf1kNoqXKfMmZrr6DoVtdrKYjYJY/4phwJ\nx6NUIOO+ZQKagJunMRjq4qbAwGbdQw+1XgVGc39UoYm2j68ZVloHkU6g31JOErPBOLipxXru1NOM\nbYHk6hX3yCAMag8cPPtYksM2IgSUMKyF2BvLEcSY+j39CKMZ8W29pswu1O/IttaTmrZg0/AHW3SI\nz+L4nEJ/PL9raatcU1EfLGc099QF6JRJ3TqLL54a0dSJhhkRDSBS25Eht06P7uZJJSrrQ++fS9C9\nufKM73pD99Q5rIACsX+NQnZjsU83743A7FPGyg==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nXlLvtlTSSF8sH+XfrSClMgxkHY98hTFFc0DfYcUZStFT6OX+TcKGYnahL6GaeVbR6KRu1l3MH+Qf\nNDhEuzz5kIqW0tm1tK1YhKnOYisr/bS+V0CRsII4wrWg58kws17hF/r0yKdFf4bwt4c6y24h1mC8\nISdrxHZC5OqMjzEWUD8j7+Fvew5PPt6grZV7ZiuDXkDcPhtSCqsckTGVdIv33bQNrkaTbRVmkRX5\ni7RUiBWd7bTvtedYFq4fsKOvOs+58u3isvemYL+GdrsXg2rUc8W831Y6erY4tiGWaosrxd8JGkTY\n571QUO48QJbtifeSvfEFj/kAdp9w6JzGqAW81Q==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nGurT/+cXPnDploCER5sXenqGF2E/6XdlV1uohiMfTt+RD3ORIPtULbgYMgE0zAH0FZNWAeecY2mq\ni5jQhq64mRQZBmUrwq2MV3chNXYs5uWtowtSRLvTeU8bJFoUlBaLACw4A55OW9IC7dFhUwt5AkUj\nzOTNpUTxfbRdVlU+3UaIVos8qq5kOOrGSTcH1WsntkO07bNmD3j9jvKJIETKjO2tWEo6wLhFkmau\nv2zJMitY6QD++SRwNV6dDA/jI8EDOz+Jx+SfGauVRnRgBGznV80pjt/6MpYts6WVHTdvvsBhZFlx\nsAUEosByPj92SgAWwCJMqXWMLQb7Q+QArt1PNQ==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 12464)\n`pragma protect data_block\n/GT65feKxOxX3rp61AY7iVqPNpUvHZre1qx5IYW8XFNcDOv8hsfJTckNb/4sItSw80KlGJa6Dgt8\n585Ji46DGYiRsRRAaWAKQZ8+rXO9LwLWU6mWk412J4DXvTSc4w3I+29qXdx35aS5MdSxK6Lcp05M\nolbZ5c5tQSv8I/tkE3ioRxirAcEafjs3HHpgXPqKDbSzoM1S2m8KC1JZhVfzqU0HvmYHvOsB+q8H\nNYHoUokv/Fjz2d+4V5sAw8P/0NLVUdR+QRviin4OWuARNm25/5BzeVaHUi1EQxPqLRx4LNvmEo6Y\nlBEHQSkG0uqB/tps+73AG6zP+00EJlteJqHXkkwhaa7RWNIVOAl+GosWyZuG4pcnPYW9q/5ke2vz\njuaWPu2iKNuw5Fip5S1rhT0CTZDkCWO3hbkhSYPks7bA6dM16LAi6e5WdUee+gv2DCoxJP7wZBWl\n0s5iiVsPhm4+kS7Bf8VUsQU7o5BqZ9o+uYAzbvLnoQsReih/MpfnpMyV7DbDUK7kePTo1ml4BTIb\nJpyCjntk7e73f5XWABRYLUU619vxVKYmrycopAN1ar+nlRfPMIB7hukKv4d9leC1WZ5pYy/6PZif\nEYFpD6ZINE+vfwn0LY9erCBnSUFJYY4p6FQrytVOnbMW807bBcgsz/v01SKm39iED3NScBqTWG3D\nRo47Mh4BGsGuutZ0wans2YRDFdMxWsrg8Busy7JoaWBFT0duX8/kDUS927nlAbK4fFD+5xvXMlKb\nMc12cCao2Myqepc9gZbBGJzhYO0fcmqOLg9UOZ4OhPc7f1EPJqFJ6xeFjsi3J5uhJP7ku0GhgOBC\nC/TwWNxlyJXma4Rjc70Evs2PfjfwBAVnDEQXuohVqLkJIsU53wThiWD7x3D6sgxE+Z4d7QK6B5hS\nGm9a+QJvraJwcL6iD1NunChc6ccrEBTGglwrce0NM0zG0i/iBp4xA/x+QjBuM9CnKbsrNjvol7GI\nOnb/W6br0lavPRLeV/Oy7Gg9S99cCycR1p44O7rsG4WOCAqvKNEBSmJbk70mdVzQgSyJUTmYRlFl\nWGM9FVZR5UmV9g8UYT+FmI52RIS/uVF629XCFY5V2cQ1ZmitT1dJXw/gdBaHrDO4gtyPzA/glk37\nAA67Ic/z604a+l2YNgdug6LiL88fzhwc1420PRx7Da9jRvf3Esam39AWWAVcredW+N7kER4rBwT2\nh99rmMGW6VdnB9dVoIetp0AK0gahvvXWZQNuIiiIVtaiYWiXmqyM388XpkLbBc3sKLNweL3Om82R\n+dSJAWvEQsrD7neM8iiuBwh6cCNQvP/J8Aumdyp0hTRCti7iB98GYyqb50r0PX3mWEn6aIvBXe5k\nGhK9QRBngqu8lxIXVOLtWnEZX9k/TLd4blae94Az/sUUURXZXPbJZs7BOtOQ6+8hKPQsZ4exsgOi\nfGfVTfevmFLzPBx915ymMw8v64xjUd6dDhTfJnzBd6msCIEoTPSvQtOFbhR3sGlEq1/S3GPeRvDT\nO47S92WYSyrWEiRVBC5lJD7dWwEN2ywy2uoDhLO5ISJPKwkQMchKQ9MRGgxgoXNggEgDYnWmizoG\nmejkXPKg1y5zZXz46iIZ1xkvS9+emX7nNlwZriJwLPnawbXkHqauUTeOXglOyfSio8Wx59g2rUcn\ndsDNcrWEZK1TB1PG1XE/MVgqb9RjnNKrZf7Tn2H6R52dBI+XwQq75BbYwOuD7Q3SZhepCyrZYM2K\nAEITrl585Q4GiuX2xku1/viLeh4VNnL0QxBUiA1DMLxSqVX8FWj8ATIkhfIlwe0YiO33raMeHaHj\nvRdbUQk+QZFMm5g/lZGP73OFAABltFhrwPxG7mgw3ZvjHc8fFSJe5u/GWEZLM03grq7QKMlQQWl7\nB3AsfmNAUFcWgrCDtKRKOHhnYq64xkyGhm4bXgURw8iUQxnmc5EQGI9IS8M7OXPKJsVij4+CCMY5\nGNuLXR20Bz/N9mrD+LpkWQQGuvbYiym3wcfXGcbp3omy+KAfM3CoXbNE1RTJTrl1oCBDOmYJyxBw\ns1TaCVWJag1tas9KRsq3yzK1Mf+jqrhMgY8f+R/GLCVnFvyBXO3CFAT1lHf3JyQT4DJse3r7VL+g\nMp5pHFWqdZ8CQ3ck0wRo2OejKZ9hr8RlNwPDdI6ZVd2UoblCASViolT7lRE5M+S5RZ/fJcgw3mxO\nSfKDK/ncxAtsNdN/4WTYwb4IQItjSaV0dTSrP+63FU/bFUHo6fOhSb3Ji1XBC2KWQRshFpVmebML\ncx9eCP3is0rbFRo24rvJ6UbNdNDH1OKrT+gLFifHyt7C63jRV1jwxBvUiVvvkNL+qllYcG+9R59e\nByKsGZLh832ZON/7jwCsHfwH7PMPuu/w5MiO+pC9tiZWYXEZITwEf1S6TFGjP9GoWgZhZ4qYD/PR\nUcMYV7kSp43XZzvBFEETt6SIT8VV+bwKap2nc4CfEeM7AxcjuyedRI08U4KEQXZkPvn7ImNvs1Us\nao3cyB1aE+4RNDG7WbpdHq9KbDPEKWgft/CG8JL1Zoig2wHjkN7GHbGeWqsMuznn13FQbMTBy89v\n5giPHxQfIr7DsKJLsCE5qncP+u3Bpcm/bzh9NADdXOFva+YobZcHjp8klk3DxFS/ZVWHthppXOBP\nA6k4n9Heex0jjOBpNhrWYBYPsui19Sypw5KUryqiLwNeRaIxoMT3OgHR1/9sR+VwRVuepXekDwcV\n8KNYNJ+b6x5KLSyh0o3E2TiJmpQzdG4gRX+7LN/h/C84hGEa1jxaSp6yof73EqkWlRWkmeAX30KG\nyLKcOBZVphqCxkRuDmc8WgFFuZzPizcksOb0NUXZyWEGGmawCGdHF7R20wUCwMyzs8NjV+FmR0LO\nNNxfjFX+tKNrEd1ipD9xQcgYZJzA2a0HvUARS9sBPrJ+exAeiQqdSN9GYKy/HUIjEuBtvp+GavLf\nA61jEz2H6k3bL5naAdpq8rDWH6J+8ReUQWrvAW37yX6BHk+DciMVutTHFkv7+4bQrVlvCGJiCjkw\nHam1gycVcOOCrNJzBU/yczjXMr0JGw1uvX/aI8QmofpYEZiZ1OW5PjkWKQ0ENElhw/It5NAkGL5S\nBkADaru3F7m4i0j6RVv4QoAGhYVNdb7qO3mfwlZUs11sxLWfvWglkypoSeYnn65mo1m6bxBt4+d8\naUx6Q+CEulB9ugVXHTPlLfADAK5v8mudXYpIHlUbcfjhqs7FX8YhZ8pSwwSojzkp1I2+oo/R4UtO\n2OxkI/BNlbBlrk7PbuZr2yKjrgRS7+UciaHtyN3+7mTyTii5B88YDLwLrWQk2IuJ/t9pXIl81fm2\nmSfkPmEtyAbH8L5N9tzD6CAEzLIDWnayMmgie6SVKjukIZWa1+YiALr5tDlMRinmwgprfQqy0O08\n+3zGF9ufwPgPTqHMz0iXXsQk/kqYj22KkXG6wXob3G3Q282b0GFPxOMbyoB3VhCVIwYjyKfsrZXr\nsH7dAbAFwFJgfR9YGT07FF9ISnoE/fCHaSrwhusJ0tKUVOuCibFGR7vKfT51UAqKG5OLNz0o/xvU\nbuOz02Y5eIOrdWoyCfVWeAhU6zdOhzVveFDNprsmLKfgps/QR3wgYRPimUegT2MSfKhTCrYSda8W\n04WTeDxFNcFEV0Tr0Xwg9eRYasc8P8SgNrio3kmAY4W95sBZOJYhgfbpf8jkySvurRvFao43LcsW\nfmjP5iJWQElHpVYb79/amcQRpFVbCILepes6UzVezT/BKYsB6TzFWYb5SXBxla9SKLi4uAuGW8uW\nRbK2dTD+al+QA4jYSUoMXynitONOmBpWS3eEr3r2lMP/iyQzeU8K/HfqaGVvXtW4lQRhLX6dLdor\nLz8uvD1mANX60AZQzhbFAQ8pC4iOliAI2wSbNaZjtl3qyxZwCijZjjZrLgAukRSSyPRrxGiAXs8L\ncV/LEnNnpMP0kKWOf52Ht8BH17TKRV63nxKC0n3B3Lq0eeUDlM49B7KFd+wEebPs2ifchwfG9bKb\nGhI7QjFMzX/qkK9/oo4220VDC9YY6mz6Ezol+Oev4AGEZBvILY1UdkX1nbItevV06k78OanwOC84\nDICFWFV751b/roKKDtWej/Kvz6RiGj8o+TJH1qC24laAt0wFZTkW13VkIP+ngbnmGkoZx9BDxEOG\n/uSAGqXAgibeXGNnpvE2OF9b6Ryz4yAJuz0vE3eNNS1Kk0CO9Ia3p6Wmo/fDzrIpdUihB2GOWRIu\n66HU3LEAKzCvcLbd4FSiZIQZ2AIMRmwdJ0hnCs9RXmYHJ41un9Ui4lz7pPrhYTG+5tjGIA9JfwRm\nspOO2L36wQcUuZHdvo0rwoHgLqVUHO3h0FL/yNEwBgFbpCvrzd3Exdb6f6GEaIklZlebIjuF570g\niDmTBWWaG3/MHY1fAbjqfU0XLdZAH7tEl6kzfz4fO0is3Lkm5NooxRDBQiVlOcSVLy2SXRujkly8\n0RLn50A+XRiH9/9hvrMxT4HsLvCawIt/c6ymk17DfJrGNCz2WgF12RzWxR/T7M3R4j7bfkS5GQkG\nfuEVKPlWq79mc0FcltwwZ+XA0j6RrYW8SXa/hfJwrIDw1f23hUPpYEEgX7YK+tSFFFD6eA0wtbKH\nDS3TsoSGLbMAooSuHIQ58sr1rojxg+cJ+y+mu7mIjPoJSyHq07Kws1bdylX8jOGhz92ftuJc10ic\nSVtnCxag1wLoLoS03T+ibSZ6v5MtOIsb7jzLBWWMAN63tSOjbnpKffdOVO2qnTjxWvOkQRvMAh3f\nl78YBgyyzhEw2TBJJXsNDISbKqe3L2aL5q9q6Uop/5kG+coDxwoKEOni8bTWuHDEXCIBzs10V7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QQ5u8fdckcHh484JO+OD5JXAjeMAyWKvNWp+dOPDpt1TPPHl27k6FPdFVTZcst6i\nLDniiX4HJYXroT7D9vYWwArypAxRMCkob0PXd5kvtdY2VkcqwkZAwqwu+0U1ONBqxeLtvil0NXK4\n867XxQdLnVxC/ax+ENOLoIG0CRhP6CJS9E6Zcv3tiHQdrqDWdsNYDnuvEVs2Tglp4JbY7Or6quOe\nWgYABVTmwUOJkjCWjAKWf2T2+UMODkTHlGmT59nQIdIkU2B2PL3Op5IPDIQGVmayOmZod/ybIutQ\n8QvBPEWLidYmKIDRB9AcUTSd5/OSfPuzKaS4mRg/Sy/K7xx66JxNXau747+wwXlJj0Jj7ObPA+Ch\n2KidAx2oJQgMj7Kd1s/e+PdQ6ag/OgBtuV3CTOzTDOwcTIvf1VRUDGrTRVjPAVjm7RxsoXQHB8P+\nTyAcj7od26aaqIZROXMLKhyYCvu55ESx/974rFWjtOu2u6jeXeWR+6rmVIWNb7rv6kJLQM+7Fnax\nc2ZzqVjOAEjiMbkpWsP+KSQ1eBSqq6lrdM/ZAVu4pph7A7vmTRxEFvqy1Ue/JIFEFKN27FaqRkDr\nvP0uhcZeXP+erBdsQdo8eLPS243I3Ml8axS8zjpcS8xXqknascrws77dLtuU488T0TL+PGojWRgt\n7SnJoLEXwXZQM37TwDH70sUXoWh0NrcyoCLSveYkbvAGfBpe5lu4zSdV/fyuSiaHn59scICPACD/\n/343VXearCtLvU9+aZMEiwy/gBmoaL68/f8wpsW2Il3I4nq3BNddZZNzarPNffUjZbYPGdXHFekf\nIUyDysgvh6V9NYJfWkN+BhUubKI6cQWCRqxO2IzCLeLYeRj3OOqXf4Ixu1I3B6vxOmwSv6eDWyLF\nVyILPRqstDQFlZshH7yIrWvG4I1KHXYVe7novipDwfKpHRAvBnv8/OD2PHG+oXE1sSB6g7Zo8yE3\nCUUF6muW0EYjCnIvJsVkkbKkSx9awIG4kY/i3NZ/eMRCk1KPxji2iUNL5HRYjAFrmDyOV/AnxrMn\nqXEbVNxvhFt1giMHZ5Cg26/fwxgzhTuZGRYGjxT8ZwzRJk5V1sCHUaZmmOWiMjLDltXFWp8LoMRq\n9lryZlRrzfMO2kUf9Vrio9HUYlxjkWkcoJ49SmVVLI/++47ybENMAMGfsfYl5GfhCwF99bRMsVFs\nmhHu8YV8Q9yaKeiuibm0mIWTZ+bpHkUVoXIVieHRVqwlSKXfIfhn8B+ZnVIQXcWUOVW7YxsoSV6J\nn3nqMk0fVEgIx0LSefe0uHrIgiIEynz8icSApGGOp1pdUEp+u7lHMxRXlPm6iHRKroR7GBZMtN/m\ngOAxCcREEi/R879QAelCOEOiX9+3y6obtj849d2PCRLEJp3zh1PP/72aZysvm4lM3SveAVHJDdCx\nCg63p2kn/BwkuQPtWdzTAEWfoZs+X9oO5zYeSJB/8k2x/pmj7Gv4PlvE3IhwkJGkm6K/xHDbiBm0\n5VEpBKSFuZ6PTKciVXBNhUTCGBBG3Cm0eo0SbljExlfWiBzI7ZDMSJjbrsx5IbgvZZ80kmMF3Q0n\ndoLFEe9Tcey3Z19NBCU3UYIlg1Z6sKNBc30N4/qGxnM8/myRb3/I58ErBAju0ExIxF3S/3qxX1Se\nhl1hw7mYnhywHwFrSVJ+bpHSQrQrDjXx9RqbP3MJrlShC7H7SsM9A++FjRYOlUTdBhm/4t98uN0P\nLjHFJw6tjJlfOe9HMOKEIU2fdwp0uO1/EiioM3W0sgzHmUQx9ecq9UH4xVTO8f45THfA0GRBIUn9\nscuc4I+jtdX/LQ0tkX04ak/VsOXt03Q/JxwmXvtPyS3Rl6P1P3CqBwt6Oe/PI47jVQoMuxdlil0u\nR0uzuwyxtlAGSw5PgPw3bDa0Ff4La7N4uePsH2RKauR17XJFLraC+7pZzylY/QeU/uMKWf7PKn8g\naq7S1e4WHiY8/Sew+DTpTYCydkxWbn5nnYnuBwewiHUFztkJu3c=\n`pragma protect end_protected\n", "num_lines": 302}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nReplC5Ahoe/ekHadJrZrmcxktMbPXmgewEOVkFltxDCtp7tjIROEjR2J0SX8SJSOj28503HOqCPD\n5HwauVkxEw==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\ndq0jjzDFNxyZLuCz/pQfvevO7zrYA9e/RXFtC0zs9vJkavN7vpFs4dWp1T45tmALQCanKasqmhhA\nbRrgjw4a32LZXERx90Sp9x8VBmLXOfw9Xg/LRBctRS+xLJvPuQPnD61fU2yD+DHHuAh4V7z97iBY\nW3qQSUzTTNMN1JprB7Q=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfslYTuc1ifY4iZRomp+98coaTdM+sERsLRzARKGgfhdyl4ejm0X1439hhlJZ7d7tGRtc9wOwzpsg\n/BjAHfhI0GN98FPbTMXmwIVZ4xb8F6OfUvJz71o+5oFDkZBQA5t9GaBxUno9++/GrhnRLkDhBhE6\nqqZtEGogfxjP7u3D1TCkD57v8OrsqHuuLKBzwJzuoxeo8w98GmBS0W1HbRoWI1ihFZb8bi6u07hw\n6G/59mB0i1MeTrA/nlfp4ZqwFcMwUkVv7BNdFPdniOghdGRFQwXzx6glpgnvSkzxIUcz9YddAzDR\nz9lTjMsWZaJg/1VTBaZLzzRjVS4NidlGCWcAtQ==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nNuhRHq63Nn7DJ7N9KmLTkmFO/pzyN322hkWuLK9DFqmNH1Sh/KUkgVIzA4YEJIlgTsfdGyxmXhIz\nye2BkQBEOyNZ9V8Yy0f0wvu/732rGkqabthdyRagbuLIY+po+fNOV3Mh+L2sobV0cCL9+FkFM9WG\nudMRIHdqJoU5F1Uyivp9XQ5p1DqVBUEeKGqb4oI5hyk7rgBR/wdsMmZaySBunPsOQOM+GCZmCwia\nOxj7Y7YMR/AuildHo/MG6rH7+TPk72luhTUoxeUU4RFZ+OBOXVV8A746tcjYIW954lHFuz1lOjyX\n6s/E2ZGSB1daVYsVGbXZCDGXztOubhxgABsydw==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nQ+3bSvkzpWqHz+Js8pO2JND+aLH8PVPx7Ga566/XW/zU52UJgqgvgfPO06Rxm0MrzgGVOeqcgfjk\nl8f8T74yQPJFxYE97dwn6Ek9c/4P015WcEt3HbSC2NgCSmyf6Fk4N4oPC6TDJ0KdzaunhIg/uT+M\nVNWRiEQq4BZ2NwoyIQg=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nKA+Enx0zxUaNQLmFOIuxV6NZpy5a6Hxgt6WW0NNg9/X6V6LK2SDqokbj3Y94Ev+d+qhLiOhG46Pt\nYdBx1YsEGgnXq9yoAf5eTiIZ0pbsxXvuh+v7YNLrVKsfNOTds0cDPcKfUIP8DTK2xNkgnlDRwXRZ\nbKquTuXNS5VL7rAeehT5VDDQmEkchpOsvfMZJh64nsWjV0Jw9Pd9l7GLuLK6FpAX8UFdoIV6Aq7J\nLzWlDwrKxbpeRz+KN3PyqsAAMIJ7xGaNHyPcGgYdeGqw6Y1OGYPhl+r0a7Rw5wZV+TAdgvDlqs0k\nHsWo+wgX0B9Jelrlwtkvf2GAQqWbLnOHJBSnag==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\naey/uF+AZUbOHsLVgq2yoW++LygRP1Vg+GXLrXqJeFzf1kNoqXKfMmZrr6DoVtdrKYjYJY/4phwJ\nx6NUIOO+ZQKagJunMRjq4qbAwGbdQw+1XgVGc39UoYm2j68ZVloHkU6g31JOErPBOLipxXru1NOM\nbYHk6hX3yCAMag8cPPtYksM2IgSUMKyF2BvLEcSY+j39CKMZ8W29pswu1O/IttaTmrZg0/AHW3SI\nz+L4nEJ/PL9raatcU1EfLGc099QF6JRJ3TqLL54a0dSJhhkRDSBS25Eht06P7uZJJSrrQ++fS9C9\nufKM73pD99Q5rIACsX+NQnZjsU83743A7FPGyg==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nXlLvtlTSSF8sH+XfrSClMgxkHY98hTFFc0DfYcUZStFT6OX+TcKGYnahL6GaeVbR6KRu1l3MH+Qf\nNDhEuzz5kIqW0tm1tK1YhKnOYisr/bS+V0CRsII4wrWg58kws17hF/r0yKdFf4bwt4c6y24h1mC8\nISdrxHZC5OqMjzEWUD8j7+Fvew5PPt6grZV7ZiuDXkDcPhtSCqsckTGVdIv33bQNrkaTbRVmkRX5\ni7RUiBWd7bTvtedYFq4fsKOvOs+58u3isvemYL+GdrsXg2rUc8W831Y6erY4tiGWaosrxd8JGkTY\n571QUO48QJbtifeSvfEFj/kAdp9w6JzGqAW81Q==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nGurT/+cXPnDploCER5sXenqGF2E/6XdlV1uohiMfTt+RD3ORIPtULbgYMgE0zAH0FZNWAeecY2mq\ni5jQhq64mRQZBmUrwq2MV3chNXYs5uWtowtSRLvTeU8bJFoUlBaLACw4A55OW9IC7dFhUwt5AkUj\nzOTNpUTxfbRdVlU+3UaIVos8qq5kOOrGSTcH1WsntkO07bNmD3j9jvKJIETKjO2tWEo6wLhFkmau\nv2zJMitY6QD++SRwNV6dDA/jI8EDOz+Jx+SfGauVRnRgBGznV80pjt/6MpYts6WVHTdvvsBhZFlx\nsAUEosByPj92SgAWwCJMqXWMLQb7Q+QArt1PNQ==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 281264)\n`pragma protect data_block\n/GT65feKxOxX3rp61AY7iXHp/L5e58ZqLm/cTFXpb2NvXXVNxItFTykMUbkPkGUYoWm51UAlkE1E\nztNoFa3ObnjNvEq2qCOqN2eKDhMt29cy43NY3QwpKJF4tVFQ3QE354I22HWf9+Uro1icahnjDhhI\n8XnSv/QcqRPW3frCqbdomSgyLTQrFzDt1RJ7y77Bv3gNI45zUpMYFzgPW33wg+jQvO9vud9YkWEo\n5EEWbM2eKEMRexTosfEOkDNK0wzVbKyoQsJJ3+8ryXZ6+Nvyqhd0voC+ozAhRWa3DCKeMIvqWfK0\nESKtQAJ1yVPqZh6ca9byV2dAw3MmcnvjTQXanyTKOBGhvtpgCYebCFC64n+G0Jz5wCJVGJ3jAMY2\nmTyNdzgomt4DcvRvwsYXIox9NBkToHGRtcuOB1OhLbSGGAaC2NLXUpuOOVgr8kFRx5bG38eKZyxB\nfYMMOjzNGgooeGpJ7KAPGRsSU8M4zU5ZWvZX44kqkOpl+2F2oHsHjtKR3YRmtyiX1LbArT/L+5wv\nRtJ9eaKwDXqVrKUO/GIS3wPGwf8qYgtDK4nnFVw/8Vl4yW8QD7ySZxV01EFS4mrA7LmHIhHzy2i7\nO8au3Omp6URoWNM73VkKZb3jmw00b2E+32UVir64Dwx8blgfS7r4r9kzuD64EYfa0MPuX5cV3MhT\niYPhMN38LV56wA1ge6xbvWDrtDQ0KGF+Ou/TM/4FdK54ZgLQEfxNTY2pZ3DfaFD0s0N1/qQw5QD2\ntSc4QKIGT56IYiq49VUW1VxozXPw9vgN9hX8Z2ImYmnqs5nXfe/OBxz+2AGeLdi6GdTZr8tGBkN2\nFgXPRe0jlF7+CLFy7o77ZEz0yiraQRmt7JT0ldrlR9nygVCJeUn7v3sPuvvLaGdUU7nnCXY6KOQy\naW4ZUEPEdLTEFr1wq0R7F4RrEoFpeO4OMMBF93pLByQBo+ZkrK6KfhQavQNRgrvLWQJGzdHfZEJR\nqwqsj60DPem9ql+KfMHrx2q7ZtCqDOkROou9MNa8B3NqRoTOxO1QTnWO6zKht8TTU5lp0XNnCKGg\nplW5LtZIWmX707lerOpcVntZ3+nPQysZ1cA0WmiaRShJ+ev7bnZa4hEbsY+fV26P7uejbxBMbfIj\nQej0fbbKNcoAJXM/j7vXaJG7vZwjMF2qo4Cf1/rGItyAoWSIaOW7wG1HBdTnTb3Nafo62/PsBbcT\n5i8vu02ncrpBQNmo0C5rQwKhfbHJz15IZgEoRmPPtMgL9GbL+BfuI0LiFS6ALl8+B2/tXkccek6H\nlOA7TIqGDVo9voJQoyyVNjHFpbCM4naTa3LHNlb0hlV2EFsJ+VvvmbIHqPgW6YvE/i9v5vxyjon2\nMa8xloQ9B0mnKwdBZVJgtcmRRjKuSJQPV5nxxv8jcop7GeyEIwDZHTbpqdF6m9O03zzQ80PwYjvp\nQCeUkPBALgdfaNZLdIyFGR+4XQWFc5pxMzQRpNa5fscPBrtpoqB4EBQNoywtvx3lIbojhZYY36uY\ngJOhK+yMYIZng9tT9t0x5MkShaAutQ+biW28DuTV5xdHyHYlBzyxyAHMUgFhIgUZltyR5RSAB5Sy\nB/v70qImq11HfnIWWWu/VY3XMmrqicGqWPeE8KmbJ+vjb3XRV58KcrcuXwSeBuxBUhHNw1a0dsTg\nrao+VQWsii+rK1qxkPjHm+2yIIf7f7u1JN1d8jsrdTFmLNugQxicB9/tG1mUdhB3dSPYVJEffWMZ\nxFg5ZJaldi3GKyLdSqy+AZiv498C7hFbiVG30trGS/9gnquErKWZaXC7F/XecNRI1lpyyZBXhNKc\nbhCrOA0HCrFXBKfeSNf8d7/8WTsD8aGs+tLOGvJhxMgIjRNtOdVjQHQMeB8wN83b6RtUvuZ4GGNX\ns4NHPKmUwalCDUC+zsMOuvyX1cJ8sQPnARXaLpiwyZN9JCMStkbO7vHfv0SBaqBaCCYg1vj4B9PA\nsJebhBEGaweDrxPTfL408ppDdbt2qtNfJrcvuVPTZCLEyFQFyc9kml5KpOpmnjxHyNHVknHF8QvX\n6NS01vYaiwcb2VehoY4DsGw8FvXw4qzdiaKvL3kizDdaUlfoye0FvYLBGQycamkXxlDImGIuKc2F\no8WIu3Ke3QXEWieaArc48gC3aN5NjX0HkCWksgIs876qal5Wsd8an/4FIXnQLoiJhLcMMMmaq6Iv\nTh4EKFu/C3c6VHnKys17pN84kfnAWJaOLjrlQ05P3SCGbXvcKLiOqzfeTcjrxXkBZ5o7hYNIX7bg\n8d0VbD/cL3wnTkJM0Esu08folZa75Rx7/ThO5ah56TlM81l2PO9uxBhP79aTKbm6JWvijfuftro0\nvyugonR4SCzahRyPryk4CdUKGDjJRx+OU5D2+3OUXJcpMOZPds0PbCu++KEa9jU+bkVHz7nUqI8o\nHMOYDVehCRtcOXwCnPQv+tcf3wZq2XRmuGwoRAppQBS+zSonAZ3oWL4pRvbxSk4v7tgZ+QA9eGJP\nLKq+T3Dm9T4nmm/Vgc2MimrdrtILMHkFOJqIeLE0s5+eBqINHKqeXT7AfReRbjiPhzIlFkaQDH3A\nK98HUfoPAU2dhzQb9QazlNZq3vFm1JjTsEQrvTA/+z2NO+MSyqo3dwcs6eM6qDDC3FH3P6ieTkUS\nY4W3/78oRUM66VWTQnPXGTd/2rj6Bwwfoc6W29vXzum3RJNSCCzZu8OMSp3HN3Yi61xDOM4i9wYm\nvwDYszZz+KG4ajBFMb6ZI1mcw9+D0L9Sgd/3g8cu38GMDk90TwjNPbY94t60R1ye/oN01kG79O6H\n6fFarapEuwFDU+zU2xyohe4LbsJAUzWQbuf2Ak+vQ4iltv+CbT0Q/YJgqt/gtimQknDYJqlRwfbz\nuNtTJib5rGSsMGbjyNrLVpsKgUJVP8O0kPFGqJ2OOOSrYVC67Iyaoe0hcMKF7Yi33f3xn2UdOvCe\nBNlABzkyQm15OxaxlWLiLF/ccVp5LmZGNR1MfeiXO/iTEhsrRNDvb+J6Qq0+cR5KLIAr1de9FEBD\nWh1GWjm9hUFoJSUNUY4u9P4n2X6pt5lqCOqtYjdvEW/BOmR29Qus6ZOOrtjefYWBjKQ2ZjxMo5RQ\nLLb0K/vjbAiQlxg3c8Q4Axb2TZM7tZcjILwTP6t9CBvlDSpoTMDOJwYAaSRjetV/GTsuf8sccMKO\n7d2lbsx76F5N7+qi2UJMhEio5SFCIm0N4bDiz/D3sC8UcraAC2jKLdrJKowNkERNC3ndHSP7YnHP\n4QaHL8hJhyAOhpXkgD1jKpnN040bkBsFX9/hdkBGQbbMqhDHBCG7uENkn9RZTfLPv/qYGUnqlqco\nf5AA9FzjzmnJAnB37l0WlFkIbWhaOB5p6fPK5cBjo05tiCEBsKV2tosDGc9X78aJVb9CvKuKYdUf\nJPA5bdLrA6SVFwIe+8AH+GZTIQjgh+OnC5bo1cQ5XCvBkrMSVpL9HN+SxnanseFuE8fW4kYefquv\nZTAnE49TiCJPGZhEeB2NM8l6rVJjM/HGZT9FPavjf6cVAScbb0XfeSDX4TD9x0WQOOz89mUaXAb+\nSa5uJdIjJefwBk3pLjTQlsu/6h1hqxu6Od+Tmc8b4rQ7uW+yHwWVnt+jG+GQzqcV/rXK9II//zx4\nzzFR5JvYoZ1YK2VrN7xcI1tsbP8jlaPwHeH9GKfLCJkieZBrwUVx9qMAiepPHp1nZZeySc36m51D\n5IJJ20nC/bXGRsFwKSc1J5TdP9mqruxlS3ZSVKitje1wPhdFUE0mPFTXr+PvPPx9s9tusgTmmOjN\nRekzNzMDVHPxNGwVk2sHWDhNnmu8saetQgZFVF6WxJsvEDG9GNvRohRTurxc6wxbA5bZzk7dElyN\n0NmQCGORMGgk7toTCik8IZNkLpye4mdo1MDoQOpiCAYNUlPKv+ezXvHKphSkFS81ELrEqThrRaTn\nkCvgWCUUi1QQYqGZsKQJHqTs/Yn4Qb9W5SHb/fw8z1tqCMDt+GJiL8AUWi4xiGgovkpl/NWmUtyO\nfCUHDfcwNDOsE2i3NvuDQdIpS54zDqK+HHP2KhBf26jCqFMDUsLXlQLYUizeadZ8WWzbShRmZB9C\n8zDJha/GJjwdx8cVXCg6M3QTpOEOt30i0CpdWvecGPFy2rjhByMP7WD2zXtZkrptx6UstllQq5W5\nxlgu28JJXdC5nTCy6PPZNeXf8nNc9QvjHi/t2/u+7zGXKiwSfOYkDolMCnFqdpPwwfnVz3J4hqo6\nyCZDl7zPLIIknVS8qsfpKxe/jKtJZ0m4tHcaUhhL966KKpykL9Hn3oc4oIxuC8Ee6OISIdpMUOsv\nvYO0o/IyKBUO29KnX//HrcOqKtNtQABx5zOqMf+NEIu7A+McH4+jyU3S4PWv+SH/ZBfiGeF1777/\nCzC30665FhcsDMwmZhqFbFfx1RW1IuAk1u6kg8BOUfDZHJG5N0hPh31PgIInK1V1WEvvJfe93VMO\nqUkLtkvlLs6Lw52HfE8nbZmH6dJZkisuiNRDt1Ea4UGxOQipm/4nN3uIYl2ilIJDOL1RUIRtTgDg\nfKDHoBJMplV3idKB6gmCRGs7Jg2u4555F3t3al4+qb6I8CLp3zP7GoRqAWwlBrZ97UkpDucGl5gz\nGtd7sgaKrA1oA28lDu6PDuRpJyOttCntHnMBjEeBDYgzz8P0kJezEyw4NnZhoTRYWa2EbPodiEsC\ndGuu/j4Rhu1KDGu3uNz3X0GhCD6CCtt1Kj07+SzhdNIR8c+hfCij1zswF0gV1tuDfNKLH+aVWJxv\nCes4BSaOytIId2zG+n9s+Bu4Q5Zaew5FSAhf/boymI90MbcNjrsCJdgDRV7roaYAp3V4XKNKMi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luToDPakM+pkiAUpRTpw00ODwHN7VUgbqd2KS2PinJlzcVUEjdgRNUmE2N9R+6nUbPBDLOVq\nFBl+C4MwaeVLJetwhIYaBFv42X8LX1ZBfHzWRl5i8luN+GaBdp2j0WvFshIBwTVYMKuYx0cpM+Ui\ndFX+1u7Eky7eYn5QriE9kveZs3kD/p+4667p+AFrJOMgLECP1aYojCTu17POHPl4MgHPZGNbNKZ9\nORHVFza0jbPzSTLN34HUHOB1DUi/dt7xmyMnJ1X+H8wHTQg5zsFjI7sKAFaDS5b9wMZsGuab9LSA\nJraXEcoAV66/T8RCFZIYsFyTXFMahApL92O5zc9WhWzq8sUxXhaZSJWgvS2Em0wgCr2+f524E3Sl\ngBjuxc/5yHLmc0KVWRmWjupJSP8EXV7B5u5Aqgfqx/gmpHdwgfdGAuEvqsvpV7h67rRGmYpyKGqc\nGr0uZbKIfYT1uPXfZ+1sYY/h7HwrLx1Yjff4gPoWVQZFQx6856YAHwnz6Xx7yXCmdXFt7VWu6oNw\nIUtwu4Joepq4zpMQkuxdeakEXX4mQ2VE8OS84a7k7XY7MI3go/O8cxJJCWLOSzyqARQ3ArhXyq8O\naOL0BzFXr9ntoXls4mzT9wzhUIFIb8Jvxj1aL3ZhLFgI07VZK5kJpb1w0rABgxPBwaDIiGdYGPE1\nujAXIkSG6P41/HRUoc3rpTmx+tGolPCuiMzhW4VlBpUPNoh3UVYrjvP8NF1t6klzHrHmY1enkPj1\nV9KPeKSuEAnfPQdQsvUkeaq7+dnK2I45ow8H6N/U9mGeC3kU0BAfjTz7YV7qEVzCD97s8XuqFuRB\nH7b+A5ZlV3hyZke07QubGLTsus+RJ8INlZXhEYVfkstfuObflsYaxPIBJY5gej7voejrRIer620z\nshvAvTWl4oiPt/5X3cIPGK0lrcTr1CML+PUa2rQyTpIBbD6nTjVErPFDgxgt2zkwH5hNUPWyVIG6\nS/8CDDlDyaXQMNMHhTh99bQ0S4sU//5yfvZVCfm5h+v/pMi7jwjnAQ3tEE5UwDHLq4uYzD2yRdCO\nYhFEIqJO67JADW0Ta8wOivnvrIDvae5jdV9gvoYu5PSF52hghBTQlOxQH7j1IYKU+727aRPiieCj\nfr5VQcXlq9bmoTbjy794GlUh9d7pbpZCHi37lOOXD2PoW3QT202ftf2op/05dk9p0vKQID868FWM\nl7RNDsPjKwz0zzUdl/0t131M6Nv4wOeM0t32xMrG/n6DdhqlUCuPIElWoJtkeSUf/ibMNj+2KAKs\nURiPwcBehSC9eKdBwU6H9DEJ/pBYCRVM+ao0zs/g7LpDiBIRdjGZQbYM/izWr5L6651ruHxq8Am3\nEc3s139OXALgsi4Cy8+2itgjBKGmEXDDI8Dd0DRfikK7yPavpg/lefeWTZJFUP9hjkZbPMF0QgAv\nukU3MafILjGTeCXSEE2rbrejgktIWI4gQQWcqJYtF1hPenVsmMXzulVgKzpIqLD51JEyQxooRNxL\nOHGxyGvJGMt1eCSrnBPKXV0EkBHNOfCy0rjBq6MiUdAXt7jSZJkpLJuLMtpL51LtroHEQxh04I3d\nazDYNEBag5Kg11AvCs0BoqxTJ5RBEYkA4FOf6/9nJjlY5DaeG7ITrCZ22rzDDZ4Fa3l5bMRnuFWa\nBuG/ie57SrTSqcOyOGQl0/WWu7+fddpNgkH4ol96np/Oh4EwdCAzQYqO7mlqnoU/lH90mgaWTeQl\nBPINMJWz51l8Az1R3P4Ji6jwv5G+O2OkEEBqA9M1r3YFxqwLDzXVZgmfe+yTgmOPnMx1+MGD0yX/\n2evK3UlMtC9YWH1iOV5+kaxrWzHWlVcnA5HyCGkaU7HDBp8SQqmOEccpDNOnN7OVzjEjdjusJ4iy\nd1vrFj8L3qzkaefp7q2mK8thvbtVXj3nq2y6G/YkF+76LKknDRAm8LERfkGZgXTp/9mO10qmx0B8\nHdKbQMmrdDh4nyfkqdOpnzKxxw1xFDgYuaOTkA8S6aZFNfsqEyZXeWfAbNENZUkIUSeMpMD6RsFf\nKfxZNpiWNaK0WOaeAc1AyGRTXVh7WPEje4XFKOG9NuG3Tfp+tViDq2b0Ds3rnPiwfGV3PhBOR7WE\ndm+2waGFPd/GJzMUG9w3BWQc9DrCdb7Xp8hCZlBfXeCI5aJqDDBjeDp7+dlTUKXreFGcH0fXPL+N\n4/cDVZe3DTQJDQsropuwPjDkS5WMvJ1dfHjxS9Tgqto0mezS8dtcQd2vc9f3xHVB2XSKQKPJ2Obk\nZStJ4oEQQpoStW70MQtPD+06gCKNgFQyddB0ag0exLGLuct840duweSbxfJToNzFTWQf15uDT+k2\nvLNlspUivGYn/WrTqZuZEOAAkoU9GYulE9eAmJg59Nir/62WmMnEufjE5JleV2P/zOJrJTmSu3kF\nIlMN5YMgioGIYj46iQYX3FNg8sg4fQB9FuCmkTmHzHVgoppUi639LOHnGLhb0UW44Pgo8oGaHXes\n8LHfgf4vf0sC42rQ46PBJx7Y6JANv4ONmYoYDI2TGIBEmxXbUUlaCuQ/HpGQSPZUaShRauBf0KDg\nSjKPy3sa6LIcxfgficC7xKWLRI2M2VD0kHAhiMZqHE1KD/bohOt24wLmlm/bt0Ktfvz6OYQ7dC8O\ndELVZBBwXOXIHk5QLCiKS6AQEFVoGVLfGLKZPskMSQdpQpQeI82rqz8IR050b+imt3+87Jyc/2il\niYFroWctNAkC9GiBlyF6wVS0jtxe0P57uVrKgcTce+5aszlKT/yJ36NwLfQg6WrS064ZXRkJMfOe\nDSgdsCWJDBJqp/6KJhHRNePfB6d47AAqYx76z7db1+t3vZ0WjsRbWPcZ2I/fYv1yd1bmICVVE0KV\nY74bAY3llXsNBwra8TjTAU7pFIJD1xw5ApZkPLOjdtR7vgGvATjABslEkEh8kqky+V4KU2Cjkoih\nEcTFP/z+SwmZG91LLtY1G7kBcTe6SK2mGQrx5Cu2Onhe3WpGqJsMh8sI9GS7Qq12BliWwOF2iiUK\nMRAUIuOFL6qL843w9IcpJaVr1Q+RUrDa8Pr4nnalJmgzSbeqvj+MYRPEZNgvEgNvF3hCLbAzjN3U\n34r/Go1V7Dm/LhHtstfueNZPR8AaCklTBn/xLp6oKQdrbF2SgG03Qrb1y9lFxp2V/TghksDiMOhj\nIT1FPCBzjrIBMxUM3bcIV/m/WGpTZLTZBTihMTzwEHka/raeOx+k9tf1GTIhqmLsrGdE/Tw9+Tr0\nYunM9gzEk8az8gbY58Eym8SgBXvHY+JWrjYzvEpJH9NuXDI2vm3aSihiC/Cc6Eg0cNXBXPUq/Ffp\nW+gD8ywxf3huRG6CeFsjwwdPq65ms1VDIuly7b0zjbeMN8rbYxvyQGW3UfMrgijNLJK1Q9SM0LUv\n9X1gkqYBn5kdLC6glQOUuigHEpvmKvAOouSMH37PL9SHBirYMn2Cm4Ydh+pt4BphH/Nu6/tjIvCA\nrY7wvWp+m1R5Bm19rgjFxM6GbLtX8vXe4qPsZjiPreCwh7BnfLiZ0T0K7Ag+ktxIOVMaOh5AN8dF\nK3jPRHQg7YKVOZSW1UwGdLL9o04SjGeXwVYHsh+dImEaRTAm/oRseOKfJ7N/ypBhi386sTNrSwc9\nidtN8u9P1Uz53++UZHga66pko9u/P5BiJcrFQAKinRLrsYA4pUSSFq8EBJAn72SmpDofZj72ERbL\n462tlN4DDrZYAMmDZnxZ98G3ZpuEa3PS8hzLG52j9Bjuhgv4VENXRJTFjFwJiMr6JduyGJ8aUshj\n96wwoXK77A/YcCod5iEha9Gb8XfN2dfllJfKqQHrn+/reosNJs37KdWpFt11K0ua0hTC29Lj5dnI\nA+1cZ5jO2hbTFC7ovhZEA0XoviCBVb8erKSsEG/jo/afu2mj4n7hidqibyKK7CoigXVNK0TmDXmh\nV0f0DY/q+yMRVyFEYFQXsPwon7sTvJXb6hpQn9B/DL17IubPlkHf7bq7Dmj/D89sqww1/vsQoAh4\niDj22NsSJsAZwtcekyCYjJxMdrBjgyTFyo6Uzey5lZ8MRA6ZAulbAy6B6ajFm6P0rmQaJ0TbaBtl\nVEjajUqe/1saQl/YoQKlsuzY2h3pnrq2UiuArHfzkA1zymeLwP8inkSwwRqbcDUT42xudIhh8oZL\nqG7jokBMTX1ex5XOvAUgFMaQgtfLjc06LEvcVZ91eF3SgUvlLtDt0E4N/zhU+jKmDcAQMAEdED9a\n57ao5dP1JiVGH5hul7TnPkUNaTd0FS9BiXzF+YAKoUqVVqWZKJh702uyDeGur5Z3KV0Q5QPq0VcH\nGJE+MVS5OgOZyJ5K1AWwbRkjHgII3S8RiKlJftospoRJsBnN9GT1Wup98FS8CXW10xosmFcQnibM\nxxbcP2E0Bslq7E5orVV/bALqXqYbZZ0/q/cBIAiwfJBLNAWfrZ7IYvyaILzHNrzhaMdE9m0nWrng\nUNllwqtqqUiEvC1IKq+IejaDkiDxwBi8xchO2V4ipgj2A5gLBdGbcFxALZfTNQoECU5tDghIhiEq\nwQofCEn6oRPA6GfaaPRickkr2I4RaVWInx1oX8pbcZJsuXbYr16PeA+hgPWfv0tt9SHDTQ9M4DUN\nOxb5cBdClQCXba060B/zihIeOPAzGgfwnA1J5XE8fbOSVr70nXsO0xin0FjmRlCNh/aQ7rvzNxHr\nE/L1kfx1wr9S2nePmLDr/LB7So9TCCcDkMmKy6SW1gafdX2v186LaW7jyBOd3PfQQ+XY4P/p18OV\nsihVtafLv8AN4TvDYMZbRvk31AcytGwE71E1YnK95lGT6h/Ljh9RhVlkwrz5CTUhXG+iglvQOuDo\n6jfyE2QjUzs/mQIltMOsEw/79ZiwXdTdOGrpX4ntXE2sF7khyXX4r2sSs5Eqsb2UcesrmnrKEh1k\nsNeRDR2b5bLg4kr2vFTRr0XMwBKIrDEiVa6vsJb1wmNThi+WDRCupnkJS7jOBlrY5YnJDB2NLDOh\n/wTYlnDx/o/XaEddYHXc6fTZPoEkCdD05Uk2wmQ+IhsVkQWjfIC4FCt27NUvtJI2LOpOF0z20zDL\n8I3d/cTxAOjL6KPgkDadeP3376LfMqkIyXz4zD6g3PW+PYcDcKc+hr2OTTvPaUEtlmdqbYaeD6PD\nHr8BQekTfHGds0NVtX7bZKHU6udbHkbXBl/lqTxG0mKpjMXZELsRf+miJDKPmHsOe7hnvdz870mz\niGz1ZDhTLvGWLCua5oQeidSUtcLgPVCGbx2UzXYXXGkKnPLG3DmMY7g/UoRrUntBbNHagWZnuSKG\nlbqbmeGKslTRQYDj7onTArfOa029SjIsSP+TeIgKps50vST4iGwe1eUZqRXjvygPKAVIsuqFJmmy\nCu39AFY4jzvuiqVE4WDOaGA9OER3H4q621jI61qewU6q1SY3xCwHH2zvYpGVXU+hZKPNf3djQ1OC\nrwEzUOjJ94K+om6dvaom+qmm+TEQe43gstvgIuU6bOHhQxyfrIrJ5tra7FhRNjPLV6f+jXudIUJ+\nFQnSkFs+xHrDHE4v906/KAmKQRjOGbVRjkMt8g+d9CGUUU4/o34eg7CiTP/B7PUJEyunYUSQNTj5\nJMMgqXbhi02r07ThVaxb5rFjk4pA4MWp4PXKYc3t+t0b7+IH9Hohy6elRdBVQiDSZVoBi4qy9uvS\nl3wDr2KKxd92eI3KmPgIHBOoMyzYcV0sH/JoI+qnBVZDw+PeL105l83k/oDR8bRiOZnhMVHT+e2x\nuXQWSqxlVbvDy0vTHqXrgRIMgN4ihXbcF+i9hOTFOZlubGrYiNI9/c3jm6aLhYELxwEb698WTKC8\nXfHEAYyEDYmoL9OHj/4TkaaQYxcMiIMHf11ay9L2MKUBVkDfCnubRXIQCqdmNC6PS0EfJ+bZhpFO\nxm88fXiuk2CUr9Z53g4y3KIY9gT/GKZKkipE/ycmD1Cp1rPfPpRSs3snunDlnIalSnTDZntRRBlh\nngL3Qbm3c9VF1gAXBBUyY9gOTim7utEcGP2R9jXFKFCXMgcZ/Ew6em84whpy7bp00rjocQpDIQMs\nhCh1g4rDHSnbAyUJpd+2azfyWYaVc/e7mqFdfUNoatacYn19uS88HrqmykfBmZKvKatkhE1ldvyG\nlduFQpJRGtVTghc8+Eraa8Mhg/qpokIU1NiwmUBczXzw0/pRBQpupNY/z2Xp6j78ZnNZtJe4/PPY\nYwqhO3QsgeIK5HVBu7N9ij7fwlcofzFig0IMw4dC7WR8kC1sTDejRJJuxWb+ThgJyKcHr6p3gWkx\nzesZWOUPLn5ypKA1MK2+vN8+9Zh5AQnrm5CIcf0QCnYqUFU9oLm/RXc2bJO5ZvYhd3K6vkuoUJPw\naYxfqY852SGhGhDgPDDkUt/EqHadmQmF7pP25eMDZcyRj6CUBL692f9eknVfDqkssa2dYcAINjiu\nFNRj6NLN8dvT+gWacueQwpnb6woXmfwtIc+0spLLpTzU40xIZ4yJMX7+mQ4h5tcLTodnybP4Myh6\noYyKqID6dR8TswoVKtkLdHemPUSE1MmZ5xgLwB5LFuBLS6Y7oC4iyJ+kKuWrBkh1+YASOYnk+Ovo\nfnZGT75HI8kNGa6XjH3quYicueyzlCrYLHb9ju4cee3wvcDvaTCNGPxsrFL9a7kfBgXP1yxn1Nxv\nQBkuvDnFcXmi/Xf+k3/JL2lTIp+ONtbnnkteX5AXXQMtw2SjqOqe/tcJl6LmYuLzxiS9ItOJBu6y\nGBm6Yntwf5VzH0uurbXlMkq3b0vmn6Xw/40GocyP4KKjXforr0XdyEEjF8SxzPuFtUaIXunt+MsI\nSEuf3X4XiOfLIR/t2g6tSWIRKyzyu2GfQoI6dG4ZQPMWH6zeAqoqnWHxmRMuKGLzL97vanDju/Mh\nA3jLB+J5+civ+iqS5XmKLA3YiAwOhQzCEme8HWGIp3TS0IQea2zYmaZSraMitmP34wPnRA40c0tS\n1qe3J1AP0c/SCMfznTQaMSaScIi0F2KD+rMEbYIUg0dit6X11Cjm5Fsls4ZF+GLFKo9RXM5654Tl\nJO2A3lgderrEBqw4ETCglD2uMSCcQIWYB7LTcKWxTTsDFwKQg3yp5rT5bY02kZV++3b9BEZ/8/VW\n2qNV8bkplbDabP8OsBsIMQHKGwixQ/O9s16KFoRKcf/1yiqAoaZNkv+7wNsAqfOit8z4r1SYIjy1\n/eB2VQ418eyjX3e/wAmrSPr1KvLQjNaPMZlLEDWPGT3cyEP//eG1u2Et51c/b6SdBdKm/UhZ8CTT\nSoR1IZUqd0uWuRP0xtuRqogKnmLR0Jt2w7ArnlJsid3qU2GHXN8HSPWpHKBqRnO4LDo7y5LVA975\nWohCmQXKbRH01hc6/hTYjJIiJ59k3wefVSuqS4M1SPMsxVB071AzNOKClZVoVMzH3CN+DURzeuoV\nTsWHKhjCTeoSZeRQ2mSCuYqRjkPkh9DsFmavLVzHJVsYOBWI6SsX3CMbdBSgMcHUQso+cMunYdns\ndX6vcufgvaB3slVLoCi3d8oC/U+1TGmstyVdf9oqwXOwuqG10BO7KJl6FiwaV+CpnNwOE+oas2+Q\ntVdzb/ukJqkXmlJol4RpXArqPf282c0U1EHMk2jX+tufH14FgpMi6M3kD+vx13UggIpktFk7L/Cq\nVsDdtHIHLTugAzRiBIzmz2k5goROsAFGYbylHkEkST8NrMPQ8uIdEsFhCl8aNYQIST3caOmhFJ5M\noyQTamCgg/jg6UEZ1yvnwDJMViB3RwfKJkerJ2i2kr2HAXTzD7x6Le7T2AUSECTDju0jHenNoHpb\n8+qO0g5+m8hzh+bO7lol9ow/I7hN+TetulB1StL4/YhydKNHWl8VO/X64obYrTnarA8apRr+yEtz\n3FTHdZPphOJNm0f97LGhfj9OhbvHXTimP5IOVng6CaUQGWCpjZ0qmyeyG5FC1sBxQ8AEK3y3GzYh\nkoY8OxjRB3EyhszyvgdWINhLO7qDTU5lNA3qzxn6OlNIbL0B5OwFGGcSz9GxBGEk93s6iUlUh1fw\nixzz3N3DgyFGrTHwM9BzC7DN8qdcbZ/Cp6LNOSsLzi6W6iu8kbBHQThTa5bs3acey9GMzNYDYNgv\n6Gs2WySCGRjsQP599tiOgNN1s2KLm5BnujouUtGkOMmjLDXxuQ3dw8zopRppCi/9IEuMMFocyGmU\nL9P3cXVqL2gG+Lhmb3m+tjmx0lNsgSTxCsa9MorWdwJ29EOLM5D3yQApo3Et0ffWwAOkCt5wi+lI\nhDpy5PKaOg+tTYTV3d/wM419FWRyFnIOWFOY1oQ0Xnz/DFPN2xHgXWRTswJXD7Z7Rgyq5lcSGNCX\nrJa5OJC8nJh94cd6zAg87XSy3djFnxRSNElpClgouOSHpE4XYbzBrVlwHkkcl7mHkX1c6XtclucC\nOnmUVUET8+d2Yp4xbvhCjs3QHiHOak+Op9qUKr2y7ymdwIsmlCiCTAN6aKrfJLC4zARxfpO7vwUe\nE11bUlC/SNBjWDrO9yXHnoapo63RtS53a8gH8f5sxhDvXvVdwfHINirgPrj3t7ncvZjXAi+Lr3Gz\ngKuD28IkxrjJJvT8QBdD36Q4rz+zUg4X7L6mkfCCyFPf/0DOUemUUt5oDOqKFJ9Mo+1Y+Av7H0UU\nhHNILEx6rJwHzlr9TmSYKDmWPQ590nwOAL6RM1izasSthQDjQVst8yHQiGI+J/rIzWlUPz6NSRYL\nhGjc4v/vISjzXEGvn6FQj/gyKp/zykoNsepYKMDFohxARcJ879mHx8omgjtQw88KAvXGQ8qiYfH5\n4Z+flOAXTFIMna0pjtfMx2zoizZrwPVSaVdu04WW28J3jAK0Iq2jjGDU4FBVcFJ/5bZad2Lw0Zov\nUS2v2Ra2L8clyRFnV/VQ5Ii2EovZtY+nmXtcOulJ9iTC1rFDYzM0S/IqI0S6pkZeoBxDE4NT2mfX\nX0TwqggMcg9KRiV1gn9VNIrXK7G9BEmzZp/g9aMmfJOCKNzOk10NaMftV+Syqygf99hM19ca/w2/\nfnq22+06eOw/i1CdKe0QIYxO2VM/+OyD/kYdGdkpZuMFxuqM3aIOTgMWKj/44ge7g595DfkSOkw1\nwZK9QzmunfIHdxIrlOkgB4IVIsI8J5TQaFInFhDuQNl8zZ+YxpwUfwPY/Kd+JTkl1w+QPpskNcHD\ncgooKWba8jp9pNlZCqCe8mHLN5UWQRIBOqJ6uvqzCay/orFn2sXbLuBA7zruL1MqrbGAvNKl2xTG\nKkIemiXtev4GvaIbTrn3WD6tnaMZ71wFzFyzxOL+97g4tu6/UnOiT8L61PSH7Mgd0cx6GFX+yqZW\nYluzCeaKcgo5MtiHn1RmPBXKzvXu0/gXN2gg7Jscnh9Pkjkkc5oEPwcHFE3lyIElFEiKDbYuENUn\nfJq4h7Yw1pkYwBrM/iyeRuwgIhM7Wcg3UpF4Vqwv75l/0JWI8PKR2Wk8AWA9kzTEabR58OVNoISu\nqZTw3HIV7lNmlBc6F/tKOV2z5dyFmYIa/dY+20dU1jrbngx6zfxvjrIOh5AWHEbUav1bOS4MgvQ5\nKwawYR9n9TxKLctB5gSjjEDYsmbMSn+FPYcxbrAleYz3gKjLerVfdjH8eTac9OViSQCmKdAn90gp\nRBAv1ehFWAbZ8IJn2BPUjXQow82GGJFBEnztOZFu4kWTAP3UXOvy85KWCuSn7cfxcajenW4W6iQ3\nreM8NKafNfMJaSSmHZKeLgAuCMAjB81zzmJ3DhGf39fFMXpR6NIj5dYVOKkzdrymeHpza0yA9mkw\n/834RAQJY0Ymv1ji889lg6v9Oo4614MlajyZB209dbcyIWOVRvCG1XRsdi4UXftCncJQF4GMPR5j\nrWpeAuBEXTMLaGdPoRKT2pdhHfYffK2Asr45URRAjxLL+fFU6i9nT0piglb4A8387mDIMN1sQj6W\nq82xCnQqUaYB4YijpVppinUcrBYjSlYRGvFShhNrIX4VWaRnHh/Ii7SgLmyAHBmxkb4sn4dlDWOe\n/SqxhQCAJfGrh7C2lXFXPaU01jnsLr5j4O0hErOOZHQktZUtA25Cm3SbOO3bQpHsBlWjwjgupWVX\nsSdIjKWEljbsXyksW6C9P4Kh1o7BffVrmmLsuwB7ENYhXao+q6BQM5kJXjzMerrW6C7XFoQZTYPT\nldFz+XoJtUAeXqwXw90pPwplXf5i5EVkrRb5KRrS77l5zLnEAybKFlu4zUXWjprf2WfL1FexA1ux\nEdqepv8RaWgX8P7YRfM+qiAnK2M1qSPHZFkYEbW6Vcvu2TUHOeUxpKMQaGqjsV8/uRNGct2YdjLL\nWoPCTKQtVOI5AasWy1M2/PmAiE4Q7ZkDqjCgq9F9sL68wenD+FPftOMMlfOUsDDTD7VJF9cMSjeq\nIYE55H7foUwobK3CNddhfC1unWPxSNoThZ5evGMgRN/AxD8lbX7FNd/W9d4a5hImon7MZqqBSMF+\nKIs4HzoVPYXI2UxWRom8Y6WmMnvuJ0lmGbRepjFRGtrv+Lp/tRfPKspKCadUFZiwTEdGzmZovXpf\noI0k9FTjcMFJiyKdwazwG+SR9kVNYfZcvKbbBtYswdillC0AGF7rTEEJTIkdWGSU6OP/msUceEx3\nXQvK0uV/u9U4KkAXl2FYZQJnnVSV16N0u7zTupLI2IWE47EbJRVAJC2P6P9upcho9yBGJ2nuRThi\nNQ8V+n8GV2jtxaCV2ykSZWkfGBM4AvLm7hDewit90SgPKMmPh2p8JgbO4D+3mPMFzwN1UH8vZRTZ\nWeCOp4BC+F4c08pJwbtzttN4J2ptlO+nVx9DNK9ZKvFo2bznGXgfmCU+EOyJHwbaEaiNeuHYVq8U\nNia/Pr6yGrs82FtyGvLM0TuOrTIqzId5hBnkQeF0q1J+fT+eDlI7jvzHKzzr288qyprEt0VVnZLs\n88lbq+27kdAFA2FTULRyd+bNo8fMW8/XxDKMC6at47xXqtrYy72XgeR9AT1XERw6FXr79+YCaG4S\n+e9aaN7OiHs9sAfmvan+UapK3eC9gePljOoT4iKRL1p4pFLWGDb1PPdhJyk5dl1gkrIDAEVT/31d\nCnfWO7bES/FfOk33WBX3MZiSeto6D5E0XSEE7Kcgpr+s3Y2N8kV93iVhAMFkyCd2EzmeQrsijoxK\nHJH+u8cKwhhon6npb9KUHSU4YhW2gwAGlnlPoV/oDRf3HW0SqTmzey16K+7B5tE4PY5GjzVAMq6g\njWcnOxER3muT6Rg5mt+bvsB1NuF6/OkiyyZyQZRqbigXjEkyxqMLDLYhDjGP30sC2yZy6mgUHRDG\ngH2pvDQ2o2YclDsZnQ1W1Xye5DDNuOXYCCi8kNMQAboZTHsu0INjPb1vSudnpY/hHGbK0oUiRhsb\n13LIKrPHxYBIBpWxy8RETVVl/DyvW32UH1VQ8ALvkFo3YlkmaI9+OYkPOBqPNapiARh1w3yzPDDA\ni1UAkTq79G1B+tMIOQH51kB3z7YywJm0tTFAkUHe9p3OpV5sS9b3wpP+OMCfnKo18sY+fQvXiSuP\nABaF7Y8GDHwgetiN8Z3s2xdRi4eA8NowaYJT8tZz4Ao53x914WHEiHT64+j0Yhr+KZ1xzXk0UCbf\nPC4YmQ4UvRUMf4oet+C+wkjsIZDp5bnes3Em3+BN9XNcfwwrqCioXJju+fT1+D/E013vau05kaJg\n9Lvj4McIp0tIO9GjsuuGvLuvaMV4Iu1/uGxSCVGg+7VeWb8EJvqEjm7S5c34ehC9GacusQKUhkFm\nuCnFie3Ji/vNL9OXWioCkpKpYG79oX8yRt7b7G4yKwGT2U5AT3PdOg6FmXjPdHtMjFbqWXtS91C7\nV/crqNDp0TXUQBFpPZ3YI6dEKa3aAXnCZT/gjnB8+WWh6moPPWMlYeFqHvVjnD4/EAfMssQFPTnX\nPV2HZLdcCWbRbUmOyDngSayJO0ad184rXhHDEf+qFsMSrsHRLRN3LnowC57YgnytEavASo4nhrlB\nAYGARHijl2CHGGwhuyjf1rUVKd21YCDiG8Ywvm0iSv9TT1GF2Sd3OdaQnfMz83ctwvDJhp2zrSmB\nv2hJjJWnbKUxHn2BHLt3Uv6LiSQ2Cx8S+ivo4Ogr8gtB/aa0JmtCAIV0N+WHNGTasOtpFatOJk1j\noWPec9XCKgi5uUGtFXgvnly5tLjW9hmBS3T7ngSdYZNUdCcPEz/ebfU1D6gqb0NPXFlc75vL+POx\nQ7RXD8X+CBTJseXUkJISRuJw1QOGHcNMPCBRJJ6m6KYbOCgTAzPGSQ/uLoNzDGtmKFyc3SEMRTwy\nKgx7yjgjp/ZOUQ/oVJzlHoAxUsBY+0Kv1pLaeF+W7P6vY4pMfS2iZUWgQUOHFtrhOtHKaEBgi5al\n6ahRYfYT2lcmaS7syQBnS09xQeLnZcM93QJIpgFt3pTcxzZG5Gws3yYEPzWk+SFFGd+RT1dXgNfm\nc5n/TPiKpufcBA+gNVjIRgHW6S45vdRZ8OFmsJYSvwglgcI4MhqOsUCEcxxettPGY/oJqI/dAA8z\n+WhM6f2nx29yzVn76PDItfWl6/zQJLoRXMmLqjtyXY9WmzJFA8kPUU3DlaMSSOqrPABVMOynsjkk\nT+fbpfXp5yaGrPoyux0VoFvTyCpuI7rW+PbLaieJoYwr9SqvZVqNEjbRt1QdPBn/Whwvo+2EhkrG\nRi90xuexWIdkDMwkJZJOFjF+pblk4zK6dNiZowcC+NfjGsY4plsNQTMLXCO5eBqjXw1PE0r/9brO\naMjs54Awh4K7xSBxKIUmKgomi8H6b4FDpdxA2F7mhR1h0beHRBzyeSi42OZkT9+lkbWnR2Mr+pMk\nasTe4QN50QYP1qmh7z8PYo85EyOMqLvkIJOH7qAbDWIlFJdKDfCFev9u5Me7IISmRuLRA9iHOtGd\nockkcdJgNo+OMYwvj89HSoxsaC178xAmVKRHy+DvOSf6ejrWf0m0YVKB2FxlxraW15gd4B7umdBc\nSogdhl4dl0+jsUNtlDYSMG/s32ahSDn1JtM1314msciCebnmHK6a+BqJ7scYMp/MUM6gfkQsELMw\nkC5sQFwC699Kpbiyp0n7RkiIFgFcxou10D4tp5o8YG/DgrFokng31PnYqCEnsTYP+GDt8l7D2vXj\n9hSLM4UU7RD88pFnChJIjIJ0B7f6MdgHbJPPuqBkYfTc6MMkLMXdCuuf/RS9M3EIb6sZpH9vvbRo\nJ2FfClTWP21lajcZ/cyCo2LE2RWTH1t4UMfEkBN9dO5kUt2DJ/q0IHb7Mt4buuDOUyfFyS7aQ44s\ncJq+lM1l9pgFq35i9Gv+IQoh8PBoHW9rRpWwANZ5K2P0uvRDmRjhy0OY9Bo7kx4CKEXeO7c9uv0E\neql1JXRp0Dx4+YdVPGoAMbVyVXMzOlY9v+/5LSCQoRIckyCJQggczsCvXDWJMUjvUfDQ1TbgY4a4\n7y0MS3nnstpgBQw+hrJ6Y9B2Jmjz6SGw/dCXWIiJOUf9RhSE7TEsmsYd3/OfAQVqvgH7fOkj/xEE\nPKy+7Jyt36eRFB/I9qHWQtBBzKw8uGJ1eoxerH/WT4Muza6pM/9VEoh5/W4LvxvRce93bLP98cIP\nscJ5B3Yr5YbRYupC81qKfcUoS3pM6zEsjAeUKI40POD7luUmpbga6o7eIMmhmIJ/mUEJ30WmnE2B\n9P7SDY/0IbAw08pkhAT/J0EBkO5V982OHIyiuJHixWmqVA6t5hmwPGT1Cgz7L7Ga4x8UgKFo3+rR\nnD89cfbQ99yRw8pY68992AgmWZ8FptoO0hq3zncbNhvOJYik3yZHNqOfsKsbHbntCkluFkiszxHn\nNF3zujN1sQ+Smid9rwbx03V5S3kAL9XXoRE4WDz5fy7zw8lII2KpuEup/yWDylkuDnEr34PltJNZ\n2y3rH0XqEyeHBLLo3rxU4XOSrJCX5O5x9d9sfObtmYYPsUfbr3u12qLkdQ+qgqf81L8yrJMukVks\n0oBjHM01Rb2uFsAU6Lj6PUcvAraYfkmYIv8YlUWpBkEMHlXH/UKZosavQfFHr6Ej4dVvpz/dVebM\n2umN0zP0Q6Rn8Une7kHyqPrt4LoUuXljPF6beTKdyeWyZFQquEZNoGUve3mqmD3qatLVl/u4QTb3\n+KAwM7VH3TcRtcIhOzrN5yAi56nU4km82enCr0s201o/NcV5BbC1tMtvHFR7SiNyAWln3UEooHBD\npW+X8xD8NE/zNl+pZuNZfw+5zt1lWYY0xhN+Jo0GDR+nfie9uM7NsX2xnvqBDJoUmTtmYSzBMawI\nkQqpbfPI/g2Wtb2YAqqBu/hkKImJbqn5ugDuZJ+oHHJkGc+XXNPVqWGd32iiEMCK8laW5tCi0B4J\nCElSsWpg4RbB9coxx0RcDx2Sqn1QYd2odQI9gL4u78g8hvwvTo/MqL0+yhwilnt86P6sZe+CreU5\n45iTqsWIKV4HXAuumo+fFLjvZscLwgSL+6mwPFbmEPsQtFBt4ZsZ/vYzrw3KVjks5BmlHkLfTGoF\ntDy0YsMq5+ViB0tlagkRtTjuKH+P3lJNdruyqExJZFyF9VuNaRM1rY2ZuM+EZz0HkUZ+NnKymxwc\n17lAiTQz5KpY0o4PlB04NtiH5l2ylNPzRmoWMooKPpm8d1OUL2E/Li98cx+IEqNGdOxcbzMsxecM\nla+HvNr2LcGw/k8zyUZjpEe+9Rbk/xARf/n9VcFmB6vd05jM33voRFRmDux/FoT7r0YHQQffUY/X\nI+pYf/lDfEpefGDTGoLvga5wljeWkfFPEguFgXwpWcr/xN34i/zlAfu4rAnvAtVvdTlWqEBlofXH\nJH8rEuN3q3IXkPr+QlwUBo6+f85rrJXpijRB+NDBbeAJbuOaF6Tvr4BNurv1DEr0LEMakxdmVM6B\nRzwDoP+75QwfLDR10Ie9kmRYMzZbG82hXpZ0zTzK2VVC4+egDzl1v2ZcKeaA9WFEvhNiePhPRrUH\nlRwYAvluOib/gOnGfJBDeWdEQ27l9kIaHGndN1JNTmKqQNK6yRcdHc7n4Kp6a6Y+dCzALyc+7//E\nfxbGkMWf/u2e5vGgfrWk3dUj7jGkHVO2gq/XYvheJ1/zBF3Q05E+wYgE1RsVp5BUreQHk0OijZeS\nEttXXdWTgy8wkvXJBlGzmCN9vtdMFQQONANlMboMlQSQWHKtDPSKoHr5FBKkjSAxk2kFKX9YruRk\nOjDX7AsA15TjnIF3lmJKJeyD2FxjQIcQGTDMJHEpGW0+Uqy4akDPVHS12Ha6g3glG2rB6U801ixc\nw6wXw5zBaTCsEEwk4ktdUDRETsc1fCq5QohGSuiDGOAGV/hvxSCDlrTZlP443PTNbwsi/UT7WYgg\n562rsFefdoX5yr7NFBWXyj0ykYgwf7M4q8Hu9Na6jLGQTQ0Ld9gIyBzV7nIIXYihbCJQrpT8AT4t\nexwHu/Q1Np52iga0p3MLL7/GHSif/kKSgtZwJ2I63iw6aLwcoB2bg+bGeXJNFqVcAS3J4Q+dcVY+\n7BVVYeIahrxUbRckCsWh415G70YPrSNYDNGmAOeKCnHK+r3L9Dp9BHjeHwqw3QbTKvat1GQcpy1O\n8jj0IxjzBQoM+tiCz1ZCOiqSaVGyDUAVjwVo8rYHWw4ZQYF7H090UhrCYdJvDpJ+xmALYs6Zb5lp\n851y6BfQRxH7uIX9h7qa7znHIrw9+q10SR8ZgaYU6LFp0GnWrFnLtDQBPkNTsBrn/tuRwVB9hdG3\n0fxGbjJt3VHLGqUHFThY/fjrvnjfPQ6UpDhijWgMz7CLV8edmMAg4u5kCP+fXviZSmwWMdwgHapV\n5F0Llsl338BDFiZy9kphbUNP1Wzaml4rNKpaMEWLXVlZNGNz/bZOyPUxOYa64hR4H8nRMykv/dvv\nNbP3tjUatK6j3U385MUNPcihPMud41a+QvENE4EBKV1XupP4BIzzsfITI3uj0Ptr61CRaj2i2zAI\nvyre/uewvDCoAlRRS7neCwhVZRSm2kOooti2vviYRuNcq7XDwe2LVa63QDbuqOZRZuC+1KxMyRx7\nVNKxpYW5yDm2JI027wRpXpyvSCwc+7/M77myzTaqSyPmaiN6oqAFJY8e7Q6SyX99eKTq9d08RbS1\n2HIRLozLfaSQ4AYIwargWEY7I8r+6HwKNAVWSmTDFUiSsSmSSoaeHtYVjYqBdeOSGyoy2evR9CCa\nyyTINekDC60Lueoc+2mjzy1TGNF+ytZnH3NDZyVKkvRvxxwaaO3kDr2dKXePQrfDzKL5cIYHkiVZ\nroKnVc6tU1xfvALIXZouYFenq0MLWiL+Ouo3FPy+LvsgxX+lD/sZJbCHCbNQZqrtRDCClJ15ePn1\ngUtoU5rl+xXB4UhtffeGYHsrc1mggxVLIbxTXbTg6RL0fUo6QYnMBQMJdr8aNcKL31ymmO9zRZn4\n+vQpFBJyUA3q7IHPJhkV+gZkHLm/qIw56LOvNEqcTFL5Zff/MZxgzt05Bkuvir+MTB4LthqkBjDI\nIgu6wCv4qDJa97MgfKrs62wAlmMWwUzPBF8t5mWhVBRrRebdFVey+o0wWY9Jq4hU1rXPgIGcgpi2\n6JqTH3X7oFOLCygRIZ5UsLBxBSDurhf/0fDMSRiWfw7DAjelHjP1TX526N0u5voaXesWArqwBqM8\n9vAK0pzHYGUHYxezOmpGf8b8PCmtswBDVe7HrW1O+uw0xzbhRT0grsHkR7o9Z7RxDYavp3IjTFy/\nkGWWtcVjp8iLNMJSq8HdpCUQ+x3Cb3wn8BU4ai/dKAoTcypnYGZonWPv6iwvbu376d0l0HHU/eqz\nw6TeInWfCHQSnYxLam6+ytHP49WUL5jsAI5WZZXrRQ+hO1EGeekvohTlGadBXB4ujMo3u2tstoLN\ncihireH8zwJ/sbZi+b29AZ5tMlw9ZuCIzt2WepiW/vp01EuHXwrkR+0XAM1wW68sFHW6oQuKlxHz\n9uzdC4TJaKw8UelcVhxlqoCdlftgc5woarRSySEoQSa1yYP/jZJpUKEkFs4ll/DaaRyoBbrzKIW9\nCw71wKTAQtxIOMuy/L1XExDJd/EKXf8/Ls9pb2FSe7vOD5mE8fOF/zxjeynhDtNIWuBGWgr9Kc9X\nQuezurgfPwL4WlGdg6dNMIaMa2XUgFABZL2EHlPau1VJIoQ3T/nQc6SV3dYyzwTRNXClMUV69sT/\n1+6DRaVONQFmBeBbz1tYnliEV3XerXyI+6B74EZyUYQGLKFl4nbpG6JndFotAHqjxQ0EXIy2Zlb+\nmg1TZVwh5JmD6qyHfoBPs2CoRzlR96WfBmhLs7OLGFlJv+oTrhiCfdwpYM7/CKbxsKE/kdWZov9q\n2sjvqpyE5NQxY+UuMTiKxo72H5Dhl51IJ+89aLIedydykhiNJ1q+berBJQxDG1PBXbrJIvvZuzqU\nkMBFDrJz8AO48uPntmR3f55P+yjPHiBJa7QsAqPq3IK776d+wnKUAehjwNd/iX9GyHHzl1zq6TH8\n1D5wbK16xNm18klLOA8f0O3RVoLy6Q+tUBO3eebjNB1w9yz2oxwuq8wuwmNWayiCnYZ4GrN1RjwB\n4cYTDDq2GA6xU7IMPcmz10ve2iigiK3kZ94+DLXPsecpZqZkGLK1dGlAukkW+Dq7S5X0hr8mEB5L\nDN+13Rg4ZHY9Hdw9cYkZMPDkypo4hpixjoR3FWSK2l9N8Sjxfc6Q6jWQtV1c4IvEH2xWeFsDXE3k\n5nvMYIG8w49ENjSPywB8y7YKn0BeWRXVf2vorwk8cakQaBvlXWiynKUA6KfbA3gvGA5yJ1hewhFg\nqWODNi2UqMOWTC7B7JVyPYuPaATtHtzjNwyfPzM4QU8XxBeML9o6ZwNfs7MZt7bckKn28Ll5/ESd\nhNvEEIihhZyZVKue+Yn8xwO03kI2QgutoTTlEH4rLYeSAT2xD9XAZbnzsL6m5dI2oaVdb+Ny/LAS\nUAcbMExyaOcBnkI/PibZj9dChg/+/4id1V3kvo8Z7FmMbK+w8911aLCN8Ts7DpA3Mph98HzbP04p\nue4q/we6K+SkiwPrroMc8rM1IsNlwasTB1AthaHN5lP0KI5+lknPdy5H+wizPa/jNnKo4136yCHW\n7hIcNe6qAwwalsSrpUv3HpvmXJ8SqEXW3YwpPIiwxGt80XizRMFfF/fuI3g6fmeDOtKbYPsdpig0\niR+BlHlqtSm2iNuYpKDrZ4OZXWR/0mDMX1JW2lPwpHlD9ul0QuQ/8pVp75p8mDpEqyY6Z5MBYOfV\nkB+sxPQbG8E1bQwZQsQdJpgzBjtjowZj2vxIhfm5ncJOrNtjQjIEb3uztkiQ4K5YSCgEZ4xUmAVe\ni6Jgg8zGD+oBsUM8DLtuyZijjW3wIHhbQZowD/XDFuw9es0zU79sxY0Bvqi8fxxvmyl+BLiBcwkQ\nhAVYg/HPM+ryLjHTp0RPa5hXMnDjDjQkV76ht6kLR1qzH1780XzXcdhdIvq6f9K+gcw4S6n1ZVl2\nvQDiWuY56XV3a1nXdl8mjWxrgJax5pEW7BY6S6yJ1hBhtoEWucxPCipNqxK3qKDKDDn0QZ5EuRuL\n3rTW6Q5qiQZA36a6jyXmOyODaT8sMtd/Ra4QWurUGV6kEKRYFNLsDIJVx5fcnxz/btx0VKwPwUKG\nGVLFRgQFzJrABQ4/l+7+3kX57KATJMI+gm74cbz3LL3w10Ax7+t6rLnL4O3WBh8LtqO7A7zjNKPI\nnOJOwCNOqRiINgBrrgu3A5rxjDFf/sHHXCZPfiuvBXrZx9C5LoR/dF5vYv2bA7sA1Nv+snk2yxyz\nrkb1gLWc90SMo2397w8XmW8bX2YpfxkRyGYnbExU2dsiVUNilgaSDrJBKc+beG+gyac/SJpn0ZQ0\nkd0jM1PfGoMuFnUQ/tZo5MtSmFROoiy0fYda0ijnFasIjV+ZVi8YMI0V2Z/IWxUf5JSXUc+ebFP8\nwQlGiDPcl548o3nglD8PYyUkaaCVPIcGQXmnsdyAAU5n6ZNPECufyoM+4wVGZMAjox9lj/fOBGPS\neOV8QDpQjw1BKc7/oCHLwtcOgqe1NWwy32rn4nmCb3QJN55ryzgJoeMAN3aHuiKaMrgAzQlTw75k\n6StLMh6/Gv0SyytN1SgS8LrAPjA3lAoNJU8CXw0swZF9dxLP8EZN+9031ivvU75yaJ6rDwTIEtfP\nHnKMPMwb82pLOLp2mzNK6SeDqnW5eFmEi8A/HYYCuQmJCXYEmyM3HQfl/kYToPsU1wLPlY5iKymh\nEmPqorSgwZRNZMH7CPhKwIeISW73O8VCTeSM+6MDvGI3q+mtmGWXUs9U0WWfhcIbI4AlEmc5szL/\n1bSrNdZKj9G7sqEFedi9KuamTLBxsisCyQkpvpzINjcIoVs0dLFgzm2x9fvqJasR3eWA+R2rJ5vR\nK0bYxFnVsb4PfaEGOPSTeSNQWsx0ei9eFZaeJl5M38VCaRhUvbG/C+yFoTRRKKlHia22OcV8/beG\n7PGtGMlMk9BdLCt1fG+pbL/sN2ECGaD2X6OxFFhiaQCJPBEcaVE8srH5RTEtOJi92kM04GSo0mpE\n4ksJOG2oPvGHl+MHrrN6MTvKwVvdu6UzX75md7cRqJdkaz3fROAfovihvZBmApBfKJtsq8b6PFQ0\nD2o1wRaPd8om9OpF3Lj+2BjMMR3TjIL5IjEdB5WZ6/Qi6NYRjaXKzeq1IzwlcRF3PY7snFxcXhuP\n3WWUq0VQ8TI6OFe82EK+CAklLcHjtrXmTqfmMW8HxR1r3bqpue9/Sgn4VbqtOYaPbjWoR1PGI+ZU\nsrAb/MeLEECFcOsVxKDLptRd8gqGk0AeujCPU4YM2F9MI/2TUlnsIrYItd40EROp8aSMufBnfdDB\nhmjo2wq55HFb4zoYs5UAufJsp+7fwoIkA3S0NWQPT1jjGRfekMGk325rqEmr9/kR5Y3H5USBvTjl\n1iJH8LUp5x0eYUtNwQB2TGQrwIW52MK8pSx+2CKy4pYL0BFoJEubKp4tpsuguKFW+TDSxYpPPDcF\nbqQYYc0FaAXqERdQu/Ur8HAIH/2js1RRR5UjPtDXWLgUzI0XhcEErmHkdjQb6cx8JfnkXA5MRRec\n/kZE0IA6agR2G7UtFwXCWQ5ExHrCtXtZgWUvtH/2ZznhLUE5mxhJbTHdhYB3hXZDtWJ2L4wmxy6M\nPvCJ8fAkOxB2Jm0KVkGYqbb/qvMVZT/HmGrTETxVSguZoI4pRWwarntpywXv7hIWINbae6aoQL55\nVZQtSGzCeDx7KNcisGVQlaceCIvMkNDg1LqQgzUzjAmWaSlEAC9q4ajxPg5pr+o8wpZua14/184J\n/Rg5PCzCcCFnqbc20UwIvwkdBJTnwbTq3XUzV1oBUMfZEV+kLXFFQs46vbvonKfTYG2APiUizbDh\n5TYzTn2BAP0Ba6HVTfnnZGwoSCv7IKJfKRcEC2SlWbXogejxYr5LA2RJcvCcfeVKYhc4KzEHagTH\nGO/5EU81kUIW8P0Wr6nDOuG18cJlRxUp5Guv/xT3dwe2bVEwnknZ2/qXSR5Pqcnw273QWzfNiugt\n16JefeegriqerDXfMDrhu4rfEpwS/OljFToTPKt96GDN0frs92Vrx62DN7WtSswRdIa+tpjhXsTr\n1Cjnp5jQcDP3VhXbHYrlsu+x1gJhJkaeo6tySz0bdgemop287CXFelih1mVS0nBhns7bbNZoeBU2\nfqjD5OZPY0gigTXaEoReTZUBmBc0Vce/STFCZUHCSU/NVsOHHTQ/aFiAnHeNMUCT37MfFB67ZjvX\nhbtT7kfR1PKPveXm3Z8nFID1YOz4IyLYAn2O4086phOXzBVNEflhq4EuJ9IZwPLuzMaR903+ajx7\nTNC85mjC9iAoBxEcR9D4ZYXZ65wI3meADPofBRSwSsTIrAVC0ggShZlfbbLm3fDsngu6833htWfZ\nDqQoe1Yf3adGdsx1buOtlrIJd2A7ZlGYiheoB6LaOZ/HHaK9R5Hg7AZkJHY/Bxj721jAWvIuLXNe\nim9+N2pDMyfqLaTvrPKjXhXG+WqmHDH8L5xrPUYkZ5ztJtPy3fdfFHQUdCmKmp7/IzQi5dUx++Li\n8Gmbz7UZDRsznLKCjGrPplz+qpTFOZwGZSzjTxSlwx/R2OFKEguhTdZTXxiLovbdeAfnxeft5qRf\nxC3QyQ/ypM3JrlJ2xwBiFLi0UJrqCc+jEBRROuElt4v+shtJWkjfVEA47UR1NZwUDTl4YGRG97Jc\nBRNSJBDHEx3bMIGA+2PCdJWRGstB6W0EPDv0gwxvyNAz66i/dnXT5+DfNOlXFMfj3qaYJp5HM96l\nwNmOZwb+aGmp+4P9tKQ8ro0smm7FcpmvERHDRJ6LS65JBACr6ElA3Zl8xkooQhgqYH29542HJeZK\nLIuFcYbLf7nejT9vbGH2V1LBLT5dlL9Jud+ybVD4gW+0Winl9iXkgUOioJdpPBtuWws5B34E4hs5\nHnPKCtCU9nTMY799ePaNfo50ZR/yvnaJPisWwC5MzZEvcK6e5piNk8XbkWPlrb20xevz9pM/wZxc\nJnDc9rHWwekXIZ5xjaMIjqerl0TmYvGCPg6OBpiDd24jr85sl2dSMckaBDk32XUQrEXOP0Gr9QA2\n7ZgEeUQohFuINgDqqdY/rKrAM2Zam/eGxh2pL5YQuuv5LnKrzX+Ay22B0s5+xsYP7nRhmCKJ9DWc\nZZ2A6y5L6DaJHKlWDJ2hr0GY/ck2eiqUdHOWjamV6Vs/5RmvwUiuFsN7MrZJo3giqCx+kC/8DSh/\nliIu5m6wfE069dErZ28n1UdC1OEzRU23NpjyMQ4RjDVSRqkFulqyXRxDkt4QeAtlMjyQoZ2gZHvr\nz4MExwoBJ7N8fwcphDq382vHFapDLINCTJSvTOwdNFWLu3mc6iMlVFqk2vzlPySWNVVrgJjo9RIS\n5ELIhEliYxm5Z6H0PhYoz8WC0zrhxBE+5NCwy7r7sASXuWo+ZdnbD6DSdP6h/DmZEIfli4S2c7PH\nWkl/L/qPA8TG7Td8/5A9bJgWGn0fUjnZd7N5BEw+LQXnzlGMHiPY5FKWgEH2UbUS1OKBDmJSdxaH\nvAQa8vjipYmLqrrHvaT1pwIvIMC7DU3CtSKD2SQebaA2v2anzln2S0jOaKFG3+e0EUJi6Od923ao\nvxLT3pWhC2DigOQzYH9YH9/svAf+2GgJA4TXEG6RLvtGK4r341iJAJM8i5Cif1JlPr7NB43p2aHF\nJ1bySci5dC057N3SFqkjzAQqq7rUTtys1+I0TnHQcbpLDlGA+vOenH76Yvoza07pAwPqS66GfSov\nPe6M4/6Ny8srlCBPqFgy1HWpXj9oVm0ZaKzU/FqUfTpALCO9hFOFRSxqRV/4wWqsyTalmj0XrN6R\nT8Z+rRihD/lojLAHvJwOPvWCx1PM2otB6X/LqyupJDbBp+WGgMbbEbuzGvKgUef79rPzHTOfW7aT\nQLIE6YrVKY3axDvbCRhaWcV20d8/kp7HOf3S1teMM014SsePjqVt0/FOTGnv/D61VkxJWzIsJNJU\nxDEdHG96+cYsqkBG2aQl1bglEG6VHMyoXf5oENVoUE+tny4X5S3PiLWtd8nkjioIHtlo+Q2jtgnk\n9HierpCAwK3FEOFL0uPmmAYwrnUxEkyH2qb5IHNObeDQOY1d6Y+6RNHwDzT64G5vi/phBzqb4bLY\nFiW4VvurKqCxbk84Wf6ZS1zjXBjSKMEylMPIGDphDrLq8BCxqUAn/iaa8GOu51/A+NIZ/WhfkQY9\ngzgvID8PIMPPnMr3B+z2axk8b2jzVBpP+a/fyE5j8Me9d6bcQ6ROlsVsSB06vPq44n68oC4wdCNV\nPuODScq+3KLnPR/cjhfBTnwF8CMeI3Ubb/H7Mg620S2CClq+cbHc15GQiyucnH4Teh78Tm2n84/T\n3jyMOdKf+hcbj2fLO9WotCwk/GdvjC5kpMF+ZMHuayGPzvN+ABKbak3+5flMXlnWYMtyBy5EKQ63\nJBiphH0T/pa3NsnE/GhyfbXireqqucg+txJI489Ygfs3eKrIEgGy/H8n6qumVLPAnN/ytb4+1mdE\nZtlKCSyE+TnIRv4UWaxsJppOtgMAS36GvmZCJM3zuuDYcKIhz/CmMpzFVbV4SeXbd45RoCnb7PAK\nqPvBIdonyrwRWXT4NyjOCvF/KeH4JdB++B42GtXr75QpONkBJEvXv21zVZGYLhIneNVMZdE9/3wh\n4sTSThzX7zz/LR5rX8hN8c2AmAXb8huw9eZLTv1fGj3/6TDuWxn7k4u1AmbrCqLHWiGcgOdRlZ6u\nk3u5HqMpKYNjEjG+LtmHUsx/vaQNGkSPISP8Oem+DmHIgR0rL/YVcDqQ8ALhvOkQ35qgahc9P2Hq\nkiW6TxgAtUwwEed7rTUX5oIQAKb3e0R7Yikf0/Du5/9cx9gmAUSc4QoSGWlIbRK9dYeNcuxTnzJX\nbl83iaRF4sazGA3ietqBrLP6nMpwCSWBPUpLG1zLQCIVirBfQQauKtC9YZRQwdaiEdo7d3bWOfSv\npDqjq9OyDPy0HHBnQrs37MqUgTeu34s16YKv+LDLl0VYQhsNzNL2CLffkpCe9lWovqi6K9rTykjC\nkp8GvbF0HgCMm7HbwIo4RZlOXcI4SNjLaFc7iS5dw77Epml5e7UfzmRJ7WJt7v9XMKit8zfad2Fx\nd7IVqOr4Rr59itCUbBVRHjmS3nRXNIplhmWQ8y3543D2AUA7KMrp2VkMqzA1i0wRgLr4q3AVdyT4\nkouJ6EWzOZWWPdJ5DD1HiU6stLFPwIETpJMDy4Tw+qHQkyDOSpAc49W25FscA9xy1bVG3Ka/NtCO\nI++zckHfL2C0slR+eZ6Uxa6PmaxcVn6voDLq8UmpD/7AzwQvxeCIdg6lUQ9QgJ3KMz03a97IhGnF\nGYHFqKIN/UIKhNWPla2BW+sguvH6owIlOGA4KdKrWniE6qLuB8Tq3TKy15hyxeSUJUqrljEXQ5S2\nNo2Ns0oXpRVVrLsChdZhQ1lUTcI5fOvSVZNcyDTYeNfboyDzKLvJAS1q9TzDqE4Rfps/zRL/KkZn\noHSF/9lgZSDXQToxL3Pgs+9ehXWMwE+2EPUuFnC4PXd/eapgokBnpl2dPrmYXIGZIg730Ez2oCyW\nRQYSt1YNvmgyNwQ7ZDadn7QOlikamwlC0ri7bZ3ZPVYb4/0dPxEIXjI+NiaEmgBmDtUaeC6h8hD/\nefVBnDDMV7058+hOEaPDkEhOsS/ZvndMqqrqTBp0eAuIWQ8R6VJc0dTf1KdldWVrvxtW9ONsziTg\njlPAvXfhhzhMJi2irglrgoZcRwS5jv8jbwzUbJyD2cb1NydRVZYUlxvRh9bXgkaeDYOPuLDCgyPd\nrYSVAOvrabr5BIs06Qd+BCptS6yDyBb6Ox4gI5SILSia3eI7QDEKEbbqgM9IDGjJpCmD7A1xoYX5\nfQELRuYjmleJ5pMQtApjYgKPq+3Dhh17iVwVhPjVfG7bguVprtS69LXzEasfAeyWYoRfZAwZBHRA\ncuGcASni2JCPEkgu/qeM+qGBmwrTlSSOjS0PrBQjKNp8i9/3BVY+FdtFm1AGMVvkBQ35yuLTbK3i\na7YwCAKdn+yDaNTgEaSiLluaSAqInmODK1uNNzpPw6A6oEDLp0qxW+kp7qP8ZLivDeysQ+avD+Xx\nioiBc42nyBXc5VdQ1/xEbcL7a1vxACyzRSVT7TrKdH5OGXFiB6pkpoePUqhxK0pPo2qSRaRz/3kG\nx97AP1FCKffp5ZPaDR2FNFPBEQe17QAEn5LYqBYv7FY8UdNuRHkRKZQmJeFIwOYmZXGFlnFSVbtK\nxFoQboVwmfPiNGJBC0qUU29+Gn0VLLLn1CJtMM6dwyJx5dvxUIoMXZ2iNVYqxMjlWXPAZ76yDLKo\nO/npw/GNzI4P6oGjavGpL3vVI/WLZVb3HZr4Jj47zwvgOhF10D2p5e/20A9mWg1gD48N3gkP1VPS\nnkVj4rDLzyRYk/T36uhnTcud5ePFPmVRugM68nNN68kMhHc9RkKTZDTYcsmRskksvzqENbtvjop7\n2+iVbP9p6YCLuzL+FJJX84IsBELFwzD5FyktOg4djnkkbCnxcYRAuGPyyzuTpg3HFFel1a81kzJx\ngbLtR/FpCC3OxA83d0woxE36GxqlLrIdCQExiK6K4XggkIt8qyU0EycvOHBsahhwoybJpacsqasx\nh4riqqfQEmq72AsEX2xK7JRLI8CWAAm2DkEQCfS02Q7IO5SKpCMdk46XDJhDUb+ccTphqWZT3dwV\n5DH7gob86z8PP1xM0FSotPy2kUtbSbwhbAdTK0+owApkATMKnQ8MDUSFgmMBlhJq1I0Zo1zWz4IS\nG7M0chLpAWvxNO1Fw6y54OqKz4w/AIK4L6L5WPwjZJRGoAOGoSy/rqhbi2HlaVcioRdVmexaIhpX\nDPgum8ntbkjrs7IuPRaTAav/1Aqau7J34FkobGlaC7Vt/PoXCE+jhZozIQ22KCGnl2RJhS4vJh73\nOprZkjLoXDrrsMSbtyPUrV4896fxgQMYHeVpNomcEWHgj969wbJvRi9DI0Do96M194Cg52vDhVqZ\nWj+PqBq3GxjACebHkSd+XRbwPAvkoMs/bxQv0WomPNIl4/acJuPEuSqcmsxW0Z1wlywjOO5jXLGG\nDaZmCC/Tn7AgB/J6zM/4ex34Ybxgg2YXMIs5T9wtOjO1Yvu5FoRp1VOSiamgqz+jw9utR8GSw0U2\n5VLpyNwXhahZVu6Re7RDGsns1Tq53mCn92IGUIvWciea1bIBSeIPAg4VS05nVYPczjShRUGCssMb\nD69OIvDr0nQVG3QMLrRgeA+lKCtFkWR+VvVwOSReqFajSTFJ1zja5GzfpibZFsNPlWBdwFSmT+wR\nxtNw/99hkk6yvmlrdcjiSmJ5/nwgEferQdNZCR2GgT2/aACJhF4guCzHrrd+HHB8kPVRq+NO1xK8\n3AkERkQdOMv+BIZ7xI7JFPvAhkwPSq8/D1iB7XHLlKkEnJzmjQQrrlXmQySCJhj0x+QihPYQJWdB\nyrTighqrSJhWdiF+PCeB0i1nZdKDczja4N7YbX4qJj/wTZXx4SHNY5kgD5EM/HkNhzcgUhUO4ZB4\nKDP2SKECye4Ps/t+V+LxvO6uYI61gmVMRbZhMlTAKL45yHMY7DgRqi5W0m7HBfXq5L73nDQWg2xY\nAhIW224m8nGIcOWl5cbh2t0tQNVqt9ELlE84UlBUhL6rcJFsQ6NzJrGS9ZIW/vMBqo+zUJuPm1L3\nFX/PAFPec+GObU+maPSO1M+G9JTC1kfMQbYnwPeiI8U2b3eEVbQGuyBJoWrG0yrCEd/4MX7BBIur\nNRyI9JzoDkC4OtansDB8eqwNrLYPRRlfBuYJKhEOiDo0pJHtPYpdvMvvb0EEYNUDSH0/nUYEFLKz\nV9OE5p9bINeYgdhpya8p7wGcR+3FAvEnjFK/TFc2wuWPOBjbB1Xi31ADGbRW3ZcfnfbyRWpbf2Qv\n55FRIdcoBMVxVCCQVe1egVKy9KPnkvVvIXaBQDIqtjMBaUgS3vcSYqg1xpT8zn/gEW3iEdFQtJ+6\nh0bfP2ikFH98FgROlj1mHqhp9aWrF6ji6fAtsuCmHQHRjSqxP+JEVC+frdZuBXOI6DXIKQ0e5MqV\nTiMs3mtyGpd1EtDofzS6tYWVQArC3Y9JUyxuz23wPuXcrDxn2WfXJuWV5rAksUqgdyCFsXtXAVym\n2ySNy8jfKanYIPpVaf1mfITaw/Y6ixwBz5A1ibxMiAaUlPcfEto6rGYQhhokT1UguVdW9InEPR0P\n1Ts7IyskC0LbAnyx3Oa1PzvUeu9Q6f/J9p7FS/CQ20eG3u+P1dRY1dS7ynP5yL1v0pMNpQigfgjw\nnZQxpfdK3RTLfIYpGw6YCDi9Hz7FPH/RFW0Bl2KM3dyT0G4GgekgqxIgmMqC1RLxomwLBi47QcFg\nfAYvxwo58K559ZJcTKirgwze2xa5S8WnJVSslX21KK6GaALreUaaou8cBbDzrY13vH36HEP5neeI\nUIZbmBhdygrigYPn9ExrpRkBKRmqPFpgRPIruQm5ZmP2IjYTZ+bYTp9jRVIHU9OVOssXIb+1chi+\nBSN4F9nsielDghwQwDD9aMWKImwU5TpZ76w+UttLwsOJkuruQYInGbd6erxSNzHoRh7Sm0DNUtWV\nBcQIuC5Z1yn1Px6i3vh7VkFoZbFCFWdUsiJSL4P1zFbFLXWqKm76hLSo3/3jMa73eJGzqpZUYeJS\niMb2oyI/jU+9KdbsbVdhHlmfBI4dRYCdzoMNZI6kR3kGkHUB/zTM0m/0ALsSziTG+4YslgSac8tT\nc3e37552KnECWqK31Hwkly6qWQAGEG6SoeKTGcVlP6Gf2UrBilexqgF8RoQXyk+yXJhGt0zQiChS\nUOZvOJVDJcsTqxKz/mHm5I5RUN9+ej8TFRq3Q0UWtHdUvmEpSIroaLAWjkm8MQr+uXOMBqQ6rWN0\novUT93IGkeAH+37Cdyib/vfY+KKTkImvSckH73ny+SZXJmrRiehIzywYSOHOuUFX4ktmqi+Fj7QI\nm9sWSdhrx0S32rvh+BCZWStZMSrW5ZRqqXCsabNuq+Fp3DolcwF9fSnGx/1PeRF31sFf3tSvHg5P\nnc02QXAHXCi+x9Gijfa6vQSHWb5VjA9viW2b43QGL/JWKTzRYbJKz9hnjs/kiwdxjMlFuGLaQeqW\nMuy3utHzXm4Qwo+HcEj+7t2BFriNm/hkB3GmH3mpexZWI0RRWK88kCBQgDRDg+NyjL8AEI4/I4Yo\n7UN39IOtO/O4A0nuJZ1NOMPJjL24aUikjIpecrLSe3/gQCj1aEyhYEhn++CinWT1EAj6FhlFmYCy\ntJ80i/ezJxTpIVlaLV+OEhfMGM472tn/DpE+pdDv8eGWJ3logJXibB2kVu+6h117XqiNuSztPKY8\nWG/lvAlbu4gojoYlgK7gdzpB5Aw1Z3XlBgD3hO6NScc7c8gfGRiUlqwC0uTGbJeAzYbQ+gvbUh11\nA8mFay5MVgn0RLVb2MaDCfJ0g3lNhaa3OczGODoE7DA6MFxM5wBGqQIxn4aEKl0+LZEqA1qGfeut\nojsyPrMcjfzHhhRTNu0ARU6du0VgugX2CM6EiVhMPN3oUoWHmbMgg3r3iV1kZwaVLSKP0+O+UUME\nDuc0QS5VnIL0NuHYYlZkV8hPpq+XNRp3yd1xlDRbl21nyMwOrKVsKi+L9SI0S9Sybio0hgSy4o6F\nTGPP17P3w5wamgTp0b4VUipN0SAxt2MVYUHIx7L67daEtRMjv27Bo99vyNsELKyA2bMtSAx0fRY3\nAdKURPCupTZh3DkB+HuD0as3LyA3UHdo9/OyvLbhadT64y8QdxI69gjXvkNnBzl+LgDuTBXNyhQX\nUl4PxbufK6pvTxc+/KdZNZruKnbyruJwzqSQwxfzHrgnjhKN5RCUcWw8Edn6KOFI3AokFWDCim3v\nfdFlhP60PEH8XnWiFz6GFUOIwGy+HQdy9i1Z1oxIoZyffNaqm29dDkjvtDAJu8yS+eVyhfRyJ9sZ\nau8PzaIjZE7Ntb7IyDQChJDBPOET4aP39ntDO9kEGQKX2VSdlrjm8Inuzn+TqJtJUPEw5deEVEXt\nlIiKtde6Teg/+SPeP2MUctVoc5Ds/LmWAzBD9YSIA0uCwJg5LpXNGmhix+j0CoNlPDvyASVCPkRc\nJhuqz7GgJM1b0/n1zQUEJ0+LhcZRqVvqqpHCx9bZicZwNRGKg9024Uf6DF2vJ4Umi9/7bCTxp+mG\naGawHEJ0sXJ8mZVH2Pzea5Pk60jz8m0p9T3hAYhOhKGGQOPxzNPD9rsmIq26eUo5LaOCIYnFGTzY\n9HNgcBELHTl0epNrmuqsIDleZHW21AOWGQZI6SuuioU2NZXxCAF1BvNUdqn3DLtFcw6tlC0ArOSP\nLQx0/MCBHxh/3J9mI7isY+a6buAmteuxwb2qK//J1sa3mcc/8D0FmYOfdI7gNgrzU3kXE+d7Gx7b\nUGk+ztw8WujFWi0JG6gUeC2I1VrcfP72XkfrzjirMCq0Q4IOXDIjHUJSQnXCw4Hn1cDXj5P+XOSr\ny07HNj+owOc/HUOmQDjWa9auDqdZI5mRur0KjEFtoIeY95cJgOqWQK9xxqdvk/vJwDyjBFkVqHUW\n/cG/A3TjWaHxMzpNR8RlJK+F0CZ+ujpBsX4EI91a7eqF9gtCJFD7heFiX0TcZ6lu0ug9pj2aniIy\neDfwVZOirpZITk6jWOoAxZO+bPzovKlpUkPjox/4GF3DcNgqFpT5YSdT+EgRgdIv1yMvVsWp8M7A\nRR0DB9vEH46wN+zWU7K21L98nD9X+if+zCjhekvmiuwNg3cPJ8+NzMfOQIDDfam6BVFVsiNPBJo/\n+w0bE9Q2gwf+VNoOEgTyNlGSLODJD04PCp4v7LZiTuNRcqvb3dUgg6aOjnf/rv+K65gwcHMhZsCo\n3JwfFEUxEAxe1FCOjPTvtv/iwWpJU1UGq93TezYvJdbG+XsUMJd6YQwRaodc1amOu/8z03v773a+\n/JFgj5x63AsSRcAJEFFg0zbcJn8BrFxk122O+rO38JgbEEgLErO52bqYnYQWONptMU9vuBoYq4zq\nk9hR05WY1ijAPQ0wxTp2A9v16hr1OdvBu/Yhx4+fGkRWpflPRxzECFJWPHIC5gtv0HzYLYrtoy/a\nFHqLBKACvkVsVZjUZLsDG0CBl1LTHfkv7Mq1cTBH90xfvkaDvEcdSfBFVw6C4FeeoRmDJpMvV3BQ\nuvJW88u0KBGI1Zk8krQaxueZtuz9zsgMXFhT/7hXP63zyJVPhoBXR8t4zg/on1JdrmLHtIlA3Dt2\n5v9F1hTVH4w4mm9D3bVKPnM5hA7ZHlvOm54oog0YESIELd4AW0LEjkK7FbyoIcORiZTsxzZwRzTQ\nYBdT6x542AE1m+I71MgehxioIAF2ky+GIHE1Xc3R3khvAlCKaURwB0aK8xiOSA7gE4hVtHtcPf+l\nocfEFV63c/jVLj/qoDxSHKcleRgS8a3HslTQOfjUwdTT8WCJl+jcFw4SRkpie7l213z6jM31E+NI\nYXALlaMoNGyNphRHLrmNcLtXlAYsOhzu+pChMVAsogaEv7af1jHTOTtvarOqdxC70YCZKcQhnbVT\nWTt2NXzQscma0OOHYbMEWdoIXrnHQtUzNPXIUH/W8+8BzKiocT9/5PP/7g2TSJMAHQ/Fl8Bw8X0n\nxaTPb+TmhSZ3cYHrJlrlRIJ3ThPlLESRKfi+fHFJxYybxqPhXbECW+NUZ1ggbt4yCTcd6/YLK7Yq\nG7/aRwLnKIKL4ypI1Jmxv3ooFcJhpQIk/h2+MOk/8YkC+HWKJBpSBzjLWhUBRsTZwQNkAPrVMZpP\noK2TRKblTYpJqylZ93Y6CUUoADVg9kibIWZQsvVYrDAB1JdukNV1ZF1fOR9FgHv9LLv1d7z7EZnn\nF6lZEBJkRRXwsNRDX1kuF/6tQt6aNHULf/qmVrIqG9uRbdoDgo35NuU3ybcrvWIFqB6SkwRFjfCp\nRi2tEBI08tck4Xoqx840JhPUk9Zrtq0AkiJTGUoAMMW957W1JXMDsrKHyia5iXA3qYoL7Yz1LDcK\n4YIiCNl/sb/o/J8cDeuqGbFAHGSjFhnm2OVjK1BP9FDItyJBnH+sGD31Vmb3QCnAhYSDKzXA2rWa\nDSNIteaWyKh0d04OJCz66BrrtdOLC4xvdNZ9RKAwerPf2D0y7ZglwN8IRyFZuWk2H8HnURUnFnBD\nR4Oa9F2EJZbmcPD14Ziqu/WNQ4XKjHdlcMOQ3Sz7SlqnbMnDpQPxPBsxAJms6VDWEIMBiTAQXSzl\nH1gCsgCA4YbbI9u8VKfEyWqFaMUBZbTqi+wpooFJUbbefy1P41ez53uC2ilE0b14gaQDzglBBNKx\n4DTd20ZmJ+DqRAam8G7EMT6QYupHzb5YADQapXUCb29poEqbw6HSJZ0QzpUja7Laq9Z9NGZ6al1j\nIc2avOETip5A2bnb3k8aPjNv+1E3Uv/BLBwwqM7Z18nTcnnXjjQfeAfidPhLIRvDeZkRDCa95dtw\nHHCYlODblGNCkh+xQu2o6jsgFmMhPEjfUej2nkAmsC3mQOi7bm5P639OizzEkPHjA5jtvsvCagOY\nHrbXCv9NmS1DyJ49hU94OGL9ewNwj8kawzSaNEAt+r8kbkF03/mP2MhrnFZqNStwIOh/oEpuXbQ+\n/z5ZPlzQkyn4Cc6pPcOABs5mIdXAyi90pzsL6jCoV1/8mqgfvsIaFxmpA0kJZCu5PsTHopC5sdDx\ntSFIepUvlims4HQAmuyoHiZ+Zn25CQTJ6iiXv8GwSaR0nT3ratKZQpIKafFeqEuhMJ2kKSHHbF4f\nBxw8PZMvEV9yL+cFU41UKX46yMRQWJbeHh2pGJikKzvvPd+9acaZv7DQSuLleOx3juIrlEfOkD8M\nwGfsKy00+nvCWDXmDwNrn9nJkdPyCTUcI6/WletPGKkorXMiODhfHwJnstPo+B/lrcb9k8Ssi1L8\nVIF1SFEkBCMvGrQ6ysADD2jOboVuD3Ru3i4kGdc+wyq+sjnqbXfcAfzM7+yz1/IdJXdx3LTCOk5r\nct4ISzSRT/YC+LHqKIeNU+jTfB1Ut4jNiSAdbCCWzM50nWIMwvUPMtXor7kifYaBT6JdmtKKbhN6\n/TMo+D8vha2ipk7GSmzb1+S/1xxmNSAMqitNB2PZtF+qsUKaAqqX0TwAyG0vR8IHQIRANFi2L5dH\nyGL0kAmbmMJ/6VoLs+IhT7BpR0TAHRwQ9V8uNPecNrk5wBzexX4MRBELjh3BqiwRtzflyX0UT46c\nMJFiHlApA3xrXgqKiH7z6wrv8G8uoqAUvKViPnT1v4oQakyRac7cw/Oxb+iwhYBdfuRW3JWoZwyr\nBwbMtmloYmz/BfDam7dMfqZ9Ij174RFYJ8b9WXrMmqqdfA72e9JHlXY6iSuMpAerun1jMxVU7Req\nVJpuwxjhM9DgiLDy4wSFjL7b1oJpWMvVnlCOsXKZWocGrF+Po4pEv5/zcweODo3X1rTSNLIIsoei\nqTzwCpk5HOs/AeDR3Gr0HSG2xuLozyEk5KlQ9EFei/Fc2w5cWbmzL10x4E2KgUj8NUng3xaQDJ+b\nidX557kDah4OQI8z6Tyr2xT9+d8bezR4VuNpijtLVfFcFsFA4CC2Zzzu+uwwesN0Yl+6nxG0emFY\nBwBZbrsgPVIX8cp7U9zBRaXMznsm+KTMiDxLdYjiK4ixGMDd5rTtso5XrhdIZZ2AXv3UvaFnFBLF\naSyCc0jkEU5AQu0+iUR6XRbaZW9qUDPif6kXIATaNRwQqxaJTdgHIhGc+l6eM160uVjXW+0pWDrs\nAcSsTBne3oNrO2ZkcKqNE0inaIiiAC3Zvs0511PJTOu3Q6nsY7ejKZPKVSspBfYBJuQ2ojHfvE6h\ngewK/Fyrwj1lePwIWjgCA5q/Di9BEPCkIxynksPLPDv+7i11ZxZKsX3hJQEZu2PKhB46YQS7Uj63\np6bPAibsm1o5pTbiC8+Lb1OZsRmL4a1GmAWMGEBXLfT21IIQ7CMNg9XiauXnaQ+H9CSIyn0b/dy8\nk6C91P2WZkNpMBCKp4hVh5KhYBWr36WgberxSUY8S2Z7QiJ2P2JfSC1HIhXD99v+G5RbC9Z6GXWB\nIfqRq3vgaRjLiBA46EppfMTYHRDBsPRrYwFdd0NacdjwhkYbjRMa9m4B0b5awGtI2orNkizy/P6k\nvBE4+N4NksctGjrzmq6ov5JO5y5WBIkIdmCgE7OQs9waau29e2EifYVy/oTeqVi0SI9135eRfoA4\nEjvBmhq3VlMgEt5nKogtGQn7NEZYFfdKooxaGLueY5l3uJBl1c4RPHxdTFXWGd3oQf6nPo+dxdvT\n0Poxpb9miME4quk6mjZJeEucPgFe//ds0Ej7Yh/9rGRun5M6OfGv7w0DJ9c7VvEvWpYD8FQ+BJ7r\n6LIyU9rmr00vAwA37uTdEsITI9Yje0W6vXemk2er5vaXfKKSoQNm+57k3d5CE38P2fKW7Q2iK3Wg\nDbkbPv5iSKGDytvTyvwelLK4y5M4y++E42tTwgON8DRlBlxwD1IeF3rewCnmveFzCgkIk5Tg45Zu\nG4AXgxJcbX2LH6QCW7CMP0tqPrB2N04mky3XKtq8fsJJr6jnsU6E6IKJQ7gH8OE++F+uEJ8b8Gbb\nb+dXsP2TdkIfhZh/dtPuToS8wABTpaysxAF5D/TyKOTlHwAqpZ9GlPbIAaA1iXlT84OtEwn+kTSf\nhvxgPBPMYZK0aWvmgyEhAZcKJprdxdVs/S5QMADHmOcWr2Pt3R+vSDXoPvhzWBzdom/HWlyK/0EX\n6CJ5b4VRiv5AuFu3g3Ekpyonk1nA8Op1yBNY60S8WVd8Znvo2vpJiKEw6qgRhdYNCiYp+NBQTSaX\nC41878217J7pzAYDmrQFP7DLG5w6DofqPWaj6Z5kdLZfID18mG5o1sjo/xzFfgebh/Xi42lvSN2P\nL7r+6yYBcDf5bcD2BphSJ6mLD0t112qUWwGI40FrLzmvz4FlRNMYnTIkC76wZdv8R4pONRlD1DWj\ntgfEhz7QznSc2jed/HOmlUJDTjPTuwVaCGzGcLrQ9AS4Z2sIm6DdCK7b1Lwa4qRIIP3hSRfZJZig\nZB0b9JO58gaSty1oUJO21s7ok3pxar3/UK0jAzpVh9gHBzd0/7chZPEw1rulnEckwIlBM38nkjmm\nyVYxhNsEPC8FzsQ2KCaTZitIaxCQTYCTlecz4rKrGsXTtCwTyFQl69Q5BT8sz9ZmCehXW4NmFbzx\n/78F4Qpg4W4NnnqytnTY83RQxO8+5fE7gw76LXMsHgeJiHHzd557Wvo+x7wK/ZpOpnnxQ6oCOVnu\nXwku6RumJ6GimEr/9pfkmPGvLfrcsouT+UEePH4hKRRXqd/vayKDR1JkX8b4bF4nU4VM6bw4GBOZ\nIXVeH2lcr5GFcLmyq9RorN6facMVqopgeh3DWvan0ocsCGUEtxAtWjXd/jYxyFhs9Cj5XhBP2wZF\nP6pvTs2lsiDp4pJIYmv34AVTMfAMxZuD6bJQs8UgQiTr6DwjMZtsjMAeHVIGE8qBCoRhb6iu31gt\npkbXMmCiTHRXdLVHPr7E6HN1wvA6XOPhrpHGxrXczvlRJBGDD2hRTgbGBdwAPFOfFq7MRmEMfji3\nT3I/hDupfrwrI9obJTyXtA1tVImy2Lhsm0rq3KKDm8uym+7mWZIEhHxycF9YGt6OPSTVXJteyM8k\naykOf2zl8u0Pn1Qhw8Z561nUM87skdv6O+Um5Nk0zGXoGsYw7PldxhXYDtySeARCgSpERnowIDUX\nsKHUFgQiUPBY4Aq/2vo/2icQpQc08ZIWx+lbfDJb1jQ5Z9xGRrkzwOa79idaeK1Ists1GI1iOms0\nznbiJ/GV1T3pJbUJG63bQfgVFxEcxFL4kqHgWWU1QG92iWI7WsOzQBHNmjPY6qG765GPCCWXOOrM\ncjXRu++6FkCr5Ua+QE1hKLUpHC5M8Nj3Z1GQm6+JzY99SMjhJaCjKlv47CyM7MYOxFuTY6ZAEK4D\n0LhhcsPwaT4v2qkgklS2TExvbSIWHeV5E+PPnJbuB92+pCcb9xYpDHNSe0WEVo1uGJJnokZYGKYi\np5cJrF8kgurbXyiNonpwTXq4buTmHaKlfb/MOdhnXx8zwlgPmuQ+EhA3UwB6GLUkyerME5TvJuGd\nT7yGW9sBbkxdkhI/o7lsLYRKJiOPkt6qxA3yFDKsRif7rh9WQ+2TBKQg455pQtKA3KZO651hvIY3\nNV9tTs954VfC1GC3Cqj2gC4ZIGh2OG04HiK5AolWnAsTJbnXY7EoGRhyrf4rVrdYLPaFQVKzZuYX\n0OITFNpCTYEJw4CkKlavz2tnhWGWyiurOyMXLJk231ovVdLpTMVJOvNNr0cHn3DIP0EOQm4qsAA0\nNp+cH4tGx3YneBtMxi7afFHG7EtgUmqi8Dwl/49z7+5q1hKtylV0W0k/Vd33m8/wU1YYJMfKqydX\nn7YaEz1rSbrDQd1XD6S3rqf6Q4/muGLFmhXZdjfABKMTlTWRjCo7uew3xLcBlob/3dUAWpOgv5E5\nz8da5xGi7h97wH+oIuFyuJp5sMwwcs4u8RzcE2jPRHZtw+eeXulgRfghplGxq4D207hjIXShtFi0\ns2lN0J5++EQYwZlohXmYlOF88Da7QYvBzkk67sMsgpD/LpKGGsDYGy6WFrkmw2Z3/wa0Jl5NGm1Y\n0AWj0KhNFX95ixtsZqZZQfTtjYgMpYaHzxJF/+P3ttY6ZEcTQdHw88ErpksWswca2gacAPMOmsiP\nakP1m9Gy/AVz9ZlFIG+ar54ccQDerSaIjze+jrjdGIIeYqjq5sRQ30flJM9SKigP0KrmkzkkpGcn\nMVOPTJOyf1jGrVE0q7Bkhvpjngh/p27RfmDjo2qI5mjgVZRZOTjfXOjjWJYc1J6nRWVHsxngNJwU\nKdmzaV0u4vRhuuuV06nu0H99P8G18OxMQrJEtBbaI1feQkCcBQukc327Q4EtEvmtzRJq1NLjV6a3\n/qdq2U+n9grjMxQaswC4mcRhNQfqWCvc1PAaFlpgwQNV3W8+JlHbB0VThm9w2yXBaq+kruNF2PyT\nQsEbwvAY/Ctuzr+Jj+V2g+/zTTztMxDCdDmLZtXDoDsRpLWOLVdt27RtQ4zM9CiR0MF194d7mcLN\n2xXATkIidrkmeRffESn+ixWO+tfb2l7xc/wKdHVEgLmmsnne57wud5mRxkPohPU/XwwbaTZ0w0tk\nEEo7Ae7wUQve7cLuO4gZp9Xy7I3wxU/kYQZT0EfUXSEjyB0IPlP5pEae6EgM7KBLXSCt/BDLBxqU\naD07LhqhYsTkzoiuQolTPfZwRX89ekwywShjj6zmC5wJU310K00ZeL0QxNwe82vEpKJJUHcx3RFj\nP2JirFA8xg5SK7vAwLvyfXw+QOtWxKRKuD6Pzen72JQQmnp1CQ9lcY6KXgdd4cM28/GGKRjtZtnm\nENCZxoj0Q8MV1MYDp8DmNy5+Mw6rrJi5Js8qD7ioVdBSHyJ00DcLEspNsFIlBIqSOqrrj6I9CSJB\n395FN4uNriUehNUzMWrUcvzdXWG1aOkUkRNgqerN/qH9ebL8JZIg4LQ7YoK+Up/JBQWCZuFXI5Ws\n11hTPGty6JebbXvJf8ze0/4evO3SfCzd/DZwBA3RBiFqL5flj5MQ9VE6Y9iszlQE2Y7on6SDdnwC\nHWYZXQuI7vI1hXqZWJYcmNoDbHaQR5s9G96KBVIbCfBrSgDB1It2iMnyOdcgtz6DEnoNE1dNJImI\nWTCn5J709ikNpNWc16XDM2ViklkOirXoByCUsPjqnvpERZwBqgvXmGnZ5VkdpE0RZKgVN+h/eRhJ\nTLuNDMgqA3Zwn6He43JWarLn6cCPIGxUz2rHFxl2TB2Nnx/h+9bDsKGezMm2i7Cc5rXn4NZqU1BX\n9GXaIb/vdqrBMxGxU7IC4ew7/zzuXB0+D3zS9V4aqbK3bigs8Dg2IOKYlbL7xUblNNJykOmg0J1w\nXviqXo5Orfu/zZkMtDR4zsjy0C6M3lfuF1opli8FaX7aDjr/iPnmQ9ZgPjGTo6lKYP8t5Y7OE/bh\n164OP+gLJI3TFRnm2lepGnvvpKkq3Ss0cRwDJenyc1K6UVyqbdiAyOkWsp2SpAe0HhbMQDckVf+E\nMekJdHfVRF9jJBifeKYo+cp5E0DT3BRR4NnGFz2CxMiScbCD8z7Nj22yE8uR2P6pO+x0+IdFQ4ON\nTZzDAvJLs+BdgLu947A6TIbwuKsWx/sy+7YbJw6fXRRH29pZzJrw7Q8CNfuXCJhL+8Ng/zNBncz5\n1/UYLrsmccYhdR+TdWE3sjqeTPkCu7Gn7EpgG21CcQhl9mMoVCCQSjzyckAEHviPyWRNnz8E9+bs\nvAhybuPtj2O802S/dNczc2+8g5/ccLV/eJW4LndP4Ona3xwbJd+sRFPV6lbS33BGLPKi2/TXzei3\nDgzUYEvaO55ztzk9odyovt/EHdi14Mjbq/xOA5KduHkAnsKg14aBsIhDQv+0q8MX+cGIM9uZlZwU\nKQborAM3mwB+jDpyp2D3HwuF+RqAAg5kXKjTgjIGAf5EB4jwEu6oiK8hm6hwVjYo6gw1bQUizZE9\n98DCLgNUeAZZIDPYNmi3yswjxSIO7Sc24bX2iciYCf0diQqih4Jcz+s5gfhN3gSFnyFDk2JOu0xM\n4Ty/t7IJJkGn0tMU+KmQo9VVGaTz8hr90tI3zn9NC145kU7JdfahSf7k5h0ZN/zFyQgh0fWtTtOk\nd9oLlg5K6BI0haRCKHI6ibGZ2SAFlMwPG/PsxrsRA4qu4WZPco8dIC2tx42U5gf7tHslKtVDObui\nVmPILstbLvKf9C5U4DpgkbBQFz/mFYMgkxjqNBO7dtj7ZGUuWQpdg1n0W3A1vBwHRqYCrveiYR/o\nN8RlnjosP9oOeZ/dAl+ObuNxAvEE4eVYV0m93OreMuQsXjxipqfZBlldkyu5UsLsy18mQsxiNMSY\ny/FGm9jKMSFv9YpmYTq5KdQy7EWov1KILWvBjuBsUZFd2Z7o3vXfRe4IdOSs8rM00nuRaggNcobd\np7IpziKiG+RQdYMcJJ4vDh5P2X/TgPv7qvMWzIBFu/rOf5RNqEHVAQIulg7IE7luZ1S5Mrc3em0j\n++wuOhiJ8/x/pRGiCc3c/4pVWD5H1x4WYxk7nkCAqj5Q5Id2KIec+u0BxdbA6+CP5sKj2FlQG2q/\nkMmt/QBVjSWjH0fSKF/mVL2JNUBwuduMX9J2fjPemGmQqZ3Ul5s1AA8viIfkUw3vR5r0w0cY2sNB\n+msep1R56nsJDMQCmOPrNZfKdnh7IL6mBpmy5+vwhOjd1rmdBYG0oRkAK5xfRen90FiO342UIrbD\n7BQOfMVCiaSk35OLUpAcm0Wd/wTxn6KJPYOJAHjLGtr0f99qpT/TKUcqrc6q7eQz4o5qCI4d1XLn\nT5UyM6MuLLMUF6GDabDVg82sI//hmC8yUWoej90TtnGPPRSHjepKBLAsnY/OhU/76L401SwkSyrE\nqlwP0ZAMKRRq1MH23qhBVnqK7pOmDxF2/YElu5UIvE2MUzD83JHBW6rZbaKfiEZbOr5jBJWrsRGe\nRN0X5MJ8MZ7M6yH01oUGfXaFsBvfa3g9EQbtKh9OOaqLYyHkmXB+h3zaolqVjfe1Tzx0OfTj64kC\nkzZt3zAoXwHIOYvDsQdE1KcXJVLtuvBhkX8zCiG6+qb+rZmlzVfzRrDzRROrROmM2Jx7jxkEXC8i\ng60IiyKt0G31fhH1UqZn57ai6HrdowtGgQEDsB7e6kZTIHDfDQj0sPBuK9WYlYmSdD7EeqpTeTG/\nWCcC5g0L7gHYD4+ewqaJjzWeN0+X/AFG4w0o3u8pzHqW+EOARHDawtxsWYBezkLxK5h8tQGq4soi\n/ykG+nompM7khFfGJV3nyHodHdPRu5D1fA9dKekrR0fiINx/4FG8PsMStlDThjLY3pxd9NO7QDco\naTq1HRzU7GnW7CnSvD0+oN+HX6irfeJbdgMN0NU/F42a6fXwH6XlYAZ1to117tEaZdV9uuxb2eLL\niDl11JBlT4YEVzw/0OCxw1Jrv7XPRxiYOmaxSv/mmqO3Zb14hk44kmFTWsnqX+pjE70IilE61aNX\nqEAzwogh2g+X3IU4zoNXtrc5oO0CkmodLjJd5+rJiuwVGyNCz7WolkW6dz21oOD848y+HIwN04B4\nVHh/2KwBNOGIkbTLf2/Q7WrmVbI9lXXfVzkLeunoVHK5abs88Ji4GMUqpO8gMvndeeqeEt9lWRgw\nFgPSZYKxdNG+3CqmRhUl4az2SmfZ5IWuM2nOH7NREwEsaE80ELxALXhNOXd3qsTV51WBzytJR3J2\n8zCzJEp2Po/wY8iylA+TPDNyhvcA2+28La02c7OTsqp0zdYgthQyNJlCeqtmp6tlxyKAkjckyUCc\nmkBMaOms7jrGXP5lWfbt/Tfm6t6i+Ba/c2OfaEjcDj5ZIvYRab3UatxjX4YiRXk7X7dhyPl9j5Gc\nj7854hUQpaINUntqPzdxi3FlL0x7jwpV0C/TpPLXiQMHmeis1E4d6dLFJjnZ/jD86XYOx05BEgMR\nQ3/Z+yJOky5JMynHxfFkJYEhSJyw+C4wT+Y9xgiJ4tVmYesvQQ9V+fnwMDjyqtlE7t+SUceXm36B\nJL3CcDzG/PAHxqU9q5YBs492NTkn1Nd4355eLmZzwSJEwGSmZDRGeQtyD7NbPRWbOXpBLPUtyyuZ\n51MyrnYZ+mZQ91ONvNCt8LQb/ppVAlEp5mxRFxZAaHTtkgBMP1jHruY2J/BFzyGNx1wQpEVOmJZ1\n3NkraxQTZsLrzGhYNI4qoPjiOwoNbMh4vkRaz9Upl1aR1qVlCoQefyDCplSntQCGN7bBl4+iklsO\niZ7+Io5AcQI0eCYGV0WBj9jziyDWKLP0DVVNAQF4PIOgayN1Z88X99xrdONjY1dJftxa/ml37+EW\nBL2Tugp10EkBxBz7NOFIJgToKE4W/fwfBrYae6I7TTX1ZSzN8LX7+O/2hEHoiIF7MP55WOecqfTr\nU2N2/HkXizfiMnOHaX+bVzpDx1sqG7X3euBd30Amml2p2uRk3+qIhvb3PnwNryvwQjhJYqESVPR4\nQfHFRP4fg4FAhp9Lc8k61OE/RyD6Jtx4RSCNN7rDwnKaPyCeRkJJ/kofTRTdOHQ3SlscD6DzUTCu\nMm5JAs/2kp06sOk72qw6Slh37TIVCK16DmZ8pC+I9hL0XGaeg9/1v8Bn9EOrrpxMPFPzU0YuMUhD\nCkuB4f6dUpY8IM9bQAgHJWQsAXhv6amnzYbJ0ssfqERETLC1GW2GtBRJSd/uCRjWw+BKa/rlwONo\nZPC1kUC2kHGtBhWsHEHF0he8bcpWTFUIBJ9g7t7QnbKDn+2bpgONXQOqCfsgcQ/AVkAPs1idV1R4\n5WRrufDvGN4wTx3/wPyNKiuwWTuheU04VnE4z508Bh6UxMwB8K8l69l53vcmWHLs1ixXMIUo1PBR\nIYjP7k2a/vWiskVfeJ7zzPBJewH440WRo9xa6gIa6wFRXYEmzItYy+5ANjb4abDIakgV3iyq04Lw\nSPNXdEhNJDXJ9c6RbUDW8YmJsFXiHvE1E7RHLFDJsZc/S8OOcj3IeIYiher96fwt6RVeYspqOdAv\nHT1LL9pnbI/Sp64XtcVwHJQekubgwg2gfMDUzglOdxWJCEziWfv9PbIEB8wAEyzQo+3TH59rAaIy\nqXV0bo29IR9ah8IByostaAuqMJEcsJ0Rie3TSfxGo0ffhJe6tucUNZDy6z7X6PE/hO9MTA7bAzGF\n5LgCDV5PDETneALfq5fgVXnCLjs1w4y7N2IG1Kcn7s7pHc2dpnai6R9oBmcwXijFgv+By0y5iUmN\nlH5zIoRRweaxTZozqYtrT/d9kc+N8R3njUAV635/t7mYsjfZXarIB54nK5evwOT/jPikj1EeiwVq\n+UMuLnGBtWA4muO0tktJIW4Xy7k0YDFHwYrKPPMtws/LpGnG7XB6quhCbzi0Y2che5ijJogqi56x\ncKSsgiEiI2sU8DMaECT01o9Dp8ayOaV9y9g8P2KOpBLYQl8U9vgaUHXOpiB7HBp98+2lbCLPiQnD\n7b8JvAHQb6ZWuwhWJukkMTba3wJvzFQjR2q7vFJ70D2aVCMWJOEogVysfs4z1LYJpaw35qczkMyz\n1/b28GI8sYa0xr2d3qN9A+axim3QTS53yKBTBbDHZbE+Od+RLubX09N7L8T51jb+wJbmr3ukOq/y\n/zA9pIcIZRI89NQTSnY5CBcOrDPiKkL+kiOiSpzvQRKfRu0kfu/7YxzJCzuYdm/2jMsnP8V8hwbY\nWbnQ0pTcmaDhbw+IidmJveSQEhi+TXFHH0iD4V01sNAggousdhf5U4ZfWwHHGG6tmFiqmja7aOIu\nnqgEKI6trhpdvCM1ZFz/1RyUUDeLq4S9+l8b14WHPOHfGKb1/dGk9wdn8iqOVtmfeA37Of4lxIe5\n2Kf52JI+DcEuSyOpC7ferp/tCjDl/odnpEkzeOzNrUbu90XN20qvJ2/2/v88A0jgcBpkfL7kx47I\ny6rVgQP+9Z13ZnsaJfqI8fh4Etwb0xg6DIlFh1Qt107sLewWQ28bA4OWt4KmDSrCUG6u3wsMr5wl\nfEa/qTIMGmfKZuG9nO+HygnAXVaMBidP5FtqVyNjZD9ZJ8dLAPJUB+1Kt4aHyjcDsglE2Tjie8iz\no4spl4ixY8RGshrbuR3zG8+f+TVtxdvCAa+o5iybW86YX0sonMCX5w4OkHdJxfMW1/liz3Zz4cK/\nxTrYYa0PjSG01EUOon4sD6yDrzoxUf7toOCcI+o2AiI/rE1S9ZSXZGw8LJ3dHA2qIzDyN/zVLgrn\ntBBXj0b9naehR9CjT68d4VvOaTQY2oOUvMA4wBukSIHzMokfCLSrpe1XZPNICp83p94mdfYBW3su\nxJyWRTngpyLz+jJ3rDu7j8YdphFdb6+iJTJEb5iPX0tzV58istJWVmLh1Ktpyqwb/glIbeX9+T+d\n6myJsZLoVwsqSUTuI/hnbjk9fO39stSMuTh+f+JjihVRJsK0ghL/hjeeWimNU+vllkgxS0uYu9GP\nwiAJABNEXEeEwvzcO2tMraLugy3wta6/i8GFg8Uqgg5e/2j5ozrr9H39bZCP1iC9aoz/KWM9IFJd\nJ9+pKN6WazLNXf2aFvO7GTxP6zZrNGI3yoIGznD+2xeCPCwxQ/2zIGs8JY+5Lh6STabzx4Q4Vs+F\n1U2nQcXqXc48vnFQ9sJVxwrBU/a29pRL+K7NqJBQhAYtk55oRQrNQrvFB3DJNqqpjdOBaW7dIK0h\n9XkccroP67Y/Jpirptg8iBGwUTBPM+RU/wcUTktgthmaXoAxGVXu0JhPVW8HKhSDLWlpCvc97vdR\nr9yWy1DOWZNYsk+hCaqaEaVp7NjnDtA0XqzrkfscpIYnBE9RNomnNDdMbjp0lHtdf3Iy61Rc5htM\nTqmvzbdjcShfYfffqTeEbT/q5KbM6W2yJF6wCy7opOvWiIv2XIilK1KwhBpZHaSNzGgPEFQYmMQE\nQK5qjvXgBnc+lil6wdlFiE6iZUCUrMYE67Cjes2TfoDRuGQjgGAzufdGJSVJFsaINzE6RVUdqkjB\n00dH0jnjQANxUeHHQO4KfobYSOcr+4ShmRmVQrZK78SlOaj1b1xuKUEpFtHmJs44E0hCOtYneIPQ\nq4pJPj+W/ib/QrXETLAYrxxu60kX+aEcKFzPCwRnE9MzGWYf5duFQiByDUlDEkQTEdZXqnW+j/+S\nAvj/9mfYRRMhBIqvR4BV/Bi1lajb/zdRKcTPkKmqwzrJNe1El2e+Et7ppjLjYj+Gf+hBWNWjrbeQ\nqeKI8PueTqpeI9ndiTZmy8WuUMsBPdXu6BHk9wdLJAuPY19HmucrBbVy+jNcCClPH6HEh5tr06jD\n1Wl/Rrc4d///lYQBNrBSUo+X4Js2YPeJZc6irHj5InoFwRsqv0oEFLlrlu/HZsyXTkqNLyC7/xSo\nMrXfzdPbGMGRnXDxATc0l5eAXFJIxelTLuHLlum1lKC+w4uBaEgzegU2AVKFwWGYP+6QtY7jI7ai\nFDB04u9ayLh8d4eul50zeNes7IH4vqQlzxWKYj7t1BR0f+VR5/aFnbb2FovW/I6K+TGeCLmHw3bY\nO7khyHO4OirL4X2dJhGMcJtwRt5+C6/FJPyfatYyfBjHYbtnF2BXeIQEApShhrOCB0/l2Th60iAx\nDcS155Nqx1gB4sd1aqpvvbJkrXv6sHnQljsPnme35tszH7M6x1VT6mfp3DC35xQhl0QG7VjDIX9G\nJGLZS2uKqSmAz/58dw2EI+zTVT6jMcHUGyl4lJZU9W7WZvGr0rZ+WDV6bPTwRzVqWlaDiq9MRDq0\nVyQM7MnL6ynbe+Fi7bMOdOdkcHgqqRBGWObS0DF49h6g1LqdKHpayT8vFJKLCaBmkk3QndqGfdSZ\nBrVKPISV8W6DslCOcIMTFtImVd7cUzC3cflKvECbWPJO2Elbt7ziTmBo75wLutiCfn3KKtj0Ffcu\nQeKf8NQVq7HtTQHrbPwh8jnGLNdVlqgkaXj3JQGYWTN0oslL8nbxO+2YFwRzrYIuqhUlAk1MB1A9\nKGUkTSnjHxFPXb+BBzkZMkEn1kyQQ4/q/7uhtw+9C3qV1vI7cruzLy50jXqhp3hTEIM3dOb9z51b\nUFUvNBqGZWXAxnOpWb82+74AdsByIq3zGgFnln+zuIBOoMyBrprnNDSxApRyQYir5Z9UixPq8cdq\nHwK+YYSLFJ4gg14obWRt39d9FU2im6x5B/rLkH7ioO+eN2MuVXKqzaxJFYE0hoQp02qZoMH2vBc9\n2ObcguNJweeB4CUmPYmSTSsZveGqfn9qof1lSfppMjfdNH2zAH2YJfjjmS+qMYePbMQwQtxgncKr\nlB6Vw5jYNGxfpy9OkCjalnazZLmYtLiEuaPppjYR2Pl8dC39Ypzk0XEyverF3eFrSzRtN/j2Q8ZB\nvYmNI4SC6TuL8WuIlVsNwZxaqCiLCegdrhFoZJfSQ04uF10qel0rkuryFijCvp5hE+EICBqzucwz\nV0Cw67t+Ju6IpCLx++YgH+jv2+2z7H9M0c1izK1WMZNLYBd7EMmBohiNXM6+ci5LTT55JCh1qYdo\nvn/flV5sG9bBv0lwDybu6AShnvpEpjD/Nh1kenyagSX+vVSjCFxzqQN9Y/6ZrJ8gzulmjPyfqSeX\n7l3/jSE7O7AqXSoa9YeQWNw/EAsmLQpCmbP8PzcJBh+zzMgNZwLQJ+O+MrAIyR+dmWe7JQVxJzGc\nd989343qQjddHI1OdNO9aCOZ+grbhP6ObWhN9V1TMXDg42trGiqCPse7iZwRmEIpbFmpiwLWy0Bb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yaZYFgCAdbiWG6mrs+IIXXe7x/uuUhJUTV9gSpjFcVr/LZmLLxH+Jg7odw514/\nz5PrF1cUYjDakvwj9D0JxvAfe8w4egh+yF6cutvSoiUYlqOlQj1G01SwLWpx+GUsQgd2yNiiNVsR\n7zFL5QKUCnatCt74mCZtdtfxm9OWqC7LgFPg3lEmy3uYMCGKxuda4CMjzeFAmWpD5bIbY8haBlgr\nRqo3r2w5muJTsgk1XsKnzjMH1MkX/3wqK4T1ZZkoBfi6oy36nLxWtfgIb2y1IAC/UgVUqCKpWet/\nVGgtTJtoBsPaySK/Wdr8mXsd6NcieLqp83CGCkC0P8tJ9bZjTMkIDi6b1PCAAG07tLAsi7GdThyr\nSZbfmK9Mad2n05VZaQ85fzzth52fJBMEPlAdSS8Q/AeKQ6QQ8vUKzDchn6aF2eApAMmycb+ImU5m\naEsX/DWptZnB5UYX5SmzwugmtQKIl89FIXROs16z4pxodYNUv0LOa3gEOopJOEQUiu6GG2KBcIYc\nBvbLbEGPMbGTjAG+dT2qan7Q9twu368Z8hkHnD7br3e5XtxPLWialaSYO6U/lOcSt3MoTkfwXtHf\n41NsQCQq4ACpBGFfWb9kic2vU3fX/86kZeI05OidyM/A0fEsBfUrzFYiTpT+PbrjmtIrXrL9HRCv\ndFIm0Kh+GxKEWZ6Dk0CfGq4Me2yx8sSF8B+B4UVSTyrcJSQ1J/zkajZL6VOXd2XH9pNshyWGdr0v\nZ+E9EsUm+WowElBsvyP+2xF5pBXw4Nh1QRpA0R8B0Z1hwuTKvmzMyrzxs1J1/V9gpxnONQC7UYoK\ntDnHH5WspLO4CMHRjY4XqOwIFJZCHbRCceMeTRjmoiQ/v0nX3sKxSE3ZID5jOinPiJCTSkcbpVX+\niHFQNdXpVPwaZV9Sk88xDRdb+HPucUDguJaugq/VAo2IUD0Od/dD5CYENob0+OZ0nMMyusqKU07G\nb8SwJlij/iOaYFwXVWgzrPgg9dEnu42t/mB5FAFAq2jLEIq4UMW+1dfoqpz+L0R4KvnaP661xIVb\nnU0Lz8NFkfFWehVbqM4ly2cEQD6mj4HoXqWXcyleRF+Sm6t0/ieNqEUfF647TWEoMb/Ip+vQdzHk\n+nXPesy9Q4+MWsQpldicSEVZ4DY0HJY2iuqUO3/gisC/lMw76pz9sE6/LVMx6Q0I3ZWlY8NbDl87\nAhrhSiFB2Ld3c0IUrPLBlHBuza4NNWIdj9KIXE/FTLvOdqyDe4JP054Tc92zWSZvlS11dksOHw6j\nM1K0qoIf0p/A9/Q32/B+j1LSkO4p5rWPzqST64cflqXNKydvx72aMW1FgUjLiVZSZ6/ftTySaNBc\nBz0FLme2Zsh7RP6jRR0iat5nPe1Xi1uUgkZp99bAHRUvs6J5y23MJoqGPFJUAnybDYaGslYFCeeb\n4hMWmVnNwk9sLG8OYBdDdPhcud0zrjRMNUgbd1ERm3sEGyE3GlR0hVcwXN7bPuw55Gyc7Ddd6mYp\nplrfLoELuxIrAt2Mr69XVZeT/GOPqE0kgThgOcHWAFGuAPqw9WKlmXvUTd7jPicnwgWlme3PdCPt\nNMgiMyDx0e0QR821hXsBq8/OK1I/LUjsA+979DRiLp8J61ITwk/Z61F6C1mQ933VC7p/BJxzuSaX\nN+bGOfNz6+v6kKYSifpcj1EM36m90WcArMdYeV9Ngs51ippPZ3vrbhMQrkDIDHjkdRr2vJbonbr1\nZFzuCL4pmSuzt8984n/5EV5OeRYBRIbnuSOAXXH0Cksv/rq1BXjJhxObiC2+aSq/2I/YbFEguvlf\ncasSj27TVI8GS55e8WGzEguDRVL0jXMjqJJy0G8MASvVtUpKSbtd6D5yh+GUtcu+VklUjm2/33GC\nKuzEV4Zhp42Y5tl3Tq8H9fnBYQj6+YK6cwdBAUyHsxr6hSdP+5mdJyUZiiBCE+fghZBGDUqPfQAK\niSlYH030FjI8xXQ0xzissKDwweJVl0PrZdjhyOLZn+v8Yt5iLPE3A29vK6YezlgbU8nxXktNhNBy\nBhXwDFTOpujC5XuW16QyvF2eEGpaHD3ZQWk+ho1lQL+rNwyKR3aQ+FpO2jaAtOcffAydhF9VsbyM\nSf5j6M9wvR+qQuRfOLlxBznQcYyyxJbuiuTfdtU3ojDSo/dD4BFIf+agX1Xsb/oyubt900DoHy5G\nw1X6ycOCuoyunsc6L1bUidZpUIEmoONb1c17UVo7LPYM8ArM/lGYUO8TgvL35/h1dfg4XlDSQEVg\nF1NjzPNrw6Up7gzrL3OS4hpAQdPojj5TBtZsdo6NorgTxFLhzNzWrjOzHywDbsyEGCNlVBA0ONKE\nrzi9maSghRjjFiGS79m/Za4/ikfIjLyyC8b+IWyDgAzpBt8BvxBWLkxr++JPRYwmpZnxwKkZwibm\n76sk5jnhDKkhnahGTCCEqQXZmoXK2jYfo7JSSsKhGitBqi7n5bBKgndueFfKA9S12P2nSdmssKd0\neQm3bqUIdWLRVPU2kTsNOnN4/kBJeRWtzNyzlkUyipo8qaR1RgasLJinJ16TOVaJHHzjbNUcaNm1\nu+C7WELadK+LNs9gdHU2a5+/953OdST2tekpsYWy4YjA8iZfzOk5i3YiOucIGcixNR3F0S6IimU8\nslj9LiCHxy7BcB/DshcGVu4GyrrWY10B2lzKpNZ9BD04HM8A7PkDoqzat5Io5UhsIBPRd4teBvR9\nPPxmJy5YYXlS47I6GGELTxzBb2SSU9UcLXGhofOWmJfQ7kY8Xrwx1KV06s1i2zm2rnmGgonAJwC+\nB4JjnfZpqaw6tzfnm1tdS2iwsie8EN7mz52yQCWUpqmLSGBGLbhV3FcE+HfKbpQQLY7knDtTS1F0\nAz7mUx94snnqG+N92YnddEv1nr/iT+f9IhaslXDcpaDQaS1nj+TiS315Ivm+dqycejZoAP6KbSN3\n5pRjVDINWRAoTdiy32nr6HYp//kBJj2MU6V024tQ/bwSNreC5BRnK4kVT9pgOZcQMwXr3FiZE8Va\nuyovlnLppp2TJgLyidXK5L46zoOiAlPg6ir2txPsjHVNKGLh4UHju3Ef1pvlHb/J073vs5ieW8V0\n3l8e0zvnn88J8Jh4j6Tshn6v6svHVgxRjURfFBGLNwm6x8dCeRs5Gtc5/WTV7tDTY028JObmkwI3\nWl6vR7khLM6IjIqGEAP9NXUnl3easdQp6R0WgwCN4mbXWMIdtTlfCkFlKt1Lr1ZOarkMwuKErooW\n338DJ9SEzWA/GjRSjzhc1w9nvXXxg9pzqD4PoR0+UnkCb4K9AY93HQP1sqkP7aXmg9Vicwv2+40j\nyaL+I1eM6HOmexLvwLMdklygtpWHAJ8nSau7SAlR0wpDBjI7v2iqCAvepjygRjNRyj22vGY59jBi\noEd8u3ist4XVXsFl6WlksL3PvM3+BpOqUi42vPjojBgN0HFlr2wUjamkj30ks4Ewo0VOu447yuW2\nj9pvSN41CNAO5XoBT+hL+iukUd6W5cDfQgWutfamqX1t/jEl8INqDXdmNnUYuIwK1gprmt3k3YpM\nZz2ilJVKGUJi0f5qsdPBHPjR4S2iSeAXI0WenH0keTzfP5UHLWzFhA45lO779u8ZWfjVPLHG9Dnh\n4493GnDM83S0k+PP2Hn1C/EG5uVpE9haI+7ie4r62dr5buf11vLsCFe8mU062S5YImqt304t1WKR\nNpYoC6ryvrzFKSgs85vhuANQ1c1ATfHBu/jLTjiAblbLk2zC1PSaO1RX21pQUjAigO0iX7EQaT+8\nYoobs81Z6yzpakzexene7d4HxB8A0NtLFAVYrT8aoZ5+phTBQP1Zjs1fV4F5OebN94q8ePfhv4TO\nkY61KmtVZ9d0XVp0YJMA8DQUoK98QEtK/+KVkqLcfWJvYIvauSuApTM9rzfMWaj1efGzFatQZI6Z\n1aeJ9NzDUzPAM5jmGWObbGnhatxa5nYE52rJpIjnlGOMRJRBmBvcsrOipQBUcUNGHC15I7T8z+/B\niWxKojR6mY2L53qLv1k191A74CtIj4f1uIICZ58qlFkr4VW/Hbo/EKnEKAt2ePaBvWcm5Rr6zi2L\nlBKPFa+Ios62xRrhUflD0PJYsrh6dRh9KbT91lptADZ237WcfaBkyZ0/PkvRFZt7XZ2ky0bE6VRV\nH/mWp5ntkQ93XNzeZ8X8qj6JRxqHVlhLcoo6TT7OZ9KhOipk3ZLN0D+1UlYmacZ4fmFGdAmAg7TT\nIz6VouJtywPQNZ89NeOUqUfzzK72kmGsQzbxxZ6RNSFPNfURkDlRTHfTLSBDsAf/n8GhTA7Cvtaj\nhP4yzPAYP/vxnG8dzj9hKkU3iYwbEx4Gvku7CedxmF3UKLlofiq+ecRdXSUv/TW+phNUy7IpALBR\n9wth0ocvom3Q3WYrHJbKGh9G9abErJnqlde2tjlsAbkKYNblYaQYLXntChIiu1GRtpD3ExclseiJ\n+ray5fwS0UbQVHAonwKK0GDMpo3aJkOO80BEZvm1iHi14xqLc+JFT8LDJ5JLK1Bm0uU1Cr1R6ByS\ntP0jVWzPpCv8MprVvc1xXg3m5kfUCwXLNq0pN8ngB4VFoapPP7gBauSDWLrgFM5dwG1NaCn+1o1u\nTaacmRAche8AflyDeaVv3qCvVI2OJLrzFhw52bS+84ECj94bAE8HN796ZRKQhbdF92MfQaBbEVPF\navGaYISMrxbA2S7SvAIAU19AG2ZQynv0e+b5Qjhouf+1XAqncv40aVycnCEefsekCLUDB/thbO/V\n0+FxW7Sh3UMxkiXjzZq0bSPjMgVZVn0aKC6sDPyb8J6m3UJdCp3ZWqqsr64aFeAy+QBfzNHnT1Y3\n+TaxubKmZifd48UpfjxnaKRTwpljpyr4wk4Ggi3hMd+TRu1aocfbicJxNw0fkzGCpWeqbCOi6Ptr\nOX0dT5WYeBwnSLxwb+nN5+TTPgqTw4lP/tjwTH+kdSXI5PKcEKc/xEByUJGGhDJ9ta4x01A1FQJd\nWrX4U1AeMemO6YUG3z89qTv7iUogrAHHVZ9FBCfoByKlqWaQEB6ZYR1Rt7rOVf1mpvDDgsjqHfpd\nBPU5H88z9hKFlUbSWRz5HC3GDdDYF/fwkLTXspy+VrKNXJ+MVRTCyeDlouO4c2xLsBFXQXHsfKLW\n919+JIMicbp4fH4/l0Sew+x8uueBRbphrmdmYPeSuTxSkUiBZDy0/ySevsDL46D/iwerdRLrLekx\nGK4icfdBcikn6iCwPrEVeYbFQfb8U5ddinq6xL38rxHWUOt6wXVCJUbfGBdEuouh8dJRUDQUN32G\n3zH/Lt9kAp2WaypJG7XvLOJ41AnuctB6TtCGxqPpSZqHVyqDWAHPAOToZNdexkN+OEURseiTKZWm\nvwxJv4+tHb5otBUBZRbpjFB8TlRiQsogkllssPlmiKyuowxc2j5FI79ObJiQs2IR2eHRZwLxJX+p\nLp1fMTyb0rF/amW3SPafbH9I/e46YBQHNU7aIK47dgZ1cUxDPlvvx+yacQWY3v1fRJrHNDqKvRQj\nP7o9PObsI8BlHOIhVeAw20HbF5LuFABIaEK0E1CChk6HCuCGbuVF0CoM8nwxNZv8fkWOXas4eg3d\nc08Jwpzu8K27Kfnf/xYCjObMAvv/oFnMApFYpoG1CK7B9csxXgiIS065y01qhDm0tYMFrW/skekG\n2QfCIroEboVuYSOuG4dVUkTXiSKN5843fCyynkCp0+U8BlH7E4j9GIj9iafKWL/rCVEM6aE4QcNr\nHSXgXXcmj8YALRJSv0hyQj7GgWl9rYfUKAUbJWN/wXUXWcEE235umHV8my1+6Ng5QxDVYH8MNpKA\nw6stI7j59mBzdlO20aWhdZw8IMukgmp/fXVBluWxo1PQF4RwtsPKq1Et+Q97PmOy+CTfAfIalMp/\nenM1rIZAzAbw0q/bQrGr0iWK5r2hXPJxHy0hENNqPOmwlzdcs70VssW15hSiySgR69u0s+gX2NZg\nwPgUKUtCE4uq19l1E/XKgNCuJ9Y/07uXXhZxwCwPQlLR4NUp7IIw/27iIyrw43FOUFT7BECHLAZn\n51sp7quH+oIW010ozyNRjfeUxXpdJ6nCGtSS9wChPG/J/KPvzC6l3Rqi6TP8jE1vfVlF83QeZeV6\nWo58DWRpHiidgKgq6GOJZ+XCYrsp0t9wUcbOmf/DIxonX/LGS2Y8lQeNXzXvSndiOt4eqIVgSCXt\nNHM9GcFg7WDmFhzD4NgbD73j9HODn9cf9/aYzdr8TSN7iVCudouSK4D5vbnB+66SQzoRUEMHvBMY\n68nj47dCQennrUcNCf2zIcsyT5z+ibBptquc1XdhpNmu/TiRL6kYp/pt2fYliyHt34vvc02ieF/b\n3p4VXh5r+ADgpEhaqESjQfQOPNmDtOTolHAsaQMqTcy4S7ICJTZWTEDKo9jn7gbr1uwRbVNx6aul\nqfpXeFwa5V28q1mc5HtryB0xBEBjO73Ry8K8Y/15x5C+38nFAebHCIfO8YnsZE5gxX77q7zbTVmt\nnkK1jVxme8MAPo/9iN0KOcGaiMzANOPLaUztcg6M7bad0zyONuZEExv616oOA18P0lek6moUmJ0e\n8gixWc5H3e/3iDedJmmMNZW/sGwOw0UYulHx3lliRDoolX0Qt3xyr4HoaswQukvaljOYY5UUPYYd\nT7hmnDtZ5+Jcok4o2RTX37CXkuROTRt6fS/iE9OlL1v6eL1DUZXzGtnQbQzXI+kFypbLygONmgS+\nraS53yWrLWY4GfM4pam2+RJRVlQBg9uOzln5EWcPyw/4BM3+RshErmNUul4e0rtBCEfzTwZNDlI7\n8OPWXsP/i2JBa350fJtEL0B68KvuSQNMaknJaorFX/Itbgxp/l6QU6CJBP/bWNhdg0B5JqsaV7M1\nGppWWV+u0pWsN7MecF5HZMKqdhNr4t+R9ym6iBzd5IITFkxc/GIQktUiX69Xex2rs0DqfEmYRz1h\ni0ghB0nRRXTlq82PbND2BOHYUlzEHMZv/fRzlBnzfF6h6bVtgBBhPq0tYYEDiq1VC3G16VsGwIHp\nNWGwTnvvdXZ91vsNwbSv4Ftffw2wsiAY2yVjWtl0SUXm2U7yQd+iluiXmyAY13Br2es7pUFxkrLT\n5yyY+eul4ayOi0aMDaQawGsDXTXlmnWEltb2A5NGk0v6hJVB5hOcgNDCSnE42kN8lI7odJ9+TSw7\n6DwHl05hOe/WyocIDRW/5nQH96Ar0n+xmmYJyoQJKOR/hGXRxJBTuOvcGXANnfImSiEouR+bn+O6\nlmJDOBB4T1LfPsZQSjLCef0M3QODYO4W1xwRcJLx7d3JKEww+8gCillzUvfMPh5b2d9i6Zw5drbV\nK4l39aVXK+XR4KYs36UC5FXJXulV++T9Xq5ArQTA/mvFstNnjgqwSltDHLHgt4872PkAsp5g7+Rx\nI5VEx7VmKWF1DDwwtP7vnWfaSjlnTd9fdxb9mpsogBTc8w7m4LKX/40/vbQQu2hrUSVwNNWJVbAs\nqbxvMReLLkaCJC8paHSOwpNcbFesEOmzy/YF1jMZlWgcSb+GNPMXHqAEqkNAq2nrxQGG6tSkTvhi\ndMYAVtEbkAo8FprTOlPkmACVoheittPJ8IFC/IC9E9OIz+9AnIFAXgL+ocfWFy7w88UiHknczxcv\nvdoN6M3sWqyfnvJsb2Dyy/5UJRdYQrxg3DCcu2EZus3+zDw6P/y/15Ko8Cm25/sYe7g0JTaZY25E\nXbU2ls8dR1UxKYcBt0eTuBZjmJQhlQ5zcExHn+bNmtncLgEUut/h2IS8758EOvCsNlLQ2SMdXQ0f\nsX6yYGwUBhE8Lv+RZM4Mt8bMkTBFmOKFz6Qvdn3AlEvtqS017Bp/m+qOnnLZnthFRTp/bUgwcJf4\nKjLNVdByxyidQcCt58fPdSLU0L9iDFHaiyQql/UpdKDklziUi+m3/wIVA8phPM05m60GCl3CsoJJ\n9ta6zHVCGmSDAj2n4UiaWcYTdFlRRK9TUBSX6SR+aQJnQOvptHgbmOV1zyb2s2dlwReguzh2fLKT\n0DVDN7gsln37H89ncwcAZfgHRtVOsLRqxL8j7XqG7p08ae52W04CzHDg+r/0n7PuxFgkEY+gg8TZ\nf4wjhHksUjewgU2yaWwLSI0Ua55zuGnjIidwdBJhgdrAmJyfjXnY7esguYV79WxruX6kWNnkemRN\ni/TWWEz/lQTxwcB8JWiT/pQ5VWAE5+19DrO4feixlcmUTlaLtuzKIJ8P4hEwxuFTECxv9Xu+gruw\n/Rn3+AlGrKvFetS4fBK6KJ+NIb0bjhCumHk0t0SFFQwgBCtlELoc0vvsXWUDG9HHtKTIX+S1Oa4S\nzJVFDRTF215DfAIrhzxq3K3y/6DMDPURs4SuW+98/jwegwOH7ka4Z8uODnVOPjWnA1NLPn+bqsQx\nlYIKOptx4M09BqSpJJrmnaQXQZjWA/Afqs4WwpUEgFo+1RNACXIlIVyGQl2yAITmbiCqbk03650h\nFiq9AYH8STFF2W1cXZ9XxX1PGADjtCWp5Ci1pXg60UFOSWrGHMxELVAQDwJjb6WoMHOTcxQScmVz\n26UgHzQEf6HbhyQMCZRp5zfTsqAym+w9OrHsfH/e/EdjLJ2wi2fO4TAloIU65VA/OEEWFoYB8hyf\nlj3RQepiJ0qI5NPacazneEvNKVoqicyyBb6axd/+gvzTwbyHv0H6zTIOwgXgrf6ku44sW0cw7z/a\nhXNdvAbX0JwTWT5NV+6vaVv2bB1ob9yQdCM/sa5inpe719Gf/ConDM2baMV+/3XnOIALI5xHyCyV\nft7djjktp+kbUDRRDMDUpF1p2k2+O57mLFmidPTIIGWVRzkgbfCt+RapeRTkPU+NI/oecbFmoTNH\n9dEyo14ETWzqfzToBCQankkMgXKKL2NRJuE8rczNRdrsG6WkMK3VfzkRrojUuLaDz1yfAR7/eQnN\nW7KNRxDZUi9YItcPxra1P7XqAMgclFOb3xgKiLwEX9xlSh8WvB7IMe260DnnV27Vc/Rz0lafnJ+C\ntag1Q63xBX1rX0lBcG1fExR3RgELbjB/rGnjeSl8oXq4Nz5nT9NRuCh2cxRvs/FDZ5qvnW9siqve\n2ZJlwVlmzWeCQp/UjmofWX6JDyinOkprJGF+dWU5j/RggfHtqnf9aEGEzPJtnZqMzH291KFkY2RH\n3GcmCtwEkCdhSFw1N+TnOymEVLjI4GVog2wQVHpM8jaINqr8McAKwHsoxl6J7eaVZ+2ftiEuFFHZ\nNtyc5fmBWYs/EZ0y5ioYNzX/LvD257mmYHvSWnPd4Znpmfs/Xxz4OWgc5XciL6HZllR+sevY165r\nE2S7ZI0j97sLA3ffkC7m6DWLMC+4qje5Fr7wCQU/XM7B9Dm16AWUcxbqX4YoRVMxrzwYS51yrl0H\nnBpbfJC1UETjHOHn6yc21opRq5JYiMZW8SEb4J69odFKg0L1tvOAIdzr/m62AwUBarRp9LZ41Hj3\nWHfov90lifyngyQlhHaJs7mQSv/fSmX8D82tr+hB71sy1j44A3dSnqldTn1B2KL/tb+T583xi2Mu\na2SKFr0F7ZuvMo+jB0/57YKdIi/wdbPqsXVQa2YWleMFjhTzZxhHeVztYra9Y+HEptMdgDFxi579\nCLFoTeAFwlHFz77yHCdZ219B6+7TydsOr1eNApS6VdHpNT2eD+PI58er5WOpYig0n+PYAq6G1g5N\nNZejsqf8EVafzUieYrXD3hHIRxOCLl76JdIR1Hx8PC7V7UBUfyI2ZATgzEODyyELuUpUsm/5NBkO\neFfWZJzepvojby999EvgZvkgZNjIUmhRj+Z8BCmFjxulsaKC9Am7LKnWycIg+vjN46iTNCcGIA8j\nr/QQIB3UlLkDmopL3RyrNet9PmxuzAQIldfM2sIMDOp74ePCpIjTTrRR9F+Ana46nOIiaLhZMzBo\n4ORL3jYW/GHLKu1/dzGFJSR1XGe3zMYjQKWe1TjH55lB0nDlOoBNMxe0lPVzyR046VmwPvqa5Map\nfRs/OZJKJ3wLCmyCgMeBBmFN0rZaQrAx7u5FMB4jqFDXMFqtyFqwWSq4fiEMtF4TpmRQjguZGRIy\nxDM/IRYj87ovIgvHMyV6cm/4Ug+YXLs+f4j4yzXQdj+5/gotiH/9vJaVqivH3jaM9wbZIYLwhFLy\n0PeXZGkC6IqWfutG/EVwcEVywbg+P4thk9nXwIOd3pNEVm5Oree5aTRGktDk8cLeEK8ghqxmve/H\nxfDy6niCPRcnetRWjqXNthq/yoKdjFVzTQ1tZJ39rRQIN2aeokaKA+bq3ssZj+iErT9APeC2lDLH\n+Ww0PCu4F9V0eGZ9QXkUHFmHJGbm3Gl2tteio0R21aTACl4RezdlPqmJ3meXenFSLQ40tjjCksJb\nFhl0MaZrJ5/9R89Od06MI/Sv+n1OkSRpRR4iGkuC8R6jXzJ19dV0fgbejsJsb4RC35O+QYY+7+XD\n2WEh8neRXhXTBa7e9qo6MGGu7/wkm/kjY7EL4JDLMjNaWCprvXS168/b3hnfeYCxz8cESURoQpNA\nNLGrG4ozcluivvRtdzF8lHkm4ZfKnoCJfk2eK0A1hiamd0lB7udV+6mYRq2vn7tnpDLKYPmolZd3\nPClcT2C+2RSH/3pS0dU+xqX1oVqZCAw5Looj4V/xU/h0zH29GeS8FxNMMRIO6KLpz3iKRpPZzx+u\npTvyH4OGU2Qd1dFmE4tvKuPNN6f1zidcS+KPdQXj8sW15m4u8Lv8i5wLu5yKtt1Nun8w30r36T1q\nCPZwvQ078p4GAjLijGEm1f+BZCU0GwoQnx2VvgXVqgC5DKe4zzy9sD0xNGWfcOe8j4q15V0WXcAi\nx+nV04xPmz9cRqfWDs84DdkHs51hJF2LnyiUa9+e3vA/PtbdL6SUZt0P/9rwQUL931ryJK8R9IKK\nXqZyxvLgOeFHVw9JmB9VRC0N/fGxFO40YJHzuJGvfTFs8KRAFYYyAwLrZ+IT29/qjBZe58i/6ORm\nX1fjg4hGZDiHVZE1aego9Nt1Q1sgOp2l4ZqHAjJB5vPRzoyPGRZSCjnOFp4RVrGe+7WU0/X+AnV1\nUTMJxS88tKC4qRK2M8rhhUbBmL/5wV0KcFWWxBnce1GAfzYmGtItkvo+0T4sj76FLaCe9WPr4je0\natVaTutrKPZHRbNIhD2ApfPk9wbWhsr/2DQS3Z/zQjT+k95pzD+Cjf52LJKmOuHbr8Y9yHmp26yM\nzbJmEfP7cJu69inDwwy4lILavEWvEuYI/CLLuGz/koLY0wMl54ThtgPslxjqRHbGbaqwonkAvk35\nC2tc1q+gWjCau9FVdnN+cp29l7rShXD0ynr+CSV/ssGoCxaif95jCwRYRrI2mUIKzZ3h+hZEKQOG\nuI0eW4Emf4o7dremMINY2YbQb70027H0mDfaJFca3pTDh2mKfw8MyiGsxjSBa8dIC2XwF1+CROj0\n0iAXG9HTniDqQxWfQMJoLY5Ow/+tFWuWqdgrvK5GP2lMXF9xEXtxOakfoxhM4v3wB1f004bQVrrj\nZzuiowdpAYJ8Pbp2nF4sCOeRYyed1N21e66XRXATfnPd41V/aApl86jGquhMI49IvDp28haxNNrr\nWbJLvP6x8/UT3fjQYiIcnYhJh+EF6HbQA78w2j6E0bGjXznxTe0KKRC9jBn3TMVHAQpr+5dZgav6\n7JFyjO3DCh9gsE6WL0Q5EC63MdgQXxAmNVol5ARnT8Vg1bPZgeM8iGSBJbD+kP/o3tlwhbIFnnQr\ncLPgY9+PUI4rehP1EY9Bcr9j100UV3RfYq2yaUiF8sf/mKjdZm82D6sOn4oRThUzKb6CjpHShZws\nMSN38IDqWpXDOSTonFeN0DQligjJPaU7Ep6NLzym/RqtChzyf4uVuZIGl1YP76RuDwowng9J2y55\n8nFfLGkNGw0GJZreWdBxdsBzK6FrNd8pyAXWXna82EcRu7HmpMkGVXes7H42ty51HVOl4C37xPDD\naJKSfbfHI6610lrAw5jbs6x2N2ROn3vcuKHxvj3+VZOSV29Nwq5Db59Yqda/I+UNk4ZaHTejDSVO\nOYrYPC7XOTuJ3vSr2BwI9bkp3Z/89O5VMuPU7GTJhqy1vZFt2ED2d0GTHNThPCqJ1v8ELzDIISUy\nAKQYy+XcFsYZXzPfBN7R/yolbd2PU7zVChoW8vvSldnSYghaQpH9Y2hG86uM64bjqkrPukgWpJTN\nArmSv3ofrHMGtuXCDpGAtLjWlYksnf6szzvhSrGzVSvVBN85Y+3w6XZOV28B4cOanKcjKsQaZQdS\nsilardWJsOqraoeLbbk57+YXaISP1hCqk5+NheFbKdX3MRNSOk5KkJlcggMswjSCGM+BJpmjJ9yp\nhM0mWEVQfpWVWPJfftm8jf9IeNbHioFW2QITa1KctOrVIzsgZw3J7hFmjwlW5KuljXZOvE25WPEK\nbfGJRwnOC2j7uGuCP3at0fsfimTQ+5OvGqqAsMbRaY28MtlGd4zJBI0HZFsG9ZCsYdGiPddlfoor\nLvpLvffT6Z8FcgHum8iSNztDbwqpuozlXKH6caZCKHdBOFBUQyxmA6/3GNZglJXKNd2vPW1ZOawq\niZjOMKqDfDoavkU6g3WxsxsJS+0Sh/Q5F8XYzYagjO7jCFtCoKl7XL5BOnrF9IwMiGkP2fiNDX4h\nwG7puming4KhiLp4r3WsR9+iUsqOpZoTPmhrYkF5LgiX9irJNz/YQlBrZS2Gk1mkZEKLasXUmTs2\nRyCcQANOqowitygDy0u99tre5j9eSNIXzzX6EagQJd+qsrv50hh++6wTWxDRavho9D9aVVl8XdGl\n+HU9F2v4L1E4HhbxL3tFwb5bHUnlcz8wOqsC/mqmWdi/SCZ0jaIG6jZdGPbQW1whZih7ynbOh4d1\naMAE348HZeAGEw4LQ4L5LWBhpKnAymTk4HdmqNBlK1veNUnQ0MVzU+SNasXIz+P8CpUznjagxTHu\n0N2zbIccoRk0UFjw9HG6GEOseQFC3i7iOG2fNSJ9CQwQV34RJVjRpKXTWJl/VKyGhPG1RlUEACx9\nLpUVCSrer+s/4iXrVwiIQlVTWIkMj087j2Aqa91UbtwDNRZG70m/8CwgGAP3eOGu/ABe36+GiMdh\nqFK22BwcE3UGZYUj1BrjLmddjhqDX8B8BqtdhiYgidb9AekdrR6iT8SCU21D+86KsgscDKl2IhFD\ngKvgR00XgGdgEbsX2ZJprMMdFWEa9PhvIDjSSGcgnPLD2Q1+bOQ4j/IHIcuFuYHrvZBuuGuHwjDz\nxv09jgeeA6IYa3DIT4gxa6Cvb5emqYXSRFoj1CBH9T7HDjXR664y999OtkXIjPqtQNc4KqHiAnsN\n1IvhlDAAgqr3C28KfPAUXacUnVtsxud4YfXZuX0Y3JDQAf4cnCeUveq6aa98moi1cDVX5V6NHVmw\n00L6SKy9CgPWa1LJEwPUmXq8XlFe5ApxupliU3HVu4cATMHmUiciQW4imTF8r3YTXAtE8YDId1Oe\nJz/d+7P6CDHBK90hvdwQ0VFx/mxkTrd14+RBCbW0UWDuBRNMcNc1X9PK/WqYQTJAcowQta5A6GGI\n+D1QxsMihRglobsIupLZ+pva6iEWALfrf3TZparJryHeotacj/845z2/nuTPHcK77Fbp0LbsbBmu\nQRReptbv5zR6sWBTEciRgcZ1Nch1+Fwjlsi9KfPjqAzakbpPokOiNYB8vXBiD+UnQw3uPDrCOJ94\n7ordiFAczuszq08lD9qre7FH4N0Hlkg7xFvh6S+ceKgJnML891mdChy7ccU3DSHgEffBD9bAQsaW\nX7UtNN630m2xfPaBUIiglvYn2ZM6D3dZDWBLSyQo4TvHGtOSfysuz8p1UULQlMssfDBNxj6wmxsa\nrNhbqS6TeqDJYZIR5r7+sMxqxN1ikhHLVzjSiHyusZzG+ixxZg2/fuQi3LpWwz7JHLLwto0tWlxW\npmDS2vn080DPNabn5S6R3yDgZzUC+MQSH0Sj0GvqzPaN77bQnVdMWVQfIjO5utnFrBqmzuZxoGCM\n5FTiBxdnu/jSYUbAAPCpxRRk0jZnJ17jlz/urCWy7OYKEI/kbzRFskHHv4i1A35lOH4B2Rrs6Mt1\nklKl/k0xg9AhSS/K8gXWaQGKIbCp54+Eti7pNxUHdnHZeIlQyqlUrB5vlHI4LAhNnOT2Y+JoM9Z8\nOxw4poUXLaURLmFS2GYZnbVyCvtJwdBhYr4fuHaEV2Qw4ZJR468827wxhZfWj20HmY5RXB2wilgN\nGwC+dg0AHxfqh8tngBheZujA8fPxYBMFQ4/gxUh8uTdYtyCVyxtFZcC3gfuP/GtTqgYVDWYdy/hD\nJidnTz9DZ9KHwp2KnEEQR3ux5YgYmTQwiM9ob1mSirWm4vXCOPc5d4KmOvAlnuQFzAjPV1qahyGs\nSvKiOGfwWWzqZQ6pnJB4HsVhHs3kpipQ/YT0a5KbCd0Fz4ZE4fGiFC+fGIYXg9MwbZImHF7yMKm2\n/Cu5Hb9uoo5VBcckpKfr/bn7R6oUIU+stYOBCHQlVLQGKxxSch/47TJXxnInUg4O51i6hMs4NkL4\n1VA+93jsmPM1OFW/2jzGyiC4Y0AMIbv8Uwun6p7lBOJm1MbvDqGyTYE1SI5iBqUBAvR6YCwaZZkX\noGXe/IdHFsCnbzm5bZlj/qflqao/myr5wA+WcyJgqm40tah6CULFT0IEI1PKjM3uLxX9VpkCKGVh\nc1QUWWVXk+uhjrKkXgJvwrkYNauthB/8t3Xg540hQxCXzYig5kArs6oGM5PAfKWwN0b1uZ2RD6Am\niDGt7xrbJUSHp3MzgG73TBbR1DK715a8pshKt5DmOXFcjyWzuFmI/InIJW8+bjT6dKIIjg8F3cg6\nav0oKe7fbWerz1v9iipZ/MflRAty8Kq5p+gsQBmi6MC+ys8Mp6X//Sk3XGdWr5M7d1uymZ6NTp2h\n7+nj6960gM4qOKjGvGIHkKXma2LOU6c/RcRDjFKzbmPtGfs2nMS8w3+IbRv3IGnydz89OfgylcNk\nkikIXE/MPDBy1Tbp185pai9avh8BHzebm7OMxMneUUa9hvscv9eIZ4hlnTOvdic8INt5ZHKxRkek\nsa8mAOVMIEWpxDq5owpon3iABhJLdgc7pW0AvpJp0U3cpwNBjkcDlgCytkLy/NrrO4kdkoWjgq+I\nwxoSLZ+eSPmRupyfUfBgOKFhupvxtphUUrh3JoiS67YoaFDoO+U85IjB7L9yO44QxwFbo3HDpG9I\noCa7q9tq9l3Xc1eWK3VVXeIJC0T8mBOxJP16ldnArO0+2XEk9TSCQVH86fZSJrnfL0XLc68R0kz+\nd56VngUWfl6Z0+e3VJeZoGm8rfS6+ov3yWgMwoaCE/qnNRp4shEIx3eM6URt/q4rTzF2Qhi4fpTw\n42gcxhACCqRIbF3S4OmeAUJJDRW1tUYTA6340TfY3KmPdU4XeX4RBqgvm9giZ9JEAQ6Bs0rVCHpy\nsJw7BRsCcVg54QxaHeMsRdLtmz7rSHRLTFtYkeNDmflwGtZ/XPiTP4+equi2+xRjsOyDR2NRfE5z\n4IoGu9ftJHb2eU7N4Qk/hplK61VAZdCYigQ04GgQIed+uFB2l57CSkFZzBnvbpFFZhtak6Wy2yy7\nDltAPhNdrxOs8AywkzVFnoN6kK9Gwy42yDxbLsTOGR1dHYH/n4Kk+8jr/ib2U9ht9ozi2t2QV7MX\nwthuJgTRxSb959MkE3ti3zYd4zRDgjVuxRG/kjyqYK+xzY/RsK24HW7Bzlu/2c5aR7HFyoKzRF5v\nu5cLsRe2nEvUopps9UDiO6vybMIlWvfrmmjXc15I7CWUzPr7dA6ceAtg1XR4IWDdo/dAMxQ8B7C4\nbTml8m40P/WnpAzB5/tup8ZnZxByM+g5T3oAD4hJIkLaEZBPNHRz8AjT2QXfsapfS2De2EfRMr63\nVQFDIljxKUGdwz7Ko0KUWXspqvTYLYDDYb23njMyxRwQeOIXUIP1CHagj5t0OvcCyuihPXvvuyJ9\nvC6iO441E3RBmjnkPPZllVZyrkrjBKENRqyVsNdDIKWHzfp3H93w7wgBykG152OF1ID2OCKy41I9\n/P9Z7X131Z4uBCZ3/Y1eO9pDdHIJEVVZdFviBEUMkc89cMX04MvQKDXI7zU7xIdWLyywvVxEBLUR\nUOkOHhBOiA1+C7giXsWrcK2vUJOTJe097N7axQClzRdY1SM8DBA2MN8eOfTZiQBJTQBFD/i0eOiV\nO+PgsdEnzGE6tfS/nWA/+IsMMrPbHH8KVlHe82Mn5WEZ08VTOjCnqmPdPpbbw/agzWZS2Jxn37Iy\neh4ovdNnxKX1H5jOemP0yr69uM3gZk3wcbutn4thzUUg/wzC4rtksLwg2MOuYmMQkvwMh/ZyfFnN\n8yi8zkXA9dsmHg6Pa3/1/AnwfyY+6w2Jrwu7Ha9PdzcajruwJJ//ak+H+08zmPJqvTEW5edEwJe9\nZ/AyfWqV1VDl8h6yVacBg62cQbNb+YI5fLwZ/HzEb3zWsxsB+jsBhsNmGOC8GScF2yAzYcy2jdUb\nyNdZ0uygrzlWhocRB3rr+KpdnB7nr8SgM4S3N0JwmrBYXzJgyVR7phZMQHMCB+wopPzNKXmp5uWO\n4v/uFZVG3nbpwElh3+hjEmNMTcTAa0fxU9Vr2wx73FdLiTuumhcNmcRv+HUdEAq9s+7MvsKmNoHk\ne2xU3JhR+KjGkP9b+56L+Ql3BqNT12W0mNwiRNwOtO3bnvaqyMixDUTw5ptWpHyYahgyDHAoO8mv\n5wDbLvjkyiiSpz4ISk96l7kbANVXSfEdHosJaSlTJg5iwHbrbWEv7CgM/uYkKqdbW61ITkJlVJxz\n53psCt6/bq/9pjOg+Fmc66jakrvRCxS0ux9XR5WHotKcEoAbX6yu2rehNNVjOSUEEFdiRpLpO7+1\ndtMGivTIfrZHOxCqTZN7f+iBvln80H0U/LPW5anClyxWJIsz2+8+/56KoyN/c3kC2UmOLfhlSB3u\nD2RItY7KJt/yK2rhILgcaUFn9mAneL+LE3xMEQWF4it2fm4kUGg6rrd0Ew1JM8fTMv3d+6IS1KwT\nMQZnKEIZsweeSCJekMIWoSaDzDGXZzx8S4srp/P75SH98mmxww4+pnI6okBIL1JaYwAsxDF/PxST\n8XVyQ/x8YFWQhFSqkK92Hg/UkD5Yl2KUkkPzJKw/QCmiBuE2w1FQ+nQyXSoD/cNQwMFGl7Q8E41n\n8SFB8L5FX3/TSqyCoOcvIaUA3ZRDHFiBOb2fuI45xxMrMNfQ5LMfZPXPQwN5C2lKWlcBa5FvZHBz\nVBpM+gOk10kZK9ulzGz+WDs3JG2UohLW1gK4uZPspBEPMMIvP3E6jaPVvrJCv8ql+pPX0p35WKRN\nsdgNELkbeza/UuithHMnx/mGXRwgcuRvLm2zZ53FiGlsxF0RsEFHhm2BSeTGUao+nmsR5ME0SJol\nhHLXeMgf8QbZ2RgdfdZZyrFEzZnS3abF9iui3tP8qnyf69lCwbKJPnlkbJsWnEStHdQIOWfThoFA\nra2xrXUcWns03zqQ4IbillAhLb5sHnh45d3J2zSGVdkFeA0cqs+YkDIT8VE1hL0vii6gCeVKeITM\nHPgAPFuhULDP63hdprko/njNUSUjSp/fESHVacWcBhtvyofHXB/Vk0uOOaDXhZWxeH9ZM+EHpzvV\ngHyW/cNsfEEOFW5WZpM5KMnDvD+hvI4LuXjemCLFEKmnHMO7h3pqC+G4hpZQ7mUbQDJ4uUpebOcn\nwu30QbKkpW1rZM0UCzw6n+OAceIP6rl8Do3A4GLlVB5XHWyAywjT4g0CHf7mtnsKkGoPpA/+pUOp\nF6i3JTnuGHfvhpjMV7CzOv1HAWBoooyVx33sthEzRfKpSjbRO3p/E7Xv+zKNzzu4QgTru4gqfP+S\nlpa0kwdT9YDCLjbc9l3vF1G5uZPSeEJB/FzSAecpbsIsLZyeiVQasf3MHf/v2NncNcelr2TUabKy\njM4IoDmAoHZLqaS/DSKH/cMGhySAF5QXoDOjD6BBEpnBuIHsRz5D0cDNA8kseDGrH2ledUhAdKqt\nIu1sOHjyCgpj5iddkpbPWgd2h3VyCRARy6Y90mKTY8jzuAp+uj7RXciPnNVei71oN1rK7Bh3oCoL\nOsCicA11krbUiC42tliG0BnlwuwdmFbIdBlw3ctN3D4fDwivxOhOfCTCwuX0Htn5jCAlD3v5yGj1\n0xPOD8keGetPmFUAPmxIf4b8D115oZlSvcOPAjzn01vnb9GeDNK9L88kDKi6PRSdIxaLegDoZ895\nA7TmaSzIzMGRq8hQYxk1lDQtX6fosJIcR+NbHbdAkIKsQBwMd0YjvWTNFVcOdjpeNTgvjukaBdF4\nYUmYVNpamDI5oJKJhiOilck2YvVY8bihBoBe23f0xZ47SPa6zKsCG7VhGXrzs+KRxYQVc3Lysfq3\nST8ZiL/f7rHaySCf3Peew6wDEVD5xQx/5sXNF2pZ23v4U77melxj1L359/rJ4HDd+Ofe1p48kgbf\n3uyCAN3S1XgJ5MI5VKGa+3cJk5OwbgSUO6SGISo4KsfAivueoqMqOOG/j7Qqa8HnYvWPUmttU3C1\nE8ZGLOsRgVJY/dhHQFqfMUjZTreuQP1UsnIE2bq9H+25wwX9N8p8LQZvoCpQoKyPMTKE/zeW2YHE\nml3URHxkOTV4u7CZaTFWR50UvaLqBGiesNiLFhHtBv6n7I7bb7RSHhiVcP0ByNFwDVoSXWhw37+5\ngGc47NggblYoDDsqcX0PBQGNKrAadQJigU/QB4k5PfWiu2mumFL9s/GLDQY+vHlTyK8hHXt7CCG8\nmot/JpHOBGcoFsZzmzgg+tCvoP8iG28TDL7U41XhAYvm4WvLQFoD2y0L48v6JpWR2TFVuaEqqmV6\nYI4yvFhO84ap7Q5IxiuL1dkZs0w+Pa3cwwYMLaAzo3UA+InqOIfydUXMn/krnfRF/y90p1e6KLaU\nEvx/R8w+r2PPtwI/4HaKnZNpApMMWqP5EzrgzV8SKyFg00AIo/xkxgYpmTn0xo/3h56aP0gextPx\nl81YPN5ScimdkFxx9QhAnhrsYN+lFUh5I1A8fsm+YEapaSq5/L9nyvSjG29m5nrJU4WfJJXH6EsI\nqd7N7U+hSQdoeyPcyc+p26DGZAEooMIeg3iag5LzStZYvOiOS32ufnx4L1YUfrRrywO1sFfuHosL\nat4/muTKfWE7jY1xDZDZ6lJfBYhPoO4gwwB+dFInR3aB80ovZmybN8yscojapEOrrgCDKVWBfAaP\nzCayq6e8hHn+HUWlxi2GcdAvQ6afetCIsd0j6P6OclnR9ic/OFgGmmWUn3ef4Nn6aVDxi6ct/RNb\nJzV+KJ97aZ4nICHJ3NfcwQHbwOA1bVAJbAtev8H3mfRKjUwKH3AjAdiyHoHCG2iO9t8iLX3tWWsG\nVKEPiugguniFrlfjwmzjJThda7IM0L6pKaofEKZabHigqU4ziKV30/lMBnai65hLpsyE501Zkq5W\nxCuLQk+ZVOp1YqDWuPTRZe7Gr8qS8fx/dZqnDplPr6rNCLqUh3wJ2pR7emKyFmcYrqSiXjeRLXCx\n1PgDtHzd/3ncM2wFs0dlMDUiobmsfB/eX7C73O+U1ecXWPltxTKD0M+w8OKYwvsu2Ob7xNo6Rnjv\nSNf8naXNNL3jzPLnS8OEkrMCWwwri7vBBfZJCStQoqRRMt2S+PEOdJp+JAq9isj3UvPjGqIUwJP2\noQhniF1LUhC9JiWeoveA2ExDkWe3LP0smbH7Y0g1H23KPSoT9uUNX9icoVYwapjws0v30ieLZ9KY\nh8BydOhgWDPzDw0UxLhQlRHena2hN5mRY2fsaPLoeVUJqI2hcHGTdEhySjRaxVefYhFQJQ/0TKDQ\n7OsoOFyADeFdE5y4ILzOxXLh6V7xGJRvnvoWdid1uCTarDQpVhXLuMca4LXL2VKloYKcAGSkFIsb\n+xjmnQUDrD9y85z0oCN90n9tGcM3ps8GRjVsWGoAixUNseV6tkp9v7+2NVJujBFXbvTmLcCDuWOK\n1UM6odSIC1ZjkmSy5MB/A87Xg00h3PhfT6s95lZCc/1ZR3ohK4pyTwv+2urj2Mj7+DKGZGLBqQVf\nZShzn7g4ywLHJp8J6mgc3k5nWXn+9Agi/tFLWhpCAqzAsjVuV+6157seEHIxFTPG6X9UK0tX3cld\n1vM43wXJn2gr7DxMWPQHTDpcEFXn5BGit4BBGNa5hY8l8vMg2vUy118Ke5+47Us9O0mZBYsvguH/\n5cyP28Enh8O7YsaLWmEaSq/8shMZq1SSslwFsed4ZhTbobFeid6PPvbqswnwEuuMBW+NHbEYs5BF\nJjavY93RaTuNAtb0RBmjnKjCNmDA+Np9W19bJ8IvYKWwOfUmT9SDmMB3X7VEX/FnSAdxS1Y4gQtm\n3De845avK8se6mtr5MgysRmRCFaue7J1dH3+r58XvzfOwQBaMwHsiwVMkm+Dqd/Becw4XKz7ZXHK\nJoeg+erAR0vhKOaK08chHHr3JYxXuWYON4SHSGLtRjPkboPCyKYp24/IFodUEtFEFQD/iy2gCeqQ\nL0+x98c/AUbYejyMN6jyBIL0CkUMkGDPQCLR3E3IbT5XU9ja5BVfL97Ufz7+qc8akkQJiRvI6/aB\nuP+2hizoMFhJrWtxEdIb/4VVpQiPdiJls/sv591HL2nhq5xsinZJkO15+c6Kni/zTKkXZG+0pmTO\nnwEa67OFewmcIWaNNnFWX9YBZMxKQ6muPCS0LcaRZlRXsScmViQnKAayiFv7RJD+WvaX+cSHUvMt\ntquH/hUbnxPKOv+MK8p+bXH4XWlvk4i3Kl6V33NLZdQsT5Fq3pYjfM6myCOMQhr+YDrUmILRBeaJ\n7W9UZQ028gGe0nU3/nPylLFl7MNHWzCVvk5NThP79Ik4tLNscReFnpo5Bj/wBp40Dv1dGsUgc/tP\nTTmRfCNB88NL0XOpg03V6npzJDlTWkhS1amkp5OE4LIU9jKc6iDxTgTr10uf6KHPebQEV9YRBcs8\nIWljsGVGWGrmsQ0jdLynWSRt8MMBsOurXxdoru0gEENyvlJouOl1GUyZjhF5/qPWWZcVxVBB45t3\nIPf919j0tmQ2qYA7z/Gj09l52LhZDBAHgrFA8AxMkmkD8McWILk3aeAqH/6p2FCPV+M7ZGzvRmwB\nsepRf6hTyVpZT8Gt7oRO58JOs1XrkupTzJCpWE9erfDkd0jQF/kflFqU2XbQesttZMXWQTHMb3oy\nwpotbfL6ExLhAVBk6NIcXmmVteQpaZRDne7ZoU7kLWX4wZ16NuPZJVoTMtEaAmqkDZPyT9Yi3TF4\n0TczSi0MkWmPV/CbWk1HHFgRy5caAf7BqndikEJC2EoUs+WamRc8/TlTqJVNVjfUNluJXbwC0NV9\nJvee9lqihjrC9i9DUG2Z4Y3ubsRbZxlaewBLqxJ4M0kQpKtN2TRV+ldSmJ8iIqTO/UVtzUyTh8HP\nd1J66AUFuvm6yIgDSuTxytm8XvqLTB+CMz9cKhCHmD4IbMTgmwcdPDGE2xSmo4fy8z82d/FhLGp2\nNfQmtyyJ1JoXlsEePwGmPgCFE9Xy2GQ29WKj7OwgWbzpkK9tGwVojJo8HuO/4rd8Mk0DMKcQSgNz\nnhVmxOX9UTCRpIcF9gpdBj3rw3w5T5VvHwihVf//NocJWMiSVKgvoZHxcYZ+jqLQNY6wSKSmoeYs\nuEziErT8OS5rLWAxM8gqerxdeBm6UL0Z6nLb0z0YOr+5gFH/IcBfjAK5Iey9L9nPAxi+O8gb59P7\nfFbJ2JSZWK1FD1t6AVbHzqs3AgbxCk5yRkWkV7aGKsEQRfyOlRe4Cf2g/5w5WtOzDLl311P5U05O\nHCx3EoeHNKfzRD2+9aIAoNHEfhOU07YKTJ92sBPgu63wo/krVhgdbynmhaVc36fJKhbapTY9WUMO\nRqrVcWdB05tNIKRCn/Xas6o79WhOonhNHyG07QdOUo6C9xL0/z/sCRsZJSX7fIVJqjG5K9fq1TAD\nTHaXSTP+ZXD8BESgYqYRwIYl1MIwXdBGUZ70hNDQBR9f6GuwUEUDEbf+RVkB3jspVBJngNStyxe3\ngs8Tgtm/kgZpXau9b8riMYARqNXbOYMpAoSKXwFp1Qeg6qWDe6EZeXsm1VNOwOz//4SYj7kjJI+V\nXOQgCRQ4jnUJ8suynYiwNSCw3EKX/9oPlerkrsM4Zl+O8oTD0MO9Koa9eU/tVNjK+6bGoXmmalXS\nVZMshTLvQrFyh6vlDgBTpFuaZkEloxc4qVsId9rQDTYVbFHhE4CoMPJwDw+0RzDsrnezrR6lGuwM\nGgxUDuYzG4TD1GFktTMzMmJARod3CkFGH6Y4MnEA2pOCjtarmqwuOaB2PunXUcm9Ikpvy4j2ip1N\nh269npZuV5LdAadHiGTd7ZrdjKUlqNkKBJMcTURqcfwXG2w7zKL0Zdx+z4QHH/tsD7g2YwToYcII\nX5yHiNZzURBlO6XfKTnu7Q1+0j6HmT+OnFCxjIfIfEPep92SPkmZvuGr0I4+KI5rnCSxcOxImVH3\nZsxPSHASMtuBpmhd9bVOt8SZ/58dK82tibUpYjR79apSYL5noRNv3SPjrTEMlq7efn2kDBs00yT+\nfkeB8UZz4+4/yDfPPoDeiltspB4VS6cwJbNMrmR+GvMWxdTeGR/JvjO3gRIwiB1jpfXPSKodZKo2\nAYfyGEKsUV+PfmyqE3fehWoIo5lNsBQ15K6W9vPo7ucy2ALTMR7rzxr93ZFEAtU9BXtn/67sFRw4\ntCsUWW+qxSM+XQoW3BBSpqAc3gGUsaKIv66MMNTnTHkKn8F/mOKsmnEZ6ipv0774/J1GPtVRBKKM\nUFbTUMTzY5nLEa7R+tueoAUcVpfs9LK9PqL5CZzPKRZhJuFNm0Re4PFQBLLBWPBBgnXakbBReOE6\nFeSoioQ7aeEubiPD6VKOjurCLlvqm2TduIEOSYjRNug9+5oMNN1ArRb3ehtoe4ZCDsfh2G5+S1qz\nPviKsPCJzWG7PT4OmH35HFsybP1NLWfAvVz+3eCwEUpYCVEEYG5UyinVuFO6tZXr2KNAiwMen6tG\nTsnWyNbarF6g+KtOE4BHrbdAqMFofu3ImMqs/JG4ZEUevcU4LyfZyFn4/Zx7Od8rOBoOyPkmwIoQ\nPgBrprqk5TPaDb2xRIkJmMrwQYqX6q6G94sOq7ETlEEqXG1ForDMeL2pmaW/riirBdLSHm+vvHrv\nkyV0dqbFgbGOBzzaF470AK2sqbAjYCuk1A+nbvx4Bu9pMBjz90t3SSHVl39oZGxy42eSfIqKdUdJ\nhHgLXiI0kOj+NwWcU0npKovHG1Iob8t7+zlj1RBvdceXYASdPbl2iZnfQnF+uVmrePEcwGMxfY5j\nr5Oe7hGkyNEJJhiRWdy3TDiqTkJCxViAGEELPHXSe2YswvcQaxszFx0GwQ6NhgeEsQIlstKhTsVR\nsPvqB93CHTfdfsWCcyeSUYp8sztUQtXyE4DLICR1606qQ5e7fZyeth+inoCS28TI/E/6PQw4GN3c\nI3UCnHfpnVC61Un7oEdeO0fIJUU2kE3ZghBTSqH5RvgbrvlCD1XnknzebXo+0Czqdxbvu4qar4JS\nLr4UrTem5z8+YeTsgh4aS6kxM8Os3350MCxiPbIXvWdtUpDGPd41R23L8q9tfV3Kz718TJBBqzn+\nUPThz2lWtbFh8ew+PsySf/mJ4BKbuzzpXZXSOil49ftq2Vj4pQ6Ul8J6ZaYpM4ai5WwsXRmfEsxo\nZf3k/IXIxrOzJ+OvoCD6mRy62kQFAcfj2tt2koM+UMX+zwUKE0vpi3h2hVMezpcExDNGAPlbK2Kc\nDDN50SRXK9DpmKDjYLqy5vlxls2ZnTe9ReqeKtLyJY12if8HZRRfOnqPplwHi2EtmsZ+2mcYLzRd\nRDrIqYx+MHUFUtEvFEravmQkh05F9ggFoMlz72t4hOdCwt06UHeWXkd01jNp/VIM9ux/bNxHPP7N\nc67XheO/2kd8yC2l4WCD7IXWqa2HJOXvCxkBGZKQc/NScPGUML50r9Xg8IF6JwAlKA9mpVMW0VxT\nWQ27UW82Y6gW12i4s4P6Wn96SA7rRUelBt/QVUXWDiN/Pn4h8QaXviVh6+MVoBcVAIdaI6ox3ay1\nLGwgg17UMmEuaKw1rZb91ncUkaxGZvhHD+wAQD6pawfSuSmzrHCvnLpwt+P/bUmSanXUANvNaAey\nMYkl1nVSsJjnqarFDzEwxbJIsXg6/p5X9UN5TYEjdU0SPL4OfzpGRO5p301kJ27GAai2cS0sd6Jk\nDBXx1G+GGuGKa7UFMwehNaDW+u+eRz1rOWbSmv20/wS/dSFFXUpc9ihVRmLDYOVC8AgGXnygLc0X\nGmrB3ZeSxvy4cOK0T9giJZFEbnU76uldlumJAKQz9f37A+4k0AdlGQVQYLO9OYOZ7NDzM8ISElOx\njA/qN6iA7QwzGOHnh0KIl4DIFU9iQcW5UvXnN8Fs19Djez+FPk+MQjCGhwv/EXi07PKa4OKhptTW\n3wvNRhXjfLpi8MBT8KX5JUS8jqRodU6720uCs1JED2rFY/bneMqKGxS0W+I4/hO4C5/RwM0K2kdK\na3S2llvymEzlUqa5UTVZoEB6iRwjb4QlCfSLlRHZ74K7np+LEXYlz/cZSuXeuVLZANk/TGo+1yGz\nB1id/wG/80AuEFVIwRPRjMFwaWunsTbdZzPAYf+IEiEnpz+Mg+EwIsf9QBvEbAiinn2NCi8KvJ/l\nWzBfND4SFlygGTFjBegzbuZpWjQgYEl+pYWRD7gHrDyalyzz13Lw2bcXwLdxKZR6eCLZrmJsIrwX\nYosSPdHnEQot249x8ua1CZ+9Tt9rY2FbL7X1ge9lCn9AQxcHWya02T2p53Fxurv8kYXmcFDsoKIw\n2DPAFHQKdMFYlvuib75JRtuZZOKNw2x8sTf0Hx7CfhOpdWkHjpZSbGuyG3768FlAYaoebXd17Tye\nzFsKrU0Y+EkNmxpH0SsEpyewJTjgV2SnyEAbseGf44EvcEGILQPqtez9RVm5DeKeCwpVoG78M4Db\nSLdUmZhAroU4NHl4EgAJzwtnR3ECMk6w+dTOEQfw91zX8bFdhMRDgLjYIMbzm9bwibBRUWREd1kV\n+n1e797f62BYrW1EkkJIWTBdpyktuAuV0hgsaWjRDTU1jSQU6QrVsFtCRU6pZ8fDW/VtEiVOB9BQ\nNRq0BqTDA8sp5AA2IK3+oHt/ne+rnFh2R7SfPGsUN08ZcRK9PiA9RNE9m/tUBRbL6TCNIAYJauDa\nu2yl932Rw7/15yp4RmB2NqHMZA9rFShIEwI95bUN3Ss1LdvAku4ECaVXiGjXmcvGLf2R5OFdaYgF\n6nKBO2u6zlnD4iPWUxztzxU069UaSA2OOSB/8f5704X74tstrGT8yuSEyFkOrZbTafEXHfpYnupF\nDRrSCtVK+/9CMTWJ3cZFuSHBFnPSyzctDD3hZ/zqWJ3JR0hIQufT/DryVFMlWB3+S7IeRkIFI6YA\n/H4zcwj/4CJZVdHnkG98SXYlwFfB+NPLQqfwsNgUsSeMox8Gls17IrDkLXZI5UJUf1dskADPAZ9C\ntuJs26G9H5XHFjZvjMYm/awsX9hXyMDf8tpiSD78rBbciRtuNw3T7OioyLuJfvgMaIJA5ZPyPGE0\nolQmSCdwcLis8bBmoYEqQsIX7UR5w9GM2GKmhqJPRCNXN+Bo0eh2OENItLTqAd4TQaIYqxWC0M39\nRT8kGP5B3mg7BSbqsExulJ1tyKsGeuqklrTzyf7DS6nQyQ8ykElmPd1gHpTwpT5XyvXIVqB7lq8M\nB9TAFKxVDoTVdZwP/bFRuN/FbZFy6Ab2TYQAg3GRi3cB3PJQ1VSiVsG68BFxnkoUYyAgo7ICc5vv\n6xkBb/fP9qXb+NK4oUEVjJToxT43FHgu/qPLRuLNEVF5UI8ljC2iEiGe1DABqIiNuPBKso3K+PJ/\nEUT1mn7GgRZ7Uecrt0KMm5LCE3Qit6oyVH/a40J/tJXSFK9SMtIVI2mmuePOZuADY3cBvi4siFqj\nMih3s7ldrOs6xMyRMYWtkP0/WCQNdrDyVqNGxrMCtP95R85CFW+shAy4LRlmpgfL/CmW3PEbzNMv\n2lQnw6clwHaR8IkQVRuP2vlzrARsrZIO7VnQAd3ypBWP2FA7MZo9hOvF8d0MjKtIcvXK74urX/Fv\niQD7MfyQGE1CoxpN2+uZBU8A8C/g9JmEljrJJfeGSSoaGXG0zH173ekoBRg/iILxnU76fw3NXY8f\nIKNt1vWja7aAFow0RPWL1bwmC5bgn43mjqWZxOIlOE2NErZ49gLp3MNZzroXpD1CL1l2aE4LDj24\n9kv77Aop7S4liqW7wJIDexrmH9l8orRbS2UPZ/R3mQGNJ2iPvWReXNINgIk3bLdbO7KKjjMIyChL\npyuaXowxFaJpb+UKq4eLP8p9SF3L6F6Eq+4gBqxP9G3igtC3kj9Zxvh6WX+cJQlthClQiH0lkKpi\nfSSIpWp2Hou6sj+Jra8gz58oM4nrA78I77PiSHa/0rCY0vr6ROqxer7vChZe5HIHjEfuRXKVub3g\nSmVI7q3dXxNMIeA5ViVmC9zOWm1JyX1LIG09AlSjkGOfhR9NsDmmW8ylIfJvRbafUGFim5lN+yAo\nrU1qlHH6uuHyTt/5CwFrM5uifPPnC0qwkqY3G3TTM5sYE8CFZf/JigbIEBZ42de9SJvc1h37LPJB\nNTsmCBIsyI3Dex7Zm1nmKPAJ/ayZyQdTY6JYJILfC+L6wicLqw2oN/nhS8OvL3rFj4aKBWF5rt8I\n01aKba0mYRQvyf3C0y3RRhJlg6hzrIblCCnUdMdEgIWtWn7VQ4np7+v1w8BM2FNqNUPZMFhdbVQ1\nlH8yxAx5wiauB916IXUE6Lq39N8tWo8DSoDb1QWfFF/BToIKuPijRPjS54vXXpASsM86fyXIOmjm\nB79V6mx/NufXvRL+nE+Eu76RiPoKEBbpArqwxejRGwrSVhX+i8xOsmvfSO9DPF+ijpu7q3s+O3c+\nNIgZgD5NlQlPG+URz+MrmG5/svtWh3dTcpM76X5C0LKOls6tlShI5neeBrY5EuJff0oFPrzpnpeM\nzk8b023GdHLRqV2Ikuyz75upYvu35ue8mEeity8TAERGjlXEoTypLCEEy/VkUMr14ONgRhsZDutB\napqpdELZ4RLAhiKvs5iIK/wiOIqk7sHfJ6I7vr3pt2D8tu8VaWc0UxSGOqcKr7D7/3OVEWkvZOnv\n8fJoRmEj+oxh5jkVndsOf06FuegH2oPjxipkxbQGTT0LZUoWBC0gyXwt7i2Zz7vZQw7fGlP3vveW\nYszeVe+tu4rWcKbakK5yYjNmuccI2PiU/oJdrUvtITIR64/sgFq/t59l+QESDcYpBSU4K0QoEPe1\nd4Qm+SqUmv+R4zk0qTJsfjRPeME83FuEj0W0Vvw0XkhpoG3sU7DDETawm18tXxhm+8nPOTxVjkIX\nUJxL9yic1gMDeoeE5qaPJgLUGa0iBjEiAted/I1PDS5BydsZZxPW0Xh+jmAiBh9hxPYIGJQ7W610\nc/ZCbfCOn7uf9QiupLagphGGHnrFVLI7CkLxUOag5icgdUJzMppFOzjF1U+jQq5yIK4k3qfg6m+m\nN+cj6J5HPzW7P9w+ub3V7v1+UzrL9bOsL8+xtKHY/FYuoMWA3AL+iGJE/p69eaoqkZadJ3QPEGdk\n7mpepz1GLUyqxbMbLMtKY7gtItlCbMxL1vCqy+JURAN+lZndGwDcPE4MKxUhy1rxzdjNll0ZgzaA\nygAWY8k/IO4INEjXl6drzIJaEtw4y1yk7Y/+z90FyrlSOcXjLdrKiSWeJNMuJPhpgBk18qQaIi9z\neDSc3xrh9kYSiowceaDitdlNxMmHXr46y2qgSN30CseN5CfC6EBmjhegAAckdwEQ+tz5cCpDNP2u\niv9oMqNywyWkszXfmsxc7q1MMtxhsG/EQ44qjlbToDsDW0vZBa9HQWGGC4G8HJOi2xr4xi0agG7+\nLeKPl12o9bPLRzo4WVgm7rVyVfrUxuROXoEeDVKqZsz6BEh25SElhXUp+Atv9MpW/8Eh0uubnktI\nwIjZWZJqwxmD7xLftxsKZaFfiYE+FvDHyR0+bVCFRsBnG5Mp4eNX6wyZXR/vXoUlYKqPkvYE17P3\nmbHmtkK0Roz0Qt/87saAfDLfG+n+mKd2u+tcXgxTH9JNT/d+KuwVV/zTrsYM9dNEyRoScdjHbCiQ\n3z26vVMkpI2jbYzD1u1izcdX0YWOsOE3oyEPTTMxNPFUuzKVmHN3cIg26QewIsGH6FLcQneqAW4N\nplQNvfUYdf2B7/1wnWxcS1yjTuxYaXRE25TUNE0eUgJvC8uXx1RvuWXEbho0RUKaGatCvQdprTaH\ngMixytrT+UjDgp3L/Iqc7u4UZx3rnRCfWBZ7WJNWyDWQLc+BBfdD84X+yjneGF2zS6N0tETGyYQ4\nvDvkIq0j6jffWAQ2uCez0Y6WnWmOSAFw8BvBPwi25+ALBQVs+edH+/K/C85HQV4cPQSV1XI9T5ex\nEJ+6w9LPE0XnlHI10LctSlVNgiYI5ezq0Z3+4L+/b/CUrhLwcle+oZjw9G34vgzqmKGpVO5FwGqa\nlRx/q5AMt8ib7ZBXlJgLC/F9BiTLdtzAWAGE9PoEbGBHfihjy6p4oGwxReHYpEaQySlV2l6L06Ke\nSlLNrhmv9Eo6OmlBdhDA3i4I/8hT8brEHw7VFdKYvAeJZZGWbFkw6uNA1zPrJbgGquqBLuO1GjGr\nknpu7mzBWIN2T6f3VtOUWyJvgzkf7QSYjCp6dPum7Z6+/gxKaeUeZSbYjzcd6uCAKP43z61gJdBW\nCDRKHPmueR5lS8Q3sWqvlERFFM9ln86u/kH5qeyVzCk39o8guT/pk9MJui9ogHJ0DxcPnZIRql0E\nMad6RKnBhdnFSiXcKvCojmE3v5qRGNdY8qe60zHF4p3haQyrpJJwBBRjRCeolgEqRV0UWaLhmV8w\nBFy5WXwpqK3BmD8mK8MV8YfwrYk4N7P8QQDLgScEuHpebvvbF2PKqbC+KJAv3Z1B/UUaWHLmGFXO\naX/VJ3QKOlRml0xS83SiLGuv31dr6/jer3LUrZ4EisQq12zDUwmUltOerRdbl0evDE8Jwj+abn0R\nFV0qCn5pUwm83ukG4m3vQVv1OmzEU4JIqTz2/tpSp2i9/WVkVm+XnuMOb5dqWWdZcMeOJW9YraJy\n6WCgoP62DLKPpNQ+JHZxz/mjANdGGDlbwl8gwFzxDfanbmoLBE+hRh6etHkWoQM4r/hL5xqrXuyR\n0snXDgVPIx82emND+hzPw0LcA/nKOmuRIB1efqDtTHBOU85MttWbzcTtV4Cd9S6cNRUVX/CQzjt0\naU/prM5pwmlZRusjJlQIbJPz6J39yHvR9oQWmu7PUg8ht4b9bao6QLIWW53Se0aR9lnqeHE1MLf2\nixeJf+Uhzwdpt7K0FQWQPA9wbQRvb+pfDrsz9NyaoiQH41RJJ2PoNIeElyFQlfmTFLVv0lgRYJH/\neZpMxXafNm7OiRLuy3HuTVVeQk3lApBXKu0a3xcGLABxaYVuqZN0PzfUoWVUCf8bf2Qx6MpSaIN9\niIbEpq7CkFPY6oSZ0mOlY2QckwlcmO48UZdHa+75V2l0PhfcgrUyHBg8xayAoN78ltjdYLPyKfkk\np1ivdNu+Bd6qTD19PM7qY4d/w5nYFbn0oFkeNxittd1K1tpAcOfnzK4asHG/0sm1GP/ei5JcI0Ut\nH/PvduaDHG4cZ3MEUGxcl6/2fbBiy32mns4mfYgzpHHQIV0+JXBaJttTNorzlG09lILEXL6TLU4/\njdaYkrfKHP4QQKPgk/mMhCOPAPZV5uVGG+LGRn9V2Lk/aT3h9SQJvQyWk6ScqUu7MwiHeB6hVf0N\niUabBJBc0QvVokLNJVoncMD3tP/jUscFt3T2/3O1BeVLHKdq9luQFfAZOOR1OCfX+0tbR8VB7g1r\nQ/b3/Y4HxOw7n2L4kNFkw0ODgR2N9AJbkDQrNKlz34MiOXWjQbucZtnkTwaxRr8cYlsi2ryyfmd8\niZjRdCHHaprTSBfY7IXG2kaCMz9XwFPdd6rFjRHdvn3aa3YY94kSseE5R0yTGYv8qSOscHYKKZvg\nVwez4yiFwUuEMLqSAVRyOuZ3L+kCZ+q0z9oH8bGR6hyO5pD+TLxiA465wcB0MXLZXawRdu2fHymz\nkXDnf0sZdFc+FuFuj1YStDz8IbpFQNNKuAMK3zLMVwyhvUqLkwOsUE1tIf76wqxWlF+FU2cWTEtk\nDmwbS+s5BqxX8kwstGhkcUNFDjuOKF9xxEUFzbUrZIcVdqNeKFSUgw1e5yYIUpMkgRJ6qEKjShm0\nLvBTb99pS6Yl7ClKGBPUujxmhdPxnvBWH7mftLDsJaRQDjCDdXHpdIcw+k7ctrjXl23N+hUkMgHp\nlzHoLWvVdAjchd06TVE540DEMXWSBoGM9vJjUbBt1U0yd5iHa0cjY2rj4PwPV6zj8Hd4mmFmvrEJ\n1KzynKxSk4qBDKOWavMJ5ErN3Fx0crY4HO1KrW33m9LohPD3XNmOg9efFiNIdRmxH1yP5D0OXJg9\nlUSaEaPU5y8Tu66lLs/thRvmuhJVd/GRmQlIsXQ+W8iuUiDma6hkAMFPZvznaORsV6wplvAz2pyP\nCccS2irQ3DcDMtUQ4ZkesW9kXIopH7M1zT/CEl6dJZ8TPgJ+CFMeepBBosoj1fMYihhw8O5azlh4\nMfKjFnfQm06s/3tw38JevWzI/wclg8hhqFyfwfHm6AXLrKrX3KhurjXh3iFKuuV67TD9NfwTe/xp\nUnc/pwuimmGLO/N7q8D9j3pV2qeGsGUWuhfHdw0Xy3GkEmI4210pr1iJVgAnm1wgQk0YDxkrCRGe\nzbbGutvCCaLLRQrmRU3WdZ6Qg3+mlJgWbszpsRucTj6Vs2DgorA3qBePZrAoinMd6mEuOEkUMS8M\no34KdIZVKUJH7BWBtJ9Ev5YZ5KVrqGrvsBR0bsL2ZH0T/GVBdP4JyZIqDTysCos1k5++u1xJHs4V\n/YDLFA8IHh6pW9rwxg1nBkvAl3ophXlZTZC6YFFOVL4fOEV7YDWOE2fa8J6Gy9HC7uYMJunNTy/r\nxGh6mPhrdCwXNmgDLvkvEG+5+nUyKB4yq9114H5yUJJW64Hrp4b+y7KxUjTWP9Bie5JhKJlym7SB\nW++ZWCfbLqDir50i0LkfmNaPRtPB/A+k3STKuZsnHGH3T9fKx7F+jUsQrPIj+EpABU9HmP6XKa0t\neqyXzJeD98fKj5UmQoO8aWb7mq5V67SU3TRjxb/QnYtQW4ng9HUd92gWEMtYytRCLUCGopz8nuUW\ntBPDJqAIHtE4QlGpOch89E08iCsaNiRNmtMCjO+ayf9I+i3+XCcL7YIuq1xEkogCcofO1kKI5Xj8\nbwZ+212jeNpjVKJ63/KMxzwMDC0JTxfJ0pAJaJbl37a7KOZkUW4O4zG8sN8VEWlhf4vPCglbPzMY\nM9uRdM8b+EiFMPjYzmWgooA+m/v20Ma3TDVxJwuYNcrP+zTqlrRaBSWuzAAr1qSnvu1qkalz/uP6\nKmwKC5yHbXLFvCVn4d64uBKnfiqe+V0GbNpCVs9LBtOA+qBfPJsYpjG3viPatAZ+kT1VG83eD0t+\nDgo7EZddmZtr9+oG3fcHe2JcwYt8zhr11BQfZr8Gg50iZ3GMzDQzO3H5JAe7LdOOADeSs7aeQ/21\nH4K8rA4SHOZGLQsf/iZs/DoRcOP4lrRnvb9x4tZT6t5JHDwCh4hincNrXMYFoph46jfftHQzyVfr\ncuneaxNYg1ICGbdM+SzAarI0j/EX0jmmxWnnBqx7mtpeMu1J1XdSDHO13UTMeAl0plcKb860Q3Wj\nzX0GOQ5r8zINwBecxZDUMjpyim561PNzKAVxfVSuhpjAmw29PGgkqxFpKkYFABA3FIygkikCVOea\nLGI6+Za4MoHM22iqX+Fmqnt02J/TrkZhCyAOGPgfhfgJPwg0PnNhM4r1I5LmUU8Pou9R+GIxKs/y\ntc3qPxRJGgEKOQn/6lghe8EX75FvEGKUBJ4tZil61VFhm10iIqjqkxbiA3FKUmW6/ivJ0zsYXP/a\nouGJz6SdjzWOWAYartMLhHMIz9qIAW0PllP3Xe5mhrU5dZXDRluLhzCDriuesGUbnZ2VNE0Y2NoM\nRVjIGcUF2TeEi6+o6DS1rKTmvkB6sN7AAHwBZYVT1rAGJeZzbsV3H1JeSLDtzEwk9cVb/IJ1VZaf\nCGWuXziYJWc+0wzImlkpnN1Cvjfxf13skw6GKcYhNUkPXqJbmcQv92B9O0h414nT/7yTV8VIuBb1\nO1UPRPQBbyAjnvu/7zhjTvRGOp3Xpgqt8x8RoiDwMC3Ud2sUIwAW0zp0uL/kYuwm0DaaZdXmoVnc\nMIbSKK9Wk+6Rgp38NynIhTGObCAmntJjGGSlbOrgfD32ynH9Lih7/GwIjhH7SGXI3MEzS1JnMbbE\nBqxYucKT0IyArMIf2n0NuKNFYwpuRCkDymeYJGVTDZ1ZxyakI0ER0C5cSsNBGT0IQNX5o7MgPURG\n4y8+nOEMbUClmXkhF/b8M2DqwTczTqRM0hJqtvZa761YC26hvYuk7On1pJxVwsSe4YLegn4UsE4k\nEMh4ySf5KuqY/XM1CJH6BJxvaSiwdGWOoF/EsHfRp+3cKtV7A2bLJsr7ujrEEtZ+Rh7yRK3ljp2i\nrU0UMriqHKZtYJsw3Ll2z48A8fnuKkkqPmiaG7rbEvXzS2mMo+aXGBhm61q0OiTadnNGuvUi5X4G\n/t9f3Aq0ykA65VEB4Mu7J5/vjCofUZyIQfzukVtr/FU1w4eiTYBoRPsPmlAk1CO6Dt77s/yHHigd\n+4B2Jg75T5MtdwdKckikeqj5Befl5zsqo6a7B7VpEbeb2bTV7hGKXe0BRU40iBQ5PaQF7ebp+tJN\n+nKlxrnfXmrGLMZWObdeOIDwmDuKwxndirYX8JrLVCg3YVRe55Bzyd52w+MjY3c43nF5orIWtj5d\nEV+R/7LcrYc4+YxiACE14HUzJtZoameKgUjswOnWi+XdxQlXRVvZ6v6YG3dm6LzWclGw5x8HxPix\n3Rp28i7Lu2XJfCbbf7XEbIDKrHsE3kLRQ+MCGvJ4AVkNGHxsfImuIBF0UX+E/d14ox+gBNrxJUXd\nk2FtyYut3mIT6NkjyLuugGaZoqO45NvktT1bNDLFDt1NHHGfAsgcWfuF8G9G0p6OAej3yvCacTLP\nD2/s2NLg5BCun8jdGP6TY8skVfz1DqKzsAqFXRaPgYKneuNFoHFCCjR4vSSONM/+uIqsJCtEo9BW\nU31HOfA/HDTwYLToXcHsAgbiR4zpz9zAUpq844q9SN/alJ+chDlXUpwdCKJGbTwsO1Yw1o6nIbdP\nKL6rPtYEw82aRK+iY5uDJRBtHx5BGhW5TU3EMsO5LIe8fzblxry2NYJmbTmci40SbFqSoRwaLoMq\nTp0N8bKkz7eLMulX/f8LRNmSoASlc0pLWgBzXV8GJCu7jyuQyEbJ477k5d7zKq3gqsxcM8BuA5NK\nQU2/dV9FfHaZYU10J7n93ly48wMw20JamD1CxUxsCoR6wJvfHB3eTe7v7/4jJuTu1wC40RcYxX8T\n8aYE5jin2sA5uATMPPVKNbjEG1QknUlmFTLMv3VvQNfaCbYPsvc2Y90rpMGEhHZb3lo5zQz3A6rR\nGHIeA5lrU6IXjzQJpAPuVQ6lRV+Hvb4Hh6c9qylildIhAqSdRgh2aksPicznNwBBzzsHHRO5upCD\nIGp7eVMgkkjb1XTkkcKqkb0ygAIcrFXrhSmjXsC1KC0zr1QjjK9Ms19Tjhqp4OATx9faH2Lee7m6\nX9Liot8WcNnnHlf8FWPqLU+4YuYJUP6kk49wo6pS1WoJ9K8ZPyvVXqUpFDn0Bd/xXDVXnftpeZRP\nHsiGwGXomE12/XBadfRq/seo+9MuycGurG3FPCG1gyWvF+2nAKdrG/VjFmSiIO4+QBnmNGQrtpS+\n2rYP5BaDjx49iL8RfKatXx68b/O5ySNSSWh2JHLVi6/M8GloXl9hlf+HiPCFXIJOr4dfJU3dbKA9\ntlf77ifY1H//Oq3s0+jZ8Ho+gGWPRqFYJqpRek6ImdcNhv83ZvnVJjOC6PJifGIpZjLaYLPsZzLT\nK5AnjibhsBR7qfXGLF4Fq7YpO4mqJfRzZBD9iMa6LZ1pYWlAHq5B8AwWl1Xps7SjAN1tHqN6ncjv\nKHEmLjBoa4ipcGPlotcWAWNsuCCRCYl2oA7XAsxHKPkPCZRqC/Sa2vUl07QfKeH/LiNIEH7yDNKM\ncWa3N+8XwJotwcY+R1K6OEJ1dnIm/MjVy2Xaqt0UI6rfvfYd0zk9G+dg37jDfnOeNnye3WkTMORk\nZsoGFp7lgo4nL8mw7AK5bFW27TYwRcWDdhoXUuL6IMiO2C2npe8vnbvrM3s1CayTrl5rtdFFhXA7\n1KOlSMrh1PfD48Jj4R5lNCq7aVkdKJ6Xb9VAqLWvllKIsWcR7WGbTv6JSQTi1mrp1JDc/R339SB3\nGVJX2CX9ZS2L5zRK2DHMNFxn7dftEb7ozD8XwURwlWmYrA4eqJR5wbh30jd/GC/5i+W0s5z0ll3N\nftJ9Ahb+kBXtT23zTkTzDM28ur+PAHHumldySi4hnSEKOdy1Lk6KbKKRqVK4qOyn/kvO4DLl9rlg\n2GAmRAOwOAgIDK7Ve6BhT00ZJEIYQAu4XOY2qDJIf5lIYo5th4ZGrOwJkcEFWTcxyDcu/M983bkv\nmGEcrswNjTW+yJ1H8wHYznfMN1r+jAauwjZF9lRVgvVbCkt4vcsYuT1670PltEsZUN7VSG8HKmN9\n6fKCmoCzH45bNAknmw4Vtcr9N8a/9+Kuq3Wn7BmoCxxSV2qKM6QC4sl6K/jYaXIg40aMIWx+5bKV\nEe60fjYnQSlEdhxtRSsdOasG5TuEUaE1INqGqyYSge2Oe+iMlWpzWY9i9qsNfMnmgy1Z7N4RUZnv\nn0XadssMr8rl4qSEuk+To3bquBktA1CqgLw3sDC+UHDkHF+7Dv0CXJoG+9tyZSSqBPYFC86x1g6t\nxVi4MMRZFgOuE3vi+A4LOqbFWLS+Vghecg61gyTcV38qoTL/AbH2ADNWvw9zBwuNDxuPJP/jCeHH\nAvYFZzEa9lQe3Aq2gygbgsSvLkuhYjcWrKVepniQHR6RE0Qc+HmMfRbuSOOjlMeG43T/28YFr5ht\nXsDRt2c7QkaEd6qPaXGzkbpAlH26eZryE0HKpFb4OhKOq54KW/k19PKHCWwcZqSc3om7aG89S8VC\nqlxoyQrxf0G1EoM8JfOGWF1hLRNt6wlcc+OZXedWkw2j7FdL9YkwhAgklXxNSic329b9FqyaLywT\nXykfBf/iV7VcqLZrLY1TxIEqS9gz0YIDmsGZR2wI5eQZw+gC591mgUlsU4Q33xUmpEwRbovtPBvw\ngM/7jkdby3mOvCGfIOKF6BklA9SztAn3das51JOP4BZtxb2Kc2Uq5d215YudSgtCkJjHDz/3+2EA\neHudRspc0Muvx3Kn8858qxksCTQjhlg//Uio0BulHQN6axImGCv3vKjWbJJQ/IYPnNfqvtAIJxXT\nNerLButbfECfOPEnXYEr1sFiXIMDr6qes/+49600hdmTJjIAknJo6NRnsEpmq0llBYQgbrhmwQF1\nn3otUUQSAjqcv3B5nnTkBIh9r7cot2ubb4LMu5KiUCs586Uamol4AgQzpvRiCuzf49UmyBpTYYGD\nDo8E3rnDQBb0SGPGR+RV+p2bmdjkHCwpB2Qogot8+FKJOko/GNURCsOnErZR0cDnL6G0Vcu/AZ4H\nYlN7Vhf8n7S6z9UpR3itZsPP00lh+ix+ztZSrXMnC6H8HRRIk6qgCPZb1uswmQWTC4+gy64uDCAT\nP01DnMc6pjoCq1VklDVmzYkpGYizirqXNkHQTvlMOPcP77XbzcQjYIUYPsCsNJ/BxageK5jUJgRF\n/KaBZB1Aad2I09/YLSjJv4C+Ic7ZJ0szDgoT42uSNptENpUcic78uUankleiH+8pz5HJtc3v+GGC\n7w4Xdv1fXfr0TSmoCvJwB1I/kRG4jjbm2nYQzmcfEkZm///9U2Cwc7SxLUYtzHB8xcxxAyZvmQT5\nsjuGu/3KqkNAWhdBkBvKE72RgQH3gbvCVMAZP/IjzxXPWjNe719EHjpBKQI0svEzPTuTLTJl0D5e\nA/qJFluvbTq5GbvAEp/lAq5AFg7EzOr1bpo9p12hhudIhYIs2gCSfqriW0HQoFA1ntFznqJ7XB5l\nziSMapPRWIJJbK6HPl1rYn+6yGPwlTBjQqMrvKVao+PKkTUyrQT2VeTmZpIiHcI0FoQ+Ry5EFkEp\napfMmvs0e5mgFNa+IdQjYtCkcV1MiUsJiB3fKzsI3F3iqaNiq9TYeAjZkW0y5Hq68HA8CJaGVt6/\n/4bGytTp0pBIsqPpXfjV17Af/GPBU4rp1IYIVJlYc47NVAqyv0MeRv2dO45N3pZU89y8b9PnEK/N\nXcHOMnMUp37ucLlkaAhjs7Bi4NmGamnP6alKR2gtcNd9HQIGe+b5/oD2IIEdfBoEwAvg47EIY0+U\n9TmsCtVW1WUxVTMKKL8PorcVHsf52pASYhaM1vWeLIEC1cbIldvn41Yj6v9vkVTOYJjywf69zyng\nrMKHX2ftiZOFmiyX0Cfg8NypnhF7rbIquNfyJWRh6Jq7r4EA4SjLJWHmmS2V7GQ9E2EryuD69bDR\nPUizO82EpjaXzr1yC3zUPOqADmHNFHfymb+WeqpJ2aDmQruv1+pxkUrpMaKpdtebJzted19DLDaZ\n/uKz22h5AV9UbJvzresToYlC7Va2OwFXTGKv0m8+f9TNWYQPsZQMiRSJsOgQgrIjBIK4k7HqqefV\nvwHVmaGUWGs9mun4uC4GPD7v7P5V/BZTTB4NxelNSevIQdJ0R+TSZxuxpQiv2W1aifTRpgOfUEj9\nIYbtb+J+I1uaxNKtICrZ0NlsbEDKIIHNLdgF3F5rbyin+jVDBlPOacfj6TzcrJT43z8Hw9vydhw6\nnqJA/hyky+SkaqL8qnQlJobXtTbwWG+XJfdfr3AYajmf8N2yp5m1mL28gAEDX18v+IzbAaJEYnNA\n2BE5UJbP0uLJfsFRyxVC0e/CvLYKjcFUpCISY+r1gItfeDgr+6HIS9Lg0POVqcznatEzT1I7V5aw\ncoosPsTm3Ms6ymoS6vg7b+APtaS4mrZNL63vqhmIAGdE4FNsWbeopC4P5oZCm6zGJ/kOkSYcQ8Lt\nLOa2W2f+uY9ad4LPVdluvxCKTKxtSJJCimi66u+IkYrYopI12ALAiKylCY0+YNum/d8X0QKv7pG5\nI+OLzvvIpeGb/xOEvRkcj11SoMnH9WzDiowt6T1pIb3jHTj4FehxQq2CJWzXAraFWJNpjA+fFtVi\nEyme3OheIwiNl1W/YTlfmoWBKsi/Y6GVxbLuh70PpptBMfLy0RM8Qso9MEozKLq2505huFUhQQ0r\nnXW2vgwRy/04xS5K1xFQj/e51rjLmmD2rDDvuMafW2kikulyohUI9ysJpN8MEE5zP1DpO+oEovor\n4nLLYLVYRus9q5wLi6jh02cs3rQmKu9p0bC4g5qxPJBh87oWF4q4O9Dr5cc81w5vfBTj9K9Mc4bx\ns9uT7J1m1dU/csB6ayCClP+nbJ3bsD43bCzGmRlb2FMl/H6vjp53n7FzEVIrRCgI/BTPWtqK9nkN\nMNYvtzZRaGQIvTTjPVpNGjehPm/FErXoxhlPhCt8mca1uqsT++uCYhC1r+9nezfNwODHfYwbkBUR\nMxN6xrkuNxl6CjzKIowgPy3mE4Lhfhay6skORXqISkOb0v1JKuuKOgOPX7TAbc2gbNU8p26KSeXR\nIBf7+HomNn6PnJrky0Wh3AjBRdb3/reMIj7M8s5OFJ87DaWmHfq+RIVbDZmePPpMICacji5vxsU3\nrHhdq0pmb3k3aJL3HhojY8/4Z/C85x0y7ZDFVTWXzcIQJvHMsvNrLjpDNE7TbfkwpWk75kAqiG3f\norI3hlBTyGc1ANF0KFpaV6jj8xRmNybJVIZ9TwtY3y30m7EIVPLC+0tJlqxrEOPrqlAEWAljOfYk\nvWRuDRPDKx7f1GQ2y5DKRB5zyU1dv12tKvNLv68wXJVjA0CeTVyx6k8W8XMptHEts5DntrB9U00m\n+5oKxVwGjah4R2eiWvZlZdv7XQzUqxhZW0CTdEZbBIlDXEjw2kZHRleR4hjfXFG3hcdLqB73GKZ3\nRHpLI0sgzR085BpNjWNI4WVBOk4zIY2693Es9OG8mjLHnUyY15VYgBSuBDr8us0RA0nDspTh4mOd\nRHmtxTt4r9BNaOapAeOhEl0uSOaujBxR7urtl3eSsiVx7ZpHjF7z98yftonYINCFbmt5MRFfGL6N\nfTpWWSmnK7hpMperBAguhPlDsuuDX0zCQCWKl8WjeJtHw8JDf5C5UVHxy5V5OluyiirnyiAbIbQ0\nidcDR0+C8k6uj/1DsVlfIDgcrRcmHRv3heEcZ1VMD3KL4xxOjPChNBPFGDRD1H+5w9aqkxv14i15\naZdx/q0O9pb3/rH1F6RdGSb2/MMCL5gKLIP6+UnFZdv9XvV7qu+Zx+iPWUhjbLOm+bxWFB+Al5ly\nxz8sln5Ucz0+IGwALDsf5S9wDLFRNwjgLn0CTUU+6BSGoNIIzBgjUQqCu4mlhQpEX06tLiz8MEzd\npixKVbfv9H7Hcw77Tk4E/6cWNQMWsLagTAUrI9/SxR1O43xQ3DyLZszrTh1/RHfqrgGweO/rzrfC\naas6+queFE0MfOZ5Ilhi34tGHqvx3wW8LgVh+m+LP3IOurZKFyijJWbEs+3w3DCsdTyPdijVFVQI\nZ2XNjC+LC5QJURxy5Cg1yYJzfjbNO5/xij4NWlGPzuqLelLT7vnzsCbB1fdjq4kE84Iqwg0HHLj/\nASOs9xLfourMSxAW2EkNDMvJvTamaWBtcQsTDBzXVilczKgbT6YRvCisPO/gR/InPhqd4XLTQgg6\nOCyBFpbZiq90iRdpd/7GndHVID9UsgRY/jq6AZYh6UHYnBFUTrRJlaesyhF+NAjjVbRp74divVyy\n6MAYU2jwKz3ef/QnsuNLLprrSbJdzRtQg27mSM2Q8BvYa/EuCYYmzmMQbdYDdY4NheRKSnnnkrNn\njrwViyreIoovhpgDROwFTJeI6WDe52O7lkMspwmt9SjOKCCebGmdKRWzfXhMF8D3K744aomE1JJX\nOcHEY+BD1i8Gko1bPRBchNOmITV4b8Cn+8JmlGB/0kZlsAiQeQt7/Z7CQNRfR+45kDL97fWPxCHz\n7ARyp+Mf2QupXbussA8z32Qi2caQWTKJMnwb8qoaddOMDvX6hF1MZKAqSmVEcDPT7BqkAg+BaBEp\ng3PEs/KNIzyK8QVFyLzeSJeLEwJSLBWIioMbinDl7DBrCc1UL87ZYr7JNrjFLFqOjf99JibfRQ8t\nOfuz462d0G9pbIYewUdW1ZaNPCCPeH7+bO+jw1CEMj5Sr+eRnPiMkmeqZ/dLV7/9l+6OEMhzNVW3\nWxi5FRFBrUq7XO9aM4p1HrID1VV4tK9/+Y5792AZXDdnAWSNI3H13hyLenam+Zh/0RYIZnUPPndC\nduiGhAEhF3ZKX7hTRUPAHEVt+M3A7FzkPbbqr4ldsH2EbOJnfNLk0HqktnOOq6G62WeudYTgLFmU\nx8NAVfqhBrausQY5ZL4wlxNlejGsHCkOtDE6sr/PffbCgI4EXoAFTkVYBxMsT7+63X7h0XtdtUyA\nGm6JU0QXsoPtyTueV8Eugw3IVrMlGDhax1WMYCJwHRzi5jCRdhXjyLWXx73cW2CPbeuT3fiRHwyg\n9rLyECvptl8+8QAGa53NsSrpvKgLMTc84j1LWG8vT9GNfE/UMPXw6MPflZmyG8PcoTNNY06XHmIo\ntJ3/V+zcUuQxZMX8lRjdAMMEccVkKVW2TnBkYKJ/T69xtSNOzs4cDhyvYa5Fr8ZyY3jt6C1YmfJT\nuMFH9htoqpcdI83U+CsNowBnVdNnP2ppJDqYCeSR3d7fvWJnEeZeVefmySKIEp/vUNzbZy22Ii1L\nHGlf6RYqAUKYcXgZ4iLXfO3KbnTPVVtbzRoJ1UdkWEvrVLVMelo+crunrQfhyxCmPByHJn0KL29g\nxoxhio1PFs4oyKfVZ0wpGaNUgiV9j3EUZ/LVEap8kCjiZ9GVEvw7YEb1Ry/0IQ0y5xLZiE3QGbHu\nWLLwNc47XPiZpW/ukwdz7pHmmHef04rcR3CsJW65tHIC4nM2aLYHnaEzSWsn0/XWPhKhI3jwRgId\nZAUcb3J0Ov+w8E1NmUdfHra4Tp+GLhkNyx8ff6WWwagLRvUVReIN3Gha16k6u9jaDK6U53+aj6H2\nImHIc1nhn3LFjmUO5eBFt6hUsuVPtl0MkvP0a92YosAmAko4LuBRulwTYRpL2PE4OokOovorBX4k\n/U9Tx32xJUL8muMGqqDXFU5HRxdby7Ys6JmUj08C7UQ5bs2SR0xNXN0Z4btiLOd3RokIzZt0YGVt\nzaS0pW/HVofRDr1AnV9/RxbYK2p5lY+1ZTjn5rpr0zEErF2l4kwvdmoKnKqHkqZQ2Jms3R2MDP4W\n+AkosnHC7LhMyiaP1tIm1K2U+CYAq8oV9faa66khVRkRwDNFzp5Rz4K6PSXacecypQo3zB0xt2cX\nudkeEyUc48XoznYVIpgDs7QnTl3/wPRrFlHXxedue1W4cRP6EYmItuPMjR+pr6DT+rvuxG25sVsg\n4KGiTqKfah78JXeqUnNS2KKhuLe+5cy+kt/lINvM8MDTh4XCdXlIxzTD5CdDJxUe9sZ6LsxDwJfW\nM6JOg5q8wakJ4KqH9KpytKjFMMVmFfJOWkif8a/Bjt9NuuvIFJar5tiX/1moacdbmey7ziK1pD9q\n0/yCum5jd0OY7z6Zv8WeFcpsuf3dn/zDcr0T0xwQq5ZPpZ4Sw2twlKSHffUpgsUvlfE/yNYE3qX7\n/980zJbf96++yvfmmV/LUGuNHRSOmnA+z+x4sxxJqpwD9Qb/BrN11ijlukAFBE0QVLwGxUN2ZzoQ\nAWby7PFJ/o6iHV0Oo3StCBdsTwSZiKktDwmKBebmO7BkNJgpcov/cTvj9TBaDod6/SYVtk8qwdJ1\nJ+q6yS78onM8ryEg1YUdKU/Gy1M9S1TprLgN7PgWo4lO6IlibXpdPS2C2uM54p6IKj/dk9wkpLhA\nKH4A1QhjmXAMCnAYupnbancevU+tVYtEG7eb+u+OyeI6hIgIyHE6Og871weFu2vzSg6g2LIYKn7j\nAvvsgRTyVmo/DI5Vxi7EjzcZwQ+m3SoMxh3KMt+OfbnAKz0DBORi+R4Wl34KIxA2QKk7SjpMADpZ\neRi56OJ3ZT1Ngwifb9t5AqgtkKWiFdwzUxmMkGaHUjkFJNF5Gu1FI4oibReL1cF7O015fPUb1wE3\nvLCriiI1vpNw6Lhv6CKEywt2hmbIyvn8TGkCCfr+0COi3/QBSAnN5Y6cdSw0g4Amc7FERyAt0GyS\nRatjJp4qovPaAgi+HrnulOAvDKD3Hxp4+Ntm+LeYYFw354/w/2oIKgvELaVgxzRUSN8SSYNjuHAv\nZdRLbnZWCvn5J4FXIfJDKud9s7KS2Xo6FtR65HIEKhV+ZqoPMQBJ1wTxGudMipE8XdOw+FcCq1uJ\nTjwhQ9Tav7y/3TSTZB+dExshDW9uq5lQdAjpjks1d0bul705XsotntvM3ATSjZvWJ0pLLsoyKX1H\nawiIZQS8CGJwgW0tDnuJ6cwjujqDzJid4KlJ6lfStgaA7dwkQFG/gGpzBLzFkBgkhHhPX/WPBg6v\n6alwkYWMsgcwPC0ewH0yUFqgk8X4wm+cOKrCq7NcwPbhFrqJlI8Z5JHu6trxdA7imm5FjEAMuINF\nodfwsI9Y92gh7Kp41B02n8ttgjVJfirT4duVDo4i/7HfViBcH4FaBRljntzHQyc2indp074jxNma\npAKbFvRejUdoJG+hSEK3opglz+RqK1AwAgnb6TKpb4xANobu94j5fw4Omiz9hQOSqyhIz1joVI/C\ndSfIflkZ/na84qQA7LFdGWT+h+5vZGxjFuERD2VzFQggqO5oTvKzMl/S2njm7G00uffGbJm4MPIO\nqNmijL0a6oOZscFJYbHne+EZZge3XbGcuoGaUUJYkr0v649WdThN1X4ksdPCiqwYlGrrrOS+Sw7c\nNSxeEEIKHOYuLhlc/fGt86GTnubVPXsNMyN6D5Oh8Wk4U5B3fhgaYC+eT5OCQxwtOh+KQ7QRwzeL\nluFPl3KN74oJ7WcsBLU6ZDKRiC+n33t4iVz5QJI8Ag1HZ/O98tijD9uq2NDM0R3t/Tm7fH359KxB\nUbljd/PjKCBZoLJHhgCN7jWq3yrnhtUHucwnsx1Uba1lPXY75zlh1wILCJWdyy925Pa0ivBparX3\n9RHACK74mjpPeyTS7KxMqHX94RAEdW90rV7K31om3I3yWzbepp/m9mU19LXyFgGQJYv9SRidjA/F\nzqTa29O6r5oftrR9nk8fp588yHzqsNn8Y8Sv4gE2cTnuqvoTsVwrI7D/G3qlTge41hk4L+/4jMPW\nkh2mp+wyfwinqJpjfBRcWrjOALhnlzVwU24Ru3irNNzT012FphbBYVpAMcUNoeWPQAv73E8w4ijy\n0fXDQsy8rlB6NYh5UTqLPdRLt+r93RB/KDJkvsew4ofd4R4NVGWfCBrnlXpU9IH0BBPzFsvJoOzT\nwe5zbgHBIl6+pwOLFy3z3kzVXnZSSR9P+UWTdv+PtOpdbdQpBgDp3PrW41G0LWvthr21AdhVt+6g\nWKqMDP1tM8r8SKpvZyDp4TdYrpX2pWlWb29hx49ty34u0e3thr9qmfslCzdJt63tVBuI7W11eFl/\nF7uh/ZTBgUefXh2wJRlfs+bUINOCa6oN3XW+t8FFtdpepPHxoZ897GPC2CZTEwSR5jDYMHCvxnZG\nsnaTXkXM+M3Mt8Kl/pHk29egMWMhPRmpxB3QYY427cfJRoYod8Tq0c5XT1TgRLa6BDbDa+9tgDWR\n8OjGobVd2vGzE9DkqarBp9Ev0HqvuINhrfRtWDyclKbokW/4nS/r7urKLScCeNzZpRFFMZVgDYo5\nzSABd4Sr9XSIZYdqHj08G9DlLcxAfeug1c5Mzc2ZoQBgUtNRIS0uIUUWwHc33Xf1swfSQTOstAO1\n+ND5SNH3p98eSDSJpybyqpLV64rNbjTzdBVxYuTP1hnrKNbVkqvh7Stc7RsU2biWfKMU3EL+qjLD\npIrbJQpN6nD2gFvqagAFTidMaUXwDsg97a7fsYwt0C/xMBxF9dDqXDtAXz2kHe7fJgV80F0vq9HZ\nbMLXIN/Aslx2Ujt2OxAsdBjrlpOxLlHZ94TQOfMOak8iVP+gg+GbtenrxbDEPfTR55CEBmWMxc0t\nrMRDU9VnmNrE0dEwqJORpFQXDnb0vbR94mq5zPVCQM229utup45hXjuOSbw2tAoSdBMmc4brA43b\nxFjg5YqJYqOCatp9b5809gyDYvvbri17UkOS8h/ifTmDbdAND17zP8lk/Os8cUBQ1M6HJh4yypjm\nFlIteWsqO9+Q5r6ruB+ri4G+k/4uRIGbpUsZgOJLRMUpkPBsSS/OxP4avorsyGaXf0kze+8jWyKM\nr/dMv1SbFilMQB/8tg9o+WzQKziqwMnVrSlYcWg3QPYVP08Pk4jHzhQgZSWUCx+uYBt6aZc5JiR0\nGtZibc6L4msonXuDCvZ1+kdBymI0J4m/WF0LFP2EsH9PQTL/xdQB1PcFyp7mGVmVquIyU/ODHkdJ\nnZe90m4RbpSRMVJn+LDTZIuAkLEUEjdx3ojknLLc6j/E7M+0C4vE8IAELQl7UfqjcaXqynXqHwJo\nyPtPoYXnWYDNTyn64NeY5G/+lgcZnIpKMcwrIWui6lUMqwPwL8qGkAB1uraMxdz11MV0GD9ijNC/\nNYfqrf1G6oF+dfHua3VBcCCrpWOIde49TuMUjM8TNLcnuCKTxsWn9HbTtuBW6aneFwPtCeZHfEKc\nEkCt5xY9oYGxqInIOrGzRq9nbeltUFFhKAVJ09KNg9/hBbsQW2YEzPlylEudD0lxrvmcZrMzNlZP\nCdgq9GX+JsrU/GHFB2SzZBp1aqspB/Gr1V/AMAdqqGbk16ODJllHhl5kwaGLnFaLXgq5RL1LQ57u\nVMgk4udL56BLFkYBnmLJHLsbDhNLvcA957TDq/0vu+W8XMxrQ5zOO9dqVA4Sx0s0jHB3jkn760p+\nXbyRHaptH7gfIMa0fP3RyvWOIorSxSH9TMIIaR21hlyAkQG7rgOTbTHuEkhncMPLka72uIT5u/bk\n8BS+j+6OjrrgJOCR4DU8trtB5sliXc/HRNoFxeuKkdSf4qUBwx3YxySj+Xa8gwfmpUeNv/RafaWK\nK8bpxYZFzGt1pamixyE6Gm3yUm696U234thfmgfiZW9IxB+wD6Pr2mqDtqju05lOy4RXBuf15Adc\nVcJ4ZKrxrq7ynanaFe0K9HP7S600CrJ6LmWae6l9Pz/iu4QTUiRDD1v2mJnHIBqN/2qoZ94acshb\nxen8rhh9EkFmRjE8i7885pHPI0tuy0nIv5306RSVHePnYnomUNwR83hTI0TpdEhnras648tQyAZD\nyLNcBFz76y+JYyFNLQQ0f7J8Pwpk7rZQn3YIf5cjLGcS6j2xg1rbdMtOkaIoNQPbqMpjlx7ya0+K\nY+utyRg8/SFv1DXx5h9gJTc/H/tHdi8YDacYSWAoocm8X7qJGrQ4Wm7oP5BiHsUjmdIASjd9jRCi\ndGBNLh/IS8s2SqgrwoLawovLY5xvkZTnOZjxan7HZjIAVL/xnXC83cTHXHNW2IfgroZYCctQCt4N\nZiaYNeY5CFnYjlIO1DsWu9rr6dM1YOZOETeNN2nEazFxdUSiIL+Cp9KNomsvlL/lvKCjVbElT3MQ\ncK9PA4hSw80bl1EQz8c1wewOcEdXmW3FhoCD2fzS8fD9n6NHHloD4T02xerIPVxCY+G81LtPzKav\nA5qUBhrIYmZu2nkp/tZgcOolDcR6cjJwLwQHu+MeW7VFFqvr/WK8f6SO2hMyKNZRsDeeIlnonFBC\nVDwafpWDJdH+Dm8uDpiEmhYo183WmxfwZxYRnbuFneY7aXQVXdMkMkj8m9OPxJqT2zXXkBa1fFvX\nMoU+zBBjyVJg4NiUHtqvbQPeZONh+Xl5JHc0CN+wv5kXe6KdQe7wPQReu4YiajHue11P9xhedViD\nTZaeLRXK64YbI1rGc/tG40tngmAha108iOoSszi4T3h4Bk0b0kzNz5pSB8Z8detd5xEXY1H8O7D9\nprdRO/umf2V0vGgWC97Hpkzfi7vBux47rpkx4686dfIb4wsW5e/+24kaxMIHjSmSdhsIYRZpoqTv\n/61bW1Q31WUasDarLBChZpXCcAs3wVwcO+sQIrDBU5jZJInlBGx/OWX9m4oGkbjIoiiEZUajy4pJ\ndNtBoO+AlnFcuEVoOhwIRzoyoMUwQxQV/EIw43nqgD2C17QlsDjx1yN4ETNOniebRFMVoDHnLTAj\nMnIcZEVxIQ6DLULVJF5BWojhOpAsRcoZJO2O0h2a56q8uJ9/jU1CGHKEdhaoeg7d39rzqmEZ5Lz4\nma/3uWWaSLtbki6kO3SaS9DnUzh1QmncC+AJ/ggtclOHyIHOg1roV6AV4Zoj0RZz5SUrL/lMqR7K\nIMs1dvo3d+Kyysu11SsT1hACaVq8/iJIEjQhd+zW9x55GQ/u+YhU2j8NbEmE7B+SOC2uuJrjh7XW\nz9vWpt3TqX4zOOAW27s3TWGylv4YZU7w/Vvuqd44G2WB2adQe1KaYPj3bDe70i59KMwnFY+uvx9q\n/fMVEEiBZz9j1sCY2Q+ZXea2AoQtTQe5+C1WCYt4blx4/WbvmLy5tfbLyXudU3sKAOq2O/5VZioS\nDFKccHv7i8d/0E784nSXFoFWis7esrHdTa7MHUqvd3X2ZdDgbN+GE5ht6JTvnr4SAvtUFO1ccnWI\nYg0a0Ip00ySAMas1ZxEleSpzead93O90Y7a26XMyvOczGiq+9OifmQrcJK1J7sMPZA1GKgG1ZDxz\nILEzoUHRENZtf9wm81eopjj9XZJ9HAa7rz7KwZKs0qFs5qHMtZ+s82xeKtWFuJ3d/2MSDCIZo0MN\nUITWrSjmkqgGuIjCX9jhbbTwlujWq5gIWH0SZaq4vjUEH7HQ9JnCAVs/yhFKHyQt3Vagpvusr1eA\nFLbrYEF1oX+/53s+xJUzf7jzdYAFkN7kRWvwRNrM191fQZj5f/Oykdf2jA5cXbqVICcOiLIHXqim\nymoIJiRIpjNRhQAYzQ0bKfRgRZbKYxtTTf8nQOXxIgqecN0AuEa4YD/EGHDKuNxmfCUYnWsAhbxf\n8wfeOkLTqZRtNfD7MAsrVaRkb/DwKVmHjDSd5EeMhSKgY1jc+guk2LI5R8IlxWy4yW7PBE4g/nCd\nagjEFUHrsJrpGhUe7/fztwDDNsgBig/Y/1vQytfnCd0ST17cKjl8KSBlcWyrA0921kT3GkLq0KJt\nrYAWI9wDKCvOMr7xjjznaQnmuWsbslq+BAyKPnqeG6kDvmrbatLZLxtw+lo7jmhf18LMVEKxOoM8\nNRE64X5OmyvWmocNp5l332dB1oRRNIRuHLoQcWkQ8h6QPTFqKSsI5Oi84+JBgwB2Verj0fhBLs50\nqn97bcHEfWXCnGFf1MJLLvHQ2/w8oOEUufYN2T/raCg2zQhs8GtGK59WPnsiW4uZ9m0flTtnoZbo\na9MbtavVSRfp10wigCOhhiKOVVedOi9tN48i9WqreweFIwqmpbT/kIGV+LsjwKyTRxfo0MriDzau\nTlKMKHnlAah2PEvK1R+RcF7Jf5oM8J3nb6VkSGr7rbm+BF6vsccZvJaZu8SaEHrPEBmqfXhm3NPe\nW+4ex/FmiC+5Tnm1CmI+871n22c4wExSvE4xzmJL9CP0m73Zjoufgbdo163jmcI/Rlo35RgNSvlK\nbH+Vpx8VWuZ0ccRzzF14BDsf6XIczlLqWihQX3Q+BZ0UCqlEOJ2YUMbPoEkd4s2P1nYzML7gSArI\ng2puqrlyTX8+ZSSeDBQ1RkL8aKasEr2XTOTKYp6VWiiJcHUXgL4DYaGdNgXDxdHM5OaQukMbyKOp\nZ8lUTx/tCZ7JMi3RBUWbzG8yaHgd1rgB7gOesNEdwE5kcnLOADCRhztMrG/mQr4ErUBoSaEvjQgG\ni2veNHK5a+R1LTRuuhM/5ugyh6jsGkp+v5dEkJCfZ6lZEcQ2KCXiDps9q5BP+BkwB6ZaL7f/ivbx\ncXOVTyOAgvsE1iH5hBb5OdgeEZf7SaK8hBKOXgSVEwnwuU8ayU+2zARKYcTMzGPmYxXDowrfvLVj\nnkP5pIi09pJVp7gRkndJ929O3Jn3y0+8uvYFIVgbeL8aL8JsXVTLiJtTbJfwkqZNcfhDV8F7atYQ\n9jgyeo1/zcLJi0hBOVx25lK+Zydw9vNK6ogLTCoKoeu/hcT0TLzNClqr+RT7jaIGaMYyMs4IFlPe\ngyy/KLE1jBwhXKcrbX6Xm29Ef5/gQpj5tYWcuwLOWK5XPrEMb388AZE9vwTmRhq5Mb4lJ1VpU+cQ\ntb5joSHuZZWkndO0QcAUIoAK11KpLN5vmyeU2yRYubn8HiHdwwBeIoZM5F6YiF1fUe19OB96wEAY\nxBKsyH5t8Bcuwj5wo4Bg7zMhKUylfXB1uzDMMhilBYP5hg51mSXKvlmzmEof5xSHHRemWAE/dYUV\nAP+Bf+9kVh6aMEuanJ/GGkPrIM0v7D3mMcH1enrv/dlgfNs78BFIvkYZpJCFbdJiGAm3AFA23Q6w\nfSfWUQFICQTW5CIuvzBbgroZsBFEYO4pWpe2ok9G7bi26vo6VEXQzzbfc1ymaXmAQ0JiX0nQGh0n\nYanHWYxjqXGvDyQE+edWhPIMsqs2O5JydhNvk47E3YF3Iu/YOjfxOeLzpGne65Y0XYcGdHP8VwC2\njkVj7WODvLYH8HTrSmaL1Qtiq9ZscDc7qCuhWfPLo8jXYI7o2O06UdPOI4m/I7EIKI7HTBCsfrYY\nzIV6TGhwErzo2Q4g2YKal23HJAC3255+7Ii2xzk1hJoqClGDNOYAhnoz2ak1eHdhjkQx8FTqr1FK\nSFhm/7+2kgG4Q98heYV49FxIIImnudAI1ON2BdlZMzjw1XoFG2Ui/hkZ2e7TE8m7qV+YrHfW3hIv\nr0ovWG4FXZSWLhjplpLrtO+hudWPgmMYVXctJLtJlQdiR5e5D0iqcjj9fuYpfC/RsiLMo5dWkJNr\nWroX4ucqmlOO6hEs9Kj6NEa4QdJwY1FztCfUAGlYswKt2ONCHwLSV4MzJ2xN7NzpY/8XbQPTouq+\ngQxmvxWCOoeuG7GKHJzf06pohikF453/UK8QTeHVFPDmTder5n6+QcOgUctUxbNPcBc+In7toJIr\n/copnUSmKAHAVp5VyP3ugz0lpItUGqw7AfTtfxk8TtE22fgICcWZCKVKAkFVt+675tH+oD2PLFJG\nRCWx7n+4CM2XLT+dUUnEmpCfpAQgKygs2hjpWoH4DjnvrBWbfN7HQNrc2Bq8vllmjnc1AnGOEmRV\nBqnJQhwWD1GOd1pYoAB4SWk/zz8qBi/6NdcVVBCvKM/H4tJIc8gWs94hyJ8XUe/4OAJrr2OaH4oC\nb5SxQVwjSsRHCUBAhPpwPsZmZ3rQ2oC9dB3JU2juttVvrla4pmZ4BDyhbo52YgqOb/DiH8fOdGDU\nvHZSyy/SK9htTkN7M5KyER72RHuhNM3RdsyuzRBUKEvQ7eY529pX231lS1nSMn5FWI3RNtSqOl1i\n7hlisRC8Cl5ikyX/F7dk8JlMp90gjUUTarWTVzJnePHu3oGrhLzKbtaxrdw6p6KWWCUbmc7R0gCi\nJoofa/VexzFz9RVti0Vud+aucNW0NxDBzIJHhjZmYxgrFXgIeilE5rLJMeJVSrJqtrL9LvZC2MNZ\ntAhQpHg61AopLU8edP2qyUPdsyFodLy/ETHyht06BWD5hgu4L4J4Q1eTeZ+uLRdpKotqVJkYR/IW\n45u81Xbse5pVKQydmtnH/ST9d/HECozAaKV7y3GSy8AhI/5yY557c3QvkcMW++09ZGTv6wt/Iyx0\nK6HWUwfsYG/JVgWqGS1P35Pzjl5Tmfi32prK1vqqQz76eB31XXvXUaHI/KX6hyQ5V+WzECURosLS\ndoQqUaRYKoZe5sZRxuBbyhRsik1tpTZkTCClkyP06l6sS6lcic53JLxv2HIpQIcprAaNcQrrT2zE\nQm9ZrIrzX9eVr9Uxa2hbfyLgi8cDsmJrmTslW2/WID2hZudJlFjnS9sBIfrWZqyXJVOoIlaziB0U\nnvgHaorDItOFhocHvKgYz8eFzAEBLj7zwQ7QLcA2BX9YGl1Lob+XspA82J+lYeMAhkYLajY/Raa9\n/aAPga2b01vwfyLUsTEWbFpRwwmWOvWJb36HNCZyFJI/vmjvYJSqqIqR7KEk0NFW9CPlCC3tDX9q\nTCrUeKIkg9zDQvybya8av2w6XYUAi1ZOszYskE9veyMgscSWq/LcgLj82nb/A9Qi6bitgDFWNifI\nfVc/g4WBGM4LQt2wDr1Yzikijo4LQwy1jtR6F0r6gk9ng6fJ8aSRd31Lc4DcdNBgjIrIfV2k6Tf4\na6oy4OTTxVSYfkHTR0ECdOYLom2M/GJMi00UcdrYgNI9tGgWl8hMux4wzqR5hBcLryP455y/vJqa\nPINof8qXYIQqmNZQ1L1d/KL0mpaSOo5cXDxXptrdr/Cp/812xSUL4yvomv16LTYrb0ZDa2Lh1+oO\nAVK8UU1k3Oq7T3vVvKI1IeX1hzg7QWoNk3QtqeJdbsBT1/s18GE+CWPhyxDf9AgVhZdFrMgIhBZG\nXTKNf1KNUudTPxsS1knIQSRPVsZoIlIyEdOZpzJyNSXUrj9inMhPjDfEjVC+Qf5MOm+yjuqgJWGo\nY+Hu4D1WdCpYMUJxRXljxz1iq507D2qdNZEca7JylxW6LQAJ0vYOIqIPgWQ4AsV2zuhIq3m1YJuX\nKD3yAVX16dECAYIpGVLz8kUN3d3/ItcN5esC1+Vh+2bkZzRYtIACPlDd9ZT48H4CFwGJ+2CAucgn\nHP8QHU3HeIQlJwBWDG4rjc4GU/BOPVJ0Ml+KOam/3yW1gKTMonCNppyCS1Qdj3X3jYIIyRJ1pBr/\nbCxjsvoME4fkNk01SvW3MJW+eiXucZaQim2jcQ8Nr2F+WmXfdbTZe1aUc1gHmNYwDnMMOnCGRe0r\nhH5EaVOcaaEi7dFBSlcy1k3h38zB3E2Rt9dav7fStKQhExPBBFYgWS7ARmk+iW6PFuT/X3k+6SQU\nZ8cGte8Mtg2jamMSo+KbnFj9qKU1BIxOB7y98HxpcpwbYR5mZ9q5QLmVPdhNDmxh+tedYTOEkYjS\n0bU16tzQUrRQL5gOqpxt5D7RUwpmZzNiht58uEI756Q9BGzsBPMwLik+8g5cbZKHqGo0o2rvTxfH\nzi3DGk6WHzOrwJ9WLVBjKyP4VGk6+825FWfbac8WkOJniNHFyRxHaSRpzxeA149N3ENoYoZsN/0Y\nzp5oAQ/n9JrMPixWjJzYbvh3tldVZOyUEJbZUuOw/M+2tgEtV4AlOHdNc76ieFP44PPASbqvm6Lh\n7E9Y+Nx+9f4yz/ubwmz4M5/9uSyAXmnN/e264roipbCHq8lwnNCvRGsSiyNCGMZRWHukYkIu9sow\nxNPecE//2u/xXKA45TPRzweEdKpHbJ3Oo09YtOL/HvgTyEDdp0w6lr3xLRDgudo3ntt7RkKvDn1F\nmaLwpL/w758VQ3OgrR4P32ZlzfBV6MTBxrOV0951kuSf2HBhtQABZu5ia6tXBgHIAXakEhyR5+jg\nVJh5L4phm/voHnzFg/QK2RbsCuw7nu1OeT+/5R34xF3UsJfd7TQMl5Fx5g/0d915np9ww9kAB5xg\nfKT/DL7QFwS4freqdB71x501RH6mXHw/MK83bAIOIyjBHOWwYJKtDlMa/kQRJ4RMNTIKqfiUg9nN\nFSvRnse045HDlfFn9aPXpsRC+BpwvftumGIlUPiqstpHCu4wHiDCyxNR8/dG4kTvJ8ImTbTCV24R\n1bP5rdNoqwSzymuPL+HvOjHkyFsI9JNGpKMP1du7jjHYBPP5o4mpizTGxXdb7wCfg3AxkWwYOVz0\n6aV4tTgm5sH0+MrBbAwCSGtF3sWpJjV9DHa6XfW/t0IRJUNUgrnCjMSlrrgBCVowopcMx5Tg9HTK\nlrSHRhwMd9Hr9P+0ZuerF0qjOYUiC1aGz055AERPjGhLuyDH1ddczETrCQ5BtEbsTQAbswNOFuou\ngx8jaLAcO8LO6azPPhgf8k6+1ajbHU2jzostoOIQt0TXNoHg74xsjBNRJpPapzwF/pkTJf3YHE0D\nL7FBCBMjho0D6A/JAg+Uc2EahvZmma63XaLto5FvRjHA+fik2MlPBEQ7pBpFf1yNo//GWe1UnyX2\nqfGotB6AuEBMKR/Ep5pCcx2M6uq7+PjeMVXRLKfr7IHGEJqT2WkIVjWtcxMFuBIgDRyBtcqB/GJs\n7mOK9Hk5kPzIqw7SNttRUyYwizLEZFm8syNJmGgMWLDhy1C08+H+1MAsJ5ZLdAOTQJbW2a3F7zu0\nmjdQFe2khfKWV3VRVW21xd1ZKG4CiuPjp+zWf8mZUPGrIHrzVbTBm3QJMkNQdfV3swvUsr3zX5Qr\n36V3L1m3OL1ExDiodRjf0K5+TogtSXQmCUlKgdSkx+LRNEyJsInkWaIaS1lv/MZDFXmLU5HedJU+\nlWYOdCUZ6J2nlop/U2rUB8aUEVydL4VawEjtBqovNEa1Jw3I0N5Ssya5InbnEp9jfwNldEAUUyS5\nShD1nggYr/s6bo8WMw7BwyrZAVebVWUyyqxyHFwhtrQNFJT36e3GWjyd/oNBj8DtpmJUOdMaj969\nHK0fC1ERvr7hIFRB6v01yq6V0UjYhwSNyOTXmIcxozTT5nlB/ADFnu1v8sg4Mvyeh/K35mkFtvay\nd4aSEuXTqpdy1aWLG+25Im0xRSyvN8e03opI7d9wl93syrMfaaSL/DwkuV1aUOwM+6JtgTHh4C5u\nGJHL1lkig1RDMqKCj7dgI4yziQGjUEKUPHkkRp3JlC46/JeBhKHqrobyqFU9+41ijcFkcLGplOSM\nymgSZEufYr8uzdvXRviYDXTTyS6RJw/iU3005Xly9Kw1X5f874yVdkQCi0DDbo6M9Crkk+mmrdQa\nYv7kY+5eVo3V7kNYTWQl55Xrg6x917Exetjti9/wlBdombG+4xTYo81ptH3qctC5tCUqUNIHGQXt\nsOubU896IvuBrq1feM+QjLDYf+5413yFx35jXZh1OenHgpl4CBa8466lPGmy8eru0hVIcPf92oLw\n1bqmcJrFgoz3lRH7n9EplnkEggAl4DiyJxPyCqYJ27+rhgIabSJnm1ICLcZ5aTF7fQublY5qCXUK\nybsLsL591a/vl2wKICOvOFHN6s/GA2bb/9KRRQKS83fh5zXtrEFIa18GFjot9CsPSZqE53bDEAdE\n2LgFPN+rzDNKcX4aeVhHRr1hG1ZpFQINbW0efGCTpJkNigky/jBz0wupjx++Tov5k3mFyt+mah7u\nWONx/k9yVrwsFz7WmIOV2u31ABR1zg8iOTOF+l/dkBEzTzjhoUIZNhPZgAWaOJ84JFYoESk8ul4W\nOImf3y1weos050DxIOCVNQkxT3d58u7+PJLNQoEYT1/B5wNMqp55Q/64VgH2vqNpzxzc/msdB+j3\nV30gqKmKCigYi2A5WYwVhDRsyhKhfaTruDOZ1yoANMRraitZnLg393k0XaspWcmOuCDUdwPRQ7DD\n5fCWt++EqzmBDsKlv5LeKTc5AmQXYgCeDLU7iP48P21DVhpmOW6wGOijWQA9ss+zdS9DANLpTtMC\nQN+P3Vm6VIopBWmYOP5Mvlhq2AxRMWQjrKCLV7dHDyEPLY+pqRK1W5zFTI7J9aomgYmwM86i57Fd\nE+BNxa6yNPdhwSS7Ylp5l5LvLstktQqNr2H1DPlaAJHys2/xEfBhmE63Cx+YDrthBcbCqTgePriK\nYDNv8+yCOCxdZtu7Il0+lLeDNNNuQgU6M88P4YZ/eKs/chGDQIVMratBAUFfvZp994h1TDBkCM2X\nh1QaoLnnzLabqOIpPr4R7/C9DZJBU302w9jePYT8d4jgUfsLXKxugyJ9G50LBK+NNdqHXw+h89Nx\nMR/mnBj4eSpssSCqaZvLoqZxWSNk5omTHXY42A12BCItxXQ34gg7vR/kbJ9dbVQaPzK+WooeLCQA\nfyYaxN+SWTywygfH2ybt40TosMkueB0uBr7dBEkYWzFnSkVVPMqXzR7a3FQCCcT/+4lxtY6/SQ2n\ntNjqzdIq4OT/3wFEcla6pWJUhGx/wRoE2trseonvqnbplfJUSpuEYw+hA+k2lTpATL+FuzuoTZaW\n4qpIsitXAQFHUKpvQRHSxz7nFnpS2rczkfcvHacT9yFeE40ABo4zQyBDaHyfnxf428KFALYS+4kX\nqX9+wO7v7jzIuQRn+I+ShEBFawDfa7ErbBlLvByZC0Ooro3mrl3E0YniYCiyxumMcxDJ58rDU7xj\npMrWd4vWmw5TgtyhV7m9TXzH45SdA5oxsQtP2hIN9cW1mmIG75sldf1L5CeRjmCAeae7dj/INwJK\nzk/ZAJDNy8GYhC/2YKXiUvcLAEUVDzZgqqEPG4U72GDKzFQQO7rNlwiGw5IPbvnBpjJGXJvC0c+f\n2kEOGwGMrRntg9pUhqJ5l0elVrmwkyTzUnDCPbrN+/X1vPO3NOJnjo5sNMHMJCF0rh3QNDOIr4IO\nzO45k8dl1fReJBdCIDmzOze8/DxVLZeLTuffWjfx30cDs7ec8YjMdsJdcksykYAZYCSu1AVlX91m\n29yyH40rYntfjebc4IwouxNzpYvHs7/i0lRLT1nKUitCloKJt+9H+JCh/5bge2AhEvhE6Y7j1pTl\n9BldMHMauKhb43pVMqXwEzAhwOVfmfo5Yqiy7H5pr4mPXu7A08Vqckht+hF4tNejsCd/3Aqv/uLm\nfdNBHsVwBeyUv0bzm38ELFpSa3bdiIwFA06FvU/OQ3Us9ef3gcwDXVtz47U8ZN2sLfJiNPwBk2iF\nIz3Sr4qqKAggKtkUnesAw5HghZiZqLjHcr6XKKj6EKJEKsfLz2ML3bkUlUMMSgctVwV2F8gpQi7m\nf34RmNCd1eM+SEZp04x7GLsxIUBiWVd+GTU6VkrB1u7Ae7PNtTHte2D5MaCAjBzCSG3r1IIB3zqR\ne04H84z0KAguQ3KPV81wG+IQqegKEVA8gU6AkL0DTVFV6ysuhZl4eHJDu32KJaD0KyOwghltZK/q\n5pD17Vqx0GVPj2+vFJbXF+WB9kUDciVUMlykGI6MU5NIfXowvOToYQfzYa0luN7QvJ8oqqn2Aj7w\nhOAUav/TWT2Cy95gHmaSy9QwuslFun/vlRipJEC+7Fl94nCmQ7GOp3ic9pJZTej0IBeAMGE22jE+\npVxTWoC/xkhqiRO0Bja69kMnjl3+tlBn2XR5qPt8xBLZmlSmNs7Ecys8GaRMlquBQre20Y95QOjL\nmE/vV8H2BDkZHU8OXKROYMeGAVllq6zMytpAji7jrwAvwid6dhUryj1+BPH8HiLu8Z1VkAXiwV98\nU/Ss3R54RCFLT9r/kkFbEAEUIySZIWW4N3OQYlBePjt8CTmeO/NHjmBesUk/rlWruw5Nuvw8A83h\nqh06KbMajh59HgboJ1iEXggaltXzKvs0cwmlBVeJjJZ62z0lB4fgilyTVuFzE68gbrvd6x+O9vI4\n27KG13EIHKfcXoUDBNYM68e0KGZAQogkRcXEziLWjBF6MX/pkcC+oklNI3Gs/gZ+vmBxz6DifQkz\nU1tnjv37W9KmfKCzDPooP8xIWGKQ4Q71Y7a+0FsoDeWcPuEGOmpTv3l4U/7hMwOfNaB5PhbrpBOj\nU6p4MFokFbSm3Pc0NsusQ9qwFD9pgZ3WlepprE7mepW5jMBDsVMGBWk1ZSxxcjEohQp9LzHSY95d\naePuYKS4QZZp4Om6OXcWSFnS8kO/IazK9g/tUOg5lm5DGIIXwLs9Ownl4VvJEWpAX63ScQZC8TMe\n7ydRB3+f0pBl3B/uIqA7SlRZPv+m9VulNhFUKjufr4CA0Kd/+GmsIneaKr/IAU6lNEy+QdS5jpCc\nZoLJQuGjP2NUGX/Jg0T9VDlac0ka8vxMZsOeJLp4JTOQCWpA1tascKSCfvGSlU+UxbFhQR997rGc\nzO/Yad1G/E5iWv10z8k8Dl5QAq4uMytCm9K3C8VE7q8ljnfKh4HxQbos17ASA/UH/KUbm1Vyc8oM\nJGoOaaSMSW3dpm+IsXD9vQ7apnxMDa8/dr/Bxe8Dmx31MN31qhC0KL9nVs0y/cpbQ0h/kenwbmAr\n8Jp9T7BJWDGV23pKPp7/kQyECZkTrGQKcPCv49+hqcq1P/copkvNxPrexPpdswujRHcY8shfkkxW\nrhXm/92ljDYLbcMIVfYtHQzBlVyIn9LeDgV7jar2s+slqfnBFE5iou7iAN9PcQCSlVaoJcDokn01\n3uq5Oq04HqH4AgwkbuB4DjXjylI6jlryCGdok6c9bKsbMV60HPXnKKgCxN4ZUSIq5lTCVCU2UXct\n9lX8mlTYcyFbTvhgahavj13t0R0frHH6qqYlRlxsRcvAm6/ZIOYGll/bvxS5QtKGV5+FMl2PM3nt\nDXXCuPyN7zH2bvCOSo4XRml6vJ8woqqer3Al+lFYkHKhNFpYJ58njfxJVatQziXAarDaehegLn8p\n64mIM834mV3cTo6fE6m37SsBE+FaOUL/+Grgn79OUDoeA0FnlYjVi2fLCZImrYmVFiviVcE24BcO\nLpSZVFCkSQdYSBo1sYxbo4o69Ap8B3te615hKCe5+vu4l6Jfz3AzR6bZK3C90Ri1p93M+2yoCPNF\n2c8mUhhCf8H5O5QAyKWEawPLS9VjV3lV/mZUjoaZafyTvxxZ985wynkP88y1Yllte3KO65vzp3sH\nyf5AnZmZOiUc/DJKjDs6vq7VQeDlExobEfYMQo8aWLSuXubBgKHe/e9OkIiHuOHrJ04c7ByTBIbb\nv7pwgtmcyVKoffFYI24yATt4GWgf39XkAzpkXh0Syod4duZdatRGXnHZGwOz3mKhyBQ+iyWX09DE\n2v0rZZTXmTJ5P0FhVdWncu896/w2OXEQIgi+ymUc4I8Z/b9N8a8KBwiXrJL19NbYiSbAeHe9BKOG\n0mb/oJrMT1Tjjt5CHN2u6phe6amWhSsTib/iV7EXe14lo98ajjcFqRbK/Sks20Pti5B+5nbqCzuS\nFcH5dfZEudSja+ynRfCt2C34A0zheJ502+99gMeJwzwjOeRjs5EHqElPq3Oz5bT3AW5QxoETJE1o\nYADVkuGXmSy586Jb9fCDmJkhRIINRVju9juR6smyruKkp/MbUBhGnYuSfeXdQGdpDf+z6dTpDUmN\nwEA1s0kfTt2wjmge7nvu1LoKq8pQsqBRF4UmRUJwZclSFgR6tlSNTd3MWR005BoyK99u4AUJ57fI\nb9w2IU8a8njFHRcFVVO/cRAzb0beMsQYxNGwqt5sLpECL8mbiDq3h19DsEMdwDJSpxf7sGrp3eoq\nl7RlsGq2/2b5rPoVyL5bebV9FtGBxS65dJipU1LU4zK9zvxNouWvr9lKdDXfy/MLiuN8ENP9qK5w\nrsS0sYSMRdnSge2nXKFjT8M2gLysC2CxZVi5+VSRIjPSecYjNV3OHATw1/Pxp7Yn9EdR1StSyrE/\nKn/uG2t3USVv32kFb7/EJdW9TROW7qeaHABKRRWn7E9bFCUeabO+aTiMfI1dW4CUvl0dL7vaR4Nf\n7gdtyCFeuRxHtvIGBoYWMM6dU3m4JuMkxV9sb3SCX2LIkTjMuVqqoEYqigpzxoc9Xz/XNxY4p5HO\nQF2mDhB977JL63jVoMtCCJ7nqEt+0F5kXq1mhDdMiH/XHucajwY+UW0ja74VXcxFKBeMx7opL9M3\ndxQlWueqw1a8EFSu2yDbbv2LjSafjSx7MzgHTo1kQzb+oe+5IWSEp8dzZz3Ehr3GO313EZhqDLCJ\nyo1cahPNbeWe5y9/iF29OKxnj3171g/q35nkqP0cFb2hVGQKl5xjdtJBcDRxgvdjMl5yVgLU2Y9b\nrWMc0J/qMf6vh3H+8m9e14K2oMtRUOxNAJetHzvZ04Xho3WY2e5vS8sZCG6dpavxRbLqF+J846Xq\nfW6iHuEJcV6DYL5/nJQN1VjaWrU58E3WGiTuNCo7TT7zwSVixJmFk3rujd8bEG0z7TuG1XTHp96o\ngIotYDFLuhBJiEkG9h635N+DuHDcpjSLG59bWaD4MulB6Cr21EwrQRi5EmD4qrfX2kSulW9lg2+T\nSxQBApx6L5b4XbQCYdmmH52GO55M+joKrrx9loNCo/RCcwbV9VBIFZTAcpK867qktCCEVwx/Dd+h\n5pkrJ7hiLtwEFZRT2ZislK2uLL4to6XAEeAUDtxqr7GbNB94K1mPXaotsiR76kUvYQuOJYjEuADV\nOf6VrAuwbyVTdBVSmNIlHwxsxbOMk/0y405/BU1d5RfEmU28YEjvOLEOUnZEYmFq2TpCz/Vx2BDD\nyAW/P5JFTM0U+aSlbnXCpNdtTQ9z30R1jiNiJ9agXUkYneoMm4OUYmLh+MQbAr9OCWhI3he22Igq\nEW9cFCa+j3nh2/7cpbm1n36x6TK1o5A4Rv8dxbFwPOOrfAX0F1kCrnfwMsZPTVgKIvnxcM7/x0xm\nlByzyuJQ3BOd5mcHrVbFc+ag+T4wxWu5q38WDX5YXu5kJqG8W6iKBbBlOQMcCdx2nOeEQde/jNm2\nD019hojvLUQtNfcyBpmYNINUuTW2gQ/y5G1kO5NrPVCFZB2LZuCTBd5+jgpL9tFW2st4hiCvSlLu\nichX9D1u6Ofi+bnWV2X4ZYgPRp43BpzDo3ueScSZd0Bd05z/8KuIcFduGl+Zp69OE0qF/GEGcWpl\nAeztSszzda7HMenaM9kE1krdXCiAUB0Ajz/wozETFLzKW2B+3LXexCohOfTd0mVfO6eZaRAame55\ntGRtQ11CK5ZbpZgJyKXFLCMvQuUPjG5TMYupevxtHg996d5P6vZiJ6c309oITgKYCQTIXd3yGwZ0\nYAdT6b4z3oyndo3gn+5NGTK8I784Si/tzNeBRahnLMohdiJBIZq07tMIHXnJ9jgSriomJRYlnvrI\nr2Co0DQyoaWtmG7/bxpojTGGnujddcpy4p47zux4wux+X3gsIxuGThypOvm3p9s3xDfJPyl5BtMB\nzm4dyFFlMDjY0T/iEMgc/PILkLMvpeX/o0KkjWHcjeMvjbUydFanl23wFuJ13hfgkYdBXtNrxaSt\nfQ2wug2M6MQZ8LhIeDolTyOeFbfDfZr9KloIeBY60JcyThg7h+hUrjlexvX5p4/wAOyoozpTb14A\n3OQzyJB212FMJeQAqnzivRM5H/t6TNkZrmxyjJTSlKPFRGtJdPFq1OZo+SZ/ZcKDkVQra1pLTfVx\ngKvuQ5DrxsRbmWk2tXvvcjR9HlO9vsgBi8YwwLCUxiES+kSly+QCcDhQFrS4uuPvLBGlvNE+qypT\ngNhoqT5omTrutTCsodH/r8ZtHzu3ac+KUWaTnS+hBl68l7C2gSpYQ6ev9MiWDfgnwp5sVu5nE8mx\n/U1k3lBrVRDp9HQQHl31eYMlRA3YYGNrlERa8KNRy7BB2gnqSNvg7MZ9cLRLXzEwCxLvZ6FXGOPe\nZXOZRvZhBE3/rbYcXAGolgMBq3L0GogQoVwXjOP/Lp9G+YCCsvJPmlulYpyi+yL+t+3uDrkkGXBz\nyt4LZK+9Dxtt7sz7kojNmhRi8l322KZWUTrqrFsga4uAsnQUKGIvCHECsDVus3trG/Jw28NdLhJw\n5SB/UCFRmQiSNOgu7qMbv3CQvsDdh/F4f/p8UrR7zs2QpCCdAz6fyUSM2uMtAQuhzOOWSZoKkXBX\nkZivZ0cYdpBM54ggQukKYW+MZVAUpOnpOijtNEcfDonhsxh90B+mGMDLpLKrNMMk2raR+Ny9dwWL\n0RbCeq1i2L0QhPIWQfauSL4/637GKz4Gl/3Ql/pJYnN++tJA97AWcEusf5A2KkfoIlhecxBFff7i\njP7PdcVbCIUdDlBMgJXA8euhybHk2g1d/aXCoF5kMYl2/C571d+hgTyNMflnd2zyt94wxzp+G34y\n+TypwKOOTT6pfy9RtUcbhcPfmgXvMf8Pn+/Bt0jh+piQn1/lcF5Ru651dmZLDUTz2Nn3CGSpbEoa\nvuBhGmfuyWALsHZS8ReZJh9h5NWtIpst5hylDs25wYVWBovObmtsbRMZ2CxXijcFbjN2VNytXc3a\nwXTc3oJMksMhk6Zsm6Wst37x5XW7WKeyI1kASTtx5wYMVAlmJ4w410QgFt4t4YJffV1TE+/5jWbX\n3uJv2SoKj3A4tU/v7pE1CSfzlR5Qj+rbRX9mVviCtSDJw4RPbVjLXz763BZNlTd8F9lqUIgojNYJ\na0Zg/6nSctDAuSTC6E0yLPxYjihPW73Xb9l6hSt5NBHgtC1c11/1isoAhmXbzJ0Ih/fsjIeH9DSO\nyVMpNCmjZKq0TH3dNIFdgK7RpcWxOfQjpBuRG3SEOQcaOnDRnsuyV6nPH3TsjkNBxRmus4+glAtc\n68WnBSyhO088MDCHcPrALvTOR4dipQjiQqcondvi/P12bArUHKz4tqLVM3lU6+HhhSZYsOJTWN0A\n8RWMHDIQpSsmI9QSecrSUHxzcXSgiLUzY5wAXwrwboMWZkKLil+3N9nKyBADythgfBmZPUSDiQ8p\nw0q8G1W+1NllU6qrVMax5xl6CQ7aPgAiKi073hmkvsfwNHhftDbwm4tJpbkpuiZCpuS9IYL9wXyN\nrQxkh2bIfkvEbpbjICECrZBPlb1HraWomc+Q7wB5+YyswRmsRFXJsttqDJuMYopK+i/Tt8fV8+QU\nRq5autg/hBEFm2dIH2sP68TDZTxPnb2fdiz8spru4WgcWTtMolhJtscqX1WN3U5TwKLVlbkmdihj\nFzq9FPZyevKYPmuVCx5FFImmbQV4u3cbBBJzBEi9iqgQWLR9dXEnqqRSGObmQd3s/4GEg18NOv/u\nFDNInYQbZa2h0PwRJTZFdyT/oZJnbMOOwJ8VV9Yw1nNR/6KTSHUDXp+MZQ84nd3Ib65KrPaPWjeM\n7aQ+YnbtIO8lCbcYqm4KZyQbqKg2cSBa8S3P2HJvhkhOz8ysiWwhFZKWV1YhcCHhR7MHmBUWwt5f\n1doPV4dmbeOMOr5+7SGJTVc2KWinUXPty0/cZBmTRBTJsI4SQGa+gNWJyDnUHJmwCiPWNU1Ybk8D\nMB5hDek1P++XUjly8XN2aznRewYffk+gQ6dv9Gd+urPvQ71lH2nKbnstVGKJxpvLXjREEEPeyy9W\n1/K335OAbTryL/VzgzGLfcmIoZ/rg5EHdis7EHWS4Z9YiNh5LMJJiTsA7JepDVzWWzCrBDbhlNGC\nQW7bsWvSTKb5DeCx32RIrR8+9sALeo20aiBUXHStCKGfzB2Ea1gqf2l5cHKa5UF3ew7K5umkH9J3\nXy12TjJssr5K+z/fBZhEvP7A1xF9rV+hBWU2DhXAN3rPMKb86dj37STlx0e4WlaVe1behb7sI69n\nF65/LgnjQQNcZPPfnRkK1ZqcS/FsrRCPj9gbQwBUjLeQ2CTxCD9gAL29J460Gryv8V52h8QwL7Wp\nX2yTMG0i980DlF1kVZWgrJz0ARaKPigRYBHzCKBklRYLwTHfrFDB5GKJ09pZ/WIrksaemNTjq2Wz\n8RfVF3bbOCH8Ez2gqiP4vTWlWy7ravKcbm1hlf8yL7OWUuDN3qXTCPIsyNkea+OprKEb1V9c1vVB\nGoIKJJzsHCSAuDP9OrqVQjbldGq3iVxbtqTFOz/H+Q5evaZT4ePMeoyV9xc0qxx+wwc8SjRkXsY2\ngUSIWaCqGEm6gZBPpLmW3+u8dUpx+GYT7vE+gm/TmN0UfVNydTj+xiT5iQWlb9a5qfoeDZCxUNef\nCUt96bxV7dMu+d7CeHzpw0yqVEgxeIL+LzeddTXZ8IdMIvNSTlY3IpxTrasT+xqSapwhmUXeq5WZ\ne9hpm04afULBOn+fQMlNlUWaq5I+NKj2vWPQKqW/4hKGpZXR524D9j+XkQr913EBtmfUawhAjhvN\n1LH87k76gyNo0aoBgZVvI0FjRLeTZPZ+uQU5dGkSPFeLC6MHq1PfWZiig8vXxLlHXxtt8QgMIRBh\niVQqO7l4zqS/RuGG3+CJhmRuWZQDUUv9mt5glJlzECar5GeLnqk39n6YPzYUIL89SJ87FvICeXnO\nOYm4+xpKUY8YyRLoI1x74uJebj4QJQQERvouZbI2qqoUx3sDefDjCU0aKPOiyM2VP3E0c0QYF3SA\nXloTlVOL/V6d9pdettTOWHGomQpM65vkBotrUMDIm4Kg/03FicoVVsJ8hytsfj6d95zm2qR2K4LN\nTxr066pIJymcV/utnFICE4Wx/wesfoo9RqaDKrYDPskGmAVvbUtW4BBk7bQRhn9xmqJg1cmg+WqC\nq9y7J8ivw89IADCWu0HqXU9/rpOwuoBtPW5vYSTSgwhcpqqsclTxtGemkg3YDxzSkS8MqJIoZVXR\nyZL/lPiizAvCPTD+8svK2jNdvSX1sLBTncvEFWE8/xNenAGTxkjPO74Q845lu3pL+NQLR7+uUAIK\n9ajzwvr//+Udx2T/xhFFY+q9J9V6HyU/ANDnnOifo/kLNC22wKNRDR2V5z70IdlxjA0uUXkU5Pvt\n0dsOBEJbfmnJxdSN5dNhFFZ+5k2hGPNj3g27AkiMC88K0BxAy34kkGVtpVNXH8PM3gsiTs9DD3Sr\ngMs9OumlKLBNBOfBLstlAQPTQIV6JzsK1q45xzQ/r+6vh/1p2tnzaMjEt8jVDOG66jhVlU+ZefiB\nppMEiULy4t30RjCNWyuYx7r+FcsLlH7f4BG4why86ciFSa68t974eQGHTsDmiWI41osjm+oGQvXr\n5Kybws5ceQP47XQClLgoiOCtl3Rm0Kzhrpribo7m4YoeYG/JKhJIBPu2kX9pXmq2xexb5BbrHu0H\nLsIfPCsFW5+xh81L1i8ilygAaHYYdKbRe3kl+s9h0EzEN9RKuWchLRm4v0g6AHpxzfQtTVFedPAA\nXNHcaaXnnkDQf7QKMflNsFsOu0RzzmIzpDCd0aZ8icVA9/JXWCx3hOcCxO9a5VfRzWop1NUb0qDq\n3yL8qJ6aSvCNx7F3ZsQXrHhouM01r5/GFgjkgzJQs1hf+AbaDi4aog8pBS0ZFzQPLmPe3d+CQK6t\n0SBcfjJFp1hJF3stBzcp1IDJtN66rDgUV0e5/6E2jqLMj7t+k14qLU9YJxO+wPz36NmAKFl87K8s\nKleAT/bcGlsDAsYEUewBdbmid4fjrVBWHaY17I/crfviiWkJ3PJFPBxMjnxbz3jAsQAQ3ebM0eqU\ndP44I6osOfbc/LEgEVzNjB/MAuxLVba1gFgRrvcGi9WMUyKNgIwo4oyKP9kNk+oJ08TIEkI6ypS6\nq02apDtw1pafX1wGr3f/l0E9noRU2QKEw8XRJKY0GRo626q92FVyqy9McN9auU62xSYZzV2ENT0d\n8zMRXSuPfc6k2wBCZZe3fpu9MoDZ1clFm+1OiJUY85UAEaYlACjuDcbeMiJCW+vmF4QQ7fgaS+Pe\n+Jaosfs1R3P2+wsQNe0C3jCStCn12zT27mMQhONS/kP9EfQMYaIGwCr9IoJ0DvVAoHHNpS4M/9Ak\nxWXQj4SXcVjffpbZnrhX8gbawaJfQqCV3aWdpzia9Tit3QRiuaKD+85IsPrRZEtHEiZRCszFocVi\nWCJHROY+i/ewpdWO53AmSAM4ohn/vb9AwCftusuyGU7WTlftQGy5Lqn+BvdaXhlbsLoj0LT9bFWS\n4SGJLRDJVF6ZDV5sVLBDr29JfyxP4z3iDtorbLvQ3Jje0ddJAaS6XMsYDJDtuDCTFhr6JIczx1Ry\nay+xdHEQ6oa8dvFmc8ewwH8lSMaRed/JtEZ1O+25EzBt+qGlkF8dZg/zYKQwj9877M3XFqbmPAFj\nyik8/e1bIlXeeOVlfCqhevZBQ0mfvzsPijOdmKqBePOwOK8yPTtQ+0EiFsGFRjNovxZ3c/73pYGg\nnaVbFE2Bik3DwnE3VsUrQ/aT4AfQV8FSnRflVlcdxHqInvzzosA0uEYlBeBgmpszh2WHwFzx/p2o\neX63zUXRfrihqSEg5DwmbPBdRBO1aJ7v6ZlGdMLYJWHOEZYCRHFiJKMdLEo8MvUqBAlWWWIwzC0X\nkKRl9yHPXx9iD7bHzZKVXv645aCLQAtwK+1hX8/pYx2ogKr1COlTnWKvyC+2Ts8FvUQ1WqcBDwNm\nXAbHiCTKR2Komh35BhQpIIdufLeJ50brxLeePeFzT77dRBExpA43OmmdrgOj7OJbFMyUXfJDFNc7\nqLtibMNcWqBJptnziS/cdhhYgzrcH4ulSU4vqGXYZXxK6WzwRa/ZTDybX0nq2IF5NhibD+g7p7Bq\n0Y0iyuZdKPy1PJo2rlamRQ2BfbKtISnrZnKlLd1oxapfTGousVJ1DtD0kles+QtM/Eo8DGGPozrx\nmz/3Y5ggKl8OGZtLwq32a2nKisZLsgYjnO9pw3lXDK2vddPVmsSOVRfsVlqhCpHRbl7d6WEBO2l1\nxVWRSjBGC2q2zK9qRYb78J0zQKGJvB3No8Z89+xFftIgjsw34qGWO0LpC1dwB4EATuIKbRT/9qOz\n7cMJzY+QoJ/NxXJ2XLvUhedA5TIoJw0jNsameuikdR7Xh/pxQvJnizDxn9o7cfMP9AKV5KzCzdWr\nWoF5uXCZpIEXweDi/4ZC+27x4jsDzOFY83EfTUk+YPKCClUcCP1KzZY35SGPme5CFkI7G/i81OGC\n1w3mhWE+3dK2SqT+e2Vy5xA5NuSgRnniYvH/8wTxhVwy4c/i72Hx9uO0jY/6MlpmzBKVvzMnXh6I\nlzWY8GS4nqcMFxuYVpg9I/4ROvT36kntn4FThkSmf7oFHCbw3gPeDF15PjTEj99VXQegYkNEygdG\nWbor9xaVXaZAGqT35RDu1CwqjWVEgTh6cRyaw1t1dl6hqxYF69kKdZ9vVXsw+uoKbh0bqijacnIV\nP3M5uuvQIaAU8GYu7pD2Fa1qSLBjJC33RY/M1M2kl3UwpNyCMQNtFp10RsQP1CFVDRdWW+v8GwEF\nZ4UFR148ddBHtiv/0mY88ET2F5k590BThenIwYmJ3yN4rr4ZaAPuk1W6pUaRRE+V4OzmEb3p778r\nMa/L4ZuYjA47R3zyVf2cXcZKS5klhHfXbxUe7NU6By1P9plvZ2Rt9MA2vFyzzTLzPvdn2oQ93/F0\nAc1UiEZ7NAC20VNplvgEQkCY0Wpaaijkh81IDeSErjLwkg5N35qCKKfy/UCzON3q/xIIfry5aLO+\nwnVGB6E3jx5hkYbDfeRXsZmGX1SngmeeL7Mw2uCzE0ZF+PpBzfihDASoN0e5UDZJBOyEsQ6eB7yS\nb/KVr8USuiya2TlVtqcSmqYTZjN3wAssB4Sjfn+nBNNyx6cGmEF1hazr7JZ7pe0DVaZjiR4D/y6G\nIUbTmrkUj4mg7VGIjbDTOya66g8vkJavE3leVLH7A+Zv48qUJR4P2damE98Yvp9RBW8jieGk5x/e\nVOSsQHQjcBYU2Qv/YDOtbiCGQD1H0bcrc1W0LCDzQT2N0EDprBycPMz+JoN7lztOtPQVDJZWIuMJ\nrREgdiiqf2crVv5VfBWukCPl22MXrurqd5hyFudvxcZZ3VZu26TXPEhWLjmtzinGUpOrGZmoUR8I\nsuYBrAMF13xjDhuK2kpbMHexkLdIUk9XQ9o1elC/OPT1DeGGUPOWIj3BSwhafp1T/IzVlx4lr2sk\naLbm7/gKQQbTwunzOBpRbm3mS7MWWdzkA6Q9uAp1/fmNfws4knqj12rNZ/oKOAg6eunZ3AGHcEpK\ncVZxTZ7voVXLrnMxfFDg/iS8g9ysKfeb9BZJcj5EgmeV1blLOz4t5lsNN35P5MIEQzipI/Xe1H69\nchOoiPtKyC17qNQMUM7nGPBk5kGfITCoEJHMZnzb3PyqghtvXllwKOf8gc5J4BYOKgLY+J9osqGY\nVzP83I06J6X+S0YnyDInYsOAyHCJxItdlajiXYHJcC4LyBzPE2NjFgu2PbZKDu2E8O5j/EpJlb4s\nry+t055JEroxb2tCu3n6bwimiyRybussiu7OR7gFiOEWiNZINUngh5E83G93sQE+VdHWPlpo5WXr\nBTOWKDfViNm8jFEsLFkHrsmWhyFF2FLtOkXY1ClXh2KuJGNhF9JfwSsEoaVgAUONaqFJzz0tEKWv\nkr0Rj+nV3Cs/qWw+gJtHkX5Ln2FfYURYOkKfbeaEeQsk/HsfcJ7MISvUrjPvoAl2Sp7dx4fOglGu\naEA2K9nx+kcNB+y3VlShrPF/zC80abl2nXax5oxxLKr59qK3LiqxGYNlroAK2lhntjaIm/MN/dke\nobLPvMCATBu58pKeKiOiAwBxScxr366owAZHN5Dm3XzS6d5q4+bqxK3aEpcqJ9+QGv63Mzetwz91\nxRCEUbCeuN5KwAeeaLQgDqM5FZCw/SNrwPFpzXYIkt8A3KLms4UCOdhvHDvPLOeSbG/Usb1wf8n/\nBkmiJkAIPN56OhQZH31uArgIFmZvVa8v4GOpFHVuTk76RY/pNo+vIhbE1aGHyzC1ZjmvdlQVz4gL\nCGA5Pe0tVKQZJzt7tUwCSRfB9UDEOQfbPYtH04FE77qSUSXyqS9GCQeb0lHX6+9rD21OYymfamTa\ny3mQYvEajojk5LOgNgvRDvamDtmzjezQ4la91Kg3thy0amc9t9A1h39zbdIux2QVQZlvW9oWn9us\noiG2gFdEc9vl0YPTdkZy1Z86anqK0GP+4y731EnDUy8sFXF8wwqQvYovFBLD5jsW7kRDocCPP/jU\nW9TwuRBydI/EaxwzFeNXxYDOeKC9go09CAoB4jEbxCysaxzYaIaviASwPXY0lcFSZqHjVwieTLiW\n+52naLi8UlKXX5Wk88IXiiO78+XWcU8pYYvz9rXGU8Gpv4hd/aG8x/T2wSG4aN/GcJjwx75IsCDP\njCAd6gQK4icFnR4MeYSOog0jLnruZO1aICqgHrFKVvz79RWZA1pQ/Gb2Qk0BNAxOtuE1K00MDQjP\nu1o5rsa0CnvlyEcNpZKOocn6k+4x7eA+rSZfz85Xy1G7gPxbnfgK8dfGre8Fa5FA4kTPJhCucNop\nhVfavXantqjtKIQerOLo6XDlM3m9ZfZQ1JvfSey86sQAzVOwzB09OYhRr1dBNBInKXpJV2zfENpX\nL/w79oHUMVaGIZwdWUxRi2x5BgdFv++rwnP7WV6i5V0nqEZRq3I6CTaALZbJ5/x+9urw4DrwKJPb\npj4IFVDGerspwcqUExG1iNFVUeIaUcd/QnGi/HDg04QhkdPqNmPQOA+UZwCDP5qBR39VvNbuwnUj\nOeOLccNbQoPDs5RmZk1dX0Fk2D5d2/bjuzRz655Fml3s7MsifinmkDci4s33/jyEr305losfrw8r\n2GuDjVl/oTyHuW5j+TK8y5gWxELKIE5E6NUTGYdDFppKsOJHvM27w/o0NuZQHs2tRczDkCPyI1y2\nymKxBGv//8V54Ch0dBUZtxv7Vb6kvvZ/Mz97GwxnsP6s3Z4ZGj3JeNkBqt/9DKdhjs3lVFXx3DSv\n6yaVPmeIXIHdhUU9Znnd4cXb/s5j9mQ8tjx58ypBskENDaL3syx6Pvqr1MgDWznrFqdkSLP59NAF\nKjmer1gPRNqgiaqZgkoCLMbFLT8qTVeWbFAfZhdKRfnEPiaG6ujInKrPuKRvpUmOY3jjKidFqrKC\nfNwSVqi3zoeQvi/V3pJs0YhvBWhvYKeMe91soJVd9lwzwtPBsFGJqzf9afgqN1k/D1zG0ix60ynZ\n9wuiBPPS6rOD0vL6L1vtMRWxU6mOQwK2/UjiANzeZNYlbE8RyFEkEXvSiq3oWm+MwRGLVob4y+fA\nH5S2UX5ufhpJ5cvdI+9fBu3JxigjwlFJtiQQWgZdRo1CQbYYaHQjxzycMLVSQE6JOcfYU94LIU5A\nUwT5TTAoTnC+JxulWJRvpj96KqNlJWaHG1Ahtt+bdSYEoS0CofPlHNxBWQbnzFAX3tnT/mYenXeA\nrt69v7ba3bOXdxxjDvh/AgP0cOf2SxqZGhzOTN4oaU++tHGD/ZVu8Kqu4Yp5zb8ZfAlyNkdHRjJN\ncCtrui6fCn+FtTM5x5quWiRDt7fUjbYh7In0xZUCiMnWjeEfn9pJlPf0GA2PXSeQqD8HYOS+NJCB\nVHXyiq5JUpxvZft8LWpkdbZfzZGkO6kVF1aN92WicGRMUgMJWVBphunFYS/+VEmoDKHBszfZ0OWx\n++9mzAJAUFqjNysjPCKk6hsLm/dpEOa0KtDDDpvNwPWSi/xX/B3y0jwzR1FrjP/lz8ar+crM+f9R\nen07LQf2OROO/mIQ+XdSdOWr1DSV7T8i+3Hz9S2ZEc10AlymMBKSZRnR0hiHA4CglfovnTplE5AJ\nZGZbMWLNQpuyWUfbgtspI6YfBZLOepJC+hf5M2vBpQZXjwH38+jTJKI7otrnOYWG6t6N4KEYf1eX\nIL58KbvMNkBgjjS2SZczbaB9qkMWatxSO9ADhEPs50Uj5zd38HZvlu3gJn1KBGCSRoWqNej2TdE0\nXvghOC1um1JVFDU7UP711bsaJZh36hLZchPOrplvkOyfBfLoJU0jlR561QncrLIqkDh+HKRX3CZp\n2GazvKjH4bflVhfpj0kgrxrKFNLcwrJ1Y6ql0LDQS0sKMHK9Tf1CWL4djp0uMwihRe0IYd6T09Xl\n/QDa6gsDep1NPv3aUkH6/IG21MuINGV5jMLWi8x3wlltqhgCQmXvSqHyt5IDDVrWVL3QStonFx7m\nnJwCEZHf64lSt7hxTcOw9V48EDLP4+TaNwoLUJwaeFfTv3ckVHH+NR2c5I6a+AbEqKAkuAxu/l/v\nofUDsTeEG6nSe9CgdMbS5kCkXqQRs9NGyNq/187I/367uoCgKFjQMKXOAWrB5pIhyWGIT0/ZUs2e\nutKYwlNxqeB1fOmmgg9CSnjWrXY04r7GKEefoEzuj2iZllmBdbnD/UpG3qYpf3PA0beA5gMPGcvF\ncdDLXs1OJwJgPQSVWCarOydXIwtbRmjK+ucsiz7DPXEnuH6VPKk+7pqs6dJnK3HaUnPL2/LFl8i3\nSEAumdaHma1MYyG3SLg7jLZnP3O+3MSUV1uCPLaJJqzWBpXSPEgsxKQv/UNnBBByo55IMuaYLEGg\n3qPUdgrBvQmMwlo4DFbGz1YEPPtfU6o1mGylE0tQPS7bSE5sM3XWoygIMAQxnGitxpDrEYU4AZAh\n+PmTWzrEo9762fvKRN8+usz9LEvKMHEkN2WvKPP3j33ZAH6kBK2Ow6VO1XYj2HDq4hSjPQvD3SPP\nS3JBbTNONrukiXUy46HnG1ZAnnGQguHrHfoXqKpwbpWPh3pihdFcoIpuN93Ghntvl8/Uko3jRA7v\npoFys/qfsbQ/4UCex375jeKLFB9OmWLXMJxX472o8FW3UvMT5U59f3yXnab9eHnMgWcqqbuAcqCv\nCUPpsrrseXWpZAaJTJqoLaZv4/XoYDfm5dLSHx7slE7FhjuK7+rsyVRYunDvN02OnD2oEGTt0VMi\n6mpYaYorouGLulqh0jgRAz639HJepEbnVJLMUui39XjjnNFfTvwx4J+R50h5wZKUgNt3h9b6fb0T\nc30pJWD5+Xp4aKZKk6C4l5BSDXROl/1DcU+NjP7ieVtcRPAlMiUJ+Af98oorgLqEDlfS0O+N4CQP\nTLnDBNbyUDp6Ezyv88eYedhjzIWuZNOtZ8hbu5gkKkKRl3CBcq6RrmjPfsltfohZGAK4PBQ3tFMc\n+V8qsTQVCbvMxu7E+HIDSBaByvCAHFuZYcZoQ4bLs5NJZXImOiybpCZ8LLgJ1tbvipFl+EK/AKBx\nN2gpnBHt7RepFV7165a24YW5ATpqNwS5M2JEOD+bH0KcAu8t2X0VaK/BVcbg+zpOKCicmaDlZVNu\nNaaAP3OyHATcotesbGqrDRjTT+om2NYRkCbwiuDTw+qk4k6KE3kUKYhdUbJmYvD0ypLFYZuv+Rvh\nyb9fzlnio4X26iYiMroRHxLbdwNfrm/4LvTMV48bXwtHAAQ16w0jrcsn+LDjb/IC7elnbMCxZWSf\nt5snRDRrswymXWZTNrzD8jCknbQiUKuMkJY1KLuum5pw30u6FSc0gyqiLHUrl/5SMO0sgRHkamSS\nQIldFfzniIIKJ+noXgkBwHV5UjR1BP7dKv3jvMmv0/0+EpyzhtZplR4Akv8LQbjI3wrlR3LCg7Dw\n/jZp0VEDDx8OcXnpNXVpRmcceW/1jjyGMEsOhDgabjMcB6cWcz0FcaKXouG1gCpdGUT2gTB5+HuC\n3cOcgDw06nuVMSeQOfkiwIAnzsYL90Kxs3HcoHQTBcdFweeUxTm/iCH3jl9fSq9QtlcypQIZwfbP\nLFllg3R2yDYGkMtmL9BwKc+FjsqCvacSS3VkXtJJWZL6xHcJJGtvVXtPJRHsvlumDm8dp2p0TGPw\nisHENGqigWE4HYZZT7JfiJ3Ogcqjn624frTNo5XBUTyiZQg7aNY4Vnq+INKmT1Y+GY3kIuGn7UT3\ne2EzeMB0X8opb3paDeCUt/IYsyQdaos7c09JBWzp5mO0gIgBsDQdOdv5QGSLcZCCyOf0nDIP7rjj\n4ihTQ9sEt6yYwLpeyaFSQTiXi890tj1FHeaKisit3LXZexWjlKR9ku3Xgp+2XRuZah1C08VucvLb\nl19t3oGzcXXo34M7/iaerIB5aA5EsCPH4ii8E39sn32oCrspYZ5MXx13Tm827SmknLcT7f+FKgGz\n4v6xOlvawEA1JB08y7Th3uBx28Wld3iH94X+PMIiTZY6mmjPs/V6au79xE4Erw1O0DPysWPrX0IP\n2BcJZPWsC3oBGHjfVUw3WBmqOXIx7uqv+3tMYwYdCTP0Cw9MT4g90vqozVwBZSuEA5gsGEHIau+h\nLMiRia23cQL21ucEq8Qh3xEuiIzAHzf5hO2Zu6T61mAm2jI5nRCZbe+6T2KkkpBuJ5foWeyf5JEh\nyl+MSeiI8XbgsdRpzJ/lc7Czyk4ol2PFkNt4M3698gektRaP4zSrJ2je4QRjxRdYmEoYME5N3/SS\nEnc3oQ8I8Z1fRvtxMw4XqgwmWepIYwBGPS/qZzvm8pZOpkdTEGaqTJ2sMdBV2hl5OgYCNlPbWBCo\nG6qQAxQ5B930QwYB/ruPP+FlUlWTw01qRqRhLDQifY8V6fdPr81wKtfjeyg0zD1EqCZcHf+9tHvO\nOJcSqpOD0nJyIahCZM0KkiBJ9i2ac0D0tsuKKI/kQ8VJtWkUn3v/1ZxSj+hYNBpwsAJf01qqWS2z\nL4jhyPbj9NdNtEOxX9wgieAhwHPOFjnBKSUTI9wak+i14zO1pCYAwxzSSBhZDVi3S8S2gGuhrj4L\nYAVVAbS+hjyyM9/2jI5YOc7KWI8vZVZqanuI452tQ8Vlf9yxgmA8U/ET/rLVkJWxlWpiRqJn7l7J\nEATcsGXQqPimbkGgD09pGGuzOWJJi6dKRJc7weJyxIM5pPW5Lf3Mc/41fU2C2X03qBuT0D7RNNdY\nv3vyaCJnwDuH4akfW6VZWc0EiSoXgTuxIz4taQWcqAZgtOQYuGGHzAR/awKzUX3rbKXc2qkAB4K2\ni065jfcMK6hhwAZSFMBpypSz7ZiNmcUWtskGGNmFYN/RZ/9d7UG+q9AmkQd0VLu5Ps/UIbmSCc9A\nh/JyeqqH4sOk2cPfAMRbwxXaCDiwnbWvxpowktBw4CGxQJ7xL1Kj9hybInCvP7tebUCzMflFj9YG\nHBztCvEYvabM7o/0G8fzzNndRaK5CdLRDCQ1NnJyANHN07BAWqahQMJplvgjInTnO8kIta8MU9WN\nAct7VFGlc/A5NbjTet7NLI2MxQi1nuKymcwLGBbXIGL+rckDV2Z+gkCH7pgUjMXqdREmgeggpZJW\ntZr1B00qcBtUys7PBSjpqKeQvyDl0vf788FdmjA6Jm5R2U4Lmd0IHGn4xPylAHBaFbb2y+QZugFb\n0ylWI3rSBcW3D4u3SSJeAWNcuV8bv7/ltvQUawU9EjjufYxgg+Jqb2NdFuVh7mkz4TWKwGTgD3cs\nyxJ/jWJ64AfrGQIQS9vlfz/6A7TEYl1Ji4eMIu69IVBAAI/rs0tRc76k0BGB7Qt/7xH3D3jpciKh\nLfusb6fxNeGLMQKg4xh9gMvz5eK+0AIawE4xUEz3SqlCvHtmzKBo4Jc112/nptJA6RUX3OvJff5e\nFvvMToeoL04gkZff5nUYwTzKRy9m/tPFhvoI4YOpO5vNTW7NHG3ddtSD6dxq4xaNdXPxKbKhIP77\nj1ESsJFcfZFP06IWlmcLtzbczDQn3jXh1TGyXhcQ0SxQMgzz4z27JN2MrXXuc3EqCtXqH+JNe5bl\n9O9IUK6Pw1YxF+dLjmJJr4wwWxtJ5D+ZLLob95ZWLsvuCK0HvBEF+7zFq6OmLGdN6Sv8nLivtRap\nfVOtbFP+WitWeYYqnAMpqqzO6WnURtV13OFnOz3ozpii8haM0G1ecWB9SC387zdcEEMyWqkosG1P\nyITsBffO4ANNZiigL8jMLSUys0Wit2KK89EFead1KYEuVfKKGXuH0SUJxyf13ETTbF528tutFRsI\ngYSSFGuTihStp3cKIKDGa1AgKNsYaX75X0eDpAhtxhj4xoX3Vcgyu3oQnuH2WDzX7Ym42g/yg/QB\nv0T4kIs9Mbk4JoVfPPXL5sfowzwlEEFP3bUgyWuwOrPt4JLBEyCQoO5uTKh1Pqp5P8+0eVSIp+Ze\nhmLAZ/wM/eUnwkeq/NmRUV71zhOTx6Pc6WA2ugb8bpUtFKackVQ9NqatdKN0pom1aS9txdFwqCkP\nxT3t/1a0MHNf0kXb1LPpOMhkZv9uwfg/+gx/F1yqHlVOe6AWWRUweJVqqwiHpn0TxgxNGNkYpeIe\nkkdrFPzq0hlKgM+Hr4HjvVvt/zwoJiUC2/xbm8waFX/P1R5xT+dZZFEWsyLJaQzGVgEZREN1n4Fk\nsnOpSpM14mTEJkvSTPSYI4lGE7etATmQrEK8a7OaTRaSposDoIoeCLc6EmRqbwmD8IwhMLVebJhY\nPNOuL0Pcem2Fw/Cy0yMYqsCWvFn1M+sTHT2+y77he78tfz7zRA+ijzMCaQoU6Pc5qYKoNDHK2ff3\nieJt2jUeiKbjU6Fzzykae3nUT2KMP04OVhFM37WPGmAptGMoTbh6WMRPsJNh488uQgZw23PKaCXh\n/hlzltRWzeWYnU/oMzbWQvcnt1RcqKWOwk7t/BJsV0zb8yuhOr8NeeTqqZmXSuckHvFb5J0HO+8J\na3nh0UX5XH0yBfIsrbjio616E8HQ4fYfVs4LOftn6LdNQ0wrX7wOw5cun2NRNsJkFCp89ZkCnutF\nWWfCcT8X8PjoPQlBGWraPK6RzDvVJhtYIZoj8IHiwE2tpVneePFcqISBlZIl38Xu0CP1A3CmyMcq\nPeNxKC06bTHcWnHVd8+kjGoNjugX9TP3BxZ+hN5k6+kmoEWAN6n1y6bVthFXXCaKtvU/rI1PWFyQ\nCwXDNash/YOt8afMmGm2z8niRl08td41iBVzIsmXq4JAglvgPR7gwUqAAEVoKF9Fb+hpwOsv5qv0\nfZ4TbMhuf4Hxiw0RkBN+syqmxsGBO3IuFY6tYr9XpwvXaEIDNepj06jh7KTJx26WNgGdMzF5yHxY\nIuszxtKiejxAnTe379isIJT4Pr1PA42tYrstLs7zj2JegW3d8dOSB8oHanUE2lAyAkQaYhwDTI3N\nhLUqmF8ShsQAcgG8dIjMGM0AE3KGGzTk92SQtygIsa+nU+vHunemxBI4C2MgwgV+NBpaoZeQHoAc\n3cwE0B3lB0uPLnh6KJ7lVyPxe7+6FOf62NfZzChn/z1OE8noa7U9ebCA9lK8Yu07/yZzXi3lSl4M\nwa7wlrXuMRJDN3Fzf0xjUZT4kX/or5g8G6knQc2417bKzfNsF7si1in3KUa4W+V8Q5P4Hy0XTfD8\nHsPGvfWvuEjG9qpjgjbQvldQMEk6mSFb0dzQgxjZELolERpatlUbXXPs7PD95/8aknLvUsjlKYyA\nf/CMnSQX0QkR35tHkD3W0iLJSr4DtezZ6ct8K6krP4uH2Yn50KZno8bmJQaiJfL0uS+HKpgDf0Uy\njZPjdrDr+x80cxIpIe1+VSiEXnV2uq5BOz4A8959xITYm8UyXABbzPXj1Swi2yK8iKzpIw/Ff+Ey\nmLXpZAln6/PcXz1kRbu+Xb8CgO7kVivOJuQkyIEm1odTPohJuWxVsApdBEB3kDeOzPmWVfQ7Mr3k\nThnBBPycGuAGhj3uHV2fSvtMwh/lK/MBXqfteUvcuUBgPMuPttG6iL1bjhjsg4MV27mhtZ414oOq\n4rPAjiglxL5RdbMgHx1i0dXjTYOmN3mabk3ph77DbmyK6sYfzxTDll4wFlWJOEAnH77l0nk1YfM1\nJ8N8xyFAA3CmO2ie2gauaj9yJPZsLwXoiwx+4Q8dRodg8WmXsSkOWCW1AIYLbnG6EfJCJ0xaBK0C\nkkvdCHkxqTIS/0LKHEQ1D1kiqCW+gS4bgnbw+2Wi3Tt8icZziZFrG9AtWZNjJXbtPHaqxLFpJGCx\n1BdDrlhIKm/OMW7LSxMkYPHHkkY0IPiI22Xq4MPjW3SjKhWRRKchnydwLympY8Z8iGaIxMiwcPGk\ncSWFL9I+ULM9CBqyS0eRie9cgAo+LApBSL7IhaiRV1h1Bnhp2gtPDwlEIMq9UQ6s6n/XAu2CbIX0\nI0NEkXJh1Vfj9teC6lT6AsWykaz4hcXjpfLo0UW1o7bP4vo5rlfZqASVhmMTchjLD4BrnYxC0Mb2\nBnw9KhGg2F8vdHO1LuwAdiJCNwooix63G7Gcuxl/bT38qV3XMD2Etx0dUv/sNw/o0I6+aDtZ0fVD\njgHj7pbgyaBBAqa7O+liSyj0wrXWzE0NyEaoZsNmxfyusrQ0ncyzwHUogt8QEGszsxFcC+gpc2FK\nHzD3OJIKby3G1xh5KMDsOYrqyhT04Ey1lNcTL7NCtqt/xqUyt+lkUVwCFUwutOxoVOY1WEURmFkf\nSDufX6samDjBIG+hrp87h6klEHWlSXM07u5sobZYXzwyUS6Xphm+Ac9Vudc2coznXsrf3C01VN7K\nTlX/J5VX5eyhimCUAMbuCUU9myorYQ+99yVOoGkEshpvvbr/edOTm7CSo9E4SxsiHTYtBTJ+yJtA\nJi+AQPm1FDr0+icU+neI0jpOrVZ99BKBhGNyo+skAX7AMh35uGEDJb58WBM6NKLoQiKNqaDujSD/\n4C4ZBsszLoB9R9OwPJBWg/kNvl+W626JBVkmOZ0wy2KWFiho3XTu4h/bms20QpLDxWgpxWke8/0R\nxpt9fms/SDbYDu+y1qKcv1KGn/ltK2ax7PKg90v68PF18G4izswKaXL3aQvWGBbKWzrzt0O6Srww\nOW7lEyknLYUBXzCc3UOYDIB/HZLizRak3xaeyK5zQH7efb9qU7naw4VNWso0HkmL7GBCBBA2wQPt\n8UONZ8rNQX3rNMdr9bI7d4QbH8Wgo2AoDATIm+fnY7RTau9hFg5u+SRCHG6jbu0D4Eog1HOIvSt6\ndJeTDuCDhBh+DbUJYgb4X9XHZOVDMuoubzvFeyJ2WKpvF7NQU0tRBKnV/d3wCZtfCm0GiFIFTF+J\n2Oj8ZmHpk/+JdSe7tQ7BYAmRBwcEJrih+muViCQBeueXDaqsTnl1w7gOgnYeAcftRxvBHzhoR9Ka\nh8w5YS73tphvmJKbRTZUYq9AsUZ/lyzyQjSCIJUV9xlEgP5ORmQNOF/GXwjgtDJlDxA9Rx9B6XLh\nRv3JfQbIYCpLYje3OkDktkgZQR/CkjMdlP8k0JQCVzM83l9XiclNArDTchR9sVTJaBw+LrB4/Z7t\ngbuhDmbmMXNshgOICHxp3AFRYCmvWEmHRsVlJkktwqONVUqj6lQ3AuJwxln1zYDaF0ldlicyuhdC\nrsvYE1cXKnuY9tIMDtPuIGKbNSIDtCVcrXp9igJBGE35/6ac4ULFxFxv4CaI+EYe53Cz+9cSlVmy\nIuphGp2CTM+3uDt3Cj1oGpvY3sJIKggef2vPjCxT9QjNpUhiu6EP0WwYw0F4G7uJkEpCGqguOQfU\nI5iF4gd9BEN2nABt3pWVKvowBkT2PI9AR0GuBFNKnDelpMxgJmmf5VDp72K2JKT6kh2F2xYm7etv\nhFTtASdLNdg3JSRIFTiJM6oWO00gSf1RX4DBDRB2zUmqrwl03JS4VUlNbmADB/xh96i8HaVFqcRF\nC+sG8XqQA94kX0pizyXoRsrAVjk7dP1vMhg4L05zseMMSOZVD8Fm1hvYY8+6d7BdNelc8yN3oId9\nU+9si5NnMZopLEX4BxTcHt99yJz+i3HaF3KQ9LaOQDkpmxWxPuLNCn+HfOM+Ok/tGUg3xQZvXru1\n8ua90lys5DTnwmiO72TCBnmYlgoNki9txQ+S+1PjuRPLhTtVPrIL/iMSYAmzvi1ByOGOLeQ/8I7s\nI05yO65pJNSMeb/B0vRiRZEIYoVGSCcBoWdAGYHgXqIBsXFnNJomvHDczHdXv67ssx+Q3HPJJ/bE\nnfxWOLsIxr+Hj+4pagzJBkEjn6FId+/BXozmmIaQO5hMJEDPNu4exDc8rIuopKy8ef6r80ky9W0E\nyBx4xRw1K5aK3asxS9GplnTQobBcWsaSLv9Ot9HcoCXs2vFH2wmAcxRV0PnwVgId+Bw9XjeoIhkj\nxln4/EqehqSNt4BpoWyMKPcvhiONg1pKxpZY9M9I/zR0bfKtiVaFPMvWELR2gOynYYAH6dqVxeZt\nhks72UWvzRxvR8f7V7u0OgvJ4diejuLLDVscdltQr+vY1QQthnzFlSFnvrDrgsOrPe9zyBpwEjOO\nEAkhp8c6CghDs6SPyo+HwFBJSxSRR6L8IVFin/FGJEW+kYdat0O/F6x6edpIYTV10vYANb66gu9S\nCuLbRwwz1OpKquqcOoXXioc/HpJu16+QhCY75YKdx537X6AcLxvp17Q2vCt+xl1DsEQJuAbpsUPl\nwGYT+qXydYs13PtzWV4168UFej3pQReAfLB6tk1mtzqaFSe8ktHtJj8vrdYJmU/qDCpEdmE4o1O2\nd/VDMwsHfxsgUu9NsZLBRtkQQrg2U3GySROPBxTj1AJzirUHrNDiGCYTZw/RZAh3BSNplKZ9rCXw\nRXjJ9WxpibqeKaR5HFZQbDAoEX34ZET9ONx079lDd4AYrb0X+cU3dbphqeATV1cRK+pf54gLr1cB\naIJEj8dLCohF9WgfRFeDGPx9smlv39WDD2t1IDyGVvkA3Kk5wE/2SePlpX+Wa9cn0dLYp3e2wc2J\nIHb3u+URLgxb+ZeHveVDKp39iKZdeh+csGPOqJqF+KhTgR99X65OSBN7FK2HzdpQUCkPDIsDx36o\nOulc7vqxBIUyUGqUaIlK+MG5+P2pUN14djL6O5gyjcw0+0B3fq2oO+i0EDGltvpap7LDw/MKPsVj\nnbrt6jVDiHe3EiOlssVz7ctl3pzgNL3LWoG82e/pweD1lCYaZmaqlWz6Lv/5107Ee05w+/Grnwik\nHca0gSSRnPO+RL0Qw2LiTMO5YphtFRvC76KelIooyv2iUEObprboOZfXio0bNe72fItChIyvAiH9\nqDrtfXA+VyMRj26J24FmBOwJxNZ3CBJpbczRZDvSC8I6Fl8mCAxrFsFZWHPTNfEYvSdTPPoxJqgJ\nIUjSa3RdbcbaSJJGiS0gOowr8xn1/tfXNF//EnZxxqZBE9M3mA4xIiKairCcQOxzT0yGB9PGyrG6\nyF6FN3lJn2+97aUaVIR9Uq5g35Qg0AetAgD0VbG1uC+TK+i3ErKWY72hwzKdH7vbVdDyld4mSe07\nnMtAXyGAdzXX65aIH9L0h5BRQeAgzWZ5juRz1v9pfM5pVOMAhaKbU+uCUww1iteBY9qFqHIfZ8QB\nqu6uzPkUAn2umhi+xGxD9dKvP93Z+BbHtpgj8wCjq38SevaUpKnceaHHvnKfzYsqwaDY1YqVCwx4\npxXn5SLaYLN39cfx1ECC7yUO3ZLXctxz1swHynm+xj9Mqj8FL0z+Yl0tejvWVKZXUj7lXXpwJoY8\nXOYBCst6yZLxkGTCqTUzzGlGhc/bmbcPSYcG0U5bM77y8RDkM5lUMo3OL4QO38Nz3bkPY9H+2kzc\nzwc10I793m617pwaADgotXHAeRXm12HMB5OmzPZ8B6eEyyPwxbpsEsRLBBXKBWmC0w9+rtRF0sE9\nToi3gBplDamYaYoNRDp4Hor51OfAA4fZsPbUryNF7u5/KzTMUsVeSYHIHwLJnpSm7CFEI/+EkZhC\ne72wNuD0wP27Bk9+IK0LrJYZeXowobd7eIxT19J9qkr+uMW+ef1MYY0HsjSdpLv4Ty/oOdEHhAp2\nypRD911MgvGzalg5zu3s9wRTPM1/To3ExuVj0vp7cPMrW8lQpbBdTz/eFY81Uay7RZKZHKwH9pVA\n1/IP9/hMHVfdi9WRHYGjSX1xcUbgrBUcGfS7AZeLipHFfKYhL2rXQBIkXy4bln7PWv991tynPOTF\nJWj7mpV4hX0PdbmCXrJUNQOOluBCG3o/PYLrmoxFQ/BYHyIKTwP0SvgOwSVNhDib011J0PZ6xWg7\nyOAoBmcN+yKeyNMEPIbQ7gnVk8alnUi/ton6SVRdYAyJAxegAxqLubVKGHGvbkuL/7PgL1Fjqcwd\nDGhEhvvIJWlvaJUSVNPiakDxsq1SyoCfm3Stx2mFa35jgOCcTknuq51vMWgECAlV2wk5QeAkAMIu\nnNYq6BipX5MIVrZCwy1uEpJV4HJv+X1qBDTfqKmtQe8GDxiMYN1LRgZRFgu1R+IglmquR97e3S1W\n5LGqDEFt6qTMg2/EC1Si2uSuFLSsu3xYNFOKLhEx4fme1S22hAv8jmCFUF2CsXmUYyvkWKGfqvCa\nnBZ60r508d8//NYMFGevyYXN7SVZrIgkJRR1MLPIlL69gxs8VVj/ioyj4tCzlSJ2bgo/aWuzHg9s\n62tYwr8QqpfE881U+GTAZcDS/GvIU/pJSEfolvBGdEYjEjf8DbcNjb+3rAe3/c7U9DfEENxBqnz3\n4X1EmqWV9dO0EQF9oUHOmJvtE9156KgOBQFqfOWLgtCOUSa+JEPkU1WI/bUlQo6eXJxsC9GCY62W\nrZaP/Xyf6ksY58hnqc9QrRRfL47ROJfuFKqxc8/Ifa5LhwX/0oDVOKVS+KAt9EMpsEER9B9IaMeM\nqH3VcgBhnZQ2rzTDD4VCJMEhFpthnIn+kTUHCrkjys0G9zKC750FJyOZDrpeHDGj/HsPqnBptqO1\nOilfL5dpim4aZkhM62invXIildkyDgb7oNBGL80SiGLStfK4Pm47bRlFRdJsFNLT1gZNiTeTSYfz\nZqrL0/pl//yK7hxMtu1MO2CoM4CK1rrqtvPoKSKNkW61p7c++ZYsml1FLNTpSuxNp1E5g1fpm22e\n0thRXur3wf1sZou1K8Vjxr0g4rUQwWoM1gyU2AmTCpmXQzOekB7hrvfQpX063pF5AIBKbJ8y2/gh\n+lfZ7cQF3pGPsGdJxejBylnYMlb8alEVpks+1+SGW4bYOpeRm274NiB5BxHuTVsSoKixNvlKVuma\nKdPQRtj59Zvraz+Uw11FNMg4m/qcbM0xF6IpFvXziqsNYEy/76FvF7caCIppqh0P/fI3VFKpXbzw\nQkmY6RXaqqJMJfk6lRAaeyZQpW4uz/HPuW09OjMFRIn4xSvIUqHhfNpc7/Y6O6Y77MVYM2mz4uxQ\n/S6aBqM9XKZg8obNa44P8sSNI50nEWtgv0G1fhki4QQcywkTudqWXQA7dJYAWT4QdbBK/CjvxJ9R\nmBFTMhon+ly8tzg0Fh2aA5D0Uk6Nqfx5GU5tf+dseB2GfbIwuXiZ4EqdRfwJACBZ+cgut4hXXDcb\nn9ZQyHrqcTzApebBohfpGAh+dH6X0Y406G129v1ntQEnpWxroGhvudoWhEe1RZrh+CUwmf526u4w\nM3AGVzQpqgQbSk3qspE8/pdNdvnL6YJHc58FOzuXUiitscnFHgLgQVfXbQYz/6tWWGszrxZhmUga\nUUC/KMKSucMuX79MBRJUU257YbwtQPr+/NRhcwWorjTiFlnpPxufcYEsCJvaFbd7zzziNNnlM8AZ\njjf+4vW5m5LkC0cM/ors2e57Lzclw2rlLv6cQgmTJdYZZnHzmydFxmGtgu+iJp2qQyuKWONF72Vn\ngGHPOMdn6rwPNYOeP966Wsul0uR2bV1mImRsZRIXC8aS6QZ3Hj/POvxRgnIcB+zpkO8/khafmwSF\nuha64tQ+uFwsXXuLZFPVlX4ZRI1gO/m3Oy0Ee2wLiPWEYUK8g6eyYXVK6bjoQ5w0SxyS52sUOHb4\n04sqVbAUgU0sv4KR2yinPwQDFGAo9/qd8GF+exxOyB/AXZd9bQIgyqKO2MgQwR2O1laVaT7BuHY7\nG1QjXt/bZg/BJBCoOgczjj+vpeoM7LWGJZsIgtR4z7SowKxPxhpTTuOL/SbYggWdpPCYHkhEhnTl\noq3Bvj5CMwHpnbEszIFO6hyQkjcOmxbquCuSGL5L4WtA7zX4VXzRhEv+ybbEMRWBSODmmkRe4rE3\nQmTBDkxsb+4m9aJVSULUFGUwGmHsm5VV7cmImO160DN6wZotG/AUCfDovDqRN6wn4pvkXHbiUsEd\n+d9HTRjOHOtOR61GFmjt9kSYyS7PTNT66S04BQisRky9SfICVD+QLXWjk8ugkqBODrOYLDuTPmm7\nJER3/t/ZoIBZDWmBF57BFYy+MA4dWJFjPfY+xQFDDvv6ll8WSAaZuo6X0ECAwVVHXUro78VVVQ11\nVjxgbP+P4OhLKjZAf+yCpGksgp9jJR2ilOsAMartaCBe13WntHuXBaon/A6e4bx4KUAsVE2DeCeK\nxgUqpBYAON9N5l7zMgdHR873vDs1yfcJ6q7aUrSpwAbtfQeuyB5h2xeFTyKC4BI1ltM5CtYLfc/d\n/bqJC7G5MZPBLOH3zYJtriASBMR4WOPQrJ9NWxS+CI7YAcCADObr8xRRlO2U/fhU3mifJhnXdDwM\nMsQ6l8T+Le7naI+zFz83RvDyXG8ENktHT8n/5rwrlhtljWJAteVeG/AF2cf6Xj4wiVxKi8QcH93Q\ncQM+jBeUFkA9hgL11lJqdii8uKfBgnknET6qTksr3HGFBz1zmJKrBDZdYpj0+lYNnwisv1vuFkbT\ne/GgP94qjBOpVSaHbaIamt+WPgJPh3i9+ixjAdTshsQxR955LNTQ6//8jSfQLW57WFYkPWuzVPmm\nty6/QJMaylKZCZmXhrIF6EiRwgTRUaWd8NnMuWq9xlmx1/Zb/GazRGtdZrkxl9ExBo8CVgHYJvd2\n5mGvtaydfns0t2T6gOn2bK+janniiGAcCvOuKSWJ080Y3zFDsShJ/GRXIRggSvHJL2B0xn6vxWi+\n7CBj9dirrssKbDygkQfZjZnrIUb3pGVubgrcJWdc3iLDSK6wHP/sd5PFUdmQCFY6FtbOzzGCiXWP\n8e7Ka9skPDxi+/ZrBkn+oEE8816XGtRA/4PHNUdLFiyjO3qqGn1tOp3pvQWHmxPuYRJfeRGESfEX\nVxPp5bySGY11bTKgydUsMfyR/g/xIX/EvZqgs3ewdUiwlKsrvL5L/r2rdVd7jWKhi1vjmrILsEVb\nNUdixIk2ctGVgISfVKZ5rDuaSnf9WqaLlbJ9TK2LlB1nLf8YYgPe6DsCy4Ge2QA9nQQDxvPrqFiV\nm0VEJBzjvX4gG7CmYA/XY9V8LkiSWiNRVXvdRdTrumW1wRp+36b84SsRRMdPRTsGzU4/UEFnjFuR\nOjbcf7k2J5Fp9dDw7vgg1YMCS6lWvhQu5A3xp23Xn7iRaky7x7MLQWOZSqcCeq271FVf7R3FI8x8\nlnipAltY/zLmS8LRUDhR1lJkbIAnKc6Pwi15/DDDVVtMdIG83II0ytPQp9HEC79bCC/reO/tt3Il\nu4fkAFaWd7cpUr38E245dqH3PDLGtrVzF+h9GvJ93yUtAiGuXMTJ0zFXqcx9oWxl57KHNlu+cfQS\n6WZB9qU7SiGH1Daf48S6w6XqVeKVxUonduYooQR/gzmhzedQtSXMdLHckkGKBLVkVzbGdqbf5uRL\nBVZxWM1010UuEN9EB0RP0tteAuGUqhqKJzjuA3oqeDGnk0bdzydMy0L9T8MRzy7HJngPXoPASHoo\n6y8hMwYHvbP3jOd4YSlQ8MEpqMNBvPo/E8aE0zmWkZAa0hyyoGDeNTpMk6cj+5vIsHYR5nNQSUEi\nSF1ndu5UMpGP5vaXnGnzezmn115poTZovBmfnO1WaBCya2Sre/Q+em1+5P5GSv30sxW7GLuJrhlj\nAigWUndqFKae08ljiCJrz2iylzMS/cKEY9sv/xmq4+dNFjgZ5bk7jBRhizV5RHEIbrxolQ304AXt\nfhbi53XbI6/K1f+7XGvsXs84Ak+wfljy6VFPXajp6MaQxVesa6Zm5vqeQKRYjHJgrZQw5qshMTVz\nftpszcOOZIberlVsggiyACplUxY3mgGOuJLUiCYKsK+NkS+DRf/G3WIR4g5zVBZLbkzrWsjmg9P+\n2NJnz0TgfEypRJidjVFb5uSCvA3TgKl8r4ig/sUiX74Q9LaxOB6Sr+qChDLmAwWfyC9NCFZt/FFQ\nOHMSYj0mmIHxp78H0u0JD8YvTtaExAgzc7vs3my+nW4hogn7nScCXRxs5QadSbuuZxj56FXezV28\nz2h5QMxrTI/l4AQ28NlaHooEZScD5WDpEQRxYIME6O1+ByUJO3UC29+UKTW3uWIeTYx2ToFa6Io8\nYs8A/7oMGMiZHwC2DGnWa5t1S868X2yruJjx0ELTh0VnOZIIaAxVIRWN+cHGQaDOGPihckpUCwff\njsghlSQVGkLeFFoCxmz/DQCZXJVb4JhplG4o9+WrJV9c5w7NtwE2Lcwt0FhEKpnBJMfN6RHweEtR\nPPixFGRe0/q5fiKHA3wsWv5W5nTqdxQpfZ2eyiN8xPJ8qX4lg5UQZsQIggIhiwbu/K0JAOAzSuyo\nTKAHTbBT6O6Co74si81hSV0PLuEdile06Zbv68sACqmnK6vtMejasRoS2ALUSsMJjxAktZTX8900\nV0JXNuuOMbu+z3CrwDNbLnUvh4o/bkqqHKZZvPVWBaL4Nwdg5s0V1y8WVhNOfHo/i1SLXAtm7dz5\nidnV5CIdl6uvIC53wvANRfEyNsYr0TbQppWeleHyiHqhP1dbjBYP/5GXtpgPapY4njAhOK1r5FVC\nWPJ14ahgDNxZG2rkW+MKJyw+E0R8rVHTzMrCAZXG/80gyO0VHff1PTpeQrFnrGqZjf9N02XgEFWL\nvuHUpqBmwpG4+bVU/cH828wqhLGSt2lEGHaIaRUe1cvWloOda3rdLIC+r3YuMzFJKNjF0CsVBZKV\nbIMblTP9jViEkGUoFJF6iaat7t8waskwHtpb680uATQBROQ6eknG6+Us9o5A5g5tbKolHHqDtqUx\nV4PqCdE/o6Jw3vyfy1Xg7Ah5d3vuWUNFpkguU0af/51I/cuMPM3VOJfr3m25x3x4XmNbHIkf3ja1\nwTgIe8gQINkNXbp8QZefFQKgS6CAZ9KdK3FSImwePseJCMTfg6CNzI5TxlUNsP5ZBJaeJfK+WwQ5\nf1/IJbXzrZlbfC2AiIWj7PYdN/Kw1hKe0FTU1RNyolT1QO4y3McYyzQkZRSmN4hBo6wxLSC5HuOy\n7t4XTNbYU3SGtoeFXw7hn5IRYeyq86lLks5dZSssWWR6H5OHlcM4zEFc53U4mQlp1Dzpp5yJFkOL\n9zIMrVBbUEvQQSKgqNf+mqRntL4gpoE18V4nzo/x7EDYiha36edl7AJP1FX9t1w1RGDwHfK8Uytd\nmf4foSmFjXMJtCj21CzqUo/SjG6+XtLcOkrivRIcLAoME7fVEn3/XQ1oFTZ/s2+6KstqJjaCoHdg\ngmkEE6/wHGjQsTdYQjRkjsCzn9ctx76RPkBuWgt5E6EmeQNb8Lf4l4igjjRWrFtLApd9TaorftUI\nAQ/YyOs6mFOKZlq7mOAxZUpz26bWFyRN5P0WFx/h0Vpjr86Omn9Rss9nMqZeBhLaPhhKXXlElhoH\nMIWW6f+4Lxs4heYjFF/eB7OAmFyoifROc3X7Nw2jVb8DpQUSMWy5cbKywMt8EwkB0HpZo5zuO7qS\nnuVeZIVSjrXftQh2lPC/t7PPX0xILkxWGj2Gig2ojdVRCIMSWv8gAlcgqjwHHneNf3QCjb5yAnDM\nEJSY4zCckEqVgIUSNpYn3kTJYk04lNCge3LpTSHbWkSH0tskvVSFNGxkuJdFtInodqM+BLmpwWJU\n9opTL5JZYxVfxJEqV267Biyzhc+fY9QK3SDI3i8HWChndh/2ELlYNcddvnWNCwZExseTFo1uqjhJ\nU9/FD8INJMqZNXWyBKeNsjzw6lb908YwxaKkZPfEC138yfuyBnWNW0jh3DDwBqm8hEzLgVLcS74L\nPY4xpg0hi60eCPTwo9LFLHBk+4+h1YtbezKYbbbqjvBiz+6ssJUJNokU5oRJjN/R7u4BAitOMUBR\ns7+2SoEhW11k/7WoGHSV3E6/M4ikeQS9wNUCqSo9uco/N0mBrDPA6tqBAih+Vl0Q4W1q7suTld6/\n856x0etS3gBny2doKouibRIIIj8exU2Wgs0I2/FQz7MocDiCh5M1UE71Z0zuygjBgDwOUxDTZpKR\nv/xXAFErhDA7BqqobZO0l+XNYmW3ew8JBSkZ3S4nq8s4Rjxo9I7trlb3vRDBb+W6B82kcFvzspsq\n3kSY9kDyc4az7ZWHd8BDhlTptmjD+6BV0v+ugW/lBWDEirWRhmzPxXoozs1XF7X8BqeFSg5b1YUX\nbgaQfl/HbR6Ip/GasKAiK0ASSMrU2arqOPfKgc0TipjX0bQKM0uR561Ao7+ShOnOhVRqftUai9KM\nFN5S32Dn/huZYNR1WTp4Z70yDkkOsq6mPlGPufNof+mlKKKAzYq8dahfx1eFVb9/iRuAY3WER6L+\nYeVHR07Zxrzir9pzm7LiSr/uKkCiXUayZJZQZSkCiwua4kHhqwQs3cTi2mbyxSq4CtpPkhosbqqT\n4wraFGGm7j0llIFZ3gNnkcJ9nTY9m8KLVZIQ9elep3py9/cQabl+QtRmplXlko3PpGXHQt+V9J8n\nuF0cMSmH2eImRdcWMXdxsL7bYcGFGi3F0Me5x+1pMEJpyC0+036+cl3lgk0pk4Us9fM4BRsbi7Gx\n0/rzhDZ5YOYlk24Tm7dM4uQmCPdJUx+TggbPfDAGN9WLjJJxs01elMV+teR1Jfx36lQY2AnYs4EU\nXqN2ZKXsH6hOP63tPVnYNw9Ro6zMZ0rw3w4OV55BqQ8xUypQP6EtVE/BqWDjpbqsPG1WXdUCbvfe\nGkYKrjOcqwQ3GasBoOOcZe/328GFidi4mME8DlQ/Y0DyPvPzf7sO2Vkcoze93Nft1MxiyIkIwedp\nWtxFw3Rcx1O5Npg6Xq0O8n4+UPGJv6D5DtsMrbtxOgetRd/6c3En3rGOlYmlCOijeKjVJp0U2i3a\ngt5tSUd5RXlMyC7Zh5tiJq+r6BZXyHQ42pdvRJXdpswDTXuVwTJQRZpxxttX87t9X+KhL5N3378D\nZpcTWRaodpVOJlsIqM3vT7Gqh5cB4gZYOcI3eIa3CBCGjn40m/IykE2P5QWrVOEo7ZDuniUDrpVY\nYSSZVzPMhut13IZahcT0Hneou7w8B2OjGoE4ycBuO3gRb8lzyWWdE8GKpvCkF4I+bPBvvqltsfYG\nKWn7rBXJXHhF78Leobclf436dwL5Hu+xk3aWFZMtKFNCV+gYuahsJhFRRGWMkcHD+EOHH0zyPAfw\nXWcD1T4hf32OCxElfnaLhgCNS9j7D+81NZrNE59dcAGrIz9LBlGRgwzi4bMYKCUghfnKEpg4a2LP\nEazYkwfd7dkQm3Q97KlaA7siVnU3F2XiET1GiDicE+YBK/gssq8EwIWfQJ3CRxX/BbwASM53DcpP\nSblWFwx4n85HVxQNTNELwHub0rPfsOF8MsMwYRNQE3fjUe+1Te1rteBBrfAz2ZbZHE06yPyZb/yP\nUU3biFOnqhRcYnNtDwZ7YpCqdfTvey0pX3Pc0O1C2ZX/TxlBzVrCL0r4mDVh2/cPgjqvxWaQNmGJ\nEYDFQ1eUIMZQ63RjITHu91SwSBmg8hx6KEvCHVTMnPn/RGgThghn/IOclL0JfiRedoYaae88M1Z6\nlQof5PuPGTlIp7ZtTPf/Qgtl/mSf5HN3cPh6xMQ7Pd/3mJ4aVJsMN+YVhdR9D7V3NB9/MM9fQ0at\nz+x1kZjJbV51kOv45N+sJRH6O4H3WVbDqqTmisGUaRpNNdus6usUiueWfYHoMsOepSbVrNsdt9zt\ntwAkKByDTYnV9jxTlOsE3AFQVwnggwECnCtx2LBXfTrtEHeMHN807NrzkCSzMHU1tefyDxy+E7Ui\no+vYzoimF58zEcgbf3P1ETgN1s9FC3dSCotc8EIz2/VtedAxy374/HUKLCCKZ3xQSqmk/lVx5NYh\nG75UGypaaO71r+omYhRHuPzlzagJvihlTJ2fWajEr4m472cKQyLXCtZnodm+Q0WwUGqkVUKViiWr\nW1vKOr1/0iT5s1czkSY1B0b42ouTNP0lDsxzeGchBazBaNZ6cInzmuv1Vm1BGtzUzsIHVWYx2Un/\n9YAQAFc8vGTW4I+1DpQynb5yY4ll8cT4x6NlX+khZYe3rLDmsGNb7K5KdOvkA1DqNbFF2Q9U8NkE\nBvcVCMz96WyU50OXVB/S9TJY4hfGRn5mSWVoNgLAUyWmx/vIh+b7V9ePvkHSxMREw/ZtlWPz1SrE\nnSfBco2T7L0RFAfLQfI5AbXfDjSHiYUIAMAIP8qS23f31VCiU93zp3qrwUh818z4Sd5oyv+4SMP9\nOJOlxwJKe/6yZ+Tw7KVV7f3FD57I/Hd/GLEoCqvdEmehxPuuaWw7mck/6+2e3sanCANHr2Lro22S\nFg3zuWTL39+oRp/kg27zvdr8EYDUaJ/5X9P1xbHztv7L/52VeJ3d6FF/r/nusfWlKd0VXoeGE83S\nFbMs6dmdoTqHEzeSA0dCedPwiW0ath+wvqoLd+IjFbTEgSsy6Z/BfoCj9R/C96Fmahhs5GX5TmNH\nNxOrXUqKTt5pPn5+rcUGoh6nXkUFvIXb2pw7537yy1d0+RUkABhasEgEZeTcwAPr0a06hA0JmTIv\nu/kXdo2VJzWNzPULXjAHf3hXXQRHtrlo8GF7sylH+558q/ivCIPpFVgNToR/0oYnIR0b6zS8U/VT\n7VBIrDloRaI7xs4YKroVYvl2e5fJ2aneTtYfcmW5C23bMsQB7IF/zQVZDjEQdkc2DWgNY2SXdbT8\naBCA6tKWWMPuPw0mtJqnOc273PqPIkCpSJVer5KI3QI5g3jXUCAWI5MdHE3kIlmFl548++pHUjky\n+FGW0oKpup42QvRmw/sTTuzIVRwKFtlqth0EGhqTJQ96YlX9hmFp1Qz1hZOhN1gFHQksJiHgVWIH\n/lD8gwKrf0OrRbZXx3KqjvznfPQ40slqrXB+rUntroaH0n3zWdSaS/ZRaLBAkWc7ZmkPbVjYeVVG\nW1rrcNLFRYcqRR6HioZIzA0tGOoPOI9MB0rEZ1VfGlZMG2s5fL/xaxRRZ1lcVm8yMZ5J7qizo+0b\nD8jyswWoiGojFgKO0VEcBRoikci/usTH8if8/RmM2Xd36uRbV+1JL6p/R73opGtkAgEiUqjrXTbf\nbeOcezT6Xk3/pReIeXXbRsLoNNxMz4FuFbo3MNX9JKRKl1uvaNBoJ9cX7PZzeW1K0/gGBsuPSjOK\nK0eIFGsXjzvI2enm/rJx2dKp8646oOB2IfJVne+DPhx6QCMSSEWbt7yYdk+dOMrIq7vCu2jkwXGE\nEfQvCPkG5C6hXddVZRoh2vNXV3sBgnWMFO/GqpdCZzEeILO9CBgzUSnyxcurlbg6MioORBTrR2dE\nUcAdl2igI3Eq3r/t870+uptqm/riTF2q7nBn/5aZSidgGIQ2WI0AFLzGTiWPPVLui7xrthzYnqUM\nepM/jILZJwCIFSQNvEv98+ILhlItUWOLEGV5EHWjsoviR04ktIsPZ11JgymGFHkUYSP26RG9lIaM\nyzpRmbasNzoPDZ7jhIOzX6LY4WWry2bD1Io2k+prkmelMpgH9hBjIXMuvsmkinNVK7PgQ828ioRG\nedL5sIEp/nVXmvmDuvzRwKRZqJhBdIRIXbRGl5qNP6fXQxUkCyje+p/HD4F5UHj+NF8QM0bOFY3q\nM1HtqB6YZlJK6zI94hkBCiP4ewsYHxygKbnbbvLBFgeKGxbfaI7Rbxjj6gITnEjdBo90AIg5jhYZ\nQhjGbChdtEc/S+toNgVibqbRn8lefOpGniiyIWwxqc6I3DDpaCjG5O9+5mEoyV2iTF3CRSSw67dW\nK02hTnn7rgKPErYIqVMmr/ayz+/yNZ/o4QiyPeYnDEhbR3qyFjb9X5zFTdEzmAlsfvkgbw1m6R38\nQfCXPzOxm/jI0GLN6OYXxaVvdVBCyo9i5Tx8Yf6b/lLI7m9VJ+NoYFsr8eZr962FgipqP5Fwe4/N\nORVIsDRhsIFlFeSnug+34W/4+RBkvcMrVIgVhvwwgyA0Fh/j3Wz1VFTGhjXlZoMCwFdZlugE71cz\nXG1Oieemi6TKyGEnN7DzPdb/vOwOgbLSOvfTvTyWUd9YcxACULDp4/2QvcqC6PoP97DP+AKVkDqg\njRdnuPrBh0xZKKuxAPRnjkpsJnnD/TJEc4GubL0/j95+k7oJoIUOezO/5tLi+RxhKIoZerG8MpT6\nZahyka/GNUDo0ACc8c4vHp0mvM5usdDf8WVebGbuCZI2kdpWxovq8KGFf4r5YiwNcnNmR2lvInx1\nT+muDULXukc2w4sw8Fv7EQ8/bHQpNUWJzk/Re+qqrmeSe/oLgo0gzdVundYRq/IOQ94VvUUMkGRB\nsEloCnF5sEYZszEBhhO5fVpCnpJHjqbyM2eXCwCc8WD/XNNYYETUk0XYD1jb0TB3WuXvHtjzm5W2\nHvtZG1QRMMgitcaOZ030BITCiZYVlAkPjDtSL2q0N4sQsi0WkkHaRLKjx+rLqYRf0sDmuYknwhVX\nBXoEXIZwYtcRgAyTRc5+fH3ThBhncSdcIJFtC/Hssg0QWi08i+hgqkBF5YpkXgqp4oC7YmjD8gst\n6X6KCHV38k0DH3urYbRBLYvo/YhiRQBbP+jcDepTd1M0L50/V0RmPiubrkuqMsZ53AYCpid52E+G\nKurzEpN8zp1u/vr1BWuEUdzm2x+3i2fMkaldeYLLx4WS0X204EWpdCGqvz6dNe0635yqejkpPIGw\nbZjNo7DErx8ufmmjpHnS9pVPiIwSIYhyFtcWZKtx6AGp5EccXhB74ZMHLIUp6wKGQkCSzdllvzXn\nPtRMmvGXAGaR5W1TbuWYezU7jr4R3sHWDYAWaCkO4FiBZGaZTfM7B7ej4VJOjVOinxMl2N8M9sCW\nxsQ4pU5Y7HJRI0D5sMC0zC72nxEZJg8+/6nyCpgWr4/URd3w1G2Wqd7SAQeeMlGDTCTSYfhRJ/4H\nCMnQDIkOKwTd55/4twdRJXgC/O/GmV1vDvBvc9qjjOT71EfSzVtcBBuzmxR7Zk0l0zLz01O2ZBvw\nA0zKfvYI242OA8VxUyeA79hJeIwAFKtZ9aKSCcl6cn+FQHvxhyJeNByHPu8A3PjdWNmKrKaki7ec\nmg2t+Yn2T6yslAQESXyCjoDJ3Prlj4EqgGQ2ZslTH+V2u5pGvvXrUNlmQGtiGeKd+rJNmL01ROgJ\nlW5RcXtOrSguWPjRPFByVNgUIlbq7CV5RG1IVAQo4xWYRM494GH2dQDNzQnqCepUr8wDgYbECqQg\nUBJjfzBjBdrzHpMH6RanKhXGjdYNk817t1vbqTHNiJwBKE28MmL2quU2YF8xQXEcomajCb51qQEf\nJWl6mB7KLLu9Pze3WijW4n6IQHIRr/SCx/CqNmm5ZZqRzSp17dTBuUuMx7UeOOZeGU+ri7J7KWKh\nvj/FzxpDfvwviyN61743zsoNmnJK6rydTCX6MsFV2A7koIrXOfxoZ4bsO8jovpW8arSWSY6WLWzc\nsMahu7I0AlnWd72eVMiMXXUEZAM5rT6fefzRkyrlItFeluiscPRVZL/iBaJi9xTdO4w1cXXbTrBM\nYxCXLxEXBq6syfwNNyKouHfP3gmY9V0o8T53nhSsNgyQzVss5DaEoseqikHwSf7eQDRoP/mb/Iog\nVYkL8eN6xVaX4M9FhvugejQDrEDrsuSEc5YdzQLC+Fb3QE1Lmk2tPJIZFgxsNRWPUggbHHAVmYk4\n+qL2W36HPjFSWKSSoy6qSPegRb0rOEYeRqsOZljO0CMfyZ+ZhOKSL/5H1mDEEaejC4+5NauPCEuw\ns71y6AIAlmA1A9AyURN1xZSJZzmqXBssa3QzeLMSTXt10LboKKv2D+0XqRHigf3xv2grErbF0sS9\nMh7wzFZt6WWOEYJTJ19gd+07qsBAopgnXiJptbAnQ7yNaaDxI0AtNMTjL+qhm8Mtwn+LgdxfwqWg\nIAFpHqgPjb1wa3KgtSlm5Hqum4aIF2kS46G9EmCh9yCIVmyZkhb1AkyZU5MXCsBxJI/Hdyyoiw2h\n2dq1j3Qh7X2LB8QaxmXGbMdcJUCIrIUIQ78I999Nf2VCbOAXEigMF/Z92/g3d57Sm2gjKtKZwCFB\nHMOVXrt2ilbB6HLKaqjRWVFlIJPjbsiWq9EOfcHdf5XBdL6HujRXftzata7VTxihcZpBer6SUBDv\n5HjUdEp74yzRyYqOq6x/tPxQV4Kn30LWRZ5Xs/jPKBZm+IAotzbVhA0uuPJpwrvGXLVIZ73DjB11\np7pVJEGorzsXxpXVv7ghAotsVZaYJTInRAMCw65RMGveT3EJqddTFpuCnbJlAsFiAWhZEqf9mhBm\n8h6PMasTgZDmeyDLTXH/I3xjkKjFzipqhxTJ8Ce0fvv9AMzYm8Ed9NpNqI9AoKhjeZqus/dfJYep\npK7M+Nzc6hnfL+6BgVT7DulRkt+tODXv/9EkR2bsDnV7CMXQzJzpFMpmUDPrX8wshcBQAZQe2z8C\nTMpg30dRK25T1zt3krZefwm7XWLbD0M54CENpRBdmgYk4adBF0A8tGed+NPXH5/ptNu0hRO0Vqzh\np0GN0Pi3ltMbP1iDO251SlEsNxPynBJTJnrpQTRoJCI4RmhrFlNr83SXHqOii+IMLed5Ei1yA6cO\nIW7owIoWjhDLyBT1rDeCWRVHGKFO+/34OAAig00W6IWAs1wHXLvFumtck6aMHHbr0BwvV56tSQFC\nOBXgEKcecTuwVYL0av/EGZCqyNzpKbPkqDRJLKbMawG4A3rtBbDGP52Tu2NCxrfLZKB5kcOAxXPD\nfpTLwbb2SdtcVBfYVuPZ8M187Qn414UrSv7knH8vOZhKpClsOxkMwJYIykj/EgnLae5p3jSMc+/T\nu2y3kKmwo26urEg5xfj2aULlF60tcgztCexBomcB5r2FJQTXbUBvAnXhd91/yj3NiKNDaY6tN4Wf\nNyr/nyVqilQFzlv/C1EFMhAo0qbbEB7y8NICNr2E1dxJtss1hyKKhsxOoycYAMQX7nKKP/sCnj/r\n2+3LIeIeM7OLEQTDCs6fjShhDVp0v5lUgcZHsBfi6qW3WoT4DY92hZUTNbnE4nPQm6kc6/6GsfOr\nTfuUQdi1WrhETUsykFDCYzW5BqIVE6KSLOmRh1r30G58RZ8tBD5T8rVC4OigLyp3vL8gFY6c99Co\n/w4GmG2c5x4v6P4/4MIZpd84La44b8aa/lOtb6s9LEz6X3nGEBLjkaD2uY2DuVo2hlxyyZAimXWO\nrPP+OjuSRJDIAFgS0cw/NNUrVKYzWGJXLN1UQlolLeLCI3yOQlweyc0K0iTIKquB4hk9B/gBjma8\n/4Mk/SC4kXKNDVoOtMm4P8fuAebZixnb9s7rPZ0cQtTzlB2VsMt1m5Xi973l3ol5tE1hdv2FbkYq\njlhWaBNpahQJU4UWch3XTKtIl3whrvvtX2mFBAIC9ANBLJe14ek+2RdtK30ucQSIt2oxEksQKSKJ\n08x89u/XtTrU1ozmPs1xGcXGyGP1m55ppNtqsEcPfIGaweWcF2+IoT/So66KbBRgFay1885wQFeV\nhqo0dRtolmIi+rGfzTTKWeTN2vLfhW89t14rTa/VbdyD5woXZ/DeyzVMYbcth5Mj/mN6k5WfVpQJ\nm0w4P9XcmxiDXw/GOpqFGCM9kUcnlTxdL4W6b3zcC2TAstXz2gNPQnabMy8P0mxVxU7qKYJTv2hC\ntWKxG5mBM3HwycSSPNXO3m3y5C4fc5hUncJ6QcNSuMQMSaj6QqwN/4IDHfMPF4jAvd6u1GNf5k9C\nOqvu0uM55Uhxe4JUfzHJYB4XVHzO6ypI20jfIduBlfrPaLR8pusO8Db3FpuAUdI9BDZdE2IKyxtI\nNVwzuesedunS8VZTxZMfSJEYiTP5nZXjYbyFdsvg3oWJOVCzvyadCwVFqP0Zq5QnNE1w105Bg1jg\n+uFZpDzDIAdSsdNyjva98N229zUhmmMGCSPvtyW+f5QSWMJZiYjKIlCgxS1YyUsTqSNMeNNHdPf5\n9IBHCfdVRayTO5HojE6Ac7kIObEkRa4ej7Rm8IWs7V9A80M80RZhh6/Q9u9lqnzvglzfF2rZexS7\n4n8QZU41miyHjZqu4jjTiLj7vXuo/8sudQBsmAwefQBlz3Zs9Slbghcq4OokUDMiHJRh9Kp7h0HM\nt8XsznL91oNbD5FuMr93tiaJGqiEBbtJLazPv25l3tSdWCA7DhvCEKXjdONjQVQLoobPAh4czE1T\nSmpn/mwwgisRIsdmw5WJD23Oat8MEze2pNtqmPz8z20NZKniDilclTw0u2awqu7LmTki1zZlZxwM\nbshQo97hDiQNwDKrNyeKHSwuIE68texevSze2uZzrK2QFxtv965SAxh/kgczPVn/ikGmzkdyRJBI\n7N3QgCNscs9chn4qxASdklgden/IwpXF7HkMhPd1qJj3hFpVDbo0EMVixk8KQ/1rSO1DY9VZ/L0u\nDCOMWUPgYvQ+Q9B/YjAZDaxKKo70Oz13GeQn0a8CvlscdYRSs43NdxPohP95N/1sY6uVnMCY/6sz\nS9uWzCapHM94RBo9UyYwTzIBnI8GXXXvW08KE8weOcxtCKN5WSebAGsYlbOT1QBm7l/tuh3ZJJL8\nc3nvT0XsiryO+kxJuQLcVihMc0Twusml4UH/+0skGBow0OuuuB5sYdC9ZpMFuykKVBOpe032d/fO\nOuS1KMyOTHx3Fzb12DUIUqMN8x4dCI8PDwWBj6/hOmNrQg6LdbT5vvvqKFkpL68jgpNuevVVP1cQ\n9NvXncYgZEV3pZb/lUhziZgN3w8sfNTuT7Ku+8MqE4Xu61I0uwSSzVSywsOqTd8PneJS8RA0Avrt\nncNOgDonFgCtXb86ArmDlYADoFStA2xewxNj0oHWacFUjLsGuOypHv766l9o0FQS3DLa2SYc9q8l\n7XNfir8N98ZIGFG7Ll3/8kznCIXqrR3YiI6ZF3j4NkVmb0iUqOJGHXysNFaJapMht0ThguwFHG4q\n3Q3RGGUCXzT34lETJWMqvXMhHC1xxD70nGs/XEoawT+WcO5Phc9HU2HcbRusfyFn479cSeTXiSRK\nk2NpvY55vE28/aFK2xQz405MgGsMjb2t2RpW7sFMDjPqgm/sKw3fjUSlXGRR1TlfVDrJ4ObxBKYl\n8tAKWwVgKCTl0Z1KaEzepcr/y4GIRdMb8q/QTHsqRfOnOFUu5Jjc/BgbqJM1Ai/fqYjLG/mhuT+C\npN4NgZlZhK1r8Bkx5d9vc6w508mzweIuIUkHmGFYkjKqSyFqsY9zLa+hhzJYMqSXkxP1ZZywlGDb\nWt4M5/Mq0i/p4W4ETzDuljZ1PWZvVQiiIhkqBbCpYsIllqJ5fu+TA0o6MZHJmTAwzS1aAEJCQFi4\nTttqEcBUO4u+bbPw/saNjf5k+yT9uDXedGpaSGC52icvL59+sg63njorl1OzLVxyLUGR0DJtE7QA\ngmTBvMBr3/P3JDBsitRtkvmSxB4iWJduFCA6QjV8uh5WAA5ubSqPNhbNc5IfWZ5DVOGjmeWAleU2\nGnSpg7uF65WxhyK+15Kb9qRGwvKnuNnkaZwSGCUox1BEnVWuLUDY1By7J9cySsEFXpVYZGC+9kJl\nz+7uJckaSsLNMpeZP1sVaXNFs70x/IVcAKMAFLa1s726BQ6WDIRU3+38he9XmybdXWQdNIWThvlB\n6Myuh/qia4aTcV4ufk3ycSVkgTGfs+tEGegTfFljozjNBZu9bTCjKqhisQ03hqLvFlRRAmXy2SkI\nkwUUPwFAZ/rlwqekOQ3x7YidWpjufamE5Bv2JxrTgct17euM2FIwkgbESrnWvFrL2f35UOTnA0Qm\napVTkcGYu47nw8tZZJXPMsiX1SkGL+KWqlYcY7CTlk7atb7gZKjnoo7leWzMcHRFbJc4CWCHv/1B\ngrDSg1b4Futbyy4/enxRFPJ4bQWs/BUsYhlbGK7P6cw71RFoSjLBNZOuYsCGYOjAVEPgc/xOu/Xo\nw6FQD5sf93l89zBB3pi4S5kj0w3ghl7YHOA1xYEJbFbGCj+g3y4+KiuMsiLA0H0pBL2ayJCDsbno\nhDy63NkCQnnmJxt9gOBpjP1maSfYC53dMYcwDNpIFZ7DmG48ZF/ai6SDxgqfy/bbPQEXIPpWuruM\ny6id/tKIhUf2aYnLD9MQPDaSwrdxmysGxXI1WAKxwSkYHw0lQvQ9kcQqEk9ILi/TsihRVjose2qj\n81y3BetACczm6aIeOMzDVP3nHwPmQCzGso4bnYbHSqxxoEh59LPSKkrF9hPkx9fQiVjC00payhH2\n+jiXM4Pk3/1LyVFrZTACRTPG1/fHEqewgPaMnLJFb4jH1wq9m6lAWls6cCX8G8YlQ5QMkKpXnB/s\nJATEy2r/C280e+gAPKNiD+TSsK+ZutJiHdCyuwFCyJaTDb/X0SVPM6777ZkLnsRraQi6Vs6Q4A/2\nVrDbqv0lViPEJzR4pGg9Nv9A15oRbFxY6NsUEjxDz/7ny+PgNbeJUvb2pbrR9nYFOkr5EZAZz0AE\nhw+fSUpJiKUie5F+J1uIQWImm2VsaOogq/3D/trCwz3PDa+6qVMGIs9iKlqKlEb9tcnvrdmuFi8D\n/jy8DK1Jlrg7/AFIIelo1yidI4lrKi4CtJLSOBW9mO6O8G/S4d8UkyqWFP4gzSs4py45OkarTOCD\nS/VFy8Jq7tjjgovyJQzhH+9FcNY8f+v5r8B+NCkWNM5RrpYAEWcABeYkwzviuzUoqdrlXX+d5VmM\nXJMpE6cxhWvfJ9PXqV/cILAq8Nwhhe3Ty4JAA0imI+5lo7fJ04G88NkIlJnwb6THxdTtrhufQR5S\n5xU4owGdShLA9n0g3q18m3QHrDkluMeJ81XXB2CXOTHHaCUT6Nt+Flme/lAXHj74b5sWPueYdn9H\nYEAbTEAXj15BO4SIDLcLUf7ituInlup3V7c68IrXVhCbWiKLhFiucM7I974jruVIDiCI7qe/eZNF\n0WmL3jFQ0scAnqox9ZFlCcBPCNK2wRDBpicJi0Il5LHEA0MkLHSlQTniXOV+z2Ccg9I7ckOXGYSl\nXW0z8cQXJPM7yj0Trtdm1FL8Cdf8dRjQIiThCoFP/7gKHdHdabUDHUk/gjrJWFxmocoJjiSwUwA7\nOEAvSZ6hh8aBEmusnuvxZmYYlPYhh6Rxv2hIsIvyQwChxdXBirykz21I5X6saL+WN986mPOBKeWi\nxscqn6T8PkscoKrx8BJZ1T+JnmID1/Ycpm3vQFwBBBYmxFZD58RxQNLc4YRdIcJ8tvEuKYw9+vzZ\nieleDRRplnQQBzp9C2wVfVsfB1YZxKmO3U58fq8YIYI3S4ozE1CW3D1jGARHG/dnMu1f5/obS0cW\nzuzaNDNtxM64Foyqe1MclT6Y6dElRwV6A89O3Jd2wdc8WOXSVLjxlHZXIzdh4+Dm15fVQz2t1ltV\nh19DIxoo7kPPazuK8ru7Tg09pQssFscQqhQgagj/RqNwZlOAAI1NC7+OzUdBj5z/t9agO4Vl/2aG\nG8tY7ilpU7p7FrKbSlZbjS5EVzMPHzxKHKOYIpPpBGcRp5G/Lf+fd0h+JIyFx8cbhqGB9sWSpthN\nXIdCNf340qshaD9qzKIutS18kLP3FZ+bhnO0CMj36sr9ESKk5OPRs+RrPod0zIGwt9BqR/ASMbfC\nmRO5eyaf2AzarzO1ABimrMff/eJuq+MicVty6J1Rm2sxKoBBp4fc8oyuQ/r6C0s1b+UNco+xsWgX\ne7IxFPH8ITNBffslNYAvjRAMGPYtOfu6hd57u9AWD5l9/sKMM3lkjM74DRL129PijT3MkQIQd+p3\n2Lp0k48yOjLc2b2XyyQKyT8ftndoGHrnYvBiXws0e02J1+SuHodRysckDn2MQSpan7wXkNfO0TL2\nqroIDV1jDSHgVGTX5lHF8qxlK2VgM93CBw0FJwsuBfukSCVdQfBTCVobTsYQx274U0aq+XL16hzu\nEXu8BDa9nUmJkK+gfC7MWWh2B9re4Z1pO7rJ/9YWXB802yNWdk5ZBE2PwDMzpTI/zvJ8TSy54QcH\n0WKhlp555bRmVJkAU67JfdBy9RFSkqD1ZycTPzcNrNc8LybP0eLuDcJOyz5sLJ0p0HRn7M0gc9mW\n4NzdaCFQiQ3Z5qfG1OjriMfIJ/mpzpor+rtNFKM6Zxcl0urdHnhlbq+x60dzVdiT/2aCjQar/Nt6\ncCxEJv/EXEoAgWhZ/vdR1o+E4SbBu4LLkRbKQBmnl82QBK2eSr6bmMa/EzjHPbqmwPTroMvVfVNw\nyiE6AuKrbD2ax6WTAPz0y7Ird/3oZ26oNDCuAehL1yHzjtUtlKetEu4dYhESh/l6nC7NylG+DzSY\nXuDqKqkmk/rsDCn8ud/uRcoH/8pPM8UtWxg4e2hOH/X//lpfNsxnaHXRyoVtiNRz+QIwQasuzk8C\njddFAJrt8Eo0J0ZoU4+pd8CQu6G3H6b7q9JtyVLnt/1G4JwHf89m5/Nj5xeryUfw/csRdKy6qSmD\nmKVDNhtC3Y1kJmAuvOgIDEypEIZBUYtzkvRYquh+mw6VsPQJlc5Q7CTRvHeWKLPUCMggKOkAGyrJ\nr+xZ8Qm/69ICTHUU77cqhYcP8OKLJtJASUwV4xTA28I/ujT5MQIXYpJO+wLBHdo5ZyMfHOz96kSu\nBNVUIyrGH54aKlCMj7PJzaqh7l18fgcfJymNvGMphd0D1fBZRZ+OS0/MgLF1G/6YIuNyFYQqwlVo\nkhBU0+tI2w4v2Q9xO/Tk/qQO0vaZcjwADglBMob7yYEGTlCCOMiF5McUEPxXgt19V/ZiSlTrzRbk\nYoLCltJUWeSs0fgIAMnGChFZsc6Qfor63JMftiQysOnJ63lE1x7e/rgbuHzX0RI8yxGku+2/0A8V\nu4ll1gT8BlK6YrfacqzopSKtG9rCc7ZeGmtNG006CKn223EkKNyQZ84mAX3yTzkYZPUSrSp5tM5n\nyLgb+KFZbfQL2jG4OWu+wHYJEgNpl0Mc8A2b6PwgyTE/3S1cO019W7VcERYNX+SxZ7lNmFeHj0/E\nRF7gOUI2w7gW/yRp2LbBbA/e5aWaC3aMHHcwEzHagunwiK2HJU8UKf0nz3jr3I9Hg3gLMYOJTm4M\nMD8n0IlXCngfG2ZTQJa65OqzzfFo2Y9dIncZQ0SA58nVKEOCcbHiFh4S3LMVgOzaM/gqtclLtN9q\nsse6z/ih1dhjmsZf1RdeYQGwV7sxxGBz2ENsry7BP81wRWddl3ygohI2QjCLeEkvgOEGTQ8fW1dP\n569uhsVXtBwQKzBFO4ZSxQbnZnjvevAMfoDhjE3SyBqvwZU6PpDWlOpczjhlyrozh/aLuAI1aT0s\n2HmUARkpqCkKykUEYU5UFqQ/fvDUcCwzo1U6Ai2TDGN95cd8wnoY8iQYD9oasE9uHq+knpnBB0Om\nwGqTvT0fqFzhUrIXjvGWu2I7QAsLtKgKQ2ZOKhBUOuhmmNFBwF1618h5m9E+BHJiSFoOBgfaNPeM\nyRygxUrY8p3PLhjx35nqlh7LquBLfYi7fWydGFbI+lmaGB5PzH0WPU/MhC1XWe5ePUDFidEoJIzy\nW9idm3SY3DunG4Lo2xxlOZTumtjvPgq3TDhxGbh0JpgjFmxSZMvJm21b7hDJqAJlX4zn0PMCgTEC\naVAZW3nEPjjXjHOikfLlgNnSU9rIG0iASzCH3A0vDZNAho6atGTVNsCNV2naobHBVxBe3YkGSI0N\nE3BX8DSv5FUY/IpsE0tkIkAOP0nXvkzyXd0VvHuDMi3YjaOyT3ML7a8S+bWWoHV5sIZkkjx15kSo\nVAIIsU680mGzuXJrxzSniiGah3aSwrUsRiOK/ykIMfDl2z/TwFtQ8n/RgGp4V9QTvvqz0obzp9N7\neg6BowrZmewDJnZiot7im9usXdZPSxCDq1Q845ZG8Vd9pZu1ZXJA9tNDL34WhN0HItCcocX2Be72\nV3dMFbw4OD9K4QVXiVTfQJPP2gFly23HZj6gvXhRPP/2/NIkekJnCAB5L/TDzdVh2hZe702ra28+\nWeWGMDau/ulQT/Hz3+4VOrQ9EUu/+fzyey/uQbnx/RglWU38oCnvBbz8DNL68FcaVUWSIMntTPYf\nqKLLdh7CNcdsdz5m4jvtcX10WulBhwyjisRsU6g+b+aQhN2SPE49aWjtRIIaDTe1IJiZ2qZbRtjl\niq1AvLIcY/NjvKAXiRsN0la+z/3dkhI8IEsjMZr2mJLSZFwMTvs8OCsZawsMD7j8fSmymYqxA8OI\nlSPSoFYH+MbriB+CROKcnawe56Vcxdnc04PjwULDcKI8+2DV600DoFxJY/oYLNgkfmKNKEzHrqQi\n0q0jbvKj1PiGXUwPc8YuNShbgUeGtfT4D8B1wsh3+r/BUWD1rM1RuwUitKmffeCwUCH63JpJ4z5m\nyhIwLO0QAJ29gQ7wxv0D6Hj+qvAjx3/2LP4q3OU8jbW6V+WUL+iDIL2NCoi6HhKAQV1eLnDT5Dw8\ndsL2XnXqu5ZKd0w952i/AGCt34Q5vjjewFODdfobJILG1Op4yqQsOd6tCJ+jxtysZHs8nel4X9to\n69pya9KgkdzRfYn54ZGaXD82Hb04y169WJS9s9MJZjLaTQMykmgW8GyR5nPxGVXDYO8oyvFAmHWg\nfH2rVPe7hpDpOmYrlRQ/Zagp5TuZGbAaz/2xKHqTpJ3y1VAuI/9NJa3kIae5fx82/SGLQV1cISj7\nsu8d6BbPcn8TBTdZY9fZH6bgpc+VUvzQJwo84ymVyA0StHU0fqmnWba/wIIjI0Lt5oZvHsWfjrO9\n5N6iOG7YMNAbMxBV5Vf7nQ1dDoohPPbUo7iZ29eJMrwYldMHuH/OrhPph6ztyfKOudgR+z9xiHie\n6Zbi9rFDIfM3LgTGYkIdTeK7UkVw+1cwkvfFkpnuANRxlf7LV7UicA5kHCZ1/bWK7UJdpRRtsDtU\nGNF1GLeZMYYaWUv4UY4apwWn92A5L7TcbSmFy8hda4z8Fbjl1PGg1Tt3hD3bp5zYnpPChl14vyso\nmv0tHoxn5krugdwQqsBmEe7crYNW2oG9d2kyJam8XBn/qtaaWRRhNGZ0YGRjjRGhobRUGsbdA1lf\nyB1QCv99lkBRzFMYBcDwF7uBTYiJ9dgqheUfUpIoqmIK+FwkMgqnFD0vpSJCequpneyjClTwC3oT\niFx6n8i+Wk8ml1Qvx/mq3HIJKU+Fbwo59k7PQ0dAIhMHnLMuaH4GT3yueWpGVdczthc0AoY6XX4j\n2/346cP+8LJWw7jq0yuZF2+Z7RTySb4M1NTJQRCExGFZJl3DDQfYBkq3hdTO35YDiC7hkASXTK4j\nU76xpKQ7ULrpsVuT8ZIyRAOXzP+wBCe8TlNS2yH3yRI6lO6tn5qQLh/GdyZNjpsaBye+MS/bnGMo\nz+n8MrY7KAffFFjrFADDknoIdclpJ93KPlQSe9LJZShEPoBdfln++G/UCZrE+0u95Hi3MUxi3kAM\n7Q1h4kOnV13BAr1vH/8ke9UUMW9BQR0WPxc5aIb9MJyWLOCe3ZE0l3EfuN1mJX3J1PwqW4bfsCVq\niMsuCsH70+67yzWQSqjvYxRFs6QjVtWsiFyrSWZEg/vvQyMYD4Ll5lL9lsWodxeyINvrwCSC+wyz\nYOPNOA8J9/xK+svQB0rOz/L9ZqGiGutVRyAKRPvqRXaBFqEalppo9gMN6kb51ddgdEI0FYWl7f2O\nOpN6oqDTsPjvKBf5+SPvo1EiCI8lBCG9Ul4nyL+bvnpGGaC2ijn80VhR0GxOR58ahTTwLRNxigaj\nZGhDHgyY1C+QgLJ8UED8Q2RtbaKC01o30QPC945XrzlWf7uT/ZSq2Fdy7H08V6cp9jVcENG842ol\nBywtv/zTJSR+lH1mkbr4s2pW8fQc7Qpr+IXNKbI5i7zNUbaj5mJPdzJ9zRZgE2CNfAH2E/AccKAj\n7zoCPpwIDq0bcpRzZoGePfnu1+MES0jZAWJoGkZr0vZX212fRjpHDkTsiTn7Aa7OAoKCLcWp/gpK\n8R+mjSHjkLlwApDqzpvQQbmAvoIZ2JLkBQ119rKvs1vpO5L7zUSB4y0HVWDPOPMy2ZJqWgs8O/X+\n2eHllbtVwgpL5iQrskXCMEP0sCuXnaIrmcdxRt5c8mCc/KjiWs77SgwSxLbiEYTUXmpbum6pmVMw\ngoyTZR9byD0+xN5AOTssXUTiWin6DhAYZEEF83fLzPA78Wu5Ds3CXIE6gdiq/5MrMXraivrdS+wY\njqhpLm2WJSRYWMkad0NFSwfvZexJFdvdTMEM033uAxVb/G6hb6q0R7LrfgciMq7rfJb/cpKUBzH+\nb9LbGJYafmSGQePYYFCrfl5QD6DRZXBpt/4RpWKKD0HT6LZY0usJeLfaUp1ZeJmq1Vv9LLIfvvx2\ndaN5hr43PYlA89gfRbN8O59utSZcy1iumyMEAGjLJkB+jTufZHbjUj63rbKrXhEboouqfFCzmMXP\nOtnd2vQyhrX9xXsym+MMbM+YHV6PqU1e1Svo07r3MEXU7KAE8KFOtRMN+PZ2kX+s+tWD+U4duzog\nn/Fmf8Ty2Zbhljt2XnuMsrK2SS8E1+lYJgdvGJ3X3skNOgW2ZMG132oGq61PjIU1NOs0GMv8QzZF\nZFQDLrePmFlFywMZdvXUgzJND1749aR9Dr/Mp4vf1I6lQe2uQ1B1tn6W18CfMs+bF1uk6IW9Ac4X\nGze2RPpZbsaIERu0iS98y2pKLeRFYBD3OrtcvfeGqFHZD9byQVmIaCXGiKYhrJP94XQF5RUy711t\n/e+VYun6GtZaoJ5umhM+JdbpLwNhUSnc08ZZoFw3RNXpIdFgtJNBzGHZDpHYEL1Jh+jgKzZyRspM\nSO/K55Y47UqiZDoQ0PTvKXM57kZR5vjfhjRmK0S7Fkt8ojgorJqTxwvjK3HNN2E12so4IL0RkJfZ\nISZCqvNsZLtpBy+dqyWvn79bmPSlwJSqfCjISFSunsgLqjBjk+yKS86A3/EPZKrkPkZ9pfPBIyaA\n7E4nrK9avZFGwVHmrS93hUDyl+JV2UTOi2qiV3qfNxiiqAd6dciSDpFP+AFAmS7fr12M/b7YbmN1\nknfs/kk3wLjQacxeeMY29cPrYbDHaZMae9RaGQ0KlaZh55tptYWQtHBIkCyPOkYNOBsTJUsaZfm2\nICLS1p8tCwcfcUizH3VOGz6R77s6yUJl+7vtcZklcNyDb7KTD7FErux6ukjXaiuwI9WDEXuBCL6f\n3Hhb+kTSbLih4K8PLMF9VWhxi+elKVfdMmx3+mGHR6xtl1940FSeJ2f6E5Je6cKcR3JJpLfurX6S\nPAJPsWd5AjjHh2mkdIl1HkdQiGS5oFogKqv32IVuSnSus9q82C2CqEy6+XLFCbse9YU2xHp9srg6\nBvmwodJV68HEyCwrSZbNdvDa0ptK0Wu174SiIH2OS0MT3Mhef8kriibArev7BVXOFGs8xSUoP2Vw\n+9sKumZvdWQnMp7HbG6Mk4ytEKvYbkjgQlGTU8irGBAZOZouLZlEgeiCAU0BP3yP25hn3vkpIC8k\nEwRpo7YW/JkAAOvruQdb5ijy6Ncw2X2qHXRZuFLF/4DR6NrngBEh9rTxSP/zPj8LjihEdZnRr1Jf\nbPsZbZbp6JCxfGR7f0U1ns0ReQgW0rZUpmB1gsuans6zgPu0EP4KJLGzVGY0KBiv9a0yYP01WwGr\npEaFPqoMtauE6LYzm+xwacnpXIfsJa4V4VzhGk5kmiHJ4xM//TZRqCv5qyj/MmrK56/pPJ8zp2X1\nl1qwE2KM7fohM+YGGBcx7NM6bsBaEP9o9zSo5+OPtS6+0TTAtJn23FcKoaz3BFtV2s07cdm54jrz\nFShdU1I4a23cOWjBilI2RpTexKm/pmLciNqhyLi1Y/Zvb1vQ/frgx80pjQRfP2JLUfuVoPUQYley\n77zZ6iY7SF19kUbhL4OI5msb93/g4acC49Xhy8EHC2uhQGelW2PXOxwOy1NUeKWXzurAlV+hwIyR\nTZy7HHFq3LQS3XeXSkG0Ko6iWOhdWva7vZV/ZhwJhEl8M+MkrGsTBl93BYJaYQgrHuPepqNeDrbJ\nZF/ed17DHmMcIDD5AbdGot0fK50ZnOjZ/SzRYd8TVYxnWGaVEKuH1tJKNsiEH16reWiKEgdp06Ro\nnUPOum9mQoBRRP4WZd5aA95HqKR1LEvk1QvEm2K2opjRBaJ8k9DHZsyo+I5v4F4k+mYu5A/w7EW4\nOElZByJHTeB6VDaSNwI2CHDUNYeQr5U4ST3OgeA82B3MQHDgvd7DjiI9dIf7UFVgSljZmcmsFQGQ\nXWCNALWKYAYsHEP4IPcAvak1xEt7Z6RzLxVcKUvaklCmXGav+1X35BEKaB3Ohj2HkUrwrZOC4i16\ndiCJaBdM82PDfbcEM4Ng/ppZrdXYt5CZCbgnxH0wtAfYdzr2LkVrOvCKxFJN/V+YuUZv8ZHVFnIU\nSfFeDR8RafuFOtDSF19qYXXy7vdG6TjN7Cq9gQWpkgSrop6fTqVdz/CdRdT3MvgTUEQbAH8+7ZAk\n6HEjte3hN/9XOiPj+gZCHMUz+3RqQ2khtw5dRiaGLvVWM2QzgokGFalACtrskxgncZgIcXDq690A\no9lLrypy7gQqvENsi9v9MLTGhlzM1HRnPf/OCvBSbuFoauxeR0v8rYA/sESeMyiTFqmOfS/rwU0G\n2qfJ/NF4qpRVQuU+XOVoKhaz2YcfLLiFCjiNwSK6NTArZIsdwf40nxfCIrNX7vdtnh3jdhzVOQvI\nhHBAEAO3VX6V1dXsaxpTKduvYGXbZZ7yH+DHfHtDWsuHKouaZIlG/gqey6XFHnm3r9Ru1OI+m6GB\nWeFjPa7HfBWjGxBqk4Y9ceAVd2i11Lj32zxAHyW9S75vzPtU49i6RyklCUtXKt5nlE6Q8yj6MaXx\nM+JfnilpDBiz2uThBB6pVAT77Uj1Iuz8vSnK7erXMCiz6Z+xbgRUlABEQ1Jqv6/bNPm1dCYbhEXR\nezvXJDaF8oab9mtpeEJug3cRDYcriEITFn3DUlYnYjDpImqzY4DtLj6O0EziQ8e9gikTAm7fIyE+\nL3XS8ZH/JQTEQS1nLDhXJ895m32U9FEpuRl8G6GakynBj9zaHANaDyAfiLOZ5DXtEAhnKPTWRE1i\nlTfbUfUAMRnq8g7eKh9GC49k1Om6WQlB4ttiajampZlOuSWegg+BLBuxhTX6EwovSD5W+DsoyMti\nym9Via6JgHxHGp5xhTb20ZIHQBV2+O6IC+4dgvRgYfUMvRl7xLxYjBBVJNvrd8LnpuiXExm9U6gc\nnqaeI5dzOuRIuMB7tn4JqHSb9C2u21SX+Hb1Mm8RM6jqdQrKyRVxdh91B9s6ActQzTSLj1xts1g7\n+zgwhjWJ3VcibqebLsJuL0rIHKkq2cTAZh16aGhBsi3s4z+xFSj/Re+RNHDBbxXbbUdOYeAGhow3\nHOCx5PDUTiENaYnPQtlm/WbwbYjmtRw02Z4I0jSCocjGj3ESGxEuA8e7qeZpMS/qzzdu5XTeiwWJ\nVJCpnJcrxdBoKWEI0M/2gw0EAmIgw1gTm68YMkZHsTOARK0j4YNUvN2J6CnhvPpqoZv7GI9d0OzU\nYn50l8KQSjKDY65Hz65eGrHz46WaIjAGxxYed6hOeVeAi60lL5wzZwoHvHzdkniXNjHk0JTk+8O+\nzoFnDpPEY5RT1yIr2efaKezWSVY3oneyqQ6qX0LS1m9R1ulr4/BclDQJVZwYjEFQXhUpWRXgPoJn\nlDpDrF9C2nKe8noaInP/0t0l9UwSUEuPVZvu6uxsu+ectsA/K2Y5BJDOhuHT05hobfdDvif5IFYA\nbHEmBlqjcBRiKjMl0QHthlJK5gzL+87QclnMvvJ+Y35LbzWx7K8tarwllqIv3tn7Gg/5sVIZ6vv6\nOYOODO0saJBNZFQPEMY/KEKbEUVn2a2+ublisrdUF5ItmD/Ey7lttUSg9+32Dp4dffgMSkrZoCYA\nGuEWXkE0p8E4kcpghccWs5YyMGp3ro5IXYPT2f72pFwfLx1w9K0eIgfwoAjVs1NgxCLiVyYP4jC+\nSki12L8b4T9Q6MNGD+SLAXy2zyyzTKLdfRDI+rb37XxEoKNz5u3i0xzFAUhTo3HDrdOojEfe6uZk\n24sd8PoQKoFIegAvj/n4RZhAZ20Kg/580vwHWrH1PgOkaFEA8rCW0OnL/5ZN9DfZwxesmUxuDYsx\nwLDrpa0vCYAmDPvJ/rAHDuiam+zZYavTr+biHUXhfCpaA1eGwW/FHcHvapURdcWkK+wW6b9XicEk\npN8suRWivCHcgShoHTpNSdvFyYEK46lSaB2fRWxIkY6nAsKoBQzk9q7z7bLDGDnBpSt0XGTVvH9D\nDlDZ5EzKodSgIa8Oe7Aw9gXREY8da9bYtbtxDfS004xjayqqY14OJHUDOSYaWbmr5CZIH+ekFbJJ\nX/xhqIpLyWaY1J4X7PpTuwP2BPqstDxi7ytuFTT+ZOUEFyAjlNe/WPr62C6Os0Wdd36FbR/9ekf5\nj7FzOYvLwh0MLpIWlHD4VDPTr2YrgJBs0lf5S2HU8lmqVZViQJ2xkKGPd5qwdHDG95kfG5BOL2Y3\nACPDc7s7v9Dd9rgrPsVBSzbPSfPmYkolzccn87KiR80esa17GVtsnCnO9KliPEnsjPMxdwnq6I5G\n48zQrxZNmJMpSzw5Ki3hHOqr7tOCSL4EZSXKZ5i2ia4/I7kVVqpgkl3GHR9B0IgsSisby3dMx5lr\nBXi1vO+gZlICctvPxo9PZwlmcueUxrBAOTGr7ijRalG7U4YavQIeGArqVqMJ1SIb75sQ/enFicGf\nC3+c8wD92UqEcgdt6FySpBu3WJ+AYF6BwStPc/r0UIz1wfiyCOTQOCnR8PqrJ2NvoocXFTqpJ5PS\ncP9WjxdZTXprtLAfBSvJYP/FjVv3KVRZTt/LQst6fc+7KXxUyZ65jhjKKxzueJNI26Sh+EJfnZab\nC1sBCcnEjsNfYlzCWM2D5KHfnTNnhkOqKphzf1mQx0k/6CHnJvGRYup2GPRJWRCFUIWgXJ6DLrYF\n1nj1Lu9+Zy7ZxcHTodt654RWqKEZQ1oMjSfIYDxVUrW8oDd3867FkyGRTxstdD61CT3tDZZD1us6\nyGI/5lgmqmGTlC0xjK8EMxfC9kS1yeAUDdvj4NsQN+2ygKvcG5W7d3IUOgrwluPyeNhStrpjA4Mj\nvHce8TszzvRHgHguypp+8kzrRVqqF+1J7SbxD99H0JFASzvj3H51EfYNM9ONWBNABJeRXnOHRrgK\n08qoxrsRA63sdcEfrIq38DZLFxl7SoCVM7C93bMNCktLpodjR0adOHqibnIb/y5MJpwNLn8oMni4\n+l+Y/LnBHyJvElLl7g7Y7+qdmrOo53OCjrfH0QU0kVuno8Lxz3cxgT6/W2TgFV/Hg8wzb8VyEIiS\n6hfDjxq80WmjTNYd1WTrTsvuwQkWGdT/6onyPUg8UMz7FTBfGcT6UziST7pe1tyNPWadumqCBGfy\nhEdBNtbRpmVaJJq0kSLukoiIVOMhWP0JZ7eEJM5qA8lSGfRy49jFnNWDRDsf4w8vu22jpzVu5lz8\npKvICC8RW4SAO/HmQJmkmonpQU663ry2nZ79kagjVSh5oJlQZejj5QlUmIVHq1e8OZyE63oL86Fn\nvQI2j7sAxAKkmumkFUCWFy/bpUY6b6pCQ23BE3UOuxvUCs3G+ssQUYRJPol0BWIEOPa2K5nU/GEv\nAPkFM/twp89k7Yn3UDbIQhpk8xq3roSY1meSVG066JqJV9rW5OXS5chmAtD8WFGIFtBkt+YwDmxL\nxcjJTRAswKQDkzhhx2Cdq8aSv8sUyQXe5EJXRSZNrUVVvE8Ea9ZthPc2iZLDHgogrdcbPTrl1M34\ng1609Gm95AmQHsCCOu8vTRZz/SimiKFz7H8HOKFZewmP84Ta1UKP1dhIJRa3CEhSYN4hwkoTAe6f\n0gEUPygzUahaRsD07siqu6m9WQSfg164yYYffsO/LTRjk/Xjx2j+hcQDMZbheaDGrYIm5RLBlfUf\nsY6RGN4L6ihuggBTuRbnl3jjQpSfCnhOJcEQCcaEr6M1p9D81lnmjdwLeldEfuw+aRJb0OtYbDwB\nZqGPmiFvBuA/uANRYfB50EYLT83p3xYmEiUDXeJi4Fz76KyR8jZcZEfJPASnSMQ4OhB5vVFvb+Eh\nuo9FMV4JQ3Z0uHLfVRMqVVqLPs10ymsFJ2lQmJTW0OPpY9spXASDmLgBTu14/cfaidQz9d5AYn8a\nKu6O4GdgNqZnp2bi0kruHxByWLxtPXxYGh8DgUhBnkaE81RalY3ZoB6Sl6HQQAOxZ2UvKbu0pbSB\nlyYasqkFMIV/lEbUZDYS1fzFFSbx9a3M0Xm70WRLN/R10Uft6LzIg9xIzVW+bxFHI6dETy83JGkf\nfiFXiQk5XBqc25XPPRZGSsDNSr/Ls8a/YlKHUHUU2mQ6eOTtpXWLyB65ZotACywqTJmT9lzagLFZ\n2xn/5ckHXBaLcQX0iNfxDkxoEtRSL646iUdRkX3PWK3yMUyxjIXV6SnzN4c3WxEiAq7ZtKeVHcRk\nRF6reikA25+0wNlFjd210XwyN0R8oVPlvAb06Ruoa5RkAiw/PxgSgZHdqBGcEiNMGYqOdxg012xn\noa7oZvwza3EtuTHLV0N8qqJhFBsFBqzw+HIigYP9MOZwPPiIbmRKEPXKeWH0jRITlhpszLSidis1\nVs6oSFH5Cw1E5WVjNjbwsw5z5qaAYP7xf6xfuVe/GtlAzgn+LJQjTizeuqpEBHQPCdKG0VlO1lC1\ndrbpA965Z5zCIagpyvvz3apjdBQ4NdSDDFpICxvlvZcRGG/1qfslZtYUfyt8l/4HtEjfER+tvzCq\nE0WIraKUXMFZdVSAKqb/Z7/Yjcz8Nh/2CM8kVH8mqCMsyL3OP7Uama2VFd83C1Gco2EIK3GSaNw7\nrMbcAsdKoW/RrdEAuSy6giLu76+9JTvtvE/TqTVEsusPqoIaOrYt3mWzTz56KeRT068B0mEHAqqs\nZDft21ScnNL1hWz+fTVtYzmegg/IdKhkVJKxE6gfa8WR+FRjinPiEmcVDNGdKTAw61rzkPRpHK/a\ny6EtP+N5VsTQ06pKMaOJoCtHjleRGx6gxplmLYbrZTCcTAAEoNC0UkJmzG5Ml4SI6MBVQ/pxo8Rx\nH7TbP1AIm7oPpjKD157teJphXzJDw6jYw3sJDnowLISeC6vDpX/FqfBA5ZwiSH3HVUuS/Pptyckg\nPrjDv+YgJj7uDgjYXGHou3LNr0qG2rdQcSN7P73f7x/LbFAm54zFloV/cz5AMyXPng0cdjAIUWFQ\nurKzWRoGAOXinSMO3ER/rE05/v5l71DfEMAFs+qoW/9J3u5jkDEtwn2leuhkhgb+FIyKrOk7euqe\nSRTYjsXIr0JXQxLdL71yoROJ653wXvUsb/ePL9RBKUZbpKSfRcvbnSAk07+UxmUmsI/69UzFbYLt\n3u8WekrBuLZ+en08w7e1O/wgdxIdPdyNoM6DyZBYsWw/1vq/h04LXFD8HRtipK5GcaZMxfvwOJh0\n6yP/ejUZBgGTiQZYiweKEvu2CbS+k49O+8GkGvZHVQtSwrhQhSm3upaBVUKgMVJj90lHvC/wPmaJ\nGBj39L5PVkGpYRA+8HSK3XPxBLKx0PjLaaVyAeKSwBtnooRLmkPJoIsIZBcyX/+b+rx6PIdCKs0K\ns++HmmuLpUdx2wopeJmYKt8hswOwcYQPotO1zLs5Ia2yAU8M8oaQaxicOEhH0YzkHAP3/8GBkmn+\nkgn+tDwTZoW+r0Ml2mZDxLJw4UINiiDSzs03mouQ1atIUGtMZzLiQqtcvSx5W0Y730Ho8QnPV1NF\nphFL7VoI2gigJnr9R1oieN0ZVJUw40myhOqL9VYZIKIByVC82AKPMJoynUnaRUAsGmasiQhWbCH9\n30qPC07qd/S78DaKA3TNHSVxVJzUYWaj/dshnb14clfbj8p3mmkJHQXswD7Dj1NrRXHbJb0QuVg5\nYVAVgJAWDyCKFT40ppmeHMQzlL3YDh5eYJ3JmNTMYMjGNwwH61DCWapczirYQTJfA6swy7+Shhjh\nEHyLuRhmBU7b5TEjwd8h7VRRTuVfHlcXikax9zKumYbeJpPv0lS5Eah2lYpagqV4T5It27f9AjMJ\nOfRcq2fs0acLYlaYPGnREjbroZZjS0ArC524l5u2W+zx8k0FuNdn/JO2WaffZsUFje2oZoFPGAXg\njb0cUBdbXhtMqKR9k9EE3Qqdu5lvFWwt3MG4tp1ahSozcye/I/FA1kgjxH3jf56q3mPBMm+eLgnW\n+WEGM56PbwNApbvPFDf5uoEk5+fptgAzn9XSzBwWCPGJ98a75QZP40+jHupmdQ1JpOYbVcuQfq8N\nBduucGyF3EJzmx3J76b6LNBCCItaSg6skD2HlTC5mcgGyxO4bAVnKmMczwx2dB7QL5si/Ut3wI2w\nv9CW9Jy/ySBUyIGTB2Z5MKF2nFuIeUQGdXn9ZM5SE6l/W9jiKCfMMtuFBM1izMh+gN/C8ccw4Go9\nmFnns8a0Rl3wAVmUf9B1bLRPfttE4B60sdtgvVvObq5iBkDS3Ewj8lsjQAh4rZzn89t3IJbxt1Qn\nIZrpfw1dOErT+RYgVUSPeA02ZEBFENlysK9Xz9eBj1bBg249vBCDlMCCeEVVK+Csv2IjYWuRmS4M\nIMJVjx/E/rSboIrR+7Uw8WRnLTtC+o1nnKg0INBhaT3qkvCFBBjg/7NZaFsv/gBTt9uy17pILVWD\nZSO0HGL5eRWii5n+ySDXQPRuC0EQPTOL09vpiGsGW8S7hMZ/ofDjXh7R2kHT0o57a4lhyt3oK8Ry\nrHHSfx3Ky9GmtcGNEkGkDJRP/XNUnCV2H1dztXzyrrXRHzW34RrDmV2+pZ2YcWXcfQihunYHWCVO\nyODPzBHmzTa9dUwfwhVP/mOKAqtyqSmvtc2qFEmBkHO2dEEEmW4yCIqLMLzo6/UTxYGSP17HU3Ui\n/mC6B5tkI5Hfpb5T+cXuJfuWZYEbzCr3PIGA39PASkTDRS4U8vkSBLgNH4whWp44k6Gp0brQ3zLL\nGs68GsfjH+657Bcg76oEHmItPk52N6ncq+HHRiV5iAPyZx4dVH6LBLv35Lz1cau9mby6jI0fSkDO\nHuwhHAi9CUm/YrfIJqoZRi+Y3T9kEizHtQu2rCGOG7MqjJHfeqnW+dKEg2/yJOu3UDqtH4PiCUAT\n6OaClJKsSBYamBiJXOeAx+TBsMwVnSrg8WyOhytkjGmlgYXSlKc/A5b2uA4aOgFPoAV8ZBwSZc8F\nXfmwASe0j0uKWQ7gn0s3JvWsuC4of7RGY7KrcOY0NngzRtdZzNOZocadKbJKxiF1q22FYvmfxd//\nQpdoSevU9PQTMobGOPCCsGrgS5BchzUtyE4kBinZ8jCVe1H98eIGoUbHNhzsAeDJrLFdXfWd4rGU\nCrK40v1cwKNy7sOwAImOVWRl8m6C8X8Y2N22GNJkJe2FnT9bIwE+u23KQ/5JMAwz/dw0WrUPePG+\nWKevUGnd9P24I/IViOM/Qn5gtAn28R0qenkilnZmKM8jKmpBSaPNzY0NthRl1Q/xMj1QJn/WHPEF\nGnteOeEQkuTjmEm2lNpmP72JDolt0JP3OmfeuLTOFbIQB7838XX8JsmvaVaxIxF/jjOoO5uHEzlH\nkqlJeZiTB0sSkN8w8fojCUFn8lfYx6omYOAEdGHg5p3KAni7mBP2tD7KBRwgcoGsDBGoUb33S0Y/\nr/to+Pf8zVAMyKfC8xeKeBfJxY7apl9PBsPYfX0tCMdhFVb2Vvtus86qaGNhPeRx0KliiZpxzRXo\n1Kc0pVpcPwFuSfuRewO7ibNFpQ8EGWY9niYjcDivHCpM//yrW8FRpnYNSOLYPMaEKSiHnx3kj3Vz\n9dpH/HF9IIe35RkAiyTaYShT5RJ+N3BXIylICCg319w/xEZz8xOlun+BV9BQql8D0uinT/D5dibl\nGgcEA3lhPKODxq5eaLIpd4p2ATmsAZS8kcRGFTshm1J+OCjHq4MGicshcF1PB1qbde/3qRvllyDi\nBR7P21tL1hCxhNTEQ9eaxobqXSNpkc/2Vm7tJUfAFJoW2XjYu8vJe0SI1c0ECqLKPEpwmSVwVvTX\nFKyEOVVNIdpLN/l/uOCcH4xIu0vJvS9CB2BfMffgk2DMg0GXsfccKAcYM9qxPdDBYiTk1qOUZBlK\nDpsq5Jrvm1jOy0S/0yFov/Ag/nV9oqcESybTrUdBvSFDjbSfz9Fas/TTRvE0dZENzvHaHhxJYMl+\np5pVssV6fduHUXFpUG7mLLnRuOjGxfk4UXKI6z3+5w/xOv/G7/NhpKEPIflRCiF6Uk63AClp17lo\nKjOXYcFc6Lu52FhrZMdPrbIUXcKGKhR7Db0moZhTOLlwOcjGkaj9tTpTDxlXxESZ6AuC5ldEiF35\ng5Il6jFKlh5tUpbYIwusmZG7mnkh9EPFBPq8AqLcsCV1FA042meN/LtzeGGH/rtkSl8pcKFZ6fe+\n2oYyWE33TYmERuFpbWGFXPGW3P89wJoxXRfD1W55U14s7Xvu2gx2+gpJ6VhwG8A3JU4KzAzp8BCT\nVzTQovfxXE4wtOB5zcVbB7lK8fmjFeO2X8Z3gmOOpHurIRQifU12NEbCA7Gyjb0EE7m0sV+09oQL\nvlig8v0WRvDyDgiGJ/facQxgYyGz1UDMbKcDQivWrSiHOF3Xxu0i+APChQFQ6/Fx+VOe8f108+m2\n6VFQciyZU/Raci2jHYy/4GdPXoleTR1vCjyAC/QHvZsRuIjoS8/uj2DzwF91ENnAeLcYs/gNFzsv\nU4v6Z+nhszUK77WgXLhp2pqM4ssS9UAJaHmAPZfUXwpPBo3xT+/bHY/xXs1j7+UMQ2cpZq2/kWzm\nx8Lc8V6Jyg1EQ/iTaQuM3PCHecJFChcAdFsnIJ5Do+fK8uCjwv8AX6KFuCMXC/+y0OpDlJ3soRN7\nGLDgjxP8bfH2G+dJknW/YRGUFFTDC68ILtoTuejwfv5Q8OHrHsH02nexbkoYBTNdeZhHFIrvOKr8\n2prlr63tkKu82MbpoU+kmkWt8ZOz9zc1hgP887wSgfmJf/EK9ORbsBczQOmKBkcLD/AnDwoiYYlN\nOxL7Qvkgp/51N4LHF/Vv6HOsRQuCC1SFrZw4rC4+8b7xlU/bu3f9mt9w3TO05Qp+xYYkOXdd+1hy\ny82GTvrMlku95L1rvr7Vjvn+KVAsl+x59NByJ3BMR7ekl2n+2A4PJh3XRyRKWdkuqlO5ESnIXlE2\nZoivI/AkzR7a4MrsBdmtluSCSfpwX/nujwFLRomx6o5V6F8DUO3UzWU/mb9BbyRelloRIvN3gsRH\nqmxYHayfp6R1sCeAKUhrqlFi0lVCwNrB6+RSdbubvpG05e6d66a0n/2+/Cc38uOOeVvzJKaYCSLF\nHyhqno7S9TF4uCUKWro+84Qfbw8AALMb0WaULd787UNbNBEM/lI17mpxeKT7Tclu1csecUz/26md\nD/CM74HkpL3hlaFO96XVkWOZBWUbOaZKaDrb/gjwrvCZ+NOvCQoFTl6his+6P5w9mk8bYrEzt6wh\nzhsdQum8Yg0XGPfV0QM82B159x9PTD7SJZV0AI/V6y3EVkARkUelX3ZdXkNynGVezd/Mq5os56Hg\nVEsOwVEVzm6GtTBBW5jWJfH7E8b6j6QSCu6txHQJ7Nq3f14nqnkJumx89+Xpd8SVBs30bFktD+fM\nTBw0S9f9WtUwfHzgb04SWssUx6RkXIZ3Namp71WAj+YDHp2njwThvGs+gYvklAeLSuBXhf98tl2k\nJ5ZAp4H2C61OzY+jCFOeJPR18+iNN7Xn0MwoNossJrNw8fP2cAF4XD9NFGGIJWqxHtSDroT0q82H\n/q3D/PtyizDxYkzdUTnNvsgJQHKHRIwXVgTd2psY/PcKQMAB9Bfaa2eIPNZubITASFjf7eV2NDyg\nowc3Y7HVHHdfBV2Nf4cBxxK8p8KKbU+Ce1DCk4HSZlqPwnzRDklIv798xAdo9Cl3IxLfq9mPtiHG\nh5VYHl3OOB0mOvglcJOofcNPyQjGPEwYnD7OhG55SeF+Nsjwbc5Co0gRBPywm29Gl9DYCyS/+3eM\n2DZy+isxpL5rD8/k0qyCY5kB0sNZhmTwV0CO1gFG0FJFZtWlP3hePAyqpABxkLYdHjyzhSHL+4v8\n48RVPdCuzQbht6yDvRSYsCutVu9sptrJtobHwrQKvRGg1U+dGbQ0ikv6YpzktrZKOunS+Xk+nsR9\nbko9mtCIYKxaoK02gq1Y8p8clJIhy/60pkcz0P8hKbJAOEKFZRlaaaO642mbMc6o23+sg5Vaox/J\nx/Yj7WUuk+rjXhVmm1jX2/4hkbUbDZpjn0PZEFK80soYUO85gAa8F8RXzUlaYQl0zW18Ks1dxlkM\nxTlJxSbA6R72uocvf8V0YIcX3zQkgO4Z1Id4RLYF29vzomh1ryn7yJWFif2TIqaifnrWVqo5IRF4\nKtERY0TMkNgPFN4MWlQb11lPhgtR89aliQrufTGBpjnl9cPYFsMcINrbf0PjZXW/zvENIgeFSxcF\nGqK2g620knP0e19dWRjnZfz9d/FrAT8Hne8hB3UgnZfyvF5wD1Hm/xZ2Rz0Io1J6ATghfD9j13EF\nqiIL5BurZrahsI/nntmHm4vKWg58spqJHWbdDkFAgB+9P4exQXTqq5X9otj55FcuOJX642T6BwiA\nGqWVqxIwDMfX6nVCw+eM4+A9RWzfYMvCUrYKj4P7g6LtAOxfyg3H5N3AKy2AGHO6P0fEAlfDsLaV\n69r93eHDBASiupz2fdil1fzYasTcmtKDd6yJL0uT7jGFG+OdYgi/tDUgTnJ61CeoO5DIJjHD6bm5\nwtIFgz0j5zFxfWb5h4CHSRmCdn3aBGRyw2eNxmcK1KSCevu3e61QZLoJC5Vch74QexRjOSdRd1Mj\nsDmprY9d/7zpEMc9xQTclaZIs6NX4GeCXQ2AqurskgTeT6d/6Q+sHano7JqbDAbHvZVrQiPZae+W\nJL0dyXJJ1cOE8rHnIwkyWM0y5AYcf5mDDIK+VbHXvhshhgQ/Wht6nQBmReYluWkXFRPRcn0Px/bM\ncefQB2uSuZMKCaCCE62Nq6SitPDFucm6u3RtckEgaIppjW4lp3kld0vEgKnhbl7TsTgkEzbss+Ca\nOD94vvtTT7XidMtAdcOm2g+mOgGLf3ep4ucT43mm7DOUHW1oJCeojJiOXJLtqQMOJmZXFU7ClWIy\nBaNGvzF/dK8RChC5h1xzNb4VL61K6/icI6SJ5VNYSAup8GSamm+q8j/CS72cr0wIg5jLkQ8ZRL6v\nEc+PkOEeTJ2/3yccumJieIJsAQ40kq9lDAib4xSoZC5wvEHusgQNDF+Q1rO21g/5hwV0bHSR/FWl\n6XkHWniRbuTK2GwFD61rLI+1ZsN3UQMxxteYd8lVB0t5C+umL5XasQl4YtpJAUgjFZ20mgQvJdeg\nx/GeIhDWButAg3PKnouL+BsGqnvGgjdhPKLwdah4EQ/INvglnpkiVQAC1jYnjLrr2Pfl7WgD7LCs\nFh+kusKNEYS4sH7ZChTdbNa4ihWs9Xngtccuw2qWB4M/K6mteqgNU/8AtWKJPFmU/iYgiXFWf45M\n1Njiz/gMhGadKi6VGabVjoU1BOxw2JHCUPqT8zZ6eGJ5TgQ/LbBPobgvsz04U2UKrZ7Jxo339Tll\nSOYfMLgkrwX96hURjtFfIkAKEFa2JEOB8CF7IW6+vjYyCQCE/xrXntWyaKY5uQLxzD6OOmGcD8Je\n7NwQIcjLciRMGrcuV6T7qUVlxsg50GimPfTImUK3cRKhqQLGup25s+ziT/bK/nn3YDUDAAdAnIuV\nXqLuU5BM4PTknl+aiB9cqEwaR3q40jEJglcK9yFS3v3wSioaVSoHaTH25hYLgLnpIKatk3zW6eoZ\nVRpFY+ffTyJTJKWmbbWlMgNsSmQaaKGp+hGrlejAwT3GxTT7Wu2miIvAx0VSanBejGzMqpCTycvz\nsE46H28C/8w2Kx86ZczjVwh6685HEthGx8bDWEvVzOcJGo7rKXKmVTN6ImwBIb3hu/4olRhwdX+2\nH0XJ7fw9zbg6KfHm5AktBx6pl/bo54vHjroervO4Y4vMGCQ6uKo30FvzhH0GDWP5udAkbbKoZaEx\nVvMrGPm2htNiuCO3SO8+4JtHVaJKyjWyiw7EUd5Y4PvDv1D4eZnCudVnowjEHxe5Njoto/ZYgTDE\nSy59oZhU5AnnntuA8hcj+nvAj91TBOvaAlNKOSEdx0vdz2S6hHAe8+mZxL0HtQ09ydciTLRVCc8r\nA+ewCmZ8OqhGvoR8adeW2/4aTpI+V9l56hm2TlM8d7fz2FovPtXN4QgnGyt7MFp6e4Dsm6fr7/UD\nnqmBj82wXOGUbKBp99GNwNhlYKKbtA65HT+v5PiwZnir1yQFUSD1Ia6cFIkgLAqzPX7TgW0kKCFn\nssnyVvMlfDL7OFSo/FqWIi5K3Ji+Y7GW89afJyERSwZpul34/ywCc4fere+gQL3qVVhIp+63PIpk\nFBKgzE9e1PWmqhY4daLuU+AU7kIh6xNlmzVLik5i5Gutut8rDOMz4r3Yq4DVKYKP9AcOt38MIVyg\n9IlZioP6ru+JIrgCVZ7OiV8N5Ei+IdwirmJJR3CMSeV6xUYM8q0YQpkoqAAI8/M24KVOzbBbeWdF\nxrzu7njSGIjZ+MhCbNY97EJjDwIdI/+6D4zSawZzIx0uWBL9Kc7eqYLQ0fkri5YgwWrJeXhj8V6P\nYfJurM2BKeL67AbQWgzhS8+2BBIfA35sgyQMHb9wKE6vyGwr26aEUfKKjEuSaYH6uvkt32+7JsiT\nsiS0ARexOZkm0TFi+uGuNWfIYKsn5o+uKYq4ocVh2hP13or+D9OJv6Q1sEWYa6Wtq0Fkb+/PwOx3\nIhb37bikOcZjis1rjq3HfGq6OI6DZmULkrBB+Wnh5YBJSnT8DKKt9gpciBrYqZJpc6KqY57iJjt9\nzYxWjqWpO0ul5mkPaurDVydV7Nbv0UVRCf8pb9uT7JtdRXic7fO2Xd72uT/PxcikRmYGOJ/F/M/A\nk1V+KTF7So9xb9iRxGk78fG7+iXAmG8yEjmh/OLwEFmfBiTfNh+lGbsOBNi+R/JFHECR15LG4LzT\nM5McaAlllLiYS2Gn27g2w4AqQ28GXlkp5U+S7Yam8Hk1KToP9FKve6UVJe2kczb0ZB4d2NopM6VK\nUBSNV0pkh/YdPDg+O282oxoVhBt/ezj97lc3/Kf7QvN8q9sHclqMRhNPe5hR3zNUZxRsTJyJ6/Lb\nKNpMVq8+2PLxuqZDopVKwR7RF6+mQht8IhYI554P5lLdRYTtefz1TZv/jd+3fZMrlnb5nNxY1OoL\naCJZ2zKZZGqerQ7A+GKqcznHU6+hOxjOH9osehiPX73vAHHP5WScWBuNc9iVyvsoLQk8fCVo8E9A\naOT4vZEBiSEe4RbYLsZtqKpHdmCItsnQRa0dQmwlTT6Nnchh1dEsEnlbc0pcXtUadfigS6vL31Jl\nNt7AY4bWYlPuOnLISOIOkKT1CEUP4CcThjUB1FFc9U0CDgW/HZfURMcc6goOMqOAmgV1OCWqajy8\n64LkfARss//8pIaLTsj6ryPF3YoitBBsL3irQs8E61yHJnbwaHZO0jDg9pi9lclMUPUkDtEUnvWG\nINOKJraTKodmya4pjTNpfSnRdtcU9zKYZdTEqUc1Y4dxgnSvCHL0Nsi2VVUVx/o8VVsBSh1hzaRW\nXqV2TY5lFdQSabqa1jdy7v2FOhqT+Gn2Dj2IeGMaoV4RV/04fHx82x9ABIXY+60BFrzGVc8lYxRu\nvCLYUJO6mxJIbh13mHMtsWPrOOI4DrnElTgtVq2camG2RcEcaiq4LhjNzsSrH+T8BIRO/ZQJJlLY\nu3+NVzxctDQtKcnQ2rSmbr2quAXSMGe4mnD2mPp9vVCUEcOG8Xq+cEVUEDxl66xQDNMmZsmLTb+I\nYTHRIq2C3Z6JW3JR3RaCWn89oHtEc/vphd/G39tm0E5y/0XwoutbnuasK46MlewiGesEeifG6s8I\noI1fOFA+RjYxqfYgfM5OR2VqnJz2lC6wK+5sK1/JSQv+RkWoOcvtO9OTR/tYKeOGaiFUQgvy+v/G\n7kTqR1MUVeCU74NW72n43sEIEevOQ8cXH18suddS6pGWVrdocP/LVQZtbxL4GL3UIXbqkRcMNk8/\nEGn0raVp9HnvM6w52PXFV2A035LjX8oY0gY086kTxbm5B4qInHii34huY4tS7ipFkeVNzzUnm5Mi\napFdwiKiDTN0gNRYyTjfq3b6kd90zh2LYdUXPtTbZmQLQ3uXUbY9aWJKTvMURFpJiG8VtUP002jA\nZKebN58mTleGBMwHYUrOf2l0bsVxZNFXr43q6GHXEbIbA7RGaYklY4yU/zZGgKjD/9n2OvvVHv7I\npUha/0ZoKVUHgdZeLizoiFCAgoPvG5fU+tWluHigCUoAXXajvP/GIDivoGqotKHXasHYOKMzzocF\npsG5gd2b2VZliTytSl0CQkluLJd0FnrbYtFwg9kDANRm0CvTeLQeR6gUN4S1yS4atV0M8Ci9xo9+\ny7I++1PQig1+G8GEm3WJ9RI3800Yw4dfRETccSX1xH1R75P9JycJuiHfBYHoyqdyAKJ3DveO1jqI\ndTREsXrgKWC/5xqHXGcQn7HPcWKjxSw179sPYR7VT71asz7NPYA0vnIFYQFzAOGdev0dGW6HwMEF\n+x36DvgUSzTHb8Lmo9wxapE/ziI1MgBEuuHrYQMS+f9PszBQqi8G8i4xj9N2jDDw/Q0SW8gA3Iop\np3chS5jPmJ9u7hA+bvPItLCQkaBOB3AfRyLXX+IjeetCWSlHG2CcjFHwZ5Co3tqjiyJzkN5NUkSG\nwYjXVo2C/hVfgKx7kGKghZ57kAu1bgMvY1uw5c+CtZJ5rJtBjWqbTpbLvwlgtLRQ5zBCMbEbR78H\nbvYr8Ma97BREpTW3LgM4SDoAVpfuhSshSok625fU77p7WBj/PyVWz6Opa2lGtdMfhEm8yjEODAS2\nbZAy/G41sxHnjPETwY/gcRjOUCdZxt6MCrPkig/cgckJmoFyUJEiG/A+vr1SRE68MkZFn3jsonKL\nrnoedVjMbkntUL4v1k1lYncmSnCgebrxOaOEEA8k7nQZpS5+GD0HRJcoEsWdPJGzqs6zNuIw2Q8F\nc72IndmfR/7Gtscp479Bl2PoaGacHYv0zNyiAbLy/t5I/pGXEE1x3SxXiy6DMRP3pwiZSOepu9fu\n41pfag1WjbvW6k/J12tWHtdrZxWHUdnR9NMpsIxIjOi+UtbJoxDu/QUpTZfv9+31ioXZhy7bz/hS\nVvWIQE588OZnuWqF1w8mczO0YeGefDTXTWpSbmte68J5Oau+oF2WPfrbYMtB8xOTyYdgD5cpHRTa\nTHnsB+C9NtmhwqEG1On6U0sE/UjGKTzhftas27X6qljCsKmr9fRql4JuQhDait2aqiVynU1ec+9B\nl+n9Yh7Jaqnz4/2SoqJu6xzwf3LeaM2FWBsTJENJtEmMQTbkCldMq3h0KLEghla8I6ogu8a8weCh\n+JhpDk+7dqDs3F2wtNkLmZt8FINoUpQXxTDQb+LGMd7OYUbFWIO1TYBnyvqRePPrcLzEx6VTitJT\nBwLN0/k3NaYiaF9Kos8QG5u/JuWCBlBTY8sZQeNqoYV9VpQ0RjkES9WeFJECultzmjM8uEEbzvzz\nO5PNBcrovvQJsblUJ1xL6Oh4X8TcMnJ3ywv2pKFsstUk9Y+tAaXOD49va2GPBipf3TmbioIxaaEK\njqkn/dQMrXgFLhX4XdJpcElsWY9xwSansZ/DBhsS4B4eTAyNfC80qD5TsNbttHvaldZTR3vSogft\nThP54B2tkTO9e6Hofv8Nw61Owbt+pn8/+Exl+Pa1zipb1cbh0UUfa8x3AHqMhl2gzMJu0m75bvDQ\n6l1Ep9kOIZ0x4KbLZ2jtsmHO75aPGOzOquY/DY0zpmODtG2Tdi31OuUvZ7CfPzCaKLuO421D7Ajo\nZQUK4OA1w0wVilVmzVtjztwzMf+P76MvLBggm+QqB2aBw+iYH88lc0EL6li5k6b2O1T1l3QjN+76\np1sm6c+Q1kGpkHxrJMmcViwfBP7iaFwA/lPO/LxZ9MEwwB974okjaHC2lze/M8sh6P6i5/EPr7Di\n2vHQ5EY4t2BVn5/phX5vFeFnU/yAAzXflpErQErj0aYSfjNS7EUOKPV/5J/k37MQE6ClBzw0SWVq\nuczSy7Ti8vKChXLnQl6GBZ9ObG/gFeLmPqXAOry8mF23s97GHr2KfgANKwcggOeaZVerjrrD5EJf\nCFWc/L6yUfRfhRFMZ5GNTvtB6Y9RVxQalZymx2jmZj5ol5/1viB5/YLhFMoYnmFXVshin+E0dJHm\nfMZi2fhDypaf0Ksk3+cu0gkV2kYRzoQcL2BBwMGXAzA1H3iIfXrD+YBHBSXE57t+8yL6oWa5w60O\nJU3w3krylWplN2A765R1iImPuUmzx0vtWkgCeE3a7La2PZ+r20OXcyuH7lo2rAHRj9SNK5mAkpQe\nzyYOEuBw1evygEyRDox/aoOf7HRsbhUThc9cbyj8OqZMiYVUaHwZzpGwCbdrSthKAGYZOIw028Uj\n/Zx8p+ptusB4//PDR054FN4/brinYWgxrlqnXsXe+wyuDIEkv1KYLiCWR1dSmYyGT8fc5GTNHGXQ\n2HsNLAfOa7MQeRqS28ndc3esG/meBSi0MPpGooWurgIRt1lXz/vrwvS9lIT1nbMSwtx0eLRJIx5C\n8bE0bpIp8ZL8e+cozFkNkKYguV1hCi2LVNWpjZndtfHOPZ/MOHe2l+l6TRJSRZwZpCT8X3sLE2/W\nxvwrNqn+6lGGHrEiuUJPT+v2f9C1ceeY8WE2j/XlX8nVAqytx1kljNN0orpVqTY1lQl35OBW0Dfn\nrqWjo87XTPDLptEPaeNqlT0d283gQjcgqj8utkKZVk2D8EVNZdnX5+AEqk1TYzzPiBtmeT/mxbQT\nHo+oPVxP2L4FOWcouT8+W6dX9yYP5Y7Y3ljQ4OyXODnxXEwT1O2obTLK4bMFhVuzSWvwgWP9EC7r\nFLpxqNc53pFY8o/4Xu7UQgD2JzQolttjsZuY+8qEcesQ+SAWEhEViX5SJjd0pfhBqiU7ekMxtNth\nvZh07O7hMV05XKb8ai0JKxAX9TMgw4sESHby1slN/TWwGN76ElMWlqwjw9iVR6LfkaNt3WJW4nI8\nAMrVCkYLqNkrgZORYwpTkBopvoUmULAgX6wYrI3vICP9lD2oRtdukr1egqQ3TNsyARUC4ni7WYvB\nquAZoizTATFFWigKbQqFjyztKF/0DOaAcMIvPoFtDi+5PX3mVGCOwDR/a5E7GF7hreRktR/dQZfE\nkc7VWBjoM9YX9520vUg7rX3xeKZb4z2BijJLw+uwqhnY5pJvFSV8fvv+jnkuo1hFs+6KN9d2I398\nNLIzqhMHylYeC6AT+lLFH32o+c4i6xFq75wvMi1+s75abiKJlVXVm1mJhr/JzDdAIyDW4F0sJHWi\n0oP/hz9EHOdvMn2RARCc1Tj1MiaLoGiHjyIX1blbRg2aVZlh7gplbjJ+qXrxQe3KaDs8iR51GIDa\nmshffGDaVNUFfwJ9YFvVQF7CtzBHQqx78nKXx7X6D8E3dLh4i+jze79FDBjcDtY2BMbddk51kca+\nxhl4nrnAyEli1vr0AW+6oJpXbfUAboIFKDJFCIJ7ekAZDoCBtvt8u8QimUSWyiuvS0qtYUFnc/YP\nHjIdR8/hROdxIDBt3Y4k1HvB9k6dslIKdOn1aZf6gEThkGXOtDKrbYWEiU0+CXGRxugIoJbgUSQR\nu/NzRJUIPgIzwC0IWdIKfJkH8TzgEj3diXC4PXCRsYJaRrKwO3bvGed+nq4GquSKAyFALyU9Q/QW\nNDwDww7u7R7+YxRCW0FKclYIJqC9/Man7tkoB+f6++G5c5phKYtzfEHmeXcxMMA5AVRfm5VSZcGQ\nNQdbuVQyWlT8+is97cdfRScTWZc7/sdj3jId3HQ66RP6epNL/6qrK0ho4hdpw9a5ullZyVzvIWCh\n4rvrFESX3zl1SwFjs/7cQj+13QppzHPG2dANWf+mEW5ZNLzTVOUylLqvDrbXOXdCDCyRApWhwRnn\n0GsKHA15dkFWjgwJWt7+ey98TuxjDHQw3jEoah9sx4e5aIJv1t9+UKiS6mEqJdHlkOWOAXKrfZPJ\nxGscLy6Cy2pCyw7DzRXZRu3fbbq/7d/FcyafSA02eJirF8/BaSiZ0QIZiig0zsbZL71zQByjsFvL\nX/OZo20DPNu0zAglfzAj4VW/BRTTkDCMgcSS+fcFiw8ag65e4j0m82UFTPFn0ZyD8PeLd8K8kI0/\nYrnGNSSe1lg1xgsSClaXjB/mQRznCdhLIqi9ZIlICsk1yvnIHSlWtn0Wx1vpfPrLwdmi+90hI99k\nQ6fUJCX0wjc0qFINj3dY8KH6H4Z8IGTPqO4O4xBG9ycoeO8BzyL96wLwlNwWB/Rx5CD67IHaoGYu\nwsVfE4sXd6YTWXnAY8Nbwjw49KReIB01b5NhVdgGNBvIeLKuFvFxLjUoOlC0Iu0jEHRSUGUEU6BJ\nO6lC9mcs53SygToe2ZLs4Lx36AezgeRvMFuxZCSlfdDnOQfxRZ3DtCDtShewLfkqPFtgqyzQeoZE\nNVerkcXddXYFZ1CHh0QhaCi+/IuZ/p0C435ACJaEoEU4tZjy/sJXx5KDPom5DlY7lOLZEiriTKqt\nwQRBsT79CY2na8O45DRSMn/0K6kLIlrjQKyoihtV0zZxHaZccw9lwEKjtarJeEBSSiahG39VR8de\nqQXbB1k19q/qklWb60VaPY3JdViBCRMdwOv04IWO26NQ9lrAvqQh1F9+2i2MNAuMxHjq4/TKOHcf\nDDxAy0Rl/s96YgWANWwQGuy+5+o8aIkCHCHE3vnaHfIHRQaKO9zZkvtRXZAhJ6A7vPjsbzOSmNE0\nfbtvM6QYYv0ZlVLVdVAWcG66t6LtAHiSpdaeH44Ov/E5Kord4OxBcjkOjoJI4H1A3Ucnt0fUscK3\nm4BWhWWxQaLtM2Cna8wR6Zouwnm2lKfrrzL78GFnhjkdRLhBJyZ4PizdoCN6179hGaC+Qr4cIq7r\nN33gPbMFaUpwmTla7OkseMtFb8I3+nCGFIAPq4A9TPbRMYLIswn6+XLRwYZkhDElY8vrgmTcl+ZR\ngrX1VrNMC6ncTl6Fvyjayt3a0PjbacCbFdpfXVZmAvRmIghyKMW1liPM2eXul2qk/CoYzrUQhMb4\n898NeFwzKDO90yfcSm9PvGVgYgaZH3y3IMRGOUu3HO50XqcIWJkZ/A+EGhS9cTrzAZQTKoVHcAGl\nq5N8pI6TfwMHIuX8NCK0lzfytNCdpRhKSkPtv2YrlXcvXSgVXoH1Sdlu5vOxqM82+ZjfS6hcif/c\nQb8x9C8w96YZ+LvIEGVD2ozJ1lcY3Opepl726ZitURIDTLKrjoChoR4BqXFauQG9BrKXL0y7Kn7Y\n/enpoRww7PNuXNT6HMrhuP0je45bEWmCcYAtmwoaqITLqGIgMid2VL0nx9TJAbw2akApIGfWZJ4b\nSeog6ySZfdNFWsvkpuvn3rWq+GwXMZNXi2i8dZid4Tbn4BaAaNMUK5OhpSco8TVwarO9MssohIzN\nSMWA2fluMh0luw+udMf2FokBurrqVEWFNQnk8wydJc2Z4DJQXyuJa4vnBq7KofwQj/HvcCb13fXq\nRC2sksGEU/B8pgarDOJ3Mbv/ve8ZoKjxfUz2FEe8LNv+MCpmnI/e5vFmgOx2cHj9ZTTX0u9iAO2P\niTNR/A2ub9gT+nIjurAd2ftVmN7gDq4TBNKs3vavXnCgjH/5bohFLQMxlYCaATvr0bvhns6Ul3/K\nHFr83MmrCqEtzu6B8sHb3dU7fVOyESvItw6zhBiwxhHRaee6pwGKKicyLx/H9elhgk5gsjFvn3kZ\nPq4rxx+rzsRgnlK6vG8hWT60G4JEPtWShmoBkrN1gTWvCjRxTwA/8YM4n4hsJSwituB+QZw4h6S/\nz6QCqVVqHR5q6HKlxKH9yZXMf6795Bb4CTqNtG8/1cN7VHO0EkTikz3PQpZUe2/WQhzbrScpOK/N\nt/Th1pXNeWf+n94wF7iLZFuHiOgs/7hReqwk+HmitYUfufffEz8OZ78mozXcmgKY1s/fIKGgvkd0\nMZCbnnRHbRdCFjIOHZVgKgqPmglh6WZLz7ac+zD7G9NZGDpd38xUHDevzu6yCmVL6w/3u90KTr6E\nGarduqryhf8jP6SpTqGcEo2tE7bU+hInBWSSKVcVqVgHklPqmpuTT3nj2t/9xf5lzXPh51K3posg\nE/w7odLpNSE9w3g9gsOb61NCQ2icGwTAC/mld4RjV6iySl56JJ43bE7Zz7QVeg0Hup/eyrriLuZE\nlCQQilYoeUdZl45ZzeLX4Woyq20O8KDQNrGGJRV20eG9Prqf4gyhvClYBIsk824E5jW++VffUulB\nY7LLCzvuByEc3hzHdRfYR/uid3LY1CgfQrSk+dFnE93wIb4+e70XPlaTIbl5nm/QzCdwyLQI9zs4\nEsDTvNtS+sQT8GO+YfIoGtMc3cziXS+WSIOqZL5NSgC9LBZCTfqQRBvyL/jPnLloDoeM70jLFqoO\nxCCCkYNFml16voxg6+eDONHt1Vsf7NMRSXE28gR+AUo1h2tDt5XKErhelzACX6w4IwHqFaUN0wf7\ntjz8RoN3LakbiZU0flNKZkjkCes0wHR6kglfMIaZ3EN/G7FEp0qBJ9qyHQOXqQxqqv8+DUBZsCx8\nJlN1ygz18gblzZyqISEY9+4saEZ/Xrx6svkXQDFy33bk/RPxPl6W4B4xnZ7AIx9OZlZOfYDuvZzV\niaD8kVp6VPgonYDmwnI7wVeCfo+befScX62fbBXelx51eMgKJm40by2Z/D3bAu/1cocG8KyO3JjW\nxyo+zbkBPgDpGpcD++lOafp5/wqk5g0ZzSzfLNMkrq4pbB6TZ7wEJBsm4+XQYk0ci+4oHOwH3XHy\nUWFtfJcAKOoSRkXW258e+bXAgO0iZmFjbe+opffoGLN88F1I3BrUe7liYh0PHr+SMKAQ0+aGlXEG\n8+Zi6rCvXoaCIZdhZAuw8UXoLJrbIC0PuFLN+O8/6htWvWHauBigvm67SeRwk1KSnNrI5uPXCimE\nbFVzE6GWNRJPzOYNY6c40xg9YQ5SyC/ufh+IpkrJ78DV4RihOCCLbd37FBlwwwBND89HMUeL1J8L\nAVRfOWLU+KY41EpapZB05v17AUESKg1illfLGtVqKwcEJDPBPk+Bcg0olDtkpo4btQS0XPLhCozs\nHhf0JafNtNadpLyp6TrkOVIrlK9DFwrOn6mJ/zEl6DD7I6s4/1vr7sF6c+y4+IH56KQ4lbij0//N\npBDHNZoh4vtqIEPYXN3/6KpAIJ0H+4JxQQduuqfI9nGasLvBLVDS/HS8HKpmpxSfbTUhnYpGTC2J\n1kiiLBsfx9xPCc2afbfuoiuoO86oy0vzaQ+EDRC1Q7Feji+Svtg4nTJ0YyeVxAnjfk9pV8t/Fssx\n6bKfeCS7hFFNd+mbiCOvZw9lXtDkA9YGRGx2AXqmm4BqNgtuUcPqIfW+hjvAbyrK0jrd0jSZw3s/\nkwXbytokntFenJ9yLwG0rwd6S4O/vgBaP3KRS4YVguFK1LSGWb/FXJ+H3F2HefFRr9yEQKWpujvJ\ntsvXvr/n+87uaKuUE4XcHur+WzxcJhol8cYeqCJSnOF3wseq1E/lH9GD7ZQfK6U/XKPqqh4cZ06I\nB5avn/4ZKydiKSc5Xq2fd/b7poO2tHhVV5RGB50OnbPL3soK3/wwuA0sNocniss2gWM73c5W6Sxm\nw9+V1nma+j9Of5oVnCS+0LxYEkhq+53K6hqn226TnIU1rV9hjIEWpXIfUZHnQjlRmsM0tnmvgeaY\nBUBOJ8fmdskF0nr2KbX5zxVPB/NrKdUzqyrQpJEouWiH1R4tcSfVxsw/ewDxsp4v7G4iPmzavKQ7\ny6aMDzOpsY2r88vP3/3UkC+E69OKlHE0A2GAr1qNQ771tkwUzSjtBGCcZNNz6OWzYj4MC6iJ7MoH\nRl0NyzW3H+IjhI14EMyY6E9A9/9DH0JUWUj1MNAmt+zc2pFKBKzHYJg1sxeGruR/o1wHNQjXYQVV\nxa6vKncBKJ0QVqaWRAHao5/P83LlIYoYfaUlg9DvI3AWL6AK5Gj816SO20T7mTnAGthw4tJoDytO\ntk2c+nwuRyrtm3/MgFCM05FpaeMpIkwJwI+jDWjH+sLm5vo2YWvYZ/htjDEspZLYMHN/bb94MvdN\n7+FfSFAWV78fNWViC8DLXwPW53B7U1CJ/10UqB7uM6YQ1NFv1Wardvo71TRpnX4zPhYRPxe+UInd\n31pVzpSDCTiafp4a7QdqSCWc7BNnrU8x/d/ZwnYq9Twnmmorr+cUO/+seIYIOVoI8GjsevZA3Fnu\n5lO63wEqgPXppr3s6WpDoN5OCVVBlLZR2dFOa94n+xLIwB46xP0WzgKWcsiHflPKr7yOiYbXQGRY\nQis1BY0r8H7GH3lJANYfvQVPrjovPz5MY26uwbuL8Lc/8XVH+xlti3kZWooXez5jTxoJbcFaaiHj\nS/r0NV6EHZYz0Ir8bP7PKeN35ExlJa+ggrJ9Ll8laWhBWnFWe5gePgTjxskzXsA3wuxrVclpeWg5\ngnDST46F3huyrB5k2dSkrLXwrRr27odLzPhTcunuls+J4yS/hzGRll3COjTEPEgwMoxHnHr2R7+U\ngK/GYcvwdDN89BohDdBKuXqwp/CIIteRJri4s3zdMQwp7X6oJdUOLNvqY31T7yWwk6MNMfFiw5b3\n5+d2tyxmTh2kqwh4mI5+uNDWJkf3lMPN0whsOEzIztjLJWsOBlNAAJkWyFrWGFjbch8/a/F+BUhy\nE6fTqumwXOXXaB8JqbSvuuyltZTrsLFWEGFU92C3J5VB9svYePaD/1EHjTDOV6E8EJrAnVI9UgVR\nRe2/6ILPALLhDGVNQQEaK3nb4XNioLKwMpG2vPgiW3jgWVabjVs42B0RS7m1MWXwvLX9mMYX8z0t\nxdsGixCt/k0bGOWY2uP9x1Efta8VytH5NeM+H55vovTOF/nH8PQSxEIEXQBnCTT5FgAF7OQ8k63y\n7HrCSupfn9OyY2/YO55utmiBaEip0wkh0jvzSmPLjsi1y/8KZxn2vf0Rd0h+7fSfm92qOQzllzCY\nl8/LJtMd/cEY84w2bv8UGBMPwM+CsL8cyou2+opZh3OY5hGOm5i6waTuh5s313OJk8QzVFoLflHQ\nPG+vx/jgVbsIG8n07WYyFV22i1D9S22dqzurDt998cbavI0zYu9cBjBF0QYLEcnSFjclNGeMcLM+\nsC9lzo60UGJy4JxzhjekLyjN9csbUDmjCO46KlFlNyehC46ScSdYupy4C6x+WgkqkVxu+wojSapP\nL9585UhWl3KTYUsk1A+IlXGfaA3Tu6r/h+DcPxD0kZxRo1exCG4W8s2un0dBtlxCjX465tNhiaTr\nqiiAS8kXX8FZI9mfgS540/9UhG987gF1AL8Qc1WuR3R33nMCYCCfXQfyT0HmpTID2hLh8mPq4Oxt\n7B2jN5j7IPOWnN2X3DkO8E63QfrjLdPvG/Rb3vRdTixOmQAxbrOOtKYH/oV6X0Qs8qK/c0N9ZSU0\nESSr8BH44Ae/VbKbes1GIDAVoYIDIST3uNHAxO44O9hp8v89q1N4LvHT4hO5XgpY87BsUsJp+WyY\nq5J9c+kKVlnj9FstmruwYbApwV92OLOWJhdQpL+1AXlQKnbH1onqC4LJ4bJjAWxEMOZcuz5Vf8HF\nweINzuo9GtHBifotA5op71Adewc3WZtfDvB0kBqJi39LWMAIXwcDDxSRuujJx2zm0X+wKSRwnlOg\nDNVaeZcNKohWeNcC66UjExz9ttZifeFAuh/yKq8sLlYVJ0g2jl0pbvA0jDKnGMaWp0ApHptYnoAb\ntjUSYXhQGug92EthJWGE8uWsByKyA9N00boqeekGrBEZ5b34m2Mr9wdR4ffpNh9mEdGsBXczKYru\nXxMLeyYqnU3JmwQZZI12EMRljUYhVyRjtzmdP3/zWLh0wWso4t+2rwb9gyG/iYSgAowBXpdz7Ki1\nFcAG7GC1N5B5NeqQ/jsYYWangPh/MH48EMu+lzZlJui3jIoKniXwHquLboyPUWp84TWb/jdEJhbJ\n0CBLqQTofvUhgPsYHpmyhw5Tf+qQQ/141Ye96h8/7CYNJxKUjomZJ8H9KCdNyvCdbmhE87Z96kUi\nz6w1ot7iSx6AoONVaUrPFcvtgIF7gcpVVzAj43eMbj2VwsiODlQ/ijjtMhnF6aAwE0BgQ15oQODI\nFm9MMpVbTY5ai9eEAvDDpc9WrDqQ6c98AG2sVXfgRTGm6Lf+J5R+lGPsmUx8Gb/EZJLs8fI8YWO9\nkzLqc55KFZTlqhfeoFLo/NWTKpV74XaFm+YFctpTnqKv870XOVl9l7E/VD/kcJ5rXyJ8HPoQTVta\nOqAoY7nJyPlhYAVfjfAEZYmYoG09SrnGNOonRgYPyXH9SUV6RuWU+7BLWW0DuOuti1QUV7U3HHxs\na7VAFp4lcelZuR2dQlHuxmUKipeYNW+lh46YK2Jq4XgyuAJS/8LV4cQaF9SKp3M6sg/D6PS0u/iP\nTk9kczr7yL+Ko0P540R2oyyK8gti4W2bDklXoq3KerLKsb1OyyXjV655V012LKpieNvdecbdZdHt\nbVKItGHNtch/X2Wmzrn++ufDfJQdMNCdpaW3XuFJ7cckICzkQALwnRLQ3KYqpRVsnvtAd1DXlCnS\nFhaEBmxv9vMIxnzipkdZJh3NDOxvnUvBjq1WIbn7NIeRqkTjmaFGoU1lOu1VBN5holVQOUymrN8q\nOuO6/QcAiXfQd1d1pzqK/qWi4Nqyf17wt+1X0LBTPpSRFycYILIQJ0NCwBRlQfUg47LC/CWZYE/z\nbero/MKvMuxFYLjPY7VthT98uwIKBrJWr+/22nYFKN27btmhmc86kBcingXxGddifEZOMOo9r+0v\niK7IaiX0Fk20yn4uPyBKDn51jXUSOWZHTdnB6RRKTr32s8BC0lub/NPue4F+l9kdpp+9AxSdEEXZ\n3Jca5uBvwQT/PG3nSLnTSPeFq6exVh9xa76G4ubYxWTZQm8/9VUgyeECfOGRcWSGsRFmLyqSa5IT\n6JARjNn+EWBDnTf/KxBp88L8Gn0c+h665z05M5vDAPYvKbtFrBDpfAAIgGGpK1k6P+4DddvHCiZ/\nBZKMmUSbUXqdpOjkBAOFXxD2MXT/tFcHPhDc/jl0vGgfOHSJlKnfZQk9Qf2sX49pc/6GsgUaQqbq\nSIfy7l9g75HnkM057efINmkistyEFIPDFlICCSbjMAeGFq2enMA6JJaxjNpBHpfm3leReAvtJ8Pn\nuCNE6XdJvPBDrrdw+WrtrkO06CObXGMTy71oQPoD20xQ3rA5WKgYOva+oct3g4p2HEYWC1KxoT6B\nB/Gm5Pa975AKWtiIbrZS/pBWAE35CbBk7SjG8pNcCD3V5bEUF2GknrfOk/X95chDtE+tVr4F0oCG\njnO0ssaJHpaWFQB17wxrpPT2Fl4pO1znuWdml7o7Y4P21J+3v6jgzYWOZ96Izm1E6aNfGck8+Q/n\n9eqgVUH5I39WybVJcF09sPKDvmtYsIqsJrB/OujtEvq6Ek2pAWqpYlgjnuxHhsALKy4EbqE253In\nslIW1vrvCXISt3CxWAGbfKZJxl3c0yJr3bk/wKjYl8+wMgLm9s6ftps/GPT+Wwkf279IPlhelFbe\ndOu9XXpe+LomIZqQ8S0IqULcxGfOUx9N+BoONuPLlLf+kW/9+pbyOkCeJFxAMhyDpIu2odE8crC7\nvMolzgmbnPxjj+ZcSKvfJsFTl2hOq/nKAoBm7amjktph/mYwk3kC54PgF7mUf8Gcu1GXZ57udyg3\nqCDtJcDVeOgRZF+1TfdovyUWjaShs3c2yZbbGoqF4rgapYtYHxsuIYn2Vv8kaJ6Dg//Gum4dFN2x\nnJh3LV/7cNhmag141D1lxINHYOfZGTFEW/8ufUvn52VlavJ6W6ukDnOP7AvtiJe1GBcWg2QqxxeV\nLMTQkREl7Z8TvNtUZMX5YhyceLycQJjohm9bxRem8alfCqJXNGG7cPY9yR1zZkknPW+iwYtq5XW6\nV5Jjv7Zzpv6KQZPHsBEiPy466hl2heyB/Xfg3q/ugP7vDT8Xpu+tnW81w4Gpi6bD+JRKvJbp5Qsj\nGMxJ4uwsMK0aGjpLf9NX0vhMTKHj+ud0GVpzVPj7BDKGQDA0dUEDeSjFn5KVgVUUvgOKvHNDbaqF\n6IdD4gTw1O2p1fuE3hkPikU3jXEkSvTPZoTC6Lh1zFsIiMSv4AbGw0n66F6frIJN+fRt2JgTCnqw\nVW6zyPR+iTjh7K3Un8XcYRdQDCJtfbEFPz6Ii4AkBCoMGFlqw6Tj3g9croUkCJp+dW0e/5/1+/2W\nJoRBkFvlifbh54wEM2ScuLVyfs60A0AovRv1sVPE3uIncXsEltnysXVptozVKpcqMXjPrbLCEH+t\n3XTSzNYzmhZ3NNw5lMd5NzxcDcptkKThZ82wJ8gpk3qfDbz8ergXm+rKJw6/nHP4bIEl/g+CB1L3\n4fLMtmaYxlO2Z2/HT2GkyKfJjRmae2aQJw4qVAxFigmJrogPH1sxek19qWJAX9/+qcYHwpdUOXWX\nVqiFki3trExLMGF/AdzfRLSPX8+9WqX5QO8zi5GalkPt6jD3SnpMYPziEt2wvgb/0NniPzWOzt7t\nRjij7ChcG6qJY8q5h5tz9JpKJeb5Yy4/lI8dJS54T8NiuVKNEje3+u9D9rB1CVLrDRo/M0fuvGTZ\ny+lwgStlOQVRiv1I+vwIIqTvDHY3J5LAE8ujSy+TJhrlBcqt2HKPJcZFpq8dQSau6KxzabI9Z/yG\nwJJkhr1R/aTeIzBH/tzGVpAAELM5xUBeQv2VqpJUfRg6mB3Ls2VQ4rCXPfoVXDcDBxY8wkrEnnle\nyoMS/1JhwqFS1gwGXBfxEvg62PTBuotMlHgPoCVCWh0hHQ/gcatMZ9lfil2bhoh2XQmK453zp3BE\n3IiS7Do3qYQA7bb7MZq+HGJXjPG3XXreW6HaFqu+fe6l8AEKK8Wrl3R/AXuRZbTbrXHY0vXRI9q9\nj+DBe9nUDd5BPGKjvtWqGuVRWEgZZBzjDOw5sz2IWIBEVYfICCctFqgBz+lJQ5KfEvkEwOKuqTP/\nFAU89ey8vzQgx8owABqaul4vim7CjSgwKm1qtg7dtcGHSSjrLO28sXcxsAP5LKXWyIBwAkQWrkJJ\nBf8jqJgScvQMpcEJFUoeh9wt1O/fQhkWhoflreAoaJ/t1zkmwBtOpyCZVeE4OG2EhUtpf2gzjXuU\nLSLG+HDSNdoAiNs1f3tnFKzWrG1FtnIfrf1EYIeOGypQppvFumfH6Ak0eHB1BLSNJ4R9yU/tx9D5\nCagKiy7eh2YMXYYEU1VMIfd8Kc6P1OJo8PU0lCll5KXRxPpv8x3tLhjFDvmxd/ItWpHkrFouMg8Q\nySMqYgT3NwVzdzIm9hPd7LnrqVGsaXnhKH3lHPzOms+zQmXtKo5k9sDblIBPUoCtgGc2Da7H+Ms8\nWnvCf6rrZD1Eeh8MAy6+9lZhwxvgQYP6cDkNcUMSi1Y1zZZVk8PrJdOWsRAC8Lv77kFGV0Yas2BH\nsZyXB+yeiWBowqGByluM4arIWrYK8MgAidM8igYifhS3Fy/9pTZyS878xwwgIpYadc/ry4CqaUpj\nRy3KG6pf/VfWC94FP/dDYS3hY9QIeSJTCSLrj+Ahtvv4wkU9+onFXSwaM+99nk5BNCIxPZnEvG9W\niSyPnSSCSLXySg4SXxDS8xuAa/v7ki4CLOsCCdxmYG8oayc/zqsbxV38kBbMnCf/nolP/PX9a5pN\nMM1XrKc/1gXU2w4QziIIpyEtlrZNuvS1o71UsPw4WlytogRFT+sK16+X0UfeGkliopUWAv0U9pm6\n+mGeKB2oZvbt6f7EqRTw0mvbikqqTS45IuugX0ODGlWfALbi+UI0OfjArIEaoJa60JWUHJ3JjW12\nOC1oYbs4KcyAbP9MmkRII9eO6arq9j3r9XY0/JG/t6AvuiptICCtpmgZG1VaOWtHiaJp7t6MaIqr\npDHUL+D51xgr20sJthEDE+ONij9TqCVdBuFoIt0WKpcW/kE3GJU0ULLlvivzt6Bum+cpY59MfyRi\n4dgGIi9rh9Z6boO/cLmGmLCnVaLw5kbuERrbmMw69UERtCdQeBrPylXiAuhBmFY7kuwW38egZTav\n91qd6jm2bgaTWf8DGS1lf4Wo8FbBOhed9PHEQrro7sJpXQtLBIx00KydxxMruvPvxSr2R9unCo+C\n1xluNwPdiFPDv2VUuHy8gndaMUd9T0sAfajVbQ4LjgZPj9gL6G9lQelfgNRJmjC3tnOt1hX1c//o\nAIFR+9n9m2CIzr5CFBhE8VSFaLQnQUjWOUljt54JOoOwQqJfK3hTkDqunKtdWguDEOzOE1idhsUG\nZ8059UOD6RyjnRjg1v4PBJI1p5a3FjAFcoM89kd15WydIvPRlhV0SQAGQkTn/GbB+mMksWXLeAWm\nG6vkwxH6O7u4IWJ5HImrYJxZrISY7EMXNdOuzfskCqtBribLfKTJHzk8jRCqwKjHA9M49k/g5Nhv\n4RS6Za0A8DjAgjEANPtcGvFkLNJVaO1TIJbW5+X1OmWwpv6z1sV6jGKG/hlswZhyW4J5EZRziu/K\nl9d0epheKlpg4khqPI7gRQJbXcOPrNgCiHC4BOeuXgVa3VAl4LSlE7uTu0WLmzkoHxH28dyqp2M9\n1psH0SJqEpNG1FwRZcnRaNdKXjIrEAqxCTU4Dd4ZzJSySyvwB0lE8+1GxRbapddj3zhw54nQc7cp\n97BTb/Rym5OmfOifieKB2/14M7oD7I0HFgB/8P2NJMMFBzoC9aszfLhsx56uZ83Q33VDoDB2k4m6\njr3uRABI61imi1Z7dRqC35GrL0qMpy9kSZiphp/au+U5J6OV6pJosS35z6SrwpDBHJwbU+u2S07C\nIoylBmvk4A6Ivxs0OwtgJPZSaoPH20g+IN22WIER9r2Y2ujDurnToDQDpCaGG33Tc3AJ/6VYcref\n9So4kz00XQggRLGjvjAup2W4Otz1nJZeutOpcZqyeK/qFNP75MZSHvUNEOcjsrV375n/fB8ZsAI4\nHvnJ4AqPdfWWxidDkNEXRbESccIrbD5PgRIz45MsFkZgW06LrmzjmjPR601WUTRKYDS2W/VmwBPR\nwjY64zfZW3TfP6NyhRogtBkQ7bPx4VLR1GIyyuk4Gzux0j7PHg7QsG2MTwzooIXUncF9WS4tGptu\nIq0o/Vfessp5MNrYR1n2INpz5qZexjWNC1cnDMCY7pMtDluqS5T3Jzz+5cF5brOLUWhzPBlJH4uB\nzHoEWGt1o54Jyy60QR53m6GsDQFdb2+YVfCWfE6TXlbfQpOzbLbjJhNacbePd6MZCoEFH71FLCky\nTMCRDIEg4WACXTe5f2PGwbRE89+PWnvU35pIP+bYlG3/t1Xofp/dNoBHKvmfpybTI/TxhuCWmPgY\nRmKUhTlkbr/zJTHXLgcaprWTuSK0OTvkplhjTcinm4PesYzTfl4i3TUxFonv+83kgp4uVdJbAey0\nvKrbVpXZyPU7DxdlWI7+1WNd2IK5BcTQWyVBFhiednIOaxT3OpEe44KhwxEBqnvYT1A8mgwiXR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f1/Uq96VN2WVK5EExjAZe7s6uyal/Et4K3omAnk0TV9E0WGUp5ti9FOD+iumbFfTDES+hNRc\nJgrC5qPDPzL/Y4FueLb2xg3NvllZsAdHODvmpkdxw0Mqli3tlnDTrkjpajEMjnp2PY1C2cnYWgMp\n8ihSXL5iOx/8U8W4FghaoCdL7nvTJ+p3YJjTv4RRW5ho+lqovghyP0IxQanZXSJDVyQ3MoJh1XwW\nNCfKNfkp31ZFrC51/IfFAll0lYfhgyBjuZRWPfsWEZHlUij+mFN1AALKhF1IzGJop/YNMZtZp5Zs\nAtrWTWaDonSL+f+EuMpMkvIHGzBJziq5MvDSGX/CzE19+LhdiXzpf9tj1/C3Q7X2H8jdx7XwFC8y\nTyxYxc8LxZ5JVnnJucbCIH9ySVDyrH3JAQWYl7wO/7dKT4l2DvFZ8qb8TBfvLVMSiOCILeG2E49O\nZJHGrLn5QA+NYHgkajyGVFiKNekU/49dOAz1O1vSmmEu3Cfmtl0oYfqg9nCzoGhQ+BAtXAb19B3r\nUqsMlazbE1Cev4nU0mWPByMIfFz7H1f5vmbCrFzgh4yAZ+GdAi41WXHKFzYLzPk0ye3NpHGNIsdD\ncS5h9DTaeotSe5E+8dc5ClzeVyyEzb6Q+HUtJ8M4IHd27UxGBLTM5SPcEGOv6FH1T5F3vzYUSysp\nFTq5JFK2TGG+cMQBohqTK6FEE54UntFqXWCiaD+xpPTSLwRfrd6vBrcEVdKnovCO30nDdNKjJ9Sg\nznHqQHKkOCQx181cQ+0zqgzyJo3Xk4MNB5ykA4uNTC1S34rpxZqyjbOCSvTg0VHa48iVnShFDalU\nvlaQGJMO35+515lMfu0qnh/osFnZhEj0TyiC255TcAVZtZrE7eRYVDD21XZDOCUjy0AwHi+vmEwn\n/MoP//e8cHMCfxIJYmFvI0Zu5dOOF85EAL2bsutcbs9hVWHtGmkedS8re+SCM/CGGTpkRvQTkZ8j\nQnMWkMa653N9ZMRkFtg8+gc6AZaob9bXnfxpQo0yZglzohiOBpJCfbkesc2y3VmH6svGKydtAeqj\njVmue3VvCXko8wGRnBRfvUUN8JOe5TQAW6e0VBdkWmZ0n9jTxI1/Re2jgj9ZqBBpk/YfJJgQwHcC\nfCjH8/j0W/UFswUNVrr0Y2ntvHWHJfyFO3V12ixzwDNs5YMC5CTDyPNM4KaSPG1jHVmKEnUs34Or\nxLxT177GXydg9/udU6qQKuWmzRVl0AL7ElxyDpvOOTPt5lPJU5BrtL2Z0OyrdEeX4Jl/ZTWQT02+\nd4Cc+WWmIK80c4uqLKJ4jvya3fPuylC6KLx6UCx9Xr5tOFtSERSQANOOG0q2h8Qyn6M/EV6HLCp+\nhUYFXwQt//FuxGmKmbxFdFnf67c+qRdpcIAQaceLBjPPbdN+h8z3g5wrbQgEyvurksp/jXVrOXI1\nEVELkUaqKyhm00f6gX78Tk9nTITkJp2yEdDZonlw8V5cjtiR8s0qp/34DaeS/Ku0sXZ05NUD97+f\n7b7uy0cuw1+gVZfPzgopoqpWZHIcBuAItT2h70mfg3rY0KRnABDXIk2ZDYWMQoNHaA2zjk+NZ25/\neLBt9B0kPXm8KRzXyVo6HiCGF4ggO/676hflNDd+8Wpr4vryWp0XaQtwP2r5IJIjfZeYl15RzABY\n7nwTC2cP0zyTxg437zdDicZcmyUjc9QHtiq/+TmS3VunO9P3YwtQ+7AznwSjWI/dqTxm4mUrk1hl\nR9UZGGqff/lbVur4HYhJCCyj81oYyfDJHuNnU4WreLe0dkEJOqk2jMR+zxPYejZ4n0OtbtiYTgM2\ngMCBfCq6+r1BytQ0WEnEkXAnKTm7gsylPElObyMpA7b7ICdNGe+D4g71CglfzMonv+V+olJg5xUJ\n8rpWrWMxT8OEK482g9DFxendiANIZQGPZaHo+hs93f5mKwYKxfkXx8GHMsGa0DrzOpSKGa9iVrpM\nnZkunhMzuqtAeI6Vx/v3MXBcIARnGhCDVLT8kMkeqcK9LiJCMwuw0Ues7AJIGgJf42uIfxRmYErk\nYEHUrpuoB68KOtV8KeBDEWUT+Sm8uinnrQpSjIf7pLXy/oSJ2QBltM6g0C+BMH1X170JRaX2FM+u\nRxqCJyfukqNvbqy8Rx2GasQepr+t9xCI90H21xgNGCzyytFFVR8nOCzNuEI94RoTF0HJoFJgyi2R\nt3FuPfjnhTaJsPsq2lHra10MeA1KpEXTwiJObUWFpl4BOpPQ4up0qH3KjtIZYW/unmZV35Gw9M0Q\nVieePKlPzpxDm/HetPwStnK+NZxIxe2PPHMk8NIcpcg4rOBZRpxuwoXP8mN+O1yQAi9ICArlGG/I\n0FWgA/d//LhSEh18a1gyOVQT+ZFK40X+lh+IXaf6MRuxhvoW3dg5RPbGRupSldLFyAhsefYiy+zC\n5wP8L6VKxL7FX6d6dJnzHK+kWv7ec4f7E9iUzc3kRVhFl5nsvbd4uweRM1BXwT+c5b21xsWdzO83\nM231hwF13fKyBP1uJeWhpiYDKeT1ZhnDJJCJEOqqkxXwbwaSC2ZXpl1o3FFmcFjKjiBod7fdeEgL\n1EYTl4A//fhIDMTQ8OQ1od44/hJUAQa/vgB2NSvKNjX4q6ohGDfCxoqvjYW55vOwp6unaW8FG9/6\nMrJuWbFAfkDheLVQc9odRtNKKLXEMeOFXLALmPBOA+gBofQH7j9zZB8NSdierDhqZ9CIns1J6OG/\nNmfU4AilR1XEuCoMIdbvFyXa0y7IZffERyzY5YcMAwfqIHHlITvQHXz8qZCTVI4Ht1RIEURI/Ff+\nee1FiJ7H5CvNv3vkmQI7AL7cb3djcfhNWra0lSxFFoOrrZ5XTRcsaPuMyUX49Pago8ROMC53izCj\nLUfU7zeK/pb+so3pmBW80s6rUGA5nmSeH3b192fVjA5z99pSn1rO0uACeZ8wp3uwfzjj66WOVT6s\nXWQHpWbLfn2DW5dsrLkuQ2z9R76u7qZc0vhwr1jUkMIWK2ONUh1Z+gRZF2DK1pvJ3QRVDtgGv7w/\n226pay8Cqj3SY5Hkc8QRj6sOTW0NTCy0NnhbJiybFhTGDLtMbIt1pagUMbpueFyg3EiitBvKuHMa\nDGobWaWWw+MlbiXWRQX4w6qNiAI7cb0uB3tl5mpLNzIUIO2EK25MnFhVgIXF5wa/Vs4JBvKVnjkd\nyNYJAoKEdFh926jHcGUgnSkhNM3+AZMZbza+Tz3AS6iDe+saUMbIGdOcNk36cQxnoYw/JKPS5USA\ntEYvm+V/SQirtektFG/Qovf70y9Gdyp/1Ry6/lErBvpvgfnY19ipuI3EGL0tGlA6lK36eWCoURJS\n8r4q/daScF7H/sxwkHQVtQUWcrvlECm+8wG20yw0LB+3GLR+w6DTqjqfWztrTY1YAAgi7mjMAnPe\nS3ebVrUpoMt7NhhtRSc58HVVQBaGf/DTJ+xbcPPEWAhEm86I9Vf5yAns2XMvVgOwO9erEDO4rezz\nwprgG/L37pWwK2q7Us0stRNzY4ttnoTm5/vAL/HwcvKxgMk8ajkNnnuxrwHNnJp24QpWsxCAtaEj\nUT+PfVEB2q0IkfzgHREYjzdhyF1q/qcxIoD5G9yk5OxKCLdQOmUgUTy4Fyi/A4rnrTDeZlwTLTjl\nG8ggsnqeIynv6GQTvB27cw2qq2Il+CUWVS3Q2MdMmTcmw7eBYeIfDwmOo5IeztpUP+53C0FwOmxL\nflOTOaa6kIZhI/obBdcgDtCPD4JLHwV5B63gWflqg0MjhlskwlmOvnjDSYbHfHiRgGxw4sN58lYK\n/8Bj2I8Udw/LxCVfb7ZwGWct/p1q9OCXBT8Ja0rLtwIJygJwEUh4zpHgerJJuY2DK2cnFgZ+Ac33\nfuYlbRlifhJZdj0hdATkKxTdgf6Lr4TQ/uNoJcLCrEWEDrjpMjJYPmvKNsCaQN3TntU8eDhHb+nv\n57V9i7eeBNNFc2dNKtmdHL4yavLnzCr10f/gGXqoXM/FYzbvEZVf/iWAm3obe6uEZdJUMV+E0lc4\ndzQmIVyOjqEQH3XK3oTIUJMZQsJgsHiqZ0xRukhr2UwPqX8JtGTsdT7r/wKET8OCUANUWvuHvhqK\n6C2pUXgqs4SsN3X09g3YXBk8kpK+OMccYte7bfpElrkl4Ps9UaeCsqbFOO9pCtt88WouipR5dNBm\nbCpLXNV2sIzUiDNzvn6ezlmKMwMeCNLc5dfVBybIjMKeDDFpHJe/YTWgXHy2AXqxfGJf8fvLB1ny\n+k7JkP8QlWf4PftItA96jpmQyO2uinMkWkzcg/rebWoCXWozzaEdCDj9QI2INYshOp6Y4AMr5jEC\nsWTAP6/TIKdL7ERlRXyfuGyBNLsEAyyzPcdHFAK1MfOhJfdvBTZKo3HRwz8TYzeEE9wMQQChfQcq\n/OSsEbBs4awDKqOeLMIQo0vcrf2/U5REJHL1UGupt1jX4GQcgQl2k9COrAwQtUwyezUqU54vPkFr\n4rM6G3p/DeuMjVnSeXzTWb6w2pAuRY8Y0jf6EFJ8a02bmt2yAgHfADNbIv2B2D+8A1EY3EMANBdV\nPg0qrBc66Zr8aRs7rH1ifYUGq45fczcEavqrVz7TM3/xh7xOvfuBcdQUgbjBWJqBJ5l5bsvmPVtr\nyBsgq+VoOJQ8Kdl7nOowHS+A5a+8JugPcrT4bf5jSSAWl5VAJFE3RtI/LD0JixjgmlwdsWevJVn+\n1IEkotWlZeJkI7KAU4X9VIpdXxltZRevzV4vD8I+qGC+wAeNzhv5ZLaxj8GqX9nIr+/JZXeP4sNb\nhpTtaahN4v9WQ9cLDQILZOlbpKQaoMowvDuz5K2P3sm5UIrsmjyLcxOECihTP1ri/UsANM/l8qWe\nuwZnIsFnDYmLdJgWezjF3H2PFEgOQ7SaWhaBAP7BWoqgoHCKQFkID8TYTs5poo/WrLJ3Wd+4xs3I\nuzXsJIFAYlQgIc/5wIFP2eE3gz5PBnO/vXO3ATHAEcTRJMGX+IqEoTlTMxMiJvuqjBtYGE7pYgey\n3dg6i4nM1WZsR3c1jQjmxGGerZLMLuuzxrFlpU9oJwMQylpoURE2CVh1u5euHIjkZdEfu13F+rfV\neVVz8jqcQP/3XpUPowFa0MctsicvjZeB6pPMNe/5PfaDXux4xFGee/ZCZXElJ8nEszueXi+AZIsm\nVeJJ4zX9UvMBe5+6c0YWnuVwqp9dMkaLJyXXdABMSOehE9HNT5sSYV06L8UvBC5ndPv3oeMbYZtG\nXeRT8KCrjN8s3F4NL23SWEZ6gerNIY3AEBLh4XsrkwaxsR4NTRHIPHBMHzrIMDygQ/IbTZsbdrBx\n/x5MXBYH+BFhjOlP0r8uCD6EX7Y3nLT8dLLH9aKVTwss6icU2OLx1Y6k8p3YqOU4s4Vvclmjxc7m\nMVsqBdCNQE75rZx117UttDwnkyF3Q0UEAakCuwce2+uTYbm72gTrKufHeW0s+MMrqKJoQ/9Hzj3Q\nTPtJa/ZuyTpvDxVPMeZgxj/7TA3Ugn2/V1zB+WyK7qxLy2YNhWLZOJx4YyWcvcRBvcj0z++D0Enu\n/j7kk+i9xLqiucS4aAknnT3Vl06aUVK7dJganKJYPGCxowMSUW1GirNUR2cyP04d91YW/BkcVVY9\nPP8BKkiSBuRutQvYG+eVJ8TqIYTczQUHKVnwxJdKBfQr/tCE7c+BhGfAbH6ZglCAjdJCnDF8Iznq\nlR9z8ZvhjTFFHnclKWjfM1PnYjFlSOngku30p8pdQeGD1u3lW3EoL5IgcB1FvnnGGcMYOJRPR7EK\nxWukdC7MZbY05Pft+K8dAbM9R6vHFsYM3ezXZ30WN491e6rplMieB71wLDMrP9RFkh55hqn9pPMU\nBJSTfLMWJShEVClHvoZy28AxQ1Co0AD1YS0yh0Aw8NetSsazDHZyu3TZkKk8yRHCe4Rt4LqKwj5F\nZPms/tK1YLAYomWQt1k7ycVJxKQPeOGGP8On6FkdN6IyqJKc/rDyq3/YD6s1hBi3dGPPpe+JAwz+\nAHYDTvm1H1bWpppY/kaXClAz8FNiDKTjAc9Yv7CsXaX331J7EzKuf1Q1ClT+x8LpfPHZLPexO1Sh\nYN4ceMmYXjq/+o/AZ5UCHTKIru0daH+MGJTnLH9Xau/uL2QNhRnU+c/3DbVYccLMGRy6GclHo1tW\nd+A8MwoYSrqwB+egtrblEFngtKkz5vbawcLRHcGfrUalaimmWNpj10t1TB+qGWwpjWo5eOg7tGY0\nqMdjFbMVH3Jop6WcDY2rTIwxaMT4VJL8JNKYWtABYlQPrJQ15K7hAmY35LzzSZ5cEwrDb3k6arhK\n4NOO0MVJsf+MSiki+dxMtoR07jrHhtDOsAPWWeoj8CUpii2eps1QaAzs9PiTAsQ5qIO5ybEZ/cul\nsb5/S6CedWyuKUVqqUN+wu9OpDKoQYDVzwacu1gcaZbGToSSXHJoqif2q5Ua9G0A9OQ0MUFHQxdj\nwG6LfGzpsPhRGspRMmGNDA5yDTvmwY7ufSUETRZWl1Dola0Smksofhp3DjyE4q6CAnbCPMKLLlEp\n8qwPzxFCDGBtvYcwKRXDxBi/+qs+JL9Tixz83fyFWIdUtSjLOZ/S7HKObw7zhqjHihsvU2X/N9ep\n6xrbMySZJAVA2S4kF80ohKuSZ+iqkHXvS4VA+A1afGHzo7SP4MSaLryDJDOKwWiWBHmLqa7c2xHh\nnlxSagfJIQasmq2V5MABfNIvGl8TWkj/eOzTQOOSNiCFOnFbM7xdfFCyw7Z3dUzhRyy4E5T1Fz0W\n+DZzmzItHOq37Ucm/nFbQnzGQPXERtVtzkWW0/ggauIzmFL/i+aPsx1dEuDv2Vza2KkBpeR8+u9H\n/F5SdRtYbTtHMPVUrZjDLF9pklKlmWA0n8Nhbw+w/W8+riVdtZsCuvtfMMu2yz8cWiZaFjUCZi6f\nbmWVVmE9FuyZV6qRLHyPiKL13XRz68IgdjyNBN6hPNKPj/58xLl/t0zxvdQ3Vtll1GFZfHmw31pk\n2+g3rfEZylfuKXY4vcRkI+IFos4OHt4VXlb3GUwYfg6JDFSd9XkVODz69hLVisCWj4s4Vmi8VQlB\ng0NTwC+tG+u8q+LEkbmKebE7C5F3B65wLY2RrDAX68LzgsumE02pKv/fqIXCKEgzQfmczSxzeWoa\nmYw+pMLLBgchH7KN08Q1ivXgp+EKqt3vVloY/3+yHhhvzsY7k0TYvhH6iKrWTkEQ0EB6OV9Jjl/E\nMCN6POom40Iq3QvMXCryCYs5CMkfISeqfild42gPpV/waXXSbqIwR1pfVIMJicbUPNYG/kUDl6WQ\nDHWJ1JH0Qhif9mh90IlLPnKSjiU6N6kewlVvcn4ZwX2JAupxVQhHF/rpw8v1uK2mendLG9H9eeSl\ncvpWHJl3p5qpaBCrCwyWoJQp4u+E1p2m1FHO6XcoU0WOxF4kHFNC9YAHP6vNjYppz82xmMKxje20\n9fb+5ds46L1vLQZAXvyQ3TSpN9I3EotPyOUlQEbYJLo5NLvEtN6jOuDGj6VzfirFXlCPYy8p1ojj\ntm/UO9ecjBlhvuxfibOZTehIxoK1cMJuzcm3QejU1xSGKremESnBFAUiuG4WazyI/WJEfYrc6ajV\noG39jS/jCGRO3fqWXoiUU56Qs0gQEojGBEW0GJtSV5spEETiehnS4qBS+Z4AJ6bDdsBtEbwsdIw5\nOyhv9RjUGzXR0RobNyLhV3qCrcxmUyuyFW3V5YCgebaojuaJ5+r+9FM5/PmDaOOS0jBf6+jagT9u\n4BCNon3q71UPkyP5P2OjBDOxpQS8oVqAJz2IVeSfl/o3pNekUw4rgOhQnKgkCDRK73vDrVR75gwG\n8+Weivt15FGgJ3QHmMcBcNrIfsXHHqNe5K9Yyn94Hua5OMPatEYgf3otlydwg8rOZyG6ReqYYKFT\nhU8CtppQzbARkBRJNWV3BjeFQ2yMrkuPGcK+hUSO6VODGlACf4PME2jrQVVrUt5IVvP412fDLxyn\n5LDNCreF3nauMV18ZY5a9FSFSTN9uGDSDs9T+Ta4pyp62lpWQ9bNIze0XUoEWmUyQg0sjyeKZEPg\nb+er1y12GD4INFnARkCGL6nh0i4+KX0XYjBed5aNMNsiV1qtzGFwtdRkhC3V1hU9fB9o4N2d48tj\no/RgHoxyTReDje7Lb5TJvWn6ze/F0ftQVO9LqCK0kxtslpIOoCTuoe/y10B45WCj5OtHmyGW/LYh\nY2JmjvQsdo2+2ry+sifGv5s3j8hik7SWn4Qg6eJy0iuSjRIFMf1SEyvc5JRnP5cHmdutYFefQpbh\n0p5QEbVn2oeNfSRuQZ9da6ZY+IvM4QWUeJ18QtbLjisExDsg3txDbmJTAV33/fIZfht6mLolkrXy\naadKYZDcx1XKHCFxco6hmjQrcVP6ITkT17F3onrTe5YCPPAPcBW6vJIpbR1UENthDgSmMakNDwYq\nZab1qBIbknbUyp7mIIKQtaRny9BpJBIPpauzSs9R1mKHuji0E+fVSYAV9i5EJI/+xksbVyw5yT9Q\not4HdwTw3e8SA9PAVoC9PXdlNb5wXf96LXcQnGCQ7ahPqYLpCWQsUsVFMBLPfQLWw0M76TuXhhGg\nw5P2gRG7SoEFYhkJziZK/znavBouLycKdVECmqKtDU/Lb0GQGDVYJfGGVXl6RMC65V7jYx/OW2kz\nfXSTEFpql4DN2pmkbmUj8nhDmhwG4Esud+aARBOAqp9CpCEFn/xkfQZBWe9iWGJP2xqRYRMapVxB\nrXNMERp6TFPuVmjCtZ4uL1CtRRoI8cr/1a7o1teO8WyygLGG4FO2vj8V4a3eOcje9wFVUVT4M6yp\n0/4P/UWAxM9jKlZrWq4yMQNWclTXZzNTyYIv0Rx2/qscVL9UIlGiQkmrDE5+RZ9Yr5BIJwG4LoNo\n6NuYz6ug6uDQ/ydgsyr7559JnLlQlShjCvVrw9uE6T4HTukAWykVw48vihYpYtvqpbC/B2usZJm9\njv+KR70xs68O8aev1hRg67QWiYhJMME20kBcT3QUhcq8LWMN04bDCHz2eh0woONTDv93B6OlpT3p\nc42+dlLVgFTtllQa7BT4qRwxs6CRFt1VzV+fqyh2KeNsNHe26IkVOZeVtVihCwhVKrSWNyL3LnNQ\nWNX8F0asxX71dTPk2a9bewQirYm9l4T3fgtsmO4BmqBUfnJlvLVadR00tg9pQVbIysBrr4EPRChz\nJyAtdjQynSmqBTtxaniYVmmsSJqrGQA6LsQk0p+LuD6A7w3AWY80wbOG9S+XFe23FZWdVBKojimm\n78SK6O1smbwuNI2JH1zupbsDYIyHEwj6ULg37o420FF9AaibWH6GKYFIEyudlWfFHbnAY4ec2m4w\n9rXov5YAQvvXTDUbWTQ2mpcVPu0zk3FByRZ3KpVgfwCLrlLFqQ6AwyxjSMDeX4mGAfSx1vn927N6\nhlp5d0XE7qeNbBK8eCJeBaKVZvVEu4l10YqYviabsYn/HU/vQdvSbaLb98aYNjSVaphlWU+D6NA7\n+L/ZGlHGII9I9Nb6kIM0KV0++g02mreTUvhLBV4GuHeEZUIJzj/Sc4yy/VpGdY78A2PDTfBgRiD1\nnp8kXoGkssZKk7yUWFp3ywqockk6R8q2GUwNCDjvvr/aJxteYgonH+O6/2ZetHVqmzfGvJjgBOk1\nV0d32L2P2sjObGXaa/ijPcNENDEC02TynmBEzLPIcnIc7gT/HaR1WQrlaahdBVtlNSXWHgJvRZPi\nSwNe+CgEdtSThZKj6CsALVhEStKqYtXdvNRiqVHb+yHnHJT4RDTJdknFRXiUISbG/m2pj9TK6svf\nHCReDmkFcHCjWsGNuUvUkg4m5AabYTH7TJjjbMZA7OtyCJLxvih1qUK0P/4I1p+xUIiYQN8WvtUn\nusrydxMvAzYG58tWl9Btr3T1YzZFqQ1/aq/NZPgR+bfowHXA577J1ABIMW3MbnIRmM/evf8S911u\nuOKHbWHZ/C6szT/zBVjSHTfakrOkjCTl15q9SJSMIitdY+bo05UsOFXboJLi7/6y0oXKSkpn83GE\nrhKKNuILSUXBPBOFZJTihsOwZo/9xB9uxD0A3gkEd/A05RT2cA6+jylmnWuJUO1QQtZgM/NyHg91\nIIJlARIk/exKsg9Z/twpf8sMXkiPm1i1J82DaXxEeXJXcy0hnAgXy7Hh+gtVZQfFH15zAoQwxbmi\nldiENS+qlWk/UVPeqilCXlrEOZKEzhk+aTg1mMdGXSbrY+EpqRqoVtKk+WtNnbm22EfS7TlsuJWV\npxqeL2Dh04042nV976N4ukCXQ5Qr+6YiUxZ6dQ1nV/JsAIVTL+yJDrQSFJIcChLRGSBPYEw2IHVR\nmo3AavaC9HAxDbbUoMZvV2C2w3R5DctMJRppdhD27y0REQnKdUIdEDWV79RHfFzmq/QgphCaIJnC\n/UK7E1uuFq0AK2DP3kFTDddwkRZzBLbUHL1Gu5RivT1mbfwgsmX7uVoxWhSu8NPlt31tRjqbT1hN\neeidR1ROCAR07a+NizryOZHunvPW9MzD0b5/OV5XTG+jfWSZqblIacNpJwU6rmjkF8DWPXn1LRMA\nZcNqdH9hyHXKdrB62zuwl3GGzK/RJujim/QZMkMAEb6aJK7vtK2vV1eaIGErsSPSJlbF2uymHOOn\nMQaiZuyMomzvCrtoWZlOuI7RXZl80tw6yUDJiczir+L9wIZSK2qJ01Fip3tIdnxxYhdm4ehzBX6M\ntewxpbzln/zpIXJEz2mCzW8GW4vaS/rSdVyBx0f4ZlZyNIDe9ECBQMOAGx9USznIrET6cz4WufUd\nb6NLjU65vG970HXYhQdStBMnnpD5uNZwxwUAMXsUaq5o76ofBv/ajjjG/Vp1lSIhAwgYuD+EHoWC\n6DMmHbHoa7RxORClykLoRIK2vYCXqn7GbYI8u0aZhlFOl9d3fMT12v6XZUpMW6oDzcEQ0byFgCWk\nDF3w3iMPOGKqrW17jCFNkx7qrhTGCEX/ug8bbNkegLOMy9teglLRs9/wg8/cocSxJuVp5Ek60JkZ\ni7d73hHR6k/n2JQZmgqg9JqHjJ1u6sDYsDbo0pPSJ+NoR1Om6ZWxsZitFexzpiWUhVMUmHjlV9Ux\nTYzlsBWQPFs6sX7Lka9pK5zywHBYgyZK7A9CeX7SMqYGtzSQioBGixzGG1bwK6MMuWlAyM8p0xTe\ngpMjtIildlX6BdJhN2J7kLeylJBixUz0iYRzeXAlqESe15jF0hKDLk9NPw2Eb+3+silx91LjPu66\np35Am8EG8XLUQ+hahMXXUwWtT2h4S0kpw0DzsPTq6Xft6iBEUaQ4bk8P5eq7cPeBlRapxe65AdVF\nUZWDhLvbNH8IlFf7EEceU5Hhm4hdheCFS1D4d1tzNg4CNL0LnXZ1Xg9V74HhlcoKA15lsbOuS2Ij\nnlkwab1H+/vUFrTUnbGt5gg2J20N4lEULbOQ6NhoGbs9hhFLDiyy+jguzr651frBD1eB/bHq1mDT\nx5dC0m/Jzgd0ZQb2fMwXC4mRB1kNBAdQuh3VPKNAqQeLqJMi3c3l5AhdriVX/smtQCYN5W43Z8nH\nSGUpGbGsS5sb/AdE1XYu/hQd34Das0sOVffSiYntLHjiFB6ct63H3h08ADoKdwyv1Jm4b3GIfvyn\nvOX0yVoaQUhzDRN3K8gWHQBbXBm12yPo9Ouhd+1GGJ351mCLZA+1/g8HMbunpj0+95r7dSJzcVW3\nRl7GwgsxXawk4JTgpvH6E+xyRoXOwJ8XD7WnkGYJCVLlW3ZHd5OAifW5byETZwKFrWno19tq6a74\nWEgq8ApscihVsBCJb5QuPrHNlSb5uoa/yFDSU1RxoAr3NW4qtT7G42JsjrrebY5Vm20eccil/wa+\n1tiNC6bPlc+BO3tsVH5USlYkxpxr1vSlDLqR412+u8EGWmpUP0qaw/mExLM527rKGei57dXSuUHO\nrDqtLAabd++zeBMF28E/MyzENvRhfq3dtmkutVEt91jO5o7A5uQ6FrbSyGax0W3DbhwOhXQnN7oF\nVaadQyaViaLCPIT/h4+TRuCrhqFx3NFZDIYe87lQ9zOCsiMBMrsk6gq7fRpTzmIraBXfoJ+wWpBz\nRbS1WbEKnuoO6DxGqSp7C7eBQwfspAiAUfdZ5LuznsG+cSHBekL9O1NHeynzfNIyvxbfO/JlqxBO\ne/Zs+z9dc9Y4Tmi8PYh2xrp4lY89zzHLceX+ToDk8l4I8Jl0R5vxzYeWHKzsaEFCEJXXaoV+KooR\nUpWJgBamiVR8rAEQciqdzaSrgoiMVR0s8rHj/EM/hfS7LLIQzUIKAgZcyn2Nc25eZahSPgJAKznm\ntLVnwKetBPKtzyGitSGyL6g4DD5jcAekkhyK0QHZBj6h1FXZhDp6RVhHmRztPkS0ZCIqRN+PMlOM\nuE/lqBA+zkdPPFPTiC0IOavLXiBs6z05G6vLRUolUAhfQkK0RHdwYrJnSzwDaU78VL1c9d9s1o2X\n18MhEwB5WquqQChrkvkhThR9WcvS1IGHrZOIzvV4noA9QqCpAIW37q11yX58TOCrixsPSDJVJzY4\nH0tVBLdh7uwvk5u3EEkFhccH2/FEimbj8v9/5/z8o6vvFCTAPzZwBhv0pxinfQVyXkoM9Q98PBjp\nK5JJcYDW8oMxNBwjC2g5hIivaeP8qm4FVhngjKXtSGW3ox/rhqlqngtFakaJjemU3PSK5F3Fs8LU\nq7XKpgt60H/ic6QbV+HC8Fo/gaDi16EijwIba/FX+fg86VfIyDB9+HVFxDrUyicSLI6h9jZ5SXIp\ndGNbmRXZqWzkE/coiLsJZ0EzMsUtqdQgmYP8F73ArnGjrotPARurx3OnskatQpCMkTXcJQQSFteb\neiGsXQ7wse7Asp+wTe0G5KmJHSr1ZiScUYph1QTTqSOBL76ICftwYCaORqqJwOQQFNdx/ploJbMq\nOUUMyJGLhMT00Svv0pUw67L04nzL9FVFbkZRCrDcXm7wUi4dko6u4midaN9lQCNsuFx+UjCTKOuM\nuzd6es0/6xJAzHKL41c77okWSsJSDWV2pN9pGJMWkilPb7c2IZXsqx3qCvXN1Dbw4dl+8MZ74r54\nwTBbv2Lw+ZzUCh/tnG5mE4IPcfcPdI6XZkff4ndp33b6Wboxid8CWx8jubsi+2BEyj6J7DJjC6o8\nwSxmv35i0i5cEU7mmrIWs9vRIICCfXgucifL4xUFMvKB7Yh25Rm7UgbyxUAJ1BHSLyUBC6ewedkY\nHpzaE+VkicH9sl29+unhY356DMcihDc5fRFFbYgWmk6v2Cr2brcCUXcJNsdRBxVbuQFt+H0RFX8W\ngWccQ/xk52nWEW30gCFkHHu7xzF/yA8qH7k1gcvnQ4fFYRNUVHctPUfivPwfNAFf2Kw9EwH+g50c\nShN0YFnwZEBeSnnSxpIeZ5b35GpH9BFov+ouPBiFqs6oJcrYdczGOl449XOnAw6ut77ioeGn8L0j\nfCD41DR30jzuwkfjvWiet3YC7xbbJwCBEk95FmLnnaJ9idwHYr1LZdJCOwNapAuT25T2PgTl8on1\nkwURHVdTGwZdUD3oJGtdf+tLKnx60w9Qg0WdgRSKyqJrXUndlXGLv9z2ofpvG4G4TpOeZvhGoKRI\n1gbqJgIaJlheuNI0jeiQBTe0c1KU/e4EiVk7hzTYpZpIc+34j+4LGzCQhtaU/QlC94u+GKPjmyPC\nq3/+PmOfhjhAFl3yKdCHTTTFklnSMVGU47QRhN9p0EClAJeFWP1u7/iwlyM2NKE0QLPwOJGq7Hbh\nbpHLLVzpUogpdbFJCWYrPeFLqVpaLdpF5wd6MqQ24IaUHiGFijdBPw30aYceJRSczPva9hNZ+783\nk8ZaeVctnDBaCRPsou17PQ4C164NowshOMoQlliL80YKKCb16th1B9g5MWv5m6P8qebinMSZF961\nK40B+5/NIWjr3zP9ODj+bf8YpUiU127Rh0LQfResiwrDYiQtxhI4WD8zX/8KC0MFhr4ctZQmkZ1g\ny7zT7L+ZT7Ku1GdSJkdd6LwcxBZ2qC9CMAvPH48KJ58g91OhQ5WQx243z11q8xXvpvi61Uh5JLNP\nKYVt8IHa+Gkv0IzuL8WJ69ypfWJZ75TgU1E6dzNZ9j9YkK6tNtlSSBY5XUSPCkcas1Z9K+lx+tC2\nNjbUtWp8DbaWbflRbJ/7LL5zM8wZdOgZesRDiaX8bho/aZB3BncVmEtdCKaozPHFBCrFAaVx7gJh\nqfLk6zJrDZJkPiJL2bYKZZUTpjK7+6KiF6Rf3XjIpW1TYolGIK8hgQJTVNORP7RNQHYkx3I9UocX\n/+/hRSOaJygEDK26y0lCGsndjC2CbQISVB3ZMxIe4L31gfqKraiISOXi+7pFRdi2Z6OdbZpFHn9R\nTTmvRnjB8NTCiSCYKX5xFw9gnwuIrXYl4l1ZthQAbx7pIGyMqjmvCocKUYusDgZxZyReUVp1SQDd\nAqQZsMSzAz2t0rSZnsybmDC7g9zNmW7GzAR2Ek4Uy0W7rcaQfQN33TCDhKEpq9Uqcm7HfSV4Ldyg\nA5SOBolp/wkBWBNPtzEHRIW1ocUL6rNGIfhxf83zT1coDg5MGfZ/tfV3Q2My4jHtNolFX8Ue0T4X\n63DaskeiikHNj3Q6d296aEfmEIEYH8zwWHK5rMPIMaJEQzKRL8eetBHir+HicC21d8sVupY7uW7E\ncfsi0GAXpklpLeuslLq5Exs81NmBbeoJM+KMe1vKIZcowkxwHeI8lH7l7bubVrJaCYb69jDt/YBG\nRkRcJi5mAXCBU4w/LegepTqXSf3pvTNzhk7uBAHfMUFh+qrf1GJuTJPtV2s9It8sdZ/Ewz5pGhe9\nmPkyIp4BFHg+RkboLRiIEa78NDucxecBBeoGfb90BFwxg8JAmF22ECdWKKEI8dSUy5NzLtMAeXMm\n6grQYf9Ny5o2IBrgJ0U17cfUCOqQn698kjHVM6uRHLRpPu7q/EoBNDzvVaiEN0SFkFZfo7agYPYw\nQLLVrBFg0R0W9J/eoIwjahxe0rrq+Z8QZN3I0GpGQC2UlPh+Bzg6mn8AtMmCXwL+fZQuZCpVMZGY\n5JTJ50WxRnv+VtGg8yajt/YyRqqV6B/urXnkTE+Ay2fm1M/MSF0FOuCAwrztyut5WIWHEdUZGqvI\nLi3qTPpr3LWl6yIQtrDdPaFLudT0ofAWeyZZVdH6rH+i7z58v/zJbA8TK/GacME/QzTF1rGKaE11\njh2KKl4+g9e5tN9OfQDAdOxxxql8BWA7qD4AddSUZui7mF7GATSmfzLimkH0GG0H4a7bRR6Jaagu\ni9ahyoSfiEzRKOpF/3Lps6Yr0h22XS3B0+D6a19D7FrbsCIHSDJS5wNh2nSY3caT2lQb5qwNiD1P\ndd6GjnnA53b8nReQLjrC+n2Egg7kUNyc6dkVKnv5FaYhxAlk9VtFowoonI7/xGOJ2/dQ28vBZP5/\nSXSv+WE6IpPdqzmYE9+/dvFZRlx7AiCh3WoU9mOfYQ9eYFWW5kjMnzN2l2Qp9eGFQp1HR0mT9I6N\ncE1moedoSd+fHCGuWH7cT01lTqkLcmJstkJ/lDp9DVIM2sADy2pkHv2rEEGXXcy8y7tfcNE9UXfQ\n3qO63MZX+XwsZMuRC9/yFSrP+dg34fn/4dGxQba+Hg7SPfUEpT70U4iZ7eEaYv9IjtwF3kQNzCgt\nDSis+iio3EW9xDYZfOar9r62IgIb6iXUW/kL5BP47LlTsyGAPYb+G5KzPczHu0e89H0NChzpc/yR\nliwWZ5FQ0tgFQogS9kaDv1ci3bCSBbK4fNWfp68hKRxcnpQglyUSRzqRstE1y1H8RpO53HQu9FSO\nm1uN79ZhqyFlLSGO0pIDRo+fC4sqmRH/6m7GUZxBf5SGnwc8XsNXT/7sVFyqFadkrxGIe5+IbX3H\nKd01VXwvfiHde2uq6cikJPIw7sygu9vPtpLg1oZmPv4+DxiQ2krYkl+qcBj71yO7xjc5M008NDyC\nUB0GJl3hddXnYiE0Dqh1vKdBCwHqwXCi5FoReah7+oWMZG/VfaAVA/E5HObwLlFaMNrhSLCfHIZ7\nbLQTvHipps/ZzUZskZMuivSwaHz8iJ4RYdmcpGbnCxMrpR3NF3rfa8zhgIgfJI9/HZAWeL3Jmr0r\nVLVNp1AkRxaAXXrXBPsTV8D1tSEjEhbZoACI2mZs6usfAQC62GSBuDZTWQGa2cN7CzU0Wdzxmn2q\ndW3hCoAcLCiSEZbcg3cG1W36fVGYXaDHt++AjF/JnEGNc6l48lFM5aE/szofn6HXKlYVSaleSBtV\nHkhlOpL26lMHd2P8OmPNa/vSeHq7o0Wgjdg1FpCCL+Xp2jYt9Mfqlatr8wtJmM13exJugfwJcLYD\neG6s+z+9dTyS2mbqfL0slrm7XRNaii2b8hn53NGL/A0bvfMi4LEKRcylH1SuPYUb2KlB6mXOKUFw\nWD7euysZk848ceeLCtyswk+n7ZwAlwIvCPtUt0osh0U/2rz3Wuk8UUCPsR/NX7I1IJXfIBq+heuq\noC1W32auIbdg3oG/vK91xOybey67OsfLhtb85wefwebMeUwQyfWwy0rCjt50GnXjvDeH2RmGXbgK\nPBra/kFh5gvtnhdSBI/xe7wdOAL/6t1PIzQwC8ahneTYIbMLds7NISHyMwDrE9HXPsaOUnlOcdyg\n7p2694dLuYdwqZXjRNZ/lBqfkm5uWyLvacNB5tb/R7GZeFDwp1MqopvQw8w+EUuPqFa+HRF69jVH\nUx/N1Cym4+fnuuCDhfsNqJ4hHeWdGccn9PRvbBSOce8GlJ/Oe89h0BJrJkIcza+nxp4RTp1ZY+J3\n1oaYEaRKJAag5M5LrC27z7hXvfdb7qqQ3+sROAfBrm0xptByYzSnyfDQm3fu7hfgrusBbRVzvTJ5\nGVqaEsCvsWtMqbjXmCZzUP2Pcf9kepigJ7fjoVWLcZLCnN3VZjQxflcRqcMnh3zhPXz4SACSEuJB\nhp6nCrmfY0Vl532fpx0ITtMli+BGIItnUlK0+nyofv+tRgFPioWw+wh2gOfu/rtXaIPCQI7/mG3Z\nL6Q8IQBYsyveCdzqSFYgW3KqJUURvPCTm8qPEsz/c41ketWw4KupYqo3byADqP4DP9B6wwmUiesf\nGVa2YwKdwdWM1cxjYcrbrcjdiD7oAiR+0O6sJxQBM7iXJ9NqFQUOfkuLVNWTB8B14GZN9XxsjguN\nZ1h6gsx+4uJB0XaGL4j47SfPTizEfSB5tkPmpkKNnW6kN3OEtXTP1+ILmQ9OEH6wjq2u14ZI4NnS\nYVsQxlfdLWTK9/j4SFyTUWYzuVkQ0lojq4/Uly6fMbA4JNq7hZRxeOmlBYkZE/8IdBYL+jGUc3hn\ns+BIeect59xDYJRCE9N00sQBIvCTy5U6Vo0QpMXR5qf4wE5pGUx7PntkZ3xNNmK9G2mdvN9VA4oK\n38mDlkj7QG6Bf2EhrMIah+bFdHDfVIOrJBUGBKKT/R1zijabXsFOMI+c2uZNj5o4g2P6tHHh+aO0\nfj1+fG4X16/CnKTnGYoq1jZqvMP+7vsUZQT8l3k3qbGJQgrXp3zz0j9+OLaEXgdyxztfpGpwTlCV\nhqjuiQCFratxqnV8yI52Aj7kpLa7gVrh9kQ16Aw/e2NT1VsQRfZ0n4DB4xij2AGq4m35pqCFPj7Y\nfqOat0b6eeQLZ/7ttO+t1/N7d+ljdZ7tQEp4VtnRs5IdGHNBx58ojKBTSSu2QdUcTX3igptAkKP6\nWG0bfvcR4DdwHgiyh7x70MnOtsYpyiNaokM/lIok2KgaCNxvcCqA8yaRVJVkrp9m7twm3rFOO3XG\nMw2huCVe3Rlw4yEKluuul6yc9kSkaCQKsvy2ubx3ifsh3iV3y0r/TJa43IDjER4Lv7xIW6jErXev\nlMZyiX2dveAID5DdaluRQDYEaTbuTx65egrge4Aqfxe94c1lr0qFg4nUyY+ken71eZ8sl1d1Xah/\ncquxnKUsos6f3zMhS6jdahQiwmOfmGL3/DjlloM6/k/qNK+xXzyXqKivK5Vo0/kgqaCltiRXNbUi\nSocAbeqwR8iodxTYqirDmmoYuN8AZAyn/FGIjuM3IYQLalYa/qbiU51XFUJw0vNUcfEDw4BEMC4c\nTWV2MyimfMxNrAUNE2TwPp1WUVM5dP83MKbP1KAUE4oy5/x1YBlwTWoAgmJ78MIp2pJBeIK06USZ\naS290vtLmlLGsIHn0X4vqVJu0ENrvA9LXo8CnUK4QtKWJD0D72DcQ/paLjY2UscjjavxhWW74Ewp\nyGUQwVsdKr3LAhdYfWBayNBFgho/Vl40OyAi5qF3fs/eQ9n8KJGFCxR+jKfWRJPuwOy5+zYLJWJK\nP/R67zIgZTLAGar+IKX+cYmnix2JYa5jh3G7VOXPfPce19PKTvX27iw8KrnZP6icTcWAtjFjaxeA\nGYbjOMXrYNSV8CTS2NS7FmdfEi8nKkO9xGlplc44SEVQvUEBVqpzZrw7PyaM2X+jzeDe+mkqmsvO\nGTuUCbbqH1sJ8ehKdihcjivHqZQ6gP7WQB7MTtsPeSZYSR1SYPZAbBdMHRvQPyuKcBpMtBM/6kzv\nREnFiuOJ3zWl64EfuYzkLliSbI/UwyCFzgCQ09RenKSXVKezpmlXlio87fbI6syRRcmZYj3FwlHt\nWcQPvlpzfsmLIFtKrtvTOK55Jnfm9xm3zXLKV77vx+TdWDnQ6gK8lQb7pArFmXxDboZeMgAC7ao6\nUeE7mLR2htAVouLTxxsvkXHVVoezumUyYEghHUvDibRHdYhTeH9kfZWr/1L1Xar8xdUbtQ57oTQE\n/87cZ+RQMPmtRQ+dbgCp+hZt1vaciB+D9He7GYobzMAkDYnh7WPD08UlGJTsG88LvyJ51UJsBInK\njkHTtAVkEeoe6e+jEDM94PVDGcS0SuHFF0bujwKhvSykwIhgWICmAP0KulA2yhn3l5ZuM/k/zHCq\nMw21NpcD3Mx4EaJHGPpna0UQKwka5yovG/XFzH3hE8K3P/ZcxvOPAUXOqr5DMXU+YyuEWCyDv6is\n+WQpPj3HuJaSkL96Glo4Nv69kF5rnZrpTcIMPf1wJUalX0AY+TZNjzp0+7eIxfiSSuD1Ejpzn/MQ\n7Ml2SshOk8WmOyUTW0q70LKf5cG7VL0FHNAeXkYlCLZW0a0V70olseBMS/OXcX9l91N9oJzuDMxj\n8wsPvPVcd4oTtNZzHDyTwCtNsAszh61Epy5gSir7+7VfxaTvgy5psRP3TyvNvcGcsTDBX2XHh/eY\nZfaU/j154GgdWj8eKXKAIs+gC4geVGo8S6DuMjub3ao90sM7KgfjwSIS9Cv21nhbezBl1d6EGkr+\nXp0NkFobTbVcWy2n3RSbNnA8QmZh/lrsXXvS4/jM6vuSK1CrErASrobcSMZCmcptMzCSOf4nzBHv\nDql0T6KiXIAxYO3J8d3QYS13LsNwr4RdHQSvPqKiAkzRaEHYQC/WBiYwDcV26WjUZeLJTnZ0rGCv\ny2+7Mrng4pPPt3ZTePSvqEcTJ4gon1R200QunS5JFxHWWJswIeHSbCewwLIoNXy5s/qOzKxCGh3g\nyqKVSw9lgpjLI/BfsBsv2IXewN0qGApykjou+7bMF7SlsuN3/Y1ilgoTZZoLTzyi8UwbKJVQW3ut\nOJ8uDPeSh77LvJfWT/SrBDN5MaAgmrzMjMYZMhSgexe/XCJE5rbFrj0VoyRkDupJJVyviX2Eqvph\nu6aa5/Fc2uJT2KfkZOoCUn7Iqq8TIHBR+OqAKNBsUWynI+iTiKCfO0ZZIEMFmcyWj52sdZRtP/iU\n78jFhKiOtpNIa9VhX+qHJJmLgbnT8OPT9HqguGb24EUqnpH0J5sPIk8XD/K4uiIwj1HDGDnQzVey\n9qEY3xF38PVWmvU19qtv6Djlj0F3rocjUfJhBVE7pFhKL43I4XUpYWSQUCC77cdJTQFXrvq9O+Fn\n7jPxvIYqGImGWk6DbmHdJ6wSgmWWvzD7DyFJ9bWqpQbstAIaQaB8KFRpcmli4iWzUiVtTJqFEd/o\n1GdNwfSe5W7I8aH7yoRKHVu1QeuJQtdqrbZkTZfz/Tu3fXN+R7KgVnwKakGTOsjqJG96Ug9TwIxN\n7fHYEoFyCjUcWXr7RvG2bq4EJuc6UmsSMsRY8SoKVhDR1XAYvPJdttZkiYU4U+1R8AiekisdkdfF\nHNqQMWqWTjzYWTvclYPa/jhfFjoNGHysC7lAPqRxz1XN6jLD8jOhFUF318HTLh/d9zoOeVvuEuQJ\n3kyy9k/iVGbfHV5R1xpf0x1REZN/G16TL9IxTTg7P8u0w/ZB1pFXUBxHQisCDuLkaAYfxmnCKgk5\nuliD1DIpOLZYFY/hu7tyI5jtLTns9uLnm1WkqhJ0rGBKEG9o/m6rM3pprEIptGV053u9Rst9ncdu\n6u4WqOuRM60VGB750HKypmaKOddWx8CJEc3oUOpBUpDnF9qRI5Xe6ygS7U19ccz1AVeflQGf6AF6\nqQ3yIE3VGPsdgs+4eWZtTYT/+akCD/oCVt8yKXNKupwBp4bXFh6wSsyhiZbwQqfesigrv8PmLnsz\niA/a9nzlzvjxXIn6RJTo1d/QWSr/lYLdPSHCVmFw/ca/F9EdqQLbvkeW8EHJS59XQDtEsF98TaFl\ngTse4/nEyXXnNXQsRCDgZNTxcLlPr2EbC4qQKfQIMU0/4HW+0sRJ/PTSgPJy4LyQVwDsIdwO2TW7\nKfaKzL+1mTjmh1NkFoAgBlvU8NS7QCtO2tXNrjcEa4hcBfpV4u1Q+ChqRwEuDX/A0zAVGLwAChhX\nPu+/qN0K8dIpvmKvHxVeWjUp+SQq4al8YRFSYqQfRUlQE9s4lmR38a4YC2GWv63eBTs/qN2TeJCl\nopfpsUxLW9bdL6Ne50jzMeM97oFowc7xxGxjxUI7QvaOnPPXRnwexliqckxbpjwcBghDq702YvMm\nlLUUlhbiIsD6fWDPnSORnrT2EF5gK1Gy6UpgjQSAz9HAVG/mh0cJXq8oDbwf1hlFJW4eC+2xu41r\n8/9nBYOwcwEz3OeEIIGKpwS8p9vnVI3mGW36o/+5Fp0tqCKssofKB0xh0+qIG76/pEGv6CVUdDNU\nJLizq3B7y9k3bOYrWcukCobcJmFpRc378b1SJIY7IBDnX1na0NyKtnD02S+1cuetgEY/lq0jAIE+\ngXycNWDo2KmMEiUOvy+dgT/QgvIoU4PufLj2y4RfASoGw72n9jT76PooS7ndN7P9rPTFukxu4epS\nZ1aUEeuZmF2CJ7bSiuXXkEmGpffq2vkxetjW4Tx2ShFlW2sEnnIZAjrDh3+WiVvRDpHV7KBc/NqV\noXgooWeNpIAfHP6CTOwBfLE4BVPCWoxHkJiDU+WC0lWixmMfwxjV+713CD+egqbU+bsngi4Yy0Q0\nAG4Voua2oJMQNoj5qHV7WvluMl4ZUhSe6NA0sKwVD14oQiUnGLqsizwyXwdHQc6dYUFLwo3doV94\nZcGEMHsEJrkmWUP34jkGaVDI7AQBv+hPTM8dZbhY+2e1lii7NsJJVHZcZN2ptXexHOynX2z1bVFs\nu6BEvmEJezajPndbB40LrYdiZEpUN28g30ZtAei5zlCxOrHWOkjs7yrpVCNlJ0XTQvvDNDfHExNN\nnMX9GFj4dhJugQDglt15lhe0EfDofcePBQysQhshIDHJe2hnWzVZFhE/c0DZdOCXxRWgT//1d73D\n3gfSwWvw5+AYBwBpjg1HBFUzyQp6pNmjOiiE507lR8JF/w2pe53CBbvAj2rsmywIzDLIbSwo3/Q5\nqP2AKmBKYuaGuridrwcoe35huDSN02M6gYtnLz6TT7TWVWEWJ8c/fBlo/xXPluri6zBgIcD7GH82\nXD4qX0cEjIZr83hF6HRb0afaeDF4e8cZoP7na0/0v5q8PLYCiRonu/YIg66j3GXGFG9nffSaW3bc\nIsizgR//2rawH3Zc7DCm6ZScANoNt8w/DpOLInV8uwc77hkqn4mLC0+jirLGiEkzwxLMUlXhHmLY\nCfLia5PNLaRmIXqC4BWBJXxETqyKClp3waOFS1335sgRuUSlz70tHocXER16eXv5vvjvX0qf1Q8E\n4FEoeyptvEwp0unBcH2dwwP8ajNQsDVz1d6fsU5zDHgfO3O+OQE17JFUNuf7SrCMe5r5LCAUmFWs\n8XRlyFEUNkHaySSIe6bcVBizFWpVyVOIKaYDMah5sp/3Bee0CqxN0d9IkULmfkrkFYSNepfjp8be\nZ/s1MyThZW8VZu/Gu+VlzUaSet/1JdxC+/BqR1vzTGb2n3XSAKTl5s7csJJBPkENanZ7k5E18KRP\nwfIhY7trRQb0FVFOiHK8uH1Y3tVzx7m+7UBNKEkOgFLUwZNE8mv6aW0kYF6MD0adP7Rzg7LCK4Cz\nN3VLheIA+W5L2uRH2y20zEn0RkimNlMwWpyZlAzA/4Z3FFmOjclcl0OgNI1WvpdK0IEuPlIglku7\nszO+wm2+2FJZ5TIsfRCO5HzENpdmLZyuFBZoasRbpgZM+7WEyLtCeuyuAQWAkzsndqnARH0/GlDO\nSA/QcdbyVnd5wVOibU9JbhCGI+mVXN+0YhuykZIs4oaAGzX5YJ5NlNcX6xoHcaS3mJXCOgKVIguH\nnxa6hb0YtQuwReoIqgueXQPqqlbhJAMRNbwy8fbzutzaQfP8ivV6BpaULHKu+9OrIFghuug/M5h1\nJYueo2Hyw0aOJ1MnT86+aTCgkOw/HipaCaWvMLw5E0IiQO6AJRUUHKCIfQua/fqboKP6oPcvRiTC\nfWoGnKVLEnrjlcb5v2B6hx7xCMqeDXVPoejN48ImHKDhAV8XHj7MBs4/2uB0FIV/L1Hf/xn+P8nt\ngvYfOG4dO/y0ilbzj3/zOR+3+tYJUU7oS2i/YfCd9papwiz2fuZQ3IVDf+N0dlB1b0E2nrWJbUod\ntqWl6rXNcSt17x5TIKKAJppTXInXmwE4t6CyCfNKaUbRaCuI8RznVxE4NuYa440S4dyfZ3CWKovn\novM166J96Tr4Tevl0dC0fHYJYv0fZwh2fSkZQwzDUNXmGSZOWZP5dqv1pJCp5idbGm1k3afnxrIL\nkYhVWYP33cRpf6Qr/Vf5Bb+k++rvhvuRqOGkUplaG5lqWz2DwHCi8nhANq0Azf/zAH9AN3Snw+4b\naiBA1OVf8G+ab4BYPTnvstfOfST9W3vm+AwbG9lKOtWX/w4fO79OP7Q2pq9RdT7jkxYZbLLxDFcC\n/h0k1fsoHdLpTSRBae7XdnYyBcoIxqzqLnPrb+6D2P/guOuWIbdjw9wQblE/FxQCOwbN2wgMwZ53\npLUadKbLNgC3VlYnb1uZyplMOkR83K2SXjbWKT7U8smwilkqMZ3FUNk6Vdmc5S0XllCtPxr6eJKX\nSSddzxsvdoUoWqNriqrQCMfm0fqg71bksYdnnbDp65zya7jCH4v0m6sN7co1RleX1UzFM/oZmjy8\npSkvpIDfiIueep8ehBCi3Tp83qafHLeOrl+vEVNTd6WbduaAFhsEhauH1bdzCyM8oju/hhHVTICv\nFQ/QW6FQbZrDUJn9sn9+FwiFQR6HR0rogM8sgxaGEek5VCI12u2eqhHBdGajWpm4wMAx70c/PuFV\nBn0tFF6OAQWUf8+l2wP2Yg5LTy7bUs01p4/OxbWYi/SV0+sBjGjBnlSBaB4auh7614xNDHY8Fk7o\nuwM03z3JQdJk+CEw+QrAQySR5DpzKTHu8TsmEi2WkuAmpO8qV8Gnrb7d3+30Ev25zJxygMUDJKAy\nFOpAuj8WsKImbqn/w7BG/HOMWHQ0S8q1q59Pt4D6kwghvVouae8vj1HnPHSR340t9fLuH3+BRpkm\nDzNRpMwcYcJ5UdG9EgAycsPn1iAW4y6OAlfNK2J24aV0ubCFxoztdvk9OouuMdFEHRCeBg5yFF+P\nPYzDv3muXyXyn2UMOlcHahy8+d1gcQ9O5ZpS7xuhdLA3lcyXZchaPFmxxAOibvxmCBgiiOQKfyVd\nD/eX8iKUoyV0pgt0Xal6udEAlXPHJLp7/vxo5hI9fJcR7uos1bTklpFkPO0JvCvcsTtP8ZFudfR1\nEFgnAnQpn0NuSVKobED4+8q4OlROgZbhoRjSBDCl20hnTTHNk9CrU4uPAar9BvAeKxVWCGpSawuh\nJxi6teBd4OXXL1m3f59KooGGHDhzFjQq/HBCLO2ZXsWexmHxlm0wKkf2ThLuaZPJPtA/mxdqzPXv\nwa8qirk5e8K/Ty3YVJMa2/Nl6Ssurano8S6OKvqntA0zg2gLNH2qpsU23QdIVX9SNENjFnkdzMCi\nTYF58O/AQXAAB+ILNVfHnyGIeaXFabNZrQSYmz4DI+101Mwg9VPN2OOcUOFDroo1nHez7AitoCT6\nR7CA/T4cL8C3unAM0CUl4HYvDHI6J72zMfImM4u490B2T4D6iCsWCs1l7DCcnwgta8a/gbvfk9I8\n6tPwjgpZpBhyRaGyuwB3lIbOSqNpz2T0vnf8nss5N6yaKiil+tuaTWugIqL9V0gcbD+KttCIlmGs\n/hoFz/8r8Vb73p/174vCn2oh3UN4OX5wPLRoRYJLK+zldSFAPdHtMwslUza4VsUM3FcCoMehA70K\nWrI2Zb3EScdG1j6+ncV/nfctjpncp2aM/lGb8fB3hy7+NE2ICaVOpdDSf9RLJgfI7Qswk/o3d6uu\nKN1H9EqqYu0QJcBsKHidbiFEziJY/+gxWA1UsF/xcUerQQtAYdoW1NA0iS8T1uA3McGHHcsOyBD6\n4Mv5kwUhOn/e+GnW5ArfN+I3Nd1LHEXX8DCR/wRImdHJ2uYl2GEKln478fWLijVJU7q46KKTCXQE\nJFg/TVlIVipfdpbFs9ls7yFBpvI69nayzqjlEnPwEzjXapgGY28YFOwy9ABoBaeYOouAu/h6OBtS\nmAe8EL4DVi9uiQlP90nyrgi/Rw7YajPxtKNTx6RpEpRAwvqsXL3OZiLeIF9I9pVNDa5ON2b4dXPZ\nGOjkaROX9siUailCS7J5lnMzT64uSaIXB+kFeX4mgv1nQTt5sDwSZPXwCFj9IlMJV4zQkln5n80r\n68PLWTCZfz4FxwoQWLLsWclVYRwt4P/fbIdBG81sDj8Zk+RLy77sx8+Ph0rJanxH6/BKcaqMBvLV\ng8EMaPO1Lx6fnw25jLbBQ7IrdCqlcDsuDQNgyhdElXKG/Fs/T9yBjA5gqRXT1JuzKs7GhE7Ug7+Q\nFaKJz50GYzo6bgvn+iifgHk73x/tIcg1hNq81Wt63KT2LdcymyZSY6NwPi2EAKLVn+Tok7r6TerT\ntI+cIFP4jP69tnAHBuPMfugp9dGaJxzREZLyr9m2TQP2iHrI58kpJbSJYtpZoxU9et8yXgQTQPWD\nbJxcpqfMfNFe99YZO6wLB7jLVVa/b00PUg/HFe41WxJUubBpNEa/coMyqpIe+B9zm1NEiIjIkDg7\nnw/s8ymCOkowYQVNIo8UcuPsKrD1asXs5wChAG/7tKaAT7XrNodBmaz8VyTvP+Ah+TBs3iLINVXg\nq9wb8VcbUStUYs8UsOPGno/0jMQvUojnocikkv/bYgnPcr8JrWVNau9sbnq9qxiUu/m2/ADmijpL\noKkECIkR4rFKPLE5VgPrH2V08L+XGK5NRTrQsHdW2dpogQPdh6tOExphQLD6nR48y0fcCnemWcEV\nRPV2tCC/LteHVG9ypU2hwO/t90DYccxKn/WJA453qvXWpYCLFZT+Il5fASwc3Mr+jkIxfR2h+KQs\npddVdyHoVEAS5aaO2QRKoItY+noJENmPrOc3oReHqRNUZ7yk4i/1V0mPS0whkA9mQ3afZvnRR62P\nAMm4dyeEqPKs7dI7q4ftrNOKpXfvTybWWvIayjOn1qK/JJB5KXLrG27uDJQnz6W+3cobfI7b1gGw\nY6hs7CrTtwmkwD7gRZmf/qoVJ/t/pTHAW4qXylCL9i0T+pZO2eK/mF1q85skRLlVgopxPu1S2eya\n7C8o33sXLExsHQmFATPh4GK66KPPBCfZ9zOqOB8PRs6GVqHQ6eAZ30GZxqYxNiVk3JxTA5cNQO5Y\nTbTpbYYj0AS99C8pw1LB9CrLcjnyPS9utMGk3twhgZyHX/wZE21bvIcWRQgJuGvUnNQNzW+EAxdf\nE37jwImdDd17S/yXodVMvRq26Usopr9u3Bvrgido/9buQJZJPO5bfzVrxjha9eh1ZH92vwTlYj2L\noHXEOjPUperrTjheQRwu4xwk01bREbFpTPBI4Qwl5DzdNYurBuFNW00KbFzsUEqZGK34MKIPsTBW\nJEdg+Bz2OfJNXAHbtVVWcAlWbKONbuJj0KaHC5/BTxMLGXOkc+jRGvRtriwYzFZZieCUwt1J4stj\naAxAP4uW22zixfVZ+V9ADUOFc04mPu1WYt/MEdZga/kZbf0f0DKKvvk27K7BKheGva5RRMePL7b9\nmXN4VP+8jS5OGpihIopCape5ncmd5+Yi92gFhXnPC8vfvO2BHIYmXXgTZA2WjIStXOqtu1tXJ62l\ngBsaczQqRMe6Ib1bWuKcDcj/saAJ8HuE1vX4tBE5cROggtOVPhgxRLnXNMTGZ4eLURdcZibL/qGJ\nAFGE2dB2zLq++O+zxJ/aFEz1CTnsDI6M3uW45lfUmlwXET4sdMGPz/nHIMOUs8OXxPbZkbQpfg4M\nXwx2T0ydcePcLf/pZVBcXoA1vH0ZekkBRTCHQE61BYikdj/3B/wg8YSKipVD8J/sFdWuwY1F44Qy\n0Qq89YHpowwH+689uL7I8JS1F3rb8rHKgGHOMZsz0SU70iOALd8Wu7TGylyr1Y7iFARUeuNHGVFL\nEmGHSB3YBBcugr7bbQteWYKatv8Ke+j1Oei/7LMIXHh9NWNs0jtTP+41NTlVwgMjgsAK18df43oM\nRH+ljr5ooEgq7sRX+5IOhzXAyc/ghTv4sPmCyAt7e2jTOKRYgVoL5ihOzNvWr34H8232drIX58/J\nYQId81zUlSh+5lFObUu/tXRR2YoXOSO0BcHmUb6+U2ZYqlc3t9lhp6FfWovNWIogLk/8NdJbc7mK\n+fJ0yTf2iDp4drl2hooSW+/+jrnFGd3dK5A88kjcbKs+LmiG5YPXxm3FSn/YDYoyNCX6/ophCxr3\nDZ0uzFpi9N6WBI9BV5tqUuADB+6M7aC7M//bRTr1QnwJS2Q2AO0ZiVhlNuQlcInbAQMcarjNJqml\nEY3MqR2mKz4tTnqAE9fwq7Ou2T3LQswKFyWWzuLuUfwr7IFJ2LbABshzk6eFJI+vdGa7F0wjhYrd\n/Dn1oZVasrfNpcBJjd3l3eHalVSy4+lh/r+/hA5ba+CNFvEkf1snYJcqwRzHmcE9GbqESJwfzq5g\nMD0y3ZgGCZ/5Hyzy/k2uwtaz10iZyjriw5smBS0Utf+UupcwSPjajRcBZEsl3kTCpeM9d6ibe8Ty\ncOdHPLpoFN15rqgIXBCgZlIdhhJfuQGjSBLE4IbDoLxoAn/+JOPdDpJQdfSa+y39GfqcScCr7W0l\nxjdo5DLQWDg8sc3p3B/M0Zhp5LyT0rFLM7mOPSBIwl6eXYuB3xX7EjDzlUPuVZ6Qvo1vQ4aKgRm0\npE/b826zJp4CIdzaq1qG2gjr6T+sAiES2lAqlCQQ9SznOQzgp8Drv5UKtvtJ20GX7Qqyxo3H8um4\nAniPOUGs0aP6b/QUZQWap/dhvlEkwPOuqZfkStz2F4n03Zibqw863qhOwp9SogmZwSJsd7OZBc5f\n4u3hQrqhrQg6vaWklU/wzADPUQgZBgojGmDgEo2gqb7UAGZWC3U80jcyJtMqkPxSj5GzidoEujM/\nEV/1NpbDFp7QpYJ/PBG1/T1AioM1Ys7GRtdxN+/ZsPeiusX6eYhZkLkWlogF73fwnfulzqXtNa2W\nahgBoHbgTEKm+envefLSbCmW2VRwkIY/0IMoeADuIi/qZzk7foy4TF5QM4DnWbrQx+ZcHlceubk2\nzg1t+9s8nG0IbQpk4juLv8JUYeeabelX+Bx26oNuFt8u5zy8DepKgxppVIcog1yQxO4O6hKBurft\nH+yFjhriOcIFt4h58xiSlR5Vm1NkBDaLXCuoS6O0Psy8JySN0JkFE/dtEx1EsumUwOgoQKguVVeJ\nhyfY02nVYis0aQGVTO0Au+iDXJwR50IEilZ1I53sUtGuywyx/zAO+dHShxIY6qko3hGeHc7BVsQD\nh4lYHpeLG1BbA/aZMK6pEVH+clTEQLG1Qrkm1DqcOP3YW66WARDy3UNDZk3hx2iNZR0fKHdl1B8n\n+n8w+pTI1gEcVoEklnXUZgBXoVzfSZdHmBv1Rkeqa0a6CmbZiu4oL2ZEh0XjF4QDI5KqfF2olu8F\n6pKBcj0CKN1IQGrhjka5LBNl0IE/gZ+9CDrkCYUxqFyPX7OOdFl+5bRpP93aUGci6ju8m7Q0nCvo\nkTXR4hDjcue0r5HdfB6h9omxjUUDTW5f9Xl/9x0+ExtUM+V0ZMWlkd4Cld87PY5OBGAZXHK7cNzd\nN0xlv1Z8Cww7LsrRlwhRWKX85N5qtPCtcaXE+eQKt/cE69UxDhkGJVimAZqnq+hVPlVD43sFA2pZ\n3sxz8lDsD0X6KAlpzLYI7z8YK3nMrHU1LAGP6pRoFAzO2npCSRwGLq+evEX8DXeT8r7gGFO4ZCFB\nIQMaI1pYWo5mrwlcI85Xy2pBf2J/ADJJSXBqU6Bq+kHzoXPfMkjfyxQEB+lzni5SPgm7FLMmHYY7\ntfeLH4U9OBMhEWHnzByjod5aqBZXtSY//+XC30JHzNAdC006Joo6n2g0QZMWvZ/IS04p0PxmJBjj\nRGIu8clm6uyV1uw0FR3fTq705ELIRrj6PSRMJ2aKuH3A9itwPJd1UQbxxdXHAYScUZ/WzOnvQ2dN\ns7uWWp9nvG4A3P22B3Ui8yDO5HFjJl3THBgsjo5H6TEB/qdhp+Lr5U0RmwnxcqT+zhsVn+5RqNqF\nSTrBPAAefHzIiPLvKUNzEqlnaCrCfJE+ngRhtKWJSM1PdJjw8UrN+DxWHY2vgAb6fc6i1OpfFK0x\nfGrR++W1B14UYGSGacBa2TmXUhWLYVRNXqiJ2NVHv3LPYGzFwQgoL0yY+ag3wP6HNzD+0cbssYS9\nwdnTLZmZZhSy+P1F5beaXHl5RhHSSXIue8sdlyqu34qY4YCXHee5dawUQNeNhzdjl5g/2HvM2TN4\nIy3q6/EL3WMsfGI12DIRkgPZVMpMffyh+rqrxmZr+JCfbeytnZ08i+sY/bFKHYhsZaBE8Sx6GCPg\n2eZbH+yaAx8qK41DDZlZqDeKx7wnGzCoid2r+bASTDQjWpkDiMHsAVui0c1OudfrR56wHomZ9yiW\nHouG6P8QeiWmJjd9A18H+olaVDkzv3ETzbLDzSZnhKIqrlQ+u2s+L8u6aHwY7WsTDIk0oy1Nf+H1\nSAoHtdaNmvNwD1Gq+CZvU15tD7mUFSFK30eRuJszJrd3U0jNywQXj7ZyDGI4iMVjX2jA1fpY517Z\njaXdBJjJfcKQBxU+ER+Q19Praywvufplcx52jVY7rnBfwNOJCE+nyP9cRUQ0VGG1tUqgnXRiEUVf\nFzV421XO+Z9pYVPbZmvv0+NxEmhsW3+bxOGEbKZuoM7CDdzZebu2zJdDTKZ212IBidfqz9Z42Jx9\nSIJp0FQfnIiSJRzCHf4jz+z/3KqBRM/05GK0MPWsVE8DFwwMkc9CWSuYfGFHG9iHgTDkpdOIXA3l\naNjDWufJDefhZg+Oeg5AXUFa5JEo3nh+TEB09XMIvImD1gxwVcbvMAagFNVZhRMobThfDFlW4PPg\ncwINiBd8tIF6Js5D2vzcK7qTxWe+pMx7CsuZL5HjGwm2G+JEs/hkLkXO30dSfPgoTul6kydZdsLd\njYXYT9TyUOYlus+ri5M6SWFgr31K87M87sm9a6xl02sLwg3XFHTu+V/1/awNSzql41/lMrzZOV+Q\n+oFXigB7JYG2tFaj+eAd4yu3LZ2Xv7nDn1TcqjpdSAC5HDxQWXvem4CDnI1XGvOCJZu+/d54ELED\n2ViHmo4xtMkbtcdUJ4BfxuoCmvJYdrKFQzYKVczqlIksw/Y2AQXOiu5e5wpfzLcW/D8dyWSGiZ+8\nGIoUP7gz/rqju9ybJ8bMnJVPTCEBP+Vtw3ebaXoT+QH56880dIS4XxusoHBpqZ41gJo3L9kR3rSs\nLXFT47IXLpTpHOAiOIA7nBNEhEfxBACfv+1h6Wv2Ml1xKB3tiaIIEaOxLdQ2Tw9eN/TVIc6D09jq\nwBVsO2eodx29+EnsNBlbWyYL4R6G5mc5m6miXdwKdpFVDS0YsEsAgWUBwIwJCdwZ8PsMC1R33fnL\n4hhxVMXIB8mTxSMCTMo2U4QJ6QSWABVsW45P1GjAmLa8kp2mR/I8x7IDJPVLu3q0wc2vkK5aOuIS\nlLToRxpiekE7VBk8ykDOvu7gupJHCDM5qvZXmTx7Vk7bJrcqolvo2ifU3DAbN6QQG7QXTex8FYOk\nvAHWUE4FCtsRMqka2JKSqNTTvyRBY7jYeKvo+O5IJhNYfx1iY0zR2XrgAfORSVG6NsJH3Jfz8TSe\ntDm1kh49aNU0nTo8C0ly8nilWHZuFexXI1ZrhWnki+Yp0w4nYCC3s29DyW5tfzkmGDngHkXR3XXx\nnLaLNyvyql/hMrK6zluOwM1/HxgE7k01X5Nh1ZiH7PpadypgT6YZk2+BQmhnnxHzC8Rt9WWMbCSK\ngylpOq6ejmhSggwXM8YAe1h5PR2+RfqoYsxMHxDXDRjTEQ/1X2/MbD2EzZ8909G4hdaQlkS2nGrT\noVZ8mpbBuC1a6P6MkoIp3ur575pw8fdG9sV3vDRZrArtvAp4yjSxm9l/d4l3mcQgqm/4hZ4BsSAv\n1+7jkw1lpZ/XYNfJwnF0In3NwEs5zgIAfrXi+ihAJJZeApaoIrP7UWI/NtW3a0t5Ll0sy56/bCyg\nb2BiqIim7m6Le4EiFRaaqdEHkhVUMAtx11d8IdW7V2SUk6yEuwz0J91jHuGTEPXtZ86m9AzB+xSl\njRbEh8eCIW0kTDWEA1hHrHNAg2AA6SNlqAK/29MyOz/CKhYc0Cq5P+zEWprkT3n0xqHpQLwBN+xl\nTeOt2yzmIlky27OYQbYdcC7LN6ICfixDixcp9+n/yvQ2QlKID9yzKyc0AOrXeyb8NFc3KAaaHoex\nn+WfAJUn04uZY1qkXI86+MYOHtVSMBRdI4IqjsTFrStJqn/Tp7bYF1FORQyQbCGHd6X1wdJOgsWF\ntN6/Gn9mUXxiye1/DpbX2wPBgGrAr9UFpGiQLevnoAvxe/xVDtdjQ9qyjRNvyp6ekKnZ9mXLwoqB\nyx9fb4x44UZZ29Y89BW22SPuUhW1+AXRN4BWUGS2gRWEA+p3axH5dUal8B/lnZE4aF4z9hndWcNl\n89NFS5zDbflAMGzz0m4I8RJirQ43lDBEhyDk6wD6RtAC6KeBEIWc90HoT0C1GHuc/Q/81SEZfwi+\nx0d8zCb3wXORM4axlej21dJSMNNkDnEuYkCQuR524osytqyiI2oCIdEch2OYoiokRuhZSRXi0Fu8\nu1hLGHRUH7DeqaL12aObgfiXgQa4bDcgJALDWiPOcbmXDPQWWZb7D3WSlcoAWWVVdLBR2aTMBhkY\ne3yLC163gQuVOmdblq/B+NSmq5IhFrZZUT20Nxbz4ee/zqmidFitgdnS1z2h8xZpJC3W8YvCAwdL\n+IF/0ZhVGe1n6eWLT4EjQ4sPQknSRtETUciDaP5xfaXt/R5dfWCEg07yxmNpkwwRfNzGGugo1y/r\nURoiq4fHhs0GGZQK9j8SA40Zf7bqayRzKbBDZqQRVjAn8F+CtHkjcZcdacGMypzHwBBRV85rzPHr\nSQj+J1izomqxwMoyoPWkWEUCMxItRhBLsD8+CLa3xy4JmyBIsdeMszJwcFuMm40RJmLUQpR47hV8\nAhQA7lbJHJ1kNbF4HdmY4ipldK6aTg61wJEiisVlurBX4xR7O/YfQZdILkMRXsWO4IkaAvwZQm9X\nH1YzpINXhh9osZhPC2yR74ZJeNZgP/JPPF1/57+UbqPwqIIeQLRoI1Cqj/RR0+S2gALCc3VrxpxQ\nvREdH12arGztF+24qQibnYUIw5d5dDpm93fbXMnuqXGms/9WmItH6Rh3lHe/QFINI51svZkFvS6Q\n2oYR7AFIOmv8KDp1Bscw1jBfqDVjuu6W/Gxsq4yGWgzwwRyctG7nYmQ4xAFGUIZ5GwfeWbIMqsl0\nGSQot+2yxXQBT/YKarPRqq3IuSrKXpVp3peyCR30a/bEDbtOaPqC/wIVTGcyQFky6bMHl5eCC0OG\nU3NyjOHI//YbAYxS1F2T318F+cqFsV/Vt3Ih7EVPurwZtjZfT7gXCapPkIFq2NU3BL3YLoEet1x8\nna9ORdd0UM3eeVmOFvXb84yq7c8kcVAGYzkJZHcUcj8vVTzxd7BlGkPA223OQR1aN6psjS40ml26\njpBi53vqJf8Qwpht+6wDN1pFjF4Ot5GcEMO5iW8GyOyEHs4aXa0ij9+7BsU7g/eZTFubGko0kBvK\nkn+0vLyhsYCv+amPxTz59akZGU58qT28ZfyWxptNka7GT2tck6FgqiaLp0h5f3ZTdl8PEWSkUzz/\npcDVat5na5TyGI9d+EbOwdS7ejYcTqd6q1mIu5DrTjDtYccXC1mR4lBoBsBY7WCpTKYeTVSuNwoF\nsv8U7jl+u5npyglNIyclnlV031M/mef/jsXdb8sxQnQup/Q297qJBH3WbT0VCEQ2DwWHyIEhBQLX\nLxUh4xIlqJYSR2yfjlruVQETyq/75QEkd7dH42a8uusKyrMpRTPONims0x3R9DM+D5/xqnbJ77k7\nvg7KJl11GnVNP6pvwbopAs4o6tz6xssBnNDN5poTcTCDqPFtsp3xv/qVlLcwZpsNliNdNzyS7S2R\nysd3H2CMrMfkfpgWnOF6ttV4bWtNjVkuBLLD6ShiWbJjXWlV2rYNKjtmQrbzQaPIkLo3z9VDNGH+\nipVWAtpe4kpQEpmJUyJnz7XWMip35IRaptPbq6NjN5B281sVsfnPOmJmWUMK9lhCFFu0WXiBO7UL\nGXLgyJALkVgnrirNkP+jghjvrU+d7Ahzaft9GgL4u0EyY4oL2NHWGyznJMGd1mkukidGWW7rR7Hk\ndRbwhi1ziD+WTa9kWsdASmH4PTrrEY9WfUyMyh13rod5Xzu0XLNYmt+s/ic3zSjRnhN2wY7OaQV1\nB1DWbMdKjeuL8vGXE8yhVSEFK6ocNmMSOVLvT1VAGW7w0Dup3ox8QOraZzSu6cQz1OEqoluptJlV\n4Azyo1FK+v2fzuXpo9DCeOy6OZPx+ZzKOp4uzXwG+9en6YF1XwLTWiWhFur4qUtQt8UuztXOyOOS\ntFjVif+G2oeGewBik/p5/Y5+QKqX1yvesttQ9bmRe1y9lVpUak12NHSkZoeYrGStqVsb50KE0UYk\n7kwm99ydr0x+XhpQGAB0yWdVacmOa0RnoAww1X14SfTe+/5pRfbF5GSpwsrlV+ZD2QO925mrzeap\nCBpnQDuTMd9dEKLaN3oWd2zHNOGD37fez2d988y+cCwzNnWRmsK9bTndK7QxXyxkqPJ8MuoLF8e0\nuECHhjNMDXiDKl5WN96kdN4o0dtDWCnr0S9baza/2ohzp9zCFlYIsJKPEKYmKkTZm6rBbCxuVj6Z\nXaWvIgH5t1ntm3AOHod4/cbphpnl3LuXUFEhEIClV6oYQUgo0suSGjimp73E+1mZSNvGZg95j05v\nkS5jsWHMBPDsS0F4xY+BfEjqRb37Kbboidxo5z2C7vmwTMcOpwTz/sVgk7r5iYXZN/Q/NS31NHM/\nwDEJ6c6n1Bubw7tE88iduc5+9Emqyzoew84JUdF4Rk85x19Oi/B2faHe8jrnseaJKeLXgGDws8X6\ncsZVH6sYqel7p4RHvLBfncHEqVNXYiaQZI0qSuaKy2jbj+RZ5ap7bEJ3q4DosL+ITbK+iiCXRO71\nHM9K3OxDiAw0IlBWC4UUFavC+yEzgJB707ofkD6YK7+f2ywQL3V7sJ5O7PWa7byAi2JTPGJa1cuZ\n1o2RAhAuOjku3rWsCnLBnyRCsRZeFW6whvPdgyTICARVdRnSXUbY+STVeOYgPxuFIXm0Mz3AL5l6\nHP1bv4wxDBxx/87m0i1evWGZCGDPvCUHsqihGTma4A8dRBxIHAdfgEBnxyHGf2JYiRHSHfTVWCO6\nygtxL/c+AZoN2jjdFJOL7v+ibpCeTMg3Mr5KB6BWwsP/cQRMvpx9hrbloMDkVygOyIAhnjF7AEJW\nrM+1J7RQRtQ/FMBtx/jCooXg00NfqJtkX//MXFiymhORw1VqY6Dlei0rTPn1hkZBW0936nrgLlSA\nQ/zLcoozr+C8pPLz2uiGUGVcFm9r2If7kHObpq19TS2FPbAJWXUS66n4p644d4VD7SMxUoAOGk9Z\nXF+tQaWkM51W+LaVGuJJjcAhedO+Ff3OkCNbjHdNDmFbd4YcoUFyiV3120s/n6VlRIUvPmltFDiU\nqJx7b6WI+EsedHD0BKfWHmWIEc9CCFGE5pwmpRqD7Pywded1k3X69pLUONxjNr3dcIB/uOXzLVeq\nzyeAthjTvz/hSAZD59i36wQnqXMCLheF7+E7CA2OzAlTmara/vS/6+JD9NfvhRiO+hJs1G2CBmpL\nhQIvRMJ4P/+Ty2mm+cA0ubxLNArKbRx08QE2lfPItY4Mnsx28FNvGiym6PlhwPD9xUFG7R9xsi16\nahKTRcqbyv+GpTYvtBboskbPI884uuYUX1UchBNnsJv45c0f0AjE3BlpJ5SKPFy5nZQyRreV/kJb\nsJooTIrPrqy6t6GfA8AHrjtSgoP7GJQozMzCsxLsBSWB+Z07M/ZHvXyilp7z0kq7ur/VUfk5ujyA\ncpKFH7HPrdcIT2x7hrSmOKafP7Xz65X7GdeArWw83c7hCbgRBcW/acIaI83e/+08rmwN8vnyWQyT\nV6X+3EyyRAKV87a3OBfB5VcYecqUWBY75C2pJ1n8WxF9s2BJo28L8vx7DWplWQ5xgMNp0LtlHbzl\nNTjy8Lu0W5CvbxGZrkd8rrV+NSdXYNFnc1WEOoIwyFfKMmXccTN2ybJGJiHOmNwrDb3D4dWqdNKU\nwzWRlUFk7LFerDqFzl+l7PepZ1gbVfpiKZ1schXVku/aRQPyfK9hx44RR0Ve/SwCZZJIFjc3rtkP\njGYuYbw4yDwUBC/6bJzPEXSiH4/L442UMQqGspWghSVX/D/24dmmgceKKFTVyB/LYeyuV1GsS2E2\neu7i0B0zwFpGqAyzOGkSY8Yi75r4a9ZFkw6A3Cxw2Sar9e9/tNskgSE13WYPqXiOu1Xh9qTlo34Q\nAIn/qLNQeKPn0i4VwcetrOqPL4dEssyyHUGxNCRwq+xvtW4IzkKwJCfNplnkVrY69FwP176x9bTY\n89SN5Lh3aNMNCE42+CjCsL6ClEA9vLG060EcCHBwmsS9ZazMD2R/nyUt5Ak02ZRbewBa248iSCLB\nwHaspvJwI14w3Fwgto9LTQRCpRnXmT+cFlgOy9iRVw+f9GG0H81BNTj0/xGWMIb13p6cs1usrwC1\nG/8jRi7Rrt1U9hRJF5qROORfCp39EhqO/sK4UItlxO+WbAQsft0RF+Qk/aAExhEmwctqJNB68ggN\nIxLQKTJJrLwHf9Wez4yRyJ+MktsN56innylMxYv9DYTZr3cfxMLn7wWbl5BqOA1u07fcHwyeUskz\nZWMrO85mDo4dCyw2Og2Y0JAEmqWMWWygSN0uMO+pZlNEj4cCOMTsMpcJAabX/0lKmruxhbXfGslp\nN4+cqm6W1nKwOJ8lfA0aeRxZ3kUVsQo3553nKF82ViQA91/hiyH1Y8vSAlHnSKw88sKu/Arh8fN6\nCbPGKkcdt8lvhgekY8yaU/9GIhgDOf0tqvSp8JckIyxf1qAs1GqVPrGF3/C3XjJuwGa6RK940Jwg\nukYvqRkgAku/IinitGVZvqJUDkjI6G3m5lH8tMatHl3Zqsa7HaVxHvICNrwwwtKRiqbc128zJHK4\n6F0MAhVZ7xXbJomuHFkSEBsA4AFyGzCRXiA7Z7hW5dK19HUv+XfJRWNMZHsmXRRm07h2UH4YhcAh\nOmgGGV58QAKGSqRqKdSVqAdX5TfADy8PeCWp66WY+Z9efF/awYIvppVs5Tqle6mqdf4uRBZmRadJ\nUlZek2xa/lVx3BImX27X3cZvx9bNv9ug9id5Eov6NhOfOlpUyzguVp93N3oEkB1rhmr1SDJjXcSD\nXCq3Zz600wkakloxdZoQr4jDO+BNXDOqX5tbRLsojukH9T5k61eJ87cx/MAJ4Ry8VyRBS13ojKOw\nmHdOkgelQ3BhLYctB/ucaUTBwewTvPEcnZGYY6xDkpkmGwGkpAmO4+IsDqIz3DrLDYEyItUhwQpP\nr2Txn+j3pIEzsGu8dgIIBf86EDMMnVzvVPiCCC9HRt+5DzfKapxv+JKSh2BQ8NA41s2NRx/GROOA\n8gPz3a4C6ivZvA51jMQJPmwDNulgQVgEW5AFWn3BFx4H3NNVx/g8t2CaLe3P15zucYSdNoKTcUYl\n7GHGbQdoaRAnRSeMqHef0qfvT0dR7LIESAjQyPKu7QM4QNql/tvncBelFhNIaloAKWVxI1jC+rnA\nidnvAT0u3Nm8FbCAQS+FZYd/G0qvAmUaTdHSY5YQBu598M52triIqPfwnrYkcPTihkbzok4Jj5VN\n02WuYm95k9kxRBiEaHsA5FsJXYFqMrHhBmEV57lgvUOlXxkwjQzpFPvmlzUQNp2lzJInOPFmiFo5\nzMMyEAMabQ0UMxSEDTmmdefcGb+5ge9Y+EsF6RLpc7UeVX13avfMD4o1+QKqaoEFtdyc65TG1sN4\nK+vwuU+qlkgzP53vlLjabwB7Hy2zM6EICdSI9DO1CVEo3QwwzuOK4BGViWJPvt/CB/+5xFbU1RCI\nI8Zb8l0aUedAwsWOUWEEJsD8R/2CRCOWHivSDj9gDawU40bX4U1Qd1MC9Lo3SJOk89j+CiS724H6\nHb/qF3AtkszYGlurniI1/eoqdTONG49xVRDUoyAcp9SucxC6dlLkfeLDVoTujJyTTeN8CKvCyXUD\n3g2QfSMPuqKsd2lSD0RgBcNbDa8ZTiXg9I1tkz6ECDvKVYB4wgdCff0BK2GmQu3XD1GmYbPTyhcl\nFcYmu7h0p77CIK1Kk1NogiBM77nhXEbtncdoW6+FyWxr5952fHaiL+P5qsgGigkx7ZUaV0BUxygd\n3QfJ0weNBgp1i0MLMfXZPWw4x8jGakU4IfkFcKXIImVygYceNyP8RIqxHOpTlwUU+XdW81ZlbcaL\nOM7oZyRunS01y8ZBLxxb7WkY4kP7YLpoAEP/dzGzSd/HQm1lzrKwvNlcpvBY2mXxdKXSwASLilyP\nnt6W9IN4dhET86MM6huDnALHXtA/wxypyYioJ/hjiOujG5e6aXGdUAnFeEJydE3EeBLBcrPgOP4t\nvlMeIK4KcOzOD6nvxMHBBreXrGkDIVEdD3O9oJjMwRu8krYXrIEug0aTbYgxNsOs4BgVFdWXStrk\nIqYk5AxnNiavg13gorMqdI1CLL8YVjzZX0H9FAm6g3IDf+5nNoYa8XP2WQ4cNVaAmItXLTB8PoAu\nyIMgmN9VpAGeVsjF0UGI4NKm8vWmNAOOLIIZQjgbeAlOm60gFMRXjkYpbR5FRS25I+EJjqdrnAbM\nE75moXvfyLIizPm/P0hKczvAahUVa9a/dNVDl4+gYh4oGJaT4BwiPGIT99Rh+xnbqwaiUsEDSBVZ\nXbR/zkDna1iaITHvnNGA5wtgWxmi98qz/EVfZb1vZJSIMt8I3jufZXJOFgSNCXaGNJ2NbQHpDJ37\nX94nwiIv+jHrgemcfoEpyPl2R54eyF0y5IC+k+kUp/8JYvkRG1mjL1DySafKB2xylm5+xCypB8+I\nMY6t2sPxD1MoTsJQuiLhQpf2rrVMR5DDE5KHG8BmvyNknW1hpH2uqopTLc2y/puPiPTcuSUYnTt3\nOuL4qss3h8RIX2k8aShGbhSW23+GLmXA4v5fKFCS6ykKAWm5gLWz53MRzhBYwb9UBcbKuV0zi9EL\nFUKX9VgO3jFPoOXD+IIZj0/D14h6N0TWsnTAz93hBQA8CivSjqLOLnwMMVm4iRMpxbMsDrg2EI3o\nhuev5nBTlLsTmxUnlCtsPcnjmZIB2SmXlRyyruE7Q6TG6DAeIeDqfC3pttmCZhhTdGLKswPtXDzC\nD5YvU+/gdBQpP9VHGdWIrXsb/Jd6Dz7q8HZx2rLJ5zMbnHhgndrdWXsQzE4drNZ4Vw/2Zkg8xy5D\nUm0oTwQQcDTJLoIRo/x5DkndsTueDBp8U6DIkx82PniqNJTiq3asvS76jjTZPnpLJFhivYIfnKWj\nQ6+X+UTnQTN/6UApRBrAEx38fH48X7fg5robVlWoJdk3W5FnbG+8Qhn9huPCFWnK3CeCkR0jWApW\n6Mi1spvKosOZDXf/ioRSsbqbP42EOATRrY5Ibl8Hr/o4x0LQpPUKjV42C1ASdtPth5t7dwtzGtf9\nEgaS2EAi7MlqsWM+lgvKdeHroED+81qrwuu1+Wqg0zAHXqPHB9kcVvBDdGtr1PW4kynIPWyuvKLU\nkWa3ZTZLdHCfmcfaj3i+PwKLJzGMFrPeSfKXUw0R+Tq2bdiNPavboVwQmnLZNNYkyKE29UsDivjw\n/dFfRwrdat1a3p1/22fzNnC/wgSI4JLCFExhWZ7MdJG/GD6h2AIUvi1KN3OT+aFVmsNNMrGoEB9o\neMGDfYKc6z6Vp9PzzrDEUBLcFJePmo1Fwp7Vx9dvLMJS7Y9DX/VrApwXNi0xro7X6GCYwdkFCFLJ\ntgA5Q6aWT0/1mz5kheKwmY/mLuNm4PjCy9R0j0C8syNHPbpToWbJ3jkTzumMx7EwvPGGT5ACkMYL\nNBvkkmCueM3yey+wI/EEgCgw8jVFhlrOalJYmaUJO75tQRuZ6twLPesD2U/yr7nvqk2DL350Tqz+\nqyMlOyYsMoOkHY3+4VeGjYup/5vEg6dVnSIDwTMkIhwfq0sadTqTTeWB//ejlA3t6+Fk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j+Cfw37MsBQbT57g53rBMerORc7ryFxm95xjTusU+axm116fXAFywBnav6OY54\noRR5V55S/GIdRT0ita55wz7c9csX9MI4ez+Eha4eqbO3is05RP+6EK62kXlzTm4DS6iHP9jK3XYp\nKauVqviIbqyqmhuzAe7U1WNBiMYV1D0EZ2jNScKL+FK0ufv3wPCcqo9MIgvLOrGnNZU8Pcu7FU1E\nmUb5TtoUPf3n+uMkJrTM1ykB0ao14WN8eh03YT07Xh4sDJJ+rkvMz0M4tSz14udfoIdQEJxGDAZy\n8q3oz0oBcnezYmEO6+etv5K4fY5LjJ1WWCKtXc7VbbraKnkOt+JOgOcUQNQmNFzuowP8YFjkgUvr\n0Pmf4TfsCJfnnNX2aYJsOYtXnHfYBJmuTP6qsD47gg1Y5z6ptJumj/IHhG4HT+KLb6jdBUJwXxVT\n29o4ayeZARUa/AjZ3O58/EkabQB7SmZw1H5Cz0/3BUH17AbveCf4ODT+6BqGLXgKwlHsomdFH5BJ\n1YltM+qn47jgCnnWA/j5H5T/+NDyhdnWsjsRzR+3WX+65bNnTQsT2VTv3kRyAesYg8ITlsAsEkKO\n7TxD9wrmD2VuD888T2NAcWc/zvblUvNZeC2s1E/XsQ5Lgdg2gwHQkyYNz55R3a2R5r2bZuDX0be2\nGMAQZO/L52oALOXvn2djHPWFqcHgmCE3hgR2OHEm0Lv27l3NW3XgJe0xijJ+sRWzzbHFlGP0J5/3\naExSF709uXkvxxg02CiO+okGM3FZ8rvF7JUPfFUx7Xk76pltJQEqWstqnVCqp06x5vVIOvReIozC\nnSBce0AP08DJAbHddh52ASWpBHzihU3M9dyXGzYcTtfAs5WRue0dQid3KvV93QMl8KttHf6b43oN\njiO5e16Id7AtEsXQ5LHyb5PvVnfubwzDNiUAnaRNooQY2hGuvnJ7WXy3a7ZT/XypExNkQzaem/u6\n33Zht28MJWvVmPz8H1dDcbVhzCz42L8Pzll5JysEuvLD82B8vyiGOroCHHgfry4MPUTaz1pf4Iug\n2vWAvIZLOg5vcfzl6Q5t5Oi7mqUya1URwtqUwKhyEan/fQRtNeosdwDabd324ZVg3m1IE9UxaesC\nafkCcaFg8YFPM/yNUJ47FCpyr/yhSzrxdK+fwbqXoQWQe7gzDTkEfWj9mxFS6ag46KurNXR3+uMa\nnI50pZ7f4IkM0BoEKzvIBtf2NLegzGPlJAQEL+hsBdn0qKLF5IX/thn+Ia9GbTe0slTlsGbfx+ON\nv1jDA1AC2miovrhzxdqgVde1z+RzUBC4sH58t/LLBPYHpZvWxD5V1spsgOhlNhg8w/xVuzV6IGfl\nXIdRMsBnsaZfRBhsisAcEC7zeQ3vlsStSI5oJVPFGuyyuYWoDZRXvvx1hMzxEDe9yY22DD4gckzM\n/FAdpoxBv8VT0S8NHv2L9+DUbs1l2zt1b47J/OzmhLZ7/OirgyOFMOJBLYNriZN033PJsWyO2W5Y\nl8ByZ11TfjJfDekxcT8X+pz8qjKh4m6s5zG8UZ2Ki/+5EFDj8OiTQ3uM+wFI/rPQWtjZj1l4AfUI\nOjQAsJLaIBd3Ongf2RDI+nvELbRB0eZbQ7G8800kNQCzuyKLdhijjwz8rmuMMe21Frbb98Hzvx2v\nUrMPw4tiLDDwm8UmGs4DspSiKLbVwwPIOnK88yLjC7ut8n/JngCxhoNRX/dQ9PDMItclBn37fXQ8\nQo/sj3DiEvpm/3S/1TLxiUiH4dROeg7jQehI3N1qo01/rKVzsy6CHOJdLxvW9yG02Dae4BBm+A1c\n8D0ne5r8PoPmsZhJ7+gtnqUD3u7vWGBZVN3Ee3R+8pkFp1SyeGtpp371rmcJAbyaN4nzxeMAjnRr\ne241+0S6Qr5z31/4faoPe7j2BuyuDSsfAfKlDwBPlc5guWgzHGRp4ZZEZNTwLwhX55hOSX4sEJ1Z\nPC97p8EC88PodAF16iXwmg2UmGkAVKqdbApPeyLqs05Ggt8yZLTPYHATxCF/Oa/OWTxSRQOiX27h\n+9EhVM7159xq6lwZAYHAMSMyWaMRsUKbzORz8K7mCOssh8i/u/TpTL5pg1XyIjvk0BG4DXUvplou\n6jwvTFugADovXdFKxAD0PKEejjgAsEBMKQdfYhdXcYe4ATft3KxDOHbKCdiU5Fyqr+bqz4LHvx1q\ne6tW0FeJT/lsC08kL65iGpt4slIMT4EqT0whqPCpSbLfbvVTEHffSM1SfwM//dBov7Y3ffBrnMxN\nvBLn/cXBbyHE1YqlPBo6AC7acz4xGpfyZqZpjWMGLzTBaGYMPHkjivBhmP7AzMdx3qtlDlwgngSj\nCGHGzSrvzwgpCHmZ1M5MD7c32cbwq9xzw5OBU1ug6wxZ7+oZRHLJZK63OsXqXTjz3ZPx24GBkZiK\n1ZA7bNQJhcAd30B8zXefcYaMKCuf6p2Pn5Td8yKAhOuMQm5Dp9H2MUdwVOScpMKBLRMCftMyeZNJ\nyFeHhh9rvDnTKBGQnsTdetLbkpbSKTV0Khjq11VuBaoJ9jyEmqaLFNh73yl8DI0AH5gVla2Uea9r\njBpxlCR2R3MNRZr2f20Pl7QXkhJQrBruDHBfsB0uXuSIFDnDaYn2CnCu0pgAOMRtp0RtWC9IROXA\nJcGoyH1Qj5WwCl/CIFUockfKOutrYS9AVhWmRi0lMcEenEyhivOx9acOtOW3mDipgVemh6YPk2SP\nzNGPMEs1SrXr1D5W0d13PjPiRhuZVK60uNTJ+qnAc8zViCko3sLgn6+21qkEt/KXnNi5tPuWZ3ZX\nwFkm2rvPSIqp49m6zvdeuuvigOhNwtNW9/MwJoHdsObZOVC6I+hPhfqq37PHr3ixJmguJHB1h6ZY\nMaa1KLtpUreuhsWeBC2EP9plwltwLj+t3oyYOkauhKbZQ0wbSr0QmK/gPUmBiXZuZPJMZ/Cr8t80\nLdhAuYu/LsMvDvMi47FAfzerdNw1gmm+VeyQmU6lnV4VsqlRecBN2RI7z7//wPyflTMgnIXQceez\nihB9NFJWtWE3xB525j6RFzz3D2j81vJ82dAmoVCy5dd9fSbAlbldvowY95Eb3WAzqlyMeuMmKsk2\n9fQpIclafHuXWiCm6HvtfMAesiz83W/xdRz3OO1HoiY16RT7mV/tjrs7MOZlodHoLUDmBUrOtBle\nQUpti/j0lPOMXDNhGrlFnl3w5Dvj4dVyMPMvtWIhxTh6hiF0fjmBx0lH01VnsL+vmmQ3NIzyKyXW\nCIpYAMb0W1Uj+VQ0tjDjVWHvnR2A/KWAByBfHqWjEdmp/CCVW6z/BP3hfTLr9AZ3+92dX7nA7Hi/\n15Uoei1DyP+5vC210Uokorvpzvzb0ylI6eJX2o0GdCCLYPTsH2R2tyS1bxGgF4bqFMNp5cpfICVY\nRzvXjFzARkgTm9jZJUmwgtwDui/Uxhhwr61u8zO5WsGhB/YVyEGVvlGGa3rFN0REmtXLj1vqyomf\nzSYCKdFZh7N3XkB2i1KLlran/51tWM4ayET6wOLAM7sBVALves/tqKTDE5TDiev5PMBETq/BmMfJ\npzgW1F5BQERJFjH5/QQ0BrMesOv6xfzIsb5jTMe0ArXwjcYGFkCuI+NYSj560Ux3yh0aLMJHrXgg\nLzWamLaMcL7cMaLosBbCjI/AFNkB85hT8bx0puob3sXZlf2E9wi/zxhs7vr51GL93Z4Np+jn5FIu\nh6Sa+LaYz1R7gx17e+jyO3Lv20elyDeMRUMDXeu7VH7GYh12c80awotJWQulCzlwz2o8JUZbQOQv\nOnlUjFxiWUNtHwxzPI7PjufT4Pe4AwrNP46bwItDfCX2I7GAV4+YCo+SJFxBmtMXGDRrGaH5pjAp\nzN7h7FLAS9BaxYyYQZbi7JSaphlzh74KeNdZxZU0sUxGNMGLSYM1sakS5Hk8JdELxXLkmGvqNU+u\npfGa83YLyTozrwwnxkYAuFh8od2CX82Sep4KBd4nfZ/AAcyGnB6/YmvWFQ9GcKC9OPrKb97O5OsH\nWQU7mOVHLMOLTrpRtekPtfRH8kCF63TojYH0YfNW5ahbvUx3NWSPPPxnM6SUIR7hLacpcRIH/+JS\nu/aXqGQMgigXg6aNeGzMW6Z4bxV/KltwChV0hHplVuln8ow7j7/0Yi+NLJqkTHCnUd/4TkQAhM4g\nrl11SqrnjXYxlK0PM/TmC835bd/D/HHmDXsWrCRhDFezuKPgQh7dpXUDdIXi2if+T3VOLZQL2rGu\nSFd+PiSTZzaQeLmj6YH1aJvzLMUwF+E5n1t/j2z1xEfQwHe0TpobMOuESFcFznlV2nV9cdajbKk9\ngBea/7vJAgk1PI/3yTisuZPI6xFLJUZ6+nT9TD2bjILQSczUCcMnm2OVPpQGzt23Eu0XdoeBJRl8\nyLGjHgl67R/xG7il/Icmo6OcbL39sAiOOgEHboDlJv/H6OW/kWO4YEiax5zKnmS5Hczu+0r2R6RV\n2fLgfFxWtuXnDhXemf3pWPksSbfymvRssVRXAnzo+FVi51EI8IluTdAKgX9TflM4LcpS7TXwVbt/\nnY0vxCGY2+55IS5YGtJAdrmlvTEZJB+SxR3ubMJp7U4WFXKih2wxWkXyuRKSa3SrHz++owohV/XX\nDgqWGZtID19FXAGPQ9IICUcnyDtTTVj6ExbfMgmPb7zBrZOTh+NJzFwR+5aXJL2LteEpEYijEEjB\nRtKsIb5b8IaUmWGzVrGuOMPmteHKh5OMUXtUxF6Iub0rbFUVxk8ZnfwxRtCFvCdXpuxBWpEOWUnY\nNLE6uy0Nvp3jVzkITz7dAQCFynXssstQNlVz6MFkhe4Fa1L47Zk/GWZyjrwA74LK342BnOvMAldw\nMfpTXLZ2bmDk6qRzaCPsHn4JyDG3WuKWXSnL2PXKKosnhmITmAmbPPvKkRHxMbyD6Wcn+NQ1Na7u\nE9XdjR+5XUZWhzMHUHEkVKabBRa4edljJI7AFyS2UkO3AWnvW7ngXXm17lzdUv421tea0kKCOeWI\nnzAlrQYTP7uoDOeb4mFgQZqWGpc7D4fMF4jisUAZ5cQ3VAZoyvizNoDRX2Z4Tzlhxt0VbMTapbD2\nRPPyWWDuDkaESqi20IaZaMl5BNborESQ+XfwJbnroaTmVDHIJka2rL8ND/Wrbmq+3kI7EOrEaEO3\nF+dN5cb3hjD05jUmnpfBybdQjWCoWd7fNe33LYfxZfMUyS0Qg+KVmOVBrvVZu4rTlpk6xRMOh51C\nJTybid5KEDjkYQR4qKMaDi7vQjWdvwHkBvnTMeC1LI3SEyAetKvXAl3OqFr5CO0LF6ur6MhewyoC\nEXwhywzgKl0tCXjnPy5vJsWiH7DYeqZOcI/LlIuDaFXpNaWW6F/srOMkAKx7tQFoEVTBpPtGRVRj\ndFejy935WgUVG7AJCa/bo/AO+VNu/zClTf87Dt57XAY4n6rW/guQJicGbcHZxL0nd9RQcxSx7ypr\n+3YNT7vC5lRkBl+KJLguf8y/s6eLkWFvGaU0dLDYo9UeZNfgc5xFAjl3mH/oH/e00JclC0KKsZgX\nyhFd2n1n9Gv/FNSUy4eEqBAB1L/fK7KrgvSQeIhO6nbvqohfQwa8OGC+DfgIXf3s8mohzmoee3P5\nEIaobJ9CCatAgjbbTkzKDD8x3nUrOV760207rE6IBNgZ4h2YS38eXW2LdSGG3ciJu0ZjbNx9BL5n\nIu1/uQNcYneyszfp0H239thXd+TFSpguz8zOKPu4orLwCxkfBVNxkEtDbR1IRoSd8LaXfmHw4JoL\nwhX+ujfI4VSndNsWwb67mdmQea+nIe1QXbzotui2NONrIkumkUm0uMDvl9vVIoEr55K4rrlNwtHy\n7xQCEAj2RRGh+8uTK2BvMoCnNN3bdUfS6nIrM1kK+Ux3z/M+xcsbZRzB4JTYI5wyl9gcWm8s4tO5\nrOdl06VQEb55yo04vNqymYtXI+nZ6j4lJp0xhIMI9cO84Cst97RuSGH+Sn58T00Gi9SyBv9ybwuI\nwz7YutN8eFAtio92LRJk5fUeYDU1x2iKhUH0uKxzh66pA63d04NvBqVb8HIA8j1AUhDIeI++3w+A\nLJoB6oAK6AE9kt/3lMF+TOztIX4Wjj8jH0UUT/mk4TLThCPvnFVyNVKtZ3NEBXVnVWkZWhcv/KLX\nPY/CkrFFjahJAmwM4Cu9b7z9DG+sStNISfc0fWDs5Y+Rm021muREdjvHujVCqkyNKRs6J+ZI/ziF\nnMQl5c8UqNn+ck9OC1jYwxBIk7hNwQaT5bUCV91CklCjDoUcfkigFy7COMGPFUQ29Qc4yb4hFv+y\nCeXySIq7JDwm5ONBLfdFAYYe2u4GGS/yVpa2dIBLBCr3OnrcROoZi2nlEgxFalVhbyBya4ot2CH6\ndyH5XQJPb9aCfmaA74J7gXnZCnPVmclgr4mI+blDuNL6N7FDT5VM3hnggCb0tYDM8rtykAH+gQXD\nydcBNaLxL4oL8BZ4rcuRonQr9aPjGXhP3b5J2JyVL94gPSIvqPBzj0WEP0ROUv+3jn9u8/Erm8Z0\n9bvbuclXP6VOvXE/cAgG0YgN4843Tv/nrO12NjuroOHtCj+KsRhus05ciZe4/dSoeP4r0p6tHeXE\nedx/UooBnUQQkQIyhgbqLQamDGYBPgp7aMEizN4sZPPqWXbIxbD6MD3iUVDp/750TvH5KamhB2bB\nBTtQK9Tv5TFhVL1PNbRnsd5lVhoPCWZFz/iX+1S3WpAOo90GzuFuri+INSk7RH8ugMiqlinrt1B6\nFeYaJ/6LOV6shkLcr10QpRA4fuwbTnAD4XRARAlb/SQKZjfM+ESxPRYUJVXyTnPXNZ54AjfIUDlv\nEccw/qbSnd6G1MWfrElHYFw8AIJ2Vvp3AY4ed6tg+LRrnMwz9/lJShOlWcHPd6ZY1TpakMV8G/mM\n4noDqixZNSgiNMXB4z3eBuot+lo7s009iYls0VJBXh3afqSXMEvDUpQnfPz1WUYFmjhQpCr3Rp9b\ncrN+emcXrdg2qgYH2/GDweFa47gLquGOPPz7LZd0vOTCYrrjuSyBiCfJ4ljlK0d6i8llTkyL+jPW\npC7QLSXnGLIxD8r0JgRrap+2vfCU9KoAqe5HBtxjJXO04KB/dRzZvwDTlIJHvetlu51+N54rYEhv\n5WX9gllnoitGLeqAARfAdelA4jUnN04nXLAvGSW/piWaGHrLjK1LUsmK4qYnJy7Zdhzge66iGsHJ\nCHolHtQRs/FWaBgrRaMtweTzqHjBPeN1mwBwYb9JvNG0OGs60oQMD07Ca6PB/rXz6onpwY9t+TWP\nNX/RxhyDGVLMF4sV3fNn70EJ0QN2JV3SUYIBKB/sQJIQSVkyXA2P0whyiwvXwVR31y+5RpACeGtm\nZKiGVdRLpSw/VBntDbLsFqwHjHDF8yOgLbPcAMTzhiRWXaEpN7g3UfZoirImFNy74AFkbicq92cB\nGfUfwnKB33jZIrksRKyidDRG6CKqaHXprKwuTrnxwWTOAGa2ZN5s2aMQHG3ECRNEVgizy23wdAeL\nvh6jDimu4c+n6T3zI+78mFcwcAL+vTBAo6JUwM8TTbrIjTjVLpGfjWl613k6Tr1tETOsR/KwTSEO\ngzuBbPNdyes/iI2TC9jqcO66Tko7rRsqG7XFrJ1joqWoMYlEGF3lJr3dJll7CLZnQ3pCmmjnwsbP\n5KJdw93+TCDD9zTzBilgh6Mo7NNg0+b1lzVR3LfI8AZOqKX/tdxEB/LfGDFvfzZGmlkqn279uLxQ\noXP+9BLZpjyS6bcf8L3fNf0u2/Fm8z1JdtM7bQK8t4jk3gB2vpYwAXab1wLUr8sL6Mq7cCF1Fvvb\nBWrfZWcFgwc0iXxqHUJiA1TZRIkVsclkRNYcR8P5MwLMP+bhxfX7J9ywRFRNEmXuLmNpp71VcFob\nq84A+hXofZS7uFuj3oUJfZnuftmwsDrH8/vqRI3AVK4GgIAKUnzJAZaAe66TPOxx9kjAq9EeKwHt\n9mFo3M7+GSxcZhtkxR9LjWXO/rj4n9+8vBUQbGUChmPLLHe9t+UnBVl1OSSvTjkVppgZ8UiYmuh7\nXuHgTcBvkUkYfh+sk1gADnpuXG+yH4iPEkCOU2Gp/URNz0W78V4SpkNf4+bEKNuRbJjUkGDYX/2E\nb4ihi0gd7mvLSPtdk6Wo6JlgJzpfkTTmEp494fTpzFA5Uznd2dgjYAj1E34IOBjzXQl8cVs7jWfL\nfdUsMQ4Bur4GIhGnsHwKLlBt9ley/dw6US7gfqcYUBNG/mCD9oJiJSnbFYc7URN5wZjqr8CK1Y1X\n97EmfO6q/Qch/+WxLUVvpqYYb3bTBF4Z1MAVLSkmGXADnOz0KfzY7kHEUQCZxnChjLufCXVyHOek\nzW/4kjhRMXJtNePHfL24CQeaPz3kXh7iS/uSlmOzCXN1WBPdv7X0ZPKUKcNEYIdOVnop3u4noUG2\nYuCKuWNWR6r49lEvRBRpo7pFmM2THXnxu+4oqJ5/fKCYbDjMCBZiUnY8wfyOSe4m7T6+ElHk23Hk\n8OQpD4lFXokkzsl/fMD66eJvgVXgtxr9ogZtK0b8+P1a/69IRlHc3vVTq65kZ387nL4h0j8GYypl\ndRzdVoYeMCLhGwa/jjuVmosBj8jNFwZhF8IJO++z1GHJ0cQEmVRHWXDxVwPFiq85/ttl9X3p0+xA\noEhM63iHRpYrm5swsp7hLCcKCLG4eVt9/1JoO5S8w0GyGcXdCRVRZ1QYp0RTIc5Ub+FZlXuM5Bkd\n/6Acv6C5CwpJXua1J3J+q/E9cGv2roWcMVn4eFgVYxaEOQAoD4pGR+BziDMYhD9CbbrfguxqbBSc\nFfHrSgYQywkGg2sEsOwSru0GAgPsD1gOZyBQ4PJqnxECV1jR0+8Io3Prqt2712ZYbeoVSgONtc8C\nczwcM/dkCwb7HDrO8bydIbe5PzeJhVOtYJxINnw3OPCBjqI/ZDNB7Zsszc9OK3PU5YJ+LFA5EUzH\nFp23e8G6mD9FPJWH/PM+ZKnRd5BNEb9OU5rrnC7887WPpR0TGlHQNRjeBbJdjS5+XzFuRUBQm95s\nyfJL5GcytnYY0T4l570OZu5zMHYmqDPv4TvZdE567u2sf+s47WwEAhDQ/nVamSmD0miTORTQz3bp\nh917Qrdh4qgxN51caY0HaRS7vp+MIENj3mmUt9JcQqjheCNas4pjQ4/vohcTTIrDQeAHz6dicbAF\nFiVsVyvUl8SeroUMkymW1ex2YSW3FeOvmfKewI5Xw9kLe6FRqel1xS5kX1caIN2r2IZeQM65tVVl\nHM/ai9GbqV8e+ZzzpOQpd350CCDiwowlR3Aa0NOfliZc14X8ivq4ROzb2475yFrfxHgqhmz4ySPA\n8KOoSu2cDxFZXP4wls81A/LmhndsdBzNcX8/Ol7u53Pws/TjE/irazYiy0zwLZboeBUNugiRcO81\nvnLZ0JXyk/BXzczKypr2FCuplBtsfWxh8PCs6rSplmadhRcNmxUAfz+L+SSkuK1jpcFTeZLaQEeU\n5UiBc36FlnxZK8Txu9+blQ8xycGu6S8VEBRRyXhAy1UPpChsn905SfjkUNKmETrkpJmuqdMDszUq\nflbNDCVOu19SlcasyftCBRolllxfqa5x5iClYigZW/635ji+nZ4CowwQXsh4++a4hkkfrbHn30GE\n5FvVUmKIqRpAOyiLr/pPfKkihS3GQzoVWU49QVmxLbAiT6ApBXGAJbxijNQbN/os0donJ6cZqsOJ\nnuHOOb0G2cSYwpWRNMpoZ3int2pKk9TBfmh6Km0/53X3mXaOmzbHJAVa9xYbuyeCgbzV9e79fjYw\nXZoNoJqJWlJIhLMaZPLYwzjnUEo+OYQXe5W1o+RpfPYJvBjQDdtZQB0ZFS+3X39fjEXWGyYO6gEW\nU8ZW7cOqCjiAtH6fXQH4lVKWA6uJb6l+1+wy25v46S2tNIZoRC0jYzJ6Zb/wqBD6nfZCA8dQMZgz\nH3i1cXfzdetvO/7Hncfk7xKUKXhxD+Amtu+bLOt1o9yofetPY+YoFKh96+uwwcRTLeM3P+eLcScR\ngT29wMMJFC/+e47x1kz+AsAhPE71RAaol1o6KSSoJOcMemk//MWnq5WgKH+VPp5cz4tmjJGldQvK\nNTbu5I6dSU6LPG8qDqn73F/wL1W+/rlrVuuS8AFzehqoasyQsv3Sghq9dbgsWjUxmE6W1jUYtaw2\nrawBLDSZLKHpYoHwZeUcp53s5LhRNGF7+ZBgCcDFTiBfewQFuGvnS/U/UUZii/RDkMW+4UvtJ2IS\nqNn6H69I2vMxICuizi3O8YndssXbrlpv7i3EmJlUplPeoaqFmUJhsa95hQmgBZEkxh8UB8eHZ5Kx\n8hqV/r36zEvz0XR5i7AUWeTu/TEQKrmrcPs3AKl5Ioyi/9VVDf8XeutYE4Cxr9Ci9NnosWETxu1Z\npcmbSek3gOwNlwes//MXx1GzIFJ7miSiG9GV0j7HSUAbWdZzwB4Wvwqwc+VZt4ta1ckeIknVjVqp\nY8rcRiZGxfJcfF6NDojqzJuUKkpxZpJJ2msIutqcFSRyec7wv8TCcAqXhXohMKNHQV+NyVpJ8IZy\nP3qgeH9xpQLIwGwjWsVu+bs2jLz6b+2HBGkrJbw9sgeogPoUNppb/5A3IxBKE562i6oFjJ/kmN+K\n0/5Zo7yK3fm1zn3O1ArOWt+1tNV+QR1eMxyhXTDeer77socAetXY1NeYVLJHck4o/pI1MknE9cXW\nXpOPnp6blBiNgKM26rIs+Lp9AOgZlmnR1T8eehRW83yVw0UHkHOWM7S8hbT5NdhcbhdrRkH5modI\nGQKWN0dM6pmSec1vC8GsKnIodkT9XX6sG/4P70tRU753ulmiB5IJwKVM3CUQ/g0A3nrOkH3CGVYm\ngvZysCfIMq895matvgm2pJp0Xp6vN1eQvPkDQqm0wSjloLzGN+eIUI3fYTzOKvk0c4Hv0AFt2lkj\nfG6TGSSe7JEJ3Vl3iQINDi3hL2yi+ivAYmYxsx79Jv/vM1QYgf7z2qye+OvC2rAH0ZFx6j942rvP\ndExKp9rGmP2KPSNANDckU7Xe//flyV4WgK8FrJQG7jn3b6efj/DMjjarBkJs0p4td30kZKsbxAOn\ncMZY0iSlRqKvZvI19sZrQsO+FTfH1C8+p/N7Ozvpuf9lxEC/gtBdm7A/HtVqmOOZ6TxdQXTHAn4S\nWbcNPP1KHuBCF3UheMWPYZRP4YqdH+RB6NacMBDdHcRwMdFb5m8qPTEK0hzbNRRKHmxTb8MxkK+r\nVRWLaAVBdTWl4Zv/Hdg0O+PvF9+jDqSudZ6y8hiugNtbHwgTug63znnpTHu+0uC/hVCu0X5ysWLs\nYdDNTdXjn0L61HP51nQT2KMVnCP5FYikMbZKzIWYJhIM/vTVYluH/lbpBQwtZZN3rv+VEQ2VIHy6\nqP/JLDRIHkk0GppmF8JZf/XIGhae5jITmB7pxL5UUaYiiW0vHJL/kYW+CLwVK1Cm10NGdlt9t5ii\n8ndHn1BiKBhNmaPO2cWYctCbGNIAP6PaEl+k5G7Hq9oAhM0NxVSf66tEqjFBDz0yeCeyKLLEPDzh\nVRi8PvJFxNbbLV5xOcvHfb8J0OktESsRnkGpyyEbnBZOFLqGgWjfBGcsWHaUnFirlghZj9nEs5qh\ntndh9rIs0YAcKW0YirX+/bmf+sR31DjMEscJcErcNuc4w84IOu2K1Ys9Ox3GU1wvK5i92XbyXF8b\n0npzv4Cym4Q+aSAkR/tYPpQe54b2ibn117M4z0x49+swHRVJ549tL4j+/Sc4m/ZZYS6hJUqcUzKy\nT3Nkg1FIuLj4vlP094eK0H5GtXQCJilyaKsLbV3iXMsi8kjTPY7oxp7yKuuiuxZKaZ8eNoHpmUBl\n2xnlaB+oVARdjUtAQ/iFqltXIP9vH2K/QRncO9mHJYUpNXubMIXFvzhooE4x35rzUjiQ8IPDu+MP\n0XsYIoqklhDwrLK8kTCBnPUl5ivDYnZuyLHMauPtS0VwRIna51qz3wzXnkmfasrYYiu92K0zMbGL\niS7gJKLTFO5HsxWtuLTFTKxAUMzvQCsV0Ss/sSnSv0k8vCTiqvz7/LaUUeGRYK+UDOsWwSxOrzFt\nSQ226IRWAolvE7PwOw0ZAcbCK2rq0Wy+7038v1w5IOj00W8LW04pg5KLEu9OwIv1vik3zJsBfGGE\nYzNhip/WyqA5z+NlwqrEZhyEr4MIUanFbOq0OPUvOHI2I7ThCAo+avbSm30gCYa0hC3Oc1fr/vNk\nK1afGnpgDEz9HpuwWatXX4SKXqjpUC2hjqjRdF6WGMWDkAGHzIses0/xxK+TPdnTXQxHUJmWYK3n\nRC8LoJpcroo5g0tLBUc1asyVlvUthZolU1jAKslsCvS2AJZhkvIfkc7yS547BRpp9A6TfdqYYWqR\nmo1YHwBNphKDcXzwWT424Kah48WaddmdzSYwj8UXRBYZXvLrrksfzI+gNpKgvzjfHboZgdFaQYKA\nLm4tnx6pCo2IgdK2luFOVM0StpEJOCHWXp6tpS6cM5k4hIagiVP74q811sQxmI+nt5F9129tYwuJ\n8LxxhniARFr5x2gmeQfEB0OWZ608jovYyZJaCmSBWIdw69kiR7cXLJR0NintA+L8EmW+jIYyBGIK\ni7QADWyM8UAWuv35PkJFNqvBDwOwHLtj8hoKzQQ+Eg7IxYz5EqyZP5s/kmyuUqHwqcZI1/4iGJZ3\n44XKkFLlNjQNoy+KsP+rWqck3qte5pvza1ILv9JHBDqag0j6liwmx+sf1Vm4lnGIJnM84HdrySaC\ndaKn+JXpUvOTCob7zP+MTCz2RHj4yoYZnOBy9Mejxqc7iwOb0yapQzFgC8tOIlwE3x1urRC6bHnk\nzmjrgZZowl1waVVzzAZEkWlso1mdpt7JXx3yF8/N47hpd8ldAuw1x7gqPB2kzCQLtqamt8ZP6Mar\np1cCdJ1BBTg6ROqgGtSsJRlO7tGtq59RDnURWh9kAstr4MjosyJeV7SzMzFO3N4N+Jah8IBg73Wj\nGERONgegcIzn2KtPcMVHusI5hGS1ORqJYsCLeiWvyAVEJ7EtKbzWZqJryBRP7Lu/l9IoCepgBhno\nRo9etAUIlJLcUUxood5uo8xXBde0SroMGTYvgCftccVIj0RfXH/KrM0VBvfXITJSTXB9QU49OeuI\n11hVMMyDHz9QlifcOgs1xmGouYX7OPr+C+9U2gt39r+hvo1zsKIyeH7X3nEFXVbdSz/jqbG9zGbx\nmFH0D1CRtPJv+P5HS+JlodOKfsVvxqX7xDelamLf/YAIq/gzDrr/ENt53/b+1HlRHsgA0U8Xo/p3\nudmfGdy+W2Nlf9uOYThin8aqPaFW3RRgJGDzalLgGZecaw5rNJzyVNgqUN4kkf20YOdWelY34pJ3\nL1q0pFjGoIUrTWA4eTYZw8OoXR5uG2+vLcuRm6HFhtxaK8Ffg6MeUnZxTKTbSyZwL/VJybuIySXK\nxsMmvtT0WLqaJT8fowfKUmywhJOqrWklwtEZAYjzKZBdreg2TfmEpnNM4xOeAuhdFqSzEKxHcq/Z\nuJnR5ZJJhRvde8BiYfQ/p5ajpJwYNIb9svmFP/a/FxEJ/eLQiaewa43R5QRF9IhCCejEJsEUFJBU\n7M5Akgm89NYU3VKOLD6E+zROa+FZq3fJYIOD14IKhM7/Q6CCVEM8dBsvjIQO5ZWYwVOIia7D7qiN\nDS94QsOM4rIp03nlfEtnQ6D8nKTEn+fW2Jt4g41gBaFlJfXC9wYbt0wZ/0jmmyuPs6W1XSCuK1Qw\nQDsPjdr+2PKzOea8tLgms8Su+4ZoQk9v9bMXnCOAwIsW6lrW7Sigsfeny/QhLgwvXnTL18hyAdji\nDD7zaM8MBVB7vhL02mlkwS+Yz9bgcwEgdeIqfC9uwzZYqfE2BMr0BcSB0uGrJLsKMq9h8uRcC6pu\n2b/XhUcHW+ItpCPr4572DTUIZTWidJyRcU5MvpAH1uZShE5bSuNsWlQWFMLPW9HukeJ227iuezNN\nQdKRdsmvrggGdqjOcPUckxra00e65F1OEcw1G3LTpsqdAVvwmmNx6Ly6Bd/vVOGeag+VVJBvxf5o\nrMyoSzW1v2Uyh8p5djNGNHJFttxl1O9vnMrFaks7XW6j8ozzz1UCeoNBwJvTOumSMcfP1qxOKi/P\nT/q3CVEEy2J4BY6BPuVBgiSezVext/kdro8gCckmewDuL4om7pzsK80j5GsupQzkluHn+uc2+jXT\nuBBB4NBo5oxpdDPJtOtn3ZNwmJqMgiJIKX852f4+yxaNPG0tZZT+6PfSzhNy8Fp76NNUEuov06oO\nQuCUUPheCr3QguYXeezOmlqf6VNDfd6QO/ZMW+krYSCfErF8DAF5O81y7mkTEA6oP52VrM0at/3G\nUgnciJX1HmT5Y06DbNHNv1U6iLjyqpD6nmCyKMsEdk6VnQJTVhWuP0Rtto06nAmszyNK8KO0D0d5\nNUP/gPYvfCFyufHTUkRUe7DRUGtst4C/H+a9qU/Ti3kddUyYytNr24n+snyzLCcN2x7qzX4B0AHJ\nojZnJBJXGOi35Voq/gFeLatiG+wrfq+xz0PQvhAHgi/BqhkJyg4lqbPj+WZAjz6L8skai7T6eAA9\nz4zYMIixZaOBj0I9bGxyfxQakJWX7VqY0wLmbgPuxAl9FxNk7VlAt+ic5H94knl4hZqa9j5qV6rF\nBhwijZCNdRK4fjVBWKcUVo+AUGkNzrQ77t7mH/2VMgR4dbU+GfLgdsbZUWcqlKJdvAZR1n4tA89Y\nk5Vl788WgcYuBxM7QiiqcqQWDSgrurchp0Uej1CE8TFfBmLQ26YLwipmz6RV3+nionCWV5ICXD4K\nIt+TQG0XB61wwUKOMB3eJlh2jCV5V1LdJmY4714vMTeYNvkgvT6rlRlbbKPmhh4f5WkkTzhjTxix\nzUqsYa2CF0YmKic8Zaz9Upu/Yqv6fgJj25EQ5T1s6aTPiGc3KXDbu5MA7bdSuPHV75igKBgtOrOi\nQU8DCVsRnRrBsEoCipDcJzZr5Rfyw9HKMD9wIscAgPwTA+5IHw94FYrHkWSViHwP2jCT3p+dPn3z\nCzqMji/xZcs/4Owbrg8E6PxERFw+AjSFrER8Y6GNexbjUKHw+DSKS6I5ea3SGNDsHKMuD3r3Mkay\ngx6UbaulcE0t7PM3dCqbZQ9BP+83/gsIgJpHIPb8sbzD5jGynf9Wejhh0MD4H1QMOSOPZu8Npjt6\nPn1w9jrrAG1EJ0A3sAmGRpKSWxvd3VNFMpmISobIhuHMHGTUuKiDnwFnyitDEFYr4fcm+qtSm3GV\nR9mklSbQekfyQCIBB21MdV4oyox9SWEfDMWTPFn5rGm7GbwGxkrNPssrSLKBt9zTmy+4VQ1dGC6I\n+xQIK1rNw97wSd8/Sx/BKdKcV7rs8zRlp09Y8iM0fvLj6scZPT7X7TH9vf/WmsPkB52trm9mX2Oo\nmLIC0WAcpoh5mMaGKjdROCsI9pbrrpOVtG+wT6S9ZnQRWWTZRPPLHfyWX2LzRXSLy+XLJZwRnUyn\n45cfS3wWvpb1Vg3XyFiNNvYEY1keugJMUGx5EESp0Nm5CyQDyQ9qo2XrrRh48Akc4EQF1G7SGa1z\n8W7PWZF6eKZk0azr4QKnbC0/1biAHjvdDbOymP76EfS4UTM11v3RzWxqlUFm2kqNeVpHZPy2NKRu\nNpKxrJDFC1d2QpsJlT1jQzW8LV10+SSSPj51YUKirZWYYa4wYMugtIQlohEOvdTLdt7T97Kgkw9Z\no5N8WM95BbPTWfiAEwTDYM6kGhQOCh+7SwDNIHx9fQCEoE7ud1hkS2U70ByEP4YTI9rYa6ZvMDxi\nF6s2qU3uqA5kpU9UD0/AI8rP3wqB4xG88d/9JeK/fV6pF/A1s3V2EQsY8rXOGghpNiy2R0gNYa9D\nHi+fjXiS9EaEkgM31M2gWo+oUpyyCsNKOUDjSLmF7B9D7HXuSn5v/axhadcur5njTtr6O6jPfX81\nNTzKcyIndJ7n/KY7EQEDTiBOqtPU46/+tvrggOIJduC/klcmGiJOGggMr0QOjBL/hmWpz0ut5cC6\n2IQBl67p3mwOtj3ok/FfMLx6h6bt9zUcEvq+f/JvCCEyZHBCoWIuTyAqpd0lsiOtPX9xiiS19gGk\nZiO5klN2P7ucRJFNm5fGrWBHjl6td8Y2jVFB2bmhiHxj+LzxSkHLZKx3hlzclumt663rykZV7J/V\nOpQnoLOhm1VnPG0a2RwOI50uK1h49bcjHAPf8IeH23eFtg8KfRKTLZ3tMZgtWyxK5mPM3XsxsmbQ\nRDQ5U4luxzHz9zY6O+Jp9DsMfvFJOYoMAd/Xf0/1OtDJPxwpSwrIlBPItlBz2XiJPyd9bo9xZwF4\njZsTZfJKt18ckYdg0vSq1Y6chPr+58JEG+R8Eoyh82/JnUgXqeDSDo3x+ZevFCtUN1lqKfONmwUI\nOkES8kRfJbYI4NKhIAyqiUcbdi4m0uVkMsp2GIq11Ok8qGMdCc1sTT92Vy16v9s12wUJqOmjYiJ3\nN7yQESissgaWzDOFR7QLobhaOisupX1t72or9KtxgLvmwfOp3nVCOwtjdymUySOh7e0zQrS90IO8\nDMoUCKj8phiVBovw6oqIdocKhgYAaVcG1O+GZbfsJzohnk8xh4VaR34Lv55Bhof2AjdbAeBnQebF\nyTHhnnnTn9BkFGhnpWr135xc3iEdB1yoaSF1q7UOfAN+jqoxuoucjglLnFZTQhuQq9PpZYSa6qF8\nTeivjaZxGDbkyYWWL/mYtqk0WyphJmNy0u7whly2EU/DoKhN/eRXMtOXjM/00uqhJ7JkyMzAzE9r\nmUD3n2dl0CPLmPp1gK0wYPYtuvSljftl/MAUIPRSORtUtXm/y1uP/U/Y3L2xsG0Ohe7scOnXBsHT\ndchQ9mJDXhqs4RaspWBB9pGcfDuAWFmLTVWNYXTYwaA1THhgpjvb6ZkQho0h2Cnnu8/1kbl0RB/u\nNSfDkNDtV0Grb+Yr+kMRdQ+KG0Lh5L2nr/aqWGnTUHYsKKBfLXDWDfz7XmNLdzCibYSUeGejKDxt\nzJVE4+riZIRoFHXw670hdRKtpykl3AGs64HFWAXJRmB6q07KDdzQa4S44D4hPVFlq7LX3GRkj62k\n2Ab1JTglaWBPwajeRO1Uf9BBc9W/xOAyW/mo5dr5UZA+HgP4mMF2RpG6f9kn3R/K5koqQFoce0Qx\nRkp68YwPn2ATuoyq7V6KsukrqpUiqNiGyVgUAxSQ1N0SYamfjXchVCDrjybUZXUqiCUoLNXxBZBX\nVJG1mH38TKeO6BHuCf4ME1J3AeHx6uW6ToXGg4OERC7ir5TmyfX1zbN8kfjUx72YHK97+nVzggPf\nhV6PSNPyKapvR1hP6KBtwOQThChn1Rha8jrWU7qk4pYuMmTO+8FPkiLzhUJg7stmXs4vO7A9O4k8\np4SynjxIoUWmvnwHNn/nmUdxMc+9Z7oruUXfW+/aQtTF0JR4s945UDO6/kd8G3xE5qe7Vy9xyoa3\nNoZyoOd2PSkxIlN85HBjNCL/qE5MI5kpuFEkWjRezqzktKGsbzjACTlB2feYN69/qwaiLrk5U5Jl\nRAspfMm/2Klr/ZyHoQP33X5s1yZwQmir6QqCsRghUh09U3l+s7mz/z/r+EgI81b3R0NOfnC5vNfu\n0ZInci8q/I+mx8H3rqYBWMT2fCeLkYEAAi+Z6Ppr5hNKXHo05Dr/TYBVTzzeAID60+nn1saBr3PG\nHOiE1+yWjaUYdld7cDPOi5Sg+qQ9MWy7ubQy/lZ7Mc6eVHHl/Zi4z3Aig0StkCLXUz8xC3PmoizR\naQmW8TyVLS1vvHEFzvw/FWgPki9508eOITzFfG4gEUW9CxlJOKyNTvUhVqdorkWUng2q6ssNc/dx\nbB3u1uMLZqHfye+9zoMGQb+FLvXH48IyUwpRsya70EVrdGtFGz/eJSomQJHT6mD0UUzbf9VWVXoA\nBlVEjDlvWqEypgNEkL/oaxZkDc/1eRfnKjHPXXPaBlkcdkxsDIBmu+qurAv8o6tna34A5xpjVD5o\niGD/GxnBCej1BDP45StBuQhwkzRUE5TI24MV8iRGZ+t6CMtHXWq6Ec/EXx+s+eMe51x7F56ZxXs9\nMo23Jen4ojXg4tZp2euH0Cs1p8vTwuBo3yA5lnBwO3OuwHvii/DTmGGAHK2a7DzVI2BXirlDP7Og\nikZSZhmGJKeMw4VG3DTYQR1Apm5U647jH3s9QAv2nrsEiCgW8APAZ1n8cIJENS6nElC/PlD7enCk\na7mqzQe9cG2orQ1Ktj4BmNwrbb98Ls37ssjSb9Jx+FSWg/TYmAji+3WqoM+j83OY8YEai/PWkEfS\nW/3A0njXyb51hCZC1gU2lfHaTucwdnnn8y11HRt3AtyaXJD2aefzU2h7PSk7jbXKwBBQZQHRM0uE\nDbFbxKjKSqv7UBlF8B2hg89FtxJ2elEq98HAZ7BjPEGPxGBFKQ5rpsiQBJ4c73hZdzvWk6sJgsQX\nSNGmVPnkyllQZRoNczb3OcA7kWrd19zRsuyW8bIBT//3nhueZ9ZD4fsrGGmxs0YL3hU6mz1N8oBW\nvK1DFOgjnL9u6f51K5ZcIf44q5T0id9+6pa7Im9qyI9YRkENyXX1R19YxtOS2OEn7CXxCrXEAvee\nqb67T/P3CBFDoW5wPve11RL5cFD2NkcRfv7GvKHYNzpLFASMGzli/XyfsvJdREgdAxXfJ+P2oLv9\nR/WPfJ9MrRfhXB+N9yVgS0+/uLJpsAPwSlkqr5mWR2ynT8f9dwLD9kq/6KMoXPwulnkrb4RdVW8f\nlu1uUhnfez74mJeB3HNuVgDhvspNVMRmgKO7doJ6P1TJHUylNnoYQ2OOcNA0ZALgbIAo9DjavBTR\nWfuMngkoCpxePRCI55Yx2lW9VLkke9nKfxwgzZjQiLdmGjhbhGGdhMn3bNLvvQ16U7wD9iB44r1y\n/E75B0b4JeII9324Y2yhW9qtWL/VftpZST7GJuG/i7q7XgcIM3OCinME4YbE4eKzxpRWtKrEmgkI\na7JM6bpkjhe7fCBc+tq5Sfh86GFORN+jKo0w4NGLf7UP0laAgWKgKf6d7oKMRR3cP9a9/Zeut9zS\npgZCXFPSXno2Y7+clV2ofOcqQxL2s1QHjoup08B9O08Y0qcY87G5x55C/p5/oW0zdRk8RC8mOC7C\nkm++49eNIf3ssG9lkE1lnYYYrHSiZvxB/4evG/JBSRUmaLSrP/W/qskh34H/2YIaklHJ4SfafFvP\ngG4YcODaFis1FLyyToE1f1wLg+D3IIW1QJRi+5CeAbbSb2kmQ5a0l1Bqk572U3yR4PfW5kkVBlfq\nymdPpUl3PoSvhDtUR3xkAxGHAz6UqWcc319nJILKwLcH1z2ffUj7WdiUH0HI3X4QU02ArKjIh7dv\nhiC/Zx1AcOBQKhZ4m2qm+EobLULWuM0PWeStmZxYFy5E/XZTGGWOlHsSaRP81JQefyJn34jkqiFZ\njqo9mw0J492fwA2JYya7RzTECKjm+LP/I+Krppsjh8VVXycF5KiOIFIcm7Mkc1q2fvfiC/qhhrcx\nIkhOCQHPn9hEuOgDxKmS9sC5QmmXLoQyU6BMq+dnKUIh5gab1ghF5VKQCg+a97qK+JOq+V5rbzkY\nWNc9q1QRvUOe5UimJGMM5kz0HDH6uj+GXVGMj2Gh9cSyyQ9Bxu4KW6UL3nGYaCpcquTAyxOoWk2s\nkz2g3NF7X2pNP9P7JhEM+/b1fqk82ce6BnmqP1A3m3i/keLgw7ESg4JCN5Gm/GN2atbReOft0bht\nWn+YuXJf7CE60OtgRo/Ag9/OXwfBBYlnEsazQVGmBQceXqnEZm28ZnmSnL0YlFSl8cfFyOsgi4aR\no8dJWZO7A450GkHBnng+idVd5UZm6tTeQ3jr7NAMAiK2RwW297lMKmd7MD87eF4bMX6+h58baT1D\nD45nfNjcdCwGHU+YF3/1a/wkTgtYZYGqWm0PHPjEuBailGTvmOs3FIz+EXDwmWXzkgraGFjJUciF\ngpvrRdXC0Lis8wQMM/Yf6ZYqaR4cMDq2ryowgD4rJGLDYYQd1LDT+Ay2TfBPkNBOe1yPbj4ZGvFi\nEW1NA1AXcnlmyXf2I/Q4eBUSJRAV2JGrMHQsWaM76HM3R5vf6ddPbHxyAteHULIvGpJQ2wyIV/Ty\nKaPEEZxk/Od8xSSkyZfFF/aP8dY5qL0LAnokeQrBcFci9kIiNhB9RotAhBtURWiy64MGw05tWMDQ\nSD7PTEEaFQVRpB9GIkxPXqP/PKPmGbc34XfWdaCHwDO+CP/ZiGHJf0cE4C4JaS9VZ2t95puaDS+l\n60bMo+qiHfi/aIvqIcM7h8s6OBKhGWWHwDqiYToybqQkf6kEq/vC3XSBSe2KEQ5pzMIeG7eTTtmU\niK3unJg//lCXHH7v3eBZykBYU5jr2CW8V8U094N12SlAjUV5WlJHPJ1c1XByNEXLZyPrPmjkFYOq\nL/m7pKPhv6muIk7AWp7o8ofhyGPI5Gq59y5778BvnFcBM6LsDRzxda/kCdV9OVoUvE2k0tVDE+dE\n36hkvpsEV7ouccRINpDNQhug+uKJPqbyymBKrNSpU2bbxs6CicC2EqFXn4SQsof2I5OSx3E47V9o\nROgMSi7MkM8fRNazKSt/W1SgAe3go2K8yw2/b48uikD6JP5GDgUPS/GJU3SCuj0IS/tNxDQp4c+E\nSWDaPNU+bIhXNHV4PxOyS4yN1mA9DqKdkFFWo1TyWsw88jL44aWiFmZYcCwIqQYmRliKV5eQcqWC\nsmikz4YnEXKWjU4iVpSW31RVRJ/iKPsnX0dyHd7mH4RnIJ6CvFm/QFJcQ4y2SlqBJX2mWQr6i6S7\nhQe1WxlzJhdqhcrax2ggUBgVF+U4X+7xXu9Yyk6Ox41jhJPLLXl2L5vxRuAd03jO8mCNIlzjKMH8\n/MRyjeh3jHm/8+XsX4HKe0VJDj42OYj75UEg1xnkD+p0cDyqMNN1JwHN4VDOfPvPmdWaiVm4KHdy\nTp7lr7LBeA9y4Ij1pa64DiGrBZ7yXYsuOWIy8PL9zKuVy9UXRrutTi6q0l3oQyFCdj6rX74bGX1+\n7uC/5vYjg8dg4AgBwd4EyR65+NmD+4abjSUqnFMzxND6KKFprHTMJM1G0Xekd5Hm4RniwNdPW+wy\nMmn2mVAm0ziFpc59pzOYjenNtD7FDKO80tM35kRuXQWiEM9j6mtci876JKgNB8Sut1vgeFPjXW2U\nePYuoyfobJzVADIRPmzSJCaz06L2TlVE6v72JNCzzC2YFEpzQrNs1UWNcEPGDlWatv+XkeL8vEYy\nAtsAfTBQWexSLUrWYb1gw2bTV+v6oGUo3a94iwjXpUD0+udgthtitWRCY1PvizAO9OHHPAopFD6H\nbGG+fBw3I0ARV31UEN501q+TCC94ZH8s7TylZzY47Q3IZbQVcmzat5sv7cjGXubVlUeducDnB9MF\nsKqXQUkQK1U0HOurDr0n/miwraaOQcXjPgopYsZ+1QzwQJRLuZmBJJgHA9RIdxZi2fV9x1cuRKHB\nQZZzFbBtBE4hPVNHboKyWtX+X5MBE1s2t7V6fDGX3VQ/xA9un+HImFLQ4zUrR4XqPrHgzVoeZDpW\nvp5F1leiM8+hDKZuoPk3E+rRN88QEX6i+pz0K++3N+e/OhQ1c7JlDBm9ibbjXCFqd1Y1GYwEX3+q\nagShxl2wmZ+tpcR9yzczZ3bH01YJjVU/7411HvSy0JblyailvSuDaAHtS2gGiNK+3LZwkG1byKb+\nvGJxdzhKni09FUF6+sCoXhCUMeLKPYeZ8qubqwu+q31gFcYiAOwgqVnUtwLqJeGEOP9uyVJwfOt4\nWtIKq4gkG4Eh2rFgfGTch+XTs06IEhrrrZ7GQMmUlMY2YnS+bgA9VdfGqmndpJk102I0xYBMELd6\nsVkLqSblDZf9muBKG8AgzAkiYsDxwTU0E6yAH65MLFNz5F3W0qZZV1CKT0nHH3qFf09K9CKAM40D\nx6Uc88tEOFsKiIT7UTGrv05/Mn2STirjyywdQfjkKcJpwqNuBoad2ohKIcKWUxvNyyYRoIhc7T7Q\nHqUw9Ewv8cNvRMXjWGfjn3ADinlVJSz7uhM7oDuavUPjlTZyC3PxUMKEAVcw+EIgoj7Y+SHcB1f4\nGsZtLYb16UfcTST+D77Ul3mNN8RivDfFQ9UqBe6AWH/scaP2uB4f6AOItbley0ccLObu+ZQu7tXa\nMTuatLllc7Rf84Bp+cfx1snDkoFY+xoLGwqx21Fl6EPeG9038MqQSbTPTDeVF+Au3QzixZBfD/nO\nyvQ2XpVOHzBLdB0VSIs4TYy4sF9dFmlFf48YggADX0uQnS/2vb04ABz1vzZvKF4RKVAjTyWyACsB\nVf6KhqegN0MgV4Z9fWsdrhrZnAQHb04agGe8wqSRYbEtHr7WVJUd1tglKP5CrPhslqu3h9Ier1GS\nMNsHYq0pC5zuAu5vV0WAZrkbVJsGVzH48xE3CCX/UGRlYeHid+QXBrFnoEZm4+vKqztIxz8JGI60\n8tiue5wZKDJZA/WMrAydNwrP/FmNt6yt0LA9cRcmYR+snH9CJLK2K3Fi6Dx1uKLRwLXl7r3+FLc9\n9szMVpqaU4K0yGgXux2jDaRH+A4Sg6ItNrDuabqMr99WY00ICMZGAUHxgFwau6fjlOtg0YUDrICx\npSkvrzRZiyba0lAwL0zATMKYlYOHWDJ92hHNILO6fVxhn6Vj5LRLP4hS/KKqeHFSf+DEplap4MqI\nUtveYsvA7g/dhz8oJ2FwKUnQMicyK+r7oJj4OjOxUcLU4ZU2vbRaVmfgy968gWqs8DNqFDNViW6V\nBy1HD9NwdcNMbg9S0QIUSkBidGb0yYTfYrYGP9Xvu2BM6NsrvZZXYJL/HBp2tnNdjT4cIFwum3cf\nelDLB9qkzrGBBIkok8ywHs0H6+XVLdd4h5yj/tZMC7yDTXGkuKRWhn/Qbexrssl2rUrU3+zDi3+/\nNa8B45lL1h3JAksZlbAf1OmzG3G0XP6+IyGQCV/WyR/N7zyaRkAYMQV6Orb8QGcN1GRJONkDFu0L\nepGDOY9Q87pEghCUvs+veOqYSyYf1WZnFwMoImn/dyoMwJcIy+tRRFN59x4AqfK+eRYyd1oiEPd3\nty7LliR854/kgSc6qWXCNfUixKllSHgAbHep9StrFIbQL8D6vcXACNgYuyopmhJovCKpGOnbMhrW\nk5hpZE055rPAHijpMfg25EKP+ra7Id1wu4CZMRAXLHLQU2cSkci3GTSovDiZ/I+3aeWdpelEO9F2\nEUazfjcxdubRNiGSH7AcY2fDvBi2L02hn0RJqzbIsdbp4r5+1jjyTTCNuoNnj5VOUH+WS4bL1YWW\nqoJkNX8j9qrMcBHdqMFj2xwNDZ/4ooYGsliaETsHDNdBKCBaY3UJwe6ZDL3g3f4yZXLPeuwjvqyW\nVK/z2VpwdRUgYglI0mFF88y7+05dXm/2d9Jgp5GJnQlNgP6WazLf3UFXFUW8iNbkS26zstKlwqtk\nkM2juHyumvYu9thV8r4cf7SXkeEW3l7i39h/hcJesLLYqeIegDmZw7+tceS2IdberB2zTF9oY/3i\ny1Qpi2sVaKAuKe7fqqzYDGJR5fDkfq3kCuz1B+PfxpSF0ogxBfYJKHy73ute5wrsxoaRQjYeydsq\npfb0NJso5vMOYybgK0hrwsH97MR6KGWf9dRf1zawwuWhAGzDoG4gwxQ6O2s+CuSHa02JY8eJgC54\nwUEHi4IWgEGv/15g7HamrFTcmyKxJHPbIsDoSRM9iN8tBi33AU1y6B+tWTWkYe2sVt5sancFVl4W\nvgciaxoBRXNgrLFo9qej6ILriqP8eAvKz5NeHXdCQ73W4oDSk1saQjQqSO7w2voNnkT9PHOGSpqm\nlYGSAVDbelg80OQOvQ4Nj6i031QXMTON/t2S2LfPiapZEOJzKan/OIe+H/giAF9KUCeft/lFNqZK\nKUD9L+oMIMqHFs3kW8y2jUORPNw97spJMiTDedTN+QLAtLEvB67n7J2WCgxlmRUGZ4hgxVNZFwN/\ns262TFL0utg4Wylf7B5TqpOgRNyenuIUWYXnD576599yRq8UhGBOGCnbyXxuGpBREJZOPYBU3u3O\nGj1gRMLSFID2KZec2CQtGX8XjrvNWeeM67wxomAQeWZqvNxfzMslOvb5JB2mrwBYNPYRWqFvauYO\n3awSQT7D6lArEsn1oE3a4fYfrnfd5NH6ltMSoNsbGW6wTu9+UoR6Ox6nAMx5Huak3idkxZc4uFs/\nI2HqBNQITyKBADov9WtdK0A6nzmmioPs65MaSEBQtHW7uMmd3SXBY0mLf40XJEIEliw/S3XzyHEd\nVXZJfNERB1pv3uGBRTkC4vzVne2rEOnpNCePZRpq05Pc8n1oTRAVn8krJylxrbB6KyDqqBnqZPYQ\ncgXU/MTDnc1bo/5jH6YbS4TaWSKp5F9P/xJYL5wTjQF+QiwtQAe2T1CUSaJyxGhx5KrWCCRqF16p\nQQgISK5DjAaeC7MvO8vpdNpRTsCWOlUHXvjRRij6UXmUGdpNqQBcXFxuzETJ39/8VrHeD0cA5c90\nzv5HKYG/p3omUAxwj/IqMd43jRg9UvHyB12s9FmiNBHqtChqRoGaLJ81+ANBVIOrTKqBU3EKYMtN\nH2+26VO9KlivhU/+ZxSxlEnCaZ6aaJhbc4ohIP/ojtRmQ1U3PsguRfpkLYFJxBnxEgP616L6qF5x\nxMTaIEYXiEApJhYn1dFFTJxckKkI0H6mlvxLfgtQhfw0dM/PS1vC2zKTXnhYFD0IBo537wphFBkR\nqdbjuphT9NhVKWN8Wl0C+VXLeMhfT+gWgVMWzQWD85gT2i9zxqUtVckYVO1lVMSYff4DU28ofkKH\nD72y2WgKGyaw0ag1wXT/dq/fZeR8LVyziFh4u2JN+5BShbmO8V2Xk8RUkJzrjK4fiFt/g6yYMlgO\nYl15c3pZx6kHiW/ckUlMTojgOFgSETXa1FOWAPwoAys1Wt0tscgMAFdUTZIt/CFTb5qKc5yDJ2c4\nBwF615AMYBlMzRf8Mao51F83L5VL7iICbzdI4pjt6vEHYm/bA8whViJemEKxV79BJ64MDftD7Vzc\nXyYUxA2/d2cfeubMPWwpBYI5PBObB245VnJddZLCjgv+zgllTrCk1wZf1pt4cRe3c3Uoa0Ly4XOW\nxpXbiL91SwqAr6RYQxwmhy4alsXf2odG2Os5V0pNxgLLUU4hp1i1osOdJpcQxYgValvjAuWVc5Uh\n3RQBnaWm/SMm6W8avIxpahbiMdP0SIU8RmUFcbdiI6qz+mY/mFNdB155UMAJKhLq85hWWrRgwN+R\nY2VNc8eP0awXNxAoncb/ECX+nzGIPL0TY+3fklyhBq7Uvwepppq4J4Mxnsa3Pd54+3aUrDwbOyMb\nilphgDTCsJgR/emMcwOyuzhu1aO0s0fT4vNKhVJSjzn8Z4ykTF/wU11s+/7zOMeFs1AAmEWcwDwc\nZ9vClo8h7om7xHs82VhEqDCL33wyHUMBO3yYa7zqevDYpqYNhJIkD+GlJDCw7fxRTIb6sZFLaNiC\n6SY38ihJA8uMYF7A6G0g+YCuGeuPp1olZtc8gWJsT62JoZWa6VlLSL7C4YDdxBNFZUuGgiqWniv6\n8ZeuN02TLgbtUpqfFDQqIvCpMzsRifmLsR3078zxdPJKT08gbK8M/NLyac6PQQwrgbdl2kyuVbFd\n2xodCIw3OzQlbH9Bm5VaXsLRBR+Ir6NIdaCbztB64C5dNZ/y9kknIDy74+3qTowSR2SrOkD7k6Av\nd5IWZ76z9UZL7Yo7HVj805TLHCeXiLFznxOpGqqBDd4No3MFcRH3aZeSa1wvhkd954D2/d+KHAsj\nYAz+YbNFaDo1BIV0/kTghjj+oHeZkWJ+2j2/omUc3QO5wBD7jijQ+Z54Gh+OCAH3WDQEws3ULQin\nJcevYDy74pqhRQWagT7/afbf+Rcan3aK/JM7mPQdCQsR5nchas5NTV7ZOJjQbIffMuCk91qUOhMt\nwjv3EXtB9tcjuHG8/k7MNCwDDmxm99Naj0Dxa8k5DfpNw0thp4CAWdzh3xLUYU1S7ZBMNlZwQUMs\n75wjDY2yMCqJoSVNey2vLCxDnEoJc326rWJKxs9n6VyNsA+ypRs+PJD2LBb3j6b5F25ZhxAMI+E6\nq5BjixaC4UqadXHMr8gLjte17sZqcSZQShcdqcD7SDHQ1fVozvRyhYVMgI50zIYol2HQhZhpgPT2\ne69PtGNbceyBavfkSRTROcz/EVQpFI6tYcKO+Rph9fhHKM5/Ktt5aAHUaUUyfLnwXOd7IQQT2wSr\nqwH15itB854rdhmlpCEFKK4sLQARMy90l+pZ8FkjtA+Uh6bXzYP10idg1a2Yuywk7fB9up1CUoSo\nWM0LPUoQQosjZmPxleaq8oZq8A45iSa3R3t0OpGWtI4iT2uO5TdqeE7P9/hCyREaYx+5psSS/Wyn\n+egqLw27j86TRYre/TgeKhF4yKBwhPVX9JpiP/KIvA8mpkPy7pJgWSDnnGQ3AfBC+becxsY6zUXj\nsgi27/gHYdM5JpicOs3z+/kT59v0SZYsLsYlKuu5SXmbMyPa1Bt2GDJg0Rc1p93QYxy/wXHBs/rZ\n1XqkCwBg8iDKGFF56lBRg7EsNu1iYG7HkMSqKjEnwj4U5jkvh9V9SuicjIGFcr1pWpJIaZcSWNM8\n/dcfk80bPSp01JjlJzowbmsS6TuXoZxe1a3x+qBPU6ddmDuu4ZkrV7DB71Dl/oGnYTkYCfH571Ai\nSO0Y59/L6x1azSLrE2SJqA+HICB+EL5XXPXcEAAQNwMS9chYxKaprkwLOlqgOU246ucXPYCq8lJ2\n4ZTe6lvILX1qwI99aZIxYxm4GCOiDY/vYJoMmQCpS6rzkCBVTSam4jTPicHatHLxavi9mw+gB5tQ\n7xQ59H3vdbMsxm0LyFyP0o2Ot5mNek0azemUsSwQcr37suK+72hyBRKUqBhdb3qInlhETKe3Od0r\n/C2mzJ6yZK2pkuVQvUR61Xjr3xF5WGGrHClOldrcuMzVnJyYPH4IzUfW5rDeAotBUMbGj4y3aP03\nk+bIvoIA2qgQBdny8HT0E8KlXZJ5kM1t4oc594YKzplHuhpS0AwuI8XLXfO6bmEuaJH8lDTdHVrR\ncR9QS4tDMaY00JOfCVa+VtI0P75Zxt1ByqQw1L/n6kfCy8wtxR5HucNAdgcJl3qDT7O+VHnsux8o\nBDUqjifWr9qEo4sN/ece5e3fw4eiH4nfQkW/OtcvShc2t0DbbQGnAtxKQNdW4OsvrHii0NfoZBzH\n4Dwhtih8AJ7CtZnBFMYpktmhU6k9ZmFrE7BSjwCSW4GqQU5fH4ynSeVVvouvksnzNJOinH+S0Uiu\nTO2iHdZP4nnyNFM8bsMXmXfXgesPwNP2hwP4KUDEGyyzX+iaZHlAD2uslvZ3RTHwtqRE1p3cdmrP\n11/bAKEELtgi5GSZTgwATfNUVSQakOuZFiF9Jd8XYcOV1vGaFX2qflcsxdnKp2RGZ0D3D4hJLL5t\n/vxKSD4E6aXyxJMfEnaqtX2PAY61kymfrW1zENc/V+KzxSsljqZurfyYPF1BJ3F+eoyPQnsfs6f2\n9D0q1QUtzDncvSVaP5eSF/efJ0ygTsHctOn4s8zvBNJbzF4x5684P9nP/rtHGQsc8Y45efDM0Dhk\nn/8/Ze18DfIptb3MAp7K/hie/1Uv7Y1zUrK0Hzvl/F1zWxhWxa9n+IsfnMyJPlJPEjqgp7bMqygr\ne3BXH2D4heRCq/vGoUzAY+V2HTdNwGyXHRw70td5pg1C+h6IBdJ1qNPp24alhnnJyqHjk6078OGT\nQ2VIwmmHAHcM9KMX8t5RyGPJUg9BR1Cbo5TQIYbKTwnAv27tzpZUJyGvjU7d+B1oIG/7hkcXeQFR\n/l2ZKjNZYWni7Yt0S3eV/tejKANYuA1mLBlYS2TBrTiPHED6LGDEaDqnecE/4G6uzHvwNUQhAFva\nPhChQEtJHIxAf9TcIUPLnoUR0iHkyvf17V18VefVZz2ErwWbAVmiu55PUL/GBQfmisBbV92gYowv\nQe/4cvNddd2LqsySpVHa1h2FeM0tBBRSWh/ZihN1m5tl7ZWpEFfpVAnDHzL92/88dzAsawjTlI1y\n+IBnM3gx7s+8IryLcfexNm7PDogGBL+AWdIRvTSPVnsguflZLmuyidKXKrMlhEapoJko+H9/cI1a\nkj5NPNLuBQ8gqnpTg5IRnYV7L9N0bjs7g/dv1v1drAOPRL3CYpKrmTxJCNliLN3i3LdaRay30g3a\nCO7tsSC8gftJLcW+WvqzU/+VTH9z4Ck10BF7i4pPEpYq0HlltvxkOhmn6Kle5JLvKN8fhStFNmID\nCQEHRDtsknTr5BLh/BQBwRgTHNs8qAcR4cUOKs1s9s8+tmkmWgTMnmwi1qvwd7HCpCS1xrjWMZLi\npWwGuIKXM+tGYB3MjR3tR/QWg45QMuALDRhzUStGwMsU4CqcozREet87o9lSxQm6AFPtzvmNPdmL\nIKK3BUEN8OFjMBaZwp2DXnPfbiG4AguA4G/vjdLknN42nAbTWdIbF1hs8vL5/Z9xZbY92njcDQP7\nOcYOdPAwGpKZbSfiakqGuZIqiu2vcKuKD0TODy+irkRUavo3OdMlH+xP6NgJOk0nd0VPL27tQUU+\npSKJIoOnrV/U15BD8HMTvJ0NA70gFPjZLUcDnq3Z+NVKWKNmKUfXT15+yQFykML/oJNRUBglA471\nWBmN5HD24Fqc/amIB1AaZFPMM8JI5+qdc4x4dqOyWFnVXFwvQjWvK8cpbYl+wXiv4HG8Knq3qzxD\nSCejiSul23zoRldV+W83KpH/GmKlpgVqpP2lnd6PEDr4UmgDFUuBChwrVui+F73kSz1KaLUOQW74\ndGmpd3+xLSQOzd9dwQPjsnGubDSH9+uL+51FceWmynRp4tboCM+GXxFVSImCQak8/kLIS9FWbVER\nkuPLOdqaSRNlXFaX5dqLu9FOs6NafiDhG2vPFKj25mZw3NWsde3yeWLNYEZaBvQHsDFiWs8S2XN3\nLTtiovGNVA6sSQcuRRfyVMI/ha3MdUdKnwi442zgHK6v9Uq70joIyMKnlt+kKp7if/xdTRwNRyUZ\ncLcCJJ0vICERuj/w8bxXidDJ+5AJJQRx41QkM/sdlpybrSa21SN9I2gMLiCK0i7skDqe94g9gw8H\n1ElUfsf59yeHoSWDVRpIZTCvSlTQcMGi4bMC106DOUWlSnZEpbxl3pMmLh4NvetlTLuQWZKgyMdP\nxVP0KMJG1oMxFFwR7Pa4dKQwv0h4DX+M+gkzhr7N/mBS1CuanB/SVR4qXVHE5fqDEdTh19EVBMXP\nVuDWKfZgHgHyYTr3NodtMZcqZzajj4p5w4d3GmR1fNBfOfhT0Y0eTQNnIOrkoN/P6yZsnQVv1RlA\nDQ15az07JPF31fZqv6KHXSjxZRS642041nTADzgHJfd4srOEo6ar/xrmFzsAQwGKAjrOeiHhj7k7\nJ7HG2pINVGIe20OymsxCgsh7RNctTRKVcSWfgR/HhW00tqKw1Bt4qHOHRWLoBLuYoeQiirQcqDI1\n2QRqRI4MS+yPUkNIUe9hHYVhd6VTGEJXnL8dFCl7dkZnygrv83vLtwrhJVSLDDjZ+DAOXok1Qo4n\narWWg5kVC7XlB6/xe7WULKkhEk7ehngXgHLoWBgwJKv9qZIF/uXGdgPsTv0YQ+rs8NoejLZXpcfI\nGAztS0+hZHt7/7xC1cz+UxTCWGWqd5blcrlnqcGrSfTmD/2JfkDgGKLPMbEDaUcW5YkKXpSBUKPn\nLcApBcXUD2Q5OcdoJYCSfnUKzk1RAksACQmLGaHBCdaORAmwh41ZvO0wscOXZSiVBGLMuqC71Vn5\nkrGwefW8gG0sTAmG9kqrtc7zcK8jml64H48eUvVhDz+rogi9YVU72dDhzy/r+ul4jFAvBW5ULWkn\ng3k5DGRDnxAEEecS/D5MRh6+gFzUoNoDGWTnD65swWx5fd1kgPSoBxMLxr2jxypz2GIbUsIcKIk7\nTdxUfdnbH3/oS55UvcFF0kNW/pJjEn+HH80tqLHte1Pusesz0qhnltdYzQnLzKo8GyD9zpIRqN1T\nWt/ziUcfVClFxA53+xQ1oWlPYB9Oahd4tJtxrdfYdJeZmYEfw2DnrrdGwZL4TT8YE7nKGfJLQLoz\nkaTFljAqGYBDUIaY6aQZtSjB6GtDC/PZQGhkA2vx9Jl1tpLddl9aWJ38GSd5DIHC1EKmI4QqovFF\nZbAVbBXHoA7G1Esb6sB/B2QdjooCgBzwlrWKl8Y9k3olVw6lPtENtEhHgKEhZJM7PvtRX1fMaspY\nOJaK491y3gu471RDJSYXzLVulR63t2uXY6NyKNo35KGU/N5SsmZMlSP42HaloAyDvfJzAD1TvjE0\nHq4o11+b2hlzoc1oVyZa7gLmuDy0cPdk5j4HNB1w1B2wrAuQ3pL3RGUqRypLPH1Dx1HyeYC8o5b2\nstmzfd587YfJfthSYEgGPaozKtpb1Dq01BaORma4S4EDqkJiUxmPGEatrBH6D8ywS7/kxhlWp1qv\nLxEkrxtWr7B4pkG3I6/OvKn1MXj8F9rzuhyPtrxMmCD5Y2JFgLQJxTo78DNIxZQUkA4KVvSr91S8\nTwK6E4ISw7mh5UwbICzRWS5SXYCBkyjxhWUvUjZGiX8mWqUflwy+xCnzL9SATWCNuqy4vr+HSH7a\nKjjrHPYqE3CssjYh2Yr7NXgiFDL93iBeRznf0IniUZI1K4UmfvC1IcEGkTvYUgc4wV1p+34uyKZ+\nKcopoBeME42MRGnWYTJT+13msDO+RE8OomB4a3P+lx1aVN39FNdJjcT80itlp1H4kiYK38ojyFew\ncUwEwFpTqZuDSIylxxukQYdVMHtBm9Tk5qH2E+gKR22vFKRr4iDuCgnf+gxvDHlVipErUC1EozNj\nqskFIiX/EYP9ltN6QehRcxXO9IvmGfauut+VBGyfG0JW/J/ehPcQt1cKUdx/kCdehpC8hzHXV5Ly\nqQSDZ8EXiO4wNFGYycy7rbSNyimXnI8QROfvB0wQhoite26y/2SKIUeCC4WBPARhE5ziVzQNEQJL\ncPyf7Hyci+Fp3EiLJjsBU++EKX9zJ5EKtzQrKdvcR6TvmbcHMra64m8OjXjybGZ0vSF4EFZsb1zX\noYRI+X/WDWO6plpPHMx9acO3kip3zm1ZLeQelMwuAUZQj/iGeEdBLy0ap0mhYErB8ZH5UWbETP6r\nSB6NStZryM6J3awA5aHL9qYtnyRZiy+AnQb/2yuZeR7MCBImtkrsPPzwxXmlM+gT3dN7j52qWiiV\nF71BAfbnF8VnLowIVyCp36C5vWElRzdLMjEoe5A4Bi4T+/XZ3nk0sQN3bgrr3Sxy5BTfIh0mqj4i\nqxnonv2nOqFFjvy5c2J66N6ChbPa4uFbTEaizv6r1oOsfzA/mP8KydsBNjzKTKTXPZBooEMET0vc\nSdYp87VEDLCBdwhCTnCgsM+HIAs71V4WCFFe6lGrLNBE8StlwbRYDMXoVKDaWdcKLIAmNfg6dtZh\nOsJbyXc0nsWp9j4q9Azn6ngjLXMryua6TgyB8+XKR4xGNItS/Q+YkhfFz3r3OxadpryCc/a+v9fk\nGXRssaIs2mIYjl1UJ379PGriwmrXzgUT3uqMbZgR8kX6MDZGIeA1UIRExOvTpBWsRTg3GzrP550U\nbXWWobW4GaqTfyG6Jh1/x3OW2t5wIQatmT6YRQ3u2S65N5bCnU3uzMwCR4M6lCqpWhASUmSsww2Q\nP875far4IB+WZkI4ReHN4i3x04yecZbHbT3F3EoPNv+mBp+QQ9Hc6o7NRgxpzvKoZLBv/dHRX2mi\nN8Ank7pDaKppp2JRp5NvMFRsfKLDYZffwTjvw1Lf/A7nTxYgG7QxMuSv3zbYllTCnWJ9uwvdwk/Z\no4i9IC7gjaUc54V1e0G3GVsdd3xHD6OnJhfn8+4I5AUeYc925YRMa5UmNjeODnd3HZXQx4MkbGGQ\nCR1lOmNd8Fj5P485RG+jBnL/fOOWa5MEa3SBVBrYrMHVzX7QDz6fUrDGon55PX9GaaGwH6Z11epW\n1Qlgi7WMrUSX2G7CNCB7HlIIndh/dc0qoELiWD9l9mX9j7VBPJnq6TiHqdMZC6Hgdnqrpi3R7FfC\n8lOp+04Co82uXjmQNo0Iczd+2xr/7OTboQBafBPSie7Q2F6z0z0qOUk6usSC9QBwHUpvbEMFK5bU\nM6iueiQg0+5h2yi4fFr8VA6Sz1HxOYEbZz0Fa6pp2k1wy0EQlLoUPYjarR+SFUfshcEYF0D9s0o8\n44vyzCKjZIAuK6IEZV4KkS4E47TVYS6TZNpxnJjvRz6omquE6TcjYylJBynRuN0+RBu6RK/NiTFQ\n8HPNr3jvQMArx8zKl7hlGzI90MrAxYTqcFm3A8VW0zop/Zl9A0hVirVi4OOVJ1jGABljmq85LkX5\nleZmVA76a8NRhpho+1ZMzvPXafAut5WMLqBJiZHoe/uo7fK55afMZz72DThdck9jCpWYunHem50/\nD+u5oV7xG5JaZUGXane8xjq98nvgK1OxlNtvdMhZwOga8E4bGM/MnzZD2RN+07J71taEx9g2MZqf\nARnkl5s5fVI/RCjBQipGsIErpoCR96CwfwqVJqzjN/eQr8gQwwU8qXYUcG2+J4h++EfpHuppQJYr\nyUUF7OabsN8mGVd8YXg+ZLV4L5g+x9KoEzextUxJwfzDt0nhyKE2WGShZNZq3TZKIhnmC4GRBSsV\n/FQ3roATg8wqIMwqsk7KDZFUflV8Eppo2+xN3DnXkGH3W2eSeZF9Rh8d6680FdiYfVK72V83Ln4e\nKq3J+q8E6N7XX7E42bW9kvPds9Mmwm2VSclc7EIrV4uZjyzNyS0JaFNw0n3/pf0H9dAYyVzyEda1\nhY/o5FEsGQh/dF2by4sQn1VB93tuW+8AaID3jdShCY0Et4yO0qE/g39nEKuSXvnhm+KXflUgrBT2\nKrIt2eZ6Y9fs300nEEgrZfLspO+rEVJa6hIKW7rA/I8lkvYI8lUXpzksZnSd91SKdIJTUVV8AkCx\nPM7xZ3RBep+w5YoMOK6TwE0z0VFqVPqKGuLRchvjFX8lW3LYhKcQlIOHsQ1G7bjWZoliFKjVXJl6\nl2P6lVcyiCpG2Eb5HPssJMVt7pcztBp9rtMPh2ZqnAwh8Gq9+71+GkxGgcHZqzLzCJ+4348knY4A\ncJnbjTbcYwXtnHrNGnZlifNFYmw9GIOQUbVs3Ub7ZO8ZrbFKdQAZKXrqybTbeXfxEAIVilRuE1qh\nfp3LOwxFN/LysIPng5YeaMYWk7peAzNF0TrtmLW5Drlkn1FDBYVulgrPJ/RInPKPvcvbBqqFquFA\nL4KP76iR0dLPcl4oPIBvemk9UBQr8glQmWdIz5UaaULck0WlM6A0RqM1VZrU2p/dh84BcNqhiNVf\nacq5NZWVLBcKCMxuMQZfzPVd0TMDR13+frm5X59TvpA+c5xCosjQ+rSmwC34cYQ1FaBte6pBEfWd\ngFnRWi8hJlicd3+YamZHkHI2I9i/iDemhLsBvFd8e3rM6QlzToXjWPSBL8sWq5rgv3aVms1cf5qn\nz3zpzqy9cBrKmrRGNzVMajYCQtSJbCYNicHucoEJhyQmaARHDXYYgcAEtRHdpvIjKTeocl7KhIn4\nvaj0BfoLrnCsie6hTcShPdydvIwRZ3DR+3CQGD7EdkyEtN/+mbUGsuuNV/pXiPt7+5u/lhma1/a4\nbDXS7pCz/xGIPTD5i/0EmoMAUQtWO4VaBfB3/hNg2j3nPPBX87YEDykZlyOEp8VO6kFojRX+jj3f\nPrZXxw/n5ZatROVD6fxbACcOiBeCbPH6+nh06wdJk5TJm9GnvLPA4oPbmJFNlTOi+6efN/AWU4+f\nYKNay8VA/g7NitQYsH0o52EKzkYNC+U9TKDkIZakGQL0h1oji7tq/0OtIcYmgYiNSuttysjmhEw9\nMkhQzJpQdSf0EmEyZ0h9amWi+RfoZvDHwd0Fn5EcYbmaKnyfs37JMGbkgc69MDurpilDtWpQ8Nqt\nHkrZyhjidkufh6gboIH9l8STdqjik/d+8q9uhS8J6VoZ0oxiozynnqcqWFLRAu8NKqsg9YQgf1qQ\ncuuaelrsBqS5E4hu1ou+EkLXhDIKdSDiusmfxDe+0BSIBuSvH69avq/mUz1+4OdBNbO6WTnOg6r3\n805/pDoW2cu0pnrc/PbOb1PMXbLUal60Z3wYTlc8d8LwZRQwiKrpKQAobQmhI9qL1np5QHj19F54\n91wlOSaqCZCBC4dEEL13nuXvq1crCh002JXZfA3eXqS0GX938+NiOgJp7/iv3RgE5RsVHYwXun6S\nAoNNct0e19FKUGgF5tiSQzU/rDBZPXzlq44qSTyr+T0xv8KRxMhtcJ02nvAcNTNgR0QX9bpdkB+L\nxxHeCNQaWAxupYyXLSnf6z0c91+P7FKec8F755h+S0H2/Me0V3kJgPSCNV3Rn0KRpZ4wkAn6C9PP\nEt1hLR9CH0UxwVG5be4JEcbGoiPla3BXmPK3/+t2wNIYBIb4f6QZg7DGCVdUYrNlZ0LS/Nmzwl9l\navNo7Ms1NIFw2uougE7ZagDp50TD0gg6xbh+sIRu+8ZESh6Wo0xRAKthGBWXonoi6K0uR8T+dD1W\nOCv01D1jEPCihS8C3Fv3L7fwp6KomhFVsBoz496SfkZsc49WhyUZzuwXZ4a53jmEipmF1nNqu5VA\ncAOKZnhEzqDiCZ/3cxveHaStZ1B7H2rEiyR5s+59Z7ojfCBlKf9XdT3X/I0mrPaTrN2lS6CrZ6xO\nnRCxyI9UF+Hl2oGZAsGkCWgjyCdmZCjqFogp1QgwZxEhfPBnpbX+ystuX5HgzCCabGHhBVLhjPg5\nIi8VUzyJZVln2kp7gnzZO/4pyIIS0Zlur0ux5ZJ/a4PqEl3O7OjL4rCdcGGZJn2G45w2Ztj4jrJ0\nK1YfoFJpVENcAAmunS7Gq+53cSX2Gwk0dIcFYNiGJW5bxAj+H6L5DSZ6/Cb7+CypHlFqUZNK2dxj\nl272+lAKSfaqhHEtWHraKxJNclyzwFICAVt6ZEjRjYBfbErYXoi32LoEKHyyWkjJPxqx50n6042t\nfGGHJgweZ11inO0vFLQncnW+Cbs0wilFkQXRUX5K0YvqfOALRJUtKQmmY6NqmYqiuDHWNN7QJxzq\naT6iURSiRVJImpcyC/4EDKu/3NewooAo995/V6D2GvJYincFQpRaIQalv7ccHjKjRdYSOF+R9cif\n97BD2EJnXseHWyWcnHKdcTL+AvyiSfACTL8Rod1gIxlFSs57LYTE6ehIVF5IKfYiZhbvw0rXmMZf\nZX1EN4Ld1wRkp48+Ge2JTZhrBXTd+e52N55/fOBAKs+HRyyAYwWClBjXIhUGoRgF7xZf9zruuANY\nKnqdZksv5G5yeB7G//Zyil2ixpIENXBLIkl3jliiWuwBC4Su8fleYf+Nj9TdJ3OwuHH9wJ/3kP/P\n9JFF/MZsMIjyC2rI7cmsOzRPB60X8dPurA7XR1LB1qr589QtV2CMY5k5xs4Zs54BdNyiqmEB+kuM\nIur5BxPj65EvpW/I8WujpEmanfzMPFwosxRxj20lpfM2EWKCbsyHVhHH8nFrUnZld24fofB6EMVr\nl79vtB4UpIM3jN+2SQkEZxPMO9kI2H9d5Apau47AR8FmkRJHPr3EwEkr8Wx3ZbVC7SD7TQL5SX70\nxgypBQ1XCNzIvJCWwSW3radZnhotvJyJGrTWJMEPdLHGI7y2Pn9hWM6iBgOES9QWa5PzJt0ToFKV\nvOGNZhSYaIkJnPZYwVdXftE21A/SEKHRNkjmEc3S7zmzz9XG/Dqh+YyuCNpgFtdW5WQ8BgNbWMqT\nJOBrnXyushMiB7KJSdvKuM8Am+jWpxxQyIg8R8ljHQpXMCMKfY3z2lSjsakg2EnF9XCbYwudwI85\nHMGRhrItXuCAdMJJtWkoLQKDbhVw9IcDUqi2JjOP3LuIHDF+/uii8lNf/NLOeafGreQqbSlIlHe7\nYJY35L/MTkKagcJ2+cYo1Y0bJky53yVoFAD7KayWP+pFgT0QzBLXr/V0jR1Fv64gnJYRHeTVKfPY\nrRu1QB7koWIzJ07W/pEsffYFQq3rfGtDNsmTqj63xu9dX7WIP+5Ws+VPWDmx3eC+14LLDX9AiqB2\nX14DjsyzKwItEh4HOFj+i7vKYnVPjQLddBVILh+cmTaL7s2VOmKvnQBFCbMjXG5CDx9mQ9Stqsix\n7PJ1bPo0MQdrnAJIaZi+IbOQqdq0ApoDSwSNioMSZ6uDrcF6lMdrtB+jJQt4iAehuqa44VzfuqzI\nf/zUyf4/YIje11G9qsCU3lvoFaIAv6/iv9Ts7S4QIRFTH6THhYUh0XoHM6XJknkmbNXtrU7WfDAa\n8lP+6rRGpFjtaooVIJNxhL3Al67E8UomaAkha1RUl8WEzWd8uukFnUMpyxNTSX289u4qZyo8DynR\n/QFuXL8o4dOu2dPas+8pi6mRFsjUIivWUShUFx2XOT2eUQD2ZvIRk6O6GjnbvBEad0Mf/5du/3pZ\nPH+v39AQA55Oh7S1yqdqVBFiTmIrSEQauOWxqIaxP0WfWoB/bx1ilPF4AZ/w2gfYXUeuRNAGJQu7\ntCpIzBI6Mmse9zyFqPUVli4O82Gt3656i5jiCKurgN6qZo7lc+88bzAnb57F0OCGAcQ4ujYsFOB3\n9YqNoiRtllKJfevNltSnZgj5dQs6zh6zu95x6ZkEguOAbVrFbEETHeG7xQZyP/OPxMFitmU8AMXt\nRoWHBzweGOPgT0eUH//W80VPvzaD/QlLSAWvmTbGNa751miwhzsnAz4cg61fZMpfOwz8D7GkAB3L\nyKCAFsWJ9Ch5z2ZJp15sx33fKF61Qii7ds7NmITHuT8tVWtmek25QL1Ivb/B3nvZKYyhgZoSPXoh\n5j8LSBK8pkyHGAFEjdf+P5Z4FWD7hhb6Uj+2KcBZYzBNczOGJ4yebDtKvtdNP6ONMNZiVI8jqibX\n4ARtNCxhToRd2waMr4+DRR8Tuz+OtdFSNc5YMkMLo2owWzhHWonSD0GKbW0FeBqg09x2hdxTLDmQ\njCx8aTZOy59v3Nswn6YA5vKKYcoP3YbVSTEiz0m2N7hKWGq6eVuT+l+SvCdxKyH95MBus5OdsbNd\n4rLRS+ATa00SaKzUYFt/CFOmFMnHzsZ3xcTBDLgfq3cYx5CQv/cDNsePnLKgcLR10tSO60nLE+vs\nu+TJiuGbuya0SdYet37d+JtmwGym8vhN8PR/xtzJyeiXwMFjSNiaib2qDQdoIATpVHD2AezYpqu0\nmVJzuxP/AlXkylAAPrtZkcSBSNgjnbCa+MxtJ+ycXOoRBkrotbUBk2Wxo0uF0Al+/8Tr3MxsdP10\nMDneY6Pw2TEzM6AxgWDl+WCt5vEr4kgLcAeKjI4Qr/ZsA4Wib6FOTI/HmzZdWZvQu9qkQ5EXIwfj\nmlFH0cBGttN1u0LeBHzoyZP88e4mMd+zrFggeI1clSNDYt53EC1ldITrqK3sL5euyF7iRydwL1JA\nfDtwKhjW2hWx+gSjCzYXdjlLpFFUK8xFcc+p/QJatmGI8atlcHHObnrwRyeM/9MD4ULDrHsx1tTf\nHObGv5g8g1IFR1DRv3VhFt6hZs9F4gjL/raTAapiVyBSltZFAyDCsWbtzGaOv4E5DodO7Nb8T+rn\ndc7rObtC8ZoFqAGf/1180vTPWJqBkcfP89N7SNy50k5CPI3Rf8B2ohWcjOLUNiTbJ81AINu0P7Tj\nWlGv4awC27OYSfqK391U79t69H7cXDL5xZAwDCKZnKyCjX1WNXmO38GoxHl8T3+0r6WfTFoieBpu\n9fLDorbJz80cdy5HN57wPwrdXtJ2Nfxptsbg2nSGSt9L/3r6Q++rxU6m2cNi4tTsHLCu9uEUPeEl\nbYsQAcomn9gM7HphMUjLAJkEfh3aRyEbpL2lPCwbo25gmATke+sWDGfQ8Mec3mKAiVsp2v0LZk/X\nwzWwN4DJQHgPHMQ1bBlIlqMvOXXP6PD/RNj8C9PcAanwNmBYIu69i8fHg9cJm5n73ARQacmde2+Y\nLdNzWz27jCrVG2tpyHRoy8Epstw2/L+sZ8ILYsltl6/YJ3inALsfW+6Q/GBsJfj4bi3sNpJshHsw\n6tpul3wSZcWpgQ0WjC3Cz7o3qUX5FEaPeSqdKAF122nrNYIJl4UZK9KPo1YMSESMTCePMB/Spl6Y\n/irqFKucHn7jTcm7C66K1bSfyuE9bb8dpMm0WRRiueR2UIJ3p1q+wludZifxmE56ADbJhcG6hI+Q\n+1OzOJvBj5k60x4sQqPeYzIoInS7gdIoGnHEsRQuLJ2yr21+Ajaff7/3fsnOplvO5YKZZdUqW2ee\ndUfiYBfJTIPRc04Y01JZYc25ByNZqBYyYde0eKasckjVTr9EYu39x1WjMc4vekrEzonFbmNBMiHQ\nCsqG9FfNSajmwARndAgb8Zx7PnZ/8E1kcguO9LU7SZb38VZcPS5t+U2Z+ifkoGunm+PW8ooNNOYp\nPLj1pN7A+yM6t+eDV/VnTXjLhC6PT64Qc2JQJ+d0eVcp4K/fG/A7oMTJ9Ydv68U3CdRkwr8VvJT/\nn/CoilNnAZFBCr0ty+Xm3wy+l5CkyAQc+ZB112KHGaGab5UAmnHl9mkHH/mw8NZ2u79vJqNshD9p\nDQvXQesMPT2sgkncvuWo3O4NcXorJv8Fwe5kAgq/5LpU1Hze1uiYR5E2OM6ygpJt9aWTHEEAWqDR\nnXUQvLPKiDiH4nRxef07trRckQzy+ky+sH95PvbOx2WRztt52UT0RNlXcr43iejttpQ16HT6zV8z\nRg0keSYVxhUHNI5zCLnhPk1c2d6IVxODYZmiBAsr66so/6TroQYY0WgyYXRH0A4PUeG2stP3IBNk\n3uNaTLupi3XLME6p7pc5p7xnsXT5SlMt9QGc0+G6xAl2uTzqo5FTkJVNdPMlU4AtsxkPvmZlTRCI\nAk6h9ta09NFhZjcFY1jMCG0TPQ/71VfsaKFLD6CrwHixNcqfAr7VRmQOvDZuqALsr70JMKgUlvjg\nJe6Gc247XjNHRbMJD1jtYLReqnBOnVEdqyhqaCM+79D+EbuMonj0tChFkdEwfT0NMnI7OmWTuXeQ\nU5P8LFHGNcm4341Xlk+NKxjcYQtkT8hSF+ljD79LHB/c1BC95YtOtB+36W0Tb/VGHMS3YvyhpAVo\nIjMlSB0RNQJgyxs7yfcj94N8wapDIqqYtIRHZ7ggofCilhAnW7MFehZVF4nQc2SKsaszAN/HopMx\nk4hq110yRJ14JCS9d3hbkUgTXTO58ZmMWpdnmxEK31D25YfjpFa5rNNJsfWQunFG3HFavxpb5j3a\nw+A1D+iFz3qh1Z4JDXCSWGhIVebI+kkle26hoxz7dDXVovKlaCh+ojf6maWNbCVq5IhZxHeaqZln\nGsqnOC7+4USzZWvvTJI82k2HfPawYQGVE5N43P8oHaa+oXFeBUOOgWRFlPhpNIDn53xdh6kkWczd\nHolDLPMRurpG6Jy3L9ZOfeNZ55PHCXsyehjkekFiLqJTgEyiCYg2hgq0CDkLrbBBRin6y9K7JTSv\n7V2So0ObOlph/kYNKtAYyeetOwc4jj1lfPtpH85nhpOinwHILCo2IHWpqLoWxUsY/nUH5kk7VRol\ny384dewjc8sIGF7PH9BgDrimVND8PLuoI36frv+BZdHKBCqgFm8gMR9jTyLDi331rmssCB5xPPaO\n3zLvip2TiOXSAKLiZP2fbT2NlYkd/ISZyg+QO3Y/kgn3h+R1jVFORBH/OVC0bVGLlLoBn2bhTZhl\nDMSKXMl24Cjx88RNhH3+nRGxxPK5UOFvFruRKeNN762vkuOLNarht/WALfUhFbBzdMn8vcwcO7zj\nppOX3k2eBfMszbtT3rsYe3JVnhqtLpM/YbRJ94m5N6x6ZGbuhh/VXekdpULvyxALnm4A0FQ5SHNH\nA5DVOWLx3eYDmuhmvNBdnqqiachrLBWPpFQpGRwjdiRAzHLyewQRFxUiUaDu5fESJPJnUrVp1SzG\nuEjHdAvWyrFzHCa9YVc1s/3fpVfRIIkZXxAVQZuUESpg+LGXH6J+eC4LmCfOiRV61sByJ6fe6q7U\nNIvi5tBfyrV4E+0kqAr6yRAKm3SU27wZrpi479cyf33+gD2I0G5KaTZYmYzptTdPNpRp/goEY9Lr\n8RvmlCyHf3aXw27KdhS1zJXVm+IQV6+vVdRnFnb2h0TaWiz6V/SHOUWsDlUhNk0kCZY9BqKqtAbB\nICUbZ8ml3F9vBXV0bvYfnkNa7l0BOKXvMGyGzJWugeoGmji9iGiC33g4X2F8NAtfAj0FNbFXJUrn\nBA8y0IP+QrDS09eaft8VaHhDBBXgS5wVNZ1AMnXzKmTKEp7aJosywAiM0ARobcdUnyXx4NLPJCY2\nsbBFLK4wmDrGDhE/dYZJThOEw78eXD5De34/2xI55yWNXW/mZZkWUC6L6+NOGw8xumxL+BEe4TVB\n+D419LbKWfbn1a8cX4cdTk/LkIoi7wPi8Y6RPu/mumRqvpk4IWzSoRofTN28a3HmCZpZNUWLLwfA\nsDl/VOvqEBk9xpfMx7PqkpVhY3hCBsdflHV+ACTl1DLoC8goigg0zWXlE8Id8fCYEgjSiUiHPvGV\nAQfSV/1jyM92e+rwhn/7l1W31XzChQ4yuSdiEU0Zfn7PyTNvvtI/E6dx7OnMgA7cY0ZseMm8sru1\nyRGVIwLFIXZqVkn6lCflZhZ9rgvmXMjC/7ynSmjwx/J2KrP1//or0ok3ujIkwp0Eg3V/rZ+itugT\nC3HFxevIjUpdEc0B1d4kTmgC5geFaBWKc1sVu04R8zsP6unevq4PuW4y10O9y3Q/HRfMHFHyO8Ds\n1vmRfk1eLRaAOs/XPDZPZbE8GJyDk4gDP8up8kIQtUxb/Gu8brvM7RVv0Y6yGEQ9S9rywfuIhK87\nmXfbJqpqrdxPpqkR/5bQ62j5Wn4Ne/Q5VNCf7dEImHwM5wwy2l8oAQAdyFbXmD0J2EWWZOokqdbm\nhruLjMoGH28JosttxWkrn1j9EbDWpVUBnDXmk7gyo4oBUK46Ws9nXtdWW6CExTyYR3mKvVDCn7g4\ncTNAOTSAJlbhq+1AEMqW/5U6pC5sTGdGT8T2QM1dt9jxbzb2pqT4H6KPO6fTuEnkdMWmXs+yTLO1\nxPyPfy+LzTY2R0fodOINkQqGpRoJ8kn+7OD0rnF1K3js0i+af8zp7K1hs0xqnhKrb2vM1KidVJ7/\nUI6hamP+4KNl50Tn8Lbw0/cvNZbI4vYoGd7w7socIlvXsVI70FpUXbKZ3F4BuOHSmXRwZIJ6NaWt\n61TV1Y4nopsF+UDMbQ1oQs5x+IdHusbyTW/MYT+A5goQbTDuBTR+W/X1ofCbV9mBimfNJZi8d1A+\nzJBJOtDvHMqpjPI1FXg9543hPeU9/ot77U1jrNlsGs0t8rJUfkqm+m7Nnbjgt93gVY1as1/FTfrK\npQ+IaBaSr2Kv5PYImav7+EEtucC+afnKJGDGzuXMQTEHIwJvp9ULRL9DPOgRZ+oUEsEMXWrWZDIS\nTWRDt1yzqbS5QCOwjUYyNshSqmxTeZwaB+1r8uCsSVD1t3nVugj4qo7K7qwtHnHScxm3XE3TegtW\ngX7liXEXADZSQEx0COBYcOFOWxHGtCji1IBCWKCzi+aEyssI1zwmj7vqDCLBbenLspgOriAB5xE+\nDl6Kdtm+NvLPPJOnEyp1yTJPLJc4fDO50NA52QwFpnytW6H51XbYfbZWRZWWusBmlaB+n/iYi63X\nnOEe2bKeuuqA56UaJTTUOz1RK21NwnbQUbdQszFrtuH6aGbA3JZvuS+8ufmQHsZ0R4KEZQ1/jFxJ\nv8njYjxMVNXvaLcOOlDET08GNoaMooGbXGW6GH1Xda7DFlWwNKC4ZnUdYoEAEruIWST0req6RmEG\nj6rHJeehI1thHm6GSB5yquEitlC8Ryw2XzoOVOdryT/uRC8We5g3yG4VqwzIXdLnCP9GE02nSrWV\npbOwG4tenkLm0FihYLaMbvOsVBCcOcqmLjAzVT6Zs/hF4k1CzymQX2d9j9UQc+DZxyystVIFqn6Y\nfsHHUVyJQyVnoNszb8Qn9MtwNt4ieZprwP3ProPwMDWHGjVbZEGfuLeDcBIIIhY/HgvdjLrfSg/r\nobfkkxi/FYM3gj5bbiWdESCVM5cpIuahYa7FevzDqlSbKr2rjREYGYGq7RNWJZ6+cus/QLFh9baH\nxaX9iPp4OBCyYY+tSgmF7j48ysshUBf12gXYJIEdxqAUik6R8RLHGO6dJ3P4r0USqiVjHOJoei6I\nf9inHKm7ZhM2cMk3UO8OQfLA6EcvWLGoqw/EfdNI9x4Yy0uIZ5/xIh6P88BBxjjLRIzqDc/Rb53h\nGG20hpiZU8mabYqBu+NKL6FlNymmez8P8cJXEVV6Xfv0jWqVBQUuD17FTzsWGUjdh2v/UkyPc0FS\np8bI8vpfPt5cgmU+SDi3gQjdklNWgakfVAIklzgCRLfVawCwVbFFi8fNBBAlkzGn8EoMTiLT6u5Z\nijPffwgqyM8HMJMIlFM+Md1K4cSPffJVIvpv1zTQCOd2rNr27g2Al2Ik/mzsh7eGbQsfzP8sUlp7\nsfu/n2RQsWVF7JgOAYiJGYkIjM0avuaLQMlKHDLGMqFWjjBbRrORTpdfyHH3jQKcT6X9DeIIaYUi\nMDZUmxpWDMs25rIgVQo/vBTQ05/2FU0W20pafr2MDajzkrGOVAfeph0eoiqedotyrqWn7a7Xp2mb\nf2LdP2znBFcrqNk2Bbx93/acTap3vvTWyyU8V7cRgv51QM/k1XqMF/3bI7apg73tSdU6Nud64vBl\no0YuOIYMS4dmqLk35zjzrU0O4B7gGLOEVV0nk192MZJqQgfeyUnK6zo/XpEXYtUUpLkNhmO0e9kt\nKYk1K8pYXdF8PdWcDryhFYPjRy0c+L5vYIqtmCSOeATb6Br8/qN/iP3f2c6iTajDUTe78gJz4w1E\n35lxW+ktYRuNlBrtG74OMoFsmfHXUnGDACjZRE9Dree/MdoQqiTgkigmQmN2viAnBEU/QrJcwCn5\nPW+BcSwKfe6T+cn79AdsMNm6Ut0SU3XxVPJeEZhhrwvHqKMPNgybwb+mk87txn+8NKrTpHLU4mCe\nYqiPLRSjjMaT+ix1lM3oNcdTNkkGSS2wMCA5eM4glJR5yY6Dkym3KA/jr+xxhJouZQpTCKjc6ELf\nY1PFwhAeb5v4Skxb2rEALid+xFpzS1tqWLE3+eqE212DzU02lG4CpgOS0UlwZZKrxQx9LYSipLmd\nyEzBSEy4GVGLpoN0GroAb0TExF2TOk6w85TklYspi4hM/n6V4YQJWGO6lhTGRxcTWpqKb9FOP/u1\nupAQZfix21M5/xv54Pdwz5lIhKLcLx7F1QbrZUUiFQDTj1xQgrkhoL2wXEpqSlgX2xQTBsXcGr7B\ncEJRNPGn9+PoC9ldOI/t9QIfQ9XSzlGZXzQ/ZNl5f1/qXV1GgGayhLxfFch7oFgLsB2898jBomrv\n9xv7zZihVHFeJiNLN32MbSSZfwjoNUgQj+M48bsz1fijC6iZa0q1fO0IgisbZ9Gh/ezcxG4f6PPX\ngoCzyzf3GxBQix0FwDx1/ZXowTaj+C7xIQCp/WXvt4DH40rAwqKKljVeCuTxPo6qrEpmsvRUdoCY\n2sm/Npv8+vaiJi5kkRZDUmtFnl1mUgoOueZ0KjNROvzqOUlj5P4sQo9/37vR/XYy64ibJFlUMK+2\nxvEyJqBXnoTL3QJeaHy0ktHAXk0mz5laEORzXsUZlWeEl0Xp/1xNyi5ds95mQO5DRKrcNoxlUvxU\nO+MMICt2HZDeHOMhdFF2Qk39699AnWcLqo6MO63ph3KL6vCaYvY4HJb2MJublZKmTkM1xziP7TBc\noFWSyMEdI4+VEs0GzRatnFgtWtOHquiGeNEZd7ZxRjNgElw+wmvbGghzrgWZX/PWD7ydRgmrC5yN\nHCoZ00krWkcBHS5RCQWijDlqcm9tPwBkHAp3YQ6ZrdvTdOsYLdDWWuMhZhRsq0cVbJc+Lq03Hg7x\nZ5bqLGFwqzHKp3StkSgT+FyZ4LHysejI6rc03mYl8wtFuesfB9/q2qWl7+9Kg4mc6h6dDkXBbFF3\nkatV21PNaHAY7z7Mm46qEM2fSIBYKDB0Iw1yiFphsP364GF+e4nb//VpuaK2a0QrFDLl8J0Z/GOF\nDTJZO7Ly29NBNxnGQFU9dHWhI4xoxay6gxxuWQArVn0uJwKu8thrLWTjRR/oPVt9LRXMj6kDLizM\n31RKe308yQhcv5WMhgjBwayCrjrh+rY46ROumwu81VX7vthLudmpuFVG4mGsqLi+crhsyAFDHE1/\nuMnH3J8gUMytmy/Mg8MB3e2ZLpauiZ9hM7suuuYOffrkkBmdzhfJzTbXjxsGFEtpRykkflVOxu4q\n8wtZu/LDfD13tPNxyWwBLMZ7tXV31m9/+lrDv5ibaHU8LiWJ8DQEQt84HHRzN90HaebFLyf/JMVE\ni5hkb6THI7+R0nWtt5e7In+gm5JeLORx6XqGHiW6Ie9iZeVYEGkeA4XQVayOfpKKk/iNLR6gckPx\nWo7KQjG/QWN2ERctvewC0lAqAwpk+FL37jx1mAWLJWduZPswr3dkV/5Qs2psYpxmQ5vnxLH+LHY9\nxkOL1hfIbjNBQQulcv/oIKyUX2DPIgwofMG6KIIAi4BCyrjSJ/EosKfPa7LW7t0CZnmPep4bBSgK\noDhHUBoWMH2EnzlBcnGfzMwtvMIM1TeccT5xYt1sFsfUfFK51gUvh8R9MlmmNvjOZC/EI3gn0eo/\nhfZT/NOkd21j8CO57vpyMsSRCNVEPytYOwj+Wn61XgAB3omFk0KKt6vlqtT3uGgjEitGt1/wPZ6a\nvHwc7EJShbKFkZH0YmVKqQd/fBZv6YM7MlKLHLs2gZrpKcggEAppePcRFbB9Op+M4KqbXdSHfk+A\na50OnBaC9Q7y2qsD6ksba/VgJCnHTCd9L3tFmu4pOy8Lq2s0E7CnRzlldPbv/JliU/1wcFq51rL4\nZzpSRH9YuJqa0ROd+J8Qplzlk9omGGqGAy+dJZDrO1e3veIBchF93+kzHdEid/QTmbuJ+5pHFIml\nsPIDsb2oZi+u5pvBGWpGy3ZdQcRONgtuDPseygn5WesmITASS8ff/12m7f+ZIaJ9Mg5+zPI7pUXg\nPmv7FHyN2sEGgfaQA6CJcNYA7hsr1mGxq+K5EmS3l7b7eNBjLFyF4x+6VejY+MJfx0Zed0ODReJ9\nq7C9WRqOKDk9eAUP/WeOnCTEzLeb9uow8IgVudDAo8vGBAnPx2X/Bj17b4tUExDcxRcDSyn/PqFd\n3PKc59uPGumFcnjU9Yhf0XndbMkBzzMHoUW9XnV6Q9nt9jrMXf06OkEVCi9hLoZfrRgx0WBwDqKc\nzKIhlF/WR0XrRGgEnUmgBIehvVTRP+rZOpCy69HZCb2fZmhNwU3RkwZOpV3K/4XnkFakXGR1UJ6Z\n0nq15bGQeXnwb3fZLtWdsilds107YerZ6GyeufZhGtxIl4lTz30pDtHBmRmkV3NKntnJZyCntq49\nuEio+RClBXsKcT+P7Z/M/9Qz/owbImoDLFSdiDiuLEV/lennVJB2gQ1USktoOE5q+qngDnC0ub/A\nbraMAev00F/hGe+TjlxvBDJQhKl1RoTZvjSHtFHA19F7bXmi3csNWBN0oaiuhxYeGqaiKsifhwgA\nD1N9QILelVLEZv2mL/6O/jG64Gi7z7EnwfGyvL5UxW4Svq1wi15D7oHklHdg0GvzYlLLoEIej5Gj\nWnBmTLZcVGKnLu+XsW/y5NT+Lv91oaXKSjzRtIYgEM71P5V0GdYC6B2FXulPSwk19krUK3ZLIbVb\nTOqfqaVCu6izLnopC1ZTKQLCTwWud+246Hpbaeok6PZiWpUs86rRl1msZwgNKIlKZscWfn9x1eZa\nW7JoFQp+1gHYcF1F8Aq4lxLz2wED1iwSBWDROtbeMt2ZxVBQ1B50v2rl99vg6e2zPsrbJZfVaIBk\nyTbUMKhfqUfJ4rSZHE8S7uDN/ThbpWHE8NIiWxkNGz0DJMGYoIEEkIG5Uv3OBkolKzm1KKb0Pus3\n7K/Zxs21TMKYCjmQzCRrMKAYOV7zWvTqfIlUoF/f6HWboT/xDT8cixcsNYReTFd1JMOpOEI4oQd7\nwxSMpWg6hnd8k6oEzKS/n5ts/OXXOowqVIXmHHpNgO9HcaYpsb8/lzLBjFkPzCTDCbLb7TGpiKyJ\nIQ6emEOJLk1xJq6HLP6BT/aVDjXNwiMtH1ANFPH2xUd3mO3iuQkMYvXnvAEcfY3IJax5eSZP54UO\nsDSoZPs2hfYkgjFKpC8t1pJZiGlS8BmqLZBvhhI2sui+HY+Idre9XL0la8NJuKH6kZrA3YXXfLSk\ndPSdmr5VSCObddNDXR5KEGxv/1KiMrCpfFf5C2qfaszClBtQIaKrPS9T1iLUuHkhbOS8R6qWW/HA\nnmm+U55ei6NCiRgZQvgLgivspB4areYeoz1KgzLo9R8qmxMLb4/xfNNHNvar3PwDn2L4huG7iXGX\nNTV92tBDYxpOmEqinc7Da+cUU4tNCElpkjqW7qeBNNkj7mpSFSkirDEQtYpYkvyQddXrDhcC9wCp\n5ZPrI7gLtoUKL+Me3VUGFlSifAkNcRdYt3drm56tP5V58ysrAXKOWDjSGRf4iBQGClE9U8x7p5Hp\neAvWvWF4yJngczTlq6vZapEtp61w5PCwYmkJC/ZeQ4JP841QINknGYFfKLMq9w60ONN4zWXSdOtG\nXfIQ1SzAkdBrRrTn+iIpuNaQHWaF8oXcu7feEQWG9SvCH493dhSFWnZW7kt0OJq+RgByO0RyMUwb\nYkmUERIeOpXBx1ixx6uDi2SmUqwWRslD6WeOKT5RE8mInhcezFSkzfBbjav/ww4YPxs5I7+CaUUT\nBuD/V/P5jKpOELDua5bW7CkF/JkeR5PRWzLOmMz8uqgDLp5DYiKpkwuiyscUZJxLZLrveVcAi39y\nJDGOiQBaBmYasjNlgc9tqY96PG2wWl1Dzz0/pcqFiQ2PGQxnV5vwa2NSCt+GtNva1xBIKzi6ET3c\nt8sIiV5hHMMV2sLNC3VKCey+fb8daugt/PUUqXLuk+Ycptw5VPkA5yqqsLZqKTk6FYOpOHRjHZey\ngaPlrxP+FDmJ7i0eOg/fvR+1SZy0ErhgBoL5nixcviyds2TTW2d7AW0K+Oq6OxkOL0U0NkFEEH9+\nV+LlfBcGwlNuZQXcTqyAnVajvEDf6NWmXUmZPCyK6HnvAtbOLV/bwZ1S0PBKwIQTUwqU2383fWtJ\ncP8nKsUUXtIxMQcXXehCorEVeXdkYCStsnvdgkwDDupG2wxmhBC1VOXr8lHSzUZutbbUEAsnjdiA\nN2Cz5VaANGXFnNYwaYOi+zE2DdEMnW2Vbxk7aJku+aLQ9wGpHg7Ec2q19sJe+GcWAlVvlovbwXq3\nrU6vO+tPqXeIvzANnCS05v+VJQat2sLPkgVtG6GxAVaH/zR6cPcFw0l/sEeT37IudCwbb2neeFNl\nUvSmHyt1JGu+0bQ6DQGNihmGdIVNW+50jxaHcdw8vM55qfr7jQ9wCFcvesGj+vM21i3kAUJ5h51Q\nbeWXoqVk3W/P06M1wodyKKZJqlndM/130yJaSBM2kycQrpfL+Os6+KTEUR2nYdPXJnZ+KQ2SfLr0\nxB1BdrJU8QFoVMokqZC+HusrhnQhmkLEwLNs1UuVCuG4px0NS+pUO0Dl0o8xwCEww7DLwZWng9IO\ncusfpcupuVggip6rEw0d6HKhhaVShnZYG32bG49KLlpUwmUNvQikFqdsJmIa4WPbpjI0vUPU6Tf6\noOuuc6Wc87ZRKXT3Sp5WeLZTpt58vtmBFNrtt6h6RHIMHaB3k1eAQ1MtruCycTEu/5DmUI1LIMbk\n4HlfjSCWJ8n8CD9XMck5A6Wwd/hzBFFguPHWutyxPafx2+vl777gMzq7Ez5/dGJx56XKUz1gvGFN\ncebdqT83DPH+jyglzz2atVRick8pYbCcTYMvlxfkiWMpEVUluSNJMrS9E/NM+VqCxd6Yyfmv17Iz\ngXL9Bnvjyx92PvxoPBOCP3DuUnirUQr2CqxSE1qh/EYNnLELmUge7R9vOpEfhutQffMbbcXE2nZq\nufBgn75Xl6Mj2Qcehaa5d6dGA5kL4HV2NfnOxJWj4KXncKJZu/MU18yyg7QyCMXS0+woPw2dMdhE\nXfFeP1zTKlBtui6iXrgQ49XSWnexOPevdMBmtMLRrGXByzH6yKeLNxxBYBw3RJYhc+Rp1udayrCu\nXCYzYcbArMajjU/nItDLcIRgievi+jo6bCUOCajkZVAQu7xNHKzuHJfWFXhwgl915uXEcWEkN7jB\nmWx0q1+8GfGAl6/n5FIRoYROxkqyBzHwKvru/TCok4fN6gsOqBUASXI9sPLsxmruKUFGrmKb+6mL\njaXYuIKNZ7eEbdCnt+VVJo0ORWkjPavGn/6jWtrSkoGq1MBpkOoySiS4KXWnn2zRVLv3eVSUlduD\nKQnuU+9OL6njEFcc7joBx/KkV72lCJd8o0/AI+A4uKLXD8W5gyYd/7xnYA1f4SRurH1TTIO9s4Uq\n3xmhjZxAX4E80PhwhaBBQDqn4XZAKD1D01WARmttcO/uhQcGku8H6Ci83N2Bzrg0X9k9TIKTntrz\nYpCOIguBCu7qtM2UwMfsZWh41MKvngKIXgFyhS+d7nzgggX+cZ0ecK6Op1msayErtP6YnyPTYmp1\ntJ9sikTymk9AZYZ03oYgTP51t/ChaXfY8nYlPZoqkF7/WZKcxVgvfkECgM4LXGv30VYIwaq8A2aK\nE61i8eomgMLmZistiXiUzliXsVHCu3TEebgjNClZ4WSaBs82J2Gxs5QIOw6RTg1uqLgSWL+82a4X\n7CxBn7zC9mtVRw7TUPfrUNb2fDGdIdan8uI4scftd1EVL77JAyM211WYjSDUxmOlgkEscOklbYHE\nAmA+QzGnyZem7iP6uvqYFGucfXTO83SzGEwVit2B74aOUiFepKARK3Hm/PtXXh1J0+izs3PUhV8R\n0ycKABe2vqlQ4xufPQe6eruGAAg5S29qFZqIIkoDbU0s5Mr8K9jjWKthGOBAdcZN7uTHzpZkaE2C\nfyBd77pHW7UF0ZwcN0Ilq9NQdzlUdmd2EE0oRWRCKGLFqxVdX79nVj8i+E/E05qaMddOyta81Tt3\n/Rpu6WYsw11iE7xRlpUfH61Qz2OKDuSjSLL/hdhD6ElIU51yGxqXvDjHpmJ2xizHiMnYiSyYK6vX\n06H4ZnKK9D9hqpGAE3wviDUGFHagRbTaWql8ek6zjJKsMRDs5r7JHkzcHHnU4itWbBDzMSLLl7Tp\ngdWd4yCZankDM1/ZqOKzu7EOc0+Vg3vt3omqxM56leRF+xlYsWmljbG04Nx4GfjWW+5QP109uUl8\n8q4YkeFWc78UGud5ZBZC53hhHECXMfojiu1jE2MHr1jkQBbqTEDNEN1XNmIfr/ENDhQFmRfBLfN2\nycCZOV9W10XUWyGYIkkw5kZwou/u+6RuMiDWq4sdGhrC677D3D43keV8UDj5lAI1p3cFa3udzK2k\nVkqGZcPunsGQrUSyA7clYx4H4HFZ6+yfCLOxHqZIyg3ssg540AomsgCQw33ErWPpSyMJdzsbt/3X\nAxuOf/uJXttMYEg/vsvIR64RK7n430IxcWmyYdSYsuOr4l3HFyQSENU4W2P+7E7y6nZZ5fdWrTfY\nilD33oBoDQMaMVxivH1wRQozitOP0XfyoDNVWj4omPx36D16bl376JOltiffUsrykE++846DLzdT\n/1/z5JTMRahcxyMxaXOTO/i5x2plL0QRmg4iwwVGowXTednuRTbUOojAkbeptK7i/lU3Dj4f167B\nupaw1uOUcMf0qmOnwYlx9y3Aa6BYFdbGLkdwYRytMJiNjbNpDHM6I0EvJ+/mLNdN+msivODYSSQC\ni/Cvb0LiNMTB5pkS0Vwv7m5f0Vh0siHDetx/XnZWmZxEegzcUj6YjZUtGAvHYOOkxUT1dVc5RhAA\n8kvMsLFzBu1pSPCCNbtidzzNe/kZFi/C8DJ0MtqKx0x54Afsky3ss+X+P4+eRRX4i+QvKR/u7QUy\nw6v/izd4z48Rc8LnS0abQsAQ4FuyraN2mtbkCCrIyL/8qxeU/yUPUeQoDZ0YL9KualTbg3H9xWGa\nfQgBWrpAk4pvYROtxFLN8JkQIXk4MKKxww3ovpxIOQ0G2/JQYUk6Uq4OkrcjJWEYoYkZhT5loALQ\n9tMK7fVmRYjZ8jSknn9A3zqZvamMMe8v7U6+TDCSYzbTU4oMR1bGpWZw/nEW5YnELp1aM5A0HV0c\nCviQws5TAhEOHviv+nQDz1IxvBStwTllxRhMKoWBuspN8AwUvp/T7Ssl0CbC/oSq1yGzMyV2QQVe\no68zH7i2WQCGc7ZmcUL31AaXcDpZDQgkHmSd1Wl+c0/lWNOgBH/Hk1OxaLH+b7m6F44z4OzAB0hx\nBKUW3R7XbPRzbIULCHGcHc1+tG5M36MpWJTpUnDsZEeG6WyQHIiOrtPLA/lcSxRzqctHC/XUiSAO\nJ8HBMLM/chxVaCt9NCoom7TrCE1rauTvFMJSCrd4nNLxUbJXjnP2mcDmaewv1LvZ3alAaL++vVzX\nh1Om5BUC1R8dT/IoQ9MlaQcfaT6H+Vi8LF6s98I55nVmD563VuRxKAsCkh+wpnpjj5ZOOeNjn0r+\nUGrFFPvJVWJeM/frt4wbM0ygNzkPIRVllk9JbQvyy151sWMTlNRU9ivMwh1NHbLemlR2A0Q9gS/+\nSEpmWm2LomXHp3yefTMRlFuXBkQ3Il+Jo8lI8ksC3qpP2FJvOvd9hyq96scfXE2NF1U4AL7+nz6b\nDDln5XrI3000o2s1V0URNj3SV+EMiK8fe55DUtxFm99q18juKz3Htj9226ZiUQvMTPQqpLikV6tI\noJ8raMP91y06imgCEqChgybACXu/bGCBdOzSVcu275Gy4DEmxWxJpuXFIm60bGe4KGsIdDpbSbR+\nfPaFT5+remoF7pD2uTIjqvdIJoui6GpX0CRQMYASK2ZR5DCWXZ4LLu2TmpRQYrTSCR0uP6xLGm+C\nL58vK8CI/yFmV2GSVHA6sGQPvGgSm1z+ZJxeSKb7JYCRfo1z+AGu2aAndn/3RXpbAr3YuHXGpcgn\nC0kor5nSx5L8k+MH/q4GsKoQ7SoggCttZISapMK+67HgLhcB5VDR18j61WLUyM3++t61C67/AOkz\n+IJMVM8AQLZUQ/edw1f+eEcn3FH1eOICUyg2bc8ZPtrlVUyW+r8x18p2FTTcIrNkaWK3vk5vvzB3\nxgXQA0ABxQBk5gaycggFy+aDkkLtqFzzjv/y/bQ2Qr4/no9HxhX+fRinrpJEF8NQCCrWCeeZil06\nzmW/iz506fItrRTVhh5dwep05ucnEWW7UWFQxq169YMaIl+XM4+PlBBY3SoS1tC2xvoF2ibanS7o\npO0UNbBabQ4XZ17E0tkkT0cfpWKyaaECSmr4IoBnNZNL5LWXL6fopD2SM91hv6XPoWqmiZVaIpue\n3Say9XyFz64SfqUxnaFuP1VgB+lP5PuI63bqTuk5LRcLfTwZ8ekdAYVV040KUIXsE7J/l9XjHBIK\nlNVUpuf0xS2QjDit7gG1EhM3h2uMY+mwMjEb2aAWb+n8/GYyQB5TSpk/dIODV79aFLghCZlFQNzM\n3Vc/7nWAKCGa+Qlrp2N1X//xVR0kOpIQXz65nr+zf57QaMZImxEh7YiurnLlny3XVKBuwjPasml0\nX+SdbCYrtSC6XjoYpvDQD3jVw9kKnh50Qkvpp+nKss/2ESeDFIwm+yAwo6sf+n/v9d8HRfCwsQUL\nTDYgTUt/7d5YocIPJslKqAfv3rcyLDvkx3nvxkGQ197xw1DIz/1sPlnYyRHPGH2qziUJcH093AS3\n5YqT7IsKkWuBT7I2IB9OjjVvnhwLuZptKCsHlkJO1mLvr8D4qdHOrxrf2oRs1wTV7icCDw6Ti57n\nDld6pk2ZNJxKVguDHOsaLddgcWzUbY/xZH4LW0BFKw0jVZKg69DORN7lrfJQje34oQH6PVZPz5R9\n4r11CDYcNnzlkdfJt42pG0CV5HLVGOgHPzd2Zs+cwy0P/6AC5R343rNUGy2zjwa7/xKtekcmS7Rg\nLAl8Bn5juagcA+ebFnGK/jV+UulfUktxX9WnZbZd66TIbmnnTedHJdrdPbMfL7Xsn6mwhBtMT+i4\nBfN38A1J+WWe3C+XnzMZ2SVB9UgFDYq6a62XEvyw2Xykm/Cr2M4CuxPosYrZFl/J5WfaDp0z3dx7\nBBRX0CP8c5FeNhyPx0Aa4AvhQ7o8aAU48i+t6japZTALHzQDBNz9Lav9Jo+WhSpr+JhJy5SP5KbO\n5DlrY6WZxmZV4eZSwcOk5IjZEFQGcAquPk2eM0nTvaqi4dTL8nNMzgp9xAUx+DUDAkSZBWSNt4WH\n3ltlSuZNUzV4OIspZ6g3JSCWkjBbC906BiEUWQ4uaYMfe5WvQloBVxH+50gpyFTiba7a1z35GMVN\n4Ag0H9rmyXdbBL+nLXNNP+WQQkR02FNowavRCop/YCBpm/2pRTMsitK/yspzQFVNC8scWxhtfGzL\nnqSuvpRGkObG7Nt96nwG3HlpZwpaIxYr3f+T56L1e9UmF0KwylrBzGmV5Oxtm3r+/+TLuyZHHrY5\nveBRHQ3DMc/grtY3ecQD9A3GH4VgD7hHMs+P6ijLSzJsQgseAG2ACfgUrxdu099IuP9jgYFfCXGS\n4itpm0TAS/9FdW55iC5Lu3z7XlZ45SBkWUxQxh/L091ENMGFjM8BamRls12M5VT6jGhApKvbOpAc\n1MhWCVd2xXH94Zz839zTminzBcxRFmcQJrFvBseDcdbt1DXdvD0do6AQcSiNEu46DROMXOo/Fnet\nzFAfQqk2TUo5eXT5D4z0U3W6FuWfq83W2r+RezebBO5fceGozA4FOp7aIxdhWZY8NiKpmReF0eQC\nhqa328S0/eml58im88s+iH7MDRUUWskjkeF+d+anaymnU6qfhJ02TYfw89E6zCf1EN7RIkUy7fpK\njT4jZ8qqL/QoWsIKYV4xD8qwCf5rrQSk1nsjoY7oyan+ZN7BYxEW8uQpHgO/owDOuXOolg6BMxxR\nEqgk5CS0JzsrogIwEUtB2gN9ahsSuyqBlMc1oyxoHRnhRDCvBtS38A6hvoW8ikWogejBwjvo3+ei\n3lkC3xgzjDTKy0b23Z3Ymikav01KMFqBGKYEeSgLnxQlhu/KZ8jDixhdki9dcds3BSG5Lsa2RjDl\nzlu7Mq8aNuMf04ACWGPIjm4o3vuzeLqPpyRjCsjLK0O3RUdT6vSLRtZFdF9kUG3zfrmaLYkgpafi\nh4PiIwUtiF+D195Qru+8rFLYHNHb0sSfDA18UHUaHHI0s2mD5GH3z692KGRjb5MZraKgpgNyiadv\nzbES2J1S+QyYcKS9/F3+JsumPZtUgXbThHkFov0CdC/uoEa9fcdX8o0GsAlctqvHkz1UW36gosDs\nbHTsvharIqpT1HNxyMUlZxka4Yzj/bzI6zSYVCzJhb93eaNzQyfCnveTjw3Y4aNVCldzr3yU/rON\ndiYkIO/2n0EQAuEOcj5yY4QoXRNBvTAbiOSYjvl77yKR22Q13tSviAuvpXAUWar15QLKkQfuYqJs\nDUA60qL4DjemXb2pabsM+ySGk8MTA8tKFRVpSL+Xw6ltgeynZb/eM60neKJNxUmxiteDmMa+ZQDM\nKaKdeg/z2V7381sGcsw5WZYN2vvjTEy5Lp+uDnBOASoMMZ1AXLoqogE1qdeQ0Jdws5gmAxQajPaX\nrkMegjZof8oHOSVahkOC6NA5/OUFBHw4MqaJV88CPW0oYN22iByXOLYEuOgnt3264WfmEqDpJnIC\nTFy9WIUKpGOiRMgKrLiKBQoq9XjHGA4Sqxf/zRIpdRTqxiM3Y2RsI87h3NapRRcQOR/+SUDW8lA1\n3pSIZz+RFWEBMPBo0IHvDUfiHdUZ1U+vy1mVCkheANb9TCwEFwoodL73JIBDgOpp5rrnzKYfJlA2\n46JiZo8qGs6GPGJxTygYnRrU27tHI35XEjCvOMk/YgI9Wx+3QA5IW7AR4UoM/UsRavevV+z3UmuX\nigUIeP1zdnxYAHYuC00PwtkxpuvVxm2ofOWbi/l+M45CwOUQcZAikLdTz2Y5jfUYhKo6T/nZkC3y\nqlHqtQu0OSUs1h3qKayMigzKvHHhfTNsuCZYdqzH+xXvvCshb6oJSNrk0MbV6vZlf41J3IKoVO5h\noyG/ELfdPHJLhQzO+l28wONhyHtPztA8wM9uq1iG3WBw+iX73RW7RaiiXnWqVL5lrlS0CyAUUxry\nNUJPN8jnbQ4uK1ioR7YmGh0+Dfb/XKsNJjlL2feLLfz3WwOpb5YLzZ7WrI8/XTvVENZFbOP/6vdG\n3a0CNnMB6A7O1dHbUWWCPEFlwLpMznFD8oJBa2z/0jw5FMzl/IMfEsK+5u3gl8qGrHHCC5zg0+vk\nE+FMlint8OxthQwNZr/9wVsNmQ8wZ3snYJuAGQOmhkwNM+oYNtc+vKJKgAJtuLTudrAQnPR4QYZO\neIdq9l+lR9fuIh5q05Inq6KUPWIzgOX6S3QQC8h5efHlkRGG3fD5/3RxAVgB+RCaZV4IsULnyP7k\nWF/mSWZ5zc7wu5xoF9Ou5DSsQtCnSynxlwY2DbVBZWWr/vGQ0jux+e/8CPZfUknRPPm9DGtFAocW\ndYZlCeQ/Tnt2AIp2k3lqreNvsWELtO9TbFQg020n7pPEram0sGGvX2wEhMTI0mlKdIGgwbrrHZNS\nZ3ZjIGe8WLGwNksfSZkaTEZkim+1S6Qz80dFPQx/GzOY67KWBIlqX/fGhSudjJmNxil3o8/xUnP3\nIioBvRWJ30QjjDNcHUkaUCdncleiWhlOH7ptTOr9rkZR6LCM25SAZ73r8H36Kv88kjzXvk8UOCc0\np/Ja+p05uoLPlBsOko5ocbqMGloxlU0m4gBCQySr66QTt0qqZmQMUZJpS5Vivf6BVNkVXjR/QLK9\nLHce24dow3H47/pjXSQPS714l2uRsOTEbrlhk6JGXG8G9e6NQh6lRMGKcQPi9DdAUzSjEFCao8Zh\nqUeDfVResGNsfvhl1Era6H4laA0DiizyhdTXvO4oCXVkGvauOcSrRHE+IeTobJcOTXVq2gn7QZSz\nrG4Eev0Nk51Uxb8Ov9ZS0bKtK50SxYex0E2lfljyE+7b6i75zSsxdBco/D93BzpVIoWdEV4JoP1B\nsFaw0lCbeXLO3Erq26KKmiJlaxm4lJYNyLo3jWfR3MpBaLPGmDqXJb566lJbAnqWVQ34f4WMbWQm\nB9Io0UH4A86JKmt4Z3jPqqiR/EnvMH58m+se4LwLNfm7kcqrY7VMOFMD8FAXzn7leGNaSXhWDCyY\n3xiIgvV/xguc+ORGAEzosRGaZERTT4JTZPLaigh2S9hVQD2HtB/f9bzBv5z+Wluby1V8rLRjdwSq\nxTrcePEvHf8dQ+WmrLVahRyUq7r/oJ/wg0KTSfTjh6roqbhpUsx219xJnWuqjLeg5chGKITGHce0\n2jlrokr/RWsd/Ep4jnfN25tHvO3tYfwQlcElgAeIM1Q+BudXjdXG0jQN2XGXazNY132ATyNAVKSh\nbVvIiG6hkX2MvY0yBVqkb2PFVm59XqncdxXLYJqFdFrsPZRzQ5xAYRCoEb45ewS+T3yfsYEgCZ6v\nOHnWiWA7xnTcXpzkzb1cISP/6tm3YcZSHT2qWXp+tCZ3wu5LqPExC67Wii1B/L0mVNnsnsJj+KfA\n2VHLsC/zgQ22cvbdX+WQrjp13iFfZf/kdGhDssHTghl7IrQr7GYMn4IZl8zcVdS0ZQVOwNZKRT8e\nkvlOwVQcI2oqPepwCOIYoDu6BhM2wMWZ5X6p8RfTlSPXZfBlit0RdDwenM3eKmt5/eLV2B8wcvNU\nPtSTbk2os4X+1gy5flvaItoXThpK8ZLVquqza7MkYAbMt4dXDedwFO8yWuS5oDNINXUug/6l80uL\nWCmkNlHQ1A4av1NV+27bE/Ol5LF1v5UhfDCpTt8qQ8Lhjn4jQkvCv9eFcI2Oeu5VmQDCFgArDVvU\nDcrzqy9K0tN0pohbperrmnsu2WV9MSkp5ANADeAdgdHvFM917Wd36Xi9S83BmVRevUlyOcwDV6Ly\nAtGCB7fv+KvWsp8SeVw1MabyZpqUpJ2VUB96LEjNmURAhgjDTZz+aHg79wC5RlACIcxUNUopJ0SC\nu9oU01zMLcykXTbg5CmEFxVpIE4ZKZhRvgxkm+0bYOq6HhurtQep6C+oxSWmYVPj3LjxJbnat9Is\nZgAmAM3ykFylmHGSe5mI+RyZYPZqnuyiDDmzA2w/3sw7ZVtCLyeleiq9SB3nrqUE0y5EXK6pZcEU\nTIws2oYgDxBkT4+JURkwx/+8HDALfgIT+LiAURWQxPszZCaoqADYBQ+9/FxLpyp7gwNHw0rUkpQD\nlGF14z0jHKS9K1SsAy5eFf1Ihrk7U+4VTU0uk8xk4PP955i7a9aArqoW3A8KZo22uKSUHL/n+o8Q\nCbWU8AyxlP73/xJDM4u2Gu3SXp0ZSWM17e5iFVH/A5r5qiuCAvG7J/Q7CZnrI3jLLq9WGclNm55e\nORn/8wwuH6aW+nzdzLLaVI/XL9gpW2qTHZ9NTojdfQGQvJC0njkgxjCGk0gxOXk0roU4MfLAEOwt\n5knJdjMMRNI7/acv7q282B6ERlg8Zlu4rhlQGoB6eMPM5XkhOOiPRtCQ/0IuoeP3f984b0fJB+1Z\n4b/5k4dXvtLwJcci2BcZsspHngVgNgXvjiYAJIQ2wco4/3OPi128WqMC4zToSQVquIFBkr8eW148\nNleuh3qqfWYp5ukWSwsEqbcnCjBSLhvTV4X+ZNbKmCE+9V4UEgPcZ2cZpdie5dJQxPmSWcp4GdAF\nAbhUTEJ8z4H9YrnSXsbr1FwwVS19NtHsY+6qdD0tZOjyM0gg+8SJQPhNujRbp7jclY72fo15m6WZ\ncAgWRvT+1Nn5Y4/9af1xdjfe0Jn2n8HQ1HWGPs+fZDXyUDZCGWHrUqg4t//3p0MHXKjYQ0Iu8hEr\npS+oOyg5mBg0vFZzQHgvXsulDcY087HT+JE61N/D/a3fNPFB3WrxjcH6AI/yktoY18hgTyJbgsVq\nJxYWhkipA6NSpi60iLbMZVCxQWkf8kAsb3CzNM6YFCcUkzgan/yKiVe7vFQdgK4GPjKBX2hqKqlM\nSM96u2XEZhpOtao/5pAayi9unSRG1/C9SQyy1JNIdWJV6+jSRxWRTiXYxfIcFYS/LUpKw7Y5BlwR\nFNPS7kiRkfMnKYF3ou/NLYTaM/jzQnTvxJnJAocOv5dEsuUy4WmRUdCjL175Pt7WSoalQCCMPrDM\nmhDW3hLNEkIieu2rOPAWi58PYcc9it0ZGn+w3VMsnW0TduHas+SkwMgSV8l/0bJrxFDsiRe6Zp3j\nMHopZVaPx+oOriVoY3Tn01X0JQnX4/kIrnMeFCIZqNDRJv1pgIZSObDOw2MHqJVJ49ykUO0BZZQh\nVSAwZyh7Pg37y+pzFXT5dFc0odbcCw4SHOxaJ4MIfX2A06lVdWsDd3rCbgsXMIdt8a5oMGiRDsmI\n+ExRDDiYzaFs/I0mWdAtDY28vRVuE9B1Dd50QkFo19dlwtUZoaqkAiLhlCRvOVTlUtFTwEg0VUHJ\nYHmjmO4vjxfYZsl4Avz8bR4aaGcydl/C1/CF4ImAyxheX4sVVTvFTqkU0EF4aW5i0+zJurDpr+jp\n4i8dr8cA+iA72951MC8n+qj0EgNclUksqF4aPTZzB6AVZ2NSImYBvVYr8WmsTGfn3R+fwxUDdaqx\nVi5xI6hrYpzOIWlJ1qbq5vg1W7E7Qq2YkGFdhEZjv3yCPdJIz4wOmru/uPvrSrFf+9NpiZLHWupo\nKcejnXS6jRYpi0hHbVyFY8pO9i4Nd9tQ7b6e1onT+bE3SVX0oJBWb0+NmVuC5aVxLHICnzttO85Q\n7GR4xhfdZrTSuRJKFXj3dMAoiwxWkYbFCB0HJ+g3kAYPjfsm0SD6UdvL0VxFdtDcpGoHUdPwebs1\nyImBI4zO8uTVbLZuAX9eLhSFa0WAd+YQebwfjO9BPa6P2arCpEmTLOhr961C8vIll1F1DLGsbWle\nEr2/m26cy/hZBOyPRq5lffyJ5Ne7zZ5UTpq30BQJgqck6nytq6JU7tB2UHooB2t6AJ0XZVpww4ob\nWFDzRcMu3D1fh9lMdJjUj2KMs5plewnH2H+o+zNG1+6oxpT3y/1cBLjulgpCGLlRWYg2lKt7NiVG\nbKvZ8+djXtsrZcHuAvMcWBodgSKRYfGhmdGkTJRORE2wuoOKEKjo47gh/uPg9WfZ4PtXm8DulRih\nfJkZDEM7hNdW2cL8iBOEtq1K5cVCWNkZUaPT2IBTSV2Ck6KaeuorOwEq7w7OhX5BcZLCk4T36eO1\nDYufRbC44Z+RDL1u0jhvkKfV5qElvdev4hLOsA2ezAaW3MutsLRDwJh485GeaE6S9TjbhCI1v9uH\nHM1QMeYb6E0iB0z8+jxPjw2aTZW+OHOjFvvhBresFDLGI+AVy9R4y8Ab6GnCSz0ZL9+hTwVy9K07\nr65Z4ufdm7a7bPhZReNVTStVORdqFN1pS8oNczXF6NcEgUTsNCSQ1TGy033I94kiSIxMe/o66AjE\noYAkONm5VY9cKq1IeVIDTV/N9TDDpnn7Mfvy/p9FXOLlwRwupohWrk6eZk7Jvi6x/QpwyFHXyUXx\nq1ETkec1tEU0V8D/WDBaaXBO3ZWTgDOkn32S06BuDjmLObrsqUVSF61QWzhrUQA0Fg5iKItgQvJs\nE8gATioh/jr0Cd4uJWfNHtjq6/QDKsJ+DZC7KoiY90jEejU2GE6Mi78lxrHkz3t7fzrrann4G+7i\nvcuP6QkBAdSBdQpYFxPZ5LlGJlESPAQUK0cYNV0l4XNl53yo4p0eC3D453lqPn930BAcYhraIBop\na0KE7luB+eV9l1duU6C1iqQQd/hczBbwJtWhSDaaWL0aDJpdmo5DIpK+W6zHRgjF4kHqrLEhTVfo\nkQtTsdjhFpxpOfpzN6Yl//rhn+v7Z9a9K9F0tFQOfxB10YvZL1owQICiLCtN7/F5bfc/I8CeiVF0\npHGF9PRAzW/p9BsybJDapD9EbWSXRLe6zZFQbsAkxc/sH/ZZJJZ4db+OLGuQEb8TX92I48v4mNH3\n4DfqX2jdtvjSNsbXvwTJEDRiWANCzVV0gaEh7hcwZVj+JWvaAAZ0imTo0ykhQaY6esRWpOtUSBxx\n+iaQkuSOYIiT2/6mTh38qAootAjsk20KQPsCe9NpkVRwslebWjCl3e96zQOWC/1Ti4oYmYYmE3Mo\nu0pE7coHZMlEvjLuYEcGZn8mapufk7QPaZGaO8or5DWesIQqoUlHhOyLpUrTZuMASeB2hFCMDAx4\nO12cxmiFTOPOdKh0tGev6kYifIEOEHlKob6Q1ubi6XyzJLZ8WTen+CxfMwp726LAFAqI7mOu1lcw\nEK29NPQZSHBXleyOgZbWTn0gcPsqLqaJFbzKKFEvFH6FWaKl4nQCS+96x0BwCKl4UG+iPyEkieaP\n812qmoQlNMekMal26Tvv2k976HRBdTUnIlOpwPCmyVA7KBtP0jXNrXzwC5t5P9Cdfy+UomzKK5sm\nsreX7UsoawxJAJK7xaMD9/vXGenTzsXKYz0CExN40jKQlwPMi3M6t+3wKuLo1o9YxY+L73bfNpWP\nAp1uIaE0ONdH9Y2PCwxtf7AlsldXMCQz91kuhPUS3ymF48MaJ1K9xrkc6CtqWPSXvN5d3472ShzJ\nkhGoAadIO5TAeMftxGmiut4X51kxN9hgylx1YypjxIFku+b9Y6qU3dax8r8x3nfRw6RxXpqijpZB\nRndCIaeVjx6c6kPJZ0fbdCoVou71KNauds8CkOm7Z1jKt2iiKez1wV8AK73otZhcy/bfLTeuYgTk\nTfg/qBfcX4Ar23IwDqVYMfw87VM/15jy0Il1ph/8r0X3psEb1cnJLrAbits3khfXkGBMDZ0lrC8D\nDf6k2bjIv2zgYwhEXuWU1N8iab/p0HnUh1T32/RYlPTJ79fFMQsk4udY4jARsxefP0fVAlsbjfLA\n3glP5U9/jmmUgBNuxMh74yNFlE5QcUADieggUUV3Xt4QXEGwNnI/i/zxdh9bnCJgjg2N/fbr+jpN\nLp5Ozi7A80IIGNITLdjaNoWRHSFo3hD3/JgINejrvVVSFL6xQKwJAe5CoC7rP6jObe+OpKFt1PEK\ngvuuN8i4etRGsJi5TYDuSSEIeA2/SB7qgtRzESeiKBsPJBScaEcyGez6Xl64XsCowyb62g6f5wVQ\n8h2+IArK+pjn1nX+wkYPbr/rB7xJnWVbkTTbrKqlV/rrqqFtPFWbgs3VZ2Xar/gqyv6ZwS6fuj9B\nMm/Q7QKnUPfarqOLNVfS+BFIBdcBf+yhGhbTIjfZf+9mKP3PV4g8S6vYQ/dWx4tEQCPhy69v3PP5\ncJV1vA4Z4RIWmIHQkIuWM/msHmLkKI8EjHfEDy7/g68H4aM/Gg0gHjgl0XniD8VLk7yZvKaGY5va\nXQFqKgJWR3lGcDRdTOLdNH3n4DY6cFfdrq7+zSutz7Zbqnj2YcJQ7NfEDaRDtr5fw/cWIxzhJS+y\nj4zVHvxdJEgi14uvgK/ZaMCxmpMBIFwhBpXwObgEk3b8eCqnpKNvM3hLEbBQW9o3MRqrPoPLcfKC\ncYfYLJBHa9YdzOc3X599s/nVuYffq6GmoEqeY2+Kdd19T/26/Pfx4Q6ASdk0lNoDfevy74aYf91w\nvPcFAHgqIogeVg4TU7+ZFVsIO4RcgZsFL2kdqTWhxha8PdCA19plEQepfcL+QEnMQYWvLAgi91lS\nBBk2xixBkpaqwKU51+OnErXxbDwv6oirm6XJ3VLOvc3+N+CSHVJgaZHZFO/bPKIJ4ztwF6PsZqdV\nF/hLeE+fv+qBwgjKYdsQ6FOkmwr82PPYrVSAPi3/FhdneqHABOMxnbLozt0mfQSsJ0JXTQ6vW+lf\nPb9g6nIUyBlfWWcxEl30UbsLxLUSYh846RHB5y17/EaQ3jcRbNoTpUJkL+W37BpGZw9lIFko/KpB\nbXJRH8EQe2kdCoJHARUzBG8LHmFTTVQ4lXciJKMVm/OYmrF0BcHHz/AkDxirOXsXoe0KATEmEKdc\nUt1C1decSA75gZG7sVNGjftIbNQI3x33D3pL59SkxFNL4TnYslfKeJW0XGWs69jAQE1VEpmmnxFn\naJMu7OxcLr0QNgcuyBlAXfAwGY6cRyP0vysp1Ptl4iX6hf7URfsMhUj5OJIQS3DZ0GYkqJ1oCFXF\nwk3ZfKAq75Hi73yOgReE2X/uSBfREStxjMmUGpCxGPDKE97SCMdobpj86ccqUdoWlRuNn9FnX5V3\nGoFkba2WVi0ta1ki3wfgfk6XvYQukRhi/RDcaI5RaHYLym46gkPY95AUH27yAV694Dqy+M5iBPyI\n3sVoUVMYv6BvvVF2fT3rQnDpLfHJ310CK/imSjIJMpgbyo2sduPxxR3OTVUloPdDiF3D6udoNW58\nod0nHoH81aaV+TPo1NhdH+oILDCyaDeT7REaBxJM+4EHgfTBiJAjbtUC6Dt41RAWaZcYSX2/iLqN\nE2zmmi37sobS6dEQGPhwDfPOHABVKRSUMszlnN0xtEfB8vJgKMIGqH7iItV0k/rwH4HSDMxzA+8v\nt8wrAdK/ZgHPZNQZ9ms2JlJhFX5K35EHoGdEMPUpmnCYadipmd2T6wJqSmy5skwuISsKVTbRzSml\noigs6OnLExWei+dFR56s4umPkjir3U27oab/aiul4HFgJx0TfgSSreM+0wgfAVTMij2sc4bUuuJZ\nQVxA1GBEl8CRX4SFtXG4Q3USnt4gJ7LD4NvigCnl060BC4tjq90vaOskpgW0ivk57AP+9MLR8NjA\n0rIq1q/u3rrYZWyAByOiQZsvu3x9dOQ901ygmlc93m4i6sCiQozEPoEXG86y/M/3p5wtyp5BPpvH\ndWxYmv8VbROZPaTCmftkGVED3fKuqpXadjO3/7OztaQ1eipvsNtHvE1sGCfUDx5bCd8wspOC27AL\nBRDvfT9dE9XMukgG4nKT0+Zgs9woyhkHJDDMVQvwYRjabeNCFM5ccJjQpHdVrAps9AyTR5XEsk6f\n6S9IK7bhdXLKen4DxTpQ7CvbmMl3yNtg5+NGUMSHJpy6toRydENGnELRSQ/7AoOo/Xq0fYg8pdUG\naUzhIUOBPN+3+196DvN0Mpsyr7q5t8k5NB0tuBDBCUG+ltjxKP3tYCo3+AxRWZ5GONdPRVVx7R5W\nLA/e86KjvXnh3ZjgXFvQeaOHYIvIg8JooXmRoMb0wwpNnaoYoPM7I9jDRVR2Tb7Lzc/11uN0pobE\nEefpvEiuJGT1fQxbINBPuKUv5TgOAkyqANKEiEHndq2MLi2lL6GYcZjSGbNR8mqAcLG6IGu6736Y\nY4h7ZKHiOz6Xt6411pRYuhhdXxbDCemDA+VVJfEvbnZ2IZrG3qcMe3GemfNHjujNrWl+lxIohXbl\nXhVAl/uxdxq9JvSjEjUFQsxffRrQTyt/ek3sUNN3+UagRZlEz2jQLqIKxkU+wFEKUCyXWNeRXeEj\nGS96eczjfsw+MCKlvZy/8oo0L9bvaSCaZSLhwEN9sB597lcriSjMDAdER9220JRFJWCCt5NGo3Ne\nrqFKbTvX3bV0h7bCHcedqa73GOtBIVcdhPT10rsPPXoRHAwkdilB78iNbzeM9olbP77IO9QwzeLW\np/dTvczz0zwP/gnSwa1v8yJSYFbKf10x0yozNq7dq5xk28jP4grpIUR6rLF+c5GmuG+ktUD46uJP\nzSZVNOK1iYspDBgEwkbZ/sjBQTAjTQoxHEiNWTqosX14NPxERbR/drMoKPFbpB/1rme39D3OwOxY\nGlkfi0iQ8ZyyaG1zQ/SqF4U5SV3NoVDEx8UZnf1lKFivghtTgPBzrGBH2cMxdUuDescgp/cQw40l\n3vccRvGplhkQQYVU3AvaUDVm0O0Fylm/B1HN6SP0/+tSR1qgUL+VkIDW6I0RhZUmPkOt34pN52YV\n8Nfmekmdnn3V/9Dt64CRFR7g0Ol3VkCjW3/BnUenCfcvwdHoxNpB0KslpmWdeTHLCz+3KgCYFKi6\nrL9S6KHL7QjLh3F5WCzNe3N9MQnhQPbxHkTSKByHDbeQuJLqx/gg2WaVRw9x71/rf3Cxk8iNSWMM\nUo/OKWVqd1HcdWyWQb7QaRaXDWb8tXv4ENGeUZfHv3v7bvR+CqH4aR9XScWiHhZarsw6aUVkCGxr\ndn3flJErlqH5b2VPgsQJWOsjlicExGvUbIdVCnPcpWuhhMg2gWgzHlfERpRlxvrbDJc2AXAMw03g\nM1tbE6Sv0z1zK2TWJXNGJbJpCFAm7GDJYLtnRTSTFAH9CUKeqa7RqShCqQzvkdEJtVYwB4iaH8xO\n2+xwv1XRn483QgOYp695QjlMkBNGJOHNCGjwHZLA3V3nisQschXigOkvZKqgJA6njLjMfcPrSUIt\nYtrrga1hAev/sZxyrh5ilOCZqkzd/wjz3gbS5/dtmYhr147VFKGeigW0ZgZTKOcm/VEkjOClqrNW\n4Y8q703VCNvwc2cMsUHrCppRVhjOwO2MAalIxzkgvPpuzPDSs8hkM4Ip70mSudssr73rQFpdNnPR\nUIMXqLIvxMbSwdj80QpuNerDRiBIMsk307BdDW4cjBcIvKdXvGJhEGK16WZGCAw+OG2RtzRMm4gM\nguXOoTkpUWFu3wHoURgn8LFagn+GgSLcQT670dn3ar56ky5p+9kORfBs0CEY0UUjCTaXoC9Uw5iC\ntJshHUPcKlkw1+pteyldDGaLwN+2GTsqruDkY9fhFaBgnl5IGDsbkks06SnWlVn6StcU89G/Po/4\nnj8AFPYLm8ZUnnpl2xfBsBkZazv6ADW6xRkecHi4MVO4nWATpR8WeTopSeJBAJWdTlWY1C3tqPxE\n+cjXmfBKZuuDC3zVru3lw6L16O3795Wd4YW3XlckSlWxhf2G6d/49tM4oyjsaM5hJ9ZEKCJkfMC7\nuuxlu3qAxW1GpyVoSHTr4vS01RT/7gHRtRLaS5fg3GaQfGgjjcForhSJ01br+vvsNQNylOUeiR/M\nbmSwLbP91X54qxjaajv3cprJesUxdjleWHICihh9tUgMsX2CkhtgV8r1R3O8E3xLn5b1ys4hcb3p\nnYW9mPhPyNCVgNxQXKn0pVcPXhQHp0S5nAV4NWUFiWVXSy9xi7CTzicYxJbjeqmM+sqF6HKxcTaJ\nXEWe+3hrLaIFFRzlXmC7atgGuJveEQzG/GRbsc7qE87qPzjJsRM+sqhtsJbd7d/gElwySoVmDQhU\nl9ofXyj0skrfQSL7NtUYVuNn0eNdUEVkfmLAxqo8B1UMvTlz7TuN1wMcEoXkSk0kt+X4OjOtXRDq\nTr1BbeVAwPWA41b7tV1a5RHQbzDgeFs1clTZLw+N5mO+GexVN6a6hImw+1WXITE6uWfGpcOnk7Vd\nCjtk6CrtcCmHK6DfpHXTpI9cg2t0Q24z5X/n7pQ2CLU7wdwBefDCygMzf+20sV/ELxY+n52ROCng\n5eh3x92Rylm7r3bRFLWsUIHDL6KKJos567Cmfb2R8903HE/XqIHiFU/zI6C4q+UsWpJNIv3T/wMa\n5Rk9AL9hCMBR1n8+npYBj2J/Z4xEqFRnRpcVjlOZFFX/gvZIlih6s/zC6Gqaz7t5bQpBCPoLF5RY\nWovKl+kfmxPoHvFYH2HuptjedAw643h4LkndLJHRfNuGDEgROVwmpuYUMDBmyBCisy3fo71sFA1L\ndH3d+z0GtRuLUXVgnpA2eN5yntlmr2OFfIVGNRrsMyEZEeChqPTYDHSDdsf0jCCt0ls+LgdzUzRF\nP8qWE8X/oXJ2uXtEdCrUC4G1bfQ0It6Y6iHdQ6iGBLY/DwdS/bp9281m2AQgqQS4P/YRvuMQOT36\nY80AHPYajf+EC4Qi75hkpX8gkUsngccplVC113SXRltTMcDNJWvWjQ9oI3lV4zQAxTEkbH4NzDpL\ngt15eail3hnxo/o1MozDOM+PaChaTHSDeoJMngj8b23xUwa5wsEFi1BBKimgBRz9WR91lb46e904\n/hwv24BJKgi9E7XhzK4y/3CzmJxbO7zPxgp7JDDl1dZA490IgCp3FSxbaSiA5y1zxPJ1QUB0njwe\nADthZPGKJrlhuPZD7gmxZeSwyPfZbBjcfrd5wXb7SY6q7M51368h9MPGcwF4SK12ks+uvnv66OE0\nEX3YcbwL1mYlzL6h2D66LWfTq5V+PdHB2+aWivqihJja3SDu6E1e1xsi16fQob5FB5/rpQbn6ZsQ\nzexoaNgx6x6rZruCW77Vlg5VAX/gaOQEw7Un8UJKazkVFelRHbc4RCuIBIj7+ZpYZpaXq61DfLoz\ndGguPvPcYARafI67EI2uWpBK7KAhwDivjBP1ZPRFJvXAVpqcb9WWsijewRcWHQd75gxxj0A5ReeS\njrDgsWTVcnZB4gg240Oi1HtSHOaUc95AMxEg1jzRZSM1h8hHKRrdOGTEf4Ax9pGXqKMfOW+wrNM9\nJnaJKiIqFHIHuIssyr24DXUk1ezXNzykdbYGPKTWmdBO8gzNxog+J3lOz/9zhTlLDI9r/eg/QJM3\nMtMTtJ5EG4dF8YOX5SI0DvVjQJC2h9cdYy7RksHtZk6V5JHOVANgLJq1Srwinx+0ye3ZgiqMDtI3\nrUhl7t9v0YkDljymU03adXBGA4vxLVf5RGHIMxqw/iBopB+v2zejIPfRHen3dvZm0WCHIMKaG1bg\nV+ez2lr8MejbDnb4A3m7vB2lnkEKEhjQItXWosmZVCPz3dNN/mFPSfLbxBvCKxHlr/QS2TURS3vA\np3vZeWfF5R/rk3M4NX+bdGVTEZOolHvBROe9FbuWjKhjGwQgKBQn2AAPuxEXnWqCI9DnFzcwTLnn\nvqMKKmHQ2hyYfZO8ycumNP5znlHNcTrHr41amYh2euxBA08jlHKeyad6TRiSmqEtYP4QYD4hkDGT\ntdRwuoBV5bfyWixvZW4soowepV0SCZyHXmiar7cVw32UHOKnNww5+g5Uz5AbP7nfygMVM2zAswjD\nG/KRDInC5gx+8C/C+H4w0vFVH3q//bzv2VkBBMN8NsCxo+/9Y1uX3RGdLNnkR7Of2u7+z1GCJXox\nszv6OWNNm7bMt/H1RrNv5FYLsOCfggOHMJeD2IEVW6L56nt5CrvRPNLpHo24jyGKmpJWGwhQPg/5\nCYHsu22E1RYkxxytnRguyIL9LrerkeaaKutZ2nuDBaO7c/eR5Ow6iUxGnV2vO+dsO2y+evD/eJOM\nxKUBuEXMJmdkBHye6brGSueQbwAj8kirAXgZ4vIIyENB1cF5AimTPnn0Vm0bwgmjspBAtaNHzb7a\n/Gd4eDzl3HcY+w+w2c02vjaXnzf1fWif2pFC8SNKsaj2Zg4Jr0SAqu7dt+1LywtEmj0L8AvRsuoR\nX+7puu+h95LZlgmhq3jg8ggy9qg2B2mPHVxkSnjfd0oFFV3xbTnMeUojpup/0Y5lDHN/1tflPUnF\nVheRy8d3SixjeoLLb7zjNRPe2C2rIE1ZZ2yU51I9bRtnM+x3ci0jgEscHLzLDcJXsSd5TKblgomr\nEWud1gK5biNvA9N1+IvV94ef066F/Vo1iK8rxDTd6E73c6xMZi7r8d1j1JyoBIHI3Li8xeFNWuQm\nrBiFOL+eBgyISGmc5Wz/YcAy6m3R77E1mfrxEXL9ykQw4mSQ40k9a3Bmzy8InIBB3Rjdr9l+SKOD\nI7eBvRyPNaF/46hwb1LJryesmSTAVxgBKsK9tIbLxKiJl+ubbCfyLfrntRuRSFhl/Kd2XQrLXu/f\nxkv3DEgys7cO8o+mMtWSnHkIHvOrqGEY04pPBynbErb8QmiUsbbuH/BvQzWzHg56MVS5WfnrGUxu\nEe6w8PhdUull9xJwxMKbbadq4ms8E7CK0pvjJcT+bwWvAaqxg0E8MxEzHC5kUKOZn5XltT/5FumF\nMsu4d2jCi4GvT3IOlmh6Z5izdJXzjhhuAA1tu8Bfx2x13rByFCOHhNiv0DLIwdXtil5Bu1qNs10F\nnlMnz7D7YToxFegv3ZW59lGMnfJzweQ33B+cL0Akdkt6iKN8nqMJtO/5vqh2V6FvFrXAEFYyDvbG\nzDntLI7yo3acXVqpdgLy0uG3bB5V6wc0vhEJ5pzXH1b//XnQN2iQI34WaECL879xfSSjYd8yFUze\n6JJvpx6gPwypx7qJFmIlzCjugxTw1akrRvNM8zW/V98JmHdnFLHLBU1l+2CwHMl5BmYeMFNTo6SJ\nqd5NM3WDiKgRw9RHAo+ElfTctpsBrQpksSMgD+vGGrZ8QU05e/2gZ/gOnRQ5NL6m0OmGIYHPLaV+\nU5rD8WZJQ54E0TU/gwdW3mZ9UcBqNpZpRX84mE7pSgVLbR5gykyTV/zHSbKPnXdHZKAHgFXcuhrI\ndzAcZ9gMHFOCPXLusy2xM5YTTuf/eC8/TiTr8foM2Gjxa+p7SjHyggphs2Vp3htnGAX1QMBd/+kZ\n2dV9O4/l1k2Vmnk+9/eraWOdK4XGAasuMjSAwvY1sJ8ubEdHVmZYlxZjMLl4S9RtTv9HTqkyXysT\njpO/F+BGtdHmsUUYE0ZzQj51IFPWIozcbkbPPuq7oeCmplZCQq6L4jkJdBehre/kPKRTKz9VgtSV\nSIl5rkjQvdTq5mlZMvru8KjID52jNUEcb/hpK0RdzSr5YRl0aaHeCF1zU0GpA7gKZfneVhdESmMo\n+CiGrqHyOHMxwlPb0U+mowoPqpbr6i3G2Qboq1Jjw61ozjgmItpmR9l4S7qUosnHuk6vz5olxMTC\n8HbaMCeF+kJoKHLizNleUdIMKCs4McW0E9aWLuT1QOurTQxBpSkpHDv3WyjEAY6wDndnD4coAlBD\nQI0qg6BNPd9ohuGzApx5dr7AvpgASrSGbu3suiWn8kglb47G9p9e8K17pHrN+Nkj8jwig/wJJE9A\nJD1gPQw3hcNlIGIBDPrvYQDHag1vIzyJQH4D6gpEVmt/rL2u6uRxx5GtRr9nuL2a2w2cYnwrRYCh\nAadR77uR0wXCCf7BLQgEU9Ni5P/4cY65kve1+P9DRQJaii9ejVuS2+g7LbocRPj3Y2zc6rTlJJN4\n/OiE7rIdwwt7BMLDQHUVVsXAXJtRDMF89KqeQHnFhS9xV59H+SJo0eQpGipPtLB7BbPJ/y/TGnnb\nFo+LiLEk/A3AdIIMAkILK5WoYPrHkjkeJ73GU939cx2dbU55ZCx8/kylru9oqjlrglVflGcL1KCL\nzwviD64s0DKHLJHdJAxBBN473Nla2L8WcbDL1UG+VzvEPG80u6d++ax8od727WSL8ISnruwptTll\n81H29YEZR0hNwnMsnhGSZERu+K9Y9L5EZppyOApQHxQNkg4RncnA7Cpwp/TvCvFm8GvwmGhz251L\nFyO0+4Plurc5ZLnGIrLH69si8Y6NnOLj+xzKtnKXA8DmvYkcUmZAN7hx4IRA8D7g1MgHJgZLzWhu\nxL1uXzJ5ojawYVnwnkfWWGt6LEoyhqZzPhLwhKG89gPpsnhAY2jpJZVkaHNSES722X5Ty5cLFRJO\n36ENXiLbsTaUcIPcrv/AYGE4NMaGJF2MbIyAP58BJOYnK3QqxUdostdgSG2goVGLVQgGE3ofWdHE\nZmh0dBS0t1xglOJa+FEDf70QBqs1OEvhhMhgOH/qw4i5x9M/JW3psQNv7e2reIczCaaoXj/au+Rr\nyQN/x+zYpnr/hfSfjrsW1LJ+LdqTAaftNQ/NQXJl360ieYDZ8UHy7vQT76oRgT4qhzbh3TRchQ1y\nuvn+EFK4qI02kJksKXrtNW2o5WKM3cjy2y4ApF8I1bKA+NUpexL6U+QYZwXedoHNJhVMuB9PiNVW\n1VMt+0vs+uYGW+bTNXyWaMfw6WPOhiC7YC2oer3mYoam/edo6iCkyI57HHGBOJYaamRKrNYYRblq\nyD75VDrrSeXSA+oPEQDsIeWI0vdVcKZVr+BYOHjAB5RO1InFNyLn9FKspHdzdKQC6bRobjjpQX/9\nGhvMmW8t5BYVcphvM6b8ofo5Ybbj/ynYtwUgN1+iU+NOV0+50+M1ufbEMrnld4WNekY747wpGbUI\nxDgKSHYhmK/NVCVh0Dsfo5nE80jNPt9Te24L4yHOnuZSzItG8GnvI4Y60Fx+VL685r9bcXChzU7w\nEomShk6ruVhe/Se51lFLstM+/6/lGbNyNvYQtdReqcqezYcHClZDaL3seVMvWbwpVyXtZR2TNlKs\nNioNkEcIDUKlT259fsCOL4iU0qb47/kSYrNHAXV1oecg9IN0iZK63NBykvNQ5Bg45QAuuu3lzE8Y\nLzomJ0MoLHraud9CFL5t4UUuSIdKS/Xp7ohEvy6yiVm1Y1j1DtWdEpKlozwtaMWUecMvDPNnt10x\nipn9yd87v4ncJeeDn6k3Lc/Mzlalo3NP1ntFAiGORZonUZMIqkS8B+ZuNskYKEjQVaWLsTG0NWJX\ndBXchjcufPBpuB4lCDv58l6R9c+qZallbm2TgCP/rYqxMHcH9gyZsVvijbPjBjLoWd9kUiZG+cwN\nXvelEU27/ybJpVp0CqKugXqlfhP/0emiF1/TfJ1BKv9SrQ7/Szte4R/vGdnorSkadgCyM+khRvo7\nvePOHbwI6OGyHnr8rqCr1JBy5rqEilY3JlzNN8mMWil+TzoCgc7JAKtVk/wlIYyM4t4lv+nUX6lR\nZjUqPoZ437knlatvtbgaqr3ZfJSxlz0agfTUeALLvOoGByxZLxORiU51Rl2BEuTUTggnZgtMcmDe\nsUheGDELLaL+89R4n74BDLpxEezXH+5IRxsBT4u7HdmYJ1TbF7SUe4pdg8IoNDW2UjyjjI7JumQU\ni+V93AKsQNdIv3BIcEfXgWsaud9YgC9howX/lEGGwEHnpq38VR2nrpCCrT0qI7xVv0LW2U1nl/kR\nYTeWvx6v8KO66kzjTUFBkqMQr5srlweBEzUQ9jFm97+woZ58/NlW7Gh5iJzwTlb4GZXIm3JuC10x\nW7d9ue5yszyyQRm7iayvlcdRUsi+5HfEjYtmWKBtJ0ybjo0IZMALX/leod/P438BAj9HoGdT6jH2\nSeu4I/sY7+JNPDoYariBWLDiA/T7dz8Hloe9dbyW6UNqQxhQwm0HSZkiOwmVClFcmJK2P9pgGc4R\ni9/mGwnAsYi8N+G1+m29nCimRQWZMhdvZ+pufwMQwFv+FjpJCARiUwalWsgGvmv44a5m/m/5z56g\nSO58xsDSUBnbpNIdRXPmv6keAS0ki100HRwrYoZcA3EITE1zpXsc0uMMzE+QH29HeIud3z9tyYds\nz+F8RSmITbAiXuK9bCRenqKhvwaRoWagtSeYD3TPF/SYmmmVeleZPwLvKPSFuRiIqSy85KeR3Fpk\nmGPRWVtTHdAY7HQdIYLgDzQEbXJnumfvFVX7z2v0WQqEODZqSYV3K82R+d2XtpqzJuEueTz44B/H\nEtps80hbqSsmgIlBow1J3FucGRJeo5dGbP/ukqKzHC/mMDHY2ytfW8zXmUaU1Piy9stBx5IXoOyd\n0bKbZJWZNewz+j7dVKXSJNLVLf8E1RufBVsQF+RJ63qK7KioVAWC4TDXj6TujXCItH70M33TDDDE\nBMVguJv4lcAQ/1thR3hhl8+visWQWFzIChPC4lNFGVsd0aes72Z7GmcYuxnx1abwDIfDbxM0ZNxj\n7SXAWNlUmPqCdD9LzaGOnJC1HzOpLjMi/1OcQnoEIWZtrdhGWgT5VIUHznxBo/3mGFfvwp3qT0Kk\nMksUEtnj1kT/nCgrK3KJCk//P2FRN988InSoACPjUSKnHzJo4s4rIKsXI2ztyTffCgh39hPqM+HQ\nGHzHsTRxHzAybx3EZvQqz8aq5Js7JwEU8Q/yFh7hP43lYu1YwfdZQIc2YKD1DnICjvyISKuNNZLf\n3OKMDkkF5mrYxOCQlGMt0fZMSnus+vF6KArkjq89gw76Xe2WD/8DXN4/lYZh21LwzVSyGugsNsIH\n/WL9HsrBiJk50tNvQINeBBHS5xAQLRv7ZEESf+XJhzed/OnoXEwHrtnJDbG4rWXv32hUdHEyWDC7\nQ7X0iOBCOgwLB+ZmVjfFdaSn4dEsdiPiiyf+w7LHoOsD4jKD4exYhgOBXdzj9Gb6z9tDI7bSOoZ5\nj/OYw5yN5nOSs+QLYM7/sawTQFFqdgRJxl3A39EvmIR5JkfQWf7knE8U0fgRvqvAWZHTqBSaNP3i\nZ1nZSjpZIQuWvNTsOOwj+zETyGSGbGtpe0ObNlE3IkFqEC/iAJ8BVfEoTlaygq6tYLolNpX/9rB6\nqJphoKq5GddFAyBcyiM2IEajQZvw7wauM4TTyRTyAkXdtq/52Kc5C2cLGAbeh97j0ox5qyEJOGQl\nheZoKFTlVKyCZMPSsznWGbgkh7aDmnZfdHmlG5iC29iLaeQf+Q3gbJtsFeqYnyAHKfVZLpwRTL7Y\n8D6kT369qJlwvXz4P+c3WqvUIWrk5yspStL7odX1gRMo9FE4zC21JVO//sFYotut1rfPA0YBhSpm\nvZuFfLdRzmcw9Jdao7EyY8mDOB+DFZrAIrJjhAVfzGF22C27NZqhnphJBCRuvvTgYaGKT/fbopV5\n7pyMQC+Gxfo9zAfe+i2XHNcy7JqVcHGZhDMcmQQVyMnjWOGzC4GjFgIHbIg8iZ1Izs7AtoQDN2KM\nHHKV+NjQiPFzYhI/57rYRybd0tyQa8Z9q1Yr3GYT0/8V8fvQCsVK/bN/Qhsk9Z2Se0WMMdx4fTaz\nzSJ5pf57qprDYSDATQu6XEqtCAlOGmzy7lZuwrZqb1PxkZ/ueKRO4ddVM9cDHNowB7etB9bJKMiT\nB9LxZg4Gd85WdkArdxrnd9eS2SBOfOYLvRikyKrtwIFNMmbJZhS+9ylwq2hpBR8s58ykSaRkeuBN\nkZmsk3Q9XJ183BEjlk6hVPbj6v/OQamMJGahfpumtK7oQ9NSvEF09EhK2GwOQJTg5Qq4PQqpK33Z\nD21N3mEL8zLNxFpr6zy5JmrfAWngoDX/zad3fx0bK19RtIRIqUWftjmj/cReGwVtcKSSHKvi1yWM\nDdg22/UogI+L1dU73IKs38EvSp5L02fod3Uwywdnx121+uVLHvqFlTrv87W8VLRtOFQ+5dlE28oK\nYE1Pfx4BHvlLWMszTyt7MSL33ozcuedqmkH8pjgCNq7igg6zsQNZXgEISARsHyTHBTF5dY2dEkXj\n/BPZOKu0KZuCQ4CjBLV0O38TlKIPFyQkt/jFJjN5GqhfzXUIJbHMQyHh2VTGbP/SO/7uP2hV0iaz\nHX3AZXjj/szqpwEYa/Py0L43nM8p2HkMBQ/fqbaKKzbVNKEg3mqlBRhbmw4NfRGyAoTuKI5udyyo\nhQTN9yfFjGc/gSJUOTn1waRMtshH6GIKp5UMxJcK6C+AupbddePf5Dah0u5JS5TD06HzYoMjFz1H\nhlSPWrOR7fOBNUK+f14xfVTYbwYBU5z/RoXu3WOOwDqK7ZHXufpRaLWuW84E6b7C+9W1LtiMwaPO\nPaFBXfNtmFRznjmf7fEBstPbf32g/UlRyokyWs/tS/OHCyzok5onma2hjh2JuoW2wu5hpBLXTYP+\n2jYKeYgV2uET5HwqZ5VtQ0lEhhIovpLXLA1GRljkBAvyKiCFr/KQmTUD+pDvzLWg5El2LFrxQLSM\npZ/VDB6ZMQjibfeD1tOSiQ3htbPhacdjSGBkYIXf+YJsYJxdl/vjTDpfjq98Ar+/jdCFdeUroTiE\nuKx1W/IwTIf+mORpXxMs1UuXMltBCLE38WUccG8kRT6vtW7PFL6uUMrYR/bHhd7zcmBu5T3CRghX\nwuHSB2i5M871nyDO5GbpDpRfBdatGPmVRGE9TCUVHGHvDIvbT2ywkr7tUGlgLOxqIuC03290GLD5\n5NdT8O+nHUvJF0ONFJICT+mklm0ZxWajRCfoktwimCUd0S4LEayWqFoGKSS+rR13oxUlcJu0octH\nkP9TUchvnh2rvcHjcr/+Cr7uQa4fB2In44nl00HgMDTjCeb+b0IDdocLsk/xmjT/6jUymnNXNXPU\ntZyL8rGrJcKWjVVKbZCb7P0KCDa053E0qUm7c7VaSFJOBedLr4wAFcigVB1Xn7XlueZ0lPk2bER4\nn1Ivyv4j3q88HaQlJ5Ybw0wpgp3xqlnucVMQjtlcC8596Ck0LljZtme5AMw+KuE7coKbmF8KnUpR\ncu7RefAP+B8MiSWLioO/xLSVFWhmO63ZVfiQeqjeoosrfO77sisURcV2inuRonzQ6rjUxfllIjT5\nUVB8wnoQtPXWpmPSnZwsiMjCzcYPYzox5xFXjY3/eWlrwKVAKb4fpgbfFX6uAkqLMaRsUeQQRxOj\ntUXPy+3w08I/LpGiuSoXGKsqOdqdnSFw+BNmrpUIpYOJLweEy2W3z3+65FtK0rTRAOWzoJltDJp4\nEv6fIjlI9uSQowRqKXgD3XOsbIBTEu/NSnM6UlryG7uZ4aA8hivO+ODKrcjrnnGkDARCgGxQrxMt\nvHXeQJTBF6Pbqm3qEOeypaydGJ6gsban0bRJrG8H/Trew7uvBdp2pJ6Goyv9j9iW2olRCHxj8xAQ\n77iO8uuOabRuN9WcRr1/Y6TC+8nAowISAoQXa+n9ghO9gUBZU4tNb46I0Q3AWXNJ7EeQggw6aJC/\nXHgd8eH90tg8lNu39TdLgoXuLBkBGVpD2FPaHuoYNTBAu3xFXM7uYvcelwPGV/YGvNipXLwP2j0Y\nDh82/G8cb/7YXSV9/P9Or0rfcYB2wbALf0jHb3xaBWqDFjw5emnxNzNLrfiN3zdPfU9wVZVkANsJ\nXbrU4WAR1CI3nC1tswwYUJJS1U+CLWn0aFJb2dr83DqOCC0IxSZObfiJtj0spzXOi3KkIROvv3T7\npXtSwyd5OkBsMffefKejh+3li/vYrZZKS2NYXdmWTq9RetxC4P+SunxnxH7kPOcBTIlVOnnImf8t\nov9OCECpj0pKunVjJH/8XeEvs50/2urXRRmxcvsMDRyaeCfucmrxsv3px9pJlfmZgMC4n+uDM85a\nCl4gAn0fZrAmCP8L4mq6D6tjHTj1+lIxcUMk9TpkZvavmx6jziEJnX9d6JWQJigedGOTp+UNLF3W\nK5bSvjXthXSYT/+CC7RFtSnL8aY4RIzPXDhrYrSXT1vyYNULFlyi1oVhSj++Mybxb3za1sUrPpsp\nEI2RAR7ZChzeXm/vFRn2e1H6H/teHebxA/F1ybmZ/RsOIHWW2QtqlSZHfe1toNAbM5eYW1x5ToDI\n+09tRUYbAHKt0SsWs4fDiZL9h8MJiNNKwowFIf5oovxguOQLjf+b4qIVWps76DJCdAyb6kq+9Lnj\n4jXsxeoarVPtJi/3d9XmWZ9ceN+h86Z295O1CZ5Xe2toKcUFpS7kNz1Mabins+rwYHt+5mezQuwv\nHK0orlOYctkEge8gUPN+wM2esm2aXPDA0MeubXnrGPCiwH7VDFChRXXeqx7wjejE40c9Q+fuZgbh\n+cMsnNdRitJ1jGSsvVolUxOn6g/9OYwXWwoFJZGYXqK+k+BUIv4FJ47XHYTMlymH+oJGnbYNXBzY\nOceAXdzRl8oeZnhhsLiei07UpwHVrD4N8W5aqbtji+eCQo4JhjDsTykVLz2lvRTyxzjt5prRoN2U\nhRlCtK1Js8fosNk/QXwbRg/YPDPTHzs2LhvgNvpciSuEA20WS3b9Zk/EKqe3Yyy/DGpEfqDa3aAX\neWBOF4OS737pJN5xCYgSsJGwAukHaZ+05b2WUsl6NlXoKHKSSh5wJVoFPdoE92kBrFvoJHNjSl4r\nFasHmMG791tAX7Jil4DmnZI0KShj52DGR0oaDeppwwUjVJknZKuZyromc1o5HJ+umf4zH/gKFtvB\nPQfqFkl5K+bcFB5pHJB1roX1UuImb/vDR6zjScBhpHaoPpzwltwl8dE114zZXA3jyU8K4/5zzD3u\nwhzdznzb7Th8yR/+MkknBHqtzzRZzB8lgYiH4QuVG8+s0yZmxKaZpiS3vu5x0hdb44duKQIEbW3O\nZ5wI5gw+sA5O5Kq5KVg/79Pv65RAgdomWDSHU34fTRmznXGZ+SRb2m7zKnBAl6xY2MjLs1KWZu0/\nyMYBLjrSZLzurX3kKh5F90ZoMy2z+2TLVxrPu2jM5KvaDIKrYCMAYqbjnooyV8iBzwXyYzQxKjr1\nxHwXwWRJXAYddrg75Yvm3byU+glfZn3YcujqWGsSd4WMae9aPNf9Id5RxTC29pinLAVhhfy7pWI8\ndKO41wQ6wk4S55hJQ5gAQjP+V9BhITkHSRYGcsllRfU3B+TAqhCRxEj2zjT5hEwpR77dH5vvuHV3\n3udxVH2jJ2Y/7wC3ewu5QTLlS0Pem1Wa8Idr+PoMZyAlKd/7fHriQa8/DwP6HtgaoOvsvq7ArpUH\nFgU9uAs8deZVSEXnwD1wyLeRHg323ghYpgf+0bu9fbiF5uWuQXOEU/0Hz+3fSEXzBUvw7Ak8qGNt\n0Xn9gi1sn285hOORunafrX23FYkXVhVX1FknPAm1EIPX3+oPvOpQjnPGjE36krJvycBA18aA4RuU\nXAfjyXZoDVvWlpfr1Ht3m8Idq/tidh1C4NzcOVg8FBS+GRk2Jj4xqYlTjdbTVmruOBix+MPKxMoU\nA72u4Ef+6XHX47/hPyCQjzLt3et4ywo0fTBkcSvSZIJBqv9QVAnCj37yTK1C1l1L8XTgA/BN6p+R\n4Wci/E4/Y1Ue9YLqnPS5Gp/Glq6YJWtOCCPkq3etDdZsSGIpeCLuwgfp+NHSr6VOxozxYpDwo03z\n79gKPcupo3atCPNfKaXRQIDeSVz669+Kh3wpxXmsRIs2aRUrhKSsmKH4Fb/+CxXuxFVWmskPG9xO\nJG05r+HOfp7+kJPB/nQuT1jGetDWk69soK3Hdc1w7OuyKRpPQte2OfnNyYftcfVvivYOWLhe6Jle\nvApklAPNjBI+eqa9RlSIL7cfWxr9bZ4HbjnTXVmanm6xkdfw4GETPCdB7y1hvF2UpnfjONFz8Gyi\nkLT2ieNn0dr+Dwt+2qXKi2jyMLL0MwjkV+L6pbyMpftlV1CKNeE+xrLCZxT6/7TPMVpx0+WanQDJ\nVBc/vcTpCQo8eED9NFte+vl/23Wzq7nQilbdo95Vy6kIoCi/0KgSiERivW+ARhLvuY/9E/Sb/3E4\nyILKksT5VkX0QgIoNHgrr/9RMJoOSmigAYWCS5X9Y/AtiybHASVcmKP19q4nHHZcsZ6tnm/bCaTL\n/Jsdeg35gPM7P6Q8DnQcYnAlss7L8P3lVeUlGfghWPpx3O/ODT6y1fRf7x4SF/u3Gh5iFPkwbShf\nNzDL1xGqcBp6nnwFGoOQPN+Q7EnXlXPKePZY6fwg/nEG1M1NnczYjCZBV2ETkmuR81VaMRWpKdxj\nnUl+X0vkJNP9emarCQFSo4Y8wi/2mGJrPUB135ZBBBMmpnmLbI3ySsrvqUU2iLCH1oEUw3BvH4+1\nE7y8WHYvecBY7FO2rxOf43UcUt14KTSfDYMq8Pg0htdcGHufgkH39eWYBcwxlqeWTbvAigjFYdRC\nE6PPydLSYSmiYaUGulaaQllPu6zjPlKS51mQ43HwpEwQh3IgcpHcOm3UH6OCxvqXvYYgE/pUqnxB\nMV91s/blCreQxU9UiwL4mlAW213BhiRJOqsgMHappuaYI8/80cnxhezTTGROya2PU6Oa7f3IXtw9\n9lGfxLRq26fe0vn+txy3r2B42Elunm10KHbKZK/fpF9g2X0+tpb1dGlox7dzMltmOb/bhnN9lCfA\ncYhbh1zPMytTSeXSggqodVzpfQDACJ7H99DrU4JPwpGaC6xe7cu9IGDFLxRO866ja5jEaZCyc5J4\nZgwncGvLcmjNZlqTj/zqM56NntOwp9Uvr81xKJV7qgN+pU2b9yPXC2v3xmIIM023NPAnFhcxZdfb\nb52SsqWZxgaHOtItbREFEB2cZmbLGqvidGj9aVoWnVDjLMK7pcolFGLnegC9tZUDrt/KS0K/9fTD\nGqc/Qps/TX3uLi4F/r3fjT4hIBmLzebvrZiI6Z3onPAVEVS42bRagcUssYCmBUHCr5QKeXmj1mHe\nKliV1eFhtEmtVWiZ/TusTALy9TKlcaW/VkeLdJhJxIxh8idd125uokFnO1vRvhbE4g9ZKpt8tnID\n4EMIpBXDPgogmdyAGqi8jgH6uJjMfwSm7Rw/+Iz90f085rG/4QcVQQLpCMxQjOV4/zNAmaWauFN3\nfEzUwsmIBvRFAu/OHoyuuQVmX+ZrmBd3Frqq+Q3bQlwrC5lRc+uYK8xtDV/T4sDYfbTRMIRXE/4u\n7rAvh2SUlv4phazPL3WMva6+GGIyrqnSszopcS/v5mabLLzS1H42Heq9R21ePuO1ADg5odbTpX+c\nmTYTEIrb5awUs5KDLxm4Ln1EGqUvVCoLpef2ZihfWq0kPtF3WxEqAZAYER2cQW9JiMJFCD9vXDGf\noJ/BSQV2R68U/xhTMgORRh+aYfa8pLY2kpx4DQZGWANn58l3pcKZpnEo0Q8+9ND9xOrjjGdU8jwc\nIdnTI/jAmNT6Yjxv+IbF2T3tTbmI19ZSLJGfiY3+kBjnW6DWjusxQX8Ex9lfvPR9wy0pXsMzWF3s\nqiF2Ja4zJErN2woJoNiVISOJtvCOcNQL9rUT/e0a/3ZfyoGYUhAsYxgUl/gAs9lgVorXkZO9u2Lj\nH4DGSeamUBuBplR7hOZh7/DmquUbjGMgkaEcq0uQ4hw11MiLQjqhqmcyZtmHvB37yyFe8EGT+93B\nXk8QXIJPehyHYqxnHYJ8xcXRTmS7pgWZsY525UwlEkbw/C/gd3caSNz9fUWSt7zO95FWoT/Rs9DF\nmT4y8L2kOlKC0KFb+t8VbWA5VAO00Ama/U5W4k1UaPEnCTOup21iNEj9E3EP7JQAmbqTJk7Lg9lB\nNwbv3DSZzS+cqdaUIqttfNLHoOj05nTxg1zVlCkRBBgorAB/VbX5kIPwFGNGoH+iAGHBvTqcYT4F\nHO1W8jlWaV8mTcSt7qOjatUlJVtjpwWlDw2DbhZxqpWrFgovUVbpCu1d7yzf1hc2uFn5xS9A/1P2\nrWO1bD2RdRVYl+jLOuovoTCzwWWT69siknsWmU7GmHv4Eun96yTBfum2JBc0W6RT0Gln0YcZ+zmj\naN+piqTj07Zz6kXAXVFLgz7dKngs6uK2YLewsJWT64to/IzICAWZhYPoCCd5KC5iAKUO8j6YOXAD\n9JebGuJ5Q0pwUUKt5hOzhGebeunzbocUiKoMHFmlqgvknLWEG8FEC0g+4DxBJ13Uv71mLS0brpfG\n1dg2LE9wumjpqSC8xSAl5AQaE22xtBQBtx7dCXag8v7VC57tv3cG7fzE/zlEVdkK6hUyb7t7XJhu\nx+bxaPg6SR1TDsn4Qe8XtJn7rMi4797XS+0aIHpCuC2O9iO/FokOje1A+t5FyGqpDy5TmwkX19qt\nhGPlwrUUo42UZ/TP+cTbsqwtWIT3bjGzj7g+MqDWWzDonb7neibCTpZTO5Hj0sJ9Y1/OVfJRX1wm\n+gjiXlKcMgGHHzzxfXqySrYnf3QUo0ZRrs3YjSO7SkiMm/n8SDHvIpN2/HaC+h1xhkYbTeM8fSmr\nfcC/H29sqNImllOILuKCQVsl5sXBE2XyLz2gw5xY51HOwO8WYT8QrX9WMQvBKMfBnwxNiRK27xRr\npr8EY6o9l1XURJidENTLIy2wabMPMiEe5Bt0oWUC4TFnQOVkEI9OaBFKPUh4j4Kr7j4qpxeS0uO4\nrfFuLqGzWLHa89a5nlZR7eCjNh+xmhl+bdp4FcgfqBp03yhSzs/JUWxudxic1Ss+knIbaMgc9Uz/\nmnAIh/8zZePtOsyWnp97DGwaFHPlAu+njso2P2ZsHHXvLy0HjbwwkUtMxYi8zCBsFLB74B6D7FBn\nJrTFxMrb1O6Ag1/QqdwWgNZcMFUETMX3UFGoTSziM/RGVHCKp1pFJ4JV+uGHq2BCtxKpPuPVBm1i\naXDpuqB/4d18f7+uz5LaBEcwtEbIH9gUmlWD+Hp9StLe5bF4yyru3D2FZ5cNO8U06qkNJo44fYT/\nFeigM13R1i7YLOs2BP9FLBrOkRRYKCeWQWYbm3q/Fz0Nt17oN53GoVdN/i/PT5JOee6VPie1boAH\nYD4cse4zf8igKWof/AA7+MZ1nn3F9gShaml5jDtnonWVSz1nDwNvqGzi4BVPNWn+fMRQzwzB1bWX\nGzpbn1ICVXP/6ogU0gzZg2cec1HPcug9XU+es/ej0t9v8IHmfJPiD7Ji6Go7ftNU+qRhrPfCojQj\nJGR/CgTHb73c1zzpSYEtkgbyYU3S5mjjbttz2Jg9Ux6n5Z08AOpzbbKsDr1HIrmtdZweh+8FaZqK\nJg47h1KEwGH/6CpxGJK8wjTbhOeXni7xY9izeCljOfy6v0hh69o7T2CwTuoAK/lqZZZ5hLCEVjF4\nyCgqpWR579ftWxrvYTibys1fxjTTLjWBhQNVppWCz+tJpeVQW0gOcDUOPkS+RbloG/nDuaT2pDP6\n8uNiyJnBG6mfEIy2XjDcNrxja4jtx6JhVMFrvnHvtYznhLnBQZBtwmI9KIZqSS3UlDKGF86yh8gJ\n2dOcLwddeTvG/vAwICqD9Tm+QWJudMqAwHsXEYHC8JNFJhsif1fZZsR2lgqryruf/kZ8Dq/qrTok\n3/fCEDKngxA3i9tu4iUMFo7EV4v9x8HNWyKhQHmAAwMExVZhohx+0B3D8P7ruajSc6rLE/2UPQII\n8XBU0wKVw7KHHXQd9osAvXCkNTQBRme9KFWJuKn1mtprVxkqWpi/rRi5TqCxy+1bbAjJoYafZkHg\nzPee9rfJKSFu1DFKZZR2XD0Dh0j6XJYFW6tSiXrmLzfp3XjcuWBeGHCGxGWrOyeTtYG1q9Pbdl3i\nGAVn/EfHZkuqcBaAnziAHmlm4c9Nj40/B531Uib1BI0+5t74esUChW5Kr4uq5z9toZ7viIj1xjPL\n/m8jNXIJ8NWF2+TpqRTqEy5knLTwqIj+pBlMTXgAbOjabZBm8JGNgQZJPNDpVHhvzzQ5pSgxFNGf\nda++9zhUWWVI2L7jM3ixp+NvSfrhqcTzHAKVlbWB+1GV1b1rUoHLuDTblsWIduLNoyMNGJbbJyAS\nq0eW8MBFq3nSIdsFF2YewHH7rivenPFmtb6+2WeGmlMFFhaksR2GXw2sY1YR9nMcJvKAUG+RAc29\n0YiOu0nSWZbS5SY19VZTPMEzlKShwgDKH7k0prbKUo0ATFfjqXvayKeO3TUxeecZedXOpleuY5PE\nJlolFdoB+KFlsCAZVrqicDnyKedag1ROXrKTcVPfPfKDFDWy+ChaK+P7funoTs+8jfWcYWCD+7Vl\n99jdyZYaeUy4IDXPP7ZpGn2QH2WANV8iHjA3xZcPtfQTqGGwD/aMRjToWmJOMB9n5tf5pfRN1RFJ\nlPaC0RH2vBBqxmv1Y5fJJYRwPg3HrZBB63A7rbFXyW9nlJ5qwfQVMpgOOgv/Wb49Z2LfiSv/lyOP\nkSJa2FwcGFk8mxtwVlw27YMtIzOCzwQyiaQNdCZyRCKdkM7APaxMufoPJY07TLkyohZ4RX4IqaCh\nltvk2RfTC3fPZ4kuueNCgYDTK4vu7i6YxRz++hE+A3ni2NuEHyuJGaMOCbbEsRG9OuvjGV+U4Fal\nGxkNA+lkF0vvq20efdf52s88cvHnh+HsvMXmLmns469D9LC7WfIunhnLEcix2hcgC0lBJqwNE6ld\nxcXkbWJUbD+lip44P3QhCdfaY5PiaC+JbgDnxYj3pSEUnCBNRGwGbuI8qyuhHhfyMtI9BdwGGvMX\nfa2861LwcvfdxdOBUi4qyO1qcHdFJ9kvCoS1Zxh0Xogq0P80qRD6T3zbBv2OdfxZfYNa4RswUpgD\nK9fJGEwj8sY2tPulPT7cGWE68pCZMrRfOy1qFf8mTS2Xee4R6HEUBAdB39Sf+ySiaYt5bGWjFGRS\nsWvPM2edL6feJZOam5vnPwUt2Bz8G6+2WFptpobhgC2XG2wpy5qSphoW3I/+9zJW8waO+8LB8/hU\nK/ZhlZhCHWitIKHaa4uDYa+i/XzjYxUt6z5xojrXzZszpmweOF0oo+1loW7meCydN5JE9W3GCtog\nYGQqdpikmoxp2Joxn6f46wR2KqT1PUD2h3ZHho/D2SSm58KF2o+PGJmYz6PE379fJNWb16xjlzIR\n7uS/GYqSW4Yc1cXF+UfNT7Q7/2A3TlsqUfi56BL/ZAzgE9sQ/bylYX3rdweeusbfhrGIlnPS2VME\noewOctd7kG96opKd5K2+XM7a8JdeczkLJVuOaXutc+F0o9vHzExEmHEgt5XIaNs/KPmboqrfvYFp\noon7Oo7pk4U02HX0CAWTvdzu8IK/u4IGo1DHgM2lJQd/jS2lme5wnhYOgXl/alTnklBpwK9Cjhyo\n8KYpbELv1h0gTHlIIDEUSHipblCLAbZklP1D/BqqbmIY9DAyBJaRIcCioB57BzmqnNduVmPLfYJA\n8JrQwamydtLt/83D+whK0MnswL8YZ3HiBCQ63NWbRtomjTZvDP41unkGJ1VrIcCLMWwPc5ud8/H/\nhvQUpgUfHRpTTX4PJIqe6ZmWMkZokOetT5i+ghbV5abCb10K57+f6g/KKukBgXdhqpnUV8YDh1b9\n3hpYznSbO0TMFBE2hggDjc8MqXWGap/OTFwPB3NIzrefEf+0pcrIaUjDJVz00vSUO1geBBB0qjjA\nxHCY0g4UIJiEpqeeJSCSxYLcZEWgsWDvVWo5L1VJ8lGzx4lFIN6KsSPa25R05lqGhOuzT0ec9Bmf\nK7bo8E4omxlM4DlY12u6CmT9d+QbN4oHJmf4CNOV8WuYxXKozWCSjhNiGq8seQKKbHGizWQohewN\nRNLyHX9MLTLIefXQIc6wT3Ho6s527qa/cZKmZKTASbo6HIDZzhAntO+lj4fYFT6YFMOLVgwdz+Fg\ncJ0PdDm5+eDkyBpUj6fhkNlnmmrzRj+tjqWqnY3TNqNG2SL0suNbKHYZEv/22P/A8pdd+tOoAnaT\nEf2D3DtiuCwiUlqkMXSZHDk+zt1Y2hHzwYT25f4Qg4Y8LyZzBkVhcWwT1Z1UU7EHBqaCZGYLT4hJ\nDp1dB+H4SRaFva9SqyluxotziZnshKrdygvrVzyw56BqofQF2yWSZrqgcor+qJJDTb5sEsVIgxrJ\nHYpaHNZaDD8cdWTi8G77WLnzeG7tHjz08Lf3JQaNxoJyDkwjPcK52ZKLR6I3dU4UbDbsKSpsAwea\n0UIDqIo8N1JTvS/Q0oQlFsndrcsGmfLaT6jcSqVDq+Lc5uvQsPhq2H6xXexIiNxjp6rcoQgnqfxA\njIdsa1GQpJuVdSsAWevMkRGQrEUO91OQx3bgSY7iBvQyKD76a8jlEvL3e7izb6NLt9Q5SsmKUFP7\nP2v6pGcBWRe9oB1pj8o/r+yT7HQPzzk+EYTVrX2AumB2exON1CUeBvXL2HzoqGg+V/aKMLKyHXFP\ntxdAdIPsEOczy/NIAPh5m8IdAm2O+JvPGvaopFyiuDrQ0iY3ud8Ir9fOV7kcOTEEt6MkpvaBjOaA\nfvwRIqx86vhwmgqZOl5/G25MxT4+S5MDvce2G4D1pT5alf05ebu7CwVZHhK4lHzK070J2q7lmZkC\ndIeMbkz172+YWHrlxlQ1XdkrMTmV77w6dvckk96wR560zHr/gafuMOrrNmug9OvoH6vIrFBqVz1z\nUrXsrohOVOPLCpitmr1ae4FM7tBnR33UCZjcYcL8MAtUWTAHkuOq/UEnmoT4bdfPlK8w/M7y2U3j\nXXrMTpaPOhcvWed4QtDP+STgvlnK5paXt3hvtRqj7MvOAvNPvEAKaRwsCsOdGP4pr1RUjxiXY358\nNuyu08WaSZOBSIjeZFSjQBq0aJud2q5l6DmsuPoZ1MZIqcstcIjTIAWve/tsHu9qamkjMrloqr4D\nDTU7f/09V7uZSHHIVrzWBw4FlTYgoFfYFg+lDgs2VSfeu4c0x5TDLQ3/riHuqNR0/K/jPJuXKOh+\nkymdFloGfL27xV3UYXw6lRQRX7lTPY5UOkgGa2YWnh7iqTp4f3/QESRJVTCHi68FrFwQ1/j/rgL9\nJweyMN0JXFXlLv6qY7dNAQ2/2JLjcKvFCrh2ScEJk4YZXrYnHeqTBoOOHt0ZbxIkJ+1yhetZTJ0t\nJO3sArhQFcKByckkq1aJdfL7Ki+r++QsWz5DF70SL5ClpIjLKKIryrMLxZDSALFeQdYmYUV2dh7k\nuzOWOwt++2zfGLQeKbtbQb8EGl73/LBLtRDa2c7HjXv2VCRoYjkNTbW/obN0dYm+TQKpEbgpnnWl\nFXJfvyIqn1ovGgWxkbyb0ZFVM6ZWcL4eSWmLLmoDMjwqmnSoqsrHe8eY15bMOM1E11MGKp+udcmr\nF3AsPuGpArswdU38ht9fobjgwgEa7GrJAazP7um0z44yF5D8uCKM6QRJr8PKnJ5/6kmLLpq1xWX7\nzXe4w12qYcz9k2BJqkIUmFMWaIeJLlN9kyWkpiRoDcGdXdOET6vhnUHLvxCmzpb+v0/MO87wry9Z\nvhn0Xjv1OEVWsBc7wNCyzasG9KfW3da9pPp8DAfesqTvG9BPHCln2vesQ9Fy5fIK2bGTkXqezdz1\niQMZ1dl9VpfKzAbInM5KVQy7nRD+untAvDpSWXE8tAPnRdmmslli1R/epFi0QRuXE9E28IGwIIYD\nBQYBA346tjpQc1slFOBfOKelMGTLlEjUrocE9usHFhMbeA7WNykETkAsOqcMWzR9zoWyPxGcZIec\nm9/hioNiCP4htHT2rM91aqRmQS+fhNfk0RZALsbUeaBf5gKkPy7sMxaVTyBa/GPvZUJUIDtkoUTW\nHW0nOM5v2+i2hknabNshG6/O7yzoBuNcPyQWBIPF5yBF8CgIsFz+jedC++1w61hMnnPXnEAaqqj1\n2SPCrvQL4dFZynGM0iuZLRFdMml9CHN4vHfprdHGJHBICzVhWrRrfk66WDnfpnmlbnekxzmdhYYC\nYce3S0ZJnzlNLhpdTyIAqYjHtGWB/RnUs+n5DPOBmLrDOW64hMhr14VVkrx701ROosCE8pVy8jQ4\nuKmYHZmsAH4Muu7/21vzQKntqiy2wICku/tZ0tOCwifE8EzV5h3fbtatxXXe30Tk/XdhpBTJRUYu\nJvRywZ6+b03bgN98PESv1XJjJV+n7VhiBtTSEB88DEMjAGqkLmPvog9iiZCubydz5kaUiNE1+0T/\nagIxfbpOJ8YX4ODCOsMijcpnErrXNrGLHcTrxeMsMKd3P2jBzTg8i4cTIudPH8NVuYwXl+VciJ7Y\nMcMXZoJQ+0oIxaH7UUofcEXDcxGb6TD2mKybGQY9JqAV8cT6eLvRzBzais+yOe6pFcmp3fUzFd0z\nRcDLiX19vEyFZIZBeeuU75SGcQVcVhIGSDsjn27Tdy/JjvDaDsQ6bqANWmjKbrsPrYNzI0n0AZSy\nphILzSxlhj0lFATH7IA27r3B7P24Dm47MkXCe7oDs8xY6kUvmONohsgb+jpUSsl3knQE8ZAY7FpN\nuc3kvTBvHzyuTdue1ytLNK6DriKnwQ8Ggz8TDI2uv1Ow+bQsjCaN62nm1oRmjo/ukDg75NnsiGFq\nCdKs51OAtVLWPakXN7CByjru06e3Rp6kRXRACw7iMGScgaTDmcqLN0nfCwyeDOwG8k9I+q7u4+56\n2A/BMXw3vbpU/adhGn4p2EUC/CTEb1x99KJ3peTiAOVzOieSAmtmYDSMDFOaPeBFi22q7ZutZ8PC\nZH25LJXrqBYqGhIFUNV5haZds/Tr+tmQHTV29n2dPmebzwvWsWToqCq2IaYER9y4+L3fE8VHnDWK\noHRlhwMmiGu5kfakEZDNGO0dJdPCkX69gZQxsJPvWVhhL1kM6fJoaKYPhKLMMFuOEYMawsC4jdAL\nef+lutL2zqy5OSS0hxCbdI83tKQY0PheSt+WLVWTLiNu1w3BP5KhzawCPSoykAGdl/RtNVeeb9db\n5sxkm5LM59qCA9oJwPdCclao0jaXhzYK1x2K6RPIN6nLrrccfIQA1dl/iXBl5Es7f0tL2hiV7EGo\nzmqT/jxe9Q0226gD+vPhHBH65qZMHvtZ2kreFlYAaQQBXoddL72QnOvRz/H5kIa7y4JmJu1kuUX5\n4HUYA5GjIY4v5DB9Ryaj/fTH+T8945ROh70Jilrmkc1g401zHSYQrJkIuslSmm8A5m78jTfcTtSe\nXtqC+8KBhxA02Wkd7YH1jC+v36YlFYFgAV+mRCXx4QhmOr61d6kKEAsEJf8zdNq1HCUGsLUgg6hC\nbulSL7HNopRSAjeyd/adtGLD62dtGU5QUBnNb034ScobETFgEsUtwP9tH4Q1rjSj0a8SOQ2nfPxh\nJekgSVJ6qm1FCY41VLN+z9FBruKxptQ7URrf02r0Jjg1yqGAfuA4O0fpdA32KHkMgB9ZS7k+id5d\n6ZXpsoP2dQTPLj96FVVhRyGG0k2ZIUKn1V4+TnzejSml9w1Vd9zvYEBURGYGBG/Z793DW8Mo+jFa\njHXB0wmprxQrhuXlir5HQSgeGosjUck2Hs+zOAEfSXkxmE9ovdS/wP1UI9xYWNxJJJzDA7fCcDYz\nZdRLUzr1N0BXhaaILYTLgLQ41BrthcULJFI8LlXv9F+F2aH61i/XF7iMVUYnPVodwl0z8JcvJ3lh\nScxMM9ill9uPY+0sKMI4DJprF9QIaFfobhcHeGou5Bm22TtvV2DziXlyLuXfbMaiS1RfxQjTnaF4\nD+lJKdolGpbPrZa7bndJU9eCRHS1y8T8ymp/35hlDnM6jgpcn8XNhQLAAUnCoPUGEIklWqCgdK1w\ncSHyW6BcJpLwa3F0I/FJChpurwEj96Bd5iZM916H7q1Bzce96SP8BN3gcvgH5G5Dorb4450axvAR\nqW8uyUOp83entDgTAbvrguG3ozD6PLt1PYOUQf2KX8AWQ6Rb0F0B806dsvadjngqNpjreS3f7qp7\nFvPS26/KYKNM7C+X4kCsytcnZs4fTz1REu+HZGklpF1QxsEYvU55GUpk7suYygpb/GkxMehTRXQ4\ndBJ71UOQBmCUtjtImDLoiFUTMXR2GgoBl5s/rOqwFkWbqn0Mz8FAftEEFv2e+3/nApigooO9aIke\n2YuFYNwTBGJe33x0znavAjhbG9SJfLK1MW4iKETj/okr4JU4Xfw03IwDMRR/u7xQpI+0E3sEPZwr\nHifwOTGeyUcEyY20WGEdlMpn9jBTRKN5ycmJ3aLdLL1EX2PvFy1rgYrX+Djoed48hcmPlxzqwCGz\n1GrksbTsIztZnhGCfscHGKZy5wkdD3sNXMXgluSwDB+1ewJXfejfP6MnHekqxWYtYl3Vk1kSCa+a\nkLXU96jUKDWCKtpsyGcMETNv9unlSPgHrfYxytzyK4FrExv6q50sEMIRB160kSNG1IsxQVHDLhcN\ntKyHNn07iwO75tjNhIYAOw7/1u01XXSfBBnVQ46wyt3j6TbO2CfbNXZBrQ6XShoGQGpm08w4QSMr\nA61Tr5WRtmL+Zu1ZQebMYXRxwJgCekXKvs3ZcluuBb49Mwkk56NoRgZLGyEYJ+1IxEJz1BwVm4CJ\nsd+UjbZAYzvA1pCQvzv3r+DFMBpughNx4ec+/y2sxVir4GpcxHQVwt7aNlXmm1gtQD+gZDg0KVcT\nlKACz+CEVcLihTpM7ibQdx7UQRMQ8YEmHNrMyMl65Jh3J1qPb7k/KvxiUm9zDqgchtp0/Hj08too\niHRhnNA7UxoGRPCLYhwVyFCogCteAykzUgpvFwgshq2zPRa/L8e7TTDJhRVf7wt4XCTbUGb3UQoH\n7dp+GJKu/jrIDw4P61m8FnHIEDAn56gQ/JyYYaK7qyPXDpGxBOhvjJnFij8r0OY6NDXkOI/8M0Di\nENW6dOI5QYnQpI18+5JsSoLG/aadGaK7D0/kHZLxWP1bfk0gTHfbBjqyUFwaE+yMK1NNs08IqC69\nDsgEtvZnB+3svy1EeMJSxfY9S1NkOHP/PS3t3XYkgY7vXlqLWTSpZcvz0tQyXEoGuVZ0EMCOPWiz\nS0Rjt5pItZ89kqiBxZkVTJwjnGulFTVWv0R9CyoL8/sqsZuCEw+ZLvYfXVBnWnCp2CbRtd/PVYQa\njDhgOsTDOkHq4K5A2xmIB/v10oYtAiAWGQxiO7Y32EnneZnPR3qrNjPtAOP9dTBg/D7km/j0W/bz\n0H1hgf6AaLlefGMWf46Wmuz5txY1EdsdUAnI9W9tAVsyWb5imz5E4zeFSLm4TfuLlaIUGeTaRpv6\nWpUicSuE/kLFZD8lOESIOLDBJTHmIWtYXTB3JTUYr8AFdvxJwDQPMcLaCXXQuc3/RlT+Icc/HwjQ\nHdTZffINd76bkTJjv+t5S6P/b7J5a8PnPw4u0NsDwInbH1moxCpAxNuzf73Q0esKEYnWOB2QCNDT\nklPntYHzypdHOBsz05vph5PeZHRsbSrkDe4LbZ04S5zzkqbFuuHWhPeL7sVw1eoBgDFs/gKL1q4z\n+kXHUvwWcUfxzfjx4A0tIwT3knlPNUq6CeH07vEvq3uho0PVwBZivHbVI2oEs+KgNo8sWgR4gK5z\nFAacAwbPOKYDCcjoMC+VSBsBuK6SPksiycpClpqYo7ctPALK4vtsjTLEyUU0fwnF8KzZbMcloRQX\n7/eSUnbYtZ2i0bcT9gcTXk9IevbcP75L/js/Vx6RXo9zN7PohQYZrEjeoUSaOz0VHZidi9pnQJI1\nTUJI4ZP2azdGgHTw1o7t4v9t3yat6JTacs6HK9MEOn08k184Msj9e4GAPSpsEp1aQD4DsKQ3RJZY\nHwhWFam315UpraBflGW013RjfIYhdJaK1euCFuafhOgKTr8oVLlYkm7lP1Ouol79v55j589DXcQm\nj+8WHaubwUyQ6T3ZVMJH2UfvlooqY9aBSPCLI9SBrSLZ332NDwdvHHQNG3h3F244meO1fXrMjzyW\n/I8Mc/kG8AsSQMWt6lDmU2jWUHi77MJ/SCaGXUFyzzQpt18kDcL8fVUZMLHjSZ5FfI/yNEzS3S1C\nk1vZI/QWu7ZLJnNXnA3NqXvqsxg8g8/loMzhI9AwCM115SikwW3YLV5iJEhI+EhZZjEO1gEyfMsW\nL4IYslHgNKUELCUgF4eN4msqZgkVKy7cF92EiQIQnsCWOG5pNlnA0TazBQHHdAdGi5aaDIBq45DZ\ngPr275Ofx1NQ4g+1Bo1oR5Flc9Z7o0ulfgC+CtPfAtCgKtYD3oKzHtphfDfK6h9Lmv4xU6BfnPVF\n1KBWAPA9qZTMQg9FJFm/Ci/gT/zPcSa+E4EBusn+eohNdN2FPMHbhQSetLIllC057lX5Al0tOcTe\n4hs2tVQbXsKn9vau4AYmTbLae/ZGISKT7DDrDmumxdvAvRzZMCz/iLlv2gxO9KQE4B2Rl/hIrLNr\n18l0OQATijqS2NRIlknpwTFLihYQerQ5Kqt6zbE6Gbwvt3aaQ/q0bjbkzZ4OlXO9cbazAV+Lc1MX\npQ+mXyZek5tQWIzJjQ/CJe+U1wNdMNFp8Isvj0C0DuVtPHIMR2g4m8LuCYgzGuDtWO0A1Asb/ZLF\nR/Rl9mOST8AW3xOHOo7CvCjU52i+1AbNzheXyASw8keBuCKc6sbsBzCJ9+3FiiLhLuhdBA03SPZA\n7rdI3Y7PaR66yjg/LEUkqxxMLxK7c2uyVeoNE/O9+uttHMqToltijBT2jUL9XBcCiQw8w043IwGX\nUQ0cw8qFM6jRJBl3LjP3zZfAvdITDa5R3718Ay+AqrBdMqo5Qdz1vLd9hxqNGpP1FPjkdUvIiiEd\nUmH8s7/8SovNuLC/Vn9Bjc3y14QnILqDjZkQPLd3h+uohOYikSznhO/Oq358LKZa6VDgLjbuDWQE\nTV4E4lrqxy3zxyINOfBAR1+LsFwD4PNmMXktMhR4eDpDbcIGXzgZ1gQ+Uz8CXZi1w6UTpAVDdjL0\njzBLZnc1acrfVGnPHYmUUr1v7miMfVv7RK2ySCCfUyEnC868tfyfZv8kyK1sP7egJrpCvJEwHd6k\n1mdsFyRMcv02NbCXrT7VhU3MNoYw3vpRGgI4a3bgUvDqOM3xJmjAuNNEih9D26koMHLIx+NahPST\nnKFPJzlJOMmEJCkVS2h+gLnrjiHiNXc98c7+PEbTCVzPhoxQ86SFqFinogctDHWofAAZoEXd9Zd3\noAhWghtdxMbBMBXIy3Ww38m3jZV0w/tlExCrJ8YuC1fX9er53QgF5LL51UT5qT620I1ag160OBL+\nFgB5244/PZ1T7CNiMd0995dCBH+Qg1NZJO8iUHjvjJhVAmmtnUDCoaw3rEJ9eXutXSWH+T7WUnfz\nG0I0IB6gXeJInb856HGM4LzqGjvHFM6GlWjrp7g5XgQ8BV6MlaS2dPSfCbgASkr6ciBV+VEDtxvv\nLecBMA+FbolUT8IlyL4KYZS+gay2R3JA1YMsqoTMreBxd0Lo61UwuCeDM4GcFrzI/ZfDH+IU+1v4\nLr/bLUrJgNFp5269KdwTbH8rD/b1Nv9MbI3h8VbCMMZbzVtinhke41AM95BPNVUzRR+IKC4ftkHF\nXLOJxM1huPMZKDILeclF+Qtl3rBJjefSgYRt/KxFCzVN2UOmqnwxb/GO3jeobVur121+VAhh0hgc\n6U9NwO43Pr7QqyN+7wJT8bWuyIOb97Bs4R+gdqZSxpQwyYcWNWb3+Wh7DNKn4JAHCfhwJTsj6XpH\n7ZiUeTk7UX5z/iJz4V9/msHOdP9Y/CWSHB2I8nWTpBl7hNj6lUcxTRqocrolXhDYU9lt2Np1scwW\nDzDnFrGzPphcytpZbGXv7sR3S52iB5e9B7GhJw0HgxtesuNpMLfsRzK86syhaQMCEomCu6pxRccG\nfElsvk2eedjv8DMYATSMusBPZ6NYgylQX0G2szz6nEM2bTTPNjcx5p5RmxGk/lpoINImu7V/wj8c\nEuw8JiNh/MqAn73cmc+vCM69qL4wk/Ln1BIi2TGf7JOpcSxO0gcPCJko/TjcmgYHevzjvJSE8xYL\n1dCxtKR4x16qUYamg9y5/V7eyM5936PU3b5Z1zc2F+41tsyLOmFOmZuSPlnmYEyKuzyp484S3rTJ\n7WE2vcUb3WCJSEU8HDAHbKOcnuDSNn1ZBX7l8imKUj2zQ6EMC2z890q/MqRRo+g0kcmRYRR7Xlfd\nDcFhdSrwUEzmU6WZgVjJuPIxV2UEOFLJreGnxRzB0KZhLMJ6CuWFBYHsO6sJb9FDfn/1nv0rdctx\nVVqEgTspRTyuD9ZiGLpwx49jNyJLCJVd/uQNCAMHG3WwfwaLXX1P6eqWG5sFdbcIBQTBumYzdYV8\nHnmsFv67jD2ramLOWG4fQrZo4l7G19y9EHzWYuBgxFE1d1VHBT/VkIyhld8McoOUWlfkH2SqNsoN\n26vdW3NOIbpaheU4eH7LMfOr1kYyNAfpRSUcIDXmKhBvZXRhOUChkmlalpSiDFDKxJ7jmw+Jnur5\naWm8FXg1dSof0VlLk2JW4c3pQjhbrm4VWRkwU2gOU+oUCHz0LJ6Of/4zG3Ib85ImF4POpuvvWVzT\npx5FGgi/0FsssO49D8+2itQVxaiVzdjrmPm+NnwMTzWDDh+NQfQJFRvsf+BeaHRiHMsp8xdW+ERG\npTTNrPN+D2Lc0SVEWA+vzj3xp+r3tOTHBB4XKXeDpUiqr60vIYH8K3UAka3jduXqXTQzvJXvXUfe\n6DxGH8ZC3pbasp2jSXkMtJd4HHteSbRfIUiE3uyPmjSgqLQ3QZY3KYnEwEMLfv3Pa2ygbBBs3CeZ\nUt6Y77lq90njxgm6i5vNGheVAbtpqPHyfdFE6anYRzF5A9/MA4QcARcPuHkbiMTI8HEdyucfDdmr\nEkGzWCF1H/4f+wLuYCKu77fjQiPk9RbOMccWO86no4MJucf1KIjG2fk4KS1qVlqlpA5yAiIh+jPV\nNX6lCRRuZ+KxChvzBNKb98qZqVoPemfc2jwuD1PKJ3+iPNvhVvgogE3bT60rymlqUNy7O8VURkoW\nTL8jgN/6L9gOHZMqiTIwH8FTI+jihn8HS2Xs1vX9DgVT9YoWfLGwl5jyrHwbrzn4vsDgRpKMDyYv\nyYga8TN5uF/IDb65QwvjxTzZb6Y+b5DZVQ9xANqrQaKA/qJwjjekNt/wBRR8uxXoyjOK64BW85XV\n5nKEX0FsyQz3Tpkh2zKn4VjCZsYcAkqMN8bfu+yJwmUz/Ko0WEuOq8nbV5cbvyMY12q7xI/d7CMu\nAGOw/CihZ4JYCK41K2vxH95TlEMohGp6CHuLRJrcrAQ2FxthU/mHRApJd1VcjK67GFy/rI4Izl/I\nonAA0nGgfVFLUN3flY6Ah3djnRtw9gOoDaM+6Gcg2txPWZtoFt+UWoWnIlq+IHp7X3WUHo/0Rhs5\n8qD0NwIiMN2OkbDY0LxY35o1ANNnANmUwSgIE/j60oCIeVC/FFwirRxYDS27gMrY/WKdw61fI1YD\n/JknXxa05Lnpg0rB5RCVpmcLIYzHGPGlVvroFlG3lWw7bmVDbOCtpk+Xq/ZUbgvjwEL64g6WRLXy\nJCbzEUU77qlEyy9mA2znG4GA/mgBEqbSStYMb71wOoFEqVCPhE4iFkkbmxJ1vQatgiqbb1fp9/S4\nk4Rz37BSFmp4vg9DvQasuRw2KKooa8bbtuVNhyCxN3j4L9BnLXI9NxP7hP8lMBYVxu10tG8LDeOr\nRO9Tm6m7b7AvasY5acQJIPu2Z3f81FFl5N0xFjJFxhXLtJ91QUjxvcu/AYVKZiYg1TLGtWeyBBAy\nyAXNrpwiWFuIDwD2S+QYuIxyqp0YkIPa5RLXdW1qaS4hTAOMRCaRku0SaOf0lCU2GHAbWRkAdp4B\nhGlr3wdn42E+QHvqgJXatmSGMsGYRAf9pO5IkDWW8p/7Ae+ItefEz14swOPVw+hFzjkgKj+N1lnL\nZABD+1Zq5av62BaeC/o7+PzQAK0qLnwbinA/8zoZkn89bM8vNSBgbkQaScNq5XE8rgD6nqAcLiMW\naj8x8/6ylUnylx/rg484udVfjv8M++g0npvbXK12ezuwPRYAE7l0AORKc1BW41Qb/RX/8CoUa7Ui\nl5HncnUA421aTmt0RL05imF4h/euBvbKCEs+eDoHwljoXkXaQ+zQDwhIWSkLVVeyHauDhydCXBWR\n70Aw7T6aYQxA4/3/LqTLCdl0I+6u127Ntp7SXlQYPlk09RpptKs59aN6U5wD3YSzjaUOcVVHHSKr\nIkAPlO57FG6DMfQ/W8STtpTZHg5lxsV8azWY59o2lKDKeV1T0p1id/k9ezPLJud89lEHeSw1QMdf\nOMvYrPfAZvDpsCKak4cplQ5S+YlwKV3BjBTuLsND2JifopCOqsvooZ4WzuemQPfKvjnfp8MPgJWu\nz8G36dXZnZDClGzeylf3fx/TFfl1Cc8ayw2KDxlDRwtbZLNdd1YKN9QO9VYKxQAVm98vbfMong2C\n8z00FwSa6rZDJrv8Hyqjoyr6K0US/Aj8QbCx/4ZIQwKCVW0rP+GoaCfRFqRs6oMAxObyBq7wCLIt\nfzQc1JLlhV7PATR5bKcIcZng3Yvyh5Zy3Oe/AAmuziBeha6039ffwofKalSRvNs13CVOrJQ3MUHX\nX7z3oQGzGEGphydPfZQQvbgr+8LmUC6b/iEk8xyYero8D893IFh8wVJ5o7xVo0z8T6+bZUh5tIzV\nPZjpe0o9/1pK/FznzEnsYOWJ26TTJqMmz3wmiWO4pyCweI0Etc0FiTwRpHv8hxf/AceK97+UIsw/\nmc22b8vOGt42wGzW/ew6hfaBcwedfG4RQ1mlajrURZKlXud5gCW64msjFFiFLGjq2wDCrta/1/4W\n2vwTywQxQM8fhfUc6NeyysmQyYmVEfZ2FwDy0ASp1duUvyx5HIgDJJmmeOhYmroGI1B1U/sN5EJ/\n6Xmg/jXYfAZ1qHh3zsVTOmr60U/yfEOf3EUi996Bgoik/fC60IVz0ONsk6QJ3H3D9RZ1ZOlTIjeN\nGH5nW2QLKA/hQXOO+pQ3ox9dT55XA8FpxCJ99rohIhUOC0BYGhoGoMQNmGOxDZw1kw2hnwGaL+JE\n8FpVFv+GohFIGZYme92nZKY0gizOpmHnJM/icFcxpMODJsAGh/Dtos+wbaJuFeyW1aEXtWQriyt5\npwXd429xQ28mFeHze2CIrfJJj5CZJlu7uGqHUHBgPjRJYUNn3S2DcXOr9Ce4pIkrVMzbQAea/VTC\nsCGdvR569PwDNhlTYJ6Q/xC9sLP+Zc4GAYSqVkXGwbmckXDbyfA+E0aHeRLSdQfUn135jMxo4K0R\nbzRvnM2dw1FYFnd8viVBQIWJqPAqMgnvdgMEeL2TyxFIdyH71Y8YaoUreqMi2K8zrwhsPasLgvq2\nQ49LiGhuUT9NJqrC4byAgVQCo2/4yU7zga4K0GdPMB4Dhlb4VDo3Xf+caFwScHs5DMNho5H2UQ5r\nu4MF6ZJybmcDARHSSs65i7nBeHjutYt9VzwXp7/QtScBzqn2QhAl4zww22nq3Jx18jqLCXRATdBH\nlcQuJ60uaH/cHTfeTJ2nBkph4z3k0nw3R3ooa5+vn4yOZA+ApnfL9HKwbg8XwOlCnFc3eVeBLQDr\nJ0L5KtIwprH/UjIjbnrbIRZWK30N7SzPpWyVAe6AMvK0O4zybrMgiXsApk/KA+Mh7DIxB8EgIlKI\niA3Yt/KtekTa4uMQut/EOuAMIw+2xCL4X7t0vupJs2SfNzcfw04GAl/R8YUfZxVSHrfw8nzaEJ7w\nqjBDh+Oe1D6UFzsn99gkalY/19suZXirYpZfwjXZwsItwOBtGaEpvoZ8M76MSIal+cauC5sem9gc\nSWkUAmr55D/XGW3ycF9JUFuCu1nlgUpm4ZK+6aqcone/6VbeQh1J4gyAHA1JnSTCbPDtrQx9bqh4\ncRmD9oeUlirLs90iLzPozq/8PkavElbMWMh4DTOqL9Bs0qGElwKhTybuuYSPCGuhR3mE8oxsKsp0\nWYPNd3HWDX/gnpnLmwwaVl42y/fvCoUua2V+cZMTGtUW5mtedg/CiOJ4mIDlY0JGTFkOKaTEDTiX\nSy9qEJZdM86N0Hs83ldmSQvvyHk+mM0DxEslhcTC+/MumFGbhmMqu5Qz//6fdoyHyib66AGe7+3V\n2p3/PeJMSF1vkEiTZIcjow7cdKeoBE1RtUsr4sOFoMbS5GnzPGO6+lusk/7s9zofs9YSf2GDL2Kl\nZqA9ro1FHEcRBVKdPUM0A0l7FIwJnIQvZLtSrGqq3n7Fj7sPO55s+s69c+NI4k0+4AtO3Jb9J4S8\nsJEkFqABX26A4JP6+p+PPGoq70asKuAuO9hzWcfhyLdXNiT0fBTrdywU4gG+sDujdfRPNm6ttJOk\nZjHbAbnjEvl53hEXVw+NNylGl8kLv1HnXhP5VogGV57CB8tfrVtypSRo6qsWteq67+FOkZvPvPhw\nx+oOaDhvj9BYylf/kEkQsg6ECK+Z9EVP6Ahk9AY2tsrZfiUg2sSqkTMglC+wGHz8ZFLuwNyw4CEf\nGjoFmPUkXw0BcLUCY2UG09xexhIjrIWJQ9C5NpmSPieZPeqJIVjQvbelldK6c4lZjGIBguT2Vmep\nfTG128d22dMpwOUgi+VJ8lj5bgWeSNH6IhQ9+WljexVniDBuNgyflU9sXtQAwZwwLnStG2JOlk+O\nQjqeOQJuDgLQleSqhxRXYkr780nNLGDO3vKbBNKA8MQTtbbW4DpM59DCTjADOOqwgaB0E8kV/IKF\nWWSKOcAtW7lOiJzsXvwbuR0CWUbcA8yehGUWmx2R7qKnR8L92GY/+NL1jArvlw5G24uEkDtdBG3L\nREYq/AWn6ymvTXqVCU6O3Ybaly0Qt8f0QN5kpoHacqP+05Gt7DFKXdAKNKyZ3OW2pi91vkvAcB23\n/ZeC4MWpbJnFwRASUAypvd0Eh1UO9rXF80gkK+uDvRVPoWNKRfg04ry9A0MMr0FkxWK+iPp8B8ot\neaN+5pFRyEQONa0VShWj/Gohent5S3UKZf/dqFyhEmNtqbjEpYTIy8uR8JdBjLqmKfUNrCTJiyeD\nsUKqwu1epV0DXakflCTBn22NB9ZR/pP6Bsu7spnmr3frbf1LH1f1qWonuovtSNSWAx5uMLVthi2f\ndJoLerhOzvE/1h03rkd+igCZKucLEPPutTdpjfgPtjfdqWEEQyT0mx7WyNmHFOTjOD+dpYOj2GOa\nwtRQ5Gsfpq5pPxhYwdo9hXvU/EmlzKFf+AUaLSZje741qsLYhxPtRR1nuNcdK1+q1i6zGD3I/lio\nroZ8btQMucydA9VkKK2ZV4RTIF0cgEHqAj7bpUmVFVDf0xs0iqp4eAA4enMjLzFWXUIwVzF1+r76\nqaBJph5V5SP327vqp6zDDoiYioqHoIZ7MMCacgdgdQQz+8rrfmTJnR/geV8syT8wAS62LSZiCBEK\nWKUY6gVIVmrIejPCVl0Mp8H5AtLTdxPVq3UPYvO/M1fhdvZG7ZTe3Jt5VMrdmaM5YktZuCo1nMIS\na/TuQMvhDX3txYHu9fdLMoXGSYlRen6YtlY1oWiQfz4JrvYJPeRGCRUQinYbNjpRA1NoEBcoiQiE\nMdJmlxnH4d5XrI9ZfW8MjY38NxLNtVrrR2HV26SAx4Et5sLbUzgVJFhqbA5iXPhcDLXbTBVu5LvA\n0zY/yOQg6VAo1+Me73OXUcMANSxCcEqXeSdVOZmEVe1Nt4Het6npy6Zx0FRo+5L5GpMNDbDrfE8G\nVDr3WMrXLoNAf3VEdZ4RoyBEqZNsXEVZEb9IXmVMlxNtXTJ6dtZLObn5/wOK+jAle7+m18KlmDbu\njmP1hHkulSHR3r5BZX6hv4jgVTsGcbFOk1qVjo1Ks/IyxaDd3ZRrAFe0+YtW3r9UINOYZg6DlZFW\naKK7jZ0Gyz24buZg2laPbOr4F7YYDVHrULXpT9kZYoebkvzItcYZxgZLJMuwHlgIBREqES96CGsK\n6RS9iDGugiZBK0W+a3W/RZVaCo1uXkjruLlIkqUNv24gJTfbp+O8Fmwi+6gTjL7X/WawjAeHMsCm\nSuXuQv+K5TJmJ3OTEOjb9cYxrx8YwDJ+QNftwipzMpfRBifksW8Nksk0Jnjn3onTiQrNY6eB3EaU\nYdbqiEVvz0+B2eBnUZPruM0dgjYOfYiD61mE7ytOabm5l73y6vM4VigHG3Rra4msikUZpq7AkNjK\nKzjpo7IFVi0MV/kVfApjnhXdV4amQE0AzuPXU/FZZBBnt4AQl2b1UbHHLe5+UyNSNP4/yyjRjx0Z\n8ff+zWMaReptipW4gkO6LF8nYurJnGYk/6uPrPS+suArvSCWDXOwsqeciBrR1dKqB9sFCdB1g5Js\nSdIkCEUJM4ZNQ6j/MPyzVkuuDGImo49msAZZ1nwCRqX5lL26N5auG6G0CHdj3TTwQGgJhX2TBD7x\n/a0o9/kgUO7kkT4FQEm8YoVWES59ADJugfon+i9dltoqZFzK+Kz4H7CBQy51aZcBd1Z/sSJ+tRaa\nlLhutLatD4dQAs9nbQVwyZ3bnXwoUsOcGWDTfWFavtDQaUYf2E4Rv5WvYFkeORjuVkAhEiVSQTRQ\nysidLe4XhdF0oDxB0rezR2SARmLT6hChaxgAA8lQSleaaBsHAttpCY80fhTQgREQoq1oR28uEzN5\nYS1FwYh1DSAnQRt538pDKyuzXTZomct7G3mMIDChLv8SuddfAbUlMjTBu6CFVLqb/GMFADDq6P36\nxVD0Vd98LrGAiUGrkGD+gx/gpo8RInfpYbGtgTawYVoUJ50fiD0JsB5IbRphUn8AdzoZLLCBXUSF\nDxTTrcQ3HKL8DO/jcq8W4Lz4PCwZzuDU8PrBX+F3FkBok313VUvS4WMb10zgdM4iKAnqL5NCPlG9\nn8Yq2uMOQJcWSzhLWQjUpGdIOY18x88Z8j+LSFYytCVUATIvUOE0vsHUX2K+BWaZ2JYwY1gch9Hz\nRADFHkmuA1blcOacCctpAtFIa0sbamGgKT5KGXwIEELQvR9/1U2H9votxoz0wLQqJe9HXWlj0qE3\ngDaSeaLQpg7UQkFN0YFPaiGc41DIzINXiY27I3DABxnicleDxi+npA548W3v6LwdceW1LlxfYcfI\nn5PKAHytRxSfqnpXZtiCP69ZpMzK+3xDJDBA1DzJQun0P/8DN1BgwimKKcGHHmy6MSx8eRAIXnr3\nhNu0SKlNoFYsC0dZMtgzTo3wxDsRU3/nmme67/OweQlWowCVvttXfS5ZPvMDEH71aF3IiX/dRJDb\najtqNWmCcNNuGfy6TG58/CbvGC2yqPKjun5yA4CL5+Q1rn4vv1Ns3aK2h9iVjjZyuv9dGwFNZJK6\nOT248gam8IaRqu1jLVP4EMD+fclclPWUoVdVmF82A5VAX61PQNrWxjIcSCgZzXQYxIax5gp5G8WJ\nRlsqCtOHSwRIuDdSPa4thBM48hwiqPRGMVq+t1JMgP+90CEYli1M1/gANz2CBetTpRWWVclTwQmP\nS27nQAH1mQxJhvAaK9DYi2irgpUJnx7WQIOC9EawzgB32i3FMUNxZzSjZNXre9/kvIEcYWkDge+A\nBLALSB0WWXltAvtuAKmNxCKYIUzJlltF6QmQiiArAflNS3D8Fc4IdL9p807KVozdaAW9mKzIhARp\nO2GIMYvPJJy+I2WdZ+VGu/oaDDHwtcskW5WmbYiQR8J0vJHXZARoUY4miuMiPyAlog3woGeUL71v\n3kgSSxuM3OJ3HgI+jhJvLZFmAqXme8pt3tl7MB2wIF/NsPPz3mJOhEScL4YlrfHSEEJH6SqyBrF2\nPUrbeInPyM6J1UO3p3UyKkZkwPKm11Tg6nfkslHFUvd0spn4aeJWe1IpZIcNU5nxkI5KFKsyxW/P\nlohfj/2/16qXHq9WGPPU2C7rhe99z73OXWJkwxFbGp7DxNHrG3qAZtpW02GrMaqYkBI3W8kNq8S3\nVKmdCsktg6IGc7vICnTjsc2GsWDuYx0xi893VcBnt54L9MGVIYmVBdplIfR3XQsLGXldq1+1Y7z2\nfnCwrZPeqhxrqMr0ukA7DCFeFROzKhrbGA4R0hrrQw/q/vfrufsY7LTcCpMekiNX7MxxHRNJBgyV\nX0uG4EbFrsuQWmw6aNd2Oa+ndWsnkZ1/Qzlg5nP/m3VtcDmLl+Bh0zsm5VzSGXmIZ6lbYXbC1Vsj\nqIzjOhZM0VWqEvkCoz5XJ1eirUc8kfJvou/G1fM8ad3mKKj7j5+U/cy7FHo5QF9hvTC1Q0RFyoPr\n4FRCxVmiKh4c/4GKaszu65RObJ29S/aN7iIOZ0tNtjyp/ek3VHgu31KnfH7X7kGleGXCF81tPVTJ\nXMCLNlINk/ZNBMnsF0BZm/v2nXzC4gcEoJMsp9bSQeWWeVslGFpBmuqej9lFxhYQtuzow42Wd+2i\n5wlWphfhHY6WTwUPQSNZjkEvRrsZYvf0OH+8Dr6Ob1QrHaDSR3rcM+smW2pWEytcvB9gOM3iWMP0\njFhFddu8CpAoHGHdBoGhXXHnDCUSCAqZvscWPXezrGaa6cyaX9va1l/hum08byjfdU4wgrFGYgO7\n/44xFHDMbL12FlRfbGlYq7j/ZCnvb7v4HlLVzO/lpwWdcArS7SCn/IhfGilX/zKNPTgWcCO8HZSS\nIUcGnR2jqs+XccHj/5Lhp1NhOXmcaf7fLUe9z/5wbBJ0+iE2DODoMEUSEWZ4KkN33a764ufAAo7k\nqGiUDi2igAHxe8UW2ecnHviT4vmPdAlK/xYYKyVNmcEmPsx6tRDyougusVb4KLERzf2Hqqg0urg0\n8lY7iWHsenBWJSReGFSFlzot5rW3gIyP/f/3ALEKnHnF4wwCR/kCg3Y0NmllTO+pbonpFeYCs5My\nq6npW1gGJ5+CjAX85/v83lAoecOmcpp+SIZVXn2DiBIl5riFp0csm+V2iHIe9qhUYjo0VzjdJvVC\nKCirQG/T+nlk5KqaHAZQlns0DU36FYjtA0U6zjMGik5toUfjZOACBG4hoXL9TMPh51/BcO3Lbh3N\nXHz6jxzxtvhL2VJHbd5NQjybpPJS/fWW8MqgDx9PHunn/ER9xVWQQ7fNgjTciTQQRVApwzKnx8UK\n8vPCfEVu3pbp3iX4tXvYhpkfS1S9kboPPGaAgzNgjbA8jaIshB+ajpaHpfiNKFW+UOzl2okkw9VR\nuRfUGurZITwEeiMbvY20LC+g2OBkB6RRMW1/qySqbAIehUaVw++CCu74Z0vxIsnlHkAC+UP8cBb1\ntiVRnzi3ahlfxH0kZWzD46My9DwRkMQZaiJ9tqzGEdKzFh2ckiixmC4+f2QnBXiOnMUMsFvM5ce1\n+8vJGfQY1/Eo1uS1i+avrIzrS4LZmjQvtq+XO7wQrFfghoTUmKsoOa5cA1DKf4w07V3/POK2F+cU\ntWV8JOUijogfE3hpgscbGW4uYLiNnHgsQA9OvbMICdpSxfg3nsQwQx08oJbBATP0l231H52U7Bhk\n4qRnaKInzpV1fBSoEWrpcYspk/csKPaSmRIzp/keJRCQ2ST30a5s+2hulKhk+PUP38xe5LbN7tgg\n0sjLhwlEJNyYNbY3GHb5+L1DL1aVU4G0KJTNKbB1r8rTHBcP8XZtNh1OkZ1WojMfgSkGNRQA+u9Z\n+qZ9OAISVM5JW8TfcHA7vIWqWEx+sRcottR+YnvqK9P28xtt0rsqapaJYIecOX81nmsJVPvITJQ1\nTFnQRWajieo6Tbo3XpqaC/MhSNZMRyVo6IwOmK5KpWHdq76w3vyuVKh1O1dU7fvwNRnH40AGTTBO\nvpkQfa3g4mQxyQevG8tGyL2t0B7maFnfQYOjwgzLOfvZOytBNsyVMn520jaoF6VITg4AvNVU7EDd\ntZ9mssgF+XcsOvqLdXeylPcBOF3Ag1Z2UL1dt5XieFEg+3Qy5NacY3Bmv4q3MsiY5g6OPaBsfIq3\nC9fHqTUW6vlVmU3JGAPzTolkd6XICYBmIbcxRqq1Bl6zGOD3uecShbOlKEvDnjr96sweP8kbWhHV\nkjhoz0cCtssP0GGJhui2Iob6fOf7alniLcdV6Kp0UNeJYa4tEETTb2hFs1G43ozEZdohUSyCFi3G\nIzlI8pLXMQzAhTqNUYPZ6Yq+IS87Ab/bcprjWNSIXxss6enpMIJLNpKIWdnRtm845wgwckdTrsGV\nwptAiHGdS+dw7WITp6Id8fS4WaKlZReyvjSbpi7rOzQsKroNWEsZl9CD+s2aWIecC9Xp2/95gTPr\njxAKukD05CULBOpoGF7AL08JfoD0rBR4XK+CTPg0EUWBVZ1u+SsftWgSsGLnleVvxizEu0On3Nkh\nTJP4XBRYOc401Hb/DfDQlDYzGVQPVri3NoKaKuSMpBJqHs32IlPW4b367vQMQ9T6eivoypugTPAP\nn0edlinph0fPV5EWHf4ZVB8z6ZumQCkUFFnZiChtB7IhyRz5Ndh05H2wmN8Q4tKDVZtdXJUrsXOu\nOx2NgaJ4COimBSJSYJYXNVX8nI8e3tFkx/yR0gMaXJyAj5C7WSvJC4RpfLaVkoun6UW4OeHEN/E1\nqSk1IoIVeiRP1bUe9jvIbB8srtkBh42cqapFPwTKo1TZZriKtjdNUOoAmNvsVRBYH9nTwvdevOSY\n4hnYudep5M3Dt5h9mr0RtU1zn/N2sQK352Txr9HJxMdMz9u4a9ADB8Swtj7qWtWxyUcHwnDtV4Jl\n0+BEmOSrteLGZfOO1/+FJzyCuvK0I5s0OnJVO1nvDgrqiZOVXIVSLFISrw8VzGYoB3RFr8yyAMbH\nu7wxFuHEGL1aid9izu1JEzZTpLnF64WltqMJnqWBbDSxakc0nptmKiGGTCQDn0ypCPv/u5shA/vn\nagQJ4c5bjkUV1nx7c9cP1lGsVm/07r2H4udbejlNTOIEUDlBvndNbVp94N7B7QL6hqEg/5OdtwW7\nY9PGPBVeTanNukyGCCHx6bFSDG759fm0X/MFlbyFabI+/OBsibD1it4eqAYbK7me70SotN/MP/oV\nQwaCpDQb6x2esHwrB4CVwmD2Akc1NO+t+NcaRuCow+uumlXBau2YWGWPVtwraqBbhrUNgsqxh3k9\nceItbpZMZc6ll0uXcd7Wu+UvQ/bGnwfsT8zOl5zCbMj/6FI+WHUBnWNAg7TLVuAEmol4VkQL1tSf\nWGHYqnY41Vm78l4jndLrPpK/XOm1o2hgstHUpoO5aycH13TcuSWm/NI/VKFGfnVTDXJT3dPkaIyS\nd6T+JnX0kSFDBEKc7u+UjbhLMBV8FhFt5Ho8V5mP0UmvKi2QzQqqq5zKLmPfdBAKoquUESNwwwAk\nlZqh9Ypd+0OXD5uMDLwIYesDPbSpvXC4Fxv2rY7bniwx0COc4+WAlTeMSMLIwAdoYYZqKTTczufR\nD/4fM+QQ3JOb+yvUUqc36w6j6U0uCRRtSbiDyw9bTBCQWNi/Jtek/QKJdBx2p/yVLBa2Z4nqnNpF\nfayjxRESpprStGC2X94df376fSkoanjv9S/SSRrOXVgfZrlMPgBNpAsbbIOZaP/bgbpbah36GptD\nEd8uI9KhT9p4Xotg+5bDJg7Lr+VktyEnvZkCXsVlDYdHt59DDamfkbLqxJhERv5gqg5rfPv8n+RA\nT5qXlSyjXUXd3rbT+s29NbqItEdI2PiQF7nAeApz1KfR8Cn8WadCnIIuiYu87arDzb6xATmefOB7\nhI5e1jm8FmhA+W4t4NQ6yfolYXOazgwb3s/4rg1HjkZsErUJugrcBtgY0JRi32nR6vyj8RwcE9uT\nQ0LQQ5MxEP6mK/XE70FJ1XQBOe+OoKA1JOkVlh4HKTmSlOzfXoH3ZMd7Qep2m5tZ4aCBbMk89N2s\nJKCxgGpkl+dWOOFFwB+UeSYoaOicML2Jj35MY9lAK6yv7/DAp9Pd8gDTrarh6E1Buf6fvYkb095m\nBale7lbwlRDVDEKERLD4RkzxJZ3cioegrxgJ98H15DnRlnlJEUT4AtP+7xJ/8gVckkAhNWnOD622\nT4poHPIgAH08kecGhqJBpwvto9cXh10MToMSnYTOhS0jj8FPs6Lng24FS/EY+ARqgMlDV2sDYoVO\n+JeW4KWlDiTV6NBBAyqoRYkGlt17RTB0GLdGvbtWd3ccQSOfnhKdxQ3CyuRf4b4x+Pdj5j4NaMSW\nNOTUntzUK/cWoRa5GmMVHiykDqG34ho33xNIUw3Zv0H4HShYwcRoLvxEUEASsXWGVCJI18Q7Pl7H\nAtNO8807Cu0YCJwZH3DGmFqSzlJpTVlMiNTFID738g+THzTi+ZCv0Uye6/sPKs/VFXfy+4psaR0o\n+8Uws+yLsNYxF/kCZm/poclMMhrzRapV1hxw/2F3g3IJ//LKAW5xP3rwXhFCp71E43QywnJizITJ\nAa5MrK7XL1MLg6sU1Z2U9QAM6AyctbSxR6Yk2BASRV54eX5Qcub5nD/7oCg9M4hGxkmJ7ScTTabh\nZTGgzUBEo1HdgcruMnI9eMiSyWcuSHZ338YjccwujpYHMnOwseRoQZag74IYWauDklVL7XHUo1Su\nKnf9i46O7PZ1L0BiEZpBjEpJsIe+SopKRN1SBW8/QGTTKrOn3ufiBvYEJd1jUaMPI1BrAqIwstEC\nb+3KnYH5kW95O6AHVUyTDKdLwgFqaPUtWQOEMLYcs4YO9TjTf+lOf8Ri8tKeS1FuIBo53JHO6hZP\nt24cU+CxcvXsFOIRFrO6c8J0qxNL+zfKYl3QlXcFEdSslT7T8UnZ0nEKvTdWeMpDJfZHmNhn1D6u\nuwxJ0HQRzTmdTbNtqYupXYoJRr/2qO6KCNu37OXE/hLr0I8Gw3j9Uwy/dKCTqbZFJ4q4yy/XboUV\n4TRgoJzAWka0imX6Y1Aa4KcnbA1CrIwyBKh6lSsJ2a/wt+V7zkctm9GxZoi5f4zEiG/uC4v/n/mP\ns+MAnouXnKqXAOd9kiPKqayh18VWwm9vED4Zmn6pb+XKVoiGt+oVdl9QzuCL3SaO/DU1vPmmsFdP\nDtC0tYMBVXeE2/O+KOzoqqXTtavTDiPS4hCFrONMVOjI29J9M2s8d4YhnIRBPwLLLtUIlOHFmjDJ\ns3IHqNoTcc007iQuJrceerrRECk7PHTDN9sd6QDs9wqtm9k1vXOFShaQtuNttY6F5VATaZxj6Wwo\nYbr5Sr8gWBcKYCA5qJkZeNJtsSiBWdhWXwbFu/ozbuTozB0hgvIFZ/F0gk665ID4nTDYorFpGuVb\nbsT46sWBZgFyT5MRPBv6EwD3NXKM6FkzIy+LneULKYk4wxqBoqc+07fmQ1kmEx4tikXnpU2rBJ9e\nHglCFTDB+siyDG27s64wbKxXJuKILFb6YqyRqxqHOSGEOFN9uRwm7LzGjCHIL0PA9RLI5jGa6JFi\nKrhf6WFPD4Ar7f9sIv7HBS7Xx5fnk67vpbO929bqYwGYVLx+Ytk8e0rZTxd+kqoX4IQQoedrJndD\n1uYXSxxk9vTh3KDNyGfaLnPZNuos/0z6KqNXYNKh3Bfv34YY5gwgF77FNXWpD5PSTNMSzp0zR2Rl\n2+vV0cgGKLZXDVVI0hVNImkunrCfylKogj9zKmsgvLjRe0Lwhi8GUO+47MvOlH5Id0Jd2Falsrb7\nWMvWzE5KJNragmQ2tcmCqWCyzFODN4wZMJxbb2ezNtQNEDkYfMdsheRwtkNjS4jlj8lJ79LKggXz\nwxMl5XXnQITc79WJyMuVk8GQkD9xFJnoGeRXBIWhCz2cM4UWnoAUxS0P9fSdJeJOrpsrMo0GBG9k\nvmkyq9mnNaeIHrugdXmhHe4sMDYpQYjts73gxw6Uro+NHl+Acn69A8AxYSF154sMAkjZxtBhNb+Y\nx37sDMI1tUENHFRiR5GSJrIk/6lWQSC+3CE8YBk1mKZ5tlAhveHxuf4zCDV7l39YXt3xrJSmhw93\ntb14cuzsQdkMAEIfJCaUi01oAr5QAexhYA0wnqZajXo5EgnbVm5QwCK8+4FoHqGcj/B2ex25eHet\nBOcdPnZEktlU1gBZt7OnL1ifd2hIJIHRx2dYg89wGROyMgZIK7XMLjjhXRzuxp1G+IMGoRzqXx2o\nVmzshX1xeg6GX/hipB3eLG9eThC+ACnTtRnlIb9AN1pRJdYz1yYOkMvFIMs9aWboGKio9w7y2AAm\nNqBLljOn1tRox/zFuqkAbGWEb7wjoPN2LK+5HffKvH5N6CZqegXWUFRW8c7FAdZ7A1eiA2r5AxC8\nGPUCLNuRwOxcc6vPOwjyMmj86jzrCvt8YaUFAweqTYROHE7UjJB1fwAw9XwBMIkJG1wEj3Conha6\ndTLue7r6Zs9PGzbV4onyUoG59n9oep6xdwT1Wlt5oDGBqzx6qK3YxEx/qfxaz0toxyNfzbiDAd5u\nfqxG9mA3Qg8r1brF50etdB8AQfnG9fY5zv5oRB0iw1/ByWLnhj+A2LacuYRyvY0WQT8xB71Z5c4d\nnIfU1C6sNX9hnVlbH9WEKFuna9DMXuiFBZNDAMZFTK03tZ+NchWP39DKMyhMPFmZwYhygf8Gsc+e\nygEUrUjQHR1bW3iyqU1nz5j6T8ZkvM9jl8T5O7t+ZGgwCVYFxL3eQ1u0ep5112LpLX8gvNCrnDG7\nSaqEJQfYxruURw/idNqFMA28bFcueltKeyn/Xgs44IrmY2JAhu2DBlR7hEZd9WPl2JSzOV3Zs7vD\nHmGoAfEpB5uWqonM3PHyiW18cbeMlRiFAb6IJ1L9EPQ20cBUgGAmWsRUT4EtrT++FX4E8fZrJ6Dx\nNgy1orxr0GMbFhig+AV7wrGocWW+E/GLcVZKvUd3g/lWJaAMcnDBcTDoLWDaIkeDNPyDgMNny0dw\nHMVAXYAOfi/9aai3xj/a7F6xm2aerj3GeLoe6DG2LW7R4N+6iNnjBHlyhPqfU3s1gYSl0afTDeiH\niS71x4UUoeewsSzuNhNucHd+Z0KykJZAUxzEo3DtbawEzDgPXZt5EQ+6sKwMCGeZ5GX8r2cWsIX8\neATTEi0thNqgjHax5wjf5MTs1tKFUYe0JlToiw25gmX1Uf7CjfJBczEjpoXeWZCGJhpDynRBKniG\n2X5PT0VJVfwOdpzJgRbOUcx/v8KyieJU7fR3s0wo0RqZYQLWEcxZzxoUvPmz+F+RrwkLFrAEYd+t\n/2Mb+Oer9LYnObWQP7M4lYAMdG0IjGwNpVjOciAB1PqQkqQfcOFi4veAju0C7TtamKMFduJxQmiP\nla6vBSHeBIMPgBr8Xny0vSdHW8nYN8qUPOWj/h9xUBIda2BGrWvBGzicVgeDMwNlG4GJyXuHOj4B\n/qaC8Kt0afcPO+yy1v95WjiKcTl7LyZyRdxkqnem1YvMJHZkU0ojKeeR+UYWI4iRyksFKoVqsr5L\ncO5XfZsEI/3beFwdV4hnfYSNcbT9au2cL1fQxsVql6/X3o1pLv8hEj4J2lx+O8FKdX+ZsgCwV07e\ngXzosqw7DqxmyPDEciZZ6qk/d0moVQr/QZT9aDITk+l2b+WItq9ZeoF3Fpmo/cS99dX42+DF9f09\naOK8lXiSOuJMGraIHvhAMbw4hdlXdpBzaOL1lp3yzUyIWS8hVARTgHF3QSe51BwZY+N55QD9Wd4F\nmvAMo2GXTB94NtaaSUMVWpFv81RY2TMT1Cxh6AXt52nA5RzK9YLU/DmN/bqrGRTX1mZxJHPrMjLl\nk1S2Vldi0JmcL96xik9zz8NM9+1yt1FP6782CXcOYlvQcsNSsygT3TJD8Q9wLxSQAM/YJQ9v1qH0\nhsiDdmcrp15QPXmN7BEnWEJYbkEe5MhDdu1yOv5P1KncTWNBa3dZuK6DJJVvkymsppZza3UzGJzF\n0yyTN3fJ+jeH7HU5UbdH1th45ullkWvvpF3f1NrRMcaijpQUJoN+cPAsVBhK87+iqko5d0AXkpTc\nkTeCmbYDtjHYv/hjlv8x0tMpRpMESUncjoqp6aAclXwepaTW0HGahkwlUCL3zE0Fs2BihhsvyfnW\nscwh6TdnM9dxIEU4rotLq10+ZMhN6wpm0Cf3Fd2tRp4EH26x3SfSvuq5+1jBU0/LioQb+7uJNnqs\n21n3uFBiek3zW0uRZLLW3ncQjOd9RE08BgSWJDkjim6ClKqCZQ016ol97rQ1GDzupj5cfp8ySDhJ\nG7aWYcpzxaphd4TShpLyBUnz0e7IE8RVHpk3SEIk4AvDTrlRwfamqR7KpdW2i9G5fQT/hLeHcZkZ\nVgG6AjYcUBwYlQfxEuiL/j/59luO2NdIygvbqtbBnoTHvBQf8CNR9woKKIKNblzNRtJoMVKch1Bv\nGPapsz0pinSuPeVtqefBqj5lKkB0otfeLDgzjFL5rue+MOsK/prUjJo6nKRtXBEhw9G2M4buVyJZ\n0bccZw4Ixq//1hh6gTvLi4cK1z9ZsDRe2SAXozmyoSQU60zrhPMe4b+ZEeg5nb8MJLHijsTX2TlP\n+rrDTotSTfxqJkUndqid/HyTC6ch5Z7I2QSz4qPu5V5UYFc4lG3NQN7j8NglcnZz85wWtwoo2SYw\njaWIx5Vrclriu0fm+tDFgj92u/d5A6wrygm65SHgLaUl1MuQlZzAF10oqMUy3utSwm3aaQzNkjur\ncB9yiE1ikkYy951pQw257bQ5sJy5V1DO7r9lKZWL9x1QIO7gMC77dvTc14mKc6MkdnDUFrXp8P8L\nz4ldtCzkRVd3kREGCI76Mx6pSxWyK5SyeVGpm1j94iBnO4EZwzg1xMecH7iKR8ZgRSZ+nI3oFcji\nC0SIz8/HN15w6+M1jrReVkbaao6KDPlRKnrJ+1Q/kBwUPuDRXkfUMFX7AVtE36NX8zujyfDGIRHp\niFCdffbhrQ0dl8sqC7GU+dwRQy9LfJ3AfLCQkfsjzYd8De6oRxwKN4PuY/hkyl+2AeMLDc4453Lw\npnTNap8fQSFwjmSUZAroNdZSFYYaDuGAz37LKeJ/sUi9ZXC9bJglPWjMsxU9t4i+tmSIcCmH1rZ1\nzng+W2p/jKFf+EdbTgw2+TjlmAT+OzxwEnxKuUfi37iyLD9rVip2kRyVW9bO3D6BgzIRjMRO3OZI\nSJaTek10EItMqPQQyodBCmAcxqOoYoj7PMbTLu4ps+tfpQeNj9b1z3+nhSpRbOBMk+rNTF39DWqR\nf6yDIrN5AVvR1NWAtS6JfnQo2QOgexpmja9V2u+RvY2NUhmcGojsyj/1zpaeBT8D2fFoN3BugCOo\npauKzhW2QHzZjL7CFbU8E66YquFgx5n2qsEuGx6cjT607PyiL8toURB5QwQLtwTnizz/pKXvwKVe\nB5M1M6YQ3cUIJFHpMJX8Jhod29JrxIVmuhc6m1XTeNybW13uBPyYQbcSCn+EOEhQBuEkMP21c6An\nm3/HwPCVY3DS28HP0m27JclpLSvN52fbbkG5i9k24WeonV/HmEpjhn6DQllOqphcln45xgeBTdKJ\nOcNdCfVZr/2RfOiRqUQCmpTi5IVPBcGjDEq3S7c9ngvTxsgxaF4BrI3G8efkTAbfxzbmiT+5UjLv\n6wgZQ3TAn8cjNmLj2dTa2xaYQkExL6wb6Kl9+rbtJeb11MNHEWjqmPrgGiUmTzDA40mxuQuzSkRJ\nn8+X2kjWJb/gPPRBqXql8Cax87b8JXBqtQsO6RpbeLd+Uo92RLyf8LXD4Bi6/krZTdvQeyJ9Y184\nOsD/4aaWz3gXNZjs0LxyR3ne85nePACCV7rvizP13tFBPZr+CGY+Z0H/ES5w1JvhCOBWxZBxXNmC\nZuiikmgtiB/rOSTP9Ux8z4EpysIcJHrhE4bnGuKi9k3sEEYE2L1leF1bXTpdhfC46gKucW9TObc2\nNcF/jdw7etIHps/XajOnxS2z2/+SagTRttiWFUurEIQHzsvbc6z/S7T0ddpY4dKwk8iFeGa1sB14\nP2+zo1yLia7FMxHfewfPMoyN+9vSb+BqmutR9nsoCFBRBFsCZq3SHSwC0hEpeFH1O1gkJFHptyqd\nHIg/tBtzDICTQSgUXElLpjM6MQf/90EJUiaPWp7XfR+ExG07tDsVEtc/4IYVXBuhl3+qZRYI73JT\nwGiylULoE2kVOwMn8gXDAbzgsBAVtbOXZ5lQuvuC8yba41JsO+w8oaDS0lpVKNaQ0QELoFsMynKc\n08TGrelrnNC4BRM0IMvaJkT3NDqmRER/VjiIT6H7u34z2WBvo4y4ggyMrikYH6Ib18sF3Sf9C3oZ\n6ecmNcWKlWo3+ldox2OueRalExvXwgqgCjnQb20hy71WUbaNxHBVcJ8uLDvfb7mdgBIFJ1b7goYI\nc23Kc+QMDTzMCGSFiwdGSPnllcCk0bUWzK+/sltM5USRnDtuS22kOprp3Dg9TSDszp+kcoS1hSTx\nPI1Cjw5jL9CYTYgzWQ3WdpTOFw3WFL9nJSUeG09fk4uKaiwdM7IhUGMkl8w366Lpi6zxiFuPuHoR\nLQuCbkMIQ9t/mewqvfwE+/nQ4CEIE3dG6RK62QxhBYIl4hsIGnu83jYRUN3HZWzlW9LBkzT6Tr98\n41bE715JwI0922t1kg/HkZt7d3uEVKfbEozhf9o2f/x+oWo0ePjicm0mkIKCNdQAC5ctGH8HPTzm\nZJ6/SGLiz8C28+2yMVJ6+VF4YAJBVX9J0NspMNZq9M4xVKmFiBNE9ns5/pj2MKtK36bSbDTyDwdV\nAVgm8Bl2d793jjCxhPLvdkPiQ0tz+imMMPMZo7nXohhhpBvz4EoPquKUsjV0d3PZ5rIg5FIP7jy4\nqZBeaJb5qBL/qhc9C/oJfGCi1Kh0nKMtX42dSh2AdKlxMv/NKBMjRhQnZ8i5DGGSdXc15L7ntASU\nh79muv0uFccDAq9ILx0sH3mfz/dp9IRyF93a0kFI2Kbj836S/jgst1tzUrqHsvFoQGMfI8vusydf\nXXodQ3EFIiH9njloxYlCxt8zjjSuTra0WI9c4gdZQA0aSLFKbH94Y+EILQEZ5YtfzSyHpB7AO4ik\nGtNbTGkpNmhNH2ponuRlWqbpBcx7kx7N6fCG83NIb/e3ALPE7knJ1oUbD/x4PZlywIE3sLPav0co\n65eRk6TlA870wygUJhFUBS+9xh9M9k5KuCWbVMQ84yRefkFvcgTak29Fb0mrFYfxsQOt6XQuZwcZ\nlsI3KZJ2w6L4gWTBoBFpQLtm83tDQ79vRBvPgbDW7f0qtENhFtSDqEGwYY9KjNV0Ut/ZncS9nDk2\nyT28iyTnZgb48OP5vr435Q37zFfyaQ4zqaeJmEV6+SWYDcxg7GxlujdguAxUjw9qRhmPwwPYZaz2\nfAg4NnHjw4aTzzkm4TJyGMXtQNbO9wKwy5tvOw7BFgqCF7Ui2qoQvN51m3mQaIRO/MW5almgWdp6\nATYs79Iz2SRglBkv+5lANYAROHO6pZCA1kmm+eEbnDI2EfyNY1kDSsTG25Xao1hBux5FND9RejSP\nPMr9erV/SGss85V9a3excPMg36tDjYUR9kWGIWfqrFLFjEmIiRU0uiEBXdwVCsx/fHV2RkhY/dnN\nf+Y683hJWBECjsK5LEDm+icoWK8nBPscR1yHWS6uMqaWU6PXzi81xvs904ZWXxRjgPZwoZ52aFHQ\nNf4bRD+AdxQnHRXjB5Zh/5pXOGy1VFnS4WR77LhkX2pyH/iAlBLluSdZ7aTEyQH8AdSSlshcF1sa\n1WvhDKWqpuM6/CnOfvLV9He+hXwQmvjOqRTkbj1x3g5f9ORTBp7oUGqwfxQL1cG+IyG7GhJjq/59\nC81X94vghRXNpfHLWWimRvMGLtcmJjukcUjrOTH1Cwt8snVi6ltOw7L76K0fUWwky0y3pdWJTiRB\n1g581aD8K2hgo7wVHVJH/9l/laS5mVeoZd7WAux6k0WqOO6XSCpg7cPicpoSRBLML0hovJurIraC\nhQO4QLw3vZOfE6lvBjPAU34jzGcg6rY0uzAF9nrTzwBeKecc6lmZ0ll9ROjxbd/rZzUcOVIj1Gm0\n/N5s4CNmrU9hPvdPxtcFk4XCKmyx+0Sgqi+ngC+/MEq4qQn9yPQHpIJC5cJ3zh2XP9PAtwFccaAr\nV+j3OVSBSFyqPhAjjP/jeBQiEDYu9sD8izblBjiu4JRGFWtyf+Hbhs4gm+umzYZ5fIsCMTwTOQ17\nW21H6fU6s0IyoTTx9y5D6RilW8bayei15i/SMNintI8O2o05D/XajK35XX6LRuT1rMFpbcDEO7Ut\nR/QZJW6fuz3FPGiH9McsWfTKogd3qitWk+Qq/IsI/saWvGi8gag+tP2+hXJQ6MJaV2+rh5xmcL8L\n8g53LZJn5i2z6u5XArbKOmwcxPqDRJGZN3qTIlHp7T2mGR/TSYDR6WfdsDc5IiW44Wyb7ThfTGzX\n/jsbjlzjDJJ+Geo822SPOQhEoi1+3kjtgfJY/ZigqMhalZSUBzEtz8fV+Z30+DwuDBys7WNw7B3I\neBMoOIispzecLuiOm1BkEzNbqRdr/lVI97M66xR801CUnKAs4f4oZLxXav0CERRn70UHDYQ30JNC\n9e1BpOqQK2G7NBHE7ljLYFBs/sihes2ccKVJaI9rYeET4p6aSEing8faZsD/9R4thw1uBfg6VaI8\nvwzoC5fTaI3ktXakrHzEFkwpMZ6hhmt2/jjFoXz+aCTS8CinhQwaNojYPchWOf707fmmsrKp9FFg\nW4AAtERdWQ0ERNM2vVKBkCbBYigATR9Pj9UZZ15Am3WXRbaqwJWaWrUQ0ixU88o9jaDcOuh/ZNGb\nSWtbJMoP+URFkMtc81H/3PN21vKIGtiY7ZZjek3IZiS6ID0tiWBzm1b0f+t/os6RWOqm+eTXTseA\nKhsWRrsKEQoCKtatjrkXnNBzezqWHw/qrFbsQYeBdaw2/R5qdjtQgwOyLZ8uOeQkC3LP0QGf7lgn\nsERBiiTsL7gGpFt43RbePVRLvBDMx5KtqF3F1hmOefEcToJA6/XqVxpOA3+/qDr6dvFBdd25SWTK\nHHDxtLnWIxAFE70VhD5O/Ry3SUSmRrRJnBY433VD/RUXgCDOqvBupBVjRfMJ3gQ3AAf4OZYOJA/u\nN4QOIK6cw+hqkWB6BWMyj7Vsu8lYiBzngBfHifwJbYgLFefcJuci9R2KmpG0leOYSg2+CIGO4tHZ\ndAdK2RRbYRgEisa5Xhru7NtDHxpLdUJ5GKXcMY49QlkXnWfHjEnLNqh0d+LCcaHuthcHIBiqRRdw\nFqQ+ebuUiKwPpefUuhwCQHqUROCFmaEeEwByxG7s3e1ScdpTvnaRLytqo5obmiSf3E8MrP9JsZbK\nVJTo7CWQC0Sc4olb2DN4kP5rZ0KWNcF1t//J569OXmjZUCPULnrjJCR+Lj/Ij+By7olGN726Aqks\nfMwFHhuY6LSz65rtkijpmvR38vFfJB87V+UPkwK5w6Rz0vjGRh7DlWUsHbGI3ZkXYRj9Sea14BFd\nJhmuxdfW11BN6dy3BX8fWB3s8UGVB0qgoN5eQ5r6b5IEF96USSoLyEwBsBFiWeWbBFwoMcp5v1PO\n5H6+izgpoTsXGGbHQvIuIrg9Xd9NtKK2puyDrh2BqKdlXtZ6EFhWwa6gaKX1gdYp8BPFrMDEXqjG\nyRMetG0Y6HPqAdRAkpoqIa4KuIXHLkdVUxZEpsf0Gf6qg7o4QmeLsUDQ1uBX1tW/6pfzESsvhWmP\n5NQfGcHAiRBSSYCRaEHteREpgNrtdotlNK8RAItPGnF5q+Yy9xW8NE4+csv6DibNykkpFqyCkfa2\nSzHq3rwgOvI3ArZLnTlrcYQgsNmA7gPfn/1/SQGz1lBXhWCdW5oOH4ycrjcZAT2syal9bx9Styj8\nn2MwTtXp3EZPlFW+zLh1mu+00RvIE4aLHq/dxFMrqs+h0ycB32D07gZtD+llmteK4kqjmxJ1PVnX\nFPGwcfLCaHhUv3W/NlM9+qElVMxs4h5e/2/hJoUu583IaQRPI8MSJlW7jXCVA7U5sqVpLcC+9mz8\nt5EbGJhAEjZDLPVL8GXAlGUwGmF2RuqjS/PjsDLbiQVxnejtF3VCk5eulc9lFSRuXaZissViKl9t\nXQ5gck8z25ONgcYR4NrzG+8qo8S6isSeYGL4i6dlOtMh2DQiAz4nmHz8/9NnI+NdfeQ7pqAv2NRX\ns/em+3qKonJ75sVDIJ10bLrb7DRR7czSDdgRIv71H1BmNJWKJDyruDt8FqcZ1V9wfHuxG8pqnlvE\nclkG2kPoiYTD+ftr/Lqe61BiRgy3sqMsU1657aLbkgIVXzedBKtzeRxR9CLTI0Zngtu7mqCSB6id\nhkh5QtA585//gR8RT6aU56DpfNXbrKneVOFVpUbdjY0IOtkC5xYJz0Ql98rh5qCGZUGoVSrUcHz7\n2VdxFIodb1vs3Vin2ca08EvJL4sBoMqgYFvJYrhSKzyr9rNOmSAFsFoXMqEMp5E6jR4JwhPHx/pv\nGdClwnEBYu/NlUmArgSvD/y2MqDdCRo0KDunej4lnvooArUcmJX+xReoTsWsnkGcAkvgpadiYigT\nEyLv3+oaBx01BSkHfB/6uSsQtaXN5HnxpJ/QGJQRvKFv7M6gbfhgTiLkFZXITR/mjB1lQ26ZGL7p\ngFJAICfIoWxFPEUHssfY3EVK8HaU8JDesk/dVc4JMA1//s2u0jDe7x/QnbhMgJPN4EPuF+BPm5Dy\nyW0u2TTKowdftZ4fd7Fypaz3to2Z5trRLNtP8aTt7q58W9tI3uxyboINgigvDHADDb43h0HhubQ+\nOn3d1hdFZzApCgNve4g69flgqKJYcWnsYcIPVXbdCO2fUBxWSBLkIkLVsOJJ1HnfmU1S7S2TP1aQ\n4sDl1GSQzqoUen/zH9r5xu0MyTxcL2Hh7UO6o7VxVO1/ANqdfZWpmVGd/+wT0tB6DlRB/OKmYEFY\nJ03aDfWI2xrLVI13cdyM6K09Q/xZuMQpQeIZVgLpsioehJb4YGOyO+RJf9xP13mgsSn49j2Nbt/c\nr2wAR9vs3DCLLg2lHMbMfhHvETAMZMrOODta5jPDNJU5CdOUAZxopeqx26E8vKwmSg2lhtLO/FUl\nnSW55MaEV9HUUTN+2qcNTXU9p2K2P1LSFuu+qP6tj7qeAV3dKdZPYKY83fihO2YLMrCOtaHOFAqa\nECRoxM5Lvvf3IO2m2HRCB/KImtCITWyIVtCr+oAudBdpt9GEqJ4PQRP5IapDUDlb9DkgeOp27aP0\n7NhlNOgVz6bCc5eR+yh1/4WwoK35svMX+Ql3NlwwqxLkyDUVW7FaLUkXCnoewziy+r5PtCR5FnRC\nXxpSbFlpu0NyZMPItY/sMLf0MgIyfG9eEGtcXKdSsj8GTtNxR5CcR9yGOImzRVNYptFoH03XWM5b\nnG0C3kIl8XNarP5yQ5O712wNbo1mUO9yvzabvEA5ZBSBydKNp1iQ+QWrqbW/g2BBG5vHVnoJeHsQ\n41EvxCexRAcCTx4jpmGIjek8y1MCIZqalrqaZu/9Px3VAsedQcFQ2h9ebEdpxMCeHRSk3xRmtwpy\nARGvR3dTattSQqaHKtoAp0sxHPnbLexwDsowajUlruUFGLAUAa+HuUMOzeF+/FzjQxjhScBXx22A\nLZPNmBnfjH8RTP4rUzI4vftPXfi7mhI8hHnTfC0y6fDSmPQaaqfpD/zFs/l+Db3lIuRX5xYHkKBN\n24oItfaS9SwXwI84FI2DEhBdx2ePKStRdqs53JYTn2RfsAGmjHw7sn//5lXqrhxTxbAlfLs4EEoM\neawCCfOVTeO4RfwoXyLXuABzvAoMyf9n++WRUSxhZva114+rvNCM4/bE4+Fhiy7IazfBaUkeHX9n\n8p9afp0XbXnWD7GiJI2XxJi+35IDzkLUZ7rAWWiOFqwW5RMo173brtPZxOPhWjPdhCE2dNnYTOuj\nlgg++wPqIE2ShluqgAvkasaKCSCyQhzN4Tkqzfx4rXqZQTiFnrp4vTIjz9OeFV58XPEdBj5PbXSi\nN2pvuz5anTe92IGnk4J0ioZKlBhgR/rwhMlxG6CFjtVXkAVHbVVjjMQzlT5KVZvO6rRqjxmdL9uw\n9ViRGqfpqQOn4SXiU2YO3GgKHet5nGBKj2qnW/NSZ3Qbh70PIoH3mXsHnJYRav/dvqc9am4qPNS7\n+bdID+vVMLTIp0JTJS1k9Dsrl8Kij7CVuHD2JBNGT23/w1QhFKZpYS1tdgvDaA3R5+Q3ohjrtPYZ\nBr0RVttXbxwFe7ovaoBp8EyJw9246NrW8ZoH14E+QJy4Xp+kU/0fydU8gSvEJ/NXS4E8RckTQO0r\niPIEVGoG0hgGWkTpJH1BPGu/iLrgov/c8Bn41Qa7R2iaO1f6q58xObfar65yuAugHWPh2lGx5lF+\neckeWx1ShgtINqEXtBtcwTW8HHjps9XVRXRqMEdoozpH9doJlDsquIne791xPqjQcInAVGIho4A0\nQjQ7q16ez/Htb01v+lLOh9ZYkeGd1HniGlwt9tjzASydzdIpTMlxmBwbOScemeP+gEuJJYLqfJNa\ndJY/1n94r764C0TrwERWtEfH2jhqkxGeB7jHaJHRrkwUOK7JRrdjLHRaTBRnP9z3FzxYKR0zkvbc\nCGgmk8QjsvWSlh8SuLVSfKdgDo7lDAmj0AmlI8JvynA/LckBug+oK7tZb2Zjkkk9mB8kw00dxw55\nlKj4l5TTpWcB7y1WyxIpYHmSvWUtLYVd0tHSZsU70u3XuHfODe+iVFsSpd86rx3qtpTLnnykLFYC\nczPuua3rbi44Zy9GcHuTe3hHBE7BKdt6iBP2372lu3g5+r97xd2Bra5Bo7vLH4MzrksADi6Qpayw\nOEJjtvxhPPI1kl7snXAjkWii+nmHacgBp+BFyoOzFG9B7TagCUwJPcam5wVYG1brsuHf3puXq+Br\nmvMkGuiH24Nfa25fxw5Bsrm+h34l4t9+hGd0ZZUa0kX9SJ4JOcGX2yhA0BRUfEfoEz1MyRpzOqDw\nSN29BQudhlL3YLJRpVFzhMuUxs7nDoDiRawduOsv5ooDlq7QIOPmUHoSkCsU+QeSm+tIQ5MXoSqw\n0exc/+p5yPnHFaZuB0od1KYTXQiDDc1VTwstDJiigP/7CGBlVB4uBUdyRBMZi6IQD7Jk5Dv7YSBQ\nBZTjxgUW9nGc0YxhlHw3z04h39U3Hd6SaX7GBAsU1t1HXNAppGu2pnfJHPgz4FiLH0vYlg+xI0C2\nW5l63YTsShnHrBdXJ7O2FyBeHUN0XeibF9DjmDsJSd3UInPgvFsmfmWpAF6pbmuS84dhGpddtaMr\n6TcCioZ3j9lBwU3/WDBlCdVPHGPKZKIUAvh+h8J/1jUQCg8MEyKis8D0a9cT0KZgdcpZHbkso7Y3\nOa0XugZyCVVqoy6yEL2IqPbh1ErJlWxmleQczbkbTd6nJt6q4SB77CkswO+BVUfbgu9w1I5M1Yj6\nEeh9qpeFUc3TG/N1Jt3iYfhYMfipE7PtFT2PDPGC76/C5k84NNqPg2bQEIfJk9Ieao3nZqQCqTK2\nQntHycWU9qwgN1fpw2chsHEMLsyjU8G6iXU5U864IgtsBrtw55wQoxiEssod7Mx9lOB2pYXVO8EW\n3rgBaN5Xgv4X/GSen1IEXCXu6tTy/8ChpiLEy4rUVydO2KMHXh7rcuAY1lBWaauubFlpyPaJYuNz\nHTCVo850svMqhCA/knoG51+EUscHBBKa0S6lfk2ePwDUfWChNOoeiZLTbma68Jo+KclswR3e8K+D\nvADfanXefBbX2+MEZeIZjszH0GTwyp23PmRMvjYqbCaZvkmtR7XIbUfkIdcQnq/1Is1YDt72HPgW\nZi9mA2XG9lcr7943C2h7vIDN8djKfLtP/XP3wSGSy7xAjD0YLnFVSK1buGa4NxEyi+vbLR0Jcdbm\nSLaBdUY4PcXZf/pTnOuE0aFttQuAbIYvu6D/KRPSsY6XACHS14Qok9ZU49y3y4VaZxGLk46v0m4m\nMwyIX4uAK/NlxU0WTXuyUYvCGzTOZAykxP5bTnkCMEbuL9xBDPXn9ow4yrRspglFd8hQwIYvRkOt\nxjX2IWNhbcuZvHBGuU+iuvKyeAGr5EHqj860jKDGdfUJ9cO7narYsRTRYqQ4ZD3R2CsM9sHrbLFt\nxHvnyA4iVMFwEu9uJrui15DyMiKPtLEu0E/Xy9Ef2nmAofkhUwPN5BW4PXDzOPFezlUZshmjb98h\nhT7gdW8VIcTFdqoUCgCzYhoUHk6fZsGjznefhlOYvzfihDGyKhbIePaud4gv3Hs2Slvmcu1vbDWl\nnNmqetUKwf0UE1NcBfNhlLS72uqDxi7iOPQH4jhF2G4e1dJfMbb8dW88M8tFdKGmfD2PZrtDWN91\nh1XXOh+iy0c9LB42/died2mWubSdT6FfAtMoVIjU+UzyIUd70oePSvO1pLKtdQf/wsnVSJz7P9gt\nAZitPXf7DdooE1g8XnACeQu/vtgSjs+Zug6b/jxsH+kQK/ts5KAzrDKNS60RqFZZQ5sXYMROK+3d\nuJvoxl3f2FtEOOa4mMw0NPbabnyxx7bhUCL/rodGFohYVjt09fTL1StTGPAy5IDQTz6L2Gh6Xa4B\nrcfagh7Cm+xVDWR7udxxMDcovPSD7djdqUa65haf3kou5CEa2SMnAHWjUbwHI8lBoIOb9ZnpYhR3\nFcJrOWqFj4lvz7lLZK0Y/wNEJKg527n8rfw16R3e3RigUEWHeCtQ+SIl0PQAfwCESxyhgk4aCrmS\nfK4fQGgIoQAHkQnOScef0NxOl0imZZmpaqxoI37lhbyTYYlF2O5FDmRHXBNUYQPLmFaX7F/i7VTz\nHr192oELo4zZGktWun4sKH4BUtddqEKfhXT4LE/KlFQLM2kJNheDdQ9IGOrLg2B7BSnoSGIUWKWV\nzPp2ijDtq0A6UVZdqFwnA2msxtHQEVqFaHtividlhrHBcBiCRZ+gCDqbRdTJ8dajqF3HHLB3iZhO\nSVuLJYzEPnlxVr4jEQo20VesCtJxmXSCIhv6R3CNvE4xdtRfx3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protect end_protected\n", "num_lines": 5018}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\ngazeSTBrENHvbt5mZLx18dRtoyW+Km4t51uVxxH7ZGNnmTTcoKqZyFpOrZ3w8kS9aFoiQlh5unYf\nVMD36zgB+w==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nJaIcYFxN5pqUbzepnqrpmFHdFIYWDYoimv/QCWvvIMmet78lyyCu7OmAbUWaZA7w0zL3MGnfxCUN\nn3vQGmg/2D1qvx/q2zy23sfhZfE87aSbXcNL67XF+GYu6OLKGGPH8rnW6exQAoemSF54SZgfsVR+\nZQSjSgAEtaKfNJS48WA=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nfa+581mCG4lxTJxvsYAMI+Y0/3DEJVi5IASCLU/HkCRmXkai01uuifj6HPVqiueReLeiWI0bzNp5\nJVlbpO/kKqg9MkQMgg1uBw2FFsg7gfVjpDJV9TVBp9Tm4YsSrWm6yWxzb6uMaHsxRa5Y+E4WUKp7\nkFXmUM1qfaMPGyGNdQg20KAvKFwwN0302/mi6GDcLvLNvvne93tcew0yQIxg/gqJlcURIlak/g5o\ntVj030iWkuj/kKp5guYfq3gEFKVEr4SV1BC/f5KX961SkhTxXGKLNLPd//Gm7akdx9a4SnpGY1Jj\ndKETnZJbnXtrvqcZUh2N1o7nl+YTs0mjObgM4A==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nQPlIuDrSSApp/O5dvtKOql3r2+lVEipJtAA3M9T5a18Cd2E2LeOe6u54LQRqvqSgFUElg4Mk3hH/\nGPHlO6wLGkc68a2QHrQWBA8YylrYUj+OZbum9kUQm5R3TPU5Wchw/mhpqWpgPlWvyK/cO9FxrB5n\nHD5ZuDk7iJeShjEmKewIRdMZqkkvQahMZk1eJ8aT2jahULqIomSMODM8v16Cxv6S3q0ohUtT2DVH\nwOkY6nsqo58T1MDDOffgorFUWVqkQwGQ/maDu/KENCo/JCJZOAmODbmBfBAsXvg7bqGZKB9VPp6h\nTMfEboGK0PjL8yhECxqeqwtqHk+eixHOqSANVQ==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nb4dHNcYwRRv3ODYilIe7aZan8VP5sGFpEcM4Sk9B84EsHlTRadyHodV0BfhfsPQB7kezG88HW5h6\nWNkuMny+KpZj54uRmnCQmrVIyZTZC+1+fpR1i46q7pc1ZFH0ByfdNqY/66Ew72bJ3bqt98VUJ+b1\nKDNSnYmqrLKj6TtcYAc=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUFVtDvwzUgfeTJK5RQPCu5bEQXOVNdg/Ctt3LMq1WwNKEczcihJ2sl86P3NdRo0ERI8ueQtux6aa\neHgbxrha+qncx9ha9CjfRUqPzzsOn3Y7i1ixq84ynt9jVyhbj9UUv8UyPbi4K5iayWqESAXrtTyL\n4izB0qPIWl4//8zsVriy5QoAxHYuCOVTFT74KhP0GfBhGq8gl2pE4gyETTs/8CEabnJ3ERkaoy22\nqOEPUjVTsxS8vgRq8tS716SKeECQKpsy4XCSTfx1d1knluz73QztnOOUXoIisTy9nHoSAbC1cRDx\n3ja7kCl2MkDQsfmBWkq0ozzVuY4qo/oIb33DVw==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nYC06/kx9685ntAX7i3acgvLk/EwgC2VW4WVhE+P9S0QST/y6VSJ0oBWMmzsdOs5O1+nblcA3DkpX\niLfXgmvlzh61Du6yn0zIyDDTLrMYWINvRbXV5FG9pLM3G/U+6fTbBV97iUYMHPWk0A2DdkXIWMP3\nmcLuMBQc2y0dm038tnqa7fuMeTcvxPhQ4wTWwHXvp54ejwq4bTAhNgyJeExmEzOvR+zWXm2VgpLp\nqcMFWAA6nlUIG5ZF4M15/u9UyutQPOLlX5+QPwfoMVi/kyC+JK5AUrviJ1QU+rzwvU3tw3rXqAgE\nsMTi8fHZ/Nt42HIXty0cXb5zEQDuP6pPBNW6XA==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nHg7KeQWoQfRjpmFIAWAFbtestpXMcHBDYTZuLUSbL+kKuRGBZWT+FXknqinVcx0pJ+q5acUTBtyX\n7dcJkS4qdpYpoaBETZeL/wcOfYFz/CcO2z0+LWoGRDW3DzXn1oRWWZyJwgJkigyMIHPH5qxsjDO6\nJPKj81fkKJMHi/vC0LbmZMiKSmWL7sQNeQyH9Dn6VLxtXovGL9yVh0SoMlG0/v81wA1TX/bXmqKJ\neUvzBU070O5AHkn3Z9WRSK5S2L7x/k+ltWDFho5jtXYcevcbA/14blQqT6/9PetAyFmzvbIS+6Sy\ncJ54zu+VswtKtSOWyzlOnfx1Jgt9q/yLpCG10A==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nn/U5obQaKe7e57D8Mwxo0WeDlQ4fxz4sWCrMViskbh2tk4bDpeUf1ENBUputMkID5xX5gqlPeFYH\n/lod/5hBiFEecXymoK17ADl/jmNo1MjfVQ/nqN6xaJWL8VqmPoJ2XUvVt/nh5gTeI6QOH0BkigMy\npLFieK53VJ/5XRJXmLUeyAKMuQYF3FZPQdvCn1NDG/xTrxv61UqQKbL35Q6DuG8ZqHIJKSJFVln1\nchCHgEOHDKo7nJ9MCjYRgwBWPGvr+w4IgHNPDhatfWTGz3wjSXmjYynT7/3ZWqR/d7FCLN+lZ/ht\nr87GH/juUmy47PmZd6QhKuuc19/j3eDrwcHg8g==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 25472)\n`pragma protect data_block\nrVD/wL4DHCsEfzFEf1VoQTKecFocJw604Tk0NgO7M3ODm6t/6/biD0QPzz/Fzy1UxKBEqQ8Nxpt0\nkd5dp5nyCwOVRYlAXNcBHWyWuF3ImZ0fp1y2c4napTVULuw+XU5nSbEmfo3EFsLjHWHYarc33XNE\neccwGpgfFccdUa90fp+q6imfJMIuCWHWowLNMDGdb8ZqNKZUIE8ob6W2adzfUxW6BcwKDMhYtONy\nphGaaPcir/7ub5AXgPuxZ+H/dTq9wgn1aTqOJAp1ucnPzVq3IUtg1OC2yU2vi0qMrGvEVqZa5al3\nShGeBdw/lrrv+XpB0FfkT2KARuuSvzee9a4oDMMvB9rD6SluK40ECZ1+yy9NV8VPy1Z2E7wjjpHJ\nomuIJmTDG6P4NMgl9qjKSn4GSHvEJtg8Hs/pMVAdAds6SMK+O9p7rBsB9TJ+Jfe+EKBicHLzhqUf\nYcNZCfyCtkGAWU7HcdbTu9BHbBM7GuhixBjPG1gZBzSE0WtB6MGt0YXj5LC9B2B4gUc+LuNxNcc9\nUKE7AQ6OnNorwxgTIT1j4f2lTdDpN7naMjcc0dFrzhwLEt7EYhpH25Cb1lTtbt3ny3KVcWNrvcLk\nv09yJ3wThnjJnQl+GUiERUgWu8ROGl8TiZbUBs5yecOS/BsLolr6ykQh3uUot6ZrpLggo7e2zZy4\n3svfbA7sVv+IfBOnba21zodL6jR5Io/8RZ9dAtTSxEkwNKn6woPbXr0vzkNOcXmNshPgXMNfn7kP\nhh71P3gVjrM1Z4XR2k5FHBKIFP7xvG46B9zLPPSpe9cKzJ4DSqgt0aNr031h/E4RKIrUZmmfW0JP\nOP5eFKLhkwM5x+n5EaEHSfUgoGX++y4UkfnBJWjFbVIWdkTMzBCFia7/hFiP4k87QX08uk84BfEf\nsgKGgULddxVYXIDV7mrWaO9Cy6yLEYGh6+7ZOBVM7Zy6cqp9LP7Kc0FPdoy8x9BVG6p/reTiiw1v\nNn3v32uEnt3XP6T+LoaKu/6mrF1npJimdRr7SstYkFy0LoyzKWhUHUz/VQ3iwILTJ0JnGP770FqV\nmvyHmvHBk6MZTTlNhtcVSTTwbM0lw0LvHbExAUCD9Laa09kQXtQstGMFqjckEvN2jqCALunjsEkp\nBQy8rtux02oSB0O2baktMwI571Rh+4HmnparL2+x49hG7tthybchylTgZbFDHKBCvdQBZkzVuo3Q\nj7Y3oKUrm2bmuJSbom1St7TbGFQq8d0b0kTXHL3I2ohjaio0dcvYDfVg+yWz93shEUO3Jy4PUuCC\nxhV2WTmsBi64HHIJgemiKEoZqO3e18N4F8cdUteag8hQdvF+6ZlNnZ/ms6TH575Di4UiksGkL0FR\n3sJm4AQ9V6tp6J/S+c+1flwE89qo+Xsg1/cG+L8vSsQxqyAk/ovRsYwYHiS7Yy4/606czKjJjQLN\n/Od4Z/RzSCDTe9OkRgKnHt5zK3yQjI9keM6uYHLPJND8bpBNdWrqOdAkXjDHjM3I9U6L2JJqeXVK\njIP4ArCrIq1ZHjpvCnFaxB+/+BBdYcUPUm1A5us5vUT7+x9nSm5EoMOVcMVFqrdJ27v3WAGi6+E4\nKO2C+XigT9fiGzmzXlKKtsTeS9pPq+XJ+3ohj5rZIoPhbrKxWjCzmpLqwAJ0gNd1WFfrHgE2LOe/\nH0ryLItmrp8oOSGEdzqkIi3IjIWzEJsFuNK57sg85CLkLBrD/2GAE829x/TXqmIJN9TXeNtV2gKP\nzoR4NFQendQZY0s22N8NsE4Y00GMNZhaQdHbxhimdXjmLk0d7qaq06rLRbHcsoP5Sq1QJlF2K1qR\nCGKoiuDSQoQ4Ys7EOeerLV2n/FRB2yqoN8xeHjway1HTDoAPAet9wYutlxLTBUccGt+zU65u6OaV\ns1H2YlNFqtwE716Dp39IzGvOD4w6IjA/vBYiXj/dOVHbBBfQr0u5i5m07Mu8+ql9fOGoJP2wqBln\neGByChXLhb4uLoe6Bht9vwf98nzSbRmiaYLyALBXHgZKs5L5Udkanozr2NM301M2pzP8QIPa2aQb\n64OnBA4icxCxWwz320VkF/K5BM1ObCLOipn/07v1naPYJx/9aT/ZVupp+QL9cBnPp8LZtldMFsxi\nZojdTH/u0pOw8jx+SH84VqjOEloFoTxTXkAMHKRulU7yj7ZmWlEviMhxT+f63SOqtMW6bd8ndq86\nbFiDcjGNkZC4YUerGzbOM6M+me6Qe5RcwL5VJARilQoyPMlPtvzSwMzUJQyUmabaCEispxMMZ3QX\ndNb4c+W7FDY4fxsytOmuPwhCZS3ytA1vCB92ukP2KVeOien0DKc4mIwjdBllzW9+QN+GNSzRe5LN\n/YyvlmAWUmlNSB8smtrpmB84JVKlWaXOOrpOLxRHtFaYpnmpmXJcNveKAB4LMvGTHJdEDlR6LZ5n\nCgWcU34eHvwxJ0N7D9kxlxL15EDsPFjxeT/vykJmOvcwVPmia0M2nwFaolKZW5cm0pZvf3bzkkBt\nkxFF4vDu3VKJBPN1qqR6ngJ8w5cII2VcSG+TZBxeAg/XH5mW1JuetQkNdLK940Rk85qvx9Z5tYFu\nFKrDM/P9zlRri+ggEpi73JzEUnuwXVzjIe4bn+BCJz+SYBKbr3OlasPo2GXinaCm5ZjGwKSqBbnw\nJNQvpJstSIPLThwNEK3IT7qyWtVrGoCDNiYO4H+x3es6P4VqLqh4r/0++vkRSTM4Ov8V4lO1aK+/\na/Wba1G4sbX+xCKKd66y0Rr3rr77pOo7IC0W9booS++rNRLvt64SbPyun/PqLmZi9rwotRAJRA4k\n7TXOcgtq4Ki6pKRKU7oKP5pQXRmGEVr/qGRqcX/IFcGkvR76WQxcFoASm0Yj/3Xu7bvEHJDX02tK\n4cAJxbC+4JkeI2Yc4e6V27wCtFNv8VAnJEAIJxM8w8Y+uK3Wdth00+HnMr/teyh9PAFI23BCDQ8k\nP3/TGEk+2X9AelM3jnJ1cx55xK7Y/PsWkiPKyUozhHYOyR4SaETBIxAtZ3ttpyHm7JPgipayDsI8\n7gYw9SePFZFjYEZhCtfrBAzTmKhxEJ4BYA2Yq5/1Djk3dqr1Y7XDyyIaLjVim9C05XBvKk/3JjmK\no/4wBHIRPWEui8ORGTOUvziQUj+FDTHjthpKosRq4PYd0gugZGbbhdlEj9IDDCDNxkVM9Xyk3ytf\nEqvvgLtYOih3D2Pq4LqFEqHahfAKS8ugstEsKmEWOeBnP50FSppoksT7QdPuZ9PWlAatvnkJv763\n5BXALS8jMNlPIJvelWHd2qCx6OhCgLmUmRPNd7LCMMydqv2c9uA7voFh6jp9JGAvPu53dzjWz83r\ncFeBSw11OeeiKRsJaiHddsq8L7nMEeMcZshhvcS5y26j+2tp1zr6sVBFicGgokYH1CKTQFIpiTib\nXPL5vAVDlvFDdaC5VNkFNCs76Bou5yWCTAwG2DcN88BLMV7QS7M/iGZSbCw8JV01LKDRqeheVsxP\njaLYS5XkKHDpYtsCzcVvCn6u+nDFLOLhz20cYL4vxwmt1pMKikYG15ONmScVDm5/xQBKe7nWsOKz\nSN1w6zj36KQ/C80gFY0GXtFZkG2CqAMt0M3uDfWx3VKuW6ObJNUb3R0TpZri4OwLbrrUpL5UT8yt\nITdov+Beft7qZpxoMu9KLHhncLx4TJH0gBzyTVfAPg4ljeaBsL7cmVfDmZ1PxNBQWN2/Ms5XhA42\nF3BDbS8YdOU8JUxHPgD9tCaXHqmt/co4uhm7Qtmm+DeDE3O6ljX5zbblXhS0345LHi4MFfhCkb81\nJ5XdY0hze86Ye/grd4KM1+hLV49/08mXyM5oQSWFRPGDY5ivO4n9anEwslLWZ2OKFvXtW0ZjW0tT\nRXEjOIOyE8jyr36AQDMI1LnOl15xPMnKxb/u3VpCatxnNlgTk/jzmFAD36PDOdzIPJr58KDGvKFS\nG18BSpcfrx+8cPWzVMM9M9Xk88D3Mxb+hWAv6UC/efp1x3+Hvihd9zDuubo8/FLjegZC0fa3een9\ndOTgEIsRfcfWWWdtQEDcPKuUn7WhoHt0SvpvO5dTcLaAmCPwcROmaH0teqy1XjMnZYp+sKIWZe7h\naa/hTWP68T4UHeFB8IDD9md4MZDlB/L2ac5XlcVY7UmN/GXG3pc7Gbc6uN0CzGUQcYa/v04G+11h\nT8nRzZQJdZlq0lH1U8k7gR7YudvLKtUfLHu1xmyJshSEKbRWUUdGRnwfJUm+3jGXNSoyoDu4eVa0\nmvh2E9+h8tpc6Hdxbe0/dRAb6sSYseeMuPA07z/+SsPa5oJMBS4zBtxgDX7xBkPmnOmMnJAKzWdI\n2/zXRzhP8OaEODsQLJm6++pIgkkHCqOGr6GeXrHTdMP3idL7UslwV4Lad1r2Y9+61kW7fcGSJ1KP\nG39vh0sAfFWWeb9d5TVQgwz+KIoe74xDJPYPPSkVl5kx3YFKk6vty4CYAB+5DVSd9bLaBnJ4/6l1\nJ76KqFbRsqIPDPWm7OcGTLW7JIMmU/Ofpv4nidkb4LPNVbPMfVS+Z32QG6FXVhOpIqgiKe8BfVka\nxk1jg5/fA0RQ/P5VlZhWUzEHywD2+khTh9xwSLldzJ30El7YZ++yRrsgkGW93hRzZdx/r1YMGGS/\nQBmRuRM3FKMkS0svshNKaNg8DySBg+q2X6Ky9IjA3dznU49GnthwMKhx58ThDxQ+szVA0MrLc0o9\n+rEmk+wXvMx1gpwkFLsJocOcBtoyq3atxI33E/X4g0N1mdf0f7XCxqKCPRyQfjfDQQv222kEzPfK\no/j6pJzL/bq2QCtQD62ViO655dAFs1zzuPSuwrN0eWO5sKLw4bi9ekjxE61AGmPACWDjdfaFWJ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dNrJi4eDjTX7egADR1lPi7IHJnaNzULLyzuO3tY20xdNoS1WZ9Cd6zJ3177q62zFD9IqW5Lu\nqwbBMBn9Srz8L15/PmeO818lgnRA+Obqkway5NlS5ktpFQ+pamj3jyYU+gi61IJh4yOrdmG+0YNr\nYFfUfUywA+Vb0DyVlm6VO+PiHnezjyvHEOcYEa8umdPJ9zJG7DIv0F2B2RqLChYKcamD2eAeDTbH\nfV0/YaWwv1GhQ+Ao8z4mbGlH71ah+UI4VMNU5k94werdUcmCZDFEnscd9SO86QRSF05j+ffi1CCi\nv+ySBxYK9APjuLQjNVrNKkjo3sgO/wtZFTimlVD9eKKZO3oJ+8ImII4d0IrCjHSBC0BNLtUvbme9\nmUJX8cvZmqs02dF+ATX/gcguP3DCUJDAUSvbg94oU5zILWF5KshRjRmpg3/63m3Mqua565kXaXW0\nqSB075zLeZeUTxd874xUJdwhzrCH1TkgjtNBULzc+e1zgGneUDlKpF7+GM3E4g2yPDntlKDSV4tq\nZg/J9yLjn1WZ+g3OXJp3EuqNpixt4tWc7g4zpFD+6PkEQHyikmzegOPhSHkmz2B78XcqHnVlVRT6\nu+h8+OajG4S+2zUQ2+y9ii2QR22KHBEnoriSV0FkkgCt9aEB2YKRRKtPBMXtQpeLYxm70Z3gLSUA\nW29k0A/vnaVEOuEOlY/jqfFKbKb1K4q9aVjX+++COWTPhV5kly9w8ujzb69MbaQWfX7p+PvJCGyF\nTwCS/7D3fUAjuzGmkdfDhZccW80v40olYz+LXAUl7tUuByKyy15G+0BKB5YEi6hGFv6lEz3GSGxe\n8/uUmYAPkJ1u1STOydIjaaYXqD83ZO/ZOVEKqhVutfVl2hSHLzYw6/gUFpFcMwZWXX5eOGNLl2/T\nFF4MzK6u9+0KXGdOAvATi0btUYD6QYMM1f5b1kBWZjJcC1//GBYKhkVUuwduwTVT6aj/2wzH5gz7\nQ8qEmTw4zYRBtJXQgOs/voolLCe3EfZEyqm2uQ/r1PchYuV1+d7io3uQFszexWSuf/eYepqWnq/v\nz2Gz7GegP8v46bRpzZKV61eoGO59seLhOTjvp7L/gdDO8xjlrHxYtOpMrNrj06dtbzUUacmPBceR\nd/N3VW3ovm04JbtMLrbwXdgY4PIFgeC5ldjlU2bnibhXKkE2/MjYx8B5HonlmJU3YGnjfnMzuVhi\nsfVEj1uJaRWKiNw0ZAITwD1bMfhDZShTe0WQqn6LrI1/UH5oUhqovpbWw70bz+ENp+D4TDwsZS0s\nSpmlHT0fP8DbRP044UI6dumqUBh6K1XNWgERFQD7UXK8EUV+Idp/rnr1NbNDOlaD0+dhG+p4Id+F\niQe8It9F8OXKRtsV/b7VJ70PE+RuIgrdPemrpm67UkBWnBSKixKvX9kJd4ecWPpr0hHeiPZFRA8U\nD+ACqk7FL3Q4yr05PC//O0H2Vym+cbqKruXPHgWLbH9CI9zSMFo/j+Fq7Aq+EDCG58e6G9X+bmFP\nH/5XNkvZhbeggLK+WQr8H9GQIZLZMQCboRvhX9u+eUuhUUvRU9gwFbtDrSz8K8kJBMzb8blG5UwM\nC2N2y41I2+paR+I2m5hEXkKM9tXl7VclIQIsYF6NoNH3ncc1x4HOPwxgUUR36L2amu/bzBn8MXVJ\nftczkKFdZiYMB5xIcDLovipakJFSH/w2xu6WVXWMOiA5kvgUvu+hbbVi6sHkQNFHYKIAjobH3q+3\nDrc09phW+ROYO+aTcQbKrIjZd71OhsV5rzwZ2JQ7ki7NSzGWrG6x8vZodBDEMCl2MIjkqJ+PHIov\ngo1cRx+oS/5Dae9iXLZjx04CKFNUWUSPyHHrfbNDyOPrdvGCTFr/67j/rGj1J8vVNCxtLm1bEQpc\nSIhvaUaLDRXNEjLHerJ79+3XQHd7IqCcBLemBhPmU+/fiAWJozadBEb+HGZqlMPDNzwkut2l43PB\n24M9Sj7odg/0kwUb+nkDDFoZdwlMwRh+gKg8uvy1/fK1j0sJaMju2Livjx2dKdE1F0GLrtHWI04A\nauTXE9SM5DeEDogTpQeQZPSjlINIteGYpH+oQKh9ZNsv/7z+zVFuvjSsLxXZy0AmwKADhVa+Xh1q\nPOrIzFEtf3FEPdGmEyelpCcZbjgkSf1KggQSt4O4YkgNwswY8tEBLIDAXDQExIjCYv/AIeVtzzzl\n+gKWU0UQjKYMVQCWH9zUlHQz8rQcLCB8EgUlMKDsQVoRJbvQR365CNfAX3W8rMVy4nTztqh7zU8Y\npTMGjwCCnBVie6sRytRY79AmqVpgvBPcuQdAMszg+wqIOS/YOXfWuVWaAHwDpxw6UNFMhWcFKSOH\n05VPD72EbnrzamjHK7JEkayKLgR8VVQaXYvT1jVmwbJ6/f9Gfy8CZaZuJJhKPAbeo8mMHuGWa9HL\nA8hVOZll51JKNbAGr5wPKjPHhfBCcWJqs7VIW00Fms/7xNFGllj/SZtUXSzpO/+2FCnmtjO36lw7\nuBLmHLf7CfjRZYUEgQLNVQA07zta/IkjSnwAojzCOOGiriJKJh6Xxrq7QrpLKKMpwb75V+Bf7UIq\nXCrPo45BCxCLgZ/361L4yE1xbmngU707NlaRF24SuFTe7juhvITEAy3wY6U7A7XsGp1GhBBNaYzx\n63YNFYggmHPw2SyXoCLq+pVuz+tvr1PMqnV3zzb1XvR/5Y4Tsp3bIfi00nNB+tv7WU3mCiKl+KDn\nWulilfdt2qcMkdt7dtmcPpClSu9KfkwSQANc0ehkxDHMf0CT2X361QRvY1BiIqs5wfHnQurPZVvW\nIHViiyTAS3AZ/VOpqQJ9UeATGNz/qAOHlu4l0AAE6xdtAPmQ/ccoAbLOCtCJRlTP4bk+mK/UXsj4\nG5Fs43hzF3JxJ4LR9C2FvUvkNnM4hsoGeWg5/PI3h1hXU7vUZJWEgYReDK1L7mkquUjzkWOBvs/Z\ndZTkag4LuLtNIBkAuT8lMHzT6gfGfl8FX5+8nSILKBx072cjdYwUpvNqyRE2Z/RnolUwJalgqWFb\njwYgWT1LgrAf9zDNpkiBuskNgatldY/dyAyHZ8aoMboKqqPiZMkqJKavv+FSK4leOWqG8/2gaZke\nxNn4gg7BPj+xor4DbD81mH/cZ6YSEZbXxAo5ynx3BpP6mXWX3Q9BVYMbSPDKd5LP/sL+FLO4lhXe\nHGsXA3ZwJficyeFbwqcUF4WXXjftNC8xtQgoYUdMYTmtiO2Wko7wUYf5VzXvf3iAJh6h+ii7bnNk\nQD8LnpXLyWkBAxCxXLS439nKagcl9eGoV9S59YSrP18BCUxHteCTtVutmEwT40IhND3eY4xiK2gJ\n1mJGaWYTHkCq+0qg0+pobyEVhuMvAbp+hax+P5gFIK4xkXaUrJY/rnaXTMMpPlU/ew3xGKHRD6Rn\naz43KtCgy0a0LgYTDuQkkWgfEbeC3Qc3rv1tAYrQoiVSwPN1Ppmyb500ZaLxhfGyslQtV6Cj8IKf\ncHcbEG1SU/vgXR+I/iJitzfGYck2dBP6Hc9bkQiJgCaJyzVJKT2nLPrMra+TZpxLjAf8bfzTaIR7\nyBzAM1+ONLzI4NZwoabqZphQMBeLgkvRZ4iutHq9/65XXwPhJ9rawATImQizNXIWZ/Xc/dBdeYci\ncXlh4cNi9lXr86kv42EtzQO8wiXxvpJNllzagqcYzoDS/2+v9gDA81y/sHczLBSXich8fCL9sHnk\n5HEPy+MWeoxHTXzk4NVKhoDg310u7DNHN/iqdC9jowVF45NxlX5xEGTagsxET2kbWxiMiA+l/seJ\n6hm9WQ5oT/E2yZHcl+/+7WtuGZN65uRALxVa5/5f/aiPVjAc+nbCopYK6mlCZQ1fe6EPe8V6UAwu\nmK6Uxk5h9aHjCoxyl5jtUOUpA3Z2E0IY5HjWDUmo2bW13KxWLnEpTdxtgduawTSy7y1brrIDV9Ou\nthZNeteFd9ZEFakDiqLVxSlFcVeSaMOlBtkUpVqZgEIwE4RUExVbKFs+H5eWDhOO8OZe9cSg9acu\nYYhr68IKC7t9VpDYX5OOgNcj2vxcsNVFwYRGOiq0HeDo2RS36LOmkhoHKBwolhA0gBjZd70RygkT\ne+ujgmuAfYLnTYLZ2nHTE2bGOp0zk1L9xPoBXxIvdp+k5T53k9MUi7R5IRINuNmzr5bC5Qfp1foo\nokZfB1U6tHv1oEOoThzFFHi5MhTQsKEn/ks7GCTg2bAFKYJNuuE7GjA61F1+6Pfp7NPIjUwbK7bN\nTlw/pFPKgsPwRciluwLrUwG/LcAxhFFcg+lpOR6KrBVha2FXaGyrxGufH4oJo5wlwekT/MUb5pmW\nZJgQFHqzjiiXpwW275Qpn8xplJiwEhsVfRYaQIzC5HzBQtBD0Z5xnctY48i77DbgIyL0hIwb/9pW\nQhRC7/N0v7qdT27P0pl+jumTiuNVZta8YTC7G0xouZu+vXxOvE/NO0wbDODHNploJXlfweCV1oyP\nI1N1H5/jXLW0L2eiuCupnTrqSGPbGlL5ABfwLqaZsT5pSY34+77u60VZWbsIexLeWmMfjCRnwqdW\nlazA/KsFkNe9O1U2719btMuPKm+/4TvoYxbpn1POEQsMuuwf9Pu5ujFjLAJq7KtmxM83P+hUfwbr\nG2G0JYCgS4d2fxUgAQiic7SD6J+PBgVi9fHwO7v/rbC/r7wgRKqfvQmlWmB1raUV5e7qFyPgMl91\nDb8DOYHV7Rpd6qEz88xkcQTRT4wIs2PzJ7zBQmRJXb+XbWW88jQEJVpOwGMGWqG33QS7T/CszEl2\n8G/UzSnCH9i0fIkX5bB8hX1jdnr9OkaiXmXu43+ixOyLIbZDRN2aRFEU4bczxAuR5mDXA3WX1DWF\n1LMX3PBCA3DIdqjhKv1+o7MLR+9Hree79XghCuZgtetNgzE+BgpYsP/L+wq4AzZceo2gx/0A3Ad2\nJHE71pWJ/OStHuQFDk7oCr02NKijAhZT/5I73DLzWpVMrpPwG0706DOFl5+bko+2xhL+vKkL4s9G\n43sC21ZYXx40qplG+nB4fhtMI7Lx12xMc6QgJO/DJGJbPIp5sPUk5yZyzFSb6vxhQcGKzF0jRKk2\nblj8QeOpzwmj2vNpKnM80a3UxpPiqfN7qiNdQV/oGE4utr7yunmZfyhLjo/uE0vfzSjmvB87f5Xq\nlSz9CuGzxhmVUGtT60TctfVAGIWcvXELEXV9HRvbEvzJ/XxlarWtZBkumvhDxv+H3/qxTBYBB3VL\nEE7GwzXzsRqrfwK5sZNZBrnzd+XIfp91Cnc96mK+7oU/+LV+A6NtqwEEdxNXA9EK6BlqTOYrfmNU\nUAyIzodRgP4dyJKUwF0WnCNbwi+WgWfKxeD6J6U5fRGoUSwKaIxOmNvBMgeSQ2eA+671h0YMe4NP\nqggDfVx9cXGcpytVWFntnxs6aQPg4qSpVOZkJHP2/oUPTaeW/+Hvyja+m3VTiajRHS+lfWABSwkq\n7pRAbCjzIbKeOM6sY4W63453Ewo296f3xh5ZY65u0scQgUyXtB48n3211e4tIIKNN/AwXo08/bhL\n8gThWAG9WhH2kzkFX3M7AZm47XgemDZnxChGhAXlif7chETEzzJtM8Ytn6zgg/ph9GV3i/Z6aun0\nmrCG0LMtrg4CJo+4mHmQUG27Gtd/PIm9eqWdt4ywk02K4gGJ67YvXnm+EhJHkApngBbKhp+I52ee\nZtUw0Li4xW6bs49i2dOUAjx86jsKeU7uJiWkirUvQ+aK37MPYTPcfME8nYmJNlOwZWzbVKfm00HL\nk0qmK6iDSmL/DSdx9VnPtGsNRFDgI1hAkSsqoGO2mCxxCyfAc48cWKxErLRoVWoO8VSl834ogKht\noeVK58ezIAHphOWtGVwz6GZwBiIy//1koxIMb3oR/qvXYhyucGPrvWOoGAHfpFsQPqwrb+rEKn03\nScU9PlrRZFhZOONC3GwM8Pssp2AOJT6RI+RXmNsMX2QRDtwDnC4vmHwen9MePiN3F/jppJhwA8RW\n/Rm1C2FX8ODUUj/mJU2oyh2u1HV75vH1uvUNFzDmB27k9IBiPpU0jjvuSXAJRPkzve4rYPV9xTL8\nfvi3Vtkjj6ahvzGVcsAVgAX4iWHLuRCHlAmMaXvPjURqSCU6XRgDTx1ia0CoytuL3y2O+KSUqBEK\nUqmtax5Wn+VzUtROS462rJdrp3YARn//1bxpXyg/j1/juWv0yJPQgUYcU3d3JuYIp8Q8jjoVodhn\nP1QPd79DXNB/Pwd711DNxOb0sk8yEPXHXc1Xcnnuz7a1WrYqeU+Ww/PpVga/3biOfdSOi339aWgB\nfndekDI0qMl0s9pWT+9CPjkyL0nbVWARb/uVgNpjHNmro4Nbj0HpFXKX9fwsBDeBmD2lgBrmbKj6\nbdRKGMZutn+k3xVU2uNfdFPeVpbC5lod/2xvC8Ful+0xSpTdyyvsUgfPwPgPtL/SOrLFT0nutxzZ\nkz8gjdMQ4dFDPg5YoKfi+ICV/qlSloXDse3ooI5N1ZuDqcKdcXjzm46vsfHbCZCzGxIgo+W3tT29\nAKYT0/xSqJTbX1kkMmCMOiQqCfGf29k8J1SaP1lrOC5l1AA8nrKBjm3OvciG8hf+5r02GNnwBp8Z\nZDCjx/Atsr+9LAHvecc6HiHJPuNCINcP5TLiSfF0jgcdsQm3869+RWCQUX5yLZWiVCpuQxFzPLPm\n9mjy+MRdZRDrfpkdPkHapHE3kPmPVWQXDTnhLYOgE4vdcljB4tWrpeCNm+JgRQ03G+v+wSPN9TYb\nrwX2GUhJoR/ax47EWPbYauv7LNZ2bJGfOb9s/o8KYw68eXkgj+FDljZzzP0dKUQqYjNgIw2TGCxY\ngcJ7cxv8BTZJ/JTxk7ZL577zd1AInIq0wuKBFqp2t/9tMsxSXegD0PLlzMB2fDYVGmncDtT4PzlE\nozcuiUJRipjY6DoesJlfHKyxNqJNNxjDOW3SjMiKtI8JtSQNH0BSyrRIyGNGXzX/uQArTH65IiPY\nkbNFkh5LMdN5Wn42QqnWV583GGVqmNlGzHkdprd4C+xMN4kkWbjaJVSDHQGeVbUdqT7K6j1Sa/gY\nKGZmys+BhBpakUrOXa2ouadrpwLjtjwhGHVq+zFPcxNyMBIuT43rLb116BwmRtaHmmQRa1Y9fgPg\n7LWLlkhNqEKOAPWFDQUuPpJqYr94vCP0A9arjsxYSzLkGGUsYf0r35nsW4eRMZjFyywzOyktfHup\nchvurg5EDDibgz8QtOdlGNqjerLNTRx+XGEqla27/jSiw8H1kgGrPDAeYsfAVs5y2+3WJNAsw9hT\nZzFM8t/CCIgXX2pj4yrJxSskmH6QjRspvr+VxbpVgFbgSKw/l1lDbmJDDPgX89Wmo0Bog+C8R21R\nqseSnoWZu17XsTWPMkOBeLmus/g7Aw7CMHMIYuQ4A4cJu9j0Gc6RVLvud7iLe2FMoSn0HdrObS/v\nRUAkfW832KW7aEdntoOLUdjtzOQ5QKD8YnNfz4LAzm3OhInLz/DshGnUdxR3EAL159zxjVlLZKGK\nElxu0aK5Jr8coyzWWtm+4HX92C+Qb5vXEXsmqRgIZoQPp5RpRukTUGg4zq4uAWspaTKNzxxlIEYI\npM4B/sIKkQ7sHptRAgZ/K8sDCJolRdeda8ln2ywDEJkz2nu1Kw0jm/+XghX8j1SIOG0qWiz6/Ybc\nzdbJO4Plp4J+X39ZxONVdiGg1EbaJ8UYFl+7inGY0c+VUCclN6lhgWULVKgp0ZbB3yLpKvdDBKgD\n7ZPXHoHemwi+R5aEY7fxs2S9MQcCvo7n2z8hTeHWb+DA5zq8/x/8eWhaI77HZ3DTvtkC2mVsiImR\nwjAkfk0z5JHXQ10Dqdwey7NVkAHLKwgXQG7SZFqrdI2PQV9HHw8bn3m6P+f7/EAy4MkYv8OHlwCg\nAz44PcpP9zXgPo5kl094cZivvFVVOC9A14EHv5xaRJSbue3ckHwAaVgXMonasMWqzQXHHWB4pM/2\nzq4cgM+X11VuzcRfROlRKdmu9umzZJq3sAFpM5xM4oyWtBLLHCdk+kmOffwThUPQcFT6Cp9se2Wv\nBQ3DldAMEtZ/j40qXaVivpsdHisEwN5FZQdxBMQqzZaP4UxldJ4xWKA3n61Muv4KIfoUKajddLuS\nZ5bqFL3zAkvxOf3JPUroU3wJfi2PGRcFmrNSWgp7VEHsWiBw//1PEbEYYXNzlCG322IbiY2RL6iR\nA7vI7/83fM4uY75AhDlBhuQHcEG1mL/9OfaC8TOhJiCwn2ByChDEFZhloTgtP/ZWa3aVGajOfbb2\n9X2Q7O2fzO9lBbF49OOnRLGTGH3jggbIELpZYfUF2wHdMdRJa3vJce8DTqVv771jzqUjE+fnwOv1\n269F8crvbc0cn13uXMkAyw1nN0wpG1H9l1P6jnVhrYq74DkOPEjkiK4unQKlx0aZI/YIHcAfszVM\nY0VIC2djUXZXrZlW3Y4bUmtoO4kMwI/iMgrYuA2cnHULO79HXnYXhrsdAAv9xYSiCAVQv1w7trDt\nXOmMVGvsc7eY3BpFegOKEqPqYIb5cwa75vy47XFo1zUtjPohgZ/g+MCSwqRz13l5N9vQlFSUL857\nRIPEeotyNTAsdh3vFX/jYfsonxch698ZbFLAAZ2uagiQ4oDuMeZpgeUnzcsT64lJa8GhO9cVASuE\ny0F6GpshZvVOe791qrdIB+EJ+FSESXq7IBlZ7u8nKzT3vwJbAFCmo2FIPqzBzR6n3aAQnYVuJIKN\n5Sg85UzY90qoBTGnu7wz2Z8lnZ8kGtpDSDOGhDFHBOGL1+xytbC3IeWxpkSUppE4dMh3UBtUpQpc\nrznsPHtwQusNoU5UHNl+ro08V1FXkHUs3BGo7cjO1E5mEsXECd0Yh+x/PAAC2sove1R0oZM6sGqv\n+cCCB7Vc9Az/Ei+rKcaQ7/cztvAERpeXYbhXrHeIwzJOeo6SllZ6eWAU0t9Umj75FZpWqfPlVngg\nxspwNQyDQ+pzoelgqX6CDTSoJJVBX6ypQoRpbQK004AUM2ODfMQeGrXJroVW7Dn/UvFzPHrPglZC\nHQmAG7G0MAv1OywENidA/tXzqhJYQ8VCtT2y/tKc3sh+T2PofUFs/sXPkTtUY9ALHm3DeX3H4CQP\n3Rb+ibBMospJV/C4wY8lXWgxxVCfBnLgO5r4RdQZ9iG+D+jNnqOzIsmOWgzNE+mbRYtKgPjmCs5w\nkpDjZCTmayxeTJBGAHsyCqnJxUhm0lia66LtCTkMcuB6j6i35CZ97kDpwIOi7AutER7n7lPH++Gn\nm3D321MZdm8kTkBVzTPhrnCA4JFEy+muDff1jfJIYuipA9VLqGCgficM2pPxl5PAt10RYCFRIczP\nImS8vQ89vm3/mEJLxVdbhKLSSIOUe0SyhbZ2qI77n7Pds4qv2SY5jt+R+iIhRASw7/v/kNYUxdiU\nd2whz+3cp4AylBxKxxEOrtr+SEwv9Onfj3IHTQtGHr7vZ7YgYe0YTvUebilhEDptwX6Bk4wHVH18\nELtY4IKlOENXltTlk4Fmfj2DWrqzrYwE27mXmVsBkrge382vltAomA/zHyDmmVAR9fSNI8kJqPv9\nBf0kt+ri0IU1ZZg9Woj0aa6yJritF6/2sxQwnu7hDud4nxN6agLEuHlhB37LbdL4HSPtvvRyQBEA\neetF5eYD5jUT+9nAbGZ+gGiyc7is+4wBcp5djCDST+xp/aqAUweRDNoGPk9chJw7tOrYGAsiLigf\nXAdVxBdEHR7w35WoJZOKR/ohU4uVHNlLcsqfPX8Dvr6UBD0lPGmwIq2vqjVCbdb7t6yILuEq9Ufm\nMGfARBYUMcz0CLCaO6fMddLXYb3+7JNc6BfgeNNs4c+og1l/7cS5kyAZ7etGCS4NmxOe8lgxHUWw\n8IO0tvTl6ukkA/6HFwXkZ0AbJcHifOFomjCv7anv2hOfuO9oEeFpp3WDj12n2Td+ZsWkf1AmoukR\neHaSxklqdCPcEI+UKHxQLNyr8pAOYswoRRGZbIqYW/ta17ZpL5ObFe7L0dnkTerzaK6+7QuQcXN4\nPEGg/nZtybL619pmNPfMj7PZjzIQeW/8N19FXPNLpPAoVClkPHG4Jw2tWKC4w+NgfUpUZJV5/oLG\nE0Qzbcl2mu8ISb5O1UcRkK4QStBrSta2QNvkxAkqOMW/jbQTViSnlFGnQPa3JBnvZ5xx8kSZDoL4\nzRzW+5sj6EamucW1FGMHEcaRnfoI9HYpQXf/8IyKuWe1UyYuhDL/2GkuQjpJTaIy21kze3sprXk6\nwpt1QJZ0Edtv5/8ks9db7hw2IbtXZBpSZpvE9ugD0lLiq5rPGhEahktiI7dZ3qbKT0bTXgXhrq9q\nSUMqwZoXaG/OkXvzEGInn5k3AP8V71EZfoxn5fn/UOuomkWmITLVKtg7tWd1LyrVbmJiZZFDZ7qI\np/XN53yVoQSXwoT4AshECVSbN/qX2+Qwu9Li7N8ET6x0aZ5qsJoEZr2yW2YVjQfbzCQy2cyj06/R\nMr7wwHXXa9rwr8iPvJZqmheEb7Y0AT8RjFFkICCE3TaRpLpc5GXvlm30aMqecTG2WVjbcnNiR+4F\n/C2wlDxRVm2bYvBdaKYVpicEjIE4yUAuMM8LkISEeRh569nRfVlQvmBwU9/WwXT3Ti/9jnbnlYvr\n+Ahjwb2/qNZd5qdcZoIm53BHEPFH6Vq1H/Gh/kzAJKdFN/PoXZKFLX463Mi70+9jrOYA1OiCHndK\no3zf7txPRp00vR2xJpj4unJbmpT4ffdThfuCSmKXRBTTZrgzY9yS6ftKCkee51Ztt+U6nPNlUpAN\nllyRhHkTPq060dxFuYOAoh9z58j+mdFB8eni0jqIqTlySXsVysNMX8AEngW2l89h7oV7E6W3Cthj\nLMSiKmG2/uMLyVm+c2btxBH1BiQRhQ1Rv9q39KwMbuGrzU1o1P3FtPG5HSsyJGmJtp6rDaNiiwxb\npFvHTWhTiDlj/0drNkTzFhG1JwaNzt0kOuewsLPdSir3uklbO6ecYaPK8Z4jgXerghf6lEyknZLS\nAYkKYA3rNh+45AAi1hRUOi3cp/pEHV/rSRmAPuczKvBZi/XmAqj6LGPxNcENDgMujqSw+7+uJJ0U\nQ9Yc5CELdrqvZ7mpxDFUx8QeiSww/sXE6aExkV68LMQHbrd4YaV96mjBcBLcyVqzRhLPDyuNzEFw\np4qk0TDXF1ACMNds2+Dt/Uuq9fxkmO5/q/GV1TyqO2RLP/z8GSXYvfZqOpJDtkFNGW4YcUU9OabN\nad+Q/9AomAx6BhJN0djqPBEafbnO0Jt3UVlPRE+gFekn0MvN+Tvw8vtBYQDL9VjaXZ350tmEqM5n\n8r4nQDI2NKf2AqFC1h6yx1D80OPYltLCRgU0y2GMZwp5ffMxpciUQYx48wteQkIj1vSGxelD7w3D\nFp/RHW7VRDRDzGez/pb0ZUlkmUzN7U1Eo3XRciUGIqIIUNn/ONyb3yvpQQA8wPiq1mwZIKZxyItD\n0U/CJNypm/F4npGM0VnY7fDcgFt7D29oorNPtCf2GAGAwDgKQmSNPmHVa8jJsYiuDcpw9URnTY9V\ntlH1HgWU+Tvr/riLXwOUqSufAPwmdP3p7nNAJVhufvf+5dLe5d3hxHtLxI6kjQwypWq3UBSwzQs2\nLO1+IJ1O4ds3iOra8+5J6u94UI1YsUbGYPOJwvzJ6SjHcLu8x6cWFhaUV2G6xs1fpi+7XO3lbm0y\n5W27tdy11ymOBHal9SdMg+tCFS62wxb2pPE8ZYDSXcwFxnU2QoKifLjZMYzKxXJFwweri6WL3VCt\niqEVBjol27uPCleezJI93TjZrRwL5CETU1b0nUl7hB5tni/KeEvIgKJ04f3KhE3w8g2abb6a0kXC\nuIlTQIIPxUM1ALbGJ+4f5qlVpvJ7nwT2bZ394BwTsH2S8eP241Bq2eVSuOi3Ab6tapNU4YNxIpBL\nDzcIQ/Jq3ToPenfueZrnGr3xKjeXYHJFhki5fzQIs0UkV8rvZP5qWUrko6dILN62pdzGOFJ+y4W0\nXfyMB2uKuXJv6Utx9fFydtYUyEj8Zrn90goiFM+NQU0iFdZ4QEvl1Ts+dv8/rrQH3eJTZqvI/yE3\n12TofYflRc2uRuGlx0r+Q6/3+33yPzrfr6U/aRx1N2E+vcv/L2kGVucq16ibQzJGIZqfHdBints2\nnB/xvJob2flgExd0M73QfeiBCRHzrKKyzj9Xy/YqcQjnpVZHJ0z8Khrxyx3uHHEjnFnVbod7bFEU\nc9ZV++TR2/rvd4/6tgAzf4slQhJqLWCG50xvRj+FPZPCbvxvtFnpArHuGPLhQP58M+qu8J1r6I7s\nag7qtFsFsPbykd8JxRwlB3lt4K7cNC1bKu6iSfT4vsU6XRY/ascVBykqvZDfh/zsnUvrZgmKCCBr\np5h8nDwS5zWHjQ5jShlMEqUr1g8tXsoh0g0RCOAYfHMpevkuPO3hdOrwj6+xJKkkfvuUKAJ15Siq\nsfGhPHOKEye2SzkPITZCk6Epg3vCrRweshnptUBNLAAEgZFGjAcsUQpnC+ckfUoseyAmdGwL2gw7\njQTTYXUrHvMyk+sKl6YTqd1bkaKW4kkUvaZ/rhWQefXwi759KpCKAStFGqfBO0P0buiDMWT3NQZW\nSLbgrltCu/0xvuYiq4t2Dq4pEfgQhWDCTXNAaavjbEt3oNWVDk2/oLH9DhhaEGJ7cp8+e6N6+QOS\n0bspQnURwauJmMJ8yUNYyf9ta8c40Np3aJDOareux0hbEISmQSc4Ibt8NqJFXqF7N2NWS5A+gSsi\norAZxPtzThjQ23JkrwJ0ZPNmbmcrPw1mfTOehFBdqoWPx/V1eDm5NNyriTd6LoYLbfHomQ+8WALR\nvZEOzoN+xewA5Uyk1S3+MzmEKZ3CVhK3GHoxuIMA7jpKebjYySo4sCnlQMb6qqT/bEYEyIsnWvcy\n82f7UbQc9TnIkHDhaRJw2m92dRvylHLCW54hHu6QLRMVKvHYeJNzEdtEit7GocKKSTkPn4BPI/Yi\nDB78TGR7uT3b85v7IOyxHBzEe9as39kKuQRced8pqdr9rbXMTxKG9fjurivrGePnZUbfZnOrpVRL\nkKCb+IpI64a/68XG/DR/SKALmfHrlb33vpCSd0LPcJ9gJUYGctaIA7XC5VtBzhDIcR9PBU+tTm9W\nau9psrwiInRr05n+P2ka3juxmJUvRjj+VYdfHsFkpNtAyitihSAmtBzaFQ/GCY9qd7kXWuxltG51\nrFrtLeXwN+9Dnr+9ExBWRWkyD107BNXg7Q127EZxGeVB9VR/X1KLOqjRClcK7lJrRpdva5kHRJ54\nKhRZV1sepRiHDRVCJIhJ9U6FWd/rQgWMmmcGawdgO1OX8kC5EdLJpXpkSeH5Yjqv3zzjASPu7K1e\nwWPiAxuwVgjdGKJIbluw6G5pJQ2uXDR5Xa5xsfAdroYQ0IRUvAkeOY3tND4Lkw/XVvx8KeFAWTNp\nXenmRJ5/iBqiIfM/c/rIofFpZCA5QqrNEMfQtDBkAJrxtq1sol50O0rih87WaJ+mdtwngYU7HOXS\nRQ+QLH1ciUq6EcJ73P+0hPAOokjzgjhqaori7+/iLyN1C/AWI1S59VXo4s8Lrl4s1/kVBR4QHr5V\nNiVmq4cDDDzuL1SP1j/K7bkn0GyS/RY8DPXrsujE06j3tTvjvnMGY/HaviTzAHivPGFzfXWofpT/\nFOBIBBwbn4pUVoeGWQJXIoNTcyeIxLLEOiJ2zYAUEwEdsOn+f8+dtBaERYpwAhYE4NLbwH6ple55\nRwSPKczzLDMieRAXxc+iQjGV4j/5oqHAmcwgXN7zvk/aGpMYPyA2berXcmFw0LSY1sepZIKYaWuj\noYF9Y7ElShrguXYyk1lAuvOX8VPhIpudfS7dnJHZRceapQi/Xl8DlsQg5fPaQo7gvh+5Hxbe5/dt\nsNmxiidiIGAyoTi091EqBHlEwjR9IhtjBB9469BfzhnT6ccPVCINNxJpiUBJiEOtublFQ/M7KWIP\nfC2d0pCxn06H9bmLT9zfhWsyldmMeBU9AEB2Ck/kn+c75sFlRezkk8wmqlFM2NcAvQcSf8GR2hO/\ncFxi9ZzXFOJCgdfy/9zY0YFHKKnurAgHZlgOdBl8inDgvgC2RlDXnzIuz23kNA9RxHQ2/FXl0z61\nnYwe+SCMNDzoPcUZcUBhPZonJ+3irIWLUdjkbb7qTGymgjf5KR/XMuWA/VX/8uRtjWSOc95Nbt8a\nCaci43oMh2lwO79FoeUffZYmZV3fldqnDs1ze/aOGywPwqcT1jntje94qn3lvQoQ/BJ/k93rEy+2\n5x0vRK6gNlXO4KtnS9D9Ypwk0VbvxdQ8n1IGdI8B9XTjg6ENjqtUbomhDPSFQCjwicweZXrRfUOD\nh+cPfCp22/DQgxGK2DHVgSjAS7NgTpMzbMt2/jQdh7ewO5Ek07NBPGfI47RJujdhRIoS6lFB2L5i\nM2Ly8kjyyAQreVG7AMc6P3r5WOlcr9TujTmvWGh8TOwQ1LDhVNVKJ+JGG1AzuIFYfDJBzzcZd1A5\nteF80j/Z0cUfa1hdkR4d4OTqS5QotD9WNh4QCndwopopxD6G1h9s/s5UVf0blaIfjDBU0/Nx9WVK\n6t/6Ruyhta8hQ9IxRw2VqEEY6Evx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protect end_protected\n", "num_lines": 530}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n`timescale 1ns / 1ps\nmodule vio_0 (\nclk,\nprobe_in0,probe_in1,probe_in2,probe_in3,\nprobe_out0,\nprobe_out1,\nprobe_out2,\nprobe_out3,\nprobe_out4,\nprobe_out5,\nprobe_out6\n);\n\ninput clk;\ninput [0 : 0] probe_in0;\ninput [0 : 0] probe_in1;\ninput [7 : 0] probe_in2;\ninput [15 : 0] probe_in3;\n\noutput reg [0 : 0] probe_out0 = 'h0 ;\noutput reg [0 : 0] probe_out1 = 'h0 ;\noutput reg [0 : 0] probe_out2 = 'h1 ;\noutput reg [0 : 0] probe_out3 = 'h0 ;\noutput reg [7 : 0] probe_out4 = 'h00 ;\noutput reg [15 : 0] probe_out5 = 'h0000 ;\noutput reg [15 : 0] probe_out6 = 'h0000 ;\n\n\nendmodule\n", "num_lines": 77}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n// DO NOT MODIFY THIS FILE.\n\n(* X_CORE_INFO = \"vio,Vivado 2020.2\" *)\n(* CHECK_LICENSE_TYPE = \"vio_0,vio,{}\" *)\n(* CORE_GENERATION_INFO = \"vio_0,vio,{x_ipProduct=Vivado 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_WIDTH=1,C_PROBE_OUT179_WIDTH=1,C_PROBE_OUT180_WIDTH=1,C_PROBE_OUT181_WIDTH=1,C_PROBE_OUT182_WIDTH=1,C_PROBE_OUT183_WIDTH=1,C_PROBE_OUT184_WIDTH=1,C_PROBE_OUT185_WIDTH=1,C_PROBE_OUT186_WIDTH=1,C_PROBE_OUT187_WIDTH=1,C_PROBE_OUT188_WIDTH=1,C_PROBE_OUT189_WIDTH=1,C_PROBE_OUT190_WIDTH=1,C_PROBE_OUT191_WIDTH=1,C_PROBE_OUT192_WIDTH=1,C_PROBE_OUT193_WIDTH=1,C_PROBE_OUT194_WIDTH=1,C_PROBE_OUT195_WIDTH=1,C_PROBE_OUT196_WIDTH=1,C_PROBE_OUT197_WIDTH=1,C_PROBE_OUT198_WIDTH=1,C_PROBE_OUT199_WIDTH=1,C_PROBE_OUT200_WIDTH=1,C_PROBE_OUT201_WIDTH=1,C_PROBE_OUT202_WIDTH=1,C_PROBE_OUT203_WIDTH=1,C_PROBE_OUT204_WIDTH=1,C_PROBE_OUT205_WIDTH=1,C_PROBE_OUT206_WIDTH=1,C_PROBE_OUT207_WIDTH=1,C_PROBE_OUT208_WIDTH=1,C_PROBE_OUT209_WIDTH=1,C_PROBE_OUT210_WIDTH=1,C_PROBE_OUT211_WIDTH=1,C_PROBE_OUT212_WIDTH=1,C_PROBE_OUT213_WIDTH=1,C_PROBE_OUT214_WIDTH=1,C_PROBE_OUT215_WIDTH=1,C_PROBE_OUT216_WIDTH=1,\\\nC_PROBE_OUT217_WIDTH=1,C_PROBE_OUT218_WIDTH=1,C_PROBE_OUT219_WIDTH=1,C_PROBE_OUT220_WIDTH=1,C_PROBE_OUT221_WIDTH=1,C_PROBE_OUT222_WIDTH=1,C_PROBE_OUT223_WIDTH=1,C_PROBE_OUT224_WIDTH=1,C_PROBE_OUT225_WIDTH=1,C_PROBE_OUT226_WIDTH=1,C_PROBE_OUT227_WIDTH=1,C_PROBE_OUT228_WIDTH=1,C_PROBE_OUT229_WIDTH=1,C_PROBE_OUT230_WIDTH=1,C_PROBE_OUT231_WIDTH=1,C_PROBE_OUT232_WIDTH=1,C_PROBE_OUT233_WIDTH=1,C_PROBE_OUT234_WIDTH=1,C_PROBE_OUT235_WIDTH=1,C_PROBE_OUT236_WIDTH=1,C_PROBE_OUT237_WIDTH=1,C_PROBE_OUT238_WIDTH=1,C_PROBE_OUT239_WIDTH=1,C_PROBE_OUT240_WIDTH=1,C_PROBE_OUT241_WIDTH=1,C_PROBE_OUT242_WIDTH=1,C_PROBE_OUT243_WIDTH=1,C_PROBE_OUT244_WIDTH=1,C_PROBE_OUT245_WIDTH=1,C_PROBE_OUT246_WIDTH=1,C_PROBE_OUT247_WIDTH=1,C_PROBE_OUT248_WIDTH=1,C_PROBE_OUT249_WIDTH=1,C_PROBE_OUT250_WIDTH=1,C_PROBE_OUT251_WIDTH=1,C_PROBE_OUT252_WIDTH=1,C_PROBE_OUT253_WIDTH=1,C_PROBE_OUT254_WIDTH=1,C_PROBE_OUT255_WIDTH=1,C_PROBE_OUT0_INIT_VAL=0x0,C_PROBE_OUT1_INIT_VAL=0x0,C_PROBE_OUT2_INIT_VAL=0x1,C_PROBE_OUT3_INIT_VAL=0x0,C_PROBE_OUT4_INIT_VAL=0x00,C_PROBE_OUT5_INIT_VAL=0x0000,C_PROBE_OUT6_INIT_VAL=0x0000,C_PROBE_OUT7_INIT_VAL=0,C_PROBE_OUT8_INIT_VAL=0,C_PROBE_OUT9_INIT_VAL=0,C_PROBE_OUT10_INIT_VAL=0,C_PROBE_OUT11_INIT_VAL=0,C_PROBE_OUT12_INIT_VAL=0,C_PROBE_OUT13_INIT_VAL=0,C_PROBE_OUT14_INIT_VAL=0,C_PROBE_OUT15_INIT_VAL=0,C_PROBE_OUT16_INIT_VAL=0,C_PROBE_OUT17_INIT_VAL=0,C_PROBE_OUT18_INIT_VAL=0,C_PROBE_OUT19_INIT_VAL=0,C_PROBE_OUT20_INIT_VAL=0,C_PROBE_OUT21_INIT_VAL=0,C_PROBE_OUT22_INIT_VAL=0,C_PROBE_OUT23_INIT_VAL=0,C_PROBE_OUT24_INIT_VAL=0,C_PROBE_OUT25_INIT_VAL=0,C_PROBE_OUT26_INIT_VAL=0,C_PROBE_OUT27_INIT_VAL=0,C_PROBE_OUT28_INIT_VAL=0,C_PROBE_OUT29_INIT_VAL=0,C_PROBE_OUT30_INIT_VAL=0,C_PROBE_OUT31_INIT_VAL=0,C_PROBE_OUT32_INIT_VAL=0,C_PROBE_OUT33_INIT_VAL=0,C_PROBE_OUT34_INIT_VAL=0,C_PROBE_OUT35_INIT_VAL=0,C_PROBE_OUT36_INIT_VAL=0,C_PROBE_OUT37_INIT_VAL=0,C_PROBE_OUT38_INIT_VAL=0,C_PROBE_OUT39_INIT_VAL=0,C_PROBE_OUT40_INIT_VAL=0,C_PROBE_OUT41_INIT_VAL=0,C_PROBE_OUT42_INIT_VAL=0,C_PROBE_OUT43_INIT_VAL=0,C_PROBE_OUT44_INIT_VAL=0,C_PROBE_OUT45_INIT_VAL=0,C_PROBE_OUT46_INIT_VAL=0,C_PROBE_OUT47_INIT_VAL=0,C_PROBE_OUT48_INIT_VAL=0,C_PROBE_OUT49_INIT_VAL=0,C_PROBE_OUT50_INIT_VAL=0,C_PROBE_OUT51_INIT_VAL=0,C_PROBE_OUT52_INIT_VAL=0,C_PROBE_OUT53_INIT_VAL=0,C_PROBE_OUT54_INIT_VAL=0,C_PROBE_OUT55_INIT_VAL=0,C_PROBE_OUT56_INIT_VAL=0,C_PROBE_OUT57_INIT_VAL=0,C_PROBE_OUT58_INIT_VAL=0,C_PROBE_OUT59_INIT_VAL=0,C_PROBE_OUT60_INIT_VAL=0,\\\nC_PROBE_OUT61_INIT_VAL=0,C_PROBE_OUT62_INIT_VAL=0,C_PROBE_OUT63_INIT_VAL=0,C_PROBE_OUT64_INIT_VAL=0,C_PROBE_OUT65_INIT_VAL=0,C_PROBE_OUT66_INIT_VAL=0,C_PROBE_OUT67_INIT_VAL=0,C_PROBE_OUT68_INIT_VAL=0,C_PROBE_OUT69_INIT_VAL=0,C_PROBE_OUT70_INIT_VAL=0,C_PROBE_OUT71_INIT_VAL=0,C_PROBE_OUT72_INIT_VAL=0,C_PROBE_OUT73_INIT_VAL=0,C_PROBE_OUT74_INIT_VAL=0,C_PROBE_OUT75_INIT_VAL=0,C_PROBE_OUT76_INIT_VAL=0,C_PROBE_OUT77_INIT_VAL=0,C_PROBE_OUT78_INIT_VAL=0,C_PROBE_OUT79_INIT_VAL=0,C_PROBE_OUT80_INIT_VAL=0,C_PROBE_OUT81_INIT_VAL=0,C_PROBE_OUT82_INIT_VAL=0,C_PROBE_OUT83_INIT_VAL=0,C_PROBE_OUT84_INIT_VAL=0,C_PROBE_OUT85_INIT_VAL=0,C_PROBE_OUT86_INIT_VAL=0,C_PROBE_OUT87_INIT_VAL=0,C_PROBE_OUT88_INIT_VAL=0,C_PROBE_OUT89_INIT_VAL=0,C_PROBE_OUT90_INIT_VAL=0,C_PROBE_OUT91_INIT_VAL=0,C_PROBE_OUT92_INIT_VAL=0,C_PROBE_OUT93_INIT_VAL=0,C_PROBE_OUT94_INIT_VAL=0,C_PROBE_OUT95_INIT_VAL=0,C_PROBE_OUT96_INIT_VAL=0,C_PROBE_OUT97_INIT_VAL=0,C_PROBE_OUT98_INIT_VAL=0,C_PROBE_OUT99_INIT_VAL=0,C_PROBE_OUT100_INIT_VAL=0,C_PROBE_OUT101_INIT_VAL=0,C_PROBE_OUT102_INIT_VAL=0,C_PROBE_OUT103_INIT_VAL=0,C_PROBE_OUT104_INIT_VAL=0,C_PROBE_OUT105_INIT_VAL=0,C_PROBE_OUT106_INIT_VAL=0,C_PROBE_OUT107_INIT_VAL=0,C_PROBE_OUT108_INIT_VAL=0,C_PROBE_OUT109_INIT_VAL=0,C_PROBE_OUT110_INIT_VAL=0,C_PROBE_OUT111_INIT_VAL=0,C_PROBE_OUT112_INIT_VAL=0,C_PROBE_OUT113_INIT_VAL=0,C_PROBE_OUT114_INIT_VAL=0,C_PROBE_OUT115_INIT_VAL=0,C_PROBE_OUT116_INIT_VAL=0,C_PROBE_OUT117_INIT_VAL=0,C_PROBE_OUT118_INIT_VAL=0,C_PROBE_OUT119_INIT_VAL=0,C_PROBE_OUT120_INIT_VAL=0,C_PROBE_OUT121_INIT_VAL=0,C_PROBE_OUT122_INIT_VAL=0,C_PROBE_OUT123_INIT_VAL=0,C_PROBE_OUT124_INIT_VAL=0,C_PROBE_OUT125_INIT_VAL=0,C_PROBE_OUT126_INIT_VAL=0,C_PROBE_OUT127_INIT_VAL=0,C_PROBE_OUT128_INIT_VAL=0,C_PROBE_OUT129_INIT_VAL=0,C_PROBE_OUT130_INIT_VAL=0,C_PROBE_OUT131_INIT_VAL=0,C_PROBE_OUT132_INIT_VAL=0,C_PROBE_OUT133_INIT_VAL=0,C_PROBE_OUT134_INIT_VAL=0,C_PROBE_OUT135_INIT_VAL=0,C_PROBE_OUT136_INIT_VAL=0,C_PROBE_OUT137_INIT_VAL=0,C_PROBE_OUT138_INIT_VAL=0,C_PROBE_OUT139_INIT_VAL=0,C_PROBE_OUT140_INIT_VAL=0,C_PROBE_OUT141_INIT_VAL=0,C_PROBE_OUT142_INIT_VAL=0,C_PROBE_OUT143_INIT_VAL=0,C_PROBE_OUT144_INIT_VAL=0,C_PROBE_OUT145_INIT_VAL=0,C_PROBE_OUT146_INIT_VAL=0,C_PROBE_OUT147_INIT_VAL=0,C_PROBE_OUT148_INIT_VAL=0,C_PROBE_OUT149_INIT_VAL=0,C_PROBE_OUT150_INIT_VAL=0,C_PROBE_OUT151_INIT_VAL=0,C_PROBE_OUT152_INIT_VAL=0,C_PROBE_OUT153_INIT_VAL=0,C_PROBE_OUT154_INIT_VAL=0,C_PROBE_OUT155_INIT_VAL=0,C_PROBE_OUT156_INIT_VAL=0,C_PROBE_OUT157_INIT_VAL=0,C_PROBE_OUT158_INIT_VAL=0,C_PROBE_OUT159_INIT_VAL=0,C_PROBE_OUT160_INIT_VAL=0,\\\nC_PROBE_OUT161_INIT_VAL=0,C_PROBE_OUT162_INIT_VAL=0,C_PROBE_OUT163_INIT_VAL=0,C_PROBE_OUT164_INIT_VAL=0,C_PROBE_OUT165_INIT_VAL=0,C_PROBE_OUT166_INIT_VAL=0,C_PROBE_OUT167_INIT_VAL=0,C_PROBE_OUT168_INIT_VAL=0,C_PROBE_OUT169_INIT_VAL=0,C_PROBE_OUT170_INIT_VAL=0,C_PROBE_OUT171_INIT_VAL=0,C_PROBE_OUT172_INIT_VAL=0,C_PROBE_OUT173_INIT_VAL=0,C_PROBE_OUT174_INIT_VAL=0,C_PROBE_OUT175_INIT_VAL=0,C_PROBE_OUT176_INIT_VAL=0,C_PROBE_OUT177_INIT_VAL=0,C_PROBE_OUT178_INIT_VAL=0,C_PROBE_OUT179_INIT_VAL=0,C_PROBE_OUT180_INIT_VAL=0,C_PROBE_OUT181_INIT_VAL=0,C_PROBE_OUT182_INIT_VAL=0,C_PROBE_OUT183_INIT_VAL=0,C_PROBE_OUT184_INIT_VAL=0,C_PROBE_OUT185_INIT_VAL=0,C_PROBE_OUT186_INIT_VAL=0,C_PROBE_OUT187_INIT_VAL=0,C_PROBE_OUT188_INIT_VAL=0,C_PROBE_OUT189_INIT_VAL=0,C_PROBE_OUT190_INIT_VAL=0,C_PROBE_OUT191_INIT_VAL=0,C_PROBE_OUT192_INIT_VAL=0,C_PROBE_OUT193_INIT_VAL=0,C_PROBE_OUT194_INIT_VAL=0,C_PROBE_OUT195_INIT_VAL=0,C_PROBE_OUT196_INIT_VAL=0,C_PROBE_OUT197_INIT_VAL=0,C_PROBE_OUT198_INIT_VAL=0,C_PROBE_OUT199_INIT_VAL=0,C_PROBE_OUT200_INIT_VAL=0,C_PROBE_OUT201_INIT_VAL=0,C_PROBE_OUT202_INIT_VAL=0,C_PROBE_OUT203_INIT_VAL=0,C_PROBE_OUT204_INIT_VAL=0,C_PROBE_OUT205_INIT_VAL=0,C_PROBE_OUT206_INIT_VAL=0,C_PROBE_OUT207_INIT_VAL=0,C_PROBE_OUT208_INIT_VAL=0,C_PROBE_OUT209_INIT_VAL=0,C_PROBE_OUT210_INIT_VAL=0,C_PROBE_OUT211_INIT_VAL=0,C_PROBE_OUT212_INIT_VAL=0,C_PROBE_OUT213_INIT_VAL=0,C_PROBE_OUT214_INIT_VAL=0,C_PROBE_OUT215_INIT_VAL=0,C_PROBE_OUT216_INIT_VAL=0,C_PROBE_OUT217_INIT_VAL=0,C_PROBE_OUT218_INIT_VAL=0,C_PROBE_OUT219_INIT_VAL=0,C_PROBE_OUT220_INIT_VAL=0,C_PROBE_OUT221_INIT_VAL=0,C_PROBE_OUT222_INIT_VAL=0,C_PROBE_OUT223_INIT_VAL=0,C_PROBE_OUT224_INIT_VAL=0,C_PROBE_OUT225_INIT_VAL=0,C_PROBE_OUT226_INIT_VAL=0,C_PROBE_OUT227_INIT_VAL=0,C_PROBE_OUT228_INIT_VAL=0,C_PROBE_OUT229_INIT_VAL=0,C_PROBE_OUT230_INIT_VAL=0,C_PROBE_OUT231_INIT_VAL=0,C_PROBE_OUT232_INIT_VAL=0,C_PROBE_OUT233_INIT_VAL=0,C_PROBE_OUT234_INIT_VAL=0,C_PROBE_OUT235_INIT_VAL=0,C_PROBE_OUT236_INIT_VAL=0,C_PROBE_OUT237_INIT_VAL=0,C_PROBE_OUT238_INIT_VAL=0,C_PROBE_OUT239_INIT_VAL=0,C_PROBE_OUT240_INIT_VAL=0,C_PROBE_OUT241_INIT_VAL=0,C_PROBE_OUT242_INIT_VAL=0,C_PROBE_OUT243_INIT_VAL=0,C_PROBE_OUT244_INIT_VAL=0,C_PROBE_OUT245_INIT_VAL=0,C_PROBE_OUT246_INIT_VAL=0,C_PROBE_OUT247_INIT_VAL=0,C_PROBE_OUT248_INIT_VAL=0,C_PROBE_OUT249_INIT_VAL=0,C_PROBE_OUT250_INIT_VAL=0,C_PROBE_OUT251_INIT_VAL=0,C_PROBE_OUT252_INIT_VAL=0,C_PROBE_OUT253_INIT_VAL=0,C_PROBE_OUT254_INIT_VAL=0,C_PROBE_OUT255_INIT_VAL=0}\" *)\nmodule vio_0 (\nclk,\nprobe_in0,probe_in1,probe_in2,probe_in3,\nprobe_out0,\nprobe_out1,\nprobe_out2,\nprobe_out3,\nprobe_out4,\nprobe_out5,\nprobe_out6\n);\n\ninput clk;\ninput [0 : 0] probe_in0;\ninput [0 : 0] probe_in1;\ninput [7 : 0] probe_in2;\ninput [15 : 0] probe_in3;\n\noutput [0 : 0] probe_out0;\noutput [0 : 0] probe_out1;\noutput [0 : 0] probe_out2;\noutput [0 : 0] probe_out3;\noutput [7 : 0] probe_out4;\noutput [15 : 0] probe_out5;\noutput [15 : 0] probe_out6;\n\n\nwire [16:0] sl_oport0;\nwire [36:0] sl_iport0;\n\nvio_v3_0_19_vio #(\n.C_XLNX_HW_PROBE_INFO(\"DEFAULT\"),\n.C_XDEVICEFAMILY(\"virtexuplus\"),\n.C_CORE_TYPE(2),\n.C_CORE_INFO1(0),\n.C_CORE_INFO2(0),\n.C_NUM_PROBE_IN(4),\n.C_EN_PROBE_IN_ACTIVITY(1),\n.C_NUM_PROBE_OUT(7),\n.C_MAJOR_VERSION(2013),\n.C_MINOR_VERSION(1),\n.C_BUILD_REVISION(0),\n.C_CORE_MAJOR_VER(2),\n.C_CORE_MINOR_VER(0),\n.C_CORE_MINOR_ALPHA_VER(97),\n.C_XSDB_SLAVE_TYPE(33),\n.C_NEXT_SLAVE(0),\n.C_CSE_DRV_VER(1),\n.C_USE_TEST_REG(1),\n.C_PIPE_IFACE(0),\n.C_PROBE_IN0_WIDTH(1),\n.C_PROBE_IN1_WIDTH(1),\n.C_PROBE_IN2_WIDTH(8),\n.C_PROBE_IN3_WIDTH(16),\n.C_PROBE_IN4_WIDTH(1),\n.C_PROBE_IN5_WIDTH(1),\n.C_PROBE_IN6_WIDTH(1),\n.C_PROBE_IN7_WIDTH(1),\n.C_PROBE_IN8_WIDTH(1),\n.C_PROBE_IN9_WIDTH(1),\n.C_PROBE_IN10_WIDTH(1),\n.C_PROBE_IN11_WIDTH(1),\n.C_PROBE_IN12_WIDTH(1),\n.C_PROBE_IN13_WIDTH(1),\n.C_PROBE_IN14_WIDTH(1),\n.C_PROBE_IN15_WIDTH(1),\n.C_PROBE_IN16_WIDTH(1),\n.C_PROBE_IN17_WIDTH(1),\n.C_PROBE_IN18_WIDTH(1),\n.C_PROBE_IN19_WIDTH(1),\n.C_PROBE_IN20_WIDTH(1),\n.C_PROBE_IN21_WIDTH(1),\n.C_PROBE_IN22_WIDTH(1),\n.C_PROBE_IN23_WIDTH(1),\n.C_PROBE_IN24_WIDTH(1),\n.C_PROBE_IN25_WIDTH(1),\n.C_PROBE_IN26_WIDTH(1),\n.C_PROBE_IN27_WIDTH(1),\n.C_PROBE_IN28_WIDTH(1),\n.C_PROBE_IN29_WIDTH(1),\n.C_PROBE_IN30_WIDTH(1),\n.C_PROBE_IN31_WIDTH(1),\n.C_PROBE_IN32_WIDTH(1),\n.C_PROBE_IN33_WIDTH(1),\n.C_PROBE_IN34_WIDTH(1),\n.C_PROBE_IN35_WIDTH(1),\n.C_PROBE_IN36_WIDTH(1),\n.C_PROBE_IN37_WIDTH(1),\n.C_PROBE_IN38_WIDTH(1),\n.C_PROBE_IN39_WIDTH(1),\n.C_PROBE_IN40_WIDTH(1),\n.C_PROBE_IN41_WIDTH(1),\n.C_PROBE_IN42_WIDTH(1),\n.C_PROBE_IN43_WIDTH(1),\n.C_PROBE_IN44_WIDTH(1),\n.C_PROBE_IN45_WIDTH(1),\n.C_PROBE_IN46_WIDTH(1),\n.C_PROBE_IN47_WIDTH(1),\n.C_PROBE_IN48_WIDTH(1),\n.C_PROBE_IN49_WIDTH(1),\n.C_PROBE_IN50_WIDTH(1),\n.C_PROBE_IN51_WIDTH(1),\n.C_PROBE_IN52_WIDTH(1),\n.C_PROBE_IN53_WIDTH(1),\n.C_PROBE_IN54_WIDTH(1),\n.C_PROBE_IN55_WIDTH(1),\n.C_PROBE_IN56_WIDTH(1),\n.C_PROBE_IN57_WIDTH(1),\n.C_PROBE_IN58_WIDTH(1),\n.C_PROBE_IN59_WIDTH(1),\n.C_PROBE_IN60_WIDTH(1),\n.C_PROBE_IN61_WIDTH(1),\n.C_PROBE_IN62_WIDTH(1),\n.C_PROBE_IN63_WIDTH(1),\n.C_PROBE_IN64_WIDTH(1),\n.C_PROBE_IN65_WIDTH(1),\n.C_PROBE_IN66_WIDTH(1),\n.C_PROBE_IN67_WIDTH(1),\n.C_PROBE_IN68_WIDTH(1),\n.C_PROBE_IN69_WIDTH(1),\n.C_PROBE_IN70_WIDTH(1),\n.C_PROBE_IN71_WIDTH(1),\n.C_PROBE_IN72_WIDTH(1),\n.C_PROBE_IN73_WIDTH(1),\n.C_PROBE_IN74_WIDTH(1),\n.C_PROBE_IN75_WIDTH(1),\n.C_PROBE_IN76_WIDTH(1),\n.C_PROBE_IN77_WIDTH(1),\n.C_PROBE_IN78_WIDTH(1),\n.C_PROBE_IN79_WIDTH(1),\n.C_PROBE_IN80_WIDTH(1),\n.C_PROBE_IN81_WIDTH(1),\n.C_PROBE_IN82_WIDTH(1),\n.C_PROBE_IN83_WIDTH(1),\n.C_PROBE_IN84_WIDTH(1),\n.C_PROBE_IN85_WIDTH(1),\n.C_PROBE_IN86_WIDTH(1),\n.C_PROBE_IN87_WIDTH(1),\n.C_PROBE_IN88_WIDTH(1),\n.C_PROBE_IN89_WIDTH(1),\n.C_PROBE_IN90_WIDTH(1),\n.C_PROBE_IN91_WIDTH(1),\n.C_PROBE_IN92_WIDTH(1),\n.C_PROBE_IN93_WIDTH(1),\n.C_PROBE_IN94_WIDTH(1),\n.C_PROBE_IN95_WIDTH(1),\n.C_PROBE_IN96_WIDTH(1),\n.C_PROBE_IN97_WIDTH(1),\n.C_PROBE_IN98_WIDTH(1),\n.C_PROBE_IN99_WIDTH(1),\n.C_PROBE_IN100_WIDTH(1),\n.C_PROBE_IN101_WIDTH(1),\n.C_PROBE_IN102_WIDTH(1),\n.C_PROBE_IN103_WIDTH(1),\n.C_PROBE_IN104_WIDTH(1),\n.C_PROBE_IN105_WIDTH(1),\n.C_PROBE_IN106_WIDTH(1),\n.C_PROBE_IN107_WIDTH(1),\n.C_PROBE_IN108_WIDTH(1),\n.C_PROBE_IN109_WIDTH(1),\n.C_PROBE_IN110_WIDTH(1),\n.C_PROBE_IN111_WIDTH(1),\n.C_PROBE_IN112_WIDTH(1),\n.C_PROBE_IN113_WIDTH(1),\n.C_PROBE_IN114_WIDTH(1),\n.C_PROBE_IN115_WIDTH(1),\n.C_PROBE_IN116_WIDTH(1),\n.C_PROBE_IN117_WIDTH(1),\n.C_PROBE_IN118_WIDTH(1),\n.C_PROBE_IN119_WIDTH(1),\n.C_PROBE_IN120_WIDTH(1),\n.C_PROBE_IN121_WIDTH(1),\n.C_PROBE_IN122_WIDTH(1),\n.C_PROBE_IN123_WIDTH(1),\n.C_PROBE_IN124_WIDTH(1),\n.C_PROBE_IN125_WIDTH(1),\n.C_PROBE_IN126_WIDTH(1),\n.C_PROBE_IN127_WIDTH(1),\n.C_PROBE_IN128_WIDTH(1),\n.C_PROBE_IN129_WIDTH(1),\n.C_PROBE_IN130_WIDTH(1),\n.C_PROBE_IN131_WIDTH(1),\n.C_PROBE_IN132_WIDTH(1),\n.C_PROBE_IN133_WIDTH(1),\n.C_PROBE_IN134_WIDTH(1),\n.C_PROBE_IN135_WIDTH(1),\n.C_PROBE_IN136_WIDTH(1),\n.C_PROBE_IN137_WIDTH(1),\n.C_PROBE_IN138_WIDTH(1),\n.C_PROBE_IN139_WIDTH(1),\n.C_PROBE_IN140_WIDTH(1),\n.C_PROBE_IN141_WIDTH(1),\n.C_PROBE_IN142_WIDTH(1),\n.C_PROBE_IN143_WIDTH(1),\n.C_PROBE_IN144_WIDTH(1),\n.C_PROBE_IN145_WIDTH(1),\n.C_PROBE_IN146_WIDTH(1),\n.C_PROBE_IN147_WIDTH(1),\n.C_PROBE_IN148_WIDTH(1),\n.C_PROBE_IN149_WIDTH(1),\n.C_PROBE_IN150_WIDTH(1),\n.C_PROBE_IN151_WIDTH(1),\n.C_PROBE_IN152_WIDTH(1),\n.C_PROBE_IN153_WIDTH(1),\n.C_PROBE_IN154_WIDTH(1),\n.C_PROBE_IN155_WIDTH(1),\n.C_PROBE_IN156_WIDTH(1),\n.C_PROBE_IN157_WIDTH(1),\n.C_PROBE_IN158_WIDTH(1),\n.C_PROBE_IN159_WIDTH(1),\n.C_PROBE_IN160_WIDTH(1),\n.C_PROBE_IN161_WIDTH(1),\n.C_PROBE_IN162_WIDTH(1),\n.C_PROBE_IN163_WIDTH(1),\n.C_PROBE_IN164_WIDTH(1),\n.C_PROBE_IN165_WIDTH(1),\n.C_PROBE_IN166_WIDTH(1),\n.C_PROBE_IN167_WIDTH(1),\n.C_PROBE_IN168_WIDTH(1),\n.C_PROBE_IN169_WIDTH(1),\n.C_PROBE_IN170_WIDTH(1),\n.C_PROBE_IN171_WIDTH(1),\n.C_PROBE_IN172_WIDTH(1),\n.C_PROBE_IN173_WIDTH(1),\n.C_PROBE_IN174_WIDTH(1),\n.C_PROBE_IN175_WIDTH(1),\n.C_PROBE_IN176_WIDTH(1),\n.C_PROBE_IN177_WIDTH(1),\n.C_PROBE_IN178_WIDTH(1),\n.C_PROBE_IN179_WIDTH(1),\n.C_PROBE_IN180_WIDTH(1),\n.C_PROBE_IN181_WIDTH(1),\n.C_PROBE_IN182_WIDTH(1),\n.C_PROBE_IN183_WIDTH(1),\n.C_PROBE_IN184_WIDTH(1),\n.C_PROBE_IN185_WIDTH(1),\n.C_PROBE_IN186_WIDTH(1),\n.C_PROBE_IN187_WIDTH(1),\n.C_PROBE_IN188_WIDTH(1),\n.C_PROBE_IN189_WIDTH(1),\n.C_PROBE_IN190_WIDTH(1),\n.C_PROBE_IN191_WIDTH(1),\n.C_PROBE_IN192_WIDTH(1),\n.C_PROBE_IN193_WIDTH(1),\n.C_PROBE_IN194_WIDTH(1),\n.C_PROBE_IN195_WIDTH(1),\n.C_PROBE_IN196_WIDTH(1),\n.C_PROBE_IN197_WIDTH(1),\n.C_PROBE_IN198_WIDTH(1),\n.C_PROBE_IN199_WIDTH(1),\n.C_PROBE_IN200_WIDTH(1),\n.C_PROBE_IN201_WIDTH(1),\n.C_PROBE_IN202_WIDTH(1),\n.C_PROBE_IN203_WIDTH(1),\n.C_PROBE_IN204_WIDTH(1),\n.C_PROBE_IN205_WIDTH(1),\n.C_PROBE_IN206_WIDTH(1),\n.C_PROBE_IN207_WIDTH(1),\n.C_PROBE_IN208_WIDTH(1),\n.C_PROBE_IN209_WIDTH(1),\n.C_PROBE_IN210_WIDTH(1),\n.C_PROBE_IN211_WIDTH(1),\n.C_PROBE_IN212_WIDTH(1),\n.C_PROBE_IN213_WIDTH(1),\n.C_PROBE_IN214_WIDTH(1),\n.C_PROBE_IN215_WIDTH(1),\n.C_PROBE_IN216_WIDTH(1),\n.C_PROBE_IN217_WIDTH(1),\n.C_PROBE_IN218_WIDTH(1),\n.C_PROBE_IN219_WIDTH(1),\n.C_PROBE_IN220_WIDTH(1),\n.C_PROBE_IN221_WIDTH(1),\n.C_PROBE_IN222_WIDTH(1),\n.C_PROBE_IN223_WIDTH(1),\n.C_PROBE_IN224_WIDTH(1),\n.C_PROBE_IN225_WIDTH(1),\n.C_PROBE_IN226_WIDTH(1),\n.C_PROBE_IN227_WIDTH(1),\n.C_PROBE_IN228_WIDTH(1),\n.C_PROBE_IN229_WIDTH(1),\n.C_PROBE_IN230_WIDTH(1),\n.C_PROBE_IN231_WIDTH(1),\n.C_PROBE_IN232_WIDTH(1),\n.C_PROBE_IN233_WIDTH(1),\n.C_PROBE_IN234_WIDTH(1),\n.C_PROBE_IN235_WIDTH(1),\n.C_PROBE_IN236_WIDTH(1),\n.C_PROBE_IN237_WIDTH(1),\n.C_PROBE_IN238_WIDTH(1),\n.C_PROBE_IN239_WIDTH(1),\n.C_PROBE_IN240_WIDTH(1),\n.C_PROBE_IN241_WIDTH(1),\n.C_PROBE_IN242_WIDTH(1),\n.C_PROBE_IN243_WIDTH(1),\n.C_PROBE_IN244_WIDTH(1),\n.C_PROBE_IN245_WIDTH(1),\n.C_PROBE_IN246_WIDTH(1),\n.C_PROBE_IN247_WIDTH(1),\n.C_PROBE_IN248_WIDTH(1),\n.C_PROBE_IN249_WIDTH(1),\n.C_PROBE_IN250_WIDTH(1),\n.C_PROBE_IN251_WIDTH(1),\n.C_PROBE_IN252_WIDTH(1),\n.C_PROBE_IN253_WIDTH(1),\n.C_PROBE_IN254_WIDTH(1),\n.C_PROBE_IN255_WIDTH(1),\n.C_PROBE_OUT0_WIDTH(1),\n.C_PROBE_OUT1_WIDTH(1),\n.C_PROBE_OUT2_WIDTH(1),\n.C_PROBE_OUT3_WIDTH(1),\n.C_PROBE_OUT4_WIDTH(8),\n.C_PROBE_OUT5_WIDTH(16),\n.C_PROBE_OUT6_WIDTH(16),\n.C_PROBE_OUT7_WIDTH(1),\n.C_PROBE_OUT8_WIDTH(1),\n.C_PROBE_OUT9_WIDTH(1),\n.C_PROBE_OUT10_WIDTH(1),\n.C_PROBE_OUT11_WIDTH(1),\n.C_PROBE_OUT12_WIDTH(1),\n.C_PROBE_OUT13_WIDTH(1),\n.C_PROBE_OUT14_WIDTH(1),\n.C_PROBE_OUT15_WIDTH(1),\n.C_PROBE_OUT16_WIDTH(1),\n.C_PROBE_OUT17_WIDTH(1),\n.C_PROBE_OUT18_WIDTH(1),\n.C_PROBE_OUT19_WIDTH(1),\n.C_PROBE_OUT20_WIDTH(1),\n.C_PROBE_OUT21_WIDTH(1),\n.C_PROBE_OUT22_WIDTH(1),\n.C_PROBE_OUT23_WIDTH(1),\n.C_PROBE_OUT24_WIDTH(1),\n.C_PROBE_OUT25_WIDTH(1),\n.C_PROBE_OUT26_WIDTH(1),\n.C_PROBE_OUT27_WIDTH(1),\n.C_PROBE_OUT28_WIDTH(1),\n.C_PROBE_OUT29_WIDTH(1),\n.C_PROBE_OUT30_WIDTH(1),\n.C_PROBE_OUT31_WIDTH(1),\n.C_PROBE_OUT32_WIDTH(1),\n.C_PROBE_OUT33_WIDTH(1),\n.C_PROBE_OUT34_WIDTH(1),\n.C_PROBE_OUT35_WIDTH(1),\n.C_PROBE_OUT36_WIDTH(1),\n.C_PROBE_OUT37_WIDTH(1),\n.C_PROBE_OUT38_WIDTH(1),\n.C_PROBE_OUT39_WIDTH(1),\n.C_PROBE_OUT40_WIDTH(1),\n.C_PROBE_OUT41_WIDTH(1),\n.C_PROBE_OUT42_WIDTH(1),\n.C_PROBE_OUT43_WIDTH(1),\n.C_PROBE_OUT44_WIDTH(1),\n.C_PROBE_OUT45_WIDTH(1),\n.C_PROBE_OUT46_WIDTH(1),\n.C_PROBE_OUT47_WIDTH(1),\n.C_PROBE_OUT48_WIDTH(1),\n.C_PROBE_OUT49_WIDTH(1),\n.C_PROBE_OUT50_WIDTH(1),\n.C_PROBE_OUT51_WIDTH(1),\n.C_PROBE_OUT52_WIDTH(1),\n.C_PROBE_OUT53_WIDTH(1),\n.C_PROBE_OUT54_WIDTH(1),\n.C_PROBE_OUT55_WIDTH(1),\n.C_PROBE_OUT56_WIDTH(1),\n.C_PROBE_OUT57_WIDTH(1),\n.C_PROBE_OUT58_WIDTH(1),\n.C_PROBE_OUT59_WIDTH(1),\n.C_PROBE_OUT60_WIDTH(1),\n.C_PROBE_OUT61_WIDTH(1),\n.C_PROBE_OUT62_WIDTH(1),\n.C_PROBE_OUT63_WIDTH(1),\n.C_PROBE_OUT64_WIDTH(1),\n.C_PROBE_OUT65_WIDTH(1),\n.C_PROBE_OUT66_WIDTH(1),\n.C_PROBE_OUT67_WIDTH(1),\n.C_PROBE_OUT68_WIDTH(1),\n.C_PROBE_OUT69_WIDTH(1),\n.C_PROBE_OUT70_WIDTH(1),\n.C_PROBE_OUT71_WIDTH(1),\n.C_PROBE_OUT72_WIDTH(1),\n.C_PROBE_OUT73_WIDTH(1),\n.C_PROBE_OUT74_WIDTH(1),\n.C_PROBE_OUT75_WIDTH(1),\n.C_PROBE_OUT76_WIDTH(1),\n.C_PROBE_OUT77_WIDTH(1),\n.C_PROBE_OUT78_WIDTH(1),\n.C_PROBE_OUT79_WIDTH(1),\n.C_PROBE_OUT80_WIDTH(1),\n.C_PROBE_OUT81_WIDTH(1),\n.C_PROBE_OUT82_WIDTH(1),\n.C_PROBE_OUT83_WIDTH(1),\n.C_PROBE_OUT84_WIDTH(1),\n.C_PROBE_OUT85_WIDTH(1),\n.C_PROBE_OUT86_WIDTH(1),\n.C_PROBE_OUT87_WIDTH(1),\n.C_PROBE_OUT88_WIDTH(1),\n.C_PROBE_OUT89_WIDTH(1),\n.C_PROBE_OUT90_WIDTH(1),\n.C_PROBE_OUT91_WIDTH(1),\n.C_PROBE_OUT92_WIDTH(1),\n.C_PROBE_OUT93_WIDTH(1),\n.C_PROBE_OUT94_WIDTH(1),\n.C_PROBE_OUT95_WIDTH(1),\n.C_PROBE_OUT96_WIDTH(1),\n.C_PROBE_OUT97_WIDTH(1),\n.C_PROBE_OUT98_WIDTH(1),\n.C_PROBE_OUT99_WIDTH(1),\n.C_PROBE_OUT100_WIDTH(1),\n.C_PROBE_OUT101_WIDTH(1),\n.C_PROBE_OUT102_WIDTH(1),\n.C_PROBE_OUT103_WIDTH(1),\n.C_PROBE_OUT104_WIDTH(1),\n.C_PROBE_OUT105_WIDTH(1),\n.C_PROBE_OUT106_WIDTH(1),\n.C_PROBE_OUT107_WIDTH(1),\n.C_PROBE_OUT108_WIDTH(1),\n.C_PROBE_OUT109_WIDTH(1),\n.C_PROBE_OUT110_WIDTH(1),\n.C_PROBE_OUT111_WIDTH(1),\n.C_PROBE_OUT112_WIDTH(1),\n.C_PROBE_OUT113_WIDTH(1),\n.C_PROBE_OUT114_WIDTH(1),\n.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inst (\n.clk(clk),\n.sl_iport0(sl_iport0),\n.sl_oport0(sl_oport0),\n.probe_in0(probe_in0),\n.probe_in1(probe_in1),\n.probe_in2(probe_in2),\n.probe_in3(probe_in3),\n.probe_in4(0),\n.probe_in5(0),\n.probe_in6(0),\n.probe_in7(0),\n.probe_in8(0),\n.probe_in9(0),\n.probe_in10(0),\n.probe_in11(0),\n.probe_in12(0),\n.probe_in13(0),\n.probe_in14(0),\n.probe_in15(0),\n.probe_in16(0),\n.probe_in17(0),\n.probe_in18(0),\n.probe_in19(0),\n.probe_in20(0),\n.probe_in21(0),\n.probe_in22(0),\n.probe_in23(0),\n.probe_in24(0),\n.probe_in25(0),\n.probe_in26(0),\n.probe_in27(0),\n.probe_in28(0),\n.probe_in29(0),\n.probe_in30(0),\n.probe_in31(0),\n.probe_in32(0),\n.probe_in33(0),\n.probe_in34(0),\n.probe_in35(0),\n.probe_in36(0),\n.probe_in37(0),\n.probe_in38(0),\n.probe_in39(0),\n.probe_in40(0),\n.probe_in41(0),\n.probe_in42(0),\n.probe_in43(0),\n.probe_in44(0),\n.probe_in45(0),\n.probe_in46(0),\n.probe_in47(0),\n.probe_in48(0),\n.probe_in49(0),\n.probe_in50(0),\n.probe_in51(0),\n.probe_in52(0),\n.probe_in53(0),\n.probe_in54(0),\n.probe_in55(0),\n.probe_in56(0),\n.probe_in57(0),\n.probe_in58(0),\n.probe_in59(0),\n.probe_in60(0),\n.probe_in61(0),\n.probe_in62(0),\n.probe_in63(0),\n.probe_in64(0),\n.probe_in65(0),\n.probe_in66(0),\n.probe_in67(0),\n.probe_in68(0),\n.probe_in69(0),\n.probe_in70(0),\n.probe_in71(0),\n.probe_in72(0),\n.probe_in73(0),\n.probe_in74(0),\n.probe_in75(0),\n.probe_in76(0),\n.probe_in77(0),\n.probe_in78(0),\n.probe_in79(0),\n.probe_in80(0),\n.probe_in81(0),\n.probe_in82(0),\n.probe_in83(0),\n.probe_in84(0),\n.probe_in85(0),\n.probe_in86(0),\n.probe_in87(0),\n.probe_in88(0),\n.probe_in89(0),\n.probe_in90(0),\n.probe_in91(0),\n.probe_in92(0),\n.probe_in93(0),\n.probe_in94(0),\n.probe_in95(0),\n.probe_in96(0),\n.probe_in97(0),\n.probe_in98(0),\n.probe_in99(0),\n.probe_in100(0),\n.probe_in101(0),\n.probe_in102(0),\n.probe_in103(0),\n.probe_in104(0),\n.probe_in105(0),\n.probe_in106(0),\n.probe_in107(0),\n.probe_in108(0),\n.probe_in109(0),\n.probe_in110(0),\n.probe_in111(0),\n.probe_in112(0),\n.probe_in113(0),\n.probe_in114(0),\n.probe_in115(0),\n.probe_in116(0),\n.probe_in117(0),\n.probe_in118(0),\n.probe_in119(0),\n.probe_in120(0),\n.probe_in121(0),\n.probe_in122(0),\n.probe_in123(0),\n.probe_in124(0),\n.probe_in125(0),\n.probe_in126(0),\n.probe_in127(0),\n.probe_in128(0),\n.probe_in129(0),\n.probe_in130(0),\n.probe_in131(0),\n.probe_in132(0),\n.probe_in133(0),\n.probe_in134(0),\n.probe_in135(0),\n.probe_in136(0),\n.probe_in137(0),\n.probe_in138(0),\n.probe_in139(0),\n.probe_in140(0),\n.probe_in141(0),\n.probe_in142(0),\n.probe_in143(0),\n.probe_in144(0),\n.probe_in145(0),\n.probe_in146(0),\n.probe_in147(0),\n.probe_in148(0),\n.probe_in149(0),\n.probe_in150(0),\n.probe_in151(0),\n.probe_in152(0),\n.probe_in153(0),\n.probe_in154(0),\n.probe_in155(0),\n.probe_in156(0),\n.probe_in157(0),\n.probe_in158(0),\n.probe_in159(0),\n.probe_in160(0),\n.probe_in161(0),\n.probe_in162(0),\n.probe_in163(0),\n.probe_in164(0),\n.probe_in165(0),\n.probe_in166(0),\n.probe_in167(0),\n.probe_in168(0),\n.probe_in169(0),\n.probe_in170(0),\n.probe_in171(0),\n.probe_in172(0),\n.probe_in173(0),\n.probe_in174(0),\n.probe_in175(0),\n.probe_in176(0),\n.probe_in177(0),\n.probe_in178(0),\n.probe_in179(0),\n.probe_in180(0),\n.probe_in181(0),\n.probe_in182(0),\n.probe_in183(0),\n.probe_in184(0),\n.probe_in185(0),\n.probe_in186(0),\n.probe_in187(0),\n.probe_in188(0),\n.probe_in189(0),\n.probe_in190(0),\n.probe_in191(0),\n.probe_in192(0),\n.probe_in193(0),\n.probe_in194(0),\n.probe_in195(0),\n.probe_in196(0),\n.probe_in197(0),\n.probe_in198(0),\n.probe_in199(0),\n.probe_in200(0),\n.probe_in201(0),\n.probe_in202(0),\n.probe_in203(0),\n.probe_in204(0),\n.probe_in205(0),\n.probe_in206(0),\n.probe_in207(0),\n.probe_in208(0),\n.probe_in209(0),\n.probe_in210(0),\n.probe_in211(0),\n.probe_in212(0),\n.probe_in213(0),\n.probe_in214(0),\n.probe_in215(0),\n.probe_in216(0),\n.probe_in217(0),\n.probe_in218(0),\n.probe_in219(0),\n.probe_in220(0),\n.probe_in221(0),\n.probe_in222(0),\n.probe_in223(0),\n.probe_in224(0),\n.probe_in225(0),\n.probe_in226(0),\n.probe_in227(0),\n.probe_in228(0),\n.probe_in229(0),\n.probe_in230(0),\n.probe_in231(0),\n.probe_in232(0),\n.probe_in233(0),\n.probe_in234(0),\n.probe_in235(0),\n.probe_in236(0),\n.probe_in237(0),\n.probe_in238(0),\n.probe_in239(0),\n.probe_in240(0),\n.probe_in241(0),\n.probe_in242(0),\n.probe_in243(0),\n.probe_in244(0),\n.probe_in245(0),\n.probe_in246(0),\n.probe_in247(0),\n.probe_in248(0),\n.probe_in249(0),\n.probe_in250(0),\n.probe_in251(0),\n.probe_in252(0),\n.probe_in253(0),\n.probe_in254(0),\n.probe_in255(0),\n.probe_out0(probe_out0),\n.probe_out1(probe_out1),\n.probe_out2(probe_out2),\n.probe_out3(probe_out3),\n.probe_out4(probe_out4),\n.probe_out5(probe_out5),\n.probe_out6(probe_out6),\n.probe_out7(),\n.probe_out8(),\n.probe_out9(),\n.probe_out10(),\n.probe_out11(),\n.probe_out12(),\n.probe_out13(),\n.probe_out14(),\n.probe_out15(),\n.probe_out16(),\n.probe_out17(),\n.probe_out18(),\n.probe_out19(),\n.probe_out20(),\n.probe_out21(),\n.probe_out22(),\n.probe_out23(),\n.probe_out24(),\n.probe_out25(),\n.probe_out26(),\n.probe_out27(),\n.probe_out28(),\n.probe_out29(),\n.probe_out30(),\n.probe_out31(),\n.probe_out32(),\n.probe_out33(),\n.probe_out34(),\n.probe_out35(),\n.probe_out36(),\n.probe_out37(),\n.probe_out38(),\n.probe_out39(),\n.probe_out40(),\n.probe_out41(),\n.probe_out42(),\n.probe_out43(),\n.probe_out44(),\n.probe_out45(),\n.probe_out46(),\n.probe_out47(),\n.probe_out48(),\n.probe_out49(),\n.probe_out50(),\n.probe_out51(),\n.probe_out52(),\n.probe_out53(),\n.probe_out54(),\n.probe_out55(),\n.probe_out56(),\n.probe_out57(),\n.probe_out58(),\n.probe_out59(),\n.probe_out60(),\n.probe_out61(),\n.probe_out62(),\n.probe_out63(),\n.probe_out64(),\n.probe_out65(),\n.probe_out66(),\n.probe_out67(),\n.probe_out68(),\n.probe_out69(),\n.probe_out70(),\n.probe_out71(),\n.probe_out72(),\n.probe_out73(),\n.probe_out74(),\n.probe_out75(),\n.probe_out76(),\n.probe_out77(),\n.probe_out78(),\n.probe_out79(),\n.probe_out80(),\n.probe_out81(),\n.probe_out82(),\n.probe_out83(),\n.probe_out84(),\n.probe_out85(),\n.probe_out86(),\n.probe_out87(),\n.probe_out88(),\n.probe_out89(),\n.probe_out90(),\n.probe_out91(),\n.probe_out92(),\n.probe_out93(),\n.probe_out94(),\n.probe_out95(),\n.probe_out96(),\n.probe_out97(),\n.probe_out98(),\n.probe_out99(),\n.probe_out100(),\n.probe_out101(),\n.probe_out102(),\n.probe_out103(),\n.probe_out104(),\n.probe_out105(),\n.probe_out106(),\n.probe_out107(),\n.probe_out108(),\n.probe_out109(),\n.probe_out110(),\n.probe_out111(),\n.probe_out112(),\n.probe_out113(),\n.probe_out114(),\n.probe_out115(),\n.probe_out116(),\n.probe_out117(),\n.probe_out118(),\n.probe_out119(),\n.probe_out120(),\n.probe_out121(),\n.probe_out122(),\n.probe_out123(),\n.probe_out124(),\n.probe_out125(),\n.probe_out126(),\n.probe_out127(),\n.probe_out128(),\n.probe_out129(),\n.probe_out130(),\n.probe_out131(),\n.probe_out132(),\n.probe_out133(),\n.probe_out134(),\n.probe_out135(),\n.probe_out136(),\n.probe_out137(),\n.probe_out138(),\n.probe_out139(),\n.probe_out140(),\n.probe_out141(),\n.probe_out142(),\n.probe_out143(),\n.probe_out144(),\n.probe_out145(),\n.probe_out146(),\n.probe_out147(),\n.probe_out148(),\n.probe_out149(),\n.probe_out150(),\n.probe_out151(),\n.probe_out152(),\n.probe_out153(),\n.probe_out154(),\n.probe_out155(),\n.probe_out156(),\n.probe_out157(),\n.probe_out158(),\n.probe_out159(),\n.probe_out160(),\n.probe_out161(),\n.probe_out162(),\n.probe_out163(),\n.probe_out164(),\n.probe_out165(),\n.probe_out166(),\n.probe_out167(),\n.probe_out168(),\n.probe_out169(),\n.probe_out170(),\n.probe_out171(),\n.probe_out172(),\n.probe_out173(),\n.probe_out174(),\n.probe_out175(),\n.probe_out176(),\n.probe_out177(),\n.probe_out178(),\n.probe_out179(),\n.probe_out180(),\n.probe_out181(),\n.probe_out182(),\n.probe_out183(),\n.probe_out184(),\n.probe_out185(),\n.probe_out186(),\n.probe_out187(),\n.probe_out188(),\n.probe_out189(),\n.probe_out190(),\n.probe_out191(),\n.probe_out192(),\n.probe_out193(),\n.probe_out194(),\n.probe_out195(),\n.probe_out196(),\n.probe_out197(),\n.probe_out198(),\n.probe_out199(),\n.probe_out200(),\n.probe_out201(),\n.probe_out202(),\n.probe_out203(),\n.probe_out204(),\n.probe_out205(),\n.probe_out206(),\n.probe_out207(),\n.probe_out208(),\n.probe_out209(),\n.probe_out210(),\n.probe_out211(),\n.probe_out212(),\n.probe_out213(),\n.probe_out214(),\n.probe_out215(),\n.probe_out216(),\n.probe_out217(),\n.probe_out218(),\n.probe_out219(),\n.probe_out220(),\n.probe_out221(),\n.probe_out222(),\n.probe_out223(),\n.probe_out224(),\n.probe_out225(),\n.probe_out226(),\n.probe_out227(),\n.probe_out228(),\n.probe_out229(),\n.probe_out230(),\n.probe_out231(),\n.probe_out232(),\n.probe_out233(),\n.probe_out234(),\n.probe_out235(),\n.probe_out236(),\n.probe_out237(),\n.probe_out238(),\n.probe_out239(),\n.probe_out240(),\n.probe_out241(),\n.probe_out242(),\n.probe_out243(),\n.probe_out244(),\n.probe_out245(),\n.probe_out246(),\n.probe_out247(),\n.probe_out248(),\n.probe_out249(),\n.probe_out250(),\n.probe_out251(),\n.probe_out252(),\n.probe_out253(),\n.probe_out254(),\n.probe_out255()\n)/* synthesis syn_noprune=1 */;\nendmodule\n", "num_lines": 1395}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_master #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_SUPPORTS_NARROW = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1,\n   parameter [C_AXI_ADDR_WIDTH-1:0] C_AXI_ADDR = 0,  // Base address\n   parameter integer C_NUM_ADDR = 1,  // Number of address iterations; range 1..2**16 (fixed increment = 32'h10000\n   parameter integer C_NUM_ID = 1,  // Number of ID iterations; range 1..2**C_ID_WIDTH (base = 0; fixed increment = 1)\n   parameter integer C_NUM_LEN = 1,  // Number of LEN iterations; range 1..9 (base = 0; value = 2**i - 1)\n   parameter integer C_NUM_TRANS = 1  // Number of transactions; range >=1 (read and write)\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_awvalid,\n  input  wire                            m_axi_awready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_awburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_awlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_awlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_awid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]    m_axi_awuser = 'b0,\n  /**************** Write Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_wid,\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]      m_axi_wdata,\n  (* dont_touch=\"true\" *) output reg [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb = {(C_AXI_DATA_WIDTH/8){1'b1}},\n  (* dont_touch=\"true\" *) output wire                             m_axi_wvalid,\n  input  wire                            m_axi_wready,\n  (* dont_touch=\"true\" *) output wire                             m_axi_wlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]     m_axi_wuser = 'b0,\n  /**************** Write Response Channel Signals ****************/\n  input  wire [2-1:0]                    m_axi_bresp,\n  input  wire                            m_axi_bvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_bready,\n  input  wire [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]     m_axi_buser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_bid,\n  /**************** Read Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_arvalid,\n  input  wire                            m_axi_arready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_arburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_arlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_arlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_arid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]    m_axi_aruser = 'b0,\n  /**************** Read Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]      m_axi_rdata,\n  input  wire [2-1:0]                    m_axi_rresp,\n  input  wire                            m_axi_rvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_rready,\n  input  wire                            m_axi_rlast,\n  input  wire [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]     m_axi_ruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_rid,\n  /**************** System Signals ****************/\n  input  wire                            aclk,\n  input  wire                            aresetn\n  );\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n  localparam integer  P_NUM_ID_LOG = f_ceil_log2(C_NUM_ID);\n  localparam integer  P_NUM_ADDR_LOG = f_ceil_log2(C_NUM_ADDR);\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL==0 ? 8 : C_AXI_PROTOCOL==1 ? 4 : 1);\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer               P_M_AXI_DATA_BYTES = (C_AXI_DATA_WIDTH / 8);\n  localparam integer               P_M_AXI_DONE_WIDTH = f_ceil_log2(C_NUM_TRANS<2?2:C_NUM_TRANS);\n  localparam integer               P_M_AXI_SIZE = f_ceil_log2(C_AXI_DATA_WIDTH)-3;\n\n  /**************** Internal Wires/Regs - Global ****************/\n   wire                            done;\n    wire                            dummy ;\n  reg                         done_i;\n  reg                         done_sel;\n  wire                         done_cycle;\n  reg                          done_d1 = 1'b0;\n  reg                   areset = 1'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] arcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] rcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [3:0]                    acc_r_i = 4'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] awcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] wcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] bcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [2:0]                    acc_b_i = 3'b0;\n\n  // Register Reset\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    \n    /**************** Internal Wires/Regs - Read Channels ****************/\n    wire                         read_xaction_done_i;\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_arid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_ADDR_WIDTH:0]      araddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  arprot_i = 3'b0;\n    reg [3-1:0]                  arsize_i = 3'b0;\n    reg [2-1:0]                  arburst_i = 2'b0;\n    reg [4-1:0]                  arcache_i = 4'b0;\n    reg [2-1:0]                  arlock_i = 2'b0;\n    reg [P_LEN_WIDTH-1:0]     arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [4-1:0]                  arqos_i = 4'b0;\n    reg [P_ID_WIDTH-1:0]        arid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [2-1:0]                  rresp_i = 2'b00;\n    reg [C_AXI_RUSER_WIDTH:0]   ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      rid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_arvalid_i = 1'b0;\n    reg                        m_axi_rready_i = 1'b0;\n    reg [P_NUM_ADDR_LOG:0]    araddr_cnt = 0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign read_xaction_done_i = m_axi_rvalid && m_axi_rready_i && ((C_AXI_PROTOCOL==2)?1'b1:m_axi_rlast);\n    assign m_axi_arvalid = m_axi_arvalid_i;\n    assign m_axi_rready = m_axi_rready_i;\n    assign m_axi_araddr = m_axi_araddr_i;\n    assign m_axi_arlen = m_axi_arlen_i;\n    always @(posedge aclk) begin\n      m_axi_arprot <= dummy ? arprot_i : 3'b000;\n      m_axi_arsize <= dummy ? arsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_arburst <= dummy ? arburst_i : 2'b01;\n      m_axi_arlock <= dummy ? arlock_i : 1'b0;\n      m_axi_arcache <= dummy ? arcache_i : 4'h3;\n      m_axi_arqos <= dummy  ? arqos_i : 4'h0;\n      m_axi_aruser <= dummy ? aruser_i : 0;\n    end\n  \n    //**********************************************\n    // Read Channel: ARVALID, ARADDR, ARLEN, RREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_arvalid_i <= 1'b0;\n        arcnt_i <= C_NUM_TRANS;\n        m_axi_arlen_i <= 0;\n        m_axi_araddr_i <= C_AXI_ADDR;\n        m_axi_arid_i <= 1;\n        araddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_arready & m_axi_arvalid_i) begin\n          arcnt_i <= arcnt_i - 1;\n          if (araddr_cnt == 1) begin\n            m_axi_araddr_i <= dummy ? araddr_i : C_AXI_ADDR;\n            araddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_araddr_i <= m_axi_araddr_i + 32'h10000;\n            araddr_cnt <= araddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_arlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_arlen_i <= dummy ? arlen_i : 0;\n          end else begin\n            m_axi_arlen_i <= (m_axi_arlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_arid_i == C_NUM_ID)) begin\n            m_axi_arid <= dummy ? arid_i : 0;\n            m_axi_arid_i <= 1;\n          end else begin\n            m_axi_arid <= m_axi_arid_i;\n            m_axi_arid_i <= m_axi_arid_i + 1;\n          end\n          if (arcnt_i == 1) begin\n            m_axi_arvalid_i <= 1'b0;\n          end\n        end else if (arcnt_i != 0) begin\n          m_axi_arvalid_i <= 1'b1;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      araddr_i <= {araddr_i, ~araddr_i[C_AXI_ADDR_WIDTH]};\n      arprot_i <= {arprot_i, ~arprot_i[3-1]};\n      arlen_i <= {arlen_i, ~arlen_i[P_LEN_WIDTH-1]};\n      arsize_i <= {arsize_i, ~arsize_i[3-1]};\n      arburst_i <= {arburst_i, ~arburst_i[2-1]};\n      arlock_i <= {arlock_i, ~arlock_i[2-1]};\n      arcache_i <= {arcache_i, ~arcache_i[4-1]};\n      arqos_i <= {arqos_i, ~arqos_i[4-1]};\n      aruser_i <= {aruser_i, ~aruser_i[C_AXI_ARUSER_WIDTH]};\n      arid_i <= {arid_i, ~arid_i[P_ID_WIDTH-1]};\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        m_axi_rready_i <= 1'b0;\n        rcnt_i <= C_NUM_TRANS;\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        rresp_i <= {2{1'b0}};\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n        rid_i <= {P_ID_WIDTH{1'b0}};\n        acc_r_i <= 4'b0;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_rvalid & m_axi_rready_i) begin\n          m_axi_rready_i <= 1'b0;\n          rdata_i <= m_axi_rdata;\n            acc_r_i[0] <= rdata_i[0];\n          rresp_i <= m_axi_rresp;\n            acc_r_i[1] <= rresp_i[0];\n          ruser_i <= m_axi_ruser;\n            acc_r_i[2] <= ruser_i[0];\n          rid_i <= m_axi_rid;\n            acc_r_i[3] <= rid_i[0];\n          if (m_axi_rlast) begin\n            rcnt_i <= rcnt_i - 1;\n          end\n        end else begin\n          rdata_i <= rdata_i>>1;\n          rresp_i <= rresp_i>>1;\n          ruser_i <= ruser_i>>1;\n          rid_i <= rid_i>>1;\n          acc_r_i <= acc_r_i>>1;\n          if (m_axi_rvalid) begin\n            m_axi_rready_i <= 1'b1;\n          end\n        end\n      end\n    end\n    \n    assign dummy = rdata_i[0];\n    \n    \n\n    /**************** Internal Wires/Regs - Write Channels ****************/\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_awid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [8-1:0]                  xfer_w_i = 8'h00;\n    wire                         write_burst_done_i;\n    reg [C_AXI_ADDR_WIDTH:0]      awaddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  awprot_i = 3'b0;\n    reg [P_LEN_WIDTH-1:0]     awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [3-1:0]                  awsize_i = 3'b0;\n    reg [2-1:0]                  awburst_i = 2'b0;\n    reg [4-1:0]                  awcache_i = 4'b0;\n    reg [2-1:0]                  awlock_i = 2'b0;\n    reg [4-1:0]                  awqos_i = 4'b0;\n    reg [P_ID_WIDTH:0]        awid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_AWUSER_WIDTH:0]    awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg [P_M_AXI_DATA_BYTES-1:0] wstrb_i = {P_M_AXI_DATA_BYTES{1'b1}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]        wid_i = {P_ID_WIDTH{1'b0}};\n    reg [2-1:0]                  bresp_i = 2'b00;\n    reg [C_AXI_BUSER_WIDTH:0]   buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      bid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_awvalid_i = 1'b0;\n    reg                        m_axi_wvalid_i = 1'b0;\n    reg                        m_axi_bready_i = 1'b0;\n    reg                        m_axi_wlast_i = 1'b0;\n    reg                        m_axi_wid_i = {P_ID_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]     wlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [P_NUM_ADDR_LOG:0]    awaddr_cnt = 0;\n  \n    /**************** Assign Write Channel Outputs ****************/\n    assign m_axi_wdata = {wdata_i, done};\n    assign write_burst_done_i = m_axi_wready && m_axi_wvalid_i && ((C_AXI_PROTOCOL==2) || m_axi_wlast_i);\n    assign m_axi_awvalid = m_axi_awvalid_i;\n    assign m_axi_wvalid = m_axi_wvalid_i;\n    assign m_axi_bready = m_axi_bready_i;\n    assign m_axi_wlast = m_axi_wlast_i;\n    assign m_axi_awaddr = m_axi_awaddr_i;\n    assign m_axi_awlen = m_axi_awlen_i;\n    assign m_axi_wid = m_axi_wid_i;\n    always @(posedge aclk) begin\n      m_axi_awprot <= dummy ? awprot_i : 3'b000;\n      m_axi_awsize <= dummy ? awsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_awburst <= dummy ? awburst_i : 2'b01;\n      m_axi_awlock <= dummy ? awlock_i : 1'b0;\n      m_axi_awcache <= dummy ? awcache_i : 4'h3;\n      m_axi_awqos <= dummy ? awqos_i : 4'h0;\n      m_axi_wstrb <= dummy ? wstrb_i : {P_M_AXI_DATA_BYTES{1'b1}};\n      m_axi_awuser <= dummy ?  awuser_i : 0;\n      m_axi_wuser <= dummy ?  wuser_i : 0;\n    end\n  \n    //**********************************************\n    // Write Channel: AWVALID, AWADDR, AWLEN, WVALID, WLAST, BREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_awvalid_i <= 1'b0;\n        m_axi_wvalid_i <= 1'b0;\n        awcnt_i <= C_NUM_TRANS;\n        wcnt_i <= C_NUM_TRANS;\n        xfer_w_i <= 8'h00;\n        m_axi_awlen_i <= 0;\n        m_axi_awaddr_i <= C_AXI_ADDR;\n        m_axi_awid_i <= 1;\n        m_axi_wid_i <= 0;\n        m_axi_wlast_i <= 1'b0;\n        wlen_i <= 0;\n        wid_i <= 0;\n        awaddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_awvalid_i <= 1'b0;\n          awcnt_i <= awcnt_i - 1;\n          if (awaddr_cnt == 1) begin\n            m_axi_awaddr_i <= dummy ? awaddr_i : C_AXI_ADDR;\n            awaddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_awaddr_i <= m_axi_awaddr_i + 32'h10000;\n            awaddr_cnt <= awaddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_awlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_awlen_i <= dummy ? awlen_i : 0;\n          end else begin\n            m_axi_awlen_i <= (m_axi_awlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_awid_i == C_NUM_ID)) begin\n            m_axi_awid <= dummy ? awid_i : 0;\n            m_axi_awid_i <= 1;\n          end else begin\n            m_axi_awid <= m_axi_awid_i;\n            m_axi_awid_i <= m_axi_awid_i + 1;\n          end\n        end else if (~m_axi_wvalid_i) begin\n          if (awcnt_i != 0) begin\n            m_axi_awvalid_i <= 1'b1;\n          end\n        end\n  \n        /**************** Write Data Channel ****************/\n\n        if (m_axi_wready && m_axi_wvalid_i) begin\n          xfer_w_i <= xfer_w_i - 1'b1;\n          if (m_axi_wlast_i) begin\n            m_axi_wvalid_i <= 1'b0;\n            wcnt_i <= wcnt_i - 1'b1;\n          end else begin\n            m_axi_wlast_i <=  (xfer_w_i == 1);\n          end\n        end else if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_wvalid_i <= 1'b1;\n          xfer_w_i <= m_axi_awlen_i;\n          m_axi_wlast_i <= (m_axi_awlen_i==0);\n          m_axi_wid_i <= m_axi_awid_i;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: WDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        wdata_i <= (m_axi_wvalid_i && m_axi_wready) ? {wdata_i[C_AXI_DATA_WIDTH-2 : 0], ~wdata_i[C_AXI_DATA_WIDTH-1]} : wdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      awaddr_i <= {awaddr_i, ~awaddr_i[C_AXI_ADDR_WIDTH]};\n      awprot_i <= {awprot_i[3-2:0], ~awprot_i[3-1]};\n      wstrb_i <= {wstrb_i, ~wstrb_i[C_AXI_DATA_WIDTH/8-1]};\n      awlen_i <= {awlen_i, ~awlen_i[P_LEN_WIDTH-1]};\n      awsize_i <= {awsize_i, ~awsize_i[3-1]};\n      awburst_i <= {awburst_i, ~awburst_i[2-1]};\n      awlock_i <= {awlock_i, ~awlock_i[2-1]};\n      awcache_i <= {awcache_i, ~awcache_i[4-1]};\n      awqos_i <= {awqos_i, ~awqos_i[4-1]};\n      awid_i <= {awid_i, ~awid_i[P_ID_WIDTH-1]};\n      awuser_i <= {awuser_i, ~awuser_i[C_AXI_AWUSER_WIDTH]};\n      wuser_i <= {wuser_i, ~wuser_i[C_AXI_WUSER_WIDTH]};\n    end\n  \n    //**********************************************\n    // Write Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_bready_i <= 1'b0;\n        bcnt_i <= C_NUM_TRANS;\n        bresp_i <= {2{1'b0}};\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n        bid_i <= {P_ID_WIDTH{1'b0}};\n        acc_b_i <= 3'b0;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_bvalid & m_axi_bready_i) begin\n          m_axi_bready_i <= 1'b0;\n          bresp_i <= m_axi_bresp;\n            acc_b_i[0] <= bresp_i[0];\n          buser_i <= m_axi_buser;\n            acc_b_i[1] <= buser_i[0];\n          bid_i <= m_axi_bid;\n            acc_b_i[2] <= bid_i[0];\n          bcnt_i <= bcnt_i - 1;\n        end else begin\n          bresp_i <= bresp_i>>1;\n          buser_i <= buser_i>>1;\n          bid_i <= bid_i>>1;\n          acc_b_i <= acc_b_i>>1;\n          if (m_axi_bvalid) begin\n            m_axi_bready_i <= 1'b1;\n          end\n        end\n      end\n    end\n\n\n  //**********************************************\n  // Assert Done\n  //**********************************************\n  always @(posedge aclk) begin\n    if (~aresetn) begin\n      done_d1 <= 1'b0;\n    end else begin\n      done_d1 <= done_i;\n    end\n  end\n\n  assign done = done_sel ? done_i : done_d1;\n  assign done_cycle = done_i & ~done_d1;\n  \n  always @ * begin\n    if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_readonly_done\n       done_i = rcnt_i==0;\n       done_sel = acc_r_i[0];\n    end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_writeonly_done\n       done_i = bcnt_i==0;\n       done_sel = acc_b_i[0];\n    end else begin : gen_readwrite_done\n       done_i = (rcnt_i==0) && (bcnt_i==0);\n       done_sel = acc_r_i[0] ^ acc_b_i[0];\n    end\n  end\n  \nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n  input  wire [3-1:0]                   s_axi_awprot,\n  input  wire                           s_axi_awvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_awready,\n  input  wire [3-1:0]                   s_axi_awsize,\n  input  wire [2-1:0]                   s_axi_awburst,\n  input  wire [4-1:0]                   s_axi_awcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_awlen,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_awlock,\n  input  wire [4-1:0]                   s_axi_awqos,\n  input  wire [4-1:0]                   s_axi_awregion,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_awid,\n  input  wire [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]   s_axi_awuser,\n  /**************** Write Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n  input  wire                           s_axi_wvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_wready,\n  input  wire                           s_axi_wlast,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_wid,\n  input  wire [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]    s_axi_wuser,\n  /**************** Write Response Channel Signals ****************/\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_bresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_bvalid,\n  input  wire                           s_axi_bready,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]    s_axi_buser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_bid = 'b0,\n  /**************** Read Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n  input  wire [3-1:0]                   s_axi_arprot,\n  input  wire                           s_axi_arvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_arready,\n  input  wire [3-1:0]                   s_axi_arsize,\n  input  wire [2-1:0]                   s_axi_arburst,\n  input  wire [4-1:0]                   s_axi_arcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_arlock,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_arlen,\n  input  wire [4-1:0]                   s_axi_arqos,\n  input  wire [4-1:0]                   s_axi_arregion,\n  input  wire [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]   s_axi_aruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_arid,\n  /**************** Read Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_rresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rvalid,\n  input  wire                           s_axi_rready,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]    s_axi_ruser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_rid = 'b0,\n  /**************** System Signals ****************/\n  input  wire                           aclk,\n  input  wire                           aresetn\n   );\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL == 1) ? 4 : 8;\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer P_S_AXI_DATA_BYTES = 32/8;\n  localparam integer P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n\n  /**************** Internal Wires/Regs - Global ****************/\n  reg                   areset = 1'b0;\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    /**************** Internal Wires/Regs - Read Channels ****************/\n    reg [8-1:0]                   xfer_r_cnt = 8'h00;\n    reg [16-1:0]                  arcnt_i = 16'h0000;\n    wire                          read_xaction_done_i;\n    reg [C_AXI_DATA_WIDTH-1:0]     rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]      arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg                           arvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     araddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   arprot_i = 3'b000;\n    reg [3-1:0]                   arsize_i = 3'b000;\n    reg [2-1:0]                   arburst_i = 2'b00;\n    reg [4-1:0]                   arcache_i = 4'b0000;\n    reg [1-1:0]     arlock_i = 1'b0;\n    reg [4-1:0]                   arqos_i = 4'b0000;\n    reg [4-1:0]                   arregion_i = 4'b0000;\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_RUSER_WIDTH:0]     ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_ar_i = 9'b0;\n    reg                           s_axi_rvalid_i = 1'b0;\n    reg                           s_axi_arready_i = 1'b0;\n    reg                           s_axi_rlast_i = 1'b0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign s_axi_rdata = rdata_i;\n    assign read_xaction_done_i = (s_axi_rready && s_axi_rvalid_i && s_axi_rlast_i);\n    assign s_axi_rvalid = s_axi_rvalid_i;\n    assign s_axi_arready = s_axi_arready_i;\n    assign s_axi_rlast = s_axi_rlast_i;\n    //**********************************************\n    // Read Channel: ARREADY, RVALID, RLAST, RID\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        xfer_r_cnt <= 8'h00;\n        arcnt_i <= 16'h0000;\n        arlen_i <= {P_LEN_WIDTH{1'b0}};\n        s_axi_rlast_i <= 1'b0;\n      end else begin\n        /**************** Read Address Channel ****************/\n        // arready\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_arready_i <= 1'b0;\n          arcnt_i <= arcnt_i + 1'b1;\n        end else if (~s_axi_rvalid_i) begin\n          s_axi_arready_i <= 1'b1;\n        end\n  \n        /**************** Read Data Channel ****************/\n        // rvalid\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_rvalid_i <= 1'b1;\n          s_axi_rid <= s_axi_arid;\n          s_axi_ruser <= ruser_i;\n        end else if(read_xaction_done_i) begin\n          s_axi_rvalid_i <= 1'b0;\n        end\n  \n        // rlast\n        if(s_axi_rready && s_axi_rvalid_i) begin\n          xfer_r_cnt <= xfer_r_cnt - 1;\n          if(xfer_r_cnt == 1) begin\n            s_axi_rlast_i <= 1'b1;\n          end\n        end else if(s_axi_arready_i && s_axi_arvalid) begin\n          xfer_r_cnt <= s_axi_arlen;\n          s_axi_rlast_i <= (s_axi_arlen==0);\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Read Channel: RDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        rdata_i <= (s_axi_rready && s_axi_rvalid_i) ? {rdata_i[C_AXI_DATA_WIDTH-2 : 0], ~rdata_i[C_AXI_DATA_WIDTH-1]} : rdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_rresp <= {2{1'b0}};\n      end else if (~s_axi_rvalid_i) begin\n        s_axi_rresp <= {acc_ar_i[0], 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n      end else begin\n        ruser_i <= (s_axi_arready_i && s_axi_arvalid) ? {ruser_i, ~ruser_i[C_AXI_RUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        araddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        arprot_i <= {3{1'b0}};\n        arsize_i <= {3{1'b0}};\n        arburst_i <= {2{1'b0}};\n        arcache_i <= {4{1'b0}};\n        arlock_i <= {1{1'b0}};\n        arqos_i <= {4{1'b0}};\n        arregion_i <= {4{1'b0}};\n        aruser_i <= {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n        acc_ar_i <= 9'b0;\n      end else if (s_axi_arvalid) begin\n        // Register Inputs\n        araddr_i <= s_axi_araddr;\n          acc_ar_i[0] <= araddr_i[0];\n        arprot_i <= s_axi_arprot;\n          acc_ar_i[1] <= arprot_i[0];\n        arsize_i <= s_axi_arsize;\n          acc_ar_i[2] <= arsize_i[0];\n        arburst_i <= s_axi_arburst;\n          acc_ar_i[3] <= arburst_i[0];\n        arcache_i <= s_axi_arcache;\n          acc_ar_i[4] <= arcache_i[0];\n        arlock_i <= s_axi_arlock;\n          acc_ar_i[5] <= arlock_i[0];\n        arqos_i <= s_axi_arqos;\n          acc_ar_i[6] <= arqos_i[0];\n        arregion_i <= s_axi_arregion;\n          acc_ar_i[7] <= arregion_i[0];\n        aruser_i <= s_axi_aruser;\n          acc_ar_i[8] <= aruser_i[0];\n      end else begin\n        araddr_i <= araddr_i>>1;\n        arprot_i <= arprot_i>>1;\n        arsize_i <= arsize_i>>1;\n        arburst_i <= arburst_i>>1;\n        arcache_i <= arcache_i>>1;\n        arlock_i <= arlock_i>>1;\n        arqos_i <= arqos_i>>1;\n        arregion_i <= arregion_i>>1;\n        aruser_i <= aruser_i>>1;\n        acc_ar_i <= acc_ar_i>>1;\n      end\n    end\n  \n  \n    /**************** Internal Wires/Regs - Write Channels ****************/\n    wire                          write_burst_done_i;\n    reg [16-1:0]                  awcnt_i = 16'h0000;\n    reg                           awvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     awaddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   awprot_i = 3'b000;\n    reg [3-1:0]                   awsize_i = 3'b000;\n    reg [2-1:0]                   awburst_i = 2'b00;\n    reg [4-1:0]                   awcache_i = 4'b0000;\n    reg [P_LEN_WIDTH-1:0]      awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [1-1:0]     awlock_i = 1'b0;\n    reg [4-1:0]                   awqos_i = 4'b0000;\n    reg [4-1:0]                   awregion_i = 4'b0000;\n    reg [C_AXI_AWUSER_WIDTH:0]     awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg                           wvalid_i = 1'b0;\n    reg [C_AXI_DATA_WIDTH-1:0]     wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH/8-1:0]   wstrb_i = {(C_AXI_DATA_WIDTH/8){1'b0}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_BUSER_WIDTH:0]     buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_aw_i = 9'b0;\n    reg [3:0]                     acc_w_i = 4'b0;\n    reg                           s_axi_bvalid_i = 1'b0;\n    reg                           s_axi_awready_i = 1'b0;\n    reg                           s_axi_wready_i = 1'b0;\n    /**************** Assign Write Channel Outputs ****************/\n    assign write_burst_done_i =s_axi_wready_i && s_axi_wvalid && ((C_AXI_PROTOCOL == 2) ? 1'b1 : s_axi_wlast);\n    assign s_axi_bvalid = s_axi_bvalid_i;\n    assign s_axi_awready = s_axi_awready_i;\n    assign s_axi_wready = s_axi_wready_i;\n  \n    //**********************************************\n    // Write Channel: AWREADY, WREADY, BVALID, BID\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awcnt_i <= 16'h0000;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        /**************** Write Address Channel ****************/\n        // awready\n        if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_awready_i <= 1'b0;\n          awcnt_i <= awcnt_i + 1'b1;\n          s_axi_bid <= s_axi_awid;\n          s_axi_buser <= buser_i;\n        end else if(~s_axi_wready_i & ~s_axi_bvalid_i) begin\n          s_axi_awready_i <= 1'b1;\n        end\n  \n        /**************** Write Data Channel ****************/\n        // wready\n        if(write_burst_done_i) begin\n          s_axi_wready_i <= 1'b0;\n        end else if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_wready_i <= 1'b1;\n        end\n  \n        /**************** Write Response Channel ****************/\n        // bvalid\n        if(write_burst_done_i) begin\n          s_axi_bvalid_i <= 1'b1;\n        end else if(s_axi_bready && s_axi_bvalid_i) begin\n          s_axi_bvalid_i <= 1'b0;\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Write Channel: BRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_bresp <= {2{1'b0}};\n      end else if (~s_axi_bvalid_i) begin\n        s_axi_bresp <= {(acc_aw_i[0] ^ acc_w_i[0]), 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: BUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (aresetn) begin\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n      end else begin\n        buser_i <= (s_axi_awready_i && s_axi_awvalid) ? {buser_i, ~buser_i[C_AXI_BUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Write Address Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awaddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        awprot_i <= {3{1'b0}};\n        awsize_i <= {3{1'b0}};\n        awburst_i <= {2{1'b0}};\n        awcache_i <= {4{1'b0}};\n        awlen_i <= {P_LEN_WIDTH{1'b0}};\n        awlock_i <= {1{1'b0}};\n        awqos_i <= {4{1'b0}};\n        awregion_i <= {4{1'b0}};\n        awuser_i <= {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n        acc_aw_i <= 9'b0;\n      end else if (s_axi_awvalid) begin\n        // Register Inputs\n        awaddr_i <= s_axi_awaddr;\n          acc_aw_i[0] <= awaddr_i[0];\n        awprot_i <= s_axi_awprot;\n          acc_aw_i[1] <= awprot_i[0];\n        awsize_i <= s_axi_awsize;\n          acc_aw_i[2] <= awsize_i[0];\n        awburst_i <= s_axi_awburst;\n          acc_aw_i[3] <= awburst_i[0];\n        awcache_i <= s_axi_awcache;\n          acc_aw_i[4] <= awcache_i[0];\n        awlock_i <= s_axi_awlock;\n          acc_aw_i[5] <= awlock_i[0];\n        awqos_i <= s_axi_awqos;\n          acc_aw_i[6] <= awqos_i[0];\n        awregion_i <= s_axi_awregion;\n          acc_aw_i[7] <= awregion_i[0];\n        awuser_i <= s_axi_awuser;\n          acc_aw_i[8] <= awuser_i[0];\n      end else begin\n        awaddr_i <= awaddr_i>>1;\n        awprot_i <= awprot_i>>1;\n        awsize_i <= awsize_i>>1;\n        awburst_i <= awburst_i>>1;\n        awcache_i <= awcache_i>>1;\n        awlock_i <= awlock_i>>1;\n        awqos_i <= awqos_i>>1;\n        awregion_i <= awregion_i>>1;\n        awuser_i <= awuser_i>>1;\n        acc_aw_i <= acc_aw_i>>1;\n      end\n    end\n  \n    //**********************************************\n    // Write Data Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        wstrb_i <= {(C_AXI_DATA_WIDTH/8){1'b0}};\n        wuser_i <= {(C_AXI_WUSER_WIDTH+1){1'b0}};\n        acc_w_i <= 4'b0;\n      end else if (s_axi_wvalid) begin\n        // Register Inputs\n        wdata_i <= s_axi_wdata;\n          acc_w_i[0] <= wdata_i[0];\n        wstrb_i <= s_axi_wstrb;\n          acc_w_i[1] <= wstrb_i[0];\n        wuser_i <= s_axi_wuser;\n          acc_w_i[2] <= wuser_i[0];\n      end else begin\n        wdata_i <= wdata_i>>1;\n        wstrb_i <= wstrb_i>>1;\n        wuser_i <= wuser_i>>1;\n        acc_w_i <= acc_w_i>>1;\n      end\n    end\n  \nendmodule\n\n\n\n//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_22_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \n(* autopipeline_module=\"yes\" *)\nmodule axi_register_slice_v2_1_22_auto_slr #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n    wire                    handshake_pipe;\n    wire                    ready_pipe;\n    wire [C_DATA_WIDTH-1:0] payload_pipe;\n    (* keep=\"true\" *)                                                                reg  s_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  s_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  s_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  s_areset_resp2 = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  m_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  m_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_areset_resp2 = 1'b0;\n    \n  // Global Reset pipelining\n  \n    always @(posedge ACLK) begin\n      s_aclear       <= ~ARESETN;\n      s_areset_fwd   <= ~ARESETN; \n      s_areset_resp  <= s_areset_fwd;  // Auto-pipeline\n      s_areset_resp2 <= s_areset_resp; // Auto-pipeline\n    end\n    \n    always @(posedge ACLK) begin\n      m_aclear       <= ~ARESETN;\n      m_areset_fwd   <= ~ARESETN; \n      m_areset_resp  <= m_areset_fwd;  // Auto-pipeline\n      m_areset_resp2 <= m_areset_resp; // Auto-pipeline\n    end\n    \n  // Source-side submodule\n    \n    axi_register_slice_v2_1_22_auto_src #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_src\n      (\n       .ACLK             (ACLK),    \n       .s_aclear         (s_aclear),\n       .s_areset_resp2   (s_areset_resp2),  \n       .S_VALID          (S_VALID),  \n       .S_READY          (S_READY), \n       .S_PAYLOAD_DATA   (S_PAYLOAD_DATA),\n       .ready_pipe        (ready_pipe), \n       .handshake_pipe    (handshake_pipe),\n       .payload_pipe      (payload_pipe)  \n      );\n    \n  // Destination-side submodule\n    \n    axi_register_slice_v2_1_22_auto_dest #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_dest\n      (\n       .ACLK           (ACLK),    \n       .m_aclear       (m_aclear),\n       .m_areset_resp2 (m_areset_resp2),  \n       .M_READY        (M_READY), \n       .M_VALID        (M_VALID),  \n       .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n       .handshake_pipe  (handshake_pipe),\n       .ready_pipe      (ready_pipe),  \n       .payload_pipe    (payload_pipe)  \n      );\n    \nendmodule  // auto_slr\n\nmodule axi_register_slice_v2_1_22_auto_src #\n  (\n   parameter integer C_DATA_WIDTH = 32\n  )\n  (\n   input  wire ACLK,\n   input  wire s_aclear,\n   input  wire s_areset_resp2,\n   input  wire S_VALID,\n   input  wire ready_pipe,\n   output wire S_READY,\n   output wire handshake_pipe,\n   output wire  [C_DATA_WIDTH-1:0] payload_pipe,\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA\n   );\n    \n   (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  [C_DATA_WIDTH-1:0] payload_pipe_r;\n    (* keep=\"true\" *) reg [2:0] s_aresetn_resp4 = 3'b000;\n    wire s_aresetn_resp3;\n    wire s_aresetn_d;\n    wire s_aresetn_q;\n    wire s_handshake_d;\n    wire s_ready_i;\n    \n    assign S_READY = s_ready_i & s_aresetn_q;\n    assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;\n    assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;\n    assign payload_pipe = payload_pipe_r;\n    \n    always @(posedge ACLK or posedge s_aclear) begin\n      if (s_aclear) begin\n        s_aresetn_resp4 <= 3'b000;\n      end else begin\n        s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      payload_pipe_r <= S_PAYLOAD_DATA;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) s_aresetn_resp3_inst (\n        .Q   (s_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~s_areset_resp2)\n     );\n    \n    // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (s_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_aresetn_d)\n     );\n    \n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (handshake_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_handshake_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (s_ready_i),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (ready_pipe)\n     );\n    \nendmodule  // auto_src\n\nmodule axi_register_slice_v2_1_22_auto_dest #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   input  wire ACLK,\n   input  wire m_aclear,\n   input  wire m_areset_resp2,\n   input  wire M_READY,\n   input  wire handshake_pipe,\n   output wire ready_pipe,\n   output wire M_VALID,\n   input  wire [C_DATA_WIDTH-1:0] payload_pipe,\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n   );\n    \n    (* keep=\"true\" *) reg [2:0] m_aresetn_resp4 = 3'b000;\n    wire m_aresetn_resp3;\n    wire m_aresetn_d;\n    wire m_aresetn_q;\n    wire m_valid_i;\n    wire pop;\n    wire m_ready_d;\n    wire m_handshake_q;\n    reg  [C_DATA_WIDTH-1:0] m_payload_q;\n    \n    assign M_VALID = m_valid_i;\n    assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;\n    assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;\n    assign pop     = M_READY & m_valid_i;\n    \n    always @(posedge ACLK or posedge m_aclear) begin\n      if (m_aclear) begin\n        m_aresetn_resp4 <= 3'b000;\n      end else begin\n        m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      m_payload_q <= payload_pipe;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) m_aresetn_resp3_inst (\n        .Q   (m_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~m_areset_resp2)\n     );\n    \n    // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (m_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_aresetn_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (m_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (handshake_pipe)\n     );\n    \n    (* autopipeline_group=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (ready_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_ready_d)\n     );\n    \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  (5)  \n      )\n      srl_fifo\n      (\n       .aclk    (ACLK),    \n       .areset  (~m_aresetn_q),\n       .aclear  (m_aclear),  \n       .s_mesg  (m_payload_q),  \n       .s_valid (m_handshake_q), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      );\n    \nendmodule  // auto_dest\n\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      reg s_valid_d;\n      reg s_ready_d = 1'b0;\n      reg s_ready_reg = 1'b0;\n      reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_22_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_RESP_MIDDLE2_LATENCY = C_PIPELINES_SLAVE + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_22_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      .ACLK           (ACLK),\n      .ARESETN         (ARESETN),\n      .S_PAYLOAD_DATA (S_PAYLOAD_DATA),\n      .S_VALID        (S_VALID),\n      .S_READY        (S_READY),\n      .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n      .M_VALID        (M_VALID),\n      .M_READY        (M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_reset;\n    wire src_ready;\n    wire dummy_reset;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  ( C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( dummy_reset   ) ,\n        .laguna_s_reset_in  ( src_reset   ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset   ) ,\n        .laguna_m_reset_in  ( src_reset  ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset2   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n      \n  end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] mid_payload;\n    wire mid_handshake;\n    wire mid_ready;\n    wire mid_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n    wire dummy_reset3;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( mid_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( mid_reset    ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset3   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset3   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out (  dummy_reset2  ) ,\n        .laguna_m_reset_in  ( mid_reset   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE2_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( mid_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2   ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset3   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset3    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n   \n  generate\n\n  (* keep=\"true\" *) reg s_reset_dd = 1'b0;\n  (* keep=\"true\" *) reg m_reset_dd = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n  \n  assign laguna_s_reset_out = laguna_s_reset_out_i;\n  assign laguna_m_reset_out = laguna_m_reset_out_i;\n  \n  always @(posedge ACLK) begin\n    laguna_s_reset_in_d <= laguna_s_reset_in;\n    laguna_m_reset_in_d <= laguna_m_reset_in;\n    s_reset_dd <= laguna_s_reset_in_d;\n    m_reset_dd <= laguna_m_reset_in_d;\n    laguna_s_reset_out_i <= C_PIPELINES==0 ? laguna_m_reset_in_d : m_reset_dd;\n    laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;\n  end\n  \n  wire ACLEAR;\n  assign ACLEAR = ~ARESETN;\n  \n  if (1) begin : common\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire laguna_s_handshake_q;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, laguna_m_ready_d}; \n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else if (p==C_PIPELINES+1) begin\n          laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n\n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = handshake_i[C_PIPELINES];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_m_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* keep=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_22_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_m_reset_out = laguna_m_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_m_reset_in_d <= laguna_m_reset_in;\n      aresetn_d <= C_CHANNEL==P_FORWARD ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? areset_dly[15]  : laguna_m_reset_in_d;\n      laguna_m_reset_out_i <= areset_d;  // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n  \n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* keep=\"true\" *)  reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      ready_d <= {ready_d, laguna_m_ready_d}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid_q;\n      assign payload_valid_d = (p==0) ? (S_VALID & s_ready_i) : handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==C_PIPELINES) begin\n          laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else if (p==0) begin\n          payload_data <= S_PAYLOAD_DATA;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n      \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_s_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* keep=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_s_reset_out = laguna_s_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_s_reset_in_d <= laguna_s_reset_in;\n      aresetn_d <= C_CHANNEL==P_RESPONSE ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? laguna_s_reset_in_d : areset_dly[15];\n      laguna_s_reset_out_i <= areset_d;  // For forward channels, reflect laguna_s_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n\n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    wire laguna_s_handshake_q;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      laguna_s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n        \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n        \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)  \n      )\n      srl_fifo_0\n      (\n       .aclk    (ACLK),    \n       .areset  (areset_d),  \n       .aclear  (ACLEAR),\n       .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n       .s_valid (push), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      ); \n  \n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  reg areset_d = 1'b0;\n  reg [3:0] areset_dly = 4'b0;\n  always @(posedge ACLK) begin\n    areset_dly <= {4{~ARESETN}} | (areset_dly<<1);\n    areset_d <= areset_dly[3];\n  end\n  \n  if (1) begin : common\n    reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID & s_ready_i;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* keep=\"true\" *)  reg payload_valid = 1'b0;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          payload_data <= S_PAYLOAD_DATA;\n          payload_valid <= S_VALID & s_ready_i & ~areset_d;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n          payload_valid <= handshake_i[((p>0)?(p-1):0)];\n        end\n      end\n    end\n    \n    if (C_PIPELINES==0) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),\n         .aclear  (1'b0),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire                        aclear,  // Async clear\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    wire [1:0] state;  // State vector register\n    reg  [1:0] next;           // Next state value\n    wire [1:0] next_qual;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    reg  m_valid_d;\n    wire m_valid_q;\n    \n    assign m_valid = m_valid_q;\n    assign next_qual = areset ? K_EMPTY : next;\n    assign m_mesg  = mesg_reg;\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_mvalid_inst (\n        .Q   (m_valid_q),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (m_valid_d)\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state0_inst (\n        .Q   (state[0]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[0])\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state1_inst (\n        .Q   (state[1]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[1])\n     );\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      m_valid_d = m_valid_q & ~areset;\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid & ~areset) begin\n            next = K_HAS1;\n            m_valid_d = 1'b0;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              m_valid_d = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n              m_valid_d = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          m_valid_d = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      (* keep_hierarchy = \"yes\" *) axi_register_slice_v2_1_22_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule  // axic_reg_srl_fifo\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   //   16 -> Auto-pipelining\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_RESERVE_MODE = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n  \n  if (C_RESERVE_MODE==1) begin : gen_reserve_si\n  \n    axi_register_slice_v2_1_22_test_slave #(\n      .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n      .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n      .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n      .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n      .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n      .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n      .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n      .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n      .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .s_axi_awaddr(s_axi_awaddr),\n      .s_axi_awprot(s_axi_awprot),\n      .s_axi_awvalid(s_axi_awvalid),\n      .s_axi_awready(s_axi_awready),\n      .s_axi_awsize(s_axi_awsize),\n      .s_axi_awburst(s_axi_awburst),\n      .s_axi_awcache(s_axi_awcache),\n      .s_axi_awlen(s_axi_awlen),\n      .s_axi_awlock(s_axi_awlock),\n      .s_axi_awqos(s_axi_awqos),\n      .s_axi_awregion(s_axi_awregion),\n      .s_axi_awid(s_axi_awid),\n      .s_axi_awuser(s_axi_awuser),\n      .s_axi_wdata(s_axi_wdata),\n      .s_axi_wstrb(s_axi_wstrb),\n      .s_axi_wvalid(s_axi_wvalid),\n      .s_axi_wready(s_axi_wready),\n      .s_axi_wlast(s_axi_wlast),\n      .s_axi_wid(s_axi_wid),\n      .s_axi_wuser(s_axi_wuser),\n      .s_axi_bresp(s_axi_bresp),\n      .s_axi_bvalid(s_axi_bvalid),\n      .s_axi_bready(s_axi_bready),\n      .s_axi_buser(s_axi_buser),\n      .s_axi_bid(s_axi_bid),\n      .s_axi_araddr(s_axi_araddr),\n      .s_axi_arprot(s_axi_arprot),\n      .s_axi_arvalid(s_axi_arvalid),\n      .s_axi_arready(s_axi_arready),\n      .s_axi_arsize(s_axi_arsize),\n      .s_axi_arburst(s_axi_arburst),\n      .s_axi_arcache(s_axi_arcache),\n      .s_axi_arlock(s_axi_arlock),\n      .s_axi_arlen(s_axi_arlen),\n      .s_axi_arqos(s_axi_arqos),\n      .s_axi_arregion(s_axi_arregion),\n      .s_axi_aruser(s_axi_aruser),\n      .s_axi_arid(s_axi_arid),\n      .s_axi_rdata(s_axi_rdata),\n      .s_axi_rresp(s_axi_rresp),\n      .s_axi_rvalid(s_axi_rvalid),\n      .s_axi_rready(s_axi_rready),\n      .s_axi_rlast(s_axi_rlast),\n      .s_axi_ruser(s_axi_ruser),\n      .s_axi_rid(s_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign m_axi_awid     = 0;\n     assign m_axi_awaddr   = 0;\n     assign m_axi_awlen    = 0;\n     assign m_axi_awsize   = 0;\n     assign m_axi_awburst  = 0;\n     assign m_axi_awlock   = 0;\n     assign m_axi_awcache  = 0;\n     assign m_axi_awprot   = 0;\n     assign m_axi_awregion = 0;\n     assign m_axi_awqos    = 0;\n     assign m_axi_awuser   = 0;\n     assign m_axi_awvalid  = 0;\n     assign m_axi_wid      = 0;\n     assign m_axi_wdata    = 0;\n     assign m_axi_wstrb    = 0;\n     assign m_axi_wlast    = 0;\n     assign m_axi_wuser    = 0;\n     assign m_axi_wvalid   = 0;\n     assign m_axi_bready   = 0;\n     assign m_axi_arid     = 0;\n     assign m_axi_araddr   = 0;\n     assign m_axi_arlen    = 0;\n     assign m_axi_arsize   = 0;\n     assign m_axi_arburst  = 0;\n     assign m_axi_arlock   = 0;\n     assign m_axi_arcache  = 0;\n     assign m_axi_arprot   = 0;\n     assign m_axi_arregion = 0;\n     assign m_axi_arqos    = 0;\n     assign m_axi_aruser   = 0;\n     assign m_axi_arvalid  = 0;\n     assign m_axi_rready   = 0;\n      \n  end else if (C_RESERVE_MODE==2) begin : gen_reserve_mi\n    \n    axi_register_slice_v2_1_22_test_master #(\n    .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n    .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .m_axi_awaddr(m_axi_awaddr),\n      .m_axi_awprot(m_axi_awprot),\n      .m_axi_awvalid(m_axi_awvalid),\n      .m_axi_awready(m_axi_awready),\n      .m_axi_awsize(m_axi_awsize),\n      .m_axi_awburst(m_axi_awburst),\n      .m_axi_awcache(m_axi_awcache),\n      .m_axi_awlen(m_axi_awlen),\n      .m_axi_awlock(m_axi_awlock),\n      .m_axi_awqos(m_axi_awqos),\n      .m_axi_awid(m_axi_awid),\n      .m_axi_awuser(m_axi_awuser),\n      .m_axi_wid(m_axi_wid),\n      .m_axi_wdata(m_axi_wdata),\n      .m_axi_wstrb(m_axi_wstrb),\n      .m_axi_wvalid(m_axi_wvalid),\n      .m_axi_wready(m_axi_wready),\n      .m_axi_wlast(m_axi_wlast),\n      .m_axi_wuser(m_axi_wuser),\n      .m_axi_bresp(m_axi_bresp),\n      .m_axi_bvalid(m_axi_bvalid),\n      .m_axi_bready(m_axi_bready),\n      .m_axi_buser(m_axi_buser),\n      .m_axi_bid(m_axi_bid),\n      .m_axi_araddr(m_axi_araddr),\n      .m_axi_arprot(m_axi_arprot),\n      .m_axi_arvalid(m_axi_arvalid),\n      .m_axi_arready(m_axi_arready),\n      .m_axi_arsize(m_axi_arsize),\n      .m_axi_arburst(m_axi_arburst),\n      .m_axi_arcache(m_axi_arcache),\n      .m_axi_arlen(m_axi_arlen),\n      .m_axi_arlock(m_axi_arlock),\n      .m_axi_arqos(m_axi_arqos),\n      .m_axi_arid(m_axi_arid),\n      .m_axi_aruser(m_axi_aruser),\n      .m_axi_rdata(m_axi_rdata),\n      .m_axi_rresp(m_axi_rresp),\n      .m_axi_rvalid(m_axi_rvalid),\n      .m_axi_rready(m_axi_rready),\n      .m_axi_rlast(m_axi_rlast),\n      .m_axi_ruser(m_axi_ruser),\n      .m_axi_rid(m_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign s_axi_awready = 0;\n     assign s_axi_wready  = 0;\n     assign s_axi_bid     = 0;\n     assign s_axi_bresp   = 0;\n     assign s_axi_buser   = 0;\n     assign s_axi_bvalid  = 0;\n     assign s_axi_arready = 0;\n     assign s_axi_rid     = 0;\n     assign s_axi_rdata   = 0;\n     assign s_axi_rresp   = 0;\n     assign s_axi_rlast   = 0;\n     assign s_axi_ruser   = 0;\n     assign s_axi_rvalid  = 0;\n\n  end else begin : gen_reg_slice  // Any normal reg-slice mode\n\n    axi_infrastructure_v1_1_0_axi2vector #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    axi2vector_0 ( \n      .s_axi_awid      ( s_axi_awid      ) ,\n      .s_axi_awaddr    ( s_axi_awaddr    ) ,\n      .s_axi_awlen     ( s_axi_awlen     ) ,\n      .s_axi_awsize    ( s_axi_awsize    ) ,\n      .s_axi_awburst   ( s_axi_awburst   ) ,\n      .s_axi_awlock    ( s_axi_awlock    ) ,\n      .s_axi_awcache   ( s_axi_awcache   ) ,\n      .s_axi_awprot    ( s_axi_awprot    ) ,\n      .s_axi_awqos     ( s_axi_awqos     ) ,\n      .s_axi_awuser    ( s_axi_awuser    ) ,\n      .s_axi_awregion  ( s_axi_awregion  ) ,\n      .s_axi_wid       ( s_axi_wid       ) ,\n      .s_axi_wdata     ( s_axi_wdata     ) ,\n      .s_axi_wstrb     ( s_axi_wstrb     ) ,\n      .s_axi_wlast     ( s_axi_wlast     ) ,\n      .s_axi_wuser     ( s_axi_wuser     ) ,\n      .s_axi_bid       ( s_axi_bid       ) ,\n      .s_axi_bresp     ( s_axi_bresp     ) ,\n      .s_axi_buser     ( s_axi_buser     ) ,\n      .s_axi_arid      ( s_axi_arid      ) ,\n      .s_axi_araddr    ( s_axi_araddr    ) ,\n      .s_axi_arlen     ( s_axi_arlen     ) ,\n      .s_axi_arsize    ( s_axi_arsize    ) ,\n      .s_axi_arburst   ( s_axi_arburst   ) ,\n      .s_axi_arlock    ( s_axi_arlock    ) ,\n      .s_axi_arcache   ( s_axi_arcache   ) ,\n      .s_axi_arprot    ( s_axi_arprot    ) ,\n      .s_axi_arqos     ( s_axi_arqos     ) ,\n      .s_axi_aruser    ( s_axi_aruser    ) ,\n      .s_axi_arregion  ( s_axi_arregion  ) ,\n      .s_axi_rid       ( s_axi_rid       ) ,\n      .s_axi_rdata     ( s_axi_rdata     ) ,\n      .s_axi_rresp     ( s_axi_rresp     ) ,\n      .s_axi_rlast     ( s_axi_rlast     ) ,\n      .s_axi_ruser     ( s_axi_ruser     ) ,\n      .s_awpayload ( s_awpayload ) ,\n      .s_wpayload  ( s_wpayload  ) ,\n      .s_bpayload  ( s_bpayload  ) ,\n      .s_arpayload ( s_arpayload ) ,\n      .s_rpayload  ( s_rpayload  ) \n    );\n    \n    axi_infrastructure_v1_1_0_vector2axi #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    vector2axi_0 ( \n      .m_awpayload    ( m_awpayload    ) ,\n      .m_wpayload     ( m_wpayload     ) ,\n      .m_bpayload     ( m_bpayload     ) ,\n      .m_arpayload    ( m_arpayload    ) ,\n      .m_rpayload     ( m_rpayload     ) ,\n      .m_axi_awid     ( m_axi_awid     ) ,\n      .m_axi_awaddr   ( m_axi_awaddr   ) ,\n      .m_axi_awlen    ( m_axi_awlen    ) ,\n      .m_axi_awsize   ( m_axi_awsize   ) ,\n      .m_axi_awburst  ( m_axi_awburst  ) ,\n      .m_axi_awlock   ( m_axi_awlock   ) ,\n      .m_axi_awcache  ( m_axi_awcache  ) ,\n      .m_axi_awprot   ( m_axi_awprot   ) ,\n      .m_axi_awqos    ( m_axi_awqos    ) ,\n      .m_axi_awuser   ( m_axi_awuser   ) ,\n      .m_axi_awregion ( m_axi_awregion ) ,\n      .m_axi_wid      ( m_axi_wid      ) ,\n      .m_axi_wdata    ( m_axi_wdata    ) ,\n      .m_axi_wstrb    ( m_axi_wstrb    ) ,\n      .m_axi_wlast    ( m_axi_wlast    ) ,\n      .m_axi_wuser    ( m_axi_wuser    ) ,\n      .m_axi_bid      ( m_axi_bid      ) ,\n      .m_axi_bresp    ( m_axi_bresp    ) ,\n      .m_axi_buser    ( m_axi_buser    ) ,\n      .m_axi_arid     ( m_axi_arid     ) ,\n      .m_axi_araddr   ( m_axi_araddr   ) ,\n      .m_axi_arlen    ( m_axi_arlen    ) ,\n      .m_axi_arsize   ( m_axi_arsize   ) ,\n      .m_axi_arburst  ( m_axi_arburst  ) ,\n      .m_axi_arlock   ( m_axi_arlock   ) ,\n      .m_axi_arcache  ( m_axi_arcache  ) ,\n      .m_axi_arprot   ( m_axi_arprot   ) ,\n      .m_axi_arqos    ( m_axi_arqos    ) ,\n      .m_axi_aruser   ( m_axi_aruser   ) ,\n      .m_axi_arregion ( m_axi_arregion ) ,\n      .m_axi_rid      ( m_axi_rid      ) ,\n      .m_axi_rdata    ( m_axi_rdata    ) ,\n      .m_axi_rresp    ( m_axi_rresp    ) ,\n      .m_axi_rlast    ( m_axi_rlast    ) ,\n      .m_axi_ruser    ( m_axi_ruser    ) \n    );\n    \n  end  // Reserve SI/MI branch\n\n  if ((C_REG_CONFIG_AW <= 9) && (C_RESERVE_MODE==0)) begin : aw\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 15) && (C_RESERVE_MODE==0)) begin : aw15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 16) && (C_RESERVE_MODE==0)) begin : aw16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) \n    )\n    aw_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if ((C_REG_CONFIG_W <= 9) && (C_RESERVE_MODE==0)) begin : w\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 15) && (C_RESERVE_MODE==0)) begin : w15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 16) && (C_RESERVE_MODE==0)) begin : w16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) \n    )\n    w_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if ((C_REG_CONFIG_B <= 9) && (C_RESERVE_MODE==0)) begin : b\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if ((C_REG_CONFIG_B == 15) && (C_RESERVE_MODE==0)) begin : b15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if ((C_REG_CONFIG_B == 16) && (C_RESERVE_MODE==0)) begin : b16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) \n    )\n    b_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if ((C_REG_CONFIG_AR <= 9) && (C_RESERVE_MODE==0)) begin : ar\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 15) && (C_RESERVE_MODE==0)) begin : ar15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 16) && (C_RESERVE_MODE==0)) begin : ar16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) \n    )\n    ar_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if ((C_REG_CONFIG_R <= 9) && (C_RESERVE_MODE==0)) begin : r\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 15) && (C_RESERVE_MODE==0)) begin : r15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 16) && (C_RESERVE_MODE==0)) begin : r16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) \n    )\n    r_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 4844}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m01_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m02_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_m03_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [6 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [6 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [6 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [6 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [6 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [6 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [6 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [6 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THR\\\nEADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(7'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_s00_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_register_slice:2.1\n// IP Revision: 22\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_s01_regslice_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awregion,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arregion,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWID\" *)\ninput wire [5 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWADDR\" *)\ninput wire [63 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLEN\" *)\ninput wire [7 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWSIZE\" *)\ninput wire [2 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWBURST\" *)\ninput wire [1 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWLOCK\" *)\ninput wire [0 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWCACHE\" *)\ninput wire [3 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWPROT\" *)\ninput wire [2 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREGION\" *)\ninput wire [3 : 0] s_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWQOS\" *)\ninput wire [3 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWVALID\" *)\ninput wire s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI AWREADY\" *)\noutput wire s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WDATA\" *)\ninput wire [511 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WSTRB\" *)\ninput wire [63 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WLAST\" *)\ninput wire s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WVALID\" *)\ninput wire s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI WREADY\" *)\noutput wire s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BID\" *)\noutput wire [5 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BRESP\" *)\noutput wire [1 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BVALID\" *)\noutput wire s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI BREADY\" *)\ninput wire s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARID\" *)\ninput wire [5 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARADDR\" *)\ninput wire [63 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLEN\" *)\ninput wire [7 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARSIZE\" *)\ninput wire [2 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARBURST\" *)\ninput wire [1 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARLOCK\" *)\ninput wire [0 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARCACHE\" *)\ninput wire [3 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARPROT\" *)\ninput wire [2 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREGION\" *)\ninput wire [3 : 0] s_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARQOS\" *)\ninput wire [3 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARVALID\" *)\ninput wire s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI ARREADY\" *)\noutput wire s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RID\" *)\noutput wire [5 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RDATA\" *)\noutput wire [511 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RRESP\" *)\noutput wire [1 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RLAST\" *)\noutput wire s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RVALID\" *)\noutput wire s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S_AXI RREADY\" *)\ninput wire s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWID\" *)\noutput wire [5 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWADDR\" *)\noutput wire [63 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLEN\" *)\noutput wire [7 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWSIZE\" *)\noutput wire [2 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWBURST\" *)\noutput wire [1 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWLOCK\" *)\noutput wire [0 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWCACHE\" *)\noutput wire [3 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWPROT\" *)\noutput wire [2 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREGION\" *)\noutput wire [3 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWQOS\" *)\noutput wire [3 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWVALID\" *)\noutput wire m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI AWREADY\" *)\ninput wire m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WDATA\" *)\noutput wire [511 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WSTRB\" *)\noutput wire [63 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WLAST\" *)\noutput wire m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WVALID\" *)\noutput wire m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI WREADY\" *)\ninput wire m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BID\" *)\ninput wire [5 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BRESP\" *)\ninput wire [1 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BVALID\" *)\ninput wire m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI BREADY\" *)\noutput wire m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARID\" *)\noutput wire [5 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARADDR\" *)\noutput wire [63 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLEN\" *)\noutput wire [7 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARSIZE\" *)\noutput wire [2 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARBURST\" *)\noutput wire [1 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARLOCK\" *)\noutput wire [0 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARCACHE\" *)\noutput wire [3 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARPROT\" *)\noutput wire [2 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREGION\" *)\noutput wire [3 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARQOS\" *)\noutput wire [3 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARVALID\" *)\noutput wire m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI ARREADY\" *)\ninput wire m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RID\" *)\ninput wire [5 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RDATA\" *)\ninput wire [511 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RRESP\" *)\ninput wire [1 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RLAST\" *)\ninput wire m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RVALID\" *)\ninput wire m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 6, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_TH\\\nREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M_AXI RREADY\" *)\noutput wire m_axi_rready;\n\n  axi_register_slice_v2_1_22_axi_register_slice #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_AXI_PROTOCOL(0),\n    .C_AXI_ID_WIDTH(6),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_REG_CONFIG_AW(7),\n    .C_REG_CONFIG_W(1),\n    .C_REG_CONFIG_B(7),\n    .C_REG_CONFIG_AR(7),\n    .C_REG_CONFIG_R(1),\n    .C_RESERVE_MODE(0),\n    .C_NUM_SLR_CROSSINGS(0),\n    .C_PIPELINES_MASTER_AW(0),\n    .C_PIPELINES_MASTER_W(0),\n    .C_PIPELINES_MASTER_B(0),\n    .C_PIPELINES_MASTER_AR(0),\n    .C_PIPELINES_MASTER_R(0),\n    .C_PIPELINES_SLAVE_AW(0),\n    .C_PIPELINES_SLAVE_W(0),\n    .C_PIPELINES_SLAVE_B(0),\n    .C_PIPELINES_SLAVE_AR(0),\n    .C_PIPELINES_SLAVE_R(0),\n    .C_PIPELINES_MIDDLE_AW(0),\n    .C_PIPELINES_MIDDLE_W(0),\n    .C_PIPELINES_MIDDLE_B(0),\n    .C_PIPELINES_MIDDLE_AR(0),\n    .C_PIPELINES_MIDDLE_R(0)\n  ) inst (\n    .aclk(aclk),\n    .aclk2x(1'B0),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awregion(s_axi_awregion),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(1'B0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(6'B0),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(1'B0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arregion(s_axi_arregion),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(1'B0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(1'B0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(1'B0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 436}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:axi_crossbar:2.1\n// IP Revision: 23\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule cl_axi_interconnect_xbar_0 (\n  aclk,\n  aresetn,\n  s_axi_awid,\n  s_axi_awaddr,\n  s_axi_awlen,\n  s_axi_awsize,\n  s_axi_awburst,\n  s_axi_awlock,\n  s_axi_awcache,\n  s_axi_awprot,\n  s_axi_awqos,\n  s_axi_awvalid,\n  s_axi_awready,\n  s_axi_wdata,\n  s_axi_wstrb,\n  s_axi_wlast,\n  s_axi_wvalid,\n  s_axi_wready,\n  s_axi_bid,\n  s_axi_bresp,\n  s_axi_bvalid,\n  s_axi_bready,\n  s_axi_arid,\n  s_axi_araddr,\n  s_axi_arlen,\n  s_axi_arsize,\n  s_axi_arburst,\n  s_axi_arlock,\n  s_axi_arcache,\n  s_axi_arprot,\n  s_axi_arqos,\n  s_axi_arvalid,\n  s_axi_arready,\n  s_axi_rid,\n  s_axi_rdata,\n  s_axi_rresp,\n  s_axi_rlast,\n  s_axi_rvalid,\n  s_axi_rready,\n  m_axi_awid,\n  m_axi_awaddr,\n  m_axi_awlen,\n  m_axi_awsize,\n  m_axi_awburst,\n  m_axi_awlock,\n  m_axi_awcache,\n  m_axi_awprot,\n  m_axi_awregion,\n  m_axi_awqos,\n  m_axi_awvalid,\n  m_axi_awready,\n  m_axi_wdata,\n  m_axi_wstrb,\n  m_axi_wlast,\n  m_axi_wvalid,\n  m_axi_wready,\n  m_axi_bid,\n  m_axi_bresp,\n  m_axi_bvalid,\n  m_axi_bready,\n  m_axi_arid,\n  m_axi_araddr,\n  m_axi_arlen,\n  m_axi_arsize,\n  m_axi_arburst,\n  m_axi_arlock,\n  m_axi_arcache,\n  m_axi_arprot,\n  m_axi_arregion,\n  m_axi_arqos,\n  m_axi_arvalid,\n  m_axi_arready,\n  m_axi_rid,\n  m_axi_rdata,\n  m_axi_rresp,\n  m_axi_rlast,\n  m_axi_rvalid,\n  m_axi_rready\n);\n\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLKIF, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLKIF CLK\" *)\ninput wire aclk;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RSTIF RST\" *)\ninput wire aresetn;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [6:0] [13:7]\" *)\ninput wire [13 : 0] s_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]\" *)\ninput wire [15 : 0] s_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]\" *)\ninput wire [3 : 0] s_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [511:0] [1023:512]\" *)\ninput wire [1023 : 0] s_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [6:0] [13:7]\" *)\noutput wire [13 : 0] s_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]\" *)\noutput wire [3 : 0] s_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [6:0] [13:7]\" *)\ninput wire [13 : 0] s_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [63:0] [127:64]\" *)\ninput wire [127 : 0] s_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]\" *)\ninput wire [15 : 0] s_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]\" *)\ninput wire [3 : 0] s_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]\" *)\ninput wire [5 : 0] s_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]\" *)\ninput wire [7 : 0] s_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RID [6:0] [6:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [6:0] [13:7]\" *)\noutput wire [13 : 0] s_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [511:0] [1023:512]\" *)\noutput wire [1023 : 0] s_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]\" *)\noutput wire [3 : 0] s_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]\" *)\noutput wire [1 : 0] s_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_\\\nTHREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME S01_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0\\\n00, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 16, NUM_WRITE_THREADS 16, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]\" *)\ninput wire [1 : 0] s_axi_rready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI AWID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI AWID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI AWID [6:0] [27:21]\" *)\noutput wire [27 : 0] m_axi_awid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_awaddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI AWLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI AWLEN [7:0] [31:24]\" *)\noutput wire [31 : 0] m_axi_awlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_awsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI AWBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI AWBURST [1:0] [7:6]\" *)\noutput wire [7 : 0] m_axi_awburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_awlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_awprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWREGION [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWQOS [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_awqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_awvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_awready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [511:0] [1023:512], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [511:0] [1535:1024], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [511:0] [2047:1536]\" *)\noutput wire [2047 : 0] m_axi_wdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_wstrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WLAST [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_wlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_wvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_wready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI BID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI BID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI BID [6:0] [27:21]\" *)\ninput wire [27 : 0] m_axi_bid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]\" *)\ninput wire [7 : 0] m_axi_bresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_bvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_bready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI ARID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI ARID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI ARID [6:0] [27:21]\" *)\noutput wire [27 : 0] m_axi_arid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [63:0] [127:64], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [63:0] [191:128], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [63:0] [255:192]\" *)\noutput wire [255 : 0] m_axi_araddr;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI ARLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI ARLEN [7:0] [31:24]\" *)\noutput wire [31 : 0] m_axi_arlen;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_arsize;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI ARBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI ARBURST [1:0] [7:6]\" *)\noutput wire [7 : 0] m_axi_arburst;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_arlock;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arcache;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]\" *)\noutput wire [11 : 0] m_axi_arprot;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARREGION [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arregion;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARQOS [3:0] [15:12]\" *)\noutput wire [15 : 0] m_axi_arqos;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_arvalid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_arready;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RID [6:0] [6:0], xilinx.com:interface:aximm:1.0 M01_AXI RID [6:0] [13:7], xilinx.com:interface:aximm:1.0 M02_AXI RID [6:0] [20:14], xilinx.com:interface:aximm:1.0 M03_AXI RID [6:0] [27:21]\" *)\ninput wire [27 : 0] m_axi_rid;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RDATA [511:0] [511:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [511:0] [1023:512], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [511:0] [1535:1024], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [511:0] [2047:1536]\" *)\ninput wire [2047 : 0] m_axi_rdata;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]\" *)\ninput wire [7 : 0] m_axi_rresp;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RLAST [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_rlast;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]\" *)\ninput wire [3 : 0] m_axi_rvalid;\n(* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE\\\n_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0\\\n.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ\\\n_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 250000000, ID_WIDTH 7, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, \\\nHAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN cl_axi_interconnect_ACLK, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0\" *)\n(* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]\" *)\noutput wire [3 : 0] m_axi_rready;\n\n  axi_crossbar_v2_1_23_axi_crossbar #(\n    .C_FAMILY(\"virtexuplus\"),\n    .C_NUM_SLAVE_SLOTS(2),\n    .C_NUM_MASTER_SLOTS(4),\n    .C_AXI_ID_WIDTH(7),\n    .C_AXI_ADDR_WIDTH(64),\n    .C_AXI_DATA_WIDTH(512),\n    .C_AXI_PROTOCOL(0),\n    .C_NUM_ADDR_RANGES(1),\n    .C_M_AXI_BASE_ADDR(256'H0000000c00000000000000080000000000000004000000000000000000000000),\n    .C_M_AXI_ADDR_WIDTH(128'H00000022000000220000002200000022),\n    .C_S_AXI_BASE_ID(64'H0000004000000000),\n    .C_S_AXI_THREAD_ID_WIDTH(64'H0000000600000006),\n    .C_AXI_SUPPORTS_USER_SIGNALS(0),\n    .C_AXI_AWUSER_WIDTH(1),\n    .C_AXI_ARUSER_WIDTH(1),\n    .C_AXI_WUSER_WIDTH(1),\n    .C_AXI_RUSER_WIDTH(1),\n    .C_AXI_BUSER_WIDTH(1),\n    .C_M_AXI_WRITE_CONNECTIVITY(128'H00000003000000030000000300000003),\n    .C_M_AXI_READ_CONNECTIVITY(128'H00000003000000030000000300000003),\n    .C_R_REGISTER(0),\n    .C_S_AXI_SINGLE_THREAD(64'H0000000000000000),\n    .C_S_AXI_WRITE_ACCEPTANCE(64'H0000002000000020),\n    .C_S_AXI_READ_ACCEPTANCE(64'H0000002000000020),\n    .C_M_AXI_WRITE_ISSUING(128'H00000010000000100000001000000010),\n    .C_M_AXI_READ_ISSUING(128'H00000010000000100000001000000010),\n    .C_S_AXI_ARB_PRIORITY(64'H0000000000000000),\n    .C_M_AXI_SECURE(128'H00000000000000000000000000000000),\n    .C_CONNECTIVITY_MODE(1)\n  ) inst (\n    .aclk(aclk),\n    .aresetn(aresetn),\n    .s_axi_awid(s_axi_awid),\n    .s_axi_awaddr(s_axi_awaddr),\n    .s_axi_awlen(s_axi_awlen),\n    .s_axi_awsize(s_axi_awsize),\n    .s_axi_awburst(s_axi_awburst),\n    .s_axi_awlock(s_axi_awlock),\n    .s_axi_awcache(s_axi_awcache),\n    .s_axi_awprot(s_axi_awprot),\n    .s_axi_awqos(s_axi_awqos),\n    .s_axi_awuser(2'H0),\n    .s_axi_awvalid(s_axi_awvalid),\n    .s_axi_awready(s_axi_awready),\n    .s_axi_wid(14'H0000),\n    .s_axi_wdata(s_axi_wdata),\n    .s_axi_wstrb(s_axi_wstrb),\n    .s_axi_wlast(s_axi_wlast),\n    .s_axi_wuser(2'H0),\n    .s_axi_wvalid(s_axi_wvalid),\n    .s_axi_wready(s_axi_wready),\n    .s_axi_bid(s_axi_bid),\n    .s_axi_bresp(s_axi_bresp),\n    .s_axi_buser(),\n    .s_axi_bvalid(s_axi_bvalid),\n    .s_axi_bready(s_axi_bready),\n    .s_axi_arid(s_axi_arid),\n    .s_axi_araddr(s_axi_araddr),\n    .s_axi_arlen(s_axi_arlen),\n    .s_axi_arsize(s_axi_arsize),\n    .s_axi_arburst(s_axi_arburst),\n    .s_axi_arlock(s_axi_arlock),\n    .s_axi_arcache(s_axi_arcache),\n    .s_axi_arprot(s_axi_arprot),\n    .s_axi_arqos(s_axi_arqos),\n    .s_axi_aruser(2'H0),\n    .s_axi_arvalid(s_axi_arvalid),\n    .s_axi_arready(s_axi_arready),\n    .s_axi_rid(s_axi_rid),\n    .s_axi_rdata(s_axi_rdata),\n    .s_axi_rresp(s_axi_rresp),\n    .s_axi_rlast(s_axi_rlast),\n    .s_axi_ruser(),\n    .s_axi_rvalid(s_axi_rvalid),\n    .s_axi_rready(s_axi_rready),\n    .m_axi_awid(m_axi_awid),\n    .m_axi_awaddr(m_axi_awaddr),\n    .m_axi_awlen(m_axi_awlen),\n    .m_axi_awsize(m_axi_awsize),\n    .m_axi_awburst(m_axi_awburst),\n    .m_axi_awlock(m_axi_awlock),\n    .m_axi_awcache(m_axi_awcache),\n    .m_axi_awprot(m_axi_awprot),\n    .m_axi_awregion(m_axi_awregion),\n    .m_axi_awqos(m_axi_awqos),\n    .m_axi_awuser(),\n    .m_axi_awvalid(m_axi_awvalid),\n    .m_axi_awready(m_axi_awready),\n    .m_axi_wid(),\n    .m_axi_wdata(m_axi_wdata),\n    .m_axi_wstrb(m_axi_wstrb),\n    .m_axi_wlast(m_axi_wlast),\n    .m_axi_wuser(),\n    .m_axi_wvalid(m_axi_wvalid),\n    .m_axi_wready(m_axi_wready),\n    .m_axi_bid(m_axi_bid),\n    .m_axi_bresp(m_axi_bresp),\n    .m_axi_buser(4'H0),\n    .m_axi_bvalid(m_axi_bvalid),\n    .m_axi_bready(m_axi_bready),\n    .m_axi_arid(m_axi_arid),\n    .m_axi_araddr(m_axi_araddr),\n    .m_axi_arlen(m_axi_arlen),\n    .m_axi_arsize(m_axi_arsize),\n    .m_axi_arburst(m_axi_arburst),\n    .m_axi_arlock(m_axi_arlock),\n    .m_axi_arcache(m_axi_arcache),\n    .m_axi_arprot(m_axi_arprot),\n    .m_axi_arregion(m_axi_arregion),\n    .m_axi_arqos(m_axi_arqos),\n    .m_axi_aruser(),\n    .m_axi_arvalid(m_axi_arvalid),\n    .m_axi_arready(m_axi_arready),\n    .m_axi_rid(m_axi_rid),\n    .m_axi_rdata(m_axi_rdata),\n    .m_axi_rresp(m_axi_rresp),\n    .m_axi_rlast(m_axi_rlast),\n    .m_axi_ruser(4'H0),\n    .m_axi_rvalid(m_axi_rvalid),\n    .m_axi_rready(m_axi_rready)\n  );\nendmodule\n", "num_lines": 427}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n//--------------------------------------------------------------------------------\n//Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020\n//Date        : Wed Dec 15 00:42:21 2021\n//Host        : a-21awsprq4sria running 64-bit Amazon Linux release 2 (Karoo)\n//Command     : generate_target cl_axi_interconnect.bd\n//Design      : cl_axi_interconnect\n//Purpose     : IP block netlist\n//--------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CORE_GENERATION_INFO = \"cl_axi_interconnect,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=cl_axi_interconnect,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=14,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}\" *) (* HW_HANDOFF = \"cl_axi_interconnect.hwdef\" *) \nmodule cl_axi_interconnect\n   (ACLK,\n    ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:clock:1.0 CLK.ACLK CLK\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF S00_AXI:M00_AXI:M01_AXI:M02_AXI:M03_AXI:S01_AXI, ASSOCIATED_RESET ARESETN, CLK_DOMAIN cl_axi_interconnect_ACLK, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000\" *) input ACLK;\n  (* X_INTERFACE_INFO = \"xilinx.com:signal:reset:1.0 RST.ARESETN RST\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW\" *) input ARESETN;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M00_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M00_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARBURST\" *) output [1:0]M00_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE\" *) output [3:0]M00_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARID\" *) output [6:0]M00_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLEN\" *) output [7:0]M00_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK\" *) output [0:0]M00_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARPROT\" *) output [2:0]M00_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARQOS\" *) output [3:0]M00_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREADY\" *) input M00_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARREGION\" *) output [3:0]M00_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE\" *) output [2:0]M00_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI ARVALID\" *) output M00_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWADDR\" *) output [63:0]M00_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWBURST\" *) output [1:0]M00_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE\" *) output [3:0]M00_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWID\" *) output [6:0]M00_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLEN\" *) output [7:0]M00_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK\" *) output [0:0]M00_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWPROT\" *) output [2:0]M00_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWQOS\" *) output [3:0]M00_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREADY\" *) input M00_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWREGION\" *) output [3:0]M00_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE\" *) output [2:0]M00_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI AWVALID\" *) output M00_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BID\" *) input [6:0]M00_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BREADY\" *) output M00_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BRESP\" *) input [1:0]M00_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI BVALID\" *) input M00_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RDATA\" *) input [511:0]M00_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RID\" *) input [6:0]M00_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RLAST\" *) input M00_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RREADY\" *) output M00_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RRESP\" *) input [1:0]M00_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI RVALID\" *) input M00_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WDATA\" *) output [511:0]M00_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WLAST\" *) output M00_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WREADY\" *) input M00_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WSTRB\" *) output [63:0]M00_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M00_AXI WVALID\" *) output M00_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M01_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M01_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARBURST\" *) output [1:0]M01_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE\" *) output [3:0]M01_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARID\" *) output [6:0]M01_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARLEN\" *) output [7:0]M01_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK\" *) output [0:0]M01_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARPROT\" *) output [2:0]M01_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARQOS\" *) output [3:0]M01_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARREADY\" *) input M01_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARREGION\" *) output [3:0]M01_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE\" *) output [2:0]M01_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI ARVALID\" *) output M01_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWADDR\" *) output [63:0]M01_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWBURST\" *) output [1:0]M01_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE\" *) output [3:0]M01_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWID\" *) output [6:0]M01_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWLEN\" *) output [7:0]M01_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK\" *) output [0:0]M01_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWPROT\" *) output [2:0]M01_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWQOS\" *) output [3:0]M01_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWREADY\" *) input M01_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWREGION\" *) output [3:0]M01_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE\" *) output [2:0]M01_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI AWVALID\" *) output M01_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BID\" *) input [6:0]M01_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BREADY\" *) output M01_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BRESP\" *) input [1:0]M01_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI BVALID\" *) input M01_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RDATA\" *) input [511:0]M01_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RID\" *) input [6:0]M01_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RLAST\" *) input M01_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RREADY\" *) output M01_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RRESP\" *) input [1:0]M01_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI RVALID\" *) input M01_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WDATA\" *) output [511:0]M01_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WLAST\" *) output M01_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WREADY\" *) input M01_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WSTRB\" *) output [63:0]M01_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M01_AXI WVALID\" *) output M01_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M02_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M02_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARBURST\" *) output [1:0]M02_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE\" *) output [3:0]M02_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARID\" *) output [6:0]M02_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARLEN\" *) output [7:0]M02_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK\" *) output [0:0]M02_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARPROT\" *) output [2:0]M02_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARQOS\" *) output [3:0]M02_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARREADY\" *) input M02_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARREGION\" *) output [3:0]M02_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE\" *) output [2:0]M02_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI ARVALID\" *) output M02_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWADDR\" *) output [63:0]M02_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWBURST\" *) output [1:0]M02_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE\" *) output [3:0]M02_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWID\" *) output [6:0]M02_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWLEN\" *) output [7:0]M02_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK\" *) output [0:0]M02_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWPROT\" *) output [2:0]M02_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWQOS\" *) output [3:0]M02_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWREADY\" *) input M02_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWREGION\" *) output [3:0]M02_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE\" *) output [2:0]M02_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI AWVALID\" *) output M02_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BID\" *) input [6:0]M02_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BREADY\" *) output M02_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BRESP\" *) input [1:0]M02_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI BVALID\" *) input M02_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RDATA\" *) input [511:0]M02_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RID\" *) input [6:0]M02_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RLAST\" *) input M02_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RREADY\" *) output M02_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RRESP\" *) input [1:0]M02_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI RVALID\" *) input M02_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WDATA\" *) output [511:0]M02_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WLAST\" *) output M02_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WREADY\" *) input M02_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WSTRB\" *) output [63:0]M02_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M02_AXI WVALID\" *) output M02_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME M03_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 7, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) output [63:0]M03_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARBURST\" *) output [1:0]M03_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE\" *) output [3:0]M03_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARID\" *) output [6:0]M03_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARLEN\" *) output [7:0]M03_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK\" *) output [0:0]M03_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARPROT\" *) output [2:0]M03_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARQOS\" *) output [3:0]M03_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARREADY\" *) input M03_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARREGION\" *) output [3:0]M03_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE\" *) output [2:0]M03_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI ARVALID\" *) output M03_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWADDR\" *) output [63:0]M03_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWBURST\" *) output [1:0]M03_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE\" *) output [3:0]M03_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWID\" *) output [6:0]M03_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWLEN\" *) output [7:0]M03_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK\" *) output [0:0]M03_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWPROT\" *) output [2:0]M03_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWQOS\" *) output [3:0]M03_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWREADY\" *) input M03_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWREGION\" *) output [3:0]M03_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE\" *) output [2:0]M03_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI AWVALID\" *) output M03_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BID\" *) input [6:0]M03_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BREADY\" *) output M03_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BRESP\" *) input [1:0]M03_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI BVALID\" *) input M03_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RDATA\" *) input [511:0]M03_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RID\" *) input [6:0]M03_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RLAST\" *) input M03_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RREADY\" *) output M03_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RRESP\" *) input [1:0]M03_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI RVALID\" *) input M03_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WDATA\" *) output [511:0]M03_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WLAST\" *) output M03_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WREADY\" *) input M03_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WSTRB\" *) output [63:0]M03_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 M03_AXI WVALID\" *) output M03_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S00_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 6, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 32, NUM_READ_THREADS 16, NUM_WRITE_OUTSTANDING 32, NUM_WRITE_THREADS 16, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) input [63:0]S00_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARBURST\" *) input [1:0]S00_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE\" *) input [3:0]S00_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARID\" *) input [5:0]S00_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLEN\" *) input [7:0]S00_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK\" *) input [0:0]S00_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARPROT\" *) input [2:0]S00_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARQOS\" *) input [3:0]S00_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREADY\" *) output S00_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARREGION\" *) input [3:0]S00_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE\" *) input [2:0]S00_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI ARVALID\" *) input S00_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWADDR\" *) input [63:0]S00_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWBURST\" *) input [1:0]S00_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE\" *) input [3:0]S00_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWID\" *) input [5:0]S00_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLEN\" *) input [7:0]S00_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK\" *) input [0:0]S00_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWPROT\" *) input [2:0]S00_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWQOS\" *) input [3:0]S00_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREADY\" *) output S00_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWREGION\" *) input [3:0]S00_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE\" *) input [2:0]S00_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI AWVALID\" *) input S00_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BID\" *) output [5:0]S00_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BREADY\" *) input S00_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BRESP\" *) output [1:0]S00_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI BVALID\" *) output S00_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RDATA\" *) output [511:0]S00_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RID\" *) output [5:0]S00_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RLAST\" *) output S00_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RREADY\" *) input S00_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RRESP\" *) output [1:0]S00_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI RVALID\" *) output S00_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WDATA\" *) input [511:0]S00_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WLAST\" *) input S00_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WREADY\" *) output S00_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WSTRB\" *) input [63:0]S00_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S00_AXI WVALID\" *) input S00_AXI_wvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARADDR\" *) (* X_INTERFACE_PARAMETER = \"XIL_INTERFACENAME S01_AXI, ADDR_WIDTH 64, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN cl_axi_interconnect_ACLK, DATA_WIDTH 512, FREQ_HZ 250000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 6, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 32, NUM_READ_THREADS 16, NUM_WRITE_OUTSTANDING 32, NUM_WRITE_THREADS 16, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0\" *) input [63:0]S01_AXI_araddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARBURST\" *) input [1:0]S01_AXI_arburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE\" *) input [3:0]S01_AXI_arcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARID\" *) input [5:0]S01_AXI_arid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARLEN\" *) input [7:0]S01_AXI_arlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK\" *) input [0:0]S01_AXI_arlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARPROT\" *) input [2:0]S01_AXI_arprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARQOS\" *) input [3:0]S01_AXI_arqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARREADY\" *) output S01_AXI_arready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARREGION\" *) input [3:0]S01_AXI_arregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE\" *) input [2:0]S01_AXI_arsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI ARVALID\" *) input S01_AXI_arvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWADDR\" *) input [63:0]S01_AXI_awaddr;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWBURST\" *) input [1:0]S01_AXI_awburst;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE\" *) input [3:0]S01_AXI_awcache;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWID\" *) input [5:0]S01_AXI_awid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWLEN\" *) input [7:0]S01_AXI_awlen;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK\" *) input [0:0]S01_AXI_awlock;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWPROT\" *) input [2:0]S01_AXI_awprot;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWQOS\" *) input [3:0]S01_AXI_awqos;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWREADY\" *) output S01_AXI_awready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWREGION\" *) input [3:0]S01_AXI_awregion;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE\" *) input [2:0]S01_AXI_awsize;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI AWVALID\" *) input S01_AXI_awvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BID\" *) output [5:0]S01_AXI_bid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BREADY\" *) input S01_AXI_bready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BRESP\" *) output [1:0]S01_AXI_bresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI BVALID\" *) output S01_AXI_bvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RDATA\" *) output [511:0]S01_AXI_rdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RID\" *) output [5:0]S01_AXI_rid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RLAST\" *) output S01_AXI_rlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RREADY\" *) input S01_AXI_rready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RRESP\" *) output [1:0]S01_AXI_rresp;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI RVALID\" *) output S01_AXI_rvalid;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WDATA\" *) input [511:0]S01_AXI_wdata;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WLAST\" *) input S01_AXI_wlast;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WREADY\" *) output S01_AXI_wready;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WSTRB\" *) input [63:0]S01_AXI_wstrb;\n  (* X_INTERFACE_INFO = \"xilinx.com:interface:aximm:1.0 S01_AXI WVALID\" *) input S01_AXI_wvalid;\n\n  wire ACLK_1;\n  wire ARESETN_1;\n  wire [63:0]S00_AXI_1_ARADDR;\n  wire [1:0]S00_AXI_1_ARBURST;\n  wire [3:0]S00_AXI_1_ARCACHE;\n  wire [5:0]S00_AXI_1_ARID;\n  wire [7:0]S00_AXI_1_ARLEN;\n  wire [0:0]S00_AXI_1_ARLOCK;\n  wire [2:0]S00_AXI_1_ARPROT;\n  wire [3:0]S00_AXI_1_ARQOS;\n  wire S00_AXI_1_ARREADY;\n  wire [3:0]S00_AXI_1_ARREGION;\n  wire [2:0]S00_AXI_1_ARSIZE;\n  wire S00_AXI_1_ARVALID;\n  wire [63:0]S00_AXI_1_AWADDR;\n  wire [1:0]S00_AXI_1_AWBURST;\n  wire [3:0]S00_AXI_1_AWCACHE;\n  wire [5:0]S00_AXI_1_AWID;\n  wire [7:0]S00_AXI_1_AWLEN;\n  wire [0:0]S00_AXI_1_AWLOCK;\n  wire [2:0]S00_AXI_1_AWPROT;\n  wire [3:0]S00_AXI_1_AWQOS;\n  wire S00_AXI_1_AWREADY;\n  wire [3:0]S00_AXI_1_AWREGION;\n  wire [2:0]S00_AXI_1_AWSIZE;\n  wire S00_AXI_1_AWVALID;\n  wire [5:0]S00_AXI_1_BID;\n  wire S00_AXI_1_BREADY;\n  wire [1:0]S00_AXI_1_BRESP;\n  wire S00_AXI_1_BVALID;\n  wire [511:0]S00_AXI_1_RDATA;\n  wire [5:0]S00_AXI_1_RID;\n  wire S00_AXI_1_RLAST;\n  wire S00_AXI_1_RREADY;\n  wire [1:0]S00_AXI_1_RRESP;\n  wire S00_AXI_1_RVALID;\n  wire [511:0]S00_AXI_1_WDATA;\n  wire S00_AXI_1_WLAST;\n  wire S00_AXI_1_WREADY;\n  wire [63:0]S00_AXI_1_WSTRB;\n  wire S00_AXI_1_WVALID;\n  wire [63:0]S01_AXI_1_ARADDR;\n  wire [1:0]S01_AXI_1_ARBURST;\n  wire [3:0]S01_AXI_1_ARCACHE;\n  wire [5:0]S01_AXI_1_ARID;\n  wire [7:0]S01_AXI_1_ARLEN;\n  wire [0:0]S01_AXI_1_ARLOCK;\n  wire [2:0]S01_AXI_1_ARPROT;\n  wire [3:0]S01_AXI_1_ARQOS;\n  wire S01_AXI_1_ARREADY;\n  wire [3:0]S01_AXI_1_ARREGION;\n  wire [2:0]S01_AXI_1_ARSIZE;\n  wire S01_AXI_1_ARVALID;\n  wire [63:0]S01_AXI_1_AWADDR;\n  wire [1:0]S01_AXI_1_AWBURST;\n  wire [3:0]S01_AXI_1_AWCACHE;\n  wire [5:0]S01_AXI_1_AWID;\n  wire [7:0]S01_AXI_1_AWLEN;\n  wire [0:0]S01_AXI_1_AWLOCK;\n  wire [2:0]S01_AXI_1_AWPROT;\n  wire [3:0]S01_AXI_1_AWQOS;\n  wire S01_AXI_1_AWREADY;\n  wire [3:0]S01_AXI_1_AWREGION;\n  wire [2:0]S01_AXI_1_AWSIZE;\n  wire S01_AXI_1_AWVALID;\n  wire [5:0]S01_AXI_1_BID;\n  wire S01_AXI_1_BREADY;\n  wire [1:0]S01_AXI_1_BRESP;\n  wire S01_AXI_1_BVALID;\n  wire [511:0]S01_AXI_1_RDATA;\n  wire [5:0]S01_AXI_1_RID;\n  wire S01_AXI_1_RLAST;\n  wire S01_AXI_1_RREADY;\n  wire [1:0]S01_AXI_1_RRESP;\n  wire S01_AXI_1_RVALID;\n  wire [511:0]S01_AXI_1_WDATA;\n  wire S01_AXI_1_WLAST;\n  wire S01_AXI_1_WREADY;\n  wire [63:0]S01_AXI_1_WSTRB;\n  wire S01_AXI_1_WVALID;\n  wire [63:0]axi_interconnect_0_M00_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M00_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M00_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M00_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M00_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M00_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARQOS;\n  wire axi_interconnect_0_M00_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M00_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M00_AXI_ARSIZE;\n  wire axi_interconnect_0_M00_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M00_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M00_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M00_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M00_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M00_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M00_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWQOS;\n  wire axi_interconnect_0_M00_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M00_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M00_AXI_AWSIZE;\n  wire axi_interconnect_0_M00_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M00_AXI_BID;\n  wire axi_interconnect_0_M00_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M00_AXI_BRESP;\n  wire axi_interconnect_0_M00_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M00_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M00_AXI_RID;\n  wire axi_interconnect_0_M00_AXI_RLAST;\n  wire axi_interconnect_0_M00_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M00_AXI_RRESP;\n  wire axi_interconnect_0_M00_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M00_AXI_WDATA;\n  wire axi_interconnect_0_M00_AXI_WLAST;\n  wire axi_interconnect_0_M00_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M00_AXI_WSTRB;\n  wire axi_interconnect_0_M00_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M01_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M01_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M01_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M01_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M01_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M01_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARQOS;\n  wire axi_interconnect_0_M01_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M01_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M01_AXI_ARSIZE;\n  wire axi_interconnect_0_M01_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M01_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M01_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M01_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M01_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M01_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M01_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWQOS;\n  wire axi_interconnect_0_M01_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M01_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M01_AXI_AWSIZE;\n  wire axi_interconnect_0_M01_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M01_AXI_BID;\n  wire axi_interconnect_0_M01_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M01_AXI_BRESP;\n  wire axi_interconnect_0_M01_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M01_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M01_AXI_RID;\n  wire axi_interconnect_0_M01_AXI_RLAST;\n  wire axi_interconnect_0_M01_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M01_AXI_RRESP;\n  wire axi_interconnect_0_M01_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M01_AXI_WDATA;\n  wire axi_interconnect_0_M01_AXI_WLAST;\n  wire axi_interconnect_0_M01_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M01_AXI_WSTRB;\n  wire axi_interconnect_0_M01_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M02_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M02_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M02_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M02_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M02_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M02_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARQOS;\n  wire axi_interconnect_0_M02_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M02_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M02_AXI_ARSIZE;\n  wire axi_interconnect_0_M02_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M02_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M02_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M02_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M02_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M02_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M02_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWQOS;\n  wire axi_interconnect_0_M02_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M02_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M02_AXI_AWSIZE;\n  wire axi_interconnect_0_M02_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M02_AXI_BID;\n  wire axi_interconnect_0_M02_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M02_AXI_BRESP;\n  wire axi_interconnect_0_M02_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M02_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M02_AXI_RID;\n  wire axi_interconnect_0_M02_AXI_RLAST;\n  wire axi_interconnect_0_M02_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M02_AXI_RRESP;\n  wire axi_interconnect_0_M02_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M02_AXI_WDATA;\n  wire axi_interconnect_0_M02_AXI_WLAST;\n  wire axi_interconnect_0_M02_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M02_AXI_WSTRB;\n  wire axi_interconnect_0_M02_AXI_WVALID;\n  wire [63:0]axi_interconnect_0_M03_AXI_ARADDR;\n  wire [1:0]axi_interconnect_0_M03_AXI_ARBURST;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARCACHE;\n  wire [6:0]axi_interconnect_0_M03_AXI_ARID;\n  wire [7:0]axi_interconnect_0_M03_AXI_ARLEN;\n  wire [0:0]axi_interconnect_0_M03_AXI_ARLOCK;\n  wire [2:0]axi_interconnect_0_M03_AXI_ARPROT;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARQOS;\n  wire axi_interconnect_0_M03_AXI_ARREADY;\n  wire [3:0]axi_interconnect_0_M03_AXI_ARREGION;\n  wire [2:0]axi_interconnect_0_M03_AXI_ARSIZE;\n  wire axi_interconnect_0_M03_AXI_ARVALID;\n  wire [63:0]axi_interconnect_0_M03_AXI_AWADDR;\n  wire [1:0]axi_interconnect_0_M03_AXI_AWBURST;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWCACHE;\n  wire [6:0]axi_interconnect_0_M03_AXI_AWID;\n  wire [7:0]axi_interconnect_0_M03_AXI_AWLEN;\n  wire [0:0]axi_interconnect_0_M03_AXI_AWLOCK;\n  wire [2:0]axi_interconnect_0_M03_AXI_AWPROT;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWQOS;\n  wire axi_interconnect_0_M03_AXI_AWREADY;\n  wire [3:0]axi_interconnect_0_M03_AXI_AWREGION;\n  wire [2:0]axi_interconnect_0_M03_AXI_AWSIZE;\n  wire axi_interconnect_0_M03_AXI_AWVALID;\n  wire [6:0]axi_interconnect_0_M03_AXI_BID;\n  wire axi_interconnect_0_M03_AXI_BREADY;\n  wire [1:0]axi_interconnect_0_M03_AXI_BRESP;\n  wire axi_interconnect_0_M03_AXI_BVALID;\n  wire [511:0]axi_interconnect_0_M03_AXI_RDATA;\n  wire [6:0]axi_interconnect_0_M03_AXI_RID;\n  wire axi_interconnect_0_M03_AXI_RLAST;\n  wire axi_interconnect_0_M03_AXI_RREADY;\n  wire [1:0]axi_interconnect_0_M03_AXI_RRESP;\n  wire axi_interconnect_0_M03_AXI_RVALID;\n  wire [511:0]axi_interconnect_0_M03_AXI_WDATA;\n  wire axi_interconnect_0_M03_AXI_WLAST;\n  wire axi_interconnect_0_M03_AXI_WREADY;\n  wire [63:0]axi_interconnect_0_M03_AXI_WSTRB;\n  wire axi_interconnect_0_M03_AXI_WVALID;\n\n  assign ACLK_1 = ACLK;\n  assign ARESETN_1 = ARESETN;\n  assign M00_AXI_araddr[63:0] = axi_interconnect_0_M00_AXI_ARADDR;\n  assign M00_AXI_arburst[1:0] = axi_interconnect_0_M00_AXI_ARBURST;\n  assign M00_AXI_arcache[3:0] = axi_interconnect_0_M00_AXI_ARCACHE;\n  assign M00_AXI_arid[6:0] = axi_interconnect_0_M00_AXI_ARID;\n  assign M00_AXI_arlen[7:0] = axi_interconnect_0_M00_AXI_ARLEN;\n  assign M00_AXI_arlock[0] = axi_interconnect_0_M00_AXI_ARLOCK;\n  assign M00_AXI_arprot[2:0] = axi_interconnect_0_M00_AXI_ARPROT;\n  assign M00_AXI_arqos[3:0] = axi_interconnect_0_M00_AXI_ARQOS;\n  assign M00_AXI_arregion[3:0] = axi_interconnect_0_M00_AXI_ARREGION;\n  assign M00_AXI_arsize[2:0] = axi_interconnect_0_M00_AXI_ARSIZE;\n  assign M00_AXI_arvalid = axi_interconnect_0_M00_AXI_ARVALID;\n  assign M00_AXI_awaddr[63:0] = axi_interconnect_0_M00_AXI_AWADDR;\n  assign M00_AXI_awburst[1:0] = axi_interconnect_0_M00_AXI_AWBURST;\n  assign M00_AXI_awcache[3:0] = axi_interconnect_0_M00_AXI_AWCACHE;\n  assign M00_AXI_awid[6:0] = axi_interconnect_0_M00_AXI_AWID;\n  assign M00_AXI_awlen[7:0] = axi_interconnect_0_M00_AXI_AWLEN;\n  assign M00_AXI_awlock[0] = axi_interconnect_0_M00_AXI_AWLOCK;\n  assign M00_AXI_awprot[2:0] = axi_interconnect_0_M00_AXI_AWPROT;\n  assign M00_AXI_awqos[3:0] = axi_interconnect_0_M00_AXI_AWQOS;\n  assign M00_AXI_awregion[3:0] = axi_interconnect_0_M00_AXI_AWREGION;\n  assign M00_AXI_awsize[2:0] = axi_interconnect_0_M00_AXI_AWSIZE;\n  assign M00_AXI_awvalid = axi_interconnect_0_M00_AXI_AWVALID;\n  assign M00_AXI_bready = axi_interconnect_0_M00_AXI_BREADY;\n  assign M00_AXI_rready = axi_interconnect_0_M00_AXI_RREADY;\n  assign M00_AXI_wdata[511:0] = axi_interconnect_0_M00_AXI_WDATA;\n  assign M00_AXI_wlast = axi_interconnect_0_M00_AXI_WLAST;\n  assign M00_AXI_wstrb[63:0] = axi_interconnect_0_M00_AXI_WSTRB;\n  assign M00_AXI_wvalid = axi_interconnect_0_M00_AXI_WVALID;\n  assign M01_AXI_araddr[63:0] = axi_interconnect_0_M01_AXI_ARADDR;\n  assign M01_AXI_arburst[1:0] = axi_interconnect_0_M01_AXI_ARBURST;\n  assign M01_AXI_arcache[3:0] = axi_interconnect_0_M01_AXI_ARCACHE;\n  assign M01_AXI_arid[6:0] = axi_interconnect_0_M01_AXI_ARID;\n  assign M01_AXI_arlen[7:0] = axi_interconnect_0_M01_AXI_ARLEN;\n  assign M01_AXI_arlock[0] = axi_interconnect_0_M01_AXI_ARLOCK;\n  assign M01_AXI_arprot[2:0] = axi_interconnect_0_M01_AXI_ARPROT;\n  assign M01_AXI_arqos[3:0] = axi_interconnect_0_M01_AXI_ARQOS;\n  assign M01_AXI_arregion[3:0] = axi_interconnect_0_M01_AXI_ARREGION;\n  assign M01_AXI_arsize[2:0] = axi_interconnect_0_M01_AXI_ARSIZE;\n  assign M01_AXI_arvalid = axi_interconnect_0_M01_AXI_ARVALID;\n  assign M01_AXI_awaddr[63:0] = axi_interconnect_0_M01_AXI_AWADDR;\n  assign M01_AXI_awburst[1:0] = axi_interconnect_0_M01_AXI_AWBURST;\n  assign M01_AXI_awcache[3:0] = axi_interconnect_0_M01_AXI_AWCACHE;\n  assign M01_AXI_awid[6:0] = axi_interconnect_0_M01_AXI_AWID;\n  assign M01_AXI_awlen[7:0] = axi_interconnect_0_M01_AXI_AWLEN;\n  assign M01_AXI_awlock[0] = axi_interconnect_0_M01_AXI_AWLOCK;\n  assign M01_AXI_awprot[2:0] = axi_interconnect_0_M01_AXI_AWPROT;\n  assign M01_AXI_awqos[3:0] = axi_interconnect_0_M01_AXI_AWQOS;\n  assign M01_AXI_awregion[3:0] = axi_interconnect_0_M01_AXI_AWREGION;\n  assign M01_AXI_awsize[2:0] = axi_interconnect_0_M01_AXI_AWSIZE;\n  assign M01_AXI_awvalid = axi_interconnect_0_M01_AXI_AWVALID;\n  assign M01_AXI_bready = axi_interconnect_0_M01_AXI_BREADY;\n  assign M01_AXI_rready = axi_interconnect_0_M01_AXI_RREADY;\n  assign M01_AXI_wdata[511:0] = axi_interconnect_0_M01_AXI_WDATA;\n  assign M01_AXI_wlast = axi_interconnect_0_M01_AXI_WLAST;\n  assign M01_AXI_wstrb[63:0] = axi_interconnect_0_M01_AXI_WSTRB;\n  assign M01_AXI_wvalid = axi_interconnect_0_M01_AXI_WVALID;\n  assign M02_AXI_araddr[63:0] = axi_interconnect_0_M02_AXI_ARADDR;\n  assign M02_AXI_arburst[1:0] = axi_interconnect_0_M02_AXI_ARBURST;\n  assign M02_AXI_arcache[3:0] = axi_interconnect_0_M02_AXI_ARCACHE;\n  assign M02_AXI_arid[6:0] = axi_interconnect_0_M02_AXI_ARID;\n  assign M02_AXI_arlen[7:0] = axi_interconnect_0_M02_AXI_ARLEN;\n  assign M02_AXI_arlock[0] = axi_interconnect_0_M02_AXI_ARLOCK;\n  assign M02_AXI_arprot[2:0] = axi_interconnect_0_M02_AXI_ARPROT;\n  assign M02_AXI_arqos[3:0] = axi_interconnect_0_M02_AXI_ARQOS;\n  assign M02_AXI_arregion[3:0] = axi_interconnect_0_M02_AXI_ARREGION;\n  assign M02_AXI_arsize[2:0] = axi_interconnect_0_M02_AXI_ARSIZE;\n  assign M02_AXI_arvalid = axi_interconnect_0_M02_AXI_ARVALID;\n  assign M02_AXI_awaddr[63:0] = axi_interconnect_0_M02_AXI_AWADDR;\n  assign M02_AXI_awburst[1:0] = axi_interconnect_0_M02_AXI_AWBURST;\n  assign M02_AXI_awcache[3:0] = axi_interconnect_0_M02_AXI_AWCACHE;\n  assign M02_AXI_awid[6:0] = axi_interconnect_0_M02_AXI_AWID;\n  assign M02_AXI_awlen[7:0] = axi_interconnect_0_M02_AXI_AWLEN;\n  assign M02_AXI_awlock[0] = axi_interconnect_0_M02_AXI_AWLOCK;\n  assign M02_AXI_awprot[2:0] = axi_interconnect_0_M02_AXI_AWPROT;\n  assign M02_AXI_awqos[3:0] = axi_interconnect_0_M02_AXI_AWQOS;\n  assign M02_AXI_awregion[3:0] = axi_interconnect_0_M02_AXI_AWREGION;\n  assign M02_AXI_awsize[2:0] = axi_interconnect_0_M02_AXI_AWSIZE;\n  assign M02_AXI_awvalid = axi_interconnect_0_M02_AXI_AWVALID;\n  assign M02_AXI_bready = axi_interconnect_0_M02_AXI_BREADY;\n  assign M02_AXI_rready = axi_interconnect_0_M02_AXI_RREADY;\n  assign M02_AXI_wdata[511:0] = axi_interconnect_0_M02_AXI_WDATA;\n  assign M02_AXI_wlast = axi_interconnect_0_M02_AXI_WLAST;\n  assign M02_AXI_wstrb[63:0] = axi_interconnect_0_M02_AXI_WSTRB;\n  assign M02_AXI_wvalid = axi_interconnect_0_M02_AXI_WVALID;\n  assign M03_AXI_araddr[63:0] = axi_interconnect_0_M03_AXI_ARADDR;\n  assign M03_AXI_arburst[1:0] = axi_interconnect_0_M03_AXI_ARBURST;\n  assign M03_AXI_arcache[3:0] = axi_interconnect_0_M03_AXI_ARCACHE;\n  assign M03_AXI_arid[6:0] = axi_interconnect_0_M03_AXI_ARID;\n  assign M03_AXI_arlen[7:0] = axi_interconnect_0_M03_AXI_ARLEN;\n  assign M03_AXI_arlock[0] = axi_interconnect_0_M03_AXI_ARLOCK;\n  assign M03_AXI_arprot[2:0] = axi_interconnect_0_M03_AXI_ARPROT;\n  assign M03_AXI_arqos[3:0] = axi_interconnect_0_M03_AXI_ARQOS;\n  assign M03_AXI_arregion[3:0] = axi_interconnect_0_M03_AXI_ARREGION;\n  assign M03_AXI_arsize[2:0] = axi_interconnect_0_M03_AXI_ARSIZE;\n  assign M03_AXI_arvalid = axi_interconnect_0_M03_AXI_ARVALID;\n  assign M03_AXI_awaddr[63:0] = axi_interconnect_0_M03_AXI_AWADDR;\n  assign M03_AXI_awburst[1:0] = axi_interconnect_0_M03_AXI_AWBURST;\n  assign M03_AXI_awcache[3:0] = axi_interconnect_0_M03_AXI_AWCACHE;\n  assign M03_AXI_awid[6:0] = axi_interconnect_0_M03_AXI_AWID;\n  assign M03_AXI_awlen[7:0] = axi_interconnect_0_M03_AXI_AWLEN;\n  assign M03_AXI_awlock[0] = axi_interconnect_0_M03_AXI_AWLOCK;\n  assign M03_AXI_awprot[2:0] = axi_interconnect_0_M03_AXI_AWPROT;\n  assign M03_AXI_awqos[3:0] = axi_interconnect_0_M03_AXI_AWQOS;\n  assign M03_AXI_awregion[3:0] = axi_interconnect_0_M03_AXI_AWREGION;\n  assign M03_AXI_awsize[2:0] = axi_interconnect_0_M03_AXI_AWSIZE;\n  assign M03_AXI_awvalid = axi_interconnect_0_M03_AXI_AWVALID;\n  assign M03_AXI_bready = axi_interconnect_0_M03_AXI_BREADY;\n  assign M03_AXI_rready = axi_interconnect_0_M03_AXI_RREADY;\n  assign M03_AXI_wdata[511:0] = axi_interconnect_0_M03_AXI_WDATA;\n  assign M03_AXI_wlast = axi_interconnect_0_M03_AXI_WLAST;\n  assign M03_AXI_wstrb[63:0] = axi_interconnect_0_M03_AXI_WSTRB;\n  assign M03_AXI_wvalid = axi_interconnect_0_M03_AXI_WVALID;\n  assign S00_AXI_1_ARADDR = S00_AXI_araddr[63:0];\n  assign S00_AXI_1_ARBURST = S00_AXI_arburst[1:0];\n  assign S00_AXI_1_ARCACHE = S00_AXI_arcache[3:0];\n  assign S00_AXI_1_ARID = S00_AXI_arid[5:0];\n  assign S00_AXI_1_ARLEN = S00_AXI_arlen[7:0];\n  assign S00_AXI_1_ARLOCK = S00_AXI_arlock[0];\n  assign S00_AXI_1_ARPROT = S00_AXI_arprot[2:0];\n  assign S00_AXI_1_ARQOS = S00_AXI_arqos[3:0];\n  assign S00_AXI_1_ARREGION = S00_AXI_arregion[3:0];\n  assign S00_AXI_1_ARSIZE = S00_AXI_arsize[2:0];\n  assign S00_AXI_1_ARVALID = S00_AXI_arvalid;\n  assign S00_AXI_1_AWADDR = S00_AXI_awaddr[63:0];\n  assign S00_AXI_1_AWBURST = S00_AXI_awburst[1:0];\n  assign S00_AXI_1_AWCACHE = S00_AXI_awcache[3:0];\n  assign S00_AXI_1_AWID = S00_AXI_awid[5:0];\n  assign S00_AXI_1_AWLEN = S00_AXI_awlen[7:0];\n  assign S00_AXI_1_AWLOCK = S00_AXI_awlock[0];\n  assign S00_AXI_1_AWPROT = S00_AXI_awprot[2:0];\n  assign S00_AXI_1_AWQOS = S00_AXI_awqos[3:0];\n  assign S00_AXI_1_AWREGION = S00_AXI_awregion[3:0];\n  assign S00_AXI_1_AWSIZE = S00_AXI_awsize[2:0];\n  assign S00_AXI_1_AWVALID = S00_AXI_awvalid;\n  assign S00_AXI_1_BREADY = S00_AXI_bready;\n  assign S00_AXI_1_RREADY = S00_AXI_rready;\n  assign S00_AXI_1_WDATA = S00_AXI_wdata[511:0];\n  assign S00_AXI_1_WLAST = S00_AXI_wlast;\n  assign S00_AXI_1_WSTRB = S00_AXI_wstrb[63:0];\n  assign S00_AXI_1_WVALID = S00_AXI_wvalid;\n  assign S00_AXI_arready = S00_AXI_1_ARREADY;\n  assign S00_AXI_awready = S00_AXI_1_AWREADY;\n  assign S00_AXI_bid[5:0] = S00_AXI_1_BID;\n  assign S00_AXI_bresp[1:0] = S00_AXI_1_BRESP;\n  assign S00_AXI_bvalid = S00_AXI_1_BVALID;\n  assign S00_AXI_rdata[511:0] = S00_AXI_1_RDATA;\n  assign S00_AXI_rid[5:0] = S00_AXI_1_RID;\n  assign S00_AXI_rlast = S00_AXI_1_RLAST;\n  assign S00_AXI_rresp[1:0] = S00_AXI_1_RRESP;\n  assign S00_AXI_rvalid = S00_AXI_1_RVALID;\n  assign S00_AXI_wready = S00_AXI_1_WREADY;\n  assign S01_AXI_1_ARADDR = S01_AXI_araddr[63:0];\n  assign S01_AXI_1_ARBURST = S01_AXI_arburst[1:0];\n  assign S01_AXI_1_ARCACHE = S01_AXI_arcache[3:0];\n  assign S01_AXI_1_ARID = S01_AXI_arid[5:0];\n  assign S01_AXI_1_ARLEN = S01_AXI_arlen[7:0];\n  assign S01_AXI_1_ARLOCK = S01_AXI_arlock[0];\n  assign S01_AXI_1_ARPROT = S01_AXI_arprot[2:0];\n  assign S01_AXI_1_ARQOS = S01_AXI_arqos[3:0];\n  assign S01_AXI_1_ARREGION = S01_AXI_arregion[3:0];\n  assign S01_AXI_1_ARSIZE = S01_AXI_arsize[2:0];\n  assign S01_AXI_1_ARVALID = S01_AXI_arvalid;\n  assign S01_AXI_1_AWADDR = S01_AXI_awaddr[63:0];\n  assign S01_AXI_1_AWBURST = S01_AXI_awburst[1:0];\n  assign S01_AXI_1_AWCACHE = S01_AXI_awcache[3:0];\n  assign S01_AXI_1_AWID = S01_AXI_awid[5:0];\n  assign S01_AXI_1_AWLEN = S01_AXI_awlen[7:0];\n  assign S01_AXI_1_AWLOCK = S01_AXI_awlock[0];\n  assign S01_AXI_1_AWPROT = S01_AXI_awprot[2:0];\n  assign S01_AXI_1_AWQOS = S01_AXI_awqos[3:0];\n  assign S01_AXI_1_AWREGION = S01_AXI_awregion[3:0];\n  assign S01_AXI_1_AWSIZE = S01_AXI_awsize[2:0];\n  assign S01_AXI_1_AWVALID = S01_AXI_awvalid;\n  assign S01_AXI_1_BREADY = S01_AXI_bready;\n  assign S01_AXI_1_RREADY = S01_AXI_rready;\n  assign S01_AXI_1_WDATA = S01_AXI_wdata[511:0];\n  assign S01_AXI_1_WLAST = S01_AXI_wlast;\n  assign S01_AXI_1_WSTRB = S01_AXI_wstrb[63:0];\n  assign S01_AXI_1_WVALID = S01_AXI_wvalid;\n  assign S01_AXI_arready = S01_AXI_1_ARREADY;\n  assign S01_AXI_awready = S01_AXI_1_AWREADY;\n  assign S01_AXI_bid[5:0] = S01_AXI_1_BID;\n  assign S01_AXI_bresp[1:0] = S01_AXI_1_BRESP;\n  assign S01_AXI_bvalid = S01_AXI_1_BVALID;\n  assign S01_AXI_rdata[511:0] = S01_AXI_1_RDATA;\n  assign S01_AXI_rid[5:0] = S01_AXI_1_RID;\n  assign S01_AXI_rlast = S01_AXI_1_RLAST;\n  assign S01_AXI_rresp[1:0] = S01_AXI_1_RRESP;\n  assign S01_AXI_rvalid = S01_AXI_1_RVALID;\n  assign S01_AXI_wready = S01_AXI_1_WREADY;\n  assign axi_interconnect_0_M00_AXI_ARREADY = M00_AXI_arready;\n  assign axi_interconnect_0_M00_AXI_AWREADY = M00_AXI_awready;\n  assign axi_interconnect_0_M00_AXI_BID = M00_AXI_bid[6:0];\n  assign axi_interconnect_0_M00_AXI_BRESP = M00_AXI_bresp[1:0];\n  assign axi_interconnect_0_M00_AXI_BVALID = M00_AXI_bvalid;\n  assign axi_interconnect_0_M00_AXI_RDATA = M00_AXI_rdata[511:0];\n  assign axi_interconnect_0_M00_AXI_RID = M00_AXI_rid[6:0];\n  assign axi_interconnect_0_M00_AXI_RLAST = M00_AXI_rlast;\n  assign axi_interconnect_0_M00_AXI_RRESP = M00_AXI_rresp[1:0];\n  assign axi_interconnect_0_M00_AXI_RVALID = M00_AXI_rvalid;\n  assign axi_interconnect_0_M00_AXI_WREADY = M00_AXI_wready;\n  assign axi_interconnect_0_M01_AXI_ARREADY = M01_AXI_arready;\n  assign axi_interconnect_0_M01_AXI_AWREADY = M01_AXI_awready;\n  assign axi_interconnect_0_M01_AXI_BID = M01_AXI_bid[6:0];\n  assign axi_interconnect_0_M01_AXI_BRESP = M01_AXI_bresp[1:0];\n  assign axi_interconnect_0_M01_AXI_BVALID = M01_AXI_bvalid;\n  assign axi_interconnect_0_M01_AXI_RDATA = M01_AXI_rdata[511:0];\n  assign axi_interconnect_0_M01_AXI_RID = M01_AXI_rid[6:0];\n  assign axi_interconnect_0_M01_AXI_RLAST = M01_AXI_rlast;\n  assign axi_interconnect_0_M01_AXI_RRESP = M01_AXI_rresp[1:0];\n  assign axi_interconnect_0_M01_AXI_RVALID = M01_AXI_rvalid;\n  assign axi_interconnect_0_M01_AXI_WREADY = M01_AXI_wready;\n  assign axi_interconnect_0_M02_AXI_ARREADY = M02_AXI_arready;\n  assign axi_interconnect_0_M02_AXI_AWREADY = M02_AXI_awready;\n  assign axi_interconnect_0_M02_AXI_BID = M02_AXI_bid[6:0];\n  assign axi_interconnect_0_M02_AXI_BRESP = M02_AXI_bresp[1:0];\n  assign axi_interconnect_0_M02_AXI_BVALID = M02_AXI_bvalid;\n  assign axi_interconnect_0_M02_AXI_RDATA = M02_AXI_rdata[511:0];\n  assign axi_interconnect_0_M02_AXI_RID = M02_AXI_rid[6:0];\n  assign axi_interconnect_0_M02_AXI_RLAST = M02_AXI_rlast;\n  assign axi_interconnect_0_M02_AXI_RRESP = M02_AXI_rresp[1:0];\n  assign axi_interconnect_0_M02_AXI_RVALID = M02_AXI_rvalid;\n  assign axi_interconnect_0_M02_AXI_WREADY = M02_AXI_wready;\n  assign axi_interconnect_0_M03_AXI_ARREADY = M03_AXI_arready;\n  assign axi_interconnect_0_M03_AXI_AWREADY = M03_AXI_awready;\n  assign axi_interconnect_0_M03_AXI_BID = M03_AXI_bid[6:0];\n  assign axi_interconnect_0_M03_AXI_BRESP = M03_AXI_bresp[1:0];\n  assign axi_interconnect_0_M03_AXI_BVALID = M03_AXI_bvalid;\n  assign axi_interconnect_0_M03_AXI_RDATA = M03_AXI_rdata[511:0];\n  assign axi_interconnect_0_M03_AXI_RID = M03_AXI_rid[6:0];\n  assign axi_interconnect_0_M03_AXI_RLAST = M03_AXI_rlast;\n  assign axi_interconnect_0_M03_AXI_RRESP = M03_AXI_rresp[1:0];\n  assign axi_interconnect_0_M03_AXI_RVALID = M03_AXI_rvalid;\n  assign axi_interconnect_0_M03_AXI_WREADY = M03_AXI_wready;\n  cl_axi_interconnect_axi_interconnect_0_0 axi_interconnect_0\n       (.ACLK(ACLK_1),\n        .ARESETN(ARESETN_1),\n        .M00_ACLK(ACLK_1),\n        .M00_ARESETN(ARESETN_1),\n        .M00_AXI_araddr(axi_interconnect_0_M00_AXI_ARADDR),\n        .M00_AXI_arburst(axi_interconnect_0_M00_AXI_ARBURST),\n        .M00_AXI_arcache(axi_interconnect_0_M00_AXI_ARCACHE),\n        .M00_AXI_arid(axi_interconnect_0_M00_AXI_ARID),\n        .M00_AXI_arlen(axi_interconnect_0_M00_AXI_ARLEN),\n        .M00_AXI_arlock(axi_interconnect_0_M00_AXI_ARLOCK),\n        .M00_AXI_arprot(axi_interconnect_0_M00_AXI_ARPROT),\n        .M00_AXI_arqos(axi_interconnect_0_M00_AXI_ARQOS),\n        .M00_AXI_arready(axi_interconnect_0_M00_AXI_ARREADY),\n        .M00_AXI_arregion(axi_interconnect_0_M00_AXI_ARREGION),\n        .M00_AXI_arsize(axi_interconnect_0_M00_AXI_ARSIZE),\n        .M00_AXI_arvalid(axi_interconnect_0_M00_AXI_ARVALID),\n        .M00_AXI_awaddr(axi_interconnect_0_M00_AXI_AWADDR),\n        .M00_AXI_awburst(axi_interconnect_0_M00_AXI_AWBURST),\n        .M00_AXI_awcache(axi_interconnect_0_M00_AXI_AWCACHE),\n        .M00_AXI_awid(axi_interconnect_0_M00_AXI_AWID),\n        .M00_AXI_awlen(axi_interconnect_0_M00_AXI_AWLEN),\n        .M00_AXI_awlock(axi_interconnect_0_M00_AXI_AWLOCK),\n        .M00_AXI_awprot(axi_interconnect_0_M00_AXI_AWPROT),\n        .M00_AXI_awqos(axi_interconnect_0_M00_AXI_AWQOS),\n        .M00_AXI_awready(axi_interconnect_0_M00_AXI_AWREADY),\n        .M00_AXI_awregion(axi_interconnect_0_M00_AXI_AWREGION),\n        .M00_AXI_awsize(axi_interconnect_0_M00_AXI_AWSIZE),\n        .M00_AXI_awvalid(axi_interconnect_0_M00_AXI_AWVALID),\n        .M00_AXI_bid(axi_interconnect_0_M00_AXI_BID),\n        .M00_AXI_bready(axi_interconnect_0_M00_AXI_BREADY),\n        .M00_AXI_bresp(axi_interconnect_0_M00_AXI_BRESP),\n        .M00_AXI_bvalid(axi_interconnect_0_M00_AXI_BVALID),\n        .M00_AXI_rdata(axi_interconnect_0_M00_AXI_RDATA),\n        .M00_AXI_rid(axi_interconnect_0_M00_AXI_RID),\n        .M00_AXI_rlast(axi_interconnect_0_M00_AXI_RLAST),\n        .M00_AXI_rready(axi_interconnect_0_M00_AXI_RREADY),\n        .M00_AXI_rresp(axi_interconnect_0_M00_AXI_RRESP),\n        .M00_AXI_rvalid(axi_interconnect_0_M00_AXI_RVALID),\n        .M00_AXI_wdata(axi_interconnect_0_M00_AXI_WDATA),\n        .M00_AXI_wlast(axi_interconnect_0_M00_AXI_WLAST),\n        .M00_AXI_wready(axi_interconnect_0_M00_AXI_WREADY),\n        .M00_AXI_wstrb(axi_interconnect_0_M00_AXI_WSTRB),\n        .M00_AXI_wvalid(axi_interconnect_0_M00_AXI_WVALID),\n        .M01_ACLK(ACLK_1),\n        .M01_ARESETN(ARESETN_1),\n        .M01_AXI_araddr(axi_interconnect_0_M01_AXI_ARADDR),\n        .M01_AXI_arburst(axi_interconnect_0_M01_AXI_ARBURST),\n        .M01_AXI_arcache(axi_interconnect_0_M01_AXI_ARCACHE),\n        .M01_AXI_arid(axi_interconnect_0_M01_AXI_ARID),\n        .M01_AXI_arlen(axi_interconnect_0_M01_AXI_ARLEN),\n        .M01_AXI_arlock(axi_interconnect_0_M01_AXI_ARLOCK),\n        .M01_AXI_arprot(axi_interconnect_0_M01_AXI_ARPROT),\n        .M01_AXI_arqos(axi_interconnect_0_M01_AXI_ARQOS),\n        .M01_AXI_arready(axi_interconnect_0_M01_AXI_ARREADY),\n        .M01_AXI_arregion(axi_interconnect_0_M01_AXI_ARREGION),\n        .M01_AXI_arsize(axi_interconnect_0_M01_AXI_ARSIZE),\n        .M01_AXI_arvalid(axi_interconnect_0_M01_AXI_ARVALID),\n        .M01_AXI_awaddr(axi_interconnect_0_M01_AXI_AWADDR),\n        .M01_AXI_awburst(axi_interconnect_0_M01_AXI_AWBURST),\n        .M01_AXI_awcache(axi_interconnect_0_M01_AXI_AWCACHE),\n        .M01_AXI_awid(axi_interconnect_0_M01_AXI_AWID),\n        .M01_AXI_awlen(axi_interconnect_0_M01_AXI_AWLEN),\n        .M01_AXI_awlock(axi_interconnect_0_M01_AXI_AWLOCK),\n        .M01_AXI_awprot(axi_interconnect_0_M01_AXI_AWPROT),\n        .M01_AXI_awqos(axi_interconnect_0_M01_AXI_AWQOS),\n        .M01_AXI_awready(axi_interconnect_0_M01_AXI_AWREADY),\n        .M01_AXI_awregion(axi_interconnect_0_M01_AXI_AWREGION),\n        .M01_AXI_awsize(axi_interconnect_0_M01_AXI_AWSIZE),\n        .M01_AXI_awvalid(axi_interconnect_0_M01_AXI_AWVALID),\n        .M01_AXI_bid(axi_interconnect_0_M01_AXI_BID),\n        .M01_AXI_bready(axi_interconnect_0_M01_AXI_BREADY),\n        .M01_AXI_bresp(axi_interconnect_0_M01_AXI_BRESP),\n        .M01_AXI_bvalid(axi_interconnect_0_M01_AXI_BVALID),\n        .M01_AXI_rdata(axi_interconnect_0_M01_AXI_RDATA),\n        .M01_AXI_rid(axi_interconnect_0_M01_AXI_RID),\n        .M01_AXI_rlast(axi_interconnect_0_M01_AXI_RLAST),\n        .M01_AXI_rready(axi_interconnect_0_M01_AXI_RREADY),\n        .M01_AXI_rresp(axi_interconnect_0_M01_AXI_RRESP),\n        .M01_AXI_rvalid(axi_interconnect_0_M01_AXI_RVALID),\n        .M01_AXI_wdata(axi_interconnect_0_M01_AXI_WDATA),\n        .M01_AXI_wlast(axi_interconnect_0_M01_AXI_WLAST),\n        .M01_AXI_wready(axi_interconnect_0_M01_AXI_WREADY),\n        .M01_AXI_wstrb(axi_interconnect_0_M01_AXI_WSTRB),\n        .M01_AXI_wvalid(axi_interconnect_0_M01_AXI_WVALID),\n        .M02_ACLK(ACLK_1),\n        .M02_ARESETN(ARESETN_1),\n        .M02_AXI_araddr(axi_interconnect_0_M02_AXI_ARADDR),\n        .M02_AXI_arburst(axi_interconnect_0_M02_AXI_ARBURST),\n        .M02_AXI_arcache(axi_interconnect_0_M02_AXI_ARCACHE),\n        .M02_AXI_arid(axi_interconnect_0_M02_AXI_ARID),\n        .M02_AXI_arlen(axi_interconnect_0_M02_AXI_ARLEN),\n        .M02_AXI_arlock(axi_interconnect_0_M02_AXI_ARLOCK),\n        .M02_AXI_arprot(axi_interconnect_0_M02_AXI_ARPROT),\n        .M02_AXI_arqos(axi_interconnect_0_M02_AXI_ARQOS),\n        .M02_AXI_arready(axi_interconnect_0_M02_AXI_ARREADY),\n        .M02_AXI_arregion(axi_interconnect_0_M02_AXI_ARREGION),\n        .M02_AXI_arsize(axi_interconnect_0_M02_AXI_ARSIZE),\n        .M02_AXI_arvalid(axi_interconnect_0_M02_AXI_ARVALID),\n        .M02_AXI_awaddr(axi_interconnect_0_M02_AXI_AWADDR),\n        .M02_AXI_awburst(axi_interconnect_0_M02_AXI_AWBURST),\n        .M02_AXI_awcache(axi_interconnect_0_M02_AXI_AWCACHE),\n        .M02_AXI_awid(axi_interconnect_0_M02_AXI_AWID),\n        .M02_AXI_awlen(axi_interconnect_0_M02_AXI_AWLEN),\n        .M02_AXI_awlock(axi_interconnect_0_M02_AXI_AWLOCK),\n        .M02_AXI_awprot(axi_interconnect_0_M02_AXI_AWPROT),\n        .M02_AXI_awqos(axi_interconnect_0_M02_AXI_AWQOS),\n        .M02_AXI_awready(axi_interconnect_0_M02_AXI_AWREADY),\n        .M02_AXI_awregion(axi_interconnect_0_M02_AXI_AWREGION),\n        .M02_AXI_awsize(axi_interconnect_0_M02_AXI_AWSIZE),\n        .M02_AXI_awvalid(axi_interconnect_0_M02_AXI_AWVALID),\n        .M02_AXI_bid(axi_interconnect_0_M02_AXI_BID),\n        .M02_AXI_bready(axi_interconnect_0_M02_AXI_BREADY),\n        .M02_AXI_bresp(axi_interconnect_0_M02_AXI_BRESP),\n        .M02_AXI_bvalid(axi_interconnect_0_M02_AXI_BVALID),\n        .M02_AXI_rdata(axi_interconnect_0_M02_AXI_RDATA),\n        .M02_AXI_rid(axi_interconnect_0_M02_AXI_RID),\n        .M02_AXI_rlast(axi_interconnect_0_M02_AXI_RLAST),\n        .M02_AXI_rready(axi_interconnect_0_M02_AXI_RREADY),\n        .M02_AXI_rresp(axi_interconnect_0_M02_AXI_RRESP),\n        .M02_AXI_rvalid(axi_interconnect_0_M02_AXI_RVALID),\n        .M02_AXI_wdata(axi_interconnect_0_M02_AXI_WDATA),\n        .M02_AXI_wlast(axi_interconnect_0_M02_AXI_WLAST),\n        .M02_AXI_wready(axi_interconnect_0_M02_AXI_WREADY),\n        .M02_AXI_wstrb(axi_interconnect_0_M02_AXI_WSTRB),\n        .M02_AXI_wvalid(axi_interconnect_0_M02_AXI_WVALID),\n        .M03_ACLK(ACLK_1),\n        .M03_ARESETN(ARESETN_1),\n        .M03_AXI_araddr(axi_interconnect_0_M03_AXI_ARADDR),\n        .M03_AXI_arburst(axi_interconnect_0_M03_AXI_ARBURST),\n        .M03_AXI_arcache(axi_interconnect_0_M03_AXI_ARCACHE),\n        .M03_AXI_arid(axi_interconnect_0_M03_AXI_ARID),\n        .M03_AXI_arlen(axi_interconnect_0_M03_AXI_ARLEN),\n        .M03_AXI_arlock(axi_interconnect_0_M03_AXI_ARLOCK),\n        .M03_AXI_arprot(axi_interconnect_0_M03_AXI_ARPROT),\n        .M03_AXI_arqos(axi_interconnect_0_M03_AXI_ARQOS),\n        .M03_AXI_arready(axi_interconnect_0_M03_AXI_ARREADY),\n        .M03_AXI_arregion(axi_interconnect_0_M03_AXI_ARREGION),\n        .M03_AXI_arsize(axi_interconnect_0_M03_AXI_ARSIZE),\n        .M03_AXI_arvalid(axi_interconnect_0_M03_AXI_ARVALID),\n        .M03_AXI_awaddr(axi_interconnect_0_M03_AXI_AWADDR),\n        .M03_AXI_awburst(axi_interconnect_0_M03_AXI_AWBURST),\n        .M03_AXI_awcache(axi_interconnect_0_M03_AXI_AWCACHE),\n        .M03_AXI_awid(axi_interconnect_0_M03_AXI_AWID),\n        .M03_AXI_awlen(axi_interconnect_0_M03_AXI_AWLEN),\n        .M03_AXI_awlock(axi_interconnect_0_M03_AXI_AWLOCK),\n        .M03_AXI_awprot(axi_interconnect_0_M03_AXI_AWPROT),\n        .M03_AXI_awqos(axi_interconnect_0_M03_AXI_AWQOS),\n        .M03_AXI_awready(axi_interconnect_0_M03_AXI_AWREADY),\n        .M03_AXI_awregion(axi_interconnect_0_M03_AXI_AWREGION),\n        .M03_AXI_awsize(axi_interconnect_0_M03_AXI_AWSIZE),\n        .M03_AXI_awvalid(axi_interconnect_0_M03_AXI_AWVALID),\n        .M03_AXI_bid(axi_interconnect_0_M03_AXI_BID),\n        .M03_AXI_bready(axi_interconnect_0_M03_AXI_BREADY),\n        .M03_AXI_bresp(axi_interconnect_0_M03_AXI_BRESP),\n        .M03_AXI_bvalid(axi_interconnect_0_M03_AXI_BVALID),\n        .M03_AXI_rdata(axi_interconnect_0_M03_AXI_RDATA),\n        .M03_AXI_rid(axi_interconnect_0_M03_AXI_RID),\n        .M03_AXI_rlast(axi_interconnect_0_M03_AXI_RLAST),\n        .M03_AXI_rready(axi_interconnect_0_M03_AXI_RREADY),\n        .M03_AXI_rresp(axi_interconnect_0_M03_AXI_RRESP),\n        .M03_AXI_rvalid(axi_interconnect_0_M03_AXI_RVALID),\n        .M03_AXI_wdata(axi_interconnect_0_M03_AXI_WDATA),\n        .M03_AXI_wlast(axi_interconnect_0_M03_AXI_WLAST),\n        .M03_AXI_wready(axi_interconnect_0_M03_AXI_WREADY),\n        .M03_AXI_wstrb(axi_interconnect_0_M03_AXI_WSTRB),\n        .M03_AXI_wvalid(axi_interconnect_0_M03_AXI_WVALID),\n        .S00_ACLK(ACLK_1),\n        .S00_ARESETN(ARESETN_1),\n        .S00_AXI_araddr(S00_AXI_1_ARADDR),\n        .S00_AXI_arburst(S00_AXI_1_ARBURST),\n        .S00_AXI_arcache(S00_AXI_1_ARCACHE),\n        .S00_AXI_arid(S00_AXI_1_ARID),\n        .S00_AXI_arlen(S00_AXI_1_ARLEN),\n        .S00_AXI_arlock(S00_AXI_1_ARLOCK),\n        .S00_AXI_arprot(S00_AXI_1_ARPROT),\n        .S00_AXI_arqos(S00_AXI_1_ARQOS),\n        .S00_AXI_arready(S00_AXI_1_ARREADY),\n        .S00_AXI_arregion(S00_AXI_1_ARREGION),\n        .S00_AXI_arsize(S00_AXI_1_ARSIZE),\n        .S00_AXI_arvalid(S00_AXI_1_ARVALID),\n        .S00_AXI_awaddr(S00_AXI_1_AWADDR),\n        .S00_AXI_awburst(S00_AXI_1_AWBURST),\n        .S00_AXI_awcache(S00_AXI_1_AWCACHE),\n        .S00_AXI_awid(S00_AXI_1_AWID),\n        .S00_AXI_awlen(S00_AXI_1_AWLEN),\n        .S00_AXI_awlock(S00_AXI_1_AWLOCK),\n        .S00_AXI_awprot(S00_AXI_1_AWPROT),\n        .S00_AXI_awqos(S00_AXI_1_AWQOS),\n        .S00_AXI_awready(S00_AXI_1_AWREADY),\n        .S00_AXI_awregion(S00_AXI_1_AWREGION),\n        .S00_AXI_awsize(S00_AXI_1_AWSIZE),\n        .S00_AXI_awvalid(S00_AXI_1_AWVALID),\n        .S00_AXI_bid(S00_AXI_1_BID),\n        .S00_AXI_bready(S00_AXI_1_BREADY),\n        .S00_AXI_bresp(S00_AXI_1_BRESP),\n        .S00_AXI_bvalid(S00_AXI_1_BVALID),\n        .S00_AXI_rdata(S00_AXI_1_RDATA),\n        .S00_AXI_rid(S00_AXI_1_RID),\n        .S00_AXI_rlast(S00_AXI_1_RLAST),\n        .S00_AXI_rready(S00_AXI_1_RREADY),\n        .S00_AXI_rresp(S00_AXI_1_RRESP),\n        .S00_AXI_rvalid(S00_AXI_1_RVALID),\n        .S00_AXI_wdata(S00_AXI_1_WDATA),\n        .S00_AXI_wlast(S00_AXI_1_WLAST),\n        .S00_AXI_wready(S00_AXI_1_WREADY),\n        .S00_AXI_wstrb(S00_AXI_1_WSTRB),\n        .S00_AXI_wvalid(S00_AXI_1_WVALID),\n        .S01_ACLK(ACLK_1),\n        .S01_ARESETN(ARESETN_1),\n        .S01_AXI_araddr(S01_AXI_1_ARADDR),\n        .S01_AXI_arburst(S01_AXI_1_ARBURST),\n        .S01_AXI_arcache(S01_AXI_1_ARCACHE),\n        .S01_AXI_arid(S01_AXI_1_ARID),\n        .S01_AXI_arlen(S01_AXI_1_ARLEN),\n        .S01_AXI_arlock(S01_AXI_1_ARLOCK),\n        .S01_AXI_arprot(S01_AXI_1_ARPROT),\n        .S01_AXI_arqos(S01_AXI_1_ARQOS),\n        .S01_AXI_arready(S01_AXI_1_ARREADY),\n        .S01_AXI_arregion(S01_AXI_1_ARREGION),\n        .S01_AXI_arsize(S01_AXI_1_ARSIZE),\n        .S01_AXI_arvalid(S01_AXI_1_ARVALID),\n        .S01_AXI_awaddr(S01_AXI_1_AWADDR),\n        .S01_AXI_awburst(S01_AXI_1_AWBURST),\n        .S01_AXI_awcache(S01_AXI_1_AWCACHE),\n        .S01_AXI_awid(S01_AXI_1_AWID),\n        .S01_AXI_awlen(S01_AXI_1_AWLEN),\n        .S01_AXI_awlock(S01_AXI_1_AWLOCK),\n        .S01_AXI_awprot(S01_AXI_1_AWPROT),\n        .S01_AXI_awqos(S01_AXI_1_AWQOS),\n        .S01_AXI_awready(S01_AXI_1_AWREADY),\n        .S01_AXI_awregion(S01_AXI_1_AWREGION),\n        .S01_AXI_awsize(S01_AXI_1_AWSIZE),\n        .S01_AXI_awvalid(S01_AXI_1_AWVALID),\n        .S01_AXI_bid(S01_AXI_1_BID),\n        .S01_AXI_bready(S01_AXI_1_BREADY),\n        .S01_AXI_bresp(S01_AXI_1_BRESP),\n        .S01_AXI_bvalid(S01_AXI_1_BVALID),\n        .S01_AXI_rdata(S01_AXI_1_RDATA),\n        .S01_AXI_rid(S01_AXI_1_RID),\n        .S01_AXI_rlast(S01_AXI_1_RLAST),\n        .S01_AXI_rready(S01_AXI_1_RREADY),\n        .S01_AXI_rresp(S01_AXI_1_RRESP),\n        .S01_AXI_rvalid(S01_AXI_1_RVALID),\n        .S01_AXI_wdata(S01_AXI_1_WDATA),\n        .S01_AXI_wlast(S01_AXI_1_WLAST),\n        .S01_AXI_wready(S01_AXI_1_WREADY),\n        .S01_AXI_wstrb(S01_AXI_1_WSTRB),\n        .S01_AXI_wvalid(S01_AXI_1_WVALID));\nendmodule\n\nmodule cl_axi_interconnect_axi_interconnect_0_0\n   (ACLK,\n    ARESETN,\n    M00_ACLK,\n    M00_ARESETN,\n    M00_AXI_araddr,\n    M00_AXI_arburst,\n    M00_AXI_arcache,\n    M00_AXI_arid,\n    M00_AXI_arlen,\n    M00_AXI_arlock,\n    M00_AXI_arprot,\n    M00_AXI_arqos,\n    M00_AXI_arready,\n    M00_AXI_arregion,\n    M00_AXI_arsize,\n    M00_AXI_arvalid,\n    M00_AXI_awaddr,\n    M00_AXI_awburst,\n    M00_AXI_awcache,\n    M00_AXI_awid,\n    M00_AXI_awlen,\n    M00_AXI_awlock,\n    M00_AXI_awprot,\n    M00_AXI_awqos,\n    M00_AXI_awready,\n    M00_AXI_awregion,\n    M00_AXI_awsize,\n    M00_AXI_awvalid,\n    M00_AXI_bid,\n    M00_AXI_bready,\n    M00_AXI_bresp,\n    M00_AXI_bvalid,\n    M00_AXI_rdata,\n    M00_AXI_rid,\n    M00_AXI_rlast,\n    M00_AXI_rready,\n    M00_AXI_rresp,\n    M00_AXI_rvalid,\n    M00_AXI_wdata,\n    M00_AXI_wlast,\n    M00_AXI_wready,\n    M00_AXI_wstrb,\n    M00_AXI_wvalid,\n    M01_ACLK,\n    M01_ARESETN,\n    M01_AXI_araddr,\n    M01_AXI_arburst,\n    M01_AXI_arcache,\n    M01_AXI_arid,\n    M01_AXI_arlen,\n    M01_AXI_arlock,\n    M01_AXI_arprot,\n    M01_AXI_arqos,\n    M01_AXI_arready,\n    M01_AXI_arregion,\n    M01_AXI_arsize,\n    M01_AXI_arvalid,\n    M01_AXI_awaddr,\n    M01_AXI_awburst,\n    M01_AXI_awcache,\n    M01_AXI_awid,\n    M01_AXI_awlen,\n    M01_AXI_awlock,\n    M01_AXI_awprot,\n    M01_AXI_awqos,\n    M01_AXI_awready,\n    M01_AXI_awregion,\n    M01_AXI_awsize,\n    M01_AXI_awvalid,\n    M01_AXI_bid,\n    M01_AXI_bready,\n    M01_AXI_bresp,\n    M01_AXI_bvalid,\n    M01_AXI_rdata,\n    M01_AXI_rid,\n    M01_AXI_rlast,\n    M01_AXI_rready,\n    M01_AXI_rresp,\n    M01_AXI_rvalid,\n    M01_AXI_wdata,\n    M01_AXI_wlast,\n    M01_AXI_wready,\n    M01_AXI_wstrb,\n    M01_AXI_wvalid,\n    M02_ACLK,\n    M02_ARESETN,\n    M02_AXI_araddr,\n    M02_AXI_arburst,\n    M02_AXI_arcache,\n    M02_AXI_arid,\n    M02_AXI_arlen,\n    M02_AXI_arlock,\n    M02_AXI_arprot,\n    M02_AXI_arqos,\n    M02_AXI_arready,\n    M02_AXI_arregion,\n    M02_AXI_arsize,\n    M02_AXI_arvalid,\n    M02_AXI_awaddr,\n    M02_AXI_awburst,\n    M02_AXI_awcache,\n    M02_AXI_awid,\n    M02_AXI_awlen,\n    M02_AXI_awlock,\n    M02_AXI_awprot,\n    M02_AXI_awqos,\n    M02_AXI_awready,\n    M02_AXI_awregion,\n    M02_AXI_awsize,\n    M02_AXI_awvalid,\n    M02_AXI_bid,\n    M02_AXI_bready,\n    M02_AXI_bresp,\n    M02_AXI_bvalid,\n    M02_AXI_rdata,\n    M02_AXI_rid,\n    M02_AXI_rlast,\n    M02_AXI_rready,\n    M02_AXI_rresp,\n    M02_AXI_rvalid,\n    M02_AXI_wdata,\n    M02_AXI_wlast,\n    M02_AXI_wready,\n    M02_AXI_wstrb,\n    M02_AXI_wvalid,\n    M03_ACLK,\n    M03_ARESETN,\n    M03_AXI_araddr,\n    M03_AXI_arburst,\n    M03_AXI_arcache,\n    M03_AXI_arid,\n    M03_AXI_arlen,\n    M03_AXI_arlock,\n    M03_AXI_arprot,\n    M03_AXI_arqos,\n    M03_AXI_arready,\n    M03_AXI_arregion,\n    M03_AXI_arsize,\n    M03_AXI_arvalid,\n    M03_AXI_awaddr,\n    M03_AXI_awburst,\n    M03_AXI_awcache,\n    M03_AXI_awid,\n    M03_AXI_awlen,\n    M03_AXI_awlock,\n    M03_AXI_awprot,\n    M03_AXI_awqos,\n    M03_AXI_awready,\n    M03_AXI_awregion,\n    M03_AXI_awsize,\n    M03_AXI_awvalid,\n    M03_AXI_bid,\n    M03_AXI_bready,\n    M03_AXI_bresp,\n    M03_AXI_bvalid,\n    M03_AXI_rdata,\n    M03_AXI_rid,\n    M03_AXI_rlast,\n    M03_AXI_rready,\n    M03_AXI_rresp,\n    M03_AXI_rvalid,\n    M03_AXI_wdata,\n    M03_AXI_wlast,\n    M03_AXI_wready,\n    M03_AXI_wstrb,\n    M03_AXI_wvalid,\n    S00_ACLK,\n    S00_ARESETN,\n    S00_AXI_araddr,\n    S00_AXI_arburst,\n    S00_AXI_arcache,\n    S00_AXI_arid,\n    S00_AXI_arlen,\n    S00_AXI_arlock,\n    S00_AXI_arprot,\n    S00_AXI_arqos,\n    S00_AXI_arready,\n    S00_AXI_arregion,\n    S00_AXI_arsize,\n    S00_AXI_arvalid,\n    S00_AXI_awaddr,\n    S00_AXI_awburst,\n    S00_AXI_awcache,\n    S00_AXI_awid,\n    S00_AXI_awlen,\n    S00_AXI_awlock,\n    S00_AXI_awprot,\n    S00_AXI_awqos,\n    S00_AXI_awready,\n    S00_AXI_awregion,\n    S00_AXI_awsize,\n    S00_AXI_awvalid,\n    S00_AXI_bid,\n    S00_AXI_bready,\n    S00_AXI_bresp,\n    S00_AXI_bvalid,\n    S00_AXI_rdata,\n    S00_AXI_rid,\n    S00_AXI_rlast,\n    S00_AXI_rready,\n    S00_AXI_rresp,\n    S00_AXI_rvalid,\n    S00_AXI_wdata,\n    S00_AXI_wlast,\n    S00_AXI_wready,\n    S00_AXI_wstrb,\n    S00_AXI_wvalid,\n    S01_ACLK,\n    S01_ARESETN,\n    S01_AXI_araddr,\n    S01_AXI_arburst,\n    S01_AXI_arcache,\n    S01_AXI_arid,\n    S01_AXI_arlen,\n    S01_AXI_arlock,\n    S01_AXI_arprot,\n    S01_AXI_arqos,\n    S01_AXI_arready,\n    S01_AXI_arregion,\n    S01_AXI_arsize,\n    S01_AXI_arvalid,\n    S01_AXI_awaddr,\n    S01_AXI_awburst,\n    S01_AXI_awcache,\n    S01_AXI_awid,\n    S01_AXI_awlen,\n    S01_AXI_awlock,\n    S01_AXI_awprot,\n    S01_AXI_awqos,\n    S01_AXI_awready,\n    S01_AXI_awregion,\n    S01_AXI_awsize,\n    S01_AXI_awvalid,\n    S01_AXI_bid,\n    S01_AXI_bready,\n    S01_AXI_bresp,\n    S01_AXI_bvalid,\n    S01_AXI_rdata,\n    S01_AXI_rid,\n    S01_AXI_rlast,\n    S01_AXI_rready,\n    S01_AXI_rresp,\n    S01_AXI_rvalid,\n    S01_AXI_wdata,\n    S01_AXI_wlast,\n    S01_AXI_wready,\n    S01_AXI_wstrb,\n    S01_AXI_wvalid);\n  input ACLK;\n  input ARESETN;\n  input M00_ACLK;\n  input M00_ARESETN;\n  output [63:0]M00_AXI_araddr;\n  output [1:0]M00_AXI_arburst;\n  output [3:0]M00_AXI_arcache;\n  output [6:0]M00_AXI_arid;\n  output [7:0]M00_AXI_arlen;\n  output [0:0]M00_AXI_arlock;\n  output [2:0]M00_AXI_arprot;\n  output [3:0]M00_AXI_arqos;\n  input M00_AXI_arready;\n  output [3:0]M00_AXI_arregion;\n  output [2:0]M00_AXI_arsize;\n  output M00_AXI_arvalid;\n  output [63:0]M00_AXI_awaddr;\n  output [1:0]M00_AXI_awburst;\n  output [3:0]M00_AXI_awcache;\n  output [6:0]M00_AXI_awid;\n  output [7:0]M00_AXI_awlen;\n  output [0:0]M00_AXI_awlock;\n  output [2:0]M00_AXI_awprot;\n  output [3:0]M00_AXI_awqos;\n  input M00_AXI_awready;\n  output [3:0]M00_AXI_awregion;\n  output [2:0]M00_AXI_awsize;\n  output M00_AXI_awvalid;\n  input [6:0]M00_AXI_bid;\n  output M00_AXI_bready;\n  input [1:0]M00_AXI_bresp;\n  input M00_AXI_bvalid;\n  input [511:0]M00_AXI_rdata;\n  input [6:0]M00_AXI_rid;\n  input M00_AXI_rlast;\n  output M00_AXI_rready;\n  input [1:0]M00_AXI_rresp;\n  input M00_AXI_rvalid;\n  output [511:0]M00_AXI_wdata;\n  output M00_AXI_wlast;\n  input M00_AXI_wready;\n  output [63:0]M00_AXI_wstrb;\n  output M00_AXI_wvalid;\n  input M01_ACLK;\n  input M01_ARESETN;\n  output [63:0]M01_AXI_araddr;\n  output [1:0]M01_AXI_arburst;\n  output [3:0]M01_AXI_arcache;\n  output [6:0]M01_AXI_arid;\n  output [7:0]M01_AXI_arlen;\n  output [0:0]M01_AXI_arlock;\n  output [2:0]M01_AXI_arprot;\n  output [3:0]M01_AXI_arqos;\n  input M01_AXI_arready;\n  output [3:0]M01_AXI_arregion;\n  output [2:0]M01_AXI_arsize;\n  output M01_AXI_arvalid;\n  output [63:0]M01_AXI_awaddr;\n  output [1:0]M01_AXI_awburst;\n  output [3:0]M01_AXI_awcache;\n  output [6:0]M01_AXI_awid;\n  output [7:0]M01_AXI_awlen;\n  output [0:0]M01_AXI_awlock;\n  output [2:0]M01_AXI_awprot;\n  output [3:0]M01_AXI_awqos;\n  input M01_AXI_awready;\n  output [3:0]M01_AXI_awregion;\n  output [2:0]M01_AXI_awsize;\n  output M01_AXI_awvalid;\n  input [6:0]M01_AXI_bid;\n  output M01_AXI_bready;\n  input [1:0]M01_AXI_bresp;\n  input M01_AXI_bvalid;\n  input [511:0]M01_AXI_rdata;\n  input [6:0]M01_AXI_rid;\n  input M01_AXI_rlast;\n  output M01_AXI_rready;\n  input [1:0]M01_AXI_rresp;\n  input M01_AXI_rvalid;\n  output [511:0]M01_AXI_wdata;\n  output M01_AXI_wlast;\n  input M01_AXI_wready;\n  output [63:0]M01_AXI_wstrb;\n  output M01_AXI_wvalid;\n  input M02_ACLK;\n  input M02_ARESETN;\n  output [63:0]M02_AXI_araddr;\n  output [1:0]M02_AXI_arburst;\n  output [3:0]M02_AXI_arcache;\n  output [6:0]M02_AXI_arid;\n  output [7:0]M02_AXI_arlen;\n  output [0:0]M02_AXI_arlock;\n  output [2:0]M02_AXI_arprot;\n  output [3:0]M02_AXI_arqos;\n  input M02_AXI_arready;\n  output [3:0]M02_AXI_arregion;\n  output [2:0]M02_AXI_arsize;\n  output M02_AXI_arvalid;\n  output [63:0]M02_AXI_awaddr;\n  output [1:0]M02_AXI_awburst;\n  output [3:0]M02_AXI_awcache;\n  output [6:0]M02_AXI_awid;\n  output [7:0]M02_AXI_awlen;\n  output [0:0]M02_AXI_awlock;\n  output [2:0]M02_AXI_awprot;\n  output [3:0]M02_AXI_awqos;\n  input M02_AXI_awready;\n  output [3:0]M02_AXI_awregion;\n  output [2:0]M02_AXI_awsize;\n  output M02_AXI_awvalid;\n  input [6:0]M02_AXI_bid;\n  output M02_AXI_bready;\n  input [1:0]M02_AXI_bresp;\n  input M02_AXI_bvalid;\n  input [511:0]M02_AXI_rdata;\n  input [6:0]M02_AXI_rid;\n  input M02_AXI_rlast;\n  output M02_AXI_rready;\n  input [1:0]M02_AXI_rresp;\n  input M02_AXI_rvalid;\n  output [511:0]M02_AXI_wdata;\n  output M02_AXI_wlast;\n  input M02_AXI_wready;\n  output [63:0]M02_AXI_wstrb;\n  output M02_AXI_wvalid;\n  input M03_ACLK;\n  input M03_ARESETN;\n  output [63:0]M03_AXI_araddr;\n  output [1:0]M03_AXI_arburst;\n  output [3:0]M03_AXI_arcache;\n  output [6:0]M03_AXI_arid;\n  output [7:0]M03_AXI_arlen;\n  output [0:0]M03_AXI_arlock;\n  output [2:0]M03_AXI_arprot;\n  output [3:0]M03_AXI_arqos;\n  input M03_AXI_arready;\n  output [3:0]M03_AXI_arregion;\n  output [2:0]M03_AXI_arsize;\n  output M03_AXI_arvalid;\n  output [63:0]M03_AXI_awaddr;\n  output [1:0]M03_AXI_awburst;\n  output [3:0]M03_AXI_awcache;\n  output [6:0]M03_AXI_awid;\n  output [7:0]M03_AXI_awlen;\n  output [0:0]M03_AXI_awlock;\n  output [2:0]M03_AXI_awprot;\n  output [3:0]M03_AXI_awqos;\n  input M03_AXI_awready;\n  output [3:0]M03_AXI_awregion;\n  output [2:0]M03_AXI_awsize;\n  output M03_AXI_awvalid;\n  input [6:0]M03_AXI_bid;\n  output M03_AXI_bready;\n  input [1:0]M03_AXI_bresp;\n  input M03_AXI_bvalid;\n  input [511:0]M03_AXI_rdata;\n  input [6:0]M03_AXI_rid;\n  input M03_AXI_rlast;\n  output M03_AXI_rready;\n  input [1:0]M03_AXI_rresp;\n  input M03_AXI_rvalid;\n  output [511:0]M03_AXI_wdata;\n  output M03_AXI_wlast;\n  input M03_AXI_wready;\n  output [63:0]M03_AXI_wstrb;\n  output M03_AXI_wvalid;\n  input S00_ACLK;\n  input S00_ARESETN;\n  input [63:0]S00_AXI_araddr;\n  input [1:0]S00_AXI_arburst;\n  input [3:0]S00_AXI_arcache;\n  input [5:0]S00_AXI_arid;\n  input [7:0]S00_AXI_arlen;\n  input [0:0]S00_AXI_arlock;\n  input [2:0]S00_AXI_arprot;\n  input [3:0]S00_AXI_arqos;\n  output S00_AXI_arready;\n  input [3:0]S00_AXI_arregion;\n  input [2:0]S00_AXI_arsize;\n  input S00_AXI_arvalid;\n  input [63:0]S00_AXI_awaddr;\n  input [1:0]S00_AXI_awburst;\n  input [3:0]S00_AXI_awcache;\n  input [5:0]S00_AXI_awid;\n  input [7:0]S00_AXI_awlen;\n  input [0:0]S00_AXI_awlock;\n  input [2:0]S00_AXI_awprot;\n  input [3:0]S00_AXI_awqos;\n  output S00_AXI_awready;\n  input [3:0]S00_AXI_awregion;\n  input [2:0]S00_AXI_awsize;\n  input S00_AXI_awvalid;\n  output [5:0]S00_AXI_bid;\n  input S00_AXI_bready;\n  output [1:0]S00_AXI_bresp;\n  output S00_AXI_bvalid;\n  output [511:0]S00_AXI_rdata;\n  output [5:0]S00_AXI_rid;\n  output S00_AXI_rlast;\n  input S00_AXI_rready;\n  output [1:0]S00_AXI_rresp;\n  output S00_AXI_rvalid;\n  input [511:0]S00_AXI_wdata;\n  input S00_AXI_wlast;\n  output S00_AXI_wready;\n  input [63:0]S00_AXI_wstrb;\n  input S00_AXI_wvalid;\n  input S01_ACLK;\n  input S01_ARESETN;\n  input [63:0]S01_AXI_araddr;\n  input [1:0]S01_AXI_arburst;\n  input [3:0]S01_AXI_arcache;\n  input [5:0]S01_AXI_arid;\n  input [7:0]S01_AXI_arlen;\n  input [0:0]S01_AXI_arlock;\n  input [2:0]S01_AXI_arprot;\n  input [3:0]S01_AXI_arqos;\n  output S01_AXI_arready;\n  input [3:0]S01_AXI_arregion;\n  input [2:0]S01_AXI_arsize;\n  input S01_AXI_arvalid;\n  input [63:0]S01_AXI_awaddr;\n  input [1:0]S01_AXI_awburst;\n  input [3:0]S01_AXI_awcache;\n  input [5:0]S01_AXI_awid;\n  input [7:0]S01_AXI_awlen;\n  input [0:0]S01_AXI_awlock;\n  input [2:0]S01_AXI_awprot;\n  input [3:0]S01_AXI_awqos;\n  output S01_AXI_awready;\n  input [3:0]S01_AXI_awregion;\n  input [2:0]S01_AXI_awsize;\n  input S01_AXI_awvalid;\n  output [5:0]S01_AXI_bid;\n  input S01_AXI_bready;\n  output [1:0]S01_AXI_bresp;\n  output S01_AXI_bvalid;\n  output [511:0]S01_AXI_rdata;\n  output [5:0]S01_AXI_rid;\n  output S01_AXI_rlast;\n  input S01_AXI_rready;\n  output [1:0]S01_AXI_rresp;\n  output S01_AXI_rvalid;\n  input [511:0]S01_AXI_wdata;\n  input S01_AXI_wlast;\n  output S01_AXI_wready;\n  input [63:0]S01_AXI_wstrb;\n  input S01_AXI_wvalid;\n\n  wire axi_interconnect_0_ACLK_net;\n  wire axi_interconnect_0_ARESETN_net;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_ARADDR;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_ARBURST;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARCACHE;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_ARID;\n  wire [7:0]axi_interconnect_0_to_s00_couplers_ARLEN;\n  wire [0:0]axi_interconnect_0_to_s00_couplers_ARLOCK;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_ARPROT;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARQOS;\n  wire axi_interconnect_0_to_s00_couplers_ARREADY;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_ARREGION;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_ARSIZE;\n  wire axi_interconnect_0_to_s00_couplers_ARVALID;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_AWADDR;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_AWBURST;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWCACHE;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_AWID;\n  wire [7:0]axi_interconnect_0_to_s00_couplers_AWLEN;\n  wire [0:0]axi_interconnect_0_to_s00_couplers_AWLOCK;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_AWPROT;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWQOS;\n  wire axi_interconnect_0_to_s00_couplers_AWREADY;\n  wire [3:0]axi_interconnect_0_to_s00_couplers_AWREGION;\n  wire [2:0]axi_interconnect_0_to_s00_couplers_AWSIZE;\n  wire axi_interconnect_0_to_s00_couplers_AWVALID;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_BID;\n  wire axi_interconnect_0_to_s00_couplers_BREADY;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_BRESP;\n  wire axi_interconnect_0_to_s00_couplers_BVALID;\n  wire [511:0]axi_interconnect_0_to_s00_couplers_RDATA;\n  wire [5:0]axi_interconnect_0_to_s00_couplers_RID;\n  wire axi_interconnect_0_to_s00_couplers_RLAST;\n  wire axi_interconnect_0_to_s00_couplers_RREADY;\n  wire [1:0]axi_interconnect_0_to_s00_couplers_RRESP;\n  wire axi_interconnect_0_to_s00_couplers_RVALID;\n  wire [511:0]axi_interconnect_0_to_s00_couplers_WDATA;\n  wire axi_interconnect_0_to_s00_couplers_WLAST;\n  wire axi_interconnect_0_to_s00_couplers_WREADY;\n  wire [63:0]axi_interconnect_0_to_s00_couplers_WSTRB;\n  wire axi_interconnect_0_to_s00_couplers_WVALID;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_ARADDR;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_ARBURST;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARCACHE;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_ARID;\n  wire [7:0]axi_interconnect_0_to_s01_couplers_ARLEN;\n  wire [0:0]axi_interconnect_0_to_s01_couplers_ARLOCK;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_ARPROT;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARQOS;\n  wire axi_interconnect_0_to_s01_couplers_ARREADY;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_ARREGION;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_ARSIZE;\n  wire axi_interconnect_0_to_s01_couplers_ARVALID;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_AWADDR;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_AWBURST;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWCACHE;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_AWID;\n  wire [7:0]axi_interconnect_0_to_s01_couplers_AWLEN;\n  wire [0:0]axi_interconnect_0_to_s01_couplers_AWLOCK;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_AWPROT;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWQOS;\n  wire axi_interconnect_0_to_s01_couplers_AWREADY;\n  wire [3:0]axi_interconnect_0_to_s01_couplers_AWREGION;\n  wire [2:0]axi_interconnect_0_to_s01_couplers_AWSIZE;\n  wire axi_interconnect_0_to_s01_couplers_AWVALID;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_BID;\n  wire axi_interconnect_0_to_s01_couplers_BREADY;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_BRESP;\n  wire axi_interconnect_0_to_s01_couplers_BVALID;\n  wire [511:0]axi_interconnect_0_to_s01_couplers_RDATA;\n  wire [5:0]axi_interconnect_0_to_s01_couplers_RID;\n  wire axi_interconnect_0_to_s01_couplers_RLAST;\n  wire axi_interconnect_0_to_s01_couplers_RREADY;\n  wire [1:0]axi_interconnect_0_to_s01_couplers_RRESP;\n  wire axi_interconnect_0_to_s01_couplers_RVALID;\n  wire [511:0]axi_interconnect_0_to_s01_couplers_WDATA;\n  wire axi_interconnect_0_to_s01_couplers_WLAST;\n  wire axi_interconnect_0_to_s01_couplers_WREADY;\n  wire [63:0]axi_interconnect_0_to_s01_couplers_WSTRB;\n  wire axi_interconnect_0_to_s01_couplers_WVALID;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m00_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m00_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARQOS;\n  wire m00_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m00_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m00_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m00_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWQOS;\n  wire m00_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m00_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m00_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m00_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_BID;\n  wire m00_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_BRESP;\n  wire m00_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m00_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m00_couplers_to_axi_interconnect_0_RID;\n  wire m00_couplers_to_axi_interconnect_0_RLAST;\n  wire m00_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m00_couplers_to_axi_interconnect_0_RRESP;\n  wire m00_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m00_couplers_to_axi_interconnect_0_WDATA;\n  wire m00_couplers_to_axi_interconnect_0_WLAST;\n  wire m00_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m00_couplers_to_axi_interconnect_0_WSTRB;\n  wire m00_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m01_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m01_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARQOS;\n  wire m01_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m01_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m01_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m01_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWQOS;\n  wire m01_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m01_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m01_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m01_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_BID;\n  wire m01_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_BRESP;\n  wire m01_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m01_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m01_couplers_to_axi_interconnect_0_RID;\n  wire m01_couplers_to_axi_interconnect_0_RLAST;\n  wire m01_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m01_couplers_to_axi_interconnect_0_RRESP;\n  wire m01_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m01_couplers_to_axi_interconnect_0_WDATA;\n  wire m01_couplers_to_axi_interconnect_0_WLAST;\n  wire m01_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m01_couplers_to_axi_interconnect_0_WSTRB;\n  wire m01_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m02_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m02_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARQOS;\n  wire m02_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m02_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m02_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m02_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWQOS;\n  wire m02_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m02_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m02_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m02_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_BID;\n  wire m02_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_BRESP;\n  wire m02_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m02_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m02_couplers_to_axi_interconnect_0_RID;\n  wire m02_couplers_to_axi_interconnect_0_RLAST;\n  wire m02_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m02_couplers_to_axi_interconnect_0_RRESP;\n  wire m02_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m02_couplers_to_axi_interconnect_0_WDATA;\n  wire m02_couplers_to_axi_interconnect_0_WLAST;\n  wire m02_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m02_couplers_to_axi_interconnect_0_WSTRB;\n  wire m02_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_ARADDR;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_ARBURST;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARCACHE;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_ARID;\n  wire [7:0]m03_couplers_to_axi_interconnect_0_ARLEN;\n  wire [0:0]m03_couplers_to_axi_interconnect_0_ARLOCK;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_ARPROT;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARQOS;\n  wire m03_couplers_to_axi_interconnect_0_ARREADY;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_ARREGION;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_ARSIZE;\n  wire m03_couplers_to_axi_interconnect_0_ARVALID;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_AWADDR;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_AWBURST;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWCACHE;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_AWID;\n  wire [7:0]m03_couplers_to_axi_interconnect_0_AWLEN;\n  wire [0:0]m03_couplers_to_axi_interconnect_0_AWLOCK;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_AWPROT;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWQOS;\n  wire m03_couplers_to_axi_interconnect_0_AWREADY;\n  wire [3:0]m03_couplers_to_axi_interconnect_0_AWREGION;\n  wire [2:0]m03_couplers_to_axi_interconnect_0_AWSIZE;\n  wire m03_couplers_to_axi_interconnect_0_AWVALID;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_BID;\n  wire m03_couplers_to_axi_interconnect_0_BREADY;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_BRESP;\n  wire m03_couplers_to_axi_interconnect_0_BVALID;\n  wire [511:0]m03_couplers_to_axi_interconnect_0_RDATA;\n  wire [6:0]m03_couplers_to_axi_interconnect_0_RID;\n  wire m03_couplers_to_axi_interconnect_0_RLAST;\n  wire m03_couplers_to_axi_interconnect_0_RREADY;\n  wire [1:0]m03_couplers_to_axi_interconnect_0_RRESP;\n  wire m03_couplers_to_axi_interconnect_0_RVALID;\n  wire [511:0]m03_couplers_to_axi_interconnect_0_WDATA;\n  wire m03_couplers_to_axi_interconnect_0_WLAST;\n  wire m03_couplers_to_axi_interconnect_0_WREADY;\n  wire [63:0]m03_couplers_to_axi_interconnect_0_WSTRB;\n  wire m03_couplers_to_axi_interconnect_0_WVALID;\n  wire [63:0]s00_couplers_to_xbar_ARADDR;\n  wire [1:0]s00_couplers_to_xbar_ARBURST;\n  wire [3:0]s00_couplers_to_xbar_ARCACHE;\n  wire [5:0]s00_couplers_to_xbar_ARID;\n  wire [7:0]s00_couplers_to_xbar_ARLEN;\n  wire [0:0]s00_couplers_to_xbar_ARLOCK;\n  wire [2:0]s00_couplers_to_xbar_ARPROT;\n  wire [3:0]s00_couplers_to_xbar_ARQOS;\n  wire [0:0]s00_couplers_to_xbar_ARREADY;\n  wire [2:0]s00_couplers_to_xbar_ARSIZE;\n  wire s00_couplers_to_xbar_ARVALID;\n  wire [63:0]s00_couplers_to_xbar_AWADDR;\n  wire [1:0]s00_couplers_to_xbar_AWBURST;\n  wire [3:0]s00_couplers_to_xbar_AWCACHE;\n  wire [5:0]s00_couplers_to_xbar_AWID;\n  wire [7:0]s00_couplers_to_xbar_AWLEN;\n  wire [0:0]s00_couplers_to_xbar_AWLOCK;\n  wire [2:0]s00_couplers_to_xbar_AWPROT;\n  wire [3:0]s00_couplers_to_xbar_AWQOS;\n  wire [0:0]s00_couplers_to_xbar_AWREADY;\n  wire [2:0]s00_couplers_to_xbar_AWSIZE;\n  wire s00_couplers_to_xbar_AWVALID;\n  wire [6:0]s00_couplers_to_xbar_BID;\n  wire s00_couplers_to_xbar_BREADY;\n  wire [1:0]s00_couplers_to_xbar_BRESP;\n  wire [0:0]s00_couplers_to_xbar_BVALID;\n  wire [511:0]s00_couplers_to_xbar_RDATA;\n  wire [6:0]s00_couplers_to_xbar_RID;\n  wire [0:0]s00_couplers_to_xbar_RLAST;\n  wire s00_couplers_to_xbar_RREADY;\n  wire [1:0]s00_couplers_to_xbar_RRESP;\n  wire [0:0]s00_couplers_to_xbar_RVALID;\n  wire [511:0]s00_couplers_to_xbar_WDATA;\n  wire s00_couplers_to_xbar_WLAST;\n  wire [0:0]s00_couplers_to_xbar_WREADY;\n  wire [63:0]s00_couplers_to_xbar_WSTRB;\n  wire s00_couplers_to_xbar_WVALID;\n  wire [63:0]s01_couplers_to_xbar_ARADDR;\n  wire [1:0]s01_couplers_to_xbar_ARBURST;\n  wire [3:0]s01_couplers_to_xbar_ARCACHE;\n  wire [5:0]s01_couplers_to_xbar_ARID;\n  wire [7:0]s01_couplers_to_xbar_ARLEN;\n  wire [0:0]s01_couplers_to_xbar_ARLOCK;\n  wire [2:0]s01_couplers_to_xbar_ARPROT;\n  wire [3:0]s01_couplers_to_xbar_ARQOS;\n  wire [1:1]s01_couplers_to_xbar_ARREADY;\n  wire [2:0]s01_couplers_to_xbar_ARSIZE;\n  wire s01_couplers_to_xbar_ARVALID;\n  wire [63:0]s01_couplers_to_xbar_AWADDR;\n  wire [1:0]s01_couplers_to_xbar_AWBURST;\n  wire [3:0]s01_couplers_to_xbar_AWCACHE;\n  wire [5:0]s01_couplers_to_xbar_AWID;\n  wire [7:0]s01_couplers_to_xbar_AWLEN;\n  wire [0:0]s01_couplers_to_xbar_AWLOCK;\n  wire [2:0]s01_couplers_to_xbar_AWPROT;\n  wire [3:0]s01_couplers_to_xbar_AWQOS;\n  wire [1:1]s01_couplers_to_xbar_AWREADY;\n  wire [2:0]s01_couplers_to_xbar_AWSIZE;\n  wire s01_couplers_to_xbar_AWVALID;\n  wire [13:7]s01_couplers_to_xbar_BID;\n  wire s01_couplers_to_xbar_BREADY;\n  wire [3:2]s01_couplers_to_xbar_BRESP;\n  wire [1:1]s01_couplers_to_xbar_BVALID;\n  wire [1023:512]s01_couplers_to_xbar_RDATA;\n  wire [13:7]s01_couplers_to_xbar_RID;\n  wire [1:1]s01_couplers_to_xbar_RLAST;\n  wire s01_couplers_to_xbar_RREADY;\n  wire [3:2]s01_couplers_to_xbar_RRESP;\n  wire [1:1]s01_couplers_to_xbar_RVALID;\n  wire [511:0]s01_couplers_to_xbar_WDATA;\n  wire s01_couplers_to_xbar_WLAST;\n  wire [1:1]s01_couplers_to_xbar_WREADY;\n  wire [63:0]s01_couplers_to_xbar_WSTRB;\n  wire s01_couplers_to_xbar_WVALID;\n  wire [63:0]xbar_to_m00_couplers_ARADDR;\n  wire [1:0]xbar_to_m00_couplers_ARBURST;\n  wire [3:0]xbar_to_m00_couplers_ARCACHE;\n  wire [6:0]xbar_to_m00_couplers_ARID;\n  wire [7:0]xbar_to_m00_couplers_ARLEN;\n  wire [0:0]xbar_to_m00_couplers_ARLOCK;\n  wire [2:0]xbar_to_m00_couplers_ARPROT;\n  wire [3:0]xbar_to_m00_couplers_ARQOS;\n  wire xbar_to_m00_couplers_ARREADY;\n  wire [3:0]xbar_to_m00_couplers_ARREGION;\n  wire [2:0]xbar_to_m00_couplers_ARSIZE;\n  wire [0:0]xbar_to_m00_couplers_ARVALID;\n  wire [63:0]xbar_to_m00_couplers_AWADDR;\n  wire [1:0]xbar_to_m00_couplers_AWBURST;\n  wire [3:0]xbar_to_m00_couplers_AWCACHE;\n  wire [6:0]xbar_to_m00_couplers_AWID;\n  wire [7:0]xbar_to_m00_couplers_AWLEN;\n  wire [0:0]xbar_to_m00_couplers_AWLOCK;\n  wire [2:0]xbar_to_m00_couplers_AWPROT;\n  wire [3:0]xbar_to_m00_couplers_AWQOS;\n  wire xbar_to_m00_couplers_AWREADY;\n  wire [3:0]xbar_to_m00_couplers_AWREGION;\n  wire [2:0]xbar_to_m00_couplers_AWSIZE;\n  wire [0:0]xbar_to_m00_couplers_AWVALID;\n  wire [6:0]xbar_to_m00_couplers_BID;\n  wire [0:0]xbar_to_m00_couplers_BREADY;\n  wire [1:0]xbar_to_m00_couplers_BRESP;\n  wire xbar_to_m00_couplers_BVALID;\n  wire [511:0]xbar_to_m00_couplers_RDATA;\n  wire [6:0]xbar_to_m00_couplers_RID;\n  wire xbar_to_m00_couplers_RLAST;\n  wire [0:0]xbar_to_m00_couplers_RREADY;\n  wire [1:0]xbar_to_m00_couplers_RRESP;\n  wire xbar_to_m00_couplers_RVALID;\n  wire [511:0]xbar_to_m00_couplers_WDATA;\n  wire [0:0]xbar_to_m00_couplers_WLAST;\n  wire xbar_to_m00_couplers_WREADY;\n  wire [63:0]xbar_to_m00_couplers_WSTRB;\n  wire [0:0]xbar_to_m00_couplers_WVALID;\n  wire [127:64]xbar_to_m01_couplers_ARADDR;\n  wire [3:2]xbar_to_m01_couplers_ARBURST;\n  wire [7:4]xbar_to_m01_couplers_ARCACHE;\n  wire [13:7]xbar_to_m01_couplers_ARID;\n  wire [15:8]xbar_to_m01_couplers_ARLEN;\n  wire [1:1]xbar_to_m01_couplers_ARLOCK;\n  wire [5:3]xbar_to_m01_couplers_ARPROT;\n  wire [7:4]xbar_to_m01_couplers_ARQOS;\n  wire xbar_to_m01_couplers_ARREADY;\n  wire [7:4]xbar_to_m01_couplers_ARREGION;\n  wire [5:3]xbar_to_m01_couplers_ARSIZE;\n  wire [1:1]xbar_to_m01_couplers_ARVALID;\n  wire [127:64]xbar_to_m01_couplers_AWADDR;\n  wire [3:2]xbar_to_m01_couplers_AWBURST;\n  wire [7:4]xbar_to_m01_couplers_AWCACHE;\n  wire [13:7]xbar_to_m01_couplers_AWID;\n  wire [15:8]xbar_to_m01_couplers_AWLEN;\n  wire [1:1]xbar_to_m01_couplers_AWLOCK;\n  wire [5:3]xbar_to_m01_couplers_AWPROT;\n  wire [7:4]xbar_to_m01_couplers_AWQOS;\n  wire xbar_to_m01_couplers_AWREADY;\n  wire [7:4]xbar_to_m01_couplers_AWREGION;\n  wire [5:3]xbar_to_m01_couplers_AWSIZE;\n  wire [1:1]xbar_to_m01_couplers_AWVALID;\n  wire [6:0]xbar_to_m01_couplers_BID;\n  wire [1:1]xbar_to_m01_couplers_BREADY;\n  wire [1:0]xbar_to_m01_couplers_BRESP;\n  wire xbar_to_m01_couplers_BVALID;\n  wire [511:0]xbar_to_m01_couplers_RDATA;\n  wire [6:0]xbar_to_m01_couplers_RID;\n  wire xbar_to_m01_couplers_RLAST;\n  wire [1:1]xbar_to_m01_couplers_RREADY;\n  wire [1:0]xbar_to_m01_couplers_RRESP;\n  wire xbar_to_m01_couplers_RVALID;\n  wire [1023:512]xbar_to_m01_couplers_WDATA;\n  wire [1:1]xbar_to_m01_couplers_WLAST;\n  wire xbar_to_m01_couplers_WREADY;\n  wire [127:64]xbar_to_m01_couplers_WSTRB;\n  wire [1:1]xbar_to_m01_couplers_WVALID;\n  wire [191:128]xbar_to_m02_couplers_ARADDR;\n  wire [5:4]xbar_to_m02_couplers_ARBURST;\n  wire [11:8]xbar_to_m02_couplers_ARCACHE;\n  wire [20:14]xbar_to_m02_couplers_ARID;\n  wire [23:16]xbar_to_m02_couplers_ARLEN;\n  wire [2:2]xbar_to_m02_couplers_ARLOCK;\n  wire [8:6]xbar_to_m02_couplers_ARPROT;\n  wire [11:8]xbar_to_m02_couplers_ARQOS;\n  wire xbar_to_m02_couplers_ARREADY;\n  wire [11:8]xbar_to_m02_couplers_ARREGION;\n  wire [8:6]xbar_to_m02_couplers_ARSIZE;\n  wire [2:2]xbar_to_m02_couplers_ARVALID;\n  wire [191:128]xbar_to_m02_couplers_AWADDR;\n  wire [5:4]xbar_to_m02_couplers_AWBURST;\n  wire [11:8]xbar_to_m02_couplers_AWCACHE;\n  wire [20:14]xbar_to_m02_couplers_AWID;\n  wire [23:16]xbar_to_m02_couplers_AWLEN;\n  wire [2:2]xbar_to_m02_couplers_AWLOCK;\n  wire [8:6]xbar_to_m02_couplers_AWPROT;\n  wire [11:8]xbar_to_m02_couplers_AWQOS;\n  wire xbar_to_m02_couplers_AWREADY;\n  wire [11:8]xbar_to_m02_couplers_AWREGION;\n  wire [8:6]xbar_to_m02_couplers_AWSIZE;\n  wire [2:2]xbar_to_m02_couplers_AWVALID;\n  wire [6:0]xbar_to_m02_couplers_BID;\n  wire [2:2]xbar_to_m02_couplers_BREADY;\n  wire [1:0]xbar_to_m02_couplers_BRESP;\n  wire xbar_to_m02_couplers_BVALID;\n  wire [511:0]xbar_to_m02_couplers_RDATA;\n  wire [6:0]xbar_to_m02_couplers_RID;\n  wire xbar_to_m02_couplers_RLAST;\n  wire [2:2]xbar_to_m02_couplers_RREADY;\n  wire [1:0]xbar_to_m02_couplers_RRESP;\n  wire xbar_to_m02_couplers_RVALID;\n  wire [1535:1024]xbar_to_m02_couplers_WDATA;\n  wire [2:2]xbar_to_m02_couplers_WLAST;\n  wire xbar_to_m02_couplers_WREADY;\n  wire [191:128]xbar_to_m02_couplers_WSTRB;\n  wire [2:2]xbar_to_m02_couplers_WVALID;\n  wire [255:192]xbar_to_m03_couplers_ARADDR;\n  wire [7:6]xbar_to_m03_couplers_ARBURST;\n  wire [15:12]xbar_to_m03_couplers_ARCACHE;\n  wire [27:21]xbar_to_m03_couplers_ARID;\n  wire [31:24]xbar_to_m03_couplers_ARLEN;\n  wire [3:3]xbar_to_m03_couplers_ARLOCK;\n  wire [11:9]xbar_to_m03_couplers_ARPROT;\n  wire [15:12]xbar_to_m03_couplers_ARQOS;\n  wire xbar_to_m03_couplers_ARREADY;\n  wire [15:12]xbar_to_m03_couplers_ARREGION;\n  wire [11:9]xbar_to_m03_couplers_ARSIZE;\n  wire [3:3]xbar_to_m03_couplers_ARVALID;\n  wire [255:192]xbar_to_m03_couplers_AWADDR;\n  wire [7:6]xbar_to_m03_couplers_AWBURST;\n  wire [15:12]xbar_to_m03_couplers_AWCACHE;\n  wire [27:21]xbar_to_m03_couplers_AWID;\n  wire [31:24]xbar_to_m03_couplers_AWLEN;\n  wire [3:3]xbar_to_m03_couplers_AWLOCK;\n  wire [11:9]xbar_to_m03_couplers_AWPROT;\n  wire [15:12]xbar_to_m03_couplers_AWQOS;\n  wire xbar_to_m03_couplers_AWREADY;\n  wire [15:12]xbar_to_m03_couplers_AWREGION;\n  wire [11:9]xbar_to_m03_couplers_AWSIZE;\n  wire [3:3]xbar_to_m03_couplers_AWVALID;\n  wire [6:0]xbar_to_m03_couplers_BID;\n  wire [3:3]xbar_to_m03_couplers_BREADY;\n  wire [1:0]xbar_to_m03_couplers_BRESP;\n  wire xbar_to_m03_couplers_BVALID;\n  wire [511:0]xbar_to_m03_couplers_RDATA;\n  wire [6:0]xbar_to_m03_couplers_RID;\n  wire xbar_to_m03_couplers_RLAST;\n  wire [3:3]xbar_to_m03_couplers_RREADY;\n  wire [1:0]xbar_to_m03_couplers_RRESP;\n  wire xbar_to_m03_couplers_RVALID;\n  wire [2047:1536]xbar_to_m03_couplers_WDATA;\n  wire [3:3]xbar_to_m03_couplers_WLAST;\n  wire xbar_to_m03_couplers_WREADY;\n  wire [255:192]xbar_to_m03_couplers_WSTRB;\n  wire [3:3]xbar_to_m03_couplers_WVALID;\n\n  assign M00_AXI_araddr[63:0] = m00_couplers_to_axi_interconnect_0_ARADDR;\n  assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_interconnect_0_ARBURST;\n  assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M00_AXI_arid[6:0] = m00_couplers_to_axi_interconnect_0_ARID;\n  assign M00_AXI_arlen[7:0] = m00_couplers_to_axi_interconnect_0_ARLEN;\n  assign M00_AXI_arlock[0] = m00_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_interconnect_0_ARPROT;\n  assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_interconnect_0_ARQOS;\n  assign M00_AXI_arregion[3:0] = m00_couplers_to_axi_interconnect_0_ARREGION;\n  assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M00_AXI_arvalid = m00_couplers_to_axi_interconnect_0_ARVALID;\n  assign M00_AXI_awaddr[63:0] = m00_couplers_to_axi_interconnect_0_AWADDR;\n  assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_interconnect_0_AWBURST;\n  assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M00_AXI_awid[6:0] = m00_couplers_to_axi_interconnect_0_AWID;\n  assign M00_AXI_awlen[7:0] = m00_couplers_to_axi_interconnect_0_AWLEN;\n  assign M00_AXI_awlock[0] = m00_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_interconnect_0_AWPROT;\n  assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_interconnect_0_AWQOS;\n  assign M00_AXI_awregion[3:0] = m00_couplers_to_axi_interconnect_0_AWREGION;\n  assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M00_AXI_awvalid = m00_couplers_to_axi_interconnect_0_AWVALID;\n  assign M00_AXI_bready = m00_couplers_to_axi_interconnect_0_BREADY;\n  assign M00_AXI_rready = m00_couplers_to_axi_interconnect_0_RREADY;\n  assign M00_AXI_wdata[511:0] = m00_couplers_to_axi_interconnect_0_WDATA;\n  assign M00_AXI_wlast = m00_couplers_to_axi_interconnect_0_WLAST;\n  assign M00_AXI_wstrb[63:0] = m00_couplers_to_axi_interconnect_0_WSTRB;\n  assign M00_AXI_wvalid = m00_couplers_to_axi_interconnect_0_WVALID;\n  assign M01_AXI_araddr[63:0] = m01_couplers_to_axi_interconnect_0_ARADDR;\n  assign M01_AXI_arburst[1:0] = m01_couplers_to_axi_interconnect_0_ARBURST;\n  assign M01_AXI_arcache[3:0] = m01_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M01_AXI_arid[6:0] = m01_couplers_to_axi_interconnect_0_ARID;\n  assign M01_AXI_arlen[7:0] = m01_couplers_to_axi_interconnect_0_ARLEN;\n  assign M01_AXI_arlock[0] = m01_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M01_AXI_arprot[2:0] = m01_couplers_to_axi_interconnect_0_ARPROT;\n  assign M01_AXI_arqos[3:0] = m01_couplers_to_axi_interconnect_0_ARQOS;\n  assign M01_AXI_arregion[3:0] = m01_couplers_to_axi_interconnect_0_ARREGION;\n  assign M01_AXI_arsize[2:0] = m01_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M01_AXI_arvalid = m01_couplers_to_axi_interconnect_0_ARVALID;\n  assign M01_AXI_awaddr[63:0] = m01_couplers_to_axi_interconnect_0_AWADDR;\n  assign M01_AXI_awburst[1:0] = m01_couplers_to_axi_interconnect_0_AWBURST;\n  assign M01_AXI_awcache[3:0] = m01_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M01_AXI_awid[6:0] = m01_couplers_to_axi_interconnect_0_AWID;\n  assign M01_AXI_awlen[7:0] = m01_couplers_to_axi_interconnect_0_AWLEN;\n  assign M01_AXI_awlock[0] = m01_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M01_AXI_awprot[2:0] = m01_couplers_to_axi_interconnect_0_AWPROT;\n  assign M01_AXI_awqos[3:0] = m01_couplers_to_axi_interconnect_0_AWQOS;\n  assign M01_AXI_awregion[3:0] = m01_couplers_to_axi_interconnect_0_AWREGION;\n  assign M01_AXI_awsize[2:0] = m01_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M01_AXI_awvalid = m01_couplers_to_axi_interconnect_0_AWVALID;\n  assign M01_AXI_bready = m01_couplers_to_axi_interconnect_0_BREADY;\n  assign M01_AXI_rready = m01_couplers_to_axi_interconnect_0_RREADY;\n  assign M01_AXI_wdata[511:0] = m01_couplers_to_axi_interconnect_0_WDATA;\n  assign M01_AXI_wlast = m01_couplers_to_axi_interconnect_0_WLAST;\n  assign M01_AXI_wstrb[63:0] = m01_couplers_to_axi_interconnect_0_WSTRB;\n  assign M01_AXI_wvalid = m01_couplers_to_axi_interconnect_0_WVALID;\n  assign M02_AXI_araddr[63:0] = m02_couplers_to_axi_interconnect_0_ARADDR;\n  assign M02_AXI_arburst[1:0] = m02_couplers_to_axi_interconnect_0_ARBURST;\n  assign M02_AXI_arcache[3:0] = m02_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M02_AXI_arid[6:0] = m02_couplers_to_axi_interconnect_0_ARID;\n  assign M02_AXI_arlen[7:0] = m02_couplers_to_axi_interconnect_0_ARLEN;\n  assign M02_AXI_arlock[0] = m02_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M02_AXI_arprot[2:0] = m02_couplers_to_axi_interconnect_0_ARPROT;\n  assign M02_AXI_arqos[3:0] = m02_couplers_to_axi_interconnect_0_ARQOS;\n  assign M02_AXI_arregion[3:0] = m02_couplers_to_axi_interconnect_0_ARREGION;\n  assign M02_AXI_arsize[2:0] = m02_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M02_AXI_arvalid = m02_couplers_to_axi_interconnect_0_ARVALID;\n  assign M02_AXI_awaddr[63:0] = m02_couplers_to_axi_interconnect_0_AWADDR;\n  assign M02_AXI_awburst[1:0] = m02_couplers_to_axi_interconnect_0_AWBURST;\n  assign M02_AXI_awcache[3:0] = m02_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M02_AXI_awid[6:0] = m02_couplers_to_axi_interconnect_0_AWID;\n  assign M02_AXI_awlen[7:0] = m02_couplers_to_axi_interconnect_0_AWLEN;\n  assign M02_AXI_awlock[0] = m02_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M02_AXI_awprot[2:0] = m02_couplers_to_axi_interconnect_0_AWPROT;\n  assign M02_AXI_awqos[3:0] = m02_couplers_to_axi_interconnect_0_AWQOS;\n  assign M02_AXI_awregion[3:0] = m02_couplers_to_axi_interconnect_0_AWREGION;\n  assign M02_AXI_awsize[2:0] = m02_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M02_AXI_awvalid = m02_couplers_to_axi_interconnect_0_AWVALID;\n  assign M02_AXI_bready = m02_couplers_to_axi_interconnect_0_BREADY;\n  assign M02_AXI_rready = m02_couplers_to_axi_interconnect_0_RREADY;\n  assign M02_AXI_wdata[511:0] = m02_couplers_to_axi_interconnect_0_WDATA;\n  assign M02_AXI_wlast = m02_couplers_to_axi_interconnect_0_WLAST;\n  assign M02_AXI_wstrb[63:0] = m02_couplers_to_axi_interconnect_0_WSTRB;\n  assign M02_AXI_wvalid = m02_couplers_to_axi_interconnect_0_WVALID;\n  assign M03_AXI_araddr[63:0] = m03_couplers_to_axi_interconnect_0_ARADDR;\n  assign M03_AXI_arburst[1:0] = m03_couplers_to_axi_interconnect_0_ARBURST;\n  assign M03_AXI_arcache[3:0] = m03_couplers_to_axi_interconnect_0_ARCACHE;\n  assign M03_AXI_arid[6:0] = m03_couplers_to_axi_interconnect_0_ARID;\n  assign M03_AXI_arlen[7:0] = m03_couplers_to_axi_interconnect_0_ARLEN;\n  assign M03_AXI_arlock[0] = m03_couplers_to_axi_interconnect_0_ARLOCK;\n  assign M03_AXI_arprot[2:0] = m03_couplers_to_axi_interconnect_0_ARPROT;\n  assign M03_AXI_arqos[3:0] = m03_couplers_to_axi_interconnect_0_ARQOS;\n  assign M03_AXI_arregion[3:0] = m03_couplers_to_axi_interconnect_0_ARREGION;\n  assign M03_AXI_arsize[2:0] = m03_couplers_to_axi_interconnect_0_ARSIZE;\n  assign M03_AXI_arvalid = m03_couplers_to_axi_interconnect_0_ARVALID;\n  assign M03_AXI_awaddr[63:0] = m03_couplers_to_axi_interconnect_0_AWADDR;\n  assign M03_AXI_awburst[1:0] = m03_couplers_to_axi_interconnect_0_AWBURST;\n  assign M03_AXI_awcache[3:0] = m03_couplers_to_axi_interconnect_0_AWCACHE;\n  assign M03_AXI_awid[6:0] = m03_couplers_to_axi_interconnect_0_AWID;\n  assign M03_AXI_awlen[7:0] = m03_couplers_to_axi_interconnect_0_AWLEN;\n  assign M03_AXI_awlock[0] = m03_couplers_to_axi_interconnect_0_AWLOCK;\n  assign M03_AXI_awprot[2:0] = m03_couplers_to_axi_interconnect_0_AWPROT;\n  assign M03_AXI_awqos[3:0] = m03_couplers_to_axi_interconnect_0_AWQOS;\n  assign M03_AXI_awregion[3:0] = m03_couplers_to_axi_interconnect_0_AWREGION;\n  assign M03_AXI_awsize[2:0] = m03_couplers_to_axi_interconnect_0_AWSIZE;\n  assign M03_AXI_awvalid = m03_couplers_to_axi_interconnect_0_AWVALID;\n  assign M03_AXI_bready = m03_couplers_to_axi_interconnect_0_BREADY;\n  assign M03_AXI_rready = m03_couplers_to_axi_interconnect_0_RREADY;\n  assign M03_AXI_wdata[511:0] = m03_couplers_to_axi_interconnect_0_WDATA;\n  assign M03_AXI_wlast = m03_couplers_to_axi_interconnect_0_WLAST;\n  assign M03_AXI_wstrb[63:0] = m03_couplers_to_axi_interconnect_0_WSTRB;\n  assign M03_AXI_wvalid = m03_couplers_to_axi_interconnect_0_WVALID;\n  assign S00_AXI_arready = axi_interconnect_0_to_s00_couplers_ARREADY;\n  assign S00_AXI_awready = axi_interconnect_0_to_s00_couplers_AWREADY;\n  assign S00_AXI_bid[5:0] = axi_interconnect_0_to_s00_couplers_BID;\n  assign S00_AXI_bresp[1:0] = axi_interconnect_0_to_s00_couplers_BRESP;\n  assign S00_AXI_bvalid = axi_interconnect_0_to_s00_couplers_BVALID;\n  assign S00_AXI_rdata[511:0] = axi_interconnect_0_to_s00_couplers_RDATA;\n  assign S00_AXI_rid[5:0] = axi_interconnect_0_to_s00_couplers_RID;\n  assign S00_AXI_rlast = axi_interconnect_0_to_s00_couplers_RLAST;\n  assign S00_AXI_rresp[1:0] = axi_interconnect_0_to_s00_couplers_RRESP;\n  assign S00_AXI_rvalid = axi_interconnect_0_to_s00_couplers_RVALID;\n  assign S00_AXI_wready = axi_interconnect_0_to_s00_couplers_WREADY;\n  assign S01_AXI_arready = axi_interconnect_0_to_s01_couplers_ARREADY;\n  assign S01_AXI_awready = axi_interconnect_0_to_s01_couplers_AWREADY;\n  assign S01_AXI_bid[5:0] = axi_interconnect_0_to_s01_couplers_BID;\n  assign S01_AXI_bresp[1:0] = axi_interconnect_0_to_s01_couplers_BRESP;\n  assign S01_AXI_bvalid = axi_interconnect_0_to_s01_couplers_BVALID;\n  assign S01_AXI_rdata[511:0] = axi_interconnect_0_to_s01_couplers_RDATA;\n  assign S01_AXI_rid[5:0] = axi_interconnect_0_to_s01_couplers_RID;\n  assign S01_AXI_rlast = axi_interconnect_0_to_s01_couplers_RLAST;\n  assign S01_AXI_rresp[1:0] = axi_interconnect_0_to_s01_couplers_RRESP;\n  assign S01_AXI_rvalid = axi_interconnect_0_to_s01_couplers_RVALID;\n  assign S01_AXI_wready = axi_interconnect_0_to_s01_couplers_WREADY;\n  assign axi_interconnect_0_ACLK_net = ACLK;\n  assign axi_interconnect_0_ARESETN_net = ARESETN;\n  assign axi_interconnect_0_to_s00_couplers_ARADDR = S00_AXI_araddr[63:0];\n  assign axi_interconnect_0_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];\n  assign axi_interconnect_0_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARID = S00_AXI_arid[5:0];\n  assign axi_interconnect_0_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0];\n  assign axi_interconnect_0_to_s00_couplers_ARLOCK = S00_AXI_arlock[0];\n  assign axi_interconnect_0_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];\n  assign axi_interconnect_0_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARREGION = S00_AXI_arregion[3:0];\n  assign axi_interconnect_0_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];\n  assign axi_interconnect_0_to_s00_couplers_ARVALID = S00_AXI_arvalid;\n  assign axi_interconnect_0_to_s00_couplers_AWADDR = S00_AXI_awaddr[63:0];\n  assign axi_interconnect_0_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];\n  assign axi_interconnect_0_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWID = S00_AXI_awid[5:0];\n  assign axi_interconnect_0_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0];\n  assign axi_interconnect_0_to_s00_couplers_AWLOCK = S00_AXI_awlock[0];\n  assign axi_interconnect_0_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];\n  assign axi_interconnect_0_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWREGION = S00_AXI_awregion[3:0];\n  assign axi_interconnect_0_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];\n  assign axi_interconnect_0_to_s00_couplers_AWVALID = S00_AXI_awvalid;\n  assign axi_interconnect_0_to_s00_couplers_BREADY = S00_AXI_bready;\n  assign axi_interconnect_0_to_s00_couplers_RREADY = S00_AXI_rready;\n  assign axi_interconnect_0_to_s00_couplers_WDATA = S00_AXI_wdata[511:0];\n  assign axi_interconnect_0_to_s00_couplers_WLAST = S00_AXI_wlast;\n  assign axi_interconnect_0_to_s00_couplers_WSTRB = S00_AXI_wstrb[63:0];\n  assign axi_interconnect_0_to_s00_couplers_WVALID = S00_AXI_wvalid;\n  assign axi_interconnect_0_to_s01_couplers_ARADDR = S01_AXI_araddr[63:0];\n  assign axi_interconnect_0_to_s01_couplers_ARBURST = S01_AXI_arburst[1:0];\n  assign axi_interconnect_0_to_s01_couplers_ARCACHE = S01_AXI_arcache[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARID = S01_AXI_arid[5:0];\n  assign axi_interconnect_0_to_s01_couplers_ARLEN = S01_AXI_arlen[7:0];\n  assign axi_interconnect_0_to_s01_couplers_ARLOCK = S01_AXI_arlock[0];\n  assign axi_interconnect_0_to_s01_couplers_ARPROT = S01_AXI_arprot[2:0];\n  assign axi_interconnect_0_to_s01_couplers_ARQOS = S01_AXI_arqos[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARREGION = S01_AXI_arregion[3:0];\n  assign axi_interconnect_0_to_s01_couplers_ARSIZE = S01_AXI_arsize[2:0];\n  assign axi_interconnect_0_to_s01_couplers_ARVALID = S01_AXI_arvalid;\n  assign axi_interconnect_0_to_s01_couplers_AWADDR = S01_AXI_awaddr[63:0];\n  assign axi_interconnect_0_to_s01_couplers_AWBURST = S01_AXI_awburst[1:0];\n  assign axi_interconnect_0_to_s01_couplers_AWCACHE = S01_AXI_awcache[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWID = S01_AXI_awid[5:0];\n  assign axi_interconnect_0_to_s01_couplers_AWLEN = S01_AXI_awlen[7:0];\n  assign axi_interconnect_0_to_s01_couplers_AWLOCK = S01_AXI_awlock[0];\n  assign axi_interconnect_0_to_s01_couplers_AWPROT = S01_AXI_awprot[2:0];\n  assign axi_interconnect_0_to_s01_couplers_AWQOS = S01_AXI_awqos[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWREGION = S01_AXI_awregion[3:0];\n  assign axi_interconnect_0_to_s01_couplers_AWSIZE = S01_AXI_awsize[2:0];\n  assign axi_interconnect_0_to_s01_couplers_AWVALID = S01_AXI_awvalid;\n  assign axi_interconnect_0_to_s01_couplers_BREADY = S01_AXI_bready;\n  assign axi_interconnect_0_to_s01_couplers_RREADY = S01_AXI_rready;\n  assign axi_interconnect_0_to_s01_couplers_WDATA = S01_AXI_wdata[511:0];\n  assign axi_interconnect_0_to_s01_couplers_WLAST = S01_AXI_wlast;\n  assign axi_interconnect_0_to_s01_couplers_WSTRB = S01_AXI_wstrb[63:0];\n  assign axi_interconnect_0_to_s01_couplers_WVALID = S01_AXI_wvalid;\n  assign m00_couplers_to_axi_interconnect_0_ARREADY = M00_AXI_arready;\n  assign m00_couplers_to_axi_interconnect_0_AWREADY = M00_AXI_awready;\n  assign m00_couplers_to_axi_interconnect_0_BID = M00_AXI_bid[6:0];\n  assign m00_couplers_to_axi_interconnect_0_BRESP = M00_AXI_bresp[1:0];\n  assign m00_couplers_to_axi_interconnect_0_BVALID = M00_AXI_bvalid;\n  assign m00_couplers_to_axi_interconnect_0_RDATA = M00_AXI_rdata[511:0];\n  assign m00_couplers_to_axi_interconnect_0_RID = M00_AXI_rid[6:0];\n  assign m00_couplers_to_axi_interconnect_0_RLAST = M00_AXI_rlast;\n  assign m00_couplers_to_axi_interconnect_0_RRESP = M00_AXI_rresp[1:0];\n  assign m00_couplers_to_axi_interconnect_0_RVALID = M00_AXI_rvalid;\n  assign m00_couplers_to_axi_interconnect_0_WREADY = M00_AXI_wready;\n  assign m01_couplers_to_axi_interconnect_0_ARREADY = M01_AXI_arready;\n  assign m01_couplers_to_axi_interconnect_0_AWREADY = M01_AXI_awready;\n  assign m01_couplers_to_axi_interconnect_0_BID = M01_AXI_bid[6:0];\n  assign m01_couplers_to_axi_interconnect_0_BRESP = M01_AXI_bresp[1:0];\n  assign m01_couplers_to_axi_interconnect_0_BVALID = M01_AXI_bvalid;\n  assign m01_couplers_to_axi_interconnect_0_RDATA = M01_AXI_rdata[511:0];\n  assign m01_couplers_to_axi_interconnect_0_RID = M01_AXI_rid[6:0];\n  assign m01_couplers_to_axi_interconnect_0_RLAST = M01_AXI_rlast;\n  assign m01_couplers_to_axi_interconnect_0_RRESP = M01_AXI_rresp[1:0];\n  assign m01_couplers_to_axi_interconnect_0_RVALID = M01_AXI_rvalid;\n  assign m01_couplers_to_axi_interconnect_0_WREADY = M01_AXI_wready;\n  assign m02_couplers_to_axi_interconnect_0_ARREADY = M02_AXI_arready;\n  assign m02_couplers_to_axi_interconnect_0_AWREADY = M02_AXI_awready;\n  assign m02_couplers_to_axi_interconnect_0_BID = M02_AXI_bid[6:0];\n  assign m02_couplers_to_axi_interconnect_0_BRESP = M02_AXI_bresp[1:0];\n  assign m02_couplers_to_axi_interconnect_0_BVALID = M02_AXI_bvalid;\n  assign m02_couplers_to_axi_interconnect_0_RDATA = M02_AXI_rdata[511:0];\n  assign m02_couplers_to_axi_interconnect_0_RID = M02_AXI_rid[6:0];\n  assign m02_couplers_to_axi_interconnect_0_RLAST = M02_AXI_rlast;\n  assign m02_couplers_to_axi_interconnect_0_RRESP = M02_AXI_rresp[1:0];\n  assign m02_couplers_to_axi_interconnect_0_RVALID = M02_AXI_rvalid;\n  assign m02_couplers_to_axi_interconnect_0_WREADY = M02_AXI_wready;\n  assign m03_couplers_to_axi_interconnect_0_ARREADY = M03_AXI_arready;\n  assign m03_couplers_to_axi_interconnect_0_AWREADY = M03_AXI_awready;\n  assign m03_couplers_to_axi_interconnect_0_BID = M03_AXI_bid[6:0];\n  assign m03_couplers_to_axi_interconnect_0_BRESP = M03_AXI_bresp[1:0];\n  assign m03_couplers_to_axi_interconnect_0_BVALID = M03_AXI_bvalid;\n  assign m03_couplers_to_axi_interconnect_0_RDATA = M03_AXI_rdata[511:0];\n  assign m03_couplers_to_axi_interconnect_0_RID = M03_AXI_rid[6:0];\n  assign m03_couplers_to_axi_interconnect_0_RLAST = M03_AXI_rlast;\n  assign m03_couplers_to_axi_interconnect_0_RRESP = M03_AXI_rresp[1:0];\n  assign m03_couplers_to_axi_interconnect_0_RVALID = M03_AXI_rvalid;\n  assign m03_couplers_to_axi_interconnect_0_WREADY = M03_AXI_wready;\n  m00_couplers_imp_1QBJ6U2 m00_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m00_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m00_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m00_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m00_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m00_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m00_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m00_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m00_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m00_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m00_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m00_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m00_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m00_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m00_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m00_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m00_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m00_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m00_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m00_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m00_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m00_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m00_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m00_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m00_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m00_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m00_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m00_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m00_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m00_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m00_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m00_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m00_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m00_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m00_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m00_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m00_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m00_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m00_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m00_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m00_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m00_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m00_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m00_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m00_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m00_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m00_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m00_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m00_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m00_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m00_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m00_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m00_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m00_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m00_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m00_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m00_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m00_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m00_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m00_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m00_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m00_couplers_BID),\n        .S_AXI_bready(xbar_to_m00_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m00_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m00_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m00_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m00_couplers_RID),\n        .S_AXI_rlast(xbar_to_m00_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m00_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m00_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m00_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m00_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m00_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m00_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m00_couplers_WVALID));\n  m01_couplers_imp_10IMR9A m01_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m01_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m01_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m01_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m01_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m01_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m01_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m01_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m01_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m01_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m01_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m01_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m01_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m01_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m01_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m01_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m01_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m01_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m01_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m01_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m01_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m01_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m01_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m01_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m01_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m01_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m01_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m01_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m01_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m01_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m01_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m01_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m01_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m01_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m01_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m01_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m01_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m01_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m01_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m01_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m01_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m01_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m01_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m01_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m01_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m01_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m01_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m01_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m01_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m01_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m01_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m01_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m01_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m01_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m01_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m01_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m01_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m01_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m01_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m01_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m01_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m01_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m01_couplers_BID),\n        .S_AXI_bready(xbar_to_m01_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m01_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m01_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m01_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m01_couplers_RID),\n        .S_AXI_rlast(xbar_to_m01_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m01_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m01_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m01_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m01_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m01_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m01_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m01_couplers_WVALID));\n  m02_couplers_imp_APDUS2 m02_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m02_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m02_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m02_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m02_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m02_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m02_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m02_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m02_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m02_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m02_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m02_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m02_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m02_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m02_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m02_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m02_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m02_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m02_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m02_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m02_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m02_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m02_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m02_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m02_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m02_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m02_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m02_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m02_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m02_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m02_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m02_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m02_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m02_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m02_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m02_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m02_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m02_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m02_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m02_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m02_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m02_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m02_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m02_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m02_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m02_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m02_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m02_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m02_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m02_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m02_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m02_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m02_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m02_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m02_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m02_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m02_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m02_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m02_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m02_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m02_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m02_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m02_couplers_BID),\n        .S_AXI_bready(xbar_to_m02_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m02_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m02_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m02_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m02_couplers_RID),\n        .S_AXI_rlast(xbar_to_m02_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m02_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m02_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m02_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m02_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m02_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m02_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m02_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m02_couplers_WVALID));\n  m03_couplers_imp_JAYOMU m03_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(m03_couplers_to_axi_interconnect_0_ARADDR),\n        .M_AXI_arburst(m03_couplers_to_axi_interconnect_0_ARBURST),\n        .M_AXI_arcache(m03_couplers_to_axi_interconnect_0_ARCACHE),\n        .M_AXI_arid(m03_couplers_to_axi_interconnect_0_ARID),\n        .M_AXI_arlen(m03_couplers_to_axi_interconnect_0_ARLEN),\n        .M_AXI_arlock(m03_couplers_to_axi_interconnect_0_ARLOCK),\n        .M_AXI_arprot(m03_couplers_to_axi_interconnect_0_ARPROT),\n        .M_AXI_arqos(m03_couplers_to_axi_interconnect_0_ARQOS),\n        .M_AXI_arready(m03_couplers_to_axi_interconnect_0_ARREADY),\n        .M_AXI_arregion(m03_couplers_to_axi_interconnect_0_ARREGION),\n        .M_AXI_arsize(m03_couplers_to_axi_interconnect_0_ARSIZE),\n        .M_AXI_arvalid(m03_couplers_to_axi_interconnect_0_ARVALID),\n        .M_AXI_awaddr(m03_couplers_to_axi_interconnect_0_AWADDR),\n        .M_AXI_awburst(m03_couplers_to_axi_interconnect_0_AWBURST),\n        .M_AXI_awcache(m03_couplers_to_axi_interconnect_0_AWCACHE),\n        .M_AXI_awid(m03_couplers_to_axi_interconnect_0_AWID),\n        .M_AXI_awlen(m03_couplers_to_axi_interconnect_0_AWLEN),\n        .M_AXI_awlock(m03_couplers_to_axi_interconnect_0_AWLOCK),\n        .M_AXI_awprot(m03_couplers_to_axi_interconnect_0_AWPROT),\n        .M_AXI_awqos(m03_couplers_to_axi_interconnect_0_AWQOS),\n        .M_AXI_awready(m03_couplers_to_axi_interconnect_0_AWREADY),\n        .M_AXI_awregion(m03_couplers_to_axi_interconnect_0_AWREGION),\n        .M_AXI_awsize(m03_couplers_to_axi_interconnect_0_AWSIZE),\n        .M_AXI_awvalid(m03_couplers_to_axi_interconnect_0_AWVALID),\n        .M_AXI_bid(m03_couplers_to_axi_interconnect_0_BID),\n        .M_AXI_bready(m03_couplers_to_axi_interconnect_0_BREADY),\n        .M_AXI_bresp(m03_couplers_to_axi_interconnect_0_BRESP),\n        .M_AXI_bvalid(m03_couplers_to_axi_interconnect_0_BVALID),\n        .M_AXI_rdata(m03_couplers_to_axi_interconnect_0_RDATA),\n        .M_AXI_rid(m03_couplers_to_axi_interconnect_0_RID),\n        .M_AXI_rlast(m03_couplers_to_axi_interconnect_0_RLAST),\n        .M_AXI_rready(m03_couplers_to_axi_interconnect_0_RREADY),\n        .M_AXI_rresp(m03_couplers_to_axi_interconnect_0_RRESP),\n        .M_AXI_rvalid(m03_couplers_to_axi_interconnect_0_RVALID),\n        .M_AXI_wdata(m03_couplers_to_axi_interconnect_0_WDATA),\n        .M_AXI_wlast(m03_couplers_to_axi_interconnect_0_WLAST),\n        .M_AXI_wready(m03_couplers_to_axi_interconnect_0_WREADY),\n        .M_AXI_wstrb(m03_couplers_to_axi_interconnect_0_WSTRB),\n        .M_AXI_wvalid(m03_couplers_to_axi_interconnect_0_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(xbar_to_m03_couplers_ARADDR),\n        .S_AXI_arburst(xbar_to_m03_couplers_ARBURST),\n        .S_AXI_arcache(xbar_to_m03_couplers_ARCACHE),\n        .S_AXI_arid(xbar_to_m03_couplers_ARID),\n        .S_AXI_arlen(xbar_to_m03_couplers_ARLEN),\n        .S_AXI_arlock(xbar_to_m03_couplers_ARLOCK),\n        .S_AXI_arprot(xbar_to_m03_couplers_ARPROT),\n        .S_AXI_arqos(xbar_to_m03_couplers_ARQOS),\n        .S_AXI_arready(xbar_to_m03_couplers_ARREADY),\n        .S_AXI_arregion(xbar_to_m03_couplers_ARREGION),\n        .S_AXI_arsize(xbar_to_m03_couplers_ARSIZE),\n        .S_AXI_arvalid(xbar_to_m03_couplers_ARVALID),\n        .S_AXI_awaddr(xbar_to_m03_couplers_AWADDR),\n        .S_AXI_awburst(xbar_to_m03_couplers_AWBURST),\n        .S_AXI_awcache(xbar_to_m03_couplers_AWCACHE),\n        .S_AXI_awid(xbar_to_m03_couplers_AWID),\n        .S_AXI_awlen(xbar_to_m03_couplers_AWLEN),\n        .S_AXI_awlock(xbar_to_m03_couplers_AWLOCK),\n        .S_AXI_awprot(xbar_to_m03_couplers_AWPROT),\n        .S_AXI_awqos(xbar_to_m03_couplers_AWQOS),\n        .S_AXI_awready(xbar_to_m03_couplers_AWREADY),\n        .S_AXI_awregion(xbar_to_m03_couplers_AWREGION),\n        .S_AXI_awsize(xbar_to_m03_couplers_AWSIZE),\n        .S_AXI_awvalid(xbar_to_m03_couplers_AWVALID),\n        .S_AXI_bid(xbar_to_m03_couplers_BID),\n        .S_AXI_bready(xbar_to_m03_couplers_BREADY),\n        .S_AXI_bresp(xbar_to_m03_couplers_BRESP),\n        .S_AXI_bvalid(xbar_to_m03_couplers_BVALID),\n        .S_AXI_rdata(xbar_to_m03_couplers_RDATA),\n        .S_AXI_rid(xbar_to_m03_couplers_RID),\n        .S_AXI_rlast(xbar_to_m03_couplers_RLAST),\n        .S_AXI_rready(xbar_to_m03_couplers_RREADY),\n        .S_AXI_rresp(xbar_to_m03_couplers_RRESP),\n        .S_AXI_rvalid(xbar_to_m03_couplers_RVALID),\n        .S_AXI_wdata(xbar_to_m03_couplers_WDATA),\n        .S_AXI_wlast(xbar_to_m03_couplers_WLAST),\n        .S_AXI_wready(xbar_to_m03_couplers_WREADY),\n        .S_AXI_wstrb(xbar_to_m03_couplers_WSTRB),\n        .S_AXI_wvalid(xbar_to_m03_couplers_WVALID));\n  s00_couplers_imp_QICM5G s00_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(s00_couplers_to_xbar_ARADDR),\n        .M_AXI_arburst(s00_couplers_to_xbar_ARBURST),\n        .M_AXI_arcache(s00_couplers_to_xbar_ARCACHE),\n        .M_AXI_arid(s00_couplers_to_xbar_ARID),\n        .M_AXI_arlen(s00_couplers_to_xbar_ARLEN),\n        .M_AXI_arlock(s00_couplers_to_xbar_ARLOCK),\n        .M_AXI_arprot(s00_couplers_to_xbar_ARPROT),\n        .M_AXI_arqos(s00_couplers_to_xbar_ARQOS),\n        .M_AXI_arready(s00_couplers_to_xbar_ARREADY),\n        .M_AXI_arsize(s00_couplers_to_xbar_ARSIZE),\n        .M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),\n        .M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),\n        .M_AXI_awburst(s00_couplers_to_xbar_AWBURST),\n        .M_AXI_awcache(s00_couplers_to_xbar_AWCACHE),\n        .M_AXI_awid(s00_couplers_to_xbar_AWID),\n        .M_AXI_awlen(s00_couplers_to_xbar_AWLEN),\n        .M_AXI_awlock(s00_couplers_to_xbar_AWLOCK),\n        .M_AXI_awprot(s00_couplers_to_xbar_AWPROT),\n        .M_AXI_awqos(s00_couplers_to_xbar_AWQOS),\n        .M_AXI_awready(s00_couplers_to_xbar_AWREADY),\n        .M_AXI_awsize(s00_couplers_to_xbar_AWSIZE),\n        .M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),\n        .M_AXI_bid(s00_couplers_to_xbar_BID),\n        .M_AXI_bready(s00_couplers_to_xbar_BREADY),\n        .M_AXI_bresp(s00_couplers_to_xbar_BRESP),\n        .M_AXI_bvalid(s00_couplers_to_xbar_BVALID),\n        .M_AXI_rdata(s00_couplers_to_xbar_RDATA),\n        .M_AXI_rid(s00_couplers_to_xbar_RID),\n        .M_AXI_rlast(s00_couplers_to_xbar_RLAST),\n        .M_AXI_rready(s00_couplers_to_xbar_RREADY),\n        .M_AXI_rresp(s00_couplers_to_xbar_RRESP),\n        .M_AXI_rvalid(s00_couplers_to_xbar_RVALID),\n        .M_AXI_wdata(s00_couplers_to_xbar_WDATA),\n        .M_AXI_wlast(s00_couplers_to_xbar_WLAST),\n        .M_AXI_wready(s00_couplers_to_xbar_WREADY),\n        .M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),\n        .M_AXI_wvalid(s00_couplers_to_xbar_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(axi_interconnect_0_to_s00_couplers_ARADDR),\n        .S_AXI_arburst(axi_interconnect_0_to_s00_couplers_ARBURST),\n        .S_AXI_arcache(axi_interconnect_0_to_s00_couplers_ARCACHE),\n        .S_AXI_arid(axi_interconnect_0_to_s00_couplers_ARID),\n        .S_AXI_arlen(axi_interconnect_0_to_s00_couplers_ARLEN),\n        .S_AXI_arlock(axi_interconnect_0_to_s00_couplers_ARLOCK),\n        .S_AXI_arprot(axi_interconnect_0_to_s00_couplers_ARPROT),\n        .S_AXI_arqos(axi_interconnect_0_to_s00_couplers_ARQOS),\n        .S_AXI_arready(axi_interconnect_0_to_s00_couplers_ARREADY),\n        .S_AXI_arregion(axi_interconnect_0_to_s00_couplers_ARREGION),\n        .S_AXI_arsize(axi_interconnect_0_to_s00_couplers_ARSIZE),\n        .S_AXI_arvalid(axi_interconnect_0_to_s00_couplers_ARVALID),\n        .S_AXI_awaddr(axi_interconnect_0_to_s00_couplers_AWADDR),\n        .S_AXI_awburst(axi_interconnect_0_to_s00_couplers_AWBURST),\n        .S_AXI_awcache(axi_interconnect_0_to_s00_couplers_AWCACHE),\n        .S_AXI_awid(axi_interconnect_0_to_s00_couplers_AWID),\n        .S_AXI_awlen(axi_interconnect_0_to_s00_couplers_AWLEN),\n        .S_AXI_awlock(axi_interconnect_0_to_s00_couplers_AWLOCK),\n        .S_AXI_awprot(axi_interconnect_0_to_s00_couplers_AWPROT),\n        .S_AXI_awqos(axi_interconnect_0_to_s00_couplers_AWQOS),\n        .S_AXI_awready(axi_interconnect_0_to_s00_couplers_AWREADY),\n        .S_AXI_awregion(axi_interconnect_0_to_s00_couplers_AWREGION),\n        .S_AXI_awsize(axi_interconnect_0_to_s00_couplers_AWSIZE),\n        .S_AXI_awvalid(axi_interconnect_0_to_s00_couplers_AWVALID),\n        .S_AXI_bid(axi_interconnect_0_to_s00_couplers_BID),\n        .S_AXI_bready(axi_interconnect_0_to_s00_couplers_BREADY),\n        .S_AXI_bresp(axi_interconnect_0_to_s00_couplers_BRESP),\n        .S_AXI_bvalid(axi_interconnect_0_to_s00_couplers_BVALID),\n        .S_AXI_rdata(axi_interconnect_0_to_s00_couplers_RDATA),\n        .S_AXI_rid(axi_interconnect_0_to_s00_couplers_RID),\n        .S_AXI_rlast(axi_interconnect_0_to_s00_couplers_RLAST),\n        .S_AXI_rready(axi_interconnect_0_to_s00_couplers_RREADY),\n        .S_AXI_rresp(axi_interconnect_0_to_s00_couplers_RRESP),\n        .S_AXI_rvalid(axi_interconnect_0_to_s00_couplers_RVALID),\n        .S_AXI_wdata(axi_interconnect_0_to_s00_couplers_WDATA),\n        .S_AXI_wlast(axi_interconnect_0_to_s00_couplers_WLAST),\n        .S_AXI_wready(axi_interconnect_0_to_s00_couplers_WREADY),\n        .S_AXI_wstrb(axi_interconnect_0_to_s00_couplers_WSTRB),\n        .S_AXI_wvalid(axi_interconnect_0_to_s00_couplers_WVALID));\n  s01_couplers_imp_GSTXQ8 s01_couplers\n       (.M_ACLK(axi_interconnect_0_ACLK_net),\n        .M_ARESETN(axi_interconnect_0_ARESETN_net),\n        .M_AXI_araddr(s01_couplers_to_xbar_ARADDR),\n        .M_AXI_arburst(s01_couplers_to_xbar_ARBURST),\n        .M_AXI_arcache(s01_couplers_to_xbar_ARCACHE),\n        .M_AXI_arid(s01_couplers_to_xbar_ARID),\n        .M_AXI_arlen(s01_couplers_to_xbar_ARLEN),\n        .M_AXI_arlock(s01_couplers_to_xbar_ARLOCK),\n        .M_AXI_arprot(s01_couplers_to_xbar_ARPROT),\n        .M_AXI_arqos(s01_couplers_to_xbar_ARQOS),\n        .M_AXI_arready(s01_couplers_to_xbar_ARREADY),\n        .M_AXI_arsize(s01_couplers_to_xbar_ARSIZE),\n        .M_AXI_arvalid(s01_couplers_to_xbar_ARVALID),\n        .M_AXI_awaddr(s01_couplers_to_xbar_AWADDR),\n        .M_AXI_awburst(s01_couplers_to_xbar_AWBURST),\n        .M_AXI_awcache(s01_couplers_to_xbar_AWCACHE),\n        .M_AXI_awid(s01_couplers_to_xbar_AWID),\n        .M_AXI_awlen(s01_couplers_to_xbar_AWLEN),\n        .M_AXI_awlock(s01_couplers_to_xbar_AWLOCK),\n        .M_AXI_awprot(s01_couplers_to_xbar_AWPROT),\n        .M_AXI_awqos(s01_couplers_to_xbar_AWQOS),\n        .M_AXI_awready(s01_couplers_to_xbar_AWREADY),\n        .M_AXI_awsize(s01_couplers_to_xbar_AWSIZE),\n        .M_AXI_awvalid(s01_couplers_to_xbar_AWVALID),\n        .M_AXI_bid(s01_couplers_to_xbar_BID),\n        .M_AXI_bready(s01_couplers_to_xbar_BREADY),\n        .M_AXI_bresp(s01_couplers_to_xbar_BRESP),\n        .M_AXI_bvalid(s01_couplers_to_xbar_BVALID),\n        .M_AXI_rdata(s01_couplers_to_xbar_RDATA),\n        .M_AXI_rid(s01_couplers_to_xbar_RID),\n        .M_AXI_rlast(s01_couplers_to_xbar_RLAST),\n        .M_AXI_rready(s01_couplers_to_xbar_RREADY),\n        .M_AXI_rresp(s01_couplers_to_xbar_RRESP),\n        .M_AXI_rvalid(s01_couplers_to_xbar_RVALID),\n        .M_AXI_wdata(s01_couplers_to_xbar_WDATA),\n        .M_AXI_wlast(s01_couplers_to_xbar_WLAST),\n        .M_AXI_wready(s01_couplers_to_xbar_WREADY),\n        .M_AXI_wstrb(s01_couplers_to_xbar_WSTRB),\n        .M_AXI_wvalid(s01_couplers_to_xbar_WVALID),\n        .S_ACLK(axi_interconnect_0_ACLK_net),\n        .S_ARESETN(axi_interconnect_0_ARESETN_net),\n        .S_AXI_araddr(axi_interconnect_0_to_s01_couplers_ARADDR),\n        .S_AXI_arburst(axi_interconnect_0_to_s01_couplers_ARBURST),\n        .S_AXI_arcache(axi_interconnect_0_to_s01_couplers_ARCACHE),\n        .S_AXI_arid(axi_interconnect_0_to_s01_couplers_ARID),\n        .S_AXI_arlen(axi_interconnect_0_to_s01_couplers_ARLEN),\n        .S_AXI_arlock(axi_interconnect_0_to_s01_couplers_ARLOCK),\n        .S_AXI_arprot(axi_interconnect_0_to_s01_couplers_ARPROT),\n        .S_AXI_arqos(axi_interconnect_0_to_s01_couplers_ARQOS),\n        .S_AXI_arready(axi_interconnect_0_to_s01_couplers_ARREADY),\n        .S_AXI_arregion(axi_interconnect_0_to_s01_couplers_ARREGION),\n        .S_AXI_arsize(axi_interconnect_0_to_s01_couplers_ARSIZE),\n        .S_AXI_arvalid(axi_interconnect_0_to_s01_couplers_ARVALID),\n        .S_AXI_awaddr(axi_interconnect_0_to_s01_couplers_AWADDR),\n        .S_AXI_awburst(axi_interconnect_0_to_s01_couplers_AWBURST),\n        .S_AXI_awcache(axi_interconnect_0_to_s01_couplers_AWCACHE),\n        .S_AXI_awid(axi_interconnect_0_to_s01_couplers_AWID),\n        .S_AXI_awlen(axi_interconnect_0_to_s01_couplers_AWLEN),\n        .S_AXI_awlock(axi_interconnect_0_to_s01_couplers_AWLOCK),\n        .S_AXI_awprot(axi_interconnect_0_to_s01_couplers_AWPROT),\n        .S_AXI_awqos(axi_interconnect_0_to_s01_couplers_AWQOS),\n        .S_AXI_awready(axi_interconnect_0_to_s01_couplers_AWREADY),\n        .S_AXI_awregion(axi_interconnect_0_to_s01_couplers_AWREGION),\n        .S_AXI_awsize(axi_interconnect_0_to_s01_couplers_AWSIZE),\n        .S_AXI_awvalid(axi_interconnect_0_to_s01_couplers_AWVALID),\n        .S_AXI_bid(axi_interconnect_0_to_s01_couplers_BID),\n        .S_AXI_bready(axi_interconnect_0_to_s01_couplers_BREADY),\n        .S_AXI_bresp(axi_interconnect_0_to_s01_couplers_BRESP),\n        .S_AXI_bvalid(axi_interconnect_0_to_s01_couplers_BVALID),\n        .S_AXI_rdata(axi_interconnect_0_to_s01_couplers_RDATA),\n        .S_AXI_rid(axi_interconnect_0_to_s01_couplers_RID),\n        .S_AXI_rlast(axi_interconnect_0_to_s01_couplers_RLAST),\n        .S_AXI_rready(axi_interconnect_0_to_s01_couplers_RREADY),\n        .S_AXI_rresp(axi_interconnect_0_to_s01_couplers_RRESP),\n        .S_AXI_rvalid(axi_interconnect_0_to_s01_couplers_RVALID),\n        .S_AXI_wdata(axi_interconnect_0_to_s01_couplers_WDATA),\n        .S_AXI_wlast(axi_interconnect_0_to_s01_couplers_WLAST),\n        .S_AXI_wready(axi_interconnect_0_to_s01_couplers_WREADY),\n        .S_AXI_wstrb(axi_interconnect_0_to_s01_couplers_WSTRB),\n        .S_AXI_wvalid(axi_interconnect_0_to_s01_couplers_WVALID));\n  cl_axi_interconnect_xbar_0 xbar\n       (.aclk(axi_interconnect_0_ACLK_net),\n        .aresetn(axi_interconnect_0_ARESETN_net),\n        .m_axi_araddr({xbar_to_m03_couplers_ARADDR,xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),\n        .m_axi_arburst({xbar_to_m03_couplers_ARBURST,xbar_to_m02_couplers_ARBURST,xbar_to_m01_couplers_ARBURST,xbar_to_m00_couplers_ARBURST}),\n        .m_axi_arcache({xbar_to_m03_couplers_ARCACHE,xbar_to_m02_couplers_ARCACHE,xbar_to_m01_couplers_ARCACHE,xbar_to_m00_couplers_ARCACHE}),\n        .m_axi_arid({xbar_to_m03_couplers_ARID,xbar_to_m02_couplers_ARID,xbar_to_m01_couplers_ARID,xbar_to_m00_couplers_ARID}),\n        .m_axi_arlen({xbar_to_m03_couplers_ARLEN,xbar_to_m02_couplers_ARLEN,xbar_to_m01_couplers_ARLEN,xbar_to_m00_couplers_ARLEN}),\n        .m_axi_arlock({xbar_to_m03_couplers_ARLOCK,xbar_to_m02_couplers_ARLOCK,xbar_to_m01_couplers_ARLOCK,xbar_to_m00_couplers_ARLOCK}),\n        .m_axi_arprot({xbar_to_m03_couplers_ARPROT,xbar_to_m02_couplers_ARPROT,xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}),\n        .m_axi_arqos({xbar_to_m03_couplers_ARQOS,xbar_to_m02_couplers_ARQOS,xbar_to_m01_couplers_ARQOS,xbar_to_m00_couplers_ARQOS}),\n        .m_axi_arready({xbar_to_m03_couplers_ARREADY,xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),\n        .m_axi_arregion({xbar_to_m03_couplers_ARREGION,xbar_to_m02_couplers_ARREGION,xbar_to_m01_couplers_ARREGION,xbar_to_m00_couplers_ARREGION}),\n        .m_axi_arsize({xbar_to_m03_couplers_ARSIZE,xbar_to_m02_couplers_ARSIZE,xbar_to_m01_couplers_ARSIZE,xbar_to_m00_couplers_ARSIZE}),\n        .m_axi_arvalid({xbar_to_m03_couplers_ARVALID,xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),\n        .m_axi_awaddr({xbar_to_m03_couplers_AWADDR,xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),\n        .m_axi_awburst({xbar_to_m03_couplers_AWBURST,xbar_to_m02_couplers_AWBURST,xbar_to_m01_couplers_AWBURST,xbar_to_m00_couplers_AWBURST}),\n        .m_axi_awcache({xbar_to_m03_couplers_AWCACHE,xbar_to_m02_couplers_AWCACHE,xbar_to_m01_couplers_AWCACHE,xbar_to_m00_couplers_AWCACHE}),\n        .m_axi_awid({xbar_to_m03_couplers_AWID,xbar_to_m02_couplers_AWID,xbar_to_m01_couplers_AWID,xbar_to_m00_couplers_AWID}),\n        .m_axi_awlen({xbar_to_m03_couplers_AWLEN,xbar_to_m02_couplers_AWLEN,xbar_to_m01_couplers_AWLEN,xbar_to_m00_couplers_AWLEN}),\n        .m_axi_awlock({xbar_to_m03_couplers_AWLOCK,xbar_to_m02_couplers_AWLOCK,xbar_to_m01_couplers_AWLOCK,xbar_to_m00_couplers_AWLOCK}),\n        .m_axi_awprot({xbar_to_m03_couplers_AWPROT,xbar_to_m02_couplers_AWPROT,xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}),\n        .m_axi_awqos({xbar_to_m03_couplers_AWQOS,xbar_to_m02_couplers_AWQOS,xbar_to_m01_couplers_AWQOS,xbar_to_m00_couplers_AWQOS}),\n        .m_axi_awready({xbar_to_m03_couplers_AWREADY,xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),\n        .m_axi_awregion({xbar_to_m03_couplers_AWREGION,xbar_to_m02_couplers_AWREGION,xbar_to_m01_couplers_AWREGION,xbar_to_m00_couplers_AWREGION}),\n        .m_axi_awsize({xbar_to_m03_couplers_AWSIZE,xbar_to_m02_couplers_AWSIZE,xbar_to_m01_couplers_AWSIZE,xbar_to_m00_couplers_AWSIZE}),\n        .m_axi_awvalid({xbar_to_m03_couplers_AWVALID,xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),\n        .m_axi_bid({xbar_to_m03_couplers_BID,xbar_to_m02_couplers_BID,xbar_to_m01_couplers_BID,xbar_to_m00_couplers_BID}),\n        .m_axi_bready({xbar_to_m03_couplers_BREADY,xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),\n        .m_axi_bresp({xbar_to_m03_couplers_BRESP,xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),\n        .m_axi_bvalid({xbar_to_m03_couplers_BVALID,xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),\n        .m_axi_rdata({xbar_to_m03_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),\n        .m_axi_rid({xbar_to_m03_couplers_RID,xbar_to_m02_couplers_RID,xbar_to_m01_couplers_RID,xbar_to_m00_couplers_RID}),\n        .m_axi_rlast({xbar_to_m03_couplers_RLAST,xbar_to_m02_couplers_RLAST,xbar_to_m01_couplers_RLAST,xbar_to_m00_couplers_RLAST}),\n        .m_axi_rready({xbar_to_m03_couplers_RREADY,xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),\n        .m_axi_rresp({xbar_to_m03_couplers_RRESP,xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),\n        .m_axi_rvalid({xbar_to_m03_couplers_RVALID,xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),\n        .m_axi_wdata({xbar_to_m03_couplers_WDATA,xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),\n        .m_axi_wlast({xbar_to_m03_couplers_WLAST,xbar_to_m02_couplers_WLAST,xbar_to_m01_couplers_WLAST,xbar_to_m00_couplers_WLAST}),\n        .m_axi_wready({xbar_to_m03_couplers_WREADY,xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),\n        .m_axi_wstrb({xbar_to_m03_couplers_WSTRB,xbar_to_m02_couplers_WSTRB,xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),\n        .m_axi_wvalid({xbar_to_m03_couplers_WVALID,xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),\n        .s_axi_araddr({s01_couplers_to_xbar_ARADDR,s00_couplers_to_xbar_ARADDR}),\n        .s_axi_arburst({s01_couplers_to_xbar_ARBURST,s00_couplers_to_xbar_ARBURST}),\n        .s_axi_arcache({s01_couplers_to_xbar_ARCACHE,s00_couplers_to_xbar_ARCACHE}),\n        .s_axi_arid({1'b0,s01_couplers_to_xbar_ARID,1'b0,s00_couplers_to_xbar_ARID}),\n        .s_axi_arlen({s01_couplers_to_xbar_ARLEN,s00_couplers_to_xbar_ARLEN}),\n        .s_axi_arlock({s01_couplers_to_xbar_ARLOCK,s00_couplers_to_xbar_ARLOCK}),\n        .s_axi_arprot({s01_couplers_to_xbar_ARPROT,s00_couplers_to_xbar_ARPROT}),\n        .s_axi_arqos({s01_couplers_to_xbar_ARQOS,s00_couplers_to_xbar_ARQOS}),\n        .s_axi_arready({s01_couplers_to_xbar_ARREADY,s00_couplers_to_xbar_ARREADY}),\n        .s_axi_arsize({s01_couplers_to_xbar_ARSIZE,s00_couplers_to_xbar_ARSIZE}),\n        .s_axi_arvalid({s01_couplers_to_xbar_ARVALID,s00_couplers_to_xbar_ARVALID}),\n        .s_axi_awaddr({s01_couplers_to_xbar_AWADDR,s00_couplers_to_xbar_AWADDR}),\n        .s_axi_awburst({s01_couplers_to_xbar_AWBURST,s00_couplers_to_xbar_AWBURST}),\n        .s_axi_awcache({s01_couplers_to_xbar_AWCACHE,s00_couplers_to_xbar_AWCACHE}),\n        .s_axi_awid({1'b0,s01_couplers_to_xbar_AWID,1'b0,s00_couplers_to_xbar_AWID}),\n        .s_axi_awlen({s01_couplers_to_xbar_AWLEN,s00_couplers_to_xbar_AWLEN}),\n        .s_axi_awlock({s01_couplers_to_xbar_AWLOCK,s00_couplers_to_xbar_AWLOCK}),\n        .s_axi_awprot({s01_couplers_to_xbar_AWPROT,s00_couplers_to_xbar_AWPROT}),\n        .s_axi_awqos({s01_couplers_to_xbar_AWQOS,s00_couplers_to_xbar_AWQOS}),\n        .s_axi_awready({s01_couplers_to_xbar_AWREADY,s00_couplers_to_xbar_AWREADY}),\n        .s_axi_awsize({s01_couplers_to_xbar_AWSIZE,s00_couplers_to_xbar_AWSIZE}),\n        .s_axi_awvalid({s01_couplers_to_xbar_AWVALID,s00_couplers_to_xbar_AWVALID}),\n        .s_axi_bid({s01_couplers_to_xbar_BID,s00_couplers_to_xbar_BID}),\n        .s_axi_bready({s01_couplers_to_xbar_BREADY,s00_couplers_to_xbar_BREADY}),\n        .s_axi_bresp({s01_couplers_to_xbar_BRESP,s00_couplers_to_xbar_BRESP}),\n        .s_axi_bvalid({s01_couplers_to_xbar_BVALID,s00_couplers_to_xbar_BVALID}),\n        .s_axi_rdata({s01_couplers_to_xbar_RDATA,s00_couplers_to_xbar_RDATA}),\n        .s_axi_rid({s01_couplers_to_xbar_RID,s00_couplers_to_xbar_RID}),\n        .s_axi_rlast({s01_couplers_to_xbar_RLAST,s00_couplers_to_xbar_RLAST}),\n        .s_axi_rready({s01_couplers_to_xbar_RREADY,s00_couplers_to_xbar_RREADY}),\n        .s_axi_rresp({s01_couplers_to_xbar_RRESP,s00_couplers_to_xbar_RRESP}),\n        .s_axi_rvalid({s01_couplers_to_xbar_RVALID,s00_couplers_to_xbar_RVALID}),\n        .s_axi_wdata({s01_couplers_to_xbar_WDATA,s00_couplers_to_xbar_WDATA}),\n        .s_axi_wlast({s01_couplers_to_xbar_WLAST,s00_couplers_to_xbar_WLAST}),\n        .s_axi_wready({s01_couplers_to_xbar_WREADY,s00_couplers_to_xbar_WREADY}),\n        .s_axi_wstrb({s01_couplers_to_xbar_WSTRB,s00_couplers_to_xbar_WSTRB}),\n        .s_axi_wvalid({s01_couplers_to_xbar_WVALID,s00_couplers_to_xbar_WVALID}));\nendmodule\n\nmodule m00_couplers_imp_1QBJ6U2\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m00_couplers_to_m00_regslice_ARADDR;\n  wire [1:0]m00_couplers_to_m00_regslice_ARBURST;\n  wire [3:0]m00_couplers_to_m00_regslice_ARCACHE;\n  wire [6:0]m00_couplers_to_m00_regslice_ARID;\n  wire [7:0]m00_couplers_to_m00_regslice_ARLEN;\n  wire [0:0]m00_couplers_to_m00_regslice_ARLOCK;\n  wire [2:0]m00_couplers_to_m00_regslice_ARPROT;\n  wire [3:0]m00_couplers_to_m00_regslice_ARQOS;\n  wire m00_couplers_to_m00_regslice_ARREADY;\n  wire [3:0]m00_couplers_to_m00_regslice_ARREGION;\n  wire [2:0]m00_couplers_to_m00_regslice_ARSIZE;\n  wire m00_couplers_to_m00_regslice_ARVALID;\n  wire [63:0]m00_couplers_to_m00_regslice_AWADDR;\n  wire [1:0]m00_couplers_to_m00_regslice_AWBURST;\n  wire [3:0]m00_couplers_to_m00_regslice_AWCACHE;\n  wire [6:0]m00_couplers_to_m00_regslice_AWID;\n  wire [7:0]m00_couplers_to_m00_regslice_AWLEN;\n  wire [0:0]m00_couplers_to_m00_regslice_AWLOCK;\n  wire [2:0]m00_couplers_to_m00_regslice_AWPROT;\n  wire [3:0]m00_couplers_to_m00_regslice_AWQOS;\n  wire m00_couplers_to_m00_regslice_AWREADY;\n  wire [3:0]m00_couplers_to_m00_regslice_AWREGION;\n  wire [2:0]m00_couplers_to_m00_regslice_AWSIZE;\n  wire m00_couplers_to_m00_regslice_AWVALID;\n  wire [6:0]m00_couplers_to_m00_regslice_BID;\n  wire m00_couplers_to_m00_regslice_BREADY;\n  wire [1:0]m00_couplers_to_m00_regslice_BRESP;\n  wire m00_couplers_to_m00_regslice_BVALID;\n  wire [511:0]m00_couplers_to_m00_regslice_RDATA;\n  wire [6:0]m00_couplers_to_m00_regslice_RID;\n  wire m00_couplers_to_m00_regslice_RLAST;\n  wire m00_couplers_to_m00_regslice_RREADY;\n  wire [1:0]m00_couplers_to_m00_regslice_RRESP;\n  wire m00_couplers_to_m00_regslice_RVALID;\n  wire [511:0]m00_couplers_to_m00_regslice_WDATA;\n  wire m00_couplers_to_m00_regslice_WLAST;\n  wire m00_couplers_to_m00_regslice_WREADY;\n  wire [63:0]m00_couplers_to_m00_regslice_WSTRB;\n  wire m00_couplers_to_m00_regslice_WVALID;\n  wire [63:0]m00_regslice_to_m00_couplers_ARADDR;\n  wire [1:0]m00_regslice_to_m00_couplers_ARBURST;\n  wire [3:0]m00_regslice_to_m00_couplers_ARCACHE;\n  wire [6:0]m00_regslice_to_m00_couplers_ARID;\n  wire [7:0]m00_regslice_to_m00_couplers_ARLEN;\n  wire [0:0]m00_regslice_to_m00_couplers_ARLOCK;\n  wire [2:0]m00_regslice_to_m00_couplers_ARPROT;\n  wire [3:0]m00_regslice_to_m00_couplers_ARQOS;\n  wire m00_regslice_to_m00_couplers_ARREADY;\n  wire [3:0]m00_regslice_to_m00_couplers_ARREGION;\n  wire [2:0]m00_regslice_to_m00_couplers_ARSIZE;\n  wire m00_regslice_to_m00_couplers_ARVALID;\n  wire [63:0]m00_regslice_to_m00_couplers_AWADDR;\n  wire [1:0]m00_regslice_to_m00_couplers_AWBURST;\n  wire [3:0]m00_regslice_to_m00_couplers_AWCACHE;\n  wire [6:0]m00_regslice_to_m00_couplers_AWID;\n  wire [7:0]m00_regslice_to_m00_couplers_AWLEN;\n  wire [0:0]m00_regslice_to_m00_couplers_AWLOCK;\n  wire [2:0]m00_regslice_to_m00_couplers_AWPROT;\n  wire [3:0]m00_regslice_to_m00_couplers_AWQOS;\n  wire m00_regslice_to_m00_couplers_AWREADY;\n  wire [3:0]m00_regslice_to_m00_couplers_AWREGION;\n  wire [2:0]m00_regslice_to_m00_couplers_AWSIZE;\n  wire m00_regslice_to_m00_couplers_AWVALID;\n  wire [6:0]m00_regslice_to_m00_couplers_BID;\n  wire m00_regslice_to_m00_couplers_BREADY;\n  wire [1:0]m00_regslice_to_m00_couplers_BRESP;\n  wire m00_regslice_to_m00_couplers_BVALID;\n  wire [511:0]m00_regslice_to_m00_couplers_RDATA;\n  wire [6:0]m00_regslice_to_m00_couplers_RID;\n  wire m00_regslice_to_m00_couplers_RLAST;\n  wire m00_regslice_to_m00_couplers_RREADY;\n  wire [1:0]m00_regslice_to_m00_couplers_RRESP;\n  wire m00_regslice_to_m00_couplers_RVALID;\n  wire [511:0]m00_regslice_to_m00_couplers_WDATA;\n  wire m00_regslice_to_m00_couplers_WLAST;\n  wire m00_regslice_to_m00_couplers_WREADY;\n  wire [63:0]m00_regslice_to_m00_couplers_WSTRB;\n  wire m00_regslice_to_m00_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m00_regslice_to_m00_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m00_regslice_to_m00_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m00_regslice_to_m00_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m00_regslice_to_m00_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m00_regslice_to_m00_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m00_regslice_to_m00_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m00_regslice_to_m00_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m00_regslice_to_m00_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m00_regslice_to_m00_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m00_regslice_to_m00_couplers_ARSIZE;\n  assign M_AXI_arvalid = m00_regslice_to_m00_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m00_regslice_to_m00_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m00_regslice_to_m00_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m00_regslice_to_m00_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m00_regslice_to_m00_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m00_regslice_to_m00_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m00_regslice_to_m00_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m00_regslice_to_m00_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m00_regslice_to_m00_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m00_regslice_to_m00_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m00_regslice_to_m00_couplers_AWSIZE;\n  assign M_AXI_awvalid = m00_regslice_to_m00_couplers_AWVALID;\n  assign M_AXI_bready = m00_regslice_to_m00_couplers_BREADY;\n  assign M_AXI_rready = m00_regslice_to_m00_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m00_regslice_to_m00_couplers_WDATA;\n  assign M_AXI_wlast = m00_regslice_to_m00_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m00_regslice_to_m00_couplers_WSTRB;\n  assign M_AXI_wvalid = m00_regslice_to_m00_couplers_WVALID;\n  assign S_AXI_arready = m00_couplers_to_m00_regslice_ARREADY;\n  assign S_AXI_awready = m00_couplers_to_m00_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m00_couplers_to_m00_regslice_BID;\n  assign S_AXI_bresp[1:0] = m00_couplers_to_m00_regslice_BRESP;\n  assign S_AXI_bvalid = m00_couplers_to_m00_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m00_couplers_to_m00_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m00_couplers_to_m00_regslice_RID;\n  assign S_AXI_rlast = m00_couplers_to_m00_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m00_couplers_to_m00_regslice_RRESP;\n  assign S_AXI_rvalid = m00_couplers_to_m00_regslice_RVALID;\n  assign S_AXI_wready = m00_couplers_to_m00_regslice_WREADY;\n  assign m00_couplers_to_m00_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m00_couplers_to_m00_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m00_couplers_to_m00_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m00_couplers_to_m00_regslice_ARID = S_AXI_arid[6:0];\n  assign m00_couplers_to_m00_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m00_couplers_to_m00_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m00_couplers_to_m00_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m00_couplers_to_m00_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m00_couplers_to_m00_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m00_couplers_to_m00_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m00_couplers_to_m00_regslice_ARVALID = S_AXI_arvalid;\n  assign m00_couplers_to_m00_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m00_couplers_to_m00_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m00_couplers_to_m00_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m00_couplers_to_m00_regslice_AWID = S_AXI_awid[6:0];\n  assign m00_couplers_to_m00_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m00_couplers_to_m00_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m00_couplers_to_m00_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m00_couplers_to_m00_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m00_couplers_to_m00_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m00_couplers_to_m00_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m00_couplers_to_m00_regslice_AWVALID = S_AXI_awvalid;\n  assign m00_couplers_to_m00_regslice_BREADY = S_AXI_bready;\n  assign m00_couplers_to_m00_regslice_RREADY = S_AXI_rready;\n  assign m00_couplers_to_m00_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m00_couplers_to_m00_regslice_WLAST = S_AXI_wlast;\n  assign m00_couplers_to_m00_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m00_couplers_to_m00_regslice_WVALID = S_AXI_wvalid;\n  assign m00_regslice_to_m00_couplers_ARREADY = M_AXI_arready;\n  assign m00_regslice_to_m00_couplers_AWREADY = M_AXI_awready;\n  assign m00_regslice_to_m00_couplers_BID = M_AXI_bid[6:0];\n  assign m00_regslice_to_m00_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m00_regslice_to_m00_couplers_BVALID = M_AXI_bvalid;\n  assign m00_regslice_to_m00_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m00_regslice_to_m00_couplers_RID = M_AXI_rid[6:0];\n  assign m00_regslice_to_m00_couplers_RLAST = M_AXI_rlast;\n  assign m00_regslice_to_m00_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m00_regslice_to_m00_couplers_RVALID = M_AXI_rvalid;\n  assign m00_regslice_to_m00_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m00_regslice_0 m00_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m00_regslice_to_m00_couplers_ARADDR),\n        .m_axi_arburst(m00_regslice_to_m00_couplers_ARBURST),\n        .m_axi_arcache(m00_regslice_to_m00_couplers_ARCACHE),\n        .m_axi_arid(m00_regslice_to_m00_couplers_ARID),\n        .m_axi_arlen(m00_regslice_to_m00_couplers_ARLEN),\n        .m_axi_arlock(m00_regslice_to_m00_couplers_ARLOCK),\n        .m_axi_arprot(m00_regslice_to_m00_couplers_ARPROT),\n        .m_axi_arqos(m00_regslice_to_m00_couplers_ARQOS),\n        .m_axi_arready(m00_regslice_to_m00_couplers_ARREADY),\n        .m_axi_arregion(m00_regslice_to_m00_couplers_ARREGION),\n        .m_axi_arsize(m00_regslice_to_m00_couplers_ARSIZE),\n        .m_axi_arvalid(m00_regslice_to_m00_couplers_ARVALID),\n        .m_axi_awaddr(m00_regslice_to_m00_couplers_AWADDR),\n        .m_axi_awburst(m00_regslice_to_m00_couplers_AWBURST),\n        .m_axi_awcache(m00_regslice_to_m00_couplers_AWCACHE),\n        .m_axi_awid(m00_regslice_to_m00_couplers_AWID),\n        .m_axi_awlen(m00_regslice_to_m00_couplers_AWLEN),\n        .m_axi_awlock(m00_regslice_to_m00_couplers_AWLOCK),\n        .m_axi_awprot(m00_regslice_to_m00_couplers_AWPROT),\n        .m_axi_awqos(m00_regslice_to_m00_couplers_AWQOS),\n        .m_axi_awready(m00_regslice_to_m00_couplers_AWREADY),\n        .m_axi_awregion(m00_regslice_to_m00_couplers_AWREGION),\n        .m_axi_awsize(m00_regslice_to_m00_couplers_AWSIZE),\n        .m_axi_awvalid(m00_regslice_to_m00_couplers_AWVALID),\n        .m_axi_bid(m00_regslice_to_m00_couplers_BID),\n        .m_axi_bready(m00_regslice_to_m00_couplers_BREADY),\n        .m_axi_bresp(m00_regslice_to_m00_couplers_BRESP),\n        .m_axi_bvalid(m00_regslice_to_m00_couplers_BVALID),\n        .m_axi_rdata(m00_regslice_to_m00_couplers_RDATA),\n        .m_axi_rid(m00_regslice_to_m00_couplers_RID),\n        .m_axi_rlast(m00_regslice_to_m00_couplers_RLAST),\n        .m_axi_rready(m00_regslice_to_m00_couplers_RREADY),\n        .m_axi_rresp(m00_regslice_to_m00_couplers_RRESP),\n        .m_axi_rvalid(m00_regslice_to_m00_couplers_RVALID),\n        .m_axi_wdata(m00_regslice_to_m00_couplers_WDATA),\n        .m_axi_wlast(m00_regslice_to_m00_couplers_WLAST),\n        .m_axi_wready(m00_regslice_to_m00_couplers_WREADY),\n        .m_axi_wstrb(m00_regslice_to_m00_couplers_WSTRB),\n        .m_axi_wvalid(m00_regslice_to_m00_couplers_WVALID),\n        .s_axi_araddr(m00_couplers_to_m00_regslice_ARADDR),\n        .s_axi_arburst(m00_couplers_to_m00_regslice_ARBURST),\n        .s_axi_arcache(m00_couplers_to_m00_regslice_ARCACHE),\n        .s_axi_arid(m00_couplers_to_m00_regslice_ARID),\n        .s_axi_arlen(m00_couplers_to_m00_regslice_ARLEN),\n        .s_axi_arlock(m00_couplers_to_m00_regslice_ARLOCK),\n        .s_axi_arprot(m00_couplers_to_m00_regslice_ARPROT),\n        .s_axi_arqos(m00_couplers_to_m00_regslice_ARQOS),\n        .s_axi_arready(m00_couplers_to_m00_regslice_ARREADY),\n        .s_axi_arregion(m00_couplers_to_m00_regslice_ARREGION),\n        .s_axi_arsize(m00_couplers_to_m00_regslice_ARSIZE),\n        .s_axi_arvalid(m00_couplers_to_m00_regslice_ARVALID),\n        .s_axi_awaddr(m00_couplers_to_m00_regslice_AWADDR),\n        .s_axi_awburst(m00_couplers_to_m00_regslice_AWBURST),\n        .s_axi_awcache(m00_couplers_to_m00_regslice_AWCACHE),\n        .s_axi_awid(m00_couplers_to_m00_regslice_AWID),\n        .s_axi_awlen(m00_couplers_to_m00_regslice_AWLEN),\n        .s_axi_awlock(m00_couplers_to_m00_regslice_AWLOCK),\n        .s_axi_awprot(m00_couplers_to_m00_regslice_AWPROT),\n        .s_axi_awqos(m00_couplers_to_m00_regslice_AWQOS),\n        .s_axi_awready(m00_couplers_to_m00_regslice_AWREADY),\n        .s_axi_awregion(m00_couplers_to_m00_regslice_AWREGION),\n        .s_axi_awsize(m00_couplers_to_m00_regslice_AWSIZE),\n        .s_axi_awvalid(m00_couplers_to_m00_regslice_AWVALID),\n        .s_axi_bid(m00_couplers_to_m00_regslice_BID),\n        .s_axi_bready(m00_couplers_to_m00_regslice_BREADY),\n        .s_axi_bresp(m00_couplers_to_m00_regslice_BRESP),\n        .s_axi_bvalid(m00_couplers_to_m00_regslice_BVALID),\n        .s_axi_rdata(m00_couplers_to_m00_regslice_RDATA),\n        .s_axi_rid(m00_couplers_to_m00_regslice_RID),\n        .s_axi_rlast(m00_couplers_to_m00_regslice_RLAST),\n        .s_axi_rready(m00_couplers_to_m00_regslice_RREADY),\n        .s_axi_rresp(m00_couplers_to_m00_regslice_RRESP),\n        .s_axi_rvalid(m00_couplers_to_m00_regslice_RVALID),\n        .s_axi_wdata(m00_couplers_to_m00_regslice_WDATA),\n        .s_axi_wlast(m00_couplers_to_m00_regslice_WLAST),\n        .s_axi_wready(m00_couplers_to_m00_regslice_WREADY),\n        .s_axi_wstrb(m00_couplers_to_m00_regslice_WSTRB),\n        .s_axi_wvalid(m00_couplers_to_m00_regslice_WVALID));\nendmodule\n\nmodule m01_couplers_imp_10IMR9A\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m01_couplers_to_m01_regslice_ARADDR;\n  wire [1:0]m01_couplers_to_m01_regslice_ARBURST;\n  wire [3:0]m01_couplers_to_m01_regslice_ARCACHE;\n  wire [6:0]m01_couplers_to_m01_regslice_ARID;\n  wire [7:0]m01_couplers_to_m01_regslice_ARLEN;\n  wire [0:0]m01_couplers_to_m01_regslice_ARLOCK;\n  wire [2:0]m01_couplers_to_m01_regslice_ARPROT;\n  wire [3:0]m01_couplers_to_m01_regslice_ARQOS;\n  wire m01_couplers_to_m01_regslice_ARREADY;\n  wire [3:0]m01_couplers_to_m01_regslice_ARREGION;\n  wire [2:0]m01_couplers_to_m01_regslice_ARSIZE;\n  wire m01_couplers_to_m01_regslice_ARVALID;\n  wire [63:0]m01_couplers_to_m01_regslice_AWADDR;\n  wire [1:0]m01_couplers_to_m01_regslice_AWBURST;\n  wire [3:0]m01_couplers_to_m01_regslice_AWCACHE;\n  wire [6:0]m01_couplers_to_m01_regslice_AWID;\n  wire [7:0]m01_couplers_to_m01_regslice_AWLEN;\n  wire [0:0]m01_couplers_to_m01_regslice_AWLOCK;\n  wire [2:0]m01_couplers_to_m01_regslice_AWPROT;\n  wire [3:0]m01_couplers_to_m01_regslice_AWQOS;\n  wire m01_couplers_to_m01_regslice_AWREADY;\n  wire [3:0]m01_couplers_to_m01_regslice_AWREGION;\n  wire [2:0]m01_couplers_to_m01_regslice_AWSIZE;\n  wire m01_couplers_to_m01_regslice_AWVALID;\n  wire [6:0]m01_couplers_to_m01_regslice_BID;\n  wire m01_couplers_to_m01_regslice_BREADY;\n  wire [1:0]m01_couplers_to_m01_regslice_BRESP;\n  wire m01_couplers_to_m01_regslice_BVALID;\n  wire [511:0]m01_couplers_to_m01_regslice_RDATA;\n  wire [6:0]m01_couplers_to_m01_regslice_RID;\n  wire m01_couplers_to_m01_regslice_RLAST;\n  wire m01_couplers_to_m01_regslice_RREADY;\n  wire [1:0]m01_couplers_to_m01_regslice_RRESP;\n  wire m01_couplers_to_m01_regslice_RVALID;\n  wire [511:0]m01_couplers_to_m01_regslice_WDATA;\n  wire m01_couplers_to_m01_regslice_WLAST;\n  wire m01_couplers_to_m01_regslice_WREADY;\n  wire [63:0]m01_couplers_to_m01_regslice_WSTRB;\n  wire m01_couplers_to_m01_regslice_WVALID;\n  wire [63:0]m01_regslice_to_m01_couplers_ARADDR;\n  wire [1:0]m01_regslice_to_m01_couplers_ARBURST;\n  wire [3:0]m01_regslice_to_m01_couplers_ARCACHE;\n  wire [6:0]m01_regslice_to_m01_couplers_ARID;\n  wire [7:0]m01_regslice_to_m01_couplers_ARLEN;\n  wire [0:0]m01_regslice_to_m01_couplers_ARLOCK;\n  wire [2:0]m01_regslice_to_m01_couplers_ARPROT;\n  wire [3:0]m01_regslice_to_m01_couplers_ARQOS;\n  wire m01_regslice_to_m01_couplers_ARREADY;\n  wire [3:0]m01_regslice_to_m01_couplers_ARREGION;\n  wire [2:0]m01_regslice_to_m01_couplers_ARSIZE;\n  wire m01_regslice_to_m01_couplers_ARVALID;\n  wire [63:0]m01_regslice_to_m01_couplers_AWADDR;\n  wire [1:0]m01_regslice_to_m01_couplers_AWBURST;\n  wire [3:0]m01_regslice_to_m01_couplers_AWCACHE;\n  wire [6:0]m01_regslice_to_m01_couplers_AWID;\n  wire [7:0]m01_regslice_to_m01_couplers_AWLEN;\n  wire [0:0]m01_regslice_to_m01_couplers_AWLOCK;\n  wire [2:0]m01_regslice_to_m01_couplers_AWPROT;\n  wire [3:0]m01_regslice_to_m01_couplers_AWQOS;\n  wire m01_regslice_to_m01_couplers_AWREADY;\n  wire [3:0]m01_regslice_to_m01_couplers_AWREGION;\n  wire [2:0]m01_regslice_to_m01_couplers_AWSIZE;\n  wire m01_regslice_to_m01_couplers_AWVALID;\n  wire [6:0]m01_regslice_to_m01_couplers_BID;\n  wire m01_regslice_to_m01_couplers_BREADY;\n  wire [1:0]m01_regslice_to_m01_couplers_BRESP;\n  wire m01_regslice_to_m01_couplers_BVALID;\n  wire [511:0]m01_regslice_to_m01_couplers_RDATA;\n  wire [6:0]m01_regslice_to_m01_couplers_RID;\n  wire m01_regslice_to_m01_couplers_RLAST;\n  wire m01_regslice_to_m01_couplers_RREADY;\n  wire [1:0]m01_regslice_to_m01_couplers_RRESP;\n  wire m01_regslice_to_m01_couplers_RVALID;\n  wire [511:0]m01_regslice_to_m01_couplers_WDATA;\n  wire m01_regslice_to_m01_couplers_WLAST;\n  wire m01_regslice_to_m01_couplers_WREADY;\n  wire [63:0]m01_regslice_to_m01_couplers_WSTRB;\n  wire m01_regslice_to_m01_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m01_regslice_to_m01_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m01_regslice_to_m01_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m01_regslice_to_m01_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m01_regslice_to_m01_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m01_regslice_to_m01_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m01_regslice_to_m01_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m01_regslice_to_m01_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m01_regslice_to_m01_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m01_regslice_to_m01_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m01_regslice_to_m01_couplers_ARSIZE;\n  assign M_AXI_arvalid = m01_regslice_to_m01_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m01_regslice_to_m01_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m01_regslice_to_m01_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m01_regslice_to_m01_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m01_regslice_to_m01_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m01_regslice_to_m01_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m01_regslice_to_m01_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m01_regslice_to_m01_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m01_regslice_to_m01_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m01_regslice_to_m01_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m01_regslice_to_m01_couplers_AWSIZE;\n  assign M_AXI_awvalid = m01_regslice_to_m01_couplers_AWVALID;\n  assign M_AXI_bready = m01_regslice_to_m01_couplers_BREADY;\n  assign M_AXI_rready = m01_regslice_to_m01_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m01_regslice_to_m01_couplers_WDATA;\n  assign M_AXI_wlast = m01_regslice_to_m01_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m01_regslice_to_m01_couplers_WSTRB;\n  assign M_AXI_wvalid = m01_regslice_to_m01_couplers_WVALID;\n  assign S_AXI_arready = m01_couplers_to_m01_regslice_ARREADY;\n  assign S_AXI_awready = m01_couplers_to_m01_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m01_couplers_to_m01_regslice_BID;\n  assign S_AXI_bresp[1:0] = m01_couplers_to_m01_regslice_BRESP;\n  assign S_AXI_bvalid = m01_couplers_to_m01_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m01_couplers_to_m01_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m01_couplers_to_m01_regslice_RID;\n  assign S_AXI_rlast = m01_couplers_to_m01_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m01_couplers_to_m01_regslice_RRESP;\n  assign S_AXI_rvalid = m01_couplers_to_m01_regslice_RVALID;\n  assign S_AXI_wready = m01_couplers_to_m01_regslice_WREADY;\n  assign m01_couplers_to_m01_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m01_couplers_to_m01_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m01_couplers_to_m01_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m01_couplers_to_m01_regslice_ARID = S_AXI_arid[6:0];\n  assign m01_couplers_to_m01_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m01_couplers_to_m01_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m01_couplers_to_m01_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m01_couplers_to_m01_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m01_couplers_to_m01_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m01_couplers_to_m01_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m01_couplers_to_m01_regslice_ARVALID = S_AXI_arvalid;\n  assign m01_couplers_to_m01_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m01_couplers_to_m01_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m01_couplers_to_m01_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m01_couplers_to_m01_regslice_AWID = S_AXI_awid[6:0];\n  assign m01_couplers_to_m01_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m01_couplers_to_m01_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m01_couplers_to_m01_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m01_couplers_to_m01_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m01_couplers_to_m01_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m01_couplers_to_m01_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m01_couplers_to_m01_regslice_AWVALID = S_AXI_awvalid;\n  assign m01_couplers_to_m01_regslice_BREADY = S_AXI_bready;\n  assign m01_couplers_to_m01_regslice_RREADY = S_AXI_rready;\n  assign m01_couplers_to_m01_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m01_couplers_to_m01_regslice_WLAST = S_AXI_wlast;\n  assign m01_couplers_to_m01_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m01_couplers_to_m01_regslice_WVALID = S_AXI_wvalid;\n  assign m01_regslice_to_m01_couplers_ARREADY = M_AXI_arready;\n  assign m01_regslice_to_m01_couplers_AWREADY = M_AXI_awready;\n  assign m01_regslice_to_m01_couplers_BID = M_AXI_bid[6:0];\n  assign m01_regslice_to_m01_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m01_regslice_to_m01_couplers_BVALID = M_AXI_bvalid;\n  assign m01_regslice_to_m01_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m01_regslice_to_m01_couplers_RID = M_AXI_rid[6:0];\n  assign m01_regslice_to_m01_couplers_RLAST = M_AXI_rlast;\n  assign m01_regslice_to_m01_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m01_regslice_to_m01_couplers_RVALID = M_AXI_rvalid;\n  assign m01_regslice_to_m01_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m01_regslice_0 m01_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m01_regslice_to_m01_couplers_ARADDR),\n        .m_axi_arburst(m01_regslice_to_m01_couplers_ARBURST),\n        .m_axi_arcache(m01_regslice_to_m01_couplers_ARCACHE),\n        .m_axi_arid(m01_regslice_to_m01_couplers_ARID),\n        .m_axi_arlen(m01_regslice_to_m01_couplers_ARLEN),\n        .m_axi_arlock(m01_regslice_to_m01_couplers_ARLOCK),\n        .m_axi_arprot(m01_regslice_to_m01_couplers_ARPROT),\n        .m_axi_arqos(m01_regslice_to_m01_couplers_ARQOS),\n        .m_axi_arready(m01_regslice_to_m01_couplers_ARREADY),\n        .m_axi_arregion(m01_regslice_to_m01_couplers_ARREGION),\n        .m_axi_arsize(m01_regslice_to_m01_couplers_ARSIZE),\n        .m_axi_arvalid(m01_regslice_to_m01_couplers_ARVALID),\n        .m_axi_awaddr(m01_regslice_to_m01_couplers_AWADDR),\n        .m_axi_awburst(m01_regslice_to_m01_couplers_AWBURST),\n        .m_axi_awcache(m01_regslice_to_m01_couplers_AWCACHE),\n        .m_axi_awid(m01_regslice_to_m01_couplers_AWID),\n        .m_axi_awlen(m01_regslice_to_m01_couplers_AWLEN),\n        .m_axi_awlock(m01_regslice_to_m01_couplers_AWLOCK),\n        .m_axi_awprot(m01_regslice_to_m01_couplers_AWPROT),\n        .m_axi_awqos(m01_regslice_to_m01_couplers_AWQOS),\n        .m_axi_awready(m01_regslice_to_m01_couplers_AWREADY),\n        .m_axi_awregion(m01_regslice_to_m01_couplers_AWREGION),\n        .m_axi_awsize(m01_regslice_to_m01_couplers_AWSIZE),\n        .m_axi_awvalid(m01_regslice_to_m01_couplers_AWVALID),\n        .m_axi_bid(m01_regslice_to_m01_couplers_BID),\n        .m_axi_bready(m01_regslice_to_m01_couplers_BREADY),\n        .m_axi_bresp(m01_regslice_to_m01_couplers_BRESP),\n        .m_axi_bvalid(m01_regslice_to_m01_couplers_BVALID),\n        .m_axi_rdata(m01_regslice_to_m01_couplers_RDATA),\n        .m_axi_rid(m01_regslice_to_m01_couplers_RID),\n        .m_axi_rlast(m01_regslice_to_m01_couplers_RLAST),\n        .m_axi_rready(m01_regslice_to_m01_couplers_RREADY),\n        .m_axi_rresp(m01_regslice_to_m01_couplers_RRESP),\n        .m_axi_rvalid(m01_regslice_to_m01_couplers_RVALID),\n        .m_axi_wdata(m01_regslice_to_m01_couplers_WDATA),\n        .m_axi_wlast(m01_regslice_to_m01_couplers_WLAST),\n        .m_axi_wready(m01_regslice_to_m01_couplers_WREADY),\n        .m_axi_wstrb(m01_regslice_to_m01_couplers_WSTRB),\n        .m_axi_wvalid(m01_regslice_to_m01_couplers_WVALID),\n        .s_axi_araddr(m01_couplers_to_m01_regslice_ARADDR),\n        .s_axi_arburst(m01_couplers_to_m01_regslice_ARBURST),\n        .s_axi_arcache(m01_couplers_to_m01_regslice_ARCACHE),\n        .s_axi_arid(m01_couplers_to_m01_regslice_ARID),\n        .s_axi_arlen(m01_couplers_to_m01_regslice_ARLEN),\n        .s_axi_arlock(m01_couplers_to_m01_regslice_ARLOCK),\n        .s_axi_arprot(m01_couplers_to_m01_regslice_ARPROT),\n        .s_axi_arqos(m01_couplers_to_m01_regslice_ARQOS),\n        .s_axi_arready(m01_couplers_to_m01_regslice_ARREADY),\n        .s_axi_arregion(m01_couplers_to_m01_regslice_ARREGION),\n        .s_axi_arsize(m01_couplers_to_m01_regslice_ARSIZE),\n        .s_axi_arvalid(m01_couplers_to_m01_regslice_ARVALID),\n        .s_axi_awaddr(m01_couplers_to_m01_regslice_AWADDR),\n        .s_axi_awburst(m01_couplers_to_m01_regslice_AWBURST),\n        .s_axi_awcache(m01_couplers_to_m01_regslice_AWCACHE),\n        .s_axi_awid(m01_couplers_to_m01_regslice_AWID),\n        .s_axi_awlen(m01_couplers_to_m01_regslice_AWLEN),\n        .s_axi_awlock(m01_couplers_to_m01_regslice_AWLOCK),\n        .s_axi_awprot(m01_couplers_to_m01_regslice_AWPROT),\n        .s_axi_awqos(m01_couplers_to_m01_regslice_AWQOS),\n        .s_axi_awready(m01_couplers_to_m01_regslice_AWREADY),\n        .s_axi_awregion(m01_couplers_to_m01_regslice_AWREGION),\n        .s_axi_awsize(m01_couplers_to_m01_regslice_AWSIZE),\n        .s_axi_awvalid(m01_couplers_to_m01_regslice_AWVALID),\n        .s_axi_bid(m01_couplers_to_m01_regslice_BID),\n        .s_axi_bready(m01_couplers_to_m01_regslice_BREADY),\n        .s_axi_bresp(m01_couplers_to_m01_regslice_BRESP),\n        .s_axi_bvalid(m01_couplers_to_m01_regslice_BVALID),\n        .s_axi_rdata(m01_couplers_to_m01_regslice_RDATA),\n        .s_axi_rid(m01_couplers_to_m01_regslice_RID),\n        .s_axi_rlast(m01_couplers_to_m01_regslice_RLAST),\n        .s_axi_rready(m01_couplers_to_m01_regslice_RREADY),\n        .s_axi_rresp(m01_couplers_to_m01_regslice_RRESP),\n        .s_axi_rvalid(m01_couplers_to_m01_regslice_RVALID),\n        .s_axi_wdata(m01_couplers_to_m01_regslice_WDATA),\n        .s_axi_wlast(m01_couplers_to_m01_regslice_WLAST),\n        .s_axi_wready(m01_couplers_to_m01_regslice_WREADY),\n        .s_axi_wstrb(m01_couplers_to_m01_regslice_WSTRB),\n        .s_axi_wvalid(m01_couplers_to_m01_regslice_WVALID));\nendmodule\n\nmodule m02_couplers_imp_APDUS2\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m02_couplers_to_m02_regslice_ARADDR;\n  wire [1:0]m02_couplers_to_m02_regslice_ARBURST;\n  wire [3:0]m02_couplers_to_m02_regslice_ARCACHE;\n  wire [6:0]m02_couplers_to_m02_regslice_ARID;\n  wire [7:0]m02_couplers_to_m02_regslice_ARLEN;\n  wire [0:0]m02_couplers_to_m02_regslice_ARLOCK;\n  wire [2:0]m02_couplers_to_m02_regslice_ARPROT;\n  wire [3:0]m02_couplers_to_m02_regslice_ARQOS;\n  wire m02_couplers_to_m02_regslice_ARREADY;\n  wire [3:0]m02_couplers_to_m02_regslice_ARREGION;\n  wire [2:0]m02_couplers_to_m02_regslice_ARSIZE;\n  wire m02_couplers_to_m02_regslice_ARVALID;\n  wire [63:0]m02_couplers_to_m02_regslice_AWADDR;\n  wire [1:0]m02_couplers_to_m02_regslice_AWBURST;\n  wire [3:0]m02_couplers_to_m02_regslice_AWCACHE;\n  wire [6:0]m02_couplers_to_m02_regslice_AWID;\n  wire [7:0]m02_couplers_to_m02_regslice_AWLEN;\n  wire [0:0]m02_couplers_to_m02_regslice_AWLOCK;\n  wire [2:0]m02_couplers_to_m02_regslice_AWPROT;\n  wire [3:0]m02_couplers_to_m02_regslice_AWQOS;\n  wire m02_couplers_to_m02_regslice_AWREADY;\n  wire [3:0]m02_couplers_to_m02_regslice_AWREGION;\n  wire [2:0]m02_couplers_to_m02_regslice_AWSIZE;\n  wire m02_couplers_to_m02_regslice_AWVALID;\n  wire [6:0]m02_couplers_to_m02_regslice_BID;\n  wire m02_couplers_to_m02_regslice_BREADY;\n  wire [1:0]m02_couplers_to_m02_regslice_BRESP;\n  wire m02_couplers_to_m02_regslice_BVALID;\n  wire [511:0]m02_couplers_to_m02_regslice_RDATA;\n  wire [6:0]m02_couplers_to_m02_regslice_RID;\n  wire m02_couplers_to_m02_regslice_RLAST;\n  wire m02_couplers_to_m02_regslice_RREADY;\n  wire [1:0]m02_couplers_to_m02_regslice_RRESP;\n  wire m02_couplers_to_m02_regslice_RVALID;\n  wire [511:0]m02_couplers_to_m02_regslice_WDATA;\n  wire m02_couplers_to_m02_regslice_WLAST;\n  wire m02_couplers_to_m02_regslice_WREADY;\n  wire [63:0]m02_couplers_to_m02_regslice_WSTRB;\n  wire m02_couplers_to_m02_regslice_WVALID;\n  wire [63:0]m02_regslice_to_m02_couplers_ARADDR;\n  wire [1:0]m02_regslice_to_m02_couplers_ARBURST;\n  wire [3:0]m02_regslice_to_m02_couplers_ARCACHE;\n  wire [6:0]m02_regslice_to_m02_couplers_ARID;\n  wire [7:0]m02_regslice_to_m02_couplers_ARLEN;\n  wire [0:0]m02_regslice_to_m02_couplers_ARLOCK;\n  wire [2:0]m02_regslice_to_m02_couplers_ARPROT;\n  wire [3:0]m02_regslice_to_m02_couplers_ARQOS;\n  wire m02_regslice_to_m02_couplers_ARREADY;\n  wire [3:0]m02_regslice_to_m02_couplers_ARREGION;\n  wire [2:0]m02_regslice_to_m02_couplers_ARSIZE;\n  wire m02_regslice_to_m02_couplers_ARVALID;\n  wire [63:0]m02_regslice_to_m02_couplers_AWADDR;\n  wire [1:0]m02_regslice_to_m02_couplers_AWBURST;\n  wire [3:0]m02_regslice_to_m02_couplers_AWCACHE;\n  wire [6:0]m02_regslice_to_m02_couplers_AWID;\n  wire [7:0]m02_regslice_to_m02_couplers_AWLEN;\n  wire [0:0]m02_regslice_to_m02_couplers_AWLOCK;\n  wire [2:0]m02_regslice_to_m02_couplers_AWPROT;\n  wire [3:0]m02_regslice_to_m02_couplers_AWQOS;\n  wire m02_regslice_to_m02_couplers_AWREADY;\n  wire [3:0]m02_regslice_to_m02_couplers_AWREGION;\n  wire [2:0]m02_regslice_to_m02_couplers_AWSIZE;\n  wire m02_regslice_to_m02_couplers_AWVALID;\n  wire [6:0]m02_regslice_to_m02_couplers_BID;\n  wire m02_regslice_to_m02_couplers_BREADY;\n  wire [1:0]m02_regslice_to_m02_couplers_BRESP;\n  wire m02_regslice_to_m02_couplers_BVALID;\n  wire [511:0]m02_regslice_to_m02_couplers_RDATA;\n  wire [6:0]m02_regslice_to_m02_couplers_RID;\n  wire m02_regslice_to_m02_couplers_RLAST;\n  wire m02_regslice_to_m02_couplers_RREADY;\n  wire [1:0]m02_regslice_to_m02_couplers_RRESP;\n  wire m02_regslice_to_m02_couplers_RVALID;\n  wire [511:0]m02_regslice_to_m02_couplers_WDATA;\n  wire m02_regslice_to_m02_couplers_WLAST;\n  wire m02_regslice_to_m02_couplers_WREADY;\n  wire [63:0]m02_regslice_to_m02_couplers_WSTRB;\n  wire m02_regslice_to_m02_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m02_regslice_to_m02_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m02_regslice_to_m02_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m02_regslice_to_m02_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m02_regslice_to_m02_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m02_regslice_to_m02_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m02_regslice_to_m02_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m02_regslice_to_m02_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m02_regslice_to_m02_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m02_regslice_to_m02_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m02_regslice_to_m02_couplers_ARSIZE;\n  assign M_AXI_arvalid = m02_regslice_to_m02_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m02_regslice_to_m02_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m02_regslice_to_m02_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m02_regslice_to_m02_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m02_regslice_to_m02_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m02_regslice_to_m02_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m02_regslice_to_m02_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m02_regslice_to_m02_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m02_regslice_to_m02_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m02_regslice_to_m02_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m02_regslice_to_m02_couplers_AWSIZE;\n  assign M_AXI_awvalid = m02_regslice_to_m02_couplers_AWVALID;\n  assign M_AXI_bready = m02_regslice_to_m02_couplers_BREADY;\n  assign M_AXI_rready = m02_regslice_to_m02_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m02_regslice_to_m02_couplers_WDATA;\n  assign M_AXI_wlast = m02_regslice_to_m02_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m02_regslice_to_m02_couplers_WSTRB;\n  assign M_AXI_wvalid = m02_regslice_to_m02_couplers_WVALID;\n  assign S_AXI_arready = m02_couplers_to_m02_regslice_ARREADY;\n  assign S_AXI_awready = m02_couplers_to_m02_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m02_couplers_to_m02_regslice_BID;\n  assign S_AXI_bresp[1:0] = m02_couplers_to_m02_regslice_BRESP;\n  assign S_AXI_bvalid = m02_couplers_to_m02_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m02_couplers_to_m02_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m02_couplers_to_m02_regslice_RID;\n  assign S_AXI_rlast = m02_couplers_to_m02_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m02_couplers_to_m02_regslice_RRESP;\n  assign S_AXI_rvalid = m02_couplers_to_m02_regslice_RVALID;\n  assign S_AXI_wready = m02_couplers_to_m02_regslice_WREADY;\n  assign m02_couplers_to_m02_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m02_couplers_to_m02_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m02_couplers_to_m02_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m02_couplers_to_m02_regslice_ARID = S_AXI_arid[6:0];\n  assign m02_couplers_to_m02_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m02_couplers_to_m02_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m02_couplers_to_m02_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m02_couplers_to_m02_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m02_couplers_to_m02_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m02_couplers_to_m02_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m02_couplers_to_m02_regslice_ARVALID = S_AXI_arvalid;\n  assign m02_couplers_to_m02_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m02_couplers_to_m02_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m02_couplers_to_m02_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m02_couplers_to_m02_regslice_AWID = S_AXI_awid[6:0];\n  assign m02_couplers_to_m02_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m02_couplers_to_m02_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m02_couplers_to_m02_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m02_couplers_to_m02_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m02_couplers_to_m02_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m02_couplers_to_m02_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m02_couplers_to_m02_regslice_AWVALID = S_AXI_awvalid;\n  assign m02_couplers_to_m02_regslice_BREADY = S_AXI_bready;\n  assign m02_couplers_to_m02_regslice_RREADY = S_AXI_rready;\n  assign m02_couplers_to_m02_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m02_couplers_to_m02_regslice_WLAST = S_AXI_wlast;\n  assign m02_couplers_to_m02_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m02_couplers_to_m02_regslice_WVALID = S_AXI_wvalid;\n  assign m02_regslice_to_m02_couplers_ARREADY = M_AXI_arready;\n  assign m02_regslice_to_m02_couplers_AWREADY = M_AXI_awready;\n  assign m02_regslice_to_m02_couplers_BID = M_AXI_bid[6:0];\n  assign m02_regslice_to_m02_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m02_regslice_to_m02_couplers_BVALID = M_AXI_bvalid;\n  assign m02_regslice_to_m02_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m02_regslice_to_m02_couplers_RID = M_AXI_rid[6:0];\n  assign m02_regslice_to_m02_couplers_RLAST = M_AXI_rlast;\n  assign m02_regslice_to_m02_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m02_regslice_to_m02_couplers_RVALID = M_AXI_rvalid;\n  assign m02_regslice_to_m02_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m02_regslice_0 m02_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m02_regslice_to_m02_couplers_ARADDR),\n        .m_axi_arburst(m02_regslice_to_m02_couplers_ARBURST),\n        .m_axi_arcache(m02_regslice_to_m02_couplers_ARCACHE),\n        .m_axi_arid(m02_regslice_to_m02_couplers_ARID),\n        .m_axi_arlen(m02_regslice_to_m02_couplers_ARLEN),\n        .m_axi_arlock(m02_regslice_to_m02_couplers_ARLOCK),\n        .m_axi_arprot(m02_regslice_to_m02_couplers_ARPROT),\n        .m_axi_arqos(m02_regslice_to_m02_couplers_ARQOS),\n        .m_axi_arready(m02_regslice_to_m02_couplers_ARREADY),\n        .m_axi_arregion(m02_regslice_to_m02_couplers_ARREGION),\n        .m_axi_arsize(m02_regslice_to_m02_couplers_ARSIZE),\n        .m_axi_arvalid(m02_regslice_to_m02_couplers_ARVALID),\n        .m_axi_awaddr(m02_regslice_to_m02_couplers_AWADDR),\n        .m_axi_awburst(m02_regslice_to_m02_couplers_AWBURST),\n        .m_axi_awcache(m02_regslice_to_m02_couplers_AWCACHE),\n        .m_axi_awid(m02_regslice_to_m02_couplers_AWID),\n        .m_axi_awlen(m02_regslice_to_m02_couplers_AWLEN),\n        .m_axi_awlock(m02_regslice_to_m02_couplers_AWLOCK),\n        .m_axi_awprot(m02_regslice_to_m02_couplers_AWPROT),\n        .m_axi_awqos(m02_regslice_to_m02_couplers_AWQOS),\n        .m_axi_awready(m02_regslice_to_m02_couplers_AWREADY),\n        .m_axi_awregion(m02_regslice_to_m02_couplers_AWREGION),\n        .m_axi_awsize(m02_regslice_to_m02_couplers_AWSIZE),\n        .m_axi_awvalid(m02_regslice_to_m02_couplers_AWVALID),\n        .m_axi_bid(m02_regslice_to_m02_couplers_BID),\n        .m_axi_bready(m02_regslice_to_m02_couplers_BREADY),\n        .m_axi_bresp(m02_regslice_to_m02_couplers_BRESP),\n        .m_axi_bvalid(m02_regslice_to_m02_couplers_BVALID),\n        .m_axi_rdata(m02_regslice_to_m02_couplers_RDATA),\n        .m_axi_rid(m02_regslice_to_m02_couplers_RID),\n        .m_axi_rlast(m02_regslice_to_m02_couplers_RLAST),\n        .m_axi_rready(m02_regslice_to_m02_couplers_RREADY),\n        .m_axi_rresp(m02_regslice_to_m02_couplers_RRESP),\n        .m_axi_rvalid(m02_regslice_to_m02_couplers_RVALID),\n        .m_axi_wdata(m02_regslice_to_m02_couplers_WDATA),\n        .m_axi_wlast(m02_regslice_to_m02_couplers_WLAST),\n        .m_axi_wready(m02_regslice_to_m02_couplers_WREADY),\n        .m_axi_wstrb(m02_regslice_to_m02_couplers_WSTRB),\n        .m_axi_wvalid(m02_regslice_to_m02_couplers_WVALID),\n        .s_axi_araddr(m02_couplers_to_m02_regslice_ARADDR),\n        .s_axi_arburst(m02_couplers_to_m02_regslice_ARBURST),\n        .s_axi_arcache(m02_couplers_to_m02_regslice_ARCACHE),\n        .s_axi_arid(m02_couplers_to_m02_regslice_ARID),\n        .s_axi_arlen(m02_couplers_to_m02_regslice_ARLEN),\n        .s_axi_arlock(m02_couplers_to_m02_regslice_ARLOCK),\n        .s_axi_arprot(m02_couplers_to_m02_regslice_ARPROT),\n        .s_axi_arqos(m02_couplers_to_m02_regslice_ARQOS),\n        .s_axi_arready(m02_couplers_to_m02_regslice_ARREADY),\n        .s_axi_arregion(m02_couplers_to_m02_regslice_ARREGION),\n        .s_axi_arsize(m02_couplers_to_m02_regslice_ARSIZE),\n        .s_axi_arvalid(m02_couplers_to_m02_regslice_ARVALID),\n        .s_axi_awaddr(m02_couplers_to_m02_regslice_AWADDR),\n        .s_axi_awburst(m02_couplers_to_m02_regslice_AWBURST),\n        .s_axi_awcache(m02_couplers_to_m02_regslice_AWCACHE),\n        .s_axi_awid(m02_couplers_to_m02_regslice_AWID),\n        .s_axi_awlen(m02_couplers_to_m02_regslice_AWLEN),\n        .s_axi_awlock(m02_couplers_to_m02_regslice_AWLOCK),\n        .s_axi_awprot(m02_couplers_to_m02_regslice_AWPROT),\n        .s_axi_awqos(m02_couplers_to_m02_regslice_AWQOS),\n        .s_axi_awready(m02_couplers_to_m02_regslice_AWREADY),\n        .s_axi_awregion(m02_couplers_to_m02_regslice_AWREGION),\n        .s_axi_awsize(m02_couplers_to_m02_regslice_AWSIZE),\n        .s_axi_awvalid(m02_couplers_to_m02_regslice_AWVALID),\n        .s_axi_bid(m02_couplers_to_m02_regslice_BID),\n        .s_axi_bready(m02_couplers_to_m02_regslice_BREADY),\n        .s_axi_bresp(m02_couplers_to_m02_regslice_BRESP),\n        .s_axi_bvalid(m02_couplers_to_m02_regslice_BVALID),\n        .s_axi_rdata(m02_couplers_to_m02_regslice_RDATA),\n        .s_axi_rid(m02_couplers_to_m02_regslice_RID),\n        .s_axi_rlast(m02_couplers_to_m02_regslice_RLAST),\n        .s_axi_rready(m02_couplers_to_m02_regslice_RREADY),\n        .s_axi_rresp(m02_couplers_to_m02_regslice_RRESP),\n        .s_axi_rvalid(m02_couplers_to_m02_regslice_RVALID),\n        .s_axi_wdata(m02_couplers_to_m02_regslice_WDATA),\n        .s_axi_wlast(m02_couplers_to_m02_regslice_WLAST),\n        .s_axi_wready(m02_couplers_to_m02_regslice_WREADY),\n        .s_axi_wstrb(m02_couplers_to_m02_regslice_WSTRB),\n        .s_axi_wvalid(m02_couplers_to_m02_regslice_WVALID));\nendmodule\n\nmodule m03_couplers_imp_JAYOMU\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arregion,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awregion,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [6:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [3:0]M_AXI_arregion;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [6:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [3:0]M_AXI_awregion;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [6:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [6:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [6:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [6:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire M_ACLK_1;\n  wire M_ARESETN_1;\n  wire [63:0]m03_couplers_to_m03_regslice_ARADDR;\n  wire [1:0]m03_couplers_to_m03_regslice_ARBURST;\n  wire [3:0]m03_couplers_to_m03_regslice_ARCACHE;\n  wire [6:0]m03_couplers_to_m03_regslice_ARID;\n  wire [7:0]m03_couplers_to_m03_regslice_ARLEN;\n  wire [0:0]m03_couplers_to_m03_regslice_ARLOCK;\n  wire [2:0]m03_couplers_to_m03_regslice_ARPROT;\n  wire [3:0]m03_couplers_to_m03_regslice_ARQOS;\n  wire m03_couplers_to_m03_regslice_ARREADY;\n  wire [3:0]m03_couplers_to_m03_regslice_ARREGION;\n  wire [2:0]m03_couplers_to_m03_regslice_ARSIZE;\n  wire m03_couplers_to_m03_regslice_ARVALID;\n  wire [63:0]m03_couplers_to_m03_regslice_AWADDR;\n  wire [1:0]m03_couplers_to_m03_regslice_AWBURST;\n  wire [3:0]m03_couplers_to_m03_regslice_AWCACHE;\n  wire [6:0]m03_couplers_to_m03_regslice_AWID;\n  wire [7:0]m03_couplers_to_m03_regslice_AWLEN;\n  wire [0:0]m03_couplers_to_m03_regslice_AWLOCK;\n  wire [2:0]m03_couplers_to_m03_regslice_AWPROT;\n  wire [3:0]m03_couplers_to_m03_regslice_AWQOS;\n  wire m03_couplers_to_m03_regslice_AWREADY;\n  wire [3:0]m03_couplers_to_m03_regslice_AWREGION;\n  wire [2:0]m03_couplers_to_m03_regslice_AWSIZE;\n  wire m03_couplers_to_m03_regslice_AWVALID;\n  wire [6:0]m03_couplers_to_m03_regslice_BID;\n  wire m03_couplers_to_m03_regslice_BREADY;\n  wire [1:0]m03_couplers_to_m03_regslice_BRESP;\n  wire m03_couplers_to_m03_regslice_BVALID;\n  wire [511:0]m03_couplers_to_m03_regslice_RDATA;\n  wire [6:0]m03_couplers_to_m03_regslice_RID;\n  wire m03_couplers_to_m03_regslice_RLAST;\n  wire m03_couplers_to_m03_regslice_RREADY;\n  wire [1:0]m03_couplers_to_m03_regslice_RRESP;\n  wire m03_couplers_to_m03_regslice_RVALID;\n  wire [511:0]m03_couplers_to_m03_regslice_WDATA;\n  wire m03_couplers_to_m03_regslice_WLAST;\n  wire m03_couplers_to_m03_regslice_WREADY;\n  wire [63:0]m03_couplers_to_m03_regslice_WSTRB;\n  wire m03_couplers_to_m03_regslice_WVALID;\n  wire [63:0]m03_regslice_to_m03_couplers_ARADDR;\n  wire [1:0]m03_regslice_to_m03_couplers_ARBURST;\n  wire [3:0]m03_regslice_to_m03_couplers_ARCACHE;\n  wire [6:0]m03_regslice_to_m03_couplers_ARID;\n  wire [7:0]m03_regslice_to_m03_couplers_ARLEN;\n  wire [0:0]m03_regslice_to_m03_couplers_ARLOCK;\n  wire [2:0]m03_regslice_to_m03_couplers_ARPROT;\n  wire [3:0]m03_regslice_to_m03_couplers_ARQOS;\n  wire m03_regslice_to_m03_couplers_ARREADY;\n  wire [3:0]m03_regslice_to_m03_couplers_ARREGION;\n  wire [2:0]m03_regslice_to_m03_couplers_ARSIZE;\n  wire m03_regslice_to_m03_couplers_ARVALID;\n  wire [63:0]m03_regslice_to_m03_couplers_AWADDR;\n  wire [1:0]m03_regslice_to_m03_couplers_AWBURST;\n  wire [3:0]m03_regslice_to_m03_couplers_AWCACHE;\n  wire [6:0]m03_regslice_to_m03_couplers_AWID;\n  wire [7:0]m03_regslice_to_m03_couplers_AWLEN;\n  wire [0:0]m03_regslice_to_m03_couplers_AWLOCK;\n  wire [2:0]m03_regslice_to_m03_couplers_AWPROT;\n  wire [3:0]m03_regslice_to_m03_couplers_AWQOS;\n  wire m03_regslice_to_m03_couplers_AWREADY;\n  wire [3:0]m03_regslice_to_m03_couplers_AWREGION;\n  wire [2:0]m03_regslice_to_m03_couplers_AWSIZE;\n  wire m03_regslice_to_m03_couplers_AWVALID;\n  wire [6:0]m03_regslice_to_m03_couplers_BID;\n  wire m03_regslice_to_m03_couplers_BREADY;\n  wire [1:0]m03_regslice_to_m03_couplers_BRESP;\n  wire m03_regslice_to_m03_couplers_BVALID;\n  wire [511:0]m03_regslice_to_m03_couplers_RDATA;\n  wire [6:0]m03_regslice_to_m03_couplers_RID;\n  wire m03_regslice_to_m03_couplers_RLAST;\n  wire m03_regslice_to_m03_couplers_RREADY;\n  wire [1:0]m03_regslice_to_m03_couplers_RRESP;\n  wire m03_regslice_to_m03_couplers_RVALID;\n  wire [511:0]m03_regslice_to_m03_couplers_WDATA;\n  wire m03_regslice_to_m03_couplers_WLAST;\n  wire m03_regslice_to_m03_couplers_WREADY;\n  wire [63:0]m03_regslice_to_m03_couplers_WSTRB;\n  wire m03_regslice_to_m03_couplers_WVALID;\n\n  assign M_ACLK_1 = M_ACLK;\n  assign M_ARESETN_1 = M_ARESETN;\n  assign M_AXI_araddr[63:0] = m03_regslice_to_m03_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = m03_regslice_to_m03_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = m03_regslice_to_m03_couplers_ARCACHE;\n  assign M_AXI_arid[6:0] = m03_regslice_to_m03_couplers_ARID;\n  assign M_AXI_arlen[7:0] = m03_regslice_to_m03_couplers_ARLEN;\n  assign M_AXI_arlock[0] = m03_regslice_to_m03_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = m03_regslice_to_m03_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = m03_regslice_to_m03_couplers_ARQOS;\n  assign M_AXI_arregion[3:0] = m03_regslice_to_m03_couplers_ARREGION;\n  assign M_AXI_arsize[2:0] = m03_regslice_to_m03_couplers_ARSIZE;\n  assign M_AXI_arvalid = m03_regslice_to_m03_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = m03_regslice_to_m03_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = m03_regslice_to_m03_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = m03_regslice_to_m03_couplers_AWCACHE;\n  assign M_AXI_awid[6:0] = m03_regslice_to_m03_couplers_AWID;\n  assign M_AXI_awlen[7:0] = m03_regslice_to_m03_couplers_AWLEN;\n  assign M_AXI_awlock[0] = m03_regslice_to_m03_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = m03_regslice_to_m03_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = m03_regslice_to_m03_couplers_AWQOS;\n  assign M_AXI_awregion[3:0] = m03_regslice_to_m03_couplers_AWREGION;\n  assign M_AXI_awsize[2:0] = m03_regslice_to_m03_couplers_AWSIZE;\n  assign M_AXI_awvalid = m03_regslice_to_m03_couplers_AWVALID;\n  assign M_AXI_bready = m03_regslice_to_m03_couplers_BREADY;\n  assign M_AXI_rready = m03_regslice_to_m03_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = m03_regslice_to_m03_couplers_WDATA;\n  assign M_AXI_wlast = m03_regslice_to_m03_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = m03_regslice_to_m03_couplers_WSTRB;\n  assign M_AXI_wvalid = m03_regslice_to_m03_couplers_WVALID;\n  assign S_AXI_arready = m03_couplers_to_m03_regslice_ARREADY;\n  assign S_AXI_awready = m03_couplers_to_m03_regslice_AWREADY;\n  assign S_AXI_bid[6:0] = m03_couplers_to_m03_regslice_BID;\n  assign S_AXI_bresp[1:0] = m03_couplers_to_m03_regslice_BRESP;\n  assign S_AXI_bvalid = m03_couplers_to_m03_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = m03_couplers_to_m03_regslice_RDATA;\n  assign S_AXI_rid[6:0] = m03_couplers_to_m03_regslice_RID;\n  assign S_AXI_rlast = m03_couplers_to_m03_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = m03_couplers_to_m03_regslice_RRESP;\n  assign S_AXI_rvalid = m03_couplers_to_m03_regslice_RVALID;\n  assign S_AXI_wready = m03_couplers_to_m03_regslice_WREADY;\n  assign m03_couplers_to_m03_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign m03_couplers_to_m03_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign m03_couplers_to_m03_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign m03_couplers_to_m03_regslice_ARID = S_AXI_arid[6:0];\n  assign m03_couplers_to_m03_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign m03_couplers_to_m03_regslice_ARLOCK = S_AXI_arlock[0];\n  assign m03_couplers_to_m03_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign m03_couplers_to_m03_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign m03_couplers_to_m03_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign m03_couplers_to_m03_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign m03_couplers_to_m03_regslice_ARVALID = S_AXI_arvalid;\n  assign m03_couplers_to_m03_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign m03_couplers_to_m03_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign m03_couplers_to_m03_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign m03_couplers_to_m03_regslice_AWID = S_AXI_awid[6:0];\n  assign m03_couplers_to_m03_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign m03_couplers_to_m03_regslice_AWLOCK = S_AXI_awlock[0];\n  assign m03_couplers_to_m03_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign m03_couplers_to_m03_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign m03_couplers_to_m03_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign m03_couplers_to_m03_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign m03_couplers_to_m03_regslice_AWVALID = S_AXI_awvalid;\n  assign m03_couplers_to_m03_regslice_BREADY = S_AXI_bready;\n  assign m03_couplers_to_m03_regslice_RREADY = S_AXI_rready;\n  assign m03_couplers_to_m03_regslice_WDATA = S_AXI_wdata[511:0];\n  assign m03_couplers_to_m03_regslice_WLAST = S_AXI_wlast;\n  assign m03_couplers_to_m03_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign m03_couplers_to_m03_regslice_WVALID = S_AXI_wvalid;\n  assign m03_regslice_to_m03_couplers_ARREADY = M_AXI_arready;\n  assign m03_regslice_to_m03_couplers_AWREADY = M_AXI_awready;\n  assign m03_regslice_to_m03_couplers_BID = M_AXI_bid[6:0];\n  assign m03_regslice_to_m03_couplers_BRESP = M_AXI_bresp[1:0];\n  assign m03_regslice_to_m03_couplers_BVALID = M_AXI_bvalid;\n  assign m03_regslice_to_m03_couplers_RDATA = M_AXI_rdata[511:0];\n  assign m03_regslice_to_m03_couplers_RID = M_AXI_rid[6:0];\n  assign m03_regslice_to_m03_couplers_RLAST = M_AXI_rlast;\n  assign m03_regslice_to_m03_couplers_RRESP = M_AXI_rresp[1:0];\n  assign m03_regslice_to_m03_couplers_RVALID = M_AXI_rvalid;\n  assign m03_regslice_to_m03_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_m03_regslice_0 m03_regslice\n       (.aclk(M_ACLK_1),\n        .aresetn(M_ARESETN_1),\n        .m_axi_araddr(m03_regslice_to_m03_couplers_ARADDR),\n        .m_axi_arburst(m03_regslice_to_m03_couplers_ARBURST),\n        .m_axi_arcache(m03_regslice_to_m03_couplers_ARCACHE),\n        .m_axi_arid(m03_regslice_to_m03_couplers_ARID),\n        .m_axi_arlen(m03_regslice_to_m03_couplers_ARLEN),\n        .m_axi_arlock(m03_regslice_to_m03_couplers_ARLOCK),\n        .m_axi_arprot(m03_regslice_to_m03_couplers_ARPROT),\n        .m_axi_arqos(m03_regslice_to_m03_couplers_ARQOS),\n        .m_axi_arready(m03_regslice_to_m03_couplers_ARREADY),\n        .m_axi_arregion(m03_regslice_to_m03_couplers_ARREGION),\n        .m_axi_arsize(m03_regslice_to_m03_couplers_ARSIZE),\n        .m_axi_arvalid(m03_regslice_to_m03_couplers_ARVALID),\n        .m_axi_awaddr(m03_regslice_to_m03_couplers_AWADDR),\n        .m_axi_awburst(m03_regslice_to_m03_couplers_AWBURST),\n        .m_axi_awcache(m03_regslice_to_m03_couplers_AWCACHE),\n        .m_axi_awid(m03_regslice_to_m03_couplers_AWID),\n        .m_axi_awlen(m03_regslice_to_m03_couplers_AWLEN),\n        .m_axi_awlock(m03_regslice_to_m03_couplers_AWLOCK),\n        .m_axi_awprot(m03_regslice_to_m03_couplers_AWPROT),\n        .m_axi_awqos(m03_regslice_to_m03_couplers_AWQOS),\n        .m_axi_awready(m03_regslice_to_m03_couplers_AWREADY),\n        .m_axi_awregion(m03_regslice_to_m03_couplers_AWREGION),\n        .m_axi_awsize(m03_regslice_to_m03_couplers_AWSIZE),\n        .m_axi_awvalid(m03_regslice_to_m03_couplers_AWVALID),\n        .m_axi_bid(m03_regslice_to_m03_couplers_BID),\n        .m_axi_bready(m03_regslice_to_m03_couplers_BREADY),\n        .m_axi_bresp(m03_regslice_to_m03_couplers_BRESP),\n        .m_axi_bvalid(m03_regslice_to_m03_couplers_BVALID),\n        .m_axi_rdata(m03_regslice_to_m03_couplers_RDATA),\n        .m_axi_rid(m03_regslice_to_m03_couplers_RID),\n        .m_axi_rlast(m03_regslice_to_m03_couplers_RLAST),\n        .m_axi_rready(m03_regslice_to_m03_couplers_RREADY),\n        .m_axi_rresp(m03_regslice_to_m03_couplers_RRESP),\n        .m_axi_rvalid(m03_regslice_to_m03_couplers_RVALID),\n        .m_axi_wdata(m03_regslice_to_m03_couplers_WDATA),\n        .m_axi_wlast(m03_regslice_to_m03_couplers_WLAST),\n        .m_axi_wready(m03_regslice_to_m03_couplers_WREADY),\n        .m_axi_wstrb(m03_regslice_to_m03_couplers_WSTRB),\n        .m_axi_wvalid(m03_regslice_to_m03_couplers_WVALID),\n        .s_axi_araddr(m03_couplers_to_m03_regslice_ARADDR),\n        .s_axi_arburst(m03_couplers_to_m03_regslice_ARBURST),\n        .s_axi_arcache(m03_couplers_to_m03_regslice_ARCACHE),\n        .s_axi_arid(m03_couplers_to_m03_regslice_ARID),\n        .s_axi_arlen(m03_couplers_to_m03_regslice_ARLEN),\n        .s_axi_arlock(m03_couplers_to_m03_regslice_ARLOCK),\n        .s_axi_arprot(m03_couplers_to_m03_regslice_ARPROT),\n        .s_axi_arqos(m03_couplers_to_m03_regslice_ARQOS),\n        .s_axi_arready(m03_couplers_to_m03_regslice_ARREADY),\n        .s_axi_arregion(m03_couplers_to_m03_regslice_ARREGION),\n        .s_axi_arsize(m03_couplers_to_m03_regslice_ARSIZE),\n        .s_axi_arvalid(m03_couplers_to_m03_regslice_ARVALID),\n        .s_axi_awaddr(m03_couplers_to_m03_regslice_AWADDR),\n        .s_axi_awburst(m03_couplers_to_m03_regslice_AWBURST),\n        .s_axi_awcache(m03_couplers_to_m03_regslice_AWCACHE),\n        .s_axi_awid(m03_couplers_to_m03_regslice_AWID),\n        .s_axi_awlen(m03_couplers_to_m03_regslice_AWLEN),\n        .s_axi_awlock(m03_couplers_to_m03_regslice_AWLOCK),\n        .s_axi_awprot(m03_couplers_to_m03_regslice_AWPROT),\n        .s_axi_awqos(m03_couplers_to_m03_regslice_AWQOS),\n        .s_axi_awready(m03_couplers_to_m03_regslice_AWREADY),\n        .s_axi_awregion(m03_couplers_to_m03_regslice_AWREGION),\n        .s_axi_awsize(m03_couplers_to_m03_regslice_AWSIZE),\n        .s_axi_awvalid(m03_couplers_to_m03_regslice_AWVALID),\n        .s_axi_bid(m03_couplers_to_m03_regslice_BID),\n        .s_axi_bready(m03_couplers_to_m03_regslice_BREADY),\n        .s_axi_bresp(m03_couplers_to_m03_regslice_BRESP),\n        .s_axi_bvalid(m03_couplers_to_m03_regslice_BVALID),\n        .s_axi_rdata(m03_couplers_to_m03_regslice_RDATA),\n        .s_axi_rid(m03_couplers_to_m03_regslice_RID),\n        .s_axi_rlast(m03_couplers_to_m03_regslice_RLAST),\n        .s_axi_rready(m03_couplers_to_m03_regslice_RREADY),\n        .s_axi_rresp(m03_couplers_to_m03_regslice_RRESP),\n        .s_axi_rvalid(m03_couplers_to_m03_regslice_RVALID),\n        .s_axi_wdata(m03_couplers_to_m03_regslice_WDATA),\n        .s_axi_wlast(m03_couplers_to_m03_regslice_WLAST),\n        .s_axi_wready(m03_couplers_to_m03_regslice_WREADY),\n        .s_axi_wstrb(m03_couplers_to_m03_regslice_WSTRB),\n        .s_axi_wvalid(m03_couplers_to_m03_regslice_WVALID));\nendmodule\n\nmodule s00_couplers_imp_QICM5G\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [5:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [5:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [5:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [5:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [5:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [5:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire S_ACLK_1;\n  wire S_ARESETN_1;\n  wire [63:0]s00_couplers_to_s00_regslice_ARADDR;\n  wire [1:0]s00_couplers_to_s00_regslice_ARBURST;\n  wire [3:0]s00_couplers_to_s00_regslice_ARCACHE;\n  wire [5:0]s00_couplers_to_s00_regslice_ARID;\n  wire [7:0]s00_couplers_to_s00_regslice_ARLEN;\n  wire [0:0]s00_couplers_to_s00_regslice_ARLOCK;\n  wire [2:0]s00_couplers_to_s00_regslice_ARPROT;\n  wire [3:0]s00_couplers_to_s00_regslice_ARQOS;\n  wire s00_couplers_to_s00_regslice_ARREADY;\n  wire [3:0]s00_couplers_to_s00_regslice_ARREGION;\n  wire [2:0]s00_couplers_to_s00_regslice_ARSIZE;\n  wire s00_couplers_to_s00_regslice_ARVALID;\n  wire [63:0]s00_couplers_to_s00_regslice_AWADDR;\n  wire [1:0]s00_couplers_to_s00_regslice_AWBURST;\n  wire [3:0]s00_couplers_to_s00_regslice_AWCACHE;\n  wire [5:0]s00_couplers_to_s00_regslice_AWID;\n  wire [7:0]s00_couplers_to_s00_regslice_AWLEN;\n  wire [0:0]s00_couplers_to_s00_regslice_AWLOCK;\n  wire [2:0]s00_couplers_to_s00_regslice_AWPROT;\n  wire [3:0]s00_couplers_to_s00_regslice_AWQOS;\n  wire s00_couplers_to_s00_regslice_AWREADY;\n  wire [3:0]s00_couplers_to_s00_regslice_AWREGION;\n  wire [2:0]s00_couplers_to_s00_regslice_AWSIZE;\n  wire s00_couplers_to_s00_regslice_AWVALID;\n  wire [5:0]s00_couplers_to_s00_regslice_BID;\n  wire s00_couplers_to_s00_regslice_BREADY;\n  wire [1:0]s00_couplers_to_s00_regslice_BRESP;\n  wire s00_couplers_to_s00_regslice_BVALID;\n  wire [511:0]s00_couplers_to_s00_regslice_RDATA;\n  wire [5:0]s00_couplers_to_s00_regslice_RID;\n  wire s00_couplers_to_s00_regslice_RLAST;\n  wire s00_couplers_to_s00_regslice_RREADY;\n  wire [1:0]s00_couplers_to_s00_regslice_RRESP;\n  wire s00_couplers_to_s00_regslice_RVALID;\n  wire [511:0]s00_couplers_to_s00_regslice_WDATA;\n  wire s00_couplers_to_s00_regslice_WLAST;\n  wire s00_couplers_to_s00_regslice_WREADY;\n  wire [63:0]s00_couplers_to_s00_regslice_WSTRB;\n  wire s00_couplers_to_s00_regslice_WVALID;\n  wire [63:0]s00_regslice_to_s00_couplers_ARADDR;\n  wire [1:0]s00_regslice_to_s00_couplers_ARBURST;\n  wire [3:0]s00_regslice_to_s00_couplers_ARCACHE;\n  wire [5:0]s00_regslice_to_s00_couplers_ARID;\n  wire [7:0]s00_regslice_to_s00_couplers_ARLEN;\n  wire [0:0]s00_regslice_to_s00_couplers_ARLOCK;\n  wire [2:0]s00_regslice_to_s00_couplers_ARPROT;\n  wire [3:0]s00_regslice_to_s00_couplers_ARQOS;\n  wire s00_regslice_to_s00_couplers_ARREADY;\n  wire [2:0]s00_regslice_to_s00_couplers_ARSIZE;\n  wire s00_regslice_to_s00_couplers_ARVALID;\n  wire [63:0]s00_regslice_to_s00_couplers_AWADDR;\n  wire [1:0]s00_regslice_to_s00_couplers_AWBURST;\n  wire [3:0]s00_regslice_to_s00_couplers_AWCACHE;\n  wire [5:0]s00_regslice_to_s00_couplers_AWID;\n  wire [7:0]s00_regslice_to_s00_couplers_AWLEN;\n  wire [0:0]s00_regslice_to_s00_couplers_AWLOCK;\n  wire [2:0]s00_regslice_to_s00_couplers_AWPROT;\n  wire [3:0]s00_regslice_to_s00_couplers_AWQOS;\n  wire s00_regslice_to_s00_couplers_AWREADY;\n  wire [2:0]s00_regslice_to_s00_couplers_AWSIZE;\n  wire s00_regslice_to_s00_couplers_AWVALID;\n  wire [6:0]s00_regslice_to_s00_couplers_BID;\n  wire s00_regslice_to_s00_couplers_BREADY;\n  wire [1:0]s00_regslice_to_s00_couplers_BRESP;\n  wire s00_regslice_to_s00_couplers_BVALID;\n  wire [511:0]s00_regslice_to_s00_couplers_RDATA;\n  wire [6:0]s00_regslice_to_s00_couplers_RID;\n  wire s00_regslice_to_s00_couplers_RLAST;\n  wire s00_regslice_to_s00_couplers_RREADY;\n  wire [1:0]s00_regslice_to_s00_couplers_RRESP;\n  wire s00_regslice_to_s00_couplers_RVALID;\n  wire [511:0]s00_regslice_to_s00_couplers_WDATA;\n  wire s00_regslice_to_s00_couplers_WLAST;\n  wire s00_regslice_to_s00_couplers_WREADY;\n  wire [63:0]s00_regslice_to_s00_couplers_WSTRB;\n  wire s00_regslice_to_s00_couplers_WVALID;\n\n  assign M_AXI_araddr[63:0] = s00_regslice_to_s00_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = s00_regslice_to_s00_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = s00_regslice_to_s00_couplers_ARCACHE;\n  assign M_AXI_arid[5:0] = s00_regslice_to_s00_couplers_ARID;\n  assign M_AXI_arlen[7:0] = s00_regslice_to_s00_couplers_ARLEN;\n  assign M_AXI_arlock[0] = s00_regslice_to_s00_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = s00_regslice_to_s00_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = s00_regslice_to_s00_couplers_ARQOS;\n  assign M_AXI_arsize[2:0] = s00_regslice_to_s00_couplers_ARSIZE;\n  assign M_AXI_arvalid = s00_regslice_to_s00_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = s00_regslice_to_s00_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = s00_regslice_to_s00_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = s00_regslice_to_s00_couplers_AWCACHE;\n  assign M_AXI_awid[5:0] = s00_regslice_to_s00_couplers_AWID;\n  assign M_AXI_awlen[7:0] = s00_regslice_to_s00_couplers_AWLEN;\n  assign M_AXI_awlock[0] = s00_regslice_to_s00_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = s00_regslice_to_s00_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = s00_regslice_to_s00_couplers_AWQOS;\n  assign M_AXI_awsize[2:0] = s00_regslice_to_s00_couplers_AWSIZE;\n  assign M_AXI_awvalid = s00_regslice_to_s00_couplers_AWVALID;\n  assign M_AXI_bready = s00_regslice_to_s00_couplers_BREADY;\n  assign M_AXI_rready = s00_regslice_to_s00_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = s00_regslice_to_s00_couplers_WDATA;\n  assign M_AXI_wlast = s00_regslice_to_s00_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = s00_regslice_to_s00_couplers_WSTRB;\n  assign M_AXI_wvalid = s00_regslice_to_s00_couplers_WVALID;\n  assign S_ACLK_1 = S_ACLK;\n  assign S_ARESETN_1 = S_ARESETN;\n  assign S_AXI_arready = s00_couplers_to_s00_regslice_ARREADY;\n  assign S_AXI_awready = s00_couplers_to_s00_regslice_AWREADY;\n  assign S_AXI_bid[5:0] = s00_couplers_to_s00_regslice_BID;\n  assign S_AXI_bresp[1:0] = s00_couplers_to_s00_regslice_BRESP;\n  assign S_AXI_bvalid = s00_couplers_to_s00_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = s00_couplers_to_s00_regslice_RDATA;\n  assign S_AXI_rid[5:0] = s00_couplers_to_s00_regslice_RID;\n  assign S_AXI_rlast = s00_couplers_to_s00_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = s00_couplers_to_s00_regslice_RRESP;\n  assign S_AXI_rvalid = s00_couplers_to_s00_regslice_RVALID;\n  assign S_AXI_wready = s00_couplers_to_s00_regslice_WREADY;\n  assign s00_couplers_to_s00_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign s00_couplers_to_s00_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign s00_couplers_to_s00_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign s00_couplers_to_s00_regslice_ARID = S_AXI_arid[5:0];\n  assign s00_couplers_to_s00_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign s00_couplers_to_s00_regslice_ARLOCK = S_AXI_arlock[0];\n  assign s00_couplers_to_s00_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign s00_couplers_to_s00_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign s00_couplers_to_s00_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign s00_couplers_to_s00_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign s00_couplers_to_s00_regslice_ARVALID = S_AXI_arvalid;\n  assign s00_couplers_to_s00_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign s00_couplers_to_s00_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign s00_couplers_to_s00_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign s00_couplers_to_s00_regslice_AWID = S_AXI_awid[5:0];\n  assign s00_couplers_to_s00_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign s00_couplers_to_s00_regslice_AWLOCK = S_AXI_awlock[0];\n  assign s00_couplers_to_s00_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign s00_couplers_to_s00_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign s00_couplers_to_s00_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign s00_couplers_to_s00_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign s00_couplers_to_s00_regslice_AWVALID = S_AXI_awvalid;\n  assign s00_couplers_to_s00_regslice_BREADY = S_AXI_bready;\n  assign s00_couplers_to_s00_regslice_RREADY = S_AXI_rready;\n  assign s00_couplers_to_s00_regslice_WDATA = S_AXI_wdata[511:0];\n  assign s00_couplers_to_s00_regslice_WLAST = S_AXI_wlast;\n  assign s00_couplers_to_s00_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign s00_couplers_to_s00_regslice_WVALID = S_AXI_wvalid;\n  assign s00_regslice_to_s00_couplers_ARREADY = M_AXI_arready;\n  assign s00_regslice_to_s00_couplers_AWREADY = M_AXI_awready;\n  assign s00_regslice_to_s00_couplers_BID = M_AXI_bid[6:0];\n  assign s00_regslice_to_s00_couplers_BRESP = M_AXI_bresp[1:0];\n  assign s00_regslice_to_s00_couplers_BVALID = M_AXI_bvalid;\n  assign s00_regslice_to_s00_couplers_RDATA = M_AXI_rdata[511:0];\n  assign s00_regslice_to_s00_couplers_RID = M_AXI_rid[6:0];\n  assign s00_regslice_to_s00_couplers_RLAST = M_AXI_rlast;\n  assign s00_regslice_to_s00_couplers_RRESP = M_AXI_rresp[1:0];\n  assign s00_regslice_to_s00_couplers_RVALID = M_AXI_rvalid;\n  assign s00_regslice_to_s00_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_s00_regslice_0 s00_regslice\n       (.aclk(S_ACLK_1),\n        .aresetn(S_ARESETN_1),\n        .m_axi_araddr(s00_regslice_to_s00_couplers_ARADDR),\n        .m_axi_arburst(s00_regslice_to_s00_couplers_ARBURST),\n        .m_axi_arcache(s00_regslice_to_s00_couplers_ARCACHE),\n        .m_axi_arid(s00_regslice_to_s00_couplers_ARID),\n        .m_axi_arlen(s00_regslice_to_s00_couplers_ARLEN),\n        .m_axi_arlock(s00_regslice_to_s00_couplers_ARLOCK),\n        .m_axi_arprot(s00_regslice_to_s00_couplers_ARPROT),\n        .m_axi_arqos(s00_regslice_to_s00_couplers_ARQOS),\n        .m_axi_arready(s00_regslice_to_s00_couplers_ARREADY),\n        .m_axi_arsize(s00_regslice_to_s00_couplers_ARSIZE),\n        .m_axi_arvalid(s00_regslice_to_s00_couplers_ARVALID),\n        .m_axi_awaddr(s00_regslice_to_s00_couplers_AWADDR),\n        .m_axi_awburst(s00_regslice_to_s00_couplers_AWBURST),\n        .m_axi_awcache(s00_regslice_to_s00_couplers_AWCACHE),\n        .m_axi_awid(s00_regslice_to_s00_couplers_AWID),\n        .m_axi_awlen(s00_regslice_to_s00_couplers_AWLEN),\n        .m_axi_awlock(s00_regslice_to_s00_couplers_AWLOCK),\n        .m_axi_awprot(s00_regslice_to_s00_couplers_AWPROT),\n        .m_axi_awqos(s00_regslice_to_s00_couplers_AWQOS),\n        .m_axi_awready(s00_regslice_to_s00_couplers_AWREADY),\n        .m_axi_awsize(s00_regslice_to_s00_couplers_AWSIZE),\n        .m_axi_awvalid(s00_regslice_to_s00_couplers_AWVALID),\n        .m_axi_bid(s00_regslice_to_s00_couplers_BID[5:0]),\n        .m_axi_bready(s00_regslice_to_s00_couplers_BREADY),\n        .m_axi_bresp(s00_regslice_to_s00_couplers_BRESP),\n        .m_axi_bvalid(s00_regslice_to_s00_couplers_BVALID),\n        .m_axi_rdata(s00_regslice_to_s00_couplers_RDATA),\n        .m_axi_rid(s00_regslice_to_s00_couplers_RID[5:0]),\n        .m_axi_rlast(s00_regslice_to_s00_couplers_RLAST),\n        .m_axi_rready(s00_regslice_to_s00_couplers_RREADY),\n        .m_axi_rresp(s00_regslice_to_s00_couplers_RRESP),\n        .m_axi_rvalid(s00_regslice_to_s00_couplers_RVALID),\n        .m_axi_wdata(s00_regslice_to_s00_couplers_WDATA),\n        .m_axi_wlast(s00_regslice_to_s00_couplers_WLAST),\n        .m_axi_wready(s00_regslice_to_s00_couplers_WREADY),\n        .m_axi_wstrb(s00_regslice_to_s00_couplers_WSTRB),\n        .m_axi_wvalid(s00_regslice_to_s00_couplers_WVALID),\n        .s_axi_araddr(s00_couplers_to_s00_regslice_ARADDR),\n        .s_axi_arburst(s00_couplers_to_s00_regslice_ARBURST),\n        .s_axi_arcache(s00_couplers_to_s00_regslice_ARCACHE),\n        .s_axi_arid(s00_couplers_to_s00_regslice_ARID),\n        .s_axi_arlen(s00_couplers_to_s00_regslice_ARLEN),\n        .s_axi_arlock(s00_couplers_to_s00_regslice_ARLOCK),\n        .s_axi_arprot(s00_couplers_to_s00_regslice_ARPROT),\n        .s_axi_arqos(s00_couplers_to_s00_regslice_ARQOS),\n        .s_axi_arready(s00_couplers_to_s00_regslice_ARREADY),\n        .s_axi_arregion(s00_couplers_to_s00_regslice_ARREGION),\n        .s_axi_arsize(s00_couplers_to_s00_regslice_ARSIZE),\n        .s_axi_arvalid(s00_couplers_to_s00_regslice_ARVALID),\n        .s_axi_awaddr(s00_couplers_to_s00_regslice_AWADDR),\n        .s_axi_awburst(s00_couplers_to_s00_regslice_AWBURST),\n        .s_axi_awcache(s00_couplers_to_s00_regslice_AWCACHE),\n        .s_axi_awid(s00_couplers_to_s00_regslice_AWID),\n        .s_axi_awlen(s00_couplers_to_s00_regslice_AWLEN),\n        .s_axi_awlock(s00_couplers_to_s00_regslice_AWLOCK),\n        .s_axi_awprot(s00_couplers_to_s00_regslice_AWPROT),\n        .s_axi_awqos(s00_couplers_to_s00_regslice_AWQOS),\n        .s_axi_awready(s00_couplers_to_s00_regslice_AWREADY),\n        .s_axi_awregion(s00_couplers_to_s00_regslice_AWREGION),\n        .s_axi_awsize(s00_couplers_to_s00_regslice_AWSIZE),\n        .s_axi_awvalid(s00_couplers_to_s00_regslice_AWVALID),\n        .s_axi_bid(s00_couplers_to_s00_regslice_BID),\n        .s_axi_bready(s00_couplers_to_s00_regslice_BREADY),\n        .s_axi_bresp(s00_couplers_to_s00_regslice_BRESP),\n        .s_axi_bvalid(s00_couplers_to_s00_regslice_BVALID),\n        .s_axi_rdata(s00_couplers_to_s00_regslice_RDATA),\n        .s_axi_rid(s00_couplers_to_s00_regslice_RID),\n        .s_axi_rlast(s00_couplers_to_s00_regslice_RLAST),\n        .s_axi_rready(s00_couplers_to_s00_regslice_RREADY),\n        .s_axi_rresp(s00_couplers_to_s00_regslice_RRESP),\n        .s_axi_rvalid(s00_couplers_to_s00_regslice_RVALID),\n        .s_axi_wdata(s00_couplers_to_s00_regslice_WDATA),\n        .s_axi_wlast(s00_couplers_to_s00_regslice_WLAST),\n        .s_axi_wready(s00_couplers_to_s00_regslice_WREADY),\n        .s_axi_wstrb(s00_couplers_to_s00_regslice_WSTRB),\n        .s_axi_wvalid(s00_couplers_to_s00_regslice_WVALID));\nendmodule\n\nmodule s01_couplers_imp_GSTXQ8\n   (M_ACLK,\n    M_ARESETN,\n    M_AXI_araddr,\n    M_AXI_arburst,\n    M_AXI_arcache,\n    M_AXI_arid,\n    M_AXI_arlen,\n    M_AXI_arlock,\n    M_AXI_arprot,\n    M_AXI_arqos,\n    M_AXI_arready,\n    M_AXI_arsize,\n    M_AXI_arvalid,\n    M_AXI_awaddr,\n    M_AXI_awburst,\n    M_AXI_awcache,\n    M_AXI_awid,\n    M_AXI_awlen,\n    M_AXI_awlock,\n    M_AXI_awprot,\n    M_AXI_awqos,\n    M_AXI_awready,\n    M_AXI_awsize,\n    M_AXI_awvalid,\n    M_AXI_bid,\n    M_AXI_bready,\n    M_AXI_bresp,\n    M_AXI_bvalid,\n    M_AXI_rdata,\n    M_AXI_rid,\n    M_AXI_rlast,\n    M_AXI_rready,\n    M_AXI_rresp,\n    M_AXI_rvalid,\n    M_AXI_wdata,\n    M_AXI_wlast,\n    M_AXI_wready,\n    M_AXI_wstrb,\n    M_AXI_wvalid,\n    S_ACLK,\n    S_ARESETN,\n    S_AXI_araddr,\n    S_AXI_arburst,\n    S_AXI_arcache,\n    S_AXI_arid,\n    S_AXI_arlen,\n    S_AXI_arlock,\n    S_AXI_arprot,\n    S_AXI_arqos,\n    S_AXI_arready,\n    S_AXI_arregion,\n    S_AXI_arsize,\n    S_AXI_arvalid,\n    S_AXI_awaddr,\n    S_AXI_awburst,\n    S_AXI_awcache,\n    S_AXI_awid,\n    S_AXI_awlen,\n    S_AXI_awlock,\n    S_AXI_awprot,\n    S_AXI_awqos,\n    S_AXI_awready,\n    S_AXI_awregion,\n    S_AXI_awsize,\n    S_AXI_awvalid,\n    S_AXI_bid,\n    S_AXI_bready,\n    S_AXI_bresp,\n    S_AXI_bvalid,\n    S_AXI_rdata,\n    S_AXI_rid,\n    S_AXI_rlast,\n    S_AXI_rready,\n    S_AXI_rresp,\n    S_AXI_rvalid,\n    S_AXI_wdata,\n    S_AXI_wlast,\n    S_AXI_wready,\n    S_AXI_wstrb,\n    S_AXI_wvalid);\n  input M_ACLK;\n  input M_ARESETN;\n  output [63:0]M_AXI_araddr;\n  output [1:0]M_AXI_arburst;\n  output [3:0]M_AXI_arcache;\n  output [5:0]M_AXI_arid;\n  output [7:0]M_AXI_arlen;\n  output [0:0]M_AXI_arlock;\n  output [2:0]M_AXI_arprot;\n  output [3:0]M_AXI_arqos;\n  input M_AXI_arready;\n  output [2:0]M_AXI_arsize;\n  output M_AXI_arvalid;\n  output [63:0]M_AXI_awaddr;\n  output [1:0]M_AXI_awburst;\n  output [3:0]M_AXI_awcache;\n  output [5:0]M_AXI_awid;\n  output [7:0]M_AXI_awlen;\n  output [0:0]M_AXI_awlock;\n  output [2:0]M_AXI_awprot;\n  output [3:0]M_AXI_awqos;\n  input M_AXI_awready;\n  output [2:0]M_AXI_awsize;\n  output M_AXI_awvalid;\n  input [6:0]M_AXI_bid;\n  output M_AXI_bready;\n  input [1:0]M_AXI_bresp;\n  input M_AXI_bvalid;\n  input [511:0]M_AXI_rdata;\n  input [6:0]M_AXI_rid;\n  input M_AXI_rlast;\n  output M_AXI_rready;\n  input [1:0]M_AXI_rresp;\n  input M_AXI_rvalid;\n  output [511:0]M_AXI_wdata;\n  output M_AXI_wlast;\n  input M_AXI_wready;\n  output [63:0]M_AXI_wstrb;\n  output M_AXI_wvalid;\n  input S_ACLK;\n  input S_ARESETN;\n  input [63:0]S_AXI_araddr;\n  input [1:0]S_AXI_arburst;\n  input [3:0]S_AXI_arcache;\n  input [5:0]S_AXI_arid;\n  input [7:0]S_AXI_arlen;\n  input [0:0]S_AXI_arlock;\n  input [2:0]S_AXI_arprot;\n  input [3:0]S_AXI_arqos;\n  output S_AXI_arready;\n  input [3:0]S_AXI_arregion;\n  input [2:0]S_AXI_arsize;\n  input S_AXI_arvalid;\n  input [63:0]S_AXI_awaddr;\n  input [1:0]S_AXI_awburst;\n  input [3:0]S_AXI_awcache;\n  input [5:0]S_AXI_awid;\n  input [7:0]S_AXI_awlen;\n  input [0:0]S_AXI_awlock;\n  input [2:0]S_AXI_awprot;\n  input [3:0]S_AXI_awqos;\n  output S_AXI_awready;\n  input [3:0]S_AXI_awregion;\n  input [2:0]S_AXI_awsize;\n  input S_AXI_awvalid;\n  output [5:0]S_AXI_bid;\n  input S_AXI_bready;\n  output [1:0]S_AXI_bresp;\n  output S_AXI_bvalid;\n  output [511:0]S_AXI_rdata;\n  output [5:0]S_AXI_rid;\n  output S_AXI_rlast;\n  input S_AXI_rready;\n  output [1:0]S_AXI_rresp;\n  output S_AXI_rvalid;\n  input [511:0]S_AXI_wdata;\n  input S_AXI_wlast;\n  output S_AXI_wready;\n  input [63:0]S_AXI_wstrb;\n  input S_AXI_wvalid;\n\n  wire S_ACLK_1;\n  wire S_ARESETN_1;\n  wire [63:0]s01_couplers_to_s01_regslice_ARADDR;\n  wire [1:0]s01_couplers_to_s01_regslice_ARBURST;\n  wire [3:0]s01_couplers_to_s01_regslice_ARCACHE;\n  wire [5:0]s01_couplers_to_s01_regslice_ARID;\n  wire [7:0]s01_couplers_to_s01_regslice_ARLEN;\n  wire [0:0]s01_couplers_to_s01_regslice_ARLOCK;\n  wire [2:0]s01_couplers_to_s01_regslice_ARPROT;\n  wire [3:0]s01_couplers_to_s01_regslice_ARQOS;\n  wire s01_couplers_to_s01_regslice_ARREADY;\n  wire [3:0]s01_couplers_to_s01_regslice_ARREGION;\n  wire [2:0]s01_couplers_to_s01_regslice_ARSIZE;\n  wire s01_couplers_to_s01_regslice_ARVALID;\n  wire [63:0]s01_couplers_to_s01_regslice_AWADDR;\n  wire [1:0]s01_couplers_to_s01_regslice_AWBURST;\n  wire [3:0]s01_couplers_to_s01_regslice_AWCACHE;\n  wire [5:0]s01_couplers_to_s01_regslice_AWID;\n  wire [7:0]s01_couplers_to_s01_regslice_AWLEN;\n  wire [0:0]s01_couplers_to_s01_regslice_AWLOCK;\n  wire [2:0]s01_couplers_to_s01_regslice_AWPROT;\n  wire [3:0]s01_couplers_to_s01_regslice_AWQOS;\n  wire s01_couplers_to_s01_regslice_AWREADY;\n  wire [3:0]s01_couplers_to_s01_regslice_AWREGION;\n  wire [2:0]s01_couplers_to_s01_regslice_AWSIZE;\n  wire s01_couplers_to_s01_regslice_AWVALID;\n  wire [5:0]s01_couplers_to_s01_regslice_BID;\n  wire s01_couplers_to_s01_regslice_BREADY;\n  wire [1:0]s01_couplers_to_s01_regslice_BRESP;\n  wire s01_couplers_to_s01_regslice_BVALID;\n  wire [511:0]s01_couplers_to_s01_regslice_RDATA;\n  wire [5:0]s01_couplers_to_s01_regslice_RID;\n  wire s01_couplers_to_s01_regslice_RLAST;\n  wire s01_couplers_to_s01_regslice_RREADY;\n  wire [1:0]s01_couplers_to_s01_regslice_RRESP;\n  wire s01_couplers_to_s01_regslice_RVALID;\n  wire [511:0]s01_couplers_to_s01_regslice_WDATA;\n  wire s01_couplers_to_s01_regslice_WLAST;\n  wire s01_couplers_to_s01_regslice_WREADY;\n  wire [63:0]s01_couplers_to_s01_regslice_WSTRB;\n  wire s01_couplers_to_s01_regslice_WVALID;\n  wire [63:0]s01_regslice_to_s01_couplers_ARADDR;\n  wire [1:0]s01_regslice_to_s01_couplers_ARBURST;\n  wire [3:0]s01_regslice_to_s01_couplers_ARCACHE;\n  wire [5:0]s01_regslice_to_s01_couplers_ARID;\n  wire [7:0]s01_regslice_to_s01_couplers_ARLEN;\n  wire [0:0]s01_regslice_to_s01_couplers_ARLOCK;\n  wire [2:0]s01_regslice_to_s01_couplers_ARPROT;\n  wire [3:0]s01_regslice_to_s01_couplers_ARQOS;\n  wire s01_regslice_to_s01_couplers_ARREADY;\n  wire [2:0]s01_regslice_to_s01_couplers_ARSIZE;\n  wire s01_regslice_to_s01_couplers_ARVALID;\n  wire [63:0]s01_regslice_to_s01_couplers_AWADDR;\n  wire [1:0]s01_regslice_to_s01_couplers_AWBURST;\n  wire [3:0]s01_regslice_to_s01_couplers_AWCACHE;\n  wire [5:0]s01_regslice_to_s01_couplers_AWID;\n  wire [7:0]s01_regslice_to_s01_couplers_AWLEN;\n  wire [0:0]s01_regslice_to_s01_couplers_AWLOCK;\n  wire [2:0]s01_regslice_to_s01_couplers_AWPROT;\n  wire [3:0]s01_regslice_to_s01_couplers_AWQOS;\n  wire s01_regslice_to_s01_couplers_AWREADY;\n  wire [2:0]s01_regslice_to_s01_couplers_AWSIZE;\n  wire s01_regslice_to_s01_couplers_AWVALID;\n  wire [6:0]s01_regslice_to_s01_couplers_BID;\n  wire s01_regslice_to_s01_couplers_BREADY;\n  wire [1:0]s01_regslice_to_s01_couplers_BRESP;\n  wire s01_regslice_to_s01_couplers_BVALID;\n  wire [511:0]s01_regslice_to_s01_couplers_RDATA;\n  wire [6:0]s01_regslice_to_s01_couplers_RID;\n  wire s01_regslice_to_s01_couplers_RLAST;\n  wire s01_regslice_to_s01_couplers_RREADY;\n  wire [1:0]s01_regslice_to_s01_couplers_RRESP;\n  wire s01_regslice_to_s01_couplers_RVALID;\n  wire [511:0]s01_regslice_to_s01_couplers_WDATA;\n  wire s01_regslice_to_s01_couplers_WLAST;\n  wire s01_regslice_to_s01_couplers_WREADY;\n  wire [63:0]s01_regslice_to_s01_couplers_WSTRB;\n  wire s01_regslice_to_s01_couplers_WVALID;\n\n  assign M_AXI_araddr[63:0] = s01_regslice_to_s01_couplers_ARADDR;\n  assign M_AXI_arburst[1:0] = s01_regslice_to_s01_couplers_ARBURST;\n  assign M_AXI_arcache[3:0] = s01_regslice_to_s01_couplers_ARCACHE;\n  assign M_AXI_arid[5:0] = s01_regslice_to_s01_couplers_ARID;\n  assign M_AXI_arlen[7:0] = s01_regslice_to_s01_couplers_ARLEN;\n  assign M_AXI_arlock[0] = s01_regslice_to_s01_couplers_ARLOCK;\n  assign M_AXI_arprot[2:0] = s01_regslice_to_s01_couplers_ARPROT;\n  assign M_AXI_arqos[3:0] = s01_regslice_to_s01_couplers_ARQOS;\n  assign M_AXI_arsize[2:0] = s01_regslice_to_s01_couplers_ARSIZE;\n  assign M_AXI_arvalid = s01_regslice_to_s01_couplers_ARVALID;\n  assign M_AXI_awaddr[63:0] = s01_regslice_to_s01_couplers_AWADDR;\n  assign M_AXI_awburst[1:0] = s01_regslice_to_s01_couplers_AWBURST;\n  assign M_AXI_awcache[3:0] = s01_regslice_to_s01_couplers_AWCACHE;\n  assign M_AXI_awid[5:0] = s01_regslice_to_s01_couplers_AWID;\n  assign M_AXI_awlen[7:0] = s01_regslice_to_s01_couplers_AWLEN;\n  assign M_AXI_awlock[0] = s01_regslice_to_s01_couplers_AWLOCK;\n  assign M_AXI_awprot[2:0] = s01_regslice_to_s01_couplers_AWPROT;\n  assign M_AXI_awqos[3:0] = s01_regslice_to_s01_couplers_AWQOS;\n  assign M_AXI_awsize[2:0] = s01_regslice_to_s01_couplers_AWSIZE;\n  assign M_AXI_awvalid = s01_regslice_to_s01_couplers_AWVALID;\n  assign M_AXI_bready = s01_regslice_to_s01_couplers_BREADY;\n  assign M_AXI_rready = s01_regslice_to_s01_couplers_RREADY;\n  assign M_AXI_wdata[511:0] = s01_regslice_to_s01_couplers_WDATA;\n  assign M_AXI_wlast = s01_regslice_to_s01_couplers_WLAST;\n  assign M_AXI_wstrb[63:0] = s01_regslice_to_s01_couplers_WSTRB;\n  assign M_AXI_wvalid = s01_regslice_to_s01_couplers_WVALID;\n  assign S_ACLK_1 = S_ACLK;\n  assign S_ARESETN_1 = S_ARESETN;\n  assign S_AXI_arready = s01_couplers_to_s01_regslice_ARREADY;\n  assign S_AXI_awready = s01_couplers_to_s01_regslice_AWREADY;\n  assign S_AXI_bid[5:0] = s01_couplers_to_s01_regslice_BID;\n  assign S_AXI_bresp[1:0] = s01_couplers_to_s01_regslice_BRESP;\n  assign S_AXI_bvalid = s01_couplers_to_s01_regslice_BVALID;\n  assign S_AXI_rdata[511:0] = s01_couplers_to_s01_regslice_RDATA;\n  assign S_AXI_rid[5:0] = s01_couplers_to_s01_regslice_RID;\n  assign S_AXI_rlast = s01_couplers_to_s01_regslice_RLAST;\n  assign S_AXI_rresp[1:0] = s01_couplers_to_s01_regslice_RRESP;\n  assign S_AXI_rvalid = s01_couplers_to_s01_regslice_RVALID;\n  assign S_AXI_wready = s01_couplers_to_s01_regslice_WREADY;\n  assign s01_couplers_to_s01_regslice_ARADDR = S_AXI_araddr[63:0];\n  assign s01_couplers_to_s01_regslice_ARBURST = S_AXI_arburst[1:0];\n  assign s01_couplers_to_s01_regslice_ARCACHE = S_AXI_arcache[3:0];\n  assign s01_couplers_to_s01_regslice_ARID = S_AXI_arid[5:0];\n  assign s01_couplers_to_s01_regslice_ARLEN = S_AXI_arlen[7:0];\n  assign s01_couplers_to_s01_regslice_ARLOCK = S_AXI_arlock[0];\n  assign s01_couplers_to_s01_regslice_ARPROT = S_AXI_arprot[2:0];\n  assign s01_couplers_to_s01_regslice_ARQOS = S_AXI_arqos[3:0];\n  assign s01_couplers_to_s01_regslice_ARREGION = S_AXI_arregion[3:0];\n  assign s01_couplers_to_s01_regslice_ARSIZE = S_AXI_arsize[2:0];\n  assign s01_couplers_to_s01_regslice_ARVALID = S_AXI_arvalid;\n  assign s01_couplers_to_s01_regslice_AWADDR = S_AXI_awaddr[63:0];\n  assign s01_couplers_to_s01_regslice_AWBURST = S_AXI_awburst[1:0];\n  assign s01_couplers_to_s01_regslice_AWCACHE = S_AXI_awcache[3:0];\n  assign s01_couplers_to_s01_regslice_AWID = S_AXI_awid[5:0];\n  assign s01_couplers_to_s01_regslice_AWLEN = S_AXI_awlen[7:0];\n  assign s01_couplers_to_s01_regslice_AWLOCK = S_AXI_awlock[0];\n  assign s01_couplers_to_s01_regslice_AWPROT = S_AXI_awprot[2:0];\n  assign s01_couplers_to_s01_regslice_AWQOS = S_AXI_awqos[3:0];\n  assign s01_couplers_to_s01_regslice_AWREGION = S_AXI_awregion[3:0];\n  assign s01_couplers_to_s01_regslice_AWSIZE = S_AXI_awsize[2:0];\n  assign s01_couplers_to_s01_regslice_AWVALID = S_AXI_awvalid;\n  assign s01_couplers_to_s01_regslice_BREADY = S_AXI_bready;\n  assign s01_couplers_to_s01_regslice_RREADY = S_AXI_rready;\n  assign s01_couplers_to_s01_regslice_WDATA = S_AXI_wdata[511:0];\n  assign s01_couplers_to_s01_regslice_WLAST = S_AXI_wlast;\n  assign s01_couplers_to_s01_regslice_WSTRB = S_AXI_wstrb[63:0];\n  assign s01_couplers_to_s01_regslice_WVALID = S_AXI_wvalid;\n  assign s01_regslice_to_s01_couplers_ARREADY = M_AXI_arready;\n  assign s01_regslice_to_s01_couplers_AWREADY = M_AXI_awready;\n  assign s01_regslice_to_s01_couplers_BID = M_AXI_bid[6:0];\n  assign s01_regslice_to_s01_couplers_BRESP = M_AXI_bresp[1:0];\n  assign s01_regslice_to_s01_couplers_BVALID = M_AXI_bvalid;\n  assign s01_regslice_to_s01_couplers_RDATA = M_AXI_rdata[511:0];\n  assign s01_regslice_to_s01_couplers_RID = M_AXI_rid[6:0];\n  assign s01_regslice_to_s01_couplers_RLAST = M_AXI_rlast;\n  assign s01_regslice_to_s01_couplers_RRESP = M_AXI_rresp[1:0];\n  assign s01_regslice_to_s01_couplers_RVALID = M_AXI_rvalid;\n  assign s01_regslice_to_s01_couplers_WREADY = M_AXI_wready;\n  cl_axi_interconnect_s01_regslice_0 s01_regslice\n       (.aclk(S_ACLK_1),\n        .aresetn(S_ARESETN_1),\n        .m_axi_araddr(s01_regslice_to_s01_couplers_ARADDR),\n        .m_axi_arburst(s01_regslice_to_s01_couplers_ARBURST),\n        .m_axi_arcache(s01_regslice_to_s01_couplers_ARCACHE),\n        .m_axi_arid(s01_regslice_to_s01_couplers_ARID),\n        .m_axi_arlen(s01_regslice_to_s01_couplers_ARLEN),\n        .m_axi_arlock(s01_regslice_to_s01_couplers_ARLOCK),\n        .m_axi_arprot(s01_regslice_to_s01_couplers_ARPROT),\n        .m_axi_arqos(s01_regslice_to_s01_couplers_ARQOS),\n        .m_axi_arready(s01_regslice_to_s01_couplers_ARREADY),\n        .m_axi_arsize(s01_regslice_to_s01_couplers_ARSIZE),\n        .m_axi_arvalid(s01_regslice_to_s01_couplers_ARVALID),\n        .m_axi_awaddr(s01_regslice_to_s01_couplers_AWADDR),\n        .m_axi_awburst(s01_regslice_to_s01_couplers_AWBURST),\n        .m_axi_awcache(s01_regslice_to_s01_couplers_AWCACHE),\n        .m_axi_awid(s01_regslice_to_s01_couplers_AWID),\n        .m_axi_awlen(s01_regslice_to_s01_couplers_AWLEN),\n        .m_axi_awlock(s01_regslice_to_s01_couplers_AWLOCK),\n        .m_axi_awprot(s01_regslice_to_s01_couplers_AWPROT),\n        .m_axi_awqos(s01_regslice_to_s01_couplers_AWQOS),\n        .m_axi_awready(s01_regslice_to_s01_couplers_AWREADY),\n        .m_axi_awsize(s01_regslice_to_s01_couplers_AWSIZE),\n        .m_axi_awvalid(s01_regslice_to_s01_couplers_AWVALID),\n        .m_axi_bid(s01_regslice_to_s01_couplers_BID[5:0]),\n        .m_axi_bready(s01_regslice_to_s01_couplers_BREADY),\n        .m_axi_bresp(s01_regslice_to_s01_couplers_BRESP),\n        .m_axi_bvalid(s01_regslice_to_s01_couplers_BVALID),\n        .m_axi_rdata(s01_regslice_to_s01_couplers_RDATA),\n        .m_axi_rid(s01_regslice_to_s01_couplers_RID[5:0]),\n        .m_axi_rlast(s01_regslice_to_s01_couplers_RLAST),\n        .m_axi_rready(s01_regslice_to_s01_couplers_RREADY),\n        .m_axi_rresp(s01_regslice_to_s01_couplers_RRESP),\n        .m_axi_rvalid(s01_regslice_to_s01_couplers_RVALID),\n        .m_axi_wdata(s01_regslice_to_s01_couplers_WDATA),\n        .m_axi_wlast(s01_regslice_to_s01_couplers_WLAST),\n        .m_axi_wready(s01_regslice_to_s01_couplers_WREADY),\n        .m_axi_wstrb(s01_regslice_to_s01_couplers_WSTRB),\n        .m_axi_wvalid(s01_regslice_to_s01_couplers_WVALID),\n        .s_axi_araddr(s01_couplers_to_s01_regslice_ARADDR),\n        .s_axi_arburst(s01_couplers_to_s01_regslice_ARBURST),\n        .s_axi_arcache(s01_couplers_to_s01_regslice_ARCACHE),\n        .s_axi_arid(s01_couplers_to_s01_regslice_ARID),\n        .s_axi_arlen(s01_couplers_to_s01_regslice_ARLEN),\n        .s_axi_arlock(s01_couplers_to_s01_regslice_ARLOCK),\n        .s_axi_arprot(s01_couplers_to_s01_regslice_ARPROT),\n        .s_axi_arqos(s01_couplers_to_s01_regslice_ARQOS),\n        .s_axi_arready(s01_couplers_to_s01_regslice_ARREADY),\n        .s_axi_arregion(s01_couplers_to_s01_regslice_ARREGION),\n        .s_axi_arsize(s01_couplers_to_s01_regslice_ARSIZE),\n        .s_axi_arvalid(s01_couplers_to_s01_regslice_ARVALID),\n        .s_axi_awaddr(s01_couplers_to_s01_regslice_AWADDR),\n        .s_axi_awburst(s01_couplers_to_s01_regslice_AWBURST),\n        .s_axi_awcache(s01_couplers_to_s01_regslice_AWCACHE),\n        .s_axi_awid(s01_couplers_to_s01_regslice_AWID),\n        .s_axi_awlen(s01_couplers_to_s01_regslice_AWLEN),\n        .s_axi_awlock(s01_couplers_to_s01_regslice_AWLOCK),\n        .s_axi_awprot(s01_couplers_to_s01_regslice_AWPROT),\n        .s_axi_awqos(s01_couplers_to_s01_regslice_AWQOS),\n        .s_axi_awready(s01_couplers_to_s01_regslice_AWREADY),\n        .s_axi_awregion(s01_couplers_to_s01_regslice_AWREGION),\n        .s_axi_awsize(s01_couplers_to_s01_regslice_AWSIZE),\n        .s_axi_awvalid(s01_couplers_to_s01_regslice_AWVALID),\n        .s_axi_bid(s01_couplers_to_s01_regslice_BID),\n        .s_axi_bready(s01_couplers_to_s01_regslice_BREADY),\n        .s_axi_bresp(s01_couplers_to_s01_regslice_BRESP),\n        .s_axi_bvalid(s01_couplers_to_s01_regslice_BVALID),\n        .s_axi_rdata(s01_couplers_to_s01_regslice_RDATA),\n        .s_axi_rid(s01_couplers_to_s01_regslice_RID),\n        .s_axi_rlast(s01_couplers_to_s01_regslice_RLAST),\n        .s_axi_rready(s01_couplers_to_s01_regslice_RREADY),\n        .s_axi_rresp(s01_couplers_to_s01_regslice_RRESP),\n        .s_axi_rvalid(s01_couplers_to_s01_regslice_RVALID),\n        .s_axi_wdata(s01_couplers_to_s01_regslice_WDATA),\n        .s_axi_wlast(s01_couplers_to_s01_regslice_WLAST),\n        .s_axi_wready(s01_couplers_to_s01_regslice_WREADY),\n        .s_axi_wstrb(s01_couplers_to_s01_regslice_WSTRB),\n        .s_axi_wvalid(s01_couplers_to_s01_regslice_WVALID));\nendmodule\n", "num_lines": 5426}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sync_clock_converter\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axic_sync_clock_converter # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_FAMILY     = \"virtex6\",\n  parameter integer C_PAYLOAD_WIDTH = 32,\n  parameter integer C_S_ACLK_RATIO = 1,\n  parameter integer C_M_ACLK_RATIO = 1 ,\n  parameter integer C_MODE = 0  // 0 = light-weight (1-deep); 1 = fully-pipelined (2-deep)\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input wire                    SAMPLE_CYCLE_EARLY,\n  input wire                    SAMPLE_CYCLE,\n  // Slave side\n  input  wire                        S_ACLK,\n  input  wire                        S_ARESETN,\n  input  wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD,\n  input  wire                        S_VALID,\n  output wire                        S_READY,\n\n  // Master side\n  input  wire                        M_ACLK,\n  input  wire                        M_ARESETN,\n  output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD,\n  output wire                        M_VALID,\n  input  wire                        M_READY\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam [1:0] ZERO = 2'b10;\nlocalparam [1:0] ONE  = 2'b11;\nlocalparam [1:0] TWO  = 2'b01;\nlocalparam [1:0] INIT = 2'b00;\nlocalparam integer P_LIGHT_WT = 0;\nlocalparam integer P_FULLY_REG = 1;\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\ngenerate\n  if (C_S_ACLK_RATIO == C_M_ACLK_RATIO) begin : gen_passthru\n    assign M_PAYLOAD = S_PAYLOAD;\n    assign M_VALID   = S_VALID;\n    assign S_READY   = M_READY;      \n  end else begin : gen_sync_clock_converter\n    wire s_sample_cycle;\n    wire s_sample_cycle_early;\n    wire m_sample_cycle;\n    wire m_sample_cycle_early;\n\n    wire slow_aclk;\n    wire slow_areset;\n    wire s_areset_r;\n    wire m_areset_r;\n   \n    reg  s_tready_r = 1'b0; \n    wire s_tready_ns; \n    reg  m_tvalid_r = 1'b0; \n    wire m_tvalid_ns; \n    reg  [C_PAYLOAD_WIDTH-1:0] m_tpayload_r;\n    reg  [C_PAYLOAD_WIDTH-1:0] m_tstorage_r;\n    wire [C_PAYLOAD_WIDTH-1:0] m_tpayload_ns; \n    wire [C_PAYLOAD_WIDTH-1:0] m_tstorage_ns; \n    reg  m_tready_hold = 1'b0;\n    wire m_tready_sample;\n    wire load_tpayload;\n    wire load_tstorage;\n    wire load_tpayload_from_tstorage;\n    reg [1:0] state = INIT;\n    reg [1:0] next_state;\n    \n    reg s_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge S_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        s_aresetn_r <= 1'b0;\n      end else begin\n        s_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign s_areset_r = ~s_aresetn_r;\n\n    reg m_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge M_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        m_aresetn_r <= 1'b0;\n      end else begin\n        m_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign m_areset_r = ~m_aresetn_r;\n\n    if (C_S_ACLK_RATIO > C_M_ACLK_RATIO) begin : gen_slowclk_mi\n      assign slow_aclk = M_ACLK;\n    end else begin : gen_slowclk_si\n      assign slow_aclk = S_ACLK;\n    end\n  \n    assign slow_areset = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? m_areset_r : s_areset_r;\n    assign s_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE_EARLY : 1'b1;\n    assign s_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE : 1'b1;\n    assign m_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE_EARLY;\n    assign m_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE;\n\n    // Output flop for S_READY, value is encoded into state machine.\n    assign s_tready_ns = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? state[1] & (state != INIT) : next_state[1];\n\n    always @(posedge S_ACLK) begin \n      if (s_areset_r) begin\n        s_tready_r <= 1'b0;\n      end\n      else begin\n        s_tready_r <= s_sample_cycle_early ? s_tready_ns : 1'b0;\n      end\n    end\n\n    assign S_READY = s_tready_r;\n\n    // Output flop for M_VALID\n    assign m_tvalid_ns = next_state[0];\n\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tvalid_r <= 1'b0;\n      end\n      else begin\n        m_tvalid_r <= m_sample_cycle ? m_tvalid_ns : m_tvalid_r & ~M_READY;\n      end\n    end\n\n    assign M_VALID = m_tvalid_r;\n\n    // Hold register for M_READY when M_ACLK is fast.\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tready_hold <= 1'b0;\n      end\n      else begin\n        m_tready_hold <= m_sample_cycle ? 1'b0 : m_tready_sample;\n      end\n    end\n\n    assign m_tready_sample = (M_READY ) | m_tready_hold;\n    // Output/storage flops for PAYLOAD\n    assign m_tpayload_ns = ~load_tpayload ? m_tpayload_r :\n                           load_tpayload_from_tstorage ? m_tstorage_r : \n                           S_PAYLOAD;\n\n    assign m_tstorage_ns = C_MODE ? (load_tstorage ? S_PAYLOAD : m_tstorage_r) : 0;\n\n    always @(posedge slow_aclk) begin \n      m_tpayload_r <= m_tpayload_ns;\n      m_tstorage_r <= C_MODE ? m_tstorage_ns : 0;\n    end\n\n    assign M_PAYLOAD = m_tpayload_r;\n\n    // load logic\n    assign load_tstorage = C_MODE && (state != TWO);\n    assign load_tpayload = m_tready_sample || (state == ZERO);\n    assign load_tpayload_from_tstorage = C_MODE && (state == TWO) && m_tready_sample;\n    \n    // State machine\n    always @(posedge slow_aclk) begin \n      state <= next_state;\n    end\n\n    always @* begin \n      if (slow_areset) begin \n        next_state = INIT;\n      end else begin\n        case (state)\n          INIT: begin\n            next_state = ZERO;\n          end\n          // No transaction stored locally\n          ZERO: begin\n            if (S_VALID) begin\n              next_state = C_MODE ? ONE : TWO; // Push from empty\n            end\n            else begin\n              next_state = ZERO;\n            end\n          end\n\n          // One transaction stored locally\n          ONE: begin\n            if (C_MODE == 0) begin\n              next_state = TWO;  // State ONE is inaccessible when C_MODE=0\n            end \n            else if (m_tready_sample & ~S_VALID) begin \n              next_state = ZERO; // Read out one so move to ZERO\n            end\n            else if (~m_tready_sample & S_VALID) begin\n              next_state = TWO;  // Got another one so move to TWO\n            end\n            else begin\n              next_state = ONE;\n            end\n          end\n\n          // Storage registers full\n          TWO: begin \n            if (m_tready_sample) begin\n              next_state = C_MODE ? ONE : ZERO; // Pop from full\n            end\n            else begin\n              next_state = TWO;\n            end\n          end\n        endcase // case (state)\n      end\n    end\n  end // gen_sync_clock_converter\n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sample_cycle_ratio\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axic_sample_cycle_ratio # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_RATIO = 2 // Must be > 0\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    SLOW_ACLK,\n  input  wire                    FAST_ACLK,\n\n  output wire                    SAMPLE_CYCLE_EARLY,\n  output wire                    SAMPLE_CYCLE\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam P_DELAY = C_RATIO > 2 ? C_RATIO-1 : C_RATIO-1; \n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_aclk_div2 = 1'b0;\nreg                posedge_finder_first = 1'b0;\nreg                posedge_finder_second = 1'b0;\nwire               first_edge;\nwire               second_edge;\nwire               any_edge;\nreg  [P_DELAY-1:0] sample_cycle_d = {P_DELAY{1'b0}};\n(* shreg_extract = \"no\" *) reg                sample_cycle_r = 1'b0;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\ngenerate\n  if (C_RATIO == 1) begin : gen_always_sample\n    assign SAMPLE_CYCLE_EARLY = 1'b1;\n    assign SAMPLE_CYCLE = 1'b1;\n  end\n  else begin : gen_sample_cycle\n    genvar i;\n    always @(posedge SLOW_ACLK) begin \n      slow_aclk_div2 <= ~slow_aclk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_aclk_div2 onto faster clock\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_first <= slow_aclk_div2;\n    end\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_second <= ~slow_aclk_div2;\n    end\n\n    assign first_edge = slow_aclk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;\n    assign any_edge = first_edge | second_edge;\n   \n    // delay the posedge alignment by C_RATIO - 1 to set the sample cycle as\n    // the clock one cycle before the posedge.\n    for (i = P_DELAY-1; i > 0; i = i - 1) begin : gen_delay\n      always @(posedge FAST_ACLK) begin\n        if (i == P_DELAY-1) begin\n          sample_cycle_d[i-1] <= any_edge;\n        end else begin\n          sample_cycle_d[i-1] <= sample_cycle_d[i];\n        end\n      end\n    end\n\n    always @(posedge FAST_ACLK) begin \n      sample_cycle_r <= (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    end\n    assign SAMPLE_CYCLE_EARLY = (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    assign SAMPLE_CYCLE = sample_cycle_r;\n  end\nendgenerate\n\nendmodule // axisc_sample_cycle_ratio\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2010 - 2016 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and\n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Clock converter module\n//   Asynchronous clock converter when asynchronous M:N conversion\n//   Bypass when synchronous and ratio between S and M clock is 1:1\n//   Synchronous clock converter (S:M or M:S must be integer ratio)\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_clock_conv\n//     fifo_generator\n//     axic_sync_clock_converter\n//       axic_sample_cycle_ratio\n//\n// PROTECTED NAMES:\n//   Instance names \"asyncfifo_*\" are pattern-matched in core-level UCF.\n//   Signal names \"*_resync\" are pattern-matched in core-level UCF.\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_lite_async #(\n  parameter integer C_DEST_SYNC_FF = 3,\n  parameter integer C_SRC_SYNC_FF  = 3,\n  parameter integer C_WIDTH        = 1\n) (\n  input wire                s_aclk,\n  input wire                m_aclk,\n  input wire                s_aresetn,\n  input wire                m_aresetn,\n  input wire                s_valid,\n  output wire                s_ready,\n  input wire [C_WIDTH-1:0]  s_payld,\n  output wire                m_valid,\n  input wire                m_ready,\n  output wire [C_WIDTH-1:0] m_payld\n);\n\nreg [C_SRC_SYNC_FF:0] s_areset_dly = {C_SRC_SYNC_FF+1{1'b0}};\nreg [C_DEST_SYNC_FF:0] m_areset_dly = {C_DEST_SYNC_FF+1{1'b0}};\nreg                s_ready_i = 1'b0;\nreg                m_valid_i = 1'b0;\nreg   src_send = 1'b0;\nreg   dest_ack = 1'b0;\nwire  src_rcv;\nwire  dest_req;\n\nassign s_ready = s_ready_i;\nassign m_valid = m_valid_i;\n\nlocalparam SRC_IDLE           = 2'b00;\nlocalparam SRC_DRV_SEND       = 2'b01;\nlocalparam SRC_WAIT_RCV_DONE  = 2'b10;\nreg [1:0] src_state = SRC_IDLE;\n\nalways @(posedge s_aclk) begin\n  s_areset_dly <= {C_SRC_SYNC_FF+1{~s_aresetn}} | (s_areset_dly<<1);\n  if (s_areset_dly[C_SRC_SYNC_FF]) begin\n    s_ready_i <= 1'b0;\n    src_send <= 1'b0;\n    src_state <= SRC_IDLE;\n  end else begin\n    case (src_state)\n      SRC_IDLE: begin\n        if (s_valid) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end\n      end\n      SRC_DRV_SEND: begin\n        if (src_rcv) begin\n          s_ready_i <= 1'b1;\n          src_send <= 1'b0;\n          src_state <= SRC_WAIT_RCV_DONE;\n        end\n      end\n      SRC_WAIT_RCV_DONE: begin\n        s_ready_i <= 1'b0;\n        if (s_valid & !src_rcv) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end else if (!src_rcv) begin\n          src_state <= SRC_IDLE;\n        end\n      end\n      default: begin\n        s_ready_i <= 1'b0;\n        src_send <= 1'b0;\n        src_state <= SRC_IDLE;\n      end\n    endcase\n  end\nend\n\nlocalparam DEST_IDLE           = 2'b00;\nlocalparam DEST_DRV_VALID      = 2'b01;\nlocalparam DEST_DRV_ACK        = 2'b10;\nreg [1:0] dest_state = DEST_IDLE;\n\nalways @(posedge m_aclk) begin\n  m_areset_dly <= {C_DEST_SYNC_FF+1{~m_aresetn}} | (m_areset_dly<<1);\n  if (m_areset_dly[C_DEST_SYNC_FF]) begin\n    m_valid_i <= 1'b0;\n    dest_ack <= 1'b0;\n    dest_state <= DEST_IDLE;\n  end else begin\n    case (dest_state)\n      DEST_IDLE: begin\n        if (dest_req) begin\n          dest_state <= DEST_DRV_VALID;\n          m_valid_i <= 1'b1;\n        end else begin\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b0;\n        end\n      end\n      DEST_DRV_VALID: begin\n        if (m_ready & m_valid_i) begin\n          dest_state <= DEST_DRV_ACK;\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b1;\n        end\n      end\n      DEST_DRV_ACK: begin\n        if (!dest_req) begin\n          dest_state <= DEST_IDLE;\n          dest_ack <= 1'b0;\n        end\n      end\n      default: begin\n        m_valid_i <= 1'b0;\n        dest_ack <= 1'b0;\n        dest_state <= DEST_IDLE;\n      end\n    endcase\n  end\nend\n\nxpm_cdc_handshake #(\n  .DEST_SYNC_FF   (C_DEST_SYNC_FF),\n  .SRC_SYNC_FF    (C_SRC_SYNC_FF),\n  .WIDTH          (C_WIDTH)\n) handshake (\n  .src_clk  (s_aclk),\n  .src_in   (s_payld),\n  .src_send (src_send),\n  .src_rcv  (src_rcv),\n  .dest_clk (m_aclk),\n  .dest_out (m_payld),\n  .dest_req (dest_req),\n  .dest_ack (dest_ack)\n);\n\nendmodule\n\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_21_axi_clock_converter #\n  (parameter         C_FAMILY = \"virtex7\",\n   parameter integer C_AXI_ID_WIDTH = 5,                    // Width of all ID signals on SI and MI side.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ADDR_WIDTH = 32,                 // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and\n                                                            // m_axi_araddr.\n                                                            // Range: 32.\n   parameter integer C_AXI_DATA_WIDTH = 32,       // Width of WDATA and RDATA (either side).\n                                                            // Format: Bit32;\n                                                            // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.\n   parameter integer C_S_AXI_ACLK_RATIO = 1,     // Clock frequency ratio of SI w.r.t. MI.\n   parameter integer C_M_AXI_ACLK_RATIO = 1,     // (Slowest of all clock inputs should have ratio=1.)\n                                                            // S:M or M:S must be integer ratio.\n                                                            // Format: Bit32; Range: >='h00000001.\n   parameter integer C_AXI_IS_ACLK_ASYNC = 1,            // Indicates whether S and M clocks are asynchronous.\n                                                            // FUTURE FEATURE\n                                                            // Format: Bit1. Range = 1'b0.\n   parameter integer C_AXI_PROTOCOL = 0,         // Protocol of this SI/MI slot.\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS  = 1,      // 1 = Propagate all USER signals, 0 = Do not propagate.\n   parameter integer C_AXI_AWUSER_WIDTH = 1,                // Width of AWUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ARUSER_WIDTH = 1,                // Width of ARUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_WUSER_WIDTH = 1,                 // Width of WUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_RUSER_WIDTH = 1,                 // Width of RUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_BUSER_WIDTH = 1,                 // Width of BUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,              // Implement AXI write channels\n   parameter integer C_AXI_SUPPORTS_READ = 1,               // Implement AXI read channels\n   parameter integer C_SYNCHRONIZER_STAGE = 3\n  )\n\n  (\n   // Slave Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n   input  wire [4-1:0]                    s_axi_awcache,\n   input  wire [3-1:0]                    s_axi_awprot,\n   input  wire [4-1:0]                    s_axi_awregion,\n   input  wire [4-1:0]                    s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0]   s_axi_awuser,\n   input  wire                            s_axi_awvalid,\n   output wire                            s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n   input  wire                            s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]    s_axi_wuser,\n   input  wire                            s_axi_wvalid,\n   output wire                            s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_bid,\n   output wire [2-1:0]                    s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0]    s_axi_buser,\n   output wire                            s_axi_bvalid,\n   input  wire                            s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n   input  wire [3-1:0]                    s_axi_arsize,\n   input  wire [2-1:0]                    s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n   input  wire [4-1:0]                    s_axi_arcache,\n   input  wire [3-1:0]                    s_axi_arprot,\n   input  wire [4-1:0]                    s_axi_arregion,\n   input  wire [4-1:0]                    s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0]   s_axi_aruser,\n   input  wire                            s_axi_arvalid,\n   output wire                            s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n   output wire [2-1:0]                    s_axi_rresp,\n   output wire                            s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0]    s_axi_ruser,\n   output wire                            s_axi_rvalid,\n   input  wire                            s_axi_rready,\n\n   // Master Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aresetn,\n\n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n   output wire [3-1:0]                    m_axi_awsize,\n   output wire [2-1:0]                    m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n   output wire [4-1:0]                    m_axi_awcache,\n   output wire [3-1:0]                    m_axi_awprot,\n   output wire [4-1:0]                    m_axi_awregion,\n   output wire [4-1:0]                    m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0]   m_axi_awuser,\n   output wire                            m_axi_awvalid,\n   input  wire                            m_axi_awready,\n\n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0]   m_axi_wstrb,\n   output wire                            m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]    m_axi_wuser,\n   output wire                            m_axi_wvalid,\n   input  wire                            m_axi_wready,\n\n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_bid,\n   input  wire [2-1:0]                    m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0]    m_axi_buser,\n   input  wire                            m_axi_bvalid,\n   output wire                            m_axi_bready,\n\n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n   output wire [3-1:0]                    m_axi_arsize,\n   output wire [2-1:0]                    m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n   output wire [4-1:0]                    m_axi_arcache,\n   output wire [3-1:0]                    m_axi_arprot,\n   output wire [4-1:0]                    m_axi_arregion,\n   output wire [4-1:0]                    m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0]   m_axi_aruser,\n   output wire                            m_axi_arvalid,\n   input  wire                            m_axi_arready,\n\n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     m_axi_rdata,\n   input  wire [2-1:0]                    m_axi_rresp,\n   input  wire                            m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0]    m_axi_ruser,\n   input  wire                            m_axi_rvalid,\n   output wire                            m_axi_rready);\n\n  localparam integer P_AXI4 = 0;\n  localparam integer P_AXI3 = 1;\n  localparam integer P_AXILITE = 2;\n  localparam integer P_LIGHT_WT = 0;\n  localparam integer P_FULLY_REG = 1;\n  localparam integer P_LUTRAM_ASYNC = 12;\n\n  // Sample cycle ratio\n  localparam  P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);\n  localparam integer P_ROUNDING_OFFSET = P_SI_LT_MI ? (C_S_AXI_ACLK_RATIO/2) : (C_M_AXI_ACLK_RATIO/2);\n  localparam integer P_ACLK_RATIO = P_SI_LT_MI ?\n    ((C_M_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_S_AXI_ACLK_RATIO) :\n    ((C_S_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_M_AXI_ACLK_RATIO);\n\n  // Write Address Port bit positions\n  localparam integer C_AWUSER_RIGHT   = 0;\n  localparam integer C_AWUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_AWUSER_WIDTH : 0;\n  localparam integer C_AWQOS_RIGHT    = C_AWUSER_RIGHT + C_AWUSER_WIDTH;\n  localparam integer C_AWQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWREGION_RIGHT = C_AWQOS_RIGHT + C_AWQOS_WIDTH;\n  localparam integer C_AWREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_AWPROT_RIGHT   = C_AWREGION_RIGHT + C_AWREGION_WIDTH;\n  localparam integer C_AWPROT_WIDTH     = 3;\n  localparam integer C_AWCACHE_RIGHT  = C_AWPROT_RIGHT + C_AWPROT_WIDTH;\n  localparam integer C_AWCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWLOCK_RIGHT   = C_AWCACHE_RIGHT + C_AWCACHE_WIDTH;\n  localparam integer C_AWLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_AWBURST_RIGHT  = C_AWLOCK_RIGHT + C_AWLOCK_WIDTH;\n  localparam integer C_AWBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_AWSIZE_RIGHT   = C_AWBURST_RIGHT + C_AWBURST_WIDTH;\n  localparam integer C_AWSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_AWLEN_RIGHT    = C_AWSIZE_RIGHT + C_AWSIZE_WIDTH;\n  localparam integer C_AWLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_AWADDR_RIGHT   = C_AWLEN_RIGHT + C_AWLEN_WIDTH;\n  localparam integer C_AWADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_AWID_RIGHT     = C_AWADDR_RIGHT + C_AWADDR_WIDTH;\n  localparam integer C_AWID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AW_WIDTH        = C_AWID_RIGHT + C_AWID_WIDTH;\n  localparam integer C_FIFO_AW_WIDTH   = C_AWUSER_WIDTH+C_AWQOS_WIDTH+C_AWQOS_WIDTH+3+C_AWCACHE_WIDTH+C_AWLOCK_WIDTH+C_AWBURST_WIDTH+C_AWSIZE_WIDTH+C_AWLEN_WIDTH+C_AXI_ADDR_WIDTH+C_AWID_WIDTH;\n\n  // Write Data Port bit positions\n  localparam integer C_WUSER_RIGHT   = 0;\n  localparam integer C_WUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_WUSER_WIDTH : 0;\n  localparam integer C_WLAST_RIGHT   = C_WUSER_RIGHT + C_WUSER_WIDTH;\n  localparam integer C_WLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_WSTRB_RIGHT   = C_WLAST_RIGHT + C_WLAST_WIDTH;\n  localparam integer C_WSTRB_WIDTH     = C_AXI_DATA_WIDTH/8;\n  localparam integer C_WDATA_RIGHT   = C_WSTRB_RIGHT + C_WSTRB_WIDTH;\n  localparam integer C_WDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_WID_RIGHT     = C_WDATA_RIGHT + C_WDATA_WIDTH;\n  localparam integer C_WID_WIDTH       = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_W_WIDTH        = C_WID_RIGHT + C_WID_WIDTH;\n  localparam integer C_FIFO_W_WIDTH   = C_WUSER_WIDTH + C_WLAST_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_DATA_WIDTH + C_WID_WIDTH;\n\n  // Write Response Port bit positions\n  localparam integer C_BUSER_RIGHT   = 0;\n  localparam integer C_BUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_BUSER_WIDTH : 0;\n  localparam integer C_BRESP_RIGHT   = C_BUSER_RIGHT + C_BUSER_WIDTH;\n  localparam integer C_BRESP_WIDTH     = 2;\n  localparam integer C_BID_RIGHT     = C_BRESP_RIGHT + C_BRESP_WIDTH;\n  localparam integer C_BID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_B_WIDTH        = C_BID_RIGHT + C_BID_WIDTH;\n  localparam integer C_FIFO_B_WIDTH    = C_BUSER_WIDTH + 2 + C_BID_WIDTH;\n\n  // Read Address Port bit positions\n  localparam integer C_ARUSER_RIGHT   = 0;\n  localparam integer C_ARUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_ARUSER_WIDTH : 0;\n  localparam integer C_ARQOS_RIGHT    = C_ARUSER_RIGHT + C_ARUSER_WIDTH;\n  localparam integer C_ARQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARREGION_RIGHT = C_ARQOS_RIGHT + C_ARQOS_WIDTH;\n  localparam integer C_ARREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_ARPROT_RIGHT   = C_ARREGION_RIGHT + C_ARREGION_WIDTH;\n  localparam integer C_ARPROT_WIDTH     = 3;\n  localparam integer C_ARCACHE_RIGHT  = C_ARPROT_RIGHT + C_ARPROT_WIDTH;\n  localparam integer C_ARCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARLOCK_RIGHT   = C_ARCACHE_RIGHT + C_ARCACHE_WIDTH;\n  localparam integer C_ARLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_ARBURST_RIGHT  = C_ARLOCK_RIGHT + C_ARLOCK_WIDTH;\n  localparam integer C_ARBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_ARSIZE_RIGHT   = C_ARBURST_RIGHT + C_ARBURST_WIDTH;\n  localparam integer C_ARSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_ARLEN_RIGHT    = C_ARSIZE_RIGHT + C_ARSIZE_WIDTH;\n  localparam integer C_ARLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_ARADDR_RIGHT   = C_ARLEN_RIGHT + C_ARLEN_WIDTH;\n  localparam integer C_ARADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_ARID_RIGHT     = C_ARADDR_RIGHT + C_ARADDR_WIDTH;\n  localparam integer C_ARID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AR_WIDTH        = C_ARID_RIGHT + C_ARID_WIDTH;\n  localparam integer C_FIFO_AR_WIDTH   = C_ARUSER_WIDTH+C_ARQOS_WIDTH+C_ARQOS_WIDTH+3+C_ARCACHE_WIDTH+C_ARLOCK_WIDTH+C_ARBURST_WIDTH+C_ARSIZE_WIDTH+C_ARLEN_WIDTH+C_AXI_ADDR_WIDTH+C_ARID_WIDTH;\n\n  // Read Data Ports bit positions\n  localparam integer C_RUSER_RIGHT   = 0;\n  localparam integer C_RUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_RUSER_WIDTH : 0;\n  localparam integer C_RLAST_RIGHT   = C_RUSER_RIGHT + C_RUSER_WIDTH;\n  localparam integer C_RLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_RRESP_RIGHT   = C_RLAST_RIGHT + C_RLAST_WIDTH;\n  localparam integer C_RRESP_WIDTH     = 2;\n  localparam integer C_RDATA_RIGHT   = C_RRESP_RIGHT + C_RRESP_WIDTH;\n  localparam integer C_RDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_RID_RIGHT     = C_RDATA_RIGHT + C_RDATA_WIDTH;\n  localparam integer C_RID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_R_WIDTH        = C_RID_RIGHT + C_RID_WIDTH;\n  localparam integer C_FIFO_R_WIDTH   = C_RUSER_WIDTH + C_RLAST_WIDTH + 2 + C_AXI_DATA_WIDTH + C_RID_WIDTH;\n\n  generate\n    if ((C_AXI_IS_ACLK_ASYNC == 0) && (P_ACLK_RATIO == 1)) begin : gen_bypass\n      \n      // Write address port\n      assign m_axi_awid     = s_axi_awid;\n      assign m_axi_awaddr   = s_axi_awaddr;\n      assign m_axi_awlen    = s_axi_awlen;\n      assign m_axi_awsize   = s_axi_awsize;\n      assign m_axi_awburst  = s_axi_awburst;\n      assign m_axi_awlock   = s_axi_awlock;\n      assign m_axi_awcache  = s_axi_awcache;\n      assign m_axi_awprot   = s_axi_awprot;\n      assign m_axi_awregion = s_axi_awregion;\n      assign m_axi_awqos    = s_axi_awqos;\n      assign m_axi_awuser   = s_axi_awuser;\n      assign m_axi_awvalid  = s_axi_awvalid;\n      assign s_axi_awready  = m_axi_awready;\n\n      // Write Data Port\n      assign m_axi_wid      = s_axi_wid;\n      assign m_axi_wdata    = s_axi_wdata;\n      assign m_axi_wstrb    = s_axi_wstrb;\n      assign m_axi_wlast    = s_axi_wlast;\n      assign m_axi_wuser    = s_axi_wuser;\n      assign m_axi_wvalid   = s_axi_wvalid;\n      assign s_axi_wready   = m_axi_wready;\n\n      // Write Response Port\n      assign s_axi_bid      = m_axi_bid;\n      assign s_axi_bresp    = m_axi_bresp;\n      assign s_axi_buser    = m_axi_buser;\n      assign s_axi_bvalid   = m_axi_bvalid;\n      assign m_axi_bready   = s_axi_bready;\n\n      // Read Address Port\n      assign m_axi_arid     = s_axi_arid;\n      assign m_axi_araddr   = s_axi_araddr;\n      assign m_axi_arlen    = s_axi_arlen;\n      assign m_axi_arsize   = s_axi_arsize;\n      assign m_axi_arburst  = s_axi_arburst;\n      assign m_axi_arlock   = s_axi_arlock;\n      assign m_axi_arcache  = s_axi_arcache;\n      assign m_axi_arprot   = s_axi_arprot;\n      assign m_axi_arregion = s_axi_arregion;\n      assign m_axi_arqos    = s_axi_arqos;\n      assign m_axi_aruser   = s_axi_aruser;\n      assign m_axi_arvalid  = s_axi_arvalid;\n      assign s_axi_arready  = m_axi_arready;\n\n      // Read Data Port\n      assign s_axi_rid      = m_axi_rid;\n      assign s_axi_rdata    = m_axi_rdata;\n      assign s_axi_rresp    = m_axi_rresp;\n      assign s_axi_rlast    = m_axi_rlast;\n      assign s_axi_ruser    = m_axi_ruser;\n      assign s_axi_rvalid   = m_axi_rvalid;\n      assign m_axi_rready   = s_axi_rready;\n      \n    end else begin : gen_clock_conv\n      \n      wire fast_aclk;\n      wire slow_aclk;\n      wire sample_cycle;\n      wire sample_cycle_early;\n    \n      // Write Address Port FIFO data read and write\n      wire [C_AW_WIDTH-1:0] s_aw_mesg ;\n      wire [C_AW_WIDTH-1:0] m_aw_mesg ;\n    \n      // Write Data Port FIFO data read and write\n      wire [C_W_WIDTH-1:0] s_w_mesg;\n      wire [C_W_WIDTH-1:0] m_w_mesg;\n    \n      // Write Response Port FIFO data read and write\n      wire [C_B_WIDTH-1:0] s_b_mesg;\n      wire [C_B_WIDTH-1:0] m_b_mesg;\n    \n      // Read Address Port FIFO data read and write\n      wire [C_AR_WIDTH-1:0] s_ar_mesg;\n      wire [C_AR_WIDTH-1:0] m_ar_mesg;\n    \n      // Read Data Ports FIFO data read and write\n      wire [C_R_WIDTH-1:0] s_r_mesg;\n      wire [C_R_WIDTH-1:0] m_r_mesg;\n    \n      wire async_conv_reset_n;\n      assign async_conv_reset_n = ~(~s_axi_aresetn | ~m_axi_aresetn);\n      \n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_awlen           ;\n      wire [3-1:0]                       si_cc_awsize          ;\n      wire [2-1:0]                       si_cc_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_awlock          ;\n      wire [4-1:0]                       si_cc_awcache         ;\n      wire [3-1:0]                       si_cc_awprot          ;\n      wire [4-1:0]                       si_cc_awregion        ;\n      wire [4-1:0]                       si_cc_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]      si_cc_awuser          ;\n      wire                               si_cc_awvalid         ;\n      wire                               si_cc_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_wid            ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]      si_cc_wstrb           ;\n      wire                               si_cc_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]       si_cc_wuser           ;\n      wire                               si_cc_wvalid          ;\n      wire                               si_cc_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_bid             ;\n      wire [2-1:0]                       si_cc_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]       si_cc_buser           ;\n      wire                               si_cc_bvalid          ;\n      wire                               si_cc_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_arlen           ;\n      wire [3-1:0]                       si_cc_arsize          ;\n      wire [2-1:0]                       si_cc_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_arlock          ;\n      wire [4-1:0]                       si_cc_arcache         ;\n      wire [3-1:0]                       si_cc_arprot          ;\n      wire [4-1:0]                       si_cc_arregion        ;\n      wire [4-1:0]                       si_cc_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]      si_cc_aruser          ;\n      wire                               si_cc_arvalid         ;\n      wire                               si_cc_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_rdata           ;\n      wire [2-1:0]                       si_cc_rresp           ;\n      wire                               si_cc_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]       si_cc_ruser           ;\n      wire                               si_cc_rvalid          ;\n      wire                               si_cc_rready          ;\n      \n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_awlen           ;\n      wire [3-1:0]                      cc_mi_awsize          ;\n      wire [2-1:0]                      cc_mi_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_awlock          ;\n      wire [4-1:0]                      cc_mi_awcache         ;\n      wire [3-1:0]                      cc_mi_awprot          ;\n      wire [4-1:0]                      cc_mi_awregion        ;\n      wire [4-1:0]                      cc_mi_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]     cc_mi_awuser          ;\n      wire                              cc_mi_awvalid         ;\n      wire                              cc_mi_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_wid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]     cc_mi_wstrb           ;\n      wire                              cc_mi_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]      cc_mi_wuser           ;\n      wire                              cc_mi_wvalid          ;\n      wire                              cc_mi_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_bid             ;\n      wire [2-1:0]                      cc_mi_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]      cc_mi_buser           ;\n      wire                              cc_mi_bvalid          ;\n      wire                              cc_mi_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_arlen           ;\n      wire [3-1:0]                      cc_mi_arsize          ;\n      wire [2-1:0]                      cc_mi_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_arlock          ;\n      wire [4-1:0]                      cc_mi_arcache         ;\n      wire [3-1:0]                      cc_mi_arprot          ;\n      wire [4-1:0]                      cc_mi_arregion        ;\n      wire [4-1:0]                      cc_mi_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]     cc_mi_aruser          ;\n      wire                              cc_mi_arvalid         ;\n      wire                              cc_mi_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_rdata           ;\n      wire [2-1:0]                      cc_mi_rresp           ;\n      wire                              cc_mi_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]      cc_mi_ruser           ;\n      wire                              cc_mi_rvalid          ;\n      wire                              cc_mi_rready          ;\n      \n    // Tie-offs\n      assign si_cc_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awid : 0 ;\n      assign si_cc_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awaddr : 0 ;\n      assign si_cc_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_awlen : {4'b0000, s_axi_awlen[3:0]}) : 0 ;\n      assign si_cc_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize : 0 ;\n      assign si_cc_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst : 0 ;\n      assign si_cc_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_awlock : {1'b0, s_axi_awlock[0]}) : 0 ;\n      assign si_cc_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache : 0 ;\n      assign si_cc_awprot    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awprot : 0 ;\n      assign si_cc_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos : 0 ;\n      assign si_cc_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion : 0 ;\n      assign si_cc_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser : 0 ;\n      assign si_cc_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awvalid : 0 ;\n      assign si_cc_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? s_axi_wid : 0 ;\n      assign si_cc_wdata     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wdata : 0 ;\n      assign si_cc_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wstrb : 0 ;\n      assign si_cc_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast : 1'b0 ;\n      assign si_cc_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser : 0 ;\n      assign si_cc_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wvalid : 0 ;\n      assign si_cc_bready    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_bready : 0 ;\n      assign si_cc_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arid : 0 ;\n      assign si_cc_araddr    = (C_AXI_SUPPORTS_READ ) ? s_axi_araddr : 0 ;\n      assign si_cc_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_arlen : {4'b0000, s_axi_arlen[3:0]}) : 0 ;\n      assign si_cc_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize : 0 ;\n      assign si_cc_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst : 0 ;\n      assign si_cc_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_arlock : {1'b0, s_axi_arlock[0]}) : 0 ;\n      assign si_cc_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache : 0 ;\n      assign si_cc_arprot    = (C_AXI_SUPPORTS_READ ) ? s_axi_arprot : 0 ;\n      assign si_cc_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos : 0 ;\n      assign si_cc_arregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion : 0 ;\n      assign si_cc_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser : 0 ;\n      assign si_cc_arvalid   = (C_AXI_SUPPORTS_READ ) ? s_axi_arvalid : 0 ;\n      assign si_cc_rready    = (C_AXI_SUPPORTS_READ ) ? s_axi_rready : 0 ;                                       \n                                                                                               \n      assign s_axi_awready   = (C_AXI_SUPPORTS_WRITE ) ? si_cc_awready : 0 ;\n      assign s_axi_wready    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_wready : 0 ;\n      assign s_axi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_bid : 0 ;\n      assign s_axi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bresp : 0 ;\n      assign s_axi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_buser : 0 ;\n      assign s_axi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bvalid : 0 ;\n      assign s_axi_arready   = (C_AXI_SUPPORTS_READ ) ? si_cc_arready : 0 ;\n      assign s_axi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rid : 0 ;\n      assign s_axi_rdata     = (C_AXI_SUPPORTS_READ ) ? si_cc_rdata : 0 ;\n      assign s_axi_rresp     = (C_AXI_SUPPORTS_READ ) ? si_cc_rresp : 0 ;\n      assign s_axi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rlast : 0 ;\n      assign s_axi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_ruser : 0 ;\n      assign s_axi_rvalid    = (C_AXI_SUPPORTS_READ ) ? si_cc_rvalid : 0 ;\n\n      assign m_axi_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awid : 0 ;\n      assign m_axi_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awaddr : 0 ;\n      assign m_axi_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_awlen : cc_mi_awlen[3:0]) : 0 ;\n      assign m_axi_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awsize : 0 ;\n      assign m_axi_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awburst : 0 ;\n      assign m_axi_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_awlock : cc_mi_awlock[0]) : 0 ;\n      assign m_axi_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awcache : 0 ;\n      assign m_axi_awprot    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awprot : 0 ;\n      assign m_axi_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_awregion : 0 ;\n      assign m_axi_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awqos : 0 ;\n      assign m_axi_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_awuser : 0 ;\n      assign m_axi_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awvalid : 0 ;\n      assign m_axi_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? cc_mi_wid : 0 ;\n      assign m_axi_wdata     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wdata : 0 ;\n      assign m_axi_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wstrb : 0 ;\n      assign m_axi_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_wlast : 0 ;\n      assign m_axi_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_wuser : 0 ;\n      assign m_axi_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wvalid : 0 ;\n      assign m_axi_bready    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_bready : 0 ;\n      assign m_axi_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arid : 0 ;\n      assign m_axi_araddr    = (C_AXI_SUPPORTS_READ ) ? cc_mi_araddr : 0 ;\n      assign m_axi_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_arlen : cc_mi_arlen[3:0]) : 0 ;\n      assign m_axi_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arsize : 0 ;\n      assign m_axi_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arburst : 0 ;\n      assign m_axi_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_arlock : cc_mi_arlock[0]) : 0 ;\n      assign m_axi_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arcache : 0 ;\n      assign m_axi_arprot    = (C_AXI_SUPPORTS_READ ) ? cc_mi_arprot : 0 ;\n      assign m_axi_arregion  = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_arregion : 0 ;\n      assign m_axi_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arqos : 0 ;\n      assign m_axi_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_aruser : 0 ;\n      assign m_axi_arvalid   = (C_AXI_SUPPORTS_READ ) ? cc_mi_arvalid : 0 ;\n      assign m_axi_rready    = (C_AXI_SUPPORTS_READ ) ? cc_mi_rready : 0 ;\n                                                                                                                                                                                                                                                                                        \n      assign cc_mi_awready   = (C_AXI_SUPPORTS_WRITE ) ? m_axi_awready : 0 ;\n      assign cc_mi_wready    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_wready : 0 ;\n      assign cc_mi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid : 0 ;\n      assign cc_mi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bresp : 0 ;\n      assign cc_mi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser : 0 ;\n      assign cc_mi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bvalid : 0 ;\n      assign cc_mi_arready   = (C_AXI_SUPPORTS_READ ) ? m_axi_arready : 0 ;\n      assign cc_mi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid : 0 ;\n      assign cc_mi_rdata     = (C_AXI_SUPPORTS_READ ) ? m_axi_rdata : 0 ;\n      assign cc_mi_rresp     = (C_AXI_SUPPORTS_READ ) ? m_axi_rresp : 0 ;\n      assign cc_mi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast : 1'b0 ;\n      assign cc_mi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser : 0 ;\n      assign cc_mi_rvalid    = (C_AXI_SUPPORTS_READ ) ? m_axi_rvalid : 0 ;\n      \n      if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL!=P_AXILITE)) begin : gen_async_conv\n        \n        fifo_generator_v13_2_5 #(\n          .C_EN_SAFETY_CKT(0),\n          .C_SELECT_XPM(0),\n          .C_INTERFACE_TYPE(2),\n          .C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ? 3 : 2),\n          .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n          .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n          .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n          .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n          .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n          .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),\n          .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n          .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n          .C_HAS_AXI_ID((C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0),\n          .C_AXI_LEN_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 8 : 4),\n          .C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 1 : 2),\n          .C_HAS_AXI_ARUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_AWUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_BUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_RUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_WUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_DIN_WIDTH_RACH(C_FIFO_AR_WIDTH),\n          .C_DIN_WIDTH_RDCH(C_FIFO_R_WIDTH),\n          .C_DIN_WIDTH_WACH(C_FIFO_AW_WIDTH),\n          .C_DIN_WIDTH_WDCH(C_FIFO_W_WIDTH),\n          .C_DIN_WIDTH_WRCH(C_FIFO_B_WIDTH),\n          .C_HAS_AXI_RD_CHANNEL(C_AXI_SUPPORTS_READ),\n          .C_HAS_AXI_WR_CHANNEL(C_AXI_SUPPORTS_WRITE),\n          .C_RACH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_RDCH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_WACH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WDCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WRCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),\n          .C_COMMON_CLOCK(0),\n          .C_COUNT_TYPE(0),\n          .C_DATA_COUNT_WIDTH(10),\n          .C_DEFAULT_VALUE(\"BlankString\"),\n          .C_DIN_WIDTH(18),\n          .C_DOUT_RST_VAL(\"0\"),\n          .C_DOUT_WIDTH(18),\n          .C_ENABLE_RLOCS(0),\n          .C_FAMILY(C_FAMILY),\n          .C_FULL_FLAGS_RST_VAL(1),\n          .C_HAS_ALMOST_EMPTY(0),\n          .C_HAS_ALMOST_FULL(0),\n          .C_HAS_BACKUP(0),\n          .C_HAS_DATA_COUNT(0),\n          .C_HAS_INT_CLK(0),\n          .C_HAS_MEMINIT_FILE(0),\n          .C_HAS_OVERFLOW(0),\n          .C_HAS_RD_DATA_COUNT(0),\n          .C_HAS_RD_RST(0),\n          .C_HAS_RST(1),\n          .C_HAS_SRST(0),\n          .C_HAS_UNDERFLOW(0),\n          .C_HAS_VALID(0),\n          .C_HAS_WR_ACK(0),\n          .C_HAS_WR_DATA_COUNT(0),\n          .C_HAS_WR_RST(0),\n          .C_IMPLEMENTATION_TYPE(0),\n          .C_INIT_WR_PNTR_VAL(0),\n          .C_MEMORY_TYPE(1),\n          .C_MIF_FILE_NAME(\"BlankString\"),\n          .C_OPTIMIZATION_MODE(0),\n          .C_OVERFLOW_LOW(0),\n          .C_PRELOAD_LATENCY(1),\n          .C_PRELOAD_REGS(0),\n          .C_PRIM_FIFO_TYPE(\"4kx4\"),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),\n          .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),\n          .C_PROG_EMPTY_TYPE(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL(1022),\n          .C_PROG_FULL_THRESH_NEGATE_VAL(1021),\n          .C_PROG_FULL_TYPE(0),\n          .C_RD_DATA_COUNT_WIDTH(10),\n          .C_RD_DEPTH(1024),\n          .C_RD_FREQ(1),\n          .C_RD_PNTR_WIDTH(10),\n          .C_UNDERFLOW_LOW(0),\n          .C_USE_DOUT_RST(1),\n          .C_USE_ECC(0),\n          .C_USE_EMBEDDED_REG(0),\n          .C_USE_FIFO16_FLAGS(0),\n          .C_USE_FWFT_DATA_COUNT(0),\n          .C_VALID_LOW(0),\n          .C_WR_ACK_LOW(0),\n          .C_WR_DATA_COUNT_WIDTH(10),\n          .C_WR_DEPTH(1024),\n          .C_WR_FREQ(1),\n          .C_WR_PNTR_WIDTH(10),\n          .C_WR_RESPONSE_LATENCY(1),\n          .C_MSGON_VAL(1),\n          .C_ENABLE_RST_SYNC(1),\n          .C_ERROR_INJECTION_TYPE(0),\n          .C_HAS_SLAVE_CE(0),\n          .C_HAS_MASTER_CE(0),\n          .C_ADD_NGC_CONSTRAINT(0),\n          .C_USE_COMMON_OVERFLOW(0),\n          .C_USE_COMMON_UNDERFLOW(0),\n          .C_USE_DEFAULT_SETTINGS(0),\n          .C_HAS_AXIS_TDATA(1),\n          .C_HAS_AXIS_TID(0),\n          .C_HAS_AXIS_TDEST(0),\n          .C_HAS_AXIS_TUSER(1),\n          .C_HAS_AXIS_TREADY(1),\n          .C_HAS_AXIS_TLAST(0),\n          .C_HAS_AXIS_TSTRB(0),\n          .C_HAS_AXIS_TKEEP(0),\n          .C_AXIS_TDATA_WIDTH(8),\n          .C_AXIS_TID_WIDTH(1),\n          .C_AXIS_TDEST_WIDTH(1),\n          .C_AXIS_TUSER_WIDTH(4),\n          .C_AXIS_TSTRB_WIDTH(1),\n          .C_AXIS_TKEEP_WIDTH(1),\n          .C_AXIS_TYPE(0),\n          .C_IMPLEMENTATION_TYPE_WACH(12),\n          .C_IMPLEMENTATION_TYPE_WDCH(12),\n          .C_IMPLEMENTATION_TYPE_WRCH(12),\n          .C_IMPLEMENTATION_TYPE_RACH(12),\n          .C_IMPLEMENTATION_TYPE_RDCH(12),\n          .C_IMPLEMENTATION_TYPE_AXIS(11),\n          .C_APPLICATION_TYPE_WACH(0),\n          .C_APPLICATION_TYPE_WDCH(0),\n          .C_APPLICATION_TYPE_WRCH(0),\n          .C_APPLICATION_TYPE_RACH(0),\n          .C_APPLICATION_TYPE_RDCH(0),\n          .C_APPLICATION_TYPE_AXIS(0),\n          .C_USE_ECC_WACH(0),\n          .C_USE_ECC_WDCH(0),\n          .C_USE_ECC_WRCH(0),\n          .C_USE_ECC_RACH(0),\n          .C_USE_ECC_RDCH(0),\n          .C_USE_ECC_AXIS(0),\n          .C_ERROR_INJECTION_TYPE_WACH(0),\n          .C_ERROR_INJECTION_TYPE_WDCH(0),\n          .C_ERROR_INJECTION_TYPE_WRCH(0),\n          .C_ERROR_INJECTION_TYPE_RACH(0),\n          .C_ERROR_INJECTION_TYPE_RDCH(0),\n          .C_ERROR_INJECTION_TYPE_AXIS(0),\n          .C_DIN_WIDTH_AXIS(1),\n          .C_WR_DEPTH_WACH(16),\n          .C_WR_DEPTH_WDCH(16),\n          .C_WR_DEPTH_WRCH(16),\n          .C_WR_DEPTH_RACH(16),\n          .C_WR_DEPTH_RDCH(16),\n          .C_WR_DEPTH_AXIS(1024),\n          .C_WR_PNTR_WIDTH_WACH(4),\n          .C_WR_PNTR_WIDTH_WDCH(4),\n          .C_WR_PNTR_WIDTH_WRCH(4),\n          .C_WR_PNTR_WIDTH_RACH(4),\n          .C_WR_PNTR_WIDTH_RDCH(4),\n          .C_WR_PNTR_WIDTH_AXIS(10),\n          .C_HAS_DATA_COUNTS_WACH(0),\n          .C_HAS_DATA_COUNTS_WDCH(0),\n          .C_HAS_DATA_COUNTS_WRCH(0),\n          .C_HAS_DATA_COUNTS_RACH(0),\n          .C_HAS_DATA_COUNTS_RDCH(0),\n          .C_HAS_DATA_COUNTS_AXIS(0),\n          .C_HAS_PROG_FLAGS_WACH(0),\n          .C_HAS_PROG_FLAGS_WDCH(0),\n          .C_HAS_PROG_FLAGS_WRCH(0),\n          .C_HAS_PROG_FLAGS_RACH(0),\n          .C_HAS_PROG_FLAGS_RDCH(0),\n          .C_HAS_PROG_FLAGS_AXIS(0),\n          .C_PROG_FULL_TYPE_WACH(0),\n          .C_PROG_FULL_TYPE_WDCH(0),\n          .C_PROG_FULL_TYPE_WRCH(0),\n          .C_PROG_FULL_TYPE_RACH(0),\n          .C_PROG_FULL_TYPE_RDCH(0),\n          .C_PROG_FULL_TYPE_AXIS(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),\n          .C_PROG_EMPTY_TYPE_WACH(0),\n          .C_PROG_EMPTY_TYPE_WDCH(0),\n          .C_PROG_EMPTY_TYPE_WRCH(0),\n          .C_PROG_EMPTY_TYPE_RACH(0),\n          .C_PROG_EMPTY_TYPE_RDCH(0),\n          .C_PROG_EMPTY_TYPE_AXIS(0),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1021),\n          .C_REG_SLICE_MODE_WACH(0),\n          .C_REG_SLICE_MODE_WDCH(0),\n          .C_REG_SLICE_MODE_WRCH(0),\n          .C_REG_SLICE_MODE_RACH(0),\n          .C_REG_SLICE_MODE_RDCH(0),\n          .C_REG_SLICE_MODE_AXIS(0)\n          )\n          asyncfifo_axi (\n            .s_aclk(s_axi_aclk),\n            .m_aclk(m_axi_aclk),\n            .s_aresetn(async_conv_reset_n),\n            .s_axi_awid           (si_cc_awid),\n            .s_axi_awaddr         (si_cc_awaddr),\n            .s_axi_awlen          (si_cc_awlen),\n            .s_axi_awsize         (si_cc_awsize),\n            .s_axi_awburst        (si_cc_awburst),\n            .s_axi_awlock         (si_cc_awlock),\n            .s_axi_awcache        (si_cc_awcache),\n            .s_axi_awprot         (si_cc_awprot),\n            .s_axi_awqos          (si_cc_awqos),\n            .s_axi_awregion       (si_cc_awregion),\n            .s_axi_awuser         (si_cc_awuser),\n            .s_axi_awvalid        (si_cc_awvalid),\n            .s_axi_awready        (si_cc_awready),\n            .s_axi_wid            (si_cc_wid),\n            .s_axi_wdata          (si_cc_wdata),\n            .s_axi_wstrb          (si_cc_wstrb),\n            .s_axi_wlast          (si_cc_wlast),\n            .s_axi_wuser          (si_cc_wuser),\n            .s_axi_wvalid         (si_cc_wvalid),\n            .s_axi_wready         (si_cc_wready),\n            .s_axi_bid            (si_cc_bid),\n            .s_axi_bresp          (si_cc_bresp),\n            .s_axi_buser          (si_cc_buser),\n            .s_axi_bvalid         (si_cc_bvalid),\n            .s_axi_bready         (si_cc_bready),\n            .m_axi_awid           (cc_mi_awid),\n            .m_axi_awaddr         (cc_mi_awaddr),\n            .m_axi_awlen          (cc_mi_awlen),\n            .m_axi_awsize         (cc_mi_awsize),\n            .m_axi_awburst        (cc_mi_awburst),\n            .m_axi_awlock         (cc_mi_awlock),\n            .m_axi_awcache        (cc_mi_awcache),\n            .m_axi_awprot         (cc_mi_awprot),\n            .m_axi_awqos          (cc_mi_awqos),\n            .m_axi_awregion       (cc_mi_awregion),\n            .m_axi_awuser         (cc_mi_awuser),\n            .m_axi_awvalid        (cc_mi_awvalid),\n            .m_axi_awready        (cc_mi_awready),\n            .m_axi_wid            (cc_mi_wid),\n            .m_axi_wdata          (cc_mi_wdata),\n            .m_axi_wstrb          (cc_mi_wstrb),\n            .m_axi_wlast          (cc_mi_wlast),\n            .m_axi_wuser          (cc_mi_wuser),\n            .m_axi_wvalid         (cc_mi_wvalid),\n            .m_axi_wready         (cc_mi_wready),\n            .m_axi_bid            (cc_mi_bid),\n            .m_axi_bresp          (cc_mi_bresp),\n            .m_axi_buser          (cc_mi_buser),\n            .m_axi_bvalid         (cc_mi_bvalid),\n            .m_axi_bready         (cc_mi_bready),\n            .s_axi_arid           (si_cc_arid),\n            .s_axi_araddr         (si_cc_araddr),\n            .s_axi_arlen          (si_cc_arlen),\n            .s_axi_arsize         (si_cc_arsize),\n            .s_axi_arburst        (si_cc_arburst),\n            .s_axi_arlock         (si_cc_arlock),\n            .s_axi_arcache        (si_cc_arcache),\n            .s_axi_arprot         (si_cc_arprot),\n            .s_axi_arqos          (si_cc_arqos),\n            .s_axi_arregion       (si_cc_arregion),\n            .s_axi_aruser         (si_cc_aruser),\n            .s_axi_arvalid        (si_cc_arvalid),\n            .s_axi_arready        (si_cc_arready),\n            .s_axi_rid            (si_cc_rid),\n            .s_axi_rdata          (si_cc_rdata),\n            .s_axi_rresp          (si_cc_rresp),\n            .s_axi_rlast          (si_cc_rlast),\n            .s_axi_ruser          (si_cc_ruser),\n            .s_axi_rvalid         (si_cc_rvalid),\n            .s_axi_rready         (si_cc_rready),\n            .m_axi_arid           (cc_mi_arid),\n            .m_axi_araddr         (cc_mi_araddr),\n            .m_axi_arlen          (cc_mi_arlen),\n            .m_axi_arsize         (cc_mi_arsize),\n            .m_axi_arburst        (cc_mi_arburst),\n            .m_axi_arlock         (cc_mi_arlock),\n            .m_axi_arcache        (cc_mi_arcache),\n            .m_axi_arprot         (cc_mi_arprot),\n            .m_axi_arqos          (cc_mi_arqos),\n            .m_axi_arregion       (cc_mi_arregion),\n            .m_axi_aruser         (cc_mi_aruser),\n            .m_axi_arvalid        (cc_mi_arvalid),\n            .m_axi_arready        (cc_mi_arready),\n            .m_axi_rid            (cc_mi_rid),\n            .m_axi_rdata          (cc_mi_rdata),\n            .m_axi_rresp          (cc_mi_rresp),\n            .m_axi_rlast          (cc_mi_rlast),\n            .m_axi_ruser          (cc_mi_ruser),\n            .m_axi_rvalid         (cc_mi_rvalid),\n            .m_axi_rready         (cc_mi_rready),\n            .m_aclk_en(1'b1),\n            .s_aclk_en(1'b1),\n            .almost_empty(),\n            .almost_full(),\n            .axis_data_count(),\n            .axis_dbiterr(),\n            .axis_injectdbiterr(1'b0),\n            .axis_injectsbiterr(1'b0),\n            .axis_overflow(),\n            .axis_prog_empty(),\n            .axis_prog_empty_thresh(10'b0),\n            .axis_prog_full(),\n            .axis_prog_full_thresh(10'b0),\n            .axis_rd_data_count(),\n            .axis_sbiterr(),\n            .axis_underflow(),\n            .axis_wr_data_count(),\n            .axi_ar_data_count(),\n            .axi_ar_dbiterr(),\n            .axi_ar_injectdbiterr(1'b0),\n            .axi_ar_injectsbiterr(1'b0),\n            .axi_ar_overflow(),\n            .axi_ar_prog_empty(),\n            .axi_ar_prog_empty_thresh(4'b0),\n            .axi_ar_prog_full(),\n            .axi_ar_prog_full_thresh(4'b0),\n            .axi_ar_rd_data_count(),\n            .axi_ar_sbiterr(),\n            .axi_ar_underflow(),\n            .axi_ar_wr_data_count(),\n            .axi_aw_data_count(),\n            .axi_aw_dbiterr(),\n            .axi_aw_injectdbiterr(1'b0),\n            .axi_aw_injectsbiterr(1'b0),\n            .axi_aw_overflow(),\n            .axi_aw_prog_empty(),\n            .axi_aw_prog_empty_thresh(4'b0),\n            .axi_aw_prog_full(),\n            .axi_aw_prog_full_thresh(4'b0),\n            .axi_aw_rd_data_count(),\n            .axi_aw_sbiterr(),\n            .axi_aw_underflow(),\n            .axi_aw_wr_data_count(),\n            .axi_b_data_count(),\n            .axi_b_dbiterr(),\n            .axi_b_injectdbiterr(1'b0),\n            .axi_b_injectsbiterr(1'b0),\n            .axi_b_overflow(),\n            .axi_b_prog_empty(),\n            .axi_b_prog_empty_thresh(4'b0),\n            .axi_b_prog_full(),\n            .axi_b_prog_full_thresh(4'b0),\n            .axi_b_rd_data_count(),\n            .axi_b_sbiterr(),\n            .axi_b_underflow(),\n            .axi_b_wr_data_count(),\n            .axi_r_data_count(),\n            .axi_r_dbiterr(),\n            .axi_r_injectdbiterr(1'b0),\n            .axi_r_injectsbiterr(1'b0),\n            .axi_r_overflow(),\n            .axi_r_prog_empty(),\n            .axi_r_prog_empty_thresh(4'b0),\n            .axi_r_prog_full(),\n            .axi_r_prog_full_thresh(4'b0),\n            .axi_r_rd_data_count(),\n            .axi_r_sbiterr(),\n            .axi_r_underflow(),\n            .axi_r_wr_data_count(),\n            .axi_w_data_count(),\n            .axi_w_dbiterr(),\n            .axi_w_injectdbiterr(1'b0),\n            .axi_w_injectsbiterr(1'b0),\n            .axi_w_overflow(),\n            .axi_w_prog_empty(),\n            .axi_w_prog_empty_thresh(4'b0),\n            .axi_w_prog_full(),\n            .axi_w_prog_full_thresh(4'b0),\n            .axi_w_rd_data_count(),\n            .axi_w_sbiterr(),\n            .axi_w_underflow(),\n            .axi_w_wr_data_count(),\n            .backup(1'b0),\n            .backup_marker(1'b0),\n            .clk(1'b0),\n            .data_count(),\n            .dbiterr(),\n            .din(18'b0),\n            .dout(),\n            .empty(),\n            .full(),\n            .injectdbiterr(1'b0),\n            .injectsbiterr(1'b0),\n            .int_clk(1'b0),\n            .m_axis_tdata(),\n            .m_axis_tdest(),\n            .m_axis_tid(),\n            .m_axis_tkeep(),\n            .m_axis_tlast(),\n            .m_axis_tready(1'b0),\n            .m_axis_tstrb(),\n            .m_axis_tuser(),\n            .m_axis_tvalid(),\n            .overflow(),\n            .prog_empty(),\n            .prog_empty_thresh(10'b0),\n            .prog_empty_thresh_assert(10'b0),\n            .prog_empty_thresh_negate(10'b0),\n            .prog_full(),\n            .prog_full_thresh(10'b0),\n            .prog_full_thresh_assert(10'b0),\n            .prog_full_thresh_negate(10'b0),\n            .rd_clk(1'b0),\n            .rd_data_count(),\n            .rd_en(1'b0),\n            .rd_rst(1'b0),\n            .rst(1'b0),\n            .sbiterr(),\n            .srst(1'b0),\n            .s_axis_tdata(8'b0),\n            .s_axis_tdest(1'b0),\n            .s_axis_tid(1'b0),\n            .s_axis_tkeep(1'b0),\n            .s_axis_tlast(1'b0),\n            .s_axis_tready(),\n            .s_axis_tstrb(1'b0),\n            .s_axis_tuser(4'b0),\n            .s_axis_tvalid(1'b0),\n            .underflow(),\n            .valid(),\n            .wr_ack(),\n            .wr_clk(1'b0),\n            .wr_data_count(),\n            .wr_en(1'b0),\n            .wr_rst(1'b0),\n            .wr_rst_busy(),\n            .rd_rst_busy(),\n            .sleep(1'b0)\n        );\n      end else if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_async_lite_conv\n        localparam C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n        `include \"axi_infrastructure_v1_1_0.vh\"\n\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n        axi_infrastructure_v1_1_0_axi2vector #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        axi2vec ( \n          .s_axi_awid      ( si_cc_awid      ) ,\n          .s_axi_awaddr    ( si_cc_awaddr    ) ,\n          .s_axi_awlen     ( s_axi_awlen     ) ,\n          .s_axi_awsize    ( si_cc_awsize    ) ,\n          .s_axi_awburst   ( si_cc_awburst   ) ,\n          .s_axi_awlock    ( s_axi_awlock    ) ,\n          .s_axi_awcache   ( si_cc_awcache   ) ,\n          .s_axi_awprot    ( si_cc_awprot    ) ,\n          .s_axi_awqos     ( si_cc_awqos     ) ,\n          .s_axi_awuser    ( si_cc_awuser    ) ,\n          .s_axi_awregion  ( si_cc_awregion  ) ,\n          .s_axi_wid       ( si_cc_wid       ) ,\n          .s_axi_wdata     ( si_cc_wdata     ) ,\n          .s_axi_wstrb     ( si_cc_wstrb     ) ,\n          .s_axi_wlast     ( si_cc_wlast     ) ,\n          .s_axi_wuser     ( si_cc_wuser     ) ,\n          .s_axi_bid       ( si_cc_bid       ) ,\n          .s_axi_bresp     ( si_cc_bresp     ) ,\n          .s_axi_buser     ( si_cc_buser     ) ,\n          .s_axi_arid      ( si_cc_arid      ) ,\n          .s_axi_araddr    ( si_cc_araddr    ) ,\n          .s_axi_arlen     ( s_axi_arlen     ) ,\n          .s_axi_arsize    ( si_cc_arsize    ) ,\n          .s_axi_arburst   ( si_cc_arburst   ) ,\n          .s_axi_arlock    ( s_axi_arlock    ) ,\n          .s_axi_arcache   ( si_cc_arcache   ) ,\n          .s_axi_arprot    ( si_cc_arprot    ) ,\n          .s_axi_arqos     ( si_cc_arqos     ) ,\n          .s_axi_aruser    ( si_cc_aruser    ) ,\n          .s_axi_arregion  ( si_cc_arregion  ) ,\n          .s_axi_rid       ( si_cc_rid       ) ,\n          .s_axi_rdata     ( si_cc_rdata     ) ,\n          .s_axi_rresp     ( si_cc_rresp     ) ,\n          .s_axi_rlast     ( si_cc_rlast     ) ,\n          .s_axi_ruser     ( si_cc_ruser     ) ,\n          .s_awpayload     ( s_awpayload ) ,\n          .s_wpayload      ( s_wpayload  ) ,\n          .s_bpayload      ( s_bpayload  ) ,\n          .s_arpayload     ( s_arpayload ) ,\n          .s_rpayload      ( s_rpayload  ) \n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_AWPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_aw (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_awvalid),\n          .s_ready  (si_cc_awready),\n          .s_payld  (s_awpayload),\n          .m_valid  (cc_mi_awvalid),\n          .m_ready  (cc_mi_awready),\n          .m_payld  (m_awpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_ARPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_ar (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_arvalid),\n          .s_ready  (si_cc_arready),\n          .s_payld  (s_arpayload),\n          .m_valid  (cc_mi_arvalid),\n          .m_ready  (cc_mi_arready),\n          .m_payld  (m_arpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_WPAYLOAD_WIDTH)\n        ) clock_conv_lite_fwd_w (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_wvalid),\n          .s_ready  (si_cc_wready),\n          .s_payld  (s_wpayload),\n          .m_valid  (cc_mi_wvalid),\n          .m_ready  (cc_mi_wready),\n          .m_payld  (m_wpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_BPAYLOAD_WIDTH)\n        ) clock_conv_lite_resp_b (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_bvalid),\n          .s_ready  (cc_mi_bready),\n          .s_payld  (m_bpayload),\n          .m_valid  (si_cc_bvalid),\n          .m_ready  (si_cc_bready),\n          .m_payld  (s_bpayload)\n        );\n\n        axi_clock_converter_v2_1_21_lite_async #(\n          .C_DEST_SYNC_FF (C_SYNCHRONIZER_STAGE),\n          .C_SRC_SYNC_FF  (C_SYNCHRONIZER_STAGE),\n          .C_WIDTH        (G_AXI_RPAYLOAD_WIDTH)\n        ) clock_conv_lite_resp_r (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_rvalid),\n          .s_ready  (cc_mi_rready),\n          .s_payld  (m_rpayload),\n          .m_valid  (si_cc_rvalid),\n          .m_ready  (si_cc_rready),\n          .m_payld  (s_rpayload)\n        );\n\n        axi_infrastructure_v1_1_0_vector2axi #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        vec2axi ( \n          .m_awpayload    ( m_awpayload    ) ,\n          .m_wpayload     ( m_wpayload     ) ,\n          .m_bpayload     ( m_bpayload     ) ,\n          .m_arpayload    ( m_arpayload    ) ,\n          .m_rpayload     ( m_rpayload     ) ,\n          .m_axi_awid     ( cc_mi_awid     ) ,\n          .m_axi_awaddr   ( cc_mi_awaddr   ) ,\n          .m_axi_awlen    ( cc_mi_awlen    ) ,\n          .m_axi_awsize   ( cc_mi_awsize   ) ,\n          .m_axi_awburst  ( cc_mi_awburst  ) ,\n          .m_axi_awlock   ( cc_mi_awlock   ) ,\n          .m_axi_awcache  ( cc_mi_awcache  ) ,\n          .m_axi_awprot   ( cc_mi_awprot   ) ,\n          .m_axi_awqos    ( cc_mi_awqos    ) ,\n          .m_axi_awuser   ( cc_mi_awuser   ) ,\n          .m_axi_awregion ( cc_mi_awregion ) ,\n          .m_axi_wid      ( cc_mi_wid      ) ,\n          .m_axi_wdata    ( cc_mi_wdata    ) ,\n          .m_axi_wstrb    ( cc_mi_wstrb    ) ,\n          .m_axi_wlast    ( cc_mi_wlast    ) ,\n          .m_axi_wuser    ( cc_mi_wuser    ) ,\n          .m_axi_bid      ( cc_mi_bid      ) ,\n          .m_axi_bresp    ( cc_mi_bresp    ) ,\n          .m_axi_buser    ( cc_mi_buser    ) ,\n          .m_axi_arid     ( cc_mi_arid     ) ,\n          .m_axi_araddr   ( cc_mi_araddr   ) ,\n          .m_axi_arlen    ( cc_mi_arlen    ) ,\n          .m_axi_arsize   ( cc_mi_arsize   ) ,\n          .m_axi_arburst  ( cc_mi_arburst  ) ,\n          .m_axi_arlock   ( cc_mi_arlock   ) ,\n          .m_axi_arcache  ( cc_mi_arcache  ) ,\n          .m_axi_arprot   ( cc_mi_arprot   ) ,\n          .m_axi_arqos    ( cc_mi_arqos    ) ,\n          .m_axi_aruser   ( cc_mi_aruser   ) ,\n          .m_axi_arregion ( cc_mi_arregion ) ,\n          .m_axi_rid      ( cc_mi_rid      ) ,\n          .m_axi_rdata    ( cc_mi_rdata    ) ,\n          .m_axi_rresp    ( cc_mi_rresp    ) ,\n          .m_axi_rlast    ( cc_mi_rlast    ) ,\n          .m_axi_ruser    ( cc_mi_ruser    ) \n        );\n\n      end else begin : gen_sync_conv\n        \n        assign {fast_aclk, slow_aclk} = P_SI_LT_MI ? {m_axi_aclk, s_axi_aclk} : {s_axi_aclk, m_axi_aclk};\n    \n        // Sample cycle used to determine when to assert a signal on a fast clock\n        // to be flopped onto a slow clock.\n        axi_clock_converter_v2_1_21_axic_sample_cycle_ratio #(\n          .C_RATIO ( P_ACLK_RATIO )\n        )\n        axic_sample_cycle_inst (\n          .SLOW_ACLK          ( slow_aclk               ) ,\n          .FAST_ACLK          ( fast_aclk               ) ,\n          .SAMPLE_CYCLE_EARLY ( sample_cycle_early ) ,\n          .SAMPLE_CYCLE       ( sample_cycle       )\n        );\n    \n      ////////////////////////////////////////////////////////////////////////////////\n      // AXI write channels\n      ////////////////////////////////////////////////////////////////////////////////\n        if (C_AXI_SUPPORTS_WRITE) begin : gen_conv_write_ch\n    \n          // Write Address Port\n          assign s_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH]     = si_cc_awaddr   ;\n          assign s_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH]     = si_cc_awprot   ;\n          assign cc_mi_awaddr   = m_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH];\n          assign cc_mi_awprot   = m_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_aw_axi4\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen    ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock[0] ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH] = si_cc_awregion ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awregion = m_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_aw_axi3\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen[3:0] ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock   ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_aw_user\n            assign s_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH]  = si_cc_awuser;\n            assign cc_mi_awuser = m_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AW_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          aw_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_aw_mesg ) ,\n            .S_VALID   ( si_cc_awvalid   ) ,\n            .S_READY   ( si_cc_awready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_aw_mesg ) ,\n            .M_VALID   ( cc_mi_awvalid   ) ,\n            .M_READY   ( cc_mi_awready   )\n          );\n    \n          // Write Data Port\n          assign s_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH] = si_cc_wdata; \n          assign s_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH] = si_cc_wstrb; \n          assign cc_mi_wdata    = m_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH];\n          assign cc_mi_wstrb    = m_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_w_axi4\n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_w_axi3\n            assign s_w_mesg[C_WID_RIGHT+:C_WID_WIDTH]     = si_cc_wid; \n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wid      = m_w_mesg[C_WID_RIGHT+:C_WID_WIDTH];\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_w_user\n            assign s_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH]  = si_cc_wuser;\n            assign cc_mi_wuser = m_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH  ( C_W_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE           ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          w_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_w_mesg ) ,\n            .S_VALID   ( si_cc_wvalid   ) ,\n            .S_READY   ( si_cc_wready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_w_mesg ) ,\n            .M_VALID   ( cc_mi_wvalid   ) ,\n            .M_READY   ( cc_mi_wready   )\n          );\n    \n          // Write Response Port\n          assign m_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH] = cc_mi_bresp;\n          assign si_cc_bresp    = s_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_b_axi\n            assign m_b_mesg[C_BID_RIGHT+:C_BID_WIDTH]     = cc_mi_bid;\n            assign si_cc_bid      = s_b_mesg[C_BID_RIGHT+:C_BID_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_b_user\n            assign m_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH] = cc_mi_buser;\n            assign si_cc_buser  = s_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_B_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          b_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_b_mesg ) ,\n            .S_VALID   ( cc_mi_bvalid   ) ,\n            .S_READY   ( cc_mi_bready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_b_mesg ) ,\n            .M_VALID   ( si_cc_bvalid   ) ,\n            .M_READY   ( si_cc_bready   )\n          );\n    \n        end else begin : gen_tieoff_write_ch\n    \n          // Write address port\n          assign cc_mi_awid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_awaddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_awlen    = {8{1'b0}};\n          assign cc_mi_awsize   = {3{1'b0}};\n          assign cc_mi_awburst  = {2{1'b0}};\n          assign cc_mi_awlock   = {2{1'b0}};\n          assign cc_mi_awcache  = {4{1'b0}};\n          assign cc_mi_awprot   = {3{1'b0}};\n          assign cc_mi_awregion = {4{1'b0}};\n          assign cc_mi_awqos    = {4{1'b0}};\n          assign cc_mi_awuser   = {C_AXI_AWUSER_WIDTH{1'b0}};\n          assign cc_mi_awvalid  = 1'b0;\n          assign si_cc_awready  = 1'b0;\n    \n          // Write data port\n          assign cc_mi_wid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_wdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign cc_mi_wstrb    = {C_AXI_DATA_WIDTH/8{1'b0}};\n          assign cc_mi_wlast    = 1'b0;\n          assign cc_mi_wuser    = {C_AXI_WUSER_WIDTH{1'b0}};\n          assign cc_mi_wvalid   = 1'b0;\n          assign si_cc_wready   = 1'b0;\n    \n          // Write response port\n          assign si_cc_bid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_bresp    = {2{1'b0}};\n          assign si_cc_buser    = {C_AXI_BUSER_WIDTH{1'b0}};\n          assign si_cc_bvalid   = 1'b0;\n          assign cc_mi_bready   = 1'b0;\n        end\n    \n        ////////////////////////////////////////////////////////////////////////////////\n        // AXI read channels\n        ////////////////////////////////////////////////////////////////////////////////\n    \n        if (C_AXI_SUPPORTS_READ) begin : gen_conv_read_ch\n    \n          // Read Address Port\n          assign s_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH]     = si_cc_araddr   ;\n          assign s_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH]     = si_cc_arprot   ;\n          assign cc_mi_araddr   = m_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH];\n          assign cc_mi_arprot   = m_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_ar_axi4\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen    ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock[0] ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH] = si_cc_arregion ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arregion = m_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_ar_axi3\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen[3:0] ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock   ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_ar_user\n            assign s_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH]  = si_cc_aruser;\n            assign cc_mi_aruser = m_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AR_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          ar_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_ar_mesg ) ,\n            .S_VALID   ( si_cc_arvalid   ) ,\n            .S_READY   ( si_cc_arready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN  ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_ar_mesg ) ,\n            .M_VALID   ( cc_mi_arvalid   ) ,\n            .M_READY   ( cc_mi_arready   )\n          );\n    \n          // Read Data Port\n          assign m_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH] = cc_mi_rdata; \n          assign m_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH] = cc_mi_rresp; \n          assign si_cc_rdata    = s_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH];\n          assign si_cc_rresp    = s_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_r_axi\n            assign m_r_mesg[C_RID_RIGHT+:C_RID_WIDTH]     = cc_mi_rid;   \n            assign m_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH] = cc_mi_rlast;\n            assign si_cc_rid      = s_r_mesg[C_RID_RIGHT+:C_RID_WIDTH];\n            assign si_cc_rlast    = s_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_r_user\n            assign m_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH] = cc_mi_ruser;\n            assign si_cc_ruser  = s_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_21_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_R_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          r_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_r_mesg ) ,\n            .S_VALID   ( cc_mi_rvalid   ) ,\n            .S_READY   ( cc_mi_rready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_r_mesg ) ,\n            .M_VALID   ( si_cc_rvalid   ) ,\n            .M_READY   ( si_cc_rready   )\n          );\n    \n        end else begin : gen_tieoff_read_ch\n    \n          // Read Address Port\n          assign cc_mi_arid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_araddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_arlen    = {8{1'b0}};\n          assign cc_mi_arsize   = {3{1'b0}};\n          assign cc_mi_arburst  = {2{1'b0}};\n          assign cc_mi_arlock   = {2{1'b0}};\n          assign cc_mi_arcache  = {4{1'b0}};\n          assign cc_mi_arprot   = {3{1'b0}};\n          assign cc_mi_arregion = {4{1'b0}};\n          assign cc_mi_arqos    = {4{1'b0}};\n          assign cc_mi_aruser   = {C_AXI_ARUSER_WIDTH{1'b0}};\n          assign cc_mi_arvalid  = 1'b0;\n          assign si_cc_arready  = 1'b0;\n    \n          // Read data port\n          assign si_cc_rid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_rdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign si_cc_rresp    = {2{1'b0}};\n          assign si_cc_rlast    = 1'b0;\n          assign si_cc_ruser    = {C_AXI_RUSER_WIDTH{1'b0}};\n          assign si_cc_rvalid   = 1'b0;\n          assign cc_mi_rready   = 1'b0;\n        end\n      end\n    end\n\n  endgenerate\n\nendmodule\n\n\n\n", "num_lines": 2178}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_master #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_SUPPORTS_NARROW = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1,\n   parameter [C_AXI_ADDR_WIDTH-1:0] C_AXI_ADDR = 0,  // Base address\n   parameter integer C_NUM_ADDR = 1,  // Number of address iterations; range 1..2**16 (fixed increment = 32'h10000\n   parameter integer C_NUM_ID = 1,  // Number of ID iterations; range 1..2**C_ID_WIDTH (base = 0; fixed increment = 1)\n   parameter integer C_NUM_LEN = 1,  // Number of LEN iterations; range 1..9 (base = 0; value = 2**i - 1)\n   parameter integer C_NUM_TRANS = 1  // Number of transactions; range >=1 (read and write)\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_awvalid,\n  input  wire                            m_axi_awready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_awburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_awlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_awlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_awid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]    m_axi_awuser = 'b0,\n  /**************** Write Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_wid,\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]      m_axi_wdata,\n  (* dont_touch=\"true\" *) output reg [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb = {(C_AXI_DATA_WIDTH/8){1'b1}},\n  (* dont_touch=\"true\" *) output wire                             m_axi_wvalid,\n  input  wire                            m_axi_wready,\n  (* dont_touch=\"true\" *) output wire                             m_axi_wlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]     m_axi_wuser = 'b0,\n  /**************** Write Response Channel Signals ****************/\n  input  wire [2-1:0]                    m_axi_bresp,\n  input  wire                            m_axi_bvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_bready,\n  input  wire [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]     m_axi_buser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_bid,\n  /**************** Read Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_arvalid,\n  input  wire                            m_axi_arready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_arburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_arlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_arlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_arid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]    m_axi_aruser = 'b0,\n  /**************** Read Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]      m_axi_rdata,\n  input  wire [2-1:0]                    m_axi_rresp,\n  input  wire                            m_axi_rvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_rready,\n  input  wire                            m_axi_rlast,\n  input  wire [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]     m_axi_ruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_rid,\n  /**************** System Signals ****************/\n  input  wire                            aclk,\n  input  wire                            aresetn\n  );\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n  localparam integer  P_NUM_ID_LOG = f_ceil_log2(C_NUM_ID);\n  localparam integer  P_NUM_ADDR_LOG = f_ceil_log2(C_NUM_ADDR);\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL==0 ? 8 : C_AXI_PROTOCOL==1 ? 4 : 1);\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer               P_M_AXI_DATA_BYTES = (C_AXI_DATA_WIDTH / 8);\n  localparam integer               P_M_AXI_DONE_WIDTH = f_ceil_log2(C_NUM_TRANS<2?2:C_NUM_TRANS);\n  localparam integer               P_M_AXI_SIZE = f_ceil_log2(C_AXI_DATA_WIDTH)-3;\n\n  /**************** Internal Wires/Regs - Global ****************/\n   wire                            done;\n    wire                            dummy ;\n  reg                         done_i;\n  reg                         done_sel;\n  wire                         done_cycle;\n  reg                          done_d1 = 1'b0;\n  reg                   areset = 1'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] arcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] rcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [3:0]                    acc_r_i = 4'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] awcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] wcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] bcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [2:0]                    acc_b_i = 3'b0;\n\n  // Register Reset\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    \n    /**************** Internal Wires/Regs - Read Channels ****************/\n    wire                         read_xaction_done_i;\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_arid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_ADDR_WIDTH:0]      araddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  arprot_i = 3'b0;\n    reg [3-1:0]                  arsize_i = 3'b0;\n    reg [2-1:0]                  arburst_i = 2'b0;\n    reg [4-1:0]                  arcache_i = 4'b0;\n    reg [2-1:0]                  arlock_i = 2'b0;\n    reg [P_LEN_WIDTH-1:0]     arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [4-1:0]                  arqos_i = 4'b0;\n    reg [P_ID_WIDTH-1:0]        arid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [2-1:0]                  rresp_i = 2'b00;\n    reg [C_AXI_RUSER_WIDTH:0]   ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      rid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_arvalid_i = 1'b0;\n    reg                        m_axi_rready_i = 1'b0;\n    reg [P_NUM_ADDR_LOG:0]    araddr_cnt = 0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign read_xaction_done_i = m_axi_rvalid && m_axi_rready_i && ((C_AXI_PROTOCOL==2)?1'b1:m_axi_rlast);\n    assign m_axi_arvalid = m_axi_arvalid_i;\n    assign m_axi_rready = m_axi_rready_i;\n    assign m_axi_araddr = m_axi_araddr_i;\n    assign m_axi_arlen = m_axi_arlen_i;\n    always @(posedge aclk) begin\n      m_axi_arprot <= dummy ? arprot_i : 3'b000;\n      m_axi_arsize <= dummy ? arsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_arburst <= dummy ? arburst_i : 2'b01;\n      m_axi_arlock <= dummy ? arlock_i : 1'b0;\n      m_axi_arcache <= dummy ? arcache_i : 4'h3;\n      m_axi_arqos <= dummy  ? arqos_i : 4'h0;\n      m_axi_aruser <= dummy ? aruser_i : 0;\n    end\n  \n    //**********************************************\n    // Read Channel: ARVALID, ARADDR, ARLEN, RREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_arvalid_i <= 1'b0;\n        arcnt_i <= C_NUM_TRANS;\n        m_axi_arlen_i <= 0;\n        m_axi_araddr_i <= C_AXI_ADDR;\n        m_axi_arid_i <= 1;\n        araddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_arready & m_axi_arvalid_i) begin\n          arcnt_i <= arcnt_i - 1;\n          if (araddr_cnt == 1) begin\n            m_axi_araddr_i <= dummy ? araddr_i : C_AXI_ADDR;\n            araddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_araddr_i <= m_axi_araddr_i + 32'h10000;\n            araddr_cnt <= araddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_arlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_arlen_i <= dummy ? arlen_i : 0;\n          end else begin\n            m_axi_arlen_i <= (m_axi_arlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_arid_i == C_NUM_ID)) begin\n            m_axi_arid <= dummy ? arid_i : 0;\n            m_axi_arid_i <= 1;\n          end else begin\n            m_axi_arid <= m_axi_arid_i;\n            m_axi_arid_i <= m_axi_arid_i + 1;\n          end\n          if (arcnt_i == 1) begin\n            m_axi_arvalid_i <= 1'b0;\n          end\n        end else if (arcnt_i != 0) begin\n          m_axi_arvalid_i <= 1'b1;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      araddr_i <= {araddr_i, ~araddr_i[C_AXI_ADDR_WIDTH]};\n      arprot_i <= {arprot_i, ~arprot_i[3-1]};\n      arlen_i <= {arlen_i, ~arlen_i[P_LEN_WIDTH-1]};\n      arsize_i <= {arsize_i, ~arsize_i[3-1]};\n      arburst_i <= {arburst_i, ~arburst_i[2-1]};\n      arlock_i <= {arlock_i, ~arlock_i[2-1]};\n      arcache_i <= {arcache_i, ~arcache_i[4-1]};\n      arqos_i <= {arqos_i, ~arqos_i[4-1]};\n      aruser_i <= {aruser_i, ~aruser_i[C_AXI_ARUSER_WIDTH]};\n      arid_i <= {arid_i, ~arid_i[P_ID_WIDTH-1]};\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        m_axi_rready_i <= 1'b0;\n        rcnt_i <= C_NUM_TRANS;\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        rresp_i <= {2{1'b0}};\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n        rid_i <= {P_ID_WIDTH{1'b0}};\n        acc_r_i <= 4'b0;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_rvalid & m_axi_rready_i) begin\n          m_axi_rready_i <= 1'b0;\n          rdata_i <= m_axi_rdata;\n            acc_r_i[0] <= rdata_i[0];\n          rresp_i <= m_axi_rresp;\n            acc_r_i[1] <= rresp_i[0];\n          ruser_i <= m_axi_ruser;\n            acc_r_i[2] <= ruser_i[0];\n          rid_i <= m_axi_rid;\n            acc_r_i[3] <= rid_i[0];\n          if (m_axi_rlast) begin\n            rcnt_i <= rcnt_i - 1;\n          end\n        end else begin\n          rdata_i <= rdata_i>>1;\n          rresp_i <= rresp_i>>1;\n          ruser_i <= ruser_i>>1;\n          rid_i <= rid_i>>1;\n          acc_r_i <= acc_r_i>>1;\n          if (m_axi_rvalid) begin\n            m_axi_rready_i <= 1'b1;\n          end\n        end\n      end\n    end\n    \n    assign dummy = rdata_i[0];\n    \n    \n\n    /**************** Internal Wires/Regs - Write Channels ****************/\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_awid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [8-1:0]                  xfer_w_i = 8'h00;\n    wire                         write_burst_done_i;\n    reg [C_AXI_ADDR_WIDTH:0]      awaddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  awprot_i = 3'b0;\n    reg [P_LEN_WIDTH-1:0]     awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [3-1:0]                  awsize_i = 3'b0;\n    reg [2-1:0]                  awburst_i = 2'b0;\n    reg [4-1:0]                  awcache_i = 4'b0;\n    reg [2-1:0]                  awlock_i = 2'b0;\n    reg [4-1:0]                  awqos_i = 4'b0;\n    reg [P_ID_WIDTH:0]        awid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_AWUSER_WIDTH:0]    awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg [P_M_AXI_DATA_BYTES-1:0] wstrb_i = {P_M_AXI_DATA_BYTES{1'b1}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]        wid_i = {P_ID_WIDTH{1'b0}};\n    reg [2-1:0]                  bresp_i = 2'b00;\n    reg [C_AXI_BUSER_WIDTH:0]   buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      bid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_awvalid_i = 1'b0;\n    reg                        m_axi_wvalid_i = 1'b0;\n    reg                        m_axi_bready_i = 1'b0;\n    reg                        m_axi_wlast_i = 1'b0;\n    reg                        m_axi_wid_i = {P_ID_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]     wlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [P_NUM_ADDR_LOG:0]    awaddr_cnt = 0;\n  \n    /**************** Assign Write Channel Outputs ****************/\n    assign m_axi_wdata = {wdata_i, done};\n    assign write_burst_done_i = m_axi_wready && m_axi_wvalid_i && ((C_AXI_PROTOCOL==2) || m_axi_wlast_i);\n    assign m_axi_awvalid = m_axi_awvalid_i;\n    assign m_axi_wvalid = m_axi_wvalid_i;\n    assign m_axi_bready = m_axi_bready_i;\n    assign m_axi_wlast = m_axi_wlast_i;\n    assign m_axi_awaddr = m_axi_awaddr_i;\n    assign m_axi_awlen = m_axi_awlen_i;\n    assign m_axi_wid = m_axi_wid_i;\n    always @(posedge aclk) begin\n      m_axi_awprot <= dummy ? awprot_i : 3'b000;\n      m_axi_awsize <= dummy ? awsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_awburst <= dummy ? awburst_i : 2'b01;\n      m_axi_awlock <= dummy ? awlock_i : 1'b0;\n      m_axi_awcache <= dummy ? awcache_i : 4'h3;\n      m_axi_awqos <= dummy ? awqos_i : 4'h0;\n      m_axi_wstrb <= dummy ? wstrb_i : {P_M_AXI_DATA_BYTES{1'b1}};\n      m_axi_awuser <= dummy ?  awuser_i : 0;\n      m_axi_wuser <= dummy ?  wuser_i : 0;\n    end\n  \n    //**********************************************\n    // Write Channel: AWVALID, AWADDR, AWLEN, WVALID, WLAST, BREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_awvalid_i <= 1'b0;\n        m_axi_wvalid_i <= 1'b0;\n        awcnt_i <= C_NUM_TRANS;\n        wcnt_i <= C_NUM_TRANS;\n        xfer_w_i <= 8'h00;\n        m_axi_awlen_i <= 0;\n        m_axi_awaddr_i <= C_AXI_ADDR;\n        m_axi_awid_i <= 1;\n        m_axi_wid_i <= 0;\n        m_axi_wlast_i <= 1'b0;\n        wlen_i <= 0;\n        wid_i <= 0;\n        awaddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_awvalid_i <= 1'b0;\n          awcnt_i <= awcnt_i - 1;\n          if (awaddr_cnt == 1) begin\n            m_axi_awaddr_i <= dummy ? awaddr_i : C_AXI_ADDR;\n            awaddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_awaddr_i <= m_axi_awaddr_i + 32'h10000;\n            awaddr_cnt <= awaddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_awlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_awlen_i <= dummy ? awlen_i : 0;\n          end else begin\n            m_axi_awlen_i <= (m_axi_awlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_awid_i == C_NUM_ID)) begin\n            m_axi_awid <= dummy ? awid_i : 0;\n            m_axi_awid_i <= 1;\n          end else begin\n            m_axi_awid <= m_axi_awid_i;\n            m_axi_awid_i <= m_axi_awid_i + 1;\n          end\n        end else if (~m_axi_wvalid_i) begin\n          if (awcnt_i != 0) begin\n            m_axi_awvalid_i <= 1'b1;\n          end\n        end\n  \n        /**************** Write Data Channel ****************/\n\n        if (m_axi_wready && m_axi_wvalid_i) begin\n          xfer_w_i <= xfer_w_i - 1'b1;\n          if (m_axi_wlast_i) begin\n            m_axi_wvalid_i <= 1'b0;\n            wcnt_i <= wcnt_i - 1'b1;\n          end else begin\n            m_axi_wlast_i <=  (xfer_w_i == 1);\n          end\n        end else if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_wvalid_i <= 1'b1;\n          xfer_w_i <= m_axi_awlen_i;\n          m_axi_wlast_i <= (m_axi_awlen_i==0);\n          m_axi_wid_i <= m_axi_awid_i;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: WDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        wdata_i <= (m_axi_wvalid_i && m_axi_wready) ? {wdata_i[C_AXI_DATA_WIDTH-2 : 0], ~wdata_i[C_AXI_DATA_WIDTH-1]} : wdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      awaddr_i <= {awaddr_i, ~awaddr_i[C_AXI_ADDR_WIDTH]};\n      awprot_i <= {awprot_i[3-2:0], ~awprot_i[3-1]};\n      wstrb_i <= {wstrb_i, ~wstrb_i[C_AXI_DATA_WIDTH/8-1]};\n      awlen_i <= {awlen_i, ~awlen_i[P_LEN_WIDTH-1]};\n      awsize_i <= {awsize_i, ~awsize_i[3-1]};\n      awburst_i <= {awburst_i, ~awburst_i[2-1]};\n      awlock_i <= {awlock_i, ~awlock_i[2-1]};\n      awcache_i <= {awcache_i, ~awcache_i[4-1]};\n      awqos_i <= {awqos_i, ~awqos_i[4-1]};\n      awid_i <= {awid_i, ~awid_i[P_ID_WIDTH-1]};\n      awuser_i <= {awuser_i, ~awuser_i[C_AXI_AWUSER_WIDTH]};\n      wuser_i <= {wuser_i, ~wuser_i[C_AXI_WUSER_WIDTH]};\n    end\n  \n    //**********************************************\n    // Write Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_bready_i <= 1'b0;\n        bcnt_i <= C_NUM_TRANS;\n        bresp_i <= {2{1'b0}};\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n        bid_i <= {P_ID_WIDTH{1'b0}};\n        acc_b_i <= 3'b0;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_bvalid & m_axi_bready_i) begin\n          m_axi_bready_i <= 1'b0;\n          bresp_i <= m_axi_bresp;\n            acc_b_i[0] <= bresp_i[0];\n          buser_i <= m_axi_buser;\n            acc_b_i[1] <= buser_i[0];\n          bid_i <= m_axi_bid;\n            acc_b_i[2] <= bid_i[0];\n          bcnt_i <= bcnt_i - 1;\n        end else begin\n          bresp_i <= bresp_i>>1;\n          buser_i <= buser_i>>1;\n          bid_i <= bid_i>>1;\n          acc_b_i <= acc_b_i>>1;\n          if (m_axi_bvalid) begin\n            m_axi_bready_i <= 1'b1;\n          end\n        end\n      end\n    end\n\n\n  //**********************************************\n  // Assert Done\n  //**********************************************\n  always @(posedge aclk) begin\n    if (~aresetn) begin\n      done_d1 <= 1'b0;\n    end else begin\n      done_d1 <= done_i;\n    end\n  end\n\n  assign done = done_sel ? done_i : done_d1;\n  assign done_cycle = done_i & ~done_d1;\n  \n  always @ * begin\n    if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_readonly_done\n       done_i = rcnt_i==0;\n       done_sel = acc_r_i[0];\n    end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_writeonly_done\n       done_i = bcnt_i==0;\n       done_sel = acc_b_i[0];\n    end else begin : gen_readwrite_done\n       done_i = (rcnt_i==0) && (bcnt_i==0);\n       done_sel = acc_r_i[0] ^ acc_b_i[0];\n    end\n  end\n  \nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n  input  wire [3-1:0]                   s_axi_awprot,\n  input  wire                           s_axi_awvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_awready,\n  input  wire [3-1:0]                   s_axi_awsize,\n  input  wire [2-1:0]                   s_axi_awburst,\n  input  wire [4-1:0]                   s_axi_awcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_awlen,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_awlock,\n  input  wire [4-1:0]                   s_axi_awqos,\n  input  wire [4-1:0]                   s_axi_awregion,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_awid,\n  input  wire [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]   s_axi_awuser,\n  /**************** Write Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n  input  wire                           s_axi_wvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_wready,\n  input  wire                           s_axi_wlast,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_wid,\n  input  wire [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]    s_axi_wuser,\n  /**************** Write Response Channel Signals ****************/\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_bresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_bvalid,\n  input  wire                           s_axi_bready,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]    s_axi_buser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_bid = 'b0,\n  /**************** Read Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n  input  wire [3-1:0]                   s_axi_arprot,\n  input  wire                           s_axi_arvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_arready,\n  input  wire [3-1:0]                   s_axi_arsize,\n  input  wire [2-1:0]                   s_axi_arburst,\n  input  wire [4-1:0]                   s_axi_arcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_arlock,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_arlen,\n  input  wire [4-1:0]                   s_axi_arqos,\n  input  wire [4-1:0]                   s_axi_arregion,\n  input  wire [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]   s_axi_aruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_arid,\n  /**************** Read Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_rresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rvalid,\n  input  wire                           s_axi_rready,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]    s_axi_ruser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_rid = 'b0,\n  /**************** System Signals ****************/\n  input  wire                           aclk,\n  input  wire                           aresetn\n   );\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL == 1) ? 4 : 8;\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer P_S_AXI_DATA_BYTES = 32/8;\n  localparam integer P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n\n  /**************** Internal Wires/Regs - Global ****************/\n  reg                   areset = 1'b0;\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    /**************** Internal Wires/Regs - Read Channels ****************/\n    reg [8-1:0]                   xfer_r_cnt = 8'h00;\n    reg [16-1:0]                  arcnt_i = 16'h0000;\n    wire                          read_xaction_done_i;\n    reg [C_AXI_DATA_WIDTH-1:0]     rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]      arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg                           arvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     araddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   arprot_i = 3'b000;\n    reg [3-1:0]                   arsize_i = 3'b000;\n    reg [2-1:0]                   arburst_i = 2'b00;\n    reg [4-1:0]                   arcache_i = 4'b0000;\n    reg [1-1:0]     arlock_i = 1'b0;\n    reg [4-1:0]                   arqos_i = 4'b0000;\n    reg [4-1:0]                   arregion_i = 4'b0000;\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_RUSER_WIDTH:0]     ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_ar_i = 9'b0;\n    reg                           s_axi_rvalid_i = 1'b0;\n    reg                           s_axi_arready_i = 1'b0;\n    reg                           s_axi_rlast_i = 1'b0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign s_axi_rdata = rdata_i;\n    assign read_xaction_done_i = (s_axi_rready && s_axi_rvalid_i && s_axi_rlast_i);\n    assign s_axi_rvalid = s_axi_rvalid_i;\n    assign s_axi_arready = s_axi_arready_i;\n    assign s_axi_rlast = s_axi_rlast_i;\n    //**********************************************\n    // Read Channel: ARREADY, RVALID, RLAST, RID\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        xfer_r_cnt <= 8'h00;\n        arcnt_i <= 16'h0000;\n        arlen_i <= {P_LEN_WIDTH{1'b0}};\n        s_axi_rlast_i <= 1'b0;\n      end else begin\n        /**************** Read Address Channel ****************/\n        // arready\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_arready_i <= 1'b0;\n          arcnt_i <= arcnt_i + 1'b1;\n        end else if (~s_axi_rvalid_i) begin\n          s_axi_arready_i <= 1'b1;\n        end\n  \n        /**************** Read Data Channel ****************/\n        // rvalid\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_rvalid_i <= 1'b1;\n          s_axi_rid <= s_axi_arid;\n          s_axi_ruser <= ruser_i;\n        end else if(read_xaction_done_i) begin\n          s_axi_rvalid_i <= 1'b0;\n        end\n  \n        // rlast\n        if(s_axi_rready && s_axi_rvalid_i) begin\n          xfer_r_cnt <= xfer_r_cnt - 1;\n          if(xfer_r_cnt == 1) begin\n            s_axi_rlast_i <= 1'b1;\n          end\n        end else if(s_axi_arready_i && s_axi_arvalid) begin\n          xfer_r_cnt <= s_axi_arlen;\n          s_axi_rlast_i <= (s_axi_arlen==0);\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Read Channel: RDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        rdata_i <= (s_axi_rready && s_axi_rvalid_i) ? {rdata_i[C_AXI_DATA_WIDTH-2 : 0], ~rdata_i[C_AXI_DATA_WIDTH-1]} : rdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_rresp <= {2{1'b0}};\n      end else if (~s_axi_rvalid_i) begin\n        s_axi_rresp <= {acc_ar_i[0], 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n      end else begin\n        ruser_i <= (s_axi_arready_i && s_axi_arvalid) ? {ruser_i, ~ruser_i[C_AXI_RUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        araddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        arprot_i <= {3{1'b0}};\n        arsize_i <= {3{1'b0}};\n        arburst_i <= {2{1'b0}};\n        arcache_i <= {4{1'b0}};\n        arlock_i <= {1{1'b0}};\n        arqos_i <= {4{1'b0}};\n        arregion_i <= {4{1'b0}};\n        aruser_i <= {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n        acc_ar_i <= 9'b0;\n      end else if (s_axi_arvalid) begin\n        // Register Inputs\n        araddr_i <= s_axi_araddr;\n          acc_ar_i[0] <= araddr_i[0];\n        arprot_i <= s_axi_arprot;\n          acc_ar_i[1] <= arprot_i[0];\n        arsize_i <= s_axi_arsize;\n          acc_ar_i[2] <= arsize_i[0];\n        arburst_i <= s_axi_arburst;\n          acc_ar_i[3] <= arburst_i[0];\n        arcache_i <= s_axi_arcache;\n          acc_ar_i[4] <= arcache_i[0];\n        arlock_i <= s_axi_arlock;\n          acc_ar_i[5] <= arlock_i[0];\n        arqos_i <= s_axi_arqos;\n          acc_ar_i[6] <= arqos_i[0];\n        arregion_i <= s_axi_arregion;\n          acc_ar_i[7] <= arregion_i[0];\n        aruser_i <= s_axi_aruser;\n          acc_ar_i[8] <= aruser_i[0];\n      end else begin\n        araddr_i <= araddr_i>>1;\n        arprot_i <= arprot_i>>1;\n        arsize_i <= arsize_i>>1;\n        arburst_i <= arburst_i>>1;\n        arcache_i <= arcache_i>>1;\n        arlock_i <= arlock_i>>1;\n        arqos_i <= arqos_i>>1;\n        arregion_i <= arregion_i>>1;\n        aruser_i <= aruser_i>>1;\n        acc_ar_i <= acc_ar_i>>1;\n      end\n    end\n  \n  \n    /**************** Internal Wires/Regs - Write Channels ****************/\n    wire                          write_burst_done_i;\n    reg [16-1:0]                  awcnt_i = 16'h0000;\n    reg                           awvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     awaddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   awprot_i = 3'b000;\n    reg [3-1:0]                   awsize_i = 3'b000;\n    reg [2-1:0]                   awburst_i = 2'b00;\n    reg [4-1:0]                   awcache_i = 4'b0000;\n    reg [P_LEN_WIDTH-1:0]      awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [1-1:0]     awlock_i = 1'b0;\n    reg [4-1:0]                   awqos_i = 4'b0000;\n    reg [4-1:0]                   awregion_i = 4'b0000;\n    reg [C_AXI_AWUSER_WIDTH:0]     awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg                           wvalid_i = 1'b0;\n    reg [C_AXI_DATA_WIDTH-1:0]     wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH/8-1:0]   wstrb_i = {(C_AXI_DATA_WIDTH/8){1'b0}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_BUSER_WIDTH:0]     buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_aw_i = 9'b0;\n    reg [3:0]                     acc_w_i = 4'b0;\n    reg                           s_axi_bvalid_i = 1'b0;\n    reg                           s_axi_awready_i = 1'b0;\n    reg                           s_axi_wready_i = 1'b0;\n    /**************** Assign Write Channel Outputs ****************/\n    assign write_burst_done_i =s_axi_wready_i && s_axi_wvalid && ((C_AXI_PROTOCOL == 2) ? 1'b1 : s_axi_wlast);\n    assign s_axi_bvalid = s_axi_bvalid_i;\n    assign s_axi_awready = s_axi_awready_i;\n    assign s_axi_wready = s_axi_wready_i;\n  \n    //**********************************************\n    // Write Channel: AWREADY, WREADY, BVALID, BID\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awcnt_i <= 16'h0000;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        /**************** Write Address Channel ****************/\n        // awready\n        if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_awready_i <= 1'b0;\n          awcnt_i <= awcnt_i + 1'b1;\n          s_axi_bid <= s_axi_awid;\n          s_axi_buser <= buser_i;\n        end else if(~s_axi_wready_i & ~s_axi_bvalid_i) begin\n          s_axi_awready_i <= 1'b1;\n        end\n  \n        /**************** Write Data Channel ****************/\n        // wready\n        if(write_burst_done_i) begin\n          s_axi_wready_i <= 1'b0;\n        end else if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_wready_i <= 1'b1;\n        end\n  \n        /**************** Write Response Channel ****************/\n        // bvalid\n        if(write_burst_done_i) begin\n          s_axi_bvalid_i <= 1'b1;\n        end else if(s_axi_bready && s_axi_bvalid_i) begin\n          s_axi_bvalid_i <= 1'b0;\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Write Channel: BRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_bresp <= {2{1'b0}};\n      end else if (~s_axi_bvalid_i) begin\n        s_axi_bresp <= {(acc_aw_i[0] ^ acc_w_i[0]), 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: BUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (aresetn) begin\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n      end else begin\n        buser_i <= (s_axi_awready_i && s_axi_awvalid) ? {buser_i, ~buser_i[C_AXI_BUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Write Address Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awaddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        awprot_i <= {3{1'b0}};\n        awsize_i <= {3{1'b0}};\n        awburst_i <= {2{1'b0}};\n        awcache_i <= {4{1'b0}};\n        awlen_i <= {P_LEN_WIDTH{1'b0}};\n        awlock_i <= {1{1'b0}};\n        awqos_i <= {4{1'b0}};\n        awregion_i <= {4{1'b0}};\n        awuser_i <= {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n        acc_aw_i <= 9'b0;\n      end else if (s_axi_awvalid) begin\n        // Register Inputs\n        awaddr_i <= s_axi_awaddr;\n          acc_aw_i[0] <= awaddr_i[0];\n        awprot_i <= s_axi_awprot;\n          acc_aw_i[1] <= awprot_i[0];\n        awsize_i <= s_axi_awsize;\n          acc_aw_i[2] <= awsize_i[0];\n        awburst_i <= s_axi_awburst;\n          acc_aw_i[3] <= awburst_i[0];\n        awcache_i <= s_axi_awcache;\n          acc_aw_i[4] <= awcache_i[0];\n        awlock_i <= s_axi_awlock;\n          acc_aw_i[5] <= awlock_i[0];\n        awqos_i <= s_axi_awqos;\n          acc_aw_i[6] <= awqos_i[0];\n        awregion_i <= s_axi_awregion;\n          acc_aw_i[7] <= awregion_i[0];\n        awuser_i <= s_axi_awuser;\n          acc_aw_i[8] <= awuser_i[0];\n      end else begin\n        awaddr_i <= awaddr_i>>1;\n        awprot_i <= awprot_i>>1;\n        awsize_i <= awsize_i>>1;\n        awburst_i <= awburst_i>>1;\n        awcache_i <= awcache_i>>1;\n        awlock_i <= awlock_i>>1;\n        awqos_i <= awqos_i>>1;\n        awregion_i <= awregion_i>>1;\n        awuser_i <= awuser_i>>1;\n        acc_aw_i <= acc_aw_i>>1;\n      end\n    end\n  \n    //**********************************************\n    // Write Data Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        wstrb_i <= {(C_AXI_DATA_WIDTH/8){1'b0}};\n        wuser_i <= {(C_AXI_WUSER_WIDTH+1){1'b0}};\n        acc_w_i <= 4'b0;\n      end else if (s_axi_wvalid) begin\n        // Register Inputs\n        wdata_i <= s_axi_wdata;\n          acc_w_i[0] <= wdata_i[0];\n        wstrb_i <= s_axi_wstrb;\n          acc_w_i[1] <= wstrb_i[0];\n        wuser_i <= s_axi_wuser;\n          acc_w_i[2] <= wuser_i[0];\n      end else begin\n        wdata_i <= wdata_i>>1;\n        wstrb_i <= wstrb_i>>1;\n        wuser_i <= wuser_i>>1;\n        acc_w_i <= acc_w_i>>1;\n      end\n    end\n  \nendmodule\n\n\n\n//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_22_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \n(* autopipeline_module=\"yes\" *)\nmodule axi_register_slice_v2_1_22_auto_slr #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n    wire                    handshake_pipe;\n    wire                    ready_pipe;\n    wire [C_DATA_WIDTH-1:0] payload_pipe;\n    (* keep=\"true\" *)                                                                reg  s_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  s_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  s_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  s_areset_resp2 = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  m_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  m_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_areset_resp2 = 1'b0;\n    \n  // Global Reset pipelining\n  \n    always @(posedge ACLK) begin\n      s_aclear       <= ~ARESETN;\n      s_areset_fwd   <= ~ARESETN; \n      s_areset_resp  <= s_areset_fwd;  // Auto-pipeline\n      s_areset_resp2 <= s_areset_resp; // Auto-pipeline\n    end\n    \n    always @(posedge ACLK) begin\n      m_aclear       <= ~ARESETN;\n      m_areset_fwd   <= ~ARESETN; \n      m_areset_resp  <= m_areset_fwd;  // Auto-pipeline\n      m_areset_resp2 <= m_areset_resp; // Auto-pipeline\n    end\n    \n  // Source-side submodule\n    \n    axi_register_slice_v2_1_22_auto_src #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_src\n      (\n       .ACLK             (ACLK),    \n       .s_aclear         (s_aclear),\n       .s_areset_resp2   (s_areset_resp2),  \n       .S_VALID          (S_VALID),  \n       .S_READY          (S_READY), \n       .S_PAYLOAD_DATA   (S_PAYLOAD_DATA),\n       .ready_pipe        (ready_pipe), \n       .handshake_pipe    (handshake_pipe),\n       .payload_pipe      (payload_pipe)  \n      );\n    \n  // Destination-side submodule\n    \n    axi_register_slice_v2_1_22_auto_dest #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_dest\n      (\n       .ACLK           (ACLK),    \n       .m_aclear       (m_aclear),\n       .m_areset_resp2 (m_areset_resp2),  \n       .M_READY        (M_READY), \n       .M_VALID        (M_VALID),  \n       .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n       .handshake_pipe  (handshake_pipe),\n       .ready_pipe      (ready_pipe),  \n       .payload_pipe    (payload_pipe)  \n      );\n    \nendmodule  // auto_slr\n\nmodule axi_register_slice_v2_1_22_auto_src #\n  (\n   parameter integer C_DATA_WIDTH = 32\n  )\n  (\n   input  wire ACLK,\n   input  wire s_aclear,\n   input  wire s_areset_resp2,\n   input  wire S_VALID,\n   input  wire ready_pipe,\n   output wire S_READY,\n   output wire handshake_pipe,\n   output wire  [C_DATA_WIDTH-1:0] payload_pipe,\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA\n   );\n    \n   (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  [C_DATA_WIDTH-1:0] payload_pipe_r;\n    (* keep=\"true\" *) reg [2:0] s_aresetn_resp4 = 3'b000;\n    wire s_aresetn_resp3;\n    wire s_aresetn_d;\n    wire s_aresetn_q;\n    wire s_handshake_d;\n    wire s_ready_i;\n    \n    assign S_READY = s_ready_i & s_aresetn_q;\n    assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;\n    assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;\n    assign payload_pipe = payload_pipe_r;\n    \n    always @(posedge ACLK or posedge s_aclear) begin\n      if (s_aclear) begin\n        s_aresetn_resp4 <= 3'b000;\n      end else begin\n        s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      payload_pipe_r <= S_PAYLOAD_DATA;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) s_aresetn_resp3_inst (\n        .Q   (s_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~s_areset_resp2)\n     );\n    \n    // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (s_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_aresetn_d)\n     );\n    \n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (handshake_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_handshake_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (s_ready_i),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (ready_pipe)\n     );\n    \nendmodule  // auto_src\n\nmodule axi_register_slice_v2_1_22_auto_dest #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   input  wire ACLK,\n   input  wire m_aclear,\n   input  wire m_areset_resp2,\n   input  wire M_READY,\n   input  wire handshake_pipe,\n   output wire ready_pipe,\n   output wire M_VALID,\n   input  wire [C_DATA_WIDTH-1:0] payload_pipe,\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n   );\n    \n    (* keep=\"true\" *) reg [2:0] m_aresetn_resp4 = 3'b000;\n    wire m_aresetn_resp3;\n    wire m_aresetn_d;\n    wire m_aresetn_q;\n    wire m_valid_i;\n    wire pop;\n    wire m_ready_d;\n    wire m_handshake_q;\n    reg  [C_DATA_WIDTH-1:0] m_payload_q;\n    \n    assign M_VALID = m_valid_i;\n    assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;\n    assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;\n    assign pop     = M_READY & m_valid_i;\n    \n    always @(posedge ACLK or posedge m_aclear) begin\n      if (m_aclear) begin\n        m_aresetn_resp4 <= 3'b000;\n      end else begin\n        m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      m_payload_q <= payload_pipe;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) m_aresetn_resp3_inst (\n        .Q   (m_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~m_areset_resp2)\n     );\n    \n    // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (m_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_aresetn_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (m_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (handshake_pipe)\n     );\n    \n    (* autopipeline_group=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (ready_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_ready_d)\n     );\n    \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  (5)  \n      )\n      srl_fifo\n      (\n       .aclk    (ACLK),    \n       .areset  (~m_aresetn_q),\n       .aclear  (m_aclear),  \n       .s_mesg  (m_payload_q),  \n       .s_valid (m_handshake_q), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      );\n    \nendmodule  // auto_dest\n\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      reg s_valid_d;\n      reg s_ready_d = 1'b0;\n      reg s_ready_reg = 1'b0;\n      reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_22_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_RESP_MIDDLE2_LATENCY = C_PIPELINES_SLAVE + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_22_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      .ACLK           (ACLK),\n      .ARESETN         (ARESETN),\n      .S_PAYLOAD_DATA (S_PAYLOAD_DATA),\n      .S_VALID        (S_VALID),\n      .S_READY        (S_READY),\n      .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n      .M_VALID        (M_VALID),\n      .M_READY        (M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_reset;\n    wire src_ready;\n    wire dummy_reset;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  ( C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( dummy_reset   ) ,\n        .laguna_s_reset_in  ( src_reset   ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset   ) ,\n        .laguna_m_reset_in  ( src_reset  ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset2   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n      \n  end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] mid_payload;\n    wire mid_handshake;\n    wire mid_ready;\n    wire mid_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n    wire dummy_reset3;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( mid_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( mid_reset    ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset3   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset3   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out (  dummy_reset2  ) ,\n        .laguna_m_reset_in  ( mid_reset   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE2_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( mid_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2   ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset3   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset3    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n   \n  generate\n\n  (* keep=\"true\" *) reg s_reset_dd = 1'b0;\n  (* keep=\"true\" *) reg m_reset_dd = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n  \n  assign laguna_s_reset_out = laguna_s_reset_out_i;\n  assign laguna_m_reset_out = laguna_m_reset_out_i;\n  \n  always @(posedge ACLK) begin\n    laguna_s_reset_in_d <= laguna_s_reset_in;\n    laguna_m_reset_in_d <= laguna_m_reset_in;\n    s_reset_dd <= laguna_s_reset_in_d;\n    m_reset_dd <= laguna_m_reset_in_d;\n    laguna_s_reset_out_i <= C_PIPELINES==0 ? laguna_m_reset_in_d : m_reset_dd;\n    laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;\n  end\n  \n  wire ACLEAR;\n  assign ACLEAR = ~ARESETN;\n  \n  if (1) begin : common\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire laguna_s_handshake_q;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, laguna_m_ready_d}; \n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else if (p==C_PIPELINES+1) begin\n          laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n\n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = handshake_i[C_PIPELINES];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_m_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* keep=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_22_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_m_reset_out = laguna_m_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_m_reset_in_d <= laguna_m_reset_in;\n      aresetn_d <= C_CHANNEL==P_FORWARD ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? areset_dly[15]  : laguna_m_reset_in_d;\n      laguna_m_reset_out_i <= areset_d;  // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n  \n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* keep=\"true\" *)  reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      ready_d <= {ready_d, laguna_m_ready_d}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid_q;\n      assign payload_valid_d = (p==0) ? (S_VALID & s_ready_i) : handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==C_PIPELINES) begin\n          laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else if (p==0) begin\n          payload_data <= S_PAYLOAD_DATA;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n      \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_s_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* keep=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_s_reset_out = laguna_s_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_s_reset_in_d <= laguna_s_reset_in;\n      aresetn_d <= C_CHANNEL==P_RESPONSE ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? laguna_s_reset_in_d : areset_dly[15];\n      laguna_s_reset_out_i <= areset_d;  // For forward channels, reflect laguna_s_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n\n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    wire laguna_s_handshake_q;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      laguna_s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n        \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n        \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)  \n      )\n      srl_fifo_0\n      (\n       .aclk    (ACLK),    \n       .areset  (areset_d),  \n       .aclear  (ACLEAR),\n       .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n       .s_valid (push), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      ); \n  \n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  reg areset_d = 1'b0;\n  reg [3:0] areset_dly = 4'b0;\n  always @(posedge ACLK) begin\n    areset_dly <= {4{~ARESETN}} | (areset_dly<<1);\n    areset_d <= areset_dly[3];\n  end\n  \n  if (1) begin : common\n    reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID & s_ready_i;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* keep=\"true\" *)  reg payload_valid = 1'b0;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          payload_data <= S_PAYLOAD_DATA;\n          payload_valid <= S_VALID & s_ready_i & ~areset_d;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n          payload_valid <= handshake_i[((p>0)?(p-1):0)];\n        end\n      end\n    end\n    \n    if (C_PIPELINES==0) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),\n         .aclear  (1'b0),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire                        aclear,  // Async clear\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    wire [1:0] state;  // State vector register\n    reg  [1:0] next;           // Next state value\n    wire [1:0] next_qual;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    reg  m_valid_d;\n    wire m_valid_q;\n    \n    assign m_valid = m_valid_q;\n    assign next_qual = areset ? K_EMPTY : next;\n    assign m_mesg  = mesg_reg;\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_mvalid_inst (\n        .Q   (m_valid_q),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (m_valid_d)\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state0_inst (\n        .Q   (state[0]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[0])\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state1_inst (\n        .Q   (state[1]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[1])\n     );\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      m_valid_d = m_valid_q & ~areset;\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid & ~areset) begin\n            next = K_HAS1;\n            m_valid_d = 1'b0;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              m_valid_d = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n              m_valid_d = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          m_valid_d = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      (* keep_hierarchy = \"yes\" *) axi_register_slice_v2_1_22_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule  // axic_reg_srl_fifo\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   //   16 -> Auto-pipelining\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_RESERVE_MODE = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n  \n  if (C_RESERVE_MODE==1) begin : gen_reserve_si\n  \n    axi_register_slice_v2_1_22_test_slave #(\n      .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n      .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n      .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n      .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n      .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n      .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n      .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n      .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n      .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .s_axi_awaddr(s_axi_awaddr),\n      .s_axi_awprot(s_axi_awprot),\n      .s_axi_awvalid(s_axi_awvalid),\n      .s_axi_awready(s_axi_awready),\n      .s_axi_awsize(s_axi_awsize),\n      .s_axi_awburst(s_axi_awburst),\n      .s_axi_awcache(s_axi_awcache),\n      .s_axi_awlen(s_axi_awlen),\n      .s_axi_awlock(s_axi_awlock),\n      .s_axi_awqos(s_axi_awqos),\n      .s_axi_awregion(s_axi_awregion),\n      .s_axi_awid(s_axi_awid),\n      .s_axi_awuser(s_axi_awuser),\n      .s_axi_wdata(s_axi_wdata),\n      .s_axi_wstrb(s_axi_wstrb),\n      .s_axi_wvalid(s_axi_wvalid),\n      .s_axi_wready(s_axi_wready),\n      .s_axi_wlast(s_axi_wlast),\n      .s_axi_wid(s_axi_wid),\n      .s_axi_wuser(s_axi_wuser),\n      .s_axi_bresp(s_axi_bresp),\n      .s_axi_bvalid(s_axi_bvalid),\n      .s_axi_bready(s_axi_bready),\n      .s_axi_buser(s_axi_buser),\n      .s_axi_bid(s_axi_bid),\n      .s_axi_araddr(s_axi_araddr),\n      .s_axi_arprot(s_axi_arprot),\n      .s_axi_arvalid(s_axi_arvalid),\n      .s_axi_arready(s_axi_arready),\n      .s_axi_arsize(s_axi_arsize),\n      .s_axi_arburst(s_axi_arburst),\n      .s_axi_arcache(s_axi_arcache),\n      .s_axi_arlock(s_axi_arlock),\n      .s_axi_arlen(s_axi_arlen),\n      .s_axi_arqos(s_axi_arqos),\n      .s_axi_arregion(s_axi_arregion),\n      .s_axi_aruser(s_axi_aruser),\n      .s_axi_arid(s_axi_arid),\n      .s_axi_rdata(s_axi_rdata),\n      .s_axi_rresp(s_axi_rresp),\n      .s_axi_rvalid(s_axi_rvalid),\n      .s_axi_rready(s_axi_rready),\n      .s_axi_rlast(s_axi_rlast),\n      .s_axi_ruser(s_axi_ruser),\n      .s_axi_rid(s_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign m_axi_awid     = 0;\n     assign m_axi_awaddr   = 0;\n     assign m_axi_awlen    = 0;\n     assign m_axi_awsize   = 0;\n     assign m_axi_awburst  = 0;\n     assign m_axi_awlock   = 0;\n     assign m_axi_awcache  = 0;\n     assign m_axi_awprot   = 0;\n     assign m_axi_awregion = 0;\n     assign m_axi_awqos    = 0;\n     assign m_axi_awuser   = 0;\n     assign m_axi_awvalid  = 0;\n     assign m_axi_wid      = 0;\n     assign m_axi_wdata    = 0;\n     assign m_axi_wstrb    = 0;\n     assign m_axi_wlast    = 0;\n     assign m_axi_wuser    = 0;\n     assign m_axi_wvalid   = 0;\n     assign m_axi_bready   = 0;\n     assign m_axi_arid     = 0;\n     assign m_axi_araddr   = 0;\n     assign m_axi_arlen    = 0;\n     assign m_axi_arsize   = 0;\n     assign m_axi_arburst  = 0;\n     assign m_axi_arlock   = 0;\n     assign m_axi_arcache  = 0;\n     assign m_axi_arprot   = 0;\n     assign m_axi_arregion = 0;\n     assign m_axi_arqos    = 0;\n     assign m_axi_aruser   = 0;\n     assign m_axi_arvalid  = 0;\n     assign m_axi_rready   = 0;\n      \n  end else if (C_RESERVE_MODE==2) begin : gen_reserve_mi\n    \n    axi_register_slice_v2_1_22_test_master #(\n    .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n    .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .m_axi_awaddr(m_axi_awaddr),\n      .m_axi_awprot(m_axi_awprot),\n      .m_axi_awvalid(m_axi_awvalid),\n      .m_axi_awready(m_axi_awready),\n      .m_axi_awsize(m_axi_awsize),\n      .m_axi_awburst(m_axi_awburst),\n      .m_axi_awcache(m_axi_awcache),\n      .m_axi_awlen(m_axi_awlen),\n      .m_axi_awlock(m_axi_awlock),\n      .m_axi_awqos(m_axi_awqos),\n      .m_axi_awid(m_axi_awid),\n      .m_axi_awuser(m_axi_awuser),\n      .m_axi_wid(m_axi_wid),\n      .m_axi_wdata(m_axi_wdata),\n      .m_axi_wstrb(m_axi_wstrb),\n      .m_axi_wvalid(m_axi_wvalid),\n      .m_axi_wready(m_axi_wready),\n      .m_axi_wlast(m_axi_wlast),\n      .m_axi_wuser(m_axi_wuser),\n      .m_axi_bresp(m_axi_bresp),\n      .m_axi_bvalid(m_axi_bvalid),\n      .m_axi_bready(m_axi_bready),\n      .m_axi_buser(m_axi_buser),\n      .m_axi_bid(m_axi_bid),\n      .m_axi_araddr(m_axi_araddr),\n      .m_axi_arprot(m_axi_arprot),\n      .m_axi_arvalid(m_axi_arvalid),\n      .m_axi_arready(m_axi_arready),\n      .m_axi_arsize(m_axi_arsize),\n      .m_axi_arburst(m_axi_arburst),\n      .m_axi_arcache(m_axi_arcache),\n      .m_axi_arlen(m_axi_arlen),\n      .m_axi_arlock(m_axi_arlock),\n      .m_axi_arqos(m_axi_arqos),\n      .m_axi_arid(m_axi_arid),\n      .m_axi_aruser(m_axi_aruser),\n      .m_axi_rdata(m_axi_rdata),\n      .m_axi_rresp(m_axi_rresp),\n      .m_axi_rvalid(m_axi_rvalid),\n      .m_axi_rready(m_axi_rready),\n      .m_axi_rlast(m_axi_rlast),\n      .m_axi_ruser(m_axi_ruser),\n      .m_axi_rid(m_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign s_axi_awready = 0;\n     assign s_axi_wready  = 0;\n     assign s_axi_bid     = 0;\n     assign s_axi_bresp   = 0;\n     assign s_axi_buser   = 0;\n     assign s_axi_bvalid  = 0;\n     assign s_axi_arready = 0;\n     assign s_axi_rid     = 0;\n     assign s_axi_rdata   = 0;\n     assign s_axi_rresp   = 0;\n     assign s_axi_rlast   = 0;\n     assign s_axi_ruser   = 0;\n     assign s_axi_rvalid  = 0;\n\n  end else begin : gen_reg_slice  // Any normal reg-slice mode\n\n    axi_infrastructure_v1_1_0_axi2vector #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    axi2vector_0 ( \n      .s_axi_awid      ( s_axi_awid      ) ,\n      .s_axi_awaddr    ( s_axi_awaddr    ) ,\n      .s_axi_awlen     ( s_axi_awlen     ) ,\n      .s_axi_awsize    ( s_axi_awsize    ) ,\n      .s_axi_awburst   ( s_axi_awburst   ) ,\n      .s_axi_awlock    ( s_axi_awlock    ) ,\n      .s_axi_awcache   ( s_axi_awcache   ) ,\n      .s_axi_awprot    ( s_axi_awprot    ) ,\n      .s_axi_awqos     ( s_axi_awqos     ) ,\n      .s_axi_awuser    ( s_axi_awuser    ) ,\n      .s_axi_awregion  ( s_axi_awregion  ) ,\n      .s_axi_wid       ( s_axi_wid       ) ,\n      .s_axi_wdata     ( s_axi_wdata     ) ,\n      .s_axi_wstrb     ( s_axi_wstrb     ) ,\n      .s_axi_wlast     ( s_axi_wlast     ) ,\n      .s_axi_wuser     ( s_axi_wuser     ) ,\n      .s_axi_bid       ( s_axi_bid       ) ,\n      .s_axi_bresp     ( s_axi_bresp     ) ,\n      .s_axi_buser     ( s_axi_buser     ) ,\n      .s_axi_arid      ( s_axi_arid      ) ,\n      .s_axi_araddr    ( s_axi_araddr    ) ,\n      .s_axi_arlen     ( s_axi_arlen     ) ,\n      .s_axi_arsize    ( s_axi_arsize    ) ,\n      .s_axi_arburst   ( s_axi_arburst   ) ,\n      .s_axi_arlock    ( s_axi_arlock    ) ,\n      .s_axi_arcache   ( s_axi_arcache   ) ,\n      .s_axi_arprot    ( s_axi_arprot    ) ,\n      .s_axi_arqos     ( s_axi_arqos     ) ,\n      .s_axi_aruser    ( s_axi_aruser    ) ,\n      .s_axi_arregion  ( s_axi_arregion  ) ,\n      .s_axi_rid       ( s_axi_rid       ) ,\n      .s_axi_rdata     ( s_axi_rdata     ) ,\n      .s_axi_rresp     ( s_axi_rresp     ) ,\n      .s_axi_rlast     ( s_axi_rlast     ) ,\n      .s_axi_ruser     ( s_axi_ruser     ) ,\n      .s_awpayload ( s_awpayload ) ,\n      .s_wpayload  ( s_wpayload  ) ,\n      .s_bpayload  ( s_bpayload  ) ,\n      .s_arpayload ( s_arpayload ) ,\n      .s_rpayload  ( s_rpayload  ) \n    );\n    \n    axi_infrastructure_v1_1_0_vector2axi #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    vector2axi_0 ( \n      .m_awpayload    ( m_awpayload    ) ,\n      .m_wpayload     ( m_wpayload     ) ,\n      .m_bpayload     ( m_bpayload     ) ,\n      .m_arpayload    ( m_arpayload    ) ,\n      .m_rpayload     ( m_rpayload     ) ,\n      .m_axi_awid     ( m_axi_awid     ) ,\n      .m_axi_awaddr   ( m_axi_awaddr   ) ,\n      .m_axi_awlen    ( m_axi_awlen    ) ,\n      .m_axi_awsize   ( m_axi_awsize   ) ,\n      .m_axi_awburst  ( m_axi_awburst  ) ,\n      .m_axi_awlock   ( m_axi_awlock   ) ,\n      .m_axi_awcache  ( m_axi_awcache  ) ,\n      .m_axi_awprot   ( m_axi_awprot   ) ,\n      .m_axi_awqos    ( m_axi_awqos    ) ,\n      .m_axi_awuser   ( m_axi_awuser   ) ,\n      .m_axi_awregion ( m_axi_awregion ) ,\n      .m_axi_wid      ( m_axi_wid      ) ,\n      .m_axi_wdata    ( m_axi_wdata    ) ,\n      .m_axi_wstrb    ( m_axi_wstrb    ) ,\n      .m_axi_wlast    ( m_axi_wlast    ) ,\n      .m_axi_wuser    ( m_axi_wuser    ) ,\n      .m_axi_bid      ( m_axi_bid      ) ,\n      .m_axi_bresp    ( m_axi_bresp    ) ,\n      .m_axi_buser    ( m_axi_buser    ) ,\n      .m_axi_arid     ( m_axi_arid     ) ,\n      .m_axi_araddr   ( m_axi_araddr   ) ,\n      .m_axi_arlen    ( m_axi_arlen    ) ,\n      .m_axi_arsize   ( m_axi_arsize   ) ,\n      .m_axi_arburst  ( m_axi_arburst  ) ,\n      .m_axi_arlock   ( m_axi_arlock   ) ,\n      .m_axi_arcache  ( m_axi_arcache  ) ,\n      .m_axi_arprot   ( m_axi_arprot   ) ,\n      .m_axi_arqos    ( m_axi_arqos    ) ,\n      .m_axi_aruser   ( m_axi_aruser   ) ,\n      .m_axi_arregion ( m_axi_arregion ) ,\n      .m_axi_rid      ( m_axi_rid      ) ,\n      .m_axi_rdata    ( m_axi_rdata    ) ,\n      .m_axi_rresp    ( m_axi_rresp    ) ,\n      .m_axi_rlast    ( m_axi_rlast    ) ,\n      .m_axi_ruser    ( m_axi_ruser    ) \n    );\n    \n  end  // Reserve SI/MI branch\n\n  if ((C_REG_CONFIG_AW <= 9) && (C_RESERVE_MODE==0)) begin : aw\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 15) && (C_RESERVE_MODE==0)) begin : aw15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 16) && (C_RESERVE_MODE==0)) begin : aw16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) \n    )\n    aw_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if ((C_REG_CONFIG_W <= 9) && (C_RESERVE_MODE==0)) begin : w\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 15) && (C_RESERVE_MODE==0)) begin : w15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 16) && (C_RESERVE_MODE==0)) begin : w16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) \n    )\n    w_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if ((C_REG_CONFIG_B <= 9) && (C_RESERVE_MODE==0)) begin : b\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if ((C_REG_CONFIG_B == 15) && (C_RESERVE_MODE==0)) begin : b15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if ((C_REG_CONFIG_B == 16) && (C_RESERVE_MODE==0)) begin : b16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) \n    )\n    b_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if ((C_REG_CONFIG_AR <= 9) && (C_RESERVE_MODE==0)) begin : ar\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 15) && (C_RESERVE_MODE==0)) begin : ar15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 16) && (C_RESERVE_MODE==0)) begin : ar16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) \n    )\n    ar_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if ((C_REG_CONFIG_R <= 9) && (C_RESERVE_MODE==0)) begin : r\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 15) && (C_RESERVE_MODE==0)) begin : r15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 16) && (C_RESERVE_MODE==0)) begin : r16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) \n    )\n    r_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 4844}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2020.2\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\ngeSCzw9gYjFCv0Dn0YxOXxhH+GZFMePCQPK3AjT+zbjt1urPphGbRmSIP212qcXhU3u6qBayOOuP\nzGTUOznyYQ==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nOnCSRn8bnLy+eSxgkIEXKk5zY3JDppSX+6N3lQVX9PeSypgnQ/2z4GTpmoL+rdMoco6U9R4G1u4m\nE0xhKuM4ba9nEk7cLfAxOQqKqsWQrZaIEmzIr1ET+cp4jOMvYA/MsN4jh93kbuKcSDuJ8zN13DFX\nRemIkmekhFjPkyUS5qM=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nMSBAO7tnsBVh2XpVImbQvPkv1Ik+6Bw1D0e9n6H/Bw1mXnRXzm0RzPaEYAIFuluPbWglTrw4pQSr\nJI/DSdCg6087Xmb+Q5zKawFvuZahx4HgmrKxTL15lZwamiIpmu3LGyxaEH/VbYGM9Ky0jp5PyDKU\nJeskyx64XVUPlRklhMjIKCtYITsgROzqjs+d1jIc494zqnDADEz0msJP38WdzHgwLDQ0NamfpodX\nBUqMR71hgPx1Rvdt7HagUbkfyaG3/12LxFvpAblT7W0W6RKBFEFgFrxWRFaDw+jzj4jgl9g+sjY0\ncveJYAA4UpZJwPSDIWehjmS+mOinzlnl8UP7jw==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nUtIiSU3lZ1iUKAuaJuT083jLC5QokBuxbJC/zVsWXf8ozOCIDAvtpSufF02lDCCaNNheB40dXQFS\nI8VBcTtdWzNr2vj/HmW17e10D6T6mqn/8t0HnWx9c3modRuXup0Too1mNTU5gTH+v3utogTO5ztm\nHbJZ/+5ov0tPkaeJufJl5L/RZAfLmRnRYybtx5bbc7XiGyWaVk6KunsaWtX5zJtVnMeUOkg0N8oL\nRBeyFp3tFqTN7ecNUp7zom6BjZ3fR6euRy36u1XviJsqBjcxzASI1k+bn2lDs3oEdXuMHoRvcuWL\nmmMddzjwWr43L7YoB/WBz/Tw7t6iYI5B6imPUA==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VELOCE-RSA\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nAMZ17uwJyVzW4KyzjD/YjCrX2GlLIDwW9HSuEat97pn8ZQ7QpDPhFLNx09klp1fHQ8yb1KlxCqpm\nIjAljp4A5oQHWcBw/s+Xhtpin6GMDGjsmd5KmAD2J5DQmzqPazc0M8vNO+pGpCJogvWarX5XrP6U\n56l9vH5mfyPmbT/09Kw=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-2\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\noAGTk8IFmmwAT5eT+h5xMK7MsqYCJnsMll3rq17njNu6wbVX2TAoOlVC5DzNg9T5ce7gVnuLuFG/\nFgNSnTJx8TlbP73KxlDubmAVofR56G/yHzaJfJ0fwNhrfXm5AFgmFaKFPTKNkrG/qjdNuwUeA8p4\niHoj1zvPx50myVHXSpHLQ8n92DLWgMUX/57aPLbMHmYu/gsD0kHOuQ8Fr2Mi2DxufAvq1gzT0kc+\nlxSntoseL+X1HLSvmKpEkR/sjaz6P9omIzqKlmOhvLeTZVEZcUtukVN1HTrlol+4/pTFDztcz0tZ\nXqYZKVNB/igvn1iP/Fej8fpkaeJOrk1YgJZ6xw==\n\n`pragma protect key_keyowner = \"Real Intent\", key_keyname = \"RI-RSA-KEY-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nHM0OWTHTT9qkiqicwldwQlaXCXhAavOkOLtzdsXybVEqcdGTuInS8Xvu2i7fjfGdnZjc+o4ZayFd\nadCXUGMQZ+7u79Rm71DMtV7WL4PMhXZmItLJgXQmNzajU211AuWse/CyD7Am9ZDJuQcIK0fcqZQI\nXVJU6sMESVWiSWdCuqkcQLSuSoBY7TVLmCDoTF9n7MlYfcxCkkK6d+2Xs/gjaWO59GZ3TbWhAQLc\n9hHL9YUJUTzZ8yPC8tX+DLS/YrniD3lBpquxXGcl1FxHKFTSpMG/6pTH+7Y5u1s29iqS/KYCCOfR\nPqg3ikxxR4ywBL+umX+Ijv+Hqgol6tBnCkWh/g==\n\n`pragma protect key_keyowner = \"Metrics Technologies Inc.\", key_keyname = \"DSim\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nDQuK/YuairmUNmnTZFN/Tbbjjk202ciTMNZWiES7z/c8BYrmlnBses/x7XzAVxFxOTns+S6gcbxv\nlho3MoYQI3b1wxR93ymMpbFY2AAKqfTaYrt9nuBi+J66NUkNb4mO5Ysrmk/FyxUuVMw2JeKhCxVf\n1Lkw2weXEA2RSHrWxd8764IFSbBqKoKUTMuqLxHovRaQHDy/mOdyefGG7/6ywGbKjVTlE8lXVH8E\n8QodSYZ7p8uod81sVFzJL26a9Tqu+u2tOgD/WqMuxrio7zRkYYC5P+/FtxLC4GaIZ6LivaJuTLOF\nbkAMneaa5dlfamLnRyzDXUCJu/DFpJtH5s1eLQ==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2020_08\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nDL1JbuaDxIhP8ir0jAdx6nea42/rMQ2VXG8PZEGqMkgF/yLmK8+UcPNvmkEnUbVxq6WNxCUUYBOO\neroUXvKd3hB7aza+lE1PkczDRQpe4dZWQ8yHCUSbqj/KnUKU7sMHOSk5MiYcbBazdC+B/zdSxJsr\nsUmnOLgp/SqygmZW7/oDYMIYyOExEOrIPD4CH/xXZGlvuNs4OjdmaSus7kQp/iaUxQz03NGaMv3/\nEuIfORb3j+mQPwXwEBQhecy81p8ky3bmOS0LK+CPuz0LF3VVvrDnnXUSBCWa2WW6t7burmoHvgPV\noB2jrvwkS6dNjRJ7CoyGvV0N6d60kiD0LjZg6Q==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 2400)\n`pragma protect data_block\nNayj+Ml813fDniWORR2jtIBWLUnTKLU73quUTC0r5jwck/h8GoDq9XKw8BqI5v1J3nTgkNVm5atb\ncAw/VaO3NkhfBheJQbSR69Nrz/dOO5tggQHH5bhiVgkyJ10J0IJijCkqHTEM7eqAUpRB+C+swn77\n0UbAbjpA6iLxZtySLCkfu1IDmIuJVGQQu5gx5HhJOOS9sbBqYLpKFtMkq0ekmdT8uVsJas5Dn/rL\nFK6cI0u3hF6jx7C6EuRP9bts5JinWmopHabvdIuMWogq/jEOmvK/YWa2F6a22JfPI9md2SGv001Z\nNF3S+OFUqWLkWcQuQiK1EeStnUgfx0DKmP44Rh49vAuwvoCnEGtGPoJcuqCj8kkx2HperJBoPMXF\nbwOXyBsVw8smubJpJUklj/jkYQU7Mhn0+1DDK4kkK06W5VS0PwpcHI/NCpCrtst2FFbkesNH2SsO\n5KIGW+Cfb4QrEDe5XavyjtAdc7Kf/olEw1ZvNmIwyZXSdJcT54GFCi4KQPPRS9kiaadQLPQS/WUP\nwP3P3JdX9YvFC5Sp1yq2sPWuL1eMLRyNl339wIhus+/wM5aQSDi/pHmJmMEl1YLUa+mN6EenORTG\n5MU9xnSDDk5SD4ObbT9KWXjRTWogMOCapY1Tv1MWBzOTNzXGtVtAJBw4cxOHMG+OFF0yGvhE/AiV\nUJBEeJzP8L2Bj71c8RCxIViFz07rXhaFlBxMGxkdgTscOVxJtGiXqO970qc+E+YhnpZrgzpPog3A\nHIxK9BG2bcC2sSeQO+WCrtfMMdvVUNZHntYQpZozeGZF5OTZeeqs2I0PvZblmP7/srlzJ/JzetZ0\nCpTygxJF6W9HlXHv9qS2in1MDX5LvPjFtN0zKGyxUv4X8CFSqcYRW0lPxKh8dQ8KfIf1/+JRuMUW\nCO3I17UAoMQyc5PLA35Nis/x1CGOS2Zq5QgnlIBPpFv5JGoS0wKJ/bIyq0i0w+v4KWN5TrLYWJ84\nsMf45/+/nnmUoNq90k8SrWlnr9pxaqXZeklZOtEGejWc0oYa3+O2lYV0522Cm+XAuCiLIx1oRyxa\n+u6HnsKXvR9DGb1osgt9gANalMh//k8N88W7tvMLcXwdkFi3uvBg/oZZeRm+o8p5swkqfDh2gQuZ\nGJ1QE8KWN8hTZ9fEsScunk4GbuTk3dg05a1sMGm1gkRzTfiEVCzyn5Hi3pFpbikjAO7g/FLU6yiZ\npKzI2Crm4XPWRCfhwxycS8r2s63JspfJUZBW7tfCcbmQHYqHgxL3ZiEIV4N4tCF6rLQe8eu8xVI4\n/ReaCvAsFB9k7r6h7vh2b/kor3j4v+vAAZs3NBd5vlKFfHc3a2phzTdGn9/IodWpqPp66h+D0hMB\n8NQHJ3785F0Znfee4XxCQdXvwh03Pq+vWOHfhxdV+GL/oYI5/3eX0cZlwNXNhgrBE/jjCvh+/qf+\nEuYKKMASHjIYzBihs/pCIBjKCya9eF6CKxRfp3KTjZ2nu0k/P00aR1alNLtPJR6SD3wEBMa7yNgY\nByaV1EQovQeu24Klh9zavCXFUHc3h3j8MqHxZrNfI/eUyIDoEuURBHymJZ13GIYA+mWIFdrXIC84\nSlX5spcjNcB+mHif2EzCB6nJP3AE9aq8cpOJcQjhkcPZHkg2t9l5F5EupuAFUvvfcTXN/y6F3qIr\nThqLyFGwSiGzZX0AwRaNpyXuZKQsNz1WTzj1BjvDSTF1//OlAgzx0F1UZOuh9Hzv4+IBl0yGCHiR\noGXeQvMTSxI1D0BcFoc61ga1nbv3+QY2aYafMEJ+LKq2sz3mGk0Vpzo+swUVCYeveAb11ugkLVq9\nRa5FHeyN5v+RwxysgCDPo+jBUyzguryY6OBJBtBUXJV3Vrg8TEC1JNfIuiaQGmXiWvUj7VD3fgFP\nA/Pax3F+Unn9dJaEhfgG23dLGZyo/H32CTtiWZfkWBJV8/W3g040xdKdNl+Y7sBtjuGt0IdS8lWJ\nbomc8CybMXpVp9SQkhVlf4135WYYZuozj6Kt0dv581TbcnOPMEkTrRnU/XCQOVj9mHD8kDE8BGPs\nu1WPZBZQ1Tfgb5SDwQQf3XYTIQNAnDzjLrEPaxy7I36CFdPTpJXR+DrTmbYH416q/LusHMxfzhkE\nw+OkHqm6czWhunOkfPBoECoA9j609E2s6JDyqqdyNGGw3KsGIu3zyudgD+AeIlbr5wvld3VhQu+k\nGbD1GKPT9sOuQylU6aG0R75sAjP0/RSbLUhGUdAL1NeNa2Q5utBg4b7xY2znf8k43uQuH9gDftQK\nMoCj+4M/kY5vFOehA+mgPmocoo8+ta7JVcwiLjJPyYN/N7RIRvu0bpPfTeQM+6DijB5NSetCHZeW\nKLrP7l1+niGT/aEUEZej5w42fhW5sZHSiMRrLyLeDxPtaeUE82Q8OzcJqmXqsrFMkgyVYOS6vWRE\np8+5qxoxSzeQ36exOktW+E2/pJPFVJYv608U/e/KsJ18RpOpuwdPQeazasQl0zwh9u34LrhV6Hgs\nG8DKy0o62/rCo+JVEb1RdF37hXvTDGFF//rlcyBQgVtwCOJFFL5geugUbu5A/8AzBEN9Pzw0vxPV\nfUaRNNckCcVybD5F7BZ3ielbt42QOneOK6+07rP2GQq6wu4Kocbpi5WXkAwDwn9iEsJT6Vh3Xz9A\nGjEIelxMlGde1Ett9oxHhKcMYEnPyv4evAmG7EErwlTCQd+vp8tPPTmVvXbIJEpz4ViA5GiW8eTI\nk/BkHd7IGq64iYXdddJ63IxopIFrccFbADHVy2LXr73bfFWYkRzvShUlQXRs2nK8iLqkmlEeNa8u\nxaG3JQj0CYQCzTlqrKFs7AK8b8BwqaXmZ3FB9Xfj65H3mkW01gIq4i7sdVBBe4FgjsQAPdA+QPyP\nFymbOZEQQPblH3qHCFfiQ9DDi/zDZi26sar4BjLeoS6GuI2juEmSKZLMcHezPShGjMq7TDo25lD6\nlTlVWv5FmEIE4aI6UTNu4lJ3xl7a4lWJea95qzcitsplCEQA3mhp4zu9euRzSrneC01njKmDnrPH\nmqzSlSiWOcwitRn6BFaIcXktL6gU0l0wbOKHkv4u6Wd4kbpRfHuZGrrcUU9JHlIQn9e7Rhx3a8Le\nWewZ4FHJqc4gDvS+d8JPbCOb0K5VOINAjyn78G8320oCOfCyv3IKlkmyNHvqFcKzpNFcaza/1v/w\nwP46e8ZI\n`pragma protect end_protected\n", "num_lines": 126}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_master #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_SUPPORTS_NARROW = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1,\n   parameter [C_AXI_ADDR_WIDTH-1:0] C_AXI_ADDR = 0,  // Base address\n   parameter integer C_NUM_ADDR = 1,  // Number of address iterations; range 1..2**16 (fixed increment = 32'h10000\n   parameter integer C_NUM_ID = 1,  // Number of ID iterations; range 1..2**C_ID_WIDTH (base = 0; fixed increment = 1)\n   parameter integer C_NUM_LEN = 1,  // Number of LEN iterations; range 1..9 (base = 0; value = 2**i - 1)\n   parameter integer C_NUM_TRANS = 1  // Number of transactions; range >=1 (read and write)\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_awvalid,\n  input  wire                            m_axi_awready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_awsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_awburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_awlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_awlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_awqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_awid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]    m_axi_awuser = 'b0,\n  /**************** Write Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_wid,\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]      m_axi_wdata,\n  (* dont_touch=\"true\" *) output reg [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb = {(C_AXI_DATA_WIDTH/8){1'b1}},\n  (* dont_touch=\"true\" *) output wire                             m_axi_wvalid,\n  input  wire                            m_axi_wready,\n  (* dont_touch=\"true\" *) output wire                             m_axi_wlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]     m_axi_wuser = 'b0,\n  /**************** Write Response Channel Signals ****************/\n  input  wire [2-1:0]                    m_axi_bresp,\n  input  wire                            m_axi_bvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_bready,\n  input  wire [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]     m_axi_buser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_bid,\n  /**************** Read Address Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arprot = 3'b0,\n  (* dont_touch=\"true\" *) output wire                             m_axi_arvalid,\n  input  wire                            m_axi_arready,\n  (* dont_touch=\"true\" *) output reg [3-1:0]                     m_axi_arsize = 3'b0,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                     m_axi_arburst = 2'b01,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arcache = 4'b0,\n  (* dont_touch=\"true\" *) output wire [(C_AXI_PROTOCOL==1?4:8)-1:0]        m_axi_arlen,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_PROTOCOL==1?2:1)-1:0]       m_axi_arlock = 1'b0,\n  (* dont_touch=\"true\" *) output reg [4-1:0]                     m_axi_arqos = 4'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]         m_axi_arid = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]    m_axi_aruser = 'b0,\n  /**************** Read Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]      m_axi_rdata,\n  input  wire [2-1:0]                    m_axi_rresp,\n  input  wire                            m_axi_rvalid,\n  (* dont_touch=\"true\" *) output wire                             m_axi_rready,\n  input  wire                            m_axi_rlast,\n  input  wire [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]     m_axi_ruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        m_axi_rid,\n  /**************** System Signals ****************/\n  input  wire                            aclk,\n  input  wire                            aresetn\n  );\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n  localparam integer  P_NUM_ID_LOG = f_ceil_log2(C_NUM_ID);\n  localparam integer  P_NUM_ADDR_LOG = f_ceil_log2(C_NUM_ADDR);\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL==0 ? 8 : C_AXI_PROTOCOL==1 ? 4 : 1);\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer               P_M_AXI_DATA_BYTES = (C_AXI_DATA_WIDTH / 8);\n  localparam integer               P_M_AXI_DONE_WIDTH = f_ceil_log2(C_NUM_TRANS<2?2:C_NUM_TRANS);\n  localparam integer               P_M_AXI_SIZE = f_ceil_log2(C_AXI_DATA_WIDTH)-3;\n\n  /**************** Internal Wires/Regs - Global ****************/\n   wire                            done;\n    wire                            dummy ;\n  reg                         done_i;\n  reg                         done_sel;\n  wire                         done_cycle;\n  reg                          done_d1 = 1'b0;\n  reg                   areset = 1'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] arcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] rcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [3:0]                    acc_r_i = 4'b0;\n  reg [P_M_AXI_DONE_WIDTH:0] awcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] wcnt_i = {P_M_AXI_DONE_WIDTH{1'b0}};\n  reg [P_M_AXI_DONE_WIDTH:0] bcnt_i = {P_M_AXI_DONE_WIDTH{1'b1}};\n  reg [2:0]                    acc_b_i = 3'b0;\n\n  // Register Reset\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    \n    /**************** Internal Wires/Regs - Read Channels ****************/\n    wire                         read_xaction_done_i;\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_arid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_ADDR_WIDTH:0]      araddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  arprot_i = 3'b0;\n    reg [3-1:0]                  arsize_i = 3'b0;\n    reg [2-1:0]                  arburst_i = 2'b0;\n    reg [4-1:0]                  arcache_i = 4'b0;\n    reg [2-1:0]                  arlock_i = 2'b0;\n    reg [P_LEN_WIDTH-1:0]     arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [4-1:0]                  arqos_i = 4'b0;\n    reg [P_ID_WIDTH-1:0]        arid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [2-1:0]                  rresp_i = 2'b00;\n    reg [C_AXI_RUSER_WIDTH:0]   ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      rid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_arvalid_i = 1'b0;\n    reg                        m_axi_rready_i = 1'b0;\n    reg [P_NUM_ADDR_LOG:0]    araddr_cnt = 0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign read_xaction_done_i = m_axi_rvalid && m_axi_rready_i && ((C_AXI_PROTOCOL==2)?1'b1:m_axi_rlast);\n    assign m_axi_arvalid = m_axi_arvalid_i;\n    assign m_axi_rready = m_axi_rready_i;\n    assign m_axi_araddr = m_axi_araddr_i;\n    assign m_axi_arlen = m_axi_arlen_i;\n    always @(posedge aclk) begin\n      m_axi_arprot <= dummy ? arprot_i : 3'b000;\n      m_axi_arsize <= dummy ? arsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_arburst <= dummy ? arburst_i : 2'b01;\n      m_axi_arlock <= dummy ? arlock_i : 1'b0;\n      m_axi_arcache <= dummy ? arcache_i : 4'h3;\n      m_axi_arqos <= dummy  ? arqos_i : 4'h0;\n      m_axi_aruser <= dummy ? aruser_i : 0;\n    end\n  \n    //**********************************************\n    // Read Channel: ARVALID, ARADDR, ARLEN, RREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_arvalid_i <= 1'b0;\n        arcnt_i <= C_NUM_TRANS;\n        m_axi_arlen_i <= 0;\n        m_axi_araddr_i <= C_AXI_ADDR;\n        m_axi_arid_i <= 1;\n        araddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_arready & m_axi_arvalid_i) begin\n          arcnt_i <= arcnt_i - 1;\n          if (araddr_cnt == 1) begin\n            m_axi_araddr_i <= dummy ? araddr_i : C_AXI_ADDR;\n            araddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_araddr_i <= m_axi_araddr_i + 32'h10000;\n            araddr_cnt <= araddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_arlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_arlen_i <= dummy ? arlen_i : 0;\n          end else begin\n            m_axi_arlen_i <= (m_axi_arlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_arid_i == C_NUM_ID)) begin\n            m_axi_arid <= dummy ? arid_i : 0;\n            m_axi_arid_i <= 1;\n          end else begin\n            m_axi_arid <= m_axi_arid_i;\n            m_axi_arid_i <= m_axi_arid_i + 1;\n          end\n          if (arcnt_i == 1) begin\n            m_axi_arvalid_i <= 1'b0;\n          end\n        end else if (arcnt_i != 0) begin\n          m_axi_arvalid_i <= 1'b1;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      araddr_i <= {araddr_i, ~araddr_i[C_AXI_ADDR_WIDTH]};\n      arprot_i <= {arprot_i, ~arprot_i[3-1]};\n      arlen_i <= {arlen_i, ~arlen_i[P_LEN_WIDTH-1]};\n      arsize_i <= {arsize_i, ~arsize_i[3-1]};\n      arburst_i <= {arburst_i, ~arburst_i[2-1]};\n      arlock_i <= {arlock_i, ~arlock_i[2-1]};\n      arcache_i <= {arcache_i, ~arcache_i[4-1]};\n      arqos_i <= {arqos_i, ~arqos_i[4-1]};\n      aruser_i <= {aruser_i, ~aruser_i[C_AXI_ARUSER_WIDTH]};\n      arid_i <= {arid_i, ~arid_i[P_ID_WIDTH-1]};\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        m_axi_rready_i <= 1'b0;\n        rcnt_i <= C_NUM_TRANS;\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        rresp_i <= {2{1'b0}};\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n        rid_i <= {P_ID_WIDTH{1'b0}};\n        acc_r_i <= 4'b0;\n      end else if (C_AXI_SUPPORTS_READ!=0) begin\n        if (m_axi_rvalid & m_axi_rready_i) begin\n          m_axi_rready_i <= 1'b0;\n          rdata_i <= m_axi_rdata;\n            acc_r_i[0] <= rdata_i[0];\n          rresp_i <= m_axi_rresp;\n            acc_r_i[1] <= rresp_i[0];\n          ruser_i <= m_axi_ruser;\n            acc_r_i[2] <= ruser_i[0];\n          rid_i <= m_axi_rid;\n            acc_r_i[3] <= rid_i[0];\n          if (m_axi_rlast) begin\n            rcnt_i <= rcnt_i - 1;\n          end\n        end else begin\n          rdata_i <= rdata_i>>1;\n          rresp_i <= rresp_i>>1;\n          ruser_i <= ruser_i>>1;\n          rid_i <= rid_i>>1;\n          acc_r_i <= acc_r_i>>1;\n          if (m_axi_rvalid) begin\n            m_axi_rready_i <= 1'b1;\n          end\n        end\n      end\n    end\n    \n    assign dummy = rdata_i[0];\n    \n    \n\n    /**************** Internal Wires/Regs - Write Channels ****************/\n    reg [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr_i = C_AXI_ADDR;\n    reg [C_NUM_ID:0]     m_axi_awid_i = 0;\n    reg [P_LEN_WIDTH-1:0]     m_axi_awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH-1:0]    wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [8-1:0]                  xfer_w_i = 8'h00;\n    wire                         write_burst_done_i;\n    reg [C_AXI_ADDR_WIDTH:0]      awaddr_i = {(C_AXI_ADDR_WIDTH+1){1'b0}};\n    reg [3-1:0]                  awprot_i = 3'b0;\n    reg [P_LEN_WIDTH-1:0]     awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [3-1:0]                  awsize_i = 3'b0;\n    reg [2-1:0]                  awburst_i = 2'b0;\n    reg [4-1:0]                  awcache_i = 4'b0;\n    reg [2-1:0]                  awlock_i = 2'b0;\n    reg [4-1:0]                  awqos_i = 4'b0;\n    reg [P_ID_WIDTH:0]        awid_i = {P_ID_WIDTH{1'b0}};\n    reg [C_AXI_AWUSER_WIDTH:0]    awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg [P_M_AXI_DATA_BYTES-1:0] wstrb_i = {P_M_AXI_DATA_BYTES{1'b1}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]        wid_i = {P_ID_WIDTH{1'b0}};\n    reg [2-1:0]                  bresp_i = 2'b00;\n    reg [C_AXI_BUSER_WIDTH:0]   buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [P_ID_WIDTH:0]      bid_i = {P_ID_WIDTH{1'b0}};\n    reg                        m_axi_awvalid_i = 1'b0;\n    reg                        m_axi_wvalid_i = 1'b0;\n    reg                        m_axi_bready_i = 1'b0;\n    reg                        m_axi_wlast_i = 1'b0;\n    reg                        m_axi_wid_i = {P_ID_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]     wlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [P_NUM_ADDR_LOG:0]    awaddr_cnt = 0;\n  \n    /**************** Assign Write Channel Outputs ****************/\n    assign m_axi_wdata = {wdata_i, done};\n    assign write_burst_done_i = m_axi_wready && m_axi_wvalid_i && ((C_AXI_PROTOCOL==2) || m_axi_wlast_i);\n    assign m_axi_awvalid = m_axi_awvalid_i;\n    assign m_axi_wvalid = m_axi_wvalid_i;\n    assign m_axi_bready = m_axi_bready_i;\n    assign m_axi_wlast = m_axi_wlast_i;\n    assign m_axi_awaddr = m_axi_awaddr_i;\n    assign m_axi_awlen = m_axi_awlen_i;\n    assign m_axi_wid = m_axi_wid_i;\n    always @(posedge aclk) begin\n      m_axi_awprot <= dummy ? awprot_i : 3'b000;\n      m_axi_awsize <= dummy ? awsize_i : C_SUPPORTS_NARROW==0 ? P_M_AXI_SIZE : P_M_AXI_SIZE-1;\n      m_axi_awburst <= dummy ? awburst_i : 2'b01;\n      m_axi_awlock <= dummy ? awlock_i : 1'b0;\n      m_axi_awcache <= dummy ? awcache_i : 4'h3;\n      m_axi_awqos <= dummy ? awqos_i : 4'h0;\n      m_axi_wstrb <= dummy ? wstrb_i : {P_M_AXI_DATA_BYTES{1'b1}};\n      m_axi_awuser <= dummy ?  awuser_i : 0;\n      m_axi_wuser <= dummy ?  wuser_i : 0;\n    end\n  \n    //**********************************************\n    // Write Channel: AWVALID, AWADDR, AWLEN, WVALID, WLAST, BREADY\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_awvalid_i <= 1'b0;\n        m_axi_wvalid_i <= 1'b0;\n        awcnt_i <= C_NUM_TRANS;\n        wcnt_i <= C_NUM_TRANS;\n        xfer_w_i <= 8'h00;\n        m_axi_awlen_i <= 0;\n        m_axi_awaddr_i <= C_AXI_ADDR;\n        m_axi_awid_i <= 1;\n        m_axi_wid_i <= 0;\n        m_axi_wlast_i <= 1'b0;\n        wlen_i <= 0;\n        wid_i <= 0;\n        awaddr_cnt <= C_NUM_ADDR;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_awvalid_i <= 1'b0;\n          awcnt_i <= awcnt_i - 1;\n          if (awaddr_cnt == 1) begin\n            m_axi_awaddr_i <= dummy ? awaddr_i : C_AXI_ADDR;\n            awaddr_cnt <= C_NUM_ADDR;\n          end else begin\n            m_axi_awaddr_i <= m_axi_awaddr_i + 32'h10000;\n            awaddr_cnt <= awaddr_cnt - 1;\n          end\n          if (C_NUM_LEN<2 || |(m_axi_awlen_i>>(C_NUM_LEN-2))) begin\n            m_axi_awlen_i <= dummy ? awlen_i : 0;\n          end else begin\n            m_axi_awlen_i <= (m_axi_awlen_i<<1) | 1'b1;\n          end\n          if (C_NUM_ID<2 || (m_axi_awid_i == C_NUM_ID)) begin\n            m_axi_awid <= dummy ? awid_i : 0;\n            m_axi_awid_i <= 1;\n          end else begin\n            m_axi_awid <= m_axi_awid_i;\n            m_axi_awid_i <= m_axi_awid_i + 1;\n          end\n        end else if (~m_axi_wvalid_i) begin\n          if (awcnt_i != 0) begin\n            m_axi_awvalid_i <= 1'b1;\n          end\n        end\n  \n        /**************** Write Data Channel ****************/\n\n        if (m_axi_wready && m_axi_wvalid_i) begin\n          xfer_w_i <= xfer_w_i - 1'b1;\n          if (m_axi_wlast_i) begin\n            m_axi_wvalid_i <= 1'b0;\n            wcnt_i <= wcnt_i - 1'b1;\n          end else begin\n            m_axi_wlast_i <=  (xfer_w_i == 1);\n          end\n        end else if (m_axi_awready & m_axi_awvalid_i) begin\n          m_axi_wvalid_i <= 1'b1;\n          xfer_w_i <= m_axi_awlen_i;\n          m_axi_wlast_i <= (m_axi_awlen_i==0);\n          m_axi_wid_i <= m_axi_awid_i;\n        end\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: WDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        wdata_i <= (m_axi_wvalid_i && m_axi_wready) ? {wdata_i[C_AXI_DATA_WIDTH-2 : 0], ~wdata_i[C_AXI_DATA_WIDTH-1]} : wdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Write Channel: Random outputs\n    //**********************************************\n    always @(posedge aclk) begin\n      awaddr_i <= {awaddr_i, ~awaddr_i[C_AXI_ADDR_WIDTH]};\n      awprot_i <= {awprot_i[3-2:0], ~awprot_i[3-1]};\n      wstrb_i <= {wstrb_i, ~wstrb_i[C_AXI_DATA_WIDTH/8-1]};\n      awlen_i <= {awlen_i, ~awlen_i[P_LEN_WIDTH-1]};\n      awsize_i <= {awsize_i, ~awsize_i[3-1]};\n      awburst_i <= {awburst_i, ~awburst_i[2-1]};\n      awlock_i <= {awlock_i, ~awlock_i[2-1]};\n      awcache_i <= {awcache_i, ~awcache_i[4-1]};\n      awqos_i <= {awqos_i, ~awqos_i[4-1]};\n      awid_i <= {awid_i, ~awid_i[P_ID_WIDTH-1]};\n      awuser_i <= {awuser_i, ~awuser_i[C_AXI_AWUSER_WIDTH]};\n      wuser_i <= {wuser_i, ~wuser_i[C_AXI_WUSER_WIDTH]};\n    end\n  \n    //**********************************************\n    // Write Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        m_axi_bready_i <= 1'b0;\n        bcnt_i <= C_NUM_TRANS;\n        bresp_i <= {2{1'b0}};\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n        bid_i <= {P_ID_WIDTH{1'b0}};\n        acc_b_i <= 3'b0;\n      end else if (C_AXI_SUPPORTS_WRITE!=0) begin\n        if (m_axi_bvalid & m_axi_bready_i) begin\n          m_axi_bready_i <= 1'b0;\n          bresp_i <= m_axi_bresp;\n            acc_b_i[0] <= bresp_i[0];\n          buser_i <= m_axi_buser;\n            acc_b_i[1] <= buser_i[0];\n          bid_i <= m_axi_bid;\n            acc_b_i[2] <= bid_i[0];\n          bcnt_i <= bcnt_i - 1;\n        end else begin\n          bresp_i <= bresp_i>>1;\n          buser_i <= buser_i>>1;\n          bid_i <= bid_i>>1;\n          acc_b_i <= acc_b_i>>1;\n          if (m_axi_bvalid) begin\n            m_axi_bready_i <= 1'b1;\n          end\n        end\n      end\n    end\n\n\n  //**********************************************\n  // Assert Done\n  //**********************************************\n  always @(posedge aclk) begin\n    if (~aresetn) begin\n      done_d1 <= 1'b0;\n    end else begin\n      done_d1 <= done_i;\n    end\n  end\n\n  assign done = done_sel ? done_i : done_d1;\n  assign done_cycle = done_i & ~done_d1;\n  \n  always @ * begin\n    if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_readonly_done\n       done_i = rcnt_i==0;\n       done_sel = acc_r_i[0];\n    end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_writeonly_done\n       done_i = bcnt_i==0;\n       done_sel = acc_b_i[0];\n    end else begin : gen_readwrite_done\n       done_i = (rcnt_i==0) && (bcnt_i==0);\n       done_sel = acc_r_i[0] ^ acc_b_i[0];\n    end\n  end\n  \nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2019 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule axi_register_slice_v2_1_22_test_slave #\n  (\n   parameter integer C_AXI_ID_WIDTH = 0,\n   parameter integer C_AXI_ADDR_WIDTH = 32,\n   parameter integer C_AXI_DATA_WIDTH = 32,\n   parameter integer C_AXI_PROTOCOL = 0,\n   parameter integer C_AXI_AWUSER_WIDTH = 0,\n   parameter integer C_AXI_ARUSER_WIDTH = 0,\n   parameter integer C_AXI_WUSER_WIDTH = 0,\n   parameter integer C_AXI_RUSER_WIDTH = 0,\n   parameter integer C_AXI_BUSER_WIDTH = 0,\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,\n   parameter integer C_AXI_SUPPORTS_READ = 1\n   )\n  (\n  /**************** Write Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n  input  wire [3-1:0]                   s_axi_awprot,\n  input  wire                           s_axi_awvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_awready,\n  input  wire [3-1:0]                   s_axi_awsize,\n  input  wire [2-1:0]                   s_axi_awburst,\n  input  wire [4-1:0]                   s_axi_awcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_awlen,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_awlock,\n  input  wire [4-1:0]                   s_axi_awqos,\n  input  wire [4-1:0]                   s_axi_awregion,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_awid,\n  input  wire [(C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH)-1:0]   s_axi_awuser,\n  /**************** Write Data Channel Signals ****************/\n  input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n  input  wire                           s_axi_wvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_wready,\n  input  wire                           s_axi_wlast,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_wid,\n  input  wire [(C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH)-1:0]    s_axi_wuser,\n  /**************** Write Response Channel Signals ****************/\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_bresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_bvalid,\n  input  wire                           s_axi_bready,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH)-1:0]    s_axi_buser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_bid = 'b0,\n  /**************** Read Address Channel Signals ****************/\n  input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n  input  wire [3-1:0]                   s_axi_arprot,\n  input  wire                           s_axi_arvalid,\n  (* dont_touch=\"true\" *) output wire                            s_axi_arready,\n  input  wire [3-1:0]                   s_axi_arsize,\n  input  wire [2-1:0]                   s_axi_arburst,\n  input  wire [4-1:0]                   s_axi_arcache,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]     s_axi_arlock,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]      s_axi_arlen,\n  input  wire [4-1:0]                   s_axi_arqos,\n  input  wire [4-1:0]                   s_axi_arregion,\n  input  wire [(C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH)-1:0]   s_axi_aruser,\n  input  wire [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]       s_axi_arid,\n  /**************** Read Data Channel Signals ****************/\n  (* dont_touch=\"true\" *) output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n  (* dont_touch=\"true\" *) output reg [2-1:0]                    s_axi_rresp = 2'b0,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rvalid,\n  input  wire                           s_axi_rready,\n  (* dont_touch=\"true\" *) output wire                            s_axi_rlast,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH)-1:0]    s_axi_ruser = 'b0,\n  (* dont_touch=\"true\" *) output reg [(C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH)-1:0]        s_axi_rid = 'b0,\n  /**************** System Signals ****************/\n  input  wire                           aclk,\n  input  wire                           aresetn\n   );\n\n  /**************** Local Parameters ****************/\n  localparam integer  P_LEN_WIDTH = (C_AXI_PROTOCOL == 1) ? 4 : 8;\n  localparam integer  P_LOCK_WIDTH = (C_AXI_PROTOCOL == 1) ? 2 : 1;\n  localparam integer P_S_AXI_DATA_BYTES = 32/8;\n  localparam integer P_ID_WIDTH = C_AXI_ID_WIDTH==0?1:C_AXI_ID_WIDTH;\n\n  /**************** Internal Wires/Regs - Global ****************/\n  reg                   areset = 1'b0;\n  always @(posedge aclk) begin\n      areset <= ~aresetn;\n  end\n\n    /**************** Internal Wires/Regs - Read Channels ****************/\n    reg [8-1:0]                   xfer_r_cnt = 8'h00;\n    reg [16-1:0]                  arcnt_i = 16'h0000;\n    wire                          read_xaction_done_i;\n    reg [C_AXI_DATA_WIDTH-1:0]     rdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [P_LEN_WIDTH-1:0]      arlen_i = {P_LEN_WIDTH{1'b0}};\n    reg                           arvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     araddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   arprot_i = 3'b000;\n    reg [3-1:0]                   arsize_i = 3'b000;\n    reg [2-1:0]                   arburst_i = 2'b00;\n    reg [4-1:0]                   arcache_i = 4'b0000;\n    reg [1-1:0]     arlock_i = 1'b0;\n    reg [4-1:0]                   arqos_i = 4'b0000;\n    reg [4-1:0]                   arregion_i = 4'b0000;\n    reg [C_AXI_ARUSER_WIDTH:0]    aruser_i = {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_RUSER_WIDTH:0]     ruser_i = {(C_AXI_RUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_ar_i = 9'b0;\n    reg                           s_axi_rvalid_i = 1'b0;\n    reg                           s_axi_arready_i = 1'b0;\n    reg                           s_axi_rlast_i = 1'b0;\n  \n    /**************** Assign Read Channel Outputs ****************/\n    assign s_axi_rdata = rdata_i;\n    assign read_xaction_done_i = (s_axi_rready && s_axi_rvalid_i && s_axi_rlast_i);\n    assign s_axi_rvalid = s_axi_rvalid_i;\n    assign s_axi_arready = s_axi_arready_i;\n    assign s_axi_rlast = s_axi_rlast_i;\n    //**********************************************\n    // Read Channel: ARREADY, RVALID, RLAST, RID\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_arready_i <= 1'b0;\n        s_axi_rvalid_i <= 1'b0;\n        xfer_r_cnt <= 8'h00;\n        arcnt_i <= 16'h0000;\n        arlen_i <= {P_LEN_WIDTH{1'b0}};\n        s_axi_rlast_i <= 1'b0;\n      end else begin\n        /**************** Read Address Channel ****************/\n        // arready\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_arready_i <= 1'b0;\n          arcnt_i <= arcnt_i + 1'b1;\n        end else if (~s_axi_rvalid_i) begin\n          s_axi_arready_i <= 1'b1;\n        end\n  \n        /**************** Read Data Channel ****************/\n        // rvalid\n        if(s_axi_arready_i && s_axi_arvalid) begin\n          s_axi_rvalid_i <= 1'b1;\n          s_axi_rid <= s_axi_arid;\n          s_axi_ruser <= ruser_i;\n        end else if(read_xaction_done_i) begin\n          s_axi_rvalid_i <= 1'b0;\n        end\n  \n        // rlast\n        if(s_axi_rready && s_axi_rvalid_i) begin\n          xfer_r_cnt <= xfer_r_cnt - 1;\n          if(xfer_r_cnt == 1) begin\n            s_axi_rlast_i <= 1'b1;\n          end\n        end else if(s_axi_arready_i && s_axi_arvalid) begin\n          xfer_r_cnt <= s_axi_arlen;\n          s_axi_rlast_i <= (s_axi_arlen==0);\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Read Channel: RDATA\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        rdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n      end else begin\n        rdata_i <= (s_axi_rready && s_axi_rvalid_i) ? {rdata_i[C_AXI_DATA_WIDTH-2 : 0], ~rdata_i[C_AXI_DATA_WIDTH-1]} : rdata_i;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_rresp <= {2{1'b0}};\n      end else if (~s_axi_rvalid_i) begin\n        s_axi_rresp <= {acc_ar_i[0], 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: RUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        ruser_i <= {(C_AXI_RUSER_WIDTH+1){1'b0}};\n      end else begin\n        ruser_i <= (s_axi_arready_i && s_axi_arvalid) ? {ruser_i, ~ruser_i[C_AXI_RUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        araddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        arprot_i <= {3{1'b0}};\n        arsize_i <= {3{1'b0}};\n        arburst_i <= {2{1'b0}};\n        arcache_i <= {4{1'b0}};\n        arlock_i <= {1{1'b0}};\n        arqos_i <= {4{1'b0}};\n        arregion_i <= {4{1'b0}};\n        aruser_i <= {(C_AXI_ARUSER_WIDTH+1){1'b0}};\n        acc_ar_i <= 9'b0;\n      end else if (s_axi_arvalid) begin\n        // Register Inputs\n        araddr_i <= s_axi_araddr;\n          acc_ar_i[0] <= araddr_i[0];\n        arprot_i <= s_axi_arprot;\n          acc_ar_i[1] <= arprot_i[0];\n        arsize_i <= s_axi_arsize;\n          acc_ar_i[2] <= arsize_i[0];\n        arburst_i <= s_axi_arburst;\n          acc_ar_i[3] <= arburst_i[0];\n        arcache_i <= s_axi_arcache;\n          acc_ar_i[4] <= arcache_i[0];\n        arlock_i <= s_axi_arlock;\n          acc_ar_i[5] <= arlock_i[0];\n        arqos_i <= s_axi_arqos;\n          acc_ar_i[6] <= arqos_i[0];\n        arregion_i <= s_axi_arregion;\n          acc_ar_i[7] <= arregion_i[0];\n        aruser_i <= s_axi_aruser;\n          acc_ar_i[8] <= aruser_i[0];\n      end else begin\n        araddr_i <= araddr_i>>1;\n        arprot_i <= arprot_i>>1;\n        arsize_i <= arsize_i>>1;\n        arburst_i <= arburst_i>>1;\n        arcache_i <= arcache_i>>1;\n        arlock_i <= arlock_i>>1;\n        arqos_i <= arqos_i>>1;\n        arregion_i <= arregion_i>>1;\n        aruser_i <= aruser_i>>1;\n        acc_ar_i <= acc_ar_i>>1;\n      end\n    end\n  \n  \n    /**************** Internal Wires/Regs - Write Channels ****************/\n    wire                          write_burst_done_i;\n    reg [16-1:0]                  awcnt_i = 16'h0000;\n    reg                           awvalid_i = 1'b0;\n    reg [C_AXI_ADDR_WIDTH-1:0]     awaddr_i = {C_AXI_ADDR_WIDTH{1'b0}};\n    reg [3-1:0]                   awprot_i = 3'b000;\n    reg [3-1:0]                   awsize_i = 3'b000;\n    reg [2-1:0]                   awburst_i = 2'b00;\n    reg [4-1:0]                   awcache_i = 4'b0000;\n    reg [P_LEN_WIDTH-1:0]      awlen_i = {P_LEN_WIDTH{1'b0}};\n    reg [1-1:0]     awlock_i = 1'b0;\n    reg [4-1:0]                   awqos_i = 4'b0000;\n    reg [4-1:0]                   awregion_i = 4'b0000;\n    reg [C_AXI_AWUSER_WIDTH:0]     awuser_i = {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n    reg                           wvalid_i = 1'b0;\n    reg [C_AXI_DATA_WIDTH-1:0]     wdata_i = {C_AXI_DATA_WIDTH{1'b0}};\n    reg [C_AXI_DATA_WIDTH/8-1:0]   wstrb_i = {(C_AXI_DATA_WIDTH/8){1'b0}};\n    reg [C_AXI_WUSER_WIDTH:0]     wuser_i = {(C_AXI_WUSER_WIDTH+1){1'b0}};\n    reg [C_AXI_BUSER_WIDTH:0]     buser_i = {(C_AXI_BUSER_WIDTH+1){1'b0}};\n    reg [8:0]                     acc_aw_i = 9'b0;\n    reg [3:0]                     acc_w_i = 4'b0;\n    reg                           s_axi_bvalid_i = 1'b0;\n    reg                           s_axi_awready_i = 1'b0;\n    reg                           s_axi_wready_i = 1'b0;\n    /**************** Assign Write Channel Outputs ****************/\n    assign write_burst_done_i =s_axi_wready_i && s_axi_wvalid && ((C_AXI_PROTOCOL == 2) ? 1'b1 : s_axi_wlast);\n    assign s_axi_bvalid = s_axi_bvalid_i;\n    assign s_axi_awready = s_axi_awready_i;\n    assign s_axi_wready = s_axi_wready_i;\n  \n    //**********************************************\n    // Write Channel: AWREADY, WREADY, BVALID, BID\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awcnt_i <= 16'h0000;\n        s_axi_awready_i <= 1'b0;\n        s_axi_wready_i <= 1'b0;\n        s_axi_bvalid_i <= 1'b0;\n      end else begin\n        /**************** Write Address Channel ****************/\n        // awready\n        if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_awready_i <= 1'b0;\n          awcnt_i <= awcnt_i + 1'b1;\n          s_axi_bid <= s_axi_awid;\n          s_axi_buser <= buser_i;\n        end else if(~s_axi_wready_i & ~s_axi_bvalid_i) begin\n          s_axi_awready_i <= 1'b1;\n        end\n  \n        /**************** Write Data Channel ****************/\n        // wready\n        if(write_burst_done_i) begin\n          s_axi_wready_i <= 1'b0;\n        end else if(s_axi_awready_i && s_axi_awvalid) begin\n          s_axi_wready_i <= 1'b1;\n        end\n  \n        /**************** Write Response Channel ****************/\n        // bvalid\n        if(write_burst_done_i) begin\n          s_axi_bvalid_i <= 1'b1;\n        end else if(s_axi_bready && s_axi_bvalid_i) begin\n          s_axi_bvalid_i <= 1'b0;\n        end\n      end\n    end\n  \n  \n    //**********************************************\n    // Write Channel: BRESP\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        s_axi_bresp <= {2{1'b0}};\n      end else if (~s_axi_bvalid_i) begin\n        s_axi_bresp <= {(acc_aw_i[0] ^ acc_w_i[0]), 1'b0};\n      end\n    end\n  \n    //**********************************************\n    // Read Channel: BUSER\n    //**********************************************\n    always @(posedge aclk) begin\n      if (aresetn) begin\n        buser_i <= {(C_AXI_BUSER_WIDTH+1){1'b0}};\n      end else begin\n        buser_i <= (s_axi_awready_i && s_axi_awvalid) ? {buser_i, ~buser_i[C_AXI_BUSER_WIDTH]} : 0;\n      end\n    end\n  \n    //**********************************************\n    // Write Address Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if (areset) begin\n        awaddr_i <= {C_AXI_ADDR_WIDTH{1'b0}};\n        awprot_i <= {3{1'b0}};\n        awsize_i <= {3{1'b0}};\n        awburst_i <= {2{1'b0}};\n        awcache_i <= {4{1'b0}};\n        awlen_i <= {P_LEN_WIDTH{1'b0}};\n        awlock_i <= {1{1'b0}};\n        awqos_i <= {4{1'b0}};\n        awregion_i <= {4{1'b0}};\n        awuser_i <= {(C_AXI_AWUSER_WIDTH+1){1'b0}};\n        acc_aw_i <= 9'b0;\n      end else if (s_axi_awvalid) begin\n        // Register Inputs\n        awaddr_i <= s_axi_awaddr;\n          acc_aw_i[0] <= awaddr_i[0];\n        awprot_i <= s_axi_awprot;\n          acc_aw_i[1] <= awprot_i[0];\n        awsize_i <= s_axi_awsize;\n          acc_aw_i[2] <= awsize_i[0];\n        awburst_i <= s_axi_awburst;\n          acc_aw_i[3] <= awburst_i[0];\n        awcache_i <= s_axi_awcache;\n          acc_aw_i[4] <= awcache_i[0];\n        awlock_i <= s_axi_awlock;\n          acc_aw_i[5] <= awlock_i[0];\n        awqos_i <= s_axi_awqos;\n          acc_aw_i[6] <= awqos_i[0];\n        awregion_i <= s_axi_awregion;\n          acc_aw_i[7] <= awregion_i[0];\n        awuser_i <= s_axi_awuser;\n          acc_aw_i[8] <= awuser_i[0];\n      end else begin\n        awaddr_i <= awaddr_i>>1;\n        awprot_i <= awprot_i>>1;\n        awsize_i <= awsize_i>>1;\n        awburst_i <= awburst_i>>1;\n        awcache_i <= awcache_i>>1;\n        awlock_i <= awlock_i>>1;\n        awqos_i <= awqos_i>>1;\n        awregion_i <= awregion_i>>1;\n        awuser_i <= awuser_i>>1;\n        acc_aw_i <= acc_aw_i>>1;\n      end\n    end\n  \n    //**********************************************\n    // Write Data Channel: PROCESS INPUTS\n    //**********************************************\n    always @(posedge aclk) begin\n      if(areset) begin\n        wdata_i <= {C_AXI_DATA_WIDTH{1'b0}};\n        wstrb_i <= {(C_AXI_DATA_WIDTH/8){1'b0}};\n        wuser_i <= {(C_AXI_WUSER_WIDTH+1){1'b0}};\n        acc_w_i <= 4'b0;\n      end else if (s_axi_wvalid) begin\n        // Register Inputs\n        wdata_i <= s_axi_wdata;\n          acc_w_i[0] <= wdata_i[0];\n        wstrb_i <= s_axi_wstrb;\n          acc_w_i[1] <= wstrb_i[0];\n        wuser_i <= s_axi_wuser;\n          acc_w_i[2] <= wuser_i[0];\n      end else begin\n        wdata_i <= wdata_i>>1;\n        wstrb_i <= wstrb_i>>1;\n        wuser_i <= wuser_i>>1;\n        acc_w_i <= acc_w_i>>1;\n      end\n    end\n  \nendmodule\n\n\n\n//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_22_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \n(* autopipeline_module=\"yes\" *)\nmodule axi_register_slice_v2_1_22_auto_slr #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n    wire                    handshake_pipe;\n    wire                    ready_pipe;\n    wire [C_DATA_WIDTH-1:0] payload_pipe;\n    (* keep=\"true\" *)                                                                reg  s_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  s_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  s_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  s_areset_resp2 = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_aclear = 1'b0;\n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  m_areset_fwd   = 1'b0;\n    (* autopipeline_group=\"resp\" *)                                                  reg  m_areset_resp  = 1'b0;\n    (* keep=\"true\" *)                                                                reg  m_areset_resp2 = 1'b0;\n    \n  // Global Reset pipelining\n  \n    always @(posedge ACLK) begin\n      s_aclear       <= ~ARESETN;\n      s_areset_fwd   <= ~ARESETN; \n      s_areset_resp  <= s_areset_fwd;  // Auto-pipeline\n      s_areset_resp2 <= s_areset_resp; // Auto-pipeline\n    end\n    \n    always @(posedge ACLK) begin\n      m_aclear       <= ~ARESETN;\n      m_areset_fwd   <= ~ARESETN; \n      m_areset_resp  <= m_areset_fwd;  // Auto-pipeline\n      m_areset_resp2 <= m_areset_resp; // Auto-pipeline\n    end\n    \n  // Source-side submodule\n    \n    axi_register_slice_v2_1_22_auto_src #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_src\n      (\n       .ACLK             (ACLK),    \n       .s_aclear         (s_aclear),\n       .s_areset_resp2   (s_areset_resp2),  \n       .S_VALID          (S_VALID),  \n       .S_READY          (S_READY), \n       .S_PAYLOAD_DATA   (S_PAYLOAD_DATA),\n       .ready_pipe        (ready_pipe), \n       .handshake_pipe    (handshake_pipe),\n       .payload_pipe      (payload_pipe)  \n      );\n    \n  // Destination-side submodule\n    \n    axi_register_slice_v2_1_22_auto_dest #\n      (\n       .C_DATA_WIDTH (C_DATA_WIDTH)\n      )\n      slr_auto_dest\n      (\n       .ACLK           (ACLK),    \n       .m_aclear       (m_aclear),\n       .m_areset_resp2 (m_areset_resp2),  \n       .M_READY        (M_READY), \n       .M_VALID        (M_VALID),  \n       .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n       .handshake_pipe  (handshake_pipe),\n       .ready_pipe      (ready_pipe),  \n       .payload_pipe    (payload_pipe)  \n      );\n    \nendmodule  // auto_slr\n\nmodule axi_register_slice_v2_1_22_auto_src #\n  (\n   parameter integer C_DATA_WIDTH = 32\n  )\n  (\n   input  wire ACLK,\n   input  wire s_aclear,\n   input  wire s_areset_resp2,\n   input  wire S_VALID,\n   input  wire ready_pipe,\n   output wire S_READY,\n   output wire handshake_pipe,\n   output wire  [C_DATA_WIDTH-1:0] payload_pipe,\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA\n   );\n    \n   (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *) reg  [C_DATA_WIDTH-1:0] payload_pipe_r;\n    (* keep=\"true\" *) reg [2:0] s_aresetn_resp4 = 3'b000;\n    wire s_aresetn_resp3;\n    wire s_aresetn_d;\n    wire s_aresetn_q;\n    wire s_handshake_d;\n    wire s_ready_i;\n    \n    assign S_READY = s_ready_i & s_aresetn_q;\n    assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q;\n    assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;\n    assign payload_pipe = payload_pipe_r;\n    \n    always @(posedge ACLK or posedge s_aclear) begin\n      if (s_aclear) begin\n        s_aresetn_resp4 <= 3'b000;\n      end else begin\n        s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      payload_pipe_r <= S_PAYLOAD_DATA;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) s_aresetn_resp3_inst (\n        .Q   (s_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~s_areset_resp2)\n     );\n    \n    // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (s_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_aresetn_d)\n     );\n    \n    (* autopipeline_group=\"fwd\",autopipeline_limit=24,autopipeline_include=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (handshake_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (s_handshake_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (s_ready_i),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (s_aclear),\n        .D   (ready_pipe)\n     );\n    \nendmodule  // auto_src\n\nmodule axi_register_slice_v2_1_22_auto_dest #\n  (\n   parameter integer C_DATA_WIDTH = 32\n   )\n  (\n   input  wire ACLK,\n   input  wire m_aclear,\n   input  wire m_areset_resp2,\n   input  wire M_READY,\n   input  wire handshake_pipe,\n   output wire ready_pipe,\n   output wire M_VALID,\n   input  wire [C_DATA_WIDTH-1:0] payload_pipe,\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n   );\n    \n    (* keep=\"true\" *) reg [2:0] m_aresetn_resp4 = 3'b000;\n    wire m_aresetn_resp3;\n    wire m_aresetn_d;\n    wire m_aresetn_q;\n    wire m_valid_i;\n    wire pop;\n    wire m_ready_d;\n    wire m_handshake_q;\n    reg  [C_DATA_WIDTH-1:0] m_payload_q;\n    \n    assign M_VALID = m_valid_i;\n    assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q;\n    assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;\n    assign pop     = M_READY & m_valid_i;\n    \n    always @(posedge ACLK or posedge m_aclear) begin\n      if (m_aclear) begin\n        m_aresetn_resp4 <= 3'b000;\n      end else begin\n        m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3};\n      end\n    end\n    \n    always @(posedge ACLK) begin\n      m_payload_q <= payload_pipe;\n    end\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) m_aresetn_resp3_inst (\n        .Q   (m_aresetn_resp3),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (1'b0),\n        .D   (~m_areset_resp2)\n     );\n    \n    // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.\n    FDCE #(\n        .INIT(1'b0)\n     ) reset_asyncclear (\n        .Q   (m_aresetn_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_aresetn_d)\n     );\n    \n    FDCE #(\n        .INIT(1'b0)\n     ) handshake_asyncclear (\n        .Q   (m_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (handshake_pipe)\n     );\n    \n    (* autopipeline_group=\"resp\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) ready_asyncclear (\n        .Q   (ready_pipe),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (m_aclear),\n        .D   (m_ready_d)\n     );\n    \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  (5)  \n      )\n      srl_fifo\n      (\n       .aclk    (ACLK),    \n       .areset  (~m_aresetn_q),\n       .aclear  (m_aclear),  \n       .s_mesg  (m_payload_q),  \n       .s_valid (m_handshake_q), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      );\n    \nendmodule  // auto_dest\n\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      reg s_valid_d;\n      reg s_ready_d = 1'b0;\n      reg s_ready_reg = 1'b0;\n      reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_22_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_RESP_MIDDLE2_LATENCY = C_PIPELINES_SLAVE + 2 + C_PIPELINES_MIDDLE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_22_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      .ACLK           (ACLK),\n      .ARESETN         (ARESETN),\n      .S_PAYLOAD_DATA (S_PAYLOAD_DATA),\n      .S_VALID        (S_VALID),\n      .S_READY        (S_READY),\n      .M_PAYLOAD_DATA (M_PAYLOAD_DATA),\n      .M_VALID        (M_VALID),\n      .M_READY        (M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_reset;\n    wire src_ready;\n    wire dummy_reset;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  ( C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( dummy_reset   ) ,\n        .laguna_s_reset_in  ( src_reset   ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset   ) ,\n        .laguna_m_reset_in  ( src_reset  ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset2   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n      \n  end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire src_reset;\n    wire [C_DATA_WIDTH-1:0] mid_payload;\n    wire mid_handshake;\n    wire mid_ready;\n    wire mid_reset;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n    wire dest_reset;\n    wire dummy_reset1;\n    wire dummy_reset2;\n    wire dummy_reset3;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN             (ARESETN),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( src_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset1   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset1   ) ,\n        .laguna_s_reset_in  ( src_reset    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out ( mid_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset2   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset2   ) ,\n        .laguna_s_reset_in  ( mid_reset    ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dest_reset   ) ,\n        .laguna_m_reset_in  ( dummy_reset3   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .laguna_s_reset_out ( dummy_reset3   ) ,\n        .laguna_s_reset_in  ( dest_reset    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_22_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        .ACLK               (ACLK),\n        .ACLK2X             (1'b0),\n        .ARESETN            ( ARESETN ),\n        .S_PAYLOAD_DATA     (S_PAYLOAD_DATA),\n        .S_VALID            (S_VALID),\n        .S_READY            (S_READY),\n        .laguna_m_reset_out ( dummy_reset1   ) ,\n        .laguna_m_reset_in  ( src_reset   ) ,\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle_slave (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( src_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset1    ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_reset_out (  dummy_reset2  ) ,\n        .laguna_m_reset_in  ( mid_reset   ) ,\n        .laguna_m_payload   ( mid_payload ) , \n        .laguna_m_handshake ( mid_handshake   ) ,\n        .laguna_m_ready     ( mid_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE2_LATENCY)\n      )\n      slr_middle_master (\n        .ACLK               ( ACLK ) ,\n        .ARESETN             ( ARESETN ) ,\n        .laguna_s_reset_out ( mid_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset2   ) ,\n        .laguna_s_payload   ( mid_payload ) ,\n        .laguna_s_handshake ( mid_handshake   ) ,\n        .laguna_s_ready     ( mid_ready   ) ,\n        .laguna_m_reset_out ( dummy_reset3   ) ,\n        .laguna_m_reset_in  ( dest_reset   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_22_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_CHANNEL    ( C_CHANNEL ),\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK               ( ACLK            ) ,\n        .ACLK2X             (1'b0),\n        .ARESETN             ( ARESETN        ) ,\n        .laguna_s_reset_out ( dest_reset   ) ,\n        .laguna_s_reset_in  ( dummy_reset3    ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA     (M_PAYLOAD_DATA),\n        .M_VALID            (M_VALID),\n        .M_READY            (M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n   \n  generate\n\n  (* keep=\"true\" *) reg s_reset_dd = 1'b0;\n  (* keep=\"true\" *) reg m_reset_dd = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n  (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n  \n  assign laguna_s_reset_out = laguna_s_reset_out_i;\n  assign laguna_m_reset_out = laguna_m_reset_out_i;\n  \n  always @(posedge ACLK) begin\n    laguna_s_reset_in_d <= laguna_s_reset_in;\n    laguna_m_reset_in_d <= laguna_m_reset_in;\n    s_reset_dd <= laguna_s_reset_in_d;\n    m_reset_dd <= laguna_m_reset_in_d;\n    laguna_s_reset_out_i <= C_PIPELINES==0 ? laguna_m_reset_in_d : m_reset_dd;\n    laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd;\n  end\n  \n  wire ACLEAR;\n  assign ACLEAR = ~ARESETN;\n  \n  if (1) begin : common\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire laguna_s_handshake_q;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, laguna_m_ready_d}; \n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else if (p==C_PIPELINES+1) begin\n          laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n\n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = handshake_i[C_PIPELINES];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   input  wire laguna_m_reset_in,\n   output wire laguna_m_reset_out,\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_m_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* keep=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_22_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_m_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_m_reset_out = laguna_m_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_m_reset_in_d <= laguna_m_reset_in;\n      aresetn_d <= C_CHANNEL==P_FORWARD ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? areset_dly[15]  : laguna_m_reset_in_d;\n      laguna_m_reset_out_i <= areset_d;  // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n  \n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    wire m_handshake_d;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* keep=\"true\" *)  reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      laguna_m_ready_d <= laguna_m_ready; \n      ready_d <= {ready_d, laguna_m_ready_d}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid_q;\n      assign payload_valid_d = (p==0) ? (S_VALID & s_ready_i) : handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==C_PIPELINES) begin\n          laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end else if (p==0) begin\n          payload_data <= S_PAYLOAD_DATA;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n      \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & s_ready_i) : handshake_i[P_PIPE_WIDTH-1];\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_m_handshake_asyncclear_inst (\n        .Q   (laguna_m_handshake),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (m_handshake_d)\n     );\n    \n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_CHANNEL = 0,  // 0=Forward, 1=Response\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire laguna_s_reset_in,\n   output wire laguna_s_reset_out,\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  if (C_REG_CONFIG == 13) begin : tdm\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    always @(posedge ACLK) begin\n      areset_d <= ~ARESETN;\n    end\n    assign laguna_s_reset_out = 1'b0;\n  \n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* keep=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1;\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_FORWARD = 0;\n    localparam integer P_RESPONSE = 1;\n     \n    (* keep=\"true\" *)    reg aresetn_d = 1'b1;\n    (* keep=\"true\" *) reg areset_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_in_d = 1'b0;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *) reg laguna_s_reset_out_i = 1'b0;\n                               reg [15:0] areset_dly = 16'b0;\n    \n    assign laguna_s_reset_out = laguna_s_reset_out_i;\n    \n    always @(posedge ACLK) begin\n      laguna_s_reset_in_d <= laguna_s_reset_in;\n      aresetn_d <= C_CHANNEL==P_RESPONSE ? ARESETN : 1'b1;\n      areset_dly <= {16{~aresetn_d}} | (areset_dly<<1);\n      areset_d <= C_REG_CONFIG == 12 ? ~ARESETN : C_CHANNEL==P_FORWARD ? laguna_s_reset_in_d : areset_dly[15];\n      laguna_s_reset_out_i <= areset_d;  // For forward channels, reflect laguna_s_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used.\n    end\n\n    wire ACLEAR;\n    assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ~ARESETN;\n  \n    (* USER_SLL_REG=\"true\", shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    wire laguna_s_handshake_q;\n    (* USER_SLL_REG=\"true\", keep=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      laguna_s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1];\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      wire payload_valid_d;\n      wire payload_valid_q;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q;\n      assign payload_valid_d = handshake_i[((p>0)?(p-1):0)];\n      \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          laguna_s_payload_d <= laguna_s_payload;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n        end\n      end\n        \n      FDCE #(\n          .INIT(1'b0)\n       ) payload_valid_asyncclear_inst (\n          .Q   (payload_valid_q),\n          .C   (ACLK), \n          .CE  (1'b1),\n          .CLR (ACLEAR),\n          .D   (payload_valid_d)\n       );\n    end  // loop p\n    \n    (* USER_SLL_REG=\"true\" *)\n    FDCE #(\n        .INIT(1'b0)\n     ) laguna_s_handshake_asyncclear_inst (\n        .Q   (laguna_s_handshake_q),\n        .C   (ACLK), \n        .CE  (1'b1),\n        .CLR (ACLEAR),\n        .D   (laguna_s_handshake)\n     );\n        \n    axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n      (\n       .C_FIFO_WIDTH (C_DATA_WIDTH), \n       .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4)  \n      )\n      srl_fifo_0\n      (\n       .aclk    (ACLK),    \n       .areset  (areset_d),  \n       .aclear  (ACLEAR),\n       .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n       .s_valid (push), \n       .m_mesg  (M_PAYLOAD_DATA),  \n       .m_valid (m_valid_i), \n       .m_ready (pop)\n      ); \n  \n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_22_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESETN,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  reg areset_d = 1'b0;\n  reg [3:0] areset_dly = 4'b0;\n  always @(posedge ACLK) begin\n    areset_dly <= {4{~ARESETN}} | (areset_dly<<1);\n    areset_d <= areset_dly[3];\n  end\n  \n  if (1) begin : common\n    reg s_ready_i = 1'b0;\n    (* keep=\"true\" *)  reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}};\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push = handshake_i[C_PIPELINES];      \n    assign M_VALID = m_valid_i;\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      ready_d <= {ready_d, (M_READY | ~m_valid_i)}; \n      if (areset_d) begin\n        s_ready_i <= 1'b0; \n      end else begin\n        s_ready_i <= (C_PIPELINES==0) ? (M_READY | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; \n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID & s_ready_i;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* keep=\"true\" *)  reg payload_valid = 1'b0;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          payload_data <= S_PAYLOAD_DATA;\n          payload_valid <= S_VALID & s_ready_i & ~areset_d;\n        end else begin\n          payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH];\n          payload_valid <= handshake_i[((p>0)?(p-1):0)];\n        end\n      end\n    end\n    \n    if (C_PIPELINES==0) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),\n         .aclear  (1'b0),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire                        aclear,  // Async clear\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    wire [1:0] state;  // State vector register\n    reg  [1:0] next;           // Next state value\n    wire [1:0] next_qual;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    reg  m_valid_d;\n    wire m_valid_q;\n    \n    assign m_valid = m_valid_q;\n    assign next_qual = areset ? K_EMPTY : next;\n    assign m_mesg  = mesg_reg;\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_mvalid_inst (\n        .Q   (m_valid_q),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (m_valid_d)\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state0_inst (\n        .Q   (state[0]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[0])\n     );\n\n    FDCE #(\n        .INIT(1'b0)\n     ) asyncclear_state1_inst (\n        .Q   (state[1]),\n        .C   (aclk), \n        .CE  (1'b1),\n        .CLR (aclear),\n        .D   (next_qual[1])\n     );\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      m_valid_d = m_valid_q & ~areset;\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid & ~areset) begin\n            next = K_HAS1;\n            m_valid_d = 1'b0;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              m_valid_d = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n              m_valid_d = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              m_valid_d = 1'b1;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          m_valid_d = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      (* keep_hierarchy = \"yes\" *) axi_register_slice_v2_1_22_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule  // axic_reg_srl_fifo\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_22_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   //   16 -> Auto-pipelining\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_RESERVE_MODE = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n  \n  if (C_RESERVE_MODE==1) begin : gen_reserve_si\n  \n    axi_register_slice_v2_1_22_test_slave #(\n      .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n      .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n      .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n      .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n      .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n      .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n      .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n      .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n      .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .s_axi_awaddr(s_axi_awaddr),\n      .s_axi_awprot(s_axi_awprot),\n      .s_axi_awvalid(s_axi_awvalid),\n      .s_axi_awready(s_axi_awready),\n      .s_axi_awsize(s_axi_awsize),\n      .s_axi_awburst(s_axi_awburst),\n      .s_axi_awcache(s_axi_awcache),\n      .s_axi_awlen(s_axi_awlen),\n      .s_axi_awlock(s_axi_awlock),\n      .s_axi_awqos(s_axi_awqos),\n      .s_axi_awregion(s_axi_awregion),\n      .s_axi_awid(s_axi_awid),\n      .s_axi_awuser(s_axi_awuser),\n      .s_axi_wdata(s_axi_wdata),\n      .s_axi_wstrb(s_axi_wstrb),\n      .s_axi_wvalid(s_axi_wvalid),\n      .s_axi_wready(s_axi_wready),\n      .s_axi_wlast(s_axi_wlast),\n      .s_axi_wid(s_axi_wid),\n      .s_axi_wuser(s_axi_wuser),\n      .s_axi_bresp(s_axi_bresp),\n      .s_axi_bvalid(s_axi_bvalid),\n      .s_axi_bready(s_axi_bready),\n      .s_axi_buser(s_axi_buser),\n      .s_axi_bid(s_axi_bid),\n      .s_axi_araddr(s_axi_araddr),\n      .s_axi_arprot(s_axi_arprot),\n      .s_axi_arvalid(s_axi_arvalid),\n      .s_axi_arready(s_axi_arready),\n      .s_axi_arsize(s_axi_arsize),\n      .s_axi_arburst(s_axi_arburst),\n      .s_axi_arcache(s_axi_arcache),\n      .s_axi_arlock(s_axi_arlock),\n      .s_axi_arlen(s_axi_arlen),\n      .s_axi_arqos(s_axi_arqos),\n      .s_axi_arregion(s_axi_arregion),\n      .s_axi_aruser(s_axi_aruser),\n      .s_axi_arid(s_axi_arid),\n      .s_axi_rdata(s_axi_rdata),\n      .s_axi_rresp(s_axi_rresp),\n      .s_axi_rvalid(s_axi_rvalid),\n      .s_axi_rready(s_axi_rready),\n      .s_axi_rlast(s_axi_rlast),\n      .s_axi_ruser(s_axi_ruser),\n      .s_axi_rid(s_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign m_axi_awid     = 0;\n     assign m_axi_awaddr   = 0;\n     assign m_axi_awlen    = 0;\n     assign m_axi_awsize   = 0;\n     assign m_axi_awburst  = 0;\n     assign m_axi_awlock   = 0;\n     assign m_axi_awcache  = 0;\n     assign m_axi_awprot   = 0;\n     assign m_axi_awregion = 0;\n     assign m_axi_awqos    = 0;\n     assign m_axi_awuser   = 0;\n     assign m_axi_awvalid  = 0;\n     assign m_axi_wid      = 0;\n     assign m_axi_wdata    = 0;\n     assign m_axi_wstrb    = 0;\n     assign m_axi_wlast    = 0;\n     assign m_axi_wuser    = 0;\n     assign m_axi_wvalid   = 0;\n     assign m_axi_bready   = 0;\n     assign m_axi_arid     = 0;\n     assign m_axi_araddr   = 0;\n     assign m_axi_arlen    = 0;\n     assign m_axi_arsize   = 0;\n     assign m_axi_arburst  = 0;\n     assign m_axi_arlock   = 0;\n     assign m_axi_arcache  = 0;\n     assign m_axi_arprot   = 0;\n     assign m_axi_arregion = 0;\n     assign m_axi_arqos    = 0;\n     assign m_axi_aruser   = 0;\n     assign m_axi_arvalid  = 0;\n     assign m_axi_rready   = 0;\n      \n  end else if (C_RESERVE_MODE==2) begin : gen_reserve_mi\n    \n    axi_register_slice_v2_1_22_test_master #(\n    .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n    .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),\n    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH)\n    ) inst (\n      .m_axi_awaddr(m_axi_awaddr),\n      .m_axi_awprot(m_axi_awprot),\n      .m_axi_awvalid(m_axi_awvalid),\n      .m_axi_awready(m_axi_awready),\n      .m_axi_awsize(m_axi_awsize),\n      .m_axi_awburst(m_axi_awburst),\n      .m_axi_awcache(m_axi_awcache),\n      .m_axi_awlen(m_axi_awlen),\n      .m_axi_awlock(m_axi_awlock),\n      .m_axi_awqos(m_axi_awqos),\n      .m_axi_awid(m_axi_awid),\n      .m_axi_awuser(m_axi_awuser),\n      .m_axi_wid(m_axi_wid),\n      .m_axi_wdata(m_axi_wdata),\n      .m_axi_wstrb(m_axi_wstrb),\n      .m_axi_wvalid(m_axi_wvalid),\n      .m_axi_wready(m_axi_wready),\n      .m_axi_wlast(m_axi_wlast),\n      .m_axi_wuser(m_axi_wuser),\n      .m_axi_bresp(m_axi_bresp),\n      .m_axi_bvalid(m_axi_bvalid),\n      .m_axi_bready(m_axi_bready),\n      .m_axi_buser(m_axi_buser),\n      .m_axi_bid(m_axi_bid),\n      .m_axi_araddr(m_axi_araddr),\n      .m_axi_arprot(m_axi_arprot),\n      .m_axi_arvalid(m_axi_arvalid),\n      .m_axi_arready(m_axi_arready),\n      .m_axi_arsize(m_axi_arsize),\n      .m_axi_arburst(m_axi_arburst),\n      .m_axi_arcache(m_axi_arcache),\n      .m_axi_arlen(m_axi_arlen),\n      .m_axi_arlock(m_axi_arlock),\n      .m_axi_arqos(m_axi_arqos),\n      .m_axi_arid(m_axi_arid),\n      .m_axi_aruser(m_axi_aruser),\n      .m_axi_rdata(m_axi_rdata),\n      .m_axi_rresp(m_axi_rresp),\n      .m_axi_rvalid(m_axi_rvalid),\n      .m_axi_rready(m_axi_rready),\n      .m_axi_rlast(m_axi_rlast),\n      .m_axi_ruser(m_axi_ruser),\n      .m_axi_rid(m_axi_rid),\n      .aclk(aclk),\n      .aresetn(aresetn)\n    );\n    \n     assign s_axi_awready = 0;\n     assign s_axi_wready  = 0;\n     assign s_axi_bid     = 0;\n     assign s_axi_bresp   = 0;\n     assign s_axi_buser   = 0;\n     assign s_axi_bvalid  = 0;\n     assign s_axi_arready = 0;\n     assign s_axi_rid     = 0;\n     assign s_axi_rdata   = 0;\n     assign s_axi_rresp   = 0;\n     assign s_axi_rlast   = 0;\n     assign s_axi_ruser   = 0;\n     assign s_axi_rvalid  = 0;\n\n  end else begin : gen_reg_slice  // Any normal reg-slice mode\n\n    axi_infrastructure_v1_1_0_axi2vector #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    axi2vector_0 ( \n      .s_axi_awid      ( s_axi_awid      ) ,\n      .s_axi_awaddr    ( s_axi_awaddr    ) ,\n      .s_axi_awlen     ( s_axi_awlen     ) ,\n      .s_axi_awsize    ( s_axi_awsize    ) ,\n      .s_axi_awburst   ( s_axi_awburst   ) ,\n      .s_axi_awlock    ( s_axi_awlock    ) ,\n      .s_axi_awcache   ( s_axi_awcache   ) ,\n      .s_axi_awprot    ( s_axi_awprot    ) ,\n      .s_axi_awqos     ( s_axi_awqos     ) ,\n      .s_axi_awuser    ( s_axi_awuser    ) ,\n      .s_axi_awregion  ( s_axi_awregion  ) ,\n      .s_axi_wid       ( s_axi_wid       ) ,\n      .s_axi_wdata     ( s_axi_wdata     ) ,\n      .s_axi_wstrb     ( s_axi_wstrb     ) ,\n      .s_axi_wlast     ( s_axi_wlast     ) ,\n      .s_axi_wuser     ( s_axi_wuser     ) ,\n      .s_axi_bid       ( s_axi_bid       ) ,\n      .s_axi_bresp     ( s_axi_bresp     ) ,\n      .s_axi_buser     ( s_axi_buser     ) ,\n      .s_axi_arid      ( s_axi_arid      ) ,\n      .s_axi_araddr    ( s_axi_araddr    ) ,\n      .s_axi_arlen     ( s_axi_arlen     ) ,\n      .s_axi_arsize    ( s_axi_arsize    ) ,\n      .s_axi_arburst   ( s_axi_arburst   ) ,\n      .s_axi_arlock    ( s_axi_arlock    ) ,\n      .s_axi_arcache   ( s_axi_arcache   ) ,\n      .s_axi_arprot    ( s_axi_arprot    ) ,\n      .s_axi_arqos     ( s_axi_arqos     ) ,\n      .s_axi_aruser    ( s_axi_aruser    ) ,\n      .s_axi_arregion  ( s_axi_arregion  ) ,\n      .s_axi_rid       ( s_axi_rid       ) ,\n      .s_axi_rdata     ( s_axi_rdata     ) ,\n      .s_axi_rresp     ( s_axi_rresp     ) ,\n      .s_axi_rlast     ( s_axi_rlast     ) ,\n      .s_axi_ruser     ( s_axi_ruser     ) ,\n      .s_awpayload ( s_awpayload ) ,\n      .s_wpayload  ( s_wpayload  ) ,\n      .s_bpayload  ( s_bpayload  ) ,\n      .s_arpayload ( s_arpayload ) ,\n      .s_rpayload  ( s_rpayload  ) \n    );\n    \n    axi_infrastructure_v1_1_0_vector2axi #( \n      .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n      .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n      .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n      .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n      .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n      .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n      .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n      .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n      .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n      .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n      .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n      .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n      .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n      .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n      .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n      .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n    )\n    vector2axi_0 ( \n      .m_awpayload    ( m_awpayload    ) ,\n      .m_wpayload     ( m_wpayload     ) ,\n      .m_bpayload     ( m_bpayload     ) ,\n      .m_arpayload    ( m_arpayload    ) ,\n      .m_rpayload     ( m_rpayload     ) ,\n      .m_axi_awid     ( m_axi_awid     ) ,\n      .m_axi_awaddr   ( m_axi_awaddr   ) ,\n      .m_axi_awlen    ( m_axi_awlen    ) ,\n      .m_axi_awsize   ( m_axi_awsize   ) ,\n      .m_axi_awburst  ( m_axi_awburst  ) ,\n      .m_axi_awlock   ( m_axi_awlock   ) ,\n      .m_axi_awcache  ( m_axi_awcache  ) ,\n      .m_axi_awprot   ( m_axi_awprot   ) ,\n      .m_axi_awqos    ( m_axi_awqos    ) ,\n      .m_axi_awuser   ( m_axi_awuser   ) ,\n      .m_axi_awregion ( m_axi_awregion ) ,\n      .m_axi_wid      ( m_axi_wid      ) ,\n      .m_axi_wdata    ( m_axi_wdata    ) ,\n      .m_axi_wstrb    ( m_axi_wstrb    ) ,\n      .m_axi_wlast    ( m_axi_wlast    ) ,\n      .m_axi_wuser    ( m_axi_wuser    ) ,\n      .m_axi_bid      ( m_axi_bid      ) ,\n      .m_axi_bresp    ( m_axi_bresp    ) ,\n      .m_axi_buser    ( m_axi_buser    ) ,\n      .m_axi_arid     ( m_axi_arid     ) ,\n      .m_axi_araddr   ( m_axi_araddr   ) ,\n      .m_axi_arlen    ( m_axi_arlen    ) ,\n      .m_axi_arsize   ( m_axi_arsize   ) ,\n      .m_axi_arburst  ( m_axi_arburst  ) ,\n      .m_axi_arlock   ( m_axi_arlock   ) ,\n      .m_axi_arcache  ( m_axi_arcache  ) ,\n      .m_axi_arprot   ( m_axi_arprot   ) ,\n      .m_axi_arqos    ( m_axi_arqos    ) ,\n      .m_axi_aruser   ( m_axi_aruser   ) ,\n      .m_axi_arregion ( m_axi_arregion ) ,\n      .m_axi_rid      ( m_axi_rid      ) ,\n      .m_axi_rdata    ( m_axi_rdata    ) ,\n      .m_axi_rresp    ( m_axi_rresp    ) ,\n      .m_axi_rlast    ( m_axi_rlast    ) ,\n      .m_axi_ruser    ( m_axi_ruser    ) \n    );\n    \n  end  // Reserve SI/MI branch\n\n  if ((C_REG_CONFIG_AW <= 9) && (C_RESERVE_MODE==0)) begin : aw\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 15) && (C_RESERVE_MODE==0)) begin : aw15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if ((C_REG_CONFIG_AW == 16) && (C_RESERVE_MODE==0)) begin : aw16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) \n    )\n    aw_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if ((C_REG_CONFIG_W <= 9) && (C_RESERVE_MODE==0)) begin : w\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 15) && (C_RESERVE_MODE==0)) begin : w15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if ((C_REG_CONFIG_W == 16) && (C_RESERVE_MODE==0)) begin : w16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) \n    )\n    w_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if ((C_REG_CONFIG_B <= 9) && (C_RESERVE_MODE==0)) begin : b\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if ((C_REG_CONFIG_B == 15) && (C_RESERVE_MODE==0)) begin : b15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if ((C_REG_CONFIG_B == 16) && (C_RESERVE_MODE==0)) begin : b16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) \n    )\n    b_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if ((C_REG_CONFIG_AR <= 9) && (C_RESERVE_MODE==0)) begin : ar\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 15) && (C_RESERVE_MODE==0)) begin : ar15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if ((C_REG_CONFIG_AR == 16) && (C_RESERVE_MODE==0)) begin : ar16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) \n    )\n    ar_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if ((C_REG_CONFIG_R <= 9) && (C_RESERVE_MODE==0)) begin : r\n    axi_register_slice_v2_1_22_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 15) && (C_RESERVE_MODE==0)) begin : r15\n    \n    axi_register_slice_v2_1_22_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if ((C_REG_CONFIG_R == 16) && (C_RESERVE_MODE==0)) begin : r16\n    \n    axi_register_slice_v2_1_22_auto_slr # (\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) \n    )\n    r_auto (\n      // System Signals\n      .ACLK(aclk),\n      .ARESETN(aresetn),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_RESERVE_MODE==0) begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_22_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_reset_in  ( 1'b0 ) ,\n      .laguna_m_reset_out  (  ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_22_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESETN        ( aresetn        ) ,\n      .laguna_s_reset_in  ( 1'b0 ) ,\n      .laguna_s_reset_out  (  ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 4844}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/*\n *******************************************************************************\n *\n * FIFO Generator - Verilog Behavioral Model\n *\n *******************************************************************************\n *\n * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.\n *\n * This file contains confidential and proprietary information\n * of Xilinx, Inc. and is protected under U.S. and\n * international copyright and other intellectual property\n * laws.\n *\n * DISCLAIMER\n * This disclaimer is not a license and does not grant any\n * rights to the materials distributed herewith. Except as\n * otherwise provided in a valid license issued to you by\n * Xilinx, and to the maximum extent permitted by applicable\n * law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n * (2) Xilinx shall not be liable (whether in contract or tort,\n * including negligence, or under any other theory of\n * liability) for any loss or damage of any kind or nature\n * related to, arising under or in connection with these\n * materials, including for any direct, or any indirect,\n * special, incidental, or consequential loss or damage\n * (including loss of data, profits, goodwill, or any type of\n * loss or damage suffered as a result of any action brought\n * by a third party) even if such damage or loss was\n * reasonably foreseeable or Xilinx had been advised of the\n * possibility of the same.\n *\n * CRITICAL APPLICATIONS\n * Xilinx products are not designed or intended to be fail-\n * safe, or for use in any application requiring fail-safe\n * performance, such as life-support or safety devices or\n * systems, Class III medical devices, nuclear facilities,\n * applications related to the deployment of airbags, or any\n * other applications that could lead to death, personal\n * injury, or severe property or environmental damage\n * (individually and collectively, \"Critical\n * Applications\"). Customer assumes the sole risk and\n * liability of any use of Xilinx products in Critical\n * Applications, subject only to applicable laws and\n * regulations governing limitations on product liability.\n *\n * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n * PART OF THIS FILE AT ALL TIMES.\n *\n *******************************************************************************\n *******************************************************************************\n *\n * Filename: fifo_generator_vlog_beh.v\n *\n * Author     : Xilinx\n *\n *******************************************************************************\n * Structure:\n * \n * fifo_generator_vlog_beh.v\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_as\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_ss\n *    |\n *    +-fifo_generator_v13_2_5_bhv_ver_preload0\n * \n *******************************************************************************\n * Description:\n *\n * The Verilog behavioral model for the FIFO Generator.\n *\n *   The behavioral model has three parts:\n *      - The behavioral model for independent clocks FIFOs (_as)\n *      - The behavioral model for common clock FIFOs (_ss)\n *      - The \"preload logic\" block which implements First-word Fall-through\n * \n *******************************************************************************\n * Description:\n *  The verilog behavioral model for the FIFO generator core.\n *\n *******************************************************************************\n */\n\n`timescale 1ps/1ps\n`ifndef TCQ\n `define TCQ 100\n`endif\n\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_vlog_beh\n  #(\n    //-----------------------------------------------------------------------\n    // Generic Declarations\n    //-----------------------------------------------------------------------\n    parameter C_COMMON_CLOCK                 = 0,\n    parameter C_COUNT_TYPE                   = 0,\n    parameter C_DATA_COUNT_WIDTH             = 2,\n    parameter C_DEFAULT_VALUE                = \"\",\n    parameter C_DIN_WIDTH                    = 8,\n    parameter C_DOUT_RST_VAL                 = \"\",\n    parameter C_DOUT_WIDTH                   = 8,\n    parameter C_ENABLE_RLOCS                 = 0,\n    parameter C_FAMILY                       = \"\",\n    parameter C_FULL_FLAGS_RST_VAL           = 1,\n    parameter C_HAS_ALMOST_EMPTY             = 0,\n    parameter C_HAS_ALMOST_FULL              = 0,\n    parameter C_HAS_BACKUP                   = 0,\n    parameter C_HAS_DATA_COUNT               = 0,\n    parameter C_HAS_INT_CLK                  = 0,\n    parameter C_HAS_MEMINIT_FILE             = 0,\n    parameter C_HAS_OVERFLOW                 = 0,\n    parameter C_HAS_RD_DATA_COUNT            = 0,\n    parameter C_HAS_RD_RST                   = 0,\n    parameter C_HAS_RST                      = 1,\n    parameter C_HAS_SRST                     = 0,\n    parameter C_HAS_UNDERFLOW                = 0,\n    parameter C_HAS_VALID                    = 0,\n    parameter C_HAS_WR_ACK                   = 0,\n    parameter C_HAS_WR_DATA_COUNT            = 0,\n    parameter C_HAS_WR_RST                   = 0,\n    parameter C_IMPLEMENTATION_TYPE          = 0,\n    parameter C_INIT_WR_PNTR_VAL             = 0,\n    parameter C_MEMORY_TYPE                  = 1,\n    parameter C_MIF_FILE_NAME                = \"\",\n    parameter C_OPTIMIZATION_MODE            = 0,\n    parameter C_OVERFLOW_LOW                 = 0,\n    parameter C_EN_SAFETY_CKT                = 0,\n    parameter C_PRELOAD_LATENCY              = 1,\n    parameter C_PRELOAD_REGS                 = 0,\n    parameter C_PRIM_FIFO_TYPE               = \"4kx4\",\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter C_PROG_EMPTY_TYPE              = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter C_PROG_FULL_TYPE               = 0,\n    parameter C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter C_RD_DEPTH                     = 256,\n    parameter C_RD_FREQ                      = 1,\n    parameter C_RD_PNTR_WIDTH                = 8,\n    parameter C_UNDERFLOW_LOW                = 0,\n    parameter C_USE_DOUT_RST                 = 0,\n    parameter C_USE_ECC                      = 0,\n    parameter C_USE_EMBEDDED_REG             = 0,\n    parameter C_USE_PIPELINE_REG             = 0,\n    parameter C_POWER_SAVING_MODE            = 0,\n    parameter C_USE_FIFO16_FLAGS             = 0,\n    parameter C_USE_FWFT_DATA_COUNT          = 0,\n    parameter C_VALID_LOW                    = 0,\n    parameter C_WR_ACK_LOW                   = 0,\n    parameter C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter C_WR_DEPTH                     = 256,\n    parameter C_WR_FREQ                      = 1,\n    parameter C_WR_PNTR_WIDTH                = 8,\n    parameter C_WR_RESPONSE_LATENCY          = 1,\n    parameter C_MSGON_VAL                    = 1,\n    parameter C_ENABLE_RST_SYNC              = 1,\n    parameter C_ERROR_INJECTION_TYPE         = 0,\n    parameter C_SYNCHRONIZER_STAGE           = 2,\n\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE               = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3\n    parameter C_AXI_TYPE                     = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3\n    parameter C_HAS_AXI_WR_CHANNEL           = 0,\n    parameter C_HAS_AXI_RD_CHANNEL           = 0,\n    parameter C_HAS_SLAVE_CE                 = 0,\n    parameter C_HAS_MASTER_CE                = 0,\n    parameter C_ADD_NGC_CONSTRAINT           = 0,\n    parameter C_USE_COMMON_UNDERFLOW         = 0,\n    parameter C_USE_COMMON_OVERFLOW          = 0,\n    parameter C_USE_DEFAULT_SETTINGS         = 0,\n\n    // AXI Full/Lite\n    parameter C_AXI_ID_WIDTH                 = 0,\n    parameter C_AXI_ADDR_WIDTH               = 0,\n    parameter C_AXI_DATA_WIDTH               = 0,\n    parameter C_AXI_LEN_WIDTH                = 8,\n    parameter C_AXI_LOCK_WIDTH               = 2,\n    parameter C_HAS_AXI_ID                   = 0,\n    parameter C_HAS_AXI_AWUSER               = 0,\n    parameter C_HAS_AXI_WUSER                = 0,\n    parameter C_HAS_AXI_BUSER                = 0,\n    parameter C_HAS_AXI_ARUSER               = 0,\n    parameter C_HAS_AXI_RUSER                = 0,\n    parameter C_AXI_ARUSER_WIDTH             = 0,\n    parameter C_AXI_AWUSER_WIDTH             = 0,\n    parameter C_AXI_WUSER_WIDTH              = 0,\n    parameter C_AXI_BUSER_WIDTH              = 0,\n    parameter C_AXI_RUSER_WIDTH              = 0,\n\n    // AXI Streaming\n    parameter C_HAS_AXIS_TDATA               = 0,\n    parameter C_HAS_AXIS_TID                 = 0,\n    parameter C_HAS_AXIS_TDEST               = 0,\n    parameter C_HAS_AXIS_TUSER               = 0,\n    parameter C_HAS_AXIS_TREADY              = 0,\n    parameter C_HAS_AXIS_TLAST               = 0,\n    parameter C_HAS_AXIS_TSTRB               = 0,\n    parameter C_HAS_AXIS_TKEEP               = 0,\n    parameter C_AXIS_TDATA_WIDTH             = 1,\n    parameter C_AXIS_TID_WIDTH               = 1,\n    parameter C_AXIS_TDEST_WIDTH             = 1,\n    parameter C_AXIS_TUSER_WIDTH             = 1,\n    parameter C_AXIS_TSTRB_WIDTH             = 1,\n    parameter C_AXIS_TKEEP_WIDTH             = 1,\n\n    // AXI Channel Type\n    // WACH --> Write Address Channel\n    // WDCH --> Write Data Channel\n    // WRCH --> Write Response Channel\n    // RACH --> Read Address Channel\n    // RDCH --> Read Data Channel\n    // AXIS --> AXI Streaming\n    parameter C_WACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic\n    parameter C_WDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_WRCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_AXIS_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n\n    // AXI Implementation Type\n    // 1 = Common Clock Block RAM FIFO\n    // 2 = Common Clock Distributed RAM FIFO\n    // 11 = Independent Clock Block RAM FIFO\n    // 12 = Independent Clock Distributed RAM FIFO\n    parameter C_IMPLEMENTATION_TYPE_WACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WRCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_AXIS     = 0,\n\n    // AXI FIFO Type\n    // 0 = Data FIFO\n    // 1 = Packet FIFO\n    // 2 = Low Latency Sync FIFO\n    // 3 = Low Latency Async FIFO\n    parameter C_APPLICATION_TYPE_WACH        = 0,\n    parameter C_APPLICATION_TYPE_WDCH        = 0,\n    parameter C_APPLICATION_TYPE_WRCH        = 0,\n    parameter C_APPLICATION_TYPE_RACH        = 0,\n    parameter C_APPLICATION_TYPE_RDCH        = 0,\n    parameter C_APPLICATION_TYPE_AXIS        = 0,\n\n    // AXI Built-in FIFO Primitive Type\n    // 512x36, 1kx18, 2kx9, 4kx4, etc\n    parameter C_PRIM_FIFO_TYPE_WACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WRCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_AXIS          = \"512x36\",\n\n    // Enable ECC\n    // 0 = ECC disabled\n    // 1 = ECC enabled\n    parameter C_USE_ECC_WACH                 = 0,\n    parameter C_USE_ECC_WDCH                 = 0,\n    parameter C_USE_ECC_WRCH                 = 0,\n    parameter C_USE_ECC_RACH                 = 0,\n    parameter C_USE_ECC_RDCH                 = 0,\n    parameter C_USE_ECC_AXIS                 = 0,\n\n    // ECC Error Injection Type\n    // 0 = No Error Injection\n    // 1 = Single Bit Error Injection\n    // 2 = Double Bit Error Injection\n    // 3 = Single Bit and Double Bit Error Injection\n    parameter C_ERROR_INJECTION_TYPE_WACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WRCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_AXIS    = 0,\n\n    // Input Data Width\n    // Accumulation of all AXI input signal's width\n    parameter C_DIN_WIDTH_WACH               = 1,\n    parameter C_DIN_WIDTH_WDCH               = 1,\n    parameter C_DIN_WIDTH_WRCH               = 1,\n    parameter C_DIN_WIDTH_RACH               = 1,\n    parameter C_DIN_WIDTH_RDCH               = 1,\n    parameter C_DIN_WIDTH_AXIS               = 1,\n\n    parameter C_WR_DEPTH_WACH                = 16,\n    parameter C_WR_DEPTH_WDCH                = 16,\n    parameter C_WR_DEPTH_WRCH                = 16,\n    parameter C_WR_DEPTH_RACH                = 16,\n    parameter C_WR_DEPTH_RDCH                = 16,\n    parameter C_WR_DEPTH_AXIS                = 16,\n\n    parameter C_WR_PNTR_WIDTH_WACH           = 4,\n    parameter C_WR_PNTR_WIDTH_WDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_WRCH           = 4,\n    parameter C_WR_PNTR_WIDTH_RACH           = 4,\n    parameter C_WR_PNTR_WIDTH_RDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_AXIS           = 4,\n\n    parameter C_HAS_DATA_COUNTS_WACH         = 0,\n    parameter C_HAS_DATA_COUNTS_WDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_WRCH         = 0,\n    parameter C_HAS_DATA_COUNTS_RACH         = 0,\n    parameter C_HAS_DATA_COUNTS_RDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_AXIS         = 0,\n\n    parameter C_HAS_PROG_FLAGS_WACH          = 0,\n    parameter C_HAS_PROG_FLAGS_WDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_WRCH          = 0,\n    parameter C_HAS_PROG_FLAGS_RACH          = 0,\n    parameter C_HAS_PROG_FLAGS_RDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_AXIS          = 0,\n\n    parameter C_PROG_FULL_TYPE_WACH          = 0,\n    parameter C_PROG_FULL_TYPE_WDCH          = 0,\n    parameter C_PROG_FULL_TYPE_WRCH          = 0,\n    parameter C_PROG_FULL_TYPE_RACH          = 0,\n    parameter C_PROG_FULL_TYPE_RDCH          = 0,\n    parameter C_PROG_FULL_TYPE_AXIS          = 0,\n\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS      = 0,\n\n    parameter C_PROG_EMPTY_TYPE_WACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WRCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_AXIS         = 0,\n\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS     = 0,\n\n    parameter C_REG_SLICE_MODE_WACH          = 0,\n    parameter C_REG_SLICE_MODE_WDCH          = 0,\n    parameter C_REG_SLICE_MODE_WRCH          = 0,\n    parameter C_REG_SLICE_MODE_RACH          = 0,\n    parameter C_REG_SLICE_MODE_RDCH          = 0,\n    parameter C_REG_SLICE_MODE_AXIS          = 0\n\n    )\n\n   (\n    //------------------------------------------------------------------------------\n    // Input and Output Declarations\n    //------------------------------------------------------------------------------\n\n    // Conventional FIFO Interface Signals\n    input                               backup,\n    input                               backup_marker,\n    input                               clk,\n    input                               rst,\n    input                               srst,\n    input                               wr_clk,\n    input                               wr_rst,\n    input                               rd_clk,\n    input                               rd_rst,\n    input [C_DIN_WIDTH-1:0]             din,\n    input                               wr_en,\n    input                               rd_en,\n    // Optional inputs\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_assert,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_negate,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_assert,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_negate,\n    input                               int_clk,\n    input                               injectdbiterr,\n    input                               injectsbiterr,\n    input                               sleep,\n\n    output [C_DOUT_WIDTH-1:0]           dout,\n    output                              full,\n    output                              almost_full,\n    output                              wr_ack,\n    output                              overflow,\n    output                              empty,\n    output                              almost_empty,\n    output                              valid,\n    output                              underflow,\n    output [C_DATA_COUNT_WIDTH-1:0]     data_count,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]  rd_data_count,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count,\n    output                              prog_full,\n    output                              prog_empty,\n    output                              sbiterr,\n    output                              dbiterr,\n    output                              wr_rst_busy,\n    output                              rd_rst_busy,\n\n\n    // AXI Global Signal\n    input                               m_aclk,\n    input                               s_aclk,\n    input                               s_aresetn,\n    input                               s_aclk_en,\n    input                               m_aclk_en,\n    \n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_awid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_awaddr,\n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_awlen,\n    input [3-1:0]                       s_axi_awsize,\n    input [2-1:0]                       s_axi_awburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_awlock,\n    input [4-1:0]                       s_axi_awcache,\n    input [3-1:0]                       s_axi_awprot,\n    input [4-1:0]                       s_axi_awqos,\n    input [4-1:0]                       s_axi_awregion,\n    input [C_AXI_AWUSER_WIDTH-1:0]      s_axi_awuser,\n    input                               s_axi_awvalid,\n    output                              s_axi_awready,\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_wid,\n    input [C_AXI_DATA_WIDTH-1:0]        s_axi_wdata,\n    input [C_AXI_DATA_WIDTH/8-1:0]      s_axi_wstrb,\n    input                               s_axi_wlast,\n    input [C_AXI_WUSER_WIDTH-1:0]       s_axi_wuser,\n    input                               s_axi_wvalid,\n    output                              s_axi_wready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_bid,\n    output [2-1:0]                      s_axi_bresp,\n    output [C_AXI_BUSER_WIDTH-1:0]      s_axi_buser,\n    output                              s_axi_bvalid,\n    input                               s_axi_bready,\n    \n    // AXI Full/Lite Master Write Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_awid,\n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_awlen,\n    output [3-1:0]                      m_axi_awsize,\n    output [2-1:0]                      m_axi_awburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_awlock,\n    output [4-1:0]                      m_axi_awcache,\n    output [3-1:0]                      m_axi_awprot,\n    output [4-1:0]                      m_axi_awqos,\n    output [4-1:0]                      m_axi_awregion,\n    output [C_AXI_AWUSER_WIDTH-1:0]     m_axi_awuser,\n    output                              m_axi_awvalid,\n    input                               m_axi_awready,\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_wid,\n    output [C_AXI_DATA_WIDTH-1:0]       m_axi_wdata,\n    output [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb,\n    output                              m_axi_wlast,\n    output [C_AXI_WUSER_WIDTH-1:0]      m_axi_wuser,\n    output                              m_axi_wvalid,\n    input                               m_axi_wready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_bid,\n    input [2-1:0]                       m_axi_bresp,\n    input [C_AXI_BUSER_WIDTH-1:0]       m_axi_buser,\n    input                               m_axi_bvalid,\n    output                              m_axi_bready,\n    \n    \n    // AXI Full/Lite Slave Read Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_arid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_araddr, \n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_arlen,\n    input [3-1:0]                       s_axi_arsize,\n    input [2-1:0]                       s_axi_arburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_arlock,\n    input [4-1:0]                       s_axi_arcache,\n    input [3-1:0]                       s_axi_arprot,\n    input [4-1:0]                       s_axi_arqos,\n    input [4-1:0]                       s_axi_arregion,\n    input [C_AXI_ARUSER_WIDTH-1:0]      s_axi_aruser,\n    input                               s_axi_arvalid,\n    output                              s_axi_arready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_rid,       \n    output [C_AXI_DATA_WIDTH-1:0]       s_axi_rdata, \n    output [2-1:0]                      s_axi_rresp,\n    output                              s_axi_rlast,\n    output [C_AXI_RUSER_WIDTH-1:0]      s_axi_ruser,\n    output                              s_axi_rvalid,\n    input                               s_axi_rready,\n    \n    \n    \n    // AXI Full/Lite Master Read Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_arid,        \n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,  \n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_arlen,\n    output [3-1:0]                      m_axi_arsize,\n    output [2-1:0]                      m_axi_arburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_arlock,\n    output [4-1:0]                      m_axi_arcache,\n    output [3-1:0]                      m_axi_arprot,\n    output [4-1:0]                      m_axi_arqos,\n    output [4-1:0]                      m_axi_arregion,\n    output [C_AXI_ARUSER_WIDTH-1:0]     m_axi_aruser,\n    output                              m_axi_arvalid,\n    input                               m_axi_arready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_rid,        \n    input [C_AXI_DATA_WIDTH-1:0]        m_axi_rdata,  \n    input [2-1:0]                       m_axi_rresp,\n    input                               m_axi_rlast,\n    input [C_AXI_RUSER_WIDTH-1:0]       m_axi_ruser,\n    input                               m_axi_rvalid,\n    output                              m_axi_rready,\n    \n    \n    // AXI Streaming Slave Signals (Write side)\n    input                               s_axis_tvalid,\n    output                              s_axis_tready,\n    input [C_AXIS_TDATA_WIDTH-1:0]      s_axis_tdata,\n    input [C_AXIS_TSTRB_WIDTH-1:0]      s_axis_tstrb,\n    input [C_AXIS_TKEEP_WIDTH-1:0]      s_axis_tkeep,\n    input                               s_axis_tlast,\n    input [C_AXIS_TID_WIDTH-1:0]        s_axis_tid,\n    input [C_AXIS_TDEST_WIDTH-1:0]      s_axis_tdest,\n    input [C_AXIS_TUSER_WIDTH-1:0]      s_axis_tuser,\n    \n    // AXI Streaming Master Signals (Read side)\n    output                              m_axis_tvalid,\n    input                               m_axis_tready,\n    output [C_AXIS_TDATA_WIDTH-1:0]     m_axis_tdata,\n    output [C_AXIS_TSTRB_WIDTH-1:0]     m_axis_tstrb,\n    output [C_AXIS_TKEEP_WIDTH-1:0]     m_axis_tkeep,\n    output                              m_axis_tlast,\n    output [C_AXIS_TID_WIDTH-1:0]       m_axis_tid,\n    output [C_AXIS_TDEST_WIDTH-1:0]     m_axis_tdest,\n    output [C_AXIS_TUSER_WIDTH-1:0]     m_axis_tuser,\n    \n           \n    \n    \n    // AXI Full/Lite Write Address Channel signals\n    input                               axi_aw_injectsbiterr,\n    input                               axi_aw_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_rd_data_count,\n    output                              axi_aw_sbiterr,\n    output                              axi_aw_dbiterr,\n    output                              axi_aw_overflow,\n    output                              axi_aw_underflow,\n    output                              axi_aw_prog_full,\n    output                              axi_aw_prog_empty,\n    \n    \n    // AXI Full/Lite Write Data Channel signals\n    input                               axi_w_injectsbiterr,\n    input                               axi_w_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_rd_data_count,\n    output                              axi_w_sbiterr,\n    output                              axi_w_dbiterr,\n    output                              axi_w_overflow,\n    output                              axi_w_underflow,\n    output                              axi_w_prog_full,\n    output                              axi_w_prog_empty,\n    \n    \n    // AXI Full/Lite Write Response Channel signals\n    input                               axi_b_injectsbiterr,\n    input                               axi_b_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_rd_data_count,\n    output                              axi_b_sbiterr,\n    output                              axi_b_dbiterr,\n    output                              axi_b_overflow,\n    output                              axi_b_underflow,\n    output                              axi_b_prog_full,\n    output                              axi_b_prog_empty,\n    \n    \n    \n    // AXI Full/Lite Read Address Channel signals\n    input                               axi_ar_injectsbiterr,\n    input                               axi_ar_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_rd_data_count,\n    output                              axi_ar_sbiterr,\n    output                              axi_ar_dbiterr,\n    output                              axi_ar_overflow,\n    output                              axi_ar_underflow,\n    output                              axi_ar_prog_full,\n    output                              axi_ar_prog_empty,\n\n    \n    // AXI Full/Lite Read Data Channel Signals\n    input                               axi_r_injectsbiterr,\n    input                               axi_r_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_rd_data_count,\n    output                              axi_r_sbiterr,\n    output                              axi_r_dbiterr,\n    output                              axi_r_overflow,\n    output                              axi_r_underflow,\n    output                              axi_r_prog_full,\n    output                              axi_r_prog_empty,\n\n    \n    // AXI Streaming FIFO Related Signals\n    input                               axis_injectsbiterr,\n    input                               axis_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_wr_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_rd_data_count,\n    output                              axis_sbiterr,\n    output                              axis_dbiterr,\n    output                              axis_overflow,\n    output                              axis_underflow,\n    output                              axis_prog_full,\n    output                              axis_prog_empty\n\n    );\n\n    wire                              BACKUP;\n    wire                              BACKUP_MARKER;\n    wire                              CLK;\n    wire                              RST;\n    wire                              SRST;\n    wire                              WR_CLK;\n    wire                              WR_RST;\n    wire                              RD_CLK;\n    wire                              RD_RST;\n    wire [C_DIN_WIDTH-1:0]            DIN;\n    wire                              WR_EN;\n    wire                              RD_EN;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_ASSERT;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_NEGATE;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_ASSERT;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_NEGATE;\n    wire                              INT_CLK;\n    wire                              INJECTDBITERR;\n    wire                              INJECTSBITERR;\n    wire                              SLEEP;\n    wire [C_DOUT_WIDTH-1:0]           DOUT;\n    wire                              FULL;\n    wire                              ALMOST_FULL;\n    wire                              WR_ACK;\n    wire                              OVERFLOW;\n    wire                              EMPTY;\n    wire                              ALMOST_EMPTY;\n    wire                              VALID;\n    wire                              UNDERFLOW;\n    wire [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT;\n    wire [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT;\n    wire                              PROG_FULL;\n    wire                              PROG_EMPTY;\n    wire                              SBITERR;\n    wire                              DBITERR;\n    wire                              WR_RST_BUSY;\n    wire                              RD_RST_BUSY;\n    wire                              M_ACLK;\n    wire                              S_ACLK;\n    wire                              S_ARESETN;\n    wire                              S_ACLK_EN;\n    wire                              M_ACLK_EN;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_AWLEN;\n    wire [3-1:0]                      S_AXI_AWSIZE;\n    wire [2-1:0]                      S_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_AWLOCK;\n    wire [4-1:0]                      S_AXI_AWCACHE;\n    wire [3-1:0]                      S_AXI_AWPROT;\n    wire [4-1:0]                      S_AXI_AWQOS;\n    wire [4-1:0]                      S_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     S_AXI_AWUSER;\n    wire                              S_AXI_AWVALID;\n    wire                              S_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     S_AXI_WSTRB;\n    wire                              S_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      S_AXI_WUSER;\n    wire                              S_AXI_WVALID;\n    wire                              S_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_BID;\n    wire [2-1:0]                      S_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      S_AXI_BUSER;\n    wire                              S_AXI_BVALID;\n    wire                              S_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_AWLEN;\n    wire [3-1:0]                      M_AXI_AWSIZE;\n    wire [2-1:0]                      M_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_AWLOCK;\n    wire [4-1:0]                      M_AXI_AWCACHE;\n    wire [3-1:0]                      M_AXI_AWPROT;\n    wire [4-1:0]                      M_AXI_AWQOS;\n    wire [4-1:0]                      M_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     M_AXI_AWUSER;\n    wire                              M_AXI_AWVALID;\n    wire                              M_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     M_AXI_WSTRB;\n    wire                              M_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      M_AXI_WUSER;\n    wire                              M_AXI_WVALID;\n    wire                              M_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_BID;\n    wire [2-1:0]                      M_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      M_AXI_BUSER;\n    wire                              M_AXI_BVALID;\n    wire                              M_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_ARID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_ARADDR; \n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_ARLEN;\n    wire [3-1:0]                      S_AXI_ARSIZE;\n    wire [2-1:0]                      S_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_ARLOCK;\n    wire [4-1:0]                      S_AXI_ARCACHE;\n    wire [3-1:0]                      S_AXI_ARPROT;\n    wire [4-1:0]                      S_AXI_ARQOS;\n    wire [4-1:0]                      S_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     S_AXI_ARUSER;\n    wire                              S_AXI_ARVALID;\n    wire                              S_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_RID;       \n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_RDATA; \n    wire [2-1:0]                      S_AXI_RRESP;\n    wire                              S_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      S_AXI_RUSER;\n    wire                              S_AXI_RVALID;\n    wire                              S_AXI_RREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_ARID;        \n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_ARADDR;  \n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_ARLEN;\n    wire [3-1:0]                      M_AXI_ARSIZE;\n    wire [2-1:0]                      M_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_ARLOCK;\n    wire [4-1:0]                      M_AXI_ARCACHE;\n    wire [3-1:0]                      M_AXI_ARPROT;\n    wire [4-1:0]                      M_AXI_ARQOS;\n    wire [4-1:0]                      M_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     M_AXI_ARUSER;\n    wire                              M_AXI_ARVALID;\n    wire                              M_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_RID;        \n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_RDATA;  \n    wire [2-1:0]                      M_AXI_RRESP;\n    wire                              M_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      M_AXI_RUSER;\n    wire                              M_AXI_RVALID;\n    wire                              M_AXI_RREADY;\n    wire                              S_AXIS_TVALID;\n    wire                              S_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     S_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     S_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     S_AXIS_TKEEP;\n    wire                              S_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       S_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     S_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     S_AXIS_TUSER;\n    wire                              M_AXIS_TVALID;\n    wire                              M_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     M_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     M_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     M_AXIS_TKEEP;\n    wire                              M_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       M_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     M_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     M_AXIS_TUSER;\n    wire                              AXI_AW_INJECTSBITERR;\n    wire                              AXI_AW_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_RD_DATA_COUNT;\n    wire                              AXI_AW_SBITERR;\n    wire                              AXI_AW_DBITERR;\n    wire                              AXI_AW_OVERFLOW;\n    wire                              AXI_AW_UNDERFLOW;\n    wire                              AXI_AW_PROG_FULL;\n    wire                              AXI_AW_PROG_EMPTY;\n    wire                              AXI_W_INJECTSBITERR;\n    wire                              AXI_W_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_RD_DATA_COUNT;\n    wire                              AXI_W_SBITERR;\n    wire                              AXI_W_DBITERR;\n    wire                              AXI_W_OVERFLOW;\n    wire                              AXI_W_UNDERFLOW;\n    wire                              AXI_W_PROG_FULL;\n    wire                              AXI_W_PROG_EMPTY;\n    wire                              AXI_B_INJECTSBITERR;\n    wire                              AXI_B_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_RD_DATA_COUNT;\n    wire                              AXI_B_SBITERR;\n    wire                              AXI_B_DBITERR;\n    wire                              AXI_B_OVERFLOW;\n    wire                              AXI_B_UNDERFLOW;\n    wire                              AXI_B_PROG_FULL;\n    wire                              AXI_B_PROG_EMPTY;\n    wire                              AXI_AR_INJECTSBITERR;\n    wire                              AXI_AR_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_RD_DATA_COUNT;\n    wire                              AXI_AR_SBITERR;\n    wire                              AXI_AR_DBITERR;\n    wire                              AXI_AR_OVERFLOW;\n    wire                              AXI_AR_UNDERFLOW;\n    wire                              AXI_AR_PROG_FULL;\n    wire                              AXI_AR_PROG_EMPTY;\n    wire                              AXI_R_INJECTSBITERR;\n    wire                              AXI_R_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_RD_DATA_COUNT;\n    wire                              AXI_R_SBITERR;\n    wire                              AXI_R_DBITERR;\n    wire                              AXI_R_OVERFLOW;\n    wire                              AXI_R_UNDERFLOW;\n    wire                              AXI_R_PROG_FULL;\n    wire                              AXI_R_PROG_EMPTY;\n    wire                              AXIS_INJECTSBITERR;\n    wire                              AXIS_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_RD_DATA_COUNT;\n    wire                              AXIS_SBITERR;\n    wire                              AXIS_DBITERR;\n    wire                              AXIS_OVERFLOW;\n    wire                              AXIS_UNDERFLOW;\n    wire                              AXIS_PROG_FULL;\n    wire                              AXIS_PROG_EMPTY;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count_in;\n    wire                              wr_rst_int;\n    wire                              rd_rst_int;\n    wire                              wr_rst_busy_o;\n    wire                              wr_rst_busy_ntve;\n    wire                              wr_rst_busy_axis;\n    wire                              wr_rst_busy_wach;\n    wire                              wr_rst_busy_wdch;\n    wire                              wr_rst_busy_wrch;\n    wire                              wr_rst_busy_rach;\n    wire                              wr_rst_busy_rdch;\n\n\n\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n\n\n\n    // Conventional FIFO Interface Signals\n    assign BACKUP                 = backup;\n    assign BACKUP_MARKER          = backup_marker;\n    assign CLK                    = clk;\n    assign RST                    = rst;\n    assign SRST                   = srst;\n    assign WR_CLK                 = wr_clk;\n    assign WR_RST                 = wr_rst;\n    assign RD_CLK                 = rd_clk;\n    assign RD_RST                 = rd_rst;\n    assign WR_EN                  = wr_en;\n    assign RD_EN                  = rd_en;\n    assign INT_CLK                = int_clk;\n    assign INJECTDBITERR          = injectdbiterr;\n    assign INJECTSBITERR          = injectsbiterr;\n    assign SLEEP                  = sleep;\n    assign full                   = FULL;\n    assign almost_full            = ALMOST_FULL;\n    assign wr_ack                 = WR_ACK;\n    assign overflow               = OVERFLOW;\n    assign empty                  = EMPTY;\n    assign almost_empty           = ALMOST_EMPTY;\n    assign valid                  = VALID;\n    assign underflow              = UNDERFLOW;\n    assign prog_full              = PROG_FULL;\n    assign prog_empty             = PROG_EMPTY;\n    assign sbiterr                = SBITERR;\n    assign dbiterr                = DBITERR;\n//    assign wr_rst_busy            = WR_RST_BUSY | wr_rst_busy_o;\n    assign wr_rst_busy            = wr_rst_busy_o;\n    assign rd_rst_busy            = RD_RST_BUSY;\n    assign M_ACLK                 = m_aclk;\n    assign S_ACLK                 = s_aclk;\n    assign S_ARESETN              = s_aresetn;\n    assign S_ACLK_EN              = s_aclk_en;\n    assign M_ACLK_EN              = m_aclk_en;\n    assign S_AXI_AWVALID          = s_axi_awvalid;\n    assign s_axi_awready          = S_AXI_AWREADY;\n    assign S_AXI_WLAST            = s_axi_wlast;\n    assign S_AXI_WVALID           = s_axi_wvalid;\n    assign s_axi_wready           = S_AXI_WREADY;\n    assign s_axi_bvalid           = S_AXI_BVALID;\n    assign S_AXI_BREADY           = s_axi_bready;\n    assign m_axi_awvalid          = M_AXI_AWVALID;\n    assign M_AXI_AWREADY          = m_axi_awready;\n    assign m_axi_wlast            = M_AXI_WLAST;\n    assign m_axi_wvalid           = M_AXI_WVALID;\n    assign M_AXI_WREADY           = m_axi_wready;\n    assign M_AXI_BVALID           = m_axi_bvalid;\n    assign m_axi_bready           = M_AXI_BREADY;\n    assign S_AXI_ARVALID          = s_axi_arvalid;\n    assign s_axi_arready          = S_AXI_ARREADY;\n    assign s_axi_rlast            = S_AXI_RLAST;\n    assign s_axi_rvalid           = S_AXI_RVALID;\n    assign S_AXI_RREADY           = s_axi_rready;\n    assign m_axi_arvalid          = M_AXI_ARVALID;\n    assign M_AXI_ARREADY          = m_axi_arready;\n    assign M_AXI_RLAST            = m_axi_rlast;\n    assign M_AXI_RVALID           = m_axi_rvalid;\n    assign m_axi_rready           = M_AXI_RREADY;\n    assign S_AXIS_TVALID          = s_axis_tvalid;\n    assign s_axis_tready          = S_AXIS_TREADY;\n    assign S_AXIS_TLAST           = s_axis_tlast;\n    assign m_axis_tvalid          = M_AXIS_TVALID;\n    assign M_AXIS_TREADY          = m_axis_tready;\n    assign m_axis_tlast           = M_AXIS_TLAST;\n    assign AXI_AW_INJECTSBITERR   = axi_aw_injectsbiterr;\n    assign AXI_AW_INJECTDBITERR   = axi_aw_injectdbiterr;\n    assign axi_aw_sbiterr         = AXI_AW_SBITERR;\n    assign axi_aw_dbiterr         = AXI_AW_DBITERR;\n    assign axi_aw_overflow        = AXI_AW_OVERFLOW;\n    assign axi_aw_underflow       = AXI_AW_UNDERFLOW;\n    assign axi_aw_prog_full       = AXI_AW_PROG_FULL;\n    assign axi_aw_prog_empty      = AXI_AW_PROG_EMPTY;\n    assign AXI_W_INJECTSBITERR    = axi_w_injectsbiterr;\n    assign AXI_W_INJECTDBITERR    = axi_w_injectdbiterr;\n    assign axi_w_sbiterr          = AXI_W_SBITERR;\n    assign axi_w_dbiterr          = AXI_W_DBITERR;\n    assign axi_w_overflow         = AXI_W_OVERFLOW;\n    assign axi_w_underflow        = AXI_W_UNDERFLOW;\n    assign axi_w_prog_full        = AXI_W_PROG_FULL;\n    assign axi_w_prog_empty       = AXI_W_PROG_EMPTY;\n    assign AXI_B_INJECTSBITERR    = axi_b_injectsbiterr;\n    assign AXI_B_INJECTDBITERR    = axi_b_injectdbiterr;\n    assign axi_b_sbiterr          = AXI_B_SBITERR;\n    assign axi_b_dbiterr          = AXI_B_DBITERR;\n    assign axi_b_overflow         = AXI_B_OVERFLOW;\n    assign axi_b_underflow        = AXI_B_UNDERFLOW;\n    assign axi_b_prog_full        = AXI_B_PROG_FULL;\n    assign axi_b_prog_empty       = AXI_B_PROG_EMPTY;\n    assign AXI_AR_INJECTSBITERR   = axi_ar_injectsbiterr;\n    assign AXI_AR_INJECTDBITERR   = axi_ar_injectdbiterr;\n    assign axi_ar_sbiterr         = AXI_AR_SBITERR;\n    assign axi_ar_dbiterr         = AXI_AR_DBITERR;\n    assign axi_ar_overflow        = AXI_AR_OVERFLOW;\n    assign axi_ar_underflow       = AXI_AR_UNDERFLOW;\n    assign axi_ar_prog_full       = AXI_AR_PROG_FULL;\n    assign axi_ar_prog_empty      = AXI_AR_PROG_EMPTY;\n    assign AXI_R_INJECTSBITERR    = axi_r_injectsbiterr;\n    assign AXI_R_INJECTDBITERR    = axi_r_injectdbiterr;\n    assign axi_r_sbiterr          = AXI_R_SBITERR;\n    assign axi_r_dbiterr          = AXI_R_DBITERR;\n    assign axi_r_overflow         = AXI_R_OVERFLOW;\n    assign axi_r_underflow        = AXI_R_UNDERFLOW;\n    assign axi_r_prog_full        = AXI_R_PROG_FULL;\n    assign axi_r_prog_empty       = AXI_R_PROG_EMPTY;\n    assign AXIS_INJECTSBITERR     = axis_injectsbiterr;\n    assign AXIS_INJECTDBITERR     = axis_injectdbiterr;\n    assign axis_sbiterr           = AXIS_SBITERR;\n    assign axis_dbiterr           = AXIS_DBITERR;\n    assign axis_overflow          = AXIS_OVERFLOW;\n    assign axis_underflow         = AXIS_UNDERFLOW;\n    assign axis_prog_full         = AXIS_PROG_FULL;\n    assign axis_prog_empty        = AXIS_PROG_EMPTY;\n\n\n    assign DIN                       = din;\n    assign PROG_EMPTY_THRESH         = prog_empty_thresh;\n    assign PROG_EMPTY_THRESH_ASSERT  = prog_empty_thresh_assert;\n    assign PROG_EMPTY_THRESH_NEGATE  = prog_empty_thresh_negate;\n    assign PROG_FULL_THRESH          = prog_full_thresh;\n    assign PROG_FULL_THRESH_ASSERT   = prog_full_thresh_assert;\n    assign PROG_FULL_THRESH_NEGATE   = prog_full_thresh_negate;\n    assign dout                      = DOUT;\n    assign data_count                = DATA_COUNT;\n    assign rd_data_count             = RD_DATA_COUNT;\n    assign wr_data_count             = WR_DATA_COUNT;\n    assign S_AXI_AWID                = s_axi_awid;\n    assign S_AXI_AWADDR              = s_axi_awaddr;\n    assign S_AXI_AWLEN               = s_axi_awlen;\n    assign S_AXI_AWSIZE              = s_axi_awsize;\n    assign S_AXI_AWBURST             = s_axi_awburst;\n    assign S_AXI_AWLOCK              = s_axi_awlock;\n    assign S_AXI_AWCACHE             = s_axi_awcache;\n    assign S_AXI_AWPROT              = s_axi_awprot;\n    assign S_AXI_AWQOS               = s_axi_awqos;\n    assign S_AXI_AWREGION            = s_axi_awregion;\n    assign S_AXI_AWUSER              = s_axi_awuser;\n    assign S_AXI_WID                 = s_axi_wid;\n    assign S_AXI_WDATA               = s_axi_wdata;\n    assign S_AXI_WSTRB               = s_axi_wstrb;\n    assign S_AXI_WUSER               = s_axi_wuser;\n    assign s_axi_bid                 = S_AXI_BID;\n    assign s_axi_bresp               = S_AXI_BRESP;\n    assign s_axi_buser               = S_AXI_BUSER;\n    assign m_axi_awid                = M_AXI_AWID;\n    assign m_axi_awaddr              = M_AXI_AWADDR;\n    assign m_axi_awlen               = M_AXI_AWLEN;\n    assign m_axi_awsize              = M_AXI_AWSIZE;\n    assign m_axi_awburst             = M_AXI_AWBURST;\n    assign m_axi_awlock              = M_AXI_AWLOCK;\n    assign m_axi_awcache             = M_AXI_AWCACHE;\n    assign m_axi_awprot              = M_AXI_AWPROT;\n    assign m_axi_awqos               = M_AXI_AWQOS;\n    assign m_axi_awregion            = M_AXI_AWREGION;\n    assign m_axi_awuser              = M_AXI_AWUSER;\n    assign m_axi_wid                 = M_AXI_WID;\n    assign m_axi_wdata               = M_AXI_WDATA;\n    assign m_axi_wstrb               = M_AXI_WSTRB;\n    assign m_axi_wuser               = M_AXI_WUSER;\n    assign M_AXI_BID                 = m_axi_bid;\n    assign M_AXI_BRESP               = m_axi_bresp;\n    assign M_AXI_BUSER               = m_axi_buser;\n    assign S_AXI_ARID                = s_axi_arid;\n    assign S_AXI_ARADDR              = s_axi_araddr; \n    assign S_AXI_ARLEN               = s_axi_arlen;\n    assign S_AXI_ARSIZE              = s_axi_arsize;\n    assign S_AXI_ARBURST             = s_axi_arburst;\n    assign S_AXI_ARLOCK              = s_axi_arlock;\n    assign S_AXI_ARCACHE             = s_axi_arcache;\n    assign S_AXI_ARPROT              = s_axi_arprot;\n    assign S_AXI_ARQOS               = s_axi_arqos;\n    assign S_AXI_ARREGION            = s_axi_arregion;\n    assign S_AXI_ARUSER              = s_axi_aruser;\n    assign s_axi_rid                 = S_AXI_RID;\n    assign s_axi_rdata               = S_AXI_RDATA;\n    assign s_axi_rresp               = S_AXI_RRESP;\n    assign s_axi_ruser               = S_AXI_RUSER;\n    assign m_axi_arid                = M_AXI_ARID;        \n    assign m_axi_araddr              = M_AXI_ARADDR;  \n    assign m_axi_arlen               = M_AXI_ARLEN;\n    assign m_axi_arsize              = M_AXI_ARSIZE;\n    assign m_axi_arburst             = M_AXI_ARBURST;\n    assign m_axi_arlock              = M_AXI_ARLOCK;\n    assign m_axi_arcache             = M_AXI_ARCACHE;\n    assign m_axi_arprot              = M_AXI_ARPROT;\n    assign m_axi_arqos               = M_AXI_ARQOS;\n    assign m_axi_arregion            = M_AXI_ARREGION;\n    assign m_axi_aruser              = M_AXI_ARUSER;\n    assign M_AXI_RID                 = m_axi_rid;        \n    assign M_AXI_RDATA               = m_axi_rdata;  \n    assign M_AXI_RRESP               = m_axi_rresp;\n    assign M_AXI_RUSER               = m_axi_ruser;\n    assign S_AXIS_TDATA              = s_axis_tdata;\n    assign S_AXIS_TSTRB              = s_axis_tstrb;\n    assign S_AXIS_TKEEP              = s_axis_tkeep;\n    assign S_AXIS_TID                = s_axis_tid;\n    assign S_AXIS_TDEST              = s_axis_tdest;\n    assign S_AXIS_TUSER              = s_axis_tuser;\n    assign m_axis_tdata              = M_AXIS_TDATA;\n    assign m_axis_tstrb              = M_AXIS_TSTRB;\n    assign m_axis_tkeep              = M_AXIS_TKEEP;\n    assign m_axis_tid                = M_AXIS_TID;\n    assign m_axis_tdest              = M_AXIS_TDEST;\n    assign m_axis_tuser              = M_AXIS_TUSER;\n    assign AXI_AW_PROG_FULL_THRESH   = axi_aw_prog_full_thresh;\n    assign AXI_AW_PROG_EMPTY_THRESH  = axi_aw_prog_empty_thresh;\n    assign axi_aw_data_count         = AXI_AW_DATA_COUNT;\n    assign axi_aw_wr_data_count      = AXI_AW_WR_DATA_COUNT;\n    assign axi_aw_rd_data_count      = AXI_AW_RD_DATA_COUNT;\n    assign AXI_W_PROG_FULL_THRESH    = axi_w_prog_full_thresh;\n    assign AXI_W_PROG_EMPTY_THRESH   = axi_w_prog_empty_thresh;\n    assign axi_w_data_count          = AXI_W_DATA_COUNT;\n    assign axi_w_wr_data_count       = AXI_W_WR_DATA_COUNT;\n    assign axi_w_rd_data_count       = AXI_W_RD_DATA_COUNT;\n    assign AXI_B_PROG_FULL_THRESH    = axi_b_prog_full_thresh;\n    assign AXI_B_PROG_EMPTY_THRESH   = axi_b_prog_empty_thresh;\n    assign axi_b_data_count          = AXI_B_DATA_COUNT;\n    assign axi_b_wr_data_count       = AXI_B_WR_DATA_COUNT;\n    assign axi_b_rd_data_count       = AXI_B_RD_DATA_COUNT;\n    assign AXI_AR_PROG_FULL_THRESH   = axi_ar_prog_full_thresh;\n    assign AXI_AR_PROG_EMPTY_THRESH  = axi_ar_prog_empty_thresh;\n    assign axi_ar_data_count         = AXI_AR_DATA_COUNT;\n    assign axi_ar_wr_data_count      = AXI_AR_WR_DATA_COUNT;\n    assign axi_ar_rd_data_count      = AXI_AR_RD_DATA_COUNT;\n    assign AXI_R_PROG_FULL_THRESH    = axi_r_prog_full_thresh;\n    assign AXI_R_PROG_EMPTY_THRESH   = axi_r_prog_empty_thresh;\n    assign axi_r_data_count          = AXI_R_DATA_COUNT;\n    assign axi_r_wr_data_count       = AXI_R_WR_DATA_COUNT;\n    assign axi_r_rd_data_count       = AXI_R_RD_DATA_COUNT;\n    assign AXIS_PROG_FULL_THRESH     = axis_prog_full_thresh;\n    assign AXIS_PROG_EMPTY_THRESH    = axis_prog_empty_thresh;\n    assign axis_data_count           = AXIS_DATA_COUNT;\n    assign axis_wr_data_count        = AXIS_WR_DATA_COUNT;\n    assign axis_rd_data_count        = AXIS_RD_DATA_COUNT;\n\n\n  generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_COMMON_CLOCK \t\t(C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DATA_COUNT_WIDTH\t\t(C_DATA_COUNT_WIDTH),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH),\n        .C_DOUT_RST_VAL\t\t\t(C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),\n        .C_DOUT_WIDTH\t\t\t(C_DOUT_WIDTH),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n        .C_HAS_ALMOST_EMPTY\t\t(C_HAS_ALMOST_EMPTY),\n        .C_HAS_ALMOST_FULL\t\t(C_HAS_ALMOST_FULL),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_DATA_COUNT\t\t(C_HAS_DATA_COUNT),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_HAS_RD_DATA_COUNT\t\t(C_HAS_RD_DATA_COUNT),\n        .C_HAS_RD_RST\t\t\t(C_HAS_RD_RST),\n        .C_HAS_RST\t\t\t(C_HAS_RST),\n        .C_HAS_SRST\t\t\t(C_HAS_SRST),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_HAS_VALID\t\t\t(C_HAS_VALID),\n        .C_HAS_WR_ACK\t\t\t(C_HAS_WR_ACK),\n        .C_HAS_WR_DATA_COUNT\t\t(C_HAS_WR_DATA_COUNT),\n        .C_HAS_WR_RST\t\t\t(C_HAS_WR_RST),\n        .C_IMPLEMENTATION_TYPE\t\t(C_IMPLEMENTATION_TYPE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_MEMORY_TYPE\t\t\t(C_MEMORY_TYPE),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n        .C_PRELOAD_LATENCY\t\t(C_PRELOAD_LATENCY),\n        .C_PRELOAD_REGS\t\t\t(C_PRELOAD_REGS),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL),\n        .C_PROG_EMPTY_THRESH_NEGATE_VAL\t(C_PROG_EMPTY_THRESH_NEGATE_VAL),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL),\n        .C_PROG_FULL_THRESH_NEGATE_VAL\t(C_PROG_FULL_THRESH_NEGATE_VAL),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_RD_DATA_COUNT_WIDTH),\n        .C_RD_DEPTH\t\t\t(C_RD_DEPTH),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_RD_PNTR_WIDTH\t\t(C_RD_PNTR_WIDTH),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n        .C_USE_ECC                      (C_USE_ECC),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_EN_SAFETY_CKT\t\t(C_EN_SAFETY_CKT),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_USE_FWFT_DATA_COUNT\t\t(C_USE_FWFT_DATA_COUNT),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_DATA_COUNT_WIDTH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (C_ENABLE_RST_SYNC),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE),\n        .C_AXI_TYPE                     (C_AXI_TYPE),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE)\n      )\n    fifo_generator_v13_2_5_conv_dut\n      (\n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .CLK                      (CLK),\n        .RST                      (RST),\n        .SRST                     (SRST),\n        .WR_CLK                   (WR_CLK),\n        .WR_RST                   (WR_RST),\n        .RD_CLK                   (RD_CLK),\n        .RD_RST                   (RD_RST),\n        .DIN                      (DIN),\n        .WR_EN                    (WR_EN),\n        .RD_EN                    (RD_EN),\n        .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),\n        .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),\n        .PROG_FULL_THRESH         (PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),\n        .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),\n        .INT_CLK                  (INT_CLK),\n        .INJECTDBITERR            (INJECTDBITERR), \n        .INJECTSBITERR            (INJECTSBITERR),\n  \n        .DOUT                     (DOUT),\n        .FULL                     (FULL),\n        .ALMOST_FULL              (ALMOST_FULL),\n        .WR_ACK                   (WR_ACK),\n        .OVERFLOW                 (OVERFLOW),\n        .EMPTY                    (EMPTY),\n        .ALMOST_EMPTY             (ALMOST_EMPTY),\n        .VALID                    (VALID),\n        .UNDERFLOW                (UNDERFLOW),\n        .DATA_COUNT               (DATA_COUNT),\n        .RD_DATA_COUNT            (RD_DATA_COUNT),\n        .WR_DATA_COUNT            (wr_data_count_in),\n        .PROG_FULL                (PROG_FULL),\n        .PROG_EMPTY               (PROG_EMPTY),\n        .SBITERR                  (SBITERR),\n        .DBITERR                  (DBITERR),\n        .wr_rst_busy_o            (wr_rst_busy_o),\n        .wr_rst_busy              (wr_rst_busy_i),\n        .rd_rst_busy              (rd_rst_busy),\n        .wr_rst_i_out             (wr_rst_int),\n        .rd_rst_i_out             (rd_rst_int)\n       );\n  end endgenerate\n\n\n\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n  localparam C_AXI_SIZE_WIDTH   = 3;\n  localparam C_AXI_BURST_WIDTH  = 2;\n  localparam C_AXI_CACHE_WIDTH  = 4;\n  localparam C_AXI_PROT_WIDTH   = 3;\n  localparam C_AXI_QOS_WIDTH    = 4;\n  localparam C_AXI_REGION_WIDTH = 4;\n  localparam C_AXI_BRESP_WIDTH  = 2;\n  localparam C_AXI_RRESP_WIDTH  = 2;\n\n  localparam IS_AXI_STREAMING  = C_INTERFACE_TYPE == 1 ? 1 : 0;\n  localparam TDATA_OFFSET      = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;\n  localparam TSTRB_OFFSET      = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;\n  localparam TKEEP_OFFSET      = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;\n  localparam TID_OFFSET        = C_HAS_AXIS_TID   == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;\n  localparam TDEST_OFFSET      = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;\n  localparam TUSER_OFFSET      = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;\n  localparam LOG_DEPTH_AXIS    = find_log2(C_WR_DEPTH_AXIS); \n  localparam LOG_WR_DEPTH      = find_log2(C_WR_DEPTH); \n\n\n  function [LOG_DEPTH_AXIS-1:0] bin2gray;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      begin\n         bin2gray = x ^ (x>>1);\n      end\n   endfunction\n\n  function [LOG_DEPTH_AXIS-1:0] gray2bin;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      integer                i;\n      begin\n         gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];\n         for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin\n            gray2bin[i] =  gray2bin[i+1] ^ x[i];\n         end\n      end\n   endfunction\n\nwire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;\nwire  [LOG_WR_DEPTH-1 : 0]  w_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;\nreg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;\nwire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;\nwire [LOG_WR_DEPTH : 0] r_inv_pad;\nwire [LOG_WR_DEPTH-1 : 0] d_cnt;\nreg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;\nreg adj_w_cnt_rd_pad_0 = 0;\nreg r_inv_pad_0 = 0;\n\n\n   genvar l;\n\n   generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (LOG_WR_DEPTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_int), \n         .CLK      (RD_CLK), \n         .DIN      (w_q[l-1]), \n         .DOUT     (w_q[l])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter\n    assign wr_eop_ad = WR_EN & !(FULL);\n    assign rd_eop_ad = RD_EN & !(EMPTY);\n\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt    <= 1'b0;\n      else if (wr_eop_ad)\n        w_cnt    <= w_cnt + 1;\n    end\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt_gc    <= 1'b0;\n      else \n        w_cnt_gc    <= bin2gray(w_cnt);\n    end\n\n\n    assign  w_q[0]  = w_cnt_gc;\n    assign  w_cnt_gc_asreg_last       = w_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        w_cnt_rd    <= 1'b0;\n      else \n        w_cnt_rd    <= gray2bin(w_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        r_cnt    <= 1'b0;\n      else if (rd_eop_ad)\n        r_cnt    <= r_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;\n   assign r_inv_pad[LOG_WR_DEPTH : 1]        = ~r_cnt;\n   assign adj_w_cnt_rd_pad[0]                = adj_w_cnt_rd_pad_0;\n   assign r_inv_pad[0]                       = r_inv_pad_0;\n\n\n  always @ ( rd_eop_ad )\n    begin\n      if (!rd_eop_ad) begin\n        adj_w_cnt_rd_pad_0    <= 1'b1;\n        r_inv_pad_0           <= 1'b1;\n      end else begin \n        adj_w_cnt_rd_pad_0    <= 1'b0;\n        r_inv_pad_0           <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        d_cnt_pad    <= 1'b0;\n      else \n        d_cnt_pad    <= adj_w_cnt_rd_pad + r_inv_pad ;\n    end\n\n   assign  d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;\n   assign  WR_DATA_COUNT = d_cnt;\n\n  end endgenerate // fifo_ic_adapter\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter\n   assign  WR_DATA_COUNT = wr_data_count_in;\n\n  end endgenerate // fifo_icn_adapter\n\n\n\n  wire                          inverted_reset = ~S_ARESETN;\n  wire                          axi_rs_rst;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_din          ;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_dout         ;\n  wire                          axis_full         ;\n  wire                          axis_almost_full  ;\n  wire                          axis_empty        ;\n  wire                          axis_s_axis_tready;\n  wire                          axis_m_axis_tvalid;\n  wire                          axis_wr_en        ;\n  wire                          axis_rd_en        ;\n  wire                          axis_we           ;\n  wire                          axis_re           ;\n  wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;\n  reg                           axis_pkt_read = 1'b0;\n  wire                          axis_rd_rst;\n  wire                          axis_wr_rst;\n\n  generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||\n               C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst\n      reg                           rst_d1 = 0        ;\n      reg                           rst_d2 = 0        ;\n      reg [3:0]                    axi_rst = 4'h0     ;\n      always @ (posedge inverted_reset or posedge S_ACLK) begin\n        if (inverted_reset) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          axi_rst        <= 4'hf;\n        end else begin\n          rst_d1         <= #`TCQ 1'b0;\n          rst_d2         <= #`TCQ rst_d1;\n          axi_rst        <= #`TCQ {axi_rst[2:0],1'b0};\n        end\n      end\n\n      assign axi_rs_rst = axi_rst[3];//rst_d2;\n  end endgenerate // gaxi_rs_rst\n\n  generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming\n\n    // Write protection when almost full or prog_full is high\n    assign axis_we    = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : \n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign axis_re    = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :\n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? axis_we & S_ACLK_EN : axis_we;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE               (C_INTERFACE_TYPE),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 2  || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_AXIS),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_AXIS),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),\n        .C_USE_ECC                      (C_USE_ECC_AXIS),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_AXIS),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_axis_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (axis_wr_en),\n        .RD_EN                    (axis_rd_en),\n        .PROG_FULL_THRESH         (AXIS_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXIS_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .INJECTDBITERR            (AXIS_INJECTDBITERR), \n        .INJECTSBITERR            (AXIS_INJECTSBITERR),\n  \n        .DIN                      (axis_din),\n        .DOUT                     (axis_dout),\n        .FULL                     (axis_full),\n        .EMPTY                    (axis_empty),\n        .ALMOST_FULL              (axis_almost_full),\n        .PROG_FULL                (AXIS_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXIS_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (AXIS_OVERFLOW),\n        .VALID                    (),\n        .UNDERFLOW                (AXIS_UNDERFLOW),\n        .DATA_COUNT               (axis_dc),\n        .RD_DATA_COUNT            (AXIS_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXIS_WR_DATA_COUNT),\n        .SBITERR                  (AXIS_SBITERR),\n        .DBITERR                  (AXIS_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_axis),\n        .rd_rst_busy              (rd_rst_busy_axis),\n        .wr_rst_i_out             (axis_wr_rst),\n        .rd_rst_i_out             (axis_rd_rst),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign axis_s_axis_tready    = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;\n    assign axis_m_axis_tvalid    = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;\n    assign S_AXIS_TREADY         = axis_s_axis_tready;\n    assign M_AXIS_TVALID         = axis_m_axis_tvalid;\n\n  end endgenerate // axi_streaming\n\n  wire axis_wr_eop;\n  reg  axis_wr_eop_d1 = 1'b0;\n  wire axis_rd_eop;\n  integer  axis_pkt_cnt;\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)\n        axis_pkt_read    <= 1'b0;\n      else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_wr_eop_d1    <= 1'b0;\n      else\n        axis_wr_eop_d1   <= axis_wr_eop;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_cnt    <= 0;\n      else if (axis_wr_eop_d1 && ~axis_rd_eop)\n        axis_pkt_cnt    <= axis_pkt_cnt + 1;\n      else if (axis_rd_eop && ~axis_wr_eop_d1)\n        axis_pkt_cnt    <= axis_pkt_cnt - 1;\n    end\n  end endgenerate // gaxis_pkt_fifo_cc\n\n\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;\nwire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;\nwire axis_rd_has_rst;\nwire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;\nwire  [LOG_DEPTH_AXIS-1 : 0]  wpkt_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;\nwire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;\nwire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;\nwire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;\nwire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;\nreg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;\nreg adj_axis_wpkt_cnt_rd_pad_0 = 0;\nreg rpkt_inv_pad_0 = 0;\nwire axis_af_rd ;\n\ngenerate if (C_HAS_RST == 1) begin : rst_blk_has\n  assign axis_rd_has_rst = axis_rd_rst;\nend endgenerate //rst_blk_has\n\ngenerate if (C_HAS_RST == 0) begin :rst_blk_no\n  assign axis_rd_has_rst = 1'b0;\nend endgenerate //rst_blk_no\n\n   genvar i;\n\n   generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (LOG_DEPTH_AXIS)\n        )\n     rd_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (wpkt_q[i-1]), \n         .DOUT     (wpkt_q[i])\n        );\n \n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (1)\n        )\n     wr_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (axis_af_q[i-1]), \n         .DOUT     (axis_af_q[i])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (diff_pkt_cnt == 1))\n        axis_pkt_read    <= 1'b0;\n      else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt    <= 1'b0;\n      else if (axis_wr_eop)\n        axis_wpkt_cnt    <= axis_wpkt_cnt + 1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt_gc    <= 1'b0;\n      else \n        axis_wpkt_cnt_gc    <= bin2gray(axis_wpkt_cnt);\n    end\n\n\n    assign  wpkt_q[0]  = axis_wpkt_cnt_gc;\n    assign  axis_wpkt_cnt_gc_asreg_last       = wpkt_q[C_SYNCHRONIZER_STAGE];\n    assign  axis_af_q[0]                      = axis_almost_full;\n    //assign  axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];\n    assign  axis_af_rd                        = axis_af_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_wpkt_cnt_rd    <= 1'b0;\n      else \n        axis_wpkt_cnt_rd    <= gray2bin(axis_wpkt_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_rpkt_cnt    <= 1'b0;\n      else if (axis_rd_eop)\n        axis_rpkt_cnt    <= axis_rpkt_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;\n   assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1]             = ~axis_rpkt_cnt;\n   assign adj_axis_wpkt_cnt_rd_pad[0]                                = adj_axis_wpkt_cnt_rd_pad_0;\n   assign rpkt_inv_pad[0]                                            = rpkt_inv_pad_0;\n\n\n  always @ ( axis_rd_eop )\n    begin\n      if (!axis_rd_eop) begin\n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b1;\n        rpkt_inv_pad_0                <= 1'b1;\n      end else begin \n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b0;\n        rpkt_inv_pad_0                <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        diff_pkt_cnt_pad    <= 1'b0;\n      else \n        diff_pkt_cnt_pad    <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;\n    end\n\n   assign  diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;\n\n\n\n\n\n   end endgenerate // gaxis_pkt_fifo_ic\n\n\n\n\n  // Generate the accurate data count for axi stream packet fifo configuration\n  reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_dc_pkt_fifo <= 0;\n      else if (axis_wr_en && (~axis_rd_en))\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;\n      else if (~axis_wr_en && axis_rd_en)\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;\n    end\n    assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;\n  end endgenerate // gdc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt\n    assign AXIS_DATA_COUNT = 0;\n  end endgenerate // gndc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc\n    assign AXIS_DATA_COUNT = axis_dc;\n  end endgenerate // gdc\n\n  // Register Slice for Write Address Channel\n  generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_AXIS),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_AXIS)\n            )\n    axis_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (axis_din),\n          .S_VALID                   (axis_wr_en),\n          .S_READY                   (S_AXIS_TREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (axis_dout),\n          .M_VALID                   (M_AXIS_TVALID),\n          .M_READY                   (axis_rd_en)\n          );\n  end endgenerate // gaxis_reg_slice\n\n\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata\n    assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;\n    assign M_AXIS_TDATA   = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb\n    assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;\n    assign M_AXIS_TSTRB   = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep\n    assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;\n    assign M_AXIS_TKEEP   = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid\n    assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;\n    assign M_AXIS_TID     = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest\n    assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;\n    assign M_AXIS_TDEST   = axis_dout[TID_OFFSET-1:TDEST_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser\n    assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;\n    assign M_AXIS_TUSER   = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast\n    assign axis_din[0] = S_AXIS_TLAST;\n    assign M_AXIS_TLAST   = axis_dout[0];\n  end endgenerate\n\n  //###########################################################################\n  //  AXI FULL Write Channel (axi_write_channel)\n  //###########################################################################\n\n  localparam IS_AXI_FULL       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;\n  localparam IS_AXI_LITE       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;\n\n  localparam IS_AXI_FULL_WACH  = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WDCH  = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WRCH  = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RACH  = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RDCH  = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_AXI_LITE_WACH  = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WDCH  = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WRCH  = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RACH  = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RDCH  = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_WR_ADDR_CH     = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;\n  localparam IS_WR_DATA_CH     = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;\n  localparam IS_WR_RESP_CH     = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;\n  localparam IS_RD_ADDR_CH     = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;\n  localparam IS_RD_DATA_CH     = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;\n\n  localparam AWID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;\n  localparam AWADDR_OFFSET     = AWID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam AWLEN_OFFSET      = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;\n  localparam AWSIZE_OFFSET     = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;\n  localparam AWBURST_OFFSET    = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;\n  localparam AWLOCK_OFFSET     = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;\n  localparam AWCACHE_OFFSET    = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;\n  localparam AWPROT_OFFSET     = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam AWQOS_OFFSET      = AWPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam AWREGION_OFFSET   = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;\n  localparam AWUSER_OFFSET     = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;\n\n  localparam WID_OFFSET        = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;\n  localparam WDATA_OFFSET      = WID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam WSTRB_OFFSET      = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;\n  localparam WUSER_OFFSET      = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;\n\n  localparam BID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;\n  localparam BRESP_OFFSET      = BID_OFFSET - C_AXI_BRESP_WIDTH;\n  localparam BUSER_OFFSET      = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;\n\n\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_din          ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout         ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout_pkt     ;\n  wire                          wach_full         ;\n  wire                          wach_almost_full  ;\n  wire                          wach_prog_full    ;\n  wire                          wach_empty        ;\n  wire                          wach_almost_empty ;\n  wire                          wach_prog_empty   ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_din          ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_dout         ;\n  wire                          wdch_full         ;\n  wire                          wdch_almost_full  ;\n  wire                          wdch_prog_full    ;\n  wire                          wdch_empty        ;\n  wire                          wdch_almost_empty ;\n  wire                          wdch_prog_empty   ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_din          ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_dout         ;\n  wire                          wrch_full         ;\n  wire                          wrch_almost_full  ;\n  wire                          wrch_prog_full    ;\n  wire                          wrch_empty        ;\n  wire                          wrch_almost_empty ;\n  wire                          wrch_prog_empty   ;\n  wire                          axi_aw_underflow_i;\n  wire                          axi_w_underflow_i ;\n  wire                          axi_b_underflow_i ;\n  wire                          axi_aw_overflow_i ;\n  wire                          axi_w_overflow_i  ;\n  wire                          axi_b_overflow_i  ;\n  wire                          axi_wr_underflow_i;\n  wire                          axi_wr_overflow_i ;\n  wire                          wach_s_axi_awready;\n  wire                          wach_m_axi_awvalid;\n  wire                          wach_wr_en        ;\n  wire                          wach_rd_en        ;\n  wire                          wdch_s_axi_wready ;\n  wire                          wdch_m_axi_wvalid ;\n  wire                          wdch_wr_en        ;\n  wire                          wdch_rd_en        ;\n  wire                          wrch_s_axi_bvalid ;\n  wire                          wrch_m_axi_bready ;\n  wire                          wrch_wr_en        ;\n  wire                          wrch_rd_en        ;\n  wire                          txn_count_up      ;\n  wire                          txn_count_down    ;\n  wire                          awvalid_en        ;\n  wire                          awvalid_pkt       ;\n  wire                          awready_pkt       ;\n  integer                       wr_pkt_count      ;\n  wire                          wach_we           ;\n  wire                          wach_re           ;\n  wire                          wdch_we           ;\n  wire                          wdch_re           ;\n  wire                          wrch_we           ;\n  wire                          wrch_re           ;\n\n  generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel\n    // Write protection when almost full or prog_full is high\n    assign wach_we    = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wach_re    = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        wach_m_axi_awvalid & awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY && wach_m_axi_awvalid :\n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY : 1'b0;\n    assign wach_wr_en = (C_HAS_SLAVE_CE == 1)  ? wach_we & S_ACLK_EN : wach_we;\n    assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 2  || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),\n        .C_USE_ECC                      (C_USE_ECC_WACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wach_wr_en),\n        .RD_EN                    (wach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AW_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AW_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AW_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AW_INJECTSBITERR),\n  \n        .DIN                      (wach_din),\n        .DOUT                     (wach_dout_pkt),\n        .FULL                     (wach_full),\n        .EMPTY                    (wach_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_AW_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_AW_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_aw_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_aw_underflow_i),\n        .DATA_COUNT               (AXI_AW_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AW_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AW_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AW_SBITERR),\n        .DBITERR                  (AXI_AW_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wach),\n        .rd_rst_busy              (rd_rst_busy_wach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wach_s_axi_awready    = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;\n    assign wach_m_axi_awvalid   = ~wach_empty;\n    assign S_AXI_AWREADY        = wach_s_axi_awready;\n\n    assign AXI_AW_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;\n    assign AXI_AW_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_aw_overflow_i  : 0;\n\n  end endgenerate // axi_write_address_channel\n\n  // Register Slice for Write Address Channel\n  generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WACH)\n            )\n    wach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_din),\n          .S_VALID                   (S_AXI_AWVALID),\n          .S_READY                   (S_AXI_AWREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n  end endgenerate // gwach_reg_slice\n  \n  generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (1)\n            )\n    wach_pkt_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_dout_pkt),\n          .S_VALID                   (awvalid_pkt),\n          .S_READY                   (awready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n\n    assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;\n\n    assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; \n    assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset == 1) begin\n\twr_pkt_count <= 0;\n      end else begin\n\tif(txn_count_up == 1 && txn_count_down == 0) begin\n\t  wr_pkt_count <= wr_pkt_count + 1;\n\tend else if(txn_count_up == 0 && txn_count_down == 1) begin\n\t  wr_pkt_count <= wr_pkt_count - 1;\n\tend\n      end\n    end //Always end\n    assign awvalid_en = (wr_pkt_count > 0)?1:0;\n  end endgenerate\n  \n  generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr\n    assign awvalid_en    = 1;    \n    assign wach_dout     = wach_dout_pkt;\n    assign M_AXI_AWVALID = wach_m_axi_awvalid;\n  end\n  endgenerate\n\n\n\n  generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel\n    // Write protection when almost full or prog_full is high\n    assign wdch_we    = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wdch_re    = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;\n    assign wdch_wr_en = (C_HAS_SLAVE_CE == 1)  ? wdch_we & S_ACLK_EN : wdch_we;\n    assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;\n\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 2  || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),\n        .C_USE_ECC                      (C_USE_ECC_WDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wdch_wr_en),\n        .RD_EN                    (wdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_W_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_W_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_W_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_W_INJECTSBITERR),\n  \n        .DIN                      (wdch_din),\n        .DOUT                     (wdch_dout),\n        .FULL                     (wdch_full),\n        .EMPTY                    (wdch_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_W_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_W_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_w_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_w_underflow_i),\n        .DATA_COUNT               (AXI_W_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_W_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_W_WR_DATA_COUNT),\n        .SBITERR                  (AXI_W_SBITERR),\n        .DBITERR                  (AXI_W_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wdch),\n        .rd_rst_busy              (rd_rst_busy_wdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wdch_s_axi_wready     = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;\n    assign wdch_m_axi_wvalid = ~wdch_empty;\n    assign S_AXI_WREADY      = wdch_s_axi_wready;\n    assign M_AXI_WVALID      = wdch_m_axi_wvalid;\n\n    assign AXI_W_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i  : 0;\n    assign AXI_W_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_w_overflow_i   : 0;\n\n  end endgenerate // axi_write_data_channel\n\n  // Register Slice for Write Data Channel\n  generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WDCH)\n            )\n    wdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wdch_din),\n          .S_VALID                   (S_AXI_WVALID),\n          .S_READY                   (S_AXI_WREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wdch_dout),\n          .M_VALID                   (M_AXI_WVALID),\n          .M_READY                   (M_AXI_WREADY)\n          );\n  end endgenerate // gwdch_reg_slice\n\n  generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel\n    // Write protection when almost full or prog_full is high\n    assign wrch_we    = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wrch_re    = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;\n    assign wrch_wr_en = (C_HAS_MASTER_CE == 1)  ? wrch_we & M_ACLK_EN : wrch_we;\n    assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 2  || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WRCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WRCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),\n        .C_USE_ECC                      (C_USE_ECC_WRCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WRCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WRCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_wrch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wrch_wr_en),\n        .RD_EN                    (wrch_rd_en),\n        .PROG_FULL_THRESH         (AXI_B_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_B_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .INJECTDBITERR            (AXI_B_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_B_INJECTSBITERR),\n  \n        .DIN                      (wrch_din),\n        .DOUT                     (wrch_dout),\n        .FULL                     (wrch_full),\n        .EMPTY                    (wrch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_B_PROG_FULL),\n        .PROG_EMPTY               (AXI_B_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_b_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_b_underflow_i),\n        .DATA_COUNT               (AXI_B_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_B_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_B_WR_DATA_COUNT),\n        .SBITERR                  (AXI_B_SBITERR),\n        .DBITERR                  (AXI_B_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wrch),\n        .rd_rst_busy              (rd_rst_busy_wrch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wrch_s_axi_bvalid = ~wrch_empty;\n    assign wrch_m_axi_bready     = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;\n    assign S_AXI_BVALID      = wrch_s_axi_bvalid;\n    assign M_AXI_BREADY      = wrch_m_axi_bready;\n\n    assign AXI_B_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i  : 0;\n    assign AXI_B_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_b_overflow_i   : 0;\n  end endgenerate // axi_write_resp_channel\n\n  // Register Slice for Write Response Channel\n  generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WRCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WRCH)\n            )\n    wrch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wrch_din),\n          .S_VALID                   (M_AXI_BVALID),\n          .S_READY                   (M_AXI_BREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wrch_dout),\n          .M_VALID                   (S_AXI_BVALID),\n          .M_READY                   (S_AXI_BREADY)\n          );\n  end endgenerate // gwrch_reg_slice\n\n\n    assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW  == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;\n    assign axi_wr_overflow_i  = C_USE_COMMON_OVERFLOW   == 1 ? (axi_aw_overflow_i  || axi_w_overflow_i  || axi_b_overflow_i)  : 0;\n\n  generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output\n    assign M_AXI_AWADDR    = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];    \n    assign M_AXI_AWLEN     = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];    \n    assign M_AXI_AWSIZE    = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];    \n    assign M_AXI_AWBURST   = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];    \n    assign M_AXI_AWLOCK    = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];    \n    assign M_AXI_AWCACHE   = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];    \n    assign M_AXI_AWQOS     = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];    \n    assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET]    = S_AXI_AWADDR;\n    assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET]   = S_AXI_AWLEN;\n    assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET]   = S_AXI_AWSIZE;\n    assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;\n    assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;\n    assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;\n    assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;\n    assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET]   = S_AXI_AWQOS;\n  end endgenerate // axi_wach_output\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion\n    assign M_AXI_AWREGION  = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];    \n  end endgenerate // axi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion\n    assign M_AXI_AWREGION  = 0;    \n  end endgenerate // naxi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser\n    assign M_AXI_AWUSER  = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];    \n  end endgenerate // axi_awuser\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser\n    assign M_AXI_AWUSER  = 0;    \n  end endgenerate // naxi_awuser\n\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid\n    assign M_AXI_AWID      = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];\n  end endgenerate //axi_awid\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid\n    assign M_AXI_AWID      = 0;\n  end endgenerate //naxi_awid\n\n  generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output\n    assign M_AXI_WDATA     = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n    assign M_AXI_WLAST     = wdch_dout[0];\n    assign wdch_din[WID_OFFSET-1:WDATA_OFFSET]   = S_AXI_WDATA;\n    assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;\n    assign wdch_din[0]   = S_AXI_WLAST;\n  end endgenerate // axi_wdch_output\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin\n    assign M_AXI_WID       = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];\n  end endgenerate\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin\n    assign M_AXI_WID       = 0;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin\n    assign M_AXI_WUSER     = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];    \n  end endgenerate\n  generate if (C_HAS_AXI_WUSER == 0) begin\n    assign M_AXI_WUSER       = 0;\n  end endgenerate\n\n  generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output\n    assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; \n    assign wrch_din[BID_OFFSET-1:BRESP_OFFSET]   = M_AXI_BRESP;\n  end endgenerate // axi_wrch_output\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser\n    assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];\n  end endgenerate // axi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser\n    assign S_AXI_BUSER = 0;\n  end endgenerate // naxi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid\n    assign S_AXI_BID   =  wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];\n  end endgenerate // axi_bid\n  \n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid\n    assign S_AXI_BID   =  0 ;\n  end endgenerate // naxi_bid  \n\n\n  generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1\n    assign wach_din        = {S_AXI_AWADDR, S_AXI_AWPROT};\n    assign M_AXI_AWADDR    = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];    \n  end endgenerate // axi_wach_output1\n\n  generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1\n    assign wdch_din        = {S_AXI_WDATA, S_AXI_WSTRB};\n    assign M_AXI_WDATA     = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n  end endgenerate // axi_wdch_output1\n\n  generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1\n    assign wrch_din        = M_AXI_BRESP;\n    assign S_AXI_BRESP     = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; \n  end endgenerate // axi_wrch_output1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1\n    assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET]     = S_AXI_AWUSER;\n  end endgenerate // gwach_din1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2\n    assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET]     = S_AXI_AWID;\n  end endgenerate // gwach_din2\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3\n    assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET]     = S_AXI_AWREGION;\n  end endgenerate // gwach_din3\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1\n    assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;\n  end endgenerate // gwdch_din1\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2\n    assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;\n  end endgenerate // gwdch_din2\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1\n    assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET]    = M_AXI_BUSER;\n  end endgenerate // gwrch_din1\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2\n    assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET]    = M_AXI_BID;\n  end endgenerate // gwrch_din2\n\n  //end of  axi_write_channel\n\n  //###########################################################################\n  //  AXI FULL Read Channel (axi_read_channel)\n  //###########################################################################\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_din            ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout           ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout_pkt       ;\n  wire                               rach_full           ;\n  wire                               rach_almost_full    ;\n  wire                               rach_prog_full      ;\n  wire                               rach_empty          ;\n  wire                               rach_almost_empty   ;\n  wire                               rach_prog_empty     ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_din            ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_dout           ;\n  wire                               rdch_full           ;\n  wire                               rdch_almost_full    ;\n  wire                               rdch_prog_full      ;\n  wire                               rdch_empty          ;\n  wire                               rdch_almost_empty   ;\n  wire                               rdch_prog_empty     ;\n  wire                               axi_ar_underflow_i  ;\n  wire                               axi_r_underflow_i   ;\n  wire                               axi_ar_overflow_i   ;\n  wire                               axi_r_overflow_i    ;\n  wire                               axi_rd_underflow_i  ;\n  wire                               axi_rd_overflow_i   ;\n  wire                               rach_s_axi_arready  ;\n  wire                               rach_m_axi_arvalid  ;\n  wire                               rach_wr_en          ;\n  wire                               rach_rd_en          ;\n  wire                               rdch_m_axi_rready   ;\n  wire                               rdch_s_axi_rvalid   ;\n  wire                               rdch_wr_en          ;\n  wire                               rdch_rd_en          ;\n  wire                               arvalid_pkt         ;\n  wire                               arready_pkt         ;\n  wire                               arvalid_en          ;\n  wire                               rdch_rd_ok          ;\n  wire                               accept_next_pkt     ;\n  integer                            rdch_free_space     ;\n  integer                            rdch_commited_space ;\n  wire                               rach_we             ;\n  wire                               rach_re             ;\n  wire                               rdch_we             ;\n  wire                               rdch_re             ;\n\n  localparam ARID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;\n  localparam ARADDR_OFFSET     = ARID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam ARLEN_OFFSET      = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;\n  localparam ARSIZE_OFFSET     = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;\n  localparam ARBURST_OFFSET    = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;\n  localparam ARLOCK_OFFSET     = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;\n  localparam ARCACHE_OFFSET    = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;\n  localparam ARPROT_OFFSET     = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam ARQOS_OFFSET      = ARPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam ARREGION_OFFSET   = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;\n  localparam ARUSER_OFFSET     = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;\n\n  localparam RID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;\n  localparam RDATA_OFFSET      = RID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam RRESP_OFFSET      = RDATA_OFFSET - C_AXI_RRESP_WIDTH;\n  localparam RUSER_OFFSET      = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;\n\n\n  generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rach_we    = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;\n\n    // Read protection when almost empty or prog_empty is high\n//    assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;\n    assign rach_re    = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        rach_m_axi_arvalid & arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY && rach_m_axi_arvalid :\n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY : 1'b0;\n    assign rach_wr_en = (C_HAS_SLAVE_CE == 1)  ? rach_we & S_ACLK_EN : rach_we;\n    assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;\n\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 2  || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),\n        .C_USE_ECC                      (C_USE_ECC_RACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_rach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rach_wr_en),\n        .RD_EN                    (rach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AR_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AR_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AR_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AR_INJECTSBITERR),\n  \n        .DIN                      (rach_din),\n        .DOUT                     (rach_dout_pkt),\n        .FULL                     (rach_full),\n        .EMPTY                    (rach_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_AR_PROG_FULL),\n        .PROG_EMPTY               (AXI_AR_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_ar_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_ar_underflow_i),\n        .DATA_COUNT               (AXI_AR_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AR_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AR_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AR_SBITERR),\n        .DBITERR                  (AXI_AR_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rach),\n        .rd_rst_busy              (rd_rst_busy_rach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rach_s_axi_arready    = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;\n    assign rach_m_axi_arvalid = ~rach_empty;\n    assign S_AXI_ARREADY      = rach_s_axi_arready;\n\n    assign AXI_AR_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;\n    assign AXI_AR_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_ar_overflow_i  : 0;\n\n  end endgenerate // axi_read_addr_channel\n\n  // Register Slice for Read Address Channel\n  generate if (C_RACH_TYPE == 1) begin : grach_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RACH)\n            )\n    rach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_din),\n          .S_VALID                   (S_AXI_ARVALID),\n          .S_READY                   (S_AXI_ARREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice\n\n  // Register Slice for Read Address Channel for MM Packet FIFO\n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (1)\n            )\n    reg_slice_mm_pkt_fifo_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_dout_pkt),\n          .S_VALID                   (arvalid_pkt),\n          .S_READY                   (arready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice_mm_pkt_fifo\n\n  \n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid\n    assign M_AXI_ARVALID      = rach_m_axi_arvalid;\n    assign rach_dout          = rach_dout_pkt;\n  end endgenerate // grach_m_axi_arvalid\n  \n  \n  generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd\n    assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;\n    assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;\n    assign accept_next_pkt  = rach_m_axi_arvalid && arready_pkt && arvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset) begin\n\trdch_commited_space <= 0;\n      end else begin\n\tif(rdch_rd_ok && !accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space-1;\n\tend else if(!rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);\n\tend else if(rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);\n\tend\n      end\n    end //Always end\n\n    always@(*) begin\n      rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));\n    end\n\n    assign arvalid_en = (rdch_free_space >= 0)?1:0;\n  end\n  endgenerate\n  \n  generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd\n    assign arvalid_en = 1;    \n  end\n  endgenerate\n\n  generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rdch_we    = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready  & M_AXI_RVALID : M_AXI_RVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign rdch_re    = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid  & S_AXI_RREADY : S_AXI_RREADY;\n    assign rdch_wr_en = (C_HAS_MASTER_CE == 1)  ? rdch_we & M_ACLK_EN : rdch_we;\n    assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;\n\n    fifo_generator_v13_2_5_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 2  || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),\n        .C_USE_ECC                      (C_USE_ECC_RDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_RDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_5_rdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rdch_wr_en),\n        .RD_EN                    (rdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_R_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_R_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_R_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_R_INJECTSBITERR),\n  \n        .DIN                      (rdch_din),\n        .DOUT                     (rdch_dout),\n        .FULL                     (rdch_full),\n        .EMPTY                    (rdch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_R_PROG_FULL),\n        .PROG_EMPTY               (AXI_R_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_r_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_r_underflow_i),\n        .DATA_COUNT               (AXI_R_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_R_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_R_WR_DATA_COUNT),\n        .SBITERR                  (AXI_R_SBITERR),\n        .DBITERR                  (AXI_R_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rdch),\n        .rd_rst_busy              (rd_rst_busy_rdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rdch_s_axi_rvalid = ~rdch_empty;\n    assign rdch_m_axi_rready     = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;\n    assign S_AXI_RVALID      = rdch_s_axi_rvalid;\n    assign M_AXI_RREADY      = rdch_m_axi_rready;\n\n    assign AXI_R_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i  : 0;\n    assign AXI_R_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_r_overflow_i   : 0;\n\n  end endgenerate //axi_read_data_channel\n\n  // Register Slice for read Data Channel\n  generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice\n\n    fifo_generator_v13_2_5_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RDCH)\n            )\n    rdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rdch_din),\n          .S_VALID                   (M_AXI_RVALID),\n          .S_READY                   (M_AXI_RREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rdch_dout),\n          .M_VALID                   (S_AXI_RVALID),\n          .M_READY                   (S_AXI_RREADY)\n          );\n  end endgenerate // grdch_reg_slice\n\n\n    assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;\n    assign axi_rd_overflow_i  = C_USE_COMMON_OVERFLOW  == 1 ? (axi_ar_overflow_i  || axi_r_overflow_i) : 0;\n\n\n  generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output\n    assign M_AXI_ARADDR    = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];    \n    assign M_AXI_ARLEN     = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];    \n    assign M_AXI_ARSIZE    = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];    \n    assign M_AXI_ARBURST   = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];    \n    assign M_AXI_ARLOCK    = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];    \n    assign M_AXI_ARCACHE   = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];    \n    assign M_AXI_ARPROT    = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];    \n    assign M_AXI_ARQOS     = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];    \n    assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET]    = S_AXI_ARADDR;\n    assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET]   = S_AXI_ARLEN;\n    assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET]   = S_AXI_ARSIZE;\n    assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;\n    assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;\n    assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;\n    assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;\n    assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET]   = S_AXI_ARQOS;\n  end endgenerate // axi_full_rach_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion\n    assign M_AXI_ARREGION  = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];    \n  end endgenerate // axi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion\n    assign M_AXI_ARREGION  = 0;    \n  end endgenerate // naxi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser\n    assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];    \n  end endgenerate // axi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser\n    assign M_AXI_ARUSER = 0;    \n  end endgenerate // naxi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid\n    assign M_AXI_ARID      = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];\n  end endgenerate // axi_arid\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid\n    assign M_AXI_ARID      = 0;\n  end endgenerate // naxi_arid\n\n  generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output\n    assign S_AXI_RDATA     = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];\n    assign S_AXI_RRESP     = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n    assign S_AXI_RLAST     = rdch_dout[0];\n    assign rdch_din[RID_OFFSET-1:RDATA_OFFSET]   = M_AXI_RDATA;\n    assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;\n    assign rdch_din[0] = M_AXI_RLAST;\n  end endgenerate // axi_full_rdch_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output\n    assign S_AXI_RUSER     = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];\n  end endgenerate // axi_full_ruser_output\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output\n    assign S_AXI_RUSER     =  0;\n  end endgenerate // axi_full_nruser_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid\n    assign S_AXI_RID       = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];\n  end endgenerate // axi_rid\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid\n    assign S_AXI_RID       = 0;\n  end endgenerate // naxi_rid\n\n  generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1\n    assign rach_din      = {S_AXI_ARADDR, S_AXI_ARPROT};\n    assign M_AXI_ARADDR  = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];\n    assign M_AXI_ARPROT  = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];\n  end endgenerate // axi_lite_rach_output\n\n  generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1\n    assign rdch_din      = {M_AXI_RDATA, M_AXI_RRESP};\n    assign S_AXI_RDATA   = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];\n    assign S_AXI_RRESP   = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n  end endgenerate // axi_lite_rdch_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1\n    assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET]     = S_AXI_ARUSER;\n  end endgenerate // grach_din1\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2\n    assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET]     = S_AXI_ARID;\n  end endgenerate // grach_din2\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin\n    assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1\n    assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET]     = M_AXI_RUSER;\n  end endgenerate // grdch_din1\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2\n    assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;\n  end endgenerate // grdch_din2\n\n  //end of axi_read_channel\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf\n    assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :\n                       (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :\n                       (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;\n  end endgenerate // gaxi_comm_uf\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of\n    assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :\n                      (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :\n                      (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;\n  end endgenerate // gaxi_comm_of\n  \n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  // Pass Through Logic or Wiring Logic\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  \n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Write Address Channel\n  generate if (C_WACH_TYPE == 2) begin : gwach_pass_through\n    assign M_AXI_AWID      = S_AXI_AWID;\n    assign M_AXI_AWADDR    = S_AXI_AWADDR;\n    assign M_AXI_AWLEN     = S_AXI_AWLEN;\n    assign M_AXI_AWSIZE    = S_AXI_AWSIZE;\n    assign M_AXI_AWBURST   = S_AXI_AWBURST;\n    assign M_AXI_AWLOCK    = S_AXI_AWLOCK;\n    assign M_AXI_AWCACHE   = S_AXI_AWCACHE;\n    assign M_AXI_AWPROT    = S_AXI_AWPROT;\n    assign M_AXI_AWQOS     = S_AXI_AWQOS;\n    assign M_AXI_AWREGION  = S_AXI_AWREGION;\n    assign M_AXI_AWUSER    = S_AXI_AWUSER;\n    assign S_AXI_AWREADY   = M_AXI_AWREADY;\n    assign M_AXI_AWVALID   = S_AXI_AWVALID;\n  end endgenerate // gwach_pass_through;\n\n  // Wiring logic for Write Data Channel\n  generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through\n    assign M_AXI_WID       = S_AXI_WID;\n    assign M_AXI_WDATA     = S_AXI_WDATA;\n    assign M_AXI_WSTRB     = S_AXI_WSTRB;\n    assign M_AXI_WLAST     = S_AXI_WLAST;\n    assign M_AXI_WUSER     = S_AXI_WUSER;\n    assign S_AXI_WREADY    = M_AXI_WREADY;\n    assign M_AXI_WVALID    = S_AXI_WVALID;\n  end endgenerate // gwdch_pass_through;\n\n  // Wiring logic for Write Response Channel\n  generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through\n    assign S_AXI_BID       = M_AXI_BID;\n    assign S_AXI_BRESP     = M_AXI_BRESP;\n    assign S_AXI_BUSER     = M_AXI_BUSER;\n    assign M_AXI_BREADY    = S_AXI_BREADY;\n    assign S_AXI_BVALID    = M_AXI_BVALID;\n  end endgenerate // gwrch_pass_through;\n\n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Read Address Channel\n  generate if (C_RACH_TYPE == 2) begin : grach_pass_through\n    assign M_AXI_ARID      = S_AXI_ARID;\n    assign M_AXI_ARADDR    = S_AXI_ARADDR;\n    assign M_AXI_ARLEN     = S_AXI_ARLEN;\n    assign M_AXI_ARSIZE    = S_AXI_ARSIZE;\n    assign M_AXI_ARBURST   = S_AXI_ARBURST;\n    assign M_AXI_ARLOCK    = S_AXI_ARLOCK;\n    assign M_AXI_ARCACHE   = S_AXI_ARCACHE;\n    assign M_AXI_ARPROT    = S_AXI_ARPROT;\n    assign M_AXI_ARQOS     = S_AXI_ARQOS;\n    assign M_AXI_ARREGION  = S_AXI_ARREGION;\n    assign M_AXI_ARUSER    = S_AXI_ARUSER;\n    assign S_AXI_ARREADY   = M_AXI_ARREADY;\n    assign M_AXI_ARVALID   = S_AXI_ARVALID;\n  end endgenerate // grach_pass_through;\n\n  // Wiring logic for Read Data Channel \n  generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through\n    assign S_AXI_RID      = M_AXI_RID;\n    assign S_AXI_RLAST    = M_AXI_RLAST;\n    assign S_AXI_RUSER    = M_AXI_RUSER;\n    assign S_AXI_RDATA    = M_AXI_RDATA;\n    assign S_AXI_RRESP    = M_AXI_RRESP;\n    assign S_AXI_RVALID   = M_AXI_RVALID;\n    assign M_AXI_RREADY   = S_AXI_RREADY;\n  end endgenerate // grdch_pass_through;\n\n  // Wiring logic for AXI Streaming\n  generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through\n    assign M_AXIS_TDATA   = S_AXIS_TDATA;\n    assign M_AXIS_TSTRB   = S_AXIS_TSTRB;\n    assign M_AXIS_TKEEP   = S_AXIS_TKEEP;\n    assign M_AXIS_TID     = S_AXIS_TID;\n    assign M_AXIS_TDEST   = S_AXIS_TDEST;\n    assign M_AXIS_TUSER   = S_AXIS_TUSER;\n    assign M_AXIS_TLAST   = S_AXIS_TLAST;\n    assign S_AXIS_TREADY  = M_AXIS_TREADY;\n    assign M_AXIS_TVALID  = S_AXIS_TVALID;\n  end endgenerate // gaxis_pass_through;\n\n\nendmodule //fifo_generator_v13_2_5\n\n\n\n/*******************************************************************************\n * Declaration of top-level module for Conventional FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_CONV_VER\n  #(\n    parameter  C_COMMON_CLOCK                 = 0,\n    parameter  C_INTERFACE_TYPE               = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_COUNT_TYPE                   = 0,\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DEFAULT_VALUE                = \"\",\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_ENABLE_RLOCS                 = 0,\n    parameter  C_FAMILY                       = \"virtex7\", //Not allowed in Verilog model\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_BACKUP                   = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_INT_CLK                  = 0,\n    parameter  C_HAS_MEMINIT_FILE             = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RD_RST                   = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_RST                   = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_INIT_WR_PNTR_VAL             = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_MIF_FILE_NAME                = \"\",\n    parameter  C_OPTIMIZATION_MODE            = 0,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PRIM_FIFO_TYPE               = \"\",\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_FREQ                      = 1,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_ECC                      = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_USE_FIFO16_FLAGS             = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_FREQ                      = 1,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_WR_RESPONSE_LATENCY          = 1,\n    parameter  C_MSGON_VAL                    = 1,\n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2,\n    parameter  C_AXI_TYPE                     = 0\n   )\n\n  (\n   input                               BACKUP,\n   input                               BACKUP_MARKER,\n   input                               CLK,\n   input                               RST,\n   input                               SRST,\n   input                               WR_CLK,\n   input                               WR_RST,\n   input                               RD_CLK,\n   input                               RD_RST,\n   input [C_DIN_WIDTH-1:0]             DIN,\n   input                               WR_EN,\n   input                               RD_EN,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_ASSERT,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_NEGATE,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_ASSERT,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_NEGATE,\n   input                               INT_CLK,\n   input                               INJECTDBITERR,\n   input                               INJECTSBITERR,\n  \n   output [C_DOUT_WIDTH-1:0]           DOUT,\n   output                              FULL,\n   output                              ALMOST_FULL,\n   output                              WR_ACK,\n   output                              OVERFLOW,\n   output                              EMPTY,\n   output                              ALMOST_EMPTY,\n   output                              VALID,\n   output                              UNDERFLOW,\n   output [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT,\n   output [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT,\n   output [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT,\n   output                              PROG_FULL,\n   output                              PROG_EMPTY,\n   output                              SBITERR,\n   output                              DBITERR,\n   output                              wr_rst_busy_o,\n   output                              wr_rst_busy,\n   output                              rd_rst_busy,\n   output                              wr_rst_i_out,\n   output                              rd_rst_i_out\n  );\n\n/*\n ******************************************************************************\n * Definition of Parameters\n ******************************************************************************\n *     C_COMMON_CLOCK                : Common Clock (1), Independent Clocks (0)\n *     C_COUNT_TYPE                  :    *not used\n *     C_DATA_COUNT_WIDTH            : Width of DATA_COUNT bus\n *     C_DEFAULT_VALUE               :    *not used\n *     C_DIN_WIDTH                   : Width of DIN bus\n *     C_DOUT_RST_VAL                : Reset value of DOUT\n *     C_DOUT_WIDTH                  : Width of DOUT bus\n *     C_ENABLE_RLOCS                :    *not used\n *     C_FAMILY                      : not used in bhv model\n *     C_FULL_FLAGS_RST_VAL          : Full flags rst val (0 or 1)\n *     C_HAS_ALMOST_EMPTY            : 1=Core has ALMOST_EMPTY flag\n *     C_HAS_ALMOST_FULL             : 1=Core has ALMOST_FULL flag\n *     C_HAS_BACKUP                  :    *not used\n *     C_HAS_DATA_COUNT              : 1=Core has DATA_COUNT bus\n *     C_HAS_INT_CLK                 : not used in bhv model\n *     C_HAS_MEMINIT_FILE            :    *not used\n *     C_HAS_OVERFLOW                : 1=Core has OVERFLOW flag\n *     C_HAS_RD_DATA_COUNT           : 1=Core has RD_DATA_COUNT bus\n *     C_HAS_RD_RST                  :    *not used\n *     C_HAS_RST                     : 1=Core has Async Rst\n *     C_HAS_SRST                    : 1=Core has Sync Rst\n *     C_HAS_UNDERFLOW               : 1=Core has UNDERFLOW flag\n *     C_HAS_VALID                   : 1=Core has VALID flag\n *     C_HAS_WR_ACK                  : 1=Core has WR_ACK flag\n *     C_HAS_WR_DATA_COUNT           : 1=Core has WR_DATA_COUNT bus\n *     C_HAS_WR_RST                  :    *not used\n *     C_IMPLEMENTATION_TYPE         : 0=Common-Clock Bram/Dram\n *                                     1=Common-Clock ShiftRam\n *                                     2=Indep. Clocks Bram/Dram\n *                                     3=Virtex-4 Built-in\n *                                     4=Virtex-5 Built-in\n *     C_INIT_WR_PNTR_VAL            :   *not used\n *     C_MEMORY_TYPE                 : 1=Block RAM\n *                                     2=Distributed RAM\n *                                     3=Shift RAM\n *                                     4=Built-in FIFO\n *     C_MIF_FILE_NAME               :   *not used\n *     C_OPTIMIZATION_MODE           :   *not used\n *     C_OVERFLOW_LOW                : 1=OVERFLOW active low\n *     C_PRELOAD_LATENCY             : Latency of read: 0, 1, 2\n *     C_PRELOAD_REGS                : 1=Use output registers\n *     C_PRIM_FIFO_TYPE              : not used in bhv model\n *     C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold\n *     C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold\n *     C_PROG_EMPTY_TYPE             : 0=No programmable empty\n *                                     1=Single prog empty thresh constant\n *                                     2=Multiple prog empty thresh constants\n *                                     3=Single prog empty thresh input\n *                                     4=Multiple prog empty thresh inputs\n *     C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold\n *     C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold\n *     C_PROG_FULL_TYPE              : 0=No prog full\n *                                     1=Single prog full thresh constant\n *                                     2=Multiple prog full thresh constants\n *                                     3=Single prog full thresh input\n *                                     4=Multiple prog full thresh inputs\n *     C_RD_DATA_COUNT_WIDTH         : Width of RD_DATA_COUNT bus\n *     C_RD_DEPTH                    : Depth of read interface (2^N)\n *     C_RD_FREQ                     : not used in bhv model\n *     C_RD_PNTR_WIDTH               : always log2(C_RD_DEPTH)\n *     C_UNDERFLOW_LOW               : 1=UNDERFLOW active low\n *     C_USE_DOUT_RST                : 1=Resets DOUT on RST\n *     C_USE_ECC                     : Used for error injection purpose\n *     C_USE_EMBEDDED_REG            : 1=Use BRAM embedded output register\n *     C_USE_FIFO16_FLAGS            : not used in bhv model\n *     C_USE_FWFT_DATA_COUNT         : 1=Use extra logic for FWFT data count\n *     C_VALID_LOW                   : 1=VALID active low\n *     C_WR_ACK_LOW                  : 1=WR_ACK active low\n *     C_WR_DATA_COUNT_WIDTH         : Width of WR_DATA_COUNT bus\n *     C_WR_DEPTH                    : Depth of write interface (2^N)\n *     C_WR_FREQ                     : not used in bhv model\n *     C_WR_PNTR_WIDTH               : always log2(C_WR_DEPTH)\n *     C_WR_RESPONSE_LATENCY         :    *not used\n *     C_MSGON_VAL                   :    *not used by bhv model\n *     C_ENABLE_RST_SYNC             : 0 = Use WR_RST & RD_RST\n *                                     1 = Use RST\n *     C_ERROR_INJECTION_TYPE        : 0 = No error injection\n *                                     1 = Single bit error injection only\n *                                     2 = Double bit error injection only\n *                                     3 = Single and double bit error injection\n ******************************************************************************\n * Definition of Ports\n ******************************************************************************\n *   BACKUP       : Not used\n *   BACKUP_MARKER: Not used\n *   CLK          : Clock\n *   DIN          : Input data bus\n *   PROG_EMPTY_THRESH       : Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag\n *   PROG_FULL_THRESH        : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag\n *   RD_CLK       : Read Domain Clock\n *   RD_EN        : Read enable\n *   RD_RST       : Read Reset\n *   RST          : Asynchronous Reset\n *   SRST         : Synchronous Reset\n *   WR_CLK       : Write Domain Clock\n *   WR_EN        : Write enable\n *   WR_RST       : Write Reset\n *   INT_CLK      : Internal Clock\n *   INJECTSBITERR: Inject Signle bit error\n *   INJECTDBITERR: Inject Double bit error\n *   ALMOST_EMPTY : One word remaining in FIFO\n *   ALMOST_FULL  : One empty space remaining in FIFO\n *   DATA_COUNT   : Number of data words in fifo( synchronous to CLK)\n *   DOUT         : Output data bus\n *   EMPTY        : Empty flag\n *   FULL         : Full flag\n *   OVERFLOW     : Last write rejected\n *   PROG_EMPTY   : Programmable Empty Flag\n *   PROG_FULL    : Programmable Full Flag\n *   RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)\n *   UNDERFLOW    : Last read rejected\n *   VALID        : Last read acknowledged, DOUT bus VALID\n *   WR_ACK       : Last write acknowledged\n *   WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)\n *   SBITERR      : Single Bit ECC Error Detected\n *   DBITERR      : Double Bit ECC Error Detected\n ******************************************************************************\n */\n\n  //----------------------------------------------------------------------------\n  //- Internal Signals for delayed input signals\n  //- All the input signals except Clock are delayed by 100 ps and then given to\n  //- the models.\n  //----------------------------------------------------------------------------\n \n  reg                         rst_delayed                       ;\n  reg                         empty_fb                       ;\n  reg                         srst_delayed                      ;\n  reg                         wr_rst_delayed                    ;\n  reg                         rd_rst_delayed                    ;\n  reg                         wr_en_delayed                     ;\n  reg                         rd_en_delayed                     ;\n  reg  [C_DIN_WIDTH-1:0]      din_delayed                       ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_delayed         ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_assert_delayed  ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_negate_delayed  ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_delayed          ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_assert_delayed   ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_negate_delayed   ;\n  reg                         injectdbiterr_delayed             ;\n  reg                         injectsbiterr_delayed             ;\n   wire                        empty_p0_out;\n\n  always @* rst_delayed                       <= #`TCQ RST                      ;\n  always @* empty_fb                       <= #`TCQ empty_p0_out                      ;\n  always @* srst_delayed                      <= #`TCQ SRST                     ; \n  always @* wr_rst_delayed                    <= #`TCQ WR_RST                   ; \n  always @* rd_rst_delayed                    <= #`TCQ RD_RST                   ; \n  always @* din_delayed                       <= #`TCQ DIN                      ; \n  always @* wr_en_delayed                     <= #`TCQ WR_EN                    ; \n  always @* rd_en_delayed                     <= #`TCQ RD_EN                    ; \n  always @* prog_empty_thresh_delayed         <= #`TCQ PROG_EMPTY_THRESH        ; \n  always @* prog_empty_thresh_assert_delayed  <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; \n  always @* prog_empty_thresh_negate_delayed  <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; \n  always @* prog_full_thresh_delayed          <= #`TCQ PROG_FULL_THRESH         ; \n  always @* prog_full_thresh_assert_delayed   <= #`TCQ PROG_FULL_THRESH_ASSERT  ; \n  always @* prog_full_thresh_negate_delayed   <= #`TCQ PROG_FULL_THRESH_NEGATE  ; \n  always @* injectdbiterr_delayed             <= #`TCQ INJECTDBITERR            ; \n  always @* injectsbiterr_delayed             <= #`TCQ INJECTSBITERR            ; \n\n  /*****************************************************************************\n   * Derived parameters\n   ****************************************************************************/\n  //There are 2 Verilog behavioral models\n  // 0 = Common-Clock FIFO/ShiftRam FIFO\n  // 1 = Independent Clocks FIFO\n  // 2 = Low Latency Synchronous FIFO\n  // 3 = Low Latency Asynchronous FIFO\n  localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :\n                              (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n\n  //Internal reset signals\n  reg                                rd_rst_asreg    = 1'b0;\n  reg                                rd_rst_asreg_d1 = 1'b0;\n  reg                                rd_rst_asreg_d2 = 1'b0;\n  reg                                rd_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_reg      = 1'b0;\n  reg                                rd_rst_comb     = 1'b1;\n  reg                                rd_rst_comb_d1  = 1'b0;\n  reg                                wr_rst_d0       = 1'b0;\n  reg                                wr_rst_d1       = 1'b0;\n  reg                                wr_rst_d2       = 1'b0;\n  reg                                rd_rst_d0       = 1'b0;\n  reg                                rd_rst_d1       = 1'b0;\n  reg                                rd_rst_d2       = 1'b0;\n  reg                                rd_rst_d3       = 1'b0;\n  reg                                wrrst_done      = 1'b0;\n  reg                                rdrst_done      = 1'b0;\n  reg                                wr_rst_asreg    = 1'b0;\n  reg                                wr_rst_asreg_d1 = 1'b0;\n  reg                                wr_rst_asreg_d2 = 1'b0;\n  reg                                wr_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_wr_d0    = 1'b0;\n  reg                                rd_rst_wr_d1    = 1'b0;\n  reg                                rd_rst_wr_d2    = 1'b0;\n  reg                                wr_rst_reg      = 1'b0;\n  reg                                rst_active_i    = 1'b1;\n  reg                                rst_delayed_d1  = 1'b1;\n  reg                                rst_delayed_d2  = 1'b1;\n  reg                                wr_rst_comb     = 1'b1;\n  reg                                wr_rst_comb_d1  = 1'b0;\n  wire                               wr_rst_i;\n  wire                               rd_rst_i;\n  wire                               rst_i;\n\n  //Internal reset signals\n  reg                                rst_asreg     = 1'b0;\n  reg                                srst_asreg    = 1'b0;\n  reg                                rst_asreg_d1  = 1'b0;\n  reg                                rst_asreg_d2  = 1'b0;\n  reg                                srst_asreg_d1 = 1'b0;\n  reg                                srst_asreg_d2 = 1'b0;\n  reg                                rst_reg       = 1'b0;\n  reg                                srst_reg      = 1'b0;\n  reg                                rst_comb      = 1'b1;\n  reg                                rst_comb_d1   = 1'b0;\n  wire                               srst_comb;\n  reg                                rst_full_gen_i = 0;\n  reg                                rst_full_ff_i = 0;\n  reg  [2:0]                         sckt_ff0_bsy_o_i = {3{1'b0}};\n                                     \n  wire                               RD_CLK_P0_IN;\n  wire                               RST_P0_IN;\n  wire                               RD_EN_FIFO_IN;\n  wire                               RD_EN_P0_IN;\n\n  wire                               ALMOST_EMPTY_FIFO_OUT;\n  wire                               ALMOST_FULL_FIFO_OUT;\n  wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT_FIFO_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DOUT_FIFO_OUT;\n  wire                               EMPTY_FIFO_OUT;\n  wire                               fifo_empty_fb;\n  wire                               FULL_FIFO_OUT;\n  wire                               OVERFLOW_FIFO_OUT;\n  wire                               PROG_EMPTY_FIFO_OUT;\n  wire                               PROG_FULL_FIFO_OUT;\n  wire                               VALID_FIFO_OUT;\n  wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT_FIFO_OUT;\n  wire                               UNDERFLOW_FIFO_OUT;\n  wire                               WR_ACK_FIFO_OUT;\n  wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT_FIFO_OUT;\n\n\n  //***************************************************************************\n  // Internal Signals\n  //   The core uses either the internal_ wires or the preload0_ wires depending\n  //     on whether the core uses Preload0 or not.\n  //   When using preload0, the internal signals connect the internal core to\n  //     the preload logic, and the external core's interfaces are tied to the\n  //     preload0 signals from the preload logic.\n  //***************************************************************************\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_OUT;\n  wire                               VALID_P0_OUT;\n  wire                               EMPTY_P0_OUT;\n  wire                               ALMOSTEMPTY_P0_OUT;\n  reg                                EMPTY_P0_OUT_Q;\n  reg                                ALMOSTEMPTY_P0_OUT_Q;\n  wire                               UNDERFLOW_P0_OUT;\n  wire                               RDEN_P0_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_IN;\n  wire                               EMPTY_P0_IN;\n  reg  [31:0]                        DATA_COUNT_FWFT;\n  reg                                SS_FWFT_WR  ;\n  reg                                SS_FWFT_RD ;\n\n  wire                               sbiterr_fifo_out;\n  wire                               dbiterr_fifo_out;\n  wire                               inject_sbit_err;\n  wire                               inject_dbit_err;\n  wire                               sckt_wr_rst_i;\n  wire                               sckt_rd_rst_i;\n  reg                                sckt_wr_rst_i_q = 1'b0;\n \n  wire                               w_fab_read_data_valid_i;\n  wire                               w_read_data_valid_i;\n  wire                               w_ram_valid_i;\n  // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.\n  assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectsbiterr_delayed : 0;\n  assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectdbiterr_delayed : 0;\n                           \n  assign wr_rst_i_out = wr_rst_i;\n  assign rd_rst_i_out = rd_rst_i;\n  assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];\n  generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o\n    wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;\n    always @ (posedge clk_i)\n      sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; \n  end endgenerate \n// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL\n// parameter (1=Independent Clocks, 0=Common Clock)\n\n  localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;\ngenerate\ncase (C_VERILOG_IMPL)\n0 : begin : block1_ss\n  //Common Clock Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_ss\n  #(\n    .C_FAMILY                            (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                  (C_DATA_COUNT_WIDTH),            \n    .C_DIN_WIDTH                         (C_DIN_WIDTH),                   \n    .C_DOUT_RST_VAL                      (C_DOUT_RST_VAL),                \n    .C_DOUT_WIDTH                        (C_DOUT_WIDTH),                  \n    .C_FULL_FLAGS_RST_VAL                (FULL_FLAGS_RST_VAL),            \n    .C_HAS_ALMOST_EMPTY                  (C_HAS_ALMOST_EMPTY),            \n    .C_HAS_ALMOST_FULL                   ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),             \n    .C_HAS_DATA_COUNT                    (C_HAS_DATA_COUNT),              \n    .C_HAS_OVERFLOW                      (C_HAS_OVERFLOW),                \n    .C_HAS_RD_DATA_COUNT                 (C_HAS_RD_DATA_COUNT),           \n    .C_HAS_RST                           (C_EN_SAFETY_CKT?0:C_HAS_RST),                     \n    .C_HAS_SRST                          (C_EN_SAFETY_CKT?1:C_HAS_SRST),                    \n    .C_HAS_UNDERFLOW                     (C_HAS_UNDERFLOW),               \n    .C_HAS_VALID                         (C_HAS_VALID),                   \n    .C_HAS_WR_ACK                        (C_HAS_WR_ACK),                  \n    .C_HAS_WR_DATA_COUNT                 (C_HAS_WR_DATA_COUNT),           \n    .C_IMPLEMENTATION_TYPE               (C_IMPLEMENTATION_TYPE),         \n    .C_MEMORY_TYPE                       (C_MEMORY_TYPE),                 \n    .C_OVERFLOW_LOW                      (C_OVERFLOW_LOW),                \n    .C_PRELOAD_LATENCY                   (C_PRELOAD_LATENCY),             \n    .C_PRELOAD_REGS                      (C_PRELOAD_REGS),                \n    .C_PROG_EMPTY_THRESH_ASSERT_VAL      (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL      (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                   (C_PROG_EMPTY_TYPE),             \n    .C_PROG_FULL_THRESH_ASSERT_VAL       (C_PROG_FULL_THRESH_ASSERT_VAL), \n    .C_PROG_FULL_THRESH_NEGATE_VAL       (C_PROG_FULL_THRESH_NEGATE_VAL), \n    .C_PROG_FULL_TYPE                    (C_PROG_FULL_TYPE),              \n    .C_RD_DATA_COUNT_WIDTH               (C_RD_DATA_COUNT_WIDTH),         \n    .C_RD_DEPTH                          (C_RD_DEPTH),                    \n    .C_RD_PNTR_WIDTH                     (C_RD_PNTR_WIDTH),               \n    .C_UNDERFLOW_LOW                     (C_UNDERFLOW_LOW),               \n    .C_USE_DOUT_RST                      (C_USE_DOUT_RST),                \n    .C_USE_EMBEDDED_REG                  (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                     (C_EN_SAFETY_CKT),            \n    .C_USE_FWFT_DATA_COUNT               (C_USE_FWFT_DATA_COUNT),         \n    .C_VALID_LOW                         (C_VALID_LOW),                   \n    .C_WR_ACK_LOW                        (C_WR_ACK_LOW),                  \n    .C_WR_DATA_COUNT_WIDTH               (C_WR_DATA_COUNT_WIDTH),         \n    .C_WR_DEPTH                          (C_WR_DEPTH),                    \n    .C_WR_PNTR_WIDTH                     (C_WR_PNTR_WIDTH),               \n    .C_USE_ECC                           (C_USE_ECC),                     \n    .C_ENABLE_RST_SYNC                   (C_ENABLE_RST_SYNC),             \n    .C_ERROR_INJECTION_TYPE              (C_ERROR_INJECTION_TYPE),\n    .C_FIFO_TYPE                         (C_FIFO_TYPE)                     \n  )\n  gen_ss\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .CLK                      (CLK),\n    .RST                      (C_EN_SAFETY_CKT?1'b0:rst_i),\n    .SRST                     (C_EN_SAFETY_CKT?sckt_wr_rst_i:srst_delayed),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .USER_EMPTY_FB            (empty_fb),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .DATA_COUNT               (DATA_COUNT_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .WR_RST_BUSY              (wr_rst_busy),\n    .RD_RST_BUSY              (rd_rst_busy),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n1 : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT), \n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .fab_read_data_valid_i    (w_fab_read_data_valid_i),\n    .read_data_valid_i        (w_read_data_valid_i),\n    .ram_valid_i              (w_ram_valid_i),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\n2 : begin : ll_afifo_inst\n  fifo_generator_v13_2_5_beh_ver_ll_afifo\n  #(\n    .C_DIN_WIDTH                    (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                 (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                   (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_RD_DATA_COUNT            (C_HAS_RD_DATA_COUNT),\n    .C_HAS_WR_DATA_COUNT            (C_HAS_WR_DATA_COUNT),\n    .C_RD_DEPTH                     (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                (C_RD_PNTR_WIDTH),\n    .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n    .C_WR_DATA_COUNT_WIDTH          (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                     (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                (C_WR_PNTR_WIDTH),\n    .C_FIFO_TYPE                    (C_FIFO_TYPE)\n   )\n  gen_ll_afifo\n  (\n    .DIN                        (din_delayed),\n    .RD_CLK                     (RD_CLK),\n    .RD_EN                      (rd_en_delayed),\n    .WR_RST                     (wr_rst_i),\n    .RD_RST                     (rd_rst_i),\n    .WR_CLK                     (WR_CLK),\n    .WR_EN                      (wr_en_delayed),\n    .DOUT                       (DOUT),\n    .EMPTY                      (EMPTY),\n    .FULL                       (FULL)\n  );\nend\ndefault : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_5_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT),\n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\nendcase\nendgenerate\n\n\n   //**************************************************************************\n   // Connect Internal Signals\n   //   (Signals labeled internal_*)\n   //  In the normal case, these signals tie directly to the FIFO's inputs and\n   //    outputs.\n   //  In the case of Preload Latency 0 or 1, there are intermediate\n   //    signals between the internal FIFO and the preload logic.\n   //**************************************************************************\n   \n   \n   //***********************************************\n   // If First-Word Fall-Through, instantiate\n   // the preload0 (FWFT) module\n   //***********************************************\n   wire                        rd_en_to_fwft_fifo;\n   wire                        sbiterr_fwft;\n   wire                        dbiterr_fwft;\n   wire [C_DOUT_WIDTH-1:0]     dout_fwft;\n   wire                        empty_fwft;\n   wire                        rd_en_fifo_in;\n   wire                        stage2_reg_en_i;\n   wire [1:0]                  valid_stages_i;\n   wire                        rst_fwft;\n   //wire                        empty_p0_out;\n   reg  [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n   localparam IS_PKT_FIFO      = (C_FIFO_TYPE == 1) ? 1 : 0;\n   localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;\n   assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2_fwft\n\n\n         fifo_generator_v13_2_5_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_EMBEDDED_REG  (C_USE_EMBEDDED_REG),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (C_FIFO_TYPE)\n             )\n             fgpl0\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (RST_P0_IN),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (RD_EN_P0_IN),\n                .FIFOEMPTY        (EMPTY_P0_IN),\n                .FIFODATA         (DATA_P0_IN),\n                .FIFOSBITERR      (sbiterr_fifo_out),\n                .FIFODBITERR      (dbiterr_fifo_out),\n                // Output\n                .USERDATA         (dout_fwft),\n                .USERVALID        (VALID_P0_OUT),\n                .USEREMPTY        (empty_fwft),\n                .USERALMOSTEMPTY  (ALMOSTEMPTY_P0_OUT),\n                .USERUNDERFLOW    (UNDERFLOW_P0_OUT),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_fifo_in),\n                .USERSBITERR      (sbiterr_fwft),\n                .USERDBITERR      (dbiterr_fwft),\n                .STAGE2_REG_EN    (stage2_reg_en_i),\n                .fab_read_data_valid_i_o    (w_fab_read_data_valid_i),\n                .read_data_valid_i_o        (w_read_data_valid_i),\n                .ram_valid_i_o              (w_ram_valid_i),\n                .VALID_STAGES                (valid_stages_i)\n                );\n\n         \n         //***********************************************\n         // Connect inputs to preload (FWFT) module\n         //***********************************************\n         //Connect the RD_CLK of the Preload (FWFT) module to CLK if we \n         // have a common-clock FIFO, or RD_CLK if we have an \n         // independent clock FIFO\n         assign RD_CLK_P0_IN       = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);\n         assign RST_P0_IN          = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;\n         assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n         assign EMPTY_P0_IN        = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;\n         assign DATA_P0_IN         = DOUT_FIFO_OUT;\n         \n         //***********************************************\n         // Connect outputs from preload (FWFT) module\n         //***********************************************\n         assign VALID              = VALID_P0_OUT ;\n         assign ALMOST_EMPTY       = ALMOSTEMPTY_P0_OUT;\n         assign UNDERFLOW          = UNDERFLOW_P0_OUT ;\n         \n         assign RD_EN_FIFO_IN      = rd_en_fifo_in;\n         \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:\n           (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : \n           DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];  \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               EMPTY_P0_OUT_Q       <= 1;\n               ALMOSTEMPTY_P0_OUT_Q <= 1;\n            end else begin\n               EMPTY_P0_OUT_Q       <= #`TCQ empty_p0_out;\n//               EMPTY_P0_OUT_Q       <= #`TCQ EMPTY_FIFO_OUT;\n               ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;\n            end\n         end //always\n         \n         \n         //***********************************************\n         // logic for common-clock data count when FWFT is selected\n         //***********************************************\n         initial begin\n            SS_FWFT_RD = 1'b0;\n            DATA_COUNT_FWFT = 0 ;\n            SS_FWFT_WR   = 1'b0 ;\n         end //initial\n         \n         \n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter. SS_FWFT_WR and SS_FWFT_RD\n         // are the up/down enables for the counter.\n         //***********************************************\n         always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin\n            if (C_VALID_LOW == 1) begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;\n            end else begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;\n            end\n            SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT))  ;\n         end \n\n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter for FWFT. This always block \n         // calculates the counter.\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               DATA_COUNT_FWFT      <= 0;\n            end else begin\n               //if (srst_delayed && (C_HAS_SRST == 1) ) begin\n               if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin\n                  DATA_COUNT_FWFT      <= #`TCQ 0;\n               end else begin\n                  case ( {SS_FWFT_WR, SS_FWFT_RD})\n                    2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                    2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;\n                    2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;\n                    2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                  endcase  \n               end //if SRST\n            end //IF RST\n         end //always\n\n      end endgenerate // : block2\n\n    // AXI Streaming Packet FIFO\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_plus1 = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_reg   = 0;\n    reg                         partial_packet     = 0;\n    reg                         stage1_eop_d1      = 0;\n    reg                         rd_en_fifo_in_d1   = 0;\n    reg                         eop_at_stage2      = 0;\n    reg                         ram_pkt_empty      = 0;\n    reg                         ram_pkt_empty_d1   = 0;\n\n    wire [C_DOUT_WIDTH-1:0]     dout_p0_out;\n    wire                        packet_empty_wr;\n    wire                        wr_rst_fwft_pkt_fifo;\n    wire                        dummy_wr_eop;\n    wire                        ram_wr_en_pkt_fifo;\n    wire                        wr_eop;\n    wire                        ram_rd_en_compare;\n    wire                        stage1_eop;\n    wire                        pkt_ready_to_read;\n    wire                        rd_en_2_stage2;\n\n    // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)\n    // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP\n    // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of\n    // write packet count\n    generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop\n       always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n          if (wr_rst_fwft_pkt_fifo)\n             partial_packet   <= 1'b0;\n          else begin\n             if (srst_delayed | wr_rst_busy | rd_rst_busy)\n                partial_packet <= #`TCQ 1'b0;\n             else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))\n                partial_packet <= #`TCQ 1'b1;\n             else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)\n                partial_packet <= #`TCQ 1'b0;\n          end\n        end\n    end endgenerate // gdummy_wr_eop\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin : gpkt_fifo_fwft\n      assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;\n      assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);\n      assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];\n  \n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft) begin\n          stage1_eop_d1    <= 1'b0;\n          rd_en_fifo_in_d1 <= 1'b0;\n        end else begin\n          if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            stage1_eop_d1    <= #`TCQ 1'b0;\n            rd_en_fifo_in_d1 <= #`TCQ 1'b0;\n          end else begin\n            stage1_eop_d1    <= #`TCQ stage1_eop;\n            rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;\n          end\n        end\n      end\n      assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;\n      assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);\n      assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);\n      assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;\n\n\n         fifo_generator_v13_2_5_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (2) // Enable low latency fwft logic\n             )\n         pkt_fifo_fwft\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (rst_fwft),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (rd_en_delayed),\n                .FIFOEMPTY        (pkt_ready_to_read),\n                .FIFODATA         (dout_fwft),\n                .FIFOSBITERR      (sbiterr_fwft),\n                .FIFODBITERR      (dbiterr_fwft),\n                // Output\n                .USERDATA         (dout_p0_out),\n                .USERVALID        (),\n                .USEREMPTY        (empty_p0_out),\n                .USERALMOSTEMPTY  (),\n                .USERUNDERFLOW    (),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_2_stage2),\n                .USERSBITERR      (SBITERR),\n                .USERDBITERR      (DBITERR),\n                .STAGE2_REG_EN    (),\n                .VALID_STAGES     ()\n                );\n\n      assign pkt_ready_to_read  = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));\n      assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft)\n          eop_at_stage2 <= 1'b0;\n        else if (stage2_reg_en_i)\n          eop_at_stage2 <= #`TCQ stage1_eop;\n      end\n\n      //---------------------------------------------------------------------------\n      // Write and Read Packet Count\n      //---------------------------------------------------------------------------\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count  <= 0;\n         else if (srst_delayed  | wr_rst_busy | rd_rst_busy)\n            wr_pkt_count  <= #`TCQ 0;\n         else if (wr_eop)\n            wr_pkt_count  <= #`TCQ wr_pkt_count + 1;\n      end\n    \n    end endgenerate //: gpkt_fifo_fwft\n\n    assign DOUT               = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;\n    assign EMPTY              = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            rd_pkt_count       <= 0;\n            rd_pkt_count_plus1 <= 1;\n         end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            rd_pkt_count       <= #`TCQ 0;\n            rd_pkt_count_plus1 <= #`TCQ 1;\n         end else if (stage2_reg_en_i && stage1_eop) begin\n            rd_pkt_count       <= #`TCQ rd_pkt_count + 1;\n            rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;\n         end\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (SRST | wr_rst_busy | rd_rst_busy) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n    end endgenerate //grss_pkt_cnt\n    \n    localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;\n    reg  [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_b2g = 0;\n    wire [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_rd;\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt\n      // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count_b2g  <= 0;\n         else\n            wr_pkt_count_b2g  <= #`TCQ wr_pkt_count;\n      end\n\n      // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            wr_pkt_count_q       <= 0;\n         else\n            wr_pkt_count_q       <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};\n      end\n\n      always @* begin\n        if (stage1_eop)\n           rd_pkt_count    <= rd_pkt_count_reg + 1;\n        else\n           rd_pkt_count    <= rd_pkt_count_reg;\n      end\n\n      assign wr_pkt_count_rd    = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            rd_pkt_count_reg       <= 0;\n         else if (rd_en_fifo_in)\n            rd_pkt_count_reg       <= #`TCQ rd_pkt_count;\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (rd_pkt_count != wr_pkt_count_rd) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n\n      // Synchronize the empty in write domain\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            pkt_empty_sync  <= 'b1;\n         else\n            pkt_empty_sync  <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};\n      end\n\n    end endgenerate //gras_pkt_cnt\n\n   generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO\n\n     //***********************************************\n     // If NOT First-Word Fall-Through, wire the outputs\n     // of the internal _ss or _as FIFO directly to the\n     // output, and do not instantiate the preload0\n     // module.\n     //***********************************************\n\n     assign RD_CLK_P0_IN       = 0;\n     assign RST_P0_IN          = 0;\n     assign RD_EN_P0_IN        = 0;\n\n     assign RD_EN_FIFO_IN      = rd_en_delayed;\n\n     assign DOUT               = DOUT_FIFO_OUT;\n     assign DATA_P0_IN         = 0;\n     assign VALID              = VALID_FIFO_OUT;\n     assign EMPTY              = EMPTY_FIFO_OUT;\n     assign ALMOST_EMPTY       = ALMOST_EMPTY_FIFO_OUT;\n     assign EMPTY_P0_IN        = 0;\n     assign UNDERFLOW          = UNDERFLOW_FIFO_OUT;\n     assign DATA_COUNT         = DATA_COUNT_FIFO_OUT;\n     assign SBITERR            = sbiterr_fifo_out;\n     assign DBITERR            = dbiterr_fifo_out;\n\n   end endgenerate // STD_FIFO\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO\n     assign empty_p0_out       = empty_fwft;\n     assign SBITERR            = sbiterr_fwft;\n     assign DBITERR            = dbiterr_fwft;\n     assign DOUT               = dout_fwft;\n     assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n\n   end endgenerate // NO_PKT_FIFO\n\n   //***********************************************\n   // Connect user flags to internal signals\n   //***********************************************\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3\n      if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);\n      end //block_ic\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3\n   endgenerate\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30\n       if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30\n   endgenerate\n\n\n    \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both\n       if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30_both\n   endgenerate\n\n generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both\n      if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));\n      end //block_ic_both\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3_both\n   endgenerate\n\n\n   //If we are not using extra logic for the FWFT data count,\n   //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the\n   //internal FIFO instance  \n   generate\n      if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n   //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal\n   //FIFO instance\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1) begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n      else begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n\n   //Connect other flags to the internal FIFO instance\n   assign       FULL        = FULL_FIFO_OUT;\n   assign       ALMOST_FULL = ALMOST_FULL_FIFO_OUT;\n   assign       WR_ACK      = WR_ACK_FIFO_OUT;\n   assign       OVERFLOW    = OVERFLOW_FIFO_OUT;\n   assign       PROG_FULL   = PROG_FULL_FIFO_OUT;\n   assign       PROG_EMPTY  = PROG_EMPTY_FIFO_OUT;\n\n\n  /**************************************************************************\n  * find_log2\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n   // if an asynchronous FIFO has been selected, display a message that the FIFO\n   //   will not be cycle-accurate in simulation\n   initial begin\n      if (C_IMPLEMENTATION_TYPE == 2) begin\n         $display(\"WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.\");\n      end else if (C_MEMORY_TYPE == 4) begin\n         $display(\"FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.\");\n         $finish;\n      end\n\n      if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin\n         $display(\"FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.\");\n         $finish;\n      end\n\n      if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin\n         $display(\"FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.\");\n         $finish;\n      end\n\n      if (C_USE_ECC == 1) begin\n         if (C_DIN_WIDTH != C_DOUT_WIDTH) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.\");\n            $finish;\n         end\n         if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.\");\n            $finish;\n         end\n      end\n\n   end //initial\n\n  /**************************************************************************\n  * Internal reset logic\n  **************************************************************************/\n  assign wr_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg|sckt_wr_rst_i : 0;\n  assign rd_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg|sckt_rd_rst_i : 0;\n  assign rst_i            = C_HAS_RST ? rst_reg|sckt_wr_rst_i : 0;\n\n  wire rst_2_sync;\n  wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;\n\n  localparam RST_SYNC_STAGES = C_EN_SAFETY_CKT == 0 ? C_COMMON_CLOCK ? C_SYNCHRONIZER_STAGE : C_SYNCHRONIZER_STAGE+2 : 5;\n  localparam RST_BUSY_LEN    = 4;\n  reg  wr_rst_busy_i = 0;\n  reg  rd_rst_busy_i = 0;\n  generate\n      if (C_ENABLE_RST_SYNC == 0 || (C_HAS_RST == 0 && C_HAS_SRST == 0)) begin : gnrst_sync\n        always @* begin\n          wr_rst_reg <= wr_rst_delayed;\n          rd_rst_reg <= rd_rst_delayed;\n          rst_reg    <= 1'b0;\n          srst_reg    <= 1'b0;\n        end\n        assign rst_2_sync = wr_rst_delayed;\n        assign wr_rst_busy = 1'b0;\n        assign wr_rst_busy_o = 1'b0;\n        assign rd_rst_busy = 1'b0;\n        assign sckt_wr_rst_i = 1'b0;\n        assign sckt_rd_rst_i = 1'b0;\n      end // gnrst_sync\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 0) begin : g7s_ic_rst_nsckt\n        reg [1:0]                 arst_sync_wr  = 2'b11;\n        reg [1:0]                 arst_sync_rd  = 2'b11;\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge WR_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge RD_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_rd    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_rd    <= #`TCQ {arst_sync_rd[0], rst_delayed};\n        end\n        always @(posedge WR_CLK) begin\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n\tend\n        always @(posedge WR_CLK or posedge arst_sync_wr[1]) begin\n\t  if (arst_sync_wr[1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n            rd_rst_wr_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            rd_rst_wr_ext  <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t    if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t      sckt_wr_rst_ic <= #`TCQ 1'b0;\n            else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t      wr_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n        always @(posedge RD_CLK) begin\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], sckt_wr_rst_ic};\n\tend\n        always @(posedge RD_CLK or posedge arst_sync_rd[1]) begin\n\t  if (arst_sync_rd[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n            wr_rst_rd_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            wr_rst_rd_ext  <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t    if (wr_rst_rd_ext[1]) begin\n\t      sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t      rd_rst_busy_i  <= #`TCQ 1'b0;\n\t    end\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic|arst_sync_wr[1];\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic|arst_sync_rd[1];\n      end // g7s_ic_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 1) begin : g7s_ic_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] arst_sync_rd  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        always @(posedge WR_CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n          rd_rst_wr_ext    <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_wr[RST_SYNC_STAGES-1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n          end else if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t    sckt_wr_rst_ic <= #`TCQ 1'b0;\n          else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t    wr_rst_busy_i  <= #`TCQ 1'b0;\n\tend\n        always @(posedge RD_CLK) begin\n\t  arst_sync_rd     <= #`TCQ {arst_sync_rd[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n          wr_rst_rd_ext    <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_rd[RST_SYNC_STAGES-1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n\t  end else if (wr_rst_rd_ext[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t    rd_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic;\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic;\n      end // g7s_ic_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 0) begin : g7s_cc_rst_nsckt\n        reg [1:0]              arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge CLK) begin\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0] | arst_sync_wr[1]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc | arst_sync_wr[1];\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 1) begin : g7s_cc_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n\n        always @(posedge CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc;\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst\n        assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;\n        assign rd_rst_busy = rst_reg;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = rst_reg;\n        always @* rst_full_ff_i  <= 1'b0;\n        always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;\n\n        always @(posedge CLK) begin\n          rst_delayed_d1 <= #`TCQ srst_delayed;\n          rst_delayed_d2 <= #`TCQ rst_delayed_d1;\n          if (rst_reg || rst_delayed_d2) begin\n            rst_active_i <= #`TCQ 1'b1;\n          end else begin\n            rst_active_i <= #`TCQ rst_reg;\n          end    \n        end   \n        always @(posedge CLK) begin\n          if (~rst_reg && srst_delayed) begin\n             rst_reg <= #`TCQ 1'b1;\n           end else if (rst_reg) begin\n             rst_reg <= #`TCQ 1'b0;\n           end else begin\n             rst_reg <= #`TCQ rst_reg;\n           end    \n        end   \n      end // g8s_cc_rst\n      else if (IS_8SERIES != 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_srst\n        assign wr_rst_busy = srst_delayed;\n        assign rd_rst_busy = srst_delayed;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = srst_delayed;\n        always @* rst_full_ff_i  <= 1'b0;\n      end // g7s_cc_srst\n  endgenerate \n\n  reg rst_d1 = 1'b0;\n  reg rst_d2 = 1'b0;\n  reg rst_d3 = 1'b0;\n  reg rst_d4 = 1'b0;\n  generate\n    if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1\n    // RST_FULL_GEN replaces the reset falling edge detection used to de-assert\n    // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.\n\n    // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &\n    // PROG_FULL\n\n      always @ (posedge rst_2_sync or posedge clk_2_sync) begin\n        if (rst_2_sync && C_EN_SAFETY_CKT == 0) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          rst_d3         <= 1'b1;\n          rst_d4         <= 1'b0;\n        end else begin\n          if (srst_delayed) begin\n            rst_d1         <= #`TCQ 1'b1;\n            rst_d2         <= #`TCQ 1'b1;\n            rst_d3         <= #`TCQ 1'b1;\n            rst_d4         <= #`TCQ 1'b0;\n          end else begin\n            rst_d1         <= #`TCQ wr_rst_busy;//1'b0;\n            rst_d2         <= #`TCQ rst_d1;\n            rst_d3         <= #`TCQ rst_d2 | sckt_wr_rst_i;\n            rst_d4         <= #`TCQ rst_d3;\n          end\n        end\n      end\n\n      always @* rst_full_ff_i  <= C_HAS_SRST ? 1'b0 : rst_d2 | sckt_wr_rst_i;\n      always @* rst_full_gen_i <= C_HAS_SRST ? rst_d4 : rst_d3;\n\n    end else if (C_EN_SAFETY_CKT == 1 && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full_sckt\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end\n  endgenerate // grstd1\n\nendmodule //fifo_generator_v13_2_5_CONV_VER\n\n\nmodule fifo_generator_v13_2_5_sync_stage\n  #(\n    parameter  C_WIDTH          = 10\n   )\n   (\n    input                     RST,\n    input                     CLK,\n    input       [C_WIDTH-1:0] DIN,\n    output reg  [C_WIDTH-1:0] DOUT = 0\n   );\n   always @ (posedge RST or posedge CLK) begin\n     if (RST)\n       DOUT <= 0;\n     else\n       DOUT <= #`TCQ DIN;\n   end\nendmodule // fifo_generator_v13_2_5_sync_stage\n\n/*******************************************************************************\n * Declaration of Independent-Clocks FIFO Module\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_as\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2 \n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input                                         SAFETY_CKT_WR_RST,\n   input                                         SAFETY_CKT_RD_RST,\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_ASSERT,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_NEGATE,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_ASSERT,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_NEGATE,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         RD_EN_USER,\n   input                                         RST,\n   input                                         RST_FULL_GEN,\n   input                                         RST_FULL_FF,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   input                                         INJECTDBITERR,\n   input                                         INJECTSBITERR,\n   input                                         USER_EMPTY_FB,\n   input                                         fab_read_data_valid_i,\n   input                                         read_data_valid_i,\n   input                                         ram_valid_i,\n   output reg                                    ALMOST_EMPTY = 1'b1,\n   output reg                                    ALMOST_FULL = C_FULL_FLAGS_RST_VAL,\n   output      [C_DOUT_WIDTH-1:0]                DOUT,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    EMPTY_FB = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL,\n   output                                        OVERFLOW,\n   output                                        PROG_EMPTY,\n   output                                        PROG_FULL,\n   output                                        VALID,\n   output      [C_RD_DATA_COUNT_WIDTH-1:0]       RD_DATA_COUNT,\n   output                                        UNDERFLOW,\n   output                                        WR_ACK,\n   output      [C_WR_DATA_COUNT_WIDTH-1:0]       WR_DATA_COUNT,\n   output                                        SBITERR,\n   output                                        DBITERR\n  );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   \n  \n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   \n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;\n   // Array that holds the error injection type (single/double bit error) on \n   // a specific write operation, which is returned on read to corrupt the\n   // output data.\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   //The amount of data stored in the FIFO at any time is given\n   // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK\n   // domain.\n   //num_wr_bits is calculated by considering the total words in the FIFO,\n   // and the state of the read pointer (which may not have yet crossed clock\n   // domains.)\n   //num_rd_bits is calculated by considering the total words in the FIFO,\n   // and the state of the write pointer (which may not have yet crossed clock\n   // domains.)\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   wire                        wr_rst_i = WR_RST;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n   wire                        rd_rst_i = RD_RST;\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n\n\n\n   // Delayed ram_rd_en is needed only for STD Embedded register option\n   generate\n     if (C_PRELOAD_LATENCY == 2) begin : grd_d\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n       end\n     end\n   endgenerate\n   \n    generate\n     if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n           fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n       end\n     end\n   endgenerate\n\n  \n\n   // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;\n     end else begin : rdl // Read depth lesser than or equal to write depth\n       assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n     end\n   endgenerate\n\n   // Generate Empty and Almost Empty\n  // ram_rd_en used to determine EMPTY should depend on the EMPTY.\n   assign ram_rd_en        = RD_EN & !EMPTY;\n   assign empty_int        = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));\n   assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));\n\n   // Register Empty and Almost Empty\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else begin\n         rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};\n\n         if (empty_int)\n           EMPTY           <= #`TCQ 1'b1;\n         else\n           EMPTY           <= #`TCQ 1'b0;\n\n         if (!EMPTY) begin\n           if (almost_empty_int)\n             ALMOST_EMPTY  <= #`TCQ 1'b1;\n           else\n             ALMOST_EMPTY  <= #`TCQ 1'b0;\n         end\n       end // rd_rst_i\n     end // always\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY_FB     <= 1'b1;\n       end else begin\n         if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else if (empty_int)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else\n           EMPTY_FB   <= #`TCQ 1'b0;\n       end // rd_rst_i\n     end // always\n\n   // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;\n     end else begin : wdl // Write depth lesser than or equal to read depth\n       assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n     end\n   endgenerate\n\n  // Generate FULL and ALMOST_FULL\n  // ram_wr_en used to determine FULL should depend on the FULL.\n  assign ram_wr_en       = WR_EN & !FULL;\n  assign full_int        = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));\n  assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));\n\n   // Register FULL and ALMOST_FULL Empty\n   always @ (posedge WR_CLK or posedge RST_FULL_FF)\n     begin\n       if (RST_FULL_FF & C_HAS_RST) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else begin\n         if (full_int) begin\n           FULL           <= #`TCQ 1'b1;\n         end else begin\n           FULL           <= #`TCQ 1'b0;\n         end\n\n         if (RST_FULL_GEN) begin\n           ALMOST_FULL    <= #`TCQ 1'b0;\n         end else if (!FULL) begin\n           if (almost_full_int)\n             ALMOST_FULL  <= #`TCQ 1'b1;\n           else\n             ALMOST_FULL  <= #`TCQ 1'b0;\n         end\n       end // wr_rst_i\n     end // always\n   always @ (posedge WR_CLK or posedge wr_rst_i)\n     begin\n       if (wr_rst_i) begin\n         wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};\n       end else begin\n         wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};\n       end // wr_rst_i\n     end // always\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i) begin\n           stage1_valid     <= 0;\n           stage2_valid     <= 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n   //Pointers passed into opposite clock domain\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_EMPTY.\n   wire [31:0] num_read_words_pe = \n     num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_FULL.\n   wire [31:0] num_write_words_pf =\n     num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n    \n    \n   /***************************************************************************\n    * Internal registers and wires\n    **************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire [C_DOUT_WIDTH-1:0] ideal_dout_out;      \n   wire valid_i;\n   wire valid_out1;\n   wire valid_out2;\n   wire valid_out;  \n   wire underflow_i;\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]               err_type                 = 0;\n   reg [1:0]               err_type_d1              = 0;\n   reg [1:0]               err_type_both              = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout               = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_d1            = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_both            = 0;\n   reg                     ideal_wr_ack             = 0;\n   reg                     ideal_valid              = 0;\n   reg                     ideal_overflow           = C_OVERFLOW_LOW;\n   reg                     ideal_underflow          = C_UNDERFLOW_LOW;\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   reg         valid_d1     = 0;\n   reg         valid_d2     = 0; \n   \n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n   \n\n  /****************************************************************************\n   * Function Declarations\n   ***************************************************************************/\n\n  /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n      if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n    end\n  endtask\n\n  /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n  /***********************************************************************\n  * hexstr_conv\n  *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n  ***********************************************************************/\n  function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_d2           = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n    end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the \n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n    wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;   \n   wire RD_CLK;\n   wire RD_EN;\n   wire RST;\n   wire WR_CLK;\n   wire WR_EN;\n    */\n\n   //***************************************************************************\n   // Dout may change behavior based on latency\n   //***************************************************************************\n   assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?\n                         ideal_dout_d1: ideal_dout;   \n   assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; \n\n   //***************************************************************************\n   // Assign SBITERR and DBITERR based on latency \n   //***************************************************************************\n   assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                    (C_PRELOAD_LATENCY == 2 &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?\n                    err_type_d1[0]: err_type[0]; \n   assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                    (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                    err_type_d1[1]: err_type[1]; \n  \n   //***************************************************************************\n   // Safety-ckt logic with embedded reg/fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n       //  if (C_HAS_VALID == 1) begin\n       //       assign valid_out = valid_d1;\n       //  end\n             \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)\n          begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else \n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n          end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                  @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n           end\n           else begin\n                   if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                   end\n             end \n           end  \n      end \n      endgenerate   \n\n//***************************************************************************\n   // Safety-ckt logic with embedded reg + fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else begin\n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n               fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n          end\n        end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   ideal_dout_both <= #`TCQ dout_reset_val;\n              end\n           end else begin\n             if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n              \n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n             end\n           end \n         end      \n      end \n      endgenerate    \n \n   //***************************************************************************\n   // Overflow may be active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_OVERFLOW==1) begin : blockOF1\n   assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n      end\n   endgenerate\n\n   assign PROG_EMPTY = ideal_prog_empty;\n   assign PROG_FULL  = ideal_prog_full;\n\n   //***************************************************************************\n   // Valid may change behavior based on latency or active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_VALID==1) begin : blockVL1\n   assign valid_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;\n   assign valid_out1 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?\n                       valid_d1: valid_i;  \n   assign valid_out2 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?\n                       valid_d2: valid_i; \n   assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;\n   assign VALID     = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Underflow may change behavior based on latency or active-low   \n   //***************************************************************************\n   generate\n      if (C_HAS_UNDERFLOW==1) begin : blockUF1\n   assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;\n   assign UNDERFLOW   = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n    end\n   endgenerate\n\n   //***************************************************************************\n   // Write acknowledge may be active low\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_ACK==1) begin : blockWK1\n   assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext\n\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_wr_pntr = 0;\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_rd_pntr = 0;\n      wire [C_PNTR_WIDTH-1:0]  diff_wr_rd_tmp;\n      wire [C_PNTR_WIDTH:0]    diff_wr_rd;\n      reg  [C_PNTR_WIDTH:0]    wr_data_count_i  = 0;\n        always @* begin\n          if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = 0;\n            adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n          end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin\n            adjusted_rd_pntr = rd_pntr_wr;\n            adjusted_wr_pntr = 0;\n            adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n          end else begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = rd_pntr_wr;\n          end\n        end // always @*\n\n        assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;\n        assign diff_wr_rd     = {1'b0,diff_wr_rd_tmp};\n\n        always @ (posedge wr_rst_i or posedge WR_CLK)\n        begin\n            if (wr_rst_i)\n              wr_data_count_i <= 0;\n            else\n              wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;\n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n\n        always @* begin\n          if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];\n          else\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n        end // always @*\n      end // wdc_fwft_ext\n   endgenerate\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   reg  [C_RD_PNTR_WIDTH:0]    rdc_fwft_ext_as  = 0;\n\n   generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n\n\n   always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= 0;\n            end else begin\n              if (!stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 0;\n              else if (!stage1_valid && stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 1;\n              else\n                rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;\n            end \n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n      end // rdc_fwft_ext\n end\n   endgenerate\n\n\n  generate if (C_USE_EMBEDDED_REG == 3) begin\n     if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n        wire [C_RD_PNTR_WIDTH:0]  diff_rd_wr_1;\n   //     assign diff_rd_wr_1 = diff_rd_wr +2'h2;\n\n       always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= #`TCQ 0;\n            end else begin\n          //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))\n          //    rdc_fwft_ext_as <= 1'b0;\n          //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) \n          //    rdc_fwft_ext_as <= 1'b1;\n          //else\n            rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;\n        end\n\n\n\nend\nend\nend\nendgenerate\n          \n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1) begin : grdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?\n          rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :\n          rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?\n          wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :\n          wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n\n  /**************************************************************************\n  * Assorted registers for delayed versions of signals\n  **************************************************************************/\n  //Capture delayed version of valid\n  generate\n      if (C_HAS_VALID==1) begin : blockVL2\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n      valid_d1 <= 1'b0;\n      valid_d2 <= 1'b0;\n    end else begin\n      valid_d1 <= #`TCQ valid_i;\n      valid_d2 <= #`TCQ valid_d1;\n    end \n//    if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin\n  //      valid_d2 <= #`TCQ valid_d1;\n      //  end \n  end \n      end\n endgenerate  \n   \n  //Capture delayed version of dout\n  /**************************************************************************\n    *embedded/fabric reg with no safety ckt\n    **************************************************************************/\n  generate \n       if (C_USE_EMBEDDED_REG < 3) begin\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n       if (C_USE_DOUT_RST == 1'b1) begin\n         @(posedge RD_CLK)\n           ideal_dout_d1   <= #`TCQ dout_reset_val;\n           ideal_dout   <= #`TCQ dout_reset_val;\n       end\n      // Reset err_type only if ECC is not selected\n      if (C_USE_ECC == 0)\n        err_type_d1     <= #`TCQ 0;\n     end else if (ram_rd_en_d1) begin\n      ideal_dout_d1   <= #`TCQ ideal_dout;\n      err_type_d1     <= #`TCQ err_type;\n           end    \n  end  \n   \nend  \nendgenerate \n/**************************************************************************\n    *embedded + fabric reg with no safety ckt\n    **************************************************************************/\n\ngenerate \n  if (C_USE_EMBEDDED_REG == 3) begin\n    always @(posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i == 1'b1) begin\n        if (C_USE_DOUT_RST == 1'b1) begin\n           @(posedge RD_CLK)\n             ideal_dout    <= #`TCQ dout_reset_val;\n             ideal_dout_d1   <= #`TCQ dout_reset_val;\n             ideal_dout_both   <= #`TCQ dout_reset_val;\n        end\n        // Reset err_type only if ECC is not selected\n        if (C_USE_ECC == 0) begin\n          err_type_d1     <= #`TCQ 0;\n          err_type_both   <= #`TCQ 0;\n        end\n      end else begin\n         if (ram_rd_en_d1) begin\n           ideal_dout_both   <= #`TCQ ideal_dout;\n           err_type_both     <= #`TCQ err_type;\n         end    \n         if (fab_rd_en_d1) begin\n           ideal_dout_d1   <= #`TCQ ideal_dout_both;\n           err_type_d1     <= #`TCQ err_type_both;\n         end\n      end\n    end  \n  end  \nendgenerate \n\n  \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate\n     if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n       always @(posedge WR_CLK) begin\n         ideal_overflow    <= #`TCQ WR_EN & FULL;\n       end\n     end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n       always @(posedge WR_CLK) begin\n         //ideal_overflow    <= #`TCQ WR_EN & (FULL | wr_rst_i);\n         ideal_overflow    <= #`TCQ WR_EN & (FULL );\n       end\n     end\n   endgenerate\n\n   generate\n     if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ EMPTY & RD_EN;\n       end\n     end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ (EMPTY) & RD_EN;\n         //ideal_underflow    <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;\n       end\n     end\n   endgenerate\n\n   /**************************************************************************\n   * Write/Read Pointer Synchronization\n   **************************************************************************/\n   localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;\n   wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   genvar gss;\n\n   generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst\n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (C_WR_PNTR_WIDTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_i), \n         .CLK      (RD_CLK), \n         .DIN      (wr_pntr_sync_stgs[gss-1]), \n         .DOUT     (wr_pntr_sync_stgs[gss])\n        );\n \n     fifo_generator_v13_2_5_sync_stage\n       #(\n         .C_WIDTH  (C_RD_PNTR_WIDTH)\n        )\n     wr_stg_inst\n        (\n         .RST      (wr_rst_i), \n         .CLK      (WR_CLK), \n         .DIN      (rd_pntr_sync_stgs[gss-1]), \n         .DOUT     (rd_pntr_sync_stgs[gss])\n        );\n   end endgenerate // Sync_stage_inst\n\n   assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;\n   assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;\n   always@* begin\n     wr_pntr_rd           <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n     rd_pntr_wr           <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n   end\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp\n     if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)\n       wr_pntr           <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)\n       wr_pntr           <= #`TCQ 0;\n   end\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (wr_rst_i == 1'b1) begin\n       num_wr_bits       <= 0;\n       next_num_wr_bits   = 0;\n       wr_ptr            <= C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= C_RD_DEPTH - 1;\n       ideal_wr_ack      <= 0;\n       ideal_wr_count    <= 0;\n       tmp_wr_listsize    = 0;\n       rd_ptr_wrclk_next <= 0;\n       wr_pntr_rd1       <= 0;\n\n     end else begin //wr_rst_i==0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       //If this is a write, handle the write by adding the value\n       // to the linked list, and updating all outputs appropriately\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD \n             >= C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full, but reporting full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //With DEPTH-1 words in the FIFO, it is almost_full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n\n           //If the FIFO is completely empty, but it is\n           // reporting FULL for some reason (like reset)\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=\n                C_FIFO_WR_DEPTH-2) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //FIFO is really not close to full, so change flag status.\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n           end //(tmp_wr_listsize == 0)\n\n         end else begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=\n              C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack       <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count     <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;\n\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //This write is CAUSING the FIFO to go full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is 2 from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == \n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits =  next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Still 2 from full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is not close to being full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <\n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //wr_rst_i==0\n   end // gen_fifo_w\n\n\n  /***************************************************************************\n   * Programmable FULL flags\n   ***************************************************************************/\n\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;\n\n   generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;\n   end else begin // STD\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;\n   end endgenerate\n\n   always @(posedge WR_CLK or posedge wr_rst_i) begin\n\n     if (wr_rst_i == 1'b1) begin\n       diff_pntr         <= 0;\n     end else begin\n       if (ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);\n       else if (!ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);\n    end\n  end\n\n\n   always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf\n\n     if (RST_FULL_FF & C_HAS_RST) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else begin\n\n       if (RST_FULL_GEN)\n         ideal_prog_full   <= #`TCQ 0;\n       //Single Programmable Full Constant Threshold\n       else if (C_PROG_FULL_TYPE == 1) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else\n             ideal_prog_full <= #`TCQ 0;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Constant Thresholds\n       end else if (C_PROG_FULL_TYPE == 2) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else if (diff_pntr < pf_thr_negate_val)\n             ideal_prog_full <= #`TCQ 0;\n           else\n             ideal_prog_full <= #`TCQ ideal_prog_full;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Single Programmable Full Threshold Input\n       end else if (C_PROG_FULL_TYPE == 3) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH)\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Threshold Inputs\n       end else if (C_PROG_FULL_TYPE == 4) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH_ASSERT)\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < PROG_FULL_THRESH_NEGATE)\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       end // C_PROG_FULL_TYPE\n\n     end //wr_rst_i==0\n   end //\n\n   \n   /**************************************************************************\n   * Read Domain Logic\n   **************************************************************************/\n\n\n   /*********************************************************\n    * Programmable EMPTY flags\n    *********************************************************/\n   //Determine the Assert and Negate thresholds for Programmable Empty\n\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd      = 0;\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe\n\n     if (rd_rst_i & C_HAS_RST) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else begin\n       if (ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;\n       else if (!ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr);\n       else\n         diff_pntr_rd       <=  #`TCQ diff_pntr_rd;\n  \n       if (C_PROG_EMPTY_TYPE == 1) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 2) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 3) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 4) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end  //C_PROG_EMPTY_TYPE\n     end\n   end // gen_pe\n\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;\n   end endgenerate // single_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;\n   end endgenerate // multiple_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;\n   end endgenerate // single_multiple_pe_thr_const\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp\n     if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n       rd_pntr            <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)\n       rd_pntr            <= #`TCQ 0;\n   end\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rd_rst_i & C_HAS_RST) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n     end else begin //rd_rst_i==0\n\n       rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 1\n       /*****************************************************************/\n       if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Reminder that FIFO is still empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end // if (tmp_rd_listsize <= 0)\n\n             //If the FIFO is one from empty, but it is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 1)\n\n             //If the FIFO is two from empty, and is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Fifo has two words, so is neither empty or almost empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 2)\n\n             //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid <= #`TCQ 1'b0;\n                 //Note that the FIFO is No Longer Empty or Almost Empty\n\n                 ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n               end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n             end // else: if(ideal_empty == 1'b1)\n\n           else //if (ideal_empty == 1'b0)\n             begin\n\n               //If the FIFO is completely full, and we are successfully reading from it\n               if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)\n\n               //If the FIFO is not close to being empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n               //If the FIFO is two from empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Fifo is not yet empty. It is going almost_empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n\n               //If the FIFO is one from empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Note that FIFO is GOING empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 1)\n\n\n               //If the FIFO is completely empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n                 begin\n                   //Do not change the contents of the FIFO\n\n                   //Do not acknowledge the read from empty FIFO\n                   ideal_valid        <= #`TCQ 1'b0;\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize <= 0)\n\n             end // if (ideal_empty == 1'b0)\n\n           end //(RD_EN == 1'b1)\n\n         else //if (RD_EN == 1'b0)\n           begin\n             //If user did not attempt a read, do not give an ack or err\n             ideal_valid          <= #`TCQ 1'b0;\n\n             ideal_rd_count       <= #`TCQ num_read_words_sized_i;\n\n           end // else: !if(RD_EN == 1'b1)\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 0\n       /*****************************************************************/\n       end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty, but it is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty, and is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Fifo has two words, so is neither empty or almost empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                         (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that the FIFO is No Longer Empty or Almost Empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n           end else begin\n\n             //If the FIFO is completely full, and we are successfully reading from it\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is not close to being empty\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                          (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Fifo is not yet empty. It is going almost_empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Note that FIFO is GOING empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is completely empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if (tmp_rd_listsize <= 0)\n\n           end // if (ideal_empty == 1'b0)\n\n         end else begin//(RD_EN == 1'b0)\n\n         \n           //If user did not attempt a read, do not give an ack or err\n           ideal_valid           <= #`TCQ 1'b0;\n           ideal_rd_count        <= #`TCQ num_read_words_sized_i;\n\n         end // else: !if(RD_EN == 1'b1)\n       end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //rd_rst_i==0\n   end //always gen_fifo_r_as\n\nendmodule // fifo_generator_v13_2_5_bhv_ver_as\n\n\n/*******************************************************************************\n * Declaration of Low Latency Asynchronous FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_beh_ver_ll_afifo\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_FIFO_TYPE                    = 0\n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   output reg  [C_DOUT_WIDTH-1:0]                DOUT = 0,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL\n  );\n\n  //-----------------------------------------------------------------------------\n  // Low Latency Asynchronous FIFO\n  //-----------------------------------------------------------------------------\n\n  // Memory which will be used to simulate a FIFO\n  reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n  integer i;\n  initial begin\n    for (i = 0; i < C_WR_DEPTH; i = i + 1)\n      memory[i] = 0;\n  end\n\n  reg  [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;\n  wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;\n  reg  [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;\n  reg                        ll_afifo_full    = 1'b0;\n  reg                        ll_afifo_empty   = 1'b1;\n  wire                       write_allow;\n  wire                       read_allow;\n\n  assign write_allow = WR_EN & ~ll_afifo_full;\n  assign read_allow  = RD_EN & ~ll_afifo_empty;\n\n  //-----------------------------------------------------------------------------\n  // Write Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      wr_pntr_ll_afifo   <= 0;\n    else if (write_allow)\n      wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Read Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      rd_pntr_ll_afifo_q   <= 0;\n    else\n      rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;\n  end\n  assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;\n  \n  //-----------------------------------------------------------------------------\n  // Fill the Memory\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK) begin\n    if (write_allow)\n      memory[wr_pntr_ll_afifo] <= #`TCQ DIN;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate DOUT\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK) begin\n      DOUT <= #`TCQ memory[rd_pntr_ll_afifo];\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate EMPTY\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      ll_afifo_empty   <= 1'b1;\n    else\n      ll_afifo_empty   <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | \n                           (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate FULL\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      ll_afifo_full   <= 1'b1;\n    else\n      ll_afifo_full   <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | \n                           (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));\n  end\n\n  always @* begin\n    FULL  <= ll_afifo_full;\n    EMPTY <= ll_afifo_empty;\n  end\n\nendmodule // fifo_generator_v13_2_5_beh_ver_ll_afifo\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_ss\n   \n  /**************************************************************************\n   * Declare user parameters and their defaults\n   *************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0 \n   )\n   \n  /**************************************************************************\n   * Declare Input and Output Ports\n   *************************************************************************/\n   (\n    //Inputs\n    input                                 SAFETY_CKT_WR_RST,\n    input                                 CLK,\n    input       [C_DIN_WIDTH-1:0]         DIN,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_ASSERT,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_NEGATE,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_ASSERT,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_NEGATE,\n    input                                 RD_EN,\n    input                                 RD_EN_USER,\n    input                                 USER_EMPTY_FB,\n    input                                 RST,\n    input                                 RST_FULL_GEN,\n    input                                 RST_FULL_FF,\n    input                                 SRST,\n    input                                 WR_EN,\n    input                                 INJECTDBITERR,\n    input                                 INJECTSBITERR,\n    input                                 WR_RST_BUSY,\n    input                                 RD_RST_BUSY,\n                                    \n    //Outputs                       \n    output                                ALMOST_EMPTY,\n    output                                ALMOST_FULL,\n    output reg   [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,\n    output       [C_DOUT_WIDTH-1:0]       DOUT,\n    output                                EMPTY,\n    output reg                            EMPTY_FB = 1'b1,\n    output                                FULL,\n    output                                OVERFLOW,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]    RD_DATA_COUNT,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]    WR_DATA_COUNT,\n    output                                PROG_EMPTY,\n    output                                PROG_FULL,\n    output                                VALID,\n    output                                UNDERFLOW,\n    output                                WR_ACK,\n    output                                SBITERR,\n    output                                DBITERR\n   );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;\n   wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n   localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; \n\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n   localparam  EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //localparam  EXTRA_WORDS_PE_PARAM  = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not \n   //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.\n   // Therefore, during SRST, all the FULL flags reset to 0.\n   localparam                      C_HAS_FAST_FIFO = 0;\n   localparam                      C_FIFO_WR_DEPTH = C_WR_DEPTH;\n   localparam                      C_FIFO_RD_DEPTH = C_RD_DEPTH;\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;\n   localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;\n   localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;\n   localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n  localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; \n  localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; \n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   \n   /**************************************************************************\n    * Internal Registers and wires\n    *************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire                           underflow_i;\n   wire                           valid_i;\n   wire                           valid_out;\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_reg = 1'b0;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n   wire                         srst_rrst_busy;\n\n\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]                      err_type           = 0;\n   reg [1:0]                      err_type_d1        = 0;\n   reg [1:0]                      err_type_both      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout         = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_d1      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_both      = 0;\n   wire [C_DOUT_WIDTH-1:0]        ideal_dout_out;\n   wire                           fwft_enabled;\n   reg                            ideal_wr_ack       = 0;\n   reg                            ideal_valid        = 0;\n   reg                            ideal_overflow     = C_OVERFLOW_LOW;\n   reg                            ideal_underflow    = C_UNDERFLOW_LOW;\n\n   reg                            full_i             = C_FULL_FLAGS_RST_VAL;\n   reg                            full_i_temp        = 0;\n   reg                            empty_i            = 1;\n   reg                            almost_full_i      = 0;\n   reg                            almost_empty_i     = 1;\n   reg                            prog_full_i        = 0;\n   reg                            prog_empty_i       = 1;\n   reg [C_WR_PNTR_WIDTH-1:0]      wr_pntr            = 0;\n   reg [C_RD_PNTR_WIDTH-1:0]      rd_pntr            = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg [C_RD_PNTR_WIDTH-1:0]      diff_count         = 0;\n\n   reg                            write_allow_q      = 0;\n   reg                            read_allow_q       = 0;\n   reg                            valid_d1           = 0;\n   reg                            valid_both           = 0;\n   reg                            valid_d2           = 0;\n   wire                           rst_i;\n   wire                           srst_i;\n\n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]         dout_reset_val = 0;\n\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n\n\n\n   /****************************************************************************\n    * Function Declarations\n    ***************************************************************************/\n\n   /****************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***************************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin\n        case (def_data[7:0])\n          8'b00000000 : begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default : begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1) begin\n          if ((index*4)+j < C_DOUT_WIDTH) begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   //reg         valid_d1     = 0;\n   \n   \n   //user specified value for reseting the size of the fifo\n   //reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n\n\n /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n     if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n\n     end\n  endtask\n\n\n   \n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_dout_both    = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_both         = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n\n   end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the\n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n   wire CLK;\n   wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;\n   wire RD_EN;\n   wire RST;\n   wire WR_EN;\n    */\n\n  // Assign ALMOST_EPMTY\n  generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae\n    assign ALMOST_EMPTY = almost_empty_i;\n  end else begin : gnae\n    assign ALMOST_EMPTY = 0;\n  end endgenerate // gae\n\n  // Assign ALMOST_FULL\n  generate if (C_HAS_ALMOST_FULL==1) begin : gaf\n    assign ALMOST_FULL  = almost_full_i;\n  end else begin : gnaf\n    assign ALMOST_FULL  = 0;\n  end endgenerate // gaf\n\n   // Dout may change behavior based on latency\n  localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?\n                         ideal_dout_d1: ideal_dout; \n  assign DOUT = ideal_dout_out;\n\n  // Assign SBITERR and DBITERR based on latency \n  assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[0]: err_type[0]; \n  assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[1]: err_type[1]; \n\n  assign EMPTY         = empty_i;\n  assign FULL          = full_i;\n  //saftey_ckt with one register\n\n  generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)\n          begin\n          if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n              valid_d1 <= #`TCQ 1'b0;\n          end\n          else begin\n               ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n               valid_d1 <= #`TCQ valid_i;\n          end\n          end\n          \n           always@(posedge rst_delayed_sft2 or posedge CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n              end\n           else if (srst_rrst_busy == 1'b1) begin\n                   if (C_USE_DOUT_RST == 1'b1) begin\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   end\n           end else if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                end\n           end   \n      end //if \n      endgenerate   \n\n//safety ckt with both registers\n\ngenerate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK) begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            valid_d1 <= #`TCQ 1'b0;\n          end else begin\n            ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n            fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n            valid_both <= #`TCQ valid_i;\n            valid_d1 <= #`TCQ valid_both;\n          end\n        end\n\n        always@(posedge rst_delayed_sft2 or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                  ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else if (srst_rrst_busy == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else begin \n            if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n            end\n          end\n        end\n      end //if \n      endgenerate    \n \n \n  //Overflow may be active-low\n  generate if (C_HAS_OVERFLOW==1) begin : gof\n    assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n  end else begin : gnof\n    assign OVERFLOW = 0;\n  end endgenerate // gof\n\n  assign PROG_EMPTY    = prog_empty_i;\n  assign PROG_FULL     = prog_full_i;\n\n   //Valid may change behavior based on latency or active-low\n  generate if (C_HAS_VALID==1) begin : gvalid\n    assign valid_i       = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;\n    assign valid_out     = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?\n                            valid_d1 : valid_i; \n    assign VALID         = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n  end else begin : gnvalid\n    assign VALID         = 0;\n  end endgenerate // gvalid\n\n  //Trim data count differently depending on set widths\n  generate if (C_HAS_DATA_COUNT == 1) begin : gdc\n    always @* begin\n      diff_count <= wr_pntr - rd_pntr;\n      if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin\n        DATA_COUNT[C_RD_PNTR_WIDTH-1:0]  <= diff_count;\n        DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; \n      end else begin\n        DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];\n      end\n    end\n//  end else begin : gndc\n//    always @* DATA_COUNT <= 0;\n  end endgenerate // gdc\n\n  //Underflow may change behavior based on latency or active-low\n  generate if (C_HAS_UNDERFLOW==1) begin : guf\n    assign underflow_i   = ideal_underflow;\n    assign UNDERFLOW     = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n  end else begin : gnuf\n    assign UNDERFLOW     = 0;\n  end endgenerate // guf\n \n\n  //Write acknowledge may be active low \n  generate if (C_HAS_WR_ACK==1) begin : gwr_ack\n    assign WR_ACK        = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n  end else begin : gnwr_ack\n    assign WR_ACK        = 0;\n  end endgenerate // gwr_ack\n\n\n  /*****************************************************************************\n   * Internal reset logic \n   ****************************************************************************/\n  assign srst_i        = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;\n  assign rst_i            = C_HAS_RST ? RST : 0;\n  assign srst_wrst_busy   = srst_i;\n  assign srst_rrst_busy   = srst_i;\n\n   /**************************************************************************\n    * Assorted registers for delayed versions of signals\n    **************************************************************************/\n   //Capture delayed version of valid\n   generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20\n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1 <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n           end else begin\n              valid_d1 <= #`TCQ valid_i;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n     end \n   endgenerate // blockVL20\n\n  generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin \n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1   <= 1'b0;\n           valid_both <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n              valid_both <= #`TCQ 1'b0;\n              \n           end else begin\n              valid_both <= #`TCQ valid_i;\n               valid_d1 <= #`TCQ valid_both;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n  end\n endgenerate // blockVL20\n\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge CLK or posedge rst_i) begin\n         if (rst_i) begin\n           stage1_valid     <= #`TCQ 0;\n           stage2_valid     <= #`TCQ 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n\n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc\n       assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc\n       assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n   \n   //reg ram_rd_en_d1 = 1'b0;\n   //Capture delayed version of dout\n   generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         ram_rd_en_d1 <= #`TCQ 1'b0;\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n        end\n      end else begin\n         ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n         if (srst_rrst_busy) begin\n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            // Reset err_type only if ECC is not selected\n            if (C_USE_ECC == 0) begin\n               err_type_d1   <= #`TCQ 0;\n               err_type_both <= #`TCQ 0;\n            end\n            // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n            if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n            end \n         if (C_USE_DOUT_RST == 1) begin\n           // @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         end else begin\n            if (ram_rd_en_d1 ) begin\n            ideal_dout_d1 <= #`TCQ ideal_dout;\n            err_type_d1   <= #`TCQ err_type;\n            end\n         end\n      end    \n   end   // always\nend\nendgenerate \n\n//no safety ckt with both registers\n generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n          ram_rd_en_d1 <= #`TCQ 1'b0;\n          fab_rd_en_d1 <= #`TCQ 1'b0;\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val; \n            \n      end\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val;\n       end\n      end else begin\n         if (srst_rrst_busy) begin \n           ram_rd_en_d1 <= #`TCQ 1'b0;\n           fab_rd_en_d1 <= #`TCQ 1'b0;\n           // Reset err_type only if ECC is not selected\n           if (C_USE_ECC == 0) begin\n              err_type_d1   <= #`TCQ 0;\n              err_type_both <= #`TCQ 0;\n           end\n           // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n           if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n              ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end \n           if (C_USE_DOUT_RST == 1) begin\n             ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end\n         end else begin\n           ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n           fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);\n           if (ram_rd_en_d1 ) begin\n             ideal_dout_both <= #`TCQ ideal_dout;\n             err_type_both   <= #`TCQ err_type;\n           end\n           if (fab_rd_en_d1 ) begin\n             ideal_dout_d1 <= #`TCQ ideal_dout_both;\n             err_type_d1   <= #`TCQ err_type_both;\n           end\n         end\n      end    \n   end   // always\nend\nendgenerate \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n     always @(posedge CLK) begin\n       ideal_overflow    <= #`TCQ WR_EN & full_i;\n     end\n   end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n     always @(posedge CLK) begin\n       //ideal_overflow    <= #`TCQ WR_EN & (rst_i | full_i);\n       ideal_overflow    <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);\n     end\n   end endgenerate // blockOF20\n \n   generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n     always @(posedge CLK) begin\n       ideal_underflow   <= #`TCQ empty_i & RD_EN;\n     end\n   end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n     always @(posedge CLK) begin\n       //ideal_underflow   <= #`TCQ (rst_i | empty_i) & RD_EN;\n       ideal_underflow   <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;\n     end\n   end endgenerate // blockUF20\n\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n\n  /*************************************************************************\n   * Write and Read Logic  \n   ************************************************************************/\n   wire              write_allow;\n   wire              read_allow;\n   wire              read_allow_dc;\n   wire              write_only;\n   wire              read_only;\n   //wire              write_only_q;\n   reg              write_only_q;\n   //wire              read_only_q;\n   reg              read_only_q;\n   reg              full_reg;\n   reg              rst_full_ff_reg1;\n   reg              rst_full_ff_reg2;\n   wire              ram_full_comb;\n   wire              carry;\n   \n   assign write_allow  = WR_EN & ~full_i;\n   assign read_allow   = RD_EN & ~empty_i;\n   assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;\n   //assign write_only   = write_allow & ~read_allow;\n   //assign write_only_q = write_allow_q;\n   //assign read_only    = read_allow    & ~write_allow;\n   //assign read_only_q  = read_allow_q ;\n   wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;\n   wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;\n   wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;\n\n   assign diff_pntr_pe_max = DIFF_MAX_RD;\n   assign diff_pntr_max = DIFF_MAX_WR;\n\n\n\n   generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym\n    assign write_only   = write_allow & ~read_allow;\n    assign read_only    = read_allow    & ~write_allow;\n    end endgenerate\n    generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd\n     assign read_only   = read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;\n     assign write_only    = write_allow    & ~(read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n    generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr\n     assign read_only   = read_allow & ~(write_allow  & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n     assign write_only    = write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;\n    end endgenerate\n\n\n   //-----------------------------------------------------------------------------\n   // Write and Read pointer generation\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       wr_pntr         <= 0;\n       rd_pntr         <= 0;\n     end else begin\n       if (srst_i) begin\n         wr_pntr       <= #`TCQ 0;\n         rd_pntr       <= #`TCQ 0;\n       end else begin\n         if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;\n         if (read_allow)  rd_pntr <= #`TCQ rd_pntr + 1;\n       end\n     end\n   end\n\n   generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout\n   always @(posedge CLK) begin\n     if (write_allow) begin\n       if (ENABLE_ERR_INJECTION == 1)\n         memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};\n       else\n         memory[wr_pntr] <= #`TCQ DIN;\n     end\n   end\n\n   reg  [C_DATA_WIDTH-1:0] dout_tmp_q;\n   reg [C_DATA_WIDTH-1:0] dout_tmp = 0;\n   reg  [C_DATA_WIDTH-1:0] dout_tmp1 = 0;\n   always @(posedge CLK) begin\n     dout_tmp_q <= #`TCQ ideal_dout;\n   end\n\n\n\n     always @* begin\n       if (read_allow)\n         ideal_dout <= memory[rd_pntr];\n       else\n         ideal_dout <= dout_tmp_q;\n     end\n   end endgenerate // gll_dm_dout\n\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   assign ram_rd_en        = RD_EN & !EMPTY;\n\n   //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   generate if (C_FIFO_TYPE != 2) begin : gnll_din\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i == 1'b1) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n\n     end else begin //rst_i==0\n     if (srst_wrst_busy) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n     end else begin//srst_i=0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n         end else begin\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error  \n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           //end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //srst_i==0\n     end //wr_rst_i==0\n   end // gen_fifo_w\n    end endgenerate\n\n   generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout\n     always @(posedge CLK) begin\n       if (rst_i || srst_rrst_busy) begin\n         if (C_USE_DOUT_RST == 1) begin\n           ideal_dout <= #`TCQ dout_reset_val;\n           ideal_dout_both <= #`TCQ dout_reset_val;\n         end\n       end\n     end\n    end endgenerate\n\n\n\n\n   generate if (C_FIFO_TYPE != 2) begin : gnll_dout\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_r\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n\n     end else begin //rd_rst_i==0\n     if (srst_rrst_busy) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets synchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= #`TCQ 0;\n         err_type_both    <= #`TCQ 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n      end //srst_i\n      else begin\n\n       //rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n         if (RD_EN == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end \n           else \n             begin\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n         end\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //s_rst_i==0\n     end //rd_rst_i==0\n   end //always\n  end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate diff_pntr for PROG_FULL generation\n   // Generate diff_pntr_pe for PROG_EMPTY generation\n   //-----------------------------------------------------------------------------\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         write_only_q   <= 1'b0;\n         read_only_q    <= 1'b0;\n         diff_pntr_reg1       <= 0;\n         diff_pntr_pe_reg1    <= 0;\n         diff_pntr_reg2       <= 0;\n         diff_pntr_pe_reg2    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_rrst_busy) begin\n           read_only_q  <= #`TCQ 1'b0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n           diff_pntr_pe_reg2  <= #`TCQ 0;\n          end\n          if (srst_wrst_busy) begin\n           write_only_q <= #`TCQ 1'b0;\n           diff_pntr_reg1     <= #`TCQ 0;\n           diff_pntr_reg2     <= #`TCQ 0;\n          end\n         end else begin\n           write_only_q <= #`TCQ write_only;\n           read_only_q  <= #`TCQ read_only;\n           diff_pntr_reg2  <= #`TCQ diff_pntr_reg1;\n           diff_pntr_pe_reg2  <= #`TCQ diff_pntr_pe_reg1;\n\n           // Add 1 to the difference pointer value when only write happens.\n           if (write_only)  \n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;\n           else\n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;\n\n           // Add 1 to the difference pointer value when write or both write & read or no write & read happen.\n           if (read_only)  \n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;\n           else\n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;\n         end\n       end\n     end\n   assign diff_pntr_pe = diff_pntr_pe_reg1;\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow\n\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym\n    assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};\n    assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         diff_pntr_pe_asym    <= 0;\n         diff_pntr_reg1       <= 0;\n         full_reg             <= 0;\n         rst_full_ff_reg1     <= 1;\n         rst_full_ff_reg2     <= 1;\n         diff_pntr_pe_reg1    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_wrst_busy)\n           diff_pntr_reg1     <= #`TCQ 0;\n          if (srst_rrst_busy)\n           full_reg             <=  #`TCQ 0;\n           rst_full_ff_reg1     <=  #`TCQ 1;\n           rst_full_ff_reg2     <=  #`TCQ 1;\n           diff_pntr_pe_asym    <=  #`TCQ 0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n         end else begin\n             diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;\n             full_reg          <= #`TCQ full_i;\n             rst_full_ff_reg1  <=  #`TCQ RST_FULL_FF;\n             rst_full_ff_reg2  <=  #`TCQ rst_full_ff_reg1;\n           if (~full_i) begin  \n             diff_pntr_reg1 <=  #`TCQ wr_pntr - adj_rd_pntr_wr;\n          end\n         end\n       end\n     end\n   assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));\n   assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow_asym\n\n\n   //-----------------------------------------------------------------------------\n   // Generate FULL flag\n   //-----------------------------------------------------------------------------\n   wire                 comp0;\n   wire                 comp1;\n   wire                 going_full;\n   wire                 leaving_full;\n \n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin :  gpad \t\n    assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;\n    assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin :  gtrim \n    assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n  end endgenerate\n\n   assign comp1         = (adj_rd_pntr_wr == (wr_pntr + 1'b1));\n   assign comp0         = (adj_rd_pntr_wr == wr_pntr);\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp\n     assign going_full    = (comp1 & write_allow & ~read_allow);\n     assign leaving_full  = (comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym\n      assign going_full = (comp1 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_full = (comp0 & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp \n      assign going_full = (comp1 & write_allow & ~read_allow);\n      assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n\n   assign ram_full_comb = going_full | (~leaving_full & full_i);\n\n   generate if (C_HAS_RST == 1) begin : grst_full\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF & C_HAS_RST)\n         full_i   <= C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_SRST == 1) begin : gsrst_full\n     always @(posedge CLK) begin\n       if (srst_wrst_busy)\n         full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_full\n     always @(posedge CLK) begin\n         full_i   <= #`TCQ ram_full_comb;\n     end\n   end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate EMPTY flag\n   //-----------------------------------------------------------------------------\n   wire                 ecomp0;\n   wire                 ecomp1;\n   wire                 going_empty;\n   wire                 leaving_empty;\n   wire                 ram_empty_comb;\n\n  \n generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin :  pad \t\n    assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n    assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin :  trim \n    assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n  end endgenerate\n\n   assign ecomp1         = (adj_wr_pntr_rd == (rd_pntr + 1'b1));\n   assign ecomp0         = (adj_wr_pntr_rd == rd_pntr);\n\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp\n     assign going_empty    = (ecomp1 & ~write_allow & read_allow);\n     assign leaving_empty  = (ecomp0 & write_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp\n      assign going_empty = (ecomp1 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_empty = (ecomp0 & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp \n      assign going_empty = (ecomp1 & ~write_allow & read_allow);\n      assign leaving_empty =(ecomp0 & write_allow);\n    end endgenerate\n\n\n\n    assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);\n\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       empty_i  <= 1'b1;\n     else if (srst_rrst_busy)\n       empty_i  <= #`TCQ 1'b1;\n     else\n       empty_i  <= #`TCQ ram_empty_comb;\n    end\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       EMPTY_FB     <= 1'b1;\n     end else begin\n       if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))\n         EMPTY_FB   <= #`TCQ 1'b1;\n       else\n         EMPTY_FB   <= #`TCQ ram_empty_comb;\n     end\n   end // always\n\n   //-----------------------------------------------------------------------------\n   // Generate Read and write data counts for asymmetic common clock\n   //-----------------------------------------------------------------------------\n\n    reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; \n    wire [C_GRTR_PNTR_WIDTH :0] ratio; \n    wire decr_by_one;\n    wire incr_by_ratio;\n    wire incr_by_one;\n    wire decr_by_ratio;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n\n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr \n      assign ratio         = C_DEPTH_RATIO_RD;\n      assign decr_by_one   = (IS_FWFT == 1)? read_allow_dc : read_allow;\n      assign incr_by_ratio = write_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (decr_by_one) begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc - 1;\n           else\n\t    count_dc <= #`TCQ count_dc - 1  + ratio ;\n\t end\n\t else begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc + ratio ;\n\tend\n       end\n       end\n\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n\n    end endgenerate\n\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd \n      assign ratio         = C_DEPTH_RATIO_WR;\n      assign incr_by_one   = write_allow;\n      assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (incr_by_one) begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc + 1;\n           else\n\t    count_dc <= #`TCQ count_dc + 1  - ratio ;\n\t end\n\t else begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc - ratio ;\n\tend\n       end\n       end\n\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n\n    end endgenerate\n\n\n\n\n\n\n   //-----------------------------------------------------------------------------\n   // Generate WR_ACK flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_wr_ack  <= 1'b0;\n     else if (srst_wrst_busy)\n       ideal_wr_ack  <= #`TCQ 1'b0;\n     else if (WR_EN & ~full_i)\n       ideal_wr_ack  <= #`TCQ 1'b1;\n     else\n       ideal_wr_ack  <= #`TCQ 1'b0;\n    end\n\n   //-----------------------------------------------------------------------------\n   // Generate VALID flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_valid  <= 1'b0;\n     else if (srst_rrst_busy)\n       ideal_valid  <= #`TCQ 1'b0;\n     else if (RD_EN & ~empty_i)\n       ideal_valid  <= #`TCQ 1'b1;\n     else\n       ideal_valid  <= #`TCQ 1'b0;\n    end\n\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_FULL flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss\n\n     wire                 fcomp2;\n     wire                 going_afull;\n     wire                 leaving_afull;\n     wire                 ram_afull_comb;\n\n\n   assign fcomp2         = (adj_rd_pntr_wr == (wr_pntr + 2'h2));\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp\n     assign going_afull    = (fcomp2 & write_allow & ~read_allow);\n     assign leaving_afull  = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym\n      assign going_afull = (fcomp2 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_afull = (comp1 & (~write_allow) & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp \n      assign going_afull = (fcomp2 & write_allow & ~read_allow);\n      assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n     assign ram_afull_comb  = going_afull | (~leaving_afull & almost_full_i);\n\n\n    generate if (C_HAS_RST == 1) begin : grst_afull\n      always @(posedge CLK or posedge RST_FULL_FF) begin\n        if (RST_FULL_FF & C_HAS_RST)\n          almost_full_i   <= C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_SRST == 1) begin : gsrst_afull\n      always @(posedge CLK) begin\n        if (srst_wrst_busy)\n          almost_full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_afull\n      always @(posedge CLK) begin\n          almost_full_i   <= #`TCQ ram_afull_comb;\n      end\n    end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_EMPTY flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss\n\n     wire                 ecomp2;\n     wire                 going_aempty;\n     wire                 leaving_aempty;\n     wire                 ram_aempty_comb;\n      \n     assign ecomp2          = (adj_wr_pntr_rd == (rd_pntr + 2'h2));\n   \n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp\n     assign going_aempty    = (ecomp2 & ~write_allow & read_allow);\n     assign leaving_aempty  = (ecomp1 & write_allow & ~read_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp\n      assign going_aempty = (ecomp2 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp \n      assign going_aempty = (ecomp2 & ~write_allow & read_allow);\n      assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);\n    end endgenerate\n\n\n     assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);\n\n     always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         almost_empty_i  <= 1'b1;\n       else if (srst_rrst_busy)\n         almost_empty_i  <= #`TCQ 1'b1;\n       else\n         almost_empty_i  <= #`TCQ ram_aempty_comb;\n      end\n  // end endgenerate // gae_ss\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL\n   //-----------------------------------------------------------------------------\n\n   localparam  C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT \n                                  C_PROG_FULL_THRESH_ASSERT_VAL; // STD\n   localparam  C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT\n                                  C_PROG_FULL_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;   \n   generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin \n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n          prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr>= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  ((diff_pntr) < C_PF_ASSERT_VAL )\n        prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate // single_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr >= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n       else if  (diff_pntr < C_PF_NEGATE_VAL)\n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate //multiple_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT\n                                               PROG_FULL_THRESH; // STD\n   generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input\n\n     always @(posedge CLK or posedge RST_FULL_FF) begin//0\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin //1\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin//2 \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin//3\n           if (diff_pntr > pf3_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if (diff_pntr == pf3_assert_val) begin//4\n             if (read_only_q)\n               prog_full_i <= #`TCQ 1'b0;\n             else\n               prog_full_i <= #`TCQ 1'b1;\n           end else//4\n             prog_full_i <= #`TCQ 1'b0;\n         end else//3\n           prog_full_i <= #`TCQ prog_full_i;\n       end //2\n       else begin//5\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin//6 \n        if (diff_pntr >= pf3_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  (diff_pntr < pf3_assert_val) begin//7\n         prog_full_i <= #`TCQ 1'b0;\n       end//7\n       end//6\n      else\n           prog_full_i <= #`TCQ prog_full_i;\n       end//5\n     end//1\n     end//0\n   end endgenerate //single_pf_input\n  \n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_ASSERT; // STD\n   wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_NEGATE; // STD\n\n   generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin\n           if (diff_pntr >= pf_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if ((diff_pntr == pf_negate_val && read_only_q) ||\n                  diff_pntr < pf_negate_val)\n             prog_full_i <= #`TCQ 1'b0;\n           else\n             prog_full_i <= #`TCQ prog_full_i;\n         end else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin \n        if (diff_pntr >= pf_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n       else if (diff_pntr < pf_negate_val) \n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n\n     end\n   end\n   end endgenerate //multiple_pf_inputs\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY\n   //-----------------------------------------------------------------------------\n   localparam  C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD\n   localparam  C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i) \n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy) \n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL)\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > C_PE_ASSERT_VAL)\n         prog_empty_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n     end\n     end\n   end endgenerate // single_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > C_PE_NEGATE_VAL) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n\n     end\n\n     end\n   end endgenerate //multiple_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH -2) : // FWFT\n                                                PROG_EMPTY_THRESH; // STD\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe < pe3_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (diff_pntr_pe == pe3_assert_val) begin\n             if (write_only_q)\n               prog_empty_i <= #`TCQ 1'b0;\n             else\n               prog_empty_i <= #`TCQ 1'b1;\n           end else\n             prog_empty_i <= #`TCQ 1'b0;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe3_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > pe3_assert_val)\n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n\n     end\n   end endgenerate // single_pe_input\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_ASSERT; // STD\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_NEGATE; // STD\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n      else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe <= pe4_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || \n                     (diff_pntr_pe > pe4_negate_val)) begin\n             prog_empty_i <= #`TCQ 1'b0;\n           end else\n             prog_empty_i <= #`TCQ prog_empty_i;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe4_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > pe4_negate_val) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n     end\n   end endgenerate // multiple_pe_inputs\n\nendmodule // fifo_generator_v13_2_5_bhv_ver_ss\n\n\n\n/**************************************************************************\n * First-Word Fall-Through module (preload 0)\n **************************************************************************/\nmodule fifo_generator_v13_2_5_bhv_ver_preload0\n  #(\n    parameter  C_DOUT_RST_VAL            = \"\",\n    parameter  C_DOUT_WIDTH              = 8,\n    parameter  C_HAS_RST                 = 0,\n    parameter  C_ENABLE_RST_SYNC         = 0,\n    parameter  C_HAS_SRST                = 0,\n    parameter  C_USE_EMBEDDED_REG        = 0,\n    parameter  C_EN_SAFETY_CKT           = 0, \n    parameter  C_USE_DOUT_RST            = 0,\n    parameter  C_USE_ECC                 = 0,\n    parameter  C_USERVALID_LOW           = 0,\n    parameter  C_USERUNDERFLOW_LOW       = 0,\n    parameter  C_MEMORY_TYPE             = 0,\n    parameter  C_FIFO_TYPE               = 0\n  )\n  (\n    //Inputs\n    input                          SAFETY_CKT_RD_RST,\n    input                          RD_CLK,\n    input                          RD_RST,\n    input                          SRST,\n    input                          WR_RST_BUSY,\n    input                          RD_RST_BUSY,\n    input                          RD_EN,\n    input                          FIFOEMPTY,\n    input       [C_DOUT_WIDTH-1:0] FIFODATA,\n    input                          FIFOSBITERR,\n    input                          FIFODBITERR,\n   \n    //Outputs\n    output reg  [C_DOUT_WIDTH-1:0] USERDATA,\n    output                         USERVALID,\n    output                         USERUNDERFLOW,\n    output                         USEREMPTY,\n    output                         USERALMOSTEMPTY,\n    output                         RAMVALID,\n    output                         FIFORDEN,\n    output reg                     USERSBITERR,\n    output reg                     USERDBITERR,\n    output reg                     STAGE2_REG_EN,\n    output                         fab_read_data_valid_i_o,\n    output                         read_data_valid_i_o,\n    output                         ram_valid_i_o,\n    output      [1:0]              VALID_STAGES \n  );\n //Internal signals\n wire                      preloadstage1;\n wire                      preloadstage2;\n reg                       ram_valid_i;\n reg                       fab_valid;\n reg                       read_data_valid_i;\n reg                       fab_read_data_valid_i;\n reg                       fab_read_data_valid_i_1;\n reg                       ram_valid_i_d;\n reg                       read_data_valid_i_d;\n reg                       fab_read_data_valid_i_d;\n wire                      ram_regout_en;\n reg                       ram_regout_en_d1;\n reg                       ram_regout_en_d2;\n wire                      fab_regout_en;\n wire                      ram_rd_en;\n reg                       empty_i        = 1'b1;\n reg                       empty_sckt     = 1'b1;\n reg                       sckt_rrst_q    = 1'b0;\n reg                       sckt_rrst_done = 1'b0;\n reg                       empty_q        = 1'b1;\n reg                       rd_en_q        = 1'b0;\n reg                       almost_empty_i = 1'b1;\n reg                       almost_empty_q = 1'b1;\n wire                      rd_rst_i;\n wire                      srst_i;\n reg  [C_DOUT_WIDTH-1:0]   userdata_both;\n wire                      uservalid_both;\n wire                      uservalid_one;\n reg                       user_sbiterr_both = 1'b0;\n reg                       user_dbiterr_both = 1'b0;\n  \nassign ram_valid_i_o = ram_valid_i;\nassign read_data_valid_i_o = read_data_valid_i;\nassign fab_read_data_valid_i_o = fab_read_data_valid_i; \n\n\n\n/*************************************************************************\n* FUNCTIONS\n*************************************************************************/\n\n   /*************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***********************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n   \n   //*************************************************************************\n   //  Set power-on states for regs\n   //*************************************************************************\n   initial begin\n      ram_valid_i       = 1'b0;\n      fab_valid         = 1'b0;\n      read_data_valid_i = 1'b0;\n      fab_read_data_valid_i = 1'b0;\n      fab_read_data_valid_i_1 = 1'b0;\n      USERDATA          = hexstr_conv(C_DOUT_RST_VAL);\n      userdata_both          = hexstr_conv(C_DOUT_RST_VAL);\n      USERSBITERR       = 1'b0;\n      USERDBITERR       = 1'b0;\n      user_sbiterr_both = 1'b0;\n      user_dbiterr_both = 1'b0;\n   end //initial\n\n   //***************************************************************************\n   //  connect up optional reset\n   //***************************************************************************\n   assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;\n   assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;\n\n   reg  sckt_rd_rst_fwft = 1'b0;\n   reg  fwft_rst_done_i  = 1'b0;\n   wire fwft_rst_done;\n   assign fwft_rst_done = 1'b1;//C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;\n   always @ (posedge RD_CLK) begin\n     sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;\n   end\n\n   always @ (posedge rd_rst_i or posedge RD_CLK) begin\n     if (rd_rst_i)\n       fwft_rst_done_i  <= 1'b0;\n     else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)\n       fwft_rst_done_i  <= #`TCQ 1'b1;\n   end\n\n   localparam INVALID             = 0;\n   localparam STAGE1_VALID        = 2;\n   localparam STAGE2_VALID        = 1;\n   localparam BOTH_STAGES_VALID   = 3;\n\n   reg  [1:0] curr_fwft_state = INVALID;\n   reg  [1:0] next_fwft_state = INVALID;\n\n\ngenerate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin\n         always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n \n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n     \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n    \n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = preloadstage2;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;\n   end\nendgenerate // gnll_fifo\n\n   reg curr_state         = 0;\n   reg next_state         = 0;\n   reg leaving_empty_fwft = 0;\n   reg going_empty_fwft   = 0;\n   reg empty_i_q          = 0;\n   reg ram_rd_en_fwft     = 0;\n   generate if (C_FIFO_TYPE == 2) begin : gll_fifo\n     always @* begin // FSM fo FWFT\n       case (curr_state)\n         1'b0: begin\n           if (~FIFOEMPTY)\n             next_state <= 1'b1;\n           else\n             next_state <= 1'b0;\n           end\n         1'b1: begin\n           if (FIFOEMPTY && RD_EN)\n             next_state <= 1'b0;\n           else\n             next_state <= 1'b1;\n           end\n         default: next_state <= 1'b0;\n       endcase\n     end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_i       <= 1'b1;\n           empty_i_q     <= 1'b1;\n           ram_valid_i   <= 1'b0;\n        end else if (srst_i) begin\n           empty_i       <= #`TCQ 1'b1;\n           empty_i_q     <= #`TCQ 1'b1;\n           ram_valid_i   <= #`TCQ 1'b0;\n        end else begin\n           empty_i       <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);\n           empty_i_q     <= #`TCQ FIFOEMPTY;\n           ram_valid_i   <= #`TCQ next_state;\n        end\n     end //always\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n           curr_state    <= 1'b0;\n        end else if (srst_i) begin\n           curr_state    <= #`TCQ 1'b0;\n        end else begin\n           curr_state    <= #`TCQ next_state;\n        end\n     end //always\n\n     wire                  fe_of_empty; \n     assign fe_of_empty   = empty_i_q & ~FIFOEMPTY;\n\n     always @* begin // Finding leaving empty\n       case (curr_state)\n         1'b0:    leaving_empty_fwft <= fe_of_empty;\n         1'b1:    leaving_empty_fwft <= 1'b1;\n         default: leaving_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Finding going empty\n       case (curr_state)\n         1'b1:    going_empty_fwft <= FIFOEMPTY & RD_EN;\n         default: going_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Generating FWFT rd_en\n       case (curr_state)\n         1'b0:    ram_rd_en_fwft <= ~FIFOEMPTY;\n         1'b1:    ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;\n         default: ram_rd_en_fwft <= 1'b0;\n       endcase\n     end\n\n     assign ram_regout_en = ram_rd_en_fwft;\n     //assign ram_regout_en_d1 = ram_rd_en_fwft;\n     //assign ram_regout_en_d2 = ram_rd_en_fwft;\n     assign ram_rd_en     = ram_rd_en_fwft;\n   end endgenerate // gll_fifo\n\n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false.\n   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n   generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           ram_valid_i     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              ram_valid_i     <= #`TCQ 1'b0;\n           end else begin\n              if (ram_rd_en == 1'b1) begin\n                 ram_valid_i   <= #`TCQ 1'b1;\n              end else begin\n                 if (ram_regout_en == 1'b1)\n                   ram_valid_i <= #`TCQ 1'b0;\n                 else\n                   ram_valid_i <= #`TCQ ram_valid_i;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_ram_valid\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n  \n generate if(C_USE_EMBEDDED_REG < 3) begin\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else\n        read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);\n   end //always\nend \nendgenerate\n\n   \n   \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n generate if ( C_USE_EMBEDDED_REG < 3) begin\n  always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin         // asynchronous reset (active high)\n             almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ FIFOEMPTY;\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n   \n   \n     \n  // BRAM resets synchronously\n generate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin\n   always @ ( posedge rd_rst_i)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n           @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n             USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end  else if (fwft_rst_done) begin\n            if (ram_regout_en) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end\n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n//safety ckt with one register\ngenerate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n            @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n        end\n     end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n          //@(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end \n       end\n        else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n            //  @(posedge RD_CLK)\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end else if (fwft_rst_done) begin\n            if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end          \n          end\n        end\n       end //always\n  end //if\nendgenerate\n\n\ngenerate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin\n         \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d1 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d1 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d1 <= #`TCQ ram_regout_en;\n                 end\n            end //always\n   //  assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));\n       assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d2 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d2 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;\n                 end\n            end //always\n\n    \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n     always @ (posedge RD_CLK) begin\n        ram_valid_i_d <= #`TCQ ram_valid_i;\n        read_data_valid_i_d <= #`TCQ read_data_valid_i;\n        fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;\n\n     end\n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n    \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;\n   end\n   endgenerate // gnll_fifo\n\n   \n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n     generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid\n\n     \n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           fab_valid     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              fab_valid    <= #`TCQ 1'b0;\n           end else begin\n              if (ram_regout_en == 1'b1) begin\n                 fab_valid  <= #`TCQ 1'b1;\n              end else begin\n                 if (fab_regout_en == 1'b1)\n                   fab_valid <= #`TCQ 1'b0;\n                 else\n                   fab_valid <= #`TCQ fab_valid;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_fab_valid\n\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n    generate if(C_USE_EMBEDDED_REG == 3) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else begin\n        if (ram_regout_en == 1'b1) begin\n          read_data_valid_i <= #`TCQ 1'b1;\n        end else begin\n         if (fab_regout_en == 1'b1)\n          read_data_valid_i <= #`TCQ 1'b0;\n        else\n          read_data_valid_i <= #`TCQ read_data_valid_i;\n        end \n      end \n   end //always\nend\nendgenerate\n\n//generate if(C_USE_EMBEDDED_REG == 3) begin\n//   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n//      if (rd_rst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//      else if (srst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//\n//      if (ram_regout_en == 1'b1) begin\n//        fab_read_data_valid_i <= #`TCQ 1'b0;\n//      end else begin\n//       if (fab_regout_en == 1'b1)\n//        fab_read_data_valid_i <= #`TCQ 1'b1;\n//      else\n//        fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;\n//      end \n//   end //always\n//end\n//endgenerate\n\n     generate if(C_USE_EMBEDDED_REG == 3 ) begin \n    always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid\n      if (rd_rst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else \n        fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);\n   end //always\nend\nendgenerate\n \nalways @ (posedge RD_CLK ) begin : proc_del1\n             begin\n                 fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;\n              end\n            end //always\n \n \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty_both\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n   reg FIFOEMPTY_1;\n   generate if (C_USE_EMBEDDED_REG == 3 ) begin\n    always @(posedge RD_CLK) begin\n            FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;\n           end\n    end\nendgenerate\n    generate if (C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n   begin\n      if (rd_rst_i) begin         // asynchronous reset (active high)\n           almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ (~ram_valid_i);\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_sckt <= #`TCQ 1'b1;\n           sckt_rrst_q <= #`TCQ 1'b0;\n           sckt_rrst_done <= #`TCQ 1'b0;\n        end else begin\n           sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;\n           if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin\n              sckt_rrst_done <= #`TCQ 1'b1;\n           end else if (sckt_rrst_done) begin\n              // rising clock edge\n              empty_sckt <= #`TCQ 1'b0;\n           end\n        end\n     end //always\n   \n   \n//   assign USEREMPTY       = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;\n   assign USEREMPTY       = empty_i;\n   assign USERALMOSTEMPTY = almost_empty_i;\n   assign FIFORDEN        = ram_rd_en;\n   assign RAMVALID        = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;\n   assign uservalid_both       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3)  ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);\n   assign uservalid_one       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3)  ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);\n   assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;\n   assign USERUNDERFLOW   = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;\n//no safety ckt with both reg\ngenerate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n            USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              userdata_both   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end else begin\n            if (fwft_rst_done) begin\n              if (ram_regout_en) begin\n                 userdata_both     <= #`TCQ FIFODATA; \n                 user_dbiterr_both <= #`TCQ FIFODBITERR;\n                 user_sbiterr_both <= #`TCQ FIFOSBITERR; \n              end\n              if (fab_regout_en) begin\n                 USERDATA     <= #`TCQ userdata_both;\n                 USERDBITERR  <= #`TCQ user_dbiterr_both;\n                 USERSBITERR  <= #`TCQ user_sbiterr_both; \n              end             \n            end             \n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n\n//safety_ckt with both registers\n generate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always @ (posedge RD_CLK) begin\n          if (rd_rst_i || srst_i) begin\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n              @(posedge RD_CLK)\n              USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n               userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end\n        end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n     if (rd_rst_i) begin //asynchronous reset (active high)\n       if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n         USERSBITERR       <= #`TCQ 0;\n         USERDBITERR       <= #`TCQ 0;\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end\n       // DRAM resets asynchronously\n       if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n         USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end \n     end else begin // rising clock edge\n       if (srst_i) begin\n         if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n           USERSBITERR       <= #`TCQ 0;\n           USERDBITERR       <= #`TCQ 0;\n           user_sbiterr_both <= #`TCQ 0;\n           user_dbiterr_both <= #`TCQ 0;\n         end\n         if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n           USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end\n       end else if (fwft_rst_done) begin\n         if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            userdata_both     <= #`TCQ FIFODATA;\n            user_dbiterr_both <= #`TCQ FIFODBITERR;\n            user_sbiterr_both <= #`TCQ FIFOSBITERR; \n         end\n         if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            USERDATA          <= #`TCQ userdata_both;\n            USERDBITERR       <= #`TCQ user_dbiterr_both;\n            USERSBITERR       <= #`TCQ user_sbiterr_both;\n         end\n       end\n     end\n   end //always\n  end //if\nendgenerate\n\nendmodule //fifo_generator_v13_2_5_bhv_ver_preload0\n\n\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Register one AXI channel on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   reg_slice\n//\n//--------------------------------------------------------------------------\n\nmodule fifo_generator_v13_2_5_axic_reg_slice #\n  (\n   parameter C_FAMILY     = \"virtex7\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   )\n  (\n   // System Signals\n   input  wire                      ACLK,\n   input  wire                      ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0]   S_PAYLOAD_DATA,\n   input  wire                      S_VALID,\n   output wire                      S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0]   M_PAYLOAD_DATA,\n   output wire                      M_VALID,\n   input  wire                      M_READY\n   );\n\n  localparam RST_SYNC_STAGES = 5;\n  localparam RST_BUSY_LEN    = 6;\n  reg [1:0] arst_sync_wr  = 2'b11;\n  reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n  wire sync_reset;\n  wire extnd_reset;\n\n\n  always @(posedge ARESET or posedge ACLK) begin\n    if (ARESET)\n      arst_sync_wr <= 2'b11;\n    else\n      arst_sync_wr <= #`TCQ {arst_sync_wr[0], 1'b0};\n  end\n\n  always @(posedge ACLK) begin\n    sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[1]};\n  end\n\n  assign sync_reset     = |sckt_wr_rst_cc[RST_BUSY_LEN-5:0] | arst_sync_wr[1]; \n  assign extnd_reset    = |sckt_wr_rst_cc | arst_sync_wr[1];\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000)\n    begin\n      reg [1:0] state;\n      localparam [1:0] \n        ZERO = 2'b10,\n        ONE  = 2'b11,\n        TWO  = 2'b01;\n      \n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg [C_DATA_WIDTH-1:0] storage_data2 = 0;\n      reg                    load_s1;\n      wire                   load_s2;\n      wire                   load_s1_from_s2;\n      reg                    s_ready_i; //local signal of output\n      wire                   m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with either slave side data or from storage2\n      always @(posedge ACLK) \n      begin\n        if (load_s1)\n          if (load_s1_from_s2)\n            storage_data1 <= storage_data2;\n          else\n            storage_data1 <= S_PAYLOAD_DATA;        \n      end\n\n      // Load storage2 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data1;\n\n      // Always load s2 on a valid transaction even if it's unnecessary\n      assign load_s2 = S_VALID & s_ready_i;\n\n      // Loading s1\n      always @ *\n      begin\n        if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction\n             // Load when ONE if we both have read and write at the same time\n             ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||\n             // Load when TWO and we have a transaction on Master side\n             ((state == TWO) && (M_READY == 1)))\n          load_s1 = 1'b1;\n        else\n          load_s1 = 1'b0;\n      end // always @ *\n\n      assign load_s1_from_s2 = (state == TWO);\n                       \n      // State Machine for handling output signals\n      always @(posedge ACLK) begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          state <= ZERO;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          case (state)\n            // No transaction stored locally\n            ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE\n\n            // One transaction stored locally\n            ONE: begin\n              if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO\n              if (~M_READY & S_VALID) begin\n                state <= TWO;  // Got another one so move to TWO\n                s_ready_i <= 1'b0;\n              end\n            end\n\n            // TWO transaction stored locally\n            TWO: if (M_READY) begin\n              state <= ONE; // Read out one so move to ONE\n              s_ready_i <= 1'b1;\n            end\n          endcase // case (state)\n        end\n      end // always @ (posedge ACLK)\n      \n      assign m_valid_i = state[0];\n\n    end // if (C_REG_CONFIG == 1)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000001)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg                    s_ready_i; //local signal of output\n      reg                    m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b0;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else if (m_valid_i & M_READY) begin\n          s_ready_i <= 1'b1;\n          m_valid_i <= 1'b0;\n        end else if (S_VALID & s_ready_i) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b1;\n        end\n        if (~m_valid_i) begin\n          storage_data1 <= S_PAYLOAD_DATA;        \n        end\n      end\n      assign M_PAYLOAD_DATA = storage_data1;\n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // reg_slice\n", "num_lines": 10520}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sync_clock_converter\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_14_axic_sync_clock_converter # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_FAMILY     = \"virtex6\",\n  parameter integer C_PAYLOAD_WIDTH = 32,\n  parameter integer C_S_ACLK_RATIO = 1,\n  parameter integer C_M_ACLK_RATIO = 1 ,\n  parameter integer C_MODE = 0  // 0 = light-weight (1-deep); 1 = fully-pipelined (2-deep)\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input wire                    SAMPLE_CYCLE_EARLY,\n  input wire                    SAMPLE_CYCLE,\n  // Slave side\n  input  wire                        S_ACLK,\n  input  wire                        S_ARESETN,\n  input  wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD,\n  input  wire                        S_VALID,\n  output wire                        S_READY,\n\n  // Master side\n  input  wire                        M_ACLK,\n  input  wire                        M_ARESETN,\n  output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD,\n  output wire                        M_VALID,\n  input  wire                        M_READY\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam [1:0] ZERO = 2'b10;\nlocalparam [1:0] ONE  = 2'b11;\nlocalparam [1:0] TWO  = 2'b01;\nlocalparam [1:0] INIT = 2'b00;\nlocalparam integer P_LIGHT_WT = 0;\nlocalparam integer P_FULLY_REG = 1;\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\ngenerate\n  if (C_S_ACLK_RATIO == C_M_ACLK_RATIO) begin : gen_passthru\n    assign M_PAYLOAD = S_PAYLOAD;\n    assign M_VALID   = S_VALID;\n    assign S_READY   = M_READY;      \n  end else begin : gen_sync_clock_converter\n    wire s_sample_cycle;\n    wire s_sample_cycle_early;\n    wire m_sample_cycle;\n    wire m_sample_cycle_early;\n\n    wire slow_aclk;\n    wire slow_areset;\n    wire s_areset_r;\n    wire m_areset_r;\n   \n    reg  s_tready_r = 1'b0; \n    wire s_tready_ns; \n    reg  m_tvalid_r = 1'b0; \n    wire m_tvalid_ns; \n    reg  [C_PAYLOAD_WIDTH-1:0] m_tpayload_r;\n    reg  [C_PAYLOAD_WIDTH-1:0] m_tstorage_r;\n    wire [C_PAYLOAD_WIDTH-1:0] m_tpayload_ns; \n    wire [C_PAYLOAD_WIDTH-1:0] m_tstorage_ns; \n    reg  m_tready_hold = 1'b0;\n    wire m_tready_sample;\n    wire load_tpayload;\n    wire load_tstorage;\n    wire load_tpayload_from_tstorage;\n    reg [1:0] state = INIT;\n    reg [1:0] next_state;\n    \n    reg s_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge S_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        s_aresetn_r <= 1'b0;\n      end else begin\n        s_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign s_areset_r = ~s_aresetn_r;\n\n    reg m_aresetn_r = 1'b0; // Reset delay register\n    always @(posedge M_ACLK) begin\n      if (~S_ARESETN | ~M_ARESETN) begin\n        m_aresetn_r <= 1'b0;\n      end else begin\n        m_aresetn_r <= S_ARESETN & M_ARESETN;\n      end\n    end\n    assign m_areset_r = ~m_aresetn_r;\n\n    if (C_S_ACLK_RATIO > C_M_ACLK_RATIO) begin : gen_slowclk_mi\n      assign slow_aclk = M_ACLK;\n    end else begin : gen_slowclk_si\n      assign slow_aclk = S_ACLK;\n    end\n  \n    assign slow_areset = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? m_areset_r : s_areset_r;\n    assign s_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE_EARLY : 1'b1;\n    assign s_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE : 1'b1;\n    assign m_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE_EARLY;\n    assign m_sample_cycle       = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE;\n\n    // Output flop for S_READY, value is encoded into state machine.\n    assign s_tready_ns = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? state[1] & (state != INIT) : next_state[1];\n\n    always @(posedge S_ACLK) begin \n      if (s_areset_r) begin\n        s_tready_r <= 1'b0;\n      end\n      else begin\n        s_tready_r <= s_sample_cycle_early ? s_tready_ns : 1'b0;\n      end\n    end\n\n    assign S_READY = s_tready_r;\n\n    // Output flop for M_VALID\n    assign m_tvalid_ns = next_state[0];\n\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tvalid_r <= 1'b0;\n      end\n      else begin\n        m_tvalid_r <= m_sample_cycle ? m_tvalid_ns : m_tvalid_r & ~M_READY;\n      end\n    end\n\n    assign M_VALID = m_tvalid_r;\n\n    // Hold register for M_READY when M_ACLK is fast.\n    always @(posedge M_ACLK) begin \n      if (m_areset_r) begin\n        m_tready_hold <= 1'b0;\n      end\n      else begin\n        m_tready_hold <= m_sample_cycle ? 1'b0 : m_tready_sample;\n      end\n    end\n\n    assign m_tready_sample = (M_READY ) | m_tready_hold;\n    // Output/storage flops for PAYLOAD\n    assign m_tpayload_ns = ~load_tpayload ? m_tpayload_r :\n                           load_tpayload_from_tstorage ? m_tstorage_r : \n                           S_PAYLOAD;\n\n    assign m_tstorage_ns = C_MODE ? (load_tstorage ? S_PAYLOAD : m_tstorage_r) : 0;\n\n    always @(posedge slow_aclk) begin \n      m_tpayload_r <= m_tpayload_ns;\n      m_tstorage_r <= C_MODE ? m_tstorage_ns : 0;\n    end\n\n    assign M_PAYLOAD = m_tpayload_r;\n\n    // load logic\n    assign load_tstorage = C_MODE && (state != TWO);\n    assign load_tpayload = m_tready_sample || (state == ZERO);\n    assign load_tpayload_from_tstorage = C_MODE && (state == TWO) && m_tready_sample;\n    \n    // State machine\n    always @(posedge slow_aclk) begin \n      state <= next_state;\n    end\n\n    always @* begin \n      if (slow_areset) begin \n        next_state = INIT;\n      end else begin\n        case (state)\n          INIT: begin\n            next_state = ZERO;\n          end\n          // No transaction stored locally\n          ZERO: begin\n            if (S_VALID) begin\n              next_state = C_MODE ? ONE : TWO; // Push from empty\n            end\n            else begin\n              next_state = ZERO;\n            end\n          end\n\n          // One transaction stored locally\n          ONE: begin\n            if (C_MODE == 0) begin\n              next_state = TWO;  // State ONE is inaccessible when C_MODE=0\n            end \n            else if (m_tready_sample & ~S_VALID) begin \n              next_state = ZERO; // Read out one so move to ZERO\n            end\n            else if (~m_tready_sample & S_VALID) begin\n              next_state = TWO;  // Got another one so move to TWO\n            end\n            else begin\n              next_state = ONE;\n            end\n          end\n\n          // Storage registers full\n          TWO: begin \n            if (m_tready_sample) begin\n              next_state = C_MODE ? ONE : ZERO; // Pop from full\n            end\n            else begin\n              next_state = TWO;\n            end\n          end\n        endcase // case (state)\n      end\n    end\n  end // gen_sync_clock_converter\n  endgenerate\nendmodule\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_sample_cycle_ratio\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_14_axic_sample_cycle_ratio # (\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter C_RATIO = 2 // Must be > 0\n  )\n (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    SLOW_ACLK,\n  input  wire                    FAST_ACLK,\n\n  output wire                    SAMPLE_CYCLE_EARLY,\n  output wire                    SAMPLE_CYCLE\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam P_DELAY = C_RATIO > 2 ? C_RATIO-1 : C_RATIO-1; \n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_aclk_div2 = 1'b0;\nreg                posedge_finder_first = 1'b0;\nreg                posedge_finder_second = 1'b0;\nwire               first_edge;\nwire               second_edge;\nwire               any_edge;\nreg  [P_DELAY-1:0] sample_cycle_d = {P_DELAY{1'b0}};\n(* shreg_extract = \"no\" *) reg                sample_cycle_r = 1'b0;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\ngenerate\n  if (C_RATIO == 1) begin : gen_always_sample\n    assign SAMPLE_CYCLE_EARLY = 1'b1;\n    assign SAMPLE_CYCLE = 1'b1;\n  end\n  else begin : gen_sample_cycle\n    genvar i;\n    always @(posedge SLOW_ACLK) begin \n      slow_aclk_div2 <= ~slow_aclk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_aclk_div2 onto faster clock\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_first <= slow_aclk_div2;\n    end\n    always @(posedge FAST_ACLK) begin \n      posedge_finder_second <= ~slow_aclk_div2;\n    end\n\n    assign first_edge = slow_aclk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;\n    assign any_edge = first_edge | second_edge;\n   \n    // delay the posedge alignment by C_RATIO - 1 to set the sample cycle as\n    // the clock one cycle before the posedge.\n    for (i = P_DELAY-1; i > 0; i = i - 1) begin : gen_delay\n      always @(posedge FAST_ACLK) begin\n        if (i == P_DELAY-1) begin\n          sample_cycle_d[i-1] <= any_edge;\n        end else begin\n          sample_cycle_d[i-1] <= sample_cycle_d[i];\n        end\n      end\n    end\n\n    always @(posedge FAST_ACLK) begin \n      sample_cycle_r <= (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    end\n    assign SAMPLE_CYCLE_EARLY = (P_DELAY>1) ? sample_cycle_d[0] : any_edge;\n    assign SAMPLE_CYCLE = sample_cycle_r;\n  end\nendgenerate\n\nendmodule // axisc_sample_cycle_ratio\n\n`default_nettype wire\n\n\n\n// -- (c) Copyright 2010 - 2016 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and\n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Clock converter module\n//   Asynchronous clock converter when asynchronous M:N conversion\n//   Bypass when synchronous and ratio between S and M clock is 1:1\n//   Synchronous clock converter (S:M or M:S must be integer ratio)\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_clock_conv\n//     fifo_generator\n//     axic_sync_clock_converter\n//       axic_sample_cycle_ratio\n//\n// PROTECTED NAMES:\n//   Instance names \"asyncfifo_*\" are pattern-matched in core-level UCF.\n//   Signal names \"*_resync\" are pattern-matched in core-level UCF.\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_14_lite_async #(\n  parameter integer C_DEST_SYNC_FF = 2,\n  parameter integer C_SRC_SYNC_FF  = 2,\n  parameter integer C_WIDTH        = 1\n) (\n  input wire                s_aclk,\n  input wire                m_aclk,\n  input wire                s_aresetn,\n  input wire                m_aresetn,\n  input wire                s_valid,\n  output wire                s_ready,\n  input wire [C_WIDTH-1:0]  s_payld,\n  output wire                m_valid,\n  input wire                m_ready,\n  output wire [C_WIDTH-1:0] m_payld\n);\n\nreg                s_ready_i = 1'b0;\nreg                m_valid_i = 1'b0;\nreg   src_send = 1'b0;\nreg   dest_ack = 1'b0;\nwire  src_rcv;\nwire  dest_req;\n\nassign s_ready = s_ready_i;\nassign m_valid = m_valid_i;\n\nlocalparam SRC_IDLE           = 2'b00;\nlocalparam SRC_DRV_SEND       = 2'b01;\nlocalparam SRC_WAIT_RCV_DONE  = 2'b10;\nreg [1:0] src_state = SRC_IDLE;\n\nalways @(posedge s_aclk) begin\n  if (s_aresetn == 1'b0) begin\n    s_ready_i <= 1'b0;\n    src_send <= 1'b0;\n    src_state <= SRC_IDLE;\n  end else begin\n    case (src_state)\n      SRC_IDLE: begin\n        if (s_valid) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end\n      end\n      SRC_DRV_SEND: begin\n        if (src_rcv) begin\n          s_ready_i <= 1'b1;\n          src_send <= 1'b0;\n          src_state <= SRC_WAIT_RCV_DONE;\n        end\n      end\n      SRC_WAIT_RCV_DONE: begin\n        s_ready_i <= 1'b0;\n        if (s_valid & !src_rcv) begin\n          src_state <= SRC_DRV_SEND;\n          src_send <= 1'b1;\n        end else if (!src_rcv) begin\n          src_state <= SRC_IDLE;\n        end\n      end\n      default: begin\n        s_ready_i <= 1'b0;\n        src_send <= 1'b0;\n        src_state <= SRC_IDLE;\n      end\n    endcase\n  end\nend\n\nlocalparam DEST_IDLE           = 2'b00;\nlocalparam DEST_DRV_VALID      = 2'b01;\nlocalparam DEST_DRV_ACK        = 2'b10;\nreg [1:0] dest_state = DEST_IDLE;\n\nalways @(posedge m_aclk) begin\n  if (m_aresetn == 1'b0) begin\n    m_valid_i <= 1'b0;\n    dest_ack <= 1'b0;\n    dest_state <= DEST_IDLE;\n  end else begin\n    case (dest_state)\n      DEST_IDLE: begin\n        if (dest_req) begin\n          dest_state <= DEST_DRV_VALID;\n          m_valid_i <= 1'b1;\n        end else begin\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b0;\n        end\n      end\n      DEST_DRV_VALID: begin\n        if (m_ready & m_valid_i) begin\n          dest_state <= DEST_DRV_ACK;\n          m_valid_i <= 1'b0;\n          dest_ack <= 1'b1;\n        end\n      end\n      DEST_DRV_ACK: begin\n        if (!dest_req) begin\n          dest_state <= DEST_IDLE;\n          dest_ack <= 1'b0;\n        end\n      end\n      default: begin\n        m_valid_i <= 1'b0;\n        dest_ack <= 1'b0;\n        dest_state <= DEST_IDLE;\n      end\n    endcase\n  end\nend\n\nxpm_cdc_handshake #(\n  .DEST_SYNC_FF   (C_DEST_SYNC_FF),\n  .SRC_SYNC_FF    (C_SRC_SYNC_FF),\n  .WIDTH          (C_WIDTH)\n) handshake (\n  .src_clk  (s_aclk),\n  .src_in   (s_payld),\n  .src_send (src_send),\n  .src_rcv  (src_rcv),\n  .dest_clk (m_aclk),\n  .dest_out (m_payld),\n  .dest_req (dest_req),\n  .dest_ack (dest_ack)\n);\n\nendmodule\n\n\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_clock_converter_v2_1_14_axi_clock_converter #\n  (parameter         C_FAMILY = \"virtex7\",\n   parameter integer C_AXI_ID_WIDTH = 5,                    // Width of all ID signals on SI and MI side.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ADDR_WIDTH = 32,                 // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and\n                                                            // m_axi_araddr.\n                                                            // Range: 32.\n   parameter integer C_AXI_DATA_WIDTH = 32,       // Width of WDATA and RDATA (either side).\n                                                            // Format: Bit32;\n                                                            // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.\n   parameter integer C_S_AXI_ACLK_RATIO = 1,     // Clock frequency ratio of SI w.r.t. MI.\n   parameter integer C_M_AXI_ACLK_RATIO = 1,     // (Slowest of all clock inputs should have ratio=1.)\n                                                            // S:M or M:S must be integer ratio.\n                                                            // Format: Bit32; Range: >='h00000001.\n   parameter integer C_AXI_IS_ACLK_ASYNC = 1,            // Indicates whether S and M clocks are asynchronous.\n                                                            // FUTURE FEATURE\n                                                            // Format: Bit1. Range = 1'b0.\n   parameter integer C_AXI_PROTOCOL = 0,         // Protocol of this SI/MI slot.\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS  = 1,      // 1 = Propagate all USER signals, 0 = Do not propagate.\n   parameter integer C_AXI_AWUSER_WIDTH = 1,                // Width of AWUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_ARUSER_WIDTH = 1,                // Width of ARUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_WUSER_WIDTH = 1,                 // Width of WUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_RUSER_WIDTH = 1,                 // Width of RUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_BUSER_WIDTH = 1,                 // Width of BUSER signals.\n                                                            // Range: >= 1.\n   parameter integer C_AXI_SUPPORTS_WRITE = 1,              // Implement AXI write channels\n   parameter integer C_AXI_SUPPORTS_READ = 1,               // Implement AXI read channels\n   parameter integer C_SYNCHRONIZER_STAGE = 3\n  )\n\n  (\n   // Slave Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        s_axi_aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n   input  wire [4-1:0]                    s_axi_awcache,\n   input  wire [3-1:0]                    s_axi_awprot,\n   input  wire [4-1:0]                    s_axi_awregion,\n   input  wire [4-1:0]                    s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0]   s_axi_awuser,\n   input  wire                            s_axi_awvalid,\n   output wire                            s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0]   s_axi_wstrb,\n   input  wire                            s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]    s_axi_wuser,\n   input  wire                            s_axi_wvalid,\n   output wire                            s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_bid,\n   output wire [2-1:0]                    s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0]    s_axi_buser,\n   output wire                            s_axi_bvalid,\n   input  wire                            s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]     s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n   input  wire [3-1:0]                    s_axi_arsize,\n   input  wire [2-1:0]                    s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n   input  wire [4-1:0]                    s_axi_arcache,\n   input  wire [3-1:0]                    s_axi_arprot,\n   input  wire [4-1:0]                    s_axi_arregion,\n   input  wire [4-1:0]                    s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0]   s_axi_aruser,\n   input  wire                            s_axi_arvalid,\n   output wire                            s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     s_axi_rdata,\n   output wire [2-1:0]                    s_axi_rresp,\n   output wire                            s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0]    s_axi_ruser,\n   output wire                            s_axi_rvalid,\n   input  wire                            s_axi_rready,\n\n   // Master Interface System Signals\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aclk,\n   (* KEEP = \"TRUE\" *) input  wire        m_axi_aresetn,\n\n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n   output wire [3-1:0]                    m_axi_awsize,\n   output wire [2-1:0]                    m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n   output wire [4-1:0]                    m_axi_awcache,\n   output wire [3-1:0]                    m_axi_awprot,\n   output wire [4-1:0]                    m_axi_awregion,\n   output wire [4-1:0]                    m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0]   m_axi_awuser,\n   output wire                            m_axi_awvalid,\n   input  wire                            m_axi_awready,\n\n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]     m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0]   m_axi_wstrb,\n   output wire                            m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]    m_axi_wuser,\n   output wire                            m_axi_wvalid,\n   input  wire                            m_axi_wready,\n\n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_bid,\n   input  wire [2-1:0]                    m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0]    m_axi_buser,\n   input  wire                            m_axi_bvalid,\n   output wire                            m_axi_bready,\n\n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]       m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]     m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n   output wire [3-1:0]                    m_axi_arsize,\n   output wire [2-1:0]                    m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n   output wire [4-1:0]                    m_axi_arcache,\n   output wire [3-1:0]                    m_axi_arprot,\n   output wire [4-1:0]                    m_axi_arregion,\n   output wire [4-1:0]                    m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0]   m_axi_aruser,\n   output wire                            m_axi_arvalid,\n   input  wire                            m_axi_arready,\n\n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]       m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]     m_axi_rdata,\n   input  wire [2-1:0]                    m_axi_rresp,\n   input  wire                            m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0]    m_axi_ruser,\n   input  wire                            m_axi_rvalid,\n   output wire                            m_axi_rready);\n\n  localparam integer P_AXI4 = 0;\n  localparam integer P_AXI3 = 1;\n  localparam integer P_AXILITE = 2;\n  localparam integer P_LIGHT_WT = 0;\n  localparam integer P_FULLY_REG = 1;\n  localparam integer P_LUTRAM_ASYNC = 12;\n\n  // Sample cycle ratio\n  localparam  P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);\n  localparam integer P_ROUNDING_OFFSET = P_SI_LT_MI ? (C_S_AXI_ACLK_RATIO/2) : (C_M_AXI_ACLK_RATIO/2);\n  localparam integer P_ACLK_RATIO = P_SI_LT_MI ?\n    ((C_M_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_S_AXI_ACLK_RATIO) :\n    ((C_S_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_M_AXI_ACLK_RATIO);\n\n  // Write Address Port bit positions\n  localparam integer C_AWUSER_RIGHT   = 0;\n  localparam integer C_AWUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_AWUSER_WIDTH : 0;\n  localparam integer C_AWQOS_RIGHT    = C_AWUSER_RIGHT + C_AWUSER_WIDTH;\n  localparam integer C_AWQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWREGION_RIGHT = C_AWQOS_RIGHT + C_AWQOS_WIDTH;\n  localparam integer C_AWREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_AWPROT_RIGHT   = C_AWREGION_RIGHT + C_AWREGION_WIDTH;\n  localparam integer C_AWPROT_WIDTH     = 3;\n  localparam integer C_AWCACHE_RIGHT  = C_AWPROT_RIGHT + C_AWPROT_WIDTH;\n  localparam integer C_AWCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_AWLOCK_RIGHT   = C_AWCACHE_RIGHT + C_AWCACHE_WIDTH;\n  localparam integer C_AWLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_AWBURST_RIGHT  = C_AWLOCK_RIGHT + C_AWLOCK_WIDTH;\n  localparam integer C_AWBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_AWSIZE_RIGHT   = C_AWBURST_RIGHT + C_AWBURST_WIDTH;\n  localparam integer C_AWSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_AWLEN_RIGHT    = C_AWSIZE_RIGHT + C_AWSIZE_WIDTH;\n  localparam integer C_AWLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_AWADDR_RIGHT   = C_AWLEN_RIGHT + C_AWLEN_WIDTH;\n  localparam integer C_AWADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_AWID_RIGHT     = C_AWADDR_RIGHT + C_AWADDR_WIDTH;\n  localparam integer C_AWID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AW_WIDTH        = C_AWID_RIGHT + C_AWID_WIDTH;\n  localparam integer C_FIFO_AW_WIDTH   = C_AWUSER_WIDTH+C_AWQOS_WIDTH+C_AWQOS_WIDTH+3+C_AWCACHE_WIDTH+C_AWLOCK_WIDTH+C_AWBURST_WIDTH+C_AWSIZE_WIDTH+C_AWLEN_WIDTH+C_AXI_ADDR_WIDTH+C_AWID_WIDTH;\n\n  // Write Data Port bit positions\n  localparam integer C_WUSER_RIGHT   = 0;\n  localparam integer C_WUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_WUSER_WIDTH : 0;\n  localparam integer C_WLAST_RIGHT   = C_WUSER_RIGHT + C_WUSER_WIDTH;\n  localparam integer C_WLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_WSTRB_RIGHT   = C_WLAST_RIGHT + C_WLAST_WIDTH;\n  localparam integer C_WSTRB_WIDTH     = C_AXI_DATA_WIDTH/8;\n  localparam integer C_WDATA_RIGHT   = C_WSTRB_RIGHT + C_WSTRB_WIDTH;\n  localparam integer C_WDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_WID_RIGHT     = C_WDATA_RIGHT + C_WDATA_WIDTH;\n  localparam integer C_WID_WIDTH       = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_W_WIDTH        = C_WID_RIGHT + C_WID_WIDTH;\n  localparam integer C_FIFO_W_WIDTH   = C_WUSER_WIDTH + C_WLAST_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_DATA_WIDTH + C_WID_WIDTH;\n\n  // Write Response Port bit positions\n  localparam integer C_BUSER_RIGHT   = 0;\n  localparam integer C_BUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_BUSER_WIDTH : 0;\n  localparam integer C_BRESP_RIGHT   = C_BUSER_RIGHT + C_BUSER_WIDTH;\n  localparam integer C_BRESP_WIDTH     = 2;\n  localparam integer C_BID_RIGHT     = C_BRESP_RIGHT + C_BRESP_WIDTH;\n  localparam integer C_BID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_B_WIDTH        = C_BID_RIGHT + C_BID_WIDTH;\n  localparam integer C_FIFO_B_WIDTH    = C_BUSER_WIDTH + 2 + C_BID_WIDTH;\n\n  // Read Address Port bit positions\n  localparam integer C_ARUSER_RIGHT   = 0;\n  localparam integer C_ARUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_ARUSER_WIDTH : 0;\n  localparam integer C_ARQOS_RIGHT    = C_ARUSER_RIGHT + C_ARUSER_WIDTH;\n  localparam integer C_ARQOS_WIDTH      = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARREGION_RIGHT = C_ARQOS_RIGHT + C_ARQOS_WIDTH;\n  localparam integer C_ARREGION_WIDTH   = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;\n  localparam integer C_ARPROT_RIGHT   = C_ARREGION_RIGHT + C_ARREGION_WIDTH;\n  localparam integer C_ARPROT_WIDTH     = 3;\n  localparam integer C_ARCACHE_RIGHT  = C_ARPROT_RIGHT + C_ARPROT_WIDTH;\n  localparam integer C_ARCACHE_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;\n  localparam integer C_ARLOCK_RIGHT   = C_ARCACHE_RIGHT + C_ARCACHE_WIDTH;\n  localparam integer C_ARLOCK_WIDTH     = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ?  2 : 0;\n  localparam integer C_ARBURST_RIGHT  = C_ARLOCK_RIGHT + C_ARLOCK_WIDTH;\n  localparam integer C_ARBURST_WIDTH    = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;\n  localparam integer C_ARSIZE_RIGHT   = C_ARBURST_RIGHT + C_ARBURST_WIDTH;\n  localparam integer C_ARSIZE_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;\n  localparam integer C_ARLEN_RIGHT    = C_ARSIZE_RIGHT + C_ARSIZE_WIDTH;\n  localparam integer C_ARLEN_WIDTH      = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;\n  localparam integer C_ARADDR_RIGHT   = C_ARLEN_RIGHT + C_ARLEN_WIDTH;\n  localparam integer C_ARADDR_WIDTH     = C_AXI_ADDR_WIDTH;\n  localparam integer C_ARID_RIGHT     = C_ARADDR_RIGHT + C_ARADDR_WIDTH;\n  localparam integer C_ARID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_AR_WIDTH        = C_ARID_RIGHT + C_ARID_WIDTH;\n  localparam integer C_FIFO_AR_WIDTH   = C_ARUSER_WIDTH+C_ARQOS_WIDTH+C_ARQOS_WIDTH+3+C_ARCACHE_WIDTH+C_ARLOCK_WIDTH+C_ARBURST_WIDTH+C_ARSIZE_WIDTH+C_ARLEN_WIDTH+C_AXI_ADDR_WIDTH+C_ARID_WIDTH;\n\n  // Read Data Ports bit positions\n  localparam integer C_RUSER_RIGHT   = 0;\n  localparam integer C_RUSER_WIDTH     = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_RUSER_WIDTH : 0;\n  localparam integer C_RLAST_RIGHT   = C_RUSER_RIGHT + C_RUSER_WIDTH;\n  localparam integer C_RLAST_WIDTH     = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;\n  localparam integer C_RRESP_RIGHT   = C_RLAST_RIGHT + C_RLAST_WIDTH;\n  localparam integer C_RRESP_WIDTH     = 2;\n  localparam integer C_RDATA_RIGHT   = C_RRESP_RIGHT + C_RRESP_WIDTH;\n  localparam integer C_RDATA_WIDTH     = C_AXI_DATA_WIDTH;\n  localparam integer C_RID_RIGHT     = C_RDATA_RIGHT + C_RDATA_WIDTH;\n  localparam integer C_RID_WIDTH       = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;\n  localparam integer C_R_WIDTH        = C_RID_RIGHT + C_RID_WIDTH;\n  localparam integer C_FIFO_R_WIDTH   = C_RUSER_WIDTH + C_RLAST_WIDTH + 2 + C_AXI_DATA_WIDTH + C_RID_WIDTH;\n\n  generate\n    if ((C_AXI_IS_ACLK_ASYNC == 0) && (P_ACLK_RATIO == 1)) begin : gen_bypass\n      \n      // Write address port\n      assign m_axi_awid     = s_axi_awid;\n      assign m_axi_awaddr   = s_axi_awaddr;\n      assign m_axi_awlen    = s_axi_awlen;\n      assign m_axi_awsize   = s_axi_awsize;\n      assign m_axi_awburst  = s_axi_awburst;\n      assign m_axi_awlock   = s_axi_awlock;\n      assign m_axi_awcache  = s_axi_awcache;\n      assign m_axi_awprot   = s_axi_awprot;\n      assign m_axi_awregion = s_axi_awregion;\n      assign m_axi_awqos    = s_axi_awqos;\n      assign m_axi_awuser   = s_axi_awuser;\n      assign m_axi_awvalid  = s_axi_awvalid;\n      assign s_axi_awready  = m_axi_awready;\n\n      // Write Data Port\n      assign m_axi_wid      = s_axi_wid;\n      assign m_axi_wdata    = s_axi_wdata;\n      assign m_axi_wstrb    = s_axi_wstrb;\n      assign m_axi_wlast    = s_axi_wlast;\n      assign m_axi_wuser    = s_axi_wuser;\n      assign m_axi_wvalid   = s_axi_wvalid;\n      assign s_axi_wready   = m_axi_wready;\n\n      // Write Response Port\n      assign s_axi_bid      = m_axi_bid;\n      assign s_axi_bresp    = m_axi_bresp;\n      assign s_axi_buser    = m_axi_buser;\n      assign s_axi_bvalid   = m_axi_bvalid;\n      assign m_axi_bready   = s_axi_bready;\n\n      // Read Address Port\n      assign m_axi_arid     = s_axi_arid;\n      assign m_axi_araddr   = s_axi_araddr;\n      assign m_axi_arlen    = s_axi_arlen;\n      assign m_axi_arsize   = s_axi_arsize;\n      assign m_axi_arburst  = s_axi_arburst;\n      assign m_axi_arlock   = s_axi_arlock;\n      assign m_axi_arcache  = s_axi_arcache;\n      assign m_axi_arprot   = s_axi_arprot;\n      assign m_axi_arregion = s_axi_arregion;\n      assign m_axi_arqos    = s_axi_arqos;\n      assign m_axi_aruser   = s_axi_aruser;\n      assign m_axi_arvalid  = s_axi_arvalid;\n      assign s_axi_arready  = m_axi_arready;\n\n      // Read Data Port\n      assign s_axi_rid      = m_axi_rid;\n      assign s_axi_rdata    = m_axi_rdata;\n      assign s_axi_rresp    = m_axi_rresp;\n      assign s_axi_rlast    = m_axi_rlast;\n      assign s_axi_ruser    = m_axi_ruser;\n      assign s_axi_rvalid   = m_axi_rvalid;\n      assign m_axi_rready   = s_axi_rready;\n      \n    end else begin : gen_clock_conv\n      \n      wire fast_aclk;\n      wire slow_aclk;\n      wire sample_cycle;\n      wire sample_cycle_early;\n    \n      // Write Address Port FIFO data read and write\n      wire [C_AW_WIDTH-1:0] s_aw_mesg ;\n      wire [C_AW_WIDTH-1:0] m_aw_mesg ;\n    \n      // Write Data Port FIFO data read and write\n      wire [C_W_WIDTH-1:0] s_w_mesg;\n      wire [C_W_WIDTH-1:0] m_w_mesg;\n    \n      // Write Response Port FIFO data read and write\n      wire [C_B_WIDTH-1:0] s_b_mesg;\n      wire [C_B_WIDTH-1:0] m_b_mesg;\n    \n      // Read Address Port FIFO data read and write\n      wire [C_AR_WIDTH-1:0] s_ar_mesg;\n      wire [C_AR_WIDTH-1:0] m_ar_mesg;\n    \n      // Read Data Ports FIFO data read and write\n      wire [C_R_WIDTH-1:0] s_r_mesg;\n      wire [C_R_WIDTH-1:0] m_r_mesg;\n    \n      wire async_conv_reset_n;\n      assign async_conv_reset_n = ~(~s_axi_aresetn | ~m_axi_aresetn);\n      \n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_awlen           ;\n      wire [3-1:0]                       si_cc_awsize          ;\n      wire [2-1:0]                       si_cc_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_awlock          ;\n      wire [4-1:0]                       si_cc_awcache         ;\n      wire [3-1:0]                       si_cc_awprot          ;\n      wire [4-1:0]                       si_cc_awregion        ;\n      wire [4-1:0]                       si_cc_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]      si_cc_awuser          ;\n      wire                               si_cc_awvalid         ;\n      wire                               si_cc_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_wid            ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]      si_cc_wstrb           ;\n      wire                               si_cc_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]       si_cc_wuser           ;\n      wire                               si_cc_wvalid          ;\n      wire                               si_cc_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_bid             ;\n      wire [2-1:0]                       si_cc_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]       si_cc_buser           ;\n      wire                               si_cc_bvalid          ;\n      wire                               si_cc_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]        si_cc_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] si_cc_arlen           ;\n      wire [3-1:0]                       si_cc_arsize          ;\n      wire [2-1:0]                       si_cc_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] si_cc_arlock          ;\n      wire [4-1:0]                       si_cc_arcache         ;\n      wire [3-1:0]                       si_cc_arprot          ;\n      wire [4-1:0]                       si_cc_arregion        ;\n      wire [4-1:0]                       si_cc_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]      si_cc_aruser          ;\n      wire                               si_cc_arvalid         ;\n      wire                               si_cc_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]          si_cc_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]        si_cc_rdata           ;\n      wire [2-1:0]                       si_cc_rresp           ;\n      wire                               si_cc_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]       si_cc_ruser           ;\n      wire                               si_cc_rvalid          ;\n      wire                               si_cc_rready          ;\n      \n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_awid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_awaddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_awlen           ;\n      wire [3-1:0]                      cc_mi_awsize          ;\n      wire [2-1:0]                      cc_mi_awburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_awlock          ;\n      wire [4-1:0]                      cc_mi_awcache         ;\n      wire [3-1:0]                      cc_mi_awprot          ;\n      wire [4-1:0]                      cc_mi_awregion        ;\n      wire [4-1:0]                      cc_mi_awqos           ;\n      wire [C_AXI_AWUSER_WIDTH-1:0]     cc_mi_awuser          ;\n      wire                              cc_mi_awvalid         ;\n      wire                              cc_mi_awready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_wid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_wdata           ;\n      wire [C_AXI_DATA_WIDTH/8-1:0]     cc_mi_wstrb           ;\n      wire                              cc_mi_wlast           ;\n      wire [C_AXI_WUSER_WIDTH-1:0]      cc_mi_wuser           ;\n      wire                              cc_mi_wvalid          ;\n      wire                              cc_mi_wready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_bid             ;\n      wire [2-1:0]                      cc_mi_bresp           ;\n      wire [C_AXI_BUSER_WIDTH-1:0]      cc_mi_buser           ;\n      wire                              cc_mi_bvalid          ;\n      wire                              cc_mi_bready          ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_arid            ;\n      wire [C_AXI_ADDR_WIDTH-1:0]       cc_mi_araddr          ;\n      wire [((C_AXI_PROTOCOL!=1)?8:4)-1:0] cc_mi_arlen           ;\n      wire [3-1:0]                      cc_mi_arsize          ;\n      wire [2-1:0]                      cc_mi_arburst         ;\n      wire [((C_AXI_PROTOCOL!=1)?1:2)-1:0] cc_mi_arlock          ;\n      wire [4-1:0]                      cc_mi_arcache         ;\n      wire [3-1:0]                      cc_mi_arprot          ;\n      wire [4-1:0]                      cc_mi_arregion        ;\n      wire [4-1:0]                      cc_mi_arqos           ;\n      wire [C_AXI_ARUSER_WIDTH-1:0]     cc_mi_aruser          ;\n      wire                              cc_mi_arvalid         ;\n      wire                              cc_mi_arready         ;\n      wire [C_AXI_ID_WIDTH-1:0]         cc_mi_rid             ;\n      wire [C_AXI_DATA_WIDTH-1:0]       cc_mi_rdata           ;\n      wire [2-1:0]                      cc_mi_rresp           ;\n      wire                              cc_mi_rlast           ;\n      wire [C_AXI_RUSER_WIDTH-1:0]      cc_mi_ruser           ;\n      wire                              cc_mi_rvalid          ;\n      wire                              cc_mi_rready          ;\n      \n    // Tie-offs\n      assign si_cc_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awid : 0 ;\n      assign si_cc_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awaddr : 0 ;\n      assign si_cc_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_awlen : {4'b0000, s_axi_awlen[3:0]}) : 0 ;\n      assign si_cc_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize : 0 ;\n      assign si_cc_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst : 0 ;\n      assign si_cc_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_awlock : {1'b0, s_axi_awlock[0]}) : 0 ;\n      assign si_cc_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache : 0 ;\n      assign si_cc_awprot    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awprot : 0 ;\n      assign si_cc_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos : 0 ;\n      assign si_cc_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion : 0 ;\n      assign si_cc_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser : 0 ;\n      assign si_cc_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awvalid : 0 ;\n      assign si_cc_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? s_axi_wid : 0 ;\n      assign si_cc_wdata     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wdata : 0 ;\n      assign si_cc_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wstrb : 0 ;\n      assign si_cc_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast : 1'b0 ;\n      assign si_cc_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser : 0 ;\n      assign si_cc_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wvalid : 0 ;\n      assign si_cc_bready    = (C_AXI_SUPPORTS_WRITE ) ? s_axi_bready : 0 ;\n      assign si_cc_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arid : 0 ;\n      assign si_cc_araddr    = (C_AXI_SUPPORTS_READ ) ? s_axi_araddr : 0 ;\n      assign si_cc_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? s_axi_arlen : {4'b0000, s_axi_arlen[3:0]}) : 0 ;\n      assign si_cc_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize : 0 ;\n      assign si_cc_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst : 0 ;\n      assign si_cc_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_arlock : {1'b0, s_axi_arlock[0]}) : 0 ;\n      assign si_cc_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache : 0 ;\n      assign si_cc_arprot    = (C_AXI_SUPPORTS_READ ) ? s_axi_arprot : 0 ;\n      assign si_cc_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos : 0 ;\n      assign si_cc_arregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion : 0 ;\n      assign si_cc_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser : 0 ;\n      assign si_cc_arvalid   = (C_AXI_SUPPORTS_READ ) ? s_axi_arvalid : 0 ;\n      assign si_cc_rready    = (C_AXI_SUPPORTS_READ ) ? s_axi_rready : 0 ;                                       \n                                                                                               \n      assign s_axi_awready   = (C_AXI_SUPPORTS_WRITE ) ? si_cc_awready : 0 ;\n      assign s_axi_wready    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_wready : 0 ;\n      assign s_axi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_bid : 0 ;\n      assign s_axi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bresp : 0 ;\n      assign s_axi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_buser : 0 ;\n      assign s_axi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bvalid : 0 ;\n      assign s_axi_arready   = (C_AXI_SUPPORTS_READ ) ? si_cc_arready : 0 ;\n      assign s_axi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rid : 0 ;\n      assign s_axi_rdata     = (C_AXI_SUPPORTS_READ ) ? si_cc_rdata : 0 ;\n      assign s_axi_rresp     = (C_AXI_SUPPORTS_READ ) ? si_cc_rresp : 0 ;\n      assign s_axi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rlast : 0 ;\n      assign s_axi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_ruser : 0 ;\n      assign s_axi_rvalid    = (C_AXI_SUPPORTS_READ ) ? si_cc_rvalid : 0 ;\n\n      assign m_axi_awid      = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awid : 0 ;\n      assign m_axi_awaddr    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awaddr : 0 ;\n      assign m_axi_awlen     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_awlen : cc_mi_awlen[3:0]) : 0 ;\n      assign m_axi_awsize    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awsize : 0 ;\n      assign m_axi_awburst   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awburst : 0 ;\n      assign m_axi_awlock    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_awlock : cc_mi_awlock[0]) : 0 ;\n      assign m_axi_awcache   = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awcache : 0 ;\n      assign m_axi_awprot    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awprot : 0 ;\n      assign m_axi_awregion  = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_awregion : 0 ;\n      assign m_axi_awqos     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awqos : 0 ;\n      assign m_axi_awuser    = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_awuser : 0 ;\n      assign m_axi_awvalid   = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awvalid : 0 ;\n      assign m_axi_wid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? cc_mi_wid : 0 ;\n      assign m_axi_wdata     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wdata : 0 ;\n      assign m_axi_wstrb     = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wstrb : 0 ;\n      assign m_axi_wlast     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_wlast : 0 ;\n      assign m_axi_wuser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_wuser : 0 ;\n      assign m_axi_wvalid    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wvalid : 0 ;\n      assign m_axi_bready    = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_bready : 0 ;\n      assign m_axi_arid      = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arid : 0 ;\n      assign m_axi_araddr    = (C_AXI_SUPPORTS_READ ) ? cc_mi_araddr : 0 ;\n      assign m_axi_arlen     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL!=P_AXI3 ) ? cc_mi_arlen : cc_mi_arlen[3:0]) : 0 ;\n      assign m_axi_arsize    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arsize : 0 ;\n      assign m_axi_arburst   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arburst : 0 ;\n      assign m_axi_arlock    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_arlock : cc_mi_arlock[0]) : 0 ;\n      assign m_axi_arcache   = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arcache : 0 ;\n      assign m_axi_arprot    = (C_AXI_SUPPORTS_READ ) ? cc_mi_arprot : 0 ;\n      assign m_axi_arregion  = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_arregion : 0 ;\n      assign m_axi_arqos     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arqos : 0 ;\n      assign m_axi_aruser    = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_aruser : 0 ;\n      assign m_axi_arvalid   = (C_AXI_SUPPORTS_READ ) ? cc_mi_arvalid : 0 ;\n      assign m_axi_rready    = (C_AXI_SUPPORTS_READ ) ? cc_mi_rready : 0 ;\n                                                                                                                                                                                                                                                                                        \n      assign cc_mi_awready   = (C_AXI_SUPPORTS_WRITE ) ? m_axi_awready : 0 ;\n      assign cc_mi_wready    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_wready : 0 ;\n      assign cc_mi_bid       = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid : 0 ;\n      assign cc_mi_bresp     = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bresp : 0 ;\n      assign cc_mi_buser     = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser : 0 ;\n      assign cc_mi_bvalid    = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bvalid : 0 ;\n      assign cc_mi_arready   = (C_AXI_SUPPORTS_READ ) ? m_axi_arready : 0 ;\n      assign cc_mi_rid       = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid : 0 ;\n      assign cc_mi_rdata     = (C_AXI_SUPPORTS_READ ) ? m_axi_rdata : 0 ;\n      assign cc_mi_rresp     = (C_AXI_SUPPORTS_READ ) ? m_axi_rresp : 0 ;\n      assign cc_mi_rlast     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast : 1'b0 ;\n      assign cc_mi_ruser     = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser : 0 ;\n      assign cc_mi_rvalid    = (C_AXI_SUPPORTS_READ ) ? m_axi_rvalid : 0 ;\n      \n      if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL!=P_AXILITE)) begin : gen_async_conv\n        \n        fifo_generator_v13_2_1 #(\n          .C_EN_SAFETY_CKT(0),\n          .C_SELECT_XPM(0),\n          .C_INTERFACE_TYPE(2),\n          .C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ? 3 : 2),\n          .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),\n          .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),\n          .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),\n          .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),\n          .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),\n          .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),\n          .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),\n          .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),\n          .C_HAS_AXI_ID((C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0),\n          .C_AXI_LEN_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 8 : 4),\n          .C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL != P_AXI3) ? 1 : 2),\n          .C_HAS_AXI_ARUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_AWUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_BUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_RUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_HAS_AXI_WUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),\n          .C_DIN_WIDTH_RACH(C_FIFO_AR_WIDTH),\n          .C_DIN_WIDTH_RDCH(C_FIFO_R_WIDTH),\n          .C_DIN_WIDTH_WACH(C_FIFO_AW_WIDTH),\n          .C_DIN_WIDTH_WDCH(C_FIFO_W_WIDTH),\n          .C_DIN_WIDTH_WRCH(C_FIFO_B_WIDTH),\n          .C_HAS_AXI_RD_CHANNEL(C_AXI_SUPPORTS_READ),\n          .C_HAS_AXI_WR_CHANNEL(C_AXI_SUPPORTS_WRITE),\n          .C_RACH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_RDCH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),\n          .C_WACH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WDCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_WRCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),\n          .C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),\n          .C_COMMON_CLOCK(0),\n          .C_COUNT_TYPE(0),\n          .C_DATA_COUNT_WIDTH(10),\n          .C_DEFAULT_VALUE(\"BlankString\"),\n          .C_DIN_WIDTH(18),\n          .C_DOUT_RST_VAL(\"0\"),\n          .C_DOUT_WIDTH(18),\n          .C_ENABLE_RLOCS(0),\n          .C_FAMILY(C_FAMILY),\n          .C_FULL_FLAGS_RST_VAL(1),\n          .C_HAS_ALMOST_EMPTY(0),\n          .C_HAS_ALMOST_FULL(0),\n          .C_HAS_BACKUP(0),\n          .C_HAS_DATA_COUNT(0),\n          .C_HAS_INT_CLK(0),\n          .C_HAS_MEMINIT_FILE(0),\n          .C_HAS_OVERFLOW(0),\n          .C_HAS_RD_DATA_COUNT(0),\n          .C_HAS_RD_RST(0),\n          .C_HAS_RST(1),\n          .C_HAS_SRST(0),\n          .C_HAS_UNDERFLOW(0),\n          .C_HAS_VALID(0),\n          .C_HAS_WR_ACK(0),\n          .C_HAS_WR_DATA_COUNT(0),\n          .C_HAS_WR_RST(0),\n          .C_IMPLEMENTATION_TYPE(0),\n          .C_INIT_WR_PNTR_VAL(0),\n          .C_MEMORY_TYPE(1),\n          .C_MIF_FILE_NAME(\"BlankString\"),\n          .C_OPTIMIZATION_MODE(0),\n          .C_OVERFLOW_LOW(0),\n          .C_PRELOAD_LATENCY(1),\n          .C_PRELOAD_REGS(0),\n          .C_PRIM_FIFO_TYPE(\"4kx4\"),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),\n          .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),\n          .C_PROG_EMPTY_TYPE(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL(1022),\n          .C_PROG_FULL_THRESH_NEGATE_VAL(1021),\n          .C_PROG_FULL_TYPE(0),\n          .C_RD_DATA_COUNT_WIDTH(10),\n          .C_RD_DEPTH(1024),\n          .C_RD_FREQ(1),\n          .C_RD_PNTR_WIDTH(10),\n          .C_UNDERFLOW_LOW(0),\n          .C_USE_DOUT_RST(1),\n          .C_USE_ECC(0),\n          .C_USE_EMBEDDED_REG(0),\n          .C_USE_FIFO16_FLAGS(0),\n          .C_USE_FWFT_DATA_COUNT(0),\n          .C_VALID_LOW(0),\n          .C_WR_ACK_LOW(0),\n          .C_WR_DATA_COUNT_WIDTH(10),\n          .C_WR_DEPTH(1024),\n          .C_WR_FREQ(1),\n          .C_WR_PNTR_WIDTH(10),\n          .C_WR_RESPONSE_LATENCY(1),\n          .C_MSGON_VAL(1),\n          .C_ENABLE_RST_SYNC(1),\n          .C_ERROR_INJECTION_TYPE(0),\n          .C_HAS_SLAVE_CE(0),\n          .C_HAS_MASTER_CE(0),\n          .C_ADD_NGC_CONSTRAINT(0),\n          .C_USE_COMMON_OVERFLOW(0),\n          .C_USE_COMMON_UNDERFLOW(0),\n          .C_USE_DEFAULT_SETTINGS(0),\n          .C_HAS_AXIS_TDATA(1),\n          .C_HAS_AXIS_TID(0),\n          .C_HAS_AXIS_TDEST(0),\n          .C_HAS_AXIS_TUSER(1),\n          .C_HAS_AXIS_TREADY(1),\n          .C_HAS_AXIS_TLAST(0),\n          .C_HAS_AXIS_TSTRB(0),\n          .C_HAS_AXIS_TKEEP(0),\n          .C_AXIS_TDATA_WIDTH(8),\n          .C_AXIS_TID_WIDTH(1),\n          .C_AXIS_TDEST_WIDTH(1),\n          .C_AXIS_TUSER_WIDTH(4),\n          .C_AXIS_TSTRB_WIDTH(1),\n          .C_AXIS_TKEEP_WIDTH(1),\n          .C_AXIS_TYPE(0),\n          .C_IMPLEMENTATION_TYPE_WACH(12),\n          .C_IMPLEMENTATION_TYPE_WDCH(12),\n          .C_IMPLEMENTATION_TYPE_WRCH(12),\n          .C_IMPLEMENTATION_TYPE_RACH(12),\n          .C_IMPLEMENTATION_TYPE_RDCH(12),\n          .C_IMPLEMENTATION_TYPE_AXIS(11),\n          .C_APPLICATION_TYPE_WACH(0),\n          .C_APPLICATION_TYPE_WDCH(0),\n          .C_APPLICATION_TYPE_WRCH(0),\n          .C_APPLICATION_TYPE_RACH(0),\n          .C_APPLICATION_TYPE_RDCH(0),\n          .C_APPLICATION_TYPE_AXIS(0),\n          .C_USE_ECC_WACH(0),\n          .C_USE_ECC_WDCH(0),\n          .C_USE_ECC_WRCH(0),\n          .C_USE_ECC_RACH(0),\n          .C_USE_ECC_RDCH(0),\n          .C_USE_ECC_AXIS(0),\n          .C_ERROR_INJECTION_TYPE_WACH(0),\n          .C_ERROR_INJECTION_TYPE_WDCH(0),\n          .C_ERROR_INJECTION_TYPE_WRCH(0),\n          .C_ERROR_INJECTION_TYPE_RACH(0),\n          .C_ERROR_INJECTION_TYPE_RDCH(0),\n          .C_ERROR_INJECTION_TYPE_AXIS(0),\n          .C_DIN_WIDTH_AXIS(1),\n          .C_WR_DEPTH_WACH(16),\n          .C_WR_DEPTH_WDCH(16),\n          .C_WR_DEPTH_WRCH(16),\n          .C_WR_DEPTH_RACH(16),\n          .C_WR_DEPTH_RDCH(16),\n          .C_WR_DEPTH_AXIS(1024),\n          .C_WR_PNTR_WIDTH_WACH(4),\n          .C_WR_PNTR_WIDTH_WDCH(4),\n          .C_WR_PNTR_WIDTH_WRCH(4),\n          .C_WR_PNTR_WIDTH_RACH(4),\n          .C_WR_PNTR_WIDTH_RDCH(4),\n          .C_WR_PNTR_WIDTH_AXIS(10),\n          .C_HAS_DATA_COUNTS_WACH(0),\n          .C_HAS_DATA_COUNTS_WDCH(0),\n          .C_HAS_DATA_COUNTS_WRCH(0),\n          .C_HAS_DATA_COUNTS_RACH(0),\n          .C_HAS_DATA_COUNTS_RDCH(0),\n          .C_HAS_DATA_COUNTS_AXIS(0),\n          .C_HAS_PROG_FLAGS_WACH(0),\n          .C_HAS_PROG_FLAGS_WDCH(0),\n          .C_HAS_PROG_FLAGS_WRCH(0),\n          .C_HAS_PROG_FLAGS_RACH(0),\n          .C_HAS_PROG_FLAGS_RDCH(0),\n          .C_HAS_PROG_FLAGS_AXIS(0),\n          .C_PROG_FULL_TYPE_WACH(0),\n          .C_PROG_FULL_TYPE_WDCH(0),\n          .C_PROG_FULL_TYPE_WRCH(0),\n          .C_PROG_FULL_TYPE_RACH(0),\n          .C_PROG_FULL_TYPE_RDCH(0),\n          .C_PROG_FULL_TYPE_AXIS(0),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(15),\n          .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),\n          .C_PROG_EMPTY_TYPE_WACH(0),\n          .C_PROG_EMPTY_TYPE_WDCH(0),\n          .C_PROG_EMPTY_TYPE_WRCH(0),\n          .C_PROG_EMPTY_TYPE_RACH(0),\n          .C_PROG_EMPTY_TYPE_RDCH(0),\n          .C_PROG_EMPTY_TYPE_AXIS(0),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(13),\n          .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1021),\n          .C_REG_SLICE_MODE_WACH(0),\n          .C_REG_SLICE_MODE_WDCH(0),\n          .C_REG_SLICE_MODE_WRCH(0),\n          .C_REG_SLICE_MODE_RACH(0),\n          .C_REG_SLICE_MODE_RDCH(0),\n          .C_REG_SLICE_MODE_AXIS(0)\n          )\n          asyncfifo_axi (\n            .s_aclk(s_axi_aclk),\n            .m_aclk(m_axi_aclk),\n            .s_aresetn(async_conv_reset_n),\n            .s_axi_awid           (si_cc_awid),\n            .s_axi_awaddr         (si_cc_awaddr),\n            .s_axi_awlen          (si_cc_awlen),\n            .s_axi_awsize         (si_cc_awsize),\n            .s_axi_awburst        (si_cc_awburst),\n            .s_axi_awlock         (si_cc_awlock),\n            .s_axi_awcache        (si_cc_awcache),\n            .s_axi_awprot         (si_cc_awprot),\n            .s_axi_awqos          (si_cc_awqos),\n            .s_axi_awregion       (si_cc_awregion),\n            .s_axi_awuser         (si_cc_awuser),\n            .s_axi_awvalid        (si_cc_awvalid),\n            .s_axi_awready        (si_cc_awready),\n            .s_axi_wid            (si_cc_wid),\n            .s_axi_wdata          (si_cc_wdata),\n            .s_axi_wstrb          (si_cc_wstrb),\n            .s_axi_wlast          (si_cc_wlast),\n            .s_axi_wuser          (si_cc_wuser),\n            .s_axi_wvalid         (si_cc_wvalid),\n            .s_axi_wready         (si_cc_wready),\n            .s_axi_bid            (si_cc_bid),\n            .s_axi_bresp          (si_cc_bresp),\n            .s_axi_buser          (si_cc_buser),\n            .s_axi_bvalid         (si_cc_bvalid),\n            .s_axi_bready         (si_cc_bready),\n            .m_axi_awid           (cc_mi_awid),\n            .m_axi_awaddr         (cc_mi_awaddr),\n            .m_axi_awlen          (cc_mi_awlen),\n            .m_axi_awsize         (cc_mi_awsize),\n            .m_axi_awburst        (cc_mi_awburst),\n            .m_axi_awlock         (cc_mi_awlock),\n            .m_axi_awcache        (cc_mi_awcache),\n            .m_axi_awprot         (cc_mi_awprot),\n            .m_axi_awqos          (cc_mi_awqos),\n            .m_axi_awregion       (cc_mi_awregion),\n            .m_axi_awuser         (cc_mi_awuser),\n            .m_axi_awvalid        (cc_mi_awvalid),\n            .m_axi_awready        (cc_mi_awready),\n            .m_axi_wid            (cc_mi_wid),\n            .m_axi_wdata          (cc_mi_wdata),\n            .m_axi_wstrb          (cc_mi_wstrb),\n            .m_axi_wlast          (cc_mi_wlast),\n            .m_axi_wuser          (cc_mi_wuser),\n            .m_axi_wvalid         (cc_mi_wvalid),\n            .m_axi_wready         (cc_mi_wready),\n            .m_axi_bid            (cc_mi_bid),\n            .m_axi_bresp          (cc_mi_bresp),\n            .m_axi_buser          (cc_mi_buser),\n            .m_axi_bvalid         (cc_mi_bvalid),\n            .m_axi_bready         (cc_mi_bready),\n            .s_axi_arid           (si_cc_arid),\n            .s_axi_araddr         (si_cc_araddr),\n            .s_axi_arlen          (si_cc_arlen),\n            .s_axi_arsize         (si_cc_arsize),\n            .s_axi_arburst        (si_cc_arburst),\n            .s_axi_arlock         (si_cc_arlock),\n            .s_axi_arcache        (si_cc_arcache),\n            .s_axi_arprot         (si_cc_arprot),\n            .s_axi_arqos          (si_cc_arqos),\n            .s_axi_arregion       (si_cc_arregion),\n            .s_axi_aruser         (si_cc_aruser),\n            .s_axi_arvalid        (si_cc_arvalid),\n            .s_axi_arready        (si_cc_arready),\n            .s_axi_rid            (si_cc_rid),\n            .s_axi_rdata          (si_cc_rdata),\n            .s_axi_rresp          (si_cc_rresp),\n            .s_axi_rlast          (si_cc_rlast),\n            .s_axi_ruser          (si_cc_ruser),\n            .s_axi_rvalid         (si_cc_rvalid),\n            .s_axi_rready         (si_cc_rready),\n            .m_axi_arid           (cc_mi_arid),\n            .m_axi_araddr         (cc_mi_araddr),\n            .m_axi_arlen          (cc_mi_arlen),\n            .m_axi_arsize         (cc_mi_arsize),\n            .m_axi_arburst        (cc_mi_arburst),\n            .m_axi_arlock         (cc_mi_arlock),\n            .m_axi_arcache        (cc_mi_arcache),\n            .m_axi_arprot         (cc_mi_arprot),\n            .m_axi_arqos          (cc_mi_arqos),\n            .m_axi_arregion       (cc_mi_arregion),\n            .m_axi_aruser         (cc_mi_aruser),\n            .m_axi_arvalid        (cc_mi_arvalid),\n            .m_axi_arready        (cc_mi_arready),\n            .m_axi_rid            (cc_mi_rid),\n            .m_axi_rdata          (cc_mi_rdata),\n            .m_axi_rresp          (cc_mi_rresp),\n            .m_axi_rlast          (cc_mi_rlast),\n            .m_axi_ruser          (cc_mi_ruser),\n            .m_axi_rvalid         (cc_mi_rvalid),\n            .m_axi_rready         (cc_mi_rready),\n            .m_aclk_en(1'b1),\n            .s_aclk_en(1'b1),\n            .almost_empty(),\n            .almost_full(),\n            .axis_data_count(),\n            .axis_dbiterr(),\n            .axis_injectdbiterr(1'b0),\n            .axis_injectsbiterr(1'b0),\n            .axis_overflow(),\n            .axis_prog_empty(),\n            .axis_prog_empty_thresh(10'b0),\n            .axis_prog_full(),\n            .axis_prog_full_thresh(10'b0),\n            .axis_rd_data_count(),\n            .axis_sbiterr(),\n            .axis_underflow(),\n            .axis_wr_data_count(),\n            .axi_ar_data_count(),\n            .axi_ar_dbiterr(),\n            .axi_ar_injectdbiterr(1'b0),\n            .axi_ar_injectsbiterr(1'b0),\n            .axi_ar_overflow(),\n            .axi_ar_prog_empty(),\n            .axi_ar_prog_empty_thresh(4'b0),\n            .axi_ar_prog_full(),\n            .axi_ar_prog_full_thresh(4'b0),\n            .axi_ar_rd_data_count(),\n            .axi_ar_sbiterr(),\n            .axi_ar_underflow(),\n            .axi_ar_wr_data_count(),\n            .axi_aw_data_count(),\n            .axi_aw_dbiterr(),\n            .axi_aw_injectdbiterr(1'b0),\n            .axi_aw_injectsbiterr(1'b0),\n            .axi_aw_overflow(),\n            .axi_aw_prog_empty(),\n            .axi_aw_prog_empty_thresh(4'b0),\n            .axi_aw_prog_full(),\n            .axi_aw_prog_full_thresh(4'b0),\n            .axi_aw_rd_data_count(),\n            .axi_aw_sbiterr(),\n            .axi_aw_underflow(),\n            .axi_aw_wr_data_count(),\n            .axi_b_data_count(),\n            .axi_b_dbiterr(),\n            .axi_b_injectdbiterr(1'b0),\n            .axi_b_injectsbiterr(1'b0),\n            .axi_b_overflow(),\n            .axi_b_prog_empty(),\n            .axi_b_prog_empty_thresh(4'b0),\n            .axi_b_prog_full(),\n            .axi_b_prog_full_thresh(4'b0),\n            .axi_b_rd_data_count(),\n            .axi_b_sbiterr(),\n            .axi_b_underflow(),\n            .axi_b_wr_data_count(),\n            .axi_r_data_count(),\n            .axi_r_dbiterr(),\n            .axi_r_injectdbiterr(1'b0),\n            .axi_r_injectsbiterr(1'b0),\n            .axi_r_overflow(),\n            .axi_r_prog_empty(),\n            .axi_r_prog_empty_thresh(4'b0),\n            .axi_r_prog_full(),\n            .axi_r_prog_full_thresh(4'b0),\n            .axi_r_rd_data_count(),\n            .axi_r_sbiterr(),\n            .axi_r_underflow(),\n            .axi_r_wr_data_count(),\n            .axi_w_data_count(),\n            .axi_w_dbiterr(),\n            .axi_w_injectdbiterr(1'b0),\n            .axi_w_injectsbiterr(1'b0),\n            .axi_w_overflow(),\n            .axi_w_prog_empty(),\n            .axi_w_prog_empty_thresh(4'b0),\n            .axi_w_prog_full(),\n            .axi_w_prog_full_thresh(4'b0),\n            .axi_w_rd_data_count(),\n            .axi_w_sbiterr(),\n            .axi_w_underflow(),\n            .axi_w_wr_data_count(),\n            .backup(1'b0),\n            .backup_marker(1'b0),\n            .clk(1'b0),\n            .data_count(),\n            .dbiterr(),\n            .din(18'b0),\n            .dout(),\n            .empty(),\n            .full(),\n            .injectdbiterr(1'b0),\n            .injectsbiterr(1'b0),\n            .int_clk(1'b0),\n            .m_axis_tdata(),\n            .m_axis_tdest(),\n            .m_axis_tid(),\n            .m_axis_tkeep(),\n            .m_axis_tlast(),\n            .m_axis_tready(1'b0),\n            .m_axis_tstrb(),\n            .m_axis_tuser(),\n            .m_axis_tvalid(),\n            .overflow(),\n            .prog_empty(),\n            .prog_empty_thresh(10'b0),\n            .prog_empty_thresh_assert(10'b0),\n            .prog_empty_thresh_negate(10'b0),\n            .prog_full(),\n            .prog_full_thresh(10'b0),\n            .prog_full_thresh_assert(10'b0),\n            .prog_full_thresh_negate(10'b0),\n            .rd_clk(1'b0),\n            .rd_data_count(),\n            .rd_en(1'b0),\n            .rd_rst(1'b0),\n            .rst(1'b0),\n            .sbiterr(),\n            .srst(1'b0),\n            .s_axis_tdata(8'b0),\n            .s_axis_tdest(1'b0),\n            .s_axis_tid(1'b0),\n            .s_axis_tkeep(1'b0),\n            .s_axis_tlast(1'b0),\n            .s_axis_tready(),\n            .s_axis_tstrb(1'b0),\n            .s_axis_tuser(4'b0),\n            .s_axis_tvalid(1'b0),\n            .underflow(),\n            .valid(),\n            .wr_ack(),\n            .wr_clk(1'b0),\n            .wr_data_count(),\n            .wr_en(1'b0),\n            .wr_rst(1'b0),\n            .wr_rst_busy(),\n            .rd_rst_busy(),\n            .sleep(1'b0)\n        );\n      end else if ((C_AXI_IS_ACLK_ASYNC) && (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_async_lite_conv\n        localparam C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n        `include \"axi_infrastructure_v1_1_0.vh\"\n\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n        wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n        wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n        wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n        wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n        wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n        axi_infrastructure_v1_1_0_axi2vector #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        axi2vec ( \n          .s_axi_awid      ( si_cc_awid      ) ,\n          .s_axi_awaddr    ( si_cc_awaddr    ) ,\n          .s_axi_awlen     ( s_axi_awlen     ) ,\n          .s_axi_awsize    ( si_cc_awsize    ) ,\n          .s_axi_awburst   ( si_cc_awburst   ) ,\n          .s_axi_awlock    ( s_axi_awlock    ) ,\n          .s_axi_awcache   ( si_cc_awcache   ) ,\n          .s_axi_awprot    ( si_cc_awprot    ) ,\n          .s_axi_awqos     ( si_cc_awqos     ) ,\n          .s_axi_awuser    ( si_cc_awuser    ) ,\n          .s_axi_awregion  ( si_cc_awregion  ) ,\n          .s_axi_wid       ( si_cc_wid       ) ,\n          .s_axi_wdata     ( si_cc_wdata     ) ,\n          .s_axi_wstrb     ( si_cc_wstrb     ) ,\n          .s_axi_wlast     ( si_cc_wlast     ) ,\n          .s_axi_wuser     ( si_cc_wuser     ) ,\n          .s_axi_bid       ( si_cc_bid       ) ,\n          .s_axi_bresp     ( si_cc_bresp     ) ,\n          .s_axi_buser     ( si_cc_buser     ) ,\n          .s_axi_arid      ( si_cc_arid      ) ,\n          .s_axi_araddr    ( si_cc_araddr    ) ,\n          .s_axi_arlen     ( s_axi_arlen     ) ,\n          .s_axi_arsize    ( si_cc_arsize    ) ,\n          .s_axi_arburst   ( si_cc_arburst   ) ,\n          .s_axi_arlock    ( s_axi_arlock    ) ,\n          .s_axi_arcache   ( si_cc_arcache   ) ,\n          .s_axi_arprot    ( si_cc_arprot    ) ,\n          .s_axi_arqos     ( si_cc_arqos     ) ,\n          .s_axi_aruser    ( si_cc_aruser    ) ,\n          .s_axi_arregion  ( si_cc_arregion  ) ,\n          .s_axi_rid       ( si_cc_rid       ) ,\n          .s_axi_rdata     ( si_cc_rdata     ) ,\n          .s_axi_rresp     ( si_cc_rresp     ) ,\n          .s_axi_rlast     ( si_cc_rlast     ) ,\n          .s_axi_ruser     ( si_cc_ruser     ) ,\n          .s_awpayload     ( s_awpayload ) ,\n          .s_wpayload      ( s_wpayload  ) ,\n          .s_bpayload      ( s_bpayload  ) ,\n          .s_arpayload     ( s_arpayload ) ,\n          .s_rpayload      ( s_rpayload  ) \n        );\n\n        axi_clock_converter_v2_1_14_lite_async #(\n          .C_DEST_SYNC_FF (2),\n          .C_SRC_SYNC_FF  (2),\n          .C_WIDTH        (G_AXI_AWPAYLOAD_WIDTH)\n        ) aw_handshake (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_awvalid),\n          .s_ready  (si_cc_awready),\n          .s_payld  (s_awpayload),\n          .m_valid  (cc_mi_awvalid),\n          .m_ready  (cc_mi_awready),\n          .m_payld  (m_awpayload)\n        );\n\n        axi_clock_converter_v2_1_14_lite_async #(\n          .C_DEST_SYNC_FF (2),\n          .C_SRC_SYNC_FF  (2),\n          .C_WIDTH        (G_AXI_ARPAYLOAD_WIDTH)\n        ) ar_handshake (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_arvalid),\n          .s_ready  (si_cc_arready),\n          .s_payld  (s_arpayload),\n          .m_valid  (cc_mi_arvalid),\n          .m_ready  (cc_mi_arready),\n          .m_payld  (m_arpayload)\n        );\n\n        axi_clock_converter_v2_1_14_lite_async #(\n          .C_DEST_SYNC_FF (2),\n          .C_SRC_SYNC_FF  (2),\n          .C_WIDTH        (G_AXI_WPAYLOAD_WIDTH)\n        ) w_handshake (\n          .s_aclk   (s_axi_aclk),\n          .m_aclk   (m_axi_aclk),\n          .s_aresetn(s_axi_aresetn),\n          .m_aresetn(m_axi_aresetn),\n          .s_valid  (si_cc_wvalid),\n          .s_ready  (si_cc_wready),\n          .s_payld  (s_wpayload),\n          .m_valid  (cc_mi_wvalid),\n          .m_ready  (cc_mi_wready),\n          .m_payld  (m_wpayload)\n        );\n\n        axi_clock_converter_v2_1_14_lite_async #(\n          .C_DEST_SYNC_FF (2),\n          .C_SRC_SYNC_FF  (2),\n          .C_WIDTH        (G_AXI_BPAYLOAD_WIDTH)\n        ) b_handshake (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_bvalid),\n          .s_ready  (cc_mi_bready),\n          .s_payld  (m_bpayload),\n          .m_valid  (si_cc_bvalid),\n          .m_ready  (si_cc_bready),\n          .m_payld  (s_bpayload)\n        );\n\n        axi_clock_converter_v2_1_14_lite_async #(\n          .C_DEST_SYNC_FF (2),\n          .C_SRC_SYNC_FF  (2),\n          .C_WIDTH        (G_AXI_RPAYLOAD_WIDTH)\n        ) r_handshake (\n          .s_aclk   (m_axi_aclk),\n          .m_aclk   (s_axi_aclk),\n          .s_aresetn(m_axi_aresetn),\n          .m_aresetn(s_axi_aresetn),\n          .s_valid  (cc_mi_rvalid),\n          .s_ready  (cc_mi_rready),\n          .s_payld  (m_rpayload),\n          .m_valid  (si_cc_rvalid),\n          .m_ready  (si_cc_rready),\n          .m_payld  (s_rpayload)\n        );\n\n        axi_infrastructure_v1_1_0_vector2axi #( \n          .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n          .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n          .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n          .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n          .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n          .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n          .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n          .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n          .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n          .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n          .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n          .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n          .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n          .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n          .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n          .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n        )\n        vec2axi ( \n          .m_awpayload    ( m_awpayload    ) ,\n          .m_wpayload     ( m_wpayload     ) ,\n          .m_bpayload     ( m_bpayload     ) ,\n          .m_arpayload    ( m_arpayload    ) ,\n          .m_rpayload     ( m_rpayload     ) ,\n          .m_axi_awid     ( cc_mi_awid     ) ,\n          .m_axi_awaddr   ( cc_mi_awaddr   ) ,\n          .m_axi_awlen    ( cc_mi_awlen    ) ,\n          .m_axi_awsize   ( cc_mi_awsize   ) ,\n          .m_axi_awburst  ( cc_mi_awburst  ) ,\n          .m_axi_awlock   ( cc_mi_awlock   ) ,\n          .m_axi_awcache  ( cc_mi_awcache  ) ,\n          .m_axi_awprot   ( cc_mi_awprot   ) ,\n          .m_axi_awqos    ( cc_mi_awqos    ) ,\n          .m_axi_awuser   ( cc_mi_awuser   ) ,\n          .m_axi_awregion ( cc_mi_awregion ) ,\n          .m_axi_wid      ( cc_mi_wid      ) ,\n          .m_axi_wdata    ( cc_mi_wdata    ) ,\n          .m_axi_wstrb    ( cc_mi_wstrb    ) ,\n          .m_axi_wlast    ( cc_mi_wlast    ) ,\n          .m_axi_wuser    ( cc_mi_wuser    ) ,\n          .m_axi_bid      ( cc_mi_bid      ) ,\n          .m_axi_bresp    ( cc_mi_bresp    ) ,\n          .m_axi_buser    ( cc_mi_buser    ) ,\n          .m_axi_arid     ( cc_mi_arid     ) ,\n          .m_axi_araddr   ( cc_mi_araddr   ) ,\n          .m_axi_arlen    ( cc_mi_arlen    ) ,\n          .m_axi_arsize   ( cc_mi_arsize   ) ,\n          .m_axi_arburst  ( cc_mi_arburst  ) ,\n          .m_axi_arlock   ( cc_mi_arlock   ) ,\n          .m_axi_arcache  ( cc_mi_arcache  ) ,\n          .m_axi_arprot   ( cc_mi_arprot   ) ,\n          .m_axi_arqos    ( cc_mi_arqos    ) ,\n          .m_axi_aruser   ( cc_mi_aruser   ) ,\n          .m_axi_arregion ( cc_mi_arregion ) ,\n          .m_axi_rid      ( cc_mi_rid      ) ,\n          .m_axi_rdata    ( cc_mi_rdata    ) ,\n          .m_axi_rresp    ( cc_mi_rresp    ) ,\n          .m_axi_rlast    ( cc_mi_rlast    ) ,\n          .m_axi_ruser    ( cc_mi_ruser    ) \n        );\n\n      end else begin : gen_sync_conv\n        \n        assign {fast_aclk, slow_aclk} = P_SI_LT_MI ? {m_axi_aclk, s_axi_aclk} : {s_axi_aclk, m_axi_aclk};\n    \n        // Sample cycle used to determine when to assert a signal on a fast clock\n        // to be flopped onto a slow clock.\n        axi_clock_converter_v2_1_14_axic_sample_cycle_ratio #(\n          .C_RATIO ( P_ACLK_RATIO )\n        )\n        axic_sample_cycle_inst (\n          .SLOW_ACLK          ( slow_aclk               ) ,\n          .FAST_ACLK          ( fast_aclk               ) ,\n          .SAMPLE_CYCLE_EARLY ( sample_cycle_early ) ,\n          .SAMPLE_CYCLE       ( sample_cycle       )\n        );\n    \n      ////////////////////////////////////////////////////////////////////////////////\n      // AXI write channels\n      ////////////////////////////////////////////////////////////////////////////////\n        if (C_AXI_SUPPORTS_WRITE) begin : gen_conv_write_ch\n    \n          // Write Address Port\n          assign s_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH]     = si_cc_awaddr   ;\n          assign s_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH]     = si_cc_awprot   ;\n          assign cc_mi_awaddr   = m_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH];\n          assign cc_mi_awprot   = m_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_aw_axi4\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen    ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock[0] ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH] = si_cc_awregion ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awregion = m_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_aw_axi3\n            assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH]         = si_cc_awid     ;\n            assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH]       = si_cc_awlen[3:0] ;\n            assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH]     = si_cc_awsize   ;\n            assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH]   = si_cc_awburst  ;\n            assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH]     = si_cc_awlock   ;\n            assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH]   = si_cc_awcache  ;\n            assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH]       = si_cc_awqos    ;\n            assign cc_mi_awid     = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];\n            assign cc_mi_awlen    = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];\n            assign cc_mi_awsize   = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];\n            assign cc_mi_awburst  = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];\n            assign cc_mi_awlock   = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];\n            assign cc_mi_awcache  = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];\n            assign cc_mi_awqos    = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_aw_user\n            assign s_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH]  = si_cc_awuser;\n            assign cc_mi_awuser = m_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_14_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AW_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          aw_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_aw_mesg ) ,\n            .S_VALID   ( si_cc_awvalid   ) ,\n            .S_READY   ( si_cc_awready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_aw_mesg ) ,\n            .M_VALID   ( cc_mi_awvalid   ) ,\n            .M_READY   ( cc_mi_awready   )\n          );\n    \n          // Write Data Port\n          assign s_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH] = si_cc_wdata; \n          assign s_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH] = si_cc_wstrb; \n          assign cc_mi_wdata    = m_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH];\n          assign cc_mi_wstrb    = m_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_w_axi4\n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_w_axi3\n            assign s_w_mesg[C_WID_RIGHT+:C_WID_WIDTH]     = si_cc_wid; \n            assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;\n            assign cc_mi_wid      = m_w_mesg[C_WID_RIGHT+:C_WID_WIDTH];\n            assign cc_mi_wlast    = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_w_user\n            assign s_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH]  = si_cc_wuser;\n            assign cc_mi_wuser = m_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_14_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH  ( C_W_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE           ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          w_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_w_mesg ) ,\n            .S_VALID   ( si_cc_wvalid   ) ,\n            .S_READY   ( si_cc_wready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_w_mesg ) ,\n            .M_VALID   ( cc_mi_wvalid   ) ,\n            .M_READY   ( cc_mi_wready   )\n          );\n    \n          // Write Response Port\n          assign m_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH] = cc_mi_bresp;\n          assign si_cc_bresp    = s_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_b_axi\n            assign m_b_mesg[C_BID_RIGHT+:C_BID_WIDTH]     = cc_mi_bid;\n            assign si_cc_bid      = s_b_mesg[C_BID_RIGHT+:C_BID_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_b_user\n            assign m_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH] = cc_mi_buser;\n            assign si_cc_buser  = s_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_14_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_B_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          b_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_b_mesg ) ,\n            .S_VALID   ( cc_mi_bvalid   ) ,\n            .S_READY   ( cc_mi_bready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_b_mesg ) ,\n            .M_VALID   ( si_cc_bvalid   ) ,\n            .M_READY   ( si_cc_bready   )\n          );\n    \n        end else begin : gen_tieoff_write_ch\n    \n          // Write address port\n          assign cc_mi_awid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_awaddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_awlen    = {8{1'b0}};\n          assign cc_mi_awsize   = {3{1'b0}};\n          assign cc_mi_awburst  = {2{1'b0}};\n          assign cc_mi_awlock   = {2{1'b0}};\n          assign cc_mi_awcache  = {4{1'b0}};\n          assign cc_mi_awprot   = {3{1'b0}};\n          assign cc_mi_awregion = {4{1'b0}};\n          assign cc_mi_awqos    = {4{1'b0}};\n          assign cc_mi_awuser   = {C_AXI_AWUSER_WIDTH{1'b0}};\n          assign cc_mi_awvalid  = 1'b0;\n          assign si_cc_awready  = 1'b0;\n    \n          // Write data port\n          assign cc_mi_wid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_wdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign cc_mi_wstrb    = {C_AXI_DATA_WIDTH/8{1'b0}};\n          assign cc_mi_wlast    = 1'b0;\n          assign cc_mi_wuser    = {C_AXI_WUSER_WIDTH{1'b0}};\n          assign cc_mi_wvalid   = 1'b0;\n          assign si_cc_wready   = 1'b0;\n    \n          // Write response port\n          assign si_cc_bid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_bresp    = {2{1'b0}};\n          assign si_cc_buser    = {C_AXI_BUSER_WIDTH{1'b0}};\n          assign si_cc_bvalid   = 1'b0;\n          assign cc_mi_bready   = 1'b0;\n        end\n    \n        ////////////////////////////////////////////////////////////////////////////////\n        // AXI read channels\n        ////////////////////////////////////////////////////////////////////////////////\n    \n        if (C_AXI_SUPPORTS_READ) begin : gen_conv_read_ch\n    \n          // Read Address Port\n          assign s_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH]     = si_cc_araddr   ;\n          assign s_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH]     = si_cc_arprot   ;\n          assign cc_mi_araddr   = m_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH];\n          assign cc_mi_arprot   = m_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH];\n          if (C_AXI_PROTOCOL == P_AXI4) begin : gen_ar_axi4\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen    ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock[0] ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH] = si_cc_arregion ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arregion = m_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_ar_axi3\n            assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH]         = si_cc_arid     ;\n            assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH]       = si_cc_arlen[3:0] ;\n            assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH]     = si_cc_arsize   ;\n            assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH]   = si_cc_arburst  ;\n            assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH]     = si_cc_arlock   ;\n            assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH]   = si_cc_arcache  ;\n            assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH]       = si_cc_arqos    ;\n            assign cc_mi_arid     = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];\n            assign cc_mi_arlen    = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];\n            assign cc_mi_arsize   = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];\n            assign cc_mi_arburst  = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];\n            assign cc_mi_arlock   = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];\n            assign cc_mi_arcache  = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];\n            assign cc_mi_arqos    = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_ar_user\n            assign s_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH]  = si_cc_aruser;\n            assign cc_mi_aruser = m_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_14_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_AR_WIDTH ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE(P_LIGHT_WT)\n          )\n          ar_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( s_axi_aclk     ) ,\n            .S_ARESETN  ( s_axi_aresetn ) ,\n            .S_PAYLOAD ( s_ar_mesg ) ,\n            .S_VALID   ( si_cc_arvalid   ) ,\n            .S_READY   ( si_cc_arready   ) ,\n            .M_ACLK     ( m_axi_aclk     ) ,\n            .M_ARESETN  ( m_axi_aresetn ) ,\n            .M_PAYLOAD ( m_ar_mesg ) ,\n            .M_VALID   ( cc_mi_arvalid   ) ,\n            .M_READY   ( cc_mi_arready   )\n          );\n    \n          // Read Data Port\n          assign m_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH] = cc_mi_rdata; \n          assign m_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH] = cc_mi_rresp; \n          assign si_cc_rdata    = s_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH];\n          assign si_cc_rresp    = s_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH];\n          if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_r_axi\n            assign m_r_mesg[C_RID_RIGHT+:C_RID_WIDTH]     = cc_mi_rid;   \n            assign m_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH] = cc_mi_rlast;\n            assign si_cc_rid      = s_r_mesg[C_RID_RIGHT+:C_RID_WIDTH];\n            assign si_cc_rlast    = s_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH];\n          end\n          if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_r_user\n            assign m_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH] = cc_mi_ruser;\n            assign si_cc_ruser  = s_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH];\n          end\n    \n          axi_clock_converter_v2_1_14_axic_sync_clock_converter #(\n            .C_FAMILY         ( C_FAMILY ) ,\n            .C_PAYLOAD_WIDTH ( C_R_WIDTH ) ,\n            .C_M_ACLK_RATIO   ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,\n            .C_S_ACLK_RATIO   ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,\n            .C_MODE((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)\n          )\n          r_sync_clock_converter (\n            .SAMPLE_CYCLE (sample_cycle),\n            .SAMPLE_CYCLE_EARLY (sample_cycle_early),\n            .S_ACLK     ( m_axi_aclk     ) ,\n            .S_ARESETN  ( m_axi_aresetn ) ,\n            .S_PAYLOAD ( m_r_mesg ) ,\n            .S_VALID   ( cc_mi_rvalid   ) ,\n            .S_READY   ( cc_mi_rready   ) ,\n            .M_ACLK     ( s_axi_aclk     ) ,\n            .M_ARESETN  ( s_axi_aresetn ) ,\n            .M_PAYLOAD ( s_r_mesg ) ,\n            .M_VALID   ( si_cc_rvalid   ) ,\n            .M_READY   ( si_cc_rready   )\n          );\n    \n        end else begin : gen_tieoff_read_ch\n    \n          // Read Address Port\n          assign cc_mi_arid     = {C_AXI_ID_WIDTH{1'b0}};\n          assign cc_mi_araddr   = {C_AXI_ADDR_WIDTH{1'b0}};\n          assign cc_mi_arlen    = {8{1'b0}};\n          assign cc_mi_arsize   = {3{1'b0}};\n          assign cc_mi_arburst  = {2{1'b0}};\n          assign cc_mi_arlock   = {2{1'b0}};\n          assign cc_mi_arcache  = {4{1'b0}};\n          assign cc_mi_arprot   = {3{1'b0}};\n          assign cc_mi_arregion = {4{1'b0}};\n          assign cc_mi_arqos    = {4{1'b0}};\n          assign cc_mi_aruser   = {C_AXI_ARUSER_WIDTH{1'b0}};\n          assign cc_mi_arvalid  = 1'b0;\n          assign si_cc_arready  = 1'b0;\n    \n          // Read data port\n          assign si_cc_rid      = {C_AXI_ID_WIDTH{1'b0}};\n          assign si_cc_rdata    = {C_AXI_DATA_WIDTH{1'b0}};\n          assign si_cc_rresp    = {2{1'b0}};\n          assign si_cc_rlast    = 1'b0;\n          assign si_cc_ruser    = {C_AXI_RUSER_WIDTH{1'b0}};\n          assign si_cc_rvalid   = 1'b0;\n          assign cc_mi_rready   = 1'b0;\n        end\n      end\n    end\n\n  endgenerate\n\nendmodule\n\n\n\n", "num_lines": 2174}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axis to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axi2vector #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,\n  input  wire [3-1:0]                               s_axi_awsize,\n  input  wire [2-1:0]                               s_axi_awburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,\n  input  wire [4-1:0]                               s_axi_awcache,\n  input  wire [3-1:0]                               s_axi_awprot,\n  input  wire [4-1:0]                               s_axi_awregion,\n  input  wire [4-1:0]                               s_axi_awqos,\n  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,\n  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,\n  input  wire                                       s_axi_wlast,\n  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,\n  output wire [2-1:0]                               s_axi_bresp,\n  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,\n\n   // Slave Interface Read Address Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,\n  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,\n  input  wire [3-1:0]                               s_axi_arsize,\n  input  wire [2-1:0]                               s_axi_arburst,\n  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,\n  input  wire [4-1:0]                               s_axi_arcache,\n  input  wire [3-1:0]                               s_axi_arprot,\n  input  wire [4-1:0]                               s_axi_arregion,\n  input  wire [4-1:0]                               s_axi_arqos,\n  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,\n  output wire [2-1:0]                               s_axi_rresp,\n  output wire                                       s_axi_rlast,\n  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,\n\n  // payloads\n  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,\n  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,\n  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,\n  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,\n  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;\nassign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;\n\nassign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;\nassign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;\n\nassign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];\n\nassign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;\nassign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;\n\nassign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];\nassign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;\n    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;\n    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;\n    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;\n    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;\n    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;\n    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;\n\n    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;\n    end\n    else begin : gen_no_axi3_wid_packing\n    end\n\n    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];\n\n    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;\n    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;\n    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;\n    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;\n    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;\n    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;\n    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;\n\n    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];\n    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;\n      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;\n    end \n    else begin : gen_no_region_signals\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;\n      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;\n      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];\n      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;\n      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];\n    end \n    else begin : gen_no_user_signals\n      assign s_axi_buser = 'b0;\n      assign s_axi_ruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign s_axi_bid = 'b0;\n    assign s_axi_buser = 'b0;\n\n    assign s_axi_rlast = 1'b1;\n    assign s_axi_rid   = 'b0;\n    assign s_axi_ruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n// Description: SRL based FIFO for AXIS/AXI Channels.\n//--------------------------------------------------------------------------\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_axic_srl_fifo #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter         C_FAMILY     = \"virtex7\",\n  parameter integer C_PAYLOAD_WIDTH = 1,\n  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                        aclk,    // Clock\n  input  wire                        aresetn,  // Reset\n  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data\n  input  wire                        s_valid, // Input data valid\n  output reg                         s_ready, // Input data ready\n  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data\n  output reg                         m_valid, // Output data valid\n  input  wire                        m_ready  // Output data ready\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n// ceiling logb2\nfunction integer f_clogb2 (input integer size);\n  integer s;\n  begin\n    s = size;\n    s = s - 1;\n    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n          s = s >> 1;\n  end\nendfunction // clogb2\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;\nwire [4-1:0]                        fifo_addr;\nwire                                push;\nwire                                pop ;\nreg                                 areset_r1;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nalways @(posedge aclk) begin \n  areset_r1 <= ~aresetn;\nend\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin\n    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};\n  end\n  else begin\n    fifo_index <= push & ~pop ? fifo_index + 1'b1 :\n                  ~push & pop ? fifo_index - 1'b1 : \n                  fifo_index;\n  end\nend\n\nassign push = s_valid & s_ready;\n\nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    s_ready <= 1'b0;\n  end\n  else begin \n    s_ready <= areset_r1 ? 1'b1 : \n               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :\n               ~push & pop ? 1'b1 : \n               s_ready;\n  end\nend\n\nassign pop = m_valid & m_ready;\n               \nalways @(posedge aclk) begin \n  if (~aresetn) begin \n    m_valid <= 1'b0;\n  end\n  else begin \n    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :\n               push & ~pop ? 1'b1 : \n               m_valid;\n  end\nend\n\ngenerate \n  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr\n    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};\n  end\n  else begin : gen_fifo_addr\n    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];\n  end\nendgenerate\n\n\ngenerate\n  genvar i;\n  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit\n    SRL16E \n    u_srl_fifo(\n      .Q   ( m_payload[i] ) ,\n      .A0  ( fifo_addr[0]     ) ,\n      .A1  ( fifo_addr[1]     ) ,\n      .A2  ( fifo_addr[2]     ) ,\n      .A3  ( fifo_addr[3]     ) ,\n      .CE  ( push              ) ,\n      .CLK ( aclk              ) ,\n      .D   ( s_payload[i] ) \n    );\n  end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n\n\n//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// axi to vector\n//   A generic module to merge all axi signals into one signal called payload.\n//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_infrastructure_v1_1_0_vector2axi #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n  parameter integer C_AXI_PROTOCOL                = 0,\n  parameter integer C_AXI_ID_WIDTH                = 4,\n  parameter integer C_AXI_ADDR_WIDTH              = 32,\n  parameter integer C_AXI_DATA_WIDTH              = 32,\n  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,\n  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,\n  parameter integer C_AXI_AWUSER_WIDTH            = 1,\n  parameter integer C_AXI_WUSER_WIDTH             = 1,\n  parameter integer C_AXI_BUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH            = 1,\n  parameter integer C_AXI_RUSER_WIDTH             = 1,\n  parameter integer C_AWPAYLOAD_WIDTH             = 61,\n  parameter integer C_WPAYLOAD_WIDTH              = 73,\n  parameter integer C_BPAYLOAD_WIDTH              = 6,\n  parameter integer C_ARPAYLOAD_WIDTH             = 61,\n  parameter integer C_RPAYLOAD_WIDTH              = 69\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  // Slave Interface Write Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,\n  output wire [3-1:0]                               m_axi_awsize,\n  output wire [2-1:0]                               m_axi_awburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,\n  output wire [4-1:0]                               m_axi_awcache,\n  output wire [3-1:0]                               m_axi_awprot,\n  output wire [4-1:0]                               m_axi_awregion,\n  output wire [4-1:0]                               m_axi_awqos,\n  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,\n\n  // Slave Interface Write Data Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,\n  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,\n  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,\n  output wire                                       m_axi_wlast,\n  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,\n\n  // Slave Interface Write Response Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,\n  input  wire [2-1:0]                               m_axi_bresp,\n  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,\n\n   // Slave Interface Read Address Ports\n  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,\n  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,\n  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,\n  output wire [3-1:0]                               m_axi_arsize,\n  output wire [2-1:0]                               m_axi_arburst,\n  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,\n  output wire [4-1:0]                               m_axi_arcache,\n  output wire [3-1:0]                               m_axi_arprot,\n  output wire [4-1:0]                               m_axi_arregion,\n  output wire [4-1:0]                               m_axi_arqos,\n  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,\n\n  // Slave Interface Read Data Ports\n  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,\n  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,\n  input  wire [2-1:0]                               m_axi_rresp,\n  input  wire                                       m_axi_rlast,\n  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,\n\n  // payloads\n  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,\n  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,\n  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,\n  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,\n  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n`include \"axi_infrastructure_v1_1_0.vh\"\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI4, AXI4LITE, AXI3 packing\nassign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];\nassign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];\n\nassign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];\nassign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];\n\nassign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;\n\nassign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];\nassign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];\n\nassign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;\nassign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;\n\ngenerate\n  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing\n    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;\n    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];\n    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];\n    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;\n    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;\n    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;\n    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;\n\n    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;\n    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing\n      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;\n    end\n    else begin : gen_no_axi3_wid_packing\n      assign m_axi_wid = 1'b0;\n    end\n\n    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;\n\n    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;\n    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];\n    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];\n    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;\n    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;\n    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;\n    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;\n\n    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;\n    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;\n\n    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals\n      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];\n      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];\n    end \n    else begin : gen_no_region_signals\n      assign m_axi_awregion = 'b0;\n      assign m_axi_arregion = 'b0;\n    end\n    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals\n      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];\n      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;\n      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;\n      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];\n      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;\n    end \n    else begin : gen_no_user_signals\n      assign m_axi_awuser = 'b0;\n      assign m_axi_wuser = 'b0;\n      assign m_axi_aruser = 'b0;\n    end\n  end\n  else begin : gen_axi4lite_packing\n    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_awburst = 'b0;\n    assign m_axi_awcache = 'b0;\n    assign m_axi_awlen = 'b0;\n    assign m_axi_awlock = 'b0;\n    assign m_axi_awid = 'b0;\n    assign m_axi_awqos = 'b0;\n\n    assign m_axi_wlast = 1'b1;\n    assign m_axi_wid = 'b0;\n\n\n    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;\n    assign m_axi_arburst = 'b0;\n    assign m_axi_arcache = 'b0;\n    assign m_axi_arlen = 'b0;\n    assign m_axi_arlock = 'b0;\n    assign m_axi_arid = 'b0;\n    assign m_axi_arqos = 'b0;\n\n    assign m_axi_awregion = 'b0;\n    assign m_axi_arregion = 'b0;\n\n    assign m_axi_awuser = 'b0;\n    assign m_axi_wuser = 'b0;\n    assign m_axi_aruser = 'b0;\n  end\nendgenerate\nendmodule \n\n`default_nettype wire\n\n\n", "num_lines": 671}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule axi_register_slice_v2_1_15_tdm_sample (\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations\n///////////////////////////////////////////////////////////////////////////////\n  input  wire                    slow_clk,\n  input  wire                    fast_clk,\n  output wire                    sample_cycle\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg                slow_clk_div2 = 1'b0;\nreg                posedge_finder_first;\nreg                posedge_finder_second;\nwire               first_edge;\nwire               second_edge;\nreg                sample_cycle_d;\n(* shreg_extract = \"no\" *) reg                sample_cycle_r;\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n    always @(posedge slow_clk) begin \n      slow_clk_div2 <= ~slow_clk_div2;\n    end\n\n    // Find matching rising edges by clocking slow_clk_div2 onto faster clock\n    always @(posedge fast_clk) begin \n      posedge_finder_first <= slow_clk_div2;\n    end\n    always @(posedge fast_clk) begin \n      posedge_finder_second <= ~slow_clk_div2;\n    end\n\n    assign first_edge = slow_clk_div2 & ~posedge_finder_first;\n    assign second_edge = ~slow_clk_div2 & ~posedge_finder_second;\n\n    always @(*) begin \n      sample_cycle_d = first_edge | second_edge;\n    end\n   \n    always @(posedge fast_clk) begin \n      sample_cycle_r <= sample_cycle_d;\n    end\n    \n    assign sample_cycle = sample_cycle_r;\n\nendmodule // tdm_sample\n\n`default_nettype wire\n\n\n// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_srl_rtl #\n  (\n   parameter         C_A_WIDTH = 2          // Address Width (>= 1)\n   )\n  (\n   input  wire                 clk, // Clock\n   input  wire [C_A_WIDTH-1:0] a,   // Address\n   input  wire                 ce,  // Clock Enable\n   input  wire                 d,   // Input Data\n   output wire                 q    // Output Data\n   );\n\n  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;\n  \n    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};\n    always @(posedge clk)\n      if (ce)\n        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};\n    assign q = shift_reg[a];\n\nendmodule  // srl_rtl\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axic_register_slice #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   // C_REG_CONFIG:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => RESERVED (all outputs driven to 0).\n   //   5 => RESERVED (all outputs driven to 0).\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  (* use_clock_enable = \"yes\" *)\n\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 0\n  // Bypass mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000) begin\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 9\n  // Source (SI) interface completely registered\n  //\n  ////////////////////////////////////////////////////////////////////\n      \n    else if (C_REG_CONFIG == 32'h00000009) begin\n      reg [C_DATA_WIDTH-1:0] s_payload_d;\n      wire [C_DATA_WIDTH-1:0] srl_out;\n      reg s_ready_i = 1'b0;\n      reg m_valid_i = 1'b0;\n      reg payld_sel;\n      reg push;\n      reg pop;\n      wire s_handshake_d;\n      (* max_fanout = 66 *) reg s_valid_d;\n      (* max_fanout = 66 *) reg s_ready_d = 1'b0;\n      (* max_fanout = 66 *) reg s_ready_reg = 1'b0;\n      (* max_fanout = 66 *) reg [2:0] fifoaddr = 3'b110;\n      \n      reg areset_d = 1'b0;\n      always @(posedge ACLK) begin\n        areset_d <= ARESET;\n      end\n      \n      assign s_handshake_d = s_valid_d & s_ready_d;\n\n      always @ * begin\n        case (fifoaddr)\n          3'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready\n            s_ready_i = 1'b1;\n            payld_sel = 1'b0;\n            pop = 1'b0;\n            case ({s_handshake_d, M_READY}) \n              2'b00, 2'b01: begin  // Idle\n                m_valid_i = 1'b0;\n                push = 1'b0;\n              end\n              2'b10: begin  // Payload received\n                m_valid_i = 1'b1;\n                push = 1'b1;\n              end\n              2'b11: begin  // Payload received and read out combinatorially\n                m_valid_i = 1'b1;\n                push = 1'b0;\n              end\n            endcase\n          end\n\n          3'b000: begin  // 1 payload item in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push\n                s_ready_i = 1'b0;  // Doesn't de-assert on SI until next cycle\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b1;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b001: begin  // 2 payload items in SRL\n            m_valid_i = 1'b1;\n            payld_sel = 1'b1;\n            case ({s_handshake_d, M_READY}) \n              2'b00: begin  // Idle\n                s_ready_i = 1'b0;\n                push = 1'b0;\n                pop = 1'b0;\n              end\n              2'b01: begin  // Pop\n                s_ready_i = 1'b1;\n                push = 1'b0;\n                pop = 1'b1;\n              end\n              2'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b0;\n              end\n              2'b11: begin  // Push and Pop\n                s_ready_i = 1'b0;\n                push = 1'b1;\n                pop = 1'b1;\n              end\n            endcase\n          end\n\n          3'b010: begin  // 3 payload items in SRL\n            m_valid_i = 1'b1;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b1;\n            push = 1'b0;\n            if (M_READY) begin  // Handshake cannot complete on SI\n              pop = 1'b1;\n            end else begin\n              pop = 1'b0;\n            end\n          end\n\n          default: begin  // RESET state (fifoaddr = 3'b110)\n            m_valid_i = 1'b0;\n            s_ready_i = 1'b0;\n            payld_sel = 1'b0;\n            push = 1'b1;  // Advance to Empty state\n            pop = 1'b0;\n          end  // RESET\n        endcase\n      end\n\n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifoaddr <= 3'b110;\n          s_ready_reg <= 1'b0;\n          s_ready_d <= 1'b0;\n        end else begin\n          s_ready_reg <= s_ready_i;\n          s_ready_d <= s_ready_reg;\n          if (push & ~pop) begin\n            fifoaddr <= fifoaddr + 1;\n          end else if (~push & pop) begin\n            fifoaddr <= fifoaddr - 1;\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        s_valid_d <= S_VALID;\n        s_payload_d <= S_PAYLOAD_DATA;\n      end\n\n      assign S_READY = s_ready_reg;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;\n\n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n      genvar i;\n      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls\n        axi_register_slice_v2_1_15_srl_rtl #\n          (\n           .C_A_WIDTH (2)\n          )\n          srl_nx1\n          (\n           .clk (ACLK),\n           .a   (fifoaddr[1:0]),\n           .ce  (push),\n           .d   (s_payload_d[i]),\n           .q   (srl_out[i])\n          );\n      end      \n    end \n        \n        \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 1 (or 8)\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg [C_DATA_WIDTH-1:0] skid_buffer;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else begin\n          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);\n        end\n        \n        if (M_READY | ~m_valid_i) begin\n          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;\n        end\n        \n        if (s_ready_i) begin\n          skid_buffer <= S_PAYLOAD_DATA;\n        end\n      end\n\n    end // if (C_REG_CONFIG == 1)\n    \n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 2\n  // Only FWD mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000002)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      wire                   s_ready_i; //local signal of output\n      reg                    m_valid_i = 1'b0; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg aresetn_d = 1'b0; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 1'b0;\n        end else begin\n          aresetn_d <= ~ARESET;\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data;\n      \n      // M_Valid set to high when we have a completed transfer on slave side\n      // Is removed on a M_READY except if we have a new transfer on the slave side\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d) \n          m_valid_i <= 1'b0;\n        else\n          if (S_VALID) // Always set m_valid_i when slave side is valid\n            m_valid_i <= 1'b1;\n          else\n            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n              m_valid_i <= 1'b0;\n      end // always @ (posedge ACLK)\n      \n      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;\n\n    end // if (C_REG_CONFIG == 2)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 3\n  // Only REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000003)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data;\n      reg                    s_ready_i = 1'b0; //local signal of output\n      reg                    has_valid_storage_i;\n      reg                    has_valid_storage;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // Save payload data whenever we have a transaction on the slave side\n      always @(posedge ACLK) \n      begin\n        if (S_VALID & s_ready_i)\n          storage_data <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n      // Need to determine when we need to save a payload\n      // Need a combinatorial signals since it will also effect S_READY\n      always @ *\n      begin\n        // Set the value if we have a slave transaction but master side is not ready\n        if (S_VALID & s_ready_i & ~M_READY)\n          has_valid_storage_i = 1'b1;\n        \n        // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n        // transaction \n        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n          has_valid_storage_i = 1'b0;\n        else\n          has_valid_storage_i = has_valid_storage;\n      end // always @ *\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          has_valid_storage <= 1'b0;\n        else\n          has_valid_storage <= has_valid_storage_i;\n      end\n\n      // S_READY is either clocked M_READY or that we have room in local storage\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          s_ready_i <= 1'b0;\n        else\n          s_ready_i <= M_READY | ~has_valid_storage_i;\n      end\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n\n      // M_READY is either combinatorial S_READY or that we have valid data in local storage\n      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];\n      \n    end // if (C_REG_CONFIG == 3)\n    \n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n    begin\n// synthesis translate_off\n      initial begin  \n        $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n      end\n// synthesis translate_on\n      assign M_PAYLOAD_DATA = 0;\n      assign M_VALID        = 1'b0;\n      assign S_READY        = 1'b0;    \n    end  \n\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 6\n  // INPUTS mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000006)\n    begin\n      localparam [1:0] \n        ZERO = 2'b00,\n        ONE  = 2'b01,\n        TWO  = 2'b11;\n      reg [1:0] state = ZERO;\n      reg [1:0] next_state;\n\n      reg [C_DATA_WIDTH-1:0] storage_data1;\n      reg [C_DATA_WIDTH-1:0] storage_data2;\n      reg                    s_valid_d = 1'b0;\n      reg                    s_ready_d = 1'b0;\n      reg                    m_ready_d = 1'b0;\n      reg                    m_valid_d = 1'b0;\n      reg                    load_s2;\n      reg                    sel_s2;\n      wire                   new_access;\n      wire                   access_done;\n      wire                   s_ready_i; //local signal of output\n      reg                    s_ready_ii;\n      reg                    m_valid_i; //local signal of output\n      \n      reg [1:0] aresetn_d = 2'b00; // Reset delay register\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign s_ready_i = s_ready_ii & aresetn_d[1];\n\n      // Registrate input control signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) begin          \n          s_valid_d <= 1'b0;\n          s_ready_d <= 1'b0;\n          m_ready_d <= 1'b0;\n        end else begin\n          s_valid_d <= S_VALID;\n          s_ready_d <= s_ready_i;\n          m_ready_d <= M_READY;\n        end\n      end // always @ (posedge ACLK)\n\n      // Load storage1 with slave side payload data when slave side ready is high\n      always @(posedge ACLK) \n      begin\n        if (s_ready_i)\n          storage_data1 <= S_PAYLOAD_DATA;          \n      end\n\n      // Load storage2 with storage data \n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= storage_data1;\n      end\n\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          m_valid_d <= 1'b0;\n        else \n          m_valid_d <= m_valid_i;\n      end\n\n      // Local help signals\n      assign new_access  = s_ready_d & s_valid_d;\n      assign access_done = m_ready_d & m_valid_d;\n\n\n      // State Machine for handling output signals\n      always @*\n      begin\n        next_state = state; // Stay in the same state unless we need to move to another state\n        load_s2   = 0;\n        sel_s2    = 0;\n        m_valid_i = 0;\n        s_ready_ii = 0;\n        case (state)\n            // No transaction stored locally\n            ZERO: begin\n              load_s2   = 0;\n              sel_s2    = 0;\n              m_valid_i = 0;\n              s_ready_ii = 1;\n              if (new_access) begin\n                next_state = ONE; // Got one so move to ONE\n                load_s2   = 1;\n                m_valid_i = 0;\n              end\n              else begin\n                next_state = next_state;\n                load_s2   = load_s2;\n                m_valid_i = m_valid_i;\n              end\n\n            end // case: ZERO\n\n            // One transaction stored locally\n            ONE: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 1;\n              if (~new_access & access_done) begin\n                next_state = ZERO; // Read out one so move to ZERO\n                m_valid_i = 0;                      \n              end\n              else if (new_access & ~access_done) begin\n                next_state = TWO;  // Got another one so move to TWO\n                s_ready_ii = 0;\n              end\n              else if (new_access & access_done) begin\n                load_s2   = 1;\n                sel_s2    = 0;\n              end\n              else begin\n                load_s2   = load_s2;\n                sel_s2    = sel_s2;\n              end\n\n\n            end // case: ONE\n\n            // TWO transaction stored locally\n            TWO: begin\n              load_s2   = 0;\n              sel_s2    = 1;\n              m_valid_i = 1;\n              s_ready_ii = 0;\n              if (access_done) begin \n                next_state = ONE; // Read out one so move to ONE\n                s_ready_ii  = 1;\n                load_s2    = 1;\n                sel_s2     = 0;\n              end\n              else begin\n                next_state = next_state;\n                s_ready_ii  = s_ready_ii;\n                load_s2    = load_s2;\n                sel_s2     = sel_s2;\n              end\n            end // case: TWO\n        endcase // case (state)\n      end // always @ *\n\n\n      // State Machine for handling output signals\n      always @(posedge ACLK) \n      begin\n        if (~aresetn_d[0]) \n          state <= ZERO;\n        else\n          state <= next_state; // Stay in the same state unless we need to move to another state\n      end\n      \n      // Master Payload mux\n      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n    end // if (C_REG_CONFIG == 6)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // C_REG_CONFIG = 7\n  // Light-weight mode.\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000007) begin\n      reg [C_DATA_WIDTH-1:0] m_payload_i;\n      reg                    s_ready_i = 1'b0; \n      reg                    m_valid_i = 1'b0;\n\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n      assign M_PAYLOAD_DATA = m_payload_i;\n\n      reg [1:0] aresetn_d = 2'b00; // Reset delay shifter\n      always @(posedge ACLK) begin\n        if (ARESET) begin\n          aresetn_d <= 2'b00;\n        end else begin\n          aresetn_d <= {aresetn_d[0], ~ARESET};\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (~aresetn_d[0]) begin\n          s_ready_i <= 1'b0;\n        end else if (~aresetn_d[1]) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;\n        end\n        \n        if (~aresetn_d[1]) begin\n          m_valid_i <= 1'b0;\n        end else begin\n          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;\n        end\n        \n        if (~m_valid_i) begin\n          m_payload_i <= S_PAYLOAD_DATA;\n        end\n      end\n      \n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // axic_register_slice\n\n\n// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axic_register_slice_slr\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_multi_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_CHANNEL = 0,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER = 0,\n   parameter integer C_PIPELINES_SLAVE = 0,\n   parameter integer C_PIPELINES_MIDDLE = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n   \n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  localparam integer P_REG_CONFIG = 15;\n  localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2;\n  localparam integer P_RESP_MIDDLE_LATENCY = C_PIPELINES_SLAVE + 2;\n  localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS==2) ? (C_PIPELINES_MIDDLE+2) : 0);\n  localparam integer P_RESP_DEST_LATENCY = C_PIPELINES_SLAVE + 2 + ((C_NUM_SLR_CROSSINGS==2) ? (C_PIPELINES_MIDDLE+2) : 0);\n\n  generate\n  \n  if (C_NUM_SLR_CROSSINGS==0) begin : single_slr\n    \n    axi_register_slice_v2_1_15_single_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n      .C_PIPELINES  (C_PIPELINES_MASTER) \n    )\n    slr_master (\n      // System Signals\n      .ACLK(ACLK),\n      .ARESET(ARESET),\n\n      // Slave side\n      .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n      .S_VALID(S_VALID),\n      .S_READY(S_READY),\n\n      // Master side\n      .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n      .M_VALID(M_VALID),\n      .M_READY(M_READY)\n    );\n    \n  end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n    end\n    \n  end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr\n    \n    wire [C_DATA_WIDTH-1:0] src_payload;\n    wire src_handshake;\n    wire src_ready;\n    wire [C_DATA_WIDTH-1:0] dest_payload;\n    wire dest_handshake;\n    wire dest_ready;\n        \n    if (C_CHANNEL==P_FORWARD) begin : fwd\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_master (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK           ( ACLK ) ,\n        .ARESET         ( ARESET ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE),\n        .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY)\n      )\n      slr_slave (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n      \n    end else begin : resp\n      axi_register_slice_v2_1_15_source_region_slr # (\n        .C_FAMILY     ( C_FAMILY ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_SLAVE) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) \n      )\n      slr_slave (\n        // System Signals\n        .ACLK(ACLK),\n        .ARESET(ARESET),\n\n        // Slave side\n        .S_PAYLOAD_DATA(S_PAYLOAD_DATA),\n        .S_VALID(S_VALID),\n        .S_READY(S_READY),\n\n        // Master side\n        .laguna_m_payload   ( src_payload ) , \n        .laguna_m_handshake ( src_handshake   ) ,\n        .laguna_m_ready     ( src_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_middle_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_PIPELINES  (C_PIPELINES_MIDDLE),\n        .C_SOURCE_LATENCY (P_RESP_MIDDLE_LATENCY)\n      )\n      slr_middle (\n        .ACLK           ( ACLK ) ,\n        .ARESET         ( ARESET ) ,\n        .laguna_s_payload   ( src_payload ) ,\n        .laguna_s_handshake ( src_handshake   ) ,\n        .laguna_s_ready     ( src_ready   ) ,\n        .laguna_m_payload   ( dest_payload ) , \n        .laguna_m_handshake ( dest_handshake   ) ,\n        .laguna_m_ready     ( dest_ready   )\n      );\n      \n      axi_register_slice_v2_1_15_dest_region_slr #(\n        .C_FAMILY     ( C_FAMILY         ) ,\n        .C_REG_CONFIG ( P_REG_CONFIG ) ,\n        .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n        .C_SLR_WIDTH  ( C_DATA_WIDTH ),\n        .C_PIPELINES  (C_PIPELINES_MASTER),\n        .C_SOURCE_LATENCY (P_RESP_DEST_LATENCY)\n      )\n      slr_master (\n        .ACLK           ( ACLK            ) ,\n        .ARESET         ( ARESET        ) ,\n        .laguna_s_payload   ( dest_payload ) ,\n        .laguna_s_handshake ( dest_handshake   ) ,\n        .laguna_s_ready     ( dest_ready   ) ,\n        .M_PAYLOAD_DATA(M_PAYLOAD_DATA),\n        .M_VALID(M_VALID),\n        .M_READY(M_READY)\n      );\n    end\n  end\n  \nendgenerate\nendmodule  // multi_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_middle_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n   \n  localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (1) begin : common\n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    (* dont_touch=\"true\" *)  reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_handshake_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg [((C_PIPELINES>0)?(C_PIPELINES-1):0):0] ready_d = 0;\n    wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+2)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign laguna_s_ready = laguna_s_ready_i;\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0; \n        laguna_m_ready_d <= 1'b0; \n        ready_d <= 0;\n      end else begin\n        laguna_m_ready_d <= laguna_m_ready; \n        if (C_PIPELINES==0) begin\n          laguna_s_ready_i <= laguna_m_ready_d;\n        end else if (C_PIPELINES==1) begin\n          ready_d <= laguna_m_ready_d; \n          laguna_s_ready_i <= ready_d;\n        end else begin\n          ready_d <= {ready_d, laguna_m_ready_d}; \n          laguna_s_ready_i <= ready_d[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n        end\n      end\n    end\n\n    for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_d : payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, laguna_m_ready_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{laguna_m_ready_d}};\n            payload_valid_enable <= laguna_m_ready_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==0) begin\n                laguna_s_payload_d[i] <= laguna_s_payload[i];\n              end else if (p==C_PIPELINES+1) begin\n                laguna_m_payload_i[i] <= payload_i[C_PIPELINES*C_DATA_WIDTH + i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          if (areset_d) begin\n            laguna_s_handshake_d <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_s_handshake_d <= laguna_s_handshake;\n          end\n        end else if (p==C_PIPELINES+1) begin\n          if (areset_d) begin\n            laguna_m_handshake_i <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_m_handshake_i <= handshake_i[C_PIPELINES];\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n  end // gen_slr\n  endgenerate\nendmodule  // middle_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_source_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_SLR_WIDTH-1:0] laguna_m_payload,\n   output wire laguna_m_handshake,\n   input  wire laguna_m_ready\n   );\n\n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (C_REG_CONFIG == 13) begin : tdm\n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [P_EVEN_WIDTH-1:0] payload_d1;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_m_payload_i;\n    (* dont_touch=\"true\" *)    reg laguna_m_handshake_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg laguna_m_ready_d = 1'b0;\n    wire sample_cycle;\n    integer i;\n\n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = laguna_m_ready_d;\n        \n    always @(posedge ACLK) begin\n      if (laguna_m_ready_d) begin\n        payload_d1 <= S_PAYLOAD_DATA;  // ACLK cycle 1\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin  \n        if (laguna_m_ready_d) begin\n          if (~sample_cycle) begin  // First (high) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i+1];  // Mux odd bits\n          end else begin  // Second (low) phase of ACLK cycle 2\n            laguna_m_payload_i[i] <= payload_d1[2*i];  // Mux even bits\n          end\n        end\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_handshake_i <= 1'b0;\n        laguna_m_ready_d <= 1'b0;\n      end else begin\n        if (laguna_m_ready_d) begin\n          laguna_m_handshake_i <= S_VALID;\n        end\n        laguna_m_ready_d <= laguna_m_ready;  // Half-cycle setup from dest_region.laguna_s_ready_i\n      end\n    end\n\n    axi_register_slice_v2_1_15_tdm_sample tdm_sample_inst (\n      .slow_clk     (ACLK),\n      .fast_clk     (ACLK2X),\n      .sample_cycle (sample_cycle)\n    );\n    \n  end else begin : common\n\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n    localparam integer P_PIPE_LATENCY = (C_PIPELINES>0) ? C_PIPELINES : 1;\n     \n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i;\n    (* dont_touch=\"true\" *)  reg laguna_m_handshake_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_m_ready_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] ready_d = 0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    genvar p;\n    \n    assign laguna_m_payload = laguna_m_payload_i;\n    assign laguna_m_handshake = laguna_m_handshake_i;\n    assign S_READY = (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_LATENCY-1];\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_m_ready_d <= 1'b0; \n        ready_d <= 0;\n      end else begin\n        laguna_m_ready_d <= laguna_m_ready; \n        if (C_PIPELINES>0) begin\n          ready_d <= {ready_d, laguna_m_ready_d}; \n        end\n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, laguna_m_ready_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{laguna_m_ready_d}};\n            payload_valid_enable <= laguna_m_ready_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        if (C_PIPELINES==0) begin\n          if (laguna_m_ready_d) begin\n            laguna_m_payload_i <= S_PAYLOAD_DATA;\n          end\n        end else begin\n          for (r=0; r<P_REPLICATION; r=r+1) begin\n            if (payload_data_enable[r]) begin\n              for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n                if (p==C_PIPELINES) begin\n                  laguna_m_payload_i[i] <= payload_i[((C_PIPELINES>0)?(C_PIPELINES-1):0)*C_DATA_WIDTH + i];\n                end else if (p==0) begin\n                  payload_data[i] <= S_PAYLOAD_DATA[i];\n                end else begin\n                  payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n                end\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (C_PIPELINES==0) begin\n          if (areset_d) begin\n            laguna_m_handshake_i <= 1'b0;\n          end else if (laguna_m_ready_d) begin\n            laguna_m_handshake_i <= S_VALID;\n          end\n        end else begin\n          if (p==C_PIPELINES) begin\n            if (areset_d) begin\n              laguna_m_handshake_i <= 1'b0;\n            end else if (payload_valid_enable) begin\n              laguna_m_handshake_i <= handshake_i[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n            end\n          end else if (p==0) begin\n            if (areset_d) begin\n              payload_valid <= 1'b0;\n            end else if (payload_valid_enable) begin\n              payload_valid <= S_VALID;\n            end\n          end else begin\n            if (areset_d) begin\n              payload_valid <= 1'b0;\n            end else if (payload_valid_enable) begin\n              payload_valid <= handshake_i[((p>0)?(p-1):0)];\n            end\n          end\n        end\n      end\n    end\n  end // gen_slr\n  endgenerate\nendmodule  // source_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_15_dest_region_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_REG_CONFIG = 12,\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_SLR_WIDTH = 32,\n   parameter integer C_PIPELINES = 0,\n   parameter integer C_SOURCE_LATENCY = 1\n      // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr .\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ACLK2X,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_SLR_WIDTH-1:0] laguna_s_payload,\n   input  wire laguna_s_handshake,\n   output wire laguna_s_ready,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (C_REG_CONFIG == 13) begin : tdm\n    localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH;\n    \n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  laguna_s_payload_d;\n    (* shreg_extract = \"no\" *) reg [C_SLR_WIDTH-1:0]  payload_tdm_d4;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n    (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n    (* shreg_extract = \"no\" *) reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)    reg laguna_s_ready_i = 1'b0;\n    (* shreg_extract = \"no\" *) reg s_ready_d2 = 1'b0;\n    reg [P_EVEN_WIDTH-1:0] payload_demux;\n    reg m_valid_r = 1'b0;\n    wire push;\n    wire pop;\n    reg [1:0] fifo_cnt = 2'h0;\n    integer i;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign M_VALID = m_valid_r;\n    assign M_PAYLOAD_DATA = fifo_out;  // Registered outputs\n    assign pop = M_READY & m_valid_r;\n    assign push = laguna_s_handshake_d & s_ready_d2;      \n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_handshake_d <= 1'b0;\n      end else if (s_ready_d2) begin\n        laguna_s_handshake_d <= laguna_s_handshake;\n      end\n    end\n\n    always @(posedge ACLK2X) begin\n      if (s_ready_d2) begin\n        payload_tdm_d4 <= laguna_s_payload_d;\n        laguna_s_payload_d <= laguna_s_payload;\n      end\n    end\n    \n    always @ * begin\n      for (i=0;i<C_SLR_WIDTH;i=i+1) begin\n        payload_demux[2*i+1] = payload_tdm_d4[i];       // Odd bits captured during second (low) phase of ACLK cycle 2\n        payload_demux[2*i] = laguna_s_payload_d[i];  // Even bits captured during first (high) phase of ACLK cycle 3\n          // Complete payload_demux signal is stable during second (low) phase of ACLK cycle 3 (gets clobbered after each ACLK active edge)\n      end\n    end\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        fifo_cnt <= 2'h0;\n        m_valid_r <=  1'b0;\n        s_ready_d2 <= 1'b0;\n      end else begin\n        s_ready_d2 <= laguna_s_ready_i;  // Half-cycle setup from laguna_s_ready_i\n        if (push & ~pop) begin\n          fifo_cnt <= fifo_cnt + 2'h1;\n          m_valid_r <=  1'b1;\n        end else if (~push & pop) begin\n          fifo_cnt <= fifo_cnt - 2'h1;\n          m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n        end\n      end\n    end\n\n    always @(negedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0;\n      end else begin\n        laguna_s_ready_i <= M_READY | ~m_valid_r;  // Half-cycle setup\n      end\n    end\n\n    always @(posedge ACLK) begin\n      case (fifo_cnt)\n        2'h0: begin  // EMPTY\n          fifo_out <= payload_demux;\n        end\n        \n        2'h1: begin\n          fifo_out_n1 <= payload_demux;\n          if (pop) begin\n            fifo_out <= payload_demux;\n          end\n        end\n        \n        default: begin  // fifo_cnt == 2\n          if (pop) begin\n            fifo_out <= fifo_out_n1;\n            fifo_out_n1 <= payload_demux;\n          end\n        end\n      endcase\n    end\n\n  end else begin : common\n\n    localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES;\n    localparam integer P_FANOUT = 256;\n    localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n     \n    (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d;\n    (* dont_touch=\"true\" *)  reg laguna_s_handshake_d = 1'b0;\n    (* dont_touch=\"true\" *)  reg laguna_s_ready_i = 1'b0;\n    (* dont_touch=\"true\" *)  reg [((C_PIPELINES>0)?(C_PIPELINES-1):0):0] ready_d = 0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] push_enable_d = 0;\n    (* dont_touch=\"true\" *)  reg root_enable_d = 1'b0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire push;\n    wire pop;\n    wire push_enable;\n    genvar p;\n    \n    assign laguna_s_ready = laguna_s_ready_i;\n    assign pop = M_READY & m_valid_i;\n    assign push_enable = push_enable_d[P_PIPE_LATENCY-1];\n    assign push = handshake_i[C_PIPELINES] & push_enable;      \n    assign M_VALID = m_valid_i;\n\n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        laguna_s_ready_i <= 1'b0; \n        ready_d <= 0;\n        push_enable_d <= 0;\n        root_enable_d <= 1'b0; \n      end else begin\n        push_enable_d <= {push_enable_d, root_enable_d};\n        root_enable_d <= M_READY | ~m_valid_i;\n        if (C_PIPELINES==0) begin\n          laguna_s_ready_i <= root_enable_d;\n        end else if (C_PIPELINES==1) begin\n          ready_d <= root_enable_d; \n          laguna_s_ready_i <= ready_d;\n        end else begin\n          ready_d <= {ready_d, root_enable_d}; \n          laguna_s_ready_i <= ready_d[((C_PIPELINES>0)?(C_PIPELINES-1):0)];\n        end\n      end\n    end\n    \n    for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data;\n      assign handshake_i[p] = (p==0) ? laguna_s_handshake_d : payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, root_enable_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{root_enable_d}};\n            payload_valid_enable <= root_enable_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==0) begin\n                laguna_s_payload_d[i] <= laguna_s_payload[i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==0) begin\n          if (areset_d) begin\n            laguna_s_handshake_d <= 1'b0;\n          end else if (payload_valid_enable) begin\n            laguna_s_handshake_d <= laguna_s_handshake;\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n    if ((C_PIPELINES==0) && (C_SOURCE_LATENCY<=1)) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES+C_SOURCE_LATENCY>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        ); \n  \n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // dest_region_slr\n\n`timescale 1ps/1ps\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\nmodule axi_register_slice_v2_1_15_single_slr #\n  (\n   parameter C_FAMILY     = \"virtex6\",\n   parameter integer C_DATA_WIDTH = 32,\n   parameter integer C_PIPELINES = 0\n   )\n  (\n   // System Signals\n   input wire ACLK,\n   input wire ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n   input  wire S_VALID,\n   output wire S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n   output wire M_VALID,\n   input  wire M_READY\n   );\n\n  generate\n\n  localparam integer P_PIPE_LATENCY = (C_PIPELINES>0) ? C_PIPELINES : 1;\n  localparam integer P_FANOUT = 256;\n  localparam integer P_REPLICATION = (C_DATA_WIDTH>P_FANOUT) ? (C_DATA_WIDTH/P_FANOUT + 1) : 1;\n   \n  (* dont_touch=\"true\" *) reg areset_d = 1'b0;\n  always @(posedge ACLK) begin\n    areset_d <= ARESET;\n  end\n  \n  if (1) begin : common\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] ready_d = 0;\n    (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0] push_enable_d = 0;\n    (* dont_touch=\"true\" *)  reg root_enable_d = 1'b0;\n    wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i;\n    wire [(C_PIPELINES+1)-1:0] handshake_i;\n    wire m_valid_i;\n    wire s_ready_i;\n    wire push;\n    wire pop;\n    wire push_enable;\n    genvar p;\n    \n    assign pop = M_READY & m_valid_i;\n    assign push_enable = (C_PIPELINES == 0) ? root_enable_d : push_enable_d[P_PIPE_LATENCY-1];\n    assign push = handshake_i[C_PIPELINES] & push_enable;      \n    assign M_VALID = m_valid_i;\n    assign s_ready_i = (C_PIPELINES == 0) ? root_enable_d : ready_d[P_PIPE_LATENCY-1];\n    assign S_READY = s_ready_i;\n        \n    always @(posedge ACLK) begin\n      if (areset_d) begin\n        ready_d <= 0;\n        push_enable_d <= 0;\n        root_enable_d <= 1'b0;\n      end else begin\n        root_enable_d <= M_READY | ~m_valid_i;\n        if (C_PIPELINES > 0) begin\n          ready_d <= {ready_d, root_enable_d}; \n          push_enable_d <= {push_enable_d, root_enable_d};\n        end\n      end\n    end\n    \n    assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA;\n    assign handshake_i[0] = S_VALID;\n    \n    for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe\n      (* dont_touch=\"true\" *)  reg [P_PIPE_LATENCY-1:0]  delay_chain = 0;\n      (* dont_touch=\"true\" *)  reg [P_REPLICATION-1:0] payload_data_enable = 0;\n      (* dont_touch=\"true\" *)  reg payload_valid_enable = 1'b0;\n      (* shreg_extract=\"no\" *) reg [C_DATA_WIDTH-1:0]  payload_data;\n      (* dont_touch=\"true\" *)  reg payload_valid = 1'b0;\n      integer r;\n      integer i;\n      \n      assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data;\n      assign handshake_i[p] = payload_valid;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          delay_chain <= 0;\n          payload_data_enable <= 0;\n          payload_valid_enable <= 1'b0;\n        end else begin\n          delay_chain <= {delay_chain, root_enable_d};\n          if (P_PIPE_LATENCY<=1) begin\n            payload_data_enable <= {P_REPLICATION{root_enable_d}};\n            payload_valid_enable <= root_enable_d;\n          end else begin\n            payload_data_enable <= {P_REPLICATION{delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)]}};\n            payload_valid_enable <= delay_chain[(P_PIPE_LATENCY<2)?0:(P_PIPE_LATENCY-2)];\n          end\n        end\n      end\n      \n      always @(posedge ACLK) begin\n        for (r=0; r<P_REPLICATION; r=r+1) begin\n          if (payload_data_enable[r]) begin\n            for (i=r*P_FANOUT; (i<(r+1)*P_FANOUT)&&(i<C_DATA_WIDTH); i=i+1) begin\n              if (p==1) begin\n                payload_data[i] <= S_PAYLOAD_DATA[i];\n              end else begin\n                payload_data[i] <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH + i];\n              end\n            end\n          end\n        end\n      end\n        \n      always @(posedge ACLK) begin\n        if (p==1) begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= S_VALID;\n          end\n        end else begin\n          if (areset_d) begin\n            payload_valid <= 1'b0;\n          end else if (payload_valid_enable) begin\n            payload_valid <= handshake_i[((p>0)?(p-1):0)];\n          end\n        end\n      end\n    end\n    \n    if (C_PIPELINES<=1) begin : ff_fifo\n\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1;\n      (* shreg_extract = \"no\" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2;\n      reg [1:0] fifo_cnt = 2'h0;\n      reg m_valid_r = 1'b0;\n      \n      assign M_PAYLOAD_DATA = fifo_out; \n      assign m_valid_i = m_valid_r;\n      \n      always @(posedge ACLK) begin\n        if (areset_d) begin\n          fifo_cnt <= 2'h0;\n          m_valid_r <=  1'b0;\n        end else begin\n          if (push & ~pop) begin\n            fifo_cnt <= fifo_cnt + 2'h1;\n            m_valid_r <=  1'b1;\n          end else if (~push & pop) begin\n            fifo_cnt <= fifo_cnt - 2'h1;\n            m_valid_r <= fifo_cnt[1];  // fifo_cnt >= 2\n          end\n        end\n      end\n\n      always @(posedge ACLK) begin\n        case (fifo_cnt)\n          2'h0: begin  // EMPTY\n            fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n          end\n          \n          2'h1: begin\n            fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          2'h2: begin\n            fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n          \n          default: begin  // fifo_cnt == 3\n            if (pop) begin\n              fifo_out <= fifo_out_n1;\n              fifo_out_n1 <= fifo_out_n2;\n              fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH];\n            end\n          end\n        endcase\n      end\n    \n    end else begin : srl_fifo\n    \n      axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n        (\n         .C_FIFO_WIDTH (C_DATA_WIDTH), \n         .C_FIFO_SIZE  ((C_PIPELINES>12) ? 5 : 4)  \n        )\n        srl_fifo_0\n        (\n         .aclk    (ACLK),    \n         .areset  (areset_d),  \n         .s_mesg  (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]),  \n         .s_valid (push), \n         .m_mesg  (M_PAYLOAD_DATA),  \n         .m_valid (m_valid_i), \n         .m_ready (pop)\n        );\n\n    end // gen_fifo\n  end // gen_slr\n  endgenerate\nendmodule  // single_slr\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axic_reg_srl_fifo #\n  // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full\n  (\n   parameter integer C_FIFO_WIDTH  = 1,      // Width of s_mesg/m_mesg.\n   parameter integer C_FIFO_SIZE = 5        // Depth of FIFO is 2**C_FIFO_SIZE.  \n   )\n  (\n   input  wire                        aclk,    // Clock\n   input  wire                        areset,  // Reset\n   input  wire [C_FIFO_WIDTH-1:0]     s_mesg,  // Input data\n   input  wire                        s_valid, // Input data valid\n   output wire [C_FIFO_WIDTH-1:0]     m_mesg,  // Output data\n   output wire                        m_valid, // Output data valid\n   input  wire                        m_ready  // Output data ready\n   );\n  \n  genvar i;\n\n  generate\n  \n    localparam integer P_FIFO_DEPTH            = 2**C_FIFO_SIZE;\n    localparam [C_FIFO_SIZE-1:0] P_EMPTY       = {C_FIFO_SIZE{1'b1}};\n    localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}};\n    \n    localparam M_VALID_0   = 1'b0;\n    localparam M_VALID_1   = 1'b1;\n    localparam SRL_VALID_0 = 1'b0;\n    localparam SRL_VALID_1 = 1'b1;\n    localparam S_VALID_0   = 1'b0;\n    localparam S_VALID_1   = 1'b1;\n    localparam M_READY_0   = 1'b0;\n    localparam M_READY_1   = 1'b1;\n    \n    localparam [1:0] K_EMPTY   = {SRL_VALID_0, M_VALID_0};\n    localparam [1:0] K_HAS1    = {SRL_VALID_0, M_VALID_1};\n    localparam [1:0] K_MIN2    = {SRL_VALID_1, M_VALID_1};\n\n    reg  push;       // SRL push\n    reg  pop;        // SRL pop\n    wire [C_FIFO_WIDTH-1:0] srl_reg;\n    reg [C_FIFO_SIZE-1:0]  fifoaddr = P_EMPTY;\n    \n    (* fsm_encoding = \"none\" *) reg [1:0] state = K_EMPTY;  // State vector register\n    reg [1:0] next;           // Next state value\n    \n    reg  load_mesg;  // Load output register\n    reg  srl2mesg;   // Output reg loads from SRL (else from s_mesg)\n    reg  [C_FIFO_WIDTH-1:0] mesg_reg;  // No initial state\n    \n    assign m_valid = state[0];  // Drive m_valid from state vector\n    assign m_mesg  = mesg_reg;\n\n    always @ * begin\n      next = state;  // Default: hold state unless re-assigned\n      load_mesg = 1'b1;\n      srl2mesg = 1'b0;\n      push = 1'b0;\n      pop = 1'b0;\n      case (state)\n        K_EMPTY: begin  // FIFO Empty; pre-assert s_ready\n          load_mesg = s_valid;\n          srl2mesg = 1'b0;\n          push = 1'b0;\n          pop = 1'b0;\n          if (s_valid) begin\n            next = K_HAS1;\n          end\n        end  // EMPTY\n        \n        K_HAS1: begin  // FIFO contains 1 item in the output register (SRL empty)\n          srl2mesg = 1'b0;\n          pop = 1'b0;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a 2nd item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop to empty\n              next = K_EMPTY;\n              load_mesg = 1'b1;  // Inconsequential\n              push = 1'b0;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping; replace contents of output reg\n              next = K_HAS1;\n              load_mesg = 1'b1;\n              push = 1'b0;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_HAS1;\n              load_mesg = 1'b0;\n              push = 1'b0;\n            end\n          endcase\n        end  // HAS1\n        \n        K_MIN2: begin  // FIFO contains >1 item, some in SRL\n          srl2mesg = 1'b1;\n          casex ({s_valid,m_ready})\n            {S_VALID_1,M_READY_0}: begin  // Receive a new item, push into SRL\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b1;\n              pop = 1'b0;\n            end\n            \n            {S_VALID_0,M_READY_1}: begin  // Pop SRL to replace output reg\n              next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b0;\n              pop = 1'b1;\n            end\n            \n            {S_VALID_1,M_READY_1}: begin  // Push a new item while popping\n              next = K_MIN2;\n              load_mesg = 1'b1;\n              push = 1'b1;\n              pop = 1'b1;\n            end\n            \n            default: begin  // s_valid=0, m_ready=0: hold state\n              next = K_MIN2;\n              load_mesg = 1'b0;\n              push = 1'b0;\n              pop = 1'b0;\n            end\n          endcase\n        end  // MIN2\n        \n        default: begin  // Same as RESET\n          next = K_EMPTY;\n        end  // default\n      endcase\n    end\n    \n    always @(posedge aclk) begin\n      if (areset) begin\n        state <= K_EMPTY;\n      end else begin\n        state <= next;\n      end\n    end\n            \n    always @(posedge aclk) begin  // Payload reg needs no reset\n      if (load_mesg) begin\n        mesg_reg <= srl2mesg ? srl_reg : s_mesg;\n      end\n    end\n        \n    // SRL FIFO address pointer\n    always @(posedge aclk) begin\n      if (areset) begin\n        fifoaddr <= P_EMPTY;\n      end else begin\n        if (push & ~pop) begin\n          fifoaddr <= fifoaddr + 1;\n        end else if (~push & pop) begin\n          fifoaddr <= fifoaddr - 1;\n        end\n      end\n    end\n        \n    //---------------------------------------------------------------------------\n    // Instantiate SRLs\n    //---------------------------------------------------------------------------\n    for (i=0;i<C_FIFO_WIDTH;i=i+1) begin : srl\n      axi_register_slice_v2_1_15_srl_rtl #\n        (\n         .C_A_WIDTH (C_FIFO_SIZE)\n        )\n        srl_nx1\n        (\n         .clk (aclk),\n         .a   (fifoaddr),\n         .ce  (s_valid),\n         .d   (s_mesg[i]),\n         .q   (srl_reg[i])\n        );\n    end      \n  endgenerate\n  \nendmodule\n\n\n//  (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.\n//\n//  This file contains confidential and proprietary information\n//  of Xilinx, Inc. and is protected under U.S. and\n//  international copyright and other intellectual property\n//  laws.\n//\n//  DISCLAIMER\n//  This disclaimer is not a license and does not grant any\n//  rights to the materials distributed herewith. Except as\n//  otherwise provided in a valid license issued to you by\n//  Xilinx, and to the maximum extent permitted by applicable\n//  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//  (2) Xilinx shall not be liable (whether in contract or tort,\n//  including negligence, or under any other theory of\n//  liability) for any loss or damage of any kind or nature\n//  related to, arising under or in connection with these\n//  materials, including for any direct, or any indirect,\n//  special, incidental, or consequential loss or damage\n//  (including loss of data, profits, goodwill, or any type of\n//  loss or damage suffered as a result of any action brought\n//  by a third party) even if such damage or loss was\n//  reasonably foreseeable or Xilinx had been advised of the\n//  possibility of the same.\n//\n//  CRITICAL APPLICATIONS\n//  Xilinx products are not designed or intended to be fail-\n//  safe, or for use in any application requiring fail-safe\n//  performance, such as life-support or safety devices or\n//  systems, Class III medical devices, nuclear facilities,\n//  applications related to the deployment of airbags, or any\n//  other applications that could lead to death, personal\n//  injury, or severe property or environmental damage\n//  (individually and collectively, \"Critical\n//  Applications\"). Customer assumes the sole risk and\n//  liability of any use of Xilinx products in Critical\n//  Applications, subject only to applicable laws and\n//  regulations governing limitations on product liability.\n//\n//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//  PART OF THIS FILE AT ALL TIMES. \n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n//   Register selected channels on the forward and/or reverse signal paths.\n//   5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   axi_register_slice\n//      axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_register_slice_v2_1_15_axi_register_slice #\n  (\n   parameter C_FAMILY                            = \"virtex6\",\n   parameter C_AXI_PROTOCOL                      = 0,\n   parameter integer C_AXI_ID_WIDTH              = 1,\n   parameter integer C_AXI_ADDR_WIDTH            = 32,\n   parameter integer C_AXI_DATA_WIDTH            = 32,\n   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n   parameter integer C_AXI_AWUSER_WIDTH          = 1,\n   parameter integer C_AXI_ARUSER_WIDTH          = 1,\n   parameter integer C_AXI_WUSER_WIDTH           = 1,\n   parameter integer C_AXI_RUSER_WIDTH           = 1,\n   parameter integer C_AXI_BUSER_WIDTH           = 1,\n   // C_REG_CONFIG_*:\n   //   0 => BYPASS    = The channel is just wired through the module.\n   //   1 => FWD_REV   = Both FWD and REV (fully-registered)\n   //   2 => FWD       = The master VALID and payload signals are registrated. \n   //   3 => REV       = The slave ready signal is registrated\n   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n   //   6 => INPUTS    = Slave and Master side inputs are registrated.\n   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)\n   //   12 => SLR Crossing (source->dest flops, full-width payload, single clock)\n   //   13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock)\n   //   15 => Variable SLR Crossings (single clock)\n   parameter integer C_REG_CONFIG_AW = 7,\n   parameter integer C_REG_CONFIG_W  = 1,\n   parameter integer C_REG_CONFIG_B  = 7,\n   parameter integer C_REG_CONFIG_AR = 7,\n   parameter integer C_REG_CONFIG_R  = 1,\n   parameter integer C_NUM_SLR_CROSSINGS = 0,\n   parameter integer C_PIPELINES_MASTER_AW = 0,\n   parameter integer C_PIPELINES_MASTER_W  = 0,\n   parameter integer C_PIPELINES_MASTER_B  = 0,\n   parameter integer C_PIPELINES_MASTER_AR = 0,\n   parameter integer C_PIPELINES_MASTER_R  = 0,\n   parameter integer C_PIPELINES_SLAVE_AW = 0,\n   parameter integer C_PIPELINES_SLAVE_W  = 0,\n   parameter integer C_PIPELINES_SLAVE_B  = 0,\n   parameter integer C_PIPELINES_SLAVE_AR = 0,\n   parameter integer C_PIPELINES_SLAVE_R  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AW = 0,\n   parameter integer C_PIPELINES_MIDDLE_W  = 0,\n   parameter integer C_PIPELINES_MIDDLE_B  = 0,\n   parameter integer C_PIPELINES_MIDDLE_AR = 0,\n   parameter integer C_PIPELINES_MIDDLE_R  = 0\n   )   \n  (\n   // System Signals\n   input wire aclk,\n   input wire aclk2x,\n   input wire aresetn,\n\n   // Slave Interface Write Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,\n   input  wire [3-1:0]                  s_axi_awsize,\n   input  wire [2-1:0]                  s_axi_awburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,\n   input  wire [4-1:0]                  s_axi_awcache,\n   input  wire [3-1:0]                  s_axi_awprot,\n   input  wire [4-1:0]                  s_axi_awregion,\n   input  wire [4-1:0]                  s_axi_awqos,\n   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n   input  wire                          s_axi_awvalid,\n   output wire                          s_axi_awready,\n\n   // Slave Interface Write Data Ports\n   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,\n   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n   input  wire                          s_axi_wlast,\n   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,\n   input  wire                          s_axi_wvalid,\n   output wire                          s_axi_wready,\n\n   // Slave Interface Write Response Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,\n   output wire [2-1:0]                 s_axi_bresp,\n   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n   output wire                         s_axi_bvalid,\n   input  wire                         s_axi_bready,\n\n   // Slave Interface Read Address Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,\n   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,\n   input  wire [3-1:0]                  s_axi_arsize,\n   input  wire [2-1:0]                  s_axi_arburst,\n   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,\n   input  wire [4-1:0]                  s_axi_arcache,\n   input  wire [3-1:0]                  s_axi_arprot,\n   input  wire [4-1:0]                  s_axi_arregion,\n   input  wire [4-1:0]                  s_axi_arqos,\n   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n   input  wire                          s_axi_arvalid,\n   output wire                          s_axi_arready,\n\n   // Slave Interface Read Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,\n   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,\n   output wire [2-1:0]                 s_axi_rresp,\n   output wire                         s_axi_rlast,\n   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n   output wire                         s_axi_rvalid,\n   input  wire                         s_axi_rready,\n   \n   // Master Interface Write Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,\n   output wire [3-1:0]                  m_axi_awsize,\n   output wire [2-1:0]                  m_axi_awburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,\n   output wire [4-1:0]                  m_axi_awcache,\n   output wire [3-1:0]                  m_axi_awprot,\n   output wire [4-1:0]                  m_axi_awregion,\n   output wire [4-1:0]                  m_axi_awqos,\n   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n   output wire                          m_axi_awvalid,\n   input  wire                          m_axi_awready,\n   \n   // Master Interface Write Data Ports\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,\n   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,\n   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n   output wire                          m_axi_wlast,\n   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,\n   output wire                          m_axi_wvalid,\n   input  wire                          m_axi_wready,\n   \n   // Master Interface Write Response Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,\n   input  wire [2-1:0]                 m_axi_bresp,\n   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n   input  wire                         m_axi_bvalid,\n   output wire                         m_axi_bready,\n   \n   // Master Interface Read Address Port\n   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,\n   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,\n   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,\n   output wire [3-1:0]                  m_axi_arsize,\n   output wire [2-1:0]                  m_axi_arburst,\n   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,\n   output wire [4-1:0]                  m_axi_arcache,\n   output wire [3-1:0]                  m_axi_arprot,\n   output wire [4-1:0]                  m_axi_arregion,\n   output wire [4-1:0]                  m_axi_arqos,\n   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n   output wire                          m_axi_arvalid,\n   input  wire                          m_axi_arready,\n   \n   // Master Interface Read Data Ports\n   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,\n   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,\n   input  wire [2-1:0]                 m_axi_rresp,\n   input  wire                         m_axi_rlast,\n   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n   input  wire                         m_axi_rvalid,\n   output wire                         m_axi_rready\n  );\n\n  wire reset;\n\n  localparam integer C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;\n  localparam integer P_FORWARD = 0;\n  localparam integer P_RESPONSE = 1;\n  `include \"axi_infrastructure_v1_1_0.vh\"\n\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;\n  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;\n  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;\n  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;\n  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;\n  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;\n\n  assign reset = ~aresetn;\n  \n  generate\n\n  axi_infrastructure_v1_1_0_axi2vector #( \n    .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n    .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n    .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n    .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n    .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n    .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n    .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n    .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n    .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n    .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n    .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n    .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n    .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n    .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n    .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n    .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n  )\n  axi2vector_0 ( \n    .s_axi_awid      ( s_axi_awid      ) ,\n    .s_axi_awaddr    ( s_axi_awaddr    ) ,\n    .s_axi_awlen     ( s_axi_awlen     ) ,\n    .s_axi_awsize    ( s_axi_awsize    ) ,\n    .s_axi_awburst   ( s_axi_awburst   ) ,\n    .s_axi_awlock    ( s_axi_awlock    ) ,\n    .s_axi_awcache   ( s_axi_awcache   ) ,\n    .s_axi_awprot    ( s_axi_awprot    ) ,\n    .s_axi_awqos     ( s_axi_awqos     ) ,\n    .s_axi_awuser    ( s_axi_awuser    ) ,\n    .s_axi_awregion  ( s_axi_awregion  ) ,\n    .s_axi_wid       ( s_axi_wid       ) ,\n    .s_axi_wdata     ( s_axi_wdata     ) ,\n    .s_axi_wstrb     ( s_axi_wstrb     ) ,\n    .s_axi_wlast     ( s_axi_wlast     ) ,\n    .s_axi_wuser     ( s_axi_wuser     ) ,\n    .s_axi_bid       ( s_axi_bid       ) ,\n    .s_axi_bresp     ( s_axi_bresp     ) ,\n    .s_axi_buser     ( s_axi_buser     ) ,\n    .s_axi_arid      ( s_axi_arid      ) ,\n    .s_axi_araddr    ( s_axi_araddr    ) ,\n    .s_axi_arlen     ( s_axi_arlen     ) ,\n    .s_axi_arsize    ( s_axi_arsize    ) ,\n    .s_axi_arburst   ( s_axi_arburst   ) ,\n    .s_axi_arlock    ( s_axi_arlock    ) ,\n    .s_axi_arcache   ( s_axi_arcache   ) ,\n    .s_axi_arprot    ( s_axi_arprot    ) ,\n    .s_axi_arqos     ( s_axi_arqos     ) ,\n    .s_axi_aruser    ( s_axi_aruser    ) ,\n    .s_axi_arregion  ( s_axi_arregion  ) ,\n    .s_axi_rid       ( s_axi_rid       ) ,\n    .s_axi_rdata     ( s_axi_rdata     ) ,\n    .s_axi_rresp     ( s_axi_rresp     ) ,\n    .s_axi_rlast     ( s_axi_rlast     ) ,\n    .s_axi_ruser     ( s_axi_ruser     ) ,\n    .s_awpayload ( s_awpayload ) ,\n    .s_wpayload  ( s_wpayload  ) ,\n    .s_bpayload  ( s_bpayload  ) ,\n    .s_arpayload ( s_arpayload ) ,\n    .s_rpayload  ( s_rpayload  ) \n  );\n    \n  if (C_REG_CONFIG_AW <= 9) begin : aw\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) \n    )\n    aw_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else if (C_REG_CONFIG_AW == 15) begin : aw15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AW) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AW) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AW) \n    )\n    aw_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_awpayload),\n      .S_VALID(s_axi_awvalid),\n      .S_READY(s_axi_awready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_awpayload),\n      .M_VALID(m_axi_awvalid),\n      .M_READY(m_axi_awready)\n    );\n    \n  end else begin : aw12\n    \n    localparam integer P_AW_EVEN_WIDTH = G_AXI_AWPAYLOAD_WIDTH[0] ? (G_AXI_AWPAYLOAD_WIDTH+1) : G_AXI_AWPAYLOAD_WIDTH;\n    localparam integer P_AW_TDM_WIDTH = P_AW_EVEN_WIDTH/2;\n    localparam integer P_AW_SLR_WIDTH = (C_REG_CONFIG_AW == 13) ? P_AW_TDM_WIDTH : G_AXI_AWPAYLOAD_WIDTH;\n    \n    wire [P_AW_SLR_WIDTH-1:0] slr_awpayload;\n    wire slr_awhandshake;\n    wire slr_awready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_awpayload ) ,\n      .S_VALID        ( s_axi_awvalid   ) ,\n      .S_READY        ( s_axi_awready   ) ,\n      .laguna_m_payload   ( slr_awpayload ) , \n      .laguna_m_handshake ( slr_awhandshake   ) ,\n      .laguna_m_ready     ( slr_awready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AW       ) ,\n      .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AW_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_aw (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_awpayload ) ,\n      .laguna_s_handshake ( slr_awhandshake   ) ,\n      .laguna_s_ready     ( slr_awready   ) ,\n      .M_PAYLOAD_DATA ( m_awpayload ) , \n      .M_VALID        ( m_axi_awvalid   ) ,\n      .M_READY        ( m_axi_awready   )\n    );\n  end  // gen_aw\n    \n  if (C_REG_CONFIG_W <= 9) begin : w\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) \n    )\n    w_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else if (C_REG_CONFIG_W == 15) begin : w15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_W) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_W) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_W) \n    )\n    w_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_wpayload),\n      .S_VALID(s_axi_wvalid),\n      .S_READY(s_axi_wready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_wpayload),\n      .M_VALID(m_axi_wvalid),\n      .M_READY(m_axi_wready)\n    );\n    \n  end else begin : w12\n    \n    localparam integer P_W_EVEN_WIDTH = G_AXI_WPAYLOAD_WIDTH[0] ? (G_AXI_WPAYLOAD_WIDTH+1) : G_AXI_WPAYLOAD_WIDTH;\n    localparam integer P_W_TDM_WIDTH = P_W_EVEN_WIDTH/2;\n    localparam integer P_W_SLR_WIDTH = (C_REG_CONFIG_W == 13) ? P_W_TDM_WIDTH : G_AXI_WPAYLOAD_WIDTH;\n    \n    wire [P_W_SLR_WIDTH-1:0] slr_wpayload;\n    wire slr_whandshake;\n    wire slr_wready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_wpayload ) ,\n      .S_VALID        ( s_axi_wvalid   ) ,\n      .S_READY        ( s_axi_wready   ) ,\n      .laguna_m_payload   ( slr_wpayload ) , \n      .laguna_m_handshake ( slr_whandshake   ) ,\n      .laguna_m_ready     ( slr_wready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_W       ) ,\n      .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_W_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_w (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_wpayload ) ,\n      .laguna_s_handshake ( slr_whandshake   ) ,\n      .laguna_s_ready     ( slr_wready   ) ,\n      .M_PAYLOAD_DATA ( m_wpayload ) , \n      .M_VALID        ( m_axi_wvalid   ) ,\n      .M_READY        ( m_axi_wready   )\n    );\n  end  // gen_w\n\n  if (C_REG_CONFIG_B <= 9) begin : b\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) \n    )\n    b_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n \n  end else if (C_REG_CONFIG_B == 15) begin : b15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_B) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_B) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_B) \n    )\n    b_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_bpayload),\n      .S_VALID(m_axi_bvalid),\n      .S_READY(m_axi_bready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_bpayload),\n      .M_VALID(s_axi_bvalid),\n      .M_READY(s_axi_bready)\n    );\n    \n  end else begin : b12\n    \n    localparam integer P_B_EVEN_WIDTH = G_AXI_BPAYLOAD_WIDTH[0] ? (G_AXI_BPAYLOAD_WIDTH+1) : G_AXI_BPAYLOAD_WIDTH;\n    localparam integer P_B_TDM_WIDTH = P_B_EVEN_WIDTH/2;\n    localparam integer P_B_SLR_WIDTH = (C_REG_CONFIG_B == 13) ? P_B_TDM_WIDTH : G_AXI_BPAYLOAD_WIDTH;\n    \n    wire [P_B_SLR_WIDTH-1:0] slr_bpayload;\n    wire slr_bhandshake;\n    wire slr_bready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( m_bpayload ) ,\n      .S_VALID        ( m_axi_bvalid   ) ,\n      .S_READY        ( m_axi_bready   ) ,\n      .laguna_m_payload   ( slr_bpayload ) , \n      .laguna_m_handshake ( slr_bhandshake   ) ,\n      .laguna_m_ready     ( slr_bready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_B       ) ,\n      .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_B_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_b (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_bpayload ) ,\n      .laguna_s_handshake ( slr_bhandshake   ) ,\n      .laguna_s_ready     ( slr_bready   ) ,\n      .M_PAYLOAD_DATA ( s_bpayload ) , \n      .M_VALID        ( s_axi_bvalid   ) ,\n      .M_READY        ( s_axi_bready   )\n    );\n  end  // gen_b\n\n  if (C_REG_CONFIG_AR <= 9) begin : ar\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) \n    )\n    ar_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else if (C_REG_CONFIG_AR == 15) begin : ar15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_FORWARD ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_AR) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_AR) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_AR) \n    )\n    ar_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(s_arpayload),\n      .S_VALID(s_axi_arvalid),\n      .S_READY(s_axi_arready),\n\n      // Master side\n      .M_PAYLOAD_DATA(m_arpayload),\n      .M_VALID(m_axi_arvalid),\n      .M_READY(m_axi_arready)\n    );\n    \n  end else begin : ar12\n    \n    localparam integer P_AR_EVEN_WIDTH = G_AXI_ARPAYLOAD_WIDTH[0] ? (G_AXI_ARPAYLOAD_WIDTH+1) : G_AXI_ARPAYLOAD_WIDTH;\n    localparam integer P_AR_TDM_WIDTH = P_AR_EVEN_WIDTH/2;\n    localparam integer P_AR_SLR_WIDTH = (C_REG_CONFIG_AR == 13) ? P_AR_TDM_WIDTH : G_AXI_ARPAYLOAD_WIDTH;\n    \n    wire [P_AR_SLR_WIDTH-1:0] slr_arpayload;\n    wire slr_arhandshake;\n    wire slr_arready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_master_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( s_arpayload ) ,\n      .S_VALID        ( s_axi_arvalid   ) ,\n      .S_READY        ( s_axi_arready   ) ,\n      .laguna_m_payload   ( slr_arpayload ) , \n      .laguna_m_handshake ( slr_arhandshake   ) ,\n      .laguna_m_ready     ( slr_arready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_AR       ) ,\n      .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_AR_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_slave_ar (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_arpayload ) ,\n      .laguna_s_handshake ( slr_arhandshake   ) ,\n      .laguna_s_ready     ( slr_arready   ) ,\n      .M_PAYLOAD_DATA ( m_arpayload ) , \n      .M_VALID        ( m_axi_arvalid   ) ,\n      .M_READY        ( m_axi_arready   )\n    );\n  end  // gen_ar\n        \n  if (C_REG_CONFIG_R <= 9) begin : r\n    axi_register_slice_v2_1_15_axic_register_slice # (\n      .C_FAMILY     ( C_FAMILY             ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) \n    )\n    r_pipe (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else if (C_REG_CONFIG_R == 15) begin : r15\n    \n    axi_register_slice_v2_1_15_multi_slr # (\n      .C_FAMILY     ( C_FAMILY              ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_CHANNEL    ( P_RESPONSE ),\n      .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) ,\n      .C_PIPELINES_MASTER  (C_PIPELINES_MASTER_R) ,\n      .C_PIPELINES_SLAVE   (C_PIPELINES_SLAVE_R) ,\n      .C_PIPELINES_MIDDLE  (C_PIPELINES_MIDDLE_R) \n    )\n    r_multi (\n      // System Signals\n      .ACLK(aclk),\n      .ARESET(reset),\n\n      // Slave side\n      .S_PAYLOAD_DATA(m_rpayload),\n      .S_VALID(m_axi_rvalid),\n      .S_READY(m_axi_rready),\n\n      // Master side\n      .M_PAYLOAD_DATA(s_rpayload),\n      .M_VALID(s_axi_rvalid),\n      .M_READY(s_axi_rready)\n    );\n    \n  end else begin : r12\n    \n    localparam integer P_R_EVEN_WIDTH = G_AXI_RPAYLOAD_WIDTH[0] ? (G_AXI_RPAYLOAD_WIDTH+1) : G_AXI_RPAYLOAD_WIDTH;\n    localparam integer P_R_TDM_WIDTH = P_R_EVEN_WIDTH/2;\n    localparam integer P_R_SLR_WIDTH = (C_REG_CONFIG_R == 13) ? P_R_TDM_WIDTH : G_AXI_RPAYLOAD_WIDTH;\n    \n    wire [P_R_SLR_WIDTH-1:0] slr_rpayload;\n    wire slr_rhandshake;\n    wire slr_rready;\n        \n    axi_register_slice_v2_1_15_source_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0)\n    )\n    slr_slave_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .S_PAYLOAD_DATA ( m_rpayload ) ,\n      .S_VALID        ( m_axi_rvalid   ) ,\n      .S_READY        ( m_axi_rready   ) ,\n      .laguna_m_payload   ( slr_rpayload ) , \n      .laguna_m_handshake ( slr_rhandshake   ) ,\n      .laguna_m_ready     ( slr_rready   )\n    );\n\n    axi_register_slice_v2_1_15_dest_region_slr #(\n      .C_FAMILY     ( C_FAMILY         ) ,\n      .C_REG_CONFIG ( C_REG_CONFIG_R       ) ,\n      .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,\n      .C_SLR_WIDTH  ( P_R_SLR_WIDTH ),\n      .C_PIPELINES  (0),\n      .C_SOURCE_LATENCY (2)\n    )\n    slr_master_r (\n      .ACLK           ( aclk            ) ,\n      .ACLK2X         ( aclk2x            ) ,\n      .ARESET         ( reset        ) ,\n      .laguna_s_payload   ( slr_rpayload ) ,\n      .laguna_s_handshake ( slr_rhandshake   ) ,\n      .laguna_s_ready     ( slr_rready   ) ,\n      .M_PAYLOAD_DATA ( s_rpayload ) , \n      .M_VALID        ( s_axi_rvalid   ) ,\n      .M_READY        ( s_axi_rready   )\n    );\n  end  // gen_r\n\n  axi_infrastructure_v1_1_0_vector2axi #( \n    .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,\n    .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,\n    .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,\n    .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,\n    .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,\n    .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,\n    .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,\n    .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,\n    .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,\n    .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,\n    .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,\n    .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,\n    .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,\n    .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,\n    .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,\n    .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) \n  )\n  vector2axi_0 ( \n    .m_awpayload    ( m_awpayload    ) ,\n    .m_wpayload     ( m_wpayload     ) ,\n    .m_bpayload     ( m_bpayload     ) ,\n    .m_arpayload    ( m_arpayload    ) ,\n    .m_rpayload     ( m_rpayload     ) ,\n    .m_axi_awid     ( m_axi_awid     ) ,\n    .m_axi_awaddr   ( m_axi_awaddr   ) ,\n    .m_axi_awlen    ( m_axi_awlen    ) ,\n    .m_axi_awsize   ( m_axi_awsize   ) ,\n    .m_axi_awburst  ( m_axi_awburst  ) ,\n    .m_axi_awlock   ( m_axi_awlock   ) ,\n    .m_axi_awcache  ( m_axi_awcache  ) ,\n    .m_axi_awprot   ( m_axi_awprot   ) ,\n    .m_axi_awqos    ( m_axi_awqos    ) ,\n    .m_axi_awuser   ( m_axi_awuser   ) ,\n    .m_axi_awregion ( m_axi_awregion ) ,\n    .m_axi_wid      ( m_axi_wid      ) ,\n    .m_axi_wdata    ( m_axi_wdata    ) ,\n    .m_axi_wstrb    ( m_axi_wstrb    ) ,\n    .m_axi_wlast    ( m_axi_wlast    ) ,\n    .m_axi_wuser    ( m_axi_wuser    ) ,\n    .m_axi_bid      ( m_axi_bid      ) ,\n    .m_axi_bresp    ( m_axi_bresp    ) ,\n    .m_axi_buser    ( m_axi_buser    ) ,\n    .m_axi_arid     ( m_axi_arid     ) ,\n    .m_axi_araddr   ( m_axi_araddr   ) ,\n    .m_axi_arlen    ( m_axi_arlen    ) ,\n    .m_axi_arsize   ( m_axi_arsize   ) ,\n    .m_axi_arburst  ( m_axi_arburst  ) ,\n    .m_axi_arlock   ( m_axi_arlock   ) ,\n    .m_axi_arcache  ( m_axi_arcache  ) ,\n    .m_axi_arprot   ( m_axi_arprot   ) ,\n    .m_axi_arqos    ( m_axi_arqos    ) ,\n    .m_axi_aruser   ( m_axi_aruser   ) ,\n    .m_axi_arregion ( m_axi_arregion ) ,\n    .m_axi_rid      ( m_axi_rid      ) ,\n    .m_axi_rdata    ( m_axi_rdata    ) ,\n    .m_axi_rresp    ( m_axi_rresp    ) ,\n    .m_axi_rlast    ( m_axi_rlast    ) ,\n    .m_axi_ruser    ( m_axi_ruser    ) \n  );\n\nendgenerate\nendmodule // axi_register_slice\n\n\n", "num_lines": 3108}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nYpfMx9GvesTR0nGdN/CyBECjW9iz+5g/YsUCkmLyfcl9kUguiUzzNwVg3ON/A4BrqXdSVCEc4oc9\njf3mXlpRVA==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\ncsN9JMXmg9BJlgjFcEph5gOv1+p3hZIqsmwL5z2Czw9ZfUoTeQK8FE1D4XRyaYorfGhXvVrScPSF\n14EXvUeXM4z8gXl7ggoHA3zrbps1E0fuKYuJVXPPM4YvEgQ09ApyfPThDlQ60osC/OzCsb7WAWU6\n3ppy//9UC055RD8QArg=\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nEMnukfw+EF6W7W68TalTatBqzkeWepH6qfewzeutG3Q+uulyg7ZBqD9VY6MkOWr/5PVt3VvwPTv0\ncTqcPlL+v5/amIsFL6u84fyqMWdVKV+/QEiQiBDjGctlcblh2c8OMk6DpQaTNwhyN3D23UxA8+w7\niiVSaZ0o+KPcB6mYhbU=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nENtcLOHCNxDYI9wIzYepJfjNyw7YNxm9g2EJL0jkt9SXZIAPCKrT6yX7EgSe8KWiPlvUcB5Xf6lt\nXInmua4ZJi+zLfCh9FxCEZt27Funifdm0/53JKR79McWrEE1XHWqcwq0XDL8ZPDBILgHyz+l8d+R\nv/722mxUdGqIcEefgyNZATx1aHURCY9XO4KN9s0KEkVk/SaBeMo9HAxLkOm12jBFIZobuIc7GydH\nreLCALybcg3Td+1K/U8mDaPpzLbfOSZlmeXOUfvRxYANrnuJzcmqR+Kk6bIzQ2Zld9unF35AM6nu\nl73TF1pvbs8jZU9uKDkqqOpIesBTQUBjAU18Tw==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\ng98f31KFk932yZSp44BGJiVI84eiNM0aomH1rJ10xqNbK7Ace/1VwJ1bChweO2Olr46vTnnXLi86\npChf5tfT3of2mBtxgJk7aHrA6oA1NWlJT5SGAkTYtqJqmYfIoJsedjSjgN92lkePNbASK31ecyQo\n+pkILfAlx20IHRX7vRRotxahNFAzn39Si5+eLONMqhkPrLNXaKAJi2Lq2bZ8FpKeolihf6dLsFf8\nBr8Xd1s9cpRAAHDoE9OkdICG9MeUb755cRZovBOuJYFBSSvSDmx1bk1pXFWSxDG4Z7kQ78Cr4AAq\n2pSeJ+//Owp2/n0gWP+phsgpA3zegics2/gpRw==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinx_2016_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nSJKBkZFw7Efj+9dJLkxk1jngEsHj0sd8fIn4WQTY4TcrYB3t0c6gxiQubxvLLEJg4QgsvsgSLnD6\niFfpfDF5nj5X/fP3btucB79804nSQ2iTm2UxEOwbHTwKwaXqs0OIRH3AexAv6pYTksMqC6OPQi5/\nYJwjAqN+/W4Q1Yno+OKjz9/1vURz26EHmEcun6zS9kFfW08h9R57AWuSasizu2vGSd3THmF1+Sx5\ncvngOfWiK5CjeInipR9ydR6F4Ky87RfDTJmYSJKHrUne5+DadfO+yLtBH9UFKu4OcZA3ryLTKzXR\nyWltCNxGczDM62TEU1auvaKD9/cuoEdZHiKZvg==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 2368)\n`pragma protect data_block\ni9xS00la1AKc+pJxWfZRqs0vdEkUthXwAPplov4xkH6M1Oy3c17Ein1DprC9vsLj/Kix6nguoJkj\nKCod6CkRJgG9tSxBeQA7Z/oUhYIf7mvdK+6F5Kpd25sD1cB99b+wcRo1wX4AT/ryVDDJQ9r8w10n\nG32bDB64yxCmBb6jbg8UFFqCIP/s0r3d7HiC2IJHu81lSirXOnE0PBG597aHI1PvEhtreezy3KDB\nGEG5yVba/WMSPkiqzYE1L/YU73FuELj68OhfvcAbl3JLD5hqh6Wa0zLB0kpVIVbBjhgLErreoZRI\nTtlbCyjxPD7LIsrs0H08tqRMFbV2zi7ag2k0DLKA8z7uEvXfgWRqBLmwR5n68aiF7MJxWeYIPZ2k\neP1lhUPJAdpHbSUIbHeKrA85leRnmAIx4AjMV5ehyAfy1wFi6lTbzA1qRfy+bRi2YkIDaUR9+4+C\nbO8LnO6todEvhJ6NYaP/AukCAoaG+PjsaBBa7I43ylsdaxqAzRiPHN76FWfV5cCp+YYCED3MqXeK\nP9kWVzXnR50I7lMenjuhFCrbPDdSHGnSJE1/jNOIIwfXiWSkG45VRPxFaGmqZTownaT40ltJ+Uz8\n8QBnTao9a371YgNTVzMkvh+CxUb9O60aWXRC4Fl1l86tceST+blaHaHoU8wh8onQo0ag8cJdUeex\nul4iE+iaZH5Pq9PqQL+0JyY+ScclVTjn3lWgYgLYLBs2O4noyV7o8E8iDl8kNx5oyOq6nWrk8vJ6\n0rYffch66ELbnAkKJ7+HxuSIiNan856Ev/jDaj8arA96bInqV4Hyou/zhO0pNtZ8BofBSXII3KVv\nmUr9np+UC6PeIEl4ERCkoO725dESs6agRczlN3U3zi06YtKF4NHnNQF6Q5k/yFRDATvJFntSa5cX\nCq2riSlI5fD7HZ7AptAQ94GWFNE2vRKG/+7VqwXnvCJKhKXsUbkDulcIf34AbI7r7s7Bggm8vK1Q\nTxCGOHb7/txQtTj9kih0FQUbV68Wpcq8r2aXRFMa4xR9oJ6n/uON5rpZaTG0oWQubxKZ7vVhH6Bw\ngMA3qKO7tHqkQyarIZNw6rxijluCcVTlBw1Nv+A3WAZtZmiprqmbgmELrb//6VTWtOiwa5FayqfT\nOCvhEz0X61jHQ/bJQpQ8flkTToiL9Pnx++NvFRaTb9OL51VO4VV0A/WFyCmp9NZEFaQMuAdiiyi3\n8IU9vxp7jPvoBKCmvVcSbCnbylujhBT1j7hKlIFnwbdtdEGP+P3irmAfInLukus8V4vleb8yuZwc\nRJbxZsssfmdJgOp/T+xYcVUzTDRvBEgyl+6pvy9I/Neb8phhKPl5/JPGWj+jnWsh9QI7MG+W8kQC\n8gv8+Cw3E5qqdtHfQNIXNRqYZ9XvpxEXIo3GRBvfeZ36eoscT6C2sdA5sGMkDPTzTgPfKPDXFO75\nnuVOy/jeNaDHMbJdYKnpsW1IciGj/OyrhXQLw2OVWC4613A/RCXB/+IvUAwTO8TcAPN7fJZarIgg\nhRszeUDEbVlB/uvsptOs9WqbpYNmknXaqo4nl/lbhxCokfgjf6J9aCjZ6giiRZQhjraYsTTmgOR0\nmq8Z1cRwNjiEp5TB9CA2DOS4Oq5Jbupig1xdKM8QBsSfuG2pvmT2bcICutejSjadlgRpXBumeqdl\np5FxiBFjAyE0c/JkbHoUYXFTEWpwCndGVxtz+pU4uOHQiun8HME0Qp0d+60ECE8r+TtfFAVTK1Au\n0AW+/HbKSlWGTSYdIhpEvCXHyUbRZWyjjkttSvSyVbGey2fb7DcGkOIEhJ3EOjVaCiyL8iZPSiiu\nqk2HKfl04mGQ86Mk+NRgpxNsKnGsK0zU8gQO68bN2B3y8leN9y64VvO8FKnpe8Tg955t5LKNuDyE\nPuhgiOwXLPZGcvd1+vCJp0w1ykY9crDzlCcFhieGrLtqQvRLamarNoeVpAAWIebNPsULqskg8r9i\nP1M9To2EfMtFRIvqpa62MDBjCmO7JJSaExLI1ln5FrGUKnwPVqrD9TDw7tR/2/peBK/yH4aIMu0b\npauK4r7gzQV4ttelqKpGpKcv/nY3GaVPPLfS0sw6zXO8AepcgXn1BYoy74kPoeUAp+6HASxfwlS+\nyq/FAc/mSnKEykRQJf7b93w6hUOV1djXkg/gTUQP30vmrjLdz23bQBR6kFqB/IaYqUbnLnUdQdF+\nN0L43kGHdODb49/jQIPmUtPRF+2eOamdWnhI8He+tHC74whG1noCMH+vt/J/hOAlwR70V6P6r5C2\nxii06A18tR7AFDqOcHywfQ0SG66MJ1wfcK4WfmCeXptdl4MRr4yM6cjw5vwfOs7pXsPi8UcbDnxk\nQbI/K2zU75AQAKL8CnAkfQpaxWSbssrWEYtItkDsJ/g5iKO0v7a4XaFOEjZo0BIA/BglSJP2FK/o\n2cRqlWqdUQRq1zUfpT7T324k+yv9QHUpqIax6w0r7SklsNt9HqXZUrPphKA4qa7iOgFFI6b32zLJ\n3Tj/5UJcTEQHv1UDu71qoy0ogdwd53UD+X47b6YFP/2IQ/5kbtI9p0xy1uSkSRUEJh7tvTIaen49\nOk3sdK6UHd9DkD/Mp7zmfXmbKvruKMxgZh7siZsRhFhiug8DPXBo0+9llnkzPdgCuy+fnojuTmKH\nurAWObrpux7rdscEd6OoR26GxTudav49B9TpCQ/VI0OzaaAiHo7EYHa9TkW7x4n2sIyS1QioDcqS\nHqcIz7uaK/mn9i77fElGAObB2yfUPvV9lppH+1iWz2VPlFX5FWFUsSi1+52r4jhiIZkrqfZEpYQk\nMXjoJX860HOVFwRmDviJUzr9DTkU8KI2zuElz6AmLHvnIjuhvznKEFNPvHPINrqmRAn0CyLw0zSb\nnG2NHdM+uHlzEdCb4tCXaNUpI6cvsYadbkYFhR0yIV263LL4kHeL3hrnsd34TQBZ7cWbtpi3y47b\n2KZtkvJvMeM0uYgXXMC0B3BOewXOy3GQGB6gBeQoqKGj2lOJ5H/MfDxW6j1uH2uGy8qNYjPeSzCW\nGGQuiREDn9GNj3Vj6qN3IjPwi4qOwRqoPfMf0HHs8nJm00XYEmk0tda12Gu26T4+Uh+BCySqUnAC\nR1AkQAGI8bOcy4o+pmcjyoXC1nBZY0XGTNDKRbP8hg==\n`pragma protect end_protected\n", "num_lines": 98}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_4_4.v\n *\n * Description:\n *   This file is the Verilog behvarial model for the\n *       Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n *          Jun 11, 2007 Added independent register stages for \n *                       Port A and Port B (IP1_Jm/v2.5)\n *          Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n *          Mar 13, 2008 Behavioral model optimizations\n *          April 07, 2009  : Added support for Spartan-6 and Virtex-6\n *                            features, including the following:\n *                            (i)   error injection, detection and/or correction\n *                            (ii) reset priority\n *                            (iii)  special reset behavior\n *    \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5);\n\n  parameter INIT = 64'h0000000000000000;\n\n  input I0, I1, I2, I3, I4, I5;\n\n  output O;\n\n  reg O;\n  reg tmp;\n\n  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin\n \n    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;\n\n    if ( tmp == 0 || tmp == 1)\n\n        O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n  end\nendmodule\n\nmodule beh_vlog_muxf7_v8_4 (O, I0, I1, S);\n\n    output O;\n    reg    O;\n\n    input  I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t    if (S)\n\t\tO = I1;\n\t    else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_4 (Q, C, CLR, D);\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n\n    input  C, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (CLR)\n\tQ<= 1'b0;\n      else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_4 (Q, C, D, PRE);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, D, PRE;\n\n    reg Q;\n\n    initial Q= 1'b0;\n\n    always @(posedge C )\n      if (PRE)\n           Q <= 1'b1;\n      else\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D);\n\n  parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n    output Q;\n    input  C, CE, CLR, D;\n\n    reg Q;\n\n    initial Q= 1'b0;\n    always @(posedge C )\n       if (CLR)\n           Q <= 1'b0;\n       else if (CE)\n\t   Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_4\n#(\n   parameter\t     C_AXI_TYPE = 0\n )\n (\n    S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n    w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n    S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n  );\n\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_AWVALID;\n    input S_AXI_WVALID;\n    input S_AXI_BREADY;\n    input w_last_c;\n    input bready_timeout_c;\n    output aw_ready_r;\n    output S_AXI_WREADY;\n    output S_AXI_BVALID;\n    output S_AXI_WR_EN;\n    output addr_en_c;\n    output incr_addr_c;\n    output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n  wire w_ready_r_7;\n  wire w_ready_c;\n  wire aw_ready_c;\n  wire NlwRenamedSignal_bvalid_c;\n  wire NlwRenamedSignal_incr_addr_c;\n  wire present_state_FSM_FFd3_13;\n  wire present_state_FSM_FFd2_14;\n  wire present_state_FSM_FFd1_15;\n  wire present_state_FSM_FFd4_16;\n  wire present_state_FSM_FFd4_In;\n  wire present_state_FSM_FFd3_In;\n  wire present_state_FSM_FFd2_In;\n  wire present_state_FSM_FFd1_In;\n  wire present_state_FSM_FFd4_In1_21;\n  wire [0:0] Mmux_aw_ready_c ; \nbegin\n  assign\n  S_AXI_WREADY = w_ready_r_7,\n  S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n  S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n  incr_addr_c = NlwRenamedSignal_incr_addr_c,\n  bvalid_c = NlwRenamedSignal_bvalid_c;\n\n  assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( aw_ready_c), \n      .Q ( aw_ready_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( w_ready_c), \n      .Q ( w_ready_r_7)\n    );\n  beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4 (\n      .C ( S_ACLK), \n      .D ( present_state_FSM_FFd4_In), \n      .PRE ( S_ARESETN), \n      .Q ( present_state_FSM_FFd4_16)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd3_In), \n      .Q ( present_state_FSM_FFd3_13)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd2_In), \n      .Q ( present_state_FSM_FFd2_14)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C ( S_ACLK), \n      .CLR ( S_ARESETN), \n      .D ( present_state_FSM_FFd1_In), \n      .Q ( present_state_FSM_FFd1_15)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000055554440))\n  present_state_FSM_FFd3_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( S_AXI_AWVALID), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088880800))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( S_AXI_WVALID), \n      .I2 ( bready_timeout_c), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd2_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAA2000))\n  Mmux_addr_en_c_0_1 (\n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd2_14), \n      .I3 ( S_AXI_WVALID), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 (1'b0), \n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hF5F07570F5F05500))\n  Mmux_w_ready_c_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( w_ready_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 ( present_state_FSM_FFd2_14), \n      .I4 ( present_state_FSM_FFd1_15), \n      .I5 ( S_AXI_BREADY), \n      .O ( present_state_FSM_FFd1_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( present_state_FSM_FFd2_14), \n      .I2 ( present_state_FSM_FFd3_13), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( NlwRenamedSignal_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h2F0F27072F0F2200))\n  present_state_FSM_FFd4_In1 (\n      .I0 ( S_AXI_WVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_AWVALID), \n      .I3 ( present_state_FSM_FFd3_13), \n      .I4 ( present_state_FSM_FFd4_16), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( present_state_FSM_FFd4_In1_21)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  present_state_FSM_FFd4_In2 ( \n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( present_state_FSM_FFd4_In1_21), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( present_state_FSM_FFd4_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h7535753575305500))\n  Mmux_aw_ready_c_0_1 ( \n      .I0 ( S_AXI_AWVALID), \n      .I1 ( bready_timeout_c), \n      .I2 ( S_AXI_WVALID), \n      .I3 ( present_state_FSM_FFd4_16), \n      .I4 ( present_state_FSM_FFd3_13), \n      .I5 ( present_state_FSM_FFd2_14), \n      .O ( Mmux_aw_ready_c[0])\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000F8))\n  Mmux_aw_ready_c_0_2 (\n      .I0 ( present_state_FSM_FFd1_15), \n      .I1 ( S_AXI_BREADY), \n      .I2 ( Mmux_aw_ready_c[0]), \n      .I3 (1'b0), \n      .I4 (1'b0), \n      .I5 (1'b0), \n      .O ( aw_ready_c)\n    );\nend \nend \nendgenerate\n\n  //---------------------------------------------------------------------\n  // AXI FULL\n  //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n  wire w_ready_r_8; \n  wire w_ready_c; \n  wire aw_ready_c; \n  wire NlwRenamedSig_OI_bvalid_c; \n  wire present_state_FSM_FFd1_16; \n  wire present_state_FSM_FFd4_17; \n  wire present_state_FSM_FFd3_18; \n  wire present_state_FSM_FFd2_19; \n  wire present_state_FSM_FFd4_In; \n  wire present_state_FSM_FFd3_In; \n  wire present_state_FSM_FFd2_In; \n  wire present_state_FSM_FFd1_In; \n  wire present_state_FSM_FFd2_In1_24; \n  wire present_state_FSM_FFd4_In1_25; \n  wire N2; \n  wire N4; \nbegin\nassign\n  S_AXI_WREADY = w_ready_r_8,\n  bvalid_c = NlwRenamedSig_OI_bvalid_c,\n  S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  aw_ready_r_2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( aw_ready_c),\n      .Q ( aw_ready_r)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  w_ready_r\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( w_ready_c),\n      .Q ( w_ready_r_8)\n    );\n beh_vlog_ff_pre_v8_4  #(\n      .INIT (1'b1))\n  present_state_FSM_FFd4\n    (\n      .C ( S_ACLK),\n      .D ( present_state_FSM_FFd4_In),\n      .PRE ( S_ARESETN),\n      .Q ( present_state_FSM_FFd4_17)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd3\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd3_In),\n      .Q ( present_state_FSM_FFd3_18)\n    );\nbeh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_19)\n    );\n beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1\n    (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd1_In),\n      .Q ( present_state_FSM_FFd1_16)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000005540))\n  present_state_FSM_FFd3_In1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd4_17),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd3_In)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hBF3FBB33AF0FAA00))\n  Mmux_aw_ready_c_0_2\n    (\n      .I0 ( S_AXI_BREADY),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd1_16),\n      .I4 ( present_state_FSM_FFd4_17),\n      .I5 ( NlwRenamedSig_OI_bvalid_c),\n      .O ( aw_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hAAAAAAAA20000000))\n  Mmux_addr_en_c_0_1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( bready_timeout_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( S_AXI_WVALID),\n      .I4 ( w_last_c),\n      .I5 ( present_state_FSM_FFd4_17),\n      .O ( addr_en_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000A8))\n  Mmux_S_AXI_WR_EN_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( present_state_FSM_FFd2_19),\n      .I2 ( present_state_FSM_FFd3_18),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( S_AXI_WR_EN)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000002220))\n  Mmux_incr_addr_c_0_1\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( incr_addr_c)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000008880))\n  Mmux_aw_ready_c_0_11\n    (\n      .I0 ( S_AXI_WVALID),\n      .I1 ( w_last_c),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( NlwRenamedSig_OI_bvalid_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000D5C0))\n  present_state_FSM_FFd2_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd2_In1_24)\n    );\nSTATE_LOGIC_v8_4 #(\n      .INIT (64'hFFFFAAAA08AAAAAA))\n  present_state_FSM_FFd2_In2\n    (\n      .I0 ( present_state_FSM_FFd2_19),\n      .I1 ( S_AXI_AWVALID),\n      .I2 ( bready_timeout_c),\n      .I3 ( w_last_c),\n      .I4 ( S_AXI_WVALID),\n      .I5 ( present_state_FSM_FFd2_In1_24),\n      .O ( present_state_FSM_FFd2_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00C0004000C00000))\n  present_state_FSM_FFd4_In1\n    (\n      .I0 ( S_AXI_AWVALID),\n      .I1 ( w_last_c),\n      .I2 ( S_AXI_WVALID),\n      .I3 ( bready_timeout_c),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( present_state_FSM_FFd4_In1_25)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88F8))\n  present_state_FSM_FFd4_In2\n    (\n      .I0 ( present_state_FSM_FFd1_16),\n      .I1 ( S_AXI_BREADY),\n      .I2 ( present_state_FSM_FFd4_17),\n      .I3 ( S_AXI_AWVALID),\n      .I4 ( present_state_FSM_FFd4_In1_25),\n      .I5 (1'b0),\n      .O ( present_state_FSM_FFd4_In)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_w_ready_c_0_SW0\n    (\n      .I0 ( w_last_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N2)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'hFABAFABAFAAAF000))\n  Mmux_w_ready_c_0_Q\n    (\n      .I0 ( N2),\n      .I1 ( bready_timeout_c),\n      .I2 ( S_AXI_AWVALID),\n      .I3 ( present_state_FSM_FFd4_17),\n      .I4 ( present_state_FSM_FFd3_18),\n      .I5 ( present_state_FSM_FFd2_19),\n      .O ( w_ready_c)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_aw_ready_c_0_11_SW0\n    (\n      .I0 ( bready_timeout_c),\n      .I1 ( S_AXI_WVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O ( N4)\n    );\n STATE_LOGIC_v8_4 #(\n      .INIT (64'h88808880FFFF8880))\n  present_state_FSM_FFd1_In1\n    (\n      .I0 ( w_last_c),\n      .I1 ( N4),\n      .I2 ( present_state_FSM_FFd2_19),\n      .I3 ( present_state_FSM_FFd3_18),\n      .I4 ( present_state_FSM_FFd1_16),\n      .I5 ( S_AXI_BREADY),\n      .O ( present_state_FSM_FFd1_In)\n    );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_4 #(\n      parameter C_AXI_TYPE                 = 1,\n      parameter C_ADDRB_WIDTH              = 12\n      ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n          S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n          S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n          S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n    input S_AXI_R_LAST_INT;\n    input S_ACLK;\n    input S_ARESETN;\n    input S_AXI_ARVALID;\n    input S_AXI_RREADY;\n    output S_AXI_INCR_ADDR;\n    output S_AXI_ADDR_EN;\n    output S_AXI_SINGLE_TRANS;\n    output S_AXI_MUX_SEL;\n    output S_AXI_R_LAST;\n    output S_AXI_ARREADY;\n    output S_AXI_RLAST;\n    output S_AXI_RVALID;\n    output S_AXI_RD_EN;\n    input [7:0] S_AXI_ARLEN;\n\n  wire present_state_FSM_FFd1_13 ; \n  wire present_state_FSM_FFd2_14 ; \n  wire gaxi_full_sm_outstanding_read_r_15 ; \n  wire gaxi_full_sm_ar_ready_r_16 ; \n  wire gaxi_full_sm_r_last_r_17 ; \n  wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n  wire gaxi_full_sm_r_valid_c ; \n  wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n  wire gaxi_full_sm_ar_ready_c ; \n  wire gaxi_full_sm_outstanding_read_c ; \n  wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n  wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n  wire present_state_FSM_FFd2_In ; \n  wire present_state_FSM_FFd1_In ; \n  wire Mmux_S_AXI_R_LAST13 ; \n  wire N01 ; \n  wire N2 ; \n  wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n  wire N4 ; \n  wire N8 ; \n  wire N9 ; \n  wire N10 ; \n  wire N11 ; \n  wire N12 ; \n  wire N13 ; \n  assign\n  S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n  S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n  S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n  S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_outstanding_read_r (\n      .C (S_ACLK),\n      .CLR(S_ARESETN),\n      .D(gaxi_full_sm_outstanding_read_c),\n      .Q(gaxi_full_sm_outstanding_read_r_15)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_r_valid_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_r_valid_c),\n      .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  gaxi_full_sm_ar_ready_r (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (gaxi_full_sm_ar_ready_c),\n      .Q (gaxi_full_sm_ar_ready_r_16)\n    );\n  beh_vlog_ff_ce_clr_v8_4 #(\n      .INIT(1'b0))\n  gaxi_full_sm_r_last_r (\n      .C (S_ACLK),\n      .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .CLR (S_ARESETN),\n      .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n      .Q (gaxi_full_sm_r_last_r_17)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd2 (\n      .C ( S_ACLK),\n      .CLR ( S_ARESETN),\n      .D ( present_state_FSM_FFd2_In),\n      .Q ( present_state_FSM_FFd2_14)\n    );\n  beh_vlog_ff_clr_v8_4 #(\n      .INIT (1'b0))\n  present_state_FSM_FFd1 (\n      .C (S_ACLK),\n      .CLR (S_ARESETN),\n      .D (present_state_FSM_FFd1_In),\n      .Q (present_state_FSM_FFd1_13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000000000000B))\n  S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000008))\n  Mmux_S_AXI_SINGLE_TRANS11 (\n      .I0 (S_AXI_ARVALID),\n      .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_SINGLE_TRANS)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000004))\n  Mmux_S_AXI_ADDR_EN11 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (S_AXI_ARVALID),\n      .I2 (1'b0),\n      .I3 (1'b0),\n      .I4 (1'b0),\n      .I5 (1'b0),\n      .O (S_AXI_ADDR_EN)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hECEE2022EEEE2022))\n  present_state_FSM_FFd2_In1 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( present_state_FSM_FFd1_13),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .O ( present_state_FSM_FFd2_In)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000044440444))\n  Mmux_S_AXI_R_LAST131 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_RREADY),\n      .I5 (1'b0),\n      .O ( Mmux_S_AXI_R_LAST13)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h4000FFFF40004000))\n  Mmux_S_AXI_INCR_ADDR11 (\n      .I0 ( S_AXI_R_LAST_INT),\n      .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( Mmux_S_AXI_R_LAST13),\n      .O ( S_AXI_INCR_ADDR)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000FE))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n      .I0 ( S_AXI_ARLEN[2]),\n      .I1 ( S_AXI_ARLEN[1]),\n      .I2 ( S_AXI_ARLEN[0]),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N01)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000001))\n  S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n      .I0 ( S_AXI_ARLEN[7]),\n      .I1 ( S_AXI_ARLEN[6]),\n      .I2 ( S_AXI_ARLEN[5]),\n      .I3 ( S_AXI_ARLEN[4]),\n      .I4 ( S_AXI_ARLEN[3]),\n      .I5 ( N01),\n      .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000000007))\n  Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I2 ( 1'b0),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N2)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0020000002200200))\n  Mmux_gaxi_full_sm_outstanding_read_c1 (\n      .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd1_13),\n      .I3 ( present_state_FSM_FFd2_14),\n      .I4 ( gaxi_full_sm_outstanding_read_r_15),\n      .I5 ( N2),\n      .O ( gaxi_full_sm_outstanding_read_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000000004555))\n  Mmux_gaxi_full_sm_ar_ready_c12 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000000000EF))\n  Mmux_S_AXI_R_LAST11_SW0 (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I3 ( 1'b0),\n      .I4 ( 1'b0),\n      .I5 ( 1'b0),\n      .O ( N4)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hFCAAFC0A00AA000A))\n  Mmux_S_AXI_R_LAST11 (\n      .I0 ( S_AXI_ARVALID),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( present_state_FSM_FFd1_13),\n      .I4 ( N4),\n      .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n      .O ( gaxi_full_sm_r_valid_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000AAAAAA08))\n  S_AXI_MUX_SEL1 (\n      .I0 (present_state_FSM_FFd1_13),\n      .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 (S_AXI_RREADY),\n      .I3 (present_state_FSM_FFd2_14),\n      .I4 (gaxi_full_sm_outstanding_read_r_15),\n      .I5 (1'b0),\n      .O (S_AXI_MUX_SEL)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'hF3F3F755A2A2A200))\n  Mmux_S_AXI_RD_EN11 (\n      .I0 ( present_state_FSM_FFd1_13),\n      .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I2 ( S_AXI_RREADY),\n      .I3 ( gaxi_full_sm_outstanding_read_r_15),\n      .I4 ( present_state_FSM_FFd2_14),\n      .I5 ( S_AXI_ARVALID),\n      .O ( S_AXI_RD_EN)\n    );\n  beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 (\n      .I0 ( N8),\n      .I1 ( N9),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( present_state_FSM_FFd1_In)\n    );\n\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000005410F4F0))\n  present_state_FSM_FFd1_In3_F (\n      .I0 ( S_AXI_RREADY),\n      .I1 ( present_state_FSM_FFd2_14),\n      .I2 ( S_AXI_ARVALID),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I5 ( 1'b0),\n      .O ( N8)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000072FF7272))\n  present_state_FSM_FFd1_In3_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N9)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 (\n      .I0 ( N10),\n      .I1 ( N11),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( gaxi_full_sm_ar_ready_c)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000FFFF88A8))\n  Mmux_gaxi_full_sm_ar_ready_c14_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_RREADY),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n      .I5 ( 1'b0),\n      .O ( N10)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h000000008D008D8D))\n  Mmux_gaxi_full_sm_ar_ready_c14_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( S_AXI_R_LAST_INT),\n      .I2 ( gaxi_full_sm_outstanding_read_r_15),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N11)\n    );\n  beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 (\n      .I0 ( N12),\n      .I1 ( N13),\n      .S ( present_state_FSM_FFd1_13),\n      .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h0000000088088888))\n  Mmux_S_AXI_R_LAST1_F (\n      .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n      .I1 ( S_AXI_ARVALID),\n      .I2 ( present_state_FSM_FFd2_14),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N12)\n    );\n  STATE_LOGIC_v8_4 #(\n      .INIT (64'h00000000E400E4E4))\n  Mmux_S_AXI_R_LAST1_G (\n      .I0 ( present_state_FSM_FFd2_14),\n      .I1 ( gaxi_full_sm_outstanding_read_r_15),\n      .I2 ( S_AXI_R_LAST_INT),\n      .I3 ( S_AXI_RREADY),\n      .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n      .I5 ( 1'b0),\n      .O ( N13)\n    );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_4\n  # (\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE           = 0, // 0: Native Interface; 1: AXI Interface\n    parameter C_AXI_TYPE                 = 0, // 0: AXI Lite; 1: AXI Full;\n    parameter C_AXI_SLAVE_TYPE           = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n    parameter C_MEMORY_TYPE              = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n    parameter C_WRITE_DEPTH_A            = 0,\n    parameter C_AXI_AWADDR_WIDTH         = 32,\n    parameter C_ADDRA_WIDTH \t         = 12,\n    parameter C_AXI_WDATA_WIDTH          = 32,\n    parameter C_HAS_AXI_ID               = 0,\n    parameter C_AXI_ID_WIDTH             = 4,\n    // AXI OUTSTANDING WRITES\n    parameter C_AXI_OS_WR                = 2\n    )\n    (\n     // AXI Global Signals\n    input S_ACLK,  \n    input S_ARESETN,\n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n    input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n    input [8-1:0] S_AXI_AWLEN,\n    input [2:0] S_AXI_AWSIZE,\n    input [1:0] S_AXI_AWBURST,\n    input  S_AXI_AWVALID,\n    output S_AXI_AWREADY,\n    input  S_AXI_WVALID,\n    output S_AXI_WREADY, \n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n    output S_AXI_BVALID,\n    input  S_AXI_BREADY,\n    // Signals for BMG interface\n    output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n    output S_AXI_WR_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n                       ((C_AXI_WDATA_WIDTH==16)?1:\n                       ((C_AXI_WDATA_WIDTH==32)?2:\n                       ((C_AXI_WDATA_WIDTH==64)?3:\n                       ((C_AXI_WDATA_WIDTH==128)?4:\n                       ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n  wire bvalid_c                 ;\n  reg bready_timeout_c          = 0;\n  wire [1:0] bvalid_rd_cnt_c;\n  reg bvalid_r         \t= 0;\n  reg [2:0] bvalid_count_r = 0;\n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n  reg [1:0] bvalid_wr_cnt_r = 0;\n  reg [1:0] bvalid_rd_cnt_r = 0;\n  wire w_last_c                 ;\n  wire addr_en_c                ;\n  wire incr_addr_c              ;\n  wire aw_ready_r \t        ;\n  wire dec_alen_c               ;\n  reg bvalid_d1_c = 0;\n  reg [7:0] awlen_cntr_r = 0;\n  reg [7:0] awlen_int = 0;\n  reg [1:0] awburst_int = 0;\n\n  integer total_bytes              = 0;\n  integer wrap_boundary            = 0;\n  integer wrap_base_addr           = 0;\n  integer num_of_bytes_c           = 0;\n  integer num_of_bytes_r           = 0;\n  // Array to store BIDs\n  reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n  wire S_AXI_BVALID_axi_wr_fsm;\n\n  //-------------------------------------\n  //AXI WRITE FSM COMPONENT INSTANTIATION\n  //-------------------------------------\n write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n      (\n      .S_ACLK(S_ACLK),\n      .S_ARESETN(S_ARESETN),\n      .S_AXI_AWVALID(S_AXI_AWVALID),\n      .aw_ready_r(aw_ready_r),\n      .S_AXI_WVALID(S_AXI_WVALID),\n      .S_AXI_WREADY(S_AXI_WREADY),\n      .S_AXI_BREADY(S_AXI_BREADY),\n      .S_AXI_WR_EN(S_AXI_WR_EN),\n      .w_last_c(w_last_c),\n      .bready_timeout_c(bready_timeout_c),\n      .addr_en_c(addr_en_c),\n      .incr_addr_c(incr_addr_c),\n      .bvalid_c(bvalid_c),\n      .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t  );   \n  \n   \n   //Wrap Address boundary calculation \n   always@(*) begin\n    num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n    total_bytes    = (num_of_bytes_r)*(awlen_int+1);\n    wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n    wrap_boundary  = wrap_base_addr+total_bytes;\n  end\n  \n  //-------------------------------------------------------------------------\n  // BMG address generation\n  //-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n         if (S_ARESETN == 1'b1) begin\n           awaddr_reg       <= 0;\n\t   num_of_bytes_r   <= 0;\n\t   awburst_int      <= 0; \n\t end else begin\n           if (addr_en_c == 1'b1) begin\n              awaddr_reg       <= #FLOP_DELAY S_AXI_AWADDR  ;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      awburst_int      <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t   end else if (incr_addr_c == 1'b1) begin\n\t      if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t  awaddr_reg  <= wrap_base_addr;\n\t\tend else begin\n\t\t  awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t      end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg   <= awaddr_reg + num_of_bytes_r;\n\t      end\n           end\n         end\n   end\n  \n    \n   assign S_AXI_AWADDR_OUT   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t  \t       awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n  //-------------------------------------------------------------------------\n  // AXI wlast generation\n  //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          awlen_cntr_r      <= 0;\n\t  awlen_int       <= 0;\n\t  end else begin\n          if (addr_en_c == 1'b1) begin\n\t    awlen_int         <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    awlen_cntr_r      <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t    end else if (dec_alen_c == 1'b1) begin\n            awlen_cntr_r      <= #FLOP_DELAY awlen_cntr_r - 1 ;\n          end\n        end\n    end\n\n    assign w_last_c          = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n    \n    assign dec_alen_c        =  (incr_addr_c | w_last_c);\n\n   //-------------------------------------------------------------------------\n   // Generation of bvalid counter for outstanding transactions  \n   //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r             <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t  bvalid_count_r          <=   #FLOP_DELAY bvalid_count_r ;\n\t  end else if (bvalid_c == 1'b1) begin  \n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r + 1 ;\n\t  end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t  bvalid_count_r          <=  #FLOP_DELAY  bvalid_count_r - 1 ;\n\tend\n      end\n    end\n\n    //-------------------------------------------------------------------------\n    // Generation of bvalid when BID is used \n    //-------------------------------------------------------------------------\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n          bvalid_d1_c                <=  0;\n\tend else begin\n         // Delay the generation o bvalid_r for generation for BID \n         bvalid_d1_c  <= bvalid_c;\n         \n         //external bvalid signal generation\n         if (bvalid_d1_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n        end\n      end\n    end\n    endgenerate\n      \n   //-------------------------------------------------------------------------\n   // Generation of bvalid when BID is not used \n   //-------------------------------------------------------------------------\n   generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          bvalid_r                   <=  0;\n\tend else begin\n         //external bvalid signal generation\n         if (bvalid_c == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n           bvalid_r                <=   #FLOP_DELAY 0 ;\n         end\n       end\n    end\n    end\n   endgenerate\n    \n    //-------------------------------------------------------------------------\n    // Generation of Bready timeout\n    //-------------------------------------------------------------------------\n    always @(bvalid_count_r) begin\n    \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t  bready_timeout_c        <=   1'b1;\n\tend else begin\n\t  bready_timeout_c        <=   1'b0;\n\tend\n    end\n    \n    //-------------------------------------------------------------------------\n    // Generation of BID \n    //-------------------------------------------------------------------------\n    generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n            bvalid_wr_cnt_r   <= 0;\n            bvalid_rd_cnt_r   <= 0;\n\tend else begin\n          // STORE AWID IN AN ARRAY\n          if(bvalid_c == 1'b1) begin\n            bvalid_wr_cnt_r  <= bvalid_wr_cnt_r + 1;\n          end\n\t  // generate BID FROM AWID ARRAY\n\t  bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t  S_AXI_BID       <= axi_bid_array[bvalid_rd_cnt_c];\n        end       \n    end\n    \n    assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n    \n    //-------------------------------------------------------------------------\n    // Storing AWID for generation of BID\n    //-------------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n      if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n      end\n    end\n  \n  end\n  endgenerate\n\n  assign S_AXI_BVALID   =  bvalid_r;\n  assign S_AXI_AWREADY  =  aw_ready_r;\n\n  endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_4\n# (\n    //// AXI Interface related parameters start here\n    parameter  C_INTERFACE_TYPE           = 0,\n    parameter  C_AXI_TYPE                 = 0,\n    parameter  C_AXI_SLAVE_TYPE           = 0,\n    parameter  C_MEMORY_TYPE              = 0,\n    parameter  C_WRITE_WIDTH_A            = 4,\n    parameter  C_WRITE_DEPTH_A            = 32,\n    parameter  C_ADDRA_WIDTH              = 12,\n    parameter  C_AXI_PIPELINE_STAGES      = 0,\n    parameter  C_AXI_ARADDR_WIDTH         = 12,\n    parameter  C_HAS_AXI_ID               = 0,\n    parameter  C_AXI_ID_WIDTH             = 4,\n    parameter  C_ADDRB_WIDTH              = 12\n    )\n   (\n\n    //// AXI Global Signals\n    input S_ACLK,\n    input S_ARESETN,\n    //// AXI Full/Lite Slave Read (Read side)\n    input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n    input [7:0] S_AXI_ARLEN,\n    input [2:0] S_AXI_ARSIZE,\n    input [1:0] S_AXI_ARBURST,\n    input S_AXI_ARVALID,\n    output S_AXI_ARREADY,\n    output S_AXI_RLAST, \n    output S_AXI_RVALID,\n    input S_AXI_RREADY,\n    input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n    output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n    //// AXI Full/Lite Read Address Signals to BRAM\n    output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n    output S_AXI_RD_EN\n    );\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n  localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n                       ((C_WRITE_WIDTH_A==16)?1:\n                       ((C_WRITE_WIDTH_A==32)?2:\n                       ((C_WRITE_WIDTH_A==64)?3:\n                       ((C_WRITE_WIDTH_A==128)?4:\n                       ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n  reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n  wire addr_en_c; \n  wire rd_en_c; \n  wire incr_addr_c; \n  wire single_trans_c; \n  wire dec_alen_c; \n  wire mux_sel_c; \n  wire r_last_c; \n  wire r_last_int_c; \n  wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n  reg [7:0] arlen_int_r=0; \n  reg [7:0] arlen_cntr=8'h01; \n  reg [1:0] arburst_int_c=0; \n  reg [1:0] arburst_int_r=0; \n  reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n        C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n  integer num_of_bytes_c           = 0;\n  integer total_bytes              = 0;\n  integer num_of_bytes_r           = 0;\n  integer wrap_base_addr_r         = 0;\n  integer wrap_boundary_r          = 0;\n\n  reg [7:0] arlen_int_c=0;                  \n  integer total_bytes_c            = 0;\n  integer wrap_base_addr_c         = 0;\n  integer wrap_boundary_c          = 0;\n\n  assign dec_alen_c        = incr_addr_c | r_last_int_c;\n\n\n  read_netlist_v8_4\n  #(.C_AXI_TYPE      (1),\n    .C_ADDRB_WIDTH   (C_ADDRB_WIDTH)) \n    axi_read_fsm (\n    .S_AXI_INCR_ADDR(incr_addr_c),\n    .S_AXI_ADDR_EN(addr_en_c),\n    .S_AXI_SINGLE_TRANS(single_trans_c),\n    .S_AXI_MUX_SEL(mux_sel_c),\n    .S_AXI_R_LAST(r_last_c),\n    .S_AXI_R_LAST_INT(r_last_int_c),\n\n    //// AXI Global Signals\n    .S_ACLK(S_ACLK),\n    .S_ARESETN(S_ARESETN),\n    //// AXI Full/Lite Slave Read (Read side)\n    .S_AXI_ARLEN(S_AXI_ARLEN),\n    .S_AXI_ARVALID(S_AXI_ARVALID),\n    .S_AXI_ARREADY(S_AXI_ARREADY),\n    .S_AXI_RLAST(S_AXI_RLAST),\n    .S_AXI_RVALID(S_AXI_RVALID),\n    .S_AXI_RREADY(S_AXI_RREADY),\n    //// AXI Full/Lite Read Address Signals to BRAM\n    .S_AXI_RD_EN(rd_en_c)\n      );\n\n   always@(*) begin\n     num_of_bytes_c   = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n     total_bytes      = (num_of_bytes_r)*(arlen_int_r+1);\n     wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n     wrap_boundary_r  = wrap_base_addr_r+total_bytes;\n\n     //////// combinatorial from interface\n     arlen_int_c      = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n     total_bytes_c    = (num_of_bytes_c)*(arlen_int_c+1);\n     wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n     wrap_boundary_c  = wrap_base_addr_c+total_bytes_c;\n     \n     arburst_int_c    = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);  \n   end\n\n  ////-------------------------------------------------------------------------\n  //// BMG address generation\n  ////-------------------------------------------------------------------------\n   always @(posedge S_ACLK or S_ARESETN) begin\n     if (S_ARESETN == 1'b1) begin\n        araddr_reg \t<= 0;\n   \tarburst_int_r   <= 0;\n\tnum_of_bytes_r  <= 0;\n     end else begin\n        if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t      arburst_int_r    <= arburst_int_c;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      if (arburst_int_c == 2'b10) begin\n\t\t    if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t      araddr_reg <= wrap_base_addr_c;\n\t\t    end else begin\n\t\t      araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t    end\n\t      end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t    araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t      end\n\n        end else if (addr_en_c == 1'b1) begin\n              araddr_reg       <= S_AXI_ARADDR;\n\t      num_of_bytes_r   <= num_of_bytes_c;\n\t      arburst_int_r    <= arburst_int_c;\n\t    end else if (incr_addr_c == 1'b1) begin\n\t      if (arburst_int_r == 2'b10) begin\n\t     \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t     \t  araddr_reg <= wrap_base_addr_r;\n\t     \tend else begin\n\t     \t  araddr_reg <= araddr_reg + num_of_bytes_r;\n\t     \tend\n\t      end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t      araddr_reg   <= araddr_reg + num_of_bytes_r;\n\t      end\n         end\n         end\n   end\n\nassign araddr_out   =  ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n  \n\n ////-----------------------------------------------------------------------\n    //// Counter to generate r_last_int_c from registered ARLEN  - AXI FULL FSM\n ////-----------------------------------------------------------------------\n    always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          arlen_cntr        <= 8'h01;\n\t    arlen_int_r     <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n            arlen_cntr      <= S_AXI_ARLEN - 1'b1;\n\t  end else if (addr_en_c == 1'b1) begin\n\t    arlen_int_r     <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t    arlen_cntr      <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t  end else if (dec_alen_c == 1'b1) begin\n            arlen_cntr      <= arlen_cntr - 1'b1 ;\n          end\n\t  else begin\n\t        arlen_cntr      <= arlen_cntr;\n\t  end\n     end\n   end\n\n    assign r_last_int_c          = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n    ////------------------------------------------------------------------------\n    //// AXI FULL FSM\n    //// Mux Selection of ARADDR\n    //// ARADDR is driven out from the read fsm based on the mux_sel_c\n    //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n    //// given out to BRAM\n    ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n    \n    ////------------------------------------------------------------------------\n    //// Assign output signals  - AXI FULL FSM\n    ////------------------------------------------------------------------------\n    assign S_AXI_RD_EN = rd_en_c;\n\n    generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n      always @(posedge S_ACLK or S_ARESETN) begin\n        if (S_ARESETN == 1'b1) begin\n          S_AXI_RID <= 0;\n          ar_id_r   <= 0;\n\tend else begin\n          if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n             S_AXI_RID <= S_AXI_ARID;\n             ar_id_r <= S_AXI_ARID;\n          end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t     ar_id_r <= S_AXI_ARID;\n          end else if (rd_en_c == 1'b1) begin\n             S_AXI_RID <= ar_id_r;\n          end\n        end\n     end \n     end \n   endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_4\n  #(parameter C_DATA_WIDTH = 8\n   )(\n    input   ACLK,\n    input   ARESET,\n    input   S_VALID,\n    output  S_READY,\n    input   [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n    output  M_VALID,\n    input   M_READY,\n    output  reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n    );\n\n    reg  [C_DATA_WIDTH-1:0] STORAGE_DATA;\n    wire S_READY_I;\n    reg  M_VALID_I;\n    reg  [1:0] ARESET_D;\n\n      //assign local signal to its output signal\n      assign S_READY = S_READY_I;\n      assign M_VALID = M_VALID_I;\n\n   always @(posedge ACLK) begin\n\t  ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n      \n      //Save payload data whenever we have a transaction on the slave side\n   always @(posedge ACLK or ARESET) begin\n        if (ARESET == 1'b1) begin\n  \t    STORAGE_DATA <= 0;\n\tend else begin\n\t  if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n  \t    STORAGE_DATA <= S_PAYLOAD_DATA;\n  \t  end\n  \tend\n     end\n\n   always @(posedge ACLK) begin\n     M_PAYLOAD_DATA = STORAGE_DATA;\n   end\n      \n      //M_Valid set to high when we have a completed transfer on slave side\n      //Is removed on a M_READY except if we have a new transfer on the slave side\n       \n   always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n  \t    M_VALID_I <= 1'b0;\n\tend else begin\n\t  if (S_VALID == 1'b1) begin\n\t    //Always set M_VALID_I when slave side is valid\n            M_VALID_I <= 1'b1;\n\t  end else if (M_READY == 1'b1 ) begin\n\t    //Clear (or keep) when no slave side is valid but master side is ready\n\t    M_VALID_I <= 1'b0;\n\t  end\n\tend\n      end\n\n      //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n      assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n  endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_4_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_output_stage\n  #(parameter C_FAMILY              = \"virtex7\",\n    parameter C_XDEVICEFAMILY       = \"virtex7\",\n    parameter C_RST_TYPE            = \"SYNC\",\n    parameter C_HAS_RST             = 0,\n    parameter C_RSTRAM              = 0,\n    parameter C_RST_PRIORITY        = \"CE\",\n    parameter C_INIT_VAL            = \"0\",\n    parameter C_HAS_EN              = 0,\n    parameter C_HAS_REGCE           = 0,\n    parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_MEM_OUTPUT_REGS = 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter C_USE_ECC             = 0,\n    parameter NUM_STAGES            = 1,\n\tparameter C_EN_ECC_PIPE         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input                         RST,\n   input                         EN,\n   input                         REGCE,\n   input      [C_DATA_WIDTH-1:0] DIN_I,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN_I,\n   input                         DBITERR_IN_I,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN_I,\n   input                         ECCPIPECE,    \n   output reg [C_ADDRB_WIDTH-1:0]    RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RST               : Determines the presence of the RST port\n  // C_RSTRAM                : Determines if special reset behavior is used\n  // C_RST_PRIORITY          : Determines the priority between CE and SR\n  // C_INIT_VAL              : Initialization value\n  // C_HAS_EN                : Determines the presence of the EN port\n  // C_HAS_REGCE             : Determines the presence of the REGCE port\n  // C_DATA_WIDTH            : Memory write/read width\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS   : Designates the use of a register at the output \n  //                           of the RAM primitive\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // NUM_STAGES              : Determines the number of output stages\n  // FLOP_DELAY              : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // RST    : Reset input to reset memory outputs to a user-defined \n  //           reset state\n  // EN     : Enable all read and write operations\n  // REGCE  : Register Clock Enable to control each pipeline output\n  //           register stages\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n//  Fix for CR-509792\n\n  localparam REG_STAGES  = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n  \n  // Declare the pipeline registers \n  // (includes mem output reg, mux pipeline stages, and mux output reg)\n  reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n  reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n  reg [REG_STAGES-1:0] sbiterr_regs;\n  reg [REG_STAGES-1:0] dbiterr_regs;\n\n  reg [C_DATA_WIDTH*8-1:0]          init_str = C_INIT_VAL;\n  reg [C_DATA_WIDTH-1:0]            init_val ;\n\n  //*********************************************\n  // Wire off optional inputs based on parameters\n  //*********************************************\n  wire                              en_i;\n  wire                              regce_i;\n  wire                              rst_i;\n  \n  // Internal signals\n  reg [C_DATA_WIDTH-1:0]     DIN;\n  reg [C_ADDRB_WIDTH-1:0]    RDADDRECC_IN;\n  reg                        SBITERR_IN;\n  reg                        DBITERR_IN;\n\n\n  // Internal enable for output registers is tied to user EN or '1' depending\n  // on parameters\n  assign   en_i    = (C_HAS_EN==0 || EN);\n\n  // Internal register enable for output registers is tied to user REGCE, EN or\n  // '1' depending on parameters\n  // For V4 ECC, REGCE is always 1\n  // Virtex-4 ECC Not Yet Supported\n  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n  \n  //Internal SRR is tied to user RST or '0' depending on parameters\n  assign   rst_i   = (C_HAS_RST==1) && RST;\n\n  //****************************************************\n  // Power on: load up the output registers and latches\n  //****************************************************\n  initial begin\n    if (!($sscanf(init_str, \"%h\", init_val))) begin\n      init_val = 0;\n    end\n    DOUT = init_val;\n    RDADDRECC = 0;\n    SBITERR = 1'b0;\n    DBITERR = 1'b0;\n\tDIN     = {(C_DATA_WIDTH){1'b0}};\n    RDADDRECC_IN = 0;\n    SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n    out_regs = {(REG_STAGES+1){init_val}};\n    rdaddrecc_regs = 0;\n    sbiterr_regs = {(REG_STAGES+1){1'b0}};\n    dbiterr_regs = {(REG_STAGES+1){1'b0}};\n  end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n  generate if (NUM_STAGES == 0) begin : zero_stages\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n    always @* begin\n      DIN = DIN_I;\n\t  SBITERR_IN = SBITERR_IN_I;\n      DBITERR_IN = DBITERR_IN_I;\n      RDADDRECC_IN = RDADDRECC_IN_I;\n    end\n  end\n  endgenerate\n\n  generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n    always @(posedge CLK) begin\n      if(ECCPIPECE == 1) begin\n\t    DIN <= #FLOP_DELAY DIN_I;\n        SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n        DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n        RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n      end\n\tend\n  end\n  endgenerate\n\n\n  //***********************************************\n  // NUM_STAGES = 1 \n  // (Mem Output Reg only or Mux Output Reg only)\n  //***********************************************\n\n  // Possible valid combinations: \n  // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n  //   +-----------------------------------------+\n  //   |   C_RSTRAM_*   |  Reset Behavior        |\n  //   +----------------+------------------------+\n  //   |       0        |   Normal Behavior      |\n  //   +----------------+------------------------+\n  //   |       1        |  Special Behavior      |\n  //   +----------------+------------------------+\n  //\n  // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n  // Special = EN gates reset, as in the case of S3ADSP.\n\n  generate if (NUM_STAGES == 1 && \n                 (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n                  C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n  begin : one_stages_norm\n\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end else begin             //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY DIN;\n            RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n            SBITERR <= #FLOP_DELAY SBITERR_IN;\n            DBITERR <= #FLOP_DELAY DBITERR_IN;\n          end //Output signal assignments\n        end //end Priority conditions\n    end //end RST Type conditions\n  end //end one_stages_norm generate statement\n  endgenerate\n\n  // Special Reset Behavior for S3ADSP\n  generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n  begin : one_stage_splbhv\n    always @(posedge CLK) begin\n      if (en_i && rst_i) begin\n        DOUT <= #FLOP_DELAY init_val;\n      end else if (regce_i && !rst_i) begin\n        DOUT <= #FLOP_DELAY DIN;\n      end //Output signal assignments\n    end  //end CLK\n  end //end one_stage_splbhv generate statement\n  endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n //              or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n //              or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n       //Asynchronous Reset\n      always @(posedge CLK) begin\n        if (C_RST_PRIORITY == \"CE\") begin  //REGCE has priority\n          if (regce_i && rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end else begin                     //RST has priority\n          if (rst_i) begin\n            DOUT    <= #FLOP_DELAY init_val;\n            RDADDRECC <= #FLOP_DELAY 0;\n            SBITERR <= #FLOP_DELAY 1'b0;\n            DBITERR <= #FLOP_DELAY 1'b0;\n          end else if (regce_i) begin\n            DOUT    <= #FLOP_DELAY\n                          out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n            RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n            SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n            DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n          end //Output signal assignments\n        end   //end Priority conditions\n         // Shift the data through the output stages\n         if (en_i) begin\n           out_regs     <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n           rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n           sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n           dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n         end\n      end  //end CLK\n  end //end multi_stage generate statement\n  endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_4_4_softecc_output_reg_stage\n  #(parameter C_DATA_WIDTH          = 32,\n    parameter C_ADDRB_WIDTH         = 10,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_USE_SOFTECC         = 0,\n    parameter FLOP_DELAY            = 100\n  )\n  (\n   input                         CLK,\n   input      [C_DATA_WIDTH-1:0] DIN,\n   output reg [C_DATA_WIDTH-1:0] DOUT,\n   input                         SBITERR_IN,\n   input                         DBITERR_IN,\n   output reg                    SBITERR,\n   output reg                    DBITERR,\n   input      [C_ADDRB_WIDTH-1:0]             RDADDRECC_IN,\n   output reg [C_ADDRB_WIDTH-1:0]             RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_DATA_WIDTH                  : Memory write/read width\n  // C_ADDRB_WIDTH                 : Width of the ADDRB input port\n  // C_HAS_SOFTECC_OUTPUT_REGS_B   : Designates the use of a register at the output \n  //                                 of the RAM primitive\n  // C_USE_SOFTECC                 : Determines if the Soft ECC feature is used or\n  //                                 not. Only applicable Spartan-6\n  // FLOP_DELAY                    : Constant delay for register assignments\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLK    : Clock to synchronize all read and write operations\n  // DIN    : Data input to the Output stage.\n  // DOUT   : Final Data output\n  // SBITERR_IN    : SBITERR input signal to the Output stage.\n  // SBITERR       : Final SBITERR Output signal.\n  // DBITERR_IN    : DBITERR input signal to the Output stage.\n  // DBITERR       : Final DBITERR Output signal.\n  // RDADDRECC_IN  : RDADDRECC input signal to the Output stage.\n  // RDADDRECC     : Final RDADDRECC Output signal.\n  //////////////////////////////////////////////////////////////////////////\n\n  reg [C_DATA_WIDTH-1:0]           dout_i       = 0;\n  reg                              sbiterr_i    = 0;\n  reg                              dbiterr_i    = 0;\n  reg [C_ADDRB_WIDTH-1:0]          rdaddrecc_i  = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n    always @* begin\n      DOUT = DIN;\n      RDADDRECC = RDADDRECC_IN;\n      SBITERR = SBITERR_IN;\n      DBITERR = DBITERR_IN;\n    end\n  end\n  endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n      always @(posedge CLK) begin\n      dout_i <= #FLOP_DELAY DIN;\n      rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n      sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n      dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n      end\n\n      always @* begin\n      DOUT = dout_i;\n      RDADDRECC = rdaddrecc_i;\n      SBITERR = sbiterr_i;\n      DBITERR = dbiterr_i;\n      end //end always\n      end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4_mem_module\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_USE_ECC                 = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter FLOP_DELAY                = 100,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_DISABLE_WARN_BHV_RANGE  = 0\n  )\n  (input                       CLKA,\n   input                       RSTA,\n   input                       ENA,\n   input                       REGCEA,\n   input [C_WEA_WIDTH-1:0]     WEA,\n   input [C_ADDRA_WIDTH-1:0]   ADDRA,\n   input [C_WRITE_WIDTH_A-1:0] DINA,\n   output [C_READ_WIDTH_A-1:0] DOUTA,\n   input                       CLKB,\n   input                       RSTB,\n   input                       ENB,\n   input                       REGCEB,\n   input [C_WEB_WIDTH-1:0]     WEB,\n   input [C_ADDRB_WIDTH-1:0]   ADDRB,\n   input [C_WRITE_WIDTH_B-1:0] DINB,\n   output [C_READ_WIDTH_B-1:0] DOUTB,\n   input                       INJECTSBITERR,\n   input                       INJECTDBITERR,\n   input                       ECCPIPECE,\n   input                       SLEEP,\n   output                      SBITERR,\n   output                      DBITERR,\n   output [C_ADDRB_WIDTH-1:0]  RDADDRECC\n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_4_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_4_4_xst.v nor present in the instantiation template\n// coregen generates\n  \n  //***************************************************************************\n  // constants for the core behavior\n  //***************************************************************************\n  // file handles for logging\n  //--------------------------------------------------\n  localparam ADDRFILE           = 32'h8000_0001; //stdout for addr out of range\n  localparam COLLFILE           = 32'h8000_0001; //stdout for coll detection\n  localparam ERRFILE            = 32'h8000_0001; //stdout for file I/O errors\n\n  // other constants\n  //--------------------------------------------------\n  localparam COLL_DELAY         = 100;  // 100 ps\n\n  // locally derived parameters to determine memory shape\n  //-----------------------------------------------------\n\n  localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n  localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n             C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n  localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n             C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n  localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n             MIN_WIDTH_A : MIN_WIDTH_B;\n\n  localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n             C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n  localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n             C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n  localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n             MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n  // locally derived parameters to assist memory access\n  //----------------------------------------------------\n  // Calculate the width ratios of each port with respect to the narrowest\n  // port\n  localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_A  = C_READ_WIDTH_A/MIN_WIDTH;\n  localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n  localparam READ_WIDTH_RATIO_B  = C_READ_WIDTH_B/MIN_WIDTH;\n\n  // To modify the LSBs of the 'wider' data to the actual\n  // address value\n  //----------------------------------------------------\n  localparam WRITE_ADDR_A_DIV  = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n  localparam READ_ADDR_A_DIV   = C_READ_WIDTH_A/MIN_WIDTH_A;\n  localparam WRITE_ADDR_B_DIV  = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n  localparam READ_ADDR_B_DIV   = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n  // If byte writes aren't being used, make sure BYTE_SIZE is not\n  // wider than the memory elements to avoid compilation warnings\n  localparam BYTE_SIZE   = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n  // The memory\n  reg [MIN_WIDTH-1:0]      memory [0:MAX_DEPTH-1];\n  reg [MIN_WIDTH-1:0]      temp_mem_array [0:MAX_DEPTH-1];\n  reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n  // ECC error arrays\n  reg                      sbiterr_arr [0:MAX_DEPTH-1];\n  reg                      dbiterr_arr [0:MAX_DEPTH-1];\n\n  reg                 softecc_sbiterr_arr [0:MAX_DEPTH-1];\n  reg                 softecc_dbiterr_arr [0:MAX_DEPTH-1];\n  // Memory output 'latches'\n  reg [C_READ_WIDTH_A-1:0] memory_out_a;\n  reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n  // ECC error inputs and outputs from output_stage module:\n  reg                      sbiterr_in;\n  wire                     sbiterr_sdp;\n  reg                      dbiterr_in;\n  wire                     dbiterr_sdp;\n\n  wire [C_READ_WIDTH_B-1:0]            dout_i;\n  wire                     dbiterr_i;\n  wire                     sbiterr_i;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_i;\n\n  reg [C_ADDRB_WIDTH-1:0]  rdaddrecc_in;\n  wire [C_ADDRB_WIDTH-1:0]  rdaddrecc_sdp;\n\n  // Reset values\n  reg [C_READ_WIDTH_A-1:0] inita_val;\n  reg [C_READ_WIDTH_B-1:0] initb_val;\n\n  // Collision detect\n  reg                      is_collision;\n  reg                      is_collision_a, is_collision_delay_a;\n  reg                      is_collision_b, is_collision_delay_b;\n\n  // Temporary variables for initialization\n  //---------------------------------------\n  integer                  status;\n  integer                  initfile;\n  integer                  meminitfile;\n  // data input buffer\n  reg [C_WRITE_WIDTH_A-1:0]    mif_data;\n  reg [C_WRITE_WIDTH_A-1:0]    mem_data;\n  // string values in hex\n  reg [C_READ_WIDTH_A*8-1:0]   inita_str       = C_INITA_VAL;\n  reg [C_READ_WIDTH_B*8-1:0]   initb_str       = C_INITB_VAL;\n  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;\n  // initialization filename\n  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;\n  reg [1023*8-1:0]             mem_init_file_str    = C_INIT_FILE;\n\n\n  //Constants used to calculate the effective address widths for each of the \n  //four ports. \n  integer cnt = 1;\n  integer write_addr_a_width, read_addr_a_width;\n  integer write_addr_b_width, read_addr_b_width;\n\n    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY==\"virtexuplushbm\"?\"virtex7\":(C_FAMILY==\"zynquplusrfsoc\"?\"virtex7\":(C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))))));\n\n  // Internal configuration parameters\n  //---------------------------------------------\n  localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n  localparam IS_ROM      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n  localparam HAS_A_WRITE = (!IS_ROM);\n  localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n  localparam HAS_A_READ  = (C_MEM_TYPE!=1);\n  localparam HAS_B_READ  = (!SINGLE_PORT);\n  localparam HAS_B_PORT  = (HAS_B_READ || HAS_B_WRITE);\n\n  // Calculate the mux pipeline register stages for Port A and Port B\n  //------------------------------------------------------------------\n  localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n                             C_MUX_PIPELINE_STAGES : 0;\n  \n  // Calculate total number of register stages in the core\n  // -----------------------------------------------------\n  localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n  localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n  wire                   ena_i;\n  wire                   enb_i;\n  wire                   reseta_i;\n  wire                   resetb_i;\n  wire [C_WEA_WIDTH-1:0] wea_i;\n  wire [C_WEB_WIDTH-1:0] web_i;\n  wire                   rea_i;\n  wire                   reb_i;\n  wire                   rsta_outp_stage;\n  wire                   rstb_outp_stage;\n  // ECC SBITERR/DBITERR Outputs\n  //  The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n  //  For Virtex-5, these outputs will be tied to 0.\n   assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n   assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n   assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n  // This effectively wires off optional inputs\n  assign ena_i = (C_HAS_ENA==0) || ENA;\n  assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n  // To match RTL : In RTL, write enable of the primitive is tied to all 1's and\n  // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the\n  // write operation depends on both enable and write enable. So, the below code\n  // which is actually doing the write operation only on enable ignoring the wea\n  // is removed to be in consistent with RTL.\n  // To Fix CR855535 (The fix to this CR is reverted to match RTL)\n  //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n  assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n  assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n  assign rea_i = (HAS_A_READ)  ? ena_i : 'b0;\n  assign reb_i = (HAS_B_READ)  ? enb_i : 'b0;\n\n  // These signals reset the memory latches\n\n  assign reseta_i = \n     ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n      (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n  assign resetb_i = \n     ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n      (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n  // Tasks to access the memory\n  //---------------------------\n  //**************\n  // write_a\n  //**************\n  task write_a\n    (input  reg [C_ADDRA_WIDTH-1:0]   addr,\n     input  reg [C_WEA_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_A-1:0] data,\n     input  inj_sbiterr,\n     input  inj_dbiterr);\n    reg [C_WRITE_WIDTH_A-1:0] current_contents;\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_A_DIV);\n      if (address >= C_WRITE_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEA) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_A == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_A + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEA_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Insert double bit errors:\n        if (C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399            \n            current_contents[0] = !(current_contents[30]);\n            current_contents[1] = !(current_contents[62]);\n            \n            /*current_contents[0] = !(current_contents[0]);\n            current_contents[1] = !(current_contents[1]);*/\n          end\n        end\n    \n        // Insert softecc double bit errors:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n            doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n            doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n            current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n          end\n        end\n    \n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_A == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_A + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n\n        // Store the address at which error is injected:\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            sbiterr_arr[addr] = 1;\n          end else begin\n            sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            dbiterr_arr[addr] = 1;\n          end else begin\n            dbiterr_arr[addr] = 0;\n          end\n        end\n\n        // Store the address at which softecc error is injected:\n        if (C_USE_SOFTECC == 1) begin\n          if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n            (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n          begin\n            softecc_sbiterr_arr[addr] = 1;\n          end else begin\n            softecc_sbiterr_arr[addr] = 0;\n          end\n  \n          if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n            softecc_dbiterr_arr[addr] = 1;\n          end else begin\n            softecc_dbiterr_arr[addr] = 0;\n          end\n        end\n\n      end\n    end\n  endtask\n\n  //**************\n  // write_b\n  //**************\n  task write_b\n    (input  reg [C_ADDRB_WIDTH-1:0]   addr,\n     input  reg [C_WEB_WIDTH-1:0]     byte_en,\n     input  reg [C_WRITE_WIDTH_B-1:0] data);\n    reg [C_WRITE_WIDTH_B-1:0] current_contents;\n    reg [C_ADDRB_WIDTH-1:0]   address;\n    integer i;\n    begin\n      // Shift the address by the ratio\n      address = (addr/WRITE_ADDR_B_DIV);\n      if (address >= C_WRITE_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Write\",\n                    C_CORENAME, addr);\n        end\n\n      // valid address\n      end else begin\n\n        // Combine w/ byte writes\n        if (C_USE_BYTE_WEB) begin\n\n          // Get the current memory contents\n          if (WRITE_WIDTH_RATIO_B == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            current_contents = memory[address];\n          end else begin\n            for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n              current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n                = memory[address*WRITE_WIDTH_RATIO_B + i];\n            end\n          end\n\n          // Apply incoming bytes\n          if (C_WEB_WIDTH == 1) begin\n            // Workaround for IUS 5.5 part-select issue\n            if (byte_en[0]) begin\n              current_contents = data;\n            end\n          end else begin\n            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n              if (byte_en[i]) begin\n                current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n                  = data[BYTE_SIZE*i+:BYTE_SIZE];\n              end\n            end\n          end\n\n        // No byte-writes, overwrite the whole word\n        end else begin\n          current_contents = data;\n        end\n\n        // Write data to memory\n        if (WRITE_WIDTH_RATIO_B == 1) begin\n          // Workaround for IUS 5.5 part-select issue\n          memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n        end else begin\n          for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n            memory[address*WRITE_WIDTH_RATIO_B + i]\n              = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n          end\n        end\n      end\n    end\n  endtask\n\n  //**************\n  // read_a\n  //**************\n  task read_a\n    (input reg [C_ADDRA_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRA_WIDTH-1:0] address;\n    integer i;\n  begin\n\n    if (reset) begin\n      memory_out_a <= #FLOP_DELAY inita_val;\n    end else begin\n      // Shift the address by the ratio\n      address = (addr/READ_ADDR_A_DIV);\n      if (address >= C_READ_DEPTH_A) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for A Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_a <= #FLOP_DELAY 'bX;\n      // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_A==1) begin\n          memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n            memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n          end\n        end //end READ_WIDTH_RATIO_A==1 loop\n\n      end //end valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // read_b\n  //**************\n  task read_b\n    (input reg [C_ADDRB_WIDTH-1:0] addr,\n     input reg reset);\n    reg [C_ADDRB_WIDTH-1:0] address;\n    integer i;\n    begin\n\n    if (reset) begin\n      memory_out_b <= #FLOP_DELAY initb_val;\n      sbiterr_in   <= #FLOP_DELAY 1'b0;\n      dbiterr_in   <= #FLOP_DELAY 1'b0;\n      rdaddrecc_in <= #FLOP_DELAY 0;\n    end else begin\n      // Shift the address\n      address = (addr/READ_ADDR_B_DIV);\n      if (address >= C_READ_DEPTH_B) begin\n        if (!C_DISABLE_WARN_BHV_RANGE) begin\n          $fdisplay(ADDRFILE,\n                    \"%0s WARNING: Address %0h is outside range for B Read\",\n                    C_CORENAME, addr);\n        end\n        memory_out_b <= #FLOP_DELAY 'bX;\n        sbiterr_in <= #FLOP_DELAY 1'bX;\n        dbiterr_in <= #FLOP_DELAY 1'bX;\n        rdaddrecc_in <= #FLOP_DELAY 'bX;\n        // valid address\n      end else begin\n        if (READ_WIDTH_RATIO_B==1) begin\n          memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n        end else begin\n          // Increment through the 'partial' words in the memory\n          for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n            memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n              <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n          end\n        end\n\n        if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n         end else  if (C_USE_SOFTECC == 1) begin\n          rdaddrecc_in <= #FLOP_DELAY addr;\n          if (softecc_sbiterr_arr[addr] == 1) begin\n            sbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            sbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n\n          if (softecc_dbiterr_arr[addr] == 1) begin\n            dbiterr_in <= #FLOP_DELAY 1'b1;\n          end else begin\n            dbiterr_in <= #FLOP_DELAY 1'b0;\n          end\n        end else begin\n          rdaddrecc_in <= #FLOP_DELAY 0;\n          dbiterr_in <= #FLOP_DELAY 1'b0;\n          sbiterr_in <= #FLOP_DELAY 1'b0;\n        end //end SOFTECC Loop\n      end //end Valid address loop\n    end //end reset-data assignment loops\n  end\n  endtask\n\n  //**************\n  // reset_a\n  //**************\n  task reset_a (input reg reset);\n  begin\n    if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n  end\n  endtask\n\n  //**************\n  // reset_b\n  //**************\n  task reset_b (input reg reset);\n  begin\n    if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n  end\n  endtask\n\n  //**************\n  // init_memory\n  //**************\n  task init_memory;\n    integer i, j, addr_step;\n    integer status;\n    reg [C_WRITE_WIDTH_A-1:0] default_data;\n    begin\n      default_data = 0;\n\n      //Display output message indicating that the behavioral model is being \n      //initialized\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n      // Convert the default to hex\n      if (C_USE_DEFAULT_DATA) begin\n        if (default_data_str == \"\") begin\n         $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n          $finish;\n        end else begin\n          status = $sscanf(default_data_str, \"%h\", default_data);\n          if (status == 0) begin\n            $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n                                \"from C_DEFAULT_DATA: %0s\"},\n                      C_CORENAME, C_DEFAULT_DATA);\n            $finish;\n          end\n        end\n      end\n\n      // Step by WRITE_ADDR_A_DIV through the memory via the\n      // Port A write interface to hit every location once\n      addr_step = WRITE_ADDR_A_DIV;\n\n      // 'write' to every location with default (or 0)\n      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n      end\n\n      // Get specialized data from the MIF file\n      if (C_LOAD_INIT_FILE) begin\n        if (init_file_str == \"\") begin\n          $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n                    C_CORENAME);\n          $finish;\n        end else begin\n          initfile = $fopen(init_file_str, \"r\");\n          if (initfile == 0) begin\n            $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                \"C_INIT_FILE_NAME: %0s!\"},\n                      C_CORENAME, init_file_str);\n            $finish;\n          end else begin\n            // loop through the mif file, loading in the data\n            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n              status = $fscanf(initfile, \"%b\", mif_data);\n              if (status > 0) begin\n                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n              end\n            end\n            $fclose(initfile);\n          end //initfile\n        end //init_file_str\n      end //C_LOAD_INIT_FILE\n\n\n      if (C_USE_BRAM_BLOCK) begin\n            // Get specialized data from the MIF file\n            if (C_INIT_FILE != \"NONE\") begin\n              if (mem_init_file_str == \"\") begin\n                $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n                          C_CORENAME);\n                $finish;\n              end else begin\n                meminitfile = $fopen(mem_init_file_str, \"r\");\n                if (meminitfile == 0) begin\n                  $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n                                      \"C_INIT_FILE: %0s!\"},\n                            C_CORENAME, mem_init_file_str);\n                  $finish;\n                end else begin\n                  // loop through the mif file, loading in the data\n                    $readmemh(mem_init_file_str, memory );\n                      for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n                      end \n                  $fclose(meminitfile);\n                end //meminitfile\n              end //mem_init_file_str\n            end //C_INIT_FILE\n      end //C_USE_BRAM_BLOCK\n\n      //Display output message indicating that the behavioral model is done \n      //initializing\n      if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n          $display(\" Block Memory Generator data initialization complete.\");\n    end\n  endtask\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n\n  //*******************\n  // collision_check\n  //*******************\n  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n                                    input integer iswrite_a,\n                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,\n                                    input integer iswrite_b);\n    reg c_aw_bw, c_aw_br, c_ar_bw;\n    integer scaled_addra_to_waddrb_width;\n    integer scaled_addrb_to_waddrb_width;\n    integer scaled_addra_to_waddra_width;\n    integer scaled_addrb_to_waddra_width;\n    integer scaled_addra_to_raddrb_width;\n    integer scaled_addrb_to_raddrb_width;\n    integer scaled_addra_to_raddra_width;\n    integer scaled_addrb_to_raddra_width;\n\n\n\n    begin\n\n    c_aw_bw = 0;\n    c_aw_br = 0;\n    c_ar_bw = 0;\n\n    //If write_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_b_width. Once both are scaled to \n    //write_addr_b_width, compare.\n    scaled_addra_to_waddrb_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_b_width));\n    scaled_addrb_to_waddrb_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n    //If write_addr_a_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to write_addr_a_width. Once both are scaled to \n    //write_addr_a_width, compare.\n    scaled_addra_to_waddra_width  = ((addr_a)/\n                                        2**(C_ADDRA_WIDTH-write_addr_a_width));\n    scaled_addrb_to_waddra_width  = ((addr_b)/\n                                        2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n    //If read_addr_b_width is smaller, scale both addresses to that width for \n    //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_b_width. Once both are scaled to \n    //read_addr_b_width, compare.\n    scaled_addra_to_raddrb_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_b_width));\n    scaled_addrb_to_raddrb_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n    //If read_addr_a_width is smaller, scale both addresses to that width for \n    //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n    //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n    //scale it down to read_addr_a_width. Once both are scaled to \n    //read_addr_a_width, compare.\n    scaled_addra_to_raddra_width  = ((addr_a)/\n                                         2**(C_ADDRA_WIDTH-read_addr_a_width));\n    scaled_addrb_to_raddra_width  = ((addr_b)/\n                                         2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n    //Look for a write-write collision. In order for a write-write\n    //collision to exist, both ports must have a write transaction.\n    if (iswrite_a && iswrite_b) begin\n      if (write_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_bw = 1;\n        end else begin\n          c_aw_bw = 0;\n        end\n      end //width\n    end //iswrite_a and iswrite_b\n\n    //If the B port is reading (which means it is enabled - so could be\n    //a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //to asymmetric write/read ports.\n    if (iswrite_a) begin\n      if (write_addr_a_width > read_addr_b_width) begin\n        if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n    end else begin\n        if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n          c_aw_br = 1;\n        end else begin\n          c_aw_br = 0;\n        end\n      end //width\n    end //iswrite_a\n\n    //If the A port is reading (which means it is enabled - so could be\n    //  a TX_WRITE or TX_READ), then check for a write-read collision).\n    //This could happen whether or not a write-write collision exists due\n    //  to asymmetric write/read ports.\n    if (iswrite_b) begin\n      if (read_addr_a_width > write_addr_b_width) begin\n        if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end else begin\n        if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n          c_ar_bw = 1;\n        end else begin\n          c_ar_bw = 0;\n        end\n      end //width\n    end //iswrite_b\n\n\n\n      collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n    end\n  endfunction\n\n  //*******************************\n  // power on values\n  //*******************************\n  initial begin\n    // Load up the memory\n    init_memory;\n    // Load up the output registers and latches\n    if ($sscanf(inita_str, \"%h\", inita_val)) begin\n      memory_out_a = inita_val;\n    end else begin\n      memory_out_a = 0;\n    end\n    if ($sscanf(initb_str, \"%h\", initb_val)) begin\n      memory_out_b = initb_val;\n    end else begin\n      memory_out_b = 0;\n    end\n\n    sbiterr_in   = 1'b0;\n    dbiterr_in   = 1'b0;\n    rdaddrecc_in = 0;\n\n    // Determine the effective address widths for each of the 4 ports\n    write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n    read_addr_a_width  = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n    write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n    read_addr_b_width  = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n    $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n  end\n\n  //***************************************************************************\n  // These are the main blocks which schedule read and write operations\n  // Note that the reset priority feature at the latch stage is only supported\n  // for Spartan-6. For other families, the default priority at the latch stage\n  // is \"CE\"\n  //***************************************************************************\n      // Synchronous clocks: schedule port operations with respect to\n      // both write operating modes\n  generate\n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        \n        if (rea_i) read_a(ADDRA, reseta_i);\n \n       //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n      always @(posedge CLKA) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n         if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else \n    if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n      always @(posedge CLKA) begin\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n                    \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n      always @(posedge CLKA) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n                    \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if(C_COMMON_CLK) begin: com_clk_sched_default\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n      // Asynchronous clocks: port operation is independent\n  generate\n    if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n          if (rea_i) read_a(ADDRA, reseta_i);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n      always @(posedge CLKA) begin\n        //Read A\n        if (rea_i) read_a(ADDRA, reseta_i);\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n      end\n    end\n    else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n      always @(posedge CLKA) begin\n        //Write A\n        if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n        //Read A\n         if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n      end\n    end\n  endgenerate\n\n  generate \n    if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n      always @(posedge CLKB) begin\n        //Read B\n          if (reb_i) read_b(ADDRB, resetb_i);\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n      end\n    end\n    else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n      always @(posedge CLKB) begin\n        //Write B\n        if (web_i) write_b(ADDRB, web_i, DINB);\n        //Read B\n          if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n      end\n    end\n  endgenerate\n\n  \n  //***************************************************************\n  //  Instantiate the variable depth output register stage module\n  //***************************************************************\n  // Port A\n  \n  assign rsta_outp_stage = RSTA & (~SLEEP);\n\n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTA),\n      .C_RSTRAM                 (C_RSTRAM_A),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_A),\n      .C_INIT_VAL               (C_INITA_VAL),\n      .C_HAS_EN                 (C_HAS_ENA),\n      .C_HAS_REGCE              (C_HAS_REGCEA),\n      .C_DATA_WIDTH             (C_READ_WIDTH_A),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_A),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_A),\n\t  .C_EN_ECC_PIPE            (0),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_a\n        (.CLK         (CLKA),\n         .RST         (rsta_outp_stage),//(RSTA),\n         .EN          (ENA),\n         .REGCE       (REGCEA),\n         .DIN_I       (memory_out_a),\n         .DOUT        (DOUTA),\n         .SBITERR_IN_I  (1'b0),\n         .DBITERR_IN_I  (1'b0),\n         .SBITERR     (),\n         .DBITERR     (),\n         .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n         .RDADDRECC   ()\n        );\n\n  assign rstb_outp_stage = RSTB & (~SLEEP);\n\n  // Port B \n  blk_mem_gen_v8_4_4_output_stage\n    #(.C_FAMILY                 (C_FAMILY),\n      .C_XDEVICEFAMILY          (C_XDEVICEFAMILY),\n      .C_RST_TYPE               (\"SYNC\"),\n      .C_HAS_RST                (C_HAS_RSTB),\n      .C_RSTRAM                 (C_RSTRAM_B),\n      .C_RST_PRIORITY           (C_RST_PRIORITY_B),\n      .C_INIT_VAL               (C_INITB_VAL),\n      .C_HAS_EN                 (C_HAS_ENB),\n      .C_HAS_REGCE              (C_HAS_REGCEB),\n      .C_DATA_WIDTH             (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH            (C_ADDRB_WIDTH),\n      .C_HAS_MEM_OUTPUT_REGS    (C_HAS_MEM_OUTPUT_REGS_B),\n      .C_USE_SOFTECC            (C_USE_SOFTECC),\n      .C_USE_ECC                (C_USE_ECC),\n      .NUM_STAGES               (NUM_OUTPUT_STAGES_B),\n      .C_EN_ECC_PIPE            (C_EN_ECC_PIPE),\n      .FLOP_DELAY               (FLOP_DELAY))\n      reg_b\n        (.CLK         (CLKB),\n         .RST         (rstb_outp_stage),//(RSTB),\n         .EN          (ENB),\n         .REGCE       (REGCEB),\n         .DIN_I       (memory_out_b),\n         .DOUT        (dout_i),\n         .SBITERR_IN_I  (sbiterr_in),\n         .DBITERR_IN_I  (dbiterr_in),\n         .SBITERR     (sbiterr_i),\n         .DBITERR     (dbiterr_i),\n         .RDADDRECC_IN_I (rdaddrecc_in),\n         .ECCPIPECE   (ECCPIPECE),\n         .RDADDRECC   (rdaddrecc_i)\n        );\n\n  //***************************************************************\n  //  Instantiate the Input and Output register stages\n  //***************************************************************\nblk_mem_gen_v8_4_4_softecc_output_reg_stage\n    #(.C_DATA_WIDTH                 (C_READ_WIDTH_B),\n      .C_ADDRB_WIDTH                (C_ADDRB_WIDTH),\n      .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),\n      .C_USE_SOFTECC                (C_USE_SOFTECC),\n      .FLOP_DELAY                   (FLOP_DELAY))\n  has_softecc_output_reg_stage\n      (.CLK       (CLKB),\n      .DIN        (dout_i),\n      .DOUT        (DOUTB),\n      .SBITERR_IN        (sbiterr_i),\n      .DBITERR_IN        (dbiterr_i),\n      .SBITERR        (sbiterr_sdp),\n      .DBITERR        (dbiterr_sdp),\n      .RDADDRECC_IN        (rdaddrecc_i),\n      .RDADDRECC        (rdaddrecc_sdp)\n);\n\n  //****************************************************\n  // Synchronous collision checks\n  //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision = 0;\n        end\n      end else begin\n          is_collision = 0;\n      end\n\n      // If the write port is in READ_FIRST mode, there is no collision\n      if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n        is_collision = 0;\n      end\n      if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n        is_collision = 0;\n      end\n\n      // Only flag if one of the accesses is a write\n      if (is_collision && (wea_i || web_i)) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B %0s address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA,\n                web_i ? \"write\" : \"read\", ADDRB);\n      end\n    end\n\n  //****************************************************\n  // Asynchronous collision checks\n  //****************************************************\n  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n    // Delay A and B addresses in order to mimic setup/hold times\n    wire [C_ADDRA_WIDTH-1:0]  #COLL_DELAY addra_delay = ADDRA;\n    wire [0:0]                #COLL_DELAY wea_delay   = wea_i;\n    wire                      #COLL_DELAY ena_delay   = ena_i;\n    wire [C_ADDRB_WIDTH-1:0]  #COLL_DELAY addrb_delay = ADDRB;\n    wire [0:0]                #COLL_DELAY web_delay   = web_i;\n    wire                      #COLL_DELAY enb_delay   = enb_i;\n\n    // Do the checks w/rt A\n    always @(posedge CLKA) begin\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_a = 0;\n        end\n      end else begin\n        is_collision_a = 0;\n      end\n\n      if (ena_i && enb_delay) begin\n        if(wea_i || web_delay) begin\n          is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n                                                                    web_delay);\n        end else begin\n          is_collision_delay_a = 0;\n        end\n      end else begin\n        is_collision_delay_a = 0;\n      end\n\n      // Only flag if B access is a write\n      if (is_collision_a && web_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n      end else if (is_collision_delay_a && web_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A %0s address: %0h, B write address: %0h\\n\",\n                wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n      end\n\n    end\n\n    // Do the checks w/rt B\n    always @(posedge CLKB) begin\n\n      // Possible collision if both are enabled and the addresses match\n      if (ena_i && enb_i) begin\n        if (wea_i || web_i) begin\n          is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n        end else begin\n          is_collision_b = 0;\n        end\n      end else begin\n        is_collision_b = 0;\n      end\n\n      if (ena_delay && enb_i) begin\n        if (wea_delay || web_i) begin\n          is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n                                                                        web_i);\n        end else begin\n          is_collision_delay_b = 0;\n        end\n      end else begin\n        is_collision_delay_b = 0;\n      end\n\n\n      // Only flag if A access is a write\n      if (is_collision_b && wea_i) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n      end else if (is_collision_delay_b && wea_delay) begin\n        $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n                C_CORENAME, $time);\n        $fwrite(COLLFILE, \"Instance: %m, A write address: %0h, B %s address: %0h\\n\",\n                addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n      end\n\n    end\n  end\n  endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_4_4\n  #(parameter C_CORENAME                = \"blk_mem_gen_v8_4_4\",\n    parameter C_FAMILY                  = \"virtex7\",\n    parameter C_XDEVICEFAMILY           = \"virtex7\",\n    parameter C_ELABORATION_DIR         = \"\",\n    parameter C_INTERFACE_TYPE          = 0,\n    parameter C_USE_BRAM_BLOCK          = 0,\n    parameter C_CTRL_ECC_ALGO           = \"NONE\",\n    parameter C_ENABLE_32BIT_ADDRESS    = 0,\n    parameter C_AXI_TYPE                = 0,\n    parameter C_AXI_SLAVE_TYPE          = 0,\n    parameter C_HAS_AXI_ID              = 0,\n    parameter C_AXI_ID_WIDTH            = 4,\n    parameter C_MEM_TYPE                = 2,\n    parameter C_BYTE_SIZE               = 9,\n    parameter C_ALGORITHM               = 1,\n    parameter C_PRIM_TYPE               = 3,\n    parameter C_LOAD_INIT_FILE          = 0,\n    parameter C_INIT_FILE_NAME          = \"\",\n    parameter C_INIT_FILE               = \"\",\n    parameter C_USE_DEFAULT_DATA        = 0,\n    parameter C_DEFAULT_DATA            = \"0\",\n    //parameter C_RST_TYPE                = \"SYNC\",\n    parameter C_HAS_RSTA                = 0,\n    parameter C_RST_PRIORITY_A          = \"CE\",\n    parameter C_RSTRAM_A                = 0,\n    parameter C_INITA_VAL               = \"0\",\n    parameter C_HAS_ENA                 = 1,\n    parameter C_HAS_REGCEA              = 0,\n    parameter C_USE_BYTE_WEA            = 0,\n    parameter C_WEA_WIDTH               = 1,\n    parameter C_WRITE_MODE_A            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_A           = 32,\n    parameter C_READ_WIDTH_A            = 32,\n    parameter C_WRITE_DEPTH_A           = 64,\n    parameter C_READ_DEPTH_A            = 64,\n    parameter C_ADDRA_WIDTH             = 5,\n    parameter C_HAS_RSTB                = 0,\n    parameter C_RST_PRIORITY_B          = \"CE\",\n    parameter C_RSTRAM_B                = 0,\n    parameter C_INITB_VAL               = \"\",\n    parameter C_HAS_ENB                 = 1,\n    parameter C_HAS_REGCEB              = 0,\n    parameter C_USE_BYTE_WEB            = 0,\n    parameter C_WEB_WIDTH               = 1,\n    parameter C_WRITE_MODE_B            = \"WRITE_FIRST\",\n    parameter C_WRITE_WIDTH_B           = 32,\n    parameter C_READ_WIDTH_B            = 32,\n    parameter C_WRITE_DEPTH_B           = 64,\n    parameter C_READ_DEPTH_B            = 64,\n    parameter C_ADDRB_WIDTH             = 5,\n    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,\n    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,\n    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n    parameter C_MUX_PIPELINE_STAGES     = 0,\n    parameter C_USE_SOFTECC             = 0,\n    parameter C_READ_LATENCY_A          = 1,\n    parameter C_READ_LATENCY_B          = 1,\n    parameter C_USE_ECC                 = 0,\n\tparameter C_EN_ECC_PIPE             = 0,\n    parameter C_HAS_INJECTERR           = 0,\n    parameter C_SIM_COLLISION_CHECK     = \"NONE\",\n    parameter C_COMMON_CLK              = 1,\n    parameter C_DISABLE_WARN_BHV_COLL   = 0,\n\tparameter C_EN_SLEEP_PIN            = 0,\n    parameter C_USE_URAM                = 0,\n    parameter C_EN_RDADDRA_CHG          = 0,\n    parameter C_EN_RDADDRB_CHG          = 0,\n    parameter C_EN_DEEPSLEEP_PIN        = 0,\n    parameter C_EN_SHUTDOWN_PIN         = 0,\n\tparameter C_EN_SAFETY_CKT           = 0,\n\tparameter C_COUNT_36K_BRAM          = \"\",\n\tparameter C_COUNT_18K_BRAM          = \"\",\n\tparameter C_EST_POWER_SUMMARY       = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE  = 0\n\t\n  )\n  (input                       clka,\n   input                       rsta,\n   input                       ena,\n   input                       regcea,\n   input [C_WEA_WIDTH-1:0]     wea,\n   input [C_ADDRA_WIDTH-1:0]   addra,\n   input [C_WRITE_WIDTH_A-1:0] dina,\n   output [C_READ_WIDTH_A-1:0] douta,\n   input                       clkb,\n   input                       rstb,\n   input                       enb,\n   input                       regceb,\n   input [C_WEB_WIDTH-1:0]     web,\n   input [C_ADDRB_WIDTH-1:0]   addrb,\n   input [C_WRITE_WIDTH_B-1:0] dinb,\n   output [C_READ_WIDTH_B-1:0] doutb,\n   input                       injectsbiterr,\n   input                       injectdbiterr,\n   output                      sbiterr,\n   output                      dbiterr,\n   output [C_ADDRB_WIDTH-1:0]  rdaddrecc,\n   input                       eccpipece,\n   input                       sleep,\n   input                       deepsleep,\n   input                       shutdown,\n   output                      rsta_busy, \n   output                      rstb_busy, \n   //AXI BMG Input and Output Port Declarations\n \n   //AXI Global Signals\n   input                         s_aclk,\n   input                         s_aresetn,\n \n   //AXI                        Full/lite slave write (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_awid,\n   input  [31:0]                 s_axi_awaddr,\n   input  [7:0]                  s_axi_awlen,\n   input  [2:0]                  s_axi_awsize,\n   input  [1:0]                  s_axi_awburst,\n   input                         s_axi_awvalid,\n   output                        s_axi_awready,\n   input  [C_WRITE_WIDTH_A-1:0]  s_axi_wdata,\n   input  [C_WEA_WIDTH-1:0]      s_axi_wstrb,\n   input                         s_axi_wlast,\n   input                         s_axi_wvalid,\n   output                        s_axi_wready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_bid,\n   output [1:0]                  s_axi_bresp,\n   output                        s_axi_bvalid,\n   input                         s_axi_bready,\n \n   //AXI                        Full/lite slave read (write side)\n   input  [C_AXI_ID_WIDTH-1:0]   s_axi_arid,\n   input  [31:0]                 s_axi_araddr,\n   input  [7:0]                  s_axi_arlen,\n   input  [2:0]                  s_axi_arsize,\n   input  [1:0]                  s_axi_arburst,\n   input                         s_axi_arvalid,\n   output                        s_axi_arready,\n   output [C_AXI_ID_WIDTH-1:0]   s_axi_rid,\n   output [C_WRITE_WIDTH_B-1:0]  s_axi_rdata,\n   output [1:0]                  s_axi_rresp,\n   output                        s_axi_rlast,\n   output                        s_axi_rvalid,\n   input                         s_axi_rready,\n \n   //AXI                        Full/lite sideband signals\n   input                         s_axi_injectsbiterr,\n   input                         s_axi_injectdbiterr,\n   output                        s_axi_sbiterr,\n   output                        s_axi_dbiterr,\n   output [C_ADDRB_WIDTH-1:0]    s_axi_rdaddrecc \n \n  );\n//******************************\n// Port and Generic Definitions\n//******************************\n  //////////////////////////////////////////////////////////////////////////\n  // Generic Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // C_CORENAME              : Instance name of the Block Memory Generator core\n  // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n  //                           options are available - \"spartan3\", \"spartan6\", \n  //                           \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n  // C_MEM_TYPE              : Designates memory type.\n  //                           It can be\n  //                           0 - Single Port Memory\n  //                           1 - Simple Dual Port Memory\n  //                           2 - True Dual Port Memory\n  //                           3 - Single Port Read Only Memory\n  //                           4 - Dual Port Read Only Memory\n  // C_BYTE_SIZE             : Size of a byte (8 or 9 bits)\n  // C_ALGORITHM             : Designates the algorithm method used\n  //                           for constructing the memory.\n  //                           It can be Fixed_Primitives, Minimum_Area or \n  //                           Low_Power\n  // C_PRIM_TYPE             : Designates the user selected primitive used to \n  //                           construct the memory.\n  //\n  // C_LOAD_INIT_FILE        : Designates the use of an initialization file to\n  //                           initialize memory contents.\n  // C_INIT_FILE_NAME        : Memory initialization file name.\n  // C_USE_DEFAULT_DATA      : Designates whether to fill remaining\n  //                           initialization space with default data\n  // C_DEFAULT_DATA          : Default value of all memory locations\n  //                           not initialized by the memory\n  //                           initialization file.\n  // C_RST_TYPE              : Type of reset - Synchronous or Asynchronous\n  // C_HAS_RSTA              : Determines the presence of the RSTA port\n  // C_RST_PRIORITY_A        : Determines the priority between CE and SR for \n  //                           Port A.\n  // C_RSTRAM_A              : Determines if special reset behavior is used for\n  //                           Port A\n  // C_INITA_VAL             : The initialization value for Port A\n  // C_HAS_ENA               : Determines the presence of the ENA port\n  // C_HAS_REGCEA            : Determines the presence of the REGCEA port\n  // C_USE_BYTE_WEA          : Determines if the Byte Write is used or not.\n  // C_WEA_WIDTH             : The width of the WEA port\n  // C_WRITE_MODE_A          : Configurable write mode for Port A. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_A         : Memory write width for Port A.\n  // C_READ_WIDTH_A          : Memory read width for Port A.\n  // C_WRITE_DEPTH_A         : Memory write depth for Port A.\n  // C_READ_DEPTH_A          : Memory read depth for Port A.\n  // C_ADDRA_WIDTH           : Width of the ADDRA input port\n  // C_HAS_RSTB              : Determines the presence of the RSTB port\n  // C_RST_PRIORITY_B        : Determines the priority between CE and SR for \n  //                           Port B.\n  // C_RSTRAM_B              : Determines if special reset behavior is used for\n  //                           Port B\n  // C_INITB_VAL             : The initialization value for Port B\n  // C_HAS_ENB               : Determines the presence of the ENB port\n  // C_HAS_REGCEB            : Determines the presence of the REGCEB port\n  // C_USE_BYTE_WEB          : Determines if the Byte Write is used or not.\n  // C_WEB_WIDTH             : The width of the WEB port\n  // C_WRITE_MODE_B          : Configurable write mode for Port B. It can be\n  //                           WRITE_FIRST, READ_FIRST or NO_CHANGE.\n  // C_WRITE_WIDTH_B         : Memory write width for Port B.\n  // C_READ_WIDTH_B          : Memory read width for Port B.\n  // C_WRITE_DEPTH_B         : Memory write depth for Port B.\n  // C_READ_DEPTH_B          : Memory read depth for Port B.\n  // C_ADDRB_WIDTH           : Width of the ADDRB input port\n  // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n  //                           of the RAM primitive for Port A.\n  // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n  //                           of the RAM primitive for Port B.\n  // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n  //                           of the MUX for Port A.\n  // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n  //                           of the MUX for Port B.\n  // C_HAS_SOFTECC_INPUT_REGS_A  : \n  // C_HAS_SOFTECC_OUTPUT_REGS_B : \n  // C_MUX_PIPELINE_STAGES   : Designates the number of pipeline stages in \n  //                           between the muxes.\n  // C_USE_SOFTECC           : Determines if the Soft ECC feature is used or\n  //                           not. Only applicable Spartan-6\n  // C_USE_ECC               : Determines if the ECC feature is used or\n  //                           not. Only applicable for V5 and V6\n  // C_HAS_INJECTERR         : Determines if the error injection pins\n  //                           are present or not. If the ECC feature\n  //                           is not used, this value is defaulted to\n  //                           0, else the following are the allowed \n  //                           values:\n  //                         0 : No INJECTSBITERR or INJECTDBITERR pins\n  //                         1 : Only INJECTSBITERR pin exists\n  //                         2 : Only INJECTDBITERR pin exists\n  //                         3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n  // C_SIM_COLLISION_CHECK   : Controls the disabling of Unisim model collision\n  //                           warnings. It can be \"ALL\", \"NONE\", \n  //                           \"Warnings_Only\" or \"Generate_X_Only\".\n  // C_COMMON_CLK            : Determins if the core has a single CLK input.\n  // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n  // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n  //                           warnings\n  //////////////////////////////////////////////////////////////////////////\n  // Port Definitions\n  //////////////////////////////////////////////////////////////////////////\n  // CLKA    : Clock to synchronize all read and write operations of Port A.\n  // RSTA    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port A.\n  // ENA     : Enable all read and write operations of Port A.\n  // REGCEA  : Register Clock Enable to control each pipeline output\n  //           register stages for Port A.\n  // WEA     : Write Enable to enable all write operations of Port A.\n  // ADDRA   : Address of Port A.\n  // DINA    : Data input of Port A.\n  // DOUTA   : Data output of Port A.\n  // CLKB    : Clock to synchronize all read and write operations of Port B.\n  // RSTB    : Reset input to reset memory outputs to a user-defined \n  //           reset state for Port B.\n  // ENB     : Enable all read and write operations of Port B.\n  // REGCEB  : Register Clock Enable to control each pipeline output\n  //           register stages for Port B.\n  // WEB     : Write Enable to enable all write operations of Port B.\n  // ADDRB   : Address of Port B.\n  // DINB    : Data input of Port B.\n  // DOUTB   : Data output of Port B.\n  // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n  // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n  // SBITERR       : Output signal indicating that a Single Bit ECC Error has been\n  //                 detected and corrected.\n  // DBITERR       : Output signal indicating that a Double Bit ECC Error has been\n  //                 detected.\n  // RDADDRECC     : Read Address Output signal indicating address at which an\n  //                 ECC error has occurred.\n  //////////////////////////////////////////////////////////////////////////\n\n  wire SBITERR;\n  wire DBITERR;\n  wire S_AXI_AWREADY;\n  wire S_AXI_WREADY;\n  wire S_AXI_BVALID;\n  wire S_AXI_ARREADY;\n  wire S_AXI_RLAST;\n  wire S_AXI_RVALID;\n  wire S_AXI_SBITERR;\n  wire S_AXI_DBITERR;\n\n  wire [C_WEA_WIDTH-1:0]       WEA              = wea;\n  wire [C_ADDRA_WIDTH-1:0]     ADDRA            = addra;\n  wire [C_WRITE_WIDTH_A-1:0]   DINA             = dina;\n  wire [C_READ_WIDTH_A-1:0]    DOUTA;\n  wire [C_WEB_WIDTH-1:0]       WEB              = web;\n  wire [C_ADDRB_WIDTH-1:0]     ADDRB            = addrb;\n  wire [C_WRITE_WIDTH_B-1:0]   DINB             = dinb;\n  wire [C_READ_WIDTH_B-1:0]    DOUTB;\n  wire [C_ADDRB_WIDTH-1:0]     RDADDRECC;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_AWID       = s_axi_awid;\n  wire [31:0]                  S_AXI_AWADDR     = s_axi_awaddr;\n  wire [7:0]                   S_AXI_AWLEN      = s_axi_awlen;\n  wire [2:0]                   S_AXI_AWSIZE     = s_axi_awsize;\n  wire [1:0]                   S_AXI_AWBURST    = s_axi_awburst;\n  wire [C_WRITE_WIDTH_A-1:0]   S_AXI_WDATA      = s_axi_wdata;\n  wire [C_WEA_WIDTH-1:0]       S_AXI_WSTRB      = s_axi_wstrb;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID;\n  wire [1:0]                   S_AXI_BRESP;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_ARID       = s_axi_arid;\n  wire [31:0]                  S_AXI_ARADDR     = s_axi_araddr;\n  wire [7:0]                   S_AXI_ARLEN      = s_axi_arlen;\n  wire [2:0]                   S_AXI_ARSIZE     = s_axi_arsize;\n  wire [1:0]                   S_AXI_ARBURST    = s_axi_arburst;\n  wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID;\n  wire [C_WRITE_WIDTH_B-1:0]   S_AXI_RDATA;\n  wire [1:0]                   S_AXI_RRESP;\n  wire [C_ADDRB_WIDTH-1:0]     S_AXI_RDADDRECC;\n  // Added to fix the simulation warning #CR731605\n  wire [C_WEB_WIDTH-1:0]       WEB_parameterized = 0;\n  wire                         ECCPIPECE;\n  wire                         SLEEP;\n  reg                          RSTA_BUSY = 0;\n  reg                          RSTB_BUSY = 0;\n  // Declaration of internal signals to avoid warnings #927399\n  wire                         CLKA;\n  wire                         RSTA;\n  wire                         ENA;\n  wire                         REGCEA;\n  wire                         CLKB;\n  wire                         RSTB;\n  wire                         ENB;\n  wire                         REGCEB;\n  wire                         INJECTSBITERR;\n  wire                         INJECTDBITERR;\n  wire                         S_ACLK;\n  wire                         S_ARESETN;\n  wire                         S_AXI_AWVALID;\n  wire                         S_AXI_WLAST;\n  wire                         S_AXI_WVALID;\n  wire                         S_AXI_BREADY;\n  wire                         S_AXI_ARVALID;\n  wire                         S_AXI_RREADY;\n  wire                         S_AXI_INJECTSBITERR;\n  wire                         S_AXI_INJECTDBITERR;\n\n  assign CLKA                 = clka;\n  assign RSTA                 = rsta;\n  assign ENA                  = ena;\n  assign REGCEA               = regcea;\n  assign CLKB                 = clkb;\n  assign RSTB                 = rstb;\n  assign ENB                  = enb;\n  assign REGCEB               = regceb;\n  assign INJECTSBITERR        = injectsbiterr;\n  assign INJECTDBITERR        = injectdbiterr;\n  assign ECCPIPECE            = eccpipece;\n  assign SLEEP                = sleep;\n  assign sbiterr              = SBITERR;\n  assign dbiterr              = DBITERR;\n  assign S_ACLK               = s_aclk;\n  assign S_ARESETN            = s_aresetn;\n  assign S_AXI_AWVALID        = s_axi_awvalid;\n  assign s_axi_awready        = S_AXI_AWREADY;\n  assign S_AXI_WLAST          = s_axi_wlast;\n  assign S_AXI_WVALID         = s_axi_wvalid;\n  assign s_axi_wready         = S_AXI_WREADY;\n  assign s_axi_bvalid         = S_AXI_BVALID;\n  assign S_AXI_BREADY         = s_axi_bready;\n  assign S_AXI_ARVALID        = s_axi_arvalid;\n  assign s_axi_arready        = S_AXI_ARREADY;\n  assign s_axi_rlast          = S_AXI_RLAST;\n  assign s_axi_rvalid         = S_AXI_RVALID;\n  assign S_AXI_RREADY         = s_axi_rready;\n  assign S_AXI_INJECTSBITERR  = s_axi_injectsbiterr;\n  assign S_AXI_INJECTDBITERR  = s_axi_injectdbiterr;\n  assign s_axi_sbiterr        = S_AXI_SBITERR;\n  assign s_axi_dbiterr        = S_AXI_DBITERR;\n\n  assign rsta_busy            = RSTA_BUSY;\n  assign rstb_busy            = RSTB_BUSY;\n\n  assign doutb            = DOUTB;\n  assign douta            = DOUTA;\n  assign rdaddrecc        = RDADDRECC;\n  assign s_axi_bid        = S_AXI_BID;\n  assign s_axi_bresp      = S_AXI_BRESP;\n  assign s_axi_rid        = S_AXI_RID;\n  assign s_axi_rdata      = S_AXI_RDATA;\n  assign s_axi_rresp      = S_AXI_RRESP;\n  assign s_axi_rdaddrecc  = S_AXI_RDADDRECC;\n\n  localparam FLOP_DELAY  = 100;  // 100 ps\n\n   reg                       injectsbiterr_in;\n   reg                       injectdbiterr_in;\n   reg                       rsta_in;\n   reg                       ena_in;\n   reg                       regcea_in;\n   reg [C_WEA_WIDTH-1:0]     wea_in;\n   reg [C_ADDRA_WIDTH-1:0]   addra_in;\n   reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n  wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n  wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n  wire s_axi_wr_en_c;\n  wire s_axi_rd_en_c;\n  wire s_aresetn_a_c;\n  wire [7:0] s_axi_arlen_c ;\n\n\n  wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n  wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n  wire [1:0] s_axi_rresp_c;\n  wire s_axi_rlast_c;\n  wire s_axi_rvalid_c;\n  wire s_axi_rready_c;\n  wire regceb_c;\n\n  localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n  wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n  wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n  reg [4:0] RSTA_SHFT_REG = 0;\n  reg POR_A = 0; \n  reg [4:0] RSTB_SHFT_REG = 0;\n  reg POR_B = 0;\n \n  reg ENA_dly = 0;\n  reg ENA_dly_D = 0;\n\n  reg ENB_dly = 0;\n  reg ENB_dly_D = 0;\n\n  wire RSTA_I_SAFE;\n  wire RSTB_I_SAFE;\n\n  wire ENA_I_SAFE;\n  wire ENB_I_SAFE;\n  \n  reg ram_rstram_a_busy = 0;\n  reg ram_rstreg_a_busy = 0;\n  reg ram_rstram_b_busy = 0;\n  reg ram_rstreg_b_busy = 0;\n\n  reg ENA_dly_reg = 0;\n  reg ENB_dly_reg = 0;\n \n  reg ENA_dly_reg_D = 0;\n  reg ENB_dly_reg_D = 0;\n\n  //**************\n  // log2roundup\n  //**************\n  function integer log2roundup (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\n         if (data_value > 1) begin\n            for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n               width = width + 1;\n            end //loop\n         end //if\n\n         log2roundup = width;\n\n      end //log2roundup\n   endfunction\n\n  //**************\n  // log2int\n  //**************\n  function integer log2int (input integer data_value);\n      integer width;\n      integer cnt;\n      begin\n         width = 0;\n\t\t cnt= data_value;\n\n            for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n               width = width + 1;\n            end //loop\n\n         log2int = width;\n\n      end //log2int\n   endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n  function integer divroundup (input integer data_value,input integer divisor);\n      integer div;\n      begin\n    div   = data_value/divisor;\n         if ((data_value % divisor) != 0) begin\n      div = div+1;\n         end //if\n         divroundup = div;\n         end //if\n   endfunction\n\n  localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n  localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n  localparam C_AXI_ADDR_WIDTH     = C_AXI_ADDR_WIDTH_MSB;\n \n  //Data Width        Number of LSB address bits to be discarded\n  //1 to 16                      1\n  //17 to 32                     2\n  //33 to 64                     3\n  //65 to 128                    4\n  //129 to 256                   5\n  //257 to 512                   6\n  //513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n  localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n      always @* begin\n      injectsbiterr_in = INJECTSBITERR;\n      injectdbiterr_in = INJECTDBITERR;\n      rsta_in    = RSTA;\n      ena_in     = ENA;\n      regcea_in  = REGCEA;\n      wea_in     = WEA;\n      addra_in   = ADDRA;\n      dina_in    = DINA;\n      end //end always\n      end //end no_softecc_input_reg_stage\n endgenerate\n\n  generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n      always @(posedge CLKA) begin\n      injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n      injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n      rsta_in     <= #FLOP_DELAY RSTA;\n      ena_in     <= #FLOP_DELAY ENA;\n      regcea_in  <= #FLOP_DELAY REGCEA;\n      wea_in     <= #FLOP_DELAY WEA;\n      addra_in   <= #FLOP_DELAY ADDRA;\n      dina_in    <= #FLOP_DELAY DINA;\n      end //end always\n      end //end input_reg_stages generate statement\n endgenerate\n\n  //**************************************************************************\n  // NO SAFETY LOGIC\n  //**************************************************************************\n\n   generate \n     if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n       assign ENA_I_SAFE     = ena_in;\n       assign ENB_I_SAFE     = ENB;\n       assign RSTA_I_SAFE    = rsta_in;\n       assign RSTB_I_SAFE    = RSTB;\n     end\n   endgenerate\n\n  //***************************************************************************\n  // SAFETY LOGIC\n  // Power-ON Reset Generation\n  //***************************************************************************\n  generate \n    if (C_EN_SAFETY_CKT == 1) begin\n      always @(posedge clka)  RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clka)  POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n      always @(posedge clkb)  RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n      always @(posedge clkb)  POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n      assign RSTA_I_SAFE = rsta_in | POR_A;  \n      assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- RSTA/B_BUSY Generation\n  //-----------------------------------------------------------------------------\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n      always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n      always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n      always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n    end\n  endgenerate\n\n  generate \n    if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n      always @(*) RSTB_BUSY = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1)  begin : RSTB_BUSY_NO_REG\n      always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n    end\n  endgenerate\n    \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG  \n      always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n      always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n    end\n  endgenerate\n\n  //-----------------------------------------------------------------------------\n  //  -- ENA/ENB Generation\n  //-----------------------------------------------------------------------------\n  \n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG    \n      always @(posedge clka) begin\n        ENA_dly   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_D <= #FLOP_DELAY ENA_dly;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n      always @(posedge clka) begin\n        ENA_dly_reg   <= #FLOP_DELAY RSTA_I_SAFE;\n        ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n      end\n      assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n    end\n  endgenerate\n\n  generate \n    if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n      assign ENB_I_SAFE = 1'b0;\n    end\n  endgenerate\n\n  generate \n    if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly   <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_D <= #FLOP_DELAY ENB_dly;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n    end\n  endgenerate\n  \n  generate \n    if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n      always @(posedge clkb) begin : PROC_ENB_GEN\n        ENB_dly_reg    <= #FLOP_DELAY RSTB_I_SAFE;\n        ENB_dly_reg_D  <= #FLOP_DELAY ENB_dly_reg;\n      end\n      assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n    end\n  endgenerate\n\n  generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\n\n  generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n  localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n  localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n  localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n  localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n  localparam C_MEM_MAP_ADDRA_WIDTH_MSB     = C_ADDRA_WIDTH_MSB;\n  localparam C_MEM_MAP_ADDRB_WIDTH_MSB     = C_ADDRB_WIDTH_MSB;\n\n  // Data Width        Number of LSB address bits to be discarded\n  //  1 to 16                      1\n  //  17 to 32                     2\n  //  33 to 64                     3\n  //  65 to 128                    4\n  //  129 to 256                   5\n  //  257 to 512                   6\n  //  513 to 1024                  7\n  // The following two constants determine this.\n\n  localparam MEM_MAP_LOWER_BOUND_VAL_A      = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n  localparam MEM_MAP_LOWER_BOUND_VAL_B      = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8)));\n  localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n  localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n  wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n  wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n  wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n  \n  assign msb_zero_i = 0;\n  assign lsb_zero_i = 0;\n  assign RDADDRECC  = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (C_HAS_ENA),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (C_USE_BYTE_WEA),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH_ACTUAL),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (C_HAS_ENB),\n    .C_HAS_REGCEB                      (C_HAS_REGCEB),\n    .C_USE_BYTE_WEB                    (C_USE_BYTE_WEB),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH_ACTUAL),\n    .C_HAS_MEM_OUTPUT_REGS_A           (C_HAS_MEM_OUTPUT_REGS_A),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (C_HAS_MUX_OUTPUT_REGS_A),\n    .C_HAS_MUX_OUTPUT_REGS_B           (C_HAS_MUX_OUTPUT_REGS_B),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE                     (C_EN_ECC_PIPE),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (CLKA),\n   .RSTA             (RSTA_I_SAFE),//(rsta_in),\n   .ENA              (ENA_I_SAFE),//(ena_in),\n   .REGCEA           (regcea_in),\n   .WEA              (wea_in),\n   .ADDRA            (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n   .DINA             (dina_in),\n   .DOUTA            (DOUTA),\n   .CLKB             (CLKB),\n   .RSTB             (RSTB_I_SAFE),//(RSTB),\n   .ENB              (ENB_I_SAFE),//(ENB),\n   .REGCEB           (REGCEB),\n   .WEB              (WEB),\n   .ADDRB            (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n   .DINB             (DINB),\n   .DOUTB            (DOUTB),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .ECCPIPECE        (ECCPIPECE),\n   .SLEEP            (SLEEP),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .RDADDRECC        (rdaddrecc_i)\n  );\n end\n endgenerate\n\n  generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n      assign S_AXI_RDATA    = s_axi_rdata_c;\n      assign S_AXI_RLAST    = s_axi_rlast_c;\n      assign S_AXI_RVALID   = s_axi_rvalid_c;\n      assign S_AXI_RID      = s_axi_rid_c;\n      assign S_AXI_RRESP    = s_axi_rresp_c;\n      assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n        assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n        assign regceb_c = REGCEB;\n end\n     endgenerate\n\n     generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RDATA     = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n     generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n        assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n        assign S_AXI_RDATA     = s_axi_rdata_c;\n        assign S_AXI_RID       = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n        assign S_AXI_RRESP     = m_axi_payload_c[2:1];\n        assign S_AXI_RLAST     = m_axi_payload_c[0];\n end\n     endgenerate\n\n  generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n    blk_mem_axi_regs_fwd_v8_4\n      #(.C_DATA_WIDTH    (C_AXI_PAYLOAD))\n    axi_regs_inst (\n        .ACLK           (S_ACLK), \n        .ARESET         (s_aresetn_a_c),\n        .S_VALID        (s_axi_rvalid_c), \n        .S_READY        (s_axi_rready_c),\n        .S_PAYLOAD_DATA (s_axi_payload_c),\n        .M_VALID        (S_AXI_RVALID),\n        .M_READY        (S_AXI_RREADY),\n        .M_PAYLOAD_DATA (m_axi_payload_c)\n    );\n end\n endgenerate\n\n  generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n  blk_mem_axi_write_wrapper_beh_v8_4\n    #(.C_INTERFACE_TYPE           (C_INTERFACE_TYPE),\n      .C_AXI_TYPE                 (C_AXI_TYPE),\n      .C_AXI_SLAVE_TYPE           (C_AXI_SLAVE_TYPE),\n      .C_MEMORY_TYPE              (C_MEM_TYPE),\n      .C_WRITE_DEPTH_A            (C_WRITE_DEPTH_A),\n      .C_AXI_AWADDR_WIDTH         ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n      .C_HAS_AXI_ID               (C_HAS_AXI_ID),\n      .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n      .C_ADDRA_WIDTH              (C_ADDRA_WIDTH),\n      .C_AXI_WDATA_WIDTH          (C_WRITE_WIDTH_A),\n      .C_AXI_OS_WR                (C_AXI_OS_WR))\n  axi_wr_fsm (\n      // AXI Global Signals\n      .S_ACLK                     (S_ACLK),\n      .S_ARESETN                  (s_aresetn_a_c),\n      // AXI Full/Lite Slave Write interface\n      .S_AXI_AWADDR               (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n      .S_AXI_AWLEN                (S_AXI_AWLEN),\n      .S_AXI_AWID                 (S_AXI_AWID),\n      .S_AXI_AWSIZE               (S_AXI_AWSIZE),\n      .S_AXI_AWBURST              (S_AXI_AWBURST),\n      .S_AXI_AWVALID              (S_AXI_AWVALID),\n      .S_AXI_AWREADY              (S_AXI_AWREADY),\n      .S_AXI_WVALID               (S_AXI_WVALID),\n      .S_AXI_WREADY               (S_AXI_WREADY),\n      .S_AXI_BVALID               (S_AXI_BVALID),\n      .S_AXI_BREADY               (S_AXI_BREADY),\n      .S_AXI_BID                  (S_AXI_BID),\n      // Signals for BRAM interfac(\n      .S_AXI_AWADDR_OUT           (s_axi_awaddr_out_c),\n      .S_AXI_WR_EN                (s_axi_wr_en_c)\n      );\n\n  blk_mem_axi_read_wrapper_beh_v8_4\n  #(.C_INTERFACE_TYPE             (C_INTERFACE_TYPE), \n    .C_AXI_TYPE\t\t          (C_AXI_TYPE), \n    .C_AXI_SLAVE_TYPE             (C_AXI_SLAVE_TYPE), \n    .C_MEMORY_TYPE                (C_MEM_TYPE), \n    .C_WRITE_WIDTH_A              (C_WRITE_WIDTH_A), \n    .C_ADDRA_WIDTH                (C_ADDRA_WIDTH), \n    .C_AXI_PIPELINE_STAGES        (1), \n    .C_AXI_ARADDR_WIDTH\t          ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n    .C_HAS_AXI_ID                 (C_HAS_AXI_ID), \n    .C_AXI_ID_WIDTH               (C_AXI_ID_WIDTH), \n    .C_ADDRB_WIDTH                (C_ADDRB_WIDTH)) \n  axi_rd_sm(\n    //AXI Global Signals\n    .S_ACLK                       (S_ACLK), \n    .S_ARESETN                    (s_aresetn_a_c),\n    //AXI Full/Lite Read Side\n    .S_AXI_ARADDR                 (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n    .S_AXI_ARLEN                  (s_axi_arlen_c),\n    .S_AXI_ARSIZE                 (S_AXI_ARSIZE),\n    .S_AXI_ARBURST                (S_AXI_ARBURST),\n    .S_AXI_ARVALID                (S_AXI_ARVALID),\n    .S_AXI_ARREADY                (S_AXI_ARREADY),\n    .S_AXI_RLAST                  (s_axi_rlast_c),\n    .S_AXI_RVALID                 (s_axi_rvalid_c),\n    .S_AXI_RREADY                 (s_axi_rready_c),\n    .S_AXI_ARID                   (S_AXI_ARID),\n    .S_AXI_RID                    (s_axi_rid_c),\n    //AXI Full/Lite Read FSM Outputs\n    .S_AXI_ARADDR_OUT             (s_axi_araddr_out_c),\n    .S_AXI_RD_EN                  (s_axi_rd_en_c)\n  );\n\nblk_mem_gen_v8_4_4_mem_module\n  #(.C_CORENAME                        (C_CORENAME),\n    .C_FAMILY                          (C_FAMILY),\n    .C_XDEVICEFAMILY                   (C_XDEVICEFAMILY),\n    .C_MEM_TYPE                        (C_MEM_TYPE),\n    .C_BYTE_SIZE                       (C_BYTE_SIZE),\n    .C_USE_BRAM_BLOCK                  (C_USE_BRAM_BLOCK),\n    .C_ALGORITHM                       (C_ALGORITHM),\n    .C_PRIM_TYPE                       (C_PRIM_TYPE),\n    .C_LOAD_INIT_FILE                  (C_LOAD_INIT_FILE),\n    .C_INIT_FILE_NAME                  (C_INIT_FILE_NAME),\n    .C_INIT_FILE                       (C_INIT_FILE),\n    .C_USE_DEFAULT_DATA                (C_USE_DEFAULT_DATA),\n    .C_DEFAULT_DATA                    (C_DEFAULT_DATA),\n    .C_RST_TYPE                        (\"SYNC\"),\n    .C_HAS_RSTA                        (C_HAS_RSTA),\n    .C_RST_PRIORITY_A                  (C_RST_PRIORITY_A),\n    .C_RSTRAM_A                        (C_RSTRAM_A),\n    .C_INITA_VAL                       (C_INITA_VAL),\n    .C_HAS_ENA                         (1),\n    .C_HAS_REGCEA                      (C_HAS_REGCEA),\n    .C_USE_BYTE_WEA                    (1),\n    .C_WEA_WIDTH                       (C_WEA_WIDTH),\n    .C_WRITE_MODE_A                    (C_WRITE_MODE_A),\n    .C_WRITE_WIDTH_A                   (C_WRITE_WIDTH_A),\n    .C_READ_WIDTH_A                    (C_READ_WIDTH_A),\n    .C_WRITE_DEPTH_A                   (C_WRITE_DEPTH_A),\n    .C_READ_DEPTH_A                    (C_READ_DEPTH_A),\n    .C_ADDRA_WIDTH                     (C_ADDRA_WIDTH),\n    .C_HAS_RSTB                        (C_HAS_RSTB),\n    .C_RST_PRIORITY_B                  (C_RST_PRIORITY_B),\n    .C_RSTRAM_B                        (C_RSTRAM_B),\n    .C_INITB_VAL                       (C_INITB_VAL),\n    .C_HAS_ENB                         (1),\n    .C_HAS_REGCEB                      (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_USE_BYTE_WEB                    (1),\n    .C_WEB_WIDTH                       (C_WEB_WIDTH),\n    .C_WRITE_MODE_B                    (C_WRITE_MODE_B),\n    .C_WRITE_WIDTH_B                   (C_WRITE_WIDTH_B),\n    .C_READ_WIDTH_B                    (C_READ_WIDTH_B),\n    .C_WRITE_DEPTH_B                   (C_WRITE_DEPTH_B),\n    .C_READ_DEPTH_B                    (C_READ_DEPTH_B),\n    .C_ADDRB_WIDTH                     (C_ADDRB_WIDTH),\n    .C_HAS_MEM_OUTPUT_REGS_A           (0),\n    .C_HAS_MEM_OUTPUT_REGS_B           (C_HAS_MEM_OUTPUT_REGS_B),\n    .C_HAS_MUX_OUTPUT_REGS_A           (0),\n    .C_HAS_MUX_OUTPUT_REGS_B           (0),\n    .C_HAS_SOFTECC_INPUT_REGS_A        (C_HAS_SOFTECC_INPUT_REGS_A),\n    .C_HAS_SOFTECC_OUTPUT_REGS_B       (C_HAS_SOFTECC_OUTPUT_REGS_B),\n    .C_MUX_PIPELINE_STAGES             (C_MUX_PIPELINE_STAGES),\n    .C_USE_SOFTECC                     (C_USE_SOFTECC),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_HAS_INJECTERR                   (C_HAS_INJECTERR),\n    .C_SIM_COLLISION_CHECK             (C_SIM_COLLISION_CHECK),\n    .C_COMMON_CLK                      (C_COMMON_CLK),\n    .FLOP_DELAY                        (FLOP_DELAY),\n    .C_DISABLE_WARN_BHV_COLL           (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE                     (0),\n    .C_DISABLE_WARN_BHV_RANGE          (C_DISABLE_WARN_BHV_RANGE))\n    blk_mem_gen_v8_4_4_inst\n   (.CLKA            (S_ACLK),\n   .RSTA             (s_aresetn_a_c),\n   .ENA              (s_axi_wr_en_c),\n   .REGCEA           (regcea_in),\n   .WEA              (S_AXI_WSTRB),\n   .ADDRA            (s_axi_awaddr_out_c),\n   .DINA             (S_AXI_WDATA),\n   .DOUTA            (DOUTA),\n   .CLKB             (S_ACLK),\n   .RSTB             (s_aresetn_a_c),\n   .ENB              (s_axi_rd_en_c),\n   .REGCEB           (regceb_c),\n   .WEB              (WEB_parameterized),\n   .ADDRB            (s_axi_araddr_out_c),\n   .DINB             (DINB),\n   .DOUTB            (s_axi_rdata_c),\n   .INJECTSBITERR    (injectsbiterr_in),\n   .INJECTDBITERR    (injectdbiterr_in),\n   .SBITERR          (SBITERR),\n   .DBITERR          (DBITERR),\n   .ECCPIPECE        (1'b0),\n   .SLEEP            (1'b0),\n   .RDADDRECC        (RDADDRECC)\n  );\n end\n endgenerate\nendmodule\n\n\n\n", "num_lines": 4523}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "/*\n *******************************************************************************\n *\n * FIFO Generator - Verilog Behavioral Model\n *\n *******************************************************************************\n *\n * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.\n *\n * This file contains confidential and proprietary information\n * of Xilinx, Inc. and is protected under U.S. and\n * international copyright and other intellectual property\n * laws.\n *\n * DISCLAIMER\n * This disclaimer is not a license and does not grant any\n * rights to the materials distributed herewith. Except as\n * otherwise provided in a valid license issued to you by\n * Xilinx, and to the maximum extent permitted by applicable\n * law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n * (2) Xilinx shall not be liable (whether in contract or tort,\n * including negligence, or under any other theory of\n * liability) for any loss or damage of any kind or nature\n * related to, arising under or in connection with these\n * materials, including for any direct, or any indirect,\n * special, incidental, or consequential loss or damage\n * (including loss of data, profits, goodwill, or any type of\n * loss or damage suffered as a result of any action brought\n * by a third party) even if such damage or loss was\n * reasonably foreseeable or Xilinx had been advised of the\n * possibility of the same.\n *\n * CRITICAL APPLICATIONS\n * Xilinx products are not designed or intended to be fail-\n * safe, or for use in any application requiring fail-safe\n * performance, such as life-support or safety devices or\n * systems, Class III medical devices, nuclear facilities,\n * applications related to the deployment of airbags, or any\n * other applications that could lead to death, personal\n * injury, or severe property or environmental damage\n * (individually and collectively, \"Critical\n * Applications\"). Customer assumes the sole risk and\n * liability of any use of Xilinx products in Critical\n * Applications, subject only to applicable laws and\n * regulations governing limitations on product liability.\n *\n * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n * PART OF THIS FILE AT ALL TIMES.\n *\n *******************************************************************************\n *******************************************************************************\n *\n * Filename: fifo_generator_vlog_beh.v\n *\n * Author     : Xilinx\n *\n *******************************************************************************\n * Structure:\n * \n * fifo_generator_vlog_beh.v\n *    |\n *    +-fifo_generator_v13_2_1_bhv_ver_as\n *    |\n *    +-fifo_generator_v13_2_1_bhv_ver_ss\n *    |\n *    +-fifo_generator_v13_2_1_bhv_ver_preload0\n * \n *******************************************************************************\n * Description:\n *\n * The Verilog behavioral model for the FIFO Generator.\n *\n *   The behavioral model has three parts:\n *      - The behavioral model for independent clocks FIFOs (_as)\n *      - The behavioral model for common clock FIFOs (_ss)\n *      - The \"preload logic\" block which implements First-word Fall-through\n * \n *******************************************************************************\n * Description:\n *  The verilog behavioral model for the FIFO generator core.\n *\n *******************************************************************************\n */\n\n`timescale 1ps/1ps\n`ifndef TCQ\n `define TCQ 100\n`endif\n\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_vlog_beh\n  #(\n    //-----------------------------------------------------------------------\n    // Generic Declarations\n    //-----------------------------------------------------------------------\n    parameter C_COMMON_CLOCK                 = 0,\n    parameter C_COUNT_TYPE                   = 0,\n    parameter C_DATA_COUNT_WIDTH             = 2,\n    parameter C_DEFAULT_VALUE                = \"\",\n    parameter C_DIN_WIDTH                    = 8,\n    parameter C_DOUT_RST_VAL                 = \"\",\n    parameter C_DOUT_WIDTH                   = 8,\n    parameter C_ENABLE_RLOCS                 = 0,\n    parameter C_FAMILY                       = \"\",\n    parameter C_FULL_FLAGS_RST_VAL           = 1,\n    parameter C_HAS_ALMOST_EMPTY             = 0,\n    parameter C_HAS_ALMOST_FULL              = 0,\n    parameter C_HAS_BACKUP                   = 0,\n    parameter C_HAS_DATA_COUNT               = 0,\n    parameter C_HAS_INT_CLK                  = 0,\n    parameter C_HAS_MEMINIT_FILE             = 0,\n    parameter C_HAS_OVERFLOW                 = 0,\n    parameter C_HAS_RD_DATA_COUNT            = 0,\n    parameter C_HAS_RD_RST                   = 0,\n    parameter C_HAS_RST                      = 1,\n    parameter C_HAS_SRST                     = 0,\n    parameter C_HAS_UNDERFLOW                = 0,\n    parameter C_HAS_VALID                    = 0,\n    parameter C_HAS_WR_ACK                   = 0,\n    parameter C_HAS_WR_DATA_COUNT            = 0,\n    parameter C_HAS_WR_RST                   = 0,\n    parameter C_IMPLEMENTATION_TYPE          = 0,\n    parameter C_INIT_WR_PNTR_VAL             = 0,\n    parameter C_MEMORY_TYPE                  = 1,\n    parameter C_MIF_FILE_NAME                = \"\",\n    parameter C_OPTIMIZATION_MODE            = 0,\n    parameter C_OVERFLOW_LOW                 = 0,\n    parameter C_EN_SAFETY_CKT                = 0,\n    parameter C_PRELOAD_LATENCY              = 1,\n    parameter C_PRELOAD_REGS                 = 0,\n    parameter C_PRIM_FIFO_TYPE               = \"4kx4\",\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter C_PROG_EMPTY_TYPE              = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter C_PROG_FULL_TYPE               = 0,\n    parameter C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter C_RD_DEPTH                     = 256,\n    parameter C_RD_FREQ                      = 1,\n    parameter C_RD_PNTR_WIDTH                = 8,\n    parameter C_UNDERFLOW_LOW                = 0,\n    parameter C_USE_DOUT_RST                 = 0,\n    parameter C_USE_ECC                      = 0,\n    parameter C_USE_EMBEDDED_REG             = 0,\n    parameter C_USE_PIPELINE_REG             = 0,\n    parameter C_POWER_SAVING_MODE            = 0,\n    parameter C_USE_FIFO16_FLAGS             = 0,\n    parameter C_USE_FWFT_DATA_COUNT          = 0,\n    parameter C_VALID_LOW                    = 0,\n    parameter C_WR_ACK_LOW                   = 0,\n    parameter C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter C_WR_DEPTH                     = 256,\n    parameter C_WR_FREQ                      = 1,\n    parameter C_WR_PNTR_WIDTH                = 8,\n    parameter C_WR_RESPONSE_LATENCY          = 1,\n    parameter C_MSGON_VAL                    = 1,\n    parameter C_ENABLE_RST_SYNC              = 1,\n    parameter C_ERROR_INJECTION_TYPE         = 0,\n    parameter C_SYNCHRONIZER_STAGE           = 2,\n\n    // AXI Interface related parameters start here\n    parameter C_INTERFACE_TYPE               = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3\n    parameter C_AXI_TYPE                     = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3\n    parameter C_HAS_AXI_WR_CHANNEL           = 0,\n    parameter C_HAS_AXI_RD_CHANNEL           = 0,\n    parameter C_HAS_SLAVE_CE                 = 0,\n    parameter C_HAS_MASTER_CE                = 0,\n    parameter C_ADD_NGC_CONSTRAINT           = 0,\n    parameter C_USE_COMMON_UNDERFLOW         = 0,\n    parameter C_USE_COMMON_OVERFLOW          = 0,\n    parameter C_USE_DEFAULT_SETTINGS         = 0,\n\n    // AXI Full/Lite\n    parameter C_AXI_ID_WIDTH                 = 0,\n    parameter C_AXI_ADDR_WIDTH               = 0,\n    parameter C_AXI_DATA_WIDTH               = 0,\n    parameter C_AXI_LEN_WIDTH                = 8,\n    parameter C_AXI_LOCK_WIDTH               = 2,\n    parameter C_HAS_AXI_ID                   = 0,\n    parameter C_HAS_AXI_AWUSER               = 0,\n    parameter C_HAS_AXI_WUSER                = 0,\n    parameter C_HAS_AXI_BUSER                = 0,\n    parameter C_HAS_AXI_ARUSER               = 0,\n    parameter C_HAS_AXI_RUSER                = 0,\n    parameter C_AXI_ARUSER_WIDTH             = 0,\n    parameter C_AXI_AWUSER_WIDTH             = 0,\n    parameter C_AXI_WUSER_WIDTH              = 0,\n    parameter C_AXI_BUSER_WIDTH              = 0,\n    parameter C_AXI_RUSER_WIDTH              = 0,\n\n    // AXI Streaming\n    parameter C_HAS_AXIS_TDATA               = 0,\n    parameter C_HAS_AXIS_TID                 = 0,\n    parameter C_HAS_AXIS_TDEST               = 0,\n    parameter C_HAS_AXIS_TUSER               = 0,\n    parameter C_HAS_AXIS_TREADY              = 0,\n    parameter C_HAS_AXIS_TLAST               = 0,\n    parameter C_HAS_AXIS_TSTRB               = 0,\n    parameter C_HAS_AXIS_TKEEP               = 0,\n    parameter C_AXIS_TDATA_WIDTH             = 1,\n    parameter C_AXIS_TID_WIDTH               = 1,\n    parameter C_AXIS_TDEST_WIDTH             = 1,\n    parameter C_AXIS_TUSER_WIDTH             = 1,\n    parameter C_AXIS_TSTRB_WIDTH             = 1,\n    parameter C_AXIS_TKEEP_WIDTH             = 1,\n\n    // AXI Channel Type\n    // WACH --> Write Address Channel\n    // WDCH --> Write Data Channel\n    // WRCH --> Write Response Channel\n    // RACH --> Read Address Channel\n    // RDCH --> Read Data Channel\n    // AXIS --> AXI Streaming\n    parameter C_WACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic\n    parameter C_WDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_WRCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_RDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n    parameter C_AXIS_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n\n    // AXI Implementation Type\n    // 1 = Common Clock Block RAM FIFO\n    // 2 = Common Clock Distributed RAM FIFO\n    // 11 = Independent Clock Block RAM FIFO\n    // 12 = Independent Clock Distributed RAM FIFO\n    parameter C_IMPLEMENTATION_TYPE_WACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_WRCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RACH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_RDCH     = 0,\n    parameter C_IMPLEMENTATION_TYPE_AXIS     = 0,\n\n    // AXI FIFO Type\n    // 0 = Data FIFO\n    // 1 = Packet FIFO\n    // 2 = Low Latency Sync FIFO\n    // 3 = Low Latency Async FIFO\n    parameter C_APPLICATION_TYPE_WACH        = 0,\n    parameter C_APPLICATION_TYPE_WDCH        = 0,\n    parameter C_APPLICATION_TYPE_WRCH        = 0,\n    parameter C_APPLICATION_TYPE_RACH        = 0,\n    parameter C_APPLICATION_TYPE_RDCH        = 0,\n    parameter C_APPLICATION_TYPE_AXIS        = 0,\n\n    // AXI Built-in FIFO Primitive Type\n    // 512x36, 1kx18, 2kx9, 4kx4, etc\n    parameter C_PRIM_FIFO_TYPE_WACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_WRCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RACH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_RDCH          = \"512x36\",\n    parameter C_PRIM_FIFO_TYPE_AXIS          = \"512x36\",\n\n    // Enable ECC\n    // 0 = ECC disabled\n    // 1 = ECC enabled\n    parameter C_USE_ECC_WACH                 = 0,\n    parameter C_USE_ECC_WDCH                 = 0,\n    parameter C_USE_ECC_WRCH                 = 0,\n    parameter C_USE_ECC_RACH                 = 0,\n    parameter C_USE_ECC_RDCH                 = 0,\n    parameter C_USE_ECC_AXIS                 = 0,\n\n    // ECC Error Injection Type\n    // 0 = No Error Injection\n    // 1 = Single Bit Error Injection\n    // 2 = Double Bit Error Injection\n    // 3 = Single Bit and Double Bit Error Injection\n    parameter C_ERROR_INJECTION_TYPE_WACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_WRCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RACH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_RDCH    = 0,\n    parameter C_ERROR_INJECTION_TYPE_AXIS    = 0,\n\n    // Input Data Width\n    // Accumulation of all AXI input signal's width\n    parameter C_DIN_WIDTH_WACH               = 1,\n    parameter C_DIN_WIDTH_WDCH               = 1,\n    parameter C_DIN_WIDTH_WRCH               = 1,\n    parameter C_DIN_WIDTH_RACH               = 1,\n    parameter C_DIN_WIDTH_RDCH               = 1,\n    parameter C_DIN_WIDTH_AXIS               = 1,\n\n    parameter C_WR_DEPTH_WACH                = 16,\n    parameter C_WR_DEPTH_WDCH                = 16,\n    parameter C_WR_DEPTH_WRCH                = 16,\n    parameter C_WR_DEPTH_RACH                = 16,\n    parameter C_WR_DEPTH_RDCH                = 16,\n    parameter C_WR_DEPTH_AXIS                = 16,\n\n    parameter C_WR_PNTR_WIDTH_WACH           = 4,\n    parameter C_WR_PNTR_WIDTH_WDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_WRCH           = 4,\n    parameter C_WR_PNTR_WIDTH_RACH           = 4,\n    parameter C_WR_PNTR_WIDTH_RDCH           = 4,\n    parameter C_WR_PNTR_WIDTH_AXIS           = 4,\n\n    parameter C_HAS_DATA_COUNTS_WACH         = 0,\n    parameter C_HAS_DATA_COUNTS_WDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_WRCH         = 0,\n    parameter C_HAS_DATA_COUNTS_RACH         = 0,\n    parameter C_HAS_DATA_COUNTS_RDCH         = 0,\n    parameter C_HAS_DATA_COUNTS_AXIS         = 0,\n\n    parameter C_HAS_PROG_FLAGS_WACH          = 0,\n    parameter C_HAS_PROG_FLAGS_WDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_WRCH          = 0,\n    parameter C_HAS_PROG_FLAGS_RACH          = 0,\n    parameter C_HAS_PROG_FLAGS_RDCH          = 0,\n    parameter C_HAS_PROG_FLAGS_AXIS          = 0,\n\n    parameter C_PROG_FULL_TYPE_WACH          = 0,\n    parameter C_PROG_FULL_TYPE_WDCH          = 0,\n    parameter C_PROG_FULL_TYPE_WRCH          = 0,\n    parameter C_PROG_FULL_TYPE_RACH          = 0,\n    parameter C_PROG_FULL_TYPE_RDCH          = 0,\n    parameter C_PROG_FULL_TYPE_AXIS          = 0,\n\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH      = 0,\n    parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS      = 0,\n\n    parameter C_PROG_EMPTY_TYPE_WACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_WRCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RACH         = 0,\n    parameter C_PROG_EMPTY_TYPE_RDCH         = 0,\n    parameter C_PROG_EMPTY_TYPE_AXIS         = 0,\n\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH     = 0,\n    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS     = 0,\n\n    parameter C_REG_SLICE_MODE_WACH          = 0,\n    parameter C_REG_SLICE_MODE_WDCH          = 0,\n    parameter C_REG_SLICE_MODE_WRCH          = 0,\n    parameter C_REG_SLICE_MODE_RACH          = 0,\n    parameter C_REG_SLICE_MODE_RDCH          = 0,\n    parameter C_REG_SLICE_MODE_AXIS          = 0\n\n    )\n\n   (\n    //------------------------------------------------------------------------------\n    // Input and Output Declarations\n    //------------------------------------------------------------------------------\n\n    // Conventional FIFO Interface Signals\n    input                               backup,\n    input                               backup_marker,\n    input                               clk,\n    input                               rst,\n    input                               srst,\n    input                               wr_clk,\n    input                               wr_rst,\n    input                               rd_clk,\n    input                               rd_rst,\n    input [C_DIN_WIDTH-1:0]             din,\n    input                               wr_en,\n    input                               rd_en,\n    // Optional inputs\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_assert,\n    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_negate,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_assert,\n    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_negate,\n    input                               int_clk,\n    input                               injectdbiterr,\n    input                               injectsbiterr,\n    input                               sleep,\n\n    output [C_DOUT_WIDTH-1:0]           dout,\n    output                              full,\n    output                              almost_full,\n    output                              wr_ack,\n    output                              overflow,\n    output                              empty,\n    output                              almost_empty,\n    output                              valid,\n    output                              underflow,\n    output [C_DATA_COUNT_WIDTH-1:0]     data_count,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]  rd_data_count,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count,\n    output                              prog_full,\n    output                              prog_empty,\n    output                              sbiterr,\n    output                              dbiterr,\n    output                              wr_rst_busy,\n    output                              rd_rst_busy,\n\n\n    // AXI Global Signal\n    input                               m_aclk,\n    input                               s_aclk,\n    input                               s_aresetn,\n    input                               s_aclk_en,\n    input                               m_aclk_en,\n    \n    // AXI Full/Lite Slave Write Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_awid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_awaddr,\n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_awlen,\n    input [3-1:0]                       s_axi_awsize,\n    input [2-1:0]                       s_axi_awburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_awlock,\n    input [4-1:0]                       s_axi_awcache,\n    input [3-1:0]                       s_axi_awprot,\n    input [4-1:0]                       s_axi_awqos,\n    input [4-1:0]                       s_axi_awregion,\n    input [C_AXI_AWUSER_WIDTH-1:0]      s_axi_awuser,\n    input                               s_axi_awvalid,\n    output                              s_axi_awready,\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_wid,\n    input [C_AXI_DATA_WIDTH-1:0]        s_axi_wdata,\n    input [C_AXI_DATA_WIDTH/8-1:0]      s_axi_wstrb,\n    input                               s_axi_wlast,\n    input [C_AXI_WUSER_WIDTH-1:0]       s_axi_wuser,\n    input                               s_axi_wvalid,\n    output                              s_axi_wready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_bid,\n    output [2-1:0]                      s_axi_bresp,\n    output [C_AXI_BUSER_WIDTH-1:0]      s_axi_buser,\n    output                              s_axi_bvalid,\n    input                               s_axi_bready,\n    \n    // AXI Full/Lite Master Write Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_awid,\n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,\n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_awlen,\n    output [3-1:0]                      m_axi_awsize,\n    output [2-1:0]                      m_axi_awburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_awlock,\n    output [4-1:0]                      m_axi_awcache,\n    output [3-1:0]                      m_axi_awprot,\n    output [4-1:0]                      m_axi_awqos,\n    output [4-1:0]                      m_axi_awregion,\n    output [C_AXI_AWUSER_WIDTH-1:0]     m_axi_awuser,\n    output                              m_axi_awvalid,\n    input                               m_axi_awready,\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_wid,\n    output [C_AXI_DATA_WIDTH-1:0]       m_axi_wdata,\n    output [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb,\n    output                              m_axi_wlast,\n    output [C_AXI_WUSER_WIDTH-1:0]      m_axi_wuser,\n    output                              m_axi_wvalid,\n    input                               m_axi_wready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_bid,\n    input [2-1:0]                       m_axi_bresp,\n    input [C_AXI_BUSER_WIDTH-1:0]       m_axi_buser,\n    input                               m_axi_bvalid,\n    output                              m_axi_bready,\n    \n    \n    // AXI Full/Lite Slave Read Channel (write side)\n    input [C_AXI_ID_WIDTH-1:0]          s_axi_arid,\n    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_araddr, \n    input [C_AXI_LEN_WIDTH-1:0]         s_axi_arlen,\n    input [3-1:0]                       s_axi_arsize,\n    input [2-1:0]                       s_axi_arburst,\n    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_arlock,\n    input [4-1:0]                       s_axi_arcache,\n    input [3-1:0]                       s_axi_arprot,\n    input [4-1:0]                       s_axi_arqos,\n    input [4-1:0]                       s_axi_arregion,\n    input [C_AXI_ARUSER_WIDTH-1:0]      s_axi_aruser,\n    input                               s_axi_arvalid,\n    output                              s_axi_arready,\n    output [C_AXI_ID_WIDTH-1:0]         s_axi_rid,       \n    output [C_AXI_DATA_WIDTH-1:0]       s_axi_rdata, \n    output [2-1:0]                      s_axi_rresp,\n    output                              s_axi_rlast,\n    output [C_AXI_RUSER_WIDTH-1:0]      s_axi_ruser,\n    output                              s_axi_rvalid,\n    input                               s_axi_rready,\n    \n    \n    \n    // AXI Full/Lite Master Read Channel (read side)\n    output [C_AXI_ID_WIDTH-1:0]         m_axi_arid,        \n    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,  \n    output [C_AXI_LEN_WIDTH-1:0]        m_axi_arlen,\n    output [3-1:0]                      m_axi_arsize,\n    output [2-1:0]                      m_axi_arburst,\n    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_arlock,\n    output [4-1:0]                      m_axi_arcache,\n    output [3-1:0]                      m_axi_arprot,\n    output [4-1:0]                      m_axi_arqos,\n    output [4-1:0]                      m_axi_arregion,\n    output [C_AXI_ARUSER_WIDTH-1:0]     m_axi_aruser,\n    output                              m_axi_arvalid,\n    input                               m_axi_arready,\n    input [C_AXI_ID_WIDTH-1:0]          m_axi_rid,        \n    input [C_AXI_DATA_WIDTH-1:0]        m_axi_rdata,  \n    input [2-1:0]                       m_axi_rresp,\n    input                               m_axi_rlast,\n    input [C_AXI_RUSER_WIDTH-1:0]       m_axi_ruser,\n    input                               m_axi_rvalid,\n    output                              m_axi_rready,\n    \n    \n    // AXI Streaming Slave Signals (Write side)\n    input                               s_axis_tvalid,\n    output                              s_axis_tready,\n    input [C_AXIS_TDATA_WIDTH-1:0]      s_axis_tdata,\n    input [C_AXIS_TSTRB_WIDTH-1:0]      s_axis_tstrb,\n    input [C_AXIS_TKEEP_WIDTH-1:0]      s_axis_tkeep,\n    input                               s_axis_tlast,\n    input [C_AXIS_TID_WIDTH-1:0]        s_axis_tid,\n    input [C_AXIS_TDEST_WIDTH-1:0]      s_axis_tdest,\n    input [C_AXIS_TUSER_WIDTH-1:0]      s_axis_tuser,\n    \n    // AXI Streaming Master Signals (Read side)\n    output                              m_axis_tvalid,\n    input                               m_axis_tready,\n    output [C_AXIS_TDATA_WIDTH-1:0]     m_axis_tdata,\n    output [C_AXIS_TSTRB_WIDTH-1:0]     m_axis_tstrb,\n    output [C_AXIS_TKEEP_WIDTH-1:0]     m_axis_tkeep,\n    output                              m_axis_tlast,\n    output [C_AXIS_TID_WIDTH-1:0]       m_axis_tid,\n    output [C_AXIS_TDEST_WIDTH-1:0]     m_axis_tdest,\n    output [C_AXIS_TUSER_WIDTH-1:0]     m_axis_tuser,\n    \n           \n    \n    \n    // AXI Full/Lite Write Address Channel signals\n    input                               axi_aw_injectsbiterr,\n    input                               axi_aw_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_rd_data_count,\n    output                              axi_aw_sbiterr,\n    output                              axi_aw_dbiterr,\n    output                              axi_aw_overflow,\n    output                              axi_aw_underflow,\n    output                              axi_aw_prog_full,\n    output                              axi_aw_prog_empty,\n    \n    \n    // AXI Full/Lite Write Data Channel signals\n    input                               axi_w_injectsbiterr,\n    input                               axi_w_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_rd_data_count,\n    output                              axi_w_sbiterr,\n    output                              axi_w_dbiterr,\n    output                              axi_w_overflow,\n    output                              axi_w_underflow,\n    output                              axi_w_prog_full,\n    output                              axi_w_prog_empty,\n    \n    \n    // AXI Full/Lite Write Response Channel signals\n    input                               axi_b_injectsbiterr,\n    input                               axi_b_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_wr_data_count,\n    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_rd_data_count,\n    output                              axi_b_sbiterr,\n    output                              axi_b_dbiterr,\n    output                              axi_b_overflow,\n    output                              axi_b_underflow,\n    output                              axi_b_prog_full,\n    output                              axi_b_prog_empty,\n    \n    \n    \n    // AXI Full/Lite Read Address Channel signals\n    input                               axi_ar_injectsbiterr,\n    input                               axi_ar_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_rd_data_count,\n    output                              axi_ar_sbiterr,\n    output                              axi_ar_dbiterr,\n    output                              axi_ar_overflow,\n    output                              axi_ar_underflow,\n    output                              axi_ar_prog_full,\n    output                              axi_ar_prog_empty,\n\n    \n    // AXI Full/Lite Read Data Channel Signals\n    input                               axi_r_injectsbiterr,\n    input                               axi_r_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_wr_data_count,\n    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_rd_data_count,\n    output                              axi_r_sbiterr,\n    output                              axi_r_dbiterr,\n    output                              axi_r_overflow,\n    output                              axi_r_underflow,\n    output                              axi_r_prog_full,\n    output                              axi_r_prog_empty,\n\n    \n    // AXI Streaming FIFO Related Signals\n    input                               axis_injectsbiterr,\n    input                               axis_injectdbiterr,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_full_thresh,\n    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_empty_thresh,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_wr_data_count,\n    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_rd_data_count,\n    output                              axis_sbiterr,\n    output                              axis_dbiterr,\n    output                              axis_overflow,\n    output                              axis_underflow,\n    output                              axis_prog_full,\n    output                              axis_prog_empty\n\n    );\n\n    wire                              BACKUP;\n    wire                              BACKUP_MARKER;\n    wire                              CLK;\n    wire                              RST;\n    wire                              SRST;\n    wire                              WR_CLK;\n    wire                              WR_RST;\n    wire                              RD_CLK;\n    wire                              RD_RST;\n    wire [C_DIN_WIDTH-1:0]            DIN;\n    wire                              WR_EN;\n    wire                              RD_EN;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_ASSERT;\n    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_NEGATE;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_ASSERT;\n    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_NEGATE;\n    wire                              INT_CLK;\n    wire                              INJECTDBITERR;\n    wire                              INJECTSBITERR;\n    wire                              SLEEP;\n    wire [C_DOUT_WIDTH-1:0]           DOUT;\n    wire                              FULL;\n    wire                              ALMOST_FULL;\n    wire                              WR_ACK;\n    wire                              OVERFLOW;\n    wire                              EMPTY;\n    wire                              ALMOST_EMPTY;\n    wire                              VALID;\n    wire                              UNDERFLOW;\n    wire [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT;\n    wire [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT;\n    wire                              PROG_FULL;\n    wire                              PROG_EMPTY;\n    wire                              SBITERR;\n    wire                              DBITERR;\n    wire                              WR_RST_BUSY;\n    wire                              RD_RST_BUSY;\n    wire                              M_ACLK;\n    wire                              S_ACLK;\n    wire                              S_ARESETN;\n    wire                              S_ACLK_EN;\n    wire                              M_ACLK_EN;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_AWLEN;\n    wire [3-1:0]                      S_AXI_AWSIZE;\n    wire [2-1:0]                      S_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_AWLOCK;\n    wire [4-1:0]                      S_AXI_AWCACHE;\n    wire [3-1:0]                      S_AXI_AWPROT;\n    wire [4-1:0]                      S_AXI_AWQOS;\n    wire [4-1:0]                      S_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     S_AXI_AWUSER;\n    wire                              S_AXI_AWVALID;\n    wire                              S_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     S_AXI_WSTRB;\n    wire                              S_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      S_AXI_WUSER;\n    wire                              S_AXI_WVALID;\n    wire                              S_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_BID;\n    wire [2-1:0]                      S_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      S_AXI_BUSER;\n    wire                              S_AXI_BVALID;\n    wire                              S_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_AWID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_AWADDR;\n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_AWLEN;\n    wire [3-1:0]                      M_AXI_AWSIZE;\n    wire [2-1:0]                      M_AXI_AWBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_AWLOCK;\n    wire [4-1:0]                      M_AXI_AWCACHE;\n    wire [3-1:0]                      M_AXI_AWPROT;\n    wire [4-1:0]                      M_AXI_AWQOS;\n    wire [4-1:0]                      M_AXI_AWREGION;\n    wire [C_AXI_AWUSER_WIDTH-1:0]     M_AXI_AWUSER;\n    wire                              M_AXI_AWVALID;\n    wire                              M_AXI_AWREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_WID;\n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_WDATA;\n    wire [C_AXI_DATA_WIDTH/8-1:0]     M_AXI_WSTRB;\n    wire                              M_AXI_WLAST;\n    wire [C_AXI_WUSER_WIDTH-1:0]      M_AXI_WUSER;\n    wire                              M_AXI_WVALID;\n    wire                              M_AXI_WREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_BID;\n    wire [2-1:0]                      M_AXI_BRESP;\n    wire [C_AXI_BUSER_WIDTH-1:0]      M_AXI_BUSER;\n    wire                              M_AXI_BVALID;\n    wire                              M_AXI_BREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_ARID;\n    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_ARADDR; \n    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_ARLEN;\n    wire [3-1:0]                      S_AXI_ARSIZE;\n    wire [2-1:0]                      S_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_ARLOCK;\n    wire [4-1:0]                      S_AXI_ARCACHE;\n    wire [3-1:0]                      S_AXI_ARPROT;\n    wire [4-1:0]                      S_AXI_ARQOS;\n    wire [4-1:0]                      S_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     S_AXI_ARUSER;\n    wire                              S_AXI_ARVALID;\n    wire                              S_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_RID;       \n    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_RDATA; \n    wire [2-1:0]                      S_AXI_RRESP;\n    wire                              S_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      S_AXI_RUSER;\n    wire                              S_AXI_RVALID;\n    wire                              S_AXI_RREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_ARID;        \n    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_ARADDR;  \n    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_ARLEN;\n    wire [3-1:0]                      M_AXI_ARSIZE;\n    wire [2-1:0]                      M_AXI_ARBURST;\n    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_ARLOCK;\n    wire [4-1:0]                      M_AXI_ARCACHE;\n    wire [3-1:0]                      M_AXI_ARPROT;\n    wire [4-1:0]                      M_AXI_ARQOS;\n    wire [4-1:0]                      M_AXI_ARREGION;\n    wire [C_AXI_ARUSER_WIDTH-1:0]     M_AXI_ARUSER;\n    wire                              M_AXI_ARVALID;\n    wire                              M_AXI_ARREADY;\n    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_RID;        \n    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_RDATA;  \n    wire [2-1:0]                      M_AXI_RRESP;\n    wire                              M_AXI_RLAST;\n    wire [C_AXI_RUSER_WIDTH-1:0]      M_AXI_RUSER;\n    wire                              M_AXI_RVALID;\n    wire                              M_AXI_RREADY;\n    wire                              S_AXIS_TVALID;\n    wire                              S_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     S_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     S_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     S_AXIS_TKEEP;\n    wire                              S_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       S_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     S_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     S_AXIS_TUSER;\n    wire                              M_AXIS_TVALID;\n    wire                              M_AXIS_TREADY;\n    wire [C_AXIS_TDATA_WIDTH-1:0]     M_AXIS_TDATA;\n    wire [C_AXIS_TSTRB_WIDTH-1:0]     M_AXIS_TSTRB;\n    wire [C_AXIS_TKEEP_WIDTH-1:0]     M_AXIS_TKEEP;\n    wire                              M_AXIS_TLAST;\n    wire [C_AXIS_TID_WIDTH-1:0]       M_AXIS_TID;\n    wire [C_AXIS_TDEST_WIDTH-1:0]     M_AXIS_TDEST;\n    wire [C_AXIS_TUSER_WIDTH-1:0]     M_AXIS_TUSER;\n    wire                              AXI_AW_INJECTSBITERR;\n    wire                              AXI_AW_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_RD_DATA_COUNT;\n    wire                              AXI_AW_SBITERR;\n    wire                              AXI_AW_DBITERR;\n    wire                              AXI_AW_OVERFLOW;\n    wire                              AXI_AW_UNDERFLOW;\n    wire                              AXI_AW_PROG_FULL;\n    wire                              AXI_AW_PROG_EMPTY;\n    wire                              AXI_W_INJECTSBITERR;\n    wire                              AXI_W_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_RD_DATA_COUNT;\n    wire                              AXI_W_SBITERR;\n    wire                              AXI_W_DBITERR;\n    wire                              AXI_W_OVERFLOW;\n    wire                              AXI_W_UNDERFLOW;\n    wire                              AXI_W_PROG_FULL;\n    wire                              AXI_W_PROG_EMPTY;\n    wire                              AXI_B_INJECTSBITERR;\n    wire                              AXI_B_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_RD_DATA_COUNT;\n    wire                              AXI_B_SBITERR;\n    wire                              AXI_B_DBITERR;\n    wire                              AXI_B_OVERFLOW;\n    wire                              AXI_B_UNDERFLOW;\n    wire                              AXI_B_PROG_FULL;\n    wire                              AXI_B_PROG_EMPTY;\n    wire                              AXI_AR_INJECTSBITERR;\n    wire                              AXI_AR_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_RD_DATA_COUNT;\n    wire                              AXI_AR_SBITERR;\n    wire                              AXI_AR_DBITERR;\n    wire                              AXI_AR_OVERFLOW;\n    wire                              AXI_AR_UNDERFLOW;\n    wire                              AXI_AR_PROG_FULL;\n    wire                              AXI_AR_PROG_EMPTY;\n    wire                              AXI_R_INJECTSBITERR;\n    wire                              AXI_R_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_RD_DATA_COUNT;\n    wire                              AXI_R_SBITERR;\n    wire                              AXI_R_DBITERR;\n    wire                              AXI_R_OVERFLOW;\n    wire                              AXI_R_UNDERFLOW;\n    wire                              AXI_R_PROG_FULL;\n    wire                              AXI_R_PROG_EMPTY;\n    wire                              AXIS_INJECTSBITERR;\n    wire                              AXIS_INJECTDBITERR;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_FULL_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_EMPTY_THRESH;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_WR_DATA_COUNT;\n    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_RD_DATA_COUNT;\n    wire                              AXIS_SBITERR;\n    wire                              AXIS_DBITERR;\n    wire                              AXIS_OVERFLOW;\n    wire                              AXIS_UNDERFLOW;\n    wire                              AXIS_PROG_FULL;\n    wire                              AXIS_PROG_EMPTY;\n    wire [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count_in;\n    wire                              wr_rst_int;\n    wire                              rd_rst_int;\n    wire                              wr_rst_busy_o;\n    wire                              wr_rst_busy_ntve;\n    wire                              wr_rst_busy_axis;\n    wire                              wr_rst_busy_wach;\n    wire                              wr_rst_busy_wdch;\n    wire                              wr_rst_busy_wrch;\n    wire                              wr_rst_busy_rach;\n    wire                              wr_rst_busy_rdch;\n\n\n\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n\n\n\n    // Conventional FIFO Interface Signals\n    assign BACKUP                 = backup;\n    assign BACKUP_MARKER          = backup_marker;\n    assign CLK                    = clk;\n    assign RST                    = rst;\n    assign SRST                   = srst;\n    assign WR_CLK                 = wr_clk;\n    assign WR_RST                 = wr_rst;\n    assign RD_CLK                 = rd_clk;\n    assign RD_RST                 = rd_rst;\n    assign WR_EN                  = wr_en;\n    assign RD_EN                  = rd_en;\n    assign INT_CLK                = int_clk;\n    assign INJECTDBITERR          = injectdbiterr;\n    assign INJECTSBITERR          = injectsbiterr;\n    assign SLEEP                  = sleep;\n    assign full                   = FULL;\n    assign almost_full            = ALMOST_FULL;\n    assign wr_ack                 = WR_ACK;\n    assign overflow               = OVERFLOW;\n    assign empty                  = EMPTY;\n    assign almost_empty           = ALMOST_EMPTY;\n    assign valid                  = VALID;\n    assign underflow              = UNDERFLOW;\n    assign prog_full              = PROG_FULL;\n    assign prog_empty             = PROG_EMPTY;\n    assign sbiterr                = SBITERR;\n    assign dbiterr                = DBITERR;\n//    assign wr_rst_busy            = WR_RST_BUSY | wr_rst_busy_o;\n    assign wr_rst_busy            = wr_rst_busy_o;\n    assign rd_rst_busy            = RD_RST_BUSY;\n    assign M_ACLK                 = m_aclk;\n    assign S_ACLK                 = s_aclk;\n    assign S_ARESETN              = s_aresetn;\n    assign S_ACLK_EN              = s_aclk_en;\n    assign M_ACLK_EN              = m_aclk_en;\n    assign S_AXI_AWVALID          = s_axi_awvalid;\n    assign s_axi_awready          = S_AXI_AWREADY;\n    assign S_AXI_WLAST            = s_axi_wlast;\n    assign S_AXI_WVALID           = s_axi_wvalid;\n    assign s_axi_wready           = S_AXI_WREADY;\n    assign s_axi_bvalid           = S_AXI_BVALID;\n    assign S_AXI_BREADY           = s_axi_bready;\n    assign m_axi_awvalid          = M_AXI_AWVALID;\n    assign M_AXI_AWREADY          = m_axi_awready;\n    assign m_axi_wlast            = M_AXI_WLAST;\n    assign m_axi_wvalid           = M_AXI_WVALID;\n    assign M_AXI_WREADY           = m_axi_wready;\n    assign M_AXI_BVALID           = m_axi_bvalid;\n    assign m_axi_bready           = M_AXI_BREADY;\n    assign S_AXI_ARVALID          = s_axi_arvalid;\n    assign s_axi_arready          = S_AXI_ARREADY;\n    assign s_axi_rlast            = S_AXI_RLAST;\n    assign s_axi_rvalid           = S_AXI_RVALID;\n    assign S_AXI_RREADY           = s_axi_rready;\n    assign m_axi_arvalid          = M_AXI_ARVALID;\n    assign M_AXI_ARREADY          = m_axi_arready;\n    assign M_AXI_RLAST            = m_axi_rlast;\n    assign M_AXI_RVALID           = m_axi_rvalid;\n    assign m_axi_rready           = M_AXI_RREADY;\n    assign S_AXIS_TVALID          = s_axis_tvalid;\n    assign s_axis_tready          = S_AXIS_TREADY;\n    assign S_AXIS_TLAST           = s_axis_tlast;\n    assign m_axis_tvalid          = M_AXIS_TVALID;\n    assign M_AXIS_TREADY          = m_axis_tready;\n    assign m_axis_tlast           = M_AXIS_TLAST;\n    assign AXI_AW_INJECTSBITERR   = axi_aw_injectsbiterr;\n    assign AXI_AW_INJECTDBITERR   = axi_aw_injectdbiterr;\n    assign axi_aw_sbiterr         = AXI_AW_SBITERR;\n    assign axi_aw_dbiterr         = AXI_AW_DBITERR;\n    assign axi_aw_overflow        = AXI_AW_OVERFLOW;\n    assign axi_aw_underflow       = AXI_AW_UNDERFLOW;\n    assign axi_aw_prog_full       = AXI_AW_PROG_FULL;\n    assign axi_aw_prog_empty      = AXI_AW_PROG_EMPTY;\n    assign AXI_W_INJECTSBITERR    = axi_w_injectsbiterr;\n    assign AXI_W_INJECTDBITERR    = axi_w_injectdbiterr;\n    assign axi_w_sbiterr          = AXI_W_SBITERR;\n    assign axi_w_dbiterr          = AXI_W_DBITERR;\n    assign axi_w_overflow         = AXI_W_OVERFLOW;\n    assign axi_w_underflow        = AXI_W_UNDERFLOW;\n    assign axi_w_prog_full        = AXI_W_PROG_FULL;\n    assign axi_w_prog_empty       = AXI_W_PROG_EMPTY;\n    assign AXI_B_INJECTSBITERR    = axi_b_injectsbiterr;\n    assign AXI_B_INJECTDBITERR    = axi_b_injectdbiterr;\n    assign axi_b_sbiterr          = AXI_B_SBITERR;\n    assign axi_b_dbiterr          = AXI_B_DBITERR;\n    assign axi_b_overflow         = AXI_B_OVERFLOW;\n    assign axi_b_underflow        = AXI_B_UNDERFLOW;\n    assign axi_b_prog_full        = AXI_B_PROG_FULL;\n    assign axi_b_prog_empty       = AXI_B_PROG_EMPTY;\n    assign AXI_AR_INJECTSBITERR   = axi_ar_injectsbiterr;\n    assign AXI_AR_INJECTDBITERR   = axi_ar_injectdbiterr;\n    assign axi_ar_sbiterr         = AXI_AR_SBITERR;\n    assign axi_ar_dbiterr         = AXI_AR_DBITERR;\n    assign axi_ar_overflow        = AXI_AR_OVERFLOW;\n    assign axi_ar_underflow       = AXI_AR_UNDERFLOW;\n    assign axi_ar_prog_full       = AXI_AR_PROG_FULL;\n    assign axi_ar_prog_empty      = AXI_AR_PROG_EMPTY;\n    assign AXI_R_INJECTSBITERR    = axi_r_injectsbiterr;\n    assign AXI_R_INJECTDBITERR    = axi_r_injectdbiterr;\n    assign axi_r_sbiterr          = AXI_R_SBITERR;\n    assign axi_r_dbiterr          = AXI_R_DBITERR;\n    assign axi_r_overflow         = AXI_R_OVERFLOW;\n    assign axi_r_underflow        = AXI_R_UNDERFLOW;\n    assign axi_r_prog_full        = AXI_R_PROG_FULL;\n    assign axi_r_prog_empty       = AXI_R_PROG_EMPTY;\n    assign AXIS_INJECTSBITERR     = axis_injectsbiterr;\n    assign AXIS_INJECTDBITERR     = axis_injectdbiterr;\n    assign axis_sbiterr           = AXIS_SBITERR;\n    assign axis_dbiterr           = AXIS_DBITERR;\n    assign axis_overflow          = AXIS_OVERFLOW;\n    assign axis_underflow         = AXIS_UNDERFLOW;\n    assign axis_prog_full         = AXIS_PROG_FULL;\n    assign axis_prog_empty        = AXIS_PROG_EMPTY;\n\n\n    assign DIN                       = din;\n    assign PROG_EMPTY_THRESH         = prog_empty_thresh;\n    assign PROG_EMPTY_THRESH_ASSERT  = prog_empty_thresh_assert;\n    assign PROG_EMPTY_THRESH_NEGATE  = prog_empty_thresh_negate;\n    assign PROG_FULL_THRESH          = prog_full_thresh;\n    assign PROG_FULL_THRESH_ASSERT   = prog_full_thresh_assert;\n    assign PROG_FULL_THRESH_NEGATE   = prog_full_thresh_negate;\n    assign dout                      = DOUT;\n    assign data_count                = DATA_COUNT;\n    assign rd_data_count             = RD_DATA_COUNT;\n    assign wr_data_count             = WR_DATA_COUNT;\n    assign S_AXI_AWID                = s_axi_awid;\n    assign S_AXI_AWADDR              = s_axi_awaddr;\n    assign S_AXI_AWLEN               = s_axi_awlen;\n    assign S_AXI_AWSIZE              = s_axi_awsize;\n    assign S_AXI_AWBURST             = s_axi_awburst;\n    assign S_AXI_AWLOCK              = s_axi_awlock;\n    assign S_AXI_AWCACHE             = s_axi_awcache;\n    assign S_AXI_AWPROT              = s_axi_awprot;\n    assign S_AXI_AWQOS               = s_axi_awqos;\n    assign S_AXI_AWREGION            = s_axi_awregion;\n    assign S_AXI_AWUSER              = s_axi_awuser;\n    assign S_AXI_WID                 = s_axi_wid;\n    assign S_AXI_WDATA               = s_axi_wdata;\n    assign S_AXI_WSTRB               = s_axi_wstrb;\n    assign S_AXI_WUSER               = s_axi_wuser;\n    assign s_axi_bid                 = S_AXI_BID;\n    assign s_axi_bresp               = S_AXI_BRESP;\n    assign s_axi_buser               = S_AXI_BUSER;\n    assign m_axi_awid                = M_AXI_AWID;\n    assign m_axi_awaddr              = M_AXI_AWADDR;\n    assign m_axi_awlen               = M_AXI_AWLEN;\n    assign m_axi_awsize              = M_AXI_AWSIZE;\n    assign m_axi_awburst             = M_AXI_AWBURST;\n    assign m_axi_awlock              = M_AXI_AWLOCK;\n    assign m_axi_awcache             = M_AXI_AWCACHE;\n    assign m_axi_awprot              = M_AXI_AWPROT;\n    assign m_axi_awqos               = M_AXI_AWQOS;\n    assign m_axi_awregion            = M_AXI_AWREGION;\n    assign m_axi_awuser              = M_AXI_AWUSER;\n    assign m_axi_wid                 = M_AXI_WID;\n    assign m_axi_wdata               = M_AXI_WDATA;\n    assign m_axi_wstrb               = M_AXI_WSTRB;\n    assign m_axi_wuser               = M_AXI_WUSER;\n    assign M_AXI_BID                 = m_axi_bid;\n    assign M_AXI_BRESP               = m_axi_bresp;\n    assign M_AXI_BUSER               = m_axi_buser;\n    assign S_AXI_ARID                = s_axi_arid;\n    assign S_AXI_ARADDR              = s_axi_araddr; \n    assign S_AXI_ARLEN               = s_axi_arlen;\n    assign S_AXI_ARSIZE              = s_axi_arsize;\n    assign S_AXI_ARBURST             = s_axi_arburst;\n    assign S_AXI_ARLOCK              = s_axi_arlock;\n    assign S_AXI_ARCACHE             = s_axi_arcache;\n    assign S_AXI_ARPROT              = s_axi_arprot;\n    assign S_AXI_ARQOS               = s_axi_arqos;\n    assign S_AXI_ARREGION            = s_axi_arregion;\n    assign S_AXI_ARUSER              = s_axi_aruser;\n    assign s_axi_rid                 = S_AXI_RID;\n    assign s_axi_rdata               = S_AXI_RDATA;\n    assign s_axi_rresp               = S_AXI_RRESP;\n    assign s_axi_ruser               = S_AXI_RUSER;\n    assign m_axi_arid                = M_AXI_ARID;        \n    assign m_axi_araddr              = M_AXI_ARADDR;  \n    assign m_axi_arlen               = M_AXI_ARLEN;\n    assign m_axi_arsize              = M_AXI_ARSIZE;\n    assign m_axi_arburst             = M_AXI_ARBURST;\n    assign m_axi_arlock              = M_AXI_ARLOCK;\n    assign m_axi_arcache             = M_AXI_ARCACHE;\n    assign m_axi_arprot              = M_AXI_ARPROT;\n    assign m_axi_arqos               = M_AXI_ARQOS;\n    assign m_axi_arregion            = M_AXI_ARREGION;\n    assign m_axi_aruser              = M_AXI_ARUSER;\n    assign M_AXI_RID                 = m_axi_rid;        \n    assign M_AXI_RDATA               = m_axi_rdata;  \n    assign M_AXI_RRESP               = m_axi_rresp;\n    assign M_AXI_RUSER               = m_axi_ruser;\n    assign S_AXIS_TDATA              = s_axis_tdata;\n    assign S_AXIS_TSTRB              = s_axis_tstrb;\n    assign S_AXIS_TKEEP              = s_axis_tkeep;\n    assign S_AXIS_TID                = s_axis_tid;\n    assign S_AXIS_TDEST              = s_axis_tdest;\n    assign S_AXIS_TUSER              = s_axis_tuser;\n    assign m_axis_tdata              = M_AXIS_TDATA;\n    assign m_axis_tstrb              = M_AXIS_TSTRB;\n    assign m_axis_tkeep              = M_AXIS_TKEEP;\n    assign m_axis_tid                = M_AXIS_TID;\n    assign m_axis_tdest              = M_AXIS_TDEST;\n    assign m_axis_tuser              = M_AXIS_TUSER;\n    assign AXI_AW_PROG_FULL_THRESH   = axi_aw_prog_full_thresh;\n    assign AXI_AW_PROG_EMPTY_THRESH  = axi_aw_prog_empty_thresh;\n    assign axi_aw_data_count         = AXI_AW_DATA_COUNT;\n    assign axi_aw_wr_data_count      = AXI_AW_WR_DATA_COUNT;\n    assign axi_aw_rd_data_count      = AXI_AW_RD_DATA_COUNT;\n    assign AXI_W_PROG_FULL_THRESH    = axi_w_prog_full_thresh;\n    assign AXI_W_PROG_EMPTY_THRESH   = axi_w_prog_empty_thresh;\n    assign axi_w_data_count          = AXI_W_DATA_COUNT;\n    assign axi_w_wr_data_count       = AXI_W_WR_DATA_COUNT;\n    assign axi_w_rd_data_count       = AXI_W_RD_DATA_COUNT;\n    assign AXI_B_PROG_FULL_THRESH    = axi_b_prog_full_thresh;\n    assign AXI_B_PROG_EMPTY_THRESH   = axi_b_prog_empty_thresh;\n    assign axi_b_data_count          = AXI_B_DATA_COUNT;\n    assign axi_b_wr_data_count       = AXI_B_WR_DATA_COUNT;\n    assign axi_b_rd_data_count       = AXI_B_RD_DATA_COUNT;\n    assign AXI_AR_PROG_FULL_THRESH   = axi_ar_prog_full_thresh;\n    assign AXI_AR_PROG_EMPTY_THRESH  = axi_ar_prog_empty_thresh;\n    assign axi_ar_data_count         = AXI_AR_DATA_COUNT;\n    assign axi_ar_wr_data_count      = AXI_AR_WR_DATA_COUNT;\n    assign axi_ar_rd_data_count      = AXI_AR_RD_DATA_COUNT;\n    assign AXI_R_PROG_FULL_THRESH    = axi_r_prog_full_thresh;\n    assign AXI_R_PROG_EMPTY_THRESH   = axi_r_prog_empty_thresh;\n    assign axi_r_data_count          = AXI_R_DATA_COUNT;\n    assign axi_r_wr_data_count       = AXI_R_WR_DATA_COUNT;\n    assign axi_r_rd_data_count       = AXI_R_RD_DATA_COUNT;\n    assign AXIS_PROG_FULL_THRESH     = axis_prog_full_thresh;\n    assign AXIS_PROG_EMPTY_THRESH    = axis_prog_empty_thresh;\n    assign axis_data_count           = AXIS_DATA_COUNT;\n    assign axis_wr_data_count        = AXIS_WR_DATA_COUNT;\n    assign axis_rd_data_count        = AXIS_RD_DATA_COUNT;\n\n\n  generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_COMMON_CLOCK \t\t(C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DATA_COUNT_WIDTH\t\t(C_DATA_COUNT_WIDTH),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH),\n        .C_DOUT_RST_VAL\t\t\t(C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),\n        .C_DOUT_WIDTH\t\t\t(C_DOUT_WIDTH),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n        .C_HAS_ALMOST_EMPTY\t\t(C_HAS_ALMOST_EMPTY),\n        .C_HAS_ALMOST_FULL\t\t(C_HAS_ALMOST_FULL),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_DATA_COUNT\t\t(C_HAS_DATA_COUNT),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_HAS_RD_DATA_COUNT\t\t(C_HAS_RD_DATA_COUNT),\n        .C_HAS_RD_RST\t\t\t(C_HAS_RD_RST),\n        .C_HAS_RST\t\t\t(C_HAS_RST),\n        .C_HAS_SRST\t\t\t(C_HAS_SRST),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_HAS_VALID\t\t\t(C_HAS_VALID),\n        .C_HAS_WR_ACK\t\t\t(C_HAS_WR_ACK),\n        .C_HAS_WR_DATA_COUNT\t\t(C_HAS_WR_DATA_COUNT),\n        .C_HAS_WR_RST\t\t\t(C_HAS_WR_RST),\n        .C_IMPLEMENTATION_TYPE\t\t(C_IMPLEMENTATION_TYPE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_MEMORY_TYPE\t\t\t(C_MEMORY_TYPE),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n        .C_PRELOAD_LATENCY\t\t(C_PRELOAD_LATENCY),\n        .C_PRELOAD_REGS\t\t\t(C_PRELOAD_REGS),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL),\n        .C_PROG_EMPTY_THRESH_NEGATE_VAL\t(C_PROG_EMPTY_THRESH_NEGATE_VAL),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL),\n        .C_PROG_FULL_THRESH_NEGATE_VAL\t(C_PROG_FULL_THRESH_NEGATE_VAL),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_RD_DATA_COUNT_WIDTH),\n        .C_RD_DEPTH\t\t\t(C_RD_DEPTH),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_RD_PNTR_WIDTH\t\t(C_RD_PNTR_WIDTH),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n        .C_USE_ECC                      (C_USE_ECC),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_EN_SAFETY_CKT\t\t(C_EN_SAFETY_CKT),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_USE_FWFT_DATA_COUNT\t\t(C_USE_FWFT_DATA_COUNT),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_DATA_COUNT_WIDTH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (C_ENABLE_RST_SYNC),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE),\n        .C_AXI_TYPE                     (C_AXI_TYPE),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE)\n      )\n    fifo_generator_v13_2_1_conv_dut\n      (\n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .CLK                      (CLK),\n        .RST                      (RST),\n        .SRST                     (SRST),\n        .WR_CLK                   (WR_CLK),\n        .WR_RST                   (WR_RST),\n        .RD_CLK                   (RD_CLK),\n        .RD_RST                   (RD_RST),\n        .DIN                      (DIN),\n        .WR_EN                    (WR_EN),\n        .RD_EN                    (RD_EN),\n        .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),\n        .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),\n        .PROG_FULL_THRESH         (PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),\n        .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),\n        .INT_CLK                  (INT_CLK),\n        .INJECTDBITERR            (INJECTDBITERR), \n        .INJECTSBITERR            (INJECTSBITERR),\n  \n        .DOUT                     (DOUT),\n        .FULL                     (FULL),\n        .ALMOST_FULL              (ALMOST_FULL),\n        .WR_ACK                   (WR_ACK),\n        .OVERFLOW                 (OVERFLOW),\n        .EMPTY                    (EMPTY),\n        .ALMOST_EMPTY             (ALMOST_EMPTY),\n        .VALID                    (VALID),\n        .UNDERFLOW                (UNDERFLOW),\n        .DATA_COUNT               (DATA_COUNT),\n        .RD_DATA_COUNT            (RD_DATA_COUNT),\n        .WR_DATA_COUNT            (wr_data_count_in),\n        .PROG_FULL                (PROG_FULL),\n        .PROG_EMPTY               (PROG_EMPTY),\n        .SBITERR                  (SBITERR),\n        .DBITERR                  (DBITERR),\n        .wr_rst_busy_o            (wr_rst_busy_o),\n        .wr_rst_busy              (wr_rst_busy_i),\n        .rd_rst_busy              (rd_rst_busy),\n        .wr_rst_i_out             (wr_rst_int),\n        .rd_rst_i_out             (rd_rst_int)\n       );\n  end endgenerate\n\n\n\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n  localparam C_AXI_SIZE_WIDTH   = 3;\n  localparam C_AXI_BURST_WIDTH  = 2;\n  localparam C_AXI_CACHE_WIDTH  = 4;\n  localparam C_AXI_PROT_WIDTH   = 3;\n  localparam C_AXI_QOS_WIDTH    = 4;\n  localparam C_AXI_REGION_WIDTH = 4;\n  localparam C_AXI_BRESP_WIDTH  = 2;\n  localparam C_AXI_RRESP_WIDTH  = 2;\n\n  localparam IS_AXI_STREAMING  = C_INTERFACE_TYPE == 1 ? 1 : 0;\n  localparam TDATA_OFFSET      = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;\n  localparam TSTRB_OFFSET      = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;\n  localparam TKEEP_OFFSET      = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;\n  localparam TID_OFFSET        = C_HAS_AXIS_TID   == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;\n  localparam TDEST_OFFSET      = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;\n  localparam TUSER_OFFSET      = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;\n  localparam LOG_DEPTH_AXIS    = find_log2(C_WR_DEPTH_AXIS); \n  localparam LOG_WR_DEPTH      = find_log2(C_WR_DEPTH); \n\n\n  function [LOG_DEPTH_AXIS-1:0] bin2gray;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      begin\n         bin2gray = x ^ (x>>1);\n      end\n   endfunction\n\n  function [LOG_DEPTH_AXIS-1:0] gray2bin;\n      input [LOG_DEPTH_AXIS-1:0] x;\n      integer                i;\n      begin\n         gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];\n         for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin\n            gray2bin[i] =  gray2bin[i+1] ^ x[i];\n         end\n      end\n   endfunction\n\nwire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;\nwire  [LOG_WR_DEPTH-1 : 0]  w_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;\nreg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;\nwire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;\nwire [LOG_WR_DEPTH : 0] r_inv_pad;\nwire [LOG_WR_DEPTH-1 : 0] d_cnt;\nreg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;\nreg adj_w_cnt_rd_pad_0 = 0;\nreg r_inv_pad_0 = 0;\n\n\n   genvar l;\n\n   generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage\n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (LOG_WR_DEPTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_int), \n         .CLK      (RD_CLK), \n         .DIN      (w_q[l-1]), \n         .DOUT     (w_q[l])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter\n    assign wr_eop_ad = WR_EN & !(FULL);\n    assign rd_eop_ad = RD_EN & !(EMPTY);\n\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt    <= 1'b0;\n      else if (wr_eop_ad)\n        w_cnt    <= w_cnt + 1;\n    end\n\n  always @ (posedge wr_rst_int or posedge WR_CLK)\n    begin\n      if (wr_rst_int)\n        w_cnt_gc    <= 1'b0;\n      else \n        w_cnt_gc    <= bin2gray(w_cnt);\n    end\n\n\n    assign  w_q[0]  = w_cnt_gc;\n    assign  w_cnt_gc_asreg_last       = w_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        w_cnt_rd    <= 1'b0;\n      else \n        w_cnt_rd    <= gray2bin(w_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        r_cnt    <= 1'b0;\n      else if (rd_eop_ad)\n        r_cnt    <= r_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;\n   assign r_inv_pad[LOG_WR_DEPTH : 1]        = ~r_cnt;\n   assign adj_w_cnt_rd_pad[0]                = adj_w_cnt_rd_pad_0;\n   assign r_inv_pad[0]                       = r_inv_pad_0;\n\n\n  always @ ( rd_eop_ad )\n    begin\n      if (!rd_eop_ad) begin\n        adj_w_cnt_rd_pad_0    <= 1'b1;\n        r_inv_pad_0           <= 1'b1;\n      end else begin \n        adj_w_cnt_rd_pad_0    <= 1'b0;\n        r_inv_pad_0           <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge rd_rst_int or posedge RD_CLK)\n    begin\n      if (rd_rst_int)\n        d_cnt_pad    <= 1'b0;\n      else \n        d_cnt_pad    <= adj_w_cnt_rd_pad + r_inv_pad ;\n    end\n\n   assign  d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;\n   assign  WR_DATA_COUNT = d_cnt;\n\n  end endgenerate // fifo_ic_adapter\n\n      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter\n   assign  WR_DATA_COUNT = wr_data_count_in;\n\n  end endgenerate // fifo_icn_adapter\n\n\n\n  wire                          inverted_reset = ~S_ARESETN;\n  wire                          axi_rs_rst;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_din          ;\n  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_dout         ;\n  wire                          axis_full         ;\n  wire                          axis_almost_full  ;\n  wire                          axis_empty        ;\n  wire                          axis_s_axis_tready;\n  wire                          axis_m_axis_tvalid;\n  wire                          axis_wr_en        ;\n  wire                          axis_rd_en        ;\n  wire                          axis_we           ;\n  wire                          axis_re           ;\n  wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;\n  reg                           axis_pkt_read = 1'b0;\n  wire                          axis_rd_rst;\n  wire                          axis_wr_rst;\n\n  generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||\n               C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst\n      reg                           rst_d1 = 0        ;\n      reg                           rst_d2 = 0        ;\n      reg [3:0]                    axi_rst = 4'h0     ;\n      always @ (posedge inverted_reset or posedge S_ACLK) begin\n        if (inverted_reset) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          axi_rst        <= 4'hf;\n        end else begin\n          rst_d1         <= #`TCQ 1'b0;\n          rst_d2         <= #`TCQ rst_d1;\n          axi_rst        <= #`TCQ {axi_rst[2:0],1'b0};\n        end\n      end\n\n      assign axi_rs_rst = axi_rst[3];//rst_d2;\n  end endgenerate // gaxi_rs_rst\n\n  generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming\n\n    // Write protection when almost full or prog_full is high\n    assign axis_we    = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : \n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign axis_re    = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :\n                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? axis_we & S_ACLK_EN : axis_we;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_INTERFACE_TYPE               (C_INTERFACE_TYPE),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 2  || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_AXIS),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_AXIS),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),\n        .C_USE_ECC                      (C_USE_ECC_AXIS),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_AXIS),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_axis_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (axis_wr_en),\n        .RD_EN                    (axis_rd_en),\n        .PROG_FULL_THRESH         (AXIS_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXIS_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n        .INJECTDBITERR            (AXIS_INJECTDBITERR), \n        .INJECTSBITERR            (AXIS_INJECTSBITERR),\n  \n        .DIN                      (axis_din),\n        .DOUT                     (axis_dout),\n        .FULL                     (axis_full),\n        .EMPTY                    (axis_empty),\n        .ALMOST_FULL              (axis_almost_full),\n        .PROG_FULL                (AXIS_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXIS_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (AXIS_OVERFLOW),\n        .VALID                    (),\n        .UNDERFLOW                (AXIS_UNDERFLOW),\n        .DATA_COUNT               (axis_dc),\n        .RD_DATA_COUNT            (AXIS_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXIS_WR_DATA_COUNT),\n        .SBITERR                  (AXIS_SBITERR),\n        .DBITERR                  (AXIS_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_axis),\n        .rd_rst_busy              (rd_rst_busy_axis),\n        .wr_rst_i_out             (axis_wr_rst),\n        .rd_rst_i_out             (axis_rd_rst),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign axis_s_axis_tready    = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;\n    assign axis_m_axis_tvalid    = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;\n    assign S_AXIS_TREADY         = axis_s_axis_tready;\n    assign M_AXIS_TVALID         = axis_m_axis_tvalid;\n\n  end endgenerate // axi_streaming\n\n  wire axis_wr_eop;\n  reg  axis_wr_eop_d1 = 1'b0;\n  wire axis_rd_eop;\n  integer  axis_pkt_cnt;\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)\n        axis_pkt_read    <= 1'b0;\n      else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_wr_eop_d1    <= 1'b0;\n      else\n        axis_wr_eop_d1   <= axis_wr_eop;\n    end\n\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_pkt_cnt    <= 0;\n      else if (axis_wr_eop_d1 && ~axis_rd_eop)\n        axis_pkt_cnt    <= axis_pkt_cnt + 1;\n      else if (axis_rd_eop && ~axis_wr_eop_d1)\n        axis_pkt_cnt    <= axis_pkt_cnt - 1;\n    end\n  end endgenerate // gaxis_pkt_fifo_cc\n\n\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;\nwire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;\nwire axis_rd_has_rst;\nwire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;\nwire  [LOG_DEPTH_AXIS-1 : 0]  wpkt_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;\nwire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE]  ;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;\nwire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;\nwire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;\nwire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;\nreg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;\nreg adj_axis_wpkt_cnt_rd_pad_0 = 0;\nreg rpkt_inv_pad_0 = 0;\nwire axis_af_rd ;\n\ngenerate if (C_HAS_RST == 1) begin : rst_blk_has\n  assign axis_rd_has_rst = axis_rd_rst;\nend endgenerate //rst_blk_has\n\ngenerate if (C_HAS_RST == 0) begin :rst_blk_no\n  assign axis_rd_has_rst = 1'b0;\nend endgenerate //rst_blk_no\n\n   genvar i;\n\n   generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage\n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (LOG_DEPTH_AXIS)\n        )\n     rd_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (wpkt_q[i-1]), \n         .DOUT     (wpkt_q[i])\n        );\n \n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (1)\n        )\n     wr_stg_inst\n        (\n         .RST      (axis_rd_has_rst), \n         .CLK      (M_ACLK), \n         .DIN      (axis_af_q[i-1]), \n         .DOUT     (axis_af_q[i])\n        );\n   end endgenerate // gpkt_cnt_sync_stage\n\n\n  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic\n    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n    assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n    always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_pkt_read    <= 1'b0;\n      else if (axis_rd_eop && (diff_pkt_cnt == 1))\n        axis_pkt_read    <= 1'b0;\n      else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))\n        axis_pkt_read    <= 1'b1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt    <= 1'b0;\n      else if (axis_wr_eop)\n        axis_wpkt_cnt    <= axis_wpkt_cnt + 1;\n    end\n\n  always @ (posedge axis_wr_rst or posedge S_ACLK)\n    begin\n      if (axis_wr_rst)\n        axis_wpkt_cnt_gc    <= 1'b0;\n      else \n        axis_wpkt_cnt_gc    <= bin2gray(axis_wpkt_cnt);\n    end\n\n\n    assign  wpkt_q[0]  = axis_wpkt_cnt_gc;\n    assign  axis_wpkt_cnt_gc_asreg_last       = wpkt_q[C_SYNCHRONIZER_STAGE];\n    assign  axis_af_q[0]                      = axis_almost_full;\n    //assign  axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];\n    assign  axis_af_rd                        = axis_af_q[C_SYNCHRONIZER_STAGE];\n\n\n\n  always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_wpkt_cnt_rd    <= 1'b0;\n      else \n        axis_wpkt_cnt_rd    <= gray2bin(axis_wpkt_cnt_gc_asreg_last);\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        axis_rpkt_cnt    <= 1'b0;\n      else if (axis_rd_eop)\n        axis_rpkt_cnt    <= axis_rpkt_cnt + 1;\n    end\n\n\n  // Take the difference of write and read packet count\n  // Logic is similar to rd_pe_as\n   assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;\n   assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1]             = ~axis_rpkt_cnt;\n   assign adj_axis_wpkt_cnt_rd_pad[0]                                = adj_axis_wpkt_cnt_rd_pad_0;\n   assign rpkt_inv_pad[0]                                            = rpkt_inv_pad_0;\n\n\n  always @ ( axis_rd_eop )\n    begin\n      if (!axis_rd_eop) begin\n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b1;\n        rpkt_inv_pad_0                <= 1'b1;\n      end else begin \n        adj_axis_wpkt_cnt_rd_pad_0    <= 1'b0;\n        rpkt_inv_pad_0                <= 1'b0;\n      end\t\n    end\n\n  always @ (posedge axis_rd_rst or posedge M_ACLK)\n    begin\n      if (axis_rd_has_rst)\n        diff_pkt_cnt_pad    <= 1'b0;\n      else \n        diff_pkt_cnt_pad    <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;\n    end\n\n   assign  diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;\n\n\n\n\n\n   end endgenerate // gaxis_pkt_fifo_ic\n\n\n\n\n  // Generate the accurate data count for axi stream packet fifo configuration\n  reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt\n    always @ (posedge inverted_reset or posedge S_ACLK)\n    begin\n      if (inverted_reset)\n        axis_dc_pkt_fifo <= 0;\n      else if (axis_wr_en && (~axis_rd_en))\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;\n      else if (~axis_wr_en && axis_rd_en)\n        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;\n    end\n    assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;\n  end endgenerate // gdc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt\n    assign AXIS_DATA_COUNT = 0;\n  end endgenerate // gndc_pkt\n\n  generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc\n    assign AXIS_DATA_COUNT = axis_dc;\n  end endgenerate // gdc\n\n  // Register Slice for Write Address Channel\n  generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice\n    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;\n    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_AXIS),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_AXIS)\n            )\n    axis_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (axis_din),\n          .S_VALID                   (axis_wr_en),\n          .S_READY                   (S_AXIS_TREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (axis_dout),\n          .M_VALID                   (M_AXIS_TVALID),\n          .M_READY                   (axis_rd_en)\n          );\n  end endgenerate // gaxis_reg_slice\n\n\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata\n    assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;\n    assign M_AXIS_TDATA   = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb\n    assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;\n    assign M_AXIS_TSTRB   = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep\n    assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;\n    assign M_AXIS_TKEEP   = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid\n    assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;\n    assign M_AXIS_TID     = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest\n    assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;\n    assign M_AXIS_TDEST   = axis_dout[TID_OFFSET-1:TDEST_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser\n    assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;\n    assign M_AXIS_TUSER   = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];\n  end endgenerate\n\n  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast\n    assign axis_din[0] = S_AXIS_TLAST;\n    assign M_AXIS_TLAST   = axis_dout[0];\n  end endgenerate\n\n  //###########################################################################\n  //  AXI FULL Write Channel (axi_write_channel)\n  //###########################################################################\n\n  localparam IS_AXI_FULL       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;\n  localparam IS_AXI_LITE       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;\n\n  localparam IS_AXI_FULL_WACH  = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WDCH  = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_WRCH  = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RACH  = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_FULL_RDCH  = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_AXI_LITE_WACH  = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WDCH  = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_WRCH  = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RACH  = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n  localparam IS_AXI_LITE_RDCH  = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n  localparam IS_WR_ADDR_CH     = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;\n  localparam IS_WR_DATA_CH     = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;\n  localparam IS_WR_RESP_CH     = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;\n  localparam IS_RD_ADDR_CH     = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;\n  localparam IS_RD_DATA_CH     = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;\n\n  localparam AWID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;\n  localparam AWADDR_OFFSET     = AWID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam AWLEN_OFFSET      = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;\n  localparam AWSIZE_OFFSET     = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;\n  localparam AWBURST_OFFSET    = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;\n  localparam AWLOCK_OFFSET     = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;\n  localparam AWCACHE_OFFSET    = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;\n  localparam AWPROT_OFFSET     = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam AWQOS_OFFSET      = AWPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam AWREGION_OFFSET   = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;\n  localparam AWUSER_OFFSET     = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;\n\n  localparam WID_OFFSET        = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;\n  localparam WDATA_OFFSET      = WID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam WSTRB_OFFSET      = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;\n  localparam WUSER_OFFSET      = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;\n\n  localparam BID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;\n  localparam BRESP_OFFSET      = BID_OFFSET - C_AXI_BRESP_WIDTH;\n  localparam BUSER_OFFSET      = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;\n\n\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_din          ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout         ;\n  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout_pkt     ;\n  wire                          wach_full         ;\n  wire                          wach_almost_full  ;\n  wire                          wach_prog_full    ;\n  wire                          wach_empty        ;\n  wire                          wach_almost_empty ;\n  wire                          wach_prog_empty   ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_din          ;\n  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_dout         ;\n  wire                          wdch_full         ;\n  wire                          wdch_almost_full  ;\n  wire                          wdch_prog_full    ;\n  wire                          wdch_empty        ;\n  wire                          wdch_almost_empty ;\n  wire                          wdch_prog_empty   ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_din          ;\n  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_dout         ;\n  wire                          wrch_full         ;\n  wire                          wrch_almost_full  ;\n  wire                          wrch_prog_full    ;\n  wire                          wrch_empty        ;\n  wire                          wrch_almost_empty ;\n  wire                          wrch_prog_empty   ;\n  wire                          axi_aw_underflow_i;\n  wire                          axi_w_underflow_i ;\n  wire                          axi_b_underflow_i ;\n  wire                          axi_aw_overflow_i ;\n  wire                          axi_w_overflow_i  ;\n  wire                          axi_b_overflow_i  ;\n  wire                          axi_wr_underflow_i;\n  wire                          axi_wr_overflow_i ;\n  wire                          wach_s_axi_awready;\n  wire                          wach_m_axi_awvalid;\n  wire                          wach_wr_en        ;\n  wire                          wach_rd_en        ;\n  wire                          wdch_s_axi_wready ;\n  wire                          wdch_m_axi_wvalid ;\n  wire                          wdch_wr_en        ;\n  wire                          wdch_rd_en        ;\n  wire                          wrch_s_axi_bvalid ;\n  wire                          wrch_m_axi_bready ;\n  wire                          wrch_wr_en        ;\n  wire                          wrch_rd_en        ;\n  wire                          txn_count_up      ;\n  wire                          txn_count_down    ;\n  wire                          awvalid_en        ;\n  wire                          awvalid_pkt       ;\n  wire                          awready_pkt       ;\n  integer                       wr_pkt_count      ;\n  wire                          wach_we           ;\n  wire                          wach_re           ;\n  wire                          wdch_we           ;\n  wire                          wdch_re           ;\n  wire                          wrch_we           ;\n  wire                          wrch_re           ;\n\n  generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel\n    // Write protection when almost full or prog_full is high\n    assign wach_we    = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wach_re    = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        wach_m_axi_awvalid & awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY && wach_m_axi_awvalid :\n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? \n                        awready_pkt & awvalid_en : \n                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? \n                        M_AXI_AWREADY : 1'b0;\n    assign wach_wr_en = (C_HAS_SLAVE_CE == 1)  ? wach_we & S_ACLK_EN : wach_we;\n    assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 2  || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),\n        .C_USE_ECC                      (C_USE_ECC_WACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_wach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wach_wr_en),\n        .RD_EN                    (wach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AW_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AW_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AW_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AW_INJECTSBITERR),\n  \n        .DIN                      (wach_din),\n        .DOUT                     (wach_dout_pkt),\n        .FULL                     (wach_full),\n        .EMPTY                    (wach_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_AW_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_AW_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_aw_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_aw_underflow_i),\n        .DATA_COUNT               (AXI_AW_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AW_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AW_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AW_SBITERR),\n        .DBITERR                  (AXI_AW_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wach),\n        .rd_rst_busy              (rd_rst_busy_wach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wach_s_axi_awready    = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;\n    assign wach_m_axi_awvalid   = ~wach_empty;\n    assign S_AXI_AWREADY        = wach_s_axi_awready;\n\n    assign AXI_AW_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;\n    assign AXI_AW_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_aw_overflow_i  : 0;\n\n  end endgenerate // axi_write_address_channel\n\n  // Register Slice for Write Address Channel\n  generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WACH)\n            )\n    wach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_din),\n          .S_VALID                   (S_AXI_AWVALID),\n          .S_READY                   (S_AXI_AWREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n  end endgenerate // gwach_reg_slice\n  \n  generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),\n            .C_REG_CONFIG            (1)\n            )\n    wach_pkt_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wach_dout_pkt),\n          .S_VALID                   (awvalid_pkt),\n          .S_READY                   (awready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wach_dout),\n          .M_VALID                   (M_AXI_AWVALID),\n          .M_READY                   (M_AXI_AWREADY)\n          );\n\n    assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;\n\n    assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; \n    assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset == 1) begin\n\twr_pkt_count <= 0;\n      end else begin\n\tif(txn_count_up == 1 && txn_count_down == 0) begin\n\t  wr_pkt_count <= wr_pkt_count + 1;\n\tend else if(txn_count_up == 0 && txn_count_down == 1) begin\n\t  wr_pkt_count <= wr_pkt_count - 1;\n\tend\n      end\n    end //Always end\n    assign awvalid_en = (wr_pkt_count > 0)?1:0;\n  end endgenerate\n  \n  generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr\n    assign awvalid_en    = 1;    \n    assign wach_dout     = wach_dout_pkt;\n    assign M_AXI_AWVALID = wach_m_axi_awvalid;\n  end\n  endgenerate\n\n\n\n  generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel\n    // Write protection when almost full or prog_full is high\n    assign wdch_we    = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wdch_re    = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;\n    assign wdch_wr_en = (C_HAS_SLAVE_CE == 1)  ? wdch_we & S_ACLK_EN : wdch_we;\n    assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;\n\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 2  || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),\n        .C_USE_ECC                      (C_USE_ECC_WDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_wdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wdch_wr_en),\n        .RD_EN                    (wdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_W_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_W_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_W_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_W_INJECTSBITERR),\n  \n        .DIN                      (wdch_din),\n        .DOUT                     (wdch_dout),\n        .FULL                     (wdch_full),\n        .EMPTY                    (wdch_empty),\n        .ALMOST_FULL              (),\n        .PROG_FULL                (AXI_W_PROG_FULL),\n        .ALMOST_EMPTY             (),\n        .PROG_EMPTY               (AXI_W_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_w_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_w_underflow_i),\n        .DATA_COUNT               (AXI_W_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_W_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_W_WR_DATA_COUNT),\n        .SBITERR                  (AXI_W_SBITERR),\n        .DBITERR                  (AXI_W_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wdch),\n        .rd_rst_busy              (rd_rst_busy_wdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wdch_s_axi_wready     = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;\n    assign wdch_m_axi_wvalid = ~wdch_empty;\n    assign S_AXI_WREADY      = wdch_s_axi_wready;\n    assign M_AXI_WVALID      = wdch_m_axi_wvalid;\n\n    assign AXI_W_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i  : 0;\n    assign AXI_W_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_w_overflow_i   : 0;\n\n  end endgenerate // axi_write_data_channel\n\n  // Register Slice for Write Data Channel\n  generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WDCH)\n            )\n    wdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wdch_din),\n          .S_VALID                   (S_AXI_WVALID),\n          .S_READY                   (S_AXI_WREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wdch_dout),\n          .M_VALID                   (M_AXI_WVALID),\n          .M_READY                   (M_AXI_WREADY)\n          );\n  end endgenerate // gwdch_reg_slice\n\n  generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel\n    // Write protection when almost full or prog_full is high\n    assign wrch_we    = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign wrch_re    = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;\n    assign wrch_wr_en = (C_HAS_MASTER_CE == 1)  ? wrch_we & M_ACLK_EN : wrch_we;\n    assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 2  || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WRCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WRCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),\n        .C_USE_ECC                      (C_USE_ECC_WRCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WRCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WRCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_wrch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (wrch_wr_en),\n        .RD_EN                    (wrch_rd_en),\n        .PROG_FULL_THRESH         (AXI_B_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_B_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n        .INJECTDBITERR            (AXI_B_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_B_INJECTSBITERR),\n  \n        .DIN                      (wrch_din),\n        .DOUT                     (wrch_dout),\n        .FULL                     (wrch_full),\n        .EMPTY                    (wrch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_B_PROG_FULL),\n        .PROG_EMPTY               (AXI_B_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_b_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_b_underflow_i),\n        .DATA_COUNT               (AXI_B_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_B_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_B_WR_DATA_COUNT),\n        .SBITERR                  (AXI_B_SBITERR),\n        .DBITERR                  (AXI_B_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_wrch),\n        .rd_rst_busy              (rd_rst_busy_wrch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign wrch_s_axi_bvalid = ~wrch_empty;\n    assign wrch_m_axi_bready     = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;\n    assign S_AXI_BVALID      = wrch_s_axi_bvalid;\n    assign M_AXI_BREADY      = wrch_m_axi_bready;\n\n    assign AXI_B_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i  : 0;\n    assign AXI_B_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_b_overflow_i   : 0;\n  end endgenerate // axi_write_resp_channel\n\n  // Register Slice for Write Response Channel\n  generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_WRCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_WRCH)\n            )\n    wrch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (wrch_din),\n          .S_VALID                   (M_AXI_BVALID),\n          .S_READY                   (M_AXI_BREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (wrch_dout),\n          .M_VALID                   (S_AXI_BVALID),\n          .M_READY                   (S_AXI_BREADY)\n          );\n  end endgenerate // gwrch_reg_slice\n\n\n    assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW  == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;\n    assign axi_wr_overflow_i  = C_USE_COMMON_OVERFLOW   == 1 ? (axi_aw_overflow_i  || axi_w_overflow_i  || axi_b_overflow_i)  : 0;\n\n  generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output\n    assign M_AXI_AWADDR    = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];    \n    assign M_AXI_AWLEN     = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];    \n    assign M_AXI_AWSIZE    = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];    \n    assign M_AXI_AWBURST   = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];    \n    assign M_AXI_AWLOCK    = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];    \n    assign M_AXI_AWCACHE   = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];    \n    assign M_AXI_AWQOS     = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];    \n    assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET]    = S_AXI_AWADDR;\n    assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET]   = S_AXI_AWLEN;\n    assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET]   = S_AXI_AWSIZE;\n    assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;\n    assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;\n    assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;\n    assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;\n    assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET]   = S_AXI_AWQOS;\n  end endgenerate // axi_wach_output\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion\n    assign M_AXI_AWREGION  = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];    \n  end endgenerate // axi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion\n    assign M_AXI_AWREGION  = 0;    \n  end endgenerate // naxi_awregion\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser\n    assign M_AXI_AWUSER  = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];    \n  end endgenerate // axi_awuser\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser\n    assign M_AXI_AWUSER  = 0;    \n  end endgenerate // naxi_awuser\n\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid\n    assign M_AXI_AWID      = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];\n  end endgenerate //axi_awid\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid\n    assign M_AXI_AWID      = 0;\n  end endgenerate //naxi_awid\n\n  generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output\n    assign M_AXI_WDATA     = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n    assign M_AXI_WLAST     = wdch_dout[0];\n    assign wdch_din[WID_OFFSET-1:WDATA_OFFSET]   = S_AXI_WDATA;\n    assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;\n    assign wdch_din[0]   = S_AXI_WLAST;\n  end endgenerate // axi_wdch_output\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin\n    assign M_AXI_WID       = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];\n  end endgenerate\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin\n    assign M_AXI_WID       = 0;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin\n    assign M_AXI_WUSER     = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];    \n  end endgenerate\n  generate if (C_HAS_AXI_WUSER == 0) begin\n    assign M_AXI_WUSER       = 0;\n  end endgenerate\n\n  generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output\n    assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; \n    assign wrch_din[BID_OFFSET-1:BRESP_OFFSET]   = M_AXI_BRESP;\n  end endgenerate // axi_wrch_output\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser\n    assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];\n  end endgenerate // axi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser\n    assign S_AXI_BUSER = 0;\n  end endgenerate // naxi_buser\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid\n    assign S_AXI_BID   =  wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];\n  end endgenerate // axi_bid\n  \n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid\n    assign S_AXI_BID   =  0 ;\n  end endgenerate // naxi_bid  \n\n\n  generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1\n    assign wach_din        = {S_AXI_AWADDR, S_AXI_AWPROT};\n    assign M_AXI_AWADDR    = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];    \n    assign M_AXI_AWPROT    = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];    \n  end endgenerate // axi_wach_output1\n\n  generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1\n    assign wdch_din        = {S_AXI_WDATA, S_AXI_WSTRB};\n    assign M_AXI_WDATA     = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];\n    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n  end endgenerate // axi_wdch_output1\n\n  generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1\n    assign wrch_din        = M_AXI_BRESP;\n    assign S_AXI_BRESP     = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; \n  end endgenerate // axi_wrch_output1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1\n    assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET]     = S_AXI_AWUSER;\n  end endgenerate // gwach_din1\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2\n    assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET]     = S_AXI_AWID;\n  end endgenerate // gwach_din2\n\n  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3\n    assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET]     = S_AXI_AWREGION;\n  end endgenerate // gwach_din3\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1\n    assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;\n  end endgenerate // gwdch_din1\n\n  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2\n    assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;\n  end endgenerate // gwdch_din2\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1\n    assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET]    = M_AXI_BUSER;\n  end endgenerate // gwrch_din1\n\n  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2\n    assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET]    = M_AXI_BID;\n  end endgenerate // gwrch_din2\n\n  //end of  axi_write_channel\n\n  //###########################################################################\n  //  AXI FULL Read Channel (axi_read_channel)\n  //###########################################################################\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_din            ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout           ;\n  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout_pkt       ;\n  wire                               rach_full           ;\n  wire                               rach_almost_full    ;\n  wire                               rach_prog_full      ;\n  wire                               rach_empty          ;\n  wire                               rach_almost_empty   ;\n  wire                               rach_prog_empty     ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_din            ;\n  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_dout           ;\n  wire                               rdch_full           ;\n  wire                               rdch_almost_full    ;\n  wire                               rdch_prog_full      ;\n  wire                               rdch_empty          ;\n  wire                               rdch_almost_empty   ;\n  wire                               rdch_prog_empty     ;\n  wire                               axi_ar_underflow_i  ;\n  wire                               axi_r_underflow_i   ;\n  wire                               axi_ar_overflow_i   ;\n  wire                               axi_r_overflow_i    ;\n  wire                               axi_rd_underflow_i  ;\n  wire                               axi_rd_overflow_i   ;\n  wire                               rach_s_axi_arready  ;\n  wire                               rach_m_axi_arvalid  ;\n  wire                               rach_wr_en          ;\n  wire                               rach_rd_en          ;\n  wire                               rdch_m_axi_rready   ;\n  wire                               rdch_s_axi_rvalid   ;\n  wire                               rdch_wr_en          ;\n  wire                               rdch_rd_en          ;\n  wire                               arvalid_pkt         ;\n  wire                               arready_pkt         ;\n  wire                               arvalid_en          ;\n  wire                               rdch_rd_ok          ;\n  wire                               accept_next_pkt     ;\n  integer                            rdch_free_space     ;\n  integer                            rdch_commited_space ;\n  wire                               rach_we             ;\n  wire                               rach_re             ;\n  wire                               rdch_we             ;\n  wire                               rdch_re             ;\n\n  localparam ARID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;\n  localparam ARADDR_OFFSET     = ARID_OFFSET - C_AXI_ADDR_WIDTH;\n  localparam ARLEN_OFFSET      = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;\n  localparam ARSIZE_OFFSET     = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;\n  localparam ARBURST_OFFSET    = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;\n  localparam ARLOCK_OFFSET     = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;\n  localparam ARCACHE_OFFSET    = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;\n  localparam ARPROT_OFFSET     = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;\n  localparam ARQOS_OFFSET      = ARPROT_OFFSET - C_AXI_QOS_WIDTH;\n  localparam ARREGION_OFFSET   = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;\n  localparam ARUSER_OFFSET     = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;\n\n  localparam RID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;\n  localparam RDATA_OFFSET      = RID_OFFSET - C_AXI_DATA_WIDTH;\n  localparam RRESP_OFFSET      = RDATA_OFFSET - C_AXI_RRESP_WIDTH;\n  localparam RUSER_OFFSET      = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;\n\n\n  generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rach_we    = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;\n\n    // Read protection when almost empty or prog_empty is high\n//    assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;\n    assign rach_re    = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        rach_m_axi_arvalid & arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY && rach_m_axi_arvalid :\n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? \n                        arready_pkt & arvalid_en : \n                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? \n                        M_AXI_ARREADY : 1'b0;\n    assign rach_wr_en = (C_HAS_SLAVE_CE == 1)  ? rach_we & S_ACLK_EN : rach_we;\n    assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;\n\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 2  || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RACH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RACH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RACH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),\n        .C_USE_ECC                      (C_USE_ECC_RACH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RACH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_rach_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (S_ACLK),\n        .RD_CLK                   (M_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rach_wr_en),\n        .RD_EN                    (rach_rd_en),\n        .PROG_FULL_THRESH         (AXI_AR_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_AR_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n        .INJECTDBITERR            (AXI_AR_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_AR_INJECTSBITERR),\n  \n        .DIN                      (rach_din),\n        .DOUT                     (rach_dout_pkt),\n        .FULL                     (rach_full),\n        .EMPTY                    (rach_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_AR_PROG_FULL),\n        .PROG_EMPTY               (AXI_AR_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_ar_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_ar_underflow_i),\n        .DATA_COUNT               (AXI_AR_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_AR_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_AR_WR_DATA_COUNT),\n        .SBITERR                  (AXI_AR_SBITERR),\n        .DBITERR                  (AXI_AR_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rach),\n        .rd_rst_busy              (rd_rst_busy_rach),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rach_s_axi_arready    = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;\n    assign rach_m_axi_arvalid = ~rach_empty;\n    assign S_AXI_ARREADY      = rach_s_axi_arready;\n\n    assign AXI_AR_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;\n    assign AXI_AR_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_ar_overflow_i  : 0;\n\n  end endgenerate // axi_read_addr_channel\n\n  // Register Slice for Read Address Channel\n  generate if (C_RACH_TYPE == 1) begin : grach_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RACH)\n            )\n    rach_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_din),\n          .S_VALID                   (S_AXI_ARVALID),\n          .S_READY                   (S_AXI_ARREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice\n\n  // Register Slice for Read Address Channel for MM Packet FIFO\n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),\n            .C_REG_CONFIG            (1)\n            )\n    reg_slice_mm_pkt_fifo_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rach_dout_pkt),\n          .S_VALID                   (arvalid_pkt),\n          .S_READY                   (arready_pkt),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rach_dout),\n          .M_VALID                   (M_AXI_ARVALID),\n          .M_READY                   (M_AXI_ARREADY)\n          );\n  end endgenerate // grach_reg_slice_mm_pkt_fifo\n\n  \n  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid\n    assign M_AXI_ARVALID      = rach_m_axi_arvalid;\n    assign rach_dout          = rach_dout_pkt;\n  end endgenerate // grach_m_axi_arvalid\n  \n  \n  generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd\n    assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;\n    assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;\n    assign accept_next_pkt  = rach_m_axi_arvalid && arready_pkt && arvalid_en;\n\n    always@(posedge S_ACLK or posedge inverted_reset) begin\n      if(inverted_reset) begin\n\trdch_commited_space <= 0;\n      end else begin\n\tif(rdch_rd_ok && !accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space-1;\n\tend else if(!rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);\n\tend else if(rdch_rd_ok && accept_next_pkt) begin\n\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);\n\tend\n      end\n    end //Always end\n\n    always@(*) begin\n      rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));\n    end\n\n    assign arvalid_en = (rdch_free_space >= 0)?1:0;\n  end\n  endgenerate\n  \n  generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd\n    assign arvalid_en = 1;    \n  end\n  endgenerate\n\n  generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel\n\n    // Write protection when almost full or prog_full is high\n    assign rdch_we    = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready  & M_AXI_RVALID : M_AXI_RVALID;\n\n    // Read protection when almost empty or prog_empty is high\n    assign rdch_re    = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid  & S_AXI_RREADY : S_AXI_RREADY;\n    assign rdch_wr_en = (C_HAS_MASTER_CE == 1)  ? rdch_we & M_ACLK_EN : rdch_we;\n    assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;\n\n    fifo_generator_v13_2_1_CONV_VER\n      #(\n        .C_FAMILY\t\t\t(C_FAMILY),\n        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),\n        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 2  || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),\n        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :\n                                         (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),\n        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RDCH),\n        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),\n        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RDCH),\n        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),\n        .C_USE_ECC                      (C_USE_ECC_RDCH),\n        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RDCH),\n        .C_HAS_ALMOST_EMPTY\t\t(0),\n        .C_HAS_ALMOST_FULL\t\t(0),\n        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_RDCH),\n        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),\n\n        .C_HAS_WR_RST\t\t\t(0),\n        .C_HAS_RD_RST\t\t\t(0),\n        .C_HAS_RST\t\t\t(1),\n        .C_HAS_SRST\t\t\t(0),\n        .C_DOUT_RST_VAL\t\t\t(0),\n\n        .C_HAS_VALID\t\t\t(0),\n        .C_VALID_LOW\t\t\t(C_VALID_LOW),\n        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n        .C_HAS_WR_ACK\t\t\t(0),\n        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n        .C_FULL_FLAGS_RST_VAL           (1),\n        .C_USE_EMBEDDED_REG\t\t(0),\n        .C_USE_DOUT_RST                 (0),\n        .C_MSGON_VAL                    (C_MSGON_VAL),\n        .C_ENABLE_RST_SYNC              (1),\n        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),\n        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),\n        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n        .C_RD_FREQ\t\t\t(C_RD_FREQ),\n        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n        .C_WR_FREQ\t\t\t(C_WR_FREQ),\n        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n      )\n    fifo_generator_v13_2_1_rdch_dut\n      (\n        .CLK                      (S_ACLK),\n        .WR_CLK                   (M_ACLK),\n        .RD_CLK                   (S_ACLK),\n        .RST                      (inverted_reset),\n        .SRST                     (1'b0),\n        .WR_RST                   (inverted_reset),\n        .RD_RST                   (inverted_reset),\n        .WR_EN                    (rdch_wr_en),\n        .RD_EN                    (rdch_rd_en),\n        .PROG_FULL_THRESH         (AXI_R_PROG_FULL_THRESH),\n        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH        (AXI_R_PROG_EMPTY_THRESH),\n        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n        .INJECTDBITERR            (AXI_R_INJECTDBITERR), \n        .INJECTSBITERR            (AXI_R_INJECTSBITERR),\n  \n        .DIN                      (rdch_din),\n        .DOUT                     (rdch_dout),\n        .FULL                     (rdch_full),\n        .EMPTY                    (rdch_empty),\n        .ALMOST_FULL              (),\n        .ALMOST_EMPTY             (),\n        .PROG_FULL                (AXI_R_PROG_FULL),\n        .PROG_EMPTY               (AXI_R_PROG_EMPTY),\n  \n        .WR_ACK                   (),\n        .OVERFLOW                 (axi_r_overflow_i),\n        .VALID                    (),\n        .UNDERFLOW                (axi_r_underflow_i),\n        .DATA_COUNT               (AXI_R_DATA_COUNT),\n        .RD_DATA_COUNT            (AXI_R_RD_DATA_COUNT),\n        .WR_DATA_COUNT            (AXI_R_WR_DATA_COUNT),\n        .SBITERR                  (AXI_R_SBITERR),\n        .DBITERR                  (AXI_R_DBITERR),\n        .wr_rst_busy              (wr_rst_busy_rdch),\n        .rd_rst_busy              (rd_rst_busy_rdch),\n        .wr_rst_i_out             (),\n        .rd_rst_i_out             (),\n  \n        .BACKUP                   (BACKUP),\n        .BACKUP_MARKER            (BACKUP_MARKER),\n        .INT_CLK                  (INT_CLK)\n       );\n\n    assign rdch_s_axi_rvalid = ~rdch_empty;\n    assign rdch_m_axi_rready     = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;\n    assign S_AXI_RVALID      = rdch_s_axi_rvalid;\n    assign M_AXI_RREADY      = rdch_m_axi_rready;\n\n    assign AXI_R_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i  : 0;\n    assign AXI_R_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_r_overflow_i   : 0;\n\n  end endgenerate //axi_read_data_channel\n\n  // Register Slice for read Data Channel\n  generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice\n\n    fifo_generator_v13_2_1_axic_reg_slice\n          #(\n            .C_FAMILY                (C_FAMILY),\n            .C_DATA_WIDTH            (C_DIN_WIDTH_RDCH),\n            .C_REG_CONFIG            (C_REG_SLICE_MODE_RDCH)\n            )\n    rdch_reg_slice_inst\n        (\n          // System Signals\n          .ACLK                      (S_ACLK),\n          .ARESET                    (inverted_reset),\n\n          // Slave side\n          .S_PAYLOAD_DATA            (rdch_din),\n          .S_VALID                   (M_AXI_RVALID),\n          .S_READY                   (M_AXI_RREADY),\n\n          // Master side\n          .M_PAYLOAD_DATA            (rdch_dout),\n          .M_VALID                   (S_AXI_RVALID),\n          .M_READY                   (S_AXI_RREADY)\n          );\n  end endgenerate // grdch_reg_slice\n\n\n    assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;\n    assign axi_rd_overflow_i  = C_USE_COMMON_OVERFLOW  == 1 ? (axi_ar_overflow_i  || axi_r_overflow_i) : 0;\n\n\n  generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output\n    assign M_AXI_ARADDR    = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];    \n    assign M_AXI_ARLEN     = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];    \n    assign M_AXI_ARSIZE    = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];    \n    assign M_AXI_ARBURST   = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];    \n    assign M_AXI_ARLOCK    = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];    \n    assign M_AXI_ARCACHE   = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];    \n    assign M_AXI_ARPROT    = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];    \n    assign M_AXI_ARQOS     = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];    \n    assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET]    = S_AXI_ARADDR;\n    assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET]   = S_AXI_ARLEN;\n    assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET]   = S_AXI_ARSIZE;\n    assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;\n    assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;\n    assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;\n    assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;\n    assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET]   = S_AXI_ARQOS;\n  end endgenerate // axi_full_rach_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion\n    assign M_AXI_ARREGION  = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];    \n  end endgenerate // axi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion\n    assign M_AXI_ARREGION  = 0;    \n  end endgenerate // naxi_arregion\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser\n    assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];    \n  end endgenerate // axi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser\n    assign M_AXI_ARUSER = 0;    \n  end endgenerate // naxi_aruser\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid\n    assign M_AXI_ARID      = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];\n  end endgenerate // axi_arid\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid\n    assign M_AXI_ARID      = 0;\n  end endgenerate // naxi_arid\n\n  generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output\n    assign S_AXI_RDATA     = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];\n    assign S_AXI_RRESP     = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n    assign S_AXI_RLAST     = rdch_dout[0];\n    assign rdch_din[RID_OFFSET-1:RDATA_OFFSET]   = M_AXI_RDATA;\n    assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;\n    assign rdch_din[0] = M_AXI_RLAST;\n  end endgenerate // axi_full_rdch_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output\n    assign S_AXI_RUSER     = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];\n  end endgenerate // axi_full_ruser_output\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output\n    assign S_AXI_RUSER     =  0;\n  end endgenerate // axi_full_nruser_output\n  \n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid\n    assign S_AXI_RID       = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];\n  end endgenerate // axi_rid\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid\n    assign S_AXI_RID       = 0;\n  end endgenerate // naxi_rid\n\n  generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1\n    assign rach_din      = {S_AXI_ARADDR, S_AXI_ARPROT};\n    assign M_AXI_ARADDR  = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];\n    assign M_AXI_ARPROT  = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];\n  end endgenerate // axi_lite_rach_output\n\n  generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1\n    assign rdch_din      = {M_AXI_RDATA, M_AXI_RRESP};\n    assign S_AXI_RDATA   = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];\n    assign S_AXI_RRESP   = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n  end endgenerate // axi_lite_rdch_output\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1\n    assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET]     = S_AXI_ARUSER;\n  end endgenerate // grach_din1\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2\n    assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET]     = S_AXI_ARID;\n  end endgenerate // grach_din2\n\n  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin\n    assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;\n  end endgenerate\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1\n    assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET]     = M_AXI_RUSER;\n  end endgenerate // grdch_din1\n\n  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2\n    assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;\n  end endgenerate // grdch_din2\n\n  //end of axi_read_channel\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf\n    assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :\n                       (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :\n                       (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;\n  end endgenerate // gaxi_comm_uf\n\n  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of\n    assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :\n                      (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :\n                      (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;\n  end endgenerate // gaxi_comm_of\n  \n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  // Pass Through Logic or Wiring Logic\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  //-------------------------------------------------------------------------\n  \n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Write Address Channel\n  generate if (C_WACH_TYPE == 2) begin : gwach_pass_through\n    assign M_AXI_AWID      = S_AXI_AWID;\n    assign M_AXI_AWADDR    = S_AXI_AWADDR;\n    assign M_AXI_AWLEN     = S_AXI_AWLEN;\n    assign M_AXI_AWSIZE    = S_AXI_AWSIZE;\n    assign M_AXI_AWBURST   = S_AXI_AWBURST;\n    assign M_AXI_AWLOCK    = S_AXI_AWLOCK;\n    assign M_AXI_AWCACHE   = S_AXI_AWCACHE;\n    assign M_AXI_AWPROT    = S_AXI_AWPROT;\n    assign M_AXI_AWQOS     = S_AXI_AWQOS;\n    assign M_AXI_AWREGION  = S_AXI_AWREGION;\n    assign M_AXI_AWUSER    = S_AXI_AWUSER;\n    assign S_AXI_AWREADY   = M_AXI_AWREADY;\n    assign M_AXI_AWVALID   = S_AXI_AWVALID;\n  end endgenerate // gwach_pass_through;\n\n  // Wiring logic for Write Data Channel\n  generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through\n    assign M_AXI_WID       = S_AXI_WID;\n    assign M_AXI_WDATA     = S_AXI_WDATA;\n    assign M_AXI_WSTRB     = S_AXI_WSTRB;\n    assign M_AXI_WLAST     = S_AXI_WLAST;\n    assign M_AXI_WUSER     = S_AXI_WUSER;\n    assign S_AXI_WREADY    = M_AXI_WREADY;\n    assign M_AXI_WVALID    = S_AXI_WVALID;\n  end endgenerate // gwdch_pass_through;\n\n  // Wiring logic for Write Response Channel\n  generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through\n    assign S_AXI_BID       = M_AXI_BID;\n    assign S_AXI_BRESP     = M_AXI_BRESP;\n    assign S_AXI_BUSER     = M_AXI_BUSER;\n    assign M_AXI_BREADY    = S_AXI_BREADY;\n    assign S_AXI_BVALID    = M_AXI_BVALID;\n  end endgenerate // gwrch_pass_through;\n\n  //-------------------------------------------------------------------------\n  // Pass Through Logic for Read Channel\n  //-------------------------------------------------------------------------\n\n  // Wiring logic for Read Address Channel\n  generate if (C_RACH_TYPE == 2) begin : grach_pass_through\n    assign M_AXI_ARID      = S_AXI_ARID;\n    assign M_AXI_ARADDR    = S_AXI_ARADDR;\n    assign M_AXI_ARLEN     = S_AXI_ARLEN;\n    assign M_AXI_ARSIZE    = S_AXI_ARSIZE;\n    assign M_AXI_ARBURST   = S_AXI_ARBURST;\n    assign M_AXI_ARLOCK    = S_AXI_ARLOCK;\n    assign M_AXI_ARCACHE   = S_AXI_ARCACHE;\n    assign M_AXI_ARPROT    = S_AXI_ARPROT;\n    assign M_AXI_ARQOS     = S_AXI_ARQOS;\n    assign M_AXI_ARREGION  = S_AXI_ARREGION;\n    assign M_AXI_ARUSER    = S_AXI_ARUSER;\n    assign S_AXI_ARREADY   = M_AXI_ARREADY;\n    assign M_AXI_ARVALID   = S_AXI_ARVALID;\n  end endgenerate // grach_pass_through;\n\n  // Wiring logic for Read Data Channel \n  generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through\n    assign S_AXI_RID      = M_AXI_RID;\n    assign S_AXI_RLAST    = M_AXI_RLAST;\n    assign S_AXI_RUSER    = M_AXI_RUSER;\n    assign S_AXI_RDATA    = M_AXI_RDATA;\n    assign S_AXI_RRESP    = M_AXI_RRESP;\n    assign S_AXI_RVALID   = M_AXI_RVALID;\n    assign M_AXI_RREADY   = S_AXI_RREADY;\n  end endgenerate // grdch_pass_through;\n\n  // Wiring logic for AXI Streaming\n  generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through\n    assign M_AXIS_TDATA   = S_AXIS_TDATA;\n    assign M_AXIS_TSTRB   = S_AXIS_TSTRB;\n    assign M_AXIS_TKEEP   = S_AXIS_TKEEP;\n    assign M_AXIS_TID     = S_AXIS_TID;\n    assign M_AXIS_TDEST   = S_AXIS_TDEST;\n    assign M_AXIS_TUSER   = S_AXIS_TUSER;\n    assign M_AXIS_TLAST   = S_AXIS_TLAST;\n    assign S_AXIS_TREADY  = M_AXIS_TREADY;\n    assign M_AXIS_TVALID  = S_AXIS_TVALID;\n  end endgenerate // gaxis_pass_through;\n\n\nendmodule //fifo_generator_v13_2_1\n\n\n\n/*******************************************************************************\n * Declaration of top-level module for Conventional FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_1_CONV_VER\n  #(\n    parameter  C_COMMON_CLOCK                 = 0,\n    parameter  C_INTERFACE_TYPE               = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_COUNT_TYPE                   = 0,\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DEFAULT_VALUE                = \"\",\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_ENABLE_RLOCS                 = 0,\n    parameter  C_FAMILY                       = \"virtex7\", //Not allowed in Verilog model\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_BACKUP                   = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_INT_CLK                  = 0,\n    parameter  C_HAS_MEMINIT_FILE             = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RD_RST                   = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_RST                   = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_INIT_WR_PNTR_VAL             = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_MIF_FILE_NAME                = \"\",\n    parameter  C_OPTIMIZATION_MODE            = 0,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PRIM_FIFO_TYPE               = \"\",\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_FREQ                      = 1,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_ECC                      = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_USE_FIFO16_FLAGS             = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_FREQ                      = 1,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_WR_RESPONSE_LATENCY          = 1,\n    parameter  C_MSGON_VAL                    = 1,\n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2,\n    parameter  C_AXI_TYPE                     = 0\n   )\n\n  (\n   input                               BACKUP,\n   input                               BACKUP_MARKER,\n   input                               CLK,\n   input                               RST,\n   input                               SRST,\n   input                               WR_CLK,\n   input                               WR_RST,\n   input                               RD_CLK,\n   input                               RD_RST,\n   input [C_DIN_WIDTH-1:0]             DIN,\n   input                               WR_EN,\n   input                               RD_EN,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_ASSERT,\n   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_NEGATE,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_ASSERT,\n   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_NEGATE,\n   input                               INT_CLK,\n   input                               INJECTDBITERR,\n   input                               INJECTSBITERR,\n  \n   output [C_DOUT_WIDTH-1:0]           DOUT,\n   output                              FULL,\n   output                              ALMOST_FULL,\n   output                              WR_ACK,\n   output                              OVERFLOW,\n   output                              EMPTY,\n   output                              ALMOST_EMPTY,\n   output                              VALID,\n   output                              UNDERFLOW,\n   output [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT,\n   output [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT,\n   output [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT,\n   output                              PROG_FULL,\n   output                              PROG_EMPTY,\n   output                              SBITERR,\n   output                              DBITERR,\n   output                              wr_rst_busy_o,\n   output                              wr_rst_busy,\n   output                              rd_rst_busy,\n   output                              wr_rst_i_out,\n   output                              rd_rst_i_out\n  );\n\n/*\n ******************************************************************************\n * Definition of Parameters\n ******************************************************************************\n *     C_COMMON_CLOCK                : Common Clock (1), Independent Clocks (0)\n *     C_COUNT_TYPE                  :    *not used\n *     C_DATA_COUNT_WIDTH            : Width of DATA_COUNT bus\n *     C_DEFAULT_VALUE               :    *not used\n *     C_DIN_WIDTH                   : Width of DIN bus\n *     C_DOUT_RST_VAL                : Reset value of DOUT\n *     C_DOUT_WIDTH                  : Width of DOUT bus\n *     C_ENABLE_RLOCS                :    *not used\n *     C_FAMILY                      : not used in bhv model\n *     C_FULL_FLAGS_RST_VAL          : Full flags rst val (0 or 1)\n *     C_HAS_ALMOST_EMPTY            : 1=Core has ALMOST_EMPTY flag\n *     C_HAS_ALMOST_FULL             : 1=Core has ALMOST_FULL flag\n *     C_HAS_BACKUP                  :    *not used\n *     C_HAS_DATA_COUNT              : 1=Core has DATA_COUNT bus\n *     C_HAS_INT_CLK                 : not used in bhv model\n *     C_HAS_MEMINIT_FILE            :    *not used\n *     C_HAS_OVERFLOW                : 1=Core has OVERFLOW flag\n *     C_HAS_RD_DATA_COUNT           : 1=Core has RD_DATA_COUNT bus\n *     C_HAS_RD_RST                  :    *not used\n *     C_HAS_RST                     : 1=Core has Async Rst\n *     C_HAS_SRST                    : 1=Core has Sync Rst\n *     C_HAS_UNDERFLOW               : 1=Core has UNDERFLOW flag\n *     C_HAS_VALID                   : 1=Core has VALID flag\n *     C_HAS_WR_ACK                  : 1=Core has WR_ACK flag\n *     C_HAS_WR_DATA_COUNT           : 1=Core has WR_DATA_COUNT bus\n *     C_HAS_WR_RST                  :    *not used\n *     C_IMPLEMENTATION_TYPE         : 0=Common-Clock Bram/Dram\n *                                     1=Common-Clock ShiftRam\n *                                     2=Indep. Clocks Bram/Dram\n *                                     3=Virtex-4 Built-in\n *                                     4=Virtex-5 Built-in\n *     C_INIT_WR_PNTR_VAL            :   *not used\n *     C_MEMORY_TYPE                 : 1=Block RAM\n *                                     2=Distributed RAM\n *                                     3=Shift RAM\n *                                     4=Built-in FIFO\n *     C_MIF_FILE_NAME               :   *not used\n *     C_OPTIMIZATION_MODE           :   *not used\n *     C_OVERFLOW_LOW                : 1=OVERFLOW active low\n *     C_PRELOAD_LATENCY             : Latency of read: 0, 1, 2\n *     C_PRELOAD_REGS                : 1=Use output registers\n *     C_PRIM_FIFO_TYPE              : not used in bhv model\n *     C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold\n *     C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold\n *     C_PROG_EMPTY_TYPE             : 0=No programmable empty\n *                                     1=Single prog empty thresh constant\n *                                     2=Multiple prog empty thresh constants\n *                                     3=Single prog empty thresh input\n *                                     4=Multiple prog empty thresh inputs\n *     C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold\n *     C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold\n *     C_PROG_FULL_TYPE              : 0=No prog full\n *                                     1=Single prog full thresh constant\n *                                     2=Multiple prog full thresh constants\n *                                     3=Single prog full thresh input\n *                                     4=Multiple prog full thresh inputs\n *     C_RD_DATA_COUNT_WIDTH         : Width of RD_DATA_COUNT bus\n *     C_RD_DEPTH                    : Depth of read interface (2^N)\n *     C_RD_FREQ                     : not used in bhv model\n *     C_RD_PNTR_WIDTH               : always log2(C_RD_DEPTH)\n *     C_UNDERFLOW_LOW               : 1=UNDERFLOW active low\n *     C_USE_DOUT_RST                : 1=Resets DOUT on RST\n *     C_USE_ECC                     : Used for error injection purpose\n *     C_USE_EMBEDDED_REG            : 1=Use BRAM embedded output register\n *     C_USE_FIFO16_FLAGS            : not used in bhv model\n *     C_USE_FWFT_DATA_COUNT         : 1=Use extra logic for FWFT data count\n *     C_VALID_LOW                   : 1=VALID active low\n *     C_WR_ACK_LOW                  : 1=WR_ACK active low\n *     C_WR_DATA_COUNT_WIDTH         : Width of WR_DATA_COUNT bus\n *     C_WR_DEPTH                    : Depth of write interface (2^N)\n *     C_WR_FREQ                     : not used in bhv model\n *     C_WR_PNTR_WIDTH               : always log2(C_WR_DEPTH)\n *     C_WR_RESPONSE_LATENCY         :    *not used\n *     C_MSGON_VAL                   :    *not used by bhv model\n *     C_ENABLE_RST_SYNC             : 0 = Use WR_RST & RD_RST\n *                                     1 = Use RST\n *     C_ERROR_INJECTION_TYPE        : 0 = No error injection\n *                                     1 = Single bit error injection only\n *                                     2 = Double bit error injection only\n *                                     3 = Single and double bit error injection\n ******************************************************************************\n * Definition of Ports\n ******************************************************************************\n *   BACKUP       : Not used\n *   BACKUP_MARKER: Not used\n *   CLK          : Clock\n *   DIN          : Input data bus\n *   PROG_EMPTY_THRESH       : Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag\n *   PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag\n *   PROG_FULL_THRESH        : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag\n *   PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag\n *   RD_CLK       : Read Domain Clock\n *   RD_EN        : Read enable\n *   RD_RST       : Read Reset\n *   RST          : Asynchronous Reset\n *   SRST         : Synchronous Reset\n *   WR_CLK       : Write Domain Clock\n *   WR_EN        : Write enable\n *   WR_RST       : Write Reset\n *   INT_CLK      : Internal Clock\n *   INJECTSBITERR: Inject Signle bit error\n *   INJECTDBITERR: Inject Double bit error\n *   ALMOST_EMPTY : One word remaining in FIFO\n *   ALMOST_FULL  : One empty space remaining in FIFO\n *   DATA_COUNT   : Number of data words in fifo( synchronous to CLK)\n *   DOUT         : Output data bus\n *   EMPTY        : Empty flag\n *   FULL         : Full flag\n *   OVERFLOW     : Last write rejected\n *   PROG_EMPTY   : Programmable Empty Flag\n *   PROG_FULL    : Programmable Full Flag\n *   RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)\n *   UNDERFLOW    : Last read rejected\n *   VALID        : Last read acknowledged, DOUT bus VALID\n *   WR_ACK       : Last write acknowledged\n *   WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)\n *   SBITERR      : Single Bit ECC Error Detected\n *   DBITERR      : Double Bit ECC Error Detected\n ******************************************************************************\n */\n\n  //----------------------------------------------------------------------------\n  //- Internal Signals for delayed input signals\n  //- All the input signals except Clock are delayed by 100 ps and then given to\n  //- the models.\n  //----------------------------------------------------------------------------\n \n  reg                         rst_delayed                       ;\n  reg                         empty_fb                       ;\n  reg                         srst_delayed                      ;\n  reg                         wr_rst_delayed                    ;\n  reg                         rd_rst_delayed                    ;\n  reg                         wr_en_delayed                     ;\n  reg                         rd_en_delayed                     ;\n  reg  [C_DIN_WIDTH-1:0]      din_delayed                       ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_delayed         ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_assert_delayed  ;\n  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_negate_delayed  ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_delayed          ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_assert_delayed   ;\n  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_negate_delayed   ;\n  reg                         injectdbiterr_delayed             ;\n  reg                         injectsbiterr_delayed             ;\n   wire                        empty_p0_out;\n\n  always @* rst_delayed                       <= #`TCQ RST                      ;\n  always @* empty_fb                       <= #`TCQ empty_p0_out                      ;\n  always @* srst_delayed                      <= #`TCQ SRST                     ; \n  always @* wr_rst_delayed                    <= #`TCQ WR_RST                   ; \n  always @* rd_rst_delayed                    <= #`TCQ RD_RST                   ; \n  always @* din_delayed                       <= #`TCQ DIN                      ; \n  always @* wr_en_delayed                     <= #`TCQ WR_EN                    ; \n  always @* rd_en_delayed                     <= #`TCQ RD_EN                    ; \n  always @* prog_empty_thresh_delayed         <= #`TCQ PROG_EMPTY_THRESH        ; \n  always @* prog_empty_thresh_assert_delayed  <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; \n  always @* prog_empty_thresh_negate_delayed  <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; \n  always @* prog_full_thresh_delayed          <= #`TCQ PROG_FULL_THRESH         ; \n  always @* prog_full_thresh_assert_delayed   <= #`TCQ PROG_FULL_THRESH_ASSERT  ; \n  always @* prog_full_thresh_negate_delayed   <= #`TCQ PROG_FULL_THRESH_NEGATE  ; \n  always @* injectdbiterr_delayed             <= #`TCQ INJECTDBITERR            ; \n  always @* injectsbiterr_delayed             <= #`TCQ INJECTSBITERR            ; \n\n  /*****************************************************************************\n   * Derived parameters\n   ****************************************************************************/\n  //There are 2 Verilog behavioral models\n  // 0 = Common-Clock FIFO/ShiftRam FIFO\n  // 1 = Independent Clocks FIFO\n  // 2 = Low Latency Synchronous FIFO\n  // 3 = Low Latency Asynchronous FIFO\n  localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :\n                              (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n\n  //Internal reset signals\n  reg                                rd_rst_asreg    = 1'b0;\n  reg                                rd_rst_asreg_d1 = 1'b0;\n  reg                                rd_rst_asreg_d2 = 1'b0;\n  reg                                rd_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_reg      = 1'b0;\n  reg                                rd_rst_comb     = 1'b1;\n  reg                                rd_rst_comb_d1  = 1'b0;\n  reg                                wr_rst_d0       = 1'b0;\n  reg                                wr_rst_d1       = 1'b0;\n  reg                                wr_rst_d2       = 1'b0;\n  reg                                rd_rst_d0       = 1'b0;\n  reg                                rd_rst_d1       = 1'b0;\n  reg                                rd_rst_d2       = 1'b0;\n  reg                                rd_rst_d3       = 1'b0;\n  reg                                wrrst_done      = 1'b0;\n  reg                                rdrst_done      = 1'b0;\n  reg                                wr_rst_asreg    = 1'b0;\n  reg                                wr_rst_asreg_d1 = 1'b0;\n  reg                                wr_rst_asreg_d2 = 1'b0;\n  reg                                wr_rst_asreg_d3 = 1'b0;\n  reg                                rd_rst_wr_d0    = 1'b0;\n  reg                                rd_rst_wr_d1    = 1'b0;\n  reg                                rd_rst_wr_d2    = 1'b0;\n  reg                                wr_rst_reg      = 1'b0;\n  reg                                rst_active_i    = 1'b1;\n  reg                                rst_delayed_d1  = 1'b1;\n  reg                                rst_delayed_d2  = 1'b1;\n  reg                                wr_rst_comb     = 1'b1;\n  reg                                wr_rst_comb_d1  = 1'b0;\n  wire                               wr_rst_i;\n  wire                               rd_rst_i;\n  wire                               rst_i;\n\n  //Internal reset signals\n  reg                                rst_asreg     = 1'b0;\n  reg                                srst_asreg    = 1'b0;\n  reg                                rst_asreg_d1  = 1'b0;\n  reg                                rst_asreg_d2  = 1'b0;\n  reg                                srst_asreg_d1 = 1'b0;\n  reg                                srst_asreg_d2 = 1'b0;\n  reg                                rst_reg       = 1'b0;\n  reg                                srst_reg      = 1'b0;\n  reg                                rst_comb      = 1'b1;\n  reg                                rst_comb_d1   = 1'b0;\n  wire                               srst_comb;\n  reg                                rst_full_gen_i = 0;\n  reg                                rst_full_ff_i = 0;\n  reg  [2:0]                         sckt_ff0_bsy_o_i = {3{1'b0}};\n                                     \n  wire                               RD_CLK_P0_IN;\n  wire                               RST_P0_IN;\n  wire                               RD_EN_FIFO_IN;\n  wire                               RD_EN_P0_IN;\n\n  wire                               ALMOST_EMPTY_FIFO_OUT;\n  wire                               ALMOST_FULL_FIFO_OUT;\n  wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT_FIFO_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DOUT_FIFO_OUT;\n  wire                               EMPTY_FIFO_OUT;\n  wire                               fifo_empty_fb;\n  wire                               FULL_FIFO_OUT;\n  wire                               OVERFLOW_FIFO_OUT;\n  wire                               PROG_EMPTY_FIFO_OUT;\n  wire                               PROG_FULL_FIFO_OUT;\n  wire                               VALID_FIFO_OUT;\n  wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT_FIFO_OUT;\n  wire                               UNDERFLOW_FIFO_OUT;\n  wire                               WR_ACK_FIFO_OUT;\n  wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT_FIFO_OUT;\n\n\n  //***************************************************************************\n  // Internal Signals\n  //   The core uses either the internal_ wires or the preload0_ wires depending\n  //     on whether the core uses Preload0 or not.\n  //   When using preload0, the internal signals connect the internal core to\n  //     the preload logic, and the external core's interfaces are tied to the\n  //     preload0 signals from the preload logic.\n  //***************************************************************************\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_OUT;\n  wire                               VALID_P0_OUT;\n  wire                               EMPTY_P0_OUT;\n  wire                               ALMOSTEMPTY_P0_OUT;\n  reg                                EMPTY_P0_OUT_Q;\n  reg                                ALMOSTEMPTY_P0_OUT_Q;\n  wire                               UNDERFLOW_P0_OUT;\n  wire                               RDEN_P0_OUT;\n  wire [C_DOUT_WIDTH-1:0]            DATA_P0_IN;\n  wire                               EMPTY_P0_IN;\n  reg  [31:0]                        DATA_COUNT_FWFT;\n  reg                                SS_FWFT_WR  ;\n  reg                                SS_FWFT_RD ;\n\n  wire                               sbiterr_fifo_out;\n  wire                               dbiterr_fifo_out;\n  wire                               inject_sbit_err;\n  wire                               inject_dbit_err;\n  wire                               sckt_wr_rst_i;\n  wire                               sckt_rd_rst_i;\n  reg                                sckt_wr_rst_i_q = 1'b0;\n \n  wire                               w_fab_read_data_valid_i;\n  wire                               w_read_data_valid_i;\n  wire                               w_ram_valid_i;\n  // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.\n  assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectsbiterr_delayed : 0;\n  assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?\n                           injectdbiterr_delayed : 0;\n                           \n  assign wr_rst_i_out = wr_rst_i;\n  assign rd_rst_i_out = rd_rst_i;\n  assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];\n  generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o\n    wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;\n    always @ (posedge clk_i)\n      sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; \n  end endgenerate \n// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL\n// parameter (1=Independent Clocks, 0=Common Clock)\n\n  localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;\ngenerate\ncase (C_VERILOG_IMPL)\n0 : begin : block1_ss\n  //Common Clock Behavioral Model\n  fifo_generator_v13_2_1_bhv_ver_ss\n  #(\n    .C_FAMILY                            (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                  (C_DATA_COUNT_WIDTH),            \n    .C_DIN_WIDTH                         (C_DIN_WIDTH),                   \n    .C_DOUT_RST_VAL                      (C_DOUT_RST_VAL),                \n    .C_DOUT_WIDTH                        (C_DOUT_WIDTH),                  \n    .C_FULL_FLAGS_RST_VAL                (FULL_FLAGS_RST_VAL),            \n    .C_HAS_ALMOST_EMPTY                  (C_HAS_ALMOST_EMPTY),            \n    .C_HAS_ALMOST_FULL                   ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),             \n    .C_HAS_DATA_COUNT                    (C_HAS_DATA_COUNT),              \n    .C_HAS_OVERFLOW                      (C_HAS_OVERFLOW),                \n    .C_HAS_RD_DATA_COUNT                 (C_HAS_RD_DATA_COUNT),           \n    .C_HAS_RST                           (C_EN_SAFETY_CKT?0:C_HAS_RST),                     \n    .C_HAS_SRST                          (C_EN_SAFETY_CKT?1:C_HAS_SRST),                    \n    .C_HAS_UNDERFLOW                     (C_HAS_UNDERFLOW),               \n    .C_HAS_VALID                         (C_HAS_VALID),                   \n    .C_HAS_WR_ACK                        (C_HAS_WR_ACK),                  \n    .C_HAS_WR_DATA_COUNT                 (C_HAS_WR_DATA_COUNT),           \n    .C_IMPLEMENTATION_TYPE               (C_IMPLEMENTATION_TYPE),         \n    .C_MEMORY_TYPE                       (C_MEMORY_TYPE),                 \n    .C_OVERFLOW_LOW                      (C_OVERFLOW_LOW),                \n    .C_PRELOAD_LATENCY                   (C_PRELOAD_LATENCY),             \n    .C_PRELOAD_REGS                      (C_PRELOAD_REGS),                \n    .C_PROG_EMPTY_THRESH_ASSERT_VAL      (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL      (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                   (C_PROG_EMPTY_TYPE),             \n    .C_PROG_FULL_THRESH_ASSERT_VAL       (C_PROG_FULL_THRESH_ASSERT_VAL), \n    .C_PROG_FULL_THRESH_NEGATE_VAL       (C_PROG_FULL_THRESH_NEGATE_VAL), \n    .C_PROG_FULL_TYPE                    (C_PROG_FULL_TYPE),              \n    .C_RD_DATA_COUNT_WIDTH               (C_RD_DATA_COUNT_WIDTH),         \n    .C_RD_DEPTH                          (C_RD_DEPTH),                    \n    .C_RD_PNTR_WIDTH                     (C_RD_PNTR_WIDTH),               \n    .C_UNDERFLOW_LOW                     (C_UNDERFLOW_LOW),               \n    .C_USE_DOUT_RST                      (C_USE_DOUT_RST),                \n    .C_USE_EMBEDDED_REG                  (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                     (C_EN_SAFETY_CKT),            \n    .C_USE_FWFT_DATA_COUNT               (C_USE_FWFT_DATA_COUNT),         \n    .C_VALID_LOW                         (C_VALID_LOW),                   \n    .C_WR_ACK_LOW                        (C_WR_ACK_LOW),                  \n    .C_WR_DATA_COUNT_WIDTH               (C_WR_DATA_COUNT_WIDTH),         \n    .C_WR_DEPTH                          (C_WR_DEPTH),                    \n    .C_WR_PNTR_WIDTH                     (C_WR_PNTR_WIDTH),               \n    .C_USE_ECC                           (C_USE_ECC),                     \n    .C_ENABLE_RST_SYNC                   (C_ENABLE_RST_SYNC),             \n    .C_ERROR_INJECTION_TYPE              (C_ERROR_INJECTION_TYPE),\n    .C_FIFO_TYPE                         (C_FIFO_TYPE)                     \n  )\n  gen_ss\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .CLK                      (CLK),\n    .RST                      (C_EN_SAFETY_CKT?1'b0:rst_i),\n    .SRST                     (C_EN_SAFETY_CKT?sckt_wr_rst_i:srst_delayed),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .USER_EMPTY_FB            (empty_fb),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .DATA_COUNT               (DATA_COUNT_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .WR_RST_BUSY              (wr_rst_busy),\n    .RD_RST_BUSY              (rd_rst_busy),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n1 : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_1_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT), \n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .fab_read_data_valid_i    (w_fab_read_data_valid_i),\n    .read_data_valid_i        (w_read_data_valid_i),\n    .ram_valid_i              (w_ram_valid_i),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\n2 : begin : ll_afifo_inst\n  fifo_generator_v13_2_1_beh_ver_ll_afifo\n  #(\n    .C_DIN_WIDTH                    (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                 (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                   (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_RD_DATA_COUNT            (C_HAS_RD_DATA_COUNT),\n    .C_HAS_WR_DATA_COUNT            (C_HAS_WR_DATA_COUNT),\n    .C_RD_DEPTH                     (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                (C_RD_PNTR_WIDTH),\n    .C_USE_DOUT_RST                 (C_USE_DOUT_RST),\n    .C_WR_DATA_COUNT_WIDTH          (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                     (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                (C_WR_PNTR_WIDTH),\n    .C_FIFO_TYPE                    (C_FIFO_TYPE)\n   )\n  gen_ll_afifo\n  (\n    .DIN                        (din_delayed),\n    .RD_CLK                     (RD_CLK),\n    .RD_EN                      (rd_en_delayed),\n    .WR_RST                     (wr_rst_i),\n    .RD_RST                     (rd_rst_i),\n    .WR_CLK                     (WR_CLK),\n    .WR_EN                      (wr_en_delayed),\n    .DOUT                       (DOUT),\n    .EMPTY                      (EMPTY),\n    .FULL                       (FULL)\n  );\nend\ndefault : begin : block1_as\n  //Independent Clocks Behavioral Model\n  fifo_generator_v13_2_1_bhv_ver_as\n  #(\n    .C_FAMILY                          (C_FAMILY),\n    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),\n    .C_DIN_WIDTH                       (C_DIN_WIDTH),\n    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),\n    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),\n    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),\n    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),\n    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),\n    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),\n    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),\n    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),\n    .C_HAS_RST                         (C_EN_SAFETY_CKT?0:C_HAS_RST),\n    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),\n    .C_HAS_VALID                       (C_HAS_VALID),\n    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),\n    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),\n    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),\n    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),\n    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),\n    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),\n    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),\n    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),\n    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),\n    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),\n    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),\n    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),\n    .C_RD_DEPTH                        (C_RD_DEPTH),\n    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),\n    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),\n    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),\n    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),\n    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT),\n    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),\n    .C_VALID_LOW                       (C_VALID_LOW),\n    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),\n    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),\n    .C_WR_DEPTH                        (C_WR_DEPTH),\n    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),\n    .C_USE_ECC                         (C_USE_ECC),\n    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),\n    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),\n    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)\n  )\n  gen_as\n  (\n    .SAFETY_CKT_WR_RST        (sckt_wr_rst_i),\n    .SAFETY_CKT_RD_RST        (sckt_rd_rst_i),\n    .WR_CLK                   (WR_CLK),\n    .RD_CLK                   (RD_CLK),\n    .RST                      (rst_i),\n    .RST_FULL_GEN             (rst_full_gen_i),\n    .RST_FULL_FF              (rst_full_ff_i),\n    .WR_RST                   (wr_rst_i),\n    .RD_RST                   (rd_rst_i),\n    .DIN                      (din_delayed),\n    .WR_EN                    (wr_en_delayed),\n    .RD_EN                    (RD_EN_FIFO_IN),\n    .RD_EN_USER               (rd_en_delayed),\n    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),\n    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n    .PROG_FULL_THRESH         (prog_full_thresh_delayed),\n    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),\n    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),\n    .INJECTSBITERR            (inject_sbit_err),\n    .INJECTDBITERR            (inject_dbit_err),\n    .USER_EMPTY_FB            (EMPTY_P0_OUT),\n    .DOUT                     (DOUT_FIFO_OUT),\n    .FULL                     (FULL_FIFO_OUT),\n    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),\n    .WR_ACK                   (WR_ACK_FIFO_OUT),\n    .OVERFLOW                 (OVERFLOW_FIFO_OUT),\n    .EMPTY                    (EMPTY_FIFO_OUT),\n    .EMPTY_FB                 (fifo_empty_fb),\n    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),\n    .VALID                    (VALID_FIFO_OUT),\n    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),\n    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),\n    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),\n    .PROG_FULL                (PROG_FULL_FIFO_OUT),\n    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),\n    .SBITERR                  (sbiterr_fifo_out),\n    .DBITERR                  (dbiterr_fifo_out)\n   );\nend\n\nendcase\nendgenerate\n\n\n   //**************************************************************************\n   // Connect Internal Signals\n   //   (Signals labeled internal_*)\n   //  In the normal case, these signals tie directly to the FIFO's inputs and\n   //    outputs.\n   //  In the case of Preload Latency 0 or 1, there are intermediate\n   //    signals between the internal FIFO and the preload logic.\n   //**************************************************************************\n   \n   \n   //***********************************************\n   // If First-Word Fall-Through, instantiate\n   // the preload0 (FWFT) module\n   //***********************************************\n   wire                        rd_en_to_fwft_fifo;\n   wire                        sbiterr_fwft;\n   wire                        dbiterr_fwft;\n   wire [C_DOUT_WIDTH-1:0]     dout_fwft;\n   wire                        empty_fwft;\n   wire                        rd_en_fifo_in;\n   wire                        stage2_reg_en_i;\n   wire [1:0]                  valid_stages_i;\n   wire                        rst_fwft;\n   //wire                        empty_p0_out;\n   reg  [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n   localparam IS_PKT_FIFO      = (C_FIFO_TYPE == 1) ? 1 : 0;\n   localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;\n   assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2_fwft\n\n\n         fifo_generator_v13_2_1_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_EMBEDDED_REG  (C_USE_EMBEDDED_REG),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (C_FIFO_TYPE)\n             )\n             fgpl0\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (RST_P0_IN),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (RD_EN_P0_IN),\n                .FIFOEMPTY        (EMPTY_P0_IN),\n                .FIFODATA         (DATA_P0_IN),\n                .FIFOSBITERR      (sbiterr_fifo_out),\n                .FIFODBITERR      (dbiterr_fifo_out),\n                // Output\n                .USERDATA         (dout_fwft),\n                .USERVALID        (VALID_P0_OUT),\n                .USEREMPTY        (empty_fwft),\n                .USERALMOSTEMPTY  (ALMOSTEMPTY_P0_OUT),\n                .USERUNDERFLOW    (UNDERFLOW_P0_OUT),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_fifo_in),\n                .USERSBITERR      (sbiterr_fwft),\n                .USERDBITERR      (dbiterr_fwft),\n                .STAGE2_REG_EN    (stage2_reg_en_i),\n                .fab_read_data_valid_i_o    (w_fab_read_data_valid_i),\n                .read_data_valid_i_o        (w_read_data_valid_i),\n                .ram_valid_i_o              (w_ram_valid_i),\n                .VALID_STAGES                (valid_stages_i)\n                );\n\n         \n         //***********************************************\n         // Connect inputs to preload (FWFT) module\n         //***********************************************\n         //Connect the RD_CLK of the Preload (FWFT) module to CLK if we \n         // have a common-clock FIFO, or RD_CLK if we have an \n         // independent clock FIFO\n         assign RD_CLK_P0_IN       = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);\n         assign RST_P0_IN          = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;\n         assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n         assign EMPTY_P0_IN        = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;\n         assign DATA_P0_IN         = DOUT_FIFO_OUT;\n         \n         //***********************************************\n         // Connect outputs from preload (FWFT) module\n         //***********************************************\n         assign VALID              = VALID_P0_OUT ;\n         assign ALMOST_EMPTY       = ALMOSTEMPTY_P0_OUT;\n         assign UNDERFLOW          = UNDERFLOW_P0_OUT ;\n         \n         assign RD_EN_FIFO_IN      = rd_en_fifo_in;\n         \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:\n           (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : \n           DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];  \n         \n         //***********************************************\n         // Create DATA_COUNT from First-Word Fall-Through\n         // data count\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               EMPTY_P0_OUT_Q       <= 1;\n               ALMOSTEMPTY_P0_OUT_Q <= 1;\n            end else begin\n               EMPTY_P0_OUT_Q       <= #`TCQ empty_p0_out;\n//               EMPTY_P0_OUT_Q       <= #`TCQ EMPTY_FIFO_OUT;\n               ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;\n            end\n         end //always\n         \n         \n         //***********************************************\n         // logic for common-clock data count when FWFT is selected\n         //***********************************************\n         initial begin\n            SS_FWFT_RD = 1'b0;\n            DATA_COUNT_FWFT = 0 ;\n            SS_FWFT_WR   = 1'b0 ;\n         end //initial\n         \n         \n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter. SS_FWFT_WR and SS_FWFT_RD\n         // are the up/down enables for the counter.\n         //***********************************************\n         always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin\n            if (C_VALID_LOW == 1) begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;\n            end else begin\n              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;\n            end\n            SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT))  ;\n         end \n\n         //***********************************************\n         // common-clock data count is implemented as an\n         // up-down counter for FWFT. This always block \n         // calculates the counter.\n         //***********************************************\n         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n            if (RST_P0_IN) begin\n               DATA_COUNT_FWFT      <= 0;\n            end else begin\n               //if (srst_delayed && (C_HAS_SRST == 1) ) begin\n               if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin\n                  DATA_COUNT_FWFT      <= #`TCQ 0;\n               end else begin\n                  case ( {SS_FWFT_WR, SS_FWFT_RD})\n                    2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                    2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;\n                    2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;\n                    2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n                  endcase  \n               end //if SRST\n            end //IF RST\n         end //always\n\n      end endgenerate // : block2\n\n    // AXI Streaming Packet FIFO\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count       = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_plus1 = 0;\n    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_reg   = 0;\n    reg                         partial_packet     = 0;\n    reg                         stage1_eop_d1      = 0;\n    reg                         rd_en_fifo_in_d1   = 0;\n    reg                         eop_at_stage2      = 0;\n    reg                         ram_pkt_empty      = 0;\n    reg                         ram_pkt_empty_d1   = 0;\n\n    wire [C_DOUT_WIDTH-1:0]     dout_p0_out;\n    wire                        packet_empty_wr;\n    wire                        wr_rst_fwft_pkt_fifo;\n    wire                        dummy_wr_eop;\n    wire                        ram_wr_en_pkt_fifo;\n    wire                        wr_eop;\n    wire                        ram_rd_en_compare;\n    wire                        stage1_eop;\n    wire                        pkt_ready_to_read;\n    wire                        rd_en_2_stage2;\n\n    // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)\n    // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP\n    // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of\n    // write packet count\n    generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop\n       always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n          if (wr_rst_fwft_pkt_fifo)\n             partial_packet   <= 1'b0;\n          else begin\n             if (srst_delayed | wr_rst_busy | rd_rst_busy)\n                partial_packet <= #`TCQ 1'b0;\n             else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))\n                partial_packet <= #`TCQ 1'b1;\n             else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)\n                partial_packet <= #`TCQ 1'b0;\n          end\n        end\n    end endgenerate // gdummy_wr_eop\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin : gpkt_fifo_fwft\n      assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;\n      assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);\n      assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];\n  \n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft) begin\n          stage1_eop_d1    <= 1'b0;\n          rd_en_fifo_in_d1 <= 1'b0;\n        end else begin\n          if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            stage1_eop_d1    <= #`TCQ 1'b0;\n            rd_en_fifo_in_d1 <= #`TCQ 1'b0;\n          end else begin\n            stage1_eop_d1    <= #`TCQ stage1_eop;\n            rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;\n          end\n        end\n      end\n      assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;\n      assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);\n      assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);\n      assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;\n\n\n         fifo_generator_v13_2_1_bhv_ver_preload0\n           #(\n             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),\n             .C_DOUT_WIDTH        (C_DOUT_WIDTH),\n             .C_HAS_RST           (C_HAS_RST),\n             .C_HAS_SRST          (C_HAS_SRST),\n             .C_USE_DOUT_RST      (C_USE_DOUT_RST),\n             .C_USE_ECC           (C_USE_ECC),\n             .C_USERVALID_LOW     (C_VALID_LOW),\n             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),\n             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),\n             .C_MEMORY_TYPE       (C_MEMORY_TYPE),\n             .C_FIFO_TYPE         (2) // Enable low latency fwft logic\n             )\n         pkt_fifo_fwft\n               (\n                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n                .RD_CLK           (RD_CLK_P0_IN),\n                .RD_RST           (rst_fwft),\n                .SRST             (srst_delayed),\n                .WR_RST_BUSY      (wr_rst_busy),\n                .RD_RST_BUSY      (rd_rst_busy),\n                .RD_EN            (rd_en_delayed),\n                .FIFOEMPTY        (pkt_ready_to_read),\n                .FIFODATA         (dout_fwft),\n                .FIFOSBITERR      (sbiterr_fwft),\n                .FIFODBITERR      (dbiterr_fwft),\n                // Output\n                .USERDATA         (dout_p0_out),\n                .USERVALID        (),\n                .USEREMPTY        (empty_p0_out),\n                .USERALMOSTEMPTY  (),\n                .USERUNDERFLOW    (),\n                .RAMVALID         (),\n                .FIFORDEN         (rd_en_2_stage2),\n                .USERSBITERR      (SBITERR),\n                .USERDBITERR      (DBITERR),\n                .STAGE2_REG_EN    (),\n                .VALID_STAGES     ()\n                );\n\n      assign pkt_ready_to_read  = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));\n      assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n        if (rst_fwft)\n          eop_at_stage2 <= 1'b0;\n        else if (stage2_reg_en_i)\n          eop_at_stage2 <= #`TCQ stage1_eop;\n      end\n\n      //---------------------------------------------------------------------------\n      // Write and Read Packet Count\n      //---------------------------------------------------------------------------\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count  <= 0;\n         else if (srst_delayed  | wr_rst_busy | rd_rst_busy)\n            wr_pkt_count  <= #`TCQ 0;\n         else if (wr_eop)\n            wr_pkt_count  <= #`TCQ wr_pkt_count + 1;\n      end\n    \n    end endgenerate //: gpkt_fifo_fwft\n\n    assign DOUT               = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;\n    assign EMPTY              = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;\n\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            rd_pkt_count       <= 0;\n            rd_pkt_count_plus1 <= 1;\n         end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n            rd_pkt_count       <= #`TCQ 0;\n            rd_pkt_count_plus1 <= #`TCQ 1;\n         end else if (stage2_reg_en_i && stage1_eop) begin\n            rd_pkt_count       <= #`TCQ rd_pkt_count + 1;\n            rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;\n         end\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (SRST | wr_rst_busy | rd_rst_busy) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n    end endgenerate //grss_pkt_cnt\n    \n    localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;\n    reg  [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;\n    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_b2g = 0;\n    wire [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_rd;\n    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt\n      // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            wr_pkt_count_b2g  <= 0;\n         else\n            wr_pkt_count_b2g  <= #`TCQ wr_pkt_count;\n      end\n\n      // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            wr_pkt_count_q       <= 0;\n         else\n            wr_pkt_count_q       <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};\n      end\n\n      always @* begin\n        if (stage1_eop)\n           rd_pkt_count    <= rd_pkt_count_reg + 1;\n        else\n           rd_pkt_count    <= rd_pkt_count_reg;\n      end\n\n      assign wr_pkt_count_rd    = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft)\n            rd_pkt_count_reg       <= 0;\n         else if (rd_en_fifo_in)\n            rd_pkt_count_reg       <= #`TCQ rd_pkt_count;\n      end\n\n      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n         if (rst_fwft) begin\n            ram_pkt_empty    <= 1'b1;\n            ram_pkt_empty_d1 <= 1'b1;\n         end else if (rd_pkt_count != wr_pkt_count_rd) begin\n            ram_pkt_empty    <= #`TCQ 1'b0;\n            ram_pkt_empty_d1 <= #`TCQ 1'b0;\n         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n            ram_pkt_empty    <= #`TCQ 1'b1;\n         end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin\n            ram_pkt_empty_d1 <= #`TCQ 1'b1;\n         end\n      end\n\n      // Synchronize the empty in write domain\n      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n         if (wr_rst_fwft_pkt_fifo)\n            pkt_empty_sync  <= 'b1;\n         else\n            pkt_empty_sync  <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};\n      end\n\n    end endgenerate //gras_pkt_cnt\n\n   generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO\n\n     //***********************************************\n     // If NOT First-Word Fall-Through, wire the outputs\n     // of the internal _ss or _as FIFO directly to the\n     // output, and do not instantiate the preload0\n     // module.\n     //***********************************************\n\n     assign RD_CLK_P0_IN       = 0;\n     assign RST_P0_IN          = 0;\n     assign RD_EN_P0_IN        = 0;\n\n     assign RD_EN_FIFO_IN      = rd_en_delayed;\n\n     assign DOUT               = DOUT_FIFO_OUT;\n     assign DATA_P0_IN         = 0;\n     assign VALID              = VALID_FIFO_OUT;\n     assign EMPTY              = EMPTY_FIFO_OUT;\n     assign ALMOST_EMPTY       = ALMOST_EMPTY_FIFO_OUT;\n     assign EMPTY_P0_IN        = 0;\n     assign UNDERFLOW          = UNDERFLOW_FIFO_OUT;\n     assign DATA_COUNT         = DATA_COUNT_FIFO_OUT;\n     assign SBITERR            = sbiterr_fifo_out;\n     assign DBITERR            = dbiterr_fifo_out;\n\n   end endgenerate // STD_FIFO\n\n   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO\n     assign empty_p0_out       = empty_fwft;\n     assign SBITERR            = sbiterr_fwft;\n     assign DBITERR            = dbiterr_fwft;\n     assign DOUT               = dout_fwft;\n     assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n\n   end endgenerate // NO_PKT_FIFO\n\n   //***********************************************\n   // Connect user flags to internal signals\n   //***********************************************\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3\n      if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);\n      end //block_ic\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3\n   endgenerate\n   \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30\n       if (C_COMMON_CLOCK == 0) begin : block_ic\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30\n   endgenerate\n\n\n    \n   //If we are using extra logic for the FWFT data count, then override the\n   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both\n       if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));\n       end \n       else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n        end \n      end //block30_both\n   endgenerate\n\n generate\n      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both\n      if (C_COMMON_CLOCK == 0) begin : block_ic_both\n         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));\n      end //block_ic_both\n      else begin\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end \n      end //block3_both\n   endgenerate\n\n\n   //If we are not using extra logic for the FWFT data count,\n   //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the\n   //internal FIFO instance  \n   generate\n      if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31\n         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n   //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal\n   //FIFO instance\n   generate\n      if (C_USE_FWFT_DATA_COUNT==1) begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n      else begin : block4\n         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n      end\n   endgenerate\n\n\n   //Connect other flags to the internal FIFO instance\n   assign       FULL        = FULL_FIFO_OUT;\n   assign       ALMOST_FULL = ALMOST_FULL_FIFO_OUT;\n   assign       WR_ACK      = WR_ACK_FIFO_OUT;\n   assign       OVERFLOW    = OVERFLOW_FIFO_OUT;\n   assign       PROG_FULL   = PROG_FULL_FIFO_OUT;\n   assign       PROG_EMPTY  = PROG_EMPTY_FIFO_OUT;\n\n\n  /**************************************************************************\n  * find_log2\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function integer find_log2;\n    input integer int_val;\n    integer i,j;\n    begin\n      i = 1;\n      j = 0;\n      for (i = 1; i < int_val; i = i*2) begin\n        j = j + 1;\n      end\n      find_log2 = j;\n    end\n  endfunction\n\n   // if an asynchronous FIFO has been selected, display a message that the FIFO\n   //   will not be cycle-accurate in simulation\n   initial begin\n      if (C_IMPLEMENTATION_TYPE == 2) begin\n         $display(\"WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.\");\n      end else if (C_MEMORY_TYPE == 4) begin\n         $display(\"FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.\");\n         $finish;\n      end\n\n      if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin\n         $display(\"FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.\");\n         $finish;\n      end\n\n      if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin\n         $display(\"FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.\");\n         $finish;\n      end\n\n      if (C_USE_ECC == 1) begin\n         if (C_DIN_WIDTH != C_DOUT_WIDTH) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.\");\n            $finish;\n         end\n         if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin\n            $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.\");\n            $finish;\n         end\n      end\n\n   end //initial\n\n  /**************************************************************************\n  * Internal reset logic\n  **************************************************************************/\n  assign wr_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg|sckt_wr_rst_i : 0;\n  assign rd_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg|sckt_rd_rst_i : 0;\n  assign rst_i            = C_HAS_RST ? rst_reg|sckt_wr_rst_i : 0;\n\n  wire rst_2_sync;\n  wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;\n\n  localparam RST_SYNC_STAGES = C_EN_SAFETY_CKT == 0 ? C_COMMON_CLOCK ? C_SYNCHRONIZER_STAGE : C_SYNCHRONIZER_STAGE+2 : 5;\n  localparam RST_BUSY_LEN    = 4;\n  reg  wr_rst_busy_i = 0;\n  reg  rd_rst_busy_i = 0;\n  generate\n      if (C_ENABLE_RST_SYNC == 0 || (C_HAS_RST == 0 && C_HAS_SRST == 0)) begin : gnrst_sync\n        always @* begin\n          wr_rst_reg <= wr_rst_delayed;\n          rd_rst_reg <= rd_rst_delayed;\n          rst_reg    <= 1'b0;\n          srst_reg    <= 1'b0;\n        end\n        assign rst_2_sync = wr_rst_delayed;\n        assign wr_rst_busy = 1'b0;\n        assign wr_rst_busy_o = 1'b0;\n        assign rd_rst_busy = 1'b0;\n        assign sckt_wr_rst_i = 1'b0;\n      end // gnrst_sync\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 0) begin : g7s_ic_rst_nsckt\n        reg [1:0]                 arst_sync_wr  = 2'b11;\n        reg [1:0]                 arst_sync_rd  = 2'b11;\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge WR_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge RD_CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_rd    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_rd    <= #`TCQ {arst_sync_rd[0], rst_delayed};\n        end\n        always @(posedge WR_CLK) begin\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n\tend\n        always @(posedge WR_CLK or posedge arst_sync_wr[1]) begin\n\t  if (arst_sync_wr[1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n            rd_rst_wr_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            rd_rst_wr_ext  <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t    if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t      sckt_wr_rst_ic <= #`TCQ 1'b0;\n            else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t      wr_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n        always @(posedge RD_CLK) begin\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], sckt_wr_rst_ic};\n\tend\n        always @(posedge RD_CLK or posedge arst_sync_rd[1]) begin\n\t  if (arst_sync_rd[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n            wr_rst_rd_ext  <= #`TCQ {RST_SYNC_STAGES{1'b0}};\n\t  end else begin\n            wr_rst_rd_ext  <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t    if (wr_rst_rd_ext[1]) begin\n\t      sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t      rd_rst_busy_i  <= #`TCQ 1'b0;\n\t    end\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic|arst_sync_wr[1];\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic|arst_sync_rd[1];\n      end // g7s_ic_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 1) begin : g7s_ic_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] arst_sync_rd  = {RST_SYNC_STAGES{1'b1}};\n        reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;\n        reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;\n        reg [3:0]                 rd_rst_wr_ext = 0;\n        reg [1:0]                 wr_rst_rd_ext = 0;\n        reg                       sckt_wr_rst_ic = 0;\n        reg                       sckt_rd_rst_ic = 0;\n\n        always @(posedge WR_CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_rd_rst_wr   <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};\n          rd_rst_wr_ext    <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_wr[RST_SYNC_STAGES-1]) begin\n\t    sckt_wr_rst_ic <= #`TCQ 1'b1;\n\t    wr_rst_busy_i  <= #`TCQ 1'b1;\n          end else if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])\n\t    sckt_wr_rst_ic <= #`TCQ 1'b0;\n          else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])\n\t    wr_rst_busy_i  <= #`TCQ 1'b0;\n\tend\n        always @(posedge RD_CLK) begin\n\t  arst_sync_rd     <= #`TCQ {arst_sync_rd[RST_SYNC_STAGES-2:0], rst_delayed};\n          sckt_wr_rst_rd   <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n          wr_rst_rd_ext    <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};\n\t  if (arst_sync_rd[RST_SYNC_STAGES-1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b1;\n\t    rd_rst_busy_i  <= #`TCQ 1'b1;\n\t  end else if (wr_rst_rd_ext[1]) begin\n\t    sckt_rd_rst_ic <= #`TCQ 1'b0;\n\t    rd_rst_busy_i  <= #`TCQ 1'b0;\n\t  end\n\tend\n\n        assign rd_rst_busy       = rd_rst_busy_i;\n        assign wr_rst_busy       = wr_rst_busy_i;\n        assign wr_rst_busy_o     = wr_rst_busy_i;\n        assign sckt_wr_rst_i     = sckt_wr_rst_ic;\n        assign sckt_rd_rst_i     = sckt_rd_rst_ic;\n      end // g7s_ic_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 0) begin : g7s_cc_rst_nsckt\n        reg [1:0]              arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n        assign rst_2_sync = arst_sync_wr[1];\n\n        always @(posedge CLK or posedge rst_delayed) begin\n          if (rst_delayed == 1'b1)\n\t    arst_sync_wr    <= #`TCQ 2'b11;\n          else\n\t    arst_sync_wr    <= #`TCQ {arst_sync_wr[0], rst_delayed};\n        end\n\n        always @(posedge CLK) begin\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0] | arst_sync_wr[1]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc | arst_sync_wr[1];\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_nsckt\n      else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 1) begin : g7s_cc_rst_sckt\n        reg [RST_SYNC_STAGES-1:0] arst_sync_wr  = 0;\n        reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n\n        always @(posedge CLK) begin\n\t  arst_sync_wr     <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};\n\t  sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};\n\tend\n\n        assign sckt_wr_rst_i  = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0]; \n        assign sckt_rd_rst_i  = sckt_wr_rst_i;\n        assign wr_rst_busy    = |sckt_wr_rst_cc;\n        assign rd_rst_busy    = |sckt_wr_rst_cc;\n        assign wr_rst_busy_o  = |sckt_wr_rst_cc;\n      end // g7s_cc_rst_sckt\n      else if (C_ENABLE_RST_SYNC == 1 && IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst\n        assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;\n        assign rd_rst_busy = rst_reg;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = rst_reg;\n        always @* rst_full_ff_i  <= 1'b0;\n        always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;\n\n        always @(posedge CLK) begin\n          rst_delayed_d1 <= #`TCQ srst_delayed;\n          rst_delayed_d2 <= #`TCQ rst_delayed_d1;\n          if (rst_reg || rst_delayed_d2) begin\n            rst_active_i <= #`TCQ 1'b1;\n          end else begin\n            rst_active_i <= #`TCQ rst_reg;\n          end    \n        end   \n        always @(posedge CLK) begin\n          if (~rst_reg && srst_delayed) begin\n             rst_reg <= #`TCQ 1'b1;\n           end else if (rst_reg) begin\n             rst_reg <= #`TCQ 1'b0;\n           end else begin\n             rst_reg <= #`TCQ rst_reg;\n           end    \n        end   \n      end // g8s_cc_rst\n      else if (IS_8SERIES != 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_srst\n        assign wr_rst_busy = srst_delayed;\n        assign rd_rst_busy = srst_delayed;\n        assign rst_2_sync = srst_delayed;\n        assign sckt_wr_rst_i = srst_delayed;\n        always @* rst_full_ff_i  <= 1'b0;\n      end // g7s_cc_srst\n  endgenerate \n\n  reg rst_d1 = 1'b0;\n  reg rst_d2 = 1'b0;\n  reg rst_d3 = 1'b0;\n  reg rst_d4 = 1'b0;\n  generate\n    if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1\n    // RST_FULL_GEN replaces the reset falling edge detection used to de-assert\n    // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.\n\n    // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &\n    // PROG_FULL\n\n      always @ (posedge rst_2_sync or posedge clk_2_sync) begin\n        if (rst_2_sync && C_EN_SAFETY_CKT == 0) begin\n          rst_d1         <= 1'b1;\n          rst_d2         <= 1'b1;\n          rst_d3         <= 1'b1;\n          rst_d4         <= 1'b0;\n        end else begin\n          if (srst_delayed) begin\n            rst_d1         <= #`TCQ 1'b1;\n            rst_d2         <= #`TCQ 1'b1;\n            rst_d3         <= #`TCQ 1'b1;\n            rst_d4         <= #`TCQ 1'b0;\n          end else begin\n            rst_d1         <= #`TCQ wr_rst_busy;//1'b0;\n            rst_d2         <= #`TCQ rst_d1;\n            rst_d3         <= #`TCQ rst_d2 | sckt_wr_rst_i;\n            rst_d4         <= #`TCQ rst_d3;\n          end\n        end\n      end\n\n      always @* rst_full_ff_i  <= C_HAS_SRST ? 1'b0 : rst_d2 | sckt_wr_rst_i;\n      always @* rst_full_gen_i <= C_HAS_SRST ? rst_d4 : rst_d3;\n\n    end else if (C_EN_SAFETY_CKT == 1 && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full_sckt\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full\n      always @* rst_full_ff_i  <=  C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n      always @* rst_full_gen_i <= 1'b0;\n    end\n  endgenerate // grstd1\n\nendmodule //fifo_generator_v13_2_1_CONV_VER\n\n\nmodule fifo_generator_v13_2_1_sync_stage\n  #(\n    parameter  C_WIDTH          = 10\n   )\n   (\n    input                     RST,\n    input                     CLK,\n    input       [C_WIDTH-1:0] DIN,\n    output reg  [C_WIDTH-1:0] DOUT = 0\n   );\n   always @ (posedge RST or posedge CLK) begin\n     if (RST)\n       DOUT <= 0;\n     else\n       DOUT <= #`TCQ DIN;\n   end\nendmodule // fifo_generator_v13_2_1_sync_stage\n\n/*******************************************************************************\n * Declaration of Independent-Clocks FIFO Module\n ******************************************************************************/\nmodule fifo_generator_v13_2_1_bhv_ver_as\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_SYNCHRONIZER_STAGE           = 2 \n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input                                         SAFETY_CKT_WR_RST,\n   input                                         SAFETY_CKT_RD_RST,\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_ASSERT,\n   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_NEGATE,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_ASSERT,\n   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_NEGATE,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         RD_EN_USER,\n   input                                         RST,\n   input                                         RST_FULL_GEN,\n   input                                         RST_FULL_FF,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   input                                         INJECTDBITERR,\n   input                                         INJECTSBITERR,\n   input                                         USER_EMPTY_FB,\n   input                                         fab_read_data_valid_i,\n   input                                         read_data_valid_i,\n   input                                         ram_valid_i,\n   output reg                                    ALMOST_EMPTY = 1'b1,\n   output reg                                    ALMOST_FULL = C_FULL_FLAGS_RST_VAL,\n   output      [C_DOUT_WIDTH-1:0]                DOUT,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    EMPTY_FB = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL,\n   output                                        OVERFLOW,\n   output                                        PROG_EMPTY,\n   output                                        PROG_FULL,\n   output                                        VALID,\n   output      [C_RD_DATA_COUNT_WIDTH-1:0]       RD_DATA_COUNT,\n   output                                        UNDERFLOW,\n   output                                        WR_ACK,\n   output      [C_WR_DATA_COUNT_WIDTH-1:0]       WR_DATA_COUNT,\n   output                                        SBITERR,\n   output                                        DBITERR\n  );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   \n  \n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   \n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;\n   // Array that holds the error injection type (single/double bit error) on \n   // a specific write operation, which is returned on read to corrupt the\n   // output data.\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   //The amount of data stored in the FIFO at any time is given\n   // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK\n   // domain.\n   //num_wr_bits is calculated by considering the total words in the FIFO,\n   // and the state of the read pointer (which may not have yet crossed clock\n   // domains.)\n   //num_rd_bits is calculated by considering the total words in the FIFO,\n   // and the state of the write pointer (which may not have yet crossed clock\n   // domains.)\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   wire                        wr_rst_i = WR_RST;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n   wire                        rd_rst_i = RD_RST;\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n\n\n\n   // Delayed ram_rd_en is needed only for STD Embedded register option\n   generate\n     if (C_PRELOAD_LATENCY == 2) begin : grd_d\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n       end\n     end\n   endgenerate\n   \n    generate\n     if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i)\n           ram_rd_en_d1 <= 1'b0;\n         else\n           ram_rd_en_d1 <= #`TCQ ram_rd_en;\n           fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n       end\n     end\n   endgenerate\n\n  \n\n   // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;\n     end else begin : rdl // Read depth lesser than or equal to write depth\n       assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n     end\n   endgenerate\n\n   // Generate Empty and Almost Empty\n  // ram_rd_en used to determine EMPTY should depend on the EMPTY.\n   assign ram_rd_en        = RD_EN & !EMPTY;\n   assign empty_int        = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));\n   assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));\n\n   // Register Empty and Almost Empty\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) begin\n         EMPTY             <= 1'b1;\n         ALMOST_EMPTY      <= 1'b1;\n         rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n       end else begin\n         rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};\n\n         if (empty_int)\n           EMPTY           <= #`TCQ 1'b1;\n         else\n           EMPTY           <= #`TCQ 1'b0;\n\n         if (!EMPTY) begin\n           if (almost_empty_int)\n             ALMOST_EMPTY  <= #`TCQ 1'b1;\n           else\n             ALMOST_EMPTY  <= #`TCQ 1'b0;\n         end\n       end // rd_rst_i\n     end // always\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n         EMPTY_FB     <= 1'b1;\n       end else begin\n         if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else if (empty_int)\n           EMPTY_FB   <= #`TCQ 1'b1;\n         else\n           EMPTY_FB   <= #`TCQ 1'b0;\n       end // rd_rst_i\n     end // always\n\n   // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n   generate\n     if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;\n     end else begin : wdl // Write depth lesser than or equal to read depth\n       assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n     end\n   endgenerate\n\n  // Generate FULL and ALMOST_FULL\n  // ram_wr_en used to determine FULL should depend on the FULL.\n  assign ram_wr_en       = WR_EN & !FULL;\n  assign full_int        = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));\n  assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));\n\n   // Register FULL and ALMOST_FULL Empty\n   always @ (posedge WR_CLK or posedge RST_FULL_FF)\n     begin\n       if (RST_FULL_FF & C_HAS_RST) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n         FULL             <= C_FULL_FLAGS_RST_VAL;\n         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;\n       end else begin\n         if (full_int) begin\n           FULL           <= #`TCQ 1'b1;\n         end else begin\n           FULL           <= #`TCQ 1'b0;\n         end\n\n         if (RST_FULL_GEN) begin\n           ALMOST_FULL    <= #`TCQ 1'b0;\n         end else if (!FULL) begin\n           if (almost_full_int)\n             ALMOST_FULL  <= #`TCQ 1'b1;\n           else\n             ALMOST_FULL  <= #`TCQ 1'b0;\n         end\n       end // wr_rst_i\n     end // always\n   always @ (posedge WR_CLK or posedge wr_rst_i)\n     begin\n       if (wr_rst_i) begin\n         wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};\n       end else begin\n         wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};\n       end // wr_rst_i\n     end // always\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge RD_CLK or posedge rd_rst_i) begin\n         if (rd_rst_i) begin\n           stage1_valid     <= 0;\n           stage2_valid     <= 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN_USER) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n   //Pointers passed into opposite clock domain\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_EMPTY.\n   wire [31:0] num_read_words_pe = \n     num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);\n\n   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n   // (Do not include data in FWFT stages)\n   //Used to calculate PROG_FULL.\n   wire [31:0] num_write_words_pf =\n     num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n    \n    \n   /***************************************************************************\n    * Internal registers and wires\n    **************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire [C_DOUT_WIDTH-1:0] ideal_dout_out;      \n   wire valid_i;\n   wire valid_out1;\n   wire valid_out2;\n   wire valid_out;  \n   wire underflow_i;\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]               err_type                 = 0;\n   reg [1:0]               err_type_d1              = 0;\n   reg [1:0]               err_type_both              = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout               = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_d1            = 0;\n   reg [C_DOUT_WIDTH-1:0]  ideal_dout_both            = 0;\n   reg                     ideal_wr_ack             = 0;\n   reg                     ideal_valid              = 0;\n   reg                     ideal_overflow           = C_OVERFLOW_LOW;\n   reg                     ideal_underflow          = C_UNDERFLOW_LOW;\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   reg         valid_d1     = 0;\n   reg         valid_d2     = 0; \n   \n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n   \n\n  /****************************************************************************\n   * Function Declarations\n   ***************************************************************************/\n\n  /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n      if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n    end\n  endtask\n\n  /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n  /***********************************************************************\n  * hexstr_conv\n  *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n  ***********************************************************************/\n  function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_d2           = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n    end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the \n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n    wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;   \n   wire RD_CLK;\n   wire RD_EN;\n   wire RST;\n   wire WR_CLK;\n   wire WR_EN;\n    */\n\n   //***************************************************************************\n   // Dout may change behavior based on latency\n   //***************************************************************************\n   assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?\n                         ideal_dout_d1: ideal_dout;   \n   assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; \n\n   //***************************************************************************\n   // Assign SBITERR and DBITERR based on latency \n   //***************************************************************************\n   assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                    (C_PRELOAD_LATENCY == 2 &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?\n                    err_type_d1[0]: err_type[0]; \n   assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                    (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                    err_type_d1[1]: err_type[1]; \n  \n   //***************************************************************************\n   // Safety-ckt logic with embedded reg/fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n       //  if (C_HAS_VALID == 1) begin\n       //       assign valid_out = valid_d1;\n       //  end\n             \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)\n          begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else \n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n          end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                  @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n           end\n           else begin\n                   if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                   end\n             end \n           end  \n      end \n      endgenerate   \n\n//***************************************************************************\n   // Safety-ckt logic with embedded reg + fabric reg\n   //***************************************************************************\n     generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n\n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin\n          if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n          else begin\n               ram_rd_en_d1 <= #`TCQ ram_rd_en;\n               fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n          end\n        end\n          \n        always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge RD_CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   ideal_dout_both <= #`TCQ dout_reset_val;\n              end\n           end else begin\n             if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n              \n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n             end\n           end \n         end      \n      end \n      endgenerate    \n \n   //***************************************************************************\n   // Overflow may be active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_OVERFLOW==1) begin : blockOF1\n   assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n      end\n   endgenerate\n\n   assign PROG_EMPTY = ideal_prog_empty;\n   assign PROG_FULL  = ideal_prog_full;\n\n   //***************************************************************************\n   // Valid may change behavior based on latency or active-low\n   //***************************************************************************\n   generate\n      if (C_HAS_VALID==1) begin : blockVL1\n   assign valid_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;\n   assign valid_out1 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?\n                       valid_d1: valid_i;  \n   assign valid_out2 = (C_PRELOAD_LATENCY==2 &&\n                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?\n                       valid_d2: valid_i; \n   assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;\n   assign VALID     = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Underflow may change behavior based on latency or active-low   \n   //***************************************************************************\n   generate\n      if (C_HAS_UNDERFLOW==1) begin : blockUF1\n   assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;\n   assign UNDERFLOW   = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n    end\n   endgenerate\n\n   //***************************************************************************\n   // Write acknowledge may be active low\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_ACK==1) begin : blockWK1\n   assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n     end\n   endgenerate\n\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext\n\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_wr_pntr = 0;\n      reg  [C_PNTR_WIDTH-1:0]  adjusted_rd_pntr = 0;\n      wire [C_PNTR_WIDTH-1:0]  diff_wr_rd_tmp;\n      wire [C_PNTR_WIDTH:0]    diff_wr_rd;\n      reg  [C_PNTR_WIDTH:0]    wr_data_count_i  = 0;\n        always @* begin\n          if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = 0;\n            adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n          end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin\n            adjusted_rd_pntr = rd_pntr_wr;\n            adjusted_wr_pntr = 0;\n            adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n          end else begin\n            adjusted_wr_pntr = wr_pntr;\n            adjusted_rd_pntr = rd_pntr_wr;\n          end\n        end // always @*\n\n        assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;\n        assign diff_wr_rd     = {1'b0,diff_wr_rd_tmp};\n\n        always @ (posedge wr_rst_i or posedge WR_CLK)\n        begin\n            if (wr_rst_i)\n              wr_data_count_i <= 0;\n            else\n              wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;\n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n\n        always @* begin\n          if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];\n          else\n            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n        end // always @*\n      end // wdc_fwft_ext\n   endgenerate\n\n   //***************************************************************************\n   // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n   //***************************************************************************\n   reg  [C_RD_PNTR_WIDTH:0]    rdc_fwft_ext_as  = 0;\n\n   generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n\n\n   always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= 0;\n            end else begin\n              if (!stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 0;\n              else if (!stage1_valid && stage2_valid)\n                rdc_fwft_ext_as <= #`TCQ 1;\n              else\n                rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;\n            end \n        end // always @ (posedge WR_CLK or posedge WR_CLK)\n      end // rdc_fwft_ext\n end\n   endgenerate\n\n\n  generate if (C_USE_EMBEDDED_REG == 3) begin\n     if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;\n      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;\n      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;\n        always @* begin\n          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n            adjusted_wr_pntr_rd = 0;\n            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n          end else begin\n            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n          end\n        end // always @*\n\n        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n        assign diff_rd_wr     = {1'b0,diff_rd_wr_tmp};\n        wire [C_RD_PNTR_WIDTH:0]  diff_rd_wr_1;\n   //     assign diff_rd_wr_1 = diff_rd_wr +2'h2;\n\n       always @ (posedge rd_rst_i or posedge RD_CLK)\n        begin\n            if (rd_rst_i) begin\n              rdc_fwft_ext_as   <= #`TCQ 0;\n            end else begin\n          //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))\n          //    rdc_fwft_ext_as <= 1'b0;\n          //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) \n          //    rdc_fwft_ext_as <= 1'b1;\n          //else\n            rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;\n        end\n\n\n\nend\nend\nend\nendgenerate\n          \n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1) begin : grdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?\n          rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :\n          rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?\n          wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :\n          wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n\n  /**************************************************************************\n  * Assorted registers for delayed versions of signals\n  **************************************************************************/\n  //Capture delayed version of valid\n  generate\n      if (C_HAS_VALID==1) begin : blockVL2\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n      valid_d1 <= 1'b0;\n      valid_d2 <= 1'b0;\n    end else begin\n      valid_d1 <= #`TCQ valid_i;\n      valid_d2 <= #`TCQ valid_d1;\n    end \n//    if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin\n  //      valid_d2 <= #`TCQ valid_d1;\n      //  end \n  end \n      end\n endgenerate  \n   \n  //Capture delayed version of dout\n  /**************************************************************************\n    *embedded/fabric reg with no safety ckt\n    **************************************************************************/\n  generate \n       if (C_USE_EMBEDDED_REG < 3) begin\n  always @(posedge RD_CLK or posedge rd_rst_i) begin\n    if (rd_rst_i == 1'b1) begin\n       if (C_USE_DOUT_RST == 1'b1) begin\n         @(posedge RD_CLK)\n           ideal_dout_d1   <= #`TCQ dout_reset_val;\n           ideal_dout   <= #`TCQ dout_reset_val;\n       end\n      // Reset err_type only if ECC is not selected\n      if (C_USE_ECC == 0)\n        err_type_d1     <= #`TCQ 0;\n     end else if (ram_rd_en_d1) begin\n      ideal_dout_d1   <= #`TCQ ideal_dout;\n      err_type_d1     <= #`TCQ err_type;\n           end    \n  end  \n   \nend  \nendgenerate \n/**************************************************************************\n    *embedded + fabric reg with no safety ckt\n    **************************************************************************/\n\ngenerate \n  if (C_USE_EMBEDDED_REG == 3) begin\n    always @(posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i == 1'b1) begin\n        if (C_USE_DOUT_RST == 1'b1) begin\n           @(posedge RD_CLK)\n             ideal_dout    <= #`TCQ dout_reset_val;\n             ideal_dout_d1   <= #`TCQ dout_reset_val;\n             ideal_dout_both   <= #`TCQ dout_reset_val;\n        end\n        // Reset err_type only if ECC is not selected\n        if (C_USE_ECC == 0) begin\n          err_type_d1     <= #`TCQ 0;\n          err_type_both   <= #`TCQ 0;\n        end\n      end else begin\n         if (ram_rd_en_d1) begin\n           ideal_dout_both   <= #`TCQ ideal_dout;\n           err_type_both     <= #`TCQ err_type;\n         end    \n         if (fab_rd_en_d1) begin\n           ideal_dout_d1   <= #`TCQ ideal_dout_both;\n           err_type_d1     <= #`TCQ err_type_both;\n         end\n      end\n    end  \n  end  \nendgenerate \n\n  \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate\n     if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n       always @(posedge WR_CLK) begin\n         ideal_overflow    <= #`TCQ WR_EN & FULL;\n       end\n     end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n       always @(posedge WR_CLK) begin\n         //ideal_overflow    <= #`TCQ WR_EN & (FULL | wr_rst_i);\n         ideal_overflow    <= #`TCQ WR_EN & (FULL );\n       end\n     end\n   endgenerate\n\n   generate\n     if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ EMPTY & RD_EN;\n       end\n     end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n       always @(posedge RD_CLK) begin\n         ideal_underflow    <= #`TCQ (EMPTY) & RD_EN;\n         //ideal_underflow    <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;\n       end\n     end\n   endgenerate\n\n   /**************************************************************************\n   * Write/Read Pointer Synchronization\n   **************************************************************************/\n   localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;\n   wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n   genvar gss;\n\n   generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst\n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (C_WR_PNTR_WIDTH)\n        )\n     rd_stg_inst\n        (\n         .RST      (rd_rst_i), \n         .CLK      (RD_CLK), \n         .DIN      (wr_pntr_sync_stgs[gss-1]), \n         .DOUT     (wr_pntr_sync_stgs[gss])\n        );\n \n     fifo_generator_v13_2_1_sync_stage\n       #(\n         .C_WIDTH  (C_RD_PNTR_WIDTH)\n        )\n     wr_stg_inst\n        (\n         .RST      (wr_rst_i), \n         .CLK      (WR_CLK), \n         .DIN      (rd_pntr_sync_stgs[gss-1]), \n         .DOUT     (rd_pntr_sync_stgs[gss])\n        );\n   end endgenerate // Sync_stage_inst\n\n   assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;\n   assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;\n   always@* begin\n     wr_pntr_rd           <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n     rd_pntr_wr           <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n   end\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp\n     if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)\n       wr_pntr           <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)\n       wr_pntr           <= #`TCQ 0;\n   end\n   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (wr_rst_i == 1'b1) begin\n       num_wr_bits       <= 0;\n       next_num_wr_bits   = 0;\n       wr_ptr            <= C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= C_RD_DEPTH - 1;\n       ideal_wr_ack      <= 0;\n       ideal_wr_count    <= 0;\n       tmp_wr_listsize    = 0;\n       rd_ptr_wrclk_next <= 0;\n       wr_pntr_rd1       <= 0;\n\n     end else begin //wr_rst_i==0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       //If this is a write, handle the write by adding the value\n       // to the linked list, and updating all outputs appropriately\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD \n             >= C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full, but reporting full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //With DEPTH-1 words in the FIFO, it is almost_full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n\n           //If the FIFO is completely empty, but it is\n           // reporting FULL for some reason (like reset)\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=\n                C_FIFO_WR_DEPTH-2) begin\n             //No change to FIFO\n\n             //Write not successful\n             ideal_wr_ack      <= #`TCQ 0;\n             //FIFO is really not close to full, so change flag status.\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n           end //(tmp_wr_listsize == 0)\n\n         end else begin\n\n           //If the FIFO is full, do NOT perform the write,\n           // update flags accordingly\n           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=\n              C_FIFO_WR_DEPTH) begin\n             //write unsuccessful - do not change contents\n\n             //Do not acknowledge the write\n             ideal_wr_ack       <= #`TCQ 0;\n             //Reminder that FIFO is still full\n\n             ideal_wr_count     <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is one from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n                C_FIFO_WR_DEPTH-1) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;\n\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //This write is CAUSING the FIFO to go full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is 2 from full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == \n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits =  next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Still 2 from full\n\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n           //If the FIFO is not close to being full\n           end else \n             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <\n                C_FIFO_WR_DEPTH-2) begin\n             //Add value on DIN port to FIFO\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error\n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //wr_rst_i==0\n   end // gen_fifo_w\n\n\n  /***************************************************************************\n   * Programmable FULL flags\n   ***************************************************************************/\n\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;\n   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;\n\n   generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;\n   end else begin // STD\n     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;\n     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;\n   end endgenerate\n\n   always @(posedge WR_CLK or posedge wr_rst_i) begin\n\n     if (wr_rst_i == 1'b1) begin\n       diff_pntr         <= 0;\n     end else begin\n       if (ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);\n       else if (!ram_wr_en)\n         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);\n    end\n  end\n\n\n   always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf\n\n     if (RST_FULL_FF & C_HAS_RST) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin\n       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;\n     end else begin\n\n       if (RST_FULL_GEN)\n         ideal_prog_full   <= #`TCQ 0;\n       //Single Programmable Full Constant Threshold\n       else if (C_PROG_FULL_TYPE == 1) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else\n             ideal_prog_full <= #`TCQ 0;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Constant Thresholds\n       end else if (C_PROG_FULL_TYPE == 2) begin\n         if (FULL == 0) begin\n           if (diff_pntr >= pf_thr_assert_val)\n             ideal_prog_full <= #`TCQ 1;\n           else if (diff_pntr < pf_thr_negate_val)\n             ideal_prog_full <= #`TCQ 0;\n           else\n             ideal_prog_full <= #`TCQ ideal_prog_full;\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Single Programmable Full Threshold Input\n       end else if (C_PROG_FULL_TYPE == 3) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH)\n               ideal_prog_full <= #`TCQ 1;\n             else\n               ideal_prog_full <= #`TCQ 0;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       //Two Programmable Full Threshold Inputs\n       end else if (C_PROG_FULL_TYPE == 4) begin\n         if (FULL == 0) begin\n           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n             if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end else begin // STD\n             if (diff_pntr >= PROG_FULL_THRESH_ASSERT)\n               ideal_prog_full <= #`TCQ 1;\n             else if (diff_pntr < PROG_FULL_THRESH_NEGATE)\n               ideal_prog_full <= #`TCQ 0;\n             else\n               ideal_prog_full <= #`TCQ ideal_prog_full;\n           end\n         end else\n           ideal_prog_full   <= #`TCQ ideal_prog_full;\n       end // C_PROG_FULL_TYPE\n\n     end //wr_rst_i==0\n   end //\n\n   \n   /**************************************************************************\n   * Read Domain Logic\n   **************************************************************************/\n\n\n   /*********************************************************\n    * Programmable EMPTY flags\n    *********************************************************/\n   //Determine the Assert and Negate thresholds for Programmable Empty\n\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;\n   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd      = 0;\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe\n\n     if (rd_rst_i & C_HAS_RST) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       diff_pntr_rd       <= 0;\n       ideal_prog_empty   <= 1'b1;\n     end else begin\n       if (ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;\n       else if (!ram_rd_en)\n         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr);\n       else\n         diff_pntr_rd       <=  #`TCQ diff_pntr_rd;\n  \n       if (C_PROG_EMPTY_TYPE == 1) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 2) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 3) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else\n             ideal_prog_empty <= #`TCQ 0;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end else if (C_PROG_EMPTY_TYPE == 4) begin\n         if (EMPTY == 0) begin\n           if (diff_pntr_rd <= pe_thr_assert_val)\n             ideal_prog_empty <= #`TCQ 1;\n           else if (diff_pntr_rd > pe_thr_negate_val)\n             ideal_prog_empty <= #`TCQ 0;\n           else\n             ideal_prog_empty <= #`TCQ ideal_prog_empty;\n         end else\n           ideal_prog_empty   <= #`TCQ ideal_prog_empty;\n       end  //C_PROG_EMPTY_TYPE\n     end\n   end // gen_pe\n\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;\n   end endgenerate // single_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;\n   end endgenerate // multiple_pe_thr_input\n\n   generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const\n     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;\n     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n                                C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;\n   end endgenerate // single_multiple_pe_thr_const\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp\n     if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n       rd_pntr            <= 0;\n     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)\n       rd_pntr            <= #`TCQ 0;\n   end\n\n   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rd_rst_i & C_HAS_RST) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n\n     end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin\n       num_rd_bits        <= 0;\n       next_num_rd_bits    = 0;\n       rd_ptr             <= C_RD_DEPTH -1;\n       rd_pntr_wr1        <= 0;\n       wr_ptr_rdclk       <= C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n          ideal_dout    <= dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= 1'b0;\n       ideal_rd_count     <= 0;\n     end else begin //rd_rst_i==0\n\n       rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 1\n       /*****************************************************************/\n       if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Reminder that FIFO is still empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end // if (tmp_rd_listsize <= 0)\n\n             //If the FIFO is one from empty, but it is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 1)\n\n             //If the FIFO is two from empty, and is reporting empty\n             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid        <= #`TCQ 1'b0;\n                 //Fifo has two words, so is neither empty or almost empty\n\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               end // if (tmp_rd_listsize == 2)\n\n             //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))\n               begin\n                 //Do not change the contents of the FIFO\n\n                 //Do not acknowledge the read from empty FIFO\n                 ideal_valid <= #`TCQ 1'b0;\n                 //Note that the FIFO is No Longer Empty or Almost Empty\n\n                 ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n               end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n             end // else: if(ideal_empty == 1'b1)\n\n           else //if (ideal_empty == 1'b0)\n             begin\n\n               //If the FIFO is completely full, and we are successfully reading from it\n               if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)\n\n               //If the FIFO is not close to being empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Not close to empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n               //If the FIFO is two from empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Fifo is not yet empty. It is going almost_empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n\n               //If the FIFO is one from empty\n               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))\n                 begin\n                   //Read the value from the FIFO\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   //Note that FIFO is GOING empty\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 1)\n\n\n               //If the FIFO is completely empty\n               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n                 begin\n                   //Do not change the contents of the FIFO\n\n                   //Do not acknowledge the read from empty FIFO\n                   ideal_valid        <= #`TCQ 1'b0;\n\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize <= 0)\n\n             end // if (ideal_empty == 1'b0)\n\n           end //(RD_EN == 1'b1)\n\n         else //if (RD_EN == 1'b0)\n           begin\n             //If user did not attempt a read, do not give an ack or err\n             ideal_valid          <= #`TCQ 1'b0;\n\n             ideal_rd_count       <= #`TCQ num_read_words_sized_i;\n\n           end // else: !if(RD_EN == 1'b1)\n\n       /*****************************************************************/\n       // Read Operation - Read Latency 0\n       /*****************************************************************/\n       end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n         if (ram_rd_en == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n\n             //If the FIFO is completely empty, and is reporting empty\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty, but it is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty, and is reporting empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Fifo has two words, so is neither empty or almost empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n               //If the FIFO is not close to empty, but is reporting that it is\n             // Treat the FIFO as empty this time, but unset EMPTY flags.\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                         (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Note that the FIFO is No Longer Empty or Almost Empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n           end else begin\n\n             //If the FIFO is completely full, and we are successfully reading from it\n             if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is not close to being empty\n             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n                          (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Not close to empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is two from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Fifo is not yet empty. It is going almost_empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is one from empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n               //Read the value from the FIFO\n               read_fifo;\n               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n               //Acknowledge the read from the FIFO, no error\n               ideal_valid        <= #`TCQ 1'b1;\n               //Note that FIFO is GOING empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             //If the FIFO is completely empty\n             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n               //Do not change the contents of the FIFO\n\n               //Do not acknowledge the read from empty FIFO\n               ideal_valid        <= #`TCQ 1'b0;\n               //Reminder that FIFO is still empty\n\n               ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n             end // if (tmp_rd_listsize <= 0)\n\n           end // if (ideal_empty == 1'b0)\n\n         end else begin//(RD_EN == 1'b0)\n\n         \n           //If user did not attempt a read, do not give an ack or err\n           ideal_valid           <= #`TCQ 1'b0;\n           ideal_rd_count        <= #`TCQ num_read_words_sized_i;\n\n         end // else: !if(RD_EN == 1'b1)\n       end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //rd_rst_i==0\n   end //always gen_fifo_r_as\n\nendmodule // fifo_generator_v13_2_1_bhv_ver_as\n\n\n/*******************************************************************************\n * Declaration of Low Latency Asynchronous FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_2_1_beh_ver_ll_afifo\n   \n  /***************************************************************************\n   * Declare user parameters and their defaults\n   ***************************************************************************/\n  #(\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_FIFO_TYPE                    = 0\n   )\n\n  /***************************************************************************\n   * Declare Input and Output Ports\n   ***************************************************************************/\n  (\n   input       [C_DIN_WIDTH-1:0]                 DIN,\n   input                                         RD_CLK,\n   input                                         RD_EN,\n   input                                         WR_RST,\n   input                                         RD_RST,\n   input                                         WR_CLK,\n   input                                         WR_EN,\n   output reg  [C_DOUT_WIDTH-1:0]                DOUT = 0,\n   output reg                                    EMPTY = 1'b1,\n   output reg                                    FULL = C_FULL_FLAGS_RST_VAL\n  );\n\n  //-----------------------------------------------------------------------------\n  // Low Latency Asynchronous FIFO\n  //-----------------------------------------------------------------------------\n\n  // Memory which will be used to simulate a FIFO\n  reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n  integer i;\n  initial begin\n    for (i = 0; i < C_WR_DEPTH; i = i + 1)\n      memory[i] = 0;\n  end\n\n  reg  [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;\n  wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;\n  reg  [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;\n  reg                        ll_afifo_full    = 1'b0;\n  reg                        ll_afifo_empty   = 1'b1;\n  wire                       write_allow;\n  wire                       read_allow;\n\n  assign write_allow = WR_EN & ~ll_afifo_full;\n  assign read_allow  = RD_EN & ~ll_afifo_empty;\n\n  //-----------------------------------------------------------------------------\n  // Write Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      wr_pntr_ll_afifo   <= 0;\n    else if (write_allow)\n      wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Read Pointer Generation\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      rd_pntr_ll_afifo_q   <= 0;\n    else\n      rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;\n  end\n  assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;\n  \n  //-----------------------------------------------------------------------------\n  // Fill the Memory\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK) begin\n    if (write_allow)\n      memory[wr_pntr_ll_afifo] <= #`TCQ DIN;\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate DOUT\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK) begin\n      DOUT <= #`TCQ memory[rd_pntr_ll_afifo];\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate EMPTY\n  //-----------------------------------------------------------------------------\n  always @(posedge RD_CLK or posedge RD_RST) begin\n    if (RD_RST)\n      ll_afifo_empty   <= 1'b1;\n    else\n      ll_afifo_empty   <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | \n                           (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));\n  end\n\n  //-----------------------------------------------------------------------------\n  // Generate FULL\n  //-----------------------------------------------------------------------------\n  always @(posedge WR_CLK or posedge WR_RST) begin\n    if (WR_RST)\n      ll_afifo_full   <= 1'b1;\n    else\n      ll_afifo_full   <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | \n                           (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));\n  end\n\n  always @* begin\n    FULL  <= ll_afifo_full;\n    EMPTY <= ll_afifo_empty;\n  end\n\nendmodule // fifo_generator_v13_2_1_beh_ver_ll_afifo\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_v13_2_1_bhv_ver_ss\n   \n  /**************************************************************************\n   * Declare user parameters and their defaults\n   *************************************************************************/\n  #(\n    parameter  C_FAMILY                       = \"virtex7\",\n    parameter  C_DATA_COUNT_WIDTH             = 2,\n    parameter  C_DIN_WIDTH                    = 8,\n    parameter  C_DOUT_RST_VAL                 = \"\",\n    parameter  C_DOUT_WIDTH                   = 8,\n    parameter  C_FULL_FLAGS_RST_VAL           = 1,\n    parameter  C_HAS_ALMOST_EMPTY             = 0,\n    parameter  C_HAS_ALMOST_FULL              = 0,\n    parameter  C_HAS_DATA_COUNT               = 0,\n    parameter  C_HAS_OVERFLOW                 = 0,\n    parameter  C_HAS_RD_DATA_COUNT            = 0,\n    parameter  C_HAS_RST                      = 0,\n    parameter  C_HAS_SRST                     = 0,\n    parameter  C_HAS_UNDERFLOW                = 0,\n    parameter  C_HAS_VALID                    = 0,\n    parameter  C_HAS_WR_ACK                   = 0,\n    parameter  C_HAS_WR_DATA_COUNT            = 0,\n    parameter  C_IMPLEMENTATION_TYPE          = 0,\n    parameter  C_MEMORY_TYPE                  = 1,\n    parameter  C_OVERFLOW_LOW                 = 0,\n    parameter  C_PRELOAD_LATENCY              = 1,\n    parameter  C_PRELOAD_REGS                 = 0,\n    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n    parameter  C_PROG_EMPTY_TYPE              = 0,\n    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,\n    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,\n    parameter  C_PROG_FULL_TYPE               = 0,\n    parameter  C_RD_DATA_COUNT_WIDTH          = 2,\n    parameter  C_RD_DEPTH                     = 256,\n    parameter  C_RD_PNTR_WIDTH                = 8,\n    parameter  C_UNDERFLOW_LOW                = 0,\n    parameter  C_USE_DOUT_RST                 = 0,\n    parameter  C_USE_EMBEDDED_REG             = 0,\n    parameter  C_EN_SAFETY_CKT                = 0,\n    parameter  C_USE_FWFT_DATA_COUNT          = 0,\n    parameter  C_VALID_LOW                    = 0,\n    parameter  C_WR_ACK_LOW                   = 0,\n    parameter  C_WR_DATA_COUNT_WIDTH          = 2,\n    parameter  C_WR_DEPTH                     = 256,\n    parameter  C_WR_PNTR_WIDTH                = 8,\n    parameter  C_USE_ECC                      = 0, \n    parameter  C_ENABLE_RST_SYNC              = 1,\n    parameter  C_ERROR_INJECTION_TYPE         = 0,\n    parameter  C_FIFO_TYPE                    = 0 \n   )\n   \n  /**************************************************************************\n   * Declare Input and Output Ports\n   *************************************************************************/\n   (\n    //Inputs\n    input                                 SAFETY_CKT_WR_RST,\n    input                                 CLK,\n    input       [C_DIN_WIDTH-1:0]         DIN,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_ASSERT,\n    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_NEGATE,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_ASSERT,\n    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_NEGATE,\n    input                                 RD_EN,\n    input                                 RD_EN_USER,\n    input                                 USER_EMPTY_FB,\n    input                                 RST,\n    input                                 RST_FULL_GEN,\n    input                                 RST_FULL_FF,\n    input                                 SRST,\n    input                                 WR_EN,\n    input                                 INJECTDBITERR,\n    input                                 INJECTSBITERR,\n    input                                 WR_RST_BUSY,\n    input                                 RD_RST_BUSY,\n                                    \n    //Outputs                       \n    output                                ALMOST_EMPTY,\n    output                                ALMOST_FULL,\n    output reg   [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,\n    output       [C_DOUT_WIDTH-1:0]       DOUT,\n    output                                EMPTY,\n    output reg                            EMPTY_FB = 1'b1,\n    output                                FULL,\n    output                                OVERFLOW,\n    output [C_RD_DATA_COUNT_WIDTH-1:0]    RD_DATA_COUNT,\n    output [C_WR_DATA_COUNT_WIDTH-1:0]    WR_DATA_COUNT,\n    output                                PROG_EMPTY,\n    output                                PROG_FULL,\n    output                                VALID,\n    output                                UNDERFLOW,\n    output                                WR_ACK,\n    output                                SBITERR,\n    output                                DBITERR\n   );\n\n\n   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n   wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;\n   wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;\n   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n   /***************************************************************************\n    * Parameters used as constants\n    **************************************************************************/\n  localparam IS_8SERIES         = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\" || C_FAMILY == \"virtexuplushbm\") ? 1 : 0;\n   localparam C_DEPTH_RATIO_WR =  \n      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n   localparam C_DEPTH_RATIO_RD =  \n      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n   //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n   //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n   localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; \n\n\n   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC\n   //  -----------------|------------------|-----------------|---------------\n   //  1                | 8                | C_RD_PNTR_WIDTH | 2\n   //  1                | 4                | C_RD_PNTR_WIDTH | 2\n   //  1                | 2                | C_RD_PNTR_WIDTH | 2\n   //  1                | 1                | C_WR_PNTR_WIDTH | 2\n   //  2                | 1                | C_WR_PNTR_WIDTH | 4\n   //  4                | 1                | C_WR_PNTR_WIDTH | 8\n   //  8                | 1                | C_WR_PNTR_WIDTH | 16\n   \n   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n   localparam  EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n   //localparam  EXTRA_WORDS_PE_PARAM  = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n\n   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n   \n   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n   \n   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n   \n   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n   //When RST is present, set FULL reset value to '1'.\n   //If core has no RST, make sure FULL powers-on as '0'.\n   //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not \n   //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.\n   // Therefore, during SRST, all the FULL flags reset to 0.\n   localparam                      C_HAS_FAST_FIFO = 0;\n   localparam                      C_FIFO_WR_DEPTH = C_WR_DEPTH;\n   localparam                      C_FIFO_RD_DEPTH = C_RD_DEPTH;\n   // Local parameters used to determine whether to inject ECC error or not\n   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n   localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;\n   localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;\n   localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;\n   localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n  localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; \n  localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; \n\n\n   /**************************************************************************\n    * FIFO Contents Tracking and Data Count Calculations\n    *************************************************************************/\n   // Memory which will be used to simulate a FIFO\n   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n   reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n   \n   /**************************************************************************\n    * Internal Registers and wires\n    *************************************************************************/\n\n   //Temporary signals used for calculating the model's outputs. These\n   //are only used in the assign statements immediately following wire,\n   //parameter, and function declarations.\n   wire                           underflow_i;\n   wire                           valid_i;\n   wire                           valid_out;\n   reg [31:0]  num_wr_bits;\n   reg [31:0]  num_rd_bits;\n   reg [31:0]  next_num_wr_bits;\n   reg [31:0]  next_num_rd_bits;\n\n   //The write pointer - tracks write operations\n   // (Works opposite to core: wr_ptr is a DOWN counter)\n   reg  [31:0]                 wr_ptr;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;\n   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;\n   reg                         wr_rst_d1      =0;\n\n   //The read pointer - tracks read operations\n   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n   reg  [31:0]                 rd_ptr;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;\n   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;\n\n   wire                        ram_rd_en;\n   wire                        empty_int;\n   wire                        almost_empty_int;\n   wire                        ram_wr_en;\n   wire                        full_int;\n   wire                        almost_full_int;\n   reg                         ram_rd_en_reg = 1'b0;\n   reg                         ram_rd_en_d1 = 1'b0;\n   reg                         fab_rd_en_d1 = 1'b0;\n   wire                         srst_rrst_busy;\n\n\n\n   //Ideal FIFO signals. These are the raw output of the behavioral model,\n   //which behaves like an ideal FIFO.\n   reg [1:0]                      err_type           = 0;\n   reg [1:0]                      err_type_d1        = 0;\n   reg [1:0]                      err_type_both      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout         = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_d1      = 0;\n   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_both      = 0;\n   wire [C_DOUT_WIDTH-1:0]        ideal_dout_out;\n   wire                           fwft_enabled;\n   reg                            ideal_wr_ack       = 0;\n   reg                            ideal_valid        = 0;\n   reg                            ideal_overflow     = C_OVERFLOW_LOW;\n   reg                            ideal_underflow    = C_UNDERFLOW_LOW;\n\n   reg                            full_i             = C_FULL_FLAGS_RST_VAL;\n   reg                            full_i_temp        = 0;\n   reg                            empty_i            = 1;\n   reg                            almost_full_i      = 0;\n   reg                            almost_empty_i     = 1;\n   reg                            prog_full_i        = 0;\n   reg                            prog_empty_i       = 1;\n   reg [C_WR_PNTR_WIDTH-1:0]      wr_pntr            = 0;\n   reg [C_RD_PNTR_WIDTH-1:0]      rd_pntr            = 0;\n   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;\n   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;\n   reg [C_RD_PNTR_WIDTH-1:0]      diff_count         = 0;\n\n   reg                            write_allow_q      = 0;\n   reg                            read_allow_q       = 0;\n   reg                            valid_d1           = 0;\n   reg                            valid_both           = 0;\n   reg                            valid_d2           = 0;\n   wire                           rst_i;\n   wire                           srst_i;\n\n   //user specified value for reseting the size of the fifo\n   reg [C_DOUT_WIDTH-1:0]         dout_reset_val = 0;\n\n   reg [31:0]  wr_ptr_rdclk;\n   reg [31:0]  wr_ptr_rdclk_next;\n   reg [31:0]  rd_ptr_wrclk;\n   reg [31:0]  rd_ptr_wrclk_next;\n\n\n\n\n   /****************************************************************************\n    * Function Declarations\n    ***************************************************************************/\n\n   /****************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***************************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin\n        case (def_data[7:0])\n          8'b00000000 : begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default : begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1) begin\n          if ((index*4)+j < C_DOUT_WIDTH) begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n /**************************************************************************\n  * log2_val\n  *   Returns the 'log2' value for the input value for the supported ratios\n  ***************************************************************************/\n  function [31:0] log2_val;\n    input [31:0] binary_val;\n\n    begin\n      if (binary_val == 8) begin\n        log2_val = 3;\n      end else if (binary_val == 4) begin\n        log2_val = 2;\n      end else begin\n        log2_val = 1;\n      end\n    end\n  endfunction\n\n   reg                     ideal_prog_full          = 0;\n   reg                     ideal_prog_empty         = 1;\n   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n   //Assorted reg values for delayed versions of signals   \n   //reg         valid_d1     = 0;\n   \n   \n   //user specified value for reseting the size of the fifo\n   //reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;\n   \n   //temporary registers for WR_RESPONSE_LATENCY feature\n   \n   integer                           tmp_wr_listsize;\n   integer                           tmp_rd_listsize;\n   \n   //Signal for registered version of prog full and empty\n   \n   //Threshold values for Programmable Flags\n   integer                           prog_empty_actual_thresh_assert;\n   integer                           prog_empty_actual_thresh_negate;\n   integer                           prog_full_actual_thresh_assert;\n   integer                           prog_full_actual_thresh_negate;\n\n\n /**************************************************************************\n   * write_fifo\n   *   This task writes a word to the FIFO memory and updates the \n   * write pointer.\n   *   FIFO size is relative to write domain.\n  ***************************************************************************/\n  task write_fifo;\n    begin\n      memory[wr_ptr]     <= DIN;\n      wr_pntr <= #`TCQ wr_pntr + 1;\n      // Store the type of error injection (double/single) on write\n      case (C_ERROR_INJECTION_TYPE)\n        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};\n        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1'b0};\n        1:       ecc_err[wr_ptr]    <= {1'b0,INJECTSBITERR};\n        default: ecc_err[wr_ptr]    <= 0;\n      endcase\n      // (Works opposite to core: wr_ptr is a DOWN counter)\n      if (wr_ptr == 0) begin\n        wr_ptr          <= C_WR_DEPTH - 1;\n      end else begin\n        wr_ptr          <= wr_ptr - 1;\n      end\n    end\n  endtask // write_fifo\n\n  /**************************************************************************\n   * read_fifo\n   *   This task reads a word from the FIFO memory and updates the read \n   * pointer. It's output is the ideal_dout bus.\n   *   FIFO size is relative to write domain.\n   ***************************************************************************/\n  task read_fifo;\n    integer i;\n    reg [C_DOUT_WIDTH-1:0]      tmp_dout;\n    reg [C_DIN_WIDTH-1:0]       memory_read;\n    reg [31:0]                  tmp_rd_ptr;\n    reg [31:0]                  rd_ptr_high;\n    reg [31:0]                  rd_ptr_low;\n    reg [1:0]                   tmp_ecc_err;\n    begin\n      rd_pntr <= #`TCQ rd_pntr + 1;\n\n      // output is wider than input\n      if (reads_per_write == 0) begin\n        tmp_dout = 0;\n        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n          tmp_dout = tmp_dout << C_DIN_WIDTH;\n          tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n           \n          // (Works opposite to core: rd_ptr is a DOWN counter)\n          if (tmp_rd_ptr == 0) begin\n            tmp_rd_ptr = C_WR_DEPTH - 1;\n          end else begin\n            tmp_rd_ptr = tmp_rd_ptr - 1;\n          end\n        end\n\n      // output is symmetric\n      end else if (reads_per_write == 1) begin\n        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n        // Retreive the error injection type. Based on the error injection type\n        // corrupt the output data.\n        tmp_ecc_err = ecc_err[rd_ptr];\n        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n            if (C_DOUT_WIDTH == 1) begin\n              $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n              $finish;\n            end else if (C_DOUT_WIDTH == 2)\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n            else\n              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n          end else begin\n            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n          end\n          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n        end else begin\n          err_type <= 0;\n        end\n\n      // input is wider than output\n      end else begin\n        rd_ptr_high = rd_ptr >> log2_reads_per_write;\n        rd_ptr_low  = rd_ptr & (reads_per_write - 1);\n        memory_read = memory[rd_ptr_high];\n        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n      end\n      ideal_dout <= tmp_dout;\n       \n      // (Works opposite to core: rd_ptr is a DOWN counter)\n     if (rd_ptr == 0) begin\n        rd_ptr <= C_RD_DEPTH - 1;\n      end else begin\n        rd_ptr <= rd_ptr - 1;\n      end\n\n     end\n  endtask\n\n\n   \n  /*************************************************************************\n  * Initialize Signals for clean power-on simulation\n  *************************************************************************/\n   initial begin\n      num_wr_bits        = 0;\n      num_rd_bits        = 0;\n      next_num_wr_bits   = 0;\n      next_num_rd_bits   = 0;\n      rd_ptr             = C_RD_DEPTH - 1;\n      wr_ptr             = C_WR_DEPTH - 1;\n      wr_pntr            = 0;\n      rd_pntr            = 0;\n      rd_ptr_wrclk       = rd_ptr;\n      wr_ptr_rdclk       = wr_ptr;\n      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);\n      ideal_dout         = dout_reset_val;\n      err_type           = 0;\n      err_type_d1        = 0;\n      err_type_both      = 0;\n      ideal_dout_d1      = dout_reset_val;\n      ideal_dout_both    = dout_reset_val;\n      ideal_wr_ack       = 1'b0;\n      ideal_valid        = 1'b0;\n      valid_d1           = 1'b0;\n      valid_both         = 1'b0;\n      ideal_overflow     = C_OVERFLOW_LOW;\n      ideal_underflow    = C_UNDERFLOW_LOW;\n      ideal_wr_count     = 0;\n      ideal_rd_count     = 0;\n      ideal_prog_full    = 1'b0;\n      ideal_prog_empty   = 1'b1;\n\n   end\n\n\n  /*************************************************************************\n   * Connect the module inputs and outputs to the internal signals of the\n   * behavioral model.\n   *************************************************************************/\n   //Inputs\n   /*\n   wire CLK;\n   wire [C_DIN_WIDTH-1:0] DIN;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;\n   wire RD_EN;\n   wire RST;\n   wire WR_EN;\n    */\n\n  // Assign ALMOST_EPMTY\n  generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae\n    assign ALMOST_EMPTY = almost_empty_i;\n  end else begin : gnae\n    assign ALMOST_EMPTY = 0;\n  end endgenerate // gae\n\n  // Assign ALMOST_FULL\n  generate if (C_HAS_ALMOST_FULL==1) begin : gaf\n    assign ALMOST_FULL  = almost_full_i;\n  end else begin : gnaf\n    assign ALMOST_FULL  = 0;\n  end endgenerate // gaf\n\n   // Dout may change behavior based on latency\n  localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n                         1: 0;\n  assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?\n                         ideal_dout_d1: ideal_dout; \n  assign DOUT = ideal_dout_out;\n\n  // Assign SBITERR and DBITERR based on latency \n  assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[0]: err_type[0]; \n  assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n                   err_type_d1[1]: err_type[1]; \n\n  assign EMPTY         = empty_i;\n  assign FULL          = full_i;\n  //saftey_ckt with one register\n\n  generate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)\n          begin\n          if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n              ram_rd_en_d1 <= #`TCQ 1'b0;\n              valid_d1 <= #`TCQ 1'b0;\n          end\n          else begin\n               ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n               valid_d1 <= #`TCQ valid_i;\n          end\n          end\n          \n           always@(posedge rst_delayed_sft2 or posedge CLK) \n           begin\n           if (rst_delayed_sft2 == 1'b1) begin\n              if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n              end\n              end\n           else if (srst_rrst_busy == 1'b1) begin\n                   if (C_USE_DOUT_RST == 1'b1) begin\n                   ideal_dout_d1 <= #`TCQ dout_reset_val;\n                   end\n           end else if (ram_rd_en_d1) begin\n                   ideal_dout_d1   <= #`TCQ ideal_dout;\n                   err_type_d1[0] <= #`TCQ err_type[0];\n                   err_type_d1[1] <= #`TCQ err_type[1];\n                end\n           end   \n      end //if \n      endgenerate   \n\n//safety ckt with both registers\n\ngenerate\n         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         \n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge CLK) begin\n          rst_delayed_sft1 <= #`TCQ rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            valid_d1 <= #`TCQ 1'b0;\n          end else begin\n            ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n            fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n            valid_both <= #`TCQ valid_i;\n            valid_d1 <= #`TCQ valid_both;\n          end\n        end\n\n        always@(posedge rst_delayed_sft2 or posedge CLK) begin\n          if (rst_delayed_sft2 == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n                   @(posedge CLK)\n                  ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else if (srst_rrst_busy == 1'b1) begin\n             if (C_USE_DOUT_RST == 1'b1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n             end\n          end else begin \n            if (ram_rd_en_d1) begin\n               ideal_dout_both   <= #`TCQ ideal_dout;\n               err_type_both[0] <= #`TCQ err_type[0];\n               err_type_both[1] <= #`TCQ err_type[1];\n             end\n             if (fab_rd_en_d1) begin\n               ideal_dout_d1   <= #`TCQ ideal_dout_both;\n               err_type_d1[0] <= #`TCQ err_type_both[0];\n               err_type_d1[1] <= #`TCQ err_type_both[1];\n            end\n          end\n        end\n      end //if \n      endgenerate    \n \n \n  //Overflow may be active-low\n  generate if (C_HAS_OVERFLOW==1) begin : gof\n    assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n  end else begin : gnof\n    assign OVERFLOW = 0;\n  end endgenerate // gof\n\n  assign PROG_EMPTY    = prog_empty_i;\n  assign PROG_FULL     = prog_full_i;\n\n   //Valid may change behavior based on latency or active-low\n  generate if (C_HAS_VALID==1) begin : gvalid\n    assign valid_i       = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;\n    assign valid_out     = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?\n                            valid_d1 : valid_i; \n    assign VALID         = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n  end else begin : gnvalid\n    assign VALID         = 0;\n  end endgenerate // gvalid\n\n  //Trim data count differently depending on set widths\n  generate if (C_HAS_DATA_COUNT == 1) begin : gdc\n    always @* begin\n      diff_count <= wr_pntr - rd_pntr;\n      if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin\n        DATA_COUNT[C_RD_PNTR_WIDTH-1:0]  <= diff_count;\n        DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; \n      end else begin\n        DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];\n      end\n    end\n//  end else begin : gndc\n//    always @* DATA_COUNT <= 0;\n  end endgenerate // gdc\n\n  //Underflow may change behavior based on latency or active-low\n  generate if (C_HAS_UNDERFLOW==1) begin : guf\n    assign underflow_i   = ideal_underflow;\n    assign UNDERFLOW     = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n  end else begin : gnuf\n    assign UNDERFLOW     = 0;\n  end endgenerate // guf\n \n\n  //Write acknowledge may be active low \n  generate if (C_HAS_WR_ACK==1) begin : gwr_ack\n    assign WR_ACK        = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n  end else begin : gnwr_ack\n    assign WR_ACK        = 0;\n  end endgenerate // gwr_ack\n\n\n  /*****************************************************************************\n   * Internal reset logic \n   ****************************************************************************/\n  assign srst_i        = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;\n  assign rst_i            = C_HAS_RST ? RST : 0;\n  assign srst_wrst_busy   = srst_i;\n  assign srst_rrst_busy   = srst_i;\n\n   /**************************************************************************\n    * Assorted registers for delayed versions of signals\n    **************************************************************************/\n   //Capture delayed version of valid\n   generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20\n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1 <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n           end else begin\n              valid_d1 <= #`TCQ valid_i;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n     end \n   endgenerate // blockVL20\n\n  generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin \n     always @(posedge CLK or posedge rst_i) begin\n        if (rst_i == 1'b1) begin\n           valid_d1   <= 1'b0;\n           valid_both <= 1'b0;\n        end else begin\n           if (srst_rrst_busy) begin\n              valid_d1 <= #`TCQ 1'b0;\n              valid_both <= #`TCQ 1'b0;\n              \n           end else begin\n              valid_both <= #`TCQ valid_i;\n               valid_d1 <= #`TCQ valid_both;\n           end\n        end    \n     end // always @ (posedge CLK or posedge rst_i)\n  end\n endgenerate // blockVL20\n\n\n   // Determine which stage in FWFT registers are valid\n   reg stage1_valid = 0;\n   reg stage2_valid = 0;\n   generate\n     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n       always @ (posedge CLK or posedge rst_i) begin\n         if (rst_i) begin\n           stage1_valid     <= #`TCQ 0;\n           stage2_valid     <= #`TCQ 0;\n         end else begin\n\n           if (!stage1_valid && !stage2_valid) begin\n             if (!EMPTY)\n               stage1_valid    <= #`TCQ 1'b1;\n             else\n               stage1_valid    <= #`TCQ 1'b0;\n           end else if (stage1_valid && !stage2_valid) begin\n             if (EMPTY) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (!stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b0;\n             end else if (!EMPTY && !RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else if (stage1_valid && stage2_valid) begin\n             if (EMPTY && RD_EN) begin\n               stage1_valid    <= #`TCQ 1'b0;\n               stage2_valid    <= #`TCQ 1'b1;\n             end else begin\n               stage1_valid    <= #`TCQ 1'b1;\n               stage2_valid    <= #`TCQ 1'b1;\n             end\n           end else begin\n             stage1_valid    <= #`TCQ 1'b0;\n             stage2_valid    <= #`TCQ 1'b0;\n           end\n         end // rd_rst_i\n       end // always\n     end\n   endgenerate\n\n\n\n   //***************************************************************************\n   // Assign the read data count value only if it is selected, \n   // otherwise output zeros.\n   //***************************************************************************\n   generate\n      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc\n       assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n      end\n   endgenerate\n\n   generate\n      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n\n   //***************************************************************************\n   // Assign the write data count value only if it is selected, \n   // otherwise output zeros\n   //***************************************************************************\n   generate\n      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc\n       assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;\n      end\n   endgenerate\n   \n   generate\n      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n      end\n   endgenerate\n   \n   //reg ram_rd_en_d1 = 1'b0;\n   //Capture delayed version of dout\n   generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         ram_rd_en_d1 <= #`TCQ 1'b0;\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n        end\n      end else begin\n         ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n         if (srst_rrst_busy) begin\n            ram_rd_en_d1 <= #`TCQ 1'b0;\n            // Reset err_type only if ECC is not selected\n            if (C_USE_ECC == 0) begin\n               err_type_d1   <= #`TCQ 0;\n               err_type_both <= #`TCQ 0;\n            end\n            // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n            if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n               ideal_dout_d1 <= #`TCQ dout_reset_val;\n            end \n         if (C_USE_DOUT_RST == 1) begin\n           // @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n         end\n         end else begin\n            if (ram_rd_en_d1 ) begin\n            ideal_dout_d1 <= #`TCQ ideal_dout;\n            err_type_d1   <= #`TCQ err_type;\n            end\n         end\n      end    \n   end   // always\nend\nendgenerate \n\n//no safety ckt with both registers\n generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin\n   always @(posedge CLK or posedge rst_i) begin\n      if (rst_i == 1'b1) begin\n          ram_rd_en_d1 <= #`TCQ 1'b0;\n          fab_rd_en_d1 <= #`TCQ 1'b0;\n         // Reset err_type only if ECC is not selected\n         if (C_USE_ECC == 0) begin\n            err_type_d1      <= #`TCQ 0;\n            err_type_both    <= #`TCQ 0;\n         end\n         // DRAM and SRAM reset asynchronously\n         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val; \n            \n      end\n        if (C_USE_DOUT_RST == 1) begin\n            @(posedge CLK)\n            ideal_dout_d1 <= #`TCQ dout_reset_val;\n            ideal_dout_both <= #`TCQ dout_reset_val;\n       end\n      end else begin\n         if (srst_rrst_busy) begin \n           ram_rd_en_d1 <= #`TCQ 1'b0;\n           fab_rd_en_d1 <= #`TCQ 1'b0;\n           // Reset err_type only if ECC is not selected\n           if (C_USE_ECC == 0) begin\n              err_type_d1   <= #`TCQ 0;\n              err_type_both <= #`TCQ 0;\n           end\n           // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n           if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n              ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end \n           if (C_USE_DOUT_RST == 1) begin\n             ideal_dout_d1 <= #`TCQ dout_reset_val;\n           end\n         end else begin\n           ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n           fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);\n           if (ram_rd_en_d1 ) begin\n             ideal_dout_both <= #`TCQ ideal_dout;\n             err_type_both   <= #`TCQ err_type;\n           end\n           if (fab_rd_en_d1 ) begin\n             ideal_dout_d1 <= #`TCQ ideal_dout_both;\n             err_type_d1   <= #`TCQ err_type_both;\n           end\n         end\n      end    \n   end   // always\nend\nendgenerate \n   /**************************************************************************\n    * Overflow and Underflow Flag calculation\n    *  (handled separately because they don't support rst)\n    **************************************************************************/\n   generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n     always @(posedge CLK) begin\n       ideal_overflow    <= #`TCQ WR_EN & full_i;\n     end\n   end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n     always @(posedge CLK) begin\n       //ideal_overflow    <= #`TCQ WR_EN & (rst_i | full_i);\n       ideal_overflow    <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);\n     end\n   end endgenerate // blockOF20\n \n   generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n     always @(posedge CLK) begin\n       ideal_underflow   <= #`TCQ empty_i & RD_EN;\n     end\n   end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n     always @(posedge CLK) begin\n       //ideal_underflow   <= #`TCQ (rst_i | empty_i) & RD_EN;\n       ideal_underflow   <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;\n     end\n   end endgenerate // blockUF20\n\n\n   /**************************\n    * Read Data Count\n    *************************/\n\n   reg [31:0] num_read_words_dc;\n   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n   \n   always @(num_rd_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //If using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain, \n        // and add two read words for FWFT stages\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //If not using extra logic for FWFT Data Counts, \n        // then scale FIFO contents to read domain.\n        //This value is only a temporary value and not used in the code.\n        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_read_words_sized_i = \n          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n   \n   /**************************\n    * Write Data Count\n    *************************/\n\n   reg [31:0] num_write_words_dc;\n   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n   \n   always @(num_wr_bits) begin\n     if (C_USE_FWFT_DATA_COUNT) begin\n        \n        //Calculate the Data Count value for the number of write words, \n        // when using First-Word Fall-Through with extra logic for Data \n        // Counts. This takes into consideration the number of words that \n        // are expected to be stored in the FWFT register stages (it always \n        // assumes they are filled).\n        //This value is scaled to the Write Domain.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //EXTRA_WORDS_DC is the number of words added to write_words \n        // due to FWFT.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n        \n        //Trim the write words for use with WR_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n        \n     end else begin\n        \n        //Calculate the Data Count value for the number of write words, when NOT\n        // using First-Word Fall-Through with extra logic for Data Counts. This \n        // calculates only the number of words in the internal FIFO.\n        //The expression (((A-1)/B))+1 divides A/B, but takes the \n        // ceiling of the result.\n        //This value is scaled to the Write Domain.\n        //When num_wr_bits==0, set the result manually to prevent \n        // division errors.\n        //This value is only a temporary value and not used in the code.\n        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n        \n        //Trim the read words for use with RD_DATA_COUNT\n        num_write_words_sized_i = \n          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n        \n     end //if (C_USE_FWFT_DATA_COUNT)\n   end //always\n\n\n  /*************************************************************************\n   * Write and Read Logic  \n   ************************************************************************/\n   wire              write_allow;\n   wire              read_allow;\n   wire              read_allow_dc;\n   wire              write_only;\n   wire              read_only;\n   //wire              write_only_q;\n   reg              write_only_q;\n   //wire              read_only_q;\n   reg              read_only_q;\n   reg              full_reg;\n   reg              rst_full_ff_reg1;\n   reg              rst_full_ff_reg2;\n   wire              ram_full_comb;\n   wire              carry;\n   \n   assign write_allow  = WR_EN & ~full_i;\n   assign read_allow   = RD_EN & ~empty_i;\n   assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;\n   //assign write_only   = write_allow & ~read_allow;\n   //assign write_only_q = write_allow_q;\n   //assign read_only    = read_allow    & ~write_allow;\n   //assign read_only_q  = read_allow_q ;\n   wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;\n   reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;\n   wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;\n   wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;\n   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;\n   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;\n\n   assign diff_pntr_pe_max = DIFF_MAX_RD;\n   assign diff_pntr_max = DIFF_MAX_WR;\n\n\n\n   generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym\n    assign write_only   = write_allow & ~read_allow;\n    assign read_only    = read_allow    & ~write_allow;\n    end endgenerate\n    generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd\n     assign read_only   = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;\n     assign write_only    = write_allow    & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n    generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr\n     assign read_only   = read_allow & ~(write_allow  & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n     assign write_only    = write_allow &  &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;\n    end endgenerate\n\n\n   //-----------------------------------------------------------------------------\n   // Write and Read pointer generation\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       wr_pntr         <= 0;\n       rd_pntr         <= 0;\n     end else begin\n       if (srst_i) begin\n         wr_pntr       <= #`TCQ 0;\n         rd_pntr       <= #`TCQ 0;\n       end else begin\n         if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;\n         if (read_allow)  rd_pntr <= #`TCQ rd_pntr + 1;\n       end\n     end\n   end\n\n   generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout\n   always @(posedge CLK) begin\n     if (write_allow) begin\n       if (ENABLE_ERR_INJECTION == 1)\n         memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};\n       else\n         memory[wr_pntr] <= #`TCQ DIN;\n     end\n   end\n\n   reg  [C_DATA_WIDTH-1:0] dout_tmp_q;\n   reg [C_DATA_WIDTH-1:0] dout_tmp = 0;\n   reg  [C_DATA_WIDTH-1:0] dout_tmp1 = 0;\n   always @(posedge CLK) begin\n     dout_tmp_q <= #`TCQ ideal_dout;\n   end\n\n\n\n     always @* begin\n       if (read_allow)\n         ideal_dout <= memory[rd_pntr];\n       else\n         ideal_dout <= dout_tmp_q;\n     end\n   end endgenerate // gll_dm_dout\n\n\n   /**************************************************************************\n   * Write Domain Logic\n   **************************************************************************/\n   assign ram_rd_en        = RD_EN & !EMPTY;\n\n   //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n   generate if (C_FIFO_TYPE != 2) begin : gnll_din\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_w\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i == 1'b1) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n\n     end else begin //rst_i==0\n     if (srst_wrst_busy) begin\n       num_wr_bits       <= #`TCQ 0;\n       next_num_wr_bits   = #`TCQ 0;\n       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;\n       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;\n       ideal_wr_ack      <= #`TCQ 0;\n       ideal_wr_count    <= #`TCQ 0;\n       tmp_wr_listsize    = #`TCQ 0;\n       rd_ptr_wrclk_next <= #`TCQ 0;\n       wr_pntr           <= #`TCQ 0;\n       wr_pntr_rd1       <= #`TCQ 0;\n     end else begin//srst_i=0\n\n       wr_pntr_rd1   <= #`TCQ wr_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n                         num_wr_bits/C_DIN_WIDTH;\n       rd_ptr_wrclk_next = rd_ptr;\n       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n                                          - rd_ptr_wrclk_next);\n       end else begin\n         next_num_wr_bits = num_wr_bits -\n                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n       end\n\n       if (WR_EN == 1'b1) begin\n         if (FULL == 1'b1) begin\n\n             ideal_wr_ack      <= #`TCQ 0;\n             //Reminder that FIFO is still full\n             ideal_wr_count    <= #`TCQ num_write_words_sized_i;\n\n         end else begin\n             write_fifo;\n             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;\n             //Write successful, so issue acknowledge\n             // and no error  \n             ideal_wr_ack      <= #`TCQ 1;\n             //Not even close to full.\n             ideal_wr_count    <= num_write_words_sized_i;\n\n           //end\n\n         end\n\n       end else begin //(WR_EN == 1'b1)\n\n         //If user did not attempt a write, then do not\n         // give ack or err\n         ideal_wr_ack   <= #`TCQ 0;\n         ideal_wr_count <= #`TCQ num_write_words_sized_i;\n       end\n       num_wr_bits       <= #`TCQ next_num_wr_bits;\n       rd_ptr_wrclk      <= #`TCQ rd_ptr;\n\n     end //srst_i==0\n     end //wr_rst_i==0\n   end // gen_fifo_w\n    end endgenerate\n\n   generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout\n     always @(posedge CLK) begin\n       if (rst_i || srst_rrst_busy) begin\n         if (C_USE_DOUT_RST == 1) begin\n           ideal_dout <= #`TCQ dout_reset_val;\n           ideal_dout_both <= #`TCQ dout_reset_val;\n         end\n       end\n     end\n    end endgenerate\n\n\n\n\n   generate if (C_FIFO_TYPE != 2) begin : gnll_dout\n   always @(posedge CLK or posedge rst_i) begin : gen_fifo_r\n\n     /****** Reset fifo (case 1)***************************************/\n     if (rst_i) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets asynchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= 0;\n         err_type_both    <= 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n\n     end else begin //rd_rst_i==0\n     if (srst_rrst_busy) begin\n       num_rd_bits        <= #`TCQ 0;\n       next_num_rd_bits    = #`TCQ 0;\n       rd_ptr             <= #`TCQ C_RD_DEPTH -1;\n       rd_pntr            <= #`TCQ 0;\n       //rd_pntr_wr1       <= #`TCQ 0;\n       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;\n  \n       // DRAM resets synchronously\n       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n          ideal_dout    <= #`TCQ dout_reset_val;\n  \n       // Reset err_type only if ECC is not selected\n       if (C_USE_ECC == 0) begin\n         err_type         <= #`TCQ 0;\n         err_type_d1      <= #`TCQ 0;\n         err_type_both    <= #`TCQ 0;\n       end\n       ideal_valid        <= #`TCQ 1'b0;\n       ideal_rd_count     <= #`TCQ 0;\n      end //srst_i\n      else begin\n\n       //rd_pntr_wr1   <= #`TCQ rd_pntr;\n\n       //Determine the current number of words in the FIFO\n       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n                         num_rd_bits/C_DOUT_WIDTH;\n       wr_ptr_rdclk_next = wr_ptr;\n\n       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n         next_num_rd_bits = num_rd_bits +\n                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n                                         - wr_ptr_rdclk_next);\n       end else begin\n         next_num_rd_bits = num_rd_bits +\n                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n       end\n\n         if (RD_EN == 1'b1) begin\n\n           if (EMPTY == 1'b1) begin\n                 ideal_valid        <= #`TCQ 1'b0;\n                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n               end \n           else \n             begin\n                   read_fifo;\n                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n                   //Acknowledge the read from the FIFO, no error\n                   ideal_valid        <= #`TCQ 1'b1;\n                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;\n\n                 end // if (tmp_rd_listsize == 2)\n         end\n\n       num_rd_bits      <= #`TCQ next_num_rd_bits;\n       wr_ptr_rdclk     <= #`TCQ wr_ptr;\n     end //s_rst_i==0\n     end //rd_rst_i==0\n   end //always\n  end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate diff_pntr for PROG_FULL generation\n   // Generate diff_pntr_pe for PROG_EMPTY generation\n   //-----------------------------------------------------------------------------\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         write_only_q   <= 1'b0;\n         read_only_q    <= 1'b0;\n         diff_pntr_reg1       <= 0;\n         diff_pntr_pe_reg1    <= 0;\n         diff_pntr_reg2       <= 0;\n         diff_pntr_pe_reg2    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_rrst_busy) begin\n           read_only_q  <= #`TCQ 1'b0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n           diff_pntr_pe_reg2  <= #`TCQ 0;\n          end\n          if (srst_wrst_busy) begin\n           write_only_q <= #`TCQ 1'b0;\n           diff_pntr_reg1     <= #`TCQ 0;\n           diff_pntr_reg2     <= #`TCQ 0;\n          end\n         end else begin\n           write_only_q <= #`TCQ write_only;\n           read_only_q  <= #`TCQ read_only;\n           diff_pntr_reg2  <= #`TCQ diff_pntr_reg1;\n           diff_pntr_pe_reg2  <= #`TCQ diff_pntr_pe_reg1;\n\n           // Add 1 to the difference pointer value when only write happens.\n           if (write_only)  \n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;\n           else\n             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;\n\n           // Add 1 to the difference pointer value when write or both write & read or no write & read happen.\n           if (read_only)  \n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;\n           else\n             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;\n         end\n       end\n     end\n   assign diff_pntr_pe = diff_pntr_pe_reg1;\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow\n\n   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym\n    assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};\n    assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};\n     always @(posedge CLK ) begin\n       if (rst_i) begin\n         diff_pntr_pe_asym    <= 0;\n         diff_pntr_reg1       <= 0;\n         full_reg             <= 0;\n         rst_full_ff_reg1     <= 1;\n         rst_full_ff_reg2     <= 1;\n         diff_pntr_pe_reg1    <= 0;\n       end else begin\n         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n          if (srst_wrst_busy)\n           diff_pntr_reg1     <= #`TCQ 0;\n          if (srst_rrst_busy)\n           full_reg             <=  #`TCQ 0;\n           rst_full_ff_reg1     <=  #`TCQ 1;\n           rst_full_ff_reg2     <=  #`TCQ 1;\n           diff_pntr_pe_asym    <=  #`TCQ 0;\n           diff_pntr_pe_reg1  <= #`TCQ 0;\n         end else begin\n             diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;\n             full_reg          <= #`TCQ full_i;\n             rst_full_ff_reg1  <=  #`TCQ RST_FULL_FF;\n             rst_full_ff_reg2  <=  #`TCQ rst_full_ff_reg1;\n           if (~full_i) begin  \n             diff_pntr_reg1 <=  #`TCQ wr_pntr - adj_rd_pntr_wr;\n          end\n         end\n       end\n     end\n   assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));\n   assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];\n   assign diff_pntr = diff_pntr_reg1;\n   end endgenerate // reg_write_allow_asym\n\n\n   //-----------------------------------------------------------------------------\n   // Generate FULL flag\n   //-----------------------------------------------------------------------------\n   wire                 comp0;\n   wire                 comp1;\n   wire                 going_full;\n   wire                 leaving_full;\n \n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin :  gpad \t\n    assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;\n    assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin :  gtrim \n    assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n  end endgenerate\n\n   assign comp1         = (adj_rd_pntr_wr == (wr_pntr + 1'b1));\n   assign comp0         = (adj_rd_pntr_wr == wr_pntr);\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp\n     assign going_full    = (comp1 & write_allow & ~read_allow);\n     assign leaving_full  = (comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym\n      assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp \n      assign going_full = (comp1 & write_allow & ~read_allow);\n      assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n\n   assign ram_full_comb = going_full | (~leaving_full & full_i);\n\n   generate if (C_HAS_RST == 1) begin : grst_full\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF & C_HAS_RST)\n         full_i   <= C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_SRST == 1) begin : gsrst_full\n     always @(posedge CLK) begin\n       if (srst_wrst_busy)\n         full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else\n         full_i   <= #`TCQ ram_full_comb;\n      end\n   end endgenerate\n\n   generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_full\n     always @(posedge CLK) begin\n         full_i   <= #`TCQ ram_full_comb;\n     end\n   end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate EMPTY flag\n   //-----------------------------------------------------------------------------\n   wire                 ecomp0;\n   wire                 ecomp1;\n   wire                 going_empty;\n   wire                 leaving_empty;\n   wire                 ram_empty_comb;\n\n  \n generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin :  pad \t\n    assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n    assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;\n  end endgenerate\n\n  generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin :  trim \n    assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n  end endgenerate\n\n   assign ecomp1         = (adj_wr_pntr_rd == (rd_pntr + 1'b1));\n   assign ecomp0         = (adj_wr_pntr_rd == rd_pntr);\n\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp\n     assign going_empty    = (ecomp1 & ~write_allow & read_allow);\n     assign leaving_empty  = (ecomp0 & write_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp\n      assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp \n      assign going_empty = (ecomp1 & ~write_allow & read_allow);\n      assign leaving_empty =(ecomp0 & write_allow);\n    end endgenerate\n\n\n\n    assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);\n\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       empty_i  <= 1'b1;\n     else if (srst_rrst_busy)\n       empty_i  <= #`TCQ 1'b1;\n     else\n       empty_i  <= #`TCQ ram_empty_comb;\n    end\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i && C_EN_SAFETY_CKT == 0) begin\n       EMPTY_FB     <= 1'b1;\n     end else begin\n       if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))\n         EMPTY_FB   <= #`TCQ 1'b1;\n       else\n         EMPTY_FB   <= #`TCQ ram_empty_comb;\n     end\n   end // always\n\n   //-----------------------------------------------------------------------------\n   // Generate Read and write data counts for asymmetic common clock\n   //-----------------------------------------------------------------------------\n\n    reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; \n    wire [C_GRTR_PNTR_WIDTH :0] ratio; \n    wire decr_by_one;\n    wire incr_by_ratio;\n    wire incr_by_one;\n    wire decr_by_ratio;\n\n   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n\n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr \n      assign ratio         = C_DEPTH_RATIO_RD;\n      assign decr_by_one   = (IS_FWFT == 1)? read_allow_dc : read_allow;\n      assign incr_by_ratio = write_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (decr_by_one) begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc - 1;\n           else\n\t    count_dc <= #`TCQ count_dc - 1  + ratio ;\n\t end\n\t else begin\n\t   if (!incr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc + ratio ;\n\tend\n       end\n       end\n\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n\n    end endgenerate\n\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd \n      assign ratio         = C_DEPTH_RATIO_WR;\n      assign incr_by_one   = write_allow;\n      assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;\n\n      always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         count_dc  <= #`TCQ 0;\n       else if (srst_wrst_busy)\n         count_dc  <= #`TCQ 0;\n       else begin\n\t if (incr_by_one) begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc + 1;\n           else\n\t    count_dc <= #`TCQ count_dc + 1  - ratio ;\n\t end\n\t else begin\n\t   if (!decr_by_ratio) \n            count_dc <= #`TCQ count_dc ;\n           else\n\t    count_dc <= #`TCQ count_dc - ratio ;\n\tend\n       end\n       end\n\n       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;\n       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n\n    end endgenerate\n\n\n\n\n\n\n   //-----------------------------------------------------------------------------\n   // Generate WR_ACK flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_wr_ack  <= 1'b0;\n     else if (srst_wrst_busy)\n       ideal_wr_ack  <= #`TCQ 1'b0;\n     else if (WR_EN & ~full_i)\n       ideal_wr_ack  <= #`TCQ 1'b1;\n     else\n       ideal_wr_ack  <= #`TCQ 1'b0;\n    end\n\n   //-----------------------------------------------------------------------------\n   // Generate VALID flag\n   //-----------------------------------------------------------------------------\n   always @(posedge CLK or posedge rst_i) begin\n     if (rst_i)\n       ideal_valid  <= 1'b0;\n     else if (srst_rrst_busy)\n       ideal_valid  <= #`TCQ 1'b0;\n     else if (RD_EN & ~empty_i)\n       ideal_valid  <= #`TCQ 1'b1;\n     else\n       ideal_valid  <= #`TCQ 1'b0;\n    end\n\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_FULL flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss\n\n     wire                 fcomp2;\n     wire                 going_afull;\n     wire                 leaving_afull;\n     wire                 ram_afull_comb;\n\n\n   assign fcomp2         = (adj_rd_pntr_wr == (wr_pntr + 2'h2));\n\n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp\n     assign going_afull    = (fcomp2 & write_allow & ~read_allow);\n     assign leaving_afull  = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;\n    end endgenerate\n\n    // Write data width is bigger than read data width\n    // Write depth is smaller than read depth\n    // One write could be equal to 2 or 4 or 8 reads\n    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym\n      assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n      assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp \n      assign going_afull = (fcomp2 & write_allow & ~read_allow);\n      assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;\n    end endgenerate\n\n     assign ram_afull_comb  = going_afull | (~leaving_afull & almost_full_i);\n\n\n    generate if (C_HAS_RST == 1) begin : grst_afull\n      always @(posedge CLK or posedge RST_FULL_FF) begin\n        if (RST_FULL_FF & C_HAS_RST)\n          almost_full_i   <= C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_SRST == 1) begin : gsrst_afull\n      always @(posedge CLK) begin\n        if (srst_wrst_busy)\n          almost_full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;\n        else\n          almost_full_i   <= #`TCQ ram_afull_comb;\n       end\n    end endgenerate\n\n    generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_afull\n      always @(posedge CLK) begin\n          almost_full_i   <= #`TCQ ram_afull_comb;\n      end\n    end endgenerate\n\n   //-----------------------------------------------------------------------------\n   // Generate ALMOST_EMPTY flag\n   //-----------------------------------------------------------------------------\n   //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss\n\n     wire                 ecomp2;\n     wire                 going_aempty;\n     wire                 leaving_aempty;\n     wire                 ram_aempty_comb;\n      \n     assign ecomp2          = (adj_wr_pntr_rd == (rd_pntr + 2'h2));\n   \n    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp\n     assign going_aempty    = (ecomp2 & ~write_allow & read_allow);\n     assign leaving_aempty  = (ecomp1 & write_allow & ~read_allow);\n    end endgenerate\n\n    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp\n      assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n      assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n    end endgenerate\n  \n   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp \n      assign going_aempty = (ecomp2 & ~write_allow & read_allow);\n      assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);\n    end endgenerate\n\n\n     assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);\n\n     always @(posedge CLK or posedge rst_i) begin\n       if (rst_i)\n         almost_empty_i  <= 1'b1;\n       else if (srst_rrst_busy)\n         almost_empty_i  <= #`TCQ 1'b1;\n       else\n         almost_empty_i  <= #`TCQ ram_aempty_comb;\n      end\n  // end endgenerate // gae_ss\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL\n   //-----------------------------------------------------------------------------\n\n   localparam  C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT \n                                  C_PROG_FULL_THRESH_ASSERT_VAL; // STD\n   localparam  C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? \n                                  C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT\n                                  C_PROG_FULL_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;   \n   generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin \n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n          prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr>= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  ((diff_pntr) < C_PF_ASSERT_VAL )\n        prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate // single_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n           prog_full_i <= #`TCQ 1'b1;\n         else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)\n           prog_full_i <= #`TCQ 1'b0;\n         else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~RST_FULL_GEN ) begin \n        if (diff_pntr >= C_PF_ASSERT_VAL )\n          prog_full_i <= #`TCQ 1'b1;\n       else if  (diff_pntr < C_PF_NEGATE_VAL)\n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n      end\n     end\n   end endgenerate //multiple_pf_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT\n                                               PROG_FULL_THRESH; // STD\n   generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input\n\n     always @(posedge CLK or posedge RST_FULL_FF) begin//0\n       //if (RST_FULL_FF)\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin //1\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin//2 \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin//3\n           if (diff_pntr > pf3_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if (diff_pntr == pf3_assert_val) begin//4\n             if (read_only_q)\n               prog_full_i <= #`TCQ 1'b0;\n             else\n               prog_full_i <= #`TCQ 1'b1;\n           end else//4\n             prog_full_i <= #`TCQ 1'b0;\n         end else//3\n           prog_full_i <= #`TCQ prog_full_i;\n       end //2\n       else begin//5\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin//6 \n        if (diff_pntr >= pf3_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n        else if  (diff_pntr < pf3_assert_val) begin//7\n         prog_full_i <= #`TCQ 1'b0;\n       end//7\n       end//6\n      else\n           prog_full_i <= #`TCQ prog_full_i;\n       end//5\n     end//1\n     end//0\n   end endgenerate //single_pf_input\n  \n   //-----------------------------------------------------------------------------\n   // Generate PROG_FULL for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_ASSERT; // STD\n   wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? \n                                               (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT\n                                               PROG_FULL_THRESH_NEGATE; // STD\n\n   generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs\n     always @(posedge CLK or posedge RST_FULL_FF) begin\n       if (RST_FULL_FF && C_HAS_RST)\n         prog_full_i   <= C_FULL_FLAGS_RST_VAL;\n       else begin\n         if (srst_wrst_busy)\n           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n       else if (IS_ASYMMETRY == 0) begin \n         if (RST_FULL_GEN)\n           prog_full_i <= #`TCQ 1'b0;\n         else if (~almost_full_i) begin\n           if (diff_pntr >= pf_assert_val)\n             prog_full_i <= #`TCQ 1'b1;\n           else if ((diff_pntr == pf_negate_val && read_only_q) ||\n                  diff_pntr < pf_negate_val)\n             prog_full_i <= #`TCQ 1'b0;\n           else\n             prog_full_i <= #`TCQ prog_full_i;\n         end else\n           prog_full_i <= #`TCQ prog_full_i;\n       end\n       else begin\n       if (RST_FULL_GEN)\n        prog_full_i <= #`TCQ 1'b0;\n       else if (~full_i ) begin \n        if (diff_pntr >= pf_assert_val )\n          prog_full_i <= #`TCQ 1'b1;\n       else if (diff_pntr < pf_negate_val) \n         prog_full_i <= #`TCQ 1'b0;\n       else\n         prog_full_i <= #`TCQ prog_full_i;\n        end \n       else\n         prog_full_i <= #`TCQ prog_full_i;\n       end\n\n     end\n   end\n   end endgenerate //multiple_pf_inputs\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY\n   //-----------------------------------------------------------------------------\n   localparam  C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD\n   localparam  C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT\n                                  C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold constant\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i) \n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy) \n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL)\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > C_PE_ASSERT_VAL)\n         prog_empty_i <= #`TCQ 1'b0;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n     end\n     end\n   end endgenerate // single_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold constants\n   //-----------------------------------------------------------------------------\n   generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n           prog_empty_i <= #`TCQ 1'b1;\n         else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)\n           prog_empty_i <= #`TCQ 1'b0;\n         else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n       if (~rst_i ) begin \n        if (diff_pntr_pe <= C_PE_ASSERT_VAL )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > C_PE_NEGATE_VAL) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n       end\n\n     end\n\n     end\n   end endgenerate //multiple_pe_const\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for single programmable threshold input port\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH -2) : // FWFT\n                                                PROG_EMPTY_THRESH; // STD\n   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n       else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe < pe3_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (diff_pntr_pe == pe3_assert_val) begin\n             if (write_only_q)\n               prog_empty_i <= #`TCQ 1'b0;\n             else\n               prog_empty_i <= #`TCQ 1'b1;\n           end else\n             prog_empty_i <= #`TCQ 1'b0;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe3_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if  (diff_pntr_pe > pe3_assert_val)\n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n\n     end\n   end endgenerate // single_pe_input\n\n   //-----------------------------------------------------------------------------\n   // Generate PROG_EMPTY for multiple programmable threshold input ports\n   //-----------------------------------------------------------------------------\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_ASSERT; // STD\n   wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?\n                                               (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT\n                                                PROG_EMPTY_THRESH_NEGATE; // STD\n   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs\n     always @(posedge CLK or posedge rst_i) begin\n       //if (rst_i)\n       if (rst_i && C_HAS_RST) \n         prog_empty_i  <= 1'b1;\n       else begin\n         if (srst_rrst_busy)\n           prog_empty_i <= #`TCQ 1'b1;\n      else if (IS_ASYMMETRY == 0) begin \n          if (~almost_full_i) begin\n           if (diff_pntr_pe <= pe4_assert_val)\n             prog_empty_i <= #`TCQ 1'b1;\n           else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || \n                     (diff_pntr_pe > pe4_negate_val)) begin\n             prog_empty_i <= #`TCQ 1'b0;\n           end else\n             prog_empty_i <= #`TCQ prog_empty_i;\n         end else\n           prog_empty_i <= #`TCQ prog_empty_i;\n       end\n       else begin\n        if (diff_pntr_pe <= pe4_assert_val )\n          prog_empty_i <= #`TCQ 1'b1;\n        else if (diff_pntr_pe > pe4_negate_val) \n         prog_empty_i <= #`TCQ 1'b0;\n       else\n         prog_empty_i <= #`TCQ prog_empty_i;\n        end \n     end\n     end\n   end endgenerate // multiple_pe_inputs\n\nendmodule // fifo_generator_v13_2_1_bhv_ver_ss\n\n\n\n/**************************************************************************\n * First-Word Fall-Through module (preload 0)\n **************************************************************************/\nmodule fifo_generator_v13_2_1_bhv_ver_preload0\n  #(\n    parameter  C_DOUT_RST_VAL            = \"\",\n    parameter  C_DOUT_WIDTH              = 8,\n    parameter  C_HAS_RST                 = 0,\n    parameter  C_ENABLE_RST_SYNC         = 0,\n    parameter  C_HAS_SRST                = 0,\n    parameter  C_USE_EMBEDDED_REG        = 0,\n    parameter  C_EN_SAFETY_CKT           = 0, \n    parameter  C_USE_DOUT_RST            = 0,\n    parameter  C_USE_ECC                 = 0,\n    parameter  C_USERVALID_LOW           = 0,\n    parameter  C_USERUNDERFLOW_LOW       = 0,\n    parameter  C_MEMORY_TYPE             = 0,\n    parameter  C_FIFO_TYPE               = 0\n  )\n  (\n    //Inputs\n    input                          SAFETY_CKT_RD_RST,\n    input                          RD_CLK,\n    input                          RD_RST,\n    input                          SRST,\n    input                          WR_RST_BUSY,\n    input                          RD_RST_BUSY,\n    input                          RD_EN,\n    input                          FIFOEMPTY,\n    input       [C_DOUT_WIDTH-1:0] FIFODATA,\n    input                          FIFOSBITERR,\n    input                          FIFODBITERR,\n   \n    //Outputs\n    output reg  [C_DOUT_WIDTH-1:0] USERDATA,\n    output                         USERVALID,\n    output                         USERUNDERFLOW,\n    output                         USEREMPTY,\n    output                         USERALMOSTEMPTY,\n    output                         RAMVALID,\n    output                         FIFORDEN,\n    output reg                     USERSBITERR,\n    output reg                     USERDBITERR,\n    output reg                     STAGE2_REG_EN,\n    output                         fab_read_data_valid_i_o,\n    output                         read_data_valid_i_o,\n    output                         ram_valid_i_o,\n    output      [1:0]              VALID_STAGES \n  );\n //Internal signals\n wire                      preloadstage1;\n wire                      preloadstage2;\n reg                       ram_valid_i;\n reg                       fab_valid;\n reg                       read_data_valid_i;\n reg                       fab_read_data_valid_i;\n reg                       fab_read_data_valid_i_1;\n reg                       ram_valid_i_d;\n reg                       read_data_valid_i_d;\n reg                       fab_read_data_valid_i_d;\n wire                      ram_regout_en;\n reg                       ram_regout_en_d1;\n reg                       ram_regout_en_d2;\n wire                      fab_regout_en;\n wire                      ram_rd_en;\n reg                       empty_i        = 1'b1;\n reg                       empty_sckt     = 1'b1;\n reg                       sckt_rrst_q    = 1'b0;\n reg                       sckt_rrst_done = 1'b0;\n reg                       empty_q        = 1'b1;\n reg                       rd_en_q        = 1'b0;\n reg                       almost_empty_i = 1'b1;\n reg                       almost_empty_q = 1'b1;\n wire                      rd_rst_i;\n wire                      srst_i;\n reg  [C_DOUT_WIDTH-1:0]   userdata_both;\n wire                      uservalid_both;\n wire                      uservalid_one;\n reg                       user_sbiterr_both = 1'b0;\n reg                       user_dbiterr_both = 1'b0;\n  \nassign ram_valid_i_o = ram_valid_i;\nassign read_data_valid_i_o = read_data_valid_i;\nassign fab_read_data_valid_i_o = fab_read_data_valid_i; \n\n\n\n/*************************************************************************\n* FUNCTIONS\n*************************************************************************/\n\n   /*************************************************************************\n    * hexstr_conv\n    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n    ***********************************************************************/\n    function [C_DOUT_WIDTH-1:0] hexstr_conv;\n    input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n    integer index,i,j;\n    reg [3:0] bin;\n\n    begin\n      index = 0;\n      hexstr_conv = 'b0;\n      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n      begin\n        case (def_data[7:0])\n          8'b00000000 :\n          begin\n            bin = 4'b0000;\n            i = -1;\n          end\n          8'b00110000 : bin = 4'b0000;\n          8'b00110001 : bin = 4'b0001;\n          8'b00110010 : bin = 4'b0010;\n          8'b00110011 : bin = 4'b0011;\n          8'b00110100 : bin = 4'b0100;\n          8'b00110101 : bin = 4'b0101;\n          8'b00110110 : bin = 4'b0110;\n          8'b00110111 : bin = 4'b0111;\n          8'b00111000 : bin = 4'b1000;\n          8'b00111001 : bin = 4'b1001;\n          8'b01000001 : bin = 4'b1010;\n          8'b01000010 : bin = 4'b1011;\n          8'b01000011 : bin = 4'b1100;\n          8'b01000100 : bin = 4'b1101;\n          8'b01000101 : bin = 4'b1110;\n          8'b01000110 : bin = 4'b1111;\n          8'b01100001 : bin = 4'b1010;\n          8'b01100010 : bin = 4'b1011;\n          8'b01100011 : bin = 4'b1100;\n          8'b01100100 : bin = 4'b1101;\n          8'b01100101 : bin = 4'b1110;\n          8'b01100110 : bin = 4'b1111;\n          default :\n          begin\n            bin = 4'bx;\n          end\n        endcase\n        for( j=0; j<4; j=j+1)\n        begin\n          if ((index*4)+j < C_DOUT_WIDTH)\n          begin\n            hexstr_conv[(index*4)+j] = bin[j];\n          end\n        end\n        index = index + 1;\n        def_data = def_data >> 8;\n      end\n    end\n  endfunction\n\n   \n   //*************************************************************************\n   //  Set power-on states for regs\n   //*************************************************************************\n   initial begin\n      ram_valid_i       = 1'b0;\n      fab_valid         = 1'b0;\n      read_data_valid_i = 1'b0;\n      fab_read_data_valid_i = 1'b0;\n      fab_read_data_valid_i_1 = 1'b0;\n      USERDATA          = hexstr_conv(C_DOUT_RST_VAL);\n      userdata_both          = hexstr_conv(C_DOUT_RST_VAL);\n      USERSBITERR       = 1'b0;\n      USERDBITERR       = 1'b0;\n      user_sbiterr_both = 1'b0;\n      user_dbiterr_both = 1'b0;\n   end //initial\n\n   //***************************************************************************\n   //  connect up optional reset\n   //***************************************************************************\n   assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;\n   assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;\n\n   reg  sckt_rd_rst_fwft = 1'b0;\n   reg  fwft_rst_done_i  = 1'b0;\n   wire fwft_rst_done;\n   assign fwft_rst_done = 1'b1;//C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;\n   always @ (posedge RD_CLK) begin\n     sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;\n   end\n\n   always @ (posedge rd_rst_i or posedge RD_CLK) begin\n     if (rd_rst_i)\n       fwft_rst_done_i  <= 1'b0;\n     else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)\n       fwft_rst_done_i  <= #`TCQ 1'b1;\n   end\n\n   localparam INVALID             = 0;\n   localparam STAGE1_VALID        = 2;\n   localparam STAGE2_VALID        = 1;\n   localparam BOTH_STAGES_VALID   = 3;\n\n   reg  [1:0] curr_fwft_state = INVALID;\n   reg  [1:0] next_fwft_state = INVALID;\n\n\ngenerate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin\n         always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n \n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n     \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n    \n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = preloadstage2;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;\n   end\nendgenerate // gnll_fifo\n\n   reg curr_state         = 0;\n   reg next_state         = 0;\n   reg leaving_empty_fwft = 0;\n   reg going_empty_fwft   = 0;\n   reg empty_i_q          = 0;\n   reg ram_rd_en_fwft     = 0;\n   generate if (C_FIFO_TYPE == 2) begin : gll_fifo\n     always @* begin // FSM fo FWFT\n       case (curr_state)\n         1'b0: begin\n           if (~FIFOEMPTY)\n             next_state <= 1'b1;\n           else\n             next_state <= 1'b0;\n           end\n         1'b1: begin\n           if (FIFOEMPTY && RD_EN)\n             next_state <= 1'b0;\n           else\n             next_state <= 1'b1;\n           end\n         default: next_state <= 1'b0;\n       endcase\n     end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_i       <= 1'b1;\n           empty_i_q     <= 1'b1;\n           ram_valid_i   <= 1'b0;\n        end else if (srst_i) begin\n           empty_i       <= #`TCQ 1'b1;\n           empty_i_q     <= #`TCQ 1'b1;\n           ram_valid_i   <= #`TCQ 1'b0;\n        end else begin\n           empty_i       <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);\n           empty_i_q     <= #`TCQ FIFOEMPTY;\n           ram_valid_i   <= #`TCQ next_state;\n        end\n     end //always\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n           curr_state    <= 1'b0;\n        end else if (srst_i) begin\n           curr_state    <= #`TCQ 1'b0;\n        end else begin\n           curr_state    <= #`TCQ next_state;\n        end\n     end //always\n\n     wire                  fe_of_empty; \n     assign fe_of_empty   = empty_i_q & ~FIFOEMPTY;\n\n     always @* begin // Finding leaving empty\n       case (curr_state)\n         1'b0:    leaving_empty_fwft <= fe_of_empty;\n         1'b1:    leaving_empty_fwft <= 1'b1;\n         default: leaving_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Finding going empty\n       case (curr_state)\n         1'b1:    going_empty_fwft <= FIFOEMPTY & RD_EN;\n         default: going_empty_fwft <= 1'b0;\n       endcase\n     end\n\n     always @* begin // Generating FWFT rd_en\n       case (curr_state)\n         1'b0:    ram_rd_en_fwft <= ~FIFOEMPTY;\n         1'b1:    ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;\n         default: ram_rd_en_fwft <= 1'b0;\n       endcase\n     end\n\n     assign ram_regout_en = ram_rd_en_fwft;\n     //assign ram_regout_en_d1 = ram_rd_en_fwft;\n     //assign ram_regout_en_d2 = ram_rd_en_fwft;\n     assign ram_rd_en     = ram_rd_en_fwft;\n   end endgenerate // gll_fifo\n\n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false.\n   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n   generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           ram_valid_i     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              ram_valid_i     <= #`TCQ 1'b0;\n           end else begin\n              if (ram_rd_en == 1'b1) begin\n                 ram_valid_i   <= #`TCQ 1'b1;\n              end else begin\n                 if (ram_regout_en == 1'b1)\n                   ram_valid_i <= #`TCQ 1'b0;\n                 else\n                   ram_valid_i <= #`TCQ ram_valid_i;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_ram_valid\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n  \n generate if(C_USE_EMBEDDED_REG < 3) begin\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else\n        read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);\n   end //always\nend \nendgenerate\n\n   \n   \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n generate if ( C_USE_EMBEDDED_REG < 3) begin\n  always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin         // asynchronous reset (active high)\n             almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ FIFOEMPTY;\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n   \n   \n     \n  // BRAM resets synchronously\n generate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin\n   always @ ( posedge rd_rst_i)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n           @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n             USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end  else if (fwft_rst_done) begin\n            if (ram_regout_en) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end\n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n//safety ckt with one register\ngenerate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK)\n          begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n          end\n        always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n            @(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n        end\n     end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n          //@(posedge RD_CLK)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end \n       end\n        else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1) begin\n            //  @(posedge RD_CLK)\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n          end\n          end else if (fwft_rst_done) begin\n            if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n               USERDATA     <= #`TCQ FIFODATA;\n               USERSBITERR  <= #`TCQ FIFOSBITERR;\n               USERDBITERR  <= #`TCQ FIFODBITERR;\n            end          \n          end\n        end\n       end //always\n  end //if\nendgenerate\n\n\ngenerate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin\n         \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID: begin\n               if (~FIFOEMPTY)\n                  next_fwft_state     <= STAGE1_VALID;\n               else\n                  next_fwft_state     <= INVALID;\n               end\n            STAGE1_VALID: begin\n               if (FIFOEMPTY)\n                  next_fwft_state     <= STAGE2_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            STAGE2_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= INVALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE1_VALID;\n               else if (~FIFOEMPTY && ~RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= STAGE2_VALID;\n               end\n            BOTH_STAGES_VALID: begin\n               if (FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= STAGE2_VALID;\n               else if (~FIFOEMPTY && RD_EN)\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               else\n                  next_fwft_state     <= BOTH_STAGES_VALID;\n               end\n            default: next_fwft_state     <= INVALID;\n         endcase\n      end\n\n      always @ (posedge rd_rst_i or posedge RD_CLK) begin\n         if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n            curr_fwft_state  <= INVALID;\n         else if (srst_i)\n            curr_fwft_state  <= #`TCQ INVALID;\n         else\n            curr_fwft_state  <= #`TCQ next_fwft_state;\n      end\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d1 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d1 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d1 <= #`TCQ ram_regout_en;\n                 end\n            end //always\n   //  assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));\n       assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1\n            if (rd_rst_i == 1) begin\n                ram_regout_en_d2 <= #`TCQ 1'b0;\n            end\n            else begin\n                 if (srst_i == 1'b1) \n                 ram_regout_en_d2 <= #`TCQ 1'b0;\n                 else\n                 ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;\n                 end\n            end //always\n\n    \n\n      always @* begin\n         case (curr_fwft_state)\n            INVALID:           STAGE2_REG_EN <= 1'b0;\n            STAGE1_VALID:      STAGE2_REG_EN <= 1'b1;\n            STAGE2_VALID:      STAGE2_REG_EN <= 1'b0;\n            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n            default:           STAGE2_REG_EN <= 1'b0;\n         endcase\n      end\n\n     always @ (posedge RD_CLK) begin\n        ram_valid_i_d <= #`TCQ ram_valid_i;\n        read_data_valid_i_d <= #`TCQ read_data_valid_i;\n        fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;\n\n     end\n    assign VALID_STAGES = curr_fwft_state;\n\n     //***************************************************************************\n     //  preloadstage2 indicates that stage2 needs to be updated. This is true\n     //  whenever read_data_valid is false, and RAM_valid is true.\n     //***************************************************************************\n    \n     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n\n     //***************************************************************************\n     //  preloadstage1 indicates that stage1 needs to be updated. This is true\n     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n     //  false (indicating that Stage1 needs updating), or preloadstage2 is active\n     //  (indicating that Stage2 is going to update, so Stage1, therefore, must\n     //  also be updated to keep it valid.\n     //***************************************************************************\n     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n  \n     //***************************************************************************\n     // Calculate RAM_REGOUT_EN\n     //  The output registers are controlled by the ram_regout_en signal.\n     //  These registers should be updated either when the output in Stage2 is\n     //  invalid (preloadstage2), OR when the user is reading, in which case the\n     //  Stage2 value will go invalid unless it is replenished.\n     //***************************************************************************\n     assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n     //***************************************************************************\n     // Calculate RAM_RD_EN\n     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n     //  update the value in Stage1.\n     //   One case when this happens is when preloadstage1=true, which indicates\n     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically\n     //  be updated.\n     //   The other case is when the user is reading from the FIFO, which \n     // guarantees that Stage1 or Stage2 will be invalid on the next clock \n     // cycle, unless it is replinished by data from the memory. So, as long \n     // as the RAM has data in it, a read of the RAM should occur.\n     //***************************************************************************\n     assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;\n   end\n   endgenerate // gnll_fifo\n\n   \n\n   //***************************************************************************\n   // Calculate RAMVALID_P0_OUT\n   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n   //\n   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n   //   RAMVALID_P0_OUT is certainly going to be true.\n   //   If the RAM is not being read from, but the output registers are being\n   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n   //   therefore causing RAMVALID_P0_OUT to be false   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.\n   //***************************************************************************\n   // PROCESS regout_valid\n     generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid\n\n     \n     always @ (posedge RD_CLK or posedge rd_rst_i) begin  \n        if (rd_rst_i) begin \n           // asynchronous reset (active high)\n           fab_valid     <= #`TCQ 1'b0;\n        end else begin\n           if (srst_i) begin \n              // synchronous reset (active high)\n              fab_valid    <= #`TCQ 1'b0;\n           end else begin\n              if (ram_regout_en == 1'b1) begin\n                 fab_valid  <= #`TCQ 1'b1;\n              end else begin\n                 if (fab_regout_en == 1'b1)\n                   fab_valid <= #`TCQ 1'b0;\n                 else\n                   fab_valid <= #`TCQ fab_valid;\n              end\n           end //srst_i\n        end //rd_rst_i\n     end //always\n   end endgenerate // gnll_fifo_fab_valid\n\n   \n   //***************************************************************************\n   // Calculate READ_DATA_VALID\n   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n   //  Stage2 has valid data whenever Stage1 had valid data and \n   //  ram_regout_en_i=1, such that the data in Stage1 is propogated \n   //  into Stage2.\n   //***************************************************************************\n    generate if(C_USE_EMBEDDED_REG == 3) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n      if (rd_rst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        read_data_valid_i <= #`TCQ 1'b0;\n      else begin\n        if (ram_regout_en == 1'b1) begin\n          read_data_valid_i <= #`TCQ 1'b1;\n        end else begin\n         if (fab_regout_en == 1'b1)\n          read_data_valid_i <= #`TCQ 1'b0;\n        else\n          read_data_valid_i <= #`TCQ read_data_valid_i;\n        end \n      end \n   end //always\nend\nendgenerate\n\n//generate if(C_USE_EMBEDDED_REG == 3) begin\n//   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n//      if (rd_rst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//      else if (srst_i)\n//        read_data_valid_i <= #`TCQ 1'b0;\n//\n//      if (ram_regout_en == 1'b1) begin\n//        fab_read_data_valid_i <= #`TCQ 1'b0;\n//      end else begin\n//       if (fab_regout_en == 1'b1)\n//        fab_read_data_valid_i <= #`TCQ 1'b1;\n//      else\n//        fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;\n//      end \n//   end //always\n//end\n//endgenerate\n\n     generate if(C_USE_EMBEDDED_REG == 3 ) begin \n    always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid\n      if (rd_rst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else if (srst_i)\n        fab_read_data_valid_i <= #`TCQ 1'b0;\n      else \n        fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);\n   end //always\nend\nendgenerate\n \nalways @ (posedge RD_CLK ) begin : proc_del1\n             begin\n                 fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;\n              end\n            end //always\n \n \n   //**************************************************************************\n   // Calculate EMPTY\n   //  Defined as the inverse of READ_DATA_VALID\n   //\n   // Description:\n   //\n   //  If read_data_valid_i indicates that the output is not valid,\n   // and there is no valid data on the output of the ram to preload it\n   // with, then we will report empty.\n   //\n   //  If there is no valid data on the output of the ram and we are\n   // reading, then the FIFO will go empty.\n   //\n   //**************************************************************************\n   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           // asynchronous reset (active high)\n           empty_i <= #`TCQ 1'b1;\n        end else begin\n           if (srst_i) begin\n              // synchronous reset (active high)\n              empty_i <= #`TCQ 1'b1;\n           end else begin\n              // rising clock edge\n              empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);\n           end\n        end\n     end //always\n   end endgenerate // gnll_fifo_empty_both\n   \n   // Register RD_EN from user to calculate USERUNDERFLOW.\n   // Register empty_i to calculate USERUNDERFLOW.\n   always @ (posedge RD_CLK) begin\n     rd_en_q <= #`TCQ RD_EN;\n     empty_q <= #`TCQ empty_i;\n   end //always\n   \n   \n   //***************************************************************************\n   // Calculate user_almost_empty\n   //  user_almost_empty is defined such that, unless more words are written\n   //  to the FIFO, the next read will cause the FIFO to go EMPTY.\n   //\n   //  In most cases, whenever the output registers are updated (due to a user\n   // read or a preload condition), then user_almost_empty will update to\n   // whatever RAM_EMPTY is.\n   //\n   //  The exception is when the output is valid, the user is not reading, and\n   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n   // memory, so we need to make sure user_almost_empty deasserts properly under\n   // this condition.\n   //***************************************************************************\n   reg FIFOEMPTY_1;\n   generate if (C_USE_EMBEDDED_REG == 3 ) begin\n    always @(posedge RD_CLK) begin\n            FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;\n           end\n    end\nendgenerate\n    generate if (C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK or posedge rd_rst_i)\n   begin\n      if (rd_rst_i) begin         // asynchronous reset (active high)\n           almost_empty_i <= #`TCQ 1'b1;\n             almost_empty_q <= #`TCQ 1'b1;\n        end else begin // rising clock edge\n           if (srst_i) begin          // synchronous reset (active high)\n              almost_empty_i <= #`TCQ 1'b1;\n              almost_empty_q <= #`TCQ 1'b1;\n           end else begin\n              if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin\n                 almost_empty_i <= #`TCQ (~ram_valid_i);\n              end\n              almost_empty_q   <= #`TCQ empty_i;\n           end\n        end\n     end //always\nend\nendgenerate\n     always @ (posedge RD_CLK or posedge rd_rst_i) begin\n        if (rd_rst_i) begin\n           empty_sckt <= #`TCQ 1'b1;\n           sckt_rrst_q <= #`TCQ 1'b0;\n           sckt_rrst_done <= #`TCQ 1'b0;\n        end else begin\n           sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;\n           if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin\n              sckt_rrst_done <= #`TCQ 1'b1;\n           end else if (sckt_rrst_done) begin\n              // rising clock edge\n              empty_sckt <= #`TCQ 1'b0;\n           end\n        end\n     end //always\n   \n   \n//   assign USEREMPTY       = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;\n   assign USEREMPTY       = empty_i;\n   assign USERALMOSTEMPTY = almost_empty_i;\n   assign FIFORDEN        = ram_rd_en;\n   assign RAMVALID        = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;\n   assign uservalid_both       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3)  ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);\n   assign uservalid_one       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3)  ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);\n   assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;\n   assign USERUNDERFLOW   = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;\n//no safety ckt with both reg\ngenerate \n        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin\n   always @ (posedge RD_CLK)\n     begin\n        if (rd_rst_i || srst_i) begin\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n            USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n     end //always\n\n \n   always @ (posedge RD_CLK or posedge rd_rst_i)\n     begin\n        if (rd_rst_i) begin //asynchronous reset (active high)\n          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n            USERSBITERR    <= #`TCQ 0;\n            USERDBITERR    <= #`TCQ 0;\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n          end\n          // DRAM resets asynchronously\n          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)\n            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n            user_sbiterr_both <= #`TCQ 0;\n            user_dbiterr_both <= #`TCQ 0;\n        end\n        end  else begin // rising clock edge\n          if (srst_i) begin\n            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n              USERSBITERR  <= #`TCQ 0;\n              USERDBITERR  <= #`TCQ 0;\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              userdata_both   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end else begin\n            if (fwft_rst_done) begin\n              if (ram_regout_en) begin\n                 userdata_both     <= #`TCQ FIFODATA; \n                 user_dbiterr_both <= #`TCQ FIFODBITERR;\n                 user_sbiterr_both <= #`TCQ FIFOSBITERR; \n              end\n              if (fab_regout_en) begin\n                 USERDATA     <= #`TCQ userdata_both;\n                 USERDBITERR  <= #`TCQ user_dbiterr_both;\n                 USERSBITERR  <= #`TCQ user_sbiterr_both; \n              end             \n            end             \n          end\n        end\n     end //always\n   end   //if\n  endgenerate\n\n//safety_ckt with both registers\n generate\n       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;\n         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;\n         reg [1:0] rst_delayed_sft1              =1;\n         reg [1:0] rst_delayed_sft2              =1;\n         reg [1:0] rst_delayed_sft3              =1;\n         reg [1:0] rst_delayed_sft4              =1;\n         \n        always@(posedge RD_CLK) begin\n          rst_delayed_sft1 <= #`TCQ rd_rst_i;\n          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n        end\n        always @ (posedge RD_CLK) begin\n          if (rd_rst_i || srst_i) begin\n            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n              @(posedge RD_CLK)\n              USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n               userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n              user_sbiterr_both <= #`TCQ 0;\n              user_dbiterr_both <= #`TCQ 0;\n            end\n          end\n        end //always\n \n   always @ (posedge RD_CLK or posedge rd_rst_i) begin\n     if (rd_rst_i) begin //asynchronous reset (active high)\n       if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n         USERSBITERR       <= #`TCQ 0;\n         USERDBITERR       <= #`TCQ 0;\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end\n       // DRAM resets asynchronously\n       if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)\n         USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         user_sbiterr_both <= #`TCQ 0;\n         user_dbiterr_both <= #`TCQ 0;\n       end \n     end else begin // rising clock edge\n       if (srst_i) begin\n         if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n           USERSBITERR       <= #`TCQ 0;\n           USERDBITERR       <= #`TCQ 0;\n           user_sbiterr_both <= #`TCQ 0;\n           user_dbiterr_both <= #`TCQ 0;\n         end\n         if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n           USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n         end\n       end else if (fwft_rst_done) begin\n         if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            userdata_both     <= #`TCQ FIFODATA;\n            user_dbiterr_both <= #`TCQ FIFODBITERR;\n            user_sbiterr_both <= #`TCQ FIFOSBITERR; \n         end\n         if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n            USERDATA          <= #`TCQ userdata_both;\n            USERDBITERR       <= #`TCQ user_dbiterr_both;\n            USERSBITERR       <= #`TCQ user_sbiterr_both;\n         end\n       end\n     end\n   end //always\n  end //if\nendgenerate\n\nendmodule //fifo_generator_v13_2_1_bhv_ver_preload0\n\n\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n//   Register one AXI channel on forward and/or reverse signal path\n//\n// Verilog-standard:  Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n//   reg_slice\n//\n//--------------------------------------------------------------------------\n\nmodule fifo_generator_v13_2_1_axic_reg_slice #\n  (\n   parameter C_FAMILY     = \"virtex7\",\n   parameter C_DATA_WIDTH = 32,\n   parameter C_REG_CONFIG = 32'h00000000\n   )\n  (\n   // System Signals\n   input  wire                      ACLK,\n   input  wire                      ARESET,\n\n   // Slave side\n   input  wire [C_DATA_WIDTH-1:0]   S_PAYLOAD_DATA,\n   input  wire                      S_VALID,\n   output wire                      S_READY,\n\n   // Master side\n   output wire [C_DATA_WIDTH-1:0]   M_PAYLOAD_DATA,\n   output wire                      M_VALID,\n   input  wire                      M_READY\n   );\n\n  localparam RST_SYNC_STAGES = 5;\n  localparam RST_BUSY_LEN    = 6;\n  reg [1:0] arst_sync_wr  = 2'b11;\n  reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;\n  wire sync_reset;\n  wire extnd_reset;\n\n\n  always @(posedge ARESET or posedge ACLK) begin\n    if (ARESET)\n      arst_sync_wr <= 2'b11;\n    else\n      arst_sync_wr <= #`TCQ {arst_sync_wr[0], 1'b0};\n  end\n\n  always @(posedge ACLK) begin\n    sckt_wr_rst_cc   <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[1]};\n  end\n\n  assign sync_reset     = |sckt_wr_rst_cc[RST_BUSY_LEN-5:0] | arst_sync_wr[1]; \n  assign extnd_reset    = |sckt_wr_rst_cc | arst_sync_wr[1];\n  generate\n  ////////////////////////////////////////////////////////////////////\n  //\n  // Both FWD and REV mode\n  //\n  ////////////////////////////////////////////////////////////////////\n    if (C_REG_CONFIG == 32'h00000000)\n    begin\n      reg [1:0] state;\n      localparam [1:0] \n        ZERO = 2'b10,\n        ONE  = 2'b11,\n        TWO  = 2'b01;\n      \n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg [C_DATA_WIDTH-1:0] storage_data2 = 0;\n      reg                    load_s1;\n      wire                   load_s2;\n      wire                   load_s1_from_s2;\n      reg                    s_ready_i; //local signal of output\n      wire                   m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with either slave side data or from storage2\n      always @(posedge ACLK) \n      begin\n        if (load_s1)\n          if (load_s1_from_s2)\n            storage_data1 <= storage_data2;\n          else\n            storage_data1 <= S_PAYLOAD_DATA;        \n      end\n\n      // Load storage2 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (load_s2)\n          storage_data2 <= S_PAYLOAD_DATA;\n      end\n\n      assign M_PAYLOAD_DATA = storage_data1;\n\n      // Always load s2 on a valid transaction even if it's unnecessary\n      assign load_s2 = S_VALID & s_ready_i;\n\n      // Loading s1\n      always @ *\n      begin\n        if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction\n             // Load when ONE if we both have read and write at the same time\n             ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||\n             // Load when TWO and we have a transaction on Master side\n             ((state == TWO) && (M_READY == 1)))\n          load_s1 = 1'b1;\n        else\n          load_s1 = 1'b0;\n      end // always @ *\n\n      assign load_s1_from_s2 = (state == TWO);\n                       \n      // State Machine for handling output signals\n      always @(posedge ACLK) begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          state <= ZERO;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else begin\n          case (state)\n            // No transaction stored locally\n            ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE\n\n            // One transaction stored locally\n            ONE: begin\n              if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO\n              if (~M_READY & S_VALID) begin\n                state <= TWO;  // Got another one so move to TWO\n                s_ready_i <= 1'b0;\n              end\n            end\n\n            // TWO transaction stored locally\n            TWO: if (M_READY) begin\n              state <= ONE; // Read out one so move to ONE\n              s_ready_i <= 1'b1;\n            end\n          endcase // case (state)\n        end\n      end // always @ (posedge ACLK)\n      \n      assign m_valid_i = state[0];\n\n    end // if (C_REG_CONFIG == 1)\n  ////////////////////////////////////////////////////////////////////\n  //\n  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n  // Operates same as 1-deep FIFO\n  //\n  ////////////////////////////////////////////////////////////////////\n    else if (C_REG_CONFIG == 32'h00000001)\n    begin\n      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n      reg                    s_ready_i; //local signal of output\n      reg                    m_valid_i; //local signal of output\n\n      // assign local signal to its output signal\n      assign S_READY = s_ready_i;\n      assign M_VALID = m_valid_i;\n\n      reg  areset_d1; // Reset delay register\n      always @(posedge ACLK) begin\n        areset_d1 <= extnd_reset;\n      end\n      \n      // Load storage1 with slave side data\n      always @(posedge ACLK) \n      begin\n        if (sync_reset || extnd_reset) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b0;\n        end else if (areset_d1 && ~extnd_reset) begin\n          s_ready_i <= 1'b1;\n        end else if (m_valid_i & M_READY) begin\n          s_ready_i <= 1'b1;\n          m_valid_i <= 1'b0;\n        end else if (S_VALID & s_ready_i) begin\n          s_ready_i <= 1'b0;\n          m_valid_i <= 1'b1;\n        end\n        if (~m_valid_i) begin\n          storage_data1 <= S_PAYLOAD_DATA;        \n        end\n      end\n      assign M_PAYLOAD_DATA = storage_data1;\n    end // if (C_REG_CONFIG == 7)\n    \n    else begin : default_case\n      // Passthrough\n      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n      assign M_VALID        = S_VALID;\n      assign S_READY        = M_READY;      \n    end\n\n  endgenerate\nendmodule // reg_slice\n", "num_lines": 10519}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale  1 ps / 1 ps\n\nmodule glbl ();\n\n    parameter ROC_WIDTH = 100000;\n    parameter TOC_WIDTH = 0;\n    parameter GRES_WIDTH = 10000;\n    parameter GRES_START = 10000;\n\n//--------   STARTUP Globals --------------\n    wire GSR;\n    wire GTS;\n    wire GWE;\n    wire PRLD;\n    wire GRESTORE;\n    tri1 p_up_tmp;\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n    wire PROGB_GLBL;\n    wire CCLKO_GLBL;\n    wire FCSBO_GLBL;\n    wire [3:0] DO_GLBL;\n    wire [3:0] DI_GLBL;\n   \n    reg GSR_int;\n    reg GTS_int;\n    reg PRLD_int;\n    reg GRESTORE_int;\n\n//--------   JTAG Globals --------------\n    wire JTAG_TDO_GLBL;\n    wire JTAG_TCK_GLBL;\n    wire JTAG_TDI_GLBL;\n    wire JTAG_TMS_GLBL;\n    wire JTAG_TRST_GLBL;\n\n    reg JTAG_CAPTURE_GLBL;\n    reg JTAG_RESET_GLBL;\n    reg JTAG_SHIFT_GLBL;\n    reg JTAG_UPDATE_GLBL;\n    reg JTAG_RUNTEST_GLBL;\n\n    reg JTAG_SEL1_GLBL = 0;\n    reg JTAG_SEL2_GLBL = 0 ;\n    reg JTAG_SEL3_GLBL = 0;\n    reg JTAG_SEL4_GLBL = 0;\n\n    reg JTAG_USER_TDO1_GLBL = 1'bz;\n    reg JTAG_USER_TDO2_GLBL = 1'bz;\n    reg JTAG_USER_TDO3_GLBL = 1'bz;\n    reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n    assign (strong1, weak0) GSR = GSR_int;\n    assign (strong1, weak0) GTS = GTS_int;\n    assign (weak1, weak0) PRLD = PRLD_int;\n    assign (strong1, weak0) GRESTORE = GRESTORE_int;\n\n    initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n    end\n\n    initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n    end\n\n    initial begin \n\tGRESTORE_int = 1'b0;\n\t#(GRES_START);\n\tGRESTORE_int = 1'b1;\n\t#(GRES_WIDTH);\n\tGRESTORE_int = 1'b0;\n    end\n\nendmodule\n`endif\n", "num_lines": 85}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// Amazon FPGA Hardware Development Kit\n//\n// Copyright Amazon.com, Inc. or its affiliates. All Rights Reserved.\n// SPDX-License-Identifier: Apache-2.0\n`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nuVw5JhLL11X7sFlU0pAE+ly6TbXZG7ItJn3Ex9cXjSY7p1sc5OM17XcDMDqOEbaLgeEhUuwbGf++\nsY41qYpCyxKVTUSlo4RbifB6OdtPL5WbplRlVmZr6tVckowDKyf+KTfQD5yDuN/lqu/csQO2OWFG\n+FTZmZC2+4QJQc3yS24aV3ap6SiICL9zEXwFqFiBkzn/JHjRL0ul0SX2IlY2DGLf1ZP0frmZpeV5\njf+hw24P7s4xKjAFgaTp3id7hTx/VMEsA2ezH0GQbEMKybRgNRwMm93ZH7rKsmeh+vLM4uzdiiPH\nviyKgiHJcWlJF11UMelWbvVoYsF7uDJ90n/5Ww==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\ns7Yn4DABLzF4SLp/0V98P0CDCkZYnP8iqDei0IedIEX1lGPO+wDX247jQ5AIWSMu+s+1jQIMeWFm\nwwhaOWGt3o1acmXqPnf1xmu+ASh0sjaaro7Te7bhxTdbst8KbfW4m1RJX+UShZxi74/veNFylojR\nHiUek/GVQNWaepFc9Xo=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nSulZTeegbwtiqqiy6RNAoCNHsjD2rBzbr8ndOVV7AUZ0X/egfC2PVGUQ2Zwy0uxx/G5Py0ihEuGz\nMBiYAP/4TcshTSjLEVglOzGlp6fbSx9KYr1eCu1tcnF84602dfHBQHUV4WrLSSNvwXOKp/AKyOG7\n1ALfiTkaDf2vG5TjkzI=\n\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nVeIIJaaPUtlfe1VvZdR/BjuSRIXs9q5wYiTwm+LKSUDNMtXCl0A6nj2xESHweWlx4Lsjnho6VXem\n7zwg08AWnw==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 7104)\n`pragma protect data_block\nwefYcOgqtn2tETmWi8Rbf/n6M5BAutN587juaTMCMKbYASYN238z7WFXImp+yjGBHm7wW2Qi2r+8\n4CRJlSWuxJt/0DjSKDEbzfKT3Ywf24s2HItiITNYHmiQcHbmwcaginWLJcD0kej9qvRWROT7Jdol\n6p1ceAC2CxqBZd8KtGKA1yOqZfjvM7YDupzNTlJ8EnI8spiXjcW/hk3QdzvAAT+3MvEBtuMYPwg9\n6lfyMWuzIMCb7mND59+z+A6Y9kmp4sJ1RgfrKaInNYqTVwGLVkKRUjCmdH7pptXLJFzQOfA5LFUW\nobrQsrQaXZr1Mz+i68t31XE12AhBmHbtN+SpVLApbX+A7sMdDFo2lpQqBa40lYnZyJF0g5cBx9eK\nu/YEW1iX6rq8HaTsVLk4BbMrZfJuq/ODD2Hp1/UIgsW2JSJqGaqwAQCFGNDS4mcRv8RLAnveqAZk\nQJ8psKOMHRMC4OGuZIkI4024u74khNdkgiCs1gth4R7narobPlg4Q1xuWpMbTFi7SaFjQWRMZYuD\nXCpsVXxX6vJGREZGrkT0uDJN8Q2kassteI7QYPLCqBCso1vuH8+WxUjwDI4MUv7K04VLAsg3wBK+\n0JIPZi/4FajT04MDy6kNpP+n0IuV23UORkPa5JOjr91sST7nORbqbnmCvN2fJXIJk7Fp9NQkdEwu\nxszleI12aemGZtWMSMo/Yw9cLBEm7dD+fyEi5AaB4AenenIBt0mhm/YqnEAVS5CyAJ4ZE7BiQ+i4\nlPsd5hxGf2V8/DRGh6IvQW83WVybzSIpKXqO6wZR7tsyNQi2AgJ+tz+mgLmCJ4qkHUYy2hX5liKy\nbPuyhZrK5eiNylPw6q423CflAgusNlPaO9suIp/Ta27JXKduOp/w4qos1f9BSXZ9DPBdjOcBbmQQ\nGKEYc4ykhwrSCAJbKyUc31uCRSR2vHBTA0uWvT1M8em3RURw8SEequIg8khij6hLbWSIZRqOVcBP\nqxurjqLk3i/fFqrn3BeY1wAlVCLZtKwtqZQ2Vm2JUaXy7kji2/DMv1EdIBqG4PjerdHcq1kLi8dz\nvQWrs7ahQcDnbtatpipQmYvFLSibcxgbv/Wy4zmPFBPxbDQ14gsIlGAGxSvfTAbdhz6aND0bYNAL\ng5AxZ7grqhvUL3vZLmRXTCr4E6K4B3SHixdvy1pjqydw4HWhrjRqYU/kYtbCbNP6Hu6T8bLYd3w/\neyGeXDpt3rX4qPYHFQh0CAJDQXBlfSgFRkGbUERcnTsFd4Kefn1ps1W1X86TjdD91zgxnVN00G7x\nQbiu2bMxC7GOXCb1dxT1qK3NCQnDZ+XmJbSRMR1V8WCT+zGUq6PAtBdtNsa6RgXpiQXQq+37FyoC\nHJEsBhWai0+IOpX0pp/Aj5uip51yQntzZYOPF0NEyXRRKkc+ApQjKOSfQPjp72Fz3Ssf6FRKD67Z\nHxpKJY+W5nNJWGckwAsl9xTFDX7i8J0KuFZnTjINILEHA2t3d+XPxSL/CBjqjYGwWr5tyet3UvOW\nvfpPXfNJEPcSDk2Tq/Ri3WnZMBs42waPIHQ5iEmPfqUSkJoRUbAQVZIMU1fuLLr3IU0Sm4NQsm7R\niBcGU3ZtCPjFCZ/JWLBtpVgS01bfyxn0w99Uw8hU6J5K7Nz4yC5rdWRo0f7JwzlMFK53HN/KerBc\nkk1UxRXXV7wMXPhAqh+7aaJuC5L4LLtPEqS6fnZpdmGeHPrsBAfGTOboziF33th9LNMlzfiCldSq\nI6Il8GGakTn5ITvWEK1zr247DtesEHNq2M/8CoP58Mjy+CXtVw9tdCVbqDikeDEMekaiA2ePeShx\n7MfcxfX1Uyio9Fel+QYF3/UlfS4wU6+gNlIvp6Kx7pwbr4NyOaZbPVsgw0apkRVga9J6O5ZuddBZ\nC8a9Iz4qs5NnSBaBDYVNu+o4RcupeeD7HaTcaOAB13glw5GYK/Ko97sTzBs+H4d+hU2dEMg78Meu\nD96CVhOJs8NdwBZrngVU1YhCZHNO1zguTlmltQQnRvVsmrKK2omvEWXhFnpifkhoxEMcARBXC6No\nGlmt/RT+zZJ1cq2e9hSUo7muggLroNn9LCdh24kSWKHLCPqQEDcs+VWql1s014FO8/YhAl+vgSOy\nMLKuB7ahyrHdqWxamWl2NjiEfqQbZhorqzecPvO3C+MIOjH+kc+8C2sjjeTlLvLEiNvSJUY2ScQq\n7k1w1wtXmnA5aCzy48N0W4dWyp4o6ggVYxUA3usZ62CEH3969mLAqKCH17d8NNiGAzTx9SvuqfH1\nPBIugYI8wdnk265EWMJ48pWELaJR84CUsyhrCdJcKZsWYFFwX0Xybptwcvdv3DrdgM1EtUw2T63a\nj52XnrbyMiLaL70QgAm1C9NM8wSkDd4p/3qJSFwm5nFZbxAT20sUjLX98hgjqgftnGHR0q1AX2vI\nGWS9EGeznXoeO0XKivK0RA2mWBAkSNmij5Ld/GIlvPk9rRtfj9f5Ea96eiOhhF5zBaI85OzzY7Xh\nHPwX4c88zzFHuo1fZAaNkKgl98ABmPOY5zA4O0wNaDZEaPZ1MYjryQWRBW25yQgBckj+lrUA2WLV\nAtKub0Syvb0DQOWSMHWbWZirghKqfXThee+BRsekENnno7s5JJaQAUKapZT5V9z0g6crTPyHR9xH\n0UR5hbvcjwVGuMKEqlS2asqpngEM1qA05Kyx3eGs0tH15B7oj7YHh9E4k0XflMmdYVhamgsxoNop\nBMfkbDLXN6Wd62I3UcksmvSKFEBT4X6wUZ7d0ee5xEqMorIiTL22CwJZEq2F2geLjXJw6nmkjmsQ\nuEoSQXdxsFzUD1DUsq/iYZXiqnoPsPOOqE7Wy7biuvztAApCx4bvTACdN5CrMbXyyijG0AB8x04C\nDvnnlL3R+YnzBPbhBOCWqOzPTDgPCWTKX7iqgxnUd/FN02uNTgBj/XfgEPYDfn6NSosMLGGO5jyK\n/EL5fWieF7VlM9Xw642jkqotOo5D1OEvpbok+gkLDUMi8uC7XRnG/+3VJpJI0xanVS4Wi67yb5DH\n15q6Q9iJ0QZ7m1eE7WxQzljO7VYDF7cPwUTRlSL1TWD62vbMcZXEY1JDOC3RUDpudW3kOA2v0MZd\nbizUm6VX34P8KVB+EoKiuW2u2lM+fuFJGRecdRHTdl9ma+WXYXrY6gHVYV9cPpwgR6QG6NgQ5h0U\nIt5jm/fEp/kp/bT/iAKAgWgwxQ7jNq7KnTdgWcudVm75OP8G7Kl36hUdVXRiRnh4F19jGHDQpOo9\nOcu2jggnXM5p1zo2+4pauk2pHmHkxbojSkSyuZDMw7NGALkigvsuTqArn9TMg2WpiiiBYP1W4fqp\nrzQRXJ0e32c9agUvg7n6iisaCrzBmamPHeBdNQvL7yVedfYyPkYuaAo+N1BfRWsj7UfA0hXExJXp\ns9SRL0BHvuDFV3IC0SLO41je/zPtegjXnwLF+r1MWLukp+D2+P6XSYAPJ+PbcpKs8Qyjqu2hj8aR\n+gs4UaHeltMKAp5YGD3eqLLrfrdVI1OhqNu6CdW6cr6ykNwIe9OivOfGrgQ0kpzi9tZ0ee99I6ij\nVpYa0Wcv7b5dMMQLLNTL+g4iXP7nOsFcOHWGAnz/V68vWUjbhAMxVypGQ1ZjMlRVvGaA+7NTG6DR\nARlTDjGD87LaapxJnCbZk7i/psXzrRKaxjqbLqtUexSO41esE/eWUSO8LoYXs4G32tyFgHuHSlTQ\nyJ2CYi+p/7E+TXbWhcWPpuxIALzg0E+nj34gYYvJ2TQqmmAmnktNBdOesvOPGUA0xWREY1KeYwl/\nnn+XI9NRI3zdWrGoWwVZcxZK+/fxGxFKR1o+yaS78liIadtPImR3vdRscgVWVBnNqiVzmdbH/qe2\nI3XKPkvviCY952zd6HPEY+2AqrK9G02vQC3EyMEIOAdIHoMhFh+j8woFa9I/dUWvZ5KMl0qd/ZBy\n5jx1Uh4Vhd1m1yVGO39Jr391I0qT80SfoFbqTMKP+cN3aY5SZR5n/v/gJ1mBuvGul5sJ4ckvn997\nPX8HxwG5r7+OpIEjM3jqRKs3SNcUaAQcZq47oaM3jYBbAcbmePUN+I0GT0XENdOx6fo9br/cSDXN\nrIrz7X+NgXR9xyjxzkxoo8LUMYGwfXa/LivuuCHd1ZY/oXLA4kkNX6wzz+EfS59w7YlQ1x6ym7/0\nlhL2fp5PLDL7Lutn6tEzDNLbQigU+AWiXbsVe9w//gq4J0rg0arJNpWk4bDTImBLn9JQrWZj7TCv\nTSPp7t/1Y+Ql8s4Zy738UcT16UGNjTkughC+eA3AwD0ue6EHENSybOw9xC8Jfn4EaF8RlD2APPV/\nT19fBHegE2NL2oSm5rJL5WvCbG+yzGJpA/1N0PlT30e1IZNWGrGHwzOZjy5LHbFQC9rb/5JcLl90\nPxNwiqyq7Y1wux6wZQAr0DQgQ2pQut2jPzMGEnRJDmv8+JFt63IZkv6sinlY548ReZpX945nKd25\n5ZIq7Cfek95Z8n3ULAnGHQrwVwOW0/VC2W6dA2qLZXt09TYWTG1PsMmZYovnoHEBsqlw9RxGfIJ6\nS3SxpXT3lX2jbLagMDjuxx3fYwMvJb6atVioJhSlysMNr8Hocg/B95SOuIK+jYAVBYbKvKNVF5Dx\nmFj9GdP4Q64FhYgUvehcWFHKGotEN+o6EIxrEi4UXphlXDJTxBtnZtpv2WIVhwq7k3AeiwW1V44/\nk4Vvaiyg2rttg6pl3VZZQfJXHpQKs1tDq7SbHxyTuawbM8NFisbhFNEZmdgPId4CUcNeeexSWAHM\n8SeRDlNWVd5h2NY0RzrpVyEl4R/VkGJsKks6mM1+rn1KgZVJ65EdnIMmWFCQJu3M8OKwIR/LRG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protect end_protected\n", "num_lines": 167}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// Amazon FPGA Hardware Development Kit\n//\n// Copyright Amazon.com, Inc. or its affiliates. All Rights Reserved.\n// SPDX-License-Identifier: Apache-2.0\n`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinxt_2017_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nYzI6RhCTbTb6xat5gHIeU45bfm2pOxmnaHqAF/ihtojvH1fxm05ID+E4jV65ljsSxg5hk/XNYq68\n5CkBs8aMWX2C/dCynTYKfDqEpu1XOG5vhg2rSwLazHMgBBiUX8dd/TfHBU43+45Jtb+i6MJjiXIT\nLBsrAhuqqlguwXMgFHWIpVMes70PJFciS4hmicgXcR8ADn99xdNaECHKlsOyP4wal/3xETbCLOgz\nrY0WTcy6+DeDqM50GUbu/OwxE/H7hE1bcXDowM9dJ67aUow8Jz9FWmx9rnWha+w0R2idFxiRDIkF\nqo2Q/g7aiLrgZhYsdr48/+HQ+hZdLV1ht2cUCw==\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nxSa4lDWJPFFHiwekdDATEy0KtH6thL6nQyd1iZiJLJlNN0m72osWSdzXVg5vlTAOLu1Djn8YfwAS\n8Ci1p8N1sdRHih0qs3bR8EdQIdQgSH6Jvo7IeitExQzPQSHZX2FFBNfeFMSNWqy7rAf966pPa8x4\nuVfwS3Iqq45mqDrB+Fo=\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nMauTOqq1ePQoCVfMD6s8BkjRyvniNKLMVJv97eUg2GNKwdp6+Pq3ihUtha7atOOqdhLkbr2DWntz\nDGYI4P4MrI/o9m4u8NYO4xNDlwHAyMABzkf+86pzXRQGz9LFVwrluUGiWtQQ0Y6xlUjx0xJUwINH\nsPrEw3NmP7E+F1pVM2A=\n\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\nT1wGXZJPz+3eyrBmcY4j5dqmG1h41cDh5HE8W3W6NQEuDP2Md6yWbAfQdk8OYIwa/nvJab58+7LM\nDngjbM3YwQ==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 2864)\n`pragma protect data_block\nvR7+IXoeIJpBd3RFIeE3dOK6BypJOZY90p1Ac8F+1N5uMKLd4HYmm/VAQzJiaiYp9plobe/jVyh7\nmQpaUK5vPpi7nd2BtL2p8GAoeQOQ2B+uzqNcTJSjA/yudJDdSSkw3xy3GDWxPvHsixMHDu1aDGfJ\n8+mwwNJdr7qEJ6MPXswuWq174H6HCrUpQSsWW6qveCd7SOSmP+m9kCj/KdoOlzEfBVqOxVVLDuHE\nmdotE8mGo5jbnsJgBE8IuVMnxgHmNq3bhYzIYusn+nX+X9XXBXD1Qupk1OQYf3Nwc8GYoCGPzCk3\nojQwxOvS541fF/xn9NAj3hj1T/tXwrlkkoInomWJ/JS9TdEbKyQBCtyKf59hSolXzqmLfxPRU1/i\n6AOKABIOTjDiwOrz2iwIaal/D7d72iPZTY3UExoy9YutY2AmVI0WbL29SyDQDAeiXJiOAEU/8img\nbRDyi0c1UO4F10eyBYoWBsW71tV5cBGjrszeS+H5GIS97UVOQ1qVw1mQpd3ZpLztce3VhziNRr5R\nL/FYl+AzceFYPLynkpfKUB1UyaZgNypdcNmlvTBb2AtZARRt8TFA5M5KGl1A7lP5Bap1c1HY1hgP\n9lZit/phjdAvayLwFKcoOFXpqNhcSGH75lsvcf2a8Cb48BSnfh3vgpRkoLjxoVcaekA6ZrUHTwbB\nX6jVLd61+QuRAYZ7f7Yl4dIskRKaYQctxxvT8867KeyNW/Q9xRaUaKS7M6uZRzpRbR2Hd7VaUtx+\nkxP7w5bSIASjBIctHZvWgtmvkUGiKHarC/OGkM6vIylCEYOLlBv5YgKX81CvNjZH/4CfAp7GMHdy\nrmmy12YztImSsxhrNfHTy1HGxLcnwS1kQxUNlEkq02ZEF+mEMxMumfAGlHdJbOBXn1EE2fMm5zhk\nJVI0rja3v33WlGb2R5NHArLna5PNh0UaZSC+exqb8sUxNS89jUypbtCJkBBhVMEHgv6+Iu+c3Orc\n4jkk87BGuZI8nnGUbOwO8KCeFUcbT3XrxhokwjpqlcblZ5+D+EbjvE2dAR2dreFckak3RXIuam5h\nzKjWbpv4g2qThgwWedMBFBuGEltpMNpZp1S/eng2cVDqrR0xam5E1EwEspWIZvXat+eke0hv5uDC\nrpp3/ipF0m/GgD2tmdmBsFNZNLWjK2vpFF5Y+19xYc00QpzR9td2M9pzcmboiA0JHaC4E2wVFabm\nwn4sI3BFJEiRj4F8ag8IneahRFxNinQqejokeDQQKMB+b6/TqG4KSnbL05AHAuBYmo93SwKmHlu9\niQXEOaws0ck0A/mWpinx5U4ADgASu7aqFx+7QXYYvepDs1WMF0Jhr1NU9TckcYlQ0aiP1pEKcO4+\ndbZanSWH9iolIFNGzBgZtQ+j4dVeSiCwPCyAu8c36i1/bjc+N9wiAJhheLmq6fYOSn3V19ATajp7\npM+hflNQ6GlRXV/FMbNuUM17SVqy+TjJ8LFWFQKUN9bddyJFavGHr30DlQ5U1AgCVVZLI2EuQiok\n27B45wfZ2UgyqUHaS2eJggqOS9jsDgjsES64hjIsjorQlyZyRV9nVejQk0L9+Kf6ScRxGD/joWuY\nQ9eGnJnkwq0t6nF5xWh5nlNkaBEtZeeaE7P0LqhuE9k2zskOFFF1XOzovKHBEfuCYgE/0KADYDnK\nDkDbnj2xDjaJ4qJ0Kh6HUNS/xy5CHRoQAUPJ7H9eJLm3dsWcJQ3PWQodYEKz7vilSsiy6ryMymRo\n8X0nQHDQb5vOoxwNOOn7C+LkNow4w4aKhdC2s12H5M7SRmpnQ8CcEsh50ZdxWWlSVrFXHcgPmXHE\nKE/y8isAA8ZABU5Wr4Mm+lh2lFyZe5tDT17kiQvkBiJfAoFb9nrc9kvtKxFcbtWAOYq83zVh7sw2\nkBaTJ2DxxKMWEKaXwl4xsMuCsZ6OaVhW6UcGIITe1KdfnoBTWBM+xDwv3ck5rKWGb3AUqRnbUMsK\n8DgVGU9D8My1BDQgiRzJ5c+abFZ6kTSugULXCEq9ERntrWG1M+kX0IzzMZTVMAvybi4i+lq7jTK4\n6tS2Bpzt891+3GezNjhRbQzxlZIsuZ5TQ61RU/j5H44mnEEM61nPmQPcFhcCPx/wnin4WbViJC5a\n+UT6qm5fNii4cuiJqEhTBzr0CmdFPfjnv6SSEGvYy+cOcQdo1+gQkEcKWGT5dL8IdCjZSsAQWAFC\n+x3MH32YBUYwixG/o1AV2Ko/a9N5LRIX954/UCeYOJCe5hFcD9NKhmprzKMz2xwopfnh4yoXcdMJ\ntkkrhoiNs0DjPu5mKH6hoCDZOJeAIiPoPPc01Vo8w0aoTwhCWBHYR9RSu78Dmy0+MSHhDzxzvZYF\nGTxyfwwkV1t8YkxY75K1AtaHHhQLmUNoddAFtKroQBuplzNQEYrDosfqC/CFODAVjNC6S9l3FS4T\nWbi+jtJ0lQErhQl2Xr2LEMlp/cN7o9YlZcbp5K+wlVbB4R2RHR+4mqPbm49XOdE97IeqRWR5F7tF\nOj+iOH6D9v0nKJKHLIPnUNmigwODed8KwZ09HI3FLuqIcUqTlTZABuxPhqOc8xXkXLxrH+bzJjyl\nGMuLGUwplfc2bLbueKeSWuOQitcyDYjKbPGSky8qrtl4RhW/4YI5Hn3KVmxIad1e9vrOf5Ux7LqL\nzRw7be2tFjtsqpKJ/zFMTtK56IN6FXWcisEAn9lkk+pYDkBIr/dQwZarBPmbXJQtrKEPt/iz50kN\n3JtjeFB1l3lTNEm4ki+S+kpY6PmLV2P8Xwg9eSMBe606GzPYqWZg9XOPRWuDnP71jx+Ahj5kBiRB\n83BM3i9ZyPODeLP6tz+JBiQPNaKRfdzGlBTDUVUM7xUwrRFxbqNYG6KYj+493GKo0Kcn8+yVs78m\nuMsPjwBGYieWKbse0kBY3p2T9/KtA39rxUt8p2eISqVordD1KV/vIenzYMqZDok0QHwx768MwWU6\n1q57GzzyB8hd+YPOlTz8B8BMrrL1AJId1nJfL0z4W6NNKifE0dZLB4qFxus4d2AXgfnEDT9ZHZiV\nwwi3LdybbzpsM2mseT9w2HBSIuTgqwX6kdSfRPLxc/bpn7ZqAODF2bZ/kmm+8o7YI+/CTqfj4TLF\nk2+r95/P+ce/2a2g8o+RxpYehSNSiG0BK4oa4Zd8z4zVk7DBde0Yena1bdDCid9GsPyTGcbCWMdP\nGRGhsUeNSBcWi1h9gY0V2CGUJAT/rWqV9wwXGQVV6jEfosieq+6DmNYVIav+xvxPshfeulHrknPu\nCx1u5uoilA+a8nCZxYMa8dUYCihg8Ca4ftPjbbTIH3R0+z+GlweFNkdLbSuOGomo97DYoAiuig1Y\nYMf9kHMxqu/lmj2fr8kRuDKmk7deHFbxD3TTdX3fa/FhHTCBUTs4zDhko5t1d8vSjSD1HmIiS6lk\nwVcYyWoJ8JZOq4D/TJTY3QUualQEE+Vlu6NsX7bTye24cdOhPM+Ou0szgCHhtpweGrPt0l46DKtb\nwKZVhN3jMfTSCeAbYN/RjA4Gyb7mlIDSsuKQog9l2jP8yb0dRD0NAZ/c7UPGggwWIX7G8Eei7c2V\nobqHNG9fmiQFr1sa4P1qjfM53NzWwEg2AZUaDTn1p0mkJ3YC/GfucgquVbIbz91FjD+m+ehmp3vg\nYDzcoZvNKpq5J2VBYs9iKqn9UE6FObH4YupmYYb/xcq7Nu+mjc8wMq+3g6L7cAsayrobefUwCIDP\nEoUxh8G2NibYTXadOPt7oH21Z3IDfjxOccCqE7LepfQzE/OH2E500qlTRdKJY/Tmgcekh2bUnwu3\nXlQJsZphGfJyyvZyppk=\n`pragma protect end_protected\n", "num_lines": 93}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// Amazon FPGA Hardware Development Kit\n//\n// Copyright Amazon.com, Inc. or its affiliates. All Rights Reserved.\n// SPDX-License-Identifier: Apache-2.0\n\n`pragma protect begin_protected\n`pragma protect version = 2\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect begin_commonblock\n`pragma protect control error_handling=\"delegated\"\n`pragma protect end_commonblock\n`pragma protect begin_toolblock\n`pragma protect rights_digest_method=\"sha256\"\n`pragma protect key_keyowner = \"Xilinx\", key_keyname= \"xilinxt_2017_05\", key_method = \"rsa\", key_block\nEZ2tH3LeMVv7vukHaN/tv+pQmwZX81o7thyHVDWF7mM93FaXyNhCXTSyDdazJu7/59Py93a+cCj9\nEEEG/UMXcssv/u4GhJzoLhNbGUxPXLsX3SIGrTAhYMqUghm1uiPpNdST+Khvq3rfWs5cehEPvsWw\n8A52qamT0g71hscVONAjIadCoIAAQvF6wBVGan/xoUsiiuVj/StB/MRCaU1h33zJVnkJChMNuv1u\nGcwL2vTjF2mJSTLkMDWU4d3JqnNNe6JLK5eokUOlzu7E90SIv72KLBebeiWgyJXoUTk3vuN6RBcl\n1NLulevXSjI5J1IzTMQ8KdMirHBaVA6r1l2Wsw==\n\n`pragma protect control xilinx_configuration_visible = \"false\"\n`pragma protect control xilinx_enable_modification = \"false\"\n`pragma protect control xilinx_enable_probing = \"false\"\n`pragma protect end_toolblock=\"rUY20Sun5Njk38TaHPm9PEsmv9niNjWSTL+22BD4WpE=\"\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 7104)\n`pragma protect data_block\ns80ewUsMopuQpWnFB2sB+ONF6yKt/CFEoFhY8eN6Fd++8VwoecJwX+D+xdDD1B4a99zC2wgLlCPa\nLpG4B34md3a1iLti2ElPTT75bw6YhUJ3GFvtvWk43x4QV9jMJaVTQIQQC5q0jUynSr0bHfYCiI88\nyr6/+srQ6R6y+eENcHfUzONGqx+BfCa29/UbSZohsT1dVC59xufibiI0SvLZRvICksWXk9bL3dow\nWxrDptbLgNjVBIhyLPwiuQvDtZ5PMZWKKhwF8c2Kh4IGBpy4tY8doLEbF5CaNIcRp92hAQ/MOEYh\ni1gneLVYlLQiQR8nlBGPcYH4u7ymoTFvL+Sx0mMJSAxCrFziTeNdzNWf5te5fh2RxaZ+6l2QS9Zk\nOxAMKLy0ZmD/ND/8AXlSsLUughpPYFeij8vZmZ+WsDCp8B5ibGhpEZrjrZQNTgu0HU4wsgr3jbiv\nyDCQJIMTSWKKGwDHgVjti4ctxK+IjUu8zYEAdsjlLFKx0rGaJjnCGqD9L0DryHXvfojIT5xfvR8C\nqy5bTiLFSQawaXjWjJmXgdvIxazoE7yIsDENaKMCBdSafJsNkx+O/MR0plWJ/Pgx04t/pEP5Cy6W\notlG94pAmM47ogF4MnMHRF+rVpysu9p8m0sl3rUiPHfRhIOFWgHRKk1ZC3HOo4TQmeQaGWyTeWvM\n9OlrB+DE2U4vCjeoJV9O+vKiKC8tq3z9IfSvRqcW9Fhk7dEjs3qnCPaD1kYi8+UZCio/j6eYf7UN\nUKhq+I9qxsyR1BmhFNu6Af6B3hAY5Qeb6UH/KMbqHCoGlJEhXsfes2Kp8BvqBfl8/CdHhvLpK0aX\ntAfF+W+Uh/DfOmIE4/wtmA8TpolUsdEHfd6qFWx74M/+vi1cZgIN2YkyZ8GWTixSjIbciGE3+T5f\neVr2/IrDuPSuAn7sq89UGWxnDYMorw7GGSt1X28kEK3NaFs9f87SLlx0k/Z+/MFXs8PPrf5eIv2W\nLC0Y0bSmQY4Fk4j8+thYuNvWqXR/67m6PT0NlzZa5bDgn4+htU2HhH4eLs9ABfPQLT3pa2R5P2HP\nscuqY0NDBfGiyCKbUsAAqrURj+BP4avJ0C0mm2SM260c/HYpjQ+unBaY0G0yc9iXMTCmEDor4qav\nlQw2qFwUTFdc0WiZoeO80OZd27i9heulJJ301rqnlDvSz/9Fk7cUz7GFiKaHVCTqL+/u5J8xY+O9\nN/ahSBFZGwQR/ODX+M3OGTfJi3ZCKECD6qTDlmZqjqXd24O3YWSIo2+IT6QVV4XPZoXkLrOmVDnI\nr8LK+396XsuJ8HnkGihELPBRVQgg/Y2U/kCdTPFL9/+0rtJdAxLNGqJOdEeUz5gW9g7i+bvdSiyC\nvcYoq8wmOhoVRi+spru+R2/MUsriYLHXx24rxpeMNG04lEU10Hor/xAcwgmTI8tNwDJB4b0r80JM\nr+swUyO06BPv9ZsbHycD7I4g10HyBw/mu20EZ/yf5QcjEDjBrIdDIZPl+4FwDjq7McfG2NR6Vwau\nD5IS7YrxlAThTO0K1P2pE9MbOgfEQ1Rk4DZWkKil33leAcmvydIcK3HYtwtDU/YQPEcxWx448JRL\n+qaDsGmAxIA4wczgpXq7YKRq+f+3Hmu+PfOUTEUnwRQIjVl8R6IOpAh0WOMZQWCdOgrGPjGlCuRG\nSj34xTHAXX0+vONpgapnAJgA4gi493EuFeruDbwCdyanUOvJqUveFWtpF/0aJlHU/Df1tiLryl4G\n/GwLb58dMvdwNDSQrE0G3RroxyiyvK+EfLIKkCE+nHmsoBwCOn3V0+ZdOFfuj0Dr6dAyCYx6yDno\nyhkLi4iZLHxkUVs6Z8BKFIxza/StaoqYG8iGqRhRdGH0JfU1H7J/A+yjerNS61Ap4SQ7Vm1v/f7h\n2iRJeYDTWlK/2fL8HZBAG/PAjHDQf3E9YuObk+Xgu9fN1de5T5A1lQRGuneOwRHOofo/EXNtJAq/\nOl0V+IO/oPnzm9DMJrVbAVHm30VyzW9VxHsCliYJxoVEalwZJybjLwk+FdHFmb9246qlJwJbWnH4\ntXbVHikM/TbIGn4q8M4UCERAA1I/krb+5dLwu4egiG7NkuoUuuoABg4oN7dXc/r/Mm8NEFa+P4Hw\ne+1sp9vGpG+kHMIhaMTEDLIa/6KzlIXRsYsdYa0QpnyY06TR4l0Gy4ytHNPGLgqBD7PviK+eZzvf\nP8nygmraTiTwNwRtqoF5DkLMPY7KrNhHdsJTTgHFL/vhwfvTUgukqPrT5ehF3IK9BvQCfIRVdvDr\ngwbBGNbtI4SJJkYmHZH/m/KGnWlqoCOXNVvjVDavftAXr4mNtx5vSqVFx+9OMVmYlyn0EUCCGYtu\nEC3KGWAXVkH646lAaw8lNgp5NCLhLM6Hx3e+9V6h/Q6I/QDjA7/6NUF5Zf/Gcjobv2X/ey8c6eDl\n284v7ZAE1oBlpj8Y0/yDyt9KKkpq6RP70BnA+rfwWmLP4pygJWuO/cPHybgeC8CqCZ7GoeORZAXA\nU4r33uwqrqnIZSGSYXJMsnsybG/GrXXAIwRo3bH6SR0rX6gQJdotqEgabVXMX0P0hpouKaVn0M68\nuF9IZxrO+3PD+j1RpJ8LJHpEaJwyION/7PgQyBNXJ0SBSmbP1LLmxStNb4a9PMJ7VQO7xcHrVVXw\nlfMG4cbHHGmohg8vRFuAyWwTXUlQmISjk6tTQOsdVWJB/BoXku5d98fMhEEnHoZ0jJ1atIFuijgr\n828KNwZdmI3SZSmD5lVONV/zLFgtWrlNp7hcnl4q49r1tG8YgA71mEeB7XFAciZXDdRX10DdKQ/8\nueUhQ7XYmyKp+Yl5ILHf7G8htGitx9q5hDLIxDq8h3Z0R4PaX9WK87RP+mog7nObs8ajRs8bI5Rm\nu0hIk8VsLXzRr7pT92a89EPnBnGpkAEdBziznE+hxBHR5o4teEJvce0yQl52gWeO2dcql9BozfJE\nFL9If/OEfYyQdWi8qzS5fsl53esw7AH11jwoYPsxhQUUmeH1dAxMi+RkW3+WaQOgEJjRZxSIQJqL\n33lwu/jfnmRXWEII7s8SpUseLgIeo7HT6+ZmveNMOw8uguta78FJfrif6tpA1KBoCkNnb5bxhmb5\nzDhe/Q4Eg0UW7/VSpMZfi7ypuyIGzdWCY1KNWeDovzco0xeg13BFsxiVw29YpKKRcFQTLsJt6OWh\n87ouBHuJBg2984G5TcShmKAsBR8D0ZPEACu0MrWXeQw34UPWNdtrmvq996W5xNQHnqN8lPAWBvVI\n9rrYk6I2uook//PGmgLi/1WDq3Gix3OSNfPkDtUvbQJA1pEXOgYASEjgdyob1B5NpHQguqAqG/NP\nCBILzgyuQZ0/CDtPua+otMbnSz1hhu9UC8Na/QyhKNT0yHY0ug2C9+sruPezZJTWMnmEXRjxRPuz\n21KqzD4jhi/g6BMrG4QGVwUhahok3g5FtRrmVakP2xzBwhMX1cg/pKzY9ne9lAVLtwctLnxPlAzs\nGdi5Q7fg8K2NaopGE/r7Pv5DggEiCQ9Hi8nXlRSJMMKJwbFjikNyte8r4eQocIjYNj0UNQETMbk4\npe2gg2x7enboyWj99a97kTLiGsUF9TwCN287ECxoUJxcvX/1kbUGR+Xcp0y1L98rVe0eXeHsju3U\nUgzRncsty6h4r+hpjjBLgWmv5AJGYXEQ2BY9IvgZ24vfeM3HufVPfJdh/zmH/xq8f0MT5fPvMyVL\nle16t9riMoGhkW24elZpnNUmNLz4sByGsu23+ad/aelyWV4QEuFzRuUbM5E7bmkb1szuc0njsNcx\nLWcRDU7MTOM2fQ3FCQFxicl2wh+vW48qbL1ZT1JmiDqb8QYCEutTKcar6njaeXvBlFfiBTXdWp2C\n9X84Vc2EB5jCk1F7rUTlBtbGteCdD7P28n11GyVA+pJu5ixjtgg+tB9hxn6h/JBj8jChM+MC2PRB\nCZXXu5bTgSwmFO6yjYsFBkB145FV5v2dsyQFO9OgQZnZ21xVj2gik4U5hwFDrJtHeLUfmZ2cwR8P\ncoevnuwsBDXk4At8S24i8lNr4vgZRwV5SeMuVbH4V2ma6vze9/Ja8i4GxWzTlexnY4mdK6Bx7HFx\nWpAK3k5KxaKAUYf4H5I79b5ooSFwEhqeiVP5s/Ee3eGnqD50nAmNbwNVRfotlVzqtIljbTAPOHGP\nByBkZ/BRg4DqPQv/cn3Uw5zzE0jBTfisKxUrglduvQ2alHDWBbQbXcgI5VRf6HmZumEEnHzxByrm\n2EcwT3aOsJISSctNqu0oBvFtYuIFegeIfRZZ0HL50kRBPFsfJNmyukH9pWUsc89MqXDoA8MMJYdk\nHHbdKQeWkjL1tI4z4alE5OrwZeH49ome+bTTpxv02lLxfprer07a2Oq7k5q1Reql9rOR4QqiOMuM\nZyrwD1sLXYLE/6AmGYTArRQWEM0/9pehNoZvWq4Ilu8z8Yh8oydxsCCjEkTshdOUQ43xmPI+1/gZ\nBHpyvU12X7xqEd1HqLLFiGhilgpjSp/Fsbe4VQbfn4VZ/nUfYBGodDEK+gyjt/OT/atph4YN3JhS\nfuhY0wT3zaZbBXVXrt8yhz4IfVDN9d02WMFaBvPKYuGjiyDL8+CsYklbIhGZ8miP4nKqs1sUTyxZ\nn+K21cQoq7Ojc+A9Xo3KI00PBTw1lZA7EhzBOV2E9LjvwkadmwaRQvlFEk+Ocn5Hin0wkKeINBEo\n+SAMJFr8tRLPDnumTaH+zKX+VRFc3a78jKnRamRCqiZ+nVobBjl9sQT0rl6/J/Q+v6V4munc6L+/\n1Pdq84XnKdcQOj4fjFFVUzoyw2enbm0hc3ViDLtensCWwA0pa9d1mVjtgk8oweDzsRRtyCmCBX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protect end_protected\n", "num_lines": 155}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "// Amazon FPGA Hardware Development Kit\n//\n// Copyright Amazon.com, Inc. or its affiliates. All Rights Reserved.\n// SPDX-License-Identifier: Apache-2.0\n\n`pragma protect begin_protected\n`pragma protect version = 2\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect begin_commonblock\n`pragma protect control error_handling=\"delegated\"\n`pragma protect end_commonblock\n`pragma protect begin_toolblock\n`pragma protect rights_digest_method=\"sha256\"\n`pragma protect key_keyowner = \"Xilinx\", key_keyname= \"xilinxt_2017_05\", key_method = \"rsa\", key_block\nvxYrgyihqymJKAP1U28sgDSyhejSTPCyoUjaqdt5WpBI9R20BcLbWe1TkPoIfiLoe5JcYoh8zcEy\n0EJbDuzXNpMlUsLCLACJKyYPFgeXm3JJjqNgDHxdT4SnSA+6wAkcS7u+0KKbWdDKoDGvhR0h8tUN\nw3uYUVG4qKcNbH3Lj2AtVob8BETwf+2i9aj1O6RkfV8/w5fzT6nAZbgaFIeP2n5jyxDhbzUod7zq\nvpH2JIlIoFJiS2SJPVXJnOMeLJjESPv4qaVrQETlfkJzB6BM+S9FHJwwyltBkbbw9lu2CJhM67vz\nXaH48z6tgRVlzhHMwLlMvbLnZdz9VLTy0g6N/A==\n\n`pragma protect control xilinx_configuration_visible = \"false\"\n`pragma protect control xilinx_enable_modification = \"false\"\n`pragma protect control xilinx_enable_probing = \"false\"\n`pragma protect end_toolblock=\"x+L9+fi2J1WDHSxBWt5lueyga5qkA+vDtQM6hMKDc1E=\"\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 2864)\n`pragma protect data_block\n5taEktq50cRsA2FFJCoSas6h/TCKO1CVAPgsswMGXGhqo89jI3VrZTh7SQbXb6QW5t0Qsr3Qm8UA\nLM3S186QWkudLr+GQUVrHMdLFhNN2Iq5q4wm4UTrtKDiZnG6U8shDJV0wIx6iPF0qWV6rxPoWmJM\n6vMB1J2dmpnHqjvaDEVjrjMJqeVARsfjyZPMkKdOsdZ4JABmvQlvkB3awwuePZ/fmtoQYjy7BiVQ\nbRykXvYs7Zcu7s/tZYAULiw+XT+bzD9F3+/dUBmOb4MDnJdEfide9Hjb07FrSGHJhYsigWpSnV7E\npLZ4k2SUT9FImUFhdq+2uH6qaY5jjJHtS4Azh4O5PagpjFuTrxngrBALm+RLx4yzWvnikosgRTGB\nuMC5E743faQ1fXmzhJtsYiCjNw2U1NgzTahU3gdIpPXG4ng23qPBlFBVPPw5CSTLsgkfN3+dLrAn\nseCaDcswFoN6ircxRELdg8PQ+VNXc7QQzTB1s3RuFigVLqu5YZ7VjSgJ7C1/Wb/RfJUEzEioMB3J\n73SSim6WfdSOUfzck+kREOv9ncUyCk2g3gvCSl9R9+TSJF/OHvAzegxI7s3b5DoYCnl4X5pJ5y8s\n5bbkLzpxFdhwxWXokP2GJ7hUY2TymJWPOw0yydphTXzfbDiITc6IeMeG18Fa3Y8JAtKPTMfoYKZz\nbf4KajYP0SWreoTpr/tsXqJfwXqDUgnAqeySH9cPyZmdocS5K8qxtT/tgDF4fb5DEQjv4bnxnZoo\nGGjJangAk+DKFm9EaqmJnySi/eiBQ+IjX7pS+71GFFQXAbyky0xUwD4p0bGfJNOOGyP2vi3OP2hC\nxWTgfnghzTlwZUa49zWoyqLYAxe0RadRXo1ktTwQcqAyWxPz6aUFnFyzC4WgJSVYb1/xUK0FAhCv\nAWBsqO14dK256a1t7Fk7oAJKwWa4KgXWnQkg2ks2IbiWn4NXCcN6+wOtCEBEq5ubcahtYD71iVvx\nikpW8w1LwDvsf4wC7E8Emk4/nRaYEvqnuDOXWFVox6O7psO7tY9cJs80XXDRROEXVEKSnbL1cS7H\nfMuMags3AHXr+ylq14rwmKgAJRDSR0u0R6nLbXEL6KM1NLXSOcUjw3/LXEWRnfAkj6Yf6ub/C+ER\nr2KYiyq5/doLwcVIyAojamSNmWPg6LeMnE48RIBnzUPm87UHajCzraztpiVzn85brW/qqydwYOZB\nWuIDmrAPelZvgSiOYKGeL0j764Idfi+zRHHehnKhelB4GJJBwt0EsFxZ0DOOz+PWUvp32JDsdXfx\n8uKmWb5Gma9ylHp5FSkVZsQbkn4PmzK72UwaUQFx1LvrQ+fi5DEUpDmkrkapEhBmsMq4dQ25arLt\nO2aGbF+w4SqF2IygkHe6GbTJH+2xO3ezQ9Z5nzQUBEcdyYSwos2WYy7VjSJHmtitPQjD432boeQj\njg24Vv4WttYBdXKyQNpclDyDVeXFS4YtFr1YVDFu+DYHKsYP2w4Axh62q65xeK3do1cTpT2nIVyB\nslqUvk13qIH1WWUDTXOLvHuGg7GgqVhRl17G1AhAR+ivzxvn+BN+6apWIb3oZH/1Ig8BbjkechJG\nyqWZcpCGrcEEOh3Ld/b4ZfvAlEAk1L3uvW1qNMTjyOn96iMj88mGfoULkQlA1ynrUxAvi/u4BBVE\n0AHUmX4S93UaltYkZJAjRbnhWZV5Flhd87wWnbGidmqd1mJmyS75csuA6vZ1JlNr3GEZqY1a69bG\n2F5MFJ3Zlcs8U8D7mdCMCBfZGjoQ7PCIBZ3bWKWTCHfko039pH0ilSTz4Vr/mcKh05hX+Nzcs8t9\nTSD6y1DMWKMEJgGMcZADjQsIcIzOBcqcXWnc7S0RY1blKGkNNBcDz+MWZgdd6sf+JZTej9sblrue\nkJQ8PZfHrbK61Cb9RK4+oZg4fPtdNsBDDhlga6DVDJb0DbTHRFpDvUMQwMRbFq9Lfty+lAElnf7u\nTa+/S+uc0Gn18671sm1/Oe6HYROdOG+x4YNCxlwU6VzICpEcv7dXYOZL0fdRa8VG957QeoZvgiuv\nQ6cbSXf/evWVXtN/snCnsmrF44kSZxMwYtKVBIYQVm1V/ve1c1kD8eMUGu4BCOykD0ma25e0BboL\nYTwhJTeVkRHsUP7tL87gLyqfsMB2TxYCeMhZ4Sp+AzB6wQVgg1dbgRarT5tx3gUH92pf+PXNrGxt\nMWSyPLnCk3GS7OXK1Sgod+pmzwtlyCGhypTVYNXmIWyZzmPro/zjFG4aeVZ2qpAO3Ep12/YiN3uZ\nojJqdDy3PXPAwq8TUFasbVWAxZGdkS4rrPFx4zIKCZJh4FzM/DgiVStDvn7sNB2ZOyhVlQEuksAl\nEek3OL9PBqkcKmjByLM0ykjFcuI1WXfw1cT/ntVWvLNsLWH7MI5/anG+Yh07FNNhOCRu0sWec8hV\nbutTOkBWjm5UUV4AJSSvRWhgJ+/FMjXPQUvEL8IkAdtZpwNCQmdbvS5VmKMFC/4DTCHOnqpVQ+T2\nsIkWpbPqUrHSM4Af06D2PeiKHgI+Xl/rBmNLI/Lij142EAhapTf8U8ct61FEUupggAmQfjO7ijtM\n5xtKWVMnymCXH30kUgqzjmuBK/+o3a4kkmzMs0KzWMGJA45gM7N/K0FywSBBEJdIqG54fW6IsbpW\nm/Z6iOXVPFnDIg04hh8ny5B1XrGmsg/5hECNTDIj0iIzI7CKr8sE4dN8phQrwMlKQ53rOCdzuvTi\nCYLgF9GBa/NEFw0Jut2nHn90X2AITHpM4tRgGTDoWcJUQkKxhvoKFKogeo4S4OiPan/VuG96vvoy\n5vJwvqHNIGqEjrraUCHfSTRhmOAhMsndoJUbMeS1Yu+2fUCzp07aypRaA/+nXUEyP1wn6/h2sp+f\nrpc39ww6BK/ozcBRNVYth38sf3ql7ZbSsErm+Exbq2tivUVp5DsR1P//Kj1H6lPUkbPVj2kDvwTi\nzF+S+T+6rS18i/vKYqz7rggdQRX9xoYvw1as4tCRQSs3wSsgW17YzPW1L74LqgZMbMbPKQxJio3G\nlFcbHQdHNt80DX9wqDu++zDI9mF7CC/s6jxnZL5WNXmlxwXD8RQXQKl//K7pKN/LO2qxAWCqGzOh\nQq00M8IpLWaFMqpIDGS8oZQWIh74sPqstcpgTJN6vXMtSrvdSjrPxsgxEiVPbLbXCIduWyanCJnX\nJ2eFxR1N9hshNBNOPi9mrLlHOXUROpVkvvKMXMNCpeCoYRtXVZiBh0GXesz/kLYTYSSqQNjlKW4u\nIg8hXlP1uGW34eyrd7uifQpwQUHSLvXn18f1ldLYH9XoLp3qElinpFPm6dp1hTcNPtFULXYK64Fj\na+92yCnj7/stq+5UuDereuLSe3icjDZYIBo8Oz3YwHP9bOe+GWanG+AtuPqE1bU+k6OsMuuCkbAz\nv7MEUbMSxKQDzzq4ObJeu3pwHw6U6/UAzSdLtJiZ6bU2r2XrSkwW15/v3+Ren7nEXjUQSEReo2Fj\n31H8jinz+FpmNhEe2mhFIg0vbkzIznHJwIjrqNAVsX6LejMxubwI/TvbcgQruQvR4nMmlBV0txet\nl2fcLkt33a3wMFaS1i0GmjfY0zbZN0NaEPwO6xYKe4zIy99cJ/mIJT9KTHbyWd5JB2MaI3Hrue3N\nP0R+NXDfASQi/zgWQ76EuyLK8F3RDXC/PNpi5KlHxPgiac3aTNUAUp5Lr461CY4gk97xV68zDyOD\nFl/rZwacKC5ffSrSDC0RXeIpN4Mw1zRSBCvMnATTxknYmpVnbU/gP+6VgFVKlINOrTv2AOjbNIr1\nUvDXqRks7iP9II8C2V8=\n`pragma protect end_protected\n", "num_lines": 81}
{"repo_name": "aws-fpga-f1-u200", "repo_creator": "aws", "programming_language": "V", "code": "//*****************************************************************************\n// (c) Copyright 2011-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n\n//Generated by MBAC v3.04\n//8-12-2010, 14h 8m 23s\n//--------------------------------------------\n\n//RESET_POLARITY_SYMBOL, set to ! (or blank) for active low (high)\n`define AKRPS ! // ###MBAC###\n\n`timescale 1 ps / 1 ps // ###MBAC###\n\n//Assertion circuit for vunit: inline\n//vunit is bound to module: Axi4LitePC\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_protocol_checker_v1_1_12_axi4litepc_asr_inline (Axi4LitePC_asr_inline_out, reset, BVALID, BRESP, ACLK, RVALID, RRESP);\n  parameter DATA_WIDTH = 64;\n  output [3:1] Axi4LitePC_asr_inline_out;\n  input reset, BVALID, ACLK, RVALID;\n  input [1:0] BRESP;\n  input [1:0] RRESP;\n\n  reg ASR_1, ASR_2, ASR_3;\n\n  assign Axi4LitePC_asr_inline_out={ASR_3, ASR_2, ASR_1};\n\n  //---------------\n  //ASR_1 : assert property ( @(posedge ACLK) ( BVALID |-> BRESP != 2'b1 ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_1<=0; else\n    ASR_1 <= ((BVALID && !((BRESP != 2'b1))));\n\n  //---------------\n  //ASR_2 : assert property ( @(posedge ACLK) ( RVALID |-> RRESP != 2'b1 ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_2<=0; else\n    ASR_2 <= ((RVALID && !((RRESP != 2'b1))));\n\n  //---------------\n  //ASR_3 : assert property ( @(posedge ACLK) ( ( DATA_WIDTH == 32 || DATA_WIDTH == 64 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_3<=0; else\n    ASR_3 <= (!(((DATA_WIDTH == 32) || (DATA_WIDTH == 64))));\n\nendmodule //Axi4LitePC_asr_inline\n/*Instantiation code:\nAxi4LitePC_asr_inline #(DATA_WIDTH) i_Axi4LitePC_asr_inline (Axi4LitePC_asr_inline_out, reset, BVALID, BRESP, ACLK, RVALID, RRESP);\n*/\n//End of circuit(s) for vunit: inline\n\n\n//*****************************************************************************\n// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n\n//RESET_POLARITY_SYMBOL, set to ! (or blank) for active low (high)\n`define AKRPS ! // ###MBAC###\n\n`timescale 1 ps / 1 ps // ###MBAC###\n\n//Assertion circuit for vunit: inline\n//vunit is bound to module: Axi4PC\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_protocol_checker_v1_1_12_axi4pc_asr_inline (Axi4PC_asr_inline_out, reset, AWVALID, AWBURST, AwAddrIncr, AWADDR, ACLK, AlignMaskW, AWLEN, AWLOCK, AWCACHE, AwSizeInBits, ARESETn, AWREADY, AWID, AWPROT, AWSIZE, AWQOS, AWREGION, i_RecommendOn, i_RecMaxWaitOn, WriteDataNumError, BStrbError, WVALID, WREADY, WDATA, WLAST, WSTRB, BrespErrorLast, BrespExokError, BVALID, BrespErrorLead, BREADY, BID, BRESP, ARVALID, ARBURST, ArAddrIncr, ARADDR, AlignMaskR, ARLEN, ARLOCK, ARCACHE, ArSizeInBits, ARREADY, ARID, ARPROT, ARSIZE, ARQOS, ARREGION, RVALID, RREADY, ArCountPending, ArLenPending, RLAST, RidMatch, RRESP, ArExclPending, RDATA, RID, CSYSREQ, CSYSACK, ExclMask, ExclReadAddr, ExclAwMatch, ExclAddr, ExclSize, ExclLen, ExclBurst, ExclCache, ExclProt, ExclRegion, ArLenInBytes, ExclReadData, AWUSER, WUSER, BUSER, ARUSER, RUSER); // ###MBAC###\n  parameter DATA_WIDTH = 64;\n  parameter ID_WIDTH = 4;\n  parameter AWUSER_WIDTH = 32;\n  parameter WUSER_WIDTH = 32;\n  parameter BUSER_WIDTH = 32;\n  parameter ARUSER_WIDTH = 32;\n  parameter RUSER_WIDTH = 32;\n  parameter MAXRBURSTS = 16;\n  parameter MAXWBURSTS = 16;\n  parameter ADDR_WIDTH = 32;\n  parameter EXMON_WIDTH = 4;\n  parameter DATA_MAX = DATA_WIDTH - 1; // ###MBAC###\n  parameter ADDR_MAX = ADDR_WIDTH - 1;\n  parameter STRB_WIDTH = DATA_WIDTH / 8;\n  parameter STRB_MAX = STRB_WIDTH - 1;\n  parameter ID_MAX = ID_WIDTH ? ID_WIDTH - 1 : 0;\n  parameter EXMON_MAX = EXMON_WIDTH - 1;\n  parameter EXMON_HI = {EXMON_WIDTH{1'b1}};\n  parameter AWUSER_MAX = AWUSER_WIDTH ? AWUSER_WIDTH - 1 : 0; // ###MBAC###\n  parameter WUSER_MAX = WUSER_WIDTH ? WUSER_WIDTH - 1 : 0;\n  parameter BUSER_MAX = BUSER_WIDTH ? BUSER_WIDTH - 1 : 0;\n  parameter ARUSER_MAX = ARUSER_WIDTH ? ARUSER_WIDTH - 1 : 0;\n  parameter RUSER_MAX = RUSER_WIDTH ? RUSER_WIDTH - 1 : 0;\n  parameter MAX_AW_WAITS = 16;\n  parameter MAX_AR_WAITS = 16;\n  parameter MAX_W_WAITS  = 16;\n  parameter MAX_R_WAITS  = 16;\n  parameter MAX_B_WAITS  = 16;\n  output [87:1] Axi4PC_asr_inline_out;\n  input reset, AWVALID, ACLK, AWLOCK, ARESETn, AWREADY, i_RecommendOn, i_RecMaxWaitOn, WriteDataNumError, BStrbError, WVALID, WREADY, WLAST, BrespErrorLast, BrespExokError, BVALID, BrespErrorLead, BREADY, ARVALID, ARLOCK, ARREADY, RVALID, RREADY, RLAST, ArExclPending, CSYSREQ, CSYSACK, ExclAwMatch; // ###MBAC###\n  input [1:0] AWBURST;\n  input [ADDR_MAX:0] AwAddrIncr;\n  input [ADDR_MAX:0] AWADDR;\n  input [6:0] AlignMaskW;\n  input [7:0] AWLEN;\n  input [3:0] AWCACHE;\n  input [10:0] AwSizeInBits;\n  input [ID_MAX:0] AWID;\n  input [2:0] AWPROT;\n  input [2:0] AWSIZE;\n  input [3:0] AWQOS;\n  input [3:0] AWREGION;\n  input [DATA_MAX:0] WDATA; // ###MBAC###\n  input [STRB_MAX:0] WSTRB;\n  input [ID_MAX:0] BID; // ###MBAC###\n  input [1:0] BRESP;\n  input [1:0] ARBURST;\n  input [ADDR_MAX:0] ArAddrIncr;\n  input [ADDR_MAX:0] ARADDR;\n  input [6:0] AlignMaskR;\n  input [7:0] ARLEN;\n  input [3:0] ARCACHE;\n  input [10:0] ArSizeInBits;\n  input [ID_MAX:0] ARID;\n  input [2:0] ARPROT;\n  input [2:0] ARSIZE;\n  input [3:0] ARQOS;\n  input [3:0] ARREGION;\n  input [8:0] ArCountPending;\n  input [8:0] ArLenPending;\n  input [31:0] RidMatch;\n  input [1:0] RRESP;\n  input [DATA_MAX:0] RDATA; // ###MBAC###\n  input [ID_MAX:0] RID;\n  input [14:0] ExclMask;\n// ###MBAC###  input [EXMON_MAX:0] ExclAwId;\n// ###MBAC###  input [ADDR_MAX:0] ExclAddr [EXMON_HI:0];\n// ###MBAC###  input [2:0] ExclSize [EXMON_HI:0];\n// ###MBAC###  input [7:0] ExclLen [EXMON_HI:0];\n// ###MBAC###  input [1:0] ExclBurst [EXMON_HI:0];\n// ###MBAC###  input [3:0] ExclCache [EXMON_HI:0];\n// ###MBAC###  input [2:0] ExclProt [EXMON_HI:0];\n// ###MBAC###  input [3:0] ExclRegion [EXMON_HI:0];\n  input [ADDR_MAX:0] ExclAddr;\n  input [2:0] ExclSize;\n  input [7:0] ExclLen;\n  input [1:0] ExclBurst;\n  input [3:0] ExclCache;\n  input [2:0] ExclProt;\n  input [3:0] ExclRegion;\n  input ExclReadAddr;\n  input ExclReadData;\n// ###MBAC###\n  input [15:0] ArLenInBytes;\n  input [AWUSER_MAX:0] AWUSER; // ###MBAC###\n  input [WUSER_MAX:0] WUSER;\n  input [BUSER_MAX:0] BUSER;\n  input [ARUSER_MAX:0] ARUSER;\n  input [RUSER_MAX:0] RUSER;\n// ###MBAC###  input [31:0] RIndex;\n// ###MBAC###  input [31:0] WIndex;\n\n  function integer f_clogb2 (input integer size);\n    integer s;\n    begin\n      s = size;\n      s = s - 1;\n      for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)\n            s = s >> 1;\n    end\n  endfunction // clogb2\n\n  wire [2:0] s1s;\n  reg [2:0] s1sq;\n  reg [ADDR_MAX:0] s2;\n  wire [2:0] s4s;\n  reg [2:0] s4sq;\n  reg [1:0] s5;\n  wire [2:0] s7s;\n  reg [2:0] s7sq;\n  reg [3:0] s8;\n  wire [2:0] s10s;\n  reg [2:0] s10sq;\n  reg [ID_MAX:0] s11;\n  wire [2:0] s13s;\n  reg [2:0] s13sq;\n  reg [7:0] s14;\n  wire [2:0] s16s;\n  reg [2:0] s16sq;\n  wire [2:0] s19s;\n  reg [2:0] s19sq;\n  reg [2:0] s20;\n  wire [2:0] s22s;\n  reg [2:0] s22sq;\n  reg [2:0] s23;\n  wire [2:0] s25s;\n  reg [2:0] s25sq;\n  reg [3:0] s26;\n  wire [2:0] s28s;\n  reg [2:0] s28sq;\n  reg [3:0] s29;\n  wire [2:0] s31s;\n  reg [2:0] s31sq;\n  wire [2:0] s32s;\n  reg [2:0] s32sq;\n  wire [2:0] s34s;\n  reg [2:0] s34sq;\n  reg [DATA_MAX:0] s35;\n  wire [2:0] s37s;\n  reg [2:0] s37sq;\n  wire [2:0] s40s;\n  reg [2:0] s40sq;\n  reg [STRB_MAX:0] s41;\n  wire [2:0] s43s;\n  reg [2:0] s43sq;\n  wire [2:0] s44s;\n  reg [2:0] s44sq;\n  wire [2:0] s46s;\n  reg [2:0] s46sq;\n  reg [ID_MAX:0] s47;\n  wire [2:0] s49s;\n  reg [2:0] s49sq;\n  reg [1:0] s50;\n  wire [2:0] s52s;\n  reg [2:0] s52sq;\n  wire [2:0] s53s;\n  reg [2:0] s53sq;\n  wire [2:0] s55s;\n  reg [2:0] s55sq;\n  reg [ADDR_MAX:0] s56;\n  wire [2:0] s58s;\n  reg [2:0] s58sq;\n  reg [1:0] s59;\n  wire [2:0] s61s;\n  reg [2:0] s61sq;\n  reg [3:0] s62;\n  wire [2:0] s64s;\n  reg [2:0] s64sq;\n  reg [ID_MAX:0] s65;\n  wire [2:0] s67s;\n  reg [2:0] s67sq;\n  reg [7:0] s68;\n  wire [2:0] s70s;\n  reg [2:0] s70sq;\n  wire [2:0] s73s;\n  reg [2:0] s73sq;\n  reg [2:0] s74;\n  wire [2:0] s76s;\n  reg [2:0] s76sq;\n  reg [2:0] s77;\n  wire [2:0] s79s;\n  reg [2:0] s79sq;\n  reg [3:0] s80;\n  wire [2:0] s82s;\n  reg [2:0] s82sq;\n  reg [3:0] s83;\n  wire [2:0] s85s;\n  reg [2:0] s85sq;\n  wire [2:0] s86s;\n  reg [2:0] s86sq;\n  wire [2:0] s88s;\n  reg [2:0] s88sq;\n  reg [DATA_MAX:0] s89;\n  wire [2:0] s91s;\n  reg [2:0] s91sq;\n  reg [ID_MAX:0] s92;\n  wire [2:0] s94s;\n  reg [2:0] s94sq;\n  wire [2:0] s97s;\n  reg [2:0] s97sq;\n  reg [1:0] s98;\n  wire [2:0] s100s;\n  reg [2:0] s100sq;\n  wire [2:0] s101s;\n  reg [2:0] s101sq;\n  reg [31:0] s103;\n  wire [2:0] s105s;\n  reg [2:0] s105sq;\n  reg [WUSER_MAX:0] s106;\n  wire [2:0] s108s;\n  reg [2:0] s108sq;\n  reg [BUSER_MAX:0] s109;\n  wire [2:0] s111s;\n  reg [2:0] s111sq;\n  reg [ARUSER_MAX:0] s112;\n  wire [2:0] s114s;\n  reg [2:0] s114sq;\n  reg [RUSER_MAX:0] s115;\n  wire [2:0] s117s;\n  reg [2:0] s117sq;\n  reg [AWUSER_MAX:0] s118;\n  reg [WUSER_MAX:0] s120;\n  reg [BUSER_MAX:0] s122;\n  reg [ARUSER_MAX:0] s124;\n  reg [RUSER_MAX:0] s126;\n  reg [ID_MAX:0] s128;\n  reg [ID_MAX:0] s130;\n  reg [ID_MAX:0] s132;\n  reg [ID_MAX:0] s134;\n  wire s3, s6, s9, s12, s15, s18, s21, s24, s27, s30, s36, s39, s42, s48, s51, s57, s60, s63, s66, s69, s72, s75, s78, s81, s84, s90, s93, s96, s99, s104, s107, s110, s113, s116, s119, s121, s123, s125, s127, s129, s131, s133, s135;\n  reg ASR_1, ASR_2, ASR_3, ASR_4, ASR_5, ASR_6, ASR_7, ASR_8, ASR_9, ASR_10, ASR_11, ASR_12, ASR_13, ASR_14, s17, ASR_15, ASR_16, ASR_17, ASR_18, ASR_19, ASR_20, ASR_21, ASR_22, ASR_23, ASR_24, ASR_25, s38, ASR_26, ASR_27, ASR_28, ASR_29, ASR_30, ASR_31, ASR_32, ASR_33, ASR_34, ASR_35, ASR_36, ASR_37, ASR_38, ASR_39, ASR_40, ASR_41, ASR_42, ASR_43, ASR_44, ASR_45, ASR_46, ASR_47, ASR_48, ASR_49, ASR_50, ASR_51, s71, ASR_52, ASR_53, ASR_54, ASR_55, ASR_56, ASR_57, ASR_58, ASR_59, ASR_60, ASR_61, ASR_62, ASR_63, ASR_64, s95, ASR_65, ASR_66, ASR_67, ASR_68, ASR_69, ASR_70, ASR_71, ASR_72, ASR_73, ASR_74, ASR_75, ASR_76, ASR_77, ASR_78, ASR_79, ASR_80, ASR_81, ASR_82, ASR_83, ASR_84, ASR_85, ASR_86, ASR_87;\n\n  assign Axi4PC_asr_inline_out={ASR_87, ASR_86, ASR_85, ASR_84, ASR_83, ASR_82, ASR_81, ASR_80, ASR_79, ASR_78, ASR_77, ASR_76, ASR_75, ASR_74, ASR_73, ASR_72, ASR_71, ASR_70, ASR_69, ASR_68, ASR_67, ASR_66, ASR_65, ASR_64, ASR_63, ASR_62, ASR_61, ASR_60, ASR_59, ASR_58, ASR_57, ASR_56, ASR_55, ASR_54, ASR_53, ASR_52, ASR_51, ASR_50, ASR_49, ASR_48, ASR_47, ASR_46, ASR_45, ASR_44, ASR_43, ASR_42, ASR_41, ASR_40, ASR_39, ASR_38, ASR_37, ASR_36, ASR_35, ASR_34, ASR_33, ASR_32, ASR_31, ASR_30, ASR_29, ASR_28, ASR_27, ASR_26, ASR_25, ASR_24, ASR_23, ASR_22, ASR_21, ASR_20, ASR_19, ASR_18, ASR_17, ASR_16, ASR_15, ASR_14, ASR_13, ASR_12, ASR_11, ASR_10, ASR_9, ASR_8, ASR_7, ASR_6, ASR_5, ASR_4, ASR_3, ASR_2, ASR_1};\n\nlocalparam L_AW_WAIT_WIDTH = f_clogb2(MAX_AW_WAITS+1);\nlocalparam L_AR_WAIT_WIDTH = f_clogb2(MAX_AW_WAITS+1);\nlocalparam L_W_WAIT_WIDTH  = f_clogb2(MAX_W_WAITS+1);\nlocalparam L_R_WAIT_WIDTH  = f_clogb2(MAX_R_WAITS+1);\nlocalparam L_B_WAIT_WIDTH  = f_clogb2(MAX_B_WAITS+1);\n\n\n  //---------------\n  //ASR_1 : assert property ( @(posedge ACLK) ( AWVALID & ( AWBURST == 2'b1 ) |-> ( AwAddrIncr[ADDR_MAX:12] == AWADDR[ADDR_MAX:12] ) ) );\n  //---------------\n  reg [ADDR_MAX-12:0] AwAddrIncr_q1;\n  reg [ADDR_MAX-12:0] AWADDR_q1;\n  reg                 asr_1_ctrl;\n  always @(posedge ACLK) begin\n    AwAddrIncr_q1 <= AwAddrIncr[ADDR_MAX:12];\n    AWADDR_q1     <= AWADDR[ADDR_MAX:12];\n    asr_1_ctrl   <= (AWVALID & ( (AWBURST == 2'b1) ));\n  end\n\n  always @(posedge ACLK) if (`AKRPS reset) ASR_1<=0; else\n    ASR_1 <= asr_1_ctrl && !(AwAddrIncr_q1 == AWADDR_q1);\n\n  //---------------\n  //ASR_2 : assert property ( @(posedge ACLK) ( AWVALID & ( AWBURST == 2'b10 ) |-> ( ( AWADDR[6:0] & AlignMaskW ) == AWADDR[6:0] ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_2<=0; else\n    ASR_2 <= (((AWVALID & ( (AWBURST == 2'b10) )) && !((( (AWADDR[6:0] & AlignMaskW) ) == AWADDR[6:0]))));\n\n  //---------------\n  //ASR_3 : assert property ( @(posedge ACLK) ( AWVALID |-> ( AWBURST != 2'b11 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_3<=0; else\n    ASR_3 <= ((AWVALID && !((AWBURST != 2'b11))));\n\n  //---------------\n  //ASR_4 : assert property ( @(posedge ACLK) ( AWVALID & AWLEN > 8'b1111 |-> ( AWLOCK != 1'b1 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_4<=0; else\n    ASR_4 <= (((AWVALID & (AWLEN > 8'b1111)) && !((AWLOCK != 1'b1))));\n\n  //---------------\n  //ASR_5 : assert property ( @(posedge ACLK) ( AWVALID & ~ AWCACHE[1] |-> ( AWCACHE[3:2] == 2'b0 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_5<=0; else\n    ASR_5 <= (((AWVALID & (~ AWCACHE[1])) && !((AWCACHE[3:2] == 2'b0))));\n\n  //---------------\n  //ASR_6 : assert property ( @(posedge ACLK) ( AWVALID & AWLEN > 8'b1111 |-> ( AWBURST != 2'b0 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_6<=0; else\n    ASR_6 <= (((AWVALID & (AWLEN > 8'b1111)) && !((AWBURST != 2'b0))));\n\n  //---------------\n  //ASR_7 : assert property ( @(posedge ACLK) ( AWVALID & ( AWBURST == 2'b10 ) |-> ( AWLEN == 8'b1 || AWLEN == 8'b11 || AWLEN == 8'b111 || AWLEN == 8'b1111 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_7<=0; else\n    ASR_7 <= (((AWVALID & ( (AWBURST == 2'b10) )) && !(((((AWLEN == 8'b1) || (AWLEN == 8'b11)) || (AWLEN == 8'b111)) || (AWLEN == 8'b1111)))));\n\n  //---------------\n  //ASR_8 : assert property ( @(posedge ACLK) ( AWVALID |-> ( AwSizeInBits <= DATA_WIDTH ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_8<=0; else\n    ASR_8 <= ((AWVALID && !((AwSizeInBits <= DATA_WIDTH))));\n\n  //---------------\n  //ASR_9 : assert property ( @(posedge ACLK) ( ! ( ARESETn ) ##1 ARESETn |-> ! AWVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s1sq<=3'h4; else\n    s1sq<=s1s;\n  assign s1s={1'b1,\n    !(ARESETn),\n    (s1sq[1] && (ARESETn && AWVALID))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_9<=0; else\n    ASR_9 <= (s1s[0]);\n\n  //---------------\n  //ASR_10 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWADDR) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s2<=AWADDR;\n//  assign s3 = s2 == AWADDR;\n//  always @(posedge ACLK) if (`AKRPS reset) s4sq<=3'h4; else\n//    s4sq<=s4s;\n//  assign s4s={1'b1,\n//    ((ARESETn & AWVALID) & (! AWREADY)),\n//    (s4sq[1] && (ARESETn && !(s3)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_10<=0; else\n//    ASR_10 <= (s4s[0]);\nlocalparam integer L_NUM_AWADDR_BYTES       = ((ADDR_WIDTH + 7) / 8);\nlocalparam integer L_NUM_AWADDR_BYTE_LANES  = ((L_NUM_AWADDR_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_AWADDR_EQ_LANES    = (L_NUM_AWADDR_BYTE_LANES / 8);\nlocalparam integer L_NUM_AWADDR_AND1_LANES  = (L_NUM_AWADDR_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_AWADDR_AND2_LANES  = (L_NUM_AWADDR_AND1_LANES + 7) / 8;\n\nreg   [ADDR_WIDTH - 1:0]  AWADDR_q;\nreg   [4:0]               s_AWADDR_sq;\nwire  [4:0]               s_AWADDR_s;\nwire                      s_AWADDR_sqaa;\n\nreg [(8*L_NUM_AWADDR_EQ_LANES)-1:0]    AWADDR_eq;\nreg [(8*L_NUM_AWADDR_AND1_LANES)-1:0]  AWADDR_stage_1_eq;\nreg [(8*L_NUM_AWADDR_AND2_LANES)-1:0]  AWADDR_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_AWADDR_sq<=5'h00; \n    ASR_10 <=0;\n  end else begin\n    s_AWADDR_sq<=s_AWADDR_s;\n    ASR_10 <= (s_AWADDR_s[0]);\n  end\nend\n\nassign s_AWADDR_s={\n  (((ARESETn & AWVALID) & (! AWREADY))),\n  (s_AWADDR_sq[4] && ARESETn),\n  (s_AWADDR_sq[3]),\n  (s_AWADDR_sq[2]),\n  (s_AWADDR_sq[1] & !(s_AWADDR_sqaa))\n  };\n\nassign s_AWADDR_sqaa = &AWADDR_stage_2_eq;\n\nwire  [(L_NUM_AWADDR_BYTES*8)-1:0]      AWADDR_expand;\nwire  [(L_NUM_AWADDR_BYTES*8)-1:0]      AWADDRsqa_expand;\ngenvar AWADDR_bit;\ngenerate\n  ///////////////////////////////////////////////////////////////////////////////////////////\n  //Expand the AWADDR up to the nearest byte\n  for (AWADDR_bit = 0; AWADDR_bit < (L_NUM_AWADDR_BYTES * 8); AWADDR_bit = AWADDR_bit + 1) begin : AWADDR_BIT_LOOP\n    if (AWADDR_bit < ADDR_WIDTH) begin : VAL\n      assign AWADDR_expand[AWADDR_bit] = AWADDR[AWADDR_bit];\n      assign AWADDRsqa_expand[AWADDR_bit] = AWADDR_q[AWADDR_bit];\n    end else begin\n      assign AWADDR_expand[AWADDR_bit] = 1'b0;\n      assign AWADDRsqa_expand[AWADDR_bit] = 1'b0;\n    end\n  end\nendgenerate\n\ninteger AWADDR_bc;\ninteger AWADDR_stage_1;\ninteger AWADDR_stage_2;\n\nalways @(posedge ACLK) begin\n  AWADDR_q<=AWADDR;\n\n  for (AWADDR_bc = 0; AWADDR_bc < L_NUM_AWADDR_EQ_LANES*8; AWADDR_bc = AWADDR_bc + 1) begin : AWADDR_BC_LOOP\n    if (AWADDR_bc < L_NUM_AWADDR_BYTES) begin\n      AWADDR_eq[AWADDR_bc] <= AWADDR_expand[AWADDR_bc*8 +:8] == AWADDRsqa_expand[AWADDR_bc*8 +: 8];\n    end else begin\n      AWADDR_eq[AWADDR_bc] <= 1'b1;\n    end\n  end\n\n  for (AWADDR_stage_1 = 0; AWADDR_stage_1 < L_NUM_AWADDR_AND1_LANES * 8;AWADDR_stage_1 = AWADDR_stage_1 + 1) begin : AWADDR_S1\n    if (AWADDR_stage_1 < L_NUM_AWADDR_EQ_LANES) begin\n      AWADDR_stage_1_eq[AWADDR_stage_1] <= &AWADDR_eq[AWADDR_stage_1*8 +:8];\n    end else begin\n      AWADDR_stage_1_eq[AWADDR_stage_1] <= 1'b1;\n    end\n  end\n\n  for (AWADDR_stage_2 = 0; AWADDR_stage_2 < L_NUM_AWADDR_AND2_LANES * 8;AWADDR_stage_2 = AWADDR_stage_2 + 1) begin : AWADDR_S2\n    if (AWADDR_stage_2 < L_NUM_AWADDR_AND1_LANES) begin\n      AWADDR_stage_2_eq[AWADDR_stage_2] <= &AWADDR_stage_1_eq[AWADDR_stage_2*8 +:8];\n    end else begin\n      AWADDR_stage_2_eq[AWADDR_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n  //---------------\n  //ASR_11 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWBURST) ) );\n  //---------------\n  always @(posedge ACLK)\n    s5<=AWBURST;\n  assign s6 = s5 == AWBURST;\n  always @(posedge ACLK) if (`AKRPS reset) s7sq<=3'h4; else\n    s7sq<=s7s;\n  assign s7s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s7sq[1] && (ARESETn && !(s6)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_11<=0; else\n    ASR_11 <= (s7s[0]);\n\n  //---------------\n  //ASR_12 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWCACHE) ) );\n  //---------------\n  always @(posedge ACLK)\n    s8<=AWCACHE;\n  assign s9 = s8 == AWCACHE;\n  always @(posedge ACLK) if (`AKRPS reset) s10sq<=3'h4; else\n    s10sq<=s10s;\n  assign s10s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s10sq[1] && (ARESETn && !(s9)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_12<=0; else\n    ASR_12 <= (s10s[0]);\n\n  //---------------\n  //ASR_13 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWID) ) );\n  //---------------\n  always @(posedge ACLK)\n    s11<=AWID;\n  assign s12 = s11 == AWID;\n  always @(posedge ACLK) if (`AKRPS reset) s13sq<=3'h4; else\n    s13sq<=s13s;\n  assign s13s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s13sq[1] && (ARESETn && !(s12)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_13<=0; else\n    ASR_13 <= (s13s[0]);\n\n  //---------------\n  //ASR_14 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWLEN) ) );\n  //---------------\n  always @(posedge ACLK)\n    s14<=AWLEN;\n  assign s15 = s14 == AWLEN;\n  always @(posedge ACLK) if (`AKRPS reset) s16sq<=3'h4; else\n    s16sq<=s16s;\n  assign s16s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s16sq[1] && (ARESETn && !(s15)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_14<=0; else\n    ASR_14 <= (s16s[0]);\n\n  //---------------\n  //ASR_15 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWLOCK) ) );\n  //---------------\n  always @(posedge ACLK)\n    s17<=AWLOCK;\n  assign s18 = s17 == AWLOCK;\n  always @(posedge ACLK) if (`AKRPS reset) s19sq<=3'h4; else\n    s19sq<=s19s;\n  assign s19s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s19sq[1] && (ARESETn && !(s18)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_15<=0; else\n    ASR_15 <= (s19s[0]);\n\n  //---------------\n  //ASR_16 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWPROT) ) );\n  //---------------\n  always @(posedge ACLK)\n    s20<=AWPROT;\n  assign s21 = s20 == AWPROT;\n  always @(posedge ACLK) if (`AKRPS reset) s22sq<=3'h4; else\n    s22sq<=s22s;\n  assign s22s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s22sq[1] && (ARESETn && !(s21)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_16<=0; else\n    ASR_16 <= (s22s[0]);\n\n  //---------------\n  //ASR_17 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWSIZE) ) );\n  //---------------\n  always @(posedge ACLK)\n    s23<=AWSIZE;\n  assign s24 = s23 == AWSIZE;\n  always @(posedge ACLK) if (`AKRPS reset) s25sq<=3'h4; else\n    s25sq<=s25s;\n  assign s25s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s25sq[1] && (ARESETn && !(s24)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_17<=0; else\n    ASR_17 <= (s25s[0]);\n\n  //---------------\n  //ASR_18 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWQOS) ) );\n  //---------------\n  always @(posedge ACLK)\n    s26<=AWQOS;\n  assign s27 = s26 == AWQOS;\n  always @(posedge ACLK) if (`AKRPS reset) s28sq<=3'h4; else\n    s28sq<=s28s;\n  assign s28s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s28sq[1] && (ARESETn && !(s27)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_18<=0; else\n    ASR_18 <= (s28s[0]);\n\n  //---------------\n  //ASR_19 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWREGION) ) );\n  //---------------\n  always @(posedge ACLK)\n    s29<=AWREGION;\n  assign s30 = s29 == AWREGION;\n  always @(posedge ACLK) if (`AKRPS reset) s31sq<=3'h4; else\n    s31sq<=s31s;\n  assign s31s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s31sq[1] && (ARESETn && !(s30)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_19<=0; else\n    ASR_19 <= (s31s[0]);\n\n  //---------------\n  //ASR_20 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> AWVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s32sq<=3'h4; else\n    s32sq<=s32s;\n  assign s32s={1'b1,\n    ((ARESETn & AWVALID) & (! AWREADY)),\n    (s32sq[1] && (ARESETn && !(AWVALID)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_20<=0; else\n    ASR_20 <= (s32s[0]);\n\n  //---------------\n  //ASR_21 : assert property ( @(posedge ACLK) ( ARESETn & i_RecommendOn & i_RecMaxWaitOn & ( AWVALID & ! AWREADY ) |-> ##[1:16] ( ! AWVALID | AWREADY ) ) );\n  //---------------\n\n  reg [L_AW_WAIT_WIDTH-1:0]  aw_cnt;\n  wire asr_21_set;\n\n  generate\n    if (MAX_AW_WAITS > 0) begin : gen_aw_wait\n      always @(posedge ACLK) begin\n        if (`AKRPS reset) begin\n          aw_cnt <= {L_AW_WAIT_WIDTH{1'b0}};\n        end else begin\n          //Valid, not ready, clken\n          if (((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) & ( AWVALID & ! AWREADY )) begin\n            aw_cnt <= aw_cnt + 1;\n          end else begin\n            aw_cnt <= {L_AW_WAIT_WIDTH{1'b0}};\n          end\n        end\n      end\n\n      assign asr_21_set = (aw_cnt == MAX_AW_WAITS) & (AWVALID & ! AWREADY);\n    end else begin : gen_no_aw_wait\n      assign asr_21_set = 1'b0;\n    end\n  endgenerate\n\n  always @(posedge ACLK) if (`AKRPS reset) ASR_21<=0; else\n    ASR_21 <= asr_21_set;\n\n  //---------------\n  //ASR_22 : assert property ( @(posedge ACLK) ( ARESETn |-> ~ WriteDataNumError ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_22<=0; else\n    ASR_22 <= ((ARESETn && WriteDataNumError));\n\n  //---------------\n  //ASR_23 : assert property ( @(posedge ACLK) ( ARESETn |-> ~ BStrbError ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_23<=0; else\n    ASR_23 <= ((ARESETn && BStrbError));\n\n  //---------------\n  //ASR_24 : assert property ( @(posedge ACLK) ( ! ( ARESETn ) ##1 ARESETn |-> ! WVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s34sq<=3'h4; else\n    s34sq<=s34s;\n  assign s34s={1'b1,\n    !(ARESETn),\n    (s34sq[1] && (ARESETn && WVALID))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_24<=0; else\n    ASR_24 <= (s34s[0]);\n\n  //---------------\n  //ASR_25 : assert property ( @(posedge ACLK) ( ARESETn & WVALID & ! WREADY ##1 ARESETn |-> $stable(WDATA) ) );\n//  //---------------\n//  always @(posedge ACLK)\n//    s35<=WDATA;\n//  assign s36 = s35 == WDATA;\n//  always @(posedge ACLK) if (`AKRPS reset) s37sq<=3'h4; else\n//    s37sq<=s37s;\n//  assign s37s={1'b1,\n//    ((ARESETn & WVALID) & (! WREADY)),\n//    (s37sq[1] && (ARESETn && !(s36)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_25<=0; else\n//    ASR_25 <= (s37s[0]);\n\nlocalparam integer L_NUM_WDATA_BYTES       = ((DATA_WIDTH + 7) / 8);\nlocalparam integer L_NUM_WDATA_BYTE_LANES  = ((L_NUM_WDATA_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_WDATA_EQ_LANES    = (L_NUM_WDATA_BYTE_LANES / 8);\nlocalparam integer L_NUM_WDATA_AND1_LANES  = (L_NUM_WDATA_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_WDATA_AND2_LANES  = (L_NUM_WDATA_AND1_LANES + 7) / 8;\n\nreg   [DATA_WIDTH - 1:0]  WDATA_q;\nreg   [4:0]               s_WDATA_sq;\nwire  [4:0]               s_WDATA_s;\nwire                      s_WDATA_sqaa;\n\nreg [(8*L_NUM_WDATA_EQ_LANES)-1:0]    WDATA_eq;\nreg [(8*L_NUM_WDATA_AND1_LANES)-1:0]  WDATA_stage_1_eq;\nreg [(8*L_NUM_WDATA_AND2_LANES)-1:0]  WDATA_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_WDATA_sq<=5'h00; \n    ASR_25 <=0;\n  end else begin\n    s_WDATA_sq<=s_WDATA_s;\n    ASR_25 <= (s_WDATA_s[0]);\n  end\nend\n\nassign s_WDATA_s={\n  (((ARESETn & WVALID) & (! WREADY))),\n  (s_WDATA_sq[4] && ARESETn),\n  (s_WDATA_sq[3]),\n  (s_WDATA_sq[2]),\n  (s_WDATA_sq[1] & !(s_WDATA_sqaa))\n  };\n\nassign s_WDATA_sqaa = &WDATA_stage_2_eq;\n\ninteger WDATA_bc;\ninteger WDATA_stage_1;\ninteger WDATA_stage_2;\n\nalways @(posedge ACLK) begin\n  WDATA_q<=WDATA;\n\n  for (WDATA_bc = 0; WDATA_bc < L_NUM_WDATA_EQ_LANES*8; WDATA_bc = WDATA_bc + 1) begin : WDATA_BC_LOOP\n    if (WDATA_bc < L_NUM_WDATA_BYTES) begin\n      WDATA_eq[WDATA_bc] <= WDATA_q[WDATA_bc*8 +:8] == WDATA[WDATA_bc*8 +: 8];\n    end else begin\n      WDATA_eq[WDATA_bc] <= 1'b1;\n    end\n  end\n\n  for (WDATA_stage_1 = 0; WDATA_stage_1 < L_NUM_WDATA_AND1_LANES * 8;WDATA_stage_1 = WDATA_stage_1 + 1) begin : WDATA_S1\n    if (WDATA_stage_1 < L_NUM_WDATA_EQ_LANES) begin\n      WDATA_stage_1_eq[WDATA_stage_1] <= &WDATA_eq[WDATA_stage_1*8 +:8];\n    end else begin\n      WDATA_stage_1_eq[WDATA_stage_1] <= 1'b1;\n    end\n  end\n\n  for (WDATA_stage_2 = 0; WDATA_stage_2 < L_NUM_WDATA_AND2_LANES * 8;WDATA_stage_2 = WDATA_stage_2 + 1) begin : WDATA_S2\n    if (WDATA_stage_2 < L_NUM_WDATA_AND1_LANES) begin\n      WDATA_stage_2_eq[WDATA_stage_2] <= &WDATA_stage_1_eq[WDATA_stage_2*8 +:8];\n    end else begin\n      WDATA_stage_2_eq[WDATA_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n\n  //---------------\n  //ASR_26 : assert property ( @(posedge ACLK) ( ARESETn & WVALID & ! WREADY ##1 ARESETn |-> $stable(WLAST) ) );\n  //---------------\n  always @(posedge ACLK)\n    s38<=WLAST;\n  assign s39 = s38 == WLAST;\n  always @(posedge ACLK) if (`AKRPS reset) s40sq<=3'h4; else\n    s40sq<=s40s;\n  assign s40s={1'b1,\n    ((ARESETn & WVALID) & (! WREADY)),\n    (s40sq[1] && (ARESETn && !(s39)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_26<=0; else\n    ASR_26 <= (s40s[0]);\n\n  //---------------\n  //ASR_27 : assert property ( @(posedge ACLK) ( ARESETn & WVALID & ! WREADY ##1 ARESETn |-> $stable(WSTRB) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s41<=WSTRB;\n//  assign s42 = s41 == WSTRB;\n//  always @(posedge ACLK) if (`AKRPS reset) s43sq<=3'h4; else\n//    s43sq<=s43s;\n//  assign s43s={1'b1,\n//    ((ARESETn & WVALID) & (! WREADY)),\n//    (s43sq[1] && (ARESETn && !(s42)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_27<=0; else\n//    ASR_27 <= (s43s[0]);\nlocalparam integer L_NUM_WSTRB_BYTES       = (((DATA_WIDTH/8) + 7) / 8);\nlocalparam integer L_NUM_WSTRB_BYTE_LANES  = ((L_NUM_WSTRB_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_WSTRB_EQ_LANES    = (L_NUM_WSTRB_BYTE_LANES / 8);\nlocalparam integer L_NUM_WSTRB_AND1_LANES  = (L_NUM_WSTRB_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_WSTRB_AND2_LANES  = (L_NUM_WSTRB_AND1_LANES + 7) / 8;\n\nreg   [(DATA_WIDTH/8) - 1:0] WSTRB_q;\nreg   [4:0]               s_WSTRB_sq;\nwire  [4:0]               s_WSTRB_s;\nwire                      s_WSTRB_sqaa;\n\nreg [(8*L_NUM_WSTRB_EQ_LANES)-1:0]    WSTRB_eq;\nreg [(8*L_NUM_WSTRB_AND1_LANES)-1:0]  WSTRB_stage_1_eq;\nreg [(8*L_NUM_WSTRB_AND2_LANES)-1:0]  WSTRB_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_WSTRB_sq<=5'h00; \n    ASR_27 <=0;\n  end else begin\n    s_WSTRB_sq<=s_WSTRB_s;\n    ASR_27 <= (s_WSTRB_s[0]);\n  end\nend\n\nassign s_WSTRB_s={\n  (((ARESETn & WVALID) & (! WREADY))),\n  (s_WSTRB_sq[4] && ARESETn),\n  (s_WSTRB_sq[3]),\n  (s_WSTRB_sq[2]),\n  (s_WSTRB_sq[1] & !(s_WSTRB_sqaa))\n  };\n\nassign s_WSTRB_sqaa = &WSTRB_stage_2_eq;\n\nwire  [(L_NUM_WSTRB_BYTES*8)-1:0]      WSTRB_expand;\nwire  [(L_NUM_WSTRB_BYTES*8)-1:0]      WSTRBsqa_expand;\ngenvar WSTRB_bit;\ngenerate\n  ///////////////////////////////////////////////////////////////////////////////////////////\n  //Expand the WSTRB up to the nearest byte\n  for (WSTRB_bit = 0; WSTRB_bit < (L_NUM_WSTRB_BYTES * 8); WSTRB_bit = WSTRB_bit + 1) begin : WSTRB_BIT_LOOP\n    if (WSTRB_bit < (DATA_WIDTH/8)) begin : VAL\n      assign WSTRB_expand[WSTRB_bit] = WSTRB[WSTRB_bit];\n      assign WSTRBsqa_expand[WSTRB_bit] = WSTRB_q[WSTRB_bit];\n    end else begin\n      assign WSTRB_expand[WSTRB_bit] = 1'b0;\n      assign WSTRBsqa_expand[WSTRB_bit] = 1'b0;\n    end\n  end\nendgenerate\n\ninteger WSTRB_bc;\ninteger WSTRB_stage_1;\ninteger WSTRB_stage_2;\n\nalways @(posedge ACLK) begin\n  WSTRB_q<=WSTRB;\n\n  for (WSTRB_bc = 0; WSTRB_bc < L_NUM_WSTRB_EQ_LANES*8; WSTRB_bc = WSTRB_bc + 1) begin : WSTRB_BC_LOOP\n    if (WSTRB_bc < L_NUM_WSTRB_BYTES) begin\n      WSTRB_eq[WSTRB_bc] <= WSTRB_expand[WSTRB_bc*8 +:8] == WSTRBsqa_expand[WSTRB_bc*8 +: 8];\n    end else begin\n      WSTRB_eq[WSTRB_bc] <= 1'b1;\n    end\n  end\n\n  for (WSTRB_stage_1 = 0; WSTRB_stage_1 < L_NUM_WSTRB_AND1_LANES * 8;WSTRB_stage_1 = WSTRB_stage_1 + 1) begin : WSTRB_S1\n    if (WSTRB_stage_1 < L_NUM_WSTRB_EQ_LANES) begin\n      WSTRB_stage_1_eq[WSTRB_stage_1] <= &WSTRB_eq[WSTRB_stage_1*8 +:8];\n    end else begin\n      WSTRB_stage_1_eq[WSTRB_stage_1] <= 1'b1;\n    end\n  end\n\n  for (WSTRB_stage_2 = 0; WSTRB_stage_2 < L_NUM_WSTRB_AND2_LANES * 8;WSTRB_stage_2 = WSTRB_stage_2 + 1) begin : WSTRB_S2\n    if (WSTRB_stage_2 < L_NUM_WSTRB_AND1_LANES) begin\n      WSTRB_stage_2_eq[WSTRB_stage_2] <= &WSTRB_stage_1_eq[WSTRB_stage_2*8 +:8];\n    end else begin\n      WSTRB_stage_2_eq[WSTRB_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n  //---------------\n  //ASR_28 : assert property ( @(posedge ACLK) ( ARESETn & WVALID & ! WREADY ##1 ARESETn |-> WVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s44sq<=3'h4; else\n    s44sq<=s44s;\n  assign s44s={1'b1,\n    ((ARESETn & WVALID) & (! WREADY)),\n    (s44sq[1] && (ARESETn && !(WVALID)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_28<=0; else\n    ASR_28 <= (s44s[0]);\n\n  //---------------\n  //ASR_29 : assert property ( @(posedge ACLK) ( ARESETn & i_RecommendOn & i_RecMaxWaitOn & ( WVALID & ! WREADY ) |-> ##[1:16] ( ! WVALID | WREADY ) ) );\n  //---------------\n  reg [L_W_WAIT_WIDTH-1:0]  w_cnt;\n  wire asr_29_set;\n\n  generate\n    if (MAX_W_WAITS > 0) begin : gen_w_wait\n      always @(posedge ACLK) begin\n        if (`AKRPS reset) begin\n          w_cnt <= {L_W_WAIT_WIDTH{1'b0}};\n        end else begin\n          //Valid, not ready, clken\n          if (((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) & ( WVALID & ! WREADY )) begin\n            w_cnt <= w_cnt + 1;\n          end else begin\n            w_cnt <= {L_W_WAIT_WIDTH{1'b0}};\n          end\n        end\n      end\n\n      assign asr_29_set = (w_cnt == MAX_W_WAITS) & ( WVALID & ! WREADY );\n    end else begin : gen_no_w_wait\n      assign asr_29_set = 1'b0;\n    end\n  endgenerate\n\n  always @(posedge ACLK) if (`AKRPS reset) ASR_29<=0; else\n    ASR_29 <= asr_29_set;\n\n  //---------------\n  //ASR_30 : assert property ( @(posedge ACLK) ( ARESETn |-> ~ BrespErrorLast ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_30<=0; else\n    ASR_30 <= ((ARESETn && BrespErrorLast));\n\n  //---------------\n  //ASR_31 : assert property ( @(posedge ACLK) ( ARESETn |-> ~ BrespExokError ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_31<=0; else\n    ASR_31 <= ((ARESETn && BrespExokError));\n\n  //---------------\n  //ASR_32 : assert property ( @(posedge ACLK) ( ! ( ARESETn ) ##1 ARESETn |-> ! BVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s46sq<=3'h4; else\n    s46sq<=s46s;\n  assign s46s={1'b1,\n    !(ARESETn),\n    (s46sq[1] && (ARESETn && BVALID))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_32<=0; else\n    ASR_32 <= (s46s[0]);\n\n  //---------------\n  //ASR_33 : assert property ( @(posedge ACLK) ( ARESETn |-> ~ BrespErrorLead ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_33<=0; else\n    ASR_33 <= ((ARESETn && BrespErrorLead));\n\n  //---------------\n  //ASR_34 : assert property ( @(posedge ACLK) ( ARESETn & BVALID & ! BREADY ##1 ARESETn |-> $stable(BID) ) );\n  //---------------\n  always @(posedge ACLK)\n    s47<=BID;\n  assign s48 = s47 == BID;\n  always @(posedge ACLK) if (`AKRPS reset) s49sq<=3'h4; else\n    s49sq<=s49s;\n  assign s49s={1'b1,\n    ((ARESETn & BVALID) & (! BREADY)),\n    (s49sq[1] && (ARESETn && !(s48)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_34<=0; else\n    ASR_34 <= (s49s[0]);\n\n  //---------------\n  //ASR_35 : assert property ( @(posedge ACLK) ( ARESETn & BVALID & ! BREADY ##1 ARESETn |-> $stable(BRESP) ) );\n  //---------------\n  always @(posedge ACLK)\n    s50<=BRESP;\n  assign s51 = s50 == BRESP;\n  always @(posedge ACLK) if (`AKRPS reset) s52sq<=3'h4; else\n    s52sq<=s52s;\n  assign s52s={1'b1,\n    ((ARESETn & BVALID) & (! BREADY)),\n    (s52sq[1] && (ARESETn && !(s51)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_35<=0; else\n    ASR_35 <= (s52s[0]);\n\n  //---------------\n  //ASR_36 : assert property ( @(posedge ACLK) ( ARESETn & BVALID & ! BREADY ##1 ARESETn |-> BVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s53sq<=3'h4; else\n    s53sq<=s53s;\n  assign s53s={1'b1,\n    ((ARESETn & BVALID) & (! BREADY)),\n    (s53sq[1] && (ARESETn && !(BVALID)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_36<=0; else\n    ASR_36 <= (s53s[0]);\n\n  //---------------\n  //ASR_37 : assert property ( @(posedge ACLK) ( ARESETn & i_RecommendOn & i_RecMaxWaitOn & ( BVALID & ! BREADY ) |-> ##[1:16] ( ! BVALID | BREADY ) ) );\n  //---------------\n  reg [L_B_WAIT_WIDTH-1:0]  b_cnt;\n  wire asr_37_set;\n\n  generate\n    if (MAX_B_WAITS > 0) begin : gen_b_wait\n      always @(posedge ACLK) begin\n        if (`AKRPS reset) begin\n          b_cnt <= {L_B_WAIT_WIDTH{1'b0}};\n        end else begin\n          //Valid, not ready, clken\n          if (((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) & ( BVALID & ! BREADY )) begin\n            b_cnt <= b_cnt + 1;\n          end else begin\n            b_cnt <= {L_B_WAIT_WIDTH{1'b0}};\n          end\n        end\n      end\n\n      assign asr_37_set = (b_cnt == MAX_B_WAITS) & ( BVALID & ! BREADY );\n\n    end else begin : gen_no_b_wait\n      assign asr_37_set = 1'b0;\n    end\n  endgenerate\n\n  always @(posedge ACLK) if (`AKRPS reset) ASR_37<=0; else\n    ASR_37 <= asr_37_set;\n\n  //---------------\n  //ASR_38 : assert property ( @(posedge ACLK) ( ARVALID & ( ARBURST == 2'b1 ) |-> ( ArAddrIncr[ADDR_MAX:12] == ARADDR[ADDR_MAX:12] ) ) );\n  //---------------\n  reg [ADDR_MAX-12:0] ArAddrIncr_q1;\n  reg [ADDR_MAX-12:0] ARADDR_q1;\n  reg                 asr_38_ctrl;\n  \n  always @(posedge ACLK) begin\n    ArAddrIncr_q1 <= ArAddrIncr[ADDR_MAX:12];\n    ARADDR_q1     <= ARADDR[ADDR_MAX:12];\n    asr_38_ctrl   <= (ARVALID & ( (ARBURST == 2'b1) ));\n  end\n  \n  always @(posedge ACLK) if (`AKRPS reset) ASR_38<=0; else\n    ASR_38 <= asr_38_ctrl && !(ArAddrIncr_q1 == ARADDR_q1);\n\n  //---------------\n  //ASR_39 : assert property ( @(posedge ACLK) ( ARVALID & ( ARBURST == 2'b10 ) |-> ( ( ARADDR[6:0] & AlignMaskR ) == ARADDR[6:0] ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_39<=0; else\n    ASR_39 <= (((ARVALID & ( (ARBURST == 2'b10) )) && !((( (ARADDR[6:0] & AlignMaskR) ) == ARADDR[6:0]))));\n\n  //---------------\n  //ASR_40 : assert property ( @(posedge ACLK) ( ARVALID |-> ( ARBURST != 2'b11 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_40<=0; else\n    ASR_40 <= ((ARVALID && !((ARBURST != 2'b11))));\n\n  //---------------\n  //ASR_41 : assert property ( @(posedge ACLK) ( ARVALID & ARLEN > 8'b1111 |-> ( ARLOCK != 1'b1 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_41<=0; else\n    ASR_41 <= (((ARVALID & (ARLEN > 8'b1111)) && !((ARLOCK != 1'b1))));\n\n  //---------------\n  //ASR_42 : assert property ( @(posedge ACLK) ( ARVALID & ~ ARCACHE[1] |-> ( ARCACHE[3:2] == 2'b0 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_42<=0; else\n    ASR_42 <= (((ARVALID & (~ ARCACHE[1])) && !((ARCACHE[3:2] == 2'b0))));\n\n  //---------------\n  //ASR_43 : assert property ( @(posedge ACLK) ( ARVALID & ARLEN > 8'b1111 |-> ( ARBURST != 2'b0 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_43<=0; else\n    ASR_43 <= (((ARVALID & (ARLEN > 8'b1111)) && !((ARBURST != 2'b0))));\n\n  //---------------\n  //ASR_44 : assert property ( @(posedge ACLK) ( ARVALID & ( ARBURST == 2'b10 ) |-> ( ARLEN == 8'b1 || ARLEN == 8'b11 || ARLEN == 8'b111 || ARLEN == 8'b1111 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_44<=0; else\n    ASR_44 <= (((ARVALID & ( (ARBURST == 2'b10) )) && !(((((ARLEN == 8'b1) || (ARLEN == 8'b11)) || (ARLEN == 8'b111)) || (ARLEN == 8'b1111)))));\n\n  //---------------\n  //ASR_45 : assert property ( @(posedge ACLK) ( ARVALID |-> ( ArSizeInBits <= DATA_WIDTH ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_45<=0; else\n    ASR_45 <= ((ARVALID && !((ArSizeInBits <= DATA_WIDTH))));\n\n  //---------------\n  //ASR_46 : assert property ( @(posedge ACLK) ( ! ( ARESETn ) ##1 ARESETn |-> ! ARVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s55sq<=3'h4; else\n    s55sq<=s55s;\n  assign s55s={1'b1,\n    !(ARESETn),\n    (s55sq[1] && (ARESETn && ARVALID))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_46<=0; else\n    ASR_46 <= (s55s[0]);\n\n  //---------------\n  //ASR_47 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARADDR) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s56<=ARADDR;\n//  assign s57 = s56 == ARADDR;\n//  always @(posedge ACLK) if (`AKRPS reset) s58sq<=3'h4; else\n//    s58sq<=s58s;\n//  assign s58s={1'b1,\n//    ((ARESETn & ARVALID) & (! ARREADY)),\n//    (s58sq[1] && (ARESETn && !(s57)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_47<=0; else\n//    ASR_47 <= (s58s[0]);\nlocalparam integer L_NUM_ARADDR_BYTES       = ((ADDR_WIDTH + 7) / 8);\nlocalparam integer L_NUM_ARADDR_BYTE_LANES  = ((L_NUM_ARADDR_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_ARADDR_EQ_LANES    = (L_NUM_ARADDR_BYTE_LANES / 8);\nlocalparam integer L_NUM_ARADDR_AND1_LANES  = (L_NUM_ARADDR_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_ARADDR_AND2_LANES  = (L_NUM_ARADDR_AND1_LANES + 7) / 8;\n\nreg   [ADDR_WIDTH - 1:0] ARADDR_q;\nreg   [4:0]               s_ARADDR_sq;\nwire  [4:0]               s_ARADDR_s;\nwire                      s_ARADDR_sqaa;\n\nreg [(8*L_NUM_ARADDR_EQ_LANES)-1:0]    ARADDR_eq;\nreg [(8*L_NUM_ARADDR_AND1_LANES)-1:0]  ARADDR_stage_1_eq;\nreg [(8*L_NUM_ARADDR_AND2_LANES)-1:0]  ARADDR_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_ARADDR_sq<=5'h00; \n    ASR_47 <=0;\n  end else begin\n    s_ARADDR_sq<=s_ARADDR_s;\n    ASR_47 <= (s_ARADDR_s[0]);\n  end\nend\n\nassign s_ARADDR_s={\n  (((ARESETn & ARVALID) & (! ARREADY))),\n  (s_ARADDR_sq[4] && ARESETn),\n  (s_ARADDR_sq[3]),\n  (s_ARADDR_sq[2]),\n  (s_ARADDR_sq[1] & !(s_ARADDR_sqaa))\n  };\n\nassign s_ARADDR_sqaa = &ARADDR_stage_2_eq;\n\nwire  [(L_NUM_ARADDR_BYTES*8)-1:0]      ARADDR_expand;\nwire  [(L_NUM_ARADDR_BYTES*8)-1:0]      ARADDRsqa_expand;\ngenvar ARADDR_bit;\ngenerate\n  ///////////////////////////////////////////////////////////////////////////////////////////\n  //Expand the ARADDR up to the nearest byte\n  for (ARADDR_bit = 0; ARADDR_bit < (L_NUM_ARADDR_BYTES * 8); ARADDR_bit = ARADDR_bit + 1) begin : ARADDR_BIT_LOOP\n    if (ARADDR_bit < ADDR_WIDTH) begin : VAL\n      assign ARADDR_expand[ARADDR_bit] = ARADDR[ARADDR_bit];\n      assign ARADDRsqa_expand[ARADDR_bit] = ARADDR_q[ARADDR_bit];\n    end else begin\n      assign ARADDR_expand[ARADDR_bit] = 1'b0;\n      assign ARADDRsqa_expand[ARADDR_bit] = 1'b0;\n    end\n  end\nendgenerate\n\ninteger ARADDR_bc;\ninteger ARADDR_stage_1;\ninteger ARADDR_stage_2;\n\nalways @(posedge ACLK) begin\n  ARADDR_q<=ARADDR;\n\n  for (ARADDR_bc = 0; ARADDR_bc < L_NUM_ARADDR_EQ_LANES*8; ARADDR_bc = ARADDR_bc + 1) begin : ARADDR_BC_LOOP\n    if (ARADDR_bc < L_NUM_ARADDR_BYTES) begin\n      ARADDR_eq[ARADDR_bc] <= ARADDR_expand[ARADDR_bc*8 +:8] == ARADDRsqa_expand[ARADDR_bc*8 +: 8];\n    end else begin\n      ARADDR_eq[ARADDR_bc] <= 1'b1;\n    end\n  end\n\n  for (ARADDR_stage_1 = 0; ARADDR_stage_1 < L_NUM_ARADDR_AND1_LANES * 8;ARADDR_stage_1 = ARADDR_stage_1 + 1) begin : ARADDR_S1\n    if (ARADDR_stage_1 < L_NUM_ARADDR_EQ_LANES) begin\n      ARADDR_stage_1_eq[ARADDR_stage_1] <= &ARADDR_eq[ARADDR_stage_1*8 +:8];\n    end else begin\n      ARADDR_stage_1_eq[ARADDR_stage_1] <= 1'b1;\n    end\n  end\n\n  for (ARADDR_stage_2 = 0; ARADDR_stage_2 < L_NUM_ARADDR_AND2_LANES * 8;ARADDR_stage_2 = ARADDR_stage_2 + 1) begin : ARADDR_S2\n    if (ARADDR_stage_2 < L_NUM_ARADDR_AND1_LANES) begin\n      ARADDR_stage_2_eq[ARADDR_stage_2] <= &ARADDR_stage_1_eq[ARADDR_stage_2*8 +:8];\n    end else begin\n      ARADDR_stage_2_eq[ARADDR_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n  //---------------\n  //ASR_48 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARBURST) ) );\n  //---------------\n  always @(posedge ACLK)\n    s59<=ARBURST;\n  assign s60 = s59 == ARBURST;\n  always @(posedge ACLK) if (`AKRPS reset) s61sq<=3'h4; else\n    s61sq<=s61s;\n  assign s61s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s61sq[1] && (ARESETn && !(s60)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_48<=0; else\n    ASR_48 <= (s61s[0]);\n\n  //---------------\n  //ASR_49 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARCACHE) ) );\n  //---------------\n  always @(posedge ACLK)\n    s62<=ARCACHE;\n  assign s63 = s62 == ARCACHE;\n  always @(posedge ACLK) if (`AKRPS reset) s64sq<=3'h4; else\n    s64sq<=s64s;\n  assign s64s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s64sq[1] && (ARESETn && !(s63)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_49<=0; else\n    ASR_49 <= (s64s[0]);\n\n  //---------------\n  //ASR_50 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARID) ) );\n  //---------------\n  always @(posedge ACLK)\n    s65<=ARID;\n  assign s66 = s65 == ARID;\n  always @(posedge ACLK) if (`AKRPS reset) s67sq<=3'h4; else\n    s67sq<=s67s;\n  assign s67s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s67sq[1] && (ARESETn && !(s66)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_50<=0; else\n    ASR_50 <= (s67s[0]);\n\n  //---------------\n  //ASR_51 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARLEN) ) );\n  //---------------\n  always @(posedge ACLK)\n    s68<=ARLEN;\n  assign s69 = s68 == ARLEN;\n  always @(posedge ACLK) if (`AKRPS reset) s70sq<=3'h4; else\n    s70sq<=s70s;\n  assign s70s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s70sq[1] && (ARESETn && !(s69)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_51<=0; else\n    ASR_51 <= (s70s[0]);\n\n  //---------------\n  //ASR_52 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARLOCK) ) );\n  //---------------\n  always @(posedge ACLK)\n    s71<=ARLOCK;\n  assign s72 = s71 == ARLOCK;\n  always @(posedge ACLK) if (`AKRPS reset) s73sq<=3'h4; else\n    s73sq<=s73s;\n  assign s73s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s73sq[1] && (ARESETn && !(s72)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_52<=0; else\n    ASR_52 <= (s73s[0]);\n\n  //---------------\n  //ASR_53 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARPROT) ) );\n  //---------------\n  always @(posedge ACLK)\n    s74<=ARPROT;\n  assign s75 = s74 == ARPROT;\n  always @(posedge ACLK) if (`AKRPS reset) s76sq<=3'h4; else\n    s76sq<=s76s;\n  assign s76s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s76sq[1] && (ARESETn && !(s75)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_53<=0; else\n    ASR_53 <= (s76s[0]);\n\n  //---------------\n  //ASR_54 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARSIZE) ) );\n  //---------------\n  always @(posedge ACLK)\n    s77<=ARSIZE;\n  assign s78 = s77 == ARSIZE;\n  always @(posedge ACLK) if (`AKRPS reset) s79sq<=3'h4; else\n    s79sq<=s79s;\n  assign s79s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s79sq[1] && (ARESETn && !(s78)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_54<=0; else\n    ASR_54 <= (s79s[0]);\n\n  //---------------\n  //ASR_55 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARQOS) ) );\n  //---------------\n  always @(posedge ACLK)\n    s80<=ARQOS;\n  assign s81 = s80 == ARQOS;\n  always @(posedge ACLK) if (`AKRPS reset) s82sq<=3'h4; else\n    s82sq<=s82s;\n  assign s82s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s82sq[1] && (ARESETn && !(s81)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_55<=0; else\n    ASR_55 <= (s82s[0]);\n\n  //---------------\n  //ASR_56 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARREGION) ) );\n  //---------------\n  always @(posedge ACLK)\n    s83<=ARREGION;\n  assign s84 = s83 == ARREGION;\n  always @(posedge ACLK) if (`AKRPS reset) s85sq<=3'h4; else\n    s85sq<=s85s;\n  assign s85s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s85sq[1] && (ARESETn && !(s84)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_56<=0; else\n    ASR_56 <= (s85s[0]);\n\n  //---------------\n  //ASR_57 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> ARVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s86sq<=3'h4; else\n    s86sq<=s86s;\n  assign s86s={1'b1,\n    ((ARESETn & ARVALID) & (! ARREADY)),\n    (s86sq[1] && (ARESETn && !(ARVALID)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_57<=0; else\n    ASR_57 <= (s86s[0]);\n\n  //---------------\n  //ASR_58 : assert property ( @(posedge ACLK) ( ARESETn & i_RecommendOn & i_RecMaxWaitOn & ( ARVALID & ! ARREADY ) |-> ##[1:16] ( ! ARVALID | ARREADY ) ) );\n  //---------------\n  reg [L_AR_WAIT_WIDTH-1:0]  ar_cnt;\n  wire asr_58_set;\n\n  generate\n    if (MAX_AR_WAITS > 0) begin : gen_ar_wait\n      always @(posedge ACLK) begin\n        if (`AKRPS reset) begin\n          ar_cnt <= {L_AR_WAIT_WIDTH{1'b0}};\n        end else begin\n          //Valid, not ready, clken\n          if (((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) & ( ARVALID & ! ARREADY )) begin\n            ar_cnt <= ar_cnt + 1;\n          end else begin\n            ar_cnt <= {L_AR_WAIT_WIDTH{1'b0}};\n          end\n        end\n      end\n\n      assign asr_58_set = (ar_cnt == MAX_AR_WAITS) & ( ARVALID & ! ARREADY );\n\n    end else begin : gen_no_ar_wait\n      assign asr_58_set = 1'b0;\n    end\n  endgenerate\n\n  always @(posedge ACLK) if (`AKRPS reset) ASR_58<=0; else\n    ASR_58 <= asr_58_set;\n\n  //---------------\n  //ASR_59 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & RREADY |-> ( ( ( ArCountPending == ArLenPending ) & RLAST ) | ( ( ArCountPending != ArLenPending ) & ~ RLAST ) ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_59<=0; else\n    ASR_59 <= ((((ARESETn & RVALID) & RREADY) && !((( (( (ArCountPending == ArLenPending) ) & RLAST) ) | ( (( (ArCountPending != ArLenPending) ) & (~ RLAST)) )))));\n\n  //---------------\n  //ASR_60 : assert property ( @(posedge ACLK) ( ARESETn & RVALID |-> ( RidMatch > 0 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_60<=0; else\n    ASR_60 <= (((ARESETn & RVALID) && !((RidMatch > 0))));\n\n  //---------------\n  //ASR_61 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & RREADY & ( RRESP == 2'b1 ) |-> ( ArExclPending ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_61<=0; else\n    ASR_61 <= (((((ARESETn & RVALID) & RREADY) & ( (RRESP == 2'b1) )) && !(ArExclPending)));\n\n  //---------------\n  //ASR_62 : assert property ( @(posedge ACLK) ( ! ( ARESETn ) ##1 ARESETn |-> ! RVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s88sq<=3'h4; else\n    s88sq<=s88s;\n  assign s88s={1'b1,\n    !(ARESETn),\n    (s88sq[1] && (ARESETn && RVALID))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_62<=0; else\n    ASR_62 <= (s88s[0]);\n\n  //---------------\n  //ASR_63 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> $stable(RDATA) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s89<=RDATA;\n//  assign s90 = s89 == RDATA;\n//  always @(posedge ACLK) if (`AKRPS reset) s91sq<=3'h4; else\n//    s91sq<=s91s;\n//  assign s91s={1'b1,\n//    ((ARESETn & RVALID) & (! RREADY)),\n//    (s91sq[1] && (ARESETn && !(s90)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_63<=0; else\n//    ASR_63 <= (s91s[0]);\nlocalparam integer L_NUM_RDATA_BYTES       = ((DATA_WIDTH + 7) / 8);\nlocalparam integer L_NUM_RDATA_BYTE_LANES  = ((L_NUM_RDATA_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_RDATA_EQ_LANES    = (L_NUM_RDATA_BYTE_LANES / 8);\nlocalparam integer L_NUM_RDATA_AND1_LANES  = (L_NUM_RDATA_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_RDATA_AND2_LANES  = (L_NUM_RDATA_AND1_LANES + 7) / 8;\n\nreg   [DATA_WIDTH - 1:0]  RDATA_q;\nreg   [4:0]               s_RDATA_sq;\nwire  [4:0]               s_RDATA_s;\nwire                      s_RDATA_sqaa;\n\nreg [(8*L_NUM_RDATA_EQ_LANES)-1:0]    RDATA_eq;\nreg [(8*L_NUM_RDATA_AND1_LANES)-1:0]  RDATA_stage_1_eq;\nreg [(8*L_NUM_RDATA_AND2_LANES)-1:0]  RDATA_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_RDATA_sq<=5'h00; \n    ASR_63 <=0;\n  end else begin\n    s_RDATA_sq<=s_RDATA_s;\n    ASR_63 <= (s_RDATA_s[0]);\n  end\nend\n\nassign s_RDATA_s={\n  (((ARESETn & RVALID) & (! RREADY))),\n  (s_RDATA_sq[4] && ARESETn),\n  (s_RDATA_sq[3]),\n  (s_RDATA_sq[2]),\n  (s_RDATA_sq[1] & !(s_RDATA_sqaa))\n  };\n\nassign s_RDATA_sqaa = &RDATA_stage_2_eq;\n\ninteger RDATA_bc;\ninteger RDATA_stage_1;\ninteger RDATA_stage_2;\n\nalways @(posedge ACLK) begin\n  RDATA_q<=RDATA;\n\n  for (RDATA_bc = 0; RDATA_bc < L_NUM_RDATA_EQ_LANES*8; RDATA_bc = RDATA_bc + 1) begin : RDATA_BC_LOOP\n    if (RDATA_bc < L_NUM_RDATA_BYTES) begin\n      RDATA_eq[RDATA_bc] <= RDATA_q[RDATA_bc*8 +:8] == RDATA[RDATA_bc*8 +: 8];\n    end else begin\n      RDATA_eq[RDATA_bc] <= 1'b1;\n    end\n  end\n\n  for (RDATA_stage_1 = 0; RDATA_stage_1 < L_NUM_RDATA_AND1_LANES * 8;RDATA_stage_1 = RDATA_stage_1 + 1) begin : RDATA_S1\n    if (RDATA_stage_1 < L_NUM_RDATA_EQ_LANES) begin\n      RDATA_stage_1_eq[RDATA_stage_1] <= &RDATA_eq[RDATA_stage_1*8 +:8];\n    end else begin\n      RDATA_stage_1_eq[RDATA_stage_1] <= 1'b1;\n    end\n  end\n\n  for (RDATA_stage_2 = 0; RDATA_stage_2 < L_NUM_RDATA_AND2_LANES * 8;RDATA_stage_2 = RDATA_stage_2 + 1) begin : RDATA_S2\n    if (RDATA_stage_2 < L_NUM_RDATA_AND1_LANES) begin\n      RDATA_stage_2_eq[RDATA_stage_2] <= &RDATA_stage_1_eq[RDATA_stage_2*8 +:8];\n    end else begin\n      RDATA_stage_2_eq[RDATA_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n  //---------------\n  //ASR_64 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> $stable(RID) ) );\n  //---------------\n  always @(posedge ACLK)\n    s92<=RID;\n  assign s93 = s92 == RID;\n  always @(posedge ACLK) if (`AKRPS reset) s94sq<=3'h4; else\n    s94sq<=s94s;\n  assign s94s={1'b1,\n    ((ARESETn & RVALID) & (! RREADY)),\n    (s94sq[1] && (ARESETn && !(s93)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_64<=0; else\n    ASR_64 <= (s94s[0]);\n\n  //---------------\n  //ASR_65 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> $stable(RLAST) ) );\n  //---------------\n  always @(posedge ACLK)\n    s95<=RLAST;\n  assign s96 = s95 == RLAST;\n  always @(posedge ACLK) if (`AKRPS reset) s97sq<=3'h4; else\n    s97sq<=s97s;\n  assign s97s={1'b1,\n    ((ARESETn & RVALID) & (! RREADY)),\n    (s97sq[1] && (ARESETn && !(s96)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_65<=0; else\n    ASR_65 <= (s97s[0]);\n\n  //---------------\n  //ASR_66 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> $stable(RRESP) ) );\n  //---------------\n  always @(posedge ACLK)\n    s98<=RRESP;\n  assign s99 = s98 == RRESP;\n  always @(posedge ACLK) if (`AKRPS reset) s100sq<=3'h4; else\n    s100sq<=s100s;\n  assign s100s={1'b1,\n    ((ARESETn & RVALID) & (! RREADY)),\n    (s100sq[1] && (ARESETn && !(s99)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_66<=0; else\n    ASR_66 <= (s100s[0]);\n\n  //---------------\n  //ASR_67 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> RVALID ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) s101sq<=3'h4; else\n    s101sq<=s101s;\n  assign s101s={1'b1,\n    ((ARESETn & RVALID) & (! RREADY)),\n    (s101sq[1] && (ARESETn && !(RVALID)))};\n  always @(posedge ACLK) if (`AKRPS reset) ASR_67<=0; else\n    ASR_67 <= (s101s[0]);\n\n  //---------------\n  //ASR_68 : assert property ( @(posedge ACLK) ( ARESETn & i_RecommendOn & i_RecMaxWaitOn & ( RVALID & ! RREADY ) |-> ##[1:16] ( ! RVALID | RREADY ) ) );\n  //---------------\n  reg [L_R_WAIT_WIDTH-1:0]  r_cnt;\n  wire asr_68_set;\n\n  generate\n    if (MAX_R_WAITS > 0) begin : gen_r_wait\n      always @(posedge ACLK) begin\n        if (`AKRPS reset) begin\n          r_cnt <= {L_R_WAIT_WIDTH{1'b0}};\n        end else begin\n          //Valid, not ready, clken\n          if (((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) & ( RVALID & ! RREADY )) begin\n            r_cnt <= r_cnt + 1;\n          end else begin\n            r_cnt <= {L_R_WAIT_WIDTH{1'b0}};\n          end\n        end\n      end\n\n      assign asr_68_set = (r_cnt == MAX_R_WAITS) & ( RVALID & ! RREADY );\n    end else begin : gen_no_r_wait\n      assign asr_68_set = 1'b0;\n    end\n  endgenerate\n\n  always @(posedge ACLK) if (`AKRPS reset) ASR_68<=0; else\n    ASR_68 <= asr_68_set;\n\n  //---------------\n  //ASR_69 : assert property ( @(posedge ACLK) ( ( ARVALID & ( ARLOCK == 1'b1 ) & ( ARLEN == 8'b0 || ARLEN == 8'b1 || ARLEN == 8'b11 || ARLEN == 8'b111 || ARLEN == 8'b1111 ) ) |-> ( ( ARADDR[10:0] & ExclMask ) == ARADDR[10:0] ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_69<=0; else\n    ASR_69 <= ((((ARVALID & ( (ARLOCK == 1'b1) )) & ( (((((ARLEN == 8'b0) || (ARLEN == 8'b1)) || (ARLEN == 8'b11)) || (ARLEN == 8'b111)) || (ARLEN == 8'b1111)) )) && !((( (ARADDR[10:0] & ExclMask) ) == ARADDR[10:0]))));\n\n  //---------------\n  //ASR_70 : assert property ( @(posedge ACLK) ( ARVALID & ( ARLOCK == 1'b1 ) |-> ( ( ARLEN == 8'b0 ) || ( ARLEN == 8'b1 ) || ( ARLEN == 8'b11 ) || ( ARLEN == 8'b111 ) || ( ARLEN == 8'b1111 ) ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_70<=0; else\n    ASR_70 <= (((ARVALID & ( (ARLOCK == 1'b1) )) && !(((((( (ARLEN == 8'b0) ) || ( (ARLEN == 8'b1) )) || ( (ARLEN == 8'b11) )) || ( (ARLEN == 8'b111) )) || ( (ARLEN == 8'b1111) )))));\n\n  //---------------\n  //ASR_71 : assert property ( @(posedge ACLK) ( i_RecommendOn & AWVALID & AWREADY & ( AWLOCK == 1'b1 ) & ExclReadAddr[ExclAwId] & ExclAwMatch |-> ( ( ExclAddr[ExclAwId] == AWADDR ) & ( ExclSize[ExclAwId] == AWSIZE ) & ( ExclLen[ExclAwId] == AWLEN ) & ( ExclBurst[ExclAwId] == AWBURST ) & ( ExclCache[ExclAwId] == AWCACHE ) & ( ExclProt[ExclAwId] == AWPROT ) & ( ExclRegion[ExclAwId] == AWREGION ) ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_71<=0; else\n    ASR_71 <= (((((((i_RecommendOn & AWVALID) & AWREADY) & ( (AWLOCK == 1'b1) )) & ExclReadAddr) & ExclAwMatch) && !(((((((( (ExclAddr == AWADDR) ) & ( (ExclSize == AWSIZE) )) & ( (ExclLen == AWLEN) )) & ( (ExclBurst == AWBURST) )) & ( (ExclCache == AWCACHE) )) & ( (ExclProt == AWPROT) )) & ( (ExclRegion == AWREGION) ))))); // ###MBAC###\n\n  //---------------\n  //ASR_72 : assert property ( @(posedge ACLK) ( ( ARVALID & ( ARLOCK == 1'b1 ) & ( ARLEN == 8'b1 || ARLEN == 8'b11 || ARLEN == 8'b111 || ARLEN == 8'b1111 ) ) |-> ( ArLenInBytes <= 128 ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_72<=0; else\n    ASR_72 <= ((((ARVALID & ( (ARLOCK == 1'b1) )) & ( ((((ARLEN == 8'b1) || (ARLEN == 8'b11)) || (ARLEN == 8'b111)) || (ARLEN == 8'b1111)) )) && !((ArLenInBytes <= 128))));\n\n  //---------------\n  //ASR_73 : assert property ( @(posedge ACLK) ( i_RecommendOn & AWVALID & AWREADY & ( AWLOCK == 1'b1 ) |-> ( ExclAwMatch && ExclReadAddr[ExclAwId] && ExclReadData[ExclAwId] ) ) );\n  //---------------\n  always @(posedge ACLK) if (`AKRPS reset) ASR_73<=0; else\n    ASR_73 <= (((((i_RecommendOn & AWVALID) & AWREADY) & ( (AWLOCK == 1'b1) )) && !(((ExclAwMatch && ExclReadAddr) && ExclReadData)))); // ###MBAC###\n\n  //---------------\n  //ASR_74 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWUSER) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s103<=AWUSER;\n//  assign s104 = s103 == AWUSER;\n//  always @(posedge ACLK) if (`AKRPS reset) s105sq<=3'h4; else\n//    s105sq<=s105s;\n//  assign s105s={1'b1,\n//    ((ARESETn & AWVALID) & (! AWREADY)),\n//    (s105sq[1] && (ARESETn && !(s104)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_74<=0; else\n//    ASR_74 <= (s105s[0]);\nlocalparam integer L_NUM_AWUSER_BYTES       = ((AWUSER_WIDTH + 7) / 8);\nlocalparam integer L_NUM_AWUSER_BYTE_LANES  = ((L_NUM_AWUSER_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_AWUSER_EQ_LANES    = (L_NUM_AWUSER_BYTE_LANES / 8);\nlocalparam integer L_NUM_AWUSER_AND1_LANES  = (L_NUM_AWUSER_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_AWUSER_AND2_LANES  = (L_NUM_AWUSER_AND1_LANES + 7) / 8;\n\nreg   [AWUSER_WIDTH - 1:0] AWUSER_q;\nreg   [4:0]               s_AWUSER_sq;\nwire  [4:0]               s_AWUSER_s;\nwire                      s_AWUSER_sqaa;\n\nreg [(8*L_NUM_AWUSER_EQ_LANES)-1:0]    AWUSER_eq;\nreg [(8*L_NUM_AWUSER_AND1_LANES)-1:0]  AWUSER_stage_1_eq;\nreg [(8*L_NUM_AWUSER_AND2_LANES)-1:0]  AWUSER_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_AWUSER_sq<=5'h00; \n    ASR_74 <=0;\n  end else begin\n    s_AWUSER_sq<=s_AWUSER_s;\n    ASR_74 <= (s_AWUSER_s[0]);\n  end\nend\n\nassign s_AWUSER_s={\n  (((ARESETn & AWVALID) & (! AWREADY))),\n  (s_AWUSER_sq[4] && ARESETn),\n  (s_AWUSER_sq[3]),\n  (s_AWUSER_sq[2]),\n  (s_AWUSER_sq[1] & !(s_AWUSER_sqaa))\n  };\n\nassign s_AWUSER_sqaa = &AWUSER_stage_2_eq;\n\nwire  [(L_NUM_AWUSER_BYTES*8)-1:0]      AWUSER_expand;\nwire  [(L_NUM_AWUSER_BYTES*8)-1:0]      AWUSERsqa_expand;\ngenvar AWUSER_bit;\ngenerate\n  ///////////////////////////////////////////////////////////////////////////////////////////\n  //Expand the AWUSER up to the nearest byte\n  for (AWUSER_bit = 0; AWUSER_bit < (L_NUM_AWUSER_BYTES * 8); AWUSER_bit = AWUSER_bit + 1) begin : AWUSER_BIT_LOOP\n    if (AWUSER_bit < AWUSER_WIDTH) begin : VAL\n      assign AWUSER_expand[AWUSER_bit] = AWUSER[AWUSER_bit];\n      assign AWUSERsqa_expand[AWUSER_bit] = AWUSER_q[AWUSER_bit];\n    end else begin\n      assign AWUSER_expand[AWUSER_bit] = 1'b0;\n      assign AWUSERsqa_expand[AWUSER_bit] = 1'b0;\n    end\n  end\nendgenerate\n\ninteger AWUSER_bc;\ninteger AWUSER_stage_1;\ninteger AWUSER_stage_2;\n\nalways @(posedge ACLK) begin\n  AWUSER_q<=AWUSER;\n\n  for (AWUSER_bc = 0; AWUSER_bc < L_NUM_AWUSER_EQ_LANES*8; AWUSER_bc = AWUSER_bc + 1) begin : AWUSER_BC_LOOP\n    if (AWUSER_bc < L_NUM_AWUSER_BYTES) begin\n      AWUSER_eq[AWUSER_bc] <= AWUSER_expand[AWUSER_bc*8 +:8] == AWUSERsqa_expand[AWUSER_bc*8 +: 8];\n    end else begin\n      AWUSER_eq[AWUSER_bc] <= 1'b1;\n    end\n  end\n\n  for (AWUSER_stage_1 = 0; AWUSER_stage_1 < L_NUM_AWUSER_AND1_LANES * 8;AWUSER_stage_1 = AWUSER_stage_1 + 1) begin : AWUSER_S1\n    if (AWUSER_stage_1 < L_NUM_AWUSER_EQ_LANES) begin\n      AWUSER_stage_1_eq[AWUSER_stage_1] <= &AWUSER_eq[AWUSER_stage_1*8 +:8];\n    end else begin\n      AWUSER_stage_1_eq[AWUSER_stage_1] <= 1'b1;\n    end\n  end\n\n  for (AWUSER_stage_2 = 0; AWUSER_stage_2 < L_NUM_AWUSER_AND2_LANES * 8;AWUSER_stage_2 = AWUSER_stage_2 + 1) begin : AWUSER_S2\n    if (AWUSER_stage_2 < L_NUM_AWUSER_AND1_LANES) begin\n      AWUSER_stage_2_eq[AWUSER_stage_2] <= &AWUSER_stage_1_eq[AWUSER_stage_2*8 +:8];\n    end else begin\n      AWUSER_stage_2_eq[AWUSER_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n\n  //---------------\n  //ASR_75 : assert property ( @(posedge ACLK) ( ARESETn & WVALID & ! WREADY ##1 ARESETn |-> $stable(WUSER) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s106<=WUSER;\n//  assign s107 = s106 == WUSER;\n//  always @(posedge ACLK) if (`AKRPS reset) s108sq<=3'h4; else\n//    s108sq<=s108s;\n//  assign s108s={1'b1,\n//    ((ARESETn & WVALID) & (! WREADY)),\n//    (s108sq[1] && (ARESETn && !(s107)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_75<=0; else\n//    ASR_75 <= (s108s[0]);\nlocalparam integer L_NUM_WUSER_BYTES       = ((WUSER_WIDTH + 7) / 8);\nlocalparam integer L_NUM_WUSER_BYTE_LANES  = ((L_NUM_WUSER_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_WUSER_EQ_LANES    = (L_NUM_WUSER_BYTE_LANES / 8);\nlocalparam integer L_NUM_WUSER_AND1_LANES  = (L_NUM_WUSER_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_WUSER_AND2_LANES  = (L_NUM_WUSER_AND1_LANES + 7) / 8;\n\nreg   [WUSER_WIDTH - 1:0] WUSER_q;\nreg   [4:0]               s_WUSER_sq;\nwire  [4:0]               s_WUSER_s;\nwire                      s_WUSER_sqaa;\n\nreg [(8*L_NUM_WUSER_EQ_LANES)-1:0]    WUSER_eq;\nreg [(8*L_NUM_WUSER_AND1_LANES)-1:0]  WUSER_stage_1_eq;\nreg [(8*L_NUM_WUSER_AND2_LANES)-1:0]  WUSER_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_WUSER_sq<=5'h00; \n    ASR_75 <=0;\n  end else begin\n    s_WUSER_sq<=s_WUSER_s;\n    ASR_75 <= (s_WUSER_s[0]);\n  end\nend\n\nassign s_WUSER_s={\n  (((ARESETn & WVALID) & (! WREADY))),\n  (s_WUSER_sq[4] && ARESETn),\n  (s_WUSER_sq[3]),\n  (s_WUSER_sq[2]),\n  (s_WUSER_sq[1] & !(s_WUSER_sqaa))\n  };\n\nassign s_WUSER_sqaa = &WUSER_stage_2_eq;\n\nwire  [(L_NUM_WUSER_BYTES*8)-1:0]      WUSER_expand;\nwire  [(L_NUM_WUSER_BYTES*8)-1:0]      WUSERsqa_expand;\ngenvar WUSER_bit;\ngenerate\n  ///////////////////////////////////////////////////////////////////////////////////////////\n  //Expand the WUSER up to the nearest byte\n  for (WUSER_bit = 0; WUSER_bit < (L_NUM_WUSER_BYTES * 8); WUSER_bit = WUSER_bit + 1) begin : WUSER_BIT_LOOP\n    if (WUSER_bit < WUSER_WIDTH) begin : VAL\n      assign WUSER_expand[WUSER_bit] = WUSER[WUSER_bit];\n      assign WUSERsqa_expand[WUSER_bit] = WUSER_q[WUSER_bit];\n    end else begin\n      assign WUSER_expand[WUSER_bit] = 1'b0;\n      assign WUSERsqa_expand[WUSER_bit] = 1'b0;\n    end\n  end\nendgenerate\n\ninteger WUSER_bc;\ninteger WUSER_stage_1;\ninteger WUSER_stage_2;\n\nalways @(posedge ACLK) begin\n  WUSER_q<=WUSER;\n\n  for (WUSER_bc = 0; WUSER_bc < L_NUM_WUSER_EQ_LANES*8; WUSER_bc = WUSER_bc + 1) begin : WUSER_BC_LOOP\n    if (WUSER_bc < L_NUM_WUSER_BYTES) begin\n      WUSER_eq[WUSER_bc] <= WUSER_expand[WUSER_bc*8 +:8] == WUSERsqa_expand[WUSER_bc*8 +: 8];\n    end else begin\n      WUSER_eq[WUSER_bc] <= 1'b1;\n    end\n  end\n\n  for (WUSER_stage_1 = 0; WUSER_stage_1 < L_NUM_WUSER_AND1_LANES * 8;WUSER_stage_1 = WUSER_stage_1 + 1) begin : WUSER_S1\n    if (WUSER_stage_1 < L_NUM_WUSER_EQ_LANES) begin\n      WUSER_stage_1_eq[WUSER_stage_1] <= &WUSER_eq[WUSER_stage_1*8 +:8];\n    end else begin\n      WUSER_stage_1_eq[WUSER_stage_1] <= 1'b1;\n    end\n  end\n\n  for (WUSER_stage_2 = 0; WUSER_stage_2 < L_NUM_WUSER_AND2_LANES * 8;WUSER_stage_2 = WUSER_stage_2 + 1) begin : WUSER_S2\n    if (WUSER_stage_2 < L_NUM_WUSER_AND1_LANES) begin\n      WUSER_stage_2_eq[WUSER_stage_2] <= &WUSER_stage_1_eq[WUSER_stage_2*8 +:8];\n    end else begin\n      WUSER_stage_2_eq[WUSER_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n\n  //---------------\n  //ASR_76 : assert property ( @(posedge ACLK) ( ARESETn & BVALID & ! BREADY ##1 ARESETn |-> $stable(BUSER) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s109<=BUSER;\n//  assign s110 = s109 == BUSER;\n//  always @(posedge ACLK) if (`AKRPS reset) s111sq<=3'h4; else\n//    s111sq<=s111s;\n//  assign s111s={1'b1,\n//    ((ARESETn & BVALID) & (! BREADY)),\n//    (s111sq[1] && (ARESETn && !(s110)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_76<=0; else\n//    ASR_76 <= (s111s[0]);\nlocalparam integer L_NUM_BUSER_BYTES       = ((BUSER_WIDTH + 7) / 8);\nlocalparam integer L_NUM_BUSER_BYTE_LANES  = ((L_NUM_BUSER_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_BUSER_EQ_LANES    = (L_NUM_BUSER_BYTE_LANES / 8);\nlocalparam integer L_NUM_BUSER_AND1_LANES  = (L_NUM_BUSER_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_BUSER_AND2_LANES  = (L_NUM_BUSER_AND1_LANES + 7) / 8;\n\nreg   [BUSER_WIDTH - 1:0] BUSER_q;\nreg   [4:0]               s_BUSER_sq;\nwire  [4:0]               s_BUSER_s;\nwire                      s_BUSER_sqaa;\n\nreg [(8*L_NUM_BUSER_EQ_LANES)-1:0]    BUSER_eq;\nreg [(8*L_NUM_BUSER_AND1_LANES)-1:0]  BUSER_stage_1_eq;\nreg [(8*L_NUM_BUSER_AND2_LANES)-1:0]  BUSER_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_BUSER_sq<=5'h00; \n    ASR_76 <=0;\n  end else begin\n    s_BUSER_sq<=s_BUSER_s;\n    ASR_76 <= (s_BUSER_s[0]);\n  end\nend\n\nassign s_BUSER_s={\n  (((ARESETn & BVALID) & (! BREADY))),\n  (s_BUSER_sq[4] && ARESETn),\n  (s_BUSER_sq[3]),\n  (s_BUSER_sq[2]),\n  (s_BUSER_sq[1] & !(s_BUSER_sqaa))\n  };\n\nassign s_BUSER_sqaa = &BUSER_stage_2_eq;\n\nwire  [(L_NUM_BUSER_BYTES*8)-1:0]      BUSER_expand;\nwire  [(L_NUM_BUSER_BYTES*8)-1:0]      BUSERsqa_expand;\ngenvar BUSER_bit;\ngenerate\n  ///////////////////////////////////////////////////////////////////////////////////////////\n  //Expand the BUSER up to the nearest byte\n  for (BUSER_bit = 0; BUSER_bit < (L_NUM_BUSER_BYTES * 8); BUSER_bit = BUSER_bit + 1) begin : BUSER_BIT_LOOP\n    if (BUSER_bit < BUSER_WIDTH) begin : VAL\n      assign BUSER_expand[BUSER_bit] = BUSER[BUSER_bit];\n      assign BUSERsqa_expand[BUSER_bit] = BUSER_q[BUSER_bit];\n    end else begin\n      assign BUSER_expand[BUSER_bit] = 1'b0;\n      assign BUSERsqa_expand[BUSER_bit] = 1'b0;\n    end\n  end\nendgenerate\n\ninteger BUSER_bc;\ninteger BUSER_stage_1;\ninteger BUSER_stage_2;\n\nalways @(posedge ACLK) begin\n  BUSER_q<=BUSER;\n\n  for (BUSER_bc = 0; BUSER_bc < L_NUM_BUSER_EQ_LANES*8; BUSER_bc = BUSER_bc + 1) begin : BUSER_BC_LOOP\n    if (BUSER_bc < L_NUM_BUSER_BYTES) begin\n      BUSER_eq[BUSER_bc] <= BUSER_expand[BUSER_bc*8 +:8] == BUSERsqa_expand[BUSER_bc*8 +: 8];\n    end else begin\n      BUSER_eq[BUSER_bc] <= 1'b1;\n    end\n  end\n\n  for (BUSER_stage_1 = 0; BUSER_stage_1 < L_NUM_BUSER_AND1_LANES * 8;BUSER_stage_1 = BUSER_stage_1 + 1) begin : BUSER_S1\n    if (BUSER_stage_1 < L_NUM_BUSER_EQ_LANES) begin\n      BUSER_stage_1_eq[BUSER_stage_1] <= &BUSER_eq[BUSER_stage_1*8 +:8];\n    end else begin\n      BUSER_stage_1_eq[BUSER_stage_1] <= 1'b1;\n    end\n  end\n\n  for (BUSER_stage_2 = 0; BUSER_stage_2 < L_NUM_BUSER_AND2_LANES * 8;BUSER_stage_2 = BUSER_stage_2 + 1) begin : BUSER_S2\n    if (BUSER_stage_2 < L_NUM_BUSER_AND1_LANES) begin\n      BUSER_stage_2_eq[BUSER_stage_2] <= &BUSER_stage_1_eq[BUSER_stage_2*8 +:8];\n    end else begin\n      BUSER_stage_2_eq[BUSER_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n  //---------------\n  //ASR_77 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARUSER) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s112<=ARUSER;\n//  assign s113 = s112 == ARUSER;\n//  always @(posedge ACLK) if (`AKRPS reset) s114sq<=3'h4; else\n//    s114sq<=s114s;\n//  assign s114s={1'b1,\n//    ((ARESETn & ARVALID) & (! ARREADY)),\n//    (s114sq[1] && (ARESETn && !(s113)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_77<=0; else\n//    ASR_77 <= (s114s[0]);\nlocalparam integer L_NUM_ARUSER_BYTES       = ((ARUSER_WIDTH + 7) / 8);\nlocalparam integer L_NUM_ARUSER_BYTE_LANES  = ((L_NUM_ARUSER_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_ARUSER_EQ_LANES    = (L_NUM_ARUSER_BYTE_LANES / 8);\nlocalparam integer L_NUM_ARUSER_AND1_LANES  = (L_NUM_ARUSER_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_ARUSER_AND2_LANES  = (L_NUM_ARUSER_AND1_LANES + 7) / 8;\n\nreg   [ARUSER_WIDTH - 1:0] ARUSER_q;\nreg   [4:0]               s_ARUSER_sq;\nwire  [4:0]               s_ARUSER_s;\nwire                      s_ARUSER_sqaa;\n\nreg [(8*L_NUM_ARUSER_EQ_LANES)-1:0]    ARUSER_eq;\nreg [(8*L_NUM_ARUSER_AND1_LANES)-1:0]  ARUSER_stage_1_eq;\nreg [(8*L_NUM_ARUSER_AND2_LANES)-1:0]  ARUSER_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_ARUSER_sq<=5'h00; \n    ASR_77 <=0;\n  end else begin\n    s_ARUSER_sq<=s_ARUSER_s;\n    ASR_77 <= (s_ARUSER_s[0]);\n  end\nend\n\nassign s_ARUSER_s={\n  (((ARESETn & ARVALID) & (! ARREADY))),\n  (s_ARUSER_sq[4] && ARESETn),\n  (s_ARUSER_sq[3]),\n  (s_ARUSER_sq[2]),\n  (s_ARUSER_sq[1] & !(s_ARUSER_sqaa))\n  };\n\nassign s_ARUSER_sqaa = &ARUSER_stage_2_eq;\n\nwire  [(L_NUM_ARUSER_BYTES*8)-1:0]      ARUSER_expand;\nwire  [(L_NUM_ARUSER_BYTES*8)-1:0]      ARUSERsqa_expand;\ngenvar ARUSER_bit;\ngenerate\n  ///////////////////////////////////////////////////////////////////////////////////////////\n  //Expand the ARUSER up to the nearest byte\n  for (ARUSER_bit = 0; ARUSER_bit < (L_NUM_ARUSER_BYTES * 8); ARUSER_bit = ARUSER_bit + 1) begin : ARUSER_BIT_LOOP\n    if (ARUSER_bit < ARUSER_WIDTH) begin : VAL\n      assign ARUSER_expand[ARUSER_bit] = ARUSER[ARUSER_bit];\n      assign ARUSERsqa_expand[ARUSER_bit] = ARUSER_q[ARUSER_bit];\n    end else begin\n      assign ARUSER_expand[ARUSER_bit] = 1'b0;\n      assign ARUSERsqa_expand[ARUSER_bit] = 1'b0;\n    end\n  end\nendgenerate\n\ninteger ARUSER_bc;\ninteger ARUSER_stage_1;\ninteger ARUSER_stage_2;\n\nalways @(posedge ACLK) begin\n  ARUSER_q<=ARUSER;\n\n  for (ARUSER_bc = 0; ARUSER_bc < L_NUM_ARUSER_EQ_LANES*8; ARUSER_bc = ARUSER_bc + 1) begin : ARUSER_BC_LOOP\n    if (ARUSER_bc < L_NUM_ARUSER_BYTES) begin\n      ARUSER_eq[ARUSER_bc] <= ARUSER_expand[ARUSER_bc*8 +:8] == ARUSERsqa_expand[ARUSER_bc*8 +: 8];\n    end else begin\n      ARUSER_eq[ARUSER_bc] <= 1'b1;\n    end\n  end\n\n  for (ARUSER_stage_1 = 0; ARUSER_stage_1 < L_NUM_ARUSER_AND1_LANES * 8;ARUSER_stage_1 = ARUSER_stage_1 + 1) begin : ARUSER_S1\n    if (ARUSER_stage_1 < L_NUM_ARUSER_EQ_LANES) begin\n      ARUSER_stage_1_eq[ARUSER_stage_1] <= &ARUSER_eq[ARUSER_stage_1*8 +:8];\n    end else begin\n      ARUSER_stage_1_eq[ARUSER_stage_1] <= 1'b1;\n    end\n  end\n\n  for (ARUSER_stage_2 = 0; ARUSER_stage_2 < L_NUM_ARUSER_AND2_LANES * 8;ARUSER_stage_2 = ARUSER_stage_2 + 1) begin : ARUSER_S2\n    if (ARUSER_stage_2 < L_NUM_ARUSER_AND1_LANES) begin\n      ARUSER_stage_2_eq[ARUSER_stage_2] <= &ARUSER_stage_1_eq[ARUSER_stage_2*8 +:8];\n    end else begin\n      ARUSER_stage_2_eq[ARUSER_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n  //---------------\n  //ASR_78 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> $stable(RUSER) ) );\n  //---------------\n//  always @(posedge ACLK)\n//    s115<=RUSER;\n//  assign s116 = s115 == RUSER;\n//  always @(posedge ACLK) if (`AKRPS reset) s117sq<=3'h4; else\n//    s117sq<=s117s;\n//  assign s117s={1'b1,\n//    ((ARESETn & RVALID) & (! RREADY)),\n//    (s117sq[1] && (ARESETn && !(s116)))};\n//  always @(posedge ACLK) if (`AKRPS reset) ASR_78<=0; else\n//    ASR_78 <= (s117s[0]);\nlocalparam integer L_NUM_RUSER_BYTES       = ((RUSER_WIDTH + 7) / 8);\nlocalparam integer L_NUM_RUSER_BYTE_LANES  = ((L_NUM_RUSER_BYTES + 7) / 8) * 8;\nlocalparam integer L_NUM_RUSER_EQ_LANES    = (L_NUM_RUSER_BYTE_LANES / 8);\nlocalparam integer L_NUM_RUSER_AND1_LANES  = (L_NUM_RUSER_EQ_LANES + 7) / 8;\nlocalparam integer L_NUM_RUSER_AND2_LANES  = (L_NUM_RUSER_AND1_LANES + 7) / 8;\n\nreg   [RUSER_WIDTH - 1:0] RUSER_q;\nreg   [4:0]               s_RUSER_sq;\nwire  [4:0]               s_RUSER_s;\nwire                      s_RUSER_sqaa;\n\nreg [(8*L_NUM_RUSER_EQ_LANES)-1:0]    RUSER_eq;\nreg [(8*L_NUM_RUSER_AND1_LANES)-1:0]  RUSER_stage_1_eq;\nreg [(8*L_NUM_RUSER_AND2_LANES)-1:0]  RUSER_stage_2_eq;\n\nalways @(posedge ACLK) begin\n  if (`AKRPS reset) begin\n    s_RUSER_sq<=5'h00; \n    ASR_78 <=0;\n  end else begin\n    s_RUSER_sq<=s_RUSER_s;\n    ASR_78 <= (s_RUSER_s[0]);\n  end\nend\n\nassign s_RUSER_s={\n  (((ARESETn & RVALID) & (! RREADY))),\n  (s_RUSER_sq[4] && ARESETn),\n  (s_RUSER_sq[3]),\n  (s_RUSER_sq[2]),\n  (s_RUSER_sq[1] & !(s_RUSER_sqaa))\n  };\n\nassign s_RUSER_sqaa = &RUSER_stage_2_eq;\n\nwire  [(L_NUM_RUSER_BYTES*8)-1:0]      RUSER_expand;\nwire  [(L_NUM_RUSER_BYTES*8)-1:0]      RUSERsqa_expand;\ngenvar RUSER_bit;\ngenerate\n  ///////////////////////////////////////////////////////////////////////////////////////////\n  //Expand the RUSER up to the nearest byte\n  for (RUSER_bit = 0; RUSER_bit < (L_NUM_RUSER_BYTES * 8); RUSER_bit = RUSER_bit + 1) begin : RUSER_BIT_LOOP\n    if (RUSER_bit < RUSER_WIDTH) begin : VAL\n      assign RUSER_expand[RUSER_bit] = RUSER[RUSER_bit];\n      assign RUSERsqa_expand[RUSER_bit] = RUSER_q[RUSER_bit];\n    end else begin\n      assign RUSER_expand[RUSER_bit] = 1'b0;\n      assign RUSERsqa_expand[RUSER_bit] = 1'b0;\n    end\n  end\nendgenerate\n\ninteger RUSER_bc;\ninteger RUSER_stage_1;\ninteger RUSER_stage_2;\n\nalways @(posedge ACLK) begin\n  RUSER_q<=RUSER;\n\n  for (RUSER_bc = 0; RUSER_bc < L_NUM_RUSER_EQ_LANES*8; RUSER_bc = RUSER_bc + 1) begin : RUSER_BC_LOOP\n    if (RUSER_bc < L_NUM_RUSER_BYTES) begin\n      RUSER_eq[RUSER_bc] <= RUSER_expand[RUSER_bc*8 +:8] == RUSERsqa_expand[RUSER_bc*8 +: 8];\n    end else begin\n      RUSER_eq[RUSER_bc] <= 1'b1;\n    end\n  end\n\n  for (RUSER_stage_1 = 0; RUSER_stage_1 < L_NUM_RUSER_AND1_LANES * 8;RUSER_stage_1 = RUSER_stage_1 + 1) begin : RUSER_S1\n    if (RUSER_stage_1 < L_NUM_RUSER_EQ_LANES) begin\n      RUSER_stage_1_eq[RUSER_stage_1] <= &RUSER_eq[RUSER_stage_1*8 +:8];\n    end else begin\n      RUSER_stage_1_eq[RUSER_stage_1] <= 1'b1;\n    end\n  end\n\n  for (RUSER_stage_2 = 0; RUSER_stage_2 < L_NUM_RUSER_AND2_LANES * 8;RUSER_stage_2 = RUSER_stage_2 + 1) begin : RUSER_S2\n    if (RUSER_stage_2 < L_NUM_RUSER_AND1_LANES) begin\n      RUSER_stage_2_eq[RUSER_stage_2] <= &RUSER_stage_1_eq[RUSER_stage_2*8 +:8];\n    end else begin\n      RUSER_stage_2_eq[RUSER_stage_2] <= 1'b1;\n    end\n  end\n\nend\n\n  //---------------\n  //ASR_79 : assert property ( @(posedge ACLK) ( ARESETn & ( AWUSER_WIDTH == 0 ) |-> $stable(AWUSER) ) );\n  //---------------\n  always @(posedge ACLK)\n    s118<=AWUSER;\n  assign s119 = s118 == AWUSER;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_79<=0; else\n    ASR_79 <= (((ARESETn & ( (AWUSER_WIDTH == 0) )) && !(s119)));\n\n  //---------------\n  //ASR_80 : assert property ( @(posedge ACLK) ( ARESETn & ( WUSER_WIDTH == 0 ) |-> $stable(WUSER) ) );\n  //---------------\n  always @(posedge ACLK)\n    s120<=WUSER;\n  assign s121 = s120 == WUSER;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_80<=0; else\n    ASR_80 <= (((ARESETn & ( (WUSER_WIDTH == 0) )) && !(s121)));\n\n  //---------------\n  //ASR_81 : assert property ( @(posedge ACLK) ( ARESETn & ( BUSER_WIDTH == 0 ) |-> $stable(BUSER) ) );\n  //---------------\n  always @(posedge ACLK)\n    s122<=BUSER;\n  assign s123 = s122 == BUSER;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_81<=0; else\n    ASR_81 <= (((ARESETn & ( (BUSER_WIDTH == 0) )) && !(s123)));\n\n  //---------------\n  //ASR_82 : assert property ( @(posedge ACLK) ( ARESETn & ( ARUSER_WIDTH == 0 ) |-> $stable(ARUSER) ) );\n  //---------------\n  always @(posedge ACLK)\n    s124<=ARUSER;\n  assign s125 = s124 == ARUSER;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_82<=0; else\n    ASR_82 <= (((ARESETn & ( (ARUSER_WIDTH == 0) )) && !(s125)));\n\n  //---------------\n  //ASR_83 : assert property ( @(posedge ACLK) ( ARESETn & ( RUSER_WIDTH == 0 ) |-> $stable(RUSER) ) );\n  //---------------\n  always @(posedge ACLK)\n    s126<=RUSER;\n  assign s127 = s126 == RUSER;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_83<=0; else\n    ASR_83 <= (((ARESETn & ( (RUSER_WIDTH == 0) )) && !(s127)));\n\n  //---------------\n  //ASR_84 : assert property ( @(posedge ACLK) ( ARESETn & ( ID_WIDTH == 0 ) |-> $stable(AWID) ) );\n  //---------------\n  always @(posedge ACLK)\n    s128<=AWID;\n  assign s129 = s128 == AWID;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_84<=0; else\n    ASR_84 <= (((ARESETn & ( (ID_WIDTH == 0) )) && !(s129)));\n\n  //---------------\n  //ASR_85 : assert property ( @(posedge ACLK) ( ARESETn & ( ID_WIDTH == 0 ) |-> $stable(BID) ) );\n  //---------------\n  always @(posedge ACLK)\n    s130<=BID;\n  assign s131 = s130 == BID;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_85<=0; else\n    ASR_85 <= (((ARESETn & ( (ID_WIDTH == 0) )) && !(s131)));\n\n  //---------------\n  //ASR_86 : assert property ( @(posedge ACLK) ( ARESETn & ( ID_WIDTH == 0 ) |-> $stable(ARID) ) );\n  //---------------\n  always @(posedge ACLK)\n    s132<=ARID;\n  assign s133 = s132 == ARID;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_86<=0; else\n    ASR_86 <= (((ARESETn & ( (ID_WIDTH == 0) )) && !(s133)));\n\n  //---------------\n  //ASR_87 : assert property ( @(posedge ACLK) ( ARESETn & ( ID_WIDTH == 0 ) |-> $stable(RID) ) );\n  //---------------\n  always @(posedge ACLK)\n    s134<=RID;\n  assign s135 = s134 == RID;\n  always @(posedge ACLK) if (`AKRPS reset) ASR_87<=0; else\n    ASR_87 <= (((ARESETn & ( (ID_WIDTH == 0) )) && !(s135)));\n\nendmodule //Axi4PC_asr_inline\n\n\n// (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//*****************************************************************************\n// Notes            : The assertion ASR_23 is not implemented for WDATA before\n//                    AWADDR, since that would require storing all WSTRB in a\n//                    burst.\n//\n//                    The following assertions use FIFOs to store AW and W\n//                    signals, and can be disabled to improve frequency and\n//                    reduce area: ASR_22, ASR_23, ASR_30, ASR_31, ASR_33.\n//\n//                    The following assertions use FIFOs to store AW and W\n//                    signals, and can be disabled to improve frequency and\n//                    reduce area: ASR_59, ASR_60, ASR_61, ASR_63, ASR_73.\n//                    In particular, ASR_59 is timing critical.\n//*****************************************************************************\n\n`timescale 1ps/1ps\n`default_nettype none\n\n`define AXI4PC_TYPES\n// ALEN Encoding\n`define AXI4PC_ALEN_1            8'b00000000\n`define AXI4PC_ALEN_2            8'b00000001\n`define AXI4PC_ALEN_3            8'b00000010\n`define AXI4PC_ALEN_4            8'b00000011\n`define AXI4PC_ALEN_5            8'b00000100\n`define AXI4PC_ALEN_6            8'b00000101\n`define AXI4PC_ALEN_7            8'b00000110\n`define AXI4PC_ALEN_8            8'b00000111\n`define AXI4PC_ALEN_9            8'b00001000\n`define AXI4PC_ALEN_10           8'b00001001\n`define AXI4PC_ALEN_11           8'b00001010\n`define AXI4PC_ALEN_12           8'b00001011\n`define AXI4PC_ALEN_13           8'b00001100\n`define AXI4PC_ALEN_14           8'b00001101\n`define AXI4PC_ALEN_15           8'b00001110\n`define AXI4PC_ALEN_16           8'b00001111\n\n// ASIZE Encoding\n`define AXI4PC_ASIZE_8           3'b000\n`define AXI4PC_ASIZE_16          3'b001\n`define AXI4PC_ASIZE_32          3'b010\n`define AXI4PC_ASIZE_64          3'b011\n`define AXI4PC_ASIZE_128         3'b100\n`define AXI4PC_ASIZE_256         3'b101\n`define AXI4PC_ASIZE_512         3'b110\n`define AXI4PC_ASIZE_1024        3'b111\n\n// ABURST Encoding\n`define AXI4PC_ABURST_FIXED      2'b00\n`define AXI4PC_ABURST_INCR       2'b01 \n`define AXI4PC_ABURST_WRAP       2'b10 \n\n// ALOCK Encoding\n`define AXI4PC_ALOCK_EXCL        1'b1\n\n// RRESP / BRESP Encoding\n`define AXI4PC_RESP_OKAY         2'b00\n`define AXI4PC_RESP_EXOKAY       2'b01\n`define AXI4PC_RESP_SLVERR       2'b10\n`define AXI4PC_RESP_DECERR       2'b11\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_protocol_checker_v1_1_12_core #(\n  parameter integer C_ERROR_COUNT = 97,\n  parameter integer C_AXI_ID_WIDTH = 1,\n  parameter integer C_AXI_DATA_WIDTH = 32,\n  parameter integer C_AXI_ADDR_WIDTH = 32,\n  parameter integer C_AXI_AWUSER_WIDTH = 1,\n  parameter integer C_AXI_WUSER_WIDTH  = 1,\n  parameter integer C_AXI_BUSER_WIDTH  = 1,\n  parameter integer C_AXI_ARUSER_WIDTH = 1,\n  parameter integer C_AXI_RUSER_WIDTH  = 1,\n  parameter integer C_AXI_PROTOCOL = 0,\n  parameter integer MAXRBURSTS = 16,\n  parameter integer MAXWBURSTS = 16,\n  parameter integer EXMON_WIDTH = 4,\n  parameter integer RecommendOn = 1,\n  parameter integer RecommendWaitOn = 1,\n  parameter integer MAX_AW_WAITS = 16,\n  parameter integer MAX_AR_WAITS = 16,\n  parameter integer MAX_W_WAITS = 16,\n  parameter integer MAX_R_WAITS = 16,\n  parameter integer MAX_B_WAITS = 16,\n  parameter integer C_PC_SUPPORTS_NARROW_BURST     = 1,\n  parameter integer C_PC_HAS_SYSTEM_RESET = 0,\n  parameter integer C_PC_MAX_BURST_LENGTH          = 256\n) (\n   output wire [C_ERROR_COUNT-1:0]     pc_status,\n   input wire                          resetn,\n\n   input wire                          ACLK,\n   input wire                          ARST_N,\n   input wire [C_AXI_ID_WIDTH-1:0]     AWID,\n   input wire [C_AXI_ADDR_WIDTH-1:0]   AWADDR,\n   input wire [7:0]                    AWLEN,\n   input wire [2:0]                    AWSIZE,\n   input wire [1:0]                    AWBURST,\n   input wire [0:0]                    AWLOCK,\n   input wire [3:0]                    AWCACHE,\n   input wire [2:0]                    AWPROT,\n   input wire [3:0]                    AWQOS,\n   input wire [3:0]                    AWREGION,\n   input wire [C_AXI_AWUSER_WIDTH-1:0] AWUSER,\n   input wire                          AWVALID,\n   input wire                          AWREADY,\n\n   input wire                          WLAST,\n   input wire [C_AXI_DATA_WIDTH-1:0]   WDATA,\n   input wire [C_AXI_DATA_WIDTH/8-1:0] WSTRB,\n   input wire [C_AXI_WUSER_WIDTH-1:0]  WUSER,\n   input wire                          WVALID,\n   input wire                          WREADY,\n   input wire [C_AXI_ID_WIDTH-1:0]     BID,\n   input wire [1:0]                    BRESP,\n   input wire [C_AXI_BUSER_WIDTH-1:0]  BUSER,\n   input wire                          BVALID,\n   input wire                          BREADY,\n   input wire [C_AXI_ID_WIDTH-1:0]     ARID,\n   input wire [C_AXI_ADDR_WIDTH-1:0]   ARADDR,\n   input wire [7:0]                    ARLEN,\n   input wire [2:0]                    ARSIZE,\n   input wire [1:0]                    ARBURST,\n   input wire [0:0]                    ARLOCK,\n   input wire [3:0]                    ARCACHE,\n   input wire [2:0]                    ARPROT,\n   input wire [3:0]                    ARQOS,\n   input wire [3:0]                    ARREGION,\n   input wire [C_AXI_ARUSER_WIDTH-1:0] ARUSER,\n   input wire                          ARVALID,\n   input wire                          ARREADY,\n   input wire [C_AXI_ID_WIDTH-1:0]     RID,\n   input wire                          RLAST,\n   input wire [C_AXI_DATA_WIDTH-1:0]   RDATA,\n   input wire [1:0]                    RRESP,\n   input wire [C_AXI_RUSER_WIDTH-1:0]  RUSER,\n   input wire                          RVALID,\n   input wire                          RREADY\n  );\n\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Functions\n  /////////////////////////////////////////////////////////////////////////////\n  \n  // Log2.\n  function integer log2;\n    input integer value;\n    integer a;\n    begin\n      a = value;\n      \n      for (log2=0; a>1; log2=log2+1) begin\n        a = a >> 1;\n      end\n    end\n  endfunction\n\n  function integer f_ceil_log2\n    (\n     input integer x\n     );\n    integer acc;\n    begin\n      acc=0;\n      while ((2**acc) < x)\n        acc = acc + 1;\n      f_ceil_log2 = acc;\n    end\n  endfunction\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n\n  localparam WEXCL           = 0;\n  localparam WALENLO         = WEXCL + 1;\n  localparam WALENHI         = WALENLO + 7;\n\n  localparam WADDRLO         = 0;\n  localparam WADDRHI         = 6;\n  localparam WASIZELO        = WADDRHI + 1;\n  localparam WASIZEHI        = WASIZELO + 2;\n\n  localparam STRB_WIDTH      = C_AXI_DATA_WIDTH/8;\n  localparam LOG2_STRB_WIDTH = log2(STRB_WIDTH);\n\n  localparam ID_MAX          = C_AXI_ID_WIDTH? C_AXI_ID_WIDTH-1:0;\n  localparam integer P_NUM_THREADS = ((2**C_AXI_ID_WIDTH) < MAXRBURSTS) ? 2**C_AXI_ID_WIDTH : MAXRBURSTS;\n  localparam integer P_ACCEPTANCE_LOG = f_ceil_log2(MAXRBURSTS);\n  localparam ID_SIZE         = (2**C_AXI_ID_WIDTH) - 1;\n\n  localparam ADDRLO          = 0;\n  localparam ADDRHI          = 6;\n  localparam EXCL            = ADDRHI + 1;\n  localparam ALENLO          = EXCL + 1;\n  localparam ALENHI          = ALENLO + 7;\n  localparam ASIZELO         = ALENHI + 1;\n  localparam ASIZEHI         = ASIZELO + 2;\n  localparam BURSTLO         = ASIZEHI + 1;\n  localparam BURSTHI         = BURSTLO + 1;\n  localparam LP_ADDR_WIDTH   = (C_AXI_ADDR_WIDTH > 12) ? C_AXI_ADDR_WIDTH : 13;\n  localparam LP_EXMON_WIDTH  = (EXMON_WIDTH == 0) ? 1 : EXMON_WIDTH;\n\n  wire internal_AWLOCK;\n  wire internal_ARLOCK;\n  \n  assign internal_AWLOCK = (EXMON_WIDTH == 0) ? 1'b0 : AWLOCK;\n  assign internal_ARLOCK = (EXMON_WIDTH == 0) ? 1'b0 : ARLOCK;\n\n\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n\n  wire [87:1]                 Axi4PC_asr_inline_out;\n  wire [3:1]                  Axi4LitePC_asr_inline_out;\n  reg  [11:1]                 xilinx_inline_out;\n  wire [5:1]                  Axi4PC_aux;\n\n  reg  [6:0]                  AlignMaskR;\n  reg  [6:0]                  AlignMaskW;\n  reg  [14:0]                 ExclMask;\n  reg  [LP_ADDR_WIDTH-1:0]    ArAddrIncr;\n  reg  [LP_ADDR_WIDTH-1:0]    AwAddrIncr;\n  reg  [15:0]                 ArLenInBytes;\n  reg  [10:0]                 ArSizeInBits;\n  reg  [10:0]                 AwSizeInBits;\n  wire                        ArExclPending;\n  wire                        WriteDataNumError;\n  reg                         BStrbError;\n  wire [8:0]                  ArCountPending;\n  wire [8:0]                  ArLenPending;\n  reg                         RidMatch_index;\n  wire [31:0]                 RidMatch;\n  wire                        i_RecommendOn;\n  wire                        i_RecMaxWaitOn;\n  reg  [LP_EXMON_WIDTH-1:0]   ExclAwId;\n  wire                        ExclIdOverflow;\n  wire [LP_ADDR_WIDTH-1:0]    ExclAddr_indexed;\n  wire [2:0]                  ExclSize_indexed;\n  wire [7:0]                  ExclLen_indexed;\n  wire [1:0]                  ExclBurst_indexed;\n  wire [3:0]                  ExclCache_indexed;\n  wire [2:0]                  ExclProt_indexed;\n  wire [3:0]                  ExclRegion_indexed;\n  wire                        ExclReadAddr_indexed;\n  wire                        ExclReadData_indexed;\n\n  genvar                      i;                    // FIFO generation variable\n\n  // Write FIFO signals\n  reg  [8:0]                  WCountIn;\n  wire                        WDataOut[0:ID_SIZE];\n  reg                         WDataNumError1;\n  reg                         BrespErrorLead;\n\n  // Read FIFO signals\n  reg  [BURSTHI:0]            RBurstCam_index;\n  wire [BURSTHI:0]            RBurstCam;\n//  reg  [BURSTHI:0]            RBurstCam1;\n  reg  [8:0]                  RCountCam_index;\n  wire [8:0]                  RCountCam;\n  reg  [8:0]                  RCountCam1;\n\n  reg  [8:0]                  RCount[0:P_NUM_THREADS-1];\n  reg  [0:P_NUM_THREADS-1]    RCountIncr;\n  reg  [BURSTHI:0]            Burst;\n  wire [BURSTHI:0]            RDataOut[0:P_NUM_THREADS-1];\n  wire [P_NUM_THREADS-1:0]    REmpty;\n  wire [P_NUM_THREADS-1:0]    RFull;\n//  reg  [11:0]                 Bcount1;\n//  reg  [11:0]                 Bcount;\n//  reg  [16:0]                 Bshift1;\n//  reg  [15:0]                 Bshift;\n\n  wire [LP_ADDR_WIDTH-1:0] awaddr = {LP_ADDR_WIDTH{1'b0}} | AWADDR[C_AXI_ADDR_WIDTH-1:0];\n  wire [LP_ADDR_WIDTH-1:0] araddr = {LP_ADDR_WIDTH{1'b0}} | ARADDR[C_AXI_ADDR_WIDTH-1:0];\n\n  wire [C_AXI_ID_WIDTH-1:0]       AWIDOut;\n  wire [7:0]                      AWLENOut;\n  wire [6:0]                      AWStrbAddrOut;\n  wire [2:0]                      AWStrbsizeOut;\n  wire                            AWEmpty;\n  wire                            AWFull;\n  wire [8:0]                      WCheckCountOut;\n  wire [C_AXI_DATA_WIDTH/8-1:0]   WCheckstrbOut;\n  wire                            WCheckEmpty;\n  wire                            WCheckFull;\n  reg  [C_AXI_DATA_WIDTH/8-1:0]   WSTRBq;\n  wire [C_AXI_DATA_WIDTH/8-1:0]   WstrbIn;\n  reg                             first_strb;\n  wire                            wcheckPop;\n  reg  [log2(MAXWBURSTS):0]       AWXferCount[0:ID_SIZE];\n  reg                             AWXferCountOverflow;\n  wire                            AWPush;\n  wire                            WLastPush;\n\n  wire  reset_i;\n  wire  resetn_out;\n  wire  checker_main_resetn;\n  (* shreg_extract=\"no\", iob=\"false\", equivalent_register_removal = \"no\" *) reg [2:0] reset_resync;\n\n  assign reset_i = ~resetn;\n  assign resetn_out = (C_PC_HAS_SYSTEM_RESET == 1) ? reset_resync[2] : ARST_N;\n  \n  always @(posedge ACLK or posedge reset_i) begin\n    if (reset_i) begin\n      reset_resync <= 3'b000;\n    end else begin\n      reset_resync <= {reset_resync[1:0], 1'b1};\n    end\n  end\n\n  assign checker_main_resetn = resetn_out & ARST_N;\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Rewritten auxillary code to meet timing derived from Axi4PC.sv\n  /////////////////////////////////////////////////////////////////////////////\n\n  //---------------------------------------------------------------------------\n  // RDataMask\n  //---------------------------------------------------------------------------\n//  always @(posedge ACLK)\n//  begin : p_ByteCountShiftSeq\n//    if (!checker_main_resetn) begin\n//      Bcount1    <= 12'b0;\n//      Bcount     <= 12'b0;\n//      Bshift1    <= 17'b0;\n//      RBurstCam1 <= {BURSTHI+1{1'b0}};\n//      RCountCam1 <= 9'b0;\n//      Bshift     <= 16'b0;\n//    end else begin\n//      Bcount1    <= ByteCount(RBurstCam, RCountCam);\n//      Bcount     <= Bcount1;\n//      Bshift1    <= ByteShift1(RBurstCam, RCountCam);\n//      RBurstCam1 <= RBurstCam;\n//      RCountCam1 <= RCountCam;\n//      Bshift     <= ByteShift2(RBurstCam1, RCountCam1, Bshift1);\n//    end\n//  end\n\n  //---------------------------------------------------------------------------\n  // Read CAMs: One FIFO per ID instead of true CAMs to improve timing\n  //---------------------------------------------------------------------------\n\n\n  /////////////////////////////////////////////////////////////////////////////\n  //\nreg  [(P_ACCEPTANCE_LOG+1)-1:0] accept_cnt;\nwire [P_NUM_THREADS-1:0] thread_valid;\nwire [P_NUM_THREADS-1:0] aid_match;\nwire [P_NUM_THREADS-1:0] rid_match;\nwire [P_NUM_THREADS-1:0] cmd_push;\nwire [P_NUM_THREADS-1:0] cmd_pop;\nwire [P_NUM_THREADS:0]   accum_push;\nreg  [P_NUM_THREADS*C_AXI_ID_WIDTH-1:0] active_id;\nreg  [P_NUM_THREADS*8-1:0] active_cnt;\nwire any_aid_match;\nwire any_rid_match;\nwire accept_limit;\nwire any_push;\nwire any_pop;\n  \nassign any_push = ARREADY & ARVALID;\nassign any_pop = RVALID && RREADY && RLAST;\nassign accept_limit = (accept_cnt == MAXRBURSTS) & ~any_pop;  // Allow next push if a transaction is currently being completed\n\nassign any_aid_match = |aid_match;\nassign any_rid_match = |rid_match;\nassign accum_push[0] = 1'b0;\n    \nalways @(posedge ACLK) begin\n  if (!checker_main_resetn) begin\n    accept_cnt <= 0; \n  end else begin\n    if (any_push & ~any_pop) begin\n      accept_cnt <= accept_cnt + 1;\n  end else if (any_pop & ~any_push & (accept_cnt != 0)) begin\n      accept_cnt <= accept_cnt - 1;\n    end\n  end \nend\n\nalways @(araddr or internal_ARLOCK or ARBURST or ARLEN or ARSIZE) begin\n  Burst[ADDRHI:ADDRLO]     = araddr[ADDRHI:ADDRLO];\n  Burst[EXCL]              = (internal_ARLOCK == `AXI4PC_ALOCK_EXCL);\n  Burst[BURSTHI:BURSTLO]   = ARBURST;\n  Burst[ALENHI:ALENLO]     = ARLEN;\n  Burst[ASIZEHI:ASIZELO]   = ARSIZE;\nend\n\ninitial begin : REG_DEFAULTS\n  active_cnt = {MAXRBURSTS*8{1'b0}};\nend\n\n\ngenvar gen_thread;\ngenerate\n  for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop\n\n    assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: P_ACCEPTANCE_LOG+1] != 0);\n\n    /////////////////////////////////////////////////////////////////////////////////\n    // The currect thread is active for the requested transaction if\n    // this thread slot is not vacant, and\n    // the requested ID matches the active ID for this thread.\n    assign aid_match[gen_thread] =  thread_valid[gen_thread] && (ARID[C_AXI_ID_WIDTH-1:0] == active_id[gen_thread*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]);\n\n    /////////////////////////////////////////////////////////////////////////////////\n    // cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot.\n    assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread];\n    assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread]));\n    \n    /////////////////////////////////////////////////////////////////////////////////\n    // cmd_pop points to the position of the active thread that matches the current RID.\n    assign rid_match[gen_thread] = thread_valid[gen_thread] & ((RID[C_AXI_ID_WIDTH-1:0]) == active_id[gen_thread*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]);\n    assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread];\n  \n    always @(posedge ACLK) begin\n      if (!checker_main_resetn) begin\n        active_id[gen_thread*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] <= {C_AXI_ID_WIDTH{1'b0}};\n        active_cnt[gen_thread*8+:8] <= 0; \n      end else begin\n        if (cmd_push[gen_thread]) begin\n          active_id[gen_thread*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] <= ARID[C_AXI_ID_WIDTH-1:0];\n          if (~cmd_pop[gen_thread]) begin\n            active_cnt[gen_thread*8+:P_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:P_ACCEPTANCE_LOG+1] + 1;\n          end\n        end else if (cmd_pop[gen_thread]) begin\n          active_cnt[gen_thread*8+:P_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:P_ACCEPTANCE_LOG+1] - 1;\n        end\n      end \n    end\n\n    axi_protocol_checker_v1_1_12_syn_fifo #(\n      .C_DATA_WIDTH (BURSTHI+1),\n      .C_ADDR_WIDTH (P_ACCEPTANCE_LOG)\n    ) RDCAM (\n      .clk      (ACLK),\n      .rst      (!checker_main_resetn),\n      .data_in  (Burst),\n      .rd       (cmd_pop[gen_thread]),\n      .wr       (cmd_push[gen_thread]),\n      .data_out (RDataOut[gen_thread]),\n      .empty    (REmpty[gen_thread]),\n      .full     (RFull[gen_thread])\n    );\n  \n    // One Counter per ID\n    always @(posedge ACLK) begin : p_RCountSeq\n      if (!checker_main_resetn | cmd_pop[gen_thread] | (cmd_push[gen_thread] & REmpty[gen_thread])) begin\n        RCount[gen_thread] <= 9'h000;\n      end else if (rid_match[gen_thread] & (RVALID & RREADY & !RLAST)) begin\n        RCount[gen_thread] <= RCount[gen_thread] + 9'h001;\n      end\n    end\n  end\n  \n  \nendgenerate\n\ninteger gen_match;\n\nalways@( * ) begin : MUX_OUT\n  RBurstCam_index = {BURSTHI+1{1'b0}};\n  RCountCam_index = {9{1'b0}};\n  RidMatch_index  = 1'b0;\n  for (gen_match = 0; gen_match < P_NUM_THREADS; gen_match = gen_match + 1) begin : GEN_MATCH\n    if (rid_match[gen_match] == 1'b1) begin : RID_MATCH\n      RBurstCam_index = RDataOut[gen_match];\n      RCountCam_index = RCount[gen_match];\n      RidMatch_index = 1'b1;\n    end\n  end\nend\n\n  assign RBurstCam     = RBurstCam_index;\n  assign RCountCam     = RCountCam_index;\n\n  assign RidMatch      = !RidMatch_index ? 32'h00000000 : 32'h00000001;\n\n  //---------------------------------------------------------------------------\n  // Write CAMs: One FIFO per ID instead of true CAMs to improve timing.\n  // Write bursts are not stored in single structure for checking when complete.\n  // This prevents checking of write strobes for write data before address.\n  //---------------------------------------------------------------------------\n  always @(posedge ACLK) begin : p_WCountInSeq\n    if (!checker_main_resetn | (WVALID & WREADY & WLAST)) begin\n      WCountIn <= 9'h000;\n    end else if (WVALID & WREADY & !WLAST) begin\n      WCountIn <= WCountIn + 9'h001;\n    end\n  end\n\n  //---------------------------------------------------------------------------\n  // Auxillary logic assertions\n  //---------------------------------------------------------------------------\n  assign Axi4PC_aux[1] = |(RFull  & cmd_push) & ARST_N; // Rd CAM overflow\n  assign Axi4PC_aux[2] = |(REmpty & cmd_pop) & ARST_N; // Rd CAM underflow\n\n\n  assign Axi4PC_aux[3] = ((AWFull & AWPush) | AWXferCountOverflow) & ARST_N; // Wr CAM overflow\n  assign Axi4PC_aux[4] = (WCheckFull & WLastPush)  & ARST_N; // Wr CAM underflow\n  assign Axi4PC_aux[5] = (C_AXI_PROTOCOL != 2) & ExclIdOverflow & ARST_N;  // Excl overflow\n\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Code from Axi4PC.sv (modifications indicated with ###)\n  /////////////////////////////////////////////////////////////////////////////\n\n  localparam DATA_MAX    = C_AXI_DATA_WIDTH-1;\n  localparam EXMON_HI    = {LP_EXMON_WIDTH{1'b1}};\n  localparam AWUSER_MAX  = C_AXI_AWUSER_WIDTH ? C_AXI_AWUSER_WIDTH-1:0;\n  localparam WUSER_MAX   = C_AXI_WUSER_WIDTH ? C_AXI_WUSER_WIDTH-1:0;\n  localparam BUSER_MAX   = C_AXI_BUSER_WIDTH ? C_AXI_BUSER_WIDTH-1:0;\n  localparam ARUSER_MAX  = C_AXI_ARUSER_WIDTH ? C_AXI_ARUSER_WIDTH-1:0;\n  localparam RUSER_MAX   = C_AXI_RUSER_WIDTH ? C_AXI_RUSER_WIDTH-1:0;\n  localparam STRB_MAX    = C_AXI_DATA_WIDTH/8-1;\n  localparam STRB_1      = {{STRB_MAX{1'b0}}, 1'b1};\n\n  wire    [LP_EXMON_WIDTH-1:0] ExclIdWrPtr;\n  reg               [ID_MAX:0] ExclId[EXMON_HI:0];\n  reg                          ExclIdDelta;\n  reg             [EXMON_HI:0] ExclIdValid;\n  wire                         ExclIdFull;\n  reg     [LP_EXMON_WIDTH-1:0] ExclIdFreePtr;\n  reg                          ExclAwMatch;\n  reg     [LP_EXMON_WIDTH-1:0] ExclArId;\n  reg                          ExclArMatch;\n  reg     [LP_EXMON_WIDTH-1:0] ExclRId;\n  reg                          ExclRMatch;\n  reg                          ExclReadAddr[EXMON_HI:0];\n  reg                          ExclReadData[EXMON_HI:0];\n  reg      [LP_ADDR_WIDTH-1:0] ExclAddr[EXMON_HI:0];\n  reg                    [2:0] ExclSize[EXMON_HI:0];\n  reg                    [7:0] ExclLen[EXMON_HI:0];\n  reg                    [1:0] ExclBurst[EXMON_HI:0];\n  reg                    [3:0] ExclCache[EXMON_HI:0];\n  reg                    [2:0] ExclProt[EXMON_HI:0];\n  reg                    [3:0] ExclQos[EXMON_HI:0];\n  reg                    [3:0] ExclRegion[EXMON_HI:0];\n  reg [C_AXI_AWUSER_WIDTH-1:0] ExclUser[EXMON_HI:0];\n\n\n//------------------------------------------------------------------------------\n// INDEX:   2) Combinatorial Logic\n//------------------------------------------------------------------------------\n\n  //----------------------------------------------------------------------------\n  // INDEX:      a) Masks\n  //----------------------------------------------------------------------------\n\n  // INDEX:           - AlignMaskR\n  // =====\n  // Calculate wrap mask for read address\n  always @(ARSIZE or ARVALID)\n  begin\n    if (ARVALID)\n      case (ARSIZE)\n        `AXI4PC_ASIZE_1024:  AlignMaskR = 7'b0000000;\n        `AXI4PC_ASIZE_512:   AlignMaskR = 7'b1000000;\n        `AXI4PC_ASIZE_256:   AlignMaskR = 7'b1100000;\n        `AXI4PC_ASIZE_128:   AlignMaskR = 7'b1110000;\n        `AXI4PC_ASIZE_64:    AlignMaskR = 7'b1111000;\n        `AXI4PC_ASIZE_32:    AlignMaskR = 7'b1111100;\n        `AXI4PC_ASIZE_16:    AlignMaskR = 7'b1111110;\n        `AXI4PC_ASIZE_8:     AlignMaskR = 7'b1111111;\n        default:             AlignMaskR = 7'b1111111;\n      endcase\n    else\n      AlignMaskR = 7'b1111111;\n  end\n\n\n  // INDEX:           - AlignMaskW\n  // =====\n  // Calculate wrap mask for write address\n  always @(AWSIZE or AWVALID)\n  begin\n    if (AWVALID)\n      case (AWSIZE)\n        `AXI4PC_ASIZE_1024:  AlignMaskW = 7'b0000000;\n        `AXI4PC_ASIZE_512:   AlignMaskW = 7'b1000000;\n        `AXI4PC_ASIZE_256:   AlignMaskW = 7'b1100000;\n        `AXI4PC_ASIZE_128:   AlignMaskW = 7'b1110000;\n        `AXI4PC_ASIZE_64:    AlignMaskW = 7'b1111000;\n        `AXI4PC_ASIZE_32:    AlignMaskW = 7'b1111100;\n        `AXI4PC_ASIZE_16:    AlignMaskW = 7'b1111110;\n        `AXI4PC_ASIZE_8:     AlignMaskW = 7'b1111111;\n        default:             AlignMaskW = 7'b1111111;\n      endcase // case(AWSIZE)\n    else\n      AlignMaskW = 7'b1111111;\n  end\n\n\n  // INDEX:           - ExclMask\n  // =====\n  always @(ARLEN or ARSIZE)\n  begin : p_ExclMaskComb\n    ExclMask = ~((({7'b000_0000, ARLEN} + 15'b000_0000_0000_0001) << ARSIZE) - 15'b000_0000_0000_0001);\n  end // block: p_ExclMaskComb\n\n\n  //----------------------------------------------------------------------------\n  // INDEX:      b) Increments\n  //----------------------------------------------------------------------------\n\n  // INDEX:           - ArAddrIncr\n  // =====\n  always @(ARSIZE or ARLEN or araddr)\n  begin : p_RAddrIncrComb\n    ArAddrIncr = araddr + (ARLEN << ARSIZE);  // The final address of the burst\n  end\n\n\n  // INDEX:           - AwAddrIncr\n  // =====\n  always @(AWSIZE or AWLEN or awaddr)\n  begin : p_WAddrIncrComb\n    AwAddrIncr = awaddr + (AWLEN << AWSIZE);  // The final address of the burst\n  end\n\n\n  //----------------------------------------------------------------------------\n  // INDEX:      c) Conversions\n  //----------------------------------------------------------------------------\n\n  // INDEX:           - ArLenInBytes\n  // =====\n  always @(ARSIZE or ARLEN)\n  begin : p_ArLenInBytes\n    // bytes = (ARLEN+1) data transfers x ARSIZE bytes\n    ArLenInBytes = (({8'h00, ARLEN} + 16'h001) << ARSIZE); \n  end\n\n\n  // INDEX:           - ArSizeInBits\n  // =====\n  always @(ARSIZE)\n  begin : p_ArSizeInBits\n    ArSizeInBits = (11'b000_0000_1000 << ARSIZE); // bits = 8 x ARSIZE bytes\n  end\n\n\n  // INDEX:           - AwSizeInBits\n  // =====\n  always @(AWSIZE)\n  begin : p_AwSizeInBits\n    AwSizeInBits = (11'b000_0000_1000 << AWSIZE); // bits = 8 x AWSIZE bytes\n  end\n\n\n  //----------------------------------------------------------------------------\n  // INDEX:      d) Other\n  //----------------------------------------------------------------------------\n\n  // INDEX:           - ArExclPending\n  // =====\n  // Avoid putting on assertion directly as index is an integer\n  assign ArExclPending = RBurstCam[EXCL]; // ### Rewritten\n\n  // INDEX:           - ArLenPending\n  // =====\n  // Avoid putting on assertion directly as index is an integer\n  assign ArLenPending = {1'b0, RBurstCam[ALENHI:ALENLO]}; // ### Rewritten\n\n  // INDEX:           - ArCountPending\n  // =====\n  // Avoid putting on assertion directly as index is an integer\n  assign ArCountPending = RCountCam; // ### Rewritten\n\n\n//------------------------------------------------------------------------------\n// INDEX:   3) EXCL Accesses\n//------------------------------------------------------------------------------\n\n  // INDEX:        - Exclusive Access ID Lookup\n  // =====\n  // Map transaction IDs to the available exclusive access storage loactions\n\n  // Lookup table for IDs used by the exclusive access monitor\n  // Each location in the table has a valid flag to indicate if the ID is in use\n  // The location of an ID flagged as valid is used as a virtual ID in the\n  // exclusive access monitor checks\n  always @(posedge ACLK)\n  begin : p_ExclIdSeq\n    integer i;  // loop counter\n    if (!checker_main_resetn)\n    begin\n      ExclIdValid <= {EXMON_HI+1{1'b0}};\n      ExclIdDelta <= 1'b0;\n      for (i = 0; i <= EXMON_HI; i = i + 1)\n      begin\n        ExclId[i] <= {ID_MAX+1{1'b0}};\n      end\n    end else if (EXMON_WIDTH > 0) // clk edge\n    begin\n      // exclusive read address transfer\n      if (ARVALID && ARREADY && (internal_ARLOCK == `AXI4PC_ALOCK_EXCL) &&\n          !ExclIdFull)\n      begin\n        ExclId[ExclIdWrPtr] <= ARID;\n        ExclIdValid[ExclIdWrPtr] <= 1'b1;\n        ExclIdDelta <= ~ExclIdDelta;\n      end\n      // exclusive write\n      if (AWVALID && AWREADY && (internal_AWLOCK == `AXI4PC_ALOCK_EXCL) &&\n          ExclAwMatch)\n      begin\n        ExclIdValid[ExclAwId] <= 1'b0;\n        ExclIdDelta <= ~ExclIdDelta;\n      end\n    end // else: !if(!checker_main_resetn)\n  end // block: p_ExclIdSeq\n\n  // Lookup table is full when all valid bits are set\n  assign ExclIdFull = &ExclIdValid;\n\n  // Lookup table overflows when it is full and another exclusive read happens\n  // with an ID that does not match any already being monitored\n  assign ExclIdOverflow = ExclIdFull &&\n                          ARVALID && ARREADY && (internal_ARLOCK == `AXI4PC_ALOCK_EXCL) &&\n                          !ExclArMatch;\n\n  // New IDs are written to the highest location\n  // that does not have the valid flag set \n  always @(ExclIdValid)\n  begin : p_ExclIdFreePtrComb\n    integer i;  // loop counter\n    ExclIdFreePtr = 0;\n    for (i = 0; i <= EXMON_HI; i = i + 1)\n    begin\n      if (ExclIdValid[i] == 1'b0)\n      begin\n        ExclIdFreePtr = i;\n      end\n    end\n  end // p_ExclIdFreePtrComb\n\n  // If the ID is already being monitored then reuse the location\n  // New IDs are written to the highest location\n  // that does not have the valid flag set \n  assign ExclIdWrPtr = ExclArMatch ? ExclArId : ExclIdFreePtr;\n\n  // Write address ID comparator\n//  always @(AWVALID or AWID or ExclIdValid or ExclIdDelta or ExclId)\n  always @( * )\n  begin : p_ExclAwMatchComb\n    integer i;  // loop counter\n    ExclAwMatch = 1'b0;\n    ExclAwId = {LP_EXMON_WIDTH{1'b0}};\n    if (AWVALID)\n    begin\n      for (i = 0; i <= EXMON_HI; i = i + 1)\n      begin\n        if (ExclIdValid[i] && (AWID == ExclId[i]))\n        begin\n          ExclAwMatch = 1'b1;\n          ExclAwId = i;\n        end\n      end\n    end\n  end // p_ExclAwMatchComb\n\n  // Read address ID comparator\n//  always @(ARVALID or ARID or ExclIdValid or ExclIdDelta or ExclId)\n  always @( * )\n  begin : p_ExclArMatchComb\n    integer i;  // loop counter\n    ExclArMatch = 1'b0;\n    ExclArId = {LP_EXMON_WIDTH{1'b0}};\n    if (ARVALID)\n    begin\n      for (i = 0; i <= EXMON_HI; i = i + 1)\n      begin\n        if (ExclIdValid[i] && (ARID == ExclId[i]))\n        begin\n          ExclArMatch = 1'b1;\n          ExclArId = i;\n        end\n      end\n    end\n  end // p_ExclArMatchComb\n\n  // Read data ID comparator\n  always @( * )\n  begin : p_ExclRMatchComb\n    integer i;  // loop counter\n    ExclRMatch = 1'b0;\n    ExclRId = {LP_EXMON_WIDTH{1'b0}};\n    if (RVALID)\n    begin\n      for (i = 0; i <= EXMON_HI; i = i + 1)\n      begin\n        if (ExclIdValid[i] && (RID == ExclId[i]))\n        begin\n          ExclRMatch = 1'b1;\n          ExclRId = i;\n        end\n      end\n    end\n  end // p_ExclRMatchComb\n\n  // INDEX:        - Exclusive Access Storage\n  // =====\n  // Store exclusive control info on each read for checking against write\n\n  always @(posedge ACLK)\n  begin : p_ExclCtrlSeq\n    integer i;  // loop counter\n\n    if (!checker_main_resetn)\n      for (i = 0; i <= EXMON_HI; i = i + 1)\n      begin\n        ExclReadAddr[i] <= 1'b0;\n        ExclReadData[i] <= 1'b0;\n        ExclAddr[i]     <= {LP_ADDR_WIDTH{1'b0}};\n        ExclSize[i]     <= 3'b000;\n        ExclLen[i]      <= {8{1'b0}};\n        ExclBurst[i]    <= 2'b00;\n        ExclCache[i]    <= {4{1'b0}};\n        ExclProt[i]     <= {3{1'b0}};\n        ExclQos[i]      <= {4{1'b0}};\n        ExclRegion[i]   <= {4{1'b0}};\n        ExclUser[i]     <= {ARUSER_MAX+1{1'b0}};\n      end\n    else if (EXMON_WIDTH > 0) // clk edge\n    begin\n      // exclusive read address transfer\n      if (ARVALID && ARREADY && (internal_ARLOCK == `AXI4PC_ALOCK_EXCL) &&\n          !ExclIdFull)\n      begin\n        ExclReadAddr[ExclIdWrPtr] <= 1'b1; // set exclusive read addr flag for ARID\n        ExclReadData[ExclIdWrPtr] <= 1'b0; // reset exclusive read data flag for ARID\n        ExclAddr[ExclIdWrPtr]     <= araddr;\n        ExclSize[ExclIdWrPtr]     <= ARSIZE;\n        ExclLen[ExclIdWrPtr]      <= ARLEN;\n        ExclBurst[ExclIdWrPtr]    <= ARBURST;\n        ExclCache[ExclIdWrPtr]    <= ARCACHE;\n        ExclProt[ExclIdWrPtr]     <= ARPROT;\n        ExclQos[ExclIdWrPtr]      <= ARQOS;\n        ExclRegion[ExclIdWrPtr]   <= ARREGION;\n        ExclUser[ExclIdWrPtr]     <= ARUSER;\n      end\n      // exclusive write\n      if (AWVALID && AWREADY && (internal_AWLOCK == `AXI4PC_ALOCK_EXCL) &&\n          ExclAwMatch)\n      begin\n        ExclReadAddr[ExclAwId] <= 1'b0; // reset exclusive address flag for AWID\n        ExclReadData[ExclAwId] <= 1'b0; // reset exclusive read data flag for AWID\n      end\n      // completion of exclusive read data transaction\n      if ((RVALID && RREADY && RLAST && ExclReadAddr[ExclRId] &&\n           ExclRMatch) &&\n           // check the read CAM that this is part of an exclusive transfer\n           RBurstCam[EXCL] // ### Rewritten\n         )\n        ExclReadData[ExclRId]  <= 1'b1; // set exclusive read data flag for RID\n    end // else: !if(!checker_main_resetn)\n  end // block: p_ExclCtrlSeq\n\n//------------------------------------------------------------------------------\n// INDEX:   4) Content addressable memories (CAMs)\n//------------------------------------------------------------------------------\n\n  assign WriteDataNumError = WDataNumError1;\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Instantiation\n  /////////////////////////////////////////////////////////////////////////////\n\n  assign i_RecommendOn  = (RecommendOn == 0)     ? 1'b0 : 1'b1;\n  assign i_RecMaxWaitOn = (RecommendWaitOn == 0) ? 1'b0 : 1'b1;\n\n  assign ExclAddr_indexed     = ExclAddr[ExclAwId];\n  assign ExclSize_indexed     = ExclSize[ExclAwId];\n  assign ExclLen_indexed      = ExclLen[ExclAwId];\n  assign ExclBurst_indexed    = ExclBurst[ExclAwId];\n  assign ExclCache_indexed    = ExclCache[ExclAwId];\n  assign ExclProt_indexed     = ExclProt[ExclAwId];\n  assign ExclRegion_indexed   = ExclRegion[ExclAwId];\n  assign ExclReadAddr_indexed = ExclReadAddr[ExclAwId];\n  assign ExclReadData_indexed = ExclReadData[ExclAwId];\n\n  axi_protocol_checker_v1_1_12_axi4pc_asr_inline #\n  (\n     .DATA_WIDTH   (C_AXI_DATA_WIDTH),\n     .ID_WIDTH     (C_AXI_ID_WIDTH),\n     .AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),\n     .WUSER_WIDTH  (C_AXI_WUSER_WIDTH),\n     .BUSER_WIDTH  (C_AXI_BUSER_WIDTH),\n     .ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),\n     .RUSER_WIDTH  (C_AXI_RUSER_WIDTH),\n     .MAXRBURSTS   (MAXRBURSTS),\n     .MAXWBURSTS   (MAXWBURSTS),\n     .ADDR_WIDTH   (LP_ADDR_WIDTH),\n     .DATA_MAX     (DATA_MAX),\n     .ADDR_MAX     (LP_ADDR_WIDTH - 1),\n     .STRB_WIDTH   (STRB_WIDTH),\n     .STRB_MAX     (STRB_MAX),\n     .ID_MAX       (ID_MAX),\n     .AWUSER_MAX   (AWUSER_MAX),\n     .WUSER_MAX    (WUSER_MAX),\n     .BUSER_MAX    (BUSER_MAX),\n     .ARUSER_MAX   (ARUSER_MAX),\n     .RUSER_MAX    (RUSER_MAX),\n     .MAX_AW_WAITS (MAX_AW_WAITS),\n     .MAX_AR_WAITS (MAX_AR_WAITS),\n     .MAX_W_WAITS  (MAX_W_WAITS),\n     .MAX_R_WAITS  (MAX_R_WAITS),\n     .MAX_B_WAITS  (MAX_B_WAITS)\n   )\n  i_Axi4PC_asr_inline\n  (\n     .Axi4PC_asr_inline_out (Axi4PC_asr_inline_out),\n     .reset                 (resetn_out),\n     .AWVALID               (AWVALID),\n     .AWBURST               (AWBURST),\n     .AwAddrIncr            (AwAddrIncr),\n     .AWADDR                (awaddr),\n     .ACLK                  (ACLK),\n     .AlignMaskW            (AlignMaskW),\n     .AWLEN                 (AWLEN),\n     .AWLOCK                (internal_AWLOCK),\n     .AWCACHE               (AWCACHE),\n     .AwSizeInBits          (AwSizeInBits),\n     .ARESETn               (ARST_N),\n     .AWREADY               (AWREADY),\n     .AWID                  (AWID),\n     .AWPROT                (AWPROT),\n     .AWSIZE                (AWSIZE),\n     .AWQOS                 (AWQOS),\n     .AWREGION              (AWREGION),\n     .i_RecommendOn         (i_RecommendOn),\n     .i_RecMaxWaitOn        (i_RecMaxWaitOn),\n     .WriteDataNumError     (WriteDataNumError),\n     .BStrbError            (BStrbError),\n     .WVALID                (WVALID),\n     .WREADY                (WREADY),\n     .WDATA                 (WDATA),\n     .WLAST                 (WLAST),\n     .WSTRB                 (WSTRB),\n     .BrespErrorLast        (1'b0),\n     .BrespExokError        (1'b0),\n     .BVALID                (BVALID),\n     .BrespErrorLead        (BrespErrorLead),\n     .BREADY                (BREADY),\n     .BID                   (BID),\n     .BRESP                 (BRESP),\n     .ARVALID               (ARVALID),\n     .ARBURST               (ARBURST),\n     .ArAddrIncr            (ArAddrIncr),\n     .ARADDR                (araddr),\n     .AlignMaskR            (AlignMaskR),\n     .ARLEN                 (ARLEN),\n     .ARLOCK                (internal_ARLOCK),\n     .ARCACHE               (ARCACHE),\n     .ArSizeInBits          (ArSizeInBits),\n     .ARREADY               (ARREADY),\n     .ARID                  (ARID),\n     .ARPROT                (ARPROT),\n     .ARSIZE                (ARSIZE),\n     .ARQOS                 (ARQOS),\n     .ARREGION              (ARREGION),\n     .RVALID                (RVALID),\n     .RREADY                (RREADY),\n     .ArCountPending        (ArCountPending),\n     .ArLenPending          (ArLenPending),\n     .RLAST                 (RLAST),\n     .RidMatch              (RidMatch),\n     .RRESP                 (RRESP),\n     .ArExclPending         (ArExclPending),\n     .RDATA                 (RDATA),\n     .RID                   (RID),\n     .CSYSREQ               (1'b0),\n     .CSYSACK               (1'b0),\n     .ExclMask              (ExclMask),\n     .ExclReadAddr          (ExclReadAddr_indexed),\n     .ExclAwMatch           (ExclAwMatch),\n     .ExclAddr              (ExclAddr_indexed),\n     .ExclSize              (ExclSize_indexed),\n     .ExclLen               (ExclLen_indexed),\n     .ExclBurst             (ExclBurst_indexed),\n     .ExclCache             (ExclCache_indexed),\n     .ExclProt              (ExclProt_indexed),\n     .ExclRegion            (ExclRegion_indexed),\n     .ArLenInBytes          (ArLenInBytes),\n     .ExclReadData          (ExclReadData_indexed),\n     .AWUSER                (AWUSER),\n     .WUSER                 (WUSER),\n     .BUSER                 (BUSER),\n     .ARUSER                (ARUSER),\n     .RUSER                 (RUSER)\n   );\n\n\n  generate\n    if (C_AXI_PROTOCOL == 2) begin : LITE\n      axi_protocol_checker_v1_1_12_axi4litepc_asr_inline #\n      (\n         .DATA_WIDTH (C_AXI_DATA_WIDTH)\n       )\n      i_Axi4LitePC_asr_inline\n      (\n         .Axi4LitePC_asr_inline_out (Axi4LitePC_asr_inline_out),\n         .reset                     (resetn_out),\n         .BVALID                    (BVALID),\n         .BRESP                     (BRESP),\n         .ACLK                      (ACLK),\n         .RVALID                    (RVALID),\n         .RRESP                     (RRESP)\n       );\n    end else begin : NO_LITE\n      assign Axi4LitePC_asr_inline_out = 3'b000;\n    end\n  endgenerate\n  \n\n  /////////////////////////////////////////////////////////////////////////////\n  // Error output masking and latching\n  /////////////////////////////////////////////////////////////////////////////\n\n  reg  [C_ERROR_COUNT-1:0] pc_status_i;\n  wire [C_ERROR_COUNT-1:0] pc_status_masked;\n\n  assign pc_status_masked = {xilinx_inline_out, Axi4LitePC_asr_inline_out, Axi4PC_aux, Axi4PC_asr_inline_out[78:1]};\n\n  always @(posedge ACLK)\n  begin : p_errorSeq\n    if (!checker_main_resetn) begin\n      pc_status_i <= {C_ERROR_COUNT {1'b0}};\n    end else begin\n      pc_status_i <= pc_status_masked | pc_status_i;\n    end\n  end\n\n  assign pc_status = pc_status_i;\n\n  assign AWPush = AWREADY & AWVALID;\n  assign WLastPush = WVALID & WREADY & WLAST;\n\n  /////////////////////////////////////////////////////////////////////////////\n  //AW-W checks\n  axi_protocol_checker_v1_1_12_syn_fifo # (\n    .C_DATA_WIDTH (WASIZEHI+1+8+C_AXI_ID_WIDTH),\n    .C_ADDR_WIDTH (log2(MAXWBURSTS))\n   ) AWCMD (\n    .clk      (ACLK),\n    .rst      (!checker_main_resetn),\n    .data_in  ({AWID,AWLEN,AWSIZE,awaddr[WADDRHI:WADDRLO]}),\n    .rd       (wcheckPop),\n    .wr       (AWPush),\n    .data_out ({AWIDOut, AWLENOut,AWStrbsizeOut, AWStrbAddrOut}),\n    .empty    (AWEmpty),\n    .full     (AWFull)\n  );\n  \n  axi_protocol_checker_v1_1_12_syn_fifo # (\n    .C_DATA_WIDTH (9+STRB_MAX+1),\n    .C_ADDR_WIDTH (log2(MAXWBURSTS))\n   ) WCHECK (\n    .clk      (ACLK),\n    .rst      (!checker_main_resetn),\n    .data_in  ({WCountIn,WstrbIn}),\n    .rd       (wcheckPop),\n    .wr       (WLastPush),\n    .data_out ({WCheckCountOut, WCheckstrbOut}),\n    .empty    (WCheckEmpty),\n    .full     (WCheckFull)\n  );\n\n  assign WstrbIn = (first_strb) ? WSTRB : WSTRBq;\n  assign wcheckPop = (!WCheckEmpty & !AWEmpty);\n\n  always @(posedge ACLK) begin : p_wstrb\n    if (!checker_main_resetn | (WVALID & WREADY & WLAST)) begin\n      WSTRBq <= {C_AXI_DATA_WIDTH/8{1'b0}};\n      first_strb <= 1'b1;\n    end else if (WVALID & WREADY & first_strb) begin\n      first_strb <= 1'b0;\n      WSTRBq <= WSTRB;\n    end\n  end\n\ninteger id_cnt;\n\nlocalparam L_CHECK_PIPE_WIDTH = 7;\n\nreg   [STRB_MAX:0] StrbMask_q1;  \nreg   [STRB_MAX:0] StrbMask_q2;  \nreg   [STRB_MAX:0] StrbMask_q3_n;  \n\nreg          [6:0] StrbAddr_q1;\nreg          [6:0] StrbAddr_q2;\nreg          [2:0] StrbSize_q1;\nreg          [2:0] StrbSize_q2;\nreg   [STRB_MAX:0] Strb_q1;\nreg   [STRB_MAX:0] Strb_q2;\nreg   [STRB_MAX:0] Strb_q3;\nreg          [L_CHECK_PIPE_WIDTH-1:0] wchechPop_shift;\nreg                CheckStrbAssert;\nreg          [6:0] mask_shift_stage_1;\nreg          [6:0] mask_shift_stage_2;\nreg          [6:0] mask_shift_stage_2_q1;\n\nalways @(posedge ACLK) begin\n  StrbAddr_q1 <= AWStrbAddrOut;\n  StrbAddr_q2 <= StrbAddr_q1;\n  StrbSize_q1 <= AWStrbsizeOut;\n  StrbSize_q2 <= StrbSize_q1;\n  Strb_q1 <= WCheckstrbOut;\n  Strb_q2 <= Strb_q1;\n  Strb_q3 <= Strb_q2;\n\n  mask_shift_stage_1 <= (AWStrbAddrOut & ((STRB_1 << AWStrbsizeOut) -  STRB_1));\n  mask_shift_stage_2 <= (AWStrbAddrOut & ((STRB_MAX << AWStrbsizeOut) & STRB_MAX));\n  mask_shift_stage_2_q1 <= mask_shift_stage_2;\n  // The basic strobe for an aligned address\n  StrbMask_q1 <= (STRB_1 << (STRB_1 << AWStrbsizeOut)) - STRB_1;\n  // Zero the unaligned byte lanes\n  // Note: the number of unaligned byte lanes is given by:\n  // (StrbAddr & ((1 << StrbSize) - 1)), i.e. the unaligned part of the\n  // address with respect to the transfer size\n  //\n  // Note! {{STRB_MAX{1'b0}}, 1'b1} gives 1 in the correct vector length\n  StrbMask_q2 <= StrbMask_q1 &                    // Mask off unaligned byte lanes\n    (StrbMask_q1 << mask_shift_stage_1);          // shift the strb mask left by the number of unaligned byte lanes\n\n  StrbMask_q3_n <= ~(StrbMask_q2 << mask_shift_stage_2_q1);\n\nend\n\nlocalparam integer L_NUM_CHKSTRB_NIBS       = (((C_AXI_DATA_WIDTH/8) + 3) / 4);\nlocalparam integer L_NUM_CHKSTRB_NIB_LANES  = ((L_NUM_CHKSTRB_NIBS + 3) / 4) * 4;\nlocalparam integer L_NUM_CHKSTRB_EQ_LANES    = (L_NUM_CHKSTRB_NIB_LANES / 4);\nlocalparam integer L_NUM_CHKSTRB_AND1_LANES  = (L_NUM_CHKSTRB_EQ_LANES + 3) / 4;\nlocalparam integer L_NUM_CHKSTRB_AND2_LANES  = (L_NUM_CHKSTRB_AND1_LANES + 3) / 4;\n\nreg [(4*L_NUM_CHKSTRB_EQ_LANES)-1:0]    CHKSTRB_eq;\nreg [(4*L_NUM_CHKSTRB_AND1_LANES)-1:0]  CHKSTRB_stage_1_eq;\nreg [(4*L_NUM_CHKSTRB_AND2_LANES)-1:0]  CHKSTRB_stage_2_eq;\n\n//assign s_CHKSTRB_sqaa = &CHKSTRB_stage_2_eq;\n\ninteger CHKSTRB_bc;\ninteger CHKSTRB_stage_1;\ninteger CHKSTRB_stage_2;\n\nalways @(posedge ACLK) begin\n  for (CHKSTRB_bc = 0; CHKSTRB_bc < L_NUM_CHKSTRB_EQ_LANES*4; CHKSTRB_bc = CHKSTRB_bc + 1) begin : CHKSTRB_BC_LOOP\n    if (CHKSTRB_bc < ((C_AXI_DATA_WIDTH/8)/4)) begin\n      CHKSTRB_eq[CHKSTRB_bc] <= |(Strb_q3[CHKSTRB_bc*4 +:4] & StrbMask_q3_n[CHKSTRB_bc*4 +: 4]);\n    end else begin\n      CHKSTRB_eq[CHKSTRB_bc] <= 1'b0;\n    end\n  end\n\n  for (CHKSTRB_stage_1 = 0; CHKSTRB_stage_1 < L_NUM_CHKSTRB_AND1_LANES * 4;CHKSTRB_stage_1 = CHKSTRB_stage_1 + 1) begin : CHKSTRB_S1\n    if (CHKSTRB_stage_1 < L_NUM_CHKSTRB_EQ_LANES) begin\n      CHKSTRB_stage_1_eq[CHKSTRB_stage_1] <= |CHKSTRB_eq[CHKSTRB_stage_1*4 +:4];\n    end else begin\n      CHKSTRB_stage_1_eq[CHKSTRB_stage_1] <= 1'b0;\n    end\n  end\n\n  for (CHKSTRB_stage_2 = 0; CHKSTRB_stage_2 < L_NUM_CHKSTRB_AND2_LANES * 4;CHKSTRB_stage_2 = CHKSTRB_stage_2 + 1) begin : CHKSTRB_S2\n    if (CHKSTRB_stage_2 < L_NUM_CHKSTRB_AND1_LANES) begin\n      CHKSTRB_stage_2_eq[CHKSTRB_stage_2] <= |CHKSTRB_stage_1_eq[CHKSTRB_stage_2*4 +:4];\n    end else begin\n      CHKSTRB_stage_2_eq[CHKSTRB_stage_2] <= 1'b0;\n    end\n  end\n\nend\n\n\nalways @(posedge ACLK) begin : bstrb_check\n  if (!checker_main_resetn) begin\n    BStrbError <= 1'b0;\n    wchechPop_shift <= {L_CHECK_PIPE_WIDTH{1'b0}};\n    CheckStrbAssert <= 1'b0;\n  end else begin\n    wchechPop_shift <= {wchechPop_shift[(L_CHECK_PIPE_WIDTH-2):0], wcheckPop};\n    BStrbError <= wchechPop_shift[(L_CHECK_PIPE_WIDTH-1)] & CheckStrbAssert;\n    CheckStrbAssert <= |CHKSTRB_stage_2_eq;\n  end\nend\n\n  always @(posedge ACLK) begin : p_check\n    if (!checker_main_resetn) begin\n      WDataNumError1 <= 1'b0;\n      for (id_cnt = 0; id_cnt <= ID_SIZE; id_cnt = id_cnt + 1) begin\n        AWXferCount[id_cnt] <= {log2(MAXWBURSTS) + 1{1'b0}};\n      end\n      BrespErrorLead <= 1'b0;\n      AWXferCountOverflow <= 1'b0;\n    end else begin\n      WDataNumError1 <= 1'b0;\n      BrespErrorLead <= 1'b0;\n      AWXferCountOverflow <= 1'b0;\n      if (wcheckPop) begin\n        WDataNumError1 <= (WCheckCountOut != {1'b0,AWLENOut});\n      end\n      ////////////////////////////////////////////////////////////////\n      //Count the number of AWID's and BID's\n      if (!(wcheckPop & (BVALID & BREADY) & (BID == AWIDOut))) begin\n        ////////////////////////////////////////////////////////////////\n        //  Increment on AWID - AW+WLast's Complete\n        // Trigger error when \n        if (wcheckPop == 1'b1) begin\n          if (AWXferCount[AWIDOut] == {1'b1,{log2(MAXWBURSTS){1'b0}}}) begin\n            AWXferCountOverflow <= 1'b1;\n          end\n          AWXferCount[AWIDOut] <= AWXferCount[AWIDOut] + 1;\n        end\n        ////////////////////////////////////////////////////////////////\n        //  Decrement on BID  - B Complete\n        if (BVALID & BREADY) begin\n          if (AWXferCount[BID] == 0) begin\n            //Trigger Error of B->{AW or W}\n            BrespErrorLead <= 1'b1;\n          end else begin\n            AWXferCount[BID] <= AWXferCount[BID] - 1;\n          end\n        end\n      end\n    end\n  end\n\n//////////////////////////////////////////////////////////////////////////////////////////////////\n//Xilinx Checks\nwire [2:0]  awready_s;\nwire [2:0]  wready_s;\nwire [2:0]  bready_s;\nwire [2:0]  arready_s;\nwire [2:0]  rready_s;\n\nreg  [2:0]  awready_sq;\nreg  [2:0]  wready_sq;\nreg  [2:0]  bready_sq;\nreg  [2:0]  arready_sq;\nreg  [2:0]  rready_sq;\n\nalways @(posedge ACLK) begin : xil_check\n  if (!resetn_out) begin\n    xilinx_inline_out <= 11'h000;\n    awready_sq <= 3'h4;\n    wready_sq <= 3'h4;\n    bready_sq <= 3'h4;\n    arready_sq <= 3'h4;\n    rready_sq <= 3'h4;\n  end else begin\n    xilinx_inline_out[1] <= (C_PC_SUPPORTS_NARROW_BURST == 0) && (AWVALID && (AWLEN > 0) && (AwSizeInBits < C_AXI_DATA_WIDTH));\n    xilinx_inline_out[2] <= (C_PC_SUPPORTS_NARROW_BURST == 0) && (ARVALID && (ARLEN > 0) && (ArSizeInBits < C_AXI_DATA_WIDTH));\n    xilinx_inline_out[3] <= (C_PC_SUPPORTS_NARROW_BURST == 0) && (AWVALID && (AWLEN > 0) && !(AWCACHE[1]));\n    xilinx_inline_out[4] <= (C_PC_SUPPORTS_NARROW_BURST == 0) && (ARVALID && (ARLEN > 0) && !(ARCACHE[1]));\n    xilinx_inline_out[5] <= (AWVALID && !(AWLEN <= (C_PC_MAX_BURST_LENGTH - 1)));\n    xilinx_inline_out[6] <= (ARVALID && !(ARLEN <= (C_PC_MAX_BURST_LENGTH - 1)));\n\n    //////////////////////////////////////////////////////////////////////////////////////////////////\n    //Xilinx xREADY checks : xREADY is LOW for the first cycle after ARESETn goes HIGH.\n    awready_sq  <= awready_s;\n    wready_sq   <= wready_s;\n    bready_sq   <= bready_s;\n    arready_sq  <= arready_s;\n    rready_sq   <= rready_s;\n\n    xilinx_inline_out[7] <= (awready_s[0]);\n    xilinx_inline_out[8] <= ( wready_s[0]);\n    xilinx_inline_out[9] <= ( bready_s[0]);\n    xilinx_inline_out[10] <= (arready_s[0]);\n    xilinx_inline_out[11] <= ( rready_s[0]);\n  end\nend\n\nassign awready_s  = {1'b1, !(ARST_N), (awready_sq[1] && (ARST_N && AWREADY))};\nassign wready_s   = {1'b1, !(ARST_N), ( wready_sq[1] && (ARST_N &&  WREADY))};\nassign bready_s   = {1'b1, !(ARST_N), ( bready_sq[1] && (ARST_N &&  BREADY))};\nassign arready_s  = {1'b1, !(ARST_N), (arready_sq[1] && (ARST_N && ARREADY))};\nassign rready_s   = {1'b1, !(ARST_N), ( rready_sq[1] && (ARST_N &&  RREADY))};\n\nendmodule\n`default_nettype wire\n\n\n//*****************************************************************************\n// (c) Copyright 2011-2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// Design Name      : axi_protocol_checker_v1_1_12_syn_fifo\n// Function         : synchronous FIFO\n// Reference        : None\n// Revision History : Initial version\n//*****************************************************************************\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_protocol_checker_v1_1_12_syn_fifo #\n  (\n   parameter C_DATA_WIDTH = 8,\n   parameter C_ADDR_WIDTH = 4\n   )\n  (\n   input  wire                    clk,\n   input  wire                    rst,\n\n   input  wire [C_DATA_WIDTH-1:0] data_in,\n   input  wire                    rd,\n   input  wire                    wr,\n   output wire [C_DATA_WIDTH-1:0] data_out,\n   output wire                    empty,\n   output wire                    full\n  );\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Local params\n  /////////////////////////////////////////////////////////////////////////////\n\n  localparam RAM_SIZE = (1 << C_ADDR_WIDTH);\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Internal signals\n  /////////////////////////////////////////////////////////////////////////////\n\n  reg [C_ADDR_WIDTH-1:0] wr_ptr;\n  reg [C_ADDR_WIDTH-1:0] rd_ptr;\n  reg [C_ADDR_WIDTH:0]   cnt;\n\n  (* ram_style=\"distributed\" *)\n  reg [C_DATA_WIDTH-1:0] data_ram[RAM_SIZE-1:0];\n\n  /////////////////////////////////////////////////////////////////////////////\n  // Code\n  /////////////////////////////////////////////////////////////////////////////\n\n  assign full  = (cnt == RAM_SIZE);\n  assign empty = (cnt == 0);\n\n  always @(posedge clk)\n  begin : COUNTER\n    if (rst) begin\n      cnt <= 0;\n    end else if (rd && !wr && (cnt != 0)) begin\n      cnt <= cnt - 1; // Just read: decrement\n    end else if (wr && !rd && (cnt != RAM_SIZE)) begin\n      cnt <= cnt + 1; // Just write: increment\n    end\n  end\n\n  always @(posedge clk)\n  begin : WRITE_PTR\n    if (rst) begin\n      wr_ptr <= 0;\n    end else if (wr) begin\n      wr_ptr <= wr_ptr + 1;\n    end\n  end\n\n  always @(posedge clk)\n  begin : READ_PTR\n    if (rst) begin\n      rd_ptr <= 0;\n    end else if (rd) begin\n      rd_ptr <= rd_ptr + 1;\n    end\n  end\n\n  // Distributed RAM\n  always @(posedge clk)\n  begin\n    if (wr)\n      data_ram[wr_ptr] <= data_in;\n  end\n\n  assign data_out = data_ram[rd_ptr];\n\nendmodule\n\n`default_nettype wire\n\n\n// (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n\n\n`timescale 1ps/1ps\n`default_nettype none\n`ifndef AXI4PC_MESSAGES\n  `define AXI4PC_MESSAGES\n  `define ERRM_AWADDR_BOUNDARY      \"AXI_ERRM_AWADDR_BOUNDARY. A write burst cannot cross a 4kbyte boundary. Spec: section 4.1 on page 4-2.\"\n  `define ERRM_AWADDR_WRAP_ALIGN    \"AXI_ERRM_AWADDR_WRAP_ALIGN. A write transaction with burst type WRAP must have an aligned address. Spec: section 4.4.3 on page 4-6.\"\n  `define ERRM_AWBURST              \"AXI_ERRM_AWBURST. When AWVALID is high, a value of 2'b11 on AWBURST is not permitted. Spec: table 4-3 on page 4-5.\"\n  `define ERRM_AWCACHE              \"AXI_ERRM_AWCACHE. A reserved value on AWCACHE is not allowed. Spec: table 5-1 on page 5-3.\"\n  `define ERRM_ARCACHE              \"AXI_ERRM_ARCACHE. A reserved value on ARCACHE is not allowed. Spec: table 5-1 on page 5-3.\"\n  `define ERRM_AWLEN_WRAP           \"AXI_ERRM_AWLEN_WRAP. A write transaction with burst type WRAP must have length 2, 4, 8 or 16. Spec: section 4.4.3 on page 4-6.\"\n  `define ERRM_AWSIZE               \"AXI_ERRM_AWSIZE. The size of a write transfer must not exceed the width of the data port. Spec: section 4.3 on page 4-4.\"\n  `define ERRM_AWVALID_RESET        \"AXI_ERRM_AWVALID_RESET. AWVALID must be low for the first clock edge that ARESETn goes high. Spec: section 11.1.2 on page 11-2.\"\n  `define ERRM_AWADDR_STABLE        \"AXI_ERRM_AWADDR_STABLE. AWADDR must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWBURST_STABLE       \"AXI_ERRM_AWBURST_STABLE. AWBURST must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWCACHE_STABLE       \"AXI_ERRM_AWCACHE_STABLE. AWCACHE must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWID_STABLE          \"AXI_ERRM_AWID_STABLE. AWID must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWLEN_STABLE         \"AXI_ERRM_AWLEN_STABLE. AWLEN must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWLOCK_STABLE        \"AXI_ERRM_AWLOCK_STABLE. AWLOCK must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWPROT_STABLE        \"AXI_ERRM_AWPROT_STABLE. AWPROT must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWSIZE_STABLE        \"AXI_ERRM_AWSIZE_STABLE. AWSIZE must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWQOS_STABLE         \"AXI_ERRM_AWQOS_STABLE. AWQOS must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWREGION_STABLE      \"AXI_ERRM_AWREGION_STABLE. AWREGION must remain stable when ARVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWVALID_STABLE       \"AXI_ERRM_AWVALID_STABLE. Once AWVALID is asserted, it must remain asserted until AWREADY is high. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWADDR_X             \"AXI_ERRM_AWADDR_X. When AWVALID is high, a value of X on AWADDR is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWBURST_X            \"AXI_ERRM_AWBURST_X. When AWVALID is high, a value of X on AWBURST is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWCACHE_X            \"AXI_ERRM_AWCACHE_X. When AWVALID is high, a value of X on AWCACHE is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWID_X               \"AXI_ERRM_AWID_X. When AWVALID is high, a value of X on AWID is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWLEN_X              \"AXI_ERRM_AWLEN_X. When AWVALID is high, a value of X on AWLEN is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWLOCK_X             \"AXI_ERRM_AWLOCK_X. When AWVALID is high, a value of X on AWLOCK is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWPROT_X             \"AXI_ERRM_AWPROT_X. When AWVALID is high, a value of X on AWPROT is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWSIZE_X             \"AXI_ERRM_AWSIZE_X. When AWVALID is high, a value of X on AWSIZE is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWQOS_X              \"AXI_ERRM_AWQOS_X. When AWVALID is high, a value of X on AWQOS is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWREGION_X           \"AXI_ERRM_AWREGION_X. When AWVALID is high, a value of X on AWREGION is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_AWVALID_X            \"AXI_ERRM_AWVALID_X. When not in reset, a value of X on AWVALID is not permitted.\"\n  `define ERRS_AWREADY_X            \"AXI_ERRS_AWREADY_X. When not in reset, a value of X on AWREADY is not permitted.\"\n  `define ERRM_WDATA_NUM            \"AXI_ERRM_WDATA_NUM. The number of write data items must match AWLEN for the corresponding address. Spec: table 4-1 on page 4-3.\"\n  `define ERRM_WSTRB                \"AXI_ERRM_WSTRB. Write strobes must only be asserted for the correct byte lanes as determined from start address, transfer size and beat number. Spec: section 9.2 on page 9-3.\"\n  `define ERRM_WVALID_RESET         \"AXI_ERRM_WVALID_RESET. WVALID must be low for the first clock edge that ARESETn goes high. Spec: section 11.1.2 on page 11-2.\"\n  `define ERRM_WDATA_STABLE         \"AXI_ERRM_WDATA_STABLE. WDATA must remain stable when WVALID is asserted and WREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_WLAST_STABLE         \"AXI_ERRM_WLAST_STABLE. WLAST must remain stable when WVALID is asserted and WREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_WSTRB_STABLE         \"AXI_ERRM_WSTRB_STABLE. WSTRB must remain stable when WVALID is asserted and WREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_WVALID_STABLE        \"AXI_ERRM_WVALID_STABLE. Once WVALID is asserted, it must remain asserted until WREADY is high. Spec: section 3.1.2 on page 3-3.\"\n  `define ERRM_WDATA_X              \"AXI_ERRM_WDATA_X. When WVALID is high, a value of X on active byte lanes of WDATA is not permitted.\"\n  `define ERRM_WLAST_X              \"AXI_ERRM_WLAST_X. When WVALID is high, a value of X on WLAST is not permitted.\"\n  `define ERRM_WSTRB_X              \"AXI_ERRM_WSTRB_X. When WVALID is high, a value of X on WSTRB is not permitted.\"\n  `define ERRM_WVALID_X             \"AXI_ERRM_WVALID_X. When not in reset, a value of X on WVALID is not permitted.\"\n  `define ERRS_WREADY_X             \"AXI_ERRS_WREADY_X. When not in reset, a value of X on WREADY is not permitted.\"\n  `define ERRS_BRESP_WLAST          \"AXI_ERRS_BRESP_WLAST. A slave must only give a write response after the last write data item is transferred. Spec: section 3.3 on page 3-6, and figure 3-5 on page 3-8.\"\n  `define ERRS_BRESP_ALL_DONE_EOS   \"AXI_ERRS_BRESP_ALL_DONE_EOS. All write transaction addresses must have been matched with corresponding write response.\"\n  `define ERRS_BRESP_EXOKAY         \"AXI_ERRS_BRESP_EXOKAY. An EXOKAY write response can only be given to an exclusive write access. Spec: section 6.2.3 on page 6-4.\"\n  `define ERRS_BVALID_RESET         \"AXI_ERRS_BVALID_RESET. BVALID must be low for the first clock edge that ARESETn goes high. Spec: section 11.1.2 on page 11-2.\"\n  `define ERRS_BRESP_AW             \"AXI_ERRS_BRESP_AW. A slave must not give a write response before the write address. Spec: section 13.4.1 on page 13-6, and figure 13-1 on page 13-6.\"\n  `define ERRS_BID_STABLE           \"AXI_ERRS_BID_STABLE. BID must remain stable when BVALID is asserted and BREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRS_BRESP_STABLE         \"AXI_ERRS_BRESP_STABLE. BRESP must remain stable when BVALID is asserted and BREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRS_BVALID_STABLE        \"AXI_ERRS_BVALID_STABLE. Once BVALID is asserted, it must remain asserted until BREADY is high. Spec: section 3.1.3 on page 3-3.\"\n  `define ERRM_BREADY_X             \"AXI_ERRM_BREADY_X. When not in reset, a value of X on BREADY is not permitted.\"\n  `define ERRS_BID_X                \"AXI_ERRS_BID_X. When BVALID is high, a value of X on BID is not permitted.\"\n  `define ERRS_BRESP_X              \"AXI_ERRS_BRESP_X. When BVALID is high, a value of X on BRESP is not permitted.  Spec: section 3.1.3 on page 3-4.\"\n  `define ERRS_BVALID_X             \"AXI_ERRS_BVALID_X. When not in reset, a value of X on BVALID is not permitted.\"\n  `define ERRM_ARADDR_BOUNDARY      \"AXI_ERRM_ARADDR_BOUNDARY. A read burst cannot cross a 4kbyte boundary. Spec: section 4.1 on page 4-2.\"\n  `define ERRM_ARADDR_WRAP_ALIGN    \"AXI_ERRM_ARADDR_WRAP_ALIGN. A read transaction with burst type WRAP must have an aligned address. Spec: section 4.4.3 on page 4-6.\"\n  `define ERRM_ARBURST              \"AXI_ERRM_ARBURST. When ARVALID is high, a value of 2'b11 on ARBURST is not permitted. Spec: table 4-3 on page 4-5.\"\n  `define ERRM_ARLEN_FIXED          \"AXI_ERRM_ARLEN_FIXED. Transactions of burst type FIXED cannot have a length greater than 16 beats. Spec: section 13.1.2 on page 13-2.\"\n  `define ERRM_AWLEN_FIXED          \"AXI_ERRM_AWLEN_FIXED. Transactions of burst type FIXED cannot have a length greater than 16 beats. Spec: section 13.1.2 on page 13-2.\"\n  `define ERRM_AWLEN_LOCK           \"AXI_ERRM_AWLEN_LOCK. Exclusive access transactions cannot have a length greater than 16 beats. Spec: section 13.1.2 on page 13-2.\"\n  `define ERRM_ARLEN_LOCK           \"AXI_ERRM_ARLEN_LOCK. Exclusive access transactions cannot have a length greater than 16 beats. Spec: section 13.1.2 on page 13-2.\"\n  `define ERRM_ARLEN_WRAP           \"AXI_ERRM_ARLEN_WRAP. A read transaction with burst type WRAP must have length 2, 4, 8 or 16. Spec: section 4.4.3 on page 4-6.\"\n  `define ERRM_ARSIZE               \"AXI_ERRM_ARSIZE. The size of a read transfer must not exceed the width of the data port. Spec: section 4.3 on page 4-4.\"\n  `define ERRM_ARVALID_RESET        \"AXI_ERRM_ARVALID_RESET. ARVALID must be low for the first clock edge that ARESETn goes high. Spec: section 11.1.2 on page 11-2.\"\n  `define ERRM_ARADDR_STABLE        \"AXI_ERRM_ARADDR_STABLE. ARADDR must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARBURST_STABLE       \"AXI_ERRM_ARBURST_STABLE. ARBURST must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARCACHE_STABLE       \"AXI_ERRM_ARCACHE_STABLE. ARCACHE must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARID_STABLE          \"AXI_ERRM_ARID_STABLE. ARID must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARLEN_STABLE         \"AXI_ERRM_ARLEN_STABLE. ARLEN must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARLOCK_STABLE        \"AXI_ERRM_ARLOCK_STABLE. ARLOCK must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARPROT_STABLE        \"AXI_ERRM_ARPROT_STABLE. ARPROT must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARSIZE_STABLE        \"AXI_ERRM_ARSIZE_STABLE. ARSIZE must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARQOS_STABLE         \"AXI_ERRM_ARQOS_STABLE. ARQOS must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARREGION_STABLE      \"AXI_ERRM_ARREGION_STABLE. ARREGION must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARVALID_STABLE       \"AXI_ERRM_ARVALID_STABLE. Once ARVALID is asserted, it must remain asserted until ARREADY is high. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARADDR_X             \"AXI_ERRM_ARADDR_X. When ARVALID is high, a value of X on ARADDR is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARBURST_X            \"AXI_ERRM_ARBURST_X. When ARVALID is high, a value of X on ARBURST is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARCACHE_X            \"AXI_ERRM_ARCACHE_X. When ARVALID is high, a value of X on ARCACHE is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARID_X               \"AXI_ERRM_ARID_X. When ARVALID is high, a value of X on ARID is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARLEN_X              \"AXI_ERRM_ARLEN_X. When ARVALID is high, a value of X on ARLEN is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARLOCK_X             \"AXI_ERRM_ARLOCK_X. When ARVALID is high, a value of X on ARLOCK is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARPROT_X             \"AXI_ERRM_ARPROT_X. When ARVALID is high, a value of X on ARPROT is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARSIZE_X             \"AXI_ERRM_ARSIZE_X. When ARVALID is high, a value of X on ARSIZE is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARQOS_X              \"AXI_ERRM_ARQOS_X. When ARVALID is high, a value of X on ARQOS is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARREGION_X           \"AXI_ERRM_ARREGION_X. When ARVALID is high, a value of X on ARREGION is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRM_ARVALID_X            \"AXI_ERRM_ARVALID_X. When not in reset, a value of X on ARVALID is not permitted.\"\n  `define ERRS_ARREADY_X            \"AXI_ERRS_ARREADY_X. When not in reset, a value of X on ARREADY is not permitted.\"\n  `define ERRS_RDATA_NUM            \"AXI_ERRS_RDATA_NUM. The number of read data items must match the corresponding ARLEN. Spec: table 4-1 on page 4-3.\"\n  `define ERRS_RLAST_ALL_DONE_EOS   \"AXI_ERRS_RLAST_ALL_DONE_EOS. All outstanding read bursts must have completed.\"\n  `define ERRS_RID                  \"AXI_ERRS_RID. A slave can only give read data in response to an outstanding read transaction, and the RID, if any, must match an outstanding ARID. Spec: section 3.1.5 on page 3-4, and section 8.3 on page 8-4.\"\n  `define ERRS_RRESP_EXOKAY         \"AXI_ERRS_RRESP_EXOKAY. An EXOKAY read response can only be given to an exclusive read access. Spec: section 6.2.3 on page 6-4.\"\n  `define ERRS_RVALID_RESET         \"AXI_ERRS_RVALID_RESET. RVALID must be low for the first clock edge that ARESETn goes high. Spec: section 11.1.2 on page 11-2.\"\n  `define ERRS_RDATA_STABLE         \"AXI_ERRS_RDATA_STABLE. RDATA must remain stable when RVALID is asserted and RREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRS_RID_STABLE           \"AXI_ERRS_RID_STABLE. RID must remain stable when RVALID is asserted and RREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRS_RLAST_STABLE         \"AXI_ERRS_RLAST_STABLE. RLAST must remain stable when RVALID is asserted and RREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRS_RRESP_STABLE         \"AXI_ERRS_RRESP_STABLE. RRESP must remain stable when RVALID is asserted and RREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRS_RVALID_STABLE        \"AXI_ERRS_RVALID_STABLE. Once RVALID is asserted, it must remain asserted until RREADY is high. Spec: section 3.1.5 on page 3-4.\"\n  `define ERRS_RDATA_X              \"AXI_ERRS_RDATA_X. When RVALID is high, a value of X on RDATA valid byte lanes is not permitted.\"\n  `define ERRM_RREADY_X             \"AXI_ERRM_RREADY_X. When not in reset, a value of X on RREADY is not permitted.\"\n  `define ERRS_RID_X                \"AXI_ERRS_RID_X. When RVALID is high, a value of X on RID is not permitted.\"\n  `define ERRS_RLAST_X              \"AXI_ERRS_RLAST_X. When RVALID is high, a value of X on RLAST is not permitted.\"\n  `define ERRS_RRESP_X              \"AXI_ERRS_RRESP_X. When RVALID is high, a value of X on RRESP is not permitted.\"\n  `define ERRS_RVALID_X             \"AXI_ERRS_RVALID_X. When not in reset, a value of X on RVALID is not permitted.\"\n  `define ERRL_CSYSACK_FALL         \"AXI_ERRL_CSYSACK_FALL. When CSYSACK transitions from high to low, CSYSREQ must be low. Spec: figure 12-1 on page 12-3.\"\n  `define ERRL_CSYSACK_RISE         \"AXI_ERRL_CSYSACK_RISE. When CSYSACK transitions from low to high, CSYSREQ must be high. Spec: figure 12-1 on page 12-3.\"\n  `define ERRL_CSYSREQ_FALL         \"AXI_ERRL_CSYSREQ_FALL. When CSYSREQ transitions from high to low, CSYSACK must be high. Spec: figure 12-1 on page 12-3.\"\n  `define ERRL_CSYSREQ_RISE         \"AXI_ERRL_CSYSREQ_RISE. When CSYSREQ transitions from low to high, CSYSACK must be low. Spec: figure 12-1 on page 12-3.\"\n  `define ERRL_CACTIVE_X            \"AXI_ERRL_CACTIVE_X. When not in reset, a value of X on CACTIVE is not permitted.\"\n  `define ERRL_CSYSACK_X            \"AXI_ERRL_CSYSACK_X. When not in reset, a value of X on CSYSACK is not permitted.\"\n  `define ERRL_CSYSREQ_X            \"AXI_ERRL_CSYSREQ_X. When not in reset, a value of X on CSYSREQ is not permitted.\"\n  `define ERRM_EXCL_ALIGN           \"AXI_ERRM_EXCL_ALIGN. The address of an exclusive access must be aligned to the total number of bytes in the transaction. Spec: section 6.2.4 on page 6-4.\"\n  `define ERRM_EXCL_LEN             \"AXI_ERRM_EXCL_LEN. The number of bytes to be transferred in an exclusive access burst must be a power of 2. Spec: section 6.2.4 on page 6-4.\"\n  `define ERRM_EXCL_MAX             \"AXI_ERRM_EXCL_MAX. The maximum number of bytes that can be transferred in an exclusive burst is 128. Spec: section 6.2.4 on page 6-4.\"\n  `define ERRM_AWUSER_STABLE        \"AXI_ERRM_AWUSER_STABLE. AWUSER must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_WUSER_STABLE         \"AXI_ERRM_WUSER_STABLE. WUSER must remain stable when WVALID is asserted and WREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRS_BUSER_STABLE         \"AXI_ERRS_BUSER_STABLE. BUSER must remain stable when BVALID is asserted and BREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_ARUSER_STABLE        \"AXI_ERRM_ARUSER_STABLE. ARUSER must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRS_RUSER_STABLE         \"AXI_ERRS_RUSER_STABLE. RUSER must remain stable when RVALID is asserted and RREADY low. Spec: section 3.1, and figure 3-1, on page 3-2.\"\n  `define ERRM_AWUSER_X             \"AXI_ERRM_AWUSER_X. When AWVALID is high, a value of X on AWUSER is not permitted. Spec: section 3.1.1 on page 3-3.\"\n  `define ERRM_WUSER_X              \"AXI_ERRM_WUSER_X. When WVALID is high, a value of X on WUSER is not permitted.\"\n  `define ERRS_BUSER_X              \"AXI_ERRS_BUSER_X. When BVALID is high, a value of X on BUSER is not permitted.\"\n  `define ERRM_ARUSER_X             \"AXI_ERRM_ARUSER_X. When ARVALID is high, a value of X on ARUSER is not permitted. Spec: section 3.1.4 on page 3-4.\"\n  `define ERRS_RUSER_X              \"AXI_ERRS_RUSER_X. When RVALID is high, a value of X on RUSER is not permitted.\"\n  `define ERRM_AWUSER_TIEOFF        \"AXI_ERRM_AWUSER_TIEOFF. AWUSER must be stable when AWUSER_WIDTH is set to 0\" \n  `define ERRM_WUSER_TIEOFF         \"AXI_ERRM_WUSER_TIEOFF. WUSER must be stable when WUSER_WIDTH is set to 0\" \n  `define ERRS_BUSER_TIEOFF         \"AXI_ERRS_BUSER_TIEOFF. BUSER must be stable when BUSER_WIDTH is set to 0\" \n  `define ERRM_ARUSER_TIEOFF        \"AXI_ERRM_ARUSER_TIEOFF. ARUSER must be stable when ARUSER_WIDTH is set to 0\" \n  `define ERRS_RUSER_TIEOFF         \"AXI_ERRS_RUSER_TIEOFF. RUSER must be stable when RUSER_WIDTH is set to 0\" \n  `define ERRM_AWID_TIEOFF          \"AXI_ERRM_AWID_TIEOFF. AWID must be stable when ID_WIDTH is set to 0\" \n  `define ERRS_BID_TIEOFF           \"AXI_ERRS_BID_TIEOFF. BID must be stable when ID_WIDTH is set to 0\" \n  `define ERRM_ARID_TIEOFF          \"AXI_ERRM_ARID_TIEOFF. ARID must be stable when ID_WIDTH is set to 0\" \n  `define ERRS_RID_TIEOFF           \"AXI_ERRS_RID_TIEOFF. RID must be stable when ID_WIDTH is set to 0\" \n  `define AUXM_DATA_WIDTH           \"AXI_AUXM_DATA_WIDTH. Parameter DATA_WIDTH must be 32, 64, 128, 256, 512 or 1024\"\n  `define AUXM_ADDR_WIDTH           \"AXI_AUXM_ADDR_WIDTH. Parameter ADDR_WIDTH must be between 32 and 64 bits inclusive\"\n  `define AUXM_EXMON_WIDTH          \"AXI_AUXM_EXMON_WIDTH. Parameter EXMON_WIDTH must be greater than or equal to 1\"\n  `define AUXM_MAXRBURSTS           \"AXI_AUXM_MAXRBURSTS. Parameter MAXRBURSTS must be greater than or equal to 1\"\n  `define AUXM_MAXWBURSTS           \"AXI_AUXM_MAXWBURSTS. Parameter MAXWBURSTS must be greater than or equal to 1\"\n  `define AUXM_RCAM_OVERFLOW        \"AXI_AUXM_RCAM_OVERFLOW. Read CAM overflow, increase Maximum outstanding READ Transactions per ID (MAX_RD_BURSTS) parameter.\"\n  `define AUXM_RCAM_UNDERFLOW       \"AXI_AUXM_RCAM_UNDERFLOW. Read CAM underflow.\"\n  `define AUXM_WCAM_OVERFLOW        \"AXI_AUXM_WCAM_OVERFLOW. Write CAM overflow, increase Maximum outstanding WRITE Transactions per ID (MAX_WR_BURSTS) parameter.\"\n  `define AUXM_WCAM_UNDERFLOW       \"AXI_AUXM_WCAM_UNDERFLOW. Write CAM underflow\"\n  `define AUXM_EXCL_OVERFLOW        \"AXI_AUXM_EXCL_OVERFLOW. Exclusive access monitor overflow, increase EXMON_WIDTH parameter.\"\n  `define RECM_EXCL_PAIR            \"AXI_RECM_EXCL_PAIR. An exclusive write should have an earlier outstanding completed exclusive read with the same ID. Spec: section 6.2.2 on page 6-3.\"\n  `define RECS_AWREADY_MAX_WAIT     \"AXI_RECS_AWREADY_MAX_WAIT. AWREADY should be asserted within MAXWAITS cycles of AWVALID being asserted.\"\n  `define RECS_WREADY_MAX_WAIT      \"AXI_RECS_WREADY_MAX_WAIT. WREADY should be asserted within MAXWAITS cycles of WVALID being asserted.\"\n  `define RECM_BREADY_MAX_WAIT      \"AXI_RECM_BREADY_MAX_WAIT. BREADY should be asserted within MAXWAITS cycles of BVALID being asserted.\"\n  `define RECS_ARREADY_MAX_WAIT     \"AXI_RECS_ARREADY_MAX_WAIT. ARREADY should be asserted within MAXWAITS cycles of ARVALID being asserted.\"\n  `define RECM_RREADY_MAX_WAIT      \"AXI_RECM_RREADY_MAX_WAIT. RREADY should be asserted within MAXWAITS cycles of RVALID being asserted.\"\n  `define RECM_EXCL_MATCH           \"AXI_RECM_EXCL_MATCH. The address, size and length of an exclusive write should be the same as the preceding exclusive read with the same ID. Spec: section 6.2.4 on page 6-4.\"\n  `define ERRS_AXI4LITE_BRESP_EXOKAY   \"AXI4LITE_ERRS_BRESP_EXOKAY. A slave must not give an EXOKAY response on an Axi4Lite interface. Spec: section 14.2.2 on page 14-3.\"\n  `define ERRS_AXI4LITE_RRESP_EXOKAY   \"AXI4LITE_ERRS_RRESP_EXOKAY. A slave must not give an EXOKAY response on an Axi4Lite interface. Spec: section 14.2.2 on page 14-3.\"\n  `define AUXM_AXI4LITE_DATA_WIDTH     \"AXI4LITE_AUXM_DATA_WIDTH. Parameter DATA_WIDTH must be either 32 or 64.\"\n  `define XILINX_AW_SUPPORTS_NARROW_BURST    \"XILINX_AW_SUPPORTS_NARROW_BURST. AW Narrow burst issued from MASTER. Connection has been declared to NOT support narrow bursts.\"\n  `define XILINX_AR_SUPPORTS_NARROW_BURST    \"XILINX_AR_SUPPORTS_NARROW_BURST. AR Narrow burst issued from MASTER. Connection has been declared to NOT support narrow bursts.\"\n  `define XILINX_AW_SUPPORTS_NARROW_CACHE    \"XILINX_AW_SUPPORTS_NARROW_CACHE. AW Non-modifiable burst issued from MASTER. Connection has been declared to NOT support narrow bursts.\"\n  `define XILINX_AR_SUPPORTS_NARROW_CACHE    \"XILINX_AR_SUPPORTS_NARROW_CACHE. AR Non-modifiable burst issued from MASTER. Connection has been declared to NOT support narrow bursts.\"\n  `define XILINX_AW_MAX_BURST                \"XILINX_AW_MAX_BURST. AW MASTER has issued a burst longer than the declared MAXIMUM.\"\n  `define XILINX_AR_MAX_BURST                \"XILINX_AR_MAX_BURST. AR MASTER has issued a burst longer than the declared MAXIMUM.\"\n  `define XILINX_AWREADY_RESET               \"XILINX_AWREADY_RESET. AWREADY must be low for the first clock edge that ARESETn goes high.\"\n  `define XILINX_WREADY_RESET                \"XILINX_WREADY_RESET. WREADY must be low for the first clock edge that ARESETn goes high.\"\n  `define XILINX_BREADY_RESET                \"XILINX_BREADY_RESET. BREADY must be low for the first clock edge that ARESETn goes high.\"\n  `define XILINX_ARREADY_RESET               \"XILINX_ARREADY_RESET. ARREADY must be low for the first clock edge that ARESETn goes high.\"\n  `define XILINX_RREADY_RESET                \"XILINX_RREADY_RESET. RREADY must be low for the first clock edge that ARESETn goes high.\"\n`endif\n\n`define REPORTER_MACRO(ERR_BIT, NET_NAME, MSG_TEXT, SEV_NUM) \\\n  always@(posedge NET_NAME) begin \\\n    if ((SEV_NUM != 0) && (NET_NAME === 1'b1)) begin \\\n      $display(\"%t : %m : BIT(%d) : %s : %s\", $time, ERR_BIT, (SEV_NUM == 0) ? \"INFO\" : (SEV_NUM == 1) ? \"WARNING\" : \"ERROR\" , MSG_TEXT); \\\n      if (SEV_NUM == 3) $stop;\\\n      if (SEV_NUM == 4) $finish;\\\n    end else if ((NET_NAME !== 1'b1) && (NET_NAME !== 1'b0)) begin \\\n      $display(\"%t : %m : BIT(%d) :   ERROR : Invalid state %b\", $time, ERR_BIT, NET_NAME); \\\n    end \\\n  end\n\n`define ASSIGN_MARKED_DEBUG(ERR_BIT, DISPLAY_NETNAME) \\\n  (* mark_debug = \"true\" *) reg DISPLAY_NETNAME;\\\n  always@(posedge aclk) DISPLAY_NETNAME <= pc_status[ERR_BIT];\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *) \nmodule axi_protocol_checker_v1_1_12_reporter #(\n  parameter integer C_PC_MESSAGE_LEVEL             = 2,\n  parameter integer C_PC_STATUS_WIDTH              = 97\n) (\n  input  wire                             aclk,\n  input  wire [C_PC_STATUS_WIDTH-1:0]     pc_status\n);\n\n`ASSIGN_MARKED_DEBUG(00, PC_00_AXI_ERRM_AWADDR_BOUNDARY          )\n`ASSIGN_MARKED_DEBUG(01, PC_01_AXI_ERRM_AWADDR_WRAP_ALIGN        )\n`ASSIGN_MARKED_DEBUG(02, PC_02_AXI_ERRM_AWBURST                  )\n`ASSIGN_MARKED_DEBUG(03, PC_03_AXI_ERRM_AWLEN_LOCK               )\n`ASSIGN_MARKED_DEBUG(04, PC_04_AXI_ERRM_AWCACHE                  )\n`ASSIGN_MARKED_DEBUG(05, PC_05_AXI_ERRM_AWLEN_FIXED              )\n`ASSIGN_MARKED_DEBUG(06, PC_06_AXI_ERRM_AWLEN_WRAP               )\n`ASSIGN_MARKED_DEBUG(07, PC_07_AXI_ERRM_AWSIZE                   )\n`ASSIGN_MARKED_DEBUG(08, PC_08_AXI_ERRM_AWVALID_RESET            )\n`ASSIGN_MARKED_DEBUG(09, PC_09_AXI_ERRM_AWADDR_STABLE            )\n`ASSIGN_MARKED_DEBUG(10, PC_10_AXI_ERRM_AWBURST_STABLE           )\n`ASSIGN_MARKED_DEBUG(11, PC_11_AXI_ERRM_AWCACHE_STABLE           )\n`ASSIGN_MARKED_DEBUG(12, PC_12_AXI_ERRM_AWID_STABLE              )\n`ASSIGN_MARKED_DEBUG(13, PC_13_AXI_ERRM_AWLEN_STABLE             )\n`ASSIGN_MARKED_DEBUG(14, PC_14_AXI_ERRM_AWLOCK_STABLE            )\n`ASSIGN_MARKED_DEBUG(15, PC_15_AXI_ERRM_AWPROT_STABLE            )\n`ASSIGN_MARKED_DEBUG(16, PC_16_AXI_ERRM_AWSIZE_STABLE            )\n`ASSIGN_MARKED_DEBUG(17, PC_17_AXI_ERRM_AWQOS_STABLE             )\n`ASSIGN_MARKED_DEBUG(18, PC_18_AXI_ERRM_AWREGION_STABLE          )\n`ASSIGN_MARKED_DEBUG(19, PC_19_AXI_ERRM_AWVALID_STABLE           )\n`ASSIGN_MARKED_DEBUG(20, PC_20_AXI_RECS_AWREADY_MAX_WAIT         )\n`ASSIGN_MARKED_DEBUG(21, PC_21_AXI_ERRM_WDATA_NUM                )\n`ASSIGN_MARKED_DEBUG(22, PC_22_AXI_ERRM_WSTRB                    )\n`ASSIGN_MARKED_DEBUG(23, PC_23_AXI_ERRM_WVALID_RESET             )\n`ASSIGN_MARKED_DEBUG(24, PC_24_AXI_ERRM_WDATA_STABLE             )\n`ASSIGN_MARKED_DEBUG(25, PC_25_AXI_ERRM_WLAST_STABLE             )\n`ASSIGN_MARKED_DEBUG(26, PC_26_AXI_ERRM_WSTRB_STABLE             )\n`ASSIGN_MARKED_DEBUG(27, PC_27_AXI_ERRM_WVALID_STABLE            )\n`ASSIGN_MARKED_DEBUG(28, PC_28_AXI_RECS_WREADY_MAX_WAIT          )\n`ASSIGN_MARKED_DEBUG(29, PC_29_AXI_ERRS_BRESP_WLAST              )\n`ASSIGN_MARKED_DEBUG(30, PC_30_AXI_ERRS_BRESP_EXOKAY             )\n`ASSIGN_MARKED_DEBUG(31, PC_31_AXI_ERRS_BVALID_RESET             )\n`ASSIGN_MARKED_DEBUG(32, PC_32_AXI_ERRS_BRESP_AW                 )\n`ASSIGN_MARKED_DEBUG(33, PC_33_AXI_ERRS_BID_STABLE               )\n`ASSIGN_MARKED_DEBUG(34, PC_34_AXI_ERRS_BRESP_STABLE             )\n`ASSIGN_MARKED_DEBUG(35, PC_35_AXI_ERRS_BVALID_STABLE            )\n`ASSIGN_MARKED_DEBUG(36, PC_36_AXI_RECM_BREADY_MAX_WAIT          )\n`ASSIGN_MARKED_DEBUG(37, PC_37_AXI_ERRM_ARADDR_BOUNDARY          )\n`ASSIGN_MARKED_DEBUG(38, PC_38_AXI_ERRM_ARADDR_WRAP_ALIGN        )\n`ASSIGN_MARKED_DEBUG(39, PC_39_AXI_ERRM_ARBURST                  )\n`ASSIGN_MARKED_DEBUG(40, PC_40_AXI_ERRM_ARLEN_LOCK               )\n`ASSIGN_MARKED_DEBUG(41, PC_41_AXI_ERRM_ARCACHE                  )\n`ASSIGN_MARKED_DEBUG(42, PC_42_AXI_ERRM_ARLEN_FIXED              )\n`ASSIGN_MARKED_DEBUG(43, PC_43_AXI_ERRM_ARLEN_WRAP               )\n`ASSIGN_MARKED_DEBUG(44, PC_44_AXI_ERRM_ARSIZE                   )\n`ASSIGN_MARKED_DEBUG(45, PC_45_AXI_ERRM_ARVALID_RESET            )\n`ASSIGN_MARKED_DEBUG(46, PC_46_AXI_ERRM_ARADDR_STABLE            )\n`ASSIGN_MARKED_DEBUG(47, PC_47_AXI_ERRM_ARBURST_STABLE           )\n`ASSIGN_MARKED_DEBUG(48, PC_48_AXI_ERRM_ARCACHE_STABLE           )\n`ASSIGN_MARKED_DEBUG(49, PC_49_AXI_ERRM_ARID_STABLE              )\n`ASSIGN_MARKED_DEBUG(50, PC_50_AXI_ERRM_ARLEN_STABLE             )\n`ASSIGN_MARKED_DEBUG(51, PC_51_AXI_ERRM_ARLOCK_STABLE            )\n`ASSIGN_MARKED_DEBUG(52, PC_52_AXI_ERRM_ARPROT_STABLE            )\n`ASSIGN_MARKED_DEBUG(53, PC_53_AXI_ERRM_ARSIZE_STABLE            )\n`ASSIGN_MARKED_DEBUG(54, PC_54_AXI_ERRM_ARQOS_STABLE             )\n`ASSIGN_MARKED_DEBUG(55, PC_55_AXI_ERRM_ARREGION_STABLE          )\n`ASSIGN_MARKED_DEBUG(56, PC_56_AXI_ERRM_ARVALID_STABLE           )\n`ASSIGN_MARKED_DEBUG(57, PC_57_AXI_RECS_ARREADY_MAX_WAIT         )\n`ASSIGN_MARKED_DEBUG(58, PC_58_AXI_ERRS_RDATA_NUM                )\n`ASSIGN_MARKED_DEBUG(59, PC_59_AXI_ERRS_RID                      )\n`ASSIGN_MARKED_DEBUG(60, PC_60_AXI_ERRS_RRESP_EXOKAY             )\n`ASSIGN_MARKED_DEBUG(61, PC_61_AXI_ERRS_RVALID_RESET             )\n`ASSIGN_MARKED_DEBUG(62, PC_62_AXI_ERRS_RDATA_STABLE             )\n`ASSIGN_MARKED_DEBUG(63, PC_63_AXI_ERRS_RID_STABLE               )\n`ASSIGN_MARKED_DEBUG(64, PC_64_AXI_ERRS_RLAST_STABLE             )\n`ASSIGN_MARKED_DEBUG(65, PC_65_AXI_ERRS_RRESP_STABLE             )\n`ASSIGN_MARKED_DEBUG(66, PC_66_AXI_ERRS_RVALID_STABLE            )\n`ASSIGN_MARKED_DEBUG(67, PC_67_AXI_RECM_RREADY_MAX_WAIT          )\n`ASSIGN_MARKED_DEBUG(68, PC_68_AXI_ERRM_EXCL_ALIGN               )\n`ASSIGN_MARKED_DEBUG(69, PC_69_AXI_ERRM_EXCL_LEN                 )\n`ASSIGN_MARKED_DEBUG(70, PC_70_AXI_RECM_EXCL_MATCH               )\n`ASSIGN_MARKED_DEBUG(71, PC_71_AXI_ERRM_EXCL_MAX                 )\n`ASSIGN_MARKED_DEBUG(72, PC_72_AXI_RECM_EXCL_PAIR                )\n`ASSIGN_MARKED_DEBUG(73, PC_73_AXI_ERRM_AWUSER_STABLE            )\n`ASSIGN_MARKED_DEBUG(74, PC_74_AXI_ERRM_WUSER_STABLE             )\n`ASSIGN_MARKED_DEBUG(75, PC_75_AXI_ERRS_BUSER_STABLE             )\n`ASSIGN_MARKED_DEBUG(76, PC_76_AXI_ERRM_ARUSER_STABLE            )\n`ASSIGN_MARKED_DEBUG(77, PC_77_AXI_ERRS_RUSER_STABLE             )\n`ASSIGN_MARKED_DEBUG(78, PC_78_AXI_AUXM_RCAM_OVERFLOW            )\n`ASSIGN_MARKED_DEBUG(79, PC_79_AXI_AUXM_RCAM_UNDERFLOW           )\n`ASSIGN_MARKED_DEBUG(80, PC_80_AXI_AUXM_WCAM_OVERFLOW            )\n`ASSIGN_MARKED_DEBUG(81, PC_81_AXI_AUXM_WCAM_UNDERFLOW           )\n`ASSIGN_MARKED_DEBUG(82, PC_82_AXI_AUXM_EXCL_OVERFLOW            )\n`ASSIGN_MARKED_DEBUG(83, PC_83_AXI4LITE_ERRS_BRESP_EXOKAY        )\n`ASSIGN_MARKED_DEBUG(84, PC_84_AXI4LITE_ERRS_RRESP_EXOKAY        )\n`ASSIGN_MARKED_DEBUG(85, PC_85_AXI4LITE_AUXM_DATA_WIDTH          )\n`ASSIGN_MARKED_DEBUG(86, PC_86_XILINX_AW_SUPPORTS_NARROW_BURST   )\n`ASSIGN_MARKED_DEBUG(87, PC_87_XILINX_AR_SUPPORTS_NARROW_BURST   )\n`ASSIGN_MARKED_DEBUG(88, PC_88_XILINX_AW_SUPPORTS_NARROW_CACHE   )\n`ASSIGN_MARKED_DEBUG(89, PC_89_XILINX_AR_SUPPORTS_NARROW_CACHE   )\n`ASSIGN_MARKED_DEBUG(90, PC_90_XILINX_AW_MAX_BURST               )\n`ASSIGN_MARKED_DEBUG(91, PC_91_XILINX_AR_MAX_BURST               )\n`ASSIGN_MARKED_DEBUG(92, PC_92_XILINX_AWREADY_RESET              )\n`ASSIGN_MARKED_DEBUG(93, PC_93_XILINX_WREADY_RESET               )\n`ASSIGN_MARKED_DEBUG(94, PC_94_XILINX_BREADY_RESET               )\n`ASSIGN_MARKED_DEBUG(95, PC_95_XILINX_ARREADY_RESET              )\n`ASSIGN_MARKED_DEBUG(96, PC_96_XILINX_RREADY_RESET               )\n\n// synthesis translate_off\n`REPORTER_MACRO(00, PC_00_AXI_ERRM_AWADDR_BOUNDARY          , `ERRM_AWADDR_BOUNDARY          , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(01, PC_01_AXI_ERRM_AWADDR_WRAP_ALIGN        , `ERRM_AWADDR_WRAP_ALIGN        , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(02, PC_02_AXI_ERRM_AWBURST                  , `ERRM_AWBURST                  , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(03, PC_03_AXI_ERRM_AWLEN_LOCK               , `ERRM_AWLEN_LOCK               , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(04, PC_04_AXI_ERRM_AWCACHE                  , `ERRM_AWCACHE                  , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(05, PC_05_AXI_ERRM_AWLEN_FIXED              , `ERRM_AWLEN_FIXED              , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(06, PC_06_AXI_ERRM_AWLEN_WRAP               , `ERRM_AWLEN_WRAP               , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(07, PC_07_AXI_ERRM_AWSIZE                   , `ERRM_AWSIZE                   , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(08, PC_08_AXI_ERRM_AWVALID_RESET            , `ERRM_AWVALID_RESET            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(09, PC_09_AXI_ERRM_AWADDR_STABLE            , `ERRM_AWADDR_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(10, PC_10_AXI_ERRM_AWBURST_STABLE           , `ERRM_AWBURST_STABLE           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(11, PC_11_AXI_ERRM_AWCACHE_STABLE           , `ERRM_AWCACHE_STABLE           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(12, PC_12_AXI_ERRM_AWID_STABLE              , `ERRM_AWID_STABLE              , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(13, PC_13_AXI_ERRM_AWLEN_STABLE             , `ERRM_AWLEN_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(14, PC_14_AXI_ERRM_AWLOCK_STABLE            , `ERRM_AWLOCK_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(15, PC_15_AXI_ERRM_AWPROT_STABLE            , `ERRM_AWPROT_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(16, PC_16_AXI_ERRM_AWSIZE_STABLE            , `ERRM_AWSIZE_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(17, PC_17_AXI_ERRM_AWQOS_STABLE             , `ERRM_AWQOS_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(18, PC_18_AXI_ERRM_AWREGION_STABLE          , `ERRM_AWREGION_STABLE          , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(19, PC_19_AXI_ERRM_AWVALID_STABLE           , `ERRM_AWVALID_STABLE           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(20, PC_20_AXI_RECS_AWREADY_MAX_WAIT         , `RECS_AWREADY_MAX_WAIT         , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(21, PC_21_AXI_ERRM_WDATA_NUM                , `ERRM_WDATA_NUM                , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(22, PC_22_AXI_ERRM_WSTRB                    , `ERRM_WSTRB                    , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(23, PC_23_AXI_ERRM_WVALID_RESET             , `ERRM_WVALID_RESET             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(24, PC_24_AXI_ERRM_WDATA_STABLE             , `ERRM_WDATA_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(25, PC_25_AXI_ERRM_WLAST_STABLE             , `ERRM_WLAST_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(26, PC_26_AXI_ERRM_WSTRB_STABLE             , `ERRM_WSTRB_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(27, PC_27_AXI_ERRM_WVALID_STABLE            , `ERRM_WVALID_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(28, PC_28_AXI_RECS_WREADY_MAX_WAIT          , `RECS_WREADY_MAX_WAIT          , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(29, PC_29_AXI_ERRS_BRESP_WLAST              , `ERRS_BRESP_WLAST              , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(30, PC_30_AXI_ERRS_BRESP_EXOKAY             , `ERRS_BRESP_EXOKAY             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(31, PC_31_AXI_ERRS_BVALID_RESET             , `ERRS_BVALID_RESET             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(32, PC_32_AXI_ERRS_BRESP_AW                 , `ERRS_BRESP_AW                 , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(33, PC_33_AXI_ERRS_BID_STABLE               , `ERRS_BID_STABLE               , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(34, PC_34_AXI_ERRS_BRESP_STABLE             , `ERRS_BRESP_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(35, PC_35_AXI_ERRS_BVALID_STABLE            , `ERRS_BVALID_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(36, PC_36_AXI_RECM_BREADY_MAX_WAIT          , `RECM_BREADY_MAX_WAIT          , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(37, PC_37_AXI_ERRM_ARADDR_BOUNDARY          , `ERRM_ARADDR_BOUNDARY          , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(38, PC_38_AXI_ERRM_ARADDR_WRAP_ALIGN        , `ERRM_ARADDR_WRAP_ALIGN        , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(39, PC_39_AXI_ERRM_ARBURST                  , `ERRM_ARBURST                  , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(40, PC_40_AXI_ERRM_ARLEN_LOCK               , `ERRM_ARLEN_LOCK               , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(41, PC_41_AXI_ERRM_ARCACHE                  , `ERRM_ARCACHE                  , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(42, PC_42_AXI_ERRM_ARLEN_FIXED              , `ERRM_ARLEN_FIXED              , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(43, PC_43_AXI_ERRM_ARLEN_WRAP               , `ERRM_ARLEN_WRAP               , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(44, PC_44_AXI_ERRM_ARSIZE                   , `ERRM_ARSIZE                   , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(45, PC_45_AXI_ERRM_ARVALID_RESET            , `ERRM_ARVALID_RESET            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(46, PC_46_AXI_ERRM_ARADDR_STABLE            , `ERRM_ARADDR_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(47, PC_47_AXI_ERRM_ARBURST_STABLE           , `ERRM_ARBURST_STABLE           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(48, PC_48_AXI_ERRM_ARCACHE_STABLE           , `ERRM_ARCACHE_STABLE           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(49, PC_49_AXI_ERRM_ARID_STABLE              , `ERRM_ARID_STABLE              , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(50, PC_50_AXI_ERRM_ARLEN_STABLE             , `ERRM_ARLEN_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(51, PC_51_AXI_ERRM_ARLOCK_STABLE            , `ERRM_ARLOCK_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(52, PC_52_AXI_ERRM_ARPROT_STABLE            , `ERRM_ARPROT_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(53, PC_53_AXI_ERRM_ARSIZE_STABLE            , `ERRM_ARSIZE_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(54, PC_54_AXI_ERRM_ARQOS_STABLE             , `ERRM_ARQOS_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(55, PC_55_AXI_ERRM_ARREGION_STABLE          , `ERRM_ARREGION_STABLE          , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(56, PC_56_AXI_ERRM_ARVALID_STABLE           , `ERRM_ARVALID_STABLE           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(57, PC_57_AXI_RECS_ARREADY_MAX_WAIT         , `RECS_ARREADY_MAX_WAIT         , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(58, PC_58_AXI_ERRS_RDATA_NUM                , `ERRS_RDATA_NUM                , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(59, PC_59_AXI_ERRS_RID                      , `ERRS_RID                      , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(60, PC_60_AXI_ERRS_RRESP_EXOKAY             , `ERRS_RRESP_EXOKAY             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(61, PC_61_AXI_ERRS_RVALID_RESET             , `ERRS_RVALID_RESET             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(62, PC_62_AXI_ERRS_RDATA_STABLE             , `ERRS_RDATA_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(63, PC_63_AXI_ERRS_RID_STABLE               , `ERRS_RID_STABLE               , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(64, PC_64_AXI_ERRS_RLAST_STABLE             , `ERRS_RLAST_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(65, PC_65_AXI_ERRS_RRESP_STABLE             , `ERRS_RRESP_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(66, PC_66_AXI_ERRS_RVALID_STABLE            , `ERRS_RVALID_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(67, PC_67_AXI_RECM_RREADY_MAX_WAIT          , `RECM_RREADY_MAX_WAIT          , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(68, PC_68_AXI_ERRM_EXCL_ALIGN               , `ERRM_EXCL_ALIGN               , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(69, PC_69_AXI_ERRM_EXCL_LEN                 , `ERRM_EXCL_LEN                 , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(70, PC_70_AXI_RECM_EXCL_MATCH               , `RECM_EXCL_MATCH               , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(71, PC_71_AXI_ERRM_EXCL_MAX                 , `ERRM_EXCL_MAX                 , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(72, PC_72_AXI_RECM_EXCL_PAIR                , `RECM_EXCL_PAIR                , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(73, PC_73_AXI_ERRM_AWUSER_STABLE            , `ERRM_AWUSER_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(74, PC_74_AXI_ERRM_WUSER_STABLE             , `ERRM_WUSER_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(75, PC_75_AXI_ERRS_BUSER_STABLE             , `ERRS_BUSER_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(76, PC_76_AXI_ERRM_ARUSER_STABLE            , `ERRM_ARUSER_STABLE            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(77, PC_77_AXI_ERRS_RUSER_STABLE             , `ERRS_RUSER_STABLE             , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(78, PC_78_AXI_AUXM_RCAM_OVERFLOW            , `AUXM_RCAM_OVERFLOW            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(79, PC_79_AXI_AUXM_RCAM_UNDERFLOW           , `AUXM_RCAM_UNDERFLOW           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(80, PC_80_AXI_AUXM_WCAM_OVERFLOW            , `AUXM_WCAM_OVERFLOW            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(81, PC_81_AXI_AUXM_WCAM_UNDERFLOW           , `AUXM_WCAM_UNDERFLOW           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(82, PC_82_AXI_AUXM_EXCL_OVERFLOW            , `AUXM_EXCL_OVERFLOW            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(83, PC_83_AXI4LITE_ERRS_BRESP_EXOKAY        , `ERRS_AXI4LITE_BRESP_EXOKAY    , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(84, PC_84_AXI4LITE_ERRS_RRESP_EXOKAY        , `ERRS_AXI4LITE_RRESP_EXOKAY    , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(85, PC_85_AXI4LITE_AUXM_DATA_WIDTH          , `AUXM_AXI4LITE_DATA_WIDTH      , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(86, PC_86_XILINX_AW_SUPPORTS_NARROW_BURST   , `XILINX_AW_SUPPORTS_NARROW_BURST, C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(87, PC_87_XILINX_AR_SUPPORTS_NARROW_BURST   , `XILINX_AR_SUPPORTS_NARROW_BURST, C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(88, PC_88_XILINX_AW_SUPPORTS_NARROW_CACHE   , `XILINX_AW_SUPPORTS_NARROW_CACHE, C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(89, PC_89_XILINX_AR_SUPPORTS_NARROW_CACHE   , `XILINX_AR_SUPPORTS_NARROW_CACHE, C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(90, PC_90_XILINX_AW_MAX_BURST               , `XILINX_AW_MAX_BURST            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(91, PC_91_XILINX_AR_MAX_BURST               , `XILINX_AR_MAX_BURST            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(92, PC_92_XILINX_AWREADY_RESET              , `XILINX_AWREADY_RESET           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(93, PC_93_XILINX_WREADY_RESET               , `XILINX_WREADY_RESET            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(94, PC_94_XILINX_BREADY_RESET               , `XILINX_BREADY_RESET            , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(95, PC_95_XILINX_ARREADY_RESET              , `XILINX_ARREADY_RESET           , C_PC_MESSAGE_LEVEL)\n`REPORTER_MACRO(96, PC_96_XILINX_RREADY_RESET               , `XILINX_RREADY_RESET            , C_PC_MESSAGE_LEVEL)\n\n// synthesis translate_on\n\nendmodule\n`ifdef AXI4PC_MESSAGES\n  `undef AXI4PC_MESSAGES\n  `undef ERRM_AWADDR_BOUNDARY      \n  `undef ERRM_AWADDR_WRAP_ALIGN    \n  `undef ERRM_AWBURST              \n  `undef ERRM_AWCACHE              \n  `undef ERRM_ARCACHE              \n  `undef ERRM_AWLEN_WRAP           \n  `undef ERRM_AWSIZE               \n  `undef ERRM_AWVALID_RESET        \n  `undef ERRM_AWADDR_STABLE        \n  `undef ERRM_AWBURST_STABLE       \n  `undef ERRM_AWCACHE_STABLE       \n  `undef ERRM_AWID_STABLE          \n  `undef ERRM_AWLEN_STABLE         \n  `undef ERRM_AWLOCK_STABLE        \n  `undef ERRM_AWPROT_STABLE        \n  `undef ERRM_AWSIZE_STABLE        \n  `undef ERRM_AWQOS_STABLE         \n  `undef ERRM_AWREGION_STABLE      \n  `undef ERRM_AWVALID_STABLE       \n  `undef ERRM_AWADDR_X             \n  `undef ERRM_AWBURST_X            \n  `undef ERRM_AWCACHE_X            \n  `undef ERRM_AWID_X               \n  `undef ERRM_AWLEN_X              \n  `undef ERRM_AWLOCK_X             \n  `undef ERRM_AWPROT_X             \n  `undef ERRM_AWSIZE_X             \n  `undef ERRM_AWQOS_X              \n  `undef ERRM_AWREGION_X           \n  `undef ERRM_AWVALID_X            \n  `undef ERRS_AWREADY_X            \n  `undef ERRM_WDATA_NUM            \n  `undef ERRM_WSTRB                \n  `undef ERRM_WVALID_RESET         \n  `undef ERRM_WDATA_STABLE         \n  `undef ERRM_WLAST_STABLE         \n  `undef ERRM_WSTRB_STABLE         \n  `undef ERRM_WVALID_STABLE        \n  `undef ERRM_WDATA_X              \n  `undef ERRM_WLAST_X              \n  `undef ERRM_WSTRB_X              \n  `undef ERRM_WVALID_X             \n  `undef ERRS_WREADY_X             \n  `undef ERRS_BRESP_WLAST          \n  `undef ERRS_BRESP_ALL_DONE_EOS   \n  `undef ERRS_BRESP_EXOKAY         \n  `undef ERRS_BVALID_RESET         \n  `undef ERRS_BRESP_AW             \n  `undef ERRS_BID_STABLE           \n  `undef ERRS_BRESP_STABLE         \n  `undef ERRS_BVALID_STABLE        \n  `undef ERRM_BREADY_X             \n  `undef ERRS_BID_X                \n  `undef ERRS_BRESP_X              \n  `undef ERRS_BVALID_X             \n  `undef ERRM_ARADDR_BOUNDARY      \n  `undef ERRM_ARADDR_WRAP_ALIGN    \n  `undef ERRM_ARBURST              \n  `undef ERRM_ARLEN_FIXED          \n  `undef ERRM_AWLEN_FIXED          \n  `undef ERRM_AWLEN_LOCK           \n  `undef ERRM_ARLEN_LOCK           \n  `undef ERRM_ARLEN_WRAP           \n  `undef ERRM_ARSIZE               \n  `undef ERRM_ARVALID_RESET        \n  `undef ERRM_ARADDR_STABLE        \n  `undef ERRM_ARBURST_STABLE       \n  `undef ERRM_ARCACHE_STABLE       \n  `undef ERRM_ARID_STABLE          \n  `undef ERRM_ARLEN_STABLE         \n  `undef ERRM_ARLOCK_STABLE        \n  `undef ERRM_ARPROT_STABLE        \n  `undef ERRM_ARSIZE_STABLE        \n  `undef ERRM_ARQOS_STABLE         \n  `undef ERRM_ARREGION_STABLE      \n  `undef ERRM_ARVALID_STABLE       \n  `undef ERRM_ARADDR_X             \n  `undef ERRM_ARBURST_X            \n  `undef ERRM_ARCACHE_X            \n  `undef ERRM_ARID_X               \n  `undef ERRM_ARLEN_X              \n  `undef ERRM_ARLOCK_X             \n  `undef ERRM_ARPROT_X             \n  `undef ERRM_ARSIZE_X             \n  `undef ERRM_ARQOS_X              \n  `undef ERRM_ARREGION_X           \n  `undef ERRM_ARVALID_X            \n  `undef ERRS_ARREADY_X            \n  `undef ERRS_RDATA_NUM            \n  `undef ERRS_RLAST_ALL_DONE_EOS   \n  `undef ERRS_RID                  \n  `undef ERRS_RRESP_EXOKAY         \n  `undef ERRS_RVALID_RESET         \n  `undef ERRS_RDATA_STABLE         \n  `undef ERRS_RID_STABLE           \n  `undef ERRS_RLAST_STABLE         \n  `undef ERRS_RRESP_STABLE         \n  `undef ERRS_RVALID_STABLE        \n  `undef ERRS_RDATA_X              \n  `undef ERRM_RREADY_X             \n  `undef ERRS_RID_X                \n  `undef ERRS_RLAST_X              \n  `undef ERRS_RRESP_X              \n  `undef ERRS_RVALID_X             \n  `undef ERRL_CSYSACK_FALL         \n  `undef ERRL_CSYSACK_RISE         \n  `undef ERRL_CSYSREQ_FALL         \n  `undef ERRL_CSYSREQ_RISE         \n  `undef ERRL_CACTIVE_X            \n  `undef ERRL_CSYSACK_X            \n  `undef ERRL_CSYSREQ_X            \n  `undef ERRM_EXCL_ALIGN           \n  `undef ERRM_EXCL_LEN             \n  `undef ERRM_EXCL_MAX             \n  `undef ERRM_AWUSER_STABLE        \n  `undef ERRM_WUSER_STABLE         \n  `undef ERRS_BUSER_STABLE         \n  `undef ERRM_ARUSER_STABLE        \n  `undef ERRS_RUSER_STABLE         \n  `undef ERRM_AWUSER_X             \n  `undef ERRM_WUSER_X              \n  `undef ERRS_BUSER_X              \n  `undef ERRM_ARUSER_X             \n  `undef ERRS_RUSER_X              \n  `undef ERRM_AWUSER_TIEOFF\n  `undef ERRM_WUSER_TIEOFF\n  `undef ERRS_BUSER_TIEOFF\n  `undef ERRM_ARUSER_TIEOFF\n  `undef ERRS_RUSER_TIEOFF\n  `undef ERRM_AWID_TIEOFF \n  `undef ERRS_BID_TIEOFF \n  `undef ERRM_ARID_TIEOFF \n  `undef ERRS_RID_TIEOFF \n  `undef AUXM_DATA_WIDTH           \n  `undef AUXM_ADDR_WIDTH           \n  `undef AUXM_EXMON_WIDTH          \n  `undef AUXM_MAXRBURSTS           \n  `undef AUXM_MAXWBURSTS           \n  `undef AUXM_RCAM_OVERFLOW        \n  `undef AUXM_RCAM_UNDERFLOW       \n  `undef AUXM_WCAM_OVERFLOW        \n  `undef AUXM_WCAM_UNDERFLOW       \n  `undef AUXM_EXCL_OVERFLOW        \n  `undef RECM_EXCL_PAIR            \n  `undef RECS_AWREADY_MAX_WAIT     \n  `undef RECS_WREADY_MAX_WAIT      \n  `undef RECM_BREADY_MAX_WAIT      \n  `undef RECS_ARREADY_MAX_WAIT     \n  `undef RECM_RREADY_MAX_WAIT      \n  `undef RECM_EXCL_MATCH           \n  `undef ERRS_AXI4LITE_BRESP_EXOKAY \n  `undef ERRS_AXI4LITE_RRESP_EXOKAY \n  `undef AUXM_AXI4LITE_DATA_WIDTH\n  `undef XILINX_AW_SUPPORTS_NARROW_BURST \n  `undef XILINX_AR_SUPPORTS_NARROW_BURST \n  `undef XILINX_AW_SUPPORTS_NARROW_CACHE \n  `undef XILINX_AR_SUPPORTS_NARROW_CACHE \n  `undef XILINX_AW_MAX_BURST\n  `undef XILINX_AR_MAX_BURST\n  `undef XILINX_AWREADY_RESET\n  `undef XILINX_WREADY_RESET \n  `undef XILINX_BREADY_RESET \n  `undef XILINX_ARREADY_RESET\n  `undef XILINX_RREADY_RESET \n`endif\n\n`default_nettype wire\n\n\n// (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n\n\n`timescale 1ps/1ps\n`default_nettype none\n\n(* DowngradeIPIdentifiedWarnings=\"yes\" *)\n module axi_protocol_checker_v1_1_12_top #(\n  //Core Level Generics\n  parameter integer C_AXI_PROTOCOL                 = 0,\n  parameter integer C_AXI_ID_WIDTH                 = 1,\n  parameter integer C_AXI_DATA_WIDTH               = 32,\n  parameter integer C_AXI_ADDR_WIDTH               = 32,\n  parameter integer C_AXI_AWUSER_WIDTH             = 1,\n  parameter integer C_AXI_ARUSER_WIDTH             = 1,\n  parameter integer C_AXI_WUSER_WIDTH              = 1,\n  parameter integer C_AXI_RUSER_WIDTH              = 1,\n  parameter integer C_AXI_BUSER_WIDTH              = 1,\n  \n  parameter integer C_PC_MAXRBURSTS                = 8,\n  parameter integer C_PC_MAXWBURSTS                = 8,\n  parameter integer C_PC_EXMON_WIDTH               = 0,\n  parameter integer C_PC_AW_MAXWAITS               = 0,\n  parameter integer C_PC_AR_MAXWAITS               = 0,\n  parameter integer C_PC_W_MAXWAITS                = 0,\n  parameter integer C_PC_R_MAXWAITS                = 0,\n  parameter integer C_PC_B_MAXWAITS                = 0,\n  parameter integer C_PC_MESSAGE_LEVEL             = 2,\n  parameter integer C_PC_SUPPORTS_NARROW_BURST     = 1,\n  parameter integer C_PC_MAX_BURST_LENGTH          = 256,\n  parameter integer C_PC_HAS_SYSTEM_RESET          = 0,\n  parameter integer C_PC_STATUS_WIDTH              = 97\n) (\n  //Protocol Checker Specific Signals\n  output wire [C_PC_STATUS_WIDTH - 1:0]               pc_status,\n  output wire                                         pc_asserted,\n  \n  input wire                                          system_resetn,\n  //AXI CLK\n  input wire                                          aclk,\n  //AXI Reset\n  input wire                                          aresetn,\n  //AXI Write Address\n  input wire [C_AXI_ID_WIDTH-1:0]                     pc_axi_awid,\n  input wire [C_AXI_ADDR_WIDTH-1:0]                   pc_axi_awaddr,\n  input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]    pc_axi_awlen,\n  input wire [2:0]                                    pc_axi_awsize,\n  input wire [1:0]                                    pc_axi_awburst,\n  input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]    pc_axi_awlock,\n  input wire [3:0]                                    pc_axi_awcache,\n  input wire [2:0]                                    pc_axi_awprot,\n  input wire [3:0]                                    pc_axi_awqos,\n  input wire [3:0]                                    pc_axi_awregion,\n  input wire [C_AXI_AWUSER_WIDTH-1:0]                 pc_axi_awuser,\n  input wire                                          pc_axi_awvalid,\n  input wire                                          pc_axi_awready,\n  //AXI Write Data\n  input wire [C_AXI_ID_WIDTH-1:0]                     pc_axi_wid,\n  input wire                                          pc_axi_wlast,\n  input wire [C_AXI_DATA_WIDTH-1:0]                   pc_axi_wdata,\n  input wire [C_AXI_DATA_WIDTH/8-1:0]                 pc_axi_wstrb,\n  input wire [C_AXI_WUSER_WIDTH-1:0]                  pc_axi_wuser,\n  input wire                                          pc_axi_wvalid,\n  input wire                                          pc_axi_wready,\n  //AXI Write Response\n  input wire [C_AXI_ID_WIDTH-1:0]                     pc_axi_bid,\n  input wire [1:0]                                    pc_axi_bresp,\n  input wire [C_AXI_BUSER_WIDTH-1:0]                  pc_axi_buser,\n  input wire                                          pc_axi_bvalid,\n  input wire                                          pc_axi_bready,\n  //AXI Read Address\n  input wire [C_AXI_ID_WIDTH-1:0]                     pc_axi_arid,\n  input wire [C_AXI_ADDR_WIDTH-1:0]                   pc_axi_araddr,\n  input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]    pc_axi_arlen,\n  input wire [2:0]                                    pc_axi_arsize,\n  input wire [1:0]                                    pc_axi_arburst,\n  input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]    pc_axi_arlock,\n  input wire [3:0]                                    pc_axi_arcache,\n  input wire [2:0]                                    pc_axi_arprot,\n  input wire [3:0]                                    pc_axi_arqos,\n  input wire [3:0]                                    pc_axi_arregion,\n  input wire [C_AXI_ARUSER_WIDTH-1:0]                 pc_axi_aruser,\n  input wire                                          pc_axi_arvalid,\n  input wire                                          pc_axi_arready,\n  //AXI Read Data\n  input wire [C_AXI_ID_WIDTH-1:0]                     pc_axi_rid,\n  input wire                                          pc_axi_rlast,\n  input wire [C_AXI_DATA_WIDTH-1:0]                   pc_axi_rdata,\n  input wire [1:0]                                    pc_axi_rresp,\n  input wire [C_AXI_RUSER_WIDTH-1:0]                  pc_axi_ruser,\n  input wire                                          pc_axi_rvalid,\n  input wire                                          pc_axi_rready\n);\n\nlocalparam LP_AXI_SIZE = (C_AXI_DATA_WIDTH == 32) ? 3'b010 : 3'b011;\n\nreg                           resetn_q;\nreg  [C_AXI_ID_WIDTH-1:0]     awid_q;\nreg  [C_AXI_ADDR_WIDTH-1:0]   awaddr_q;\nreg  [7:0]                    awlen_q;\nreg  [2:0]                    awsize_q;\nreg  [1:0]                    awburst_q;\nreg  [0:0]                    awlock_q;\nreg  [3:0]                    awcache_q;\nreg  [2:0]                    awprot_q;\nreg  [3:0]                    awqos_q;\nreg  [3:0]                    awregion_q;\nreg  [C_AXI_AWUSER_WIDTH-1:0] awuser_q;\nreg                           awvalid_q;\nreg                           awready_q;\nreg                           wlast_q;\nreg  [C_AXI_DATA_WIDTH-1:0]   wdata_q;\nreg  [C_AXI_DATA_WIDTH/8-1:0] wstrb_q;\nreg  [C_AXI_WUSER_WIDTH-1:0]  wuser_q;\nreg                           wvalid_q;\nreg                           wready_q;\nreg  [C_AXI_ID_WIDTH-1:0]     bid_q;\nreg  [1:0]                    bresp_q;\nreg  [C_AXI_BUSER_WIDTH-1:0]  buser_q;\nreg                           bvalid_q;\nreg                           bready_q;\nreg  [C_AXI_ID_WIDTH-1:0]     arid_q;\nreg  [C_AXI_ADDR_WIDTH-1:0]   araddr_q;\nreg  [7:0]                    arlen_q;\nreg  [2:0]                    arsize_q;\nreg  [1:0]                    arburst_q;\nreg  [0:0]                    arlock_q;\nreg  [3:0]                    arcache_q;\nreg  [2:0]                    arprot_q;\nreg  [3:0]                    arqos_q;\nreg  [3:0]                    arregion_q;\nreg  [C_AXI_ARUSER_WIDTH-1:0] aruser_q;\nreg                           arvalid_q;\nreg                           arready_q;\nreg  [C_AXI_ID_WIDTH-1:0]     rid_q;\nreg                           rlast_q;\nreg  [C_AXI_DATA_WIDTH-1:0]   rdata_q;\nreg  [1:0]                    rresp_q;\nreg  [C_AXI_RUSER_WIDTH-1:0]  ruser_q;\nreg                           rvalid_q;\nreg                           rready_q;\nreg                           pc_asserted_i;\n\nalways @(posedge aclk) begin\n  resetn_q    <= aresetn;\n  awid_q      <= (C_AXI_PROTOCOL != 2) ? pc_axi_awid     : {C_AXI_ID_WIDTH{1'b0}};\n  awaddr_q    <= pc_axi_awaddr;\n  awlen_q     <= (C_AXI_PROTOCOL == 0) ? pc_axi_awlen : (C_AXI_PROTOCOL == 1) ? (pc_axi_awlen | 8'h00) : 8'h00;\n  awsize_q    <= (C_AXI_PROTOCOL != 2) ? pc_axi_awsize   : LP_AXI_SIZE;\n  awburst_q   <= (C_AXI_PROTOCOL != 2) ? pc_axi_awburst  : 2'b01;\n  awlock_q    <= (C_AXI_PROTOCOL != 2) ? pc_axi_awlock[0] : 1'b0;\n  awcache_q   <= (C_AXI_PROTOCOL != 2) ? pc_axi_awcache  : 4'h0;\n  awprot_q    <= pc_axi_awprot;\n  awqos_q     <= (C_AXI_PROTOCOL != 2) ? pc_axi_awqos    : 4'h0;\n  awregion_q  <= (C_AXI_PROTOCOL != 2) ? pc_axi_awregion : 4'h0;\n  awuser_q    <= (C_AXI_PROTOCOL != 2) ? pc_axi_awuser   : {C_AXI_AWUSER_WIDTH{1'b0}};\n  awvalid_q   <= pc_axi_awvalid;\n  awready_q   <= pc_axi_awready;\n  wlast_q     <= (C_AXI_PROTOCOL != 2) ? pc_axi_wlast    : 1'b1;\n  wdata_q     <= pc_axi_wdata;\n  wstrb_q     <= pc_axi_wstrb;\n  wuser_q     <= (C_AXI_PROTOCOL != 2) ? pc_axi_wuser    : {C_AXI_WUSER_WIDTH{1'b0}};\n  wvalid_q    <= pc_axi_wvalid;\n  wready_q    <= pc_axi_wready;\n  bid_q       <= (C_AXI_PROTOCOL != 2) ? pc_axi_bid      : {C_AXI_ID_WIDTH{1'b0}};\n  bresp_q     <= pc_axi_bresp;\n  buser_q     <= (C_AXI_PROTOCOL != 2) ? pc_axi_buser    : {C_AXI_BUSER_WIDTH{1'b0}};\n  bvalid_q    <= pc_axi_bvalid;\n  bready_q    <= pc_axi_bready;\n  arid_q      <= (C_AXI_PROTOCOL != 2) ? pc_axi_arid     : {C_AXI_ID_WIDTH{1'b0}};\n  araddr_q    <= pc_axi_araddr;\n  arlen_q     <= (C_AXI_PROTOCOL == 0) ? pc_axi_arlen : (C_AXI_PROTOCOL == 1) ? (pc_axi_arlen| 8'h00) : 8'h00;\n  arsize_q    <= (C_AXI_PROTOCOL != 2) ? pc_axi_arsize   : LP_AXI_SIZE;\n  arburst_q   <= (C_AXI_PROTOCOL != 2) ? pc_axi_arburst  : 2'b01;\n  arlock_q    <= (C_AXI_PROTOCOL != 2) ? pc_axi_arlock[0] : 1'b0;\n  arcache_q   <= (C_AXI_PROTOCOL != 2) ? pc_axi_arcache  : 4'h0;\n  arprot_q    <= pc_axi_arprot;\n  arqos_q     <= (C_AXI_PROTOCOL != 2) ? pc_axi_arqos    : 4'h0;\n  arregion_q  <= (C_AXI_PROTOCOL != 2) ? pc_axi_arregion : 4'h0;\n  aruser_q    <= (C_AXI_PROTOCOL != 2) ? pc_axi_aruser   : {C_AXI_ARUSER_WIDTH{1'b0}};\n  arvalid_q   <= pc_axi_arvalid;\n  arready_q   <= pc_axi_arready;\n  rid_q       <= (C_AXI_PROTOCOL != 2) ? pc_axi_rid      : {C_AXI_ID_WIDTH{1'b0}};\n  rlast_q     <= (C_AXI_PROTOCOL != 2) ? pc_axi_rlast    : 1'b1;\n  rdata_q     <= pc_axi_rdata;\n  rresp_q     <= pc_axi_rresp;\n  ruser_q     <= (C_AXI_PROTOCOL != 2) ? pc_axi_ruser    : {C_AXI_RUSER_WIDTH{1'b0}};\n  rvalid_q    <= pc_axi_rvalid;\n  rready_q    <= pc_axi_rready;\n  pc_asserted_i <= |pc_status;\nend\n\nassign pc_asserted = pc_asserted_i;\n\naxi_protocol_checker_v1_1_12_core #(\n  .C_AXI_PROTOCOL             (C_AXI_PROTOCOL),\n  .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),\n  .C_AXI_DATA_WIDTH           (C_AXI_DATA_WIDTH),\n  .C_AXI_ADDR_WIDTH           (C_AXI_ADDR_WIDTH),\n  .C_AXI_AWUSER_WIDTH         (C_AXI_AWUSER_WIDTH),\n  .C_AXI_WUSER_WIDTH          (C_AXI_WUSER_WIDTH),\n  .C_AXI_BUSER_WIDTH          (C_AXI_BUSER_WIDTH),\n  .C_AXI_ARUSER_WIDTH         (C_AXI_ARUSER_WIDTH),\n  .C_AXI_RUSER_WIDTH          (C_AXI_RUSER_WIDTH),\n  .C_PC_SUPPORTS_NARROW_BURST (C_PC_SUPPORTS_NARROW_BURST),\n  .C_PC_MAX_BURST_LENGTH      (C_PC_MAX_BURST_LENGTH),\n  .MAXRBURSTS                 (C_PC_MAXRBURSTS),\n  .MAXWBURSTS                 (C_PC_MAXWBURSTS),\n  .EXMON_WIDTH                (C_PC_EXMON_WIDTH),\n  .MAX_AW_WAITS               (C_PC_AW_MAXWAITS),\n  .MAX_AR_WAITS               (C_PC_AR_MAXWAITS),\n  .MAX_W_WAITS                (C_PC_W_MAXWAITS),\n  .MAX_R_WAITS                (C_PC_R_MAXWAITS),\n  .MAX_B_WAITS                (C_PC_B_MAXWAITS),\n  .C_PC_HAS_SYSTEM_RESET      (C_PC_HAS_SYSTEM_RESET),\n  .C_ERROR_COUNT              (C_PC_STATUS_WIDTH)\n  ) CORE (\n    .pc_status        (pc_status),\n    .resetn           (system_resetn),\n    \n    .ACLK      (aclk),\n    .ARST_N    ( resetn_q   ),\n    .AWID      ( awid_q     ),\n    .AWADDR    ( awaddr_q   ),\n    .AWLEN     ( awlen_q    ),\n    .AWSIZE    ( awsize_q   ),\n    .AWBURST   ( awburst_q  ),\n    .AWLOCK    ( awlock_q   ),\n    .AWCACHE   ( awcache_q  ),\n    .AWPROT    ( awprot_q   ),\n    .AWQOS     ( awqos_q    ),\n    .AWREGION  ( awregion_q ),\n    .AWUSER    ( awuser_q   ),\n    .AWVALID   ( awvalid_q  ),\n    .AWREADY   ( awready_q  ),\n    .WLAST     ( wlast_q    ),\n    .WDATA     ( wdata_q    ),\n    .WSTRB     ( wstrb_q    ),\n    .WUSER     ( wuser_q    ),\n    .WVALID    ( wvalid_q   ),\n    .WREADY    ( wready_q   ),\n    .BID       ( bid_q      ),\n    .BRESP     ( bresp_q    ),\n    .BUSER     ( buser_q    ),\n    .BVALID    ( bvalid_q   ),\n    .BREADY    ( bready_q   ),\n    .ARID      ( arid_q     ),\n    .ARADDR    ( araddr_q   ),\n    .ARLEN     ( arlen_q    ),\n    .ARSIZE    ( arsize_q   ),\n    .ARBURST   ( arburst_q  ),\n    .ARLOCK    ( arlock_q   ),\n    .ARCACHE   ( arcache_q  ),\n    .ARPROT    ( arprot_q   ),\n    .ARQOS     ( arqos_q    ),\n    .ARREGION  ( arregion_q ),\n    .ARUSER    ( aruser_q   ),\n    .ARVALID   ( arvalid_q  ),\n    .ARREADY   ( arready_q  ),\n    .RID       ( rid_q      ),\n    .RLAST     ( rlast_q    ),\n    .RDATA     ( rdata_q    ),\n    .RRESP     ( rresp_q    ),\n    .RUSER     ( ruser_q    ),\n    .RVALID    ( rvalid_q   ),\n    .RREADY    ( rready_q   )\n);\n\naxi_protocol_checker_v1_1_12_reporter #(\n  .C_PC_MESSAGE_LEVEL         (C_PC_MESSAGE_LEVEL),\n  .C_PC_STATUS_WIDTH          (C_PC_STATUS_WIDTH)\n) REP (\n  .aclk         (aclk),\n  .pc_status    (pc_status)\n);\n\nendmodule // axi_protocol_checker_v1_1_12_top\n\n`default_nettype wire\n\n\n", "num_lines": 4624}
{"repo_name": "s2n-tls", "repo_creator": "aws", "programming_language": "V", "code": "Require Import List.\n\nParameter string : Type.\n\nParameter empty_string : string.\n\nParameter concat : string -> string -> string.\n\n(*3 axioms about concatenation that should hold for any reasonable implementation *)\nAxiom concat_assoc : forall a b c, concat a (concat b c) = concat (concat a b) c. \nAxiom concat_empty : forall s : string, concat s empty_string = s.\nAxiom concat_empty_l : forall s : string, concat empty_string s = s.\n\n\nParameter state : Type.\n\nParameter HMAC : string -> string -> string.\n\nParameter HMAC_init : string -> state.\n\nParameter HMAC_update : string -> state -> state.\n\nParameter HMAC_digest : state -> string.\n\n(* We have proved this as stated here in SAW *)\nAxiom update_concat : forall m1 m2 s,\n    HMAC_update (concat m1 m2) s = HMAC_update m2 (HMAC_update m1 s).\n\n(* We have proved this for a set of m and k sizes in SAW *)\nAxiom equiv_one : forall m k,\n    HMAC_digest (HMAC_update m (HMAC_init k)) = HMAC k m.\n\n(* Not yet proved in SAW, can be proved as stated *)\nAxiom update_empty : forall s, HMAC_update empty_string s = s.\n\nLemma fold_right_concat : forall s l,\n    fold_right concat (s) l = concat (fold_right concat empty_string l) s.\nProof.\n  induction l.\n  simpl in *. rewrite concat_empty_l. auto.\n  simpl in *. rewrite IHl. rewrite concat_assoc. auto.\nQed.\n\nLemma update_concat_any:\n  forall (l : list string) (key s : string),\n    HMAC_update (concat (fold_right concat empty_string (rev l)) s) (HMAC_init key) =\n    HMAC_update s (fold_right HMAC_update (HMAC_init key) l).\nProof.\n  induction l; intros.\n    + simpl in *. rewrite concat_empty_l. auto.\n    + simpl in *. rewrite <- update_concat. rewrite fold_right_app.\n      simpl. rewrite fold_right_concat. simpl. rewrite concat_empty. rewrite <- IHl. f_equal.\n      rewrite concat_assoc. auto.\nQed.\n  \nTheorem HMAC_incremental_equiv :\n  forall (ms : list string) key,\n    HMAC key (fold_right concat empty_string ms) =\n    HMAC_digest (fold_left (fun (st: state) msg => HMAC_update msg st) ms (HMAC_init key)).\nProof.\n  intros.\n  rewrite <- fold_left_rev_right in *.\n  remember (rev ms).\n  destruct l; simpl.\n  - rewrite <- equiv_one. destruct ms.\n    + simpl. rewrite update_empty. auto.\n    +  assert (rev nil = rev (rev (s :: ms))). f_equal. auto.\n       clear Heql. rewrite rev_involutive in *. simpl in *. congruence.\n  - rewrite <- equiv_one. rewrite <- update_concat_any.\n    f_equal.  assert (rev (s :: l) = rev (rev ms)). f_equal. auto.\n    rewrite rev_involutive in *. subst. clear Heql. simpl.\n    rewrite fold_right_app. simpl. rewrite concat_empty. rewrite fold_right_concat. auto.\nQed.", "num_lines": 73}
{"repo_name": "s2n-tls", "repo_creator": "aws", "programming_language": "V", "code": "(* This file has been taken from https://github.com/PrincetonUniversity/VST/blob/master/hmacfcf/HMAC_spec.v *)\n(* It has been formatted to fit your repository *)\n\n(* Copyright 2012-2015 by Adam Petcher.\t\t\t\t*\n * Use of this source code is governed by the license described\t*\n * in the LICENSE file at the root of the source tree.\t\t*)\nSet Implicit Arguments.\n\n\nRequire Import Bvector.\nRequire Import List.\nRequire Import Arith.\n\nDefinition Blist := list bool.\n\nFixpoint splitVector(A : Set)(n m : nat) : Vector.t A (n + m) -> (Vector.t A n * Vector.t A m) :=\n  match n with\n    | 0 =>\n      fun (v : Vector.t A (O + m)) => (@Vector.nil A, v)\n    | S n' =>\n      fun (v : Vector.t A (S n' + m)) =>\n        let (v1, v2) := splitVector _ _ (Vector.tl v) in\n          (Vector.cons _ (Vector.hd v) _ v1, v2)\n  end.\n\nSection HMAC.\n\n  Variable c p : nat.\n  Definition b := c + p.\n\n  (* The compression function *)\n  Variable h : Bvector c -> Bvector b -> Bvector c.\n  (* The initialization vector is part of the spec of the hash function. *)\n  Variable iv : Bvector c.\n  (* The iteration of the compression function gives a keyed hash function on lists of words. *)\n  Definition h_star k (m : list (Bvector b)) :=\n    fold_left h m k.\n  (* The composition of the keyed hash function with the IV gives a hash function on lists of words. *)\n  Definition hash_words := h_star iv.\n\n  Variable Message : Set.\n  Variable splitAndPad : Message -> list (Bvector b).\n  Hypothesis splitAndPad_1_1 :\n    forall b1 b2,\n      splitAndPad b1 = splitAndPad b2 ->\n      b1 = b2.\n\n  Variable fpad : Bvector c -> Bvector p.\n  Definition app_fpad (x : Bvector c) : Bvector b :=\n    (Vector.append x (fpad x)).\n\n  Definition h_star_pad k x :=\n    app_fpad (h_star k x).\n\n  Definition GNMAC k m :=\n    let (k_Out, k_In) := splitVector c c k in\n    h k_Out (app_fpad (h_star k_In m)).\n\n  (* The \"two-key\" version of GHMAC and HMAC. *)\n  Definition GHMAC_2K (k : Bvector (b + b)) m :=\n    let (k_Out, k_In) := splitVector b b k in\n      let h_in := (hash_words (k_In :: m)) in\n        hash_words (k_Out :: (app_fpad h_in) :: nil).\n\n  Definition HMAC_2K (k : Bvector (b + b)) (m : Message) :=\n    GHMAC_2K k (splitAndPad m).\n\n  (* opad and ipad are constants defined in the HMAC spec. *)\n  Variable opad ipad : Bvector b.\n  Hypothesis opad_ne_ipad : opad <> ipad.\n\n  Definition GHMAC (k : Bvector b) :=\n    GHMAC_2K (Vector.append (BVxor _ k opad) (BVxor _ k ipad)).\n\n  Definition HMAC (k : Bvector b) :=\n    HMAC_2K (Vector.append (BVxor _ k opad) (BVxor _ k ipad)).\n\nEnd HMAC.", "num_lines": 78}
{"repo_name": "s2n-tls", "repo_creator": "aws", "programming_language": "V", "code": "Require Import List.\nImport ListNotations.\n\nRequire Import Bvector.\nRequire Import Program. (* dependent destruction *)\nRequire Import Coqlib.\n\nRequire Import Utils.\nRequire Import Bitstream.\nRequire Import Eager.\n\nRequire Import HMAC_spec.\nRequire Import HMAC_lib.\n\n\n\nFixpoint to_bvector (w : nat) (e : ext_val) : option (Bvector w) :=\n  match e,w with\n  | eseq (ebit b :: r),S n =>\n    match to_bvector n (eseq r) with\n    | Some bv => \n      Some (Vector.cons bool b n bv)\n    | _ => None\n    end\n  | eseq nil, O => Some (Vector.nil bool)\n  | _,_ => None\n  end.\n\nLemma to_bvector_succeeds :\n  forall l n,\n    has_type (eseq l) (tseq n tbit) ->\n    exists bv,\n      to_bvector n (eseq l) = Some bv.\nProof.\n  induction l; intros.\n\n  * inversion H. subst. simpl.\n    eauto.\n\n  * inversion H. subst. inversion H2.\n    subst.\n    edestruct IHl. econstructor; eauto.\n    inversion H3. subst.\n    simpl. rewrite H0.\n    eauto.\nQed.\n\n\nLemma bytestream_type :\n  forall l t,\n    Forall (fun x => has_type x t) l ->\n    has_type (eseq l) (tseq (length l) t).\nProof.\n  induction l; intros.\n  econstructor; eauto.\n  inversion H. subst.\n  econstructor; eauto.\nQed.\n\nFixpoint bv_to_extval' {w : nat} (bv : Bvector w) : list ext_val :=\n  match bv with\n  | Vector.nil => nil\n  | Vector.cons b _ r => ebit b :: bv_to_extval' r\n  end.\n  \nDefinition bv_to_extval {w : nat} (bv : Bvector w) : ext_val :=\n  let bits := bv_to_extval' bv in\n  let bytes := get_each_n 8 bits in\n  eseq (map eseq bytes).\n\n(* Bottom out with nil, maybe not a great idea but it's ok *)\nFixpoint eappend (l : list ext_val) : ext_val :=\n  match l with\n  | nil => eseq nil\n  | (eseq l0) :: r =>\n    match eappend r with\n    | eseq x => eseq (l0 ++ x)\n    | _ => eseq nil\n    end\n  | _ => eseq nil\n  end.\n\n(* eappend takes a list of sequences of the same type t to one sequence of that type t *)\nLemma eappend_type :\n  forall l t,\n    (Forall (fun x => exists n, has_type x (tseq n t)) l) ->\n    exists n,\n      has_type (eappend l) (tseq n t).\nProof.\n  induction 1; intros.\n  eexists; econstructor; eauto.\n  destruct IHForall.\n  destruct H.\n  inversion H. subst.\n  simpl.\n  inversion H1. subst.\n  eexists. econstructor.\n  eapply Forall_app.\n  split; eassumption.\nQed.\n    \nDefinition correct_model_hash {c p : nat} (hf : ext_val -> ext_val) (h : list (Bvector (b c p)) -> Bvector c) : Prop :=\n    forall l,\n      eseq (bv_to_extval' (h l)) = hf (eappend (map bv_to_extval l)).\n\n(* We need this to be true about the hash function *)\n(* HASH takes a list of chunks and produces some bits *)\n(* hf takes a stream of bytes and produces a stream of bits *)\n(* l is a list of chunks *)\n(* (map bv_to_extval l) is a list of ext_val which are all streams of bytes *)\n(* eappend (map bv_to_extval l) is a stream of bytes *)\n(* this is the correct statement of hash commuting *)\nLemma correct_hash_commutes :\n  forall {c p : nat} hf (HASH : list (Bvector (b c p)) -> Bvector c),\n    correct_model_hash hf HASH ->\n    forall l,\n      eseq (bv_to_extval' (HASH l)) = hf (eappend (map bv_to_extval l)).\nProof.\n  intros. eapply H.\nQed.\n  \nLemma split_append :\n  forall a (x : Bvector a) b (y : Bvector b),\n    splitVector a b (Vector.append x y) = (x,y).\nProof.\n  induction x; intros.\n  simpl. reflexivity.\n  simpl. rewrite IHx. reflexivity.\nQed.\n\nLemma firstn_app :\n  forall {A} (l : list A) l',\n    firstn (length l) (l ++ l') = l.\nProof.\n  induction l; intros; simpl; auto.\n  f_equal. eapply IHl.\nQed.\n\nLemma list_drop_app :\n  forall {A} (l : list A) l',\n    list_drop (length l) (l ++ l') = l'.\nProof.\n  induction l; intros; simpl; auto.\nQed.\n\nLemma list_drop_length :\n  forall {A} (l : list A) n,\n    (length (list_drop n l) <= length l)%nat.\nProof.\n  induction l; intros.\n  simpl. destruct n; simpl; omega.\n  simpl. destruct n; simpl. omega.\n  specialize (IHl n). omega.\nQed.\n\nLemma get_each_n'_fuel :\n  forall {A} n (l : list A) fuel tot,\n    (n >= length l)%nat ->\n    (fuel >= length l)%nat ->\n    tot <> O ->\n    get_each_n' fuel tot l = get_each_n' (length l) tot l.\nProof.\n  induction n; intros.\n  destruct l; simpl in *; destruct fuel; try reflexivity; omega.\n  destruct l. simpl in *.\n  destruct fuel; reflexivity.\n  assert (n >= length l)%nat by (simpl in *; omega).\n  simpl. destruct tot; try omega.\n  simpl. destruct fuel; simpl in *; try omega.\n  f_equal.\n  assert (tot = O \\/ tot <> O) by omega.\n  destruct H3. subst. simpl.\n  eapply IHn; eauto; omega.\n  assert (length (list_drop tot l) <= length l)%nat by (eapply list_drop_length; eauto).\n  erewrite IHn; try omega.\n  symmetry.\n  eapply IHn; omega.\nQed.\n    \n\nLemma get_each_n_head :\n  forall {A : Type} (l l' : list A) n,\n    n = length l ->\n    n <> O ->\n    get_each_n n (l ++ l') = [l] ++ get_each_n n l'.\nProof.\n  induction l; intros.\n  simpl in *. congruence.\n  simpl in *.\n  destruct n; inversion H.\n  assert (n = O \\/ n <> O) by omega.\n  destruct H1. subst. \n  destruct l; simpl in H1; try omega.\n  simpl. unfold get_each_n. simpl. reflexivity.\n  unfold get_each_n. simpl.\n  rewrite firstn_app.\n  rewrite list_drop_app.\n  f_equal.\n  unfold get_each_n in IHl.\n  eapply get_each_n'_fuel; eauto.\n  \n  rewrite app_length.\n  omega.\nQed.\n\n\nLemma zero_width_is_nil :\n  forall {A} (v : Vector.t A O),\n    v = []%vector.\nProof.  \n  intros.\n  dependent destruction v.\n  reflexivity.\nQed.\n\nInductive same_bits' (n : Z) : list bool -> Prop :=\n| same_bits_nil :\n    same_bits' n nil\n| same_bits_cons :\n    forall b7 b6 b5 b4 b3 b2 b1 b0 l,\n      same_bits' n l ->\n      b7 = Z.testbit n 7 ->\n      b6 = Z.testbit n 6 ->\n      b5 = Z.testbit n 5 ->\n      b4 = Z.testbit n 4 ->\n      b3 = Z.testbit n 3 ->\n      b2 = Z.testbit n 2 ->\n      b1 = Z.testbit n 1 ->\n      b0 = Z.testbit n 0 ->\n      same_bits' n (b7 :: b6 :: b5 :: b4 :: b3 :: b2 :: b1 :: b0 :: l).\n\n\nDefinition same_bits {w : nat} (n : Z) (bv : Bvector w) : Prop := same_bits' n (Vector.to_list bv).\n\nLemma vector_to_list_cons :\n  forall {A : Type} f {w : nat} (r : Vector.t A w),\n    Vector.to_list (f :: r)%vector = f :: (Vector.to_list r).\nProof.\n  simpl; auto.\nQed.\n\nLemma vector_to_list_append :\n  forall {A : Type} {w' : nat} (f : Vector.t A w') {w : nat} (r : Vector.t A w),\n    Vector.to_list (Vector.append f r)%vector = (Vector.to_list f) ++ (Vector.to_list r).\nProof.\n  induction f; intros.\n  simpl. reflexivity.\n  unfold Vector.append. fold (@Vector.append A).\n  repeat rewrite vector_to_list_cons.\n  simpl. rewrite <- IHf.\n  reflexivity.\nQed.\n  \nLemma same_bits_testbit :\n  forall {w} n b7 b6 b5 b4 b3 b2 b1 b0 (bv : Bvector w),\n    same_bits n (Vector.append [b7;b6;b5;b4;b3;b2;b1;b0]%vector bv) ->\n    b7 = Z.testbit n 7 /\\\n    b6 = Z.testbit n 6 /\\\n    b5 = Z.testbit n 5 /\\\n    b4 = Z.testbit n 4 /\\\n    b3 = Z.testbit n 3 /\\\n    b2 = Z.testbit n 2 /\\\n    b1 = Z.testbit n 1 /\\\n    b0 = Z.testbit n 0 /\\\n    same_bits n bv.\nProof.\n  intros. unfold same_bits in H.\n  rewrite vector_to_list_append in H.\n  unfold Vector.append in H.\n  simpl in H.\n  inversion H. subst.\n  repeat (split; [solve [auto] | idtac]).\n  eassumption.\nQed.\n\nLemma BVxor_cons :\n  forall n b b' v v',\n    BVxor (S n) (b :: v)%vector (b' :: v')%vector = ((xorb b b') :: (BVxor n v v'))%vector.\nProof.\n  simpl. auto.\nQed.\n\n(* This proof is ugly, but it works *)\nLemma BVxor_to_xor_const :\n  forall keylen w ekey nkey opad n,\n    has_type (eseq ekey) (bytestream keylen) ->\n    bv_to_extval nkey = eseq ekey ->\n    same_bits n opad ->\n    map eseq (get_each_n 8 (bv_to_extval' (BVxor w nkey opad))) = map (xor_const n) ekey.\nProof.\n  induction keylen; intros.\n  * unfold bytestream in H.\n    inversion H. subst. destruct ekey; simpl in H3; try congruence.\n    simpl. destruct nkey; simpl in H0; try congruence.\n    Focus 2. unfold bv_to_extval in H0. inversion H0.\n    unfold bv_to_extval'.\n    assert (BVxor 0 []%vector opad = []%vector) by (eapply zero_width_is_nil).\n    rewrite H2. simpl. reflexivity.\n\n  * inversion H.\n    destruct ekey; simpl in H3; try congruence.\n    destruct nkey.\n    unfold bv_to_extval in H0.\n    unfold bv_to_extval' in H0. simpl in H0. inversion H0.\n    inversion H4.\n    unfold bv_to_extval in H0.\n    unfold bv_to_extval' in H0.\n    fold (@bv_to_extval' n0) in H0.\n    inversion H8. subst.\n    do 9 (destruct l1; simpl in H10; try congruence).\n    clear H10.\n    repeat match goal with\n           | [ H : Forall (fun x => has_type x tbit) _ |- _ ] => inversion H; clear H\n           end;\n      repeat match goal with\n             | [ H : has_type _ tbit |- _ ] => inversion H; clear H\n             end;\n    subst.\n    \n    do 7 (destruct nkey; [ subst;\n    unfold bv_to_extval in H0;\n    unfold bv_to_extval' in H0; simpl in H0; inversion H0;\n    inversion H4 | \n                     unfold bv_to_extval in H0;\n                     unfold bv_to_extval' in H0;\n                     fold (@bv_to_extval' n0) in H0 ]).\n    remember (bv_to_extval' nkey) as extval_key.\n\n    replace ((ebit h :: ebit h0 :: ebit h1 :: ebit h2 :: ebit h3 :: ebit h4 :: ebit h5 :: ebit h6 :: extval_key)) with\n        ((ebit h :: ebit h0 :: ebit h1 :: ebit h2 :: ebit h3 :: ebit h4 :: ebit h5 :: ebit h6 :: nil) ++ extval_key) in H0 by reflexivity.\n      \n    erewrite get_each_n_head in H0 by (simpl; eauto).\n    simpl in H0.\n    inversion H0. subst.\n    clear H0.\n    inversion H3.\n    unfold length.\n\n    eapply is_seq in H9.\n    replace (tseq (length (map eseq (get_each_n 8 (bv_to_extval' nkey)))) byte) with\n        (bytestream (length (map eseq (get_each_n 8 (bv_to_extval' nkey))))) in H9 by reflexivity.\n\n    rewrite H2 in H9.\n    do 8 (dependent destruction opad).\n    replace (h :: h0 :: h1 :: h2 :: h3 :: h4 :: h5 :: h6 :: opad)%vector with\n        (Vector.append (h :: h0 :: h1 :: h2 :: h3 :: h4 :: h5 :: h6 :: [])%vector opad) in H1 by (simpl; auto).\n    eapply same_bits_testbit in H1.\n    repeat match goal with\n           | [ H : _ /\\ _ |- _ ] => destruct H\n           end.\n    \n    eapply IHkeylen in H9;\n      [ idtac |\n        unfold bv_to_extval; reflexivity\n        | eassumption ].\n    \n    repeat rewrite BVxor_cons.\n    unfold bv_to_extval'.\n    fold (@bv_to_extval' n0).\n    replace (ebit (xorb b6 h)\n        :: ebit (xorb b5 h0)\n           :: ebit (xorb b4 h1)\n              :: ebit (xorb b3 h2)\n                 :: ebit (xorb b2 h3)\n                 :: ebit (xorb b1 h4) :: ebit (xorb b0 h5) :: ebit (xorb b h6) :: bv_to_extval' (BVxor n0 nkey opad)) with\n        ((ebit (xorb b6 h)\n        :: ebit (xorb b5 h0)\n           :: ebit (xorb b4 h1)\n              :: ebit (xorb b3 h2)\n                 :: ebit (xorb b2 h3)\n                 :: ebit (xorb b1 h4) :: ebit (xorb b0 h5) :: ebit (xorb b h6) :: nil) ++ bv_to_extval' (BVxor n0 nkey opad)) by (simpl; auto).\n    \n    erewrite get_each_n_head by (simpl; auto).\n    unfold app.\n    repeat rewrite map_cons.\n    erewrite <- H9.\n    f_equal.\n\n    unfold xor_const.\n    unfold xor_const_list.\n    unfold length.\n    f_equal.\n    subst. reflexivity.\nQed.\n\n\nLemma eappend_eseq_append :\n  forall l1 l2,\n    eseq (l1 ++ l2) = eappend ((eseq l1)::(eseq l2)::nil).\nProof.\n  intros. simpl. rewrite app_nil_r. reflexivity.\nQed.\n\nLemma eseq_eq :\n  forall x y a b,\n    x = y ->\n    eseq a = eseq b ->\n    eseq (x ++ a) = eseq (y ++ b).\nProof.\n  intros. inversion H0. congruence.\nQed.\n\n\nLemma bv_to_extval'_append :\n  forall {w w'} (x : Bvector w) (y : Bvector w'),\n    bv_to_extval' (Vector.append x y) = (bv_to_extval' x) ++ (bv_to_extval' y).\nProof.\n  induction x; intros.\n  simpl; auto.\n  simpl. f_equal. auto.\nQed.\n\nLemma eseq_backwards :\n  forall x y,\n    eseq x = eseq y ->\n    x = y.\nProof.\n  intros. inversion H. auto.\nQed.\n\nLemma eappend_map_eseq :\n  forall {A} f (l : list A),\n    eappend (map (fun x => eseq (f x)) l) = eseq (concat (map f l)).\nProof.\n  induction l; intros.\n  simpl. reflexivity.\n  simpl. rewrite IHl. reflexivity.\nQed.\n\nTheorem HMAC_equiv (MSGT : Set) :\n  forall keylen msglen key msg,\n    has_type key (bytestream keylen) ->\n    has_type msg (bytestream msglen) ->\n    forall c p hf res HashBlock iv (splitAndPad : MSGT -> list (Bvector (b c p))),\n      hmac_model hf key msg = Some res ->\n      @correct_model_hash c p hf (h_star p HashBlock iv) ->\n      forall nmsg nkey,\n        eappend (map bv_to_extval (splitAndPad nmsg)) = msg ->\n        bv_to_extval nkey = key ->\n        forall opad ipad,\n          same_bits 92 opad ->\n          same_bits 54 ipad ->\n          forall fpad,\n            (forall x, bv_to_extval' (app_fpad fpad (h_star p HashBlock iv x)) = bv_to_extval' (h_star p HashBlock iv x)) ->\n            eseq (bv_to_extval' (@HMAC c p HashBlock iv MSGT splitAndPad fpad opad ipad nkey nmsg)) = res.\nProof.\n  intros.\n  unfold HMAC.\n  unfold HMAC_2K.\n  unfold GHMAC_2K.\n  unfold hash_words.\n  rewrite split_append.\n  simpl. \n  unfold hmac_model in H1.\n  destruct key; simpl in *; try congruence.\n  destruct msg; simpl in *; try congruence.\n  destruct (hf (eseq (map (fun x : ext_val => xor_const 54 x) l ++ l0))) eqn:?; try congruence.\n  inversion H1.\n\n  match goal with\n  | [ |- eseq (bv_to_extval' (HashBlock (HashBlock iv ?V1) ?V2)) = _ ] =>\n    replace (HashBlock (HashBlock iv V1) V2) with (h_star p HashBlock iv (V1 :: V2 :: nil)) by (unfold h_star; simpl; reflexivity)\n  end.\n  match goal with\n  | [ |- context[(h_star p HashBlock (HashBlock iv ?V1) ?V2)] ] =>\n    replace (h_star p HashBlock (HashBlock iv V1) V2) with (h_star p HashBlock iv (V1 :: V2)) by (simpl; reflexivity)\n  end.\n  remember (h_star p HashBlock iv) as HASH.\n\n  rename l into ekey.\n  rename l0 into emsg.\n\n  erewrite correct_hash_commutes by eassumption.\n  \n  f_equal. simpl.\n  f_equal.\n  f_equal.\n  eapply BVxor_to_xor_const; eauto.\n\n  rewrite app_nil_r.\n  unfold Pos.to_nat in *.\n  simpl in *.\n\n  (* l1 is a list of bits *)\n  (* bv_to_extval' returns a list of bits *)\n  (* at this point the types work out *)\n  f_equal. f_equal.\n\n  remember (splitAndPad nmsg) as msgl.\n\n  rewrite H7.\n\n  eapply eseq_backwards.\n  erewrite correct_hash_commutes by eassumption.\n  rewrite <- Heqe.\n  f_equal.\n\n  (* types still good here *)\n  simpl.\n  unfold bv_to_extval.\n  erewrite eappend_map_eseq.\n  f_equal.\n  f_equal.\n\n  eapply BVxor_to_xor_const; eauto.\n\n\n  eapply eseq_backwards.\n  erewrite <- H3.\n  unfold bv_to_extval.\n  erewrite <- eappend_map_eseq.\n\n  reflexivity.\nQed.\n\n", "num_lines": 516}
{"repo_name": "s2n-tls", "repo_creator": "aws", "programming_language": "V", "code": "Require Import List.\nImport ListNotations.\nRequire Import String.\n\n(* Borrow from CompCert *)\nRequire Import Coqlib.\nRequire Import Bitvectors.\n\nRequire Import AST.\nRequire Import Semantics.\nRequire Import Utils.\nRequire Import Builtins.\nRequire Import BuiltinSem.\nRequire Import BuiltinSyntax.\nRequire Import Values.        \nRequire Import Eager.\nRequire Import Bitstream.\n\nRequire Import EvalTac.\n\nImport HaskellListNotations.\nOpen Scope string.\n\nRequire Import HMAC.\n\nRequire Import HMAC_spec.\n\nRequire Import HMAC_lib.\n\nRequire Import Kinit_eval.\n\n\n(* lemma for when the length of the key is the same as the length of the block *)\nLemma Hmac_eval_keylen_is_blocklength :\n  forall (key : ext_val) keylen,\n    has_type key (bytestream keylen) -> \n    forall GE TE SE, \n      wf_env ge GE TE SE ->\n      (forall id, In id [(371, \"ks\");(372, \"okey\");(373, \"ikey\");(374, \"internal\")] -> GE id = None) ->\n      forall h hf,\n        good_hash h GE TE SE hf ->\n        forall msg msglen unused,\n          has_type msg (bytestream msglen) ->\n          exists v,\n            eager_eval_expr GE TE SE (apply (tapply (EVar hmac) ((typenum (Z.of_nat msglen)) :: (typenum (Z.of_nat keylen)) :: (typenum unused) :: (typenum (Z.of_nat keylen)) :: nil)) (h :: h :: h :: (EValue (to_val key)) :: (EValue (to_val msg)) :: nil)) (to_sval v) /\\ hmac_model hf key msg = Some v.\nProof.\n  intros.\n  rename H1 into HIDs.\n  rename H2 into H1.\n  rename H3 into H2.\n  init_globals ge.\n  abstract_globals ge.\n  edestruct good_hash_complete_eval; eauto.\n  do 4 destruct H3.\n\n  inversion H. subst.\n  inversion H2. subst.\n  remember (hf (eseq (map (fun x3 : ext_val => xor_const 54 x3) l ++ l0))) as hv1.\n  assert (HT : exists n, has_type hv1 (tseq n tbit)). {\n    assert (exists n, has_type (eseq (map (fun x3 : ext_val => xor_const 54 x3) l ++ l0)) (bytestream n)). {\n      eexists. econstructor.\n      rewrite Forall_app. split.\n      eapply Forall_map. eauto.\n      intros. eapply xor_const_byte; eauto.\n      eauto.\n    }\n    destruct H5.\n    eapply H4 in H5. destruct H5. subst hv1. eauto.\n  }\n  destruct HT as [n0'].\n  rename H5 into HT.\n  edestruct ext_val_list_of_strictval; try eassumption.\n  rename H5 into Hlres.\n  \n  \n  eexists; split.\n\n  e. e. e. e. e. e. e. e. e.\n  ag.\n\n  e. e. e. e. e.\n  eassumption.\n  e. eassumption.\n  e. eassumption.\n  e. e.\n\n  eapply strict_eval_val_to_val.\n\n  e. e.\n  eapply strict_eval_val_to_val.\n\n  e. e. e. e. e. e. e. e.\n  g. simpl. unfold extend. simpl.\n  eapply wf_env_not_local; eauto.\n  reflexivity.\n\n  e.\n  e. e. e.\n  eapply eager_eval_global_var.\n  reflexivity.\n  reflexivity.\n  e. e. e. eapply eager_eval_global_var.\n  reflexivity.\n  reflexivity.\n\n  \n  eapply kinit_eval.\n\n  unfold bind_decl_groups.\n  unfold erase_decl_groups.\n\n  repeat eapply wf_env_extend_TE.\n  repeat eapply wf_env_erase_SE.\n  repeat eapply wf_env_extend_SE.\n  repeat eapply wf_env_extend_GE.\n  eassumption.\n\n  reflexivity.\n  reflexivity.\n  reflexivity.\n  reflexivity.\n  reflexivity.\n  reflexivity.\n  reflexivity.\n  reflexivity.\n  reflexivity.\n  reflexivity.\n  reflexivity.\n  reflexivity.\n  reflexivity.\n\n  exact H.\n\n\n  eapply good_hash_same_eval; eauto.\n  e. \n\n  repeat e. repeat e.\n  repeat e. e.\n  \n  simpl.\n  rewrite list_of_strictval_of_strictlist. \n  reflexivity.\n  \n  (* Begin model section *)\n  eapply eager_eval_bind_senvs. eassumption.\n  instantiate (1 := fun x => to_sval (xor_const 92 x)).  \n  intros. e. e. e. g. unfold extend. simpl.\n  eapply wf_env_not_local; eauto. reflexivity.\n  e. e. e. e. e. e. g.\n  unfold extend. simpl.\n  eapply wf_env_not_local; eauto. reflexivity.\n  e. repeat e. repeat e. e. repeat e.\n  repeat e. simpl.\n  inversion H5. subst. simpl.\n  unfold strictnum.\n  unfold Z.to_nat. unfold Pos.to_nat.\n  unfold Pos.iter_op. unfold Init.Nat.add.\n  rewrite <- H6.\n  rewrite xor_num. reflexivity.\n  rewrite H6. eassumption.\n  reflexivity.\n  (* End model section *)\n\n  e. g.\n  e. e. e. e. g.\n  simpl. unfold extend. simpl. eapply wf_env_not_local; eauto.\n  reflexivity.\n  e. e. e. e. e. e. e. e. e. e. e. g.\n  simpl. unfold extend. simpl. eapply wf_env_not_local; eauto.\n  reflexivity.\n  e. e. e. e. g.\n  e. e. e. g.\n  eapply kinit_eval.\n\n  unfold bind_decl_groups.\n  unfold erase_decl_groups.\n  repeat eapply wf_env_extend_GE.\n  repeat eapply wf_env_extend_TE.\n  repeat eapply wf_env_erase_SE.\n  repeat eapply wf_env_extend_SE.\n  assumption.\n\n  all: try solve [reflexivity].\n\n  exact H.\n  \n  solve [eapply good_hash_same_eval; eauto; e].\n\n  repeat e.\n  repeat e. repeat e. e.\n\n  simpl.\n  rewrite list_of_strictval_of_strictlist. \n  reflexivity.\n\n\n  eapply eager_eval_bind_senvs. eassumption.\n  instantiate (1 := fun x => to_sval (xor_const 54 x)).  \n  intros. e. e. e. g. unfold extend. simpl.\n  eapply wf_env_not_local; eauto. reflexivity.\n  e. e. e. e. e. e. g.\n  unfold extend. simpl.\n  eapply wf_env_not_local; eauto. reflexivity.\n  e. repeat e. repeat e. e. repeat e.\n  repeat e. simpl.\n  inversion H5. subst. simpl.\n  unfold strictnum.\n  unfold Z.to_nat. unfold Pos.to_nat.\n  unfold Pos.iter_op. unfold Init.Nat.add.\n  rewrite <- H6.\n  rewrite xor_num. reflexivity.\n  rewrite H6. eassumption.\n  reflexivity.\n\n  e. e. e. repeat e.\n  repeat e.\n  \n  unfold to_sval. fold to_sval.\n  rewrite append_strict_list. \n  reflexivity.\n\n  eapply global_extends_eager_eval.\n\n  replace (map (fun x3 : ext_val => to_sval (xor_const 54 x3)) l) with\n      (map to_sval (map (fun x3 => xor_const 54 x3) l)) by (rewrite list_map_compose; reflexivity).\n  rewrite <- list_append_map.\n  remember (app (map (fun x3 : ext_val => xor_const 54 x3) l) l0) as ll.\n  replace (strict_list (map to_sval ll)) with (to_sval (eseq ll)) by (reflexivity).\n  subst ll.\n  eapply H4.\n  econstructor.\n\n  rewrite Forall_app. split; auto.\n  eapply Forall_map. eassumption.\n\n  intros. eapply xor_const_byte; eauto.\n\n  unfold bind_decl_groups.\n  unfold bind_decl_group.\n  unfold declare.\n  \n  repeat (eapply global_extends_extend_r; try eapply wf_env_name_irrel_GE; eauto).\n  eapply global_extends_refl.\n\n  eapply HIDs. simpl. left. reflexivity.\n  eapply HIDs. simpl. right. left. reflexivity.\n  eapply HIDs. simpl. right. right. left. reflexivity.\n  eapply HIDs. simpl. right. right. right. left. reflexivity.\n  \n  e. repeat e.\n  e. e. e.\n\n  simpl.\n  rewrite <- Heqhv1.\n  rewrite Hlres. reflexivity.\n  \n  e. repeat e. repeat e.\n\n  rewrite append_strict_list. reflexivity.\n  eapply global_extends_eager_eval.\n\n  (* get to_sval out to outside *)\n  (* evaluate the hash function *)\n\n  replace (map (fun x4 : ext_val => to_sval (xor_const 92 x4)) l) with\n  (map to_sval (map (xor_const 92) l)) by\n      (clear -l; \n       induction l; simpl; auto; f_equal; eapply IHl; eauto).\n    \n  rewrite get_each_n_map_commutes.\n\n\n  rewrite map_strict_list_map_map_to_sval.\n  rewrite <- list_append_map.\n  rewrite strict_list_map_to_sval.\n\n  (* This one will be some fun *)\n  assert (exists n, has_type (eseq (map (xor_const 92) l ++ map eseq (get_each_n (Pos.to_nat 8) x3))) (bytestream n)). {\n\n\n    eapply has_type_seq_append.\n    exists (Datatypes.length (map (xor_const 92) l)).\n    econstructor.\n    eapply Forall_map. eassumption.\n    intros. eapply xor_const_byte; eauto.\n    subst hv1.\n    inversion HT. subst.\n    rewrite <- H5 in Hlres.\n    eapply list_of_strictval_to_sval in Hlres. inversion Hlres.\n    subst. clear Hlres.\n    remember H1 as HHash.\n    clear HeqHHash.\n    symmetry in H5.\n    eapply good_hash_fully_padded in H1; try eassumption.\n    eapply type_stream_of_bytes in H1; eauto.\n  }\n  \n  destruct H5.\n  eapply H4 in H5. destruct H5. eapply H5.\n\n  repeat (eapply global_extends_extend_r; try eapply wf_env_name_irrel_GE; eauto).\n  eapply global_extends_refl.\n\n  eapply HIDs. simpl. left. reflexivity.\n  eapply HIDs. simpl. right. left. reflexivity.\n  eapply HIDs. simpl. right. right. left. reflexivity.\n  eapply HIDs. simpl. right. right. right. left. reflexivity.\n\n  (* our result matches the model *)\n  subst hv1.\n  eapply list_of_strictval_to_sval in Hlres.\n  simpl. rewrite Hlres.\n\n  reflexivity.\n\n  Unshelve.\n  all: exact id.\n  \nQed.\n", "num_lines": 321}
{"repo_name": "s2n-tls", "repo_creator": "aws", "programming_language": "V", "code": "Require Import List.\nImport ListNotations.\nRequire Import String.\n\n(* Borrow from CompCert *)\nRequire Import Coqlib.\nRequire Import Bitvectors.\n\nRequire Import AST.\nRequire Import Semantics.\nRequire Import Utils.\nRequire Import Builtins.\nRequire Import BuiltinSem.\nRequire Import BuiltinSyntax.\nRequire Import Values.        \nRequire Import Eager.\nRequire Import Bitstream.\n\nRequire Import EvalTac.\n\nImport HaskellListNotations.\nOpen Scope string.\n\nRequire Import HMAC.\n\nRequire Import HMAC_spec.\n\nRequire Import HMAC_lib.\n\n\nLemma kinit_eval :\n  forall GE TE SE,\n    wf_env ge GE TE SE ->\n    forall (key : ext_val) keylen,\n      has_type key (bytestream keylen) ->\n      forall h hf,\n        good_hash h GE TE SE hf ->\n        forall digest t1 t2 t3 kexpr,\n          eager_eval_type GE TE t1 (tnum (Z.of_nat keylen)) ->\n          eager_eval_type GE TE t2 (tnum (Z.of_nat keylen)) ->\n          eager_eval_type GE TE t3 (tnum digest) ->\n          eager_eval_expr GE TE SE kexpr (to_sval key) ->\n          eager_eval_expr GE TE SE (apply (tapply (EVar kinit) (ETyp t1 :: ETyp t2 :: ETyp t3 ::  nil)) (h :: kexpr :: nil)) (to_sval key).\nProof.\n  intros.\n  eapply good_hash_eval in H1. do 4 destruct H1.\n  init_globals ge.\n  abstract_globals ge.\n\n  unfold bytestream in H0. inversion H0. subst.\n\n  e. e. e. e. e. ag.\n  e. e. e. e.\n  eassumption.\n  e. eassumption.\n  e. e. e. e.\n\n  g. unfold extend. simpl.\n  eapply wf_env_not_local; eauto; reflexivity.\n  e. e. e. e. \n  g. unfold extend. simpl.\n  eapply wf_env_not_local; eauto; reflexivity.\n\n  e. e. e. repeat e. repeat e. reflexivity.\n  e. e. e. \n\n  g. unfold extend. simpl.\n  eapply wf_env_not_local; eauto; reflexivity.\n\n  e. e. e. repeat e.\n  repeat e. reflexivity.\n  e. repeat e. repeat e.\n  simpl. unfold strictnum.\n\n  rewrite gt_not_refl; reflexivity.\n  simpl.\n\n  e. e. e. e.\n\n  g. unfold extend. simpl.\n  eapply wf_env_not_local; eauto; reflexivity.\n  eapply wf_env_global; eauto. reflexivity.\n  e. e. e. e. e. e. e. e. e.\n  g. unfold extend. simpl.\n  eapply wf_env_not_local; eauto; reflexivity.\n\n  e. e. e. e. e. e. e. \n  g. unfold extend. simpl.\n  eapply wf_env_not_local; eauto; reflexivity.\n\n  e. e. repeat e.\n  repeat e.\n  reflexivity.\n\n  e. repeat e. repeat e. \n\n  \n  unfold to_sval. fold to_sval.\n  rewrite append_strict_list. \n  reflexivity.\n\n  e. g. e. g. e. e. e. e.\n  g. unfold extend. simpl.\n  eapply wf_env_not_local; eauto; reflexivity.\n\n  e. e. e. e. e. e. repeat e.\n  repeat e.\n\n  erewrite <- map_length.\n  rewrite splitAt_len. reflexivity.  \n\n  simpl. reflexivity.\nQed.\n\n", "num_lines": 115}